Semiconductor storage device precharging/discharging bit line to read data from memory cell

A read circuit includes a precharge circuit, a discharge circuit, and a sense amplifier. The precharge circuit includes a first transistor which has a gate connected to the bit line, a second transistor which has a gate connected to the bit line, the second transistor having a current path one end of which is connected to one end of a current path in the first transistor, a third transistor which has a current path one end of which is connected to the other end of the current path in the first transistor, the other end of the current path in the third transistor being connected to a power supply, and a fourth transistor which has a gate connected to a junction between the current paths in the first and second transistors and which controls a charge level of the bit line.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-300666, filed Oct. 14, 2004, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor storage device that precharges/discharges a bit line to read data from a memory cell.

2. Description of the Related Art

As described in, for example, PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003, R. MICHELONI et al. “The Flash Memory Read Path: Building Blocks and Critical Aspects” pp. 537-553 (see FIG. 6(a)), in a read operation performed by a semiconductor storage device such as a flash memory, a power supply VDDfirst passes a current through a bit line via a resistor R. Then, the bit line is precharged to a predetermined level. On this occasion, when a memory cell (cell transistor) is on, the bit line is discharged. Accordingly, a sense amplifier senses the level of a node OUT to determine that the memory cell is on. On the other hand, when the memory cell is off, the level of the precharged bit line and node OUT is retained. Thus, the sense amplifier senses the level to determine that the memory cell is off.

With this read system, the precharge level of the bit line is adjusted by controlling a bias voltage BIAS applied to a gate of a MOS transistor M1. If the bias voltage BIAS is at the level of the power supply voltage VDD, the bit line is clamped to a level VDD-Vth (a threshold voltage of the MOS transistor M1). If the charge level of the bit line is excessively high, when the bit line has a large capacitance and the memory cell has only a small current, a long time is required to discharge the memory cell in the on state to a determination level. Further, to input a level equal to or lower than the power supply voltage VDDas the bias voltage BIAS to reduce the charge level of the bit line, a circuit is required which generates a bias voltage equal to or lower than VDD.

FIG. 7(b) in the above article describes, as another read circuit, a circuit in which an inverter carries out negative feedback to suppress excessive charging of the bit line. When a node A2is at ground potential GND, the bias voltage BIAS supplied to the gate of the MOS transistor M1is set at the VDDlevel to rapidly charge the bit line. Once the bit line is sufficiently precharged to, for example, about VDD/2, an output from the inverter is inverted to perform control such that the MOS transistor M1is turned off. This makes it possible to suppress the excessive charging of the bit line.

This circuit configuration eliminates the need to apply a special voltage to the gate of the MOS transistor M1. Further, the level of the bit line is sensed so that the inverter can control the MOS transistor M1. Consequently, the circuit is simple.

However, since the inverter controls the precharge level of the bit line, a drain of the MOS transistor M1has a voltage equal to or higher than the bit line voltage and equal to or lower than the power supply voltage VDD. Accordingly, after precharging, the charge on the drain of the MOS transistor M1migrates to the bit line. As a result, the bit line is continuously charged weakly. This charging does not affect reading from the memory cell in an off state. However, when the bit line is discharged with the memory cell in the on state, the output from the inverter changes so that the MOS transistor M1is turned on. Consequently, the charge on the drain of the MOS transistor M1further charges the bit line. This operation charges the bit line being discharged by the memory cell in the on state. This is a factor delaying the operation of reading from the memory cell in the on state.

Further, the inverter need not operate for practical use while the bit line is being discharged. However, an input to the inverter is at an intermediate level between 0 V and VDDafter the end of the read operation and before the potential across the bit line is reset to ground potential GND. Thus, during the read operation, the inverter continues to pass a through current. The through current is useless current consumption that is not related to operations.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the present invention, there is provided a semiconductor storage device comprising a precharge circuit configured to precharge a bit line connected to a selected memory cell for a read operation, the precharge circuit including a first MOS transistor of a first conductivity type which has a gate connected to the bit line, a second MOS transistor of a second conductivity type which has a gate connected to the bit line, the second MOS transistor having a current path one end of which is connected to one end of a current path in the first MOS transistor, a third MOS transistor of the first conductivity type which has a current path one end of which is connected to the other end of the current path in the first MOS transistor, the other end of the current path in the third MOS transistor being connected to a power supply, and a fourth MOS transistor of the second conductivity type which has a gate connected to a junction between the current paths in the first and second MOS transistors and which controls a charge level of the bit line; a discharge circuit configured to discharge the bit line using a current flowing through the selected memory cell; and a sense amplifier configured to sense a voltage across the bit line.

According to another aspect of the present invention, there is provided a semiconductor storage device comprising a precharge circuit configured to precharge a bit line connected to a selected memory cell for a read operation, the precharge circuit including a first MOS transistor of a first conductivity type which has a gate connected to a read global bit line, a second MOS transistor of a second conductivity type which has a gate connected to the read global bit line, the second MOS transistor having a current path one end of which is connected to one end of a current path in the first MOS transistor, a third MOS transistor of the first conductivity type which has a current path one end of which is connected to the other end of the current path in the first MOS transistor, the other end of the current path in the third MOS transistor being connected to a power supply, the third MOS transistor having a gate to which a precharge signal is supplied, a fourth MOS transistor of the second conductivity type which has a gate connected to a junction between the current paths in the first and second MOS transistors and which has a current path one end of which is connected to one end of the bit line, the fourth MOS transistor controlling a charge level of the bit line, and a fifth MOS transistor of the second conductivity type which has a current path one end of which is connected to the other end of the bit line, the other end of the current path in the fifth MOS transistor being connected to one end of the read global bit line, the fifth MOS transistor having a gate to which a separation signal is supplied; a discharge circuit configured to discharge the bit line using a current flowing through the selected memory cell; and a sense amplifier configured to sense a voltage across the bit line.

DETAILED DESCRIPTION OF THE INVENTION

With reference toFIG. 1, description will be given of a semiconductor storage device according to a first embodiment of the present invention.FIG. 1is a block diagram of a system LSI according to the present invention.

As shown in the figure, a system LSI1comprises CPU2and a 2Tr flash memory3. The CPU2transmits and receives data to and from the flash memory3. The flash memory3comprises a memory cell array10, a write decoder20, a select gate decoder30, a column decoder40, a write selector50, a write circuit60, a read circuit70, a read control circuit80, a source line driver90, a switch group100, an address buffer110, a write state machine120, and a voltage generator130. The LSI1is supplied with an external voltage Vcc1(up to 3 V) that is provided to the voltage generator130, the write circuit60, and the write selector50.

FIG. 2shows a specific example of a plan view (floor plan) of the memory cell array10and its periphery extracted from the system LSI shown inFIG. 1. The memory cell array10is divided into two planes, plane010-0and plane110-1. The write decoder20is placed between the plane10-0and10-1. Further, select gate decoders30-0and30-1are arranged on the respective sides of the set of planes10-0and10-1.

Read circuits (read column selectors)70-0and70-1and sense amplifiers (S/A)74-0and74-1are provided in association with the planes10-0and10-1, respectively. Column decoders (read column decoders RCD)40-0and40-1are arranged in association with the select gate decoders30-0and30-1, respectively.

replica sense amplifier amplifiers (replica S/A0and replica S/A1) and a reference cell array (ref. cell array) are arranged in the region between the sense amplifiers (S/A)74-0and74-1. The reference cell array is shared by the two planes10-0and10-1. Each of the reference cells in the reference cell array is provided for one corresponding block. In other words, one reference cell is provided for each replica sense amplifier. Signal /PRE cnt0enables the reference cells to discharge the Replica RGBL and LBL in the plane10-0(plane0) and Signal/PRE cntl enables the reference cells to discharge the Replica RGBL and LBL in the plane10-1(plane1). The gate voltage of the reference cells is the same for the two planes10-0and10-1. The reference cells are connected to transistors with gates to which power supply voltage VCC3is applied.

The memory cell array (planes10-0and10-1) has a plurality of memory cells arranged in a matrix. The configuration of the memory cell array10will be described with reference toFIG. 3.FIG. 3is a circuit diagram of a particular region of the plane10-0or10-1.

As shown in the figure, each of the planes10-0and10-1comprises a prime cell array PCA and a replica cell array RCA.

The prime cell array PCA has ((m+1)×(n+1); m and n are natural numbers) memory cell blocks BLK and a first column selector WCS and a second column selector RCS provided for each of the memory cell blocks BLK. The replica cell array RCA has ((m+1)×1) memory cell blocks BLK and the first column selector WCS and second column selector RCS provided for each of the memory cell blocks BLK. InFIG. 3, the number of columns in each of the memory cell blocks included in the replica cell array RCA is 1. However, this is only an example and a plurality of columns may be provided.

Each memory cell block BLK includes a plurality of memory cells MC. The memory cells MC are of a 2Tr flash memory. That is, each memory cell MC has a memory transistor MT and a select transistor ST. A source of the memory cell transistor MT is connected to a drain of the select transistor ST. The memory cell transistor MT comprises a stacked gate structure having a floating gate formed on a semiconductor substrate via a gate insulating film and a control gate structure formed on the floating gate via a gate insulating film. Memory cells MC adjacent to each other across the columns share a drain region of the memory cell transistor MT or a source region of the select transistor ST. Each memory cell block BLK includes (4×4) memory cells (MC). InFIG. 3, four memory cells MC are arranged across the columns. However, this is only an example, and for example, 8 or 16 memory cells MC may be provided in this direction. The number of memory cells is not limited. A drain region of each of the memory cell transistors MT in the four memory cells MC is connected to the corresponding one of four local bit lines LBL0to LBL3. One end of each of the local bit lines LBL0to LBL3is connected to the first column selector WCS. The other end local bit line is connected to the second column selector RCS. The memory cells MC in the prime cell array PCA are used to actually store data. On the other hand, the memory cells MC in the replica cell array RCA are not used to store data but to control operations of reading data from the prime cell array PCA. In the description below, to distinguish the memory cells in the prime cell array PCA from those in the replica cell array RCA, the former will be called prime cells PC and the latter will be called replica cells RC.

In each of the planes10-0and10-1, the control gates of all the memory cell transistors MT on the same row are connected to one of word lines WL0to WL(4m−1). Each of the local bit lines LBL0to LBL3connects the memory cell transistors only in the corresponding memory cell block BLK. However, the word line WL connects the memory cell transistors in all the memory cell blocks on the same row. Moreover, the word line WL connects the memory cell transistors in the prime cell array PCA and replica cell array RCA.

In the prime cell array PCA, the gates of the select transistors ST on the same row are connected to one of select gate lines SG0to SG(4m−1). Each select gate line connects the gates of all the select transistors on the same row in all the memory cell blocks BLK. Moreover, in the replica cell array RCA, the gates of all the select transistors ST on the same row are connected to one of replica select gate lines RSG0to RSG(4m−1).

The word lines WL0to WL(4m−1) are connected to the write decoder20. One end of each of the select gate lines SG0to SG(4m−1) is connected to a select gate decoder30-0or30-1. The other end of the select gate line traverses the replica cell array RCS and is connected to the write decoder20. That is, the replica cell array RCA is placed at the inner end of the plane10-0or10-1and at the position farthest from the select gate decoder30. The replica select gate lines RSG0to RSG(4m−1) are separated from the select gate lines SG0to SG(4m−1) and have the same potential (VPW) as that of a well region in which the planes10-1and10-1are formed. The source regions of the select transistors in a plurality of memory cell blocks BLK are connected together and to a source line driver90.

Now, the configuration of the first column selector WCS will be described. Each first column selector WCS comprises four MOS transistors11to14. One end of a current path in each of the MOS transistors11to14is connected to one end of the corresponding one of the local bit lines LBL0to LBL3. The other ends of the current paths in the MOS transistors11and12are connected together. The other ends of the current paths in the MOS transistors13and14are connected together. A common connection node connecting the MOS transistors11and12together will be called a node N10below. A common connection node connecting the MOS transistors13and14together will be called a node N11below. The gate of each of the MOS transistors11to14is connected to one of write column select lines WCSL0to WCSL(2m−1). The MOS transistors11and13included in all the first column selectors WCS on the same row are connected to the same write column select line WCSLi (i: 1, 3, 5, . . . ). The MOS transistors12and14included in the first column selectors WCS on the same row are connected to the same write column select line WCSL(i−1). For a write operation, the column decoder40-0or40-1selects one of the write column select lines WCSL0to WCSL(2m−1).

The nodes N10and N11in the prime cell array PCA are each connected to the corresponding one of write global bit lines WGBL0to WGBL(2n−1). On the other hand, the nodes N10and N11in the replica cell array RCA are connected to replica write global bit lines R_WGBL0and R_WGBL1, respectively. Each of the write global bit lines WGBL0to WGBL(2n−1) and replica write global bit lines R_WGBL0and R_WGBL1connects the nodes N10or N11in all the first column selectors WCS on the same column.

Now, the configuration of the second column selector RCS will be described. Each second column selector RCS comprises four MOS transistors15to18. One end of a current path in each of the MOS transistors15to18is connected to the other end of the corresponding one of the local bit lines LBL0to LBL3. The other ends of the current paths in the MOS transistors15to18are connected together. The common connection node connecting the MOS transistors15to18together will be called a node N20below. The gates the MOS transistors15to18are connected to different read column select lines RCSL0to RCSL(4m−1). The MOS transistors15to18included in all the second column selectors RCS on the same row are connected to read column select lines RCSL0to RCSL(4m−1), respectively. For a read operation, the column decoder40-0or40-1selects one of the read column select lines RCSL0to RCSL(4m−1).

The nodes N20in the prime cell array PCA are each connected to the corresponding one of read global bit lines RGBL0to RGBL(n−1). On the other hand, the nodes N20in the replica cell array RCA are connected to a replica read global bit line R_RGBL. Each of the read global bit lines RGBL0to RGBL(n−1) and replica read global bit line R_RGBL connects the nodes N20in all the first column selectors RCS on the same column.

Another description may be given of the configuration of the memory cell array10(planes10-0and10-1) according to the present embodiment. A plurality of memory cells are arranged in a matrix in the memory cell array10. A common word line connects to the control gates of the memory cell transistors MT in all the memory cells MC on the same row. A common select gate line connects to the gates of the select transistors in all the memory cells on the same row. One of the local bit lines LBL0to LBL3connects to the drains of the memory cell transistors MT in the four memory cells MC on the same row. That is, of the plurality of memory cells MC in the memory cell array10, every four memory cells MC arranged in a line are connected to a different one of the local bit lines LBL0to LBL3. One end of each of the local bit lines LBL0and LBL1on the same column is connected to the same one of the write global bit lines WGBL0to WGBL(2n−1) via the MOS transistors11and12, respectively. One end of each of the local bit lines LBL2and LBL3on the same column is connected to the same one of the write global bit lines WGBL0to WGBL(2n−1) via the MOS transistors13and14, respectively. The other end of each of the local bit lines LBL0to LBL3on the same column is connected to the same one of the write global bit lines RGBL0to RWGBL(2n−1) via the corresponding one of the MOS transistors15to18. The sources of the select transistors ST in the memory cells MC are connected together and to the source line driver. In the memory cell array configured as described above, one memory cell block BLK is composed of four columns of the four memory cells MC connected to the same local bit line. The same memory cell block is connected to the common write global bit line and the common read global bit line. In the above configuration, the memory cells MC in the memory cell block BLK located farthest from the select gate decoder30function as replica cells.

The number of memory cells in the memory cell block, the number of read global bit lines RGBL, and the number of read global bit lines WGBL are not limited to those in the present example of the configuration. Further, each of the local bit lines LBL0to LBL3in the prime cell array PCA has a parasitic capacitance smaller than that of each of the local bit lines LBL0to LBL3in the replica array RCA. This relationship is established even when all the prime cells connected to each of the local bit lines LBL0to LBL3in the prime cell array PCA.

FIG. 1will be referred to again. The write circuit60latches write data.

The write selector50applies a write voltage or a write inhibition voltage to the write global bit line and the replica global bit line.

The switch group100transfers write data provided by CPU2to the write circuit60.

With reference toFIG. 4, description will be given of the configuration of the write selector50, write circuit60, and switch group100.FIG. 4is a circuit diagram of the write selector50, write circuit60, and switch group100.

First, the write selector50will be described. The write selector50comprises select circuits51each provided for the corresponding one of the write global bit lines WGBL0to WGBL(2n−1), R_WGBL0, and R_WGBL1. Each of the select circuits51comprises two n channel MOS transistors52and53. The write inhibition voltage VBI is applied to a source of the n channel MOS transistor52. A drain of the n channel MOS transistor52is connected to corresponding write global bit line. The write voltage VNEGPRG is applied to a source of the n channel MOS transistor53. A drain of the n channel MOS transistor53is connected to the corresponding write global bit line and to the drain of the n channel MOS transistor52. The write voltage VNEGPRG is applied to back gates of the n channel MOS transistors52and53.

Now, the write circuit60will be described. The write circuit60comprises latch circuits61each provided for the corresponding one of the write global bit lines WGBL0to WGBL(2n−1), R_WGBL0, and R_WGBL1. Each of the latch circuits61comprises two inverters62and63. An input end of the inverter62is connected to an output end of the inverter63. An output end of the inverter62is connected to an input end of the inverter63. An output node of the latch circuit61is composed of a connection node connecting the input end of the inverter62and the output end of the inverter63. The output node is connected to the corresponding bit line. The inverters62and63each comprise an n channel MOS transistor64and a p channel MOS transistor65. The write voltage VNEGPRG is applied to a source of the n channel MOS transistor64. The voltage Vcc1(=3 V: constant) is applied to a source of the p channel MOS transistor65. That is, the inverters62and63each operate using Vcc1and VNEGPRG as low and high power supply voltages, respectively. A gate of the n channel MOS transistor64is connected to a gate of the p channel MOS transistor65. A connection node connecting drains of the p and n channel MOS transistors65and64in the inverter63is connected to a connection node connecting the gates of the p and n channel MOS transistors65and64in the inverter62. The connection node connecting drains of the p and n channel MOS transistors65and64in the inverter63is further connected to the corresponding write global bit line. A connection node connecting drains of the p and n channel MOS transistors65and64in the inverter62is connected to a connection node connecting the gates of the p and n channel MOS transistors65and64in the inverter63. These connection nodes constitute an input node of the latch circuit61.

The switch group100includes p channel MOS transistors101and n channel MOS transistors102so that each pair of the p channel MOS transistor101and n channel MOS transistor102is provided for the corresponding latch circuit61(the MOS transistor102will be referred to as a reset transistor below). Write data is input to one end of a current path in the p channel MOS transistor101. The other end of the current path is connected to the input node of the corresponding latch circuit61. A gate of the MOS transistor101is always grounded. The voltage Vcc1is applied to a back gate of the MOS transistor101. The write voltage VNEGPRG is applied to one end of a current path in the reset transistor and to a back gate of the reset transistor. The other end of the reset transistor is connected to the input node of the latch circuit61and the other end of the current path in the p channel MOS transistor101. The gates of all the reset transistors102are connected together. A reset signal Reset is input to these connected gates. The same ends of the current paths in the reset transistors102are also connected together. The voltage VNEGPRG is collectively applied to these ends.

The column decoder40decodes a column address signal to obtain a column address decode signal. On the basis of the column address decode signal, the column select lines WCSL and RSCL perform a selecting operation.

For a read operation, the read circuit70precharges the read global bit lines RGBL0to RGBL(n−1). The read circuit70then amplifies data read onto the read global bit lines RGBL0to RGBL(n−1).

For a read operation, the read control circuit80precharges and discharges the replica read global bit line R_RGBL. The read circuit70is then controlled on the basis of the times required to precharge and discharge the replica read global bit line R_RGBL.

With reference toFIG. 5, description will be given of the configuration of the read circuit70and read control circuit80.FIG. 5is a circuit diagram of the read circuit70and read control circuit80.

First, the read circuit70will be described. The read circuit70comprises read out units71each provided for the corresponding one of the read global bit lines RGBL0to RGBL(n−1). Each of the read out units71comprises an isolating MOS transistor72, a first precharge circuit73, and a sense amplifier74.

For a read operation, the first precharge circuit73precharges the corresponding one of the read global bit lines RGBL0to RGBL(n−1). The first precharge circuit73is composed of, for example, p channel MOS transistors Q1, Q3, and Q5and n channel MOS transistors Q2, Q4, Q6, and Q7as shown inFIG. 6. A source of the MOS transistor Q1is connected to the power supply VDD. A precharge signal /PRE is supplied to a gate of the MOS transistor Q1. A drain of the MOS transistor Q2is connected to a drain of the MOS transistor Q1. A source of the MOS transistor Q2is connected to an input end of an inverter77in the sense amplifier74and to a source of the isolating MOS transistor72. Current paths in the MOS transistors Q5, Q3, Q4, and Q6are connected in series between the power supply VDD and a ground point. Gates of the MOS transistors Q3and Q4are connected to the source of the MOS transistor Q2. The precharge signal /PRE is supplied to a gate of the MOS transistor Q5. A gate of the MOS transistor Q6is connected to the power supply VDD. The junction between drains of the drains of the MOS transistors Q3and Q4is connected to a gate of the MOS transistor Q2. A drain of the MOS transistor Q7is connected to the gate of the MOS transistor Q2. A source of the MOS transistor Q7is connected to the ground point. The precharge signal /PRE is supplied to a gate of the MOS transistor Q7.

In the above configuration, in the MOS transistors Q5, Q3, Q4, and Q6with the current paths connected in series, when the precharge signal /PRE is made low, the MOS transistor Q5is turned on to output a bias voltage BIAS. The gate voltage of the MOS transistor Q2is thus adjusted to control the level of the corresponding bit line. After the bit line is charged, the precharge signal /PRE goes high to turn off the MOS transistor Q5. The MOS transistors Q4and Q6discharge the gate (bias voltage BIAS) of the MOS transistor Q2to ground potential. This turns off the MOS transistor Q2to prevent the charge present at the drains of the MOS transistors Q1and Q2from migrating to the bit line. It is therefore possible to eliminate the effect of weakly charging the bit line after precharging.

If the bit line is low and the MOS transistor Q4has a high threshold voltage, when the precharge signal /PRE goes high, the MOS transistor Q7sets the gate voltage of the MOS transistor Q2, in other words, the bias voltage BIAS, to the ground potential. That is, the MOS transistors Q5, Q3, Q4, and Q6with the current paths connected in series make it possible to increase operation speed and reduce power consumption. However, the MOS transistors Q5, Q3, Q4, and Q6prevent a delay in setting the level of the bias voltage BIAS at 0 V if the bit line and the input end of the inverter77are at a low precharge level and if the MOS transistor Q4has a high threshold voltage. Further, precharging sets the bit line at a voltage level of about VDD/2. Accordingly, the MOS transistor Q4cannot discharge the gate (bias node) of the MOS transistor Q2rapidly. However, since the precharge signal /PRE is input to the gate of the MOS transistor Q4, the bias voltage BIAS can be logically set at 0 V quickly. Thus, the high precharge signal /PRE enables the MOS transistor Q2to be turned off quickly. Thus makes it possible to more quickly shut down migration of the charge present at the drains of the MOS transistors Q1and Q2to the bit line. The speed of a read operation performed on a memory cell in the on state can be increased.

Further, during discharging, that is, while the precharge signal /PRE is high, the MOS transistor Q5is off. Consequently, no through current flows through the MOS transistors Q5, Q3, Q4, and Q6with the current paths connected in series between the power supply VDD and the ground point. This reduces power consumption. Furthermore, since the MOS transistors Q5and Q7are controlled using the precharge signal /PRE, no new signal needs to be added. Controlled can be simply performed.

In the first precharge circuit73, the gates of the MOS transistors Q3and Q4may be connected to the source of the MOS transistor72as shown inFIG. 8. In the configuration shown inFIGS. 6 and 8, the source of the MOS transistor Q4may be connected to the ground point with the MOS transistor Q6not provided. Moreover, instead of connecting the gate of the MOS transistor to the power supply VDD, it is possible to feed back an output signal CMOUT from the inverter77via an inverter INV.

In the configuration shown inFIG. 9, in an initial state, a voltage VBL is reset to 0 V. Accordingly, an output signal CLOCKIN from the inverter INV is low. When the precharge signal /PRE goes low to start precharging. Then, when the potential VBL is at a low level, the signal CLOCKIN stays low. Consequently, the bias node (bias voltage BIAS) is high. When the potential VBL and bit line are raised to a sufficiently high level, the signal CLOCKIN goes high. This enables feedback to be applied according to the level of the potential VBL.

The provision of the inverter INV allows the potential VBL to reach the threshold value faster than the bit line. Consequently, feedback is applied before the bit line is sufficiently precharged. The provision of the inverter allows precharging to be accomplished more quickly. Thus, the speed of precharging can be increased by applying feedback while monitoring the output signal CMOUT from the inverter77.

FIG. 11is a waveform diagram of variations in the potentials of the nodes of the read circuit described inFIG. 7(b) of Non-Patent Document 1 and of the read circuit according to the present embodiment. As shown in the figure, the bias voltage BIAS rises rapidly in response to transition of the precharge signal /PRE. This makes it possible to suppress wasteful current consumption. Further, a reduced amount of charge is present at the input node of the sense amplifier. The inversion speed of the output node CMOUT of the inverter77is increased.

For a read operation, the sense amplifier74amplifies the read data read onto the corresponding one of the read global bit lines RGBL0to RGBL(n−1). The sense amplifier74comprises the inverter77and a flip flop78. The input node of the inverter77is connected to the source of the MOS transistor Q2. The output node of the inverter77is connected to an input node of the flip flop78. Output nodes OUT0to OUTn of the flip flop78output the amplified read data.

The isolating MOS transistor72is an n channel MOS transistor having a current path one end of which is connected to the corresponding one of the read global bit lines RGBL0to RGBL(n−1). The other end of the current path is connected to the source of the MOS transistor Q2and to the input node of the inverter77. That is, the first precharge circuit73and the sense amplifier74are connected to the corresponding ones of the read global bit lines RGBL0to RGBL(n−1) via the isolating MOS transistor72.

Now, the read control circuit80will be described. The read control circuit80comprises a discharge circuit81, an isolating MOS transistor82, a second precharge circuit83, and a signal processor (or signal generator)84.

For a read operation, the second precharge circuit83precharges the replica read global bit line R_RGBL. The second precharge circuit83has a configuration basically similar to that of the first precharge circuit and has the precharge capability as that of the first precharge circuit. That is, as shown inFIG. 7A, the second precharge circuit83is composed of p channel MOS transistors Q11, Q13, and Q15and n channel MOS transistors Q12, Q14, and Q16. A source of the MOS transistor Q11is connected to the power supply VDD. The precharge signal /PRE is supplied to a gate of the MOS transistor Q11. A drain of the MOS transistor Q12is connected to a drain of the MOS transistor Q11. A source of the MOS transistor Q12is connected to the input end of the inverter77in the sense amplifier74and to a drain of the isolating MOS transistor82. Current paths in the MOS transistors Q15, Q13, Q14, and Q16are connected in series between the power supply VDD and the ground point. Gates of the MOS transistors Q13and Q14are connected to a source of the MOS transistor Q12. The precharge signal /PRE is supplied to a gate of the MOS transistor Q15. A gate of the MOS transistor Q16is connected to the power supply VDD. The junction between drains of the MOS transistors Q13and Q14is connected to a gate of the MOS transistor Q12.

As described above, the read circuit free from the MOS transistor Q7is used as the read control circuit (replica read control circuit)83. Then, this read circuit performs a reliably slower read operation than the read circuit73of the main body. Consequently, the read control circuit83is more accurate. Further, a delay circuit is not required which is used to output a signal (Read-end) indicating that the read operation has been finished. This circuit also eliminates the need to tune an additional capacitance compared to a circuit that uses a replica circuit having a configuration similar to that of the read circuit and memory cell array in the main body and having an additional capacitance.

In the circuit shown inFIG. 7A, the precharge signal /PRE is supplied to the gate of the MOS transistor Q15. However, ground potential VSS may be applied to the gate of the MOS transistor Q15as shown inFIG. 7B. By thus applying the ground potential VSS to the gate of the MOS transistor Q15, it is possible to more reliably reduce the speed of a read operation performed on the replica circuit.

The second precharge circuit83may have a configuration similar to that of the first precharge circuit73. Accordingly, it is possible to apply the circuit shown inFIGS. 6 and 8and from which the MOS transistor Q6is removed and the circuit shown inFIGS. 8 and 9and from which the MOS transistor Q7is removed.

The isolating MOS transistor82is an n channel MOS transistor having a current path one end of which is connected to the replica read global bit line R_RGBL. The other end of the current path is connected to the source of the MOS transistor Q12. That is, the second precharge circuit83is connected to the corresponding ones of the read global bit lines RGBL0to RGBL(n−1) via the isolating MOS transistor82. A gate of the MOS transistor82is connected to the gates of the isolating MOS transistors72. A signal ISO is input to the gate of the MOS transistor82.

For a read operation, the signal processor84generates a read end signal Read-end on the basis of the source potential of the MOS transistor Q12, that is, the potential across the replica read global bit line R_RGBL. The read end signal Read-end is input to the flip flop78of the sense amplifier74. The read end signal Read-end causes the flip flop78to establish the output.

In the example shown inFIG. 5, one isolating MOS transistor is provided for each sense node. However, the present invention is also applicable to a configuration in which a plurality of (for example, 16) isolating MOS transistors72-0to72-nare provided for each sense node as shown inFIG. 10.

The discharge circuit81discharges the replica read global bit line R_RGBL. The configuration of the discharge circuit81will be described with reference toFIG. 12.FIG. 12is a circuit of the discharge circuit81. As shown in the figure, the discharge circuit81comprises a current source circuit87, a voltage generator88, and an n channel MOS transistor89.

The voltage generator88outputs a constant voltage Vref when discharging the replica read global bit line R_RGBL.

The current source circuit87conducts a current corresponding to the constant voltage Vref to discharge the replica read global bit line R_RGBL. The current source circuit87has n channel MOS transistors87-1and87-2. A drain of the MOS transistor87-1is connected to the replica read global bit line R_RGBL. A source of the MOS transistor87-1is connected to a drain of the MOS transistor87-2. A source of the MOS transistor87-2is connected to a drain of the MOS transistor89. Gates of the MOS transistors87-1and87-2are connected together. The constant voltage Vref is applied to these gates.

A source of the MOS transistor89is grounded. The precharge signal /PRE is supplied to a gate of the MOS transistor89. This makes the precharge signal /PRE high, that is, turns on the discharge circuit81on after precharging has been finished.

The current source circuit87may have for example, the same structure as that of the memory cell MC in the memory cell array10. That is, the MOS transistor87-1corresponds to the memory cell transistor MT. The MOS transistor87-2corresponds to the select transistor ST. A contact plug is provided which is connected to floating gates of both transistors. The constant voltage Vref is applied to the contact plug.

FIG. 1will be referred to again.

The source line driver90supplies a voltage to source lines SL.

An address buffer110retains an address signal provided by CPU2. The address buffer110then supplies a column address signal CA to the column decoder40and a row address signal RA to the write decoder20, select gate decoder30, and write circuit60.

On the basis of an instruction signal provided by CPU2, a write state machine120controls the operation of each of the circuits contained in the flash memory3. The write state machine120also controls timings for a data write, erase, and read operations. The write state machine120further executes a predetermined algorithm determined for each operation.

The voltage generator130generates a plurality of internal voltages on the basis of an externally input voltage Vcc1(about 3 V). The voltage generator comprises a negative charge pump circuit and a positive charge pump circuit. The voltage generator generates negative voltages VBB1(=−6 V), VBB2(=−3.5 V), and VBB3as well as a positive voltage VPP (=10 V). The write decoder20is supplied with the negative voltage VBB1and the positive voltage VPP. The write selector50is supplied with the negative potentials VBB1, VBB2, and VBB3. The negative potential VBB1is further supplied to the write circuit60.

Now, with reference toFIG. 13, description will be given of the configuration of the write decoder20and select gate decoder30. For a write operation, the write decoder20selects one of the word lines WL0to WL(4m−1) and applies the positive potential VPP (10 V) to the selected word line. The write decoder20applies the negative potential VBB1(−6 V) to all the select gate lines SG0to SG(4m−1). Further, for an erase operation, the write decoder20applies the negative potential VBB1to all the word lines and the positive potential VPP to all the select gate lines SG0to SG(4m−1).

For a read operation, the select gate decoder30selects one of the select gate lines SG0to SG(4m−1) and applies the positive potential Vcc1to the selected select gate line. The select gate decoder30also controls the signal ISO and thus the operation of the isolating MOS transistor82.

First, the configuration of the select gate decoder30will be described. The select gate decoder30comprises a row address decode circuit31and a switch element group32. The row address decode circuit31operates at the power supply voltage Vcc1to decode row address signals RA0to RAi of (i+1) bits to obtain a row address decode signal. The row address decode circuit31has a NAND circuit33and an inverter34provided for each of the select gate lines SG0to SG(4m−1). The NAND circuit33executes a NAND operation on the bits of the row address signals RA0to RAi. The inverter34inverses the result of the NAND operation and outputs the inverted result as a row address decode signal.

The switch element group32has an n channel MOS transistor35. The n channel MOS transistor35is provided for each of the select gate lines SG0to SG(4m−1). An output from the inverter34is provided to the select gate lines SG0to SG(4m−1) via the current path in the n channel MOS transistor35. A control signal ZISOG is input to a gate of the n channel MOS transistor35. The control signal ZISOG turns off the MOS transistor35for a write operation and turns it on for a read operation.

Now, the configuration of the write decoder20will be described. The write decoder20comprises a row address decode circuit21and a switch element group22. The row address decode circuit21decodes the row address signals RA0to RAi of (i+1) bits to obtain a row address decode signal. The row address decode circuit21has a NAND circuit23and an inverter24provided for each of the word lines WL0to WL(4m−1). The NAND circuit23and the inverter24each have a positive power supply voltage node connected to a power supply voltage node VCGNW and a negative power supply voltage node connected to the power supply voltage node VCGPW. The NAND circuit23executes a NAND operation on the bits of the row address signals RA0to RAi. The power supply voltage nodes VCGNW and VCGPW are provided with the positive voltage VPP, negative voltage VBB1, and 0 V generated by the voltage generator130. The inverter24then inverses the result of the NAND operation and outputs the inverted result as a row address decode signal.

The switch element group22has an n channel MOS transistor25. The n channel MOS transistor25is provided for each of the select gate lines SG0to SG(4m−1). One end of a current path in the MOS transistor25is connected to the corresponding one of the select gate lines SG0to SG(4m−1). The negative potential VBB1and the positive potential VPP are applied to the other end of the current path. The control signal WSG is input to a gate of the MOS transistor25. The control signal WSG turns on the MOS transistor25for a write and erase operations.

Moreover, the write decoder20applies the voltage VPW to the semiconductor substrate (well region) in which the memory cell array10is formed. The voltage VPW is provided to the replica select gate lines RSG0to RSG(4m−1) connected to the well region.

Now, with reference toFIGS. 14 to 18, description will be given of the planar structure of the memory cell array10provided in the 2Tr flash memory3.FIG. 14is a plan view of a particular region of the memory cell array10.FIGS. 14 to 18are plan views showing a planar pattern of the first to fourth-level metal interconnect layers in addition to element regions, word lines, and select gate lines. The area illustrated corresponds toFIG. 14.

As shown inFIGS. 14 to 18, a plurality of stripe-shaped element regions AA each extending in a first direction are formed in a semiconductor substrate (p-type well region)200along a second direction orthogonal to the first direction. The stripe-shaped word lines WL0to WL(4m−1) are formed to stride the plurality of element regions AA; each of the stripe-shaped word lines WL0to WL(4m−1) extends in the second reaction. Within the prime cell array PCA, the select gate lines SG0to SG(4m−1) are formed parallel to the word lines WL0to WL(4m−1). Within the replica cell array RCA, the replica select gate lines RSG0to RSG(4m−1) are formed parallel to the word lines WL0to WL(4m−1). The word lines WL0to WL(4m−1) electrically connect the prime cell array PCA and the replica cell array RCA together. In contrast, the select gate lines SG0to SG(4m−1) are electrically separated from the replica select gate lines RSG0to RSG(4m−1). The memory cell transistor MT is formed in the region where any of the word lines WL0to WL(4m−1) crosses the element region AA. On the other hand, the select transistor ST is formed in the region where any of the select gate lines SG0to SG(4m−1) crosses the element region AA and in the region where any of the replica select gate lines RSG0to RSG(4m−1) crosses the element region AA. The floating gates (not shown) of the memory cell transistors MT are each formed in the region where any of the word lines WL0to WL(4m−1) crosses the element region AA; the floating gates are separated from one another. The select transistor ST has a control gate and a floating gate similarly to the memory cell transistor MT. However, in contrast to the memory cell transistors MT, the floating gates of the select transistors ST adjacent to each other in the second direction are connected together. The select gate lines SG or word lines WL in the adjacent prime cells are adjacent to each other. The replica select gate lines RSG or word lines WL in the adjacent replica cells are adjacent to each other.

In the prime cell array PCA, the four element regions AA are collectively called a first element region group AAG1. The region between the adjacent first element region groups AAG1in which one element region AA is formed is called a source contact region SCA. The memory cells MC formed in the first element region group AAG1are used to store data. However, the memory cells MC in the source contact region SCA are dummies and are not used to store data. Further, a stitch region SA1is formed for every two first element region groups AAG1. In the present embodiment, no element region AA is formed in the stitch region SA1. The width of the stitch region SA1is equal to that of one element region AA plus an isolation region STI formed between the element regions AA. The word lines WL0to WL(4m−1) and the select gate lines SG0to SG(4m−1) are also formed on the stitch region SA1. However, the word lines WL0to WL(4m−1) and select gate lines SG0to SG(4m−1) present in the stitch region SA1do not substantially constitute prime cells. Further, the select gate lines SG0to SG(4m−1) are formed to be partly wider in the stitch region SA1. In particular, this part is formed so as to project toward to the adjacent select gate lines. This region will be a shunt region SA below. The shunt region SA2alternates with the select gate lines SG0to SG(4m−1). Specifically, in a certain stitch region SA1, the shunt region SA2is formed for each of the select gate lines SG0, SG2, SG4, . . . . In another stitch region SA1adjacent to the above stitch region, the shunt region SA2is formed for each of the select gate lines SG1, SG3, SG5, . . . . Select gate lines for which the shunt region SA2is not formed are partly removed in the stitch region SA1. The first element region group AAG1and the source contact region SCA will be collectively referred to as a second element region group AAG2.

A group of four element regions AA in the replica cell array RCA will be referred to as a third element region group AAG3. The following region will be referred to as a stitch area SA3: the region which is adjacent to the third element region group AAG3and which includes one element region AA. The word lines WL0to WL(4m−1) and the replica select gate lines RSG0to RSG(4m−1) are also formed on the stitch region SA3. However, the word lines WL0to WL(4m−1) and replica select gate lines RSG0to RSG(4m−1) present in the stitch region SA3do not substantially constitute replica cells. Further, the replica select gate lines RSG0to RSG(4m−1) are formed to be partly wider in the stitch region SA3as in the case of the stitch region SA1. In particular, this part is formed so as to project toward to the adjacent select gate lines. This region will be a shunt region SA4below.

Now, with reference toFIGS. 14 and 15, description will be given of the first-level metal interconnect layer presents on the word lines WL0to WL(4m−1), select gate lines SG0to SG(4m−1), and replica select gate lines RSG0to RSG(4m−1). The first-level metal interconnect regions are hatched inFIG. 15.

First, description will be given of the configuration of interior of the prime cell array PCA. As shown in the figures, a stripe-shaped metal interconnect layer210is formed between the adjacent select gate lines SG (SG0and SG1, SG2and SG3, . . . ); the metal interconnect layer210extends along the second direction. The metal interconnect layer210constitutes a part of the corresponding source line SL in the prime cell array PCA. The metal interconnect layer210is separated into parts by the stitch regions SA1in the longitudinal direction (second direction). That is, the metal interconnect layer210has an independent shape for each second element region group AAG2. The metal interconnect layers210are connected together by the source regions of select transistors ST in the prime cells and the contact plugs CP1. In the present example, no contact plugs CP1are formed in the source contact region SCA. Accordingly, the metal interconnect layer210is not electrically connected to the source region of the memory cell in the source contact region SCA. Further, an island-shaped metal interconnect layer220is formed on the drain region of each of the memory cell transistor MT in the first element region group AAG1. The metal interconnect layers220are separated from one another and connected by respective contact plugs CP2to the drain regions of the corresponding memory cell transistors MT. Therefore, the plurality of metal interconnect layer220groups and the stripe-shaped metal interconnect layers210are alternately arranged along the first direction; the metal interconnect layer220groups are arranged in the second direction and the metal interconnect layers210extend along the second direction. Moreover, an island-shaped metal interconnect layer230is formed on each of the shunt regions SA2. The metal interconnect layer230is connected by a contact plug CP3to the shunt region SA2of the corresponding select gate line SG. The metal interconnect layer230is extended from the upper part of the corresponding select gate line SG to the upper part of the corresponding word line WL.

Now, description will be given of the interior of the replica cell array RCA. As shown in the figures, the stripe-shaped metal interconnect layer210is formed between the adjacent replica select gate lines RSG (RSG0and RSG1, RSG1and RSG2, . . . ); the metal interconnect layer210extends along the second direction. The metal interconnect layer210constitutes a part of the corresponding source line SL in the replica cell array RCA. The metal interconnect layers210are connected together by the source regions of the select transistors ST and the contact plugs CP1. Further, as in the case of the prime cell array PCA, the island-shaped metal interconnect layer220is formed on the drain region of each of the memory cell transistors MT in the third element region group AAG3. The metal interconnect layer220is connected by the contact plug CP2to the drain region of the corresponding memory cell transistor MT. Further, metal interconnect layers400are formed in the stitch region SA3; each of the metal interconnect layers400is separated from the metal interconnect layer210. The metal interconnect layer400is connected by the corresponding contact plug CP3to the shunt regions SA4of the corresponding ones of the replica select gate lines RSG0to RSG(4m−1). The metal interconnect layer400is further connected to the element region AA by a contact plug CP8.

Now, with reference toFIGS. 14 and 16, description will be given of the pattern of the second-level metal interconnect layers present on the first-level metal interconnect layers210to230and400. The second-level metal interconnect layers are hatched inFIG. 16.

As shown in the figures, in the first element region group AAG1and third element region group AAG3, a stripe-shaped metal interconnect layer240extending along the first direction is formed on each element region AA. The metal interconnect layer240functions as the local bit line LBL0or LBL1. The metal interconnect layer240is connected to the corresponding first-level metal interconnect layer220by a contact plug CP4. A metal interconnect layer250similar to the metal interconnect layer240is formed in each source contact region SCA. Accordingly, the line width of the metal interconnect layer250is the same as that of the metal interconnect layer240. The metal interconnect layer250functions as a part of the corresponding source line SL. The metal interconnect layer240is connected to the corresponding first-level metal interconnect layer210by a contact plug CP5. That is, the plurality of metal interconnect layers210are connected together by the metal interconnect layer250; the plurality of metal interconnect layers210are separated from one another in the first direction. Further, island-shaped metal interconnect layers260are formed in each stitch region SA1. The metal interconnect layers260are formed in association with the corresponding first-level metal interconnect layers230. The metal interconnect layers260have substantially the same geometrical pattern as that of the metal interconnect layers230. The metal interconnect layers260overlap the respective metal interconnect layers230. InFIGS. 14 and 16, a contact plug CP6is located immediately above the corresponding word line WL. However, the position of the contact plug CP6is not limited provided that it enables the metal interconnect layers230and260to be connected together.

Now, with reference toFIGS. 14 and 17, description will be given of the pattern of the third-level metal interconnect layers present on the second-level metal interconnect layers240to260. The third-level metal interconnect layers are hatched inFIG. 17.

As shown in the figures, stripe-shaped metal interconnect layers270are formed and extend along the second direction. Each of the metal interconnect layers270is provided for a set of a word line and a select gate line (a set of WL0and SG1, a set of WL1and SG1, . . . ). The metal interconnect layer270is connected by a contact plug CP7to the corresponding second-level metal interconnect layer260electrically connected to the corresponding select gate line. That is, each metal interconnect layer270functions as a shunt interconnect for the corresponding one of the select gate lines SG0to SG(4m−1). Further, the metal interconnect layer270is formed in the region between a central portion of the corresponding word line WL and a central portion of the select gate line SG corresponding to the word line WL. In other words, the plurality of metal interconnect layers270are arranged at equal intervals along the first direction. Each metal interconnect layer270connects the second element region groups AAG2located adjacent to each other in the second direction. One end of the metal interconnect layer270is connected to the select gate decoder30. The other end of the metal interconnect layer270passes over the replica cell array RCA and is connected to the write decoder20.

Now, with reference toFIGS. 14 and 18, description will be given of the pattern of the fourth-level metal interconnect layers present on the third-level metal interconnect layer270. The third-level metal interconnect layers are hatched inFIG. 18.

As shown in the figures, stripe-shaped metal interconnect layers280and290are formed and extend along the first direction. Each of the metal interconnect layers280functions as one of the write global bit lines WGBL0to WGBL(2n−1) or the replica write global bit line R_WGBL0or R_WGBL1. Each of the metal interconnect layers290functions as one of the read global bit lines RGBL0to RGBL(2n−1) or the replica read global bit line R_RGBL. Two metal interconnect layers280and one metal interconnect layer290form a set. Each metal interconnect layer280is provided in association with a set of the two local bit lines LBL0and LBL1or a set of the two local bit lines LBL2and LBL3. Each metal interconnect layer290is provided in association with a set of the local bit lines LBL0to LBL3.

In the above drawings, the source contact area SCA may be provided in the replica cell array RCA.

Now, description will be given of the sectional structure of the flash memory configured as described above. First, with reference toFIGS. 19 to 25, description will be given of the sectional structure of the second element region group AAG2in the prime cell array PCA.FIGS. 19 to 23are sectional views taken along lines X1-X1′, X2-X2′, X3-X3′, X4-X4′, and X5-X5′, respectively.FIGS. 24 and 25are sectional views taken along lines Y1-Y1′ and Y2-Y2′, respectively, inFIG. 14.

As shown in the figures, an n-type well region201is formed in a surface region of a p-type semiconductor substrate200. A p-type well region202is formed in a surface region of the n-type well region201. An isolation region STI is formed in the p-type well region202. The element regions AA are each surrounded by the isolation region STI. A gate insulating film300is formed on the element region AA of the p-type well region201. The gate electrodes of the memory cell transistor MT and select transistor ST are formed on the gate insulating film300. The gate electrodes of the memory cell transistors MT and select transistors ST each have a polycrystalline silicon layer310, an inter-gate insulating film320formed on the polycrystalline silicon layer310, and a polycrystalline silicon layer330formed on the inter-gate insulating film320. The inter-gate insulating film320is formed of for example, a silicon oxide film or an ON film, an NO film, or an ONO film having a stacked structure of a silicon oxide film and a silicon nitride film.

In the memory cell transistor MT, as shown inFIGS. 19 and 22, the polycrystalline silicon layer310is separated into parts each located between the adjacent element regions AA. The polycrystalline silicon layer310thus functions as a floating gate (FG). On the other hand, the polycrystalline silicon layer330connects the adjacent element regions AA together and thus functions as control gates (word lines WL).

In the select transistor ST, as shown inFIGS. 20 and 21, the polycrystalline silicon layers310and320each connect the adjacent element regions AA together. The polycrystalline silicon layers310and330function as select gate lines SG. However, only the polycrystalline silicon layer310substantially functions as the select gate lines (this will be described later in detail).

An impurity diffusion layer340is formed in a surface of the p-type well region202located between the adjacent gate electrodes. The impurity diffusion layer340is shared by the adjacent transistors.

As preciously described, the prime cell PC, including the memory cell transistor MT and the select transistor ST is formed to have the relationship described below. The select transistors ST in the adjacent prime cells PC are adjacent to each other. The memory cell transistors MT in the adjacent prime cells PC are adjacent to each other. The impurity diffusion layer340is shared by the adjacent select transistors ST or memory cell transistors MT. Accordingly, if the select transistors ST are adjacent to each other, the two adjacent prime cells PC and PC are arranged symmetrically with respect to the impurity diffusion layer340shared by the two select transistors ST and ST. In contrast, if the memory cell transistors MT are adjacent to each other, the two adjacent prime cells PC and PC are arranged symmetrically with respect to the impurity diffusion layer340shared by the two memory cell transistors MT and MT.

An inter-level insulating film350is formed on the p-type well region202so as to cover the memory cell transistors MT and select transistors ST. The contact plug CP1is formed in the inter-level insulating film350; the contact plug CP1reaches the impurity diffusion layer (source region)340shared by the two select transistors ST and ST. The metal interconnect layer210connected to the contact plug CP1is formed on the inter-level insulating film350. The metal interconnect layer210functions as the source line SL. The contact plug CP2is formed in the inter-level insulating film350; the contact plug CP2reaches the impurity diffusion layer (drain region)340shared by the two memory cell transistors MT and MT. The metal interconnect layer220connected to the contact plug CP2is formed on the inter-level insulating film350.

An inter-level insulating film360is formed on the inter-level insulating film350so as to cover the metal interconnect layers210and220. The contact plug CP4, reaching the metal interconnect layer220, is formed in the inter-level insulting film360(seeFIG. 24). The metal interconnect layer240, connected to the plurality of contact plugs CP4, is formed on the inter-level insulating film360(seeFIG. 24). The metal interconnect layer240functions as one of the local bit lines LBL0to LBL3. The contact plug CP5, reaching the metal interconnect layer210, is formed in the inter-level insulating film360(seeFIG. 25; source contact region SCA). The metal interconnect layer250is formed on the inter-level insulating film360; the metal interconnect layer250connect the plurality of contact plugs CP5across the bit lines (seeFIG. 25; source contact region SCA). The metal interconnect layer250functions as a part of the source line SL.

An inter-level insulating film370is formed on the inter-level insulating film360so as to cover the metal interconnect layers240and250. The metal interconnect layer270is formed on the inter-level insulating film370. The metal interconnect layer270functions as the shunt interconnect of the select gate line. The interconnects are arranged at equal intervals. An inter-level insulating film380is formed on the inter-level insulating film370so as to cover the metal interconnect layer270.

The metal interconnect layers280and290are formed on the inter-level insulating film380and functions as a write global bit line and a read global bit line, respectively. An inter-level insulating film390is further formed on the inter-level insulating film380.

Now, with reference toFIGS. 20,23, and26, description will be given of the sectional structure of the stitch region SA1in the prime cell array.FIG. 26is a sectional view taken along line Y3-Y3′ inFIG. 14.

As shown in the figures, the isolation region STI is formed in the p-type well region202. The floating gate310and control gate330of the memory cell transistor MT are formed on the isolation region STI. Select gate lines not having the shunt region SA2in the stitch region SA1are free from the polycrystalline silicon layer310and330(seeFIG. 20). That is, these select gate lines are each divided into two parts across the stitch region SA1. Select gate lines having the shunt region SA2have the stacked gate formed even in the stitch region, the stacked gate containing the polycrystalline silicon layers310and330. The stacked gate is formed to project toward the adjacent select gate lines (seeFIG. 26). Moreover, as shown inFIGS. 23 and 26, in the shunt region SA2, the polycrystalline silicon layer330and the inter-gate insulating film320are removed to expose the polycrystalline silicon layer310. The contact plug CP3is formed in contact with the polycrystalline silicon layer310in this region. The contact plug CP3is electrically separated from the polycrystalline silicon layer330by an insulating film331(seeFIGS. 23 and 26). The contact plug CP3is formed so as to extend from a surface of the inter-level insulating film350to the polycrystalline silicon layer310.

The metal interconnect layer230is formed on the inter-level insulating film350. The metal interconnect layer230is extended so as to cover the upper part of the gate electrode of the corresponding select transistor ST and to cover the upper part of the stacked gate electrode of the memory cell transistor MT corresponding to the above select transistor (seeFIG. 26). The metal interconnect layer230is connected to the contact plug CP3connected to the corresponding to the select transistor ST. An inter-level insulating film360is formed on the inter-level insulating film350so as to cover the metal interconnect layer230. The contact plug CP6, reaching the metal interconnect layer230, is formed in the inter-level insulating film360. The metal interconnect layer260, connected to the contact plug CP6, is formed on the inter-level insulating film360. Like the metal interconnect layer230, the metal interconnect layer260is extended so as to cover the upper part of the gate electrode of the corresponding select transistor ST and to cover the upper part of the stacked gate electrode of the memory cell transistor MT corresponding to the above select transistor (seeFIG. 26). The inter-level insulating film370is formed on the inter-level insulating film360. The contact plug CP7, reaching the metal interconnect layer260, is formed in the inter-level insulating film370. As shown inFIG. 26, the contact plug CP7is located in a central portion of the memory cell. In other words, the contact plug CP7is formed in the region between a central portion of the stacked gate of the memory cell transistors MT and a central portion of the gate electrode of the select transistor ST. The plurality of metal interconnect layers270are arranged on the inter-level insulating film370at equal intervals as shown inFIG. 26. Interlayer insulating films380and390are formed on the inter-level insulating film370so as to cover the metal interconnect layer270.

FIG. 27is a perspective view of the shunt region SA2. As shown in the figure, the stacked gate structure forming a select gate line is formed to be partly winder. The polycrystalline silicon layer330and inter-gate insulating film320are removed from a part of the wider region. The polycrystalline silicon layer310is exposed in this part. The contact plug CP3is formed in contact with the exposed polycrystalline silicon layer310. Moreover, the contact plug CP3is electrically separated from the polycrystalline silicon layer330. That is, the polycrystalline silicon layer330is electrically separated from the shunt interconnect270.

Now, the replica cell array RCA will be described. Now, with reference toFIGS. 28 and 29, description will be given of the sectional structure of the replica cell array RCA and third element region group AAG3.FIGS. 28 and 29are sectional views taken along lines X6-X6′ and Y4-Y4′ inFIG. 14.

As shown in the figures, the configuration of the third element region group AAG3is the same as that of the prime cell array PCA. That is, the isolation region STI is formed in the p-type well region202. The element regions AA are each surrounded by the isolation region STI. The gate insulating film300is formed on the element region AA of the p-type well region201. The gate electrodes of the memory cell transistor MT and select transistor ST of the replica cell are formed on the gate insulating film300.

In the memory cell transistor MT, the polycrystalline silicon layer310is separated into parts each located between the adjacent element regions AA. The polycrystalline silicon layer310thus functions as a floating gate (FG). On the other hand, the polycrystalline silicon layer330connects the adjacent element regions AA together and thus functions as control gates (word lines WL).

In the select transistor ST, the polycrystalline silicon layers310and320each connect the adjacent element regions AA together. The polycrystalline silicon layers310and330function as replica select gate lines RSG. However, only the polycrystalline silicon layer310substantially functions as the replica select gate lines.

The polycrystalline silicon layer330is connected to the control gate of the prime cell PC; The polycrystalline silicon layer330constitutes the control gate of the memory cell transistor. On the other hand, the polycrystalline silicon layers310and330constituting the replica select gate line RSG in the replica cells RC are separated from the polycrystalline silicon layers310and330constituting the select gate line SG in the prime cell PC, at the boundary between the prime cell array PCA and the replica cell array RCA.

The impurity diffusion layer340is formed in the surface of the p-type well region202located between the adjacent gate electrodes. The impurity diffusion layer340is shared by the adjacent transistors.

As preciously described, the replica cell RC, including the memory cell transistor MT and the select transistor ST is formed to have the relationship described below. The select transistors ST in the adjacent replica cells RC are adjacent to each other. The memory cell transistors MT in the adjacent replica cells RC are adjacent to each other. The impurity diffusion layer340is shared by the adjacent select transistors ST or memory cell transistors MT. Accordingly, if the select transistors ST are adjacent to each other, the two adjacent replica cells RC and RC are arranged symmetrically with respect to the impurity diffusion layer340shared by the two select transistors ST and ST. In contrast, if the memory cell transistors MT are adjacent to each other, the two adjacent replica cells RC and RC are arranged symmetrically with respect to the impurity diffusion layer340shared by the two memory cell transistors MT and MT.

The shunt region270of the select gate line SG is formed on the inter-level insulating film360. However, the shunt interconnect270is electrically separated from the polycrystalline silicon layers310and330constituting the replica select gate line RSG. The metal interconnect layers280and290are formed on the inter-level insulating film380and function as a replica write global bit line and a replica read global bit line.

Now, with reference toFIGS. 28 and 30, description will be given of the sectional structure of the stitch region SA3in the replica cell array RCA.FIG. 30is a sectional view taken along line Y5-Y5′ inFIG. 14.

As shown in the figures, the shunt regions SA4of the replica select gate lines RSG0to RSG(4m−1) and the element regions AA are formed in the stitch region SA3. The structure of the shunt region SA4is the same as that of the shunt region SA2of the select gate line SG (seeFIGS. 27 and 30). That is, the polycrystalline silicon layer330and the inter-gate insulating film320are removed to expose the polycrystalline silicon layer310; the polycrystalline silicon layer330and inter-gate insulating film320constitute a part of the replica select gate line RSG. The contact plug CP3is formed in contact with the polycrystalline silicon layer310in this region. The contact plug CP3is electrically separated from the polycrystalline silicon layer330by an insulating film331. The contact plug CP3is formed so as to extend from the surface of the inter-level insulating film350to the polycrystalline silicon layer310.

Further, the element region AA is formed in the switch region SA3. The contact plug CP8, reaching the element region AA, is formed in the inter-level insulating film350(seeFIG. 28). The metal interconnect layer400is formed on the inter-level insulating film350. The metal interconnect layer400connects the contact plugs CP3and CP8together. The polycrystalline silicon layer310, constituting the replica select gate line RSG, is connected to the p-type well region202via the contact plugs CP3and CP8and metal interconnect layer400.

The inter-level insulating films360and370are sequentially formed on the inter-level insulating film350. The shunt interconnect270is formed on the inter-level insulating film370. The word lines WL0to WL(4m−1) are formed in the stitch region SA3. The shunt interconnects270and the word lines WL0to WL(4m−1) are connected to the write decoder20through the stitch region SA3. On the other hand, the polycrystalline silicon layers310and330, constituting the replica select gate lines RSG0to RSG(4m−1), are formed only in the replica cell array RCA.

Now, with reference toFIGS. 31 to 34, description will be given of the configuration of the current source circuit87, provided in the discharge circuit81in the read control circuit80.FIG. 31is a plan view of the current source circuit87.FIGS. 32 to 34are sectional views taken along lines X7-X7′, Y6-Y6′, and Y7-Y7′, respectively.

As shown in the figures, as in the case of the memory cell array10, the n-type well region201is formed in the surface region of the p-type semiconductor substrate200. The p-type well region202is formed in the surface region of the n-type well region201. A plurality of the isolation regions STI are formed in the surface of the p-type well region202. The element regions AA are each a stripe-shaped region which is surrounded by the isolation region STI and in which a longitudinal direction extends along the first direction. Stripe-shaped gate electrodes410and420are formed on the p-type well region202so as to stride the plurality of element regions AA along the second direction, which is orthogonal to the first direction. The gate electrodes410and420function as the gate electrodes of MOS transistors87-1and87-2, respectively. The gate electrodes410and420have a stacked structure similar to that of the select transistors ST in the prime cell PC and replica cell RC. That is, the gate electrode410comprises a polycrystalline silicon layer412formed on the p-type well region202via an inter-gate insulating film411and a polycrystalline silicon layer414formed on the polycrystalline silicon layer412via an inter-gate insulating film413. The polycrystalline silicon layers412and414are connected together between the adjacent element regions AA. The polycrystalline silicon layer412substantially functions as a gate electrode. An impurity diffusion region480is formed in the surface of the p-type well region202; the impurity diffusion layer480functions as a source and drain regions of the MOS transistors87-1and87-2. The impurity region430is shared by the source region of the MOS transistor87-1and the drain region of the MOS transistor87-2.

A plurality of MOS transistors are formed on the plurality of element regions AA. However, only several of the plurality of MOS transistors function as the MOS transistors87-1and87-2. The other MOS transistors are dummies and do not have the substantial functions of the current source circuit87.

The gate electrodes410and420are drawn to an end of the current source circuit87to form a region having the same structure as that of the shunt regions SA2and SA4of the prime cell PC and replica cell RC. That is, in the isolation region STI, the gate electrodes410and420are formed to be winder with the polycrystalline silicon layers414and424and inter-gate insulating films413and423removed.

The inter-level insulating film350is formed on the p-type well region202so as to cover the above group of MOS transistors. Contact holes CP9and CP10are formed in the inter-level insulating film350; the contact holes CP9and CP10reach the impurity diffusion layer480in the MOS transistors87-1and87-2. The contact holes CP9are connected to the drain of the MOS transistor87-1and to the drains of the dummy MOS transistors on the same row as that on which the MOS transistor87-1is located. On the other hand, the contact holes CP10are connected to the source of the MOS transistor87-2and to the sources of the dummy MOS transistors on the same row as that on which the MOS transistor87-2is located. Moreover, in the region from which the polycrystalline silicon layers414and424and inter-gate insulating films413and423are removed, a contact plug CP11reaching the polycrystalline silicon layers412and422is formed in the inter-level insulating film350.

Island-shaped metal interconnect layers430are formed on the inter-level insulating film350. The metal interconnect layers430, isolated from one another, are each contact with the contact plug CP9or CP10. Moreover, a metal interconnect layer470is formed on the inter-level insulating film350so as to be connected to the contact plugs CP11. That is, the polycrystalline silicon layer412in the gate electrode410is electrically connected to the polycrystalline silicon layer422in the gate electrode420Via the contact plug CP11and metal interconnect layer470.

The inter-level insulating film360is formed on the inter-level insulating film350so as to cover the metal interconnect layers430and470. Contact plugs CP11and CP12are formed in the inter-level insulating film360; the contact plug CP11is in contact with the metal interconnect layer430connected to the contact plug CP9and the contact plug CP12is in contact with the metal interconnect layer430connected to the contact plug CP10.

Stripe-shaped metal interconnect layers440,450, and460are formed on the inter-level insulating film360; in the metal interconnect layers440,450, and460, the longitudinal direction extends along the first direction. The metal interconnect layer440is in contact with the contact plug CP11electrically connected to the MOS transistor87-1. The metal interconnect layer450is in contact with the contact plug CP12electrically connected to the MOS transistor87-2. The metal interconnect layer460is in contact with the contact plugs CP11and CP12connected to the dummy MOS transistors. The metal interconnect layer440is connected to the replica read global bit line R_RGBL. The metal interconnect layer450is connected to the ground potential. The metal interconnect layer370is formed on the inter-level insulating film360so as to cover the metal interconnect layers440,450, and460.

As described above, the current source circuit87has a configuration similar to that of the memory cell block BLK in the memory cell array10. A part of the memory cell block can be diverted to the current source circuit87. In this case, the memory cell transistor MT and the select transistor ST can each function as the MOS transistor87-1or87-2of the current source circuit87. The metal interconnect layer220and local bit lines in the memory cell array10can be used as the metal interconnect layer430and metal interconnect layers440,450, and460, respectively, in the current source circuit87.

Now, with reference toFIG. 35, description will be given of operations of the 2Tr flash memory3configured as described above.FIG. 35is a timing chart of a reset signal Reset, a data signal, VPI, and VNEGPRG. In the description below, the following state is defined as the state in which binary 1 has been written: no electrons are injected into the floating gate and the threshold voltage is negative. The following state is defined as the state in which binary 0 has been written: electrons are injected into the floating gate and the threshold voltage is positive.

First, an initial operation will be described with reference toFIG. 36. The initial operation is performed before a data write, read, or erase operation. The initial operation is performed before time t1.FIG. 36is a circuit diagram of the write selector50, write circuit60, and switch group100corresponding to the write global bit lines WGBL0and WGBL1during the initial operation. In the description below, the gates of the MOS transistors52and53in the select circuit51which correspond to the write global bit lines WGBL0to WGBL(2n−1) will be called nodes B0to B(2n−1) and A0to A(2n−1). The gates of the MOS transistors52and53in the select circuit51which correspond to the replica write global bit lines R_WGBL0and R_WGBL1will be called nodes B0′ and B1′ and A0′ and A1′.FIG. 36shows only the circuit block corresponding to the write global bit lines WGBL0and WGBL1. The figure can be changed to one corresponding to the replica cell array RCA by replacing the write global bit lines WGBL0and WGBL1with the replica write global bit lines R_WBGL0and R_WGBL1.

In the initial operation, VPI and VNEGPRG are set to 0 V. The reset signal Reset is set to Vcc1(=3 V). Then, the reset transistor102in the switch group100is turned on. Consequently, VNEGPRG=0 V is provided to the input nodes of all the latch circuits61. Then, since the lower power supply voltage of the inverters62and63is VNEGPRG=0 V, the input nodes of all the latch circuits61are set to 0 V. The output nodes of all the latch circuits61are set to Vcc1. Then, the nodes B0to Bn and B0′ and B1′ are set to 0 V. The nodes A0to An and A0′ and A1′ are set to Vcc1. Therefore, in all the select circuits51, the MOS transistor52is turned off, whereas the MOS transistor53is turned on. As result, the source of the MOS transistor53provides 0 V to the write global bit lines WGBL0to WGBLn and to the replica write global bit lines R_WGBL0and R_WGBL1.

As described above, in the initial operation, 0 V is provided to the input node of the latch circuit.

Now, a data latch operation will be described with reference toFIG. 37. The data latch operation inputs write data to each latch circuit61before a data write operation. The data latch operation is performed between time t1and time t2inFIG. 35.FIG. 37is a circuit diagram of the write selector50, write circuit60, and switch group100corresponding to the prime cell array PCA during the data latch operation.

Before the data latch operation, the reset signal Reset is set to 0 V. Write data is input to one end of the MOS transistor101corresponding to each of the write global bit lines WGBL0to WGBL(2n−1). For a 0 write operation (electrons are injected into the floating gates), 0 V is applied to one end of the current path in the MOS transistor101. For a 1 write operation (electrons are not injected into the floating gates), 3 V is applied to one end of the current path in the MOS transistor101. Further, VPI and VNEGPRG remain at 0 V. Since the reset signal Reset is set to 0 V, all the MOS transistors102are turned off. All the MOS transistors101are on.

In the example inFIG. 37, binary 0 is written to the memory cells connected to the write global bit line WGBL0, whereas binary 1 is written to the memory cells connected to the write global bit line WGBL1.

Focusing on the write global bit line WGBL0, description will be given of an operation of writing binary 0. As shown inFIG. 37, 0 V is provided to one end of the current path in the MOS transistor101. However, since the gate voltage of the MOS transistor is 0 V, the MOS transistor101is in a cutoff state. Accordingly, the data in the latch circuit61remains the same as that during the initial state. Consequently, the node A0is at Vcc1and the node B0is at 0 V. Thus, in the select circuit51corresponding to the write global bit line WGBL0, the MOS transistor53is turned on, while the MOS transistor52is turned off. The source of the MOS transistor53provides VNEGPRG=0 V to the write global bit line WGBL0.

Now, Focusing on the write global bit line WGBL1, description will be given of an operation of writing binary 1. As shown inFIG. 37, 3 V is provided to one end of the current path in the MOS transistor101. However, since the MOS transistor is on, 3 V reaches the input node of the latch circuit. Then, since VNEGPRG=0 V, the potential of the node A1changes from Vcc1to 0 V. The potential of the node B1changes from 0 V to Vcc1. Thus, in the select circuit51corresponding to the write global bit line WGBL1, the MOS transistor53is turned off, while the MOS transistor52is turned on. The source of the MOS transistor52provides VPI=0 V to the write global bit line WGBL1.

When data is stored in the 2Tr flash memory, all the replica cells are unselected for a write operation. Accordingly, the operation of the write selector50, write circuit60, and switch group100corresponding to the replica write global bit lines R_WGBL0and R_WGBL1is the same as that performed in connection with the write global bit line WGBL1in the prime cell array PCA. That is, 3 V is provided to one end of the current path in the MOS transistor101. As a result, in the select circuit51, the MOS transistor52is turned on. Thus, the source of the MOS transistor52provides VPI=0 V to the replica write global bit lines R_WGBL0and R_WGBL1.

As described above, for the data latch operation, the data in the latch circuit corresponding to the memory cell to which binary 1 is written is inverted from the initial state. Specifically, for a 0 write operation (electrons are injected), substantially no external data is input. For a 1 write operation (no electrons are injected; unselect), external data is loaded.

Now, a write operation will be described with reference toFIGS. 38 and 39. Data is written to all the memory cell blocks on the same row at a time. However, in each memory cell block, data is simultaneously written to two memory cells: the prime cell connected the local bit line LBL0or LBL1and the prime cell connected the local bit line LBL2or LBL3. Further, binary 1 is always written to the replica cells connected to the selected word line. In other words, the data retained in the replica cells cannot be rewritten.

The write operation is started at time t4.FIG. 38is a circuit diagram of the prime cell array PCA, write selector50, write circuit60, and switch group100during the write operation.FIG. 39is a circuit diagram of the replica cell array RCA, write selector50, write circuit60, and switch group100during the write operation. InFIG. 38, data is written to the memory cell transistors MT connected to the word line WL0and local bit lines LBL0and LBL2. The binary 0 is written to the memory cell transistor MT connected to the local bit line LBL0. The binary 1 is written to the memory cell transistor MT connected to the local bit line LBL2. In other words, the memory cells connected to the local bit line LBL0are selected. The memory cells connected to the local bit line LBL2are unselected.

Before the write operation, the reset signal Reset remains at 0 V. At time t3, VNEGPRG is set to VBB1(=−6 V), and at time t4, VPI is set to VBB2(=−3.5 V). In response to an instruction from the write state machine120, the voltage generator130outputs the negative potentials VBB1and VBB2. VPI may be at a negative potential VBB3instead of VBB2.

Then, the lower power supply voltage of the inverters62and63in the latch circuit61changes from 0 V to VBB1. Consequently, the potential of the nodes B0, A1, and B1′ changes from 0 V to VBB1. In the select circuit51corresponding to the write global bit line WGBL0, the MOS transistor53is turned on. In the select circuits51corresponding to the write global bit line WGBL1and replica write global bit lines R_WGBL0and R_WGBL1, the MOS transistor52is turned on. The source potentials of the MOS transistors52and53are VPI=VBB2and VNEGPRG=VBB1, respectively. Accordingly, the write global bit lines WGBL0and WGBL1is provided with VBB1and VBB2, respectively. The replica write global bit lines R_WGBL0and R_WGBL1are provided with VBB2.

The write decoder20selects the word line WL0and applies the positive voltage VPP (10 V) to the selected word line WL0. The write decoder20also applies the negative voltage VPP1(−6 V) to all the select gate lines SG0to SG(4m−1). Moreover, the write decoder20provides VBB1to the substrate (p-type well region202) in which the memory cells are formed. All the replica select gate lines RSG0to RSG(4m−1) are set to the same potential as that of the p-type well region202, that is, the negative potential VBB1.

Further, of the two write column select lines connected to the first column selector WCS corresponding to the memory cell block BLK including the selected word line WL0, the write column select line WCS0is selected. This turns on the MOS transistors11and13in the first column selector WCS. As a result, the write global bit line WGBL0is electrically connected to the local bit line LBL0. The write global bit line WGBL1is electrically connected to the local bit line LBL2. Moreover, the replica write global bit line R_WGBL0is electrically connected to the local bit line LBL0. The replica write global bit line R_WGBL1is electrically connected to the local bit line LBL2.

The write column select lines are all unselected which are connected to the write selector WSEL corresponding to the memory cell block BLK free from the selected word line WL0. Thus, the MOS transistors11to14in the first column selector WCS are turned off which transistors correspond to the memory cell block BLK not including the selected word line. The column decoder40unselects all the read column select lines RCSL0to RCSL(4m−1). This turns off the MOS transistors15to18in all the second column selector RCS. Therefore, the read global bit line RGBL and the replica read global bit line R_RGBL are electrically separated from the local bit lines LBL0to LBL3.

As a result, in the prime cell array PCA, the write global bit line WGBL0provides the write voltage (VBB1), via the MOS transistor11in the first column selector WCS, to the local bit line LBL0in the memory cell block BLK including the selected word line WL0. Moreover, the write global bit line WGBL1provides the write inhibition voltage VPI (VBB2), via the MOS transistor13, to the local bit line LBL2in the memory cell block BLK including the selected word line WL0. On the other hand, in the replica cell array, the replica write global bit line R_WGBL0provides the write inhibition voltage VPI, via the MOS transistor13in the first column selector WCS, to the local bit line LBL0in the memory cell block BLK including the selected word line WL0. Further, the replica write global bit line R_WGBL1provides the write inhibition voltage VPI, via the MOS transistor13in the first column selector WCS, to the local bit line LBL2in the memory cell block BLK including the selected word line WL0.

As a result, there is an insufficient potential difference between the gate and channel of the memory cell transistor MT connected to the write global bit line WGBL1and word line WL0(VPP−VBB2=6.5 V). Consequently, no electrons are injected into the floating gate of the memory cell transistor. That is, the threshold voltage for the prime cells PC maintains the negative value. Similarly, no electrons are injected into the memory cell transistors MT connected to the replica write global bit lines R_WGBL1and R_WGBL1and word line WL0. The threshold voltage for the replica cells RC maintains the negative value.

In contrast, there is a sufficient potential difference between the gate and channel of the memory cell transistor MT connected to the write global bit line WGBL0and word line WL0(VPP−VBB1=16 V). Consequently, FN tunneling causes electrons to be injected into the floating gate of the memory cell transistor. This changes the threshold voltage for the memory cell transistor MT to a positive value. That is, the binary 0 is written.

As described above, data is written to the memory cell transistors for one page at a time. Only the prime cell array PCA is substantially used to store data, whereas the binary 0 is always written to the replica cell array RCA. That is, the write operation does not change the threshold voltage for the replica cells RCs, with substantially no data written to the replica cells RC.

Now, an erase operation will be described with reference toFIG. 40.FIG. 40is a circuit diagram of the prime cell array PCA, write selector50, write circuit60, and switch group100during the erase operation. The state of the replica cell array during the erase operation is similar to that shown inFIG. 40. Data is erased from all the memory cells having a common well. The erase operation is performed by drawing electrons out of the floating gate on the basis of FN tunneling.

For the erase operation, the reset signal Reset is set to 0 V, and 3 V is applied to one end of the current path in the MOS transistors91corresponding to all the write global bit lines WGBL0to WGBL(2n−1) and all the replica write global bit lines R_WGBL0and R_WGBL1. VPI is Cvv1and VNEGPRG is 0 V. Since the reset signal Reset is set to 0 V, all the MOS transistors92are turned off. All the MOS transistors91are turned on. Accordingly, 3 V is provided to the input node of the latch circuit51. Then, since VNEGPRG=0 V, the potential of the nodes A0to An, A0′, and A1′ is set to 0 V. The potential of the nodes B0to Bn, B0′, and B1′ is set to Vcc1. Consequently, in all the select circuits51, the MOS transistors42and43are brought into the cutoff state. Therefore, all the write global bit lines WGBL0to WGBL(2n−1) and all the replica write global bit lines R_WGBL0and R_WGBL1are electrically separated from the latch circuit51, VNEGPRG, and VPI. These global bit lines thus float.

The column decoder40then unselects all the write column select lines WCSL0to WCSL(2m−1) and read column select lines RCSL0to RCSL(4m−1). The column decoder40makes these column select lines low. This turns off all the MOS transistors11to18.

The write decoder20applies the negative voltage VBB1to all the word lines WL0to WL(4m−1) in the selected block. The write decoder20applies the positive voltage VPP to all the select gate lines SG0to SG(4m−1) in the selected block. The write decoder20further applies VPP to the p-type well region202in which the memory cell array is formed. Therefore, the potential of the replica select gate lines RSG0to RSG(4m−1) is set to VPP.

As a result, FN tunneling causes electrons to be drawn out of the floating gate of the memory cell transistor in the memory cell MC and carried to the semiconductor substrate. This makes negative the threshold voltage of all the prime and replica cells PC and RC connected to the word lines WL0to WL(4m−1). The data is thus erased.

As described above, the data is erased at a time.

Now, a read operation will be described with reference toFIGS. 41 and 42.FIG. 41is a circuit diagram of the prime cell array PCA and read unit71in the 2Tr flash memory3.FIG. 42is a circuit diagram of the replica cell array RCA and read control circuit80.FIG. 41shows that the data is read from the memory cell transistor MT connected to the local bit line LBL0and word line WL0.FIG. 42shows how the replica cell array RCA operates during the data read operation.

In the present embodiment, the data is read only from the prime cell array PCA and not from the replica cell array RCA. The data is read from one prime cell PC per memory cell block BLK. However, if a plurality of read global bit lines RGBL are present per memory cell block BLK, the data corresponding to the number of read global bit lines is read.

First, as shown inFIG. 41, the select gate decoder30selects the select gate line SG0(high: Vc=3 V). Further, the write decoder20unselects all the word lines WL0to WL(4m−1) (0 V) and sets the potential of the p-type well region202to 0 V. Moreover, the source line driver90sets the potential of the source lines to 0 V.

The column decoder40then selects one RCSL0of the four read column select lines RCSL0to RCSL3connected to the second column selector RCS corresponding to the memory cell block BLK including the selected select gate line SG0. This turns on the MOS transistor15in the second column selector RCS corresponding to the memory cell block BLK including the selected select gate line SG0. Further, the signal ISO goes high to turn on the MOS transistor72. This electrically connects the read global bit line RGBL0to the local bit line LBL0. However, the read column select lines are all unselected which are connected to the second column selector RCS corresponding to the memory cell block BLK not including the selected select gate line SG0.

The column decoder40unselects all the write column select lines WCSL0to WCSL(2m−1). This turns off all the four MOS transistors11to14in all the write column select lines WCSL0to WCSL(2m−1). Therefore, the write global bit line WGBL is electrically separated from the local bit lines LBL0to LBL3.

As a result, one of the local bit lines LBL0to LBL3per memory cell block BLK is connected to the sense amplifier74via the second column selector RCS, read global bit line, and MOS transistor72.

Then, the sense amplifier74amplifies a variation in the potential across the read global bit line RGBL to allow the data to be read. That is, for example, 3.0 V is applied to the read global bit line RGBL0. Then, if the binary 1 is written to the memory cell transistor MT connected to the selected word line WL0and the selected local bit line LBL0, a current flows from the read global bit line RGBL to the corresponding source line. On the other hand, if the binary 0 is written to the memory cell transistor MT, no current flows.

In the replica cell array RCA, the replica select gate lines RCA0to RCA(4m−1) are set to 0 V. Consequently, the data is not read from the replica cells RC connected to the selected word line WL0.

The read operation will be described in detail with reference toFIGS. 43 and 44.FIG. 43is a flowchart of the read operation.FIG. 44is a timing chart of various signals during the read operation. For simplification, the read global bit lines RGBL0to RGBL(n−1) will be simply referred to as RGBL.

First, before the read operation, the read global bit line RGBL and the replica read global bit line R_RGBL are connected to one of the local bit lines LBL0to LBL3. Further, the discharge circuit81is turned off (MOS transistors87-1and87-2are turned off; seeFIG. 12). Moreover, the bias voltage BIAS goes high, and signals /PRE-cnt and /PRE go low. Consequently, the following MOS transistors are turned on: the MOS transistors Q1and Q2in the first precharge circuit73and the MOS transistors Q11and Q12in the second precharge circuit83. Furthermore, the signal ISO goes high to turn on the MOS transistor82(step S10, time t1). Thus, the first and second precharge circuits73and84precharge the read global bit line RGBL and the replica read global bit line R_RGBL, respectively (step S11).

The first and second precharge circuits73and84have the same precharge capability (voltage supply capability). A parasitic capacitance present on the read global bit line RGBL is smaller than that present on the replica read global bit line R_RGBL. Accordingly, the rate of increase in the potential across the read global bit line RGBL is higher than that in the potential across the replica read global bit line R_RGBL. Thus, the potential across the read global bit line RGBL raises to a data determination threshold voltage Vth for the sense amplifier74more rapidly than that across the replica read global bit line R_RGBL. In the example inFIG. 44, it takes the potential across the replica read global bit line R_RGBL a time Δt1to reach Vth (time t3). In contrast, it takes the potential across the read global bit line RGBL a time Δt2(<Δt1) to reach Vth (time t2).

The signal processor84in the read control circuit80monitors the potential VRBL across the replica read global bit line R_RGBL (seeFIG. 4). While the potential VRBL is lower than Vth, the precharge signal /PRE is continuously asserted (low). When the potential VRBL reaches Vth (step S12; time t3), the precharge signal /PRE is negated (made high). Making the precharge signal /PRE high finishes precharging the read global bit line RGBL (step S13; time t4). As previously described, VRBL is higher than Vth at this time. After time t3, the precharge signal /PRE-cnt is also made high to finish precharging the replica read global bit line R_RGBL.

Then, the select gate decoder30selects one of the select gate lines SG to turn on the discharge circuit81(step S14, time t6). When the discharge circuit81is turned on, the voltage generator88outputs the constant voltage Vref. The output of the voltage Vref turns on the MOS transistors87-1and87-2in the current source circuit87.

When the select gate decoder30selects the select gate line SG, the data retained in the corresponding prime cell PC is read onto the corresponding read global bit line RGBL. Further, the discharge circuit81is simultaneously turned on to cause the current source circuit87to discharge the replica read global bit line R_RGBL (step S15, time t6). On this occasion, all the replica select gate lines RSG are at 0 V.

If the prime cells PC connected to the selected select gate line retain the binary 0, the potential VBL across the read global bit line RGBL maintains the value of the precharge potential. On the other hand, if the prime cells RC retain the binary 1, the potential VBL lowers from the precharge potential value to 0 V. The potential VRBL across the replica read global bit line R_RGBL lowers toward 0 V regardless of the threshold voltage for the replica cells RC. The rate of decrease in the potential across the read global bit line RGBL is higher than that in the potential across the replica read global bit line R_RGBL. Consequently, the potential across the read global bit line RGBL connected to the prime cells retaining the binary 1 lowers to the data determination threshold voltage Vth for the sense amplifier74more rapidly than that across the replica read global bit line R_RGBL. This is because the parasitic capacitance present on the read global bit line RGBL is smaller than that present on the replica read global bit line R_RGBL, so that the read global bit line RGBL requires a shorter time to be discharged than the replica read global bit line R_RGBL. In the example inFIG. 44, it takes the potential across the replica read global bit line R_RGBL a time Δt3to change from the precharge level to Vth (time t8). In contrast, it takes the potential across the read global bit line RGBL a time Δt4(<Δt3) to change from the precharge level to Vth (time t7).

While the potential VRBL is higher than Vth, the signal processor84in the read control circuit80continuously negates the read end signal Read-end (low). When the potential VRBL reaches Vth (step S16, time t8), the read end signal Read-end is asserted (made high; step S17, time t8). When the read end signal Read-end is made high, the sense amplifier74establishes read data on the basis of the potential VBL at that point in time (step S18, time t9). More specifically, the data stored in a flip flop at time t9is established as read data. That is, at time t9, the sense amplifier74determines the data to be “0” if the potential VBL exceeds Vth. The sense amplifier74determines the data to be “1” if the potential VBL does not exceed Vth. As previously described, if the prime cells PC retain the binary 1, the potential VBL is lower than Vth when the read end signal Read-end is high.

At time t10, the sense amplifier74outputs the read data established at time t9, as an output signal OUT.

The above flash memory can produce effects (1) to (10) described below.

(1) Data Read Accuracy can be Improved (Part I)

The above configuration can improve the accuracy with which data is read. This will be described with reference toFIG. 45.FIG. 45is a timing chart of the precharge signal /PRE, the potential across the select gate line SG, the read end signal Read-end, the potential across the read global bit line RGBL during a 0 read operation, and the potential across the read global bit line RGBL during a 1 read operation.

(1-1) Binary 0 Read Operation

First, a 0 read operation will be described. The conventional read method may provide an excessively short precharge time for the bit line. In the example inFIG. 45, precharging may end at time t2before the potential across the bit line rises to the data determination threshold voltage Vth for the sense amplifier. In this case, the bit line potential (precharge potential) is lower than Vth. Consequently, even if the memory cells retain the binary 0, the sense amplifier erroneously determines the read to be binary 1.

However, with the above configuration, precharging of the read global bit line ends after the replica read global bit line reaches Vth. At this time, the potential across the read global bit line is ensured to be higher than Vth. Consequently, the read data can be precisely determined. This will be described with reference toFIG. 46.FIG. 46is a schematic circuit diagram of the prime cell array PCA, replica cell array RCA, read circuit70, and read control circuit80during precharging.

The first precharge circuit73precharges the read global bit line RGBL. The second precharge circuit83precharges the replica read global bit line R_RGBL. The first and second precharge circuits have the same precharge capability. Therefore, the time required for precharging depends on the parasitic capacitance present on the read global bit line RGBL and replica read global bit line R_RGBL. A larger parasitic capacitance results in a longer time required for precharging.

As previously described, the parasitic capacitance CRCof each of the local bit lines LBL0to LBL3in the prime cell array PCA is smaller than that of each of the local bit lines LBL0to LBL3in the replica cell array RCA. That is, the total parasitic capacitance CR—RGBLpresent on the replica read global bit line R_RGBL is larger than the total parasitic capacitance CRGBLpresent on the read global bit line RGBL. Therefore, the time required to precharge the replica read global bit line R_RGBL is longer than that required to precharge the read global bit line RGBL.

The signal processor84generates a precharge signal /PRE on the basis of the potential across the replica read global bit line R_RGBL. More specifically, the precharge signal /PRE is negated after the potential across the replica read global bit line R_RGBL has exceeded the data determination threshold voltage for the sense amplifier74. In other words, the precharge signal /PRE is not negated until the potential across the bit line (replica read global bit line R_RGBL) requiring the longest time for precharging exceeds Vth. Accordingly, when the precharge signal /PRE is negated, the potentials of all the bit lines (read global bit lines and replica read global bit lines) are higher than Vth, the bit lines being included in the memory cell array10. This enables the potentials across the bit lines to be reliably precharged.

The above effect also results from the fact that the replica cell array RCA is farthest from the select gate decoder30, which controls the signal ISO. The data read operation, more specifically, the precharge operation, is not started until the signal ISO is made high to turn on the isolating MOS transistors72and82. Thus, since the isolating MOS transistor82in the read control circuit80is farther from the select gate decoder30than all the MOS transistors72in the read circuit70, the MOS transistor82is turned on after all the MOS transistors72are turned on. That is, the replica read global bit line R_RGBL is precharged after precharging of all the read global bit lines RGBL has been started. The signal processor84controls the precharge signal /PRE with reference to the potential of the replica read global bit line R_RGBL, which starts being precharged latest. This makes it possible to reliably set the potential across the read global bit line RGBL equal to or higher than Vth, the read global bit line RGBL starting being precharged earlier than the replica read global bit line R_RGBL.

Now, a 1 read operation will be described. The conventional read method may use an excessively short time for the read operation. In the example inFIG. 45, reading data from the memory cells may be ended at time t5before the potential across the bit line lowers to the data determination threshold voltage for the sense amplifier. In this case, the bit line potential is higher than Vth. Consequently, even if the memory cells retain the binary 1, the sense amplifier erroneously determine that the read binary 0.

However, with the above configuration, reading data from the prime cells is finished after the replica read global bit line starts being discharged and before the potential across the replica read global bit line lowers to Vth. By this time, the potential across the read global bit line has already reliably decreased below Vth. Consequently, the read data can be precisely determined. This will be described with reference toFIG. 47.FIG. 47is a schematic circuit diagram of the prime cell array PCA, replica cell array RCA, read circuit70, and read control circuit80during precharging.

The selected prime cells PC discharge the read global bit line RGBL. The discharge circuit81discharges the replica read global bit line R_RGBL. The current source circuit87in the discharge circuit81has the same configuration as that of the memory cells. Accordingly, the current source circuit87has the same discharge capability as that of the memory cells. Therefore, the time required for precharging depends on the parasitic capacities present on the read global bit line RGBL and replica read global bit line R_RGBL. A larger parasitic capacitance results in a longer discharge time.

As previously described, the capacitance CR—RGBLis larger than the parasitic capacitance CRGBL. Consequently, the time required to discharge the replica read global bit line R_RGBL is longer than that required to discharge the read global bit line RGBL.

The signal processor84generates a read end signal Read-end on the basis of the potential across the replica read global bit line R_RGBL. More specifically, the read end signal Read-end is asserted after the potential across the replica read global bit line R_RGBL has decrease below the data determination threshold voltage Vth for the sense amplifier74. In other words, the read end signal Read-end is not asserted until the potential across the bit line (replica read global bit line R_RGBL) requiring the longest time for discharging has decreased below VTh. Accordingly, by the time when the read end signal Read-end is asserted, the following potentials have already decreased below Vth: the potentials across the replica read global bit lines and all the read global bit lines to which the selected prime cells retaining the binary 1 are connected. In this manner, the read end signal Read-end can be asserted after the potential across the bit line from which the binary 1 has been read has reliably decreased below Vth.

(2) Data Read Accuracy can be Improved (Part II)

In the above configuration, the replica select gate lines RSG are separated from the select gate lines and connected to the p-type well region202. For the read operation, all the replica select gate lines RSG are set to 0 V. Accordingly, all the replica cells RC are off during the read operation. This configuration can prevent the replica cells RD from being used to discharge the replica read global bit line R_RGBL.

If the replica cells RC are used for discharging as in the case of the prior art, then naturally, the current supply capability available for discharging depends on the threshold voltage for the replica cells. The threshold voltage is determined by the rate of electrons injected into the floating gates. Consequently, in this case, disturbance may change the threshold voltage for the replica cells and thus the current supply capabilities of the replica cells available for discharging. This makes it difficult to always discharge the replica read global bit line R_RGBL at a fixed voltage change rate.

However, the present example of configuration can solve the above problem by avoiding using the replica cells for discharging. Instead, the current source circuit87discharges the replica read global bit line R_RGBL. Although the current source circuit87has the same configuration as that of the replica cells RC, the gate voltage is applied to its floating gate. Consequently, the current source circuit87can discharge the replica read global bit line R_RGBL at a fixed voltage change rate without being affected by the disturbance, which occurs with the replica cells RC. This serves to increase the data read accuracy.

(3) Data Read Speed can be Improved

In addition to (1), the data read speed can be improved. This will be described with reference toFIG. 45again. In the example inFIG. 45, precharging is carried out until the potential across the read global bit line RGBL substantially reaches VDD. Further, discharging is carried out until the potential across the read global bit line RGBL reaches 0 V. However, the effect (1) can also be produced by ending precharging and discharging at the times t3and t6, respectively, inFIG. 45. Specifically, even when precharging is ended at time t3, the potential across the read global bit line RGBL is higher than Vth at this time. Even when discharging is ended at time t6, the potential across the read global bit line RGBL is lower than Vth at this time. Accordingly, a precise read operation can also be performed by selecting the select gate to start discharging at time t3and ending discharging to establish read data at time t6. That is, no margins need to be provided for the precharge and discharge periods. This makes it possible to greatly improve the read operation.

(4) Effects (1) to (3) are Obtained without the Need to Complicate the Manufacturing Process.

The above configuration is provided with the replica cell array RCA and the read control circuit80. However, the replica cell array RCA has almost the same configuration as that of the prime cell array PCA. The second precharge circuit83in the read control circuit80has the same configuration as that of the first precharge circuit73in the read control circuit70. Moreover, the current source circuit87in the read control circuit80has almost the same configuration as that of the memory cell array10. Consequently, the replica cell array RCA and the read control circuit80can be manufactured during the same process as that in which the prime cell array PCA and the read circuit70are manufactured. Therefore, the above effects can be produced without the need to complicate the manufacturing process.

Further, the current source circuit87in the discharge circuit81has only to have two MOS transistors in order to provide sufficient functions. However, this may result in an isolated pattern to degrade the reliability of lithography. Accordingly, as described with reference toFIG. 31, the current source circuit87is desirably formed of a plurality of MOS transistors including dummy MOS transistors. Alternatively, since the current source circuit87is configured almost similarly to the memory cell array10, it may be placed inside the memory cell array10.

(5) Erroneous Write Operations can be Suppressed Without Reducing Write Speed.

In the above configuration, the flash memory3comprises the select circuit51provided for each bit line. The particular voltage is applied to the bit line depending on the data retained in the latch circuit61. For the 0 write operation (selected bit line), the negative write voltage VNEGPRG (VBB1) is applied to the bit line via the current path in the MOS transistor53. On the other hand, for the 1 write operation (unselected bit line), the write inhibition voltage VPI is applied to the bit line via the current path in the MOS transistor52. The voltage generator130can vary the voltage value of the write inhibition voltage VPI. In the description of the above example of configuration, VBB2or VBB3is used as the write inhibition voltage VPI. VBB3may have a larger or smaller value than VBB2. One of VBB2and VBB3which is optimum for prevention of erroneous write operations is provided as the write inhibition voltage VPI.

For example, when both lower and higher power supply voltages of the latch circuit63are set at negative values, a forward bias is applied to between the semiconductor substrate and the n-type well region of the p channel MOS transistor forming the inverter. This makes circuit operations unstable. However, the present example of configuration uses the select circuit51, including the two n channel MOS transistors52and53, formed on the same p-type well region. Thus, the select circuit51enables VNEGPRG and VPI, both of which may become negative, to be applied to the bit line.

This eliminates the need to vary another voltage, for example, the potential across the word line, in order to prevent erroneous write operations as in the prior art. Erroneous write operations can be suppressed by selecting either VBB2or VBB3as a write inhibition voltage and setting the optimum value for the write inhibition voltage.

Consequently, erroneous write operations can be suppressed without reducing the write speed. Further, the write inhibition voltage VPI can be varied among a plurality of values. This increases the degree of freedom in circuit configuration

(6) Write Operation can be Simplified.

The above configuration initializes the data in the latch circuit51during the initial operation before the write or erase operation. This makes the input to and an output from the latch circuit51to the low and high levels, respectively.

During the data latch operation, the MOS transistor101is provided with 0 V for the 0 write operation (selected bit line) and with 3 V for the 1 write operation (unselected bit line). However, the MOS transistor101is brought into the cutoff state for the 0 write operation. Consequently, externally provided binary 0 is not actually transferred to the latch circuit61. That is, the data in the latch circuit61is invariable. On the other hand, for the 1 write operation, the binary 1 is transferred to the latch circuit61via the current path in the MOS transistor101.

That is, as shown inFIG. 36, the present example of configuration performs the initial operation to initialize the data in the latch circuit61. For the 0 write operation (selected bit line), the select circuit51applies the write voltage VNEGPRG to the selected bit line on the basis of the initialized data. On the other hand, for the 1 write operation (unselected bit lines), the select circuit51applies the write inhibition voltage VPI to the unselected bit lines on the basis of externally input data instead of the initialized data.

Accordingly, the expression “the latch circuit51is initialized during the initial operation” can be changed to the expression “the binary 0 is input to all the latch circuits”. For the data write operation, external data may be input only if the binary 1 is written, that is, only if no electrons are injected into the floating gates, in other words, only for the unselected bit lines. No external data need be input if the binary 0 is written, that is, if electrons are injected into the floating gates, in other words, for the selected bit line. This makes it possible to simplify the write operation.

(7) Control of the Flash Memory can be Simplified.

In the above configuration, only the p channel MOS transistor101forms the transfer gate that transfers externally input write data to the latch circuit61. This transfer gate enables circuit area to be reduced compared to the transfer gate formed of a combination of an n channel MOS transistor and a p channel MOS transistor. Moreover, the gate of the p channel MOS transistor has only to be always set at the ground potential. The gate potential need not be controlled. This enables the simplification of control of the flash memory.

(8) Operation Speed of the Flash Memory can be Improved.

In the above configuration, the bit lines are hierarchical and include local bit lines and global bit lines (read global bit lines and write global bit lines). Specifically, a plurality of memory cells are connected to each of a plurality of local bit lines. A plurality of local bit lines are connected to each of the plurality of global bit lines. In the example inFIG. 3, 2(m−1) local bit lines (LBL0and LBL1or LBL2or LBL3) are connected to one write global bit line WGBL via the first column selector WCS. Four memory cells are connected to each local bit line LBL. Further, 4(m−1) local bit lines (LBL0to LBL3) are connected to one read global bit line RGBL via the second column selector RCS. Four memory cells are connected to each local bit line LBL.

For the write operation, only the local bit line LBL connected to the selected memory cells is connected to the write global bit line WGBL. The first column selector WCS electrically separates the local bit lines LBL to which the selected memory cells are not selected, from the write global bit lines WGBL. Accordingly, one write global bit line WGBL views only one local bit line containing the selected memory cells, that is, the four memory cells. Consequently, only these four memory cells MC contribute to the parasitic capacitance present on the write global bit line. The parasitic capacitance of the write global bit line is not contributed to by the unselected memory cells located on the same row as the selected memory cells and connected to the local bit lines LBL different from the one containing the selected memory cells. It is thus possible to sharply reduce the parasitic capacitance of the write global bit line. This also applies to the read operation.

As described above, it is possible to reduce the parasitic capacities of the write global bit line and read global bit line to improve the operation speed of the flash memory.

(9) Read Speed can be Improved.

The flash memory must handle relatively high voltages such as VPP, VBB1, and VBB2during the write operation. To meet this request, MOS transistors must be used which have a thick gate insulating film and which can withstand high voltages. In contrast, the voltages handled during the read operation are lower than those used during the write operation. Therefore, in view only of the read operation, it is desirable to use low withstand-voltage MOS transistors having a thin gate insulating film. Also in terms of the operation speed, low withstand-voltage MOS transistors are desirably used.

In this regard, in the above configuration, each local bit line is connected to the corresponding write global bit line and read global bit line. The memory cells are connected to the write circuit60Via the write global bit lines and to the read circuit70Via the read global bit lines. That is, the signal path for the write operation is different from that for the read operation. Therefore, in the signal path for the read operation, transistors with a thin insulating film can be used to form all the circuits except the second column selector RCS, which connects the read global bit lines to the local bit lines. As a result, the read operation speed can be improved.

(10) Reliability of Write Operations can be Improved.

As described above in (8), the bit lines are hierarchical. When the write path is focused on, a plurality of local bit lines are connected to one write global bit line. For the write operation, only one local bit line containing the selected memory cells is electrically connected to the write global bit lines. The other local bit lines are electrically separated from the write global bit lines. Consequently, the voltage corresponding to the write data is not applied to the local bit lines to which the selected memory cells are not connected. This effectively prevents the data from being erroneously written to the memory cells connected to these local bit lines. Therefore, the reliability of the write operation can be improved.

Now, description will be given of a semiconductor storage device according to a second embodiment of the present invention. The present embodiment corresponds to the first embodiment in which MOS transistors switch between the select gate lines and the replica select gate line. The configuration of all the components except the memory cell array is similar to that in the first embodiment. Accordingly, its description is omitted.FIG. 48is a circuit diagram of the memory cell array10provided in the 2Tr flash memory according to the present embodiment.FIG. 49is a circuit diagram of the memory cell array10, write decoder20, and select gate decoder30.

As shown in the figures, the memory cell array10according to the present embodiment corresponds to the configuration described in the first embodiment and which is varied as described below.(1) MOS transistors19-0to19-(4m−1) are provided between the prime cell array PCA and the replica cell array RCA in association with the select gate lines SG0to SG(4m−1), respectively.(2) One end of each of the select gate lines SG0to SG(4m−1) is connected to the select gate decoder30. The other end is connected to one end of the current path in the corresponding one of the MOS transistors19-0to19-(4m−1).(3) One end of each of the replica select gate lines RSG0to RSG(4m−1) is connected to the write decoder20. The other end is connected to the other end of the current path in the corresponding one of the MOS transistors19-0to19-(4m−1).(4) Gates of the MOS transistors19-0to19-(4m−1) are all connected to a select dummy line SDL.

Now, with reference toFIG. 50, description will be given of the planar structure of the memory cell array10according to the present embodiment.FIG. 50is a plan view of a particular region of the memory cell array10.

As shown in the figures, the internal configuration of the prime cell array PCA is similar to that in the first embodiment. The configuration of the third element region group AAG3in the replica cell array RCA is also similar to that in the first embodiment. The stitch region SA3in the replica cell array RCA is different from that in the first embodiment. The stitch region SA3in the replica cell array RCA has the same configuration as that of the stitch region SA1in the prime cell array PCA. The shunt interconnect270in the first embodiment is separated into two parts at the boundary between the prime cell array PCA and the replica cell array RCA. The separated part in the replica cell array functions as a shunt interconnect271for the replica select gate lines RSG0to RSG(4m−1). The boundary between the prime cell array PCA and the replica cell array RCA will be called a boundary region BR.

Now, the boundary region BR will be described. In the boundary region BR, the select gate lines SG0to SG(4m−1) and the replica select gate lines RSG0to RSG(4m−1) are removed. On the other hand, the word lines WL0to WL(4m−1) pass through the boundary region BR. The corresponding MOS transistors19-0to19-(4m−1) are formed in the region where the select gate lines SG0to SG(4m−1) and the replica select gate lines RSG0to RSG(4m−1) are removed. That is, the element regions AA are formed in which the longitudinal direction extends along the second direction. A stripe-shaped gate electrode311extending along the first direction is formed so as to stride two adjacent regions sandwiched by two word lines. The gate electrode311is connected to a stripe-shaped metal interconnect layer251extending along the first direction. The metal interconnect layer251functions as a select dummy line SDL.

One of source and drain of each of the MOS transistors19-0to19-(4m−1) connects, via contact plugs CP19and CP20and metal interconnect layers232and262, to the shunt interconnect270of the corresponding one of the select gate lines SG0to SG(4m−1). Moreover, the other of source and drain of each of the MOS transistors19-0to19-(4m−1) connects, via contact plugs CP21and CP22and metal interconnect layers233and263, to the shunt interconnect271of the corresponding one of the replica select gate lines RSG0to RSG(4m−1).

Now, description will be given of the sectional structure of the memory cell array10configured as described above.FIGS. 51 and 52are sectional views taken along lines X9-X9′ and Y8-Y8′ inFIG. 50.

As shown in the figure, the configuration of the prime cell array PCA is similar to that in the first embodiment, so that its description is omitted. Further, the configuration of the third element region group AAG3in the replica cell array RCA is the same as that in the first embodiment except that the shunt interconnect270is replaced with the shunt interconnect271. Accordingly, its description is omitted. Now, the stitch region SA3in the replica cell array RCS will be described.

As shown in the figures, the stitch region SA3has a configuration similar to that of the stitch region SA1. That is, the isolation region STI is formed in the p-type well region202. The polycrystalline silicon layers310and330are drawn out to the isolation region STI; the polycrystalline silicon layers310and330constitute the replica select gate line RSG. In the shunt region SA4, the polycrystalline silicon layer330and the inter-gate insulating film320are removed to expose the polycrystalline silicon layer310. The contact plug CP15is formed in contact with the polycrystalline silicon layer310in this region. The contact plug CP15is electrically separated from the polycrystalline silicon layer330by the insulating film331. The contact plug CP15is formed so as to extend from the surface of the inter-level insulating film350to the polycrystalline silicon layer310.

The metal interconnect layer231and the inter-level insulating film360are formed on the inter-level insulating film350. The metal interconnect layer231is provided for each contact plug CP15and connected to the corresponding contact plug CP15. A contact plug16is formed in the inter-level insulating film360. The contact CP16is provided for each metal interconnect layer360and connected to the corresponding metal interconnect layer231.

The metal interconnect layer261and the inter-level insulating film370are formed on the inter-level insulating film360. The metal interconnect layer261is provided for each contact plug CP16and connected to the corresponding contact plug CP16. A contact plug17is formed in the inter-level insulating film370. The contact CP17is provided for each metal interconnect layer261and connected to the corresponding metal interconnect layer261.

The metal interconnect layer271is formed on the inter-level insulating film370; the metal interconnect layer271functions as the shunt interconnect of the replica select gate line RSG. The metal interconnect layer271is connected to the corresponding contact plug CP17. The structure of the shunt region. SA4is the same as the configuration shown inFIG. 27.

Now, the sectional structure of the boundary region RB will be described. As shown inFIGS. 51 and 52, the MOS transistors19-0to19-(4m−1) are formed on the p-type well region202in the boundary region BR. That is, impurity diffusion layers341functioning as a source and a drain are formed in the surface region of the p-type well region202. The gate electrode (polycrystalline silicon layer)301is formed on the p-type well region202between the source and drain via the gate insulating film301. The contact plugs CP19and CP21are formed in the inter-level insulating film350for each of the MOS transistors19-0to19-(4m−1). The metal interconnect layers232and233are formed on the inter-level insulating film350for the contact plugs CP19and CP21, respectively. The contact plugs CP20and CP22are formed in the inter-level insulating film360for metal interconnect layers232and233, respectively. The metal interconnect layers262and263are formed on the inter-level insulating film360for the contact plugs CP20and CP22, respectively. Contact plugs CP23and CP24are formed in the inter-level insulating film360for metal interconnect layers262and263, respectively.

One of source and drain of each of the MOS transistors19-0to19-(4m−1) is connected, via the contact plugs CP19, CP20, and CP23and metal interconnect layers232and262, to the shunt interconnect270of the corresponding one of the select gate lines SG0to SG(4m−1). The other of source and drain of each of the MOS transistors19-0to19-(4m−1) is connected, via the contact plugs CP21, CP22, and CP24and metal interconnect layers233and263, to the shunt interconnect271of the corresponding one of the replica select gate lines RSG0to RSG(4m−1).

As described above, in the boundary region RB, the shunt interconnect270of each of the select gate lines SG0to SG(4m−1) is connected to the shunt interconnect271of the corresponding one of the replica select gate lines RSG0to RSG(4m−1) via the current path in the corresponding one of the MOS transistors19-0to19-(4m−1). The shunt interconnect270is connected to the select gate decoder30. The shunt interconnect271is connected to the write decoder20.

Now, description will be given of operations of the 2Tr flash memory3according to the present embodiment. The basic operation of the 2Tr flash memory3id similar to those in the first embodiment. Thus, in this case, the write, erase, and read operations will be described by focusing on the MOS transistors19-0to19-(4m−1).FIGS. 53 to 55are circuit diagrams showing how the write, erase, and read operations, respectively, are performed.

First, the write operation will be described with reference toFIG. 53. As shown the figure, for the write operation, the select dummy line SDL is made high (for example, Vcc=3 V or 0 V). Consequently, the MOS transistors19-0to19-(4m−1) are turned on to electrically connect the select gate lines SG0to SG(4m−1) to the replica select gate lines RSG0to RSG(4m−1), respectively.

Then, the writing decode20provides the negative voltage VBB1to the replica select gate lines RSG0to RSG(4m−1) and to the select gate lines SG0to SG(4m−1).

Now, the erase operation will be described with reference toFIG. 54. As shown in the figure, for the erase operation, the select dummy line SDL is also made high (>VPP). Consequently, the MOS transistors19-0to19-(4m−1) are turned on to electrically connect the select gate lines SG0to SG(4m−1) to the replica select gate lines RSG0to RSG(4m−1), respectively.

Then, the writing decode20provides the positive voltage VBB to the replica select gate lines RSG0to RSG(4m−1) and to the select gate lines SG0to SG(4m−1).

Now, the read operation will be described with reference toFIG. 55. As shown in the figure, for the read operation, the select dummy line SDL is also made low (for example, 0 V or the negative potential VBB1). Consequently, the MOS transistors19-0to19-(4m−1) are turned off to electrically separate the select gate lines SG0to SG(4m−1) from the replica select gate lines RSG0to RSG(4m−1), respectively.

The select gate decoder30applies the positive voltage Vcc1to the selected select gate line SG0. The select gate decoder30provides the unselected select gate lines SG1to SG(4m−1) with 0 V. On the other hand, the replica select gate lines RSG0to RSG(4m−1) float electrically. Consequently, the select transistor ST connected to the selected select gate line SG0is turned on. The select transistors are turned off which are connected to the unselected select gate lines SG1to SG(4m−1) and to all the replica select gate lines RSG0top RSG(4m−1).

As described above, the configuration according to the present embodiment can perform operations similar to those of the first embodiment and produce the effects (1) to (10), described above. The MOS transistors19-0to19-(4m−1) have only to be able to switch the connections between the select gate lines and the replica select gate lines. The manner of interconnections is not limited to the method of the present embodiment.

Now, description will be given of a semiconductor storage device and a method for controlling the semiconductor device according to the third embodiment of the present invention. The present embodiment relates to a method of controlling the parasitic capacitance present on the replica global bit line R_RGBL according to the first or second embodiment.

In the first or second embodiment, the parasitic capacitance of each of the local bit lines LBL0to LBL3in the prime cell array PCA is smaller than that each of the local bit lines LBL0to LBL3in the replica cell array RCA. With reference toFIG. 56, description will be given of a method of setting the parasitic capacitance of each of the local bit lines in the replica cell array RCA.FIG. 56is a flowchart of a method for setting the parasitic capacitance. The present method varies the number of memory cells in the replica cell array RCA which retain the binary 1.

As shown in the figures, the present method includes roughly eight steps listed below.(1) Initialize (step S20)(2) Erase (step S30)(3) Write (step S40)(4) Verify (step S50)
If a verify operation does not provide a predetermined result, the following step is executed.(5) Data update (step S60) and if a repeated verify operation composed of (2) to (4) provides a predetermined result, the following steps are executed.(6) Data update (step S70)(7) Erase (step S80)(8) Write (step S90)

These steps will be described in detail.

First, the write state machine120sets write data (step S21). In the present step, the “write data” indicates “the number of word lines in the replica cell array RCA to which the binary 0 is written. If the total number of word lines is l=(4m−1), the write state machine120sets, to (1/2), the total number k of word lines to which the binary 0 is written.

Then, the write state machine120changes to an erase mode (step S31). In accordance with an instruction from the write state machine120, the voltage generator130generates a voltage required for the erase operation (step S32). The data in all the prime and replica cells are then erased (the binary 1 is written to the cells; step S33). As a result, the threshold voltages for the prime and replica cells become negative.

Then, the write state machine120changes to a write mode (step S41). The write state machine120then loads the write data set in step S21(step S42). In accordance with an instruction from the write state machine120, the voltage generator130generates a voltage required for the write operation (step S43). The binary 0 is written to those word lines the number of which corresponds to the write data loaded in step S42(step S44). The write operation is as described in the first embodiment. However, in contrast to the normal write operation, no data is written to the prime cell array PCA. That is, the write inhibition voltage VPI is applied to all the write global bit lines. Only the replica cell array RCA is provided with the binary 0. The write operation is simultaneously performed on the replica cells RC connected to the plurality of word lines. That is, inFIG. 39, the positive voltage VPP is applied to the plurality of word lines. As a result, the threshold voltage for the replica cells RC connected to the k word lines changes to a positive value.

Then, the write state machine120changes to a verify mode (step S51). The write state machine120then reads the data from the prime cells PC and the replica cells RC. The write state machine120thus compares the speed of reading from the prime cells with that of reading from the replica cells TC (step S52). The read speed is, inFIG. 44, described in the first embodiment, the amount of time from time t6when discharging is started or time t1when precharging is started until time t7when the potential across the read global bit line RGBL reaches Vth or until time t8when the potential across the replica read global bit line R_RGBL reaches Vth.

If as a result step S52, the speed of reading from the prime cells PC is lower than that of reading from the replica cells RC (step S53), the parasitic capacitance of the replica read global bit line R_RGBL is smaller than that of the read global bit line RGBL. Accordingly, the settings must be changed so as to further increase the parasitic capacitance of the replica read global bit line R_RGBL. Thus, the write data is re-set so that k=k−α (α: an arbitrary integer). Then, steps S21to S53are repeated. That is, the data is erased from the entire chip, and then the number of word lines to which the binary 0 is written is reduced. Then, the data is written again.

If as a result step S52, the speed of reading from the prime cells PC is higher than that of reading from the replica cells RC (step S53), the parasitic capacitance of the replica read global bit line R_RGBL is larger than that of the read global bit line RGBL. That is, at this point in time, the conditions for the parasitic capacitance are met. In this case, to perform a more precise read operation, the data is written again so as to make a read margin.

First, the write data is re-set so that k=k−β (β: an arbitrary integer) (steps S71and S72)

Then, the write state machine120changes to the erase mode (step S81). In accordance with an instruction from the write state machine120, the voltage generator130generates a voltage required for the erase operation (step S82). The data is erased from all the prime and replica cells in the chip (the binary 1 is written; step S83).

Then, the write state machine120changes to the write mode (step S91). The write state machine120then loads the write data set in step S21(step S92). In accordance with an instruction from the write state machine120, the voltage generator130generates the voltage required for the write operation (step S93). The binary 0 is written to those word lines the number of which corresponds to the write data loaded in step S92(step S94).

Consequently, the threshold voltage for the replica cells RC connected to the k word lines changes to a positive value. As a result, the parasitic capacitance of each of the local bit lines LBL0to LBL3in the prime cell array PCA is smaller than that each of the local bit lines LBL0to LBL3in the replica cell array RCA.

The above method will be described in further detail with reference toFIGS. 57 and 58.FIG. 57is a block diagram of the memory cell array.FIG. 58is a flowchart of a method for setting the parasitic capacitance.

As shown inFIG. 57, the memory cell array10is assumed to have 64 word lines WL0to WL63(l=64) and 32 read global bit line RGBL0to RGBL31.

First, the write state machine120sets the write data (initialize; step S20). Since the number of word lines is 64, k=64/2=32. The write state machine120further sets α and β at 10 and 5, respectively. The values of α and β are only illustrative. The present invention is not limited to these values.

The write state machine120erases all the data from the memory cell array10at a time (step S30). The write state machine120then writes the binary 1 to the replica cells RC connected to the 32 word lines.FIG. 59is a time chart showing the potentials across the replica read global bit line R_RGBL and read global bit lines RGBL0to RGBL31obtained when the data is read from the prime cells PC and replica cells RC. As shown in the figure, the replica read global bit line R_RGBL changes from the precharge level to Vth at time t6. On the other hand, the read global bit line RGBL0to RGBL29changes from the precharge level to Vth at time t5, which is earlier than time t6. The read global bit lines RGBL30and RGBL31change from the precharge level to times t7and t8, respectively, which are later than time t5. That is, the parasitic capacitance of the replica read global bit line R_RGBL is larger than that of the read global bit lines RGBL0to RGBL29but is smaller than those of the read global bit lines RGBL30and RGBL31(step S50). Therefore, the predetermined conditions have not been met yet.

Thus, the write state machine120re-sets the write data (step S60). That is, k=k−α=32−10=22.

The write state machine120then erases the data from the entire memory cell array10at a time (step S30). The write state machine120writes the binary 1 to the replica cells RC connected to22word lines.FIG. 60is a time chart showing the potentials across the replica read global bit line R_RGBL and read global bit lines RGBL0to RGBL31obtained when the data is read from the prime cells PC and replica cells RC. As shown in the figure, not only the potential across the read global bit lines RGBL0to RGBL29but also the potential across the read global bit line RGBL30reach Vth earlier than that across the replica read global bit line R_RGBL. However, the potential across the read global bit line RGBL31reaches Vth later than that across the replica read global bit line R_RGBL. That is, the parasitic capacitance of the replica read global bit line R_RGBL is larger than those of the read global bit lines RGBL0to RGBL30but is smaller than that of the read global bit line RGBL31(step S50). Therefore, the predetermined conditions have not been met yet.

Thus, the write state machine120re-sets the write data (step S60). That is, k=k−α=22−10=12.

The write state machine120then erases the data from the entire memory cell array10at a time (step S30). The write state machine120writes the binary 1 to the replica cells RC connected to 12 word lines.FIG. 61is a time chart showing the potentials across the replica read global bit line R_RGBL and read global bit lines RGBL0to RGBL31obtained when the data is read from the prime cells PC and replica cells RC. As shown in the figure, the potentials across all the read global bit lines RGBL0to RGBL31reach Vth earlier than that across the replica read global bit line R_RGBL. That is, the parasitic capacitance of the replica read global bit line R_RGBL is larger than those of the read global bit lines RGBL0to RGBL31(step S50). Therefore, at this point in time, the predetermined conditions are met for the first time.

Then, the write state machine120re-sets the write data (step S70). That is, k=k−β=12−5=7. The write state machine120then erases the data from the entire memory cell array10at a time (step S80). The write state machine120writes the binary 1 to the replica cells RC connected to seven word lines.

The setting of parasitic capacitance of the replica read global bit line R_RGBL is thus finished. When the read operation is performed in this state, the potentials across the read global bit lines RGBL0to RGBL31and replica read global bit line R_RGBL vary as shown inFIG. 62. That is, the data read operation is completed on all the read global bit lines RGBL0to RGBL31earlier than that shown inFIG. 61

The above method can reduce the parasitic capacitance of each of the local bit lines LBL0to LBL3in the prime cell array PCA below that of each of the local bit lines LBL0to LBL3in the replica cell array RCA. In the description of the above embodiment, the parasitic capacitance in the replica cell array RCA is controlled on the basis of the number of replica cells RC to which the binary 1 is to be written. However, the parasitic capacitance in the replica cell array RCA can also be increased by bringing the replica cells into an over-erase state instead of using the number of replica cells RC.

Further, the above method allows the data corresponding to the parasitic capacitance in the prime cell array PCA to be considered to be written in the replica cell array. This eliminates the need for a fuse circuit and the like which are used to retain the data corresponding to the parasitic capacitance. It is thus possible to avoid an extra increase in chip area.

Now, description will be given of a semiconductor storage device according to a fourth embodiment of the present invention. The present embodiment is LSI in which the flash memory described in any of the first to third embodiments is mixed with other semiconductor chips on the same chip.FIG. 63is a block diagram of a system LSI according to the present embodiment.

As shown in the figure, the system LSI1comprises a NAND type flash memory500, a 3TR-NAND type flash memory600, a 2Tr flash memory3, MCU700, and an I/O circuit800which are formed on the same semiconductor substrate.

The NAND type flash memory500is used as a storage memory to which image and video data are saved.

The 3Tr-NAND type flash memory600retains an ID code or a security code used to access LSI1.

The 2Tr flash memory3retains program data used to operate MCU700. The 2Tr flash memory3is as described in the first to third embodiments.

In response to various externally input commands, MCU700executes processing on the basis of a program read from the 2Tr flash memory3. On this occasion, MCU700directly accesses the 2Tr flash memory3without using SRAM (Static Random Access Memory) or the like. Examples of processes executed by MCU700include compression and decompression of data input to the NAND type flash memory500and control of an external device. Moreover, if the data retained in the NAND type flash memory500is externally accessed, MCU700reads predetermined data from the 3TR-NAND type flash memory600. MCU700then checks the read data against an externally input ID code or security code. If the read data matches the ID code or security code, MCU700permits an access to the NAND type flash memory500. When the access to the NAND type flash memory500is permitted, the external device (host) accesses the data in the NAND type flash memory500. That is, in response to an externally received command, MCU700triggers the NAND type flash memory500to perform a data read (write) operation.

The I/O circuit800controls transmissions to and receptions of signals between the LSI1and the external device.

Now, description will be given of the configuration of the three semiconductor memories500,600, and 3 contained in LSI1.

FIG. 64is a circuit diagram of a memory cell array provided in the NAND type flash memory500. As shown in the figure, the memory cell array has a plurality of NAND cells arranged in a matrix. Each of the NAND cells includes eight memory cell transistors MT and select transistors ST1and ST2. The memory cell transistor MT comprises a stacked gate structure having a floating gate formed on the semiconductor substrate via a gate insulating film and a control gate formed on the floating gate via an inter-gate insulating film. The number of memory cell transistors MT is not limited to eight, but 16 or 32 memory cell transistors may be used. The number is not limited. Adjacent memory cell transistors MT share a source and a drain. The memory cell transistors MT are arranged between the select transistors ST1and ST2so that their current paths are connected in series. A drain region of one end of the series connected memory cell transistors MT is connected to a source region of the select transistor ST1. A source region of the other end of the series connected memory cell transistors MT is connected to a drain region of the select transistor ST2.

The control gates of all the memory cell transistors MT on the same row are connected to one of the word lines WL0to WLm. The gates of the select transistors ST1and ST2for the memory cells on the same row are connected to the select gate lines SGD and SGS, respectively. The word lines WL0to WLm are connected to a row decoder (not shown). The drains of all the select transistors ST1on the same column are connected to one of the bit lines BL0to BLn. The bit lines BL0to BLn are connected to a write circuit and a read circuit (not shown). The sources of all the select transistors ST2are connected to the source line SL and to the source line driver. Not both select transistors ST1and ST2are required. Only one of the select transistors ST1and ST2may be selected provided that the corresponding NAND cell can be selected.

FIG. 65is a sectional view of the memory cell array provided in the NAND type flash memory500; the sectional view is taken along the bit lines. As shown in the figure, a gate insulating film501is formed on the p-type semiconductor (silicon) substrate200. The gate electrodes of the memory cell transistors MT and select transistors ST1and ST2are formed on the gate insulating film501. The gate electrodes of the memory cell transistors MT and select transistors ST1and ST2have a polycrystalline silicon layer510formed on the gate insulating film501, an inter-gate insulating film520formed on the polycrystalline silicon layer510, a polycrystalline silicon layer530formed on the inter-gate insulating film520, and a silicide layer540formed on the polycrystalline silicon layer530. The inter-gate insulating film520is formed of, for example, a silicon oxide film or an ON, NO, or ONO film that has a stacked structure of a silicon oxide film and a silicon nitride film. In the memory cell transistors MT, the polycrystalline silicon layers510in the element regions AA arranged adjacent to each other across the word lines are separated from one another. The polycrystalline silicon layer510thus functions as a floating gate (FG). The polycrystalline silicon layer530and silicide layer540function control gates (word lines WL). The polycrystalline silicon layers530in the element regions AA arranged adjacent to each other across the word lines are connected together. In the select transistors ST1and ST2, the inter-gate insulating film520is partly removed in a shunt region (not shown). The polycrystalline silicon layers510and530are electrically connected together. The polycrystalline silicon layers510and530and the silicide layer540function as a select gate line SGD or SGS. In the select transistors ST1and ST2, the polycrystalline silicon layers510and530in the element regions AA arranged adjacent to each other across the word lines are not separated from each other but are connected together.

An impurity diffusion layer502is formed in the surface of the semiconductor substrate200located between the adjacent gate electrodes; the impurity diffusion layer502functions as a source/drain region. The impurity diffusion layer502is shared by the adjacent transistors. That is, the impurity diffusion layer502between the two adjacent select transistors ST1functions as the drain region of the two select transistors ST1. The impurity diffusion layer602between the two adjacent select transistors ST2functions as the source region of the two select transistors ST2. The impurity diffusion layer502between the two adjacent memory cell transistors MT functions as the source/drain region of the two memory cell transistors MT. Moreover, the impurity diffusion layer502between the memory cell transistor MT and select gate line ST1adjacent to each other functions as the source region of the memory cell transistor MT and select gate line ST1. On the other hand, the impurity diffusion layer502between the memory cell transistor MT and select gate line ST2adjacent to each other functions as the source region of the memory cell transistor MT and the drain region of the select gate line ST2. The silicide layer502is formed in the surface of the drain region502of the select transistor ST1and in the surface of the source region502of the select transistor ST2. The silicide layer is not formed in the source/drain region502of the memory cell transistor MT, in the source region502of the select transistor ST1, or in the drain region502of the select transistor ST2. Further, a side wall insulating film550is formed on side surfaces of gate electrodes (stacked gates) of the memory cell transistor MT and select transistors ST1and ST2. The side wall insulating film550is formed on both a side of the stacked gate facing the source region and a side of the stacked gate facing the drain region. The side wall insulating film550fills the region between the stacked gates of the memory cell transistor MT and each of the select transistors ST1and ST2. Therefore, the side wall insulating film550covers the source/drain region of the memory cell transistor MT, the source region of the select transistor ST1, and the top surface of the select transistor ST2.

The inter-level insulating film350is formed on the semiconductor substrate200so as to cover the memory cell transistor MT and select transistors ST1and ST2. A contact plug CP30is formed in the inter-level insulating film350; the contact plug CP30reaches the silicide layer503formed in the source region502of the select transistor ST2. A metal interconnect layer560connected to the contact plug CP30is formed on the inter-level insulating film350. The metal interconnect layer560functions as the source line SL. A contact plug CP31is also formed in the inter-level insulating film350; the contact plug CP31reaches the silicide layer503formed in the drain region502of the select transistor ST1. A metal interconnect layer570connected to the contact plug CP31is formed on the inter-level insulating film350.

The inter-level insulating film360is formed on the inter-level insulating film350so as to cover the metal interconnect layers560and570. A contact plug CP32reaching the metal interconnect layer570is formed in the inter-level insulating film360. A metal interconnect layer580connected to a plurality of contact plugs CP32is formed on the inter-level insulating film360. The metal interconnect layer580functions as the bit line BL.

The inter-level insulating film370is formed on the inter-level insulating film360so as to cover the metal interconnect layer580. A metal interconnect layer590is formed on the inter-level insulating film370. The metal interconnect layer590is connected to the silicide layer540of the select transistor ST1or ST2in a region (not shown). The metal interconnect layer590functions as the shunt interconnects of the select gate lines SGD and SGS. The inter-level insulating film380is formed on the inter-level insulating film370so as to cover the metal interconnect layer590.

FIG. 66is a circuit diagram of a memory cell array provided in a 3Tr-NAND type flash memory600. As shown in the figure, the memory cell array has a plurality of ((m+1)×(n+1); m and n are natural numbers) memory cells MC arranged in a matrix. Each of the memory cells MC has the memory cell transistor MT and select transistors ST1and ST2having current paths connected in series. The current path in the memory cell transistor MT is connected to between the current paths in the select transistors ST1and ST2. That is, this is equal to the NAND cells included in the NAND type flash memory each having only one memory cell transistor MT. The memory cell transistor MT comprises the stacked gate structure having the floating gate formed on the semiconductor substrate via the gate insulating film and the control gate formed on the floating gate via the inter-gate insulating film. The source region of the select transistor ST1is connected to the drain region of the memory cell transistor MT. The source region of the memory cell transistor MT is connected to the drain region of the select transistor ST2. Further, the memory cell transistors MT adjacent to each other across the columns share the drain region of the select transistor ST1or the source region of the select transistor ST2.

One of the word lines WL0to WLm connects to the control gates of the memory cell transistors MT in all the memory cells on the same row. One of the select gate lines SGD0to SGDm connects to the gates of the select transistors ST1in all the memory cells on the same row. One of the select gate lines SGS0to SGSm connects to the gates of the select transistors ST2in all the memory cells on the same row. A row decoder (not shown) connects to the word lines WL0to WLm and select gate lines SGD0to SGDm and SGS0to SGSm. One of the bit lines BL0to BLn connects to the drain regions of the select transistors ST1in all the memory cells MC on the same row. The bit lines BL0to BLn are connected to a write circuit and a read circuit (not shown). The source regions of the select transistors ST2in all the memory cells MC are connected to the source line SL and to the source line driver.

FIG. 67is a sectional view of the memory cell array provided in the 3TR-NAND type flash memory600. As shown in the figure, a gate insulating film601is formed on the p-type semiconductor (silicon) substrate200. The gate electrodes of the memory cell transistors MT and select transistors ST1and ST2are formed on the gate insulating film601. The gate electrodes of the memory cell transistors MT and select transistors ST1and ST2have a polycrystalline silicon layer610formed on the gate insulating film601, an inter-gate insulating film620formed on the polycrystalline silicon layer610, a polycrystalline silicon layer630formed on the inter-gate insulating film620, and a silicide layer640formed on the polycrystalline silicon layer630. The inter-gate insulating film620is formed of, for example, an ON, NO, or ONO film. In the memory cell transistors MT, the polycrystalline silicon layers610in the element regions AA arranged adjacent to each other across the word lines are separated from each other. The polycrystalline silicon layer610thus functions as a floating gate (FG). The polycrystalline silicon layer630and silicide layer640function control gates (word lines WL). The polycrystalline silicon layers630in the element regions AA arranged adjacent to each other across the word lines are connected together. In the select transistors ST1and ST2, the inter-gate insulating film620is partly removed in a shunt region (not shown). The polycrystalline silicon layers610and630are electrically connected together. The polycrystalline silicon layers610and630and the silicide layer640function as a select gate line SGD or SGS. In the select transistors STI and ST2, the polycrystalline silicon layers610and630in the element regions AA arranged adjacent to each other across the word lines are not separated from each other but are connected together. That is, the floating gate cells in the respective cells are not separated from one another as with the memory cell transistors MT but are all connected together.

An impurity diffusion layer602is formed in the surface of the semiconductor substrate200located between the adjacent gate electrodes; the impurity diffusion layer602functions as a source/drain region. The impurity diffusion layer502is shared by the adjacent transistors. That is, the impurity diffusion layer602between the two adjacent select transistors ST1functions as the drain region of the two select transistors ST1. The impurity diffusion layer602between the two adjacent select transistors ST2functions as the source region of the two select transistors ST2. Furthermore, the impurity diffusion layer602between the memory cell transistor MT and select gate line ST1adjacent to each other functions as the source region of the memory cell transistor MT and select gate line ST1. Moreover, the impurity diffusion layer602between the memory cell transistor MT and select gate line ST2adjacent to each other functions as the source region of the memory cell transistor MT and the drain region of the select gate line ST2. A silicide layer603is formed in the surface of the drain region602of the select transistor ST1and in the surface of the source region602of the select transistor ST2. The silicide layer is not formed in the source/drain region602of the memory cell transistor MT, in the source region602of the select transistor ST1, or in the drain region502of the select transistor ST2. Further, a side wall insulating film650is formed on side surfaces of gate electrodes (stacked gates) of the memory cell transistor MT and select transistors. The side wall insulating film650is formed on both a side of the stacked gate facing the source region602and a side of the stacked gate facing the drain region602. The side wall insulating film650fills the region between the stacked gates of the memory cell transistor MT and select transistor ST. Therefore, the side wall insulating film650covers the source/drain region of the memory cell transistor MT, the source region of the select transistor ST1, and the top surface of the select transistor ST2.

The inter-level insulating film350is formed on the semiconductor substrate200so as to cover the memory cell transistor MT and select transistors ST1and ST2. A contact plug CP40is formed in the inter-level insulating film350; the contact plug30reaches the silicide layer603formed in the source region602of the select transistor ST2. A metal interconnect layer660connected to the contact plug CP40is formed on the inter-level insulating film350. The metal interconnect layer560functions as the source line SL. A contact plug CP41is also formed in the inter-level insulating film650; the contact plug CP41reaches the silicide layer603formed in the drain region602of the select transistor ST1. A metal interconnect layer670connected to the contact plug CP41is formed on the inter-level insulating film350.

The inter-level insulating film360is formed on the inter-level insulating film350so as to cover the metal interconnect layers660and670. A contact plug CP42reaching the metal interconnect layer670is formed in the inter-level insulating film360. A metal interconnect layer680connected to a plurality of contact plugs CP42is formed on the inter-level insulating film360. The metal interconnect layer680functions as the bit line BL.

The inter-level insulating film370is formed on the inter-level insulating film360so as to cover the metal interconnect layer680. A metal interconnect layer690is formed on the inter-level insulating film370. The metal interconnect layer690is connected to the silicide layer640of the select transistor ST1or ST2in a region (not shown). The metal interconnect layer690functions as the shunt interconnects of the select gate lines SGD and SGS. The inter-level insulating film380is formed on the inter-level insulating film370so as to cover the metal interconnect layer690.

The configuration of the 2Tr flash memory3is as described in the above first and second embodiments. However, as shown inFIG. 68, the silicide layers332and342may be formed on the polycrystalline silicon layer330and in the surface of the impurity diffusion layer340, respectively. The side wall insulating film333may be formed on side walls of the stacked gate. In the memory cell transistor MT, the polycrystalline silicon layer330and the silicide layer332function as control gates (word lines WL).

The silicide layer340is formed in the surface of drain region340of the memory cell transistor MT and in the surface of source region340of the select transistor ST. The silicide layer is not formed in the source region340of the memory cell transistor MT or in the drain region340of the select transistor ST. The side wall insulating film333fills the region between the stacked gates of the memory cell transistor MT and select transistor ST. Therefore, the side wall insulating film333covers the top surface of source region of the memory cell transistor MT and the top surface of drain region of the select transistor ST.

As described above, the system LSI according to the present embodiment produces the effects (1) to (10), described in the first embodiment, but also the effects described below.

(11) Plural Types of Flash Memories can be Mounted on the Same Chip While Preventing an Increase in Manufacturing Costs.

The present configuration and manufacturing method make it possible to form, during the same process, the memory cell transistors MT and select transistors ST1, ST2, and ST provided in the NAND type flash memory500, 3Tr-NAND type flash memory600, and 2Tr flash memory3. That is, the MOS transistors are formed using the same oxidation step, deposition step, impurity injection step, and photolithography and etching step. As a result, the three flash memories500,600, and 3 use the same gate insulating film and inter-gate insulating film, the same floating and control gates of the memory cell transistor MT, and the same select gate of the select transistor. This manufacturing method enables a memory cell array of the three flash memories to be formed using the number of steps required to form one flash memory. This makes it possible to reduce the manufacturing costs of a system LSI on which the three types of semiconductor memories are mounted.

(12) Performance of the System LSI can be Improved.

The system LSI according to the present embodiment has the above NAND type flash memory500, 3Tr-NAND type flash memory600, and 2Tr flash memory3.

Further, according to the present embodiment, the 2Tr flash memory3stores program data required to operate MCU700. The 2Tr flash memory can operate fast as described above. Accordingly, MCU700can read data from the 2Tr flash memory3without using RAM. This eliminates the need for RAM to simplify the configuration of the system LSI. The operation speed can also be improved.

Furthermore, the 3Tr-NAND type flash memory600retains an ID code or a security code. These codes do not have a very large amount of data but are frequently changed or updated in many cases. Accordingly, a memory retaining the code data must operate at a somewhat high speed. In this regard, the 3Tr-NAND type flash memory600uses an erase unit smaller than that for the NAND type flash memory500. The 3Tr-NAND type flash memory600thus enables data to be rewritten on a page by page basis. Therefore, the 3Tr-NAND type flash memory600is a semiconductor memory that is optimum for retaining the code data.

A conventional LSI having a NAND type flash memory requires such a controller as described below in order to prevent rewrite operations from concentrating on a particular block. The controller converts an address input using ware leveling or logic into a physical address, or if any block is defective, considers it to be a defective block and performs control such that the block will no longer be used. However, the present embodiment does not require such a controller. This is because the 2Tr flash memory3may retain a firmware program that controls the blocks in the NAND type flash memory500so that MCU700can perform the above control. MCU700may perform the above control in the intervals between its intrinsic operations (control of an external device and calculation of data input to the NAND type flash memory500). Of course, if the amount of processing that must be executed by MCU700is large compared to the level of capabilities of MCU700, a hardware sequencer or the like may be provided to control the NAND type flash memory500.

As described above, with the semiconductor storage device according to any of the first to fourth embodiments, the parasitic capacitance of each of the local bit lines LBL0to LBL3in the prime cell array PCA is smaller than that of each of the local bit lines LBL0to LBL3in the replica cell array RCA. Therefore, during the read operation, the parasitic capacitance present on the replica read global bit line R_RGBL is larger than that present on the read global bit line RGBL.

During a precharge operation, after the potential across the replica read global bit line R_RGBL exceeds the data determination threshold voltage Vth for the sense amplifier, precharging of the read global bit line RGBL is finished. When a data read operation is finished, the data on the read global bit line RGBL is established after the voltage across the replica read global bit line R_RGBL has decreased from the precharge potential to Vth.

Accordingly, for the precharge operation, the potential across the read global bit line RGBL can be reliably set to at least Vth. When the binary 1 is read, the data can be established after the potential across the read global bit line RGBL has reliably decreased below Vth. This makes it possible to avoid erroneous determinations for read data.

In order to reduce the parasitic capacitance of each of the local bit lines LBL0to LBL3in the prime cell array PCA below that of each of the local bit lines LBL0to LBL3in the replica cell array RCA, it is possible to control the number of replica cells connected to the local bit lines LBL0to LBL3and retaining the binary 1. Alternatively, replica cells in an over-erase state may be provided.

In the description of the above embodiments, the discharge circuit81comprises the voltage generator88and the current source circuit87including the MOS transistors87-1and87-2. However, the configuration of the discharge circuit81is not limited provided that the replica read global bit line can be discharged at a fixed temporal variation rate. Further, the discharge capability of the discharge circuit81, shown inFIG. 12, can be varied using the size of the MOS transistor87-1or87-2or the value of the value Vref.

Further, the MOS transistors19-0to19-(4m−1), described in the second embodiment, are not limited to those shown inFIG. 50and having a planar pattern. The MOS transistors19-0to19-(4m−1) have only to be able to switch between the select gate lines SG0to SG(4m−1) and the replica select gate lines RSG0to RSG(4m−1). For example, such an arrangement as shown inFIG. 69may be used.FIG. 69shows a planar pattern of the MOS transistors19-0to19-(4m−1). For simplification, the only interconnects shown in this figure are the word lines, the shunt interconnects270of the select gate lines, the shunt interconnects271of the replica select gate lines, the gate electrode31, and the select dummy line SDL.

As shown in the figure, the two MOS transistors19-0and19-1(19-2and19-3,19-4and19-5, . . . ) are arranged between the two word lines WL0and WL1(between WL2and WL3, between WL4and WL5, . . . ) along the second direction, in contrast toFIG. 50, described in the second embodiment. The gate electrode311is formed so that its longitudinal direction extends along the second direction and that its source, channel, and drain regions extend along the first direction. The shunt interconnect270of each select gate line is connected to one of source and drain of the corresponding one of the MOS transistors19-0and19-1.

Further, like the gates of the prime and replica cells, the gate electrode311of each of the MOS transistors19-0to19-(4m−1) may have a multilayered gate structure as shown inFIGS. 70 and 71.FIGS. 70 and 71are sectional views taken across the gate length and width, respectively, of the MOS transistors19-0to19-(4m−1). As shown in the figures, the gate electrode311comprises a polycrystalline silicon layer312formed on the gate insulating film301and a polycrystalline silicon layer314formed on the polycrystalline silicon layer312via an inter-gate insulating film313. The polycrystalline silicon layer314and inter-gate insulating film313are removed in a particular region in which the contact plug CP18is formed in contact with the polycrystalline silicon layer312. In the example inFIG. 71, like the shunt region SA2, the contact plug CP18is electrically separated from the polycrystalline silicon layer314by an insulating film315. However, the contact plug CP18may be in contact with the polycrystalline silicon layer314.

In the description of the above embodiment, only the negative voltage is used as the write inhibition voltage VPI. However, instead of the negative voltage, a positive voltage or 0 V may be used as the write inhibition voltage VPI.FIG. 72shows a circuit configuration used in this case.FIG. 73is a timing chart of VPI and VNEGPRG.

As shown in the figure, the voltage generator130comprises a charge pump circuit131that generates a negative potential and a charge pump circuit132that generates a positive potential. The charge pump circuit131generates negative potentials VBB2and VBB4. The charge pump circuit132generates a positive potential VPP2. Further, a switch is used to appropriately connect an output node for these voltages and a ground potential node to a VPI node. This enables the use of a voltage best matching the situation as the write inhibition voltage VPI.

In the above embodiments, description is given of the 2Tr flash memory comprising the write decoder20and select gate decoder30. However, as shown inFIG. 74, one row decoder140may be used to select the word line and the select gate line. Further, for the erase operation, the potential of the select gate line may float.

Moreover, in the above embodiments, the bit line is hierarchical, but the present invention is not limited to this. However, if the bit line is hierarchical, the write global bit line is desirably set at 0 V for the read operation. Thus, the write selector50, the write circuit60, and the switch group100are desirably set in their initial states. Setting these components in the initial states enables the potential across the write global bit line to be set at 0 V via the current path in the MOS transistor53. Setting the potential of the write global bit line at 0 V prevents noise from the read global bit line during the read operation. This enables the read operation to be further stabilized. It is therefore possible to improve the reliability of the read operation performed on the flash memory.

Now, description will be given of an application for the above semiconductor storage device.FIG. 75shows an example of a memory card. As shown inFIG. 75, a memory card900has the flash memory3, described in the above embodiments (the 2Tr flash memory, 3Tr-NAND type flash memory, or NAND type flash memory may be used instead). The flash memory3receives predetermined control signals and data from an external device (not shown). The flash memory3also outputs predetermined control signals and data to an external device (not shown).

The following signal lines are connected to the flash memory3mounted in the memory card900: a signal line (DAT) through which data, an address, or a command is transferred, a command line enable signal line (CLE) that indicates that a command is being transferred to the signal line DAT, an address line enable signal line (ALE) that indicates that an address is being transferred to the signal line DAT, and a ready/busy signal line (R/B) that indicates whether or not the flash memory10is operative.

FIG. 76shows another example of a memory card. This memory card is different from that shown inFIG. 75in that it has a controller910which controls the flash memory3and which transmits predetermined signals to and from an external device (not shown).

The controller910connects to interface sections (I/F)911and912which receive predetermined signals from the flash memory3and an external device (not shown) or which output predetermined signals to the external device, a microprocessor section (MPU)913that executes predetermined calculations for converting a logical address input by the external device into a physical address, a buffer RAM914that temporarily stores data, ands an error correction section (ECC)915that generates an error correction code. The memory card900connects to a command signal line (CMD), a clock signal line (CLK), and the signal line (DAY).

The previously described memory card has been shown, but variations may be made to the number of control signals, the bit widths of the signal lines, or the configuration of the controller.

FIG. 77shows another application. As shown inFIG. 77, the above memory card900is inserted into a card holder920, which is then connected to an electronic device (not shown). The card holder920may have some of the functions of the controller910.

FIG. 78shows another application. As shown in the figure, the memory card900or the card holder920into which the memory card900has been inserted is inserted into a connection device1000. The connection device1000is connected to a board1300Via a connection wire and an interface circuit1200. A CPU1400and a bus1500are mounted on the board1300.

FIG. 79shows another application. The memory card900or the card holder920into which the memory card900has been inserted is inserted into a connection device1000. The connection device1000is connected to a personal computer2000Via the connection wire1100.

FIGS. 80 and 81show another application. As shown in the figures, MCU2200is mounted in an IC card2100. MCU2200comprises the flash memory10according to any of the embodiments and other circuits, for example, ROM2300, RAM2400, and CPU2500. The IC card2100is connected to MCU2200and can be connected to MCU2200Via a plane connecting terminal2600provided in the IC card2100. CPU2500comprises a calculation section2510and a control section2520connected to the flash memory3, ROM2300, and RAM2400. For example, MPU2200is provided on one surface of the IC card2100. The plane connecting terminal2600is provided on the other surface of the IC card2100.

As described above, the embodiments of the present invention suppresses migration of extra charge across the bit lines during discharging after precharging has been finished. This increases the speed of the read operation. Since no through current is conducted during discharging, power consumption can be reduced.

Further, the output from the clocked inverter can be made low immediately after precharging. Accordingly, the MOS transistor Q2can be turned off more quickly. This also increases the speed of the read operation. Furthermore, even if the bit line is at the low level and the MOS transistor Q4has a high threshold voltage, the bias voltage BIAS can be reliably made low by using the logic signal (precharge signal /PRE) to turn on the MOS transistor Q7.

Moreover, the read control circuit83free from the MOS transistor Q7turns off the MOS transistor Q2, which controls the level of the bit line, later than the read circuit73. This relatively reduces the speed of the read operation performed by the read control circuit83. It is thus possible to provide sufficient margins for the main body output and read end signal.

Therefore, an aspect of the present invention provides a semiconductor storage device that can perform a fast read operation with reduced power consumption.