Mark structure and fabrication method thereof

The present disclosure provides mark structures and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a device region, a first mark region and a second mark region; sequentially forming a device layer, a dielectric layer and a mask layer on a surface of the substrate; forming a first opening in the dielectric layer in the device region, a first mark in the dielectric layer in the first mark region, and a mark opening in dielectric layer in the second mark region, bottoms of the first opening, the first mark and the mark opening being lower than a surface of the dielectric layer, and higher than a surface of the device layer; and forming a second opening in the dielectric layer on the bottom of the first opening and a second mark in the dielectric layer on the bottom of the mark opening.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the priority of Chinese patent application No. 201610079408.1, filed on Feb. 3, 2016, the entirety of which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention generally relates to the field of semiconductor manufacturing technology and, more particularly, relates to mark structures and fabrication processes thereof.

BACKGROUND

During a semiconductor fabrication process, before forming semiconductor devices on a wafer, a layout design of the wafer is necessary to divide the wafer into a plurality of dies and a plurality of scribe lanes among adjacent dies. The dies are used to subsequently form the semiconductor devices; and the scribe lanes are used as cutting lines when the dies are packaged after forming the semiconductor devices.

Dividing the surface of the wafer into the dies and scribe lanes is often achieved by transferring patterns on a mask of a photolithography process to the surface of the wafer. Specifically, the process for dividing the surface of the wafer into the dies and the scribe lanes includes forming a photoresist layer on the surface of the wafer by a spin-coating process; installing the wafer having the photoresist layer into an exposure apparatus after baking the photoresist layer; exposing the baked photoresist to transfer the patterns on the mask to the photoresist layer by an exposure process; post-baking the exposed photoresist layer; and developing the post-baked photoresist layer to form the patterns in the photoresist layer. In the design of the mask for dividing the surface of the wafer into the dies and the scribe lanes, it is common to form the required patterns of the photolithography process, such as alignment marks and overlay marks, etc., in the scribe lanes.

For the existing techniques, the photoresist often has offset, rotation, shrinking and extending, and/or orthogonal change, etc., during the overlay exposure process because of the overlay precision, wafer shift and focusing precision, etc. Thus, an overlay measuring mark is required for measuring the exposure error between different dies formed in a same photoresist layer, and/or the exposure error between the dies at a same position of different photoresist layers. By doing so, the overlay precision of the wafer is obtained.

However, for the overlay marks formed at a same position of different photoresist layers, there is a resolution difference. Such a resolution difference affects the detection of the overlay precision. Thus, the overlay marks may be unable to meet the requirement of the continuous development of the manufacturing. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems in the art.

BRIEF SUMMARY OF THE DISCLOSURE

One aspect of the present disclosure includes a method for fabricating a mark structure. The method includes providing a substrate having a device region and a mark region including a first mark region and a second mark region surrounded by the first mark region; sequentially forming a device layer, a dielectric layer and a mask layer over a surface of the substrate; forming a first opening in the dielectric layer in the device region, a first mark in the dielectric layer in the first mark region, and a mark opening in the dielectric layer in the second mark region, a bottom of the first opening, a bottom of the first mark and a bottom of the mark opening being lower than a surface of the dielectric layer and higher than a surface of the device layer; forming a second opening exposing the device layer in the dielectric layer on the bottom of the first opening and a second mark in the dielectric layer on the bottom of the mark opening; and forming a conductive structure in the first opening and the second opening.

Another aspect of the present disclosure includes a mark structure. The mask structure includes a substrate having a device region and a mark region including a first mark region and a second mark region surrounded by the first mark region; a device layer formed on a surface of the substrate; a dielectric layer formed on a surface of the device layer; a plurality of first mark trenches formed in the dielectric layer in the first mark region; a plurality of second mark trenches formed in the dielectric layer in the second mark region; and a conductive structure electrically connected with the device layer formed in in the dielectric layer in the device region.

Another aspect of the present disclosure includes a mark structure. The mark structure includes a substrate having a device region and a mark region including a first mark region and a second mark region surrounded by the first mark region; a device layer formed on a surface of the substrate; a dielectric layer formed on a surface of the device layer; a plurality of first mark protruding structures formed in the dielectric layer in the first mark region; a plurality of second mark trenches formed in the dielectric layer in the second mark region; and a conductive structure electrically connected with the device layer formed in the dielectric layer in the device region.

DETAILED DESCRIPTION

FIGS. 1-4illustrate structures corresponding to certain stages of an existing fabrication process of an overlay mark structure. As shown inFIG. 1, the fabrication process includes providing a substrate100. The substrate100includes a mark region110and a device region120. A device layer101is formed on the surface of the substrate100in the device region120; and a dielectric layer102is formed on the surface of the device layer101and the surface of the substrate100. Further, a mask layer103is formed on the surface of the dielectric layer102.

Further, as shown inFIG. 2, a first opening121is formed in the device region120and a plurality of first mark trenches111are formed in the mark region110by etching the mask layer103and the dielectric layer102. The number of the first mark trenches111is four; and the four first mark trenches111form a quadrangle.

Further, as shown inFIGS. 3-4(FIG. 4is a top view of the structure illustrated inFIG. 3). A plurality of the second mark trenches112are formed in the region enclosed by the plurality of first mark trenches111; and a second opening122is formed on the bottom of the first opening121. The second opening122exposes the device layer101. The plurality of second mark trenches122and the second opening122are formed by etching the mask layer103in the mark region110and the bottom of the first opening121using a second etching process.

The first mark trenches111and the second mark trenches112form an overlay mark structure. The first mark trenches111are used to define the position of the first opening121; and the second mark trenches112are used to define the position of the second opening122. By measuring the relative positions between the first mark trenches111and the second mark trenches112, the offset between the first opening121and the second opening122is obtained. The fabrication process can be improved according to the obtained offset.

The first opening121and the second opening122are used to form a conductive structure used to electrically connect with the conductive layer101; and the process for forming the conductive structure is applicable to form structures with a relatively small feature size. Because the second opening122needs to expose the surface of the device layer101to achieve an electrical connection between the conductive structure and the device layer101, the first opening101needs to be aligned with the device layer101; and the second opening122also needs to be aligned with the conductive layer101.

However, after the first etching process or the second etching process, it is easy to induce a stress-releasing between the mask layer103and the dielectric layer102, and/or between the dielectric layer102and the device layer101. Thus, an offset between the position of the first opening121and the position of the first trenches111is generated. Accordingly, the position of the subsequently formed second opening122relative to the first opening121and/or the device layer121is not accurate.

Further, because the first opening121is formed firstly; and the bottom of the first opening121does not expose the device layer101, the position of the second opening122needs to be determined by the first opening121. Once the first opening121has an offset relative to the device layer101, the second opening122would have a larger offset relative to the device layer101if the second opening122has an offset relative to the first opening121. Such a larger offset easily causes the bottom of the second opening142not to be able to precisely expose the device layer101. Thus, during the fabrication of the conductive layer, it is not allowable to have gradual offsets among the device layer101, the second opening122and the first opening121along one direction.

To ensure the position of the second opening122relative to the first opening121and the device layer101to be more accurate during the fabrication of the conducive structure, the fabrication process needs to be adjusted according to the overlay precision. Specifically, the fabrication process is improved by accurately measuring the offset of the relative position between the first opening121and the second opening122; and by learning the offset situation of the relative position between the first opening121and the second opening122. Thus, the detection of the overlay precision between the first opening121and the second opening122has higher requirements.

The first etching process is used to etch the mask layer103and a portion of the dielectric layer102to form the first opening121. Thus, the first etching process has a relatively large etching rate to both the mask layer103and the dielectric layer102. Accordingly, the depth of the first mark trenches111is relatively large; and the bottom of the first mark trenches111is lower than the surface of the dielectric layer102. However, because the second etching process is used to etch the dielectric layer102on the bottom of the first opening121, the second etching process has a larger etching rate to the dielectric layer102than to the mask layer103. Such an etching rate difference causes the depth of the second mark trenches112formed on the mark region110is relatively small; or even is unable to penetrate through mask layer103to expose the dielectric layer102. Thus, the patterns of the second mark trenches112are blurry. Especially after subsequently removing the mask layer103by a chemical mechanical polishing process, the second mark trenches112are completely removed; and the overlay precision between the first mark trenches111and the second mark trenches112may not be measured. Thus, the fabrication process of the devices is affected.

The present disclosure provides an improved fabrication process of a mark structure.FIG. 15illustrates an exemplary fabrication process of a mark structure consistent with the disclosed embodiments; andFIGS. 5-9illustrate structures corresponding to certain stages of the exemplary fabrication process.

As shown inFIG. 15, at the beginning of the fabrication process, a substrate with certain structures is provided (S101).FIG. 5illustrates a corresponding structure.

As shown inFIG. 5, a substrate200is provided. The substrate200may include a mark region (not labeled) and a device region240. The mark region may include a first mark region250and a second mark region260. The first mark region250may surround the second mark region260.

Further, a device layer210may be formed on the surface of the substrate200. A dielectric layer220may be firmed on the surface of the device layer210. A mask layer230may be formed on the surface of the dielectric layer220.

The device layer210may have a conductive layer211formed in its surface in the device region240. The dielectric layer220may include a barrier layer221formed on the surface of the device layer210; a first dielectric layer222formed on the surface of the barrier layer221; and a second dielectric layer223formed on the surface of the second dielectric layer222.

The mark region may be used to form an overlay mark structure. The overlay mark structure may be used to detect the relative offset between the subsequently formed first opening and second opening. The device region240may be used to form semiconductor devices; and the semiconductor devices may form chip circuits, etc.

Further, the substrate200may also include dies (not shown) and scribe lanes (not shown) among adjacent dies distributed as an array. The dies may be used to form individual chips. The scribe lanes may be used to subsequently cut the substrate200. By cutting through the scribe lanes, the plurality of dies may be independent to each other; and the individual chips may be formed.

Further, the device region240may be disposed in a die; and the mark region may be disposed in the scribe lane. After subsequently forming the overlay mark structure in the scribe lanes, when the scribe lanes are cut through, the overlay mark structure may be removed.

in one embodiment, the substrate200may include a base substrate (not shown), The device layer210may be formed on the surface of the base substrate. The conductive layer211may be exposed on the surface of the device layer210.

The base substrate may be a Si substrate, a SiGe substrate, a SiC substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate, or a III-V compound substrate (such as GaN, or GaAs), etc.

The device layer210may include device structures on the surface of the base substrate. The device structures may include one or more of gate structures of the transistors, fuse structures, resistors, capacitors, and inductors, etc.

The device layer210may also include an insulation layer (not shown). The insulation layer may be formed on the surface of the base substrate; and may cover the device structures. The insulation layer may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric material, and ultra-low-K material, etc.

Further, the device layer210may also include electrical interconnect structures. The electrical interconnect structures may be formed on the surface of the base substrate and/or the surfaces of the device structures. The electrical interconnect structures may be used to electrically interconnect the device structures and/or electrically interconnect the device structures and the base substrate. The electrical interconnect structures may be made of metal or metal compound, such as one or more of Cu, W, Ti, Ni, TiN, and TaN, etc. The electrical interconnect structure may include conductive vias (or plugs) formed on the surface of the base substrate and/or the surfaces of the devices structures; and the conductive layer211formed on the top surface of the conductive vias. The conductive layer211may be used to electrically connect the conductive vias. The consecutive vias and the conductive layer211may be distributed in a single layer, or different layers.

In certain other embodiments, the substrate is the base substrate. A conductive layer may be formed in the substrate; and the conductive layer is exposed on the surface of the substrate. The conductive layer may be formed on the surface of an ion-doped region; and the conductive structure may be subsequently formed on the surface of the conductive layer to apply a bias voltage on the ion-doped region. Further, the conductive layer may also be able to connect with through silicon vias (TSV).

Referring toFIG. 5, the dielectric layer220may include a barrier layer221, a first dielectric layer222and a second dielectric layer223. The barrier layer223may be made of an N-containing material, etc. The first dielectric layer222may be made of an ultra-low-K dielectric material, etc. The dielectric constant of the ultra-low-K dielectric material may be smaller than approximately 2.5. The second dielectric layer223may be made of tetraethyl orthosilicate (TEOS), etc. The mask layer230may be made of TiN, etc.

The barrier layer221may be made of a material different from that of the first dielectric layer222. Thus, the barrier layer221and the first dielectric layer222may have an etching selectivity. Accordingly, the barrier layer221may be used as an etching stop layer for a subsequent etching process.

Further, the first dielectric layer222may be made of an ultra-low-K material. The ultra-low-K material may be a porous material. Thus, the external contaminations and water vapor may be easy to penetrate through the first dielectric layer222to etch the interconnect structures. Therefore, it may need to form the barrier layer221on the surface of the device layer210before forming the first dielectric layer222. The density of the barrier layer221may be greater than the density of the first dielectric material layer222. Thus, the barrier layer221may be able to prevent the external contaminations and water vapor from directly contacting with the device layer210.

The barrier layer221may be made of silicon nitride, or silicon oxynitride, etc. In one embodiment, the barrier layer221is made of silicon oxynitride. The thickness of the barrier layer221may he in a range of approximately 200 Å-500 Å. Various processes may be used to form the barrier layer221, such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, etc.

The first dielectric layer222may be made of an ultra-low-K dielectric material. The process for forming the ultra-low-K dielectric material may include forming a seed layer on the surface of the barrier layer221; and forming a bulk dielectric layer on the surface of the seed layer.

The seed layer may be made of SiCO, etc. The bulk dielectric layer may be made of porous SiCOH based on the seed layer made of SiCO.

The hardness and the density of the second dielectric layer223may be greater than those of the first dielectric layer222. The second dielectric layer223may be used as an intermediate layer between the first dielectric layer222and the mask layer230; and may be used to increase the adhesion strength between the mask layer230and the first dielectric layer222. Further, the second dielectric layer223may keep a stable morphology during the subsequent planarization process for removing the mask layer230; and may prevent the planarization process from excessively damaging the surface of the dielectric layer220.

Various processes may be used to form the second dielectric layer223. In one embodiment, a CVD process is used to form the second dielectric layer223. The precursor of the CVD process may be TEOS, etc. A TEOS layer may be formed on the surface of the first dielectric layer222. Then, the TEOS layer may be oxidized in an oxygen-containing environment; and silicon oxide may be formed.

The mask layer230may be used as a hard mask layer for subsequently etching the dielectric layer220in the device region240to form a first opening. In one embodiment, the mask layer230is made of TiN. In certain other embodiments, the mask layer230may be made of one or more of TaN, Ta, and Ti, etc. Various processes may be used to form the mask layer230, such as a CVD process, an ALD process, or a physical vapor deposition (PVD) process, etc.

In one embodiment, before forming the mask layer230, an interface layer may be formed on the surface of the dielectric layer220. The interface layer may be made of silicon oxide. The interface layer may be used to increase the adhesion strength between the mask layer230and the dielectric layer220.

Returning toFIG. 15, after forming the mask layer230, a first mark, a mark opening and a first opening may be formed (S102).FIGS. 6-7illustrate a corresponding structure; andFIG. 7is a top view of the mark region illustrated inFIG. 6.

As shown inFIGS. 6-7, a first mark (not labeled) is formed in the dielectric layer220in the first mark region250; a mark opening261is formed in dielectric layer220in the second mark region260; and a first opening241is formed in the dielectric layer220in the device region240. The bottom of the first opening214and the bottom of the mark opening261may be higher than the surface of the device layer240. The mark opening261may at least expose a portion of the dielectric layer220in the second mark region260.

The first mark may include a plurality of the first mark trenches251. The plurality of first mark trenches215may be evenly distributed around the second mark region260.

In one embodiment, the number of the first mark trenches251is four. The top of each first mark trench251may be stripe-shaped. Further, the four first mark trenches251may form a quadrangle around the second mark region260. In one embodiment, the lengths of the four first mark trenches251are identical; and the four first mark trenches251form a square around the second mark region. Further, the sidewalls of the first mark trenches251may be perpendicular to the mask layer230.

The first mark, the mark opening261and the first opening241may be formed by etching through the mask layer230and etching a portion of the dielectric layer220by a first etching process. Specifically, in one embodiment, the second dielectric layer223of the dielectric layer220may also be etched through; and the top portion of the first dielectric layer222may be etched.

The first opening241may be formed in the dielectric layer220in the device region240. The first opening241may be used to subsequently form a portion of a conductive structure. The bottom of the first opening241may be lower than the surface of the dielectric layer220; and may be higher than the surface of the device layer210. The first opening241may be used to form an electrical interconnect layer. A second opening may be subsequently formed in the bottom of the first opening241to expose the conductive layer211. The second opening may be used to form a conductive via; and the conducive via may be used to electrically interconnect the conductive layer211and the electrical interconnect layer. The conductive via and the electrical interconnect layer may form an electrical conductive structure.

When the first opening241is formed, the first mark may be formed in the first mark region simultaneously. Thus, the relative position between the first mark and the first opening241may be fixed. When a second opening is subsequently formed in the bottom of the first opening241, a second mark may also be formed simultaneously. Thus, the offset between the first opening and the second opening may he obtained according to the relative position between the first mark and the second mark. Therefore, the fabrication process may be improved according to the offset.

The process for forming the first mark trenches251, the mark opening261and the first opening241may include forming a first pattern layer201exposing portions of the surface of the mask layer230corresponding to the first mark trenches251, the mark opening261and the first opening241on the mask layer230; and etching the mask layer230and the portion of the dielectric layer220by the first etching process using the first pattern layer201has an etching mask. Thus, the first mark trenches251, the mark opening261and the first opening241may be formed. After the first etching process, the first pattern layer201may be removed.

The first pattern layer201may be a patterned photoresist layer. The process for forming the first pattern layer201may include forming a first photoresist film on the surface of the mask layer230by a spin-coating process; and exposing, developing and baking the photoresist film. Thus photoresist film may be transferred as the first pattern layer201. In certain other embodiments, the first pattern layer201may be formed by a nano-imprint process, or self-assemble process, etc.

The first etching process may be a dry etching process, or a wet etching process. In one embodiment, the first etching process is an anisotropic dry etching process. The etching gases of the dry etching process may include carbon fluoride gas, O2and a carrier gas, etc. The flow rate of the etching gas may be in a range of approximately 50 sccm-1000 sccm. The pressure of the etching gas may be in a range of approximately 1 mTorr-50 mTorr. The bias voltage of the dry etching process be in a range of approximately 10 V-80 V. The power of the dry etching process may be in a range of approximately 100 W-800 W. The temperature of the dry etching process may be in a range of approximately 40° C.-200° C. The carbon fluoride gas may include one or more of CF4, C3F8, C4F8, CH2F2, CH3F and CHF3, etc. The carrier gas may include one or more of Ar, He and N2, etc.

During the dry etching process, by the adjusting the ratio between C and F, the selectivity of the etching gas may be adjusted. The adjustment of the ratio between C and F may enable the first etching process to have a relatively high etching selectivity to the mask layer230and the dielectric layer220.

During the first etching process for forming the first opening241in the device region240and the first mark trenches251in the first mark region250, the mark opening261may be formed in the second mark region260. The second mark region260may be used to subsequently form a second mark. The second mark may have a fixed relative position with the second opening subsequently formed in the bottom of the first opening241. By measuring the overlay precision between the second mark and the first mark, the offset of the second opening to the first opening241may be obtained.

Because the subsequent second etching process used for forming the second opening may etch the dielectric layer220in the bottom of the first opening241, the second etching process may have a higher etching rate to the dielectric layer220than the etching rate of the first etching process to the dielectric layer220. The etching rate of the second etching process to the mask layer230may be reduced. To ensure the subsequent second etching process to be able to form the second mark in the dielectric layer220, the mark opening261exposing at least a portion of the dielectric layer220may be formed in the second mark region260.

In one embodiment, the bottom of the mark opening261may he lower than the surface of the dielectric layer220and higher than the surface of the device layer210. Further, the mark opening261may expose a portion of the dielectric layer220in the mark region260. The area of the exposed portion of the dielectric layer220may be greater than the area of the region corresponding to the subsequently formed second mark. Such a geometry may ensure to subsequently form the second mark in the dielectric layer220in the bottom of the mark opening261. In certain other embodiments, the mark opening261may expose the entire portion of the dielectric layer220in the second mark region260.

In one embodiment, the top of the mark opening216is a square and the length of each side of the square may be in a range of approximately 0.02 μm-0.03 μm. For example, the length of the side of the square may be approximately 0.025 μm.

Returning toFIG. 15. after forming the first mark, the first mark opening261and the first opening241, a second mark and a second opening may be formed (S103).FIGS. 8-9illustrate a corresponding structure; andFIG. 9is a top view of the mark region illustrated inFIG. 8.

As shown inFIGS. 8-9, a second opening242exposing the device layer210is formed in the dielectric layer220on the bottom of the first opening241. Further, a second mark (not labeled) is formed in the dielectric layer220on the bottom of the mark opening261.

The second mark may include a plurality of second mark trenches262. The plurality of second mark trenches262may be uniformly distributed around the central point of the second mark region260.

In one embodiment, the number of the second mark trenches262is four. The top of each of the second mark trenches262may be stripe-shaped; and the four second mark trenches262may be distributed as a quadrangle around the central point of the second mark region260.

In one embodiment, the lengths of the tops of the four second mark trenches262are identical. Thus, the second mark trenches262may form a square. Further, the side surfaces of the second mark trenches262may be perpendicular to the surface of the device layer210.

The second opening242may be used to subsequently form a portion of a conductive structure. Specifically, the second opening242may be used to form a conductive via. The conductive via may be used to electrically connect the electrical interconnect layer subsequently formed in the first opening241with the conductive layer211.

During the process for forming the second opening242, the second mark may be formed in the dielectric layer220on the bottom of the mark opening261simultaneously. The second mark and the second opening242may have a fixed relative position. The offset of the second opening242relative to the first opening241may be obtained according to the overlay mark measurement between the first mark and the second mark.

The second mark and the second opening242may be formed by etching portions of the dielectric layer220on the bottom of the first opening241and on the bottom of the mark opening261using a second etching process. Specifically, the process for forming the plurality of second mark trenches262and the second opening242may include forming a second pattern layer202exposing portions of the surface of the dielectric layer220corresponding to the second mark trenches262and the second opening242on the surface of the mask layer230and a portion of the dielectric layer220; and etching the portions of the dielectric layer220by the second etching process using the second pattern layer202as an etching mask. Thus, the second mark trenches262and the second opening242may be formed. After forming the second mark trenches262and the second opening242, the second pattern layer202may be removed.

In one embodiment, the second pattern layer202may be a patterned photoresist layer. Before forming the patterned photoresist layer, an antireflective layer may be formed on the surface of the mask layer230and the dielectric layer220; and the photoresist layer may be formed on the surface of the antireflective layer.

The process for forming the patterned photoresist layer may include forming a second photoresist layer on the surfaces of the mask layer230and the dielectric layer220by a spin-coating process; and exposing, developing and baking the photoresist layer. Thus, the second photoresist layer may be patterned. In certain other embodiments, the second pattern layer202may be formed by a nano-imprinting process, or a self-assembly process, etc.

The second etching process may be a dry etching process, or a wet etching process. In one embodiment, the second etching process is an anisotropic dry etching process. The anisotropic dry etching process may be performed until the surface of the conductive layer211is exposed.

The etching gas of the anisotropic dry etching process may include carbon fluoride gas, O2and carrier gas, etc. The flow rate of the etching gas may be in a range of approximately 50 sccm-1000 sccm. The pressure of the etching gas may be in a range of approximately 1 mTorr-50 mTorr. The bias voltage of the anisotropic dry etching process may be in a range of approximately 10 V-800 V. The power of the anisotropic dry etching process may be in a range of approximately 100 W-800 W. The temperature of the anisotropic dry etching process may be in a range of approximately 40° C.-200° C. The carbon fluoride gas may include one or more of CF4, C3F8, C4F8, CH2F2, CH3F and CF3, etc. The carrier gas may include one or more of Ar, He, and N2, etc.

By adjusting the ratio between carbon and fluoride in the carbon fluoride gas, the etching selectivity of the etching gas may be adjusted. Because the second etching process may be used to etch the dielectric layer220until the surface of the conductive layer211is exposed, the etching depth in the dielectric layer caused by the second etching process may be relatively large. Thus, the ratio between carbon and fluoride in the etching gas may need to be adjusted to increase the etching rate of the second etching process to the dielectric layer220and to reduce the etching rate of the second etching process to the mask layer230. That is, the etching rate of the second etching process to the mask layer230may be smaller than the etching rate of the first etching process to the mask layer230.

Because the second mark trenches262and the second opening242may have a fixed relative distance, by measuring the overlay precision between the second mark trenches262and the first mark trenches251, the offset of the second opening242relative to the first opening241may be obtained. According to such an offset, the fabrication process may be improved.

After forming the second mark, an overlay mark measurement may be performed to determine the offset of the second opening242relative to the first opening241. If the offset meet the design requirement, a conductive structure may be formed in the first opening241and the second opening242.

The process for forming the conductive structure may include forming a conductive material film on the surface of the mask layer230and in the first opening241and the second opening242. The conductive material film may fill the first opening241and the second opening242. After forming the conductive material film, a planarization process may be performed until the surface of the dielectric layer220is exposed.

The planarization process may be a chemical mechanical polishing process. After removing the conductive material film higher than the surface of the mask layer230, the chemical mechanical polishing process may continue until the surface of the dielectric layer220is exposed.

In one embodiment, the bottoms of the first mark trenches251and the bottoms of the second mark trenches262may be both lower than the surface of the dielectric layer220. Thus, after the planarization process, the first mark trenches251and the second mark trenches262may still exist; and may be still clear. Accordingly, the overlay precision measurement may be accurate.

In one embodiment, before forming the conductive material film, a third pattern layer (not shown) may be formed on the surface of the mask layer230, the mark opening216, the first mark trenches251and the second mark trenches262in the mark region. The third pattern layer may expose the device region240. The third pattern layer may be made of a transparent material.

In one embodiment, the conductive structure may be made of Cu; and an electro-chemical plating (ECP) process may be used to form the conductive structure. The process for forming the conductive material film may include forming a seed layer on the surface of the mask layer230, and the inner side surfaces of the first opening241and the second opening242; and forming the conductive material film by the ECP process until the first opening241and the second opening242are filled.

The seed layer may be made of a conductive material. The conductive material may be one or more of Cu, W, Al, Ag, Ti, Ta, TiN, and TaN, etc. The seed layer may be used as a conductive layer for the ECP process. Further, the seed layer may also be used as a barrier layer between the conductive structure and the dielectric layer220to prevent the metal atoms in the conductive structure from diffusing into the dielectric layer220. Various processes may be used to form the seed layer, such as a CVD process, a PVD process, or an ALD process, etc.

Thus, a mark structure may be formed by the disclosed methods and processes.FIGS. 8-9illustrate a corresponding mark structure.

As shownFIGS. 8-9, the mark structure includes a substrate200having a device region240and a mark region (not labeled). The mark region may include a first mark region250and a second mark region260surrounded by the first mark region250. The mark structure may also include a conductive layer211formed in the surface of the substrate200in the device region240; and a dielectric layer220formed on the surface of the substrate200and the surface of the conductive layer211. Further, the mark structure may also include a plurality of first mark trenches251formed in the dielectric layer220in the first mark region250; and a mark opening261and a plurality of second mark trenches262formed in the dielectric layer220in the second mark region260. Further, the mark structure may also include a conducive structure (not shown) formed in a first opening241and a second opening242in the dielectric layer220in the device region240. The detailed structures and intermediate structures are described above with respect to the fabrication processes.

FIGS. 10-14illustrate structures corresponding to certain stages of another exemplary fabrication process of a mark structure consistent with the disclosed embodiments. As shown inFIG. 10, at the beginning of the fabrication process, a substrate300is provided. The substrate300may include a mark region (not labeled) and a device region340. The mark region may include a first mark region350and a second mark region360. The first mark region350may surround the second mark region360.

The substrate300may include a device layer310; and a conductive layer311may be formed in the surface of the device layer310in the device region340. Further, a dielectric layer320may be formed on the surface of the device layer310and the conductive layer311. The dielectric layer320may include a barrier layer311formed on the surface of the device layer310and the surface of the conducive layer311, a first dielectric layer322formed on the barrier layer311and a second dielectric layer323formed on first dielectric layer322. Further, a mask layer330may be formed on the dielectric layer320. The detailed information of the substrate300, the dielectric layer320and the mask layer330may refer to the previous description of the structure illustrated inFIG. 5.

Further, as shown inFIGS. 11-12(FIG. 12is a top view of the mark region illustrated inFIG. 11), after forming the mask layer330, a first etching process may be used etch portions of the mask layer220and the dielectric layer320to form a first opening341in the device region340, a first mark (not labeled) in the first mark region350and a mark opening361in the second mark region360. The bottom of the first opening341and the bottom of the mark opening361may be higher than the surface of the device layer310. Further, the mark opening361may expose at least a portion of the dielectric layer320in the second mark region360.

The first mark may include a plurality of first mark protruding parts351. The plurality of first mark protruding parts351may be uniformly distributed around the second mark region360.

In one embodiment, the number of the first mark protruding parts351is four. The top of each first mark protruding part351may be stripe-shaped; and the four first mark protruding parts351may form a quadrangle. In one embodiment, the lengths of the four first mark protruding parts351are identical. Thus, the four first mark protruding parts351form a square. Further, the side surfaces of the first mark protruding parts351may be perpendicular to the surface of the dielectric layer320.

The process for forming the first mark protruding parts351, the mark opening361and the first opening341may include forming a first pattern layer301exposing the surface of the mask layer330in the entire second mark region360and portions of the surface of the mask layer330in the first mark region350and the device region340and covering the portions of the mask layer330corresponding to the first mark protruding parts351on surface of the mask layer330; and etching the mask layer330and the portions of the dielectric layer320by the first etching process using the first pattern301as an etching mask. Thus, the first mark protruding parts351, the mark opening361and the first opening341may be formed. After the first etching process, the first pattern layer301may be removed.

The first pattern layer301may be a patterned photoresist layer. In certain other embodiments, the first pattern layer301may be formed by a nano-imprinting process, or a self-assemble process.

In one embodiment, the first etching process may be an anisotropic dry etching process. By adjusting the carbon-to-fluoride ratio of the etching gas of the dry etching process, the etching selectivity of the dry etching process may be adjusted so as to enable the first etching process to have a relatively high etching rate to the mask layer330and the dielectric layer320.

During the first etching process for forming the first opening341and the first mark protruding structures351, the mark opening361may be formed simultaneously. The mark opening361may be used to subsequently form a second mark.

Further, as shown inFIGS. 13-14(FIG. 14is a top view of the mark region illustrated inFIG. 13), after forming the first opening341, the first mark protruding structures351and the mark opening361, a second opening342and a second mark (not labeled) may be formed. The second opening342may be formed in the dielectric layer320on the bottom of the mark opening361(as shown inFIG. 11). The second opening342may expose the device layer310.

The second mark may be formed in the dielectric layer320on the bottom of the mark opening361. The second mark may include a plurality of second mark trenches362. The plurality of second mark trenches362may be uniformly distributed around the center of the second mark region360.

In one embodiment, the number of the second mark trenches362is four. The top of each second mark trench362may be stripe-shaped; and the four second mark trenches362may form a quadrangle. In one embodiment, the lengths of the four second mark trenches362are identical. Thus, the four second mark trenches362form a square. Further, the side surfaces of the second mark trenches362may be perpendicular to the surface of the device layer310.

The process for forming the second mark trenches362and the second opening342may include forming a second pattern layer302exposing portions of the surface of the dielectric layer320corresponding to the second mark trenches362and the second opening342on the surface of the mask layer330; and etching the portions of the dielectric layer320by a second etching process using the second pattern layer302as an etching mask. Thus, the second mark trenches362and the second opening342may be formed. After the second etching process, the second pattern layer302may be removed.

The second pattern layer302may be a patterned photoresist layer. In certain other embodiments, the second pattern layer302may be formed by a nano-imprinting process, or a self-assemble process.

In one embodiment, the second etching process may be an anisotropic dry etching process. The etching rate of the first etching process to the mask layer330may be greater than the etching rate of the second etching process to the mark layer330.

In one embodiment, after the second etching process, an overlay mark measurement of the first mark and the second mark may be performed. If the offset of the first opening and the second opening matches the designed requirement, a conducive structure may be formed in the first opening341and the second opening342.

Thus, a mark structure may be formed by the disclosed methods and processes. The corresponding mark structure is illustrate inFIGS. 13-14.

As shownFIGS. 13-14, the mark structure includes a substrate300having a device region340and a mark region (not labeled). The mark region may include a first mark region350and a second mark region360surrounded by the first mark region350. The mark structure may also include a conductive layer311formed in the surface of the substrate300in the device region340; and a dielectric layer320formed on the surface of the substrate300and the surface of the conductive layer311. Further, the mark structure may also include a plurality of first mark protruding structures351formed in the dielectric layer320in the first mark region350; and a mark opening361and a plurality of second mark trenches362formed in the dielectric layer320in the second mark region360. Further, the mark structure may also include a conductive structure (not shown) formed in a first opening341and a second opening342in the dielectric layer320in the device region340. The detailed structures and intermediate structures are described above with respect to the fabrication processes.

Therefore, according to the disclosed processes and device structures, during etching the mask layer and the dielectric layer by a first etching process, not only a first opening may be formed in the device region, but also a first mark may be formed in the first mark region; and a mark opening may be formed in the second mark region simultaneously. Because the first etching process may be used to etch the mask layer, the etching raw of the first etching process to the mask layer may be relatively high. Thus, the bottom of the first opening may be lower than the surface of the dielectric layer and higher than the surface of the device layer; and the bottom of the mark opening may also be lower than the surface of the dielectric layer and higher than the surface of the device layer. The mark opening may open a process window for subsequently forming a second mark in the second mark region.

Further, because the second etching process may be used to etch the dielectric layer on the bottom of the first opening to expose the surface of the device layer, the etching rate of the second etching process to the dielectric layer may be relative large, but the etching rate of the second etching process to the mask layer may be relatively small. Because the mark opening in the second mark region may also expose a portion of the dielectric layer, the second etching process may be able to etch the dielectric layer in the mark region with an enough depth; and the patterns of the second mark may be clear. Thus, using the first mark and the second mark to perform an overlay mark measurement may be able to accurately obtain the relative offset between the first opening and the second opening. Accordingly, an auxiliary method may be provided to improve the fabrication processes of semiconductor devices.