System and method for implementing row redundancy with reduced access time and reduced device area

A system for implementing row redundancy in integrated circuit memory devices includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main subarrays including a set of support circuitry associated therewith. A discrete, redundant subarray is associated with the main subarrays, and also includes a set of support circuitry associated therewith. A common global bit line is shared by the main subarrays and the redundant subarray, and redundancy steering control circuitry is associated with the main subarrays and the redundant subarray. The redundancy steering control circuitry is configured such that word line activation of the main subarrays and the redundant subarray is performed in parallel with address compare operations performed by the redundancy steering control circuitry.

BACKGROUND

The present invention relates generally to integrated circuit memory devices and, more particularly, to a system and method for implementing row redundancy with reduced access time and reduced device area.

Memory devices are commonly employed as internal storage areas in a computer or other type of electronic equipment. One specific type of memory used to store data in a computer is random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM), for example. RAM is typically used as main memory in a computer environment. RAM is generally volatile, in that once power is turned off, all data stored in the RAM is lost.

As is the case with other types of integrated circuit devices, defects can occur during the manufacture of a memory array having rows and columns of individual memory cells. Typical defects can include, for example, bad memory cells, open circuits, shorts between a pair of rows and shorts between a row and column. In any case, defects can reduce the overall yield of the memory device manufacturing process. One way to address this problem, without discarding the memory device, is to incorporate redundant elements in the memory that selectively replace defective elements. For example, redundant rows are one type of redundant element that may be provided in memory to replace a defective primary row.

After a memory die has been manufactured, it is tested for defects. Generally with volatile memory, redundancy circuitry is used to selectively redirect access (address) requests from to the defective elements to the redundant elements. Redundancy circuitry may include, for example, electrical fuses that are selectively “blown” (open circuited) to electrically disconnect the defective rows. The redundant rows are then activated to replace the shorted rows. In addition, some memory devices may utilize non-volatile registers or fuse blocks to permanently store addresses of primary elements that are designated for replacement. The fuse blocks are typically coupled with redundancy control logic that compares address requests to addresses stored in the fuse blocks. If an address request matches an address stored in a fuse block, the redundant circuit directs or maps the access request to the redundant row instead of the defective row in the default or main array.

However, with respect to conventional approaches to row redundancy circuitry, there is typically a design tradeoff between the device real estate occupied by the circuitry and the access/setup time for implementing both the redundancy compare and memory access operations and/or repair efficiency of the redundant elements. Accordingly, it would be desirable to be able to implement a row redundancy scheme that reduces the impact on device area, and at the same time does not adversely affect access/address setup time or the repair efficiency of the elements.

SUMMARY

The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a system for implementing row redundancy in integrated circuit memory devices. In an exemplary embodiment, the system includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main subarrays including a set of support circuitry associated therewith; a discrete, redundant subarray associated with the one or more main subarrays, the redundant subarray also including a set of support circuitry associated therewith; a common global bit line shared by the one or more main subarrays and the redundant subarray; and redundancy steering control circuitry associated with the one or more main subarrays and the redundant subarray, wherein the redundancy steering control circuitry is configured such that word line activation of the one or more main subarrays and the redundant subarray is performed in parallel with address compare operations performed by the redundancy steering control circuitry.

In another embodiment, a method of implementing row redundancy in integrated circuit memory devices includes activating, based upon a presented address, a word line within one or more main subarrays and a discrete, redundant subarray associated with the one or more main subarrays; the one or more main subarrays and the redundant subarray each having word line, bit line and memory cell devices, and a set of support circuitry associated therewith, wherein the one or more main subarrays and the redundant subarray share a common global bit line; and performing, in parallel with the word line activation, an address compare operation using redundancy steering control circuitry; wherein, depending upon the result of the address compare operation, data output on the common global bit line is from either the one or more main subarrays or the redundant subarray.

DETAILED DESCRIPTION

Disclosed herein is a system and method for implementing row redundancy with low area overhead, low performance impact and low power impact. Briefly stated, a row redundancy system includes a discrete, redundant memory subarray (containing redundant-only wordlines) that is associated with the main memory subarrays. The redundant array is “integrated” with the other main (default) subarrays in the sense that a common global bit line bus is shared with the main array, thereby resulting in a seamless partition between a subarray in the main array and the redundant subarray. Since there are no separation gaps or logic dividing the main and redundant subarrays, all bussing structures, including data busses, can be shared between the two. As further described herein, the address compare logic does not contribute to word line activation time, but is instead coupled to the main/redundant array support circuitry so as to implement a “late” routing decision with respect to certain timing control signals associated with the subarray support circuitry.

Referring initially toFIG. 1, there is shown a schematic diagram of an existing row redundancy system100for memory devices. The system100may be applicable to various types of memory devices, such an SRAM array or a DRAM array, for example. The system100depicted inFIG. 1may be characterized as an “integrated row redundancy” scheme, in that each memory subarray102(e.g., Subarray_0. . . . Subarray_n), in addition to the main or “default” array104of word lines, bit lines and memory cells, is provided with its own individual redundant word line (WL) array106. By way of example, if each subarray102has 128 word lines in the default array104, then there may be a pair (2) of redundant word lines integrated within each subarray. A different number of redundant word lines may also be used, however.

As further depicted inFIG. 1, each subarray102also includes its own bit-switch/sense amplifier/global bit line driver circuitry108(also referred to herein as “support circuitry”). The support circuitry108for each subarray102is coupled to a common global bit line bus110, which in turn feeds input/output multiplexing and control logic circuitry112so that the requested memory information can be output to a requesting client or device (not shown), such as a processor for example.

In order to implement the row redundancy scheme for the system100inFIG. 1, steering control circuitry114is used. A requested address116is compared with stored fuse data in block118to determine whether the row address corresponds to one that was identified as defective, for each of the memory subarrays102. In the event that there is a match between the requested address116and any of the information stored in the fuse block118, the control circuitry causes an appropriate redundant word line in the redundant array106to be activated instead of the defective word line in the associated default array104.

More specifically, address compare logic120(e.g., exclusive OR (XOR) logic) determines whether the address bits match any of the bits stored in the associated fuse block118for each subarray102. At the same time, the address bits are decoded by word line decode circuitry122. However, it will also be seen that the decoded word line signals are gated by AND gates124before being allowed to pass through to (and hence activate) the word lines in the default arrays104. In turn, the decoded word line signals are gated when the value of the gating signal Red_Hit_N (redundancy hit negative) is high. Stated another way, the results of the comparison of the address data with data in the fuse block are entirely negative. This may be implemented, for example, through the use of NOR logic blocks126configured to compare the results of each output of the address compare logic120.

On the other hand, if there is an address match for one or more subarrays with respect to stored fuse block data, then the output of the associated NOR logic block126will be low, and the decoded word line signal will not be allowed to activate the defective word line in the associated subarray. Instead, the output of the address compare logic120will activate a redundant word line in the associated redundant word line array104.

Regardless of whether the address comparison operation results in a redundancy “hit” or “miss”, it will be seen from the system100ofFIG. 1that the word line activation (default array or redundant array) does not take place until the comparison is complete. In practical terms, this results in a speed penalty due to the propagation of signals through the address compare logic114prior to word line activation. Another disadvantage associated with the “integrated row redundancy” approach ofFIG. 1is that the repair efficiency of the redundant word lines, with respect to the size of the subarray is relative low. In other words, if a particular subarray has no defects, then the redundant word lines associated with that subarray will remain unused, since they are not configured to service any of the other subarrays in the memory device.

In contrast,FIG. 2is a schematic diagram of another conventional row redundancy system200for memory devices. As opposed to integrating word line redundancy directly into each subarray, the redundant word lines are formed as a separate subarray of the device. As more particularly shown inFIG. 2, the system200includes a plurality of memory subarrays202, labeled as Subarrays0through n. In addition, one of the subarrays202is labeled “redundant subarray.” The default subarrays each in turn include a default array204of word lines, bit lines and memory cells, as well as support circuitry208(e.g., bit-switch/sense amplifier/global bit line driver circuitry). Again, the default subarrays do not include any redundancy circuitry incorporated directly therein.

Similarly, the redundant subarray includes a redundant word line array206that can service any of the other default subarrays0through n. It will further be seen that the redundant subarray includes its own support circuitry therein, as is the case with the default subarrays. As a result, the plurality of subarrays0through n share a common default global bit line210a, which feeds a first set of input/output multiplexing and control logic circuitry212a. Because the redundant word lines are incorporated into a discrete subarray, the associated support circuitry208for the redundant subarray is coupled to a separate (redundant) global bit line210band a second set of input/output multiplexing and control logic circuitry212b. Switching between data from the default global bit line212aand the redundant global bit line212bis implemented through the use of a multiplexing device213.

In the redundancy approach ofFIG. 2, it will be seen that the redundancy steering control circuitry214is effectively decoupled from the word line decode logic, in that activation of the word lines in the subarrays O-n according to the presented address216does not wait for the results of the address comparison performed by logic214. Thus, there is no additional set up time penalty with respect to activating the word lines in the main or default array. In the event that the address compare circuitry (e.g., XOR logic220and OR logic226) determines that there is a match between any of the stored data in the fuse block218and the presented address216, then output signal Red_Hit (redundancy hit) is high, thereby causing multiplexing device213to output the data from the redundant global bit line210b.

The timing of the development of the output signal Red_Hit is before the data access for either the main or redundant array, and only a very small access time penalty is incurred from the muxing operation. The access to the redundant subarray happens later in time (after completion of the address compare). Furthermore, the redundant subarray has smaller bit line parasitics and thus its access time is actually faster than the main array. As such, the overall access time for the redundant array (i.e., the address compare time added to the relatively fast redundant array access time) is comparable to the access time of the main array.

However, notwithstanding the improvements in both speed and repair efficiency as compared to the system ofFIG. 1, the approach ofFIG. 2has its own drawbacks with respect to device area and power consumption. Because the discrete redundant subarray has its own support (bit-switch/sense amplifier/global bit line driver) circuitry208and its own input/output multiplexing and control logic circuitry212b, such an architecture occupies more device real estate and consumes more power.

Accordingly,FIG. 3is a schematic diagram of a row redundancy system300for memory devices with reduced access time and reduced device area, in accordance with an embodiment of the invention. The system300includes a plurality of main (default) memory subarrays302, labeled as Subarrays0through n. In addition, one of the subarrays302is labeled “redundant subarray.” The redundant subarray is a fast redundant array bank structure added adjacent to the default array banks. This allows for better array lithography and better power routing for the redundant array.

The default subarrays each in turn include a default array304of word lines, bit lines and memory cells, as well as support circuitry308(e.g., bit-switch/sense amplifier/global bit line driver circuitry). Similar to the approach ofFIG. 2, the default subarrays do not include any redundancy circuitry incorporated directly therein. However, as described in further detail below, system300(unlike system200ofFIG. 2) avoids the additional device area penalty associated withFIG. 2since there are no separation gaps or logic dividing the main and redundant subarrays. For example, all bussing structures (including data busses) can be shared between the main and redundant subarrays. This is reflected inFIG. 3, since both the main and redundant subarrays share a common global bit line bus310(Global_BL), and a single set of input/output multiplexing and control logic circuitry312. As a result, there is a seamless partition between a subarray in the main array and the redundant subarray.

Because the exemplary embodiment ofFIG. 3eliminates the use of separate global bit line and input/output multiplexing and control logic circuitry associated with a discrete redundant subarray, a novel approach to word line redundancy steering control is thus also shown inFIG. 3. More specifically, the redundancy steering control circuitry314associated with system300utilizes gating of the address compare results. However, whereas the conventional approach ofFIG. 1incorporates gating into the word line decode/activation signal path (thus resulting in additional word line activation time penalties), the approach ofFIG. 3incorporates gating of the address compare results into the bit-switch/sense amplifier/global bit line driver circuitry308of the main and redundant subarrays302, and in parallel with word line activation of the main and redundant subarrays.

During a read operation, the presented address316is decoded by the word line decode circuitry322associated with the main subarrays0through n. Again, the redundancy compare operations do not delay activation of the corresponding word line of each main subarray. Concurrently, the address316is compared with the programmed redundancy data in the fuse block318, and a redundancy solution is calculated in the address compare circuitry (e.g., XOR logic320and OR logic326). If a redundancy condition is determined, then an appropriate word line and the bit-switch circuitry in the redundant subarray are enabled. In addition, even though word line activation in the main subarrays is not gated off, the bit-switch selection and sense-amplifier devices308associated with the main subarray are gated off, through the use of gating logic (generally shown as324inFIG. 3). Conversely, if a redundancy condition is not determined based on the presented address316, then the bit-switch/sense amplifier/global bit line driver circuitry of the main subarrays is enabled by the gating of logic324, as described in further detail hereinafter. Correspondingly, the bit-switch/sense amplifier/global bit line driver circuitry of the redundant subarray is gated off. Complementary gating signals (R_Hit and R_Hit_N) are used to either pass or block, in an exemplary embodiment, each of three control signals: RBSN (read bit-switch), SET (sense amplifier set), and DLRST (data line restore).

Referring now toFIG. 4, there is shown a schematic diagram which illustrates the operation of the gating logic324with respect to the bit-switch/sense amplifier/global bit line driver circuitry308of the main and redundant subarrays in further detail. With respect to the support circuitry308, the exemplary embodiment gates three separate control signals as a prerequisite for transferring array data to the shared common global bit line310. For each of the three control signals, a first redundancy signal R_Hit_N (no redundancy condition) is used for the main subarrays, while a second redundancy signal R_Hit (redundancy condition) is used for the redundant subarray. As indicated above, R_Hit_N is the logical complement of R_Hit.

For each subarray302(including main and redundant subarrays), a first AND gate324agates local control signal RBSN, which corresponds to read bit-switches in the support circuitry308. In the illustrated embodiment, the read bit-switches are implemented as PFET devices402, which selectively couple one of a group of bit lines of the subarray to a sense amplifier, generally indicated at404. The global control signal (G_RBSN) for activating read bit-switches402is gated by R_Hit_N (no redundancy condition) in the case of the main subarrays, and by R_Hit (redundancy condition) in the case of the redundant subarray.

In addition to gating the read bit-switch control signals for each subarray, a second AND gate324bis used to gate local control signal DLRST, which is used to deactivate a restoring (or precharging) of the sense amp data lines. When DLRST is low, PFET devices406precharge the data lines of the sense amplifier404to a logical high value. Thus, in order to capture array data into a sense amplifier, DLRST transitions to a high value to switch off PFETs406and allow a signal developed on the bit lines to be transferred to the data lines of the sense amplifier. Accordingly, the global data line restore signal (G_DLRST) is fed to the set of second AND gates324b. Further, for each subarray, a third AND gate324cis used to gate local control signal SET, which is used to couple the sense amplifier404to a low power supply rail (e.g., ground) and enable the data on the data lines to be latched into the sense amplifier itself. Thus, the global sense-amplifier set signal (G_SET) is fed to the set of third AND gates324c.

Referring now to bothFIG. 3andFIG. 4, an exemplary operation of the support circuitry308, in view of the redundancy steering control circuitry314disclosed herein, may be summarized as follows. During the access time for the main and redundant subarrays, a corresponding word line therein is activated such that bit line signal development initiates with the corresponding bit-switches402disabled. The redundancy calculation of steering control circuitry314occurs in parallel with the bit line signal development and, when completed, a logical high value is generated on either R_Hit (redundancy condition) or R_Hit_N (no redundancy condition). In either instance, this signal enables a “late” selection of the local read bit-switch (RBSN) signals of either the main subarrays or the redundant subarray, as well as a deselection of the appropriate data line restore (DLRST) local control signals. In turn, the signal developed on the bit lines of the subarray (due to uninhibited word line activation) is transferred to the data lines. The gated sense amplifier SET signal fires shortly after. Because the global bit line310is shared between main and redundant arrays, the signal SET is also gated with redundancy-enable information.