Methods of forming NAND flash memory with fixed charge

A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.

CROSS-REFERENCE TO RELATED APPLICATION

This application is related to U.S. patent application Ser. No. 11/692,958, entitled “NAND Flash Memory With Fixed Charge”, filed on the same day as the present application. This application is incorporated in its entirety by reference as if fully set forth herein.

BACKGROUND OF THE INVENTION

This invention relates to nonvolatile memories and methods of forming nonvolatile memories. In particular, this application relates to nonvolatile memory arrays in which a series of floating gate memory cells are electrically connected in series.

Nonvolatile memory systems are used in various applications. Some nonvolatile memory systems are embedded in a larger system such as a personal computer. Other nonvolatile memory systems are removably connected to a host system and may be interchanged between different host systems. Examples of such removable memory systems include memory cards and USB flash drives. Electronic circuit cards, including non-volatile memory cards, have been commercially implemented according to a number of well-known standards. Memory cards are used with personal computers, cellular telephones, personal digital assistants (PDAs), digital still cameras, digital movie cameras, portable audio players and other host electronic devices for the storage of large amounts of data. Such cards usually contain a re-programmable non-volatile semiconductor memory cell array along with a controller that controls and supports operation of the memory cell array and interfaces with a host to which the card is connected. Several of the same type of card may be interchanged in a host card slot designed to accept that type of card. However, the development of the many electronic card standards has created different types of cards that are incompatible with each other in various degrees. A card made according to one standard is usually not useable with a host designed to operate with a card of another standard. Memory card standards include PC Card, CompactFlash™ card (CF™ card), SmartMedia™ card, MultiMediaCard (MMC™), Secure Digital (SD) card, a miniSD™ card, Subscriber Identity Module (SIM), Memory Stick™, Memory Stick Duo card and microSD/TransFlash™ memory module standards. There are several USB flash drive products commercially available from SanDisk Corporation under its trademark “Cruzer®.” USB flash drives are typically larger and shaped differently than the memory cards described above.

Different types of memory array architecture are used in nonvolatile memory systems. In one type of architecture, a NAND array, a series of strings of more than two memory cells, such as 16 or 32, are connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be over driven so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell.

SUMMARY OF THE INVENTION

A NAND flash memory array according to an embodiment of the present invention comprises: a plurality of floating gate memory cells connected in series by conductive source/drain regions, an individual floating gate memory cell including a floating gate and a fixed charge layer portion, the fixed charge layer portion located between the floating gate and an underlying substrate surface.

A NAND flash memory die according to an embodiment of the present invention comprises: a plurality of NAND strings formed on the die, an individual NAND string including floating gate memory cells connected together in series, an individual floating gate memory cell having a first fixed charge located between a floating gate and an underlying channel region, the first fixed charge affecting the threshold voltage of the floating gate memory cell, the floating gate memory cell having two control gates coupled to the floating gate.

A method of forming a NAND flash memory array according to an embodiment of the present invention comprises: forming a fixed charge layer that extends over a surface of a substrate; forming a plurality of floating gates overlying the fixed charge layer; and forming a plurality of conductive source/drain regions in areas of the substrate between floating gates, the source/drain regions connecting memory cells in series as a NAND string.

A method of forming a NAND flash memory according to an embodiment of the present invention comprises: forming a dielectric layer over a surface of a substrate; performing a plasma nitridation process on the dielectric layer; forming a plurality of floating gates over the nitrided dielectric layer; and forming a plurality of control gates that are individually interposed between neighboring floating gates of the plurality of floating gates.

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

FIG. 1shows a cross section of a NAND flash memory string100that has control gates81-84extending on both sides of floating gates33-35(this type of array is sometimes referred to as ENAND). Examples of such strings and methods of forming them are described in U.S. Pat. No. 6,888,755. In string100ofFIG. 1a floating gate is coupled to two control gates, one on either side of the control gate (e.g. floating gate34is coupled to control gates82and83). This is in contrast to a common memory design where a control gate overlies a floating gate so that each floating gate is coupled to only one control gate. A memory string such as that ofFIG. 1may be formed as part of a memory array having many strings. Neighboring strings may be isolated from each other by Shallow Trench Isolation (STI) structures, or other means (not shown inFIG. 1). In some cases, individual stings may have 8, 16, 32 or more memory cells connected together in series. Select gates45,51are provided at either end of string100and are connected to select lines80,85to allow string100to be connected to circuits used for accessing the memory cells of string100. Floating gates33-35are separated from substrate77by a gate dielectric (tunnel oxide) layer91overlying substrate surface79.

In string100ofFIG. 1, source/drain regions57,62,67,72,105,106are provided in substrate77on either side of floating gates. Source/drain regions57,62,67,72,105,106are shared by neighboring memory cells and provide an electrically conductive pathway between memory cells so that the memory cells in string100may be connected in series. Source/drain regions57,62,67,72,105,106ofFIG. 1are formed by implantation using floating gates33-35and select gates45,51to provide a mask so that source/drain regions57,62,67,72,105,106are self-aligned to floating gates33-35and select gates45,51. Control gates81-84are then formed by depositing a conductive layer (e.g. doped polysilicon) and removing the conductive material where it overlies floating gates33-35and select gates45,51so that conductive material remains between floating gates33-35. Thus, control gates81-84may be considered to be self-aligned to floating gates33-35. Control gates81-84are separated from floating gates33-35by an interlayer dielectric layer103. Control gates81-84extend in the direction perpendicular to the cross section shown and control gates of neighboring strings are connected together as word lines. Thus, a word line is a conductive element that extends through multiple strings and forms control gates where it couples to floating gates of individual strings. A control gate may couple to the underlying substrate to form a transistor where it overlies a source/drain region. By biasing a control gate, a source/drain region may be made more conductive or less conductive. Thus, the source/drain region in a memory of this type (having a control gate close to the substrate, not just overlying the floating gate) may be considered as the channel of a transistor that has the control gate as its gate. In some cases, control gate bias may be sufficient to create an inversion layer that acts as a conductive source/drain region without requiring a source/drain implant.

When an architecture such as that ofFIG. 1is scaled to small dimensions (e.g. gate length less than 45 nanometers) certain device characteristics may be negatively impacted. Problems encountered as a result of diminished channel length may be referred to as “short channel effects.” Short channel effects may be caused by implanted dopant in a source/drain region reducing the effective gate length and causing variation in effective gate length. This problem may be mitigated by reducing the amount of dopant implanted. However, less dopant results in higher resistivity and thus higher source/drain resistance, which is generally undesirable. Reduction in post implant anneal thermal cycle may also help to mitigate the problem, but does not generally eliminate short channel effects.

U.S. patent application Ser. Nos. 11/626,778 and 11/626,784 describe NAND flash memory arrays and methods of forming NAND flash memory arrays using fixed charge layer portions over source/drain regions. Such fixed charge layer portions may cause charge carriers in the underlying substrate to be drawn towards the substrate surface where they form an electrically conductive layer in the source/drain regions. Thus, source/drain regions may be made conductive, or more conductive, using fixed charge. Use of a fixed charge layer portion in this way may replace use of source/drain implantation or may be used in addition to source/drain implantation. An inversion layer is formed near the surface in the source/drain regions when an electrical charge is in close proximity, the electrical charge drawing charge carriers to the surface where they form a conductive layer. Such an electrical charge may cause a flat band voltage shift and inverts the surface. A fixed interface charge may induce enough band bending to invert the surface to form a conduction channel.

FIG. 2shows a cross section of a NAND string200according to an embodiment of the present invention. A fixed charge layer202extends over a surface204of a substrate206. Fixed charge layer202affects the band bending in the conductive channel regions, thereby altering their inversion threshold voltages.FIG. 2shows a dielectric layer208extending between fixed charge layer202and substrate surface204, though in other examples a fixed charge layer may directly overlie a substrate surface without an intervening dielectric layer. Floating gates210a-cand control gates212a-care formed over fixed charge layer202. Thus, inFIG. 2fixed charge layer202extends under both control gates212a-cand floating gates210a-cto cause formation of a conductive layer214that is continuous along NAND string200in the cross section ofFIG. 2(subject to biases applied to overlying control gates212a-c). Where conductive layer214extends under control gates212a-c, conductive layer214forms conductive source/drain regions (instead of source/drain implantation or in addition to source/drain implantation). Where conductive layer214extends under floating gates210a-c, conductive layer214forms the channels of the floating gate cells (instead of channel implantation or in addition to channel implantation). It will be understood that conductive layer214is also affected by control gates212a-cand floating gates210a-cso that conductive layer214may not be electrically conductive for all conditions. Conductive layer214also extends under select gate216where it forms the channel of a select transistor. In the example ofFIG. 2, no separate source/drain implanted regions are needed because the source/drain regions are sufficiently conductive as a result of overlying fixed charge layer202. Also, no separate channel (or threshold voltage) implant is needed because the channel is sufficiently conductive (has a desirable threshold voltage) as a result of overlying fixed charge layer202. In other examples, a fixed charge layer may be provided in addition to one or more implants used to affect the conductivity of portions of a substrate.

In addition to being used in a NAND array as shown, a fixed charge layer according to an embodiment of the present invention may be formed in peripheral circuits that are connected to the NAND array. Various devices in peripheral circuits may have a fixed charge layer portion to provide an appropriate threshold voltage. For example, logic circuits may be provided on the same die as a NAND memory array and transistors within such logic circuits may include fixed charge layer portions overlying channel regions or other regions. In some cases, a controller and a NAND flash memory may be formed on the same die. Such a controller may include devices that have fixed charge layer portions.

The amount of charge contained in a given portion of a fixed charge layer (charge per unit area) may be selected according to the desired device characteristics. Also, the type of charge, positive or negative, may be chosen according to the desired result. For example, in an NMOS device, a fixed charge layer may have positive charge, which attracts negatively charged electrons towards the surface of the substrate in the channel region. This has the effect of reducing the threshold voltage of the device. Where the charge per unit area of the fixed charge layer is sufficiently high, the channel region may be inverted with no bias on the gate (VGS=0) so that the device operates in depletion mode. Where a fixed charge layer containing negative charge is located over the channel region of an NMOS device, the threshold voltage of the device may be increased. In the case of PMOS devices, the effects of positive and negative charge over the channel are reversed.

Fixed charge layers may be formed in a variety of ways using a variety of materials. Materials may include Hf-rich Hafnium oxide, Zr-rich Zirconium oxide, Silicon nitride, nitrided Silicon dioxide or some combination of these or other materials. Fixed charge layers may be formed by plasma deposition, plasma nitrification, plasma oxidation, chemical vapor deposition, atomic layer deposition, rapid thermal processing, ion implantation or other techniques. A fixed charge layer may contain charge as-deposited or may have charge added after deposition (such as by plasma processing). In some cases, a fixed charge layer has charge as-deposited and subsequently has additional charge added. In one example, nitridation of a Silicon dioxide surface results in a nitrided Silicon dioxide that contains positive charge. A fixed charge layer may result where surface states are created on a substrate by a process such as a plasma deposition process. After a fixed charge layer is formed, the charge located in the fixed charge layer generally remains unchanged (fixed) during the lifetime of the device and is not significantly affected by voltages normally used in the device.

A fixed charge layer may be patterned in some manner so that fixed charge layer portions remain only where desired. For example, as shown inFIG. 3, fixed charge layer portions320a-dmay be desired under floating gates322a-cbut not under control gates324a-c. In this case, a separate source/drain implant may form source/drain regions326a-c. A fixed charge layer may be deposited as a blanket layer over the entire substrate328and later etched to remove portions that are not needed. For example, floating gates322a-cmay be used as a mask layer to pattern the fixed charge layer, leaving fixed charge layer portions320a-conly under floating gates322a-cand under select gate330. Other patterning schemes may also be used. WhileFIG. 3indicates that no fixed charge remains under control gates324a-c, in other cases the fixed charge layer may be reduced but not completely removed at these locations. Thus, some of the fixed charge layer may be removed, leaving a smaller amount of charge per unit area under control gates than under floating gates. Alternatively, additional processing (e.g. nitridation or implantation) may be performed to add charge to fixed charge layer portions under control gates. Other mask layers may also be provided to allow increased or decreased charge per unit area for particular regions. Such addition and removal of charge may be used to form fixed charge portions having a range of charge per unit area for different purposes.

FIGS. 4-6show a process for forming a NAND flash memory array, using a fixed charge layer, according to an embodiment of the present invention. Other processes may also be used to form a NAND flash memory array.FIG. 4shows a portion of a substrate440at an early stage of fabrication of a NAND memory array. Substrate440is a Silicon substrate that may be lightly doped and have appropriately doped wells formed near a surface442to isolate the active region from the underlying bulk. A dielectric layer444is formed on surface442of substrate440. In the example shown, dielectric layer444is a Silicon Dioxide (oxide) layer that is grown on substrate440. Dielectric layer444may be grown in a furnace in a similar process to that used for forming a conventional tunnel oxide.

Subsequent to forming dielectric layer444, a nitridation process is performed that nitrides dielectric layer444. The plasma nitridation process may be performed using conventional plasma deposition equipment such as a Dual Plasma Nitride (DPN) chamber from Applied Materials, a Slot Plane Antenna (SPA) chamber from Tokyo Electron Limited (TEL), Modified Magnetron Typed (MMT) system from Hitachi Kokusai Electric or other plasma processing equipment. In one example a MMT system performs a nitridation process using the following conditions: Temperature=350 degrees Centigrade; Pressure=50 Pascals; Gas=Nitrogen (N2); RF Power=250 Watts. The result of the nitridation is that a fixed charge layer446is formed. Fixed charge layer446may include Silicon nitride and nitrided Silicon dioxide. Positively charged species are incorporated into nitrided surfaces. Generally, the charge incorporated into nitrided surfaces in this manner is not free to move because the nitrided surface is not electrically conductive, so the charge remains fixed in place. Thus, a nitrided surface formed in this way may be considered a fixed charge layer. Nitridation of dielectric layer444may at least partially consume dielectric layer444. WhileFIG. 4shows dielectric layer444remaining after nitridation, in other cases no unnitrided dielectric may remain so that a fixed charge layer is formed directly over the substrate surface. In some cases, the location of the fixed charge within a dielectric layer may be controlled by adjusting a bias voltage applied to the substrate (or to a chuck on which the substrate sits) during plasma nitridation. Thus, a fixed charge layer may be formed directly on the substrate surface or at a chosen distance from the substrate surface.

In an alternative embodiment, a fixed charge layer may be formed by implanting ions into a dielectric layer, such as a Silicon Dioxide layer. The depth of an implanted layer may be controlled by adjusting implant energy so that the distance between the fixed charge layer and the substrate may be chosen. In an alternative embodiment, a fixed charge layer is formed by deposition of a material that contains a fixed charge as-deposited, without requiring additional processing such as plasma processing or implantation as previously described. While these techniques may be considered as alternative methods of forming a fixed charge layer, they may also be combined so that, for example, a layer may be deposited containing a fixed charge as-deposited and may then be subject to additional processing (e.g. nitridation or implantation) to add more charge. Charge may also be removed, for example by etching away some or all of the fixed charge layer.

Subsequent to the nitridation of dielectric layer444, a layer of conductive floating gate material is deposited over fixed charge layer446. In the present example, doped polysilicon is used as the floating gate material. The floating gate material is subsequently patterned using a hard mask pattern. A hard mask pattern may be formed using a conventional lithographic process where a photoresist layer is patterned and the pattern transferred to a hard mask layer. This produces hard mask portions that are as small as the minimum feature size of the lithographic process used. Alternatively, a spacer scheme may be used to form hard mask portions that are smaller than the minimum feature size of the lithographic process. Examples of such spacer schemes are provided in U.S. Pat. No. 6,888,755.FIG. 5shows hard mask portions448a-dformed using a spacer scheme and subsequently used to pattern the floating gate layer into floating gate portions450a-d. In particular, the floating gate layer is patterned by performing an anisotropic etch while hard mask layer portions448a-dare in place over the floating gate layer. The etch stops at the fixed charge layer446. An etch may be used that is selective to polysilicon over nitrided Silicon Dioxide so that little or no etching of the nitrided dielectric layer occurs.

In an alternative embodiment, a fixed charge layer is also etched at this point. Nitrided dielectric material of a fixed charge layer may be completely removed where it is exposed between remaining portions of floating gate material, or may be only partially removed. By performing partial removal, the fixed charge per unit area in the exposed portions of the fixed charge layer may be reduced to a chosen level. Thus, the fixed charge per unit area under remaining floating gate material may be greater than the fixed charge per unit area elsewhere. Complete removal of exposed fixed charge layer portions may be followed by deposition of replacement fixed charge layer portions. For example, where a nitrided dielectric layer is used to fix positive charge under floating gates, it may be desirable to have negative charge between floating gates. So, the nitrided dielectric layer is removed in these areas and is replaced by another fixed charge layer that contains negative charge. Charge may also be added to exposed portions of a fixed charge layer at this point if desired so that the charge per unit area is increased over source/drain regions. For example, additional nitridation may be performed, or ions may be implanted to alter the charge per unit area in exposed portions of a fixed charge layer. It should be noted that remaining floating gate portions450a-dofFIG. 5may be individual floating gates at this point if Shallow Trench Isolation (STI) structures are already formed (STI structures separating floating gates in the direction perpendicular to the cross section shown). Alternatively, separation of remaining floating gate portions450a-dinto individual floating gates may occur later when STI structures are formed.

Subsequent to patterning the floating gate material, an interlayer dielectric layer652is formed over the structure ofFIG. 5as shown byFIG. 6. In the present example, the interlayer dielectric layer652is a compound layer formed of a Silicon Dioxide (Oxide) layer, followed by a Silicon Nitride (Nitride) layer, followed by a second Silicon Dioxide (Oxide) layer. Such an Oxide-Nitride-Oxide (ONO) layer provides insulation between floating gates and control gates. In the present example a low thermal cycle ONO is used so that there is little or no diffusion of charge from the fixed charge layer. Other dielectric materials may also be used to form an interlayer dielectric layer in some cases.

Subsequent to formation of interlayer dielectric layer652an electrically conductive control gate material754is deposited as shown inFIG. 7. In the present example, the control gate material754is doped polysilicon (similar to the floating gate material), though other conductive materials may also be used. Control gate material754is deposited to a thickness that is sufficient to fill the gaps between remaining floating gate portion450a-d.

Subsequent to deposition of control gate material754, excess control gate material is removed as shown inFIG. 8. In the present example, removal of excess material is achieved by etching back control gate material754. The removal of excess control gate material results in the formation of separate control gates856a-cbetween floating gates450a-d. In other examples, Chemical Mechanical Polishing (CMP) or other processes may be used to remove excess control gate material. In some cases, STI structures are formed at this point to isolate adjacent NAND strings in the word line direction. In this case, word lines extending over control gates are added to connect control gates in the word line direction. Such word lines may be formed by conventional patterning of conductive material. In the example shown, no additional word lines are needed because control gates856a-cconnect from one string to another to form word lines.FIG. 8also shows a negative charge layer858that extends under floating gates450a-cand control gates856a-cof the NAND string. A negative charge layer858is formed by electrons that are attracted to surface442of substrate440by positive charge in overlying fixed charge layer446.

FIG. 9shows an alternative structure in which floating gates960a-din a NAND string are formed having an inverted-T shape in cross section. Examples of such floating gates and their formation are described in US Patent Application Publication No. 20050199939 and U.S. Pat. No. 7,026,684.FIG. 9shows a nitrided dielectric forming a fixed charge layer962underlying both floating gates960a-dand control gates964a-cas before so that fixed charge affects underlying substrate966. Subsequent to forming fixed charge layer962, floating gates960a-cand control gates964a-cmay be formed according to any suitable scheme to form floating gates having an inverted-T shape.

A fixed charge layer may be incorporated in any integrated circuit (memory or other circuit) by performing nitridation or other processing to place charge in a gate dielectric layer. Subsequent processing may be carried out as before, or with some adjustment for thermal budget etc. In the example ofFIG. 10, a NAND memory string1000has control gates1002a-dlying over floating gates1004a-d(one control gate coupled to a floating gate). A fixed charge layer1006holding positive charge extends across substrate1008so that fixed charge layer portions are present on substrate1008under floating gates1004a-dand also between floating gates1004a-d. The presence of fixed charge layer1006causes electrons to be drawn to the underlying channel and source/drain regions where they form a layer of negative charge1010as shown. Source/drain and channel implants may also be provided in this type of structure to provide added control of threshold voltage and to reduce resistance of source/drain regions.

In other examples, fixed charge layer portions are used in devices that do not include floating gates, such as logic devices used in peripheral areas of memory arrays. The use of fixed charge in such locations may be in place of, or in addition to, the use of implanted dopants to control threshold voltage. In some nonvolatile memory cells, charge trapping structures are used instead of conductive floating gates so that the state of a cell depends on the charge trapped in such a structure. Fixed charge layers may be used under such structures in a similar manner to their use under conductive floating gates.

All patents, patent applications, articles, books, specifications, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of a term between any of the incorporated publications, documents or things and the text of the present document, the definition or use of the term in the present document shall prevail.

Although the various aspects of the present invention have been described with respect to certain preferred embodiments, it is understood that the invention is entitled to protection within the full scope of the appended claims.