Flexible time stamping

In an example embodiment, an apparatus comprising a physical layer processing device that comprises logic configured to process a packet received from a physical layer interface is disclosed. The physical layer processing device logic is further configured to determine a preamble portion of the packet and a data portion of the packet. The physical layer processing device logic is further configured to insert a timestamp into the preamble portion of the packet. The physical layer processing device logic forwards the packet with the timestamp inserted into the preamble.

TECHNICAL FIELD

The present disclosure relates generally to determining when data packets are sent and/or received.

BACKGROUND

The accurate recording of a time a packet is sent or received is desirable for many applications. Timestamps can be used by network administrators for network diagnostics. For wireless networks, accurate time stamping can be useful for acquiring accurate location data for wireless nodes. Time stamping is also frequently employed in financial transaction and is used in industrial applications such as automation and control systems and power generation, transmission and distribution.

The most accurate place to time a packet is at the Physical Layer (PHY) interface or at the Media Access Control (MAC)/PHY interface where no flexible parsing occurs (for example the PHY or MAC cannot determine whether the timestamp can be discarded). The MAC is can be somewhat accurate if there are no PHY delays, but like the PHY no flexible parsing occurs. A forwarding controller (FC) or Central Processing Unit (CPU) coupled to the MAC can allow for flexible parsing, but is usually not accurate enough because of delays and jitter between the PHY, MAC and FC. Further complicating the problem is that devices such as switches frequently employ multiple PHY interfaces which should be synchronized.

OVERVIEW OF EXAMPLE EMBODIMENTS

In accordance with an example embodiment, there is disclosed herein an apparatus comprising a physical layer processing device that comprises logic configured to process a packet received from a physical layer interface is disclosed. The physical layer processing device logic is configured to determine a preamble portion of the packet and a data portion of the packet. The physical layer processing device logic is further configured to insert a timestamp into the preamble portion of the packet. The physical layer processing device logic forwards the packet with the timestamp inserted into the preamble.

In accordance with an example embodiment, there is disclosed herein a method comprising receiving a packet at a physical layer interface, that has a preamble. A timestamp is inserted into the preamble of the packet at the physical layer interface. The packet is forwarded with the inserted timestamp to a media access control interface. The packet and the timestamp are forwarded from the media access control interface to a processor.

DESCRIPTION OF EXAMPLE EMBODIMENTS

This description provides examples not intended to limit the scope of the appended claims. The figures generally indicate the features of the examples, where it is understood and appreciated that like reference numerals are used to refer to like elements. Reference in the specification to “one embodiment” or “an embodiment” or “an example embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment described herein. The appearances of the phrase “in one embodiment” or “in one or more embodiments” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Features and aspects of various embodiments may be integrated into other embodiments, and embodiments illustrated in this document may be implemented without all of the features or aspects illustrated or described.

Referring toFIG. 1there illustrated a Physical Layer (PHY) processing device100such as a local area network interface (e.g. Ethernet), modem or digital signal processor. PHY100typically performs digital signal processing, such as analog-to-digital and digital-to-analog conversion, and encoding/decoding of waveforms (modulation/demodulation). The digital signal processing can be done with general purpose digital signal processing integrated circuits, or in specially designed digital logic. In either case, PHY100is modulating/demodulating data to be compatible with the appropriate communication standard. For example for wireless devices, the Institute of Electrical and Electronic Engineers (IEEE) 802.11a standard uses Orthogonal Frequency Domain Modulation (OFDM), while the IEEE 802.11b standard employs Direct Sequence Spread Spectrum (DSSS). Data is sent and/or received on the physical layer via a physical layer interface (IF)104. On one side of PHY100, data is exchanged with a Network IF, such as a Media Access Control (MAC) processor via Network Interface (NIF)102. PHY100may suitably comprise analog-to-digital (A/D) converters for data received from Physical Layer IF104, and digital-to-analog (D/A) converters for data transmitted to Physical Layer IF104.

In accordance with an example embodiment, PHY100comprises a clock module108comprising logic for maintaining time. “Logic,” as used herein, includes but is not limited to hardware, firmware, software and/or combinations of each to perform a function(s) or an action(s), and/or to cause a function or action from another component. For example, based on a desired application or need, logic may include a software controlled microprocessor, discrete logic such as an application specific integrated circuit (ASIC), a programmable/programmed logic device, memory device containing instructions, or the like, or combinational logic embodied in hardware. Logic may also be fully embodied as software. Timestamp logic106located between Physical Layer IF104and NIF102(the interface between the PHY100and a Network Layer processing device or a MAC processing device), as will be described in more detail herein, is configured to timestamp packets that are sent and/or received on Physical Layer IF104.

In operation, as a packet is being received on Physical Layer IF104, timestamp logic106is responsive to determine a preamble portion of the packet and a data portion of the packet.FIG. 5illustrates an example of a packet700comprising a preamble portion702and a data portion704. The preamble portion702comprises a start of packet (SOP) bit or bits706and a start frame delimiter (SFD)710, which indicates the beginning of the data portion704. The portion of the packet indicated by708corresponds to bits for one or more fields for use by the physical layer processor such as Operations Administration and Maintenance (OAM) bits, application specific bits and header Cyclic Redundancy Check (CRC) bits.

After the physical layer processing device100has processed the preamble portion702of packet700, timestamp logic106acquires the current time from clock108and inserts a timestamp into the preamble portion702of the packet700. For example, the timestamp may be inserted at bits708in preamble702. The timestamp corresponds to the current time acquired from clock108. Additional information may also be inserted at bits706, such as a signature associated with the timestamp and/or other timestamp data, such as resolution. The packet700with the timestamp inserted into the preamble702is then forwarded on NIF102to a network interface processor, such as a media access control (MAC) processor.

In an example embodiment, additional data is inserted into the preamble to provide further information about the timestamp. For example, a predefined bit may be set to inform the network interface processor data about the format and/or resolution of the timestamp.

In an example embodiment, as packets are received via NIF102, timestamp logic106determines from inspecting the packet whether a timestamp corresponding to the time the packet was transmitted via the Physical Layer IF104is requested. For example, timestamp logic106may ascertain whether a time-bit and/or signature are indicated within bits708of the preamble portion702of a packet700. As another example, data may be pre-appended or appended onto the data portion704of a packet700to enable timestamp logic106to determine whether a process (or processor) desires to receive a timestamp indicating when the packet700was sent through Physical Layer IF104. In particular embodiments, a frame identification (frame ID) field may be included with the packet.

If timestamp logic106determines a timestamp is requested for a packet, such as a packet similar to packet700, timestamp logic106stores the time when the packet is sent via Physical Layer Interface104. The time is acquired from clock108. The timestamp may held in storage accessible to an external device, such as a CPU, to allow the external device to acquire the timestamp. In an example embodiment, the timestamp is stored in a first-in-first-out (FIFO) buffer for retrieval by the processor requesting the timestamp.

In an example embodiment, processing logic (not shown) within physical layer interface device100is in communication with the processor requesting the timestamp. This allows a signal to be sent from physical layer processing device100to the processor requesting the timestamp.

In example embodiments, a frame ID associated with the packet is stored with the timestamp. The frame ID can assist a processor in locating the correct timestamp.

In an example embodiment, timestamp logic106synchronizes clock108based on received external signals. For example, as packets arrive through NIF102, the timestamp on the packet from the network interface processor is acquired, and the timestamp is adjusted for the delay between the network interface processor and timestamp logic106. Clock108is updated based on the adjusted timestamp from the packet received on NIF102. As another example, an external device, such as a CPU (not shown), may send a signal requesting the current time of clock108. Timestamp logic106acquires the current time from clock108and stores it in a predetermined data storage, such as a register or FIFO, or timestamp logic106sends a signal to the requesting device with data representative of the current time acquired from clock108. Timestamp logic106may receive a signal from the external device indicating that clock108should be adjusted. The signal may comprise data indicating an amount of time to increment or decrement clock108or data indicating a new setting for clock108.

FIG. 2illustrates an example of a device200with a single CPU204and a single PHY100. PHY100is configured in accordance with at least one example embodiment described inFIG. 1. PHY100is coupled to MAC processor202. MAC202can act upon the data, for example, by encrypting or decrypting it, or by interpreting the data and making decisions as to how and when to forward it. CPU204may provide for application layer or other processing of data.

Incoming packets from the physical media are received by PHY100. PHY100associates a timestamp into the packet. For example a timestamp can be inserted into the preamble of the packet. As another example, a timestamp can be pre-appended or appended onto the packet.

Media access control (MAC) processing device202is in communication with PHY100. MAC202receives the packet with the timestamp from PHY100. MAC202comprises logic for processing the packet and timestamp received from PHY100. MAC202is configured to forward the packet and the timestamp to CPU204.

CPU204then parses the packet as received from MAC202. Upon parsing the packet, CPU204can determine whether the timestamp received with the packet should be retained or discarded. In an example embodiment, MAC202forwards the timestamp in preamble of the packet (which may or may not be the same preamble that PHY100inserted the timestamp into) and CPU204acquires the timestamp from the preamble of the packet.

In an example embodiment, CPU204sets a predefined time-bit on an outgoing packet for transmission by PHY100if CPU204wants to know when the packet was actually sent.

The packet is forwarded from CPU204to MAC202. MAC202performs any desired network processing, for example a MAC address header may be added and/or MAC layer encryption may be performed, and the packet is forwarded to PHY100with the time-bit set. PHY100is responsive to receiving the packet with the time-bit to store the time that the packet is transmitted from PHY100. The timestamp may be stored in any suitable data storage device, such as a register or FIFO that enables CPU204to acquire the timestamp for the packet. In an example embodiment, PHY100suitably comprises logic to send the timestamp to CPU204.

In an example embodiment, CPU204may further include a signature with the time-bit. In particular embodiments, CPU204includes a frame ID with the packet. The signature and/or frame ID are forwarded from CPU204to MAC202and from MAC202to PHY100. PHY100removes the frame ID and/or signature from the packet before transmission. In an example embodiment, MAC202and CPU204are implemented by a single device, e.g. a single CPU that performs both functions.

FIG. 3illustrates an example of a device300with multiple physical layer processing circuits302,304,306. Device300illustrates a configuration suitable for implementing a switch. Although the example embodiment illustrated inFIG. 3employs three physical layer processing circuits302,304,306, this should not be construed as limiting the principles described herein to devices with three physical layer processing circuits as the principles described herein can be adapted to devices having any physically realizable number of physical layer processing devices. Similarly, the principles described herein are suitable for devices having any physically realizable number of stack/CPU interfaces.

Physical layer processing devices302,304,306may be configured in accordance with any of the example embodiments described herein, such as for example were described for PHY100inFIG. 1. PHY processing devices302,304,306are coupled to a MAC processing device308(“MAC308”). MAC308is coupled to a forwarding controller (FC)310. FC310is configured to perform layer2, layer3and/or layer4(or any higher layer such as layers5,6and/or7) processing of packets to and from MAC308. In an example embodiment, memory (MEM)312is employed to transfer packets between CPU314and FC310. MEM312may also be employed to transfer packets between FC310and other processors (not shown) in addition to CPU314. In an example embodiment, FC310may directly communicate with CPU314.

When a packet is received on one of PHYs302,304,306, the PHY receiving the packet inserts a timestamp into the packet. In an example embodiment, the timestamp is inserted into a predefined portion of the packet, such as the preamble. The packet is then forwarded by the PHY receiving the packet to MAC308. MAC308is configured to receive the packet and the timestamp to forward the packet and timestamp to FC310. FC310parses the packet and determines whether the timestamp should be retained or discarded. If the timestamp is to be retained, FC310forwards the packet and timestamp to MEM and/or CPU314so CPU314can acquire the packet and timestamp; otherwise, FC310discards the timestamp and forwards the packet normally.

When CPU314desires a timestamp for a packet to be transmitted by one of PHYs302,304,306, CPU314sets a time-bit on the packet. Optionally, CPU314may include a signature, such as a frame identifier (Frame ID) to facilitate matching timestamps with packets. The packet with the time-bit set is forwarded to MEM312. MEM312forwards the packet and the time-bit to FC310. FC310processes the packet and forwards the packet and an indication that the time-bit was set to MAC308. The indication may be the time-bit itself or other data may be employed to indicate to MAC308that a timestamp for the packet is desired. MAC308processes the packet and forwards the packet with data indicating whether the time-bit was set to one of PHYs302,304,306. In an example embodiment, MAC308sets a specified bit in the preamble of the packet before forwarding the packet to one of PHYs302,304,306for processing to indicate whether a timestamp is desired. The PHY transmitting the packet (for example PHY302) receives the packet with data indicating whether the time-bit was set from MAC308. The PHY removes the data indicating whether the time-bit was set before transmitting the packet and then transmits the packet. If the time-bit was set, the transmission time is saved for later retrieval by CPU314.

In an example embodiment, if CPU314desires to receive a timestamp corresponding to when the packet was transmitted by one of PHYs302,304,306, CPU314sets a time-bit and optionally inserts a signature in a header for the packet. CPU314then forwards the packet to FC310. FC310is configured to forward the packet to MAC308. The time-bit may be sent to MAC308unchanged, or alternatively, FC310may set another pre-defined time-bit and/or signature to inform MAC308that timestamp data for the packet is desired. MAC308is configured to retrieve the time-bit and signature and to insert the time-bit and signature into a preamble of the packet to be transmitted. The packet is then forwarded to the PHY transmitting the packet (e.g. PHY304). The PHY transmitting the packet is responsive to the time-bit and signature in the preamble of the packet to store the time when the packet was transmitted. The PHY removes the time-bit, and if present the signature, before transmitting the packet and stores the timestamp for the packet.

In an example embodiment, device300may function as a switch, and packets may be received on one PHY and transmitted for another PHY. For example, a packet may be received by PHY302, processed by MAC308, and forwarded by FC310. FC310may determine the packet is to be transmitted via PHY304and thus route the packet to PHY304via MAC308. Alternatively, FC310may forward the packet to CPU314, which determines that the packet is to be routed to PHY304and thus forwards the packet to FC310, which forwards the packet to MAC308and from MAC308to PHY304. In accordance with an example embodiment, PHY302may add or insert timestamp data into the packet when it is received. Optionally, the timestamp data may include a signature/frame ID with the timestamp. When MAC308receives the packet, the timestamp may be employed for any suitable MAC layer process that employs a timestamp. MAC308forwards the packet and the timestamp data to FC310. FC310may retrieve the timestamp data and/or forward the packet and timestamp data to either CPU314and/or MEM312. When CPU314or FC310determine to route the packet through another PHY (e.g. PHY304), CPU314and/or FC310may set a time-bit associated with the packet as described herein to request a time from PHY304corresponding to when the packet was actually transmitted. In addition to a time-bit, a signature or frame ID may also be included, which may or may not be the same as a signature/frame ID inserted into the packet when it was received. The packet is routed to MAC308, which then forwards the packet and time-bit to PHY304. PHY304then records the timestamp data and retains it for either FC310and/or CPU314, as described herein.

FIG. 4illustrates an example system600configured to synchronize clock modules in a plurality of physical layer processing devices. In this example, three physical layer processing devices (PHYs)602,604,606are illustrated; however, those skilled in the art should appreciate that the principles that are described herein are applicable to systems with any physically realizable number of PHYs. PHYs602,604,606have corresponding clock modules612,614,616respectively. PHYs602,604,606are coupled to MAC620. MAC620is coupled to FC630, which is coupled to MEM640, and MEM640is coupled to CPU642. FC630may either send and/or receive packets via MEM640and/or CPU642.

In an example embodiment, clock modules612,614,616are synchronized by data packets sent from MAC620. The packets may originate from CPU642, MEM640, or any other process in communication with FC630. Clock modules612,614,616may be synchronized by every packet or during a predetermined time interval (for example once per minute). In operation, MAC620sends a time along with (or embedded in) outgoing packets to PHYs602,604,606. A bit may be set in the preamble to enable a PHY receiving the packet to determine that the time in the preamble is the current time and not a signature to be stored with the time. Logic in either the PHYs or the clock modules compensate for the delay between the MAC620and the PHY receiving the packet. For example, a packet is sent from MAC620to PHY602, after compensating for the delay between MAC620and PHY602, clock module612is synchronized with the time provided by MAC620.

In an example embodiment, clock modules612,614,616are synchronized by CPU642. For example CPU642sends a signal to PHYs602,604,606requesting their current time In an example embodiment, the signal is sent via a single hardwired connection to each PHY to minimize latency. The signal may also be sent by FC630instead of CPU642. Clock modules612,614,616respond with their current time. The times may be stored in a register accessible by CPU642and/or another memory accessible by CPU642such as a stack (e.g. a FIFO stack). CPU642can compare the times retrieved for PHYs and adjust individual PHYs. For example, if the time of clock module616is different by more than a predetermined threshold, which may also account for differences between the resolution between the clocks, then clock modules612,614, CPU642can take corrective action, such as signaling clock module616to increment or decrement the time and/or signal a new time seed.

FIG. 6illustrates an example of frame processing employing the Open Systems Interconnection stack. In the example illustrated inFIG. 6, when frames are received by the PHY, the timestamp is inserted or otherwise associated with the frame (e.g. can be appended or pre-appended). The timestamp is then passed through 802.3X, 8023ah OAM, MAC security (MACsec) and Sync Recognition protocols. Note that the timestamp inserted by the PHY can be employed by any protocol because the timestamp is protocol independent. For frames that are being transmitted, a frame ID is associated with the frame and passed through the various protocols. A frame ID can also be employed with received frames. A timestamp for a transmitted frame is generated when the frame is transmitted. The frame ID enables any protocol processing the frame to match the timestamp with the appropriate frame.

FIG. 7is a block diagram that illustrates a computer system900upon which an example embodiment may be implemented. Computer system900is suitable for implementing the functionality of the logic for the various components herein. For example, computer system900may implement PHY100, timestamp logic106, clock module108inFIG. 1; PHY100, MAC202, and CPU204inFIG. 2; PHYs302,304,306, MAC308, FC310, MEM312, and CPU314inFIG. 3; as well as the modules described inFIG. 4.

Computer system900includes a bus902or other communication mechanism for communicating information and a processor904coupled with bus902for processing information. Computer system900also includes a main memory906, such as random access memory (RAM) or other dynamic storage device coupled to bus902for storing information and instructions to be executed by processor904. Main memory906also may be used for storing a temporary variable or other intermediate information during execution of instructions to be executed by processor904. Computer system900further includes a read only memory (ROM)908or other static storage device coupled to bus902for storing static information and instructions for processor904. A storage device910, such as a magnetic disk or optical disk, is provided and coupled to bus902for storing information and instructions.

An aspect of the example embodiment is related to the use of computer system900for flexible time stamping. According to an example embodiment, flexible time stamping is provided by computer system900in response to processor904executing one or more sequences of one or more instructions contained in main memory906. Such instructions may be read into main memory906from another computer-readable medium, such as storage device910. Execution of the sequence of instructions contained in main memory906causes processor904to perform the process steps described herein. One or more processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in main memory906. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions to implement an example embodiment. Thus, embodiments described herein are not limited to any specific combination of hardware circuitry and software.

The term “computer-readable medium” as used herein refers to any medium that participates in providing instructions to processor904for execution. Such a medium may take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as storage device910. Volatile media include dynamic memory, such as main memory906. Transmission media include coaxial cables, copper wire, and fiber optics, including the wires that comprise bus902. Transmission media can also take the form of acoustic or light waves such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include for example floppy disk, flexible disk, hard disk, magnetic cards, paper tape, any other physical medium with patterns of holes, a RAM, a PROM, an EPROM, a FLASHPROM, CD, DVD or any other memory chip or cartridge, or any other medium from which a computer can read.

Various forms of computer-readable media may be involved in carrying one or more sequences of one or more instructions to processor904for execution. For example, the instructions may initially be borne on a magnetic disk of a remote computer. The remote computer can load the instructions into its dynamic memory and send the instructions using a modem. A modern local to computer system900can receive the data on the telephone line and use an infrared transmitter to convert the data to an infrared signal. An infrared detector coupled to bus902can receive the data carried in the infrared signal and place the data on bus902. Bus902carries the data to main memory906, from which processor904retrieves and executes the instructions. The instructions received by main memory906may optionally be stored on storage device910either before or after execution by processor904.

Computer system900may also include a communication interface918coupled to bus902. Communication interface918provides a two-way data communication coupling computer system900to other devices (not shown).

For example, communication interface918may be a local area network (LAN) card to provide a data communication connection to a compatible LAN. As another example, communication interface918may be an integrated services digital network (ISDN) card or a modem to provide a data communication connection to a corresponding type of telephone line. Wireless links may also be implemented. In any such implementation, communication interface918sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.

In view of the foregoing structural and functional features described above, methodologies in accordance with example embodiments will be better appreciated with reference toFIGS. 8-11. While, for purposes of simplicity of explanation, the methodologies ofFIGS. 8-11are shown and described as executing serially, it is to be understood and appreciated that the example embodiments are not limited by the illustrated order, as some aspects could occur in different orders and/or concurrently with other aspects from that shown and described herein. Moreover, not all illustrated features may be required to implement the methodologies described herein. The methodologies described herein are suitably adapted to be implemented in hardware, software, or a combination thereof.

FIG. 8illustrates an example of a method1000for time stamping a received packet at physical layer (PHY). At1002, a packet is received at the physical layer interface. The received packet is timestamped at the physical processing layer interface. In an example embodiment, the packet comprises a preamble portion and a data portion, similar to packet700illustrated inFIG. 5. In an example embodiment, timestamp data is inserted into the header portion of the packet. In another example embodiment, timestamp data is pre-appended or appended to the data portion of the packet. In an example embodiment, timestamp data may include additional data, such as data representative of the resolution of the timestamp (for example, 10 nanoseconds (ns), 5 ns, 1 ns, 0.1 ns, etc.).

At1004, the packet is forwarded to a MAC interface. If the MAC interface processor utilizes timing information for a MAC (or Network Layer) protocol, the MAC processor can retrieve the timestamp received from the PHY interface. The MAC interface forwards the packet to a processor. The processor may be a regular CPU (for example, in an end device such as a telephone) or may be a forwarding controller (for example, in a switch ASIC, which is the example illustrated inFIG. 8). The MAC interface may forward the packet unchanged as received from the PHY interface or can perform an appropriate conversion of the packet for the next processor. For example, the MAC interface may remove the preamble and insert timestamp data in the MAC header.

At1006, the forwarding controller (FC) receiving the packet from the MAC can parse the packet. The forwarding controller retrieves the timestamp associated with the packet. At1008, the forwarding controller determines whether the timestamp is needed by the CPU that will be receiving the packet. If the timestamp is needed (YES), at1012the timestamp is forwarded to the CPU. The timestamp may be forwarded in a preamble for the packet, or may be pre-appended or appended to the frame. If at1008the packet is not needed (NO), at1010the timestamp is discarded.

FIG. 9illustrates an example of a method1100for signaling a physical layer interface device to note the time a packet is actually transmitted and providing the time to a device requesting the time. Method1100enables a device, such as a processor, to acquire the actual time a packet was sent on the wire (or in the air for a wireless network) as opposed to when the packet left the device. This is more accurate because delays and jitter due to processing, such as buffering and encryption at the MAC layer, etc. may reduce the accuracy of times recorded by the CPU.

At1102, the processor requesting a time for when the packet is transmitted sets a time stamp bit (or time-bit). In particular embodiments, a signature or frame ID may also be inserted into the packet. The packet is then forwarded to the MAC interface at1104. The time-bit is forwarded with the packet. The time-bit may be sent in a preamble or header associated with the packet or, as illustrated inFIG. 4, the time-bit can be set according to the protocol processing the packet. For example, one protocol may set the time-bit in a PSV header, while another protocol may set a time-bit in a SCH header.

At1106, the packet is forwarded from the MAC (or network layer interface) to the physical layer (PHY) interface for transmission. The time-bit is retained while forwarding the packet from the MAC to the PHY so the PHY can determine whether the process sending the packet is requesting a timestamp.

At1108, the PHY processor removes the time-bit. At1110, the packet is transmitted by the PHY transmitter. If the time-bit was set, at1112the time corresponding to when the packet was sent is provided to the device (such as a processor or CPU) requesting the timestamp. As described herein supra, the time may be communicated to the CPU employing any means such as setting a register, loading a FIFO and/or sending a signal comprising data representative of the time to the CPU. In an example embodiment, the PHY stores the time (and, in particular embodiments, a signature is also stored along with the time) and waits for the device, such as a CPU, to retrieve it.

In addition to the time-bit, other data may also be forwarded from the CPU to the PHY. For example, as illustrated inFIG. 6, a frame ID may accompany the packet so the CPU can match the time sent with the appropriate packet. In addition, the PHY may provide additional data to the CPU, such as the resolution of the PHY's clock.

FIG. 10illustrates an example of a method1200for updating a physical layer (PHY) processor clock module via a packet. Methodology1200enables a PHY to update its clock module frequently. For example, the PHY may update the clock every packet or during a predetermined interval (for example, every 10 packets or every two seconds).

At1202, the MAC processor sends a packet to the PHY. The packet may be a special timing synchronization packet or may be a data packet destined for transmission by the PHY. A timestamp from the MAC accompanies the packet. The timestamp may be inserted inside a part of the packet, such as the preamble or header, which would not be encrypted or can be pre-appended or appended onto the packet.

At1204, the PHY compensates for the delay from the MAC to PHY. This enables devices such as switches with multiple PHYs to be synchronized with the MAC's clock.

At1206, the PHY updates its clock. If the resolution of the PHY is less than the resolution of the MAC, the PHY may round up or down. If the packet sent from the MAC is a packet that is to be transmitted by the PHY, the PHY also transmits the packet. The packet may be transmitted concurrent to the clock/timer being updated.

In an example embodiment, an averaging algorithm may be employed to obtain an average over many current time samples for updating the current time in the PHY. This can filter out any dynamic latency from the MAC to PHY.

FIG. 11illustrates an example of a method1300for synchronizing multiple physical layer processor clock modules. At1302, a signal is sent to all (or a plurality of) PHYs requesting their current time. This signal is sent simultaneously with minimal skew between the signal arrival and subsequent time capture at each PHY.

At1304, the CPU or device requesting the time from the PHYs receives the current time from the PHYs. Any suitable method for conveying the time can be employed. For example, the PHYs can load a register that is accessible by the CPU. As another example, the PHYs may place the data in a FIFO accessible by the CPU. The FIFO data may also include an identifier for the PHY.

At1306, the CPU compares and, if desired, adjusts PHY clocks. For example, if the CPU determines from the retrieved times that one PHY's time is different from the other PHY's time by more than a predetermined amount (e.g. 5 ns), the CPU can signal the PHY to increment or decrement its clock accordingly. In an example embodiment, the CPU may send the current time (or a time seed) to the PHY to update its clock. In an example embodiment, the CPU compares the time returned from the PHYS and compares it to its own time clock and updates any PHY whose time clock is off by more than a predetermined amount of time. In particular embodiments, the CPU compensates for delays between the PHY and CPU.

Described above are example embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies, but one of ordinary skill in the art will recognize that many further combinations and permutations of the example embodiments are possible. Accordingly, this application is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.