Semiconductor device and semiconductor system

A semiconductor system includes a controller configured to output external commands and external addresses; and a semiconductor device configured to generate internal commands from the external commands by a delay amount controlled according to PVT information in a boot-up operation, generate internal addresses by delaying the external addresses, and select a plurality of banks according to the internal addresses in synchronization with the internal commands.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2015-0029345 filed on Mar. 2, 2015 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Embodiments of the invention relate to a semiconductor device and a semiconductor system.

2. Related Art

General semiconductor devices are placed on the market as products, by being packaged with other semiconductor devices. Most of such semiconductor devices receive and output various signals by reception circuits for receiving signals transmitted from an exterior, through input pads, and output circuits for outputting signals through output pads.

The delay amounts of transfer paths through which such various signals are received and outputted are differently set due to differences in their characteristics. A synchronous semiconductor device such as an SDRAM receives and outputs various signals in synchronization with a clock, and delay amounts when receiving and outputting signals may be various according to variations in PVT (process, voltage and temperature) characteristics. Therefore, a technology for controlling the delay times of signals to be received and outputted, in conformity with variations in PVT characteristics, is demanded in the art.

SUMMARY

In an embodiment, a semiconductor system may include a controller configured to output external commands and external addresses. The semiconductor system may also include a semiconductor device configured to generate internal commands from the external commands by a delay amount controlled according to PVT information in a boot-up operation. The semiconductor device may also generate internal addresses by delaying the external addresses. In addition, the semiconductor device may select a plurality of banks according to the internal addresses in synchronization with the internal commands.

In an embodiment, a semiconductor device may include a PVT detection block configured to generate first to third control signals including PVT information. The semiconductor device may also include an internal command generation block configured to receive external commands and external addresses inputted from an exterior, be controlled in a delay amount according to a combination of the first to third control signals, and generate internal commands from the external commands. The semiconductor device may also include an internal address generation block configured to buffer the external addresses, and generate internal addresses. The semiconductor device may also include a bank active signal generation block configured to generate bank active signals for selecting a plurality of banks from the internal addresses in synchronization with the internal commands.

In an embodiment, a semiconductor system may include a controller configured to output external commands and external addresses, and output first to third control signals including PVT information. The semiconductor system may also include a semiconductor device configured to generate internal commands from the external commands by a delay amount controlled according to the first to third control signals, generate internal addresses by delaying the external addresses, and select a plurality of banks according to the internal addresses in synchronization with the internal commands.

DETAILED DESCRIPTION

Hereinafter, a semiconductor device and a semiconductor system will be described below with reference to the accompanying figures through various embodiments. Various embodiments are directed to a semiconductor device and a semiconductor system, in which control signals including PVT information are generated in a boot-up operation and an internal delay amount is controlled in a variety of ways according to a combination of the control signals, thereby preventing operation errors according to variations in PVT characteristics. According to various embodiments, control signals including PVT information are generated in a boot-up operation, and an internal delay amount is controlled in a variety of ways according to a combination of the control signals, whereby it is possible to prevent operation errors from occurring according to variations in PVT characteristics

Referring toFIG. 1, a semiconductor system in accordance with an embodiment may include a controller1and a semiconductor device2. The semiconductor device2may include a PVT detection block21, an internal command generation block22, an internal address generation block23, a bank active signal generation block24, and a memory region25.

The controller1may output first to third external commands RAS, CAS and WE and external addresses ADD<1:N>. The first external command RAS may be set as a row address strobe (RAS). The second external command CAS may be set as a column address strobe (CAS). Further, the third external command WE may be set as a write enable (WE). The first to third external commands RAS, CAS and WE may be set as commands or signals for controlling the semiconductor device2according to embodiments.

The PVT detection block21may output first to third control signals CON<1:3> including PVT information in a boot-up operation. In the boot-up operation, the first control signal CON<1> may be a signal generated as fuses are programmed in conformity with a process change amount. The second control signal CON<2> may be generated by detecting the level of an internal voltage. Further, the third control signal CON<3> may be generated by detecting an internal temperature. The PVT detection block21may be realized by a fuse array including a plurality of fuses, a voltage detection circuit and a temperature sensor. The boot-up operation may be set as an operation programmed according to whether fuses are cut and generates PVT information.

In detail, the logic levels of the first to third control signals CON<1:3> including PVT information are as follows.

The first control signal CON<1> may be generated as a logic high level where the operation speed of internal transistors is high according to a process change amount. The first control signal CON<1> may be generated as a logic low level where the operation speed of internal transistors is low.

The second control signal CON<2> may be generated as a logic high level where the level of an internal voltage is high by detecting the level of the internal voltage. The second control signal CON<2> may be generated as a logic low level where the level of the internal voltage is low.

The third control signal CON<3> may be generated as a logic high level where an internal temperature is low by detecting the internal temperature. The third control signal CON<3> may be generated as a logic low level where the internal temperature is high.

The internal command generation block22may be controlled in a delay amount according to a combination of the first to third control signals CON<1:3>. The internal command generation block22may generate first to third internal commands ACT, PCG and RD/WT from the first to third external commands RAS, CAS and WE. The first internal command ACT may be set as a command for the semiconductor device2to perform an active operation. The second internal command PCG may be set as a command for the semiconductor device2to perform a precharge operation. Further, the third internal command RD/WT is a command for the semiconductor device2to perform a read operation or a write operation.

The internal address generation block23may delay the external addresses ADD<1:N> and generate internal addresses IADD<1:N>.

The bank active signal generation block24may generate bank active signals BKA<1:N> according to a combination of the internal addresses IADD<1:N> in synchronization with the first to third internal commands ACT, PCG and RD/WT.

The memory region25may include a plurality of banks which are selected by the bank active signals BKA<1:N>. The memory region25may be realized by a plurality of banks which include memory cells generally known in the art.

The semiconductor device2may generate the first to third internal commands ACT, PCG and RD/WT from the first to third external commands RAS, CAS and WE by the delay amount controlled according to PVT information in the boot-up operation. The semiconductor device2may generate the internal addresses IADD<1:N> by delaying the external addresses ADD<1:N>. Further, the semiconductor device2may select a plurality of banks according to the internal addresses IADD<1:N> in synchronization with the first to third internal commands ACT, PCG and RD/WT.

Referring toFIG. 2, the internal command generation block22may include an input buffer221, a decoder222, and a delay control unit223.

The input buffer221may buffer the first to third external commands RAS, CAS and WE. The input buffer221may also generate first to third internal signals IRAS, ICAS and IWE.

The decoder222may decode the first to third internal signals IRAS, ICAS and IWE. The decoder222may also generate first to third pre-internal commands PACT, PPCG and PRD/WT which are selectively enabled.

The delay control unit223may be controlled in delay amount according to a combination of the first to third control signals CON<1:3>. The delay control unit223may also delay the first to third pre-internal commands PACT, PPCG and PRD/WT. Further, the delay control unit223may also generate the first to third internal commands ACT, PCG and RD/WT.

Referring toFIG. 3, the delay control unit223may include a first delay control section224, a second delay control section225, and a third delay control section226.

The first delay control section224may include a first delay part2241, a second delay part2242, and a selective transfer part2243.

The first delay part2241may delay the first pre-internal command PACT by a first delay amount. The first delay part2241may also generate a first delayed signal D1.

The second delay part2242may delay the first pre-internal command PACT by a second delay amount. The second delay part2242may also generate a second delayed signal D2. The first delay amount may be set to be larger than the second delay amount. In addition, the first delay amount and the second delay amount may be set as various delay amounts according to various embodiments.

The selective transfer part2243may output the first delayed signal D1to a node nd21from which the first internal command ACT is outputted where the first control signal CON<1> is enabled. The selective transfer part2243may also output the second delayed signal D2to the node nd21from which the first internal command ACT is outputted where the first control signal CON<1> is disabled.

The first delay control section224may delay the first pre-internal command PACT by the first delay amount and generate the first internal command ACT where the first control signal CON<1> is enabled. The first delay control section224may also delay the first pre-internal command PACT by the second delay amount and generate the first internal command ACT where the first control signal CON<1> is disabled.

The second delay control section225may include a first switch2251positioned between the node nd21and a node nd22and electrically couples the node nd21and the node nd22where the second control signal CON<2> is enabled. Further, the second delay control section225may also include a first capacitor C21which is positioned between the node nd22and a ground voltage VSS and has a first charge amount.

Namely, the second delay control section225may electrically couple the first capacitor C21to the node nd21and delay the first internal command ACT by a third delay amount where the second control signal CON<2> is enabled.

The third delay control section226may include a second switch2261which is positioned between the node nd21and a node nd23and electrically couples the node nd21and the node nd23where the third control signal CON<3> is enabled. The third delay control section226may also include a second capacitor C22positioned between the node nd23and the ground voltage VSS and has a second charge amount.

Namely, the third delay control section226may electrically couple the second capacitor C22to the node nd21and delay the first internal command ACT by a fourth delay amount where the third control signal CON<3> is enabled. The third delay amount may be set to be larger than the fourth delay amount. Further, the third delay amount and the fourth delay amount may be set as various delay amounts according to various embodiments.

The delay control unit223configured as mentioned above may be controlled in delay amount according to a combination of the first to third control signals CON<1:3>. Further, the delay control unit223may delay the first pre-internal command PACT by a controlled delay amount and generate the first internal command ACT. While it is illustrated inFIG. 3that the delay control unit223delays the first pre-internal command PACT and generates the first internal command ACT, the delay control unit223may be realized to delay the first to third pre-internal commands PACT, PPCG and PRD/WT and generate the first to third internal commands ACT, PCG and RD/WT. The delay control unit223may be realized by a plurality of delay control sections capable of delaying the first to third pre-internal commands PACT, PPCG and PRD/WT and generating the first to third internal commands ACT, PCG and RD/WT, respectively.

Operations of the semiconductor system configured as mentioned above will be described below with reference toFIG. 4, through taking as an example the case where an active operation and a precharge operation are performed in every one cycle of a clock CLK and the delay amount of the internal command generation block22is set as the sum of the second delay amount and the third delay amount, by being divided into an operation in which a delay amount is controlled as the first internal command ACT is generated earlier than the internal addresses IADD<1:N> and an operation in which a delay amount is controlled as the second internal command PCG is generated later than the internal addresses IADD<1:N>.

First, an operation in which the first internal command ACT is generated earlier than the internal addresses IADD<1:N> will be described below.

When the semiconductor device2enters the active operation, the internal command generation block22generates the first internal command ACT according to a combination of the first to third external commands RAS, CAS and WE. The delay amount of the internal command generation block22is set as the sum of the second delay amount and the third delay amount.

The internal address generation block23delays the external addresses ADD<1:N> and generates the internal addresses IADD<1:N>.

The bank active signal generation block24generates the bank active signals BKA<1:N> from the internal addresses IADD<1:N> in synchronization with the first internal command ACT. As the bank active signal generation block24generates the bank active signals BKA<1:N> from the internal addresses IADD<1:N> generated earlier than a time T1, an operation error may be caused.

An operation of controlling the delay amount of the internal command generation block22will be described below.

The PVT detection block21outputs the first control signal CON<1> of the logic high level. The PVT detection block21also outputs the second control signal CON<2> of the logic high level and the third control signal CON<3> of the logic low level in the boot-up operation.

The input buffer221of the internal command generation block22buffers the first to third external commands RAS, CAS and WE. The input buffer221also generates the first to third internal signals IRAS, ICAS and IWE.

The decoder222decodes the first to third internal signals IRAS, ICAS and IWE. The decoder222also generates the first pre-internal command PACT among the first to third pre-internal commands PACT, PPCG and PRD/WT.

The first delay control section224of the delay control unit223receives the first control signal CON<1> of the logic high level. The first delay control section224also outputs the first delayed signal D1generated as the first pre-internal command PACT is delayed by the first delay amount, to the node nd21. The second delay control section225receives the second control signal CON<2> of the logic high level. In addition, the first capacitor C21is electrically coupled to the node nd21. The third delay control section226receives the third control signal CON<3> of the logic low level. Further, the second capacitor C22is not electrically coupled to the node nd21. The delay control unit223generates the first internal command ACT of which delay amount is increased by a period ‘X’ when compared to the sum of the second delay amount and the third delay amount. In detail, the delay amount of the delay control unit223is set as the sum of the first delay amount and the third delay amount. The period ‘X’ means a delay amount difference between the first delay amount and the second delay amount.

The internal address generation block23delays the external addresses ADD<1:N>. The internal address generation block23also generates the internal addresses IADD<1:N>.

The bank active signal generation block24generates the bank active signals BKA<1:N> from the internal addresses IADD<1:N> in synchronization with the first internal command ACT. Since the bank active signals BKA<1:N> are generated using the internal addresses IADD<1:N> w generated during the period from the time T1to a time T2corresponding to 1 cycle of the clock CLK, an operation error does not occur.

In the memory region25, a bank selected by the bank active signals BKA<1:N> performs the active operation.

Next, an operation in which the second internal command PCG is generated later than the internal addresses IADD<1:N> will be described below.

When the semiconductor device2enters the precharge operation, the internal command generation block22generates the second internal command PCG according to a combination of the first to third external commands RAS, CAS and WE. The delay amount of the internal command generation block22is set as the sum of the second delay amount and the third delay amount.

The internal address generation block23delays the external addresses ADD<1:N>. The internal address generation block23also generates the internal addresses IADD<1:N>.

The bank active signal generation block24generates the bank active signals BKA<1:N> from the internal addresses IADD<1: N> in synchronization with the second internal command PCG. As the bank active signal generation block24generates the bank active signals BKA<1:N> from the internal addresses IADD<1:N> generated later than a time T3, an operation error may be caused.

An operation of controlling the delay amount of the internal command generation block22will be described below.

The PVT detection block21outputs the first control signal CON<1> of the logic low level. The PVT detection block21also outputs the second control signal CON<2> of the logic low level and the third control signal CON<3> of the logic high level in the boot-up operation.

The input buffer221of the internal command generation block22buffers the first to third external commands RAS, CAS and WE. The input buffer221also generates the first to third internal signals IRAS, ICAS and IWE.

The decoder222decodes the first to third internal signals IRAS, ICAS and IWE. The decoder222also generates the second pre-internal command PPCG among the first to third pre-internal commands PACT, PPCG and PRD/WT.

The first delay control section224of the delay control unit223receives the first control signal CON<1> of the logic low level. The first delay control section224also outputs the second delayed signal D2generated as the second pre-internal command PPCG is delayed by the second delay amount, to the node nd21. The second delay control section225receives the second control signal CON<2> of the logic low level. Further, the first capacitor C21is not electrically coupled to the node nd21. The third delay control section226receives the third control signal CON<3> of the logic high level. In addition, the second capacitor C22is electrically coupled to the node nd21. The delay control unit223generates the second internal command PCG of which delay amount is decreased by a period ‘Y’ when compared to the sum of the second delay amount and the third delay amount. In detail, the delay amount of the delay control unit223is set as the sum of the second delay amount and the fourth delay amount. The period ‘Y’ means a delay amount difference between the third delay amount and the fourth delay amount.

The internal address generation block23delays the external addresses ADD<1:N>. The internal address generation block23also generates the internal addresses IADD<1:N>.

The bank active signal generation block24generates the bank active signals BKA<1:N> from the internal addresses IADD<1: N> in synchronization with the second internal command PCG. Since the bank active signals BKA<1: N> are generated using the internal addresses IADD<1:N> generated during the period from the time T2to the time T3corresponding to 1 cycle of the clock CLK, an operation error does not occur.

In the memory region25, a bank selected by the bank active signals BKA<1:N> performs the precharge operation.

In the semiconductor system configured as mentioned above, control signals including PVT information are generated in a boot-up operation. In addition, an internal delay amount is controlled in a variety of ways according to a combination of the control signals, whereby it is possible to prevent operation errors from occurring according to variations in PVT characteristics.

Referring toFIG. 5, a block diagram illustrating a representation of an example of the configuration of a semiconductor system in accordance with an embodiment is described.

As shown inFIG. 5, a semiconductor system in accordance with an embodiment may include a controller3and a semiconductor device4. The controller3may include a PVT detection block31. The semiconductor device4may include an internal command generation block41, an internal address generation block42, a bank active signal generation block43, and a memory region44.

The controller3may output first to third external commands RAS, CAS and WE and external addresses ADD<1:N>. The first external command RAS may be set as a row address strobe (RAS). The second external command CAS may be set as a column address strobe (CAS). Further, the third external command WE may be set as a write enable (WE). The first to third external commands RAS, CAS and WE may be set as commands or signals for controlling the semiconductor device4according to various embodiments.

The PVT detection block31of the controller3may output first to third control signals CON<1:3> including PVT information, in a boot-up operation. In the boot-up operation, the first control signal CON<1> may be a signal generated as fuses are programmed. The second control signal CON<2> may be generated by detecting the level of an internal voltage. In addition, the third control signal CON<3> may be generated by detecting an internal temperature. The PVT detection block31may be realized by a fuse array including a plurality of fuses, a voltage detection circuit and a temperature sensor.

The controller3may output the first to third external commands RAS, CAS and WE and external addresses ADD<1:N>. The controller3may also output the first to third control signals CON<1:3> including PVT information in a boot-up operation.

The internal command generation block41may be controlled in a delay amount according to a combination of the first to third control signals CON<1:3>. The internal command generation block41may also generate first to third internal commands ACT, PCG and RD/WT from the first to third external commands RAS, CAS and WE. The first internal command ACT may be set as a command for the semiconductor device4to perform an active operation. The second internal command PCG may be set as a command for the semiconductor device4to perform a precharge operation. In addition, the third internal command RD/WT is a command for the semiconductor device4to perform a read operation or a write operation. Since the internal command generation block41is realized by the same circuit and performs the same operations as the internal command generation block22shown inFIG. 2, detailed descriptions thereof will be omitted herein.

The internal address generation block42may delay the external addresses ADD<1:N>. The internal address generation block42may also generate internal addresses IADD<1:N>.

The bank active signal generation block43may generate bank active signals BKA<1:N> according to a combination of the internal addresses IADD<1:N>, in synchronization with the first to third internal commands ACT, PCG and RD/WT.

The memory region44may include a plurality of banks which are selected by the bank active signals BKA<1:N>. The memory region44may be realized by a plurality of banks which include memory cells generally known in the art.

The semiconductor device4may generate the first to third internal commands ACT, PCG and RD/WT from the first to third external commands RAS, CAS and WE by a delay amount controlled according to a combination of the first to third control signals CON<1:3>. The semiconductor device4may generate the internal addresses IADD<1:N> by delaying the external addresses ADD<1:N>. Further, the semiconductor device4may select a plurality of banks according to the internal addresses IADD<1:N> in synchronization with the first to third internal commands ACT, PCG and RD/WT.

As is apparent from the above descriptions, in the semiconductor system according to various embodiments, configured as mentioned above, control signals including PVT information are generated in a boot-up operation. Further, an internal delay amount is controlled in a variety of ways according to a combination of the control signals, whereby it is possible to prevent operation errors from occurring according to variations in PVT characteristics.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of examples only. Accordingly, the semiconductor device and the semiconductor system described herein should not be limited based on the described embodiments above.