Data storage apparatus and operating method thereof

A data storage apparatus includes a nonvolatile memory device including a plurality of memory blocks in which a plurality of word lines to which one or more pages are coupled are arranged, a data buffer configured to buffer data to be stored in the one or more pages of the nonvolatile memory device, and a processor configured to detect, when a sudden power off (SPO) occurs, one or more first pages in which an interference has occurred in a memory block in use and store data corresponding to the one or more first pages in which the interference has occurred among the data buffered in the data buffer in a backup memory block of the nonvolatile memory device.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2018-0049249, filed on Apr. 27, 2018, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments of the present invention may generally relate to a semiconductor apparatus. Particularly, the embodiments relate to a data storage apparatus and an operating method thereof.

2. Related Art

The computer environment paradigm has recently shifted to ubiquitous computing, which enables computer systems to be used anytime and anywhere. As a result, use of portable electronic apparatuses such as a mobile phone, a digital camera, and a laptop computer has been increasing rapidly. Generally, portable electronic apparatuses use data storage apparatuses that employ memory devices. Data storage apparatuses may be used to store data used in the portable electronic apparatuses.

Such data storage apparatuses using memory devices have excellent stability and endurance, high information access rate, and low power consumption, since they have no mechanical driving units. Such data storage apparatuses may include a universal serial bus (USB) memory device, a memory card having various interfaces, a universal flash storage (UFS) device, a solid state drive (SSD), and the like.

SUMMARY

Embodiments are provided to a data storage apparatus capable of efficiently performing data backup and an operating method thereof.

In an embodiment of the present disclosure, a data storage apparatus may include: a nonvolatile memory device including a plurality of memory blocks in which a plurality of word lines to which one or more pages are coupled are arranged; a data buffer configured to buffer data to be stored in the one or more pages of the nonvolatile memory device; and a processor configured to detect, when a sudden power off (SPO) occurs, one or more first pages in which an interference has occurred in a memory block in use, and store data corresponding to the one or more first pages in which the interference has occurred among the data buffered in the data buffer in a backup memory block of the nonvolatile memory device.

In an embodiment of the present disclosure, an operating method of a data storage apparatus, the method may include: detecting occurrence of sudden power-off (SPO) of the data storage apparatus; detecting one or more first pages in which an interference has occurred within a memory block in use; and storing data corresponding to the one or more first pages among data buffered in a data buffer in a backup memory block of a nonvolatile memory device.

In an embodiment of the present disclosure, a memory system may include: a memory block including page planes arranged in a first direction, each coupled to a word line and each having pages arranged in a second direction, each page having quadruple level cells (QLCs) arranged in a third direction; and a controller configured to back up, when a sudden power off (SPO) occurs during one or more program operations to the memory block, buffered data to be programmed into one or more between interrupted and interfered pages of the memory block. The interrupted page is a page to which the program operation is interrupted due to the SPO, and the interfered page is a page within a page plane, which is arranged adjacent to a page plane of the interrupted page and to which program operations are completed before the interrupted program operation.

According to embodiments, only partial data corresponding to the pages, in which interference is generated, among data buffered in a data buffer may be stored in the nonvolatile memory device under the SPO situation and thus a size of data to be backed up may be reduced.

As the size of the data to be backed up is reduced, the data backup may be stably completed while a minimal operation power is maintained through a power loss protection (PLP) circuit and thus the number of capacitors for providing the minimal operation power may be reduced and the manufacturing cost of the device may be reduced.

DETAILED DESCRIPTION

Various embodiments of the present invention will be described in greater detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments (and intermediate structures). As such, variations from the configurations and shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the described embodiments should not be construed as being limited to the particular configurations and shapes illustrated herein but may include deviations in configurations and shapes which do not depart from the spirit and scope of the present invention as defined in the appended claims. It is noted that reference to “an embodiment” does not necessarily mean only one embodiment, and different references to “an embodiment” are not necessarily to the same embodiment(s).

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. In the present disclosure, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise”, “include”, “have”, etc. when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, components, and/or combinations of them but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or combinations thereof.

Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. Unless otherwise defined in the present disclosure, the terms should not be construed as being ideal or excessively formal.

The technical spirit of the present disclosure may be changed in various manners, and may be implemented as embodiments having various aspects. Hereinafter, the present disclosure will be described by way of some embodiments so that those skilled in the art can easily practice the embodiments of the present disclosure.

FIG. 1is a block diagram illustrating a configuration example of a data storage apparatus10according to an embodiment.FIG. 2is a diagram illustrating a configuration example of the nonvolatile memory device100ofFIG. 1.FIG. 3is a diagram illustrating a configuration example of a memory cell array110ofFIG. 2.

Referring toFIG. 1, a data storage apparatus10according to the embodiment may store data to be accessed by a host apparatus (not shown) such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game player, a television (TV), or an in-vehicle infotainment system, and the like. The data storage apparatus10may refer to a memory system.

The data storage apparatus10may be manufactured as any one among various types of storage apparatuses according to an interface protocol coupled to a host apparatus (not shown). For example, the data storage apparatus10may be configured as any one of various types of storage apparatuses, such as a solid state drive (SSD), a multimedia card in the form of an MMC, an eMMC, an RS-MMC, and a micro-MMC, a secure digital card in the form of an SD, a mini-SD, and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnection (PCI) card type storage device, a PCI-express (PCI-e or PCIe) card type storage device, a compact flash (CF) card, a smart media card, a memory stick, and the like.

The data storage apparatus10may be manufactured as any one among various types of packages. For example, the data storage apparatus10may be manufactured as any one of various types of packages, such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-level fabricated package (WFP), and a wafer-level stack package (WSP).

The data storage apparatus10may include a nonvolatile memory device100and a controller200.

The nonvolatile memory device100may be operated as a storage medium of the data storage apparatus10. By way of example and not limitation, the nonvolatile memory device100may include any one of various types of nonvolatile memory devices according to a memory cell, such as a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a magnetic random access memory (MRAM) using a tunneling magneto-resistive (TMR) layer, a phase-change random access memory (PRAM) using a chalcogenide alloy, and a resistive random access memory (ReRAM) using a transition metal compound.

Referring toFIG. 2, the nonvolatile memory device100may include a memory cell array110, a row decoder120, a read/write circuit130, a column decoder140, a page buffer150, a voltage generator160, a control logic170, and an input/output (I/O) circuit180.

The memory cell array110may include a plurality of memory cells (not shown) arranged in regions in which a plurality of word lines WL and a plurality of bit lines BL cross each other.

Referring toFIG. 3, the memory cell array110may include a plurality of memory blocks BLK1to BLKi and each of the plurality of memory blocks BLK1to BLKi may include a plurality of pages PG1to PGj.

By way of example and not limitation, each of the memory cells in the memory cell array110may be at least one among a single level cell (SLC) in which a single bit data (for example, 1-bit data) is to be stored, a multilevel cell (MLC) in which 2-bit data is to be stored, a triple level cell (TLC) in which 3-bit data is to be stored, and a quad level cell QLC in which 4-bit data is to be stored. The memory cell array110may include at least one or more cells among the SLC, the MLC, the TLC, and the QLC. For example, the memory cell array110may include memory cells having a two-dimensional (2D) horizontal structure or memory cells having a 3D vertical structure.

Referring back toFIG. 2, the row decoder120may be coupled to the memory cell array110through the word lines WL. The row decoder120may be operate according to control of the control logic170. The row decoder120may decode a row address X-ADDR provided from the control logic170and select and drive at least one among the word lines WL based on a decoding result. The row decoder120may provide an operation voltage Vop provided from the voltage generator160to the selected word line WL.

The read/write circuit130may be coupled to the memory cell array110through the bit lines BL. The read/write circuit130may include read/write circuits (not shown) corresponding to the bit lines BL. The read/write circuit130may operate according to control of the control logic170. The read/write circuit130may include a write driver WD configured to write data in memory cells and a sense amplifier SA configured to amplify data read out from the memory cell. The read/write circuit130may perform write and read operations on selected memory cells by providing a current pulse or a voltage pulse to the memory cells selected through the row decoder120and the column decoder140among the memory cells of the memory cell array110.

The column decoder140may be operate according to control of the control logic170. The column decoder140may decode a column address Y-ADDR provided from the control logic170. The column decoder140may couple the read/write circuits of the read/write circuit130corresponding to the bit lines BL and the page buffer150according to the decoding result.

The page buffer150may be configured to temporarily store write data which is provided from a memory interface250of the controller200and is to be written in the memory cell array110or read data which is read out from the memory cell array110and is to be transmitted to the memory interface250of the controller200. The page buffer150may be operated according to control of the control logic170.

The voltage generator160may generate various voltages for performing write, read, and erase operations on the memory cell array110based on a voltage control signal CTRL_vol provided from the control logic170. The voltage generator160may generate driving voltages flop for driving a plurality of word lines WL and a plurality of bit lines BL. The voltage generator160may generate at least one or more reference voltages for reading data stored in memory cells MC.

The control logic170may output various control signals for writing data DATA in the memory cell array110or reading out data DATA from the memory cell array110based on a command CMD, an address ADDR, and a control signal CTRL received from the controller200show inFIG. 1. The various control signals output from the control logic170may be provided to the row decoder120, the write/read circuit130, the column decoder140, the page buffer150, and the voltage generator160. Accordingly, the control logic170may control overall operations performed in the nonvolatile memory device100.

For example, the control logic170may generate the operation control signal CTRL_op based on the command CMD and the control signal CTRL and provide the generated operation control signal CTRL_op to the write/read circuit130. The control logic170may provide the row address X_ADDR and the column address Y_ADDR included in the address ADDR to the row decoder120and the column decoder140.

The I/O circuit180may be configured to receive the command CMD, the address ADDR, and the data DATA provided from the controller200or provide the data DATA read out from the memory cell array110to the controller200. The I/O circuit180may output the command CMD and the address ADDR received from the controller200to the control logic170and output the data DATA to the page buffer150. The I/O circuit180may output the data DATA received from the page buffer150to the controller200. The I/O circuit180may be operated according to control of the control logic170.

Referring back toFIG. 1, the controller200may control an overall operation of the data storage apparatus10through driving of firmware or software loaded into the memory230. The controller200may decode and drive a code-type instruction or algorithm such as firmware or software. The controller200may be implemented in hardware, or may be implemented in a combination of hardware and software.

The controller200may include a host interface210, a processor220, a memory230, a power loss protection (PLP) circuit240, and the memory interface250. The PLP circuit240may include an auxiliary power generator245.

The host interface210may perform interfacing between a host apparatus and the data storage apparatus10according to a protocol of the host apparatus. For example, the host interface210may communicate with the host apparatus through any one among protocols such as a USB protocol, a UFS protocol, an MMC protocol, a parallel advanced technology attachment (DATA) protocol, a serial advanced technology attachment (SATA) protocol, a small computer system interface (SCSI) protocol, a serial attached SCSI (SAS) protocol, a PCI protocol, and a PCI-E protocol.

The processor220may be configured of a micro-control unit (MCU) and a central processing unit (CPU). The processor220may process a request transmitted from a host apparatus. To process the request transmitted from the host apparatus, the processor220may drive the code-type instruction or algorithm, for example, firmware loaded into the memory230and control internal functional blocks thereof such as the host interface210, the memory230, the PLP circuit240, and the memory interface250and the nonvolatile memory device100.

The processor220may generate control signals for controlling an operation of the nonvolatile memory device100based on requests transmitted from a host apparatus and provide the generated control signals to the nonvolatile memory device100through the memory interface250.

The memory230may be configured of a random access memory such as a dynamic RAM (DRAM) or a static RAM (SRAM). The memory230may store firmware driven through the processor220. The memory230may store data (for example, meta data) required for driving of the firmware. For example, the memory230may operate as a working memory of the processor220.

The memory230may be configured to include a data buffer (DB) (not shown) configured to temporarily store data to be transmitted from a host apparatus to the nonvolatile memory device100or data to be transmitted from the nonvolatile memory device100to the host apparatus. For example, the memory230may operate as a buffer memory.

The PLP circuit240may supply auxiliary power to the data storage apparatus10to stably terminate the operations performing in the data storage apparatus10when the power supplied to the data storage apparatus10is abruptly interrupted (for example, due to a sudden power off (SPO)). AlthoughFIG. 1illustrates, as an example and for convenience in description, that the PLP circuit240includes the auxiliary power generator245that is configured to generate the auxiliary power, the present invention is not limited thereto. For example, the auxiliary power generator245may not be included in the PLP circuit240, and may be provided inside or outside of the controller200.

The auxiliary power generator245may be configured of a capacitor module (not shown) including one or more capacitors, but the auxiliary power generator is not limited thereto.

For example, when the SPO occurs during the write operation of storing data in memory cells of the nonvolatile memory device100according to a write request from a host apparatus, the PLP circuit240may provide the minimum operating power (that is, minimum power needed to operate) to the data storage apparatus10using the auxiliary power generator245to perform a backup operation of storing data temporarily stored in the data buffer DB of the memory230in the nonvolatile memory device100.

As the capacity of the nonvolatile memory device100is gradually increased, the size of data stored in one memory cell may also be gradually increased. Recently, there has been an increase in use of a quadruple level cell (QLC) method that stores four-bit data in one memory cell.

Due to high integration of the memory cell array110, an interval between the signal lines (for example, bit lines and word lines) may be reduced. Due to the reduction in the intervals, interference may be generated in another word line (for example, a word line in which a write operation on the data is completed) close to a word line on which the write operation is performing and thus the data stored in the corresponding word line may be damaged.

To solve these issues, when storing data into the QLC array, a first-first write operation which stores first data in first memory cells coupled to a first word line among a plurality of word lines may be performed, a second-first write operation which stores second data in second memory cells coupled to next word line (for example, second word line) close to the first word line may be performed, and a first-second write operation which stores the first data in the first memory cells of the first word line again may be performed. The first data stored by the first-first write operation may be the same as the first data stored by the first-second write operation.

According to the above-described QLC storage scheme, the amount of data buffered in the data buffer DB of the memory230may be increased and all the data stored in the data buffer DB may not be backed up to the nonvolatile memory device100while the minimum operating power provided through the PLP circuit240is maintained under the SPO situation. To increase the maintenance time of the minimum operating power provided from the PLP circuit240, one solution may be to increase the number of capacitors included in the auxiliary power generator245. However, such a method may cause the cost to increase due to the increase in the number of capacitors.

Accordingly, in the embodiment, a method of efficiently performing the PLP operation may be provided without increase in the number of capacitors included in the auxiliary power generator245. The method of performing the PLP operation will be described later in detail with reference to the drawings.

The memory interface250may control the nonvolatile memory device100according to control of the processor220. The memory interface250may refer to a memory controller. The memory interface250may provide control signals to the nonvolatile memory device100. The control signals may include the command CMD, the address ADDR, the operation control signal CTRL, and the like for controlling the nonvolatile memory device100. The memory interface250may provide the data DATA to the nonvolatile memory device100or receive the data DATA from the nonvolatile memory device100.

FIGS. 4A and 4Bare circuit diagrams illustrating an example of a memory block among the plurality of memory blocks shown inFIG. 3. Specifically,FIG. 4Ais a circuit diagram illustrating a memory block BLKa including memory cells arranged in a 2D manner andFIG. 4Bis a circuit diagram illustrating a memory block BLKb including memory cells arranged in a 3D manner. As illustrated inFIG. 3, the memory cell array110may include the plurality of memory blocks BLK1to BLKi and each of the memory blocks BLK1to BLKi may be implemented with the circuit illustrated inFIG. 4A or 4B, but this is not limited thereto.

Referring toFIG. 4A, the memory block BLKa may have a 2D horizontal structure. The memory block BLKa ofFIG. 4Amay correspond to any one among the plurality of memory blocks BLK1to BLKi shown inFIG. 3. The memory block BLKa may include a plurality of bit lines BL1to BLm arranged in a first direction and a plurality of word lines WL1to WLn arranged a second direction. The first direction may be an X-direction and the second direction may be a Y-axis direction, but this is not limited thereto. The first direction may be the Y-axis direction and the second direction may be the X-direction.

The memory block BLKa may include a plurality of cell strings CS coupled to the plurality of bit lines BL1to BLm. Each of the cell strings CS may have the same configuration as each other. For convenience of description and illustrative purposes, one cell string CS will be described below.

The cell string CS may include a plurality of memory cells MC1to MCn and select transistors DST and SST coupled between the bit line BL1and a common source line CSL. For example, the cell string CS may include a drain select transistor DST coupled to a drain select line DSL, the plurality of memory cells MC1to MCn coupled to the plurality of word lines WL1to WLn, and a source select transistor SST coupled to a source select line SSL.

As illustrated inFIG. 4A, a plurality of memory cells coupled to the same word line may refer to a page PG unit. The write operation and the read operation for the plurality of memory cells coupled to the same word line may be simultaneously performed, but this is not limited thereto.

Referring toFIG. 4B, the memory block BLKb may have a 3D vertical structure. The memory block BLKb ofFIG. 4Bmay correspond to any one among the plurality of memory blocks BLK1to BLKi shown inFIG. 3.

The memory block BLKb may include a plurality of bit lines BL1to BLm arranged to be spaced in a first direction, a plurality of cell strings CS11˜CS1kto CSm1˜CSmk coupled to the bit lines BL1to BLm and arranged to be spaced in a second direction, and a plurality of word lines WL1to WLn arranged to be spaced in a third direction. The first direction may be an X-direction, the second direction may be a Y-axis direction, and the third direction may be a Z-axis direction, but this is not limited thereto.

As k cell strings are coupled to each of m bit lines, m×k cell strings may be arranged in the memory block BLKb. Here, n, m, and k are integers greater than or equal to 1.

Each of the plurality of cell strings CS11˜CS1kto CSm1˜CSmk may include at least one source select transistor SST, first to n-th memory cells MC1to MCn, and at least one drain select transistor DST. The source select transistor SST of each cell string may be coupled between a common source line CSL and the memory cell MC1.

The source select transistors SST of the cell strings arranged on the same line in the X-axis direction may be coupled to the same source select line. For example, the source select transistors SST of the plurality of first cell strings CS11to CSm1coupled to the bit lines BL1to BLm may be coupled to the first source select line SSL1. Similarly, the source select transistors SST of the plurality of second to k-th cell strings CS12˜CSm2to CS1k˜CSmk coupled to the bit lines BL1to BLm may be coupled to the second to k-th source select lines SSL2to SSLk.

The drain select transistors DST of the cell strings arranged on the same line in the X-axis direction may be coupled to the same drain select line. For example, the drain select transistors DST of the first cell strings CS11to CSm1coupled to the bit lines BL1to BLm may be coupled to the first drain select line DSL1. Similarly, the drain select transistors DST of the plurality of second to k-th cell strings CS12˜CSm2to CS1k˜CSmk coupled to the bit lines BL1to BLm may be coupled to the second to k-th drain select lines DSL2to DSLk.

The first to n-th memory cells MC1to MCn of each of the plurality of cell strings CS11˜CS1kto CSm1˜CSmk may be coupled in series between the source select transistor SST and the drain select transistor DST.

The first to n-th memory cells MC1to MCn of each of the plurality of cell strings CS11˜CS1kto CSm1˜CSmk may be coupled to the first to n-th word lines. The memory cells coupled to the cell strings arranged on the same line in the X-axis direction and coupled to the same word line may refer to the page unit.

For example, as illustrated inFIG. 4B, the first memory cells MC1coupled to the first cell strings CS11to CSm1arranged on the same line in the X-axis direction and the first word line WL1may refer to a first-first page PG11. Similarly, the first memory cells MC1coupled to the second to k-th cell strings CS12˜CSm2to CS1k˜CSmk arranged on the same line in the X-axis direction and the first word line WL1may refer to first-second to first-k-th pages PG12to PG1k. Although a plurality of pages are coupled to one word line in the 3D vertical structure illustrated inFIG. 4B, this is not limited thereto.

K pages may be coupled to each of the word lines WL1to WLn and n×k pages may be arranged in the memory block BLKb. The number of pages in each of the word lines WL1to WLn may be changed according to the number of cell strings coupled to the bit lines BL1to BLm.

Hereinafter, an example of a write operation for a memory block having the 3D vertical structure illustrated inFIG. 4Bwill be described.

FIG. 5Ais a diagram illustrating an example of a write operation for a memory block BLKo having the 3D vertical structure.FIG. 5Bis a diagram illustrating a write operation sequence table according to pages ofFIG. 5A. The memory block BLKo ofFIG. 5Amay correspond to any one among the plurality of memory blocks BLK1to BLKi shown inFIG. 3.

FIG. 6Ais a conceptual diagram illustrating a state in which a write operation is performed on the first-first page PG11and the first-second page PG12of the first word line WL1.FIG. 6Bis a graph illustrating threshold voltage distributions for the first-first page PG11and the first-second page PG12of the write-completed first word line WL1(that is, pages in which the write operation has been completed).

FIG. 6Cis a conceptual diagram illustrating a state in which interference is generated in the first-first page PG11and the first-second page PG12of the first word line WL1as a write operation is performed on the second-first page PG21and the second-second page PG22of the second word line WL2.FIG. 6Dis a graph illustrating threshold voltage distributions for the first-first page PG11and the first-second page PG12of the interfered first word line WL1.FIG. 6Eis a graph illustrating threshold voltage distributions for the second-first page PG21and the second-second page PG22of the write-completed second word line WL2. For convenience of description and illustrative purposes, it is assumed that the memory block BLKo includes four word lines WL1to WL4and two pages PG11to PG42are coupled to the word lines WL1to WL4. However, the number of word lines and pages coupled to the word lines may vary depending on design.

Referring toFIGS. 5A and 5B, the write operation for the memory block BLKo may start from the first-first page PG11of the first word line WL1and may be terminated in a fourth-second page PG42of the fourth word line WL4as indicated by a solid arrow. For example, the write operation for the memory block BLKo may be performed in the following order: the first-first page PG11of the first word line WL1, the first-second page PG12of the first word line WL1, the second-first page PG21of the second word line WL2, the second-second page PG22of the second word line WL2, a third-first page PG31of the third word line WL3, a third-second page PG32of the third word line WL3, the fourth-first page PG41of the fourth word line WL4, and a fourth-second page PG42of the fourth word line WL4.

As the write operation is performed sequentially, first-first data and first-second data stored in the first-first page PG11and the first-second page PG12of the first word line WL1, second-first data and second-second data stored in the second-first page PG21and the second-second page PG22of the second word line WL2, third-first data and third-second data stored in the third-first page PG31and the third-second page PG32of the third word line WL3may be interfered by the write operations for the second word line WL2, the third word line WL3, and the fourth word line WL4.

For example, when the first write operation for storing the first-first data and the first-second data in the first-first page PG11and the first-second page PG12of the first word line WL1is completed as illustrated inFIG. 6A, the threshold voltage distributions for the first-first page PG11and the first-second page PG12of the first word line WL1may be formed as illustrated inFIG. 6B. When the first write operation for storing the second-first data and the second-second data in the second-first page PG21and the second-second page PG22of the second word line WL2is completed as illustrated inFIG. 6C, the threshold voltage distributions for the second-first page PG21and the second-second page PG22of the second word line WL2may be formed as illustrated inFIG. 6E, but the threshold voltage distributions for the first-first page PG11and the first-second page PG12of the first word line WL1may be deformed as illustrated inFIG. 6D. For example, when the first write operation for the second-first page PG21and the second-second page PG22of the second word line WL2is performed, first-first data and the first-second data stored in the first-first page PG11and the first-second page PG12of the first word line WL1close to the second word line WL2may be interfered and thus the threshold voltage distribution may be deformed. Accordingly, the first-first data and the first-second data stored in the first-first page PG11and the first-second page PG12of the first word line WL1may be damaged.

In an embodiment of the present invention, the first write operation on one or more pages coupled to a specific word line (for example, first word line) may be performed, the first write operation on one or more pages coupled to next word line (for example, the second word line) close to the specific word line may be performed, and then the second write operation on the one or more pages coupled to the first word line may be performed. The above-described write operation method is illustrated in more detail below with references toFIGS. 7A and 7B. InFIG. 7A, the dotted arrow may indicate the first write operation and the solid arrow may indicate the second write operation.

Referring toFIGS. 7A and 7B, the write operation for the memory block BLKo may start from the first-first page PG11of the first word line WL1and may be terminated in the third-second page PG32of the third word line WL3.

For example, the write operation for the memory block BLko may be performed in the following order: the first write operation for the first-first page PG11and the first-second page PG12of the first word line WL1, the first write operation for the second-first page PG21and the second-second page PG22of the second word line WL2, the second write operation for the first-first page PG11and the first-second page PG12of the first word line WL1, the first write operation for the third-first page PG31and the third-second page PG32of the third word line WL3, the second write operation for the second-first page PG21and the second-second page PG22of the second word line WL2, the first write operation for the fourth-first page PG41and the fourth-second page PG42of the fourth word line WL4, and the second write operation for the third-first page PG31and the third-second page P32of the third word line WL3. Accordingly, the first-first data to the fourth-second data for the first-first page PG11to the fourth-second page PG42of the first to fourth word lines WL1to WL4may be normally written.

FIGS. 8A to 12Bare conceptual diagrams illustrating a method of backing up data temporarily stored in the data buffer DB to a specific memory block BLKs of the nonvolatile memory device100under the SPO situation, according to an embodiment.FIGS. 8A and 8Bare diagrams illustrating an example in which the SPO occurs during the first write operation for the first-second page PG12of the first word line WL1.FIGS. 9A and 9Bare diagrams illustrating an example in which the SPO occurs during the first write operation for the second-first page PG21of the second word line WL2.FIGS. 10A and 10Bare diagrams illustrating an example in which the SPO occurs during the first write operation for the second-second page PG22of the second word line WL2.FIGS. 11A and 11Bare diagrams illustrating an example in which the SPO occurs during the second write operation for the first-first page PG11of the first word line WL1.FIGS. 12A and 12Bare diagrams illustrating an example in which the SPO occurs during the second write operation for the first-second page PG12of the first word line WL1. For clarity, the specific memory block BLKs may also be referred to as “the backup memory block BLKs” hereinafter.

When the SPO occurs, the processor220of the controller200may detect the write-interrupted pages (that is, pages in which write operation has been interrupted), the write-completed pages, and interfered pages (that is, pages in which interference has occurred) from the memory block BLKo that is in use. For example, the processor220may determine and detect the write-interrupted pages, the write-completed pages, and interfered pages from the memory block BLKo in use based on information for pages on which the write operation is performed under the SPO situation and information for the write operation.

As illustrated inFIG. 8A, when SPO occurs during the first write operation for the first-second page PG12of the first word line WL1, the processor220may determine the first-first page PG11of the first word line WL1as the write-completed page and determine the first-second page PG12as the write-interrupted page. As illustrated inFIG. 8B, based on the determination result, the processor220may control the nonvolatile memory device100to perform the write operation for storing the first-second data DATA12corresponding to the first-second page PG12of the first word line WL1among data DATA11to DATA22temporarily stored in the data buffer DB of the memory230in the backup memory block BLKs selected in the nonvolatile memory device100while the minimum operating power is provided through the driving of the PLP circuit240. The first-second data DATA12may be written in the backup memory block BLKs in a SLC manner, but this is not limited thereto.

As illustrated inFIG. 9A, when the SPO occurs during the first write operation for the second-first page PG21of the second word line WL2, the processor220may determine the first-first page PG11of the first word line WL1as the interfered page, determine the first-second page PG12of the first word line WL1as the write-completed page and determine the second-first page PG21of the second word line WL2as the write-interrupted page. The processor220may determine the first-first page PG11of a previous word line (for example, the first word line WL1) among word lines close to the second-first page PG21of the second word line WL2in the vertical direction (for example, the Z-axis direction) with respect to the second-first page PG21of the second word line WL2as the interfered page.

As illustrated inFIG. 9B, based on the determination result, the processor220may control the nonvolatile memory device100to perform the write operation for storing the first-first data DATA11corresponding to the first-first page PG11of the first word line WL11and the second-first data DATA21corresponding to the second-first page PG21of the second word line WL2among the data DATA11to DATA22temporarily stored in the data buffer DB of the memory230in the backup memory block BLKs while the minimum operating power is provided through the driving of the PLP circuit240.

As illustrated inFIG. 10A, when the SPO occurs during the first write operation for the second-second page PG22of the second word line WL2, the processor220may determine the first-first page PG11and the first-second page PG12of the first word line WL1as the interfered pages, determine the second-first page PG21of the second word line WL2as the write-completed page, and determine the second-second page PG22of the second word line WL2as the write-interrupted page.

As illustrated inFIG. 10B, based on the determination result, the processor220may control the nonvolatile memory device100to perform the write operation for storing the first-first data DATA11and the first-second data DATA12corresponding to the first-first page PG11and the first-second page PG12of the first word line WL1and the second-second data DATA22corresponding to the second-second page PG22of the second word line WL2among the data DATA11to DATA22temporarily stored in the data buffer DB of the memory230in the backup memory block BLKs while the minimum operating power is provided through the driving of the PLP circuit240.

As illustrated inFIG. 11A, when the SPO occurs during the second write operation for the first-first page PG11of the first word line WL1, the processor220may determine the first-first page PG11and the first-second page PG12of the first word line WL1as the write-interrupted page and the interfered page, respectively, and determine the second-first page PG21and the second-second page PG22of the second word line WL2as the write-completed pages.

As illustrated inFIG. 11B, based on the determination result, the processor220may control the nonvolatile memory device100to perform the write operation for storing the first-first data DATA11and the first-second data DATA12corresponding to the first-first page PG11and the first-second page PG12of the first word line WL1among the data DATA11to DATA22temporarily stored in the data buffer DB of the memory230in the backup memory block BLKs while the minimum operating power is provided through the driving of the PLP circuit240.

As illustrated inFIG. 12A, when the SPO occurs during the second write operation for the first-second page PG12of the first word line WL1, the processor220may determine the first-first page PG11and the first-second page PG12of the first word line WL1as the write-completed page and the write-interrupted page, respectively, and determine the second-first page PG21and the second-second page PG22of the second word line WL2as the write-completed page.

As illustrated inFIG. 12B, based on the determination result, the processor220may control the nonvolatile memory device100to perform the write operation for storing the first-second data DATA12corresponding to the first-second page PG12of the first word line WL1among the data DATA11to DATA22temporarily stored in the data buffer DB of the memory230in the backup memory block BLKs while the minimum operating power is provided through the driving of the PLP circuit240.

In the embodiment, only the partial data corresponding to the write-interrupted page and/or the interfered page among data temporarily stored in the data buffer DB may be stored in the nonvolatile memory device100in the SPO and thus the size of the data to be backed up may be reduced.

As the size of the data to be backed up is reduced, the backup of data may be stably completed while the minimum operating power provided through the PLP circuit240is maintained. The number of capacitors for providing the minimum operating power may be reduced and the manufacturing cost may be reduced.

FIG. 13is a flowchart describing a method of operating the data storage apparatus10according to an embodiment. The operation method of the data storage apparatus10according to the embodiment will be described with reference toFIGS. 1 to 12B.

In operation51010, the processor220of the controller200may detect occurrence of SPO. The SPO detection is a known technology in the related art and thus detailed description therefor will be omitted.

When the SPO of the data storage apparatus10occurs, the PLP circuit240of the controller200may be driven through control of the processor220. The PLP circuit240may provide the minimum operating power into the data storage apparatus10using the auxiliary power generator245. The data storage apparatus10may be stably terminated according to the providing of the minimum operating power.

In operation51020, the processor220may detect the interfered first page and the write-interrupted second page from the using memory block BLKo. For example, the processor220may detect the first page and the second page by determining the write-interrupted page, the write-completed page, and interfered page from the using memory block BLKo based on information for pages on which the write operation is performing under the SPO situation and information for the write operation (for example, the first write operation and the second write operation).

For example, the processor220may determine the page on which the write operation is performing under the SPO situation, determine the detected page as the write-interrupted page (for example, the second page), and determine all or a portion of pages coupled to a previous word line close to the detected second page in the vertical direction (for example, Z-axis direction) with respect to the detected second page as the interfered pages. For example, when the detected page is not a last page of the corresponding word line, the processor220may detect each page from a firstly programmed page to a page corresponding to the detected page among pages coupled to a previous word line as the first page. When the detected page is the last page of the corresponding word line, the processor220may detect each of all the pages coupled to the previous word line as the first page.

In operation S1030, the processor220may store data corresponding to the first page and data corresponding to the second page among data temporarily stored in the data buffer DB of the memory230in the backup memory block BLKs of the nonvolatile memory device100.

FIG. 14is a diagram illustrating a data processing system including a solid state drive (SSD) according to an embodiment. Referring toFIG. 14, a data processing system2000may include a host apparatus2100and a SSD2200.

The SSD2200may include a controller2210, a buffer memory device2220, nonvolatile memory devices2231to223n, a power supply2240, a signal connector2250, and a power connector2260.

The controller2210may control an overall operation of the SSD2220.

The buffer memory device2220may temporarily store data to be stored in the nonvolatile memory devices2231to223n. The buffer memory device2220may temporarily store data read from the nonvolatile memory devices2231to223n. The data temporarily stored in the buffer memory device2220may be transmitted to the host apparatus2100or the nonvolatile memory devices2231to223naccording to control of the controller2210.

The nonvolatile memory devices2231to223nmay be used as a storage medium of the SSD2200. The nonvolatile memory devices2231to223nmay be coupled to the controller2210through a plurality of channels CH1to CHn. One or more nonvolatile memory devices may be coupled to one channel. The nonvolatile memory devices coupled to the one channel may be coupled to the same signal bus and the same data bus.

The power supply2240may provide power PWR input through the power connector2260to the inside of the SSD2200. The power supply2240may include an auxiliary power supply2241. The auxiliary power supply2241may supply the power so that the SSD2200is normally terminated even when sudden power-off occurs. The auxiliary power supply2241may include large capacity capacitors capable of charging the power PWR.

The controller2210may exchange a signal SGL with the host apparatus2100through the signal connector2250. The signal SGL may include a command, an address, data, and the like. The signal connector2250may be configured of various types of connectors according to an interfacing method between the host apparatus2100and the SSD2200.

FIG. 15is a diagram illustrating the controller2210ofFIG. 14. Referring toFIG. 15, the controller2210may include a host interface2211, a controller2212, a random access memory (RAM)2213, an error correction code (ECC) component2214, and a memory interface2215.

The host interface2211may perform interfacing between the host apparatus2100and the SSD2200according to a protocol of the host apparatus2100. For example, the host interface2211may communicate with the host apparatus2100through any one among a secure digital protocol, a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, an embedded MMC (eMMC) protocol, a personal computer memory card international association (PCMCIA) protocol, a parallel advanced technology attachment (DATA) protocol, a serial advanced technology attachment (SATA) protocol, a small computer system interface (SCSI) protocol, a serial attached SCSI (SAS) protocol, a peripheral component interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, and a universal flash storage (UFS) protocol. The host interface2211may perform a disc emulation function that the host apparatus2100recognizes the SSD2200as a general-purpose data storage apparatus, for example, a hard disc drive HDD.

The controller2212may analyze and process the signal SGL input from the host apparatus2100. The controller2212may control operations of internal functional blocks according to firmware and/or software for driving the SDD2200. The RAM2213may be operated as a working memory for driving the firmware or software.

The ECC component2214may generate parity data for the data to be transferred to the nonvolatile memory devices2231to223n. The generated parity data may be stored in the nonvolatile memory devices2231to223ntogether with the data. The ECC component2214may detect errors for data read from the nonvolatile memory devices2231to223nbased on the parity data. When detected errors are within a correctable range, the ECC component2214may correct the detected errors.

The memory interface2215may provide a control signal such as a command and an address to the nonvolatile memory devices2231to223naccording to control of the controller2212. The memory interface2215may exchange data with the nonvolatile memory devices2231to223naccording to control of the controller2212. For example, the memory interface2215may provide data stored in the buffer memory device2220to the nonvolatile memory devices2231to223nor provide data read from the nonvolatile memory devices2231to223nto the buffer memory device2220.

FIG. 16is a diagram illustrating a data processing system including a data storage apparatus according to an embodiment. Referring toFIG. 16, a data processing system3000may include a host apparatus3100and a data storage apparatus3200.

The host apparatus3100may be configured in a board form such as a printed circuit board (PCB). Although not shown inFIG. 16, the host apparatus3100may include internal functional blocks configured to perform functions of the host apparatus3100.

The host apparatus3100may include a connection terminal3110such as a socket, a slot, or a connector. The data storage apparatus3200may be mounted on the connection terminal3110.

The data storage apparatus3200may be configured in a board form such as a PCB. The data storage apparatus3200may refer to a memory module or a memory card. The data storage apparatus3200may include a controller3210, a buffer memory device3220, nonvolatile memory devices3231to3232, a power management integrated circuit (PMIC)3240, and a connection terminal3250.

The controller3210may control an overall operation of the data storage apparatus3200. The controller3210may be configured to have the same configuration as the controller2210illustrated inFIG. 15.

The buffer memory device3220may temporarily store data to be stored in the nonvolatile memory devices3231and3232. The buffer memory device3220may temporarily store data read from the nonvolatile memory devices3231and3232. The data temporarily stored in the buffer memory device3220may be transmitted to the host apparatus3100or the nonvolatile memory devices3231and3232according to control of the controller3210.

The nonvolatile memory devices3231and3232may be used as a storage medium of the data storage apparatus3200.

The PMIC3240may provide power input through the connection terminal3250to the inside of the data storage apparatus3200. The PMIC3240may manage the power of the data storage apparatus3200according to control of the controller3210.

The connection terminal3250may be coupled to the connection terminal3110of the host apparatus3100. A signal such as a command, an address, and data and power may be transmitted between the host apparatus3100and the data storage apparatus3200through the connection terminal3250. The connection terminal3250may be configured in various forms according to an interfacing method between the host apparatus3100and the data storage apparatus3200. The connection terminal3250may be arranged in any one side of the data storage apparatus3200.

FIG. 17is a diagram illustrating a data processing system including a data storage apparatus according to an embodiment. Referring toFIG. 17, a data processing system4000may include a host apparatus4100and a data storage apparatus4200.

The host apparatus4100may be configured in a board form such as a PCB. Although not shown inFIG. 17, the host apparatus4100may include internal functional blocks configured to perform functions of the host apparatus4100.

The data storage apparatus4200may be configured in a surface mounting packaging form. The data storage apparatus4200may be mounted on the host apparatus4100through a solder ball4250. The data storage apparatus4200may include a controller4210, a buffer memory device4220, and a nonvolatile memory device4230.

The controller4210may control an overall operation of the data storage apparatus4200. The controller4210may be configured to have the same configuration as the controller2210illustrated inFIG. 15.

The buffer memory device4220may temporarily store data to be stored in the nonvolatile memory device4230. The buffer memory device4220may temporarily store data read from the nonvolatile memory device4230. The data temporarily stored in the buffer memory device4220may be transmitted to the host apparatus4100or the nonvolatile memory device4230through control of the controller4210.

The nonvolatile memory device4230may be used as a storage medium of the data storage apparatus4200.

FIG. 18is a diagram illustrating a network system5000including a data storage apparatus according to an embodiment. Referring toFIG. 18, the network system5000may include a server system5300and a plurality of client systems5410to5430which are coupled through a network5500.

The server system5300may serve data in response to requests of the plurality of client systems5410to5430. For example, the server system5300may store data provided from the plurality of client systems5410to5430. In another example, the server system5300may provide data to the plurality of client systems5410to5430.

The server system5300may include a host apparatus5100and a data storage apparatus5200. The data storage apparatus5200may be configured of the data storage apparatus10ofFIG. 1, the data storage apparatus2200ofFIG. 14, the data storage apparatus3200ofFIG. 16, or the data storage apparatus4200ofFIG. 17.

The above described embodiments of the present invention are intended to illustrate and not to limit the present invention. Various alternatives and equivalents are possible. The invention is not limited by the embodiments described herein. Nor is the invention limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.