Low power flash memory cell and method

Flash memory cells are provided with a high-k material interposed between a floating polysilicon gate and a control gate. A tunnel oxide is interposed between the floating polysilicon gate and a substrate. Methods of forming flash memory cells are also provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process. The high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.

BACKGROUND OF THE INVENTION

A flash memory cell may be formed on a substrate using a double polysilicon structure, with inter-poly oxide interposed between a floating polysilicon gate and a control polysilicon gate. A tunnel oxide is interposed between the floating polysilicon gate and the substrate.

The programming voltage of a flash memory cell is determined by the field required to generate tunnel current through the tunnel oxide, which is interposed between the floating polysilicon gate and the substrate, for example bulk silicon. The thinner the tunnel oxide and the inter-poly oxide the lower the programming voltage will be. As the oxide layers are thinned, the leakage current increases and the charge retention time is reduced. The required charge retention time sets the lower limit of the thickness of both the tunnel oxide and the inter-poly oxide.

SUMMARY OF THE INVENTION

By replacing the inter-poly oxide, which has been silicon dioxide, with a material having a high-k dielectric constant and low leakage current, the programming voltage can be reduced.

The programming voltage (VG) is applied to the control gate, to produce a voltage at the floating gate (VFG). The voltage at the floating gate is given by:VFG=VG⁢CPCP+CT=VG⁢tT⁢ɛPtT⁢ɛP+tP⁢ɛT
where, C is capacitance, t is thickness and ε is the dielectric constant of the insulator. The subscripts T and P denote that the parameter relates to the tunnel oxide or the inter-poly oxide, respectively. The floating gate voltage increases with increasing tunnel oxide thickness (tT), decreasing inter-poly oxide thickness (tP), and increasing inter-poly oxide dielectric constant (εP). Increasing the dielectric constant and decreasing the thickness of the inter-poly oxide is one preferred method of increasing the floating gate voltage, which corresponds to decreasing the programming voltage. Although increasing the tunnel oxide thickness would also increase the floating gate voltage, this option is not preferred, because the tunnel current decreases exponentially with increasing thickness of the tunnel oxide. To maintain desirable tunnel current, the tunnel oxide is preferably maintained as thin as possible. Therefore, one of the preferred methods of reducing the programming voltage is to replace the inter-poly silicon dioxide with a high-k dielectric material.

Accordingly, a flash memory cell structure is provided comprising a high-k dielectric material, for example hafnium oxide or zirconium oxide, interposed between a control gate and a polysilicon floating gate. A tunnel oxide is interposed between the floating gate and a substrate.

Methods of forming flash memory cells are also provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process. The high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.

DETAILED DESCRIPTION OF THE INVENTION

For the present method, a semiconductor substrate is provided. An n-well or a p-well may be formed if desired prior to isolating adjacent device areas. Threshold voltage adjustment may also be performed, if desired. Referring now toFIG. 1, a device structure10is formed by growing, or growing and depositing a tunnel oxide layer12overlying a semiconductor substrate14and depositing a first polysilicon layer16, which may also be referred to as poly1throughout this description, overlying the tunnel oxide layer12, following formation of n-wells or p-wells, if any. The first polysilicon layer16serves as a floating polysilicon gate. The thickness of poly1is referred to as Tp1.

FIG. 2shows a cross-section of the device structure10comprising two adjacent device regions17following etching of the semiconductor substrate14to form trenches18. The depth of the trenches18, which is referred to as XSTI, extends from the top of the substrate surface20to the bottom22of the trenches18. The uncertainty, or variation, in the trench depth is referred to as ΔXSTI. Following etching of the substrate, a cleaning may be performed to reduce, or eliminate, etch damage.

FIG. 3shows the device structure10following the deposition of an oxide layer30. The oxide layer30is deposited to refill the trenches with oxide. The oxide layer30has a minimum thickness that is greater than the maximum possible depth of the trench. Referring to the oxide thickness as TOX, and the uncertainty, or variation, in oxide thickness as ΔTOX, the oxide layer30should be deposited and processed so that the final processed thickness satisfies the condition that:
TOX−ΔTOX>XSTI+ΔXSTI
The oxide may comprise a thin thermal oxide to provide a good interface between the oxide and silicon in the field followed by a deposited oxide. The deposited oxide can be formed by a variety of methods including chemical vapor deposition (CVD) methods, such as, LTO, HPCVD, PECVD, or other CVD methods. Non-CVD methods such as sputtering may also be used. Following deposition of oxide by any suitable method, the oxide may then be densified at a higher temperature, if necessary or desired.

As shown inFIG. 4, a second polysilicon layer40, also referred to herein as poly2, or field poly, is deposited overlying a device structure10. The thickness of poly2is referred to as Tp2. Poly2should have a thickness selected such that the maximum thickness of poly2plus the maximum thickness of oxide layer30is thinner than the minimum depth of the trench plus the minimum thickness of poly1. Accordingly, the thickness of poly2should satisfy the condition:
Tp2+ΔTp2+TOX+ΔTOX<XSTI−ΔXSTI+Tp1−ΔTp1
To satisfy this condition and still have a meaningful thickness of poly2, there is a maximum desired oxide thickness. The maximum oxide layer30thickness should satisfy the condition:
TOX+ΔTOX<XSTI−ΔXSTI+Tp1−ΔTp1−Tp2−ΔTp2
This should result in the top level of the oxide within the trench being above the bottom level of poly1, and the top level of poly2within the trench being below the top level of poly1.

After poly2is deposited, a sacrificial oxide layer, not shown, is deposited overlying the device structure10. The sacrificial oxide layer may be, for example, undensified TEOS. In one embodiment the sacrificial oxide layer is one and a half times thicker than the maximum thickness of poly1. In another embodiment, the sacrificial oxide layer should have a thickness such that the combined thickness of the tunnel oxide layer12, poly1, the oxide layer30, poly2, and the sacrificial oxide layer is approximately two times the total step height of the active area features, which corresponds to the actual physical relief of the top surfaces.

Next, as shown inFIG. 5, the device structure10is polished using CMP to polish the oxide layer30and stop at the top of the second polysilicon layer40in the field region. This may be achieved using a two step process. In the first step, a non-selective slurry is used to remove the overlying oxide and the portion of the second polysilicon layer40overlying active areas within the device regions. The second step utilizes a selective polish, which continues to remove oxide and stops at the first polysilicon layer16in the active areas and at the second polysilicon layer40in the field regions. The actual field oxide is not polished in this step. During the selective polish the active areas are much smaller than the field areas and the polish rate of oxide can be selected to be sufficiently higher than that of polysilicon, for example greater than 5:1 oxide to polysilicon etch ratio, so this CMP process can be readily achieved. Since,
Tp2+ΔTp2+TOX+ΔTOX<XSTI−ΔXSTI+Tp1−ΔTp1
the oxide on poly1is completely removed before the CMP stop at the field poly2.

As shown inFIG. 6, a high-k dielectric material58is deposited overlying the device structure10following CMP. A high-k dielectric material refers to a dielectric material with a dielectric constant higher than that of silicon dioxide. Possible preferred high-k dielectric materials include, ZrO2and HfO2. For example, a 12.9 nm thick film of ZrO2has a relative dielectric constant of18and a leakage current of 200 nA/cm2at 2 volts. An 8 nm thick film of HfO2has a relative dielectric constant of 15 and a leakage current of 170 nA/cm2at 1.5 volts. The leakage current decreases exponentially with the inverse of the square root of thickness. Therefore, the leakage current of thicker ZrO2and HfO2is no larger than that of the CVD oxide film. High-k dielectric materials may provide a suitable replacement for the poly-oxide material, which is currently being used for flash memory transistors. A third polysilicon layer60, also referred to herein as poly3, is deposited overlying the high-k dielectric material58.

Although it is possible to make flash memory cells without non-memory transistors, in one embodiment the flash memory cells will be fabricated on a substrate that also comprises non-memory transistors. When flash memory cells and non-memory transistors are fabricated together it would be preferred to make the process steps as compatible as possible. If non-memory transistors are fabricated with the flash memory cells, a layer of photoresist is applied and patterned to protect the high-k material overlying the flash memory cells. The high-k material may then be etched from the areas overlying the non-memory transistors. The photoresist is then stripped. The third polysilicon layer60, in this embodiment, is deposited over the remaining high-k dielectric material58in the regions where the flash memory cells will be formed, and is deposited over the poly1layer16in the non-memory transistor regions, as shown in FIG.7. The actual gate polysilicon thickness of the non-memory transistors will correspond to the sum of the poly3thickness plus the thickness of poly1that remains after CMP.

In an alternative embodiment involving forming non-memory transistors together with flash memory cells, a layer of sacrificial polysilicon, not shown, is deposited over the high-k material prior applying and patterning the photoresist. The sacrificial polysilicon will be removed from areas overlying non-memory transistors prior to, or in conjunction with, the removal of the high-k material from those areas. This sacrificial polysilicon layer may protect the high-k material during patterning processes, including photoresist strip. When the third polysilicon layer60is then deposited it will overly the remaining sacrificial polysilicon over areas with high-k material. Together the sacrificial polysilicon and the polysilicon60may form the control gate of the flash memory cell.

Referring now toFIG. 8, photoresist70is applied and patterned to define a flash memory gate structure72. In some embodiments, non-memory transistor gate structures74may be defined together with the definition of the flash memory gate structure72. A multi-step etch process may be used to etch the poly3/high-k/poly1stack and the poly3/poly2stack, possibly along with the poly3/poly1stack, in the case of non-memory transistor structures. Some poly2remains under the poly3and the photoresist, including under the high-k material if present. Since TOX−ΔTOX>XSTI+ΔXSTI, poly1is not completely removed from the active region, as shown inFIG. 9, which is a cross-sectional view of the device structure shown inFIG. 8rotated ninety degrees to show the cross-section along the source/channel/drain of a flash memory transistor structure. The thickness of the remaining poly1should be independent of the CMP process. After the second polysilicon layer40has been removed, except where it remains under the photoresist, a highly selective etch is used to etch the remaining portion of the first polysilicon layer16that is not covered by photoresist. By stopping at the bottom of poly2and leaving a thin layer of poly1over the tunnel oxide layer12and then performing a highly selective etch to remove the remaining thin layer of poly1, micro-trenching may be reduced, or eliminated. By using high selectivity plasma etching, the remainder of poly1can be selectively removed without excessive removal of tunnel oxide12in the source and drain region.

The photoresist is then stripped leaving the flash memory gate structure72that comprises the remaining portions of poly1, high-k material, and poly3over each active area, as shown in FIG.10. Some poly2remains under the portion of poly3extending beyond the active region, which is not visible in FIG.10.

After formation of the gate structure, ion implantation may be used to form source and drain regions that are self-aligned to the gate structure. Poly1, poly2, and poly3are also converted to n+ or p+ polysilicon as is common in conventional processes. The flash memory gate structure may alternatively be doped prior to the gate electrode etch, and prior to the source and drain ion implant. The polysilicon gate may also be salicided. Several methods of polysilicon gate doping, silicide or self aligned processes, including salicide processes, may be applied to the present process. The flash memory gate structure72following doping is shown inFIG. 11, which also shows the implanted source and drain regions76.

Although exemplary embodiments, including possible variations have been described, the present invention shall not be limited to these examples, but rather the scope of the present invention is to be determined by the following claims.