Semiconductor package with releasable isolation layer protection

A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.

TECHNICAL FIELD

The instant application relates to semiconductor packaging, and more particularly to semiconductor packages with advanced isolation materials.

BACKGROUND

Discrete high-voltage semiconductor devices such as MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), diodes, etc., are commonly packaged in a molded semiconductor package that includes several leads protruding out an encapsulant body. These types of semiconductor packages are commonly used in high power applications such as automotive, power transmission, HVAC, etc. An important performance consideration in semiconductor packages is heat dissipation. As power semiconductor devices typically generate a substantial amount of heat during operation, package designers seek to improve the thermal dissipation characteristics of the semiconductor package, as it can lead to a favorable improvement in performance. Typical molding materials used to form the package encapsulant body offer excellent electrical insulation properties, but are poor thermal insulators. There is a need to improve the thermal dissipation capability of semiconductor packages without sacrificing electrical performance.

SUMMARY

A semiconductor device is disclosed. According to an embodiment, the semiconductor device comprises a semiconductor package, comprising a package body that comprises an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body comprises a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.

Separately or in combination, the encapsulant portion has a greater hardness than the isolation structure.

Separately or in combination, the encapsulant portion comprises a mold compound, and the isolation structure comprises thermal interface material.

Separately or in combination, the releasable layer completely covers and is releasable from the first surface of the isolation structure.

Separately or in combination, the first outer face of the package body further comprises a first surface of the encapsulant portion that surrounds the isolation structure, and the releasable layer at least partially covers and is releasable from the first surface of the encapsulant portion.

Separately or in combination, the semiconductor package further comprises an opening in the package body that extends through the isolation structure and the encapsulant portion, and the releasable layer extends over the opening.

Separately or in combination, the releasable layer is an adhesive tape that is adhered to and releasable from the first surface of the isolation structure.

Separately or in combination, the releasable layer comprises a main portion and a tab, wherein the main portion is adhered to and releasable from the first surface of the isolation structure, and wherein the tab is connected to the main portion and is decoupled from the package body.

Separately or in combination, the tab extends away from the package body in an opposite direction as the leads.

Separately or in combination, the tab extends away from the package body in the same direction as the leads.

Separately or in combination, the semiconductor package further comprises a die pad, wherein the semiconductor die is mounted on the die pad, and wherein the isolation structure is thermally coupled to the semiconductor die via the die pad.

A method of producing a semiconductor device is disclosed. According to an embodiment the method comprises: providing a semiconductor package, the semiconductor package comprising a package body that comprises an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, wherein the isolation structure is thermally coupled to the semiconductor die, and wherein a first outer face of the package body comprises a first surface of the isolation structure, applying a releasable layer to the first outer face of the package body such that the releasable layer at least partially covers the first surface of the isolation structure, wherein the releasable layer is configured to substantially protect the isolation structure from damage during transport and assembly, and wherein the releasable layer is releasable from the package body by mechanical force.

Separately or in combination, the encapsulant portion comprises a mold compound, and wherein the isolation structure comprises thermal interface material.

Separately or in combination, providing the semiconductor package comprises providing a lead frame strip that comprises a plurality of unit lead frames, each of the unit lead frames comprising a die pad and a plurality of leads that are each connected to a peripheral structure of the lead frame strip, attaching one of the semiconductor dies on each of the unit lead frames, and forming the package body on each of the each of the unit lead frames, and wherein applying the releasable layer comprises attaching a continuous layer of releasable material to each package body on the lead frame strip.

Separately or in combination, the method further comprises cutting the continuous layer to form separated ones of the releasable layers for each package body on the lead frame strip, and separating the unit lead frames from the peripheral structure of the lead frame strip after cutting the continuous layer.

Separately or in combination, forming the package body comprises a molding process, wherein the method further comprises performing a deflashing step after the molding process that removes excess mold material from the package body, and performing a plating process that forms a metal plating on the leads, and the applying of the releasable layer comprises attaching the continuous layer in between the deflashing step and the plating process.

Separately or in combination, the releasable layer comprises an adhesive tape, and wherein applying the releasable layer comprises attaching the adhesive tape to the first surface of the isolation structure after forming the package body.

Separately or in combination, the releasable layer comprises a non-adhesive film, and wherein applying the releasable layer comprises applying an adhesive to the first surface of the isolation structure after forming the package body and attaching the non-adhesive film to the adhesive.

Separately or in combination, the releasable layer comprises a main portion and a tab, and wherein the releasable layer is applied to the first outer face of the package body such that body such that the tab extends away from the package body in an opposite direction as the leads.

Separately or in combination, the releasable layer comprises a main portion and a tab, and wherein the releasable layer is applied to the first outer face of the package body such that that the tab extends away from the package body in the same direction as the leads.

DETAILED DESCRIPTION

Disclosed herein is a semiconductor package with an advanced isolation structure and a releasable layer that advantageously protects the advanced isolation structure. The semiconductor package comprises an encapsulant material that in combination with the advanced isolation structure forms an electrically insulating package body that encapsulates a semiconductor die. The advanced isolation structure has a higher thermal conductivity than the encapsulant material. For example, the advanced isolation structure may comprise a thermal interface material (TIM) whereas the encapsulant material comprises mold compound. The advanced isolation structure is thermally coupled to the semiconductor die, thus providing a thermally efficient mechanism for extracting heat away from the semiconductor die. The material properties of the advanced isolation structure, while advantageous for thermal coupling, make it susceptible to damage such as scratching. The releasable layer is an advantageous temporary structure that protects the advanced isolation structure from damage. Moreover, the releasable layer can be easily removed by simple mechanical force before the semiconductor package is mounted.

Referring toFIG.1, a semiconductor package100is depicted, according to an embodiment. The semiconductor package100comprises a package body102. The package body102is an electrically insulating structure that encapsulates and electrically isolates a semiconductor die104(shown inFIG.2). The semiconductor package100comprises a plurality of leads106that protrude out from the package body102. The package leads106are electrically conductive structures that are configured to be inserted into a circuit carrier, such as a PCB. As shown, the semiconductor package100comprises three of the package leads106. More generally, the semiconductor package100may comprise different numbers of the package leads106, e.g., two, three, four, etc.

The package body102comprises a first outer face108, a second outer face110, and outer edge sides112extending between the first and second outer faces108,110. The first and second outer faces108,110may be the largest (area wise) surfaces of the package body102. According to an embodiment, the semiconductor package100comprises an opening114that extends between the first and second outer faces108,110. The opening114may be dimensioned to receive a fastener114, e.g., in the manner depicted inFIG.2.

According to an embodiment, the semiconductor package100is configured as a discrete power device. A discrete power device refers to a single packaged device that is configured to block high voltages and and/or to conduct high currents as between two load terminals. Generally speaking, a discrete power device may be rated to block voltages of at least 100V, and more commonly on the order of 250V, 500V, 600V, 1,200V, 2,000V and/or may be rated to conduct currents of 10 A, 50 A, 100 A, 500 A or more. A discrete power device may comprise one or more semiconductor dies104connected between the two load terminals of the semiconductor package100. These semiconductor dies104may be configured as a discrete diode die, a discrete MOSFET (Metal Oxide Semiconductor Field Effect Transistor) die, a discrete IGBT (Insulated Gate Bipolar Transistor) die, a discrete HEMT (High Electron Mobility Transistors) die, a discrete JFET (Junction Field Effect Transistors) die, etc. These semiconductor dies104may be rated to block voltages of at least 100V, and more commonly on the order of 250V, 500V, 600V, 1,200V, 2,000V and/or may be rated to conduct currents of 10 A, 50 A, 100 A, 500 A or more.

In a particular embodiment of a discrete power device, the semiconductor package100may be configured as a discrete transistor package. For example, the semiconductor package100may be configured as a discrete IGBT, a discrete MOSFET, a discrete HEMT, etc. In these package types, the package leads106may correspond to the gate, source and drain terminals in the case of a MOSFET, the gate, emitter and collector terminals in the case of an IGBT, etc. A discrete transistor package may comprise a single transistor die or multiple transistor dies connected in parallel with one another so as to provide the equivalent functionality of a single transistor. Additionally or alternatively, a discrete transistor package may comprise a fourth lead that is configured as a sense terminal, (e.g., source-sense, drain-sense, etc.).

The package body102comprises an encapsulant portion116. The encapsulant portion116is formed from a rigid and electrically insulating material that provides high voltage isolation. Examples of these materials include mold compound, thermosetting plastic, epoxy, resins, and laminate materials. The encapsulant portion116can be formed by a molding process such as injection molding, compression molding, transfer molding, etc. Alternatively, the encapsulant portion116can be a laminate structure that is formed by successively stacking layers of laminate material on top of one another.

The package body102additionally comprises an isolation structure118. The isolation structure118is an electrically insulating structure with higher thermal conductivity than the encapsulant portion116. For example, the isolation structure118may have a thermal conductivity on the order of at least 1 W/mK (Watt per Meter-Kelvin), at least 2 W/mK, at least 3 W/mK, or at least 5 W/m, whereas the encapsulant portion116may have a thermal conductivity of no greater than 1 W/mK, or no greater than 0.1 W/mK. The isolation structure118may comprise a thermal interface material (TIM), a thermal grease, or a phase change material. Examples of various configurations for the isolation structured118and/or materials for the isolation structure118are described in in U.S. application Ser. No. 14/501,070 filed on Sep. 30, 2014, U.S. application Ser. No. 15/333,993 filed on Oct. 25, 2016, and U.S. application Ser. No. 16/816,561 filed on Mar. 12, 2020, the content of each document being incorporated by reference in its entirety. In an embodiment, the isolation structure118comprises a silicone matrix and thermally conductive and electrically insulating filler particles suspended in the material. These filler particles may be a metal oxide and/or metal nitride, in particular at least one of SiO2, Al2O3, AlN, ZrO2, Si3N4, BN, diamond, etc.

The first outer face108of the package body102comprises a first surface of the isolation structure118. That is, the isolation structure118forms at least part of the first outer face108of the package body102. The first surface of the isolation structure118may be coplanar with a surface of the encapsulant portion116at the first outer face108. For example, the isolation structure118can be disposed within a recess formed within the encapsulant portion116such that the encapsulant portion116forms a ring that surrounds the isolation structure118. More generally, the shape and arrangement of the isolation structure118may vary. For example, the isolation structure118may form a complete outer face of the package body102and/or may be exposed at multiple faces of the package body102.

Referring toFIG.2, an assembly that comprises the semiconductor package100and a heat sink200is shown. The semiconductor package100is mounted on the heat sink200with the first outer face108of the package body102flush against the heat sink200. The semiconductor package100comprises a die pad120and a semiconductor die104that is mounted on the die pad120. The die pad120and the leads106may be collectively provided from a lead frame formed of metal, such as copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), etc., alloys or combinations thereof. A terminal of the semiconductor die104(e.g., a drain, collector, etc.) is electrically connected to one of the leads106via the die pad120and additional terminals of the semiconductor die104(e.g. source, emitter, gate, etc.) are electrically connected to the leads106by bond wires. More generally, any of a variety of interconnect elements such as ribbons, clips, etc. may be used to complete the electrical connections between the semiconductor die104and the leads106.

The semiconductor package100is mounted to the heat sink200such that the die pad120and the isolation structure118provide a thermally conductive path that transfers heat between the semiconductor die104and the heat sink200. The isolation structure118is thermally coupled to the semiconductor die104via the die pad120, which in turn is thermally coupled to the semiconductor die104. This thermal conduction path may also comprise adhesives and intermediary materials, e.g., solder, conductive glue, etc. The high thermal conductivity of the isolation structure118allows for efficient heat transfer between the semiconductor die104and the heat sink200. Moreover, the electrically insulating properties of the isolation structure118mean that the semiconductor die104is electrically isolated from the heat sink200, which allows for high voltage operation of the semiconductor die104. The semiconductor package100may be mounted by a fastener122, e.g., screw, pin, bolt, etc. The fastener122may extend completely through the opening114and be received by the heat sink200. Additionally or alternatively, the fastener and the opening114may be may be used in combination with an external clip to secure the semiconductor package100to the heat sink200.

The isolation structure118may be a relatively soft structure. For example, the isolation structure118may have a compressibility in a range between 1% and 40% (which may be measured by applying a 1 N force at a layer of the interface structure having a thickness of 250 μm using a Vickers-micro-indenter), in particular in a range between 25% and 35%. When the isolation structure118is brought in contact with the heat sink200, the soft material properties of the isolation structure118ensure a proper full-surface contact and thus an efficient heat transfer from the isolation structure118to heat sink200. In particular, it may be sufficient to directly connect the isolation structure118with the heat sink200using the fastener122, and in particular without the need of thermal grease in between the thermal interface structure and the heat sink200. By contrast, the encapsulant portion116has a greater hardness than the isolation structure118. For example, an encapsulant portion116formed from any of the above-listed materials (e.g., mold compound, thermosetting plastic, epoxy, resins, laminate materials, etc.) may have a compressibility of less than 5%, and more commonly less than 1%, less than 0.5%, or less than 0.1% on the same measurement under the using a Vickers-micro-indenter. This difference in hardness is attributable to the different material composition of the isolation structure118and the encapsulant portion116.

The mechanical properties of the isolation structure118are such that the semiconductor package100is susceptible to damage, particularly in the time between the manufacture of the semiconductor package100and when the semiconductor package100is mounted in an assembly (e.g., as shown inFIG.2). At this time, the semiconductor package100may be tested and handled by testing equipment, packaged for shipping, transported from a manufacturer to a customer, removed from the shipping packaging, and mounted on a customer apparatus such as a heat sink and/or circuit board. A mechanical stimulus applied by humans and/or machines during any of these steps may form scratches, cracks and other imperfections may arise in the isolation structure118. This damage may degrade performance and/or render the semiconductor package100dysfunctional.

Referring toFIG.3, an assembly that comprises the semiconductor package100and a heat sink200is shown, according to another embodiment. The semiconductor package100is substantially similar to the embodiment shown inFIGS.1-2, with the following exceptions. One difference is that there is no opening114provided in the package body102. In this case, the package body102may be configured such that the encapsulant portion116is a continuous region of mold compound that covers and protects the semiconductor die104. This semiconductor package100may be secured to the heat sink200using a clip structure. A second difference in this assembly is that the first outer face108of the encapsulant portion116is a completely planar surface, and the isolation structure118is disposed on this planar surface. That is, there is no recess in the encapsulant material that accommodates the isolation structure118. Various embodiments of the semiconductor package100and the assembly may incorporate either one of the above-mentioned differences.

Referring toFIG.4, a semiconductor device300that comprises a releasable layer400affixed to the semiconductor package100is depicted, according to an embodiment. When the releasable layer400is affixed to the semiconductor package100and covering the isolation structure118, it provides a protective sheath that prevents scratching or defacing of the isolation structure118. Thus, the releasable layer400substantially mitigates or eliminates the above-described damage that may occur in the time between the manufacture of the semiconductor package100and when the semiconductor package100is mounted in an assembly. As shown, the releasable layer400completely covers the first surface of the isolation structure118, and thus completely protects all exposed surfaces of the isolation structure118. In the case that the semiconductor package100comprises the opening114, the releasable layer400may extend over the opening114as well. In the case that the isolation structure118is disposed within a recess formed within the encapsulant portion116, the releasable layer400may extend past the isolation structure118such that the releasable layer400may partially cover and be releasable from the first outer face108of the encapsulant portion116. In the case that the isolation structure118is disposed outside of the plane of first outer face108of the encapsulant portion116, the releasable layer400may exclusively contact the isolation structure118. More generally, the releasable layer400may at least partially cover any exposed surface of an isolation material, thus providing the protective benefit as described herein, and may also contact and be releasable from other adjacent surfaces of the semiconductor package100

The releasable layer400is releasable from the semiconductor package100. This means that the releasable layer400is a temporary element that can be removed from the semiconductor package100by mechanical force, e.g., human hand manipulation or robotic motion, that is non-destructive to all elements of the semiconductor package100including the isolation structure118. The releasable layer400may be a relatively thin film (e.g., between 0.1-0.01 mm thick) that is adhesively bonded to the semiconductor package100. The strength of the adhesive that secures the releasable layer400to the semiconductor package100is selected such that the releasable layer400can be removed, e.g., by peeling, without substantially damaging or altering the isolation structure118. In this way, the releasable layer400can be applied to the semiconductor package100once manufacture is complete and easily removed by a downstream user, e.g., by removing the releasable layer400immediately before mounting the semiconductor package100.

According to one embodiment, the releasable layer400comprises an adhesive tape. For example, the releasable layer400can comprise a non-conductive adhesive tape, e.g., a tape comprising polymer, rubber, silicone, etc. with a thickness between 0.1-0.01 mm. This adhesive tape can be adhered to the semiconductor package100in a commonly known manner by applying the adhesive side of the adhesive tape to the first outer face108of the package body102.

According to another embodiment, the releasable is layer a non-adhesive film. For example, the releasable layer400can be film of non-conductive material comprising polymer, rubber, silicone with a thickness between 0.1 mm and 0.01 mm. This film can be secured to the package by separately applying an electrically insulating adhesive such as an epoxy-based or silicone-based adhesive to the first outer face108of the package body102and subsequently attaching the film to the electrically insulating adhesive.

Referring toFIG.5, a semiconductor device300that comprises a releasable layer400affixed to the semiconductor package100is depicted, according to another embodiment. In this embodiment, the releasable layer400comprises a main portion402and a tab404. The main portion402is adhered to and releasable from a portion of the first outer face108of the package body102that comprises the first surface of the isolation structure118. Thus, the main portion402protects the isolation structure118in a similar manner as previously described. The tab404is connected to the main portion402and is decoupled from the package body102. That is, the tab404is not adhered to any surface of the package body102. As a result, the tab404provides a handle that can be grasped, e.g., by a human hand or robotic hand. The tab404therefore allows for easy releasing (e.g., peeling) of the releasable layer400by providing a surface from which to grip the releasable layer400. As shown, the tab404extends away from the package body102in an opposite direction as the leads106.

Referring toFIG.6, a semiconductor device300that comprises a releasable layer400affixed to the semiconductor package100is depicted, according to another embodiment. The embodiment ofFIG.5is substantially identical to that ofFIG.4, except that the orientation of the releasable layer400is reversed such that the tab404extends away from the package body102in the same direction as the leads106. This represents one other potential arrangement for a releasable layer400that comprises a tab404. More generally, the orientation, number, and geometry of the tab404(or tabs) may vary from the specific embodiments shown inFIGS.4and5. For example, the tab404may have any desired shape, and may be designed to be compatible with a particular apparatus for removing the releasable layer400. Additionally or alternatively, the releasable layer400may have multiple tabs404, e.g., for purposes of redundancy.

Referring toFIG.7, an assembly for forming the semiconductor package100is shown. The assembly comprises a lead frame strip124that comprises a plurality of unit lead frames126. Each of the unit lead frames126comprises a die pad120(e.g., as shown inFIG.2) and a plurality of leads106, thereby providing the lead frame configuration of the semiconductor package100as previously described with reference toFIG.1. The assembly shown inFIG.6corresponds to an intermediate phase of manufacture before the leads106are detached from a peripheral structure128of the lead frame strip124.

In the assembly ofFIG.7, a continuous layer408of releasable material is applied to the first outer face108of each package body102. That is, one strip of material is used to provide the releasable layer400for each semiconductor package100. The continuous layer408can be a layer of an adhesive tape, e.g., as previously described. Alternatively, the continuous layer408can be a non-adhesive film that is bonded to the semiconductor package100by a separate adhesive, e.g., as previously described.

Referring toFIG.8, a process flow for a method of producing a semiconductor device300comprising the semiconductor package100is depicted, according to an embodiment.

In a first process step500, the semiconductor dies104are attached to the die pads120for each of the unit lead frames126. This may be done by soldering, for example.

In a second process step502, a wire bonding process is performed to form the bond wires for each of the unit lead frames126.

In a third process step504, a molding process is performed. The molding process forms the encapsulant portion116of the package body102, e.g., by a transfer molding technique.

In a fourth processing step506, a post mold cure is performed so as to harden the encapsulant portion116of the package body102.

In a fifth process step508, a second molding process is performed. The second molding process forms the isolation portion of the package body102, e.g., by a compression molding technique.

In a sixth processing step510, a post mold cure if performed so as to harden the isolation portion of the package body102.

In a seventh process step512, a deflashing step is performed. The deflashing step removes mold flashes, i.e., excess portions or strands of mold material, from the package body102. The deflashing may be done using a chemical solvent, for example.

In an eighth process step514, an adhesive layer masking step is performed. The adhesive layer masking step applies a continuous layer408of releasable material to the first outer face108of each package body102, e.g., in the manner depicted inFIG.6.

In a ninth process step516, the adhesive layer is cured to the semiconductor package100. This curing may involve the application of ultraviolet light, for example.

In a tenth process step518, a plating process is performed. The plating process forms a metal plating (e.g., Ag, Cu, Ni, etc.) on the exposed metal leads106of each semiconductor package100. The plating process may comprise an electroplating process or an electroless plating technique, for example.

In an eleventh process step520, an adhesive layer cutting step is performed. The adhesive layer cuts the continuous layer408of releasable material to form the releasable layer400for each of the semiconductor packages100. This may be done by cutting the continuous layer408along a separation line130, e.g., as shown inFIG.7.

In a twelfth process step522, a package singulation step is performed. The package singulation step separates each semiconductor package100from the lead frame strip124, e.g., by cutting the leads106so as to detach them from the peripheral structure128. Advantageously, the releasable layer400is present on the isolation structure118during this step such that the package singulation step does not scratch the isolation structure.

In a thirteenth process step524, the semiconductor package100is tested. For example, the electrical functionality of the semiconductor package100and/or the electrical isolation of the isolation structure118may be tested by test equipment. Advantageously, the releasable layer400is present on the isolation structure118during this step such that the testing step does not scratch the isolation structure.

In a fourteenth process step526, the semiconductor package100is arranged in packaging for transport, e.g., by arranging the semiconductor package100in plastic, cardboard, Styrofoam, etc. Advantageously, the releasable layer400is present on the isolation structure118during this step such that the packaging step does not scratch the isolation structure.

The semiconductor package100disclosed herein illustrates just one example of a semiconductor package that includes an advanced isolation material thermally coupled to a semiconductor die. The releasable layer400described herein is more generally applicable to any type of semiconductor package that comprises a region of isolation material that is softer and more susceptible to scratching or other types of damage than conventional encapsulant material.