Production method for semiconductor device

It is intended to provide a method of producing a semiconductor device, comprising the steps of: providing a substrate on one side of which at least one semiconductor pillar stands; forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar; forming a conductive film on the first dielectric film; removing by etching a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar; forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar; etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar; forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and partially removing by etching the conductive film using the resist pattern as a mask while protecting, by the protective film-based sidewall, the portions of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar, to form a gate electrode and a gate line extending from the gate electrode.

TECHNICAL FIELD

The present invention relates to a production method for a semiconductor, and more particularly to a structure and a production method for an SGT (Surrounding Gate Transistor) which is a vertical MOS transistor comprising a pillar-shaped semiconductor layer having a sidewall serving as a channel region, and a gate electrode formed to surround the channel region.

BACKGROUND ART

With a view to achieving higher integration and higher performance of a semiconductor device, a vertical transistor SGT has been proposed which comprises a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (see the following Patent Documents 1 and 2). In the SGT, a source, a gate and a drain are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor. In addition, the gate is formed to surround a channel region, so that, as a size of a pillar-shaped semiconductor layer is reduced, channel controllability of the gate can be effectively improved to obtain steep subthreshold characteristics. Furthermore, an improvement in carrier mobility based on electric field relaxation in the channel region can be expected by setting an impurity concentration and a size of the pillar-shaped semiconductor layer to allow the pillar-shaped semiconductor layer to become fully depleted. Therefore, the use of the SGT makes it possible to simultaneously achieve higher integration and higher performance as compared with the conventional planar transistor.

FIG. 177(a) shows a top plan view of a CMOS inverter designed using the SGT disclosed in the Patent Document 1, andFIG. 177(b) is a sectional view taken along the cutting-plane line A-A′ inFIG. 177(b).

Referring toFIGS. 177(a) and177(b), an N-well1302and a P-well1303are formed in an upper region of a Si substrate1301. A pillar-shaped silicon layer1305forming a PMOS (PMOS-forming pillar-shaped silicon layer1305) and a pillar-shaped silicon layer1306forming an NMOS (NMOS-forming pillar-shaped silicon layer1306) are formed on a surface of the Si substrate, specifically on respective ones of the N-well region and the P-well region, and a gate1308is formed to surround the pillar-shaped silicon layers. Then, each of a P+drain diffusion layer1310formed beneath the PMOS-forming pillar-shaped silicon layer, and a N+drain diffusion layer1312formed beneath the NMOS-forming pillar-shaped silicon layer, is connected to an output terminal Vout7. A source diffusion layer1309formed in an upper portion of the PMOS-forming pillar-shaped silicon layer is connected to a power supply potential Vcc7, and a source diffusion layer1311formed in an upper portion of the NMOS-forming pillar-shaped silicon layer is connected to a ground potential Vss7. Further, the gate1308common to the PMOS and the NMOS is connected to an input terminal Vin7, and the diffusion layer (1310,1312) beneath a respective one of the pillar-shaped silicon layers is connected to the output terminal Vout7. In this manner, the CMOS inverter is formed.

FIGS. 178(a) to178(f) show a schematic process flow for forming a pillar-shaped silicon layer and a gate electrode in the SGT disclosed in the Patent Document 1. InFIG. 178(a), a pillar-shaped silicon layer1401is formed on a silicon substrate by etching. InFIG. 178(b), a gate dielectric film1402is formed. InFIG. 178(c), a gate conductive film1403is formed. InFIG. 178(d), a resist1404for a gate line pattern is formed to be in contact with a portion of a gate conductive film surrounding the pillar-shaped silicon layer. InFIG. 178(e), the gate conductive film1403is etched back to form a gate electrode1403and a gate line1405of an SGT. InFIG. 178(f), the resist is released. In the above process flow, the gate electrode1403is formed around the pillar-shaped silicon layer1401by a desired film thickness, in a self-alignment manner, so that two pillar-shaped silicon layers each having a gate electrode to be applied with a different potential can be arranged side-by-side with a relatively small distance therebetween.

However, in the above process flow, the resist1404must be formed to be accurately in contact with the portion of the gate conductive film around a sidewall of the pillar-shaped silicon layer, inFIG. 178(d). Therefore, a process margin in a lithography step of forming the gate line is small, which causes difficulty in stably fabricating the gate line. The following description will be made in regard to this point.

FIGS. 179(a) to179(c) illustrate a process flow in case where the resist1404is positionally deviated to the right side inFIG. 178(d).FIG. 179(a) shows a state after a resist1414for a gate line pattern is positionally deviated to the right side during alignment of a lithographic exposure. In this state, there arises a space between the resist1414and a sidewall of a pillar-shaped silicon layer1411. InFIG. 179(b), a gate etch step is performed. InFIG. 179(c), the resist is released. In this case, a gate electrode1413and a gate line1415of a resulting SGT are undesirably disconnected from each other.

FIGS. 180(a) to180(c) illustrate a process flow in case where the gate-line resist1404is positionally deviated to the left side inFIG. 178(d).FIG. 180(a) shows a state after a resist1424for a gate line pattern is positionally deviated to the left side during alignment of a lithographic exposure. In this state, there arises an overlapped area1426between the resist1424and a portion of a gate electrode on a top of a pillar-shaped silicon layer1421. InFIG. 180(b), a gate etch step is performed. InFIG. 180(c), the resist is released. In this case, a gate electrode1423of a resulting SGT undesirably has a shape abnormality1427on a side where the resist is formed.

A value of the above positional deviation of the resist arising from the alignment varies depending on a position on a wafer and a position in a chip, and thereby it is impossible to keep positional deviations in all patterns on a wafer, within a range free of the occurrence of the above problem. Thus, in the above SGT forming method, a process margin for forming the gate line becomes extremely small, and thereby it is impossible to produce an integrated circuit in high yield.

As one of the measures against the problem in the above SGT gateline forming method, the following Non-Patent Document 1 discloses an SGT gate-line forming method which is improved in process margin.FIGS. 181(a) to181(g) illustrate a schematic process flow for forming a pillar-shaped silicon layer and a gate electrode of an SGT, which is disclosed in the Non-Patent Document 1. This process flow will be described below. InFIG. 181(a), a silicon substrate is etched to form a pillar-shaped silicon layer1501. InFIG. 181(b), a gate dielectric film1502is formed. InFIG. 181(c), a gate conductive film is formed. InFIG. 181(d), the gate conductive film, and a portion of the gate dielectric film on a top of the pillar-shaped silicon layer, are polished by chemical mechanical polishing (CMP). InFIG. 181(e), the resulting gate conductive film is etched back in such a manner that a portion of the gate conductive film surrounding the pillar-shaped silicon layer is etched to have a desired gate length. InFIG. 181(f), a resist for a gate line pattern is formed by lithography. InFIG. 181(g), the gate conductive film is etched to form a gate electrode and a gate line.

In the above process flow, although a process margin in a lithography step of forming the gate line becomes larger, as compared with the process flow disclosed in the Patent Document 1, the gate electrode to be formed around the pillar-shaped silicon layer is not formed in a self-alignment manner, with respect to the pillar-shaped silicon layer. As a result, the gate electrode will be widely formed around the pillar-shaped silicon layer, and a film thickness of the gate electrode to be formed around the pillar-shaped silicon layer will vary depending on a deviation in alignment of a resist pattern and an error in size of the resist pattern. Thus, if a distance between two pillar-shaped silicon layers each having a gate electrode to be applied with a different potential is reduced, the respective gate electrodes will be short-circuited with each other. Therefore, an occupancy area of an SGT-based circuit is liable to become large.Patent Document 1: JP 2-188966APatent Document 2: JP 7-99311ANon-Patent Document 1: Ruigang Li, et al., “50 nm Vertical Surrounding Gate MOSFET with S-factor of 75 mv/dec”, Device Research Conference, 2001, p. 63

As a prerequisite to achievement of an SGT applicable to a product comprising a highly-integrated and high-performance logic circuit, such as a CPU, it is necessary for a gate forming process to meet the following requirements. A first requirement is that it is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second requirement is that it is less vulnerable to a deviation in exposure alignment during gate line formation. A third requirement is that it is capable of accurately controlling a gate length to minimize a variation in gate length and increase a process margin.

In view of above problems, it is an object of the present invention to propose an SGT production method capable of solving the above problems.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provided a method of producing a semiconductor device. The method comprises: providing a substrate on one side of which at least one semiconductor pillar stands; forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar; forming a conductive film on the first dielectric film; removing by etching a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar; forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar; etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar; forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and partially removing by etching the conductive film using the resist pattern as a mask while protecting, by the protective film-based sidewall, the portions of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar, to form a gate electrode and a gate line extending from the gate electrode.

For example, the step of removing by etching a portion of the conductive film located on a top surface and along a upper portion of a side surface of the semiconductor pillar includes the sub-steps of: forming a second dielectric film on the conductive film to allow the semiconductor pillar to be buried therein; flattening a top surface of the second dielectric film; and removing by etching a portion of the conductive film and the second dielectric film each located along the side surface of the semiconductor pillar to form the conductive film and the second dielectric film to have substantially the same height.

According to a second aspect of the present invention, there is provided a method of producing a semiconductor device. The method comprises: providing a substrate on one side of which at least one semiconductor pillar stands, the semiconductor pillar having a stopper film formed on a top surface thereof; forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar; forming a conductive film on the first dielectric film; forming a second dielectric film on the conductive film to allow the semiconductor pillar to be buried therein; flattening a top surface of the resulting product by chemical mechanical polishing (CMP), using the stopper film as a CMP stopper; removing by etching a portion of the second dielectric film and the conductive film each located along an upper portion of a side surface of the semiconductor pillar to form the conductive film and the second dielectric film to have substantially the same height; forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar; etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar; removing the second dielectric film; forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and partially removing by etching the conductive film using the resist pattern as a mask while protecting, by the protective film-based sidewall, the portions of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar, to form a gate electrode and a gate line extending from the gate electrode.

According to a third aspect of the present invention, there is provided a method of producing a semiconductor device. The method comprises: providing a substrate on one side of which at least one semiconductor pillar stands; forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar; forming a conductive film on the first dielectric film to allow the semiconductor pillar to be buried therein; etching an upper portion of the conductive film to remove a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar; forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar; etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar; forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and partially removing by etching, using the resist pattern as a mask, the conductive film to form at least a portion of the gate line, and partially removing by etching, using the protective film-based sidewall as a mask, the conductive film and the first dielectric film to form at least a portion of a gate electrode to have the desired film thickness.

For example, the method further comprises, as a preprocessing for the etching an upper portion of the conductive film to remove a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar, the step of flattening a top surface of the conductive film.

According to a fourth aspect of the present invention, there is provided a method of producing a semiconductor device. The method comprises: providing a substrate on one side of which at least one semiconductor pillar stands, the semiconductor pillar having a stopper film formed on a top surface thereof; forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar; forming a conductive film on the first dielectric film to allow the semiconductor pillar to be buried therein; flattening a top surface of the resulting product by chemical mechanical polishing (CMP), using the stopper film as a CMP stopper; etching an upper portion of the conductive film to remove a portion of the conductive film located along an upper portion of a side surface of the semiconductor pillar; forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar; etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar; forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and partially removing by etching, using the resist pattern as a mask, the conductive film to form at least a portion of the gate line, and partially removing by etching, using the protective film-based sidewall as a mask, the conductive film and the first dielectric film to form at least a portion of a gate electrode to have the desired film thickness.

For example, the conductive film is a layered structure film comprising a thin metal film on the side of the first dielectric film, and a polysilicon film.

For example, the protective film is a silicon nitride film.

For example, each of the protective film and the stopper films is a silicon nitride film.

For example, the substrate further has a diffusion region formed in contact with a lower part of the semiconductor pillar.

For example, the method further comprises the step of forming, in an upper portion of the semiconductor pillar, a diffusion region having a same conductivity type as that of the diffusion region formed in contact with a lower part of the semiconductor pillar.

For example, the diffusion region formed beneath the pillar-shaped semiconductor layer is formed in a surface region of the substrate.

The term “on one side” appears in the present specification and claims in the form of “A is on one side of B”, which should be interpreted to mean either “A is situated in contact with B on one side of B,” or “A is situated away from B on one side of B,” whenever the context allows such an interpretation.

As described above, in the production method of the present invention, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed. Thus, the method is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness, and less vulnerable to a deviation in exposure alignment during gate line formation. This makes it possible to simultaneously solve both the following conventional problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner.

Further, the step of flattening a top surface of a gate conductive film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. This makes it possible to simultaneously solve both the following conventional problems: a disconnection or open of a gate line and a variation in gate length e arising from a lithography step of forming a gate line; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIGS. 1(a) and1(b) are, respectively, a top plan view and a sectional view of an NMOS SGT formed by a SGT production method according to a first embodiment of the present invention. With reference toFIGS. 1(a) and1(b), the NMOS SGT formed by the SGT production method according to the first embodiment will be described below.

A pillar-shaped silicon layer102is formed on a silicon substrate101, and a gate dielectric film105and a gate electrode106aare formed around the pillar-shaped silicon layer102. An N+drain diffusion layer103is formed beneath the pillar-shaped silicon layer102, and an N+source diffusion layer104is formed in an upper portion of the pillar-shaped silicon layer102. A contact107, a contact108, and a contact109, are formed on the N+drain diffusion layer103, the N+source diffusion layer104, and a gate line106bextending from the gate electrode106a, respectively.

Under conditions that the N+source diffusion layer104is connected to a GND potential, and the N+drain diffusion layer103is connected to a power supply potential Vcc, a potential ranging from zero to Vcc is applied to the gate electrode106ato allow the SGT to operate as a transistor.

With reference toFIGS. 2(a) to16(b), one example of the SGT production method according to the first embodiment will be described below. InFIGS. 2(a) to16(b), the figure suffixed by (a) is a top plan view, and the figure suffixed by (b) is a sectional view taken along the line A-A′.

Referring toFIGS. 2(a) and2(b), a silicon nitride film110serving as a hard mask is formed on a silicon substrate101to have a film thickness of about 50 to 150 nm.

Referring toFIGS. 3(a) and3(b), the hard mask110and the silicon substrate101are etched to form a pillar-shaped silicon layer102. The pillar-shaped silicon layer102is formed to have a height dimension of about 30 to 300 nm, and a diameter of about 5 to 100 nm.

Referring toFIGS. 4(a) and4(b), an impurity, such as P or As, is introduced into a top surface of the silicon substrate, for example, by ion implantation, to form an N+drain diffusion layer103therein. During this step, the silicon nitride film110on a top of the pillar-shaped silicon layer functions as a stopper for preventing the impurity from being injected into the top of the pillar-shaped silicon layer.

Referring toFIGS. 5(a) and5(b), a gate dielectric film105and a gate conductive film106are formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate conductive film106is formed to have a film thickness of about 10 to 100 nm.

Referring toFIGS. 6(a) and6(b), a silicon oxide film111is formed to allow the pillar-shaped silicon layer to be buried therein.

Referring toFIGS. 7(a) and7(b), the silicon oxide film111, and respective portions of the gate conductive film and the gate dielectric film above the pillar-shaped silicon layer, are polished by chemical mechanical polishing (CMP), to flatten a top surface of the gate conductive film. Through the flattening of a top of the gate conductive film by CMP, a configuration of the gate conductive film is improved to facilitate control of a gate length. During the CMP, the silicon nitride film110on the top of the pillar-shaped silicon layer is used as a CMP stopper. The use of the silicon nitride film110as a CMP stopper makes it possible to control an amount of CMP with high repeatability. In place of the silicon nitride film, the film to be used as a CMP stopper may be any other suitable film capable of functioning as the CMP stopper film. This modification may also be made in after-mentioned embodiments.

Referring toFIGS. 8(a) and8(b), the gate conductive film106and the silicon oxide film111are etched back, wherein the gate conductive film106is etched to fix a gate length. Preferably, etching conditions to be used in this step are set to allow the gate conductive film106and the silicon oxide film111to be etched at the same rate, and at a higher selectivity ratio relative to the silicon nitride film110. The etching of the gate conductive film106and the silicon oxide film111at the same rate makes it possible to suppress occurrence of a step between respective top surfaces of the two films, which improves a configuration of a silicon nitride film-based sidewall112to be formed in a next step.

Referring toFIGS. 9(a) and9(b), a silicon nitride film112ais formed by a film thickness required for the gate conductive film106. Subsequently, as shown inFIGS. 10(a) and10(b), the silicon nitride film112ais etched back to form a silicon nitride film-based sidewall112. In this step, a film thickness of the silicon nitride film-based sidewall112is controlled to become equal to that of the gate conductive film106, by adjusting a formed film thickness of the silicon nitride film112a, and then finely adjusting the formed film thickness based on an amount of the etch-back. A portion of the gate conductive film106covered by the silicon nitride film-based sidewall112will be protected during etching for forming a gate line in a subsequent step. This makes it possible to form the gate electrode in a self-alignment manner and with a desired film thickness, so as to reduce an occupancy area. In the first embodiment, the silicon nitride film is used as a sidewall protective film. Alternatively, any other suitable film capable of functioning as the sidewall protective film, such as a silicon oxide film, may also be used. This modification may also be made in the after-mentioned embodiments.

Referring toFIGS. 11(a) and11(b), the silicon oxide film111remaining on the gate conductive film is removed by wet etching.

Referring toFIGS. 12(a) and12(b), a resist or a multilayer resist is applied, and a gate line pattern is formed with a resist113by lithography.

Referring toFIGS. 13(a) and13(b), the gate conductive film and the gate dielectric film are etched using the resist as a mask, to form a gate electrode106aand a gate line106b.

Referring toFIGS. 14(a) and14(b), the silicon nitride film110on the top of the pillar-shaped silicon layer, and the silicon nitride film-based sidewall112, are removed by wet etching.

Referring toFIGS. 15(a) and15(b), an impurity, such as P or As, is introduced into a top portion of the pillar-shaped silicon layer102, for example, by ion implantation, to form an N+source diffusion layer104therein.

Referring toFIGS. 16(a) and16(b), an interlayer dielectric film is formed, and a contact (107,108,109) is formed on each of the drain diffusion layer in the upper region of the silicon substrate, the source diffusion layer in the upper portion of the pillar-shaped silicon layer, and the gate line.

In the method according to the first embodiment, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed in the above manner. This makes it possible to achieve a gate forming process having the following features.

A first feature is that the process is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second feature is that the process is less vulnerable to a deviation in exposure alignment during gate line formation. Thus, the use of the method according to the first embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

A third feature is that the step of flattening a top surface of a gate conductive film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. Thus, the use of the method according to the first embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

As described above, the method according to the first embodiment can form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness, and adjust a film thickness of the gate electrode to be formed around the pillar-shaped silicon layer, based on a formed film thickness of a gate conductive film. Thus, two pillar-shaped silicon layers each having a gate electrode to be applied with a different potential can be arranged side-by-side with a relatively small distance therebetween, to reduce a circuit area. In cases where the gate conductive film is formed to have a relatively small film thickness, a resistance value thereof becomes higher. Thus, in the first embodiment, the gate conductive film is preferably comprised of a metal film.

Second Embodiments

A second embodiment of the present invention shows a gate forming process capable of reducing the number of steps and further increasing a process margin, as compared with the gate forming process in the first embodiment.

FIGS. 17(a) and17(b) are, respectively, a top plan view and a sectional view of an NMOS SGT formed by a SGT production method according to the second embodiment. With reference toFIGS. 17(a) and17(b), the NMOS SGT formed by the SGT production method according to the second embodiment will be described below.

A pillar-shaped silicon layer202is formed on a silicon substrate201, and a gate dielectric film205and a gate electrode206aare formed around the pillar-shaped silicon layer202. An N+drain diffusion layer203is formed beneath the pillar-shaped silicon layer202, and an N+source diffusion layer204is formed in an upper portion of the pillar-shaped silicon layer202. A contact207, a contact208, and a contact209, are formed on the N+drain diffusion layer203, the N+source diffusion layer204, and a gate line206bextending from the gate electrode206a, respectively.

In the second embodiment, the gate electrode206aand the gate line206bare formed to be at the same height position. Specifically, the gate electrode is integrally formed with the gate line in such a manner that an entire area of a top surface of the integrated combination of the gate electrode and the gate line becomes parallel to the substrate.

Under conditions that the N+source diffusion layer204is connected to a GND potential, and the N+drain diffusion layer203is connected to a power supply potential Vcc, a potential ranging from zero to Vcc is applied to the gate electrode206ato allow the SGT to operate as a transistor.

With reference toFIGS. 18(a) to27(b), one example of the SGT production method according to the second embodiment will be described below. InFIGS. 18(a) to27(b), the figure suffixed by (a) is a top plan view, and the figure suffixed by (b) is a sectional view taken along the line A-A′.

In the second embodiment, the step of forming a gate dielectric film and any step therebefore are the same as those in the first embodiment. Thus, the following description will be started from the step of forming a gate conductive film.

Referring toFIGS. 18(a) and18(b), a gate conductive film206is formed by CVD or ALD, to allow a pillar-shaped silicon layer202to be buried therein.

Referring toFIGS. 19(a) and19(b), the gate conductive film206is polished by CMP, to flatten a top of the gate conductive film. Through the flattening of the top of the gate conductive film by CMP, a configuration of the gate conductive film is improved to facilitate control of a gate length. During the CMP, a silicon nitride film210on a top of a pillar-shaped silicon layer202is used as a CMP stopper. The use of the silicon nitride film210as a CMP stopper makes it possible to control an amount of CMP with high repeatability.

Referring toFIGS. 20(a) and20(b), the gate conductive film206is etched back to fix a gate length.

Referring toFIGS. 21(a) and21(b), a silicon nitride film212ais formed by a film thickness required for an after-mentioned gate electrode. Subsequently, as shown inFIGS. 22(a) and22(b), the silicon nitride film212ais etched back to form a silicon nitride film-based sidewall212. In the second embodiment, a film thickness of the gate electrode is determined by a film thickness of the silicon nitride film-based sidewall212. Thus, a final film thickness of the silicon nitride film-based sidewall212is controlled to become equal to a desired film thickness of the gate electrode, by adjusting a formed film thickness of the silicon nitride film212aand then finely adjusting the formed film thickness based on an amount of the etch-back.

Referring toFIGS. 23(a) and23(b), a resist or a multilayer resist is applied, and a gate line pattern is formed with a resist213by lithography.

Referring toFIGS. 24(a) and24(b), the gate conductive film and the gate dielectric film are etched using the resist as a mask, to form a gate electrode206aand a gate line206b.

Referring toFIGS. 25(a) and25(b), the silicon nitride film210on the top of the pillar-shaped silicon layer, and the silicon nitride film-based sidewall212, are removed by wet etching.

Referring toFIGS. 26(a) and26(b), an impurity, such as P or As, is introduced into a top portion of the pillar-shaped silicon layer202, for example, by ion implantation, to form an N+source diffusion layer204therein.

Referring toFIGS. 27(a) and27(b), an interlayer dielectric film is formed, and a contact (207,208,209) is formed on each of the drain diffusion layer in the upper region of the silicon substrate, the source diffusion layer in the upper portion of the pillar-shaped silicon layer, and the gate line.

In the method according to the second embodiment, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed in the above manner. This makes it possible to achieve a gate forming process having the following features.

A first feature is that the process is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second feature is that the process is less vulnerable to a deviation in exposure alignment during gate line formation. Thus, the use of the method according to the second embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

A third feature is that the step of flattening a top surface of a gate conductive film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. Thus, the use of the method according to the second embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming the gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

As described above, the method according to the second embodiment can form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. In the first embodiment, a film thickness of a gate electrode is controlled based on a formed film thickness of a gate conductive film. Differently, in the second embodiment, the film thickness of the gate electrode can be controlled based on a film thickness of the silicon nitride film-based sidewall212. Further, in the second embodiment, the gate line206bhas a relatively large film thickness as compared with that of the gate line in the first embodiment. Thus, the gate conductive film is not limited to a metal film, but may be made of a material having relatively high electrical resistance, such as polysilicon.

In the first embodiment, the silicon nitride film-based sidewall112must be formed to have a thickness approximately equal to that of the gate conductive film106. Thus, if the sidewall112is excessively thicker or thinner than the gate conductive film106, a problem is likely to occur. Specifically, as shown inFIGS. 28(a) to28(d), in the case where the sidewall112is excessively thicker than the gate conductive film106, a silicon nitride film-based sidewall112having a film thickness greater than that of a gate conductive film106is formed (FIG. 28(a)), and a silicon oxide film111is removed by wet etching (FIG. 28(b)), whereafter a gate line pattern is formed by lithography (FIG. 28(c)), and a gate electrode106aand a gate line106bare formed by etching. In this case, the gate electrode has a protrusion106cformed in a lower end thereof corresponding to a region which has not been covered by a resist113. If the protrusion becomes significantly large, such a defective structure is likely to become cause a problem, such as a short-circuiting between the protrusion106cof the gate electrode and an adjacent contact. As shown inFIGS. 29(a) to29(d), in the case where the sidewall112is excessively thinner than the gate conductive film106, a silicon nitride film-based sidewall112having a film thickness less than that of a gate conductive film106is formed (FIG. 29(a)), and a silicon oxide film111is removed by wet etching (FIG. 29(b)), whereafter a gate line pattern is formed by lithography (FIG. 29(c)), and a gate electrode106aand a gate line106bare formed by etching. In this case, a part of a top of the gate conductive film is not covered by a resist113, and thereby subjected to etching. Thus, a film thickness of the gate electrode is reduced. If the reduction in film thickness becomes significant, such a defective structure is likely to cause a problem, such as etching damage on a gate dielectric film, or a change in transistor characteristics. Differently, in the second embodiment, the gate electrode is formed to have a desired film thickness, in a self-alignment manner based on the silicon nitride film-based sidewall112having a film thickness equal to the desired film thickness of the gate electrode. This makes it possible to eliminate a risk of occurrence of the above problems, and further increase a process margin in the gate forming process, as compared with that in the first embodiment.

Third Embodiment

A NMOS SGT formed by a SGT production method according to a third embodiment of the present invention is different from the NMOS SGT in the second embodiment, in that a gate electrode and a gate line extending from the gate electrode are formed in a layered structure which comprises a thin metal film and a polysilicon layer. In a gate forming process in the third embodiment, the thin metal film is formed to be in contact with a gate dielectric film so as to suppress depletion of the gate electrode, and the polysilicon layer is formed to define respective top surfaces of the gate electrode and the gate line, so as to allow the SGT to be produced in the same production line as that for a transistor having a conventional polysilicon gate.

FIGS. 30(a) and30(b) are, respectively, a top plan view and a sectional view of the NMOS SGT formed by the SGT production method according to the third embodiment. With reference toFIGS. 30(a) and30(b), the NMOS SGT formed by the method according to the third embodiment will be described below.

A pillar-shaped silicon layer302is formed on a silicon substrate301, and a gate dielectric film305and a gate electrode306aare formed around the pillar-shaped silicon layer302. The gate electrode has a layered structure which comprises a thin metal film314having a film thickness of about 1 to 10 nm, and a polysilicon layer306acovering the metal film. An N+drain diffusion layer303is formed beneath the pillar-shaped silicon layer302, and an N+source diffusion layer304is formed in an upper portion of the pillar-shaped silicon layer302. A contact307, a contact308, and a contact309, are formed on the N+drain diffusion layer303, the N+source diffusion layer304, and a gate line306bextending from the gate electrode306a, respectively.

In the third embodiment, the gate electrode306aand the gate line306bare formed to be at the same height position, in the same manner as that in the second embodiment. Specifically, the gate electrode is integrally formed with the gate line in such a manner that an entire area of a top surface of the integrated combination of the gate electrode and the gate line becomes parallel to the substrate.

Under conditions that the N+source diffusion layer304is connected to a GND potential, and the N+drain diffusion layer303is connected to a power supply potential Vcc, a potential ranging from zero to Vcc is applied to the gate electrode306ato allow the SGT to operate as a transistor.

With reference toFIGS. 31(a) to41(b), one example of the SGT production method according to the third embodiment will be described below. InFIGS. 31(a) to41(b), the figure suffixed by (a) is a top plan view, and the figure suffixed by (b) is a sectional view taken along the line A-A′.

In the third embodiment, the step of forming a gate dielectric film and any step therebefore are the same as those in the second embodiment. Thus, the following description will be started from the step of forming a thin metal film and a polysilicon layer.

Referring toFIGS. 31(a) and31(b), after forming a gate dielectric film305, a thin metal film314is formed to have a film thickness of about 1 to 10 nm, and then a polysilicon layer306is formed to allow a pillar-shaped silicon layer302to be buried therein.

Referring toFIGS. 32(a) and32(b), the polysilicon layer306, and respective portions of the thin metal film314and the gate dielectric film305above the pillar-shaped silicon layer, are polished by CMP, to flatten respective top surfaces of the polysilicon layer306and the thin metal film314. Through the flattening of respective tops of the polysilicon layer306and the thin metal film314by CMP, respective configurations of the polysilicon layer306and the thin metal film314are improved to facilitate control of a gate length. During the CMP, a silicon nitride film310on a top of the pillar-shaped silicon layer is used as a CMP stopper. The use of the silicon nitride film310as a CMP stopper makes it possible to control an amount of CMP with high repeatability.

Referring toFIGS. 33(a) and33(b), the polysilicon layer306and the thin metal film314are etched back to fix a gate length.

Referring toFIGS. 34(a) and34(b), a silicon nitride film312ais formed by a film thickness required for an after-mentioned gate electrode. Subsequently, as shown inFIGS. 35(a) and35(b), the silicon nitride film312ais etched back to form a silicon nitride film-based sidewall312. In the third embodiment, a film thickness of the gate electrode is determined by a film thickness of the silicon nitride film-based sidewall312. Thus, a final film thickness of the silicon nitride film-based sidewall312is controlled to become equal to a desired film thickness of the gate electrode, by adjusting a formed film thickness of the silicon nitride film312aand then finely adjusting the formed film thickness based on an amount of the etch-back.

Referring toFIGS. 36(a) and36(b), a resist or a multilayer resist is applied, and a gate line pattern is formed with a resist313by lithography.

Referring toFIGS. 37(a) and37(b), the polysilicon layer, the thin metal film and the gate dielectric film are etched using the resist as a mask, to form a gate electrode306aand a gate line306b.

Referring toFIGS. 38(a) and38(b), the silicon nitride film310on the top of the pillar-shaped silicon layer, and the silicon nitride film-based sidewall312, are removed by wet etching.

Referring toFIGS. 39(a) and39(b), a silicon nitride film is formed and then etched back to form a silicon nitride film315. The silicon nitride film315is formed to cover the thin metal film314of the gate electrode to keep a top surface of the thin metal film314from being exposed. This makes it possible to produce an intended SGT in the same production line as that for a transistor having a conventional polysilicon gate.

Referring toFIGS. 40(a) and40(b), an impurity, such as P or As, is introduced into a top portion of the pillar-shaped silicon layer302, for example, by ion implantation, to form an N+source diffusion layer304therein.

Referring toFIGS. 41(a) and41(b), an interlayer dielectric film is formed, and a contact (307,308,309) is formed on each of the drain diffusion layer in the upper region of the silicon substrate, the source diffusion layer in the upper portion of the pillar-shaped silicon layer, and the gate line.

In the method according to the third embodiment, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed in the above manner. This makes it possible to achieve a gate forming process having the following features.

A first feature is that the process is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second feature is that the process is less vulnerable to a deviation in exposure alignment during gate line formation. Thus, the use of the method according to the third embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

A third feature is that the step of flattening respective top surfaces of a polysilicon layer and a thin metal film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. Thus, the use of the method according to the third embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming the gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

As described above, the method according to the third embodiment can form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness, and control a film thickness of the gate electrode based on a film thickness of the silicon nitride film-based sidewall312, as with the second embodiment.

In the third embodiment, a gate is formed in a layered structure which comprises the thin metal film and the polysilicon layer, which is capable of suppressing depletion of the gate electrode, and allowing an intended SGT to be produced in the same production line as that for a transistor having a conventional polysilicon gate.

In the first embodiment, if the silicon nitride film-based sidewall has a film thickness largely different from that of the gate conductive film, the difference is likely to cause the problems as described in connection with the second embodiment. Differently, the gate forming process in the third embodiment can form a gate electrode to have a desired film thickness, in a self-alignment manner according to a film thickness of the silicon nitride film-based sidewall312, as with the second embodiment. This makes it possible to eliminate a risk of occurrence of the above problems, and further increase a process margin in the gate forming process, as compared with that in the first embodiment.

Fourth Embodiment

A fourth embodiment of the present invention shows a method of producing a CMOS inverter using the same gate forming process as that in the first embodiment. Thus, the method according to the fourth embodiment can be employed to obtain the same advantageous effects as those in the first embodiment.

FIG. 42is an equivalent circuit diagram of a CMOS inverter formed by the method according to the fourth embodiment. A circuit operation of the CMOS inverter will be described below. An input signal Vin1is applied to a gate of an NMOS Qn1and a gate of a PMOS Qp1. When the Vin1is “1”, the NMOS Qn1is placed in an ON state, and the PMOS Qp1is placed in an OFF state, so that an output signal Vout1becomes “0”. Reversely, when the Vin1is “0”, the NMOS Qn1is placed in an OFF state, and the PMOS Qp1is placed in an ON state, so that the Vout1becomes “1”. As above, the CMOS inverter is operable to allow the output signal Vout1to have a value opposite to that of the input signal Vin1.

FIG. 43is a top plan view of the CMOS inverter formed by the method according to the fourth embodiment.FIGS. 44(a) and44(b) are sectional views taken along the cutting-plane line A-A′ and the cutting-plane line B-B′ inFIG. 43, respectively. With reference toFIGS. 43,44(a) and44(b), a structure of the CMOS inverter will be described.

A P-well402and an N-well403are formed in an upper region of a silicon substrate401. A pillar-shaped silicon layer407forming an NMOS (NMOS-forming pillar-shaped silicon layer407) and a pillar-shaped silicon layer408forming a PMOS (PMOS-forming pillar-shaped silicon layer408) are formed on a surface of the silicon substrate, specifically on respective ones of the P-well region and the N-well region. A gate dielectric film409and a gate electrode (410a,410b) are formed to surround the pillar-shaped silicon layers. Further, the gate electrodes410a,410bare connected to each other through a gate line410cextending therefrom.

An N+drain diffusion layer404is formed beneath the NMOS-forming pillar-shaped silicon layer407, and an N+source diffusion layer411is formed in an upper portion of the NMOS-forming pillar-shaped silicon layer407. A P+drain diffusion layer405is formed beneath the PMOS-forming pillar-shaped silicon layer408, and a P+source diffusion layer412is formed in an upper portion of the PMOS-forming pillar-shaped silicon layer408. Each of the N+drain diffusion layer404and the P+drain diffusion layer405formed beneath respective ones of the pillar-shaped silicon layers407,408is connected to the output terminal Vout1via a contact (416a,416b). The N+source diffusion layer411formed in the upper portion of the NMOS-forming pillar-shaped silicon layer407is connected to a ground potential Vss1via a contact414, and the P+source diffusion layer412formed in the upper portion of the PMOS-forming pillar-shaped silicon layer408is connected to a power supply potential Vcc1via a contact415. Further, the gate line410cconnecting between the gate electrodes for the PMOS and the NMOS is connected to the input terminal Vin1via a contact413. In this manner, the CMOS inverter is formed.

With reference toFIGS. 45(a) to63(b), one example of the SGT production method according to the fourth embodiment will be described below. InFIGS. 45(a) to63(b), the figure suffixed by (a) is a top plan view, and the figure suffixed by (b) is a sectional view taken along the line A-A′.

Referring toFIGS. 45(a) and45(b), a silicon nitride film417serving as a hard mask is formed on a silicon substrate401to have a film thickness of about 50 to 150 nm.

Referring toFIGS. 46(a) and46(b), the hard mask417and the silicon substrate401are etched to form an element isolation region406.

Referring toFIGS. 47(a) and47(b), a silicon oxide film422is filled in the element isolation region406.

Referring toFIGS. 48(a) and48(b), a portion of the silicon oxide film422above the hard mask417is polished and flattened by CMP.

Referring toFIGS. 49(a) and49(b), the silicon oxide film422filled in the element isolation region406is etched back in such a manner that a height position of the silicon oxide film422is adjusted to become equal to that of a drain diffusion layer which is to be formed in a subsequent step.

Referring toFIGS. 50(a) and50(b), the hard mask417and the silicon substrate401are etched to form a pillar-shaped silicon layer (407,408).

Referring toFIGS. 51(a) and51(b), impurities are introduced into a surface of the silicon substrate, for example, by ion implantation, to form an N+drain diffusion layer404and a P+drain diffusion layer405therein. During this step, the silicon nitride film417on a top of each of the pillar-shaped silicon layers functions as a stopper for preventing the impurity from being injected into the top of the pillar-shaped silicon layer.

Referring toFIGS. 52(a) and52(b), a gate dielectric film409and a gate conductive film410are formed by CVD or ALD. The gate conductive film410is formed to have a film thickness of about 10 to 100 nm.

Referring toFIGS. 53(a) and53(b), a silicon oxide film418is formed to allow the pillar-shaped silicon layers to be buried therein.

Referring toFIGS. 54(a) and54(b), the silicon oxide film418, and respective portions of the gate conductive film and the gate dielectric film above the pillar-shaped silicon layer, are polished by CMP, to flatten a top surface of the gate conductive film. Through the flattening of a top of the gate conductive film by CMP, a configuration of the gate conductive film is improved to facilitate control of a gate length. During the CMP, the silicon nitride film417on the top of the pillar-shaped silicon layer is used as a CMP stopper. The use of the silicon nitride film417as a CMP stopper makes it possible to control an amount of CMP with high repeatability.

Referring toFIGS. 55(a) and55(b), the gate conductive film410and the silicon oxide film418are etched back, wherein the gate conductive film410is etched to fix a gate length. Preferably, etching conditions to be used in this step are set to allow the gate conductive film410and the silicon oxide film418to be etched at the same rate, and at a higher selectivity ratio relative to the silicon nitride film417. The etching of the gate conductive film410and the silicon oxide film418at the same rate makes it possible to suppress occurrence of a step between respective top surfaces of the two films, which improves a configuration of a silicon nitride film-based sidewall112to be formed in a next step.

Referring toFIGS. 56(a) and56(b), a silicon nitride film419ais formed by a film thickness required for the gate conductive film410. Subsequently, as shown inFIGS. 57(a) and57(b), the silicon nitride film419ais etched back to form a silicon nitride film-based sidewall419. In this step, a film thickness of the silicon nitride film-based sidewall419is controlled to become equal to that of the gate conductive film410, by adjusting a formed film thickness of the silicon nitride film419a, and then finely adjusting the formed film thickness based on an amount of the etch-back. A portion of the gate conductive film covered by the silicon nitride film-based sidewall419will be protected during etching for forming a gate line in a subsequent step. This makes it possible to form the gate electrode in a self-alignment manner and with a desired film thickness, so as to reduce an occupancy area.

Referring toFIGS. 58(a) and58(b), the silicon oxide film418remaining on the gate conductive film is removed by wet etching.

Referring toFIGS. 59(a) and59(b), a resist or a multilayer resist is applied, and a gate line pattern is formed with a resist420by lithography.

Referring toFIGS. 60(a) and60(b), the gate conductive film and the gate dielectric film are etched using the resist as a mask, to form a gate electrode (410a,410b) and a gate line410c.

Referring toFIGS. 61(a) and61(b), the silicon nitride film417on the top of the pillar-shaped silicon layer, and the silicon nitride film-based sidewall419, are removed by wet etching.

Referring toFIGS. 62(a) and62(b), impurities are introduced into respective top portions of the pillar-shaped silicon layers407,408, for example, by ion implantation, to form an N+source diffusion layer411and a P+source diffusion layer412therein.

Referring toFIGS. 63(a) and63(b), an interlayer dielectric film is formed, and a contact (413,414,415,416a,416b) is formed on each of the gate line, the source diffusion layers in the upper portions of the pillar-shaped silicon layers, and the drain diffusion layers in the upper region of the silicon substrate.

In the method according to the fourth embodiment, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed in the above manner. This makes it possible to achieve a gate forming process having the following features.

A first feature is that the process is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second feature is that the process is less vulnerable to a deviation in exposure alignment during gate line formation. Thus, the use of the method according to the fourth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

A third feature is that the step of flattening a top surface of a gate conductive film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. Thus, the use of the method according to the fourth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming the gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

As described above, the method according to the fourth embodiment can form a gate electrode around a pillar-shaped silicon layer in a self-alignment mariner and with a desired film thickness, and adjust a film thickness of the gate electrode to be formed around the pillar-shaped silicon layer, based on a formed film thickness of a gate conductive film. Thus, a distance between a pillar-shaped silicon layer (410a,410b) and a contact (416a,416b) on a drain diffusion layer can be reduced so that an area of a circuit, such as an inverter circuit, can be reduced. In cases where the gate conductive film is formed to have a relatively small film thickness, a resistance value thereof becomes higher. Thus, in the fourth embodiment, the gate conductive film is preferably comprised of a metal film.

Although the SGT production method according to the fourth embodiment has been described based on one example where it is applied to a CMOS inverter, it is understood that the present invention may be applied to any suitable circuit other than the CMOS inverter, in just the same manner.

Fifth Embodiment

A fifth embodiment of the present invention shows a method of producing a CMOS inverter using the same gate forming process as that in the second embodiment. Thus, the method according to the fifth embodiment can be employed to obtain the same advantageous effects as those in the second embodiment.

FIG. 64is an equivalent circuit diagram of a CMOS inverter formed by the method according to the fifth embodiment. A circuit operation of the CMOS inverter will be described below. An input signal Vin2is applied to a gate of an NMOS Qn2and a gate of a PMOS Qp2. When the Vin2is “1”, the NMOS Qn2is placed in an ON state, and the PMOS Qp2is placed in an OFF state, so that an output signal Vout2becomes “0”. Reversely, when the Vin2is “0”, the NMOS Qn2is placed in an OFF state, and the PMOS Qp2is placed in an ON state, so that the Vout2becomes “1”. As above, the CMOS inverter is operable to allow the output signal Vout2to have a value opposite to that of the input signal Vin2.

FIG. 65is a top plan view of the CMOS inverter formed by the method according to the fifth embodiment.FIGS. 66(a) and66(b) are sectional views taken along the cutting-plane line A-A′ and the cutting-plane line B-B′ inFIG. 65, respectively. With reference toFIGS. 65,66(a) and66(b), a structure of the CMOS inverter will be described.

A P-well502and an N-well503are formed in an upper region of a silicon substrate501. A pillar-shaped silicon layer507forming an NMOS (NMOS-forming pillar-shaped silicon layer507) and a pillar-shaped silicon layer508forming a PMOS (PMOS-forming pillar-shaped silicon layer508) are formed on a surface of the silicon substrate, specifically on respective ones of the P-well region and the N-well region. A gate dielectric film509and a gate electrode (510a,510b) are formed to surround the pillar-shaped silicon layers. Further, the gate electrodes510a,510bare connected to each other through a gate line510cextending therefrom, and the gate electrode (510a,510b) and the gate line510care formed to be at the same height position. An N+drain diffusion layer504is formed beneath the NMOS-forming pillar-shaped silicon layer507, and an N+source diffusion layer511is formed in an upper portion of the NMOS-forming pillar-shaped silicon layer507. A P+drain diffusion layer505is formed beneath the PMOS-forming pillar-shaped silicon layer508, and a P+source diffusion layer512is formed in an upper portion of the PMOS-forming pillar-shaped silicon layer508.

Each of the N+drain diffusion layer504and the P+drain diffusion layer505formed beneath respective ones of the pillar-shaped silicon layers507,508is connected to the output terminal Vout2via a contact (516a,516b). The N+source diffusion layer511formed in the upper portion of the NMOS-forming pillar-shaped silicon layer507is connected to a ground potential Vss2via a contact514, and the P+source diffusion layer512formed in the upper portion of the PMOS-forming pillar-shaped silicon layer508is connected to a power supply potential Vcc2via a contact515. Further, the gate line510cconnecting between the gate electrodes for the PMOS and the NMOS is connected to the input terminal Vin2via a contact513. In this manner, the CMOS inverter is formed.

With reference toFIGS. 67(a) to76(b), one example of the SGT production method according to the fifth embodiment will be described below. InFIGS. 67(a) to76(b), the figure suffixed by (a) is a top plan view, and the figure suffixed by (b) is a sectional view taken along the line A-A′. In the fifth embodiment, any step before the step of forming a gate dielectric film is the same as those in the fourth embodiment. Thus, the following description will be started from the step of forming a gate conductive film.

Referring toFIGS. 67(a) and67(b), a gate dielectric film509and a gate conductive film510are formed by CVD or ALD, wherein the gate conductive film510is formed to allow a pillar-shaped silicon layer (507,508) to be buried therein.

Referring toFIGS. 68(a) and68(b), the gate conductive film510is polished by CMP, to flatten a top surface of the gate conductive film. Through the flattening of a top of the gate conductive film by CMP, a configuration of the gate conductive film is improved to facilitate control of a gate length. During the CMP, a silicon nitride film517on a top of a pillar-shaped silicon layer is used as a CMP stopper. The use of the silicon nitride film517as a CMP stopper makes it possible to control an amount of CMP with high repeatability.

Referring toFIGS. 69(a) and69(b), the gate conductive film510is etched back to fix a gate length.

Referring toFIGS. 70(a) and70(b), a silicon nitride film519ais formed by a film thickness required for an after-mentioned gate electrode. Subsequently, as shown inFIGS. 71(a) and71(b), the silicon nitride film519ais etched back to form a silicon nitride film-based sidewall519. In the fifth embodiment, a film thickness of the gate electrode is determined by a film thickness of the silicon nitride film-based sidewall519. Thus, a final film thickness of the silicon nitride film-based sidewall is controlled to become equal to a desired film thickness of the gate electrode, by adjusting a formed film thickness of the silicon nitride film519aand then finely adjusting the formed film thickness based on an amount of the etch-back.

Referring toFIGS. 72(a) and72(b), a resist or a multilayer resist is applied, and a gate line pattern is formed with a resist520by lithography.

Referring toFIGS. 73(a) and73(b), the gate conductive film and the gate dielectric film are etched using the resist as a mask, to form a gate electrode (510a,510b) and a gate line510c.

Referring toFIGS. 74(a) and74(b), the silicon nitride film517on the top of the pillar-shaped silicon layer, and the silicon nitride film-based sidewall519, are removed by wet etching.

Referring toFIGS. 75(a) and75(b), impurities are is introduced into respective top portions of the pillar-shaped silicon layers507,508, for example, by ion implantation, to form an N+source diffusion layer511and P+source diffusion layer512therein.

Referring toFIGS. 76(a) and76(b), an interlayer dielectric film is formed, and a contact (513,514,515,516a,516b) is formed on each of the gate line, the source diffusion layers in the upper portions of the pillar-shaped silicon layers and the drain diffusion layers in the upper region of the silicon substrate.

In the method according to the fifth embodiment, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed in the above manner. This makes it possible to achieve a gate forming process having the following features.

A first feature is that the process is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second feature is that the process is less vulnerable to a deviation in exposure alignment during gate line formation. Thus, the use of the method according to the fifth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

A third feature is that the step of flattening a top surface of a gate conductive film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. Thus, the use of the method according to the fifth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming the gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

As described above, the method according to the fifth embodiment can form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. In the fourth embodiment, a film thickness of a gate electrode is controlled based on a formed film thickness of a gate conductive film. Differently, in the fifth embodiment, the film thickness of the gate electrode can be controlled based on a film thickness of the silicon nitride film-based sidewall519. Further, in the fifth embodiment, the gate line510chas a relatively large film thickness as compared with that of the gate line in the fourth embodiment. Thus, the gate conductive film is not limited to a metal film, but may be made of a material having relatively high electrical resistance, such as polysilicon.

In the fourth embodiment, if the silicon nitride film-based sidewall has a film thickness largely different from that of the gate conductive film, the difference is likely to cause the problems as described in connection with the second embodiment. Differently, the gate forming process in the fifth embodiment can form a gate electrode to have a desired film thickness, in a self-alignment manner according to a film thickness of the silicon nitride film-based sidewall519, as with the second embodiment. This makes it possible to eliminate a risk of occurrence of the above problems, and further increase a process margin in the gate forming process, as compared with that in the fourth embodiment.

Although the SGT production method according to the fifth embodiment has been described based on one example where it is applied to a CMOS inverter, it is understood that the present invention may be applied to any suitable circuit other than the CMOS inverter, in just the same manner.

Sixth Embodiment

A sixth embodiment of the present invention shows a method of producing a CMOS inverter using the same gate forming process as that in the third embodiment. Thus, the method according to the sixth embodiment can be employed to obtain the same advantageous effects as those in the third embodiment.

FIG. 77is an equivalent circuit diagram of a CMOS inverter formed by the method according to the sixth embodiment. A circuit operation of the CMOS inverter will be described below. An input signal Vin3is applied to a gate of an NMOS Qn3and a gate of a PMOS Qp3. When the Vin3is “1”, the NMOS Qn3is placed in an ON state, and the PMOS Qp3is placed in an OFF state, so that an output signal Vout3becomes “0”. Reversely, when the Vin3is “0”, the NMOS Qn3is placed in an OFF state, and the PMOS Qp3is placed in an ON state, so that the Vout3becomes “1”. As above, the CMOS inverter is operable to allow the output signal Vout3to have a value opposite to that of the input signal Vin3.

FIG. 78is a top plan view of the CMOS inverter formed by the method according to the sixth embodiment.FIGS. 79(a) and79(b) are sectional views taken along the cutting-plane line A-A′ and the cutting-plane line B-B′ inFIG. 78, respectively. With reference toFIGS. 78,79(a) and79(b), a structure of the CMOS inverter will be described.

A P-well602and an N-well603are formed in an upper region of a silicon substrate601. A pillar-shaped silicon layer607forming an NMOS (NMOS-forming pillar-shaped silicon layer607) and a pillar-shaped silicon layer608forming a PMOS (PMOS-forming pillar-shaped silicon layer608) are formed on a surface of the silicon substrate, specifically on respective ones of the P-well region and the N-well region. A gate dielectric film609and a gate electrode (610a,610b) are formed to surround the pillar-shaped silicon layers. Each of the gate electrodes is formed in a layered structure which comprises a polysilicon layer defining a top surface thereof, and a thin metal film623in contact with the gate dielectric film. Further, the gate electrodes610a,610bare connected to each other through a gate line610cextending therefrom, and the gate electrode (610a,610b) and the gate line610care formed to be at the same height position. An N+drain diffusion layer604is formed beneath the NMOS-forming pillar-shaped silicon layer607, and an N+source diffusion layer611is formed in an upper portion of the NMOS-forming pillar-shaped silicon layer607. A P+drain diffusion layer605is formed beneath the PMOS-forming pillar-shaped silicon layer608, and a P+source diffusion layer612is formed in an upper portion of the PMOS-forming pillar-shaped silicon layer608.

Each of the N+drain diffusion layer604and the P+drain diffusion layer605formed beneath respective ones of the pillar-shaped silicon layers607,608is connected to the output terminal Vout3via a contact (616a,616b). The N+source diffusion layer611formed in the upper portion of the NMOS-forming pillar-shaped silicon layer607is connected to a ground potential Vss3via a contact614, and the P+source diffusion layer612formed in the upper portion of the PMOS-forming pillar-shaped silicon layer608is connected to a power supply potential Vcc3via a contact615. Further, the gate line610cconnecting between the gate electrodes for the PMOS and the NMOS is connected to the input terminal Vin3via a contact613. In this manner, the CMOS inverter is formed.

With reference toFIGS. 80(a) to90(b), one example of the SGT production method according to the sixth embodiment will be described below. InFIGS. 80(a) to90(b), the figure suffixed by (a) is a top plan view, and the figure suffixed by (b) is a sectional view taken along the line A-A′. In the sixth embodiment, the step of forming a gate dielectric film and any step therebefore are the same as those in the fourth embodiment. Thus, the following description will be started from the step of forming a thin metal film and a polysilicon layer.

Referring toFIGS. 80(a) and80(b), after forming a gate dielectric film609, a thin metal film623is formed to have a film thickness of about 1 to 10 nm, and then a polysilicon layer610is formed to allow a pillar-shaped silicon layer (607,608) to be buried therein.

Referring toFIGS. 81(a) and81(b), the polysilicon layer610, and respective portions of the thin metal film623and the gate dielectric film609above the pillar-shaped silicon layer, are polished by CMP, to flatten respective top surfaces of the polysilicon layer610and the thin metal film623. Through the flattening of respective tops of the polysilicon layer610and the thin metal film623by CMP, respective configurations of the polysilicon layer610and the thin metal film623are improved to facilitate control of a gate length. During the CMP, a silicon nitride film617on a top of the pillar-shaped silicon layer is used as a CMP stopper. The use of the silicon nitride film617as a CMP stopper makes it possible to control an amount of CMP with high repeatability.

Referring toFIGS. 82(a) and82(b), the polysilicon layer610and the thin metal film623are etched back to fix a gate length.

Referring toFIGS. 83(a) and83(b), a silicon nitride film619ais formed by a film thickness required for an after-mentioned gate electrode. Subsequently, as shown inFIGS. 84(a) and84(b), the silicon nitride film619ais etched back to form a silicon nitride film-based sidewall619. In the sixth embodiment, a film thickness of the gate electrode is determined by a film thickness of the silicon nitride film-based sidewall619. Thus, a final film thickness of the silicon nitride film-based sidewall is controlled to become equal to a desired film thickness of the gate electrode, by adjusting a formed film thickness of the silicon nitride film312aand then finely adjusting the formed film thickness based on an amount of the etch-back.

Referring toFIGS. 85(a) and85(b), a resist or a multilayer resist is applied, and a gate line pattern is formed with a resist620by lithography.

Referring toFIGS. 86(a) and86(b), the polysilicon layer, the thin metal film and the gate dielectric film are etched using the resist as a mask, to form a gate electrode (610a,610b) and a gate line610c.

Referring toFIGS. 87(a) and87(b), the silicon nitride film617on the top of the pillar-shaped silicon layer, and the silicon nitride film-based sidewall619, are removed by wet etching.

Referring toFIGS. 88(a) and88(b), a silicon nitride film is formed and then etched back to form a silicon nitride film624. The silicon nitride film624is formed to cover the thin metal film623of the gate electrode to keep a top surface of the thin metal film623from being exposed. This makes it possible to produce an intended SGT in the same production line as that for a transistor having a conventional polysilicon gate.

Referring toFIGS. 89(a) and89(b), impurities are introduced into respective top portions of the pillar-shaped silicon layers607,608, for example, by ion implantation, to form an N+source diffusion layer611and a P+source diffusion layer612therein.

Referring toFIGS. 90(a) and90(b), an interlayer dielectric film is formed, and a contact (613,614,615,616a,616b) is formed on each of the gate line, the source diffusion layers in the upper portions of the pillar-shaped silicon layers and the drain diffusion layers in the upper region of the silicon substrate.

In the method according to the sixth embodiment, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed in the above manner. This makes it possible to achieve a gate forming process having the following features.

A first feature is that the process is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second feature is that the process is less vulnerable to a deviation in exposure alignment during gate line formation. Thus, the use of the method according to the sixth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

A third feature is that the step of flattening respective top surfaces of a polysilicon layer and a thin metal film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. Thus, the use of the method according to the sixth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming the gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

As described above, the method according to the sixth embodiment can form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness, and control a film thickness of the gate electrode based on a film thickness of the silicon nitride film-based sidewall619.

In the sixth embodiment, a gate is formed in a layered structure which comprises the thin metal film and the polysilicon layer, which is capable of suppressing depletion of the gate electrode, and allowing an intended SGT to be produced in the same production line as that for a transistor having a conventional polysilicon gate.

In the fourth embodiment, if the silicon nitride film-based sidewall has a film thickness largely different from that of the gate conductive film, the difference is likely to cause the problems as described in connection with the second embodiment. Differently, the gate forming process in the sixth embodiment can form a gate electrode to have a desired film thickness, in a self-alignment manner according to a film thickness of the silicon nitride film-based sidewall619. This makes it possible to eliminate a risk of occurrence of the above problems, and further increase a process margin in the gate forming process, as compared with that in the fourth embodiment.

Although the SGT production method according to the sixth embodiment has been described based on one example where it is applied to a CMOS inverter, it is understood that the present invention may be applied to any suitable circuit other than the CMOS inverter, in just the same manner.

Seventh Embodiment

A seventh embodiment of the present invention shows a method of producing an NMOS SGT on an SOI substrate (SOI NMOS SGT), using the same gate forming process as that in the first embodiment.

FIGS. 91(a) and91(b) are, respectively, a top plan view and a sectional view of the SOI NMOS SGT formed by the SGT production method according to the seventh embodiment. With reference toFIGS. 91(a) and91(b), the SOI NMOS SGT formed by the SGT production method according to the seventh embodiment will be described below.

A planar silicon layer701is formed on a buried oxide film layer700. A pillar-shaped silicon layer702is formed on the planar silicon layer701, and a gate dielectric film705and a gate electrode706aare formed around the pillar-shaped silicon layer702. An N+drain diffusion layer703is formed in the planar silicon layer701beneath the pillar-shaped silicon layer702, and an N+source diffusion layer704is formed in an upper portion of the pillar-shaped silicon layer702. A contact707, a contact708, and a contact709, are formed on the N+drain diffusion layer703, the N+source diffusion layer704, and a gate line706bextending from the gate electrode706a, respectively.

Under conditions that the N+source diffusion layer is connected to a GND potential, and the N+drain diffusion layer is connected to a power supply potential Vcc, a potential ranging from zero to Vcc is applied to the gate electrode to allow the SGT to operate as a transistor.

With reference toFIGS. 92(a) to107(b), one example of the SGT production method according to the seventh embodiment will be described below. InFIGS. 92(a) to107(b), the figure suffixed by (a) is a top plan view, and the figure suffixed by (b) is a sectional view taken along the line A-A′.

Referring toFIGS. 92(a) and92(b), a silicon nitride film710serving as a hard mask is formed on a silicon layer701aon a buried oxide film layer700in an SOI substrate, to have a film thickness of about 50 to 150 nm.

Referring toFIGS. 93(a) and93(b), the hard mask710and the silicon layer701aare etched to form a pillar-shaped silicon layer702. Through the etching, the pillar-shaped silicon layer702is formed to have a height dimension of about 30 to 300 nm, and a diameter of about 5 to 100 nm. Further, a planar silicon layer701is formed beneath the pillar-shaped silicon layer702to have a thickness of about 10 to 100 nm.

Referring toFIGS. 94(a) and94(b), the planar silicon layer701is formed in an isolated structure by etching.

Referring toFIGS. 95(a) and95(b), an impurity, such as P or As, is introduced into a top surface of planar silicon layer, for example, by ion implantation, to form an N+drain diffusion layer703therein. During this step, the silicon nitride film710on a top of the pillar-shaped silicon layer functions as a stopper for preventing the impurity from being injected into the top of the pillar-shaped silicon layer.

Referring toFIGS. 96(a) and96(b), a gate dielectric film705and a gate conductive film706are formed by CVD or ALD. The gate conductive film706is formed to have a film thickness of about 10 to 100 nm.

Referring toFIGS. 97(a) and97(b), a silicon oxide film711is formed to allow the pillar-shaped silicon layer to be buried therein.

Referring toFIGS. 98(a) and98(b), the silicon oxide film711, and respective portions of the gate conductive film and the gate dielectric film above the pillar-shaped silicon layer, are polished by CMP, to flatten a top surface of the gate conductive film. Through the flattening of a top of the gate conductive film by CMP, a configuration of the gate conductive film is improved to facilitate control of a gate length. During the CMP, the silicon nitride film710on the top of the pillar-shaped silicon layer is used as a CMP stopper. The use of the silicon nitride film710as a CMP stopper makes it possible to control an amount of CMP with high repeatability.

Referring toFIGS. 99(a) and99(b), the gate conductive film706and the silicon oxide film711are etched back, wherein the gate conductive film706is etched to fix a gate length. Preferably, etching conditions to be used in this step are set to allow the gate conductive film706and the silicon oxide film711to be etched at the same rate, and at a higher selectivity ratio relative to the silicon nitride film710. The etching of the gate conductive film706and the silicon oxide film711at the same rate makes it possible to suppress occurrence of a step between respective top surfaces of the two films, which improves a configuration of a silicon nitride film-based sidewall712to be formed in a next step.

Referring toFIGS. 100(a) and100(b), a silicon nitride film712ais formed by a film thickness required for the gate conductive film706. Subsequently, as shown inFIGS. 101(a) and101(b), the silicon nitride film712ais etched back to form a silicon nitride film-based sidewall712. In this step, a film thickness of the silicon nitride film-based sidewall712is controlled to become equal to that of the gate conductive film706, by adjusting a formed film thickness of the silicon nitride film712a, and then finely adjusting the formed film thickness based on an amount of the etch-back. A portion of the gate conductive film706covered by the silicon nitride film-based sidewall712will be protected during etching for forming a gate line in a subsequent step. This makes it possible to form the gate electrode in a self-alignment manner and with a desired film thickness, so as to reduce an occupancy area.

Referring toFIGS. 102(a) and102(b), the silicon oxide film711remaining on the gate conductive film is removed by wet etching.

Referring toFIGS. 103(a) and103(b), a resist or a multilayer resist is applied, and a gate line pattern is formed with a resist713by lithography.

Referring toFIGS. 104(a) and104(b), the gate conductive film and the gate dielectric film are etched using the resist as a mask, to form a gate electrode706aand a gate line706b.

Referring toFIGS. 105(a) and105(b), the silicon nitride film710on the top of the pillar-shaped silicon layer, and the silicon nitride film-based sidewall712, are removed by wet etching.

Referring toFIGS. 106(a) and106(b), an impurity, such as P or As, is introduced into a top portion of the pillar-shaped silicon layer702, for example, by ion implantation, to form an N+source diffusion layer704therein.

Referring toFIGS. 107(a) and107(b), an interlayer dielectric film is formed, and a contact (707,708,709) is formed on each of the drain diffusion layer in the planar silicon layer, the source diffusion layer in the upper portion of the pillar-shaped silicon layer, and the gate line.

In the method according to the seventh embodiment, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed in the above manner. This makes it possible to achieve a gate forming process having the following features.

A first feature is that the process is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second feature is that the process is less vulnerable to a deviation in exposure alignment during gate line formation. Thus, the use of the method according to the seventh embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

A third feature is that the step of flattening a top surface of a gate conductive film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. Thus, the use of the method according to the seventh embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

As described above, the method according to the seventh embodiment can form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness, and adjust a film thickness of the gate electrode to be formed around the pillar-shaped silicon layer, based on a formed film thickness of a gate conductive film. Thus, two pillar-shaped silicon layers each having a gate electrode to be applied with a different potential can be arranged side-by-side with a relatively small distance therebetween, to reduce a circuit area. In cases where the gate conductive film is formed to have a relatively small film thickness, a resistance value thereof becomes higher. Thus, in the seventh embodiment, the gate conductive film is preferably comprised of a metal film.

Eighth Embodiment

An eighth embodiment of the present invention shows a method of producing an NMOS SGT on an SOI substrate (SOI NMOS SGT), using the same gate forming process as that in the second embodiment.

The gate forming process in the eighth embodiment is capable of further reducing the number of steps and further increasing a process margin, as compared with the gate forming process in the seventh embodiment.

FIGS. 108(a) and108(b) are, respectively, a top plan view and a sectional view of the SOI NMOS SGT formed by the SGT production method according to the eighth embodiment. With reference toFIGS. 108(a) and108(b), the SOI NMOS SGT formed by the SGT production method according to the eighth embodiment will be described below.

A planar silicon layer801is formed on a buried oxide film layer800. A pillar-shaped silicon layer802is formed on the planar silicon layer801, and a gate dielectric film805and a gate electrode806aare formed around the pillar-shaped silicon layer802. An N+drain diffusion layer803is formed in the planar silicon layer801beneath the pillar-shaped silicon layer802, and an N+source diffusion layer804is formed in an upper portion of the pillar-shaped silicon layer. A contact807, a contact808, and a contact809, are formed on the N+drain diffusion layer803, the N+source diffusion layer804, and a gate line806bextending from the gate electrode806a, respectively. In the eighth embodiment, the gate electrode806aand the gate line806bare formed to be at the same height position.

Under conditions that the N+source diffusion layer is connected to a GND potential, and the N+drain diffusion layer is connected to a power supply potential Vcc, a potential ranging from zero to Vcc is applied to the gate electrode to allow the SGT to operate as a transistor.

With reference toFIGS. 109(a) to118(b), one example of the SGT production method according to the eighth embodiment will be described below. InFIGS. 109(a) to118(b), the figure suffixed by (a) is a top plan view, and the figure suffixed by (b) is a sectional view taken along the line A-A′.

In the eighth embodiment, the step of forming a gate dielectric film and any step therebefore are the same as those in the seventh embodiment. Thus, the following description will be started from the step of forming a gate conductive film.

Referring toFIGS. 109(a) and109(b), a gate dielectric film805and a gate conductive film806is formed by CVD or ALD, wherein the gate conductive film806is formed to allow a pillar-shaped silicon layer802to be buried therein.

Referring toFIGS. 110(a) and110(b), the gate conductive film806is polished by CMP, to flatten a top surface of the gate conductive film. Through the flattening of a top of the gate conductive film by CMP, a configuration of the gate conductive film is improved to facilitate control of a gate length. During the CMP, a silicon nitride film810on a top of a pillar-shaped silicon layer is used as a CMP stopper. The use of the silicon nitride film810as a CMP stopper makes it possible to control an amount of CMP with high repeatability.

Referring toFIGS. 111(a) and111(b), the gate conductive film806is etched back to fix a gate length.

Referring toFIGS. 112(a) and112(b), a silicon nitride film812ais formed by a film thickness required for an after-mentioned gate electrode. Subsequently, as shown inFIGS. 113(a) and113(b), the silicon nitride film812ais etched back to form a silicon nitride film-based sidewall812. In the eighth embodiment, a film thickness of the gate electrode is determined by a film thickness of the silicon nitride film-based sidewall812. Thus, a final film thickness of the silicon nitride film-based sidewall812is controlled to become equal to a desired film thickness of the gate electrode, by adjusting a formed film thickness of the silicon nitride film812aand then finely adjusting the formed film thickness based on an amount of the etch-back.

Referring toFIGS. 114(a) and114(b), a resist or a multilayer resist is applied, and a gate line pattern is formed with a resist813by lithography.

Referring toFIGS. 115(a) and115(b), the gate conductive film and the gate dielectric film are etched using the resist as a mask, to form a gate electrode806aand a gate line806b.

Referring toFIGS. 116(a) and116(b), the silicon nitride film810on the top of the pillar-shaped silicon layer, and the silicon nitride film-based sidewall812, are removed by wet etching.

Referring toFIGS. 117(a) and117(b), an impurity, such as P or As, is introduced into a top portion of the pillar-shaped silicon layer802, for example, by ion implantation, to form an N+source diffusion layer804therein.

Referring toFIGS. 118(a) and118(b), an interlayer dielectric film is formed, and a contact (807,808,809) is formed on each of the drain diffusion layer in the planar silicon layer, the source diffusion layer in the upper portion of the pillar-shaped silicon layer, and the gate line.

In the method according to the eighth embodiment, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed in the above manner. This makes it possible to achieve a gate forming process having the following features.

A first feature is that the process is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second feature is that the process is less vulnerable to a deviation in exposure alignment during gate line formation. Thus, the use of the method according to the eighth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

A third feature is that the step of flattening a top surface of a gate conductive film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. Thus, the use of the method according to the eighth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming the gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

As described above, the method according to the eighth embodiment can form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. In the seventh embodiment, a film thickness of a gate electrode is controlled based on a formed film thickness of a gate conductive film. Differently, in the eighth embodiment, the film thickness of the gate electrode can be controlled based on a film thickness of the silicon nitride film-based sidewall812. Further, in the eighth embodiment, the gate line806bhas a relatively large film thickness as compared with that of the gate line in the seventh embodiment. Thus, the gate conductive film is not limited to a metal film, but may be made of a material having relatively high electrical resistance, such as polysilicon.

In the seventh embodiment, if the silicon nitride film-based sidewall has a film thickness largely different from that of the gate conductive film, the difference is likely to cause the problems as described in connection with the second embodiment. Differently, the gate forming process in the eighth embodiment can form a gate electrode to have a desired film thickness, in a self-alignment manner according to a film thickness of the silicon nitride film-based sidewall812, as with the second embodiment. This makes it possible to eliminate a risk of occurrence of the above problems, and further increase a process margin in the gate forming process, as compared with that in the seventh embodiment.

Ninth Embodiment

A ninth embodiment of the present invention shows a method of producing an NMOS SGT on an SOI substrate (SOI NMOS SGT), using the same gate forming process as that in the third embodiment.

The gate forming process is different from that in the eighth embodiment, in that a gate electrode and a gate line extending from the gate electrode are formed in a layered structure which comprises a thin metal film and a polysilicon layer. In a gate forming process in the ninth embodiment, the thin metal film is formed to be in contact with a gate dielectric film so as to suppress depletion of the gate electrode, and the polysilicon layer is formed to define respective top surfaces of the gate electrode and the gate line, so as to allow the SGT to be produced in the same production line as that for a transistor having a conventional polysilicon gate.

FIGS. 119(a) and119(b) are, respectively, a top plan view and a sectional view of the SOI NMOS SGT formed by the SGT production method according to the ninth embodiment. With reference toFIGS. 119(a) and119(b), the SOI NMOS SGT formed by the method according to the ninth embodiment will be described below.

A planar silicon layer901is formed on a buried oxide film layer900. A pillar-shaped silicon layer902is formed on the planar silicon layer901, and a gate dielectric film905and a gate electrode906aare formed around the pillar-shaped silicon layer902. The gate electrode has a layered structure which comprises a thin metal film314having a film thickness of about 1 to 10 nm, and a polysilicon layer906acovering the metal film. An N+drain diffusion layer903is formed in the planar silicon layer901beneath the pillar-shaped silicon layer902, and an N+source diffusion layer804is formed in an upper portion of the pillar-shaped silicon layer902. A contact907, a contact908, and a contact909, are formed on the N+drain diffusion layer903, the N+source diffusion layer904, and a gate line906bextending from the gate electrode906a, respectively. In the ninth embodiment, the gate electrode906aand the gate line906bare formed to be at the same height position.

Under conditions that the N+source diffusion layer is connected to a GND potential, and the N+drain diffusion layer is connected to a power supply potential Vcc, a potential ranging from zero to Vcc is applied to the gate electrode to allow the SGT to operate as a transistor.

With reference toFIGS. 120(a) to130(b), one example of the SGT production method according to the ninth embodiment will be described below. InFIGS. 120(a) to130(b), the figure suffixed by (a) is a top plan view, and the figure suffixed by (b) is a sectional view taken along the line A-A′.

In the ninth embodiment, the step of forming a gate dielectric film and any step therebefore are the same as those in the seventh embodiment. Thus, the following description will be started from the step of forming a thin metal film and a polysilicon layer.

Referring toFIGS. 120(a) and120(b), after forming a gate dielectric film905, a thin metal film914is formed to have a film thickness of about 1 to 10 nm, and then a polysilicon layer906is formed to allow a pillar-shaped silicon layer902to be buried therein.

Referring toFIGS. 121(a) and121(b), the polysilicon layer906, and respective portions of the thin metal film914and the gate dielectric film905above the pillar-shaped silicon layer, are polished by CMP, to flatten respective top surfaces of the polysilicon layer906and the thin metal film914. Through the flattening of respective tops of the polysilicon layer906and the thin metal film914by CMP, respective configurations of the polysilicon layer906and the thin metal film914are improved to facilitate control of a gate length. During the CMP, a silicon nitride film910on a top of the pillar-shaped silicon layer is used as a CMP stopper. The use of the silicon nitride film910as a CMP stopper makes it possible to control an amount of CMP with high repeatability.

Referring toFIGS. 122(a) and122(b), the polysilicon layer906and the thin metal film914are etched back to fix a gate length.

Referring toFIGS. 123(a) and123(b), a silicon nitride film912ais formed by a film thickness required for an after-mentioned gate electrode. Subsequently, as shown inFIGS. 124(a) and124(b), the silicon nitride film912ais etched back to form a silicon nitride film-based sidewall912. In the ninth embodiment, a film thickness of the gate electrode is determined by a film thickness of the silicon nitride film-based sidewall912. Thus, a final film thickness of the silicon nitride film-based sidewall is controlled to become equal to a desired film thickness of the gate electrode, by adjusting a formed film thickness of the silicon nitride film912aand then finely adjusting the formed film thickness based on an amount of the etch-back.

Referring toFIGS. 125(a) and125(b), a resist or a multilayer resist is applied, and a gate line pattern is formed with a resist913by lithography.

Referring toFIGS. 126(a) and126(b), the polysilicon layer, the thin metal film and the gate dielectric film are etched using the resist as a mask, to form a gate electrode906aand a gate line906b.

Referring toFIGS. 127(a) and127(b), the silicon nitride film910on the top of the pillar-shaped silicon layer, and the silicon nitride film-based sidewall912, are removed by wet etching.

Referring toFIGS. 128(a) and128(b), a silicon nitride film is formed and then etched back to form a silicon nitride film915. The silicon nitride film915is formed to cover the thin metal film914of the gate electrode to keep a top surface of the thin metal film914from being exposed. This makes it possible to produce an intended SGT in the same production line as that for a transistor having a conventional polysilicon gate.

Referring toFIGS. 129(a) and129(b), an impurity, such as P or As, is introduced into a top portion of the pillar-shaped silicon layer902, for example, by ion implantation, to form an N+source diffusion layer904therein.

Referring toFIGS. 130(a) and130(b), an interlayer dielectric film is formed, and a contact (907,908,909) is formed on each of the drain diffusion layer in the planar silicon layer, the source diffusion layer in the upper portion of the pillar-shaped silicon layer, and the gate line.

In the method according to the ninth embodiment, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed in the above manner. This makes it possible to achieve a gate forming process having the following features.

A first feature is that the process is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second feature is that the process is less vulnerable to a deviation in exposure alignment during gate line formation. Thus, the use of the method according to the ninth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

A third feature is that the step of flattening respective top surfaces of a polysilicon layer and a thin metal film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. Thus, the use of the method according to the ninth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming the gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

As described above, the method according to the ninth embodiment can form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness, and control a film thickness of the gate electrode based on a film thickness of the silicon nitride film-based sidewall912, as with the second embodiment.

In the ninth embodiment, a gate is formed in a layered structure which comprises the thin metal film and the polysilicon layer, which is capable of suppressing depletion of the gate electrode, and allowing an intended SGT to be produced in the same production line as that for a transistor having a conventional polysilicon gate.

In the seventh embodiment, if the silicon nitride film-based sidewall has a film thickness largely different from that of the gate conductive film, the difference is likely to cause the problems as described in connection with the second embodiment. Differently, the gate forming process in the ninth embodiment can form a gate electrode to have a desired film thickness, in a self-alignment manner according to a film thickness of the silicon nitride film-based sidewall912, as with the second embodiment. This makes it possible to eliminate a risk of occurrence of the above problems, and further increase a process margin in the gate forming process, as compared with that in the seventh embodiment.

Tenth Embodiment

A tenth embodiment of the present invention shows a method of producing a CMOS SGT on an SOI substrate (SOI CMOS SGT), using the same gate forming process as that in the seventh embodiment. Thus, the method according to the tenth embodiment can be employed to obtain the same advantageous effects as those in the seventh embodiment.

FIG. 131is an equivalent circuit diagram of a CMOS inverter formed by the method according to the tenth embodiment. A circuit operation of the CMOS inverter will be described below. An input signal Vin4is applied to a gate of an NMOS Qn4and a gate of a PMOS Qp4. When the Vin4is “1”, the NMOS Qn4is placed in an ON state, and the PMOS Qp4is placed in an OFF state, so that an output signal Vout4becomes “0”. Reversely, when the Vin4is “0”, the NMOS Qn4is placed in an OFF state, and the PMOS Qp4is placed in an ON state, so that the Vout4becomes “1”. As above, the CMOS inverter is operable to allow the output signal Vout4to have a value opposite to that of the input signal Vin4.

FIG. 132is a top plan view of the CMOS inverter formed by the method according to the tenth embodiment.FIGS. 133(a) and133(b) are sectional views taken along the cutting-plane line A-A′ and the cutting-plane line B-B′ inFIG. 132, respectively. With reference toFIGS. 132,133(a) and133(b), a structure of the CMOS inverter will be described.

A planar silicon layer (1002,1003) is formed on a buried oxide film layer1000. A pillar-shaped silicon layer1007is formed on the planar silicon layer1002, and a pillar-shaped silicon layer1008is formed on the planar silicon layer1003. A gate dielectric film1009and a gate electrode (1010a,1010b) are formed around the pillar-shaped silicon layers. The gate electrodes1010a,1010bare connected to each other through a gate line1010cextending therefrom. An N+drain diffusion layer1004is formed in the planar silicon layer1002beneath the pillar-shaped silicon layer1007forming an NMOS (NMOS-forming pillar-shaped silicon layer1007), and an N+source diffusion layer1011is formed in an upper portion of the pillar-shaped silicon layer1007. A P+drain diffusion layer1005is formed in the planar silicon layer1003beneath the pillar-shaped silicon layer1008forming a PMOS (PMOS-forming pillar-shaped silicon layer1008), and a P+source diffusion layer1012is formed in an upper portion of the pillar-shaped silicon layer1008.

Each of the N+drain diffusion layer1004and the P+drain diffusion layer1005formed beneath respective ones of the pillar-shaped silicon layers1007,1008is connected to the output terminal Vout4via a contact (1016a,1016b). The N+source diffusion layer1011formed in the upper portion of the NMOS-forming pillar-shaped silicon layer1007is connected to a ground potential Vss4via a contact1014, and the P+source diffusion layer1012formed in the upper portion of the PMOS-forming pillar-shaped silicon layer1008is connected to a power supply potential Vcc4via a contact1015. Further, the gate line1010cconnecting between the gate electrodes for the PMOS and the NMOS is connected to the input terminal Vin4via a contact1013. In this manner, the CMOS inverter is formed.

With reference toFIGS. 134(a) to149(b), one example of the SGT production method according to the tenth embodiment will be described below. InFIGS. 134(a) to149(b), the figure suffixed by (a) is a top plan view, and the figure suffixed by (b) is a sectional view taken along the line A-A′.

Referring toFIGS. 134(a) and134(b), a silicon nitride film1017serving as a hard mask is formed on a silicon layer1001aon a buried oxide film layer1000in an SOI substrate, to have a film thickness of about 50 to 150 nm.

Referring toFIGS. 135(a) and135(b), the hard mask1017and the silicon layer1001aare etched to form a pillar-shaped silicon layer (1007,1008). Through the etching, the pillar-shaped silicon layer is formed to have a height dimension of about 30 to 300 nm, and a diameter of about 5 to 100 nm. A continuous planar silicon layer1001is also formed beneath the pillar-shaped silicon layer (1007,1008) to have a thickness of about 10 to 100 nm.

Referring toFIGS. 136(a) and136(b), the continuous planar silicon layer1001is formed with two isolated planar silicon layers1002,1003, by etching.

Referring toFIGS. 137(a) and137(b), impurities, such as P or As, are introduced into a top surface of respective top surfaces of the planar silicon sub-layers, for example, by ion implantation, to form an N+drain diffusion layer1004and a P+drain diffusion layer1005therein. During this step, the silicon nitride film1017on a top of the pillar-shaped silicon layer (1007,1008) functions as a stopper for preventing the impurity from being injected into the top of the pillar-shaped silicon layer.

Referring toFIGS. 138(a) and138(b), a gate dielectric film1009and a gate conductive film1010are formed by CVD or ALD. The gate conductive film1010is formed to have a film thickness of about 10 to 100 nm.

Referring toFIGS. 139(a) and139(b), a silicon oxide film1018is formed to allow the pillar-shaped silicon layer (1007,1008) to be buried therein.

Referring toFIGS. 140(a) and140(b), the silicon oxide film1018, and respective portions of the gate conductive film and the gate dielectric film above of the pillar-shaped silicon layer (1007,1008), are polished by CMP, to flatten a top surface of the gate conductive film. Through the flattening of a top of the gate conductive film by CMP, a configuration of the gate conductive film is improved to facilitate control of a gate length. During the CMP, the silicon nitride film1017on the top of the pillar-shaped silicon layer (1007,1008) is used as a CMP stopper. The use of the silicon nitride film1017as a CMP stopper makes it possible to control an amount of CMP with high repeatability.

Referring toFIGS. 141(a) and141(b), the gate conductive film1010and the silicon oxide film1018are etched back, wherein the gate conductive film1010is etched to fix a gate length. Preferably, etching conditions to be used in this step are set to allow the gate conductive film1010and the silicon oxide film1018to be etched at the same rate, and at a higher selectivity ratio relative to the silicon nitride film1017. The etching of the gate conductive film1010and the silicon oxide film1018at the same rate makes it possible to suppress occurrence of a step between respective top surfaces of the two films, which improves a configuration of a silicon nitride film-based sidewall1019to be formed in a next step.

Referring toFIGS. 142(a) and142(b), a silicon nitride film1019ais formed by a film thickness required for the gate conductive film1010. Subsequently, as shown inFIGS. 143(a) and143(b), the silicon nitride film1019ais etched back to form a silicon nitride film-based sidewall1019. In this step, a film thickness of the silicon nitride film-based sidewall1019is controlled to become equal to that of the gate conductive film1010, by adjusting a formed film thickness of the silicon nitride film1019a, and then finely adjusting the formed film thickness based on an amount of the etch-back. A portion of the gate conductive film1010covered by the silicon nitride film-based sidewall1019will be protected during etching for forming a gate line in a subsequent step. This makes it possible to form the gate electrode in a self-alignment manner and with a desired film thickness, so as to reduce an occupancy area.

Referring toFIGS. 144(a) and144(b), the silicon oxide film1018remaining on the gate conductive film is removed by wet etching.

Referring toFIGS. 145(a) and145(b), a resist or a multilayer resist is applied, and a gate line pattern is formed with a resist1020by lithography.

Referring toFIGS. 146(a) and146(b), the gate conductive film and the gate dielectric film are etched using the resist as a mask, to form a gate electrode (1010a,1010b) and a gate line1010c.

Referring toFIGS. 147(a) and147(b), the silicon nitride film1017on the top of the pillar-shaped silicon layer (1007,1008), and the silicon nitride film-based sidewall1019, are removed by wet etching.

Referring toFIGS. 148(a) and148(b), an impurity, such as P or As, is introduced into a top portion of the pillar-shaped silicon layer1007, for example, by ion implantation, to form an N+source diffusion layer1011therein. Further, an impurity, such as B or BF2, is introduced into a top portion of the pillar-shaped silicon layer1008, for example, by ion implantation, to form a P+source diffusion layer1012therein.

Referring toFIGS. 149(a) and149(b), an interlayer dielectric film is formed, and a contact (1013,1014,1015,1016a,1016b) is formed on each of the gate line, the source diffusion layers in the upper portions of the pillar-shaped silicon layers, and the drain diffusion layers in the planar silicon sub-layers.

In the method according to the tenth embodiment, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed in the above manner. This makes it possible to achieve a gate forming process having the following features.

A first feature is that the process is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second feature is that the process is less vulnerable to a deviation in exposure alignment during gate line formation. Thus, the use of the method according to the seventh embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

A third feature is that the step of flattening a top surface of a gate conductive film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. Thus, the use of the method according to the tenth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

Thus, the use of the method according to the tenth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

As described above, the method according to the tenth embodiment can form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness, and adjust a film thickness of the gate electrode to be formed around the pillar-shaped silicon layer, based on a formed film thickness of a gate conductive film. Thus, two pillar-shaped silicon layers each having a gate electrode to be applied with a different potential can be arranged side-by-side with a relatively small distance therebetween, to reduce a circuit area. In cases where the gate conductive film is formed to have a relatively small film thickness, a resistance value thereof becomes higher. Thus, in the tenth embodiment, the gate conductive film is preferably comprised of a metal film.

Eleventh Embodiment

An eleventh embodiment of the present invention shows a method of producing a CMOS SGT on an SOI substrate (SOI CMOS SGT), using the same gate forming process as that in the eighth embodiment. Thus, the method according to the eleventh embodiment can be employed to obtain the same advantageous effects as those in the eighth embodiment.

FIG. 150is an equivalent circuit diagram of a CMOS inverter formed by the method according to the eleventh embodiment. A circuit operation of the CMOS inverter will be described below. An input signal Vin5is applied to a gate of an NMOS Qn5and a gate of a PMOS Qp5. When the Vin5is “1”, the NMOS Qn5is placed in an ON state, and the PMOS Qp5is placed in an OFF state, so that an output signal Vout5becomes “0”. Reversely, when the Vin5is “0”, the NMOS Qn5is placed in an OFF state, and the PMOS Qp5is placed in an ON state, so that the Vout5becomes “1”. As above, the CMOS inverter is operable to allow the output signal Vout5to have a value opposite to that of the input signal Vin5.

FIG. 151is a top plan view of the CMOS inverter formed by the method according to the eleventh embodiment.FIGS. 152(a) and152(b) are sectional views taken along the cutting-plane line A-A′ and the cutting-plane line B-B′ inFIG. 151, respectively. With reference toFIGS. 151,152(a) and152(b), a structure of the CMOS inverter will be described.

A planar silicon layer (1102,1103) is formed on a buried oxide film layer1100. A pillar-shaped silicon layer1107is formed on the planar silicon layer1102, and a pillar-shaped silicon layer1108is formed on the planar silicon layer1103. A gate dielectric film1109and a gate electrode (1110a,1110b) are formed around the pillar-shaped silicon layers. The gate electrodes1110a,1110bare connected to each other through a gate line1110cextending therefrom. The gate electrode (1110a,1110b) and the gate line1106care formed to be at the same height position. An N+drain diffusion layer1104is formed in the planar silicon layer1102beneath the pillar-shaped silicon layer1107forming an NMOS (NMOS-forming pillar-shaped silicon layer1107), and an N+source diffusion layer1111is formed in an upper portion of the pillar-shaped silicon layer1107. A P+drain diffusion layer1105is formed in the planar silicon layer1103beneath the pillar-shaped silicon layer1108forming a PMOS (PMOS-forming pillar-shaped silicon layer1108), and a P+source diffusion layer1112is formed in an upper portion of the pillar-shaped silicon layer1108.

Each of the N+drain diffusion layer1104and the P+drain diffusion layer1105formed beneath respective ones of the pillar-shaped silicon layers1107,1108is connected to the output terminal Vout5via a contact (1116a,1116b). The N+source diffusion layer1111formed in the upper portion of the NMOS-forming pillar-shaped silicon layer1107is connected to a ground potential Vss5via a contact1114, and the P+source diffusion layer1112formed in the upper portion of the PMOS-forming pillar-shaped silicon layer1108is connected to a power supply potential Vcc5via a contact1115. Further, the gate line1110cconnecting between the gate electrodes for the PMOS and the NMOS is connected to the input terminal Vin5via a contact1113. In this manner, the CMOS inverter is formed.

With reference toFIGS. 153(a) to162(b), one example of the SGT production method according to the eleventh embodiment will be described below. InFIGS. 153(a) to162(b), the figure suffixed by (a) is a top plan view, and the figure suffixed by (b) is a sectional view taken along the line A-A′. In the eleventh embodiment, the step of forming a gate dielectric film and any step therebefore are the same as those in the tenth embodiment. Thus, the following description will be started from the step of forming a gate conductive film.

Referring toFIGS. 153(a) and153(b), a gate dielectric film1109and a gate conductive film1110is formed by CVD or ALD, wherein the gate conductive film1110is formed to allow a pillar-shaped silicon layer (1107,1108) to be buried therein.

Referring toFIGS. 154(a) and154(b), the gate conductive film1110is polished by CMP, to flatten a top surface of the gate conductive film. Through the flattening of a top of the gate conductive film by CMP, a configuration of the gate conductive film is improved to facilitate control of a gate length. During the CMP, a silicon nitride film1117on a top of a pillar-shaped silicon layer (1107,1108) is used as a CMP stopper. The use of the silicon nitride film1117as a CMP stopper makes it possible to control an amount of CMP with high repeatability.

Referring toFIGS. 155(a) and155(b), the gate conductive film1110is etched back to fix a gate length.

Referring toFIGS. 156(a) and156(b), a silicon nitride film1119ais formed by a film thickness required for an after-mentioned gate electrode. Subsequently, as shown inFIGS. 157(a) and157(b), the silicon nitride film1119ais etched back to form a silicon nitride film-based sidewall1119. In the eleventh embodiment, a film thickness of the gate electrode is determined by a film thickness of the silicon nitride film-based sidewall1119. Thus, a final film thickness of the silicon nitride film-based sidewall is controlled to become equal to a desired film thickness of the gate electrode, by adjusting a formed film thickness of the silicon nitride film1119aand then finely adjusting the formed film thickness based on an amount of the etch-back.

Referring toFIGS. 158(a) and158(b), a resist or a multilayer resist is applied, and a gate line pattern is formed with a resist1120by lithography.

Referring toFIGS. 159(a) and159(b), the gate conductive film and the gate dielectric film are etched using the resist as a mask, to form a gate electrode (1110a,1110b) and a gate line1110c.

Referring toFIGS. 160(a) and160(b), the silicon nitride film1117on the top of the pillar-shaped silicon layer (1107,1108), and the silicon nitride film-based sidewall1119, are removed by wet etching.

Referring toFIGS. 161(a) and161(b), impurities are introduced into respective top portions of the pillar-shaped silicon layers1107,1108, for example, by ion implantation, to form an N+source diffusion layer1111and a P+source diffusion layer1112therein.

Referring toFIGS. 162(a) and162(b), an interlayer dielectric film is formed, and a contact (1113,1114,1115,1116a,1116b) is formed on each of the gate line, the source diffusion layers in the upper portions of the pillar-shaped silicon layers, and the drain diffusion layers in the planar silicon layers.

In the method according to the eleventh embodiment, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed in the above manner. This makes it possible to achieve a gate forming process having the following features.

A first feature is that the process is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second feature is that the process is less vulnerable to a deviation in exposure alignment during gate line formation. Thus, the use of the method according to the eleventh embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

A third feature is that the step of flattening a top surface of a gate conductive film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. Thus, the use of the method according to the eleventh embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming the gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

As described above, the method according to the eleventh embodiment can form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. In the tenth embodiment, a film thickness of a gate electrode is controlled based on a formed film thickness of a gate conductive film. Differently, in the eleventh embodiment, the film thickness of the gate electrode can be controlled based on a film thickness of the silicon nitride film-based sidewall1119. Further, in the eleventh embodiment, the gate line1110chas a relatively large film thickness as compared with that of the gate line in the tenth embodiment. Thus, the gate conductive film is not limited to a metal film, but may be made of a material having relatively high electrical resistance, such as polysilicon.

In the tenth embodiment, if the silicon nitride film-based sidewall has a film thickness largely different from that of the gate conductive film, the difference is likely to cause the problems as described in connection with the second embodiment. Differently, the gate forming process in the eleventh embodiment can form a gate electrode to have a desired film thickness, in a self-alignment manner according to a film thickness of the silicon nitride film-based sidewall1119, as with the second embodiment. This makes it possible to eliminate a risk of occurrence of the above problems, and further increase a process margin in the gate forming process, as compared with that in the tenth embodiment.

Although the SGT production method according to the eleventh embodiment has been described based on one example where it is applied to a CMOS inverter, it is understood that the present invention may be applied to any suitable circuit other than the CMOS inverter, in just the same manner.

Twelfth Embodiment

A twelfth embodiment of the present invention shows a method of producing a CMOS SGT on an SOI substrate (SOI CMOS SGT), using the same gate forming process as that in the ninth embodiment. Thus, the method according to the twelfth embodiment can be employed to obtain the same advantageous effects as those in the ninth embodiment.

FIG. 163is an equivalent circuit diagram of a CMOS inverter formed by the method according to the twelfth embodiment. A circuit operation of the CMOS inverter will be described below. An input signal Vin6is applied to a gate of an NMOS Qn6and a gate of a PMOS Qp6. When the Vin6is “1”, the NMOS Qn6is placed in an ON state, and the PMOS Qp6is placed in an OFF state, so that an output signal Vout6becomes “0”. Reversely, when the Vin6is “0”, the NMOS Qn6is placed in an OFF state, and the PMOS Qp6is placed in an ON state, so that the Vout6becomes “1”. As above, the CMOS inverter is operable to allow the output signal Vout6to have a value opposite to that of the input signal Vin6.

FIG. 164is a top plan view of the CMOS inverter formed by the method according to the twelfth embodiment.FIGS. 165(a) and165(b) are sectional views taken along the cutting-plane line A-A′ and the cutting-plane line B-B′ inFIG. 164, respectively. With reference toFIGS. 164,165(a) and165(b), the CMOS inverter formed by the method according to the twelfth embodiment will be described.

A planar silicon layer (1202,1203) is formed on a buried oxide film layer1200. A pillar-shaped silicon layer1207is formed on the planar silicon layer1202, and a pillar-shaped silicon layer1208is formed on the planar silicon layer1203. A gate dielectric film1209and a gate electrode (1210a,1210b) are formed around the pillar-shaped silicon layers. The gate electrode (1210a,1210b) is formed in a layered structure which comprises a polysilicon layer defining a top surface thereof, and a thin metal film1221in contact with a gate dielectric film. The gate electrodes1210a,1210bare connected to each other through a gate line1210cextending therefrom. The gate electrode (1210a,1210b) and the gate line1210care formed to be at the same height position. An N+drain diffusion layer2104is formed in the planar silicon layer1202beneath the pillar-shaped silicon layer1207forming an NMOS (NMOS-forming pillar-shaped silicon layer1207), and an N+source diffusion layer1211is formed in an upper portion of the pillar-shaped silicon layer1207. A P+drain diffusion layer1205is formed in the planar silicon layer1203beneath the pillar-shaped silicon layer1208forming a PMOS (PMOS-forming pillar-shaped silicon layer1208), and a P+source diffusion layer1212is formed in an upper portion of the pillar-shaped silicon layer1208.

Each of the N+drain diffusion layer1204and the P+drain diffusion layer1205formed beneath respective ones of the pillar-shaped silicon layers1207,1208is connected to the output terminal Vout6via a contact (1216a,1216b). The N+source diffusion layer1211formed in the upper portion of the NMOS-forming pillar-shaped silicon layer1207is connected to a ground potential Vss6via a contact1214, and the P+source diffusion layer1212formed in the upper portion of the PMOS-forming pillar-shaped silicon layer1208is connected to a power supply potential Vcc6via a contact1215. Further, the gate line1210cconnecting between the gate electrodes for the PMOS and the NMOS is connected to the input terminal Vin6via a contact1213. In this manner, the CMOS inverter is formed.

With reference toFIGS. 166(a) to176(b), one example of the SGT production method according to the twelfth embodiment will be described below. InFIGS. 166(a) to176(b), the figure suffixed by (a) is a top plan view, and the figure suffixed by (b) is a sectional view taken along the line A-A′. In the twelfth embodiment, the step of forming a gate dielectric film and any step therebefore are the same as those in the tenth embodiment. Thus, the following description will be started from the step of forming a thin metal film and a polysilicon layer.

Referring toFIGS. 166(a) and166(b), after forming a gate dielectric film1209, a thin metal film1221is formed to have a film thickness of about 1 to 10 nm, and then a polysilicon layer1210is formed to allow a pillar-shaped silicon layer (1207,1208) to be buried therein.

Referring toFIGS. 167(a) and167(b), the polysilicon layer1210, and respective portions of the thin metal film1221and the gate dielectric film1209above the pillar-shaped silicon layer, (1207,1208) are polished by CMP, to flatten respective top surfaces of the polysilicon layer1210and the thin metal film1221. Through the flattening of respective tops of the polysilicon layer1210and the thin metal film1221by CMP, respective configurations of the polysilicon layer1210and the thin metal film1221are improved to facilitate control of a gate length. During the CMP, a silicon nitride film1217on a top of the pillar-shaped silicon layer (1207,1208) is used as a CMP stopper. The use of the silicon nitride film1217as a CMP stopper makes it possible to control an amount of CMP with high repeatability.

Referring toFIGS. 168(a) and168(b), the polysilicon layer1210and the thin metal film1221are etched back to fix a gate length.

Referring toFIGS. 169(a) and169(b), a silicon nitride film1219ais formed by a film thickness required for an after-mentioned gate electrode. Subsequently, as shown inFIGS. 170(a) and170(b), the silicon nitride film1219ais etched back to form a silicon nitride film-based sidewall1219. In the twelfth embodiment, a film thickness of the gate electrode is determined by a film thickness of the silicon nitride film-based sidewall1219. Thus, a final film thickness of the silicon nitride film-based sidewall is controlled to become equal to a desired film thickness of the gate electrode, by adjusting a formed film thickness of the silicon nitride film1219aand then finely adjusting the formed film thickness based on an amount of the etch-back.

Referring toFIGS. 171(a) and171(b), a resist or a multilayer resist is applied, and a gate line pattern is formed with a resist1220by lithography.

Referring toFIGS. 172(a) and172(b), the polysilicon layer, the thin metal film and the gate dielectric film? are etched using the resist as a mask, to form a gate electrode (1210a,1210b) and a gate line1210c.

Referring toFIGS. 173(a) and173(b), the silicon nitride film1217on the top of the pillar-shaped silicon layer (1207,1208), and the silicon nitride film-based sidewall1219, are removed by wet etching.

Referring toFIGS. 174(a) and174(b), a silicon nitride film is formed and then etched back to form a silicon nitride film1222. The silicon nitride film1222is formed to cover the thin metal film1221of the gate electrode to keep a top surface of the thin metal film1221from being exposed. This makes it possible to produce an intended SGT in the same production line as that for a transistor having a conventional polysilicon gate.

Referring toFIGS. 175(a) and175(b), impurities are introduced into respective top portions of the pillar-shaped silicon layers1207,1208, for example, by ion implantation, to form an N+source diffusion layer1211and a P+source diffusion layer1212therein.

Referring toFIGS. 176(a) and176(b), an interlayer dielectric film is formed, and a contact (1213,1214,1215,1216a,1216b) is formed on each of the gate line, the source diffusion layers in the upper portions of the pillar-shaped silicon layers, and the drain diffusion layers in the planar silicon layers?.

In the method according to the twelfth embodiment, the step of performing etching to fix a gate length, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed in the above manner. This makes it possible to achieve a gate forming process having the following features.

A first feature is that the process is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second feature is that the process is less vulnerable to a deviation in exposure alignment during gate line formation. Thus, the use of the method according to the twelfth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line arising from a lithography step of forming a gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

A third feature is that the step of flattening respective top surfaces of a polysilicon layer and a thin metal film by CMP, using a structure which has a silicon nitride film formed on a top of a pillar-shaped silicon layer to serve as a hard mask, is provided before the step of performing etching to fix a gate length, and, after these steps, the step of forming a gate electrode-protecting silicon nitride film-based sidewall, the step of forming a gate line pattern, and the step of performing etching to form a gate line, are sequentially performed, whereby the gate length can be accurately controlled to achieve a process capable of minimizing a variation in gate length and increasing a process margin. Thus, the use of the method according to the twelfth embodiment makes it possible to simultaneously solve both the following problems: a disconnection or open of a gate line and a variation in gate length arising from a lithography step of forming the gate line, as the problem in the method disclosed in the Patent Document 1; and an incapability to form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner, as the problem in the method disclosed in the Non-Patent Document 1.

As described above, the method according to the twelfth embodiment can form a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness, and control a film thickness of the gate electrode based on a film thickness of the silicon nitride film-based sidewall1219, as with the third embodiment.

In the twelfth embodiment, a gate is formed in a layered structure which comprises the thin metal film and the polysilicon layer, which is capable of suppressing depletion of the gate electrode, and allowing an intended SGT to be produced in the same production line as that for a transistor having a conventional polysilicon gate.

In the tenth embodiment, if the silicon nitride film-based sidewall has a film thickness largely different from that of the gate conductive film, the difference is likely to cause the problems as described in connection with the second embodiment. Differently, the gate forming process in the twelfth embodiment can form a gate electrode to have a desired film thickness, in a self-alignment manner according to a film thickness of the silicon nitride film-based sidewall1219, as with the second embodiment. This makes it possible to eliminate a risk of occurrence of the above problems, and further increase a process margin in the gate forming process, as compared with that in the tenth embodiment.

Although the SGT production method according to the twelfth embodiment has been described based on one example where it is applied to a CMOS inverter, it is understood that the present invention may be applied to any suitable circuit other than the CMOS inverter, in just the same manner.