Analog signal processing circuit

An analog signal processing block with differential signal inputs and including a differential amplifier with differential inputs is disclosed which is configurable to operate either in a differential output mode or in a single-ended output mode without affecting the desired frequency and time characteristics as determined by the switched capacitor networks. The analog signal processing block includes a pair of switched capacitor networks each having one of the differential signal inputs, an input-sided terminal connected to one of the differential inputs of the differential amplifier and an output-sided terminal. The output-sided terminal of a first one of the switched capacitor networks is connected to an output of the differential amplifier. The output-sided terminal of a second one of the switched capacitor networks is connected to a complementary output of the differential amplifier when configured to differential output mode, and connected to a reference potential when configured to the single-ended mode. In this way, an application can use an analog signal processing block in either of the fully differential and single-ended output modes without the need to reconfigure the switched capacitor networks for a desired frequency and time response characteristic.

The invention relates to an analog signal processing circuit block that can be used for filtering of analog signals.

BACKGROUND

signal processing of analog signals often requires filtering, including integration, differentiation and amplification. A common method to implement filtering of analog signals with integrated circuits is the use of switched capacitor techniques, especially including correlated double sampling to cancel non-ideal circuit parameters. In such analog signal processing circuit blocks, the frequency and time response characteristics are determined by switched capacitor networks. According to the particular application, a fully differential output or a single-ended output of the processing circuit block is required.

SUMMARY

The invention provides an analog signal processing circuit block with differential signal inputs and including a differential amplifier with differential inputs and configurable to operate either in a differential output mode or in a single-ended output mode without affecting the desired frequency and time characteristics as determined by the switched capacitor networks. Specifically, the inventive analog signal processing circuit block includes a pair of switched capacitor networks each having one of the differential signal inputs, an input-sided terminal connected to one of the differential inputs of the differential amplifier and an output-sided terminal. The output-sided terminal of a first one of the switched capacitor networks is connected to an output of the differential amplifier. The output-sided terminal of a second one of the switched capacitor networks is connected to a complementary output of the differential amplifier when configured to differential output mode, and connected to a reference potential when configured to the single-ended mode. In this way, an application can use an analog signal processing block in either of the fully differential and single-ended output modes without the need to reconfigure the switched capacitor networks for a desired frequency and time response characteristic.

In a preferred embodiment, the differential amplifier has two output stages and one of the output stages is disabled in the single-ended output mode. Where the output stages each have complementary MOSFET driver transistors, this is simply achieved by disconnecting the gates of the driver transistors and connecting them to their sources.

In a preferred implementation, the differential amplifier includes an input pair of transistors that have their drains connected to a folded cascode structure with a class AB control block included in each branch of the folded cascode structure, The class AB control block on the side of the output stage which is disabled in the single-ended output mode, is also disabled (i.e. effectively shorted) in the single-ended output mode.

The analog signal processing block of the invention preferably has common mode feedback circuitry for use in the fully differential output mode of the differential amplifier. In the single-ended output mode, there is no need for the common made feedback circuitry, and the common mode feedback circuitry is disconnected in the single-ended output mode.

Still further, in the preferred embodiment, the differential amplifier is configured by application, to the analog signal processing block, of a digital control signal that controls a set of configuration switches associated with the differential amplifier. Accordingly, to select between the fully differential and single-ended output modes, all that a particular application must provide is a digital configuration control signal.

DETAILED DESCRIPTION OF EMBODIMENTS

With reference toFIG. 1, an analog signal processing block is implemented as an integrated circuit and comprises a differential amplifier10with differential inputs In_p and In_n and differential outputs Out_p and Out_n. A first switched capacitor network12has a signal input Vin_n, and input-sided terminal connected to the inverting input In_n of amplifier10and an output-sided terminal connected to the non-inverting output Out_p of amplifier10. The processing block has a non-inverting signal output Vout_p connected to the output Out_p of amplifier10. A second switched capacitor network14has a signal input Vin_p, an input-sided terminal connected to the non-inverting input In_p of amplifier10and an output-sided terminal shown inFIG. 1as connected to the inverting output Out_n of amplifier10through a switch SW1. The processing block has an inverting signal output Vout_n connected to the output Out_n of amplifier10.

As shown inFIG. 1, the analog signal processing block is configured to be fully differential, with a pair of complementary signal inputs Vin_p, Vin_n and a pair of complementary signal outputs Vout_p, Vout_n. Each of the switched capacitor networks12,14has a clock input connected to a common sampling clock terminal CLK and a ground input connected to a common ground terminal GND. The sampled switched capacitor networks12,14determine the frequency and time response characteristics of the analog signal processing block. The basic arrangement of the capacitors and switches in these networks may, for example, be similar to the arrangement disclosed in K. Martin, G. Temes et al., “A Differential Switch-Capacitor Amplifier,” JSSC February 1987, at page 104.

To change the analog signal processing block from the fully differential mode shown inFIG. 1to a single-ended mode, the switch SW1is opened, the output-sided terminal of network14is connected to a reference potential or to ground through a switch SW2, and the differential amplifier10is configured to a single-ended output mode where its output Out_n is floating and only output Out_p is effective. A configuration control input VD/Ereceives a digital configuration control signal that controls switches SW1and SW2and is also applied to differential amplifier10.

InFIG. 2, the differential amplifier10ofFIG. 1is shown configured in a differential output mode. Basically, the differential amplifier in the embodiment shown is fully symmetrical with an n-channel input transistor pair MN1, MN2and two output stages. Input transistors MN1and MN2each have a source connected to a current source1and a drain connected to a folded cascode structure, described below. The gate of transistor MN1is connected to receive the input In_n and the gate of transistor MN2is connected to receive the input IN_p. On the inverting output side, the output stage has a p-channel transistor MP1connected in series with an n-channel transistor MN3between supply terminals AVDD and AVSS. The interconnected drains of transistors MP1and MN3constitute the inverting output Out_n of the differential amplifier. Likewise, on the non-inverting output side, the output stage has a p-channel transistor MP2connected in series with an n-channel transistor MN4between supply terminals AVDD and AVSS. The interconnected drains of transistors MP2and MN4constitute the non-inverting output Out_p of the differential amplifier.

On the non-inverting output side, the gates of the transistors MP2, MN4in the output stage are driven by a folded cascode structure that includes a series connection between supply terminals AVDD and AVSS of p-channel transistors MP3, MP4, a Class AB control block16and n-channel transistors MN5, MN6. The drain of input transistor MN2is connected to the interconnected drain and source of transistors MP3and MP4, as shown.

On the inverting output side, the gates of the transistors MP1, MN3in the output stage are driven by a folded cascode structure that includes a series connection between supply terminals AVDD and AVSS of p-channel transistors MP5, MP6, a Class AB control block18and n-channel transistors MN7, MN8. The drain of input transistor MN1is connected to the interconnected drain and source of transistors MP5and MP6, as shown.

Common mode feedback circuitry20is connected in the differential output mode to both differential outputs Out_p and Out_n and to the interconnected nodes of transistors MN7and MN8on the negative output side and transistors MN5, MN6on the positive output side.

While appropriate bias voltages V2, V3and V4are permanently applied to the gates of transistors MN7, MN5, to transistors MP6, MP4and to transistors MP5, MP3, respectively, a bias voltage V1is applied to the gates of transistors MN8and MN6only in the differential output mode through a closed switch SW3.

In the single-ended output mode shown inFIG. 3, switch SW3is opened and a switch SW4is closed to connect the gate of transistors, MN6, MN8with the drain of transistor MP6, effectively shorting the class AB control block18. At the same time, the gates of output transistors MP1and MN3are disconnected from the folded cascode structure by opening switches SW5, SW6and connected with their sources by closing switches SW7, SW8, so that the output Out_n is floating. In addition, the common mode feedback circuitry is disconnected by opening switches SW9, SW10.

All of the configuration switches SW1to SW10are controlled by the digital configuration control signal VD/E.