Memory device and a method for forming the memory device

A memory device may include a substrate, a first gate structure, a mask and a second gate structure. The substrate may include a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region. The first gate structure may be at least partially arranged over the channel region, and may include a top surface that may be substantially flat. The mask may be at least partially arranged over the top surface of the first gate structure. The second gate structure may be at least partially arranged over the mask and at least partially arranged adjacent to the first gate structure.

TECHNICAL FIELD

The present disclosure relates generally to memory devices, methods for forming the memory devices and memory cells including the memory devices.

BACKGROUND

Memory cells including embedded non-volatile memory devices are often used in various consumer electronic products such as smart phones & tablets, and micro control units (MCU). The fabrication of memory cells such as a 1.5 T split gate flash with a control gate and an erase gate is often complicated and expensive. This is usually because of the use of complicated processes for the fabrication of the memory cells. For example, a two-step polysilicon deposition/chemical mechanical polishing (CMP)/etchback process is often used to fabricate the write lines of memory cells. Further, an immersion tool is often used to fabricate the control gates of memory cells. In addition, the fabrication of the memory cells usually involves the use of several masks. The expensive and complicated processes of fabricating memory cells may not be suitable for fabricating memory cells for lower end applications.

Accordingly, it is desirable to provide a memory device that can be fabricated with a simplified process at a lower cost without significantly affecting the performance and size of the memory device.

SUMMARY

According to various non-limiting embodiments, there may be provided a memory device including a substrate including a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region; a first gate structure at least partially arranged over the channel region, wherein the first gate structure may include a top surface and wherein the top surface may be substantially flat; a mask at least partially arranged over the top surface of the first gate structure; and a second gate structure at least partially arranged over the mask and at least partially arranged adjacent to the first gate structure.

According to various non-limiting embodiments, there may be provided a method including providing a substrate; forming a first gate structure and a mask, wherein the first gate structure may be at least partially arranged over the channel region and may include a top surface, wherein the top surface may be substantially flat, and wherein the mask may be at least partially arranged over the top surface of the first gate structure; forming a source region at least partially within the substrate; forming a second gate structure at least partially over the mask and at least partially adjacent to the first gate structure; and forming a drain region at least partially within the substrate, wherein a channel region may be arranged between the source region and the drain region.

According to various non-limiting embodiments, there may be provided a memory cell including a plurality of memory devices. Each memory device may include a substrate including a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region; a first gate structure at least partially arranged over the channel region, wherein the first gate structure may include a top surface and wherein the top surface may be substantially flat; a mask at least partially arranged over the top surface of the first gate structure; and a second gate structure at least partially arranged over the mask and at least partially arranged adjacent to the first gate structure.

DETAILED DESCRIPTION

The non-limiting embodiments generally relate to devices, such as semiconductor devices. More particularly, some embodiments relate to memory devices, for example, non-volatile memory devices, such as embedded non-volatile memory devices including multi-time programmable (MTP) memory devices. The memory devices may be used to form memory cells, which may be used in various consumer electronic products such as smart phones and tablets.

According to various non-limiting embodiments, a memory device may include a substrate including a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region; a first gate structure at least partially arranged over the channel region, wherein the first gate structure may include a top surface and wherein the top surface may be substantially flat; a mask at least partially arranged over the top surface of the first gate structure; and a second gate structure at least partially arranged over the mask and at least partially arranged adjacent to the first gate structure.

According to various non-limiting embodiments, a method may include providing a substrate; forming a first gate structure and a mask, wherein the first gate structure may be at least partially arranged over the channel region and may include a top surface, wherein the top surface may be substantially flat, and wherein the mask may be at least partially arranged over the top surface of the first gate structure; forming a source region at least partially within the substrate; forming a second gate structure at least partially over the mask and at least partially adjacent to the first gate structure; and forming a drain region at least partially within the substrate, wherein a channel region may be arranged between the source region and the drain region.

According to various non-limiting embodiments, the first gate structure may include a side arranged substantially perpendicular to the top surface to form a tip.

According to various non-limiting embodiments, the first gate structure may include a tip pointing toward the second gate structure and the second gate structure may be at least partially arranged over the first gate structure such that the second gate structure at least partially surrounds the tip of the first gate structure.

According to various non-limiting embodiments, the mask may include a first side adjacent to the second gate structure and a first tip of the top surface of the first gate structure may extend beyond the first side of the mask in a direction toward the second gate structure.

According to various non-limiting embodiments, the mask may include a second side facing away from the second gate structure and a second tip of the top surface of the first gate structure may extend beyond the second side of the mask.

According to various non-limiting embodiments, forming the first gate structure and the mask may include forming a first gate electrode layer over the substrate; forming a mask layer over the first gate electrode layer; and removing portions of the first gate electrode layer and the mask layer.

According to various non-limiting embodiments, forming the first gate structure and the mask may further include smoothing the surface of the first gate electrode layer prior to forming the mask layer.

According to various non-limiting embodiments, the method may further include forming spacers adjacent to the mask and removing the spacers prior to forming the second gate structure.

According to various non-limiting embodiments, the method may further include forming a first part of a logic transistor at least partially within the substrate; and forming the second gate structure may include forming a second gate electrode layer over the substrate; and removing at least a portion of the second gate electrode layer to form the second gate structure and a second part of the logic transistor.

According to various non-limiting embodiments, a memory cell may include a plurality of memory devices. Each memory device may include a substrate including a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region; a first gate structure at least partially arranged over the channel region, wherein the first gate structure may include a top surface and wherein the top surface may be substantially flat; a mask at least partially arranged over the top surface of the first gate structure; and a second gate structure at least partially arranged over the mask and at least partially arranged adjacent to the first gate structure.

According to various non-limiting embodiments, for one or more of the memory devices, the first gate structure may include a side arranged substantially perpendicular to the top surface to form a tip.

According to various non-limiting embodiments, for one or more of the memory devices, the first gate structure may include a tip pointing toward the second gate structure and the second gate structure may be at least partially arranged over the first gate structure such that the second gate structure at least partially surrounds the tip of the first gate structure.

According to various non-limiting embodiments, for one or more of the memory devices, the mask may include a first side adjacent to the second gate structure and a first tip of the top surface of the first gate structure may extend beyond the first side of the mask in a direction toward the second gate structure.

According to various non-limiting embodiments, for one or more of the memory devices, the mask may include a second side facing away from the second gate structure and a second tip of the top surface of the first gate structure may extend beyond the second side of the mask.

As used herein, the term “connected,” when used to refer to two physical elements, means a direct connection between the two physical elements. The term “coupled,” however, can mean a direct connection or a connection through one or more intermediary elements.

FIG. 1Ashows an equivalent circuit of a memory cell100according to a non-limiting embodiment of the present invention andFIG. 1Bshows a simplified top view of a portion “A” of the memory cell100. The memory cell100may include a plurality of memory devices190.FIG. 1Cshows a cross-sectional view of the memory cell100along the line B-B′ that includes a memory device190according to a non-limiting embodiment of the present invention.FIG. 1Dshows the cross-sectional view ofFIG. 1Cwhen the memory device190is in use. In a non-limiting embodiment, the memory cell100may be referred to as a 1.5 T bitcell having a split gate architecture, with each memory device190being a non-volatile memory.

The memory device190may include a substrate102. In various non-limiting embodiments, the substrate102may include any silicon-containing substrate including, but not limited to, silicon (Si), single crystal silicon, polycrystalline Si, amorphous Si, silicon-on-nothing (SON), silicon-on-insulator (SOI) or silicon-on-replacement insulator (SRI), silicon germanium substrates, or combinations thereof, and the like. The substrate102may in addition or instead include various isolations, dopings, and/or device features. The substrate102may include other suitable elementary semiconductors, such as, for example, germanium (Ge) in crystal, a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), or combinations thereof; an alloy semiconductor including GaAsP, AlInAs, GaInAs, GaInP, GaInAsP, silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), or combinations thereof. Other types of materials as known to those skilled in the art may also be useful for forming the substrate102.

The substrate102may include a source region104and a drain region106at least partially arranged within the substrate102, and a channel region112arranged between the source region104and the drain region106. The substrate102may also include a further drain region108. A further channel region114may be arranged between the source region104and the further drain region108. The remaining portion of the substrate102may include a substrate conductivity region110. Each of the source region104, drain region106, further drain region108and substrate conductivity region110may include one or more dopants. In various non-limiting embodiments, the source region104, drain region106and further drain region108may have approximately equal doping concentrations (i.e. approximately equal concentrations of dopants). The doping concentrations of the source region104, drain region106and further drain region108may be higher than the doping concentration of the substrate conductivity region110. In various non-limiting embodiments, the doping concentration of the source region104may range from about 1E18 cm−3to about 1E20 cm−3, the doping concentration of the drain region106may range from about 1E18 cm−3to about 1E20 cm−3, the doping concentration of the further drain region108may range from about 1E18 cm−3to about 1E20 cm−3, and the doping concentration of the substrate conductivity region110may range from about 1E15 cm−3to about 1E18 cm−3. The source region104, drain region106and further drain region108may have a first conductivity type. For example, the source region104, drain region106and further drain region108may all have a p-type conductivity, in other words, include dopants having a p-type conductivity (e.g. p-type dopants). Alternatively, the source region104, drain region106and further drain region108may all have an n-type conductivity, in other words, include dopants having an n-type conductivity (e.g. n-type dopants). In a non-limiting embodiment, the substrate conductivity region110may have a second conductivity type different from the first conductivity type. For example, when the source region104, drain region106and further drain region108have a p-type conductivity, the substrate conductivity region110may have an n-type conductivity. Alternatively, when the source region104, drain region106and further drain region108have an n-type conductivity, the substrate conductivity region110may have a p-type conductivity. In one example, the implant material for the source region104, drain region106, further drain region108and substrate conductivity region110may be the same implant material, for example, an epitaxial silicon material in a non-limiting embodiment. The p-type material may be or include, but is not limited to epitaxial silicon germanium and/or the n-type material may be or include, but is not limited to doped silicon material including n-type dopants. P-type dopants can for example, include but are not limited to boron (B), aluminium (Al), indium (In) or a combination thereof, while n-type dopants can include carbon (C), phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. Other types of implant materials and dopants as known to those skilled in the art may also be useful for forming the source region104, drain region106, further drain region108and substrate conductivity region110.

In a non-limiting embodiment as shown inFIG. 1C, the memory device190may include a first segment190aand a second segment190barranged over the substrate102. The first and second segments190a,190bmay be similar to each other and may be symmetric about an axis X-X′ through a center of the memory device190. However, the memory device190need not include both the first and second segments190a,190band in alternative non-limiting embodiments, the memory device190may include only the first segment190aor only the second segment190b

The first segment190aof the memory device190may include a first gate structure116at least partially arranged over the channel region112. For example, the first gate structure116may be at least partially arranged over the channel region112and partially arranged over the source region104as shown inFIG. 1C. A first gate oxide layer118may be arranged between the first gate structure116and the substrate102. In a non-limiting embodiment as shown inFIG. 1C, the first gate structure116may be arranged over a portion of the channel region112but in other alternative non-limiting embodiments, the first gate structure116may be arranged over the entire channel region112. The first gate structure116may include a top surface116a. In various non-limiting embodiments, the top surface116aof the first gate structure116may be substantially flat. In addition, the first gate structure116may include a first side116barranged substantially perpendicular to the top surface116ato form a tip (e.g. first tip116d), and a second side116carranged substantially perpendicular to the top surface116ato form another tip (e.g. second tip116e).

The first segment190amay further include a mask120and a second gate structure124in a non-limiting embodiment. The mask120may be at least partially arranged over the top surface116aof the first gate structure116. The second gate structure124may be at least partially arranged over the mask120, and may be at least partially arranged adjacent to the first gate structure116. In a non-limiting embodiment inFIG. 1C, the first gate structure116may be arranged over a portion of the channel region112and the second gate structure124may be at least partially arranged over the channel region112. For example, the second gate structure124may include a first portion124aarranged over the mask120, a second portion124barranged adjacent to the first gate structure116and over the channel region112, and a third portion124cjoining the first and second portions124a,124b. However, in alternative non-limiting embodiments, the first gate structure116may be arranged over the entire channel region112and the second gate structure124may not overlap the channel region112. The first tip116dmay point toward the second gate structure124. The second gate structure124may be at least partially arranged over the first gate structure116such that the second gate structure124at least partially surrounds the first tip116dof the first gate structure116. For example, referring toFIG. 1C, the second gate structure124may include a first edge124dand a second edge124e. The first edge124dand the second edge124emay be substantially perpendicular to each other and the first tip116dmay be arranged between the two edges124d,124esuch that the two edges124d,124esurround the first tip116d. The second gate structure124may be spaced apart from the first gate structure116. A spacing between the first gate structure116and the second edge124eof the second gate structure124may be approximately equal to a spacing between the first gate structure116and the first edge124dof the second gate structure124.

In a non-limiting embodiment as shown inFIG. 1C, the top surface116aof the first gate structure116may include at least one tip116d/116eexposed from the mask120. For example, the mask120may include a first side120aadjacent to the second gate structure124and the first tip116dof the top surface116aof the first gate structure116may extend beyond the first side120aof the mask120in a direction toward the second gate structure124. The mask120may also include a second side120bfacing away from the second gate structure124and the second tip116eof the top surface116aof the first gate structure116may extend beyond the second side120bof the mask120. However, in alternative non-limiting embodiments, at least one side120a/120bof the mask120may be aligned with at least one side116b/116cof the first gate structure116. For example, the first side120aof the mask120and the first side116bof the first gate structure116may be aligned (although, having the first tip116dextending beyond the first side120aof the mask120may improve the erase operation of the memory device190in various non-limiting embodiments) and/or the second side120bof the mask120and the second side116cof the first gate structure116may be aligned (whether the second side120bof the mask120is aligned with the second side116cof the first gate structure116may not affect the operation of the memory device190since the erase operation may be carried out at the first tip116dinstead of the second tip116ein various non-limiting embodiments).

The first segment190amay further include spacers128,130,132. The spacers128,130may be arranged adjacent to the second gate structure124such that the second gate structure124is between the spacers128,130. The spacer132may be arranged partially adjacent to the mask120and partially adjacent to the first gate structure116. A first spacer oxide layer126may be arranged between the spacer128and the second gate structure124and a second spacer oxide layer127may be arranged between the spacer130and the second gate structure124.

Similar to the first segment190a, the second segment190bmay include a third gate structure136, a further mask140and a fourth gate structure144similar to the first gate structure116, mask120and second gate structure124, respectively. The arrangement of the third gate structure136, further mask140and fourth gate structure144may be symmetrical to the arrangement of the first gate structure116, mask120, and second gate structure124about the axis X-X′. Further, the first and second segments190a,190bmay share the same source region104. The third gate structure136may be partially arranged over the further channel region114and partially arranged over the source region104. In a non-limiting embodiment as shown inFIG. 1C, the third gate structure136may be arranged over a portion of the further channel region114(similar to the arrangement between the first gate structure116and the channel region112) and the fourth gate structure144may be arranged in a similar manner as the second gate structure124in various non-limiting embodiments. Alternatively, the third gate structure136may be arranged over the entire further channel region114and the fourth gate structure144may not overlap the further channel region114. Instead, the fourth gate structure144may be at least partially arranged over the further mask140and at least partially arranged adjacent to the third gate structure136and over the further drain region108. Similar to the first segment190a, the third gate structure136may include a substantially flat top surface136aand a first tip136dpointing toward the fourth gate structure144. The fourth gate structure144may be at least partially arranged over the third gate structure136such that the fourth gate structure144at least partially surrounds the first tip136dof the third gate structure136. Further, a second gate oxide layer138may be arranged between the third gate structure136and the substrate102. The second segment190bmay also include spacers148,150,152similar to the spacers128,130,132of the first segment190a. The spacers148,150may be arranged adjacent to the fourth gate structure144such that the fourth gate structure144is between the spacers148,150; whereas, the spacer152may be arranged partially adjacent to the further mask140and partially adjacent to the third gate structure136. A third spacer oxide layer146may be arranged between the spacer148and the fourth gate structure144, and a fourth spacer oxide layer147may be arranged between the spacer150and the fourth gate structure144.

A tunnel oxide layer122may be arranged over the substrate102, the first gate structure116, the mask120, the third gate structure136and the further mask140, such that the tunnel oxide layer122is between the second gate structure124and the first gate structure116, between the second gate structure124and the mask120, between the fourth gate structure144and the third gate structure136, and between the fourth gate structure144and the further mask140. The mask120and the first gate structure116may be separated from the spacer132via the tunnel oxide layer122. Similarly, the further mask140and the third gate structure136may be separated from the spacer152via the tunnel oxide layer122. Note that the spacers128,130,132,148,150,152, spacer oxide layers126,127,146,147and tunnel oxide layer122are not illustrated inFIG. 1AandFIG. 1Bfor simplicity.

In a non-limiting embodiment, the first and third gate structures116,136may each be referred to as a floating gate (FG), and the second and fourth gate structures124,144may each be referred to as a write line (WL). The source region104may be referred to as a source line (SL), and the drain regions106,108may each be referred to as a bit line (BL). The data retention of the memory cell100may be approximately 10 years at 125° C. and the endurance of the memory cell100may be greater than 10K. The access time of the memory cell100may be approximately 30 ns at 0.9V. The program time and erase time of the memory cell100may be approximately 10 us and 10 ms, respectively. In a non-limiting embodiment, the memory device190may be fabricated using a process simpler than the fabrication process of a prior art 1.5 T split gate flash having a control gate and an erase gate, and in this embodiment, the cell size may range from about 0.08 um2to about 0.09 um2.

The memory device190may operate by using source side injection (SSI) programming and poly-to-poly erasing, and therefore, the performance of the memory device190may be comparable to that of prior art memory devices such as a 1.5 T split gate flash with a control gate and an erase gate. For example, as compared to prior art memory devices, the memory device190may have similar low voltage (LV)/high voltage (HV) performance and less terminals. Further, the substantially flat top surfaces116a,136aof the first and third gate structures116,136can help reduce the amount of variability, read disturb, reverse tunnelling and susceptibility to retention of electrons in the memory device190. The masks120,140may facilitate the formation of the first and third gate structures116,136(FGs) during the fabrication process of the memory device190. For example, the first and third gate structures116,136may be self-aligned to the masks120,140respectively during the fabrication process. Further, the masks120,140may protect the first and third gate structures116,136during the fabrication process after forming the gate structures116,136.

FIG. 1Dshows the memory device190in use in a non-limiting embodiment.FIG. 1Dshows the flow of electrons when the source region104and the drain regions106,108have an n-type conductivity and when the substrate conductivity region110has a p-type conductivity in a non-limiting embodiment. However, it would be clear to a person skilled in the art that the direction of electron flow will change accordingly when the conductivity types of the regions104,106,108,110are reversed. Table 1 shows voltages and currents that may be provided to the source region104(SL), each of the second and fourth gate structures124,144(WL) and each of the drain regions106,108(BL) of the memory devices190to operate the memory cell100in the non-limiting embodiment illustrated inFIG. 1D. However, other voltages, currents and durations of providing these voltages and currents may be used in various alternative non-limiting embodiments.

Referring to Table 1, in a non-limiting embodiment, to program selected memory devices190of the memory cell100, a voltage of 8V may be provided to the SL of each selected memory device190, a voltage of 1.5V may be provided to each WL of each selected memory device190and a constant current of 1 uA may be provided to each BL of each selected memory device190for a duration of approximately 10 us. For each selected memory device190, because of the low positive voltage level of 1.5V provided to the second gate structure124(WL), a weakly inverted channel may be formed in the channel region112between the drain region106(BL) and the source region104(SL). Similarly, because of the low positive voltage of 1.5V provided to the fourth gate structure144, a weakly inverted channel may be formed in the further channel region114between the further drain region108(BL) and the source region104(SL). By providing a constant current 1 uA to each drain region106,108(BL), electrons may flow from each drain region106,108(BL) to the source region104(SL) through the weakly inverted channels in the channel regions112,114. Due to the difference in voltages provided to the second gate structure124(WL) and the source region104(SL) and the difference in voltages provided to the fourth gate structure144(WL) and the source region104(SL), there may be a steep potential drop along the weakly inverted channels in the channel regions112,114. When the electrons flowing through the weakly inverted channels encounter such steep potential drop, the electrons may accelerate and become heated. As a result, some electrons may be injected into each of the first and third gate structures116,136(FG) through the respective gate oxide layer118,138, as indicated by the arrows180a,180binFIG. 1D. The first and third gate structures116,136(FGs) may thus become negatively charged and the selected memory device190may be considered to be in state “0”. During the programming of the selected memory devices190, voltages of 0V, 0V, 2.5V may be provided to the SLs, WLs and BLs respectively of the remaining unselected memory devices190.

To erase selected memory devices190of the memory cell100, a voltage of 0V may be provided to the SL of each selected memory device190, a voltage of 12V may be provided to each WL of each selected memory device190and a voltage of 0V may be provided to each BL of each selected memory device190in a non-limiting embodiment. For each selected memory device190, because of the high voltage difference between the second gate structure124(WL) and the first gate structure116(FG), electrons may tunnel from the first gate structure116(FG) to the second gate structure124(WL) as indicated by the arrow182ainFIG. 1D. Similarly, because of the high voltage difference between the fourth gate structure144(WL) and the third gate structure136(FG), electrons may tunnel from the third gate structure136(FG) to the fourth gate structure144(WL) as indicated by the arrow182binFIG. 1D. The first and third gate structures116,136(FGs) may thus become positively charged (or said differently, become discharged of negatively charged electrons) and the selected memory device190may be considered to be in state “1”. The tunnelling of the electrons may be by the mechanism of Fowler-Nordheim tunnelling. Such tunnelling may be facilitated by locally-enhanced fields on the top surfaces116a,136aof the first gate structures116,136. Such locally-enhanced fields may in turn be provided by the first tips116d,136dpointing toward the second and fourth gate structures124,144respectively. During the erasing of the selected memory devices190, a voltage of 0V may be provided to each of the SLs, WLs and BLs of the remaining unselected memory devices190.

To read selected memory devices190of the memory cell100, voltages of 0V, 2.5V and 0.9V may be provided to the SLs, WLs and BLs respectively of the selected memory devices190in a non-limiting embodiment. For each selected memory device190, if the first gate structure116(FG) is positively charged (in other words, the selected memory device190is in state “1”), the portion of the channel region112directly beneath the first gate structure116(FG) may be turned on. By providing a voltage of 2.5V to the second gate structure124(WL), the portion of the channel region112directly beneath the second gate structure124(WL) may also be turned on. Thus, the entire channel region112may be turned on. Similarly, if the third gate structure136(FG) is positively charged (in other words, the selected memory device190is in state “1”), the portion of the further channel region114directly beneath the third gate structure136(FG) may be turned on. By providing a voltage of 2.5V to the fourth gate structure144(WL), the portion of the further channel region114directly beneath the fourth gate structure144(WL) may also be turned on. By providing the drain regions106,108with a voltage of 0.9V while keeping the source region104at a voltage of 0V, voltage differences between the drain regions106,108and the source region104may arise and electrical current may flow between the source region104and the drain regions106,108through the channel regions112,114. The selected memory device190may thus be read as being in the erased state (state “1”) when such electrical current is detected. On the other hand, for each selected memory device190, if the first and third gate structures116,136(FGs) are negatively charged (in other words, the selected memory device190is in state “0”), the channel regions112,114beneath the first and third gate structures116,136(FGs) may be weakly turned on or entirely shut off. Therefore, even with the voltage differences between the drain regions106,108and the source region104, there may be little or no current flowing through the channel regions112,114. The selected memory device190may thus be read as being in the programmed state (state “0”) when little or no electrical current is detected. During the reading of the selected memory devices190, a voltage of 0V may be provided to each of the SLs, WLs and BLs of the remaining unselected memory devices190.

In various non-limiting embodiments, the memory cell100including the memory devices190may be fabricated at a lower cost and with a simpler process using fewer masks, without significantly affecting the performance of the memory cell100. According to various non-limiting embodiments, a method for fabricating the memory device190may include providing the substrate102; forming the first and third gate structures116,136and the masks120,140; forming the source region104at least partially within the substrate, forming the second and fourth gate structures124,144; and forming the drain regions106,108at least partially within the substrate, with the channel regions112,114arranged between the source region104and respective drain regions106,108.

FIG. 2AtoFIG. 2Ishow cross-sectional views that illustrate a method for fabricating a semiconductor device including the memory device190, a high voltage device202and a logic transistor204according to a non-limiting embodiment. In the method shown inFIG. 2AtoFIG. 2I, the memory device190is fabricated as part of the semiconductor device. In alternative non-limiting embodiments, the semiconductor device may not include the high voltage device202or the logic transistor204and/or may include other devices to facilitate the operation of the memory device190.

Referring toFIG. 2A, the method may begin by providing the substrate102. A first oxide layer206may be formed over the substrate102. A first gate electrode layer may be formed over the substrate102, for example, over the first oxide layer206and a mask layer may be formed over the first gate electrode layer. The surface of the first gate electrode layer may be smoothed prior to forming the mask layer. Such smoothing helps form the substantially flat top surfaces116a,136aof the first and third gate structures116,136. In various non-limiting embodiments, the surface of the first gate electrode layer may be smoothed using chemical mechanical polishing/planarization (CMP) but other techniques as known to those skilled in the art may also be used. Portions of the first gate electrode layer and the mask layer may then be removed to form the first and third gate structures116,136and the masks120,140. In various non-limiting embodiments, this removal may be performed by etching the first gate electrode layer and the mask layer using a patterning mask (such as a photoresist mask) but other techniques as known to those skilled in the art may also be used. In various non-limiting embodiments, the first oxide layer206may be formed of any gate oxide material known in the art, such as high-k dielectrics or silicon dioxide, the first gate electrode layer may be formed of a conductive material, such as polysilicon, metals or alloys for example TiN, TaN, W or combinations thereof, and the mask layer may include a hard mask layer which may be formed of oxide-nitride-oxide, polysilicon oxide, nitride, or combinations thereof. However, other materials as known to those skilled in the art may also be used. Note that to avoid cluttering the figures, the surfaces116a-116c,120a-120b,136a, portions124a-124c, edges124d,124e, and the tips116d,116e,136dare not labelled inFIG. 2AtoFIG. 2I.

Referring toFIG. 2A, the method may further include forming spacers adjacent to the masks120,140. For example, a first spacer layer may be formed over the remaining portions of the mask layer and the substrate102, and then etched to form first spacers208a,208b,208cand208das shown inFIG. 2A. The etching of the first spacer layer may be performed using a dry etching technique such as reactive ion etching (RIE) but other techniques as known to those skilled in the art may also be used. The first spacers208a,208bmay be arranged adjacent to the mask120such that the mask120is between these first spacers208a,208b. Similarly, the first spacers208c,208dmay be arranged adjacent to the further mask140such that the further mask140is between these first spacers208c,208d. The first spacer layer may include a sacrificial layer formed of silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other types of dielectric materials, but other materials as known to those skilled in the art may also be used.

Referring toFIG. 2A, the method may further include forming isolation regions210at least partially within the substrate102. The method may also include forming first and second logic wells212,213of the logic transistor at least partially within the substrate102. In various non-limiting embodiments, each isolation region210may include an isolation material, such as but not limited to a gap fill oxide or nitride, or a combination of both. The logic wells212,213may include one or more dopants and may have a p-type conductivity or an n-type conductivity.

Referring toFIG. 2B, the first oxide layer206may be etched to form the gate oxide layers118,138and a second oxide layer216may be formed over the substrate102. A second spacer layer may be formed over the masks120,140, first spacers208a-208dand second oxide layer216. The second spacer layer may then be etched to form second spacers214a,214b,214c,214d. The second spacers214a,214bmay be arranged partially adjacent to the first spacers208a,208band partially adjacent to the first gate structure116, such that the first spacers208a,208band the first gate structure116are between the second spacers214a,214b. Similarly, the second spacers214c,214dmay be arranged partially adjacent to the first spacers208c,208dand partially adjacent to the third gate structure136, such that the first spacers208c,208dand the third gate structure136are between the second spacers214c,214d. The second oxide layer216may be formed of any suitable oxide material known in the art, such as but not limited to, high-k dielectrics or silicon dioxide. The second spacer layer may include a sacrificial layer formed of silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other types of dielectric materials, but other materials as known to those skilled in the art may also be used.

Referring toFIG. 2B, the method may further include forming the source region104at least partially within the substrate102. In various non-limiting embodiments, the source region104may be disposed at least partially within the substrate102by ion implantation. For example, referring toFIG. 2B, an implant mask218having an opening to expose a region of the substrate102intended for the source region104may be formed over the substrate102, and either p-type dopants (when the source region104has p-type conductivity) or n-type dopants (when the source region104has n-type conductivity) may be introduced into the exposed region of the substrate102. The implant mask218may then be removed. The implant mask218may be a photoresist mask in a non-limiting example. Other materials and techniques as known to those skilled in the art may also be useful for forming the source region104.

Referring toFIG. 2C, the method may further include removing the portion of the second oxide layer216over the region of the substrate intended for the memory device190. The method may further include forming the substrate conductivity region110which may be referred to as a memory well in a non-limiting embodiment. In various non-limiting embodiments, the substrate conductivity region110may be formed by ion implantation. For example, as shown inFIG. 2C, an implant mask234having an opening to expose the region of the substrate102intended for the memory device190may be formed over the substrate102, and either p-type dopants (when the substrate conductivity region110has p-type conductivity) or n-type dopants (when the substrate conductivity region110has n-type conductivity) may be introduced into the exposed region of the substrate102. The implant mask234may then be removed. Other materials and techniques as known to those skilled in the art may also be useful for forming the substrate conductivity region110. The method may also include forming a first high voltage device oxide layer222aand a first logic transistor oxide layer220ausing materials and techniques as known to those skilled in the art.

Referring toFIG. 2D, the method may further include removing the spacers including the first and second spacers208a-208d,214a-214d. As shown inFIG. 2D, the tunnel oxide layer122may then be deposited over the substrate102, the masks120,140and the first and third gate structures116,136. The tunnel oxide layer122may be formed of any suitable oxide material known in the art such as, but not limited to, high-k dielectrics or silicon dioxide. After the deposition of the tunnel oxide layer122, a second high voltage device oxide layer222band a second logic transistor oxide layer220bmay be formed.

FIG. 2AtoFIG. 2Dshow the formation of a first part of the logic transistor204at least partially within the substrate102and the formation of a first part of the high voltage device transistor202at least partially within the substrate102. Referring toFIG. 2E, the method may further include forming the second and fourth gate structures124,144, a second part of the logic transistor204and a second part of the high voltage device202. For example, the method may include forming a second gate electrode layer238over the substrate102. The second gate electrode layer238may be formed of a conductive material, such as polysilicon, metals or alloys for example TiN, TaN, W or combinations thereof, but other materials as known to those skilled in the art may also be used. Third and fourth logic transistor oxide layers220c,220dmay be formed over the first and second logic wells212,213respectively using materials and techniques as known to those skilled in the art.

Referring toFIG. 2F, at least a portion of the second gate electrode layer238may be removed to form the second and fourth gate structures124,144and the second parts of the logic transistor204and the high voltage device202. The second parts of the logic transistor204and the high voltage device202may include a plurality of gate structures240as shown inFIG. 2F. Removal of portions of the second gate electrode layer238may be done by etching the second gate electrode layer238. This etching may be performed using a dry etching technique such as reactive ion etching (RIE) but other techniques as known to those skilled in the art may also be used. A portion of the exposed part of the second high voltage device oxide layer222b(in other words, a portion of the part of the second high voltage device oxide layer222bnot under the gate structures240) may be removed, the entire exposed part of the third logic transistor oxide layer220c(in other words, the entire part of the third logic transistor oxide layer220cnot under the gate structures240) may be removed and a portion of the exposed part of the fourth logic transistor oxide layer220d(in other words, a portion of the part of the fourth logic transistor oxide layer220dnot under the gate structures240) may be removed.

As shown inFIG. 2AtoFIG. 2F, in various non-limiting embodiments, forming first and second spacers208a-208d,214a-214dadjacent to the masks120,140and removing them prior to forming the second and fourth gate structures124,144can help expose parts of the first and third gate structures116,136. This may in turn help to form the first tips116d,136d, such that the first tips116d,136dare surrounded by at least part of the second and fourth gate structures124,144respectively.

Referring toFIG. 2FandFIG. 2G, a first high voltage well252and a second high voltage well260may be formed at least partially within the substrate102. A first high voltage device source region254and a first high voltage device drain region256may be formed at least partially within the first high voltage well252(as shown inFIG. 2F). A second high voltage device source region262and a second high voltage device drain region264may be formed at least partially within the second high voltage well260(as shown inFIG. 2G). These may be formed using materials and techniques as known to those skilled in the art, for example, using masks258,266as shown inFIG. 2FandFIG. 2G.

Referring toFIG. 2H, the method may include forming a fifth logic transistor oxide layer220eover the first logic well212of the logic transistor204using any material or technique as known to those skilled in the art. The method may also include forming the drain region106and further drain region108of the memory device190, and the logic transistor source and drain regions272,274. In a non-limiting embodiment, the drain region106and the further drain region108of the memory device190may be formed together with the logic transistor source and drain regions272,274. For example, as shown inFIG. 2H, an implant mask276(such as, but not limited to, a photoresist mask) having openings to expose regions of the substrate102intended for the drain regions106,108of the memory device190and the logic transistor source and drain regions272,274may be formed over the substrate102. Either p-type dopants (when the drain regions106,108of the memory device190and the logic transistor source and drain regions272,274have p-type conductivity) or n-type dopants (when the drain regions106,108of the memory device190and the logic transistor source and drain regions272,274have n-type conductivity) may be introduced into the exposed regions of the substrate102. The implant mask276may then be removed. Other materials and techniques as known to those skilled in the art may also be useful for forming the drain regions106,108of the memory device190and the logic transistor source and drain regions272,274. For example, the drain regions106,108of the memory device190and the logic transistor source and drain regions272,274need not be formed simultaneously and in alternative non-limiting embodiments, the drain regions106,108of the memory device190may be formed before or after the formation of the logic transistor source and drain regions272,274.

Referring toFIG. 2I, the method may further include forming the first, second, third and fourth spacer oxide layers126,127,146,147of the memory device190, and spacer oxide layers278adjacent to the gate structures240of the high voltage device202and the logic transistor204. Spacers128,130,132,148,150,152of the memory device190and spacers280adjacent to the spacer oxide layers278of the high voltage device202and the logic transistor204may then be formed. In a non-limiting embodiment, the first, second, third and fourth spacer oxide layers126,127,146,147of the memory device190, and spacer oxide layers278adjacent to the gate structures240of the high voltage device202and the logic transistor204may be formed by forming a preliminary oxide layer over the substrate102and etching the preliminary oxide layer using for example, dry etching. Similarly, the spacers128,130,132,148,150,152of the memory device190and the spacers280of the high voltage device202and the logic transistor204may be formed by forming a spacer layer over the substrate102and etching the spacer layer using for example, dry etching. The preliminary oxide layer may be formed of silicon dioxide or other materials as known to those skilled in the art. The spacer layer may be formed of silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other types of dielectric materials, or multiple layers of insulating materials. However, other materials and techniques as known to those skilled in the art may also be used. Although not shown in the drawings, in various non-limiting embodiments, the method may further include removing all the oxide layers, except a native oxide layer having a thickness of about 10 Å.

Although not shown in the figures, the method may also further include forming additional conductive lines and contact plugs using for example, a back end of line (BEOL) process as known to those skilled in the art.

The above described order of the steps for the method is only intended to be illustrative, and the steps of the method of the present invention are not limited to the above as a specifically described order, unless otherwise specifically stated.