SEMICONDUCTOR MODULE, SEMICONDUCTOR APPARATUS, AND VEHICLE

A semiconductor module includes a laminate substrate including a first circuit board on which a semiconductor device having a plurality of upper surface electrodes including a main electrode is disposed and a second circuit board, a main terminal electrically connected to the main electrode, an auxiliary terminal electrically connected to the one of the upper surface electrodes, and a main current wiring member electrically connecting the main electrode to the main terminal. A first path through which a first control current flows and a second path through which a second control current flows are provided between the one of the plurality of upper surface electrodes and the auxiliary terminal. The first control current flows via a first auxiliary wiring, and the second control current flows via the main current wiring member, the second circuit board and a second auxiliary wiring in this order.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2021-194852, filed on Nov. 30, 2021, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a semiconductor module, a semiconductor apparatus, and a vehicle.

Description of the Related Art

A semiconductor module includes a substrate provided with a semiconductor device such as an IGBT (insulated gate bipolar transistor), a power MOSFET (metal oxide semiconductor field effect transistor), or an FWD (free wheeling diode), and is used for an inverter apparatus or the like.

In this type of semiconductor module, a semiconductor device is arranged on an upper surface of a laminate substrate, as shown in Japanese Patent Laid-Open No. 2021-068740, for example. A plurality of electrodes (including a main electrode, a gate electrode, and a sense electrode) are formed on an upper surface of the semiconductor device. For example, the main electrode of the semiconductor device is electrically connected to a main terminal for external connection via wiring members such as a circuit board and a wire. The wiring members forming a part of a current path flowing through the main terminal may be referred to as a main current wiring member, for example.

A control wiring for controlling a switching operation is connected to the semiconductor device. For example, the gate electrode of the semiconductor device is connected to an external gate terminal via a gate wiring. Further, the main electrode or the sense electrode of the semiconductor device is connected to an external auxiliary electrode via an auxiliary wiring to correspond to the gate wiring. Such a connection wiring may be referred to as a control wiring member, for example.

SUMMARY OF THE INVENTION

In a semiconductor module, a current flowing through a control wiring is smaller than that through a main current wiring. Accordingly, a relatively thin bonding wire is adopted for the control wiring. One end of the control wiring is connected to a surface of a semiconductor device that generates heat as a switching operation is performed. In this case, it is assumed that the control wiring deteriorates with a heat cycle, finally leading to disconnection. As a result, an operation of the semiconductor module may be affected. Accordingly, it has been desirable to early find the disconnection.

The present invention has been made in view of such points, and is directed to providing a semiconductor module capable of early finding disconnection of a specific wiring.

According to an aspect of the present invention, a semiconductor module includes a semiconductor device having a plurality of upper surface electrodes including at least a first main electrode formed on its upper surface, a laminate substrate in which a plurality of circuit boards including a first circuit board, on which the semiconductor device is arranged, and a second circuit board are arranged on an upper surface of an insulating plate, a first main terminal to be electrically connected to the first main electrode, an auxiliary terminal to be electrically connected to the upper surface electrode, and a main current wiring member that electrically connects the first main electrode and the first main terminal to each other, in which there is provided between the first main electrode and the first main terminal a main current path electrically connected to the first main terminal from the first main electrode via the main current wiring member and the second circuit board in this order, and there are provided between the upper surface electrode and the auxiliary terminal a first path electrically connected to the auxiliary terminal from the upper surface electrode via a first auxiliary wiring and a second path electrically connected to the auxiliary terminal from the upper surface electrode via the main current wiring member, the second circuit board, and a second auxiliary wiring in this order.

According to the present invention, disconnection of a specific wiring can be early found.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A semiconductor module and a semiconductor apparatus to which the present invention is applicable will be described below.FIG.1is a plan view of the semiconductor apparatus according to the present embodiment.FIG.2is a cross-sectional view taken along a line A-A of the semiconductor apparatus illustrated inFIG.1.FIG.3is a cross-sectional view taken along a line B-B of the semiconductor apparatus illustrated inFIG.1.FIG.4is an equivalent circuit diagram of the semiconductor apparatus according to the present embodiment.

In the following drawings, a direction in which a plurality of semiconductor devices are arranged, a direction in which paired main terminals oppose each other, a height direction of the semiconductor apparatus (a thickness direction of a substrate) are respectively defined as an X-direction, a Y-direction, and a Z-direction. X-, Y-, and Z-axes as illustrated are perpendicular to one another, to constitute a right-hand system. In some cases, the X-direction, the Y-direction, and the Z-direction may be respectively referred to as a left-right direction, a front-rear direction, and an up- down direction. The directions (front-rear, left-right, and up-down directions) are phrases used for convenience of illustration, and a correspondence with each of the X-, Y-, and Z-directions may change depending on an attachment posture of the semiconductor apparatus. For example, the heat dissipation surface side (cooler side) of the semiconductor apparatus and the opposite side thereof may be respectively referred to as the lower surface side and the upper surface side. In this specification, a planar view means a case where an upper surface or a lower surface of the semiconductor apparatus is viewed in the Z-direction. Respective aspect ratios and magnitude relationships among members in the drawings do not necessarily match one another because they are merely represented with schematic views. For convenience of illustration, a case where the magnitude relationship among members is exaggerated is also assumed.

A semiconductor apparatus100according to the present embodiment is a power conversion apparatus to be applied to an inverter of an industrial or in-vehicle motor, for example. As illustrated inFIGS.1to3, the semiconductor apparatus100is configured by arranging a semiconductor module1on an upper surface of a cooler10. In contrast with the semiconductor module1, the cooler10has any configuration.

The cooler10dissipates heat of the semiconductor module1to the exterior, and has a rectangular parallelepiped shape as a whole. Not shown in particular, the cooler10is configured by providing a plurality of fins on the lower surface side of a base plate and accommodating the fins in a water jacket. The cooler10is not limited to this, but is appropriately changeable.

The semiconductor module1is configured by arranging a laminate substrate2, a semiconductor device3, a metal wiring board4, and the like in a case5.

The laminate substrate2is composed of a DCB (direct copper bonding) substrate, an AMB (active metal brazing) substrate, or a metal base substrate, for example. The laminate substrate2is configured by laminating an insulating plate20, a heat dissipation plate21, and a plurality of circuit boards22to25, and is formed into a rectangular shape (or a square shape) in a planar view as a whole.

Specifically, the insulating plate20is formed of a plate-shaped body having an upper surface and a lower surface on its XY surface, and has a rectangular shape in a planar view. The insulating plate20may be formed of a ceramic material such as aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), aluminum oxide (Al2O3), or zirconium oxide (ZrO2).

The insulating plate20may be formed of thermosetting resin such as epoxy resin or polyimide resin or a composite material of thermosetting resin and glass or a ceramic material used as a filler. The insulating plate20may be preferably formed of a material having flexibility and containing thermosetting resin, for example. The insulating plate20may be referred to as an insulating layer or an insulating film.

The heat dissipation plate21has a predetermined thickness in a Z-direction, and has a rectangular shape in a planar view. The heat dissipation plate21is formed of a metal plate having good thermal conductivity such as copper or aluminum. The heat dissipation plate21is arranged on a lower surface of the insulating plate20. A lower surface of the heat dissipation plate21is a surface to be attached to the cooler10. The lower surface of the heat dissipation plate21also functions as a heat dissipation surface (heat dissipation region) for dissipating heat of the semiconductor module1. The heat dissipation plate21is bonded to an upper surface of the cooler10via a bonding material (not illustrated) such as a solder. The heat dissipation plate21may be arranged on the upper surface of the cooler10via a thermally conductive material such as a thermal grease or a thermal compound.

The plurality of circuit boards22to25respectively have predetermined thicknesses, and are respectively arranged at predetermined portions on the upper surface of the insulating plate20. The circuit boards are respectively formed into island shapes electrically independent of one another. For example, the circuit board22(a first circuit board) has a rectangular shape in a planar view that is long in an X-direction, and is arranged offset toward the positive side in a Y-direction on the insulating plate20.

The circuit board23(a second circuit board) has a rectangular shape (or a square shape) in a planar view, and is arranged adjacent on the negative side in the Y-direction to the circuit board22. More specifically, the circuit board23is offset toward the negative side in the Y-direction and is arranged substantially at the center in the X-direction on the insulating plate20. Although described in detail below, the circuit boards22and23constitute a part of a main current path through which a main current flows.

The circuit board24(a third circuit board) has a rectangular shape (or a square shape) in a planar view, and is arranged in a corner portion on the positive side in the X-direction and on the negative side in the Y-direction on the insulating plate20. That is, a portion having a rectangular shape of the circuit board24is arranged adjacent on the positive side in the X-direction to the circuit board23and adjacent on the negative side in the Y-direction to the circuit board22. The circuit board24has an elongated portion extending toward the negative side in the Y-direction from an end of one side of the rectangular shape. The elongated portion passes below the metal wiring board4(a connection section42), described below.

The circuit board25(a fourth circuit board) has a rectangular shape (or a square shape) in a planar view, and is arranged in a corner portion on the negative side in the X-direction and on the negative side in the Y-direction on the insulating plate20. That is, a portion having a rectangular shape of the circuit board25is arranged adjacent on the negative side in the X-direction to the circuit board23and adjacent on the negative side in the Y-direction to the circuit board22. The circuit board25has an elongated portion extending toward the positive side in the Y-direction from an end of one side of the rectangular shape. The elongated portion passes below the metal wiring board4(the connection section42), described below. The circuit board23is arranged to be interposed between the circuit boards24and25in the X-direction. The circuit boards24and25each function as a circuit board for relaying a control signal (a part of a control signal path).

Respective shapes, arrangement portions, and numbers of arrangements of the circuit boards to be thus configured are not limited to these, but are appropriately changeable. The circuit boards22to25may be each formed of a metal plate having good thermal conductivity such as copper or aluminum. Further, the circuit boards22to25may be referred to as a circuit layer or a circuit pattern.

A plurality of (two in the present embodiment) semiconductor devices3are arranged via a bonding material S such as a solder on an upper surface of the circuit board22. The semiconductor device3is formed into a rectangular shape in a planar view of a semiconductor substrate made of silicon (Si), for example.

The semiconductor device3may be composed of a wide bandgap semiconductor device (that may be referred to as a wide gap semiconductor device) formed of a wide bandgap semiconductor substrate made of silicon carbide (SiC), gallium nitride (GaN), diamond, or the like in addition to silicon, described above.

A switching element such as an IGBT (insulated gate bipolar transistor) or a power MOSFET (metal oxide semiconductor field effect transistor), or a diode such as an FWD (free wheeling diode) may be used for the semiconductor device3.

As illustrated inFIG.4, for example, the semiconductor device3may be composed of a MOSFET. A diode (an FWD, described below) may be contained in the MOSFET. In the present embodiment, an SiC-MOSFET containing a diode will be described as an example. In addition thereto, the semiconductor device3may be composed of an RC (reverse conducting)-IGBT element obtained by integrating respective functions of an IGBT (insulated gate bipolar transistor) element and an FWD (free wheeling diode) element.

The semiconductor device is not limited to this, but may be configured by combining a switching element, a diode, and the like, described above. For example, the IGBT element and the FWD element may be separately configured. An RB (reverse blocking)-IGBT or the like sufficiently resistant to a reverse bias may be used as the semiconductor device3. A shape, a number of arrangements, and an arrangement portion of the semiconductor device3are appropriately changeable.

The semiconductor device3to be thus configured has an upper surface and a lower surface on its XY surface, and electrodes are respectively formed on the upper surface and the lower surface. For example, a main electrode30aand a gate electrode31are formed on the upper surface of the semiconductor device3, and a main electrode30bis also formed on the lower surface of the semiconductor device3.

If the semiconductor device3is a MOSFET element, for example, the main electrode30amay be referred to as a source electrode, and the main electrode30bon the lower surface side may be referred to as a drain electrode. If the semiconductor device3is an IGBT element, the main electrode30amay be referred to as an emitter electrode, and the main electrode30bon the lower surface side may be referred to as a collector electrode. The gate electrode31may be referred to as a gate electrode regardless of the type of the element. An auxiliary electrode32(see a modification, described below) may be provided separately from the main electrode30aon the upper surface of the semiconductor device3. The electrodes (the main electrode30a,the gate electrode31, and the auxiliary electrode32) formed on the upper surface of the semiconductor device3may be collectively referred to as an upper surface electrode, and the electrode formed on the lower surface of the semiconductor device3may be referred to as a lower surface electrode. The gate electrode31and the auxiliary electrode32in the upper surface electrode may be each referred to as a control electrode.

In the present embodiment, the main electrode30ais an electrode through which a main current flows, and is formed into a rectangular shape in a planar view having an area representing a large part of the upper surface of the semiconductor device3. On the other hand, the gate electrode31is an electrode for controlling a gate for turning on and off a main current, is formed into a rectangular shape in a planar view sufficiently smaller than the main electrode30a,and is arranged offset toward one side of the semiconductor device3. An arrangement of the electrodes is not limited to this, but is appropriately changeable.

The semiconductor device3in the present embodiment may be a so-called vertical switching element obtained by forming functional elements such as a transistor in a thickness direction on the semiconductor substrate, or may be a horizontal switching element obtained by forming the functional elements in a planar direction.

The main electrode30aof the semiconductor device3and an upper surface of the circuit board23are electrically connected to each other by the metal wiring board4. The metal wiring board4constitutes a main current wiring member, and functions as a part of a path of a main current (a main current path) flowing in the semiconductor module1.

The metal wiring board4is composed of a plate-shaped body having an upper surface (upper main surface) and a lower surface (lower main surface). The thickness of the metal wiring board4may be not less than 0.1 nor more than 2.5 mm. The metal wiring board4is formed of a metal material such as a copper material, a copper alloy-based material, an aluminum alloy-based material, or an iron alloy-based material. The metal wiring board4is formed into a predetermined shape by press working, for example. A shape of the metal wiring board4described below merely represents an example, and is appropriately changeable. The metal wiring board4may be referred to as a lead frame. The main current wiring member is not limited to the metal wiring board4, but may be composed of a bonding wire.

The metal wiring board4according to the present embodiment has a T shape in a planar view, and is formed upon being bent a plurality of times in a side view. Specifically, the metal wiring board4includes two first bonding sections40to be each bonded to the main electrode30avia a bonding material S, a second bonding section41to be bonded to the upper surface of the circuit board23via a bonding material S, and the connection section42that connects the first bonding sections40and the second bonding section41to each other. The bonding material S may be a material having conductivity, for example, a solder or a metallic sintered material.

Each of the first bonding sections40includes a plate-shaped portion formed into a smaller rectangular shape than an outer shape of the semiconductor device3(the main electrode30a) in a planar view, having an upper surface and a lower surface on its XY surface, and having a thickness in the Z-direction. In the present embodiment, the two first bonding sections40are provided to correspond to the number of semiconductor devices3. The two first bonding sections40are arranged side by side in the X-direction, and are connected to the connection section42therebetween. Each of the first bonding sections40is arranged in the z direction to oppose the upper surface electrode (the main electrode30a) of the semiconductor device3, and is bonded thereto via a bonding material S.

The second bonding section41includes a plate-shaped portion formed into a smaller rectangular shape than an outer shape of the circuit board23in a planar view, having an upper surface and a lower surface on its XY surface, and having a thickness in the Z-direction. One end of the second bonding section41is bonded to the circuit board23, while the other end of the second bonding section41is connected to the connection sections42.

The connection section42includes two first rising portions respectively having planes on their rising YZ surfaces on the positive side in the Z-direction from edge portions of the two first bonding sections40corresponding to the number of semiconductor devices3and each having a thickness in the X-direction, a second rising portion having a plane on its rising XZ surface on the positive side in the Z-direction from an edge portion of the second bonding section41and having a thickness in the Y-direction, and a connection section having an upper surface and a lower surface on its XY surface, having a thickness in the Z-direction, and connecting the first rising portions and the second rising portion to each other.

The case5is arranged at an outer peripheral edge of the laminate substrate2. The case5is formed into a rectangular frame shape in a planar view to surround the outer periphery of the laminate substrate2, and has an opening section5ahaving a rectangular shape at its center. Specifically, the case5includes a pair of side walls50opposing each other in the X-direction and a pair of side walls51opposing each other in the Y-direction, and is formed into a rectangular frame shape by connecting their respective end portions to each other. Thus, the case5surrounds the laminate substrate2, and accommodates the semiconductor device3and the metal wiring board4inside.

The pair of side walls50rises in the Z-direction, and extends in the Y-direction. The pair of side walls51rises in the Z-direction, and extends in the X-direction. A stepped section52that falls by one step is formed inside each of the side walls50and51.

The case5is provided with main terminals60and61for main current and control terminals for control (a gate terminal62and an auxiliary terminal63, described below). The main terminals60and61are each formed of a plate-shaped elongated body, and are respectively embedded substantially at centers in the X-direction of the side walls51. The main terminals60and61are arranged to oppose each other in the Y-direction.

The main terminal60constitutes a positive electrode terminal (P terminal), and is embedded in the side wall51on the positive side in the Y-direction. One end of the main terminal60protrudes outward (toward the positive side in the Y-direction) from the side wall51. The other end of the main terminal60is electrically connected to the circuit board22inside the side wall51. Therefore, the main terminal60is electrically connected to the main electrode30b(the lower surface electrode) of the semiconductor device3via the circuit board22.

The main terminal61constitutes a negative electrode terminal (N terminal), and is embedded in the side wall51on the negative side in the Y-direction. One end of the main terminal61protrudes outward (toward the negative side in the Y-direction) from the side wall51. The other end of the main terminal61is electrically connected to the circuit board23inside the side wall51. Therefore, the main terminal61is electrically connected to the main electrode30aof the semiconductor device3via the circuit board23and the metal wiring board4.

The control terminals include the gate terminal62and the auxiliary terminal63. The gate terminal62and the auxiliary terminal63are each formed in a plate-shaped elongated body, and are embedded in the side wall51on the negative side in the Y-direction. Respective one ends of the gate terminal62and the auxiliary terminal63protrude outward (toward the negative side in the Y-direction) from the side wall51. The respective other ends of the gate terminal62and the auxiliary terminal63penetrate into the side wall51, and are respectively electrically connected to the circuit board25and the circuit board24. Therefore, the gate terminal62and the gate electrode31of the semiconductor device3are electrically connected to each other, and the auxiliary terminal63and the main electrode30aof the semiconductor device3are electrically connected to each other. The gate terminal62and the auxiliary terminal63are arranged to oppose each other in the X-direction with the main terminal61interposed therebetween.

Respective shapes, arrangement portions, and numbers of arrangements of the main terminals60and61and the control terminals are not limited to these, but are appropriately changeable. The auxiliary terminal63may be each referred to as an auxiliary emitter terminal or an auxiliary source terminal depending on the type of the semiconductor device3.

Each of the control terminals and a predetermined electrode are electrically connected to each other via a circuit board and a bonding wire (that may be collectively referred to as a control wiring). Specifically, the gate electrode31of each of the semiconductor devices3is connected to the circuit board25via a gate wiring W1. The circuit board25is connected to the gate terminal62via a gate wiring W2. That is, the gate electrode31is electrically connected to the gate terminal62via the gate wiring W1, the circuit board25, and the gate wiring W2.

Each of the first bonding sections40and the circuit board24are connected to each other by an auxiliary wiring W3. The circuit board24is connected to the auxiliary terminal63via an auxiliary wiring W4. That is, the main electrode30ais electrically connected to the first auxiliary terminal63via the first bonding section40, the auxiliary wiring W3, and the auxiliary wiring W4.

Although the auxiliary wiring W3is configured to connect the first bonding section40and the circuit board24to each other in the present embodiment, the present invention is not limited to this configuration. The auxiliary wiring W3may directly connect the main electrode30aand the circuit board24to each other. The auxiliary wiring W3may be referred to as a first auxiliary wiring.

The circuit board23and the circuit board24are connected to each other by an auxiliary wiring W5. That is, the circuit board23and the auxiliary terminal63are electrically connected to each other via the auxiliary wiring W5, the circuit board24, and the auxiliary wiring W4. An angle formed between the auxiliary wiring W5and the auxiliary wiring W3is preferably 90 degrees or less, which will be described in detail below.

A wire (bonding wire) having conductivity is used for the above-described wirings W1to W5. Any one of gold, copper, aluminum, a gold alloy, a copper alloy, and an aluminum alloy or their combination can be used as a material for the wire. A member other than the wire can also be used as the wirings. For example, a ribbon can be used for a wiring member.

Thus, in the present embodiment, there are provided between the upper surface electrode (the main electrode30a) of the semiconductor device3and the auxiliary terminal63a first path R1electrically connected to the auxiliary terminal63from the upper surface electrode (the main electrode30a) via the auxiliary wiring W3and a second path R2electrically connected to the auxiliary terminal63from the upper surface electrode (the main electrode30a) via the metal wiring board4, the second circuit board23, and the auxiliary wiring W5in this order, as illustrated inFIG.4.

A main current path R electrically connected to the main terminal61from the main terminal60via the circuit board22, the main electrodes30band30aof the semiconductor device3, the metal wiring board4, and the circuit board23in this order is provided between the main terminals60and61. A gate path electrically connected to the gate terminal62from the gate electrode31via the gate wiring W1, the circuit board25, and the gate wiring W2in this order is provided between the gate electrode31and the gate terminal62(a path from the gate electrode31to the gate terminal62inFIG.4).

An internal space defined by the frame-shaped case5is filled with sealing resin7. The sealing resin7seals the laminate substrate2, the plurality of semiconductor devices3, the metal wiring board4, the wirings W1to W5, and the like in the above-described space. That is, the case5defines (forms) an internal space accommodating the components (the laminate substrate2, the plurality of semiconductor devices3, the metal wiring board4, the wirings W1to W5, and the like). The internal space may be referred to as an internal region.

The sealing resin7is composed of thermosetting resin. The sealing resin7preferably includes at least one of epoxy, silicone, urethane, polyimide, polyamide, and polyamide-imide. Epoxy resin in which a filler is mixed, for example, is preferable in terms of insulation, heat resistance, and heat dissipation.

In a semiconductor apparatus, gate wirings are respectively connected as control wirings to gate electrodes of semiconductor devices. The gate wirings are respectively required to control switching operations of the semiconductor devices, and are respectively provided in the semiconductor devices.

Auxiliary wirings (that may be referred to as auxiliary source wirings or auxiliary emitter wirings) are respectively provided in the semiconductor devices to correspond to the gate wirings. The auxiliary wiring makes it possible to stably apply a control voltage between main electrodes (that may be referred to as “between a gate and a source” or “between a gate and an emitter”) on upper and lower surfaces of each of the semiconductor devices even if a potential difference occurs because a main current flows through a main circuit, and also makes it possible to suppress oscillation and a delay of a switching time period that can occur when an on-off timing (switching timing) of each of the semiconductor devices shifts.

The above-described auxiliary wiring is preferably arranged at a position at a potential (that may be referred to as an auxiliary source potential or an auxiliary emitter potential) relatively spaced apart from the main circuit through which the main current flows in order to separate from the main circuit. Examples of the position include the vicinity and the upper surface of the semiconductor device. On the other hand, when one end of the auxiliary wiring is connected to the vicinity and the upper surface of the semiconductor device, a bonding section of the auxiliary wiring may be broken upon early deteriorating by a heat stress and a heat cycle caused by switching of the main current. This type of control wiring has a smaller cross-sectional area than that of a wiring constituting the main circuit because current is smaller than that flowing through the main circuit. Further, the control wiring may be formed of a bonding wire having a small wire diameter, and tends to be relatively easily disconnected.

Since the above-described gate wiring is also bonded to the upper surface of the semiconductor device, there can occur a similar phenomenon to that in the auxiliary wiring. However, if the gate wiring is disconnected, a gate potential is undefined, whereby switching of the semiconductor device is not turned on.

On the other hand, when the auxiliary wiring is disconnected, respective reference potentials of a control circuit (drive circuit) and the main circuit are not determined so that an overvoltage may be applied to the gate electrode. As a result, it is assumed that the semiconductor device or the control circuit may be destroyed by the overvoltage. That is, in a power module in which a large current is handled, it can be said that an influence of the disconnection of the auxiliary wiring on the entire apparatus is larger than that of the disconnection of the gate wiring.

The present invention has occurred to the present inventors for the purpose of preventing the apparatus from being immediately destroyed even if the auxiliary wiring is disconnected and early finding the disconnection to stably stop the apparatus.

In the present invention, there are provided, in addition to a conventional auxiliary wiring (first auxiliary wiring), another auxiliary wiring (second auxiliary wiring). The first auxiliary wiring is connected to a portion relatively close to a semiconductor device (e.g., an upper surface of the semiconductor device), while the second auxiliary wiring is connected to a portion relatively spaced apart from the semiconductor device. This makes it more difficult for the second auxiliary wiring to be relatively affected by heat of the semiconductor device than the first auxiliary wiring. Therefore, the life of the second auxiliary wiring can be made longer than that of the first auxiliary wiring. Therefore, even if the first auxiliary wiring is disconnected, the second auxiliary wiring still remains. Accordingly, the apparatus is not immediately destroyed. Respective changes in signals of the first auxiliary wiring and the second auxiliary wiring make it possible to early find the disconnection of the first auxiliary wiring and to stably stop the apparatus.

Output changes before and after the first auxiliary wiring is disconnected will be described with reference toFIG.5.FIG.5is a graph illustrating output changes at the time of a switching operation. Specifically,FIG.5Aillustrates voltage changes with time, andFIG.5Billustrates current changes with time. InFIG.5A, a horizontal axis represents time, and a vertical axis represents a voltage. InFIG.5B, a horizontal axis represents time, and a vertical axis represents a current. In bothFIG.5AandFIG.5B, a solid line indicates the output change before the disconnection, and a broken line indicates the output change after the disconnection.

As illustrated inFIGS.5A and5B, before the first auxiliary wiring is disconnected, i.e., when the semiconductor module1is operating in a normal operation, if switching is turned on (or off), an output greatly changes at a predetermined timing (see a solid line portion inFIG.5).

On the other hand, when the first auxiliary wiring is disconnected, respective reference potentials of a control circuit and the semiconductor device are kept via the second auxiliary wiring. Accordingly, the control circuit or the semiconductor device can be prevented from being destroyed. A switching speed can be intentionally delayed via the second auxiliary wiring. Specifically, when the first auxiliary wiring is disconnected, a timing at which the output greatly changes because the switching is turned on (or off) shifts by ΔT, as indicated by a broken line portion inFIG.5.

Thus, if it can be detected on the apparatus side that the switching timing has been delayed by ΔT period, it can be early found that the first auxiliary wiring has been disconnected. In this case, an operation of the apparatus itself is not unstable. Thus, the apparatus can be safely stopped.

Therefore, in the present invention, if the first auxiliary wiring is disconnected because the second auxiliary wiring is provided for backing up the first auxiliary wiring, the reference potential of the circuit is ensured via the second auxiliary wiring instead. As a result, the entire apparatus can be prevented from being immediately destroyed. Further, when a switching operation via the second auxiliary wiring is delayed, the disconnection of the first auxiliary wiring can be easily detected.

A specific wiring structure in the present embodiment will be described below.FIG.6is a partial enlarged view ofFIG.1.

As illustrated inFIGS.1and6, in the present embodiment, the wiring structure includes a plurality of semiconductor devices3each having a main electrode30aand a gate electrode31formed on its upper surface, a laminate substrate2in which a plurality of circuit boards are arranged on an upper surface of an insulating plate20, a main terminal61to be electrically connected to the main electrodes30a,a gate terminal62to be electrically connected to the gate electrodes31, an auxiliary terminal63to be each electrically connected to the main electrodes30a,and a metal wiring board4that electrically connects the main electrodes30aand the main terminal61to each other.

The plurality of circuit boards include a circuit board22(a first circuit board) having the semiconductor devices3arranged on its upper surface and a circuit board23(a second circuit board) that electrically connects the main terminal61and the metal wiring board4to each other. The gate electrode31and the gate terminal62are connected to each other via a gate wiring W1. The main electrode30aor the metal wiring board4and the auxiliary terminal63are connected to each other via an auxiliary wiring W3(a first auxiliary wiring). The circuit board23and the auxiliary terminal63are connected to each other by an auxiliary wiring W5(a second auxiliary wiring).

In this case, a first connection point (P1) of the auxiliary wiring W3is in the vicinity of the semiconductor device3. On the other hand, a second connection point (P2) of the auxiliary wiring W5is positioned in the circuit board23further spaced apart from the semiconductor device3. Accordingly, the second connection point P2of the auxiliary wiring W5can be more spaced apart from the semiconductor device3than is the first connection point P1of the auxiliary wiring W3. This makes it more difficult for the auxiliary wiring W5to be affected by heat of the semiconductor device3than the auxiliary wiring W3. Further, the auxiliary wiring W3is connected to a first bonding section40in the metal wiring board4connected to the main electrode30aof the semiconductor device3. On the other hand, the auxiliary wiring W5is connected to the circuit board23. The circuit board23does not easily increase in temperature because it is cooled via the insulating plate20and a heat dissipation plate21. This makes it more difficult for the auxiliary wiring W5to be affected by heat of the semiconductor device3than the auxiliary wiring W3. As a result, the life of the auxiliary wiring W5can be made longer than that of the auxiliary wiring W3. Therefore, the auxiliary wiring W5can be effectively utilized for backing up the auxiliary wiring W3.

In the present embodiment, a circuit board24(a third circuit board) and a circuit board25(a fourth circuit board) that are independent of each other are provided. The circuit board24relays the auxiliary wiring W3and an auxiliary wiring W4between the main electrode30aand the auxiliary terminal63. The circuit board24relays the auxiliary wirings W5and W4between the circuit board23and the auxiliary terminal63. The circuit board25relays the gate wiring W1and a gate wiring W2between the gate electrode31and the gate terminal62.

Thus, when the independent circuit board24or25is set as a relay portion of wirings, a space of a connection point (bonding portion) of a wiring from the semiconductor device3can be more sufficiently ensured than when the wiring is directly connected to the control terminal (the auxiliary terminal63or the gate terminal62). As a result, the control terminal can be miniaturized to a minimum size.

The circuit boards23and24are preferably at the same potential. This configuration makes it possible to ensure respective reference potentials of a control circuit and a main circuit.

In the circuit board24, a second connection point of the auxiliary wiring W5is preferably more spaced apart from the semiconductor device3than is a first connection point of the auxiliary wiring W3. This configuration makes it possible to make the auxiliary wiring W5longer than the auxiliary wiring W3.

A current path from the semiconductor device3via the auxiliary wiring W5is preferably longer than a current path from the semiconductor device3via the auxiliary wiring W3. In other words, an impedance in the current path from the semiconductor device3via the auxiliary wiring W5is preferably larger than an impedance in the current path from the semiconductor device3via the auxiliary wiring W3. According to these configurations, a difference occurs in impedance in a predetermined current path, thereby making it possible to make a difference between switching speeds (timings) before and after the auxiliary wiring W3is disconnected. Therefore, when the difference is detected on the apparatus side, the presence or absence of the disconnection can be recognized.

As illustrated inFIG.6, in the circuit board23, the second connection point P2of the auxiliary wiring W5is preferably provided at a position shifting from a main current path R between the metal wiring board4(a second bonding section41) and the main terminal61. More specifically, the second connection point P2of the auxiliary wiring W5may be formed at a position deviating from (away from) a region connecting a bonding portion of the metal wiring board4(the second bonding section41) and a bonding portion of the main terminal61. The second connection point P2of the auxiliary wiring W5is more preferably provided at a position farther from the main terminal61than the bonding portion of the metal wiring board4(the second bonding section41). According to this configuration, the current path via the auxiliary wiring W5can be made difficult to be easily affected by a main current because it separates from the main circuit.

In the present embodiment, an angle formed between the auxiliary wiring W3and the auxiliary wiring W5is preferably 90 degrees or less in a planar view. This configuration makes it possible to make a difference between the respective current paths via the auxiliary wirings W3and W5.

One or more auxiliary wirings W3are arranged for the plurality of semiconductor devices3connected in parallel. The one auxiliary wiring W3is preferably arranged to correspond to each of the plurality of semiconductor devices connected in parallel. According to this configuration, the auxiliary wiring W3corresponding to each of the semiconductor devices3is provided, thereby making it possible to stably perform switching control.

In the present embodiment, the semiconductor device3is preferably formed of a wide bandgap semiconductor. The wide bandgap semiconductor can pass a larger current and can perform a higher temperature operation than a silicon semiconductor. This configuration more significantly exhibits an effect of the present invention in a semiconductor module that is operated with a large current and at a high temperature using the wide bandgap semiconductor.

As described above, according to the present embodiment, the second auxiliary wiring for backup is provided in addition to the first auxiliary wiring, and there occurs a difference between the switching timings before and after the first auxiliary wiring is disconnected, thereby making it possible to early find the disconnection to prevent the apparatus from being destroyed in advance.

Then, modifications will be described with reference toFIGS.7to11.FIG.7is a plan view illustrating a semiconductor apparatus according to a modification.FIG.8is an equivalent circuit diagram of the semiconductor apparatus according to the modification illustrated inFIG.7.FIG.9is a plan view illustrating a semiconductor apparatus according to another modification.FIG.10is an equivalent circuit diagram of the semiconductor apparatus according to the modification illustrated inFIG.9.FIG.11is a plan view of a semiconductor apparatus illustrating a variation ofFIG.1. In the following modification, existing components are respectively indicated by the same names and the same reference numerals, to appropriately omit description. In the modification, differences will be mainly described.

A semiconductor module1illustrated inFIGS.7and8has a rectangular shape in a planar view that is long in an X-direction. InFIG.7, a circuit board23has a U shape in a planar view, and a circuit board22is arranged inside the U shape. A notch extending in a Y-direction is formed at the center of the circuit board22. Circuit boards24and25are arranged in the notch. The circuit boards24and25each have an elongated shape extending in the Y-direction, and are arranged side by side in the X-direction. The circuit board24is positioned on the positive side in the X-direction, and the circuit board25is positioned on the negative side in the X-direction.

An auxiliary electrode32is formed separately from a main electrode30aon an upper surface of a semiconductor device3. The auxiliary electrode32may be electrically connected to the main electrode30a.InFIG.7, one metal wiring board4is provided for each semiconductor device3. A side wall50of a case is shorter than the side wall51. A gate terminal62and an auxiliary terminal63are embedded in the side wall50on the positive side in the X-direction, and are arranged side by side in the Y-direction. The auxiliary terminal63is positioned on the positive side in the Y-direction, and the gate terminal62is positioned on the negative side in the Y-direction.

InFIG.7, one end of an auxiliary wiring W3is bonded to not the main electrode30abut an upper surface of the auxiliary electrode32. In this case, the main electrode30aand the auxiliary electrode32are preferably at the same potential. In the modification illustrated inFIG.7, wirings W1to W5do not overlap one another in a planar view. In such a layout, a similar function and effect to those in the above-described embodiment can also be obtained.

In the modification illustrated inFIGS.7and8, there are provided between the upper surface electrode (the auxiliary electrode32) of the semiconductor device3and the auxiliary terminal63a first path R1electrically connected to the auxiliary terminal63from the upper surface electrode (the auxiliary electrode32) via the auxiliary wiring W3and a second path R2electrically connected to the auxiliary terminal63from the upper surface electrode (the auxiliary electrode32) via the metal wiring board4, the second circuit board23, and the auxiliary wiring W5in this order.

In the modification illustrated inFIGS.9and10, main terminals60and61are arranged side by side on a side wall51on the negative side in a Y-direction. On the other hand, another main terminal64is arranged on a side wall51on the positive side in the Y-direction. The main terminal64is connected to a circuit board22. The main terminal64may be referred to as an intermediate terminal (M terminal).

InFIG.9, two circuit boards22each having a portion extending in the Y-direction are arranged side by side in an X-direction. Two semiconductor devices3are arranged side by side in the Y-direction in each of the circuit boards22. That is, in the modification illustrated inFIG.9, the four semiconductor devices3are arranged to form a matrix of two by two. For example, the two semiconductor devices3on the positive side in the X-direction may constitute an upper arm, and the two semiconductor devices3on the negative side in the X-direction may constitute a lower arm.

A notch extending in the X-direction is formed at the center of each of the circuit boards22. Circuit boards24and25are arranged in the notch. The circuit boards24and25each have an elongated shape extending in the X-direction, and are arranged side by side in the Y-direction.

InFIG.9, control terminals (a gate terminal62and an auxiliary terminal63) are paired, and the paired two control terminals are arranged in each of the upper and lower arms. That is, the two pairs of gate terminals62and auxiliary terminals63are arranged. The gate terminals62and the auxiliary terminals63are arranged on the side wall51on the positive side in the Y-direction. The pair of control terminals on the upper arm side is arranged on the positive side in the X-direction, and the pair of control terminals is arranged on the negative side in the X-direction. The above-described wiring is connected to each of the terminals. In such a configuration, a similar function and effect to those in the above-described embodiment can also be obtained.

In the modification illustrated inFIGS.9and10, there are provided between an upper surface electrode (an auxiliary electrode32) of the semiconductor device3and the auxiliary terminal63a first path R1electrically connected to the auxiliary terminal63from the upper surface electrode (the auxiliary electrode32) via an auxiliary wiring W3and a second path R2electrically connected to the auxiliary terminal63from the upper surface electrode (the auxiliary electrode32) via a metal wiring board4, a second circuit board23, and an auxiliary wiring W5in this order.

Although a case where one end of the auxiliary wiring W3is connected to an upper surface of the first bonding section40has been described in the embodiment illustrated inFIG.1, the present invention is not limited to this configuration. As illustrated inFIG.11, for example, one end of an auxiliary wiring W3is directly connected to an upper surface of a main electrode30a.

A vehicle to which the present invention is applied will be described with reference toFIG.12.FIG.12is a plan schematic view illustrating an example of the vehicle to which the semiconductor apparatus according to the present invention is applied. A vehicle101illustrated inFIG.12includes four-wheel vehicle including four wheels102, for example. An example of the vehicle101may be an electric vehicle that drives wheels by a motor or the like or a hybrid vehicle using power of an internal combustion engine in addition to a motor.

The vehicle101includes a driving unit103that applies power to the wheels102and a control apparatus104that controls the driving unit103. The driving unit103may be composed of at least one of an engine, a motor, and a hybrid of an engine and a motor, for example.

The control apparatus104performs control (e.g., power control) of the above-described driving unit103. The control apparatus104includes the above-described semiconductor apparatus100. The semiconductor apparatus100may be configured to perform electric power control for the driving unit103.

In the above-described embodiment, the number of semiconductor devices3and an arrangement portion of each of the semiconductor devices3are not limited to those in the above-described configuration, but are appropriately changeable.

In the above-described embodiment, the number of circuit boards and a layout of the circuit boards are not limited to those in the above-described configuration, but are appropriately changeable.

Although the laminate substrate2and the semiconductor device3are components each formed into a rectangular shape or a square shape in a planar view in the above-described embodiment, the present invention is not limited to the shape. The components may be each formed into a polygonal shape other than the above-described shape.

Although the present embodiment and the modifications have been described, the present invention may be an overall or partial combination of the above-described embodiment and modifications as another embodiment.

The present embodiment is not limited to the above-described embodiment and modifications, but various changes, replacements, and modifications may be made without departing from the scope of the technical idea. Further, if the technical idea can be implemented in another method by advancement of technology or derivative other technology, the technical idea may be implemented using the method. Therefore, the claims cover all embodiments that can be included in the scope of the technical idea.

Feature points in the above-described embodiment are summarized below.

A semiconductor module according to the above-described embodiment includes at least one semiconductor device having a plurality of upper surface electrodes including at least a first main electrode formed on its upper surface, a laminate substrate in which a plurality of circuit boards including a first circuit board, on which the at least one semiconductor device is arranged, and a second circuit board are arranged on an upper surface of an insulating plate, a first main terminal to be electrically connected to the first main electrode, an auxiliary terminal to be electrically connected to the upper surface electrode, and a main current wiring member that electrically connects the first main electrode and the first main terminal to each other, in which a main current path electrically connected to the first main terminal from the first main electrode via the main current wiring member and the second circuit board in this order is provided between the first main electrode and the first main terminal, a first path electrically connected to the auxiliary terminal from the upper surface electrode via a first auxiliary wiring is provided between the upper surface electrode and the auxiliary terminal, and a second path electrically connected to the auxiliary terminal from the upper surface electrode via the main current wiring member, the second circuit board, and a second auxiliary wiring in this order.

In the semiconductor module according to the above-described embodiment, the main current wiring member is composed of a plate-shaped member made of a metal, and the first auxiliary wiring and the second auxiliary wiring are each composed of a wire made of a metal.

In the semiconductor module according to the above-described embodiment, one end of the first auxiliary wiring is connected to an upper surface of the main current wiring member arranged to oppose the first main electrode.

In the semiconductor module according to the above-described embodiment, one end of the first auxiliary wiring is connected to an upper surface of the first main electrode.

In the semiconductor module according to the above-described embodiment, the at least one semiconductor device further includes an auxiliary electrode electrically connected to the first main electrode as the upper surface electrode, and one end of the first auxiliary wiring is connected to an upper surface of the auxiliary electrode.

In the semiconductor module according to the above-described embodiment, a connection point of the second auxiliary wiring is more spaced apart from the at least one semiconductor device than a connection point of the first auxiliary wiring.

In the semiconductor module according to the above-described embodiment, the plurality of circuit boards further include a third circuit board that relays the first auxiliary wiring and/or the second auxiliary wiring to the auxiliary terminal.

In the semiconductor module according to the above-described embodiment, a second connection point of the second auxiliary wiring is more spaced apart from the at least one semiconductor device than is a first connection point of the first auxiliary wiring in the third circuit board. In other words, the first connection point P1is closer to the semiconductor device3than is the second connection point P2.

In the semiconductor module according to the above-described embodiment, the at least one semiconductor device further includes a gate electrode as the upper surface electrode, the semiconductor module further including a gate terminal to be electrically connected to the gate electrode, in which there is provided between the gate electrode and the gate terminal a gate path electrically connected to the gate terminal from the gate electrode via a gate wiring bonded to the gate electrode and a fourth circuit board further provided as one of the plurality of circuit boards in this order.

In the semiconductor module according to the above-described embodiment, the second path is longer than the first path.

In the semiconductor module according to the above-described embodiment, an impedance of the second path is larger than an impedance of the first path.

In the semiconductor module according to the above-described embodiment, a second connection point of the second auxiliary wiring is provided at a position away from a main current path between the main current wiring member and the first main terminal in the second circuit board.

In the semiconductor module according to the above-described embodiment, an angle formed between the first auxiliary wiring and the second auxiliary wiring is 90 degrees or less in a planar view.

In the semiconductor module according to the above-described embodiment, the first auxiliary wiring is arranged for each of the plurality of semiconductor devices.

In the semiconductor module according to the above-described embodiment, the at least one semiconductor device is formed of a wide bandgap semiconductor.

A semiconductor apparatus according to the above-described embodiment includes the above-described semiconductor module, and a cooler arranged on a lower surface of the laminate substrate.

A vehicle according to the above-described embodiment includes the above-described semiconductor module, or the semiconductor apparatus.

As described above, the present invention has an effect of enabling disconnection of a specific wiring to be early found, and is particularly useful in a semiconductor module and a semiconductor apparatus for industrial or electrical (in-vehicle) use.

REFERENCE SIGNS LIST