AGGREGATING CACHE MAINTENANCE INSTRUCTIONS IN PROCESSOR-BASED DEVICES

Aggregating cache maintenance instructions in processor-based devices is disclosed. In this regard, a processor-based device comprises one or more processing elements (PEs), each providing an aggregation circuit configured to detect a first cache maintenance instruction in an instruction stream. The aggregation circuit then aggregates one or more subsequent, consecutive cache maintenance instructions in the instruction stream with the first cache maintenance instruction until an end condition is detected (e.g., detection of a data synchronization barrier instruction or a cache maintenance instruction targeting a non-consecutive memory address or a different memory page than a previous cache maintenance instruction, and/or detection that an aggregation limit has been exceeded). After detecting the end condition, the aggregation circuit generates a single cache maintenance request representing the aggregated cache maintenance instructions. In this manner, multiple cache maintenance instructions may be represented by and processed as a single request, thus minimizing the impact on system performance.

BACKGROUND

I. Field of the Disclosure

The technology of the disclosure relates generally to maintenance of system caches in processor-based devices, and, in particular, to providing more efficient execution of multiple cache maintenance instructions.

Conventional processor-based devices make extensive use of system caches to store a variety of frequently used data (including, for example, previously fetched instructions, previously computed values, or copies of data stored in memory). By storing frequently used data in a system cache, a processor-based device can access the data more quickly in response to subsequent requests, thereby decreasing latency and improving overall system performance. To maintain data coherency within the processor-based device, cache maintenance operations are periodically performed on the contents of system caches using cache maintenance instructions. These cache maintenance operations may include “cleaning” the system cache by writing data to a next cache level and/or to system memory, or invalidating data in the system cache by clearing a cache line of data. Cache maintenance operations may be performed in response to modifications to system memory data, access permissions, cache policies, and/or virtual-to-physical address mappings, as non-limiting examples.

In some common use cases, multiple cache maintenance instructions may tend to be issued in “bursts,” in that the multiple cache maintenance instructions exhibit temporal locality. For example, one common use case involves performing a cache maintenance operation for each address within a translation page. Because cache maintenance instructions are typically defined as operating on a single cache line, a separate cache maintenance instruction is required for each cache line corresponding to the contents of the translation page. In this use case, the cache maintenance instructions may begin at the lowest address of the translation page, and proceed through consecutive addresses to the end of the translation page. After the last cache maintenance instruction is executed, a data synchronization barrier instruction may be issued to ensure data synchronization between different executing processes.

However, depending on cache line size and page size, hundreds or even thousands of cache maintenance instructions may need to be executed for a single translation page. If the cache maintenance instructions target memory that may be cached in system caches not owned by the processor executing the cache maintenance instructions, a snoop operation may need to be performed for all other agents that might store a copy of the targeted memory. Consequently, in processor-based devices with a large number of processors, execution of the cache maintenance instructions and associated snoop operations may consume system resources for an excessive number of processor cycles and decrease overall system performance Thus, it is desirable to provide a mechanism for more efficiently executing multiple cache maintenance instructions.

SUMMARY OF THE DISCLOSURE

Aspects according to the disclosure include aggregating cache maintenance instructions in processor-based devices. In this regard, in some aspects, a processor-based device for aggregating cache maintenance instructions is provided. The processor-based device comprises one or more processing elements (PEs), each of which includes an aggregation circuit. The aggregation circuit is configured to detect a first cache maintenance instruction in an instruction stream of the processor-based device. The aggregation circuit then aggregates one or more subsequent, consecutive cache maintenance instructions in the instruction stream with the first cache maintenance instruction until an end condition is detected. In some aspects, the end condition may include detection of a data synchronization barrier instruction, detection of a cache maintenance instruction with a non-consecutive memory address (relative to the previously detected cache maintenance instructions), detection of a cache maintenance instruction targeting a different memory page than a memory page targeted by the previously detected cache maintenance instructions, and/or detection that an aggregation limit has been exceeded. After detecting the end condition, the aggregation circuit generates a single cache maintenance request representing the aggregated cache maintenance instructions. The single cache maintenance request may then be transmitted to other PEs in aspects providing multiple interconnected PEs. In this manner, multiple cache maintenance instructions (e.g., potentially hundreds or thousands of cache maintenance instructions) may be represented by and processed as a single cache maintenance request, thus minimizing the impact on overall system performance.

In another aspect, a processor-based device for aggregating cache maintenance instructions is provided. The processor-based device comprises one or more PEs, each of which comprises an aggregation circuit. The aggregation circuit is configured to detect a first cache maintenance instruction in an instruction stream of the PE. The aggregation circuit is further configured to aggregate one or more subsequent, consecutive cache maintenance instructions in the instruction stream with the first cache maintenance instruction until an end condition is detected. The aggregation circuit is also configured to generate a single cache maintenance request representing the aggregated one or more subsequent, consecutive cache maintenance instructions.

In another aspect, a processor-based device for aggregating cache maintenance instructions is provided. The processor-based device comprises a means for detecting a first cache maintenance instruction in an instruction stream of a PE of one or more PEs of the processor-based device. The processor-based device further comprises a means for aggregating one or more subsequent, consecutive cache maintenance instructions in the instruction stream with the first cache maintenance instruction until an end condition is detected. The processor-based device also comprises a means for generating a single cache maintenance request representing the aggregated one or more subsequent, consecutive cache maintenance instructions.

In another aspect, a method for aggregating cache maintenance instructions is provided. The method comprises detecting, by an aggregation circuit of a PE of one or more PEs of a processor-based device, a first cache maintenance instruction in an instruction stream of the PE. The method further comprises aggregating one or more subsequent, consecutive cache maintenance instructions in the instruction stream with the first cache maintenance instruction until an end condition is detected. The method also comprises generating a single cache maintenance request representing the aggregated one or more subsequent, consecutive cache maintenance instructions.

DETAILED DESCRIPTION

Aspects disclosed in the detailed description include aggregating cache maintenance instructions in processor-based devices. In this regard,FIG. 1illustrates an exemplary processor-based device100that provides multiple processing elements (PEs)102(0)-102(P) for concurrent processing of executable instructions. Each of the PEs102(0)-102(P) may comprise a central processing unit (CPU) having one or more processor cores, or an individual processor core comprising a logical execution unit and associated caches and functional units. In the example ofFIG. 1, the PEs102(0)-102(P) are linked via an interconnect bus104, over which inter-processor communications (such as snoop requests and snoop responses, as non-limiting examples) are communicated. Each of the PEs102(0)-102(P) is configured to execute a corresponding instruction stream106(0)-106(P) comprising computer-executable instructions (not shown). It is to be understood that some aspects of the processor-based device100may comprise a single PE102rather than the multiple PEs102(0)-102(P) shown inFIG. 1.

The PEs102(0)-102(P) ofFIG. 1are each associated with a corresponding memory108(0)-108(P) and one or more caches110(0)-110(P). Each memory108(0)-108(P) provides data storage functionality for the associated PE102(0)-102(P), and may be made up of double data rate (DDR) synchronous dynamic random access memory (SDRAM), as a non-limiting example. The one or more caches110(0)-110(P) are configured to cache frequently accessed data for the associated PE102(0)-102(P) in a plurality of cache lines (not shown), and may comprise one or more of a Level 1 (L1) cache, a Level 2 (L2) cache, and/or a Level 3 (L3) cache, as non-limiting examples.

The processor-based device100ofFIG. 1may encompass any one of known digital logic elements, semiconductor circuits, processing cores, and/or memory structures, among other elements, or combinations thereof. Aspects described herein are not restricted to any particular arrangement of elements, and the disclosed techniques may be easily extended to various structures and layouts on semiconductor sockets or packages. It is to be understood that some aspects of the processor-based device100may include elements in addition to those illustrated inFIG. 1. For example, some aspects may include more or fewer PEs102(0)-102(P), more or fewer memory108(0)-108(P), and/or more or fewer caches110(0)-110(P) than illustrated inFIG. 1.

To maintain data coherency, each of the PEs102(0)-102(P) may execute cache maintenance instructions (not shown) within the corresponding instruction streams106(0)-106(P) to clean and/or invalidate cache lines of the caches110(0)-110(P). For example, the PEs102(0)-102(P) may execute cache maintenance instructions in response to modifications to data stored in the memory108(0)-108(P), or changes to access permissions, cache policies, and/or virtual-to-physical address mappings, as non-limiting examples. However, depending on cache line size and page size, some common use cases (such as performing cache maintenance operations on each cache line of a translation page) may require hundreds or even thousands of cache maintenance instructions to be executed. This, in turn, may require additional snoop operations to be performed by multiple PEs102(0)-102(P) that may be caching a copy of the targeted memory. As a result, execution of the cache maintenance instructions and associated snoop operations may consume system resources and decrease overall system performance.

In this regard, the PEs102(0)-102(P) each provide an aggregation circuit112(0)-112(P) to aggregate cache maintenance instructions into a single cache maintenance request to facilitate efficient system-wide cache maintenance. In some aspects, the aggregation circuit112(0)-112(P) for each of the PEs102(0)-102(P) may be integrated into an execution pipeline (not shown) of the PE102(0)-102(P), and thus may be operative to detect a cache maintenance instruction prior to execution of the cache maintenance instruction. As discussed in greater detail with respect toFIG. 2, each of the PEs102(0)-102(P), using the corresponding aggregation circuit112(0)-112(P), is configured to detect a first cache maintenance instruction within the corresponding instruction streams106(0)-106(P), and then begin aggregating subsequent cache maintenance instructions rather than continuing to process the cache maintenance instructions for execution. In some aspects, the cache maintenance instructions that are aggregated may comprise cache maintenance instructions that target the same memory page and/or a contiguous range of memory addresses.

Each aggregation circuit112(0)-112(P) of the PEs102(0)-102(P) continues to aggregate cache maintenance instructions until an end condition is encountered. The end condition, according to some aspects, may include detection of a data synchronization barrier instruction within the corresponding instruction stream106(0)-106(P). Some aspects may provide that the end condition includes detection of a cache maintenance instruction that targets a non-consecutive memory address (i.e., a memory address that is not consecutive with respect to the previous aggregated cache maintenance instruction), or a memory address corresponding to a different memory page than the previous aggregated cache maintenance instruction. According to some aspects, the end condition may include detecting that an aggregation limit has been exceeded. For example, the aggregation limit may specify a maximum number of cache maintenance instructions that can be aggregated at one time, or may represent a limit that is to be applied to the memory address (e.g., a boundary between memory pages).

After detecting the end condition, the aggregation circuit112(0)-112(P) for the executing PE102(0)-102(P) generates a single cache maintenance request, representing the aggregated cache maintenance instructions. As a non-limiting example, in multi-processor systems, the executing PE102(0) may transmit the single cache maintenance request to the other PEs102(0)-102(P). Upon receiving the single cache maintenance request, each of the receiving PEs102(0)-102(P) performs its own filtering of the single cache maintenance request to identify any memory addresses corresponding to the receiving PE102(0)-102(P), and performs a cache maintenance operation on each identified memory address. It is to be understood that the process of aggregating and de-aggregating cache maintenance instructions is transparent to any executing software.

FIG. 2illustrates in greater detail the exemplary aggregation of cache maintenance instructions in the instruction stream106(0) of the PE102(0) ofFIG. 1. It is to be understood that the PE102(0) is discussed as an example, and that each of the PEs102(0)-102(P) may be configured to perform aggregation in the same manner as the PE102(0). In the example ofFIG. 2, the instruction stream106(0) of the PE102(0) includes cache maintenance instructions200(0)-200(C), each of which represents a cache maintenance operation (e.g., cleaning, invalidating, etc.) to be performed. As the PE102(0) operates on the instruction stream106(0), the aggregation circuit112(0) detects the first cache maintenance instruction200(0). In some aspects, the aggregation circuit112(0) may be configured to detect any of a specified plurality of instructions related to cache maintenance. Upon detecting the first cache maintenance instruction200(0), the aggregation circuit112(0) prevents execution of the cache maintenance instruction200(0), and begins the process of seeking out subsequent instructions for aggregation.

For each subsequently detected cache maintenance instruction200(1),200(C), the aggregation circuit112(0) of the PE102(0) determines whether an end condition has been encountered. In some aspects, a data synchronization barrier instruction in the instruction stream106(0), such as a data synchronization barrier instruction204, may mark the end of the group of cache maintenance instructions200(0)-200(C) to be aggregated. Some aspects may provide that the end condition is triggered by the aggregation circuit112(0) detecting that a cache maintenance instruction, such as the cache maintenance instruction200(C), targets a memory address that is non-consecutive with respect to the memory addresses targeted by the previous cache maintenance instruction200(1), or targets a memory address corresponding to a different memory page than that targeted by the previous cache maintenance instructions200(0),200(1). According to some aspects, the aggregation circuit112(0) may determine whether an aggregation limit206has been exceeded. For example, the aggregation circuit112(0) may maintain a count (not shown) of the cache maintenance instructions200(0)-200(C) that have been aggregated, and may trigger an end condition when the count exceeds a value indicated by the aggregation limit206. In such aspects, the aggregation limit206may represent the maximum number of cache maintenance instructions200(0)-200(C) to aggregate into a single cache maintenance request202, and in some aspects may correspond to a maximum number of cache lines for a single page of memory. Some aspects may provide that the aggregation limit206may represent a limit, such as a boundary between memory pages, to be applied to each memory address targeted by the cache maintenance instructions200(0)-200(C).

Once an end condition is encountered, the aggregation circuit112(0) of the PE102(0) generates a single cache maintenance request202to represent the aggregated cache maintenance instructions200(0)-200(C). In some aspects, the single cache maintenance request202indicates the type of cache maintenance operation to be performed (e.g., cleaning, invalidation, etc.), and further indicates a starting memory address208corresponding to the memory address targeted by the first detected cache maintenance instruction200(0). In some aspects, the single cache maintenance request202further includes a byte count210that indicates a number of bytes on which to perform the cache maintenance operation. Alternatively, some aspects may provide an ending memory address212corresponding to the memory address targeted by the last detected cache maintenance instruction200(C). In such aspects, the starting memory address208and the ending memory address212together define a memory address range on which cache maintenance operations are to be performed.

In some aspects providing multiple processors, the PE102(0) may then transmit the single cache maintenance request202to the other PEs102(1)-102(P), shown inFIG. 1. Upon receiving the single cache maintenance request202, each of the other PEs102(1)-102(P) performs filtering operations to determine whether the single cache maintenance request202is directed to memory addresses corresponding to the PE102(1)-102(P), and performs cache maintenance operations accordingly.

To illustrate exemplary operations of the processor-based device100ofFIGS. 1 and 2for aggregating cache maintenance instructions,FIG. 3is provided. For the sake of clarity, elements ofFIGS. 1 and 2are referenced in describingFIG. 3. InFIG. 3, operations begin with the aggregation circuit112(0) of the PE102(0) of the one or more PEs102(0)-102(P) detecting a first cache maintenance instruction200(0) in an instruction stream106(0) of the PE102(0) (block300). In this regard, the aggregation circuit112(0) may be referred to herein as “a means for detecting a first cache maintenance instruction in an instruction stream of a PE of one or more PEs of the processor-based device.”

The aggregation circuit112(0) next aggregates one or more subsequent, consecutive cache maintenance instructions200(1)-200(C) in the instruction stream106(0) with the first cache maintenance instruction200(0) until an end condition is detected (block302). Accordingly, the aggregation circuit112(0) may be referred to herein as “a means for aggregating one or more subsequent, consecutive cache maintenance instructions in the instruction stream with the first cache maintenance instruction until an end condition is detected.” As noted above, the end condition may comprise detection of the data synchronization barrier instruction204, detection of a cache maintenance instruction200(C) targeting a non-consecutive memory address or a memory address corresponding to a different memory page, or detection of the aggregation limit206being exceeded. The aggregation circuit112(0) then generates a single cache maintenance request202representing the aggregated cache maintenance instructions200(0)-200(C) (block304). The aggregation circuit112(0) thus may be referred to herein as “a means for generating a single cache maintenance request representing the aggregated one or more subsequent, consecutive cache maintenance instructions.”

In aspects providing a plurality of PEs102(0)-102(P), a first PE, such as the PE102(0), next may transmit the single cache maintenance request202to a second PE, such as one of the PEs102(1)-102(P) (block306). In this regard, the first PE102(0) may be referred to herein as “a means for transmitting the single cache maintenance request from a first PE of the one or more PEs to a second PE of the one or more PEs.” In response to receiving the single cache maintenance request202, the second PE102(1)-102(P) may identify one or more memory addresses corresponding to the second PE102(1)-102(P) based on the single cache maintenance request202(block308). Accordingly, the second PE102(1)-102(P) may be referred to herein as “a means for identifying, based on the single cache maintenance request, one or more memory addresses corresponding to the second PE, responsive to the second PE receiving the single cache maintenance request from the first PE.” The second PE102(1)-102(P) may then perform a cache maintenance operation on each memory address of the one or more memory addresses corresponding to the second PE102(1)-102(P) (block310). The second PE102(1)-102(P) thus may be referred to herein as “a means for performing a cache maintenance operation on each memory address of the one or more memory addresses corresponding to the second PE.”

Aggregating cache maintenance instructions in processor-based devices according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

In this regard,FIG. 4illustrates an example of a processor-based device400for aggregating cache maintenance instructions. The processor-based device400, which corresponds to the processor-based device100ofFIGS. 1 and 2, includes one or more CPUs402, each including one or more processors404. The CPU(s)402may have cache memory406coupled to the processor(s)404for rapid access to temporarily stored data, and in some aspects may correspond to the PEs102(0)-102(P) ofFIG. 1. The CPU(s)402is coupled to a system bus408and can intercouple master and slave devices included in the processor-based device400. As is well known, the CPU(s)402communicates with these other devices by exchanging address, control, and data information over the system bus408. For example, the CPU(s)402can communicate bus transaction requests to a memory controller410as an example of a slave device.

Other master and slave devices can be connected to the system bus408. As illustrated inFIG. 4, these devices can include a memory system412, one or more input devices414, one or more output devices416, one or more network interface devices418, and one or more display controllers420, as examples. The input device(s)414can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s)416can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s)418can be any devices configured to allow exchange of data to and from a network422. The network422can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s)418can be configured to support any type of communications protocol desired. The memory system412can include one or more memory units424(0)-424(N).

The CPU(s)402may also be configured to access the display controller(s)420over the system bus408to control information sent to one or more displays426. The display controller(s)420sends information to the display(s)426to be displayed via one or more video processors428, which process the information to be displayed into a format suitable for the display(s)426. The display(s)426can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.