HIGH VOLTAGE FINGER LAYOUT TRANSISTOR

An integrated circuit, including a source region, a drain region, a channel region between the source region and the drain region, and a gate for inducing a conductive path through the channel region. The integrated circuit also includes structure, proximate a curved length of the gate, for inhibiting current flow along a portion of the channel region.

CROSS-REFERENCE TO RELATED APPLICATION

Not applicable.

BACKGROUND

The example embodiments relate to semiconductor integrated circuit (IC) fabrication, for example with respect to high voltage transistors.

One or more high voltage (HV) transistors may be formed as a discrete IC or as part of a more complex circuit layout within an IC. An HV transistor application is configured to receive or operate at a voltage beyond a relatively high voltage threshold, where for example an 80 volt or higher application is typically considered high voltage in contemporary devices. Such devices may be used, particularly as drivers and amplifiers, in various systems, with examples including motors, displays, and certain higher-power equipment. For such usages, the transistor is specified to have a safe operating area (SOA), which is typically described in one or more current/voltage plots, each of which provides the conditions, including duration, over which the transistor can operate without incurring fault or damage.

HV transistors may be formed in various layout configurations, typically with consideration to transistor operating voltage and size (including area). One approach is a multi-finger layout, in which the transistor gate includes at least two typically-parallel paths, sometimes referred to as fingers, which are electrically connected to one another. The plural paths increase total gate width in a same space where shorter total gate width would be achieved in a conventional (single finger) gate topology. The plural paths also permit sharing of either source and/or diffusion regions, that are between two parallel gate portions.

While the preceding has implementation in various prior art devices, this document provides example embodiments that may improve on certain of the above concepts, as detailed below.

SUMMARY

An integrated circuit, including a source region, a drain region, a channel region between the source region and the drain region, and a gate for inducing a conductive path through the channel region. The integrated circuit also includes structure, proximate a curved length of the gate, for inhibiting current flow along a portion of the channel region.

Other aspects are also described and claimed.

DETAILED DESCRIPTION

FIG.1is a top view of an IC100. The IC100includes a finger layout transistor (FLT)102, which may be a standalone discrete device, or may be included in the IC100as part of a multi-component device that includes plural electronic circuit elements. The FLT102as illustrated inFIG.1has some attributes known in the art, but is improved as further detailed in this document.

In an example embodiment, the FLT102is formed in a semiconductor substrate104, which may be silicon, by way of example. The FLT102includes a gate106, which is formed generally of a conductive material, for example as doped polysilicon or metal (which can be preceded by a sacrificial polysilicon member). The gate106includes, along its layout path, four generally parallel gate portions108pgp_a,108pgp_b,108pgp_c, and108pgp_d. Additionally, the gate106includes, along its layout path, four curved portions110cp_a,110cp_b,110cp_c, and110cp_d, and a linear portion1121pbetween the curved portions110cp_cand110cp_d. Further, the curved portion110cp_cis between the parallel gate portion108pgp_aand the linear portion1121p, and the curved portion110cp_dis between the parallel gate portion108pgp_dand the linear portion1121p. In an example embodiment, each of the curved portions110cp_cand110cp_dhas a same radius, r1, for example with 5 μm≤r1≤200 μm. Further, in the example embodiment, each of the curved portions110cp_cand110cp_dhas the radius, r1, over a curve distance cd1 of approximately 90 degrees. The curved portion110cp_ais also aligned between the parallel gate portions108pgp_aand108pgp_b, and the curved portion110cp_bis aligned between the parallel gate portions108pgp_cand108pgp_d. In an example embodiment, each of the curved portions110cp_aand110cp_bhas a same radius, r2, for example with 5 μm≤r1≤200 μm. In a particular example given these ranges, as shown in the example embodiment, r2<r1. Further, in the example embodiment, each of the curved portions110cp_aand110cp_bhas the radius, r2, over a curve distance cd2 of approximately 180 degrees, that is, cd2>cd1.

The FLT102also includes a source region114and a drain region116. Generally, from a top perspective, the source region114is outwardly positioned relative to the gate106, and the source region114generally surrounds the gate106. The drain region116is inwardly positioned relative to the gate106, so the source region114also generally surrounds the drain region116. Further, because the gate106includes parallel portions and, in some locations, a generally serpentine pattern, the source region114includes symmetrically positioned portions as source fingers114_SF and the drain region116includes symmetrically positioned portions as drain fingers116_DF, with the source fingers114_SF and the drain fingers116_DF generally interdigitated with respect to one another. The source and drain fingers114_SF and116_DF are shown having lengths by example and not necessarily to scale, as they may be considerably longer in implementation, relative to the other illustrated structures. In an example embodiment and described below, the drain region116also may include a separate drift region (see208,FIG.2), as may be implemented in laterally diffused metal oxide semiconductor (LDMOS) transistor. Further, the source region114and the drain region116typically include a same dopant conductivity type, for example, n-type dopant for an N-type transistor (or, p-type for a P-type transistor), with a transistor channel region between them and below the gate106(and below a gate insulator (for example, see108gi_a,FIG.2), also below the gate106).

FIG.2is a cross-section of theFIG.1FLT102. The cross-section includes the parallel gate portions108pgp_a,108pgp_b,108pgp_c, and108pgp_dpositioned above an upper surface104US of the semiconductor substrate104, each having below and between it and the upper surface104US a respective gate insulator108gi_a,108gi_b,108gi_c, and108gi_d. In an example embodiment, the FLT102implements an LDMOS configuration. Accordingly, each instance of the source region114is a heavy doped (e.g., n+) source region202that diffuses laterally under one or more respective gate portions and that also is formed within a lighter and complementary conductivity type (e.g., p) region204. Further, each instance of the drain region116is a heavy doped drain region206that functions as the transistor drain, and of the same dopant type (e.g., n+) as a heavy doped source region202of the source region114. Each heavy doped drain region206is formed within, or electrically coupled to, a drift region208that is of a same conductivity type (e.g., n type) as the heavy doped source region202but with a lesser dopant concentration (e.g., n−), and a portion of each drift region208diffuses laterally under one or more respective gate portions. The entirety of the above-described doped regions may be formed in a well210having the same conductivity type (e.g., n type), albeit at a different dopant concentration, as the heavy doped source region202and the heavy doped drain region206. Further, the well210is formed in the semiconductor substrate104, which has a complementary (e.g., p type) conductivity type to the well210.

Given theFIGS.1and2illustration and description, the operation of the FLT102will be readily understood by one skilled in the art. For example, a high voltage (e.g., 80 volts or higher) can be coupled via a contact (not separately shown) to the heavy doped drain regions206serving as the drain region116, while a lower voltage (e.g., ground) is connected to the heavy doped source region202. Further, a control voltage is then applied to the gate106, thereby coupling the control voltage to the parallel gate portions108pgp_a,108pgp_b,108pgp_c, and108pgp_d. For an N-type transistor as shown, when a positive potential is applied to the gate, the potential attracts electrons into any p-type material beneath the gate and the corresponding gate insulator, thereby inducing an n-type channel in the p-type material. In this regard,FIG.2further indicates a channel area212corresponding to the general location in each complementary conductivity type region204where the n-type channel may be so induced. Electrons flowing through the channel area212can then pass to the adjoining opposite conductivity type (e.g., n type) region of the well210and continue toward the drain region206, while in the LDMOS example also dissipating energy through an adjacent one of the drift regions208.

FIG.3illustrates additional aspects of theFIG.1IC100. InFIG.3, the FLT102includes a first channel inhibiting region300_athat is proximate the curved portion110cp_aand a second channel inhibiting region300_bthat is proximate the curved portion110cp_b. Each of the first and second channel inhibiting regions300_aand300_bis shown with dashed lines, as each is structural implementation, in the general vicinity within the respective dashed lines, to inhibit (reduce or eliminate) channel current conduction along theFIG.2channel area212, to the extent the area212is within theFIG.3illustrated dashed lines. Accordingly, for the first channel inhibiting region300_a, even when an enabling voltage is applied to the gate106, the first channel inhibiting region300_ainhibits channel current flow between the source region114and the drain region116, in the vicinity of the curved portion110cp_a. Similarly, the second channel inhibiting region300_b, even when an enabling voltage is applied to the gate106, inhibits channel current flow between the source region114and the drain region116, in the vicinity of the curved portion110cp_b. Accordingly, by reducing or eliminating current in the first and second channel inhibiting regions300_aand300_b, then potential attributes of such current, for example in areas of relatively small radii, are reduced. These reduced attributes could otherwise include, for example, higher electric fields, current crowding, and impact ionization. Reducing these attributes likewise reduces the potential complexities or even device failures that otherwise may arise. Notably, however, when an enabling voltage is applied to the gate106, the lack of the same structural implementation in locations outside of the first and second channel inhibiting regions300_aand300_bthus enables channel current to otherwise flow in theFIG.2channel area212, so that at least a majority of the area of the FLT102operates to conduct current at such time. For instance, in example embodiments, the total length of the gate106having an accompanying respective inhibiting region (e.g., first and second channel inhibiting regions300_aand300_b, or others) is less than ten percent of the entire length of the gate106. Different embodiments are contemplated, with respectively different structural implementations for the first and second channel inhibiting regions300_aand300_b, with certain examples provided below.

FIG.4is a plan view of an implementation of theFIG.1IC100, shown inFIG.4as an IC400with an FLT102_1. Generally, the FLT102_1embodies the earlier discussion of theFIG.3FLT102, with a particular structural implementation to serve as the first and second channel inhibiting regions300_aand300_b. Specifically, along the path of the gate106, two discontinuities402and404are formed in the first channel inhibiting region300_a, and similarly along the path of the gate106, two discontinuities406and408are formed in the second channel inhibiting region300_b. Each of the discontinuities402,404,406, and408, is a location where the conductor of the gate106is not formed, for example by making the area of each discontinuity during the formation of the gate structure. Without forming the gate106in a location of a discontinuity, the conductive path of the gate106is interrupted. Accordingly, the curved portion110cp_aremains within the first channel inhibiting region300_a, but it is electrically isolated from the remaining majority length of the gate106as it exists in the rest of the FLT102_1(other than in the second channel inhibiting region300_b, which also is isolated in the a comparable manner). Similarly, the curved portion110cp_bremains within the second channel inhibiting region300_b, but it is electrically isolated from the remaining majority length of the gate106as it exists in the rest of the FLT102_1(other than in the also-isolated first channel inhibiting region300_a). Also in an example embodiment, since theFIG.4curved portions110cp_aand110cp_bare isolated from the remainder of the gate106, each may be electrically biased differently than the remainder of the gate106, for example those portions may be connected to ground. Accordingly, when an enabling potential is applied to the gate106, that potential is not connected to the curved portions110cp_aand110cp_b, so channel current will not flow in the area of the first and second channel inhibiting regions300_aand300_b.

FIG.5illustrates a plan view of another implementation of theFIG.1IC100, shown as an IC500and with an FLT102_2that implements different structure to serve as theFIG.3first and second channel inhibiting regions300_aand300_b. In the FLT102_2, each of the first and second channel inhibiting regions300_aand300_bincludes a respective channel blocking insulator502_aand502_b, as both a physical and electrical barrier adjacent the proximate one of the curved portions110cp_aand110cp_b. In an example embodiment, each of the first and second channel inhibiting regions300_aand300_bis aligned generally parallel to and approximately the same curved length as the respective one of the curved portions110cp_aand110cp_b. As further illustration,FIG.6is a cross-sectional diagram along theFIG.5line6-6, thereby including a cross-section across the channel block insulator502_a. In theFIG.6example, the channel block insulator502_ais formed, for example, using shallow trench isolation (STI), between the heavy doped drain region206and the channel area212. Further, the depth of the channel block insulator502_a, into the semiconductor substrate104(or, in the example, into the well210), is selected to impede current flow, for example extending at least as deep as the heavy doped source region202. Accordingly, channel current is impeded from flowing between the source region114and the drain region116, and more particularly in the area of the first channel inhibiting region300_a. Further, and as shown inFIG.5, the same effect is achieved by the channel block insulator502_bwith respect to the second channel inhibiting region300_b. Lastly, locating the channel block insulators502_aand502_bon the drain side of the gate106may be preferred, as compared to the source side, due to the proximity or overlap of the gate106to the source region114.

FIG.7illustrates a plan view of another implementation of theFIG.1IC100, shown as an IC700and with an FLT102_3that implements different structure to serve as theFIG.3first and second channel inhibiting regions300_aand300_b. In the FLT102_3, each of the first and second channel inhibiting regions300_aand300_bare implemented by inhibiting the source region at least in those areas. As a first example, the inhibition can be achieved by masking a targeted area702, so as to inhibit the formation of at least part of the source region114(which inhibited part could include the source contact, not shown), as shown inFIG.7by shading and the corresponding legend. In an example embodiment, the targeted area702includes, but can extend beyond, each of the first and second channel inhibiting regions300_aand300_b, so as to at least be formed proximate the curved portions110cp_aand110cp_b. As further illustration,FIG.8is a cross-sectional diagram along theFIG.7line8-8, thereby including a cross-section across the targeted area702. InFIG.8, and only for illustration purposes, the heavy doped source region202is shown in phantom, that is, with a dashed outline and the masking pattern fromFIG.7, to demonstrate that the heavy doped source region202is prevented from forming in the area shown, while it is formed in the remainder of the area of the source region114, as shown in theFIG.7plan view. Accordingly, in the area of the first channel inhibiting region300_a, and where the heavy doped source region202is not formed, the remaining structure associated with the source is the complementary conductivity type (e.g., p) region204, which in an N-type transistor will not source channel current between the source region114and the drain region116. Further, and as shown inFIG.7, the same effect is achieved by the targeted area702with respect to the second channel inhibiting region300_b. Further, as a second example, either in addition to or instead of masking, some other source blocking effect may be implemented in the targeted area702, for example by an intended damaging implant (e.g., argon) in the targeted area702, so as to diminish or destroy the conductive operability of the source region114in the targeted area702. In either event, outside of the targeted area702, the majority of the drain region116remains surrounded by a functionally-operable source region114, that is, so that conduction may occur between the source region114and the drain region116, outside of the targeted area702.

FIG.9is a flow diagram of an example embodiment method900for forming an FLT102_x. The method900begins in a step902, in which the semiconductor substrate104(FIGS.1-8) is obtained. The semiconductor substrate may be a portion of a semiconductor wafer which, at this stage, will have incurred some earlier processing steps. Such processing steps may include, for example, wafer cleaning (e.g., chemical and/or mechanical), isolation, and possible formation of structures or regions below the upper surface104US. Next, the method900continues from the step902to a step904.

In the step904, portions of the FLT102_xare formed, which can include some or all of its gate106, source region114, and drain region116. These portions can be formed using various different technologies, and in various shapes and dimensions, including, for example, with a gate path that includes plural parallel portions in a multi-finger structure, and/or with LDMOS technology. Next, the method900continues from the step904to a step906.

In the step906, one or more channel inhibiting regions are formed proximate a portion or portions of the path of the gate106. Each channel inhibiting region may be formed using various example embodiments. For example, a channel inhibiting region may be formed by: (i) including at least two discontinuities along the path of the gate conductor, thereby forming an isolated portion of the gate conductor from the remainder of the gate path; (ii) including a blocking insulator, such as an STI, below the substrate upper surface104US and blocking a conductive path between the source region114and the drain region116; or (iii) selectively inhibiting the formation of a portion of either the source and drain, leaving behind a structure that is not conducive to providing a current path to the other of the source and the drain. Next, the method900continues from the step906to a step908.

In the step908and following, formation processes are performed beyond those described above, so as to complete any circuit features, connections, and the like for ICs of the semiconductor wafer. In this regard, silicides may be formed, as may additional layers and/or other devices for each IC on the wafer. Thereafter, each IC formed on the wafer can be separated from the wafer, packaged, tested, and ultimately if satisfactory, approved for distribution, such as by sale and delivery to a customer.

From the above, one skilled in the art should appreciate that example embodiments are provided for IC semiconductor fabrication, for example with respect to an IC that includes a HV transistor (or multiple HV transistors). Such embodiments provide various benefits, some of which are described above and including still others. For example, embodiments may implement a transistor with parallel gate portions, so as to provide an effective longer transistor gate within a relatively small area. As another example, such a transistor can be operated with reduced electric field and current density in areas where the gate path has a relatively small radius, thereby reducing the chance of failure in such areas and correspondingly improving SOA. As another example, modifications to the embodiments described are also contemplated. For example, whileFIGS.3-5and7illustrate channel inhibiting regions proximate gate curves of radius r2 and curve distance cd2, similar channel inhibiting regions may be used for either larger radii (e.g., r1) and/or shorter curve distance (e.g., cd1), including for example, proximate the curved portions110cp_cand110cp_d. As another example, various conductivity types may be reversed in a P-type transistor implementation. Still additional modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the following claims.