Embodiments provide metal tip-to-tip scaling for metal contacts. A structure includes a first metal line and a second metal line. The structure includes a spacer separating the first metal line from the second metal line, the spacer including a flat surface and curved tips, where the flat surface abuts the first metal line and the curved tips abut the second metal line.

BACKGROUND

The present invention generally relates to fabrication methods and resulting structures for integrated circuits (ICs), and more specifically, to fabrication methods and resulting structures for providing metal tip-to-tip scaling for metal contacts.

ICs (also referred to as a chip or a microchip) include electronic circuits on a wafer. The wafer is a semiconductor material, such as, for example, silicon or other materials. An IC is formed of a large number of devices, such as transistors, capacitors, resistors, etc., which are formed in layers of the IC and interconnected with wiring in the back-end-of-line (BEOL) layers of the wafer. on the wafer. Typical ICs are formed by first fabricating individual semiconductor devices using processes referred to generally as the front-end-of-line (FEOL). A metal-oxide-semiconductor field-effect transistor (MOSFET) is a transistor used for amplifying or switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. A conventional FET is a planar device where the entire channel region of the device is formed parallel and slightly below the planar upper surface of the semiconducting substrate. In contrast to a planar FET, there are so-called three-dimensional (3D) devices, such as a FinFET device, which is a three-dimensional structure. One type of device that shows promise for advanced integrated circuit products of the future is generally known as a nanosheet transistor. In general, a nanosheet transistor has a fin-type channel structure that includes a plurality of vertically spaced-apart sheets of semiconductor material. A gate structure for the device is positioned around each of these spaced-apart layers of channel semiconductor material.

The BEOL is the second portion of IC fabrication where a network of vias and lines (known collectively as interconnect structures) of the IC is formed. The IC's individual devices, such as transistors, capacitors, resistors, etc., are formed in earlier layers of the IC and communicatively coupled with one another using the interconnect structures in the BEOL layers of the wafer. The BEOL layer that includes the interconnection of wiring is referred to as the metallization layer, which generally begins when the first layer of metal is deposited on the wafer. BEOL layers of the IC generally include contacts, insulating layers (dielectrics), metal levels, bonding sites for chip-to-package connections, etc.

As the devices on the ICs become smaller, smaller spacing is needed between metal contacts.

SUMMARY

Embodiments of the present invention are directed to providing metal tip-to-tip scaling for metal contacts. A non-limiting method includes forming a first metal line and a second metal line. The method includes forming a spacer separating the first metal line from the second metal line, the spacer including a flat surface and curved tips, where the flat surface abuts the first metal line and the curved tips abut the second metal line.

According to one or more embodiments, a non-limiting method includes forming a spacer separating a first metal line and a second metal line and removing the spacer so as to leave a cavity between the first metal line and the second metal line. The method includes depositing dielectric material to form an airgap spacer in the cavity between the first metal line and the second metal line and to form a dielectric cap above the first and second metal lines.

Other embodiments of the present invention implement features of the above-described devices/structures in methods and/or implement features of the methods in devices/structures.

DETAILED DESCRIPTION

Embodiments of the present invention are directed to providing metal tip-to-tip scaling for metal contacts. According to one or more embodiments, a non-limiting structure includes a first metal line and a second metal line, and a spacer separating the first metal line from the second metal line, the spacer having a flat surface and curved tips, where the flat surface abuts the first metal line and the curved tips abut the second metal line.

Technical effects and technical advantages provide improved metal tip-to-tip scaling between metal lines as device sizes decrease. Technical effects and advantages provide metal line tip-to-tip space scaling by using (only) a self-aligned dielectric spacer. As further technical effects and advantages, the removal of one side of the self-aligned spacer followed by additional metal fill results in the self-aligned spacer with improved metal tip-to-tip distance.

In addition to one or more of the features described above or below, additional features include where the second metal line includes a metal extension, the metal extension being separated from the first metal line by the spacer. As technical effects and technical advantages, the metal tip-to-tip spacing is reduced by adding the metal extension to the second metal line.

In addition to one or more of the features described above or below, additional features include where the second metal line includes a metal extension, the metal extension having a larger dimension in one direction than the second metal line. As technical effects and technical advantages, the metal tip-to-tip spacing is reduced by adding the metal extension to the second metal line, and the larger dimension in the z-axis is available for contact to other metal lines or conductive vias.

In addition to one or more of the features described above or below, additional features include where the second metal line includes a metal extension, the metal extension having a larger dimension in one direction than the first metal line. As technical effects and technical advantages, the metal tip-to-tip spacing is reduced by adding the metal extension to the second metal line, and the larger dimension in the z-axis is available for contact to other metal lines or conductive vias.

In addition to one or more of the features described above or below, additional features include where a top surface of the spacer is coplanar with the first metal line and the second metal line. As technical effects and technical advantages, the top surfaces of the first and second metal lines are available for subsequent fabrication operations, while providing the scaled metal tip-to-tip separation.

In addition to one or more of the features described above or below, additional features include where the flat surface and the curved tips are on opposite sides of the spacer. As technical effects and technical advantages, the spacer is an insulator with a unique structure that physically and electrically separates the first and second metal lines.

In addition to one or more of the features described above or below, additional features include where the spacer has an airgap. As technical effects and technical advantages, the airgap reduces any capacitance between the first and second metal lines.

According to one or more embodiments, a non-limiting method includes forming a first metal line and a second metal line, and forming a spacer separating the first metal line from the second metal line, the spacer having a flat surface and curved tips, where the flat surface abuts the first metal line and the curved tips abut the second metal line.

Technical effects and technical advantages provide improved metal tip-to-tip scaling between metal lines as device sizes decrease. Technical effects and advantages provide metal line tip-to-tip space scaling by using (only) a self-aligned dielectric spacer. As further technical effects and advantages, the removal of one side of the self-aligned spacer followed by additional metal fill results in the self-aligned spacer with improved metal tip-to-tip distance.

According to one or more embodiments, a non-limiting method includes forming a spacer separating a first metal line and a second metal line, and removing the spacer so as to leave a cavity between the first metal line and the second metal line. The method includes depositing dielectric material to form an airgap spacer in the cavity between the first metal line and the second metal line and to form a dielectric cap above the first and second metal lines.

Technical effects and technical advantages provide improved metal tip-to-tip scaling between metal lines as device sizes decrease. Technical effects and advantages provide metal line tip-to-tip space scaling by using (only) a self-aligned dielectric spacer. As further technical effects and advantages, the removal of one side of the self-aligned spacer followed by additional metal fill results in the self-aligned spacer with improved metal tip-to-tip distance. Technical effects and advantages include the removal of the solid spacer and the formation of the airgap spacer that reduces any capacitance between the first and second metal lines.

In addition to one or more of the features described above or below, additional features include where the airgap spacer includes an airgap. Technical effects and advantages include the reduction of any capacitance by having the airgap between the first and second metal lines.

In addition to one or more of the features described above or below, additional features include where the airgap spacer includes a flat surface and curved tips, the flat surface abutting the first metal line and the curved tips abutting the second metal line. Technical effects and advantages include the airgap spacer with surfaces for separating the first and second metal lines.

In addition to one or more of the features described above or below, additional features include where the second metal line includes a metal extension, the metal extension being separated from the first metal line by the airgap spacer. Technical effects and advantages include the metal extension for providing a surface for further fabrication operations.

ICs are typically formed from a large number of semiconductor devices and conductive interconnect layers. More specifically, during the first portion of chip-making (i.e., the front end of line (FEOL) stage), the individual components (transistors, capacitors, etc.) are fabricated on the wafer. The middle of line (MOL) stage follows the FEOL stage and typically includes process flows for forming the contacts and other structures that communicatively couple to active regions (e.g., gate, source, and drain) of the device element. In the BEOL stage, these device elements are connected to each other through a network of interconnect structures to distribute signals, as well as power and ground. The conductive interconnect layers formed during the BEOL stage serve as a network of pathways that transport signals throughout an IC, thereby connecting circuit components of the IC into a functioning whole and to the outside world. Because there typically is not enough room on the chip surface to create all of the necessary connections in a single layer, chip manufacturers build vertical levels of interconnects. While simpler ICs can have just a few metallization layers, complex ICs can have ten or more layers of wiring.

BEOL-stage interconnect structures that are physically close to FEOL-stage components (e.g., transistors and the like) need to be small because they attach/join to the components that are themselves very small and often closely packed together. These lower-level lines, which can be referred to as local interconnects, are usually thin and short in length. Global interconnects are higher up in the IC layer structure and travel between different blocks of the circuit. Thus, global interconnects are typically thick, long, and more widely separated local interconnects. Vertical connections between interconnect levels (or layers), called metal-filled vias, allow signals and power to be transmitted from one layer to the next. For example, a through-silicon via (TSV) is a conductive contact that passes completely through a given semiconductor wafer or die. In multi-layer IC configurations, for example, a TSV can be used to form vertical interconnections between a semiconductor device located on one layer/level of the IC and an interconnect layer located on another layer/level of the IC. These vertical interconnect structures include an appropriate metal and provide the electrical connection of the various stacked metallization layers.

Turning now to a more detailed description of aspects of the present invention,FIG.1Adepicts a top view of a simplified illustration of a portion of an integrated circuit (IC)100andFIG.1Bdepicts a cross-sectional view taken along X of the IC100. For ease of understanding, some layers may be omitted from the various top views so as not to obscure the figure and to view layers underneath. As such, the top view is intended to provide a simplified illustration and a general orientation, but the top view is not intended to be a complete representation of the device. Standard semiconductor fabrication techniques can be utilized to fabricate the IC100as understood by one of ordinary skill in the art. Any suitable lithography processes including deposition techniques and etching techniques can be utilized herein.

FIGS.1A and1Bdepict the IC100having a wafer where several fabrication processes have been performed.FIGS.1A and1Billustrate the IC100after fabrication operations. The IC100can be part of the BEOL, and there can be many other devices already fabricated in an underlayer102. Metal formation (or certain placeholder material) is performed to form a metal layer106, which can be referred to as M1 or Mx. The metal layer106is formed in an interlayer dielectric (ILD) layer104. The material of the metal layer106can be Ru, copper, aluminum, tungsten, Co, gold, etc. A thin adhesion metal liner such as TiN and/or TaN is usually deposited too before the metal fill. The ILD material of the ILD layer104can be chosen such that later formed materials have etch selectivity. The ILD material can be SiO2, SiN, a low-k dielectric material or an ultra-low-k dielectric material. Low-k dielectric materials may generally include dielectric materials having a k value of about 3.9 or less. The ultra-low-k dielectric material generally includes dielectric materials having a k value less than 2.5. Unless otherwise noted, all k values mentioned in the present application are measured relative to a vacuum. Exemplary ultra-low-k dielectric materials generally include porous materials such as porous organic silicate glasses, porous polyamide nanofoams, silica xerogels, porous hydrogen silsequioxane (HSQ), porous methylsilsesquioxane (MSQ), porous inorganic materials, porous CVD materials, porous organic materials, or combinations thereof. The ultra-low-k dielectric material can be produced using a templated process or a sol-gel process as is generally known in the art. In the templated process, the precursor typically contains a composite of thermally labile and stable materials. After film deposition, the thermally labile materials can be removed by thermal heating, leaving pores in the dielectric film. In the sol gel process, the porous low-k dielectric films can be formed by hydrolysis and polycondensation of an alkoxide(s) such as tetraetehoxysilane (TEOS).

FIGS.2A and2Bdepict the IC100after a metal layer cut. A hard mask layer202is formed on top of the metal layer106and the ILD layer104. The hard mask layer202is patterned, and the patterned hard mask layer202is utilized to etch through the metal layer106into the ILD layer104, forming cavity204. The etching of the metal layer106results in two metal lines, illustrated as metal line210and metal line212, which are physically separated by the cavity204. A dry etch may be utilized. Example materials of the hard mask layer202can include nitride materials such as silicon nitride, TiN, SiON, etc.

FIGS.3A and3Bdepict the IC100after the first insulator spacer formation. A dielectric material is deposited followed by anisotropic etch process to form a spacer302, which may be referred to as the first spacer. The spacer302is a self-aligned spacer. The spacer302can include silicon dioxide, SiN, SiC, SiOC, AlOx, AlNx, etc.

FIGS.4A and4Bdepict the IC100after spacer protection patterning. Protective material can be deposited and patterned to form mask402that protects a portion of the spacer302from subsequent fabrication operations. The other portion of the spacer302is exposed. The material of the mask402may include anti-reflective coating (ARC) layer, organic planarization layer (OPL) and/or other suitable materials.

FIGS.5A and5Bdepict the IC100after removing the exposed spacer. The unprotected spacer material is removed, while the protected portion of the spacer302remains protected.

FIGS.6A and6Bdepict the IC100after depositing additional metal to extend the length of one of the metal lines. The mask402is removed. For example, OPL material can be removed by ashing. Additional metal material is deposited to form a metal extension602of the metal line212. The combination of the metal extension602and the metal line212form an aggregated metal line612. Material of the metal extension602can include Ru, copper, aluminum, Co, W, gold, etc.

The IC100includes an interconnect structure, where the spacer302isolates the two ends (e.g., from tip-to-tip) of the metal line210and metal line212. The spacer302has a flat surface that abuts the metal line210, and as hook-like tips or curved tips620that abut the metal extension602of the aggregated metal line612. The metal extension602is connected to the metal line212, such that the aggregated metal line612is isolated from the metal line210by the spacer302. The metal extension602has a larger dimension in the z-axis than the metal line210or the metal line212. Particularly, a bottom surface of the metal extension602extends below the bottom surfaces of the metal line210and metal lines212, while the top surfaces of the metal extension602, the metal lines210, and the metal line212are coplanar.

The thickness of the spacer302, as well as the airgap spacer806depicted inFIGS.8A and8B, is smaller than a thickness that could have been achieved using lithography to form the spacer. In one or more embodiments, the thickness of the spacer302(as well as the airgap spacer806) could be about 6 nanometers (nm). In one or more embodiments, the thickness of the spacer302(as well as the airgap spacer806) can range from about 4-7 nm. Accordingly, the spacer302(as well as the airgap spacer806) can provide a tip-to-tip spacing between the metal lines210and the metal lines212of about 4-7 nm.

According to one or more embodiments, modification to the interconnect structure of the IC is shown inFIGS.7A,7B,8A, and8B.FIGS.7A,7B,8A, and8Bdepict an airgap spacer utilized to separate the metal line210and the metal line212, according to one or more embodiments. Continuing from fabrication operations of the IC100shown inFIGS.1A-6B,FIGS.7A and7Bdepict the IC700after selectively removing the insulator spacer. Etching is performed to selectively remove the spacer302leaving a cavity702. In one or more embodiments, the spacer302could formed of silicon germanium such that the silicon germanium material can be selectively removed, while the ILD layer104and the metal of the metal line210, the metal line212, and the metal extension602remain.

FIGS.8A and8Bdepict the IC700after forming a dielectric cap and airgap spacer. Dielectric material is deposited as a second insulator. The dielectric material forms a dielectric cap804and is deposited in the cavity702so as to form an airgap spacer806having an airgap802. The dielectric material can be deposited by atomic layer deposition (ALD) so as to cause the airgap spacer806to be formed with the airgap spacer806.

According to one or more embodiments,FIGS.9A-22depict fabrication operations for an IC900.FIGS.9A and9Bdepict the IC900having a wafer where several fabrication processes have been performed, analogous toFIGS.1A and1B.FIG.9Adepicts a top view of a simplified illustration of a portion of the IC900andFIG.9Bdepicts a cross-sectional view taken along X of the IC900. For ease of understanding, some layers may be omitted from the various top views so as not to obscure the figure and to view layers underneath. As such, the top view is intended to provide a simplified illustration and a general orientation, but the top view is not intended to be a complete representation of the device. Standard semiconductor fabrication techniques can be utilized to fabricate the IC100as understood by one of ordinary skill in the art. Any suitable lithography processes including deposition techniques and etching techniques can be utilized herein. InFIGS.9A and9B, the metal layer106is formed in the ILD layer104.

FIGS.10A and10Bdepict the IC900after a metal layer cut. The hard mask layer202is patterned, and the patterned hard mask layer202is utilized to etch through the metal layer106into the ILD layer104, forming cavity1004. The etching of the metal layer106results in two metal lines, illustrated as metal line210and metal line212, which are physically separated by the cavity1004. A wet etch or dry etch may be utilized. Example materials of the hard mask layer202can include nitride materials such as silicon nitride.

FIGS.11A and11Bdepict the IC900after the first insulator spacer formation. A dielectric material is deposited to form the spacer302, which may be referred to as the first spacer. The spacer302can include silicon dioxide, SiN, SiOC, SiC, SiBCN, SiOCN, AlOx, AlNx, etc.

FIGS.12A and12Bdepict the IC900after spacer protection patterning. Protective material can be deposited and patterned to form mask402that protects a portion of the spacer302from subsequent fabrication operations. The other portion of the spacer302is exposed. The material of the mask402may include an ARC layer, an organic planarization layer (OPL) and/or other suitable materials.

FIGS.13A and13Bdepict the IC900after removing the exposed spacer. The unprotected spacer material is removed, while the protected portion of the spacer302remains protected.

FIGS.14A and14Bdepict the IC900after further etching. Etching is performed to expose, for example, contacts (not shown) to one or more devices in the underlayer102, thereby resulting in a cavity1402.

FIGS.15A and15Bdepict the IC900after metal fill. Metal is deposited to form conductive via1502that fills the empty cavity1402. The conductive via1502abuts both the metal line212and the spacer302. The conductive via1502may be referred to as Vx−1. Materials of the deposited metal can include Ru, copper, aluminum, W. Co, gold, etc.

FIG.16is a cross-sectional view depicting the IC900after conductive via and metal line recess. Etching is performed to selectively recess the metal line210, the metal line212, and the conductive via1502, while the spacer302is not etched. The etching results in cavities1602. A selective wet etch or dry etch may be utilized. The upper portion of the conductive via1502can be considered a metal extension to the metal line212. InFIG.16, the upper portion of the conductive via1502as the metal extension and the metal line212can be referred to as an aggregated metal line, which is analogous to aggregated metal line612.

FIG.17is a cross-sectional view depicting the IC900after dielectric cap formation. Dielectric material is deposited in the cavities1602to form a dielectric cap1702. Chemical mechanical planarization/polishing (CMP) can be performed. The dielectric material of the dielectric cap1702can be a different dielectric material than the spacer302in order to provide etch selectivity during later fabrication operations. Examples materials of the dielectric cap1702can include SiO2, SiN, SiC, SiOC, SiBCN, SiOCN, AlOx, AlNx, etc.

FIG.18is a cross-sectional view depicting the IC900after ILD fill. Dielectric material is deposited increasing the ILD layer104in preparation for further fabrication operations.

FIG.19is a cross-sectional view depicting the IC900after metal (Mx+1) patterning and via (Vx) patterning. A hard mask layer1902is formed on top of the ILD layer104. The hard mask layer1902is patterned, and the patterned hard mask layer1902is utilized to etch through portions of the ILD layer104, forming cavities1904. In some cavities1904the dielectric cap1702is exposed, which is in preparation for further fabrication operations. Also, a top surface of the spacer302is exposed in one of the cavities1904. A wet etch or dry etch may be utilized. Example materials of the hard mask layer202can include nitride materials such as silicon nitride, TiN, SiON, etc.

FIG.20is a cross-sectional view depicting the IC900after selectively opening the dielectric cap. Etching is performed to form openings2002and2004through the dielectric cap1702. The opening2002exposes a portion of the metal line210and a side portion of the spacer302. The opening2004exposes a portion of the metal line212. The selective etch process does not etch the spacer302, thereby preventing the via shorting to neighboring metal line212.

FIG.21is a cross-sectional view depicting the IC900after metal line (Mx+1) metallization and conductive via (Vx) metallization. Metal is deposited to form conductive via2110, conductive via2112, and metal lines2120. The metal lines2120can be referred to as Mx+1 because they are formed above the metal lines210and212that are referred to as Mx. The conductive vias2110and2112can be referred to as Vx because they are formed above the conductive via1502is referred to as Vx−1. The conductive via2110is in contact with both the spacer302and metal line210below and is in contact with one of the metal lines2120above. The conductive via2112is in contact with the metal line212below and another one of the metal lines2120above.

As can be seen inFIG.21, BEOL scaling has been accomplished to minimize the distance between metal line212(e.g., Mx) (including an upper portion of the conductive via1502) and the conductive via2110(e.g., Vx), as depicted by a highlighted circle2150. As depicted by a highlighted circle2152, the BEOL scaling minimizes the tip-to-tip distance between the metal line210and the metal line212including an upper portion of the conductive via1502.

FIG.22depicts highlighted portions of the IC900. An imaginary line2250is identified as being coplanar with bottom surfaces of the metal lines210and the metal lines212. InFIG.22, an angle2202is identified between a first side surface2210of the spacer302and the bottom of the metal line210identified by the imaginary line2250. The angle2202is less than 90°. An angle2204is identified between a second side surface2212of the spacer302and the bottom of the metal line212identified by the imaginary line2250. The angle2204is greater than 90°. The first side surface2210of the spacer302is opposite the second side surface2212.

According to one or more embodiments, a method includes forming a first metal line (e.g., metal line210) and a second metal line (e.g., metal line212). The method includes forming a spacer (e.g., spacer302and airgap spacer806) separating the first metal line from the second metal line, the spacer having a flat surface and curved tips620, where the flat surface abuts the first metal line (e.g., metal line210) and the curved tips620abut the second metal line.

The second metal line includes a metal extension (e.g., metal extension602and upper portion of the conductive via1502), the metal extension being separated from the first metal line by the spacer (e.g., spacer302or the airgap spacer806). The second metal line includes a metal extension, the metal extension (e.g., metal extension602and upper portion of the conductive via1502) having a larger dimension in one direction (e.g., the z-axis) than the second metal line (e.g., metal line212). The second metal line includes a metal extension (e.g., metal extension602and upper portion of the conductive via1502), the metal extension having a larger dimension in one direction (e.g., the z-axis) than the first metal line (e.g., metal line210). A top surface of the spacer is coplanar with the first metal line and the second metal line. The flat surface and the curved tips (e.g., curved tips620) are on opposite sides of the spacer. The spacer has an airgap802.

According to one or more embodiments, a method includes forming a spacer302separating a first metal line (e.g., metal line210) and a second metal line (e.g., metal line212). The method includes removing the spacer302so as to leave a cavity702between the first metal line and the second metal line. The method includes depositing dielectric material to form an airgap spacer806in the cavity702between the first metal line and the second metal line and to form a dielectric cap804above the first and second metal lines.

The airgap spacer806includes an airgap802. The airgap spacer806includes a flat surface and curved tips620, where the flat surface abuts the first metal line and the curved tips620abut the second metal line. The second metal line includes a metal extension, the metal extension being separated from the first metal line by the airgap spacer806. The second metal line includes a metal extension, the metal extension having a larger dimension in one direction than the second metal line. The second metal line includes a metal extension, the metal extension having a larger dimension in one direction than the first metal line.

As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing substrate, examples of p-type dopants, i.e., impurities, include but are not limited to: boron, aluminum, gallium and indium.

As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing substrate examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous.

In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device.

As noted above, atomic layer etching processes can be used in the present invention for via residue removal, such as can be caused by via misalignment. The atomic layer etch process provide precise etching of metals using a plasma-based approach or an electrochemical approach. The atomic layer etching processes are generally defined by two well-defined, sequential, self-limiting reaction steps that can be independently controlled. The process generally includes passivation followed selective removal of the passivation layer and can be used to remove thin metal layers on the order of nanometers. An exemplary plasma-based approach generally includes a two-step process that generally includes exposing a metal such a copper to chlorine and hydrogen plasmas at low temperature (below 20° C.). This process generates a volatile etch product that minimizes surface contamination. In another example, cyclic exposure to an oxidant and hexafluoroacetylacetone (Hhfac) at an elevated temperature such as at 275° C. can be used to selectively etch a metal such as copper. An exemplary electrochemical approach also can include two steps. A first step includes surface-limited sulfidization of the metal such as copper to form a metal sulfide, e.g., Cu2S, followed by selective wet etching of the metal sulfide, e.g., etching of Cu2S in HCl. Atomic layer etching is relatively recent technology and optimization for a specific metal is well within the skill of those in the art. The reactions at the surface provide high selectivity and minimal or no attack of exposed dielectric surfaces.

Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photoresist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators and selectively doped regions are built up to form the final device.

The photoresist can be formed using conventional deposition techniques such chemical vapor deposition, plasma vapor deposition, sputtering, dip coating, spin-on coating, brushing, spraying and other like deposition techniques can be employed. Following formation of the photoresist, the photoresist is exposed to a desired pattern of radiation such as X-ray radiation, extreme ultraviolet (EUV) radiation, electron beam radiation or the like. Next, the exposed photoresist is developed utilizing a conventional resist development process.

After the development step, the etching step can be performed to transfer the pattern from the patterned photoresist into the interlayer dielectric. The etching step used in forming the at least one opening can include a dry etching process (including, for example, reactive ion etching, ion beam etching, plasma etching or laser ablation), a wet chemical etching process or any combination thereof.