System and method for mixed mode equalization of signals

There is disclosed a mixed mode equalization system for use in a transceiver capable of operating in a high frequency Ethernet local area network (LAN). The mixed mode equalization system comprises: 1) an adaptive analog equalization filter for amplifying a first high frequency component of an incoming analog signal by a first adjustable gain factor to produce an analog filtered incoming signal; 2) an analog-to-digital converter (ADC) for converting the analog filter incoming signal to a first incoming digital signal; 3) a digital finite impulse response (FIR) filter for amplifying a second high frequency component of the first incoming digital signal factor to produce a digital filtered incoming signal; 4) a digital FIR controller for modifying at least one digital filter coefficient of the digital FIR filter according to a signal error associated with a digital output of the digital FIR filter; and 5) an analog equalization controller for modifying the first adjustable gain factor associated with the adaptive analog equalization filter according to a value of the at least one digital filter coefficient.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present invention is related to those disclosed in the following United States patent Applications:

2. Ser. No. 09/569,957, filed concurrently herewith, entitled “SYSTEM AND METHOD FOR CANCELLING SIGNAL ECHOES IN A FULL-DUPLEX TRANSCEIVER FRONT END;”

3. Ser. No. 09/570,077, filed concurrently herewith, entitled “DIGITALLY CONTROLLED AUTOMATIC GAIN CONTROL SYSTEM FOR USE IN AN ANALOG FRONT-END OF A RECEIVER;”

4. Ser. No. 09/569,828, filed concurrently herewith, entitled “SYSTEM AND METHOD FOR CORRECTING OFFSETS IN AN ANALOG RECEIVER FRONT END;”

5. Ser. No. 09/569,518, filed concurrently herewith, entitled “RECEIVER ARCHITECTURE USING MIXED ANALOG AND DIGITAL SIGNAL PROCESSING AND METHOD OF OPERATION;” and

6. Ser. No. 09/570,078, filed concurrently herewith, entitled “SYSTEM AND METHOD FOR ADAPTING AN ANALOG ECHO CANCELLER IN A TRANSCEIVER FRONT END.”

The above applications are commonly assigned to the assignee of the present invention. The disclosures of these related patent applications are hereby incorporated by reference for all purposes as if fully set forth herein.

TECHNICAL FIELD OF THE INVENTION

The present invention is generally directed to high-speed Ethernet local area networks (LANs) and, more specifically, to a mixed-mode equalization system for use in a full-duplex transceiver for a gigabit Ethernet network.

BACKGROUND OF THE INVENTION

The rapid proliferation of local area network (LANs) in the corporate environment and the increased demand for time-sensitive delivery of messages and data between users has spurred development of high-speed (gigabit) Ethernet LANs. The 100BASE-TX Ethernet LANs using category-5 (CAT-5) copper wire and the 1000BASE-T Ethernet LANs capable of one gigabit per second (1 Gbps) data rates over CAT-5 data grade wire require new techniques for the transfer of high-speed symbols.

The transfer of high-speed symbols over an Ethernet LAN requires full-duplex gigabit (Gbps) Ethernet transceivers which transmit and receive data over category-5 copper wire at the 1 Gbps data rate. This full-duplex data transfer occurs over four twisted pairs at 125 mega-symbols (125 Mbaud) per second per pair, which is the same as a transfer rate of 500 mega-symbols (Mbaud) per second in each direction.

In an exemplary system, data is transmitted using a five-level pulse amplitude modulation (PAM-5) technique. In PAM-5, data is represented by five voltage levels, designated as an alphabet symbol (A} represented by data bits with the symbol alphabet having values of −2, −1, 0, 1, 2 volts, for example. The actual voltage levels may differ from these five levels. At each clock cycle, a single one-dimensional (1D) symbol is transmitted on each wire. The four 1D symbols traveling in one direction on each of the conductor pairs at a particular sample time k are considered to be a single four-dimensional (4D) symbol. In addition, extra channel symbols represent Ethernet control characters. Therefore, five level PAM (PAM-5) with either a parity check code or trellis coding is often utilized in Gigabit Ethernet transmission.

At 125 Mbaud, each 4D symbol needs to transmit at least eight bits. Therefore, 256 different 4D symbols plus those required for control characters are required. By transmitting a 4D PAM-5 symbol alphabet, there are 54=625 possible symbols. This number of symbols allows for 100% redundancy in the data as well as for several control codes. Symbol alphabets having more than five symbols yield even greater redundancy.

Another technique for transferring data at high rates is known as non-return to zero (NRZ) signaling. In NRZ, the symbol alphabet {A} has values of −1 and +1 volts. A Logical 1 is transmitted as a positive voltage, while a Logical 0 is transmitted as a negative voltage. At 125 mega-symbols per second, the pulse width of each NRZ symbol (the positive or negative voltage) is 8 nano-seconds.

Another modulation method for high speed symbol transfer is known as multi-level transmit-3 (MLT-3) which uses three voltage levels for the transfer of data. This American National Standard Information (ANSI) approved modulation technique is used for the transfer of data over a 100BASE-TX network using unshielded twisted pairs.

In MLT3 transmission, a Logic 1 is transmitted as either a −1 or a +1 voltage while a Logic 0 is transmitted as a 0 voltage. Thus, the transmission of two consecutive Logic 1s does not require an MLT-3 system to pass data through zero. The transmission of an MLT-3 logical sequence (1, 0, 1) results in transmission of the symbols (+1, 0, −1) or (−1, 0, +1), depending on the symbols transmitted prior to this sequence. If the symbol transmitted immediately prior to the sequence is a +1, then the symbols (+1, 0, −1) are transmitted. If the symbol transmitted before this sequence is a −1, then the symbols (+1,0,−1) are transmitted. If the symbol transmitted immediately before this sequence is a 0, then the first symbol of the sequence transmitted will be a +1 if the previous Logic 1 is transmitted as a −1 and will be a −1 if the previous Logic 1 is transmitted as +1.

The signal-to-noise ratio (SNR) required to achieve a particular bit error rate is higher for MLT-3 signaling than for two level systems. The advantage of the MLT-3 system, however, is that the energy spectrum of the emitted radiation from the MLT-3 system is concentrated at lower frequencies and therefore more easily meets Federal Communications Commission (FCC) radiation emission standards for transmission over twisted pair cables.

Other modulation schemes for multi-symbol coding can also be utilized, including quadrature amplitude modulation (QAM). In QAM schemes, for example, the symbols are arranged on two-dimensional (real and imaginary) symbol constellations (instead of the one-dimension constellations of the PAM-5 or MLT-3 symbol alphabets.)

These multi-level symbol representations were not needed prior to the development of higher speed computer networks, since data could be transferred between computers at sufficient speeds and accuracy as binary data. However, the higher gigabit per second Ethernet data rate and other communications schemes requires transmitters and receivers capable of transmitting and receiving data over multiple twisted copper pair using larger symbol alphabets (i.e., 3 or more symbols). There is also a need for transceiver (transmitter/receiver) systems that operate at high symbol rates while maintaining have low bit error rates (BERs).

As in other communications systems, the transmission cable (or channel) connecting the transmitter and receiver distorts the shape of the transmitted symbol stream. Each symbol transmitted is diffused in the transmission process so that it is commingled with symbols being transmitted at later transmission times. This effect is known as “intersymbol interference” (ISI) and is a result of the dispersive nature of the communication cable. The transmitted waveform is further changed by the cable transmission characteristics, noise which is added over time, and interfacing devices such as transformers, for instance.

When the high-speed signal is received at the transceiver, it is further modified by the physical and operating characteristics of the receiving transceiver. For instance, the impedance that may be seen by the transceiver front-end not only includes the impedance of the cable and the transformer that couples the cable to the transceiver front-end, but also the impedance of on-board traces and input/output structures. Input/output structures include electrostatic discharge protectors, input/output cells, and the like, that may reside on an integrated circuit before the transceiver front-end components.

Therefore, there is a need in the art for improving the performance of full-duplex transceivers for operation at gigabit per second data rates across local area networks. There is a further need in the art for improving the performance of full-duplex transceiver front-ends to compensate for operational changes due to cable and circuit characteristics as well as the lengths of connecting cable. In particular, there is a need for improved transceiver front-ends which accommodate changes due to manufacturing processes and environmental changes across time. More particularly, there is a need in the art for a high performance full-duplex transceiver front-end which incorporates a system for improving performance by cancelling echos and correcting for signal offsets, as well as adjusting performance due to direct current and data dependent drifts and off-sets.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a mixed mode equalization system for use in a transceiver capable of operating in a high frequency Ethernet local area network (LAN). The transceiver comprises front-end analog signal processing circuitry capable of at least one of: 1) transmitting an outgoing analog signal to an external cable via a transformer, 2) reducing a DC component in an incoming analog signal; 3) reducing an echo of the outgoing analog signal in the incoming analog signal; and 4) amplifying the incoming analog signal by an adjustable gain factor. According to an advantageous embodiment of the present invention, the mixed mode equalization system comprises: an adaptive analog equalization filter capable of receiving the incoming analog signal and amplifying a first high frequency component of the incoming analog signal by a first adjustable gain factor to thereby produce an analog filtered incoming signal; 2) an analog-to-digital converter (ADC) capable of converting the analog filter incoming signal to a first incoming digital signal; 3) a digital finite impulse response (FIR) filter capable of receiving the first incoming digital signal and amplifying a second high frequency component of the first incoming digital signal factor to thereby produce a digital filtered incoming signal; 4) a digital FIR controller capable of modifying at least one digital filter coefficient of the digital FIR filter according to a signal error associated with a digital output of the digital FIR filter; and 5) an analog equalization controller capable of modifying the first adjustable gain factor associated with the adaptive analog equalization filter according to a value of the at least one digital filter coefficient.

DETAILED DESCRIPTION OR THE INVENTION

FIG. 1illustrates exemplary full-duplex transceiver100according to one embodiment of the present invention. In an advantageous embodiment of the present invention, full-duplex transceiver100is fabricated as a single integrated circuit (IC), represented as IC101, that is coupled to a local area network (LAN) via cable105and transformer110. The transmit path in full duplex transceiver100comprises data source115and line driver120. The receive path in full duplex transceiver100comprises an analog front-end portion and a digital portion. The analog front-end comprises DC offset correction circuit125, echo canceller130, automatic gain control (AGC) circuit135, and adaptive equalization filter (AEF)140. The output of adaptive equalization filter140is converted from an analog signal to a digital signal by analog-to-digital converter (ADC)145. The digital portion of full duplex transceiver100comprises digital finite impulse response (FIR) filter150and slicer155.

The operations of the analog components in full duplex transceiver100are controlled by DC offset correction controller160, echo canceller controller165, AGC controller170, and analog equalization controller175. The operation of digital FIR filter150is controlled by digital FIR filter controller180. Full duplex transceiver100also comprises timing recovery control circuit185and clock recovery mixer190, which generates a recovered clock signal from the outputs of slicer155. Timing recovery control circuit185and clock recovery mixer190use the data signal and error signal from slicer155as inputs to a digital phase-locked loop (PLL) circuit. The PLL circuit controls the phase/delay of an analog-based frequency synthesizer which, in turn, produces a low jitter clock centered at the symbol for sampling by ADC145.

Full duplex transceiver100is capable of simultaneously transmitting and receiving analog signals through cable105, which may be a copper twisted pair cable. Transformer110receives outgoing analog data signals from data source115through line driver120and transmits the outgoing signals to the LAN (not shown) via cable105. Transformer110also receives incoming analog data signals from the LAN via cable105and transmits them to direct current (DC) offset correction circuit125.

DC offset correction circuit125generates an offset signal that modifies the incoming analog data signal in order to cancel the systematic offset that accrues during the operation of transceiver100. Echo canceller130receives both the outgoing signal from line driver120and the incoming signal from DC offset correction circuit125and removes the echoes of the outgoing signal from the incoming signal. In an alternate embodiment of full-duplex transceiver100, DC offset correction circuit125may be omitted and echo canceller130may remove the echoes of the outgoing signal from the incoming signal that echo canceller130receives directly from transformer110.

After echo canceller130cancels out echoes of the outgoing signal, analog gain control (AGC) circuit135automatically adjusts the amplitude of the output of echo canceller130to the desired signal level based on the slicer levels of slicer155and transmits the amplified analog data signals to adaptive equalization filter (AEF)140. AEF140provides signal equalization by providing a high frequency boost to correct the analog data signal loss in cable105. The amount of the high frequency boost provided by AEF140changes with the length of cable105. Analog-to-digital converter (ADC)145converts the filtered analog data signals from AEF140to digital signals.

The digital output signals from ADC145are then transferred to digital finite impulse response (FIR) filter150and to data slicer155. The filter tap coefficients of digital FIR filter150are used to adjust the equalization of AEF140. Slicer155detects the five levels of the PAM-5 signal and generates both an output data signal and an output error signal. Slicer155determines the error between the signal levels of the data symbols generated by digital FIR filter150and the ideal signal levels of the modulation technique. For example, in a five-level pulse amplitude modulation (PAM-5) system, data is represented by five voltage levels, designated as an alphabet symbol having values of −2, −1, 0, +1, +2 volts. If slicer155receives a voltage level of, for example, +1.15 volts, slicer155determines that the received signal level was supposed to be +1.0 volts and cuts off the +0.15 volt error signal. The slicer error signals are used to control the amount of echo cancellation and to determine the values of the filter tap coefficients used by digital FIR filter150.

During normal operation, AGC135and AGC controller170amplify the incoming signal to a level that is sufficiently below the maximum limits of ADC145such that the expected maximum signal peaks of the incoming signal are not large enough to saturate ADC145. However, in some embodiments, the signal levels of the output of ADC145may not match the signal levels expected by slicer155. That is, it may not be possible to operate ADC145to reach the signal levels suitable for slicer155without sacrificing the extra headroom needed to prevent saturation of ADC145. To compensate for this, in an advantageous embodiment of the present invention, digital FIR filter150may also apply a flat gain to the digital output of ADC145in addition to applying signal equalization to the output of ADC145. The gain applied by digital FIR filter150may scale up or scale down the digital output signals from ADC145.

FIG. 2Aillustrates in greater detail exemplary DC offset correction circuit125according to one embodiment of the present invention. DC offset voltage accumulates in the front-end of the receiver due to process mismatches, manufacturing variations, and data-dependent offset (due to mis-matched positive and negative pulses through a band-width limited channel). DC offset correction circuit125provides a differential offset to cancel the systematic offset accrued in the analog front end of full-duplex transceiver100.

DC offset correction circuit125comprises adjustable current sources205and210, which are controlled by digital-to-analog converters that convert a digital control signal from DC offset correction controller160to produce the analog offset current Idac. Depending on the positive or negative level of the DC offset correction, the offset current may flow from adjustable current source205to adjustable current source210through resistor R11, transformer110and resistor R12, or it may flow in the reverse direction. If the bias current flows from adjustable current sources205to adjustable current source210, the junction between resistors R11and R21is biased to a higher voltage than the junction between resistors R12and R22. If the bias current flows from adjustable current sources210to adjustable current source205, the junction between resistors R11and R21is biased to a lower voltage than the junction between resistors R12and R22. The bias voltage applied to resistors R21and R22is then amplified by amplifier220in the receive path circuitry according to the value of the feedback resistors R31and R32. An N bit word from DC offset correction controller160controls Idacfrom −Imaxto +Imax. The equal and opposite (sourcing and sinking) currents flow into the differential data path as described above to produce a differential output offset correction signal at the output of amplifier220.

FIG. 2Billustrates in greater detail exemplary DC offset correction controller160according to one embodiment of the present invention. The output of ADC145is digitally filtered. This filtered output represents the average signal level through the analog front end of full duplex transceiver100. If the code being received at ADC145is DC balanced (i.e., no DC component), the output of DC offset correction controller160represents the DC offset which is accrued through the channel and the analog front end. DC offset correction controller160uses this filtered output (with negative feedback) to correct for the accrued offset in DC offset correction circuit125.

DC offset correction controller160comprises digital adder250, register255, delay element260, and digital inverter265. One input to adder250receives a current data sample from the output of ADC145. The output of ADC145may be a positive or a negative value. The other input receives from delay element260the previous contents of register255. The sum from adder250is then written as the new value in register255. The output of register255is inverted by inverter265to provide a negative feedback signal to DC offset correction circuit125. If the output of ADC145contains either a positive or a negative DC component due to accrued offset, the average value in register255is accordingly affected. The negative feedback provided by DC inverter265then reduces or increases the value of Idacin DC offset correction circuit125in order to reduce or to eliminate the positive or negative DC component caused by the accrued DC offset.

Advantageously, DC offset correction controller160can be used to cancel process-related DC offsets and dynamic data dependent offsets (such as base line wander) at the front of the11analog front end so as to relax the headroom requirements of the analog front end and ADC145. This leads to a robust implementation of full duplex transceiver100that is immune to mismatches and process-related variances.

FIG. 3Aillustrates in greater detail selected portions of exemplary echo cancellation circuit130according to one embodiment of the present invention. Echo cancellation circuit130comprises echo cancellation impedance model circuit310and amplifier220.FIG. 3Billustrates in greater detail exemplary echo impedance cancellation model circuit310according to one embodiment of the present invention. In a full-duplex system, data is simultaneously transmitted and received on cable105. An echo canceller is required in the receive path to cancel the transmitted signal, so that the received signal can be correctly recovered. Echo cancellation circuit130works on the principle of subtracting an estimate of the transmit signal from the full-duplex (receive+echo) signal on cable105. To accomplish this, echo cancellation circuit130receives a copy of the transmit signal from data source115(connection not shown inFIG. 1to simplify drawing). The signal transmitted on cable105depends on the impedance presented to IC101(i.e., the effective impedance of cable105and transformer110). Echo cancellation circuit130replicates the external impedance presented to IC101in order to estimate the transmitted signal.

The impedance presented to IC101depends on the characteristic impedance of cable105, the impedance of transformer110, the impedance of the on-board traces, and input/output (I/O) impedance of IC101(which could be electrostatic discharge devices (ESD)305A–305D and I/O cells) The effective impedance presented to IC101varies due to the manufacturing tolerances of the above mentioned components. Ideally, echo cancellation circuit130has the required degrees of freedom and range for replicating the external impedance within the expected manufacturing tolerances.

The architecture of echo cancellation circuit130depends on the architecture of the transmitter that drives the signal onto cable105. The transmitter (i.e., line driver120) may be a current-mode driver or a voltage mode driver. Off-chip cable terminations, such as R35, R36, R31A and R32A, and the on-chip circuitry, in conjunction with the magnetics of transformer110and cable105, perform the echo cancellation function. Echo cancellation impedance model circuit310comprises adjustable resistors and capacitors that are tuned to account for variations in the magnetics, cable impedance, and board parasitic losses. The adjustable resistors comprise arrays of resistors that may be placed in various series and parallel combinations by opening and closing switches controlled by echo cancellation controller165. Similarly, the adjustable capacitors comprise arrays of capacitors that may be placed in various series and parallel combinations by opening and closing switches controlled by echo cancellation controller165.

Echo cancellation controller165and echo cancellation impedance model circuit310provide high performance echo cancellation with only two degrees of tuning. The resistor (R50, R55, R60and R65) tuning accounts for the flat (DC) variation of the characteristic impedance of cable105. The capacitor (C10and C20) tuning accounts for changes in the effective bandwidth in the echo path (due to variations in transformer110, ESD variations and board capacitance).

The two paths, echo and echo canceller, are the shortest possible and consist only of passive elements. Mismatches in these two paths can lead to residual uncancelled echo. These mismatches are kept to a minimum due to the absence of active elements (and other complexity). This leads to a very robust design, which is insensitive to process offsets.

An echo canceller according to the principles of the present invention places a pole in the path of the residual echo to damp out the zero (peaking) in the impedance of transformer110. Thus, the echo canceller can be implemented as a single pole response, which makes it easier to adapt (as opposed to adapting a zero and a few poles to implement a bandpass response). Low-pass filter (LPF)370at the end of the echo canceller attenuates uncancelled high-frequency echo. The uncancelled high-frequency echo may be due to: a) differences between echo cancellation impedance model circuit310and the impedance of the echo path at high frequencies, primarily arising from the impedance peaking of transformer110; and b) errors arising from mismatches in the two signals (i.e., two signal paths) being subtracted.

FIG. 4Aillustrates in greater detail exemplary automatic gain control (AGC) circuit135according to one embodiment of the present invention. AGC circuit135comprises amplifier220, resistors R31, R32, R33, and R34, and capacitors C1and C2in a programmable gain configuration. Gain is programmed by adjusting the resistance values of adjustable resistors R33and R34. Adjustable resistors R33and R34comprise arrays of resistors that may be placed in various series and parallel combinations by opening and closing switches controlled by AGC controller170.

FIG. 4Billustrates in greater detail exemplary AGC controller170according to one embodiment of the present invention. AGC controller170comprises a digital peak detector that captures the peak of the output of ADC145and compares it with a threshold value, TH(AGC). If the absolute value of the output of ADC145is greater than threshold TH(AGC), then the AGC gain is decremented with a predetermined time constant. Otherwise, the AGC gain continuously increments at a relatively slow bleed rate.

In an advantageous embodiment of the present invention, AGC controller170comprises absolute value circuit455, comparison logic circuit460, adder465, register470, and delay element475. Absolute value circuit455determines the absolute value of a sample received from ADC145by determining the magnitude of the sample. Comparison logic circuit460compares the absolute value to predetermined threshold TH(AGC). The output of comparison logic circuit460may increment or decrement the value in register470depending by outputting a +1 or a −1. If the absolute value is greater than threshold TH(AGC), the output of comparison logic circuit460is −1. If the absolute value is less than or equal to threshold TH(AGC), comparison logic circuit460is normally 0, but periodically changes to +1 at a predetermined bleed rate. The bleed rate is relatively low so that register470increments only slowly.

One input of adder470receives the output (+1 or −1) of comparison logic circuit460. The other input of adder470receives from delay element475the previous contents of register470. The sum from adder465is then written as the new value in register470. The output of register470provides a negative feedback signal to AGC circuit135. If the absolute value of the output of ADC145is too high, the gain of AGC circuit135is accordingly reduced by the feedback signal. If the absolute value of the output of ADC145is not too high, the gain of AGC circuit135is slowly increased by the feedback signal.

The present invention implements a mixed mode equalization in which analog equalization is performed by adaptive equalization filter140and digital equalization is performed by digital FIR filter150. The mixed mode equalization occurs in alternating digital and analog stages until convergence (or a time out) occurs.FIG. 5illustrates in greater detail exemplary adaptive equalization (EQ) controller175according to one embodiment of the present invention. Adaptive EQ controller175comprises comparison logic circuit505, adder510, register515and delay circuit520. Comparison logic circuit505receives one or more of the digital filter coefficients (Bn) from digital filter FIR controller180and compares at least one of the received coefficients to a predetermined convergence threshold, TH(AEF). If the coefficient is greater than convergence threshold TH(AEF), comparison logic circuit505outputs a +1. If the coefficient is less than or equal to convergence threshold TH(AEF), comparison logic circuit505outputs a −1.

One input of adder510receives the output (+1 or −1) of comparison logic circuit505. The other input of adder510receives from delay element520a prior value stored in register515, depending on the number of clock cycle delays introduced by delay circuit520. The sum from adder510is then written as the new value in register515. The output of register515provides a control feedback signal to AEF140. If the value of the digital FIR coefficient is too high (Bn>TH(AEF)), the value in register515is incremented to increase the amount of analog equalization that occurs. This leads to a corresponding reduction in the amount of digital equalization that is needed, thereby reducing the value of the digital coefficient received by analog equalization controller175. If the value of the digital FIR coefficient is not above the convergence threshold TH(AEF), the value in register515is automatically decremented to decrease the amount of analog equalization that occurs. This leads to a corresponding increase in the amount of digital equalization that is needed, thereby increasing the value of the digital coefficient until it reaches the convergence threshold TH(AEF).

FIG. 6depicts flow diagram600, which illustrates the mixed mode equalization operation of exemplary full-duplex transceiver100according to one embodiment of the present invention. The mixed mode adaptive equalization filter provides signal equalization in the form of a high frequency boost that offsets cable loss. The amount of high frequency boost of the equalizer adapts to the length of the attached cable. Adaptive equalization filter (AEF)140is controlled (adapted) in conjunction with digital FIR filter160. The mixed mode equalization scheme provides some analog and some digital equalization to compensate for the overall attenuation of the channel. AEF140is incremented or decremented according to the predetermined converged value of digital FIR filter160.

Initially, AEF140is set to a preset value (process step605). For the initial setting of AEF140, slicer155generates a slicer error signal. To reduce or eliminate the slicer error, digital filter controller180modifies the filter tap coefficients so that digital FIR filter160is adjusted to provide gain sufficient to compensate the channel (process step610). Based on the converged value of the modified coefficients of digital FIR filter160, AEF140is incremented or decremented so as to partition the optimal balance of gain in the analog and digital data paths for optimal signal-to-noise (SNR) and signal processing requirements (process step615).

In response to the changes made by AEF140, slicer155generates a new slicer error signal. Again, to reduce or eliminate the slicer error, digital filter controller180re-adjusts the filter tap coefficients so that digital FIR filter160is adjusted to provide gain sufficient to compensate the channel (process step620). In response to the new converged value of the modified coefficients of digital FIR filter160, AEF140again is incremented or decremented in order to partition the optimal balance of gain in the analog and digital data paths (process step625).

The above-described mixed mode equalization operation continues in subsequent process steps (such as exemplary process steps630and635) until the coefficients of digital FIR filter160converge to the pre-determined threshold value, TH(AEF). At this point, no further adaptation of AEF155is required (process step640) and the operation is complete.