Test pending external interruption instruction

Testing for pending external interruptions. A Test Pending External Interruption instruction tests for pending external interruptions. The test for pending external interruptions is based on one or more program-specified subclasses, regardless of whether the machine is enabled for those classes of interruption. The instruction provides an indication for those subclasses being tested of whether there are any pending external interruptions for those subclasses.

BACKGROUND

One or more aspects relate, in general, to processing within a computing environment, and in particular, to improving such processing.

Computing environments often offer a mechanism to provide an interrupt to alter the processing sequence within a computing environment. An interrupt (also referred to as an interruption) is a signal to the operating system or processor, as examples, to temporarily stop executing a particular program to perform another task. As an example, one type of interrupt, an external interrupt, causes a currently running program to be suspended, in order to execute a higher priority operating system subroutine to handle the interrupt. The interruption mechanism in the central processing unit forces a branch out of the current program to a selected subroutine for other processing. After the interrupt is completed, the suspended program may be resumed.

This type of processing may also occur for other types of interrupts.

SUMMARY

Shortcomings of the prior art are overcome and additional advantages are provided through the provision of a computer program product for facilitating processing within a computing environment. The computer program product comprises a storage medium readable by a processing circuit and storing instructions for performing a method. The method includes, for instance, obtaining an instruction to test for one or more pending external interrupts; and executing the instruction, the executing including: determining, based on information provided by the instruction, one or more external interruption subclasses to be tested; checking whether one or more external interruptions are pending for the one or more external interruption subclasses being tested; and indicating whether one or more external interruptions are pending for the one or more external interruption subclasses being tested.

Methods and systems relating to one or more aspects are also described and claimed herein. Further, services relating to one or more aspects are also described and may be claimed herein.

DETAILED DESCRIPTION

In accordance with one or more aspects of the present invention, processing within a computing environment is facilitated by providing a capability to test for pending external interruptions. As used herein, the term “external interrupt” is an interrupt that originates from within a computer system having one or more processors (e.g., tightly coupled), but is external to a program. It is distinct from an input/output (I/O) interrupt that originates from an I/O device or a channel subsystem.

By determining if there is a pending external interruption, a control program, such as an operating system, can take action, which may include performing a task, or even avoiding or preventing a task from occurring, to facilitate processing within the environment. For instance, the control program may potentially accelerate the resolution of resource conflicts or dead-lock scenarios by avoiding certain actions. As examples, the control program may avoid performing a long-running service for a task whose time-slice is expiring, or avoid acquiring a lock when it has received a warning track interruption indicating that the operating system's logical processor is about to be undispatched by a hypervisor program. Other such examples exist.

The capability to test for pending external interruptions includes a Test Pending External Interruption instruction, which tests for pending external interruptions based on, for instance, one or more program-specified subclasses, regardless of whether the machine is enabled for those classes of interruption, as described further below.

One embodiment of a computing environment to incorporate and use one or more aspects of the present invention is described with reference toFIG. 1A. In one example, the computing environment is based on the z/Architecture, offered by International Business Machines Corporation, Armonk, N.Y. One embodiment of the z/Architecture is described in “z/Architecture Principles of Operation,” IBM Publication No. SA22-7832-10, Mar. 2015, which is hereby incorporated herein by reference in its entirety. Z/ARCHITECTURE is a registered trademark of International Business Machines Corporation, Armonk, N.Y., USA.

In another example, the computing environment is based on the Power Architecture, offered by International Business Machines Corporation, Armonk, N.Y. One embodiment of the Power Architecture is described in “Power ISA™ Version 2.07B,” International Business Machines Corporation, Apr. 9, 2015, which is hereby incorporated herein by reference in its entirety. POWER ARCHITECTURE is a registered trademark of International Business Machines Corporation, Armonk, N.Y., USA.

The computing environment may also be based on other architectures, including, but not limited to, the Intel x86 architectures. Other examples also exist.

As shown inFIG. 1A, a computing environment100includes, for instance, a computer system102shown, e.g., in the form of a general-purpose computing device. Computer system102may include, but is not limited to, one or more processors or processing units104(e.g., central processing units (CPUs)), a memory106(referred to as main memory or storage, as examples), and one or more input/output (I/O) interfaces108, coupled to one another via one or more buses and/or other connections110.

Bus110represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include the Industry Standard Architecture (ISA), the Micro Channel Architecture (MCA), the Enhanced ISA (EISA), the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI).

Memory106may include, for instance, a cache120, such as a shared cache, which may be coupled to local caches122of processors104. Further, memory106may include one or more programs or applications130, an operating system132, and one or more computer readable program instructions134. Computer readable program instructions134may be configured to carry out functions of embodiments of aspects of the invention.

Computer system102may also communicate via, e.g., I/O interfaces108with one or more external I/O devices140, one or more network interfaces142, and/or one or more data storage devices144. Example external devices include a user terminal, a tape drive, a pointing device, a display, etc. Network interface142enables computer system102to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet), providing communication with other computing devices or systems.

Data storage device144may store one or more programs146, one or more computer readable program instructions148, and/or data, etc. The computer readable program instructions may be configured to carry out functions of embodiments of aspects of the invention.

Computer system102may include and/or be coupled to removable/non-removable, volatile/non-volatile computer system storage media. For example, it may include and/or be coupled to a non-removable, non-volatile magnetic media (typically called a “hard drive”), a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”), and/or an optical disk drive for reading from or writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM or other optical media. It should be understood that other hardware and/or software components could be used in conjunction with computer system102. Examples, include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

Further details regarding one example of processor104are described with reference toFIG. 1B. Processor104includes a plurality of functional components used to execute instructions. These functional components include, for instance, an instruction fetch component150to fetch instructions to be executed; an instruction decode unit152to decode the fetched instructions and to obtain operands of the decoded instructions; instruction execution components154to execute the decoded instructions; a memory access component156to access memory for instruction execution, if necessary; and a write back component160to provide the results of the executed instructions. One or more of these components may, in accordance with an aspect of the present invention, be used to execute a Test Pending External Interruption instruction166, described further below.

Processor104also includes, in one embodiment, one or more registers170to be used by one or more of the functional components.

Another embodiment of a computing environment to incorporate and use one or more aspects is described with reference toFIG. 2A. In this example, a computing environment200includes, for instance, a native central processing unit (CPU)202, a memory204, and one or more input/output devices and/or interfaces206coupled to one another via, for example, one or more buses208and/or other connections. As examples, computing environment200may include a PowerPC processor or a pSeries server offered by International Business Machines Corporation, Armonk, N.Y.; and/or other machines based on architectures offered by International Business Machines Corporation, or other companies.

Native central processing unit202includes one or more native registers210, such as one or more general purpose registers and/or one or more special purpose registers used during processing within the environment. These registers include information that represents the state of the environment at any particular point in time.

Moreover, native central processing unit202executes instructions and code that are stored in memory204. In one particular example, the central processing unit executes emulator code212stored in memory204. This code enables the computing environment configured in one architecture to emulate another architecture. For instance, emulator code212allows machines based on architectures other than the z/Architecture, such as PowerPC processors, pSeries servers, or other servers or processors, to emulate the z/Architecture and to execute software and instructions developed based on the z/Architecture.

Further details relating to emulator code212are described with reference toFIG. 2B. Guest instructions250stored in memory204comprise software instructions (e.g., correlating to machine instructions) that were developed to be executed in an architecture other than that of native CPU202. For example, guest instructions250may have been designed to execute on a z/Architecture processor, but instead, are being emulated on native CPU202, which may be, for example, an Intel processor. In one example, emulator code212includes an instruction fetching routine252to obtain one or more guest instructions250from memory204, and to optionally provide local buffering for the instructions obtained. It also includes an instruction translation routine254to determine the type of guest instruction that has been obtained and to translate the guest instruction into one or more corresponding native instructions256. This translation includes, for instance, identifying the function to be performed by the guest instruction and choosing the native instruction(s) to perform that function.

Further, emulator code212includes an emulation control routine260to cause the native instructions to be executed. Emulation control routine260may cause native CPU202to execute a routine of native instructions that emulate one or more previously obtained guest instructions and, at the conclusion of such execution, return control to the instruction fetch routine to emulate the obtaining of the next guest instruction or a group of guest instructions. Execution of native instructions256may include loading data into a register from memory204; storing data back to memory from a register; or performing some type of arithmetic or logic operation, as determined by the translation routine.

Each routine is, for instance, implemented in software, which is stored in memory and executed by native central processing unit202. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software or some combination thereof. The registers of the emulated processor may be emulated using registers210of the native CPU or by using locations in memory204. In embodiments, guest instructions250, native instructions256and emulator code212may reside in the same memory or may be disbursed among different memory devices.

As used herein, firmware includes, e.g., the microcode or Millicode of the processor. It includes, for instance, the hardware-level instructions and/or data structures used in implementation of higher level machine code. In one embodiment, it includes, for instance, proprietary code that is typically delivered as microcode that includes trusted software or microcode specific to the underlying hardware and controls operating system access to the system hardware.

A guest instruction250that is obtained, translated and executed is, for instance, a Test Pending External Interruption instruction, described herein. The instruction, which is of one architecture (e.g., the z/Architecture), is fetched from memory, translated and represented as a sequence of native instructions256of another architecture (e.g., PowerPC, pSeries, Intel, etc.). These native instructions are then executed.

In one embodiment, the Test Pending External Interruption instruction tests for selected pending external interruptions, based, e.g., on one or more program-specified subclasses provided by the instruction, regardless of whether the machine is enabled for that class or classes of interruption and without clearing a pending external interruption condition. There may be a number of reasons to test for pending external interrupts. As examples, the control program (e.g., operating system) may be operating disabled for interruptions for a variety of reasons, including, for instance, managing queues, such as interruption queues; dispatching tasks; etc. Further, in various cases, the control program may need to determine the efficacy of an action before attempting it. Such example actions include dispatching, in a virtual environment, a process that is holding a critical system lock when the hypervisor that manages virtual machines of the environment is about to undispatch the logical CPU (potential for lock time-outs); dispatching a process when there are high-priority interruptions pending that may interfere with the process (e.g., malfunction alert, emergency signal); etc. Thus, in accordance with an aspect of the present invention, a testing mechanism is provided to test for pending external interruptions. This mechanism includes, for instance, a Test Pending External Interruption instruction. In one embodiment, the Test Pending External Interruption instruction is a single architected machine instruction at the hardware/software interface.

One example of a Test Pending External Interruption instruction is described with reference toFIG. 3. In one example, a Test Pending External Interruption (TPEI) instruction300includes an operation code (opcode) field302having an opcode to designate a test pending external interruption operation; a first register field (R1)304; and a second register field (R2)306. In one embodiment, the fields of the instruction are separate and independent from one another. However, in another embodiment, more than one field may be combined. Further, a subscript number associated with a field of the instruction denotes the operand to which the field applies. For instance, any field having a subscript 1 is associated with a first operand, any field having a subscript 2 is associated with a second operand, and so forth.

In one example, the register specified in R2306includes a mask310representing one or more external interruption subclasses that may be selected for testing for pending external interruptions. In one embodiment, these external interruptions originate from within a computer system having one or more processors (e.g., tightly coupled), but are external from a program, and are not from I/O devices or a channel subsystem. Example subclasses that may be selected for testing and associated example bit positions within the mask are shown below. In one embodiment, other bits in general register R2are reserved and are to contain zeros; otherwise, the program may not operate compatibility in the future.

Bit External Interruption Subclass30 Warning track interruption (e.g., used to warn a program (e.g., operating system) or processor that it has a grace period in which to perform a function (e.g., clean-up, etc.))48 Malfunction alert (e.g., used to warn a program or processor that another CPU in the configuration has experienced a malfunction (e.g., entered the checkstop mode or lost power))49 Emergency signal (e.g., used for high-priority inter-CPU signaling within a computer system)50 External call (e.g., used for inter-CPU signaling within a computer system)

Many other subclasses may be provided. In a further embodiment, one or more of the following subclasses may be selected for testing:

Bit Subclass52 Clock comparator (e.g., used to indicate that the current time-of-day clock has exceeded a pre-set comparand)53 CPU timer (e.g., used to indicate that a pre-set amount of CPU time has expired)54 Service signal (e.g., used to communicate with a logical service processor)57 Interruption key (e.g., used to indicate manual operator intervention)58 Measurement alert (e.g., used to indicate various changes in a CPU measurement facility)59 Timing alert (e.g., used to indicate various signals from an external time reference)

Other possibilities also exist.

In one embodiment, for this instruction, an interruption is considered to be pending for a subclass regardless of whether the subclass is enabled in a selected control register, such as control0, and regardless of the setting of a selected bit in another control register, such as a program status word (PSW), as further described herein. In one example, control register0is used to provide control information in the CPU. It includes indications for each of the subclasses listed above. In one example, the bit numbers listed above are the same bit numbers in the control register for the respective subclasses. When a bit in control register0is set, e.g., to one, the corresponding subclass is enabled. Further, in one example, the program status word is a control register that performs the functions of a status register and a program counter. It contains information used for proper program execution, including, but not limited to, a condition code, an instruction address, and other information. A selected bit, e.g., bit7, of the PSW designates an external mask and controls whether the CPU is enabled for interruptions by conditions included in an external class, such as the conditions listed above, as examples.

As indicated above, in addition to the R2field, the Test Pending External Interruption instruction also includes R1field304that designates a general register having a mask320of pending interruption subclasses, i.e., a mask that indicates whether external interrupts are pending for the selected subclasses.

In one example operation of the Test Pending External Interruption instruction, if an external interruption is pending for a designated subclass, the corresponding bit in general register R1is set to, e.g., one; otherwise, the corresponding bit in general register R1is set to, e.g., zero. Other bit positions in general register R1are set to zeros, in one example.

When a resulting bit position in general register R1contains, e.g., a one, the instruction completes by setting condition code1, as an example; otherwise, the instruction completes by setting condition code0, as an example. In particular, based on execution, there may be one of the following resulting condition codes:0—None of the tested subclasses of external interruptions is pending, or no subclasses were tested; or1—one or more of the tested subclasses of external interruptions are pending.

Moreover, the following program exceptions may occur: operation (test pending external interruption facility not installed); privileged operation; and/or transaction constraint (the executing transaction is constrained).

In one embodiment, the Test Pending External Interruption instruction does not take subclass enablement into consideration. Further, in one embodiment for the z/Architecture, the defined bit positions in general registers R1and R2match the bit positions of the corresponding external interruption subclass enablement controls in, e.g., control register0.

In a further aspect, the Test Pending External Interrupt instruction may be used in interpretive execution in, for instance, virtualized environments. In one embodiment, a hypervisor or host (e.g., z/VM) and processor (e.g., System z) hardware/firmware interact with each other in a controlled cooperative manner in order to process guest operating system operations without requiring the transfer of control from/to the guest operating system and the host. Guest operations can be executed directly without host intervention via a facility that allows instructions to be interpretatively executed for the guest, including a pageable storage mode guest. This facility provides an instruction, Start Interpretative Execution (SIE), which the host can issue, designating a control block, called a state description, which holds guest (virtual machine) state and controls, such as, for instance, indications of guest architectural mode, guest architectural features, guest registers, execution controls, and so forth. The SIE instruction places the machine into an interpretative execution mode in which guest instructions and interruptions are processed directly, until a condition requiring host attention arises. When such a condition occurs, interpretative execution is ended, and either a host interruption is presented, or the SIE instruction completes storing details of the condition encountered; the latter action is called interception. It is in this environment that the Test Pending External Interruption instruction may also be used.

For example, the Test Pending External Interruption instruction may be used to test for warning track interruptions which are available, in one embodiment, to guest configurations, and not non-guest configurations. Since the warning track facility is unavailable in non-guest configurations, in one embodiment, bit30of general register R1will not be set to, e.g., one for a configuration operating at host-level0(for example, the hypervisor). Other examples also exist.

In one example, interpretive execution of the Test Pending External Interruption instruction is subject to an execution control in the state description. In one embodiment, a selected bit, e.g., bit3of the execution control D (ECD) field of the state description, controls whether TPEI can be interpretively executed. If guest execution of TPEI is attempted, but ECD.3is not, e.g., one, then the guest execution is suppressed, and an instruction interception (e.g., code4) condition is recognized.

Further, an intervention requests (V) field of the state description may be examined based on execution of the TPEI instruction. For instance, the warning track (T) and external call (X) bits (that is, bits2and4respectively) of the V field may be examined based on the bits corresponding to those subclasses (e.g., bits30and50) being set in mask310.

Moreover, a new intervention requests extended (VX) field is defined in the state description. Bits0and1of the VX field represent thread specific indications that a guest emergency signal interruption and guest malfunction alert interruption, respectively, are pending. These bits are set and reset by the host program, and examined based on the interpretive execution of TPEI. For instance, bits0and1of the VX field are examined based on, e.g., bits49and48being set in mask310.

Other examples are also possible.

Further details regarding aspects of a Test Pending External Interruption instruction are described with reference toFIG. 4. In one example, an instruction to test for pending external interrupts, e.g., a Test Pending External Interrupt instruction, is obtained, STEP400. This instruction is, in one example, a single architected instruction. The instruction is then executed by a processor, STEP402.

The execution includes, for instance, determining, based on information provided by the instruction, one or more external interruption subclasses to be tested, STEP404. For instance, a mask included in a register designated by R2of the instruction includes a plurality of indicators (e.g., a plurality of bits). One or more of the indicators correspond to one or more external interruption subclasses that may be selected for testing for pending external interruptions. For instance, one indicator (e.g., bit30) corresponds to warning track interruptions; one indicator (e.g., bit48) corresponds to a malfunction alert; one indicator (e.g., bit49) corresponds to an emergency signal; and another indicator (e.g., bit50) corresponds to an external call. If an indicator is set to a particular value, e.g., one, then the subclass corresponding to the set indicator is to be tested for pending external interruptions. For example, if bit49is set to one, then a test for pending external interruptions for emergency signals is performed. One or more indicators may be set.

For each set indicator, a check is made as to whether external interruptions are pending for the subclass corresponding to the set indicator, STEP406. For instance, if bit49is set, a check is made as to whether external interruptions are pending for emergency signals, STEP406. In one example, for this check, in the case where no interpretive execution applies, the CPU keeps track of whether there are pending external interruptions, and the CPU tests its pending interruption latches to determine if an interruption is pending.

Where interpretive execution applies, hardware interruptions are presented to the host, and the host determines whether they are targeted to the guest. If they are targeted to the guest, the host sets pending interruption bits in the guest's state description. If the guest is enabled for the class of interruption when it is dispatched, they are presented to the guest; otherwise, the interruption remains pending. When the guest program executes a TPEI instruction, the CPU (e.g., Millicode) examines the pending bits in the guest's state description in order to formulate a response.

If an external interruption is pending for a subclass that is tested, then an indication is provided as such, STEP408. For instance, an indicator (e.g., a bit) in a mask provided in the register specified in R1that corresponds to the subclass being tested is set (e.g., to one). This same processing occurs for each tested subclass that has pending external interrupts.

Further, in one example, a summary indication indicating whether any of the tested subclasses of interruptions are pending is provided, for example, in a condition code. For example, if none of the tested subclasses of interruptions is pending, the condition code is set to0; if any of the tested subclasses of interruptions are pending, the condition code is set to1.

Described in detail herein is a Test Pending External Interruption (TPEI) instruction that determines whether one or more selected external interruptions are pending for the CPU executing the instruction. In one embodiment, TPEI determines whether one or more external interruptions are pending based on one or more specific subclasses; and it does so without clearing the one or more pending external interruptions. By testing for pending external interruptions, actions, including non-actions, may be taken to facilitate processing within a computing environment, improving performance thereof. The control program is able to determine if there is a pending interruption for a particular resource, while remaining disabled for that class of interruption. One or more aspects of the present invention are inextricably tied to computer technology and facilitate processing within a computer, improving performance thereof.

Although various embodiments are described above, these are only examples. For example, computing environments of other architectures can be used to incorporate and use one or more embodiments. Further, different instructions, instruction formats, instruction fields and/or instruction values may be used. Many variations are possible.