Internal voltage generation circuit and integrated circuit including the same

An internal voltage generation circuit includes an internal reference voltage generation unit configured to generate first and second reference voltages, a core voltage generation unit configured to receive the first reference voltage and to generate a core voltage based on the first reference voltage, and a bit line pre-charge voltage generation unit configured to receive the second reference voltage and to generate a bit-line pre-charge voltage based on the second reference voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2010-0107171, filed on Oct. 29, 2010, which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

Exemplary embodiments of the present invention relate to an internal voltage generation circuit and an integrated circuit including the same.

In general, semiconductor devices use an external power source voltage VDD_EX, which is supplied from the outside. Since the external power source voltage VDD_EX may have a change in level due to noise, the semiconductor devices are equipped with an internal voltage generation circuit for generating a stable internal voltage. Here, the internal voltage may include many different types of voltages, e.g., a core voltage VCORE which is used in a core region including a memory cell, a cell plate voltage VCP which is used as a plate voltage of a memory cell capacitor, and a bit line pre-charge voltage VBLP which is used for pre-charging a bit line. Here, the cell plate voltage VCP and the bit line pre-charge voltage VBLP are generated from the core voltage VCORE, and those are generated to have the level corresponding to a half of the core voltage VCORE in order to minimize power consumption. The cell plate voltage VCP and the bit line pre-charge voltage VBLP are generated through the same internal voltage generation unit. Hereafter, an example of the bit line pre-charge voltage VBLP is described.

FIG. 1is a block diagram illustrating a conventional integrated circuit.

Referring toFIG. 1, the integrated circuit100includes a source reference voltage generation unit110, a core reference voltage generation unit120, a core voltage generation unit130, a first internal circuit140, an over-driving unit150, a bit line pre-charge voltage generation unit160, and a second internal circuit170.

The source reference voltage generation unit110generates a source reference voltage VREF. The core reference voltage generation unit120generates a core reference voltage VREFC based on the source reference voltage VREF. The core voltage generation unit130generates a core voltage VCORE based on the core reference voltage VREFC.

The first internal circuit140performs a predetermined operation by receiving the core voltage VCORE. The over-driving unit150over-drives a core voltage VCORE terminal in response to an over-drive control signal ODP. The bit line pre-charge voltage generation unit160generates a bit line pre-charge voltage VBLP based on the core voltage VCORE. The second internal circuit170receives the bit line pre-charge voltage VBLP and performs a predetermined operation.

More specifically, the source reference voltage generation unit110generates the source reference voltage VREF based on an external power source voltage VDD_EX (not shown) and an external ground voltage VSS_EX (not shown), and the generated source reference voltage VREF is maintained at a stable level although the conditions of process, voltage and temperature (PVT) may be changed a bit. For example, the source reference voltage generation unit110may include a bandgap circuit or a Widlar circuit.

The over-driving unit150may operate to secure a fast sensing operation of a bit line sense amplifier (BLSA).

Hereafter, the operation of the integrated circuit100having the above structure is described.

The source reference voltage generation unit110receives the external power source voltage VDD_EX (not shown) and the external ground voltage VSS_EX (not shown), and generate the source reference voltage VREF. In particular, the source reference voltage generation unit110generates a stable source reference voltage VREF although the conditions of process, voltage and temperature (PVT) may be changed a bit.

The core reference voltage generation unit120generates the core reference voltage VREFC for generating the core voltage VCORE based on the source reference voltage VREF generated in the source reference voltage generation unit110, and applies the generated core reference voltage VREFC to the core voltage generation unit130. Here, the core reference voltage generation unit120may generate the core reference voltage VREFC through a down-conversion method.

The core voltage generation unit130generates the core voltage VCORE of a predetermined voltage level based on the core reference voltage VREFC and supplies the generated core voltage VCORE to the first internal circuit140.

Here, the bit line pre-charge voltage generation unit160generates the bit line pre-charge voltage VBLP based on the core voltage VCORE and supplies the generated bit line pre-charge voltage VBLP to the second internal circuit170. The bit line pre-charge voltage generation unit160may also generate the bit line pre-charge voltage VBLP through the down-conversion method, just as the core voltage generation unit130.

Meanwhile, the over-driving unit150over-drives the core voltage VCORE terminal in response to the over-drive control signal ODP.

The conventional integrated circuit100of the above structure, however, may malfunction as follows.

FIG. 2is a timing diagram describing the operation of the integrated circuit100.

Referring toFIG. 2, the core voltage VCORE maintains a predetermined target level by the core voltage generation unit130, and the bit line pre-charge voltage VBLP maintains a predetermined target level by the bit line pre-charge voltage generation unit160. In this state, when the over-drive control signal ODP is enabled upon receipt of an active command ACT, the voltage level of the core voltage VCORE terminal is increased while the over-driving unit150performs an over-driving operation. The increased core voltage VCORE, however, is used as a reference voltage of the bit line pre-charge voltage generation unit160. Therefore, the bit line pre-charge voltage VBLP generated in the bit line pre-charge voltage generation unit160is also increased during the time that the core voltage VCORE is increased. In this case, the second internal circuit170to which the increased bit line pre-charge voltage VBLP is supplied may malfunction.

SUMMARY OF THE INVENTION

An embodiment of the present invention is directed to an integrated circuit which may maintain a bit line pre-charge voltage VBLP and a cell plate voltage VCP at target levels although a core voltage VCORE terminal is over-driven.

In accordance with an exemplary embodiment of the present invention, an internal voltage generation circuit includes an internal reference voltage generation unit configured to generate first and second reference voltages; a core voltage generation unit configured to receive the first reference voltage and to generate a core voltage based on the first reference voltage; a bit line pre-charge voltage generation unit configured to receive the second reference voltage and to generate a bit-line pre-charge voltage based on the second reference voltage.

In accordance with another exemplary embodiment of the present invention, an integrated circuit includes a reference voltage generation circuit configured to generate a first reference voltage corresponding to a core voltage and a second reference voltage corresponding to a bit-line pre-charge voltage; a core voltage generation unit configured to generate the core voltage based on the first reference voltage; and a bit line pre-charge voltage generation unit configured to generate the bit-line pre-charge voltage based on the second reference voltage.

The reference voltage generation circuit may include a source reference voltage generation unit configured to generate a source reference voltage by using an external power source voltage and an external ground voltage; a first reference voltage generation unit configured to generate the first reference voltage based on the source reference voltage; and a second reference voltage generation unit configured to generate the second reference voltage based on the source reference voltage. The integrated circuit may further include: an over-driving unit configured to supply an external power source voltage to a terminal providing the core voltage in response to an over-drive control signal.

In accordance with another exemplary embodiment of the present invention, an integrated circuit includes a reference voltage generation circuit configured to generate a first reference voltage corresponding to a core voltage and a second reference voltage corresponding to a cell plate voltage; a core voltage generation unit configured to generate the core voltage based on the first reference voltage; and a cell plate voltage generation unit configured to generate the cell plate voltage based on the second reference voltage.

The reference voltage generation circuit may include a source reference voltage generation unit configured to generate a source reference voltage by using an external power source voltage and an external ground voltage; a first reference voltage generation unit configured to generate the first reference voltage based on the source reference voltage; and a second reference voltage generation unit configured to generate the second reference voltage based on the source reference voltage. The integrated circuit may further include: an over-driving unit configured to supply an external power source voltage to a terminal providing the core voltage in response to an over-drive control signal.

DESCRIPTION OF SPECIFIC EMBODIMENTS

FIG. 3is a block diagram illustrating an integrated circuit in accordance with an embodiment of the present invention.

Referring toFIG. 3, the integrated circuit200includes an internal reference voltage generation circuit210, a core voltage generation unit220, a first internal circuit230, an over-driving unit240, a bit line pre-charge voltage generation unit250, and a second internal circuit260.

The internal reference voltage generation circuit210receives an external power source voltage VDD_EX (not shown) and an external ground voltage VSS_EX (not shown) and generates a core reference voltage VREFC and a bit line pre-charge reference voltage VREFBLP. The core voltage generation unit220generates a core voltage VCORE based on the core reference voltage VREFC. The first internal circuit230performs a predetermined operation by receiving the core voltage VCORE. The over-driving unit240over-drives a core voltage VCORE terminal in response to an over-drive control signal ODP. The bit line pre-charge voltage generation unit250generates a bit line pre-charge voltage VBLP based on the bit line pre-charge reference voltage VREFBLP. The second internal circuit260receives the bit line pre-charge voltage VBLP and performs a predetermined operation.

FIG. 4is a block diagram illustrating the internal reference voltage generation unit210shown inFIG. 3.

Referring toFIG. 4, the internal reference voltage generation circuit210includes a source reference voltage generation unit212, a core reference voltage generation unit214, and a bit line pre-charge reference voltage generation unit216.

The source reference voltage generation unit212receives the external power source voltage VDD_EX and the external ground voltage VSS_EX and generates a source reference voltage VREF. The core reference voltage generation unit214generates the core reference voltage VREFC based on the source reference voltage VREF. The bit line pre-charge reference voltage generation unit216generates the bit line pre-charge reference voltage VREFBLP based on the source reference voltage VREF. Here, the core voltage VCORE is a voltage used for a core region including a memory cell (not shown), and the bit line pre-charge voltage VBLP is a voltage used for pre-charging a bit line. Meanwhile, the bit line pre-charge voltage VBLP may be also used as a plate voltage of a memory cell capacitor, which is referred to as a cell plate voltage VCP.

Here, the source reference voltage generation unit212may include a bandgap circuit or a Widlar circuit to generate a stable source reference voltage VREF although the conditions of process, voltage and temperature (PVT) are changed.

FIG. 5Ais a block diagram illustrating the core reference voltage generation unit214shown inFIG. 4.FIG. 5Bis a block diagram illustrating the bit line pre-charge reference voltage generation unit216shown inFIG. 4.

Referring toFIG. 5A, the core reference voltage generation unit214includes a first dividing block214_1, a first comparison block214_2, and a first driving block214_3. The first dividing block214_1is disposed between a core reference voltage VREFC terminal and an external ground voltage VSS_EX terminal, and divides the voltage loaded between the core reference voltage VREFC terminal and the external ground voltage VSS_EX terminal at a predetermined first division rate. The first comparison block214_2compares a first divided voltage VDIV1obtained from the division in the first dividing block214_1with the source reference voltage VREF. The first driving block214_3drives the core reference voltage VREFC terminal with the external power source/supply voltage VDD_EX in response to an output signal COMP1of the first comparison block214_2.

Here, the first dividing block214_1includes a first resistor R1coupled between the core reference voltage VREFC terminal and a first divided voltage VDIV1terminal and a second resistor R2coupled between the first divided voltage VDIV1terminal and the external ground voltage VSS_EX terminal. The first comparison block214_2includes a first differential amplifier OP1which receives the source reference voltage VREF through a negative (−) input terminal, receives the first divided voltage VDIV1through a positive (+) input terminal, and outputs a comparison signal COMP1. Also, the first driving block214_3includes a first PMOS transistor P1which receives the comparison signal COMP1of the first comparison block214_2as a gate input and includes a source and a drain coupled to an external power source voltage VDD_EX terminal and the core reference voltage VREFC terminal, respectively.

Referring toFIG. 5B, the bit line pre-charge reference voltage generation unit216includes a second dividing block216_1, a second comparison block216_2, and a second driving block216_3. The second dividing block216_1is disposed between a bit line pre-charge reference voltage VREFBLP terminal and the external ground voltage VSS_EX terminal, and divides the voltage loaded between the bit line pre-charge reference voltage VREFBLP terminal and the external ground voltage VSS_EX terminal at a predetermined second division rate. The second comparison block216_2compares a second divided voltage VDIV2obtained from the division in the second dividing block216_1with the source reference voltage VREF. The second driving block216_3drives the bit line pre-charge reference voltage VREFBLP terminal with the external power source voltage VDD_EX in response to an output signal COMP2of the second comparison block216_2.

Here, the second dividing block216_1includes a third resistor R3coupled between the bit line pre-charge reference voltage VREFBLP terminal and a second divided voltage VDIV2terminal and a fourth resistor R4coupled between the second divided voltage VDIV2terminal and the external ground voltage VSS_EX terminal. The second comparison block216_2includes a second differential amplifier OP2which receives the source reference voltage VREF through a negative (−) input terminal, receives the second divided voltage VDIV2through a positive (+) input terminal, and outputs a comparison signal COMP2. Also, the second driving block216_3includes a second PMOS transistor P2which receives the comparison signal COMP2of the second comparison block216_2as a gate input and includes a source and a drain coupled to the external power source voltage VDD_EX terminal and the bit line pre-charge reference voltage VREFBLP terminal, respectively.

FIG. 6is a block diagram illustrating the core voltage generation unit220shown inFIG. 3.

Referring toFIG. 6, the core voltage generation unit220includes a third dividing block222, a third comparison block224, and a third driving block226. The third dividing block222is disposed between the core voltage VCORE terminal and the external ground voltage VSS_EX terminal, and divides the voltage loaded between the core voltage VCORE terminal and the external ground voltage VSS_EX terminal at a predetermined third division rate. The third comparison block224compares a third divided voltage VDIV3obtained from the division in the third dividing block222with the core reference voltage VREFC. The third driving block226drives the core voltage VCORE terminal with the external power source voltage VDD_EX in response to an output signal COMP3of the third comparison block224.

Here, the third dividing block222includes a fifth resistor R5coupled between the core voltage VCORE terminal and a third divided voltage VDIV3terminal of the third dividing block222and a sixth resistor R6coupled between the third divided voltage VDIV3terminal of the third dividing block222and the external ground voltage VSS_EX terminal. The third comparison block224includes a third differential amplifier OP3which receives the core reference voltage VREFC through a negative (−) input terminal, receives the third divided voltage VDIV3through a positive (+) input terminal, and outputs a comparison signal COMP3. Also, the third driving block226includes a third PMOS transistor P3which receives the comparison signal COMP3of the third comparison block224as a gate input and includes a source and a drain coupled to the external power source voltage VDD_EX terminal and the core voltage VCORE terminal, respectively.

Referring toFIG. 7, the over-driving unit240includes a first NMOS transistor N1which receives an over-drive control signal ODP as a gate input and includes a drain and a source coupled to the external power source voltage VDD_EX terminal and the core voltage VCORE terminal, respectively. Here, the over-drive control signal ODP may be enabled to have a higher voltage level than the external power source voltage VDD_EX so as to over-drive the core voltage VCORE terminal in a duration where the over-driving unit240is activated. For example, the over-drive control signal ODP has a boost voltage VPP level in the duration where the over-driving unit240is activated.

FIG. 8is a block diagram illustrating the bit line pre-charge voltage generation unit250shown inFIG. 3.

Referring toFIG. 8, the bit line pre-charge voltage generation unit250includes a fourth comparison block252, a pull-up driving block254, and a pull-down driving block256. The fourth comparison block252compares the bit line pre-charge reference voltage VREFBLP with the bit line pre-charge voltage VBLP. The pull-up driving block254pull-up drives a bit line pre-charge voltage VBLP terminal with the external power source voltage VDD_EX in response to an output signal COMP4of the fourth comparison block252. The pull-down driving block256pull-down drives the bit line pre-charge voltage VBLP terminal with the external ground voltage VSS_EX in response to the output signal COMP4of the fourth comparison block252.

Here, the fourth comparison block252includes a fourth differential amplifier OP4which receives the bit line pre-charge reference voltage VREFBLP through a negative (−) input terminal, receives the bit line pre-charge voltage VBLP through the positive (+) input terminal, and outputs a comparison signal COMP4. The pull-up driving block254includes a fourth PMOS transistor which receives the comparison signal COMP4of the fourth comparison block252as a gate input and includes a source and a drain coupled to the external power source voltage VDD_EX terminal and the bit line pre-charge voltage VBLP terminal, respectively. Also, the pull-down driving block256includes a second NMOS transistor which receives the comparison signal COMP4of the fourth comparison block252as a gate input and includes a drain and a source coupled to the bit line pre-charge voltage VBLP terminal and the external ground voltage VSS_EX terminal, respectively.

Hereafter, the operation of the integrated circuit200having the above-described structure is described in accordance with an embodiment of the present invention.

First, the internal reference voltage generation circuit210receives an external power source voltage VDD_EX (not shown) and an external ground voltage VSS_EX (not shown) and generates a core reference voltage VREFC and a bit line pre-charge reference voltage VREFBLP. More specifically, the source reference voltage generation unit212generates a stable source reference voltage VREF although the conditions of process, voltage and temperature (PVT) may be changed, and the core reference voltage generation unit214generates a core reference voltage VREFC corresponding to a core voltage VCORE based on the source reference voltage VREF generated in the source reference voltage generation unit212, and the bit line pre-charge reference voltage generation unit216generates a bit line pre-charge reference voltage VREFBLP corresponding to a bit line pre-charge voltage VBLP based on the source reference voltage VREF generated in the source reference voltage generation unit212.

Subsequently, the core voltage generation unit220maintains the core voltage VCORE at a constant level based on the core reference voltage VREFC. The first internal circuit230receives the core voltage VCORE which is generated in the core voltage generation unit220and performs a predetermined internal operation. For example, based on the core voltage VCORE, the first internal circuit230senses and amplifies a data of a bit line after an active command ACT is applied.

Also, the bit line pre-charge voltage generation unit250maintains the bit line pre-charge voltage VBLP at a constant level based on the bit line pre-charge reference voltage VREFBLP. The second internal circuit260receives the bit line pre-charge voltage which is generated in the bit line pre-charge voltage generation unit250and performs a predetermined internal operation. For example, the second internal circuit260pre-charges the bit line based on the bit line pre-charge voltage VBLP after a data of the bit line is sensed and amplified.

When the first internal circuit230senses and amplifies a data of a bit line after the active command ACT is applied, an over-driving operation is performed together. The over-driving operation is performed to quickly complete the sense and amplification operation of a bit line sense amplifier (BLSA). This is described hereafter with reference toFIG. 9.

FIG. 9is a timing diagram describing an operation of the integrated circuit shown inFIG. 3.

When an over-drive control signal ODP is enabled upon receipt of the active command ACT, the over-driving unit240over-drives the core voltage VCORE terminal in response to the enabled over-drive control signal ODP. Accordingly, the voltage level of the core voltage VCORE terminal is increased. However, since the bit line pre-charge voltage VBLP is not affected by the over-driving operation, it may maintain a predetermined target voltage level. This is because the core voltage generation unit220and the bit line pre-charge voltage generation unit250receive reference voltages separately and generate predetermined voltages, respectively.

According to the embodiment of the present invention, although the voltage level of the core voltage VCORE is increased according to the over-driving operation, it does not affect the bit line pre-charge voltage VBLP. Therefore, the second internal circuit260which receives the bit line pre-charge voltage VBLP may perform a stable internal operation, which is advantageous.

According to an embodiment of the present invention, although the voltage level of a core voltage VCORE terminal is increased by an active operation, which is an over-driving operation, the generations of the bit line pre-charge voltage VBLP and the cell plate voltage VCP are not affected because an independent reference voltage for the bit line pre-charge voltage VBLP and the cell plate voltage VCP is generated and supplied. Therefore, stable bit line pre-charge voltage VBLP and cell plate voltage VCP are generated, and an internal circuit which receives the stable bit line pre-charge voltage VBLP and cell plate voltage VCP may also perform a stable operation. Consequently, desired operation reliability of the integrated circuit is obtained.

For example, although a bit line pre-charge voltage is described as an example in the above-described embodiments, the exemplary embodiments of the present invention may be applied to any internal voltage, such as a cell plate voltage that is generated based on a core voltage.