Fan-out unit and thin-film transistor array substrate having the same

A fan-out unit which can control a resistance difference among channels with efficient space utilization and a thin-film transistor (TFT) array substrate having the fan-out unit are presented. The fan-out unit includes: an insulating substrate; a first wiring layer which is formed on the insulating substrate and connected to a pad; a second wiring layer which is formed on the insulating substrate and connected to a TFT; and a resistance controller which is connected between the first wiring layer and the second wiring layer and includes a plurality of first resistors extending parallel to the first wiring layer and a plurality of second resistors extending perpendicular to the first resistors and alternately connecting to the first resistors, wherein the first resistors are longer than the second resistors.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims, under 35 U.S.C. §119, priority to and the benefit of Korean Patent Application No. 10-2008-0133655 filed in the Korean Intellectual Property Office on Dec. 24, 2008, the entire content of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the design and fabrication of a fan-out unit which connects a thin-film transistor (TFT) array on a substrate with input/output IC circuitry for an LCD display system.

2. Description of the Related Art

Liquid crystal displays (LCDs) are among the most widely used flat panel displays. An LCD consists of a common electrode substrate, a control substrate having a thin-film transistor (TFT) array pattern, and a layer of liquid crystal solution sandwiched in between the substrates. When a voltage related to image data is applied across the liquid crystal layer in each pixel, an incident light is allowed to pass through in varying amounts according to the image data, thus constituting different levels of display intensity in the pixel. Therefore, a sequence of voltages corresponding to an image data array can generate a desired image on an LCD screen.

A fan-out unit is used to connect a group of gate lines or a group of data lines to a gate integrated circuit (IC) or a data IC and is typically formed in a peripheral region of a TFT array substrate. Usually the channels in a fan-out unit have different lengths and thus can have non-uniform resistance values among the gate lines or data lines, which affects image consistency. Therefore, it is desired to equalize the fan-out channel lengths.

In the past, the fan-out channels were arranged in zigzag forms to equalize the channel resistance. However, size and density of LCD have been increasing, and the channel numbers continue to grow on the ever shrinking edge spaces available for the fan-out circuitry. Consequently, there is little room left to improve resistance variation by adjusting the channel lengths only. Furthermore, a zigzag wire form bends a channel and increases its resistance. Thus, it is desired to minimize the channel bending.

SUMMARY OF THE INVENTION

Present invention provides a fan-out unit with minimum channel resistance non-uniformity and efficient space utilization and a thin-film transistor (TFT) array substrate having the same fan-out unit.

One aspect of the present invention provides a fan-out unit including: an insulating substrate; a first wiring layer formed on the insulating substrate and connecting to a pad; a second wiring layer formed on the insulating substrate and connects to a TFT; and a resistance controller which connects the first wiring layer to the second wiring layer and includes a plurality of first resistors extending parallel to the first wiring layer and a plurality of second resistors extending perpendicular to the first resistors and alternately connect to the first resistors, wherein the first resistors are longer than the second resistors.

Another aspect of the present invention provides a TFT array substrate including: an insulating substrate; and a fan-out unit, wherein the fan-out unit includes: a first wiring layer formed on the insulating substrate and connects to a pad; a second wiring layer formed on the insulating substrate and connects to a TFT; and a resistance controller which connecting the first wiring layer to the second wiring layer, and includes a plurality of first resistors extending parallel to the first wiring layer and a plurality of second resistors extending perpendicular to the first resistors and alternately connected to the first resistors, wherein the first resistors are longer than the second resistors.

DETAILED DESCRIPTION OF THE INVENTION

Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

Like reference numerals refer to like elements throughout the specification. Spatially relative terms, such as “below,” “beneath,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures.

Hereinafter, a display panel including a fan-out unit on a thin-film transistor (TFT) array substrate according to an exemplary embodiment of the present invention will be described in detail.FIG. 1is a partial perspective view of a display panel1including fan-out units120and160according to an exemplary embodiment of the present invention.FIG. 2is a partial plane view of a TFT array substrate100in a display device shown inFIG. 1.

InFIG. 1andFIG. 2, the display device may include the display panel1, first flexible films110, second flexible films115, and a printed circuit board (PCB)130.

The display panel1includes the TFT array substrate100and an upper substrate200facing the TFT array substrate100. The TFT array substrate100includes a gate line26(seeFIG. 3), a data line62(seeFIG. 3), a thin-film transistor TFT (seeFIG. 3), and a pixel electrode82(seeFIG. 3). The upper substrate200includes a black matrix, a color filter, and a common electrode. In addition, a liquid crystal layer (not shown) is interposed between the upper substrate200and the TFT array substrate100.

Each of the first flexible films110is connected to the gate line26formed on the TFT array substrate100. A gate-driving chip111may be mounted on each of the first flexible films110. The gate-driving chip111is a semiconductor chip and may be mounted on one of the first flexible films110using, for example, wiring pattern and tape automated bonding (TAB) methods. The gate-driving chip111is electrically connected to the gate line26and transmits a gate signal to the gate line26. Each channel of the fan-out units120connects a gate line26and its corresponding first flexible films110. One side of every fan-out unit120connects to a pad112and is narrower than the other side which connects to the gate line26. Thus, each of the first flexible films110contacts the pad112and the gate line26as well.

Each of the second flexible films115may include a wiring pattern formed on a base film and a data driving chip116electrically connected to the wiring pattern. The data driving chip116is a semiconductor chip and may be mounted on one of the second flexible films115using the wiring pattern and TAB methods. Each of the second flexible films115delivers a data driving signal to the transistor TFT via the data line62. Each channel of the fan-out units160connects the data line62to a corresponding flexible film115. One side of each of the fan-out units160connects to a pad117and is narrower than the other side which connects to the data line62. Each of the second flexible films115contacts the pad117and the data line62as well.

Hereinafter, the TFT array substrate100according to the present embodiment will be described in more detail with reference toFIG. 3andFIG. 4.FIG. 3is an enlarged view of region A in the TFT array substrate100shown inFIG. 2.FIG. 4is a cross-sectional view of the TFT array substrate taken along the line IV-IV′ inFIG. 3.

InFIG. 3andFIG. 4, an insulating substrate10is made of transparent glass or a material having low thermal expansion and high light-transmitting properties, such as transparent plastics. Gate wiring layers (i.e., a gate electrode22, a gate line26, and a storage line29) are formed on the insulating substrate10. The gate wiring layers typically contain a metal material, for example, aluminum and an aluminum alloy, silver and a silver alloy, copper and a copper alloy, molybdenum and a molybdenum alloy, chrome (Cr), titanium (Ti) or tantalum (Ta). In addition, the gate wiring layers may contain multiple conductive films (not shown), each having distinctive physical characteristics.

The storage line29is formed parallel to the gate line26. The lines in the gate wiring layers extend in a first direction, e.g., the horizontal direction on the insulating substrate10. The gate electrode22protrudes from the gate line26, and the storage line29lies parallel to the gate line26. TFT terminals are formed by a gate electrode22, a source electrode65and a drain electrode66.

A gate insulating film30, made of silicon nitride (SiNx), is disposed on the gate wiring layers. A semiconductor layer40, made of hydrogenated amorphous silicon or polycrystalline silicon, is disposed on the gate insulating film30. The semiconductor layer40may have various shapes; for example, it may be an island or a line. In the present embodiment, the semiconductor layer40is an island, disposed under the data line62and extending above the gate electrode22. The semiconductor layer40may also be lines formed by the same patterning process as the data line62. Ohmic contact layers55and56are disposed on the semiconductor layer40and are made of materials such as silicide or n+ hydrogenated amorphous silicon doped with n-type impurities in high concentration. The ohmic contact layers55and56improve contact characteristics between the semiconductor layer40and the source electrode65or the drain electrode66, if the improvement is necessary.

The ohmic contact layers55and56may form various shapes. They may be islands or lines depending on their locations. When they are disposed under the drain electrode66and the source electrode65, they form island-shapes, as in the present embodiment. When they extend to under the data line6, they form lines.

Data wiring layers are formed on the ohmic contact layers55and56and the gate insulating film30. The data wiring layers include the data line62, the source electrode65, and the drain electrode66.

The data line62extends in a second direction, e.g., a vertical direction, crossing the gate line26. The data line62receives a data signal and delivers it to the source electrode65.

The source electrode65extends from the data line62. One end of the source electrode65connects to the data line62, and the other end is disposed above and overlaps a portion of the semiconductor layer40. One end of the drain electrode66is disposed above and overlaps a portion of the semiconductor layer40. The drain electrode66and the source electrode65are separated from each other by a predetermined gap.

The source electrode65, the drain electrode66, and the gate electrode22constitute a TFT transistor, a switching device where a voltage applied to the gate electrode22switches on an electric current between the source electrode65and the drain electrode66.

The data wiring layers may be a single film or multiple films including aluminum, chrome, molybdenum, tantalum, and titanium. The data wiring layers may be made of chrome, molybdenum-based metals, or refractory metals such as tantalum or titanium. In addition, the data wiring layers may have a multi-film structure (not shown) composed of a lower film (not shown), made of a refractory metal, and an upper film disposed on the lower film, made of a low resistivity material. Examples of multi-film structures include a chrome lower film and an aluminum upper film, or an aluminum lower film and a molybdenum upper film. Alternatively, the multi-film structure may be a triple-film structure containing molybdenum, aluminum, and molybdenum films.

A passivation layer70is coated on the data wiring layers and an exposed portion of the semiconductor layer40. The passivation layer70may be made of a photoresist, an inorganic material such as silicon nitride or silicon oxide, or a low-k dielectric material such as a-Si:C:O or a-Si:O:F, via a plasma enhanced chemical vapor deposition process (PECVD). When the passivation layer70is made of an organic material, it may have a dual-film structure having an upper organic film and a lower inorganic film such as silicon nitride or silicon oxide, thus preventing the organics in the passivation layer70from contacting the exposed semiconductor layer40.

A contact hole76is formed in the passivation layer70to expose the drain electrode66.

A pixel electrode82is disposed on the passivation layer70with the shape of a pixel, and is electrically connected to the drain electrode66via the contact hole76.

A data voltage applied to the pixel electrode82and the common electrode (not shown) aligns the liquid crystal molecules in between and thus adjusts light transmittance from a backlight assembly (not shown) to display an image on the liquid crystal display.

The pixel electrode82is made of a transparent conductor, such as indium tin oxide (ITO) or indium zinc oxide (IZO), in a transmission type of LCD, or a reflective conductor such as aluminum in a reflective type of LCD. Fan-out units120and160connect TFT arrays on the substrate to external devices. Fan-out units120are gate fan-out units, and fan-out units160are data fan-out units160. Each channel of the fan-out unit120connects a gate line26to a corresponding connector in the first flexible film110. Similarly, each channel of the fan-out unit160connects a data line62to a corresponding connector in the second flexible film115. The fan-out units120and160are located around the TFT arrays in the peripheral regions of substrate100.

Hereinafter, the fan-out units120and160, according to the present embodiment, will be described in detail with reference toFIGS. 5A and 5B.FIG. 5Ais an enlarged view of a region B of the TFT array substrate100shown inFIG. 2.FIG. 5Bis an enlarged view of a channel included in a fan-out unit shown inFIG. 5A.

Each fan-out unit includes a plurality of channels. For example, three channels, C1through C3, are shown inFIG. 5A. One terminal of each channel is connected to a pad112or117, and the other terminal is connected to a gate line26or a data line62. Each channel delivers a signal from the pad112or117to the gate line26or the data line62.

The channels of a fan-out unit are designed such that the electrical resistance from a pad to its corresponding gate line or data line is substantially equal in all fan-out units. This goal is accomplished by forming a fan-out channel in three parts: 1) a first wiring layer at the end of the pad, for example,162a,162b, or162c; 2) a second wiring layer at the input end of the gate or data line, for example,163a,163b, or163c; and 3) a resistance controller part in between the first and the second wire layers, for example,161a,161b, or161c. The resistance controllers have adjustable lengths in a winding pattern. If each of the channels C1through C3is formed such that the pad112or117is located at the shortest distance away from the gate line26or the data line62, there is a large difference between lengths of the channels C1through C3. When the channels C1through C3have different lengths, they have difference resistance values. Therefore, as shown inFIG. 5A, the channels C1through C3respectively include resistance controllers161athrough161cto eliminate the resistance difference therebetween.

The fan-out unit, i.e., the first wiring layers162athrough162c, the second wiring layers163athrough163c, and the resistance controllers161athrough161cmay be formed together in the same layer. The gate line26and its related fan-out units120may be formed together in the same layer, and the data line62and its related fan-out units160may be formed together in the same layer.

On the other hand, the resistance controllers161athrough161cmay not be formed in the same layer as the gate line26or the data line62. In some cases, the resistance controllers161athrough161cin each gate fan-out unit120may be formed as separate bridge metals (not shown) in a data metal layer62connecting the first wiring layers162athrough162cto the second wiring layers163athrough163c, respectively. Similarly, the resistance controllers161athrough161cconnecting to the data line62in each data fan-out unit160may be formed using a gate metal layer or pixel metal layer.

The resistance controllers161athrough161cin each fan-out unit120and160may be designed in a winding pattern in a plane parallel to the second wiring layers163athrough163cof channels C1through C3. In addition, the second wiring layers163athrough163cof each gate fan-out unit120may extend parallel to the gate line26, and similarly, the second wiring layers163athrough163cof each data fan-out unit160may extend parallel to the data line62. If the resistance controllers161athrough161care formed in a winding pattern in a layer parallel to the second wiring layers163athrough163c, respectively, the number of bends in each resistance controllers161athrough161cshould be minimized to not reduce resistance, which will be described in detail below. The respective resistance controllers161athrough161cin channels C1through C3have different lengths, and therefore different resistance.

FIG. 5Billustrates the structure of one fan-out channel including a first wiring layer162a, a second wiring layer163a, and a resistance controller161a, which consists multiple sections of resistors164aand168a. Among the sections of resistors, those extending parallel to the first wiring layer162aare named the first resistors, i.e.164ato166a, and those extending perpendicular to the first wiring layer are named the second resistors, i.e.167ato168a. The first resistors are parallel to each other at predetermined intervals, and are connected to each other by an adjacent second resistor, for example,167aconnects164ato165a. The second resistors have a fixed length, and the first resistors have variable lengths enabling resistance adjustment. The first resistors may be longer than the second resistors.

FIG. 6illustrates six exemplary bending angles which connect the first resistors to the second resistors in the wiring pattern. Table 1 lists the calculated relative resistance values of the structures inFIG. 6.

Table 1 shows that the resistance values increase with the bending angle, but large angle takes away space. Therefore, it is desirable to use 90 degree angle connections to maximize the control efficiency.

FIG. 7illustrates a variety of exemplary connecting structures, all of which are designed to have the same continuous length, but are bent different number of times at 90 degree angle.

TABLE 2Comparison of resistance of the structures in FIG. 7 (calculated)Wiring PatternNo. of BendsResistance ratio (%)0100197.7293.8392.1488.1587.6685.3783.6

Table 2 shows that the resistance decreases with more bends in the wiring pattern, as the result of a shortened conducting path at each bend. Paths of electrons are reduced at a wiring bend. Therefore, it is more efficient to use less bends to retain resistance.

FIGS. 8A-8Cexplain the resistance control methods used in three resistance controllers260athrough260c.

InFIG. 8A, a resistance controller260aincludes first resistors261aand263a, a second resistor262aconnecting261aand263aat the bends264a.

A total resistance from261ato263ais determined by the total length of all the first and second resistors and their connecting bends. In general, bends contribute little to the total resistance, thus, the bend resistance is often omitted in the total resistance calculation. Therefore, the length of the resistance controller260ainFIG. 8Ais the sum length of the first and the second of resistors 2L1+S.

InFIG. 8B, a resistance controller260bincludes first resistors261band263b, a second resistor262bconnecting261band263bat the bends264b. The dummy sections265bare not electrically active, but help to maintain stable process conditions by providing an equivalent area density. Likewise, the resistance controller260bhas a total length 2 L2+S.

InFIG. 8C, a resistance controller260cincludes first resistors261cand263c, a second resistor262cconnecting261band263bat the bends264c. The electrically inactive dummy sections265cextend away from the bends264cand are longer than the bends in this case inFIG. 8B. Similarly, the resistance controller260bhas a total length 2 L3+S. The dummy wiring layers265care longer than the dummy wiring layers265bof the second resistance controller260b. Thus, an electric flow actually flows through a shorter portion of the third resistance controller260cthan that of the second resistance controller260b.

Among the three resistance controllers described inFIG. 8A to 8C, controller260ahas the highest resistance because of its longest active length, and260chas the lowest resistance from its shortest active length. That is, the resistance values of the first through third resistance controllers260athrough250ccan be easily controlled by adjusting the positions of the connecting wiring layers262athrough262c, respectively. In this case, the wiring layers of each of the first through third resistance controllers260athrough260chave the same density. That is, if the resistance value of a resistance controller can be easily controlled while the densities of wiring layers thereof are maintained equal, conditions for forming each channel, e.g., for an ashing process for forming wiring, can be maintained constant.FIGS. 9A-9Cillustrate additional types of resistance controllers according to another embodiment of the present invention.

InFIG. 9A, first resistors330a,340aand350aand second resistors360a,361a,362aand363aare alternately arranged between a first wiring layer310aand a second wiring layer320a. The first resistors330a,340a,350ahave equal length, are parallel to each other and connected by the second resistors360athrough363a. Precise control of the resistance value is accomplished by adjusting the contacting locations of the two outer resistors330aand350aand the bridging second resistors360aand363a.

InFIG. 9B, first resistors330bthrough350band second resistors360bthrough363bare alternately arranged between a first wiring layer310band a second wiring layer320b. The first resistors330bthrough350bof equal length are arranged parallel to each other and connected by the second resistors360bthrough363b. The second resistors361band363bare formed at one end of the first resistors330bthrough350bnear the second wiring layer. However, the locations of the second resistors360band362bcan be adjusted to control the resistance values of the first resistors330bthrough350b.

InFIG. 9C, first resistors330cthrough350cand second resistors360cthrough363care alternately arranged between a first wiring layer310cand a second wiring layer320c. The first resistors330cthrough350chave equal lengths, are parallel to each other, and connected by the second resistors360cthrough363c. The locations of the second resistors360cthrough363care adjustable with respect to the ends of the first resistors they are connecting to, thus the precise control of the resistance values of330cto350cis achieved.

While the present disclosure of invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art in light of the foregoing that various changes in form and detail may be made therein without departing from the spirit and scope of the present teachings. The exemplary embodiments should be considered in a descriptive sense only and not for purposes of limitation.