Synchronous rectifier circuit

A first variable voltage source VS1 generates a first threshold voltage VZC1 which is variable. A first zero current detection comparator ZC_CMP1 compares a first voltage VAC1 at a first input node AC1 with the first threshold voltage VZC1, and generates a ZC_DET1 signal which indicates a comparison result. A first adjustment comparator ADJ_CMP1 compares the first voltage VAC1 with a first reference voltage VTH1. A first adjustment unit adjusts the first threshold voltage VZC1 generated by the first variable voltage source VS1, based on the output VF_DET1 of the first adjustment comparator ADJ_CMP1. A control logic switches the state of a bridge circuit according to at least the first detection signal ZC_DET1.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2015-101298, filed May 18, 2015, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a synchronous rectifier circuit.

2. Description of the Related Art

In order to rectify an AC signal, a rectifier circuit is employed. Known examples of such a rectifier circuit include a diode bridge circuit employing diodes and a synchronous rectifier circuit employing transistors (switches).FIG. 1is a circuit diagram showing a synchronous rectifier circuit. A synchronous rectifier circuit100includes a first transistor M1through a fourth transistor M4connected in the form of a bridge circuit, diodes D1through D4, and a control circuit200. The control circuit200turns on and off, in a complementary manner, a first pair consisting of the first transistor M1and the fourth transistor M4, which are oppositely positioned, and a second pair consisting of the second transistor M2and the third transistor M3, which are oppositely positioned. The output of the synchronous rectifier circuit100is connected to a smoothing capacitor120. Input terminals AC1and AC2of the synchronous rectifier circuit100allow an unshown circuit to input or otherwise to output AC currents IAC1and IAC2to or otherwise from the synchronous rectifier circuit100, with phases that are the reverse of each other. The direction of the current IAC1or IAC2that flows to the synchronous rectifier circuit100will be referred to as the “positive direction”.

A diode bridge circuit requires no complicated control operation, and accordingly requires only a simple configuration. However, such a diode bridge circuit has a problem of power loss due to voltage drop across the diodes. The synchronous rectifier circuit100employs transistors that each have a low on resistance, i.e., that each involve only a small voltage drop, thereby providing an advantage of little power loss. Thus, in a case of ideally operating the synchronous rectifier circuit100, such an arrangement provides high-efficiency rectification operation.

FIGS. 2A through 2Care waveform diagrams each showing the operation of the synchronous rectifier circuit100. It should be noted that the vertical axis and the horizontal axis shown in the waveform diagrams and the time charts in the present specification are expanded or reduced as appropriate for ease of understanding. Also, each waveform shown in the drawing is simplified or exaggerated for emphasis for ease of understanding. In order to operate the synchronous rectifier circuit100with high efficiency, there is a need to switch each transistor with a timing at which the current I becomes zero (zero-crossing point). Such an operation will be referred to as the “zero current switching”.

FIGS. 2B and 2Ceach show the current IAC1and the voltage VAC1in the vicinity of a zero current point.FIG. 2Bshows an ideal operation with high efficiency. In this operation, each switch is switched at the same time as the zero-crossing point of the current IAC1.

The control circuit200detects such a zero-crossing timing using any particular method. Furthermore, the control circuit200switches the circuit state immediately after the zero-crossing timing. However, in actuality, the zero-crossing timing detection requires a predetermined time period, leading to a non-negligible delay in the zero-crossing timing detection. Furthermore, a control delay and propagation delay occur before the circuit state switches after the zero-crossing timing is detected.FIG. 2Cshows a case in which there is a delay τ before the circuit state switches after the zero-crossing timing tZCoccurs. During the delay τ, the first transistor M1is turned off. In this state, the current IAC1, which is input to the synchronous rectifier circuit100via the AC1terminal, flows through the diode D1arranged in parallel with the first transistor M1, which leads to degraded efficiency. In particular, in a case of inputting the current IAChaving a high frequency, such a delay τ has a serious adverse effect on efficiency, i.e., leads to marked degradation in efficiency.

SUMMARY OF THE INVENTION

The present invention has been made in order to solve such a problem. Accordingly, it is an exemplary purpose of an embodiment of the present invention to provide a synchronous rectifier circuit having improved efficiency.

An embodiment of the present invention relates to a control circuit that forms a synchronous rectifier circuit together with a bridge circuit. The bridge circuit comprises: a first transistor arranged between a first input node and a rectification node; a second transistor arranged between a second input node and the rectification node; a third transistor arranged between the first input node and a reference node; and a fourth transistor arranged between the second input node and the reference node. The control circuit comprises: a first variable voltage source that generates a first threshold voltage which is variable; a first zero current detection comparator that compares a first voltage at the first input node with the first threshold voltage, and that generates a first detection signal having a first level when the first voltage is higher than the first threshold voltage and having a second level when the first voltage is lower than the first threshold voltage; a first adjustment comparator that compares the first voltage with a first reference voltage; a first adjustment unit that adjusts the first threshold voltage generated by the first variable voltage source, based on an output of the first adjustment comparator; and a control logic that switches a state of the bridge circuit according to the first detection signal.

Such an embodiment allows the first threshold voltage to be adjusted such that it has a voltage level that corresponds to ideal zero-current switching. This provides improved efficiency.

In an embodiment, the first adjustment unit may comprise an up/down counter that selects one from among a count up operation and a count down operation, according to an output of the first adjustment comparator. Also, the first adjustment voltage may be set according to a count value of the up/down counter.

In an embodiment, the first threshold voltage may be variable in the vicinity of zero. Also, the first reference voltage may be configured as a negative voltage. Also, when the first detection signal becomes the first level, the control logic may instruct the bridge circuit to transit from a first state in which a pair of the first transistor and the fourth transistor are turned off and a pair of the second transistor and the third transistor are turned on, to a second state in which the first transistor through the fourth transistor are turned off.

In an embodiment, with a forward voltage of a diode as Vf, the first reference voltage may be set to be higher than −Vf.

Such an arrangement is capable of appropriately detecting a state in which a current flows through a diode arranged in parallel with the third transistor.

In an embodiment, the control circuit may further comprise a second zero current detection comparator that compares a second voltage at the second input node with a second threshold voltage, and that generates a second detection signal having a first level when the second voltage is higher than the second threshold voltage, and having a second level when the second voltage is lower than the second threshold voltage. Also, when the second detection signal becomes the first level, the control logic may instruct the bridge circuit to transit from a third state in which a pair of the second transistor and the third transistor are turned off and a pair of the first transistor and the fourth transistor are turned on, to a fourth state in which the first transistor through the fourth transistor are turned off.

In an embodiment, the control circuit may further comprise: a second variable voltage source that generates the second threshold voltage which is variable; a second adjustment comparator that compares the second voltage with a second reference voltage configured as a negative voltage; and a second adjustment unit that adjusts the second threshold voltage generated by the second variable voltage source, based on an output of the second adjustment comparator.

Such an embodiment allows the second threshold voltage to be adjusted such that it has a voltage level that corresponds to ideal zero-current switching. This provides further improved efficiency.

In an embodiment, when the second detection signal becomes the second level, the control logic may instruct the bridge circuit to transit from the second state to the third state. Also, when the first detection signal becomes the second level, the control logic may instruct the bridge circuit to transit from the fourth state to the first state.

Such an arrangement requires only two comparators to detect a zero-current point. This allows the circuit area to be reduced.

In an embodiment, the first zero current detection comparator and the second zero current detection comparator may each be configured as a hysteresis comparator.

Such an arrangement is capable of adjusting a threshold value for controlling the transition from the second state to the third state, and a threshold value for controlling the transition from the fourth state to the first state, according to the hysteresis width.

In an embodiment, the control circuit may further comprise: a third zero current detection comparator that compares the first voltage with a third threshold voltage, and that generates a third detection signal which indicates a comparison result; and a fourth zero current detection comparator that compares the second voltage with a fourth threshold voltage, and that generates a fourth detection signal which indicates a comparison result. Also, the control logic may instruct the bridge circuit to transit from the second state to the third state according to one from among the third detection signal and the fourth detection signal. Also, the control logic may instruct the bridge circuit to transit from the fourth state to the first state according to the other signal from among the third detection signal and the fourth detection signal.

This allows the third and fourth threshold voltages to be set independently of adjustment of the first and second threshold voltages.

In an embodiment, the first threshold voltage may be variable in the vicinity of a rectified voltage at the rectification node. Also, the first reference voltage may be configured as a positive voltage that is higher than the rectified voltage. Also, when the first detection signal becomes the second level, the control logic may instruct the bridge circuit to transit from a third state in which a pair of the second transistor and the third transistor are turned off and a pair of the first transistor and the fourth transistor are turned on, to a fourth state in which the first transistor through the fourth transistor are turned off.

Also, with a forward voltage of a diode as Vf, and with the rectified voltage as VRECT, the first reference voltage may be set to be lower than (VRECT+Vf).

Such an arrangement is capable of appropriately detecting a state in which a current flows through a diode arranged in parallel with the first transistor.

In an embodiment, the control circuit may further comprise a second zero current detection comparator that compares a second voltage at the second input node with a second threshold voltage, and that generates a second detection signal having a first level when the second voltage is higher than the second threshold voltage, and having a second level when the second voltage is lower than the second threshold voltage. Also, when the second detection signal becomes the second level, the control logic may instruct the bridge circuit to transit from a first state in which a pair of the first transistor and the fourth transistor are turned off and a pair of the second transistor and the third transistor are turned on, to a second state in which the first transistor through the fourth transistor are turned off.

In an embodiment, the control circuit may further comprise: a second variable voltage source that generates the second threshold voltage which is variable; a second adjustment comparator that compares the second voltage with a second reference voltage configured as a positive voltage; and a second adjustment unit that adjusts the second threshold voltage generated by the second variable voltage source, based on an output of the second adjustment comparator.

In an embodiment, when the first detection signal becomes the first level, the control logic may instruct the bridge circuit to transit from the second state to the third state. Also, when the second detection signal becomes the first level, the control logic may instruct the bridge circuit to transit from the fourth state to the first state.

In an embodiment, the first zero current detection comparator and the second zero current detection comparator may each be configured as a hysteresis comparator.

In an embodiment, the control circuit may further comprise: a third zero current detection comparator that compares the first voltage with a third threshold voltage, and that generates a third detection signal which indicates a comparison result; and a fourth zero current detection comparator that compares the second voltage with a fourth threshold voltage, and that generates a fourth detection signal which indicates a comparison result. Also, the control logic may instruct the bridge circuit to transit from the second state to the third state according to one from among the third detection signal and the fourth detection signal. Also, the control logic may instruct the bridge circuit to transit from the fourth state to the first state according to the other signal from among the third detection signal and the fourth detection signal.

In an embodiment, the control circuit may be integrated on a single semiconductor substrate.

Examples of such a “monolithically integrated” arrangement include: an arrangement in which all the circuit components are formed on a semiconductor substrate; and an arrangement in which principal circuit components are monolithically integrated. Also, a part of the circuit components such as resistors and capacitors may be arranged in the form of components external to such a semiconductor substrate in order to adjust the circuit constants.

Another embodiment of the present invention relates to a synchronous rectifier circuit. The synchronous rectifier circuit comprises: a bridge circuit; and any one of the aforementioned control circuits that each control the bridge circuit.

Yet another embodiment of the present invention relates to a wireless power receiving apparatus. The wireless power receiving apparatus comprises: a reception coil; a bridge circuit connected to the reception coil; and any one of the aforementioned control circuits that each control the bridge circuit.

Yet another embodiment of the present invention relates to an electronic device. The electronic device comprises the aforementioned wireless power receiving apparatus.

It is to be noted that any arbitrary combination or rearrangement of the above-described structural components and so forth is effective as and encompassed by the present embodiments. Moreover, this summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.

DETAILED DESCRIPTION OF THE INVENTION

In the present specification, the state represented by the phrase “the member A is connected to the member B” includes a state in which the member A is indirectly connected to the member B via another member that does not substantially affect the electric connection therebetween, or that does not damage the functions or effects of the connection therebetween, in addition to a state in which the member A is physically and directly connected to the member B.

Similarly, the state represented by the phrase “the member C is provided between the member A and the member B” includes a state in which the member A is indirectly connected to the member C, or the member B is indirectly connected to the member C via another member that does not substantially affect the electric connection therebetween, or that does not damage the functions or effects of the connection therebetween, in addition to a state in which the member A is directly connected to the member C, or the member B is directly connected to the member C.

FIG. 3is a circuit diagram showing a synchronous rectifier circuit100including a control circuit200according to an embodiment. The synchronous rectifier circuit100includes a bridge circuit102and the control circuit200. The bridge circuit102includes an AC1terminal (first input node), an AC2terminal (second input node), a RECT terminal (rectification node), a GND terminal (reference node), a first transistor M1through a fourth transistor M4connected in the form of a bridge circuit, and diodes D1through D4. The first transistor M1is arranged between the AC1terminal and the RECT terminal. The second transistor M2is arranged between the AC2terminal and the RECT terminal. The third transistor M3is arranged between the AC1terminal and the GND terminal. The fourth transistor M4is arranged between the AC2terminal and the GND terminal. The GND terminal is grounded. In the present embodiment, the first transistor M1through the fourth transistor M4are each configured as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Also, each transistor may be configured using an IGBT (Insulated Gate Bipolar Transistor), a bipolar transistor, a GaN (gallium nitride) FET, or the like. Also, the first transistor M1and the second transistor M2, which are each configured as a high-side transistor, may be configured using a P-channel (or PNP) transistor. Also, the diodes D1through D4may each be configured as a body diode of the parallel MOSFET. Otherwise, the diodes D1through D4may each be configured as a discrete element.

The control circuit200repeatedly switches its state between a state φ1through a state φ4as listed below.

The first transistor M1is turned off.

The second transistor M2is turned on.

The third transistor M3is turned on.

The fourth transistor M4is turned off.

The first transistor M1is turned off.

The second transistor M2is turned off.

The third transistor M3is turned off.

The fourth transistor M4is turned off.

The first transistor M1is turned on.

The second transistor M2is turned off.

The third transistor M3is turned off.

The fourth transistor M4is turned on.

The first transistor M1is turned off.

The second transistor M2is turned off.

The third transistor M3is turned off.

The fourth transistor M4is turned off.

The control circuit200is configured as a function IC (Integrated Circuit) monolithically integrated on a single semiconductor substrate. The control circuit200includes output terminals OUT1through OUT4respectively connected to the gates of the first transistor M1through the fourth transistor M4, a first detection terminal AC1_DET connected to the AC1terminal, and a second detection terminal AC2_DET connected to the AC2terminal.

The control circuit200includes a control logic202, a first zero current detection circuit204, a second zero current detection circuit206, and a driver208. The first zero current detection circuit204detects a zero-crossing point in the current IAC1, based on the voltage VAC1at the AC1_DET terminal. Furthermore, the first zero current detection circuit204generates a first detection signal (ZC_DET1) having a level that is switched every time the zero-crossing point is detected.

Similarly, the second zero current detection circuit206detects a zero-crossing point in the current IAC2, based on the voltage VAC2at the AC2_DET terminal. Furthermore, the second zero current detection circuit206generates a second detection signal (ZC_DET2) having a level that is switched every time the zero-crossing point is detected. It should be noted that the zero-crossing timing indicated by the ZC_DET1signal or otherwise the ZC_DET2signal does not necessarily match the current zero-crossing point in the strict sense. Rather, the zero-crossing timing thus detected can indicate a time point that is earlier in time than the precise current zero-crossing point.

The first zero current detection circuit204includes a first variable voltage source VS1, a first zero current detection comparator ZC_CMP1, a first adjustment comparator ADJ_CMP1, and a first adjustment unit210.

The first adjustment variable voltage VS1generates a first threshold voltage VZC1which is variable and used to detect the zero-current point. The first threshold voltage VZC1is set to a value in the vicinity of zero. Typically, the first threshold voltage VZC1is set within a voltage range (minus several mV to minus several tens of mV) that is slightly lower than 0 V. The delay in the zero current detection decreases according to a reduction in the first threshold voltage VZC1. To the contrary, the delay in the zero current detection increases according to an increase in the first threshold voltage VZC1.

The first zero current detection comparator ZC_CMP1compares the first voltage VAC1at the AC1_DET terminal with the first threshold voltage VZC1. When the first voltage VAC1is higher than the first threshold voltage VZC1, the output ZC_DET1of the first zero current detection comparator ZC_CMP1is set to a first level (high level in the present embodiment). When the first voltage VAC1is lower than the first threshold voltage VZC1, the output ZC_DET1is set to a second level (low level in the present embodiment).

The first zero current detection comparator ZC_CMP1is configured as a hysteresis comparator. When VAC1<VZC1, the threshold voltage VZC1is set to a higher value. When VAC1>VZC1, the threshold voltage VZC1is set to a lower value (which will be represented by VZC3for convenience).

Description will be made later regarding the first adjustment comparator ADJ_CMP1and the first adjustment unit210.

The second zero current detection circuit206has the same configuration as that of the first zero current detection circuit204. Specifically, the second zero current detection circuit206includes a second variable voltage source VS2, a second zero current detection comparator ZC_CMP2, a second adjustment comparator ADJ_CMP2, and a second adjustment unit212.

The second zero current detection comparator ZC_CMP2compares the second voltage VAC2at the AC2_DET terminal with the second threshold voltage VZC2. The second zero current detection comparator ZC_CMP2outputs a ZC_DET2signal having a first level (high level) when VAC2>VZC2, and having a second level (low level) when VAC2<VZC2. The second zero current detection comparator ZC_CMP2is configured as a hysteresis comparator. When VAC2<VZC2, the threshold voltage VZC2is set to a higher voltage. Conversely, when VAC2>VZC2, the threshold voltage VZC2is set to a lower voltage (which will be referred to as “VZC4” for convenience).

The control logic202performs the following control operation.

(1) When the ZC_DET1signal is switched to the first level (high level), the control logic202switches the bridge circuit102from the first state φ1to the second state φ2.

(2) When the ZC_DET2signal is switched to the second level (low level), the control logic202switches the bridge circuit102from the second state φ2to the third state φ3.

(3) When the ZC_DET2signal is switched to the first level (high level), the control logic202switches the bridge circuit102from the third state φ3to the fourth state φ4.

(4) When the ZC_DET1signal is switched to the second level (low level), the control logic202switches the bridge circuit102from the fourth state φ4to the first state φ1.

The control logic202may be configured as a state machine. The control logic202generates gate signals G1through G4to be used to switch on and off the first transistor M1through the fourth transistor M4, respectively. The driver208switches on and off the first transistor M1through the fourth transistor M4according to the gate signals G1through G4, respectively.

The above is the basic configuration of the synchronous rectifier circuit100. Next, description will be made regarding the rectification operation of the synchronous rectifier circuit100.FIG. 4is a waveform diagram showing a basic operation of the synchronous rectifier circuit100.

Before the time point t0, the state is set to the first state φ1. When the first voltage VAC1at the first detection terminal AC1_DET exceeds the first threshold voltage VZC1, the ZC_DET1signal is set to the first level (high level). In this stage, the control circuit200transmits an instruction to switch the state to the second state φ2. Subsequently, at the time point t1after a detection delay τ1elapses, the outputs OUT2and OUT3are each set to the low level, which turns off the second transistor M2and the third transistor M3.

When the second voltage VAC2at the second detection terminal AC2_DET becomes lower than the threshold voltage VZC4, the ZC_DET2signal is switched to the second level (low level). In this stage, the control circuit200transmits an instruction to switch the state to the third state φ3. Subsequently, at the time point t3after a detection delay τ2elapses, the fourth transistor M4is turned on. Subsequently, at the time point t4, the first transistor M1is turned on.

When the second voltage VAC2at the second detection terminal AC2_DET exceeds the second threshold voltage VZC2, the ZC_DET2signal is switched to the first level (high level). In this stage, the control circuit200transmits an instruction to switch the state to the fourth state φ4. Subsequently, at the time point t6after a detection delay τ3elapses, the outputs OUT1and OUT4are each set to the low level, which turns off the first transistor M1and the fourth transistor M4.

When the first voltage VAC1at the first detection terminal AC1_DET becomes lower than the threshold voltage VZC3, the ZC_DET1signal is switched to the second level (low level). In this stage, the control circuit200transmits an instruction to switch the state to the first state φ1. Subsequently, at the time point t8after a detection delay τ4elapses, the third transistor M3is turned on. Subsequently, at the time point t9, the second transistor M2is turned on.

The synchronous rectifier circuit100repeatedly performs the aforementioned operation. Next, description will be made regarding a problem involved in the synchronous rectifier circuit100.

The states φ1′ through φ4′ of the bridge circuit102each transit with a delay from the transition of the corresponding state of the control circuit200, i.e., a corresponding one of the states φ1through φ4. The first threshold voltage VZC1through the fourth threshold voltage VZC4, which are to be set for the control circuit200, are determined such that the states φ1′ through φ4′ of the bridge circuit102match the actual zero-crossing points in the currents IAC1and IAC2.

Description will be made below directing attention to the transition from the first state φ1to the second state φ2. In the first state φ1, the first voltage VAC1is represented by IAC1×RON3. Here, RON3represents the on resistance of the third transistor M3. The threshold voltage VZC1may be determined such that the actual zero-current point (IAC1=0) occurs after the passage of the delay time τ1after the first voltage VAC1crosses the threshold voltage VZC1.

With the slope of the current IAC1as α (A/s), the slope of the first voltage VAC1is represented by α×RON3(V/s). Accordingly, by determining the threshold voltage VZC1so as to satisfy the following Expression (1), such an arrangement provides ideal zero-current switching.
VZC1=α×RON3×τ1  (1)

However, the delay τ1can vary due to variation in the offset voltage of the first zero current detection comparator ZC_CMP1, variation in the response speed of each comparator, variation in the delay of the control logic202, variation in the delay of the driver208, and the like.

Furthermore, variation also occurs in the on resistance RON3of the third transistor M3. In a case in which the third transistor M3is configured as an external discrete component, there is marked variation in the on resistance RON3. Furthermore, the slope α changes due to a change in the frequency of the current IACor a change in the peak value IPEAKof the current IAC.

Accordingly, in a case in which the first threshold voltage VZC1is configured as a fixed value, the switching operation deviates from ideal zero-current switching due to such variation, measurement error, a change in the current, or the like. The same can be said of the transition from the third state φ3to the fourth state φ4. Specifically, in a case in which the second threshold voltage VZC2is configured as a fixed voltage, the switching operation deviates from ideal zero-current switching. It should be noted that the problem described above has been uniquely studied by the present inventors, and is by no means within the scope of common and general knowledge of those skilled in this art.

In order to solve this problem, the control circuit200shown inFIG. 3further includes a first adjustment unit210, a first adjustment comparator ADJ_CMP1, a second adjustment unit212, and a second adjustment comparator ADJ_CMP2.

The first adjustment comparator ADJ_CMP1compares the first voltage VAC1with a predetermined first reference voltage VTH1configured as a negative voltage. With the forward voltage of each diode as Vf, the first reference voltage VTH1is set to a value that is lower than the ground voltage, i.e., 0 V, and that is higher than −Vf. Typically, each diode has a forward voltage Vf of 0.6 to 0.7 V. For example, the first reference voltage VTH1can be set to a value on the order of −50 to −300 mV. In the present embodiment, the first reference voltage VTH1is set to −120 mV. When VAC1<VTH1, the output VF_DET1of the first adjustment comparator ADJ_CMP1is set to a first level (e.g., high level). When VAC1>VTH1, the output VF_DET1is set to a second level (e.g., low level).

The first adjustment unit210adjusts the first threshold voltage VZC1generated by the first variable voltage source VS1, according to the output VF_DET1of the first adjustment comparator ADJ_CMP1.

The same operation is performed on the second zero current detection circuit206side. The second adjustment comparator ADJ_CMP2compares the second voltage VAC2with a predetermined second reference voltage VTH2configured as a negative voltage. The second reference voltage VTH2may be set to the same voltage as the first reference voltage VTH1.

When VAC2<VTH2, the output VF_DET2of the second adjustment comparator ADJ_CMP2is set to a first level (e.g., high level). When VAC2>VTH2, the output VF_DET2is set to a second level (e.g., low level).

The second adjustment unit212adjusts the second threshold voltage VZC2generated by the second variable voltage source VS2, according to the output VF_DET2of the second adjustment comparator ADJ_CMP2.

The above is the configuration of the control circuit200. Next, description will be made regarding the optimization of the first threshold voltage VZC1and the second threshold voltage VZC2.

FIGS. 5A through 5Dare operation waveform diagrams each showing the operation of the synchronous rectifier circuit100shown inFIG. 3. Description will be made directing attention to the transition from the first state φ1to the second state φ2.FIG. 5Ashows the current IAC1.FIGS. 5B through 5Deach show the first voltage VAC1, the ZC_DET1signal, and the output VF_DET1of the first adjustment comparator ADJ_CMP1. There is a difference in the first threshold voltage VZC1among the operations shown inFIGS. 5Bthrough5D.

FIG. 5Cshows ideal zero-current switching. In the switching operation shown inFIG. 5B, the first threshold voltage VZC1is set to a voltage that is higher than that shown inFIG. 5C. Accordingly, such a switching operation leads to a problem of power loss in the hatched area.

InFIG. 5D, the first threshold voltage VZC1is set to a voltage that is lower than that shown inFIG. 5C. In this case, the state transits to the second state φ2before the current zero-crossing timing ZC, which turns off the third transistor M3. In this case, the current IAC1flows through the diode D3which is in parallel with the third transistor M3, which sets the first voltage VAC1to −Vf. In this stage, the first adjustment comparator ADJ_CMP1detects that the first voltage VAC1has become −Vf, and asserts the VF_DET1signal.

In a case in which the threshold voltage VZC1is equal to or otherwise higher than an ideal value for the zero-current switching, the current IAC1does not flow through the diode D3. In this state, the VF_DET1signal is not asserted. Conversely, in a case in which the threshold voltage VZC1is lower than the ideal value, the current IACflows through the diode D3even if there is a very small difference between them. In this state, the VF_DET1signal is asserted.

In other words, the ideal value of the first threshold voltage VZC1is is the lowest possible value of the voltage that is set immediately before the VF_DET1signal is asserted. Thus, by monitoring the VF_DET1signal while changing the first threshold voltage VZC1, such an arrangement allows the first adjustment unit210to detect the ideal value of the first threshold voltage VZC1.

For example, the first adjustment unit210reduces the first threshold voltage VZC1in a stepwise manner until the VF_DET1signal is asserted. With such an arrangement, the ideal value may be set to a value of the first threshold voltage VZC1immediately before the VF_DET1signal is asserted.

As described above, with the synchronous rectifier circuit100according to the embodiment, the threshold voltages VZC1and VZC2can be adjusted to respective voltage levels that provide ideal zero-current switching even if there is variation in the circuit constants, or variation in the frequency, peak value, or slope of the current. By providing ideal zero-current switching, such an arrangement is capable of reducing the power loss across each switching element (transistor), thereby providing improved efficiency. Furthermore, by providing reduced power loss, such an arrangement is capable of suppressing heat generation. This allows the thermal design to be performed in a simple manner for the synchronous rectifier circuit100itself or otherwise for a device employing the synchronous rectifier circuit100.

With conventional techniques, in order to suppress variation in the on resistances of the third transistor M3and the fourth transistor M4, there is a need to build the bridge circuit102into the control circuit200. Otherwise, as the third transistor M3and the fourth transistor M4, there is a need to select and employ an element that has an on resistance having little variation. In contrast, with the control circuit200according to the embodiment, by adjusting the threshold voltages VZC1and VZC2, such an arrangement is capable of absorbing such variation in the on resistances RON. Such an arrangement allows the bridge circuit102to be configured as an external discrete component. Thus, by means of the operation of the control circuit200, such an arrangement provides reduced on resistances, thereby further providing improved efficiency.

Furthermore, with conventional techniques, in order to reduce the delay τ as much as possible, there is a need to employ a high-speed comparator as the first zero current detection comparator ZC_CMP1and the second zero current detection comparator ZC_CMP2. However, such a high-speed comparator requires a large circuit area and large power consumption. In contrast, with the embodiment, by adjusting the threshold voltages VZC1and VZC2, such an arrangement is capable of absorbing the delay τ itself and variation in the delay τ even if the delay τ itself is large or even if there is variation in the delay τ. Thus, such an arrangement allows the comparators ZC_CMP1and ZC_CMP2to each be configured as a low-speed comparator. This allows the circuit design to be performed in a simple manner.

With conventional techniques, as the switching period of the synchronous rectifier circuit becomes shorter, i.e., as the switching frequency becomes higher, the effects of such multiple kinds of variation become larger. Thus, it is difficult for such a conventional technique to support high-frequency switching, which is a problem. In contrast, with the embodiment, such an arrangement is capable of supporting a switching operation with the AC signal IAChaving a high frequency.

It should be noted that the adjustment of the threshold voltages VZC1and VZC2may be performed at all times in the operation of the synchronous rectifier circuit100. This allows the threshold voltages VZC1and VZC2to be adjusted according to the change in the characteristics of the AC current IACand the change in the delay τ even if a change occurs in the characteristics of the AC current IACor in the delay τ.

Conversely, the adjustment of the threshold voltages VZC1and VZC2may be performed only in a calibration period set during or otherwise before the operation of the synchronous rectifier circuit100. That is to say, if there is only a negligible change in the characteristics of the AC current IAC or in the delay τ, once the optimized voltage is determined, the optimized voltage thus determined may be repeatedly used. Such a calibration operation may be performed in a periodical manner.

This provides reduced power consumption in the first adjustment comparator ADJ_CMP1, the second adjustment comparator ADJ_CMP2, the first adjustment unit210, and the second adjustment unit212.

The present invention encompasses various kinds of circuits that can be regarded as a block configuration or a circuit configuration shown inFIG. 3, or otherwise that can be derived from the aforementioned description. That is to say, the present invention is not restricted to a specific circuit configuration. Specific description will be made below for clarification and ease of understanding of the essence of the present invention and the circuit operation. That is to say, the following description will by no means be intended to restrict the technical scope of the present invention.

FIG. 6is a circuit diagram showing an example configuration of the first adjustment unit210. A mask circuit214masks the change in the level of the ZC_DET1signal, thereby removing the effects of noise.

The first adjustment unit210includes an up/down counter220. The count value S20of the up/down counter220is used as a control signal for controlling the first variable voltage source VS1. In this description, the threshold voltage VZC1is raised according to an increase in the count value S20.

The up/down counter220counts up during a period in which the VF_DET1signal is set to the low level, i.e., during a period in which VAC1>VTH1. Conversely, the up/down counter220counts down during a period in which the VF_DET1signal is set to the high level, i.e., during a period in which VAC1<VTH1.

Inverters222,224, and226, a flip-flop228, and a delay circuit230, are arranged in order to provide timing adjustment and to provide logic level matching. The flip-flop228is arranged such that its input terminal (D) receives a high level voltage (i.e., power supply voltage VDD), and such that its clock terminal receives the VF_DET1signal inverted by the inverter222. Furthermore, the ZC_DET1signal is input to the reset terminal (logical inversion) of the flip-flop228. The second adjustment unit212is configured in the same manner as in the first adjustment unit210.

Next, description will be made regarding the operation of the first adjustment unit210.FIG. 7is a flowchart showing the operation of the first adjustment unit210shown inFIG. 6.

First, the up/down counter220is initialized (S100). The initial value of the count value S20is determined such that the threshold voltage VZC1is higher than its ideal value. For example, the count value may be set to the maximum value of the counter. Also, the count value may be set to a value such that the threshold voltage VZC1becomes 0 V.

It should be noted that, in a case in which the initial value of the threshold voltage VZC1is set such that it is lower than its ideal value, this can become a cause of a malfunction. Conversely, in a case in which the initial value is set to a high value, such an arrangement requires an increased time period to acquire the ideal value, but such an arrangement is capable of preventing a malfunction.

The state transits from the first state φ1to the second state φ2(S102). In this stage, when VAC1>VTH1(NO in S104), judgment is made that the threshold voltage VZC1is higher than its ideal value. In this case, the up/down counter220counts down (S108), which lowers the threshold voltage VZC1. Conversely, when VAC1<VTH1(YES in S104), judgment is made that the threshold voltage VZC1is lower than its ideal value. In this case, the up/down counter220counts up (S106), which raises the threshold voltage VZC1.

Subsequently, the state sequentially transits in the order of the second state φ2, the third state φ3, the fourth state φ4, and the first state φ1(S110). Next, the flow returns to Step S102.

This operation is repeatedly performed. As a result, the first threshold voltage VZC1settles in the vicinity of its ideal value. The same processing is performed in parallel on the AC2side. As a result, the second threshold voltage VZC2settles in the vicinity of its ideal value in the same manner.

Description has been made above regarding the present invention with reference to the embodiment. The above-described embodiment has been described for exemplary purposes only, and is by no means intended to be interpreted restrictively. Rather, it can be readily conceived by those skilled in this art that various modifications may be made by making various combinations of the aforementioned components or processes, which are also encompassed in the technical scope of the present invention. Description will be made below regarding such modifications.

FIG. 8is a block diagram showing a control circuit200aaccording to a first modification. In this modification, the control circuit200afurther includes a third zero current detection comparator ZC_CMP3and a fourth zero current detection comparator ZC_CMP4.

The third zero current detection comparator ZC_CMP3compares a first voltage VAC1with a third threshold voltage VZC3, and generates a third detection signal (ZC_DET3) that indicates a comparison result. When VAC1>VZC3, the ZC_DET3signal is set to a first level (e.g., high level). Conversely, when VAC1<VZC3, the ZC_DET3signal is set to a second level (low level).

On the other hand, the fourth zero current detection comparator ZC_CMP4compares a second voltage VAC2with a fourth threshold voltage VZC4, and generates a fourth detection signal (ZC_DET4) that indicates a comparison result. When VAC2>VZC4, the ZC_DET4signal is set to a first level (e.g., high level). Conversely, when VAC2<VZC4, the ZC_DET4signal is set to a second level (e.g., low level).

When the ZC_DET4signal transits to the second level (low level), the control logic202switches the bridge circuit102from the second state φ2to the third state φ3, and when the ZC_DET3signal transits to the second level (low level), the control logic202switches the bridge circuit102from the fourth state φ4to the first state φ1.

Such a modification allows the threshold voltages VZC3and VZC4to be determined independently of adjustment of the first threshold voltage VZC1and the second threshold voltage VZC2.

Description has been made in the embodiment regarding an arrangement in which both the AC1side and the AC2side are provided with the threshold voltage adjustment units for the threshold voltage VZC1and for the threshold voltage VZC2, respectively. Also, such a threshold voltage adjustment unit may be provided to only one from among the AC1side or the AC2side. For example, such a threshold voltage adjustment unit may be provided to only the AC1side. As an example, the AC1side and the AC2side may share the first adjustment comparator ADJ_CMP1and the first adjustment unit210in a time sharing manner so as to adjust the threshold voltages.

Such a modification allows the circuit area to be reduced.

Alternatively, the second threshold voltage VZC2may be adjusted based on the result of adjustment of the first threshold voltage VZC1provided by the first adjustment unit210.

In a case in which there is high symmetry between the AC1side and the AC2side, such threshold monitoring adjustment may be performed on only one side from among the AC1side and the AC2side, and the threshold voltage to be set for the other side may be optimized based on the threshold monitoring adjustment result thus obtained, thereby providing optimization processing for both the first threshold voltage VZC1and the second threshold voltage VZC2. Such an arrangement allows the circuit area to be reduced

Description has been made in the embodiment regarding an arrangement in which the first voltage VAC1and the second voltage VAC2are compared with at least a corresponding one from among the threshold voltages VZC1through VZC4, each set to a voltage in the vicinity of 0 V, so as to detect the zero-current point. However, the present invention is not restricted to such an arrangement. Also, the threshold voltages VZC1through VZC4may each be set to a voltage in the vicinity of the rectified voltage VRECT.

Such a modification includes the control circuit200having the same configuration as that shown inFIG. 3. The first threshold voltage VZC1and the second threshold voltage VZC2may each be variable in the vicinity of the rectified voltage VRECT. The first reference voltage VTH1and the second reference voltage VTH2are each configured as a positive voltage that is higher than the rectified voltage VRECTand that is lower than (VRECT+Vf).

FIG. 9is an operation waveform diagram showing the operation of the synchronous rectifier circuit100according to a third modification.

The control logic202performs the following operations.

(i) When the ZC_DET1signal becomes the second level (e.g., high level), i.e., when VAC1<VTH1, the control logic202instructs the bridge circuit102to transit from the third state φ3to the fourth state φ4.

(ii) When the ZC_DET2signal becomes the second level (e.g., high level), i.e., when VAC2<VTH2, the control logic202instructs the bridge circuit102to transit from the first state φ1to the second state φ2.

(iii) When the ZC_DET1signal becomes the first level (e.g., low level), i.e., when VAC1>VTH3, the control logic202instructs the bridge circuit102to transit from the second state φ2to the third state φ3.

(iv) When the ZC_DET2signal becomes the first level (e.g., low level), i.e., when VAC2>VTH4, the control logic202instructs the bridge circuit102to transit from the fourth state φ4to the first state φ1.

Description will be made directing attention to the transition from the third state φ3to the fourth state φ4. The first voltage VAC1in the third state φ3is represented by the following Expression (2).
VAC1=IAC1×RON3+VRECT(2)

As the current IAC1approaches zero, VAC1decreases toward VRECTwith the passage of time. With such a modification, as the first threshold voltage VZC1becomes higher, the zero-current point detection time point the zero-current point detection time point becomes earlier. For example, the first adjustment unit210may raise the first threshold voltage VZC1from an initial value in a stepwise manner, so as to detect its ideal value. The same operations are performed on the second adjustment unit212side.

The first or second modification may be applied to the third modification.

In the modification shown inFIG. 8, the threshold voltages VZC1and VZC2may each be set to a voltage in the vicinity of 0 V, and the threshold voltages VZC3and VZC4may each be set to a voltage in the vicinity of the rectified voltage VRECT. Conversely, the threshold voltages VZC1and VZC2may each be set to a voltage in the vicinity of the rectified voltage VRECT, and the threshold voltages VZC3and VZC4may each be set to a voltage in the vicinity of 0 V.

It should be noted that the assignment of the high level and the low level of each signal is shown for exemplary purposes only in the description in the embodiment, and is no more than a matter of design choice, which can be readily conceived by those skilled in this art.

Next, description will be made regarding a preferred usage of the synchronous rectifier circuit100. The synchronous rectifier circuit100is preferably applicable to a power receiving apparatus of a wireless power supply system.FIG. 10is a block diagram showing a wireless power receiving apparatus300including the synchronous rectifier circuit100.

The wireless power receiving apparatus300is mounted on an electronic device500. The electronic device500is configured as a device that is chargeable using contactless power transmission (which is also referred to as “contactless power transmission” or “wireless power supply”), examples of which include an electric shaver, an electric toothbrush, a cordless phone, a game machine controller, an electric power tool, and the like. Alternatively, the electronic device500may be configured as a cellular phone terminal, a tablet PC, a laptop PC, a digital still camera, a digital video camera, a portable audio device, a portable game machine, or the like.

The electronic device500includes a secondary battery502and the wireless power receiving apparatus300. The wireless power receiving apparatus300receives electric power from a wireless power supply apparatus400, and charges the secondary battery502. For example, the secondary battery502is configured as a nickel hydride battery or a lithium-ion battery.

The wireless power supply apparatus400supplies an electric power signal to the wireless power receiving apparatus300. The wireless power supply apparatus400includes a transmission coil402and a driver unit404. The driver unit404is configured as a voltage source or otherwise a current source, which applies an AC driving current to the transmission coil402.

A receiving coil302included in the wireless power receiving apparatus300is located in the vicinity of the transmission coil402such that they are coupled with each other. When a driving current flows through the transmission coil402, a coil current ICOILflows through the reception coil302by means of an electromagnetic induction mechanism.

In addition to the reception coil302, the wireless power receiving apparatus300includes the synchronous rectifier circuit100, a smoothing capacitor304, and a charger circuit306.

The synchronous rectifier circuit100rectifies the coil current ICOILthat flows through the reception coil302, and supplies the coil current ICOILthus rectified to the smoothing capacitor304. The charger circuit306receives the rectified voltage VRECT, and charges the secondary battery502.

The synchronous rectifier circuit100according to the embodiment is preferably employed as a rectifier circuit included in a wireless power supply that supplies an electric power signal having a frequency that is higher than that of commercial AC electric power. It should be noted that the usage of the synchronous rectifier circuit100is not restricted to such an arrangement. Rather, the synchronous rectifier circuit100can be employed in various kinds of applications such as an AC/DC converter, etc.