System and method for using an integrated circuit pin as both a current limiting input and an open-drain output

An integrated circuit comprises at least one pin and has at least one resistor connected between a reference voltage and the at least one pin. Current measurement circuitry applies a voltage across the at least one resistor and measures a current at the at least one pin responsive to the applied voltage in a first mode of operation. The measured current enables determination of a current limit set point for the integrated circuit. In a second mode of operation, the at least one resistor comprises a pull up resistor and the at least one pin that is connected to the at least one resistor comprises an open-drain output.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:

FIG. 1is a block diagram for the manner for utilizing an output pin of an integrated circuit for a current limiting input and an open-drain output;

FIG. 2is a block diagram of a USB port power supply controller in which the circuit ofFIG. 1could be implemented;

FIG. 3is a block diagram of an integrated switch hot swap controller in which the circuit ofFIG. 1could be implemented;

FIG. 4illustrates an embodiment for monitoring the current limiting input of the circuit ofFIG. 1; and

FIG. 5is a flow diagram describing the operation of the circuit ofFIG. 1.

DETAILED DESCRIPTION

Referring now to the drawings, wherein like reference numbers are used herein to designate like elements throughout, the various views and embodiments of a system and method for using an integrated circuit pin as both a current limiting input and an open-drain output are illustrated and described, and other possible embodiments are described. The figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many possible applications and variations based on the following examples of possible embodiments.

Referring now to the drawings, and more particularly toFIG. 1, there is illustrated a block diagram of a circuit for using a pin of an integrated circuit as both a current limiting input and an open-drain output. Most low voltage current limited power switches such as USB power switches are assembled in low cost, low pin count packages. The implementation illustrated inFIG. 1combines two common power switch functions into a single pin102. These functions include a current limit setting input and a fault output. A standard 8-pin pinout integrated circuit104includes an application resistor106connected between the VDDsupply (where VDD=VIN) to the integrated circuit104and the fault output pin102. The fault output pin102is also connected to a high impedance input108of some type of downstream circuit logic110. The value of the resistor106is selected such that when the integrated circuit104applies a small voltage across the resistor106, the resulting current through the resistor is measured by the integrated circuit104and then multiplied by a predetermined value to determine the current limiting set point of the integrated circuit104using current measurement logic112. The resistor106is read just one time during system start up and once the circuit104is turned on, the switch is enabled. The current read by the integrated circuit104is stored within an associated memory register114for use as the current limiting set point.

For a small voltage, 0.6 volts is chosen such that VDD−0.6 volts is still above the voltage threshold for the downstream logic110that is connected with the integrated circuit104. This prevents a fault misread during resistor value reading. Once the current limiting set point has been established by the integrated circuit104, the resistor106may be used with the output pin102as an open-drain output to the downstream logic110. This provides a valuable feature to a standard pinout package. The ability to alter the current limiting set point by altering resistor106is of a very high value since this is a primary specification feature for parts of this type. This enables a user to program current limiting to their particular system needs. Thus, using this configuration enables a current limiting resistor to initially be used for establishing a current limit for the integrated circuit104and after start up enables the resistor to operate as an open-drain output pull-up. This provides a valuable function to be added to the industry standard 8-pin pinout that has a backward compatible upgrade path.

Referring now toFIGS. 2 and 3, there are illustrated two examples of packages in which the circuitry ofFIG. 1could be used. Most low current voltage current limiting power switches like a USB power switch are implemented in low cost, low pinout packages. The package ofFIG. 2includes a standard 8-pin pinout configuration. The GND pin provides an IC reference connection to ground. The VIN pin provides a chip bias voltage that comprises a controlled supply input. The chip bias voltage is provided from the VIN pin. At VIN less than 2.5 volts the chip is functionally disabled and the fault latches associated with theFAULT_1andFAULT_2pins are cleared and floating. Additionally, the OUT_1and OUT_2pins are held low. The ENABLE_1and ENABLE_2pins comprise the channel enable input for enabling and disabling the switch.

TheFAULT_1andFAULT_2pins comprise the channel over current fault NOT indicators. The value of the pull up resistors106described with respect toFIG. 1that are attached to each of these pins determine the current limiting level for each switch202independently. The over current fault indicator provided from each of these pins floats and is disabled until the voltage applied at VIN is greater than 2.2 volts. This output is pulled low after the over current time-out period has expired and always stays latched until the enable signal applied to the enable pin of the associated channel is deasserted. The OUT_1and OUT_2pins comprise the channel voltage outputs which are connected to the load being protected. Upon an over current condition from the OUT pin, IOUTis current limited to a minimum of 0.7 or 1.1 amps. Current limit response time is within 200 microseconds. This output will remain in current limit for a nominal 12 milliseconds before being turned off either for the latch or auto retry versions. The circuit provides sensing in the MOSFET204that allows for rapid control of over current events. Once an over current condition is detected, the circuit goes into the current regulation control mode.

The current limit is set by the value of the open-drain pull up resistor106and is limited to a 4 amp maximum. Upon initial bias, the resistor value is read and the current limit level is determined and stored. The device provides a fully independent dual channel over current fault protection circuit. Each channel incorporates N-channel or P-channel MOSFET power switches204for power control. An N-channel MOSFET is shown here. Independent enabling input and fault reporting output compatible with 2.5 volt to 5 volt logic enable external control and monitoring.

Referring now also toFIG. 3, there is illustrated an alternative package in which the circuitry ofFIG. 1may be utilized. While the internal circuitry of the packaging is different, the external resistor106is able to set the limit current on one of the OUT pins in a similar manner described previously with respect toFIG. 2. The configuration ofFIG. 3includes a single output FAULT pin to which the resistor would be connected rather than the dual channel mode described earlier with respect toFIG. 2. However, the operation of the circuitry ofFIG. 1with respect to the FAULT output pins of the circuit is the same as that discussed above.

Referring now toFIG. 4, there is illustrated one embodiment of the resistor reader circuitry/current measurement logic within the integrated circuit104described with respect toFIG. 1for determining the value of the current limiting resistor106at the fault output pin102. The output pin102is connected to the inverting input of an amplifier402. A transistor404has its gate connected to the output of amplifier402. The drain/source path of the transistor404is connected between fault pin102and node406. The non-inverting input of amplifier402is connected to node408. A resistor410is connected between VDDand node408. A transistor412has its drain/source path connected between node408and node414. The gate of transistor412is connected to the output of amplifier416at node418. The inverting input of amplifier416is connected to node414, and the non-inverting input of amplifier416is connected to receive a reference voltage signal. A resistor420is connected between node414and ground. An N-bit analog-to-digital converter (ADC)422is connected to node406. The N-bit ADC422consists of a variable current source424connected between node406and ground. A comparator426has its input connected to node406and its output connected to a successive approximation register428. The other input of comparator426may be anywhere with in the swing range of the rail to rail voltage. Node406has a fixed current pouring into the top and a fixed current drawn from the bottom and thus comprises a very high impedance node. The output of the successive approximation register428is connected to an adder circuit430connected with a calibration circuit432.

At start up, when the fault pin102is at a logical “high” level, the analog-to-digital converter422scans the value of the pull up resistor106without pulling the fault pin102below the threshold voltage of the next logic stage110. The reset/pull up resistor106is selected to be precise in the range of 10 k to 300 k ohms. The pull up supply VDDmust also comprise the chip supply. This feature is transparent to standard stock and requires no PCB changes from a resistor BOM change.

Referring now toFIG. 5, there is illustrated a flow diagram generally describing the operation of the circuitry ofFIG. 1. Initially, at step502a small voltage is applied by the integrated circuit104to the resistor106through the output pin102. Responsive to the voltage across the pull-up resistor106, the current at the pin102is measured at step504. This measured current is multiplied at step506by a predetermined value to generate the set current limit for the integrated circuit104. This current limit value is stored at step508within an associated register within the integrated circuit104. The switch is then operated within the integrated circuit using the established current limit at step510. The pin102and associated pull up resistor106may then be used as an open-drain driver to drive downstream logic at step512.

It will be appreciated by those skilled in the art having the benefit of this disclosure that this system and method for using an integrated circuit pin as both a current limiting input and an open-drain output provides multiple pin options for limited pin packages. It should be understood that the drawings and detailed description herein are to be regarded in an illustrative rather than a restrictive manner, and are not intended to be limiting to the particular forms and examples disclosed. On the contrary, included are any further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments apparent to those of ordinary skill in the art, without departing from the spirit and scope hereof, as defined by the following claims. Thus, it is intended that the following claims be interpreted to embrace all such further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments.