Latency free data encryption and decryption between processor and memory

An embodiment is directed to a hardware circuit for encrypting and/or decrypting data transmitted between a processor and a memory. The circuit is situated between the processor and memory. The circuit includes a first interface communicatively coupled to the processor via a set of buses. The circuit also includes a second interface communicatively coupled to the memory. The circuit further includes hardware logic capable of executing an encryption operation on data transmitted between the processor and memory, without adding latency to data transmission speed between the processor and the memory. The hardware logic is configured to encrypt data received at the first interface from the processor, and transmit the encrypted data to the memory via the second interface. The hardware logic is also configured to decrypt data received at the second interface from the memory, and transmit the decrypted data to the processor via the first interface.

TECHNICAL FIELD

The present invention relates to hardware circuits, and more particularly to hardware circuits that encrypt and decrypt data transmitted between a processor and memory.

BACKGROUND ART

A computer system typically contains a central processing unit (CPU) and associated memory. The execution of an application by a computer system includes the CPU transmitting operations (e.g., read and write operations) to the associated memory. During these operations, an attacker may attempt to hack the application by accessing and modifying data associated with these operations. Typically, securing these operations against attackers involves intervention by the CPU, such as the CPU executing software that generates and/or applies a cipher key to encrypt/decrypt the data. In some configurations, the encryption/decryption software may be assisted by inline encryption hardware coupled to the memory.

The encryption/decryption software executed by the CPU must share the limited processing resources of the CPU with other processes, which may cause slow CPU throughput and added latency to these operations. As such, the operations cannot be performed at the speed of recent types of memory, such as Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4-SDRAM). Further, the security of the encryption/decryption software is affected by the other CPU processes, such that an exploitation of one of the other CPU processes may allow an attacker to compromise the encryption/decryption software.

SUMMARY OF THE EMBODIMENTS

A first embodiment of the present invention is directed to a computer system for encrypting and/or decrypting data. The computer system includes a processor and a memory configured to store data associated with the processor. The memory is associated with a data transmission speed. The computer system also includes an encryption circuit situated between the processor and the memory. The encryption circuit is operatively coupled to the processor via a set of buses. The encryption circuit is configured to execute an encryption and/or decryption operation on data transmitted between the processor and the memory, without adding latency to data transmission speed of the memory.

In some embodiments, the encryption circuit is further configured to: analyze traffic on one of the set of buses to detect a write operation to the memory and execute the encryption operation to encrypt data transmitted to the memory in association with the write operation. In some embodiments, the encryption circuit is further configured to: analyze traffic on one of the set of buses to detect a read operation of the memory and execute the encryption operation to decrypt data transmitted from the memory in response to the read operation. In some embodiments, the encryption circuit is an application-specific integrated circuit (ASIC). In some embodiments, the encryption circuit includes an XOR circuit configured to execute the encryption operation on the data within a given clock time that enables the encryption circuit to transmit the data without adding latency to the data transmission speed of the memory. In some embodiments, the memory is synchronous dynamic random access memory (SDRAM). In some embodiments, the memory is a double data rate 4 (DDR4) SDRAM with a high bandwidth DDR4 interface, and the encryption circuit is configured to execute the encryption operation on the data within a given clock time, such that the encryption circuit transmits the data at data transmission speed of the DDR4 interface.

In some embodiments, the data are in plaintext when transmitted from the processor. In these embodiments, the encryption circuit is configured to generate and store a cipher key at the encryption circuit and encrypt, at the encryption circuit, the plaintext data as a function of the cipher key. In some embodiments, the data are in cipher text when transmitted from the memory, and the encryption circuit is configured to decrypt, at the encryption circuit, the cipher text data as a function of the cipher key. In some embodiments, the encryption operation is executed without any central processing unit (CPU) intervention.

A second embodiment of the present invention is directed to a hardware circuit for encrypting and/or decrypting data transmitted between a processor and a memory. The memory is associated with a data transmission speed. The hardware circuit includes a first interface communicatively coupled to the processor via a set of buses. The hardware circuit also includes a second interface communicatively coupled to the memory. The hardware circuit further includes hardware logic capable of executing an encryption operation on data transmitted between the processor and memory, without adding latency to data transmission speed of the memory. The hardware logic is configured to encrypt data received at the first interface from the processor, and transmit the encrypted data to the memory via the second interface. The hardware logic is also configured to decrypt data received at the second interface from the memory, and transmit the decrypted data to the processor via the first interface.

In some embodiments, the hardware logic is further configured to: analyze traffic on one of the set buses to detect a write operation to the memory and encrypt data transmitted from the processor with the write operation. In some embodiments, the hardware logic is further configured to: analyze traffic on one of the set of buses to detect a read operation of the memory, and decrypt data transmitted from the memory in response to the read operation. In some embodiments, the hardware circuit is an ASIC. In some embodiments, the hardware logic includes an XOR circuit configured to execute the encryption operation on the data within a given clock time that enables the encryption circuit to transmit the data without adding latency to the data transmission speed of the memory. In some embodiments, the memory is SDRAM. In some embodiments, the memory is a double data rate 4 (DDR4) SDRAM with a high bandwidth DDR4 interface, the hardware logic is configured to execute the encryption operation on the data within a given clock time, such that the encryption circuit transmits the data at data transmission speed of the DDR4 interface.

In some embodiments, the data are in plaintext when received at the first interface, and the hardware logic is configured to: generate and store a cipher key at the hardware circuit, and encrypt, at the hardware circuit, the plaintext data as a function of the cipher key. In some embodiments, the data are in ciphertext when received at the second interface, and the hardware logic is configured to decrypt, at the hardware circuit, the ciphertext data as a function of the cipher key. In some embodiments, the encryption operation is executed without any central processing unit (CPU) intervention.

A third embodiment of the present invention is directed to a computer-implemented method of encrypting and/or decrypting data. The method includes receiving data at an encryption circuit situated between a processor and memory. The memory is associated with a data transmission speed. The encryption circuit operatively coupled to the processor via a set of buses. The method further includes executing an encryption operation on the data without adding latency to data transmission speed of the memory. The executing of the encryption operation includes, if the data is received from the processor, encrypting and transmitting the data to the memory, and if the data is received from the memory, decrypting and transmitting the data to the processor.

In some embodiments, the method further includes analyzing traffic on one of the set of buses to detect a write operation to the memory, and encrypting data transmitted from the processor with the write operation. In some embodiments, the method further includes analyzing traffic on one of the set of buses to detect a read operation of the memory, and decrypting data transmitted from the memory in response to the read operation. In some embodiments, the method further includes executing the encryption operation on the data within a given clock time that enables the encryption circuit to transmit the data without adding latency to the data transmission speed of the memory. In some embodiments, the memory is a double data rate 4 (DDR4) SDRAM with a high bandwidth DDR4 interface, and the encryption circuit is configured to execute the encryption operation on the data within a given clock time, such that the encryption circuit transmits the data at data transmission speed of the DDR4 interface. In some embodiments, the encryption operation is executed without any central processing unit (CPU) intervention.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

A “set” includes at least one member.

FIG.1illustrates a common interface between a processor and memory in a computer system. The processor110may be a CPU memory controller. As shown inFIG.1, a processor110is commonly coupled to memory140via buses, including a command and address (CMD/ADD) bus120and a DQ/DQS bus130. The DQ/DQS bus130includes data signal (DQ) lines and corresponding data strobe clock signal (DQS) lines. In some embodiments, the memory140is a dual in-line memory module (DIMM) Double Data Rate (DDR) Synchronous Dynamic Random-Access Memory (SDRAM). In these embodiments, the memory140may be DDR1 SDRAM, DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, or such. Each of these memories is associated with a pre-defined transmission speed. For example, see timing and transmission speeds for the DDR4 SDRAM in the Micron Automotive DDR4 SDRAM MT40A512M8 and MT40A256M16 Specifications, Micron Technology, Inc., CCMTD-1725822587-10418, 4gb_auto_ddr4_sdram_z90b_z10B.pdf-Rev. I 05/19 EN (2016), incorporated herein, in its entirety, by reference. In an example embodiment, the processor110is an Intel Xeon processor.

The processor110uses these buses120,130to perform an operation on the memory140, such as reading from the memory140, writing to the memory140, etc. In particular, the processor110uses the CMD/ADD bus120to transmit to the memory: (i) a command signal (e.g., read command, write command, etc.) corresponding to the operation and (ii) the physical address in the memory140to access with respect to the operation.

In an example protocol between the processor110and memory140(such as the DDR 4 protocol), the processor110uses the CMD/ADD bus120to transmit various types of command signals to the memory140. The command signals may include commands to calibrate the memory140, such as Mode Register Set (MRS) and ZQ Calibration. The command signals may also include a set of commands to read or write to the memory140. To perform a read or write, the processor110may first access a specific memory bank in which to read or write. To do so, the processor first sends a Bank/Row Activation (ACT) command to active a row in that bank of the memory140. The processor110may next send the Read (RD) or Write (WR) command to perform the actual read from or write to that memory bank. The processor110may then send a Pre-charge (PRE), Pre-charge All (PREA), Write Auto Pre-charge (WRA), or Read to Pre-charge (RDA) command to close the currently activated memory bank before activating a different row in the bank.

The processor110and the memory140use the DQ/DQS bus130to send a data signal associated with the command and a corresponding data strobe signal. For example, when the processor110writes data to the memory140, the processor110transmits, via the CMD/ADD bus120, the write command signal and a write address in the memory140. The processor110further transmits, via the DQ/DQS bus130, a signal of the data to be written to the address and a corresponding data strobe clock signal. After receiving the write command signal and data signal, the memory140stores the data at the write address. As another example, when the processor110reads data residing in the memory140, the processor110transmits, via the CMD/ADD bus120, the read signal and the address of the data to be read. After receiving the read command signal, the memory140reads the data from the specified address. The memory140then transmits, via the DQ/DQS, a signal of the read data and a corresponding data strobe clock signal to the processor110.

FIG.2illustrates a computer system for encrypting/decrypting data transmitted between a processor and memory in accordance with an embodiment of the present invention. The embodiment ofFIG.2includes a modification to the common interface between a processor and memory shown inFIG.1. The embodiment ofFIG.2may be used to perform encryption/decryption operations on data transmitted between the processor210and memory240, without intervention by the processor210. In particular, the computer system ofFIG.2is configured with an encryption/decryption circuit300that is positioned between the processor210and the memory240. The encryption/decryption circuit300includes an interface252that receives the command signals and associated memory addresses transmitted on the CMD/ADD bus220by the processor210. The encryption/decryption circuit300further includes an interface254that: (i) receives the data and data strobe signals transmitted on the DQ/DQS bus230from the processor210, and (ii) transmits the circuit modified (decrypted) data and data strobe signals on the DQ/DQS bus230to the processor210. The encryption/decryption circuit300also includes interface256that: (i) receives the data and data strobe signals transmitted on the DQ/DQS bus230from the memory240, and (ii) transmits the circuit modified (encrypted) data and data strobe signals on the DQ/DQS bus230to the memory240.

In the embodiment ofFIG.2, when powered up, the encryption/decryption circuit300generates and stores a cipher key for encrypting/decrypting data signals transmitted between the processor210and memory240. After powering up, the encryption/decryption circuit300uses interface252to snoop (i.e., receive and analyze) the transmissions on the CMD/ADD bus220to determine the interface and operations between the processor210and memory240, such as the command sequence, timing, use of memory registers, etc. For example, the encryption/decryption circuit300may snoop the mode register set (MRS) commands transmitted on the CMD/ADD bus220to determine the setup by the processor210of registers in the memory240, and may snoop the bank/row activation (ACT) commands to determine a bank/row in memory240is being activated for reading or writing. The circuit can used this snooped information to calibrate and control the circuit with respect to performing encryption/decryption operations.

By snooping the CMD/ADD bus220using interface252, the encryption/decryption circuit300can detect a write command transmitted by the processor210to the memory240. Based on the snooped information, the encryption/decryption circuit300can encrypt the data signal associated with the write command as this data signal is transmitted on the DQ/DQS bus230. For example, the encryption/decryption circuit300encrypts the data signal on the DQ/DQS bus230in a manner that does not violate the protocol of the memory240(e.g., DDR 4 protocol). Based on the snooped information, the encryption/decryption circuit300receives the associated data signal from interface254on the DQ/DQS bus230and can encrypt the data signal, using the stored cipher key, in a number of clock cycles (e.g., ½ a clock cycle) that avoids adding latency to the transmission speed of the data signal, such that the transmission meets the timing requirements of the memory protocol. In some embodiments, avoiding adding latency to the transmission speed is achieved in the system when neither (i) clock speed is reduced, nor (ii) additional clocks are added. Using interface256, the encryption/decryption circuit300accordingly transmits the encrypted data signal on the DQ/DQS bus230to the memory240.

Similarly, by snooping of the CMD/ADD bus220using interface252, the encryption/decryption circuit300can detect a read command transmitted by the processor210to the memory240. Based on the snooped information, the encryption/decryption circuit300decrypts the associated data signal read from the memory240as the data is transmitted on the DQ/DQS bus230. For example, the encryption/decryption circuit300decrypts the data signal on the DQ/DQS bus230in a manner that does not violate the protocol of the memory240(e.g., DDR 5 protocol). Based on the learned behavior, the encryption/decryption circuit300receives the associated data signal from interface256on the DQ/DQS bus230, and can decrypt the data signal with the stored cipher key in a number of clock cycles (e.g., ½ a clock cycle) that avoids adding latency to the transmission speed of the data, such that the transmission meets the timing requirements of the memory protocol. Using interface254, the encryption/decryption circuit300accordingly transmits the decrypted data signal on the DQ/DQS bus230to the processor210.

FIG.3illustrates an example embodiment of the encryption/decryption circuit inFIG.2. In some embodiments, the encryption/decryption circuit300is an application-specific integrated circuit (ASIC).FIG.3describes an embodiment of the encryption/decryption circuit using the block cypher of Advanced Encryption Standard (AES). However, in other embodiments, any other type of block cypher may instead be used in the encryption/decryption circuit.

The encryption/decryption circuit300may include eight primary modules as shown in the block diagram ofFIG.3. These modules are the state machine traffic controller (CTRL) module310, the XOR logic module380, the Advanced Encryption Standard (AES)-Counter (AES-CTR) module340, the Hash Function module370, the global counter memory (GCTR) module350, the global tag memory (GTAG) module360, the rows counter memory (RCTR) module330, and the true random number generator (TRNG) module320. Note, the AES-CTRL module340may be replaced by a counter mode associated with another type of block cypher.

The CTRL module310is the core of encryption/decryption circuit300, and acts as a traffic controller. The CTRL module310snoops, on the CMD/ADD bus315, the various memory commands transmitted between the processor210and the memory240. The commands and associated addresses are specified in the CMD/ADD bus315using the following signals: bank group (BG[1:0])305, bank address (BA[1:0])306, address (ADD[16:0])308, Command/Address Reference Voltage (CTRL_VREF)309, Active low chip select (CS_N)311, Active low Activation select (ACT_N)312, and On Die Termination (ODT)313. Based on the snooped command, the CTRL module310executes operations to calibrate and control the circuit300to encrypt/decrypt the data signals on the DQ/DQS bus385(on-the-fly), without causing latency that would violate the timing of the protocol of the memory240(e.g., DDR 4 protocol). For example, the CTRL module310may calibrate reference voltage, traffic direction, output drivers (e.g., driver strength), ODT, and such in accordance with the protocol of the memory240.

The CTRL module310is operatively coupled to the GCTR module350and RCTR module330. The GCTR module350stores global counters for the memory240. Each counter is associated with a corresponding cache line in the memory240. When the CTRL module310detects certain pre-defined command (such as PRE, PREA, WRA, and RDA) with respect to a given cache line, the CTRL module310asserts C_WENA352and C_ADD[20:0]351to increment the corresponding counter at the GCTR module350. C_ADD[20:0]351is comprised of bank group305, bank address306, and a row address from ADD308. If a counter reaches its maximum value, the CTRL module310asserts the key rolling interrupt (INT_1)316. Since the GCTR module350is slow in accessing the counters (e.g., due to size), the CTRL module310does not use these counters directly from the GCTR module350. Rather, the CTRL module310fetches a subset of these counters (e.g., 16 rows) into the RCTR module330which provides fast access memory.

The CTRL module310fetches such subset as follows. Upon detecting a certain pre-defined command (such as ACT), the CTRL module310asserts C_WENA352and C_ADD[20:0]351to the GCTR module350to read a pre-defined number of rows of corresponding counters. Ten clocks after asserting C_WENA352, the rows are available, and the CTRL module310asserts B_WENA354and B_ADD[4:0]353to write these rows at the RCTR module330. The rows are written to the RCTR module330on B_WDT[2047:0]355. In some embodiments, the pre-defined number of rows is the number of rows that the processor210is configured to activate and access from the memory240in a given operation. The GCTR module350is configured to allow data to be fetched and an updated counter to be written at the same time.

Upon detecting a certain pre-defined command (such as Write or Read), the CTRL module310asserts A_WENA332and A_ADD[10:0]331to the RCTR module330to read the counter corresponding to the command. The counter is read from the RCTR module330on A_RDT[31:0]334. The CTRL module330then pads the counter with the command address to create a nonce (e.g., 128-bit nonce). The CTRL module310passes the nonce to a cypher module, such as the AES-CTR module340, via ADD_PAD[127:32]342, along with the counter (CTR[1:0])339and an identifier of the cache line block (BLK_NUM[1:0])341. Note that any block cypher can be converted to a streaming cypher by using that block cypher in a counter mode. AES-CTR module330is the counter mode version of AES. In other embodiments, AES-CTR may be replaced by the counter mode of another block cypher. The nonce, counter, and cache line block are formatted together as shown in357.

The CTRL module310is operatively coupled to the TRNG module320. When the circuit300is powered up, the CTRL module310asserts an “On” signal343to the TRNG module320that causes the TRNG module320to randomly generate a key. In some embodiments, the key is 128 bits. In some embodiments, the generated key is stored in non-volatile memory (e.g., disk storage) and retrieved from that memory by the CTRL module310or TRNG module320. The CTRL module310is further operatively coupled to the AES-CTR module340. Upon a write or read command, the CTRL module310has the AES-CTR module340generate a cipher stream359that is input to the XOR logic module380to encrypt/decrypt data on the DQ/DQS bus385. In some embodiments, the circuit300includes the XOR logic module described later in connection withFIGS.6-7. AES-CTR module340generates the cipher stream359from the key generated by the TRNG module320and the nonce and counter passed to the AES-CTR module340from the CTRL module310. The generated key from the TRNG module320is provided to the AES-CTR module340via KEY[127:0]358. The cipher stream is generated from both the nonce, counter, and key because the use of the key alone would be easier for a malicious actor to hack. The key can change once or more per power-up. For example, if a counter rolls over, the CTR module340attempts to avoid repeating a key-counter pair. This can be achieved by (a) power cycling and new key generation on every power up, or (b) changing the key and bookkeeping which key was used.

The CTRL module310is also operatively coupled to the XOR logic module380, which receives inputs from the DQ/DQS bus385. The inputs from the processor201include DQ data (plaintext)322, DQS data strobe323, XOR comparator control (XOR_BIAS_OVR)319, XOR output impedance driver control (XOR_RON_SSF)321, and XOR current (XOR_RBIAS)324from the processor210. The inputs from the memory240also include DQ data (cipher text)326and DQS data strobe327. The XOR logic module380also receives as input the signals: on die termination (ODT) calibration (ZQ_CAL)328, enable reference voltage (Vref) calibration (VREF EN)367, Vref range (VREF_RNG)368, Vref levels (VREF_VAL[5:0])369, ZQCS_EN371, ZQCL_EN372, processor side output driver impedance value (CPU_RON)373, processor side ODT value (CPU_RTT[2:0])374, memory side output driver impedance value (DDR_RON)375, memory side ODT value (DDR_RTT[2:0])376, data direction (DQ_DIR)377, data strobe direction (DQS_DIR)378, high signal (HI_Z)379, bypass signal (ByPass)381.

On a write command from the processor210to the memory240, the XOR logic module380XORs the DQ data (plaintext)322with the cipher stream359generated by the AES-CTR module340to create encrypted data (cipher text) that is transmitted to the memory240. The Hash Function module370receives361either the cipher text or plain text from the XOR logic module380and generate a new authentication tag (e.g., 32-bit authentication tag) for the cache line corresponding to the write command. The GTAG module360stores the authenticated tags for the memory240. Each authentication tag is associated with a corresponding cache line in the memory240. The CTRL module310asserts the TAG_RDY signal346and the generated authentication tag is placed in the TAG[31:0] signal345(the last data of the tag set in LST_DT signal344) from the Hash Function module370to be written or updated in the GTAG module360. The CTRL module310asserts D_WENA336and D_ADD[26:0]335to write these rows at the GTAG module360. The rows are written to the GTAG module360on D_WDT[31:0]337.

On a read command from the processor210to the memory240, the XOR logic module380XORs the encrypted DQ data326(cipher text) received from the memory240with the cipher stream359to restore the cipher text to plain text. The Hash Function module370receives361either the cipher text or plain text from the XOR logic module380and generates the authentication tag for the cache line corresponding to the read command. The CTRL module310asserts the TAG_RDY346signal and the authentication tag is placed in the TAG[31:0]345signal to the CTRL module310. The CTRL module310also asserts D_WENA336and D_ADD[26:0]335to read the authentication tag stored at the GTAG module360for the cache line of the read command. The CTRL module310performs a compare of the authentication tag from the Hash Function module370and the stored authentication tag (in GTAG360). If the tags match, the XOR logic module380decrypts the DQ data326, otherwise, the CTRL module310captures the error address and asserts a tag mismatch interrupt (INT_0)314.

The inputs to the XOR logic module380are synchronized, such that the cipher stream359arrives at the XOR logic module380at same time as the DQ data322,326of the DQ/DQS bus385. Such synchronization allows the XOR logic module380to encrypt/decrypt and output the data in a clock time period (e.g., ½ clock cycles) that does not violate timing of the memory240(e.g., DDR4 timing). The timing of the cipher stream359from AES-CTR module340is relative to the internal clock of the encryption/decryption circuit300, but the timing of the DQ (plaintext)322is relative to the DQS (data strobe)321driven from the processor210and the timing of the DQ (cipher text)326is relative to the DQS (data strobe)327driven by the memory240. After calibration, the DQS321,327has a fixed timing relative to external clock of the memory240so the DQ (plaintext)322and DQ (cipher text)326should each have a fixed timing relative to this external clock. Because DQ (plaintext)322and DQ (cipher text)326are driven different drivers, their timing relative to this external clock is different. Therefore, two separate delay values, CPU Delay364and DDR Delay365, are applied to synchronize the cipher stream359to the DQ (plaintext)322or DQ (cipher text)326. The delays may be calibrated based on calibration commands snooped by the CTRL module310on the CMD/ADD bus315. To perform this synchronization, the CPU Delay364is input a tap delay number (TAP_SEL_CPU349) and DDR Delay365is input a tap delay number (TALP_SEL_DDR348).

Further, the use of the faster access memory of RCTR module330to retrieve the counter for generation of the cipher stream359facilitates the synchronization of the cipher stream359to the DQ (plaintext)322or DQ (cipher text)326at a speed that affords the XOR logic module380sufficient clock time (e.g., ½ clock cycle) to encrypt/decrypt and output the DQ data322,326without violating the memory protocol.

A delay value, HASH Delay366, is also applied to synchronize receiving the DQ (plaintext)322and DQ (cipher text)326from the XOR logic module380for generating authentication tags. To perform this synchronization, the HASH Delay366is input a tap delay number (TAP_SEL_HASH347). The embodiment of the encryption/decryption circuit inFIG.3also includes the following signals active low reset (RST N)301, differential clock (CLK_P/N)302, input debug signals (DBG_IN[7:0])317, and output debug signals (DBG_OUT[7:0])318.

FIGS.4A and4Billustrate state machines that may be used by an encryption/decryption circuit to determine current operations between a processor and memory in accordance with an embodiment of the present invention.

FIG.4Ashows an example state machine used by the CTRL module310ofFIG.3that may be used to calibrate and control the circuit to perform encrypt/decrypt operations based on commands transmitted between a processor and memory.

The state machine ofFIG.4Aprocesses determines the state of the encryption/decryption circuit based on these command. The state machine starts in the idle state405and detects a command signal410. If the command signal is a Bank/Row Activation (ACT) signal415, the state machine enters the ACT state420. In this state, the CTRL module310reads (prefetch) a certain number of rows of counters (e.g., 1 row) from the GCTR module350and write them into the RCTR module330. In some embodiments, a row has 128 32-bit counters, so a total of 128*32=4096 bits need to be transferred from the GCTR module350to the RCTR module330per row. Bus width (of B_WDT) between the GCTR module350and the RCTR module330is 2048, so two reads occur to pre-fetch each row. The processing of the ACT command is provided in more detail in connection withFIG.4B.

If the command signal is a Mode Register Set (MRS) signal425, the state machine enters the MRS state430. After power on, the processor210uses the different MRS signals to calibrate and initialize the memory240before starting any data transfer. In this state, the CTRL module310calibrates the circuit based on the different MRS signals. For example, for MRS0, the CTRL module310may determine the delay (read latency) in clock cycles from the processor's assertion of read command to the first data returned by the memory240and calibrate the XOR logic module380based on this delay. For another example, for MRS1, the CTRL module310may determine and calibrate write leveling, a nominal on die termination (ODT) value, output driver impedance value, and additive latency. For a further example, for MRS2, the CTRL module310may determine and calibrate the delay (write latency) in clock cycles from the processor's assertion of read command to the processor's first data out to memory240.

If the MRS signal indicates that write leveling435is enabled, the state machine enters the Write Leveling (WR) state440. The processor210enables write leveling in the memory240to compensate DQS to the clock skew. When enabled, the processor210drives the DQS data strobes signals and receives the DQ data signals. The CTRL module310asserts the DQ_DIR377and DQS_DIR378to calibrate the XOR logic module380accordingly.

If the command signal is a Write (WR) signal or Read (RD) signal445, the state machine enters the XFER state450. For a write transfer, the CTRL module310controls that the cipher stream so that it is available at the same time as the plaintext DQ Data322, and the XOR logic module is configured to XOR the cipher stream with the plaintext to produce and output the cipher text at a speed that does not cause latency that would violate the memory protocol timing requirements. In embodiments, the cipher stream and plaintext DQ Data322should be provided to the XOR logic module, such that the clock time to encrypt and output the DQ Data322is less than or equal to the set CWL value of the processor210. During the ACT state, prior to the XFER state450, the counter rows were already copied from the GCTR module350to the faster access RCTR module. The CTRL module control when to read the counter from the RCTR module to generate the cipher stream so that the cipher stream is available at the same time as the DQ Data322. The CTRL module310also control when to generate the authentication tag, such that the XOR logic module can encrypt the plaintext and output the cipher text at a speed that does not cause such latency.

For a read transfer, the CTRL module310similarly controls that the cipher stream so that it is available at the same time as the cipher text DQ Data326, and the XOR logic module is configured to XOR the cipher stream with the cipher text to produce and output the plain text at a speed that does not cause latency that would violate the memory protocol timing requirements. In embodiments, the cipher stream and cipher text DQ Data326should be provided to the XOR logic module, such that the clock time to decrypt and output the DQ Data322is less than or equal to the set CWL value of the processor210. During the ACT state, prior to the XFER state450, the counter rows were already copied from the GCTR module350to the faster access RCTR module330. The CTRL module310controls when to read the counter from the RCTR module330to generate the cipher stream so that the cipher stream is available at the same time as the DQ Data326. The CTRL module310also controls when to generate the authentication tag, read the stored authentication tag, and compare the two tags, such that the XOR logic module can decrypt the cipher text and output the plaintext at such a speed that does not cause such latency.

From the XFER state, an Auto Precharge command455is automatically asserted and the state machine enters the Precharge state465. This state may also be entered by detecting a Pre-charge or Pre-charge460all command. These commands are used by the processor to deactivate the open row of cache lines in a particular bank or the open row in all banks. In this state, the CTRL module310evicts all counters in the RCTRL module back to the GCTR module and writes an incremented counter to the GCTR module350for the cache line corresponding to the command.

If the command signal is ZQCS or ZQXL signal470, the state machine enters the ZQ Cal state475. The processor210initiate these command signals to enable the memory240to calibrate its internal ODT (CPU_RTT and DDR_RTT) and Output driver (CPU_RONand DDR_RON) logic using an external precision resistors associated with the processor210and memory240. When in this state, the CTRL module310calibrates the XOR logic module accordingly by asserting the ZQCS_EN or ZQCL_EN signal.

FIG.4Bshows an example state machine that may be used by the CTRL module310ofFIG.3in response to an ACT command420. The state machine starts in the idle state421and detects the ACT command signal420. The state machine then enters the GCTR read state422and the CTRL module310reads (prefetches) a row worth of counters from the GCTR module350. In this embodiment, the CTRL module310checks423if the row is available on the write bus10clock cycles later. If not, the CTRL module310repeats the read (prefetch) from the GCTR module350. The state machine then enters the RCTR write state424and the CTRL module310writes the pre-fetched row to the RCTR module330that has faster access. In this embodiment, the CTRL module310checks425the written word count. If this word count is not equal to two, the CTRL module310repeats the write to the RCTR module. By writing the row to the RCTR module330, the row can be accessed faster during a read/write command to generate a cipher stream to encrypt/decrypt the associated data (thereby allowing the circuit to perform the encryption/decryption without adding latency to the transmission, so as not to violate the memory protocol).

FIG.5illustrates an example method for encrypting/decrypting data in accordance with an embodiment of the present invention. The example method is executed by an encryption/decryption circuit, such as described in connection withFIGS.2-3, situated between the processor and the memory and operatively coupled the processor and memory via a set of buses. At step505, the circuit is powered up, and at step510, the method generates and stores a cipher key at the circuit. The cipher key may be generated using a random number technique. At step515, the method analyzes traffic between the processor and memory. For example, one of the set of buses may be a command and address bus, and the method analyzes the traffic to detect operations (or commands) between the processor and memory. At step520, the method detects a calibration operation, such as the mode register set (MRS) operation or ZQCS/ZQXL operation. At step525, based on this detected operation, the method calibrates the circuit in accordance with the information associated with this operation. In some embodiments, the calibration includes adding and calibrating delays components in the circuit, calibrating precise logic flow of data between the circuit components, and such. For example, if the information indicates that write leveling is enabled, which compensates the data strobe to the clock skew, the method may asserts the DQ_DIR377and DQS_DIR378to calibrate the encryption/decryption XOR logic of the circuit accordingly.

At step530, the method detects a memory write operation. In some embodiments, the memory write operation is associated with a set of commands, including an ACT command, a Write command, and a Pre-charge command. Based on the ACT command, the method may move counters corresponding to the cache lines being read/written from global memory (containing all cache lines of the memory) to faster access memory. Based on the Read/Write command, the method may create a cipher stream based on the cipher key generated at power up and the cache lines retrieved from the faster access memory. Based on the Pre-charge command, the method may evict the counters back to the slower global memory.

At step535, the method encrypts the associated data using the cipher key. In some embodiments, the method encrypts the associated data using the cipher key combined with a counter for the cache line in memory to which the data is being written. In some embodiments, one of the set of buses may be a data bus between the processor and memory, and the method encrypts the data on the data bus associated with the memory write operation. In the embodiments in which the write operation is associated with a set of commands, the method performs the encryption in response to the Write command, after preparing for the encryption in response to the ACT command. In embodiments, the method performs the encryption without adding latency to data transmission speed between the processor and memory. For example, the method may utilize the faster access memory to generate the cipher stream, calibrated delays components in the circuit, and calibrated precise logic flow of data between the circuit components, such that the encryption can be performed without adding such latency. At step540, the method continues transmission (e.g., on the DQ/DQS bus) of the encrypted data to the memory.

At step545, the method detects a memory read operation. In some embodiments, the memory read operation is associated with a set of commands, including the ACT command, the Read command, and the Pre-charge command. At step550, the method decrypts the associated data using the cipher key. In some embodiments, the method decrypts the associated data using the cipher key combined with a counter for the cache line in memory to which the data is being read. In some embodiments, one of the set of buses may be a data bus between the processor and memory, and the method decrypts the data, on the data bus, associated with the memory read operation. In the embodiments in which the read operation is associated with a set of commands, the method performs the decryption in response to the Read command, after preparing for the decryption in response to the ACT command. In embodiments, the method performs the decryption without adding latency to data transmission speed between the processor and memory. For example, the method may utilize the faster access memory to generate the cipher stream, calibrated delays components in the circuit, and calibrated precise logic flow of data between the circuit components, such that the decryption can be performed without adding such latency. At step555, the method continues transmission (e.g., on the DQ/DQS bus) of the decrypted data to the processor.

FIG.6illustrates a computer system for performing exclusive-or (XOR) operations on data transmitted between a processor and memory in accordance with an embodiment of the present invention.

The embodiment ofFIG.6includes a modification to the common interface between a processor and memory shown inFIG.1. The embodiment ofFIG.6may be used to perform operations (e.g., encryption, decryption, etc.) on data as it passes between the processor210and memory240, without intervention by the processor210. In particular, the computer system ofFIG.6is configured with an XOR circuit650and an AES controller (AES) circuit660that are positioned between the processor210and the memory240. The AES circuit660includes an interface652that receives the command signals and associated memory addresses transmitted on the CMD/ADD bus620by the processor610, and an interface654that forwards those command signals and associated memory addresses on the CMD/ADD bus620to the memory640.

The XOR circuit650includes an interface652that: (i) receives the data and data strobe signals transmitted on the DQ/DQS bus630from the processor610, and (ii) transmits the circuit modified (e.g., decrypted) data and data strobe signals on the DQ/DQS bus630to the processor610. The interface652emulates the memory protocol by being configured with logic that mimics the logic of the memory640, such that processor610can interface with the XOR circuit650using the memory protocol. For example, the interface652may be configured to mimic the electrical characteristics of the memory640. The XOR circuit650also includes interface654that: (i) receives the data and data strobe signals transmitted on the DQ/DQS bus630from the memory640, and (ii) transmits the circuit modified (e.g., encrypted) data and data strobe signals on the DQ/DQS bus630to the memory640. The interface654emulates the processor protocol by being configured with logic that mimics the logic of the processor610, such that the memory640can interface with the XOR circuit650using the processor protocol. For example, the interface654may be configured to mimic the electrical characteristics of the processor610.

The logic of the XOR circuit650is configured to provide a bi-directional path for operating on the data transmitted on the DQ/DQS bus630. That is, the logic of the XOR circuit650provides a first path direction, which receives data on the interface652from the processor610, performs an operation (e.g., encryption) on the data, and forwards the resulting data (e.g., encrypted data) out the interface654to the memory640. The logic of the XOR circuit650also provides a second path direction, which receives data on the interface654from the memory640, performs an operation (e.g., decryption) on the data, and forwards the resulting data (e.g., decrypted plaintext data) out the interface652to the processor610. In embodiments, the XOR circuit XORs the input DQ data with cipher stream data to generate encrypted data (cipher text) or decrypted data (plaintext).

FIG.7illustrates an example embodiment of the XOR circuit inFIG.6. In some embodiments, the XOR circuit ofFIG.7is an application-specific integrated circuit (ASIC). The XOR circuit ofFIG.6may be used as the XOR logic module380fFIG.3.

The XOR circuit may include five primary modules as shown in the block diagram ofFIG.7. These modules are the DQ Cell module710, the DQS (Strobe) Cell module740, the Vref Calibration module720, the ZQ Calibration module730, and the Direction/Switch Control module700.

The DQ Cell module710includes logic that configures a bi-directional path for processing received data. The first direction of the path processes DQ data (CPU_DQ[7:0])719received from the processor610, and includes logic709,711, and712. In the first direction, the XOR circuit includes buffer logic709configured to mimic the logic of the memory640, such as the electrical characteristics of the memory640. For example, the input to logic709includes contributions of calibrated processor ODT (CPU_RTT) and calibrated reference voltage (from the Vref Calibration module720), which enables the logic709to mimic such electrical characteristics. The use of logic709makes the processor unaware that it is not interfacing directly with the memory.

The output of logic708is input into XOR gate logic711together with a cipher stream (CPU_CSTR[7:0])705generated for the processor. The cipher stream705is input to the XOR gate logic711via buffer logic707. In the embodiment ofFIG.7, the circuit includes separate cipher stream for the processor610and the memory640, but in other embodiments a single cipher stream may be used for both the processor610and the memory640. In some embodiments, the cipher stream as generated, as described in connection withFIG.3, based on a random cipher key and a cache line counter. The encrypted data output from the XOR gate logic711is then input into the buffer logic712, together contributions of direction input from the Direction/Switch CTRL700and calibrated output driver (DDR_RTT). The output from the buffer logic712is transmitted as the DQ data to the memory640. In embodiments, configuration of the buffer logic709,712, and707causes the circuit to process (e.g., encrypt) data without adding latency to the data transmission speed, such that the processing does not violate the memory protocol.

Similarly, the DQ Cell module710includes a second path direction. The second direction processes DQ data (DDR_DQ[7:0])717received from the memory640, and includes logic713,714,715. The buffer logic715is configured to mimic the logic of the processor610, such as the electrical characteristics of the processor. For example, the input to logic715includes contributions from calibrated memory ODT (DDR_RTT) and calibrated reference voltage (from the Vref Calibration module720), which enables the logic715to mimic such electrical characteristics. The use of logic715makes the memory unaware that it is not interfacing directly with the processor610.

The output of logic715is input into XOR gate logic714, together with a cipher stream (DDR_CSTR[7:0])706generated for the memory. The cipher stream706is input to the memory via buffer logic708. The decrypted data output from the XOR gate logic714is then input into the buffer logic713, together with contributions of direction input from the Direction/Switch CTRL700and calibrated output driver (DDR_RTT). The output from the buffer logic713is transmitted as the DQ data to the processor610. The DQ Cell module710also includes a By Pass Route for the DQ data received from the processor610or memory640. In embodiments, configuration of the buffer logic713,715, and708causes the circuit to process (e.g., decrypt) data without adding latency to the data transmission speed, such that the processing does not violate the memory protocol.

The DQS Cell module740includes logic that configures a bi-directional path for processing received data strobe. The first direction of the path processes the DQS data strobe (CPU_DQS_t[7:0])725received from the processor610, and includes buffer logic732,734, and736. This logic allows keeping the DQS data strobe in synchronization with the corresponding DQ data received from the processor610. For example, the input to logic709includes contributions of the same ODT (CPU_RTT) and output driver (DDR_RON) structure as used in the first direction of the DQS (Data) Cell710. The second direction of the path processes the DQS data strobe (DDR_DQS_t[7:0])718received from the memory640, and includes buffer logic733,735, and737. This buffer logic allows keeping the DQS data strobe in synchronization with the corresponding DQ data received from the memory640(by matching clock time delays in processing the data). For example, the input to logic709includes contributions of the same calibrated ODT (DDR_RTT) and output driver (CPU_RON) structure as used in the second direction of the DQS (Data) Cell710. The DQS Cell module740also includes a By Pass Route.

Parameter values of the CPU_RTT, CPU_RON, DDR_RTT, and DDR_RON may be selected using the CPU_RTT_SEL[2:0]741, CPU_RON_SEL742, DDR_RTT_SEL[2:0]743, and DDR_RON_SEL744, respectively.

The Vref Calibration module720calibrates the reference clock voltage for the circuit in accordance with DQ data communications between the processor610and memory640The Vref Calibration module720receives as inputs: VREFDQ_SIDE[1:0}719, VREFDQ_EN722, VREFDQ_RNG723, and VREFDQ_VAL[5:0]. The ZQ Calibration module730calibrates each ODT resistor (CPU_RTT and DDR_RTT) and output driver RON(CPU_RON and DDR_RON) for the DQ and DQS inputs to the corresponding external precision resistor of the processor610or memory640. The ZQ Calibration module730receives the following signals: CPU_DQS_t725, CPU_DQS_c726, ZQCS_EN727, and ZQCL_EN728, along with input from the Direction/Switch Control module700and Vref Calibration module720.

The Direction/Switch Control module700controls the direction and switches of the circuit in accordance with communications between the processor610and memory640. It receives the following signals to control the execution of the XOR circuit: DQS_DIR701, DQ_DIR702, ZQCL_EN728, ZQCS_EN727, standby mode (STB)703, and ByPass704that turns On/Off ODT, turns On/Off RON, sets both DQ and DQS side to Hi Z, or bypasses (shorts) processor to memory. In embodiments, a controller, such as AES660ofFIG.6, operatively coupled to the XOR circuit may determine the setting of these signals based on commands transmitted from the processor610to memory640.

FIG.8illustrates an example method for XOR'ing data in accordance with an embodiment of the present invention. In the embodiment ofFIG.8, the method may be executed by an XOR circuit, such as shown inFIG.7. The XOR circuit ofFIG.8has logic that configures a bi-directional path for processing (e.g., encrypting and/or decrypting) received data. At step810, the method receives a first set of data on a first interface of the XOR circuit, where the first interface is configured to mimic a memory protocol (e.g., DDR 1 protocol, DDR 2 protocol, DDR 3 protocol, DDR 4 protocol, etc.). For example, the first interface may be configured to mimic the electrical characteristics, timing characteristics, etc. of the memory protocol. For another example, the data may be a DQ signal received from the processor on a DQ/DQS bus, which is transmitted in accordance with the memory protocol. The first interface is associated with a first direction of the bi-directional path of the circuit. At step820, the method executes, via the first direction of the bi-directional path, an operation (e.g., an encryption operation) on the data, and forwards the modified (e.g., encrypted data) via a second interface. In embodiments, the method performs the operation, without adding latency to the data transmission speed between the processor and memory, thereby avoid violation of the memory protocol. For example, the XOR circuit is configured to execute the operation within a given clock time (e.g., ½ clock cycle) to prevent adding such latency. In some embodiments, avoiding adding latency to the transmission speed is achieved in the system when neither (i) clock speed is reduced, nor (ii) additional clocks are added.

At step830, the method receives a second set of data on a second interface of the XOR circuit, where the second interface is configured to mimic a processor protocol (e.g., Intel Xeon protocol, etc.). For example, the second interface may be configured to mimic the electrical characteristics, timing characteristics, etc. of the processor protocol. For another example, the data may be a DQ signal received from the memory on a DQ/DQS bus, which is transmitted in accordance with the processor protocol. The second interface is associated with a second direction of the bi-directional path of the circuit. At step840, the method executes, via the second direction of the bi-directional path, an operation (e.g., decryption operation) on the data, and forwards the modified (e.g., decrypted plaintext data) to the processor via the first interface. In embodiments, the method performs the operation, without adding latency to the data transmission speed between the processor and memory, thereby avoid violation of the processor protocol. For example, the XOR circuit is configured to execute the operation within a given clock time (e.g., ½ clock cycle) to prevent adding such latency.

The present invention may be embodied in many different forms, including, but in no way limited to, computer program logic for use with a processor (e.g., a microprocessor, microcontroller, digital signal processor, or general purpose computer), programmable logic for use with a programmable logic device (e.g., a Field Programmable Gate Array (FPGA) or other PLD), discrete components, integrated circuitry (e.g., an Application Specific Integrated Circuit (ASIC)), or any other means including any combination thereof.

While the invention has been particularly shown and described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended clauses. While some of these embodiments have been described in the claims by process steps, an apparatus comprising a computer with associated display capable of executing the process steps in the clams below is also included in the present invention. Likewise, a computer program product including computer executable instructions for executing the process steps in the claims below and stored on a computer readable medium is included within the present invention.