Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels

A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.

BACKGROUND

This relates to methods of fabricating semiconductor devices with field effect transistors having gates that straddle fins of channel forming material (so-called FinFETs).

Conventional integrated circuit devices, such as SRAM devices, have NMOS and PMOS fin field effect transistors (FinFETs) with different channel crystal orientations laid out in a non-aligned fin layout (referred to as a “non-Manhattan” layout). Adjacent fins of different conductivity type are rotated by 45° to accommodate for the different crystal orientations of the substrate surfaces.

FIG. 1(Prior Art) illustrates a conventional layout for a multiple gate FinFET (MuGFET) device100. As shown, MuGFET100has a semiconductor material fin130straddled by a saddle-like gate120. The fin110and gate120are formed on an oxide layer140(e.g., SiO2) formed on a semiconductor substrate. The channels for MuGFET100are located on the sidewalls150of the fin130. For a usual <110> notch (001) surface wafer, the sidewall150of the fin130has a (110) crystal orientation if fin130is laid out at 0° or 90° rotation with respect to the notch. If the rotation of the fin130is laid out at 45° with respect to the notch, the fin130sidewalls150will have a (100) crystal orientation.

A (110) crystal orientation surface is good for channel hole mobility but poor for channel electron mobility, while the (100) crystal orientation channel surface is poor for channel hole mobility but good for channel electron mobility. Thus, a (110) sidewall orientation is a preferred orientation for PMOS MuGFETs and a (100) sidewall orientation is a preferred orientation for NMOS MuGFETs. To provide preferred surface orientations for PMOS and NMOS MuGFETs on the same substrate, conventional fabrication methods use mixed rotations of the fins130of 0° (or 90°) and 45°. Such mixed rotations require increases in layout area of an integrated circuit device by approximately 25% and increase lithography difficulties.

FIG. 2A(Prior Art) illustrates a top view of an example non-Manhattan layout design of a conventional SRAM storage cell which uses both PMOS and NMOS FinFETs. As shown, SRAM storage cell200has a plurality of fins210with runs of 0° and 45° rotations straddled by gates220. Fins210have enlarged pad portions away from the gates220which provide locations for connection to source/drain regions by contacts215. Gates220have enlarged pad portions away from the fins210for connection to gate electrodes by contacts225. Using industry standards for spacing between components and measurements taken between centers of outside contact points of contacts215,225, the example conventional layout for SRAM storage cell200shown inFIG. 2occupies a layout area of approximately 500 nm by approximately 812.5 nm, or approximately 406,250 nm2. (Elements of the layout for storage cell200given inFIG. 2Aare marked to show correspondence with source/drains S, D or S/D and gates G of pull-up transistors PT1, PT2, drive transistors DT1, DT2and access transistors AT1, AT2of a typical storage cell schematic diagram such as given in FIG. 1b of U.S. Pat. No. 7,087,493 which is reproduced asFIG. 2Bherein.)

SUMMARY

Embodiments described herein relate to methods for forming integrated circuit devices having fin field effect transistors (FinFETs) with different channel surface crystal orientations arranged in parallel or perpendicular alignment.

In a described example, an integrated circuit in the form of an example SRAM storage cell implementation has a first fin with a (110) crystal orientation sidewall defining a transistor channel of a PMOS FinFET in parallel alignment with a transistor channel of an NMOS FinFET defined by a second fin having a (100) crystal orientation sidewall.

The described methods enable PMOS FinFETs and NMOS FinFETs to be laid out in Manhattan layouts, i.e., fins rotated with respect to notches at 0° and 90°. By avoiding 45° rotations, substrate area requirements for mixed NMOS and PMOS FinFET layouts can be minimized. Moreover, enabling use of Manhattan layouts having 0° and 90° rotations simplifies photolithography processes used for fabrication.

DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments of the invention are described for illustrative purposes, with reference toFIGS. 3-6, in a context of a method of forming an integrated circuit device having PMOS and NMOS multiple gate FinFETs (MuGFETs) with aligned fins of different channel surface crystal orientations.

FIG. 3shows a step of providing a direct silicon bonded (DSB) substrate300having an upper silicon layer310with a (110) crystal orientation top surface over a lower silicon substrate320with a (100) crystal orientation top surface. The upper silicon layer310includes the (110) top surface by virtue of its crystalline structure and the lower silicon substrate320includes the (100) top surface by virtue of its crystalline structure. The DSB substrate300may be created using conventional techniques for creating a DSB substrate300.

FIG. 4shows a later step wherein the DSB substrate300ofFIG. 3has been processed using conventional photomask/hard mask and etching patterning techniques followed by an amorphorization implant to selectively amorphize a PMOS region430of the crystalline structure of upper silicon layer310. The crystalline structures of the lower silicon substrate320and remaining portions of the upper silicon layer310outside the PMOS region430are not implanted during the PMOS region amorphorization implant, so remain the same.

FIG. 5shows a later step wherein the DSB substrate300ofFIG. 4has been further processed to regrow and recrystallize the amorphized silicon within the amorphorized PMOS region430of upper silicon layer310. The amorphized silicon is regrown using the underlying crystalline structure of the lower silicon substrate320as a template, thereby giving the recrystallized PMOS region430a (100) crystal orientation top surface. The crystalline structures of the lower silicon substrate320and the remaining portions of the upper silicon layer310outside the PMOS region430are not regrown and recrystallized during the regrowth and recrystallization of the amorphorized PMOS region430, so remain the same.

FIG. 6shows a later step wherein the DSB substrate300ofFIG. 5has been further processed using conventional photomask/hard mask and etching patterning techniques to pattern the recrystallized PMOS region430and unrecrystallized remaining portions of the upper silicon layer310to form adjacent fins630,640having sidewall surfaces of different crystal orientations laid out in general parallel planar alignment. The patterning removes parts of the recrystallized PMOS region430and remaining portions of the upper silicon layer310from around the fin630to define a PMOS FinFET fin including a (110) crystal orientation sidewall channel and a (100) crystal orientation top surface. The patterning also removes parts of the remaining portions of the upper silicon layer310from around the fin640to define an NMOS FinFET fin including a (100) crystal orientation sidewall channel and a (110) crystal orientation top surface.

Thus, as described, using a hybrid orientation technology (HOT) direct silicon bonded (DSB) substrate300wherein the silicon DSB layer310has a (110)-oriented crystal top surface and the silicon wafer substrate320has a (100)-oriented top surface, PMOS FinFET regions in the DSB layer310may be amorphized and regrown to form PMOS multiple gate FinFETs (MuGFETs) having (100)-oriented top surfaces and (110)-oriented sidewalls providing sidewall channels with hole mobility in the <110> direction in general parallel or perpendicular (0° or 90°) alignment with channels for electron mobility in the <100> direction provided by NMOS MuGFETs formed in unamorphized regions having (110)-oriented top surfaces and (100)-oriented sidewalls.

FIG. 7illustrates a top view of an example Manhattan layout design of an SRAM storage cell700having a plurality of fins710straddled by gates720. Fins710have enlarged pad portions away from the gates720which provide locations for connection to source/drain regions by contacts715. Gates720have enlarged pad portions away from the fins710for connection to gate electrodes by contacts725. As for the layout of fins210of SRAM storage cell200shown inFIG. 2, fins710preferably have different sidewall crystal orientations for defining the channels of PMOS FinFETs and NMOS FinFETs. However, in contrast to the fins210of SRAM storage cell200, the layout of SRAM storage cell700may be accomplished without the necessity for rotating the different crystal orientation sidewall fins710at 45° relative to each other. In the SRAM storage cell700, the fins710can be laid out with fins710of different sidewall crystal orientations in 0° or 90° alignment. Fins710for PMOS FinFETs may be formed as described above for patterned fins630and fins710for NMOS FinFETs may be formed as described above for patterned fins640.

Using industry standards for spacing between components and measurements taken between centers of outside contact points of contacts715,725, the example layout for SRAM storage cell700shown inFIG. 7occupies a layout area of approximately 475 nm by approximately 755 nm, or approximately 358,625 nm2. This provides a 47,625 nm2(or approximately 25% reduction) in area over the 406,250 nm2area of the conventional layout shown inFIG. 2. (As for the layout for the storage cell200given inFIG. 2, elements of the layout for storage cell700given inFIG. 7are marked to show correspondence with source/drains S, D or S/D and gates G of pull-up transistors PT1, PT2, drive transistors DT1, DT2and access transistors AT1, AT2of the storage cell schematic diagram ofFIG. 2B.)

The principles disclosed herein apply equally to forming fins of NMOS FinFETs with (110)-oriented sidewall surfaces (<110> channel direction) and (100)-oriented top surfaces and to forming fins of PMOS FinFETs with (100)-oriented sidewall surfaces (<100> channel direction) and (110)-oriented top surfaces on a common substrate having the (110)-oriented top surface DSB layer at 0° and 90°. Incorporating a PMOS FinFET having a (100)-oriented sidewall surface on a common substrate with an NMOS FinFET also having a (100) crystal orientation sidewall surface might be done, for example, when it is considered advantageous to have a weak PMOS transistor and a strong NMOS transistor for an SRAM write operation.

The same principles may also be applied to a hybrid orientation technology (HOT) direct silicon bonded (DSB) substrate300having a (100)-oriented top surface upper layer over a (110)-oriented top surface wafer substrate. In such case, a region of the upper layer is amorphized and regrown to have a (110)-oriented top surface crystal orientation, with unamorphized portions left with the original (100)-oriented top surface.

The same principles may also be applied to a DSB substrate having same (100)-oriented top surfaces on both the upper silicon layer and the lower silicon substrate. In such case, the DSB top layer's notch is rotated by 45° relative to the DSB substrate, placing the NMOS FinFET channel direction in a <100> direction instead of a <110> direction, prior to further processing as disclosed above.

Moreover, the principles disclosed herein also make a (111)-oriented surface accessible by aligning a fin layout to a <112> direction on a (110)-oriented substrate surface. All three primary crystal surfaces are accessible to semiconductor devices using the principles disclosed herein.

Although the example disclosed herein is applied to a DSB substrate, the teachings disclosed herein may also be applied to other hybrid orientation substrates having a (110) crystal orientation on surface layer and a (100) crystal orientation surface layer.

Those skilled in the art to which the invention relates will appreciate that modifications to the above embodiments and additional embodiments are possible within the scope of the claimed invention.