NITRIDE SEMICONDUCTOR DEVICE

A nitride semiconductor device includes: a substrate; a nitride semiconductor layer above the substrate; a high-resistance layer above the nitride semiconductor layer; a p-type nitride semiconductor layer above the high-resistance layer; a first opening penetrating through the p-type nitride semiconductor layer and the high-resistance layer to the nitride semiconductor layer; an electron transport layer and an electron supply layer covering an upper portion of the p-type nitride semiconductor layer and the first opening; a gate electrode above the electron supply layer; a source electrode in contact with the electron supply layer; a second opening penetrating through the electron supply layer and the electron transport layer to the p-type nitride semiconductor layer; a potential fixing electrode in contact with the p-type nitride semiconductor layer at a bottom part of the second opening; and a drain electrode.

TECHNICAL FIELD

The present disclosure relates to a nitride semiconductor device.

BACKGROUND ART

Nitride semiconductors, typified by gallium nitride (GaN), are wide-gap semiconductors having large band-gaps, and feature greater breakdown fields and higher electrode saturated drift velocities than compound semiconductors including, for example, gallium arsenide (GaAs) or silicon (Si) semiconductors. For example, band gaps of GaN and aluminum nitride (AlN) are 3.4 eV and 6.2 eV at room temperature, respectively. As such, power transistors using nitride semiconductors, which are useful in achieving higher outputs and breakdown voltages, are being researched and developed. For example, Patent Literature (PTL) 1 discloses a vertical field-effect transistor (FET) including a GaN semiconductor layer.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

If the conventional vertical FET is used for a power converter circuit, a potential on the drain side may become lower than a potential on the source side when the conventional vertical FET is OFF, causing a great current to flow from the source to the drain, that is, a reverse conductive operation may occur. With the conventional vertical FET, there is a problem in that a breakdown voltage decreases after the reverse conductive operation.

In view of this, the present disclosure provides a nitride semiconductor device capable of suppressing a decrease in breakdown voltage due to a reverse conductive operation.

Solution to Problem

A nitride semiconductor device according to one aspect of the present disclosure includes: a substrate; a first nitride semiconductor layer above the substrate; a first high-resistance layer above the first nitride semiconductor layer, the first high-resistance layer having a resistance higher than a resistance of the first nitride semiconductor layer; a first p-type nitride semiconductor layer above the first high-resistance layer; a first opening penetrating through the first p-type nitride semiconductor layer and the first high-resistance layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided in stated order from a substrate side, the electron transport layer and the electron supply layer covering an upper portion of the first p-type nitride semiconductor layer and the first opening; a gate electrode above the electron supply layer and covering the first opening; a source electrode away from the gate electrode and in contact with the electron supply layer; a second opening penetrating through the electron supply layer and the electron transport layer to the first p-type nitride semiconductor layer; a potential fixing electrode in contact with the first p-type nitride semiconductor layer at a bottom part of the second opening; and a drain electrode below the substrate.

A nitride semiconductor device according to another aspect of the present disclosure includes: a substrate; a first nitride semiconductor layer above the substrate; a first p-type nitride semiconductor layer above the first nitride semiconductor layer; a first opening penetrating through the first p-type nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided in stated order from a substrate side, the electron transport layer and the electron supply layer covering an upper portion of the first p-type nitride semiconductor layer and the first opening; a gate electrode above the electron supply layer and covering the first opening; a source electrode away from the gate electrode and in contact with the electron supply layer; a second opening penetrating through the electron supply layer and the electron transport layer to the first p-type nitride semiconductor layer; a potential fixing electrode in contact with the first p-type nitride semiconductor layer at a bottom part of the second opening; and a drain electrode below the substrate. The potential fixing electrode includes a material in Schottky contact with the first p-type nitride semiconductor layer.

A nitride semiconductor device according to still another aspect of the present disclosure includes: a substrate; a first nitride semiconductor layer above the substrate; a first p-type nitride semiconductor layer above the first nitride semiconductor layer; a first opening penetrating through the first p-type nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided in stated order from a substrate side, the electron transport layer and the electron supply layer covering an upper portion of the first p-type nitride semiconductor layer and the first opening; a gate electrode above the electron supply layer and covering the first opening; a source electrode away from the gate electrode and in contact with the electron supply layer; a second opening penetrating through the electron supply layer and the electron transport layer to the first p-type nitride semiconductor layer; a potential fixing electrode in contact with the first p-type nitride semiconductor layer at a bottom part of the second opening; and a drain electrode below the substrate. A contact portion of the first p-type nitride semiconductor layer which is in contact with the potential fixing electrode has a thickness greater than or equal to 50 percent of a thickness of a non-contact portion of the first p-type nitride semiconductor layer which is not in contact with the potential fixing electrode, and the thickness of the non-contact portion is greater than or equal to 400 nm.

Advantageous Effects of Invention

According to the present disclosure, it is possible to provide a nitride semiconductor device capable of suppressing a decrease in breakdown voltage due to a reverse conductive operation.

DESCRIPTION OF EMBODIMENTS

(Underlying Knowledge Forming the Basis of the Present Disclosure)

The inventors of the present disclosure discovered that the conventional vertical transistor described above in the “Background Art” section has the following problems.

FIG. 1is a circuit diagram of a general power converter circuit. Power converter circuit1shown byFIG. 1is a step-up circuit. For example, power converter circuit1generates output voltage Vout of 400 V by stepping up power supply voltage Vin of 100 V generated by power source3, and supplies generated output voltage Vout to load

Power converter circuit1includes capacitor4, inductor5, gate driving circuit6, capacitor7, and two FETs8aand8b. The source of FET8ais connected to the drain of FET8b. Power source3is connected to a connecting point between two FETs8aand8bvia inductor5. Gate driving circuit6exclusively switches two FETs8aand8bbetween ON and OFF. For example, gate driving circuit6supplies a complementary pulse width modulation (PWM) signal to the gate of each of FETs8aand8b.

Power is accumulated in inductor5by switching FET8aOFF and FET8bON. The power accumulated in inductor5is released by switching FET8aON and FET8bOFF, and output voltage Vout higher than power supply voltage Vin is supplied to load2.

When FETs8aand8bare switched between ON and OFF, both may be switched ON or OFF momentarily at the same time. In this case, a reverse conductive operation occurs in each of FETs8aand8b. To put it another way, a potential on the drain side becomes lower than a potential on the source side, causing a great current to flow from the source to the drain.

As a result of the research by the inventors, they discovered that in a vertical FET, after a great current is caused to flow by a reverse conductive operation, a breakdown voltage of the vertical FET decreases. This decrease in breakdown voltage, which did not occur in a horizontal FET in which only a device surface layer is used as a current path, is a problem unique to the vertical FET.

FIG. 2is a circuit diagram illustrating an equivalent circuit of a vertical FET. As shown byFIG. 2, the vertical FET includes a parasitic diode between the source and the drain. The parasitic diode is a parasitic p-n diode formed of a parasitic p-n junction of the vertical FET.

As a result of the repeated research by the inventors, they discovered that a decrease in breakdown voltage occurs when a great current flows through the parasitic p-n diode of the vertical FET. Accordingly, the inventors found out the importance of suppressing electrical conduction to the parasitic p-n diode or a process technique when the source electrode is made into contact with a GaN layer, in order to suppress the decrease in breakdown voltage.

In view of the above, a nitride semiconductor device according to one aspect of the present disclosure includes: a substrate; a first nitride semiconductor layer above the substrate; a first high-resistance layer above the first nitride semiconductor layer, the first high-resistance layer having a resistance higher than a resistance of the first nitride semiconductor layer; a first p-type nitride semiconductor layer above the first high-resistance layer; a first opening penetrating through the first p-type nitride semiconductor layer and the first high-resistance layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided in stated order from a substrate side, the electron transport layer and the electron supply layer covering an upper portion of the first p-type nitride semiconductor layer and the first opening; a gate electrode above the electron supply layer and covering the first opening; a source electrode away from the gate electrode and in contact with the electron supply layer; a second opening penetrating through the electron supply layer and the electron transport layer to the first p-type nitride semiconductor layer; a potential fixing electrode in contact with the first p-type nitride semiconductor layer at a bottom part of the second opening; and a drain electrode below the substrate.

The first high-resistance layer is between the first nitride semiconductor layer and the first p-type nitride semiconductor layer. The first nitride semiconductor layer is formed usually using an n-type nitride semiconductor. Accordingly, the first high-resistance layer makes it possible to block a current path of a parasitic p-n diode formed between the first nitride semiconductor layer and the first p-type nitride semiconductor layer. As a result, since it is possible to prevent a great current from flowing through the parasitic p-n diode at time of a reverse conductive operation, it is possible to suppress a decrease in breakdown voltage due to the reverse conductive operation.

For example, the first high-resistance layer may be a GaN layer containing carbon. Alternatively, for example, the first high-resistance layer may be an undoped GaN layer.

With this configuration, as with the first nitride semiconductor layer and the first p-type nitride semiconductor layer, it is possible to continuously form the first high-resistance layer through epitaxial growth. Since impurities etc. are less likely to be mixed in an interface of each of the first nitride semiconductor layer, the first high-resistance layer, and the first p-type nitride semiconductor layer, it is possible to suppress the characteristic degradation of the nitride semiconductor device. It should be noted that it is possible to achieve GaN in a resistance state higher than a resistance state of undoped GaN by causing GaN to contain carbon.

For example, the potential fixing electrode may include a material in Schottky contact with the first p-type nitride semiconductor layer.

With this configuration, it is possible to form a Schottky barrier diode using the source electrode and the first p-type nitride semiconductor layer. A rise voltage of the parasitic p-n diode is high due to the reverse characteristics of the Schottky barrier diode, compared to when the source electrode and the first p-type nitride semiconductor layer are in ohmic contact. It should be noted that the rise voltage of the parasitic p-n diode is a source-drain voltage when a current starts to flow through the parasitic p-n diode. Accordingly, it is possible to prevent the current from flowing through the parasitic p-n diode and the decrease in breakdown voltage.

For example, a contact portion of the first p-type nitride semiconductor layer which is in contact with the potential fixing electrode may have a thickness greater than or equal to 50 percent of a thickness of a non-contact portion of the first p-type nitride semiconductor layer which is not in contact with the potential fixing electrode, and the thickness of the non-contact portion may be greater than or equal to 400 nm.

With this configuration, it is possible to keep away from the parasitic p-n junction a damage layer when the second opening reaching the first p-type nitride semiconductor layer is formed. As a result, it is possible to suppress the decrease in breakdown voltage due to the damage layer.

For example, the nitride semiconductor device according to one aspect of the present disclosure may further include a second p-type nitride semiconductor layer between the gate electrode and the electron supply layer.

With this configuration, the second p-type nitride semiconductor layer makes it possible to decrease a carrier concentration immediately below the gate electrode, and it is possible to shift a threshold voltage of an FET toward the positive side. Accordingly, it is possible to allow the nitride semiconductor device to operate as a normally-off FET.

For example, the nitride semiconductor device according to one aspect of the present disclosure may further include a second high-resistance layer above the first p-type nitride semiconductor layer, the second high-resistance layer having a resistance higher than a resistance of the first p-type nitride semiconductor layer. The first opening may further penetrate through the second high-resistance layer, and the electron transport layer and the electron supply layer may cover an upper portion of the second high-resistance layer.

With this configuration, the second high-resistance layer makes it possible to prevent the electron transport layer, the first p-type nitride semiconductor layer, and the first nitride semiconductor layer from forming a parasitic bipolar transistor having a parasitic npn structure.

For example, the potential fixing electrode may be electrically connected to the source electrode.

With this configuration, since it is possible to stabilize a potential of the first p-type nitride semiconductor layer, it is possible to ensure a breakdown voltage.

Embodiments of the present disclosure will be described in detail hereinafter with reference to the drawings.

Note that the following embodiments describe comprehensive or specific examples of the present disclosure. The numerical values, shapes, materials, constituent elements, arrangements and connection states of constituent elements, steps, orders of steps, and the like in the following embodiments are merely examples, and are not intended to limit the present disclosure. Additionally, of the constituent elements in the following embodiments, constituent elements not denoted in the independent claims will be described as optional constituent elements.

Additionally, the drawings are schematic diagrams, and are not necessarily exact illustrations. As such, the scales and so on, for example, are not necessarily consistent from drawing to drawing. Furthermore, configurations that are substantially the same are given the same reference signs in the drawings, and redundant descriptions will be omitted or simplified.

Additionally, in the present specification, terms indicating relationships between elements, such as “parallel” or “perpendicular”, terms indicating the shapes of elements, such as “rectangular”, and numerical value ranges do not express the items in question in the strictest sense, but rather include substantially equivalent ranges, e.g., differences of several percent, as well.

Additionally, in the present specification, terms such as “above” and “below” do not indicate the upward direction (vertically upward) and the downward direction (vertically downward) in an absolute spatial sense, but rather are used as terms defining relative positional relationships based on layering orders in layered configurations. Moreover, terms such as “above” and “below” are used not only in cases where two constituent elements are disposed with an interval therebetween and another constituent element is present between the stated two constituent elements, but also in cases where two constituent elements are disposed in close contact with each other.

In the present specification, “AlGaN” refers to an AlxGa1-xN ternary mixed crystal (where 0≤x≤1). Hereinafter, for multidimensional mixed crystals, the arrangements of the respective constituent element signs are abbreviated, e.g., AlInN, GaInN and the like. For example, AlxGa1-x-yInyN (where 0≤x≤1, 0≤y≤1), which is an example of a nitride semiconductor, is abbreviated as “AlGaInN”.

The following describes the embodiments of the present disclosure with reference to the drawings.

First, the configuration of a nitride semiconductor device according to Embodiment 1 will be described with reference toFIG. 3andFIG. 4.

FIG. 3is a cross-sectional view of nitride semiconductor device10according to the present embodiment.FIG. 4is an enlarged partial cross-sectional view of the vicinity of potential fixing electrode36of nitride semiconductor device10according to the present embodiment.

Nitride semiconductor device10is a device having a layered structure of semiconductor layers that take a nitride semiconductor such as GaN or AlGaN as a primary component. Specifically, nitride semiconductor device10has a heterostructure of an AlGaN film (electron supply layer26) and a GaN film (electron transport layer24).

In the heterostructure of an AlGaN film and a GaN film, highly-concentrated two-dimensional electron gas (2DEG) is produced at the hetero interface due to spontaneous polarization or piezo polarization on a (0001) plane. The device therefore has a characteristic where a sheet carrier concentration of at least 1×1013cm−2is achieved at the hetero interface, even in an undoped state.

Nitride semiconductor device10is a field-effect transistor (FET) that uses two-dimensional electron gas25produced in electron transport layer24as a channel. Specifically, nitride semiconductor device10is what is known as a vertical FET.

Substrate12is a substrate including a nitride semiconductor. Substrate12is, for example, a substrate formed from n+-type GaN with a thickness of 300 μm and a donor concentration of 1×1018cm−3. A top face of substrate12substantially coincides with the (0001) plane (c plane) of GaN.

It should be noted that n-type, n+-type, n−-type, p-type, p+-type, and p−-type each indicate a conductivity type of a semiconductor. n-type, n+-type, and n−-type are examples of a first conductivity type of a nitride semiconductor. p-type, p+-type, and p−-type are examples of a second conductivity type that differs from the first conductivity type in polarity.

Drift layer14is an example of a first nitride semiconductor layer provided above substrate12. Drift layer14is, for example, a film formed from n−-type GaN with a thickness of 8 μm. Drift layer14is provided so as to be in contact with the top face of substrate12. A donor concentration of drift layer14is lower than the donor concentration of substrate12, and is at least 1×1015cm−3and at most 1×1017cm−3, for example. Additionally, drift layer14may include carbon (C). A carbon concentration of drift layer14is lower than a carbon concentration of high-resistance layer16, and is at least 1×1015cm−3and at most 2×1017cm−3, for example.

High-resistance layer16is an example of a first high-resistance layer provided above drift layer14. High-resistance layer16has a resistance higher than a resistance of drift layer14. High-resistance layer16is 200 nm thick, for example. High-resistance layer16is provided so as to be in contact with a top face of drift layer14.

High-resistance layer16may include any material as long as high-resistance layer16is an insulating layer, a semi-insulating layer, or a semiconductor layer having fewer impurities. High-resistance layer16is, for example, a GaN layer containing carbon. The carbon concentration is, for example, at least 3×1017cm−3, and may be preferably at least 1×1018cm−3. High-resistance layer16may be formed by implanting, for example, magnesium (Mg), ferrum (Fe), or boron (B) ions into GaN. As long as other ion types used for ion implantation can produce a high-resistance state, the other ion types can achieve the same effect as the above ion types.

Moreover, high-resistance layer16may be an undoped GaN layer. It should be noted that the term “undoped” means that a material is not substantially doped with a dopant such as Si, oxygen (O), or Mg that changes the polarity of GaN to n-type or p-type. For example, an oxygen concentration and a silicon concentration of high-resistance layer16are lower than the carbon concentration, are at most 5×1016cm−3, and may be preferably at most 2×1016cm−3.

First base layer18is an example of a first p-type nitride semiconductor layer provided above high-resistance layer16. First base layer18is, for example, a film formed from p−-type GaN with a thickness of 400 nm. First base layer18serves as a blocking layer that prevents leak current flowing from drain electrode40toward source electrode32without passing through a channel. First base layer18is connected to potential fixing electrode36and is fixed to a predetermined potential.

Second base layer20is an example of an n-type nitride semiconductor layer provided above high-resistance layer16. Second base layer20is a film formed from n+-type GaN. Second base layer20has, for example, a thickness of 300 nm and a donor concentration of at least 1×1017cm−3and at most 3×1018cm−3.

Gate opening22is an example of a first opening that penetrates through second base layer20, first base layer18, and high-resistance layer16to drift layer14. As shown byFIG. 3, gate opening22includes bottom part22aand side wall part22b. Bottom part22ais the top face of drift layer14and is located lower than an interface between high-resistance layer16and drift layer14. Side wall part22bincludes an end face of each of second base layer20, first base layer18, and high-resistance layer16, and part of the top face of drift layer14. Side wall part22bof gate opening22is inclined at an angle with respect to a main surface of substrate12. For example, the cross-sectional shape of gate opening22is an inverted trapezoid, and more specifically, an inverted isosceles trapezoid. It should be noted that the cross-sectional shape of gate opening22may be a rectangle.

Electron transport layer24is provided so as to cover an upper portion of first base layer18and gate opening22. Specifically, electron transport layer24is provided so as to be in contact with a top face of second base layer20and side wall part22band bottom part22aof gate opening22. Electron transport layer24is a first regrowth layer formed by regrowth of the nitride semiconductor after gate opening22is formed. Electron transport layer24has a substantially even thickness and curves along the shape of gate opening22. Electron transport layer24is, for example, a film formed from undoped GaN having a thickness of 100 nm. It should be noted that electron transport layer24may be given n-type conductivity by being doped with Si etc.

Additionally, an approximately 1 nm-thick AlN layer may be provided, as a second regrowth layer, between electron transport layer24and electron supply layer26. The AlN layer suppresses alloy scattering, which makes it possible to improve channel mobility. It should be noted that the AlN layer need not be provided, and electron transport layer24and electron supply layer26may be in direct contact with each other. Two-dimensional electron gas25to be a channel is produced at an interface between the AlN layer and electron transport layer24.

Electron supply layer26is provided above electron transport layer24. Specifically, electron supply layer26is provided along a top face of electron transport layer24. Electron supply layer26is a third regrowth layer formed by regrowth of the nitride semiconductor after gate opening22is formed. Electron supply layer26has a substantially even thickness and curves along the curved shape of the top face of electron transport layer24. Electron supply layer26is, for example, a film formed from AlGaN having a thickness of 50 nm.

Source opening30is an example of a third opening that penetrates through at least electron supply layer26and exposes at least part of an end face of electron transport layer24, at a position distanced from gate electrode38. Specifically, source opening30penetrates through electron supply layer26, electron transport layer24, and second base layer20to first base layer18.

As shown byFIG. 3andFIG. 4, source opening30includes bottom part30aand side wall part30b. Bottom part30ais a top face of first base layer18and is located lower than an interface between first base layer18and second base layer20. Side wall part30bincludes an end face of each of electron supply layer26, electron transport layer24, and second base layer20, and part of the top face of first base layer18. Side wall part30bof source opening30is substantially vertical relative to the main surface of substrate12. For example, the cross-sectional shape of source opening30is a rectangle, but may be an inverted trapezoid, and more specifically, an inverted isosceles trapezoid, as with gate opening22.

Source electrode32is provided away from gate electrode38and is in contact with electron supply layer26and electron transport layer24. Source electrode32is provided so as to cover bottom part30aand side wall part30bof source opening30. Source electrode32is in direct contact with two-dimensional electron gas25at side wall part30bof source opening30.

Source electrode32is formed using a conductive material such as a metal. For example, a material which makes ohmic contact with an n-type semiconductor, such as titanium (Ti), can be used as the material of source electrode32. Source electrode32may have a layered structure of a Ti film and an Al film. The layered structure in which the Al film is lower than the Ti film is represented as Ti/Al in the present specification.

Electrode opening34is an example of a second opening that penetrates through electron supply layer26, electron transport layer24, and second base layer20to first base layer18. As shown byFIG. 3andFIG. 4, electrode opening34includes bottom part34aand side wall part34b. Bottom part34ais the top face of first base layer18and is located lower than the interface between first base layer18and second base layer20. Side wall part34bincludes an end face of each of electron supply layer26, electron transport layer24, and second base layer20, and part of the top face of first base layer18. Side wall part34bof electrode opening34is substantially vertical relative to the main surface of substrate12. For example, the cross-sectional shape of electrode opening34is a rectangle, but may be an inverted trapezoid, and more specifically, an inverted isosceles trapezoid, as with gate opening22.

Potential fixing electrode36is in contact with first base layer18at bottom part34aof electrode opening34. In the present embodiment, potential fixing electrode36is electrically connected to source electrode32. It should be noted thatFIG. 4schematically shows the electrical connection between potential fixing electrode36and source electrode32using the thick broken line. The electrical connection method is not particularly limited, and, for example, source electrode32and potential fixing electrode36are electrically connected using a source pad (not shown) provided above source electrode32.

Potential fixing electrode36is formed using a conductive material such as a metal. For example, a material which makes ohmic contact with first base layer18, such as palladium (Pd), nickel (Ni), gold (Au), or tungsten silicide (WSi), can be used as the material of potential fixing electrode36. In other words, in the present embodiment, potential fixing electrode36and source electrode32are each formed using a different material.

Gate electrode38is provided above electron supply layer26so as to cover gate opening22. Gate electrode38is formed along a top face of electron supply layer26and in contact with the top face of electron supply layer26, and is formed at a substantially uniform thickness.

Gate electrode38is formed using a conductive material such as a metal. Gate electrode38is formed using Pd, for example. It should be noted that a material which is brought into Schottky contact with an n-type semiconductor can be used as the material of gate electrode38, and thus a Ni-based material, WSi, or Au can be used, for example. In addition, gate electrode38and potential fixing electrode36can be formed using the same material. For this reason, it is possible to form gate electrode38and potential fixing electrode36in the same process.

Drain electrode40is provided below substrate12. Specifically, drain electrode40is provided in contact with a bottom face (a face opposite to a crystal growth face) of substrate12. Drain electrode40is formed using a conductive material such as a metal. For example, as with the material of source electrode32, a material which makes ohmic contact with an n-type semiconductor can be used as the material of drain electrode40.

Each nitride semiconductor layer can be formed through epitaxial growth such as metalorganic vapor-phase epitaxy (MOVPE) or molecular beam epitaxy (MBE). Specifically, drift layer14, high-resistance layer16, first base layer18, second base layer20, electron transport layer24, and electron supply layer26can be formed in stated order using an MOVPE device. Drift layer14, high-resistance layer16, first base layer18, and second base layer20are continuously formed. Subsequently, after gate opening22is formed, electron transport layer24and electron supply layer26are continuously formed.

Gate opening22, source opening30, and electrode opening34are formed through photolithography and etching. Etching is, for example, dry etching. It should be noted that electrode opening34can be formed concurrently with source opening30. For this reason, bottom part34aof electrode opening34and bottom part30aof source opening30are the same distance from substrate12.

Source electrode32, potential fixing electrode36, gate electrode38, and drain electrode40are each formed by forming a metal film through vapor deposition or sputtering etc. and patterning the metal film into a predetermined shape. Patterning can be performed through photolithography and etching. It should be noted that drain electrode40need not be patterned and may be provided on the entire bottom face of substrate12.

[Characteristic Features and Effects]

The following describes characteristic features in above-described nitride semiconductor device10.

In nitride semiconductor device10, high-resistance layer16is inserted between drift layer14and first base layer18. In other words, high-resistance layer16is inserted in a parasitic p-n junction of a parasitic p-n diode including n-type GaN (drift layer14) and p-type GaN (first base layer18), which makes it difficult for a current to flow between first base layer18and drift layer14. In short, it is possible to block the current path of the parasitic p-n junction diode.

Accordingly, even when a potential on the drain side becomes lower than a potential on the source side in the case where nitride semiconductor device10is used as FET8aor8bof power converter circuit1shown byFIG. 1, it is possible to prevent a great current from flowing from source electrode32to drain electrode40. Since a reverse conductive operation makes it difficult for a great current to flow through the parasitic p-n diode, it is possible to suppress a decrease in breakdown voltage due to the reverse conductive operation.

Moreover, the present embodiment is characterized by the thickness of first base layer18. Specifically, as shown byFIG. 4, first base layer18includes contact portion18ain contact with potential fixing electrode36, and non-contact portion18bnot in contact with potential fixing electrode36. In addition, first base layer18includes contact portion18cin contact with source electrode32

Contact portion18ais a portion of first base layer18and has the same plan view shape as bottom part34aof electrode opening34. Thickness t2of contact portion18ais a distance from a bottom face of first base layer18(specifically, an interface between first base layer18and high-resistance layer16) to bottom part34a.

Contact portion18cis a portion of first base layer18and has the same plan view shape as bottom part30aof source opening30. Thickness t3of contact portion18cis a distance from the bottom face of first base layer18(specifically, the interface between first base layer18and high-resistance layer16) to bottom part30a.

Non-contact portion18bis a portion of first base layer18which is exclusive of contact portions18aand18c. For example, non-contact portion18bhas the same plan view shape as a contact face between first base layer18and second base layer20. Thickness t1of non-contact portion18bis a distance from the bottom face of first base layer18(specifically, the interface between first base layer18and high-resistance layer16) to the top face of first base layer18(specifically, the interface between first base layer18and second base layer20).

In the present embodiment, thickness t2is at least 50 percent of thickness t1. Moreover, thickness t1is at least 400 nm. Accordingly, thickness t2is at least 200 nm. Thickness t3is at least 50 percent of thickness t1. In the present embodiment, thickness t3is equal to thickness t2. At least one of thickness t2or thickness t3may be at least 70 percent, 80 percent, or 90 percent of thickness t1. It should be noted that thickness t1, thickness t2, and thickness t3may be equal to each other.

Each of bottom part34aof electrode opening34and bottom part30aof source opening30is damaged by dry etching when the opening is formed. In other words, a damage layer resulting from the dry etching is located in a surface part of each of contact portions18aand18cof first base layer18. The damage layer includes crystal defects etc. and causes leak current.

In the present embodiment, it is ensured that thickness t2of contact portion18aand thickness t3of contact portion18care at least 200 nm. This makes it possible to keep the damage layers located in the surface parts of contact portions18aand18caway from the parasitic p-n junction (high-resistance layer16located therewithin in the present embodiment). As a result, it is possible to suppress a decrease in breakdown voltage due to the damage layers.

Next, Variation 1 of Embodiment 1 will be described.

FIG. 5is a cross-sectional view of nitride semiconductor device10A according to the present variation. As shown byFIG. 5, nitride semiconductor device10A differs from nitride semiconductor device10according to Embodiment 1 in including potential fixing electrode36A instead of potential fixing electrode36.

As shown byFIG. 5, potential fixing electrode36A is formed using a material different from the material of potential fixing electrode36. Specifically, potential fixing electrode36A is formed using a material in Schottky contact with first base layer18. To put it another way, Ti/Al etc. can be used as a material in Schottky contact with a p-type semiconductor.

Consequently, potential fixing electrode36A and first base layer18form a Schottky barrier diode. The Schottky barrier diode is connected in series and in the reverse direction to the parasitic p-n diode (i.e., the anodes are connected to each other). Accordingly, a rise voltage of the parasitic p-n diode is high due to the reverse characteristics of the Schottky barrier diode, compared to when potential fixing electrode36and first base layer18are in ohmic contact. For this reason, it is possible to prevent current from flowing through the parasitic p-n diode, which makes it possible to suppress a decrease in breakdown voltage.

Next, Variation 2 of Embodiment 1 will be described.

FIG. 6is a cross-sectional view of nitride semiconductor device10B according to the present variation. As shown byFIG. 6, nitride semiconductor device10B differs from nitride semiconductor device10A according to Variation 1 in including threshold adjustment layer28.

As shown byFIG. 6, threshold adjustment layer28is an example of a second p-type nitride semiconductor layer provided between gate electrode38and electron supply layer26. Threshold adjustment layer28is in contact with the top face of electron supply layer26and a bottom face of gate electrode38.

Threshold adjustment layer28is, for example, a nitride semiconductor layer formed from p-type AlGaN with a thickness of 100 nm and a carrier concentration of 1×1017cm−3. Threshold adjustment layer28is formed through MOVPE and patterning, after the process of forming electron supply layer26.

According to the present variation, threshold adjustment layer28increases the potential at the end of the conducting band of the channel part. For this reason, it is possible to increase the threshold voltage of nitride semiconductor device10B. In other words, it is possible to allow nitride semiconductor device10B to operate as a normally-off FET.

It should be noted that threshold adjustment layer28need not be a p-type nitride semiconductor. For example, threshold adjustment layer28may be formed using an insulating material such as silicon nitride (SiN) or silicon oxide (SiO2). Stated differently, such a material is not particularly limited as long as the material has an effect of increasing a potential of a channel.

Embodiment 2 will be described next.

A nitride semiconductor device according to Embodiment 2 mainly differs from Embodiment 1 in including a second high-resistance layer above a first p-type nitride semiconductor layer. The following descriptions will focus on the differences from Embodiment1, and descriptions of common points will be omitted or simplified.

FIG. 7is a cross-sectional view of nitride semiconductor device100according to the present embodiment.FIG. 8is an enlarged partial cross-sectional view of the vicinity of potential fixing electrode36of nitride semiconductor device100according to the present embodiment.

As shown byFIG. 7, nitride semiconductor device100differs from nitride semiconductor device10according to Embodiment 1 in including high-resistance layer116. High-resistance layer116is an example of the second high-resistance layer provided above first base layer18. High-resistance layer116has a resistance higher than a resistance of first base layer18. Additionally, high-resistance layer116has the resistance higher than a resistance of second base layer20. High-resistance layer116is provided in contact with a top face of first base layer18and a bottom face of second base layer20. High-resistance layer116is 200 nm thick, for example.

As with high-resistance layer16, high-resistance layer116is a GaN layer containing carbon or an undoped GaN layer. Although high-resistance layer116has the same carbon concentration as high-resistance layer16, high-resistance layer116may have a carbon concentration different from a carbon concentration of high-resistance layer16. High-resistance layer116is formed using the same forming method as high-resistance layer16.

In the present embodiment, since high-resistance layer116is provided, gate opening22penetrates through second base layer20, high-resistance layer116, first base layer18, and high-resistance layer16to drift layer14. An end face of high-resistance layer116is part of side wall part22bof gate opening22. Additionally, source opening30and electrode opening34penetrate through electron supply layer26, electron transport layer24, second base layer20, and high-resistance layer116to first base layer18. An end face of high-resistance layer116is part of each of side wall part30bof source opening30and side wall part34bof electrode opening34.

If high-resistance layers16and116are not provided, second base layer20of n-type, first base layer18of p-type, and drift layer14of n-type form a parasitic bipolar transistor having a parasitic npn structure. When current flows through first base layer18in the case where nitride semiconductor device100is in an OFF-state, the parasitic bipolar transistor is switched ON, which may cause a decrease in breakdown voltage of nitride semiconductor device100. In this case, nitride semiconductor device100is more likely to malfunction.

Since high-resistance layer116is provided, it is possible to prevent this parasitic npn structure from being formed. Accordingly, it is possible to suppress a decrease in breakdown voltage of nitride semiconductor device100.

It should be noted that, also in the present embodiment, as shown byFIG. 8, first base layer18includes contact portions18aand18cand non-contact portion18b. Thickness t1of non-contact portion18b, thickness t2of contact portion18a, and thickness t3of contact portion18chave the same relationship as described in Embodiment 1. Here, non-contact portion18bhas the same shape in a plan view as a contact face between first base layer18and high-resistance layer116. Thickness t1of non-contact portion18bis a distance from the bottom face of first base layer18(specifically, the interface between first base layer18and high-resistance layer16) to the top face of first base layer18(specifically, an interface between first base layer18and high-resistance layer116).

Next, a variation of Embodiment 2 will be described.

FIG. 9is a cross-sectional view of nitride semiconductor device100A according to the present variation. As shown byFIG. 9, nitride semiconductor device100A differs from nitride semiconductor device100according to Embodiment 2 in including threshold adjustment layer28and including potential fixing electrode36A instead of potential fixing electrode36.

Threshold adjustment layer28is the same as described in Variation 2 of Embodiment 1. Since nitride semiconductor device100A includes threshold adjustment layer28, it is possible to allow nitride semiconductor device100A to operate as a normally-off FET.

Potential fixing electrode36A is the same as described in Variation 1 of Embodiment 1. Since potential fixing electrode36A and first base layer18form a Schottky barrier diode, it is possible to prevent current from flowing through a parasitic p-n diode, which makes it possible to suppress a decrease in breakdown voltage.

It should be noted that nitride semiconductor device100A need not include threshold adjustment layer28. Alternatively, nitride semiconductor device100A may include potential fixing electrode36instead of potential fixing electrode36A.

Embodiment 3 will be described next.

A nitride semiconductor device according to Embodiment 3 mainly differs from Embodiment 2 in not including the first high-resistance layer. The following descriptions will focus on the differences from Embodiment 2, and descriptions of common points will be omitted or simplified.

FIG. 10is a cross-sectional view of nitride semiconductor device200according to the present embodiment.FIG. 11is an enlarged partial cross-sectional view of the vicinity of potential fixing electrode36of nitride semiconductor device200according to the present embodiment.

As shown byFIG. 10, nitride semiconductor device200does not include high-resistance layer16shown byFIG. 7. As with Embodiments1and2, in the present embodiment, as shown byFIG. 11, first base layer18includes contact portions18aand18cand non-contact portion18b. Thickness t1of non-contact portion18b, thickness t2of contact portion18a, and thickness t3of contact portion18chave the same relationship as described in Embodiments 1 and 2. In other words, thickness t1is at least 400 nm, and thickness t2and thickness t3are at least 50 percent of thickness t1.

Here, thickness t1of non-contact portion18bis a distance from the bottom face of first base layer18(specifically, an interface between first base layer18and drift layer14) to the top face of first base layer18(specifically, the interface between first base layer18and high-resistance layer116). Moreover, thickness t2of contact portion18ais a distance from the bottom face of first base layer18(specifically, the interface between first base layer18and drift layer14) to bottom part34a. Thickness t3of contact portion18cis a distance from the bottom face of first base layer18(specifically, the interface between first base layer18and drift layer14) to bottom part30a.

This makes it possible to keep the damage layers located in the surface parts of contact portions18aand18caway from the parasitic p-n junction. As a result, it is possible to suppress a decrease in breakdown voltage due to the damage layers.

Next, a variation of Embodiment 3 will be described.

FIG. 12is a cross-sectional view of nitride semiconductor device200A according to the present variation. As shown byFIG. 12, nitride semiconductor device200A differs from nitride semiconductor device200according to Embodiment 3 in including threshold adjustment layer28and including potential fixing electrode36A instead of potential fixing electrode36.

Threshold adjustment layer28is the same as described in Variation 2 of Embodiment 1. Since nitride semiconductor device200A includes threshold adjustment layer28, it is possible to allow nitride semiconductor device200A to operate as a normally-off FET.

Potential fixing electrode36A is the same as described in Variation 1 of Embodiment 1. Since potential fixing electrode36A and first base layer18form a Schottky barrier diode, it is possible to prevent current from flowing through a parasitic p-n diode, which makes it possible to suppress a decrease in breakdown voltage.

It should be noted that nitride semiconductor device200A need not include threshold adjustment layer28. Alternatively, nitride semiconductor device200A may include potential fixing electrode36instead of potential fixing electrode36A.

Other Embodiments

Although one or more aspects of a nitride semiconductor device have been described thus far on the basis of embodiments, the present disclosure is not intended to be limited to these embodiments. Forms obtained by various modifications to each of the aforementioned embodiments that can be conceived by a person skilled in the art as well as other forms realized by combining elements in each of different embodiments are included in the scope of the present disclosure as long as they do not depart from the essence of the present disclosure.

For example, if a nitride semiconductor device includes potential fixing electrode36A, the nitride semiconductor device need not include high-resistance layer16. In addition, thickness t1of non-contact portion18bof first base layer18may be less than 400 nm. Alternatively, thickness t2of contact portion18amay be less than 50 percent of thickness t1.

Moreover, for example, when a nitride semiconductor device includes high-resistance layer16, thickness t1of non-contact portion18bof first base layer18may be less than 400 nm. Alternatively, thickness t2of contact portion18amay be less than 50 percent of thickness t1.

Furthermore, for example, substrate12need not be a nitride semiconductor substrate. For example, substrate12may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, a zinc oxide (ZnO) substrate, or the like.

Moreover, for example, first base layer18may be formed not through crystal growth but by implanting Mg ions into i-GaN. Additionally, in nitride semiconductor device200or200A to which high-resistance layer16is not provided, first base layer18may be an insulating layer formed by implanting Fe ions, not a p-type semiconductor layer

Furthermore, for example, the nitride semiconductor device according to each of the embodiments and variations need not include second base layer20.

Moreover, for example, the nitride semiconductor device according to each of the embodiments and variations need not include source opening30. In this regard, however, since source electrode32and two-dimensional electron gas25can be brought into direct contact with each other by providing source opening30, it is possible to reduce an ohmic contact resistance between source electrode32and the channel.

Furthermore, for example, source opening30and electrode opening34may be integrated into one opening. In other words, bottom part30aof source opening30and bottom part34aof electrode opening34may be connected and flush with each other. Source electrode32may be provided to cover a side wall part of the one opening, and potential fixing electrode36may be provided to cover at least part of a bottom part of the one opening. In addition, source electrode32and potential fixing electrode36may be in contact with each other. This makes it possible to easily fix a potential of potential fixing electrode36to a source potential.

It should be noted that potential fixing electrode36may be fixed to a potential different from the source potential.

Moreover, for example, a donor concentration need not be even in drift layer14. For example, a donor concentration may be low in a surface part of drift layer14, that is, the vicinity of an interface between drift layer14and high-resistance layer16or first base layer18.

Forms obtained by various modifications to the respective embodiments that can be conceived by a person skilled in the art as well as forms realized by combining elements and functions in the respective embodiments are included in the scope of the present disclosure as long as they do not depart from the essence of the present disclosure.

INDUSTRIAL APPLICABILITY

The present disclosure can be used as a nitride semiconductor device capable of suppressing a decrease in breakdown voltage due to a reverse conductive operation, and can be used, for example, as a power device used in power circuitry etc. of consumer devices.