Power gating in a memory device

Methods, systems, and devices for power gating in a memory device are described for using one or more memory cells as drivers for load circuits of a memory device. A group of memory cells of the memory device may represent memory cells that include a switching component and that omit a memory storage element. These memory cells may be coupled with respective plate lines that may be coupled with a voltage source having a first supply voltage. Each memory cell of the group may also be coupled with a respective digit line that may be coupled with the load circuits. Respective switching components of the group of memory cells may therefore act as drivers to apply the first supply voltage to one or more load circuits by coupling a digit line with a plate line having the first supply voltage.

FIELD OF TECHNOLOGY

The following relates generally to one or more systems for memory and more specifically to power gating in a memory device.

BACKGROUND

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., FeRAM, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state when disconnected from an external power source. FeRAM may be able to achieve densities similar to volatile memory but may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device.

DETAILED DESCRIPTION

A memory device may include multiple load circuits, and in some examples, one or more drivers for activating the load circuits. A load circuit may be configured to supply power (e.g., a voltage, a current) to one or more components of the memory device, such as a decoder, a sense component (e.g., a sense amplifier), or a generator, among other examples. A load circuit may be configured to receive a first supply voltage (e.g., a negative supply terminal voltage, a peripheral circuitry voltage) and apply a second supply voltage (e.g., a larger supply voltage relative to the first supply voltage) to the one or more components of the memory device. In some examples, the first supply voltage may be applied to a load circuit via a driver for the load circuit, where the driver may include a switching component (e.g., a transistor) for coupling the load circuit with a voltage source having the first supply voltage. Applying or restricting a voltage (e.g., the first supply voltage) to a circuit via a driver (e.g., a transistor) may be referred to herein as power gating, among other examples. In some examples, a driver for a load circuit may take up a relatively large amount of space compared to the load circuit. The space taken up by one or more drivers for the load circuits of the memory device may in some examples increase a size of the memory device, a cost of manufacturing the memory device, or both, among other disadvantages.

The present disclosure provides techniques for using one or more memory cells as one or more drivers for one or more load circuits. A first group of memory cells (e.g., one or more memory cells) of the memory device may be configured to store one or more logic states for memory storage (e.g., data storage). A second group of memory cells (e.g., one or more memory cells) of the memory device may include memory cells that include a switching component and that omit a storage component (e.g., a memory storage element). Memory cells of the second group may each be coupled with a respective plate line that may be coupled with a voltage source having the first supply voltage. Memory cells of the second group may also each be coupled with a respective digit line that may be coupled with one or more load circuits. As such, respective switching components of the second group of memory cells may act as a respective driver to couple the voltage source having the first supply voltage with one or more load circuits. For example, one or more switching components of the second group of memory cells may be activated to couple one or more load circuits with the voltage source (e.g., by coupling a digit line with a plate line). Advantageously when the second group of memory cells are used as one or more drivers for the load circuits of the memory device, other drivers may, in some examples, be omitted from the memory device. Doing so may save space in the memory device (e.g., decrease a device size, increase a device storage density) and may decrease production and other costs associated with the memory device, among other advantages.

Features of the disclosure are initially described in the context of systems and dies as described with reference toFIGS.1-2. Features of the disclosure are described in the context of a device architecture and circuit diagrams as described with reference toFIGS.3-4. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and flowcharts that relate to power gating in a memory device as described with reference toFIGS.5-6.

FIG.1illustrates an example of a system100that supports power gating in a memory device in accordance with examples as disclosed herein. The system100may include a host device105, a memory device110, and a plurality of channels115coupling the host device105with the memory device110. The system100may include one or more memory devices110, but aspects of the one or more memory devices110may be described in the context of a single memory device (e.g., memory device110).

At least portions of the system100may be examples of the host device105. The host device105may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or some other stationary or portable electronic device, among other examples. In some examples, the host device105may refer to the hardware, firmware, software, or a combination thereof that implements the functions of an external memory controller120. In some examples, the external memory controller120may be referred to as a host or a host device105.

The memory device110may be operable to store data for the components of the host device105. In some examples, the memory device110may act as a slave-type device to the host device105(e.g., responding to and executing commands provided by the host device105through the external memory controller120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

The host device105may include one or more of an external memory controller120, a processor125, a basic input/output system (BIOS) component130, or other components such as one or more peripheral components or one or more input/output controllers. The components of host device105may be coupled with one another using a bus135.

The memory device110may include a device memory controller155and one or more memory dies160(e.g., memory chips) to support a desired capacity or a specified capacity for data storage. Each memory die160may include a local memory controller165(e.g., local memory controller165-a, local memory controller165-b, local memory controller165-N) and a memory array170(e.g., memory array170-a, memory array170-b, memory array170-N). A memory array170may be a collection (e.g., one or more grids, one or more banks, one or more tiles, one or more sections) of memory cells, with each memory cell being operable to store at least one bit of data. In some examples, memory cells within an array may be grouped into two or more groups of memory cells, for example, where each group of memory cells may share one or more characteristics. A memory device110including two or more memory dies may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

The memory die160may be an example of a two-dimensional (2D) array of memory cells or may be an example of a three-dimensional (3D) array of memory cells. A 2D memory die160may include a single memory array170. A 3D memory die160may include two or more memory arrays170, which may be stacked on top of one another or positioned next to one another (e.g., relative to a substrate). In some examples, memory arrays170in a 3D memory die160may be referred to as decks, levels, layers, or dies. A 3D memory dies160may include any quantity of stacked memory arrays170(e.g., two high, three high, four high, five high, six high, seven high, eight high). In some 3D memory dies160, different decks may share at least one common access line such that some decks may share one or more of a word line, a digit line, or a plate line. In some examples, different layers or decks of 3D memory arrays may be processed in a similar manner to produce similar memory cells, and in some examples, different layers or decks may be processed in a different manner to produce different memory cells.

The device memory controller155may include circuits, logic, or components operable to control operation of the memory device110. The device memory controller155may include the hardware, the firmware, or the instructions that enable the memory device110to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device110. The device memory controller155may be operable to communicate with one or more of the external memory controller120, the one or more memory dies160, or the processor125. In some examples, the device memory controller155may control operation of the memory device110described herein in conjunction with the local memory controller165of the memory die160.

In some examples, the memory device110may receive data or commands or both from the host device105. For example, the memory device110may receive a write command indicating that the memory device110is to store data for the host device105or a read command indicating that the memory device110is to provide data stored in a memory die160to the host device105.

A memory cell may, in some examples, be configured and used as a driver for one or more load circuits of a memory device110. For example, a first group of memory cells (e.g., one or more memory cells) of the memory device110may be configured to store one or more logic states for memory storage (e.g., data storage). A second group of memory cells (e.g., one or more memory cells) of the memory device110may include memory cells that include a switching component and that omit a storage component. Memory cells of the second group may each be coupled with a respective access line (e.g., plate line) that may be coupled with a voltage source having a first supply voltage and may each be coupled with a respective second access line (e.g., digit line) that may be coupled with one or more load circuits. As such, respective switching components of the second group of memory cells may be configured to act as drivers to couple the voltage source having the first supply voltage with one or more load circuits. When the second group of memory cells are configured as one or more drivers for the load circuits of the memory device110, other drivers may, in some examples, be omitted from the memory device. Doing so may save space in the memory device110(e.g., decrease a device size, increase a device storage density) and may decrease production and other costs associated with the memory device110, among other advantages

FIG.2illustrates an example of a memory die200that supports power gating in a memory device in accordance with examples as disclosed herein. The memory die200may be an example of the memory dies160described with reference toFIG.1. In some examples, the memory die200may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die200may include one or more memory cells205that may each be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, a memory cell205may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, a memory cell205(e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, a logic 11). In some examples, the memory cells205may be arranged in an array, such as a memory array170described with reference toFIG.1.

A memory cell205may store a state (e.g., polarization state or dielectric charge) representative of the programmable states in a capacitor. In FeRAM architectures, the memory cell205may include a capacitor240that includes a ferroelectric material to store a charge and/or a polarization representative of the programmable state. The memory cell205may include a logic storage component, such as capacitor240, and a switching component245. The capacitor240may be an example of a ferroelectric capacitor. A first node of the capacitor240may be coupled with the switching component245and a second node of the capacitor240may be coupled with a plate line220. The switching component245may be an example of a transistor or any other type of switch device that selectively establishes or de-establishes electronic communication between two components.

The memory die200may include access lines (e.g., the word lines210, the digit lines215, and the plate lines220) arranged in a pattern, such as a grid-like pattern. An access line may be a conductive line coupled with a memory cell205and may be used to perform access operations on the memory cell205. In some examples, word lines210may be referred to as row lines. In some examples, digit lines215may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, bit lines, or plate lines, or their analogues, are interchangeable without loss of understanding or operation. Memory cells205may be positioned at intersections of the word lines210, the digit lines215, and/or the plate lines220.

Operations such as reading and writing may be performed on memory cells205by activating or selecting access lines such as a word line210, a digit line215, and/or a plate line220. By biasing a word line210, a digit line215, and a plate line220(e.g., applying a voltage to the word line210, digit line215, or plate line220), a single memory cell205may be accessed at their intersection. Activating or selecting a word line210, a digit line215, or a plate line220may include applying a voltage to the respective line.

Accessing the memory cells205may be controlled through a row decoder225, a column decoder230, and a plate driver235. For example, a row decoder225may receive a row address from the local memory controller265and activate a word line210based on the received row address. A column decoder230receives a column address from the local memory controller265and activates a digit line215based on the received column address. A plate driver235may receive a plate address from the local memory controller265and activates a plate line220based on the received plate address.

Selecting or deselecting the memory cell205may be accomplished by activating or deactivating the switching component245. The capacitor240may be in electronic communication with the digit line215using the switching component245. For example, the capacitor240may be isolated from digit line215when the switching component245is deactivated, and the capacitor240may be coupled with digit line215when the switching component245is activated.

A word line210may be a conductive line in electronic communication with a memory cell205that is used to perform access operations on the memory cell205. In some architectures, the word line210may be in electronic communication with a gate of a switching component245of a memory cell205and may be operable to control the switching component245of the memory cell. In some architectures, the word line210may be in electronic communication with a node of the capacitor of the memory cell205and the memory cell205may not include a switching component.

A digit line215may be a conductive line that connects the memory cell205with a sense component250. In some architectures, the memory cell205may be selectively coupled with the digit line215during portions of an access operation. For example, the word line210and the switching component245of the memory cell205may be operable to selectively couple and/or isolate the capacitor240of the memory cell205and the digit line215. In some architectures, the memory cell205may be in electronic communication (e.g., constant) with the digit line215.

A plate line220may be a conductive line in electronic communication with a memory cell205that is used to perform access operations on the memory cell205. The plate line220may be in electronic communication with a node (e.g., the cell bottom) of the capacitor240. The plate line220may cooperate with the digit line215to bias the capacitor240during access operation of the memory cell205.

The sense component250may determine a state (e.g., a polarization state or a charge) stored on the capacitor240of the memory cell205and determine a logic state of the memory cell205based on the detected state. The sense component250may include one or more sense amplifiers to amplify the signal output of the memory cell205. The sense component250may compare the signal received from the memory cell205across the digit line215to a reference255(e.g., a reference voltage). The detected logic state of the memory cell205may be provided as an output of the sense component250(e.g., to an input/output260), and may indicate the detected logic state to another component of a memory device110that includes the memory die200.

The local memory controller265may control the operation of memory cells205through the various components (e.g., row decoder225, column decoder230, plate driver235, and sense component250). The local memory controller265may be an example of the local memory controller165described with reference toFIG.1. In some examples, one or more of the row decoder225, column decoder230, and plate driver235, and sense component250may be co-located with the local memory controller265. The local memory controller265may be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller120associated with a host device105, another controller associated with the memory die200), translate the commands or the data (or both) into information that can be used by the memory die200, perform one or more operations on the memory die200, and communicate data from the memory die200to a host device105based on performing the one or more operations. The local memory controller265may generate row signals and column address signals to activate the target word line210, the target digit line215, and the target plate line220. The local memory controller265may also generate and control various voltages or currents used during the operation of the memory die200. In general, the amplitude, the shape, or the duration of an applied voltage or current discussed herein may be varied and may be different for the various operations discussed in operating the memory die200.

The local memory controller265may be operable to perform one or more access operations on one or more memory cells205of the memory die200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controller265in response to various access commands (e.g., from a host device105). The local memory controller265may be operable to perform other access operations not listed here or other operations related to the operating of the memory die200that are not directly related to accessing the memory cells205.

A memory cell205may, in some examples, be configured as and used as a driver for one or more load circuits associated with a memory die200(or a memory device). For example, a first group of memory cells205(e.g., one or more memory cells) of the memory device may be configured to store logic states for memory storage (e.g., data storage). A second group of memory cells205(e.g., one or more memory cells) of the memory device may represent memory cells that include a switching component245and that omit a storage component (e.g., a capacitor240). Memory cells205of the second group may be coupled (e.g., each be coupled) with a respective access line (e.g., plate line220) that may be coupled with a voltage source having a first supply voltage, and may be coupled (e.g., each be coupled) with a respective second access lien (e.g., digit line215) that may be coupled with one or more load circuits. As such, respective switching components245of the second group of memory cells205may act as drivers to couple the voltage source having the first supply voltage with one or more load circuits.

FIG.3illustrates an example of a device architecture300that supports power gating in a memory device in accordance with examples as disclosed herein. Device architecture300may show a structure of one or more memory arrays within a memory device, as described with reference toFIGS.1and2. For example, device architecture300may include multiple memory cells310, where the memory cells310may be included in one of two groups320of memory cells310within the memory device. Each memory cell may be associated with a respective plate line305and a respective digit line315, where the plate line305and the digit line315may be shared by multiple memory cells310in some examples. Each memory cell may include a switching component350(e.g., a transistor), which may be configured to be activated by a respective word line (e.g., coupled with a gate of the switching component350). The word line may activate the switching component350to couple the memory cell310with the digit line315. In the example illustrated herein, the digit lines315may be oriented to extend in and out of the page, for example, to other memory cells310of the memory device.

The memory device may include a metal oxide semiconductor (MOS) layer325(e.g., a complementary MOS (CMOS) layer, such as a planar CMOS). The MOS layer325may, in some examples, be located beneath the memory cells310(e.g., beneath a memory cell array, such as a 3D memory array) to reduce a chip area of the memory array. In some examples, the MOS layer325may extend beyond an area covered by the memory array, such as extending into an edge area or peripheral area of the memory device (e.g., of the chip). The peripheral area may be close to or adjacent to one or more pins or pads of the memory device, such as one or more DQ pins or CA pins. The memory array may not be located over (e.g., may not cover) the MOS layer325in the peripheral area, for example, based on performance of peripheral circuitry. For example, circuitry supporting the memory array (e.g., sense amplifiers, decoders, drivers) may block some routing for peripheral circuitry if the memory array is located in the peripheral area, which may result in reduced performance of the peripheral circuitry.

The MOS layer325may include multiple load circuits330, and in some examples, one or more drivers335for the load circuits330. A load circuit330may be configured to supply power (e.g., a voltage or a current) to one or more components of the memory device, such as a decoder, a sense amplifier (e.g., a sense component), or a generator, among other examples. A load circuit330may be configured to receive a first supply voltage (e.g., a negative supply terminal voltage or a peripheral circuitry voltage) and apply a second supply voltage (e.g., a larger supply voltage relative to the first supply voltage) to the one or more components of the memory device.

Each load circuit330may include multiple switching components350, which may be coupled with one another in a configuration to support receiving the first supply voltage and converting the first supply voltage to the second supply voltage. For example, the multiple switching components350may be arranged in a footer power gating scheme (e.g., to reduce standby current), where switching components350may be coupled in pairs of one p-type MOS (PMOS) switching component350(e.g., PMOS transistor) and one n-type MOS (NMOS) switching component350(e.g., NMOS transistor). In such configurations, a gate of each NMOS transistor and a gate of each respective PMOS transistor may be coupled together, and a drain (e.g., a first terminal) of each NMOS transistor may be coupled with a source (e.g., a second terminal) of each respective PMOS transistor. The sources of each NMOS transistor may be coupled together and may each be couplable with the first supply voltage (e.g., via a driver335), and the drains of each PMOS transistor may be coupled together and may be coupled with a different voltage (e.g., a peripheral component voltage).

In some examples, the first supply voltage may be applied to a load circuit330via a driver335for the load circuit330, where the driver335may include a switching component350(e.g., a transistor). For example, in a first mode such as a standby mode (e.g., when a load circuit330is unpowered), a driver335associated with the load circuit330may be inactive, which may limit or restrict leakage, current, or voltage application to the associated load circuit330. In such cases, the load circuits330may experience a voltage, such as a standby or inactive voltage (e.g., based on a configuration of the multiple switching components350). In a second mode, which is different than the first mode, such as an active mode (e.g., when a load circuit330is powered), a driver335associated with the load circuit330may be active, which may result in application of the first supply voltage to the associated load circuit330. In such cases, the standby or inactive voltage may be adjusted toward the first supply voltage using the driver335(e.g., by shorting the load circuit330with a voltage source having the first supply voltage), and may thereby be brought to a same voltage level as the first supply voltage.

In some implementations, a driver335for a load circuit330may take up a relatively large amount of space compared with the load circuit330. For example, the driver335may take up one fourth of the area of the load circuit330, which may represent 20 percent of a combined area of the load circuit330and driver335. The area taken up by the drivers335for the load circuits330may increase a size of the memory device, a cost of manufacturing the memory device, or both, among other disadvantages.

The present disclosure in contrast provides techniques for using one or more memory cells310as one or more drivers for one or more of the load circuits330. A first group320-aof memory cells310of the memory device may be configured to store logic states for memory storage (e.g., data storage). A second group320-bof memory cells310of the memory device may represent memory cells310that include a switching component350, without including a memory storage element (e.g., omitting a memory storage element). For example, the second group320-bof memory cells310may include memory cells310such as memory cell310-a, which may include switching component350-a(e.g., a thin film transistor (TFT)) and may omit a memory storage element. In some examples, the second group320-bmay include a smaller quantity of memory cells310than the first group320-a. Memory cells310of the second group320-bmay be coupled (e.g., may each be coupled) with a respective plate line305(e.g., plate line305-a) that may be coupled with a voltage source having the first supply voltage, such as via circuitry340(e.g., one or more first electrode lines). Memory cells310of the second group320-bmay also be coupled (e.g., may each be coupled) with a respective digit line315(e.g., digit line315-a) that may be coupled with one or more load circuits330, such as via circuitry345(e.g., one or more second electrode lines).

As such, respective switching components350of the second group320-bof memory cells310may act as a respective driver to couple the voltage source having the first supply voltage with one or more load circuits330. For example, one or more switching components350of the second group320-bof memory cells310may be activated to couple one or more load circuits330with the voltage source (e.g., by coupling a digit line315with a plate line305, and thereby coupling circuitry345with circuitry340). In some examples, one memory cell310may act as a driver for one load circuit330, or may act as a driver for multiple load circuits330(e.g., depending on a configuration of circuitry345). In some examples, multiple memory cells310may be activated concurrently (e.g., at least partially overlapping) to activate one load circuit330, or to activate multiple load circuits330. In some examples, a supply voltage (e.g., the first supply voltage or another supply voltage) may be applied to portions of one or more load circuits330, for example, without using a switching component350, such as using a direct connection via circuitry340.

When the second group320-bof memory cells310are configured as drivers for the load circuits330of the memory device, the drivers335of the MOS layer325that would otherwise be included may, in some examples, be omitted from the memory device. Doing so may save space in the memory device (e.g., decrease a device size or increase a device storage density) and may decrease production and other costs associated with the memory device, among other advantages.

In some examples, the second group320-bof memory cells310(e.g., at least some of the second group320-bof memory cells310or all of the second group320-bof memory cells310) may be included in a peripheral area of the memory device (e.g., above the MOS layer325). Doing so may minimize an effect on available memory storage at the memory device while failing to interfere with peripheral circuitry (e.g., because supporting circuitry may not be implemented for the second group of memory cells310, based on each of the second group of memory cells310omitting a memory storage element). In some examples, some of the second group320-bof memory cells310may be included in the peripheral area of the memory device and some of the second group320-bof memory cells310(e.g., a remainder of second group320-bof memory cells310) may be included in other areas of the memory device (e.g., a memory storage area, associated with the first group320-aof memory cells310). In some examples, the second group320-bof memory cells310may be included in a lower layer or deck of memory cells310within a 3D array of the memory device (e.g., some or all of a lower layer of memory cells310). In such cases, some or all of the first group320-aof memory cells310may be included in an upper layer or deck of memory cells310. In some examples, the lower deck or layer of memory cells310may include some memory cells310of the first group320-aand some memory cells310of the second group320-b. In some examples, the second group320-bof memory cells310may be included in multiple layers or decks of memory cells310(e.g., in a peripheral area).

When manufacturing the memory device, the second group320-bof memory cells310may be processed to remove associated memory storage elements. Additionally or alternatively, the second group320-bof memory cells310may be processed differently from other memory cells310, for example, such that the second group320-bof memory cells310may not have memory storage components included during any stage of the manufacturing process.

FIGS.4A,4B, and4Cillustrate examples of circuit diagrams401,402, and403that support power gating in a memory device in accordance with examples as disclosed herein. Circuit diagrams401,402, and403may each represent a respective example of a load circuit as described with reference toFIG.3. For example, different load circuit configurations illustrated by circuit diagrams401,402, and403may be used within a memory device based on, among other aspects, a type of TFT used for memory cells of a memory device (e.g., used for a switching component405of the memory cells). As described with reference toFIG.3, a group of memory cells of the memory device may be used as respective drivers (e.g., transistors) for respective load circuits, where the group of memory cells may each include a respective switching component405(e.g., a TFT) and may omit a respective storage component (e.g., memory storage element). The load circuits illustrated by circuit diagrams401,402, and403may include multiple switching components410, which may be configured, for example, to receive a first supply voltage via the driver and apply a second supply voltage to one or more components of the memory device.

In some examples, the switching components405of the group of memory cells may be configured as PMOS TFTs (e.g., during a manufacturing process). In such cases, the memory device may be configured with load circuits similar to the load circuit illustrated by circuit diagram401. In some examples, switching components405of a first subset of the group of memory cells may be configured as PMOS TFTs and the switching components405of a second subset of the group of memory cells may be configured as NMOS TFTs. In such cases, the memory device may be configured with load circuits similar to the load circuit illustrated by circuit diagram402. In some examples, the switching components405of the group of memory cells may be configured as NMOS TFTs. In such cases, the memory device may be configured with load circuits similar to the load circuit illustrated by circuit diagram403.

Circuit diagram401related toFIG.4Amay represent a power gating scheme that may be referred to as a header scheme. A switching component405-aof the group of memory cells may be configured and used as a driver for the load circuit represented by circuit diagram401, where switching component405-amay represent a PMOS TFT. In the example illustrated by circuit diagram401, the first supply voltage may be applied to a first terminal of switching component405-a(e.g., at node415-a), for example, via a plate line as described with reference toFIG.3. If switching component405-ais activated (e.g., via a word line) the first supply voltage may be applied to respective first terminals (e.g., drains) of a first set of switching components410-aof the load circuit (e.g., PMOS transistors). In the example illustrated by circuit diagram401, the first supply voltage may represent a voltage for peripheral circuitry of the memory device.

A third supply voltage may be applied (e.g., without the use of drivers, or in a standby state) to nodes415-band415-cof circuit diagram401, where the third supply voltage may represent a negative supply terminal voltage. As such, the third supply voltage may be applied to respective second terminals (e.g., sources) of a second set of switching components410-b(e.g., NMOS transistors). A second terminal (e.g., source) of each of the first set of switching components410-amay be coupled with a respective first terminal (e.g., drain) of a respective switching component410-b, and the first and second terminals that are coupled together may also be coupled with a respective gate of each of a following pair of switching components410-aand410-b(e.g., as illustrated inFIG.4A).

Accordingly, the load circuit illustrated by circuit diagram401may be configured to receive the first supply voltage via switching component405-aand apply the second supply voltage at a node415-dof the load circuit. Node415-dmay be coupled with one or more components of the memory device, for example, to apply the second supply voltage to the one or more components.

Circuit diagram402related toFIG.4Bmay represent a power gating scheme that may be referred to as a subthreshold current reduction circuit (SCRC) scheme. A switching component405-bof the first subset of the group of memory cells may be configured and used as a first driver for the load circuit represented by circuit diagram402, and a switching component405-cof the second subset of the group of memory cells may be configured and used as a second driver for the load circuit. Switching component405-bmay represent a PMOS TFT and switching component405-cmay represent an NMOS TFT. For example, a top deck of the group of memory cells may be configured as PMOS TFTs to produce the first subset of the group and a bottom deck of the group of memory cells may be configured as NMOS TFTs to produce the second subset of the group.

The first supply voltage may be applied to a first terminal of switching component405-b(e.g., at node415-e), for example, via a plate line as described with reference toFIG.3. In such cases, the first supply voltage may represent a voltage for peripheral circuitry of the memory device. If switching component405-bis activated (e.g., via a word line) the first supply voltage may be applied to respective first terminals (e.g., drains) of a first set of switching components410-cof the load circuit (e.g., PMOS transistors). A third supply voltage may be applied to a second terminal of switching component405-c(e.g., at node415-f), for example, via a second plate line. In such cases, the third supply voltage may represent a negative supply terminal voltage. If switching component405-cis activated (e.g., via a word line) the third supply voltage may be applied to respective second terminals (e.g., sources) of a second set of switching components410-dof the load circuit (e.g., NMOS transistors).

A third set of switching components410(e.g., PMOS transistors) alternating with the first set of switching components410-cmay be directly coupled with the first supply voltage, such as via node415-e(e.g., as illustrated inFIG.4B). Similarly, a fourth set of switching components410(e.g., NMOS transistors) alternating with the second set of switching components410-dmay be directly coupled with the third supply voltage, such as via node415-f(e.g., as illustrated inFIG.4B). The third supply voltage may also be applied (e.g., without the use of drivers, or in a standby state) to node415-gof circuit diagram402.

In some examples, the terms first supply voltage and third supply voltage may be used interchangeably, such that the voltage for peripheral circuitry may be referred to as the third supply voltage and the negative supply terminal voltage may be referred to as the first supply voltage. In such cases, the peripheral circuitry voltage (e.g., third supply voltage) may still be applied at node415-eand the negative supply terminal voltage (e.g., first supply voltage) may still be applied at node415-f.

A second terminal (e.g., source) of each of the PMOS switching components410(e.g., the first and third sets of switching components) may be coupled with a respective first terminal (e.g., drain) of a respective NMOS switching component410(e.g., the second and fourth sets of switching components), and the first and second terminals that are coupled together may also be coupled with a respective gate of each of a following pair of switching components410(e.g., as illustrated inFIG.4B). Accordingly, the load circuit illustrated by circuit diagram402may be configured to receive the first supply voltage via switching component405-b, receive the third supply voltage via switching component405-c, and apply the second supply voltage at a node415-hof the load circuit. Node415-hmay be coupled with one or more components of the memory device, for example, to apply the second supply voltage to the one or more components.

The load circuit illustrated by circuit diagram402may be configured, for example, to reduce a current associated with the second supply voltage or associated with the load circuit. The reduction in current may be based on one or more constraints associated with an array of memory cells that includes the group of memory cells. For example, a scheme similar to that illustrated by circuit diagram402may be configured and the current may be reduced based on an availability or an amount of CMOS, PMOS, or NMOS devices in the memory array.

Circuit diagram403related toFIG.4Cmay represent a power gating scheme that may also be referred to as an SCRC scheme. A switching component405-dof the group of memory cells may be configured and used as a first driver for the load circuit represented by circuit diagram403, and a switching component405-eof the group of memory cells may be configured and used as a second driver for the load circuit. Switching components405-dand405-emay represent NMOS TFTs, for example, based on processing all (e.g., a top deck and a bottom deck) of the group of memory cells as NMOS TFTs.

The first supply voltage may be applied to a first terminal of switching component405-d(e.g., at node415-i), for example, via a plate line as described with reference toFIG.3. The first supply voltage may represent a voltage for peripheral circuitry of the memory device. If switching component405-dis activated (e.g., via a word line) the first supply voltage may be applied to respective first terminals (e.g., drains) of a first set of switching components410-eof the load circuit (e.g., PMOS transistors). In some examples, a gate voltage of switching component405-dmay be overdriven (e.g., via the word line) in order to put circuit diagram403into effect and apply the first supply voltage. A third supply voltage may be applied to a second terminal of switching component405-e(e.g., at node415-j), for example, via a second plate line. The third supply voltage may represent a negative supply terminal voltage. If switching component405-eis activated (e.g., via a word line) the third supply voltage may be applied to respective second terminals (e.g., sources) of a second set of switching components410-fof the load circuit (e.g., NMOS transistors).

A third set of switching components410(e.g., PMOS transistors) alternating with the first set of switching components410-emay be directly coupled with the first supply voltage, such as via node415-i(e.g., as illustrated inFIG.4C). Similarly, a fourth set of switching components410(e.g., NMOS transistors) alternating with the second set of switching components410-fmay be directly coupled with the third supply voltage, such as via node415-j(e.g., as illustrated inFIG.4C). The third supply voltage may also be directly applied to node415-kof circuit diagram403.

In some examples, the terms first supply voltage and third supply voltage may be used interchangeably, such that the voltage for peripheral circuitry may be referred to as the third supply voltage and the negative supply terminal voltage may be referred to as the first supply voltage. In such cases, the peripheral circuitry voltage (e.g., third supply voltage) may still be applied at node415-iand the negative supply terminal voltage (e.g., first supply voltage) may still be applied at node415-j.

A second terminal (e.g., source) of each of the PMOS switching components410(e.g., the first and third sets of switching components) may be coupled with a respective first terminal (e.g., drain) of a respective NMOS switching component410(e.g., the second and fourth sets of switching components), and the first and second terminals that are coupled together may also be coupled with a respective gate of each of a following pair of switching components410(e.g., as illustrated inFIG.4C). Accordingly, the load circuit illustrated by circuit diagram403may be configured to receive the first supply voltage via switching component405-d, receive the third supply voltage via switching component405-e, and apply the second supply voltage at a node415-1of the load circuit. In some examples, node415-1may be coupled with one or more components of the memory device, for example, to apply the second supply voltage to the one or more components.

FIG.5shows a block diagram500of a memory device505that supports power gating in a memory device in accordance with examples as disclosed herein. The memory device505may be an example of aspects of a memory device as described with reference toFIGS.1-4. The memory device505may include a plate line component510, a driver activation component515, a load circuit access component520, a voltage supply component525, and a second driver activation component530. Each of these modules may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The plate line component510may apply a first supply voltage to a plate line of a memory device. In some examples, the first supply voltage includes a negative supply terminal voltage or a voltage for peripheral circuitry of the memory device.

The driver activation component515may activate a switching component to couple the plate line with a digit line, where activating the switching component applies the first supply voltage to the digit line.

The load circuit access component520may apply the first supply voltage to a load circuit including a set of switching components based on activating the switching component. In some examples, the set of switching components includes a first set of switching components each including a PMOS and a second set of switching components each including an NMOS, where a terminal of each of the second set of switching components is coupled with a first terminal of a respective switching component of the first set of switching components. In some examples, the switching component includes a PMOS TFT, and a terminal of the switching component is coupled with a second terminal of each of the first set of switching components.

The voltage supply component525may apply a second supply voltage to one or more components of the memory device using the load circuit based on applying the first supply voltage to the load circuit. In some examples, the one or more components include a sense amplifier, a generator, power circuitry, or any combination thereof.

The second driver activation component530may apply a third supply voltage to a second plate line of the memory device. In some examples, the second driver activation component530may activate a second switching component to couple the second plate line with a second digit line, where activating the second switching component applies the third supply voltage to the second digit line. In some examples, the second driver activation component530may apply the third supply voltage to the load circuit based on activating the second switching component, where applying the second supply voltage to the one or more components of the memory device is based on applying the third supply voltage to the load circuit.

In some examples, a terminal of the switching component is coupled with a respective second terminal of each of a first subset of the first set of switching components and a terminal of the second switching component is coupled with a respective second terminal of each of a second subset of the second set of switching components. In some examples, the second switching component includes an NMOS TFT and the switching component includes a PMOS TFT or an NMOS TFT.

FIG.6shows a flowchart illustrating a method or methods600that supports power gating in a memory device in accordance with aspects of the present disclosure. The operations of method600may be implemented by a memory device or its components as described herein. For example, the operations of method600may be performed by a memory device as described with reference toFIG.5. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, a memory device may perform aspects of the described functions using special-purpose hardware.

At605, the memory device may apply a first supply voltage to a plate line of a memory device. The operations of605may be performed according to the methods described herein. In some examples, aspects of the operations of605may be performed by a plate line component as described with reference toFIG.5.

At610, the memory device may activate a switching component to couple the plate line with a digit line, where activating the switching component applies the first supply voltage to the digit line. The operations of610may be performed according to the methods described herein. In some examples, aspects of the operations of610may be performed by a driver activation component as described with reference toFIG.5.

At615, the memory device may apply the first supply voltage to a load circuit including a set of switching components based on activating the switching component. The operations of615may be performed according to the methods described herein. In some examples, aspects of the operations of615may be performed by a load circuit access component as described with reference toFIG.5.

At620, the memory device may apply a second supply voltage to one or more components of the memory device using the load circuit based on applying the first supply voltage to the load circuit. The operations of620may be performed according to the methods described herein. In some examples, aspects of the operations of620may be performed by a voltage supply component as described with reference toFIG.5.

In some examples, an apparatus as described herein may perform a method or methods, such as the method600. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for applying a first supply voltage to a plate line of a memory device, activating a switching component to couple the plate line with a digit line, where activating the switching component applies the first supply voltage to the digit line, applying the first supply voltage to a load circuit including a set of switching components based on activating the switching component, and applying a second supply voltage to one or more components of the memory device using the load circuit based on applying the first supply voltage to the load circuit.

In some examples of the method600and the apparatus described herein, the set of switching components may include a first set of switching components each including a PMOS and a second set of switching components each including an NMOS, where a terminal of each of the second set of switching components may be coupled with a first terminal of a respective switching component of the first set of switching components.

In some examples of the method600and the apparatus described herein, the switching component includes a PMOS TFT, and a terminal of the switching component may be coupled with a second terminal of each of the first set of switching components. Some examples of the method600and the apparatus described herein may further include operations, features, means, or instructions for applying a third supply voltage to a second plate line of the memory device, activating a second switching component to couple the second plate line with a second digit line, where activating the second switching component applies the third supply voltage to the second digit line, and applying the third supply voltage to the load circuit based on activating the second switching component, where applying the second supply voltage to the one or more components of the memory device may be based on applying the third supply voltage to the load circuit.

In some examples of the method600and the apparatus described herein, a terminal of the switching component may be coupled with a respective second terminal of each of a first subset of the first set of switching components and a terminal of the second switching component may be coupled with a respective second terminal of each of a second subset of the second set of switching components. In some examples of the method600and the apparatus described herein, the second switching component includes an NMOS TFT and the switching component includes a PMOS TFT or an NMOS TFT.

In some examples of the method600and the apparatus described herein, the one or more components include a sense amplifier, a generator, power circuitry, or any combination thereof. In some examples of the method600and the apparatus described herein, the first supply voltage includes a negative supply terminal voltage or a voltage for peripheral circuitry of the memory device.

It should be noted that the methods described herein are possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

An apparatus is described. The apparatus may include a plate line coupled with a voltage source having a first supply voltage, a switching component coupled with the plate line and a digit line, the switching component configured to selectively couple the plate line with the digit line to apply the first supply voltage to the digit line, and a set of switching components coupled with the digit line, the set of switching components configured to apply a second supply voltage to one or more components of the apparatus based on the first supply voltage being applied to the digit line.

Some examples of the apparatus may include a first group of memory cells each including a respective switching component and omitting a respective memory storage element, one of the first group of memory cells including the switching component, and a second group of memory cells each including a respective switching component and a respective memory storage element. In some examples, the first group of memory cells may be located at a first layer of the apparatus and the second group of memory cells may be located at a second layer of the apparatus. In some examples, the first group of memory cells may be located at a peripheral area of the apparatus.

Some examples of the apparatus may include one or more second digit lines each coupled with the digit line, and one or more second switching components each coupled with the plate line and with a respective second digit line, each second switching component configured to selectively couple the plate line with the respective second digit line to apply the first supply voltage to the respective second digit line.

In some examples, the set of switching components may include a first set of switching components each including a respective PMOS and a second set of switching components each including a respective NMOS, where a terminal of each of the second set of switching components may be coupled with a first terminal of a respective switching component of the first set of switching components. In some examples, the switching component includes a PMOS TFT, and a terminal of the switching component may be coupled with a second terminal of each of the first set of switching components. Some examples of the apparatus may include a second plate line coupled with a second voltage source having a third supply voltage, and a second switching component coupled with the second plate line and a second digit line, the second switching component including an NMOS TFT and configured to selectively couple the second plate line with the second digit line to apply the third supply voltage to the second digit line.

In some examples, the switching component includes a PMOS TFT, and a terminal of the switching component may be coupled with a second terminal of each of a first subset of the first set of switching components and a terminal of the second switching component may be coupled with a second terminal of each of a second subset of the second set of switching components. In some examples, the switching component includes an NMOS TFT, and a terminal of the switching component may be coupled with a second terminal of each of a first subset of the first set of switching components and a terminal of the second switching component may be coupled with a second terminal of each of a second subset of the second set of switching components.

Some examples of the apparatus may include a sense amplifier, a generator, and power circuitry, where the one or more components include the sense amplifier, the generator, the power circuitry, or any combination thereof. In some examples, the first supply voltage includes a negative supply terminal voltage or a voltage for peripheral circuitry of the apparatus. In some examples, the set of switching components includes one or more load circuits located at a MOS layer of the apparatus.

An apparatus is described. The apparatus may include a plate line, a digit line coupled with a load circuit including a set of switching components, a switching component coupled with the plate line and the digit line, the switching component configured to selectively couple the plate line with the digit line, and a controller coupled with the switching component and operable to cause the apparatus to apply a first supply voltage to the plate line, activate the switching component to apply the first supply voltage to the digit line, and apply a second supply voltage to one or more components of the apparatus based on activating the switching component.

Some examples of the apparatus may include a first group of memory cells each including a respective switching component and omitting a respective memory storage element, the first group of memory cells including the switching component, and a second group of memory cells each including a respective switching component and a respective memory storage element. Some examples of the controller may further be operable to apply the first supply voltage to the load circuit based on applying the first supply voltage to the digit line, where applying the second supply voltage to the one or more components may be based on applying the first supply voltage to the load circuit.

In some examples, the set of switching components may include a first set of switching components each including a respective PMOS and a second set of switching components each including a respective NMOS, where a terminal of each of the second set of switching components may be coupled with a first terminal of a respective switching component of the first set of switching components. In some examples, the switching component includes a PMOS TFT, and a terminal of the switching component may be coupled with a respective second terminal of each of the first set of switching components.

Some examples of the controller may further be operable to apply a third supply voltage to a second plate line of the memory device, activate a second switching component to couple the second plate line with a second digit line, where activating the second switching component applies the third supply voltage to the second digit line, and apply the third supply voltage to the load circuit based on activating the second switching component, where applying the second supply voltage to the one or more components of the memory device may be based on applying the third supply voltage to the load circuit. In some examples, a terminal of the switching component may be coupled with a respective second terminal of each of a first subset of the first set of switching components and a terminal of the second switching component may be coupled with a respective second terminal of each of a second subset of the second set of switching components.

In some examples, the second switching component includes an NMOS TFT and the switching component includes a PMOS TFT or an NMOS TFT. In some examples, the one or more components include a sense amplifier, a generator, power circuitry, or any combination thereof. In some examples, the first supply voltage includes a negative supply terminal voltage or a voltage for peripheral circuitry of the memory device.

An apparatus is described. The apparatus may include a set of first plate lines coupled with a first supply voltage, a set of first digit lines each coupled with a respective load circuit including a set of switching components, a set of first switching components each coupled with a respective plate line of the first plate lines and a respective digit line of the first digit lines and configured to selectively couple the respective plate line and the respective digit line to apply the first supply voltage to the respective digit line, where each load circuit is configured to apply a second supply voltage to one or more components of the apparatus based on the first supply voltage being applied to a corresponding digit line, a set of second plate lines each coupled with a first driver circuit for driving the respective second plate line to a plate voltage, a set of second digit lines each selectively couplable with a read circuit for reading a logic value stored at a memory cell, and a set of memory cells each coupled with a respective plate line of the second plate lines, each including a memory storage element and a second switching component, each second switching component configured to selectively couple a corresponding memory cell with a respective digit line of the second digit lines.

Some examples of the apparatus may include a set of second memory cells corresponding to the set of first plate lines and set of first digit lines, the set of second memory cells including the set of first switching components and each second memory cell of the set excluding a respective memory storage element. In some examples, the set of memory cells may be located at a first layer of the apparatus and the set of second memory cells may be located at a second layer of the apparatus. In some examples, the set of second memory cells may be located at a peripheral area of the apparatus. Some examples of the apparatus may include one or more electrode lines coupled with each of a subset of the set of digit lines, where each digit line of the subset may be coupled the other digit lines of the subset via the one or more electrode lines.

The term “layer” or “level” used herein refers to a stratum or sheet of a geometrical structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers or levels may include different elements, components, and/or materials. In some examples, one layer or level may be composed of two or more sublayers or sublevels.