IMAGE SENSOR DIAGONAL ISOLATION STRUCTURES

Image sensors, isolation structures, and techniques of fabrication are provided. An image sensor includes a source of electromagnetic radiation disposed on a substrate, a pixel array disposed on the substrate and thermally coupled with source of electromagnetic radiation, and an isolation structure disposed on the substrate between the source of electromagnetic radiation and the pixel array. The isolation structure can define a first reflective surface oriented on a first bias relative to a lateral axis of the pixel array and a second reflective surface oriented on a second bias relative to the lateral axis. The isolation structure can be configured to attenuate residual electromagnetic radiation reaching a proximal region of the pixel array by pairing a first reflection and a second reflection of the electromagnetic radiation by the first reflective surface and the second reflective surface.

TECHNICAL FIELD

This disclosure relates generally to image sensors, and in particular but not exclusively, relates CMOS image sensors and applications thereof.

BACKGROUND INFORMATION

Image sensors are widely found in digital cameras, cellular phones, security cameras, and other imaging systems as used in medical, automobile, and other applications. As image sensors are integrated into a broader range of electronic devices it is desirable to enhance their functionality and performance (e.g., resolution, power consumption, dynamic range, etc.) with improvements to device architecture design and image processing.

The typical image sensor operates in response to image light reflected from an external scene that is incident upon the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge upon absorption of the image light. The image charge photogenerated by the pixels can be measured as an analog output image signals on column bitlines that vary as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as analog image signals from the column bitlines and converted to digital values to produce digital images (i.e., image data) representing the external scene.

DETAILED DESCRIPTION

Reference throughout this specification to “one example” or “one embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one example” or “one embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in a suitable manner in one or more embodiments.

Spatially relative terms, such as “beneath,” “below,” “over,” “under,” “above,” “upper,” “top,” “bottom,” “left,” “right,” “center,” “middle,” and the like, can be used herein for ease of description to describe one element or feature's relationship relative to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is rotated or turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated ninety degrees or at other orientations) and the spatially relative descriptors used herein are interpreted accordingly. In addition, it will also be understood that when an element is referred to as being “between” two other elements, it can be the only element between the two other elements, or one or more intervening elements can also be present.

Advancements in semiconductor processing techniques have enabled the fabrication of complementary metal oxide semiconductor devices (e.g. image sensors, processors, displays, and the like) with increasingly smaller feature sizes, which has enabled miniaturization of many devices. For image sensors, miniaturization has produced devices in which image sensor components including photodiodes and metallization layers are formed on a shared substrate with signal processing and control circuitry, such as application specific integrated circuits (ASICs) and power circuits. Among the benefits of miniaturization are the reduction in power demand for image sensors, a reduction in overall sensor area, and an increase in pixel density. That being said, control and power circuitry generate heat that is transported through the shared substrate and induces dark current nonuniformity in image sensor pixel arrays. As a result, conventional approaches for correcting for dark current lose effectiveness with increasing miniaturization. There is a need, therefore, for techniques to attenuate electromagnetic radiation that is laterally transported in semiconductor substrates before it reaches photodiodes to nonuniformly induce dark current.

Embodiments described herein include an image sensor configured to attenuate electromagnetic radiation transported laterally through a semiconductor substrate of the image sensor. The image sensor includes diagonal isolation structures formed between pixels of the image sensor pixel array, which can include active pixels, dark pixels, and/or dummy pixels. The diagonal isolation structure can include a triangular sawtooth pattern (e.g., a triangular “zig-zag”) describing a substantially linear axis, with the axis oriented substantially orthogonal to a lateral axis of the image sensor (e.g., axis A-A′ ofFIG.1A). Alternatively, the diagonal isolation structure can include a rotated square lattice, rotated rectangular lattice, rotated rhomboid lattice, or other geometric lattice. Advantageously, diagonal isolation structures described herein can be formed by processes already implemented by CMOS manufacturing systems, including but not limited to photolithographic patterning, deposition and etch, and planarization. Additionally, diagonal isolation structures described herein reflect EM radiation including thermal energy away from pixels of the image sensor more effectively than conventional isolation structures, such as deep-trench isolation structures that are formed to reduce optical cross talk between photodiodes, which typically assume a square lattice configuration that is aligned with the vertical and lateral alignments of the image sensor.

FIG.1Ais a schematic diagram illustrating a plan view of an example image sensor100including an active pixel region110, a dark pixel region130, and a diagonal deep trench isolation structure109, in accordance with the embodiments of the present disclosure. Image sensor100includes active pixel region110, dummy pixel region120, dark pixel region130, peripheral region140, one or more application specific integrated circuits (ASIC)190, of which one or more components can act as sources of electromagnetic (EM) radiation195. In the illustrated embodiment, dummy pixel region120, dark pixel region130, and peripheral region140laterally surround active pixel region110. Dummy pixel region120is disposed between active pixel region110and dark pixel region130. Dark pixel region130is disposed between peripheral region140and dummy pixel region120. Dark pixel region130is also disposed between peripheral region140and active pixel region110. ASIC(s)190and EM Source(s)195are illustrated within the peripheral region140.

Active pixel region110includes one or more active pixel photodiodes112(in reference toFIG.1B) to generate one or more image signals representative of an external scene. For example, in response to incident light (e.g., electromagnetic (EM) radiation having an energy that is detectable by human eyes, EM radiation that is invisible to human eyes, etc.) on active pixel region110, image charge can be collected by active pixel photodiodes112of active pixel region110. The image charge can be read out as an analog signal that is converted to a digital signal (e.g., an image signal for a given one or more pixels included in active pixel region110). Dark pixel region130includes dark pixel photodiodes132(in reference toFIG.1B) to generate one or more dark current reference signals (e.g., based on a readout of one or more dark pixel photodiodes included in the dark pixel region130). Dark current reference signals can be generated by dark pixel photodiodes132to correct for noise output from active pixel photodiodes112. For example, dark current can result in an elevated baseline in image signals and can reduce the signal to noise ratio of image sensor100, impairing sensor performance. Dark current correction can include, but is not limited to, baseline correction and/or denoising techniques, such as subtracting dark current reference signals from the one or more image signals.

In some embodiments, a dummy pixel region120can be included between dark pixel region130and active pixel region110. Dummy pixel region120can include multiple dummy pixel photodiodes122(in reference toFIG.1B), which can correspond to non-imaging photodiodes. For example, dummy pixel region120can be disposed between active pixel region110to isolate active pixel photodiodes112from dark pixel region130, ASIC190, EM Source195, other circuitry or logic not illustrated that can be disposed within peripheral region140, or other components of the image sensor100.

Dummy pixel region120and dark pixel region130are illustrated inFIG.1Aas being substantially concentric with active pixel region110. In some embodiments, dummy pixel region120and dark pixel region130can adopt different configurations including but not limited to an open loop shape, a rectangular shape, a circular shape, or otherwise, as described in more detail in reference toFIG.3A. For example, dark pixel region130can partially surround active pixel region110and can define one more gaps to provide additional area for forming circuitry or other components (e.g., ASIC190). Dark pixel region130can have a rectangular shape that is aligned with a row or a column of active pixel photodiodes included in the active pixel region110. In some embodiments, the plurality of active pixel photodiodes included in the active pixel region110are arranged (e.g., in rows and columns) such that the active pixel region110has a square or rectangular shape. However, in other embodiments, the active pixel region110can have a different shape (e.g., a circular shape, a hexagonal shape, or another shape).

FIG.1Billustrates a cross-sectional view100-AA′ of the image sensor100illustrated inFIG.1Aalong line A-A′, in accordance with the embodiments of the present disclosure. Image sensor100includes active pixel region110, dummy pixel region120, dark pixel region130, and peripheral region140. Image sensor100further includes a semiconductor material101(e.g., silicon, a silicon germanium alloy, germanium, a silicon carbide alloy, an indium gallium arsenide alloy, other alloys formed of III-V compounds, other semiconductor materials or alloys, combinations thereof, a substrate thereof, a bulk substrate thereof, or a wafer thereof) with a first side103(e.g., a backside) and a second side105(e.g., a frontside), metal layers107, isolation structures108, diagonal trench structure(s)109, active pixel photodiodes112(e.g., a first active pixel photodiode112-1and a second active pixel photodiode112-2), dummy pixel photodiodes122(e.g., a first dummy pixel photodiode122-1), dark pixel photodiodes132(e.g., a first dark pixel photodiode132-1and a second dark pixel photodiode132-2), an anti-reflective (AR) layer150, a buffer oxide layer152, and one or more opaque and layers154and156to isolate and define active pixels112, dark pixels132, a buffer layer172(e.g., a ceramic or other oxide), color filters174(e.g., a green color filter174-G, a red color filter174-R, or other color filter), and micro-lenses176.

For active pixel region110, opaque layers154and156can form a stack to block or otherwise attenuate EM radiation incident upon the dark pixel region130(e.g., to block EM radiation from reaching the plurality of dark pixel photodiodes132). Similarly, color filters174can be formed by patterned removal of portions of opaque layers154and156and subsequent deposition of color filter174material. In this way, opaque layers154and156serve to reduce crosstalk between neighboring photodiodes112of active pixel region110, which is supported by the deposition of isolation structures108, described in more detail below.

In one or more embodiments, first side103can be referred to as an illuminated surface or side of semiconductor material101and second side105can be referred to as a non-illuminated surface or side of semiconductor material101. AR layer150can be disposed between first side103of the semiconductor material101and buffer oxide layer152. In some embodiments, anti-reflective layer150includes tantalum oxide (e.g., Ta2O5), hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), zirconium oxide (e.g., Zr2O3), or combinations thereof. Anti-reflective layer150can be about 10 nm thick, about 20 nm thick, about 30 nm thick, about 40 nm thick, about 50 nm thick, about 60 nm thick, about 70 nm thick, about 80 nm thick, about 90 nm thick, about 100 nm thick, about 110 nm thick, about 120 nm thick, about 130 nm thick, about 140 nm thick, about 150 nm thick, or thicker, including fractions and interpolations thereof. Buffer oxide layer152can be disposed between anti-reflective layer150and opaque layers154and156. In some embodiments, buffer oxide layer152includes a dielectric oxide (e.g., SiO2) and is at least 100 nm thick. In some embodiments, buffer oxide layer152has a thickness between 100 nm to 130 nm. Buffer oxide layer152can be disposed overlying AR layer150and underlying color filters174. As such, buffer oxide layer152can be planarized to a substantially uniform surface to improve consistency between different active pixels110. Buffer oxide layer152can impart improved structural integrity and chemical and/or radiation protection to underlying layers (e.g., the anti-reflective layer150, the semiconductor material101, etc.). For example, buffer oxide layer152can be disposed at a thickness to reinforce mechanical strength under chemical mechanical polishing (CMP) processes used for planarization and mitigate mechanical stress and other damage to anti-reflective layer150, semiconductor material101, etc.

In some embodiments, the semiconductor material101includes one or more layers disposed underneath buffer oxide layer152(e.g., between buffer oxide layer152and first side103of semiconductor substrate101). For example, a surface passivation layer can be disposed between AR layer152and first side103of semiconductor material101. Surface passivation layer can be formed of high-κ material (e.g., a material having a dielectric constant greater than the dielectric constant of silicon oxide) that provides a fixed negative charge (e.g., hafnium oxide, aluminum oxide, or other passivating oxide) to provide surface passivation of first side103of the semiconductor material. In this context, surface passivation describes a technique to reduce the impact of charge accumulation in photoelectric materials that can impair sensor operation and can lead to dielectric breakdown in some cases.

In active pixel region110, dummy pixel region120, and dark pixel region130, Isolation structures108(e.g., deep trench isolation structures formed of at least an oxide material) are arranged to electrically and optically isolate individual photodiodes (e.g., active pixel photodiodes112, dummy pixel photodiodes122, and/or dark pixel photodiodes132). Isolation structures108can extend from first side103of the semiconductor material101at least a portion of a distance between from first side103toward second side105. In some embodiments, isolation structures108can be formed by deposition and removal operations, including but not limited to patterned reactive ion etching of semiconductor material101, followed by depositing fill material (e.g., an oxide material, a low-n material, a different dielectric material, or combinations thereof) into trenches formed in semiconductor material101.

In some embodiments, isolation structures108can be formed by patterned removal of semiconductor substrate material and subsequent deposition of one or more dielectric materials. In some embodiments, deposition can also include a metal material that can be included as a surface film (e.g., by prior deposition of metal material), as a ceramic-metal mixture (e.g., by concurrent deposition of metal and oxide materials), or as a metal fill material deposited on a dielectric base layer (e.g., by prior deposition of dielectric materials). In some embodiments, isolation structure108(see, e.g., isolation structure108-O) is formed from anti-reflective layer150, buffer oxide layer152, and can include material layers between anti-reflective layer150and buffer oxide layer152. In this way, anti-reflective layer150, buffer oxide layer152, and material layers if included (e.g., diffusion barriers, optical absorber materials, etc.) can at least partially line isolation structures108.

It is appreciated that in some embodiments at least one isolation structure108in active pixel region110, dummy pixel region120, and/or dark pixel region130can be configured as isolation structure108-O. In some embodiments a surface passivation layer is disposed between anti-reflective layer150and buffer oxide layer152to induce a hole accumulation region in the vicinity of buffer oxide layer152. In this way, the surface passivation layer passivates surface defects and trench sidewall defects that can occur during fabrication that would otherwise impair the functioning of pixel photodiodes112and/or132.

In some embodiments, buffer layer172is disposed between micro-lenses176and opaque layer(s)154and/or156. In some embodiments, buffer layer172is a transparent (e.g., transparent to photons having a characteristic energy of incident visible and/or invisible light) dielectric layer including an oxide-based material (e.g., SiO2) or a low-n material with a refractive index less than a corresponding refractive index of the semiconductor material101, color filters174, and/or micro-lenses176. In some embodiments, at least a portion of buffer layer172has a thickness greater than 100 nm (e.g., 110 nm, 125 nm, 150 nm).

Peripheral region140can host electronic and optical components included as part of image sensor100, including but not limited to diagonal isolation structure(s)109, ASIC(s)190, and/or EM radiation source(s)195. As previously described in reference toFIG.1A, EM radiation source(s)195can include components or elements of ASIC(s)190that generate EM radiation, such as visible photons and/or thermal energy, that can induce a non-uniform dark current in dark pixel region130and/or active pixel region110. In some embodiments, EM radiation source(s)190include power circuit elements that are configured to convert supply power (e.g., from a battery) to input power for ASIC(s)190. For example, a power circuit can include a voltage stepper circuit to increase the input voltage from a battery supply voltage by several orders of magnitude.

FIGS.2A and2Bare schematic diagrams illustrating conventional isolation structures as typically employed to reduce lateral transmission of electromagnetic radiation to active pixels of the active pixel region.FIG.2Arepresents a simplified cross-sectional diagram corresponding to the section illustrated inFIG.1B, with components removed to simplify the visual explanations. As such,FIG.2Aomits photo-electric components, such as photodiodes, as well as polarization filters, color filters, micro-lenses, overlying layers, and other components, in order to focus description on the interaction of isolation structures with electromagnetic radiation transported through the substrate of an image sensor.

Isolation structures illustrated inFIG.2Arepresent conventional rectangular lattice isolation structures in the active pixel region, the dummy pixel region, and/or the dark pixel regions of a conventional image sensor for which an EM radiation source is included in or on the substrate as part of a miniaturized sensor device. The EM radiation source can be or include a power circuit or other electronic element that generates heat during operation. As such, EM radiation205is illustrated being transported through the substrate from the EM radiation source toward the dark pixel region and/or the dummy pixel region. Isolation structures, as described in more detail in reference toFIG.1B, are formed to limit crosstalk between pixels by reflecting and/or absorbing incident photons received through the first side of the image sensor. As such, isolation structures shown inFIG.2AandFIG.2Btypically include sidewalls with sidewall angles approaching a vertical angle normal to the first side. It is noted that the sidewall angle inFIG.2Ais not to scale, being emphasized to illustrate the characteristic tapered shape of isolation structures. In this way, at least a portion of EM radiation205generated by the EM radiation source that is transported through the substrate will interact with isolation structures at a substantially normal angle of incidence to the sidewalls of the isolation structures. As would be understood by a person of ordinary skill in the optical arts, EM radiation, including but not limited to photons, can be transmitted through a material interface or reflected from the material interface based at least in part on the ratio of the indexes of refraction of the materials forming the interface and on the angle of incidence relative to the surface normal of the reflecting surface. Typically, the proportion of photons reflected at an interface increases with an increasing incidence angle relative the surface normal (e.g., where the surface normal defines a zero-angle condition).

For a source of EM radiation205disposed in the peripheral region, a predictable fraction of EM radiation205will transit through a number of isolation structures, allowing residual EM radiation210to reach active pixels, which can include dark pixels and/or active pixels. In some cases photodiodes can detect residual EM radiation210, which can increase the dark current signal in a portion of active pixels in a nonuniform way. Such a non-uniform effect can significantly impair the performance of an image sensor by affecting pixels nearer to the EM radiation source differently than pixels farther from the EM radiation source. As dark current is used to correct image data, nonuniformities in dark current over active pixel region110can significantly impair image quality.

Even were isolation structures to be disposed between dark pixels and/or active pixels and the EM radiation source, as described in reference to embodiments of the present disclosure illustrated inFIGS.1A-1BandFIGS.3A-3C, residual EM radiation210would transmit through the rectangular regular isolation structure (e.g., a lattice of cells formed by isolation structure material), much less a single isolation structure with substantially vertical or narrowly tapered sidewalls. Permitting residual EM radiation210to reach active pixels, understandably, impairs sensor accuracy and performance by affecting dark current nonuniformly in an affected region of active pixel, before residual EM radiation210is attenuated to a level that induces negligible or no dark current in photodiodes of the affected region.

FIG.2Bis a schematic diagram illustrating an overhead-plan view of a rectangular lattice isolation structure and the interaction of EM radiation205with surfaces of the isolation structure. The view illustrated inFIG.2Brepresents a view from a surface of a conventional image sensor that is analogous to first surface103or second surface105. As inFIG.2A, components of a conventional image sensor are omitted to focus description on the interaction of EM radiation205with the isolation structure. As such, overlying layers, underlying layers, and interstitial materials and structures are omitted from the schematic diagram ofFIG.2B, but it is understood to describe isolation structures formed in a semiconductor substrate by CMOS-compatible fabrication processes, such as patterned etch and deposition of fill materials, as described in more detail in reference toFIG.1B.

As inFIG.2A, the EM radiation source generates EM radiation205that is transported through the semiconductor substrate toward the isolation structure. As an illustrative example, the EM radiation source is shown as an isotropic heat source (e.g., a point source) generating EM radiation205(e.g., where the EM radiation source is a heat source, as in the case where EM radiation source is a power circuit or other electronic component that emits infrared photons). In this case, EM radiation205can be transported through the substrate in a linear direction toward the isolation structure and can interact with the isolation structure in accordance with physical principles of optics, such as partial refraction and partial reflection in a manner dependent at least in part on the index of refraction of the substrate, the index of refraction of the isolation structure, and the angle of incidence of the EM radiation205.

As illustrated, EM radiation incident on a surface of the isolation structure that is aligned orthogonal to the EM radiation source will approach the surface at a low angle of incidence (where 90 degrees corresponds to the surface and zero degrees corresponds to the surface normal). In such a condition, a proportion of transmitted light will be significant and can exceed a proportion of reflected light, where the index of refraction of the material of the isolation structure is lower than the index of refraction of the material of the semiconductor substrate. Further, EM radiation205that interacts with lateral surfaces of the isolation structure will exhibit a low angle of incidence, such that reflection becomes favored when the isolation structure has a relatively low index of refraction.

For miniature CMOS image sensors, the characteristic distances between EM radiation source(s) and isolation structures can be on the order of micrometers or even nanometers. As such, formation of hot pixels, characterized by an elevated dark current, or of one or more regions of hot pixels with nonuniform dark current between the region(s) and the remaining active pixels is more likely in the proximity of EM radiation source than distant from the EM radiation source. Understandably, the impact of residual EM radiation210reaching active pixels includes impairing the signal-to-noise ratio of the affected pixels, impairing image processing (e.g., dark current correction) by affecting pixel dark current in a nonuniform and unsteady way, owing at least in part to dynamics in heat generation as the image sensor draws greater or lesser power through the EM radiation source.

FIG.3Ais a schematic diagram illustrating an example image sensor300layout including diagonal isolation structure109configured to improve isolation of active pixels110, in accordance with embodiments of the present disclosure. Example image sensor300includes components described in reference toFIG.1A. For example, example image sensor300includes an ASIC190, which can be configured to be disposed in peripheral region140of example image sensor300at least partially surrounding active pixel region110and dark pixel region130. In the forthcoming description, pixels of active pixel region110are referred to as active pixels110and pixels of dark pixel region130are referred to as dark pixels130.

As described in more detail in reference toFIG.1A, example image sensor300can include a power circuit310that includes one or more EM radiation sources195, including but not limited to sources of infrared radiation or other radiation that can induce an elevated dark current in active pixels110. Disposed between active pixels110and power circuit310, one or more diagonal isolation structures109can be configured to reduce the flux of residual EM radiation210(in reference toFIGS.2A-2B) that reaches a proximal region315of active pixels110relative to the conventional image sensor described in reference toFIGS.2A-2B.

In an illustrative example, EM radiation source(s)195can include a resistive element that exhibits ohmic heating, a voltage conversion element of power circuit310configured to step up a voltage from a supply voltage (e.g., from a battery) to an input voltage for ASIC190, or other electronic components that generate heat as part of operation. Being thermally coupled with active pixels110via substrate101, generated heat can be transported to proximal region315of active pixels by various physical mechanisms including but not limited to conduction, radiation, etc. In some embodiments, power circuit can generate EM radiation205that includes energetic photons in the visible spectrum, although transmission of visible photons through substrate101is likely to be limited.

In so doing, power circuit310can emit EM radiation205in an isotropic distribution or in an anisotropic distribution. For example, a resistive element of power circuit310can behave as an isotropic point source of thermal radiation. In this way, diagonal isolation structure(s)109nearer to localized EM radiation sources195can receive a higher incident flux of EM radiation205. As such, while diagonal isolation structure(s)109are shown extending vertically to be at least coextensive with power circuit310, at least some portion of diagonal isolation structure(s)109can be omitted and the area of the substrate can be rededicated to other purposes (e.g., ASIC190, power circuit310, other CMOS components such as vias, etc.) where source(s) of EM radiation195can be identified during design of power circuit310(e.g., by operational simulation) and the radiation transmission patterns pre-determined.

With such information, diagonal isolation structure(s)109can be disposed discontinuously in one or more regions of example image sensor300, localized in the proximity of EM radiation source(s)195, to attenuate the level of residual EM radiation210reaching proximal region315while also reserving limited substrate area for other uses. It is understood that the specific locations of EM radiation source(s)195can depend on the design of power circuit310and/or ASIC(s)190used. For at least this reason, the precise placement of diagonal isolation structure(s)109can be determined as part of overall sensor design, rather than an a priori specification based on the relative location of active pixels110and ASIC190components of example image sensor300.

In some embodiments, diagonal isolation structures can include a sloped sidewall to redirect EM radiation205away from proximal region325in a third dimension, such as out through first side103or out through second side105. For example, where EM radiation205includes thermal radiation, diagonal isolation structure305can be configured to redirect EM radiation205toward a heatsink thermally coupled with power circuit310of example image sensor300through first side103and/or through second side105.

FIG.3Bis a schematic diagram illustrating an example diagonal isolation structure320configured as a lattice, in accordance with embodiments of the present disclosure. Isolation structure320defines a first reflective surface321-1oriented on a first bias θ1relative to the array of active pixels110and a second reflective surface321-2oriented on a second bias θ2relative to the array of active pixels. In this context, the term “bias” refers to the respective angular orientation of reflective surfaces321-1and321-2relative to vertical325and lateral327axes defined by the lattice of isolation structures108used to isolate active pixels110in active pixel region110.FIG.3Billustrates a plan view of diagonal isolation structure320that can be formed as described in reference to isolation structures108ofFIG.1B. In an illustrative example, a uniform photoresist layer can be patterned with two separate patterns, the first to form isolation structure108in active pixel region110and the second to form diagonal isolation structure320in peripheral region140. Subsequent removal and deposition operations as described in more detail in reference toFIG.1Bcan be implemented concurrently to form both isolation structure108and diagonal isolation structure without increasing the number and complexity of fabrication operations.

In some embodiments, first reflective surface321-1and second reflective surface321-2are biased relative to lateral axis327by equal and opposite angles, to form a complementary pair of reflective surfaces configured to redirect EM radiation205away from active pixels110with paired low-angle reflections. In some embodiments, first bias and second bias can be unequal, as an approach to effect a redirection of incident EM radiation205away from active pixels110and from power circuit310.

First bias and/or second bias can be configured such that incident EM radiation205that is aligned or approximately aligned with lateral axis327interacts with first reflective surface321-1and/or second reflective surface321-2at an acute angle of incidence rather than a normal angle (e.g., 90 degrees relative to a respective reflective surface321-1or321-2). As described in reference toFIG.2B, a lower angle of incidence (e.g., closer to a grazing angle or an angle approaching zero degrees relative to a surface) is more likely to reflect incident radiation, where the reflective surface has a relatively lower index of refraction than the medium through which the radiation is traveling. As such, first bias and/or second bias can be configured such that incident EM radiation205from EM radiation source(s)195near to proximal region315is incident at an angle of incidence likely to reflect EM radiation205. To that end, first bias and/or second bias can be from about 10 degrees to about 90 degrees, from about 15 degrees to about 85 degrees, from about 20 degrees to about 80 degrees, from about 25 degrees to about 75 degrees, from about 30 degrees to about 70 degrees, from about 30 degrees to about 65 degrees, from about 30 degrees to about 60 degrees, from about 35 degrees to about 55 degrees, or from about 40 degrees to about 50 degrees, including fractions and interpolations thereof. For example, first bias and/or second bias can be about 1 degree, about 2 degrees, about 3 degrees, about 4 degrees, about 5 degrees, about 6 degrees, about 7 degrees, about 8 degrees, about 9 degrees, about 10 degrees, about 15 degrees, about 20 degrees, about 25 degrees, about 30 degrees, about 35 degrees, about 40 degrees, about 45 degrees, about 50 degrees, about 55 degrees, about 60 degrees, about 65 degrees, or greater, including fractions and interpolations thereof. First bias and second bias can be equal angles, opposite angles, or different angles. As described in more detail in reference toFIG.2B, for a bias at an angle approaching orthogonality relative to incident EM radiation205, reflection will become less favored as opposed to transmission when passing from a higher index of refraction to a lower index of refraction. For that reason, diagonal isolation structure320can be configured at a design stage based at least in part on the location and expected direction of EM radiation source(s)195, such that EM radiation205is redirected and/or reflected away from proximal region315.

In some embodiments, first bias and/or second bias can be determined based at least in part on the critical angle of internal reflection derived from Snell's law. For example, where substrate101has a higher index of refraction than diagonal isolation structure(s)320, a critical angle exists where EM radiation incident at an angle greater than the critical angle will be reflected. In this way, first bias and/or second bias can be about equal to the critical angle for the paired materials or less, which is described by the expression: θcrit=arcsin(n2/n1) with n1representing the index of refraction of the higher-index material.

Diagonal isolation structure320is illustrated as a repeating lattice of cells defined by a side length330, of which only a portion is shown. The ellipses “ ” ofFIG.3Bare used to indicate that the lattice can be extended in one or more directions to increase the size of diagonal isolation structure320and the number of cells. In some embodiments, lattice320can be a regular lattice defining a substantially uniform side length for every reflective surface321including reflective surfaces321-1and/or321-2, and thus a size of the cells making up the lattice of cells, that is substantially equal to the size of active pixels110defined by isolation structure(s)108. For example, a fabrication process for diagonal isolation structure320can include optical lithographic patterning of a uniform photoresist layer disposed overlying active pixel region110and peripheral region140, where a lattice pattern is transferred onto active pixel region110to later define isolation structure(s)108, after which the substrate is rotated relative to the optical lithography source (e.g., laser) and the same lattice pattern is transferred onto peripheral region140to later define diagonal isolation structure(s)320. WhileFIG.3Billustrates diagonal isolation structure(s)320as a regular rectangular/square lattice, an irregular lattice can also be provided by spatial variation of side length330and/or first bias and/or second bias. Advantageously, introducing spatial variation of lattice geometric parameters can reduce the transmission of EM radiation205through vertices or other points in diagonal isolation structure(s)320, as described in more detail in reference toFIG.3D.

To that end, side length330can approximate the size of an active pixel110, including but not limited to a length of about 0.1 about 0.2 about 0.3 about 0.4 μm, about 0.5 μm, about 0.6 μm, about 0.7 μm, about 0.8 μm, about 0.9 μm, about 1 μm, about 1.1 μm, about 1.2 μm, about 1.3 μm, about 1.4 μm, about 1.5 μm, about 1.6 μm, about 1.7 μm, about 1.8 μm, about 1.9 μm, about 2.0 μm, about 2.5 μm, about 3.0 μm, about 3.5 μm, about 4.0 μm, about 4.5 μm, about 5.0 μm, about 5.5 μm, about 6.0 μm, about 6.5 μm, about 7.0 μm, about 7.5 μm, about 8.0 μm, about 8.5 μm, about 9.0 μm, about 9.5 μm, about 10.0 μm, about 10.5 μm, about 11.0 μm, about 11.5 μm, about 12.0 μm, about 12.5 μm, about 13.0 μm, about 13.5 μm, about 14.0 μm, about 14.5 μm, about 15.0 μm, or greater, including fractions and interpolations thereof. Side length330can be practically limited, however, by space constraints of peripheral region140between proximal region315and EM radiation source(s)195. Further, smaller side length330corresponds to a denser lattice structure with more repeated instances of first reflective surface321-1and second reflective surface321-2over a given area. Advantageously, disposing a greater number of reflective surfaces between EM radiation source(s)195and proximal region315can increase the attenuation of EM radiation205, reducing the flux of residual EM radiation210reaching proximal region315. Below a lower manufacturability limit of side length330, however, first reflective surface321-1and second reflective surface321-2can be indistinct. As such, an effective lower limit on side length can be imposed by process parameters and/or constraints of a semiconductor manufacturing process used to fabricate example image sensor300.

FIG.3Cis a schematic diagram illustrating an example array350of diagonal isolation structures355configured to improve isolation of active pixels110, in accordance with embodiments of the present disclosure. As described in more detail in reference toFIG.3B, diagonal isolation structures355can be disposed in peripheral region140between EM radiation source(s)195and proximal region315, such that EM radiation205incident on diagonal isolation structures355is attenuated, reducing residual EM radiation210up to and including an extent at which the flux of residual EM radiation into proximal region315induces negligible or no non-uniform dark current in active pixel region110. In this context, “negligible” is used to indicate that a non-zero dark current in proximal region315that is attributable to residual EM radiation210can be tolerated in some instances, for example, by calibration of example image sensor300, that is unavailable with relatively higher fluxes exhibited with isolation structures described in reference toFIGS.2A-2B.

As with diagonal isolation structure(s)320, diagonal isolation structures355define first reflective surfaces321-1and second reflective surfaces321-2according to first bias and second bias, respectively. Similarly, reflective surfaces321-1and/or321-2can be described by side length330, as described in more detail in reference toFIG.3B. In some embodiments, diagonal isolation structures355include multiple repeated instances of first reflective surface321-1and second reflective surface321-2to define a “zig-zag” structure that includes multiple paired reflective surfaces that together act as a contra-directional reflector for incident EM radiation205. As with diagonal isolation structure(s)320, the ellipses “ . . . ” are used to indicate that example array350can include more or fewer than four diagonal isolation structures355, and individual diagonal isolation structures can include more or fewer than four instances of reflective surfaces321-1and321-2. In some embodiments, example array350includes one, two, three, four, five, six, seven, eight, nine, ten, or more diagonal isolation structures355. Understandably, the number of diagonal isolation structures355can be constrained by a lower manufacturability limit below which the structures are will not be distinct in a manufactured image sensor, and by an upper limit set by the area available for example array350.

Advantageously, diagonal isolation structures355be formed in substrate101without bridging between individual isolation structures355. As such, incident EM radiation205that is partially transmitted into material of diagonal isolation structures355can be isolated within diagonal isolation structures355(e.g., by internal reflection), without being transported nearer to proximal region315. Additionally, diagonal isolation structures355can be offset relative to each other, as described in more detail in reference toFIG.3D, as an approach to limiting the transmission of EM radiation205through vertices387(in reference toFIG.3D) joining reflective surfaces321.

FIG.3Dis a schematic diagram illustrating an example staggered array370of diagonal isolation structures355configured to improve isolation of active pixels, in accordance with embodiments of the present disclosure. Example staggered array370is an example of diagonal isolation structure109ofFIG.1Aand, like example array350, an example of diagonal isolation structure305ofFIG.3A. Staggered array370includes a first subset375of diagonal isolation structures355and a second subset380of diagonal isolation structures355. In example staggered array370, first subset375is offset from second subset380along vertical axis325by a vertical offset385and is offset along lateral axis327by a lateral offset395. In some embodiments, the lateral offset395can be comparable to side length330, for example, being in a range from about 0.1 μm to about 15 μm. For example, lateral offset can be about 0.1 μm, about 0.2 μm, about 0.3 μm, about 0.4 μm, about 0.5 μm, about 0.6 μm, about 0.7 μm, about 0.8 μm, about 0.9 μm, about 1 μm, about 1.1 μm, about 1.2 μm, about 1.3 μm, about 1.4 μm, about 1.5 μm, about 1.6 μm, about 1.7 μm, about 1.8 μm, about 1.9 μm, about 2.0 μm, about 2.5 μm, about 3.0 μm, about 3.5 μm, about 4.0 μm, about 4.5 μm, about 5.0 μm, about 5.5 μm, about 6.0 μm, about 6.5 μm, about 7.0 μm, about 7.5 μm, about 8.0 μm, about 8.5 μm, about 9.0 μm, about 9.5 μm, about 10.0 μm, about 10.5 μm, about 11.0 μm, about 11.5 μm, about 12.0 μm, about 12.5 μm, about 13.0 μm, about 13.5 μm, about 14.0 μm, about 14.5 μm, about 15.0 μm, or greater, including fractions and interpolations thereof. In general, a smaller spacing permits a larger number of diagonal isolation structures355to be included in example array350. The lower limit of the spacing can be based at least in part on maintaining a separation between diagonal isolation structures355. The upper limit of the spacing can be based at least in part on area constraints in peripheral region140.

As described in reference to example array350, example staggered array370can include more or fewer than four diagonal isolation structures355and can be extended in either vertical direction to include more than four instances of first reflective surface321-1and/or321-2. As with previous example isolation structures described in reference toFIGS.3B-3C, reflective surfaces321defined by diagonal isolation structures355can be configured to attenuate EM radiation205by pairing a first reflection371-1and a second reflection371-2by the first reflective surface321-1and the second reflective surface321-2. It is understood that the first reflection371-1can occur on the first reflective surface321-1or the second reflective surface321-2, as illustrated by the different ray lines of EM radiation205.

At junctions between reflective surfaces321, diagonal isolation structures355can define vertices381, including a first vertex387-1and a second vertex387-2. Using vertices381as a reference, vertical offset385can be about half of a vertical distance395between first vertex387-1and second vertex387-2. Advantageously, configuring staggered array370with vertical offset can permit EM radiation205incident on a vertex387of a diagonal isolation structure355of first subset375, where EM radiation205is more lightly to be transmitted than EM radiation205incident on reflective surfaces321, to be reflected by a diagonal isolation structure355of the second subset380. Where vertical offset385is about half of vertical distance395, paired reflections371will redirect EM radiation through a neighboring vertex387.

In some embodiments, vertical offset385can be greater than or less than vertical distance395. Advantageously, such a configuration can serve to retain EM radiation in substrate101between diagonal isolation structures355, to be removed through first surface103and/or second surface105, rather than being redirected in to source of EM radiation195.

It is appreciated that the various process steps involved in the preparation of diagonal isolation structure109(e.g., diagonal isolation structure305as illustrated inFIGS.3A-3D) can be implemented using existing CMOS manufacturing techniques such as, but not limited to photolithograph, metal deposition (e.g., atomic layer deposition, physical vapor deposition, thermal evaporation, magnetron sputtering, or the like, etching techniques (e.g., dry etching techniques such as plasma etching, wet etching techniques such as chemical etching, or the like), and planarization techniques (e.g., chemical-mechanical polishing). It is understood that CMOS manufacturing systems typically reproduce a pattern within a process tolerance that permits some level of deviation from an exact design. Edge placement error (EPE) is an example figure of merit used to describe the precision and accuracy of a CMOS process, where an EPE value below an allowable tolerance can include deviations that are tolerated.

In some cases, tolerance(s) can be based at least in part on the functionality of the resulting structure(s). For example, for diagonal isolation structure(s)320and/or355an attenuation of residual EM radiation210below a tolerable level (e.g., by an undetectable or effectively undetectable dark signal from proximal region315) can serve as a criterion for determining a manufacturing precision tolerance. In this way, the term “substantially” as in the context of “substantially aligned,” “substantially parallel,” “substantially orthogonal,” or the like, can be interpreted to indicate a structure that exhibits the stated property within manufacturing tolerances. Similarly, terms including but not limited to “approximately” that are used to describe a minor or tolerable deviation from the stated condition or property can be understood to apply to structures that are manufactured according to a design that includes the stated condition or property, where the manufacturing process can introduce the tolerable deviation.

FIG.4is a functional block diagram of an imaging system402including an image sensor400with diagonal isolation structures, in accordance with the teachings of the present disclosure. The image sensor400can have a structure corresponding to image sensor100illustrated inFIGS.1A-1Band/or example image sensor300illustrated inFIG.3A. The imaging system402includes image sensor400to generate electrical or image signals in response to incident light470, objective lens(es)465with adjustable optical power to focus on one or more points of interest within the external scene403, and controller450to control, inter alia, operation of image sensor400and objective lens(es)465. Image sensor400is one possible implementation of image sensor100illustrated inFIGS.1A-1Band/or example image sensor300illustrated inFIG.3A. Image sensor400is a simplified schematic showing a semiconductor material401with a plurality of photodiodes405disposed within respective portions of the semiconductor material401, a plurality of color filters410, and a plurality of microlenses415. The controller450includes one or more processors452, memory454, control circuitry456, readout circuitry458, and function logic460.

The controller450includes logic and/or circuitry to control the operation (e.g., during pre-, post-, and in situ phases of image and/or video acquisition) of the various components of imaging system402. The controller450can be implemented as hardware logic (e.g., application specific integrated circuits, field programmable gate arrays, system-on-chip, etc.), software/firmware logic executed on a general purpose microcontroller or microprocessor, or a combination of both hardware and software/firmware logic. In one embodiment, the controller450includes the processor452coupled to memory454that stores instructions for execution by the controller450and/or one or more other components of the imaging system402. The instructions, when executed, can cause the imaging system402to perform operations associated with the various functional modules, logic blocks, or circuitry of the imaging system402including one of, or a combination of, the control circuitry456, the readout circuitry458, the function logic460, image sensor400, objective lens465, and another element of imaging system402(illustrated or otherwise). The memory is a non-transitory computer-readable medium that can include, without limitation, a volatile (e.g., RAM) or non-volatile (e.g., ROM) storage system readable by controller450. It is further appreciated that the controller450can be a monolithic integrated circuit, one or more discrete interconnected electrical components, or a combination thereof. Additionally, in some embodiments one or more electrical components can be coupled together to collectively function as controller450for orchestrating operation of the imaging system502.

Control circuitry456can control operational characteristics of the photodiode array405(e.g., exposure duration, when to capture digital images or videos, and the like). Readout circuitry458reads or otherwise samples the analog signal from the individual photodiodes (e.g., read out electrical signals generated by each of the plurality of photodiodes405in response to incident light to generate image signals for capturing an image frame, and the like) and can include amplification circuitry, analog-to-digital (ADC) circuitry, image buffers, or otherwise. In the illustrated embodiment, readout circuitry458is included in controller450, but in other embodiments readout circuitry458can be separate from the controller450. Function logic460is coupled to the readout circuitry458to receive image data to demosaic the image data and generate one or more image frames. In some embodiments, the electrical signals and/or image data can be manipulated or otherwise processed by the function logic460(e.g., apply post image effects such as crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise).

The processes explained above can be implemented using software and/or hardware. The techniques described can constitute machine-executable instructions embodied within a tangible or non-transitory machine (e.g., computer) readable storage medium, that when executed by a machine (e.g., controller450ofFIG.4) will cause the machine to perform the operations described. Additionally, the processes can be embodied within hardware, such as an application specific integrated circuit (“ASIC”), field programmable gate array (FPGA), or otherwise.