ENHANCED TEMPERATURE RANGE FOR RESISTIVE TYPE MEMORY CIRCUITS WITH PRE-HEAT OPERATION

Example embodiments include devices, systems, and methods for enhancing an operating temperature range for resistive type memory devices. After powering up the resistive type memory die, the die temperature of the resistive type memory die is sensed. If the sensed die temperature is less than a predefined temperature threshold, one or more heaters proximately disposed to one or more memory cells of the resistive type memory die are enabled. The heaters are disabled responsive to the sensed die temperature being greater than a predefined temperature threshold. Memory write operations are enabled responsive to the sensed die temperature being greater than the predefined temperature threshold. After enabling the memory write operations, an enabled state of the memory write operations is maintained until the resistive type memory die is powered down. If the die temperature happens to fall below the predefined temperature threshold at a later time, additional heat is produced.

BACKGROUND

Inventive concepts relate to resistive type memory circuits, and more particularly to memory pre-heat devices and methods for enhancing an operating temperature range of the resistive type memory circuits.

Resistive type memories encompass a new generation of non-volatile memory and are expected to become more prevalent in the marketplace. Resistive type memories can include, for example, spin transfer torque (STT) magnetoresistive random-access memory (MRAM), MRAM (of the non-STT variety), memristor RAM, ReRAM, CBRAM, and the like.

It is preferable for STT-MRAM to operate within a set temperature range. Industrial operating temperature range requirements call for memory products to operate from −40 degrees Celsius on up. For magnetic tunnel junctions (MTJ) used in STT-MRAM, the switching voltage is inversely proportional to temperature. That is, lower temperature needs higher switching voltage. MTJ write issues exist at low temperature due to the higher required switching voltage. These problems include poor reliability due to increased possibility of breakdown and large power consumption due to high VDD supply.

FIGS. 1A and 1Bare schematic diagrams of an example STT MRAM memory cell30. In some embodiments, the memory cell30is a spin transfer torque (STT) magnetoresistive random-access memory (MRAM) memory cell. It will be understood, however, that inventive concepts described herein apply to resistive memories of other types, such as MRAM (of the non-STT variety), memristor RAM, ReRAM, CBRAM, and the like.

FIG. 1Ashows a magnetic tunnel junction (MTJ)10, which forms a variable resistor in an STT-MRAM type memory cell, and an associated select transistor20, together forming an STT-MRAM cell30. The MTJ10includes a reference or pinned layer12, a free layer16, and a tunneling layer14disposed between the reference layer12and the free layer16. Transistor20is often an NMOS type transistor due to its inherently higher current drive, lower threshold voltage, and smaller area relative to a PMOS type transistor.

In the following description, an MRAM cell is defined as being in a logic “0” state when the free and reference layers of its associated MTJ are in a parallel (P) state, i.e., the MTJ exhibits a low resistance. Conversely, an MRAM cell is defined as being in a logic “1” state when the free and reference layers of its associated MTJ are in an anti-parallel (AP) state, i.e., the MTJ exhibits a high resistance. It will be understood that in other embodiments, the MRAM cell can be defined as being in the logic “0” state when in an AP state, and the logic “1” state when in a P state. Furthermore, in the following, it is assumed that the reference layer of the MTJ10faces its associated select transistor, as shown inFIG. 1A.

Therefore, in accordance with the discussion above, a current flowing along the direction of arrow35(i.e., the up direction) either (i) causes a switch from the P state to the AP state thus to write a “1”, or (ii) stabilizes the previously established AP state of the associated MTJ. Likewise, a current flowing along the direction of arrow40(i.e., the down direction) either (i) causes a switch from the AP state to the P state thus to write a “0”, or (ii) stabilizes the previously established P state of the associated MTJ. It is understood, however, that in other embodiments this orientation may be reversed so that the free layer of the MTJ faces its associated select transistor. In such embodiments (not shown), a current flowing along the direction of arrow35either (i) causes a switch from the AP state to the P, or (ii) stabilizes the previously established P state of the associated MTJ Likewise, in such embodiments, a current flowing along the direction of arrow40either (i) causes a switch from the P state to the AP state, or (ii) stabilizes the previously established AP state.

FIG. 1Bis a schematic representation of MRAM30ofFIG. 1Ain which MTJ10is shown as a storage element whose resistance varies depending on the data stored therein. The MTJ10changes its state (i) from P to AP when the current flows along arrow35, and/or (ii) from AP to P when the current flows along arrow40.

The voltage required to switch the MTJ10from an AP state to a P state, or vice versa, must exceed a critical value Vc. The current corresponding to this voltage is referred to as the critical or switching current Ic. Under a normal operating mode, to transition from the P state (i.e., low resistance state) to AP state (i.e., high resistance state), a positive write voltage of at least Vcis applied so that a current level of at least the switching current Icflows through the memory cell. Once in the AP state, removing the applied voltage does not affect the state of the MTJ10. Likewise, to transition from the AP state to the P state under the normal operating mode, a negative write voltage of −Vcor lower is applied so that a current level of at least the switching current Icflows through the memory cell in the opposite direction. Once in the P state, removing the applied voltage does not affect the state of the MTJ10.

In other words, MTJ10can be switched from an anti-parallel state (i.e., high resistance state, or logic “1” state) to a parallel state so as to store a “0” (i.e., low resistance state, or logic “0” state). Assuming that MTJ10is initially in a logic “1” or AP state, to store a “0”, under the normal operating mode, a write current at least as great or greater than the critical current Icis caused to flow through transistor20in the direction of arrow40. To achieve this, the source node (SL or source line) of transistor20is coupled to the ground potential via a resistive path (not shown), a positive voltage is applied to the gate node (WL or word line) of transistor20, and a positive voltage is applied to the drain node (BL or bit line) of transistor20.

The MTJ10can also be switched from a parallel state to an anti-parallel state so as to store a “1”. Assuming that MTJ10is initially in a logic “0” or P state, to store a “1”, under the normal operating mode, a write current at least as great or greater than the critical current Icis caused to flow through transistor20in the direction of arrow35. To achieve this, node SL is supplied with a positive voltage via a resistive path (not shown), node WL is supplied with a positive voltage, and node BL is coupled to the ground potential via a resistive path (not shown).

As mentioned above, MTJ write issues are manifested at low temperatures due to the higher required switching voltage. Moreover, challenges arise such as poor reliability due to the increased possibility of breakdown and large power consumption due to the high Vdd supply. These and other limitations in the prior art are addressed by embodiments of the inventive concept disclosed herein, without compromising other memory chip requirement such as a simple and small area requirement, no additional writing delay, and no extra power consumption.

BRIEF SUMMARY

According to one embodiment of the inventive concept, a method for enhancing an operating temperature range for a resistive type memory die includes powering up the resistive type memory die, sensing a die temperature of the resistive type memory die, enabling one or more heaters proximately disposed to one or more memory cells of the resistive type memory die responsive to the sensed die temperature being less than a predefined temperature threshold, and disabling the one or more heaters responsive to the sensed die temperature being greater than a predefined temperature threshold.

The memory write operations may be enabled responsive to the sensed die temperature being greater than the predefined temperature threshold. After enabling the memory write operations, an enabled state of the memory write operations may be maintained until the resistive type memory die is powered down. In addition, after enabling the memory write operations, die temperature of the resistive type memory die may be sensed, and responsive to the sensed die temperature being less than the predefined temperature threshold, heat may be produced by enabling the one or more heaters proximately disposed to the one or more memory cells of the resistive type memory die. Responsive to the sensed die temperature being greater than the predefined temperature threshold, the one or more heaters may be disabled.

Another embodiment of the inventive concept includes a temperature control apparatus for use with a resistive type memory die. The temperature control apparatus may include one or more temperature sensors configured to sense a die temperature of the resistive type memory die, and a temperature control circuit configured to enable one or more heaters proximately disposed to one or more memory cells of the resistive type memory die responsive to the sensed die temperature being less than a predefined temperature threshold. The temperature control circuit may disable the one or more heaters responsive to the sensed die temperature being greater than a predefined temperature threshold.

Yet another embodiment of the inventive concept includes a computing system, comprising a bus, a memory device coupled to the bus, wherein the memory device includes a resistive type memory die, and a processor coupled to the bus and configured to store information in the memory device. The memory device may further comprise one or more temperature sensors configured to sense a die temperature of the resistive type memory die, and a temperature control circuit configured to enable one or more heaters proximately disposed to one or more memory cells of the resistive type memory die responsive to the sensed die temperature being less than a predefined temperature threshold. The temperature control circuit may disable the one or more heaters responsive to the sensed die temperature being greater than a predefined temperature threshold.

The foregoing and other features and advantages of the inventive concept will become more readily apparent from the following detailed description of the example embodiments, which proceeds with reference to the accompanying drawings.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments of the inventive concept, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth to enable a thorough understanding of the inventive concept. It should be understood, however, that persons having ordinary skill in the art may practice the inventive concept without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first circuit could be termed a second circuit, and, similarly, a second circuit could be termed a first circuit, without departing from the scope of the inventive concept.

FIG. 2Ais a diagram200illustrating the switching voltage (e.g., +Vcor −Vc) of an example STT MRAM memory cell at high (RH) and low (RL) values of MTJ resistance. When the MTJ is configured to have a low MTJ resistance of RL, a positive write voltage of at least the switching voltage +Vcis needed to achieve a write error rate (WER) of about 0.5. The WER is a probability that the magnetization of the memory cell does not switch in response to an attempt to switch the memory cell. When the MTJ is configured to have a high MTJ resistance of RH, a negative write voltage of the switching voltage −Vcor lower is needed to achieve a write error rate (WER) of about 0.5. Line205of the diagram200shows the relationship between the MTJ resistance values and the corresponding switching voltage.

FIG. 2Bis a more detailed diagram210illustrating the switching voltage of an example STT MRAM memory cell at high and low values of MTJ resistance for different temperatures. Diagram210is similar to diagram200, but as can be seen in diagram210, two different temperatures (e.g., −40 degrees Celsius and +120 degrees Celsius) are shown. The switching voltage is affected by the die temperature.

The write voltage applied to the memory cell may be determined at least in part by the measured and/or set temperature of the die. In other words, memory write voltage may be adjusted based on sensed temperature of the die. In addition, as further described below, the temperature of the die may be controlled at least in part using one or more integrated die heaters. This, in turn, can be used to control or otherwise influence the applied memory write voltage levels.

Line215of the diagram210shows the relationship between the MTJ resistance values and the corresponding switching voltage (e.g., +0.8 Volts or −0.8 Volts) at a die temperature of −40 degrees Celsius. Line220of the diagram210shows the relationship between the MTJ resistance values and the corresponding switching voltage (e.g., +0.2 Volts or −0.2 Volts) at a die temperature of +120 degrees Celsius. When the die temperature is relatively colder (e.g., −40 degrees Celsius), the switching voltage has a wide variation relative to when the die temperature is relatively warmer (e.g., 120 degrees Celsius).

For example, in automotive applications, space applications, or other rugged applications, temperatures can drop very low, which directly affect the switching voltage, which in turn has ramifications on the operability and reliability of resistive type memories.

FIG. 3is an example block diagram300of a resistive type memory cell320and an associated writer block310and regulator block305. A voltage supply VDD is coupled the regulator305and a ground voltage GND is coupled to a cell transistor315of the resistive type memory cell320. The value VMTJis the voltage drop across the resistance RMTJ. The VMTJvalue is equal to two (2) times the switching voltage Vcto achieve a WER of zero (0), or nearly zero. The value VCTRis the voltage drop across the cell transistor315. To reduce memory cell area, the cell transistor resistance RCTRis set substantially equivalent to the low value (i.e., RL) of the MTJ resistance RMTJ. The value VBLis the voltage drop across both the resistance RMTJand the cell transistor resistance RCTR. The value VBLis referred to as the write voltage. Specifically, in this example, the value VBLis equal to two (2) times the value VMTJ, or thereabout. To achieve a WER of zero or near zero, in this example, the write voltage VBLis four (4) times the switching voltage Vc(i.e., write voltage VBL=2*VMTJ, where VMTJ=2*Vc).

FIGS. 4A and 4Billustrate example diagrams400and420, respectively, demonstrating memory write issues that are encountered at relatively colder temperatures. The values VMTJand VBLare plotted as a function of die temperature405. As can be seen in diagram400, when the die temperature is relatively colder (e.g., −40 degrees Celsius), the VMTJvalue, as shown by line415, is 1.6 Volts, which is problematic because it is within the MTJ breakdown region410.FIG. 4Bincludes the additional line425showing the write voltage VBLvalue as a function of the die temperature405. When VMTJhas a value of 1.6 Volts, VBLhas a value of 3.2 Volts. To provide sufficient regulator overhead430, the voltage supply VDD has a value of 4.0 Volts. Operating at cold temperatures, such as −40 degrees Celsius, can cause the resistive type memory cells to consume large amounts of power, and at the same time, such operating conditions can cause reliability issues due to breakdown of the MTJ region.

FIG. 5illustrates a memory die500having associated one or more temperature sensors (e.g.,505) and one or more heat generators (e.g.,510) in accordance with embodiments of the inventive concept.FIG. 6is a diagram600illustrating operation of the heat generators in accordance with embodiments of the inventive concept. The heat generators510are also referred to herein as heaters510. Reference is now made toFIGS. 5 and 6.

The one or more temperature sensors (e.g.,505) can sense a die temperature605of the resistive type memory die500. A temperature control circuit520can enable or otherwise turn on one or more heaters510proximately disposed to one or more memory cells515of the resistive type memory die500responsive to the sensed die temperature605being less than a predefined temperature threshold Tref, as shown at610. The temperature control circuit520can disable or otherwise turn off the one or more heaters510responsive to the sensed die temperature605being greater than a predefined temperature threshold Tref, as shown at615.

The one or more heaters510can generate heat during a pre-heat operation. The pre-heat operation, however, may be omitted if the die temperature is determined to be less than the predefined temperature threshold Treffollowing power up. The one or more heaters510can be proximately disposed to memory cells515of the resistive type memory die500, and provide heat to the memory cells515, either during a pre-heat operation or after memory writes are enabled, or both.

A regulator circuit (e.g.,305ofFIG. 3) can enable memory write operations responsive to the sensed die temperature605being greater than the predefined temperature threshold Tref. After enabling the memory write operations, the regulator circuit305can maintain an enabled state of the memory write operations until the resistive type memory die500is powered down. In addition, after enabling the memory write operations, the one or more temperature sensors505can again sense the die temperature605of the resistive type memory die500. In response to the sensed die temperature605being less than the predefined temperature threshold Tref, the temperature control circuit520can enable or otherwise turn on the one or more heaters510to produce and transfer heat to the one or more memory cells515of the resistive type memory die500, as shown at610. Moreover, after enabling the memory write operations, the temperature control circuit520can disable the one or more heaters510in response to the sensed die temperature605being greater than the predefined temperature threshold Tref, as shown at615. In this manner, the die temperature605is regulated around Trefto keep the die temperature605above at least the predefined temperature threshold Tref.

In some embodiments of the inventive concept, the one or more heaters510can be disposed within the resistive type memory die500. In some embodiments, the one or more heaters510can be disposed underneath power lines and ground lines (not shown) of the resistive type memory die500. In some embodiments, the heat generators are proportionally distributed in multiple places within, on, or underneath the resistive type memory die500. In addition, the one or more temperature sensors505can be disposed in one or more places, and can also be proportionally distributed within, on, or underneath the resistive type memory die500.

FIGS. 7A and 7Bare diagrams700and720, respectively, illustrating a write voltage (e.g., VBL) as a function of die temperature705in accordance with embodiments of the inventive concept. Both of the values VMTJand VBLare plotted as a function of die temperature705. As can be seen in diagram700, when the die temperature is relatively colder (e.g., −40 degrees Celsius), the VMTJvalue, as shown by line710, is 1.0 Volt, which avoids the MTJ breakdown region715. Because the die temperature705is maintained above the predefined temperature threshold Tref, the VMTJvalue need not rise above 1 Volt. It will be understood that the value of 1 Volt for the VMTJvalue is illustrative, and is not limited to solely this value. The VMTJvalue can be made lower due to the temperature control apparatus described above with reference toFIGS. 5 and 6, particularly as transistor sizes continue to decrease with the general advance of semiconductor processing technology.

FIG. 7Bincludes the additional line725showing the write voltage VBLvalue as a function of the die temperature705. When VMTJhas a value of 1.0 Volt, VBLhas a value of 2.0 Volts. To provide sufficient regulator overhead730, the voltage supply VDD has a value of 2.5 Volts. It will be understood that the write voltage of 2.0 Volts and the voltage supply value of 2.5 Volts are illustrative, and the embodiments described herein are not limited to these values, but rather, other values can be used and still fall within the scope of the inventive concept. The resistive type memory die can therefore operate at cold temperatures, such as −40 degrees Celsius, without consuming large amounts of power, and without suffering reliability issues associated with breakdown of the MTJ region.

FIG. 8is a flow diagram800illustrating a technique for enhancing the operating temperature range of resistive type memories in accordance with embodiments of the inventive concept.FIG. 9is a waveform diagram900illustrating various signals and other values for enhancing the operating temperature range of resistive type memories in accordance with embodiments of the inventive concept. Reference is now made toFIGS. 8 and 9.

The technique begins at805where the resistive type memory die is powered up. In other words, initial power is supplied to the memory, as shown at905of the waveform diagram900. After powering up the resistive type memory die, the die temperature is sensed, and a determination is made at815whether the die temperature is greater than a predefined temperature threshold Tref. If the die temperature does not exceed the predefined temperature threshold Tref, the flow proceeds to820, where heat is generated by the heaters. The heat is produced as a result of heaters turning on, in response to a heater signal, as shown at910of the waveform diagram. The heaters may produce the heat during a pre-heat operation (i.e., before any memory writes have occurred). However, the pre-heat operation may be omitted if the die temperature is determined to be less than the predefined temperature threshold Treffollowing power up.

The heaters can be proximately disposed to memory cells of the resistive type memory die, and provide heat to the memory cells, either during a pre-heat operation or after memory writes are enabled, or both.

Referring back to the determination made at815, in response to the die temperature being greater than the predefined temperature threshold Tref, as shown at915of the waveform diagram900, the flow proceeds to825, where another determination can be made whether write operations are enabled. In response to determining that write operations are not enabled, the flow proceeds to830, where write operations are enabled. As shown at920of the waveform diagram900, a writer enable signal can be asserted, which may enable the write operations. Once enabled, the write enable signal920can be maintained in an enabled state until power down of the memory die. This is possible due to the fast heat generating response provided by the embodiments disclosed herein.

Referring back to the determination at825, if the writer is not yet enabled, the flow returns to815for additional determinations as to whether the die temperature exceeds the predefined temperature threshold Tref.

After enabling the memory write operations, the die temperature of the resistive type memory die continues to be sensed at815. In response to the sensed die temperature being less than (or equal to) the predefined temperature threshold, as shown at925of the waveform diagram900, heat is produced at820by enabling the heaters. Such enabling of the heaters after enabling the memory write operations is shown at930of the waveform diagram900.

After enabling the memory write operations and after enabling the one or more heaters, the die temperature of the resistive type memory die may be sensed yet again at815. The heaters can be disabled, as shown at935of the waveform diagram900, responsive to the sensed die temperature being greater than a predefined temperature threshold, as shown at940of the waveform diagram900.

The heater signal shown at910,930, and935of the waveform diagram900, for example, can cause the one or more heaters to be enabled or disabled. The heater signal is based, for example, on the sensed die temperature, as shown at915,925, and940, respectively, of the waveform diagram900. It will be understood that in some cases, a determination may be made to omit the pre-heating step. It will also be understood that in some cases, once the die temperature is higher than the predetermined threshold Tref, the die temperature may be maintained above the threshold because the die itself generates heat from its operation.

FIGS. 10A,10B, and10C are schematic block diagrams illustrating a sequence of events associated with enhancing the operating temperature range of resistive type memories in accordance with embodiments of the inventive concept. Reference is now made toFIGS. 10A,10B, and10C.

In this example, as shown in the “before” stage inFIG. 10A, the ambient temperature is negative degrees Celsius (i.e., −40° C.). The case1000includes a semiconductor package1005, which itself includes the resistive type memory die1010. Within the case1000are also included various other semiconductor packages or chips1015. Because the case and its various packages and components are not yet powered up at this stage, the temperature of the die1010is substantially equivalent to the ambient temperature of −40° C.

As shown inFIG. 10B, during the pre-heat phase, the heaters begin producing heat1020, thereby heating the die1010until the die temperature is greater than the predefined temperature threshold Tref. While the ambient temperature remains at −40° C., the die temperature rapidly reaches a temperature in which memory write operations can be performed with high reliability and low power consumption. During the pre-heat phase, the die temperature is higher than the case or ambient temperature due to thermal gradient flow. As a result, an operating temperature range for the memory device is enhanced because it can operate in cold or other harsh ambient conditions.

After the pre-heat phase, the next phase is shown inFIG. 10C, in which the natural heat1025is produced by the other packages and chips1015, and the natural heat1030is produced by the memory die1010, generally keeping the die temperature above the predefined temperature threshold Tref. However, if the die temperature happens to drop below the Trefthreshold, the heaters can be re-enabled, as described in detail above.

FIG. 11is a circuit diagram1000illustrating the temperature sensor505and the temperature control circuit520in accordance with embodiments of the inventive concept.FIG. 12is a diagram illustrating hysteresis in the regulation of the die temperature in accordance with embodiments of the inventive concept. Reference is now made toFIGS. 11 and 12.

The temperature sensor505can include a first current source I1, a first bipolar junction transistor (BJT) A1, a second current source I2, and a second BJT A2. The ratio of I1/A1is greater than the ratio of I2/A2. The amplifier1105of the temperature sensor505can compare and amplify a voltage difference between a first base-emitter voltage VBE1and a second base-emitter voltage VBE2. The base-emitter voltages can be determined according to the following formula (1):

where k and q are constants, and T is temperature.

The amplifier1105can generate a proportion to absolute temperature voltage VPTATbased on the voltage difference. Specifically, VPTATcan be determined according to the following formula (2):

where α is the amplifier gain, k and q are constants, and T is temperature.

The temperature control circuit520can include a circuit1110, which is configured to receive a user-configurable reference voltage value Vref. Although the reference value Vrefis user-configurable, it need not be configured by a user, but rather, it may be set to a predefined value by default. The circuit1110also receives the VPTATvalue, compares the reference value Vrefto the VPTATvalue, and generates a heater signal Vheat. The temperature control circuit520can transfer the heater signal Vheatto the one or more heaters to enable or disable the one or more heaters.

The predefined temperature threshold Trefis based on the Vrefvalue, as shown in the diagram1200ofFIG. 12. Preferably, the Trefthreshold is set within the temperature range of −25° C. and +85° C. This can be achieved by setting the appropriate Vrefvalue. In other words, the predefined temperature threshold Trefcorresponds to substantially an intersection of the user-configurable reference value Vrefand the VPTATvalue. This generates a hysteresis effect1215, where if the VPTATvalue as shown by line1210drops below the Vrefvalue as shown by line1220, then the heater signal (i.e., Vheat) is asserted. Conversely, if the VPTATvalue as shown by line1210rises above the Vrefvalue as shown by line1220, then the heater signal (i.e., Vheat) is not asserted. The hysteresis control loop1215facilitates the generation of a clear deterministic on-off heat signal Vheat. The Vrefand the VPTATvalues inFIG. 12are plotted as a function of die temperature1205.

FIGS. 13A and 13Billustrate example diagrams1300and1400, respectively, of heaters and associated switches in accordance with embodiments of the inventive concept. For example, the diagram1300includes a voltage supply VDD coupled to a heat element1310, which itself is coupled to an NMOS type switch transistor1305. When the NMOS type transistor receives an ON signal (i.e., a logic 1) at its gate, heat is generated by the heat element1310. Conversely, when the NMOS type transistor receives an OFF signal (i.e., a logic 0) at its gate, the heat element1310does not generate heat. The diagram1400is similar to that of 1300 except that a PMOS type switch transistor1405is used. In this embodiment, heat is generated by the heat element1410when a logic 0 signal is received at the gate of the PMOS transistor1405. Conversely, when the PMOS type transistor receives a logic 1 at its gate, the heat element1410does not generate heat.

The heat elements1310and1410can be any suitable resistive element such as metal, poly, diffusion, well, and substrate itself. In some embodiments, assuming the total current of the heat element is 200 milliamps (mA) with a 2.5 Volt VDD supply, for example, then the dissipated heat power is around 500 milliwatts (mW). As mentioned above, the heat elements can be disposed at multiple places, such as underneath the VDD and GND power lines, so that little to no die area is used.

FIG. 14is a block diagram of a memory device1405, including a resistive type memory having temperature sensors (e.g.,505) and heaters (e.g.,510), according to an embodiment of the inventive concept. Referring toFIG. 14, the memory device1405includes a memory cell array1410, a data I/O circuit1470, an address decoder1480, and control logic1490. The data I/O circuit1470may include the sense amplifier circuitry1450for sensing or reading bit information stored in memory cell array1410.

Referring toFIG. 14, the memory cell array1410may have a plurality of memory cells MC30, each of which stores one or more data bits. The memory cells MC may be connected to a plurality of word lines WLs, a plurality of source lines SLs, and a plurality of bit lines BLs. The bit lines BLs may be arranged to intersect with the word lines WLs. In addition, some of the memory cells may be reference memory cells70, as further described below. The reference memory cells70may be connected to a plurality of reference lines RLs.

The memory cells may be arranged at intersection portions (not shown) between the word lines and the bit lines.

The address decoder1480may be connected to the memory cell array1410via the word lines WLs and source lines SLs. The address decoder1480may operate responsive to the control of the control logic1490. The address decoder1480may decode an input address to select the word lines WLs and source lines SLs. The address decoder1480may receive power (e.g., a voltage or a current) from the control logic1490to provide it to a selected or unselected word line.

The data input/output circuit1470may be connected to the memory cell array1410via the bit lines BLs. The data input/output circuit1470may operate responsive to the control of the control logic1490. The data input/output circuit1470may select a bit line in response to a bit line selection signal (not shown) from the address decoder1480. The data input/output circuit1470may receive power (e.g., a voltage or a current) from the control logic1490to provide it to a selected bit line.

The control logic1490may be configured to control an overall operation of the memory device1405. The control logic1490may be supplied with external power and/or control signals. The control logic1490may generate power needed for an internal operation using the external power. The control logic1490may control read, write, and/or erase operations in response to the control signals.

FIG. 15is a block diagram schematically illustrating a computing system1500, including a host1520and a resistive type memory storage device1525, according to an embodiment of the inventive concept. The storage device1525may include a resistive type memory1510and a memory controller1505. The resistive type memory1510may include the resistive type memory die500, as described in detail above.

The storage device1525may include a storage medium such as a memory card (e.g., SD, MMC, etc.) or an attachable handheld storage device (e.g., USB memory, etc.). The storage device1525may be connected to the host1520. The storage device1525may transmit and receive data to and from the host1520via a host interface. The storage device1525may be powered by the host1520to execute an internal operation.

FIG. 16is a block diagram of a computing system1600, including a resistive memory system1610, according to an embodiment of the inventive concept. Referring toFIG. 16, the computing system1600includes a memory system1610, a power supply1635, a central processing unit (CPU)1625, and a user interface1630. The memory system1610includes a resistive memory device1620and a memory controller1615. The CPU1625is electrically connected to a system bus1605.

The resistive memory device1620may include the resistive type memory die, including temperature sensors and heaters, in accordance with an embodiment of the inventive concept. The resistive memory device1620may store data through the memory controller1615. The data may be received from the user interface1630and/or processed by the CPU1625. The memory system1600may be used as a semiconductor disc device (SSD).

FIG. 17is a block diagram schematically illustrating a memory system in which a flash memory is replaced with a storage class memory using a resistive memory, according to an embodiment of the inventive concept. Referring toFIG. 17, a memory system1700may include a CPU1710, a synchronous DRAM (SDRAM)1720, and a storage class memory (SCM)1730. The SCM1730may be a resistive memory that is used as a data storage memory instead of a flash memory.

The SCM1730may access data in higher speed compared with a flash memory. For example, in a PC in which the CPU1710operates at a frequency of 4 GHz, a resistive memory being a type of SCM1730may provide an access speed higher than a flash memory. Thus, the memory system1700including the SCM1730may provide a relatively higher access speed than a memory system including a flash memory.

FIG. 18is a block diagram schematically illustrating a memory system in which a synchronous DRAM is replaced with a storage class memory using a resistive memory, according to an embodiment of the inventive concept. Referring toFIG. 18, a memory system1800may include a CPU1810, a storage class memory (SCM)1820, and a flash memory1830. The SCM1820may be used as a main memory instead of a synchronous DRAM (SDRAM).

Power consumed by the SCM1820may be less than that consumed by the SDRAM. A main memory may take about 40% of a power consumed by a computing system. For this reason, a technique of reducing power consumption of a main memory has been developed. Compared with the DRAM, the SCM1820may on average reduce 53% of dynamic energy consumption and about 73% of energy consumption due to power leak. Thus, the memory system1800including the SCM1820may reduce power consumption compared with a memory system including an SDRAM.

FIG. 19is a block diagram schematically illustrating a memory system in which a synchronous DRAM and a flash memory are replaced with a storage class memory using a resistive memory according to an embodiment of the inventive concept. Referring toFIG. 19, a memory system1900may include a CPU1910and a storage class memory (SCM)1920. The SCM1920may be used as a main memory instead of a synchronous DRAM (SDRAM) and as a data storage memory instead of a flash memory. The memory system1900may be advantageous in the light of data access speed, low power, cost, and use of space.

A resistive memory device according to the inventive concept may be packed by at least one selected from various types of packages such as PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDI2P), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), and the like.

A resistive memory device according to an embodiment of the inventive concept may be applied to various products. The resistive memory device according to an embodiment of the inventive concept may be applied to storage devices such as a memory card, a USB memory, a solid state drive (SSD), and the like, as well as to electronic devices such as a personal computer, a digital camera, a camcorder, a cellular phone, an MP3 player, a PMP, a PSP, a PDA, and the like.

Referring to the figures described above, in some embodiments, the source lines SLs are tied to a ground GND potential, and this is the configuration that is assumed for the circuit diagram illustrated in these figures. It will be understood, however, that in some embodiments, the source lines SLs can be tied to a power supply potential VDD, and the regular VDD potential can be tied to the ground GND potential. In such case, each PMOS type transistor is replaced with an NMOS type transistor, and each NMOS type transistor is replaced with a PMOS type transistor.

The example embodiments disclosed herein provide a resistive type memory with enhanced operating temperature range. This is achieved using a simple and small die area, and including a heat element and a switch transistor. Reliability is improved and breakdown is prevented at low temperatures. Lower voltage supplies can be used, thereby resulting in reduced power loss. Once the chip is operating normally above the temperature threshold Trefafter power up, the heat generation response is much faster than the temperature drop speed. There is no additional writing delay because the writer is not disabled after the write enable signal has been asserted.

Moreover, the heat generated by the chip and surrounding components generally keeps the die temperature above the threshold after the pre-heat phase, and therefore, generally no extra power is needed to heat the die because the heaters can be left off. Nevertheless, if the die temperature happens to fall below the temperature threshold at any time, the heaters can be re-enabled to ensure efficient and reliable operation of the resistive type memory cells.

The above embodiments of the inventive concept are illustrative and not limitative. Various alternatives and equivalents are possible. The embodiments of the inventive concept are not limited by the type or the number of the magnetic random access memory cells included in a memory array. The embodiments of the inventive concept are not limited by the type of transistor, PMOS, NMOS or otherwise, included to operate the sense amplifier circuit, select a magnetic tunnel junction device, or the like. The embodiments of the inventive concept are not limited by the type of logic gates, NOR or NAND included to implement logical column selection or to produce control logic for the sense amplifier circuit. The embodiments of the inventive concept are not limited by the type of integrated circuit in which the inventive concept may be disposed. Nor are the embodiments of the inventive concept limited to any specific type of process technology, e.g., CMOS, Bipolar, or BICMOS that may be included to manufacture a memory. The embodiments described herein have been directed to sense amplifier circuits but are not limited thereto. The embodiments described herein may be included wherever improving response times, noise immunity characteristics, low voltage operation capabilities, larger voltage headroom features, or fewer sense errors, or the like, may be found useful.

Other similar or non-similar modifications can be made without deviating from the intended scope of the inventive concept. Accordingly, the inventive concept is not limited except as by the appended claims.