Apparatus and method for high speed voltage regulation

A high-speed voltage regulating apparatus and a method for high-speed voltage regulation. The apparatus includes: (A) a regulator, adapted to provide a regulated voltage; (B) switching circuitry, connected to the regulator, adapted to either (i) connect the regulator to an output node or (ii) disconnect the regulator from the output node; whereas the output node is connected to a dynamic power consuming device and to a load capacitor; (C) control logic, connected to the regulator, adapted to receive at least an indication reflecting a voltage of the output node and to control the switching circuitry such that the regulator is disconnected from the output node to facilitate a decrease in the voltage of the output node. The method includes: (A) determining whether to (i) decrease a voltage of an output node, (ii) to maintain the voltage of the output node or to (iii) increase the voltage of the output node; (B) allowing a voltage of an output node to decrease by disconnecting a regulator from the output node; whereas the output node is coupled to a dynamic power consuming device and to a load capacitor; and (C) providing a regulated voltage corresponding to a required voltage of the output node, if determining to maintain the voltage of the output node or to increase the voltage of the output node.

FIELD OF THE INVENTION

The present invention relates to methods and systems for high-speed voltage regulation and especially relates to a high-speed regulator that supports dynamic voltage scaling.

BACKGROUND OF THE INVENTION

Mobile devices, such as but not limited to personal data appliances, cellular phones, radios, pagers, lap top computers, and the like are required to operate for relatively long periods before being recharged. These mobile devices usually include one or more processors as well as multiple memory modules and other peripheral devices.

In order to reduce the power consumption of mobile devices various power consumption control techniques were suggested. A first technique includes reducing the clock frequency of the mobile device. A second technique is known as dynamic voltage scaling (DVS) or alternatively is known as dynamic voltage and frequency scaling (DVFS) and includes altering the voltage that is supplied to a processor as well as altering the frequency of a clock signal that is provided to the processor in response to the computational load demands (also referred to as throughput) of the processor. Higher voltage levels are associated with higher operating frequencies and higher computational load but are also associated with higher energy consumption.

U.S. patent application 20040052098 of Burstein et al., titled “digital voltage using current control”; U.S. patent application 20030139927 of Gabara, et al., titled “Block processing in a maximum a posteriori processor for reduced power consumption”; U.S. patent application 20020000797 of Burstein et al., titled “Switching regulator with capacitance near load”; U.S. patent application 20040025068 of Gary et al., titled “Methodology for coordinating and tuning application power”; U.S. patent application 20010038277 of Burstein et al., titled “Digital voltage regulator using current control”, and “A Dynamic Voltage Scaled Microprocessor System”, T. D. Burd, T. A. Pering, A. J. Stratakos and R. W. Brodersen, IEEE Journal Journal of solid-state circuits, Vol. 35, No. 11, November 200, all being incorporated herein by reference, provide a brief review of some dynamic voltage scaling techniques.

FIG. 1illustrates the supply voltage that is being supplied to a processor (such as the CPU ofFIG. 2) during the execution of various tasks as well during an idle period. For simplicity of explanation the supply voltage is illustrated as a sequence of ramps, and the transition periods between voltage ramps are not illustrated. The transition periods are very short, and typically do not exceed few milliseconds.

During a first time period ΔT111that starts at T0and ends at T1, the processor executes a very high throughput task and accordingly receives a very high frequency clock signal and a very high level supply voltage Vvery_high.

During a second time period ΔT212that starts at T1and ends at T2, the processor executes a high throughput task and accordingly receives a high frequency clock signal and a high level supply voltage Vhigh.

During a third first time period ΔT313that starts at T2and ends at T3, the processor executes a medium throughput task and accordingly receives a medium frequency clock signal and a medium level supply voltage Vmedium.

During a fourth time period ΔT414that starts at T3and ends at T4, the processor is idle and accordingly receives a very low frequency clock signal (or alternatively does not receive a clock signal) and a very low (even zero) level supply voltage Vvery_low.

During a fifth time period ΔT515that starts at T4and ends at T5, the processor executes a high throughput task and accordingly receives a high frequency clock signal and a high level supply voltage Vhigh.

It is noted that the voltage supplied to the processor is decreased (usually during a very short time period) at about T1, T2and T3and is increased at about T4.

FIG. 2illustrates a prior art device20that includes multiple power consuming devices such as a central processing unit (CPU), SRAM and I/O card, collectively denoted30, a frequency regulator40, a voltage regulator50, an output inductor34and a load capacitor32.

The voltage regulator50receives a desired frequency from the frequency regulator40, a 1 Mhz clock signal and provides a frequency error signal to a digital filter that in turn sends control signals to a FET control and drivers unit52that applies a pulse-width/pulse frequency modulation scheme to control a pair of power FET transistors Mn56and Mp54. The gates of Mn56and Mp54are connected to the FET control and drivers unit52, that turns them on and off in response to said modulation scheme. The source of Mp54is connected to a battery60and the drain of Mp54is connected to the drain of Mn56. The drain of Mn56is grounded.

The drains of Mn56and Mp54are connected at an output node of the regulator. This output node is connected to a first end of an inductor34. The other end of the inductor34is connected to a first end of a load capacitor32. The second end of the load capacitor32is grounded. The second end of the inductor34is also connected to the frequency regulator40and to devices30.

The load capacitor is relatively large (about 5.5 Microfarad). Typically, such as load capacitor30is used to smooth the voltage supplied to the processor. In various mobile devices the load capacitor is also used as a power reservoir that provides power during short supply power failure. Such a power reservoir is described at U.S. Pat. No. 6,226,556 of Itkin et al., which is incorporated herein by reference.

Referring back to the prior art device20, the regulator50can increase or decrease the regulated voltage supplied to its output node, and thus may dynamically alter the voltage supplied to the CPU and other devices.

In some prior art regulators a decrement in the regulated voltage involves decreasing the charge of the load capacitor32by draining said charge to the ground. Thus each voltage decrement involves power loss.

The prior art device20also loses energy as a result of removing charge from the load capacitor to a battery bypass capacitor (not shown inFIG. 2).

There is a need to provide an efficient method and apparatus for dynamically providing regulated voltage to a processor.

SUMMARY OF THE PRESENT INVENTION

Dynamically altering the voltage supplied to a processor in response to the computational load of the processor and operating frequency associated with said load. The supplied voltage is decreased by allowing a load capacitor to supply the required voltage and is increased by providing an appropriate regulated voltage.

A high-speed voltage regulating apparatus that includes: (A) a regulator, adapted to provide a regulated voltage; (B) switching circuitry, connected to the regulator, adapted to either (i) couple the regulator to an output node or (ii) disconnect the regulator from the output node; whereas the output node is connected to adynamic power consuming device, such as but not limited to a processor, and to a load capacitor; and(C) control logic, connected to the regulator,adapted to receive at least an indication reflecting a voltage of the output node and to control the switching circuitry such that the regulator is disconnected from the output node to facilitate a decrease in the voltage of the output node.

A method for high-speed voltage regulation that includes: (A) determining whether to (i) decrease a voltage of an output node, (ii) to maintain the voltage of the output node or to (iii) increase the voltage of the output node; (B) allowing a voltage of an output node to decrease by disconnecting a regulator from the output node; whereas the output node is coupled to a dynamic power consuming device, such as but not limited to a processor, and to a load capacitor; and (C) providing a regulated voltage corresponding to a required voltage of the output node, if determining to maintain the voltage of the output node or to increase the voltage of the output node.

A mobile device that includes: (A) a battery; (B) a dynamic power consuming device, such as but not limited to a processor, that is connected to an output node; (C) a regulator, connected to the battery, whereas the regulator is adapted to provide a regulated voltage; (D) switching circuitry, connected to the regulator, adapted to either (i) couple the regulator to the output node or (ii) disconnect the regulator from the output node; whereas the output node is further connected to a load capacitor; and a (E) control logic, connected to the regulator, adapted to receive at least an indication reflecting a voltage of the output node and to control the switching circuitry such that the regulator is disconnected from the output node to facilitate a decrease in the voltage of the output node.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following description related to supplying voltage to a processor. Those of skill in the art will appreciate that the disclosed systems and methods can be applied mutates mutandis to supplying voltage to other dynamic power consuming devices.

It is further noted that although the disclosed apparatus includes a buck switch that other switching elements and other configurations can be applied, including boost configurations and buck-boost configurations.

The term processor refers to an entity that is capable of performing various tasks that are associated with different computational loads. The processor can be a RISC processor, a general-purpose processor, a digital signal processor, a controller, a scalar processor and the like.

It is noted that typically the voltage regulator provides a supply voltage to multiple devices such as memory banks, displays and the like but for simplicity of explanation the drawings and associated description refer to a processor.

The term “dynamic power consuming device” refers to a device that can operate at different power consuming modes, especially in response to throughput demands that can vary over time. Such a device can be a processor that can operate at different voltage levels and different operational frequencies, to support tasks associated with different computational loads.

FIG. 3illustrates an apparatus100according to an embodiment of the invention. Apparatus100includes a voltage regulator110, a switching circuitry such as switch120and a buck switch that in turn includes NMOS transistor124and PMOS transistor122. Apparatus100further includes a load capacitor140and control logic160.

Apparatus100includes an output node102that is connected to the load capacitor140, to a processor150and to the output of the buck switch. The voltage of the output node is denoted Vout130and also referred to as “output voltage” of as the output voltage of apparatus100.

Switch120is connected between the voltage regulator110and an input of the buck switch. The input of the buck switch is connected to the gates of transistors124and122. The source of PMOS transistor122is connected to a battery128and its drain is connected to the drain of the NMOS transistor124to form an output node102of apparatus100. The drain of the NMOS transistor124is grounded.

The output node102is connected to a device such as processor150and also to one end of the load capacitor140. The other end of the load capacitor is grounded. The output node102is also connected to voltage regulator110and optionally to the control unit160to provide one or more feedback signals to said latter devices.

The voltage regulator110can be any prior art device that is capable of providing a regulated voltage. It receives as inputs a signal representative of the voltage (Vout200) of the output node102of apparatus100, but may also receive Vout itself. The regulator further receives control signals such as but not limited to Vreq204that determines a desired Vout. The voltage regulator110or the control unit160may determine the relationship between a current value of Vout and a next value of Vout. For example, referring to the example set forth atFIG. 1, at T1Vout has to be altered from Vvery_high to Vout.

Switch120is controlled by control logic160and can either connect the output of voltage regulator110to the buck switch or disconnect the buck switch from the voltage regulator110. Switch120can be implemented by a transistor, although this is not necessarily so. Conveniently, when the buck switch is disconnected from the voltage regulator110the NMOS transistor124is OFF, thus preventing the load capacitor140to discharge through the NMOS transistor124.

When switch120is closed the regulated voltage supplied by voltage regulator110is provided, via the buck switch, to the output node102of apparatus100. When switch120is open the voltage regulator110is disconnected from the output node102and the voltage of the output node is decremented by the discharging of load capacitor140by processor150.

The output node102is connected to the control unit160that may stop the decrement of the output voltage whenever the output voltage Vout reaches a voltage threshold. The voltage threshold can be dynamically set in response to the computational load of processor150. Referring again toFIG. 1, at T1, when the output voltage is altered from Vvery_high to Vhigh the voltage threshold is set to Vhigh to make sure that Vout does not fall below Vhigh, so that during the second time period ΔT2the processor can operate at an appropriate frequency.

According to an embodiment of the invention the apparatus100is also capable of controlling the discharge rate of the load capacitor140and especially to limit the discharge rate of the load capacitor140. This includes supplying a to the output node102of apparatus100a current from PMOS transistor122that is ON when the switch120disconnects the buck switch from the voltage regulator110. The current charges the load capacitor140as well as being provided to the processor150.

A limitation of the discharge rate of the load capacitor140may be required in order to simplify the control scheme of the switching circuitry and especially to prevent a scenario in which the apparatus100is not capable of preventing a decrement of Vout below a voltage threshold due to a fast discharge of the load capacitor140and timing limitations associated with the control scheme.

Apparatus100is usually included within a mobile device, such as but not limited to a PDA or a cellular phone, and is connected to the battery of that mobile device.

FIG. 4is a timing diagram that illustrates multiple transition periods, according to an embodiment of the invention.

During a first transition period Ttr_first221the supply voltage is increased from Vvery_low to V_high. Ttr_first221starts at T10230and ends at T11231. Conveniently, during this first transition period221the processor150receives regulated voltage that is gradually incremented from a current value of Vvery_low to a next value of Vvery_high, by incremental steps of ΔV. It is noted that the voltage can be incremented by other manners. Ttr_first221is followed by a relatively long intermediate period (illustrated by a dashed line) during which a regulated voltage of Vvery_high is provided to processor150.

During a second transition period Ttr_second222the supply voltage is decreased from Vvery_high to V_high. At the beginning of that period (T12232) the voltage regulator110is disconnected from the output node102and the processor150discharged the load capacitor at a current that is denoted Ihigh. Accordingly, the voltage Vout of the output node exponentially decreases. It is assumed that it decreases to Vhigh (at time T13233) before Ttr_Second222ends. At that point the apparatus100, that monitors the output voltage, connects the voltage regulator110to the buck switch so that a voltage of Vhigh is provided to the processor from T13233.

The second transition period is followed by an intermediate period through which Vout is maintained at Vhigh. The second intermediate period ends at T14234and a third transition period Ttr_third223begins.

During the Ttr_third223Vout is exponentially decreased but does not reach Vlow, thus during the whole period the voltage regulator110is disconnected.

According to an embodiment of the invention if the decrement rate of Vout is too slow (for example is below a predefined discharge rate) then Vout can be further decremented even after the transmission period and any following intermediate period ends.

FIG. 5is a flow chart illustrating method300for high-speed voltage regulation, according to an embodiment of the invention. Method300starts by stage310of determining whether to (i) decrease a voltage of an output node, (ii) to maintain the voltage of the output node or to (iii) increase the voltage of the output node. Referring toFIG. 3, the control logic160determines a target Vout level and sends voltage regulator110appropriate control signals.

Stage310is followed by stage320if stage310determines to decrease Vout. Stage320includes allowing a voltage of an output node to decrease by disconnecting a regulator from the output node; whereas the output node is coupled to a dynamic power consuming device such as but not limited to a processor and to a load capacitor. Referring again toFIG. 3the processor150is connected to load capacitor140that is discharged while providing the processor150with the required voltage and current. It is noted that during this stage the voltage regulator110is disconnected from the output node102and that it may be re-connected when Vout reaches a voltage threshold.

Stage310is followed by stage330if stage310determines to maintain or to increment Vout. Stage330includes providing a regulated voltage corresponding to a required voltage of the output node. Referring toFIG. 3, during this stage switch120is closed.

Stage320conveniently includes stage340of monitoring the decrement of the voltage of the output node and stage350of determining if the voltage of the output node decreases to substantially reach a voltage threshold. The voltage threshold can be dynamically set to a required voltage level in response to characteristics of dynamic power consuming device, such as computational load of a processor.

Stage350is followed by stage360of providing a regulated voltage that substantially equals a voltage threshold when the voltage of the output node decreases to substantially reach the voltage threshold. Stage350is followed by stage340while the voltage of the output node is above the voltage threshold.

Conveniently, stage320also includes controlling a rate of decrement of the voltage of the output node by supplying a charging current to at least the load capacitor. A portion of that current can flow through the processor150while another portion charges the capacitor140.