Burst mode clock data recovery device and method thereof

A burst mode clock data recovery device includes a clock data recovery loop, a frequency tracking loop, a frequency tracking loop, and a fast-locking unit. The clock data recovery loop receives a sampling clock signal and a data signal and uses the sampling clock signal to lock the data signal to generate a recovery clock signal. The frequency tracking loop tracks a frequency of the recovery clock signal to generate a frequency detection signal associated with the recovery clock signal. The phase lock loop receives the frequency detection signal and locks the recovery clock signal in a reference clock. The fast-locking unit generates a fast-locking signal according to the recovery clock signal and a first phase detection signal to allow the clock data recovery loop to quickly lock the data signal after the transition from a stall mode to the burst mode.

BACKGROUND

a. Field of the Invention

The invention relates generally to an electronic device, and more particularly, to a burst-mode clock data recovery device and method.

b. Description of the Related Art

FIG. 1shows a schematic diagram illustrating a conventional clock data recovery device. As shown inFIG. 1, the clock data recovery device100includes a phase detector101, a charge pump102, a voltage-controlled oscillator103, and a low-pass filter104. The phase detector101detects a phase difference among data signals data1to generate a phase detection signal de according to a recovery clock signal ckr. The charge pump102generates a voltage control signal vc1, according to the phase detection signal de. The voltage-controlled oscillator103generates the recovery clock signal ckr according to the voltage control signal vc1, and the voltage control signal vc1is low-pass filtered by the low-pass filter104.

However, since the clock data recovery device100is required to relock the phase and frequency when exiting a stall mode, it may cost considerable time and thus lower the speed.

Therefore, it is desirable to provide a clock data recovery device and a method capable of fast locking phase and frequency.

BRIEF SUMMARY OF THE INVENTION

The invention relates, in one embodiment, to a clock data recovery device and method capable of quickly locking phase and frequency under a burst mode.

In one aspect, a clock data recovery device includes a clock data recovery loop, a frequency tracking loop, a frequency tracking loop, and a fast-locking unit. The clock data recovery loop receives a sampling clock signal and a data signal and uses the sampling clock signal to lock the data signal to generate a recovery clock signal. The frequency tracking loop is coupled to the clock data recovery loop for tracking a frequency of the recovery clock signal to generate a frequency detection signal associated with the recovery clock signal. The phase lock loop is coupled to the clock data recovery loop and the frequency tracking loop for receiving the frequency detection signal and locking the recovery clock signal in a reference clock. The fast-locking unit is coupled to the clock data recovery loop for generating a fast-locking signal under a burst mode according to the recovery clock signal and a first phase detection signal to allow the clock data recovery loop to quickly lock the data signal after the transition from a stall mode to the burst mode.

According to another aspect of the invention, a method for locking a recovery clock signal includes the steps of: setting an initial fractional number for generating a recovery clock signal locked in an initial frequency; receiving a data signal; tracking the recovery clock signal to generate an accurate fractional number; entering a stall mode, where the recovery clock signal and the data signal still having an identical frequency when the data signal stops being transmitted; scanning a plurality of the recovery clock signals when the data signal turns to be transmitted again and adjusting a phase of a sampling clock signal relying on information of phase-leading or phase-lag of the plurality of the recovery clock signals with respect to the data signal to align with a temporal position of the data signal and generate a preset phase; and generating a sample clock for the data signal according to the preset phase when entering a burst mode.

According to another aspect of the invention, a method for locking a recovery clock signal includes the steps of: setting an initial fractional number for generating a recovery clock signal locked in an initial frequency; receiving a data signal; tracking the recovery clock signal to generate an accurate fractional number; entering a stall mode, where the recovery clock signal and the data signal still having an identical frequency when the data signal stops being transmitted; when the data signal turns to be transmitted again, using multiple phases of multiple recovery clock signals generated by a voltage-controlled oscillator to fetch the data signal to obtain multiple edge positions and middle positions of data of the data signal, and selecting one of the multiple phases as a preset phase according to the multiple edge positions and middle positions of data; and generating a sample clock for the data signal according to the preset phase when entering a burst mode.

According to the above embodiments, since a preset phase may serve as an initial phase for an oscillation frequency of a clock data recovery circuit, the clock data recovery loop can be quickly locked to resolve the problems of conventional designs.

Other features and advantages of the present invention will immediately be recognized by persons of ordinary skill in the art with reference to the attached drawings and detailed description of exemplary embodiments as given below.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2shows a schematic diagram illustrating a burst mode clock data recovery device according to an embodiment of the invention. As illustrated inFIG. 2, the burst mode clock data recovery device200may include a clock data recovery loop201, a phase lock loop202, and a frequency tracking loop203.

The clock data recovery loop201may include a first phase detector201a,a first charge pump201b,a voltage-controlled oscillator201c,a first low-pass filter201d,and a fast-locking unit201e.The clock data recovery loop201may receive and lock a data signal data2to generate a recovery clock signal ckr according to a sampling clock signal lc generated by the fast-locking unit201e.

The first phase detector201amay detect a phase difference between a sampling clock signal1cand an input data signal data2to generate a first phase detection signal de1. The first charge pump201bmay generate a voltage control signal vc2according to the first phase detection signal de1. The voltage-controlled oscillator201cmay generate a recovery clock signal ckr according to the voltage control signal vc2. The first low-pass filter201dmay perform a low-pass filtering operation on the voltage control signal vc2. Further, based on the recovery clock signal ckr and the first phase detection signal de1, the fast-locking unit201emay, under a burst mode, generate a fast-locking signal lc to allow the clock data recovery loop201to precisely lock phase and frequency of the data signal data2after the transition from a stall mode to the burst mode.

The phase lock loop202may include a second phase detector202a,a second charge pump202b,and a fractional-N frequency divider202c.The phase lock loop202may lock the recovery clock signal ckr in a reference clock ck_ref. The second phase detector202amay receive a reference clock ck_ref and a frequency division signal sd and may generate a second phase detection signal de2according to a phase difference between the reference clock ck_ref and the frequency division signal sd. The second charge pump202bmay generate a voltage control signal vc2according to the second phase detection signal de2. The fractional-N frequency divider202cmay receive the recovery clock signal ckr and a filtered frequency detection signal sff and generate a frequency division signal sd according to the recovery clock signal ckr and the filtered frequency detection signal sff.

The frequency tracking loop203may include a frequency detector203aand a second low-pass filter203b.The frequency tracking loop203may track the frequency of the recovery clock signal ckr. The frequency detector203amay receive the reference clock ck_ref and detect the frequency of the recovery clock signal ckr to generate a frequency detection signal sf according to the reference clock ck_ref. The second low-pass filter203bmay filter the frequency detection signal sf to generate a filtered frequency detection signal ssf. Note the filtered frequency detection signal ssf is associated with the recovery clock signal ckr and may reflect the recovery clock signal ckr and the adjustment performed thereon.

FIG. 6shows a flow chart illustrating operations for a burst mode clock data recovery device200according to an embodiment of the invention. The fast locking procedure may include the following steps.

Step S604: Set an initial fractional number for a fractional-N frequency divider203e, and turn off a clock data recovery loop201and a fast-locking unit201e.At this time, a first phase detector201a,a first charge pump201b,a first low-pass filter201dand the fast-locking unit201ein the clock data recovery loop201are all in an off state.

Step S606: Turn on a phase lock loop202, where a data signal data2is not input into the phase lock loop202until the phase lock loop202is locked. A second phase detector202of the phase lock loop202may receive a reference clock ck_ref and a frequency division signal sd with an initial value. The phase of an output second detection signal de2may be locked in the phase of the reference clock ck_ref, and the second charge pump202bmay generate a voltage control signal vc2according to the second detection signal de2. The voltage control signal vc2controls a voltage-controlled oscillator201cto allow the voltage-controlled oscillator201C to operate at an initial preset frequency. Then, the data signal data2begins to enter the first phase detector201aof the clock data recovery loop201.

Step S608: Turn off the phase lock loop202and turn on the clock data recovery loop201. At this time, the fast-locking unit201eis still in an off state, and the second phase detector202a,the second charge pump202band the fractional-N frequency divider202cof the phase lock loop202are in an off state. In comparison, the clock data recovery loop201except for the fast-locking unit201ebegins to operate. In one embodiment, the first phase detector201aof the clock data recovery loop201receives the data signal data2to generate a first detection signal de1. At this time, a sampling clock signal lc is set to have an initial constant phase difference with respect to a recovery clock signal ckr. Then, the first charge pump201breceives the first detection signal de1to generate a voltage control signal vc2. The voltage-controlled oscillator201cgenerates the recovery clock signal ckr according to the voltage control signal vc2, thus enabling the operating fast-locking unit201eto generate a sampling clock signal lc to lock the data signal data2.

Step S610: Turn on a frequency tracking loop203. In one embodiment, the frequency detector203amay receive the reference clock ck_ref and detect a frequency of the recovery clock signal ckr according to the reference clock ck ref to generate a frequency detection signal sf. The second low-pass filter203bmay filter the frequency detection signal sf to generate a filtered frequency detection signal ssf provided for the fractional-N frequency divider202.

Step S612: Generate an accurate fractional number. In one embodiment, the fractional-N frequency divider202may generate the accurate fractional number according to the filtered frequency detection signal ssf.

Step S614: Enter a stall mode when the data signal data2stops entering the clock data recovery loop201. When the burst mode clock data recovery device200is turned off according to preset criteria, the clock data recovery loop201is turned off, the frequency tracking loop203is turned off and the phase lock loop202is turned on.

Step S616: Enter a burst mode when the data signal data2recovers to enter the clock data recovery loop201. At this time, the fast-locking unit201eis turned on to select an optimized phase, and the clock data recovery loop201is still in an off state.

In one embodiment, as shown inFIG. 3A, the fast-locking unit201eincludes a fast-locking logic201e1and a phase interpolator201e2.

The fast-locking unit201e1relies on a first phase detection signal de1that indicates phase-leading or phase-lag of a sampling clock signal lc to adjust a phase of the interpolator201e2, so that the sampling clock signal lc may be aligned with a temporal position of the data signal data2. For example, an optimized temporal position may be found by scanning multiple interpolated phases. As illustrated inFIGS. 3A, 3B and 3C, in one embodiment, the phase interpolator201e2performs interpolation on the recovery clock signal ckr to generate a sampling clock signal lc, and the sampling clock signal lc may have sampling edges such as levels D0, E0, D1shown inFIG. 3C. The first phase detector201adetects phases of a sampling clock signal lc and an input data signal data2to generate a first phase detection signal de1. Then, the fast-locking logic201e1of the fast-locking unit201ereceives the first phase detection signal de1of the first phase detector201ato find out an optimized phase and thus generate a phase signal phase_ctrl. The phase interpolator201e2receives the phase signal phase_ctrl to generate the sampling clock signal lc. For example, as shown inFIG. 3C, assume the sampling clock signal lc samples the data signal data2at a position adjacent to a sampling edge to obtain values of Dn=1, En=1 and Dn+1=0, then the first phase detector201amay determine whether the sampling clock signal lc is phase-lead or phase-lag, and the fast-locking unit201e1may advance or lag a phase of the sampling clock signal lc (such as by adjusting the phase signal phase_ctrl). In this embodiment, the phase of the sampling clock signal lc may satisfy the condition: Phase_ctrl(n)=phase_ctrl(n−1)+step, where phase_ctrl(n−1) denotes a current phase value, phase_ctrl(n) denotes a succeeding phase value of the sampling clock signal lc, and step denotes a phase adjustment value. Note a phase-leading sampling clock signal lc results in a positive value of “step”, and a phase-lag sampling clock signal lc results in a negative value of “step”. In this embodiment where the three sampling values adjacent to a sampling edge are Dn=1, En=1 and Dn+1=0, it is determined that the sampling clock signal lc needs to be lagged, as indicated in an elliptical dashed circle shown inFIG. 3B.

Accordingly, after the transition from a stall mode to a burst mode of the clock data recovery device200, the fast-locking unit201emay use a phase obtained in advance to select a phase of the sampling clock signal lc with respect to the recovery clock signal ckr to achieve fast-locking of the clock data recovery loop201.

In an alternate embodiment, the fast-locking unit201emay be an oversampling unit. Since the voltage-controlled oscillator201cgenerates multiple recovery clock signals ckr having multiple phases such as eight phases, the information about edge positions and middle positions of data can be obtained relying on the multiple phases of the recovery clock signals ckr. Therefore, an optimized value can be obtained according to the multiple edge positions and middle positions of data to find out an optimized phase of the multiple phases, with the optimized phase serving as an initial phase of the sampling clock signal lc.

In one embodiment, as shown inFIG. 4A, the fast-locking unit201emay include an oversampling unit400and a fast-locking logic410. The oversampling unit400includes a flip-flop circuit401, a phase detector402, and a multiplexer403. The flip-flop circuit401includes multiple flip-flops401a-401n.In one embodiment, assume the oversampling unit400uses eight sampling phases P1, P2, P3, P4, P5, P6, P7and P8of eight recovery clock signals ckr to sample one data signal data2during a time length1UI, eight sampled phases Q1, Q2, Q3, Q4, Q5, Q6, Q7and Q8are obtained. The fast-locking logic410receives the sampled phases Q1-Q8to generate a selection signal Sel according to preset criteria. The phase detector402detects the sampled phases Q1-Q8and recognizes respective correspondence relationships between the sampled phases Q1-Q8and the data signals d1-d8to generate result signals d1/up1/dn1-dm/upm/dnm that correspond to different positions of each of the eight data signals, such as an edge position and a middle position of data.

In one embodiment, as shown inFIG. 4C, the phase detector402may include multiple sub phase detector402a-402hthat are arranged and provided with signals in an order indicated inFIG. 4C. For example, the first sub phase detector402areceives sampled phases Q1and Q5to generate a result signal d1/up1/dn1whose truth table is shown inFIG. 4D. For example, in case Q1(n)=0(data(n)=0), Q5(n)=1(edge(n)=1) and Q1(n+1)=1(data(n+1)=1), it can be determined that phase Q1is phase-lag compared with the data signal data2; that is, up(n)=1 and dn(n)=0.

Thereafter, the multiplexer403receives result signals d1/up1/dn1-dm/upm/dnm and selects one of the result signals d1/up1/dn1-dm/upm/dnm according to a selection signal sel to generate an output signal data_out/up/dn serving as a sampled data signal data_out and an input signal up/dn for the first charge pump201b.Note, in one embodiment, the criteria for the selection of result signals d1/up1/dn1-dm/upm/dnm is to determine which result signal is nearest a value of a data signal corresponding to a middle position or other position of the data signal. Under the circumstance, after the transition from a stall mode to a burst mode of the clock data recovery device200, the fast-locking unit201emay use a phase obtained in advance to serve as an initial phase of the sampling clock signal lc to achieve fast locking of the clock data recovery loop201.

Step S618: Turn off the fast-locking unit201e,turn on the clock data recovery loop201, and turn off the phase lock loop202.

Step S620: Optionally decide whether to go to Step S610to turn on the frequency tracking loop203.

FIG. 5shows a schematic diagram illustrating a burst mode clock data recovery device500according to another embodiment of the invention. As illustrated inFIG. 5, the second low-pass filter203bshown inFIG. 2may be omitted from a clock data recovery device under certain conditions, such as in the case that the signal quality is not strictly demanded. The circuit architecture and operation principle of the burst mode clock data recovery device500is similar to the clock data recovery device200shown inFIG. 2, thus not explaining in detail here.

According to the above embodiments, since the fast-locking unit may select a phase in advance and select a voltage control signal corresponding to the selected phase, a voltage-controlled oscillator or a phase interpolator may generate the selected phase serving as an initial phase for an oscillation frequency of a clock data recovery circuit. As a result, the clock data recovery loop can be quickly locked to resolve the problems of conventional designs.