THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

A 3D semiconductor device may include a stack structure and a vertical channel structure. The stack structure may include a first insulation pattern, a lower conductive pattern and a second insulation pattern. The lower conductive pattern may be arranged on the first insulation pattern. The second insulation pattern may be arranged on the lower conductive pattern. The first insulation pattern may have a thickness thicker than a thickness of the second insulation pattern. The vertical channel structure may be arranged in the stack structure. The lower conductive pattern may have an upper surface directly in contact with a lower surface of the second insulation pattern.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2022-0034065, filed on Mar. 18, 2022, in the Korean intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor device and a method of manufacturing the semiconductor device, more particularly, to a three-dimensional semiconductor device and a method of manufacturing the three-dimensional semiconductor device.

2. Related Art

An integration degree of a semiconductor device may be mainly determined by an occupying area of a unit memory cell. Recently, as integration degree improvements of the semiconductor device including a single memory cell on a substrate may have been come to limits, a three-dimensional (3D) semiconductor device including memory cells stacked on a substrate may be proposed. Further, in order to improve operational reliability of the 3D semiconductor device, various structures and fabrication methods may be developed.

SUMMARY

According to examples of embodiments, there may be provided a three-dimensional (3D) semiconductor device. The 3D semiconductor device may include at least one stack structure and at least one vertical channel structure. The stack structure may include a first insulation pattern, a lower conductive pattern and a second insulation pattern sequentially stacked. The first insulation pattern may include a first thickness, and the second insulation pattern includes a second thickness different from the first thickness. An upper surface of each of the lower conductive patterns may be directly in contact with a lower surface of each of the second insulation patterns

According to examples of embodiments, there may be provided a three-dimensional (3D) semiconductor device. The 3D semiconductor device may include a stack structure and at least one vertical channel structure. The stack structure may include at least one unit memory block. The unit memory block may include a first insulation pattern, a lower word line, a second insulation pattern and an upper word line at least once sequentially stacked in a cell region and a contact area. The vertical channel structure may include a data storage layer formed through the stack structure in the cell region. The first insulation pattern in the cell region may have a thickness thicker than a thickness of the second insulation pattern in the cell region.

According to examples of embodiments, there may be provided a method of manufacturing a 3D semiconductor device. In the method of manufacturing the 3D semiconductor device, a first insulating interlayer and a sacrificial layer may be alternately stacked at least once to form a stack structure. The sacrificial layer may be selectively removed to form an opening between the first insulating interlayers. A conductive layer may be formed on an inner surface of the opening. A second insulating interlayer may be formed in the opening with the conductive layer. The second insulating interlayer may have a thickness different from a thickness of the first insulating interlayer. A hole may be formed through the stack structure. The conductive layer exposed through the hole may be removed to define a word line. A vertical channel structure may be formed in the hole.

DETAILED DESCRIPTION

Various embodiments will be described in greater detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments (and intermediate structures). As such, variations from the configurations and shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected, Thus, the described embodiments should not be construed as being limited to the particular configurations and shapes illustrated herein but may include deviations in configurations and shapes which do not depart from the spirit and scope of the present disclosure as defined in the appended claims. It will be understood that when an element, pattern, surface, or layer etc., is referred to as being “on,” “connected to” or “coupled to” another element, pattern, surface, or layer etc., it can be directly on, connected or coupled to the other element, pattern, surface, or layer etc., or intervening element, pattern, surface, or layer etc., may be present. In contrast, when an element, pattern, surface, or layer etc., is referred to as being “directly on,” “directly connected to,” “directly contacted with” or “directly coupled to” another element, pattern, surface, or layer etc., there are no intervening element, pattern, surface, or layer etc., present

The present disclosure is described herein with reference to cross-section and/or plan illustrations of idealized embodiments of the present disclosure. However, embodiments should not be construed as limiting the concepts. Although a few embodiments will be shown and described, it will be appreciated by those of ordinary skill in the art that changes may be made in these embodiments without departing from the principles and spirit of the present disclosure.

Hereinafter, a 3D semiconductor device of various embodiments may be illustrated in detail with reference to accompanying drawings.

FIGS.1A to1Care views illustrating a 3D semiconductor device in accordance with various embodiments.FIG.1Ais a plan view illustrating the 3D semiconductor device.FIG.1Bis a cross-sectional view taken along a line A-A′ inFIG.1A.FIG.1Cis a cross-sectional view taken along a line B-B′ inFIG.1A.

Referring toFIGS.1A to1C, a 3D semiconductor device may include at least one stack structure ST, at least one vertical channel structure CH and at least one contact plug CT.

The stack structure ST may include a plurality of conductive patterns126and insulation patterns102and118. The insulation patterns102and118may be arranged between the conductive patterns126to electrically isolate the conductive patterns126from each other. The insulation patterns102and118may have different thicknesses. The insulation patterns102and118may include first insulation patterns102and second insulation patterns118. In various embodiments, the stack structure ST may include the first insulation patterns102, the conductive pattern126, the second insulation patterns118, the conductive pattern126and the first insulation pattern102repeatedly stacked in a vertical direction. Hereinafter, the vertical direction may be referred to as a first direction D1.

In various embodiments, the first insulation pattern102may have a thickness T1different from a thickness T3of the second insulation pattern118. For example, the thickness T1of the first insulation pattern102may be thicker than the thickness T3of the second insulation pattern118. For example, the thickness T1of the first insulation pattern102may be about 1.5 times to about 2.5 times the thickness T3of the second insulation pattern118. Further, the thickness T1of the first insulation pattern102may be greater than a sum of thicknesses (THx2) of the adjacent two conductive patterns126and the thickness T3of the second insulation pattern118between the adjacent two conductive patterns126(That is, T1>2TH+T3).

In various embodiments, the first insulation pattern102and the second insulation pattern118may include the same material or different materials. The first insulation pattern102and the second insulation pattern118may include an insulation material such as oxide, nitride, an air gap, etc. For example, the first insulation pattern102and the second insulation pattern118may include at least one of silicon oxide layer, a silicon nitride layer and silicon oxy-nitride layer. Alternatively, the first insulation pattern102and the second insulation pattern118may include the same insulating layer, but different stoichiometric ratios of the first insulation pattern102and the second insulation pattern118may be different. For example, any one of the first and second insulation patterns102and118may include a silicon-rich nitride layer and the other may include a silicon nitride layer that satisfies the stoichiometric ratio of the silicon nitride material. Further, the first insulation pattern102and the second insulation pattern118may include impurities such as n type impurities, p type impurities, carbon, nitrogen, etc. Further, the first insulation pattern102and the second insulation pattern118may have different thicknesses, a permittivity of the first insulation pattern102and a permittivity of the second insulation pattern118may be substantially same. Thus, a capacitance of a capacitor including the first insulation pattern102and the conductive patterns126contacted with the first insulation pattern102and a capacitance of a capacitor including the second insulation pattern118and the conductive patterns126contacted with the second insulation pattern118may be substantially uniform. For example, at least one of the first insulation pattern102and the second insulation pattern118may include any one of a perovskite ternary metal oxide layer such as SrZO3, LaAlO3, CaZrO3, SrTiO3, etc., a binary metal layer such as ZrO3, HfO2, La2O3, Ta2O5, etc., and an amorphous metal oxide layer. At least one of the first and second insulation patterns102and118may include at least one of oxide including silicon oxide and oxide containing a metal, nitride including silicon nitride and silicon oxy-nitride, an insulation material including impurities and an air gap.

The stack structure ST may include a cell region CA and a contact area CTA. The first insulation patterns102and the second insulation patterns118may be formed in the cell region CA and the contact area CTA.

Each of the first insulation patterns102, the conductive patterns126and the second insulation patterns118in the contact area CTA may have a stepped structure having a downwardly protruded shape to secure contact portions of the conductive patterns126, This stepped structure of the contact area CTA may be formed by a slimming process. For example, each of the second insulation patterns118may include a line shape with both end portions118E. At least one end portion118E of each of the second insulation patterns118may be located at the contact area CTA. A thickness of the end portion118E located at the contact area CTA may be greater than thickness T3of the second insulation pattern118except the end portion118E located at the contact area CTA.

As described above, each of the conductive patterns126may have the thickness TH thinner than the thickness T3of the second insulation pattern118. In an embodiment, the thickness TH of the conductive pattern126may be thinner than the thicknesses T1and T3of the first insulation pattern102and the second insulation pattern118to reduce a height of the 3D semiconductor device. Further, in an embodiment, a plurality of the conductive patterns126may be arranged in the 3D semiconductor device having a same height to improve an integration degree of the 3D semiconductor device. The conductive patterns126may include a metal material for example, titanium nitride (TiN), tungsten (W) or molybdenum (Mo). The conductive patterns126may include a doped polysilicon including conductive impurities, but are not limited thereto.

In various embodiments, the conductive pattern126may include a barrier layer and a conductive layer. The barrier layer may include a titanium nitride (TiN) layer, a titanium/titanium nitride (Ti/TiN) layer, etc. The barrier layer may be interposed between the first insulation pattern102and the conductive layer. For example, the conductive layer may include a tungsten material. Meanwhile, when the conductive pattern126may include a molybdenum material, the barrier layer might not be required between the first insulation pattern102and the conductive layer. In the embodiments, the conductive pattern126may correspond to a word line, a drain select line or a source line in a cell string of a NAND memory device.

As described above, the conductive patterns126may be arranged in the cell region CA and the contact area CIA. Each of the conductive patterns126in the cell region CA may be configured to surround the vertical channel structures CH, The conductive patterns126may extend in parallel with each other in a second direction D2.

For example, the conductive pattern126under the second insulation pattern118will be referred to as a lower conductive pattern126L, and the conductive pattern126on the second insulation pattern118will be referred to as an upper conductive pattern126U, referring toFIG.1C.

Further, the lower conductive pattern126L may be used as a lower word line and the upper conductive pattern126U may be used as an upper word line.

The upper conductive pattern126U in the contact area CTA may be extended to cover an upper surface of the second insulation pattern118except for an edge of the end portion118E of the second insulation pattern118. The lower conductive pattern126L may be extended to cover a lower surface of the second insulation pattern118, a side surface of the end portion118E of the second insulation pattern118and the edge of the upper surface of the end portion118E. At that time, the lower conductive pattern126L may extend to the edge of the upper surface of the second insulation pattern118, but may be electrically isolated from the upper conductive pattern126U.

The lower conductive pattern126L and the upper conductive pattern126U may be separated by a cut portion127of the conductive pattern126. The cut portion127may be arranged at the upper surface of the end portion118E of the second insulation pattern118.

The vertical channel structures CH may be formed through the stack structure ST along the first direction D1. The vertical channel structures CH may be formed in the cell region CA, Each of the vertical channel structures CH may have a cylindrical shape. The cylindrical vertical channel structure CH may have a diameter that decreases in the vertical direction or downward vertical direction, as for example shown inFIG.1b. In an embodiment, this decrease in diameter for the cylindrical vertical channel structure CH may be due to a height of the stack structure ST.

In a planar view defined along the second direction D2and the third direction D3substantially perpendicular to the first direction D1, the vertical channel structures CH may include a plurality of first vertical channel structures CH1and a plurality of second vertical channel structures CH2. For example, the first vertical channel structures CH1may be arranged to space apart with a set distance forming first rows 1strow. The second vertical channel structures CH2may be arranged to space apart with the set distance forming second rows 2ndrow. The second vertical channel structure CH2may be arranged between the first vertical channel structures and may be located between adjacent first rows, as shown inFIG.1A.

The first vertical channel structures CH1and the second vertical channel structures CH2may be repeatedly arranged in the first rows and second rows, respectively, but are not limited thereto.

Each of the vertical channel structures CH may include a channel134and memory layers128,130and132configured to surround the channel134. The channel134may include a semiconductor material such as silicon, germanium, a nano-structure, etc. The memory layers128,130and132may be interposed between the channel134and the conductive pattern126, For example, the memory layers128,130and132may include a tunnel insulation layer132, a data storage layer130and a blocking insulation layer128. The tunnel insulation layer132may be configured to surround the channel134. The data storage layer130may be configured to surround the tunnel insulation layer132, The blocking insulation layer128may be configured to surround the data storage layer130. The data storage layer130may store data changed using a Fowler-Nordheim tunneling. In various embodiments, the data storage layer130may include a charge-trapping nitride layer. The blocking insulation layer128may include oxide for blocking a charge. The tunnel insulation layer132may include silicon oxide capable of a charge tunneling.

The adjacent two stack structures ST may be spaced apart from each other by a slit structure SL, In various embodiments, the slit structure SL may include a source contact plug124and insulation spacers120and122. The insulation spacers120and122may be configured to surround an outer surface of the source contact plug124. Alternatively, the slit structure SL may include an insulation material. Further, the slit structure SL may include the insulation spacers120and122without the source contact plug124.

The contact plugs CT may be electrically connected with the conductive patterns126in the contact area CTA, respectively. In various embodiments, the contact plugs CT may be positioned on the second insulation pattern118having the relatively thick thickness, that is, the end portion118E of the second insulation pattern118.

As mentioned above, because the cut portion127may be formed at the end portion118E of the second insulation pattern118, each of the lower conductive patterns126L may extend to the edge of the upper surface of the second insulation pattern118in contact therewith. Thus, the contact plugs CT1and CT2which are respectively contacted with the upper conductive pattern126U and the lower conductive pattern126L in contact with one second insulation pattern118may have a same height,

FIGS.2A to2Care views illustrating a 3D semiconductor device in accordance with various embodiments.FIG.2Ais a plan view illustrating the 3D semiconductor device,FIG.2Bis a cross-sectional view taken along a line A-A′ inFIG.2AandFIG.2Cis a cross-sectional view taken along a line B-B′ inFIG.2A.

Referring toFIGS.2A to2C, a 3D semiconductor device may include a stack structure ST, a vertical channel structure CH and contact plugs CT.

The stack structure ST may include a plurality of conductive patterns126and insulation patterns102and118. The plurality of conductive patterns126may be vertically stacked. The insulation patterns102and118may be arranged between the conductive patterns126to electrically isolate the conductive patterns126from each other. The insulation patterns102and118may include first insulation patterns102and second insulation patterns118, In various embodiments, the stack structure ST may include the first insulation pattern102, the conductive pattern126, the second insulation pattern118, the conductive pattern126and the first insulation pattern102repeatedly stacked in the vertical direction. For example, each of the conductive pattern126may include a barrier layer126B and a conductive layer126C stacked on the barrier layer126B. For example, the barrier layer126B may make contact with the first insulation pattern102. The conductive layer126C may make contact with the second insulation pattern118. The barrier layer1268may include a TiN layer. The conductive layer126C may include a tungsten material.

The 3D semiconductor device inFIGS.2A to2Cmay be substantially the same as the 3D semiconductor device inFIGS.1A to1Cexcept for the conductive pattern126, Thus, any further illustrations with respect to the 3D semiconductor device inFIGS.2A to2Cmay be omitted herein for brevity.

FIG.3is a view illustrating a 3D semiconductor device in accordance with various embodiments.

A plan view of the 3D semiconductor device inFIG.3may be substantially the same as the 3D semiconductor device inFIG.1A. Thus,FIG.3is a cross-sectional view taken along a line A-A′ inFIG.1A. A contact area of the 3D semiconductor device inFIG.3may be substantially the same as the contact area inFIG.1C. Therefore, drawings with respect to the same structure may be omitted herein for brevity.

Referring toFIG.3, a 3D semiconductor device may include a stack structure ST, a vertical channel structure CH and contact plugs CT.

The stack structure ST may include a plurality of conductive patterns126and insulation patterns102and118. The plurality of conductive patterns126may be vertically stacked. The insulation patterns102and118may be arranged between the conductive patterns126to electrically isolate the conductive patterns126from each other. For example, the thickness T1of the first insulation pattern102may be thicker than the thickness T3of the second insulation pattern118. For example, the thickness T1of the first insulation pattern102may be about 1.5 times to about 2.5 times the thickness T3of the second insulation pattern118.

In various embodiments, the first insulation pattern102may have a width W1wider than a width W2of the second insulation patterns118adjacent to the first insulation pattern102. In other words, the width W2of each of the second insulation patterns118may be narrower than the width W1of the first insulation pattern102. Sidewalls of the first insulation patterns102which correspond to an outer surface of the vertical channel structure CH may be protrude between the adjacent two second insulation patterns118. The widths W1and W2may correspond to a length along the second direction D2in drawings.

Each of the conductive patterns126may have a width substantially the same as the width W2of the second insulation pattern118, Thus, a concave recessed portion118rmay be defined in sidewalls of the second insulation patterns118which correspond to the outer surface of the vertical channel structure CH.

InFIG.3, the conductive pattern126may include a single layer without a barrier layer. Alternatively, as shown inFIG.26, the conductive pattern126may include a barrier layer and a conductive layer stacked on the barrier layer.

Each of the vertical channel structures CH may include a channel134and memory layers128,130and132configured to surround the channel134. The memory layers128,130and132may be interposed between the channel134and the conductive pattern126. The memory layers128,130and132may include a tunnel insulation layer132configured to surround the channel134, a data storage layer130configured to surround the tunnel insulation layer132and a blocking insulation layer128configured to surround the data storage layer130.

In a vertical cross-sectional view, each of the vertical channel structures CH may have protruded portions CHp corresponding to the recessed portions118r. For example, the memory layers128,130and132may partially protrude. The protruded portions CHp may be provided to the outer surface of the vertical channel structure CH corresponding to the second insulation pattern118. In an embodiment, the protruded portion CHp may protrude towards a corresponding insulation pattern118located at a level of the protruded portion CHp as shown inFIG.3.

The 3D semiconductor device inFIG.3may be substantially the same as the 3D semiconductor device inFIGS.1A to1Cexcept for the recess portions118rof the second insulation pattern118and the protruded portions CHp of each of the vertical channel structure CH. Thus, any further illustrations with respect to the 3D semiconductor device inFIG.3may be omitted herein for brevity.

Hereinafter, a method of manufacturing a 3D semiconductor device in accordance with various embodiments may be illustrated with reference to drawings,

FIGS.4A,4B,5,6A,6B,7A,7B,8A,8B,9,10,11,12Aand12B are cross-sectional views illustrating a method of manufacturing a 3D semiconductor device in accordance with various embodiments.FIGS.4A,5,6A,7A,8A,9,10,11and12Amay show a method of manufacturing the 3D semiconductor device in a cell region.FIGS.4B,6B,7B,8B and12Bmay show a method of manufacturing the 3D semiconductor device in a contact area.

Referring toFIGS.4A and4B, a plurality of first insulation patterns102and a plurality of sacrificial patterns104alternately stacked to form a stack structure ST. A plurality of sacrificial pillars110may be formed through the stack structure ST. The stack structure ST may be formed in the cell region CA and the contact area CTA.

For example, the first insulation patterns102may include a silicon oxide layer. The sacrificial patterns104may include a material having an etching selectivity with respect to an etchant for the first insulation pattern102. For example, the sacrificial pattern104may include a silicon nitride layer.

The first insulation pattern102may have a first thickness T1. The sacrificial pattern104may have a second thickness T2. The first thickness T1may be thicker than the second thickness T2, In various embodiments, the first thickness T1may be about 1.5 times to about 3 times the second thickness T2considering a thickness of a conductive pattern (not shown) to be formed later. For example, the thickness of the sacrificial pattern104in the cell region CA may be different from that of the sacrificial pattern104in the contact area CTA. In this embodiment, the thickness of the sacrificial pattern104in the contact area CTA may be referred to as a thickness of an end portion104E, The thickness of the end portion104E may be thicker than a thickness of the sacrificial pattern104in the cell region CA.

The end portion104E of the sacrificial pattern104may be formed in the following manner. Firstly, a sacrificial layer may be formed on the first insulation pattern102. For example, the sacrificial layer may be formed to have a fourth thickness14greater than the second thickness T2. The sacrificial layer may be etched to have the second thickness T2except for a portion predetermined as the end portion104E, thereby forming the sacrificial pattern104.

The stack structure ST may be etched to form a plurality of first holes HL1in the cell region CA. The first holes HL1may be formed through the stack structure ST in a direction substantially perpendicular to a surface of a substrate (hereinafter, referred to as a first direction D1). In various embodiments, each of the first holes HL1may have a first diameter DM1. The first hole HL1may have decreased diameters as the depth of the hole HL1increases. The first diameter DM1may be an average diameter of the decreased diameters. The contact area CTA may be masked during the first holes HL1may be formed in the cell region CA.

The first holes HL1may be filled with at least one sacrificial material to form the sacrificial pillars110, The sacrificial pillars110may include a plurality of sacrificial materials106and108. Each of the sacrificial pillars110may include a first layer106and a second layer108, The first layer106may be conformally formed along surface of the stack structure ST including the first holes HL1. The second layer108may be formed to fill the first hole HL1with the first layer106. For example, the first layer106may include a silicon oxide layer. The second layer108may include a polysilicon layer.

A mask pattern114may be formed on the stack structure ST with the sacrificial pillars110. The mask pattern114may be provided to define a trench. The mask pattern114may include a photoresist pattern.

As shown in drawings, an insulating interlayer112may be additionally formed between the stack structure ST and the mask pattern114. The insulating interlayer112may include a material having an etching selectivity with respect to an etchant for the sacrificial pattern104, For example, the insulating interlayer112may include a silicon oxide layer. Alternatively, the formation of the insulating interlayer112may be omitted.

Referring toFIG.5, the insulating interlayer112may be etched using the mask pattern114. The stack structure ST may be etched using the mask pattern114and the etched insulating interlayer112as an etch mask to form a trench TR.

The trench TR may be extended along a first direction D1. For example, the trench TR may divide the stack structure ST into two stack structures ST. For example, the divided stack structures ST may correspond to a unit memory block of the 3D semiconductor device.

The trench TR may be formed in the cell region CA. The contact area CTA may be masked during the trench TR may be formed. After forming the trench TR, the mask pattern may then be removed.

Referring toFIGS.6A and6B, the exposed sacrificial patterns104may be removed to form openings OP between the adjacent first insulation patterns102. As mentioned above, the sacrificial patterns104may include the material having an etching selectivity with respect to the etchant for the first insulation patterns102. Thus, the sacrificial patterns104may be selectively removed.

In this embodiment, each of the openings OP may have a first gap in the cell region CA and a second gap in the contact area CTA. The second gap may be larger than the first gap. Further, the second gap may be corresponded to an end opening OP_E. For example, the first gap may include the second thickness T2and the second gap, that is, the end opening OP_E may include the fourth thickness T4.

Referring toFIGS.7A and7B, a conductive layer116L may be conformally formed on an exposed surface of the openings OP in the stack structure ST, The conductive layer116L may be formed in the cell region CA and the contact area CTA.

The conductive layer116L may include a metal such as tungsten, molybdenum, etc., or polysilicon including conductive impurities. When the conductive layer116L may include the tungsten, the tungsten may have a minimum thickness. For example, the conductive layer116L may have a thickness determined by the second thickness TH and a resistance of a word line. However, the openings OP might not be fully filled with the conductive layer116L. Alternatively, the conductive layer116L may include a barrier layer and a conductive material layer stacked on the barrier layer. In this case, the barrier layer may include a TiN layer or Ti/TiN layers and the conductive material layer may include a tungsten layer.

Referring toFIGS.8A and8B, the openings OP with the conductive layer116L may be filled with second insulation patterns118. The second insulation patterns118may be formed in the cell region CA and the contact area CTA, An end portion118E of each of the second insulation patterns118in the contact area CTA may have a thickness thicker than that of the second insulation patterns in the cell region CA.

The second insulation patterns118may include at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxy-nitride layer. In various embodiments, the second insulation patterns118may be used as the silicon oxide layer. Further, the first insulation patterns102and the second insulation patterns118may include the same material. Alternatively, the first insulation patterns102and the second insulation patterns118may include different materials.

As mentioned above, the first gap of the opening OP may be substantially the same as the second thickness T2. The conductive layer may be formed on the stack structures ST defined by the opening OP. Thus, the second insulation patterns118in the openings OP may have the third thickness T3thinner than the second thickness T2. The thickness T1of the first insulation pattern102may be thicker than the thickness T3of the second insulation pattern118.

Referring toFIG.9, the conductive layer exposed through the trench TR may be etched to form preliminary conductive patterns116. The etching of the conductive layer exposed through the trench TR may electrically isolate the stack structures ST from each other.

Any one of the preliminary conductive patterns116may be configured to surround the sidewall of the second insulation pattern118. That is, in a cross-sectional view, the preliminary conductive patterns116may be configured to surround the lower surface, the upper surface and the side surface of the second insulation pattern118.

Referring toFIG.10, a slit structure SL may be formed in the trench TR. In various embodiments, insulation spacers120and122may be conformally formed on an inner surface of the trench TR. The trench TR with the insulation spacers120and122may be filled with a conductive material to form a source contact plug124, Alternatively, the trench TR may be filled with an insulation material to form the insulation spacers120and122.

Referring toFIG.11, the sacrificial pillars110in the cell region CA may be removed to define the first holes HL1of each of the stack structures ST. As mentioned above, each of the first holes HL1may have the first diameter DM1. Each of the preliminary conductive patterns116exposed through the first holes HL1may be configured to surround the lower surface, the upper surface and the side surface of the second insulation pattern118.

Referring toFIGS.12A and12B, side surfaces of the preliminary conductive patterns116exposed through the first holes HL1may be etched to form second holes HL2, Each of the second holes HL2may have a second diameter DM2longer than the first diameter DM1.

By forming the second holes HL2, one preliminary conductive pattern116may be divided into an upper conductive pattern126U and a lower conductive pattern126L.

During the side surfaces of the preliminary conductive patterns exposed through the first holes HL1in the cell region CA may be etched, the preliminary conductive patterns116formed at the end portion118E of the second insulation pattern118may be partially etched to divide the preliminary conductive patterns116into the two conductive patterns126.

Thus, the preliminary conductive patterns116may be divided into the upper and lower conductive patterns126to form the 3D semiconductor device having a high integration degree in a same area.

Referring again toFIG.1B, the vertical channel structures CH may be formed in the second holes HL2in the cell region CA.

Particularly, the memory layers128,130and132may be conformally formed on inner surfaces of the second holes HL2. The memory layers128,130and132may be formed by sequentially stacking the blocking insulation layer128, the data storage layer130and the tunnel insulation layer132. The channel134may be formed in the second holes HL2with the memory layers128,130and132.

Referring toFIG.1C, a plurality of the contact plugs CT may be electrically connected with the conductive patterns126in the contact area CTA.

FIG.13is a cross-sectional view illustrating a method of manufacturing a 3D semiconductor device in accordance with various embodiments.

The structure inFIG.11may be formed the processes illustrated with reference toFIGS.4A,48,5,6A,68,7A,7B,8A,88,9,10and11.

Referring toFIG.13, the side surfaces of the preliminary conductive patterns116exposed through the first holes HL1may be wet-etched. That is, portions of the preliminary conductive patterns116covered by the first insulation patterns102and the second insulation patterns118might not be etched. In contrast, the side surfaces of the preliminary conductive patterns116exposed through the first holes HL1may be selectively etched. Thus, by selectively etching the side surfaces of the preliminary conductive patterns116, one preliminary conductive pattern116may be electrically divided into an upper conductive pattern and a lower conductive pattern. As a result, each of the preliminary conductive patterns116may be divided into the upper and lower conductive patterns126to form the 3D semiconductor device having a high integration degree in a same area.

In various embodiments, a size of the first hole HL1may be partially expanded. However, the size of the first hole HL1may be maintained.

Referring again toFIG.3, the vertical channel structures CH may be formed in the first holes HL1. The vertical channel structure CH may have a shape corresponding to a shape of the first hole HL1.

FIG.14is a block diagram illustrating a memory system in accordance with various embodiments.

As illustrated inFIG.14, a memory system1000may include a memory device1200and a controller1100.

The memory device1200may be used to store various data types such as text, graphic and software code. The memory device1200may be a non-volatile memory. In an embodiment, the memory device1200may improve an integration density of stacked word lines by the preliminary conductive pattern surrounding the insulation pattern, as shown inFIG.1toFIG.13.

The controller1100may be couple to a host and the memory device1200, and the controller1100may access the memory device1200in response to a request from the host. For example, the controller1100may control read, write, erase and background operations of the memory device1200.

The controller1100may include a random access memory (RAM)1110, a central processing unit (CPU)1120, a host interface1130, an error correction code (ECC) circuit1140and a memory interface1150.

The RAM1110may function as an operation memory of the CPU1120, a cache memory between the memory device1200and the host, and a buffer memory between the memory device1200and the host. The RAM1110may be replaced by a static random access memory (SRAM) or a read only memory (ROM).

The host interface1130may be interface with the host. For example, the controller1100may communicate with the host through one of various interface protocols with a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial-ATA protocol, a Parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol and a private protocol.

The ECC circuit1140may detect and correct errors included in data read from the memory device1200by using error correction codes (ECCs).

The memory interface1150may interface with the memory device1200. For example, the memory interface1150may include a NAND interface or a NOR interface.

For example, the controller1100may further include a buffer memory (not illustrated) configured to temporarily store data. The buffer memory may temporarily store data, externally transferred through the host interface1130, or temporarily store data, transferred from the memory device1200through the memory interface1150. In addition, the controller1100may further include ROM storing code data to interface with the host.

FIG.15is a block diagram illustrating a memory system in accordance with various embodiments.

As illustrated inFIG.15, a memory system1000′ may include a memory device1200′ and the controller1100. In addition, the controller1100may include the RAM1110, the CPU1120, the host interface1130, the ECC circuit1140and the memory interface1150.

The memory device1200, in an embodiment, may improve an integration density of stacked word lines by the preliminary conductive pattern surrounding the insulation pattern, as shown inFIG.1toFIG.13.

In addition, the memory device1200′ may be a multi-chip package composed of a plurality of memory chips. The plurality of memory chips may have the stack structures ST ofFIG.1toFIG.13.

As described above, in an embodiment, a property of the memory system1000can be improved, because the memory system includes the memory device1200including at least one stack structure improved the integrated density of the word lines, as shown inFIG.1toFIG.13.

FIG.16is a block diagram illustrating a computing system in accordance with various embodiments.

As illustrated inFIG.16, a computing system2000may include a memory device2100, a CPU2200, a random-access memory (RAM)2300, a user interface2400, a power supply2500and a system bus2600.

The memory device2100may store data, which is input through the user interface2400, and data, which is processed by the CPU2200. In addition, the memory device2100may be electrically coupled to the CPU2200, the RAM2300, the user interface2400and the power supply2500. For example, the memory device2100may be coupled to the system bus2600through a controller (not illustrated) or directly coupled to the system bus2600. When the memory device2100is directly coupled to the system bus2600, functions of the controller may be performed by the CPU2200and the RAM2300.

The memory device2100, in an embodiment, may improve an integration density of stacked word lines by the preliminary conductive pattern surrounding the insulation pattern, as shown inFIG.1toFIG.13.

The computing system2000having the above-described configuration may be one of various components of an electronic device, such as a computer, an ultra-mobile PC (UMPC), a workstation, a net-book, personal digital assistants (PDAs), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a three-dimensional (3D) television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device for transmitting/receiving information in wireless environment, one of various electronic devices for home network, one of various electronic devices for computer network, one of various electronic devices for telematics network, an RFID device, and/or one of various devices for computing systems, etc.

As described above, in an embodiment, a property of the computing system2000can be improved by improving the integrated density of the word lines of the memory device1200, as shown inFIG.1toFIG.13.

FIG.17is a block diagram illustrating a computing system in accordance with examples of embodiments.

As illustrated inFIG.17, a computing system3000ray include a software layer that has an operating system3100an application3200, a file system3300and a translation layer3400. In addition, the computing system3000may include a hardware layer such as a memory system3500.

The operating system3100manages software and hardware resources of the computing system3000, The operating system3100may control program execution of a central processing unit. The application3200may include various application programs executed by the computing system3000, The application3200may be a utility executed by the operating system3100.

The file system3300may refer to a logical structure configured to manage data and files present in the computing system3000. The file system3300may organize files or data to be stored in the memory device3500according to rules. The file system3300may be determined depending on the operating system3100that is used in the computing system3000. For example, when the operating system3100is a Microsoft Windows-based system, the file system3300may be a file allocation table (FAT) or an NT file system (NTFS). In addition, when the operating system3100is a Unix/Linux-based system, the file system3300may be an extended file system (EXT), a Unix file system (UFS) or a journaling file system (JFS).

The translation layer3400may translate an address to be suitable for the memory device3500in response to a request from the file system3300. For example, the translation layer3400may translate a logic address, generated by the file system3300, into a physical address of the memory device3500, Mapping information of the logic address and the physical address may be stored in an address translation table. For example, the translation layer3400may be a flash translation layer (FTL), a universal flash storage link layer (ULL) or the like.

The memory device3500, in an embodiment, may improve an integration density of stacked word lines by the preliminary conductive pattern surrounding the insulation pattern, as shown inFIG.1toFIG.13.

The computing system3000with the above-described configuration may be divided into an operating system layer that is operated in an upper layer region and a controller layer that is operated in a lower level region. The operating system3100, the application3200, and the file system3300may be included in the operating system layer and driven by an operation memory. In addition, the translation layer3400may be included in the operating system layer or the controller layer.

As described above, in an embodiment, a property of the computing system3000can be improved using the stack structure in which the integrated density of the word lines of the memory device1200, as shown inFIG.1toFIG.13.

The above described embodiments are intended to illustrate and not to limit the embodiments. Various alternatives and equivalents are possible. The embodiments are not limited by the embodiments described herein, Nor are the embodiments limited to any specific type of semiconductor device. Another additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.