Solid-state image pickup device, and camera module

According to one embodiment, a solid-state image pickup device includes a pixel array that includes a two-dimensionally arranged matrix of photoelectric conversion elements corresponding to pixels of a picked-up image. Each of the photoelectric conversion elements includes a first conductive semiconductor region and a second conductive semiconductor region between which an uneven junction plane is formed.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-135122, filed on Jun. 27, 2013; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a solid-state image pickup device, a method of fabricating the solid-state image pickup device, and a camera module.

BACKGROUND

In the related art, an electronic device such as a digital camera or a mobile terminal with camera function is provided with a camera module including a solid-state image pickup device. The solid-state image pickup device includes a plurality of photoelectric conversion elements arranged two-dimensionally corresponding to each pixel of a picked-up image. Each of the photoelectric conversion elements photoelectrically converts incident light into a quantity of electric charges (for example, electrons) corresponding to a light-received quantity to accumulate as information indicating luminance of each pixel.

In such solid-state image pickup device, miniaturization of the photoelectric conversion element has proceeded with downsizing of the device. As the miniaturization of the photoelectric conversion element proceeds, since the number of electrons to be accumulated by each of the photoelectric conversion elements, so-called the number of saturated electrons becomes less, reproduction characteristic of the picked-up image is reduced. In solid-state image pickup device, therefore, the photoelectric conversion element capable of increasing the number of saturated electrons in a limited region is desired.

DETAILED DESCRIPTION

In general, according to one embodiment, a solid-state image pickup device includes a pixel array that includes a two-dimensionally arranged matrix of photoelectric conversion elements corresponding to pixels of a picked-up image. Each of the photoelectric conversion elements includes a first conductive semiconductor region and a second conductive semiconductor region between which an uneven junction plane is formed.

Exemplary embodiments of a solid-state image pickup device, a method of fabricating the solid-state image pickup device, and a camera module will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

First Embodiment

FIG. 1is a block diagram illustrating a schematic configuration of a digital camera1provided with a solid-state image pickup device14according to a first embodiment. As illustrated inFIG. 1, the digital camera1includes a camera module11and a post-processing unit12.

The camera module11includes an image pickup optical system13and the solid-state image pickup device14. The image pickup optical system13receives light from an object to form an object image. The solid-state image pickup device14picks up the object image formed by the image pickup optical system13and outputs an image signal obtained by the image pickup to the post-processing unit12. Such camera module11is applied to, for example, an electronic device such as a mobile terminal with camera in addition to the digital camera1.

The post-processing unit12includes an ISP (Image Signal Processor)15, a storage unit16, and a display unit17. The ISP15carries out a signal processing of the image signal input from the solid-state image pickup device14. The ISP15carries out a high-quality picture processing such as, for example, a noise removal processing, a dead pixel correction processing, and a resolution conversion processing.

Further, the ISP15outputs the image signal after the signal processing to the storage unit16, the display unit17and a signal processing circuit21(seeFIG. 2), which will be described later, provided in the solid-state image pickup device14within the camera module11. The image signal fed back to the camera module11from the ISP15is used for adjustment or control of the solid-state image pickup device14.

The storage unit16stores the image signal input from the ISP15as an image. In addition, the storage unit16outputs the image signal of the stored image to the display unit17depending on an operation of a user. The display unit17displays the image depending on the image signal input from the ISP15or the storage unit16. Such display unit17is, for example, a liquid crystal display.

The solid-state image pickup device14provided in the camera module11will be described below with reference toFIG. 2.FIG. 2is a block diagram illustrating a schematic configuration of the solid-state image pickup device14according to the first embodiment. As illustrated inFIG. 2, the solid-state image pickup device14includes an image sensor20and a signal processing circuit21.

Here, the image sensor20which is a so-called back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described. In the CMOS image sensor, a wiring layer is formed on a surface opposite to a surface of the photoelectric conversion element which incident light enters, the photoelectric conversion element photoelectrically converting the incident light.

Further, the image sensor20according to the present embodiment is not limited to the back-illuminated CMOS image sensor, but may be arbitrary image sensors such as a front-illuminated CMOS image sensor or CCD (Charge Coupled Device) image sensor.

The image sensor20includes a peripheral circuit22and a pixel array23. In addition, the peripheral circuit22includes a vertical shift register24, a timing control unit25, a CDS (correlated double sampling unit)26, an ADC (analog/digital converting unit)27, and a line memory28.

The pixel array23is provided in an image pickup region of the image sensor20. In the pixel array23, a plurality of photoelectric conversion elements corresponding to each pixel of the picked-up image are disposed in a form of two-dimensional array (matrix form) in a horizontal direction (row direction) and a vertical direction (column direction). Then, the pixel array23accumulates signal charges (for example, electrons) generated depending on the quantity of the incident light by each of the photoelectric conversion elements corresponding to each pixel.

The timing control unit25is a processing unit that outputs a pulse signal acting as a reference of operation timing with respect to the vertical shift register24. The vertical shift register24is a processing unit that outputs a selection signal to the pixel array23, the selection signal being used to sequentially select the photoelectric conversion element which reads the signal charge out of the plurality of photoelectric conversion elements disposed in the form of array (matrix), by the row.

The pixel array23outputs the signal charge accumulated in each of the photoelectric conversion elements, which is selected through the selection signal input from the vertical shift register24by the row, to the CDS26from the photoelectric conversion element, as the pixel signal indicating the luminance of each pixel.

The CDS26is a processing unit that removes a noise from the pixel signal input from the pixel array23by the correlated double sampling and then outputs it to the ADC27. The ADC27is a processing unit that converts an analog pixel signal input from the CDS26to a digital pixel signal and then outputs it to the line memory28. The line memory28is a processing unit that temporarily holds the pixel signal input from the ADC27and outputs it the signal processing circuit21for each row of the photoelectric conversion element in the pixel array23.

The signal processing circuit21is a processing unit that performs a predetermined signal processing on the pixel signal input from the line memory28and outputs it the post-processing unit12. The signal processing circuit21performs the signal processing such as, for example, lens shading correction, flaw correction, and noise reduction processing on the pixel signal.

Like this, in the image sensor20, the plurality of photoelectric conversion elements disposed in the pixel array23photoelectrically convert the incident light into the signal charge of the quantity corresponding to the light-received quantity and accumulates the converted signal charge, and the peripheral circuit22reads the signal charge accumulated in each of the photoelectric conversion elements as the pixel signal, thus performing the image pickup.

Each of the photoelectric conversion elements disposed in the pixel array23of the image sensor20is a photodiode which is formed by PN junction between a first conductive-type (herein, referred to as an “N-type”) semiconductor (herein, referred to as a “Si: silicon”) region and a second conductive-type (herein, referred to as a “P-type”) Si region.

Then, the photoelectric conversion element accumulates the signal charge (herein, “electron”), which is generated by photoelectrically converting the incident light, in the junction portion between the N-type Si region and the P-type Si region. Therefore, as the area of the junction plane between the N-type Si region and the P-type Si region is large, the number of accumulable electrons (hereinafter, referred to as “the number of saturated electrons”) of the photoelectric conversion element increases.

However, as miniaturization of the photoelectric conversion element proceeds with downsizing of the solid-state image pickup device14, since the area of the junction plane between the N-type Si region and the P-type Si region is reduced in each of the photoelectric conversion elements, the number of saturated electrons of each photoelectric conversion element becomes less and thus reproduction characteristics of the picked-up image decreases.

In the solid-state image pickup device14according to the first embodiment, therefore, each of the photoelectric conversion elements is configured to increase the number of saturated electrons within the limited region. A configuration of the photoelectric conversion element according to the first embodiment will be described below with reference toFIGS. 3 and 4.

FIG. 3is an explanatory diagram of a photoelectric conversion element3in cross-sectional view according to the first embodiment, andFIG. 4is an explanatory diagram of the photoelectric conversion element3in plan view according to the first embodiment. Further,FIG. 4illustrates schematically a cross section of the photoelectric conversion element3corresponding to one pixel of the picked-up image taken along a direction perpendicular to a light receiving surface. In addition,FIG. 4illustrates schematically the light receiving surface of the photoelectric conversion element3corresponding to one pixel of the picked-up image.

As illustrated inFIG. 3, the photoelectric conversion element3includes an N-type Si region4provided on a semiconductor substrate31such as a Si wafer and a first P-type Si region5provided on an upper face and a lateral face of the N-type Si region4. Further, a Shallow Trench Isolation (STI)32is formed at an outer side more than the first P-type Si region5provided on the lateral face of the N-type Si region4. Each of the photoelectric conversion elements3is electrically isolated from an adjacent other photoelectric conversion element3by the STI32.

Furthermore, the photoelectric conversion element3includes a plurality of second P-type Si regions51provided so as to protrude toward the N-type Si region4from the junction plane between the first P-type Si region5provided at the upper face portion of the N-type Si region4and the N-type Si region4.

As illustrated inFIG. 4, the second P-type Si regions51are provided so as to be in the form of stripe in plan view, and the second P-type Si regions51are provided so as to be parallel with each other and be parallel with the light-receiving surface of the photoelectric conversion element3. Further, hereinafter, in a case of aiming a P-type semiconductor region formed by the first P-type Si region5and the second P-type Si regions51, it is simply referred to as “P-type Si region”.

Thus, the photoelectric conversion element3includes the second P-type Si regions51protruding in a depth direction toward the N-type Si region4from the first P-type Si region5, in addition to the first P-type Si region5. For this reason, in the photoelectric conversion element3, the PN junction is formed at the junction portion between the N-type Si region4and the first P-type Si region5and the PN junction is also formed at the junction portion between the N-type Si region4and the second P-type Si regions51.

In the photoelectric conversion element3, that is, as illustrated by a thick line inFIG. 3, the junction plane between the N-type Si region4and the P-type Si region has a concave/convex shape which are formed with a convex portion5aprotruding toward the semiconductor substrate31and a concave portion5bconcaved toward the light-receiving surface of the photoelectric conversion element3. Therefore, according to the photoelectric conversion element3, since the area of the junction plane between the N-type Si region4and the P-type Si region, that is, the area of the PN junction is enlarged compared to another photoelectric conversion element not provided with the second P-type Si region51, it is possible to increase the number of saturated electrons.

Further, the present embodiment is described on the case provided so that the second P-type Si regions51are parallel with each other as viewed from plane and are parallel with the light-receiving surface of the photoelectric conversion element3, but the shape of the second P-type Si regions51as viewed from plane is not limited thereto.

Modified examples of the second P-type Si regions51according to the first embodiment will be described below with reference toFIGS. 5 and 6.FIG. 5is an explanatory diagram of a light-receiving surface in a photoelectric conversion element3aaccording to a first modified example as viewed from plane, andFIG. 6is an explanatory diagram of a light-receiving surface in a photoelectric conversion element3baccording to a second modified example as viewed from plane. Further, inFIGS. 5 and 6, the same components as inFIG. 3are denoted by the same reference numerals as inFIG. 3.

As illustrated inFIG. 5, the photoelectric conversion element3aaccording to the first modified example includes a stripe-shaped second P-type Si region52which is disposed in a lattice pattern as viewed from plan. Further, similar to the second P-type Si region51illustrated inFIG. 3, the second P-type Si region52is also provided so as to protrude in the depth direction toward the N-type Si region4from the first P-type Si region5. Thus, since the area of the PN junction is more enlarged, it is possible to further increase the number of saturated electrons.

In addition, as illustrated inFIG. 6, the photoelectric conversion element3baccording to the second modified example includes second P-type Si regions53which are provided in a form of plural dots on the light-receiving surface of the photoelectric conversion element3b. Further, similar to the second P-type Si region51illustrated inFIG. 3, the second P-type Si region53is also provided so as to protrude in the depth direction toward the N-type Si region4from the first P-type Si region5. Even by the second P-type Si regions53, since the area of the PN junction is enlarged, it is possible to increase the number of saturated electrons.

A method of fabricating the solid-state image pickup device14provided with the photoelectric conversion element3will be described below. Further, in a fabricating process of the solid-state image pickup device14, fabricating processes other than a forming process of the photoelectric conversion element3are the same as in the solid-state image pickup device, in general. Therefore, the forming process of the photoelectric conversion element3will be described herein, and the description of other fabricating processes will not be presented.

FIGS. 7A to 7Dare explanatory diagrams illustrating the forming process of the photoelectric conversion element3according to the first embodiment. In the process of forming the photoelectric conversion element3, first, as illustrated inFIG. 7A, the N-type Si region4is formed on the semiconductor substrate31.

The N-type Si region4is formed by, for example, ion-implanting an N-type impurity such as phosphorus into the semiconductor substrate31and then performing an annealing treatment. Further, the N-type Si region4may be a Si layer doped with the N-type impurity, which is formed on the semiconductor substrate31by, for example, CVD (Chemical Vapor Deposition).

Thereafter, as illustrated inFIG. 7B, a trench (groove) is formed at a formation position of the STI32in the N-type Si region4. Subsequently, as illustrated inFIG. 7C, the first P-type Si region5and the STI32are sequentially formed.

The first P-type Si region5is formed by, for example, ion-implanting a P-type impurity such as boron into the upper face, the lateral face (lateral face of trench), and the bottom face of the N-type Si region4and then performing the annealing treatment.

In addition, the STI32is formed by burying a silicon oxide in an interior of the trench in which the first P-type Si region5is formed at an inner periphery, using the CVD, for example. Further, in a state illustrated inFIG. 7C, the junction plane between the upper face of the N-type Si region4and the first P-type Si region5is a planar shape as illustrated by the thick line inFIG. 7C.

Subsequently, as illustrated inFIG. 7D, the second P-type Si region51is formed. The second P-type Si region51is formed by, for example, forming a mask provided with a stripe-shaped opening on the upper face of the first P-type Si region5, ion-implanting the P-type impurity toward the N-type Si region4over the mask, and then performing the annealing treatment.

Further, in a case of forming the second P-type Si region51, a higher energy is applied to the P-type impurity than in the case of forming the first P-type Si region5to perform the ion implantation. For this reason, the ion implantation of the P-type impurity into the interior of the N-type Si region4is conducted deeper than that of the P-type impurity into the first P-type Si region5, and then the second P-type Si region51is formed so as to protrude in the depth direction toward the N-type Si region4from the first P-type Si region5by the annealing treatment.

As a result, in a state illustrated inFIG. 7D, the junction plane between the N-type Si region4and the P-type Si region is a concave/convex shape as illustrated by the thick line inFIG. 7D. Here, as is apparent from a comparison betweenFIGS. 7C and 7D, the area of the PN junction (see thick line illustrated inFIGS. 7C and 7D) after the formation of the second P-type Si regions51is larger than that before the formation of the second P-type Si regions51.

Thus, in the forming process of the photoelectric conversion element3, the second P-type Si region51is formed by ion-implanting the P-type impurity with energy higher than in the case of forming the first P-type Si region5to form the PN junction of the concave/convex shape.

For this reason, according to the photoelectric conversion element3, even when the second P-type Si regions51is provided, since the area of the PN junction can be enlarged to increase the number of saturated electrons, it is possible to improve the reproduction characteristics of the picked-up image.

Further, in the example illustrated inFIGS. 7A to 7D, the second P-type Si region51is formed by the ion-implantation, but the second P-type Si region51may be formed by methods other than the ion-implantation.

For example, after a structure illustrated inFIG. 7Cis formed, the N-type Si region4and the first P-type Si region5are patterned in the shape as illustrated inFIG. 7Dby performing a patterning using a photolithography technique.

In this state, the region in which the second P-type Si region51illustrated inFIG. 7Dis formed is the striped groove as viewed from plane. Then, the second P-type Si region51may be formed by burying Si, which is doped with the P-type impurity, in the groove by the CVD.

As described above, the photoelectric conversion element3according to the first embodiment is formed so that the junction plane between the N-type Si region4and the P-type Si region is the convex/concave shape. Thus, since the number of saturated electrons of each photoelectric conversion element3is increased, it is possible to improve the reproduction characteristics of the picked-up image. Further, the configurations of the photoelectric conversion elements3,3a, and3billustrated inFIGS. 3 to 6are an example, and these configurations can variously be modified. A photoelectric conversion element according to other embodiments will be described below.

Second Embodiment

FIG. 8is an explanatory diagram of a photoelectric conversion element3caccording to a second embodiment as viewed from cross section. As illustrated inFIG. 8, the photoelectric conversion element3cincludes a first N-type Si region41which is formed more thinly than the N-type Si region4and a second N-type Si region42which is formed more deeply than the first N-type Si region41, instead of the N-type Si region4illustrated inFIG. 3.

Furthermore, the photoelectric conversion element3cis configured in the same manner as illustrated inFIG. 3, except that the first N-type Si region41and the second N-type Si region42illustrated inFIG. 8are provided instead of the N-type Si region4illustrated inFIG. 3. For example, as viewed from plane, the second N-type Si region42may be formed in the parallel stripe shape as illustrated inFIG. 4, in the lattice pattern as illustrated inFIG. 5, and in the dot shape as illustrated inFIG. 6.

For example, the second N-type Si region42is formed by ion-implanting the N-type impurity into the semiconductor substrate31with the energy higher than in the case of forming the first N-type Si region41.

For this reason, the second N-type Si region42is formed so as to protrude toward the semiconductor substrate31from the junction plane between the first N-type Si region41and the semiconductor substrate31. Furthermore, the second N-type Si region42may also be formed by burying Si doped with the N-type impurity in the groove, which is formed by patterning the first N-type Si region41and the semiconductor substrate31, using the CVD rather than the ion implantation.

According to the second embodiment, as illustrated by the thick line inFIG. 8, since the junction plane between the first and second N-type Si regions41and42and the P-type Si region is the convex/concave shape, it is possible to increase the number of saturated electrons compared to a case where the second P-type Si region51is not provided.

Further, according to the second embodiment, in a case of not forming deeply the first N-type Si region41for certain reasons, since the second N-type Si region42is provided to cover at least the second P-type Si regions51, it is possible to form the PN junction of the convex/concave shape.

Third Embodiment

FIG. 9is an explanatory diagram of a photoelectric conversion element3daccording to a third embodiment as viewed from cross section. As illustrated inFIG. 9, the photoelectric conversion element3dis configured in the same manner as the photoelectric conversion element3illustrated inFIG. 3, except that a third P-type Si region54is provided inside the N-type Si region4. The third P-type Si region54is formed by ion-implanting the P-type impurity into the N-type Si region4with the energy higher than in the case of forming the second P-type Si regions51.

According to the third embodiment, since the PN junction is also formed at an interface between the third P-type Si region54and the N-type Si region4to accumulate the photoelectrically converted electron, it is possible to further increase the number of saturated electrons.

Fourth Embodiment

FIG. 10is an explanatory diagram of a photoelectric conversion element3eaccording to a fourth embodiment as viewed from cross section. As illustrated inFIG. 10, the photoelectric conversion element3eincludes a second N-type Si region43which is formed more deeply up to a deep position of the semiconductor substrate31than the second N-type Si region42illustrated inFIG. 8.

In addition, the photoelectric conversion element3eincludes a second P-type Si region55which is provided inside the second N-type Si region43and is formed more deeply up to the deep position of the semiconductor substrate31than the second P-type Si region51illustrated inFIG. 8. Further, the photoelectric conversion element3eincludes an insulation region61which is formed inside the second P-type Si region55by an insulator such as Si oxide.

In the case of forming the photoelectric conversion element3e, firstly, the structure illustrated inFIG. 7Cis formed by the processes illustrated inFIGS. 7A to 7C. Subsequently, the trench is formed toward the depth direction in the semiconductor substrate31from predetermined positions of plural locations in the upper face of the first P-type Si region5. The trench formed by the above process may be formed in the parallel stripe shape as viewed from plane, in the lattice pattern as viewed from plane, and in the dot shape as viewed from plane. Furthermore, the trench is back-filled by Si oxide.

Subsequently, the second N-type Si region43and the second P-type Si region55are formed by sequentially ion-implanting the N-type impurity and the P-type impurity into an inner periphery of the trench and then performing the annealing treatment. Finally, the insulation region61is formed by burying the insulator such as Si oxide inside the trench using, for example, the CVD, and the photoelectric conversion element3eillustrated inFIG. 10is formed.

Like this, according to the fourth embodiment, since the second N-type Si region43and the second P-type Si region55are formed by ion-implanting the N-type impurity and the P-type impurity into the inner periphery of the trench after the formation of the trench, the PN junction is formed up to the deeper position of the semiconductor substrate31.

Therefore, according to the fourth embodiment, since the PN junction formed in the photoelectric conversion element3efurther extends toward the depth direction of the semiconductor substrate31, it is possible to further increase the number of saturated electrons.

Fifth Embodiment

FIG. 11is an explanatory diagram of a photoelectric conversion element3faccording to a fifth embodiment as viewed from cross section. As illustrated inFIG. 11, the photoelectric conversion element3fdiffers from that illustrated inFIG. 10in that the second P-type Si region55illustrated inFIG. 10is not provided and a conductive region62is provided in place of the insulation region61. In addition, the conductive region62of the photoelectric conversion element3fis connected to a DC power source71through a wiring72, and a negative voltage is applied to the conductive region62from the DC power source71.

The photoelectric conversion element3fis formed without using the process of forming the second P-type Si region55in the process of forming the photoelectric conversion element3eillustrated inFIG. 10and by burying a conductor such as a poly-Si in the trench using, for example, the CVD, instead of the process of forming the insulation region61.

In the photoelectric conversion element3f, when the negative voltage is applied to the conductive region62, an inversion region56in which positive and negative of electrical characteristics are inverted is formed at a portion which comes in contact with the conductive region62in the second N-type Si region43. The inversion region56has the same function as the second P-type Si regions55illustrated inFIG. 10.

Therefore, according to the fifth embodiment, even without using the process of forming the second P-type Si region55(FIG. 10), since the PN junction further extends toward the depth direction of the semiconductor substrate31as in the fourth embodiment, it is possible to much more increase the number of saturated electrons.

Further, a material of the conductive region62in the fifth embodiment is not limited to the poly-Si, but may be a transparent electrode material represented by, for example, ITO (Indium Tin Oxide). In the case of using the transparent electrode material as the material of the conductive region62, it is possible to increase the quantity of saturated electrons while suppressing the quantity of incident light which enters the photoelectric conversion element3f.