MULTI-PHASE CLOCK GENERATION CIRCUIT WITH DIGITAL CALIBRATION

A power saving improvement in an injection locked oscillator (ILO) used is described. The ILO circuitry comprises a feedback path to provide a finecal (M-bit fine calibration signal). The feedback path need not be active at all times; only when an event occurs that requires the feedback path to update the value of the finecal signal. A monitor is provided to sense the occurrence of such event which may be, for examples, an end of a time period or a predetermined change in temperature. When the event occurs, the feedback path is activated to update the value of the finecal signal.

BACKGROUND

Modern off chip bandwidth requirements have steadily increased, forcing more and more advanced techniques to transmit data reliably.

SUMMARY

Modern off chip bandwidth requirements have steadily increased, forcing more and more advanced techniques to transmit data reliably. For example, at data rates of 2 GHZ (gigahertz) and above the “eyes” (periods of time in which data may be reliably sampled) become more and more narrow as frequency increases. It is important to sample incoming data in or near the center of the “eyes”.

Modern techniques use PLLs (phase locked loops) or ILOs (injection locked oscillators) for accurate frequency and phase control. ILOs are particularly used where a single ILO design must handle a range of frequencies, for example, for different chips operating at different frequencies. ILOs typically receive a “coarse setting” to define what the frequency of a reference clock input to the ILO is. This is typically an N-bit input (e.g., seven bits) to set a nominal frequency of the ILO. ILOs also typically receive a “fine calibration” input, typically an M-bit input (e.g., four bits “encoded” or an unencoded sixteen bits) generated within a HSIO (high speed input/output) system within which the ILO is built.

Described herein is a high speed input/output system having an ILO. The ILO receives a coarse tuning for the general frequency and a fine calibration. The fine calibration is a digital signal that may need be be changed based on a change in temperature, voltage, or a timeout of a timer.

DETAILED DESCRIPTION

The present disclosure deals with a method to control a fine calibration input to an injection locked oscillator (ILO).

Turning now toFIG.1, a high-speed input output block and explanation of the blocks are given.

HSIO120is a high-speed input output block shown, in part, to identify key parts of a clock generation portion of HSIO120.

Clock generation circuitry140comprises IQ Divider102, phase rotator104, IQ4GEN106which further comprises controller112, mini phase rotator108, and CML to CMOS110.

Monitor130is used to signal131to drivers and receivers that M-bit fine calibration207is going to be recalibrated.

Recalibration of M-bit fine calibration207would cause significant jitter in the clock output, so during the fine calibration time, the drivers and receivers are “retrained” and are not using clocks generated in clock generation circuitry140. Generally, recalibration needs to be done because of temperature or voltage changes, which also would affect the driver and receiver circuitry. This will be described in more detail later.

IQ divider102receives a single clock phase on signal101as input and outputs two clock phases 90 degrees apart, at half the input clock frequency on signal103. This is well-known in the art and will not be discussed further herein.

Phase rotator104takes, from signal103, two clock phases 90 degrees apart and mixes them according to a digital input code to produce a single output phase at the same frequency but arbitrary phase on signal105. Ideally the phase varies linearly with the digital input code. In a high-speed serial link, the phase rotator is used to align a sampling clock with a center of a data eye and obtain the lowest bit error rate, as well as track clock variation using CDR (clock data recovery). This is well-known in the art and will not be further discussed herein.

IQ4GEN106is described in more detail inFIG.2.

Mini phase rotator108is generally the same as main phase rotator104except outputs are 45 degrees apart, so there are two input phases on signal107and there is one output phase on signal109. The range of the output phase is less than that of the outputs of phase rotator104. Mini phase rotator108is used to compensate for clock skew. There are four of these in an embodiment of the current invention, so at the output of four mini phase rotators108, four clock phases are available.

CML to CMOS110converts the low swing differential signals on signal109in the preceding circuits to full rail-to-rail CMOS levels on signal111which is used in data sampling latches in receivers (not shown) in HSIO120. Signal111is also sent to controller112as a feedback loop.

With reference now toFIG.2, signal105is buffered by buffer202to signal203which is input to injection locked oscillator ILO204. ILO204outputs signal205to buffer206, which drives signal107.

Controller112has phase detector208which receives signal111from CML to CMOS110. Outputs of phase detector208are low pass filtered in LPF210and fed to comparator212, which outputs a “1” or “0” signal to random logic macro RLM214. RLM214produces the M-bit fine calibration207signal, for brevity, hereinafter referred to as finecal207.

With reference now toFIG.3, ILO204is shown to be a ring oscillator comprising four differential blocks302(302A,302B,302C, and302D) connected as an oscillating ring. Circles indicate “negative” for inputs and outputs. For example, a negative output of302A is coupled to a negative input of302B, and so on until302D's negative output is coupled to a positive input of302A. Injection locking is done by block304with receiving203(P) positive input and203(N) negative input. N3and N4are a differential stage. Outputs from block304are connected to outputs of block302A as shown.

A detailed description of block302A is shown inFIG.6.

With reference now toFIG.6, details of a block302are shown. Drains of N1and N2are coupled to resistors controlled by N-bit coarse tuning117, which sets the ILOs nominal frequency. The nominal frequency may be changed for different applications by changing the value of N-bit coarse tuning117. The tail current of the differential302is set by conventional means to control common mode output voltage on the block302outputs305and307.

Gates of N1and N2FETs (N-channel field effect transistors are assumed to be the FETs used herein) are connected to the previous ring stage's outputs a particular302has input signals301and303. Fine tuning is done using finecal207. Bits of finecal207are labeled FC0to FCM. A particular “1” bit in finecal207will turn the FET it is coupled to on both inputs to block302and cause the signal to be slowed down. If all M bits of finecal207are “1” the ILO will oscillate as slowly as possible, given the current coarse tuning117value.

Inputs to block302are signals301and303. Outputs are signals305and307.

FIG.4gives a circuit schematic of phase detector208, LPF210, and comparator212. Phase detector208has a mixer comprised of resistors R1, R2, R3, R4, R5, R6, R7, and R8; FETs (Field Effect Transistors) N5, N6, N7, N8, N9, N10, N11, and N12coupled to inputs from the four bits of signal111as shown. Phase 0 is coupled to a R1and N5series connection, with N5coupled to phase 270. Likewise, phase 270 is coupled to a R2and N6series connection with N6driven by phase 0. Similar connections occur for phases 180 and 90. R3, R4, N7, and N8. N5, N6, N7, and N8have terminals coupled to signal401, which is input to low pass filter made up of R9and C1and outputs to signal405. Likewise, phases 0, 90, 180, and 270 produce an on signal403which is input low pass filter made up of R10and C2. Output of the R10and C2low pass filter is signal407. Selector402receives signals405and407and passes signal407if polarity is 1 and405if polarity is 0. Selector404passes signal405if polarity is 1 and passes407if polarity417is 0. Signal409from selector402is coupled to a positive input of comparator212; signal411of selector404is coupled to a negative input of comparator212. Comparator212drives signal413to RLM214.

The purpose of polarity417is to account for possible mismatch in the FET differential pair in comparator212, as will be shown inFIG.5.

FIG.5illustrates a method500performed by RLM214. RLM214may be embodied with software or with random logic blocks.

In block501, finecal207is set to “0” (all M bits set to 0). Feedback loop controller112is activated. Polarity417is set to 0.

In block502, wait “X” cycles where “X” is set by a designer to allow time for effect of the value change in finecal207to reach a steady state.

In block503, comparator (signal413) is checked. If “1” an error in coarse tuning exists; if “0” control passes to block504.

In block506, the comparator signal413is checked. If the comparator signal413is still “0”, control passes back to block504. If comparator signal413is “1”, control passes to block511.

In block511, the finecal207value is stored as “first result” in latches. then finecal207is set to “1” (all bits in finecal207set to “1”).

In block513, comparator signal413is checked. If “0”, an error in coarse fine tuning exists. If “1”, control passes to block514.

In block516check comparator signal413. If “1”, pass control to block514. If “0”, pass control to block517.

In block517, set “second result” to finecal207. Final value for finecal207=(first result+second result)/2. This minimizes effect of any FET mismatch in the differential pair in the comparator212. Then feedback loop is turned off to save power (shut off phase detector208, comparator212, and logic in RLM214except for latches outputting finecal M-bit fine calibration207).

The feedback loop and attendant power is not needed until M-bit fine calibration207needs to be updated. The ILO may be running at 10 gigahertz or more, which is ten cycles per nanosecond. Changing the M-bit fine calibration may be needed if there is some change in, for example, temperature, voltage, bit error rate or other factor. At that time, a calibration period is started upon a signal from monitor130. Receivers are put into a mode where they do not use an output from clock generation circuitry140during the calibration period.

Besides power reduction from turning off the feedback loop, controller112, inherently, since no changes are made to finecal207while the receivers are using the clock generation circuitry output signal111, jitter is reduced and a faster phase response is obtained.

FIG.7Ashows a simple embodiment of monitor130. A counter702counts at a user defined frequency.

In block712, a check has been made to see if the counter has overfowed. If “No”, control returns to block710. If “Yes”, the user determined time (e.g. 10 milliseconds) which the user has determined or estimated is much shorter than a thermal time constant. Control passes to block714which runs method500.

The monitor130A may be running more calibrations than necessary as the user's estimate on frequency of updating finecal207is pessimistic.

FIG.130Bshows a more complicated monitor130that will only respond to thermal variations large enough to warrant a recalibration.

Here, a counter730, perhaps running at a faster rate than the counter702of130A, receives a temperature signal from temperature704upon overflow of counter730. Counter overflow signal731requests a new temperature reading from temperature704.

In block720, receive counter overflow signal.

In block721, make new temperature reading.

In block722, is the new reading more than a specified difference from a current reading? If yes, pass control to block723which sets current reading equal to the new reading, then block724runs method500to update finecal207. If no, control passes back to block720.