Transmitting circuit, transceiver, communication system, and method for transmitting data

A transmitting circuit, a transceiver, a communication system, and a method for transmitting data. The transmitting circuit includes a digital interface circuit configured to obtain, in a predetermined bandwidth, data to be sent, and decompose the data into N parallel sub digital signal flows; a digital modulation circuit configured to modulate the N sub digital signal flows to obtain N modulated signals; a frequency relocation circuit configured to perform frequency relocation on the N modulated signals; a synthesizer configured to modulate M modulated signals of the N modulated signals that have undergone frequency relocation into a bandwidth signal; a digital to analog converter configured to receive the bandwidth signal, and perform digital to analog conversion on the bandwidth signal to obtain an analog signal; an up-conversion circuit configured to receive the analog signal, and convert the analog signal into a radio frequency signal.

TECHNICAL FIELD

The present invention relates to the field of communications, and in particular, to a transmitting circuit, a transceiver, a communication system, and a method for transmitting data.

BACKGROUND

A radio communication system has an increasingly higher requirement on bandwidth. An E-Band microwave technology has won popularity from a medium-and-long distance high-speed wireless point-to-point system because it has a bandwidth of 10 gigahertz (GHz) (71-76 GHz and 81-86 GHz) and is in an atmospheric fading decline. With the upgrading of the technology and processing capabilities of chip, technologies such as a high-performance signal processing technology, and a high-spectral-efficiency modulation and coding technology all have come true, which all require the system to have a highly efficient analog to digital converter (ADC) and digital to analog converter (DAC).

Generally, an ADC/DAC bottleneck caused by a high bandwidth and high speed may be solved using a time domain interleaved sampling method or a frequency domain multichannel sampling method. However, these two methods need complex post-processing on an output signal of the ADC/DAC, which degrades system performance.

In addition, the DAC tends to have a higher speed and a higher precision than the ADC. Therefore, a case where capabilities of the DAC and ADC are asymmetric generally occurs in a communication system. For example, an E-band with the bandwidth of 5 GHz imposes a minimum requirement of as a high as 10 gigasample-per-second (Gsps) on the ADC and the DAC, but the DAC is easier to meet such a high requirement because the processing speed of the DAC is higher than that of the ADC.

SUMMARY

Embodiments of the present invention provide a transmitting circuit, a transceiver, a communication system, and a method for transmitting data, which can reduce the processing complexity of the transceiver, thereby improving system performance.

In one aspect, a transmitting circuit is provided, including a digital interface circuit configured to obtain, in a predetermined bandwidth, first data to be sent, and decompose the first data into N parallel first sub digital signal flows, where a bandwidth occupied by each first sub digital signal flow of the N first sub digital signal flows is smaller than the predetermined bandwidth and N is a positive integer; a digital modulation circuit configured to receive the N first sub digital signal flows, and modulate the N first sub digital signal flows to obtain N first modulated signals; a first frequency relocation circuit configured to receive the N first modulated signals, and perform frequency relocation on the N first modulated signals, where there is no frequency band gap between adjacent first modulated signals of the N first modulated signals that have undergone frequency relocation; a first synthesizer configured to synthesize M first modulated signals of the N first modulated signals that have undergone frequency relocation into a first bandwidth signal, where M is a positive integer; a first digital to analog converter configured to receive the first bandwidth signal, and perform digital to analog conversion on the first bandwidth signal to obtain a first analog signal; and a first up-conversion circuit configured to receive the first analog signal, and convert the first analog signal into a radio frequency signal, so that the radio frequency signal is sent by an antenna.

In another aspect, a transceiver is provided, including a receiving circuit and the foregoing transmitting circuit, where the receiving circuit includes a down-conversion circuit configured to convert a radio frequency signal received on a receiving antenna into an analog signal; an intermediate frequency power divider configured to decompose the analog signal into Q parallel sub analog signal flows; a second frequency relocation circuit configured to perform frequency relocation on the Q parallel sub analog signal flows; Q analog to digital converters configured to perform analog to digital conversion on the Q parallel sub analog signal flows respectively to obtain Q parallel digital signal flows; a digital demodulation circuit configured to perform demodulation processing on the Q parallel digital signal flows to obtain Q parallel demodulated signals; and a digital interface circuit configured to synthesize the Q parallel demodulated signals into second data.

In another aspect, a communication system is provided, where the communication system includes a transmitter and a receiver, where the transmitter includes the foregoing transmitting circuit; and the receiver includes a down-conversion circuit configured to convert a radio frequency signal received on a receiving antenna into an analog signal; an intermediate frequency power divider configured to decompose the analog signal into N parallel sub analog signal flows; a second frequency relocation circuit configured to perform frequency relocation on the N parallel sub analog signal flows; N analog to digital converters configured to perform analog to digital conversion on the N parallel sub analog signal flows respectively to obtain N parallel digital signal flows; a digital demodulation circuit configured to perform demodulation processing on the N parallel digital signal flows to obtain N parallel demodulated signals; and a digital interface circuit configured to synthesize the N parallel demodulated signals into first data.

In another aspect, a method for transmitting data is provided, including obtaining, in a predetermined bandwidth, first data to be sent, and decomposing the first data into N parallel first sub digital signal flows, where a bandwidth occupied by each first sub digital signal flow of the N first sub digital signal flows is smaller than the predetermined bandwidth and N is a positive integer; modulating the N first sub digital signal flows to obtain N first modulated signals; performing frequency relocation on the N first modulated signals, where there is no frequency band gap between adjacent first modulated signals of the N first modulated signals that have undergone frequency relocation; synthesizing M first modulated signals of the N first modulated signals that have undergone frequency relocation into a first bandwidth signal, where M is a positive integer; performing digital to analog conversion on the first bandwidth signal to obtain a first analog signal; and converting the first analog signal into a radio frequency signal, so that the radio frequency signal is sent by an antenna.

In another aspect, a method for transmitting data is provided, including a method for receiving data and the foregoing method for transmitting data, where the method for receiving data includes converting a radio frequency signal received on a receiving antenna into an analog signal; decomposing the analog signal into Q parallel sub analog signal flows; performing frequency relocation on the Q parallel sub analog signal flows; performing analog to digital conversion on the Q parallel sub analog signal flows respectively to obtain Q parallel digital signal flows; performing demodulation processing on the Q parallel digital signal flows to obtain Q parallel demodulated signals; and synthesizing the Q parallel demodulated signals into second data.

In another aspect, a communication method is provided, including a method for receiving data and the foregoing method for transmitting data, where the method for receiving data includes converting a radio frequency signal received on a receiving antenna into an analog signal; decomposing the analog signal into N parallel sub analog signal flows; performing frequency relocation on the N parallel sub analog signal flows; performing analog to digital conversion on the N parallel sub analog signal flows respectively to obtain N parallel digital signal flows; performing demodulation processing on the N parallel digital signal flows to obtain N parallel demodulated signals; and synthesizing the N parallel demodulated signals into first data.

The transmitting circuit in the technical solution can decompose data into multiple parallel sub digital signal flows, perform modulation and frequency relocation on the multiple sub digital signal flows respectively, and then synthesize the multiple sub digital signal flows into a large bandwidth signal; further, the transmitting circuit converts the large bandwidth signal into an analog signal using a digital to analog converter, and finally converts the analog signal into a radio frequency signal through up-conversion. Because the embodiments of the present invention can divide a large bandwidth into multiple subbands and can process multiple sub digital signal flows at a transmitting end and a receiving end independently, no complex post-processing needs to be performed on the analog signal after the digital to analog conversion is performed, which can reduce the processing complexity, thereby improving system performance.

DESCRIPTION OF EMBODIMENTS

It should be understood that the technical solution of the present invention may be applied to various communication systems, for example, a Global System of Mobile communication (GSM) system, a Code Division Multiple Access (CDMA) system, a Wideband Code Division Multiple Access (WCDMA) system, a General Packet Radio Service (GPRS), a Long Term Evolution (LTE) system, a Long Term Evolution-Advanced (LTE-A) system, a Universal Mobile Telecommunication System (UMTS), and the like.

The embodiments of the present invention may be applied to wireless networks of different standards. A radio access network may include different network elements in different systems. For example, network elements of the radio access network on LTE and LTE-A include an evolved base station (eNB, eNodeB), network elements of the radio access network on WCDMA include a radio network controller (RNC) and a base station (NodeB). Similarly, other wireless networks such as Worldwide Interoperability for Microwave Access (WiMAX) may also use a solution similar to that provided in the embodiments of the present invention, with only a slight difference in related modules of the base station system, which is not limited in the embodiments of the present invention.

The embodiments of the present invention provide an implementation solution of a high-speed millimetric wave (an E-Band in particular) system, which may be applied to a backhaul technology of microwave communication. The application scope of this implementation solution is not limited thereto according to the embodiments of the present invention, and the implementation solution may also be applied to other microwave or radio communication systems, for example, a wireless point-to-point system and the like.

When a time domain interleaved sampling method or a frequency domain multichannel sampling method is used to solve an ADC/DAC bottleneck caused by a high bandwidth and high speed, complex post-processing needs to be performed on an output signal of the ADC/DAC, and a transmitted signal is easily distorted, making it difficult to ensure system performance. The foregoing two methods have a very high requirement for DAC/ADC synchronization, which makes it more difficult to perform joint control on multiple DACs/ADCs.

FIG. 1is a schematic circuit diagram of a transmitting circuit100according to a first embodiment of the present invention. The transmitting circuit100includes a digital interface circuit110, a digital modulation circuit120, a first frequency relocation circuit130, a first synthesizer140, a first digital to analog converter150, and an up-conversion circuit160.

The digital interface circuit110obtains, in a predetermined bandwidth, first data to be sent, and decomposes the first data into N parallel first sub digital signal flows, where a bandwidth occupied by each first sub digital signal flow of the N first sub digital signal flows is smaller than the predetermined bandwidth and N is a positive integer. The digital modulation circuit120receives the N first sub digital signal flows, and modulates the N first sub digital signal flows to obtain N first modulated signals. The first frequency relocation circuit130receives the N first modulated signals, and performs frequency relocation on the N first modulated signals, where there is no frequency band gap between adjacent first modulated signals of the N first modulated signals that have undergone frequency relocation. The first synthesizer140is configured to synthesize M first modulated signals of the N first modulated signals that have undergone frequency relocation into a first bandwidth signal, where M is a positive integer. The first digital to analog converter150is configured to receive the first bandwidth signal, and perform digital to analog conversion on the first bandwidth signal to obtain a first analog signal. The first up-conversion circuit160receives the first analog signal, and converts the first analog signal into a radio frequency signal, so that the radio frequency signal is sent by an antenna.

According to the embodiment of the present invention, a predetermined bandwidth can be divided into N subbands, and each subband is processed independently, that is, each subband is sent and received independently. That is, N sub digital signal flows can be processed independently in a transmission channel of the transmitting circuit, and at least some sub digital signal flows of the N sub digital signal flows whose frequency bands are continuous are synthesized into one data flow. In addition, digital to analog conversion is performed on the data flow to obtain an analog signal; after the analog signal obtained by conversion is processed using an analog circuit, the analog signal is sent through a transmitting antenna.

At a transmitting end, the digital interface unit decomposes a single data flow or multiple data flows into multiple parallel data flows (that is, multiple sub digital signal flows). For example, the digital interface unit may decompose one piece of 4-bit data of a user into four 1-bit sub digital signal flows, or decompose two pieces of 2-bit data of a user into four 1-bit sub digital signal flows. Then, a digital modulator performs digital modulation on the N sub digital signal flows to obtain N first modulated signals with the same frequency. For example, the digital modulation circuit may perform modulation on the N sub digital signal flows respectively using N Field Programmable Gate Arrays (FPGAs). The first frequency relocation circuit may perform frequency relocation on the N first modulated signals respectively using N frequencies to obtain N modulated signals with continuous frequencies without a frequency band gap. For example, the first frequency relocation circuit may perform frequency relocation on the N first modulated signals using N frequency mixers and corresponding N local oscillators. The first synthesizer synthesizes at least some modulated signals of the N modulated signals into a large bandwidth signal. A high-speed DAC performs digital to analog conversion on the large bandwidth signal, and sends the converted signal through the up-conversion circuit. Because each subband is processed independently at the transmitting end, each subband can be split at the receiving end using a band-pass filter, and subbands are sampled by a low-speed ADC to obtain the sub digital signal flows; finally, digital modulation is performed on the sub digital signal of each subband independently.

It should be understood that bandwidths occupied by the first sub digital signal flows may be equal or unequal and M may be smaller than or equal to N. For example, when M is smaller than N, some sub digital signal flows are synthesized into a large bandwidth signal; when M is equal to N, all the sub digital signal flows are synthesized into a large bandwidth signal.

The transmitting circuit according to the embodiment of the present invention can decompose data into multiple parallel sub digital signal flows, perform modulation and frequency relocation on the multiple sub digital signal flows respectively, and then synthesize the multiple sub digital signal flows into a large bandwidth signal; further, the transmitting circuit converts the large bandwidth signal into an analog signal using a digital to analog converter, and finally converts the analog signal into a radio frequency signal through up-conversion. Because the embodiment of the present invention can divide a large bandwidth into multiple subbands and can process multiple sub digital signal flows at a transmitting end and a receiving end independently, no complex post-processing needs to be performed on the analog signal after the digital to analog conversion is performed, which can reduce the signal processing complexity of a transceiver, thereby improving system performance.

Because there is no frequency band gap between the multiple modulated signals that have undergone frequency relocation, spectral utilization is increased.

In addition, at the transmitting end, multiple subchannels use only one high-speed DAC and one analog intermediate frequency circuit, thereby saving devices and costs of the transmitting circuit.

According to the embodiment of the present invention, the first synthesizer140may include an adder, where the adder is configured to add the N first modulated signals that have undergone frequency relocation, to synthesize the modulated signals into a first bandwidth signal.

According to the embodiment of the present invention, N may be at least 4. The value of N is not limited thereto according to the embodiment of the present invention, and N may also be smaller than 4. In addition, the first data may be at least one binary digital signal flow.

FIG. 2is a schematic circuit diagram of a transmitting circuit200according to a second embodiment of the present invention. The transmitting circuit provided in the embodiment inFIG. 2may use more than two synthesizers and digital to analog converters.

The transmitting circuit inFIG. 2includes a digital interface circuit210, a digital modulation circuit220, a first frequency relocation circuit230, a first synthesizer240, a first digital to analog converter250, and an up-conversion circuit260, which are similar to the digital interface circuit110, the digital modulation circuit120, the first frequency relocation circuit130, the first synthesizer140, the first digital to analog converter150, and the up-conversion circuit160inFIG. 1and are not further described herein.

The transmitting circuit200inFIG. 2further includes a second synthesizer270and a second digital to analog converter280.

The second synthesizer270synthesizes L first modulated signals of the N first modulated signals that have undergone frequency relocation into a second bandwidth signal, where the L first modulated signals are different from the M first modulated signals, that is, the L first modulated signals are signals other than the M first modulated signals of the N first modulated signals and L is a positive integer. The second digital to analog converter280receives the second bandwidth signal, and performs digital to analog conversion on the second bandwidth signal to obtain a second analog signal; the up-conversion circuit260is configured to receive the first analog signal and the second analog signal, and synthesize the first analog signal and the second analog signal into a radio frequency signal.

For example, the first frequency relocation circuit may perform frequency relocation on the N first modulated signals respectively using N frequencies with the same gap, so that bandwidths of the N first modulated signals that have undergone frequency relocation are continuous, that is, bandwidths of the N first modulated signals are adjacent. The first frequency relocation circuit may also perform frequency relocation on the L first modulated signals respectively using L frequencies with the same gap, while perform frequency relocation on the M first modulated signals respectively using M frequencies with the same gap. In this case, the first analog signal and the second analog signal may have bandwidth overlapping or a frequency gap.

Optionally, as another embodiment, the up-conversion circuit260may also perform frequency relocation on the first analog signal and the second analog signal respectively before synthesizing the first analog signal and the second analog signal into the radio frequency signal.

For example, in a case where the first analog signal and the second analog signal have bandwidth overlapping or a frequency band gap, frequency relocation may be further performed on the first analog signal and the second analog signal, so that the bandwidths of the first analog signal and the second analog signals that have undergone frequency relocation are continuous and do not have a frequency gap or overlapping.

FIG. 3is a schematic circuit diagram of a transmitting circuit300according to a third embodiment of the present invention. The transmitting circuit provided in the embodiment inFIG. 3includes a transmitting circuit corresponding to each antenna of multiple antennas (for example, a first antenna and a second antenna), so that a multi-antenna system can be supported. Each unit of a transmitting circuit corresponding to the first antenna has the same function as each unit of a transmitting circuit corresponding to the second antenna.

Corresponding to the first antenna, the transmitting circuit300inFIG. 3includes a digital interface circuit310, a digital modulation circuit320, a first frequency relocation circuit330, a first synthesizer340, a first digital to analog converter350, and a first up-conversion circuit360, which are similar to the digital interface circuit110, the digital modulation circuit120, the first frequency relocation circuit130, the first synthesizer140, the first digital to analog converter150, and the up-conversion circuit160inFIG. 1and are not further described herein.

According to the embodiment of the present invention, corresponding to the second antenna, the digital interface circuit310further obtains, in the predetermined bandwidth, second data to be sent, and decomposes the second data into N parallel second sub digital signal flows, where a bandwidth occupied by each second sub digital signal flow of the N second sub digital signal flows is smaller than the predetermined bandwidth. As an embodiment, M may be equal to N; the digital modulation circuit320further receives the N second sub digital signal flows, and modulates the N second sub digital signal flows to obtain N second modulated signals.

Corresponding to the second antenna, the transmitting circuit300inFIG. 3further includes a second frequency relocation circuit370, a second synthesizer380, a second digital to analog converter390, and a second up-conversion circuit395.

The second frequency relocation circuit370receives the N second modulated signals, and performs frequency relocation on the N second modulated signals, where there is no frequency band gap between adjacent second modulated signals of the N second modulated signals that have undergone frequency relocation. The second synthesizer380synthesizes the N second modulated signals that have undergone frequency relocation into a second bandwidth signal. The second digital to analog converter390receives the second bandwidth signal, and performs digital to analog conversion on the second bandwidth signal to obtain a second analog signal. The first up-conversion circuit360receives a first analog signal, and converts the first analog signal into a first radio frequency signal, so that the first radio frequency signal is sent by the first antenna. The second up-conversion circuit395receives the second analog signal, and converts the second analog signal into a second radio frequency signal, so that the second radio frequency signal is sent by the second antenna.

According to the embodiment of the present invention, the digital modulation circuit320includes N modulators, where the N modulators modulate the N first sub digital signal flows respectively and modulate the N second sub digital signal flows respectively.

For example, the modulators may be implemented using an FGPA, and digital modulation is performed, using the same FPGA, on the first sub digital signal flows corresponding to the first antenna and the second sub digital signal flows corresponding to the second antenna. That is, a first modulated signal and a second modulated signal output from the same FPGA can be output to a frequency mixer that performs frequency relocation using the same frequency. Due to independence of each frequency domain subchannel, highly complex digital processing devices and FPGAs may be distributed in multiple different DSP/FPGA chips/boards, thereby making the implementation easier and more flexible.

When M=N, sub digital signal flows of the first data corresponding to the first antenna or sub digital signal flows of the second data corresponding to the second antenna are synthesized into a large bandwidth signal, and digital to analog conversion is performed on the large bandwidth signal using a DAC. That is, at the transmitting end, all subchannels corresponding to each antenna use only one high speed DAC and one analog intermediate frequency circuit, thereby saving devices and costs of the transmitting circuit.

FIG. 4is a schematic circuit diagram of a transmitting circuit400according to a fourth embodiment of the present invention. The transmitting circuit provided in the embodiment inFIG. 4includes transmitting circuits corresponding to multi-polarized antennas (for example, an H-polarized antenna and a V-polarized antenna), so that a multi-polarized antenna system can be supported.

The transmitting circuit400inFIG. 4includes a digital interface circuit410, a digital modulation circuit420, a first frequency relocation circuit430, a first synthesizer440, a first digital to analog converter450, and a first up-conversion circuit460, which are similar to the digital interface circuit110, the digital modulation circuit120, the first frequency relocation circuit130, the first synthesizer140, the first digital to analog converter150, and the up-conversion circuit160inFIG. 1and are not further described herein.

A transmitting antenna of the transmitting circuit400is a dual-polarized antenna; the digital modulation circuit420modulates the N first sub digital signal flows on the H-polarized antenna, and preferably M=N.

The digital interface circuit410further obtains, in the predetermined bandwidth, second data to be sent, and decomposes the second data into K parallel second sub digital signal flows, where a bandwidth occupied by each second sub digital signal flow of the K second sub digital signal flows is smaller than the predetermined bandwidth and K is a positive integer.

The digital modulation circuit420further receives the K second sub digital signal flows, and modulates the K second sub digital signal flows on a V-polarized antenna to obtain K second modulated signals.

The transmitting circuit400further includes a second digital modulation circuit425, a second frequency relocation circuit470, a second synthesizer480, a second digital to analog converter490, a second up-conversion circuit495, and a coupler465.

The second digital modulation circuit425receives the K second sub digital signal flows, and modulates the K second sub digital signal flows on the V-polarized antenna to obtain K second modulated signals; the second frequency relocation circuit470receives the K second modulated signals, and performs frequency relocation on the K second modulated signals, where there is no frequency band gap between adjacent second modulated signals of the K second modulated signals that have undergone frequency relocation; the second synthesizer synthesizes the K second modulated signals that have undergone frequency relocation into a second bandwidth signal; the second digital to analog converter490receives the second bandwidth signal, and performs digital to analog conversion on the second bandwidth signal to obtain a second analog signal, where the first up-conversion circuit460receives the first analog signal, and converts the first analog signal into a first radio frequency signal. The second up-conversion circuit495receives the second analog signal, and converts the second analog signal into a second radio frequency signal. The coupler465couples the first radio frequency signal and the second radio frequency signal, so that the first radio frequency signal and the second radio frequency signal are sent by the dual-polarized antenna respectively.

According to the embodiment of the present invention, the digital modulation circuit420includes N+K modulators, where the N modulators modulate the N first sub digital signal flows respectively and the K modulators modulate the K second sub digital signal flows respectively and N may be equal to K.

FIG. 5is a schematic circuit diagram of a transceiver500according to a fifth embodiment of the present invention. The transceiver500includes a receiving circuit and a transmitting circuit. The transmitting circuit inFIG. 5may include a digital interface circuit510, a digital modulation circuit520, a first frequency relocation circuit530, a first synthesizer540, a first digital to analog converter550, and an up-conversion circuit560, which are similar to the digital interface circuit110, the digital modulation circuit120, the first frequency relocation circuit130, the first synthesizer140, the first digital to analog converter150, and the up-conversion circuit160inFIG. 1and are not further described herein.

The receiving circuit may include a down-conversion circuit595, an intermediate frequency power divider590, a second frequency relocation circuit580, and N analog to digital converters570.

The down-conversion circuit595converts a radio frequency signal received on a receiving antenna into an analog signal. The intermediate frequency power divider590decomposes the analog signal into N parallel sub analog signal flows. The second frequency relocation circuit580performs frequency relocation on the N parallel sub analog signal flows. The N analog to digital converters570perform analog to digital conversion on the N parallel sub analog signal flows respectively to obtain N parallel digital signal flows. The digital demodulation circuit525performs demodulation processing on the N parallel digital signal flows to obtain N parallel demodulated signals. The digital interface circuit510synthesizes the N parallel demodulated signals into second data.

According to the embodiment of the present invention, data can be decomposed into multiple parallel sub digital signal flows; modulation and frequency relocation are performed on the multiple sub digital signal flows respectively, and then the multiple sub digital signal flows are synthesized into a large bandwidth signal; further, the large bandwidth signal is converted into an analog signal using a digital to analog converter, and finally the analog signal is converted into a radio frequency signal through up-conversion. Because the embodiment of the present invention can divide a large bandwidth into multiple subbands and can process multiple sub digital signal flows at a transmitting end and a receiving end independently, no complex post-processing needs to be performed on the analog signal after the digital to analog conversion is performed, which can reduce the signal processing complexity of a transceiver, thereby improving system performance.

According to the embodiment of the present invention, a requirement for an ADC may be reduced in a frequency domain subchannel sampling manner at a receiving end; and subchannels in a digital domain are divided at a transmitting end, so that the receiving end can process each independent frequency domain subchannel. On one hand, each frequency domain subchannel can transmit data independently, thereby increasing a system flexibility. On the other hand, due to independence of each frequency domain subchannel, highly complex digital processing devices and FPGAs may be distributed in multiple different DSP/FPGA chips/boards. Meanwhile, only one high speed DAC and one analog transmission intermediate frequency circuit are used, thereby saving related devices and costs.

FIG. 6is a schematic circuit diagram of a communication system600according to a sixth embodiment of the present invention. The communication system600includes a transmitter and a receiver.

The transmitter inFIG. 6includes the transmitting circuit inFIG. 1,FIG. 2,FIG. 3, orFIG. 4. The transmitting circuit includes a digital interface circuit610, a digital modulation circuit620, a first frequency relocation circuit630, a first synthesizer640, a first digital to analog converter650, and an up-conversion circuit660, which are similar to the digital interface circuit110, the digital modulation circuit120, the first frequency relocation circuit130, the first synthesizer140, the first digital to analog converter150, and the up-conversion circuit160inFIG. 1and are not further described herein.

The receiver includes a down-conversion circuit665, an intermediate frequency power divider655, a second frequency relocation circuit645, Q analog to digital converters635, a digital demodulation circuit625, and a digital interface circuit615.

The down-conversion circuit665converts a radio frequency signal received on a receiving antenna into an analog signal. The intermediate frequency power divider655decomposes the analog signal into Q parallel sub analog signal flows. The second frequency relocation circuit645performs frequency relocation on the Q parallel sub analog signal flows. The Q analog to digital converters635perform analog to digital conversion on the Q parallel sub analog signal flows respectively to obtain Q parallel digital signal flows. The digital demodulation circuit625performs demodulation processing on the Q parallel digital signal flows to obtain Q parallel demodulated signals. The digital interface circuit615synthesizes the Q parallel demodulated signals into first data, where Q may be equal to N in applications.

According to the embodiment of the present invention, data can be decomposed into multiple parallel sub digital signal flows; modulation and frequency relocation are performed on the multiple sub digital signal flows respectively, and then the multiple sub digital signal flows are synthesized into a large bandwidth signal; further, the large bandwidth signal is converted into an analog signal using a digital to analog converter, and finally the analog signal is converted into a radio frequency signal through up-conversion. Because the embodiment of the present invention can divide a large bandwidth into multiple subbands and can process multiple sub digital signal flows at a transmitting end and a receiving end independently, no complex post-processing needs to be performed on the analog signal after the digital to analog conversion is performed, which can reduce the signal processing complexity of a transceiver, thereby improving system performance.

According to the embodiment of the present invention, a requirement for an ADC may be reduced in a frequency domain subchannel sampling manner at a receiving end; and subchannels in a digital domain are divided at a transmitting end, so that the receiving end can process each independent frequency domain subchannel. On one hand, each frequency domain subchannel can transmit data independently, thereby increasing a system flexibility. On the other hand, due to independence of each frequency domain subchannel, highly complex digital processing devices and FPGAs may be distributed in multiple different DSP/FPGA chips/boards. Meanwhile, only one high speed DAC and one analog transmission intermediate frequency circuit are used, thereby saving related devices and costs.

The embodiments of the present invention are described in more detail with reference to specific examples.FIG. 10is a schematic circuit diagram of a transceiver according to a tenth embodiment of the present invention.FIG. 12is a schematic circuit diagram of a synthesizer according to an embodiment of the present invention. The transceiver inFIG. 10is an example of the transceiver inFIG. 5.

Referring toFIG. 10, a transmitting circuit of the transceiver includes one DAC, while a receiving circuit of the transceiver includes N ADCs, that is, the number of ADCs is N times the number of DACs. The transceiver may be divided into three parts: a digital modulation and demodulation part, an analog intermediate frequency part, and an analog radio frequency part. The following describes a working principle of the transceiver in detail using the analog intermediate frequency part and the analog radio frequency part as an example.

Referring toFIG. 10, at a transmitting end, a digital interface circuit1001obtains data in a predetermined bandwidth (for example, 5 GHz), and decomposes the data into N parallel sub digital signal flows, where a bandwidth occupied by each sub digital signal flow is smaller than the predetermined bandwidth. For example, if data with a total bandwidth of 5 GHz is decomposed into four digital signal flows (that is, four subchannels), the bandwidth of each sub digital signal flow is 1.25 GHz. For example, a piece of 4-bit data may be divided into four pieces of 1-bit sub digital signal flows, or two pieces of 2-bit data may be divided into four pieces of 1-bit sub digital signal flows, where the four pieces of 1-bit sub digital signal flows are transmitted in four subchannels respectively.

A digital modulation circuit formed by N (for example, four) FPGAs1002to1005receives the N sub digital signal flows, and modulates the N sub digital signal flows to obtain N modulated signals, where the N FPGAs1002to1005correspond to the N sub digital signal flows one by one. According to the embodiment of the present invention, the digital modulation circuit may also be implemented using an application specific integrated circuit (ASIC) and the like.

The working principle of the digital modulation circuit is as follows: N sub digital signal flows are processed independently using the N FPGAs1002to1005. Each FPGA has the same function, and the FPGA processing (in a single carrier or multicarrier modulation manner) on the sub channels mainly implement modulation on digital signals. The modulation on the digital signal flows includes but is not limited to channel coding, symbol mapping modulation, orthogonal frequency-division multiplexing (OFDM) modulation, pulse shaping, sampling rate conversion, pre-emphasis, pre-equalization, peak-to-average ratio suppression, and the like. Each FPGA may include an encoding module configured to encode input digital signal flows, for example configured to perform low-density parity-check (LDPC) coding; a constellation point mapping module configured to map the input sub digital signal flows to corresponding constellation points, for example, 64 phase quadrature amplitude modulation (QAM); an inverse fast Fourier transform (IFFT) module configured to perform inverse fast Fourier transform on the input sub digital signal flows to convert frequency domain signals into time domain signals; a window adding module configured to add a time domain window and a frequency domain window to the input time domain signals simultaneously or separately; a framing module configured to insert a preamble sequence into signals to implement a framing function; and a sampling rate converting module configured to convert a sampling rate into a sampling rate of the DAC. Through digital modulation by the FPGAs, the center frequency of a modulated signal output by each FPGA is 1.2 GHz, and a bandwidth occupied by useful signals is 0.5750 GHz to 1.8250 GHz.

A frequency relocation circuit formed by N frequency mixers1006to1009and N local oscillators f1to fNreceives the N modulated signals, and performs frequency mixing and frequency relocation on the N modulated signals. For example, assuming that N=4, if the center frequency of the modulated signal output by each FPGA is 1.2 GHz and the local oscillators choose frequencies f1=0 GHz, f2=1.25 GHz, f3=2.5 GHz, and f4=3.75 GHz, after the frequency relocation is performed, the center frequencies of modulated signals output by the frequency mixers1006to1009are changed to 1.2 GHz, 1.45 GHz, 3.6 GHz, and 4.95 GHz respectively, with the total occupied frequency band of 0.5750 GHz to 5.5750 GHz, and there is no frequency band gap between adjacent modulated signals.

The synthesizer1010synthesizes the N second modulated signals that have undergone frequency relocation into a large bandwidth signal. Referring toFIG. 12, the synthesizer1010may include an adder1210and an SINC function1220. The synthesizer1010adds data flow1to data flow N (the N modulated signals that have undergone frequency relocation). For example, assuming that N=4, and f1=0 GHz, f2=1.25 GHz, f3=2.5 GHz, and f4=3.75 GHz, the four subbands are synthesized into a large bandwidth signal of 5 GHz, that is, 0.5750 GHz to 5.5750 GHz. The SINC function1220is configured to compensate the synthesized large bandwidth signal, and output the compensated signal to a DAC1011.

The DAC1011receives the large bandwidth signal from the synthesizer1010, performs digital to analog conversion on the large bandwidth signal, and outputs the output analog signal to an up-conversion circuit.

The up-conversion circuit receives the analog signal output by the DAC1011, and converts the analog signal into a radio frequency signal, so that the radio frequency signal is sent by an antenna. The up-conversion circuit may include an up-conversion of the intermediate frequency part and an up-conversion of the analog radio frequency part. In the analog intermediate frequency part, the analog signal output by the DAC1011undergoes an analog intermediate frequency modulation (that is, a first up-conversion) by a frequency mixer1012and a local oscillator fIF, and then is filtered by a band pass filter (BPF)1013, and is further amplified by an amplifier1014; finally, the amplified analog signal is output to the analog radio frequency part. In the analog radio frequency part, the analog signal output by the analog intermediate frequency part undergoes an up-conversion (that is, a second up-conversion) by a frequency mixer1015and a local oscillator fRF, and then is amplified by an amplifier1016, and is further filtered by a BPF1017; after the analog signal is amplified by an amplifier1018, the amplified analog signal is transferred by a duplexer1019to an antenna1020for transmission.

At the receiving end, the antenna1020receives a radio frequency signal from a peer transmitter, where the radio frequency signal enters, through the duplexer1019, a receiving circuit of the transceiver, and then is filtered by a BPF1049; the radio frequency signal is further amplified by an amplifier1048, and finally undergoes a down-conversion by a frequency mixer1047and the local oscillator fRFto obtain an analog intermediate frequency signal.

The analog intermediate frequency signal is divided by an intermediate frequency power divider1046to obtain N parallel sub analog signal flows with N same frequencies and transmitted in N subchannels respectively. The sub analog signal flows are respectively amplified by amplifiers1042to1045, filtered by BPFs1038to1041, then relocated, through frequency relocation (intermediate frequency down-conversion) by frequency mixers1034to1037and local oscillators f1′ to fN′, to a desired frequency, and finally, filtered by BPFs1030to1033. Sub analog signals that have undergone intermediate frequency processing have the same frequency, which means that the frequency of each sub analog signal is the same as that of each signal output by the FPGAs of the transmitting end.

Multiple parallel sub data flows that have undergone intermediate frequency processing are sampled by their respective ADCs1026-1029to obtain sub digital signal flows (that is, discrete sampling signals) of the subchannels, and the sub digital signal flows are output to a digital demodulation circuit formed by N FPGAs1022-1025for demodulation.

The working principle of the digital demodulation circuit is as follows. Sub digital signal flows of the subchannels are processed by their respective FPGAs to obtain a sending bit decision signal corresponding to each sub digital signal flow. The FPGA processing of the subchannels mainly implement demodulation on digital signals, including a single carrier or multicarrier modulation manner. The demodulation on the digital signals includes but is not limited to channel estimation, coding demodulation, sampling rate conversion, synchronization, equalization, and the like. Each FPGA may include a sampling rate converting module configured to convert an ADC sampling rate into a sampling rate of a symbol rate; an automatic gain controlling module configured to estimate an input signal power, and adjust a gain of an analog device; a frame synchronizing module configured to implement a frame synchronization function; a frequency deviation estimating and compensating module configured to estimate and compensate a carrier frequency deviation and a sampling frequency deviation; an FFT module configured to convert a time domain signal into a frequency domain signal; a channel estimating module configured to perform channel estimation to implement correlation detection on signals; a residual frequency deviation estimating and compensating module configured to estimate and compensate a residual carrier frequency deviation and a sampling frequency deviation; a phase noise eliminating module configured to eliminate phase noise caused by radio frequency devices; and a decoding module configured to implement data decoding.

The sending bit decision signals of multiple subchannels that have been processed by the FPGA are synthesized by a digital interface circuit1001to obtain a high speed receiving decision signal.

According to the embodiment of the present invention, a requirement for an ADC may be reduced in a frequency domain subchannel sampling manner at a receiving end; and subchannels in a digital domain are divided at a transmitting end, so that the receiving end can process each independent frequency domain subchannel. On one hand, each frequency domain subchannel can transmit data independently, thereby increasing a system flexibility. On the other hand, due to independence of each frequency domain subchannel, highly complex digital processing devices and FPGAs may be distributed in multiple different DSP/FPGA chips/boards. Meanwhile, only one high speed DAC and one analog transmission intermediate frequency circuit are used, thereby saving related devices and costs.

FIG. 11is a schematic circuit diagram of a transceiver according to an eleventh embodiment of the present invention. A transmitting circuit in the transceiver inFIG. 11is an example of the embodiment inFIG. 2.

Different from the embodiment inFIG. 10, the transmitting circuit of the transceiver inFIG. 11may include M DACs, while a receiving circuit of the transceiver inFIG. 11includes N×M ADCs, that is, the number of ADCs is N times the number of DACs.

Referring toFIG. 11, at a transmitting end, a digital interface circuit1101obtains data in a predetermined bandwidth (for example, 5 GHz), and decomposes the data into M×N parallel sub digital signal flows, where a bandwidth occupied by each sub digital signal flow is smaller than the predetermined bandwidth. For example, if data with a total bandwidth of 5 GHz is decomposed into 2×N sub digital signal flows (that is, 2×N subchannels), the bandwidth of each sub digital signal flow is 5/(2×N) GHz.

A digital modulation circuit formed by 2×N FPGAs1102to1105receives the 2×N sub digital signal flows, and modulates the 2×N sub digital signal flows to obtain 2×N modulated signals, where the 2×N FPGAs1102to1105correspond to the 2×N sub digital signal flows one by one. The center frequency of a modulated signal output by each FPGA is 1.2 GHz (assuming that N=2), and the bandwidth occupied by useful signals is 0.5750 GHz to 1.8250 GHz.

A frequency relocation circuit formed by N frequency mixers1106to1107and N local oscillators f1to fNreceives N modulated signals output by the N FPGAs1102to1103, and performs frequency mixing and frequency relocation on the N modulated signals. A frequency relocation circuit formed by another N frequency mixers1108to1109and N local oscillators whose frequencies are f1to fNreceives N modulated signals output by the N FPGAs1104to1105, and performs frequency mixing and frequency relocation on the N modulated signals. For example, assuming that N=2, if the center frequency of the modulated signal output by each FPGA is 1.2 GHz and the local oscillators choose frequencies f1=0 GHz and f2=1.25 GHz, after the frequency relocation is performed, center frequencies of modulated signals output by the frequency mixers1106to1109are changed to 1.2 GHz, 2.45 GHz, 1.2 GHz, and 2.45 GHz respectively.

A synthesizer1110synthesizes the N modulated signals that have undergone frequency relocation by the N frequency mixers1006to1007into a large bandwidth signal. A synthesizer1110′ synthesizes the N modulated signals that have undergone frequency relocation by the N frequency mixers1008to1009into a large bandwidth signal. For example, assuming that N=2, and f1−0 GHz and f2=1.25 GHz, the synthesizer1110and the synthesizer1110′ synthesize their two subbands into a large bandwidth signal of 2.5 GHz respectively, that is, 0.5750 GHz to 3.0750 GHz, and there is no frequency band gap between adjacent modulated signals.

A DAC1111and a DAC1112receive the two large bandwidth signals from the synthesizer1110and the synthesizer1110′ respectively, perform digital to analog conversion on the two large bandwidth signals to obtain analog signals, and output the analog signals to an up-conversion circuit.

The up-conversion circuit receives the analog signals output by the DAC1111and the DAC1112, and converts the analog signals into radio frequency signals, so that the radio frequency signals are sent by an antenna. In the analog intermediate frequency part, the analog signals output by the DAC1111the DAC1112respectively are filtered by a BPF1113and a BPF1114, and undergo intermediate frequency up-conversion and frequency relocation by a frequency mixer1115and a local oscillator g1and a frequency mixer1116and a local oscillator gm; then the analog signals are filtered by a BPF1117and a BPF1118, and are further amplified by an amplifier1119and an amplifier1120; finally, after the two analog signals output and amplified by the amplifier1119and the amplifier1120are synthesized by an intermediate frequency power synthesizer1116, the two analog signals are output to the analog radio frequency part, where a difference between g1and gmis 2.5 GHz, so that the intermediate frequency power synthesizer1116synthesizes the two analog signals into a large bandwidth signal of 5 GHz, that is, 0.5750 GHz to 5.5750 GHz. The analog radio frequency part inFIG. 11includes a frequency mixer1121, a local oscillator fc, an amplifier1122, a BPF1123, and an amplifier1124, which are similar to the units of the analog radio frequency part inFIG. 10and are not further described herein. Finally, the analog signals output by the analog radio frequency part are transferred through a duplexer1125to an antenna1126for transmission.

An amplifier1127, a frequency mixer1128and a local oscillator fc, an intermediate frequency power divider1129, amplifiers1130to1133, BPFs1134to1137, BPFs1142to1145, ADCs1146to1149and FPGAs1150to1153of the receiving circuit in the transceiver inFIG. 11have functions similar to those of the units of the receiving circuit inFIG. 10, which are not further described herein. The receiving circuit inFIG. 11is different from the receiving circuit inFIG. 10in that frequency mixers1138to1139and a local oscillators whose frequency is f1+g1perform frequency relocation on analog signals output by the BPFs1134to1135, while frequency mixers1140to1141and a local oscillator whose frequency is fm+gmperform frequency relocation on analog signals output by the BPFs1136to1137.

FIG. 7AandFIG. 7Bare respectively schematic circuit diagrams of a transmitting circuit and a receiving circuit according to a seventh embodiment of the present invention. The transmitting circuit and the receiving circuit inFIG. 7AandFIG. 7Bare an example of the embodiment inFIG. 4.

The transmitting circuit of the embodiment inFIG. 7Amodulates a large bandwidth signal on an H-polarized antenna and a V-polarized antenna respectively to obtain an H-polarized signal and a V-polarized signal, and then sends the H-polarized signal and the V-polarized signal through a dual-polarized antenna. The receiving circuit inFIG. 7Breceives the H-polarized signal and the V-polarized signal from the dual-polarized antenna and demodulates the H-polarized signal and the V-polarized signal.

An antenna720of the transmitting circuit and an antenna770of the receiving circuit are dual-polarized antennas. A digital modulation circuit modulates N sub digital signal flows on the H-polarized antenna and the V-polarized antenna respectively. The embodiment inFIG. 7Aincludes a DAC711and a DAC731that correspond to the H-polarized antenna and the V-polarized antenna respectively.

Referring toFIG. 7A, at a transmitting end, corresponding to the H-polarized antenna, a digital interface circuit701obtains data in a predetermined bandwidth (for example, 5 GHz), and decomposes the data into N parallel sub digital signal flows. Similarly, corresponding to the DAC731, the digital interface circuit701can obtain N sub digital signal flows.

A transmitting circuit corresponding to the H-polarized antenna includes N FPGAs702to705, N frequency mixers706to709, local oscillators whose frequencies are f1to fN, a synthesizer710, the DAC711, a frequency mixer712, a local oscillator whose frequency is fIF, a BPF713, an amplifier714, a frequency mixer715, a local oscillator whose frequency is fRF, an amplifier716, a BPF717, and an amplifier718. Functions of these units are similar to those of the corresponding units of the transmitting circuit inFIG. 10, which are not further described herein. A transmitting circuit corresponding to the V-polarized antenna includes N FPGAs722to725, N frequency mixers726to729, local oscillators whose frequencies are f1to fN, a synthesizer730, the DAC731, a frequency mixer732, a local oscillator whose frequency is fIF, a BPF733, an amplifier734, a frequency mixer735, a local oscillator whose frequency is fRF, an amplifier736, a BPF737, and an amplifier738. Similarly, functions of these units are similar to those of the corresponding units of the transmitting circuit inFIG. 10, which are not further described herein. The transmitting circuit inFIG. 7Ais different from the transmitting circuit inFIG. 10in that the amplifier718and the amplifier738send the H-polarized signal and the V-polarized signal to a coupler (orthomode transducer (OMT))719respectively, and the coupler719converts the H-polarized signal and the V-polarized signal into a dual-polarized signal, and outputs the dual-polarized signal to a dual-polarized antenna720.

Referring toFIG. 7B, at a receiving end, a coupler769converts a dual-polarized signal received from a dual-polarized antenna770into an H-polarized signal and a V-polarized signal.

A receiving circuit corresponding to the H-polarized antenna includes a BPF768, an amplifier767, a frequency mixer766, and a local oscillator fRF, an intermediate frequency power divider765, amplifiers761to764, BPFs757to760, frequency mixers753to756, local oscillators whose frequencies are f1′ to fN′, BPFs749to752, ADCs745to748, and FPGAs741to744. These units are similar to the units of the receiving circuit inFIG. 10, which are not further described herein. A receiving circuit corresponding to the V-polarized antenna includes a BPF798, an amplifier797, a frequency mixer796, and a local oscillator fRF, an intermediate frequency power divider795, amplifiers791to794, BPFs787to790, frequency mixers783to786, local oscillators whose frequencies are f1′ to fN′, BPFs779to782, ADCs775to778, and FPGAs771to774. These units are similar to the units of the receiving circuit inFIG. 10, which are not further described herein. The receiving circuit inFIG. 7Bis different from the receiving circuit inFIG. 10in that the coupler769receives a dual-polarized signal from the dual-polarized antenna770, converts the dual-polarized signal into an H-polarized signal and a V-polarized signal, and outputs the H-polarized signal and the V-polarized signal to a BPF768and a BPF798respectively.

FIG. 8AandFIG. 8Bare respectively schematic circuit diagrams of a transmitting circuit and a receiving circuit according to an eighth embodiment of the present invention. The transmitting circuit and the receiving circuit inFIG. 8AandFIG. 8Bare an example of the embodiment inFIG. 3.

The transmitting circuit in the embodiment inFIG. 8Acorresponds to multiple antennas antenna 1819to antenna M839, and the receiving circuit inFIG. 8Bcorresponds to multiple antennas antenna 1869to antenna N899.

At a transmitting end, a large bandwidth signal is modulated on each antenna, and then the modulated signal is sent through each antenna. At a receiving end, multiple signals are received and demodulated on each antenna.

Referring toFIG. 8A, at a transmitting end, corresponding to each antenna, a digital interface circuit801obtains data in a predetermined bandwidth (for example, 5 GHz), and decomposes the data into N parallel sub digital signal flows.

Corresponding to antenna 1, a transmitting circuit includes N FPGAs802to805, N frequency mixers806to809, local oscillators whose frequencies are f1to fN, a synthesizer810, a DAC811, a frequency mixer812, a local oscillator whose frequency is fIF, a BPF813, an amplifier814, a frequency mixer815, a local oscillator whose frequency is fRF, an amplifier816, a BPF817, and an amplifier818. Functions of these units are similar to those of the corresponding units of the transmitting circuit inFIG. 10, which are not further described herein. Corresponding to antenna M, a transmitting circuit includes N FPGAs802to805, N frequency mixers826to829, local oscillators whose frequencies are f1to fN, a synthesizer830, a DAC831, a frequency mixer832, a local oscillator whose frequency is fIF, a BPF833, an amplifier834, a frequency mixer835, a local oscillator whose frequency is fRF, an amplifier836, a BPF837, and an amplifier838. Functions of these units are similar to those of the corresponding units of the transmitting circuit inFIG. 10, which are not further described herein. The transmitting circuit inFIG. 8Ais different from the transmitting circuit inFIG. 10in that the amplifier818and the amplifier838output a radio frequency signal to antenna 1 and antenna M respectively.

As can be seen from the above, sub digital signal flows of the transmitting circuit corresponding to antenna 1 and sub digital signal flows of the transmitting circuit corresponding to antenna M undergo digital modulation using the same FPGAs. For example, two modulated signals output by the FPGA802are output to the frequency mixer806and the frequency mixer826respectively, and two modulated signals output by the FPGA803are output to the frequency mixer807and the frequency mixer827respectively, and the like.

Referring toFIG. 8B, at a receiving end, a receiving circuit corresponding to antenna 1 includes a BPF868, an amplifier867, a frequency mixer866, and a local oscillator fRF, an intermediate frequency power divider865, amplifiers861to864, BPFs857to860, frequency mixers853to856, local oscillators whose frequencies are f1′ to fN′, BPFs849to852, ADCs845to848, and FPGAs841to844. These units are similar to the units of the receiving circuit inFIG. 10, which are not further described herein. A receiving circuit corresponding to antenna N includes a BPF898, an amplifier897, a frequency mixer896, and a local oscillator fRF, an intermediate frequency power divider895, amplifiers891to894, BPFs887to890, frequency mixers883to886, local oscillators whose frequencies are f1′ to fN′, BPFs879to882, ADCs875to878, and FPGAs841to844. These units are similar to the units of the receiving circuit inFIG. 10, which are not further described herein. The receiving circuit inFIG. 8Bis different from the transmitting circuit inFIG. 10in that the BPF868and the BPF898receive a radio frequency signal from antenna 1 and antenna N respectively.

As can be seen from the above, sub digital signal flows of the receiving circuit corresponding to antenna 1 and sub digital signal flows of the receiving circuit corresponding to antenna N undergo digital demodulation using the same FPGAs. For example, the ADC845and the ADC875each output a digital signal to the FPGA841for digital demodulation, and the ADC846and the ADC876each output a digital signal to the FPGA842for digital demodulation, and the like.

FIG. 9AandFIG. 9Bare respectively schematic circuit diagrams of a transmitting circuit and a receiving circuit according to a ninth embodiment of the present invention. The transmitting circuit and the receiving circuit inFIG. 9Aare an example of a combination ofFIG. 3andFIG. 4.

The embodiment inFIG. 9Aincludes transmitting circuits corresponding to multiple dual-polarized antennas dual-polarized antenna 1 to dual-polarized antenna M, and the embodiment inFIG. 9Bincludes receiving circuits corresponding to multiple dual-polarized antennas dual-polarized antenna 1 to dual-polarized antenna N. In addition, the transmitting circuit corresponding to each dual-polarized antenna modulates a large bandwidth signal on an H-polarized antenna and a V-polarized antenna respectively to obtain an H-polarized signal and a V-polarized signal, and sends the H-polarized signal and the V-polarized signal through the dual-polarized antenna, and the receiving circuit corresponding to each dual-polarized antenna receives the H-polarized signal and the V-polarized signal from the dual-polarized antenna and demodulates the H-polarized signal and the V-polarized signal.

At a transmitting end, a transmitting circuit corresponding to dual-polarized antenna 1 includes a transmitting circuit corresponding to the H-polarized antenna and a transmitting circuit corresponding to the V-polarized antenna. The transmitting circuit corresponding to the H-polarized antenna includes N FPGAs902to905, N frequency mixers906to909, local oscillators whose frequencies are f1to fN, a synthesizer910, a DAC911, a frequency mixer912, a local oscillator whose frequency is fIF, a BPF913, an amplifier914, a frequency mixer915, a local oscillator whose frequency is fRF, an amplifier916, a BPF917, and an amplifier918. The amplifier918is connected to a coupler919, and the coupler919is connected to an antenna920. Functions of these units are similar to those of the corresponding units of the transmitting circuit inFIG. 7A, which are not further described herein. The transmitting circuit corresponding to the V-polarized antenna includes N FPGAs902′ to905′, N frequency mixers926to929, local oscillators whose frequencies are f1to fN, a synthesizer930, a DAC931, a frequency mixer932, a local oscillator fIF, a BPF933, an amplifier934, a frequency mixer935, a local oscillator whose frequency is fRF, an amplifier936, a BPF937, and an amplifier938. The amplifier938is connected to the coupler919, and the coupler919is connected to the antenna920. Functions of these units are similar to those of the corresponding units of the transmitting circuit inFIG. 7B, which are not further described herein.

At the transmitting end, the transmitting circuit corresponding to dual-polarized antenna M includes a transmitting circuit corresponding to the H-polarized antenna and a transmitting circuit corresponding to the V-polarized antenna. The transmitting circuit corresponding to the H-polarized antenna includes N FPGAs902to905, N frequency mixers906′ to909′, local oscillators whose frequencies are f1to fN, a synthesizer910′, a DAC911′, a frequency mixer912′, a local oscillator fIF, a BPF913′, an amplifier914′, a frequency mixer915′, a local oscillator whose frequency is fRF, an amplifier916′, a BPF917′, and an amplifier918′. The amplifier918′ is connected to a coupler919′, and the coupler919′ is connected to an antenna920′. Functions of these units are similar to those of the corresponding units of the transmitting circuit inFIG. 7A, which are not further described herein. The transmitting circuit corresponding to the V-polarized antenna includes N FPGAs902′ to905′, N frequency mixers926′ to929′, local oscillators whose frequencies are f1to fN, a synthesizer930′, a DAC931′, a frequency mixer932′, a local oscillator fIF, a BPF933′, an amplifier934′, a frequency mixer935′, a local oscillator whose frequency is fRF, an amplifier936′, a BPF937′, and an amplifier938′. The amplifier938′ is connected to the coupler919′, and the coupler919′ is connected to the antenna920′. Functions of these units are similar to those of the corresponding units of the transmitting circuit inFIG. 7B, which are not further described herein.

At a receiving end, the receiving circuit corresponding to dual-polarized antenna 1970includes a receiving circuit corresponding to the H-polarized antenna and a receiving circuit corresponding to the V-polarized antenna. The receiving circuit corresponding to the H-polarized antenna includes a BPF968, an amplifier967, a frequency mixer966, and a local oscillator fRF, an intermediate frequency power divider965, amplifiers961to964, BPFs957to960, frequency mixers953to956, local oscillators whose frequencies are f1′ to fN′, BPFs949to952, ADCs945to948, and FPGAs941to944. These units are similar to the units of the receiving circuit inFIG. 7A, which are not further described herein. The receiving circuit corresponding to the V-polarized antenna includes a BPF998, an amplifier997, a frequency mixer996, and a local oscillator far, an intermediate frequency power divider995, amplifiers991to994, BPFs987to990, frequency mixers983to986, local oscillators whose frequencies are f1′ to fN′, BPFs979to982, ADCs975to978, and FPGAs941′ to944′. These units are similar to the units of the receiving circuit inFIG. 7B, which are not further described herein.

At the receiving end, the receiving circuit corresponding to dual-polarized antenna N970′ includes a receiving circuit corresponding to the H-polarized antenna and a receiving circuit corresponding to the V-polarized antenna. The receiving circuit corresponding to the H-polarized antenna includes a BPF968′, an amplifier967′, a frequency mixer966′, and a local oscillator fRF, an intermediate frequency power divider965′, amplifiers961′ to964′, BPFs957′ to960′, frequency mixers953′ to956′, local oscillators whose frequencies are f1′ to fN′, BPFs949′ to952′, ADCs945′ to948′, and FPGAs941′ to944′. These units are similar to the units of the receiving circuit inFIG. 7B, which are not further described herein. The receiving circuit corresponding to the V-polarized antenna includes a BPF998′, an amplifier997′, a frequency mixer996′, and a local oscillator far, an intermediate frequency power divider995′, amplifiers991′ to994′, BPFs987′ to990′, frequency mixers983′ to986′, local oscillators whose frequencies are f1′ to fN′, BPFs979′ to982′, ADCs975′ to978′, and FPGAs941′ to944′. These units are similar to the units of the receiving circuit inFIG. 7B, which are not further described herein.

The transmitting circuit, the transceiver, and the communication system according to the embodiments of the present invention have been described above. The following describes a method for transmitting data and a method for transmitting data according to the embodiments of the present invention with reference toFIG. 13toFIG. 15.

FIG. 13is a schematic flowchart of a method for transmitting data according to a twelfth embodiment of the present invention. The method for transmitting data includes the following content:

1310. Obtain, in a predetermined bandwidth, first data to be sent, and decompose the first data into N parallel first sub digital signal flows, where a bandwidth occupied by each first sub digital signal flow of the N first sub digital signal flows is smaller than the predetermined bandwidth and N is a positive integer.

1320. Modulate the N first sub digital signal flows to obtain N first modulated signals.

1330. Perform frequency relocation on the N first modulated signals, so that there is no frequency band gap between adjacent first modulated signals of the N first modulated signals that have undergone frequency relocation.

1340. Synthesize M first modulated signals of the N first modulated signals that have undergone frequency relocation into a first bandwidth signal, where M is a positive integer.

1350. Perform digital to analog conversion on the first bandwidth signal to obtain a first analog signal.

1360. Convert the first analog signal into a radio frequency signal, so that the radio frequency signal is sent by an antenna.

According to the embodiment of the present invention, data can be decomposed into multiple parallel sub digital signal flows; modulation and frequency relocation are performed on the multiple sub digital signal flows respectively, and then the multiple sub digital signal flows are synthesized into a large bandwidth signal; further, the large bandwidth signal is converted into an analog signal using a digital to analog converter, and finally the analog signal is converted into a radio frequency signal through up-conversion. Because the embodiment of the present invention can divide a large bandwidth into multiple subbands and can process multiple sub digital signal flows at a transmitting end and a receiving end independently, no complex post-processing needs to be performed on the analog signal after the digital to analog conversion is performed, which can reduce the signal processing complexity of a transceiver, thereby improving system performance.

Optionally, as another embodiment, the method inFIG. 13further includes synthesizing L first modulated signals of the N first modulated signals that have undergone frequency relocation into a second bandwidth signal, where the L first modulated signals are different from the M first modulated signals; and performing digital to analog conversion on the second bandwidth signal to obtain a second analog signal; in1306, the first analog signal and the second analog signal may be synthesized into the radio frequency signal.

Optionally, as another embodiment, the method inFIG. 13further includes performing frequency relocation on the first analog signal and the second analog signal respectively before synthesizing the first analog signal and the second analog signal into the radio frequency signal.

Optionally, as another embodiment, the method inFIG. 13further includes obtaining, in the predetermined bandwidth, second data to be sent, and decomposing the second data into N parallel second sub digital signal flows, where a bandwidth occupied by each second sub digital signal flow of the N second sub digital signal flows is smaller than the predetermined bandwidth and M=N; modulating the N second sub digital signal flows to obtain N second modulated signals, performing frequency relocation on the N second modulated signals, where there is no frequency band gap between adjacent second modulated signals of the N second modulated signals that have undergone frequency relocation; synthesizing the N second modulated signals that have undergone frequency relocation into a second bandwidth signal; and performing digital to analog conversion on the second bandwidth signal to obtain a second analog signal; in1360, the first analog signal is converted into a first radio frequency signal, so that the first radio frequency signal is sent by a first antenna, and the second analog signal is converted in a second radio frequency signal, so that the second radio frequency signal is sent by a second antenna.

In1320, the N first sub digital signal flows may be modulated using N modulators, and the N second sub digital signal flows may be modulated using the N modulators.

According to the embodiment of the present invention, the antenna is a dual-polarized antenna, in1320, the N first sub digital signal flows may be modulated on an H-polarized antenna, where M=N. The method inFIG. 13further includes obtaining, in the predetermined bandwidth, second data to be sent, and decomposing the second data into K parallel second sub digital signal flows, where a bandwidth occupied by each second sub digital signal flow of the K second sub digital signal flows is smaller than the predetermined bandwidth and K is a positive integer; modulating the K second sub digital signal flows on a V-polarized antenna to obtain K second modulated signals; performing frequency relocation on the K second modulated signals, where there is no frequency band gap between adjacent second modulated signals of the K second modulated signals that have undergone frequency relocation; synthesizing the K second modulated signals that have undergone frequency relocation into a second bandwidth signal; and performing digital to analog conversion on the second bandwidth signal to obtain a second analog signal; in1360, the first analog signal may be converted into a first radio frequency signal and the second analog signal is received, and the second analog signal is converted into a second radio frequency signal; and the first radio frequency signal and the second radio frequency signal are coupled, so that the first radio frequency signal and the second radio frequency signal are sent by the dual-polarized antenna.

In1320, the N first sub digital signal flows may be modulated using N modulators, and the K second sub digital signal flows may be modulated using K modulators.

In1340, the N first modulated signals that have undergone frequency relocation may be added using an adder to synthesize the modulated signals into a first bandwidth signal.

According to the embodiment of the present invention, N is at least 4, and the first data is at least one binary digital signal flow.

FIG. 14is a schematic flowchart of a method for transmitting data according to a thirteenth embodiment of the present invention.

The method for transmitting data inFIG. 14includes a method for receiving data and the method for transmitting data inFIG. 13, where the method for receiving data includes the following content.

1410. Convert a radio frequency signal received on a receiving antenna into an analog signal.

1420. Decompose the analog signal into Q parallel sub analog signal flows.

1430. Perform frequency relocation on the Q parallel sub analog signal flows.

1440. Perform analog to digital conversion on the Q parallel sub analog signal flows respectively to obtain Q parallel digital signal flows.

1450. Perform demodulation processing on the Q parallel digital signal flows to obtain Q parallel demodulated signals.

1460. Synthesize the Q parallel demodulated signals into second data, where Q may be equal to N in applications.

According to the embodiment of the present invention, data can be decomposed into multiple parallel sub digital signal flows; modulation and frequency relocation are performed on the multiple sub digital signal flows respectively, and then the multiple sub digital signal flows are synthesized into a large bandwidth signal; further, the large bandwidth signal is converted into an analog signal using a digital to analog converter, and finally the analog signal is converted into a radio frequency signal through up-conversion. Because the embodiment of the present invention can divide a large bandwidth into multiple subbands and can process multiple sub digital signal flows at a transmitting end and a receiving end independently, no complex post-processing needs to be performed on the analog signal after the digital to analog conversion is performed, which can reduce the signal processing complexity of a transceiver, thereby improving system performance.

FIG. 15is a schematic flowchart of a communication method according to a fourteenth embodiment of the present invention.

The communication method inFIG. 15includes a method for receiving data and the method for transmitting data inFIG. 13, where the method for receiving data includes the following content.

1510. Convert a radio frequency signal received on a receiving antenna into an analog signal.

1520. Decompose the analog signal into N parallel sub analog signal flows.

1530. Perform frequency relocation on the N parallel sub analog signal flows.

1540. Perform analog to digital conversion on the N parallel sub analog signal flows respectively to obtain N parallel digital signal flows.

1550. Perform demodulation processing on the N parallel digital signal flows to obtain N parallel demodulated signals.

1560. Synthesize the N parallel demodulated signals into first data.

According to the embodiment of the present invention, data can be decomposed into multiple parallel sub digital signal flows; modulation and frequency relocation are performed on the multiple sub digital signal flows respectively, and then the multiple sub digital signal flows are synthesized into a large bandwidth signal; further, the large bandwidth signal is converted into an analog signal using a digital to analog converter, and finally the analog signal is converted into a radio frequency signal through up-conversion. Because the embodiment of the present invention can divide a large bandwidth into multiple subbands and can process multiple sub digital signal flows at a transmitting end and a receiving end independently, no complex post-processing needs to be performed on the analog signal after the digital to analog conversion is performed, which can reduce the signal processing complexity of a transceiver, thereby improving system performance.

Compared with the technical solution in the prior art where a processing speed of a DAC/ADC is increased using a frequency domain method or a time domain method, the embodiments of the present invention have a lower complexity during signal processing, signals are not easily distorted, and no joint control on multiple DACs/ADCs exists. Compared with the technical solution where a signal bandwidth is reduced in the prior art, the present invention reduces the number of DACs and requirements for analog intermediate frequency processing devices of a transmitting end. Compared with the existing frequency domain multichannel technology, the present invention does not need to reserve a guard space between each channel. In addition, frequency bands can be divided freely without restriction, and the system features powerful scalability. Furthermore, the embodiments of the present invention provide a complete one-to-one sending and receiving solution, and support a system with multi-polarized antennas and/or multiple antennas.