Method for manufacturing semiconductor device and molded structure

There is provided a method for manufacturing a semiconductor device, including: forming an interconnection layer over a support base; mounting a plurality of semiconductor chips over the interconnection layer; molding the plurality of semiconductor chips with resin; forming an alignment mark in the resin; and obtaining a molded structure by removing the interconnection layer, the plurality of semiconductor chips and the resin from the support base after forming the alignment mark.

BACKGROUND

1. Technical Field

The present invention relates to a method for manufacturing a semiconductor device and a molded structure.

2. Related Art

Japanese Laid-open patent publication NO. 2005-216989 discloses a method for manufacturing a multi-chip module, which includes an interconnection layer forming process for forming a module interconnection layer having an insulating layer and an interconnection layer which are laminated and serves as a module interconnection board, on a temporary support board such as a silicon wafer, a molding process for sealing a plurality of semiconductor elements mounted on the module interconnection layer formed in the interconnection layer forming process with a molding resin, and a temporary support board removing process for removing the temporary support board from the body sealed with the molding resin to obtain the multi-chip module. It is described that with this configuration, it is possible to achieve a multi-layered and thin film interconnection layer as a module interconnection board on which semiconductor elements are mounted, at low cost, thereby making it possible to manufacture a thin multi-chip module.

A semiconductor wafer such as a silicon wafer is typically provided with an alignment mark such as a notch (V-shaped notch), an orientation flat and so on. Such an alignment mark allows adjustment of misalignment in a θ direction (rotational direction of a substrate) of the semiconductor wafer.

SUMMARY OF THE INVENTION

In the related art, however, when the temporary support board such as the silicon wafer is removed from the body sealed with the molding resin, there is no alignment mark on the molding resin-sealed body and the alignment of the molding resin-sealed body after the removal of the temporary support board could not be simply and conveniently carried out.

In one embodiment, there is provided a method for manufacturing a semiconductor device, including:

forming an interconnection layer over a support base;

mounting a plurality of semiconductor chips over the interconnection layer;

molding the plurality of semiconductor chips with resin;

forming an alignment mark in the resin; and

obtaining a molded structure by removing the interconnection layer, the plurality of semiconductor chips and the resin from the support base after forming the alignment mark.

In another embodiment, there is provided a molded structure including:

an interconnection layer;

a plurality of semiconductor chips mounted over the interconnection layer; and

resin formed to mold the plurality of semiconductor chips,

wherein an alignment mark is formed in the resin.

With the above configuration, since the alignment mark is formed in the resin after the support base is removed from the interconnection layer, it is possible to easily carry out the alignment of the molded structure.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. Throughout the drawings, like elements are denoted by like reference numerals and explanation of which will not be repeated.

First Embodiment

This embodiment includes a process of mounting a plurality of semiconductor elements (semiconductor chips) on a wafer-shaped support base while forming circuits thereon, molding the circuits and the semiconductor elements with a molding resin (resin), and removing a body molded with the molding resin from the support base to obtain a molded structure such as a wafer-shaped multi-chip module or the like, and a process of forming an alignment mark on the molding resin.

FIGS. 1A to 1Care top views showing interim steps of a sequence of manufacturing a semiconductor device102according to this embodiment.

FIG. 1Ashows a state where an interconnection layer120is disposed on a support base200and a plurality of semiconductor chips150is additionally disposed in a flat state on the interconnection layer120. Here, the support base200has a circular shape. The support base200is provided with an alignment mark201. The alignment mark201may be configured as, for example, a cut portion. The support base200may be made of, for example, glass, quartz glass, sapphire, aluminum nitride, silicon or the like. In this embodiment, the support base200may be provided as a semiconductor wafer. In this case, the alignment mark201may be typically configured as a notch (V-shape notch), an orientation flat or the like, provided in the semiconductor wafer. Since the interconnection layer120is disposed on the support base200, a shape of the alignment mark201on the support base200is also reflected in the interconnection layer120.

FIG. 1Bshows a state where a molding resin160is formed on the interconnection layer120and the plurality of semiconductor chips150and the interconnection layer120are sealed by the molding resin160. Here, the molding resin160may be formed to have substantially the same shape as the support base200when seen in a plan view from above. That is, in this embodiment, the molding resin160may be formed to have the same circular shape as the semiconductor wafer.

In addition, an alignment mark162is provided in the molding resin160at a position at which the alignment mark162overlaps with an alignment mark201on the support base200when seen in a plan view. The alignment mark162may have the same shape as the alignment mark201on the support base200. That is, the alignment mark162may have the same shape as, for example, a cut portion, a notch or an orientation flat which is typically provided in the semiconductor wafer, or the like. The same shape used herein includes substantially the same shape as the alignment mark201. The substantial same shape used herein may refer to the sameness so much to carry out an alignment based on the alignment mark162with an existing apparatus having an alignment mechanism to align a semiconductor wafer using, for example, a notch or an orientation flat provided in a conventional semiconductor wafer.

FIG. 1Cshows a state where the support base200is removed from the interconnection layer120, the plurality of semiconductor chips150and the molding resin160. In this embodiment, the alignment mark162is formed in the molding resin160at a position corresponding to the alignment mark201on the support base200. Accordingly, an alignment of the semiconductor chips150, the molded structure100and the interconnection layer120can be achieved even when the support base200is removed after the semiconductor chips150are sealed with the molding resin160.

In this embodiment, the alignment mark162may be configured to allow for the use of various existing alignment mechanisms for detecting misalignment in a θ direction of the semiconductor wafer. With this configuration, even after the support base200is removed, the alignment mark162may be used to detect misalignment in the θ direction of the molded structure100with various existing alignment mechanisms for alignment of the molded structure100. Accordingly, for example, the alignment can be easily carried out when the molding resin160is cut to sectionalize the semiconductor chips150.

In addition, when the semiconductor chips150are arranged on the support base200, the arrangement of the semiconductor chips150in the θ direction depends on the position of the alignment mark201on the support base200. In this embodiment, by providing the alignment mark162on the molding resin160at the position corresponding to the alignment mark201on the support base200, since the alignment mark162maintains the position relationship in θ direction between the alignment mark201and the semiconductor chips150, the position of the semiconductor chips150in the θ direction can be detected based on the alignment mark162.

Next, a sequence of manufacturing the semiconductor device102will be described with reference to a process sectional view.

FIGS. 2A to 2Dare process sectional views showing one example of a sequence of manufacturing the semiconductor device102according to this embodiment.

First, a removal layer202is formed on the support base200using, for example, a sputtering method, and is then subjected to heat treatment. The removal layer202may be made of a material capable of being dissolved or from which gas is produced due to a chemical reaction caused when the material is irradiated with a laser. Specifically, the removal layer202may be made of, for example, metal oxide, metal nitride, metal oxynitride or the like. Next, a seed layer204is formed on the removal layer202(FIG. 2A). The seed layer204may be made of, for example, CU/Ti or the like and may be formed using a sputtering method. Although not shown, a resist film having a predetermined pattern may be formed on the seed layer204and a circuit pattern may be formed by patterning the seed layer204using the resist film as a mask. After forming the circuit pattern, the resist film may be removed using an organic solvent.

Thereafter, an insulating resin film110is formed on the seed layer204. The insulating resin film110may be, for example, a polyimide layer. The insulating resin film110may be formed by applying and sintering an insulating material. Subsequently, via holes leading to the seed layer204are formed in the insulating resin film110and vias112are formed by filling the via holes with a conductive material using an electroplating method (FIG. 2B). The vias112may be made of, for example, Cu/Ni. In addition, a seed film made of Cu/Ti or the like may be formed on the insulating resin film110using, for example, a sputtering method, and a resist film having a predetermined pattern may be formed thereon. Subsequently, an interconnection114may be formed on the seed film exposed through openings in the resist film using an electroplating method.

Subsequently, the resist film may be removed using an organic solvent. Thereafter, a circuit pattern constituted by the seed film and the interconnection114is formed by patterning the seed film using the interconnection114as a mask (FIG. 2C).

In addition, a solder resist layer116is formed on the interconnection114, via holes leading to the interconnection114are formed in the solder resist layer116, and connection terminals118are formed by filling the via holes with a conductive material. Accordingly, an interconnection layer120is formed, which is constituted by the insulating resin film110, the vias112, the interconnection layer114, the solder resist layer116, the connection terminals118and so on (FIG. 2D).

Thereafter, the plurality of semiconductor chips150is juxtaposed on the interconnection layer120through an underfill122(FIG. 3A).

Thereafter, while the semiconductor chips150are sealed with the molding resin160, in this embodiment, the alignment mark162(seeFIGS. 1B and 1C) is formed on the molding resin160at the same time as when the molding resin160is formed. The molding resin160may be made of, for example, epoxy resin. In this embodiment, a mold used to mold the semiconductor chips150with the molding resin160has a dedicated shape such that the alignment mark162is formed on the molding resin160. Accordingly, the alignment mark162can be automatically formed on the molding resin160when the mold is released.

Hereinafter, the above-described sequence will be described with reference toFIGS. 5A to 5D.

FIG. 5Ais a schematic sectional view showing a state where the interconnection layer120is disposed on the support base200and the plurality of semiconductor chips150is disposed thereon. The removal layer202and so on are not shown in this figure although they are included in the structure. In addition, although this figure shows the semiconductor chips150having different sizes, the plurality of semiconductor chips150may have either the same size or different sizes.FIG. 5Acorresponds to the state shown inFIG. 1A. Subsequently, a mold300is used to form the molding resin160(FIG. 5B). The mold300includes a lower mold302and an upper mold304. The lower mold302of the mold300has a circular concave portion for receiving the circular support base200. The upper mold304of the mold300also has a circular concave portion for forming the molding resin160in a circular shape. Here, as described with reference toFIG. 1B, the upper mold304has a structure in which a convex portion305corresponding to the alignment mark162is formed in the circular concave portion in order to form the alignment mark162in the molding resin160.

Thereafter, when the mold300is detached, a structure where the alignment mark162is formed in the molding resin160may be obtained (FIG. 5C).FIG. 5Ccorresponds to the state ofFIG. 1B. Thereafter, the support base200is removed from the interconnection layer120to obtain the molded structure100(FIG. 5D). This sequence will described with reference toFIG. 3Bagain.

FIG. 3Bshows a state where the semiconductor chips150are sealed with the molding resin160, likeFIG. 5C. Although the alignment mark162is not shown inFIG. 3B, the alignment mark162is formed in the molding resin160in this step.

Subsequently, the support base200is removed from the interconnection layer120(FIG. 3C). At this time, removal occurs at the interface between the removal layer202and the support base200or within the removal layer202due to shrinkage stress of the molding resin160. If a material which is dissolved when irradiated with a laser is used as the removal layer202, the support base200can be removed from the interconnection layer120by irradiating the removal layer202with a laser from the rear side of the support base200. In this case, the support base200may be made of a material through which the laser can penetrate, such as glass or a semiconductor wafer. In this case, gas is generated from the chemical change in the material of the removal layer202due to the irradiation of laser, thereby lowering adhesion and hence producing removal along with the effect of shrinkage stress of the molding resin160. Alternatively, the material of the removal layer202is dissolved (ablated) to produce removal.

Subsequently, the removal layer202and the seed layer204are removed by wet etching or the like using a medicinal fluid (FIG. 4A). This state corresponds to the states ofFIGS. 1C and 5D. Accordingly, the molded structure100can be obtained where the plurality of semiconductor chips150is sealed with the molding resin160. Here, as shown inFIG. 5D, since an alignment mark such as the alignment mark162is formed in the molding resin160, alignment can be easily carried out in later processes.

Thereafter, a solder resist layer170or the like is formed below the interconnection layer120.

Subsequently, solder balls172contacting the vias112are formed (FIG. 4B). Subsequently, the molding resin160is sectionalized for each semiconductor chip150so as to obtain a plurality of semiconductor devices102(FIG. 4C). In this embodiment, since the alignment mark162is formed in the molding resin160, the alignment can be carried out using the alignment mark162when the molded structure100is cut and sectionalized as the plurality of semiconductor devices102.

FIGS. 6A to 6Care views showing another example of the alignment mark162formed on the molding resin160. The alignment mark162may be provided as a through hole as shown inFIGS. 6B and 6C. When such an alignment mark162is used, alignment can be carried out using an optical device. Although a circular through hole (pin hole) is shown here, for example, a rectangular through hole or a linear slit may be likewise employed as long as it can be used for optical alignment.

Next, a particular example of the semiconductor device102to which the alignment mark162is applied will be described in this embodiment.

FIGS. 7A to 7Care process sectional views showing another example of a sequence of manufacturing the semiconductor device102after forming the configuration shown inFIG. 4A.

Here, after forming the configuration shown in FIG.4A, a seed film made of Cu/Ti or the like is formed on the side opposing the side on which the solder resist layer116of the insulating resin film110is formed, using, for example, a sputtering method, and then is patterned using a resist film to form a circuit and an interconnection182. After forming the circuit, the resist film may be removed using an organic solvent.

In addition, a solder resist layer180is formed on the interconnection182, via holes leading to the interconnection182are formed in the solder resist layer180, and connection terminals183are formed by filling the via holes with a conductive material. Thereafter, semiconductor chips184are mounted below the solder resist layer180through an underfill122(FIG. 7B). Here, although not particularly limited, the semiconductor chips184may be provided corresponding to the semiconductor chips150.

Thereafter, solder balls186contacting the connection terminals183are formed. Subsequently, the molding resin160is sectionalized for each semiconductor chip150and each semiconductor chip184so as to obtain a plurality of semiconductor devices102(FIG. 7C). At this time, since the alignment mark162is formed in the molding resin160, the alignment can be carried out using the alignment mark162when the molded structure100is cut and sectionalized as the plurality of semiconductor devices102.

FIGS. 8A to 8Dare process sectional views showing another example of the configuration described with reference toFIGS. 7A to 7C.

Like the description ofFIGS. 7A and 7B, the solder resist layer180, the interconnection182, the connection terminals183, the underfill122and the semiconductor chips184are formed on the side opposing the side on which the solder resist layer116of the insulating resin film110is formed (FIGS. 8A and 8B). Here, a pattern of the interconnection182and the connection terminals183is appropriately designed so as to correspond to the individual semiconductor devices102.

This example is different from the example shown inFIG. 7Bin that the semiconductor chips184are connected to the connection terminals183in the solder resist layer180through a boding wire188(FIG. 8C).

Thereafter, the solder balls186contacting the connection terminals183are formed. Subsequently, the molding resin160is sectionalized for each semiconductor chip150and each semiconductor chip184so as to obtain a plurality of semiconductor devices102(FIG. 8D). At this time, since the alignment mark162is formed in the molding resin160, the alignment can be carried out using the alignment mark162when the molded structure100is cut and sectionalized as the plurality of semiconductor devices102.

According to this embodiment, since the alignment mark162is provided in the molding resin160of the molded structure100, the alignment of the molded structure100can be carried out even after the support base200is removed. Accordingly, misalignment in a θ direction of the molded structure100can be detected without using a fine alignment pattern or the like formed on the interconnection layer120. Accordingly, misalignment in a θ direction of the semiconductor chips150mounted on the interconnection layer120can be adjusted. This allows for a reduction in the time taken to manufacture semiconductor devices, and hence reduction of Turn Around Time (TAT).

In addition, since the alignment mark162provided in the molding resin160have the same shape as a notch, an orientation flat or the like provided in a conventional semiconductor wafer, an existing apparatus having an alignment mechanism for semiconductor wafers can be used without making a special alteration to the apparatus. Accordingly, an alignment can be easily carried out when processes such as, for example, surface treatment of the molding resin, rewiring, chip mounting, BGA mounting, dicing, or the like are performed on the molded structure100after the molded structure100is removed from the support base200.

Second Embodiment

FIGS. 9A to 10Dare views showing a sequence of manufacturing a semiconductor device according to this embodiment.

This embodiment is different from the first embodiment in a method for forming the alignment mark162in the molding resin160. More specifically, this embodiment is different from the first embodiment in that, instead of forming the alignment mark162using a mold, the alignment mark162is formed using a laser or a machining process after the forming of the molding resin160in a mold having no alignment mark162. In this embodiment, after forming the molding resin160using a typical mold, the alignment mark162can be formed using the laser or machining process after the release of the mold or before the removal of the support base200.

FIG. 10Ais a view showing a state where the interconnection layer120is disposed on the support base200and the plurality of semiconductor chips150is additionally disposed on the interconnection layer120. This embodiment has the same configuration as that shown inFIG. 1Ain the first embodiment. A sectional view at this time corresponds toFIG. 9A. Thereafter, in this embodiment, a mold306is used to form the molding resin160on the interconnection layer120and the plurality of semiconductor chips150is sealed with the molding resin160(FIG. 9B). In this embodiment, the mold306includes a lower mold308and an upper mold310. The lower mold308of the mold306has a circular concave portion for receiving the circular support base200. The upper mold310of the mold306also has a circular concave portion for forming the molding resin160in a circular shape. Here, the upper mold310is different from the upper mold304(seeFIG. 5B) in the first embodiment in that the former does not have the convex portion305for forming the alignment mark162in the molding resin160. Thereafter, a molded structure is detached from the mold306(FIG. 9C). A top view at this time corresponds toFIG. 10B. At this time, the alignment mark162is not formed in the molding resin160.

Subsequently, as shown inFIG. 9D, the molding resin160is irradiated with a laser190to form the alignment mark162in the molding resin160. A top view at this time corresponds toFIG. 10C. In this embodiment, the alignment mark162may be, for example, provided as a cut portion such as a notch or an orientation flat, or a through hole such as a pin hole. Here, a portion corresponding to the alignment mark162of the interconnection layer120is removed by the laser190.

Subsequently, the support base200is removed from the interconnection layer120. Accordingly, the molded structure100having the alignment mark162is obtained (FIG. 9E). A top view at this time corresponds toFIG. 10D.

In this embodiment, a removal layer (not here shown) provided between the support base200and the interconnection layer120may be made of a material which is dissolved by the laser190. The support base200can be removed from the molding resin160by irradiation of the laser. When the alignment mark162is formed using the laser190, the support base201can be subsequently removed in the same apparatus.

In this manner, when the alignment mark162is formed using the laser190, a laser wavelength and energy are selected by which the resin of the molding resin160is ablated. At this time, if the support base200is made of a material transparent to the laser wavelength, the support base200may be reused after detaching the support base200from the interconnection layer120. Here, the forming of the alignment mark162and the dissolving of the removal layer are different from each other in terms of the irradiation conditions of the laser190. The dissolving the removal layer requires less power from the laser190.

FIGS. 11A to 11Care sectional views showing another example of the sequence shown inFIGS. 9A to 9E.

AlthoughFIGS. 9A to 9Eshow an example of irradiating the molding resin160with the laser190, if the support base200is made of a material transparent to the laser wavelength of the laser190, as shown inFIG. 11B, the alignment mark162may be formed in the molding resin160by irradiating a rear side of the support base200(the side opposing the side on which the molding resin160is formed) with the laser190. In this case, the support base200may be also reused after detaching the support base200from the interconnection layer120.

In addition, in this example, by forming the alignment mark162and then irradiating the entire surface of the support base200with the laser190from the rear side of the support base200, the process of removing the support base200from the interconnection layer120may be simultaneously performed.

FIGS. 12A to 12Care sectional views showing still another example of the sequence shown inFIGS. 9A to 9E.

Here, as shown inFIG. 12B, the alignment mark162can be formed in the molding resin160using a machining process192. Examples of the machining process192may include a punching process using a drill, or a cutting process using a cutting tool such as a cutter.

While the embodiments of the present invention have been described with reference to the drawings, these embodiments are only by way of example of the present invention, but the present invention may employ other different configurations.

For example, the alignment mark162described in the above embodiments may be formed at any positions on the outer circumference of the molding resin160as long as the alignment mark162is provided at a position corresponding to the alignment mark201on the support base200to allow the molded structure100to maintain the information on the alignment mark201.

In addition, the process of removing the support base200from the interconnection layer120may be performed by immersing the support base200, on which the interconnection layer120, the semiconductor chips150and the molding resin160are formed, in a removal solution. This allows introduction of the removal solution into an interface with the removal layer202for dissolution of the removal layer202.

It is apparent that the present invention is not limited to the above embodiments, and may be modified and changed without departing from the scope and spirit of the invention.