Active photonic device having a Darlington configuration with feedback

An active photonic device having a Darlington configuration is disclosed. The active photonic device has a collector layer over a substrate, a base layer over the collector layer, and an emitter layer over the base layer. A connector structure electrically couples an inner emitter region with an outer base region, wherein the collector layer, base layer, the emitter layer and the connector structure are substantially centered within a first region over the substrate. A feedback resistor is coupled between an inner collector region and an inner base region. At least a portion of the feedback resistor is arc-shaped and resides over a first arcuate path defined by a substantially constant first radius centered in the first region.

FIELD OF THE DISCLOSURE

The present disclosure relates to active photonic devices. In particular, the present disclosure relates to geometric configurations for active photonic devices that are usable as light detectors in optical communication receivers.

BACKGROUND

Fiber optic communication provides a major portion of the backbone of the Internet. As such, photonic devices such as lasers are used for lightwave signal transmission and photodiodes (PDs) are used for lightwave signal reception. These traditional photonic devices have parasitic inductances and parasitic capacitances that limit high frequency operation for high data rate applications such as 10-100 Gbps serial communications that are transmitted and received using lightwave signals. Moreover, a particularly sensitive photodiode, known as an avalanche photodiode (APD), is used in long haul (LH) fiber optic communication and requires a relatively high supply voltage of on the order of 50V and greater for proper operation to achieve high sensitivity enabled by the intrinsic gain of the photodetector device. Thus, what is needed is an active photonic device that has substantially reduced parasitic inductances and reduced parasitic capacitances such that high data rates of 10-100 Gbps and higher are achievable using lightwave signals. Moreover, the needed active photonic device preferably operates with a relatively low supply voltage of around 3V and includes feedback.

SUMMARY

An active photonic device having a Darlington configuration is disclosed. The active photonic device has a collector layer over a substrate, a base layer over the collector layer, and an emitter layer over the base layer. The collector layer includes an inner collector region and an outer collector region that substantially surrounds the inner collector region. The base layer includes an inner base region and an outer base region that substantially surrounds the inner base region and is spaced apart from the inner base region. The emitter layer includes an emitter region that is ring-shaped and resides over and extends substantially around an outer periphery of the inner base region. The emitter layer further includes an outer emitter region that is ring-shaped and resides over and extends substantially around the outer base region. A connector structure electrically couples an inner emitter region with an outer base region, wherein the collector layer, the base layer, the emitter layer, and the connector structure are substantially centered within a first region over the substrate. A feedback resistor is coupled between an inner collector region and an inner base region. At least a portion of the feedback resistor is arc-shaped and resides over a first arcuate path defined by a substantially constant first radius centered in the first region.

DETAILED DESCRIPTION

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. For example, the phrase “substantially centered” means centered within ±10%, and the phrase “substantially constant radius” means a radial length that is maintained to within ± of an average radius. Moreover, the phrase “substantially around” means at least 50% around.

FIG. 1is a symbolic diagram of an active photonic device10of the present disclosure depicted in a common-emitter configuration with feedback.FIG. 2is a symbolic diagram of the active photonic device10depicted in a common-collector configuration with feedback.FIG. 3is a top plan view showing a circular geometry for the common-emitter configuration of the active photonic device10with feedback. It is to be understood that the common-collector configuration has a similar circular geometry with the only exceptions being ground, voltage source, and output terminal connections. Both of the common-emitter and common-collector configurations for the active device10each realize a heterojunction photonic Darlington-transimpedance amplifier (HPD-TIA) opto-electric integrated circuit (OEIC).

Returning toFIG. 1andFIG. 2, the active photonic device10is symbolically represented as having a first transistor Q1with an inner collector C1, an inner base B1, and an inner emitter E1. The first transistor Q1is responsive to light λ such that an increase in light intensity causes an increase in current flow through the first transistor Q1. The active photonic device10is further symbolically represented as having a second transistor Q2with an outer collector C2, an outer base B2, and an outer emitter E2. Both of the common-emitter configuration (FIG. 1) and the common-collector configuration (FIG. 2) of the photonic device10have the inner emitter E1of the first transistor Q1and the outer base B2coupled together to realize a heterojunction photo-Darlington (HPD) transistor configuration12. Moreover, in both configurations the inner collector C1is coupled to the outer collector C2. In some embodiments, the inner collector C1and the outer collector C2are one and the same in that there is no physical isolation between the inner collector C1and the outer collector C2. In the common-emitter configuration (FIG. 1), the outer collector C2is coupled to an output terminal VOUT. In contrast, the common-collector configuration (FIG. 2) has the outer collector C2coupled to ground GND and the output terminal VOUTis coupled to the outer emitter E2.

Both of the common-emitter configuration and the common-collector configuration have a feedback resistor RFB1coupled between the inner base B1and both of the inner collector C1and the outer collector C2. The common-emitter and common-collector configurations each include a bias resistor RBIAS1and an emitter resistor RE2. In the case of the common-emitter configuration, the bias resistor RBIAS1is coupled between the inner emitter E1and ground GND, while the emitter resistor RE2is coupled between the outer emitter E2and ground GND. In contrast, the common-collector configuration has the bias resistor RBIAS1coupled between the inner emitter E1and a negative voltage source VSS, while the emitter resistor RE2is coupled between the outer emitter E2and the negative voltage source VSS.

A base resistor RBB1can be included in both of the common-emitter and common-collector configurations. In the case of the common-emitter configuration, the base resistor RBB1is coupled between the inner base B1and ground GND, whereas in the common-collector configuration, the base resistor RBB1is coupled between the inner base B1and the negative voltage source VSS. The base resistor RBB1in conjunction with feedback resistor RFB1sets a reverse bias voltage across the base-collector junction of the first transistor Q1to maximize intrinsic photonic signal responsivity and bandwidth.

The bias resistor RBIAS1sets a quiescent bias for the first transistor Q1. An exemplary bias current (IBIAS) for the first transistor Q1is approximately a base-to-emitter voltage (Vbe) divided by the resistance of the bias resistor RBIAS1(i.e., IBIAS=Vbe/RBIAS1). Moreover, various levels of current gain between β and β2can be achieved by adjusting a relative bias between the first transistor Q1and the second transistor Q2. The current gain for the active photonic device10can be predetermined by adjusting relative sizes of emitter areas between the first transistor Q1and the second transistor Q2during fabrication. A current gain of approximately two times β (i.e., 2·β) with a single pole response in band can be achieved by making the emitter areas and the bias current of the first transistor Q1and the second transistor Q2equal. In a range close to 2·β, parallel and/or series feedback involving the feedback resistor RFB1and the emitter resistor RE2, respectively, is employable to achieve a desired overall responsivity-bandwidth, a transimpedance gain-bandwidth and/or an optical-electrical gain-bandwidth response.

FIG. 4is a vertical cross-section diagram of the HPD transistor configuration12that is shown symbolically inFIG. 1andFIG. 2. Referring now to bothFIG. 3andFIG. 4, the active photonic device10has a substrate14over which a collector layer16resides. The collector layer16has an inner collector region18and an outer collector region20that substantially surrounds the inner collector region18. A base layer22resides over the collector layer16. The base layer22includes an inner base region24and an outer base region26that substantially surrounds and is spaced apart from the inner base region24. For reference of scale, an exemplary light opening for the inner base region24has a diameter that is on the order of 10 microns. However, in at least one embodiment, the substrate14accepts edge illuminating modulated light signals from the side and guides the data signals to the inner collector region18. In at least another embodiment, the substrate14is translucent to back-side illuminating modulated light signals that pass through the substrate14and into the inner collector region18.

An emitter layer28resides over the base layer22. The emitter layer28includes an inner emitter region30that is ring-shaped and resides over and extends substantially around an outer periphery of the inner base region24. The emitter layer28includes an outer emitter region32that is ring-shaped and resides over and extends substantially around the outer base region26. A connector structure34electrically couples the inner emitter region30with the outer base region26, wherein the collector layer16, base layer22, the emitter layer28, and the connector structure34are substantially centered within a first region38over the substrate14. The connector structure34includes a metal conductor Miothat couples an inner emitter contact Eidisposed on the inner emitter region30to an outer base contact Bodisposed on the outer base region26. An electrical signal corresponding to a light signal is typically output from an outer collector contact CO, which in turn is coupled to the output terminal VOUT. In at least some embodiments, a sub-collector36resides between the substrate14and the collector layer16. An inner base contact Biis in contact with the inner base region24. In the exemplary embodiment, the sub-collector36is negatively doped (n+). In at least some of the embodiments, the collector layer16, the base layer22and the emitter layer28are made of group III-V semiconductor materials.

Referring in particular toFIG. 3, the feedback resistor RFB1is coupled between the outer collector region20and the inner base region24and formed over the substrate14and is outside of the first region38. At least a portion40of the feedback resistor RFB1is arc-shaped and resides over a first arcuate path defined by a substantially constant first radius r1centered in the first region38. In the exemplary embodiment depicted inFIG. 3, the entirety of the feedback resistor RFB1resides in the first arcuate path.

In at least the exemplary embodiment depicted inFIG. 3the base resistor RBB1is coupled between the inner base region24and a fixed voltage node, which in this exemplary case is ground GND. The base resistor RBB1is formed over the substrate14and is outside of the first region38. At least a first portion42of the base resistor RBB1is arc-shaped and resides over a second arcuate path defined by a substantially constant second radius r2that is centered on the first region38. In this exemplary embodiment the substantially constant first radius r1and the substantially constant second radius r2are the same. However, it is to be understood that in other embodiments, the substantially constant first radius r1and the substantially constant second radius r2are different.

In the exemplary embodiment ofFIG. 3, at least a second portion44of the base resistor RBB1is arc-shaped and resides over a third arcuate path defined by a substantially constant third radius r3that is centered over the first region38. Moreover, at least a third portion46of the base resistor RBB1is arc-shaped and resides over a fourth arcuate path defined by a substantially constant fourth radius r4centered over the first region38.

The bias resistor RBIAS1is coupled between the outer base region26and a fixed voltage node, which in this exemplary embodiment is ground GND. The bias resistor RBIAS1is formed over the substrate14and outside of the first region38. The bias resistor RBIAS1is coupled between the outer base region26and a fixed voltage node, which in this exemplary case is ground GND. At least a portion48of the bias resistor RBIAS1is arc-shaped and resides over a fifth arcuate path defined by a substantially constant fifth radius r5centered over the first region38.

The emitter resistor RE2is coupled between the outer emitter region32and a fixed voltage node, which in this exemplary embodiment is ground GND. The emitter resistor RE2is formed over the substrate14and is outside of the first region38. At least a first portion50of the emitter resistor RE2is arc-shaped and resides over a sixth arcuate path defined by a substantially constant sixth radius r6centered over the first region38. The resistors RFB1, RBB1, RBIAS1, and RE2can all be of the thin film type.

Returning toFIG. 4, a positive-intrinsic-negative (p-i-n) region is made up of the inner base region24that is P+ doped, the inner collector region18that is intrinsic and the sub-collector region36that is N+ doped. Intrinsic responsivity and bandwidth of the p-i-n region are calculated based on equations found in Chong, Li et al., “High bandwidth surface-illuminated InGaAs/InP uni-travelling-carrier photodetector,” Chin. Phys. B, Vol. 22, No. 11 (November 2013) 118503, which is incorporated herein by reference.FIG. 5is a nomograph based on intrinsic detector calculations for the HPD transistor configuration12depicted inFIG. 4. Exemplary intrinsic detector calculations assume a vertical indium gallium arsenide (InGaAs) detector, a wavelength of detection of 1.55 μm, and an intrinsic region (i-region) that is undoped. Further assumptions are that the inner collector region18is 4000 Angstroms thick and that a window of detection is 10 μm in diameter. Other assumptions are 100% quantum efficiency and ideal optical coupling. Under these assumptions, the calculations yield a maximum responsivity of approximately 0.324 amperes per Watt (A/W). Transit time bandwidth (Ftransit) and resistance-capacitance (RC) limited bandwidth (FRC) calculations are 112.3 GHz and 78.8 GHz respectively.

In particular,FIG. 5illustrates calculated intrinsic detector bandwidth and maximum responsivity versus collector thickness, Wc. As the collector thickness Wc is increased, the responsivity increases due to increased volume of the detection i-region. As a decrease in intrinsic detector capacitance and an increase in RC-limited bandwidth FRCoccurs, the larger the collector thickness Wc becomes. However, the transit time bandwidth Ftransit decreases with larger Wc. Therefore, a point exists on the graph ofFIG. 5where the transit time and RC-limited bandwidth FRCcalculations are equal. In this exemplary case, points of interest are located along intersections of a vertical line where the collector thickness Wc is 4000 Angstroms. The maximum responsivity found along the vertical line with a collector thickness Wc of 4000 Angstroms is 0.324 A/W and the effective bandwidth is 44.8 GHz.

The HPD transistor configuration12amplifies the intrinsic responsivity by a current gain H21, which is associated with an effective responsivity of the active photonic device10. An effective bandwidth for the active photonic device10can be approximated by calculating the square root of a summation of the RC-limited bandwidth FRC, the transit time bandwidth Ftransit, and a bandwidth associated with current gain H21. An overall opto-electrical integrated circuit (OEIC) response is evaluated by calculating a product of amplifier transimpedance Tz with the intrinsic responsivity of the p-i-n region given in V/W.

FIG. 6is an OEIC response graph for 10 Gbps operation of the active photonic device10. In this example, a bias point is selected to be 3V-13 mA for the active photonic device10. The HPD current gain is 14 with an associated bandwidth of 8 GHz. The effective responsivity of the HPD is approximately 4.48 A/W. The effective transimpedance gain is 155 Ohms with a bandwidth of 12.5 GHz and the overall effective OE Gain is 49 V/W with an effective 12.5 GHz BW.

FIG. 7is an OEIC response graph for 28 Gbs operation of the active photonic device10. The bias point is selected to be 3V-13 mA for the active photonic device10. The HPD current gain is 3.2 with an associated bandwidth of 20 Ghz. The effective HPD responsivity is approximately 1 A/W. The effective transimpedance gain is 77.6 Ohms with a bandwidth of >21 GHz. The overall effective OE Gain is 25 V/W with an effective >21 GHz bandwidth. In at least one embodiment, the active photonic device is configured to receive a modulated light signal with a bit rate of at least 100 Gbps and an electrical signal of at least 100 Gbps. Moreover, in at least some embodiments, the active photonic device10operates at a supply voltage that is between 1 V and 5 V.

FIG. 8is a symbolic diagram of the active photonic device10depicted in a p-i-n Darlington common-emitter configuration with feedback, andFIG. 9is a symbolic diagram of the active photonic device10depicted in a p-i-n Darlington common-collector configuration with feedback. In both configurations, an alternative HPD transistor configuration52includes a p-i-n diode D1that has an anode coupled between the inner base B1and the inner collector C1. Also, both schematics ofFIG. 8andFIG. 9show that the p-i-n diode is effectively in parallel with the feedback resistor RFB1.

FIG. 10is a vertical cross-section diagram of an alternate embodiment of the alternative HPD transistor configuration52that is shown symbolically inFIG. 8andFIG. 9. The p-i-n Darlington transistor configuration includes the p-i-n diode D1, which is made up of a middle P+ region54and a middle i-region56that resides between the sub-collector region36and the middle P+ region54. The p-i-n diode D1is substantially centered within the first region38. A middle connector structure58couples the anode of the p-i-n diode D1to the inner base region24. The middle connector structure58has a middle contact Bmthat is in contact with the middle P+ region54and a metal bridge Mimthat couples the middle contact Bmto the inner base region24through the inner base contact B. A first gap surrounding the p-i-n diode D1provides isolation from the inner collector region18, and a second gap surrounding the inner collector region18provides isolation from the outer collector region20.

FIG. 11is a symbolic diagram of an embodiment of the active photonic device10in which an HPD transistor configuration60includes a built-in current monitor in the form of a third transistor Q3. The built-in current monitor is usable to align a fiber optic cable with light responsive regions of the active photonic device10. The third transistor Q3comprising the built-in current monitor has a base B3coupled to the emitter E1of the first transistor Q1. The third transistor Q3also has a collector C3that is coupled to a current monitoring (IMON) terminal External devices (not shown) can be coupled to the current monitoring terminal IMONto provide feedback to a human technician that aligns an optical data transmitter with the active photonic detector10. In operation, a more strongly coupled light source will generate more current flow through the IMONterminal. In contrast, poor alignment will lead to less current flow through the IMONterminal. A third emitter resistor RE3coupled between a fixed voltage node and an emitter E3of the third transistor Q3, is usable to bias the third transistor Q3for operation at a desired operating point. The fixed voltage node in this exemplary case is ground. The third resistor R3can be constructed along a arcuate path similar to the arcuate paths defined by substantially constant radii r1-r6depicted inFIG. 3. The third resistor R3can be fabricated using thin film technology.

FIG. 12is a simplified top view diagram of a photodetector array62made up of a plurality of the active photonic device10having the built-in current monitor60. An ohmic contact64coupled to the collector layer16(FIG. 10) is polygon-shaped in at least one embodiment. In an exemplary embodiment, the ohmic contact64is hexagonal shaped. The collector layer16is represented by a dashed circle because in this exemplary embodiment a light signal is received from the backside. In this embodiment, the substrate14(FIG. 10) is optically translucent to a desired wavelength of light to be received by the photodetector array62. Due to the hexagonal shape, the photodetector array64is efficient with regard to footprint and detector area. As such, applications of this disclosure extend into high data-rate serial and/or parallel communications as well as compact voltaic solar cells wherein the disclosed ring-shaped regions have a multi-quantum structure with high spectral absorption/detection of light, which is typical of triple or multi-quantum well structures.

FIG. 13is a horizontal cross-section diagram of the HPD transistor configuration60symbolically depicted inFIG. 11. An isolated section66of the HPD transistor configuration60comprises the third transistor Q3. In this exemplary embodiment, the isolation section66is isolated from other sections of the HPD transistor configuration60by an etched boundary68. As such, the third transistor Q3is made up of an outer collector region20i, an isolated outer base region26i, an isolated outer emitter32i, and an isolated sub-collector36i. A isolation connector structure70couples the inner emitter region30with the isolated outer base region26i.