An object of the present disclosure is to suppress decrease in withstand voltage and increase in ON voltage and to increase body diode current. An SiC-MOSFET includes: a source region formed on a surface layer of a base region; a gate electrode facing a channel region which is a region of the base region sandwiched between a drift layer and the source region via a gate insulating film; a source electrode having electrically contact with the source region; and a plurality of first embedded regions of a second conductivity type formed adjacent to a lower surface of the base region. The plurality of first embedded regions are formed immediately below at least both end portions of the base region, and three or more first embedded regions are formed to be separated from each other.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to an SiC-MOSFET.

Description of the Background Art

Widely used in a power electronic apparatus is an insulated gate type semiconductor device such as an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET) as a switching element controlling a power supply to a load such as a motor.

There is a high degree of expectation in applying the MOSFET or the IGBT using a wide bandgap semiconductor such as silicon carbide (SiC) to a technical field dealing with high voltage of substantially 1 kV or more as a future switching element. Examples of the wide bandgap semiconductor include a gallium nitride series material and diamond in addition to silicon carbide.

In a MOSFET having a vertical structure, a reverse pn diode referred to as a body diode is formed by a pn junction made up of an n-type drift layer and a p-type base region. The body diode is used, thus an external diode parallelly connected to the MOSFET can be omitted, and the number of elements in a circuit can be reduced. However, known is that when current (referred to as “body diode current” hereinafter) flows in the body diode of the MOSFET applying SiC to a semiconductor material (referred to as “SiC-MOSFET” hereinafter), a stacking fault in a crystal extends by energy generated when an electron-hole pair is recombined. The stacking fault functions as a high resistance layer, thus when it extends, characteristics of the MOSFET and the body diode are deteriorated. Accordingly, the extension of the stacking fault needs to be suppressed to use the body diode of the SiC-MOSFET.

Most of the stacking fault extending due to the body diode current is derived from a substrate. 99% or more of the fault in the substrate is converted into a harmless fault at an interface between the substrate and a drift layer, and does not extend into the drift layer. However, when the body diode current increases and the hole reaches the interface between the drift layer and the substrate, a large number of stacking faults extends from the fault in the substrate as a starting point. The stacking fault functions as a high resistance layer, thus when it extends, characteristics of the MOSFET and the body diode are significantly deteriorated. The hole implanted into the drift layer serves as a minority carrier in the drift layer, thus a depth in which the hole reaches is subject to a lifetime of the minority carrier.

In the meanwhile, known is a technique of providing a Schottky barrier diode (SBD) in a MOSFET and flowing diode current into the SBD. According to this configuration, rising voltage of the SBD provided in parallel to a body diode is smaller than rising voltage in a pn junction of an SiC constituting the body diode, thus the diode current in an OFF state of the MOSFET flows not into the body diode but into the SBD. The current flowing in the SBD is electron current in which no hole intervenes, thus the extension of the stacking fault caused by the hole does not occur, and characteristics of the MOSFET, for example, are not also deteriorated. However, when the diode current increases to some degree, the body diode operates and hole current flows. The SBD is provided in a unit cell, thus a region of the MOSFET decreases. By these reasons, there is a problem that ON voltage increases.

Japanese Patent Application Laid-Open No. 2005-285984 proposes a configuration that a plurality of p-type regions are additionally provided below a p-type base region in the unit cell of the MOSFET to be adjacent thereto. According to the configuration of Japanese Patent Application Laid-Open No. 2005-285984, a lifetime of the implanted hole decreases in a region of a drift layer sandwiched between the p-type regions, thus the number of holes reaching an interface between the drift layer and a substrate can be reduced.

SUMMARY

The configuration of Japanese Patent Application Laid-Open No. 2005-285984 does not include an additional p-type region below an end portion of the p-type base region (paragraph 0045), thus there is a problem that withstand voltage decreases. The reason is that there is concern that when a width of the n-type region adjacent to the end portion of the p-type base region is large, a depletion layer does not sufficiently extend but an electrical field is concentrated, and withstand voltage decreases.

An object of a technique of the present disclosure is to suppress decrease in withstand voltage and increase in ON voltage and to increase body diode current.

An SiC-MOSFET according to the present disclosure includes an SiC substrate of a first conductivity type, a drift layer of a first conductivity type, a base region of a second conductivity type, a source region of a first conductivity type, a gate electrode, a source electrode, and a plurality of first embedded regions of a second conductivity type. The drift layer is formed on an SiC substrate. The base region is formed on a surface layer of the drift layer. The source region is formed on a surface layer of the base region. The gate electrode faces a channel region which is a region of the base region sandwiched between the drift layer and the source region via a gate insulating film. The source electrode has electrically contact with the source region. The plurality of first embedded regions are formed adjacent to a lower surface of the base region. The plurality of first embedded regions are formed immediately below at least both end portions of the base region, and three or more first embedded regions are formed to be separated from each other.

According to the SiC-MOSFET according to the present disclosure, a lifetime of the hole decreases in the region of the drift layer between the first embedded regions, thus the number of holes reaching an interface between the drift layer and the substrate can be reduced, and an extension of a stacking fault can be suppressed. Accordingly, body diode current can be increased. The first embedded region is formed immediately below the both end portions of the base region, thus decrease in the withstand voltage is suppressed. A conduction route of the MOSFET does not change even when the first embedded region is provided, thus increase in ON voltage does not occur.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Configurations of various SiC-MOSFETs are described hereinafter, however, an n type or a p type in a constituent element of each SiC-MOSFET may be an opposite conductivity type.

A-1. Comparison Example

FIG.1is a cross-sectional view of an SiC-MOSFET151according to a first comparison example of an embodiment 1. The SiC-MOSFET151is a MOSFET having a vertical structure. The SiC-MOSFET151includes an n-type SiC substrate1, an n-type drift layer2, a p-type base region3, an n-type source region4, a gate insulating film5, a gate electrode6, an interlayer insulating film7, a source electrode8, and a drain electrode9. The n-type drift layer2is formed on an upper surface of the SiC substrate1. The p-type base region3is formed on a surface layer of the drift layer2. The n-type source region4is formed on a surface layer of the base region3. A portion of the surface layer of the base region3sandwiched between the drift layer2and the source region4functions as a channel region. The gate insulating film5is formed on the channel region, and the gate electrode6is formed thereon. That is to say, the gate electrode6is formed in a position facing the channel region via the gate insulating film5. Interlayer insulating film7covers a side surface and an upper surface of the gate electrode6. The source electrode8is formed to cover the source region4, the base region3, and the interlayer insulating film7. The source electrode8has contact with an upper surface of the base region3where the source region4other than the channel region is not formed. The drain electrode9is formed on a lower surface of the SiC substrate1.

In the SiC-MOSFET151, a reverse pn diode referred to as a body diode is formed by a pn junction made up of the n-type drift layer2and the p-type base region3. The body diode is used, thus an external diode parallelly connected to the SiC-MOSFET151can be omitted, and the number of elements in a circuit can be reduced. However, when the body diode current flows in the SiC-MOSFET, a stacking fault in a crystal extends by energy generated when an electron-hole pair is recombined, and deteriorates characteristics of the MOSFET and the body diode. Accordingly, the extension of the stacking fault needs to be suppressed to use the body diode of the SiC-MOSFET.

FIG.2is a cross-sectional view of an SiC-MOSFET152according to a second comparison example 2 of the embodiment 1. The SiC-MOSFET152is different from the SiC-MOSFET151according to the first comparison example in that the plurality of p-type first embedded regions10are provided adjacent to a lower surface of the base region3. The plurality of first embedded regions10are provided for one base region3. The region of the drift layer2sandwiched between the two first embedded regions10adjacent to each other is referred to as an n-type region11. According to the SiC-MOSFET152, a lifetime of a hole implanted in the n-type region11decreases, thus the number of holes reaching an interface between the drift layer2and the SiC substrate1is reduced. However, the first embedded region10is not provided below an end portion of the base region3, thus there is a problem that withstand voltage decreases. The reason is that there is concern that when a width of the n-type region adjacent to the end portion of the base region3is large, a depletion layer does not sufficiently extend but an electrical field is concentrated, and the withstand voltage decreases.

FIG.3is a cross-sectional view of an SiC-MOSFET101according to the embodiment 1. The SiC-MOSFET101is different from an SiC-MOSFET102according to the second comparison example in that the first embedded region10is also provided immediately below the end portion of the base region3.

In the SiC-MOSFET151according to the first comparison example, the body diode current flows from the whole base region3including a portion located below the source electrode4to the drift layer2. A lifetime of the hole in the drift layer2is constant.

In the meanwhile, in the SiC-MOSFET101, a lifetime of the hole decreases around the first embedded region10. Thus, even when the body diode current which is the same as that in the SiC-MOSFET151according to the first comparison example flows in the SiC-MOSFET101, some of the holes flows from the base region3to the n-type region11are recombined in the n-type region11. As a result, the holes reaching the interface between the drift layer2and the SiC substrate1decrease in number. That is to say, the SiC-MOSFET101can flow larger body diode current without an occurrence of a fault extension than the SiC-MOSFET151according to the first comparison example.

The effect of reducing the lifetime of the hole occurs around the first embedded region10. The reason is that the holes are recombined in the n-type region11sandwiched between the first embedded region10, thus hardly reach the drift layer2on a lower side. Accordingly, an interval of the first embedded regions10adjacent to each other, that is to say, a width of the n-type region11is preferably small. However, an area ratio of the n-type region11to the base region3decreases, the holes flow from the first embedded region10to the drift layer2is dominant over the holes flowing from the n-type region11to the drift layer2, thus the n-type region11needs to have a certain degree of width. Accordingly, the width of the n-type region11is preferably equal to or larger than 0.4 μm and equal to or smaller than 4.0 μm. In the meanwhile, when the width of the first embedded region10increases, the holes flowing from the first embedded region10to the drift layer2increase in number. Thus, the width of the first embedded region10is preferably equal to or larger than half and equal to or smaller than twice the width of the n-type region11.

Although depending on the width of the base region3, two or more n-type regions11are preferably provided for one base region3. In other words, three or more first embedded regions10are preferably provided for one base region3. At this time, the width of the first embedded region10and the width of the n-type region11may be different from each other. Thus, as illustrated inFIG.3, the width of the first embedded region10located immediately below the both end portions of the base region3may be larger than the width of the first embedded region10which is not located immediately below the both end portions of the base region3.

A portion of the base region3or the source region4having contact with the source electrode8is referred to as a source contact region. A volume of flow of the holes is large immediately below the source contact region, particularly in a center portion thereof. Accordingly, in terms of the first embedded region10immediately below the source contact region, it is also applicable that the width of the first embedded region10located in a center portion is set to be narrowest to increase an effect of eliminating the holes, and the width of the first embedded region10is increased toward an outer side from the center portion. The first embedded regions10may be disposed at regular intervals for one base region3. The first embedded regions10are disposed at regular intervals, thus achieved is an effect that the body diode current evenly flows from the first embedded region10, and current characteristics are stabilized.

As a depth of the n-type region11gets larger, a distance at which the holes travel in a region where the holes have a short lifetime increases. Thus, a ratio of the depth of the first embedded region10to the depth of the base region3is at least equal to or larger than 1.2, and is preferably equal to or larger than 1.5. The depth of the first embedded region10located immediately below the end portion of the base region3is the same as the depth of the other first embedded region10, thus the withstand voltage increases.

As illustrated inFIG.3, in the case where the n-type region11is also formed immediately below the source region4, there is concern that when the width of the n-type region11is large, the depletion layer does not sufficiently extend but the electrical field is concentrated, and the withstand voltage decreases. Thus, the width of the n-type region11is preferably small. In this case, the width of the n-type region11may be smaller than “equal to or larger than 0.4 μm and equal to or smaller than 4.0 μm” described above. In the manner similar to the above description, a ratio of the depth of the first embedded region10to the depth of the base region3in this case is also equal to or larger than 1.2, and is preferably equal to or larger than 1.5.

As an impurity concentration of the first embedded region10gets larger, the effect of reducing the lifetime of the hole increases. However, if the impurity concentration of the first embedded region10increases, an electrical field applied to a lower portion of the first embedded region10increases when the SiC-MOSFET101enters an OFF state and high voltage is maintained, thus attention is needed in increasing the impurity concentration.

The plurality of first embedded regions10need to be provided immediately below the base region3because of a structure of sandwiching the n-type region11therebetween. Examples of a planar shape of the unit cell include a lattice form of a rectangular shape, a hexagonal shape, or a circular shape or a stripe shape. When the planar shape of the unit cell is the lattice form, the planar shape of the first embedded region10may be a concentric shape or a stripe shape. When the planar shape of the unit cell is the stripe form, the first embedded region10may be disposed to be parallel to or perpendicular to a longitudinal direction of the stripe of the unit cell. The first embedded region10may be disposed in a pattern in which a concentric pattern is periodically repeated along the longitudinal direction of the stripe of the unit cell.

A-3. Modification Example

FIG.4is a cross-sectional view of an SiC-MOSFET102according to a modification example of the embodiment 1. In the SiC-MOSFET102, a concave portion12is formed in an upper surface of the source region4and a source contact portion of the base region3, and the source electrode8is put into the concave portion12. Then, the first embedded region10is formed below the end portion of the base region3and below the concave portion12. According to the SiC-MOSFET102having the concave portion12, the first embedded region10can be formed using a mask for forming the base region3, thus an effect of reducing the mask is achieved.

There is a possibility that the first embedded region10is separated from the base region3depending on the relationship between the depth of the concave portion12and the depth of the first embedded region10. Even in such a case, the first embedded region10is preferably grounded. When the source electrode8is embedded into the concave portion12as illustrated inFIG.4, the first embedded region10can be grounded. It is also applicable that a part of or a whole sidewall of the concave portion12is the p type and the base region3and the first embedded region10are connected to each other.

The SiC-MOSFET according to the embodiment 1 includes: the SiC substrate1of the first conductivity type; the drift layer2of the first conductivity type formed on the SiC substrate1; the base region3of the second conductivity type formed on a surface layer of the drift layer2; the source region4of the first conductivity type formed on the surface layer of the base region3; the gate electrode6facing the channel region which is the region of the base region3sandwiched between the drift layer2and the source region4via the gate insulating film5; the source electrode8having electrically contact with the source region4; and the plurality of first embedded regions10of the second conductivity type formed adjacent to the lower surface of the base region3. The plurality of first embedded regions10are formed immediately below at least both end portions of the base region3, and three or more first embedded regions10are formed to be separated from each other. The lifetime of the hole decreases in the region of the drift layer2between the first embedded regions10, thus the number of holes reaching the interface between the drift layer2and the SiC substrate1can be reduced, and the extension of the stacking fault can be suppressed. Accordingly, body diode current can be increased. The first embedded region10is formed immediately below the both end portions of the base region3, thus decrease in the withstand voltage is suppressed. The conduction route of the MOSFET does not change even when the first embedded region10is provided, thus increase in ON voltage does not occur.

B-1. Comparison Example

FIG.5is a cross-sectional view of an SiC-MOSFET251according to a comparison example of an embodiment 2. The SiC-MOSFET251includes an active region14having a unit cell operating as a MOSFET and an outer peripheral region13on an outer side of the active region14. A configuration of the active region14of the SiC-MOSFET251is similar to that of the SiC-MOSFET151according to the first comparison example of the embodiment 1. The SiC substrate1, the drift layer2, the source electrode8, and the drain electrode9are common in the active region14and the outer peripheral region13.

A plurality of guard rings15are provided in the surface layer of the drift layer2in the outer peripheral region13. The guard rings15are p-type regions, and are concentrically disposed to surround the active region14. A width of each guard ring15gradually decreases from an inner side toward an outer side of the outer peripheral region13. The gate electrode6and a gate pad or a field oxide film, for example, are provided in the outer peripheral region13in some cases depending on the configuration of the SiC-MOSFET.

In the SiC-MOSFET251, current referred to as displacement current occurs in accordance with an expansion and contraction of a depletion layer generated in the drift layer2and the guard ring15at a time of switching operation. When potential in the guard ring15is increased by this current, a potential difference with the source electrode8or the gate electrode6increases, and the field insulating film, the interlayer insulating film7, or the gate insulating film5provided therebetween is broken. Thus, a guard ring15awhich is the guard ring15on the innermost peripheral side is provided with a portion having electrically contact with the source electrode8, that is to say, a source contact16. The guard ring15ahaving the source contact16also operates as a body diode, thus has a problem of the extension of the stacking fault due to the body diode current.

FIG.6is a cross-sectional view of an SiC-MOSFET201according to the embodiment 2. The active region14of the SiC-MOSFET201has a configuration similar to the SiC-MOSFET101according to the embodiment 1. The outer peripheral region13of the SiC-MOSFET201is different from the outer peripheral region13of the SiC-MOSFET251according to the comparison example in that a plurality of p-type second embedded regions20are provided below the guard ring15aon the innermost peripheral side to be adjacent thereto. A region of the drift layer2sandwiched between two second embedded regions20adjacent to each other is referred to as an n-type region21.

InFIG.6, the second embedded region20is formed not only immediately below the source contact16but also below both end portions of the guard ring15a. However, the second embedded region20may be provided only immediately below the source contact16. As with the description of the first embedded region10and the n-type region11in the embodiment 1, the second embedded region20is provided, thus the lifetime of the hole in the n-type region21can be reduced.

A width, a depth, and an impurity concentration of the second embedded region20are similar to those of the first embedded region10. The two or more n-type regions21are preferably provided for the guard ring15a. In other words, three or more second embedded regions20are preferably provided for the guard ring15a.

The second embedded region20of the outer peripheral region13may have the same depth as the first embedded region10of the active region14. The depths of them are the same as each other, thus withstand voltage is increased. The depth of the second embedded region20of the outer peripheral region13may be gradually larger from the outer side toward a side of the active region14.

B-3. Modification Example

FIG.7is a cross-sectional view of an SiC-MOSFET202according to a first modification example of the embodiment 2. The SiC-MOSFET202is different from the SiC-MOSFET201according to the embodiment 2 in that the concave portion12is formed in the upper surface of the source region4in the active region14and the source contact portion of the base region3and the concave portion22is formed in the upper surface of the guard ring15aon the innermost peripheral side in the outer peripheral region13. The active region14of the SiC-MOSFET202has the same configuration as the SiC-MOSFET102according to the modification example of the embodiment 1. The gate insulating film5, the interlayer insulating film7, or the source electrode8is put into the concave portion22.

FIG.8is a cross-sectional view of an SiC-MOSFET203according to a second modification example of the embodiment 2. In the SiC-MOSFET203, the width of the concave portion22is larger than that of the concave portion22in the SiC-MOSFET202, and an upper surface of an outer end portion of the guard ring15aand an upper surface of the guard ring15on an outer side of the guard ring15acoincide with a height of a bottom surface of the concave portion22.

A planar-type unit cell is used in the SiC-MOSFETs101,102,201,202, and203described above, however, a trench-type unit cell may also be used.

The SiC-MOSFET201according to the embodiment 2 includes the active region14in which the plurality of unit cells made up of the gate electrode6, the base region3, and the source region4are disposed and the outer peripheral region13surrounding the active region14. The outer peripheral region13includes the plurality of guard rings15of the second conductivity type formed in the surface layer of the drift layer2and the plurality of second embedded regions20of the second conductivity type formed adjacent to the lower surface of the guard ring15aon the innermost peripheral side of the plurality of guard rings15. The plurality of second embedded regions20are formed adjacent to at least the lower surface of both end portions of the guard ring15aon the innermost peripheral side, and three or more second embedded regions20are formed to be separated from each other. Thus, according to the SiC-MOSFET201, the body diode current which can flow without the occurrence of the fault extension can be increased also in the outer peripheral region13.

Each embodiment can be arbitrarily combined, or each embodiment can be appropriately varied or omitted.