Electrostatic discharge circuit for switching mode power supply

In one example, a circuit comprises: a controller, an electrostatic discharge (ESD) circuit, and a driver circuit. The controller has a driver control output. The ESD circuit has a driver control input and an ESD output, the driver control input coupled to the driver control output. The driver circuit has a driver input and a driver output, the driver input coupled to the ESD output.

BACKGROUND

A switched mode power supply (SMPS) uses semiconductor switching techniques to transfer power from a power source to a load. The SMPS may include an energy storage element (such as an inductor, a capacitor, a transformer, etc.) and switches. Through the repetitive enabling and disabling of the switches, the energy storage element can continuously switch between a charging state and a discharging state in each switching cycle. The SMPS may also include driver circuits to enable/disable the switches, and a controller that control the driver circuits. The controller of the SMPS can determine the on-time and off-time of the switches, which can reflect the time durations of the charging and discharging states in a switching cycle, so the SMPS can provide a desired power to the load. The switches, the driver circuits, and the controller can be in an integrated circuit. The integrated circuit can be electrically connected between the power source and the load to perform the power transfer.

The integrated circuit can be susceptible to an electrostatic discharge (ESD) event. The ESD event can occur when the integrated circuit is handled or otherwise comes into contact with another object that has electrostatic charge. The ESD event can introduce a large voltage across the semiconductor devices of the integrated circuit, and cause a large current to flow through those devices, both of which can introduce failures in the semiconductor devices.

SUMMARY

A circuit comprises a controller, an electrostatic discharge (ESD) circuit, and a driver circuit. The controller has a driver control output. The ESD circuit has a driver control input and an ESD output, the driver control input coupled to the driver control output. The driver circuit has a driver input and a driver output, the driver input coupled to the ESD output.

An integrated circuit comprises a controller, a first ESD circuit, a second ESD circuit, a voltage regulator, a first driver circuit, a second driver circuit, a first transistor, and a second transistor. The controller has a first driver control output and a second driver control output. The first ESD circuit has a first driver control input and a first ESD output, the first driver control input coupled to the first driver control output. The second ESD circuit has a second driver control input and a second ESD output, the second driver control input coupled to the second driver control output. The first driver circuit is coupled between an internal supply voltage terminal and a switching terminal and has a first driver input and a first driver output. The first driver input is coupled to the first ESD output. The second driver circuit is coupled between the regulator output and a rectifier terminal and has a second driver input and a second driver output. The second driver input is coupled to the second ESD output. The first transistor is coupled between an input voltage terminal and the switching terminal and has a first control terminal coupled to the first driver output. The second transistor is coupled between the switching terminal and the rectifier terminal and has a second control terminal coupled to the second driver output.

The same reference numbers or other reference designators are used in the drawings to designate the same or similar (functionally and/or structurally) features.

DETAILED DESCRIPTION

FIG.1illustrates schematics of an example control circuit100that can be part of a switched mode power supply (SMPS). Referring toFIG.1, control circuit100can be part of an integrated circuit including an input voltage terminal102(labelled VIN), a switching terminal104(labelled SW), a rectifier terminal106(labelled REC), and a feedback terminal108(labelled FB). Control circuit100can also include an internal voltage supply terminal110(labelled SUP), and an enable terminal112(labelled EN). Each of terminals102through112can be in the form of a pin, a lead, a solder ball, a flat contact, or any type of structure to provide an electrical connection between an external device and internal components of control circuit100. In some examples, control circuit100can be mounted on a printed circuit board (PCB) via terminals102through112.

FIG.2illustrates schematics of example internal components of control circuit100. Referring toFIG.2, control circuit100can include a switch202coupled between input voltage terminal102(VIN) and switching terminal104(SW), and a switch204coupled between switching terminal104and rectifier terminal106(REC). In a SMPS, the VIN terminal can be coupled to a power source (e.g., a battery), and the SW terminal can be coupled to an energy storage element (e.g., an inductor). Switch202can operate as a main switch to control the flow of current from the power source to charge or discharge the energy storage element. Also, switch204can operate as a rectifier to control the flow of current from the energy storage element to a load. Each of switches202and204can include a respective transistor, such as field effect transistor (FET). In some examples (not shown in the figures), switches202and204can be external to control circuit100.

Also, control circuit100can include driver circuits212and214to drive respective switches202and204. Driver circuit212can include a driver input222, a driver output224, voltage terminals226aand226b,a pull-up circuit228and a pull-down circuit230. Voltage terminal226acan be coupled to the SUP terminal (internal voltage supply terminal110), voltage terminal226bcan be coupled to the SW terminal (switching terminal104), and driver output224can be coupled to a control terminal (e.g., gate) of switch202. Pull-up circuit228can be coupled between voltage terminal226aand driver output224, and pull-down circuit230can be coupled between driver output224and voltage terminal226b.Driver circuit212can receive a control signal232from controller220and, depending on the state of control signal232, can enable one of pull-up circuit228or pull-down circuit230. By enabling pull-up circuit228and disabling pull-down circuit230, driver circuit212provide a control signal234having a first state (e.g., having the same voltage as VIN terminal) to enable switch202. Also, by enabling pull-down circuit230and disabling pull-up circuit228, driver circuit212can provide control signal234having a second state (e.g., having the same voltage as SW terminal) to disable switch202.

Also, driver circuit214can include a driver input242, a driver output244, voltage terminals246aand246b,a pull-up circuit248and a pull-down circuit250. Voltage terminal246acan be coupled to another internal voltage supply251, which can be provided by an internal voltage regulator of control circuit100(not shown in the figures), or can be derived from a voltage at the SUP terminal. Voltage terminal246bcan be coupled to the REC terminal (rectifier terminal106). Also, driver output244can be coupled to a control terminal (e.g., gate) of switch204. Pull-up circuit248can be coupled between voltage terminal246aand driver output244, and pull-down circuit250can be coupled between driver output244and voltage terminal246b.Driver circuit214can receive a control signal252from controller220and, depending on the state of control signal252, can enable one of pull-up circuit248or pull-down circuit250. By enabling pull-up circuit248and disabling pull-down circuit250, driver circuit214provide a control signal254having a first state (e.g., having the same voltage as SW) to enable switch204. Also, by enabling pull-down circuit250and disabling pull-up circuit248, driver circuit214can provide control signal254having a second state (e.g., having the same voltage as REC terminal) to disable switch204.

In addition, control circuit100can include a controller260. Controller260can receive an enable signal262from enable terminal112and a feedback signal264from feedback terminal108, and generate control signals232and252based on the states of enable signal262and feedback signal264. For example, enable signal262can indicate whether the SMPS is to be enabled. Also, feedback signal264can represent an output voltage of SMPS to the load. If the SMPS is to be enabled, controller260can generate control signals222and224to control the turn-on and turn-off durations of switches202and204based on feedback signal264to regulate the output voltage. But if the SMPS is to be disabled, controller260can generate control signals232and252to disable driver circuits212and214and/or disable switches202and204.

FIG.3illustrates schematics of an example SMPS300including control circuit100. Referring toFIG.3, input voltage terminal102of control circuit100can be coupled to a power source302, which supplies an input voltage Vi. SMPS300can also include an inductor304, which operates as an energy storage element, coupled between switching terminal104of control circuit100and a load306and a holding capacitor308. Also, rectifier terminal106can be coupled to ground. SMPS300can transfer power from power source302to load306and holding capacitor308by providing an output voltage Vobased on input voltage Vi.

InFIG.3, SMPS300is configured as a buck converter that generates the output voltage Voas a step-down version of input voltage Vi. SMPS300can provide control signals232and252as multi-cycle signals, and can set the ratio between output voltage Voand input voltage Viby setting the duty cycles of control signals232/234and252/254. SMPS300can include a voltage divider310having an input coupled to inductor304and an output coupled to feedback terminal108of control circuit100. Voltage divider310can generate feedback signal264that represents output voltage Vo, and provide feedback signal264to controller260. Controller260can modulate the duty cycles of control signals232and252based on feedback signal264to regulate output voltage Voat a target voltage.

Also, SMPS300can also include a capacitor312coupled between internal voltage supply terminal110and switching terminal104. Capacitor312can operate as a charge pump to provide an internal supply voltage VSUPfor driver circuit212from a switching voltage VSWat switching terminal104. As switching voltage VSWswitches between states (e.g., between the input voltage Viand ground voltage), charge can be added to capacitor312to increase VSUPto a level above the input voltage Vi.

FIG.4includes waveform graphs that illustrates example operations of SMPS300. InFIG.4, graph402represents the time-variation of control signal234provided by driver circuit212to switch202, and graph404represents the time-variation of control signal254provided by driver circuit214to switch204. Also, graph406represents the time-variation of an inductor current that flows from switching terminal104to load306across inductor304, and graph408represents the time-variation of a voltage across inductor304. Further, graph410represents the time-variation of a voltage at input voltage terminal102, which is substantially constant at Vi, and graph412represents the time variation of switching voltage VSWat switching terminal104.

FIG.4illustrates a switching cycle of switches202and204has a cycle period of T, and the switching cycle spans from time T0through time T1and ends at time T2. The period between T0and T1is an off-time for switch202(and an on-time for switch204) and has a duration of toff, and the period between T1and T2is an on-time for switch202(and an off-time for switch204) and has a duration of ton. A ratio between tonand T can represent the duty cycle and can set the ratio between output voltage Voand input voltage Vi.

Between T0and T1, pull-up circuit248of driver circuit214can be enabled and pull-down circuit250of driver circuit214can be disabled. Accordingly, driver circuit214can set control signal254to a VCCvoltage provided by internal voltage supply251and enable switch204, and switching voltage VSWdrops to the ground voltage (e.g., zero volt) between T0and T1. Also, pull-up circuit228of driver circuit212can be disabled, and pull-down circuit230of driver circuit212can be enabled. Accordingly, driver circuit212can set control signal234to the VSWvoltage (zero volt) and disable switch202. Between T0and T1, inductor304can discharge, the inductor current drops from a maximum value (Imax) to a minimum value (Imin), and the voltage across inductor304can be equal to negative Vo. Also, holding capacitor308can discharge to provide current to load306and to maintain the voltage across load306around positive Vo.

Also, between T1and T2, pull-up circuit248of driver circuit214can be disabled and pull-down circuit250of driver circuit214can be enabled. Accordingly, driver circuit214can set control signal254to the ground voltage and disable switch204. Also, pull-up circuit228of driver circuit212can be disabled, and pull-down circuit230of driver circuit212can be enabled. Accordingly, driver circuit212can set control signal234to the VSUPvoltage and enable switch202. The enabled switch204can bring the VSWvoltage to be equal to the input voltage Vi. Between T1and T2, inductor304can charge, the inductor current increases from a minimum value (Imin) to a maximum value (Imax), and the voltage across inductor304can be equal to negative Vi-Vo. Holding capacitor308can also maintain the voltage across load306around positive Vo.

FIG.5illustrates schematics of another example SMPS500including control circuit100. Referring toFIG.5, input voltage terminal102of control circuit100can be coupled to power source302, which supplies the input voltage Vi. SMPS500can also include an inductor508, which operates as an energy storage element, coupled to switching terminal104. Also, load306, holding capacitor308, and voltage divider310can be coupled to rectifier terminal106. SMPS500can also include capacitor312coupled between internal supply voltage terminal110and switching terminal104. InFIG.5, SMPS500can be a buck-boost converter that generates the output voltage Voas a step-down or step-up version of the input voltage Vi. Based on feedback signal264, controller206can determine the ratio between the output voltage Voand the input voltage Viby setting the duty cycles of control signals232/234and252/254.

Control circuit100can be susceptible to an electrostatic discharge (ESD) event. During an ESD event, a large amount of electrostatic charge can be transferred from another object to control circuit100within a short period of time. The ESD event can occur when the integrated circuit including control circuit100is handled or otherwise comes into contact with the other object that has electrostatic charge. For example, when input voltage terminal102is electrically connected to a power source, such as when the integrated circuit is mounted on a printed circuit board or wired to the power source, a large amount of electrostatic charge can be transferred via input voltage terminal102into control circuit100within a short period of time.

The ESD event can introduce a large voltage across the semiconductor devices of the integrated circuit including those of control circuit100, and cause a large current to flow through those devices, both of which can cause failure in the semiconductor devices.FIG.6andFIG.7illustrate example impacts of an ESD event at input voltage terminal102on control circuit100. Referring toFIG.6, input voltage terminal102may receive an ESD signal602, which may include a pulse of electrostatic charge. ESD signal602can propagate through a path604to reach internal voltage supply terminal110, and propagate through path606to reach internal voltage supply251. Specifically, switches202and204can include respective parasitic capacitances612and614along paths604and606. In a case where switches202and204include a respective NFET, each of parasitic capacitances612and614can be a gate-drain capacitance (CGD) of the NFET. From input voltage terminal102, ESD signal602can propagate through parasitic capacitance612and deposit charge at the gate/control terminal of switch202, which increases the voltage of driver output224of driver circuit212. Pull-up circuit228of driver circuit212can transmit the increased voltage as an ESD voltage signal622through voltage terminal226ato internal voltage supply terminal110.

Also, the increased voltage of driver output224can enable switch202, and the enabled switch202can transmit ESD signal602to switching terminal104. From switching terminal104, ESD signal602can propagate through parasitic capacitance614and deposit charge at the gate/control terminal of switch204, which increases the voltage of driver output244of driver circuit214. Pull-up circuit248of driver circuit214can transmit the increased voltage as an ESD voltage signal624through voltage terminal246ato internal voltage supply251.

The propagation of the ESD signals can increase the voltages at internal voltage supply terminal110and internal voltage supply251, which can create voltage stress on semiconductor devices that are coupled to and receive power from internal voltage supply terminal110and internal voltage supply251. For example, in addition to pull-up circuit228, control circuit100can include other circuits that are coupled to internal voltage supply terminal110, such as level shifter circuit and buffer circuit. Also, controller260can receive power from internal voltage supply251. Control circuit100may also include a voltage regulator to provide internal voltage supply251. All these circuits can be susceptible to voltage stress if the voltages at internal voltage supply terminal110and internal voltage supply251are increased by the ESD signal. The voltage stress can cause the semiconductor devices to fail, or at least reduce the life time of the semiconductor devices and degrade the reliability of control circuit100.

FIG.7illustrates another example impact of an ESD event at input voltage terminal102on control circuit100. Referring toFIG.7, an SMPS may include capacitor312coupled between switching terminal104and internal voltage supply terminal110. Also, as described above, ESD signal602can propagate through parasitic capacitance612and deposit charge at the gate/control terminal of switch202, which increases the voltage of driver output224of driver circuit212and enable switch202. The enabled switch202and capacitor312can form a current path702. Through current path702, ESD signal602can propagate, and a large ESD current can flow from input voltage terminal102through switch202, capacitor312, voltage terminal226a,and reach driver circuit212. The large ESD current can also damage the semiconductor devices of driver circuit212.

FIG.8andFIG.9illustrate examples of an ESD circuit800that can mitigate the impact of an ESD event on control circuit100. Referring toFIG.8, ESD circuit800can be external to control circuit100and include an input terminal802, a charge draining terminal804, and a control input806. Input terminal802of ESD circuit800can be coupled to input voltage terminal102, and charge draining terminal804can be coupled to ground. Control input806can receive a control signal, which can indicate whether ESD circuit800is enabled or disabled. When ESD circuit800is enabled, ESD circuit800can provide a current path808to remove some or all of the electrostatic charge of ESD signal602from input voltage terminal102via input terminal802, and drain the charge via charge drain terminal804to ground. Accordingly, none (or a reduced amount) of the electrostatic charge of ESD signal602reaches at internal voltage supply terminal110and internal voltage supply251, which can reduce the voltage stress and ESD current in control circuit100caused by the ESD event.

FIG.9illustrates example internal components of ESD circuit800. Referring toFIG.9, ESD circuit800can include transistors902,904,906, and908, and resistors912and914. Transistors902through908can be FET, such as NFET. First current terminals (e.g., drain) of transistors902and904can be coupled to input terminal802. A second current terminal (e.g., source) of transistor902can be coupled to the control terminal (e.g., gate) of transistor904, and a second current terminal (e.g., source) of transistor904can be coupled to charge draining terminal804. Also, resistor912can be coupled between the control terminal (e.g., gate) of transistor902and output terminal804. Resistor914can be coupled between the second current terminal of transistor902and charge draining terminal804.

Resistor912and parasitic capacitance922of transistor902(e.g., CGD) can form an RC filter. When ESD signal602appears at input terminal802, the electrostatic charge of ESD signal602can flow through parasitic capacitance922and resistor912and increase the voltage at the gate/control terminal of transistor902, and transistor902can be enabled. As transistor902is enabled, current can flow through transistor902and resistor914, and the source voltage of transistor902and the gate voltage of transistor904also increase. The increased gate voltage can enable transistor904, which can provide current path808to drain the ESD charge to ground.

Also, the control terminals of transistors906and908can be coupled to control input806. Transistor906can be coupled between the gate of transistor902and charge draining terminal104, and transistor908can be coupled between the gate of transistor904and charge draining terminal804. Charge draining terminal804can be coupled to ground. If control input806is in a first state (e.g., an asserted state), both transistors906and908can be enabled to pull the respective gates of transistors902and904to ground (charge draining terminal804) and disable transistors902and904. If control input806is in a second state (e.g., a de-asserted state), both transistors906and908can be disabled, and transistors902and904can operate responsive to an ESD event as described above.

Although ESD circuit800can mitigate the impact of an ESD event on control circuit100, various issues can impact its performance in handling the ESD event. First, transistor904can have a large width (and a large size) to reduce the resistance, and to speed up the draining of the ESD charge quickly. But the large size of transistor904can substantially increase the overall die size of the integrated circuit that includes ESD circuit800and control circuit100, while reducing the size of transistor904can slow down the removal of the ESD charge. Also, while ESD circuit800can divert/remove the ESD charge, it does not provide a mechanism to block the ESD charge from reaching internal voltage supply terminal110and internal voltage supply251. Accordingly, large voltage and current due to the ESD event can still reach internal voltage supply terminal110and internal voltage supply251, due to the delay incurred by ESD circuit800in removing the ESD charge.

FIG.10illustrates schematics of example ESD circuits that can address at least some of the issues described above. Referring toFIG.10, control circuit100can include an ESD circuit1002coupled between controller260and driver circuit212, and an ESD circuit1004coupled between controller260and driver circuit214. ESD circuit1002can include an ESD input1006, a control signal input1012, and ESD control signal outputs1014aand1014b.ESD control signal outputs1014aand1014bcan be coupled to respective driver inputs222aand222bof driver circuit212. Also, ESD circuit1004can include an ESD input1016, a driver power state input1018, a control signal input1022, and ESD control signal outputs1024aand1024b.ESD control outputs1024aand1024bcan be coupled to respective driver inputs242aand242bof driver circuit214. In some examples, ESD circuit1002can also include a driver power state input1008, and ESD circuit1004can also include a driver power state input1018.

ESD circuits1002and1004can receive respective signals1030and1040at respective ESD inputs1006and1016. Signals1030and1040can indicate whether an ESD event occurs at input voltage terminal102. In some examples, ESD input1006can be coupled to driver output224and ESD input1016can be coupled to driver output244, where the voltages at driver outputs224and244can indicate the ESD event. In some examples, ESD input1006can be coupled to input voltage terminal102and ESD input1016can be coupled to switching terminal104to detect the ESD event. In some examples, responsive to signal1030indicating an ESD event, ESD circuit1002can provide pull-up control signal1032to disable pull-up circuit228of driver circuit212. Also, responsive to receiving signal1040, ESD circuit1004can provide pull-up control signal1042to disable pull-up circuit248of driver circuit214.

Refer again toFIG.6, in an ESD event, the voltages at driver outputs224and244can increase due to the coupling of the electrostatic charge through parasitic capacitance612of switch202and through parasitic capacitance614of switch204. The disabling of pull-up circuit228by pull-up control signal1032can disconnect path604and block the increased voltage from reaching internal voltage supply terminal110. Also, the disabling of pull-up circuit248by pull-up control signal1042can disconnect path606and block the increased voltage from reaching internal voltage supply251. Accordingly, ESD circuits1002and1004can block the large voltage and current due to the ESD event from reaching the respective internal voltage supply terminal110and internal voltage supply251, which can improve the protection of the devices of control circuit100from the ESD event.

Also, ESD circuits1002and1004can receive respective signals1050and1060at respective driver power state inputs1008and1018. Both signals1050and1060can indicate whether control circuit100is in an enabled or a disabled state. In some examples, driver power state inputs1008and1018can be coupled to respective internal voltage supply terminal110and switching terminal104, where the voltages at the terminals can indicate whether control circuit100is connected to a power source and is enabled to transfer power. In some examples, driver power state inputs1008and1018can also be coupled to enable terminal112.

In some examples, ESD circuit1002can provide pull-down control signal1034to disable pull-down circuit230of driver circuit212responsive to signal1050indicating that control circuit100is in a disabled state. ESD circuit1004can also provide pull-down control signal1044to disable pull-down circuit250of driver circuit214responsive to signal1060indicating that control circuit100is in a disabled state. Such arrangements can maintain the increased voltages at driver outputs224and244to enable switches202and204, which allows the switches to drain away the electrostatic charge at input voltage terminal102via rectifier terminal106. In both the buck converter configuration ofFIG.3and the buck-boost configuration ofFIG.5, rectifier terminal106can be coupled to ground (directly connected inFIG.3, through voltage divider inFIG.5), and the electrostatic charge can be drained to the ground via rectifier terminal106. Accordingly, ESD circuits1002and1004can control switches202and204to conduct away the ESD current. Because ESD circuits1002and1004do not include additional devices to conduct away the ESD current, the overall footprint of the die including control circuit100and ESD circuits1002and1004can be small.

On the other hand, in a case where signals1030and1040do not indicate an ESD event, and where signals1050and1060indicate that control circuit100is enabled, ESD circuit1002can generate pull-up control signal1032and pull-down control signal1034based on control signal232from controller260, and ESD circuit1004can generate pull-up control signal1042and pull-down control signal1044based on control signal252from controller260.

FIG.11andFIG.12illustrate examples of internal components of ESD circuits1002,1004, pull-up circuits228and248, and pull-down circuits230and250. Referring toFIG.11andFIG.12, each of pull-up circuits228and248can include two PFETs coupled in series. Pull-up circuit228can include PFETs1102and1104coupled in series, in which a source terminal of PFET1102can be coupled to voltage terminal226aand internal voltage supply terminal110, a drain terminal of PFET1102can be coupled to a drain terminal of PFET1104, and a source terminal of PFET1104can be coupled to driver output224. PFETs1102and1104also include respective body diodes1112and1114coupled in series, with the anodes of body diodes1112and1114coupled together, the cathode of body diode1112coupled to voltage terminal226a(and internal voltage supply terminal110), and the cathode of body diode1114coupled to driver output224. Pull-down circuit230can include an NFET1106coupled between driver output224and switching terminal104.

Also, pull-up circuit248can include PFETs1122and1124coupled in series, in which a source terminal of PFET1122can be coupled to voltage terminal246aand internal voltage supply251, a drain terminal of PFET1122can be coupled to a drain terminal of PFET1124, and a source terminal of PFET1124can be coupled to driver output244. PFETs1122and1124also include respective body diodes1132and1134coupled in series, with the anodes of body diodes1132and1134coupled together, the cathode of body diode1132coupled to voltage terminal246a(and internal voltage supply251), and the cathode of body diode1134coupled to driver output244. Pull-down circuit250can include an NFET1126coupled between driver output244and rectifier terminal106.

In some examples, each of PFETs1102,1104,1122, and1124, and NFETs1106and1126, can include a transistor having a source terminal, a drain terminal, a gate terminal, a body terminal, and an isolation terminal.FIG.13illustrates schematics of cross-sectional view of a semiconductor device1300including a PFET1302and an NFET1304. PFET1302can provide PFETs1102,1104,1122, and1124ofFIGS.11and12, and NFET1304can provide NFETs1106and1126ofFIGS.11and12. Referring toFIG.13, semiconductor device1300can include a P-type substrate1310, and an N-type buried layer (NBL)1312on P-type substrate1310. PFET1302and NFET1304can be formed in NBL1312, which can provide noise insulation to PFET1302and NFET1304. Semiconductor device1300also include deep N-wells (DN)1314and1316to provide access to NBL1312from a front-side surface1320of semiconductor device1300. DN1314can be adjacent to or be part of PFET1302, and DN1316can be adjacent to or be part of NFET1304. PFET1302can include a P-well1322as body, a p+ region1324to provide access to P-well1322, n+ regions1326and1328that can be configured to be source and drain, and a gate1330. Semiconductor device1300can include an isolation terminal1332coupled to DN1314, a bulk terminal1334coupled to p+ region1324, a current terminal1336coupled to n+ region1326, a current terminal1338coupled to n+ region1328, and a control terminal1340coupled to gate1330.

Also, NFET1304can include an N-well1342as a body, an n+ region1344to provide access to N-well1342, p+ regions1346and1348that can be configured to be source and drain, and a gate1350. Semiconductor device1300can include an isolation terminal1352coupled to DN1316, a bulk terminal1354coupled to p+ region1344, a current terminal1356coupled to n+ region1346, a current terminal1358coupled to n+ region1348, and a control terminal1360coupled to gate1350.

Each of PFETs1102,1104,1122, and1124, and NFETs1106and1126, can have source, bulk, and isolation terminals coupled together to prevent latch up. For example, for PFETs1102and1122, isolation terminal1332, bulk terminal1334, and current terminal1336can be coupled together at respective voltage terminals226aand246a,and current terminal1336can be the source terminal. Also, for PFETs1104and1124, isolation terminal1332, bulk terminal1334, and current terminal1336can be coupled together at respective driver outputs224and244. Further, for NFETs1106and1126, isolation terminal1352, bulk terminal1354, and current terminal1356can be coupled together at respective voltage terminals226band246b.

Referring again toFIGS.11and12, ESD circuit1002can include an ESD pull-up control circuit1160to generate pull-up control signals1032aand1032bresponsive to signal1030and control signal232, and ESD circuit1004can include an ESD pull-up control circuit1162to generate pull-up control signals1042aand1042bresponsive to signal1040and control signal252. Specifically, responsive to signal1030indicating an ESD event, ESD pull-up control circuit1160can set pull-up control signal1032ato have the same voltage as driver output224, which can reduce the source-gate voltage of PFET1104, and disable PFET1104and pull-up circuit228. ESD pull-up control circuit1160can also forward control signal232as pull-up control signal1032b.In some examples, ESD pull-up control circuit1160can also receive signal1050, and set control signal1032bto have the same voltage as voltage terminal226aresponsive to signal1050indicating that driver circuit212(and control circuit100) is in a disabled state.

Also, responsive to signal1040indicating an ESD event, ESD pull-up control circuit1162can set pull-up control signal1042ato have the same voltage as driver output244, which can also reduce the source-gate voltage of PFET1124to below a threshold and disable PFET1124and pull-up circuit248. ESD pull-up control circuit1162can also forward control signal252as pull-up control signal1042b.In some examples, ESD pull-up control circuit1162can also receive signal1060, and set pull-up control signal1042bto have the same voltage as voltage terminal246ato disable PFET1122responsive to signal1060indicating that driver circuit214(and control circuit100) is in a disabled state.

In the example ofFIG.11, ESD circuit1002can forward control signal232as pull-down control signal1034, and ESD circuit1004can forward control signal252as pull-down control signal1044. In some examples, controller260can set control signals232and252to a high state (e.g., same voltages as voltage terminals226aand246a) to disable PFETs1102and1122prior to control circuit100being enabled, and NFETs1106and1126(of pull-down circuits230and250) can also be enabled. But the enabled NFETs1106and1126can pull down the voltages at respective driver outputs224and244and disable switches202and204, which can stop the switches from removing the electrostatic charge at input voltage terminal102.

InFIG.12, ESD circuit1002can include an ESD pull-down control circuit1202, and ESD circuit1004can include an ESD pull-down control circuit1204. ESD pull-down control circuit1202can provide pull-down control signal1034to disable NFET1106responsive to signal1050indicating that control circuit100is in the disabled state. Also, ESD pull-down control circuit1204can provide pull-down control signal1044to disable NFET1126responsive to signal1060indicating that control circuit100is in the disabled state. In an ESD event the voltages at the driver outputs224and244can increase due to the propagation of the ESD charge, and with NFETs1106and1126disabled, driver outputs224and244can be maintained at the high voltage state to enable switches202and204. Such arrangements allow switches202and204to continue removing the electrostatic charge at input voltage terminal102via rectifier terminal106.

FIG.14illustrates schematics of example internal components of ESD pull-up control circuits1160and1162. Referring toFIG.14, ESD input1006of ESD pull-up control circuit1160can be coupled to driver output224. ESD pull-up control circuit1160can include a sensing circuit1402coupled between ESD input1006and ESD control signal output1014a,which couples to the gate of PFET1104via driver input222a.Sensing circuit1402can include a resistor or a capacitor coupled between ESD input1006and ESD control signal output1014a.Sensing circuit1402can sense the voltage at driver output224(as signal1030) and provide a voltage signal at the gate of PFET1104(as pull-up control signal1032a). ESD pull-up control circuit1160can also include an RC filter1404coupled between driver power state input1008and switching terminal104, and driver power state input1008can be coupled to internal voltage supply terminal110. RC filter1404can receive a voltage of internal voltage supply terminal110(as signal1050), and provide a filtered voltage as voltage signal1405. ESD pull-up control circuit1160can also include an NFET1406coupled between ESD control signal output1014aand switching terminal104, and the gate of NFET1406coupled to the RC filter output. NFET1406can be enabled or disabled by voltage signal1405provided by RC filter1404. In some examples, the gate of NFET1406can also be coupled to enable terminal112, and NFET1406can be enabled or disabled based on enable signal262. The gates of PFET1102and NFET1106are coupled to driver input222b,which can receive control signal232from controller260that bypasses or otherwise is buffered by ESD pull-up control circuit1160.

Also, ESD input1016of ESD pull-up control circuit1162can be coupled to driver output244. ESD pull-up control circuit1162can include a sensing circuit1412coupled between ESD input1016and ESD control signal output1024a,which couples to the gate of PFET1124via driver input242a.Sensing circuit1412can include a resistor or an AC capacitor coupled between ESD input1016and ESD control signal output1024a.Sensing circuit1412can sense the voltage at driver output244(as signal1040) and provide a voltage signal at the gate of PFET1124(as pull-up control signal1042a). ESD pull-up control circuit1162can also include an RC filter1414coupled between driver power state input1018and rectifier terminal106, and driver power state input1018can be coupled to switching terminal104. RC filter1414can receive a voltage of internal voltage supply terminal110(as signal1060), and provide a filtered voltage as a voltage signal1415. ESD pull-up control circuit1162can also include an NFET1416coupled between ESD control signal output1024aand rectifier terminal106, and the gate of NFET1416coupled to the RC filter output. NFET1416can be enabled or disabled by voltage signal1415provided by RC filter1414. In some examples, the gate of NFET1416can also be coupled to enable terminal112, and NFET1416can be enabled or disabled based on enable signal262. The gates of PFET1122and NFET1126are coupled to driver input242b,which can receive control signal252from controller260that bypasses or otherwise is buffered by ESD pull-up control circuit1162.

When control circuit100is enabled and there is no ESD event, internal voltage supply terminal110can have a higher voltage than input voltage terminal102and switching terminal104. For example, referring again toFIG.3, internal voltage supply terminal110can have an internal supply voltage VSUPhigher than input voltage Viand switching terminal voltage VSW. Accordingly, RC filter1404of ESD pull-control circuit1160can generate a voltage signal1405having a higher voltage than switching terminal104, and NFET1406can be enabled. NFET1406can also be enabled by enable signal262. ESD pull-up control circuit1160can connect ESD control signal output1014ato switching terminal104, and provide pull-up control signal1032athat tracks VSW, which enables PFET1104. The state of driver output224can toggle between VSUPand VSW, as shown in graph402ofFIG.4, based on the state of control signal232.

Also, internal voltage supply251can supply a voltage (e.g., VCC) higher than the voltage of rectifier terminal106. Accordingly, RC filter1414of ESD pull-control circuit1162can generate a voltage signal1415having a higher voltage than rectifier terminal106, and NFET1416can be enabled. NFET1416can also be enabled by enable signal262. ESD pull-up control circuit1162can connect ESD control signal output1024ato rectifier terminal106, and provide pull-up control signal1042ahaving the voltage of rectifier terminal106(e.g., a ground voltage), which enables PFET1124. The state of driver output244can also then toggle between VCCand the ground voltage, as shown in graph404ofFIG.4, based on the state of control signal252.

FIG.15illustrates schematics of example operation of ESD pull-up control circuits1160and1162in an ESD event when control circuit100is in a disabled state. Referring toFIG.15, when control circuit100is in a disabled state, both internal voltage supply terminal110and internal voltage supply251can have a low voltage (e.g., ground voltage). Accordingly, RC filter1404of ESD pull-up control circuit1160can generate a voltage signal1405also having a low voltage to disable NFET1406, and RC filter1414of ESD pull-up control circuit1162can generate a voltage signal1415also having a low voltage to disable NFET1416.

During the ESD event, input voltage terminal102may receive ESD signal602including a pulse of electrostatic charge. ESD signal602can propagate through parasitic capacitance612of switch202and deposit charge at the gate/control terminal of switch202, which increases the voltage of driver output224. With NFET1406disabled and not pulling down the gate of PFET1104, sensing circuit1402can transmit the increased voltage as pull-up control signal1032ato the gate of PFET1104and disable PFET1104. Also, when control circuit100is in the disabled state, controller260can provide a control signal232having a high voltage to disable PFET1102. Accordingly, both PFETs1102and1104are disabled, and the increased voltage at driver output224can be blocked from reaching internal voltage supply terminal110by the back-to-back body diodes1112(of PFET1102) and1114(of PFET1104).

Also, the increased voltage of driver output224can enable switch202, and the enabled switch202can transmit ESD signal602to switching terminal104. From switching terminal104, ESD signal602can propagate through parasitic capacitance614and deposit charge at the gate/control terminal of switch204, which increases the voltage of driver output244of driver circuit214. With NFET1416disabled and not pulling down the gate of PFET1124, sensing circuit1412can transmit the increased voltage as pull-up control signal1042ato the gate of PFET1124and disable PFET1124. Also, when control circuit100is in the disabled state, controller260can provide a control signal252having a high voltage to disable PFET1122. Accordingly, both PFETs1122and1124are disabled, and the increased voltage at driver output244can be blocked from reaching internal voltage supply251by the back-to-back body diodes1132(of PFET1122) and1134(of PFET1124).

FIG.16illustrates schematics of another example of ESD pull-up control circuits1160and1162. Referring toFIG.16, ESD input1006can be coupled to input voltage terminal102, and ESD input1016can be coupled to switching terminal104, to sense the ESD event. In such examples, sensing circuits1402and1412can each include a capacitive divider, which provides a scaled down version of a voltage at respective input voltage terminals102and switching terminal104. During the ESD event, sensing circuit1402can provide pull-up control signal1032aby scaling down signal1030(e.g., ESD signal602at input voltage terminal102), and sensing circuit1412can provide pull-up control signal1042aby scaling down signal1040(e.g., ESD signal602transmitted by switch202to switching terminal104).

FIG.17illustrates schematics of another example of ESD pull-up control circuits1160and1162. Referring toFIG.17, ESD pull-up control circuit1160can include control signal input1012to receive control signal232from controller260. ESD pull-up control circuit1160can forward control signal232as pull-down control signal1034to NFET1106. ESD pull-up control circuit1160can also provide pull-up control signal1032ato PFET1104as described above. Also, ESD pull-up control circuit1160can include a logic circuit1702coupled to the output of RC filter1404and control signal input1012. Logic circuit1702can include a NAND logic gate to provide pull-up control signal1032bto PFET1102based on signal1405from RC filter1404(or enable signal262) and control signal232. Logic circuit1702can provide pull-up control signal1032bhaving a high voltage (e.g., higher than internal supply voltage terminal110) to disable PFET1102, if signal1405or enable signal262indicate that control circuit100is disabled. Logic circuit1702can also forward control signal232as pull-up control signal1032bif control circuit100is enabled.

Also, ESD pull-up control circuit1162can include control signal input1022to receive control signal232from controller260. ESD pull-up control circuit1162can forward control signal252as pull-down control signal1044to NFET1126. ESD pull-up control circuit1162can also provide pull-up control signal1042ato PFET1124as described above. Also, ESD pull-up control circuit1162can include a logic circuit1704coupled to the output of RC filter1414and control signal input1022. Logic circuit1704can also include a NAND logical gate to provide pull-up control signal1042bto PFET1122based on signal1415from RC filter1414(or enable signal262) and control signal252. Logic circuit1704can provide pull-up control signal1042bhaving a high voltage (e.g., higher than switching terminal104) to disable PFET1122if signal1415or enable signal262indicate that control circuit100is disabled. Logic circuit1704can also forward control signal252as pull-up control signal1042bif control circuit100is enabled.

FIG.18illustrates schematics of example ESD circuits1002and1004including the respective pull-down control circuits1202and1204. Referring toFIG.18, ESD circuit1002can include ESD pull-down control circuit1202. Pull-down control circuit1202can include a logic gate, such as logic AND gate, coupled to control signal input1012and the output of RC filter1404. Pull-down control circuit1202can provide pull-down control signal1034having a low voltage (e.g., a ground voltage) to disable NFET1106if signal1405has a low voltage (e.g., a ground voltage) indicating that control circuit100is disabled. In some examples, ESD pull-down control circuit1202can also be coupled to enable terminal102, and can provide pull-down control signal1034having a low voltage to disable NFET1106if enable signal262indicates that control circuit100is disabled. ESD pull-down control circuit1202can also forward control signal232as pull-down control signal1034if control circuit100is enabled. ESD circuit1002also includes ESD pull-up control circuit1160(e.g., sensing circuit1402, logic circuit1702ofFIG.17) to generate pull-up control signals1032aand1032b.

ESD circuit1004can include ESD pull-down control circuit1202. Pull-down control circuit1202can include a logic gate, which can also be a logic AND gate, coupled to control signal input1022and the output of RC filter1414. Pull-down control circuit1202can provide pull-down control signal1044having a low voltage (e.g., a ground voltage) to disable NFET1126if signal1415has a low voltage (e.g., a ground voltage) indicating that control circuit100is disabled. In some examples, ESD pull-down control circuit1204can also be coupled to enable terminal102, and can provide pull-down control signal1044having a low voltage to disable NFET1126if enable signal262indicates that control circuit100is disabled. ESD pull-down control circuit1204can also forward control signal252as pull-down control signal1044if control circuit100is enabled. ESD circuit1004also includes ESD pull-up control circuit1162(e.g., sensing circuit1412, logic circuit1704ofFIG.17) to generate pull-up control signals1042aand1042b.

FIG.19illustrates schematics of example operations of ESD circuits1002and1004in an ESD event when control circuit100is in a disabled state. The operations of ESD pull-up control circuits1160(including sensing circuit1402) and1162(including sensing circuit1412) are identical to the example operations described inFIG.15. Also, because control circuit100is in a disabled state, RC filters1404and1414can provide respective signals1405and1415having a low voltage. Accordingly, ESD pull-down control circuit1202can provide pull-down control signal1034having a low voltage, and ESD pull-down control circuit1204can provide pull-down control signal1044having a low voltage. NFETs1106and1126can be disabled, and the increased voltages (due to propagation of ESD signal602) at driver outputs224and244can be maintained. Accordingly, switches202and204can remain enabled to drain away ESD current1902from input voltage terminal102via rectifier terminal106to ground.

FIG.20includes waveform graphs that illustrate example operations of ESD circuits1002and1004in an ESD event.FIG.20includes graphs2002,2004,2006,2008,2010, and2012. Graph2002illustrates the time-variation of electrostatic charge at input voltage terminal102, and graph2004illustrates the time-variation of a voltage at input voltage terminal102(Vi). Also, graph2006illustrates the time-variation of a voltage at switching terminal104(VSW), and graph2008illustrates the time-variation of a voltage at internal voltage supply terminal110(VSUP). Further, graph2010illustrates the time-variation of pull-up control signal1032aprovided by ESD circuit1002, and graph2012illustrates the time-variation of pull-up control signal1042aprovided by ESD circuit1004.

At time T0, an ESD event occur, and input voltage terminal102receives electrostatic charge represented by C0in graph2002. Because of the electrostatic charge, the voltage at input voltage terminal102rises to Vi0. The electrostatic charge can propagate through parasitic capacitance612and charge up the capacitance at driver output224of ESD circuit1002, which increases the voltage at driver output224and enables switch202. The enabled switch202can transmit the electrostatic charge to switching terminal104, which increases the voltage of switching terminal104to VSW0. The electrostatic charge can also propagate from switching terminal104to driver output244via parasitic capacitance614and increase the voltage at driver output244, which enables switch204.

Sensing circuit1402can provide control pull-up control signal1032abased on the increased driver output224. Accordingly, pull-up control signal1032acan reach a peak voltage V1032a0at T0. Also, sensing circuit1402can provide pull-up control signal1042abased on the increased driver output244. Accordingly, pull-up control signal1042acan reach a peak voltage V1042a0at T0. Because control signal1032ahas a high voltage, PFET1104can be disabled to block the electrostatic charge from reaching internal voltage supply terminal110. Accordingly, the voltage of internal voltage supply terminal110can stay at VSUP0.

After time T0, ESD circuit1002can disable NFET1106and maintain the increased voltage at driver output224, and switch202can be enabled. Also, ESD circuit1004can disable NFET1116and maintain the increased voltage at driver output244, and switch204can be enabled. Accordingly, the electrostatic charge at input voltage terminal102can be drained away to ground through switches202and204, and both the electrostatic charge and the voltage at input voltage terminal102reduce with time. The charge at driver outputs224and244also reduce with time because the charge leak through the respective parasitic capacitances612and614and switches202and204to ground, and the voltages at driver outputs224and244also reduce. Accordingly, the voltages of pull-up control signals1032aand1042a,which track the voltages at driver outputs224and244, also reduce with time. But because switches202and204remain enabled, the voltage of switching terminal104tracks the voltage at input voltage terminal102and also reduce with time. The voltages at input voltage terminal102(Vi) and switching terminal104(VSW) can reduce and approach the voltage at internal supply voltage terminal110(VSUP0) at time T1when most or all of the ESD charge has been removed.

In this description, the term “couple” may cover connections, communications or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first example, device A is directly coupled to device B; or (b) in a second example, device A is indirectly coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B, so device B is controlled by device A via the control signal provided by device A.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described herein as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, such as by an end-user and/or a third party.

While certain components may be described herein as being of a particular process technology, these components may be exchanged for components of other process technologies. Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series or in parallel between identical two nodes as the single resistor or capacitor.

Uses of the phrase “ground voltage potential” in this description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter.