High speed memory device having different read and write clock signals

A memory device includes a global decoder circuit and two memory cell array devices, each of which is disposed adjacent to a respective one of opposing first and second sides of the global decoder circuit, and has global word lines coupled to the global decoder circuit. Each of two data input buffers is disposed at a third side of the global decoder circuit adjacent to a respective one of the memory cell arrays, and is coupled to the respective one of the memory cell arrays. A write control circuit is coupled to and is disposed adjacent to the third side of the global decoder circuit. A write clock buffer is disposed adjacent to the third side of the global decoder circuit, and is coupled to the data input buffers. A read control circuit is coupled to and is disposed adjacent to a fourth side of the global decoder circuit. Each of two multiplexer sets is coupled to bit lines of a respective one of the memory cell array devices. Each of two output circuits is coupled to a respective one of the multiplexer sets. A read clock buffer is disposed adjacent to the fourth side of the global decoder circuit, and is coupled to the output circuits.

BACKGROUND OF THE INVENTION
 1. Field of the Invention
 The invention relates to a memory device, such as an SRAM, that has
 different read and write clock signals.
 2. Description of the Related Art
 Referring to FIG. 1, a conventional memory device is shown to comprise a
 global decoder circuit 11, two pairs of memory cell arrays 12 each of
 which is disposed adjacent to a respective one of opposing first and
 second sides of the global decoder circuit 11 and is coupled to the global
 decoder circuit 11, a write control circuit 13 coupled to and disposed
 adjacent to a third side of the global decoder circuit 11 between the
 first and second sides, a read control circuit 14 coupled to and disposed
 adjacent to a fourth side of the global decoder circuit 11 opposite to the
 third side, a pre-decoder circuit 15 coupled to the global decoder circuit
 11 and the read control circuit 14 and disposed between the fourth side of
 the global decoder circuit 11 and the read control circuit 14, a read
 clock buffer 16 disposed on one side of the read control circuit 14
 opposite to the pre-decoder circuit 15, a write clock buffer 17 disposed
 on one side of the read clock buffer 16 opposite to the read control
 circuit 14, and a pair of data input buffers 18, each of which is disposed
 at the third side of the global decoder circuit 11 adjacent to a
 respective one of the pairs of memory cell arrays 12, and is coupled to an
 external data input device (not shown), the respective one of the pairs of
 memory cell arrays 12 and the write clock buffer 17. The global decoder
 circuit 11 includes a write global decoder portion 111 and a read global
 decoder portion 112. Each memory cell array 12 includes a local decoder
 portion 121 between two mxn cell array portions 122. A multiplexer (MUX)
 123 has an input side coupled to bit lines of the cell array portions 122
 of the memory cell arrays 12. A sense amplifier (SA) 124 is coupled to an
 output side of the multiplexer 123. An output circuit (DO) 125 is coupled
 to an output end of the sense amplifier 124, and is further coupled to the
 read clock buffer 16.
 A write operation for the aforesaid conventional memory device is conducted
 as follows: Input data to the memory cell arrays 12 are initially sent to
 the data input buffers 18. When write address sets corresponding to the
 input data are received by the write control circuit 13, the latter
 generates appropriate write address and write control signals that are
 provided to the write global decoder portion 111 of the global decoder
 circuit 11 to enable writing of the input data into the memory cell arrays
 12. At this time, the write global decoder portion 111 and the local
 decoder portions 121 of the memory cell arrays 12 decode the write address
 sets so that appropriate ones of the memory cells of the cell array
 portions 122 are activated. Write clock signals from the write clock
 buffer 17 are received by the data input buffers 18 so as to control the
 transmission of the input data from the data input buffers 18 to the
 memory cell arrays 12. The input data are written into the activated ones
 of the memory cells of the cell array portions 122 at this stage.
 A read operation for the aforesaid conventional memory device is conducted
 as follows: When read address sets are received by the read control
 circuit 14, the latter generates appropriate read address and read control
 signals to the global decoder circuit 11 to enable reading of the memory
 cell arrays 12. At this time, the pre-decoder circuit 15, the read global
 decoder portion 112 and the local decoder portions 121 of the memory cell
 arrays 12 decode the read address sets so that appropriate ones of the
 memory cells of the cell array portions 122 are activated. Data in the
 activated ones of the memory cells of the cell array portions 122 are
 received by the multiplexer 123. The output of the multiplexer 123 is
 sensed by the sense amplifier 124, and is provided to the output circuit
 125. Read clock signals from the read clock buffer 16 are received by the
 output circuit 125 to control the transmission of output data to an
 external device (not shown).
 Some of the drawbacks of the aforesaid conventional memory device are as
 follows:
 1. Because the write clock buffer 17 and the data input buffers 18 are
 disposed on opposite sides of the global decoder circuit 11, the distance
 between the write clock buffer 17 and the data input buffers 18 is
 relatively long such that parasitic effect is not negligible and can
 affect adversely synchronized transmission of the input data to the memory
 cell arrays 12.
 2. The signal strength at the bit lines of the cell array portions 122 is
 relatively weak, and is further weakened by coupling between the bit lines
 and the multiplexer 123, thereby leading to errors in the data sensed by
 the sense amplifier 124.
 3. The memory cell arrays 12 are relatively large due to the presence of
 the local decoder portions 121. The large memory cell arrays 12 require
 relatively long global word lines for connection to the global decoder
 circuit 11. The relatively long global word lines are prone to errors due
 to parasitic effect.
 SUMMARY OF THE INVENTION
 Therefore, the object of the present invention is to provide a memory
 device of the aforesaid type that is capable of overcoming the
 above-mentioned drawbacks commonly associated with the prior art.
 According to this invention, a memory device comprises a global decoder
 circuit, two memory cell array devices, two data input buffers, a write
 control circuit, write clock means, a read control circuit, two
 multiplexer sets, two output circuits, and read clock means.
 The global decoder circuit has opposite first and second sides, and
 opposite third and fourth sides between the first and second sides.
 Each of the memory cell array devices is disposed adjacent to a respective
 one of the first and second sides of the global decoder circuit, and has
 global word lines coupled to the global decoder circuit, and bit lines.
 Each of the data input buffers is disposed at the third side of the global
 decoder circuit adjacent to a respective one of the memory cell arrays, is
 coupled to the respective one of the memory cell arrays, and is adapted to
 receive input data and to transmit the input data to the respective one of
 the memory cell arrays.
 The write control circuit is coupled to and is disposed adjacent to the
 third side of the global decoder circuit. The write control circuit is
 adapted to receive write address sets corresponding to the input data and
 to generate appropriate write address and write control signals that are
 provided to the global decoder circuit upon receipt of the write address
 sets to enable writing of the input data into the memory cell array
 devices.
 The write clock means, which is disposed adjacent to the third side of the
 global decoder circuit and which is coupled to the data input buffers,
 generates write clock signals that are provided to the data input buffers
 so as to control transmission of the input data from the data input
 buffers to the memory cell array devices.
 The read control circuit is coupled to and is disposed adjacent to the
 fourth side of the global decoder circuit. The read control circuit is
 adapted to receive read address sets and to generate appropriate read
 address and read control signals that are provided to the global decoder
 circuit upon receipt of the read address sets to enable reading of the
 memory cell array devices.
 Each of the multiplexer sets is coupled to the bit lines of a respective
 one of the memory cell array devices.
 Each of the output circuits is coupled to a respective one of the
 multiplexer sets.
 The read clock means, which is disposed adjacent to the fourth side of the
 global decoder circuit and which is coupled to the output circuits,
 generates read clock signals that are provided to the output circuits so
 as to control output of data by the output circuits.
 The memory device further comprises two sense amplifier sets, each of which
 is disposed between and couples a respective one of the multiplexer sets
 to the bit lines of a respective one of the memory cell array devices.
 In a preferred embodiment, each of the memory cell array devices includes a
 pair of memory cell arrays. Each of the memory cell arrays includes two
 cell array portions, and a local decoder portion between the cell array
 portions. The cell array portions have the bit lines, and local word lines
 coupled to the local decoder portion. The local decoder portion has the
 global word lines.
 At least one component of the local decoder portion is disposed externally
 of an area allocated to the memory cell array, is disposed in a space
 between the memory cell array and the adjacent one of the data input
 buffers, and is coupled to the write control circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
 Before the present invention is described in greater detail, it should be
 noted that like elements are denoted by the same reference numerals
 throughout the disclosure.
 Referring to FIG. 2, the preferred embodiment of a memory device according
 to the present invention is shown to be embodied in an SRAM having
 different read and write clock signals, a multiplexed output, a
 demultiplexed input, and an embedded architecture. The memory device
 comprises a global decoder circuit 3, two memory cell array devices each
 constituted by a pair of memory cell arrays 2, a write control circuit 4,
 a read control circuit 5, a pre-decoder circuit 51, a read clock buffer
 52, a write clock buffer 41, a pair of data input buffers 6, two sense
 amplifier sets 7, two multiplexer sets 8, and two output circuits 9.
 The global decoder circuit 3 includes a write global decoder portion 31 and
 a read global decoder portion 32.
 Each of the two pairs of memory cell arrays 2 is disposed adjacent to a
 respective one of opposing first and second sides of the global decoder
 circuit 3. Each memory cell array 2 includes two mxn cell array portions
 21, and a local decoder portion 22 between the cell array portions 21. The
 cell array portions 21 have bit lines (not shown), and local word lines
 211 coupled to the local decoder portion 22. The local decoder portion 22
 has global word lines 221 coupled to the global decoder circuit 3.
 The write control circuit 4 is coupled to and is disposed adjacent to a
 third side of the global decoder circuit 3 between the first and second
 sides.
 The read control circuit 5 is coupled to and is disposed adjacent to a
 fourth side of the global decoder circuit 3 opposite to the third side.
 The pre-decoder circuit 51 is coupled to the read global decoder portion 32
 of the global decoder circuit 3 and the read control circuit 5, and is
 disposed between the fourth side of the global decoder circuit 3 and the
 read control circuit 5.
 The read clock buffer 52 is disposed adjacent to the fourth side of the
 global decoder circuit 3. Particularly, the read clock buffer 52 is
 disposed on one side of the read control circuit 5 opposite to the
 pre-decoder circuit 51.
 The write clock buffer 41 is disposed adjacent to the third side of the
 global decoder circuit 3.
 Clock signals from the read and write clock buffers 52, 41 preferably have
 different frequencies.
 Each of the data input buffers 6 is coupled to an external data input
 device (not shown), is disposed at the third side of the global decoder
 circuit 3 adjacent to a respective one of the pairs of memory cell arrays
 2, and is coupled to the write clock buffer 41.
 Each of the sense amplifier sets 7 includes two first sense amplifier units
 (SA1) and a second sense amplifier unit (SA2). Each of the first sense
 amplifier units (SA1) is coupled to the bit lines of one of the cell array
 portions 21 of one of the memory cell arrays 2, said one of the cell array
 portions 21 of said one of the memory cell arrays 2 being remote to the
 other one of the memory cell arrays 2 in the corresponding pair of the
 memory cell arrays 2. The second sense amplifier unit (SA2) has a size
 twice that of the first sense amplifier unit (SA1), and is coupled to the
 bit lines of adjacent ones of the cell array portions 21 in the
 corresponding pair of the memory cell arrays 2.
 Each of the multiplexer sets 8 includes two first multiplexer units (MUX1)
 and a second multiplexer unit (MUX2). Each of the first multiplexer units
 (MUX1) has an input side coupled to a respective one of the first sense
 amplifier units (SA1). The second multiplexer unit (MUX2) has an input
 side coupled to a respective one of the second sense amplifier units
 (SA2).
 Each of the output circuits 9 includes three amplifiers (DO) coupled
 respectively to output sides of the first and second multiplexer units
 (MUX1, MUX2) of a corresponding one of the multiplexer sets 8, and is
 further coupled to the read clock buffer 52.
 A write operation for the aforesaid conventional memory device is conducted
 as follows: Input data to the memory cell arrays 2 are initially sent by
 the external data input device (not shown) to the data input buffers 6,
 whereas write address sets corresponding to the input data are sent to the
 write control circuit 4. The write control circuit 4 responds by
 generating appropriate write address and write control signals that are
 provided to the write global decoder portion 31 of the global decoder
 circuit 3 to enable writing of the input data into the memory cell arrays
 2. At this time, the write global decoder portion 31 and the local decoder
 portions 22 of the memory cell arrays 2 decode the write address sets so
 that appropriate ones of the memory cells of the cell array portions 21
 are activated. Write clock signals from the write clock buffer 41 are
 received by the data input buffers 6 so as to control the transmission of
 the input data from the data input buffers 6 to the memory cell arrays 2.
 The input data are written into the activated ones of the memory cells of
 the cell array portions 21 at this stage.
 Because the write clock buffer 41 and the data input buffers 6 are disposed
 on the same side of the global decoder circuit 3, the distance between the
 write clock buffer 41 and the data input buffers 6 is shorter as compared
 to that of the conventional memory device described beforehand such that
 the parasitic effect on synchronized transmission of the input data to the
 memory cell arrays 2 is minimal.
 A read operation for the aforesaid conventional memory device is conducted
 as follows: When read address sets are received by the read control
 circuit 5 from an external data output device (not shown), the latter
 generates appropriate read address and read control signals to the global
 decoder circuit 3 to enable reading of the memory cell arrays 2. At this
 time, the pre-decoder circuit 51, the read global decoder portion 32 of
 the global decoder circuit 3, and the local decoder portions 22 of the
 memory cell arrays 2 decode the read address sets so that appropriate ones
 of the memory cells of the cell array portions 21 are activated. Data in
 the activated ones of the memory cells of the cell array portions 21 are
 amplified by the sense amplifier sets 7 to be within a full swing range of
 the latter. The amplified outputs of the sense amplifier sets 7 are
 received by the multiplexer sets 8, which provide appropriate ones of the
 amplified outputs to the output circuits 9. The output circuits 9 enhance
 the electrical current content of the signals from the multiplexer sets 8
 to enhance the driving capability of the same when received by the
 external data output device (not shown). Read clock signals from the read
 clock buffer 52 are received by the output circuits 9 to control output of
 data by the latter.
 Because the multiplexer sets 8 are coupled indirectly to the bit lines of
 the memory cell arrays 2 via the sense amplifier sets 7, output errors due
 to coupling between the bit lines and the multiplexer sets 8 can be
 minimized.
 FIG. 3 illustrates another preferred embodiment of a memory device
 according to the present invention. The main difference between the
 embodiments of FIGS. 2 and 3 resides in the local decoder portions 22, 22'
 of the memory cell arrays 2. Unlike the local decoder portion 22 of the
 previous embodiment, the local decoder portion 22' has at least one
 component 222' that is disposed externally of an area allocated to the
 memory cell array 2. Particularly, the component 222' is disposed in a
 space between the memory cell array 2 and the adjacent data input buffer
 6, and is coupled to the write control circuit 4. In the embodiment of
 FIG. 2, the local decoder portion 22 includes a three-input AND gate 23
 (see FIG. 4). In the embodiment of FIG. 3, the three input AND gate is
 implemented using an equivalent logic circuit that includes a two-input
 NAND gate 24, an inverter 25 and a two-input NOR gate 26 (see FIG. 5). The
 component 222' can thus be the inverter 25. By disposing the component
 222' externally of the area allocated to the memory cell array 2, the area
 occupied by the local decoder portion 22' in the memory cell array 2 can
 be reduced, thus resulting in shorter global word lines for connection to
 the global decoder circuit 3 that are less prone to errors due to the
 parasitic effect.
 While the present invention has been described in connection with what is
 considered the most practical and preferred embodiments, it is understood
 that this invention is not limited to the disclosed embodiments but is
 intended to cover various arrangements included within the spirit and
 scope of the broadest interpretation so as to encompass all such
 modifications and equivalent arrangements.