Magnetic memory cell structure with improved read margin

A semiconductor device includes a memory cell. The cell includes: a magnetic recording layer (MRL) formed of ferromagnetic material; first and second magnetization fixed layers (MFLs) coupled to the MRL; first and second reference layers (RLs) opposed to the MRL; and first and second tunnel barrier films (TBFs) inserted between the MRL and the first and second reference layers (RLs), respectively. The first MFL has a magnetization fixed in a first direction, and the second MFL has a magnetization fixed in a second direction opposite to the first direction. The first and second RLs and the first and second TBFs are positioned between the first and second MFLs. The first RL has a magnetization fixed in a third direction which is selected from the first and second directions, and the second RL has a magnetization fixed in a fourth direction opposite to the third direction.

INCORPORATION BY REFERENCE

This application claims the benefit of priority based on Japanese Patent Application No. 2011-163167, filed on Jul. 26, 2011, the disclosure of which is incorporated herein by reference.

BACKGROUND

The present invention relates to semiconductor devices and magnetic random access memories (MRAMs), more particularly, to magnetic memory cells of the magnetic domain wall motion type.

Recently, the MRAM, which uses magnetoresistance effect elements as memory cells, has been proposed as one of non-volatile memories, which are a sort of semiconductor devices. Especially, magnetoresistance effect elements having a magnetic tunnel junction (which may be referred to as “MTJ”, hereinafter) are often used as MRAM memory cells due to the advantage of a very large magnetoresistance effect. The magnetic tunnel junction has a laminated structure in which a non-magnetic dielectric film (hereinafter, referred to as tunnel barrier film) is disposed between two ferromagnetic films. Data are stored as the relative direction of the magnetizations of the two ferromagnetic films. For example, the state in which the magnetizations are directed in parallel is correlated with data “0” and the state in which the magnetizations are directed in antiparallel is correlated with data “1”. The electric resistance for a current flowing in the perpendicular direction to the film surface of the laminated structure varies depending on the relative angle of the magnetizations of the two ferromagnetic films. The electric resistance of the magnetic tunnel junction takes the minimum value when the magnetizations are directed in parallel, and takes the maximum value when the magnetizations are directed in antiparallel. The data read is achieved by using the changes in the electric resistance. The MRAM attracts a lot of attention in the field of embedded memories, and there is a demand for the high-speed random access of the MRAM as replacements of SRAMs (static random access memory) and DRAMs (dynamic random access memory).

Various MRAMs are known in the art and one type of the MRAM is the magnetic domain wall motion type. The magnetic domain wall motion type MRAM achieves data writing by moving the magnetic domain wall through the spin transfer effect of spin-polarized electrons with a write current flowing in the in-plane direction of a ferromagnetic film and thereby directing the magnetization of the ferromagnetic film in the direction depending on the direction of the write current. Such a magnetic domain wall motion type MRAM is disclosed in 2009 Symposium on VLSI Technology Digest of Technical Papers 12A-2.

FIG. 1Ais a diagram schematically showing the structure of a memory cell300of the magnetic domain wall motion type MRAM disclosed in this document. The memory cell shown inFIG. 1Aincludes a magnetoresistance effect element1and NMOS transistors51and52. The magnetoresistance effect element1includes: magnetization fixed layers11,12; a magnetic recording layer2disposed on the magnetization fixed layers11,12; a reference layer4; and a tunnel barrier layer3disposed between the magnetic recording layer2and the reference layer4. The magnetization fixed layers11,12and the reference layer4are each formed of a ferromagnetic film having a fixed magnetization. The magnetic recording layer2is also formed of a ferromagnetic film. The magnetizations of regions2aand2bof the magnetic recording layer2, which are coupled with the magnetization fixed layers11and12, respectively, are fixed by the exchange coupling with the magnetization fixed layers11and12. Hereinafter, the regions2aand2bmay be referred to as magnetization fixed regions2aand2b, respectively. The region2cbetween the magnetization fixed regions2aand2bhas a reversible magnetization. Hereinafter, the region2cmay be referred to as magnetization reversible region2c. The reference layer4, the tunnel barrier layer3and the magnetization reversible region2cform an MTJ.

The NMOS transistor51has a drain connected to the magnetization fixed layer11and a source connected to a write bitline BL1. The NMOS transistor52has a drain connected to the magnetization fixed layer12and a source connected to a write bitline BL2. The gates of the NMOS transistors51and52are commonly connected to the word line WL. In the structure shown inFIG. 1A, the reference layer4is connected to the grounding line GND. InFIG. 1A, the arrows101,102,110and120indicate the directions of the magnetizations of the respective layers.

FIG. 2Ais a cross section view showing an example of the cross section structure of the memory cell300shown inFIG. 1AandFIG. 3Ais a plan view showing an example of the layout of the memory cell300.FIG. 2Aschematically shows the NMOS transistors51and52, because the diffusion layers of the NMOS transistors51and52are actually disposed to extend in the direction parallel to the write bitlines BL1and BL2.

As shown inFIG. 2A, the tunnel barrier film3and the reference layer4are sequentially laminated on the magnetic recording layer2to form an MTJ. The magnetization fixed layers11and12are disposed in contact with the bottom surface of the magnetic recording layer2near both ends of the magnetic recording layer2. The reference layer4is connected to a grounding line GND via a via-contact8. The drain51aof the NMOS transistor51is connected to the magnetization fixed layer11via a via-contact61, and the drain52aof the NMOS transistor52is connected to the magnetization fixed layer12via a via-contact62. The grounding line GND is formed of a metal interconnection located in a first interconnection layer. The bitlines BL1and BL2are, on the other hand, formed of a metal interconnection located in a second interconnection layer which is positioned above the first interconnection layer.

As shown inFIG. 3A, each word line WL is provided in the form of a polysilicon gate and disposed to intersect diffusion layers53and54. Each NMOS transistor51is formed by a word line WL and a diffusion layer53, and each NMOS transistor52is formed by a word line WL and a diffusion layer54. The sources of the NMOS transistors51and52are connected to the write bitlines BL1and BL2via via-contacts63and64. The reference layer4is connected to the grounding line GND via the via-contact8. The grounding lines GND are disposed in parallel to the word line WLs.

The data writing into the memory cell300shown inFIGS. 1A to 3Ais achieved by generating a write current flowing between the write bitlines BL1and BL2with the NMOS transistors51and52turned on, and thereby switching the magnetization direction110of the magnetization reversible region2cof the magnetic recording layer2. The data reading is, on the other hand, achieved by generating a read current flowing from the write bitline BL1(or BL2) to the grounding line GND via the MTJ of the magnetoresistance effect element1and comparing the read current with a reference current by a sense amplifier (not shown). The ground line GND is shared over the memory array.

AlthoughFIGS. 1A to 3Ashows that the reference layer4is connected to the grounding line GND in the memory cell300, the reference layer4may be connected to a read bitline RBL, which is individually provided for each column, in place of the grounding line GND.FIGS. 1B to 3Bshow such a structure in which the reference layer4is connected to a read bitline RBL. In detail,FIG. 1Bschematically shows the structure of the memory cell300in which the reference layer4is connected to the read bitline RBL, andFIG. 2Bis a cross section view showing an example of the cross section structure of the MRAM cell shown inFIG. 1B.FIG. 3Bis a layout diagram showing an example of the layout of the MRAM cell shown inFIG. 1B. The high-speed read from an MRAM memory cell requires reduction in the capacitance of the interconnection used for data read, and the structure shown inFIGS. 1B to 3B, in which a read bitline RBL is provided for each column, is suitable for the high-speed operation. As shown inFIGS. 2B and 3B, the read bitlines RBL are disposed in parallel to the write bitlines BL1and BL2. In the structure shown inFIG. 2B, in which the read bitlines RBL do not intersect with the write bitlines BL1and BL2, the read bitlines RBL are formed of a metal interconnection located in the first interconnection layer. Except for this point, the memory cell300shown inFIGS. 1B to 3Bhas the same structure as that shown inFIGS. 1A to 3A.

FIG. 4is a block diagram showing one example of the structure of an MRAM which incorporates memory cells300shown inFIGS. 1B to 3B. The MRAM shown inFIG. 4includes a memory cell array in which memory cells300structured as described above are arranged in rows and columns. The memory cell array further includes word lines WL, write bitlines BL1, BL2and read bitlines RBL.

The MRAM further includes an X selector301, a write Y selector302, a write current supply circuit303, a read Y selector304, a read current load circuit305, a sense amplifier306, an output circuit307and a reference current circuit308. The X selector301is connected to the word lines WL, and selects the word line WL connected to the selected memory cell (the memory cell300to be accessed) in the write operation and read operation. InFIG. 4, the selected memory cell is denoted by the numeral300sand the selected word line is denoted by the numeral WLs.

The write Y selector302is connected to the write bitlines BL1and BL2, and selects the write bitlines BL1and BL2connected to the selected memory cell300sas the selected write bitlines BL1sand BL2s. The write current supply circuit303generates a write current to be fed to the selected memory cell300sin response to data inputted to the inputs of the write current supply circuit303.

The read Y selector304is connected to the read bitlines RBL. The read Y selector304selects the read bitline RBL connected to the selected memory cell300sas the selected read bitline RBLs. The read current load circuit305applies a predetermined voltage to the selected read bitline RBLs. The reference current circuit308includes a constant current circuit or reference cells which have the same structure as the memory cells. The sense amplifier306compares the read current flowing through the selected read bitline RBLs with a reference current supplied from the reference current circuit308to identify data stored in the selected memory cell300s. The output circuit307outputs the data identified by the sense amplifier306.

The above-described MRAM suffers from a problem of reduction in the read margin caused by the variability in the MR ratio of the MTJ on the manufacturing processes. In the above-described MRAM, the read current flowing through the MTJ of the selected memory cell300sis compared with the reference current iREFto identify the data stored in the selected memory cell300s. The ratio of the read current iHof the selected memory cell300sfor the MTJ in the high-resistance state to the read current iLfor the MTJ in the low-resistance state depends on the MR ratio of the MTJ.FIG. 5is a graph showing an exemplary waveform of the read current. The sense amplifier306identifies the data by using the differential current ΔH having the current level of the difference between the read current iHand the reference current iREFor the differential current ΔL having the current level of the difference between the read current iLand the reference current iREF. According to a reference in the art, a typical MR ratio of an MTJ is 44%. In this case, the ratio of the read currents iLand iHis represented by expression (1):
iL:iH≈1.44:1.  (1)

In general, the reference current iREFis generated so as to have the average value of the read current iHfor the high-resistance state and the read current iLfor the low-resistance state. The reference current iREFnormalized by the read current iHfor the high-resistance state is represented by expression (2):
iREF=(1.44+1)/2≈1.22.  (2)

Accordingly, the ratio of the read current iHfor the high-resistance state to the reference current iREFis represented by expression (3) and the ratio of the reference current iREFto the read current iLfor the low-resistance state is represented by expression (4):
iH:iREF=1:1.22≈0.82:1, and  (3)
iREF:iL=1.22:1.44≈1:1.18.  (4)
The differential currents ΔL and ΔH which are available for the sense amplifier306in the events that the MTJ of the selected memory cell300sis placed in the low-resistance state and the high-resistance state, respectively, can be represented by the following expressions, which are derived from expressions (1) to (4):

Expressions (7) and (8) which represent the differential currents ΔL and ΔH with the current iH, which is the read current for the high-resistance state, can be obtained from expressions (5) and (6), respectively, as follows:
ΔL=0.18×iH/0.82≈0.22×iH.  (7)
ΔH=0.18×iH/0.82≈0.22×iH.  (8)
As is understood from expressions (7) and (8), only 22% of the read current iHis available as the differential currents ΔL and ΔH, which is fed to the sense amplifier306, for the MR ratio of 44%. This undesirably reduces the read margin when the MR ratio is decreased due to the variability on the manufacturing processes.

It should be noted that techniques for increasing the read margin are disclosed in Japanese Patent Application Publications Nos. 2008-047669, 2007-004969, 2006-185477, 2004-103212, and 2004-046962. According to a study of the inventor, however, there is a more advantageous approach as discussed below.

SUMMARY

In one embodiment, a semiconductor device includes a memory cell. The memory cell includes: a magnetic recording layer formed of ferromagnetic material; first and second magnetization fixed layers coupled to the magnetic recording layer; first and second reference layers opposed to the magnetic recording layer; and first and second tunnel barrier films inserted between the magnetic recording layer and the first and second reference layers, respectively. The first magnetization fixed layer has a magnetization fixed in a first direction, and the second magnetization fixed layer has a magnetization fixed in a second direction opposite to the first direction. The first and second reference layers and the first and second tunnel barrier films are positioned between the first and second magnetization fixed layers. The first reference layer has a magnetization fixed in a third direction which is selected from the first and second directions, and the second reference layer has a magnetization fixed in a fourth direction opposite to the third direction.

The data identification of the memory cell can be achieved by generating a first read current flowing through a first MTJ which includes the first reference layer, the first tunnel barrier film and the magnetic recording layer, generating a second read current flowing through a second MTJ which includes the second reference layer, the second tunnel barrier film and the magnetic recording layer, and comparing the first and second read currents.

The above-described embodiment effectively increases the read margin of a magnetic random access memory.

DETAILED DESCRIPTION

First Embodiment

FIG. 6is a section view showing an exemplary structure of a memory cell200of a magnetic random access memory of a first embodiment andFIG. 7is a plan view showing the layout of the memory cell200. InFIG. 6, the arrows101,102,110,121and122show the magnetization directions of the respective layers.

As shown inFIG. 6, the memory cell200includes a magnetoresistance effect element1A and NMOS transistors51and52. The NMOS transistors51and52are switching elements used for the selection of the memory cell200. The NMOS transistor51has a gate connected to a word line WL and a source connected to a write bitline BL1. Similarly, the NMOS transistor52has a gate connected to the word line WL and a source connected to a write bitline BL2. The write bitlines BL1and BL2are formed in the form of metal interconnections positioned in the first interconnection layer (that is, the lowermost metal interconnection layer). It should be noted thatFIG. 6schematically shows the NMOS transistors51and52, because the diffusion layers of the NMOS transistors51and52are actually disposed to extend in the direction parallel to the write bitlines BL1and BL2.

The magnetoresistance effect element1A includes: magnetization fixed layers11,12; a magnetic recording layer2formed on the upper faces of the magnetization fixed layers11and12; reference layers41,42; and tunnel barrier films31and32disposed between the magnetic recording layer2and the reference layers41and42, respectively.

The magnetization fixed layers11and12are each formed of a ferromagnetic film having a fixed magnetization. The magnetizations of the magnetization fixed layers11and12are directed in the opposite directions. In this embodiment, the magnetization of the magnetization fixed layer11is fixed in the upward direction and that of the magnetization fixed layer12is fixed in the downward direction. The magnetization fixed layer11is connected to the drain51aof the NMOS transistor51via a via-contact61and the magnetization fixed layer12is connected to the drain52aof the NMOS transistor52via a via-contact62.

The magnetic recording layer2is also formed of a ferromagnetic film. Here, the magnetizations of regions2aand2bof the magnetic recording layer2, which are coupled to the magnetization fixed layers11and12, respectively, are fixed by exchange coupling with the magnetization fixed layers11and12. Hereinafter, the regions2aand2bmay be referred to as magnetization fixed regions2aand2b, respectively. The region2cbetween the regions2aand2bhas a reversible magnetization, and therefore the region2cmay be referred to as magnetization reversible region2c.

The tunnel barrier films31and32are disposed on the upper face of the magnetic recording layer2and the reference layers41and42are disposed on the upper faces of the tunnel barrier films31and32, respectively. Two MTJs are formed by the reference layers41,42, the tunnel barrier films31,32and the magnetization reversible region2cof the magnetic recording layer2. The reference layers41and42have magnetizations directed in the opposite directions. In this embodiment, the magnetization of the reference layer41is directed in the upward direction and that of the reference layer42is directed in the downward direction. The reference layer41is connected to a read bitline RBLT via a via-contact81and the reference layer42is connected to a read bitline RBLB via a via-contact82. Both of the read bitlines RBLT and RBLB are formed in the form of metal interconnections positioned in the first interconnection layer (that is, the lowermost metal interconnection layer).

Two memory cells200which are mirror-symmetrically arranged are shown inFIG. 7. The read bitlines RBLT, RBLB and the write bitlines BL1and BL2, which are formed of metal interconnections positioned in the same interconnection layer, are arranged in parallel to one another in accordance with given design rules. The word lines WL are formed in the form of polysilicon gates and disposed to intersect with diffusion layers53and54. The diffusion layers53,54and the word lines WL form the NMOS transistors51and52. The word lines WL are disposed to extend in the perpendicular direction to the direction of the read bitlines RBLT, RBLB and the write bitlines BL1and BL2. The drain of the NMOS transistor51is connected to the magnetization fixed layer11via the via-contact61and the drain of the NMOS transistor52is connected to the magnetization fixed layer12via the via-contact62. Furthermore, the source of the NMOS transistor51is connected to the write bitline BL1via a via-contact91and the source of the NMOS transistor52is connected to the write bitline BL2via a via-contact92. The magnetic recording layer2is arranged at certain distances from the cell boundary and the via-contacts91and92, in accordance with the design rules.

FIG. 8is a block diagram showing one example of the configuration of the MRAM which incorporates memory cells200shown inFIGS. 6 and 7. The MRAM of this embodiment includes a memory cell array in which the memory cells200structured as described above are arrayed in rows and columns. The memory cell array further includes word lines WL, write bitlines BL1, BL2and read bitlines RBLT and RBLB.

The MRAM further includes an X selector201, a write Y selector202, a write current supply circuit203, a read Y selector204, a read current load circuit205, a sense amplifier206and an output circuit207. As described later, the reference current is generated by a selected memory cell200itself and therefore the MRAM does not include any circuit corresponding to the reference current circuit308shown inFIG. 4.

The X selector201is connected to the word lines WL and selects the word line WL connected to a selected memory cell (the memory cell200to be accessed) as the selected word line in the data write operation and the data read operation. InFIG. 8, the selected memory cell is denoted by the numeral200sand the selected word line is denoted by the numeral WLs.

The write Y selector202is connected to the write bitlines BL1and BL2and selects the write bitlines BL1and BL2connected to the selected memory cell200sas the selected write bitlines BL1sand BL2s. The write current supply circuit203generates a write current to be fed to the selected memory cell200sin response to input data DIN inputted to the inputs of the write current supply circuit203.

The read Y selector204is connected to the read bitlines RBLT and RBLB. The read Y selector204selects the read bitlines RBLT and RBLB connected to the selected memory cell200sas the selected read bitlines RBLTs and RBLBs. The read current load circuit205applies a predetermined voltage to the selected read bitlines RBLTs and RBLBs. The sense amplifier206compares read currents flowing through the two selected read bitlines RBLTs and RBLBs to identify data stored in the selected memory cell200s. The output circuit207outputs the data identified by the sense amplifier206as output data DOUT.

Next, a description is given of an exemplary operation of the magnetic random access memory of the first embodiment. In the first embodiment, the magnetizations of the reference layers41and42, which are connected to the read bitlines RBLT and RBLB, respectively, are directed in the opposite directions. The arrows101,102,110,121and122indicate the magnetization direction of the respective layers. Each memory cell200thus structured is configured to generate both of a data current corresponding to stored data and a reference current to be compared with the data current.

There are two allowed states for each memory cell200, andFIGS. 9A and 9Bshow the two allowed states. Each memory cell200stores data as the position of the magnetic domain wall20, that is, the magnetization direction of the magnetization reversible region2c. The following description is given with an assumption that a memory cell200stores “0” data when the magnetization reversible region2chas a magnetization directed in the downward direction and the memory cell stores “1” data when the magnetization reversible region2chas a magnetization directed in the upward direction.

The data writing is achieved by generating a write current flowing between the write bitlines BL1and BL2via the magnetic recording layer2with the NMOS transistors51and52turned on. In detail, when the write current is generated to flow from the write bitline BL1to the write bitline BL2via the magnetization fixed layer2, the magnetic domain wall20moves in the magnetic recording layer2and reaches a position between the magnetization fixed layer11and the reference layer41as shown inFIG. 9A. In this case, the magnetization directions of the reference layer41and the magnetization reversible region2care directed in the opposite directions and the magnetization directions of the reference layer42and the magnetization reversible region2care directed in the same direction. This results in that the MTJ incorporating the reference layer41, the tunnel barrier film31and the magnetization reversible region2cis placed into the high-resistance state, and the MTJ incorporating the reference layer42, the tunnel barrier film32and the magnetization reversible region2cis placed into the low-resistance state.

When the write current is generated to flow from the write bitline BL2to the write bitline BL1via the magnetization fixed layer2, on the other hand, the magnetic domain wall20moves in the magnetic recording layer2and reaches a position between the magnetization fixed layer12and the reference layer42as shown inFIG. 9B. In this case, the magnetization directions of the reference layer41and the magnetization reversible region2care directed in the same direction and the magnetization directions of the reference layer42and the magnetization reversible region2care directed in the opposite directions. This results in that the MTJ incorporating the reference layer41, the tunnel barrier film31and the magnetization reversible region2cis placed into the low-resistance state, and the MTJ incorporating the reference layer42, the tunnel barrier film32and the magnetization reversible region2cis placed into the high-resistance state.

The data reading is achieved by applying a predetermined voltage to the read bitlines RBLT and RBLB to generate read currents flowing through the two MTJs of the selected memory cell200s. When “0” data are to be read, that is, when the magnetic domain wall20is positioned between the reference layer41and the magnetization fixed layer11as shown inFIG. 9A, the MTJ connected to the read bitline RBLTs is placed in the high-resistance state and the MTJ connected to the read bitline RBLBs is placed in the low-resistance state. When the word line WL is set to the high level to turn on the NMOS transistors51and52with the write bitlines BL1and BL2fixed to the circuit ground level and with the read bitlines RBLTs and RBLBs applied with a predetermined voltage, read currents iRBLTand iRBLBflow through the read bitlines RBLTs and RBLBs, respectively. Since the read current iRBLTflows through the MTJ in the high-resistance state and the read current iRBLBflows through the MTJ in the low-resistance state, the read current iRBLBis larger than the read current iRBLT. As is understood from this discussion, the data identification can be achieved by comparing the read currents iRBLTand iRBLBby the sense amplifier206. In this embodiment, the selected memory cell200scan be determined as storing “0” data from the fact that the read current iRBLBis larger than the read current iRBLT. In this case, the output circuit207outputs “0” data in response to the comparison result obtained by the sense amplifier206.

The data reading of “1” data can be achieved in the same way. The selected memory cell200sis determined as storing “1” data when the read current iRBLTis larger than the read current iRBLB.

The data reading described above effectively enlarges the read margin.FIG. 10is a graph showing the current levels of the read currents in reading “0” data. When “0” data are read from the selected memory cell200, the read current iRBLTflowing through the read bitline RBLTs is equal to a current flowing through the MTJ in the high-resistance state, and the read current iRBLBflowing through the read bitline RBLBs is equal to a current flowing through the MTJ in the low-resistance state. The ratio of the read currents depends on the MR ratio and the ratio of the read currents iRBLTand iRBLBis 1:1.44 for an MR ratio of 44%, which is a value disclosed in a reference in the art.

Accordingly, the differential current ΔRBL is represented by expression (9):

The read current iRBLT, which is the current flowing through the MTJ in the high-resistance state, is equal to the read current iHshown inFIG. 5. Accordingly, the differential current ΔRBL sensed by the sense amplifier206in this embodiment can be represented as follows:
ΔRBL=0.44×iH.  (10)

In the MRAM shown inFIG. 4, the differentia currents ΔL and ΔH are about 0.22 times the read current iHas indicated by expressions (7) and (8). In this embodiment, on the other hand, a differential current of 0.44 times the read current iHcan be obtained as is understood from expression (10) and the read margin is effectively enlarged. The same goes for the case when “1” data are read.

An additional advantage is that the effect of the on-resistance of the NMOS transistors51and52is made negligible, since each of the two MTJs used for the data reading is connected to the drains of the NMOS transistors51and52. In the MRAM structure shown inFIG. 4, in which the reference current is generated from a pair of reference cells, the variability in the on-resistance of the MOS transistors used for the memory cell selection undesirably reduces the read margin. The MRAM of this embodiment, in which the effect of the on-resistance of the MOS transistors used for the memory cell selection can be neglected, can make effective use of the MR ratio, and enlarge the read margin.

Although the magnetization directions of the magnetization fixed layers11,12, the magnetic recording layer2and the reference layers41and42are all described as being directed in the directions perpendicular to the film surfaces, the magnetization directions of these layers may be directed in the in-plane directions instead. Also in this case, the magnetic random access memory of this embodiment can operate in the same way.

Second Embodiment

FIG. 11is a cross section view showing an exemplary structure of a memory cell200A of a magnetic random access memory of a second embodiment. In the second embodiment, the reference layer42is positioned opposed to the reference layer41across the magnetic recording layer2and disposed on the same surface of the magnetic recording layer2as the magnetization fixed layers11and12. The tunnel barrier film32is disposed between the reference layer42and the magnetic recording layer2. The magnetization direction of the reference layer42(indicated by the arrow122) is directed in the opposite direction to the magnetization direction of the reference layer41. The reference layer42is connected to the read bitline RBLB via a via-contact82. The read bitline RBLB is positioned under the magnetic recording layer2.

The magnetization fixed layer11is connected to a metal interconnection71via a via-contact83and the metal interconnection71is connected to the drain51aof the NMOS transistor51via a via-contact63.

The magnetization fixed layer12is connected to a metal interconnection72via a via-contact84and the metal interconnection72is connected to the drain52aof the NMOS transistor52via a via-contact64.FIG. 11shows the NMOS transistors51and52only schematically, because the diffusion layers of the NMOS transistors51and52are actually formed to extend in parallel to the write bitlines BL1and BL2. The magnetoresistance effect element1B is formed between the first interconnection layer (that is, the lowermost metal interconnection layer) in which the metal interconnections71,72and the read bitline RBLB are positioned, and the second interconnection layer (that is, the second lowermost metal interconnection layer) in which the write bitlines BL1, BL2and the read bitline RBLT.

FIG. 12is a plan view showing the layout of MRAM cells in the second embodiment. As shown inFIG. 12, two memory cells200A are mirror-symmetrically arranged.

The write bitlines BL1and BL2and the read bitline RBLT, which are positioned in the second interconnection layer, are arranged in parallel in accordance with the design rules. In each memory cell200A, the diffusion layers53,54and the word line WL, which are disposed to intersect with the diffusion layers53and54, form the NMOS transistors51and52, and the word line WL is disposed to extend in the perpendicular direction to the write bitlines BL1and BL2. The drain of the NMOS transistor51is connected to the magnetization fixed layer11via the via-contact63, the metal interconnection71and the via-contact83, and the drain of the NMOS transistor52is connected to the magnetization fixed layer12via the via-contact64, the metal interconnection72and the via-contact84. The source of the NMOS transistor51, on the other hand, is connected to a metal interconnection73via a via-contact93and the metal interconnection73is connected to the write bitline BL1via a via-contact85. Furthermore, the source of the NMOS transistor52is connected to a metal interconnection74via a via-contact94and the metal interconnection74is connected to the write bitline BL2via a via-contact86. It should be noted that the metal interconnections73and74are disposed in the first interconnection layer. The magnetic recording layer2is disposed at certain distances from the memory cell boundary and the via-contacts93and94, in accordance with the design rules. The tunnel barrier film31is disposed on the upper face of the magnetic recording layer2and the reference layer41is disposed on the upper face of the tunnel barrier film31. The reference layer41is connected to the read bitline RBLT via the via-contact81. The read bitline RBLB positioned in the first interconnection layer is arranged at the same coordinates as the read bitline RBLT positioned in the second interconnection layer. The tunnel barrier film32is disposed on the bottom face of the magnetic recording layer2and the reference layer42is disposed on the bottom face of the tunnel barrier film32. The reference layer42is connected to the read bitline RBLB via the via-contact82.

The magnetic random access memory of the second embodiment operates in the same way as that of the first embodiment, and effectively enlarges the read margin as is the case with the first embodiment. Additionally, the MRAM structure of the second embodiment, in which the reference layer41overlaps the reference layer42, allows reducing the distance between the magnetization fixed layers11and12compared to the first embodiment, and thereby effectively reduces the area of the memory cell. Also, the MRAM structure of the second embodiment effectively avoids occurrence of the state in which data stored in the memory cell200A is indefinite; in the first embodiment, data stored in the memory cell200may be indefinite when the magnetic domain wall is positioned between the reference layers41and42. This advantageously improves the operation reliability. Furthermore, the MRAM structure of the second embodiment advantageously shortens the write time due to the short moving distance of the magnetic domain wall.

Third Embodiment

FIG. 13is a layout diagram showing the layout of memory cells200B of a magnetic random access memory of a third embodiment. In the third embodiment, notches131and132are provided for the magnetic recording layer2. The notches131are positioned between the magnetization fixed layer11and the reference layer41and the notches132are positioned between the reference layer42and the magnetization fixed layer12. The notches131and132function as pin potentials for the magnetic domain wall. Accordingly, the notches131and132make it easy to control the position of the magnetic domain wall in the magnetic recording layer2, effectively improving the reliability of the data writing.

Fourth Embodiment

FIG. 14is a layout diagram showing an exemplary layout of memory cells200C of an MRAM of a fourth embodiment. In the layout of the fourth embodiment shown inFIG. 14, the width W of the diffusion layers53and54are increased, compared to the layout shown inFIG. 7. More specifically, the diffusion layer53is disposed so as to at least reach the region under the read bitline RBLT from the via-contact91which connects the write bitline BL1and the diffusion layer53, and the diffusion layer54is disposed so as to at least reach the region under the read bitline RBLB from the via-contact92which connects the write bitline BL2and the diffusion layer54. In the layout shown inFIG. 14, the diffusion layers53and54are disposed to reach the region between the read bitlines RBLB and RBLT.

The increase in the channel widths (gate widths) of the NMOS transistors51and52enables flowing a large write current, and effectively reduces the length of time necessary for completing the data write. In order to generate a large write current, it is preferable that the spacing between the diffusion layers53and54is adjusted to the minimum dimension allowed in the design rules used for manufacturing the MRAM. This allows maximizing the channel widths of the NMOS transistors51and52.

Although various embodiments are described above, the present invention should not be interpreted as being limited to the above-describe embodiments. The present invention may be implemented with various modifications which are obvious to the person skilled in the art. It should be also noted that two or more of the above-described embodiments may be combined if there is no technical inconsistency. For example, the layouts of the magnetic random access memories of the third and fourth embodiments are applicable to the magnetic random access memories of other embodiments.