Application processor sharing resource based on image resolution and devices including same

An application processor includes a first scaler including a first vertical scaler and a first horizontal scaler, and a second scaler including a second vertical scaler and a second horizontal scaler, wherein the second vertical scaler is selectively shared between the first scaler and the second scaler in response to a determination of resolution for an image being processed.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119(a) from Korean Patent Application No. 10-2014-0135086 filed on Oct. 7, 2014, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Embodiments of the inventive concept relate to integrated circuits, and more particularly to application processors capable of sharing a resource based on an image resolution. Other embodiments of the inventive concept relate to devices including such application processors.

Many contemporary displays are capable of displaying images in more than one resolution. The possibility of receiving image data defined according to different resolutions places increased processing burdens upon processors in image processing systems. The size of image data is a function of resolution, and as resolutions have become greater, the performance and bandwidth provided by a display have become increasingly important. Greater resolution of the constituent display increases power consumption. In order to reduce the power consumption, the use of memory-to-memory transfer operations has increased.

In order to scale-down an image through an on-the fly operation, a competent scaler must read a large amount of data at a fixed data rate from memory, and then scale (up or down) the data. A scale-down ratio for the scaler may be restricted based on internal throughput of a scaler. When the internal throughput of a scaler is increased to increase the scale-down ratio, the resulting layout area of the scaler is increased. Accordingly, manufacturing costs associated with the scaler and/or an application processor incorporating the scaler are increased.

SUMMARY

In one embodiment, the inventive concepts provides an application processor including; a first scaler including a first vertical scaler and a first horizontal scaler; and a second scaler including a second vertical scaler and a second horizontal scaler, wherein the second vertical scaler is shared between the first scaler and the second scaler.

In another embodiment, the inventive concepts provides a system on chip including; an image source that provides images including a first image, a second image, and a third image, each having one of a plurality of image types including a first image type and a second image type, a first scaler including a first vertical scaler and a first horizontal scaler, and a second scaler including a second vertical scaler and a second horizontal scaler, wherein upon determining that the first image and the second image are respectively first image type, the first vertical scaler vertically scales a first group of pixels corresponding to the first image, and in parallel, the second vertical scaler vertically scales a second group of pixels corresponding to the second image, and upon determining that the third image is second type, the first vertical scaler together with the second vertical scaler vertically scale a third group of pixels corresponding to the third image.

In another embodiment, the inventive concepts provides a method of operating an image processing system including a processor including N direct memory access (DMA) controllers, a switch matrix, and M scalers, wherein each one of the M scalers includes a vertical scaler and a horizontal scaler, and ‘N’ and ‘M’ are natural numbers greater than two. The method includes; providing an image from an image source to the processor, determining an image type for the image based on resolution of the image, generating a selection signal in response to the determination of the image type, and configuring the switch matrix in response to the selection signal to selectively configured an arrangement of DMA controllers and scalers to process an image, wherein upon determining that the image is first image type, the arrangement of DMA controllers and scalers includes Q DMA controllers, Q vertical scalers and Q horizontal scalers, ‘Q’ being a natural number less than N and M, and upon determining that the image is second image type, the arrangement of DMA controllers and scalers includes R DMA controllers, P vertical scalers and R horizontal scalers, where ‘R’ is a natural number less than Q, and ‘P’ is a natural number greater than R.

DETAILED DESCRIPTION

The inventive concept will now be described in some additional detail with reference to the accompanying drawings in which embodiments of the inventive concept are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to only the illustrated embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Throughout the written description and drawings, like reference numbers and labels are used to denote like or similar elements.

FIG. 1is a block diagram illustrating an image processing system according to an embodiment of the inventive concept. Referring toFIG. 1, an image processing system100generally comprises a processing circuit110and a memory112. The image processing system100may be a personal computer (PC), a desktop computer, a laptop computer, a workstation computer, or a portable (or mobile) computing device, where the portable computing device may be embodied as a mobile phone, a smart phone, a tablet PC, a mobile internet device (MID), a multimedia device, a digital camera, a camcorder, or a wearable computer.

The processing circuit110may be embodied as an integrated circuit (IC), a system on chip (SoC), an application processor (AP), or a mobile AP. The processing circuit110illustrated inFIG. 1generally includes a processor120and a system memory122. However, in certain embodiments of the inventive concept, the processing circuit110will further include a modem124. Here, the processor120may be embodied as an IC, an AP, or a mobile AP. Data received via the modem124may be stored in the system memory122under the control of a controller240. In the description that follows, the data stored in the system memory122is assumed to include image data sets corresponding to images IM1, IM2, and IM3.

The processor120may include multiple DMA controllers, such as DMA controllers130-1and130-2, as well as a first scaler132-1, a second scaler132-2, a selection circuit134, and a selection signal generation circuit136. The first DMA controller130-1may be used to read a first image IM1having a first resolution, or a third image IM3having a second resolution different from (e.g., greater than) the first resolution from the system memory122. After reading of the first image IM1or third image IM3, the first DMA controller130-1transfers the first image IM1or the third image IM3to the selection circuit134. For example, the first image IM1may be a high-definition (HD) image, and the third image IM3may be an ultra-high definition (UHD) image, however the scope of the inventive concept is not limited to only this image resolution relationship.

In similar manner, the second DMA controller130-2may be used to read a second image IM2having the first resolution from the system memory122, and transfers the second image IM2to the selection circuit134. Thus, a single image frame may include the first image IM1and the second image IM2.

Although only two (2) DMA controllers130-1and130-2and two (2) scalers132-1and132-2are shown inFIG. 1, embodiments of the inventive concept may include any reasonable number of DMA controllers and scalers, where the number of DMA controllers used may be different from or the same as the number of the scalers.

The selection signal generation circuit136may be used to determine a type of each of the images IM1, IM2, and IM3based on the resolution of each of the images IM1, IM2, and IM3to be processed by the processor120, and in response to this determination, the selection signal generation circuit136will generate a corresponding selection signal SEL. Each of the images IM1, IM2, and IM3may be scaled (e.g., scaled-down or scaled-up) by each of the scalers132-1and132-2on the fly.

A “first type image” may be determined when an image (e.g., either one of images IM1and IM2) has the first resolution, while a “second type image” may be determined when an image (e.g., image IM3) has the second resolution. In this regard, more than two (2) image resolutions may be determined by the selection signal generation circuit136as more than two (2) corresponding image types. The selection signal generation circuit136may determine an image type based on resolution of the image transferred from an “image source”, such as the memory112, system memory122, and/or modem124, and generate a selection signal SEL corresponding to the determination result. In certain embodiments of the inventive concept including a camera, for example, the camera may be the image source providing images.

The memory112shown inFIG. 1may be embodied as a hard disk drive (HDD), a solid state drive (SSD), a secure digital (SD) card, a multimedia card (MMC), an embedded MMC (eMMC), a universal serial bus (USB) flash drive, or a universal flash storage (USF). In certain embodiments of the inventive concept, the memory112will be a removable memory.

The system memory122may be embodied as a random access memory (RAM), a dynamic RAM (DRAM), a static RAM (SRAM), a flash memory, a phase change RAM (PRAM), a resistive RAM (RRAM), and/or a spin-transfer torque random-access memory (STT-MRAM).

The selection signal generation circuit136illustrated inFIG. 1includes the controller240, a Central Processing Unit (CPU)242, and a selection signal generator244. Here, the controller240may be used to determine the image type based on the resolution of the image to be processed by the processor120, and transfer “image type information” corresponding to a determination result generated by the CPU242. In turn, the CPU242transfers “selection information” to the selection signal generator244based on the image type information. In certain embodiments, the selection signal generator244may be embodied as a register (e.g., a special function register—SFR) storing data associated with the selection information, and in such cases, the register may be used to generate the selection signal SEL based on the selection information provided by the CPU242.

Additionally, the CPU242may be used to control the operation (e.g., enabling/disabling) of the DMA controllers130-1and130-2based on the image type information generated by the controller240. An enabled DMA controller may read or fetch image data (or pixels) corresponding to each one of the images IM1, IM2, and IM3, as stored in the system memory122and under the control of the CPU242. For example, extending the working example illustrated inFIG. 1, when an image generated using the first resolution is to be processed by the processor120, the selection signal generation circuit136may output a selection signal SEL having a first level (e.g., a logically low level, or bit value of ‘0’) to the selection circuit134. However, when an image generated using the second resolution is to be processed by the processor120, the selection signal generation circuit136may output a selection signal SEL having a second level (e.g., a logically high level, or a bit value of ‘1’) to the selection circuit134.

InFIG. 1, the selection circuit134includes a first selector230, a second selector232, a third selector234, a fourth selector236, and a distributor231. In the illustrated embodiment ofFIG. 1, the first, second and third selectors230,232, and234are embodied as multiplexers, and the fourth selector236is embodied as a de-multiplexer.

FIG. 2is a block diagram describing the operation of the scalers shown inFIG. 1that scale images having the first resolution. When the selection signal generation circuit136is assumed to output a low selection signal SEL, the operation of the first and second scalers132-1and132-2may be understood from the following description in conjunction withFIGS. 1 and 2.

When an image to be processed by the processor120has the first resolution, each of the DMA controllers130-1and130-2is enabled by the CPU242. Moreover, it is assumed that each of the DMA controllers130-1and130-2includes a memory (or buffer) capable of storing pixels included in one or more lines of each of the images IM1and IM2, so as to reduce a read access frequency with respect to the system memory122.

The first DMA controller130-1is connected to a first vertical scaler210through the first selector230, while the second DMA controller130-2is connected to a second vertical scaler220through the second selector232. Here, the first vertical scaler210is connected to a first horizontal scaler214through the third selector234, and the second vertical scaler220is connected to a second horizontal scaler224through the fourth selector236.

The first horizontal scaler214has the largest pixel throughput among the first vertical scaler210, the first horizontal scaler214, the second vertical scaler220, and the second horizontal scaler224, where “pixel throughput” is defined by a number of pixels processed per clock period.

Thus, the first horizontal scaler214will be designed to maximize pixel throughput, while the second vertical scaler220among the remaining scalers210,220, and224will be designed for use with the first scaler132-1based on the resolution of an image to be scaled. Accordingly, the processor120or the processing circuit110according to embodiments of the inventive concept may efficiently adjust a number of resources (e.g., scalers) based on the resolution of the image to-be-scaled.

The first DMA controller130-1may read (or fetch) the first image IM1having first resolution from the system memory122, and transfer the fetched first image IM1to the first vertical scaler210through the first selector230. In parallel with this operation of the first DMA controller130-1, the second DMA controller130-2may fetch the second image IM2having first resolution from the system memory122, and transfer the fetched second image IM2to the second vertical scaler220through the second selector232. At this time, the first image IM1and the second image IM2may compose one frame, where each of the first and second images IM1and IM2include a plurality of pixels. In this context, “pixels” may be understood as image data having a particular format (e.g., RGB format, YCbCr format or YUV format). Further, the plurality of pixels may be understood as being arranged in the set image data corresponding to an image in a plurality of lines.

With continued reference toFIGS. 1 and 2, the first vertical scaler210may store pixels included in the first image IM1transferred from the first DMA controller130-1in a first line memory212, perform vertical scaling on the pixels stored in the first line memory212, and transmit vertically scaled pixels to the first horizontal scaler214through the third selector234. In parallel with the operation of the first vertical scaler210, the second vertical scaler220may store pixels included in the second image IM2transferred from the second DMA controller130-2in a second line memory222, perform vertical scaling on the pixels stored in the second line memory222, and transmit vertically scaled pixels to the second horizontal scaler224through the fourth selector236.

The first horizontal scaler214may perform horizontal scaling on the vertically scaled pixels received through the third selector234, and output the resulting horizontally scaled pixels SIM11. In parallel with the operation of the first horizontal scaler214, the second horizontal scaler224may perform horizontal scaling on the vertically scaled pixels received through the fourth selector236, and output the resulting horizontally scaled pixels SIM12.

As described above, when the selection signal generation circuit136generates a first level (low) selection signal SEL each of the scalers132-1and132-2may, independently, vertically and horizontally scale pixels corresponding to the first and second images IM1and IM2in order to generate vertically and horizontally scaled pixels SIM11and SIM12. Each of the scalers132-1and132-2may perform a scale-up (or up-scale) operation or a scale-down (down-scale) operation.

FIG. 3is a block diagram describing operation of the scalers shown inFIG. 1that scale an image having the second resolution, greater than the first resolution.FIG. 4is a conceptual diagram further describing the operation of the vertical scalers shown inFIG. 1. When it is assumed that the selection signal generation circuit136outputs a high selection signal SEL, operation of the salers132-1and132-2may be understood from the following description taken in conjunction withFIGS. 1, 3, and 4. When resolution of an image to be processed by the processor120is the second resolution, only the first DMA controller130-1is enabled by the CPU242.

An output terminal of the first DMA controller130-1is connected to an input terminal (0) of the first selector230and an input terminal of the distributor231. The distributor231may transfer a first group of pixels among the pixels output by the first DMA controller130-1to an input terminal (1) of the first selector230, and transfer a second group of pixels among the pixels output by the first DMA controller130-1to an input terminal (1) of the second selector232under the control of the CPU242.

An output terminal of the first vertical scaler210is connected to an input terminal (0) of the third selector234and an input terminal of a merger233. The merger233may be used to merge (or combine) pixels output from the first vertical scaler210and pixels output from the fourth selector236, and output the merged pixels to the third selector234under the control of the CPU242.

The second selector232may isolate or separate the second vertical scaler220from the second DMA controller130-2and connect the distributor231and the second vertical scaler220according to the high (second level) selection signal SEL. Accordingly, the first scaler132-1may additionally use the second vertical scaler220. Based on resolution of an image to be processed by the processor120, the second vertical scaler220may be used by the first scaler132-1, or may be used by the second scaler132-2. That is, the second vertical scaler220has a configuration that enables its operational capabilities to be shared as a resource between the first scaler132-1and the second scaler132-2.

As noted above, it is assumed that the first DMA controller130-1includes a memory (or buffer) which can store pixels included in one or more lines included in an image IM1or IM3so as to reduce a read access frequency with respect to the system memory122. Moreover, for convenience of description, it is assumed that the number of pixels included in each line is four. Each pixel may include RGB data or YCbCR (YUV) data.

From the foregoing description ofFIGS. 1, 2 and 3, it will be understood that the selection signal SEL—based on the resolution of an image to be processed—may be used to essentially select an operating mode for the selection circuit134. For example, in a first operating mode selected by a low selection signal, the selection circuit134will operate as described in relation toFIG. 2, but in a second operating mode selected by a high selection signal, the selection circuit134will operate as described in relation toFIG. 3.

As shown inFIG. 4, it is assumed that the first DMA controller130-1reads pixels P11, P12, P13, and P14of a kthline and pixels P21, P22, P23, and P24of (k+1)thline, and store pixels P11, P12, P13, P14, P21, P22, P23, and P24in an internal memory (or buffer) of the first DMA controller130-1. When a first (low) distribution signal DT1is generated, the first DMA controller130-1may transmit a first group P11and P13among the pixels P11, P12, P13, and P14of a kthline included in the third image IM3having second resolution to an input terminal (1) of the first selector230. The first selector230may transmit the first group P11and P13to the first vertical scaler210in response to the high selection signal SEL. The first vertical scaler210may stores the first group P11and P13transmitted through the first selector230in the first line memory212.

When a second (high) distribution signal DT2is generated, the first DMA controller130-1may transmit a second group P12and P14among the pixels P11, P12, P13, and P14of a kthline included in the third image IM3having second resolution to an input terminal (1) of the second selector232. The second selector232may transmit the second group P12and P14to the second vertical scaler220in response to the high selection signal SEL. The second vertical scaler220may store the second group P12and P14transferred by the second selector232in a second line memory222.

When the first distribution signal DT1is high, the first DMA controller130-1may transmit a first group P21and P23among the pixels P21, P22, P23, and P24of a (k+1)thline included in the third image IM3having second resolution to an input terminal (1) of the first selector230. The first selector230may transmit the first group P21and P23to the first vertical scaler210in response to the high selection signal SEL. The first vertical scaler210may store the first group P21and P23transferred by the first selector230in the first line memory212.

When the second distribution signal DT2is high, the first DMA controller130-1may transmit a second group P22and P24among the pixels P21, P22, P23, and P24of a (k+1)thline included in the third image IM3having second resolution to an input terminal (1) of the second selector232. The second selector232may transmit the second group P22and P24to the second vertical scaler220in response to the high selection signal SEL. The second vertical scaler220may store the second group P22and P24transferred by the second selector232in the second line memory222.

As described referring toFIG. 4, odd numbered pixels P11and P13among the pixels P11, P12, P13, and P14of a kthline may be sequentially stored in the first line memory212by a control of the first vertical scaler210, and even numbered pixels P12and P14among the pixels P11, P12, P13, and P14of a kthline may be sequentially stored in the second line memory222by a control of the second vertical scaler220. Moreover, odd numbered pixels P21and P23among the pixels P21, P22, P23, and P24of a (k+1)thline may be sequentially stored in the first line memory212by a control of the first vertical scaler210, and even numbered pixels P22and P24among the pixels P21, P22, P23, and P24of a (k+1)thline may be sequentially stored in the second line memory222by a control of the second vertical scaler220.

Thus, the first vertical scaler210performs vertical scaling on a first group of pixels P11, P13, P21, and P23stored in the first line memory212on a column basis. In parallel with the operation of the first vertical scaler210, the second vertical scaler220performs vertical scaling on a second group of pixels P12, P14, P22, and P24stored in the second line memory222on a column basis. For example, the first vertical scaler210may perform vertical scaling on pixels P11and P21, and P13and P23, and generate vertically scaled pixels A and B. Moreover, the second vertical scaler220vertically scales pixels P12and P22, and P14and P24, and generate vertically scaled pixels C and D. A method of generating average values of corresponding pixels is shown inFIG. 4as a method of generating vertically scaled pixels A, B, C, and D—however, this is just a selected example of how the illustrated embodiment may be operated. Other approaches, such as using an interpolation method, may be used to generate the vertically scaled pixels A, B, C, and D. The fourth selector236may transmit pixels C and D output from the second vertical scaler220to the merger233in response to the high selection signal SEL.

The merger233may now be used to merge vertically scaled pixels A and B provided by the first vertical scaler210with vertically scaled pixels C and D provided by the second vertical scaler220. The merged pixels ABCD are provided to an input terminal (1) of the third selector234under the control of the CPU240. Accordingly, the third selector234may transmit the merged pixels ABCD to the first horizontal scaler214in response to the high selection signal SEL. Thereafter, the first horizontal scaler214may horizontally scale the merged pixels ABCD, that is, the vertically scaled pixels ABCD are output as horizontally scaled pixels SIM21.

FIG. 5is a block diagram of an image processing system according to another embodiment of the inventive concept. Referring to the foregoing embodiments andFIG. 5, an image processing system100B includes; a processor310, a system memory312, and a display314. The image processing system100B may be embodied as a PC, a desktop computer, a laptop computer, a workstation computer, or a portable (or mobile) computing device.

The processor310includes a plurality of ‘n’ DMA controllers130-1to130-n, where n is a natural number greater than 2, the selection signal generation circuit136, a switch matrix320, a plurality of ‘m’ scalers330-1to330-m, where m is a natural number greater than 1, and a blender340.

The configuration and operation of each of the plurality of DMA controllers130-1to130-nmay be substantially the same as the configuration and operation of the DMA controller130-1previously described in relation toFIG. 1.

Based on resolution of an image to be processed by the processor310, the selection signal generation circuit136determines the image type, generates selection signal(s) corresponding to the image type determination, and transmits the selection signal(s) to the switch matrix320and the plurality of scalers330-1to330-m. Here, the selection signal(s) may be variously defined and may one or more selection signals.

The switch matrix320transmit pixels output from at least one of the plurality of DMA controllers130-1to130-nto at least one scaler of a plurality of scalers330-1to330-m, or the blender340in response to the selection signal(s). For example, when pixels output by at least one of the plurality of DMA controllers130-1to130-nare user interfaces (UIs), the switch matrix320may directly transmit pixels corresponding to the UI to the blender340based on the selection signal(s).

Each of the plurality of scalers330-1to330-mmay include the first scaler132-1, second scaler132-2, and selection circuit134ofFIG. 1. Accordingly, the configuration and operation of elements132-1,132-2, and134included in each of the plurality of scalers330-1to330-mmay be substantially the same as or similar to the configuration and operation of elements132-1,132-2, and134described with reference toFIGS. 1, 2, 3and/or4.

The blender240receives pixels output from the switch matrix320, and vertically and horizontally scaled pixels output from at least one of the plurality of scalers330-1to330-m, blends the received pixels, and transmits display data (blended pixels) to the display314. For example, the display data may be transferred to a display314via a MIPI® display serial interface (DSI).

FIG. 6is a flowchart summarizing operation of an image processing system consistent with certain embodiments of the inventive concept, like those shown inFIGS. 1, 2, 3, 4 and/or 5. Referring to the foregoing embodiments andFIG. 6, the controller240may be used to determine a type of an image based on resolution of the image to be processed by the processor120or310(S110). The selection signal generation circuit136may be used to generate a selection signal SEL corresponding to a determined image type (S112).

When resolution of an image to be processed by the processor120is the second resolution, and the selection signal SEL may be high (e.g., waveform shown inFIG. 3) (S114), the first vertical scaler210of the first scaler132-1vertically scales pixels stored in the first line memory212, and the second vertical scaler220shared by the first scaler132-1and the second scaler132-2vertically scales pixels stored in the second line memory222(S116).

The first horizontal scaler214may receive the pixels vertically scaled by the first vertical scaler210and the pixels vertically scaled by the second vertical scaler220, and horizontally scales the received pixels (S118). At this time, the pixels vertically scaled by the second vertical scaler220are not transmitted to the second horizontal scaler224according to an operation of the fourth selector236.

However, when resolution of an image to be processed by the processor120is the first resolution, and the selection signal SEL may be low (e.g., waveform shown inFIG. 2) (S114), the first scaler132-1may vertically and horizontally scale a first image IM1, and generate the vertically and horizontally scaled image SIM11using the first vertical scaler210and the first horizontal scaler214as described with reference toFIG. 2(S120).

In parallel (or simultaneously, meaning overlapping at least in part) with an operation of the scaler132-1, the second scaler132-2may vertically and horizontally scale a second image IM2, and generate vertically and horizontally scaled image SIM12using the second vertical scaler220and the second horizontal scaler224, and generate the vertically and horizontally scaled image SIM12(S120).

FIG. 7is a block diagram of an image processing system according to still another embodiment of the inventive concept. Referring toFIG. 7, an image processing system100-1generally includes a processing circuit110and a memory112. The image processing system100-1may be a PC, a desktop computer, a laptop computer, a workstation computer, or a portable (or mobile) computing device.

The processing circuit110may be embodied as an integrated circuit (IC), a system on chip (SoC), an application processor (AP), or a mobile AP. The processor120may include the DMA controllers130-1and130-2, the first scaler132-1, the second scaler132-2, the selection circuit134, and the selection signal generation circuit136.

Except that an input terminal of the first horizontal scaler214is connected to an output terminal of the first DMA controller130-1, and an input terminal of the second horizontal scaler224is connected to an output terminal of the second DMA controller130-2, the configuration and operation of the image processing system100-1shown inFIG. 7are substantially the same as or similar to the configuration and operation of the image processing system100shown inFIG. 1.

The first horizontal scaler214may horizontally scale pixels included in image IM1or IM3output from the first DMA controller130-1and output horizontally scaled pixels to an input terminal (0) of the first selection circuit230and an input terminal of the distributor231. The second horizontal scaler224may horizontally scale pixels included in an image IM2output from the second DMA controller130-2, and output horizontally scaled pixels to an input terminal (0) of the second selection circuit232.

FIG. 8is a block diagram describing operation of the scalers shown inFIG. 7that scale images each having the first resolution. When the selection signal generation circuit136is low (first level), the operation of the scalers132-1and132-2may be understood from the following description with reference toFIGS. 7 and 8. When resolution of an image to be processed by the processor120is the first resolution, it is assumed that each of the DMA controllers130-1and130-2is enabled under the control of the CPU242.

The first horizontal scaler214is connected to the first vertical scaler210through the first selector230, and the second horizontal scaler224is connected to the second vertical scaler220through the second selector232. The first horizontal scaler214may horizontally scale pixels included in the first image IM1having first resolution, which are output from the first DMA controller130-1, and transmit horizontally scaled pixels HS1to the first vertical scaler210. In parallel with the operation of the first horizontal scaler214, the second horizontal scaler224may horizontally scale pixels included in the second image IM2having first resolution, which are output from the second DMA controller130-2, and transmit horizontally scaled pixels HS2to the second vertical scaler220.

The first vertical scaler210may store horizontally scaled pixels HS1to the first line memory212, vertically scale pixels stored in the first line memory212, and output vertically scaled pixels VS1through the third selector234. In parallel with an operation of the first vertical scaler210, the second vertical scaler220may store horizontally scaled pixels HS2in the second line memory222, vertically scale pixels stored in the second line memory222, and output vertically scaled pixels VS2through the fourth selector236.

FIG. 9is a block diagram describing operation of the scalers shown inFIG. 7that scale an image having the second resolution greater than the first resolution. When the selection signal generation circuit136is high (second level), the operation of the scalers132-1and132-2may be understood from the following description with reference toFIGS. 4, 7, and 9.

When resolution of an image to be processed by the processor120is the second resolution, it is assumed that only the first DMA controller130-1is enabled by the CPU242. The first horizontal scaler214may horizontally scale pixels included in the third image IM3having second resolution, which are output from the first DMA controller130-1, and transmit horizontally scaled pixels HS1to an input terminal (0) of the first selector230and an input terminal of the distributor231.

The distributor231may transmit a first group of pixels of the horizontally scaled pixels HS1to an input terminal (1) of the first selector230, and transmit a second group of pixels of the pixels to an input terminal (1) of the second selector232under the control of the CPU242. An output terminal of the first vertical scaler210is connected to an input terminal (0) of the third selector234and an input terminal of the merger233. The merger233may be used to merge pixels output from the first vertical scaler210with pixels output from the fourth selector236, and output the merged pixels to the third selector234under the control of the CPU242.

FIG. 10is a block diagram of an image processing system according to still another embodiment of the inventive concept. Referring toFIGS. 1 and 10, except that each of selectors230′,232′,234′, and236′ includes a plurality of selectors and each of vertical scalers210′ and220′ includes a plurality of scalers, the configuration and operation of the data processing system100-2shown inFIG. 10are substantially the same as or similar to the configuration and operation of the data processing system100shown inFIG. 1.

FIG. 11, inclusive ofFIGS. 11A and 11B, is a conceptual diagram describing pixel processing in response to a clock signal. Referring toFIGS. 10 and 11A, it is assumed that a first vertical scaler210′ includes four scalers, the first selector230′ includes four selectors, a second vertical scaler220′ includes four scalers, the second selector232′ includes four selectors, a third selector234′ includes four selectors, each of the horizontal scalers214and224includes one horizontal scaler, each of the vertical scalers210′ and220′ vertically scales one pixel per clock signal, the first horizontal scaler214horizontally scales four pixels per the clock signal, and the second horizontal scaler224horizontally scales one pixel, two pixels, or four pixels per the clock signal.

Operation of a first scaler132-1, first selectors230′, and third selectors234′ are as follows. The distributor231may transmit a corresponding pixel of four pixels P1to P4to a corresponding selector of four selectors230′.

A corresponding pixel of four pixels P1to P4may be transmitted to a corresponding vertical scaler of four vertical scalers210′ through a corresponding selector of four selectors230′. Moreover, the distributor231may transmit a corresponding pixel of four pixels P5to P8to a corresponding selector of four selectors230′. A corresponding pixel of four pixels may be transmitted to a corresponding vertical scaler of four vertical scalers210′ through a corresponding selector of four selectors230′.

Operation of the second scaler132-2, second selectors232′, and fourth selectors236′ are substantially the same as or similar to the operation of the first scaler132-1, the first selectors230′, and the third selectors234′.

Referring toFIGS. 10 and 11B, it is assumed that the first vertical scaler210′ includes four scalers, the first selector230′ includes four selectors, the second vertical scaler220′ includes four scalers, the second selector232′ includes four selectors, the third selector234′ includes four selectors, each of the horizontal scalers214and224includes one horizontal scaler, each of the vertical scalers210′ and220′ vertically scales two pixels per clock signal, the first horizontal scaler214horizontally scales four pixels per the clock signal, and the second horizontal scaler224horizontally scales one pixel, two pixels, or four pixels per the clock signal.

Operation of the first scaler132-1, the first selectors230′, and the third selectors234′ are as follows. A pair of corresponding pixels P1and P2, P3and P4, P5and P6, and P7and P8among eight pixels P1to P8are transferred to a corresponding vertical scaler among four vertical scalers210′ through a corresponding selector among four selectors230′. That is, a corresponding vertical scaler among four vertical scalers210′ vertically scales pixels in a pair VS1, VS2, VS3, and VS4.

Operation of the second scaler132-2, the second selectors232′, and the fourth selectors236′ are substantially the same as or similar to operations of the first scaler132-1, the first selectors230′, and the third selector234′.

As described above, the distributor231may transmit one or more pixels to a corresponding selector among a plurality of first selectors230′ or a corresponding selector among a plurality of second selectors232′. The merger233may merge at least one pixel output from a corresponding vertical scaler among a plurality of first vertical scalers210′ and at least one pixel output from a corresponding selector among a plurality of four selectors236′.

In an application processor including scalers according to embodiments of the inventive concepts, some of the scaler(s) may be shared as resource(s) based on the resolution of the image being processed. Thus, an application processor including scalers according to embodiments of the inventive concepts are able to reduce power consumption, and yet still scale an image on-the-fly using parallel processing.

Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the scope of the following claims and their equivalents.