Trench MOSFET with trench termination and manufacture thereof

A trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a trench termination, including a substrate including a drain region which is strongly doped and a doping epi layer region, which is weekly doped the same type as the drain region, on the drain region; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body, and gate regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; a plurality of gate trenches filled with polysilicon to form a plurality of trenched gates on top of epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; a margin terminating gate trench which is around the gate trenches; and a margin terminating active region which is formed underneath the margin terminating gate trench.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a trenched MOSFET structure with a trench termination and the method for manufacturing thereof, and more particularly to a structure of a trenched MOSFET which is suitable for high cell density and can improve the device ruggedness.

2. The Prior Arts

In the structure of a trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) or vertical transistor, the gate of the transistor is formed in a trench on top of a substrate and the source/drain regions are formed on both sides of the gate. This type of vertical transistor allows high current to pass through and channel to be turned on/off at a low voltage.

Referring toFIG. 1, a cross-sectional diagram of the structure of a trenched MOSFET is shown. In the prior art, the trench MOSFET has a MOSFET structure comprises a drain region101, a N-type doping epi layer region102, a plurality of gate trenches103, a margin terminating gate trench104, a gate oxide layer105, a plurality of channel regions106, a plurality of source regions108, a insulating layer110, a plurality of contact plugs112, and a metal layer113. The metal layer113is formed on the top of the MOSFET structure for the source metal and the gate and field plate metal of the MOSFET. The gate trenches103are covered the gate oxide layer105and are defined as the gate of the MOSFET. The insulating layer110is formed between the metal layer113and the gate trenches103for insulating, and the contact plugs112are penetrated through the insulating layer110and contacted with the metal layer113.

In the related prior arts, the device structure is achieved with P body formation prior to trench etch, which is not suitable for high cell density with pitch smaller than 2.4 μm. When cell density increases, more trench openings, causes more boron segregation in P body from channel region near by trench during Sacrificial and gate oxidations, resulting in serious punch-through issue. Besides, separation of gate and field plate metal makes longer termination.

The present invention provides a new structure of trenched MOSFET structure with a trench termination around the contacted trenched gate which improves the lack of the prior art.

SUMMARY OF THE INVENTION

This invention provides a trenched MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a trench termination comprising a substrate comprising a drain region which is strongly doped and a doping epi layer region, which is weekly doped the same type as the drain region, on the drain region; a plurality of source and body regions formed in the epi layer; a metal layer comprising a plurality of metal layer regions which are connected to respective source and body, and gate regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; a plurality of gate trenches filled with polysilicon to form a plurality of trenched gates on top of epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; a margin terminating gate trench which is around the gate trenches; and a margin terminating active region which is formed underneath the margin terminating gate trench.

Besides, a method for manufacturing the said trench MOSFET of the present invention comprising the steps, providing an epi layer on heavily doped substrate, forming a plurality of trenches in the epi layer, covering a gate oxide layer on the sidewalls and bottom of the trenches, forming a conductive layer in the trenches to be used as the gate of MOSFET, forming a plurality of channel regions and source regions according to active regions of the trench MOSFET in the epi layer, and a plurality of channel regions and source regions according to termination regions of the trench MOSFET in the epi layer; forming an insulating layer on the epi layer, forming a plurality of contact openings in the insulating layer and the source and body regions, and forming metal contact plugs in the contact openings to directly contact with both source and body regions, and a metal layer on the insulating layer.

The present invention has some advantages. One is feasible for high cell density with pitch smaller than 2.4 μm while the P body is formed after trench formation and no Boron segregation issue which is feasible for higher cell density (cell pitch is less than 2.4 μm) to reduce On-resistance and the P body is formed in termination area also without impacting breakdown voltage. Another is that no N+ near edge of active area and termination area to improve device ruggedness since these areas near by trench gate, and easily trigger on parasitic bipolars if there exists.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The present invention is described by the following specific embodiments. Those with ordinary skills in the arts can readily understand the other advantages and functions of the present invention after reading the disclosure of this specification. The present invention can also be implemented with different embodiments. Various details described in this specification can be modified based on different viewpoints and applications without departing from the scope of the present invention.

Referring toFIG. 2A, a substrate200comprises a drain region201which is strongly n-doped, and the drain region201which is weekly n-doped haves a N-type doping epi layer region202thereon. A first mask is applied, and Lithography and dry etching processes are performed to form a plurality of gate trenches203and a margin terminating gate trench204in the N-type doping epi layer region202. The trenches203comprise a first gate trench203aand a second gate trench203b, and the first gate trench203ais deeper and wider than all the second gate trenches203b. The margin terminating gate trench204is around the gate trenches203.

Referring toFIG. 2B, a deposition or thermally grown process is performed to form a silicon oxide layer on the surface of the N-type doping epi layer region202, the gate trenches203, and the margin terminating gate trench204, which acts as a gate oxide layer205of a trenched MOSFET. Prior to the gate oxide layer205is formed, a sacrificial oxide is grown and wet etched for removal silicon damage along the gate trench203and the margin terminating gate trench204surface induced by the dry trench etch. Thereafter, a doped polysilicon layer is formed on the gate oxide layer205and filled in the gate trenches203and the margin terminating gate trench204by a deposition process. The doped polysilicon layer on the gate oxide layer205is flated by a dry etching process or a CMP (chemical-mechanical polishing process) and the doped polysilicon layer on the gate trenches203and the margin terminating gate trench204are removed by a polysilicon etching back process, and a plurality of gate structures of the trenched MOSFET in the trench are formed.

Referring toFIG. 2C, a plurality of channel regions206and a margin terminating channel region207, which are p-doped layer, are formed in the N-type doping region205by an ion implantation and diffusion processes. The channel regions206are formed aside the gate trenches203, and the margin terminating channel region207is formed underneath the margin terminating gate trench204. Thereafter, a plurality of source region208and a margin terminating source region209, which are strongly n-doped layer, are respectively formed in the channel regions206and the margin terminating channel region207by an ion implantation and thermal diffusion processes and the active regions of the trenched MOSFET are completed. Besides, a second gate oxide layer205ais formed by a deposition or thermally grown process on the surface of the gate trenches203and the margin terminating gate trench204.

Referring toFIG. 2D, an insulating layer210is formed on the gate trench203, the margin terminating gate trench204, the gate oxide layer205and the second gate oxide layer205a. This insulating layer210is a silicon dioxide layer formed by a deposition process. Then, a second mask is applied to defined a etching region, and a plurality of contact plug holes211are formed by a dry etching process and the contact plug holes211are located at the active regions, the first gate trench203aand the margin terminating gate trench204corresponding to locations of metal contacts of the trenched MOSFET.

Referring toFIG. 2E, the contact plug holes211can be filled with tungsten metal to form a plurality of contact plugs212comprising a plurality of first contact plugs212awhich are corresponding to the active regions and a plurality of second contact plugs212bwhich are corresponding to the first gate trench203aand the margin terminating gate trench204. Besides tungsten metal, aluminum metal or copper metal is used as the contact plug or the front metal layer of the trenched MOSFET. After etch back of the contact plugs212, a third mask is applied to defined a region for metal connections of the trenched MOSFET. then, a metal layer213, a metal layer Ti/Aluminum alloys, is deposited on the insulating layer210and the contact plugs212, and the metal layer213comprises a first metal layer region213aand a second metal layer region213bwhich are separated and are metal connections of the trenched MOSFET. The first metal layer region213aconnects the first contact plugs212acorresponding to the first gate trench203aand the margin terminating gate trench204, and the second metal layer region213bconnects the first contact plug212acorresponding to the channel regions206and the source regions208which are defined the active regions of the trenched MOSFET.

Referring toFIG. 2Eshowed a first embodiment again, the trench MOSFET with a trench termination of the present invention has a MOSFET structure comprises the drain region201, the N-type doping epi layer region202, the gate trenches203, the margin terminating gate trench204, the gate oxide layer205, the channel regions206, the margin terminating channel region207, the source regions208, the margin terminating source region209, the insulating layer210, the contact plugs212, and the metal layer213. The metal layer213comprises the first metal layer region213aand the second metal layer region213bwhich are formed on the top of the MOSFET structure, and the first metal layer region213band the second metal layer region213aare formed as the source metal, and the gate and field plate metal of the MOSFET, respectively. The gate trenches203comprises the first gate trench203aand the second gate trench203bwhich are covered the gate oxide layer205and are defined as the gate of the MOSFET. The insulating layer210is formed between the metal layer213and the gate trenches203for insulating, and the contact plugs212are penetrated through the insulating layer210and contacted with the metal layer213. The margin terminating channel region207and the margin terminating source region209define an active region at the termination of the MOSFET structure, and the margin terminating gate trench204, the margin terminating channel region207, and margin terminating source region209avoid margin breakdown.

Although NMOS transistors are described in the first embodiment of the invention, it is obvious for those skilled in the same art can also refer to PMOS transistor, for an example, only the n-doped regions are substituted by p-doping and vice versa.

Referring toFIG. 3showed a second embodiment, the P-doped regions of the trench MOSFET with a trench termination of the present invention can be alternatively formed by a deposition process so that a margin terminating sidewall channel region207ais formed at a side of the margin terminating gate trench204. Besides, a margin terminating sidewall source region209ais also formed on the margin terminating sidewall channel region207aduring the source region process.

Referring toFIG. 4showed a third embodiment, the trench MOSFET with a trench termination of the present invention is similar to the first embodiment of the present invention. The second metal layer region213bis divided into two parts which are the gate runner and the field plate metal of the MOSFET respectively.

Referring toFIG. 5showed a fourth embodiment, the trench MOSFET with a trench termination of the present invention is similar to the second embodiment of the present invention. The second metal layer region213bis divided into two parts which are the gate runner and the field plate metal of the MOSFET respectively.

Although various embodiments are specifically illustrated and described herein, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and are within the purview of the appended claims without departing from the spirit and intended scope of the invention.