Electro-optical device and electronic apparatus

An electro-optical device includes a scan line, a data line, a pixel circuit provided to correspond to an intersection of the scan line and the data line, a low potential line, and a high potential line with a different potential from the low potential line. The pixel circuit includes a light emitting element, a memory circuit including a first transistor, a second transistor arranged between the memory circuit and the data line, and a third transistor. A source of the first transistor is electrically connected to the low potential line, and the light emitting element and the third transistor are arranged in series between a drain of the first transistor and the high potential line.

The present application is based on and claims priority from JP Application Serial Number 2017-185867, filed Sep. 27, 2017, the disclosure of which is hereby incorporated by reference herein in its entirety.

BACKGROUND

1. Technical Field

The disclosure relates an electro-optical device and an electronic apparatus.

2. Related Art

In recent years, head-mounted displays (HMDs), a type of electronic device that enables formation and viewing of a virtual image by directing image light from an electro-optical device to the pupil of an observer, have been proposed. One example of the electro-optical device used in these electronic devices is an organic electro-luminescence (EL) device that includes an organic EL element as a light-emitting element. The organic EL devices used in head-mounted displays are required to provide high resolution (fine pixels), multiple grey scales of display, and low power consumption.

In organic EL devices in prior art, when a selecting transistor turns to an ON-state according to a scan signal supplied to a scan line, an electrical potential based on an image signal supplied from a data line is held in a capacitive element connected to the gate of a driving transistor. When the driving transistor turns to an ON-state in response to the electrical potential maintained in the capacitive element, that is, the gate potential of the driving transistor, an electric current flows through the organic EL element depending on the gate potential of the driving transistor and thus the organic EL element emits light with luminance depending on the electric current.

In this way, the organic EL device in prior art displays a grey scale using an analog drive method that controls the current flowing through the organic EL element depending on the gate potential of the driving transistor. This causes problems of variation in brightness and grey scale shift among pixels because of variation in transfer characteristics and threshold voltage of the driving transistor, and thus reduces display quality. To address the above-described problems, it is conceivable to provide an organic EL device including a compensation circuit that compensates for variation in the transfer characteristics and threshold voltage of the driving transistor (for example, refer to JP-A-2004-062199).

However, when such a compensation circuit is provided as described in JP-A-2004-062199, a current also flows through the compensation circuit, thus increasing power consumption. Furthermore, in order to achieve multiple grey scales display, the analog driving approaches in prior art require a capacitive element with large capacitance to keep image signals. This requirement is incompatible with the requirements for high resolution that means fine pixels and may result in an increased power consumption due to charging and discharging of the capacitive element. In other words, in the related art, it may be difficult to achieve an electro-optical device that can display a high quality image having a high resolution and multiple grey scales at a low power consumption.

SUMMARY

The disclosure may be implemented as several exemplary embodiments or application examples provided below.

APPLICATION EXAMPLE 1

An electro-optical device according to Application Example 1 includes a scan line, a data line, a pixel circuit provided to correspond to an intersection of the scan line and the data line, a first potential line that supplies a first potential, and a second potential line that supplies a second potential, which is a different from the first potential. The pixel circuit includes a light emitting element, a memory circuit including a first transistor, a second transistor arranged between the memory circuit and the data line, and a third transistor. A source of the first transistor is electrically connected to the first potential line. The light emitting element and the third transistor are arranged in series between a drain of the first transistor and the second potential line.

According to the configuration of Application Example 1, each pixel circuit includes the memory circuit including the first transistor. The first transistor, the light emitting element, and the third transistor are arranged between the first potential line and the second potential line. This is a good configuration for a digital drive method for displaying multiple grey scales. The digital drive method uses binary states, i.e. ON- and OFF-states and controls the time ratio between emission and non-emission of the light emitting element. Accordingly, the electro-optical device becomes less susceptible to variation in transfer characteristics and threshold voltage of each transistor, such that variation in brightness and grey scale shift among pixels can be reduced without a compensation circuit. Furthermore, the digital drive method can readily increase the number of grey scales without any capacitive elements by increasing the number of sub-fields in a field during which a single image is displayed. A sub-field is a basic period for controlling emission and non-emission of the light emitting element. Thus, finer pixels and a higher resolution can be achieved. Also, the power consumption due to charging and discharging of the capacitive element can be reduced. As a result, an electro-optical device that can display a high-quality image with a high resolution and multiple grey scales at low power consumption can be achieved.

APPLICATION EXAMPLE 2

In the electro-optical device according to the application example described above, a drain of the third transistor and the light emitting element is electrically connected to each other.

According to the configuration of Application Example 2, when the third transistor is in an OFF-state, a current does not flow through the light emitting element. Accordingly, writing a signal to the memory circuit while the third transistor is in the OFF-state makes it possible to reliably write or rewrite the signal to the memory circuit at low power consumption. Thus, the current configuration can prevent the electro-optical device from displaying a wrong or low-quality image due to incorrect writing of signals to the memory circuit.

APPLICATION EXAMPLE 3

In the electro-optical device according to the application example described above, an ON-resistance of the third transistor is sufficiently lower than an ON-resistance of the light emitting element.

According to the configuration of Application Example 3, while both the third transistor and the light emitting element are in ON-state to cause the light emitting element to emit light, the third transistor is substantially operated in the linear region. Hereinafter, a transistor operated in the linear region is simply referred to a linear operation. As a result, most of a potential drop occurring in the light emitting element and the third transistor is applied to the light emitting element, resulting in a less susceptible state to variation in the threshold voltage while the light emitting element is emitting light. Therefore, variation in brightness and grey scale shift among pixels can be reduced.

APPLICATION EXAMPLE 4

In the electro-optical device according to the application example described above, an ON-resistance of the first transistor is lower than or equal to an ON-resistance of the third transistor.

According to the configuration of Application Example 4, the current flow ability of the first transistor is larger than the current flow ability of the third transistor, thus enabling reduction of the risk that the signal stored in the memory circuit may be rewritten when the light emitting element emits light. Thus, a high-quality image without any display errors can be achieved. Moreover, since the ON-resistance of the third transistor is sufficiently lower than the ON-resistance of the light emitting element, both the first and third transistors are operated in the linear region while the light emitting element emits light. As a result, most of a potential drop occurring in the light emitting element, the first transistor, and the third transistor, is applied to the light emitting element, resulting in a less susceptible state to variation in the threshold voltage of the first transistor or the third transistor. Thus, variation in brightness and grey scale shift among pixels can be reduced.

APPLICATION EXAMPLE 5

In the electro-optical device according to the application example described above, the third transistor is in an OFF-state while the second transistor is in an ON-state.

According to the configuration of Application Example 5, when the second transistor is in the ON-state to write a signal to the memory circuit, the third transistor is in the OFF-state to prevent a current from flowing through the light emitting element. As a result, the signal can be written fast and reliably to the memory circuit with low power consumption. Thus, a high-quality image without any display errors can be achieved.

APPLICATION EXAMPLE 6

In the electro-optical device according to the application example described above, the second transistor is in an OFF-state while the third transistor is in an ON-state.

According to the configuration of Application Example 6, when the third transistor is in the ON-state to cause the light emitting element to emit light, the second transistor is in the OFF-state to prevent a signal from being written to the memory circuit. As a result, display errors caused by the signal erroneously rewritten to the memory circuit can be prevented. Moreover, controlling non-emission and emission periods in a time-division manner makes it possible to display the grey scales accurately. This is because the light is not emitted and the signal is written to the memory circuit in the non-emission period; by contrast the light is emitted and the signal is hold in the memory circuit in the emission period in the current configuration.

APPLICATION EXAMPLE 7

The electro-optical device according to the application example described above further includes an enable line. A gate of the second transistor is electrically connected to the scan line. A gate of the third transistor is electrically connected to the enable line.

According to the configuration of Application Example 7, the second transistor and the third transistor are independently controlled through the scan line and the enable line, respectively. Thus, for example, the third transistor turns into an OFF-state after the second transistor turns into an ON-state, or the third transistor turns into an ON-state after the second transistor turns into an OFF-state.

APPLICATION EXAMPLE 8

In the electro-optical device according to the application example described above, an inactive signal for bringing the third transistor into an OFF-state is supplied to the enable line during a first period in which a selection signal for turning the second transistor into an ON-state is supplied to the scan line.

According to the configuration of Application Example 8, the third transistor is in the OFF-state during the first period during which the second transistor is in the ON-state, such that the first period serves as a signal write period during which a signal is written to the memory circuit while the light emitting element is not emitting light.

APPLICATION EXAMPLE 9

In the electro-optical device according to the application example described above, a non-selection signal for turning the second transistor into an OFF-state is supplied to the scan line during a second period in which an active signal for turning the third transistor into an ON-state is supplied to the enable line.

According to the configuration of Application Example 9, the second period serves as a light emission period, i.e. a display period, since the second transistor is in the OFF-state and the third transistor is in the ON-state during the second period. During the second period the light emitting element emits light while the memory circuit holds the signal. Furthermore, this configuration makes it possible to make the second period shorter than the first period by controlling the length of the first period and the second period. As a result, the electro-optical device displays a large number of grey scales using a time-division driving manner. Moreover, driving of the electro-optical device is facilitated in this configuration, because a control signal supplied to the enable lines is shared among a plurality of pixels. Specifically, the electro-optical device is readily driven to display a short sub-field in which the light emission period is even shorter than one vertical period during which selection of each of a plurality of scan lines is completed.

APPLICATION EXAMPLE 10

In the electro-optical device according to the application example described above, a gate of the second transistor and a gate of the third transistor are electrically connected to the scan line, and the second transistor and the third transistor have polarities opposite to each other.

According to the configuration of Application Example 10, since one of the second transistor and the third transistor is P-type and the other is N-type, a signal supplied from the scan line enables one transistor to be in an ON-state and the other transistor to be in an OFF-state. Accordingly, the scan line also functions as the enable line, thus enabling reduction of the number of wires and thus, the number of wiring layers. As a result, the production yield of the electro-optical device can be improved. In addition, with a reduced number of wires, the area that shields light can be decreased to achieve an electro-optical device with a high resolution and fine pixels.

APPLICATION EXAMPLE 11

An electronic apparatus according to Application Example 11 includes the electro-optical device described in the application examples.

According to the configuration of Application Example 11, a high-quality image can be displayed on the electronic apparatus such as a head-mounted display.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Several exemplary embodiments of the disclosure will be described below with reference to the drawings. In the drawings referred to below, layers, members, and the like are not to scale in order to make the layers, members, and the like recognizable in size.

Outline of Electronic Apparatus

Outline of an electronic apparatus will now be described with reference toFIG. 1.FIG. 1schematically illustrates an electronic apparatus according to some exemplary embodiments.

A head-mounted display100is an example of the electronic apparatus according to some exemplary embodiments, and includes an electro-optical device10(refer toFIG. 3). As illustrated inFIG. 1, the head-mounted display100has an appearance like glasses. The head-mounted display100allows a user who wears the head-mounted display100to view image light GL of an image (refer toFIG. 3) and allows the user to view outside light as a see-through image. Specifically, the head-mounted display100has a see-through function that displays a superimposition of the outside light and the image light GL, has a wide angle of view and high performance, and is also small and light.

The head-mounted display100includes a see-through member101that covers the eyes of the user, a frame102that supports the see-through member101, and a first built-in device unit105aand a second built-in device unit105bthat are attached to the frame102over an area extending from cover portions at respective ends of the frame102over a portion of temples behind.

The see-through member101is a thick, curved optical member, namely a transparent eye cover, covering the eyes of the user and is separated into a first optical portion103aand a second optical portion103b.As seen on the left side inFIG. 1, a first display apparatus151, which includes a combination of the first optical portion103aand the first built-in device unit105a,is a part to display a virtual image for the right eye as a see-through image and functions by itself as an electronic apparatus with a display function. As seen on the right side inFIG. 1, a second display apparatus152, which includes a combination of the second optical portion103band the second built-in device unit105b,is a part to display a virtual image for the left eye as a see-through image and functions by itself as an electronic apparatus with a display function. Each of the first display apparatus151and the second display apparatus152has the electro-optical device10(refer toFIG. 3) incorporated therein.

Internal Structure of Electronic Apparatus

FIG. 2illustrates an internal structure of the electronic apparatus according to one exemplary embodiment.FIG. 3illustrates an optical system of the electronic apparatus according to one exemplary embodiment. The internal structure and the optical system of the electronic apparatus will now be described with reference toFIG. 2andFIG. 3. WhileFIG. 2andFIG. 3illustrate the first display apparatus151as an example of the electronic apparatus, the second display apparatus152is symmetrical to the first display apparatus151and has substantially the same structure. Accordingly, only the first display apparatus151will be described here and detailed description of the second display apparatus152will be omitted.

As illustrated inFIG. 2, the first display apparatus151includes a projection see-through device170and the electro-optical device10(refer toFIG. 3). The projection see-through device170includes a prism110to serve as a light guide member, a transparent member150, and a projector lens130for image formation (refer toFIG. 3). The prism110and the transparent member150are integrated together by bonding and are firmly fixed to the bottom of a frame161such that a top face110eof the prism110and a bottom face161eof the frame161are held in contact with each other, for example.

The projector lens130is fixed to an end of the prism110through a lens barrel162that houses the projector lens130. The prism110and the transparent member150in the projection see-through device170correspond to the first optical portion103ashown inFIG. 1. The projector lens130and the electro-optical device10in the projection see-through device170correspond to the first built-in device unit105ashown inFIG. 1.

The prism110in the projection see-through device170is an arc-shaped member that is curved along the face of the user when viewed in a plan view and may be considered to be formed of a first prism portion111on the central side closer to the nose and a second prism portion112on the peripheral side away from the nose. The first prism portion111is disposed on the light emission side and has a first face S11(refer toFIG. 3), a second face S12, and a third face S13, each of which serves as a side face having an optical function.

The second prism portion112is disposed on the light incident side and has a fourth face S14(refer toFIG. 3) and a fifth face S15, each of which serves as a side face having an optical function. Of these faces, the first face S11and the fourth face S14are adjacent to each other, the third face S13and the fifth face S15are adjacent to each other, and the second face S12is disposed between the first face S11and the third face S13. Also, the prism110has the top face110ethat is adjacent to the first face S11to the fourth face S14.

The prism110is formed from a resin material with high optical transparency in a visible range and is molded, for example, by pouring a thermoplastic resin into a mold and curing the resin. While a body portion110s(refer toFIG. 3) of the prism110is an integrally formed article, it can be considered to be formed of the first prism portion111and the second prism portion112. The first prism portion111can guide and output the image light GL and also allows outside light to be seen-through. The second prism portion112can receive and guide the image light GL.

The transparent member150is integrally fixed to the prism110. The transparent member150is a member that served as an auxiliary prism and aids in the see-through function of the prism110. The transparent member150has high optical transparency in a visible range and is formed from a resin material with a refractive index that is substantially equal to the refractive index of the body portion110sof the prism110. The transparent member150is formed, for example, by molding thermoplastics resin.

As illustrated inFIG. 3, the projector lens130includes three lenses131,132, and133that are arranged along the optical axis on the light input side. Each of the lenses131,132, and133is rotationally symmetrical with respect to the central axis of the light input surfaces of the lenses. At least one of the lenses131,132, and133is an aspherical lens.

The projector lens130directs the image light GL emitted from the electro-optical device10into the prism110to re-form an image on an eye EY. In other words, the projector lens130is a relay optical system to re-form an image of the image light GL emitted from each pixel of the electro-optical device10on the eye EY through the prism110. The projector lens130is held in the lens barrel162and the electro-optical device10is fixed to an end of the lens barrel162. The second prism portion112of the prism110is connected to the lens barrel162, which holds the projector lens130, to indirectly support the projector lens130and the electro-optical device10.

An electronic apparatus of a type that is mounted on the head of the user to cover the eyes, such as the head-mounted display100, is required to be small and light. The electro-optical device10used in the electronic apparatus such as the head-mounted display100is required to provide high resolution, fine pixels, multiple grey scales of display, and low power consumption.

Configuration of Electro-optical Device

First Exemplary Embodiment

A configuration of the electro-optical device will now be described with reference toFIG. 4.FIG. 4is a schematic plan view illustrating a configuration of the electro-optical device according to First Exemplary Embodiment. An organic EL device that includes an organic EL element as a light emitting element is explained as an example of the electro-optical device10in First Exemplary Embodiment. As illustrated inFIG. 4, the electro-optical device10according to First Exemplary Embodiment includes an element substrate11and a protective substrate12. The element substrate11is provided with a color filter (not illustrated). The element substrate11and the protective substrate12are arranged to face each other and are bonded together with filler (not illustrated).

The element substrate11is formed from, for example, a single-crystal semiconductor substrate (e.g., a single-crystal silicon wafer). The element substrate11has a display region E and a non-display region F surrounding the display region E. In the display region E, for example, sub-pixels48B that emit blue light (B), sub-pixels48G that emit green light (G), and sub-pixels48R that emit red light (R) are arranged in a matrix for example. A light emitting element20(refer toFIG. 6) is provided in each of the sub-pixels48B, the sub-pixels48G, and the sub-pixels48R. In the electro-optical device10, a pixel49that includes the sub-pixel48B, the sub-pixel48G, and the sub-pixel48R is a display unit to show full color images.

In this specification, the sub-pixel48B, the sub-pixel48G, and the sub-pixel48R are not distinguished from one another and may be collectively referred to as a sub-pixel48. The display region E is a region where light emitted from the sub-pixel48is transmitted and contributes to display. The non-display region F is a region where light emitted from the sub-pixel48is not transmitted and does not contribute to display.

The element substrate11is larger than the protective substrate12and a plurality of external connection terminals13are arranged along a first side of the element substrate11which extends out of the protective substrate12. A data line drive circuit53is provided between the display region E and the plurality of external connection terminals13. A scan line drive circuit52is provided between the display region E and a second side that is another side perpendicular to the first side. An enable line drive circuit54is provided between the display region E and a third side that is perpendicular to the first side and opposite to the second side.

The protective substrate12is smaller than the element substrate11and is disposed so that the external connection terminals13are exposed. The protective substrate12is a light transparent substrate such as a quartz substrate or a glass substrate, for example. The protective substrate12is disposed to face at least the display region E to protect the light emitting elements20disposed in the sub-pixels48in the display region E from being damaged.

The color filter may be provided on the light emitting elements20in the element substrate11or it may be provided on the protective substrate12. On the other hand, the color filter may not be required in such a configuration in which light corresponding to each color is emitted from the light emitting element20. The protective substrate12may not be required, and instead of the protective substrate12, a protective layer to protect the light emitting element20may be provided on the element substrate11.

In this specification, a direction along the first side on which the external connection terminals13are arranged is referred to as X direction, and a direction along the other two sides that are the second and third sides is referred to as Y direction. The second and third sides are perpendicular to the first side and are opposed each other. In this application the X direction is referred to as a row direction and the Y direction is referred to as a column direction. In First Exemplary Embodiment the sub-pixels48are arranged in a so-called stripe arrangement in which the sub-pixels48that emit the same color are arranged in the column direction, i.e. the Y direction, and the sub-pixels48that emit different colors are arranged in the row direction, i.e. the X direction.

The arrangement of the sub-pixels48in the row direction (the X direction) is not limited to the order of B, G, and R as illustrated inFIG. 4and may be in the other order such as R, G, and B for example. The arrangement of the sub-pixels48is not limited to the stripe arrangement and may be a delta arrangement, a Bayer arrangement, or an S-stripe arrangement. In addition, the sub-pixels48B, the sub-pixels48G, and the sub-pixels48R are neither limited to the same shape nor to the same size.

Circuit Configuration of Electro-Optical Device

A circuit configuration of the electro-optical device will now be described with reference toFIG. 5.FIG. 5is a circuit block diagram of the electro-optical device according to First Exemplary Embodiment. As illustrated inFIG. 5a plurality of scan lines42, a plurality of data lines43, and a plurality of sub-pixels48are formed in the display region E of the electro-optical device10. The scan lines42and the data lines43cross each other. The sub-pixels48are arranged in a matrix corresponding to the respective intersections of the scan lines42and the data lines43. Each sub-pixel48possesses a pixel circuit41that includes the light emitting element20, a third transistor33(refer toFIG. 8), and the like.

In the display region E, enable lines44are formed corresponding to the respective scan lines42. The scan lines42and the enable lines44extend in the row direction. Also formed in the display region E are complementary data lines45that correspond to the respective data lines43. The data lines43and the complementary data lines45extend in the column direction.

Letting M and N be each an integer of two or greater, in the electro-optical device10sub-pixels48form a matrix of M rows×N columns in the display region E. Also, M scan lines42, M enable lines44, N data lines43, and N complementary data lines45are formed in the display region E. In First Exemplary Embodiment M=720 and N=1280×p as an example. Here, p is an integer of one or more and indicates the number of basic colors for display. In First Exemplary Embodiment p=3, as an example, that is, the basic colors for display are three colors of R, G, and B.

The electro-optical device10includes a driving unit50outside the display region E. The driving unit50supplies various signals to the respective pixel circuits41arranged in the display region E, such that an image is displayed in the display region E, using the pixels49as display units. In First Exemplary Embodiment, each of the pixels49includes the sub-pixels48for the three colors. The driving unit50includes a drive circuit51and a control unit55. The control unit55supplies a display signal to the drive circuit51. The drive circuit51supplies a drive signal to each pixel circuit41via the plurality of scan lines42, the plurality of data lines43, and the plurality of enable lines44. The drive signal is based on the display signal.

The drive circuit51includes the scan line drive circuit52, the data line drive circuit53, and the enable line drive circuit54. The drive circuit51is provided in the non-display region F (refer toFIG. 4). In First Exemplary Embodiment, the drive circuit51and the pixel circuit41are formed on the element substrate11as illustrated inFIG. 4. In First Exemplary Embodiment, a single-crystal silicon wafer is used for the element substrate11. Specifically, the drive circuit51, the pixel circuit41, and the like are formed from elements, such as transistors, which are formed on the single-crystal silicon wafer.

The scan lines42are electrically connected to the scan line drive circuit52. The scan line drive circuit52outputs a scan signal (Scan) to each scan line42. The scan signal does or does not select the pixel circuit41in the row direction. The scan line42transmits the scan signal to the pixel circuit41. In other words, the scan signal has a selection-state and a non-selection-state. Each scan line42is appropriately selected, receiving the scan signal from the scan line drive circuit52.

A low potential line46and a high potential line47are arranged in the non-display region F. The low potential line46supplies a low potential (VSS) to each pixel circuit41whereas the high potential line47supplies a high potential (VDD) to each pixel circuit41. While the low potential line46and the high potential line47each extend in the row direction as an example in First Exemplary Embodiment, they may extend in the column direction or they may be arranged in the row and column directions to form a matrix.

As described later, when both a second transistor32and a complementary second transistor37are N-type (refer toFIG. 8), the scan signal in the selection-state, i.e. a selection signal, is the high potential VDD (for example VDD=5 V). On the other hand, the scan signal in the non-selection-state, i.e. a non-selection signal, is the low potential VSS (for example VSS=0 V).

As illustrated inFIG. 6, in order to specify a scan signal supplied to the scan line42in the first row among the M scan lines42the scan signal in the first row is indicated as Scan1; a scan signal supplied to the scan line42in the i-th row is indicated as Scan i to specify the scan signal in the i-th row; and a scan signal supplied to the scan line42in the M-th row is indicated as Scan M to specify the scan signal in the M-th row. The scan line drive circuit52includes a shift register circuit (not illustrated). Signals shifted in the shift register circuit are output from each stage as shift-output signal. The scan signals Scan1to Scan M are generated from the shift-output signals.

The data lines43and the complementary data lines45are electrically connected to the data line drive circuit53. The data line drive circuit53may include a shift register circuit, a decoder circuit, a multiplexer circuit, or the like (not illustrated). The data line drive circuit53supplies image signals (Data) to each of the N data lines43and supplies complementary image signals to each of the N complementary data lines45, in synchronization with the selection of the scan lines42. In First Exemplary Embodiment, the image signal and the complementary image signal are digital signals and have one of the low potential, e.g. VSS=0 V, and the high potential, e.g. VDD=5 V.

An image signal supplied to the data line43in the first column of the N data lines43is indicated as Data1to specify the image signal in the first column; an image signal supplied to the data line43in the j-th column is indicated as Data j to specify the image signal in the j-th column (refer toFIG. 6); and an image signal supplied to the data line43in the N-th column is indicated as Data N to specify the image signal in the N-th column.

Likewise, a complementary image signal supplied to the complementary data line45in the first column of the N complementary data lines45is indicated as XData1to specify the complementary image signal in the first column; a complementary image signal supplied to the complementary data line45in the j-th column is indicated as XData j to specify the complementary image signal in the j-th column (refer toFIG. 6); and a complementary image signal supplied to the complementary data line45in the N-th column is indicated as XData N to specify the complementary image signal in the N-th column.

The enable lines44are electrically connected to the enable line drive circuit54. The enable line drive circuit54outputs enable signals to the enable lines44which separately correspond to the respective rows. The enable signals are specific to the rows. The enable line44transmits the enable signal to the pixel circuit41in the corresponding row. The enable signals are potentials between a second low potential VSS2and a second high potential VDD2. The enable signal includes an active signal, i.e. an enable signal in an active state, and an inactive signal, i.e. an enable signal in an inactive state. The enable line44is an active state when it receives the active signal from the enable line drive circuit54.

As described later, when the third transistor33is N-type (refer toFIG. 8), the enable signal in the active state is the second high potential VDD2. On the other hand, the enable signal in the inactive state is the second low potential VSS2. In First Exemplary Embodiment, as an example, the second high potential VDD2and the high potential VDD are equal (VDD2=VDD=5 V), and the second low potential VSS2and the low potential VSS are equal (VSS2=VSS=0 V).

An enable signal supplied to the enable line44in the first row of the M enable lines44is indicated as Enb1to specify the enable signal in the first row; an enable signal supplied to the enable line44in the i-th row is indicated as Enb i to specify the enable signal in the i-th row (refer toFIG. 6); and an enable signal supplied to the enable line44in the M-th row is indicated as Enb M to specify the enable signal in the M-th row. The enable signal in active state may be supplied as row by row, or the enable signals in active state may be simultaneously supplied to a plurality of rows. In First Exemplary Embodiment, the active signals are simultaneously supplied to all the pixel circuits41arranged in the display region E.

The control unit55includes a display signal supply circuit56and a VRAM circuit57. The display signal supply circuit supplies the display signal to the drive circuit51. The VRAM circuit57stores a frame image and the like. The display signal supply circuit56generates the display signal from the frame image temporarily stored in the VRAM circuit57and supplies it to the drive circuit51. The display signal includes an image signal, a clock signal, and the like.

The control unit55includes a semiconductor integrated circuit that is formed on a different substrate (not illustrated) from the element substrate11. The semiconductor integrated circuit may be formed on a single-crystal semiconductor wafer. The substrate on which the control unit55is formed is connected to the external connection terminals13provided on the element substrate11by using a flexible printed circuit (FPC). Via the FPC, the display signal is supplied to the drive circuit51from the control unit55.

Configuration of Pixel

A configuration of a pixel according to some exemplary embodiments will now be described with reference toFIG. 6.FIG. 6illustrates a configuration of a pixel according to some exemplary embodiments.

As illustrated above, in the electro-optical device10, the pixel49that includes the sub-pixel48(the sub-pixel48B, the sub-pixel48G, and the sub-pixel48R) forms a display unit to display an image. In one exemplary embodiment, the length a of the sub-pixel48in the row direction (the X direction) is 4 micrometers (μm), and the length b of the sub-pixel48in the column direction (the Y direction) is 12 micrometers (μm). In other words, the pitch at which the sub-pixels48are arranged in the row direction (the X direction) is 4 μm, and the pitch at which the sub-pixels48are arranged in the column direction (the Y direction) is 12 μm.

Each sub-pixel48possesses the pixel circuit41that includes the light emitting element20. The light emitting element20emits white light. The electro-optical device10includes the color filter (not illustrated), which transmits light emitted from the light emitting element20. The color filter includes p kinds of color filters that correspond to p basic colors for display. In one exemplary embodiment, the number of basic colors is set as p=3, and color filters for colors B, G, and R, are arranged to correspond to the sub-pixel48B, the sub-pixel48G, and the sub-pixel48R, respectively.

In one exemplary embodiment an organic electroluminescence (EL) element is used as an example of the light emitting element20. The organic EL element may have an optical resonant structure that enhances the intensity of light with a specific wavelength. Specifically, the organic EL element may be configured such that a blue light is extracted from the white light emitted from the light emitting element20in the sub-pixel48B; a green light is extracted from the white light emitted from the light emitting element20in the sub-pixel48G; and a red light is extracted from the white light emitted from the light emitting element20in the sub-pixel48R.

As another example other than the examples described above, the number of basic colors may be set as p=4 so that, in addition to the color filters for B, G, and R, a color filter for another color, for example, white color which substantially disposed no color filter, yellow, or cyan, may be prepared. As the light emitting element20, a light emitting diode element using gallium nitride (GaN) and the like, or a semiconductor laser element may also be used.

Digital Driving in Electro-optical Device

An image display method by digital driving in the electro-optical device10according to one exemplary embodiment will now be described with reference toFIG. 7.FIG. 7illustrates digital driving in the electro-optical device according to one exemplary embodiment.

The electro-optical device10displays a predetermined image in the display region E (refer toFIG. 4) by digital driving method. Specifically, the light emitting element20(refer toFIG. 6) arranged in each sub-pixel48has a state of one of the binary values, namely emission of light (bright state) and non-emission of light (dark state), and the grey scale of an image to be displayed depends on the ratio of a light emission period of the light emitting element20. This is referred to as time-division driving.

As illustrated inFIG. 7, in the time-division driving, a single field (F) during which a single image is displayed is divided into a plurality of sub-fields (SFs), and emission and non-emission of light of the light emitting element20is controlled for each sub-field (SF) so that the grey scale is represented. A 6-bit time-division grey scale system is described here as an example here. This system displays 26=64 grey scales. In the 6-bit time-division grey scale system, the single field F is divided into six sub-fields, namely SF1to SF6.

InFIG. 7, the i-th sub-field in the single field F is indicated by SFi and six sub-fields including the first sub-field SF1to the sixth sub-field SF6are illustrated. Each sub-field SF includes a display period P2(P2-1to P2-6) as a second period and, optionally, a non-display period P1(P1-1to P1-6) as a first period. The non-display period P1is a signal write period.

In this specification, the sub-fields SF1to SF6may not be distinguished from one another and may be collectively referred to as a sub-field SF; the non-display periods P1-1to P1-6may not be distinguished from one another and may be collectively referred to as a non-display period P1; and the display periods P2-1to P2-6may not be distinguished from one another and may be collectively referred to as a display period P2.

The light emitting element20does or does not emit light during the display period P2while it does not emit light during the non-display period P1. An image signal is introduced to a memory circuit60(refer toFIG. 8) during the non-display period P1. The non-display period P1may adjust the ratio of a light emission period. In cases such as when the shortest sub-field (e.g., SF1) is long enough to introduce the image signals to all the sub-pixels48, the non-display period P1may be eliminated.

In the 6-bit time-division grey scale system, the display periods P2(P2-1to P2-6) in the respective sub-fields SF are set such that (P2-1in SF1):(P2-2in SF2):(P2-3in SF3):(P2-4in SF4):(P2-5in SF5):(P2-6in SF6)=1:2:4:8:16:32. Thus, for example, when an image is displayed in a progressive system with a frame frequency of 30 Hz, 1 frame=1 field (F)=33.3 milliseconds (msec).

Given that the duration of the non-display period P1is represented as x (sec), the duration of the shortest display period P2, e.g. the display period P2-1in the first sub-field SF1in the example described above, is represented as y (sec), the number of bits of grey scale, i.e. the number of sub-fields SF, is represented as g, and the field frequency is represented as f (Hz), their relation is represented by Equation (1) below:
gx+(2g−1)y=1/f(1)

The digital driving in the electro-optical device10displays grey scale based on the ratio of sum of the light emission periods to the total display periods P2in the single field F. For example, for black display corresponding to a grey scale “0”, the light emitting element20is in the non-emission state during all of the display periods P2-1to P2-6in the six sub-fields SF1to SF6. On the other hand, for white display corresponding to a grey scale “63”, the light emitting element20is in the emission state during all of the display periods P2-1to P2-6in the six sub-fields SF1to SF6.

To obtain display with an intermediate luminance corresponding to, for example, a grey scale “7” of the 64 tones, the light emitting element20is in the emission state during the display period P2-1in the first sub-field SF1, the display period P2-2in the second sub-field SF2, and the display period P2-3in the third sub-field SF3, while the light emitting element20is in the non-emission state during the display periods P2-4to P2-6in the other sub-fields SF4to SF6. In this way, the state of the light emitting element20may be selected to be the emission or the non-emission of light as appropriate for each of the sub-fields SF constituting the single field F so as to display an intermediate grey scale.

Analog-driven organic EL devices in prior art, which are electro-optical devices, display a grey scale analog-controlling the current flowing through the organic EL elements. The current depends on the gate potential of driving transistors. This causes variation in brightness as well as grey scale shift among pixels due to variation in the transfer characteristics and the threshold voltage of the driving transistor, thus resulting in a low display quality. In order to overcome this problem, when a compensation circuit is provided that compensates for the variation in the transfer characteristics and the threshold voltage of driving transistors as described in JP-A-2004-062199, an additional current must flow through the compensation circuit, thus increasing power consumption.

Furthermore, in order to achieve multiple grey scales display, organic EL devices in prior art require a capacitive element with large capacitance to store analog image signals. This requirement is incompatible with the requirements for high resolution, namely fine pixels, and has also resulted in a large power consumption due to charging and discharging of the capacitive element with large capacitance. In other words, it is difficult to achieve an electro-optical device that displays a high-quality image having a high resolution and multiple grey scales at a low power consumption by using any of organic EL devices in prior art.

Since the electro-optical device10according to one exemplary embodiment is digitally driven, using binary system of ON-state and OFF-state, the light emitting element20is in one of the binary states, namely emission of light and non-emission of light. Accordingly, the electro-optical device10is less susceptible to the variation in the transfer characteristics and the threshold voltage of each transistor as compared to those based on analog driving. As a result, the electro-optical device10according to one exemplary embodiment reduces variation in brightness and decreases shift in grey scale among the pixels49to display a high-quality image. Furthermore, since the digital driving method eliminates the requirement for a capacitive element with a large capacitance, which is required in analog driving method, it helps to achieve fine pixels49and a higher resolution and decreases the power consumption associated with charging and discharging of the large capacitive element.

Moreover, according to the digital driving method in the electro-optical device10, the number of grey scale can be readily increased by increasing the number g of sub-fields SF in a field F. Even though the non-display periods P1exist as described above, the number of grey scale is easily increased by shortening the shortest display period P2. For example, in order to display 256 grey scales with g=8 in a progressive system at a frame frequency of f=30 Hz, it is sufficient to simply set the duration of the shortest display period (P2-1in SF1) to y=0.100 millisecond according to Equation 1, if the duration of the non-display period P1is x=1 millisecond.

As described later, in the digital driving method in the electro-optical device10, the non-display periods P1as a first period can serve as a signal write period during which an image signal is written to the memory circuit60or a signal rewrite period during which an image signal is rewritten. Accordingly, 6-bit grey scale display can be easily converted to 8-bit grey scale display without changing the signal write period. This convert does not need to change the clock frequency of the drive circuit51.

Furthermore, in the digital driving method in the electro-optical device10, the image signal stored in the memory circuit60(refer toFIG. 8) will be rewritten between the sub-fields SF or between the field F, only if the memory circuit60is in the sub-pixel48that is to be changed. In other words, the image signal stored in the memory circuit60will not be rewritten and will be kept, if the memory circuit60is in the sub-pixel48that is not to be changed. As a result, the power consumption can be reduced. Thus, this configuration can achieve electro-optical device10that displays an image having a large number of grey scales and a high resolution as well as a less variation in brightness and a small shift in grey scale among the pixels49while reducing energy consumption.

Configuration of Pixel Circuit

A configuration of a pixel circuit according to First Exemplary Embodiment will now be described using a plurality of examples and modified examples. First, a configuration of a pixel circuit according to Example 1 of First Exemplary Embodiment is described with reference toFIG. 8.FIG. 8illustrates a configuration of a pixel circuit according to Example 1.

As illustrated inFIG. 8, the pixel circuit41is provided for each of the sub-pixels48that are arranged to correspond to the respective intersections of the scan lines42and the data lines43. The enable line44is arranged along the scan line42whereas the complementary data line45is arranged along the data line43. The scan line42, the data line43, the enable line44, and the complementary data line45correspond to each pixel circuit41.

In one exemplary embodiment, the low potential line46is a first potential line, and the low potential VSS is supplied as a first potential from the low potential line46to the pixel circuit41. The high potential line47is a second potential line, and the high potential VDD is supplied as a second potential from the high potential line47to the pixel circuit41.

The pixel circuit41includes the light emitting element20, the memory circuit60including a first transistor31, a second transistor32arranged between the memory circuit60and the data line43, a third transistor33, and the complementary second transistor37. The pixel circuit41includes the memory circuit60, such that the electro-optical device10can digitally drive the circuits and can make it possible to reduce the variation in display among the pixels49(the sub-pixels48), as compared to the case of analog driving.

In one embodiment, the light emitting element20is an organic EL element and includes an anode21that is a pixel electrode, a light emitting section22that is a light emitting functional layer, and a cathode23that is a counter electrode. The light emitting section22is configured to emit light when a positive hole injected from the anode21side and an electron injected from the cathode23side together form an exciton, which emits part of its energy as fluorescence or phosphorescence as it disappears (as the positive hole and the electron recombine).

The anode21of the light emitting element20is electrically connected to the high potential line47that serves as the second potential line while the cathode23of the light emitting element20is electrically connected to the drain of the third transistor33. In other words, the light emitting element20is arranged on the high potential side with respect to the third transistor33.

The memory circuit60includes a first inverter61and a second inverter62. The memory circuit60is configured to include the two inverters61and62connected together in a circle to form a so-called static memory to store a digital signal, which is an image signal. An output terminal25of the first inverter61is electrically connected to an input terminal28of the second inverter62, and an output terminal27of the second inverter62is electrically connected to an input terminal26of the first inverter61.

In this specification, the state where a terminal A and a terminal B are electrically connected to each other means a state where the logic of the terminal A and the logic of the terminal B can be equal. For example, even when a transistor, a resistor, a diode, and the like are arranged between the terminal A and the terminal B, the terminals will be regarded as a state of electrically connecting, if the logic of terminal A is the same as the logic of terminal B.

A digital signal stored in the memory circuit60has one of the binary potentials of High and Low. In one exemplary embodiment, when the output terminal25of the first inverter61is Low (when the output terminal27of the second inverter62is High), the light emitting element20is brought into a state that allows emission of light, whereas when the output terminal25of the first inverter61is High (when the output terminal27of the second inverter62is Low), the light emitting element20is brought into a state of non-emission of light.

In one exemplary embodiment, the two inverters61and62which constitute the memory circuit60are arranged between the low potential line46that serves as the first potential line and the high potential line47that serves as the second potential line, and the high potential VDD and the low potential VSS are supplied to the two inverters61and62. Accordingly, High corresponds to the high potential VDD that serves as the second potential, and Low corresponds to the low potential VSS that serves as the first potential.

When a digital signal is introduced in the memory circuit60and the output terminal25of the first inverter61is brought into Low, for example, Low is input to the input terminal28of the second inverter62to turn the output terminal27of the second inverter62to High. Then, High is input to the input terminal26of the first inverter61to turn the output terminal25of the first inverter61to Low. In this way, the digital signal introduced in the memory circuit60is maintained in a stable state until it is rewritten next time.

The first inverter61includes the N-type first transistor31and a P-type fourth transistor34. These two transistors constitute CMOS configuration. The first transistor31and the fourth transistor34are arranged in series between the low potential line46and the high potential line47. The source of the first transistor31is electrically connected to the low potential line46that serves as the first potential line. The source of the fourth transistor34is electrically connected to the high potential line47that serves as the second potential line.

The first transistor31is a component of the memory circuit60, i.e. a component of the first inverter61, and is also a driving transistor for the light emitting element20. Thus, once the first transistor31is turned in an ON-state, the light emitting element20is allowed to emit light.

The second inverter62includes an N-type fifth transistor35and a P-type sixth transistor36. These two transistors constitute CMOS configuration. The fifth transistor35and the sixth transistor36are arranged in series between the low potential line46and the high potential line47. The source of the fifth transistor35is electrically connected to the low potential line46that serves as the first potential line. The source of the sixth transistor36is electrically connected to the high potential line47that serves as the second potential line.

The drain of the first transistor31and the drain of the fourth transistor34form the output terminal25of the first inverter61. The drains of the fifth transistor35and the sixth transistor36form the output terminal27of the second inverter62. The input terminal26of the first inverter61is formed by the gates of the first transistor31and the fourth transistor34. The input terminal26is electrically connected to the output terminal27of the second inverter62. Likewise, the input terminal28of the second inverter62is formed by the gates of the fifth transistor35and the sixth transistor36. The input terminal28of the second inverter62is electrically connected to the output terminal25of the first inverter61.

In one exemplary embodiment, the first inverter61and the second inverter62each constitute CMOS configuration. However, the inverters61and62may be configured to include transistors and resistors. For example, the first inverter61may be configured to include the first transistor31and a resistor in place of the fourth transistor34. In the second inverter62, one of the fifth transistor35and the sixth transistor36may be replaced with a resistor.

The second transistor32is an N-type transistor. The second transistor32is arranged between the output terminal25of the memory circuit60(the output terminal25of the first inverter61) and the data line43. One of the source and the drain of the second transistor32is electrically connected to the data line43, while the other is electrically connected to the output terminal25of the memory circuit60(the first inverter61), that is, the drain of the first transistor31. The gate of the second transistor32is electrically connected to the scan line42.

The third transistor33is an N-type transistor. The third transistor33is arranged in series with the light emitting element20between the output terminal25of the first inverter61, that is, the drain of the first transistor31, and the high potential line47that serves as the second potential line. The third transistor33is arranged on the lower potential side than is the light emitting element20. In other words, the third transistor33is located nearer to the output terminal25than is the light emitting element20.

The drain of the third transistor33is electrically connected to the cathode23of the light emitting element20. The source of the third transistor33is electrically connected to the output terminal25of the memory circuit60(the first inverter61), that is, the drain of the first transistor31. The gate of the third transistor33is electrically connected to the enable line44. The third transistor33is a control transistor for the memory circuit60and the light emitting element20.

Note that for an N-type transistor, the source is defined so that the source potential is lower than the drain potential. Typically, an N-type transistor is arranged on the lower potential side than is the light emitting element20. On the other hand, note that for a P-type transistor, the source is defined so that the source potential is higher than the drain potential. Typically, a P-type transistor is arranged on the higher potential side than is the light emitting element20. This arrangement makes each transistor operate substantially in linear region. Hereinafter, operating a transistor in linear region simply refers to as linear operation.

In one exemplary embodiment, the first transistor31, the second transistor32, and the third transistor33are each an N-type. Accordingly, the arrangement of the first transistor31and the third transistor33on the lower potential side than the light emitting element20enables the first transistor31and the third transistor33of linear operation. As a result, the variation in the threshold voltage of the transistors31and33will not affect the display characteristics.

The complementary second transistor37is an N-type transistor. The complementary second transistor37is arranged between the output terminal27of the memory circuit60(the second inverter62) and the complementary data line45. One of the source and the drain of the complementary second transistor37is electrically connected to the complementary data line45, while the other is electrically connected to the output terminal27of the memory circuit60(the second inverter62). The gate of the complementary second transistor37is electrically connected to the enable line44.

The electro-optical device10according to one exemplary embodiment includes a plurality of complementary data lines45in the display region E (refer toFIG. 5). One data line43and one complementary data line45correspond to one pixel circuit41. Signals that are complementary to each other are supplied to a pair of the data line43and its complementary data line45, both of which corresponds to a pixel circuit41. In other words, a signal with an inverted polarity relative to the signal supplied to the data line43is supplied to the corresponding complementary data line45. Hereinafter, the signal with an inverted polarity referred to as an inverted signal. When High is supplied to the data line43, for example, Low is supplied to its paired complementary data line45. When Low is supplied to the data line43, High is supplied to its paired complementary data line45.

The gate of the second transistor32and the gate of the complementary second transistor37are electrically connected to the scan line42. The second transistor32and the complementary second transistor37are simultaneously switchable between an ON-state and an OFF-state depending on the scan signal supplied to the scan line42. The scan signal includes the selection signal and the non-selection signal. Each of the second transistor32and the complementary second transistor37is a selecting transistor for the pixel circuit41.

When the selection signal is supplied to the scan line42, the second transistor32and the complementary second transistor37are selected and both turned into the ON-state. As a result, the data line43and the output terminal25of the first inverter61of the memory circuit60are brought into electrical communications, and at the same time, the complementary data line45and the output terminal27of the second inverter62of the memory circuit60are brought into electrical communications. Thus, an image signal is written to the input terminal28of the second inverter62from the data line43via the second transistor32, and an inverted signal relative to the image signal is written to the input terminal26of the first inverter61from the complementary data line45via the complementary second transistor37and stored therein.

The digital image signal stored in the memory circuit60is maintained in a stable state until the second transistor32and the complementary second transistor37are next selected and brought into the ON-state, and subsequently the image signal and the inverted signal relative to the image signal are newly written from the data line43and the complementary data line45, respectively.

For the memory circuit60to be rewritten quickly and reliably it is required that the ON-resistance of the second transistor32is lower than the ON-resistance of the first transistor31and the ON-resistance of the fourth transistor34. In order to meet this requirement the polarity, dimensions (gate length, gate width, and the like), driving conditions (potential of the selection signal), and the like, of the first, second, and fourth transistors31,32, and34are designed. Likewise, the polarity, dimensions, driving conditions, and the like of the fifth, sixth, and complementary second transistors35,36, and37are designed so that the ON-resistance of the complementary second transistor37is lower than the ON-resistance of the fifth transistor35and the ON-resistance of the sixth transistor36. This allows the signal stored in the memory circuit60to be rewritten quickly and reliably.

The electro-optical device10according to one exemplary embodiment also includes a plurality of enable lines44in the display region E. The gate of the third transistor33is electrically connected to the enable line44. The third transistor33is switchable between an ON-state and an OFF-state depending on the enable signal which is the active signal or the inactive signal and which is supplied to the enable line44.

When the active signal is supplied to the enable line44, the third transistor33is turned into the ON-state. While the third transistor33is in the ON-state, the light emitting element20is allowed to emit light. On the other hand, when the inactive signal is supplied to the enable line44, the third transistor33is turned into the OFF-state. While the third transistor33is in the OFF-state, the memory circuit60is allowed to rewrite the stored image signal without false operation. This is described below.

In one exemplary embodiment, since the enable line44and the scan line42are independent from each other for each pixel circuit41, the second transistor32and the third transistor33can operate independently from each other. As a result, the third transistor33can be always in the OFF-state when the second transistor32is turned into the ON-state.

For an image signal being written to the memory circuit60, after the third transistor33is turned into the OFF-state, the second transistor32and the complementary second transistor37are then turned into the ON-state to supply the image signal and the inverted signal relative to the image signal to the memory circuit60. While the second transistor32is in the ON-state, the third transistor33is in the OFF-state. As a result the light emitting element20does not emit light while the image signal is being written to the memory circuit60. Consequently, the image signal can be reliably rewritten in the memory circuit60.

Subsequently to cause the light emitting element20to emit light, after the second transistor32and the complementary second transistor37are turned into the OFF-state, the third transistor33is then turned into the ON-state. At this time, the electrical conductive path that leads from the high potential line47(VDD) to the low potential line46(VSS) through the light emitting element20, the third transistor33, and the first transistor31is formed and allows a current to flow through the light emitting element20.

The image signal and the inverted signal relative to the image signal are not supplied to the memory circuit60while the light emitting element20are emitting light. This is because the second transistor32and the complementary second transistor37are in the OFF-state during the third transistor33being in the ON-state. This ensures that the image signal stored in the memory circuit60is not erroneously rewritten. As a result, a high-quality image without any display errors can be achieved.

Even using the digital driving method, if the third transistor33is not provided, or if the third transistor33is in the ON-state when the image signal stored in the memory circuit60is rewritten, the possibility of wrong operation due to a failure in rewriting the image signal in the memory circuit60and the resultant high power consumption will be increased. Even when the image signal in the memory circuit60is rewritten correctly, it may take an undesirably long time to rewrite the image signal. This is described below.

To understand the problem described above, we consider an example of imaginary circuit in which the pixel circuit41illustrated inFIG. 8does not possess the third transistor33. Since the third transistor33does not exist in the imaginary circuit, the cathode23of the light emitting element20is electrically connected to the output terminal25of the first inverter61. This imaginary circuit is then simulated with the assumption that High=VDD=5 V, Low=VSS=0 V, the logic inversion voltage for the inverters61,62is 2.5 V, and the threshold voltage for emission of the light emitting element20is 2 V. Under this condition we consider a situation where the output terminal25of the first inverter61is to be rewritten from high (5 V) to Low (0 V).

To rewrite the output terminal25of the first inverter61of the memory circuit60in the imaginary circuit to Low, the data line43is electrically connected to the low potential line46(VSS) via a transistor (not illustrated). In this state, when the second transistor32is turned into the ON-state, the potential at the output terminal25starts decreasing from 5 V (High). When the potential at the output terminal25is reduced down to 3 V, the potential difference between the anode21and the cathode23of the light emitting element20becomes the threshold voltage 2 V or higher. Consequently, a current begins to flow through the light emitting element20to cause the light emitting element20to start emitting light in the imaginary circuit.

This means the electrical conductive path that leads from the high potential line47(VDD) to the low potential line46(VSS) through the light emitting element20, the second transistor32, and the data line43, is formed in the imaginary circuit. As a result, a potential drop at the output terminal25is inhibited. For this reason, in the imaginary circuit not only will it take a considerable amount of time to rewrite the image signal in the memory circuit60, but the current consumption will also increase.

In a worst scenario, a selection period ends and the second transistor32is turned into the OFF-state before the potential at the output terminal25become lower than the logic inversion voltage (2.5 V) of the first inverter61in the imaginary circuit. In this state, rewriting from High to Low at the output terminal25has failed. As a result, a correct image signal is not written to the memory circuit60in the imaginary circuit, leading to erroneous display or low quality image display.

In contrast, in one exemplary embodiment, when the second transistor32is turned into the ON-state to rewrite the image signal in the memory circuit60, the third transistor33is in the OFF-state to disconnect the electric path between the high potential line47and the output terminal25of the memory circuit60(the first inverter61) through the light emitting element20. As a result, the problems described above are avoided and the memory circuit60is reliably rewritten in a short time with a low power consumption. Therefore, a high-quality image without any display errors can be achieved.

Furthermore, while the image signal in the memory circuit60is rewritten, the third transistor33is in the OFF-state to prevent the light emitting element20from emitting light, that is, the light emitting element20is in a non-emission state. After the second transistor32is turned into the OFF-state, the third transistor33is turned into the ON-state to allow the light emitting element20to be in an emission state or a non-emission state depending on the image signal. Accordingly, the problem that the potential change during the period for rewriting the memory circuit60affects the light emitting element20can be prevented. Therefore, non-emission of light and emission of light of the light emitting element20is precisely controlled in a time-division manner, and thus accurate grey scale is displayed by the time-division digital driving method.

Characteristics of Transistor

In the electro-optical device10according to one exemplary embodiment, it is preferable that the ON-resistance of the third transistor33is sufficiently lower than the ON-resistance of the light emitting element20. The sufficiently lower ON-resistance of the third transistor33means a driving condition that allows linear operation of the third transistor33. Specifically, the ON-resistance of the third transistor33is one hundredth or less, and preferably, one thousandth or less of the ON-resistance of the light emitting element20. Such characteristics enable the third transistor33to linear operation when the light emitting element20emits light.

It is also preferable that the ON-resistance of the first transistor31is lower than or equal to the ON-resistance of the third transistor33. If the ON-resistance of the third transistor33is sufficiently lower than the ON-resistance of the light emitting element20, and if the ON-resistance of the first transistor31is lower than or equal to the ON-resistance of the third transistor33, the ON-resistance of the first transistor31will be also sufficiently lower than the ON-resistance of the light emitting element20.

Thus, with the ON-resistance of the first transistor31and the ON-resistance of the third transistor33being sufficiently lower than the ON-resistance of the light emitting element20, both the first transistor31and the third transistor33operate linearly when the light emitting element20is brought into an ON-state to emit light. Accordingly, most of the potential difference occurring along the path from the high potential line47(VDD) to the low potential line46(VSS) across the light emitting element20, the third transistor33, and the first transistor31is applied to the light emitting element20. In other words, the potential difference between the first potential and the second potential, namely most of the power-supply voltage, is applied to the light emitting element20. As a result, the light emitting element20, when emitting light, is less susceptible to the variation in the threshold voltage and the like of the first transistor31and the third transistor33.

If the ON-resistance of the third transistor33is lower than or equal to one hundredth of the ON-resistance of the light emitting element20, the ON-resistance of the first transistor31will be also lower than or equal to one hundredth of the ON-resistance of the light emitting element20. In this case, nearly 99% or greater of the power-supply voltage is applied to the light emitting element20, such that the potential drop in the first transistor31and the third transistor33is about 1% or less of the total power-supply voltage. Thus, variation in the threshold voltage of both the transistors31and33on the characteristics of light emission of the light emitting element20tend to only have slight effect. As a result an image with a very small variation in brightness and a slight shift in grey scale among the pixels49is displayed.

Furthermore, it is preferable that the ON-resistance of the first transistor31is lower than or equal to half the ON-resistance of the third transistor33. In this case, the ON-resistance of the first transistor31is lower than or equal to one two-hundredth of the ON-resistance of the light emitting element20.

When the ON-resistance of the third transistor33is lower than or equal to one thousandth of the ON-resistance of the light emitting element20, the ON-resistance of the first transistor31is also lower than or equal to one thousandth of the ON-resistance of the light emitting element20. When the ON-resistance of the first transistor31is lower than or equal to half the ON-resistance of the third transistor33, the ON-resistance of the first transistor31is lower than or equal to one two-thousandth of the ON-resistance of the light emitting element20. As a result, the series resistance of both the transistors31and33is lower than or equal to about one thousandth of the ON-resistance of the light emitting element20.

In this case, about 99.9% or greater of the power-supply voltage is applied to the light emitting element20, such that the potential drop in both the transistors31and33is about 0.1% or less. Thus, effects of variation in the threshold voltage of both the transistors31and33on the characteristics of light emission of the light emitting element20are almost negligible. As a result, a high-quality image display can be achieved in which the variation in brightness and the grey scale shift among the pixels49are further decreased.

The ON-resistance of a transistor depends on the polarity, gate length, gate width, threshold voltage, thickness of the gate-insulating film, and the like of the transistor. In one exemplary embodiment, the polarity, gate length, gate width, threshold voltage, thickness of the gate-insulating film, and the like of each transistor are determined to satisfy the conditions described above. This is described below.

In one exemplary embodiment, an organic EL element is used as the light emitting element20, and the transistors that include the first transistor31and the third transistor33are formed on the element substrate11, which is a single-crystal silicon wafer. The current-voltage characteristics of the light emitting element20are represented approximately by Equation (2):

In Equation (2), IELis a current flowing through the light emitting element20, VELis a voltage applied to the light emitting element20, LELis the length of the light emitting element20, WELis the width of the light emitting element20, J0is the current density coefficient of the light emitting element20, Vtmis the coefficient voltage of the light emitting element20having a temperature dependence, and V0is a threshold voltage for emission of light of the light emitting element20. Vtmis a constant voltage under a constant temperature.

Using the power-supply voltage VPand the potential drop Vdsoccurring in both the first transistor31and the third transistor33, the following voltage relation holds: VEL+Vds=VP. In one exemplary embodiment, the followings were provided: LEL=11 micrometers (μm), WEL=3 micrometers (μm), J0=1.449 milliamperes per square centimeter (mA/cm2), V0=2.0 volts (V), and Vtm=0.541 volt (V).

Provided that the power-supply voltage VPis 5 V and the first transistor31and the third transistor33operate linearly, the current-voltage characteristics of the light emitting element20at Vdsbeing in the vicinity of 0 V is approximated by Equation (3):
IEL=k(VEL−V1)=−kVds+k(VP−V1)≡−kVds+I0(3)

In the case of one exemplary embodiment, the coefficient k defined by Equation (3) is such that: k=2.26×10−7(Ω−1). I0is the amount of current when all of the power-supply voltage VPapplies to the light emitting element20, and I0=1.2216×10−7(A). In Equation (3), V1is a coefficient obtained by linear approximation of the current-voltage characteristics of the light emitting element20.

A drain current Idsof the first transistor31and the third transistor33is represented by Equation (4):

In Equation (4), the first transistor31and the third transistor33are the same conductive type and are combined to a single transistor with the same gate width and the same gate-insulating film. In Equation (4), W is the gate width of the transistors31and33, L1and L3are the gate length of the first transistor31and the gate length of the third transistor33, respectively, ε0is the permittivity in vacuum, εoxis the dielectric constant of the gate-insulating film, toxis the thickness of the gate insulating film, μ is the mobility of both the transistors31and33, Vgsis a gate voltage, Vdsis a drain voltage that corresponds to the potential drop in both the transistors31and33, and Vthis the threshold voltage of both the transistors31and33.

In one exemplary embodiment, W=0.5 micrometer (μm), L1=0.5 micrometer (μm), L3=1.0 micrometer (μm), tox=20 nanometers (nm), μ=240 square centimeters per voltage per second (cm2/Vs), Vth=0.36 V, and Vgs=5 V−Vds/6. Vgsis a difference between the gate potential (VDD=5V) and the source potential. The potential drop in the first transistor31is about one third of the potential drop Vdsin both the transistors31and33, so that the source potential is set to an average of the source potential of the first transistor31of 0 V and the source potential of the third transistor33of Vds/3.

Under such conditions, a voltage for causing the light emitting element20to emit light is a voltage that satisfies IEL=Idsusing Equation (2) and Equation (4). In one exemplary embodiment, the followings were provided: VP=5 V, Vds=0.0019 V, VEL=4.9981 V, and IEL=Ids=1.2173×10−7A. The ON-resistance of the combined transistor was 1.56×104Ω and the ON-resistance of the light emitting element20was 4.11×107Ω.

Of the ON-resistance of the combined transistor, the ON-resistance of the third transistor33is about 1.04×104Ω and the ON-resistance of the first transistor31is 0.52×104Ω. Accordingly, the ON-resistance of the third transistor33is about one two-thousandth of the light emitting element20. This value is smaller than one thousandth of the ON-resistance of the light emitting element20. Thus most of the power-supply voltage VPis applied to the light emitting element20. Under such conditions, even when the threshold voltage of both the transistors31and33varies by 33% (even when the threshold voltage of both the transistors31and33varies between 0.24 V and 0.47 V), the following parameters remain unchanged: Vds=0.0019 V, VEL=4.9981 V, and IEL=Ids=1.2173×10−7A. In that example, even when the threshold voltage of both the transistors31and33varies between 0.24 V and 0.47 V, Vds, VEL, and IEL=Idsare unchanged.

Normally the threshold voltage of the transistor does not vary as significantly as above. Therefore, by setting the ON-resistance of the third transistor33to be lower than or equal to about one thousandth of the ON-resistance of the light emitting element20, the effects of the variation in the threshold voltage of the first transistor31and the third transistor33on the luminous intensity emitted from the light emitting element20is substantially eliminated.

By simultaneously solving Equation (3) and Equation (4) with IEL=Ids, the effects of variation in the threshold voltage of the first transistor31and the third transistor33on the current IEL=Idscan be approximated by Equation (5):

Since I0is the amount of current when all of the power-supply voltage VPis applied to the light emitting element20, Equation (5) indicates that the large value of Z defined by Equation (4) causes the light emitting element20to emit light at around the power-supply voltage VP. In other words, the larger the value of Z, the less the intensity of light emitted from the light emitting element20is affected by variation in the threshold voltage of the transistor.

In the case of one exemplary embodiment, since k/Z is as small as k/Z=1.636×10−2V, the second term on the left side of Equation (5) becomes k/(Z(Vgs−Vth))=3.53×10−3, which is less than 0.01 (1%). As a result, the current, which is proportional to the luminous intensity, flowing through the light emitting element20during its emission state is not affected by the variation in the threshold voltage of both the transistors31and33. Therefore, setting a value of k/(Z(Vgs−Vth)) to less than 0.01 (1%) makes the luminance of the light emitting element20independent from the variation in the threshold voltage of both the transistors31and33.

In one exemplary embodiment, the ON-resistance of the first transistor31is lower than or equal to the ON-resistance of the third transistor33. As described above, it is preferable that the ON-resistance of the first transistor31is lower than or equal to half the ON-resistance of the third transistor33. The polarities and dimensions (gate lengths, gate widths and the like) of the first transistor31and the third transistor33, driving conditions such as the potential of the enable signal in the active state, and the like are designed to satisfy the condition that the ON-resistance of the first transistor31is lower than or equal to half the ON-resistance of the third transistor33.

Setting the ON-resistance of the first transistor31to be lower than or equal to the ON-resistance of the third transistor33means that the electrical conductance of the first transistor31is higher than the electrical conductance of the third transistor33. Furthermore, setting the ON-resistance of the first transistor31to be lower than or equal to half the ON-resistance of the third transistor33means that the electrical conductance of the first transistor31is two times or higher the electrical conductance of the third transistor33. These configurations reduce the risk that the image signal stored in the memory circuit60is erroneously rewritten when the light emitting element20emits light. This is described below.

We consider a situation where the third transistor33is switched from the OFF-state to the ON-state to cause the light emitting element20to start emitting light while the potential of the output terminal25of the memory circuit (the first inverter61) is Low. Under this situation, if the ON-resistance of the first transistor31is higher than the ON-resistance of the third transistor33and if the ON-resistance of the light emitting element20is relatively low, there will be a risk that the potential of the output terminal25, i.e. the drain potential of the first transistor31, increases and exceeds the logic inversion voltage of the first inverter61.

In contrast, in one exemplary embodiment, since the ON-resistance of the first transistor31is lower than or equal to the ON-resistance of the third transistor33, even when the ON-resistance of the light emitting element20is as low as zero, the potential of the output terminal25will not increase up to half the power-supply potential and will not exceed the logic inversion potential of the first inverter61. This is because the logic inversion potential of a typical inverter is approximately equal to half the power-supply potential. As described in one exemplary embodiment, setting the ON-resistance of the first transistor31to be lower than or equal to the ON-resistance of the third transistor33substantially eliminate the risk that the image signal stored in the memory circuit60is rewritten when the light emitting element20emits light.

If the ON-resistance of the first transistor31is higher than the ON-resistance of the third transistor33, the potential at the output terminal25will increase from Low, which is close to VSS. Since the source of the third transistor33is electrically connected to the output terminal25, the potential at the output terminal25is the source potential of the third transistor33. Accordingly, when the potential at the output terminal25increases from Low, the voltage between the gate and the source of the third transistor33will decrease and the ON-resistance of the third transistor33will increase. As a result, a risk that the third transistor33does not operate linearly appears. In other words, the variation in the threshold voltage of the third transistor33may lead to variation in the luminous intensity at the light emitting element20.

In contrast, as described in one exemplary embodiment, when the ON-resistance of the first transistor31is lower than the ON-resistance of the third transistor33, linear operation of the third transistor33necessarily causes the first transistor31to be linearly operated. Thus, the effects of the variation in the threshold voltage of the third transistor33on the luminance of the light emitting element20are eliminated as described above. Therefore, with the configuration of the pixel circuit41according to one exemplary embodiment, an electro-optical device10that can display a high-quality image without any display errors is achieved.

Driving Method of Pixel Circuit

A driving method of the pixel circuit in the electro-optical device10according to one exemplary embodiment will now be described with reference toFIG. 9.FIG. 9illustrates a driving method of the pixel circuit according to one exemplary embodiment. InFIG. 9, the horizontal axis is the time axis and includes a first period (non-display period) and a second period (display period). The first period corresponds to P1(P1-1to P1-6) illustrated inFIG. 7. The second period corresponds to P2(P2-1to P2-6) illustrated inFIG. 7.

In the vertical axis inFIG. 9, Scan1to Scan M represent the scan signals supplied to the scan lines42in the first row to the M-th row of the M scan lines42(refer toFIG. 5), respectively. The scan signal includes a scan signal in the selection-state (the selection signal) and a scan signal in the non-selection-state (the non-selection signal). Enb represents the enable signal supplied to the enable line44(refer toFIG. 5). The enable signal includes an enable signal in the active state (the active signal) and an enable signal in the inactive state (the inactive signal).

As described with reference toFIG. 7, the single field (F) during which a single image is displayed is divided into the plurality of sub-fields (SF), and each sub-field (SF) includes the first period (the non-display period) and the second period (the display period) that starts immediately after the end of the first period. The first period (the non-display period) is a signal write period, during which an image signal is written to the memory circuit60(refer toFIG. 8) in each pixel circuit41(refer toFIG. 5) arranged in the display region E. The second period (the display period) is a period during which that the light emitting element20(refer toFIG. 8) can emit light in each pixel circuit41arranged in the display region E.

As illustrated inFIG. 9, in the electro-optical device10according to one exemplary embodiment, the inactive signal is supplied to all of the enable lines44during the first period (the non-display period). While the inactive signal is supplied to the enable line44, the third transistor33(refer toFIG. 8) is in the OFF-state, and thus the light emitting elements20are in a state of non-emission of light in all of the pixel circuits41arranged in the display region E.

In the first period in each sub-field (SF), the selection signal is supplied to one of the scan lines42. When the selection signal is supplied to the scan line42, the second transistor32and the complementary second transistor37(refer toFIG. 8) in a selected pixel circuit41are turned into the ON-state. Thus, in the selected pixel circuit41, an image signal is written to the memory circuit60from the data line43and the complementary data line45(refer toFIG. 8). In this way, the image signal is written to and stored in the memory circuit60in each pixel circuit41during the first period.

In the second period (the display period), the active signal is supplied to all of the enable lines44. When the active signal is supplied to each enable line44, the third transistor33is turned into the ON-state, thus allowing each light emitting element20in all of the pixel circuits41arranged in the display region E to emit light. During the second period, the non-selection signal that makes each second transistor32be in the OFF-state is supplied to all of the scan lines42. Thus, the image signal written in the first period is maintained in the memory circuit60in each pixel circuit41in this sub-field (SF).

In this way, in one exemplary embodiment, the first period (the non-display period) and the second period (the display period) is separately controlled, thus making it possible to display grey scales in a digital time-division driving manner. In addition, the second period can be set to be shorter than the first period, and thus an image with a larger number of grey scales can be displayed.

Furthermore, the enable signal supplied to the enable lines44is shared among the plurality of pixel circuits41, such that driving the electro-optical device10can be facilitated. In a case of digital driving without the first period, highly complicated driving is required to make the light emission period shorter than one vertical period within which selection of each of the plurality of scan lines42is completed. In contrast, in one exemplary embodiment, the enable signal supplied to the enable lines44is shared among the plurality of pixel circuits41. Thus, even when there is a sub-field (SF) for which the light emission period is shorter than one vertical period within which selection of each of the plurality of scan lines42is completed, the electro-optical device10can be readily driven by simply shortening the second period.

A configuration of a pixel circuit according to First Exemplary Embodiment will now be described using other examples and modified examples. In the description of the following examples and modified examples, the differences from the examples and the modified examples that have already described will be described: in the drawings, like numerals are assigned to the same components as those in the examples and modified examples already described and their description will be omitted. The driving method of the pixel circuit that will be described in the following examples and modified examples is the same as Example 1 and accordingly the same advantageous effect as Example 1 can be obtained in the configuration of the following examples and modified examples.

MODIFIED EXAMPLE 1

First, a pixel circuit according to Modified Example 1, which is a modified example of Example 1, will be described.FIG. 10illustrates a configuration of the pixel circuit according to Modified Example 1. As illustrated inFIG. 10, a pixel circuit41A according to Modified Example 1 differs from the pixel circuit41according to First Exemplary Embodiment in that the third transistor33is arranged on the higher potential side than the light emitting element20with the other configuration being the same.

In the pixel circuit41A according to Modified Example 1, the drain of the third transistor33is electrically connected to the high potential line47that serves as the second potential line, and the source of the third transistor33is electrically connected to the anode21of the light emitting element20. The cathode23of the light emitting element20is electrically connected to the output terminal25of the memory circuit60(the first inverter61), that is, the drain of the first transistor31.

In Modified Example 1, since the third transistor33is arranged on the high potential side with respect to the light emitting element20, it is preferable that the potential of the active signal supplied to the gate of the third transistor33from the enable line44is set to be higher, e.g. about 10 V, than that of Example 1 in order to prevent the voltage between the gate and the source of the third transistor33from decreasing during the second period and in order to prevent the third transistor33from failing to be linearly operated.

A configuration of a pixel circuit according to Example 2 will now be described with reference toFIG. 11.FIG. 11illustrates the configuration of the pixel circuit according to Example 2. As illustrated inFIG. 11, a pixel circuit41B according to Example 2 differs from the pixel circuits41and41A according to Example 1 and Modified Example 1 in that the third transistor33A is a P-type transistor.

The pixel circuit41B according to Example 2 includes the light emitting element20, the memory circuit60that includes the first transistor31, the second transistor32, the third transistor33A, and the complementary second transistor37. The third transistor33A, which is a P-type transistor, is arranged in series with the light emitting element20between the output terminal25of the first inverter61, that is, the drain of the first transistor31, and the high potential line47that serves as the second potential line.

The third transistor33A is arranged on the higher potential side than the light emitting element20. The source of the third transistor33A is electrically connected to the high potential line47that serves as the second potential line. The drain of the third transistor33A is electrically connected to the anode21of the light emitting element20. The cathode23of the light emitting element20is electrically connected to the output terminal25of the memory circuit60, i.e. the first inverter61, that is, the drain of the first transistor31.

In Example 2, with regard to the enable signal supplied to the third transistor33A from the enable line44, the second low potential VSS2(VSS2=VSS=0 V) is supplied as the active signal and the second high potential VDD2(VDD2=VDD=5 V) is supplied as the inactive signal for example.

During the first period (the non-display period), when the selection signal, which is supplied from the scan line42, turns the second transistor32and the complementary second transistor37into the ON-state, an image signal from the data line43and the complementary data line45is written to and stored in the memory circuit60. During the second period (the display period), when the active signal supplied from the enable line44turns the third transistor33A into the ON-state, the path that leads from the high potential line47(VDD) to the low potential line46(VSS) through the third transistor33A, the light emitting element20, and the first transistor31can be controlled by the first transistor31. As a result, the light emitting element20emits or does not emit light depending on the image signal.

MODIFIED EXAMPLE 2

A configuration of a pixel circuit according to Modified Example 2, which is a modified example of Example 2, will now be described with reference toFIG. 12.FIG. 12illustrates the configuration of the pixel circuit according to Modified Example 2. As illustrated inFIG. 12, a pixel circuit41C according to Modified Example 2 differs from the pixel circuit41B according to Example 2 in that the third transistor33A is arranged on the lower potential side than the light emitting element20.

In the pixel circuit41C according to Modified Example 2, the source of the third transistor33A is electrically connected to the cathode23of the light emitting element20, and the drain of the third transistor33A is electrically connected to the output terminal25of the memory circuit60(the first inverter61), that is, the drain of the first transistor31. The anode21of the light emitting element20is electrically connected to the high potential line47that serves as the second potential line.

In Modified Example 2, since the third transistor33A is arranged on the low potential side with respect to the light emitting element20, it is preferable that the potential of the active signal supplied to the gate of the third transistor33A from the enable line44is set to be lower than that of Example 1, e.g. about −5 V, in order to prevent the voltage between the gate and the source of the third transistor33A from decreasing during the second period and in order to prevent the third transistor33A from failing to be operated linearly.

A configuration of a pixel circuit according to Example 3 will now be described with reference toFIG. 13.FIG. 13illustrates the configuration of the pixel circuit according to Example 3. As illustrated inFIG. 13, a pixel circuit41D according to Example 3 differs from the pixel circuit41according to Example 1 in that a first transistor31A and a fifth transistor35A are each a P-type transistor, and a fourth transistor34A and a sixth transistor36A are each an N-type transistor.

The pixel circuit41D according to Example 3 includes the light emitting element20, a memory circuit60A that includes the first transistor31A, the second transistor32, the third transistor33, and the complementary second transistor37. The memory circuit60A includes a first inverter61A and a second inverter62A. In Example 3, the high potential line47serves as the first potential line, and the low potential line46serves as the second potential line.

The first inverter61A includes the P-type first transistor31A and the N-type fourth transistor34A. The source of the first transistor31A is electrically connected to the high potential line47that serves as the first potential line. The first transistor31A is a component of the first inverter61A and is also a driving transistor for the light emitting element20. The source of the fourth transistor34A is electrically connected to the low potential line46that serves as the second potential line.

The second inverter62A includes the P-type fifth transistor35A and the N-type sixth transistor36A. The source of the fifth transistor35A is electrically connected to the high potential line47that serves as the first potential line. The source of the sixth transistor36A is electrically connected to the low potential line46that serves as the second potential line.

The third transistor33is arranged in series with the light emitting element20between the output terminal25of the first inverter61A, that is, the drain of the first transistor31A, and the low potential line46that serves as the second potential line. The third transistor33is arranged on the lower potential side than the light emitting element20. More specifically, the source of the third transistor33is electrically connected to the low potential line46, and the drain of the third transistor33is electrically connected to the cathode23of the light emitting element20. The anode21of the light emitting element20is electrically connected to the drain of the first transistor31A.

In Example 3, as in Example 1, to the third transistor33from the enable line44, the enable signal of the second high potential VDD2(VDD2=VDD=5 V) is supplied as the active signal, and the enable signal of the second low potential VSS2(VSS2=VSS=0 V) is supplied as the inactive signal.

During the first period (the non-display period), when the selection signal, which is supplied from the scan line42, turns the second transistor32and the complementary second transistor37into the ON-state, an image signal from the data line43and the complementary data line45is written to and stored in the memory circuit60A. During the second period (the display period), when the active signal, which is supplied from the enable line44, turns the third transistor33into the ON-state, the path that leads from the high potential line47(VDD) to the low potential line46(VSS) through the first transistor31A, the light emitting element20, and the third transistor33can be controlled by the first transistor31. As a result, the light emitting element20emits or does not emit light depending on the image signal.

MODIFIED EXAMPLE 3

A configuration of a pixel circuit according to Modified Example 3, which is a modified example of Example 3, will now be described with reference toFIG. 14.FIG. 14illustrates the configuration of the pixel circuit according to Modified Example 3. As illustrated inFIG. 14, a pixel circuit41E according to Modified Example 3 differs from the pixel circuit41D according to Example 3 in that the third transistor33is arranged on the higher potential side than the light emitting element20.

In the pixel circuit41E according to Modified Example 3, the drain of the third transistor33is electrically connected to the output terminal25of the first inverter61A, that is, the drain of the first transistor31A, and the source of the third transistor33is electrically connected to the anode21of the light emitting element20. The cathode23of the light emitting element20is electrically connected to the low potential line46that serves as the second potential line.

In Modified Example 3, since the third transistor33is arranged on the high potential side with respect to the light emitting element20, it is preferable that the voltage of the active signal, which is supplied to the gate of the third transistor33from the enable line44, is set to be higher, e.g. about 10 V, than that of Example 3 in order to prevent the voltage between the gate and the source of the third transistor33from decreasing during the second period and in order to prevent the third transistor33from failing to be operated linearly.

A configuration of a pixel circuit according to Example 4 will now be described with reference toFIG. 15.FIG. 15illustrates the configuration of the pixel circuit according to Example 4. As illustrated inFIG. 15, a pixel circuit41F according to Example 4 differs from the pixel circuit41D according to Example 3 in that the third transistor33A is a P-type transistor.

The pixel circuit41F according to Example 4 includes the light emitting element20, the memory circuit60A that includes the first transistor31A, the second transistor32, the third transistor33A, and the complementary second transistor37. The third transistor33A, which is a P-type transistor, is arranged in series with the light emitting element20between the output terminal25of the first inverter61, that is, the drain of the first transistor31A, and the low potential line46that serves as the second potential line.

The third transistor33A is arranged on the higher potential side than the light emitting element20. The source of the third transistor33A is electrically connected to the drain of the first transistor31A. The drain of the third transistor33A is electrically connected to the anode21of the light emitting element20. The cathode23of the light emitting element20is electrically connected to the low potential line46.

In Example 4, with regard to the enable signal supplied to the third transistor33A from the enable line44the enable signal of the second low potential VSS2(VSS2=VSS=0 V) is supplied as the active signal, and the enable signal of the second high potential VDD2(VDD2=VDD=5 V) is supplied as the inactive signal, for example.

During the first period (the non-display period), when the selection signal, which is supplied from the scan line42, turns the second transistor32and the complementary second transistor37into the ON-state, an image signal from the data line43and the complementary data line45is written to and stored in the memory circuit60A. During the second period (the display period), when the active signal, which is supplied from the enable line44, turns the third transistor33into the ON-state, the path that leads from the high potential line47(VDD) to the low potential line46(VSS) through the first transistor31A, the third transistor33A, and the light emitting element20can be controlled by the first transistor31. As a result, the light emitting element20emits or does not emit light depending on the image signal.

MODIFIED EXAMPLE 4

A configuration of a pixel circuit according to Modified Example 4, which is a modified example of Example 4, will now be described with reference toFIG. 16.FIG. 16illustrates the configuration of the pixel circuit according to Modified Example 4. As illustrated inFIG. 16, a pixel circuit41G according to Modified Example 4 differs from the pixel circuit41F according to Example 4 in that the third transistor33A is arranged on the lower potential side than the light emitting element20.

In the pixel circuit41G according to Modified Example 4, the source of the third transistor33A is electrically connected to the cathode23of the light emitting element20, and the drain of the third transistor33A is electrically connected to the low potential line46that serves as the second potential line. The anode21of the light emitting element20is electrically connected to the output terminal25of the first inverter61A, that is, the drain of the first transistor31A.

In Modified Example 4, since the third transistor33A is arranged on the low potential side with respect to the light emitting element20, it is preferable that the voltage of the active signal, which is supplied to the gate of the third transistor33A from the enable line44, is set to be lower, e.g. about −5 V, than that of Example 1 in order to prevent the voltage between the gate and the source of the third transistor33A from decreasing during the second period and in order to prevent the third transistor33A from failing to be operated linearly.

Second Exemplary Embodiment

A configuration of an electro-optical device according to Second Exemplary Embodiment will now be described. The electro-optical device according to Second Exemplary Embodiment, whose illustration is omitted, differs from the electro-optical device10according to First Exemplary Embodiment in that the enable line drive circuit54and the enable lines44(refer toFIG. 5) do not exist. Accordingly, a configuration of a pixel circuit according to Second Exemplary Embodiment also differs from the configuration of the pixel circuit according to First Exemplary Embodiment. Specifically, the pixel circuit according to Second Exemplary Embodiment differs from that according to First Exemplary Embodiment in that the gate of the second transistor and the gate of the third transistor are electrically connected to the scan line, and the second transistor and the third transistor have polarities opposite to each other.

A configuration of the pixel circuit according to Second Exemplary Embodiment will now be described using a plurality of examples and modified examples. In the description of the following examples and modified examples, the differences from the examples and the modified examples that have already described will be described. In the drawings, like numerals are assigned to the same components as those in the examples and modified examples already described and their description will be omitted.

Configuration of Pixel Circuit

A configuration of a pixel circuit according to Example 5 will now be described with reference toFIG. 17.FIG. 17illustrates the configuration of the pixel circuit according to Example 5. As illustrated inFIG. 17, a pixel circuit71is provided for each of the sub-pixels48that are arranged to correspond to the respective intersections of the scan lines42and the data lines43. The scan line42, the data line43, and the complementary data line45correspond to each pixel circuit71. As described above, in Second Exemplary Embodiment, no enable line is provided but the scan lines42also function as the enable lines.

The pixel circuit71according to Example 5 includes the light emitting element20, the memory circuit60that includes the first transistor31, a second transistor32A, the third transistor33, and a complementary second transistor37A. The pixel circuit71according to Example 5 differs from the pixel circuit41according to Example 1 in that the gate of the third transistor33is electrically connected to the scan line42, and both the second transistor32A and the complementary second transistor37A are P-type transistors, which have an opposite polarity to the third transistor33.

The gates of the second transistor32A and the complementary second transistor37A, which are P-type transistors, are electrically connected to the scan line42, and the gate of the third transistor33, which is an N-type transistor, is also electrically connected to the scan line42. Accordingly, depending on the scan signal, which serves as the enable signal and which is supplied from the scan line42, when the second transistor32A and the complementary second transistor37A are turned into the ON-state, the third transistor33is turned into the OFF-state; by contrast when the second transistor32A and the complementary second transistor37A are turned into the OFF-state, the third transistor33is turned into the ON-state.

During the first period (the non-display period) a Low signal, e.g. 0 V, as the selection signal of the scan signal and also as the inactive signal of the enable signal is supplied from the scan line42to the transistors. Accordingly, the second transistor32A and the complementary second transistor37A are turned into the ON-state, thus, the data line43and the output terminal25of the memory circuit (the first inverter61) are electrically conducted while, at the same time, the complementary data line45and the output terminal27of the memory circuit60(the second inverter62) are electrically conducted. Consequently, an image signal and an inverted signal relative to the image signal are written to and stored in the memory circuit60. During the first period the light emitting element20is not allowed to emit light, because the third transistor33is in the OFF-state.

During the second period (the display period), a High signal, e.g. 5 V, as the non-selection signal of the scan signal and also as the active signal of the enable signal is supplied from the scan line42to the transistors. Accordingly, the third transistor33is turned into the ON-state, thus, the path that leads from the high potential line47(VDD) to the low potential line46(VSS) through the light emitting element20, the third transistor33, and the first transistor31can be electrically conducted. This means the light emitting element20can emit light. Furthermore, the image signal stored in the memory circuit60is maintained, because the second transistor32A and the complementary second transistor37A are in the OFF-state.

Now we consider an imaginary circuit in which the third transistor33is not provided in the pixel circuit71according to Example 5. In the imaginary circuit, since a current can flow through the light emitting element20while an image signal is written to the memory circuit60, it can be time-consuming to rewrite the image signal at the memory circuit60at best, but correct image signals may not be stored in the memory circuit60at worst. By contrast, in this Exemplary Embodiment, the third transistor33is in the OFF-state to prevent a current from flowing through the light emitting element20when an image signal is written to the memory circuit60. As a result, a high-quality image without any display errors can be achieved.

In this way, in the pixel circuit71according to Example 5 of Second Exemplary Embodiment, the gate of the second transistor32A and the gate of the third transistor33are electrically connected to the scan line42, and the second transistor32A (P-type) and the third transistor33(N-type) have polarities opposite to each other. With such a configuration, the scan line42also functions as the enable line, thus reducing the number of wires and the number of wiring layers.

In general a large number of wire layers increases the number of production steps for the electro-optical device (element substrate) and reduces the production yield, because one wire layer needs one interlayer insulating layer. With the configuration of Second Exemplary Embodiment, image display can be provided by digital driving even with a relatively small number of wire layers. Therefore, the number of production steps can be reduced and the production yield can be improved as compared to First Exemplary Embodiment. In addition, with a reduced number of light-shielding wires, the area that shields light can be decreased to achieve high resolution (fine pixels).

MODIFIED EXAMPLE 5

A pixel circuit according to Modified Example 5, which is a modified example of Example 5, will now be described.FIG. 18illustrates the configuration of the pixel circuit according to Modified Example 5. As illustrated inFIG. 18, a pixel circuit71A according to Modified Example 5 differs from the pixel circuit71according to Example 5 in that the third transistor33is arranged on the higher potential side than the light emitting element20.

In the pixel circuit71A according to Modified Example 5, the drain of the third transistor33is electrically connected to the high potential line47that serves as the second potential line, and the source of the third transistor33is electrically connected to the anode21of the light emitting element20. The cathode23of the light emitting element20is electrically connected to the output terminal25of the memory circuit60(the first inverter61), that is, the drain of the first transistor31.

In Modified Example 3, since the third transistor33is arranged on the high potential side with respect to the light emitting element20, it is preferable that the voltage of the scan signal, which is serving as the non-selection signal and also as the active signal, supplied to the gate of the third transistor33from the scan line42is set to be higher, e.g. about 10 V, than that of Example 5 in order to prevent the voltage between the gate and the source of the third transistor33from decreasing during the second period and in order to prevent the third transistor33from failing to be operated linearly.

A pixel circuit according to Example 6 will now be described.FIG. 19illustrates a configuration of the pixel circuit according to Example 6. As illustrated inFIG. 19, a pixel circuit71B according to Example 6 differs from the pixel circuit71according to Example 5 in that the third transistor33A is a P-type transistor, and both the second transistor32and the complementary second transistor37are N-type transistors.

The pixel circuit71B according to Example 6 includes the light emitting element20, the memory circuit60that includes the first transistor31, the second transistor32, the third transistor33A, and the complementary second transistor37. The third transistor33A, which is a P-type transistor, is arranged in series with the light emitting element20between the output terminal25of the first inverter61, i.e. the drain of the first transistor31, and the high potential line47that serves as the second potential line.

The third transistor33A is arranged on the higher potential side than the light emitting element20. The source of the third transistor33A is electrically connected to the high potential line47that serves as the second potential line. The drain of the third transistor33A is electrically connected to the anode21of the light emitting element20. The cathode23of the light emitting element20is electrically connected to the output terminal25of the memory circuit60(the first inverter61), that is, the drain of the first transistor31.

During the first period (the non-display period), a High signal, e.g. 5 V, as the selection signal of the scan signal and also as the inactive signal of the enable signal is supplied from the scan line42to transistors. Accordingly, the second transistor32and the complementary second transistor37are turned into the ON-state, such that an image signal from the data line43and the complementary data line45is written to and stored in the memory circuit60. During the first period the light emitting element20is not allowed to emit light, because the third transistor33A is in the OFF-state.

During the second period (the display period), a Low signal, e.g. 0 V, as the non-selection signal of the scan signal and also as the active signal of the enable signal is supplied from the scan line42to the transistors. Accordingly, the third transistor33A is turned into the ON-state, thus, the path that leads from the high potential line47(VDD) to the low potential line46(VSS) through the third transistor33A, the light emitting element20, and the first transistor31can be controlled by the first transistor31. As a result, the light emitting element20emits or does not emit light depending on the image signal. Furthermore, the image signal stored in the memory circuit60is maintained, because the second transistor32and the complementary second transistor37are in the OFF-state.

MODIFIED EXAMPLE 6

A configuration of a pixel circuit according to Modified Example 6, which is a modified example of Example 6, will now be described with reference toFIG. 20.FIG. 20illustrates the configuration of the pixel circuit according to Modified Example 6. As illustrated inFIG. 20, a pixel circuit71C according to Modified Example 6 differs from the pixel circuit71B according to Example 6 in that the third transistor33A is arranged on the lower potential side than the light emitting element20.

In the pixel circuit71C according to Modified Example 6, the source of the third transistor33A is electrically connected to the cathode23of the light emitting element20, and the drain of the third transistor33A is electrically connected to the output terminal25of the first inverter61, that is, the drain of the first transistor31. The anode21of the light emitting element20is electrically connected to the high potential line47.

In Modified Example 6, since the third transistor33A is arranged on the low potential side with respect to the light emitting element20, it is preferable that the voltage of the scan signal that is serving as the non-selection signal and also as the active signal supplied to the gate of the third transistor33A from the scan line42is set to be lower, e.g. about −5 V, than that of Example 6 in order to prevent the voltage between the gate and the source of the third transistor33A from decreasing during the second period and in order to prevent the third transistor33A from failing to be operated linearly.

A pixel circuit according to Example 7 will now be described.FIG. 21illustrates a configuration of the pixel circuit according to Example 7. As illustrated inFIG. 21, a pixel circuit71D according to Example 7 differs from the pixel circuit71according to Example 5 in that the first transistor31A and the fifth transistor35A are P-type transistors, and the fourth transistor34A and the sixth transistor36A are N-type transistors.

The pixel circuit71D according to Example 7 includes the light emitting element20, the memory circuit60A that includes the first transistor31A, the second transistor32A, the third transistor33, and the complementary second transistor37A. The memory circuit60A includes the first inverter61A and the second inverter62A. In Example 7, the high potential line47serves as the first potential line, and the low potential line46serves as the second potential line.

The first inverter61A includes the P-type first transistor31A and the N-type fourth transistor34A. The source of the first transistor31A is electrically connected to the high potential line47that serves as the first potential line. The first transistor31A is a component of the first inverter61A and is also a driving transistor for the light emitting element20. The source of the fourth transistor34A is electrically connected to the low potential line46that serves as the second potential line.

The second inverter62A includes the P-type fifth transistor35A and the N-type sixth transistor36A. The source of the fifth transistor35A is electrically connected to the high potential line47that serves as the first potential line. The source of the sixth transistor36A is electrically connected to the low potential line46that serves as the second potential line.

The third transistor33is arranged in series with the light emitting element20between the output terminal25of the first inverter61A, that is, the drain of the first transistor31A, and the low potential line46that serves as the second potential line. The third transistor33is arranged on the low potential side with respect to the light emitting element20. More specifically, the source of the third transistor33is electrically connected to the low potential line46, and the drain of the third transistor33is electrically connected to the cathode23of the light emitting element20. The anode21of the light emitting element20is electrically connected to the drain of the first transistor31A.

In Example 7, during the first period (the non-display period), when the Low signal that is serving as the selection signal and also as the inactive signal is supplied from the scan line42to the second transistor32A and the complementary second transistor37A, these transistors are turned into the ON-state, and an image signal from the data line43and the complementary data line45is written to and stored in the memory circuit60A. During the second period (the display period), when the High signal that is serving as the non-selection signal and also as the active signal is supplied from the scan line42to the third transistor33, the third transistor33is turned into the ON-state, thus, the path that leads from the high potential line47(VDD) to the low potential line46(VSS) through the first transistor31A, the light emitting element20, and the third transistor33can be controlled by the first transistor31A. As a result, the light emitting element20emits or does not emit light depending on the image signal.

MODIFIED EXAMPLE 7

A configuration of a pixel circuit according to Modified Example 7, which is a modified example of Example 7, will now be described with reference toFIG. 22.FIG. 22illustrates the configuration of the pixel circuit according to Modified Example 7. As illustrated inFIG. 22, a pixel circuit71E according to Modified Example 7 differs from the pixel circuit71D according to Example 7 in that the third transistor33is arranged on the higher potential side than the light emitting element20.

In the pixel circuit71E according to Modified Example 7, the drain of the third transistor33is electrically connected to the output terminal25of the first inverter61A, that is, the drain of the first transistor31A, and the source of the third transistor33is electrically connected to the anode21of the light emitting element20. The cathode23of the light emitting element20is electrically connected to the low potential line46that serves as the second potential line.

In Modified Example 7, since the third transistor33is arranged on the high potential side with respect to the light emitting element20, it is preferable that the voltage of the scan signal, which is serving as the non-selection signal and also as the active signal, and which is supplied to the gate of the third transistor33from the scan line42, is set to be higher, e.g. about 10 V, than that of Example 7 in order to prevent the voltage between the gate and the source of the third transistor33from decreasing during the second period and in order to prevent the third transistor33from failing to be operated linearly.

A configuration of a pixel circuit according to Example 8 will now be described with reference toFIG. 23.FIG. 23illustrates the configuration of the pixel circuit according to Example 8. As illustrated inFIG. 23, a pixel circuit71F according to Example 8 differs from the pixel circuit71D according to Example 7 in that the third transistor33A is a P-type transistor, and the second transistor32and the complementary second transistor37are each an N-type transistor.

The pixel circuit71F according to Example 8 includes the light emitting element20, the memory circuit60A that includes the first transistor31A, the second transistor32, the third transistor33A, and the complementary second transistor37. The third transistor33A, which is a P-type transistor, is arranged in series with the light emitting element20between the output terminal25of the first inverter61, that is, the drain of the first transistor31A, and the low potential line46that serves as the second potential line.

The third transistor33A is arranged on the higher potential side than the light emitting element20. The source of the third transistor33A is electrically connected to the drain of the first transistor31A. The drain of the third transistor33A is electrically connected to the anode21of the light emitting element20. The cathode23of the light emitting element20is electrically connected to the low potential line46.

In Example 8, during the first period (the non-display period), when a High signal that is serving as the selection signal and also as the inactive signal is supplied from the scan line42to the second transistor32and the complementary second transistor37, these transistors are turned into the ON-state, and an image signal from the data line43and the complementary data line45is written to and stored in the memory circuit60A. During the second period (the display period), when the Low signal that is serving as the non-selection signal and also as the active signal is supplied from the scan line42to the third transistor33, the third transistor33is turned into the ON-state, thus, the path that leads from the high potential line47(VDD) to the low potential line46(VSS) through the first transistor31A, the third transistor33A, and the light emitting element20, can be controlled by the first transistor31A. As a result, the light emitting element20emits or does not emit light depending on the image signal.

MODIFIED EXAMPLE 8

A configuration of a pixel circuit according to Modified Example 8, which is a modified example of Example 8, will now be described with reference toFIG. 24.FIG. 24illustrates the configuration of the pixel circuit according to Modified Example 8. As illustrated inFIG. 24, a pixel circuit71G according to Modified Example 8 differs from the pixel circuit71F according to Example 8 in that the third transistor33A is arranged on the lower potential side than the light emitting element20.

In the pixel circuit71G according to Modified Example 8, the source of the third transistor33A is electrically connected to the cathode23of the light emitting element20, and the drain of the third transistor33A is electrically connected to the low potential line46that serves as the second potential line. The anode21of the light emitting element20is electrically connected to the output terminal25of the first inverter61A, that is, the drain of the first transistor31A.

In Modified Example 8, since the third transistor33A is arranged on the low potential side with respect to the light emitting element20, it is preferable that the voltage of the scan signal that is serving as the non-selection signal and also as the active signal and is supplied to the gate of the third transistor33A from the scan line42is set to be lower, e.g. about −5 V, than that of Example 8 in order to prevent the voltage between the gate and the source of the third transistor33A from decreasing during the second period and in order to prevent the third transistor33A from failing to be operated linearl.

The exemplary embodiments (the examples and the modified examples) described above merely represent one aspect of the present disclosure and any variation and application may be possible within the scope of the disclosure. For example, the followings are modified examples other than those described above.

MODIFIED EXAMPLE 9

While the memory circuit60(or60A) in the pixel circuit of the exemplary embodiments (the examples and the modified examples) described above includes two inverters61and62(or61A and62A), the present disclosure is not limited to such an aspect. The memory circuit60(or60A) may be configured to include two or any greater even number of inverters.

MODIFIED EXAMPLE 10

While in the exemplary embodiments described above, an organic EL device in which the light emitting elements20each including an organic EL element are arranged in 720 rows×3840 (1280×3) columns on the element substrate11formed from a single-crystal semiconductor substrate (a single-crystal silicon wafer) is described as an exemplary electro-optical device, the electro-optical device of the present disclosure is not limited to such an aspect. For example, the electro-optical device may be configured with thin film transistors (TFTs) to serve as the transistors formed on the element substrate11formed from a glass substrate, or it may be configured with TFTs formed on a flexible substrate formed of polyimide and the like. Alternatively, the electro-optical device may be a micro LED display in which fine LED elements serving as light emitting elements are arranged at high density, or it may be a quantum dot display using a nano-sized semiconductor crystalline material as a light emitting element. The electro-optical device may use, as a color filter, quantum dots that can convert incident light into light with a different wavelength.

MODIFIED EXAMPLE 11

While in the exemplary embodiments described above, the see-through-type head-mounted display100with an integrated electro-optical device10is described as an exemplary electronic apparatus, the electro-optical device10of the present disclosure may be applied to other types of electronic apparatus including closed-type head-mounted displays. Other types of electronic apparatus include, for example, projectors, rear-projection televisions, direct-viewing televisions, cell phones, portable audio devices, personal computers, video camera monitors, automotive navigation devices, head-up displays, pagers, electronic organizers, calculators, wearable devices such as wristwatches, handheld displays, word processors, workstations, video phones, POS terminals, digital still cameras, signage displays, and the like.

The entire disclosure of Japanese Patent Application No. 2017-185867, filed Sep. 27, 2017 is expressly incorporated by reference herein.