Method, system, and storage medium for RC extraction using hierarchical modeling architecture

A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), the layout comprising a resistor-capacitor (RC) netlist comprising a plurality of circuit nodes; identifying an RC network in the RC netlist; determining a characterization matrix corresponding to the RC network; updating the RC netlist by replacing the RC network with the characterization matrix; and calculating voltages and currents of the plurality of circuit nodes based on the updated RC netlist.

BACKGROUND

In advanced semiconductor fabrication technologies, the feature density and operating frequency of devices are being progressively raised in order to achieve better performance with reduced footprint. To enable such advances, electronic design automation tools are widely used for facilitating design flows and ensuring the functional integrity of the manufactured integrated circuits (IC). The electronic design automation tools aid in establishing a software platform to evaluate the physical performance and electrical properties of the IC before the chip is fabricated. A variety of built-in device models and design rules are used to verify the performance of the circuit design, such as the functionality, power consumption, and feature geometries. The software platform can also simulate the physical behaviors and characteristics of the IC components in operation. As the semiconductor technology evolves, the component count of the IC increases, and the required computational resources and simulation time for the simulation grow accordingly.

DETAILED DESCRIPTION

In the present disclosure, a hierarchical modeling architecture is proposed to enhance the simulation efficiency of the electronic design automation (EDA) tool. As device sizes are being reduced while operation frequencies are increasing, the simulation tasks for design and manufacturing become more and more challenging. Specifically, as the device features are getting more crowded, the simulation of the device becomes increasingly complicated while the quantity of circuit nodes in the device is increased and their interactions are more prominent. When the EDA tool is leveraged to simulate the circuit design, the computing resources (CPU, RAM, etc.) consumed and processing time increase dramatically. Among the features of the circuit design, some subsets may share common properties and electrical behaviors. As such, the hierarchical modeling architecture takes advantage of the common features of the circuit subsets and tries to simplify the circuit design netlist by replacing those common circuit subsets with a characterization matrix. As a result, a multi-step simulation framework is provided that initially calculates the circuit design parameters of the simplified circuit netlist. The computational efforts can be reduced and the simulation efficiency can be improved accordingly.

FIG. 1is a schematic diagram illustrating a design flow100of a semiconductor chip, in accordance with some embodiments. The design flow100, employed for designing semiconductor integrated chips (ICs), utilizes one or more EDA tools to perform operations therein. A workstation or personal computer is typically used in executing the tools to accomplish the design flow100. The design flow100comprises a system design stage110, a logic design stage120, a synthesis stage130, a pre-layout simulation stage140, a placement and routing development stage150, a parameter extraction stage160and a post-layout simulation stage170.

Initially, at the system design stage110, a systematic architecture for the chip of interest is provided with a high-level description. At stage110, the chip functions along with performance requirements are determined according to a design specification. The chip functions are usually represented by respective schematic functional modules or blocks. In addition, an optimization or performance trade-off may be sought to achieve the design specifications with affordable cost and power.

At the logic design stage120, the functional modules or blocks are described in a register transfer level (RTL) using a hardware description language. Commercially available language tools are generally used, for example, Verilog or VHDL. In an embodiment, a preliminary functionality check is performed at stage120to verify if the implemented functions conform to the specifications set forth in stage110.

Subsequently, at the synthesis stage130, the modules in the RTL descriptions are converted into a netlist data where the circuit structures, e.g., logic gates and registers, of each function module are established. In some embodiments, mapping of logic gates and registers to available cells in the standard cell libraries is conducted. Further, the netlist data is offered to describe the functional relationship of the chip in a gate level. In an embodiment, the netlist data is transformed from a gate-level view to a transistor-level view.

Subsequently, the gate-level netlist data is verified at the pre-layout simulation stage140. During the verification process of stage140, if some of the functions fail the verification in the simulation, the design flow100may be paused temporarily or may go back to stage110or stage120for further circuit design modification. After completion of the pre-layout simulation stage140, the chip design has passed a preliminary verification and completed the front-end design process. Consequently, a back-end physical design process follows.

At the placement and routing stage150, a physical architecture representing the chip determined during the front-end process is implemented. The layout development may involve a placement operation and a routing operation in series. Detailed structure and associated geometry for the components of the chip are determined in the placement operation. Interconnects among different components are routed subsequent to the placement operation. Both placement and routing operations are performed to meet a design rule check (DRC) deck to ensure that the manufacturing requirements of the chip are fulfilled. In an embodiment, the DRC deck includes a set of parameters, such as maximal length, minimal length, minimal separation distance, etc., for the discrete elements. Once the stage150is completed, a placed-and-routed layout is created and a netlist along with data on placement and routing is generated accordingly.

At the parameter extraction stage160, a layout parameter extraction (LPE) operation is conducted to derive layout-dependent parameters, such as parasitic resistance and capacitance, resulting from the layout developed in stage150. Consequently, a post-layout netlist data is then generated, which includes the layout-dependent parameters. In an embodiment, other simulations are conducted to evaluate the voltages and currents at the nodes in the post-layout netlist. The node voltage and node current values may reflect the received voltage and current values for each circuit element in the chip. The voltage and current data may be checked against the design rules to determine if the post-layout netlist can function properly or meets the specifications. In an embodiment, subsequent to stage160, a timing analysis is performed to access the timing behavior of the designed chip incorporating the layout-dependent resistance and capacitance. The acquired voltages and currents of the nodes in the post-layout netlist are also employed for the timing analysis.

At the post-layout simulation stage170, a physical verification is performed taking into consideration the parameters acquired in previous stages. A simulation of transistor-level behavior is conducted to examine whether the chip performance meets the required system specifications. In some embodiments, the post-layout simulation is performed to minimize possibilities of electrical issues or lithographic issues during the chip manufacturing process.

Next, it is determined during stage180whether the post-layout netlist meets the design specifications. If affirmative, the circuit design is accepted at stage190and then signed off accordingly. The chip is manufactured according to the accepted post-layout netlist. However, if the result of the post-layout simulation is unfavorable, the design flow100loops back to previous stages for tuning functionalities or structures. For example, the design flow100may loop back to stage150where the layout is re-developed to fix issues from a physical perspective. Alternatively, the design flow100may retreat to an earlier stage110or120to recast the chip design from a functional level in case the problems cannot be resolved within the back-end process.

The design flow100illustrated inFIG. 1is exemplary. Modifications of the above-mentioned stages, such as change of order for the stages, partition of the stages, and deletion or addition of stages, are within the contemplated scope of the present disclosure.

FIG. 2is a schematic diagram illustrating a design flow200of a hierarchical modeling operation, in accordance with some embodiments. The design flow200may correspond to the LPE operation in stage160ofFIG. 1. In step202, a layout data is received. The layout data includes information on the placement and routing of electrical features of the chip. A post-layout netlist corresponding to the layout data is also provided in step202. In some embodiments, the chip may include an interconnect layer that is formed of stacked conductive interconnection sublayers. The interconnect layer may be formed of horizontal conductive lines interconnected through vertical conductive vias. The interconnect layer provides redistributed connections for the underlying features, such as a field-effect transistor (FET).

In step204, a parameter extraction operation is conducted based on the interconnect layer structure for incorporating the electrical performance of the interconnect layer into the post-layout netlist. The electrical performance may include different resistance and capacitance values at different locations of the interconnect layer, which may account for a resistance-capacitance (RC) delay. In addition, the electro-migration effect or the IR drop performance in each circuit feature of the chip may be evaluated via the layout-dependent parameters. In an embodiment, the layout-dependent parameters may include at least one resistance value for a circuit feature, such as a piece of conductive line or conductive via. In an embodiment, the layout-dependent parameters may include at least one capacitance value to represent a coupling effect between two or more circuit features, such as a capacitive coupling between two neighboring wires. The post-layout netlist may be expanded by adding the layout-dependent parameters. Alternatively, a layout-dependent netlist may be separately provided.

Referring toFIG. 3, an exemplary schematic circuit diagram302representative of a portion of the chip is illustrated. The circuit diagram302shows an equivalent circuit, e.g., of a section in an interconnect layer, of the chip. The circuit diagram302can be converted to a respective layout-dependent netlist, which is referred to as a resistor-capacitor (RC) netlist throughout the present disclosure. The circuit diagram302constitutes of several circuit nodes interconnected through resistors or capacitors, such as resistor R1and capacitor C1. The netlist may also include circuit nodes corresponding to the nodes in the circuit diagram302. Each resistor is assigned a resistance value, and each capacitor is assigned a capacitance value. The electrical properties in each part of the interconnect layer, such as resistance and capacitance, are reflected in the respective voltages, currents, and capacitances. The more circuit nodes that are allowed in the circuit diagram302, the higher simulation accuracy the circuit diagram302can provide. The numbers of circuit nodes and topology of the circuit pattern302shown inFIG. 3are illustrative only. Other numbers of circuit nodes and topology configurations are within the contemplated scope of the present disclosure.

In step206, at least one RC network in the circuit diagram302is identified. In an embodiment, the identification of the RC network can be done through the format of the RC netlist. An RC network refers to a subset of the RC netlist and comprises a network of resistors and capacitors. At the minimum, a single resistor or a single capacitor suffices to form an RC network. Still referring toFIG. 3, two RC networks310A and310B are identified and indicated in the circuit diagram302. In the depicted embodiment, the RC networks310A and310B share a common circuit topology. In another embodiment, the RC networks310A and310B have different circuit topologies but exhibit a same electrical behavior. For example, the RC network310A is equivalent to the RC network310B, or vice versa. In other words, the RC networks310A and310B are interchangeable. The RC network310A or310B may also include one or more capacitors, although not shown inFIG. 3. The RC network310A or310B is coupled to the remaining portion of the circuit diagram302(i.e., the RC netlist) through at least one circuit node, such as circuit nodes N1, N2, N3and N4for the RC network310A and circuit nodes N5, N6, N7and N8for the RC network310B.

In some embodiments, an RC network reduction is optionally performed, as demonstrated in step207. The goal of the RC network reduction is to reduce the quantity of nodes within the RC network in order to lower the computational burden of the RC network modeling. In an embodiment,FIG. 3Ashows that the RC network310A is reduced to an RC network310C by removing a resistor R2. As such, the nodes on two sides of the resistor R2are joined together and regarded as a single node. In an embodiment, the RC network310A is reduced by changing the resistance value of the resistor R2rather than completely removing resistor R2. The reason for changing the resistance of R2is to allow the reduced RC network310A to better fit a category of characterization matrix, as will be explained in subsequent paragraphs. In an embodiment, the RC network310A is reduced by removing the capacitor C1, as shown inFIG. 3A. In an embodiment, during the operation of an RC network reduction, one or more capacitors are eliminated in response to the removal of resistors. In some embodiments, the capacitors are rearranged to connect other circuit nodes or their capacitances are modified if they are not eliminated.

In another embodiment,FIG. 3Bshows that the RC network310A is reduced to an RC network310D by merging resistors R1and R4into another resistor R5. As such, the node connecting the resistors R1and R4is eliminated. Under such situation, a modification of connection for the remaining resistors or capacitors may be necessary. For example, the resistor R2is reallocated through being reconnected to one end of the resistor R5. A topology refinement algorithm may be utilized to determine an updated topology of the reduced RC network310D so as to lower the modeling error as much as possible.

Subsequently, in step208, a characterization matrix320is determined for characterizing an RC network. The RC network to be characterized can be an unreduced RC network or a reduced RC network. The characterization matrix320is applied as an equivalent circuit of the corresponding RC network without mentioning the circuit features inside the RC network. In the depicted example, the characterization matrix320is used as an equivalent circuit of the RC networks310A and310B, as shown inFIG. 4. The characterization matrix320has four input/output (I/O) ports M1through M4corresponding to the circuit nodes N1through N4for the RC network310A or the circuit nodes N5through N8for the RC network310B. Electrical properties of the ports M1through M4, such as the port voltages (i.e., V1through V4) and port currents (i.e., I1through I4) are related to each other based on the topology and values of the resistors and capacitors within the characterization matrix320. In an embodiment, the characterization matrix320is described through a matrix of simultaneous equations, such as an H matrix, a Y matrix, or a Z matrix, with voltages and currents of ports M1through M4as inputs and outputs.

In the embodiment of a Z matrix with entries zij, the relationships of the port voltages and port currents are represented by the following equation:

In the embodiment of a Y matrix with entries yij, the relationships of the port voltages and port currents are represented by the following equation:

In the embodiment of an H matrix with entries hij, the relationships of the port voltages and port currents for a representative two-port H matrix are represented by the following equation:

It can be appreciated by persons skilled in the art that a multiple-port H matrix with a port quantity greater than two can be extended from the two-port H matrix by assigning appropriate inputs and outputs selected from the variables of V1through V4and I1through I4. In some embodiments, each of the different forms of the characterization matrix320, i.e., Y matrix, H matrix, and Z matrix, can be converted to another form through appropriate matrix manipulation. The entries zij, yij, and hij, for the characterization matrices Z, Y and H, respectively, are determined based on the circuit topology and the resistance/capacitance of the circuit feature in the RC network to be replaced. Once the equations for the characterization matrix320are established with the values of entries obtained, the characterization matrix320is prepared and the flow200proceeds to step210.

Referring back toFIG. 2, in step210, at least one RC network of the RC netlist is replaced with a corresponding characterization matrix. In the depicted sample, the characterization matrix320is utilized to replace the RC network310A or310B.FIG. 5demonstrates a schematic circuit diagram502, which shows the circuit diagram302with two characterization matrices320in place of the RC networks310A and310B. Alternatively, the RC netlist can be rewritten by replacing the interconnections within the RC network310A or310B with the equations of the characterization matrix320shown in equations (1) through (3). Circuit nodes N1, N2, N3and N4are used to interface the first characterization matrix320with the remaining portions of the RC netlist. Similarly, circuit nodes N5, N6, N7and N8are used to interface the second characterization matrix320with the remaining portions of the RC netlist. It should be noted that the RC network310A or310B and the characterization network320can be converted to each other, and thus the electrical performances of the two circuit diagrams302and502should not be the same. Consequently, the resultant circuit diagram502has fewer circuit nodes than its counterpart circuit diagram302. In an embodiment, multiple characterization matrices are applied to a circuit diagram or an RC netlist. A higher percentage of replacement of the characterization matrix corresponds to a larger reduction of circuit nodes of the circuit diagram. Accordingly, the quantity of nodes of the updated circuit diagram (or RC netlist) and the corresponding computational burden are reduced.

As discussed previously, as long as more RC networks can be identified in the RC netlist, the modeling of the circuit diagram320can undergo additional computational reduction due to elimination of circuit nodes. In addition, if the identified RC networks can be grouped, and a characterization matrix identified for replacement, then the simulation efforts can be further reduced. In an embodiment, the RC networks310A and310B can be replaced with different characterization matrices if they have different circuit topologies. In some embodiments where the RC networks310A and310B are different, at least one of the RC network310A and310B may be subjected to a reduction operation and converted to reduced RC networks (e.g., a reduction approach exemplified for the RC networks310C and310D). When one or more among the multiple RC networks are reduced, they can be considered identical and share a same characterization matrix as replacement. The computational efforts can be reduced by cutting off the utilization of an additional characterization matrix for the different RC network.

Still referring toFIG. 2, in step212, a first-step simulation of the hierarchical modeling is conducted. The simulation is performed against the updated RC netlist corresponding to the circuit diagram502. A software simulation platform, e.g. SPICE, may be leveraged to perform the simulation task. Electrical properties, such as node voltages and node currents, are calculated. In an embodiment, the calculation of the node voltages and node currents is performed through solving simultaneous equations of all nodes. However, the circuit nodes inside the RC networks310A and310B are not taken into consideration during the present round of calculation since the relationships of such nodes on the circuit diagram502are expressed by the equations of the characterization matrix320. The node voltages and node currents at circuit nodes N1through N8are calculated, although they are also regarded part of the characterization matrix320. Those node voltages and node currents for nodes N1through N8may be stored or recorded for a second-step simulation.

Next, the second-step simulation of the hierarchical modeling is conducted, as illustrated in step214. Referring toFIG. 4, the voltages and currents of the circuit nodes inside the RC networks310A and310B are calculated. Accordingly, the overall modeling of the circuit diagram302is completed. The voltages and currents of the RC networks310A and310B can be obtained using the characterization matrix320based on the topology of the circuit diagram320and the calculated node voltages/currents at N1through N8obtained in step212. For example, the circuit nodes within the RC network310A are processed by substituting the voltages and currents of circuit nodes N1through N4obtained in step212into the port voltages/currents of ports M1through M4, respectively, of the characterization matrix320. Similarly, the circuit nodes within the RC network310B are processed by substituting the voltages and currents of circuit nodes N5through N8derived in step212into the port voltages/currents of ports M1through M4, respectively, of the characterization matrix320. In an embodiment where the RC networks310A and310B have different circuit topologies, separate calculation procedures are applied to the RC networks310A and310B. In alternative embodiments, assume the RC networks310A and310B are subjected to a reduction operation and share a common characterization matrix320with the RC network310B. In such situation, a node restoration operation may be performed in which the reduced circuit features of the RC network310A can be restored. The restored RC network310A is subjected to the second-step simulation in step214. Therefore, the RC network310A may have a node quantity different from that of the RC network310B. The node voltages and currents between the two RC networks310A and310B may also be different due to the node restoration operation.

In an embodiment, a timing analysis is performed based on the updated netlist and the calculated voltages and currents of the plurality of circuit nodes obtained in step214. The timing analysis result will determine if the post-layout netlist meets the specifications, specifically for a digital circuit.

The proposed hierarchical modeling architecture can be made more efficient if a nested characterization matrix is formed.FIG. 6Ais a schematic circuit diagram representing the characterization matrix320. An RC network610A is identified within the RC network310A. The RC network610A can be regarded as an RC subnetwork of the RC network310A. Further, another RC network610B, which is identical to the RC subnetwork610A, is also found within the RC network310A. The RC network610B can be regarded as another RC subnetwork of the RC network310A. A characterization matrix620is illustrated inFIG. 6B. The characterization matrix620includes four ports P1through P4to communicate with the remaining circuit features of the characterization matrix320. The characterization matrix620is employed to replace the RC subnetwork610A or610B, and can be regarded as a characterization submatrix of the characterization matrix320. In other words, the characterization matrix320and characterization submatrix620form a nested characterization matrix structure. As such, the RC network310A can be replaced by the characterization matrix320and the characterization matrix620recursively. In an embodiment, when the characterization matrix620is used to replace the RC submatrix610A, the ports P1and M1are seen as the same node. Similarly, the ports P2and M2are seen as the same node. Moreover, when the characterization matrix620is used to replace the RC submatrix610B, the ports P3and M3are seen as the same node, and the ports P4and M4are seen as the same node. Thus, repeated calculation efforts for the above-mentioned shared ports can be saved.

FIG. 7demonstrates a schematic circuit diagram702, which shows the circuit diagram502with four characterization sub-matrices620in place of the RC subnetworks610A and610B in the RC networks310A and310B. Alternatively, the RC netlist can be further rewritten by replacing the interconnections within the RC subnetwork610A or610B with equations similar to the equations (1) to (3). Consequently, the resultant circuit diagram502has fewer circuit nodes than its counterpart circuit diagram302. In an embodiment, multiple characterization matrices are applied to a circuit diagram or RC netlist. As can be observed, the quantity of nodes in the first-step simulation that are fed to the SPICE platform is less than the quantity of nodes inFIG. 5. Accordingly, the corresponding computational burden can be further reduced.

FIG. 8is a schematic diagram illustrating a design flow800of performing a hierarchical modeling operation, in accordance with some embodiments. The design flow800is similar to the design flow200shown inFIG. 2, except that a nested modeling framework is incorporated. The operations and structures in each step of the flow800refer to the detailed descriptions for the design flow200for simplicity and clarity except where otherwise indicated.

In step802, a post-layout data corresponding to a circuit diagram, e.g., circuit diagram302, is received. In step804, an RC extraction operation is performed on the post-layout data. In step806, at least one RC network and one RC subnetwork are identified.

In step807, an RC network reduction operation or an RC subnetwork reduction is optionally performed. The reduction operation can be performed on one or more of the identified RC network and RC subnetworks. In step808, at least one characterization matrix and one characterization submatrix are determined for characterizing an RC network and an RC subnetwork. In step810, at least one RC network and one RC subnetwork are replaced with a corresponding characterization matrix and its characterization submatrix. An exemplary circuit diagram702is obtained.

In step812, an iterative procedure for calculating the node voltages and node currents are performed. The ports in an inner characterization matrix (i.e., a characterization submatrix) are calculated subsequent to the calculation of its outer characterization matrix. Taking the circuit diagram702as an example, a first-step simulation of the hierarchical modeling is initially conducted using the updated circuit diagram702. Voltages and currents of the nodes that remain in the circuit diagram702are calculated. In the meantime, the port voltages and port currents of the characterization matrix320are also obtained, in an operation similar to that of step212. Next, the voltages and port currents of the nodes within the characterization submatrix620, e.g., the nodes N9, N10, N11and N12shown inFIG. 6A, are calculated. If the characterization submatrix620has more layers of submatrices therewithin, the step812proceeds with calculation of each characterization submatrix until the innermost characterization submatrix.

In step814, the node voltages and node currents of the innermost characterization submatrix are calculated, in a manner similar to that of step201. The overall node voltages and node currents are completed.

FIG. 9is a schematic diagram of a system900implementing layout designs, in accordance with some embodiments. The system900includes a processor901, a network interface903, an input and output (I/O) device905, a storage907, a memory909, and a bus908. The bus908couples the network interface903, the I/O device905, the storage907, the memory909and the processor901to each other.

The processor901is configured to execute program instructions that include a tool configured to perform the method as described and illustrated with reference to figures of the present disclosure. Accordingly, the tool is configured to execute the steps such as: provide design specifications, generate a netlist of a circuit, perform pre-layout simulation, generate an initial layout, identify at least one RC network in the initial layout, generate a reduced netlist by replacing the RC network with a corresponding characterization matrix, calculate node voltages and node currents of the nodes in the netlist, perform post-layout simulation and verify the post-layout simulation result.

The network interface903is configured to access program instructions and data accessed by the program instructions stored remotely through a network (not shown).

The I/O device905includes an input device and an output device configured for enabling user interaction with the system900. In some embodiments, the input device comprises, for example, a keyboard, a mouse, and other devices. Moreover, the output device comprises, for example, a display, a printer, and other devices.

The storage device907is configured for storing program instructions and data accessed by the program instructions. In some embodiments, the storage device907comprises a non-transitory computer readable storage medium, for example, a magnetic disk and an optical disk. Other forms of storage medium are also within the contemplated scope of the present disclosure.

The memory909is configured to store program instructions to be executed by the processor901and data accessed by the program instructions. In some embodiments, the memory909comprises any combination of a random access memory (RAM), some other volatile storage device, a read only memory (ROM), and some other non-volatile storage device, such as flash memory.

The proposed hierarchical modeling architecture is advantageous in several aspects. By observing that the power delivery structure of a chip contains a few repeated electrical structures, those repeated electrical structures can be simplified by a representative RC network. For example, a power delivery network may be constructed with many repeated hierarchical and nested networks. Utilizing the proposed hierarchical modeling architecture may be helpful in reducing duplicated computations for the repeated networks. As a result, repeated simulation resources can be significantly reduced, thus saving the processing time. In some configurations, the proposed hierarchical modeling architecture does not sacrifice simulation accuracy. Moreover, the proposed scheme is flexible in supporting different types of RC networks, and can accommodate an arbitrary number of ports for the RC network. In addition, the proposed architecture is compatible with current parallel processing platforms for further improving multiple thread operations at the same time.

According to an embodiment, a method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), the layout comprising a resistor-capacitor (RC) netlist comprising a plurality of circuit nodes; identifying an RC network in the RC netlist; determining a characterization matrix corresponding to the RC network; updating the RC netlist by replacing the RC network with the characterization matrix; and calculating voltages and currents of the plurality of circuit nodes based on the updated RC netlist.

According to an embodiment, a system comprises one or more processors and one or more programs including instructions which, when executed by the one or more processors, cause the system to: access a layout of an integrated circuit (IC), the layout comprising a resistor-capacitor (RC) netlist comprising a plurality of circuit nodes; identify an RC network in the RC netlist; determine a characterization matrix corresponding to the RC network; update the RC netlist by replacing the RC network with the characterization matrix; and calculate voltages and currents of the plurality of circuit nodes based on the updated RC netlist.

According to an embodiment, a non-transitory computer readable storage medium comprises instructions which, when executed by a processor, perform the steps of: accessing a layout of an integrated circuit (IC), the layout comprising a resistor-capacitor (RC) netlist comprising a plurality of circuit nodes; identifying an RC network in the RC netlist; determining a characterization matrix corresponding to the RC network; updating the RC netlist by replacing the RC network with the characterization matrix; and calculating voltages and currents of the plurality of circuit nodes based on the updated RC netlist.