Controller, memory system and operating method thereof

In accordance with an embodiment of the present disclosure, a method of a controller for controlling a nonvolatile memory device including a plurality of data storage regions may include: determining, in response to a first copy event of receiving from a host a command instructing copy of data from a first logical address into a second logical address, whether a second copy event of copying the data from a first data storage region having a first physical address mapped to the first logical address into a data storage region having another physical address will occur; and in response to determining that the second copy event will not occur, changing a logical address mapped to the first physical address from the first logical address to the second logical address and invalidating the first logical address.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2019-0076928, filed on Jun. 27, 2019, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor device, and more particularly, to a controller, a memory system and an operating method of the controller.

2. Related Art

Recently, the paradigm for the computing environment has changed to the ubiquitous computing environment in which computer systems can be used anytime anywhere. Therefore, the use of portable electronic devices such as a mobile phone, digital camera and notebook computer has rapidly increased. Such a portable electronic device generally uses a memory system using a memory device. The memory system is used to store data used in the portable electronic device.

Since the memory system using a memory device has no mechanical driver, the data storage device has excellent stability and durability, exhibits high information access speed, and has low power consumption. Examples of the memory system having such advantages include a universal serial bus (USB) memory device, a memory card having various interfaces, a universal flash storage (UFS) device, and a solid state drive (SSD).

SUMMARY

Various embodiment of the present disclosure provides a technology capable of improving the performance of a memory system.

In accordance with an embodiment of the present disclosure, a method of a controller for controlling a nonvolatile memory device including a plurality of data storage regions may include: determining, in response to a first copy event of receiving from a host a command instructing copy of data from a first logical address into a second logical address, whether a second copy event of copying the data from a first data storage region having a first physical address mapped to the first logical address into a data storage region having another physical address will occur; and in response to determining that the second copy event will not occur, changing a logical address mapped to the first physical address from the first logical address to the second logical address and invalidating the first logical address.

In accordance with an embodiment of the present disclosure, a memory system may include: a nonvolatile memory device including a plurality of data storage regions; and a controller configured to control the nonvolatile memory device, wherein the controller is configured to: determine, in response to a first copy event of receiving from a host a command instructing copy of data from a first logical address into a second logical address, whether a second copy event of copying the data from a first data storage region having a first physical address mapped to the first logical address into a data storage region having another physical address will occur; and in response to determining that the second copy event will not occur, change a logical address mapped to the first physical address from the first logical address to the second logical address and invalidate the first logical address, when the second copy event is predicted not to occur.

In accordance with an embodiment of the present disclosure, a memory system may include: a nonvolatile memory device including a plurality of memory blocks each having a plurality of data storage regions; and a controller configured to, in response to a command instructing change of a logical address corresponding to data from a first logical address to a second logical address, determine whether a copy event on the data will occur; and, in response to determining that the copy event will not occur, map a first physical address that is mapped to the first logical address to the second logical address and invalidate the first logical address.

In accordance with an embodiment of the present disclosure, it is possible to improve the performance of a memory system.

DETAILED DESCRIPTION

It will be understood that when an element is referred to as being “connected to”, or “coupled to” another element, it may be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. It will be understood that the terms “comprises,” “comprising,” “includes,” and “including” when used in this specification, specify the presence of the stated elements and do not preclude the presence or addition of one or more other elements.

Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. Detailed description of functions and structures well known to those skilled in the art will be omitted to avoid obscuring the subject matter of the present disclosure.

Hereinafter, illustrative embodiments of the present disclosure will be described below with reference to the accompanying drawings.

FIG. 1illustrates a configuration of a memory system10in accordance with an embodiment of the present disclosure.

The memory system10may store data to be accessed by a host20such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game player, a television (TV), an in-vehicle infotainment system, and the like.

The memory system10may be manufactured as any one among various types of storage devices according to an interface protocol coupled to the host20. For example, the memory system10may include any one of various types of storage devices, such as a solid state drive (SSD), a multimedia card in the forms of MMC, eMMC, RS-MMC and micro-MMC, a secure digital card in the forms of SD, mini-SD and micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a storage device of the type of a personal computer memory card international association (PCMCIA) card, a storage device of the type of a peripheral component interconnection (PCI), a storage device of the type of a PCI-express (PCI-E), a compact flash (CF) card, a smart media card, a memory stick, and the like.

The memory system10may be manufactured as any one among various types of packages. For example, the memory system10may be manufactured as any one of a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-level fabricated package (WFP), and a wafer-level stack package (WSP).

The memory system10may include a nonvolatile memory device100and a controller200.

The nonvolatile memory device100may operate as a storage medium of the memory system10. According to a memory cell included in the nonvolatile memory device100, the nonvolatile memory device100may be implemented as one among various nonvolatile memory device such as a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a magnetic random access memory (MRAM) using a tunneling magneto-resistive (TMR) layer, a phase-change random access memory (PRAM) using a chalcogenide alloy, a resistive random access memory (ReRAM) using a transition metal compound, and so forth.

AlthoughFIG. 1shows the memory system10including a single nonvolatile memory device100for clear description, the memory system10may include a plurality of nonvolatile memory devices100and the scope of the present disclosure may cover the memory system10including a plurality of nonvolatile memory devices100.

The nonvolatile memory device100may include a memory cell array (not shown) including a plurality of memory cells arranged at cross points between a plurality of word lines (not shown) and a plurality of bit lines (not shown). The memory cell array may include a plurality of memory blocks each including a plurality of pages.

For example, each of the memory cells in the memory cell array may be used as a single level cell (SLC) capable of storing 1-bit data and/or as a multi-level cell (MLC) capable of storing data of 2 or greater bits. A memory cell capable of 2-bit data may be referred to as a multi-level cell (MLC), a memory cell capable of 3-bit data may be referred to as a triple level cell (TLC), and a memory cell capable of 4-bit data may be referred to as a quadruple level cell (QLC).

The memory cell array may include at least one of the SLC and the MLC. The memory cell array may include memory cells arranged in a two-dimensional (e.g., horizontal) structure or memory cells arranged in a three-dimensional (e.g., vertical) structure.

The controller200may control general operations of the memory system10by driving firmware or software loaded in the memory230. The controller200may decode and execute instructions or algorithms expressed as code, such as firmware or software. The controller200may be implemented as hardware or combination of hardware and software.

The controller200may include a host interface210, a processor220and a memory interface240. Although not illustrated inFIG. 1, the controller200may further include an error correction code (ECC) engine configured to generate a parity by ECC-encoding write data provided from the host20and to ECC-decode read data read from the nonvolatile memory device100using the parity.

The host interface210may interface the host20and the memory system10according to a protocol of the host20. For example, the host interface210may communicate with the host20through any one among a universal serial bus (USB) protocol, a universal flash storage (UFS) protocol, a multimedia card (MMC) protocol, a parallel advanced technology attachment (PATA) protocol, a serial advanced technology attachment (SATA) protocol, a small computer system interface (SCSI) protocol, a serial attached SCSI (SAS) protocol, a peripheral component interconnection (PCI) protocol, and a PCI express (PCI-E) protocol.

The processor220may comprise a micro control unit (MCU) and/or a central processing unit (CPU). The processor220may process requests transmitted from the host20. To process the requests transmitted from the host20, the processor220may perform an instruction or algorithm expressed in code (for example, firmware) loaded into the memory230and control internal function blocks such as the host interface210, the memory230and the memory interface240and the nonvolatile memory device100.

The processor220may generate control signals for controlling operations of the nonvolatile memory device100based on the requests transmitted from the host20and may provide the generated control signals to the nonvolatile memory device100through the memory interface240.

The memory230may include a read only memory (ROM) and a random access memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). The memory230may store the firmware to be executed by the processor220. The memory230may also store data (for example, meta data) required for driving of the firmware. That is, the memory230may operate as a working memory of the processor220.

The memory230may include a data buffer configured to temporarily store write data to be transmitted to the nonvolatile memory device100from the host20, temporarily store read data to be transmitted to the host20from the nonvolatile memory device100, or both. That is, the memory230may operate as a buffer memory of the processor220.

The memory interface240may control the nonvolatile memory device100according to the control of the processor220. The memory interface240may be referred to as a memory controller. The memory interface240may provide control signals to the nonvolatile memory device100. The control signals may include a command, an address, and an operation control signal, and the like for controlling the nonvolatile memory device100. The memory interface240may provide the nonvolatile memory device100with data stored in the data buffer or store data transmitted from the nonvolatile memory device100in the data buffer.

FIG. 2illustrates a configuration of a data storage region included in the nonvolatile memory device100in accordance with an embodiment of the present disclosure.

Referring toFIG. 2, the nonvolatile memory device100may include a plurality of dies210aand210bsharing a channel CH electrically coupled to the controller200. Each of the plurality of dies210aand210bmay include a plurality of planes212aand212bsharing a way211electrically coupled to the channel CH. Each of the plurality of planes212aand212bmay include a plurality of page groups each having a plurality of pages. A page may be a minimum unit of a storage region, into which data is written or from which data is read. A bundle of a plurality of page groups, on which an erase operation is discretely performed, may be referred to as a memory block. A group of a plurality of memory blocks that is regarded as a single memory block is referred to as a super block. Although the data storage region within the nonvolatile memory device100may be any one among a die, a plane, a super block, a memory block, the page and a page group, the data storage region hereinafter may be a page unless stated otherwise.

FIG. 3is a flowchart illustrating an operation300of the memory system10in accordance with an embodiment of the present disclosure. The operation300may be performed by the controller200ofFIG. 1. Referring toFIG. 3, the controller200in step S310may detect a first copy event. The first copy event may be receiving, from the host20, a command instructing that data stored in a first logical address be copied into a second logical address. In other words, the first copy event may be receiving, from the host20, a command instructing an operation of changing a logical address corresponding to data.

In an embodiment, the first copy event may occur when a file system of the host20performs a garbage collection operation, a migration operation and so forth.

In step S315, the controller200may determine, in response to the first copy event, whether or not a second copy event of storing data, which is stored in a first data storage region having a first physical address mapped to the first logical address, into another data storage region is to occur. The second copy event may be a copy operation involved with an internal operation or a background operation such as a garbage collection operation, a wear levelling operation, a read reclaim operation and so forth. In step S320, when the controller200determines that the second copy event will occur, the process300proceeds to S340; otherwise, the process300proceeds to S330.

In an embodiment, the controller200may determine that the second copy event will not occur when a number of invalid pages within a memory block including the first data storage region is under a first threshold. In an embodiment, the controller200may determine that the second copy event will occur when the number of invalid pages within the memory block including the first data storage region is the first threshold or greater. The first threshold may be a threshold number of invalid pages to trigger a garbage collection operation.

In an embodiment, the controller200may determine that the second copy event will not occur when a number of erase operations performed on a memory block including the first data storage region is under a second threshold. In an embodiment, the controller200may determine that the second copy event will occur when the number of erase operations performed on the memory block including the first data storage region is the second threshold or greater. The second threshold may be a threshold number of erase operations performed on a memory block to trigger a wear levelling operation on the memory block.

In an embodiment, the controller200may determine that the second copy event will not occur when an occurrence frequency of an error during a read operation on the first data storage region or a number of errors occurring during a read operation on the first data storage region is under a third threshold. In an embodiment, the controller200may determine that the second copy event will occur when the occurrence frequency of an error during a read operation on the first data storage region or the number of errors occurring during a read operation on the first data storage region is the third threshold or greater. The third threshold may be a threshold occurrence frequency of an error or a threshold number of errors to trigger a read reclaim operation on the first data storage region.

In step S330, when the process300has determined that the second copy event will not occur, the controller200may change the logical address mapped to the first physical address, which is a physical address representing the first data storage region, from the first logical address to the second logical address and may invalidate the first logical address. In other words, the controller200may map the first physical address, which is originally mapped to the first logical address, to the second logical address and may invalidate the first logical address.

That is, the controller200may change, in response to the first copy event, mapping information corresponding to data without substantial copying of data. Therefore, the host20may regard the data, which originally corresponds to the first logical address, as currently corresponding to the second logical address.

In step S340, when the process300has determined that the second copy event will occur, the controller200may copy data from the first data storage region into a second data storage region as part of the processing of the second copy event. That is, when the process300determines that an internal operation or a background operation (such as a garbage collection operation, a wear levelling operation, a read reclaim operation and so forth) is to be performed on the first data storage region, the controller200may process the first copy event through the internal operation or the background operation.

In step S340, in response to the second copy event occurring, the controller200may control the nonvolatile memory device100to read data from the first data storage region and store the read data into the second data storage region having the second physical address. The controller200may map the second physical address to the second logical address.

In an embodiment, when the process300determines that the second copy event will occur, the controller200may await the occurrence of the second copy event and then process the first copy event as part of processing the second copy event.

In an embodiment, when the process300determines that the second copy event will occur, the controller200may generate the second copy event as soon as possible and then process the first copy event as part of performing the second copy event. For example, the controller200may advance the occurrence of the second copy event by controlling the nonvolatile memory device100to preferentially perform an internal operation or a background operation involving the second copy event such as a garbage collection operation, a wear levelling operation, a read reclaim operation and so forth.

FIG. 4illustrates an operation of the memory system10in accordance with an embodiment of the present disclosure.

FIG. 4illustrates a mapping table indicating a mapping relationship between logical addresses and physical addresses.

FIG. 4(a)illustrates the mapping table before the first copy event occurs. The first logical address LBA1may be mapped to the first physical address PPN1. Hereinafter, description will be made under assumption that first data is stored in a data storage region having the first physical address PPN1.

FIG. 4(b)illustrates the mapping table after the first copy event is processed at step S330ofFIG. 3when it has been determined at steps S315and S320that the second copy event will not occur. The memory system10may map the first physical address PPN1, which is originally mapped to the first logical address LBA1, to the second logical address LBA2and may invalidate the first logical address LBA1. That is, the controller200may process the first copy event without substantial copying operations by changing only the mapping relationship between the logical address and the physical address.

FIG. 4(c)illustrates the mapping table after the first copy event is processed as part of processing the second copy event at step S340when it has been determined at steps S315and S320that the second copy event will occur. The memory system10may read the first data from the data storage region having the first physical address PPN1and may store the read first data into the data storage region having the second physical address PPN2. The memory system10may map the second physical address PPN2to the second logical address LBA2. The memory system10may invalidate the first logical address LBA1and the first physical address PPN1. That is, the controller200may perform a copy operation only once by processing the first copy event as part of processing the second copy event.

FIG. 5is a diagram illustrating a configuration of a data processing system including a solid state drive (SSD) in accordance with an embodiment of the present disclosure. Referring toFIG. 5, a data processing system2000may include a host2100and a solid state drive (SSD)2200.

The SSD2200may include a controller2210, a buffer memory device2220, nonvolatile memory devices2231,2232, . . .223n, a power supply2240, a signal connector2250, and a power connector2260.

The controller2210may control overall operation of the SSD2200. The controller2210may be implemented and operate in the substantially same way as the controller200ofFIG. 1.

The buffer memory device2220may temporarily store data to be stored in the nonvolatile memory devices2231to223n. Further, the buffer memory device2220may temporarily store data read out from the nonvolatile memory devices2231to223n. The data temporarily stored in the buffer memory device2220may be transmitted to the host2100or the nonvolatile memory devices2231to223naccording to control of the controller2210.

The nonvolatile memory devices2231to223nmay be used as storage media of the SSD2200. The nonvolatile memory devices2231to223nmay be electrically coupled to the controller2210through a plurality of channels CH1, CH2, . . . CHn, respectively. One or more nonvolatile memory devices may be coupled to a single channel. The nonvolatile memory devices coupled to a single channel may be coupled to the same signal bus and data bus.

The power supply2240may provide the inside of the SSD2200with power PWR inputted through the power connector2260. The power supply2240may include an auxiliary power supply2241. The auxiliary power supply2241may supply power to allow the SSD2200to be properly terminated when sudden power-off (SPO) occurs. The auxiliary power supply2241may include large capacity capacitors capable of charging the power PWR.

The controller2210may exchange a signal SGL with the host2100through the signal connector2250. The signal SGL may include a command, an address, data, and the like. The signal connector2250may be configured as any of various types of connectors according to an interface scheme between the host2100and the SSD2200.

FIG. 6is a diagram illustrating a configuration of the controller2210illustrated inFIG. 5according to an embodiment. The controller2210may include a host interface2211, a control component2212, a random access memory2213, an error correction code (ECC) component2214, and a memory interface2215.

The host interface2211may perform interfacing between the host2100and the SSD2200according to a protocol of the host2100. For example, the host interface2211may communicate with the host2100through any of the following protocols: secure digital (SD), universal serial bus (USB), multi-media card (MMC), embedded MMC (eMMC), personal computer memory card international association (PCMCIA), parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI Express (PCI-E), universal flash storage (UFS), and the like. In addition, the host interface2211may perform a disk emulating function so that the host2100recognizes the SSD2200as a general-purpose data storage system, for example, a hard disk drive (HDD).

The control component2212may parse and process the signal SGL provided from the host2100. The control component2212may control operations of internal function blocks according to firmware or software for driving the SSD2200. The random access memory2213may operate as a working memory for use when performing such firmware or software.

The ECC component2214may generate parity data for data to be transmitted to the nonvolatile memory devices2231to223n. The generated parity data may be stored, along with the data, in the nonvolatile memory devices2231to223n. The ECC component2214may detect errors of data read out from the nonvolatile memory devices2231to223nbased on the parity data. When the detected errors are within a correctable range, the ECC component2214may correct the detected errors.

The memory interface2215may provide control signals such as commands and addresses to the nonvolatile memory devices2231to223naccording to control of the control component2212. The memory interface2215may exchange data with the nonvolatile memory devices2231to223naccording to control of the control component2212. For example, the memory interface2215may provide data stored in the buffer memory device2220to the nonvolatile memory devices2231to223nor provide data read out from the nonvolatile memory devices2231to223nto the buffer memory device2220.

FIG. 7is a diagram illustrating a configuration of a data processing system including a memory system in accordance with an embodiment of the present disclosure. Referring toFIG. 7, a data processing system3000may include a host3100and a memory system3200.

The host3100may be configured in the form of a board such as a printed circuit board. Although not shown inFIG. 7, the host3100may include internal function blocks for performing functions of a host.

The host3100may include a connection terminal3110such as a socket, a slot, or a connector. The memory system3200may be mounted on the connection terminal3110.

The memory system3200may be configured in the form of a board such as a printed circuit board. The memory system3200may be referred to as a memory module or a memory card. The memory system3200may include a controller3210, a buffer memory device3220, nonvolatile memory devices3231and3232, a power management integrated circuit (PMIC)3240, and a connection terminal3250.

The controller3210may control overall operation of the memory system3200. The controller3210may be configured in substantially same manner as the controller2210shown inFIG. 6.

The buffer memory device3220may temporarily store data to be stored in the nonvolatile memory devices3231and3232. Further, the buffer memory device3220may temporarily store data read out from the nonvolatile memory devices3231and3232. The data temporarily stored in the buffer memory device3220may be transmitted to the host3100or the nonvolatile memory devices3231and3232according to control of the controller3210.

The nonvolatile memory devices3231and3232may be used as storage media of the memory system3200.

The PMIC3240may provide the internal components of the memory system3200with power inputted through the connection terminal3250. The PMIC3240may manage the power of the memory system3200according to control of the controller3210.

The connection terminal3250may be electrically coupled to the connection terminal3110of the host3100. Through the connection terminal3250, signals such as commands, addresses, data and the like, and power may be transferred between the host3100and the memory system3200. The connection terminal3250may be configured as any of various types depending on an interface scheme between the host3100and the memory system3200. The connection terminal3250may be disposed on or in any side of the memory system3200.

FIG. 8is a diagram illustrating a configuration of a data processing system including a memory system in accordance with an embodiment of the present disclosure. Referring toFIG. 8, the data processing system4000may include a host4100and a memory system4200.

The host4100may be configured in the form of a board such as a printed circuit board. Although not shown inFIG. 8, the host4100may include internal function blocks for performing functions of a host.

The memory system4200may be configured in the form of a package of a surface-mounting type. The memory system4200may be mounted on the host4100through solder balls4250. The memory system4200may include a controller4210, a buffer memory device4220, and a nonvolatile memory device4230.

The controller4210may control overall operation of the memory system4200. The controller4210may be configured in substantially same manner as the controller2210shown inFIG. 6.

The buffer memory device4220may temporarily store data to be stored in the nonvolatile memory device4230. Further, the buffer memory device4220may temporarily store data read out from the nonvolatile memory device4230. The data temporarily stored in the buffer memory device4220may be transmitted to the host4100or the nonvolatile memory device4230according to control of the controller4210.

The nonvolatile memory device4230may be used as a storage medium of the memory system4200.

FIG. 9is a diagram illustrating a configuration of a network system5000including a memory system in accordance with an embodiment of the present disclosure. Referring toFIG. 9, the network system5000may include a server system5300and a plurality of client systems5410to5430which are electrically coupled to each other through a network5500.

The server system5300may service data in response to requests from the plurality of client systems5410to5430. For example, the server system5300may store data provided from the plurality of client systems5410to5430. In another example, the server system5300may provide data to the plurality of client systems5410to5430.

The server system5300may include a host5100and a memory system5200. The memory system5200may be configured as the memory system10illustrated inFIG. 1, the SSD2200illustrated inFIG. 5, the memory system3200illustrated inFIG. 7, the memory system4200illustrated inFIG. 8, or combinations thereof.