Bank precharge signal generation circuit

A bank precharge signal generation circuit includes a precharge signal generation unit for generating a second precharge signal including a pulse, which is generated in a period delayed by a predetermined period as compared to a pulse of a first precharge signal, in response to an all-bank precharge signal, and a bank precharge signal generation unit for receiving the first and second precharge signals and generate first and second bank precharge signals for precharging first and second banks.

TECHNICAL FIELD

The present invention relates to a semiconductor memory device, and more particularly, to a bank precharge signal generation circuit capable of enhancing noise immunity and reception sensitivity by reducing a peak current.

BACKGROUND

A synchronous dynamic random access memory (SDRAM) is a semiconductor memory device which operates synchronously with an external clock and requires stabilization the semiconductor memory device by sequentially inputting external command after initial application of a driving operation voltage (VDD). Particularly, in the SDRAM, a precharge operation is very important since all operations are performed in the precharge state.

The precharge operation in a semiconductor memory device having a multi-bank structure is classified into an all-bank precharge operation in which the precharge is performed on all of the banks, and a single-bank precharge operation, in which the precharge is performed by the banks. In the all-bank precharge operation, a peak current is increased since the precharge of the banks is performed at the same time, which will be described with reference toFIG. 1illustrating a timing diagram of operation of a conventional bank precharge signal generation circuit.

As illustrated, if an all-bank precharge signal ICAR<4> is at a high level when a pulse of a precharge signal PCGP is inputted, an all-bank precharge operation is initiated. That is to say, when the all-bank precharge signal (ICAR<4> of a high level and a precharge pulse of a high level are inputted, first through eighth bank precharge signals PCGP_BA<0:7> for precharging first through eighth banks, respectively, in a semiconductor memory device with a eight-bank structure are enabled to a high level at the same time (point X).

As such, simultaneous initiation of the precharge operation on the first through eighth banks sharply increases the peak current consumed at a time point of initiation of the all-bank precharge operation and the sharp increase in the peak current causes deterioration of noise immunity and mobile reception sensitivity.

BRIEF SUMMARY

In an embodiment of this disclosure, there is provided a bank precharge signal generation circuit that sequentially precharges a plurality of banks with predetermined delay periods in an all-bank precharge operation to reduce a peak current, and thereby noise immunity and mobile reception sensitivity can be enhanced.

In an embodiment, a bank precharge signal generation circuit includes a precharge signal generation unit for generating a second precharge signal including a pulse, which is generated in a period delayed by a predetermined period as compared to a pulse of a first precharge signal, in response to an all-bank precharge signal, and a bank precharge signal generation unit for receiving the first and second precharge signals and generate first and second bank precharge signals for precharging first and second banks.

In another embodiment, a bank precharge signal generation circuit includes a first bank precharge signal generation unit for generating a first bank precharge signal enabled when a pulse of a first precharge signal is inputted in a state that an all-bank precharge signal is enabled, and a second bank precharge signal generation unit for generating a second bank precharge signal enabled when a pulse of a second precharge signal is inputted in a state that an all-bank precharge signal is enabled, wherein the pulse of the second precharge signal is inputted, with the pulse of the second precharge signal being delayed by a predetermined period as compared to the pulse of the first precharge signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, an embodiment of the present invention will be described with reference to accompanying drawings. The embodiment is for illustrative purposes only, and the scope of the present invention is not limited thereto.

FIG. 2is a block diagram illustrating a configuration of a bank precharge signal generation circuit in accordance with an embodiment of the present invention.

The bank precharge signal generation circuit illustrated inFIG. 2includes a precharge signal generation unit1and a bank precharge signal generation unit2. The precharge signal generation unit1includes a delayed signal generation unit10and a delayed signal processing unit12.

The delayed signal generation unit10includes, as shown inFIG. 3, a logic unit100which receives a first precharge signal PCGP1and an all-bank precharge signal ICAR<4> and generates a control signal S1and an inverted control signal S1B, a transfer gate T10which transfers the first precharge signal PCGP1in response to the control signal S1and the inverted control signal S1B, a first delay unit101which delays an output signal of the transfer gate T10by a predetermined period to generate a first delayed precharge signal PCGd1, a second delay unit102which delays an output signal of the first delay unit101by a predetermined period to generate a second delayed precharge signal PCGd2, a third delay unit103which delays an output signal of the second delay unit102by a predetermined period to generate a third delayed precharge signal PCGd3, a fourth delay unit104which delays the first precharge signal PCGP1by a predetermined period, a transfer gate T11which transfers an output signal of the fourth delay unit104in response to the control signal S1and the inverted control signal S1B, and an NMOS transistor N10which initializes a node nd11to a low level in response to a power up signal PWRUP in a power up period. Here, the first precharge signal PCGP1is a signal which is inputted as a pulse for the bank precharge operation, and the all-bank precharge signal ICAR<4> is a signal which is at a low level in a single-bank precharge operation and is at a high level in the all-bank precharge operation.

The delayed signal generation unit10having the aforementioned configuration generates the first through third delayed precharge signal PCGd1-PCGd3which are all at a low level in response to the all-bank precharge signal ICAR<4> at a low level in the single-bank precharge operation, and delays the first precharge signal PCGP1by the period of the fourth delay unit104to generate the fourth delayed precharge signal PCGd4. Also, the delayed signal generation unit10generates the fourth delayed precharge signal PCGd4of a low level in response to the first precharge signal PCGP1and the all-bank precharge signal ICAR<4>, both of which are at a high level in the all-bank precharge operation, delays the first precharge signal PCGP1by the delay period of the first delay unit101to generate the first delayed precharge signal PCGd1, delays the output signal of the first delay unit101by the delay period of the second delay unit102to generate the second delayed precharge signal PCGd2, delays the output signal of the second delay unit102by the delay period of the third delay unit103to generate a third delayed precharge signal PCGd3.

The delayed signal processing unit12includes, as shown inFIG. 4, a logic unit120which performs a logic OR operation on the first delayed precharge signal PCGd1and the fourth delayed precharge signal PCGd4inputted thereto, to generate a second precharge signal PCGP2, a logic unit121which performs a logic OR operation on the second delayed precharge signal PCGd2and the fourth delayed precharge signal PCGd4inputted thereto, to generate a third precharge signal PCGP3, and a logic unit122which performs a logic OR operation on the third delayed precharge signal PCGd3and the fourth delayed precharge signal PCGd4inputted thereto, to generate a fourth precharge signal PCGP4.

The delayed signal processing unit12having the aforementioned configuration buffers the fourth delayed precharge signal PCGd4in response to the first through third delayed precharge signals PCGd1-PCGd3, which are all at a low level in the single-bank precharge operation, to generate the second through fourth precharge signals PCGP2-PCGP4. Meanwhile, in response to the fourth delayed precharge signal PCGd4at a low level in the all-bank precharge operation, the delayed signal processing unit12buffers the first delayed precharge signal PCGd1to generate the second precharge signal PCGP2, buffers the second delayed precharge signal PCGd2to generate the third precharge signal PCGP3and buffers the third delayed precharge signal PCGd3to generate the fourth precharge signal PCGP4.

The bank precharge signal generation unit2includes, as shown inFIG. 5, first through fourth bank precharge signal generation units20-23. Here, the first through fourth bank precharge signal generation units20-23have the same configuration except for signals input thereto and signals output therefrom, and thus a detailed description of configuration of the first bank precharge signal generation unit20only will be provided below.

The first bank precharge signal generation unit20includes a PMOS transistor P20which is connected between a power voltage and a node nd20and turned on in response to the first precharge signal PCGP1, an NMOS transistor N200which is connected between the node nd20and a node nd21and turned on in response to the first precharge signal PCGP1, an NMOS transistor N201which is connected between the node nd21and a ground voltage VSS and turned on in response to a first bank selection signal BANKT<0>, a logic unit200which performs a logic operation on the all-bank precharge signal ICAR<4> and the ground voltage VSS inputted thereto, an NMOS transistor N202which is connected between the node nd21and the ground voltage VSS and turned on in response to an output signal of the logic unit200, an inverter IV20which inverts a signal of the node nd20to generate first and second bank precharge signal PCGPBA<0:1>, and a PMOS transistor P21which is turned on in response to the first and second bank precharge signal PCGPBA<0:1>.

The first bank precharge signal generation unit20having the aforementioned configuration enables, in a state that a pulse of the first precharge signal PCGP1is inputted in the single-bank precharge operation, the first bank precharge signal PCGPBA<0> to a high level when the first bank selection signal BANKT<0> is inputted with a high level, and enables the second bank precharge signal PCGPBA<1> to a high level when the second bank selection signal BANKT<1> is inputted with a high level. Here, the first and second bank selection signals BANKT<0:1> are signals for respectively selecting first and second banks, and the first and second bank precharge signals PCGPBA<0:1> are signals for respectively precharging the first and second banks. Meanwhile, the first bank precharge signal generation unit20enables both the first and second bank precharge signals PCGPBA<0:1> to a high level to thereby precharge the first and second banks when pulse of the first precharge signal PCGP1is inputted and the all-bank precharge signal ICAR<4> is at a high level in the all-bank precharge operation.

Since the second through fourth bank precharge signal generation units21-23have the same circuit configuration as the first bank precharge signal generation unit20as described above, the configurations thereof will not be described and only the operations thereof will be described hereinafter. The second through fourth bank precharge signal generation units21-23precharge a bank selected by a signal of the third through eighth bank selection signals BANKT<3:8>, which is inputted with a high level, when a pulse of the second precharge signal PCGP2in the single-bank precharge operation. Meanwhile, the second through fourth bank precharge signal generation units21-23enable both the third and fourth bank precharge signals PCGPBA<2:3> to a high level to precharge third and fourth banks when the pulse of the second precharge signal PCGP2is inputted and the all-bank precharge signal ICAR<4> is at a high level in the all-bank precharge operation, enables both the fifth and sixth bank precharge signals PCGPBA<4:5> to a high level to precharge fifth and sixth banks when the pulse of the third precharge signal PCGP3is inputted, and enables both the seventh and eighth bank precharge signals PCGPBA<6:7> to a high level to precharge seventh and eighth banks when the pulse of the fourth precharge signal PCGP4is inputted.

Hereinafter, operation of the bank precharge signal generation circuit will be described with respect to the single-bank precharge operation and the all-bank precharge operation.

First, the single-bank precharge operation will be described.

The logic unit100of the delayed signal generation unit10receives the all-bank precharge signal ICAR<4> of a low level and generates the control signal S1of a high level and the inverted control signal S1B (of a low level) to turn on the transfer gate T10and turn off the transfer gate T11. Therefore, the delayed signal generation unit10generates the first through third delayed precharge signals PCGd1-PCGd3, which are all at a low level in response to the signal of the node nd11driven at a low level the power up period, and delays the first precharge signal PCGP1by the delay period of the fourth delay unit104to generate PCGd4.

Next, the delayed signal processing unit12buffers the fourth delayed precharge signal PCGd4when the first through third delayed precharge signals PCGd1-PCGd3are all at a low level in the single-bank precharge operation, to generate the second through fourth precharge signal PCGP2-PCGP4.

Next, the bank precharge signal generation unit2enables the bank selection signal for precharging the selected bank when a pulse of the precharge signal is inputted in response to the all-bank precharge signal ICAR<4> of a low level. For example, the bank precharge signal generation unit2enables the second bank precharge signal PCGPBA<1> for precharging the second bank to a high level if the second bank selection signal BANKT<1> for selecting the second bank is at a high level when a pulse of the first precharge signal PCGP1is inputted, and enables the fourth bank precharge signal PCGPBA<3> for precharging the fourth bank to a high level if the fourth bank selection signal BANKT<3> for selecting the fourth bank is at a high level when a pulse of the second precharge signal PCGP2is inputted.

Second, the all-bank precharge operation will be described.

The logic unit100of the delayed signal generation unit10receives the all-bank precharge signal ICAR<4> of a high level and the first precharge signal PCGP1and generates the control signal S1of a low level and the inverted control signal S1B of a high level to turn on the transfer gate T10and turn off the control gate T11. Therefore, the delayed signal generation unit10generates the fourth delayed precharge signal PCGd4of a low level, generates the first delayed precharge signal PCGd1a pulse of which is generated in a period delayed by the delayed period of the first delay unit101from a period where the pulse of the first precharge signal PCGP1is generated, generates the second delayed precharge signal PCGd2a pulse of which is generated in a period delayed by the delayed period of the second delay unit102from a period where the pulse of the first delayed precharge signal PCGd1is generated, and generates the third delayed precharge signal PCGd3a pulse of which is generated in a period delayed by the delayed period of the third delay unit103from a period where the pulse of the second delayed precharge signal PCGd2is generated. In other words, in the all-bank precharge operation, the pulses of the first through third delayed precharge signals PCGd1-PCGd3generated in the delayed signal generation unit10are sequentially produced.

Next, The delayed signal processing unit12buffers the first delayed precharge signal PCGd1, in response to the fourth delayed precharge signal PCGd4at a low level in the all-bank precharge operation, to generate the second precharge signal PCGP2, buffers the second delayed precharge signal PCGd2to generate the third precharge signal PCGP3, and buffers the third delayed precharge signal PCGd3to generate the fourth precharge signal PCGP4.

Next, the bank precharge signal generation unit2receives the all-bank precharge signal ICAR<4> of a high level and the pulse of the first precharge signal PCGP1and generate the first and second bank precharge signals PCGPBA<0:1> enabled to a high level. Therefore, the first and second banks are precharged at the same time. Also, the bank precharge signal generation unit2generates the third and fourth bank precharge signals PCGPBA<2:3> of a high level to precharge the third and fourth banks at the same time when the pulse of the second precharge signal PCGP2is inputted, generates the fifth and sixth bank precharge signals PCGPBA<4:5> of a high level to precharge the fifth and sixth banks at the same time when the pulse of the third precharge signal PCGP3is inputted, and generates the seventh and eighth bank precharge signals PCGPBA<6:7> of a high level to precharge the seventh and eighth banks at the same time when the pulse of the fourth precharge signal PCGP4is inputted.

As described above, when performing the all-bank precharge operation by the bank precharge signal generation circuit of the present embodiment, as shown in (Y) ofFIG. 6, the first and second bank precharge signals PCGPBA<0:1> for precharging the first and second banks are enabled to a high level, and the third and fourth bank precharge signals PCGPBA<2:3> for precharging the third and fourth banks are then enabled to a high level. Also, after lapse of a predetermined period, the fifth and sixth bank precharge signals PCGPBA<4:5> for precharging the fifth and sixth banks are enabled to a high level, and the seventh and eighth bank precharge signals PCGPBA<6:7> for precharging the seventh and eighth banks are then enabled to a high level.

As such, the bank precharge signal generation circuit of the present embodiment, unlike the conventional circuit, does not precharge all of the banks but sequentially precharges two banks at a time in the all-bank precharge operation. Therefore, as shown in (Z) ofFIG. 7, in the bank precharge signal generation circuit of the present embodiment, the peak current consumed at a time point where the all-bank precharge operation is initiated is significantly reduced as compared to the conventional circuit.

The present application claims priority to Korean application number 10-2009-0011596, filed on Feb. 12, 2009, which is incorporated by reference in its entirety.