SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device according to the present embodiment includes a semiconductor chip including a first chip and a second chip. The second chip is joined to the first chip on the first chip such that the second chip is electrically connected to the first chip. The area of the second chip is smaller than the area of the first chip. The second chip is provided in a first region on an upper surface of the first chip and the first chip includes a first pad exposed from the first chip in a second region different from the first region.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2023-025399, filed on Feb. 21, 2023, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof.

BACKGROUND

In a semiconductor in which two wafers are bonded, an unnecessary region increases when there is a mismatch between the sizes (areas) of semiconductor elements of the respective wafers.

DETAILED DESCRIPTION

Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments. It should be noted that the drawings are schematic or conceptual, and the relationship between the thickness and the width in each element and the ratio among the dimensions of elements do not necessarily match the actual ones. Even if two or more drawings show the same portion, the dimensions and the ratio of the portion may differ in each drawing. In the present specification and the drawings, elements identical to those described in the foregoing drawings are denoted by like reference characters and detailed explanations thereof are omitted as appropriate.

A semiconductor device according to the present embodiment includes a semiconductor chip including a first chip and a second chip. The second chip is joined to the first chip on the first chip such that the second chip is electrically connected to the first chip. The area of the second chip is smaller than the area of the first chip. The first chip further includes a first pad exposed from the first chip in a second region, which is different from a first region in which the second chip is provided on an upper surface of the first chip.

First Embodiment

FIG.1is a cross sectional view illustrating an example of the configuration of a semiconductor device1according to a first embodiment.FIG.2is a plan view illustrating the example of the configuration of the semiconductor device1according to the first embodiment. Line A-A inFIG.2indicates a section corresponding to the cross sectional view ofFIG.1.

FIGS.1and2illustrate an X direction and a Y direction parallel to a front surface of a wiring substrate10and orthogonal to each other, and a Z direction orthogonal to the front surface of the wiring substrate10. In the present specification, the positive Z direction is an upward direction, and the negative Z direction is a downward direction. The negative Z direction may or may not be aligned with the direction of gravity.

The semiconductor device1includes the wiring substrate10, semiconductor chips20and30to33, bonding layers40to43, a spacer50, a resin layer80, a bonding wire90, and a sealing resin91. The semiconductor device1is, for example, a packaged NAND type flash memory.

The wiring substrate10may be a printed circuit board or interposer including wiring layers11and an insulating layer15. A low resistance metal such as copper (Cu), nickel (Ni), or alloy thereof is used as the wiring layers11. An insulating material such as glass epoxy resin is used as the insulating layer15. In the diagrams, the wiring layers11are provided only on front and back surfaces of the insulating layer15. However, the wiring substrate10may include a multi-layer wiring structure formed by stacking a plurality of wiring layers11and a plurality of insulating layers15. The wiring substrate10may include a penetration electrode (column-shaped electrode) penetrating through front and back surfaces thereof like an interposer.

A solder resist layer14provided on a wiring layer11is provided on the front surface (surface F1) of the wiring substrate10. The solder resist layer14is an insulating layer for protecting the wiring layer11from a metallic material (not illustrated) connecting the semiconductor chip20and the wiring layers11and for preventing short-circuit defect.

Another solder resist layer14provided on a wiring layer11is provided on a back surface of the wiring substrate10. Metal bumps13are provided on the wiring layer11exposed through the solder resist layer14. The metal bumps13are provided to electrically connect a non-illustrated other component to the wiring substrate10.

The semiconductor chip20is, for example, a controller chip configured to control a memory chip. A non-illustrated semiconductor element is provided on a surface of the semiconductor chip20facing the wiring substrate10. The semiconductor element may be, for example, a complementary metal oxide semiconductor (CMOS) circuit constituting a controller. An electrode pillar (not illustrated) electrically connected to the semiconductor element is provided on a back surface (lower surface) of the semiconductor chip20. A low resistance metallic material such as copper, nickel, or alloy thereof is used as the electrode pillar.

A metallic material is provided around the electrode pillar as a connection bump. The electrode pillar is electrically connected through the metallic material to the wiring layer11exposed at an opening part of the solder resist layer14. A low resistance metallic material such as solder, silver, or copper is used as the metallic material. Accordingly, the metallic material electrically connects the electrode pillar of the semiconductor chip20and the wiring layer11of the wiring substrate10.

The resin layer80is provided in a region around the metallic material and a region between the semiconductor chip20and the wiring substrate10. The resin layer80is, for example, cured underfill resin and covers and protects the circumference of the semiconductor chip20.

The semiconductor chip30is, for example, a memory chip including an NAND type flash memory. The semiconductor chip30is provided with a semiconductor element (not illustrated) on its front surface (upper surface). The semiconductor element may be, for example, a memory cell array and its peripheral circuit (CMOS circuit). The memory cell array may be a stereoscopic memory cell array in which a plurality of memory cells are three-dimensionally disposed. The semiconductor chip31is bonded on the semiconductor chip30with the bonding layer41interposed therebetween. The semiconductor chip32is bonded on the semiconductor chip31with the bonding layer42interposed therebetween. The semiconductor chip33is bonded on the semiconductor chip32with the bonding layer43interposed therebetween. Similarly to the semiconductor chip30, the semiconductor chips31to33are, for example, memory chips including an NAND type flash memory. The semiconductor chips30to33may be the same memory chip. In the diagrams, the semiconductor chip20as a controller chip as well as the semiconductor chips30to33as four memory chips are stacked. However, the number of stacked semiconductor chips may be three or less or may be five or more.

As illustrated inFIG.2, the spacer50is provided, for example, on a side of the semiconductor chip20. The spacer50is bonded to the front surface (upper surface) of the wiring substrate10with a bonding layer interposed therebetween. The semiconductor chips30to33are provided above the spacer50and the semiconductor chip20. The material of the spacer50is, for example, silicon (Si) or polyimide.

The bonding wire90is connected to the wiring substrate10and optional pads of the semiconductor chips30to33. For the connection through the bonding wire90, the semiconductor chips30to33are stacked while being displaced as corresponding to the pads. The semiconductor chip20is flip-chip connected through the electrode pillar and thus not wire-bonded. However, the semiconductor chip20may be wire-bonded in addition to the connection through the electrode pillar.

The sealing resin91seals the semiconductor chips20and30to33, the bonding layers40to43, the spacer50, the bonding wire90, and the like. Accordingly, in the semiconductor device1, the plurality of semiconductor chips20and30to33are constituted as one semiconductor package on the wiring substrate10.

Details of the semiconductor chips30to33will be described below.

FIG.3is a cross sectional view illustrating the example of the configuration of the semiconductor device1according to the first embodiment.FIG.3illustrates the semiconductor chip30. Although the semiconductor chip30will be described below, the semiconductor chips31to33have the same configuration as the semiconductor chip30. Since the semiconductor chip30will be described in detail in the example illustrated inFIG.3, illustration of the semiconductor chip20inFIG.1is omitted.

FIG.4is a cross sectional view illustrating an example of the configuration of the semiconductor device1according to the first embodiment.FIG.4illustrates a diagram in which the four semiconductor chips30to33are stacked. The right and left directions are inverted betweenFIGS.3and4.

The semiconductor chip30includes a circuit chip CH1, an array chip CH2, and a spacer101. The circuit chip CH1is an example of a first chip. The array chip CH2is an example of a second chip.

The circuit chip CH1functions as a control circuit (logic circuit) configured to control operation of the array chip CH2.

The circuit chip CH1includes a semiconductor substrate111, an interlayer insulating film112, transistors (semiconductor elements)113, metal pads BP1, and a metal pad WP.

The semiconductor substrate111is provided on a lower surface side of the circuit chip CH1. The semiconductor substrate111is, for example, a silicon (Si) substrate.

The interlayer insulating film112is provided on the semiconductor substrate111. The interlayer insulating film112is, for example, a silicon oxide film or a multilayer film including a silicon oxide film and any other insulating film.

The plurality of transistors113are provided above the semiconductor substrate111. The transistors113constitute a CMOS circuit as a control circuit of a memory cell array123of the array chip CH2. The control circuit is electrically connected to the metal pads BP1.

The metal pads BP1are provided at a joining surface (bonding surface) S to the array chip CH2. The metal pads BP1are joined to metal pads BP2of the array chip CH2. The plurality of metal pads BP1are, for example, Cu layers.

The metal pad WP is provided inside the circuit chip CH1. The metal pad WP is exposed from the circuit chip CH1in a second region, which is different from a first region R1in which the array chip CH2is provided on an upper surface of the circuit chip CH1. The metal pad WP functions as an external connection pad (bonding pad) of the semiconductor chips30to33. Specifically, the metal pad WP is connected to the bonding wire90. Accordingly, the bonding wire90electrically connects the metal pad WP and the wiring substrate10. The metal pad WP includes conductive metal such as aluminum (Al). The metal pad WP is an example of a first pad.

The array chip CH2is joined (bonded) to the circuit chip CH1on the circuit chip CH1and electrically connected to the circuit chip CH1. The area of the array chip CH2is smaller than the area of the circuit chip CH1. The areas of the circuit chip CH1and the array chip CH2are areas when viewed in the Z direction.

The array chip CH2includes a semiconductor substrate121, an interlayer insulating film122, the memory cell array (semiconductor element)123, a contact plug C1, and the metal pads BP2.

The semiconductor substrate121is provided on an upper surface side of the array chip CH2. The semiconductor substrate121is, for example, a silicon (Si) substrate.

The interlayer insulating film122is provided below the semiconductor substrate121. The interlayer insulating film122is, for example, a silicon oxide film or a multilayer film including a silicon oxide film and any other insulating film.

The memory cell array123is provided below the semiconductor substrate121. The memory cell array123is, for example, a non-volatile memory. The memory cell array123includes a staircase structure part. The memory cell array123is electrically connected to the metal pads BP2.

The contact plug C1electrically connects a conductive layer (word line WL) of the memory cell array123and the metal pads BP2.

The metal pads BP2are provided at the joining surface S to the circuit chip CH1. The metal pads BP2are joined to the metal pads BP1of the circuit chip CH1. The plurality of metal pads BP2are, for example, Cu layers.

The spacer101is provided in a second region R2different from a first region R1in which the array chip CH2is provided on the upper surface of the circuit chip CH1. An upper surface of the spacer101is substantially parallel to the upper surface of the array chip CH2. Specifically, a stepped part formed due to the area difference between the circuit chip CH1and the array chip CH2can be substantially flattened by the spacer101. The spacer101of the semiconductor chip30supports the semiconductor chip31as illustrated inFIG.4. Accordingly, the risk of chip tilt or the like at assembly can be reduced. Thus, the area of the upper surface of the array chip CH2can be increased and stacking (die bonding) of the semiconductor chips30to33can be more appropriately performed.

The spacer101is provided apart from the bonding wire90. The spacer101includes a recessed part106. The recessed part106penetrates from an upper surface of the spacer101to a lower surface thereof. Accordingly, the upper surface of the circuit chip CH1is exposed at a bottom surface of the recessed part106. The bonding wire90extends through the recessed part106and is connected to the metal pad WP.

The spacer101includes resin. The resin is light-sensitive at manufacturing of the spacer101. The resin includes, for example, epoxy resin. Alternatively, the resin may include at least one kind of poly benzo oxazole resin, phenol resin, and the like. In a case where the spacer101includes resin, the spacer101includes a filler F. Since the filler F exists on an inner surface of the recessed part106, the recessed part106needs to have a large opening area (opening diameter) for connecting the bonding wire90to the metal pad WP.

The configuration of the memory cell array123and the transistors113will be described below.

FIG.5is a cross sectional view illustrating an example of the configuration of the memory cell array123and the transistors113according to the first embodiment.

The array chip CH2includes a plurality of word lines WL and a source line SL as electrode layers in the memory cell array123.FIG.5illustrates a staircase structure part201of the memory cell array123. Each word line WL is electrically connected to a word wiring layer202through the contact plug C1. A column-shaped part CL penetrating through the plurality of word lines WL is electrically connected to a bit line BL through a via plug203and electrically connected to the source line SL. The source line SL includes a first layer SL1that is a semiconductor layer, and a second layer SL2that is a metal layer.

The circuit chip CH1includes the plurality of transistors113. Each transistor113includes a gate electrode301provided on the semiconductor substrate111with a gate insulating film interposed therebetween, and a source diffusion layer and a drain diffusion layer provided in the semiconductor substrate111, which are not illustrated. The circuit chip CH1includes a plurality of contact plugs302each provided on the gate electrode301, the source diffusion layer, or the drain diffusion layer of a transistor113, a wiring layer303provided on the contact plugs302and including a plurality of pieces of wiring, and a wiring layer304provided on the wiring layer303and including a plurality of pieces of wiring.

The circuit chip CH1also includes a wiring layer305provided on the wiring layer304and including a plurality of pieces of wiring, a plurality of via plugs306provided on the wiring layer305, and the plurality of metal pads BP1provided on the via plugs306. The metal pads BP1are, for example, Cu (copper) layers or Al (aluminum) layers.

The array chip CH2includes the plurality of metal pads BP2provided on the metal pads BP1, and a plurality of via plugs307provided on the metal pads BP2. The array chip CH2also includes a wiring layer308provided on the via plugs307and including a plurality of pieces of wiring. The metal pads BP2are, for example, Cu layers or Al layers.

FIG.6is a cross sectional view illustrating an example of the configuration of the column-shaped part CL according to the first embodiment.

As illustrated inFIG.6, the memory cell array123includes the plurality of word lines WL and a plurality of insulating layers401alternately stacked on the interlayer insulating film122(FIG.5). Each word line WL is, for example, a W (tungsten) layer. Each insulating layer401is, for example, a silicon oxide film.

The column-shaped part CL sequentially includes a block insulating film402, an electric charge accumulation layer403, a tunnel insulating film404, a channel semiconductor layer405, and a core insulating film406. The electric charge accumulation layer403is, for example, a silicon nitride film and formed on side surfaces of the word lines WL and the insulating layers401with the block insulating film402interposed therebetween. The electric charge accumulation layer403may be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer405is, for example, a polysilicon layer and formed on a side surface of the electric charge accumulation layer403with the tunnel insulating film404interposed therebetween. The block insulating film402, the tunnel insulating film404, and the core insulating film406are each, for example, a silicon oxide film or a metal insulating film.

A method of manufacturing the semiconductor device1will be described below.

FIGS.7A to7Hare cross sectional views illustrating an example of the method of manufacturing the semiconductor device1according to the first embodiment.

First, as illustrated inFIG.7A, the metal pad WP is formed on a circuit wafer W1. The metal pad WP is, for example, an Al layer. The CMOS circuit constituted by the transistors113is already formed in a layer below the metal pad WP.

Subsequently, as illustrated inFIG.7B, the interlayer insulating film112is formed on the metal pad WP and ground. Accordingly, a step due to the metal pad WP can be flattened. The formation of the interlayer insulating film112is performed by, for example, chemical vapor deposition (CVD). The grinding of the interlayer insulating film112is performed by, for example, chemical mechanical polishing (CMP).

Subsequently, as illustrated inFIG.7C, the wiring layers303,304, and305, the metal pads BP1, and the like are formed. The wiring layers303,304, and305and the metal pads BP1are electrically connected to the metal pad WP. The wiring layers303,304, and305and the metal pads BP1are, for example, Cu layers.

Subsequently, as illustrated inFIG.7D, a plurality of array chips CH2are joined to the circuit wafer W1. The metal pads BP1and the metal pads BP2illustrated inFIG.3are joined to each other. Accordingly, each array chip CH2is joined to the circuit wafer W1such that the circuit wafer W1(circuit chip CH1) is electrically connected to the array chip CH2.

FIG.8is a diagram illustrating an example of the sizes of the circuit chip CH1and the array chip CH2according to the first embodiment. The size of each chip relative to a wafer is not limited to that in the example illustrated inFIG.8.

As illustrated inFIG.8, the area of the array chip CH2is smaller than the area of the circuit chip CH1. Accordingly, as illustrated inFIG.7D, the first region R1in which the array chip CH2is provided and the second region R2in which no array chip CH2is provided exist on the upper surface of the circuit chip CH1(circuit wafer W1).

Subsequently, as illustrated inFIG.7E, a member115is formed, and the recessed part106is formed in the member115. The member115is formed on the circuit wafer W1and the array chip CH2. The recessed part106is formed by partially removing the member115at a position where the metal pad WP is to be exposed. The recessed part106is formed in a region in which the metal pad WP is provided. The interlayer insulating film112is exposed at the bottom surface of the recessed part106.

The member115includes a light-sensitive material such as light-sensitive resin. In this case, the recessed part106is formed by performing exposure and image development of the member115. The light-sensitive material may be any of a positive light-sensitive material and a negative light-sensitive material. The light-sensitive material may include at least one kind of light-sensitive epoxy resin, light-sensitive poly benzo oxazole resin, light-sensitive phenol resin, and the like.

Subsequently, as illustrated inFIG.7F, a recessed part1121is formed in the interlayer insulating film112. The recessed part1121is formed by, for example, reactive ion etching (RIE). The recessed part1121communicates with the recessed part106. The metal pad WP is exposed at a bottom surface of the recessed part1121. Accordingly, the metal pad WP is exposed in the second region R2.

Subsequently, as illustrated inFIG.7H, dicing and back grinding are performed. Accordingly, the circuit wafer W1is singulated into a plurality of circuit chips CH1(semiconductor chips30to33). The spacer101illustrated inFIG.3is formed through the dicing of the member115.

Thereafter, the semiconductor chips30to33formed through the process illustrated inFIG.7Hare mounted on the wiring substrate10and a package assembling process is performed. Accordingly, the semiconductor device1illustrated inFIGS.1to3is completed.

The order illustrated inFIGS.7A to7His an example. For example, the process illustrated inFIG.7Fmay be performed after the process illustrated inFIG.7G.

InFIGS.7A to7C, the metal pad WP may be formed in the same layer as the wiring layers303,304, and305and the metal pads BP1. In this case, the metal pad WP is a Cu layer. The metal pad WP may be formed of conductive metal other than Al and Cu.

InFIG.7D, it is difficult to join thin array chips CH2to the circuit wafer W1(chip bonding) in some cases. In such a case, chip bonding may be performed with array chips CH2being thick to some extent, and thereafter, the array chips CH2may be thinned.

In the process illustrated inFIG.7E, the member115may be flattened before exposure and image development of the member115. Accordingly, pattern formation through exposure can be more appropriately performed.

As described above, according to the first embodiment, the area of each array chip CH2is smaller than the area of each circuit chip CH1. The circuit chip CH1includes the metal pad WP exposed from the circuit chip CH1in the second region R2, which is different from the first region R1in which the array chip CH2is provided on the upper surface of the circuit chip CH1. Accordingly, as illustrated inFIG.8, it is possible to reduce waste on the array wafer W2along with miniaturization of the memory cell array123. Thus, it is possible to form a larger number of array chips CH2on the array wafer W2.

Comparative Example

FIG.9is a cross sectional view illustrating an example of the configuration of a semiconductor device1aaccording to a comparative example. The comparative example is different from the first embodiment in that the area of the array chip CH2is substantially equal to the area of the circuit chip CH1.

FIG.10is a diagram illustrating an example of the sizes of the circuit chip CH1and the array chip CH2according to the comparative example.

As illustrated inFIG.10, the area of the array chip CH2is substantially equal to the area of the circuit chip CH1. In the comparative example, the semiconductor chips30to33are formed by bonding the circuit wafer W1and the array wafer W2to each other and singulating the bonded wafers. However, a mismatch between the element area of the array chip CH2and the element area of the circuit chip CH1increases along with miniaturization of the memory cell array123. In this case, as illustrated inFIGS.9and10, the area of a region WA increases as the element area of the memory cell array123decreases. The region WA is an unnecessary region in which the memory cell array123is not provided on the array chip CH2.

However, in the first embodiment, a plurality of array chips CH2are joined to the circuit wafer W1as illustrated inFIG.7D. As illustrated inFIG.8, the memory cell array123is formed without providing the unnecessary region WA on the array wafer W2. Accordingly, the unnecessary region WA can be eliminated, and a larger number of array chips CH2can be formed on the array wafer W2.

Another comparative example in which the metal pad WP is provided on the upper surface of the array chip CH2will be described below. In the semiconductor chips30to33illustrated inFIG.3, for example, the metal pad WP is provided on the upper surface of the array chip CH2as illustrated inFIG.9. However, in this case, a film needs to be formed on a surface (refer toFIG.7G, for example) where the semiconductor substrate121and the member115(spacer101) exist in mixture. The film is formed by, for example, a spin coat method. The film includes, for example, a protective film (passivation film) or a resist. The protective film is, for example, an insulating film124illustrated inFIG.5and includes, for example, polyimide. Since the semiconductor substrate121and the member115exist in mixture on the surface, it is difficult to appropriately (for example, uniformly) form the film. As a result, it is difficult to form the metal pad WP.

However, in the first embodiment, as illustrated inFIG.7E, the member115in which the array chip CH2is embedded includes the light-sensitive material. Thus, fabrication can be performed toward the metal pad WP on the lower side of the member115. Accordingly, it is possible to more easily form the metal pad WP. Moreover, in the first embodiment, fabrication such as lithography is not performed on the surface on which the semiconductor substrate121and the member115exist in mixture. Thus, it is possible to simplify fabrication for forming the metal pad WP since the metal pad WP is not provided on the upper surface of the array chip CH2.

Second Embodiment

FIG.11is a cross sectional view illustrating an example of the configuration of the semiconductor device1according to a second embodiment. The second embodiment is different from the first embodiment in the material of the spacer101.

The resin included in the spacer101is polyimide. The polyimide resin of the present embodiment includes no filler F. The polyimide resin of the present embodiment is light-sensitive at manufacturing. Since no filler F is included, the opening area of the recessed part106can be smaller than in the first embodiment in manufacturing through exposure and image development as in the first embodiment.

The material of the spacer101may be changed as in the second embodiment. With the semiconductor device1according to the second embodiment, it is possible to obtain the same effects as in the first embodiment. By using light-sensitive resin including no filler F, it is possible to obtain the same effects as in the second embodiment even in a case where the resin is other than polyimide.

Third Embodiment

FIG.12is a cross sectional view illustrating an example of the configuration of the semiconductor device1according to a third embodiment. The third embodiment is different from the first embodiment in the shape of the spacer101.

The upper surface of the spacer101is not flat. In a case where the array chip CH2has a relatively large thickness in the Z direction, the upper surface of the spacer101has a slope as illustrated inFIG.12in some cases.

The upper surface of the spacer101is positioned lower than the upper surface of the array chip CH2. More specifically, the recessed part106has an upper end positioned lower than the upper surface of the array chip CH2. Accordingly, the bonding wire90can be easily connected to the metal pad WP. Moreover, the opening area of the recessed part106can be reduced.

The shape of the spacer101may be changed as in the third embodiment. With the semiconductor device1according to the third embodiment, it is possible to obtain the same effects as in the first embodiment.

Fourth Embodiment

FIG.13is a cross sectional view illustrating an example of the configuration of the semiconductor device1according to a fourth embodiment. The fourth embodiment is different from the first embodiment in the shape of the spacer101.

The spacer101is provided with a void space in the second region R2in an area on the opposite side of the exposed metal pad WP from the array chip CH2. In other words, the spacer101is not provided in a region outside the semiconductor chip30beyond the metal pad WP connected to the bonding wire90. Accordingly, the bonding wire90can be easily connected to the metal pad WP.

The shape of the spacer101may be changed as in the fourth embodiment. With the semiconductor device1according to the fourth embodiment, it is possible to obtain the same effects as in the first embodiment.

Fifth Embodiment

FIG.14is a cross sectional view illustrating an example of the configuration of the semiconductor device1according to a fifth embodiment. The fifth embodiment is different from the first embodiment in that no spacer101is provided and no member115to be the spacer101after singulation is formed.

Since no spacer101is provided, the bonding wire90can be easily connected to the metal pad WP.

FIGS.15A and15Bare cross sectional views illustrating an example of a method of manufacturing the semiconductor device1according to the fifth embodiment. The process illustrated inFIG.15Ais performed after the same processes as inFIGS.7A to7C.

After the wiring layers303,304, and305, the metal pads BP1, and the like are formed (refer toFIG.7C), the recessed part1121is formed in the interlayer insulating film112as illustrated inFIG.15A. The recessed part1121is formed by, for example, RIE. The recessed part1121extends from an upper surface of the interlayer insulating film112(upper surface of the circuit wafer W1) to the metal pad WP. The metal pad WP is exposed at the bottom surface of the recessed part1121.

Subsequently, as illustrated inFIG.15B, a plurality of array chips CH2are joined to the circuit wafer W1. It is possible to lower difficulty of a lithography process by forming the recessed part1121before joining each array chip CH2.

Thereafter, the circuit wafer W1is singulated into a plurality of circuit chips CH1(semiconductor chips30to33) by dicing and the semiconductor chip30is mounted on the wiring substrate10(refer toFIG.14).

No spacer101may be provided as in the fifth embodiment. With the semiconductor device1according to the fifth embodiment, it is possible to obtain the same effects as in the first embodiment.

Sixth Embodiment

FIG.16is a cross sectional view illustrating an example of the configuration of the semiconductor device1according to a sixth embodiment. The sixth embodiment is different from the first embodiment in the configuration of the spacer101.

The spacer101includes a spacer chip102and a bonding layer103.

An upper surface of the spacer chip (dummy chip)102is substantially parallel to the upper surface of the array chip CH2.

The bonding layer103is provided between the circuit chip CH1and the spacer chip102. The bonding layer103is, for example, a die attach film (DAF).

The spacer chip102includes, for example, silicon (Si). However, the spacer chip is not limited thereto, and for example, may be resin. The spacer chip102preferably includes, for example, a material harder than the spacer101in the first embodiment. Accordingly, the semiconductor chips30to33stacked on the spacer101can be more appropriately supported. Moreover, the spacer chip102preferably includes a material having a thermal expansion coefficient lower than that of the spacer101in the first embodiment. Accordingly, the height of the spacer101can be easily adjusted. As a result, the semiconductor chips30to33stacked on the spacer101can be more appropriately supported.

The configuration of the spacer101may be changed as in the sixth embodiment. With the semiconductor device1according to the sixth embodiment, it is possible to obtain the same effects as in the first embodiment.

Seventh Embodiment

FIG.17is a cross sectional view illustrating an example of the configuration of the semiconductor device1according to a seventh embodiment. The seventh embodiment is different from the first embodiment in the configuration of the semiconductor substrate111.

As illustrated inFIG.17, the semiconductor chip31is stacked on the semiconductor chip30. The semiconductor chip32is stacked on the semiconductor chip31. The semiconductor chip33is stacked on the semiconductor chip32. The two semiconductor chips30and31will be described below.

The semiconductor substrate111included in the circuit chip CH1of the semiconductor chip31has a recessed part1111in which the array chip CH2of the semiconductor chip30is housed. The depth of the recessed part1111in the Z direction corresponds to, for example, the height of the array chip CH2. Accordingly, the semiconductor chip31can be more appropriately supported even in a case where no spacer101is provided.

Similarly to the case of the semiconductor chip31, the semiconductor substrate111included in the circuit chip CH1of each of the semiconductor chips32and33has the recessed part1111. As illustrated inFIG.17, the semiconductor substrate111included in the circuit chip CH1of the semiconductor chip30at the lowermost layer may have no recessed part1111.

The configuration of the semiconductor substrate111may be changed as in the seventh embodiment. With the semiconductor device1according to the seventh embodiment, it is possible to obtain the same effects as in the first embodiment.

Eighth Embodiment

FIG.18is a cross sectional view illustrating an example of the configuration of the semiconductor device1according to an eighth embodiment. The eighth embodiment is different from the first embodiment in the configurations of the bonding layers41to43.

The bonding layer41is provided between the semiconductor chips30and31. The bonding layer42is provided between the semiconductor chips31and32. The bonding layer43is provided between the semiconductor chips32and33. The two semiconductor chips30and31will be described below.

The bonding layer41provided on a lower surface of the semiconductor chip31is provided covering the array chip CH2of the semiconductor chip30. Thus, the bonding layer41is provided thick enough to cover the array chip CH2. Accordingly, the semiconductor chip31can be more appropriately supported even in a case where no spacer101is provided.

Similarly to the bonding layer41, the bonding layers42and43provided on lower surfaces of the semiconductor chips32and33, respectively, are provided thick enough to cover the array chip CH2. As illustrated inFIG.18, the bonding layer40provided on a lower surface of the semiconductor chip30at the lowermost layer does not necessarily need to be provided thick.

The configurations of the bonding layers41to43may be changed as in the eighth embodiment. With the semiconductor device1according to the eighth embodiment, it is possible to obtain the same effects as in the first embodiment.

Ninth Embodiment

FIG.19is a cross sectional view illustrating an example of the configuration of the semiconductor device1according to a ninth embodiment. The ninth embodiment is different from the fifth embodiment in that a metal bump B is provided below the bonding wire90.

The metal pad WP has an upper surface substantially parallel to the upper surface of the circuit chip CH1. The metal pad WP is exposed from the circuit chip CH1at the upper surface of the circuit chip CH1.

The semiconductor device1further includes the metal bump B. The metal bump B is provided on the metal pad WP and connected to the bonding wire90. The metal bump B is provided between the bonding wire90and the metal pad WP.

FIGS.20A to20Care cross sectional views illustrating an example of a method of manufacturing the semiconductor device1according to the ninth embodiment.

First, as illustrated inFIG.20A, the wiring layers303,304, and305, the metal pads BP1and WP, and the like are formed. The wiring layers303,304, and305and the metal pads BP1are electrically connected to the metal pad WP. The wiring layers303,304, and305and the metal pads BP1and WP are, for example, Cu layers. The metal pad WP is exposed from the circuit wafer W1and substantially flat.

Subsequently, as illustrated inFIG.20B, a plurality of array chips CH2are joined to the circuit wafer W1.

Subsequently, as illustrated inFIG.20C, the metal bump B is formed on the metal pad WP. Thus, a bonding pad can be formed without using lithography after the array chips CH2are joined. The metal bump B includes one metal layer or a plurality of stacked metal layers formed by, for example, non-electrolytic plating. Each metal layer includes, for example, Ni, Pd, or Au.

Thereafter, the circuit wafer W1is singulated into a plurality of circuit chips CH1(semiconductor chips30to33) by dicing and the semiconductor chip30is mounted on the wiring substrate10(refer toFIG.19).

The metal bump B may be provided below the bonding wire90as in the ninth embodiment. With the semiconductor device1according to the ninth embodiment, it is possible to obtain the same effects as in the fifth embodiment. The spacer101may be provided as in, for example, the first embodiment. In this case, for example, the same process as the process illustrated inFIG.7Eis performed after the process illustrated inFIG.20Bor after the process illustrated inFIG.20C. Moreover, the spacer chip102may be provided as the spacer101as in the sixth embodiment.

Tenth Embodiment

FIG.21is a cross sectional view illustrating an example of the configuration of the semiconductor device1according to a tenth embodiment. The tenth embodiment is different from the fifth embodiment in that the metal pad WP below the bonding wire90is substantially flat relative to the upper surface of the circuit chip CH1. In other words, the tenth embodiment is different from the ninth embodiment in that no metal bump B is provided.

The upper surface of the metal pad WP is substantially parallel to the upper surface of the circuit chip CH1. The metal pad WP is connected to the bonding wire90.

The process illustrated inFIG.20Cin the ninth embodiment is not performed in the tenth embodiment. Thus, the number of processes can be reduced by using the metal pad WP as a bonding pad.

The metal pad WP below the bonding wire90may be substantially flat relative to the upper surface of the circuit chip CH1as in the tenth embodiment. With the semiconductor device1according to the tenth embodiment, it is possible to obtain the same effects as in the fifth embodiment. The spacer101may be provided as in, for example, the first embodiment. In this case, for example, the same process as the process illustrated inFIG.7Eis performed after the process illustrated inFIG.20B. Moreover, the spacer chip102may be provided as the spacer101as in the sixth embodiment.

Eleventh Embodiment

FIG.22is a cross sectional view illustrating an example of the configuration of the semiconductor device1according to an eleventh embodiment. The eleventh embodiment is different from the first embodiment in that no semiconductor substrate121of the array chip CH2is provided.

The array chip CH2includes no semiconductor substrate121on the upper surface side. Accordingly, the height of the array chip CH2is lowered. In addition, the height of the spacer101is lowered since no semiconductor substrate121is provided. Moreover, the height of the semiconductor package is lowered since the height of the array chip CH2of each of the semiconductor chips30to33is lowered.

In the process illustrated inFIG.7D, the array chip CH2from which the semiconductor substrate121is removed (completely peeled off) in advance may be joined to the circuit wafer W1, or the semiconductor substrate121may be removed (fully peeled off) after the process illustrated inFIG.7D. The removal of the semiconductor substrate121is performed by, for example, wet etching.

No semiconductor substrate121of the array chip CH2may be provided as in the eleventh embodiment. With the semiconductor device1according to the eleventh embodiment, it is possible to obtain the same effects as in the first embodiment.

Other Embodiments

(a) In the above-described embodiments, the array chip CH2of each of the semiconductor chips30to33includes a stereoscopic memory cell array in which a plurality of memory cells are three-dimensionally disposed. Instead, the array chip CH2may be, for example, a two-dimensional memory cell array or an image sensor. Alternatively, the array chip CH2may be any other memory element such as a DRAM or an SRAM instead of a NAND type flash memory. The array chip CH2may be, for example, a CMOS circuit element.