Nanowire transistor structure and nanowire inverter structure

A nanowire transistor structure includes a substrate. A first nanowire is suspended on the substrate. A first gate line crosses and surrounds the first nanowire. The first gate line includes a first end and a second end. A second gate line crosses and surrounds the first nanowire. The second gate line includes a third end and a fourth end. An interlayer dielectric encapsulates the first end, the second end, the third end and the fourth end. A first distance between the first end and the first nanowire is smaller than a third distance between the third end and the first nanowire.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nanowire transistor structure and a nanowire inverter structure.

2. Description of the Prior Art

The integration of hundreds of millions of circuit elements such as transistors on a single integrated circuit necessitates further dramatic scaling down of the physical dimensions of circuit elements. Fabricating microelectronic devices which have higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the microelectronic industry. In order to achieve these highly integrated circuits, a nanowire-based device is introduced. Many different techniques have been attempted to fabricate nanowire device; however, improvements may still be need in the area of forming a nanowire device with high efficiency.

SUMMARY OF THE INVENTION

Accordingly, it is a primary object of the present invention to provide a nanowire transistor structure and a nanowire structure with better efficiency.

According to a preferred embodiment of the present invention, a transistor structure includes a substrate and a first nanowire suspended on the substrate. A first gate line crosses and surrounds the first nanowire, wherein the first gate line has a first end and a second end. A second gate line crosses and surrounds the first nanowire, wherein the second gate line has a third end and a fourth end. An interlayer dielectric layer encapsulates the first end, the second end, the third end and the fourth end. A first distance between the first end and the first nanowire is smaller than a third distance between the third end and the first nanowire.

According to another preferred embodiment of the present invention, a nanowire transistor structure includes a substrate, and a first nanowire suspended on the substrate. A first gate line crosses and surrounds the first nanowire, wherein the first gate line comprises a first end and a second end. A second gate line crosses and surrounds the first nanowire, wherein the second gate line includes a third end and a fourth end. An interlayer dielectric layer encapsulates the first end, the second end, the third end and the fourth end, wherein a first distance between the first end and the first nanowire is larger than a third distance between the third end and the first nanowire.

According to another preferred embodiment of the present invention, an inverter structure includes a substrate comprising a first-type transistor region and a second-type transistor region. A first nanowire is suspended in the first-type transistor region. A second nanowire is suspended in the second-type transistor region, wherein the first nanowire is parallel to the second nanowire. A first gate line is disposed within the first-type transistor region and the second-type transistor region, and is perpendicular to the first nanowire, wherein the first gate line comprises a first end within the first-type transistor region and a second end within the second-type transistor region. A second gate line is disposed within the first-type transistor region and the second-type transistor region, and is perpendicular to the first nanowire, wherein the first gate line comprises a third end within the first-type transistor region, and a fourth end within the second-type transistor region. An interlayer dielectric layer encapsulates the first end, the second end, the third end and the fourth end, wherein a first distance between the first end and the first nanowire is larger than a third distance between the third end and the first nanowire, and a second distance between the second end and the second nanowire is smaller than a fourth distance between the fourth end and the second nanowire.

DETAILED DESCRIPTION

FIG. 1depicts a three-dimensional figure of a nanowire transistor structure according to a first preferred embodiment of the present invention.FIG. 2shows a top view ofFIG. 1.FIG. 3depicts a nanowire transistor structure according to a modification of the first preferred embodiment of the present invention in a top view.FIG. 4depicts another nanowire transistor structure according to a modification of the first preferred embodiment of the present invention in a top view. In the present invention, like reference numerals are used to refer to like elements throughout.

Please refer toFIG. 1andFIG. 2. A nanowire transistor structure10includes a substrate12. A first direction X, a second direction Y and a vertical direction Z are defined on the substrate12. The first direction X and the second direction Y are parallel to a top surface14of the substrate12. The vertical direction Z is perpendicular to the top surface14. The first direction X is perpendicular to the second direction Y. The substrate12includes a fin structure16and a shallow trench isolation (STI)18surrounding the fin structure16. A first nanowire20is suspended on the substrate12. The first nanowire20is disposed directly on the fin structure16and aligned with the fin structure16along the vertical direction Z. The first nanowire20is parallel to the first direction X. A second nanowire22can optionally be suspended on the substrate12. The second nanowire22is disposed directly on the fin structure16and entirely aligned with the fin structure16along the vertical direction Z. The fin structure16may be a semiconductor material such as silicon, germanium, silicon germanium, or silicon carbide. The STI18is preferably silicon oxide or another insulating material. The material of the first nanowire20and the material of the second nanowire22are the same as that of the fin structure16.

A first gate line24crosses and surrounds the first nanowire20. The first gate line24includes a gate and a gate dielectric layer. The gate may be a conductive material such as doped polysilicon or metal. The gate dielectric layer may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbon nitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or high-k dielectrics having a dielectric constant greater than 5. The first gate line24is parallel to the second direction Y. The first gate line24has a first end124and a second end224. A second gate line26crosses and surrounds the first nanowire20. The second gate line26and the first gate line24have the same structure and the same material. The second gate line26is parallel to the first gate line24. The second gate line26has a third end126and a fourth end226. The first end124and the third end126are disposed at the same side of the first nanowire20. The second end224and the fourth end226are both disposed at another side of the first nanowire20. It is noteworthy that a first distance d1between the first end124and the first nanowire20is smaller than a third distance d3between the third end126and the first nanowire20. The first distance d1, the third distance d3and the second direction Y are parallel to each other. Furthermore, a second distance d2between the second end224and the first nanowire20equals a fourth distance d4between the fourth end226and the first nanowire20.

The nanowire transistor structure10preferably further includes a third gate line28which crosses and surrounds the first nanowire20. The first gate line24is disposed between the second gate line26and the third gate line28. The third gate line28and the first gate line24have the same structure and the same material. The third gate line28has a fifth end128and a sixth end228. The first end124and the fifth end128are disposed at the same side of the first nanowire20. The sixth end228and the second end224are both disposed at the same side of the first nanowire20. The first distance d1is smaller than a fifth distance d5between the fifth end128and the first nanowire20. The second distance d2equals a sixth distance d6between the sixth end228and the first nanowire20. The fifth distance d5, the sixth distance d6and the second direction Y are parallel to each other. In the embodiment inFIG. 2, the third distance d3equals the fifth distance d5. In the modification of the nanowire transistor structure10shown inFIG. 3, the third distance d3may not be equal to the fifth distance d5, as long as the third distance d3and the fifth distance d5are both larger than the first distance d1. In the nanowire transistor structure10, except for the first gate line24, each of the other gate lines has at least one end arranged following the rule that: the gate line nearer the first gate line24along the first direction X has an end nearer the first nanowire20along the second direction Y, the gate line farther from the first gate line24along the first direction X has an end farther from the first nanowire20along the second direction Y, and the distance between the end and the first nanowire20is not smaller than the first distance d1.

Furthermore, the first gate line24overlapping the first nanowire20forms a gate structure240. Source/drain doped regions (not shown) can be formed in the first nanowire20at two sides of the gate structure240. The gate structure240, the first nanowire20and the source/drain doped regions form a nanowire transistor100.

The second end224of the first gate line24, the fourth end226of the second gate line26and the sixth end228of the third gate line28can be aligned to each other as shown inFIG. 2andFIG. 3. In other cases, the second end224, the fourth end226and the sixth end228are not aligned as shown inFIG. 4. In details, as shown inFIG. 4, the second distance d2is smaller than the fourth distance d4and the sixth distance d6. The fourth distance d4equals the sixth distance d6. In other embodiments, the second distance d2is smaller than the fourth distance d4and smaller than the sixth distance d6, but the fourth distance d4does not equal the sixth distance d6. Under the circumstance that the second end224, the fourth end226and the sixth end228are not aligned, the efficiency of the nanowire transistor100is twice the efficiency of the nanowire transistor100has the second end224, the fourth end226and the sixth end228aligned. The numbers of the nanowires and the gate lines of the nanowire transistor100in theFIG. 2toFIG. 4can be increased based on different requirements. The added nanowire can be disposed along the vertical direction Z, and be aligned with the first nanowire. The added gate line can be disposed at one side of the second gate line26or the third gate line28. The position of the end of the added gate line can be disposed following the rule mentioned above. For example, as in example (a) ofFIG. 11, a fourth gate line32is added to one side of the second gate line26, and a fifth gate line34is added to one side of the third gate line28. Compared to the second gate line26, the fourth gate line32is farther from the first gate line24along the first direction X; therefore, a seventh distance d7between an end132of the fourth gate line32and the first nanowire20is larger than the third distance d3along the second direction Y. Compared to the third gate line28, the fifth gate line34is farther from the first gate line24along the first direction X; therefore, a ninth distance d9between an end134of the fifth gate line34and the first nanowire20is larger than the fifth distance d5along the second direction Y. Moreover, the first gate line24has an applied voltage. The second gate line26, and the third gate line28may have an applied voltage or be floating.

Please refer toFIG. 2,FIG. 3andFIG. 4. An interlayer dielectric layer30encapsulates the first end124, the second end224, the third end126and the fourth end226, the fifth end128and the sixth end228. The interlayer dielectric layer30and the nanowire transistor100form the nanowire transistor structure10. The interlayer dielectric layer30may be silicon nitride, silicon oxide or other insulating materials. The interlayer dielectric layer30includes stress, and the stress in the interlayer dielectric layer30is applied to the first end124, the second end224, the third end126and the fourth end226, the fifth end128and the sixth end228to change the stress in the nanowire20of the gate structure240; the efficiency of the nanowire transistor100is therefore increased. When the interlayer dielectric layer30is tensile stress, the gate structure240is a gate structure of an N-type transistor, and the nanowire transistor100is an N-type transistor; when the interlayer dielectric layer30is compressive stress, the gate structure240is a gate structure of a P-type transistor, and the nanowire transistor100is a P-type transistor.

FIG. 5depicts a three-dimensional figure of a nanowire transistor structure according to a second preferred embodiment of the present invention.FIG. 6shows a top view ofFIG. 5.FIG. 7depicts a nanowire transistor structure according to a modification of a second preferred embodiment of the present invention in a top view.FIG. 8depicts another nanowire transistor structure according to a modification of a second preferred embodiment of the present invention in a top view. Elements which are substantially the same as those in the first preferred embodiment are denoted by the same reference numerals.

The difference between the first preferred embodiment and the second preferred embodiment is the rule for disposing the end of the gate line. In the second preferred embodiment, except for the first gate line24, each of the other gate lines has at least one end which is arranged following the rule that: the gate line nearer the first gate line24along the first direction X has an end farther from the first nanowire20along the second direction Y, the gate line farther from the first gate line24along the first direction X has an end nearer the first nanowire20along the second direction Y, and the distance between the end and the first nanowire20is not larger than the first distance d1. Other elements such as the substrate12, the first nanowire20, the second nanowire22, the fin structure16, the interlayer dielectric layer30, the first gate line24and the second gate line26are the same as those in the first preferred embodiment, and an accompanying explanation is therefore omitted.

Please refer toFIG. 5andFIG. 6. A nanowire transistor structure10includes a substrate12. A first nanowire20is suspended on the substrate12. The second nanowire22is optionally suspended on the substrate12. The first gate line24crosses and surrounds the first nanowire20. The first gate line24includes a first end124and a second end224. The second gate line26crosses and surrounds the first nanowire20. The second gate line26includes a third end126and a fourth end226. Unlike the first preferred embodiment, in the second embodiment, the first distance d1between the first end124and the first nanowire20is larger than the third distance d3between the third end126and the first nanowire20. The nanowire transistor10preferably further includes a third gate line28which crosses and surrounds the first nanowire20. The first gate line24is disposed between the second gate line26and the third gate line28. The third gate line28has a fifth end128and a sixth end228. The first distance d1is larger than a fifth distance d5between the fifth end128and the first nanowire20. The second distance d2equals a sixth distance d6between the sixth end228and the first nanowire20. The first gate line24overlapping the first nanowire20forms a gate structure240. Source/drain doped regions (not shown) can be formed in the first nanowire20at two sides of the gate structure240. The gate structure240, the first nanowire20and the source/drain doped regions form a nanowire transistor100.

In the embodiment ofFIG. 6, the third distance d3and the fifth distance d5are the same. In other cases as shown inFIG. 7, the third distance d3and the fifth distance d5can be different, as long as the third distance d3and the fifth distance d5are both smaller than the first distance d1. Furthermore, the second end224of the first gate line24, the fourth end226of the second gate line26, and the sixth end228of the third gate line28can be aligned to each other as shown inFIG. 6andFIG. 7. In other cases, the second end224, the fourth end226and the sixth end228are not aligned as shown inFIG. 8. In detail, as shown inFIG. 8, the second distance d2is larger than the fourth distance d4and the sixth distance d6. The fourth distance d4equals the sixth distance d6. In other embodiments, the second distance d2is larger than the fourth distance d4and larger than the sixth distance d6, but the fourth distance d4does not equal the sixth distance d6. In the second embodiment, under the circumstance that the second end224, the fourth end226and the sixth end228are not aligned, the efficiency of the nanowire transistor100is twice the efficiency of the nanowire transistor100with the second end224, the fourth end226and the sixth end228aligned. The numbers of the nanowire and the gate lines of the nanowire transistor100in the embodiments shown inFIG. 6toFIG. 8can be increased based on different requirements. The added nanowire can be disposed along the vertical direction Z, and aligned with the first nanowire20entirely. The added gate line can be disposed at one side of the second gate line26or the third gate line28. The position of the end of the added gate line can be disposed following the rule mentioned in the second preferred embodiment.

For example, as shown in example (b) ofFIG. 11, a fourth gate line32is added to one side of the second gate line26, and a fifth gate line34is added to one side of the third gate line28. Compared to the second gate line26, the fourth gate line32is farther from the first gate line24along the first direction X; therefore, a seventh distance d7between an end132of the fourth gate line32and the first nanowire20is smaller than the third distance d3along the second direction Y. Compared to the third gate line28, the fifth gate line34is farther from the first gate line24along the first direction X; therefore, a ninth distance d9between an end134of the fifth gate line34and the first nanowire20is smaller than the fifth distance d5along the second direction Y.

An interlayer dielectric layer30encapsulates the first end124, the second end224, the third end126and the fourth end226, the fifth end128and the sixth end228. When the interlayer dielectric layer30is tensile stress, the gate structure240is a gate structure of a P-type transistor, and the nanowire transistor100is a P-type transistor; when the interlayer dielectric layer30is compressive stress, the gate structure240is a gate structure of an N-type transistor, and the nanowire transistor100is an N-type transistor.

FIG. 9depicts a three-dimensional view of an inverter structure according to a third preferred embodiment of the present invention.FIG. 10is a top view ofFIG. 9. As shown inFIG. 9andFIG. 10, an inverter structure includes a substrate50. The substrate50is divided into a first-type transistor region54and a second-type transistor region55. A first direction S, a second direction T and a vertical direction W are defined on the substrate52. The first direction S and the second direction T are parallel to a top surface56of the substrate52. The vertical direction Z is perpendicular to the top surface56. The first direction S is perpendicular to the second direction T. The substrate12includes a first fin structure58and a second fin structure60. An STI62surrounds the first structure58and the second fin structure60. The first fin structure58and the second fin structure60may be semiconductor materials such as silicon, germanium, silicon germanium, or silicon carbide. The STI62is preferably silicon oxide or other insulating material. A first nanowire64is suspended on the substrate52and entirely within the first-type transistor region54. The first nanowire64is disposed directly on the fin structure58and entirely overlaps the fin structure58in the vertical direction W. The first nanowire64is parallel to the first direction S. A second nanowire66is suspended on the substrate52and entirely within the second-type transistor region55. The second nanowire66is disposed directly on the second fin structure60and entirely overlaps the second fin structure60in the vertical direction W. The second nanowire66is parallel to the first direction S. According to another preferred embodiment, the inverter structure further includes a third nanowire68suspended on the substrate52and entirely aligns the first nanowire64along the vertical direction W. The material of the first nanowire64, the second nanowire66, the third nanowire68and the fourth nanowire70are the same as that of the first fin structure58and the second fin structure60.

A first gate line72is disposed within the first-type transistor region54and the second-type transistor region55and is perpendicular to the first nanowire64and the second nanowire66. The first gate line72includes a first end172within the first-type transistor region54and a second end272within the second-type transistor region55. A second gate line74is disposed within the first-type transistor region54and the second-type transistor region55and is perpendicular to the first nanowire64and the second nanowire66. The second gate line74includes a third end174within the first-type transistor region64and a fourth end274within the second-type transistor region55. A first distance D1between the first end172and the first nanowire64is larger than a third distance D3between the third end174and the first nanowire64and a second distance D2between the second end272and the second nanowire66is smaller than a fourth distance D4between the fourth end274and the second nanowire66. The first distance D1, the second distance D2, the third distance D3and the fourth distance D4are parallel to the second direction T. The first gate line72overlapping the first nanowire64is defined as a first-type gate structure78. Source/drain doped regions (not shown) are disposed in the first nanowire64at two sides of the first-type gate structure78. The first-type gate structure78, the first nanowire64and the source/drain doped regions forma first-type transistor82. The first gate line72overlapping the second nanowire66is defined as a second-type gate structure80. Source/drain doped regions (not shown) are disposed in the second nanowire66at two sides of the second-type gate structure80. The second-type gate structure80, the second nanowire66and the source/drain doped regions form a second-type transistor84. The first-type transistor82and the second-type transistor form an inverter.

According to a preferred embodiment of the present invention, the inverter structure50can further include a third gate line76disposed in the first-type transistor region54and the second-type transistor region55. The third gate line76is perpendicular to the first nanowire64. The first gate line72is disposed between the third gate line76and the second gate line74. The third gate line76has a fifth end176within the first-type transistor region54and a sixth end276within the second-type transistor region55. The first distance D1is larger than a fifth distance D5between the fifth end176and the first nanowire64. The second distance D2is smaller than a sixth distance D6between the sixth end276and the second nanowire66. The fifth distance D5and the sixth distance D6are parallel to the second direction T. Moreover, the third distance D3may be equal to or different from the fifth distance D5. The fourth distance D4may be equal to or different from the sixth distance D6. InFIG. 10, the third distance D3equals the fifth distance D5, and the fourth distance D4equals the sixth distance D6. Furthermore, the first gate line72has an applied voltage. The second gate line74and the third gate line76may respectively have an applied voltage or be floating. The first gate line74, the second gate line74and the third gate line76respectively include a gate and a gate dielectric layer. The gate may be a conductive material such as doped polysilicon or metal. The gate dielectric layer may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbon nitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or high-k dielectrics having a dielectric constant greater than 5.

The inverter structure50further includes an interlayer dielectric layer86encapsulating the first end172, the second end272, the third end174and the fourth end274. If there is a third gate line76, the interlayer dielectric layer86also encapsulates the fifth end176and the sixth end276. The interlayer dielectric layer86is preferably silicon nitride. When the interlayer dielectric layer86is tensile stress, the first-type transistor region54is a P-type transistor region, and the second-type transistor region55is an N-type transistor region, i.e. the first-type transistor82is P-type and the second-type transistor84is N-type. When the interlayer dielectric layer86is compressive stress, the first-type transistor region54is an N-type transistor region, and the second-type transistor region55is a P-type transistor region, i.e. the first-type transistor82is N-type and the second-type transistor84is P-type.

The gate lines in the present invention are adjusted according to the stress type of the interlayer dielectric layer, and the conductive type of the transistor. Therefore, the efficiency of both the nanowire transistor and the inverter are increased.