Precision pulse generation using a serial transceiver

An example pulse generation circuit includes a parallel-to-serial circuit configured to convert parallel data to serial data according to parallel clock signal and a serial clock signal, the serial data comprises a sequence of pulses; a clock generator configured to generate a clock signal; and a phase controller configured to generate the serial clock signal from the clock signal based on a phase control signal.

TECHNICAL FIELD

Examples of the present disclosure generally relate to electronic circuits and, in particular, to precision pulse generation using a serial transceiver.

BACKGROUND

Precision generation of pulses or data edges is desirable for various electronic equipment, such as precision instrumentation, radar, and the like. Often times, a high-speed clock is required to obtain high-precision pulses. For example, a stream of pulses with an edge position resolution of 40 picoseconds (ps) requires a 25 gigahertz (GHz) clock. A clock generator for generating such a high speed dock may consume significant power or otherwise may be unavailable. In another example, a stream of pulses with an edge position resolution of 10 ps requires a 100 GHz serial clock. A clock generator for generating such a high speed clock may not be readily available. Thus, there is a need for precision pulse generation without use of a high-speed clock.

SUMMARY

Techniques for precision pulse generation using a serial transceiver are described. In an example, a pulse generation circuit includes a parallel-to-serial circuit configured to convert parallel data to serial data according to parallel clock signal and a serial clock signal, the serial data comprises a sequence of pulses; a clock generator configured to generate a clock signal; and a phase controller configured to generate the serial clock signal from the clock signal based on a phase control signal.

In another example, a method of controlling a parallel-to-serial circuit to generate a sequence of pulses includes selecting a pulse repetition interval and a pulse width. The method further includes configuring a control circuit with a parallel data word sequence to be coupled to the parallel-to-serial circuit based on the selected pulse repetition and pulse width. The method further includes configuring the control circuit with a phase update sequence to adjust a phase controller coupled to the parallel-to-serial circuit based on the selected pulse repetition and pulse width. The method further includes coupling the parallel data word sequence and the phase update sequence from the control circuit to the parallel-to-serial circuit to generate the sequence of pulses.

In another example, a circuit includes a pulse generator configured to generate pulses; and a pulse consumer circuit configured to consume the pulses. The pulse generator includes a parallel-to-serial circuit configured to convert parallel data to serial data according to parallel clock signal and a serial clock signal, the serial data comprising the pulses; a clock generator configured to generate a clock signal; and a phase controller configured to generate the serial clock signal from the clock signal based on a phase control signal.

DETAILED DESCRIPTION

Techniques for precision pulse generation using a serial transceiver are described. In an example, a pulse generation circuit is configured to convert parallel data to serial data according to a parallel clock and a serial clock. The serial data includes a sequence of pulses, each having at least one precision edge. The pulse generation circuit includes a phase controller, such as a phase interpolator, configured to generate the serial clock from a reference clock based on a phase control signal. The reference clock can be generated by a clock generator, such as a phase locked loop (PLL) or the like. The parallel data provides for coarse control of the precision edges of the pulses. The phase controller provides for fine control of the precision edges of the pulses. The phase controller allows for use of a much lower speed reference clock to obtain a desired resolution of the precision edges. For example, the phase controller can be configured to adjust phase using 64 steps. In such an example, the reference clock can have a frequency 1/64 that of the frequency required without use of the phase controller. Thus, if a 40 ps resolution is required, the reference clock can have a frequency of only 390.25 MHz (e.g., 25 GHz/64) rather than 25 GHz. Accordingly, the pulse generator described herein obviates the need for very high-speed PLLs, which consume significant power or otherwise may be unavailable. These and other advantages are described below with respect to the drawings.

FIG. 1is a block diagram depicting a system100having a pulse generator102and a pulse consumer circuit104according to an example. The pulse generator102includes an input106configured to receive parallel data and an input108configured to receive fine phase control data. The pulse generator102includes an input112configured to receive a clock signal (“CLK”). The pulse generator102includes an output110coupled to an input of the pulse consumer circuit104. The pulse generator102outputs a stream of pulses (“pulse stream”) for use by the pulse consumer circuit104. For example, the pulse consumer circuit104can include circuits for radar applications, such as precision radio frequency (RF) envelope generation. In another example, the pulse consumer circuit104can include circuits for precision instrumentation applications, such as precision interval generation circuits or precision pulse width generation circuits. Those skilled in the art will appreciate that the pulse generator102described herein may find use in various other applications in addition to the specific example applications described herein.

In operation, the pulse generator102generates a pulse stream based on the parallel data at the input106and the fine phase control data at the input108based on the clock signal CLK at the input112. In an example, the pulse generator102performs X:1 serialization to convert the X-bit parallel data at the input106to serial data at the output110. In the example ofFIG. 1, the pulse generator102X=8 such that the pulse generator102performs 8:1 serialization of 8-bit data words. Although 8:1 serialization is described as an example, it is to be understood that other serialization ratios can be used. Further, in some examples, the pulse generator102can have a configurable serialization ratio.

The parallel data provides coarse control of pulse edge positions in the serial output data within a resolution of one unit interval (UI) of clock signal CLK at the input112. Each pulse in the output110includes a leading edge114and a trailing edge116. In the example shown, the pulses are logic high pulses, but in other examples the pulses can be logic low pulses. In an example, one of the edges114,116is a precision edge and the other of the edges114,116is the non-precision edge. The non-precision edge transitions K UI after the precision edge, where K is an integer greater than zero. That is, each pulse has a configurable pulse width of K UI. In the example shown, the leading edge114is the precision edge. In other examples, the trailing edge116can be the precision edge. In another example, both edges114,116can be precision edges.

Each logic “1” in the parallel data results in a pulse in the serial data. Logic l's can be position in the parallel data words in order to coarsely adjust the interval between the precision edges of the pulses in the serial data within a resolution of one UI. In an example, the parallel data includes at most two logic transitions per data word including between data words. The position of the precision edges of the pulses in the serial output data are further refined based on the fine phase control data on the input108. As described further below, the fine phase control data can move a given precision edge a fraction of a UI of the clock signal CLK at the input112. Operation of the fine phase control can be further understood with reference toFIG. 2.

FIG. 2is a block diagram depicting the pulse generator102according to an example. The pulse generator102includes a parallel-to-serial circuit202, a divider208, and a phase interpolator210. The pulse generator102can be coupled to a phase-locked loop (PLL)212and a control circuit214. The parallel-to-serial circuit202includes a parallel input circuit204and a serial output circuit206. The serial output circuit206generates the serial output data on the output110according to a serial clock (“serial CLK”). The serial clock signal is output by the phase interpolator210. The parallel input circuit204receives the parallel data on the input106. The parallel-to-serial circuit202serializes the parallel data received by the parallel input circuit204to generate the serial output data provided by the serial output circuit206. The parallel input circuit204processes words of the parallel data according to a word clock signal (“word CLK”). The divider208generates the word clock signal by dividing the serial clock signal by the number of bits per word (denoted as N).

The parallel-to-serial circuit202can include an input216for serialization control. In an example, the parallel-to-serial circuit202can employ different serialization rates by adjusting the input216. The serialization rate can be controlled by another circuit or by the control circuit214.

The phase interpolator210receives the clock signal CLK from the PLL212. The PLL212generates the clocks signal CLK from a reference clock signal (“reference CLK”). The PLL212can be any type of clock generator circuit for generating a clock at a particular frequency. The phase interpolator210is configured to adjust the phase of the clock signal CLK to produce the serial clock signal. The phase interpolator210can adjust the phase by discrete amounts per UI of the serial clock signal. For example, the phase interpolator210can select among 64 phase adjustments per UI of the serial clock signal. In other examples, the phase interpolator210can select among more than or less than 64 phase adjustments per UI of the serial clock signal. The step size of the phase interpolator210can be fixed or variable. In an example where the phase interpolator210is capable of 64 phase adjustments per UI of the serial clock signal, the phase interpolator210can adjust the phase by Y/64 during a phase adjustment, where Y (step size) is an integer greater than zero. In some examples, Y is fixed. In other examples, Y is variable ranging from a minimum value to a maximum value.

In the examples described herein, the pulse generator102includes the phase interpolator210for adjusting phase of the clock signal CLK to produce the serial clock signal. It is to be understood that other types of circuits can be used to adjust the phase of the clock signal. In general, the pulse generator102includes a phase controller, such as the phase interpolator210, for adjusting the phase of the clock signal to generate the serial clock signal. Other types of phase controllers include a delay line circuit, a control circuit that provides voltage pulses to a voltage controlled oscillator (VCO) of the PLL212, a phase offset control circuit for the PLL212, or the like. In general, the pulse generator102includes a phase controller that is configured to generate a serial clock signal having a phase selected from a plurality of selectable phases.

The control circuit214generates the parallel data on the input106for coarse phase control and the fine phase control data on the input108for fine phase control.FIG. 5is a flow diagram depicting a method500of controlling a parallel-to-serial circuit for pulse generation according to an example. The method500can be at least partially performed by the control circuit214or by the control circuit214in combination with other control circuitry.

The method500begins at step502, where the serialization ratio is set for the parallel-to-serial circuit202. For example, the parallel-to-serial circuit202can be set to have an 8:1 serialization ratio. At step504, the pulse width of serial output pulses is selected for the parallel-to-serial circuit202. Also, at step504, the pulse repetition rate is selected for the parallel-to-serial circuit202. For example, the pulse width can be K UI, where K is a positive integer. The pulse repetition rate can be some fractional multiple of the UI of the serial clock. At step506, the control circuit214is configured with a parallel data word sequence. The sequence of data words can be configured to coarsely adjust the phase of the pulses in the serial data. At step508, the control circuit214is configured with a fine phase update sequence. The fine phase update sequence includes a sequence of phase updates that are used to finely adjust the phase of the pulses in the serial data. At step510, the control circuit214is configured to initiate the parallel data word and fine phase update sequences to begin the pulse generation.

Operation of the control circuit214and the method500can be understood with reference to the following example. In an example, it is desired to have one UI high true pulses every 16.4657 UI, the parallel data words are 8-bits wide (e.g., 8-to-1 serialization), and the phase interpolator210operates in steps of 1/64 UI. The control circuit214updates the phase adjustment applied by the phase interpolator210before updating the data word containing the pulse edge to be varied. Table 1 below shows values for the data words and fine phase control for the above-described example.

In the example of Table 1, the parallel data word sequence is 0x80, 0x00, 0x80, 0x00, 0x40, 0x00, 0x40, 0x00, 0x20, 0x00, 0x20. While only 11 data words are shown, those skilled in the art will appreciate that the sequence can continue for more than 11 data words. This parallel data word sequence coarsely adjusts the interval between the leading pulse edges.FIG. 3shows a signal set300illustrating the coarse adjustment of pulses using the parallel data word sequence according to an example. The signal set300includes a serial clock302, a parallel word clock304, and a pulse stream306. The serial clock302illustrates an example of the serial clock input to the parallel-to-serial circuit202. The parallel word clock304illustrates an example of the word clock input to the parallel-to-serial circuit202. The pulse stream306illustrates the pulses in the serial data on the output110of the parallel-to-serial circuit202. The signals are shown over a time span of 40 UI of the serial clock302.

As shown in the example ofFIG. 3, the serialization ratio is 8:1. Thus, the parallel word clock304is the serial clock302divided by 8. Each leading edge of the parallel word clock304clocks in a data word of the data word sequence (e.g., 0x80, 0x00, 0x40, 0x00, 0x20, etc.). A pulse in the pulse stream306is generated for each logic ‘1’ in the data word sequence. In the present example, a pulse width308of the pulses in the pulse stream306is 1 UI of the serial clock302. The data word sequence in the parallel data provides coarse control of an interval310between leading edges of the pulses in the pulse stream306.

In the example of Table 1, the fine phase control sequence is no update, 30, no update, 60, no update, 25, no update, 55, no update, 21, no update. Each “no update” corresponds to the previous value of the fine phase control. While only 11 fine phase updates are shown, those skilled in the art will appreciate that the sequence can continue for more than 11 fine phase updates. This fine phase update sequence finely adjusts the interval between the leading pulse edges.FIG. 4shows a signal set400illustrating the fine adjustment of pulses using the parallel data word sequence according to an example. The signal set400includes the serial clock302, the parallel word clock304, and the pulse stream306, as well as a phase update clock402. The signals are shown over a time span of 40 UI of the serial clock302. In the present example, the pulse width308of the pulses in the pulse stream306is still 1 UI of the serial clock302. However, the combination of coarse and fine control of the leading edges of the pulses in the pulse stream306results in an interval310′ As shown in the example ofFIG. 4, the phase update clock is the parallel word clock304divided by 2. That is, the fine phase updates occur every other cycle of the parallel word clock304. The dashed boxes inFIG. 4illustrate the timing of the fine phase control updates. The signals302,304,402, the TXDATA, and the PHASE are all shifted by a fine phase (less than +/−0.5 UI) at a time shortly after any PHASE delta that occurs at the edges of the signal402, which occurs in the example ofFIG. 4at times 16 and 32. A change in the phase of the serial clock302adjusts the leading edge of the next pulse in the pulse stream306. In other examples, the fine phase updates can occur every cycle of the parallel word clock304. In general, the fine phase control signal causes the phase interpolator210to adjust the phase of the clock signal to generate the serial clock signal when the parallel data is not toggling during a threshold time interval.

Table 2 shows the error in UI of the serial clock for pulse generation without fine phase control versus pulse generation with fine phase control in the example illustrated by Table 1.

Without fine phase control, the edge resolution of the output pulses is 1 UI of the serial clock with a maximum edge position error of +/−0.5 UI of the serial clock. With fine phase control, the edge resolution of the output pulses is 1/64 UI of the serial clock with a maximum edge position error of +/− 1/128 UI of the serial clock (assuming the phase interpolator210has 64 discrete phase adjustments). Table 3 shows the edge resolution for various example serial data rates both with and without fine phase control.

In table 3, the units Gbps correspond to Gigabits per second, the units ps correspond to picoseconds, and the units fs correspond to femtoseconds. The pulse edge resolution is improved by 64 times when using fine phase control as compared to without fine phase control.

Various parameters described in the examples above can be modified to produce a stream of pulses having the desired characteristics. These parameters include serialization rates other than 8:1, precision edges that are trailing edges rather than leading edges, and pulse widths other than 1 UI of the serial clock. In general, a pulse stream includes a desired pulse repetition interval (PRI) and pulse width (PW) in terms of the UI of the serial clock. The serialization ratio, parallel data words, and fine phase control values can be chosen to implement a pulse stream having the desired PRI and PW.

In the examples described above, one of the pulse edges is a precision edge while the other pulse edge is a non-precision edge occurring K UI after the precision edge. In another example, the positioning of the pulse edges can be generalized to fine placement of consecutive pulse edges of opposite polarities. In such an example, the interval between edges of opposite polarities must be greater than minimums of the update interval of the phase interpolator times the quantity of the phase interpolator steps per UI divided by the maximum phase interpolator step size.

The pulse generator102described herein can be used in serial receivers or transceivers disposed in an IC, such as a field programmable gate array (FPGA) or other type of programmable IC. Although an FPGA is shown by way of example, it is to be understood that the pulse generator102can be implemented in other types of ICs or applications.FIG. 6illustrates an architecture of an FPGA600that includes a large number of different programmable tiles including multi-gigabit transceivers (“MGTs”)1, configurable logic blocks (“CLBs”)2, random access memory blocks (“BRAMs”)3, input/output blocks (“IOBs”)4, configuration and clocking logic (“CONFIG/CLOCKS”)5, digital signal processing blocks (“DSPs”)6, specialized input/output blocks (“I/O”)7(e.g., configuration ports and clock ports), and other programmable logic8such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (“PROC”)10.

In some FPGAs, each programmable tile can include at least one programmable interconnect element (“INT”)11having connections to input and output terminals20of a programmable logic element within the same tile, as shown by examples included at the top ofFIG. 11. Each programmable interconnect element11can also include connections to interconnect segments22of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element11can also include connections to interconnect segments24of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments24) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments24) can span one or more logic blocks. The programmable interconnect elements11taken together with the general routing resources implement a programmable interconnect structure (“programmable interconnect”) for the illustrated FPGA.

In an example implementation, a CLB2can include a configurable logic element (“CLE”)12that can be programmed to implement user logic plus a single programmable interconnect element (“INT”)11. A BRAM3can include a BRAM logic element (“BRL”)13in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile6can include a DSP logic element (“DSPL”)14in addition to an appropriate number of programmable interconnect elements. An IOB4can include, for example, two instances of an input/output logic element (“IOL”)15in addition to one instance of the programmable interconnect element11. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element15typically are not confined to the area of the input/output logic element15.

Some FPGAs utilizing the architecture illustrated inFIG. 6include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, processor block10spans several columns of CLBs and BRAMs. The processor block10can various components ranging from a single microprocessor to a complete programmable processing system of microprocessor(s), memory controllers, peripherals, and the like.