Methods of testing semiconductor memory devices in a variable CAS latency environment and related semiconductor test devices

Methods of testing a semiconductor device are provided in which a test pattern is generated for the semiconductor device that is based on the semiconductor device operating under a first CAS latency number. Then, the semiconductor device is tested using this test pattern where, at least part of the test is performed when the semiconductor device is operating under a second CAS latency number that is different from the first CAS latency number. This may be accomplished, for example, by increasing the number of clock cycles in the timing clock signal during a CAS latency-variable interval in situations where the CAS latency is changed after generation of the test pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 2003-95135, filed on Dec. 23, 2003, the disclosure of which is incorporated herein by reference as if set forth in its entirety.

FIELD OF THE INVENTION

This invention relates to semiconductor test devices and, more particularly, to methods of testing semiconductor devices using adjustable timing clock signals and related semiconductor test devices.

BACKGROUND OF THE INVENTION

Semiconductor device manufacturers often perform systematic tests to determine whether or not the semiconductor devices that they manufacture satisfy certain design parameters. The tests performed may include, for example, device parameter tests (DC testing), device logic function tests and/or device timing tests (AC testing). The semiconductor device being tested is sometimes called the Device Under Test or “DUT.” The test system used to perform the tests on the DUT is often referred to as Automatic Test Equipment or “ATE.”

Typically, the ATE is controlled by a computer that may provide voltage, current, timing, functional status and/or other information to and from the DUT. The computer may also execute a test program that monitors the response of the DUT to the respective tests. The results of the tests may, for example, be compared with predetermined thresholds to make decisions as to whether or not the DUT passed or failed a test at issue. The ATE may include, for example, a power supply, a counter, a signal generator, and a pattern generator. A Pin Electronics or “PE” circuit may be used as an interface between the ATE and the DUT to provide input signals to the DUT and receive output signals from the DUT. For example, during a device parameter test, the PE circuit might apply an input voltage to the DUT and receive an output current from the DUT, or might apply an input current to the DUT and receive an output voltage from the DUT.

A semiconductor test device is disclosed in International Patent Publication No. WO 2003/052767. This test device may be used to test a plurality of semiconductor devices simultaneously. The test device may input the same test data pattern waveform to the same pin of a plurality of semiconductor devices to perform the testing.

FIG. 1is a schematic of a conventional semiconductor test device that may be used to test a semiconductor memory device. The memory device may comprise, for example, a dynamic random access memory device (“DRAM”). As shown inFIG. 1, the device may include a clock signal generator10for generating a timing clock signal CLK. The device further includes a pattern generator12, such as an algorithmic pattern generator, that transmits a clock signal generation start signal T1to the clock signal generator10, receives the clock signal CLK from the clock signal generator10and generates an address pattern, a data pattern, and/or a control pattern. The device further includes a pattern data selector14that allocates channels to the address pattern, the data pattern and/or the control pattern that are received from the pattern generator12. A signal generator16such as a timing generator format controller may be provided that generates the actual test data in synchronization with the timing clock signal CLK based on the pattern data output from the pattern data selector14. A buffer driver18is provided that generates a buffer driving signal, and a plurality of buffers20are used to buffer the test data generated by the signal generator16. A plurality of switches22are provided that switch the data output from the plurality of buffers22to the DUT30.

FIGS. 2 and 3are exemplary diagrams of a conventional test pattern. In particular,FIG. 2shows an Xmarch CL4 pattern, andFIG. 3shows an Xmarch CL5 pattern. InFIGS. 2 and 3, AWRA refers to an “active read command”, and LAL is a “second command.”FIG. 4is a timing diagram illustrating the generation of timing clock signals according to the conventional Xmarch CL4 pattern ofFIG. 2.

Aspects of the present invention relate to semiconductor memory devices that use Column Address Strobe or “CAS” techniques. As will be understood by persons of skill in the art, CAS latency involves the period of time (or number of clock cycles) that must pass before the data that is output in a read operation appears on the output pins. As used herein, the term “CAS latency number” refers to the number of clock cycles of a clock signal that is synchronized with an external command that must pass after application of a read or write command before the input/output data can be presumed valid.

Operations for outputting test pattern data using the conventional test device ofFIG. 1will now be described with referenceFIGS. 1-4. Operations may begin with the clock signal generator10receiving a clock signal generation start signal T1from the pattern generator12. The clock signal generator10generates a timing clock signal CLK in response to the start signal T1. The pattern generator12receives the clock signal CLK from the clock signal generator10and generates a test pattern that comprises an address pattern, a data pattern and a control pattern. These patterns are output to the pattern data selector14. The test pattern may be designed, for example, to generate commands to read or write data to/from the DUT after four or five cycles of a clock signal. In particular, the test pattern may be generated according to the CAS latency number. The pattern data selector14allocates channels to the address pattern, the data pattern and the control pattern and outputs the channel-allocated patterns to the signal generator16. The signal generator16generates actual test data based on the pattern data allocated by the pattern data selector14in synchronization with the timing clock signal CLK, and outputs the generated data to the respective buffers20. The buffer driver18generates a buffer driving signal and applies it to the respective buffers20. The plurality of buffers20buffer the actual test data according to the buffer driving signal output from the buffer driver18and apply the buffered data to the respective switches22. The plurality of switches22switch on to output the data in the buffers20to the DUT30.

Thus, the pattern generator12of the above-described conventional semiconductor test device generates a test pattern that has a CAS latency number that, for example, corresponds to the test pattern ofFIG. 2or3, and the signal generator16generates actual test data based on the test pattern and transmits the generated test data to the DUT30.

When the test pattern is formed with a four-cycle clock signal4CLK as shown, for example, inFIG. 2, the conventional semiconductor test device generates an active read command for reading data after the generation of four cycles of the clock signal CLK (seeFIG. 4). However, if the CAS latency number of the semiconductor device is changed, for example, from four to five, a whole new set of test patterns is required. Accordingly, an increase or decrease of one in the CAS latency number requires a doubling in the number of test patterns required. Larger increases (or decreases) in the CAS latency number require a corresponding increase in the number of test patterns to twice the change in the CAS latency number. As the number of test patterns increases, the likelihood human errors in programming and/or verification of the test patterns increases.

SUMMARY OF THE INVENTION

Pursuant to embodiments of the present invention, methods of testing a semiconductor device are provided in which a test pattern is generated for the semiconductor device that is based on the semiconductor device operating under a first CAS latency number. Then, the semiconductor device is tested using this test pattern where, at least part of the test is performed when the semiconductor device is operating under a second CAS latency number that is different from the first CAS latency number. The second CAS latency number may be greater than the first CAS latency number.

The method may further include increasing the number of clock pulses in a clock signal that is provided to the semiconductor device during the part of the test when the semiconductor device is operating under the second CAS latency number. This may be done, for example, by selectively providing a first clock signal or a second clock signal to the semiconductor device, where the first clock signal comprises a clock signal that is used to control the operation of a test device and the second clock signal comprises a latency increasing time signal. The second clock signal may be selectively provided to the semiconductor device for periods of at least two clock cycles of the first clock signal. Moreover, the second clock signal may be generated in embodiments of the present invention by performing a logical-OR operation on the first clock signal and a CAS-latency increasing signal. A multiplexer may be used to selectively provide the first clock signal and the second clock signal to the semiconductor device.

Pursuant to further embodiments of the present invention, methods of testing a semiconductor memory device are provided in which a test pattern is generated that is associated with a first CAS latency number. A change in the CAS latency number may then be received. A clock signal that is provided to the semiconductor device may be modified in response to the change in the CAS latency number. The semiconductor device may then be tested using the test pattern and the modified clock signal.

The clock signal that is provided to the semiconductor device in response to the change in the CAS latency number may be modified by inserting at least one additional clock pulse into the clock signal pattern during each of a plurality of read or write operations. This may be done, for example, by selectively providing a first clock signal or a second clock signal to the semiconductor device, where the second clock signal is used to selectively replace a pulse of the first clock signal with at least two pulses. The second clock signal may be a latency increasing clock signal that is generated by a signal generator.

Pursuant to still further embodiments of the present invention, semiconductor test devices are provided which include an automatic test device that is configured to output a clock signal and a plurality of data signals and a clock pulse insertion circuit that is configured to selectively insert clock pulses into the clock signal output by the automatic test device. The clock pulse insertion circuit may be configured to selectively insert clock pulses into the clock signal in response to an increase in a CAS latency number. The clock pulse insertion circuit may include a multiplexer that is configured to selectively outputs the clock signal from the automatic test device and a second clock signal. The clock pulse insertion circuit may also include an OR gate that is configured to receive both the clock signal from the automatic test device and a latency changing timing signal. In such embodiments, the inputs to the multiplexer may comprise the clock signal from the automatic test device and the output of the OR gate.

Pursuant to further embodiments of the present invention, semiconductor test devices are provided which include a clock signal generator, a pattern generator, a pattern data selector, a signal generator, a buffer driver, a buffer section and a clock signal inserter. The clock signal inserted may be configured to receive a timing clock signal CLK and a latency-increasing timing signal output from the buffer section to generate a latency-increased timing clock signal CLK1. In certain embodiments, the clock signal inserter may comprise a logic gate that performs a logical OR operation on the timing clock signal CLK and the CAS latency-increasing signal to generate the clock signal inserted to increase the CAS latency and a multiplexer for that outputs the timing clock signal CLK and the clock signal inserted to increase the CAS latency during a CAS latency-increasing interval of the timing clock signal CLK according to a timing control signal Tx.

DETAILED DESCRIPTION

FIG. 5is a block diagram of a semiconductor test device100according to certain embodiments of the present invention.

As shown inFIG. 5, the semiconductor test device100includes a clock signal generator102that generates a timing clock signal CLK in response to a timing control signal Tx. The timing control signal Tx is generated by a pattern generator104. The pattern generator further receives the clock signal CLK from the clock signal generator102, and generates an address pattern, a data pattern, a control pattern and an insertion clock signal generation control signal in response thereto. A pattern data selector106is responsive to the pattern generator104. The pattern data selector106allocates channels to the address pattern, the data pattern, the control pattern and the insertion clock signal generation control signal. A signal generator108is further provided that may be used to generate both the actual test data and a latency-increasing timing signal based on the pattern data allocated from the pattern data selector106in synchronization with the timing clock signal CLK. A buffer driver110is provided that generates a buffer driving signal that controls a plurality of buffers112that buffer the actual test data and the latency-increasing timing signal. A clock signal inserter114receives the timing clock signal CLK and the latency-increasing timing signal output from one of the buffers112and outputs a timing clock signal CLK1under the control of the pattern generator104. A switching section116is provided, and a DUT200is connected to the semiconductor test device100via the switching section116. In the illustrated embodiment, the buffer section112includes buffers B1through B8, and the switching section116includes switches SW1through SW8.

FIGS. 6 to 8are diagrams of exemplary test patterns according to certain embodiments of the present invention. In particular,FIG. 6depicts a portion of an Xmarch 1Bank CL4 pattern,FIG. 7depicts a portion of an Xmarch CL5 pattern, andFIG. 8depicts a portion of an Xmarch CL6 pattern. As will be appreciated by those of skill in the art, inFIGS. 6-8, Xmarch refers to a test pattern that operates in the row (word line) direction, and Ymarch (not shown) refers to a test pattern that operates in the column (bit line) direction. AWRA refers to an “Active Read Command”, and LAL is a “Second Command.”FIG. 9is a timing diagram of the operation of the clock signal inserter114according to certain embodiments of the present invention.

FIG. 10is a diagram illustrating generation of timing clock signals for the Xmarch CL5 pattern according to certain embodiments of the present invention.FIG. 11is a diagram illustrating generation of timing clock signals for the Xmarch CL6 pattern according to certain embodiments of the present invention.

Operations for outputting test pattern data according to certain embodiments of the present invention will now be described with reference toFIGS. 5-11. Operations may start with the clock signal generator102generating a timing clock signal CLK in response to a defined timing control signal Tx from the pattern generator104. The pattern generator104receives the timing clock signal CLK and generates an address pattern, a data pattern, a control pattern and an insertion clock signal generation control signal, each of which may be provided to the pattern data selector106. The test pattern generated by the pattern generator104is based on a CAS latency number. For example, if the CAS latency number is four, the test pattern may be designed such that data is read from or written to the DUT after four cycles of the clock signal. With conventional semiconductor test devices, if the test pattern needs to be changed (due, for example, to a change in the CAS latency number) such that data is read from or written to the DUT after, for example, generation of five or six cycles of the clock signal CLK, additional test patterns are formed by a program and generated from the pattern generator104.

According to embodiments of the present invention, the pattern generator104may be used to generate, for example, a test pattern for reading/writing data after generation of four cycles of the clock signal CLK (i.e., a CAS latency number of four). If, thereafter, the CAS latency number is changed to five or six, the pattern generator104may (1) apply a timing control signal (e.g., signal Tx) to a selection terminal S of a multiplexer (“MUX”)120and (2) receive the timing clock signal CLK from the clock signal generator102to generate a CAS latency-increasing timing control signal and an insertion clock signal generation control signal, each of which are provided to the pattern data selector106. The pattern data selector106may then allocate two of the channels, such as, for example, first and second channels CH1and CH2, to the insertion clock signal generation control signal generated from the pattern generator104, and allocate the remaining channels (e.g., third through ninth channels CH3to CH9) to output an address pattern, a data pattern, and a control pattern to the signal generator108. The signal generator108generates actual test data, a timing clock signal CLK and a CAS latency-increasing signal based on the pattern data and the insertion clock signal generation control signal generated from the pattern data selector106in synchronization with the timing clock signal CLK, and outputs them to first and second buffers B1and B2of the plurality of buffers112. The buffer driver110generates a buffer driving signal and applies the generated buffer driving signal to the plurality of buffers112. The plurality of buffers112buffer the actual test data, the timing clock signal CLK and the CAS latency-increasing signal generated from the signal generator108according to the buffer driving signal output from the buffer driver110. The timing clock signal CLK and the CAS latency-increasing signal buffered in the first and second buffers B1and B2, respectively, are then applied to an OR gate118. The OR gate118performs a logical OR operation on the timing clock signal CLK and the CAS latency-increasing signal and outputs clock signals which are inserted to increase the CAS latency.

By way of example, the pattern generator104may be used to generate the test pattern ofFIG. 6for reading/writing data after generation of four cycles of the clock signal CLK. When the test pattern ofFIG. 6is changed to a test pattern ofFIG. 7for reading/writing data after generation of five timing clock signals CLK, the signal generator108outputs a timing clock signal CLK to the first buffer B1and a CAS latency-increasing signal to the second buffer B2. The timing clock signal CLK is illustrated as waveform “A” ofFIG. 9, and the CAS latency-increasing signal is illustrated as waveform “B” ofFIG. 9. As shown inFIG. 5, the timing clock signal CLK output from the first buffer B1is input to a first input of the MUX120. Additionally, the OR gate118performs a logical OR operation on the timing clock signal CLK output from the first buffer B1and the CAS latency-increasing signal output from the second buffer B2to produce a CAS latency-increasing clock signal to the other input of the MUX120. This CAS latency-increasing clock signal is illustrated as waveform “C” inFIG. 9The MUX120selectively outputs a portion of the timing clock signal CLK from the first buffer B1(i.e., waveform “A” ofFIG. 9) and the CAS latency-increasing clock signal (i.e., waveform “C” ofFIG. 9). In particular, the MUX120outputs the first three cycles of the timing clock signal CLK and then the CAS latency-increasing clock signal is output according to the timing of the control signal Tx output from the pattern generator104. Namely, the MUX120outputs the first three cycles of the waveform designated “A” inFIG. 9then outputs the CAS latency-increasing clock signal that is designated as waveform “C” inFIG. 9(which is the same as two cycles of the timing clock signal CLK) during the fourth cycle of the timing clock signal CLK. Thereafter, the MUX120selectively outputs the timing clock signal CLK. The first cycle of the timing clock signal CLK is an active read command AWRA, and the second cycle is a second command LAL. The timing clock signal CLK1selected by the MUX120is transmitted to the DUT200via the plurality of the switches116. This operation is iteratively performed to insert the CAS latency-increasing clock signal ofFIG. 10every second-cycle interval after generation of the timing clock signal synchronized with the AWRA and read data, thereby testing the semiconductor device.

As another example, again assume that the pattern generator104generates the test pattern ofFIG. 6for reading/writing data after generation of four cycles of the timing clock signal CLK. When the test pattern thereafter is changed to, for example, the test pattern ofFIG. 8for reading/writing data after generation of six cycles of the timing clock signal CLK, the signal generator108outputs the timing clock signal CLK (waveform “A” inFIG. 9) to the first buffer B1and the CAS latency-increasing signal (waveform “B” inFIG. 9) to the second buffer B2. The timing clock signal CLK output from the first buffer B1is input to a first input of the MUX120. Additionally, the OR gate118performs a logical OR operation on the third cycle of the timing clock signal CLK output from the first buffer B1and the CAS latency-increasing signal output from the second buffer B2, and outputs a clock signal that is inserted to increase the CAS latency (see signal “C” inFIG. 9) to the other input the MUX120. The MUX120selectively outputs the timing clock signal CLK output from the first buffer B1and, after generation of the second clock signal LAL, the CAS latency-increasing clock signal that is fed into the other input of the MUX120according to the timing control signal Tx output from the pattern generator104. Namely, the MUX120outputs the timing clock signal CLK (waveform “A” ofFIG. 9) up to the second cycle and then selects the CAS latency-increasing clock signal (waveform “C” ofFIG. 9) in the third cycle of the timing clock signal CLK. Thereafter, the MUX120selects the clock signal inserted to increase the latency (waveform “C” ofFIG. 9) output from the OR gate118again in the fourth cycle of the timing clock signal CLK. The timing clock signal CLK1generated by the MUX120is transmitted to the DUT200via the first switch SW1of the switching section116. This operation is iteratively performed to insert the CAS latency-increasing clock signal ofFIG. 11every second- and third-cycle interval after generation of the timing clock signal synchronized with the AWRA and read data, thereby testing the semiconductor device.

As described above, embodiments of the present invention may reduce the burden for programming and verification by generating more timing clock signals in a CAS latency-increasing interval without the need to develop a separate program for a test pattern when the latency of the test pattern for testing a semiconductor device changes.