NAND-type non-volatile memory devices having a stacked structure

A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C § 119 to Korean Patent Application 2005-121779 filed on Dec. 12, 2005, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention relates to semiconductor devices, methods of forming the same, and methods of operating the same. More particularly, the present invention relates to NAND-type nonvolatile memory devices having a stacked structure, methods of forming the same, and methods of operating the same.

A NAND-type nonvolatile memory device connects predetermined numbers of cells to NAND-type logic to increase an integration density of an array. Because a contact number in a cell array. in a NAND-type memory device is considerably less than that of a comparable NOR-type device, a size of a chip may be relatively small. Accordingly, the demand for NAND-type nonvolatile memory devices generally increases in accordance with high-integration and large-capacitance trends of semiconductor memory devices.

A conventional NAND-type nonvolatile memory device includes cell arrays in a first layer on the semiconductor substrate. However, in accordance with high-integration and large-capacitance trends of semiconductor memory devices, a size of cell arrays realized on a flat surface of the first layer is becoming smaller and the number of cell arrays is simultaneously increasing. Accordingly, as high-integration and large-capacitance progress according to the limits of photolithography processing, it may be difficult to realize cell arrays in the first layer of a NAND-type nonvolatile memory device.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention are directed to a NAND-type nonvolatile memory device having a stacked structure along with methods of forming the same and operating the same. In some embodiments of the present invention, a NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.

In other embodiments, a NAND-type nonvolatile memory device is formed by providing a semiconductor substrate, forming a first ground selection line and a first string selection line on the substrate in parallel to each other, forming a plurality of parallel first word lines on the substrate between the first ground selection line and the first string selection line, forming a first impurity-doped region formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line, forming a first interlayer dielectric layer on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate, patterning the first interlayer dielectric layer to form a hole that exposes the semiconductor substrate, forming an epitaxial contact plug that contacts the semiconductor substrate in the hole, forming a single crystalline semiconductor layer on the first interlayer dielectric layer that contacts the epitaxial contact plug, forming a plurality of parallel second word lines on the single crystalline semiconductor layer, forming a second impurity-doped region in the single crystalline semiconductor layer adjacent to the second word lines, and forming a second interlayer dielectric layer on the plurality of second word lines and the single crystalline semiconductor layer.

In further embodiments, a NAND-type nonvolatile memory device includes a cell string that includes a plurality of cell transistors. The plurality of cell transistors includes a plurality of parallel sub-strings. A first one of the sub-strings includes a first plurality of cell transistors connected to first word lines and a second one of the sub-strings includes a second plurality of cell transistors connected to second word lines. A ground selection transistor is connected to a ground selection line on one side of the plurality of sub-strings and a string selection transistor is connected to a string selection line on another side of the plurality of sub-strings. A cell in such a device may be read by applying a read voltage to one of the first word lines associated with the cell of the first one of the sub-strings, applying a pass voltage to the other ones of the first word lines connected to the first one of the sub-strings, and applying a voltage of less than zero volts to the word lines connected to the second one of the sub-strings.

DETAILED DESCRIPTION

It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected or coupled” to another element, there are no intervening elements present. Furthermore, “connected” or “coupled” as used herein may include wirelessly connected or coupled. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first layer could be termed a second layer, and, similarly, a second layer could be termed a first layer without departing from the teachings of the disclosure.

In the description, a term “substrate” used herein may include a structure based on a semiconductor, having a semiconductor surface exposed. It should be understood that such a structure may contain silicon, silicon on insulator, silicon on sapphire, doped or undoped silicon, epitaxial layer supported by a semiconductor substrate, or another structure of a semiconductor. And, the semiconductor may be silicon-germanium, germanium, or germanium arsenide, not limited to silicon. In addition, the substrate described hereinafter may be one in which regions, conductive layers, insulation layers, their patterns, and/or junctions are formed.

FIG. 1is a plane view illustrating a NAND-type nonvolatile memory device having a stacked structure according to some embodiments of the present invention.FIG. 2is a cross-sectional view. taken along line I-I′ ofFIG. 1.

Referring toFIG. 1andFIG. 2, a plurality of parallel first device isolation layers Fox1are formed to define an active region in a semiconductor substrate1and a ground selection line GSL and a string selection line SSL cross the first device isolation layer Fox1in parallel. A plurality of parallel first word lines WL1are arranged between the ground selection line GSL and the string selection line SSL. A first impurity-doped region11is located in the semiconductor substrate1on both sides of the lines GSL, SSL, WL1. The first word lines WL1are connected to a plurality of first cell transistors including a first tunnel insulation layer3b, a first charge storage layer5, a first blocking insulation layer7, and a first gate electrode9that are stacked sequentially. The string selection line SSL and the ground selection line GSL are connected to string selection transistors and ground selection transistors, respectively, including a gate dielectric layer3aand a first gate electrode9that are stacked sequentially. The string selection line SSL and the ground selection line GSL do not include the first charge storage layer5.

A first etch stopping layer13, a first lower interlayer dielectric layer15, and a first upper interlayer dielectric layer19are formed to cover the lines GSL, SSL, WL1sequentially. A common source line17is located between the ground selection line GSL and a neighboring ground selection line GSL and penetrates the first lower interlayer dielectric layer15and the first etch stopping layer13to contact the first impurity-doped region11. Between the ground selection line GSL and a neighboring first word line WL1, and between the string selection line SSL and a neighboring first word line WL1, an epitaxial contact plug23is located in a hole21penetrating the first upper interlayer dielectric layer19, the first lower interlayer dielectric layer15, and the first etch stopping layer13to electrically connect to the first impurity-doped region11.

Referring toFIG. 1andFIG. 2, a single crystalline semiconductor layer25contacting the epitaxial contact plug23is located on the first upper interlayer dielectric layer19. A second device isolation layer Fox2,27is arranged in the single crystalline semiconductor layer25to define an active region. A plurality of second word lines WL2are arranged in parallel on the single crystalline semiconductor layer25to cross the second device isolation layer Fox2,27. The second word lines WL2are connected to second cell transistors including a second tunnel insulation layer29, a second charge storage layer31, a second blocking insulation layer33, and a second gate electrode35that are stacked sequentially.

The second word lines WL2overlap the first word lines WL1. A second impurity-doped region37is located in the single crystalline semiconductor layer25on both sides of the second word lines WL2. An impurity-doped contact region39may exist in the single crystalline semiconductor layer25between the epitaxial contact plug23and the second impurity-doped region37to electrically connect the epitaxial contact plug23and the second impurity-doped region37. Without the impurity-doped contact region39, the second impurity-doped region37may directly contact the epitaxial contact plug23. A second etch stopping layer41and a second interlayer dielectric layer,43are formed sequentially to cover the second word lines WL2. A bit line contact plug47is located in a bit line contact hole45that penetrates the second interlayer dielectric layer43, the second etch stopping layer41, the second device isolation layer27, the first upper interlayer dielectric layer19, the first lower interlayer dielectric layer15, and the first etch stopping layer13to expose the semiconductor substrate1between the string selection line SSL and a neighboring string selection line SSL. A plurality of parallel bit lines49electrically connected to the bit line contact plug47are arranged on the second interlayer dielectric layer43.

Referring toFIG. 1andFIG. 2, the epitaxial contact plug23electrically connects the first impurity-doped region1located between the first word line WL1and the first ground selection line GSL1and between the first word line WL1and the first string selection line SSL1to the second impurity-doped region37located at both edges of a plurality of the second word lines WL2. First cell transistors connected to the first word lines WL1and located at the same active region comprise a first sub-string and second cell transistors connected to the second word lines WL2and located at the same active region comprise a second sub-string. A one cell string includes a ground selection transistor connected to the ground selection line GSL, a string selection transistor connected to the string selection line SSL, and the first and second sub-strings located therebetween. That is, the one cell string includes parallel structured sub-strings. The cell string is symmetrically arranged in iterative fashion.

Although not illustrated, a well may be formed in the semiconductor substrate1and the single crystalline semiconductor layer25. According to the thickness of the single crystalline semiconductor layer25and depth of the second impurity-doped region37, predetermined numbers of cell arrays are electrically interconnected in the single crystalline semiconductor layer25and it is possible to use the single crystalline semiconductor layer25as a partially or completely depleted silicon on insulator SOI substrate form.

Referring to the NAND-type nonvolatile memory device ofFIG. 1andFIG. 2, the word lines WL1, WL2have a plurality of layers so that a cell size may be reduced regardless of a limit associated with a photolithography process. Also, a control circuit, such as the string selection line SSL and the ground selection line GSL, may be formed on the semiconductor substrate1of approximately perfect semiconductor crystallizations to stably operate the device. Because the NAND-type nonvolatile memory device is not a floating gate but a charge trapping gate including a charge storage layer, operation errors due parasitic couplings of floating gates may be reduced or prevented, a vertical height may be reduced, and operation errors due to defects of an oxide layer may be reduced.

In the above-described embodiments, the word lines WL1, WL2are arranged on double layers; however word lines can be arranged on more than three single crystalline semiconductor layers as stated above.

Referring toFIG. 3, methods of operating the NAND-type nonvolatile memory device ofFIGS. 1 and 2, according to some embodiments of the present invention, will now be described.FIG. 3is an equivalent circuit diagram illustrating the NAND-type nonvolatile memory device ofFIG. 1according to some embodiments of the present invention.

Referring toFIG. 3, n first word lines WL1(1), WL1(2), . . . , WL1(N-1), WL1(N) are arranged between the string selection line SSL and the ground selection line GSL and second word lines WL2(1), WL2(2), . . . , WL2(N-1), WL2(N) are arranged in the other region. The first word lines WL1(1), WL1(2), . . . , WL1(N-1), WL1(N) are connected to a plurality of first cell transistors, respectively, and the second word lines WL2(1), WL2(2), . . . , WL2(N-1), WL2(N) are connected to a plurality of second cell transistors, respectively. The first cell transistors comprise the first sub-strings and the second cell transistors comprise the second sub-strings. The first sub-strings and the second sub-strings are connected in parallel. A drain region (not illustrated) adjacent to the string selection line SSL is connected to bit lines BL1, BL2. A source region (not illustrated) adjacent to the ground selection line GSL is connected to the common source line CSL.

When a cell transistor A is programmed in the equivalent circuit diagram ofFIG. 3, Vcc (a reference voltage) is applied to a string selection line SSL, zero volts 0V are applied to a selected bit line BL1, Vcc is applied to an unselected bit line BL2, zero volts 0V are applied to a ground selection line GSL and about 0 to 0.2 volts are applied to a common source line CSL. A program voltage, for example about twenty volts 20V, is applied to a selected cell word line WL1(2) and a pass voltage, for example about ten volts 10V, is applied to unselected cell word lines WL1(1), . . . , WL1(N-1), WL1(N), WL2(1), WL2(2), . . . , WL2(N-1), WL2(N). As a result, a channel voltage of the cell transistor A becomes about zero volts 0V and the cell transistor is programmed by a Fowler-Nordheim FN tunneling because of a large voltage difference between the gate electrode and the channel. However, unselected cell transistors are not programmed because of no tunneling.

In the equivalent circuit diagram ofFIG. 3, when a cell transistor B located at an upper layer is programmed, Vcc (a reference voltage) is applied to a string selection line SSL, zero volts 0V are applied to a selected bit line BL1, Vcc is applied to an unselected bit line BL2, zero volts 0V is applied to a ground selection line GSL, and about 0 to 0.2 volts are applied to the common source line CSL. A program voltage, for example about twenty volts 20V, is applied to a selection cell word line WL2(2) and a pass voltage, for example about ten volts 10V, is applied to unselected cell word lines WL1(1), WL1(2), . . . , WL1(N-1), WL1(N), WL2(1), . . . , WL2(N-1), WL2(N).

When a cell transistor A is read in the equivalent circuit diagram ofFIG. 3, a read voltage, for example about zero volts 0V, is applied to a selected cell word line WL1(2) and a pass voltage, for example about 4.5 volts, is applied to other word lines WL1(1), . . . , WL1(N-1), WL1(N), connected to the sub-string including a selected cell. A ground voltage or a minus voltage is applied to word lines WL2(1), WL2(2), . . . , WL2(N-1), WL2(N) connected to a sub-string not including the selected cell to turn off. A bit line voltage is applied to a selected bit line BL1, a ground voltage is applied to an unselected bit line BL2, a reference voltage is applied to a ground selection line GSL and a string selection line SSL, and a ground voltage to about 0.2 volts are applied to a common source line CSL. Because word lines are connected as a parallel structure in a plurality of layers, the voltage is selectively applied to the layer not to result in a parallel path in the read operation.

When a cell transistor B is read in the equivalent circuit diagram ofFIG. 3, a read voltage, for example about zero volts 0V, is applied to a selected cell word line WL2(2), a pass voltage, for example about 4.5 volts, is applied to other word lines WL2(1), . . . , WL2(N-1), WL2(N) connected to a sub-string including a selected cell. A ground voltage or a minus voltage is applied to word lines WL1(1), WL1(2), . . . , WL1(N-1), WL1(N) connected to a sub-string not including the selected cell to turn off. A bit line voltage is applied to a selected bit line BL1, a ground voltage is applied to an unselected bit line BL2, a reference voltage is applied to a ground selection line GSL and a string selection line SSL, and a ground voltage to about 0.2 volts is applied to a common source line CSL.

In the equivalent circuit diagram ofFIG. 3, an erase operation may be carried out as a block unit. A common source line CSL and bit lines BL1, BL2are floated, zero volts 0V are applied to word lines, and an erase voltage is applied to a semiconductor substrate (reference number1ofFIG. 2) and a well (not illustrated) of a single crystalline semiconductor layer (reference number25ofFIG. 2) to remove electrons trapped in the charge storage layers (reference numbers5and31ofFIG. 2).

FIGS. 4 through 8are flow charts illustrating methods of forming a NAND-type nonvolatile memory device ofFIG. 2.

Referring toFIG. 4, a first device isolation layer (Fox1ofFIG. 1) is formed in a semiconductor substrate to define an active region. A heat oxide layer (not illustrated), a first charge storage layer5, and a first blocking insulation layer7are formed in the semiconductor substrate1. The blocking insulation layer7and the first charge storage layer5are removed in a region where selection lines GSL, SSL will be formed. Otherwise, after a heat oxide layer (not illustrated) and a first charge storage layer5are first formed, the first charge storage layer5is removed in a region where selection lines GSL, SSL will be formed. Subsequently, a first blocking insulation layer7is formed on an entire surface. The selection lines GSL, SSL do not include a first charge storage layer5. The heat oxide layer may be a first tunnel oxide layer3bof first word lines WL1or a gate dielectric layer3aof selection lines GSL, SSL. A first gate electrode layer9is formed over an entire surface of the semiconductor substrate1where the first blocking insulation layer7is formed. For example, the first blocking insulation layer7may be formed of a silicon oxide layer and the first charge storage layer5may be formed of a silicon nitride layer. The first gate electrode layer9, the first blocking insulation layer7, the first charge storage layer5, and the heat oxide layer (not illustrated) are patterned to form a plurality of first word lines WL1. The first gate electrode layer9and the heat oxide layer (not illustrated) are patterned to form selection lines GSL, SSL. An ion-implantation process is carried out to form an impurity-doped region11in the semiconductor substrate1on both sides of the lines WL1, SSL, GSL. A first etch stopping layer13is conformably formed on an entire surface of the semiconductor substrate1.

Referring toFIG. 5, a first lower interlayer dielectric layer15is stacked on the first etch stopping layer13. The first lower interlayer dielectric layer15and the first etch stopping layer13is patterned to form a common source line groove (not illustrated) exposing the first impurity-doped region11between the ground selection line GSL and a neighboring ground selection line GSL. The groove is filled by a conductive layer and then planarized to form a common source line17. A first upper interlayer dielectric layer19is stacked on an entire surface of the semiconductor substrate1where the common source line17is formed. The first lower interlayer dielectric layer15and the first upper interlayer dielectric layer19comprise a first interlayer dielectric layer. The first upper interlayer dielectric layer19, the first lower interlayer dielectric layer15, and the first etch stopping layer13are patterned to form a contact hole exposing the semiconductor substrate1between the ground selection line GSL and a neighboring first word line WL1, and between the string selection line SSL and a neighboring first word line WL1.

Referring toFIG. 6, an epitaxial layer may be grown using selective epitaxial growth SEG from the semiconductor substrate1exposed by the contact hole21to form an epitaxial contact plug23filling the contact hole21. While the epitaxial layer is grown, an impurity may be doped by an in-situ process. For example, arsenic or phosphorus may be used as dopants at a dose of 1×1018to 1×1020atoms per cm3. A single crystalline semiconductor layer25is formed on an entire surface of the semiconductor substrate1where the epitaxial contact plug23is formed. The single crystalline semiconductor layer25may be formed by continuously growing the epitaxial layer after filling the contact hole21. Otherwise, the single crystalline semiconductor layer25, for example, may be formed by using a solid phase epitaxial SPE method such that an amorphous polysilicon layer (not illustrated) is stacked and a heat-treatment process, such as a laser annealing, is carried out to change the amorphous polysilicon layer so as to have a single crystalline silicon structure. As a result, an upper surface of the epitaxial contact plug23may function as a single crystalline seed layer. The planarization process may be carried out on an upper surface of the single crystalline semiconductor layer25.

Referring toFIG. 7, a second device isolation layer27(Fox2ofFIG. 1) is formed by a shallow trench isolation method in the single crystalline semiconductor layer25to define an active region. The second device isolation layer27may be formed by filling a second interlayer dielectric layer43formed in a subsequent process. A second tunnel oxide layer29, a second charge storage layer31, a second blocking insulation layer33, and a second gate electrode layer35are stacked on the single crystalline semiconductor layer25and patterned to form a plurality of second word lines WL2. A second impurity-doped region37is formed in the single crystalline semiconductor layer25on both sides of the second word lines WL2by using an ion-implantation mask on the second word lines. An impurity-doped contact region39is formed by using a separate ion-implantation mask on the single crystalline semiconductor layer25between the epitaxial contact plug23and the second impurity-doped region37. Otherwise, while the single crystalline semiconductor layer25is formed, the impurity-doped contact region39may be formed by doping an impurity in-situ or, before the second word lines WL2are formed, the impurity-doped contact region39may be formed by using a separate ion-implantation mask.

Referring toFIG. 8, a second interlayer dielectric layer43is formed on the second etch stopping layer41. The second interlayer dielectric layer43, the second etch stopping layer41, the second device isolation layer27, the first upper interlayer dielectric layer19, the first lower interlayer dielectric layer15, and the first etch stopping layer13are patterned to form a bit line contact hole45exposing the semiconductor substrate1between the string selection line SSL and a neighboring string selection line SSL.

Subsequently, referring toFIG. 2, a conductive layer is formed to fill the bit line contact hole45and the conductive layer is patterned to form a bit line contact47and the bit line49, which fills the bit line contact hole45.

The impurity injection regions11,37, the impurity-doped contact region39, and the epitaxial contact plug23may be formed by doping the same type impurity, for example, by doping arsenic or phosphorus at a dose of 1×1018to 1×1020atoms per cm3. A second etch stopping layer41is conformably formed in the single crystalline semiconductor layer25where the second word lines WL2are formed.

FIG. 9is a plane view illustrating a NAND-type nonvolatile memory device having a stacked structure according to other embodiments of the present invention.FIG. 10is a cross-sectional view taken along line ofFIG. 9.

Referring toFIG. 9andFIG. 10, a plurality of parallel first device isolation layers Fox1are formed in the semiconductor substrate1to define an active region, and a first ground selection line GSL1and a first string selection line SSL1cross the first device isolation layer Fox1in parallel. A plurality of first word lines are arranged in parallel between the first ground selection line GSL1and the first string selection line SSL1. The first word lines WL1connect to a first cell transistor including a first tunnel insulation layer3b, a first charge storage layer5, a first blocking insulation layer7, and a first gate electrode9that are stacked sequentially. The string selection line SSL1and the first ground selection line GSL1connect to first string selection transistors and first ground selection transistors, respectively, including a gate electrode3aand a first gate electrode9that are stacked sequentially. The first string selection line SSL1and the first ground selection line GSL1do not include the first charge storage layer5. An etch stopping layer13, a first lower interlayer dielectric layer15, and a first upper interlayer dielectric layer19are formed to cover the lines GSL1, SSL1, WL1sequentially. A first impurity-doped region11is located in the semiconductor substrate1on both sides of the lines GSL1, SSL1, WL1. A first common source line17is located between the first ground selection line GSL1and a neighboring first ground selection line GSL1and penetrates the first lower interlayer dielectric layer15and the first etch stopping layer13to contact the first impurity-doped region11. An epitaxial contact plug23is located in a hole21that penetrates the first upper interlayer dielectric layer19, the first lower interlayer dielectric layer15, and the first etch stopping layer13between the first string selection line SSL1and a neighboring first string selection line SSL1to contact the first impurity-doped region11. As shown inFIGS. 8 and 10, the epitaxial contact plug23functions as a seed layer for forming a subsequent single crystalline semiconductor layer25and as a bit line contact.

Referring toFIG. 9andFIG. 10, a single crystalline semiconductor layer25contacting the epitaxial contact plug23is located on the first upper interlayer dielectric layer19. A second device isolation layer Fox2is arranged to define an active region in the single crystalline semiconductor layer25. In the single crystalline semiconductor layer25, a second ground selection line GSL2, a second string selection line SSL2and a plurality of second word lines WL2interposed therebetween are arranged in parallel to cross the second device isolation layer Fox2,27. The second word lines WL2connect to second cell transistors including a second tunnel insulation layer29b, a second charge storage layer31, a second blocking insulation layer33, and a second gate electrode35that are stacked sequentially. The second string selection line SSL2and the second ground selection line GSL2connect to second string selection transistors and second ground selection transistors, respectively, including a gate insulation layer29aand a second gate electrode35that are stacked sequentially. The second string selection line SSL2and the second ground selection line GSL2do not include the second charge storage layer31. The second ground selection line GSL2, the second string selection line SSL2, and the second word lines WL2overlap the first ground selection line GSL1, the first string selection line SSL1, and the first word lines WL1, respectively. A second impurity injection line37is located in the single crystalline semiconductor layer25on both sides of the second string selection line SSL2, the second ground selection line GSL2, and the second word lines WL2. An impurity-doped contact region39may exist in the single crystalline semiconductor layer25between the epitaxial contact plug23and the second impurity-doped region37to electrically connect the epitaxial contact plug23and the second impurity-doped region37. Otherwise, without the impurity-doped contact region39, the second impurity-doped region37may directly contact the epitaxial contact plug23.

A second etch stopping layer41, a second lower interlayer dielectric layer42, and a second upper interlayer dielectric layer44are formed to cover the second lines GSL2, SSL2, WL2sequentially. A common source line43is located between the second ground selection line GSL2and a neighboring second ground selection line GSL2and penetrates the second lower interlayer dielectric layer42and the second etch stopping layer41to contact the second impurity-doped region37. A bit line contact plug47is located in a bit line contact hole (not illustrated) that penetrates the second upper interlayer dielectric layer44, the second lower interlayer dielectric layer42, and the second etch stopping layer41to expose the single crystalline semiconductor layer25between the second string selection line SSL2and a neighboring second string selection line SSL2. A plurality of parallel bit lines49electrically connected to the bit line contact plug47are arranged on the second upper interlayer dielectric layer44.

Referring toFIG. 9andFIG. 10, a cell string includes a first ground selection transistor connected to the first ground selection line GSL1, a first string selection transistor connected to the first string selection line SSL1, and first cell transistors connected to the word lines WL1therebetween. Another cell string includes a second ground selection transistor connected to the second ground selection line GSL2, a second string selection transistor connected to the second string selection line SSL2, and second cell transistors connected to the word lines WL2therebetween. Two cell strings located in an upper and a lower layer are influenced by a voltage applied from the bit line49through the bit line contact plug47and the epitaxial contact plug23, respectively.

Although two strings are located in an upper and a lower layer, respectively, the memory device may advantageously use an existing plane view because a flat arrangement of a string in each layer is the same as a conventional NAND-type nonvolatile memory device formed on one layer. Because a cell string in each layer is operated by a ground selection line and a string selection line, each cell string may be separately derived compared with a parallel structure of word lines of the embodiments ofFIGS. 1 and 2. Because cell strings are arranged in a plurality of layers, an entire cell size may be reduced regardless of a limit associated with a photolithography process.

Although not illustrated, in a NAND-type nonvolatile memory device ofFIG. 9andFIG. 10, wells (not shown) may be formed in the single crystalline semiconductor layer25and the semiconductor substrate1, such that the wells may be connected to different well contacts (not shown) and applied different voltages.

Although two cell strings are arranged in an upper and a lower layer, respectively, in the embodiments ofFIGS. 9 and 10, cell strings may be arranged in more than three layers. Also, nonvolatile memory devices having a structure according to a combination of the embodiments ofFIGS. 1 and 2and the embodiments ofFIGS. 9 and 10may also be formed.

Referring toFIG. 11, methods of operating the NAND-type nonvolatile memory device ofFIGS. 9 and 10, according to some embodiments of the present invention, will be described.FIG. 11is an equivalent circuit diagram illustrating a NAND-type nonvolatile memory device ofFIG. 9.

Referring toFIG. 11, one of the bit lines BL1, BL2is connected to two cell strings of an upper and a lower layer. A cell string includes a first string selection transistor connected to a first string selection line SSL1, a first ground selection transistor connected to a ground selection line GSL1, and n first cell transistors connected to n first word lines WL1(1), WL1(2), . . . , WL1(N-1), WL1(N), respectively, between the selection lines SSL1, GSL1. Another cell string includes a second string selection transistor connected to a second string selection line SSL2, a second ground selection transistor connected to a second ground selection line GSL2, and n second cell transistors connected to n second word lines WL2(1), WL2(2), . . . , WL2(N-1), WL2(N), respectively, between the selection lines SSL2, GSL2. The cell strings are connected to common source lines CSL1, CSL2respectively.

In some embodiments illustrated in the equivalent circuit diagram ofFIG. 11, methods of programming a cell memory transistor A may be similar to a method of programming an existing NAND-type nonvolatile memory device. That is, zero volts 0V may be applied to a selected first bit line BL1, Vcc (a reference voltage) may be applied to a selected first string selection line SSL1, zero volts 0V may be applied to a selected first ground selection line GSL1, and zero volts 0V may be applied to a selected first common source line CSL1. A program voltage, for example twenty volts 20V, may be applied to a first word line WL1(2) of a selected cell and a pass voltage, for example ten volts 10V, may be applied to first word lines WL1(1), . . . , WL1(N-1), WL1(N) of an unselected cell. Second lines SSL2, WL2(1), WL2(2), . . . , WL2(N-1), WL2(N), GSL2, CSL2comprising an upper string connected to the first bit line BL1may not have a turn-off voltage applied thereto.

When a cell memory transistor B is programmed in the equivalent circuit diagram ofFIG. 11, zero volts 0V is applied to a selected first bit line BL1, Vcc (a reference voltage) is applied to a selected second string selection line SSL2, zero volts 0V is applied to a selected second ground selection line GSL2, and zero volts 0V is applied to a selected second common source line CSL2. A program voltage, for example twenty volts 20V, is applied to a second word line WL2(2) of a selected cell, and a pass voltage, for example ten volts 10V, is applied to second word lines WL2(1), . . . , WL2(N-1), WL2(N) of an unselected cell. First lines SSL1, WL1(1), WL(2), . . . , WL1(N-1), WL1(N), GSL1, CSL1comprising a lower string connected to the first bit line BL1do not have a turn-off voltage applied thereto.

When reading a cell memory transistor A in the equivalent circuit diagram ofFIG. 11, a selected first string selection line SSL1and a first ground selection line GSL1are turned off. A read voltage, for example zero volts 0V, is applied to a first word line WL1(2) of a selected cell and a pass voltage, for example four to five volts, is applied to first word lines WL1(1), . . . , WL1(N-1), WL1(N) of an unselected cell. By turning off a second string selection line SSL2of an unselected cell, current does not flow into an unselected upper string due to a voltage applied via a bit line BL1.

When reading a cell memory transistor B in the equivalent circuit diagram ofFIG. 11, a selected second string selection line SSL2and a second ground selection line GSL2are turned off. A read voltage, for example zero volts 0V, is applied to a second word line WL2(2) of a selected cell and a pass voltage, for example four to five volts, is applied to second word lines WL2(1), . . . , WL2(N-1), WL2(N) of an unselected cell. By turning off an unselected first string selection line SSL1, current does not flow into an unselected upper string due to a voltage applied via a bit line BL1.

In some embodiments illustrated in the equivalent circuit diagram ofFIG. 11, an erase operation may be carried out by a block unit.

All word lines in a selected block have zero volts 0V applied thereto and a well (not shown) applies an erase voltage, for example twenty volts 20V, to erase.

FIG. 12is a cross-sectional view that illustrates methods of forming a NAND-type nonvolatile memory device ofFIG. 10in accordance with some embodiments of the present invention.

Referring toFIG. 12, a first ground selection line GSL1, a first string selection line SSL1, first word lines WL1, and a first common source line17are formed on the semiconductor substrate1using methods similar to those discussed above. A first upper interlayer dielectric layer19, a first lower interlayer dielectric layer15, and a first etch stopping layer13are sequentially patterned to form a hole21that exposes the semiconductor substrate1between the first string selection line SSL1and a neighboring first string selection line SSL1. An epitaxial layer is grown in the hole21to form an epitaxial contact plug23that fills the hole21. A single crystalline semiconductor layer25is formed on the first upper interlayer dielectric layer19by methods similar to those discussed above. A second ground selection line GSL2, a second string selection line SSL2, and second word lines WL2are formed on the single crystalline semiconductor layer25in similar fashion to the formation of the first lines GSL1, SSL1, WL1. A second impurity-doped region37is formed in the single crystalline semiconductor layer25by using an ion-implantation mask in the second lines GSL2, SSL2, WL2. An impurity-doped contact region39is formed in the single crystalline semiconductor layer25between the epitaxial contact plug23and the second impurity-doped region37. In accordance with various embodiments of the present invention, methods of forming the impurity-doped contact region39may have different sequences as discussed above. For conformably covering the second lines GSL2, SSL2, WL2, a second etch stopping layer41is formed on an entire surface.

Subsequently, referring toFIG. 10, a second lower interlayer dielectric layer42is stacked on the second etch stopping layer41. The second lower interlayer dielectric layer42and the second etch stopping layer are penetrated between the second ground selection line GSL2and a neighboring second ground selection line GSL2to form a second common source line43contacting the second impurity-doped region37. A second upper interlayer dielectric layer44is formed on the second lower interlayer dielectric layer42. The second upper interlayer dielectric layer44, the second lower interlayer dielectric layer42, and the second etch stopping layer41are penetrated between the second string selection line SSL2and a neighboring second string selection line to form a bit line contact plug47contacting the second impurity-doped region37. A bit line49connected to the bit line contact plug47is formed on the second upper interlayer dielectric layer44to complete a NAND-type nonvolatile memory device as shown inFIG. 10. The process conditions associated with the embodiments ofFIGS. 12 and 10may be the same as those used in the embodiments discussed above. Although not illustrated, control circuits such as a row recorder may be formed on the single crystalline semiconductor layer25.

According to some embodiments of NAND-type nonvolatile memory devices and methods of forming the same, word lines may be formed using a plurality of layers to reduce cell size area. In addition, a number of cell arrays may increase so as to increase cell memory capacity.