SIGNAL LINE SENSE AMPLIFYING CIRCUIT AND INTEGRATED CIRCUIT CAPABLE OF CALIBRATING DRIVING STRENGTH OF MOS TRANSISTORS

An integrated circuit includes an operation control circuit configured to control generation of a sharing signal, a pre-charge signal, a sensing signal, a latch signal, and a calibration enable signal for a calibration operation and a sense amplifying operation. The integrated circuit also includes a signal line sense amplifying circuit configured to receive the sharing signal, the pre-charge signal, the sensing signal, the latch signal, and the calibration enable signal to perform the calibration operation and the sense amplifying operation.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. 119(a) to Korean Patent Application No. 10-2022-0085245, filed on Jul. 11, 2022, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Embodiments of the present disclosure relate to a signal line sense amplifying circuit and an integrated circuit that are capable of calibrating the driving strength of MOS transistors.

2. Related Art

In general, an integrated circuit may receive or output various signals through a plurality of signal lines included therein. When transmitting signals through the signal lines, the integrated circuit uses a signal line sense amplifying circuit to sense and amplify the signals of the signal lines and transmit the signals to other signal lines. The signal line sense amplifying circuit includes a plurality of MOS transistors to sense and amplify the signals of the signal lines. Each of the MOS transistors has various process characteristics, and each of the MOS transistors is set to have a driving strength that is determined according to the process characteristics.

SUMMARY

The present disclosure may provide an integrated circuit including an operation control circuit configured to control generation of a sharing signal, a pre-charge signal, a sensing signal, a latch signal, and a calibration enable signal for a calibration operation and a sense amplifying operation, and a signal line sense amplifying circuit configured to receive the sharing signal, the pre-charge signal, the sensing signal, the latch signal, and the calibration enable signal to perform the calibration operation and the sense amplifying operation.

In the present disclosure, the signal line sense amplifying circuit may include MOS transistors for driving input nodes to which input data and inverted input data are input, is configured to calibrate a driving strength of each of the MOS transistors in the calibration operation, and is configured to generate output data by sensing and amplifying the input data and the inverted input data in the sense amplifying operation performed in a state in which the calibration operation is performed.

In addition, the present disclosure may provide a signal line sense amplifying circuit including a sense amplifying circuit including MOS transistors for driving input nodes to which input data and inverted input data are input in a calibration operation and a sense amplifying operation, and a calibration circuit configured to generate calibration signals for calibrating a driving strength of each of the MOS transistors in the calibration operation.

In the present disclosure, the sense amplifying circuit may be configured to sense and amplify the input data and the inverted input data to generate output data and inverted output data in the sense amplifying operation performed in a state in which the calibration operation is performed based on the calibration signals.

In addition, the present disclosure may provide signal line sense amplifying circuit including a sense amplifying circuit including MOS transistors for driving input nodes to which input data and inverted input data are input in a calibration operation and a sense amplifying operation, a first calibration circuit configured to generate first calibration signals for calibrating a driving strength of each of the MOS transistors in the calibration operation, and a second calibration circuit configured to generate second calibration signals for calibrating a driving strength of each of the MOS transistors in the calibration operation.

In the present disclosure, the sense amplifying circuit may be configured to sense and amplify the input data and the inverted input data to generate output data and inverted output data in the sense amplifying operation performed in a state in which the calibration operation is performed based on the first calibration signals and the second calibration signals.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following description of embodiments, when a parameter is referred to as being “predetermined,” it may be intended to mean that a value of the parameter is determined in advance when the parameter is used in a process or an algorithm. The value of the parameter may be set when the process or the algorithm starts or may be set during a period that the process or the algorithm is executed.

It will be understood that although the terms “first,” “second,” “third,” etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element and are not intended to imply an order or number of elements. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present disclosure.

A logic “high” level and a logic “low” level may be used to describe logic levels of electric signals. A signal having a logic “high” level may be distinguished from a signal having a logic “low” level. For example, when a signal having a first voltage corresponds to a signal having a logic “high” level, a signal having a second voltage corresponds to a signal having a logic “low” level. In an embodiment, the logic “high” level may be set as a voltage level which is higher than a voltage level of the logic “low” level. Meanwhile, logic levels of signals may be set to be different or opposite according to the embodiments. For example, a certain signal having a logic “high” level in one embodiment may be set to have a logic “low” level in another embodiment.

The term “logic bit set” may mean a combination of logic levels of bits included in a signal. When the logic level of each of the bits included in the signal is changed, the logic bit set of the signal may be set differently. For example, when the signal includes 2 bits, when the logic level of each of the 2 bits included in the signal is “logic low level, logic low level”, the logic bit set of the signal may be set as the first logic bit set, and when the logic level of each of the two bits included in the signal is “logic low level, logic high level”, the logic bit set of the signal may be set as the second logic bit set.

Various embodiments of the present disclosure will be described hereinafter in more detail with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

FIG.1is a block diagram illustrating a configuration of an integrated circuit1according to an embodiment of the present disclosure. As illustrated inFIG.1, the integrated circuit1may include an operation control circuit (OP CTR)11and a signal line sense amplifying circuit (SLSA)13.

The operation control circuit11may include one or more processors and/or logic gates. The operation control circuit11may control the generation of a sharing signal SHAR, a pre-charge signal PCG, a sensing signal SEN, a latch signal LATS, and a calibration enable signal CEN, based on a calibration operation signal CAL_OP and a sense amplifying operation signal SA_OP. The sharing signal SHAR may be generated to enable a first signal line (SL1ofFIG.2) and a first inverted signal line (SL1B ofFIG.2) to share signals with input nodes (n111and n112ofFIG.2) each other. As an example, the first signal line (SL1ofFIG.2) may share the signal with one of the input nodes (n111and n112ofFIG.2), and the first inverted signal line (SL1B inFIG.2) may share the signal with the other of the input nodes (n111and n112ofFIG.2). When the first signal line (SL1inFIG.2) and the first inverted signal line (SL1B inFIG.2) and the input nodes (n111and n112inFIG.2) share signals, a voltage level difference may be generated between the input nodes (n111and n112ofFIG.2) by the signals of the first signal line (SL1ofFIG.2) and the first inverted signal line (SL1B ofFIG.2). The pre-charge signal PCG may be generated for a pre-charge operation of setting the voltage levels of the input nodes (n111and n112ofFIG.2) to be the same. The sensing signal SEN may be generated to sense and amplify input data (DIN ofFIG.2) and inverted input data (DINB ofFIG.2). The latch signal LATS may be generated to generate output data (DOUT ofFIG.2) and inverted output data (DOUTB ofFIG.2) from the input data (DIN ofFIG.2) and the inverted input data (DINB ofFIG.2), respectively. The output data (DOUT ofFIG.2) and the inverted output data (DOUTB ofFIG.2) may be output through a second signal line (SL2ofFIG.2) and a second inverted signal line (SL2B ofFIG.2), respectively. The calibration enable signal CEN may be generated to generate a first calibration signal CAL1and a second calibration signal CAL2by the output data (DOUT ofFIG.2) and the inverted output data (DOUTB ofFIG.2), respectively, in a calibration operation. The calibration operation signal CAL_OP may be generated to perform the calibration operation for calibrating the driving strength of the metal-oxide semiconductor field-effect (MOS) transistors (113_1and113_2ofFIG.2) included in the signal line sense amplifying circuit13.

The operation control circuit11may sequentially apply the pre-charge signal PCG, the sensing signal SEN, the latch signal LATS, and the calibration enable signal CEN whose generation is controlled based on the calibration operation signal CAL_OP to the signal line sense amplifying circuit13in the calibration operation. The sense amplifying operation signal SA_OP may be generated to perform a sense amplifying operation of sensing and amplifying the input data (DIN ofFIG.2) and the inverted input data (DINB ofFIG.2) that are input through the first signal line (SL1ofFIG.2) and the first inverted signal line (SL1B ofFIG.2), respectively, in a state in which the calibration operation is performed and the driving strength of the MOS transistors (113_1and113_2inFIG.2) is calibrated. The operation control circuit11may sequentially apply the pre-charge signal PCG, the sharing signal SHAR, the sensing signal SEN, and the latch signal LATS whose generation is controlled based on the sense amplifying operation signal SA_OP to the signal line sense amplifying circuit13in the sense amplifying operation.

The signal line sense amplifying circuit13may be connected to the operation control circuit11and may receive the sharing signal SHAR, the pre-charge signal PCG, the sensing signal SEN, the latch signal LATS, and the calibration enable signal CEN from the operation control circuit11. The signal line sense amplifying circuit13may receive a reset signal RSTB, the pre-charge signal PCG, the sensing signal SEN, the latch signal LATS, and the calibration enable signal CEN to perform the calibration operation. The signal line sense amplifying circuit13may be initialized by the reset signal RSTB in the calibration operation. The signal line sense amplifying circuit13may perform the pre-charge operation of setting the logic levels of the input data (DIN ofFIG.2) and the inverted input data (DINB ofFIG.2) to be the same by the pre-charge signal PCG in the calibration operation. The signal line sense amplifying circuit13may sense and amplify the input data (DIN ofFIG.2) and the inverted input data (DINB ofFIG.2) by the sensing signal SEN in the calibration operation. The signal line sense amplifying circuit13may generate the output data (DOUT ofFIG.2) and the inverted output data (DOUTB ofFIG.2) from the input data (DIN ofFIG.2) and the inverted input data (DINB ofFIG.2) by the latch signal LATS, respectively, and may output the output data (DOUT ofFIG.2) and the inverted output data (DOUTB ofFIG.2) through the second signal line (SL2ofFIG.2) and the second inverted signal line (SL2B ofFIG.2), respectively, in the calibration operation. The signal line sense amplifying circuit13may generate the first calibration signal CAL1and the second calibration signal CAL2from the output data (DOUT ofFIG.2) and the inverted output data (DOUTB ofFIG.2), respectively, by the calibration enable signal CEN in the calibration operation. The signal line sense amplifying circuit13may calibrate the driving strength of the MOS transistors (113_1and113_2ofFIG.2) by the first calibration signal CAL1and the second calibration signal CAL2. The signal line sense amplifying circuit13may receive the pre-charge signal PCG, the sharing signal SHAR, and the latch signal LATS to perform the sense amplifying operation after the calibration operation. The signal line sense amplifying circuit13may stop the pre-charge operation by the pre-charge signal PCG in the sense amplifying operation performed after the calibration operation. The signal line sense amplifying circuit13may enable the first signal line (SL1ofFIG.2) and the first inverted signal line (SL1B ofFIG.2) to share the signals with the input nodes (n111and n112ofFIG.2) by the sharing signal SHAR in the sense amplifying operation performed after the calibration operation. The signal line sense amplifying circuit13may generate the output data (DOUT ofFIG.2) and the inverted output data (DOUTB ofFIG.2) from the input data (DIN ofFIG.2) and the inverted input data (DINB ofFIG.2), respectively, by the latch signal LATS in the sense amplifying operation performed after the calibration operation, and may output the output data (DOUT ofFIG.2) and the inverted output data (DOUTB ofFIG.2) through the second signal line (SL2ofFIG.2) and the second inverted signal line (SL2B ofFIG.2), respectively.

FIG.2is a circuit diagram of a signal line sense amplifying circuit13A according to an embodiment of the present disclosure. As shown inFIG.2, the signal line sense amplifying circuit13A may include a sense amplifying circuit110and a calibration circuit120.

The sense amplifying circuit110may include PMOS transistors111_1,111_2,111_3,111_4, and111_5; NMOS transistors113_1,113_2, and113_3; NAND gates115_1and115_2; and switching devices117_1and117_2. The PMOS transistor111_1may be turned on when a pre-charge signal PCG is generated at a logic “low” level for a pre-charge operation to drive input data DIN to a logic “high” level. The PMOS transistor111_2may be turned on when the pre-charge signal PCG is generated at a logic “low” level for the pre-charge operation to drive inverted input data DINB to a logic “high” level. The PMOS transistor111_3may be turned on when the pre-charge signal PCG is generated at a logic “low” level for the pre-charge operation to set the voltage level of the input data DIN to be the same as the voltage level of the inverted input data DINB. The PMOS transistors111_1,111_2, and111_3may be turned off by the pre-charge signal PCG generated at a logic “high” level in a calibration operation and a sense amplifying operation. The PMOS transistor111_4may be turned on by the inverted input data DINB of a node n112when a sensing signal SEN is generated at a logic “high” level to drive the input data DIN of the node n111to a logic “high” level in the calibration operation and the sense amplifying operation. The nodes n111and n112may be set as input nodes. The PMOS transistor111_5may be turned on by the input data DIN of the node n111when the sensing signal SEN is generated at a logic “high” level to drive the inverted input data DINB of the node n112to a logic “high” level in the calibration operation and the sense amplifying operation.

The NMOS transistor113_1may be connected between the node n111and a node n113, and may be turned on by the inverted input data DINB of the node n112when the sensing signal SEN is generated at a logic “high” level to drive the input data DIN of the node n111to a logic “low” level in the calibration operation and the sense amplifying operation. The NMOS transistor113_2may be connected between the node n112and the node n113, and may be turned on by the input data DIN of the node n111when the sensing signal SEN is generated at a logic “high” level to drive the inverted input data DINB of the node n112to a logic “low” level in the calibration operation and the sense amplifying operation. The NMOS transistor113_3may be turned on when the sensing signal SEN is generated at a logic “high” level to drive the node n113to a logic “low” level in the calibration operation and the sense amplifying operation. The NAND gate115_1may receive a latch signal LATS and the input data DIN to perform a logical NAND operation. The NAND gate115_1may inversely buffer the input data DIN when the latch signal LATS is generated at a logic “high” level to output the inversely buffered signal of the input data DIN as the inverted output data DOUTB of a node n114in the calibration operation and the sense amplifying operation. The inverted output data DOUTB may be output through a second inverted signal line SL2B. The NAND gate115_2may receive the latch signal LATS and the inverted input data DINB to perform a logical NAND operation. The NAND gate115_2may inversely buffer the inverted input data DINB when the latch signal LATS is generated at a logic “high” level to output the inversely buffered signal of the inverted input data DINB as the output data DOUT of a node n115in the calibration operation and the sense amplifying operation. The output data DOUT may be output through a second signal line SL2.

The switching device117_1may be turned on when the sharing signal SHAR is generated at a logic “high” level and may connect the first signal line SL1and the node n111so that the first signal line SL1and the node n111share the input data DIN with each other in the sense amplifying operation. The switching device117_2may be turned on when the sharing signal SHAR is generated at a logic “high” level and may connect the first inverted signal line SL1B and the node n112so that the first inverted signal line SL1B and the node n112share the inverted input data DINB with each other in the sense amplifying operation. A voltage difference may occur between the input data DIN shared by the first signal line SL1and the inverted input data DINB shared by the first inverted signal line SL1B.

The calibration circuit120may include PMOS transistors121_1and121_2; NMOS transistors122_1,122_2,125_1,125_2,125_3,125_4,127_1, and127_2; and inverters123_1,123_2,123_3, and123_4. The PMOS transistor121_1may be turned on when a reset signal RSTB is generated at a logic “low” level for initialization to initialize a node n121to a logic “high” level. The PMOS transistor121_2may be turned on when the reset signal RSTB is generated at a logic “low” level for initialization to initialize a node n123to a logic “high” level. The NMOS transistor122_1may be connected between the node n114and the node n121, and may be turned on when a calibration enable signal CEN is generated at a logic “high” level for the calibration operation to set the logic level of the node n121according to the inverted output signal DOUTB of the node n114. The NMOS transistor122_2may be connected between the node n115and the n123, and may be turned on when the calibration enable signal CEN is generated at a logic “high” level for the calibration operation to set the logic level of the node n123according to the output signal DOUT of the node n115. The inverter123_1may inversely buffer the signal of the node n121to output the inversely buffered signal of the node n121as the first calibration signal CALL The inverter123_2may inversely buffer the first calibration signal CAL1of the node n122to output the inversely buffered signal of the first calibration signal CAL1to the node n121when the calibration operation is not performed and the calibration enable signal CEN is generated at a logic “low” level. The inverter123_3may inversely buffer the signal of the node n123to output the inversely buffered signal of the node n123as the second calibration signal CAL2of the node n124. The inverter123_4may inversely buffer the second calibration signal CAL2of the node n124to output the inversely buffered signal of the second calibration signal CAL2to the node n123when the calibration operation is not performed and the calibration enable signal CEN is generated at a logic “low” level. The logic levels of the first calibration signal CAL1and the second calibration signal CAL2may be determined by the driving strength of the NMOS transistor113_1and the driving strength of the NMOS transistor113_2, respectively. For example, when the driving strength of the NMOS transistor113_1is set to be weaker than the driving strength of the NMOS transistor113_2, the first calibration signal CAL1may be generated at a logic “high” level, and the second calibration signal CAL2may be generated at a logic “low” level. In another example, when the driving strength of the NMOS transistor113_2is set to be weaker than the driving strength of the NMOS transistor113_1, the first calibration signal CAL1may be generated at a logic “low” level, and the second calibration signal CAL2may be generated at a logic “high” level. In further another example, when the driving strength of the NMOS transistor113_2and the driving strength of the NMOS transistor113_1are set to be the same, both the first calibration signal CAL1and the second calibration signal CAL2may be generated at logic “high” levels. The NMOS transistors125_1and125_2may be connected in series between the node n111and the node n113. The NMOS transistor125_1may be turned on when the driving strength of the NMOS transistor113_1is set to be weaker than that of the NMOS transistor113_2and the first calibration signal CAL1is generated at a logic “high” level, and may operate as a calibration device that calibrates the driving strength of the NMOS transistor113_1. The NMOS transistor125_2may be turned on when the inverted input signal DINB of the node n112is at a logic “high” level. The NMOS transistors125_3and125_4may be connected in series to each other between the node n112and the node n113. The NMOS transistor125_3may be turned on when the driving strength of the NMOS transistor113_2is set to be weaker than that of the NMOS transistor113_1and the second calibration signal CAL2is generated at a logic “high” level, and may operate as a calibration device that calibrates the driving strength of the NMOS transistor113_2. The NMOS transistor125_4may be turned on when the input signal DIN of the node n111is at a logic “high” level. The NMOS transistor127_1may be connected between the node n111and a floating node, and may be turned on by the second calibration signal CAL2. The NMOS transistor127_2may be connected between the node n112and the floating node, and may be turned on by the first calibration signal CAL1. Each of the NMOS transistor127_1and the NMOS transistor127_2may operate as a compensating device that compensates for a capacitance difference between the input nodes n111and n112after the calibration operation is performed. For example, when the first calibration signal CAL1is generated at a logic “high” level and the second calibration signal CAL2is generated at a logic “low” level by the calibration operation, the NMOS transistor125_1connected to the node n111and the NMOS transistor127_2connected to the node n112may be symmetrically turned on, and the NMOS transistor125_3connected to the node n112and the NMOS transistor127_1connected to the node n111may be symmetrically turned off. Accordingly, the capacitance difference between the input nodes n111and n112may be reduced or minimized. In another example, when the first calibration signal CAL1is generated at a logic “low” level and the second calibration signal CAL2is generated at a logic “high” level by the calibration operation, the NMOS transistor125_3connected to the node n112and the NMOS transistor127_1connected to the node n111may be symmetrically turned on, and the NMOS transistor125_1connected to the node n111and the NMOS transistor127_2connected to the node n112may be symmetrically turned off. Accordingly, the capacitance difference between the input nodes n111and n112may be reduced or minimized. The NMOS transistors127_1and127_2might not be used according to embodiments.

The signal line sense amplifying circuit13A may perform the calibration operation of setting the logic levels of the first calibration signal CAL1and the second calibration signal CAL2according to the driving strength of the NMOS transistor113_1and the NMOS transistor113_2, respectively, and may perform the sense amplifying operation of sensing and amplifying the signals of the first signal line SL1and the first inverted signal line SL2in a state in which the driving strength of the NMOS transistor113_1and the driving strength of the NMOS transistor113_2are calibrated to output the sense amplified signals through the second signal line SL2and the second inverted signal line SL2B.

FIGS.3to8are a timing diagram and circuit diagrams illustrating a calibration operation of a signal line sense amplifying circuit13A according to an embodiment of the present disclosure. Hereinafter, the calibration operation of the signal line sense amplifying circuit13A will be described in more detail with reference toFIGS.3to8, and the calibration operation will be described on the assumption that the driving strength of the NMOS transistor113_1is weaker than that of the NMOS transistor113_2. InFIGS.3to8, the same reference numerals as inFIG.2may indicate the same components.

First, as shown inFIGS.3and4, because the NMOS transistors121_1and121_2are turned on when a reset signal RSTB is generated at a logic “low” level (“L”) for initialization at a time point T111, the node n121and node n123may all be initialized to a logic “high” level (“H”), and both the first calibration signal CAL1of the node n122and the second calibration signal CAL2of the node n124may be initialized to a logic “low” level (“L”).

Next, as shown inFIGS.3and5, because a pre-charge signal PCG is generated at a logic low level (“L”) for a pre-charge operation during the section before a time point T112, the PMOS transistors111_1,111_2, and111_3may all be turned on, and the input data DIN of the node n111and the inverted input data DINB of the node n112may all be set to a logic “high” level (“H”).

Next, as shown inFIGS.3and6, because the pre-charge signal PCG transitions from a logic “low” level (“L”) to a logic “high” level (“H”) at the time point T112, the PMOS transistors111_1,111_2, and111_3may all be turned off.

Next, as shown inFIGS.3and6, because a sensing signal SEN is generated at a logic high level (“H”) from a time point T113, the input data DIN of the node n111and the inverted input data DINB of the node n112may be sensed and amplified by the PMOS transistors111_4and111_5and the NMOS transistors113_1and113_2. Because the driving strength of the NMOS transistor113_1is weaker than the driving strength of the NMOS transistor113_2, the input data DIN of the node n111may maintain the logic “high” level (“H”) through the sense amplifying operation by the PMOS transistors111_4and111_5and the NMOS transistors113_1and113_2, and the inverted input data DINB of the node n112may transition from the logic “high” level (“H”) to a logic “low” level (“L”).

Next, as shown inFIGS.3and7, because a latch signal LATS is generated at a logic “high” level (“H”) from a time point T114, inverted output data DOUTB may be generated at a logic “low” level (“L”) by the input data DIN of the logic “high” level (“H”), and output data DOUT may be generated at a logic “high” level (“H”) by the inverted input data DINB of the logic “low” level (“L”).

Next, as shown inFIGS.3and8, because a calibration enable signal CEN is generated at a logic “high” level (“H”) from a time point T115, a first calibration signal CAL1may be generated at a logic “high” level (“H”) by the inverted output data DOUTB of the logic “low” level (“L”), and a second calibration signal CAL2may be generated at a logic “low” level (“L”) by the output data DOUT of the logic “high” level (“H”). When the NMOS transistor125_1is turned on by the first calibration signal CAL1of the logic “high” level (“H”), the NMOS transistors125_1and125_2may drive the input data DIN of the node n111together with the NMOS transistor113_1. Accordingly, the driving strength of the NMOS transistor113_1may be calibrated by the NMOS transistors125_1and125_2.

Finally, as shown inFIG.3, at a time point T116, because the pre-charge signal PCG transitions from the logic “high” level (“H”) to a logic “low” level (“L”) and all of the PMOS transistors111_1,111_2, and111_3may be turned on, a pre-charge operation in which both the input data DIN of the node n111and the inverted input data DINB of the node n112are set to logic “high” levels (“H”) may be performed.

FIGS.9to12are diagrams illustrating a sense amplifying operation of a signal line sense amplifying circuit13A according to an embodiment of the present disclosure. Hereinafter, the sense amplifying operation of the signal line sense amplifying circuit13A will be described with reference toFIGS.9to12, and the sense amplifying operation will be described on the assumption that the sense amplifying operation is performed on the first signal line SL1set to a logic “low” level and the first inverted signal line SL1B set to a logic “high” level in a state in which the driving strength of the NMOS transistor113_1is weaker than that of the NMOS transistor113_2. InFIGS.9to12, the same reference numerals as inFIG.2may indicate the same components.

First, as shown inFIGS.9and10, when a first calibration signal CAL1is generated at a logic “high” level by a calibration operation, the NMOS transistor125_1connected to the node n111may be turned on to calibrate the NMOS transistor113_1having a driving strength that is weaker than that of the NMOS transistor113_2. In addition, when the first calibration signal CAL1is generated at a logic “high” level and a second calibration signal CAL2is generated at a logic “low” level by the calibration operation, the NMOS transistor125_1connected to the node n111and the NMOS transistor127_2connected to the node n112may be symmetrically turned on, and the NMOS transistor125_3connected to the node n112and the NMOS transistor127_1connected to the node n111may be symmetrically turned off. Accordingly, a capacitance difference between the input nodes n111and n112may be reduced or minimized.

Next, as shown inFIGS.9and11, at a time point T121, because the pre-charge signal PCG transitions from a logic “low” level (“L”) to a logic “high” level (“H”), the PMOS transistors111_1,111_2, and111_3may all be turned off. At a time point T122, a sharing signal SHAR is generated at a logic “high” level (“H”) and the first signal line SL1and the first inverted signal line SL1B share signals with the input nodes n111and n112, so that the inverted input data DINB of the node n112may be set to have a higher voltage level than the input data DIN of the node n111. Because the sensing signal SEN is generated at a logic “high” level (“H”) from a time point T123, the input data DIN of the node n111may be generated at a logic “low” level (“L”), and the inverted input data DINB of the node n112may be generated at a logic “high” level (“H”).

Next, as shown inFIGS.9and12, because the latch signal LATS is generated at a logic “high” level (“H”) from a time point T124, the inverted output data DOUTB may be generated at a logic “high” level (“H”) by the input data DIN of a logic “low” level (“L”), and the output data DOUT may be generated at a logic “low” level (“L”) by the inverted input data DINB of a logic “high” level (“H”).

Finally, as shown inFIG.9, at a time point T125, because the pre-charge signal PCG transitions from a logic “high” level (“H”) to a logic “low” level (“L”), a pre-charge operation in which both the input data DIN of the node n111and the inverted input data DINB of the node n112are set to a logic “high” level may be performed.

In the present disclosure, it is described as an example that the sensing signal SEN and the latch signal LATS are implemented as separate signals, but according to other embodiments, the sensing signal SEN and the latch signal LATS may be implemented as the same signal. The NAND gates115_1and115_2included in the sense amplifying circuit110may be implemented to operate by receiving the sensing signal SEN instead of the latch signal LATS.

FIG.13is a block diagram illustrating a configuration of an integrated circuit2according to another embodiment of the present disclosure. As shown inFIG.13, the integrated circuit2may include an operation control circuit (OP CTR)21, and a signal line sense amplifying circuit (SLSA)23.

The operation control circuit21may include one or more processors and/or logic gates. The operation control circuit21may control the generation of a sharing signal SHAR, a pre-charge signal PCG, a sensing signal SEN, a latch signal LATS, and a calibration enable signals CEN<1:N>, based on a calibration operation signal CAL_OP and a sense amplifying operation signal SA_OP. The operation control circuit21may sequentially apply the pre-charge signal PCG, the sensing signal SEN, the latch signal LATS, and the calibration enable signals CEN<1:N> whose generation is controlled for a calibration operation to the signal line sense amplifying circuit23when the calibration operation signal CAL_OP is generated. The operation control circuit21may sequentially apply the pre-charge signal PCG, the sharing signal SHAR, the sensing signal SEN, and the latch signal LATS whose generation is controlled for a sense amplifying operation to the signal line sense amplifying circuit23when the calibration operation signal CAL_OP is generated.

The signal line sense amplifying circuit23may be connected to the operation control circuit21to receive the sharing signal SHARE, the pre-charge signal PCG, the sensing signal SEN, the latch signal LATS, and the calibration enable signals CEN<1:N>. The signal line sense amplifying circuit23may receive a reset signal RSTB, the pre-charge signal PCG, the sensing signal SEN, the latch signal LATS, and the calibration enable signals CEN<1:N> to perform a calibration operation. The signal line sense amplifying circuit23may be initialized by the reset signal RSTB in the calibration operation. The signal line sense amplifying circuit23may perform a pre-charge operation of setting the logic levels of the input data (DIN inFIG.14) and the inverted input data (DINB inFIG.14) to be the same as each other by the pre-charge signal PCG in the calibration operation. The signal line sense amplifying circuit23may sense and amplify the input data (DIN inFIG.14) and the inverted input data (DINB inFIG.14) by the sensing signal SEN in the calibration operation. The signal line sense amplifying circuit23may output the output data (DOUT inFIG.14) and the inverted output data (DOUTB inFIG.14) by the latch signal LATS through the second signal line (SL2inFIG.14) and the second inverted signal line (SL2B inFIG.14) in the calibration operation.

The signal line sense amplifying circuit23may generate a first calibration signal CAL1<1:N> and a second calibration signal CAL2<1:N> by the output data (DOUT inFIG.14) and the inverted output data (DOUTB inFIG.14) by the calibration enable signals CEN<1:N> in the calibration operation. The signal line sense amplifying circuit23may calibrate the driving strength of the MOS transistors (213_1and213_2inFIG.14) by the first calibration signal CAL1<1:N> and the second calibration signal CAL2<1:N>. The signal line sense amplifying circuit23may include MOS transistors (225_1<1:N> inFIG.14) that operate as calibration devices to calibrate the driving strength of the MOS transistor (213_1inFIG.14) for each bit included in the first calibration signal CAL1<1:N>. The signal line sense amplifying circuit23may include MOS transistors (225_3<1:N> inFIG.14) that operate as calibration devices to calibrate the driving strength of the MOS transistor (213_2inFIG.14) for each bit included in the second calibration signal CAL2<1:N>. At least one of the MOS transistors (225_1<1:N> inFIG.14) or at least one of the MOS transistors (225_3<1:N> inFIG.14) may be turned on by the calibration operation.

The signal line sense amplifying circuit23may receive the pre-charge signal PCG, the sharing signal SHAR, the sensing signal SEN, and the latch signal LATS to perform a sense amplifying operation in the sensing amplifying operation performed after the calibration operation. The signal line sense amplifying circuit23may stop the pre-charge operation by the pre-charge signal PCG in the sense amplifying operation performed after the calibration operation. The signal line sense amplifying circuit23may enable the first signal line (SL1inFIG.14) and the first inverted signal line (SL1B inFIG.14) to share signals with the input nodes (n211and n212inFIG.14) by the sharing signal SHAR in the sense amplifying operation performed after the calibration operation. The signal line sense amplifying circuit23may output the output data (DOUT inFIG.2) and the inverted output data (DOUTB inFIG.2) by the latch signal LATS through the second signal line (SL2inFIG.14) and the second inverted signal line (SL2B inFIG.14) in the sense amplifying operation performed after the calibration operation.

FIG.14is a circuit diagram of a signal line sense amplifying circuit23A according to another embodiment of the present disclosure. As shown inFIG.14, the signal line sense amplifying circuit23A may include a sense amplifying circuit210and a calibration circuit220.

The sense amplifying circuit210may include PMOS transistors211_1,211_2,211_3,211_4, and211_5; NMOS transistors213_1,213_2, and213_3; NAND gates215_1and215_2; and switching deices217_1and217_2. The PMOS transistor211_1may be turned on when a pre-charge signal PCG is generated at a logic “low” level for a pre-charge operation to drive input data DIN to a logic “high” level. The PMOS transistor211_2may be turned on when the pre-charge signal PCG is generated at a logic “low” level for the pre-charge operation to drive inverted input data DINB to a logic “high” level. The PMOS transistor211_3may be turned on when the pre-charge signal PCG is generated at a logic “low” level for the pre-charge operation to set the voltage level of the input data DIN to be the same as the voltage level of the inverted input data DINB. The PMOS transistors211_1,211_2, and211_3may be turned off by the pre-charge signal PCG generated at a logic “high” level in a calibration operation and a sense amplifying operation. The PMOS transistor211_4may be turned on by the inverted input data DINB of a node n212when a sensing signal SEN is generated at a logic “high” level to drive the input data DIN of a node n211to a logic “high” level in the calibration operation and the sense amplifying operation. The nodes n211and n212may be set as input nodes. The PMOS transistor211_5may be turned on by the input data DIN of the node n211when the sensing signal SEN is generated at a logic “high” level to drive the inverted input data DIN of the node n212to a logic “high” level in the calibration operation and the sense amplifying operation. The NMOS transistor213_1may be connected between the node n211and a node n213and may be turned on by the inverted input data DINB of the node n212when the sensing signal SEN is generated at a logic “high” level to drive the input data DIN of the node n211to a logic “low” level in the calibration operation and the sense amplifying operation. The NMOS transistor213_2may be connected between the node n212and the node n213and may be turned on by the input data DIN of the node n211when the sensing signal SEN is generated at a logic “high” level to drive the inverted input data DINB of the node n212to a logic “low” level in the calibration operation and the sense amplifying operation. The NMOS transistor213_3may be turned on when the sensing signal SEN is generated at a logic “high” level to drive the node n213to a logic “low” level in the calibration operation and the sense amplifying operation. The NAND gate215_1may receive the latch signal LATS and the input data DIN to perform a logical NAND operation. The NAND gate215_1may inversely buffer the input data DIN when the latch signal LATS is generated at a logic “high” level to output the inversely buffered signal of the input data DIN as the inverted output data DOUTB of a node n214in the calibration operation and the sense amplifying operation. The inverted output data DOUTB may be output through the second inverted signal line SL2B. The NAND gate215_2may receive the latch signal LATS and the inverted input data DINB to perform a logical NAND operation. The NAND gate215_2may inversely buffer the inverted input data DINB to output the inversely buffered signal of the inverted input signal DINB as the output data DOUT of a node n215in the calibration operation and the sense amplifying operation. The output data DOUT may be output through the second signal line SL2. The switching device217_1may be turned on when the sharing signal SHAR is generated at a logic “high” level to connect the first signal line SL1and the node n211so that the first signal line SL1and the node n211share the input data DIN of the node n211with each other in the sense amplifying operation. The switching device217_2may be turned on when the sharing signal SHAR is generated at a logic “high” level to connect the first inverted signal line SL1B and the node n212so that the first inverted signal line SL1B and the node n212share the inverted input data DINB of the node n212with each other in the sense amplifying operation. A voltage difference may occur between the input data DIN shared to the first signal line SL1and the inverted input data DINB shared to the first inverted signal line SL1B.

The calibration circuit220may include PMOS transistors221_1and221_2; NMOS transistors222_1<1:N>,222_2<1:N>,225_1<1:N>,225_2,225_3<1:N>,225_4,227_1<1:N>, and227_2<1:N>; and inverters223_1,223_2<1:N>,223_3, and223_4<1:N>. The PMOS transistor221_1may be turned on when a reset signal RST is generated at a logic “low” level for initialization to initialize the node n221to a logic “high” level. The PMOS transistor221_2may be turned on when the reset signal RST is generated at a logic “low” level for initialization to initialize a node n223to a logic “high” level. Each of the NMOS transistors222_1<1:N> may be connected between a node n214and a node n221, and may be turned on when each of the calibration enable signals CEN<1:N> is generated at a logic “high” level for the calibration operation to set the logic level of the node n221according to the inverted output signal DOUTB of the node n214. Each of the NMOS transistors222_2<1:N> may be connected between a node n215and the node n223, and may be turned on when each of the calibration enable signals CEN<1:N> is generated at a logic “high” level for the calibration operation to set the logic level of the node n223according to the output signal DOUT of the node n215. The inverter223_1may inversely buffer the signal of the node n221to output the inversely buffered signal of the node n221as the first calibration signal CAL1<1:N> of the node n222. Each of the inverters223_2<1:N> may inversely buffer the first calibration signal CAL1<1:N> of the node n222when each of the calibration enable signals CEN<1:N> is generated at a logic “low” level because the calibration operation is not performed to output the inversely buffered first calibration signal CAL1<1:N> of the node n222to the node n221. The inverter223_3may inversely buffer the signal of the node n223to output the inversely buffered signal of the node n223as the second calibration signal CAL2<1:N> of the node n224. Each of the inverters223_4<1:N> may inversely buffer the second calibration signal CAL2<1:N> of the node n224when each of the calibration enable signals CEN<1:N> is generated at a logic “low” level because the calibration operation is not performed to output the inversely buffered second calibration signal CAL2<1:N> of the node n224to the node n223. The logic levels of the first calibration signal CAL1<1:N> and the second calibration signal CAL2<1:N> may be determined by the driving strength of the NMOS transistor213_1and the driving strength of the NMOS transistor213_2, respectively. The NMOS transistors225<1:N> and225_2may be connected in series between the node n211and the node n213. Each of the NMOS transistors225<1:N> may be turned on when the first calibration signal CAL1<1:N> is generated at a logic “high” level because the driving strength of the NMOS transistor213_1is set to be weaker than the driving strength of the NMOS transistor213_2to operate as a calibration device that calibrates the driving strength of the NMOS transistor213_1. The NMOS transistor225_2may be turned on when the inverted input signal DINB of the node n212is at a logic “high” level. The NMOS transistors225_3<1:N> and225_4may be connected in series between the node n212and the node n213. Each of the NMOS transistors225_3<1:N> may be turned on when the second calibration signal CAL2<1:N> is generated at a logic “high” level because the driving strength of the NMOS transistor213_2is set to be weaker than the driving strength of the NMOS transistor213_1to operate as a calibration device that calibrates the driving strength of the NMOS transistor213_2. The NMOS transistor225_4may be turned on when the input signal DIN of the node n211is at a logic “high” level. The NMOS transistor227_1<1:N> may be connected between the node n211and a floating node, and may be turned on by the second calibration signal CAL2<1:N>. The NMOS transistor227_2<1:N> may be connected between the node n212and the floating node, and may be turned on by the first calibration signal CAL1<1:N>. Each of the NMOS transistor227_1<1:N> and the NMOS transistor227_2<1:N> may operate as a compensating device that compensates for a capacitance difference between the input nodes n211and n212after the calibration operation is performed. The NMOS transistors227_1<1:N> and227_2<1:N> might not be used according to embodiments.

The signal line sense amplifying circuit23A may perform a calibration operation of setting the logic level of each of the first calibration signal CAL1and the second calibration signal CAL2according to the driving strength of the NMOS transistor213_1and the driving strength of the NMOS transistor213_2, respectively, and may perform a sense amplifying operation of sensing and amplifying the signals of the first signal line SL1and the first inverted signal line SL1B and outputting the sensed and amplified signals of the first signal line SL1and the first inverted signal line SL1B to the second signal line SL2and the second inverted signal line SL2B in a state in which the driving strength of the NMOS transistor213_1and the driving strength of the NMOS transistor213_2are calibrated.

FIG.15is a timing diagram illustrating a calibration operation of the signal line sense amplifying circuit23A according to another embodiment of the present disclosure. The calibration operation of the signal line sense amplifying circuit23A will be described assuming that the driving strength of the NMOS transistor213_1is weaker than that of the NMOS transistor213_2.

First, because the NMOS transistors221_1and221_2are turned on when a reset signal RSTB is generated at a logic “low” level (“L”) for initialization in a section before a time point T211, the nodes n221and n223may all be initialized to a logic “high” level (“H”), and the first calibration signal CAL1<1:N> of the node n222and the second calibration signal CAL2of the node n224<1:N>) may all be initialized to a logic “low” level (“L”).

In addition, because the pre-charge signal PCG is generated at a logic “low” level (“L”) for a pre-charge operation during a section before a time point T211, the PMOS transistors211_1,211_2, and211_3may all be turned on, so that the input data DIN of the node n211and the inverted input data DINB of the node n212may all be set to a logic “high” level.

Next, because the pre-charge signal PCG transitions from a logic “low” level (“L”) to a logic “high” level (“H”) at the time point T211, the PMOS transistors211_1,211_2, and211_3may all be turned off.

Next, because the sensing signal SEN is generated at a logic “high” level (“H”) from a time point T212, the input data DIN of the node n211and the inverted input data DINB of the node n212may be sensed and amplified by the PMOS transistors211_4and211_5and the NMOS transistors213_1and213_2. Because the driving strength of the NMOS transistor213_1is weaker than the driving strength of the NMOS transistor213_2, the input data DIN of the node n211may maintain a logic “high” level (“H”) by the sense amplifying operation by the PMOS transistors211_4and211_5and the NMOS transistors213_1and213_2, and the inverted input data DINB of the node n212may transition from a logic “high” level (“H”) to a logic “low” level (“L”).

Next, because the latch signal LATS is generated at a logic “high” level (“H”) from a time point T213, the inverted output data DOUTB may be generated at a logic “low” level (“L”) by the input data DIN of a logic “high” level (“H”), and the output data DOUT may be generated at a logic “high” level (“H”) by the inverted input data DINB of a logic “low” level “L”.

Next, because the first bit CEN<1> of the calibration enable signal is generated at a logic “high” level (“H”) from a time point T214, the first bit CAL1<1> of the first calibration signal may be generated at a logic “high” level (“H”) by the inverted output data DOUTB of a logic “low” level (“L”), and the first bit CAL2<1> of the second calibration signal may be generated at a logic “low” level (“L”) by the output data DOUT of a logic “high” level (“H”). When the NMOS transistor225_1<1> is turned on by the first bit CAL<1> of the first calibration signal of a logic “high” level, the NMOS transistors225_1<1> and225_2may drive the input data DIN of the node n211, together with the NMOS transistor213_1. Accordingly, the driving strength of the NMOS transistor213_1may be calibrated by the NMOS transistors225_1<1> and225_2.

Next, at a time point T215, because the pre-charge signal PCG transitions from a logic “high” level (“H”) to a logic “low” level (“L”) and the PMOS transistors211_1,211_2, and211_3are all turned on, a pre-charge operation of setting the logic level of each of the input data DIN of the node n211and the inverted input data DINB of the node212to a logic “high” level (“H”).

Next, because the pre-charge signal PCG is generated at a logic “low” level (“L”) for the pre-charge operation during a section before the time point T221, the PMOS transistors211_1,211_2, and211_3may all be turned on, and the input data DIN of the node n211and the inverted input data DINB of the node n212may all be set to a logic “high” level.

Next, because the pre-charge signal PCG transitions from a logic “low” level (“L”) to a logic “high” level (“H”) at the time point T221, all of the PMOS transistors211_1,211_2, and211_3may be turned off.

Next, because the sensing signal SEN is generated at a logic “high” level (“H”) from a time point T222, the input data DIN of the node n211and the inverted input data DINB of the node n212may be sensed and amplified by the PMOS transistors211_4and211_5and the NMOS transistors213_1and213_2. Because the driving strength of the NMOS transistor213_1is weaker than the driving strength of the NMOS transistor213_2, the input data DIN of the node n211may maintain a logic “high” level (“H”) and the inverted input data DINB of the node n212may transition from a logic “high” level (“H”) to a logic “low” level (“L”) by the sense amplifying operation by the PMOS transistors211_4and211_5and the NMOS transistors213_1and213_2.

Next, because the latch signal LATS is generated at a logic “high” level (“H”) from a time point T223, the inverted output data DOUTB may be generated at a logic “low” level (“L”) by the input data DIN of a logic “high” level (“H”), and the output data DOUT may be generated at a logic “high” level (“H”) by the inverted input data DINB of a logic “low” level (“L”).

Next, because the second bit CEN<2> of the calibration enable signal is generated at a logic “high” level (“H”) from a time point T224, the second bit CAL1<2> of the first calibration signal may be generated at a logic “high” level (“H”) by the inverted output data DOUTB of a logic “low” level (“L”), and the second bit CAL2<2> of the second calibration signal may be generated at a logic “low” level (“L”) by the output data DOUT of a logic “high” level (“H”). When the NMOS transistor225_1<2> is turned on by the second bit CAL1<2> of the first calibration signal of a logic “high” level (“H”), the NMOS transistors225_1<2> and225_2may drive the input data DIN of the node n211, together with the NMOS transistor213_1. Accordingly, the driving strength of the NMOS transistor213_1may be calibrated by the NMOS transistors225_1<2> and225_2.

Next, at a time point T225, because the pre-charge signal PCG transitions from a logic high level (“H”) to a logic “low” level (“L”) and all of the PMOS transistors211_1,211_2, and211_3are turned on, a pre-charge operation in which both the input data DIN of the node n211and the inverted input data DINB of the node n212are set to a logic high level (“H”) may be performed.

Next, because the pre-charge signal PCG is generated at a logic “low” level (“L”) for a pre-charge operation during a section before a time point T231, the PMOS transistors211_1,211_2, and211_3may all be turned on, so that the input data DIN of the node n211and the inverted input data DINB of the node n212may all be set to a logic “high” level.

Next, because the pre-charge signal PCG transitions from a logic “low” level (“L”) to a logic “high” level (“H”) at the time point T231, the PMOS transistors211_1,211_2, and211_3may all be turned off.

Next, because the sensing signal SEN is generated at a logic “high” level (“H”) from a time point T232, the input data DIN of the node n211and the inverted input data DINB of the node n212may be sensed and amplified by the PMOS transistors211_4and211_5and the NMOS transistors213_1and213_2. Because the driving strength of the NMOS transistor213_1is weaker than the driving strength of the NMOS transistor213_2, the input data DIN of the node n211may maintain a logic “high” level (“H”), and the inverted input data DINB of the node n212may transition from a logic “high” level (“H”) to a logic “low” level (“L”) by the sense amplifying operation by the PMOS transistors211_4and211_5and the NMOS transistors213_1and213_2.

Next, because the latch signal LATCH is generated at a logic “high” level from a time point T233, the inverted output data DOUTB may be generated at a logic “low” level (“L”) by the input data DIN of a logic “high” level (“H”), and the output data DOUT may be generated at a logic “high” level (“H”) by the inverted input data DINB of a logic “low” level (“L”).

Next, because the Nth bit CEN<N> of the calibration enable signal is generated at a logic “high” level (“H”) from a time point T234, the Nthbit CAL1<N> of the first calibration signal may be generated at a logic “high” level (“H”) by the inverted output data DOUTB of a logic “low” level (“L”), and the Nth bit CAL2<N> of the second calibration signal may be generated at a logic “low” level (“L”) by the output data DOUT of a logic “high” level (“H”). When the NMOS transistor225_1<N> is turned on by the Nth bit CAL1<N> of the first calibration signal of a logic “high” level (“H”), the NMOS transistors225_1<N> and225_2may drive the input data DIN of the node n211, together with the NMOS transistor213_1. Accordingly, the driving strength of the NMOS transistor213_1may be calibrated by the NMOS transistors225_1<N> and225_2.

Finally, at a time point T235, because the pre-charge signal PCG transitions from a logic “high” level (“H”) to a logic “low” level (“L”) and all of the PMOS transistors211_1,211_2, and211_3are turned on, a pre-charge operation in which all of the input data DIN of the node n211and the inverted input data DINB of the node n212are set to a logic “high” level (“H”) may be performed.

As described above, the signal line sense amplifying circuit23A may include the NMOS transistors225_1<1:N> and225_3<1> that operate as calibration devices capable of calibrating the driving strength of the NMOS transistors213_1and213_2<1:N>, and may perform a calibration operation of determining whether to turn on each of the NMOS transistors225_1<1:N> and225_3<1:N> for each bit included in the calibration enable signal CEN<1:N>. When at least one of the NMOS transistors225_1<1:N> and225_3<1:N> is turned on, the driving strength of the NMOS transistors213_1and213_2may be calibrated.

In the present embodiment, the sensing signal SEN and the latch signal LATS are implemented as separate signals, but the sensing signal SEN and the latch signal LATS may be implemented as the same signal in other embodiments. The NAND gates215_1and215_2included in the sense amplifying circuit210may be implemented to operate by receiving the sensing signal SEN instead of the latch signal LATS.

FIG.16is a circuit diagram of a signal line sense amplifying circuit23B according to yet another embodiment of the present disclosure. As shown inFIG.16, the signal line sense amplifying circuit23B may include a sense amplifying circuit310and a calibration circuit320.

The sense amplifying circuit310may include PMOS transistors311_1,311_2,311_3,311_4, and311_5; NMOS transistors313_1,313_2, and313_3; NAND gates315_1and315_2; and switching devices317_1and317_2. The PMOS transistor311_1may be turned on when a pre-charge signal PCG is generated at a logic “low” level for a pre-charge operation to drive input data DIN to a logic “high” level. The PMOS transistor311_2may be turned on when the pre-charge signal PCG is generated at a logic “low” level for a pre-charge operation to drive inverted input data DINB to a logic “high” level. The PMOS transistor311_3may be turned on when the pre-charge signal PCG is generated at a logic “low” level for a pre-charge operation to set the voltage level of the input data DIN to be the same as the voltage level of the inverted input data DINB. The PMOS transistors311_1,311_2, and311_3may be turned off by the pre-charge signal PCG generated at a logic “high” level in a calibration operation and a sense amplifying operation. The PMOS transistor311_4may be turned on by the inverted input data DINB when a sensing signal SEN is generated at a logic “high” level in the calibration operation and the sense amplifying operation to drive the input data DIN of the node n311to a logic “high” level. The nodes n311and n312may be set as input nodes. The PMOS transistor311_5may be turned on by the input data DIN of the node n311when the sensing signal SEN is generated at a logic “high” level in the calibration operation and the sense amplifying operation to drive the inverted input data DINB of the node n312to a logic “high” level. The NMOS transistor313_1may be connected between the node n311and a node n313and may be turned on by the inverted input data DINB of the node n312when the sensing signal SEN is generated at a logic “high” level to drive the input data DIN of the node n311to a logic “low” level in the calibration operation and the sense amplifying operation. The NMOS transistor313_2may be connected between the node n312and the node n313and may be turned on by the input data DIN of the node n311when the sensing signal SEN is generated at a logic “high” level to drive the inverted input data DINB of the node n312to a logic “low” level in the calibration operation and the sense amplifying operation. The NMOS transistor313_3may be turned on when the sensing signal SEN is generated at a logic “high” level to drive the node n313to a logic “low” level in the calibration operation and the sense amplifying operation. The NAND gate315_1may receive the latch signal LATS and the input data DIN to perform a logical NAND operation. The NAND gate315_1may inversely buffer the input data DIN to output the inversely buffered signal of the input data DIN as the inverted output data DOUTB of the node n314in the calibration operation and the sense amplifying operation. The inverted output data DOUTB may be output through the second inverted signal line SL2B. The NAND gate315_2may receive the latch signal LATS and the inverted input data DINB to perform a logical NAND operation. The NAND gate315_2may inversely buffer the inverted input data DINB to output the inversely buffered signal of the inverted input data DINB as the output data DOUT of the node n315when the latch signal LATS is generated at a logic “high” level in the calibration operation and the sense amplifying operation. The output data DOUT may be output through the second signal line SL2. The switching device317_1may be turned on when the sharing signal SHAR is generated at a logic “high” level to connect the first signal line SL1and the node n311to each other so that the first signal line SL1and the node n311share the input data DIN of the node n311with each other. The switching device317_2may be turned on when the sharing signal SHAR is generated at a logic “high” level to connect the first inverted signal line SL1B and the node n312so that the first inverted signal line SL1B and the node n312share the inverted input data DINB of the node n312with each other. There may be generated a voltage difference between the input data DIN shared by the first signal line SL1and the inverted input data DINB shared by the first inverted signal line SL1B.

The calibration circuit320may include PMOS transistors321_1and321_2; OR gates324_1and324_2; NMOS transistors322_1,322_2,325_1<1:N>,325_2,325_3<1:N>,325_4,327_1<1:N>, and327_2<1:N>; and inverters323_1,323_2<1:N>,323_3, and323_4<1:N>. The PMOS transistor321_1may be turned on when a reset signal RSTB is generated at a logic “low” level for initialization to initialize a node n321. The PMOS transistor321_2may be turned on when the reset signal RSTB is generated at a logic “low” level for initialization to initialize a node n323. Each of the OR gates324_1and324_2may receive the calibration enable signals CEN<1:N> to perform a logical OR operation. Each of the OR gates324_1and324_2may output a signal of a logic “high” level when one bit of the calibration enable signals CEN<1:N> is at a logic “high” level. The NMOS transistor322_1may be connected between the node n314and the node n321, and may be turned on when the output of the OR gate324_1is generated at a logic “high” level for a calibration operation to set the logic level of the node n321according to the inverted output signal DOUTB of the node n314. The NMOS transistor322_2may be connected between the node n315and the node n323, and may be turned on when the output of the OR gate324_2is generated at a logic “high” level for the calibration operation to set the logic level of the node n323according to the output signal DOUT of the node n315. The inverter323_1may inversely buffer the signal of the node n321to output the inversely buffered signal of the node n321as a first calibration signal CAL1<1:N> of the node n322. Each of the inverters323_2<1:N> may inversely buffer the first calibration signal CAL1<1:N> of the node n322to output the inversely buffered signal of the first calibration signal CAL1<1:N> to the node n321when each of the calibration enable signals CEN<1:N> is generated at a logic “low” level because the calibration operation is not performed. The inverter323_3may inversely buffer the signal of the node n323to output the inversely buffered signal of the node n323as a second calibration signal CAL2<1:N> of the node n324. Each of the inverters323_4<1:N> to the node n323when the calibration operation is not performed and each of the calibration enable signals CEN<1:N> is generated at a logic “low” level. The logic levels of the first calibration signal CAL1<1:N> and the second calibration signal CAL2<1:N> may be determined by the driving strength of the NMOS transistor313_1and the driving strength of the NMOS transistor313_2, respectively. The NMOS transistors325_1<1:N> and325_2may be connected in series between the node n311and the node n313. Each of the NMOS transistors325_1<1:N> may be turned on when the driving strength of the NMOS transistor313_1is set to be weaker than the driving strength of the NMOS transistor313_2so that the first calibration signal CAL1<1:N> is generated at a logic “high” level, to operate as a calibration device that calibrates the driving strength of the NMOS transistor313_1. The NMOS transistor325_2may be turned on when the inverted input signal SINB of the node n312is at a logic “high” level. The NMOS transistors325_3<1:N> and325_4may be connected in series between the node n312and the node313. Each of the NMOS transistors325_3<1:N> may be turned on when the driving strength of the NMOS transistor313_2is set to be weaker than that of the NMOS transistor313_1so that the second calibration signal CAL2<1:N> is generated at a logic “high” level, to operate as a calibration device that calibrates the driving strength of the NMOS transistor313_2. The NMOS transistor325_4may be turned on when the input signal DIN of the node n311is at a logic “high” level. The NMOS transistor327_1<1:N> may be connected between the node n311and a floating node and may be turned on by the second calibration signal CAL2<1:N>. The NMOS transistor327_2<1:N> may be connected between the node n312and the floating node and may be turned on by the first calibration signal CAL1<1:N>. Each of the NMOS transistor327_1<1:N> and the NMOS transistor327_2<1:N> may operate as a compensating device that compensates for the capacitance difference between the input nodes n311and n312after the calibration operation is performed. The NMOS transistors327_1<1:N> and327_2<1:N> might not be used according to embodiments.

The signal line sense amplifying circuit23B may include NMOS transistors325_1<1:N> and325_3<1:N> that operate as calibration devices capable of calibrating the driving strength of the NMOS transistors313_1and313_2, and may perform a calibration operation of determining whether to turn on each of the NMOS transistors325_1<1:N> and325_3<1:N> for each bit included in the calibration enable signals CEN<1:N>. When at least one of the NMOS transistors325_1<1:N> and325_3<1:N> is turned on, the driving strength of the NMOS transistors313_1and313_2may be calibrated.

In the present embodiments, the sensing signal SEN and the latch signal LATS are implemented as separate signals, but the sensing signal SEN and the latch signal LATS may be implemented as the same signal in other embodiments. The NAND gates315_1and315_2included in the sense amplifying circuit310may be implemented to operate by receiving the sensing signal SEN instead of the latch signal LATS.

Concepts have been disclosed in conjunction with some embodiments as described above. Those skilled in the art will appreciate that various modifications, additions, and/or substitutions are possible, without departing from the scope and spirit of the present disclosure. Accordingly, the embodiments disclosed in the present specification should be considered from not a restrictive standpoint but rather from an illustrative standpoint. The scope of the concepts is not limited to the above descriptions but defined by the accompanying claims, and all of distinctive features in the equivalent scope should be construed as being included in the concepts.