Semiconductor element built-in wiring board and method for manufacturing the same

A wiring board includes a base substrate, a semiconductor element embedded in the substrate and having active and non-active surfaces such that the semiconductor has a terminal on the active surface, a first build-up layer including an insulating layer and first conductor pads such that the first conductor pads have exposed surfaces exposed from a surface of the insulating layer on the opposite side with respect to the substrate, and a second build-up layer including an insulating layer and second conductor pads such that the second conductor pads have exposed surfaces exposed from a surface of the insulating layer on the opposite side with respect to the substrate. The insulating layer in the first build-up includes resin material and reinforcing material, the insulating layer in the second build-up includes resin material and reinforcing material, and the first conductor pads is embedded in the insulating layer in the first build-up.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2015-024575, filed Feb. 10, 2015, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a semiconductor element built-in wiring board and a method for manufacturing the semiconductor element built-in wiring board.

Description of Background Art

Japanese Patent Laid-Open Publication No. 2001-345560 describes a semiconductor element built-in wiring board which includes a core substrate, a capacitor that is embedded inside the core substrate, an upper side build-up layer that is formed by laminating an insulating layer and a conductor layer on an upper side of the core substrate, and a lower side build-up layer that is formed by laminating an insulating layer and a conductor layer on a lower side of the core substrate. The core substrate is formed of a glass-epoxy resin composite material, and the insulating layers are formed of an epoxy resin. The entire contents of this publication are incorporated herein by reference.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a wiring board having a built-in semiconductor element includes a base substrate, a semiconductor element embedded in the base substrate and having an active surface and a non-active surface on the opposite side with respect to the active surface such that the semiconductor element has a terminal on the active surface, a first build-up layer including an insulating layer and first conductor pads such that the insulating layer is formed on a non-active surface side of the semiconductor element and that the first conductor pads have exposed surfaces exposed from a surface of the insulating layer on the opposite side with respect to the base substrate, and a second build-up layer including an insulating layer and second conductor pads such that the insulating layer is formed on an active surface side of the semiconductor element and that the second conductor pads have exposed surfaces exposed from a surface of the insulating layer on the opposite side with respect to the base substrate. The insulating layer in the first build-up layer includes a resin material and a reinforcing material, the insulating layer in the second build-up layer includes a resin material and a reinforcing material, and the first conductor pads is embedded in the insulating layer in the first build-up layer.

According to one aspect of the present invention, a method for manufacturing a wiring board having a built-in semiconductor element includes forming, on a support plate, a first build-up layer including an insulating layer and first conductor pads such that the first conductor pads are formed on the support plate and embedded in the insulating layer, forming a base substrate on the first build-up layer such that a semiconductor element is embedded in the base substrate and has a non-active surface side facing the first build-up layer, forming, on the base substrate, a second build-up layer including an insulating layer and second conductor pads such that the semiconductor element has a non-active surface facing the second build-up layer, and removing the support plate from the first build-up layer such that the first conductor pads have exposed surfaces exposed from a surface of the insulating layer on the opposite side with respect to the base substrate. The insulating layer in the first build-up layer includes a resin material and a reinforcing material in the resin material, and the insulating layer in the second build-up layer includes a resin material and a reinforcing material in the resin material.

DETAILED DESCRIPTION OF THE EMBODIMENTS

First Embodiment

As illustrated inFIG. 1, a semiconductor element built-in wiring board1according to the present embodiment includes: a base substrate20that is positioned at a central position; a semiconductor element10that is embedded inside the base substrate20; and a first build-up layer30and a second build-up layer40that are respectively formed on an upper side and a lower side in a manner sandwiching the base substrate20.

The base substrate20is a so-called coreless substrate that does not have a core substrate, and is formed by laminating multiple insulating layers and conductor layers. The base substrate20has a substantially flat plate-like shape, and has one main surface (20a) and another main surface (20b), the one main surface (20a) and the other main surface (20b) opposing each other. A conductor layer in the present embodiment is a wiring layer that forms an electrical circuit, and may include a conductor pad and a wiring pattern or the like or may include only a conductor pad, depending on a forming position of the conductor layer.

A conductor layer201and a plane layer207are provided on the one main surface (20a) side of the base substrate20. The conductor layer201and the plane layer207are formed side by side on an insulating layer300of the first build-up layer30(to be described later). The conductor layer201corresponds to a “first conductor layer” in the claims and is formed, for example, by an electroless plating layer and an electrolytic plating layer. The plane layer207, similar to the conductor layer201, is formed by an electroless plating layer and an electrolytic plating layer.

As illustrated inFIG. 1, a portion of the plane layer207, and the conductor layer201, are covered by an insulating layer200that is formed on the portion of the plane layer207and on the conductor layer201. The insulating layer200corresponds to a “third insulating layer” in the claims and is formed of a resin material that contains 30% or more by weight of an inorganic filler. In the present embodiment, the insulating layer200is formed of a resin insulating material that contains 30-80% by weight of an inorganic filler of SiO2.

A conductor layer203is formed on the insulating layer200. The conductor layer203corresponds to a “second conductor layer” in the claims and is formed, for example, by an electroless plating layer and an electrolytic plating layer. An insulating layer202is further laminated on the insulating layer200and the conductor layer203. The insulating layer202corresponds to a “fourth insulating layer” in the claims and is formed of a resin material that contains 30% or more by weight of an inorganic filler. On the insulating layer202, a conductor layer is not formed, and an insulating layer204is laminated.

As illustrated inFIG. 1, in the base substrate20, a recess206is provided that penetrates the insulating layer200and the insulating layer202, and uses a portion of the plane layer207as a bottom surface. The recess206is formed to have such a size that the semiconductor element10can be accommodated inside the recess206. Further, a side wall (206a) of the recess206is formed to expand upward so as to allow the semiconductor element10to be smoothly mounted inside the recess206.

The semiconductor element10has an active surface (10b) on which terminals11are formed, and has a non-active surface (10a) that is on an opposite side of the active surface (10b). The semiconductor element10is accommodated in the recess206such that the active surface (10b) of the semiconductor element10faces toward the other main surface (20b) side of the base substrate20. A die attach film12is provided on the non-active surface (10a) of the semiconductor element10.

In a lamination direction of the insulating layers (200,202), a height of the insulating layer202is lower than that of the semiconductor element10. In this way, for example, when the semiconductor element10is picked up and mounted in the recess206using a mounting device, interference between the mounting device and the insulating layer202can be prevented, and an effect is achieved that the mounting operation can be more smoothly performed. The semiconductor element10that is mounted in the recess206is temporarily fixed on the plane layer207via the die attach film12and is further embedded by the insulating layer204that is formed around and on the semiconductor element10.

The insulating layer204corresponds to a “fifth insulating layer” in the claims and, similar to the insulating layers (200,202), is formed of a resin material that contains 30% or more by weight of an inorganic filler. A conductor layer205is further formed on the insulating layer204. The plane layer205, similar to the conductor layers (201,203), is formed by an electroless plating layer and an electrolytic plating layer. Further, the conductor layer205is divided into a part that is formed in a region above the semiconductor element10and a part that is formed outside the region. As illustrated inFIG. 1, a portion of one of the two parts and a portion of the other part are connected. In this way, a wiring that is formed can be utilized not only for signal transmission but also, for example, as a power source wiring or a ground wiring.

Among the insulating layers (200,202,204) of the base substrate20, the insulating layer200is positioned on a lowermost side and the insulating layer204is positioned on an uppermost side. Therefore, a lower surface of the insulating layer200forms the one main surface (20a) of the base substrate20, and an upper surface of the insulating layer204forms the other main surface (20b) of the base substrate20. Further, lower surfaces of the conductor layer201and the plane layer207are positioned on the same plane as the one main surface (20a) of the base substrate20.

The insulating layer202is different from the insulating layers (200,204) in that a conductor layer is not formed on the insulating layer202. When the plane layer207is subjected to a desmear treatment, which is performed after the recess206is formed, the insulating layer202prevents an influence by the desmear treatment on the conductor layer203. The insulating layer202is provided as a protective layer that protects the conductor layer203. Further, among the insulating layers (200,202,204) of the base substrate20, the insulating layer202is the thinnest. In this way, reduction in a thickness of the base substrate20can be achieved.

Via conductors208that electrically connect the conductor layer201and the conductor layer203are formed inside the insulating layer200. Via conductors209that electrically connect the conductor layer203and the conductor layer205are formed inside the insulating layers (202,204). That is, the via conductors208are formed over one insulating layer, whereas the via conductors209are formed over two insulating layers.

Further, via conductors210that electrically connect the terminals11of the semiconductor element10and the conductor layer205are formed inside the insulating layer204that is positioned above on the semiconductor element10. The via conductors (208,209,210) have truncated cone shapes that increase in diameter toward the same direction. Specifically, all of the via conductors (208,209,210) are formed such that their diameters are enlarged along a direction from the one main surface (20a) toward the other main surface (20b).

The first build-up layer30includes the insulating layer300that is formed below the one main surface (20a) of the base substrate20on the non-active surface (10a) side of the semiconductor element10, and conductor pads301that are formed on the insulating layer300. The insulating layer300corresponds to a “first insulating layer” in the claims, and is formed of a resin material that contains a reinforcing material. Here, the reinforcing material is at least one selected from the group of a glass cloth, a carbon fiber, a glass nonwoven fabric, an aramid cloth and an aramid nonwoven fabric. In the present embodiment, the insulating layer300is formed of an ABF material that contains a glass cloth (product name: ABF-GX13GC, manufactured by Ajinomoto Fine-Techno Co., Ltd.).

The conductor pads301correspond to “first conductor pads” in the claims, and are formed, for example, by an electrolytic plating layer. The conductor pads301are embedded in the insulating layer300and are exposed to outside from a surface (300a) side of the insulating layer300on an opposite side of the base substrate20(that is, from a side distanced away from the one main surface (20a) of the base substrate20). Surfaces (301a) of the conductor pads301that are exposed to the outside are positioned on the same plane as the surface (300a) of the insulating layer300on the opposite side of the base substrate20. For example, when the semiconductor element built-in wiring board1is mounted on another printed wiring board including a motherboard or the like, the conductor pads301are electrically connected via solder bumps to connection pads of the other printed wiring board including a motherboard or the like. Further, via conductors302that electrically connect the conductor pads301and the conductor layer201(which is positioned on a lowermost side of the base substrate20) are formed inside the insulating layer300.

The second build-up layer40includes an insulating layer400that is formed on the other main surface (20b) of the base substrate20on the active surface (10b) side of the semiconductor element10, and conductor pads401that are formed on the insulating layer400. The insulating layer400corresponds to a “second insulating layer” in the claims and, similar to the insulating layer300, is formed of a resin material that contains a reinforcing material. In the present embodiment, the insulating layer400is formed of an ABF material that contains a glass cloth (product name: ABF-GX13GC, manufactured by Ajinomoto Fine-Techno Co., Ltd.).

The conductor pads401correspond to “second conductor pads” in the claims, and are formed, for example, by an electroless plating layer and an electrolytic plating layer. The conductor pads401are formed on the insulating layer400and are exposed to outside from a surface (400a) side of the insulating layer400on an opposite side of the base substrate20(that is, from a side distanced away from the other main surface (20b) of the base substrate20). For example, when an external electronic component such as a chip or a printed wiring board is mounted, the conductor pads401are electrically connected via solder bumps to connection terminals or the like of the external electronic component. Further, via conductors402that electrically connect the conductor pads401and the conductor layer205(which is positioned on an uppermost side of the base substrate20) are formed inside the insulating layer400.

The via conductors302of the first build-up layer30and the via conductors402of the second build-up layer40have truncated cone shapes that increase in diameter toward the same direction. Specifically, all of the via conductors (302,402) are formed such that their diameters are enlarged along a direction from the one main surface (20a) toward the other main surface (20b).

As illustrated inFIG. 1, among the via conductors (208,209) of the base substrate20, the via conductors302of the first build-up layer30and the via conductors402of the second build-up layer40, some are linearly stacked along the lamination direction and form stack via structures. As a result, the conductor pads301of the first build-up layer30are electrically connected to the conductor pads401of the second build-up layer40via the via conductors (302,208,209,402) and the conductor layers (201,203,205). Further, although not illustrated in the drawings, among the via conductors (208,209) of the base substrate20, the via conductors302of the first build-up layer30and the via conductors402of the second build-up layer40, some are stacked along the lamination direction with their positions shifted with respect to each other and form offset via structures.

A solder resist layer (first solder resist layer)303having openings (303a) that each expose a portion of a conductor pad301is formed on the surface (300a) of the insulating layer300on an opposite side of the base substrate20. Similarly, a solder resist layer (second solder resist layer)403having openings (403a) that each expose a portion of a conductor pad401is formed on the surface (400a) of the insulating layer400on an opposite side of the base substrate20. In this way, an effect is achieved that a surface of the semiconductor element built-in wiring board1can be protected, solder can be prevented from being attached to a portion where solder is not required during mounting, and mounting reliability can be improved. When desired, it is also possible that, on the surface (300a) of the insulating layer300on the opposite side of the base substrate20, for example, only a processing film such as an OSP (Organic Solderability Preservative) film is formed and the first solder resist layer303is not formed.

In the semiconductor element built-in wiring board1having the above-described structure, the insulating layer300and the insulating layer400are formed of a resin material that contains a reinforcing material and thus can enhance strength of the base substrate20that is sandwiched between the insulating layer300and the insulating layer400. As a result, occurrence of warpage due to a difference in thermal expansion coefficient between the materials can be prevented. Therefore, for example, based on a warpage occurrence prediction situation of the base substrate20, occurrence of warpage in the semiconductor element built-in wiring board1can be prevented by changing the kind of the resin material containing a reinforcing material that is used for the insulating layer300and the insulating layer400formed on both sides of the base substrate20, or by adjusting thicknesses of the insulating layer300and the insulating layer400. For example, when it is predicted that warpage of the base substrate20is larger on the other main surface (20b) than on the one main surface (20a) side, by using a material having a higher strength for the insulating layer400positioned on the other main surface (20b) side than that of the material used for the insulating layer300positioned on the one main surface (20a) side, occurrence of warpage can be reliably prevented.

Further, the first build-up layer30is formed on the non-active surface (10a) side of the semiconductor element10and the conductor pads301are embedded in the insulating layer300. Therefore, as compared to a case where the conductor pads are not embedded in the insulating layer, a distance between each of the conductor pads301and the semiconductor element10can be reduced. Therefore, an effect of releasing heat generated from the semiconductor element10to outside can be enhanced. Further, by embedding the conductor pads301in the insulating layer300, peeling of the conductor pads301can be suppressed.

Further, the surfaces (301a) of the conductor pads301that are exposed to the outside are positioned on the same plane as the surface (300a) of the insulating layer300on the opposite side of the base substrate20. Therefore, flatness of the surface (300a) can be maintained and, when the semiconductor element built-in wiring board1is mounted via the surface (300a) to another printed wiring board including a motherboard or the like, improvement in mountability can be achieved. In addition, the surfaces (301a) of the conductor pads301that are exposed to the outside are positioned on the same plane as the surface (300a). Therefore, by utilizing a self-alignment effect, occurrence of solder bridging during mounting can be prevented.

Further, among the via conductors (208,209) of the base substrate20, the via conductors302of the first build-up layer30and the via conductors402of the second build-up layer40, some are linearly stacked along the lamination direction and form stack via structures. Therefore, as compared to a case where offset via structures are adopted, reduction in a thickness of the semiconductor element built-in wiring board1can be easily achieved, and improvement in design flexibility of the semiconductor element built-in wiring board1can be achieved.

In the following, with reference toFIGS. 2 and 3, a semiconductor package of a POP (package on package) structure that uses the semiconductor element built-in wiring board1is described.

In a semiconductor package illustrated inFIG. 2, a printed wiring board2is mounted on the second build-up layer40side of the semiconductor element built-in wiring board1. Electrodes or terminals of the printed wiring board2are electrically connected via solder bumps52to the conductor pads401of the second build-up layer40. A chip3is further mounted on the printed wiring board2. Electrodes or terminals of the chip3are electrically connected via solder bumps53to electrodes or terminals of the printed wiring board2.

In a semiconductor package illustrated inFIG. 3, a chip4and a printed wiring board5are mounted on the second build-up layer40side of the semiconductor element built-in wiring board1. The chip4and the printed wiring board5are positioned to be stacked in an up-down direction (that is, the lamination direction of the insulating layers (200,202)). Terminals or electrodes of the chip4are electrically connected via solder bumps54to some of the conductor pads401of the second build-up layer40. The printed wiring board5is positioned above the chip4. Terminals or electrodes of the printed wiring board5are electrically connected via solder bumps55to some of the conductor pads401of the second build-up layer40.

A mold resin layer7is formed between the chip4and the printed wiring board5. The chip4is sealed inside the mold resin layer7. A chip6is further mounted on the printed wiring board5. Electrodes or terminals of the chip6are electrically connected via solder bumps56to electrodes or terminals of the printed wiring board5.

Second Embodiment

In the following, with reference toFIG. 4, a second embodiment of the present invention is described. A semiconductor element built-in wiring board8according to the present embodiment is different from the first embodiment in that surfaces (304a) of conductor pads304that exposed to outside are recessed relative to the surface (300a) of the insulating layer300on the opposite side of the base substrate20. Other structures are the same as the first embodiment.

The conductor pads304correspond to “first conductor pads” in the claims, and are formed, for example, by an electrolytic plating layer. The conductor pads304are embedded in the insulating layer300and are exposed to outside from the surface (300a) of the insulating layer300on the opposite side of the base substrate20. The surfaces (304a) of the conductor pads304that are exposed to the outside are recessed to an inner side of the semiconductor element built-in wiring board8relative to the surface (300a) of the insulating layer300on the opposite side of the base substrate20. Preferably, the surfaces (304a) are recessed 3-15 μm relative to the surface (300a) of the insulating layer300on the opposite side of the base substrate20. A solder resist layer is not formed on the surface (300a) of the insulating layer300on the opposite side of the base substrate20.

The following is an example of a method that allows the surfaces (304a) of the conductor pads304to be recessed to the inner side of the semiconductor element built-in wiring board8relative to the surface (300a) of the insulating layer300on the opposite side of the base substrate20. That is, the conductor pads304are first formed from electrolytic Cu/Ni/Cu plating layers. Thereafter, the Cu plating layer of the conductor pads304on the outermost side (side close to the surface (300a) of the insulating layer300on the opposite side of the base substrate20) is removed by an etching process. In this case, the Ni plating layer prevents erosion of the inner side Cu plating layer due to the etching process, and thus only the outer side Cu plating layer is removed. As a result, recesses occur.

In the semiconductor element built-in wiring board8according to the present embodiment, the same operation effect as in the first embodiment can be obtained. In addition, since the surfaces (304a) of the conductor pads304that are exposed to the outside are recessed relative to the surface (300a) of the insulating layer300on the opposite side of the base substrate20, during mounting, a solder bump can be reliably prevented from flowing to an adjacent conductor pad, and improvement in mountability can be achieved.

Third Embodiment

In the following, with reference toFIG. 5, a third embodiment of the present invention is described. A semiconductor element built-in wiring board9according the present embodiment is different from the first embodiment in that a via conductor305that electrically connects the plane layer207and a conductor pad301is provided. Other structures are the same as the first embodiment.

Specifically, inside the insulating layer300, in addition to the via conductors302that electrically connect the conductor pads301and the conductor layer201of the base substrate20, a via conductor305that electrically connects a conductor pad301and the plane layer207of the base substrate20is further formed. Similar to the via conductors302, the via conductor305has a truncated cone shape that increases in diameter in a direction from the one main surface (20a) toward the other main surface (20b). Depending in an area of the plane layer207and an area of a conductor pad301, one or more via conductors305may be provided.

In the semiconductor element built-in wiring board9according to the present embodiment, the same operation effect as in the first embodiment can be obtained. In addition, since the via conductor305that electrically connects the plane layer207and a conductor pad301is provided, via the via conductor305, heat generated from the semiconductor element10can be efficiently transmitted to the conductor pad301and released to the outside, and occurrence of a thermal stress can be suppressed. Further, by connecting to a ground layer via the via conductor305, noise can be reduced.

Method for Manufacturing Semiconductor Element Built-In Wiring Board

In the following, with reference toFIGS. 6A-10D, a method for manufacturing the semiconductor element built-in wiring board1is described. The method for manufacturing the semiconductor element built-in wiring board1according to the present embodiment includes a first process in which the first build-up layer30is formed on a support plate50, a second process in which the base substrate20is formed and the semiconductor element10is embedded inside the base substrate20, a third process in which the second build-up layer40is formed on the base substrate20, and a fourth process in which the support plate50is removed.

First Process

First, the support plate50is prepared (seeFIG. 6A). A copper-clad laminated plate is used for the support plate50. The copper-clad laminated plate is formed by an insulating layer (50a), a first copper foil (50b) that is laminated on both sides of the insulating layer (50a), and a second copper foil (50c) that is laminated on an outer side of the first copper foil (50b). The first copper foil (50b) has a thickness of 15-20 μm, and the second copper foil (50c) has a thickness of 3-5 μm. A release layer (not illustrated in the drawings) is formed between the first copper foil (50b) and the second copper foil (50c).

Next, the conductor pads301are formed on the second copper foil (50c) (seeFIG. 6B). Specifically, first, a photosensitive resist layer is applied on the second copper foil (50c). Thereafter, by performing exposure processing and development processing, a predetermined resist pattern is formed. Next, on the second copper foil (50c) where the resist pattern is not formed, the conductor pads301are formed by electrolytic plating. Next, the resist pattern is removed, and the insulating layer300is laminated on the second copper foil (50c) and on the conductor pads301(seeFIG. 6C). As a result, the conductor pads301are embedded in the insulating layer300. The ABF material that contains a glass cloth (product name: ABF-GX13GC, manufactured by Ajinomoto Fine-Techno Co., Ltd.) is used for the insulating layer300.

Second Process

Via holes306are formed by laser processing at predetermined positions in the insulating layer300(seeFIG. 7A). In this case, the via holes306are formed to each have a truncated cone shape that increases in diameter along a direction away from the support plate50. As a result, the formed via conductors increase in diameter in the direction away from the support plate50. Further, the via holes306are formed to have a depth such that the via holes306reach the surfaces of the conductor pads301.

An upper surface of the insulating layer300and inner walls and bottom surfaces of the via holes306are subjected to a desmear treatment. Thereafter, a seed layer (201a) is formed using an electroless plating method (seeFIG. 7B). Here, instead of the electroless plating method, it is also possible to use a sputtering method to form the seed layer. As a material of the seed layer (201a), for example, titanium, titanium nitride, chromium, copper, or the like, can be used.

A predetermined resist pattern51is formed on the seed layer (201a) (seeFIG. 7C). Specifically, a photosensitive resist layer is applied on the seed layer (201a). Thereafter, by performing exposure processing and development processing, a predetermined resist pattern51is formed. Next, a copper plating layer (201b) is formed on the seed layer (201a) where the resist pattern51is not formed (seeFIG. 7D). The copper plating layer (201b) may also be a layer that is formed by laminating an electroless plating layer or by laminating an electrolytic plating layer or by laminating an electroless plating layer and an electrolytic plating layer.

The predetermined resist pattern51that is formed on the seed layer (201a) is removed. Next, a portion of the seed layer (201a) that is exposed to the outside due to the removal of the resist pattern51is etched and removed. Of the seed layer (201a) and the copper plating layer (201b) that are remaining on the insulating layer300, a portion forms the plane layer207and the rest forms the conductor layer201. Therefore, the plane layer207and the conductor layer201are in a state of being formed side by side on the insulating layer300. Further, due to the formation of the copper plating layer (201b), copper is filled in the via holes306. The via conductors302are formed by the filled copper and the seed layer (201a) formed on the inner walls and bottom surfaces of the via holes306(seeFIG. 7E).

The insulating layer200is laminated on the insulating layer300and the conductor layer201(seeFIG. 7F). A resin material that contains, for example, 30% or more by weight of an inorganic filler is used for the insulating layer200. Next, via holes (200a) are formed by laser processing at predetermined positions in the insulating layer200(seeFIG. 8A). Next, using the above-described method, the conductor layer203is formed on the insulating layer200, and the via conductors208are formed inside the via holes (200a) (seeFIG. 8B).

The insulating layer202is laminated on the insulating layer200and the conductor layer203(seeFIG. 8C). In this case, taking into account of allowing the mounting operation of the semiconductor element10(to be described later) to be smoothly performed, the height of the insulating layer202is lower than the height of the semiconductor element10. Similar to the insulating layer200, a resin material that contains 30% or more by weight of an inorganic filler is used for the insulating layer202. In order to reduce the thickness of the base substrate20, the insulating layer202is formed thinner than all of the insulating layer200and the insulating layer204(to be described later).

Laser is irradiated to a predetermined position on the insulating layer202, and the recess206is formed that penetrates the insulating layer202and the insulating layer200positioned below the insulating layer202and exposes a portion of the upper surface of the plane layer207as a bottom surface (seeFIG. 8D). Here, a bottom surface area of the formed recess206is smaller than an area of the plane layer207. The entire bottom surface of the recess206is formed by only the plane layer207.

Of the plane layer207, the portion that is exposed as the bottom surface of the recess206is subjected to a desmear treatment. As a result, resin residues of the insulating layers (200,202) attached to the surface of the exposed portion of the plane layer207are removed. In the present embodiment, the insulating layer202is formed on the conductor layer203. Therefore, when the plane layer207is subjected to the desmear treatment, an influence by the desmear treatment on the conductor layer203can be prevented. That is, the insulating layer202functions as a protective layer that protects the conductor layer203.

The semiconductor element10, which is prepared in advance, is mounted in the recess206(seeFIG. 8E). For example, the semiconductor element10is picked up using a mounting device, and is mounted on the bottom surface of the recess206such that the non-active surface (10a) faces downward. As described above, the height of the insulating layer202is lower than the height of the semiconductor element10. Therefore, when the semiconductor element10is mounted in the recess206using a mounting device, interference between the mounting device and the insulating layer202can be prevented, and the mounting operation can be smoothly performed.

The die attach film12is provided on the non-active surface (10a) of the semiconductor element10. After the semiconductor element10is mounted, the die attach film12is heated and cured and thereby the semiconductor element10is temporarily fixed on the plane layer207(seeFIG. 8F).

The insulating layer204is laminated on the insulating layer202and the semiconductor element10(seeFIG. 9A). As a result, the semiconductor element10is sealed in the insulating layer204. Similar to the insulating layers (200,202), a resin material that contains 30% or more by weight of an inorganic filler is used for the insulating layer204. Next, by laser processing, via holes (204a) are formed at predetermined positions in the insulating layer202and the insulating layer204that cover the conductor layer203, and via holes (204b) are formed at predetermined positions in the insulating layer204that covers the semiconductor element10(seeFIG. 9B). The via holes (204a) penetrate the insulating layer204and the insulating layer202, and are formed to have a depth such that the via holes (204a) reach the surface of the conductor layer203. The via holes (204b) are formed to have a depth such that the via holes (204b) reach surfaces of the terminals11of the semiconductor element10.

Using the above-described method, the conductor layer205is formed on the insulating layer204; the via conductors209are formed inside the via holes (204a); and the via conductors210are formed inside the via holes (204b) (seeFIG. 9C). Next, the insulating layer400is laminated on the insulating layer204and the conductor layer205(seeFIG. 9D). Similar to the insulating layer300, the ABF material that contains a glass cloth (product name: ABF-GX13GC, manufactured by Ajinomoto Fine-Techno Co., Ltd.) is used for the insulating layer400.

Using the above-described method, the conductor pads401and the via conductors402are respectively formed on the insulating layer400(seeFIG. 9E). Different from the conductor pads301of the first build-up layer30, the conductor pads401are formed, for example, by a seed layer and an electrolytic copper plating layer. Next, the solder resist layer403is formed on the insulating layer400and the conductor pads401(seeFIG. 10A).

Third Process

The support plate50is removed. For example, by heating the support plate50, the release layer between the first copper foil (50b) and the second copper foil (50c) is softened, and the second copper foil (50c) and the first copper foil (50b) are peeled off from each other. In this case, the second copper foil (50c) remains on the insulating layer300side of the first build-up layer30(seeFIG. 10B). Next, the remaining second copper foil (50c) is etched and removed and thereby the conductor pads301of the first build-up layer30are exposed to the outside. Thereafter, by subjecting the solder resist layer403to exposure and development processing or to laser processing, the openings (403a) that each expose a portion of a conductor pad401to the outside are formed (seeFIG. 10C).

The solder resist layer303is formed below the insulating layer300and the conductor pads301. Thereafter, by subjecting the solder resist layer303to exposure and development processing or the like, the openings (303a) that each expose a portion of a conductor pad301to the outside are formed (seeFIG. 10D). As a result, the semiconductor element built-in wiring board1is completed.

In the above-described manufacturing method, the semiconductor element built-in wiring board1is manufactured by sequentially forming the first build-up layer30, the base substrate20and the second build-up layer40on one side of the support plate50. Therefore, the semiconductor element built-in wiring board1can be manufactured using a coreless manufacturing method in which a core substrate is not provided. Therefore, as compared to a semiconductor element built-in wiring board in which a core substrate is provided, flexibility in selecting laser used in the formation of the via holes and the recess and in selecting the materials used for the insulating layers can be improved. As a result, manufacturing cost of the semiconductor element built-in wiring board1can be reduced. Further, since a core substrate is not provided, reduction in the thickness of the semiconductor element built-in wiring board1can be achieved.

Modified Embodiment of Method for Manufacturing Semiconductor Element Built-In Wiring Board

In the following, with reference toFIGS. 11A-11D, a modified embodiment of the method for manufacturing the semiconductor element built-in wiring board1is described. In the present modified embodiment, a method for forming the recess is different from that described above, but the rest is the same as that described above.

First, following the above-described contents ofFIGS. 6A-7E, the plane layer207and the conductor layer201are formed on the insulating layer300. Next, a release layer57is formed on the plane layer207in a place where the recess206is to be formed (seeFIG. 11A). For example, a heat resistant masking material (for example, manufactured by Asahi Chemical Research Laboratory Co., Ltd., product name: #503B-SH), or a high heat resistant masking material (for example, manufactured by Asahi Chemical Research Laboratory Co., Ltd., product name: #801B-R), or the like, is used for the release layer57. The release layer57has a thickness of, for example, 1-20 μm.

Next, the insulating layer200is laminated on the insulating layer300, the conductor layer201, the plane layer207and the release layer57. Next, using the above-described method, the conductor layer203is formed on the insulating layer200, and the via conductors208are formed inside the insulating layer200. Thereafter, the insulating layer202is laminated on the insulating layer200and the conductor layer203(seeFIG. 11B). Next, laser is irradiated to the insulating layer202along a cutting line58for the formation of the recess (seeFIG. 11C), and a portion on the release layer57is removed to expose the release layer57. Next, the release layer57is removed, and the recess206is formed that exposes a portion of an upper surface of the plane layer207as a bottom surface (seeFIG. 11D). In this way, the same recess as that ofFIG. 8Dcan be obtained. Next, the plane layer207that is exposed as the bottom surface of the recess206is subjected to a desmear treatment and thereafter, following the above-described contents ofFIGS. 8E-10D, the semiconductor element built-in wiring board1is manufactured.

Fourth Embodiment

In the following, with reference toFIG. 12, a fourth embodiment of the present invention is described. A semiconductor element built-in wiring board13according to the present embodiment is different from the first embodiment in that a conductor layer211and a plane layer212that are formed side by side on the one main surface (20a) side, and conductor pads405of second build-up layer40, each have a three-layer structure including a copper foil, an electroless copper plating layer and an electrolytic copper plating layer. Other structures are the same as the first embodiment.

Specifically, the conductor layer211and the plane layer212each have a copper foil213, an electroless copper plating layer214and an electrolytic copper plating layer215in this order from the one main surface (20a) side. Further, an insulating layer307of the first build-up layer30and an insulating layer404of the second build-up layer40are each formed of a prepreg material containing a glass cloth. On the other hand, the conductor pads405of the second build-up layer40each have a copper foil406, an electroless copper plating layer407and an electrolytic copper plating layer408in this order from an upper surface (404a) side of the insulating layer404(the upper surface (404a) of the insulating layer404being a surface of the insulating layer404on the opposite side of the base substrate20). The semiconductor element built-in wiring board13according to the present embodiment can achieve the same operation effect as the first embodiment.

In the following, with reference toFIGS. 13A-13E, a method for manufacturing the semiconductor element built-in wiring board13is described. First, following the above-described contents ofFIGS. 6A and 6B, the conductor pads301are formed on the second copper foil (50c). Next, a prepreg material containing a glass cloth, on one side of which the copper foil213is laminated (seeFIG. 13A), is placed and laminated on the second copper foil (50c) and the conductor pads301(seeFIG. 13B). The prepreg material containing a glass cloth forms the insulating layer307of the first build-up layer30. The copper foil213has a thickness of, for example, about 3-5 μm.

The via holes306are formed by laser processing at predetermined positions in the copper foil213and the insulating layer307(seeFIG. 13C). Next, the inner walls and the bottom surfaces of the via holes306are subjected to a roughening treatment and thereafter the electroless copper plating layer214is formed on the upper surface of the copper foil213and on the inner walls and the bottom surfaces of the via holes306using an electroless plating method (seeFIG. 13D). Next, a predetermined resist pattern is formed on the electroless copper plating layer214, and the electrolytic copper plating layer215is formed on the electroless copper plating layer214where the resist pattern is not formed.

Thereafter, portions of the electroless copper plating layer214and the copper foil213that are exposed to the outside due to removal of the resist pattern are etched and removed. Of the copper foil213, the electroless copper plating layer214and the electrolytic copper plating layer215that are remaining on the insulating layer307, a portion forms the plane layer212and the rest forms the conductor layer211. Further, the electroless copper plating layer214and the electrolytic copper plating layer215that are filled inside the via holes306form the via conductors302(seeFIG. 13E). Next, following the above-described contents of theFIGS. 7F-10D, the semiconductor element built-in wiring board13is manufactured. When the second build-up layer40is formed, as illustrated inFIG. 13A, it is also possible to use the prepreg material containing a glass cloth, on one side of which a copper foil is laminated, to form the insulating layer404and the conductor pads405.

Fifth Embodiment

In the following, with reference toFIG. 14, a fifth embodiment of the present invention is described. A semiconductor element built-in wiring board14according to the present embodiment is different from the first embodiment in that the semiconductor element10is connected via conductor posts15to the conductor layer205of the base substrate20. Other structures are the same as the first embodiment.

Specifically, the conductor posts15are formed on the active surface (10b) of the semiconductor element10. The conductor posts15are formed of, for example, Cu, and function as terminals of the semiconductor element10. The via conductors210as in the first embodiment are not formed inside the insulating layer204that is positioned above the semiconductor element10. The semiconductor element10is directly electrically connected via the conductor posts15to the conductor layer205of the base substrate20(so-called landless connection).

In the semiconductor element built-in wiring board14according to the present embodiment, the same operation effect as the first embodiment can be obtained. In addition, since the semiconductor element10is directly connected via the conductor posts15to the conductor layer205, it is not required to form via openings and via conductors using laser in the insulating layer204positioned above the semiconductor element10, and fine connection between the conductor layer205and the semiconductor element10becomes possible.

In the following, with reference toFIGS. 15A-15D, a method for manufacturing the semiconductor element built-in wiring board14is described. First, following the above-described contents ofFIGS. 6A-8D, the recess206that penetrates the insulating layer202and the insulating layer200and exposes a portion of the upper surface of the plane layer207as a bottom surface is formed at a predetermined position in the insulating layer202, and the exposed portion of the plane layer207is subjected to a desmear treatment. Next, the semiconductor element10, which is prepared in advance and has the conductor posts15, is mounted in the recess206(seeFIG. 15A). After the semiconductor element10is mounted, the die attach film12is heated and cured and thereby the semiconductor element10is temporarily fixed on the plane layer207.

The insulating layer204is laminated on the insulating layer202and the semiconductor element10(seeFIG. 15B). As a result, the entire semiconductor element10is sealed inside the insulating layer204. Next, by polishing the surface of the insulating layer204, the conductor posts15of the semiconductor element10are exposed to the outside (seeFIG. 15C). Next, using the above-described method, the conductor layer205is formed on the insulating layer204and the conductor posts15, and the via conductors209are formed inside the insulating layer204(seeFIG. 15D). As a result, the conductor layer205formed above the semiconductor element10is directly electrically connected via the conductor posts15to the semiconductor element10. Next, following the above-described contents of theFIGS. 9D-10D, the semiconductor element built-in wiring board14is manufactured.

In the above, embodiments of the present invention are described in detail. However, the present invention is not limited to the above-described embodiments. Various design modifications can be performed within the scope without departing from the spirit of the present invention as described in appended claims. For example, in the above-described embodiments, the first build-up layer30and the second build-up layer40are described that are each formed by laminating one insulating layer and one conductor layer (conductor pads). However, these build-up layers may also have a structure that is formed by alternately laminating multiple insulating layers and wiring layers.

Further, in addition to the above-described resin material that contains 30% or more by weight of an inorganic filler, an ABF (Ajinomoto Build-up Film) resin manufactured by Ajinomoto Fine-Techno Co., Ltd., or a photosensitive resin, may also be used for the insulating layers (200,202,204) of the base substrate20. When a photosensitive resin is used for the insulating layers (200,202,204) of the base substrate20, small-diameter via holes (such as the via holes (204a,204b) ofFIG. 9B) can be formed even using an exposure and development method. Further, the same material is used for the insulating layer300and the insulating layer400. However, it is also possible to use different materials for the insulating layer300and the insulating layer400. Further, in order to achieve improvement in electrical characteristics and noise reduction, the plane layer may also be formed as a ground layer. Further, when desired, the plane layer may also be formed by a copper foil, an electroless copper plating layer and an electrolytic copper plating layer.

In a semiconductor element built-in wiring board, a thermal stress may occur due to a difference in thermal expansion coefficients of the materials and warpage of the wiring board caused by the thermal stress is likely to occur.

A semiconductor element built-in wiring board according to an embodiment of the present invention prevents occurrence of warpage.

A semiconductor element built-in wiring board according to an embodiment of the present invention includes: a base substrate; a semiconductor element that is embedded in the base substrate; and a first build-up layer and a second build-up layer that are respectively formed on both sides of the base substrate so as to sandwich the base substrate. The semiconductor element has an active surface and a non-active surface, the active surface having a terminal, and the non-active surface being on an opposite side of the active surface. The first build-up layer has a first insulating layer that is formed on the non-active surface side of the semiconductor element, and has first conductor pads that are exposed to outside from a surface of the first insulating layer on a site opposite to the base substrate. The second build-up layer has a second insulating layer that is formed on the active surface side of the semiconductor element, and has second conductor pads that are exposed to outside from a surface of the second insulating layer on a side opposite to the base substrate. The first insulating layer and the second insulating layer are formed of a resin material that contains a reinforcing material. The first conductor pads are embedded in the first insulating layer.

According to an embodiment of the present invention, occurrence of warpage can be prevented.