Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system

A signaling mechanism for sending and receiving signals to and from any one of all of a plurality of devices, including peripheral controllers and processors, in a multiprocessor system. The signaling mechanism includes two switches, a first switch routing a signal command generated by the device to a signal dispatch logic and a second switch for receiving signals generated by the signal dispatch logic and routing the signals to the selected device. The signal dispatch logic receiving the signal command, decodes the destination select value and generates a signal to be sent to the selected device. The signal command includes a destination select value representing a device selectably determined by the device. The signaling mechanism also includes an arbitration mechanism connected to the signal dispatch logic and the first switch for resolving simultaneous conflicting signal commands issued by two or more devices. The signal generated by the signal dispatch logic may include a plurality of bits representing one or more types of predefined signals to be acted upon by the device.

TECHNICAL FIELD 
This invention relates generally to the field of signaling and interrupt 
mechanisms for computer and electronic logic systems. More particularly, 
the present invention relates to a method and apparatus for a signaling 
mechanism for a multiprocessor system that allows any processor or 
external interface port to signal any other processor or external 
interface port in the multiprocessor system and can resolve simultaneous 
conflicting signals. 
BACKGROUND ART 
The parent application identified above describes a new cluster 
architecture for high-speed computer processing systems, referred to as 
supercomputers. For most supercomputer applications, the objective is to 
provide a computer processing system with the fastest processing speed and 
the greatest processing flexibility, i.e., the ability to process a large 
variety of traditional application programs. In an effort to increase the 
processing speed and flexibility of supercomputers, the cluster 
architecture for highly parallel multiprocessors described in the 
previously identified parent application provides an architecture for 
supercomputers wherein a multiple number of processors and external 
interface means can make multiple and simultaneous requests to a common 
set of shared hardware resources, such as main memory, secondary memory, 
global registers, interrupt mechanisms, or other shared resources present 
in the system. 
One of the important considerations in designing such shared-resource, 
multiprocessor systems is to provide an efficient mechanism for processors 
and external interface ports to signal other processors and external 
interface ports. As used within the present invention, the term signal 
refers to the operation by which one device (processor or external 
interface port) indicates to another device that an event has occurred 
that requires action or intervention by the device being signaled. From a 
traditional software perspective, signals are more commonly referred to as 
interrupts in the sense that the operational flow of the device is 
interrupted to process the signal. 
Many parallel processor architectures implement signals as messages passed 
through the system on a common bus or channel, such as in the Intel iPSC 
Concurrent computer or in the Sequent Balance Series. In this type of 
architecture, message transmission can take milliseconds for any processor 
to interrupt another in the system, largely due to the overhead associated 
with assembling, transmitting, and interpreting a complex message 
structure. This overhead is a limitation of this type of signaling 
architecture. 
Other parallel processor architectures do not permit signals to be sent and 
received by peripheral controllers. In this architecture, processors are 
dedicated to communicating with input/output devices such that an 
input/output device can communicate only with the processor to which it is 
connected. This restriction limits the flexibility for assigning 
processors to input/output control tasks. 
Another problem with many of the present interrupt mechanisms for 
multiprocessor systems is that all of the processors in the multiprocessor 
system are unconditionally interrupted at the completion of an 
input/output activity, not just the processors associated with controlling 
that activity. The disadvantage to this technique is that all programs 
executing on the multiprocessor system are interrupted which wastes 
processor resources while the interrupt are being serviced by one of the 
processors. 
Although the prior art interrupt mechanisms for multiprocessor systems are 
acceptable under certain conditions, it would be desirable to provide a 
more effective interrupt mechanism for a multiprocessor system that was 
able to allow a process to select any individual interruptable resource to 
be the targeted handler for servicing a signal. In addition, it would be 
desirable to provide an interrupt mechanism for the cluster architecture 
for the multiprocessor system described in the parent application that 
aids in providing a fully distributed, multithreaded input/output 
environment. 
SUMMARY OF THE INVENTION 
The present invention is a signaling mechanism for a multiprocessor system 
that allows any processor or peripheral device to signal any other 
processor or peripheral device in the multiprocessor system and can 
resolve simultaneous conflicting signals. Unlike present interrupt 
mechanisms, the signaling mechanism of the present invention provides for 
targeted signals that include an address that is related to the signal 
which indicates to the hardware for the signaling mechanism where to 
direct the particular signal. Simultaneous conflicting signals (i.e., 
signals targeted to the same peripheral device or processor) are resolved 
by queuing the signals on a first-come, first-serve basis with an 
arbitration network determining the priority of simultaneous conflicting 
signals received during the same clock cycle. The simultaneous conflicting 
signals are then processed serially based upon the assigned priority. 
The present invention requires a very simple code to select a destination 
to receive a signal and provides a dedicated hardware network for signal 
distribution that rapidly transmits signals throughout the system. The 
present invention permits any processor in the system to signal any 
input/output device, as well as the reverse. 
Although it is theoretically possible for all of the devices in a 
multiprocessor system provided with the present invention to 
simultaneously issue conflicting signals, the present invention takes 
advantage of the statistical improbability of this occurrence to optimize 
the amount of hardware required to process the conflicting signals as 
compared to the decrease in the overall performance of the multiprocessor 
system as a result of serially processing such conflicting signals. 
The signaling mechanism is accessible throughout the multiprocessor system. 
All processors and peripheral devices (i.e., secondary memory transfer 
controllers and peripheral controllers) are able to send and receive 
signals. In addition, all signals carry two bits of information that are 
used by the receiving device to determine what action, if any, should be 
taken as a result of receiving the signal. These features permit the 
implementation of a variety of signaling techniques throughout the system. 
For example, a secondary memory transfer controller uses type 0 signals as 
a start command, and uses type 1 signals as a halt command. Because any 
processor or peripheral device in the system can send a signal to any 
secondary memory transfer controller, any device can start or stop any 
secondary memory transfer controller in the system. 
An objective of the present invention is to provide a method and apparatus 
for a signaling mechanism for a multiprocessor system that allows any 
processor or external interface port to signal any other processor or 
external interface port in the multiprocessor system. 
Another objective of the present invention is to provide a signaling 
mechanism that can resolve simultaneous conflicting signals issued by a 
plurality of processors or external interface ports. 
Another objective of the present invention is to provide a signaling 
mechanism that conveys a plurality of types of signal to the receiving 
device. 
These and other objectives of the present invention will become apparent 
with reference to the drawings, the detailed description of the preferred 
embodiment and the appended claims.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring to FIG. 1, the architecture of a single multiprocessor cluster of 
the preferred embodiment of the multiprocessor system for use with the 
present invention will be described. The preferred cluster architecture 
for a highly parallel scalar/vector multiprocessor system is capable of 
supporting a plurality of high-speed processors 10 sharing a large set of 
shared resources 12 (e.g., main memory 14, global registers 16, and 
interrupt mechanisms 18). The processors 10 are capable of both vector and 
scalar parallel processing and are connected to the shared resources 12 
through an arbitration node means 20. Also connected through the 
arbitration node means 20 are a plurality of external interface ports 22 
and input/output concentrators (IOC) 24 which are further connected to a 
variety of external data sources 26. The external data sources 26 may 
include a secondary memory system (SMS) 28 linked to the input/output 
concentrator 24 via a high speed channel 30. The external data sources 26 
may also include a variety of other peripheral devices and interfaces 32 
linked to the input/output concentrator 24 via one or more standard 
channels 34. The peripheral devices and interfaces 32 may include disk 
storage systems, tape storage system, printers, external processors, and 
communication networks. Together, the processors 10, shared resources 12, 
arbitration node 20 and external interface ports 22 comprise a single 
multiprocessor cluster 40 for a highly parallel multiprocessor system in 
accordance with the preferred embodiment of the present invention. 
The preferred embodiment of the multiprocessor clusters 40 overcomes the 
direct-connection interface problems of present shared-memory 
supercomputers by physically organizing the processors 10, shared 
resources 12, arbitration node 20 and external interface ports 22 into one 
or more clusters 40. In the preferred embodiment shown in FIG. 2a and 2b, 
there are four clusters: 40a, 40b, 40c and 40d. Each of the clusters 40a, 
40b, 40c and 40d physically has its own set of processors 10a, 10b, 10c 
and 10d, shared resources 12a, 12b, 12c and 12d, and external interface 
ports 22a, 22b, 22c and 22d that are associated with that cluster. The 
clusters 40a, 40b, 40c and 40d are interconnected through a remote cluster 
adapter 42 that is a logical part of each arbitration nodes means 20a, 
20b, 20c and 20d. Although the clusters 40a, 40 b, 40c and 40d are 
physically separated, the logical organization of the clusters and the 
physical interconnection through the remote cluster adapter 42 enables the 
desired symmetrical access to all of the shared resources 12a, 12b, 12c 
and 12d across all of the clusters 40a, 40b, 40c and 40d. 
Referring now to FIG. 3, the physical organization of the Signaling 
Mechanism in the four-cluster preferred embodiment of the present 
invention will be described. There are sixteen ports 47 to the global 
registers 16, signal logic 31, and fast interrupt logic 33 from the 
thirty-two processors 10 and thirty-two external interface ports 22 in a 
cluster 40. Each port 47 is shared by two processors 10 and two external 
interface ports 22 and is accessed over the path 52. A similar port 49 
services inter-cluster requests for the global registers 16, fast 
interrupt logic 31, and signal logic 33 in this cluster as received by the 
MRCA means 48 and accessed over the path 56. As each request is received 
at the NRCA means 46, a cross bar and arbitration means 51 direct requests 
to the appropriate destination. If simultaneous requests come in for 
access to the SETN registers in the fast interrupt logic 33, for example, 
these requests are arbitrated for in a pipelined manner by the cross bar 
and arbitration means 51. The cross bar and arbitration means 51 utilizes 
a Multiple Request Toggling scheme algorithm. It receives input from 
sixteen arbitration nodes 44 and one MRCA means 48. An arbitration 
decision requires address information to select the target register and 
control information to determine the operation to be performed. This 
information is transmitted to the NRCA means 46 along with the data. The 
address and control can be for data to be sent to global registers 16 or 
to signal logic 31 or the fast interrupt logic 33. 
Referring now to FIG. 9, the cross bar/arbitration means 51 is described in 
greater detail. The flow begins with data from one of the arbitration 
nodes 44 which has been buffered by the NRCA means 46. As each request is 
received at the NRCA input registers 510 (FIG. 10), decode logic 406 
decodes the request to be presented to a global register arbitration 
network 410. If simultaneous requests come in for multiple global 
registers 16 in the same global register file 400, these requests are 
handled in a pipelined manner by the FIFO's 412, pipelines 414 and the 
global register arbitration network 410. Priority is assigned by a FIFO 
(first in, first out) scheme supplemented with a multiple request toggling 
priority scheme. The global register arbitration network 410 uses this 
type of arbitration logic, or its equivalent, to prioritize simultaneous 
requests to the same global register file 400. When priority is determined 
by the arbitration network 410, a 17.times.10 crossbar switch means 430 
matches the request in the FIFO 412 with the appropriate global register 
file 400. A plurality of NRCA input registers 510 (FIG. 10) provide 
seventeen paths into the global registers input crossbar 430. There are 
eight paths 440 out of the global registers input crossbar 430 to the 
global register files 400, one path 442 to the signal logic 31, and one 
path 444 to the fast interrupt logic 33. After the global register file 
operation is completed, global register output cross bar 422 routes any 
output from the operation back to the requesting port. 
In the preferred embodiment shown in FIG. 10, each global register file 400 
has 1024 general purpose, 64-bit registers. Each global register file 400 
also contains a separate Arithmetic and Logical Unit (ALU) operation unit 
460, permitting eight separate global register operations in a single 
clock cycle per cluster. The global register files 400 are interleaved 
eight ways such that referencing consecutive locations accesses a 
different file with each reference. In this embodiment, the global 
registers are implemented using a very fast 1024.times.64-bit RAM. 
As shown in FIG. 10, address and command information travel through a 
pipeline 520 that is separate from the data pipeline 530. The address and 
command information is decoded and used to direct data and certain of the 
address bits to their destination. Because the results of the arbitration 
decisions are used to direct data to this destination, the data and 
arbitration results must arrive at the input crossbar 430 in the same 
clock cycle. Staging registers 560 are added to the data pipeline 530 to 
adjust the data delay to match the control delay through the address 
pipeline 520. 
As shown in FIG. 11, the arbitration is based on a decode of address bit 13 
(the SETN select bit), the three address least significant bit (the global 
register file select bits), and a four-bit operation code (not shown). If 
the operation code specifies a signal operation, the address and data 
information are always sent to the signal logic output port 442. If 
address bit 13 is set to one, the address, data, and command information 
are sent to the fast interrupt logic output port 444. Otherwise, the 
address, control, and data are sent to the global register file output 
port selected by the three address LSB using one of the paths 440. 
The other ten address bits of the logical address (bits 12-3) shown at path 
540 in FIG. 10 are not used in the arbitration process. They accompany the 
data and are used in the functional units to select which register in the 
file 400 will be modified. The command bits on path 540 are duplicated and 
carried through the data pipeline as well for use at the destination. 
Simultaneous requests from different sources for the same global register 
file 400 (or for the signal logic 31 or the fast interrupt logic 33) are 
resolved by the arbitration logic 410 by granting one of the requestors 
access and delaying any other requests to later cycles. The arbitration 
address pipeline registers 520 hold any requests that cannot be 
immediately serviced in the Address Pipeline FIFO 570. In any single Data 
Pipeline FIFO 580, the data are submitted serially. Similarly, requests in 
the Address Pipeline FIFO 570 are handled serially. For example, data B 
entered later cannot pass data A entered before it. Although data A may be 
waiting for a busy global register, and data B may be waiting for an 
available global register, data B can not be processed until data A is 
finished. Data stays in order within a single queue; no data under Address 
Control can slip ahead of the data order in Data Address Control. 
Ten arbitrations can be handled simultaneously by the arbitration logic 
410. If data cannot go, signals 512 and 514 are sent to FIFOs 570 and 580, 
respectively, instructing them to hold the request at their respective 
outputs. The FIFOs 570 and 580 then wait for their arbitration decision. 
Signals (not shown) are sent back to each requestor from the arbitration 
logic 410 indicating that a request has been removed from the FIFOs 570 
and 580. The source uses this signal to determine when the FIFOs 570 and 
580 are full. The source stops sending requests when the FIFOs 570 and 580 
are full so that no requests are lost. Once an arbitration decision is 
made, a multiplex select signal 590 is generated that steers the input 
cross bar 460. This automatically unloads the FIFOs 570 and 580 and sends 
data to the global register files 400 or the signal logic 31 or the fast 
interrupt logic 33. 
Referring now to FIG. 4, an overview of the architecture for the 
input/output system of the preferred embodiment of present invention will 
be described. The input/output peripheral devices 32 are connected through 
the standard channels 34, the input/output concentrator 24 and the 
external interface ports 22 to the main memory (MM) 14 and global 
registers 16 and can directly read and write to these shared resources 12 
within the same cluster 40, as well as in other clusters 40. The 
peripheral devices 32 can also read and write to secondary memory (SM) in 
the secondary memory system (SMS) 28 associated with the same cluster 40a, 
for example, but cannot access the SMS 28 in other clusters 40b-40d. It 
should be noted that a path is not available to allow processors 10 and 
peripheral devices 32 to directly exchange data. Any such exchanges must 
take place through main memory 14, SMS 28 or the global registers 16. 
The input/output concentrator (IOC) 24 contains the data paths, switches, 
and control functions to support data transfers amoung the various 
input/output components. In the preferred embodiment, either eight or 
sixteen IOC's 24 are physically located within a single input/output 
chassis 100. Each IOC 24 supports up to eight channel adapters 102 that 
interface to the standard channels 34 and the peripheral controllers 103, 
a secondary memory transfer controller (SMTC) 104 that controls a 
secondary memory port 106 to the high speed channel 30 and the SMS 28, a 
cluster port 108 that connects to the external interface ports 22, 
concentrator signal logic 110 that distributes interrupt signals to the 
channel adapters 102 and the SMTC 104, and a data path crossbar switch 
112. Each IOC 24 can read or write a single, 64-bit word in main memory 14 
every other clock cycle. The IOC 24 can also read or write a word to the 
SMS 28 while simultaneously accessing main memory 14. 
Each channel adapter 102 contains the functions necessary to exchange data 
with a peripheral device controller 103 from an input/output peripheral 
device 32 over a standard input/output channel 34. The channel adapters 
102 access main memory 14, SMS 28 and global registers 16, and send 
signals to the processors 10 through the IOC 24. The cross bar switch 112 
in the IOC 24 multiplexes access requests among the channel adapters 102 
attached to it, routing data to the destination selected by a given 
transfer. All eight channel adapters 102 requesting data at the maximum 
rate require the maximum available rate from main memory 14 or the maximum 
available rate from SMS 28. 
The peripheral controllers 103 through the standard channel 34 can initiate 
signals by writing the destination select value to the signal interrupt 
logic 31. A command code is supported by the standard channel 34 that 
allows a peripheral controller 103 to perform this operation. The SMTC 104 
may also transmit signals to peripheral device controllers 103. Logic in 
the input/output system initiates the appropriate channel activity when it 
detects that a signal has been sent to the device associated with any 
given channel. This method is used to initiate signals and the action 
taken in response to a signal varies according to device type. The 
input/output logic, the command codes and other details of the operation 
of signals in the input/output subsystem of the preferred embodiment are 
described in greater detail in the in the previously identified co-pending 
application entitled DISTRIBUTED INPUT/OUTPUT ARCHITECTURE FOR A 
MULTI-PROCESSOR SYSTEM. 
A destination for the signals is selected by transmitting a destination 
select value along with the signal. FIG. 5 shows the logical-to-physical 
mapping for the destination select values. Both processors 10 and IOCs 24 
can send and receive signals, in the same and in different clusters 40. 
The following describes how the contents of the Signal Value are 
interpreted in the system: 
Cluster Select determines which cluster 40 the Signal will be sent to. 
Logic in the NRCA means 46 and MRCA means 48 determines which cluster is 
signalled for any value. 
Substrate Select determines the physical processor 10 or input/output 
concentrator 24 which will receive the signal. 
Class Select determines which type of device will receive the interrupt. 
The two bit code is as follows: O--processor, 1--input/output 
concentrator, 2--secondary memory transfer controller, and 3--reserved. 
Channel Select. When an input/output concentrator 24 is specified in the 
Class Select field, bits 4 through 2 address a channel adapter on the IOC 
24 selected in the Substrate Select field. When the secondary memory 
transfer controller is specified in the Class Select field, bit 2 selects 
which secondary memory transfer controller in an input/output concentrator 
means 26 will be interrupted: O--The Main Memory to Secondary Memory 
Transfer Controller is signalled, 1--the Secondary Memory to Main Memory 
Transfer Controller will be signalled. This field is ignored for all other 
class selections. 
Type Select determines which type of signal is to be transmitted. The 
signal type is captured at the destination device. The effect of different 
types of signals is device dependent. 
Processors 10 generate Signals through the Signal instruction. For signals 
generated by the Signal instruction, the value in the S register selected 
by the Signal instruction is interpreted as the destination select value. 
Signals are received by the processors 10 as interrupt requests. Referring 
to FIGS. 6a and 6b, the signal are masked by the Disable Type bits (DTO-3) 
in the System Mode register. Masks for the Interval Timer and Fast 
Interrupt request as described in the previously identified parent 
application are also located in the System Mode register. Pending 
interrupts are captured in the Pending Interrupt (PI) control register. A 
bit in the PI register corresponds to each type of interrupt. An incoming 
signal sets the appropriate PI register bit and causes an interrupt if the 
SM mask for that bit is not set. PI bits are cleared by the interrupt 
handler code after recognizing the interrupts. 
Referring now to FIG. 7, a logical block diagram shows the operation of 
signals (interrupts) within the present invention. Processors 10 may 
initiate signals by executing the Signal instruction. The Signal 
instruction causes the contents of the referenced S-register to be sent to 
the NRCA means 46 through the arbitration node 44. Similarly, peripheral 
devices (i.e., peripheral controllers 103 and SMTCs 104) initiate signals 
by sending a command and signal value to NRCA means 46 through the port 47 
in the arbitration node 44. The NRCA means 46 examines the cluster select 
bits in the signal value and directs the signal to the appropriate 
cluster. If the signal is directed to the cluster 40 that the NRCA means 
46 is currently located, the NRCA means 46 will direct the signal to the 
global register crossbar 51 in that NRCA means 46. If the signal is 
directed to another cluster 40, the NRCA means 46 will send the signal to 
that cluster over the inter-cluster communication paths 58 via the MRCA 
means 48. The global register crossbar 51 will direct any signal to the 
signal dispatch logic 460. FIG. 8 relates to FIG. 7 by showing the signal 
codes as transmitted on the indicated paths (e.g., AA, BB, etc.) in the 
signal mechanism shown in FIG. 7. 
Once the signal value has reached the signal dispatch logic 460 in the NRCA 
means 46, it is dispatched from there using the signal fanout logic 470. A 
13-bit code, shown as AA in FIG. 8, is sent from the dispatch logic 460 to 
the fanout logic 470. The code is the same as the signal select value, but 
does not have the cluster select bits attached. They are no longer 
necessary at this point since the value has already been directed to the 
proper cluster 40. 
The signal fanout logic 470 decodes the substrate select field and sends a 
9-bit signal code, shown as BB in FIG. 8, to the arbitration node 44 of 
the processor 10 or external interface port 22 being signaled. Separate 
signal buses connect the fanout logic 470 with each arbitration node 44. 
Additional signal decode logic 480 within the arbitration node 44 further 
decodes the 9-bit signal code. A three-bit code, shown as DD in FIG. 8 is 
presented to each of the processors 10 attached to each arbitration node 
44. A seven-bit code, shown as CC in FIG. 8 is presented to each external 
interface ports 22 attached to the arbitration node 44 for further 
transmission to the IOC 24. 
The processors 10 further decode the signal value into the four types of 
signal and sets the appropriate bit in the PI register. If the 
corresponding interrupt disable bits are cleared in the SM register, 
processor instruction will be interrupted when the interrupt bit is set in 
the PI register. 
The IOC 24 further decodes the 7-bit signal code sent from the arbitration 
node 44 into individual signals that are sent to the channels and the 
SMTCs, as described in the previously identified co-pending application 
entitled DISTRIBUTED INPUT/OUTPUT ARCHITECTURE FOR A MULTIPROCESSOR 
SYSTEM. 
Although the description of the preferred embodiment has been presented, it 
is contemplated that various changes could be made without deviating from 
the spirit of the present invention. Accordingly, it is intended that the 
scope of the present invention be dictated by the appended claims rather 
than by the description of the preferred embodiment.