Output current monitor circuit for switching regulator

A circuit and method for providing an improved current monitoring circuit for a switching regulator. A circuit providing switching regulation with an improved current monitor, comprising a pulse width modulation (PWM) controller configured to provide P- and N-drive signals, an output stage connected to said PWM controller and configured to provide switching, comprising a high-side and low-side transistor, driven by said P- and N-drive signals, respectively, a sense circuit configured to provide output current sensing from the output stage during a sampling period when the N-drive signal is active, and a sampling timing generator configured to provide a an n-sampling signal, nsample, to the sense circuit, wherein a start of the n-sampling signal is delayed by a first delay after the sampling period and the n-sampling signal is ended prior to an end of the sampling period by a second delay.

RELATED PATENT APPLICATION

This application is related to Ser. No. 14/550,921, filed on Nov. 22, 2014, which is assigned to a common assignee, and which is herein incorporated by reference in its entirety.

BACKGROUND

Field

The disclosure relates generally to a voltage regulator and, more particularly, to output current monitoring circuit thereof.

Description of the Related Art

Voltage regulation is important where circuits are sensitive to transients, noise and other types of disturbances. The control of the regulated voltage over variations in both semiconductor process variation, and temperature is key to many applications. Additionally, power consumption is also a key design requirement.

In a recent power management integrated circuit (PMIC), precise output monitoring of a buck is required for more efficient power management of processors. Average output current is sensed and digitized, and used for controlling processors.

FIG. 1shows average output current monitor in a circuit known to the inventor. The buck100is composed of pulse width modulation (PWM) controller105and output stage130. Output current monitor is sampling timing generator170, sampler and sense circuit150. The PWM controller105has an input signal from Master clock output signal102, and Error amplifier115. The Error amplifier115a vout signal120and reference signal vref125. The PWM controller105generates two output signals pdrv111and ndrv112. The Output stage130contains p-channel metal oxide semiconductor (PMOS)135and pre-drive inverter140, and re-channel metal oxide semiconductor (NMOS145). The Output stage130drives node LX136which is connected to inductor152, capacitor load C153, and Load154for the output voltage level vout155. The sample timing generator170receives a signal from ndrv112. The sample timing generator170contains an AND logic gate175and delay device180. The output of the Sampling timing generator170is connected to the Sense150to generate an Output current information160.

FIG. 2shows the timing diagram200for the signals. The master clock PWM controller105ofFIG. 1generates PWM signals, pdrv220and ndrv230. Pdrv is activated with master clock rising210. Pulse width of pdrv is determined by the control signal from the error amplifier. When pdrv220is deactivated, ndrv230is activated immediately and keeps active until master clock rising210.

Output stage130is composed of PMOS135and NMOS145. PMOS is turned on when pdrv is active and NMOS is turned on when ndrv is active. The output, LX node136swings almost rail-to-rail and the inductor current swing in triangular waveform. The voltage drop is caused by the inductor current. The voltage drop during NMOS is turned on is expressed as Rnon*I(LX) using NMOS on-resistance Rnon.

FIG. 2highlights ndrv delay signal ndrv_dly240, sample signal nsample250, and current and voltage of the LX node136, I (LX)260, and V (LX)270. Current monitor circuit is composed of sampling timing generator170and sense circuit150ofFIG. 1. The sense circuit150estimates the average output current information160from the average of the voltage drop across the NMOS during sampling signal, nsample250ofFIG. 2is activated.

Sampling timing generator generates nsample250from NMOS on signal, ndrv. The sampling generator of prior art is composed of delay Td1and AND logic. To wait LX node136voltage settling, start of nsample250is delayed from ndrv while end of nsample is almost the same as ndrv. So the center of sampling timing is shifted by Td1/2 from the center of NMOS on-timing, and it causes sensing error. Using the delay Td1180in the sampling timing generator170, the sensing error is expressed as:
ΔIsense=dILX/dt*Td1/2=−Vout/L*Td1/2
It is affected by on the output voltage Vout and inductance L.

U.S. Patent Application 20100033146 to Irissou et al., describes a method for providing output (e.g., current) sensing and feedback in switching power converter topologies. Some embodiments include feedback functionality for generating a converter driver signal (for driving the switching converter) and/or a sample driver signal (for driving the sampling module) as a function of sensed output feedback from the sampling module

U.S. Patent Application 20080316781 to Liu, describes a buck converter LED driver circuit is provided. The driver circa, includes a buck power stage, a rectified AC voltage source, a voltage waveform sampler, and a control circuit.

U.S. Pat. No. 6,894,464 to Zhang, describes a multi-phase synchronous buck converter having plural single phase synchronous buck converter stages, connected together to provide an output current to a load. A sensing circuit in each converter stage includes a variable gain current sense amplifier.

U.S. Pat. No. 6,803,750 to Zhang, describes a device constructed of a plurality of single phase buck converter stages, and a sensing circuit for each converter stage to generate an output signal representative of the output current provided by that converter stage.

WO 1999031790 to Clark et al, describes a regulator with a sampling circuit that makes measurements of an electrical characteristic of the voltage regulator at discrete moments of time. A feedback circuit is coupled to the sampling circuit and the switch, and is configured to use the measurements to control the duty cycle to maintain the DC voltage substantially constant.

In these prior art embodiments, the solution to establish a sampling circuit in switching regulator utilized various alternative solutions.

SUMMARY

It is desirable to provide a solution to address an efficient voltage regulator with minimal power consumption.

It is desirable to provide a solution with improved sampling timing.

It is desirable to provide a solution with improved accuracy of the output current monitor.

A principal object of the present disclosure is to provide a circuit with a delay circuit which delays the master clock for the PWM controller.

Another further object of the present disclosure is to provide a circuit that generates PWM signals for the output stage, where the PMOS “on” signal, pdrv, starts when delayed clock rises and NMOS ndrv is activated during pdrv is deactivated.

Another further object of the present disclosure is to provide a circuit whose output stage PMOS is turned on during pdrv is active, and NMOS is turned on during ndrv is active.

Another further object of the present disclosure is to provide a circuit whose sampling signal generator generates a sampling signal nsample. Nsample is activated first delay signal Td1after ndrv is activated and deactivated at rising edge of master clock.

Another further object of the present disclosure is to provide a sense circuit that estimates the average output current using the average of the voltage drop across the NMOS transistor during the nsample signal is activated.

In summary, a circuit providing switching regulation with an improved current monitor, comprising a pulse width modulation (PWM) controller configured to provide P- and N-drive signals, an output stage connected to the PWM controller and configured to provide switching, comprising a high-side and low-side transistor, driven by said P- and N-drive signals, respectively, a sense circuit configured to provide output current sensing from the output stage during a sampling period when the N-drive signal is active, and a sampling timing generator configured to provide a an n-sampling signal to the sense circuit, wherein a start of said n-sampling signal is delayed by a first delay after the sampling period and said n-sampling signal is ended prior to an end of the sampling period by a second delay.

In addition, a circuit providing switching regulation with an improved current monitor comprising a pulse width modulation (PWM) controller configured to provide an output signal voltage, an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from said output stage, a sample timing generator configured to provide a first delay signal to said sense circuit wherein said sampling timing generator comprises a first delay circuit, a first flip-flop coupled to an inverter, whose inverter is coupled to an AND logic gate whose output is a second flip-flop, wherein second flip-flop is further coupled to the first delay circuit, and a master clock configured to provide a second delay signal to said PWM controller and configured to provide a signal to said sample timing generator.

In addition, a second embodiment of an output current monitor implemented in a buck regulator contains a second sampling timing generator implementation. The buck is composed of PWM controller and output stage. Output current monitor is sampling timing generator, sampler and sense circuit. The PWM controller has an input signal from Master clock signal, followed by second delay element Delay Td2, and a second input signal from Error amplifier. The Error amplifier receives a vout signal and reference signal vref. The PWM controller generates two output signals pdrv and ndrv. The Output stage contains PMOS and a pre-drive inverter, and NMOS. The Output stage drives node LX which is connected to inductor, capacitor load C, and Load for the output voltage level vout. The sample timing generator receives a signal from ndrv. The sample timing generator contains a first delay element Delay Td1followed by a 3-input logic gate. Additionally it contains a signal from the Master clock to a second 2-input logic gate, and a second signal from the delayed clock signal to an inverter. The logic gate output is connected to the 3-input logic gate. The output of the Sampling timing generator is connected to the Sense to generate an Output current information.

In addition, a method is disclosed in accordance with the embodiment of the disclosure. A method of providing an improved current monitor in a switching regulator comprising the steps of a first step, (a) providing a circuit on a pulse width modulation (PWM) controller, a master clock delay circuit, an output stage, a sampling timing generator, and a sense circuit, a second step (b) sampling the inductor current during an NMOS active period, a third step, (c) starting the sampling after a first delay after a start of the NMOS active period, and a fourth step (d) ending the sampling a second delay period before a PMOS active period begins.

Other advantages will be recognized by those of ordinary skill in the art.

DETAILED DESCRIPTION

FIG. 3is a circuit schematic in accordance with the first embodiment of the disclosure.FIG. 3shows a block diagram of the invention. The Master clock302is delayed by the delay element Delay Td2303and used for PWM controller305. Sampling signal nsample is generated in the Sampling timing generator370. It starts the first delay element Delay Td1377after ndrv is activated. Its end is the second delay element Delay Td2303earlier than ndrv, because nsample is reset by Master clock302but signal ndrv312is reset by delayed clock. This sampling timing generator is logic circuit and various kinds of implementations are possible. The necessary elements are as follows: (1) the first flip-flop which is set by rise of master clock and reset when sampling signal is inactive; (2) the second flip-flop of which output is sampling signal which is set by delayed ndrv, and reset when ndrv is inactive or when first flip-flop is active, (3) and a delay which is generated delayed ndrv from ndrv.

FIG. 3shows average output current monitor implemented in a buck regulator. The buck300is composed of PWM controller305and output stage330. Output current monitor is sampling timing generator370, sampler and sense circuit350. The PWM controller305has an input signal from Master clock signal302, followed by the second delay element Delay Td2303, an a second input signal from Error amplifier315. The Error amplifier315a vout signal320and reference signal vref325. The PWM controller305generates two output signals pdrv311and ndrv312. The Output stage330contains PMOS335and pre-drive inverter340, and NMOS345. The Output stage330drives node LX336which is connected to inductor352, capacitor load C353, and Load354for the output voltage level vout355. The sample timing generator370receives a signal from ndrv312. The sample timing generator370contains first delay element Delay Td1377followed by a flip-flop375. Additionally it contains a signal from the Master clock302to a second flip-flop380, an inverter378, an AND logic gate376whose output is connected to flip-flop375. The output of the Sampling timing generator370is connected to the Sense350to generate an Output current information360.

FIG. 4shows the timing diagram400for the signals. The master clock PWM controller signal410, has also a delayed clock signal415, that generates PWM signals, signal pdrv420and signal ndrv430. Signal pdrv is activated with signal master clock rising410. Pulse width of signal pdrv is determined by the control signal from the error amplifier. When signal pdrv420is deactivated, signal ndrv430is activated immediately and keeps active until signal master clock rising210.

Output stage430is composed of PMOS135and NMOS145. PMOS is turned on when signal pdrv is active and NMOS is turned on when signal ndrv is active. The output, LX node136swings almost rail-to-rail and the inductor current swing in triangular waveform. The voltage drop is caused by the inductor current. The voltage drop during NMOS is turned on is expressed as Rnon*I(LX) using NMOS on-resistance Rnon.

FIG. 4is a timing diagram in accordance with the first embodiment of the disclosure. Timing chart is shown inFIG. 4.FIG. 4highlights signal master clock410, signal delayed clock415, signal p-channel pdrv420, signal n-channel ndrv430, n-channel drive ndrv delay signal ndrv_dly440, sample signal nsample450, and current and voltage of the LX node336, I (LX)460, and V (LX)470.

The center of nsample signal is shifted by the first signal delay Td1and the second signal delay Td2. The sensing error due to timing shift is expressed as:
ΔIsense=dILX/dt*(Td1−Td2)/2=−Vout/L*(Td1−Td2)/2

By using identical delay circuits for the first delay element Delay Td1and the second delay element Delay Td2, for the delay signal generation, the sensing error can be minimized.

FIG. 5is a circuit schematic in accordance with the second embodiment of the disclosure.FIG. 5shows average output current monitor implemented in a buck regulator. The essential elements in this implementation for the sampling timing generator are: (1) Sampling timing is generated as AND of ndrv, ndrv_dly and mask signal; (2) Ndrv_dly is delay of ndrv, and (3) a mask signal is inactive only from master clock's rise to delayed clock's rise. The buck500is composed of PWM controller505and output stage530. Output current monitor is sampling timing generator570, sampler and sense circuit550. The PWM controller505has an input signal from Master clock signal502, followed by the second delay element Delay Td2503, and a second input signal from Error amplifier515. The Error amplifier515has two inputs, with a vout signal520and reference signal vref525. The PWM controller505generates two output signals pdrv511and ndrv512. The Output stage530contains PMOS535and pre-drive inverter540, and NMOS545. The Output stage530drives node LX536which is connected to inductor552, capacitor load C535, and Load554for the output voltage level vout555. The sample timing generator570receives a signal from ndrv512. The sample timing generator570contains first delay element Delay Td1577followed by a 3-input logic gate576. Additionally it contains a signal from the Master clock502to a second 2-input logic gate580, and a second signal from the delayed clock signal504to an inverter575. The logic gate580output is connected to the 3-input logic gate576. The output of the Sampling timing generator570is connected to the Sense550to generate an Output current information560.

FIG. 6is a method in accordance with the first embodiment of the disclosure. A method600of providing an improved current monitor in a switching regulator comprising the steps of a first step610, (a) providing a circuit on a PWM controller, a master clock delay circuit, an output stage, a sampling timing generator, and a sense circuit, a second step620(b) generating a delay to the master clock with a master clock delay circuit for the PWM controller, a third step630(c) generating a PMOS signal p-channel drive, and NMOS n-channel drive from said output stage, a fourth step640(d) generating a signal n-channel drive for said sampling timing generator when p-channel drive is de-active, a fifth step,650(e) generating a sampling timing generator delay signal n-channel drive delay, a sixth step660(f) generating a sampling signal n-channel sample when n-channel sample is activated Td1after n-channel drive is activated and deactivated at rising edge of master clock, a seventh step670(g) providing a signal from the sampling timing generator to said sense circuit, and, an eight step680(h) estimating the average output current using the average of the voltage drop across NMOS during n-channel sample is activated.

Other advantages will be recognized by those of ordinary skill in the art. The above detailed description of the disclosure, and the examples described therein, has been presented for the purposes of illustration and description. While the principles of the disclosure have been described above in connection with a specific device, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the disclosure.