Magnetoresistive random-access memory (MRAM) random number generator (RNG) and a related method for generating a random bit

In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is then read from the MRAM cell.

BACKGROUND

Many modern day electronic devices (e.g., computers, mobile phones, etc.) rely on random numbers to securely store and transmit data. These random numbers may be generated by a random number generator (RNG). Some types of random number generators are pseudorandom number generators (PRNGs), while others are true random number generators (TRNGs). PRNGs rely on algorithms (e.g., software) to generate a PRNG-sequence that resembles a sequence of random numbers. However, the PRNG-sequence is not a truly random number due to the PRNG-sequence being determined by a non-random initial value (e.g., a seed value). On the other hand, TRNGs rely on physical processes that, in theory, are truly random. Thus, TRNGs are favored over PRNGs in some digital applications (e.g., cryptography).

DETAILED DESCRIPTION

The present disclosure will now be described with reference to the drawings wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. It will be appreciated that this detailed description and the corresponding figures do not limit the scope of the present disclosure in any way, and that the detailed description and figures merely provide a few examples to illustrate some ways in which the inventive concepts can manifest themselves.

Typically, integrated chips (ICs) comprise electronic memory devices. Magnetoresistive random-access memory (MRAM) memory devices are candidates for next generation electronic memory devices due to their fast read/write speeds, low power consumption, and compatibility with current complementary metal-oxide-semiconductor (CMOS) processes. MRAM memory devices (e.g., random-access memory (RAM), read-only memory (ROM), hardware caches, solid-state disks (SSDs), etc.) typically comprise a plurality of MRAM cells arranged in an array.

The MRAM cells comprise a magnetic tunnel junction (MTJ) configured to store data based on a magnetic orientation of the MTJ. For example, the MTJ may have a first resistive state (e.g., a parallel orientation between a pinned layer and a free layer) associated with a first data state (e.g., binary “0”) or a second resistive state (e.g., an anti-parallel orientation between a pinned layer and a free layer) associated with a second data state (e.g., binary “1”). The resistive state of the MRAM cells may be switched by providing the MRAM cells an electrical signal having a specific value (e.g., voltage value, current value, etc.) corresponding to one or more pulses. To reduce the potential of read/write errors, the specific value corresponding to the one or more pulses is such that when the electrical signal is provided to the MRAM cells the MRAM cells have a probability of about 1 (e.g., about 100 percent) to switch resistive states.

In various embodiments, the present application is directed toward a method for generating a random bit with a MRAM cell. The random bit is generated by first setting a resistive state of the MRAM cell to a first resistive state. A RNG signal is then provided to the MRAM cell, where the RNG signal has a probability of about 0.5 (e.g., about 50 percent) to switch the resistive state of the MRAM cell from the first resistive state to a second resistive state. Because the RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from the first resistive state to the second resistive state, the resultant data state stored in the MRAM cell is a random bit. Further, because the MRAM cell switching its resistive state is a physical process (e.g., physically switching the orientation of its free layer) and the RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from the first resistive state to the second resistive state, multiple MRAM cells may be utilized in a random number generator (RNG) (e.g., a true random number generator). Moreover, the RNG may be integrated into an IC having a MRAM memory device without increasing manufacturing complexities (e.g., increased deposition processes, photolithography processes, etching processes, etc.), and thus the cost to integrate the RNG on the IC may be reduced.

In some embodiments, the RNG signal is generated by performing a probability trimming series on the MRAM cell. The probability trimming series comprises performing a probability trimming loop a predefined number of times. The probability trimming loop comprises providing a plurality of write signals to the MRAM cell. Each of the plurality of write signals has a corresponding value (e.g., voltage value, pulse width, number of pulses, magnetic field strength, etc.). The corresponding values of the write signals may differ from one another in a stepwise like manner (e.g., incremental increases/decreases in voltage, pulse width, number of pulses, magnetic field strength, etc.). Before each write signal is provided to the MRAM cell, the MRAM cell is set to the first resistive state. After each write signal is provided to the MRAM cell, the resistive state of the MRAM cell is read and recorded to document whether the resistive state of the MRAM cell switched from the first resistive state to a second resistive state.

Across a total number of times the probability trimming loop is performed, a total number of times the resistive state of the MRAM cell switched from the first resistive state to the second resistive state is calculated for each of the write signals. Thereafter, a calculation may be performed to determine which value of the corresponding values has a probability of about 0.5 to switch the resistive state of the MRAM cell from the first resistive state to the second resistive state. The RNG signal is then generated based on the value that has the probability of about 0.5 to switch the resistive state of the MRAM cell from the first resistive state to the second resistive state. Accordingly, the RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from the first resistive state to a second resistive state.

FIG.1illustrates a cross-sectional view of some embodiments of a magnetoresistive random-access memory (MRAM) cell100configured to generate a random bit.

As shown inFIG.1, the MRAM cell100comprises a magnetic tunnel junction (MTJ)102disposed between a top electrode104and a bottom electrode106. In some embodiments, the MTJ102comprises a pinned layer108separated from a free layer110by a dielectric tunnel barrier112. In some embodiments, the pinned layer108may comprise cobalt (Co), iron (Fe), boron (B), nickel (Ni), ruthenium (Ru), iridium (Ir), platinum (Pt), or the like. In some embodiments, the dielectric tunnel barrier112may comprise magnesium oxide (MgO), aluminum oxide (Al2O3), or the like. In some embodiments, the free layer110may comprise cobalt (Co), iron (Fe), boron (B), or the like

The pinned layer108has a magnetic moment having a fixed orientation, while the free layer110has a magnetic moment in which its orientation can be changed to be either parallel (e.g., a ‘P’ state) or anti-parallel (e.g., an ‘AP’ state) with respect to the orientation of the magnetic moment of the pinned layer108. A relationship between the magnetic moment orientation of the pinned layer108and the free layer110defines a resistive state of the MRAM cell100, and thereby enables the MRAM cell100to store a data state. For example, in some embodiments, the MRAM cell100has a first resistive state (e.g., a low resistance state) when the orientation of the magnetic moment of the pinned layer108and the free layer110are parallel, and the MRAM cell100has a second resistive state (e.g., a high resistance state) when the orientation of the magnetic moment of the pinned layer108and the free layer110are anti-parallel. Accordingly, the MRAM cell100may store either a first data state (e.g., a binary “0”) when the MRAM cell100has the first resistive state or a second data state (e.g., a binary “1”) when the MRAM cell100has the second resistive state.

To switch the resistive state of the MRAM cell100between the first resistive state and the second resistive state, resistive state switching electrical signals are provided to the MRAM cell100, respectively. The resistive state switching electrical signals comprise switching values corresponding to one or more pulses of the resistive state switching electrical signals, respectively. For example, to change the resistive state of the MRAM cell from the first resistive state to the second resistive state, a first resistive state switching electrical signal is provided to the MRAM cell100. The first resistive state switching electrical signal comprises a first switching value corresponding to one or more pulses that when provided to the MRAM cell100switches the resistive state of the MRAM cell100from the first resistive state to the second resistive state.

Further, switching the resistive state of the MRAM cell100between the first resistive state and the second resistive state is based on a probability of the resistive state of the MRAM cell100switching when the resistive state switching electrical signals are respectively provided to the MRAM cell100. For example, if the first switching value corresponding to the one or more pulses is 0.1 Volt (V), the probability that the resistive state of the MRAM cell100switches from the first resistive state to the second resistive state may be about 0.1 (e.g., 10 percent). On the other hand, if the first switching value corresponding to the one or more pulses is 5 Volt (V), the probability that the resistive state of the MRAM cell100switches from the first resistive state to the second resistive state may be about 1 (e.g., 100 percent). Typically, the MRAM cell100is utilized in a MRAM memory device (e.g., random-access memory (RAM), read-only memory (ROM), hardware caches, solid-state disks (SSDs), etc.). Accordingly, to reduce the number of read/write errors of the MRAM memory device, the first switching value corresponding to the one or more pulses may be such that the probability that the resistive state of the MRAM cell100switches from the first resistive state to the second resistive state is about 1 (e.g., 100 percent).

Also shown inFIG.1, a random number generator (RNG) signal S is provided to the MRAM cell100. The RNG signal can, for example, take the form of one or more current or voltage pulses applied across the top electrode104and bottom electrode106, or can take the form of one or more magnetic field pulses applied to the MRAM cell100. The RNG signal S comprises a RNG value that corresponds to one or more pulses and that has a probability of about 0.5 to switch the state of the MRAM cell from the first state to the second state. In some embodiments, the RNG value corresponding to the one or more pulses is a voltage value. In such an embodiment, the RNG value may be between about 1 V and 2.5 V. In some embodiments, the RNG value corresponding to the one or more pulses is a duration value of pulse width. Pulse width is the transient time in which the RNG signal S has a predefined amplitude different than a baseline amplitude. In such embodiments, the RNG value may be between about 10 nanoseconds and about 1 microsecond. In further such embodiments, the predefined amplitude and the baseline amplitude may be a measure of, for example, voltage, current, or the like.

In some embodiments, the RNG value corresponding to the one or more pulses is a number of pulse signals (e.g., write attempts) over a predefined time. In such embodiments, each of the pulse signals may have a same amplitude and a same pulse width. In further such embodiments, the amplitude may be a measure of, for example, voltage, current, or the like. In yet further such embodiments, the RNG value may be between about 1 pulse signal and about 50 pulse signals. In some embodiments, the RNG value corresponding to the one or more pulses is current value. In such embodiments, the RNG value may be between a first current value that is sufficient to induce a magnetic field that passes through the MRAM cell100with a magnetic field strength of about 100 oersted (Oe), and a second current value that is sufficient to induce a magnetic field that passes through the MRAM cell100with a magnetic field strength of about 4000 Oe. In further such embodiments, the RNG signal S may be provided to a conductive line (e.g., a bit line, word line, write line, etc.) that is disposed near the MRAM cell100.

Further, the RNG signal S has a probability of about 0.5 (e.g., about 50 percent) to switch the resistive state of the MRAM cell100from the first resistive state to the second resistive state, or vice versa. In some embodiments, the probability of about 0.5 comprises any probability within 10 percent (e.g., between 0.45 and 0.55) of the probability of 0.5. More specifically, the probability of about 0.5 comprises any probability within 8 percent (e.g., between 0.46 and 0.54) of the probability of 0.5, any probability within 6 percent (e.g., between 0.47 and 0.53) of the probability of 0.5, any probability within 4 percent (e.g., between 0.48 and 0.52) of the probability of 0.5, and/or any probability within 2 percent (e.g., between 0.49 and 0.51) of the probability of 0.5. In further embodiments, the RNG signal S has a probability of about 0.5 to switch the resistive state of the MRAM cell100due to the RNG value corresponding to the one or more pulses causing the RNG signal S to switch from the first resistive state to the second resistive state, or vice versa, about half the time the RNG signal S is provided to the MRAM cell100. Because the RNG signal S has a probability of about 0.5 to switch the resistive state of the MRAM cell100from the first resistive state to the second resistive state, or vice versa, the MRAM cell100may generate a random bit (e.g., either the first data state or the second data state).

Moreover, because the MRAM cell100switches its resistive state based on a physical process (e.g., physically switching the magnetic moment orientation of its free layer) and the RNG signal S has a probability of about 0.5 to switch the resistive state of the MRAM cell100from the first resistive state to the second resistive state, or vice versa, multiple MRAM cells100may be utilized in a random number generator (RNG) (e.g., a true random number generator). Further, the RNG may be integrated into an integrated chip (IC) having a MRAM memory device without increasing manufacturing complexities (e.g., increased deposition processes, photolithography processes, etching processes, etc.). Accordingly, the cost to integrate the RNG on the IC may be reduced.

FIG.2illustrates a layout view of some embodiments of an integrated chip (IC)200having a random number generator (RNG)201comprising a plurality of MRAM cells, each corresponding to the MRAM cell100ofFIG.1.

As shown inFIG.2, the IC200comprises a RNG201disposed on a semiconductor substrate202. The RNG201comprises a plurality of MRAM cells, and the plurality of MRAM cells comprises N MRAM cells (100-1-100-N), where N is a number greater than or equal to 1. In some embodiments, the N MRAM cells (100-1-100-N) may be, for example, field write MRAM cells, STT-MRAM cells, or the like. In some embodiments, the semiconductor substrate202comprises any type of semiconductor body (e.g., monocrystalline silicon/CMOS bulk, silicon-germanium (SiGe), silicon on insulator (SOI), etc.).

Further, the RNG201comprises a memory component204configured to store data units (e.g., 1-bit data units, 2-bits data units, 4-bits data units, 8-bits data units, 16-bits data units, etc.) for the N MRAM cells (100-1-100-N), respectively. The data units store the RNG value corresponding to the one or more pulses for the N MRAM cells (100-1-100-N), respectively. The memory component204stores the data units in memory component words206, respectively. Each of the memory component words206comprises one or more memory cells208depending on the number of bits needed to store the data units. In some embodiments, the memory cells208may be, for example, memory component MRAM cells, memory component fuses, memory component resistive random-access cells, memory component flash memory cells, etc. In further embodiments, the memory component204may be, for example, read-only memory (ROM), a solid-state disk (SSDs), a register, a hardware cache, random-access memory, or the like.

A controller210is coupled to the memory component204and each of the N MRAM cells (100-1-100-N). Initially, the controller210is configured to set the resistive states of the N MRAM cells (100-1-100-N) to the first resistive state, respectively, by providing a first write signal SW1to each of the N MRAM cells (100-1-100-N). Further, the controller210is configured to read the data units stored in the memory component204. Subsequently, the controller210is configured to provide random number generator (RNG) signals S1-SNto the N MRAM cells (100-1-100-N), respectively. Each of the RNG signals S1-SNcomprises the RNG value corresponding to the one or more pulses for its corresponding one of the N MRAM cell (100-1-100-N).

For example, one of the memory component words206may store a first data unit and another one of the memory component words206may store a second data unit. The first data unit may store a first RNG value corresponding to the one or more pulses that corresponds to one of the N MRAM cells (e.g.,100-1), and the second data unit may store a second RNG value corresponding to the one or more pulses that correspond to another one of the N MRAM cells (e.g.,100-2). The controller210may set the resistive state of the one of the N MRAM cells (e.g.,100-1) and the other one of the N MRAM cells (e.g.,100-2) to the first resistive state by providing each of them the first write signal SW1. The controller210reads the one of the memory component words206and the other one of the memory component words206. After the controller210reads the one of the memory component words206and the other one of the memory component words206, the controller210generates a first RNG signal (e.g., S1) comprising the first RNG value corresponding to the one or more pulses and a second RNG signal (e.g., S2) comprising the second RNG value corresponding to the one or more pulses. The controller210then provides the first RNG signal (e.g., S1) to the one of the N MRAM cells (e.g.,100-1) and the second RNG signal (e.g., S2) to the other one of the N MRAM cells (e.g.,100-2).

RNG output circuitry212is coupled to the N MRAM cells (100-1-100-N). The RNG output circuitry212is configured to read the resistive states of the N MRAM cells (100-1-100-N), respectively, after the controller210provides the RNG signals S1-SNto the N MRAM cells (100-1-100-N), respectively. Further, the RNG output circuitry212is configured to output an N-bit random number based on the resistive states of the N MRAM cells (100-1-100-N) read by the RNG output circuitry212. The RNG output circuitry212outputs the N-bit random number due to each of the N MRAM cells (100-1-100-N) being provided an RNG signal S1-SNcomprising the RNG value corresponding to the one or more pulses for a corresponding one of the N MRAM cell (100-1-100-N).

If the N MRAM cells (100-1-100-N) were completely identical to one another, the RNG signals S1-SNwould have identical pulse shapes as one another to provide a switching probability of about 0.5 for each of the N MRAM cells (100-1-100-N). However, because of small, uncontrollable manufacturing variations in the N MRAM cells (100-1-100-N) and/or other small structural differences in the N MRAM cells (100-1-100-N), the RNG signals S1-SNoften have slightly different pulse shapes from one another to provide a probability of about 0.5 of switching the N MRAM cells (100-1-100-N) from the first resistive state to the second resistive state. Further, in some embodiments, the RNG signals S1-SNmay be applied concurrently to the N MRAM cells (100-1-100-N); such that the N-bits of the N-bit random number can be read simultaneously as a single word.

For example, after the controller210provides the one of the N MRAM cells (e.g.,100-1) the first RNG signal (e.g., S1) and the other one of the N MRAM cells (e.g.,100-2) the second RNG signal (e.g., S2), the RNG output circuitry212reads the resistive state of the one of the N MRAM cells (e.g.,100-1) and the other one of the N MRAM cells (e.g.,100-2). The probability that the RNG output circuitry212reads the resistive state of the one of the MRAM cells (e.g.,100-1) as the second resistive state is about 0.5 (e.g., about 50 percent) due to the controller210providing the first RNG signal (e.g., S1), which comprises the first RNG value corresponding to the one or more pulses, to the one of the MRAM cells (e.g.,100-1). Further, the probability that the RNG output circuitry212reads the resistive state of the other one of the MRAM cells (e.g.,100-2) as the second resistive state is about 0.5 due to the controller210providing the second RNG signal (e.g., S2), which comprises the second RNG value corresponding to the one or more pulses, to the other one of the N MRAM cells (e.g.,100-2). Accordingly, the RNG output circuitry212may output a N-bit random number based on the RNG output circuitry212having a probability of about 0.5 of reading the resistive state of the one of the MRAM cells (e.g.,100-1) as the second resistive state and a probability of about 0.5 of reading the resistive state of the other one of the MRAM cells (e.g.,100-2) as the second resistive state.

Also shown inFIG.2, tester circuitry214is electrically coupled to the RNG201. The tester circuitry214is configured to provide electrical signals to the RNG201and receive electrical signals from the RNG201. In some embodiments, the tester circuitry214may comprise tester bias circuitry216and tester analysis circuitry218. In further embodiments, the tester bias circuitry216and the tester analysis circuitry218may be electrically coupled together and configured to provide electrical signals to one another.

In some embodiments, the tester bias circuitry216is configured to provide the first write signal to the N MRAM cells (100-1-100-N) to set the resistive states of the N MRAM cells (100-1-100-N) to the first resistive state, respectively. In some embodiments, the tester bias circuitry216is configured to provide write signals, which are discussed in more detail below (e.g., see,FIGS.4A-4B), to the RNG201. In further embodiments, the tester analysis circuitry218is configured to record and analyze the resistive states of the N MRAM cells (100-1-100-N) read by the RNG output circuitry212. In yet further embodiments, the tester bias circuitry216is configured to write the data units for the N MRAM cells (100-1-100-N) to the memory component204.

In some embodiments, the IC200comprises the tester circuitry214. In such embodiments, the tester circuitry214is disposed on the semiconductor substrate202. In other embodiments, a semiconductor wafer testing unit (not shown) comprises the tester circuitry214. In such embodiments, the tester circuitry214may be disposed in a wafer prober housing (not shown) and electrically coupled to the RNG201via a probing structure (not shown) (e.g., probe card).

FIG.3illustrates a layout view of some more embodiments of the IC200ofFIG.2.

As shown inFIG.3, an external magnetic field generator302is coupled to the tester circuitry214. The external magnetic field generator302is configured to generate an external magnetic field304that passes through the N MRAM cells (100-1-100-N). In some embodiments, the tester circuitry214provides the external magnetic field generator302a magnetic field generator signal to generate the external magnetic field304. In further embodiments, the tester circuitry214may vary the current of the magnetic field generator signal to vary the magnetic field strength of the external magnetic field304. In yet further embodiments, by passing the external magnetic field304through the MRAM cells (100-1-100-N) and varying the magnetic field strength, the tester circuitry214may determine a magnetic field strength for each of the N MRAM cells (100-1-100-N) that has a probability of about 0.5 to switch their respective resistive states from the first resistive state to the second resistive state. These magnetic field strength values may be stored, and then re-applied to the N MRAM cells (100-1-100-N) after testing to generate random numbers.

As illustrated inFIGS.4A-4B, a flowchart400of some embodiments of a method for generating an N-bit random number, where N is a number greater than or equal to 1, with the IC200ofFIG.2is provided. While the flowchart400ofFIGS.4A-4Bis illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At402, a first write signal is provided to N magnetoresistive random-access memory (MRAM) cells to set a resistive state of each of the N MRAM cells to the first resistive state, where each of the N MRAM cells is configured to switch between the first resistive state and a second resistive state, and where N is a number greater than or equal to 1. For example, with reference toFIG.2, the first write signal is provided to the MRAM cells100to set their resistive states to the first resistive state. In some embodiments, the controller210provides the first write signal to each of the MRAM cells100. In such embodiments, the tester bias circuitry216may initiate the controller210to provide the first write signal to each of the MRAM cells100.

At404, a second write signal is provided to each of the N MRAM cells, where the second write signal has a first value corresponding to one or more pulses. For example, with reference toFIG.2, the second write signal is provided to each of the MRAM cells100. In some embodiments, the controller210provides the second write signal to each of the MRAM cells100. In such embodiments, the tester bias circuitry216may initiate the controller210to provide the second write signal to each of the MRAM cells100.

In some embodiments, the RNG value corresponding to the one or more pulses is a voltage value. In such an embodiment, the first value corresponding to the one or more pulses may be between about 1 V and 2.5 V. In some embodiments, the RNG value corresponding to the one or more pulses is a time value of pulse width. Pulse width is the transient time in which the second write signal has a predefined amplitude different than a baseline amplitude. In such embodiments, the first value corresponding to the one or more pulses may be between about 10 nanoseconds and about 1 microsecond. In further such embodiments, the predefined amplitude and the baseline amplitude may be a measure of, for example, voltage, current, or the like.

In some embodiments, the RNG value corresponding to the one or more pulses is a number of pulse signals (e.g., write attempts) over a predefined time. In such embodiments, each of the pulse signals may have a same amplitude and a same pulse width. In further such embodiments, the amplitude may be a measure of, for example, voltage, current, or the like. In yet further such embodiments, the first value corresponding to the one or more pulses may be between about 1 pulse signal and about 50 pulse signals. In some embodiments, the RNG value corresponding to the one or more pulses is a current value. In such embodiments, the first value corresponding to the one or more pulses may be between a first current value that is sufficient to induce a magnetic field that passes through each of the N MRAM cells with a magnetic field strength of about 100 oersted (Oe), and a second current value that is sufficient to induce a magnetic field that passes through each of the N MRAM cells with a magnetic field strength of about 4000 Oe. In further such embodiments, the second write signal may be provided to conductive lines (e.g., bit lines, word lines, write lines, etc.) that are disposed near the N MRAM cells, respectively.

At406, the resistive state of each of the N MRAM cells is read and recorded after the second write signal is provided to the N MRAM cells. For example, with reference toFIG.2, after the MRAM cells100have been provided the second write signal, the resistive state of each of the MRAM cells100is read and recorded to determine if the resistive state of each of the MRAM cells is the first resistive state or the second resistive state. In some embodiments, the RNG output circuitry212reads the resistive states of the MRAM cells100, respectively. In further embodiments, the tester analysis circuitry218records the resistive states of the MRAM cells100read by the RNG output circuitry212.

At408, the first write signal is provided to the N MRAM cells to set the resistive state of each of the N MRAM cells to the first resistive state. For example, with reference toFIG.2, the first write signal is provided to the MRAM cells100, respectively, to set their resistive states to the first resistive state. In some embodiments, the controller210provides the first write signal to each of the MRAM cells100. In such embodiments, the tester bias circuitry216may initiate the controller210to provide the first write signal to each of the MRAM cells100.

At409, a third write signal is provided to each of the N MRAM cells, where the third write signal has a second value corresponding to the one or more pulses different than the first value corresponding to the one or more pulses. For example, with reference toFIG.2, the third write signal is provided to each of the MRAM cells100. In some embodiments, the controller210provides the third write signal to each of the MRAM cells100. In other embodiments, the tester bias circuitry216provides the third write signal to each of the MRAM cells100. In yet other embodiments, the tester bias circuitry216initiates the controller210to provide the third write signal to each of the MRAM cells100.

In such embodiments where the RNG value corresponding to the one or more pulses is a voltage value, the second value corresponding to the one or more pulses may be different than the first value corresponding to the one or more pulses by 0.05 V or 0.1 V. In such embodiments where the RNG value corresponding to the one or more pulses is a time value of pulse width, the second value corresponding to the one or more pulses may be different than the first value corresponding to the one or more pulses by 10 nanoseconds or 100 nanoseconds. In such embodiments where the RNG value corresponding to the one or more pulses is a number of pulse signals (e.g., write attempts) over a predefined time, the second value corresponding to the one or more pulses may be different than the first value corresponding to the one or more pulses by about 1 pulse signal, 5 pulse signals, or 10 pulse signals. In such embodiments where the RNG value corresponding to the one or more pulses is a current value, the second value corresponding to the one or more pulses may be different than the first value corresponding to the one or more pulses by a current value that is sufficient to change the magnetic field strength of the magnetic field that passes through the N MRAM cells by 50 Oe or 100 Oe.

At410, the resistive state of each of the N MRAM cells is read and recorded after the third write signal is provided to the N MRAM cells. For example, with reference toFIG.2, after the third write signal has been provided to the MRAM cells100, the resistive state of each of the MRAM cells100is read and recorded to determine if the resistive state of each of the MRAM cells100is the first resistive state or the second resistive state. In some embodiments, the RNG output circuitry212reads the resistive states of the MRAM cells100, respectively. In further embodiments, the tester analysis circuitry218records the resistive states of the MRAM cells100read by the RNG output circuitry212.

In some embodiments,402,404,406,408,409, and410may be referred to as a probability trimming loop412. AlthoughFIG.4Aillustrates the probability trimming loop412as providing only a second write signal and a third write signal, it will be appreciated that any number of write signals may be provided to the N MRAM cells. Further, in some embodiments, it will be appreciated that if additional write signals are provided to the N MRAM cells, the resistive state of each of the N MRAM cells is set to the first resistive state before each of the additional write signals are provided to the N MRAM cells. Moreover, it will be appreciated that if additional write signals are provided to the N MRAM cells, the resistive states of each of the N MRAM cells is read and recorded after each of the additional write signals are provided to the N MRAM cells. In addition, it will be appreciated that if additional write signals are provided to the N MRAM cells, each of the additional write signals has a value corresponding to the one or more pulses that differs (e.g., by 0.05 V or 0.1V, 10 nanoseconds or 100 nanoseconds, etc.) from the value corresponding to the one or more pulses of the most preceding write signal that was provided to the N MRAM cells.

At414, the probability trimming loop412is repeated M times, where M is a number greater than or equal to 1. For example, with reference toFIG.2, the probability trimming loop412is repeated on the MRAM cells100M times (e.g., 1 time, 2 times, 5 times, 10 times, etc.). In some embodiments, M is dependent on a predefined statistical analysis (e.g., an infinite population sample size calculation, one-tailed statistical hypothesis test, a two-tailed statistical hypothesis test, some other statistical analysis, or a combination of the foregoing). In further embodiments, conditions (e.g., confidence interval, margin of error, sample size, etc.) of the predefined statistical analysis may depend on a desired specification of the IC200. For example, M may be at least about 97 if a desired specification of the IC200is to be that a given RNG signal has a probability of 0.5, with 95 percent confidence and 10 percent margin of error, to switch the resistive state of a given MRAM cell. It will be appreciated that, in some embodiments, M may not depend on the predefined statistical analysis (e.g., M may be a predefined number not based on the predefined statistical analysis).

At416, for each of the N MRAM cells, the total number of times the second resistive state was recorded after the second write signal was provided to the N MRAM cells is calculated, and the total number of times the second resistive state was recorded after the third write signal was provided to the N MRAM cells is calculated. In some embodiments,412,414, and416may be referred to as a probability trimming series418. AlthoughFIG.4Aillustrates the probability trimming series418as calculating the total number of times the second resistive state was recorded, it will be appreciated that the probability trimming series may calculate the total number of times the first resistive state was recorded instead.

For example, with reference toFIG.2, the tester analysis circuitry218calculates the number of times the tester analysis circuitry218recorded the second resistive state for each of the MRAM cells100after the first probability signal was provided to the MRAM cells100. In addition, the tester analysis circuitry218calculates the number of times the tester analysis circuitry218recorded the second resistive state for each of the MRAM cells100after the second probability signal was provided to the MRAM cells100. In some embodiments, once the total number of times the second resistive state is recorded for each of the MRAM cells100after both the first probability signal and the second probability signal is provided to the MRAM cells100, the probability trimming series418is complete.

At420, for each of the N MRAM cells, it is determined whether either the calculated total number of times the second resistive state was recorded after the second write signal was provided to the N MRAM cells is

M+12
or the calculated total number of times the second resistive state was recorded after the third write signal was provided to the N MRAM cells is

M+12.
For example, with reference toFIG.2, the tester analysis circuitry218determines, for each of the MRAM cells100, whether either the calculated total number of times the tester analysis circuitry218recorded the second resistive state after the second write signal was provided to the MRAM cells100is

M+12.
or the calculated total number of times the tester analysis circuitry218recorded the second resistive state after the third write signal was provided to the MRAM cells100is

In some embodiments, if the calculated total number of times the second resistive state was recorded after the first write signal (or the second write signal) was provided to the N MRAM cells is within a predefined range, it will be determined that the calculated total number of times the second resistive state was recorded after the first write signal (or the second write signal) was provided to the N MRAM cells is

M+12.
On the other hand, in some embodiments, if the calculated total number of times the second resistive state was recorded after the first write signal (or the second write signal) was provided to the N MRAM cells is outside the predefined range, it will be determined that the calculated total number of times the second resistive state was recorded after the first write signal (or the second write signal) was provided to the N MRAM cells is not

M+12.
In some embodiments, the predefined range is a range that defines whether the first value corresponding to the one or more pulses or the second value corresponding to the one or more pulses has a probability of about 0.5 to switch the resistive state of a corresponding MRAM cell.

In some embodiments, the predefined range may be within about 10 percent of

M+12
plus or minus 10 percent of

M+12).
Stated differently, the predefined range may be between about 0.45 and about 0.55 (e.g., 0.5 plus or minus 10 percent of 0.5) when utilizing a probability in which the first value (or second value) corresponding to the one or more pulses switches the resistive state of the corresponding MRAM cell. In further embodiments, the predefined range may be within 8 percent of

M+12
plus or minus 8 percent of

M+12),
within 6 percent of

M+12,
within 4 percent of

M+12,
or within 2 percent of

M+12.
Stated differently, when utilizing the probability in which the first value (or second value) corresponding to the one or more pulses switches the resistive state of the corresponding MRAM cell, the predefined range may be between 0.46 and 0.54 (e.g., 0.5 plus or minus 8 percent of 0.5), between 0.47 and 0.53, between 0.48 and 0.52, or between 0.49 and 0.51.

At422, if it is determined that, for each of the N MRAM cells, the calculated total number of times the second resistive state was recorded is

M+12
after either the second write signal was provided to the N MRAM cells or after the third write signal was provided to the N MRAM cells, then either the first value corresponding to the one or more pulses is recorded or the second value corresponding to the one or more pulses is recorded for each of the N MRAM cells. The first value corresponding to the one or more pulses is recorded for each of the N MRAM cells in which the calculated total number of times the second resistive state was recorded after the second write signal was provided to the N MRAM cells is

M+12.
The second value corresponding to the one or more pulses is recorded for each of the N MRAM cells in which the calculated total number of times the second resistive state was recorded after the third write signal was provided to the N MRAM cells is

For example, with reference toFIG.2, the tester analysis circuitry218determines, for each of the MRAM cells100, that either the calculated total number of times the second resistive state was recorded is

M+12
after the second write signal was provided to the MRAM cells100or after the third write signal was provided to the MRAM cells100. For each of the MRAM cells100that the tester analysis circuitry218determines that the second resistive state was recorded is

M+12
after the second write signal was provided to the MRAM cells100, the tester bias circuitry216records (e.g., writes) the first value corresponding to the one or more pulses in a corresponding memory component word206(e.g., as a data unit). For each of the MRAM cells100that the tester analysis circuitry218determines that the second resistive state was recorded is

M+12
after the third write signal was provided to the MRAM cells100, the tester bias circuitry216records (e.g., writes) the second value corresponding to the one or more pulses in the corresponding memory component word206.

Because the first value corresponding to the one or more pulses is recorded for each of the N MRAM cells in which the calculated total number of times the second resistive state was recorded after the second write signal was provided to the N MRAM cells is

M+12,
providing the first value corresponding to the one or more pulses to such MRAM cells has a probability of about 0.5 (e.g., about 50 percent) to switch the resistive state of such MRAM cells from the first resistive state to the second resistive state. Because the second value corresponding to the one or more pulses is recorded for each of the N MRAM cells in which the calculated total number of times the second resistive state was recorded after the third write signal was provided to the N MRAM cells is

M+12,
providing the second value corresponding to the one or more pulses to such MRAM cells has a probability of about 0.5 (e.g., about 50 percent) to switch the resistive state of such MRAM cells from the first resistive state to the second resistive state.

Further, in some embodiments, for one or more of the N MRAM cells, the calculated total number of times the second resistive state was recorded may be

M+12
after both the second write signal was provided to the N MRAM cells and after the third write signal was provided to the N MRAM cells. In such an embodiment, if the first value corresponding to the one or more pulses is less than the second value corresponding to the one or more pulses, the first value corresponding to the one or more pulses is recorded for such MRAM cells to increase the reliability of such MRAM cells. In further such embodiments, if the second value corresponding to the one or more pulses is less than the first value corresponding to the one or more pulses, the second value corresponding to the one or more pulses is recorded for such MRAM cells to increase the reliability of such MRAM cells.

For example, with reference toFIG.2, if the tester analysis circuitry218determines, for one or more of the MRAM cells100, the calculated total number of times the second resistive state was recorded is

M+12
after both the second write signal was provided to the N MRAM cells and after the third write signal was provided to the N MRAM cells, the tester analysis circuitry218compares the first value corresponding to the one or more pulses to the second value corresponding to the one or more pulses to determine whether the first value corresponding to the one or more pulses is less than the second value corresponding to the one or more pulses, or vice versa. For each of the one or more MRAM cells100, if the first value corresponding to the one or more pulses is less than the second value corresponding to the one or more pulses, the tester bias circuitry216records (e.g., writes) the first value corresponding to the one or more pulses in a corresponding memory component word206. For each of the one or more MRAM cells100, if the second value corresponding to the one or more pulses is less than the first value corresponding to the one or more pulses, the tester bias circuitry216(e.g., writes) records the second value corresponding to the one or more pulses in a corresponding memory component word206.

At424, if it is determined that, for any of the N MRAM cells, the calculated total number of times the second resistive state was recorded is not

M+12
after either the second write signal was provided to the N MRAM cells or after the third write signal was provided to the N MRAM cells, the probability trimming series418is repeated X times, where X is a number greater than or equal to 1. For example, with reference toFIG.2, if the tester analysis circuitry218determines that the calculated total number of times the second resistive state was recorded is not

M+12
for one of the MRAM cells100after either the second write signal was provided to the MRAM cells100or after the third write signal was provided to the MRAM cells100, the probability trimming series418is repeated X times on the MRAM cells100. In some embodiments, X is dependent on M, the predefined statistical analysis, and/or a different predefined statistical analysis. In further embodiments, X may be the same as M. In other embodiments, X may be less than or greater than M. It will be appreciated that, in some embodiments, X may not depend on the predefined statistical analysis or M (e.g., X may be a predefined number not based on either the predefined statistical analysis or M).

At426, for each of the N MRAM cells, the calculated total number of times the second resistive state was recorded after the second write signal was provided to the N MRAM cells is averaged, and the calculated total number of times the second resistive state was recorded after the third write signal was provided to the N MRAM cells is averaged. Although426recites the phrase “for each of the N MRAM cells,” it will be appreciated that this phrase may instead recite “for each of the MRAM cells of the N MRAM cells that were determined in420that the calculated total number of times the second resistive state was recorded is not

M+12
after either the second write signal was provided to the N MRAM cells or after the third write signal was provided to the N MRAM cells.”

For example, with reference toFIG.2, if the probability trimming series418is repeated one time on the MRAM cells100, the analysis circuitry calculates an average, for each of the MRAM cells100, between two calculated total number of times (e.g., a first calculated total number of times when the probability trimming series418was performed a first time and a second calculated total number of times when the probability trimming series418was repeated the one time) the second resistive state was recorded after the second write signal was provided to the MRAM cells100. In addition, the analysis circuitry calculates an average, for each of the MRAM cells100, between two calculated total number of times (e.g., a third calculated total number of times when the probability trimming series418was performed a first time and a fourth calculated total number of times when the probability trimming series418was repeated the one time) the second resistive state was recorded after the third write signal was provided to the MRAM cells100.

At428, either the first value corresponding to the one or more pulses is recorded or the second value corresponding to the one or more pulses is recorded for each of the N MRAM cells. The first value corresponding to the one or more pulses is recorded for each of the N MRAM cells in which the average of the calculated total number of times the second resistive state was recorded after the second write signal was provided to the N MRAM cells is closer to

M+12
than after the third write signal was provided to the N MRAM cells. The second value corresponding to the one or more pulses is recorded for each of the N MRAM cells in which the average of the calculated total number of times the second resistive state was recorded after the third write signal was provided to the N MRAM cells is closer to

M+12
than after the second write signal was provided to the N MRAM cells. Although428recites the phrase “for each of the N MRAM cells” inFIG.4B, it will be appreciated that this phrase may instead recite “for each of the MRAM cells of the N MRAM cells that were determined in420that the calculated total number of times the second resistive state was recorded is not

M+12
after either the second write signal was provided to the N MRAM cells or after the third write signal was provided to the N MRAM cells.”

Because the first value corresponding to the one or more pulses is recorded for each of the N MRAM cells in which the average of the calculated total number of times the second resistive state was recorded after the second write signal was provided to the N MRAM cells is closer to

M+12
than after the third write signal was provided to the N MRAM cells, providing the first value corresponding to the one or more pulses to such MRAM cells has a probability closer to about 0.5 (e.g., about 50 percent) to switch the resistive state of such MRAM cells from the first resistive state to the second resistive state than the second value corresponding to the one or more pulses. Because the second value corresponding to the one or more pulses is recorded for each of the N MRAM cells in which the average of the calculated total number of times the second resistive state was recorded after the third write signal was provided to the N MRAM cells is closer to

M+12
than after the second write signal was provided to the N MRAM cells, providing the second value corresponding to the one or more pulses to such MRAM cells has a probability closer to about 0.5 (e.g., about 50 percent) to switch the resistive state of such MRAM cells from the first resistive state to the second resistive state than the first value corresponding to the one or more pulses.

For example, with reference toFIG.2, for each of the MRAM cells100in which the average of the calculated total number of times the second resistive state was recorded after the second write signal was provided to the MRAM cells100is closer to

M+12
than after the third write signal was provided to the MRAM cells100, the tester bias circuitry216record (e.g., writes) the first value corresponding to the one or more pulses in a corresponding memory component word206. For each of the MRAM cells100in which the average of the calculated total number of times the second resistive state was recorded after the third write signal was provided to the MRAM cells100is closer to

M+12
than after the second write signal was provided to the MRAM cells100, the tester bias circuitry216records (e.g., writes) the second value corresponding to the one or more pulses in a corresponding memory component word206.

Further, in some embodiments, for one or more of the N MRAM cells, the average of the calculated total number of times the second resistive state was recorded after the second write signal was provided to the N MRAM cells may be the same as the average of the calculated total number of times the second resistive state was recorded after the third write signal was provided to the N MRAM cells. In such an embodiment, if the first value corresponding to the one or more pulses is less than the second value corresponding to the one or more pulses, the first value corresponding to the one or more pulses is recorded for such MRAM cells to increase the reliability of such MRAM cells. In further such embodiments, if the second value corresponding to the one or more pulses is less than the first value corresponding to the one or more pulses, the second value corresponding to the one or more pulses is recorded for such MRAM cells to increase the reliability of such MRAM cells.

For example, with reference toFIG.2, if the tester analysis circuitry218determines, for one or more of the MRAM cells100, the average of the calculated total number of times the second resistive state was recorded after the second write signal was provided to the MRAM cells100is the same as the average of the calculated total number of times the second resistive state was recorded after the third write signal was provided to the MRAM cells100, the tester analysis circuitry218compares the first value corresponding to the one or more pulses to the second value corresponding to the one or more pulses to determine whether the first value corresponding to the one or more pulses is less than the second value corresponding to the one or more pulses, or vice versa. If the first value corresponding to the one or more pulses is less than the second value corresponding to the one or more pulses, for each of the one or more MRAM cells100, the tester bias circuitry216records (e.g., writes) the first value corresponding to the one or more pulses in a corresponding memory component word206. If the second value corresponding to the one or more pulses is less than the first value corresponding to the one or more pulses, for each of the one or more MRAM cells100, the tester bias circuitry216records (e.g., writes) the second value corresponding to the one or more pulses in a corresponding memory component word206.

At430, after either the first value corresponding to the one or more pulses or second value corresponding to the one or more pulses is recorded for each of the N MRAM cells, the first write signal is provided to the N MRAM cells to set the resistive state of each of the N MRAM cells to the first resistive state. For example, with reference toFIG.2, the controller210provides the first write signal to the MRAM cells100to set their resistive states to the first resistive state.

At432, an N-bit random number is outputted by providing N random number generator (RNG) signals to the N MRAM cells, respectively. The N RNG signals comprise RNG values that correspond to one or more pulses of the N RNG signals, respectively. Further, each of the RNG values corresponding to the one or more pulses is either the first value corresponding to the one or more pulses or the second value corresponding to the one or more pulses depending on the value corresponding to the one or more pulses recorded in422or428for its respective MRAM cell.

For example, with reference toFIG.2, the controller210reads the memory component words206, each of which comprises either the first value corresponding to the one or more pulses or the second value corresponding to the one or more pulses for a corresponding one of the MRAM cells100. Subsequently, the controller210generates RNG signals, each of which corresponds to one of the MRAM cells100. The RNG signals comprise RNG values that corresponds to the one or more pulses of the N RNG signals, respectively. In some embodiments, for each of the memory component words206in which the controller210read the first value corresponding to the one or more pulses, the controller generates a corresponding RNG signal comprising a RNG value corresponding to the one or more pulses of the corresponding RNG signal that is the first value corresponding to the one or more pulses. In further embodiments, for each of the memory component words206in which the controller210read the second value corresponding to the one or more pulses, the controller generates a corresponding RNG signal comprising a RNG value corresponding to the one or more pulses of the corresponding RNG signal that is the second value corresponding to the one or more pulses.

The controller210then provides the RNG signals to the MRAM cells100, respectively. After the controller210provides the RNG signals to the MRAM cells100, the RNG output circuitry212reads the resistive states of the MRAM cells100, respectively. The probability that the RNG output circuitry212reads the resistive state of any of the MRAM cells100as the second resistive state is about 0.5 (e.g., about 50 percent). This is due to the controller210providing each of the MRAM cells100in which the first value corresponding to the one or more pulses was stored in its corresponding memory component word206a corresponding RNG signal comprising a RNG value corresponding to the one or more pulses that is the first value corresponding to the one or more pulses, and providing each of the MRAM cells100in which the second value corresponding to the one or more pulses was stored in its corresponding memory component word206a corresponding RNG signal comprising a RNG value corresponding to the one or more pulses that is the second value corresponding to the one or more pulses. Accordingly, the RNG output circuitry212may output an N-bit random number based on the RNG output circuitry212having a probability of about 0.5 to read the resistive state of each of the MRAM cells100as the second resistive state.

As stated above, in some embodiments, the IC200comprises the tester circuitry214. In such embodiments, the tester circuitry214may repeat402-430at predefined intervals. For example, the tester circuitry214may repeat402-430each time a random number is to be generated, may repeat402-430after a given number of random numbers have been generated, may repeat402-430after a given time interval, or the like. In some embodiments, the tester analysis circuitry218is configured to read and analyze the resistive states MRAM cells100each time402-430is repeated, and the tester bias circuitry216is configured to write data to the memory component204each time402-430is repeated. In further embodiments, by repeating402-430at the predefined intervals, the tester circuitry214may update the RNG values of the RNG signals to account for changes in the MRAM cells from real world usage (e.g., from generating random numbers).

Also stated above, in some embodiments, a semiconductor testing unit may comprise the tester circuitry214. In such embodiments, the tester circuitry214may only perform402-430a single time. For example, the semiconductor testing unit may be a fabrication tool located at a fab, and the tester circuitry214may perform402-430at the fab. In further such embodiments, the tester analysis circuitry218may read and analyze the resistive states of the MRAM cells100only one time, and the tester bias circuitry216may write data to the memory component204only one time. It will be appreciated that, in some embodiments, the semiconductor testing unit may comprise a first tester circuitry, and the IC200may comprise a second tester circuitry. In such embodiments, the first tester circuitry may perform402-430a first time, and the second tester circuitry may perform402-430at the predefined intervals after the IC200has left the fab.

FIGS.5A-5Cillustrate some more detailed embodiments of the probability trimming series418ofFIGS.4A-4Bbeing performed on a plurality of magnetoresistive random-access memory (MRAM) cells.

As shown inFIG.5A, a flowchart500illustrates some embodiments of the probability trimming loop412ofFIGS.4A-4B. The flowchart500illustrates a series of acts502a-517athat is performed on a plurality of MRAM cells503a-503d. Corresponding tables502b-517billustrate a data state (e.g., binary “0” or binary “1”) stored by each of the MRAM cells503a-503dafter the acts502a-517aare performed on the MRAM cells503a-503d, respectively. Each of the MRAM cells503a-503dmay respectively store a first data state “0,” which indicates a resistive state of the MRAM cell is a first resistive state, or store a second data state “1,” which indicates the resistive state of the MRAM cell is a second resistive state.

At502a, a first write signal SW1is provided to each magnetoresistive random-access memory (MRAM) cell of the plurality of MRAM cells503a-503d. In some embodiments, the MRAM cells503a-503dcomprise four MRAM cells (e.g., a 1stMRAM cell503a, a 2ndMRAM cell503b, a 3rdMRAM cell503c, and a 4thMRAM cell503d). It will be appreciated, however, that in other examples any number of MRAM cells can be included. As shown in a first table502b, providing the first write signal SW1to the MRAM cells503a-503dcauses the 1st MRAM cell503a, the 2ndMRAM cell503b, the 3rdMRAM cell503c, and the 4thMRAM cell503dto store the first data state “0.”

At504a, a second write signal SW2is provided to each of the MRAM cells503a-503d. As shown in a second table504b, providing the second write signal SW2to the MRAM cells503a-503dcauses the 1stMRAM cell503a, the 2ndMRAM cell503b, and the 4thMRAM cell503dto store the first data state “0.” On the other hand, providing the second write signal SW2to the MRAM cells503a-503dcauses the 3rdMRAM cell503cto store the second data state “1.”

At505a, after the second write signal SW2is provided to each of the MRAM cells503a-503d, the resistive state of each of the MRAM cells503a-503dis read and recorded. The resistive state of each of the MRAM cells503a-503dis read by reading the data state stored by each of the MRAM cells503a-503dbecause the first data state “0” indicates the first resistive state and the second data state “1” indicates the second resistive state. As shown in a third table505b, the first resistive state is recorded for the 1st MRAM cell503a, the 2ndMRAM cell503b, and the 4thMRAM cell503d, and the second resistive state is recorded for the 3rdMRAM cell503c.

At506a, the first write signal SW1is provided to each of the MRAM cells503a-503d. As shown in a fourth table506b, providing the first write signal SW1to the MRAM cells503a-503dcauses the 1st MRAM cell503a, the 2ndMRAM cell503b, the 3rdMRAM cell503c, and the 4thMRAM cell503dto store the first data state “0.”

At508a, a third write signal SW3is provided to each of the MRAM cells503a-503d. As shown in a fifth table508b, providing the third write signal SW3to the MRAM cells503a-503dcauses the 1stMRAM cell503a, the 2ndMRAM cell503b, and the 4thMRAM cell503dto store the first data state “0.” On the other hand, providing the third write signal SW3to the MRAM cells503a-503dcauses the 3rdMRAM cell503cto store the second data state “1.”

At509a, after the third write signal SW3is provided to each of the MRAM cells503a-503d, the resistive state of each of the MRAM cells503a-503dis read and recorded. As shown in a sixth table509b, the first resistive state is recorded for the 1stMRAM cell503a, the 2ndMRAM cell503b, and the 4thMRAM cell503d, and the second resistive state is recorded for the 3rdMRAM cell503c.

At510a, the first write signal SW1is provided to each of the MRAM cells503a-503d. As shown in a seventh table510b, providing the first write signal SW1to the MRAM cells503a-503dcauses the 1st MRAM cell503a, the 2ndMRAM cell503b, the 3rdMRAM cell503c, and the 4thMRAM cell503dto store the first data state “0.”

At512a, a fourth write signal SW4is provided to each of the MRAM cells503a-503d. As shown in an eighth table512b, providing the fourth write signal SW4to the MRAM cells503a-503dcauses the 1stMRAM cell503aand the 4thMRAM cell503dto store the first data state “0.” On the other hand, providing the fourth write signal SW4to the MRAM cells503a-503dcauses the 2ndMRAM cell503band the 3rdMRAM cell503cto store the second data state “1.”

At513a, after the fourth write signal SW4is provided to each of the MRAM cells503a-503d, the resistive state of each of the MRAM cells503a-503dis read and recorded. As shown in a ninth table513b, the first resistive state is recorded for the 1stMRAM cell503aand the 4thMRAM cell503d, and the second resistive state is recorded for the 2ndMRAM cell503band the 3rdMRAM cell503c.

At514a, the first write signal SW1is provided to each of the MRAM cells503a-503d. As shown in a tenth table514b, providing the first write signal SW1to the MRAM cells503a-503dcauses the 1st MRAM cell503a, the 2ndMRAM cell503b, the 3rdMRAM cell503c, and the 4thMRAM cell503dto store the first data state “0.”

At516a, a fifth write signal SW5is provided to each of the MRAM cells503a-503d. As shown in an eleventh table516b, providing the fifth write signal SW5to the MRAM cells503a-503dcauses the 1st MRAM cell503a, the 2ndMRAM cell503b, the 3rdMRAM cell503c, and the 4thMRAM cell503dto store the second data state “1.”

At517a, after the fifth write signal SW5is provided to each of the MRAM cells503a-503d, the resistive state of each of the MRAM cells503a-503dis read and recorded. As shown in a twelfth table517b, the second resistive state is recorded for the 1stMRAM cell503a, the 2ndMRAM cell503b, the 3rdMRAM cell503c, and the 4thMRAM cell503d.

As shown inFIG.5B, the probability trimming loop412is repeated (see, e.g.,FIG.4A—414) nine times (e.g., M=9).FIG.5Billustrates that after each time the probability trimming loop412is repeated, the resistive state of each of the MRAM cells503a-503dis read and recorded after the second write signal SW2, the third write signal SW3, the fourth write signal SW4, and the fifth write signal SW5are provided to the MRAM cells503a-503d, respectively. For example,FIG.5Billustrates a thirteenth table518and a fourteenth table520that illustrate the resistive states recorded for each of the MRAM cells503a-503dafter the probability trimming loop412was repeated the first time (e.g., M=1) and after the probability trimming loop412was repeated the ninth time (e.g., M=9), respectively.

As shown inFIG.5C, for each of the MRAM cells503a-503d, the total number of times the second data state “1” was recorded after the second write signal SW2, the third write signal SW3, the fourth write signal SW4, and the fifth write signal SW5were provided to the MRAM cells503a-503dare calculated (see, e.g.,FIG.4A—416). For example, a fifteenth table522illustrates that, after the probability trimming loop412was repeated nine times, the total number of times the second write signal SW2caused the 1stMRAM cell503ato store the second data state “1” was 4 times; the total number of times the third write signal SW3caused the 1stMRAM cell503ato store the second data state “1” was 5 times; the total number of times the fourth write signal SW4caused the 1stMRAM cell503ato store the second data state “1” was 6 times; and the total number of times the fifth write signal SW5caused the 1stMRAM cell503ato store the second data state “1” was 7 times.

Also shown inFIG.5C, the calculated total number of times the third write signal SW3caused the first MRAM cell503ato store the second data state “1” is

M+12
(illustrated by a box having thick borders inFIG.5C). Because the calculated total number of times the third write signal SW3caused the first MRAM cell503ato store the second data state “1” is

M+12,
the third write signal SW3has a probability of about 0.5 to cause the first MRAM cell503ato switch from storing the first data state “0” to storing the second data state “1.” Thus, the value corresponding to one or more pulses of the third write signal SW3(e.g., 1.2 Volts (V)) is recorded for the first MRAM cell503a(see, e.g.,FIG.4B—422). Further, based on similar reasoning, the value corresponding to one or more pulses of the fifth write signal SW5(e.g., 1.4 V) is recorded for the second MRAM cell503b, the value corresponding to one or more pulses of the fourth write signal SW4(e.g., 1.3 V) is recorded for the third MRAM cell503c, and the value corresponding to the one or more pulses of the third write signal SW3(e.g., 1.2 V) is recorded for the fourth MRAM cell503d.

In some embodiments, after the values corresponding to the one or more pulses of the write signals (e.g., SW2-SW5) are recorded for each of the MRAM cells503a-503d, the first write signal SW1is provided to each of the MRAM cells503a-503d, such that each of the MRAM cells503a-503dare storing the first data state “0” (see, e.g.,FIG.4B—430). Subsequently, RNG signals (see, e.g.,FIG.2—S1-SN) are provided to the MRAM cells503a-503d, respectively, to output a 4-bit random number (see, e.g.,FIG.4B—432). Each of the RNG signals corresponds to one of the MRAM cells503a-503d. Further, each of the RNG signals comprises an RNG value that corresponds to one or more pulses and has a probability of about 0.5 to switch the data state of its corresponding MRAM cell503a-503dfrom the first data state “0” to the second data state “1.” For example, the RNG value corresponding to the one or more pulses of the RNG signal that is provided to the first MRAM cell503ais the value corresponding to the one or more pulses of the third write signal SW3(e.g., 1.2 V), the RNG value corresponding to the one or more pulses of the RNG signal that is provided to the second MRAM cell503bis the value corresponding to the one or more pulses of the fifth write signal SW5(e.g., 1.4 V), the RNG value corresponding to the one or more pulse of the RNG signal that is provided to the third MRAM cell503cis the value corresponding to the one or more pulses of the fourth write signal SW4(e.g., 1.3 V), and the RNG value corresponding to the one or more pulses of the RNG signal that is provided to the fourth MRAM cell503dis the value corresponding to the one or more pulses of the third write signal SW3(e.g., 1.2 V).

Accordingly, in some embodiments, after the RNG signals are provided to the MRAM cells503a-503d, respectively, the 4-bit random number is output by reading the data states of the MRAM cells503a-503d. For example, because the RNG value corresponding to the one or more pulses of each of the RNG signals has a probability of about 0.5 to switch the data state of its corresponding MRAM cell503a-503dfrom the first data state “0” to the second data state “1,” the probability of reading the second data state “1” (or the first data state “0”) for the first MRAM cell503a, the second MRAM cell503b, the third MRAM cell503c, or the fourth MRAM cell503dis about 0.5. Because the probability of reading the second data state “1” (or the first data state “0”) for each of the MRAM cells503a-503dis about 0.5, the 4-bit random number may be output by reading the data states of the MRAM cells503a-503d.

In some embodiments, the present application provides a method for generating a random bit. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell a first time, where the RNG signal has a probability of about 0.5 to switch a resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is read from the MRAM cell.

In other embodiments, the present application provides an integrated chip (IC). The IC includes a random number generator (RNG) comprising N magnetoresistive random-access memory (MRAM) cells, where N is a number greater than or equal to 1. One of the N MRAM cells is configured to switch between a first resistive state and a second resistive state. The IC also includes a memory component configured to store N RNG values, where one of the N RNG values has a probability of about 0.5 to switch a resistive state of the one of the N MRAM cells from the first resistive state to the second resistive state. A controller is coupled to each of the N MRAM cells and the memory component. The controller is configured to read the N RNG values and generate N RNG signals, respectively, where one of the N RNG signals comprises the one of the N RNG values. Further, the controller is configured to provide the N RNG signals to the N MRAM cells, respectively, where the one of the N RNG signals is provided to the one of the N MRAM cells. RNG output circuitry is coupled to the N MRAM cells, where the RNG output circuitry is configured to read the resistive state of each of the N MRAM cells and output an N-bit random number based on the read resistive states of the N MRAM cells.

In yet other embodiments, the present application provides a method for generating an N-bit random number. The method includes setting a resistive state of each of the N magnetoresistive random-access memory (MRAM) cells to a first resistive state, where each of the N MRAM cells is configured to switch between the first resistive state and a second resistive state, and where N is a number greater than or equal to 1. An N-bit random number is generated by providing N random number generator (RNG) signals to the N MRAM cells, respectively, where each of the N RNG signals comprises a RNG value that has a probability of about 0.5 to switch the resistive state of each one of the N RNG signals respective MRAM cell from the first resistive state to the second resistive state.