Method and system for safe and efficient chip power down drawing minimal current when a device is not enabled

Certain embodiments of a method and system for safe and efficient power down and drawing minimal current when a device is not enabled may comprise receiving within a network adapter chip (NAC) a signal that indicates a reduced power mode. Based on this signal, the NAC may control an off-chip voltage source that provides reduced voltage to circuitry within the NAC. The off-chip voltage source, which may comprise a first PNP transistor and a second PNP transistor, may reduce a voltage to a first voltage and a second voltage. The NAC may also reduce current through the off-chip voltage source to approximately zero amperes and an output voltage of the off-chip voltage source to approximately zero volts. The first voltage and/or the second voltage may be fed back to control the output voltage and current of the off-chip voltage source.

This application also makes reference to:

Each of the above stated applications is hereby incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to integrated circuits or chips. More specifically, certain embodiments of the invention relate to a method and system for safe and efficient chip power down drawing minimal current when a device is not enabled.

BACKGROUND OF THE INVENTION

It is desirable to be able to completely power down a device when it is not in use or when it is disabled. For example, a notebook computer may have a wired LAN adapter and a wireless LAN adapter installed. When the notebook computer is moved from one location to another, the wireless LAN adapter may be used, for example, when there is no wired LAN available. As a result, the wired LAN adapter may not be needed. Accordingly, the wired LAN adapter may be disabled to reduce power consumption, which conserves battery power.

Some conventional systems may configure the wired LAN adapter to operate in a power down state by disabling clock signals, turning off transceivers, and/or configuring analog devices to operate in a standby state. However, there may still be some current drawn from a power supply. For example, a network adapter device (NAC) may have three primary supply voltages: 1.2V, 2.5V, and 3.3V. When the NAC is configured to operate in the power down state by asserting, for example, a LOW_POWER_MODE pin, the lowest measured current may be, for example, about 27 mA. This may translate to over 100 mW of power consumption during the power down state when the current is regulated down from the 5V supply in the system.

The NAC may derive the other supply voltages of 2.5V and 1.2V from the 3.3V supply voltage. In order to avoid this power drain from the 2.5V and 1.2V supply voltages, as well as from the 3.3V supply voltage, some conventional systems may turn off the 3.3V supply to the NAC. A disadvantage with this approach may be that turning off the 3.3V supply voltage to the NAC may affect long-term reliability of the NAC because it may stress damage the I/O cells in the NAC. This may also lead to leakage current through the non-powered I/O cells to which the NAC may be coupled. The resulting power drain at the system level may be greater than if the 3.3V supply voltage to the NAC was not turned off.

BRIEF SUMMARY OF THE INVENTION

A system and/or method is provided for safe and efficient chip power down drawing minimal current when a device is not enabled, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and system for safe and efficient chip power down drawing minimal current when a device is not enabled. Aspects of the method may comprise receiving within a network adapter chip a signal that indicates a reduced power mode. Based on the signal indicating the reduced power mode, the network adapter chip may control an off-chip voltage source that provides reduced voltage to circuitry within the network adapter chip. The off-chip voltage source may comprise at least a first transistor and a second transistor configured to supply various voltages to the network adapter chip.

The first transistor, which may be a PNP transistor, may reduce a voltage at an emitter of the first transistor to a first voltage at a collector of the first transistor. The first voltage may be supplied to circuitry that requires the first voltage. Similarly, the second transistor, which may be a PNP transistor, may reduce a voltage at an emitter of the second transistor to a second voltage at a collector of the second transistor. The second voltage may be supplied to circuitry that requires the second voltage.

A current through the off-chip voltage source may be reduced to approximately zero amperes based on the signal indicating the reduced power mode. The voltage at the output of the off-chip voltage source, for example, the first voltage and/or the second voltage, may be reduced to approximately zero volts based on the signal indicating the reduced power mode. The reduced voltage, for example, the first voltage and/or the second voltage, may be fed back for controlling the off-chip voltage source, for example, the first transistor and/or the second transistor, from within the network adapter chip.

FIG. 1is a block diagram illustrating an exemplary network adapter card, which may be utilized in connection with an embodiment of the invention. Referring toFIG. 1, there is shown a laptop100with a few of the internal components, for example, a memory block103, a CPU105, a chipset107, and a network adapter chip (NAC)109. The CPU105may communicate with the memory block103and the chipset107, and the chipset107may communicate with the NAC109. The NAC109may be physically connected to a network, such as, for example, an Ethernet network, via a cable. In this manner, the NAC109may transmit data to the network and receive data from the network.

The memory block103may comprise suitable logic, circuitry, and/or code that may be adapted to store a plurality of control, status and/or data information. The information stored in memory block103may be accessed by other processing blocks, for example, the CPU105.

The CPU105may comprise suitable logic, circuitry, and/or code that may be adapted to process data that may be read from, for example, the memory block103. The CPU may store data in the memory block103, and/or communicate data, status, and/or commands with other devices in the laptop, for example, the chipset107and/or the NAC109.

The chipset107may comprise suitable logic, circuitry, and/or code that may be adapted to manage input/output data such as voice and/or data traffic from the CPU to the memory block103and/or peripheral devices, for example, the NAC109.

The NAC109may comprise suitable logic, circuitry, and/or code that may be adapted to physically interface to the network, for example, the Ethernet network, via a cable. Accordingly, the laptop100may send and receive data to and from the Ethernet network.

In operation, the CPU105may communicate data to the NAC109for transmission to a network destination. Data may be received from a network source, for example, an external computer that may also be on the network, and the NAC109may indicate to the CPU105the availability of the received data. The CPU105may then process the data and/or save the data in the memory block103.

FIG. 2ais a block diagram illustrating an exemplary physical layer device and media access controller, which may be utilized in connection with an embodiment of the invention. Referring toFIG. 2a, there is shown the NAC109that may comprise a physical network interface layer (PHY)212and a media access controller (MAC)214.

The PHY212may comprise suitable logic, circuitry, and/or code that may be adapted to interface to a network, for example, an Ethernet network. For example, the PHY212may be fully compatible with at least IEEE 802.3 standard for auto-negotiation of data transfer speed, where the IEEE 802.3 may be the IEEE standard for Ethernet.

The MAC214may comprise suitable logic, circuitry, and/or code that may be adapted to properly format data for packet transmission on, for example, the Ethernet network. The MAC214may also be adapted to receive data from the Ethernet network and to remove the Ethernet network related frame information so that higher level protocols may extract desired information from the received frame.

In operation, the PHY212may communicate data with the network via a transmit and receive interface217. The transmit and receive interface217may comprise a serial transmit interface216and a serial receive interface218. The PHY212may receive Ethernet network data via the serial receive interface218, and transmit data to the Ethernet network via the serial transmit interface216. The PHY212may sense collision when transmitting data and may comply with the Carrier Sense Multiple Access/Collision Detect (CSMA/CD) access method defined in IEEE 802.3

The MAC214may receive data from, for example, the CPU105(FIG. 1), and form appropriate frames for the Ethernet network, for example. The MAC214may communicate the frames to the PHY212via the interface213between the PHY212and the MAC214. Additionally, the MAC214may receive data from the Ethernet network via the PHY212. The MAC214may remove the network related information, for example, the Ethernet protocol information, and may communicate the remaining data to, for example, the CPU105via, for example, a general purpose I/O (GPIO) interface210. The CPU105may process the received frame to retrieve data that may have been sent by another application on the network. The GPIO bus210may be a general bus interface defining various pins, which may be configurable, for input and/or output usage, an interface that uses the GPIO standard, or a PCI or PCI-X interface. The particular definition of pin-outs for bus signals may be design and/or implementation dependent.

FIG. 2bis a block diagram of an exemplary Ethernet transceiver module and a media access controller, in accordance with an embodiment of the invention. Referring toFIG. 2b, there is illustrated the chipset107, the network adapter chip (NAC)109, and a network280. The NAC109may comprise the MAC214and a transceiver module220. The transceiver module220may comprise the PHY212, an electrically erasable programmable read only memory (EEPROM)240, and a physical medium dependent (PMD) transceiver225. The PMD transceiver225may comprise a PMD transmitter225aand a PMD receiver225b. The chipset107may interface with the MAC214through the GPIO bus210and may communicate with the network280through the transceiver module220. The network280may be an electrical and/or optical network. The PMD transmitter225aand a PMD receiver225bmay not be needed in cases when the network280is an electrical network.

Transceiver module220may be configured to communicate data between the chipset107and the network280. The data transmitted and/or received may be formatted in accordance with the well-known OSI protocol standard. The OSI model partitions operability and functionality into seven distinct and hierarchical layers. Generally, each layer in the OSI model is structured so that it may provide a service to the immediately higher interfacing layer. For example, a layer1may provide services to a layer2and the layer2may provide services to a layer3. A data link layer, the layer2, may include a MAC layer whose functionality may be handled by the MAC214. In this regard, the MAC214may be configured to implement the well-known IEEE 802.3 Ethernet protocol.

In an embodiment of the invention, the MAC214may represent the layer2and the transceiver module220may represent the layer1. The layer3and above may be represented by a CPU, for example, the CPU105(FIG. 1), which may be accessed from the NAC109via the chipset107. The CPU105may be configured to build five highest functional layers for data packets that are to be transmitted over the network280. Since each layer in the OSI model may provide a service to the immediately higher interfacing layer, the MAC214may provide the necessary services to the CPU105to ensure that packets are suitably formatted and communicated to the transceiver module220. During transmission, each layer may add its own header to the data passed on from the interfacing layer above it. However, during reception, a compatible device having a similar OSI stack may strip off the headers as the message passes from the lower layers up to the higher layers.

The transceiver module220may be configured to handle all the physical layer requirements, which may include, but is not limited to, packetization, data transfer and serialization/deserialization (SerDes). The transceiver module220may operate at a plurality of data rates, which may include 10 Mbps, 100 Mbps and 1 Gbps, for example. Data packets received by the transceiver module220from the MAC214may include data and header information for each of the above six functional layers. The transceiver module220may be configured to encode data packets that are to be transmitted over the network280. The transceiver module220may also be configured to decode data packets received from the network280.

The MAC214may interface with the PHY212through, for example, the interface213. The interface213may be a low pin count, self-clocked bus. The interface213may act as an extender interface for a media independent interface (XMGII). In this regard, MAC214may also include a reconciliation sublayer (RS) interface250and an XGMII extender sublayer (XGXS) interface255. The MAC214may also include an integrated link management (MGMT) interface260that may facilitate communication between the MAC214and a management data input/output (MDIO) interface of the PHY212.

The PMD transceiver225may include at least one PMD transmitter225aand at least one PMD receiver225b. In operation, PMD transceiver225may be configured to receive data from and transmit data to the network280. The PMD transmitter225amay transmit data originating from the CPU105. The PMD receiver225bmay receive data destined for the CPU105from the network280and transmit the data to the CPU105via the chipset107. The PMD225may also be configured to function as an electro-optical interface. In this regard, electrical signals may be received by PMD transmitter225aand transmitted in a format such as optical signals over the network280. Additionally, optical signals may be received by PMD receiver225band transmitted as electrical signals to the chipset107.

The transceiver module220may also include an EEPROM240. The PHY212may be coupled to the EEPROM240through an interface such as a serial interface or bus. The EEPROM240may be programmed with information such as, for example, parameters and/or code that may effectuate the operation of the PHY212. The parameters may include configuration data and the code may include operational code such as software and/or firmware, but the information is not limited in this regard.

FIG. 3is a block diagram illustrating exemplary communication from a chipset to a physical layer device for power save mode, which may be utilized in connection with an embodiment of the invention. Referring toFIG. 3, there is shown the chipset107, the NAC109, a communication block_1320, and a communication block_2330. The NAC109may comprise a signal detector312.

The communication block_1320and the communication block_2330may comprise logic, circuitry, and/or code that may be adapted to allow the laptop100(FIG. 1) to communicate with external devices. For example, the communication block_1320may be a wireless network interface adhering to the IEEE 802.11g standard for wireless networks, and the communication block_2330may be a 56 Kbps modem.

The signal detector312may comprise circuitry, logic and/or code that may be adapted to detect network activity, for example, Ethernet signals, that may be communicated to the signal detector312via the serial receive interface218. If network activity is detected, the signal detector312may, for example, assert a network activity detected signal Energy_Detect. If the signal detector312does not detect network activity, it may de-assert, for example, the network activity detected signal Energy_Detect.

In operation, the signal detector312may detect when no network data is being received via the serial receive interface218. This may be due to the laptop100using the communication block_1320or the communication block_2330for wireless network access or modem access, respectively. Accordingly, the signal detector312may communicate the lack of wired network data to the CPU105(FIG. 1) via the chipset107. The CPU105may communicate a signal to the NAC109, via the chipset107, which may indicate when the NAC109may enter a reduced power state.

The NAC109may supply power to the signal detector312even in the reduced power state. This may be so that the signal detector312may be able to detect when network data is being received via the serial receive interface218. When network data is detected, the signal detector312may communicate the detection to the CPU105via the chipset107. The CPU105may communicate a signal to the NAC109, via the chipset107, which may indicate that the NAC109may power up in order to allow the laptop100to connect to the wired LAN.

The NAC109may support a plurality of power states that may be dependent on a user set power configuration and/or system power considerations. For example, entering the reduced power state may depend on whether the laptop100is powered by AC power or by DC power from a battery. If AC power is being used by the laptop100, the laptop100may not be required to enter into a reduced power state since there may be no perceived need to save power. The laptop100may also enter a reduced power state after a certain amount of time has elapsed. The elapsed time may be a default value, for example, 10 minutes, and/or may be settable by the laptop100user.

However, if DC power is being used, an embodiment of the invention may power down the NAC109when it is determined that no network data is detected. Generally, one of a plurality of methods may be used to power down the NAC109. For example, one method may comprise disabling clock signals, turning off transceivers, and/or putting analog devices into a standby state. Another method may comprise reducing a supply voltage to the NAC109that may be used as a supply voltage by the NAC109, and from which it may generate other supply voltages. In an exemplary embodiment of the invention, the NAC109may receive a 3.3V supply voltage and generate a 2.5V supply voltage and 1.2V supply voltage from the 3.3V supply voltage. This may be accomplished with a voltage divider circuit that may use passive devices and/or active devices such as transistors. Accordingly, when the NAC109is to be powered down, the 3.3V supply voltage may be reduced to substantially zero volts.

In various embodiments of the invention, the NAC109may generate the required lower voltage supply voltages, for example, 2.5V and 1.2V supply voltages, from, for example, the 3.3V supply voltage. This may be described in more detail with respect toFIG. 4. However, if the NAC109is powered down, the 3.3V supply voltage may still be supplied to the NAC109, but the NAC109may reduce the 2.5V and 1.2V supply voltages to substantially zero volts. Additionally, the currents to the circuitry that may require the 2.5V and 1.2V supply voltages may be reduced to substantially zero amperes. This may be further described with respect toFIG. 4.

FIG. 4is a block diagram illustrating an exemplary off-chip voltage source, in accordance with an embodiment of the invention. Referring toFIG. 4, there is shown the NAC109, and a voltage source417that may comprise PNP transistors418and420. The NAC109may comprise a regulator control block412, 2.5V circuitry414, and 1.2V circuitry416.

The regulator control block412may use 3.3V supply voltage as its supply voltage and may generate a 2.5V control signal and a 1.2V control signal that may be communicated to bases of the PNP transistors418and420, respectively. The 3.3V supply voltage may be coupled to an emitter of each of the PNP transistors418and420. Collectors of the PNP transistors418and420may have as outputs the 2.5V and 1.2V supply voltages, respectively. The 2.5V supply voltage may be communicated to the 2.5V circuitry414on the NAC109, which may require the 2.5V supply voltage. Similarly, the 1.2V supply voltage may be communicated to the 1.2V circuitry416on the NAC109, which may require the 1.2V supply voltage. Accordingly, the PNP transistors418and420may be part of an off-chip voltage source417, where the NAC109may not comprise the PNP transistors418and420.

The 2.5V control signal may indicate to the transistor418to reduce the 3.3V supply voltage to 2.5 volts or to reduce the voltage to zero volts. Similarly, the 1.2V control signal may control the transistor420so as to reduce the 3.3V supply voltage to 1.2 volts or to reduce the voltage to zero volts. Additionally, the 2.5V and 1.2V supply voltages may also be fed back to the regulator control block412to assist in regulating the 2.5V and 1.2V supply voltages, respectively. Accordingly, the 2.5V and 1.2V supply voltages to the 2.5V circuitry414and the 1.2V circuitry416, respectively, may be communicated to the regulator control block412.

A Power_Down signal, which may be communicated from the chipset107, for example, via the GPIO interface210, may cause the NAC109to power down. Assertion of the Power_Down signal to indicate power down of the NAC109may be via a dedicated pin Power Down on the regulator control block412. As a result, very little, if any, current may be conducted to the 1.2V circuitry416and the 2.5V circuitry414. The regulator block412may consume a little current from the 3.3V supply voltage for the circuitry that may control the PNP transistors418and420. Additionally, since there is no input or output signals from the NAC109, except for the Power_Down signal, there may be very little power, if at all, from the 3.3V supply voltage used for the input or output of signals.

The system may re-enable the NAC109by deasserting the Power_Down pin. This may occur, for example, if a laptop100user enables operation of the NAC109by allowing connection to a network, for example, an Ethernet network. In response, the regulator control block412may generate appropriate voltage levels for the 1.2V control signal and the 2.5V control signal communicated to the base of the PNP transistors420and418, respectively. Accordingly, the voltage and current from the PNP transistors418and420may be turned on and off as needed.

FIG. 5is a flow diagram illustrating an exemplary routine for power saving mode, in accordance with an embodiment of the invention. Referring toFIG. 5, and with respect toFIG. 4, there is shown a plurality of steps510to540that may be utilized to power down and power up a chip, for example, the NAC109. In step510, a signal, for example, the signal Power_Down (FIG. 4), may be received by the regulator control block412. An asserted state of the signal Power_Down may indicate that the 1.2V and 2.5V supply voltages may need to be turned off to the 1.2V circuitry416and the 2.5V circuitry414, respectively. A de-asserted state of the signal Power_Down may indicate that the 1.2V and 2.5V supply voltages may need to be turned on to the 1.2V circuitry416and the 2.5V circuitry414, respectively.

In step520, the received signal Power_Down may indicate that the 1.2V control signal and the 2.5V control signal may be adjusted to turn off the voltage source417. Accordingly, the 1.2V and 2.5V supply voltages may be reduced to substantially zero volts, and substantially zero amperes of current may flow through the PNP transistors418and420. Accordingly, the 1.2V circuitry416and the 2.5V circuitry414may be in a powered-down state.

In step530, the received signal Power_Down may indicate that the 1.2V control signal and the 2.5V control signal may be adjusted to turn on the voltage source417. Accordingly, the 1.2V and 2.5V control signals may turn on the PNP transistors418and420, and the voltages at the collectors of the PNP transistors418and420may be substantially 2.5 volts and 1.2 volts, respectively. Accordingly, the 1.2V circuitry416and the 2.5V circuitry414may be in a powered-on state.

In step540, the 1.2V and 2.5V supply voltages communicated to the 1.2V circuitry416and the 2.5V circuitry414, respectively, may be fed back to the regulator control block. The 1.2V and 2.5V supply voltages may be used to control the 1.2V and 2.5V control signals, respectively, in order to keep the outputs of the PNP transistors418and420at the desired voltage level. For example, substantially zero volts when the PNP transistors418and420are turned off, or substantially 2.5 volts and 1.2 volts when the PNP transistors418and420, respectively, are turned on.

Although embodiments of the invention may have been described where the voltage source417may be PNP transistors, for example, the PNP transistors418and420, the invention need not be so limited. For example, the voltage source417may comprise NPN transistors, and/or MOS transistors, and/or circuits using active and/or passive parts.

The network adapter chip (NAC)109(FIG. 4) may receive a signal, for example, the Power_Down signal, which may indicate a reduced power mode. Based on the signal indicating the reduced power mode, the NAC109may control the voltage source417(FIG. 4) that may be off-chip, which may provide reduced voltage to circuitry within the NAC109. The off-chip voltage source, which may be the voltage source417, may comprise at least a first transistor, which may be the transistor418(FIG. 4), and a second transistor, which may be the transistor420(FIG. 4), that may be configured to supply various voltages to the NAC109.

The transistor418, which may be a PNP transistor, may reduce a voltage at an emitter of the transistor418to a first voltage at a collector of the transistor418. The first voltage may be supplied to circuitry that requires the first voltage, for example, the 2.5V circuitry414(FIG. 4). Similarly, the transistor420, which may be a PNP transistor, may reduce a voltage at an emitter of the transistor420to a second voltage at a collector of the transistor420. The second voltage may be supplied to circuitry that requires the second voltage, for example, the 1.2V circuitry416(FIG. 4).

A current through the voltage source417may be reduced to approximately zero amperes based on a signal, for example, the Power_Down signal (FIG. 4), indicating the reduced power mode. The voltage at the output of the off-chip voltage source417, for example, the first voltage and/or the second voltage, may be reduced to approximately zero volts based on the signal, for example, the Power_Down signal, indicating the reduced power mode. The reduced voltage, for example, the first voltage and/or the second voltage, may be fed back for controlling the voltage source417, for example, the transistor418and/or the transistor420, from within the NAC109.