Vertical LED chip package on TSV carrier

A method of forming a light-emitting device (LED) package component includes providing a substrate; forming an LED on the substrate; and lifting the LED off the substrate. A carrier wafer is provided, which includes a through-substrate via (TSV) configured to electrically connecting features on opposite sides of the carrier wafer. The LED is bonded onto the carrier wafer, with the LED electrically connected to the TSV.

TECHNICAL FIELD

This disclosure relates generally to light-emitting device (LED) package components, and more particularly to vertical LED packages including through-substrate vias (TSVs).

BACKGROUND

In recent years, optical devices, such as light emitting diodes (LEDs), laser diodes, and UV photo-detectors have increasingly been used. Group-III nitride compounds, such as gallium nitride (GaN) and its related alloys have been known suitable for the formation of the optical devices. The large bandgap and high electron saturation velocity of the group-III nitride compounds also make them excellent candidates for applications in high-temperature and high-speed power electronics.

Due to the high equilibrium pressure of nitrogen at typical growth temperatures, it is extremely difficult to obtain GaN bulk crystals. Therefore, GaN layers and the respective LEDs are often formed on other substrates that match the characteristics of GaN. Sapphire (Al2O3) is a commonly used substrate material.FIG. 1illustrates a cross-sectional view of a package component including LED2. LED2, which includes a plurality of GaN-based layers, is formed on sapphire substrate4. Sapphire substrate4is further mounted on lead frame6. LED2further includes electrodes8and10electrically connected to lead frame6through gold wires12.

Because sapphire has a low thermal conductivity, heat generated by LED2cannot be dissipated through sapphire substrate4efficiently. The heat needs to be dissipated through the top end of LED2, and through gold wires12. However, since gold wires12are relatively long since they have to extend to lead frame6, the thermal conductivity through gold wires12is also low. In addition, electrodes8and10occupy chip area, and hence the LED light output area is not optimized.

SUMMARY

In accordance with one aspect, a method of forming a light-emitting device (LED) package component is provided, including forming an LED on a substrate; and lifting the LED off the substrate. A carrier wafer is provided that includes a through-substrate via (TSV) configured to electrically connect features on opposite sides of the carrier wafer. The LED is bonded onto the carrier wafer, with the LED electrically connected to the TSV.

Other embodiments are also disclosed.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A novel light-emitting device (LED) package component and the method of forming the same are presented. The intermediate stages of manufacturing an embodiment are illustrated. The variations of the embodiment are then discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIG. 2illustrates wafer100, which includes LED22formed on substrate20. In an embodiment, substrate20is formed of sapphire (Al2O3), although it may also be formed of other materials having characteristics close to the characteristics of the LED formed thereon (which may comprise group-III and group-V elements, or also known as III-V compound semiconductor materials).

Un-doped gallium nitride (u-GaN) layer24or another heat sensitive material is formed above, and possibly contacts, substrate20. In an embodiment, u-GaN layer24is substantially free from elements other than Ga and N. LED22is formed on top of, and may possibly contact, u-GaN layer24. LED22may include a plurality of layers. Accordingly to various embodiments, LED22includes at least one multiple quantum well (MQW), a first group-III nitride (III-nitride) layer doped with a first impurity of a first conductivity type under the MQW, and a second III-nitride layer doped with a second impurity of a second conductivity type opposite the first conductivity type over the MQW. The group-III nitride layers are each connected to a TSV in the carrier wafer.

In an exemplary embodiment, LED22includes n-GaN layer (GaN doped with an n-type impurity)26, multiple quantum well (MQW)28, p-GaN layer (GaN doped with a p-type impurity)30, reflector32, and top electrode34. Reflector32may be formed of an indium tin oxide (ITO), for example. MQW28may be formed of, for example, InGaN, and acts as an active layer for emitting light. The formations of layers26,28,30,32, and34are known in the art, and hence are not disclosed in detail herein. In an exemplary embodiment, the formation methods of layers26,28,30, and32may include epitaxial growth. It is realized that LED22may have many designs, andFIG. 2only shows an exemplary version among the available variations. For example, the materials of each of the layers26,28,30, and32may be different from the above-discussed material, and may be ternary III-V compound semiconductor materials. Also, the positions of n-GaN layer26and p-GaN layer30may be swapped.

LED22as shown inFIG. 2may represent a plurality of LEDs, each comprising one electrode34, although only one LED22is illustrated. Referring toFIG. 3, LED(s)22are lifted off substrate20. In an exemplary embodiment, substrate20is exposed to light energy, for example, a laser beam (symbolized by arrows), projecting from the bottom of substrate20. The laser beam penetrates through substrate20to layer24. As a result, layer24is decomposed by the heat resulting from the laser beam, and hence LED(s)22are separated from substrate20. In an embodiment, the laser is a KrF laser with a wavelength of about 248 nm. After the lift-off, LEDs22are separated from each other, with each of LEDs22including one electrode34.

Referring toFIG. 4A, carrier wafer40is provided. Carrier wafer40may comprise substrate48, which may be a semiconductor substrate, such as a silicon substrate, or may be a dielectric substrate. Through-substrate vias (TSVs)42(denoted as42A and42B) are formed in substrate48and electrically connect features on opposite sides of carrier wafer40. TSVs42may comprise copper or other metals, such as tungsten, or alloys thereof. Solder balls46may be mounted on one side of substrate48and on TSVs42. On each side of carrier wafer40, filled TSVs42may protrude out of the surface slightly. Alternatively, bond pads (such as bond pads44) may be formed on filled TSVs42.

In various embodiments, carrier wafer40includes active circuits therein, as is schematically illustrated inFIG. 4B. In these embodiments, carrier wafer40may comprise a semiconductor substrate, such as a silicon substrate (denoted as48′). Accordingly, TSVs42may be through-silicon vias. An exemplary active circuit (symbolized by an MOS device)50is schematically shown as being formed at the surface of semiconductor substrate48′. Active circuit50may include CMOS devices (PMOS devices and NMOS devices), capacitors, diodes, or the like. Active circuit50may also include desirable CMOS circuits such as electro-static discharge (ESD) circuits/devices, which may be used to protect the optical devices mounted thereon, and/or driver circuits, for example, for driving the LEDs bonded on carrier wafer40. Inter-metal dielectric (IMD) layers52may be formed over active circuit50. Metal lines and vias (not shown) may be formed in IMD layers52to interconnect the devices in active circuit50. In alternative embodiments, no active circuit is formed in carrier wafer40.

Referring toFIG. 5, a plurality of LEDs22is bonded onto carrier wafer40. The adhesion of LEDs22to carrier wafer40may be achieved through conductive thermal interface material (TIM) layer56. In an embodiment, each of conductive TIM layers56has a similar size as that of LED22. In alternative embodiments, conductive TIM layer56includes a plurality of discrete components, each corresponding to one of TSVs42B and/or the bond pad formed thereon. Conductive TIM layers56may be formed of solder, metals, conductive organic materials, or the like, providing the materials have electrical and thermal conductivities suitable for LED operation. The bonding between LEDs22onto carrier wafer40may be performed through the reflow of the solder or through direct metal-to-metal bonding, depending on the materials of conductive TIM layers56.

With LEDs22being bonded onto carrier wafer40, n-GaN layers26in LEDs22are electrically connected to TSVs42B and solder balls46through respective conductive TIM layers56. Accordingly, solder balls46may be used to conduct a voltage to LEDs22. Further, the heat generated in LED22may be conducted to carrier wafer40through the respective conductive TIM layers56.

FIG. 6illustrates the wire-bonding of electrodes34to bond pads44, wherein conductive wires58are used to electrically connect electrodes34to TSVs42A. Conductive wires58may be gold wires or copper wires although they may also be formed of other metallic materials. Referring toFIG. 7, silicone lenses60are molded onto LEDs22. The molding of silicone lenses60is known in the art, and hence is not disclosed in detail herein. Each of silicone lenses60may cover the respective LEDs22and wires58.

Carrier wafer40may then be diced or sawed along scribe lines62, so that LED package components are separated individually. Blades or laser may be used to dice or saw the carrier wafer. Accordingly, carrier wafer40is separated into a plurality of carrier chips, with each being bonded to one of LEDs22. It is noted that in the above-discussed embodiments, the bonding of LEDs22and the wire bonding are performed at wafer level before carrier wafer40is diced or sawed. In alternative embodiments, the bonding of LEDs22and the wire bonding are performed at chip level after carrier wafer40is diced. In these alternative embodiments, one LED22is bonded onto a carrier chip that has already been sawed from carrier wafer40.

As shown inFIG. 7, the electrical connection to the bottom of LED22is made through TSVs42B. Accordingly, the LED light output area is increased since the connection to n-GaN layer26no longer requires additional chip area. Further, carrier wafer40has significantly higher thermal conductivity than a sapphire substrate, partially due to the conductive TIM layers56, silicon (in substrate48), and the plurality of TSVs42B (which may be formed of copper) all having higher thermal conductivities than sapphire. The thermal conductivity of carrier wafer40may be ten times higher than that of a sapphire substrate or even higher. The electrical conductivity to LED22may also be improved by using a plurality of TSVs42B.