Data processing systems and a plurality of memory modules

A data processing system may include a memory/storage circuit and a host. The memory/storage circuit may include a first memory module and a second memory module. Each of the first and second memory modules may include a controller and a memory device. The host may have access to the memory device of the first memory module and the memory device of the second memory module. Each of the controllers included in the first and second memory modules may be configured to selectively perform any one of a memory operation and a storage operation according to a request of the host.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. 119(a) to Korean Application No. 10-2016-0089127, filed on Jul. 14, 2016, which is herein incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments of the present disclosure may generally relate to data processing systems and, more particularly, to data processing systems relating to memory modules.

2. Related Art

Semiconductor memory devices may be categorized as either volatile memory devices or nonvolatile memory devices. This categorization depends on whether data can be retained without a power supply. As the semiconductor memory devices become smaller and more highly integrated, dynamic random access memory (DRAM) devices among the volatile memory devices and NAND flash memory devices among the nonvolatile memory devices have been widely used. In general, the nonvolatile memory devices may be used as storage media for storing data.

The DRAM devices have to be designed to perform a power-down operation and a refresh operation because of the nature of memory cells. For example, the DRAM devices may operate in a power-down mode to reduce power consumption while the DRAM devices are put into an idle state and may operate in a refresh mode to prevent data stored in cell capacitors of memory cells from being lost due to a leakage current characteristic of the cell capacitors.

The NAND flash memory devices do not provide and support an overwrite function unlike hard disk drives. Thus, the NAND flash memory devices have to perform an erasure-before-write operation in unit of blocks and have to perform a background operation according to their inherent characteristic. In general, the background operation may include a garbage collection operation (e.g., a merging operation, a compaction operation or the like) for efficiently processing valid pages and invalid pages of the NAND flash memory devices and a wear-leveling operation for equalizing wear-levels of memory cells of the NAND flash memory devices.

As described above, since the DRAM device and the NAND flash memory device perform different operations due to their own characteristics, a data processing system including both the DRAM device and the NAND flash memory device has to employ different memory modules and different interfaces to complete these different operations.

SUMMARY

According to an embodiment, a data processing system may include a memory and storage (memory/storage) circuit and a host. The memory/storage circuit may include a first memory module and a second memory module. Each of the first and second memory modules may include a controller and a memory device. The host may have access to the memory device of the first memory module and the memory device of the second memory module. Each of the controllers included in the first and second memory modules may be configured to selectively perform any one of a memory operation and a storage operation according to a request of the host.

According to an embodiment, a data processing system may include a memory/storage circuit and a host. The memory/storage circuit may include a first memory module group and a second memory module group. Each of the first and second memory module groups may include a plurality of memory modules, and each of the memory modules may include a controller and a memory device. The host may be configured to access to the memory device of at least one of the memory modules included in the first and second memory module groups. Each of the controllers included in the first and second memory module groups may be configured to selectively perform any one of a memory operation and a storage operation according to a request of the host.

DETAILED DESCRIPTION

In the following description of the embodiments, it will be understood that the terms “first” and “second” are intended to identify an element, but not used to define only the element itself or to mean a particular sequence. In addition, when an element is referred to as being located “on”, “over”, “above”, “under” or “beneath” another element, it is intended to mean relative position relationship, but not used to limit certain cases that the element directly contacts the other element, or at least one intervening element is present there between. Accordingly, the terms such as “on”, “over”, “above”, “under”, “beneath”, “below” and the like that are used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the present disclosure. Further, when an element is referred to as being “connected” or “coupled” to another element, the element may be electrically or mechanically connected or coupled to the other element directly, or may form a connection relationship or coupling relationship by replacing the other element there between.

Various embodiments may be directed to data processing systems including a plurality of memory modules.

FIG. 1is a block diagram illustrating a data processing system100according to an embodiment. Referring toFIG. 1, the data processing system100may include a memory/storage circuit200and a host300. The memory/storage circuit200may include a first memory module210and a second memory module220. Each of the first and second memory modules210and220may be configured to selectively perform any one of a memory operation and a storage operation according to a request of the host300. In general, the memory operation may be defined as an operation which is performed to temporarily store programs and data into a volatile memory device such as a DRAM device, and the storage operation may be defined as an operation which is performed to store data into a nonvolatile memory device such as a NAND flash memory device or a storage device such as a hard disk drive. However, in the present disclosure, the memory operation may include an operation which is performed to store the programs and the data into a nonvolatile memory device such as a phase change RAM (PCRAM) device. Data transmission between the host300and the first memory module210may be achieved using a first data bus310. Data transmission between the host300and the second memory module220may be achieved using a second data bus320.

The first and second memory modules210and220may be realized to have the same structure and configuration. For example, each of the first and second memory modules210and220may be realized to include a controller and a memory device which are integrated on the same substrate. In such a case, the memory device may be a PCRAM device, a magneto-resistive RAM (MRAM) device, a nano floating gate memory (NFGM) device, a resistive RAM (RRAM) device or a polymer RAM device.

The first memory module210may include a first memory device211and a first controller212. The first memory device211may be realized to include a single memory chip or a plurality of memory chips which are integrated on a substrate. The first controller212may include a first interface logic circuit (IL1)212A and a second interface logic circuit (IL2)2128. The first memory device211may communicate with the host300through the first and second interface logic circuits (IL1, IL2)212A and2128of the first controller212. The first interface logic circuit (IL1)212A may be connected to the first memory device211and may be configured to perform the memory operation of the first memory device211. The second interface logic circuit (IL2)2128may be connected to the first memory device211and may be configured to perform the storage operation of the first memory device211.

The second memory module220may include a second memory device221and a second controller222. The second controller222may include a first interface logic circuit (IL1)222A and a second interface logic circuit (IL2)222B. The second memory device221may communicate with the host300through the first and second interface logic circuits (IL1, IL2)222A and222B of the second controller222. The first and second memory modules210and220may have substantially the same structure and the same configuration. That is, the second memory device221may have the same configuration as the first memory device211, and the second controller222may also have the same configuration as the first controller212. Accordingly, in a present embodiment, the first and second memory modules210and220may be replaced with each other. In a present embodiment, the first and second memory modules210and220may be interchangeable with each other.

The first memory device211of the first memory module210may be a nonvolatile memory device having a relatively low latency to selectively perform any one of the memory operation and the storage operation according to a request of the host300. Similarly, the second memory device221of the first memory module220may also be a nonvolatile memory device having a relatively low latency to selectively perform any one of the memory operation and the storage operation according to a request of the host300. As described above, each of the first and second memory devices211and221may be a PCRAM device, an MRAM device, an NFGM device, an RRAM device or a polymer RAM device.

The host300may access to the first memory device211of the first memory module210through the first controller212and may access to the second memory device221of the second memory module220through the second controller222. In an embodiment, if the memory operation is required, the host300may access to the first memory device211of the first memory module210. In an embodiment, if the storage operation is required, the host300may access to the second memory device221of the second memory module220.

For example, if the memory operation is required, the host300may transmit a first read command or a first write command to the first controller212of the first memory module210through the first data bus310. The host300may additionally transmit various commands necessary for the memory operation to the first controller212. In some embodiments, the various commands necessary for the memory operation may include a power-down command or a refresh command. In such a case, the first interface logic circuit212A of the first controller212may control operations of the first memory device211, and the second interface logic circuit212B of the first controller212may stop controlling the operations of the first memory device211. That is, a set value for activating the first interface logic circuit212A and for inactivating the second interface logic circuit212B may be stored in a register (not illustrated) of the first controller212. The set value may be stored in the register (not illustrated) of the first controller212by the host300when the data processing system100is booted up.

If the storage operation is required, the host300may transmit a second read command (or a second write command) and address information to the second controller222of the second memory module220through the second data bus320. In such a case, the second interface logic circuit222B of the second controller222may control operations of the second memory device221, and the first interface logic circuit222A of the second controller222may stop controlling the operations of the second memory device221. That is, a set value for activating the second interface logic circuit222B and for inactivating the first interface logic circuit222A may be stored in a register (not illustrated) of the second controller222. The set value may be stored in the register (not illustrated) of the second controller222by the host300when the data processing system100is booted up.

In some other embodiments, both of the first and second memory modules210and220may perform the memory operation or the storage operation. For example, in order that both of the first and second memory modules210and220perform the memory operation, the first interface logic circuit212A of the first controller212and the first interface logic circuit222A of the second controller222may be activated and the second interface logic circuit212B of the first controller212and the second interface logic circuit222B of the second controller222may be inactivated. In order that both of the first and second memory modules210and220perform the storage operation, the second interface logic circuit212B of the first controller212and the second interface logic circuit222B of the second controller222may be activated and the first interface logic circuit212A of the first controller212and the first interface logic circuit222A of the second controller222may be inactivated.

FIG. 2is a block diagram illustrating a data processing system400according to an embodiment. Referring toFIG. 2, the data processing system400may include a memory/storage circuit500and a host600. The memory/storage circuit500may include a first memory module510and a second memory module520. Each of the first and second memory modules510and520may be configured to selectively perform any one of the memory operation and the storage operation according to a request of the host600. Data transmission between the host600and the first memory module510may be achieved using a first data bus610. Data transmission between the host600and the second memory module520may be achieved using a second data bus620.

The first and second memory modules510and520may be realized to have the same structure and configuration. For example, each of the first and second memory modules510and520may be realized to include a controller and a memory device which are integrated on the same substrate. The first memory module510may include a first memory device511and a first controller512. The first memory device511may be realized to include a single memory chip or a plurality of memory chips which are integrated on a substrate. The first controller512may include a first interface logic group512A and a second interface logic group512B. The first interface logic group512A may include a plurality of first interface logic circuits, for example, “m”-number of first interface logic circuits (IL1-1, . . . , and IL1-m)512A-1, . . . , and512A-m (wherein, “m” is a natural number which is equal to or greater than two). The first memory device511may communicate with the host600through the first and second interface logic groups512A and512B of the first controller512. The first interface logic circuits (IL1-1, . . . , and IL1-m)512A-1, . . . , and512A-m may be connected to the first memory device511and may be configured to perform the memory operation of the first memory device511. The first interface logic circuits512A-1, . . . , and512A-m may be configured to perform the memory operation of the first memory device511according to memory specifications of the first memory device511. In some embodiments, each of the memory specifications of the first memory device511may include a RAM timing, an operation clock, a memory bus width, a channel scheme, a latency, and a serial/parallel transmission scheme. The second interface logic group512B may include a plurality of second interface logic circuits, for example, “n”-number of second interface logic circuits (IL2-1, . . . , and IL2-n)512B-1, . . . , and512B-n (wherein, “n” is a natural number which is equal to or greater than two). The second interface logic circuits512B-1, . . . , and512B-n may be connected to the first memory device511and may be configured to perform the storage operation of the first memory device511. The second interface logic circuits512B-1, . . . , and512B-n may be configured to perform the storage operation of the first memory device511according to storage specifications of the first memory device511.

The second memory module520may include a second memory device521and a second controller522. The second controller522may include a first interface logic group522A and a second interface logic group522B. The first interface logic group522A may include a plurality of first interface logic circuits, for example, “m”-number of first interface logic circuits (IL1-1, . . . , and IL1-m)522A-1, . . . , and522A-m. The second interface logic group522B may include a plurality of second interface logic circuits, for example, “n”-number of second interface logic circuits (IL2-1, . . . , and IL2-n)522B-1, . . . , and522B-n. The first and second memory modules510and520may have substantially the same structure and configuration. That is, the second memory device521may have the same configuration as the first memory device511, and the second controller522may also have the same configuration as the first controller512. Accordingly, in a present embodiment, the first and second memory modules510and520may be replaced with each other. Each of the first and second memory devices511and521may be a PCRAM device, an MRAM device, an NFGM device, an RRAM device or a polymer RAM device. In a present embodiment, the first and second memory modules510and520may be interchangeable with each other.

The host600may access to the first memory device511of the first memory module510through the first controller512and may access to the second memory device521of the second memory module520through the second controller522. In an embodiment, if the memory operation is required, the host600may access to the first memory device511of the first memory module510. In an embodiment, if the storage operation is required, the host600may access to the second memory device521of the second memory module520.

For example, if the memory operation is required, the host600may transmit a first read command or a first write command to the first controller512of the first memory module510through the first data bus610. The host600may additionally transmit various commands necessary for the memory operation to the first controller512. In some embodiments, the various commands necessary for the memory operation may include a power-down command or a refresh command. In such a case, any one selected from the first interface logic circuits512A-1, . . . , and512A-m constituting the first interface logic group512A of the first controller512may control operations of the first memory device511, and all of the second interface logic circuits512B-1, . . . , and512B-n constituting the second interface logic group512B of the first controller512may stop controlling the operations of the first memory device511. That is, a set value for activating any one selected from the first interface logic circuits512A-1, . . . , and512A-m and for inactivating the remaining non-selected first interface logic circuits and all of the second interface logic circuits512B-1, . . . , and512B-n may be stored in a register (not illustrated) of the first controller512. The set value may be stored in the register (not illustrated) of the first controller512by the host600when the data processing system400is booted up.

If the storage operation is required, the host600may transmit a second read command (or a second write command) and address information to the second controller522of the second memory module520through the second data bus620. In such a case, any one selected from the second interface logic circuits522B-1, . . . , and522B-n constituting the second interface logic group522B of the second controller522may control operations of the second memory device521, and all of the first interface logic circuits522A-1, . . . , and522A-m constituting the first interface logic group522A of the second controller522may stop controlling the operations of the second memory device521. That is, a set value for activating any one selected from the second interface logic circuits522B-1, . . . , and522B-n and for inactivating the remaining non-selected second interface logic circuits and all of the first interface logic circuits522A-1, . . . , and522A-m may be stored in a register (not illustrated) of the second controller522. The set value may be stored in the register (not illustrated) of the second controller522by the host600when the data processing system400is booted up.

In some other embodiments, both of the first and second memory modules510and520may perform the memory operation or the storage operation. In order that both of the first and second memory modules510and520perform the memory operation, any one selected from the first interface logic circuits512A-1, . . . , and512A-m constituting the first interface logic group512A of the first controller512and any one selected from the first interface logic circuits522A-1, . . . , and522A-m constituting the first interface logic group522A of the second controller522may be activated. In such a case, the remaining non-selected first interface logic circuits of the first controller512, all of the second interface logic circuits512B-1, . . . , and512B-n of the first controller512, the remaining non-selected first interface logic circuits of the second controller522, and all of the second interface logic circuits522B-1, . . . , and522B-n of the second controller522may be inactivated. The first interface logic circuit selected and activated in the first controller512and the first interface logic circuit selected and activated in the second controller522may be configured to operate based on the same memory specification. In such a case, the first and second memory modules510and520may have the same memory specification. Alternatively, the first interface logic circuit selected and activated in the first controller512and the first interface logic circuit selected and activated in the second controller522may be configured to operate based on different memory specifications. In such a case, the first and second memory modules510and520may have different memory specifications.

In order that both of the first and second memory modules510and520perform the storage operation, any one selected from the second interface logic circuits512B-1, . . . , and512B-n constituting the second interface logic group512B of the first controller512and any one selected from the second interface logic circuits522B-1, . . . , and522B-n constituting the second interface logic group522B of the second controller522may be activated. In such a case, the remaining non-selected second interface logic circuits of the first controller512, all of the first interface logic circuits512A-1, . . . , and512A-m of the first controller512, the remaining non-selected second interface logic circuits of the second controller522, and all of the first interface logic circuits522A-1, . . . , and522A-m of the second controller522may be inactivated. The second interface logic circuit selected and activated in the first controller512and the second interface logic circuit selected and activated in the second controller522may be configured to operate based on the same storage specification. In such a case, the first and second memory modules510and520may have the same storage specification. Alternatively, the first interface logic circuit selected and activated in the first controller512and the first interface logic circuit selected and activated in the second controller522may be configured to operate based on different storage specifications. In such a case, the first and second memory modules510and520may have different storage specifications.

FIG. 3is a block diagram illustrating a data processing system700according to an embodiment, andFIG. 4is a block diagram illustrating any one of memory modules included in the data processing system700illustrated inFIG. 3. Referring toFIGS. 3 and 4, the data processing system700may include a memory/storage circuit800and a host900. The memory/storage circuit800may include a first memory module group810A and a second memory module group820A. The first memory module group810A may include a plurality of first memory modules, for example, “i”-number of first memory modules810-1, . . . , and810-i. The second memory module group820A may include a plurality of second memory modules, for example, “j”-number of second memory modules820-1, . . . , and820-j. Each of the first memory modules810-1, . . . , and810-iand the second memory modules820-1, . . . , and820-jmay be configured to selectively perform any one of the memory operation and the storage operation according to a request of the host900. In some embodiments, the first memory modules810-1, . . . , and810-iconstituting the first memory module group810A may perform the memory operation, and the second memory modules820-1, . . . , and820-jconstituting the second memory module group820A may perform the storage operation.

The host900may receive data from the first memory modules810-1, . . . , and810-ithrough first data buses910-1, . . . , and910-ior may output the data to the first memory modules810-1, . . . , and810-ithrough the first data buses910-1, . . . , and910-i. The number of the first memory modules810-1, . . . , and810-imay be equal to the number of the first data buses910-1, . . . , and910-i. In some embodiments, the data transmission between the host900and the first memory module810-1may be achieved using the first data bus910-1, and the data transmission between the host900and the first memory module810-imay be achieved using the first data bus910-i. The host900may receive data from the second memory modules820-1, . . . , and820-jthrough second data buses920-1, . . . , and920-jor may output the data to the second memory modules820-1, . . . , and820-jthrough the second data buses920-1, . . . , and920-j. The number of the second memory modules820-1, . . . , and820-jmay be equal to the number of the second data buses920-1, . . . , and920-j. In some embodiments, the data transmission between the host900and the second memory module820-1may be achieved using the second data bus920-1, and the data transmission between the host900and the second memory module820-jmay be achieved using the second data bus920-j.

Each of the first memory modules810-1, . . . , and810-imay be configured to include a controller and a memory device which are integrated on a substrate, and each of the second memory modules820-1, . . . , and820-jmay also be configured to include a controller and a memory device which are integrated on a substrate. In addition, the first memory modules810-1, . . . , and810-iand the second memory modules820-1, . . . , and820-jmay have the same configuration. That is, each of the first memory modules810-2, . . . , and810-iand the second memory modules820-1, . . . , and820-jmay have the same configuration as the first memory module810-1illustrated inFIG. 4. As illustrated inFIG. 4, the first memory module810-1of the first memory module group810A may include a memory device811and a controller812. The memory device811may be realized to include a single memory chip or a plurality of memory chips which are integrated on a substrate. The memory device811may be a PCRAM device, an MRAM device, an NFGM device, an RRAM device or a polymer RAM device.

The controller812may include a first interface logic group812A and a second interface logic group812B. The first interface logic group812A may include a plurality of first interface logic circuits, for example, “m”-number of first interface logic circuits (IL1-1, . . . , and IL1-m)812A-1, . . . , and812A-m. The memory device811may communicate with the host900through the first and second interface logic groups812A and812B of the first controller812. The first interface logic circuits (IL1-1, . . . , and IL1-m)812A-1, . . . , and812A-m may be connected to the memory device811and may be configured to perform the memory operation of the memory device811. The first interface logic circuits812A-1, . . . , and812A-m may be configured to perform the memory operation of the memory device811based on a memory specification of the memory device811. In some embodiments, the memory specification of the memory device811may include a RAM timing, an operation clock, a memory bus width, a channel scheme, a latency, and a serial/parallel transmission scheme. The second interface logic group812B may include a plurality of second interface logic circuits, for example, “n”-number of second interface logic circuits (IL2-1, . . . , and IL2-n)812B-1, . . . , and812B-n. The second interface logic circuits812B-1, . . . , and812B-n may be connected to the memory device811and may be configured to perform the storage operation of the memory device811. The second interface logic circuits812B-1, . . . , and812B-n may be configured to perform the storage operation of the memory device811according to a storage specification of the memory device811.

The host900may access to the memory devices811of the first memory modules810-1, . . . , and810-iconstituting the first memory module group810A or to the memory devices811of the second memory modules820-1, . . . , and820-jconstituting the second memory module group820A. In an embodiment, if the memory operation is required, the host900may access to the memory devices811of the first memory modules810-1, . . . , and810-i. In an embodiment, if the storage operation is required, the host900may access to the memory devices811of the second memory modules820-1, . . . , and820-j.

Operations of the data processing system700will be described hereinafter. If the memory operation is required, the host900may transmit a first read command or a first write command to the controllers812of the first memory modules810-1, . . . , and810-ithrough the first data buses910-1, . . . , and910-i. The host900may additionally transmit various commands necessary for the memory operation to the controllers812. In some embodiments, the various commands necessary for the memory operation may include a power-down command or a refresh command. In such a case, in each of the first memory modules810-1, . . . , and810-i, any one selected from the first interface logic circuits812A-1, . . . , and812A-m constituting the first interface logic group812A may control an operation of the memory device811, and all of the second interface logic circuits812B-1, . . . , and812B-n constituting the second interface logic group812B may stop controlling the operation of the memory device811. That is, a set value for activating any one selected from the first interface logic circuits812A-1, . . . , and812A-m constituting the first interface logic group812A as well as for inactivating the remaining non-selected first interface logic circuits and all of the second interface logic circuits812B-1, . . . , and812B-n constituting the second interface logic group812B may be stored in a register (not illustrated) of the controller812. The set value may be stored in the register (not illustrated) of the controller812by the host900when the data processing system700is booted up.

If the storage operation is required, the host900may transmit a second read command (or a second write command) and address information to the controllers812of the second memory modules820-1, . . . , and820-jthrough the second data buses920-1, . . . , and920-j. In such a case, in each of the second memory modules820-1, . . . , and820-j, any one selected from the second interface logic circuits812B-1, . . . , and812B-n constituting the second interface logic group812B may control an operation of the memory device811, and all of the first interface logic circuits812A-1, . . . , and812A-m constituting the first interface logic group812A may stop controlling the operation of the memory device811. That is, a set value for activating any one selected from the second interface logic circuits812B-1, . . . , and812B-n constituting the second interface logic group812B as well as for inactivating the remaining non-selected second interface logic circuits and all of the first interface logic circuits812A-1, . . . , and812A-m constituting the first interface logic group812A may be stored in a register (not illustrated) of the controller812. The set value may be stored in the register (not illustrated) of the controller812by the host900when the data processing system700is booted up.

In the data processing system700, some of the first memory modules810-1, . . . , and810-iconstituting the first memory module group810A may be used as memory units during the memory operation, and the remaining first memory modules may be used as storage units during the storage operation. Similarly, some of the second memory modules820-1, . . . , and820-jconstituting the second memory module group820A may be used as memory units during the memory operation, and the remaining second memory modules may be used as storage units during the storage operation. In each of the memory modules used as the memory units, any one of the interface logic circuits may be selectively activated for the memory operation. In each of the memory modules used as the storage units, any one of the interface logic circuits may be selectively activated for the storage operation.

The data processing systems as discussed above (seeFIGS. 1-4) are particular useful in the design of other memory devices, processors, and computer systems. For example, referring toFIG. 5, a block diagram of a system employing a data processing system in accordance with the various embodiments are illustrated and generally designated by a reference numeral1000. The system1000may include one or more processors (i.e., Processor) or, for example but not limited to, central processing units (“CPUs”)1100. The processor (i.e., CPU)1100may be used individually or in combination with other processors (i.e., CPUs). While the processor (i.e., CPU)1100will be referred to primarily in the singular, it will be understood by those skilled in the art that a system1000with any number of physical or logical processors (i.e., CPUs) may be implemented.

A chipset1150may be operably coupled to the processor (i.e., CPU)1100. The chipset1150is a communication pathway for signals between the processor (i.e., CPU)1100and other components of the system1000. Other components of the system1000may include a memory controller1200, an input/output (“I/O”) bus1250, and a disk driver controller1300. Depending on the configuration of the system1000, any one of a number of different signals may be transmitted through the chipset1150, and those skilled in the art will appreciate that the routing of the signals throughout the system1000can be readily adjusted without changing the underlying nature of the system1000.

As stated above, the memory controller1200may be operably coupled to the chipset1150. The memory controller1200may include at least one data processing system as discussed above with reference toFIGS. 1-4. Thus, the memory controller1200can receive a request provided from the processor (i.e., CPU)1100, through the chipset1150. In alternate embodiments, the memory controller1200may be integrated into the chipset1150. The memory controller1200may be operably coupled to one or more memory devices1350. In an embodiment, the memory devices1350may include the at least one data processing system as discussed above with relation toFIGS. 1-4, the memory devices1350may include a plurality of word lines and a plurality of bit lines for defining a plurality of memory cells. The memory devices1350may be any one of a number of industry standard memory types, including but not limited to, single inline memory modules (“SIMMs”) and dual inline memory modules (“DIMMs”). Further, the memory devices1350may facilitate the safe removal of the external data storage devices by storing both instructions and data.

The disk driver controller1300may be operably coupled to the chipset1150. The disk driver controller1300may serve as the communication pathway between the chipset1150and one internal disk driver1450or more than one internal disk driver1450. The internal disk driver1450may facilitate disconnection of the external data storage devices by storing both instructions and data. The disk driver controller1300and the internal disk driver1450may communicate with each other or with the chipset1150using virtually any type of communication protocol, including, for example but not limited to, all of those mentioned above with regard to the I/O bus1250.

It is important to note that the system1000described above in relation toFIG. 5is merely one example of a data processing system as discussed above with relation toFIGS. 1-4. In alternate embodiments, such as, for example but not limited to, cellular phones or digital cameras, the components may differ from the embodiments illustrated inFIG. 5.