Semiconductor device

A semiconductor device has a super junction structure and includes a first semiconductor layer of the second conductive type disposed on the first column region and the second column region, a second semiconductor layer of the first conductive type disposed on the first semiconductor layer, a first semiconductor region of the first conductive type that is electrically connected to the first electrode and is disposed in a surface layer portion of the second semiconductor layer to be separated from the first semiconductor layer, and a second semiconductor region of the second conductive type that is electrically connected to the second electrode and that is disposed at least in the surface layer portion of the second semiconductor layer to be separated from the first semiconductor region and is electrically connected to the first semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is national stage application of International Application No. PCT/JP2020/041633, filed on Nov. 6, 2020, which designates the United States, incorporated herein by reference, and which claims the benefit of priority from Japanese Application No. 2019-203395, filed on Nov. 8, 2019, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND ART

There are power semiconductor devices applied to a high voltage and a large current. As a power semiconductor device, a semiconductor device is known that uses a phenomenon in which a drift layer or a collector layer has low resistance by a conductivity modulation effect in an on state (e.g., L. Theolier, C. Benboujema, A. Schellmanns, N. Batut, Y. Raingeaud, J. B. Ouoirin, “BJT Application Expansion by Insertion of Superjunction”, 22nd ISPSD, pp. 157-160, 2010).

Examples of the semiconductor device using the conductivity modulation effect include a thyristor, an insulated gate bipolar transistor (IGBT), and a bipolar junction transistor (BJT).

The thyristor and the IGBT among these examples can conduct a large amount of current in a large current region. In contrast, the BJT can conduct a large amount of current in a region equal to or lower than a diffusion potential.

SUMMARY OF THE INVENTION

Problem to be Solved by the Invention

However, although the BJT excels in current characteristics at a rising edge, the BJT has disadvantages of low withstand voltage between a base and an emitter and easiness of breaking when a large current transiently flows as in an event of turn-off.

SUMMARY

An object of the embodiments of the present invention is to provide a semiconductor device that has high withstand voltage characteristics and is capable of suppressing breakage due to a large transient current.

A semiconductor device according to an embodiment includes a super junction structure including a first column region of a first conductive type and a second column region of a second conductive type disposed adjacent to the first column region. The semiconductor device further includes: first and second electrodes that are disposed on one side of the super junction structure and that constitute a transistor and are configured to control a current flowing in the transistor; and a third electrode that is disposed on an opposite side of the first and the second electrodes with the super junction structure interposed therebetween and that constitutes the transistor. The semiconductor device includes: a first semiconductor layer of the second conductive type disposed on the first column region and the second column region; a second semiconductor layer of the first conductive type disposed on the first semiconductor layer; a first semiconductor region of the first conductive type that is a semiconductor region electrically connected to the first electrode, the first semiconductor region being disposed in a surface layer portion of the second semiconductor layer to be separated from the first semiconductor layer; and a second semiconductor region of the second conductive type that is a semiconductor region electrically connected to the second electrode, the second semiconductor region being disposed at least in the surface layer portion of the second semiconductor layer to be separated from the first semiconductor region and being electrically connected to the first semiconductor layer.

DETAILED DESCRIPTION

The present invention will be described in detail below with reference to the drawings. The present invention is not limited to the following embodiments. Components in the following embodiments include those easily conceivable by a person skilled in the art or those substantially identical thereto.

A first embodiment will be described in detail below with reference to the drawings.

(Configuration Example of Semiconductor Device)

FIG.1is a sectional view illustrating an example of a configuration of a semiconductor device1according to the first embodiment. As illustrated inFIG.1, the semiconductor device1of the first embodiment includes a semiconductor substrate10including an n-type semiconductor layer11, an n-type column region12, a p-type column region13, and a p-type channel layer14, an n-type semiconductor layer15, a p-type gate region16, an n-type source region17, a source electrode21, a gate electrode22, and a drain electrode23. The names of, for example, the source electrode21, the gate electrode22, and the drain electrode23are merely for convenience, and do not necessarily identify functions thereof.

The semiconductor substrate10includes, at a bottom layer thereof, the n-type semiconductor layer11serving as an n-type semiconductor layer. The n-type column region12serving as a first column region that is an n-type semiconductor region and the p-type column region13serving as a second column region that is a p-type semiconductor region are alternately arranged so as to be adjacent to each other on/above the n-type semiconductor layer11. The n-type column region12and the p-type column region13form a super junction structure. The p-type channel layer14serving as a first semiconductor layer that is a p-type semiconductor layer is disposed on the n-type column region12and the p-type column region13.

The n-type semiconductor layer15serving as a second semiconductor layer that is an n-type semiconductor layer formed by, for example, epitaxial growth is disposed on the p-type channel layer14. The p-type gate region16serving as a second semiconductor region that is a p-type diffusion region reaching the p-type channel layer14from a surface layer portion of the n-type semiconductor layer15is disposed in the n-type semiconductor layer15. The n-type source region17serving as a first semiconductor region that is an n-type diffusion region is disposed in a surface layer portion of the n-type semiconductor layer15sandwiched between the p-type gate regions16. The n-type source region17is isolated from the p-type channel layer14and the p-type gate region16by the n-type semiconductor layer15. In this case, a distance between the n-type source region17and the p-type gate region16is preferably set to, for example, 3 μm or larger.

The total amount of impurities in the n-type column region12is set to substantially the same as the total amount of impurities in the p-type column region13. The impurity concentration of the n-type semiconductor layer15is lower than the impurity concentration of the n-type column region12, and is set to, for example, 1×1015cm−3or lower. The impurity concentration of the p-type gate region16is set higher than the impurity concentration of the p-type channel layer14.

The gate electrode22serving as a second electrode is disposed above the p-type gate region16, and is connected to the p-type gate region16via a gate contact22c. The source electrode21serving as a first electrode is disposed so as to cover the whole, and is connected to the n-type source region17via a source contact21c. An insulating layer31is disposed between the gate electrode22and the source electrode21, and thus, the gate electrode22is insulated from the source electrode21. The drain electrode23serving as a third electrode is disposed so as to cover the entire lower surface on the n-type semiconductor layer11side of the semiconductor substrate10.

The following describes an operation of the semiconductor device1configured as described above.

To turn on the semiconductor device1, a positive voltage is applied to the drain electrode23and a positive voltage is applied to the gate electrode22such that the drain side has a positive potential with respect to the source side. As a result, holes are injected from the p-type gate region16into the n-type source region17.

The holes are also injected from the p-type gate region16into the p-type channel layer14. The holes injected into the p-type channel layer14flow through the p-type channel layer14into the p-type column region13and the n-type column region12. As a result, at least an upper structure of the super junction structure is reduced in resistance by conductivity modulation.

Electrons are injected from the n-type source region17into the p-type channel layer14. The electrons injected into the p-type channel layer14flow through the p-type channel layer14into the p-type column region13and the n-type column region12that have been reduced in resistance, and finally reach the drain electrode23. As a result, a current flows between the source electrode21and the drain electrode23.

When the semiconductor device1is in an off state, no gate voltage is applied to the gate electrode22. In this state, when the positive voltage is applied to the drain electrode23, a depletion layer spreads on both sides of the p-type column region13and the n-type column region12from each of a plurality of pn junctions between the p-type column regions13and the n-type column regions12. As a result, the super junction structure is depleted at a low electric field strength, and thus, the semiconductor device1can have a high withstand voltage.

In the semiconductor device1of the first embodiment, the n-type semiconductor layer15having a low impurity concentration is disposed between the n-type source region17and the p-type channel layer14. The n-type source region17is also separated from the p-type gate region16by the n-type semiconductor layer15. As described above, the impurity concentration of the n-type semiconductor layer15is set to, for example, 1×1015cm−1or lower, and the distance between the n-type source region17and the p-type gate region16is set to, for example, 3 μm or larger. As a result, the withstand voltage between the n-type source region17and the p-type gate region16will be, for example, 50 V or higher.

Subsequently, a preferable configuration of the semiconductor device1of the first embodiment will be described usingFIG.1.

In the semiconductor device1of the first embodiment, as a pitch W2 of the super junction structure decreases, the impurity concentration of the n-type column region12can increase, and accordingly, an on-resistance can decrease.

A transistor pitch W1 depends on a width of the n-type source region17, and the width of the n-type source region17has an optimal value. This is because, as the width of the n-type source region17increases, the number of the electrons injected from the n-type source region17into the p-type channel layer14increases while a moving distance of the holes in the n-type source region17and the p-type channel layer14becomes longer, so that the source resistance and the channel resistance increase.

Therefore, in the semiconductor device1, after fixing the pitch W2 of the super junction structure, it is preferable to set the width of the n-type source region17so as to reduce the on-resistance of the semiconductor device1as much as possible and set the transistor pitch W1 based on the width of the n-type source region17.

(Thickness of Channel Layer)

Subsequently, the preferable configuration of the semiconductor device1of the first embodiment will be described usingFIGS.1and2.FIG.2is a diagram schematically illustrating a state of a depletion layer D when the semiconductor device1according to the first embodiment is in the off state.

In the on state, a transport efficiency of majority carriers (electrons) injected from the n-type source region17into the p-type channel layer14in the p-type channel layer14is closer to one as a thickness WP of the p-type channel layer14decreases, and thus, the current drive capability of the semiconductor device1improves.

However, as the thickness WP of the p-type channel layer14decreases, the p-type channel layer14is more easily completely depleted in the off state.

Therefore, an impurity concentration Ich of the p-type channel layer14is preferably increased while reducing the thickness WP of the p-type channel layer14as much as possible. As a guide, the thickness WP of the p-type channel layer14only needs to be smaller than, for example, a width W3 of the p-type column region13, and the impurity concentration Ich only needs to be higher than, for example, an impurity concentration Ico of the p-type column region13.

As illustrated inFIG.2, when the above-described configuration is employed, the depletion layer D of the super junction structure is kept from being connected between the source and drain in the off state, and the high withstand voltage can be maintained.

(Distance Between Source Region and Source Contact)

Subsequently, the preferable configuration of the semiconductor device1of the first embodiment will be described usingFIG.1.

In the semiconductor device1of the first embodiment, a distance W4 from an edge of the n-type source region17to an edge of the source contact21cis preferably equal to or larger than a predetermined distance. This configuration can reduce a current caused by minority carriers (holes) injected from the p-type gate region16into the n-type source region17, and thus, can reduce the gate current to increase the current amplification factor of the semiconductor device1. Herein, the current amplification factor of the semiconductor device1refers to drain current/gate current.

The current value caused by the holes injected from the p-type gate region16into the n-type source region17depends on a diffusion length of the holes in the n-type source region17. Therefore, the distance W4 from the edge of the n-type source region17to the edge of the source contact21cis preferably equal to or larger than the diffusion length of the holes in the n-type source region17, and the distance W4 is more preferably equal to or larger than three times the diffusion length of the holes.

Next, a semiconductor device of a comparative example will be described below usingFIG.3, and effects of the semiconductor device1of the first embodiment will be described as compared with the semiconductor device of the comparative example.

FIG.3is a sectional view illustrating a configuration of the semiconductor device according to the comparative example. As illustrated inFIG.3, the semiconductor device of the comparative example is configured as a super-junction bipolar transistor (SJ-BJT) using the super junction structure in a collector region.

A semiconductor substrate50included in the semiconductor device of the comparative example includes an n-type collector layer51, an n-type buffer layer52b, an n-type column region52, a p-type column region53, and a p-type base layer56in this order from the bottom layer. An n-type emitter region57is selectively formed in a surface layer portion of the p-type base layer56on the n-type column region52. An emitter electrode61connected to the n-type emitter region57is disposed above the n-type emitter region57. A base electrode62connected to the p-type base layer56is disposed above the p-type base layer56. The emitter electrode61is isolated from the base electrode62by an insulating layer71. A collector electrode63is disposed on a lower surface on the n-type collector layer51side of the semiconductor substrate50.

When the semiconductor device of the comparative example is in the off state, the depletion layer spreads on both sides of the p-type column region53and the n-type column region52from each of a plurality of pn junctions between the p-type column regions53and the n-type column regions52, and the super junction structure of the p-type column region53and the n-type column region52is depleted at a low electric field strength, so that the withstand voltage is increased. In the off state, the super junction structure maintains a reverse bias. Therefore, the depletion layer only slightly spreads to the p-type base layer56, and the p-type base layer56can be made thin. Therefore, in the on state, the injection efficiency of electrons from the emitter region to the collector region can be increased.

To turn on the semiconductor device of the comparative example, a positive voltage is applied to the base electrode62. As a result, holes are injected from the p-type base layer56into the n-type emitter region57, and a collector current flows between the collector and the emitter. In the semiconductor device of the comparative example serving as the SJ-BJT, the impurity concentration of the n-type column region52can be made higher than the impurity concentration of the collector layer of a conventional high withstand voltage vertical bipolar transistor. Therefore, in a region of a high collector current density, the current amplification factor can be kept from being reduced by collector resistance.

Some of the holes from the p-type base layer56flows into the p-type column region53and the n-type column region52, and the super junction structure and the n-type buffer layer52bare reduced in resistance by the conductivity modulation. Therefore, in the semiconductor device of the comparative example, a voltage equal to or higher than a diffusion potential difference need not be applied as in the case of, for example, the IGBT, and the collector current flows along with the application of the collector voltage.

As described above, the semiconductor device of the comparative example is configured as the SJ-BJT, and excels in current rising characteristics. However, in the semiconductor device of the comparative example, the high-concentration p-type base layer56is in contact with the high-concentration n-type emitter region57, and the withstand voltage between the base and the emitter is as low as approximately 10 V to 20 V. In addition, in the semiconductor device of the comparative example, when a large current transiently flows as in the event of turn-off, the p-type base layer56may be destroyed.

According to the semiconductor device1of the first embodiment, the n-type source region17is arranged on the surface layer portion of the n-type semiconductor layer15so as to be separated from the p-type channel layer14. In addition, the p-type gate region16is separated from the n-type source region17, and reaches the p-type channel layer14from the surface layer portion of the n-type semiconductor layer15. As a result, a reverse withstand voltage between the gate and the source increases to make the destruction difficult to occur.

According to the semiconductor device1of the first embodiment, the p-type gate region16is in contact with the p-type channel layer14. As a result, the resistance of a conducting path of the large current transiently generated in the event of the turn-off can be reduced, and the fracture toughness can be increased.

According to the semiconductor device1of the first embodiment, after fixing the pitch W2 of the super junction structure, the transistor pitch W1 is set based on the width of the n-type source region17.

For example, in the semiconductor device of the comparative example, the n-type emitter region57is selectively formed above the n-type column region52; the p-type base layer56is formed above the p-type column region53; and the base electrode62is formed above the p-type base layer56. That is, in the case of the SJ-BJT such as in the semiconductor device of the comparative example, the transistor pitch is the same as the pitch of the super junction.

In contrast, in the semiconductor device1of the first embodiment, the width of the n-type source region17can be optimized regardless of the pitch W2 of the super junction structure, and therefore, the on-resistance of the semiconductor device1can be suppressed.

According to the semiconductor device1of the first embodiment, the thickness WP of the p-type channel layer14is smaller than the width W3 of the p-type column region13, and the impurity concentration Ich is higher than the impurity concentration Ico of the p-type column region13. As a result, in the on state, the transport efficiency of the electrons injected from the n-type source region17into the p-type channel layer14can be made close to one. In addition, in the off state, the p-type channel layer14is kept from being fully depleted to suppress the occurrence of punch-through between the drain and the source, and the high withstand voltage can be maintained.

According to the semiconductor device1of the first embodiment, the distance W4 from the edge of the n-type source region17to the edge of the source contact21cis three times or more the diffusion length of the holes. As a result, the holes injected from the p-type gate region16to the n-type source region17can be reduced to increase the current amplification factor.

Next, a semiconductor device2of a second embodiment will be described below usingFIG.4. The semiconductor device2of the second embodiment differs from the semiconductor device of the above-described first embodiment in that a p-type gate region18is not in physical contact with the p-type channel layer14.

FIG.4is a sectional view illustrating an example of a configuration of the semiconductor device2according to the second embodiment. InFIG.4, the same components as those of the above-described first embodiment are denoted by the same reference numerals, and will not be described.

As illustrated inFIG.4, in the semiconductor device2of the second embodiment, the p-type gate region18does not reach the p-type channel layer14. However, the p-type gate region18is electrostatically connected to the p-type channel layer14. A pnp junction structure is formed between the p-type gate region18and the p-type channel layer14. The state where the p-type gate region18is electrostatically connected to the p-type channel layer14refers to a state where the holes can be injected from the p-type gate region18into the p-type channel layer14even though the n-type semiconductor layer15is interposed therebetween in this manner. That is, the gradient of the impurity concentration in the pnp junction structure between the p-type gate region18and the p-type channel layer14is adjusted to enable the operation as the semiconductor device2even though the p-type gate region18is away from the p-type channel layer14.

Accordingly, the on/off operations and the on/off characteristics of the semiconductor device2of the second embodiment are the same as those of the semiconductor device1of the first embodiment described above.

However, in the semiconductor device2, since the p-type gate region18is not diffused to an extent of reaching the p-type channel layer14, the manufacturing process of the semiconductor device2does not require heat treatment at a high temperature for a long time. As a result, interdiffusion of impurities between the n-type column region12and the p-type column region13is suppressed, and the effective amount of impurities in the n-type column region12is maintained. The effective amount of impurities in the n-type column region12contributes to the characteristics in the on state.

According to the semiconductor device2of the second embodiment, the p-type gate region18and the p-type channel layer14are not in physical contact with each other, but are electrically connected to each other. As a result, the heat treatment at a high temperature for a long time is not required, and thus, reduction in performance of the semiconductor device2can be suppressed.

Next, a semiconductor device3of a third embodiment will be described below usingFIGS.5A and5B. The semiconductor device3of the third embodiment differs from the semiconductor devices of the first and the second embodiments described above in that it includes a p-type embedded gate region19.

FIGS.5A and5Bdepict views illustrating an example of a configuration of the semiconductor device3according to the third embodiment.FIG.5Ais a vertical sectional view of the semiconductor device3.FIG.5Bis a horizontal sectional view of the semiconductor device3taken along line A-A ofFIG.5A. InFIGS.5A and5B, the same components as those of the first or the second embodiment described above are denoted by the same reference numerals, and will not be described.

As illustrated inFIG.5A, the semiconductor device3of the third embodiment includes the p-type embedded gate region19serving as a third semiconductor region that is a p-type diffusion region in the p-type channel layer14below the p-type gate region18. However, the semiconductor device3may include the p-type gate region16that reaches the p-type embedded gate region19as in the first embodiment described above.

The p-type embedded gate region19is formed by, for example, forming the p-type channel layer14on the semiconductor substrate10and then further diffusing p-type impurities in a predetermined region at a high concentration. After the n-type semiconductor layer15serving as an epitaxial layer is formed, a portion of the p-type impurities diffused at a high concentration is also diffused in the n-type semiconductor layer15, and is formed as the p-type embedded gate region19thicker than the p-type channel layer14.

A region in which the p-type embedded gate region19is disposed corresponds to a region in which the p-type gate region18is electrostatically connected to the p-type channel layer14, and serves as, for example, a conducting path of the large current transiently generated in the event of the turn-off. The p-type embedded gate region19including a high concentration of the p-type impurities reduces the resistance of this conducting path.

As illustrated inFIG.5B, the n-type source region17, the p-type gate region18, and the p-type embedded gate region19of the semiconductor device3extend in a direction along the p-type channel layer14. The direction along the p-type channel layer14includes a direction parallel to the p-type channel layer14and directions substantially parallel to the p-type channel layer14.

Pluralities of the n-type source regions17, the p-type gate regions18, and the p-type embedded gate regions19are each arranged in a direction intersecting the extending direction thereof. That is, the n-type source regions17, the p-type gate regions18, and the p-type embedded gate regions19are each arranged to have a periodic pattern in a direction intersecting the extending direction thereof. The direction intersecting the extending direction includes a direction orthogonal to the extending direction and directions substantially orthogonal to the extending direction.

The n-type column region12and the p-type column region13of the semiconductor device3extend in a direction along the extending direction of the n-type source region17, the p-type gate region18, and the p-type embedded gate region19. The direction along the extending direction includes a direction parallel to the extending direction and directions substantially parallel to the extending direction. Pluralities of the n-type column regions12and the p-type column regions13are each arranged in a direction intersecting their own extending direction. That is, the n-type column regions12and the p-type column regions13are each arranged to have a periodic pattern in a direction intersecting the extending direction thereof.

Regions indicated by oblique lines inFIG.5Bare regions in which the p-type embedded gate regions19overlap the p-type column regions13in a top view.

According to the semiconductor device3of the third embodiment, the p-type embedded gate region19is disposed in a region of the p-type channel layer14electrically connected to the p-type gate region18. As a result, the resistance of the conducting path of the large current transiently generated in the event of the turn-off can be reduced, operation of parasitic elements is suppressed, and the fracture toughness can be increased.

Next, a semiconductor device of a first modification of the third embodiment will be described below usingFIG.6. In the semiconductor device of the first modification, the extending directions of an n-type column region12aand a p-type column region13adiffer from those of the first to the third embodiments described above.

FIG.6is a horizontal sectional view illustrating an example of a configuration of the semiconductor device according to the first modification of the third embodiment. More specifically,FIG.6is a horizontal sectional view of the semiconductor device of the first modification in the same position as that of line A-A ofFIG.5A.

As illustrated inFIG.6, the n-type column region12aand the p-type column region13aof the semiconductor device of the first modification extend in a direction intersecting the extending direction of the n-type source region17, the p-type gate region18, and the p-type embedded gate region19. Pluralities of the n-type column regions12aand the p-type column regions13aare each arranged in a direction intersecting their own extending direction. Regions indicated by oblique lines inFIG.6are regions in which the p-type embedded gate regions19overlap the p-type column regions13ain the top view.

The regions in which the p-type embedded gate regions19overlap the p-type column regions13aare regions that block the flow of the electrons injected from the n-type source region17towards the drain side in the on state. The regions in which the p-type embedded gate regions19overlap the p-type column regions13ain the semiconductor device of the first modification are substantially half the regions in which the p-type embedded gate regions19overlap the p-type column regions13in the semiconductor device3of the third embodiment described above.

According to the semiconductor device of the first modification, the p-type embedded gate regions19extend in the direction along the p-type channel layer14, and the p-type column regions13aextend in the direction intersecting the extending direction of the p-type embedded gate regions19. As a result, the ratio of the regions in which the p-type embedded gate regions19overlap the p-type column regions13acan be reduced, and thus, the drain current can be increased in the on state.

Next, a semiconductor device4of a second modification of the third embodiment will be described below usingFIGS.7A and7B. The semiconductor device4of the second modification differs from the semiconductor devices of the first to the third embodiments described above in that source contacts21caare arranged in an island pattern.

FIGS.7A and7Bdepict views illustrating an example of a configuration of the semiconductor device4according to the second modification of the third embodiment.FIG.7Ais a vertical sectional view of the semiconductor device4.FIG.7Bis a horizontal sectional view of the semiconductor device4taken along line B-B ofFIG.7A.

As illustrated inFIG.7B, the source contacts21caare separated into an island pattern, and are arranged so as to be scattered in the extending direction of the n-type source region17.

FIG.7Ais a vertical sectional view of the semiconductor device4taken along line C-C ofFIG.7B, and is a vertical sectional view in a position where the source contacts21caare not present.

According to the semiconductor device4of the second modification, the source contacts21caare arranged so as to be scattered in the extending direction of the n-type source region17. As a result, an effective distance from an edge of the n-type source region17to an edge of each of the source contacts21ca(corresponding to the distance W4 inFIG.1) can be further increased, and the minority carriers injected from the p-type gate region16into the n-type source region17can be reduced. Therefore, the current amplification factor in the semiconductor device4can be further increased.

The configuration of the semiconductor device4of the second modification can be usefully applied not only to the semiconductor device3of the third embodiment, but also to the semiconductor devices1and2of the first and the second embodiments described above.

In the first to the third embodiments and the first and the second modifications of the third embodiment described above, the n-channel transistor has been described as an example. However, the above-described configurations can be applied to a p-channel transistor obtained by inverting the conductive type of each component.

EXAMPLES

Examples will be described in detail below with reference to the drawings.

First Example

FIGS.8A and8Bdepict diagrams plotting current vectors of a semiconductor device according to a first example.FIG.8Ais a diagram plotting hole current vectors, andFIG.8Bis a diagram plotting electron current vector.

On the assumption that the semiconductor device of the first example has the same configuration as that of the semiconductor device2of the second embodiment,FIGS.8A and8Bdisplays device simulation results of the semiconductor device of the first example in the on state so as to be enlarged in a region near the n-type source region17, the p-type gate region18, and the p-type channel layer14. InFIGS.8A and8B, for convenience, components corresponding to the respective components of the semiconductor device2of the second embodiment are denoted by the same reference numerals.

In the vector representation of the hole current inFIG.8A, the directions of the vectors represent the directions of movement of the holes. As illustrated inFIG.8A, in the on state, the holes are injected from the p-type gate region18toward the n-type source region17and the p-type channel layer14. The holes injected into the p-type channel layer14flow into the p-type column regions13and the n-type column regions12.

In the vector representation of the electron current inFIG.8B, the opposite directions of the vectors represent the direction of movement of the electrons. As illustrated inFIG.8B, in the on state, the electrons are injected from the n-type source region17toward the p-type channel layer14. The electrons injected into the p-type channel layer14flow into the p-type column regions13and the n-type column regions12. Then, the electrons reach the drain electrode23, and a current flows between the source electrode21and the drain electrode23.

From the simulation results ofFIGS.8A and8B, the behavior of the holes and the electrons in the region near the n-type source region17, the p-type gate region18, and the p-type channel layer14is understood, and the operations of, for example, the semiconductor devices1to3and4of the first to the third embodiments and the first and the second modifications thereof described above are confirmed.

Second Example

Next, a semiconductor device of a second example will be described below usingFIGS.9and10.

FIG.9is an electron density contour plot and a current line plot of the semiconductor device according to the second example. InFIG.9, the electron density contour plot and the current line plot are displayed so as to overlap each other. InFIG.9, the electron density is indicated to be higher as the color is lighter.

On the assumption that the semiconductor device of the second example has the same configuration as that of the semiconductor device2of the second embodiment,FIG.9displays device simulation results of the semiconductor device of the second example in the on state so as to be enlarged in a region near the n-type column regions12and the p-type column regions13. InFIG.9, for convenience, components corresponding to the respective components of the semiconductor device2of the second embodiment are denoted by the same reference numerals.

FIGS.10A and10Bdepict graphs each illustrating a concentration of donor impurities, a concentration of acceptor impurities, and the electron density of the semiconductor device according to the second example.FIG.10Ais a graph in a depth position indicated by line D-D ofFIG.9, andFIG.10Bis a graph in a depth position indicated by line E-E ofFIG.9. The concentration of the donor impurities, the concentration of the acceptor impurities, and the electron density illustrated inFIGS.10A and10Bare also based on the simulation.

As illustrated inFIGS.9,10A, and10B, the electron density increases in an upper portion of the super junction structure. This is because the holes are injected from the p-type gate region16into the n-type column regions12and the p-type column regions13through the p-type channel layer14as described above, and a charge neutral condition is made to be maintained. As illustrated by the current line plot ofFIG.9, the electron current spreads in both the n-type column regions12and the p-type column regions13.

As illustrated inFIGS.9,10A, and10B, the electron density decreases in a lower portion of the super junction structure. The electron density is substantially equal to the concentration of the donor impurities in the n-type column regions12, and is lower than the concentration of the acceptor impurities in the p-type column regions13. This is because the holes injected into the n-type column regions12and the p-type column regions13gradually decrease as they move downward in the super junction structure. As a result, the conductivity modulation effect decreases in the lower portion of the super junction structure, and the electron current flows exclusively in the n-type column regions12as illustrated in the current line plot ofFIG.9.

As described above, in the semiconductor device of the second example, mainly the upper portion of the super junction structure is reduced in resistance by the conductivity modulation in the on state.

Third Example

Next, a semiconductor device of a third example will be described below usingFIG.11.FIG.11is a graph illustrating electrical characteristics of the semiconductor device according to the third example.

On the assumption that the semiconductor device of the third example has the same configuration as that of the semiconductor device2of the second embodiment,FIG.11plots device simulation results of the semiconductor device of the third example.

As illustrated inFIG.11, the semiconductor device of the third example is predicted to exhibit a steep rise of the drain current in a saturation region, and have good electrical characteristics.

Fourth Example

Next, a semiconductor device of a fourth example will be described below usingFIG.12.FIG.12is a graph illustrating withstand voltage characteristics of the semiconductor devices according to the fourth example and the comparative example.

The semiconductor device of the fourth example is assumed to have the same configuration as that of the semiconductor device2of the second embodiment. The semiconductor device of the comparative example is the semiconductor device illustrated inFIG.3described above. The withstand voltage obtained when a reverse bias is applied to the gate electrode and the source electrode of each of these semiconductor devices was simulated.

As illustrated inFIG.12, the withstand voltage of the semiconductor device of the comparative example was lower than 20 V, whereas the withstand voltage of the semiconductor device of the fourth example was 50 V or higher.

Fifth Example

Next, a semiconductor device of a fifth example will be described below usingFIG.13.

FIG.13is a graph illustrating dependence of an on-resistance Ron on the transistor pitch in the semiconductor device according to the fifth example. The horizontal axis of the graph ofFIG.13indicates the transistor pitch by the number of the p-type column regions included between the transistors. That is, in the case of the semiconductor device1of the first embodiment illustrated inFIG.1, the number of the p-type column regions13included between the transistors is two, so that the transistor pitch is two.

On the assumption that the semiconductor device of the fifth example has the same configuration as that of the semiconductor device2of the second embodiment,FIG.13plots the device simulation results by changing the transistor pitch of the semiconductor device of the fifth example. More specifically, inFIG.13, the width of the n-type source region was changed, and the transistor pitch was changed accordingly. At this time, the pitch of the super junction structure was kept fixed.

As illustrated inFIG.13, in the semiconductor device of the fifth example, the on-resistance Ron decreases once as the transistor pitch increases. This is because, as described above, the increase in the width of the n-type source region increases the number of the electrons injected from the n-type source region into the p-type channel layer.

Further, in the semiconductor device of the fifth embodiment, the on-resistance Ron having once decreased increases again as the transistor pitch increases. This is because, as described above, the increase in the width of the n-type source region increases the moving distance of the holes in the n-type source region and the p-type channel layer, and thus, increases the source resistance and the channel resistance.

The above-described results prove that the transistor pitch has an optimum value, and the on-resistance can be reduced by optimizing the width of the n-type source region.

Sixth Example

Next, a semiconductor device of a sixth example will be described below usingFIG.14.FIG.14is a graph illustrating dependence of the on-resistance Ron and a current amplification factor hFE on the distance from the n-type source region edge to the source contact edge in the semiconductor device according to the sixth example.

On the assumption that the semiconductor device of the sixth example has the same configuration as that of the semiconductor device2of the second embodiment,FIG.14plots the device simulation results by changing the distance from the edge of the n-type source region to the edge of the source contact (corresponding to the distance W4 inFIG.1) of the semiconductor device of the sixth example.

As illustrated inFIG.14, in the semiconductor device of the sixth example, the current amplification factor hFE (=drain current/gate current) increases as the distance from the edge of the n-type source region to the edge of the source contact increases. This is because, as the distance from the edge of the n-type source region to the edge of the source contact increases, the current caused by the holes injected from the p-type gate region into the n-type source region decreases, and therefore, the gate current decreases. In contrast, changing the distance from the edge of the n-type source region to the edge of the source contact has little effect on the on-resistance Ron.

The above-described results prove that increasing the distance from the edge of the n-type source region to the edge of the source contact can increase the current amplification factor without increasing the on-resistance.

According to an embodiment of the present invention, a semiconductor device that has high withstand voltage characteristics and is capable of suppressing breakage due to a large transient current can be obtained.

While some embodiments of the present invention have been described, these embodiments have been presented as examples, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.