PRODUCT-SUM CALCULATION DEVICE AND PRODUCT-SUM CALCULATION METHOD

A product-sum calculation device multiplies first and second floating-point numbers and sequentially adds multiplication results. The device adds a first exponent and a second exponent of the respective floating-point numbers for generating a third exponent, multiplies a first mantissa and a second mantissa of the respective floating-point numbers for generating a third mantissa, sets lower n bits of the third exponent to zero and generates a fourth exponent, shifts the third mantissa to the left by the number of bits indicated by the lower n bits and generated a fourth mantissa, generates an error detection code for each 2n bits of the fourth mantissa, performs digit alignment of the fourth mantissa and a fifth mantissa and outputs an exponent as a new fifth exponent, and adds the fourth mantissa and the fifth mantissa and outputs an addition result as a new fifth mantissa.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2021-66868, filed on Apr. 12, 2021, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a product-sum calculation device and a product-sum calculation method.

BACKGROUND

A shift circuit has been known that can shift an arbitrary number of bits by shifting data including a plurality of bytes in byte units, and then, shifting the data in bit units. In this type of shift circuit, in a case where the data includes a parity for each byte, it is not necessary to provide a prediction circuit for the shifted parity by shifting the data in byte units.

Furthermore, a method is known in which an adder that adds floating-point number data performs addition using fixed point number data converted from the floating-point number data and converts an addition result into the floating-point number data.

Japanese Laid-open Patent Publication No. 61-148527, and Japanese Laid-open Patent Publication No. 2016-157299 are disclosed as related art.

SUMMARY

According to an aspect of the embodiments, a product-sum calculation device that multiplies first floating-point number data and second floating-point number data and sequentially adds multiplication results, the device including: a first adder configured to add a first exponent of the first floating-point number data and a second exponent of the second floating-point number data and generate a third exponent; a multiplier configured to multiply a first mantissa of the first floating-point number data and a second mantissa of the second floating-point number data and generate a third mantissa; a devaluation circuit configured to set lower n bits (n is integer equal to or more than one) of the third exponent to zero and generate a fourth exponent; a first shift circuit configured to shift the third mantissa to the left by the number of bits indicated by a value of the lower n bits of the third exponent and generate a fourth mantissa; an error code generation circuit configured to generate an error detection code for each 2nbits of the fourth mantissa; a second shift circuit configured to perform digit alignment of the fourth mantissa and a fifth mantissa on the basis of a difference between the fourth exponent and a fifth exponent and output an exponent that corresponds to the digit-aligned mantissa as a new fifth exponent; and a second adder configured to add the fourth mantissa and the fifth mantissa, on which digit alignment is performed, and output an addition result as a new fifth mantissa.

DESCRIPTION OF EMBODIMENTS

In a case where a calculation device such as a floating-point product-sum operator executes processing for sequentially adding multiplication results, an addition by an addition circuit is performed after a digit alignment shift circuit performs digit alignment of a mantissa of the multiplication result and a mantissa of the previous addition result. The number of bit shifts of the mantissa in digit alignment is a value determined according to a difference between an exponent of the multiplication result and an exponent of the previous addition result. Therefore, in the digit alignment shift circuit, a parity generation circuit that generates a parity of the mantissa on which digit alignment has been performed is provided. In a case where the digit alignment shift circuit is included in a loop path for a product-sum calculation, a circuit delay of the digit alignment shift circuit such as the parity generation circuit or the like easily affects an increase in a calculation time of the calculation device.

In one aspect, an object of the embodiment is to reduce a circuit delay of a digit alignment shift circuit in a calculation device that performs a product-sum calculation.

Hereinafter, embodiments are described with reference to the drawings.

InFIG. 1, an example of a calculation device according to one embodiment is illustrated. A calculation device100illustrated inFIG. 1is, for example, a product-sum operator that performs a product-sum calculation of floating-point number data and is mounted on a processor or the like. The calculation device100executes processing for multiplying operands OP1and OP2and sequentially adding multiplication results so as to achieve a calculation method.

The calculation device100includes registers10and12, an adder14, a multiplier16, a devaluation circuit18, a parity prediction circuit20, a left shift circuit22, a digit alignment shift circuit24, and an adder26. The adder14is an example of a first adder. The left shift circuit22is an example of a first shift circuit. The digit alignment shift circuit24is an example of a second shift circuit. The adder26is an example of a second adder.

The registers10and12hold operands OP1and OP2to be calculated. The operand OP1includes an exponent E1and a mantissa FL The operand OP2includes an exponent E2and a mantissa F2. Note that parity data may also be added to each of the operands OP1and OP2for each predetermined number of bits of the mantissae F1and F2.

For example, the double precision floating point number format of the Institute of Electrical and Electronics Engineers (IEEE)754(floating point number operation standard) is used, the exponents E1and E2are 11 bits, the mantissae F1and F2are 52 bits, and a sign bit is one bit. In a case where the single precision floating point number format of the IEEE 754 is used, the exponents E1and E2are eight bits, the mantissae F1and F2are 23 bits, and the sign bit is one bit. Note that, in the following description, it is assumed that positive values be used, and the sign bit is omitted.

The adder14adds the exponents E1and E2and outputs an addition result as an exponent E1The multiplier16multiplies the mantissae F1and F2and outputs a multiplication result as a mantissa F3. Note that the multiplier16may also add parity data to the mantissa F3that is the multiplication result for each predetermined number of bits. Furthermore, the multiplier16may also be protected by a residual check method.

The devaluation circuit18executes devaluation processing of the exponent E3by setting lower n bits of the exponent E3from the adder14to zero. Note that it is sufficient that n be an integer equal to or more than one. The number n is determined corresponding to the number of bits 2nof the mantissa F3that is used to generate each parity DP by the parity prediction circuit20. In the following description, it is assumed that n be two.

The parity prediction circuit20generates a parity DP for each four bits (2nbits) for four types of mantissae F4generated in a case where the mantissa F3is shifted to the left at all bit values 0 to 3 indicated by the lower two bits of the exponent E3. The parity prediction circuit20outputs the generated parity DP to the left shift circuit22. In the following, each piece of 2n−bit data (mantissa) that is a parity DP generation unit is referred to as a digit. For example, 2nbits of the data are referred to as a first digit, a second digit, a third digit, . . . , from the lower bit side.

The left shift circuit22shifts each bit of the mantissa F3to the left only by a bit value (any one of zero to three) of lower two bits of the exponent E3. As a result, the mantissa F3can be increased according to the bit value of the lower two bits of the exponent E3devaluated by the devaluation circuit18. In other words, a decrease in the exponent E4with respect to the exponent E3can offset as an increase in the mantissa F4with respect to the mantissa F3, and floating-point number data indicated by the exponent E4and the mantissa F4can be the same as floating-point number data indicated by the exponent E3and the mantissa F3.

Furthermore, the left shift circuit22selects a parity DP corresponding to the bit value of the lower two bits of the exponent E3among the parities DP corresponding to the four types of mantissae F4generated by the parity prediction circuit20. Then, the left shift circuit22embeds the selected parity DP into the mantissa F4. The parity prediction circuit20and a functional unit that selects a correct parity DP from among the parities DP corresponding to the four types of mantissae F4in the left shift circuit22are examples of an error code generation circuit. The parity DP is an example of an error detection code.

The digit alignment shift circuit24performs digit alignment of the floating-point number data indicated by the exponent E4and the mantissa F4and the floating-point number data indicated by an exponent E5and a mantissa F5and outputs the mantissa F4and the exponent E5, on which digit alignment has been performed. The adder26adds the mantissa F4on which digit alignment has been performed by the digit alignment shift circuit24and the mantissa F5that is a previous addition result and outputs the addition result as a new mantissa F5. For example, the adder26includes a parity prediction circuit (not illustrated) that predicts a parity DP corresponding to the new mantissa F5that is the addition result of the mantissae F4and F5. Because the parity prediction circuit included in the adder26operates in parallel to an addition operation by the adder26, a delay penalty is small.

For example, the digit alignment shift circuit24includes a right shift circuit25that shifts a mantissa corresponding to an exponent having a smaller value of the exponents E4and E5to the right by an absolute value of a difference between the exponents E4and E5. The digit alignment shift circuit24outputs a larger one of the exponents E4and E5as an exponent E5.

In a case where the exponent E4> the exponent E5, the right shift circuit25shifts the mantissa F5to the right by the exponent E4-the exponent E5. In a case where the exponent E4< the exponent E5, the right shift circuit25shifts the mantissa F4to the right by the exponent E5-E4. In a case where the exponent E4= the exponent E5, the right shift circuit25outputs the mantissae F4and F5to the adder26without performing right-shifting.

Lower two bits of the exponent E4are zero due to the devaluation by the devaluation circuit18. Because the exponent E5is generated on the basis of the exponent E4of which the lower two bits are set to zero, the lower two bits of the exponent E5are zero. Therefore, it is possible to constantly set a shift amount by the right shift circuit25in four-bit units (2nunits).

For example, in a case where the right shift circuit25shifts the mantissa F4, the parity DP generated by the parity prediction circuit20can be used as a parity DP for the shifted mantissa. Furthermore, in a case where the right shift circuit25shifts the mantissa F5, the parity DP generated by the adder26to be described later can be used as the parity DP for the shifted mantissa.

Therefore, a parity prediction circuit that predicts the parity DP corresponding to the mantissa shifted by the right shift circuit25can be omitted. In a case where the parity prediction circuit is mounted on the digit alignment shift circuit24, a parity DP predicted by the parity prediction circuit is supplied to the right shift circuit25. Therefore, the digit alignment shift circuit that mounts the parity prediction circuit has a longer bit shift time of the right shift circuit25than that of the digit alignment shift circuit24that does not mount the parity prediction circuit.

In this embodiment, because the digit alignment shift circuit24does not need to mount the parity prediction circuit, a circuit delay of the digit alignment shift circuit24can be reduced. For example, the bit shift time of the right shift circuit25can be shortened. As a result, a digit alignment time of the mantissae F4and F5can be shortened, and a time required for a product-sum calculation can be shortened. A calculation time shortening effect increases as the number of times of product-sum calculations increases.

FIG. 2illustrates an example of a calculation device according to another embodiment. Detailed description of elements similar to those inFIG. 1will be omitted. A calculation device102illustrated inFIG. 2is a product-sum operator that performs a product-sum calculation of floating-point number data, similarly to the calculation device100inFIG. 1. For example, the calculation device102achieves a calculation method of a product-sum calculation. In this embodiment, it is assumed that a parity DP be generated for each four bits (2nbits; n is two) of a mantissa F3.

The calculation device102includes registers110and112, an adder114, a multiplier116, a devaluation circuit118, a parity prediction circuit120, a left shift circuit122, and an intermediate register123. Furthermore, the calculation device102includes a digit alignment shift circuit200, an adder126, a loopback register127, and a normalized shift circuit128. The intermediate register123and the loopback register127are arranged to divide a clock cycle.

Functions of the registers110and112, the adder114, and the multiplier116are similar to the functions of the registers10and12, the adder14, and the multiplier16inFIG. 1. Functions of the devaluation circuit118, the parity prediction circuit120, the left shift circuit122, and the adder126are similar to the functions of the devaluation circuit18, the parity prediction circuit20, the left shift circuit22, and the adder26inFIG. 1. For example, the left shift circuit122shifts each bit of the mantissa F3to the left only by a bit value (any one of zero to three) of lower two bits of the exponent E3. An example of the mantissa F4generated by the left shift circuit122is illustrated inFIG. 3.

The intermediate register123holds an exponent E4output from the devaluation circuit118and a mantissa F4output from the left shift circuit122and outputs the held exponent E4and mantissa F4to the digit alignment shift circuit200. A function of the digit alignment shift circuit200is similar to the function of the digit alignment shift circuit24inFIG. 1. An example of the digit alignment shift circuit200is illustrated inFIG. 4. The loopback register127holds the exponent E5from the digit alignment shift circuit200and the mantissa F5from the adder126and outputs the held exponent E5and mantissa F5to the digit alignment shift circuit200and the normalized shift circuit128.

The normalized shift circuit128executes rounding processing on the mantissa F5and expresses the mantissa F5as assuming that there is an implicit one above the most significant bit of the mantissa F5. Furthermore, the normalized shift circuit128adjusts the exponent E5according to the rounding processing. Then, the normalized shift circuit128outputs the normalized exponent E5and mantissa F5as a calculation result.

InFIG. 3, an example of the mantissa F4generated by the left shift circuit122inFIG. 2is illustrated. For easy understanding, inFIG. 3, lower 16 bits in the mantissae F3and F4are extracted. It is assumed that a parity DP be added to each four bits of the mantissae F3and F4. In this case, the left shift circuit122generates the mantissa F4by left-bit shifting the mantissa F3by a number as many as a bit value (any one of zero to three) of lower two bits of the exponent E3. Furthermore, parities DP3to DP0corresponding to a bit shift amount are selected from among the parities DP (four DP3, four DP2, four DP1, and four DPO corresponding to four bit shift amounts) predicted by the parity prediction circuit120.

In a case where the shift amount is zero bit, correspondence between each four bits of the mantissa F4with the parity DP is the same as the correspondence between each four bits of the mantissa F3with the parity DP. In a case where the shift amounts are one, two, and three bits, the parity DP corresponding to the mantissa F4is different from the parity DP corresponding to the mantissa F3. Therefore, the left shift circuit122selects the parity DP according to the bit shift amount from among the parities DP predicted by the parity prediction circuit20.

In a region that indicates the mantissa F4shifted by three bits from zero bit shift inFIG. 3, a broken line of an oval indicates that parities DP (DP3to PD0) corresponding to the respective four bits in the mantissa F4are generated. The parity prediction circuit120inFIG. 2generates prediction values of 16 parities DP corresponding to 16 ovals inFIG. 3. Then, as described above, the left shift circuit122selects four parities DP according to the bit shift amount from among the16parities DP and includes the selected parities DP in the mantissa F4. Furthermore, inside of parentheses below each data bit indicates a bit position before shifting the corresponding data bit.

FIG. 4is a block diagram illustrating an example of the digit alignment shift circuit200inFIG. 2. The digit alignment shift circuit200includes a comparator201, a differential unit202, a replacement selector203, a right shift circuit204, and a selector205.

The comparator201compares the exponent E4from the intermediate register123and the exponent. E5from the loopback register127and outputs a comparison result to the selector205and the replacement selector203. The differential unit202calculates a difference between the exponent E4from the intermediate register123and the exponent E5from the loopback register127as an absolute value and outputs the calculated difference to the right shift circuit204. Here, because lower bits of both of the exponents E4and E5are zero, lower two bits of the difference output by the differential unit202are zero.

The replacement selector203outputs one of the mantissae F4and F5having the smaller one of the exponents E4and E5to the right shift circuit204on the basis of the comparison result by the comparator201and outputs a mantissa having the larger one of the exponents E4and E5to the adder126. Note that, in a case where the exponents E4and E5are equal to each other, the replacement selector203outputs the mantissae F4and F5to the right shift circuit204and the adder126, respectively, without replacing the mantissae F4and F5.

The right shift circuit204shifts the mantissa (F4or F5) supplied from the replacement selector203to the right only by the number of bits indicated by the difference from the differential unit202and outputs the right-shifted mantissa to the adder126. The right shift circuit204is an example of a bit shift circuit. Here, because lower two bits of the difference output from the differential unit202are zero, a right shift amount is a multiple of four.

Therefore, a parity DP corresponding to the right-shifted mantissa can use a parity DP corresponding to a mantissa before being right-shifted without newly generating the parity DP. As a result, because it is not necessary to provide a parity prediction circuit corresponding to the right shift circuit204, a shift operation by the right shift circuit204can be performed at higher speed than that in a case where the parity prediction circuit is provided.

The selector205outputs the larger one of the exponents E4and E5as a new exponent E5on the basis of the comparison result by the comparator201. Here, because lower bits of the exponents E4and E5are zero, lower two bits of the new exponent E5output by the selector205are also zero.

FIG. 5is a block diagram illustrating an example of the right shift circuit204inFIG. 4. InFIG. 5, for example, an example in which a parity DP [15:0] is generated for each four bits of 64-bit data R [63:0] and an example in which a parity DP [7:0] is generated for each eight bits of the 64-bit data R [63:0] are illustrated. The data R corresponds to a mantissa F. A reference numeral SA indicates a shift amount signal indicating a shift amount from zero bit to 63 bits and corresponds to the difference output from the differential unit202inFIG. 4.

In a case where the parity DP is generated for each four bits (n=2), the left shift circuit122inFIG. 2performs left-shifting by a number same as the bit value of the lower two bits of the exponent E3in advance. Therefore, a shift amount signal SA [1:0] is constantly 00, and it can be unnecessary to include a shift circuit (shift circuit212ato be described later illustrated inFIG. 8or the like) that shifts data R1[63:0] to the right by zero bit, one bit, two bits, or three bits.

A shift circuit204ain a first stage receives the mantissa F4generated by the left shift circuit122or the mantissa F5held by the loopback register127. Then, the shift circuit204auses a 4:1 selector according to a shift amount signal SA [3:2] and shifts the data R1[63:0] to the right by zero bit, four bits, eight bits, or 12 bits.

A shift circuit204bat a second stage uses a 4:1 selector according to a shift amount signal SA [5:4] and shifts data output from the shift circuit204ato the right by zero bit, 16 bits, 32 bits, or 48 bits. As a result, the right shift circuit204can shift 4·p (p is integer equal to or more than zero) bits to the right according to a shift amount signal SA [5:0] and generate the data R [63:0] and a parity DP [15:0]. Note that, because a correspondence relationship between the four bits of the data R [63:0] and each parity DP does not change, the parity DP [15:0] is not newly generated and is reused.

In a case where a parity DP is generated for each eight bits (n =3), a left shift circuit corresponding to the left shift circuit122inFIG. 2performs left-shifting in advance by a number as many as the bit value of the lower three bits of the exponent E3. Therefore, the shift amount signal SA [2:0] is constantly 000. A shift circuit204cat a first stage uses a 4:1 selector according to a shift amount signal SA [4:3] and shifts the data R1[63:0] and a parity RP1[7:0] to the right by zero bit, eight bits, 16 bits, or 24 bits.

A shift circuit204dat a second stage uses a 2:1 selector according to a shift amount signal SA [5] and shifts data output from the shift circuit204cto the right by zero bit or 32 bits. As a result, the right shift circuit204can shift 8·p (p is integer equal to or more than zero) bits to the right according to a shift amount signal SA [5:0] and generate the data R [63:0] and the parity DP [7:0]. Note that, because a correspondence relationship between the eight bits of the data R [63:0] and each parity DP does not change, the parity DP [7:0] is not newly generated and is reused.

As illustrated inFIG. 5, for example, the right shift circuit204that generates the parity DP for each four bits in the digit alignment shift circuit200can include the two-stage shift circuits204aand204b. Similarly, the right shift circuit204that generates the parity DP for each eight bits in the digit alignment shift circuit200can include the two-stage shift circuits204cand204d. Because the right shift circuit204can omit a shift circuit corresponding to the shift amount signal SA [2:0], it is possible to achieve acceleration for one stage of the shift circuit.

As described above, in the present embodiment, as in the embodiment described above, it is possible to make the parity prediction circuit be unnecessary to be mounted on the digit alignment shift circuit200. Therefore, a circuit delay of the digit alignment shift circuit200can be reduced. Moreover, in the present embodiment, in the right shift circuit204, it can be unnecessary to provide the shift circuit that shifts the data R1[63:0] to the right by zero bit, one bit, two bits, or three bits. Therefore, a time required for a shift operation by the right shift circuit204can be shortened for one stage of the shift circuit, and the circuit delay of the digit alignment shift circuit200can be further reduced.

As a result, it is possible to perform a floating-point product-sum calculation by the calculation device102at high speed, and it is possible to enhance a performance of the calculation device102. For example, a clock frequency of the calculation device102can be increased by reducing a delay time of a critical path from the intermediate register123to the loopback register127.

FIG. 6is a block diagram illustrating an example of another calculation device. Elements similar to those inFIG. 2are denoted by the same reference numerals, and detailed description is omitted. A calculation device104illustrated inFIG. 6does not include the devaluation circuit118, the parity prediction circuit120, and the left shift circuit122inFIG. 2. Therefore, the exponent E3output from the adder114and the mantissa F3output from the multiplier116are held by the intermediate register123as the exponent E4and the mantissa F4. Furthermore, the calculation device104includes a digit alignment shift circuit210instead of the digit alignment shift circuit200inFIG. 2. Other components of the calculation device104are similar to the components of the calculation device102inFIG. 2.

The exponent E4stored in the intermediate register123is an addition result of the exponents E1and E2by the adder114, and lower two bits of the exponent E4are any one of zero to three. Similarly, the exponent E5stored in the loopback register127is a result of digit alignment in one-bit units, and lower two bits of the exponent E5are any one of zero to three.

FIG. 7is a block diagram illustrating an example of the digit alignment shift circuit210inFIG. 6. Elements similar to those inFIG. 4are denoted by the same reference numerals, and detailed description is omitted. The digit alignment shift circuit210includes a right shift circuit212and a parity prediction circuit213instead of the right shift circuit204of the digit alignment shift circuit200inFIG. 4. Furthermore, lower two bits of the exponents E4and E5supplied to the digit alignment shift circuit210, lower two bits of a difference output from the differential unit202, and lower two bits of the exponent E5output from the selector205are any one of zero to three.

Therefore, the right shift circuit212performs right-bit-shifting in one bit units, for example, from zero bit to 63 bits according to the difference output from the differential unit202. Because right-bit-shifting is not performed in four bit units, the digit alignment shift circuit210predicts a parity DP with respect to a mantissa on which right-bit-shifting has been performed by the parity prediction circuit213.

FIG. 8is a block diagram illustrating an example of the right shift circuit212inFIG. 7. Detailed description of elements similar to those inFIG. 5will be omitted. InFIG. 8, for example, an example is illustrated in which a parity DP [15:0] is generated for each four bit of 64-bit data R [63:0]. The right shift circuit212includes shift circuits212a,212b, and212chaving a three-stage configuration. Functions of the shift circuits212band212care respectively the same as the functions of the shift circuits204aand204binFIG. 5.

The shift circuit212auses the 4:1 selector according to a shift amount signal SA [1:0] and shifts the data D [63:0] to the right by zero bit, one bit, two bits, or three bits. For example, the shift circuit212ashifts the data D [63:0] to the right by q (q is any one of zero to three) bits according to the shift amount signal SA [1:0] and outputs the data as the data R1[63:0].

Furthermore, the shift circuit212aselects the parity DP [15:0] corresponding to each four bits of the data R1[63:0] according to a shift amount from among the parities DP output from the parity prediction circuit213. Then, the shift circuit212aoutputs the data R1[63:0] and the parity RP1[15:0] to the shift circuit212b.

In this way, in a case where the right shift amount by the shift circuit212ais not in four bits units, the parity prediction circuit213is provided that predicts the parity DP added to the data R1[63:0] shifted by the shift circuit212a. This causes a delay penalty used for parity generation. Furthermore, the right shift circuit212mounts shift circuits212a,212b, and212cthat include one more stage than that inFIG. 5. Therefore, a time required for a right shift operation according to the shift amount signal SA [5:0] is longer than the right shift circuit204inFIG. 5.

FIG. 9is a circuit diagram illustrating an example of the shift circuit212ainFIG. 8. InFIG. 9, an example of a 4:1 selector corresponding to a third digit (R1[15:12], RP1[3]) in the shift circuit212ais illustrated. Each 4:1 selector selects an input corresponding to a bit value of the shift amount signal SA [1:0] and outputs the selected input as data R1[15:12] and the parity RP1[3] . For example, in a case where the bit value of the shift amount signal SA [1:0] is 01, five 4:1 selectors output data D [16:13] and the parity DP [1] respectively as the data R1[15:12] and the parity RP1[3].

FIG. 10illustrates an example of an operation of the shift circuit212ainFIG. 8. Detailed description of the operations similar to those inFIG. 3will be omitted. InFIG. 10, a one-bit right-shift example and a three-bit right-shift example are illustrated.

In a case where the shift amount signal SA [1:0] =01, the shift circuit212ashifts each bit to the right by one bit, inserts zero to the most significant bit, and gets the least significant bit out. Furthermore, the shift circuit212aselects a corresponding parity DP from among the parities DP predicted by the parity prediction circuit213in correspondence with each shifted digit (four bits).

In a case where the shift amount signal SA [1:0]=11, the shift circuit212ashifts each bit to the right by three bits, inserts zero into the most significant three bits, and gets the least significant three bits out. Furthermore, the shift circuit212aselects a corresponding parity DP from among the parities DP predicted by the parity prediction circuit213in correspondence with each shifted digit (four bits).

FIG. 11illustrates an example of a calculation device according to another embodiment. Elements similar to those inFIG. 4are denoted by the same reference numerals, and detailed description is omitted. A calculation device106illustrated inFIG. 11includes an intermediate register130that holds the exponent E3output from the adder114and the mantissa F3output from the multiplier116. Then, the calculation device106achieves a calculation method of a product-sum calculation.

The devaluation circuit118executes devaluation processing of the exponent E3by setting lower two bits of the exponent E3held by the intermediate register130to zero. The left shift circuit122shifts each bit of the mantissa F3held by the intermediate register130to the left by a bit value of the two lower bits of the exponent E3held by the intermediate register130(any one of zero to three).

Note that the lower two bits correspond to n of the number of bits 4 (=2n) of the mantissa F3used to generate each parity DP by the parity prediction circuit120. Therefore, the number of lower bits of the exponent E3set to zero by the devaluation circuit118is not limited to two bits, and may also be determined as n in correspondence with the number of bits 2nof the mantissa F3used to generate each parity DP by the parity prediction circuit120.

For example, the intermediate register130is arranged in a case where a sum of a multiplication time by the multiplier116and operation times by the parity prediction circuit120and the left shift circuit122exceeds a clock cycle time required for the multiplication of the mantissae F1and F2by the multiplier116. As a result, the parity prediction circuit120and the left shift circuit122can be arranged between the multiplier116and the intermediate register123without decreasing a clock frequency.

On the other hand, in a case where the intermediate register130is not arranged, the sum of the multiplication time by the multiplier116and a circuit delay time by the parity prediction circuit120and the left shift circuit122is included in the clock cycle time required for the multiplication of the mantissae F1and F2by the multiplier116. Therefore, in a case where the sum of the multiplication time by the multiplier116and the operation times by the parity prediction circuit120and the left shift circuit122is set to be within the clock cycle time required for the multiplication of the mantissae F1and F2by the multiplier116, it is necessary to decrease the clock frequency. In this case, there is a possibility that an effect of reducing the circuit delay of the digit alignment shift circuit200included in the loop path is canceled by the decrease in the clock frequency, and there is a possibility that a performance of the calculation device106is deteriorated.

As described above, in this embodiment, effects similar to those of the above-described embodiment can be obtained. Moreover, in the present embodiment, by arranging the intermediate register130according to the circuit delay time of the parity prediction circuit120and the left shift circuit122, it is possible to achieve the functions of the digit alignment shift circuit200described above without decreasing the clock frequency. As a result, it is possible to perform a floating-point product-sum calculation by the calculation device106at high speed, and it is possible to enhance a performance of the calculation device106.

From the detailed description above, characteristics and advantages of the embodiments will become apparent. This intends that claims cover the characteristics and advantages of the embodiment described above without departing from the spirit and the scope of the claims. Furthermore, one of ordinary knowledge in the technical field may easily achieve various improvements and modifications. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and the scope of the inventive embodiment may rely on appropriate improvements and equivalents included in the scope disclosed in the embodiment.