Electric optical device and electronic device

An electric optical device includes a transistor that includes a semiconductor layer having a source region connected to a data line, a drain region connected to a pixel electrode, and a channel region, and a gate electrode, a first light blocking film that is formed to be wider than the gate electrode and that is connected to the gate electrode via a first contact hole which is opened in a first insulating film disposed on the gate electrode, and a second light blocking film that is provided between the semiconductor layer and a substrate and is connected to the first light blocking film via a second contact hole which is opened to penetrate the first insulating film, a gate insulating film, and a second insulating film.

BACKGROUND

1. Technical Field

The present invention relates to an electric optical device such as, for example, a liquid crystal display, a manufacturing method thereof, and an electronic device including the electric optical device, for example, such as a liquid crystal projector.

2. Related Art

A liquid crystal display which is an example of electric optical devices may be used as a light modulation unit (that is, a light valve) of, for example, a projection type display device. Strong light is incident to the light valve from a light source, and, at this time, if a semiconductor layer forming a TFT (thin film transistor) in the light valve is irradiated with the light, this results in a light leakage current, which causes flickering or pixel unevenness to occur in a display image. In order to prevent this, a light blocking film may be provided in a laminated structure as a light blocking mechanism for blocking the incident light.

Here, the TFT may be formed in a self-aligning manner by implanting an impurity into the semiconductor layer using a gate electrode as a mask during the manufacturing thereof. For example, JP-A-2008-77030 discloses a technique in which, in such a TFT, the gate electrode is made of a conductive material having a light blocking property, and the gate electrode is provided to fill in a groove formed along the semiconductor layer, thereby blocking light coming in a tilted direction from entering the semiconductor layer. Also, JP-A-2007-142320 discloses a technique in which a first layer of the gate electrode functioning as a mask when the semiconductor layer is formed in a self-aligning manner, and a second layer which is formed to be wider than the first layer in order to prevent light from a light source from entering the semiconductor layer, are formed, and thereby the TFT can be formed in the self-aligning manner and the light blocking property of the TFT can be improved.

However, the TFTs disclosed in JP-A-2008-77030 and JP-A-2007-142320 require an annealing process for activating the impurities implanted into the semiconductor layer after forming the gate electrode functioning as a light blocking film, during the manufacturing process. The gate electrode is made of a light blocking material with a relatively high OD (optical density) value such as, for example, titanium nitride (TiN), tungsten silicide (WSi), but if these materials are exposed to high temperature due to the annealing process, the OD value is lowered, and the light blocking property is deteriorated. For this reason, the TFTs disclosed in JP-A-2008-77030 and JP-A-2007-142320 have technical problems in that, due to the manufacturing process and the structural characteristics, the light blocking property of the gate electrode functioning as a light blocking film is reduced due to the annealing process, and thus it is difficult to sufficiently decrease the light leakage current.

SUMMARY

An advantage of some aspect of the invention is to provide an electric optical device, and a manufacturing method thereof, and an electronic device, capable of suppressing a light leakage current by improving the light blocking property in a transistor which can be formed in a self-aligning manner.

According to an aspect of the invention, there is provided an electric optical device including a data line and a scan line intersecting each other; a pixel electrode provided in a pixel corresponding to an intersection of the data line and the scan line; a transistor including (i) a semiconductor layer having a first source/drain region electrically connected to the data line, a second source/drain region electrically connected to the pixel electrode, and a channel region provided between the first source/drain region and the second source/drain region, and (ii) a gate electrode disposed so as to be opposed to the channel region via a gate insulating film; an upper side light blocking film that is formed to have a part overlapping with the gate electrode further to the upper layer side than the gate electrode via an upper side insulating film and is electrically connected to the gate electrode via a first contact hole which is opened in the upper insulating film; and a lower side light blocking film that is formed further to the lower layer side than the semiconductor layer via a lower side insulating film and is electrically connected to the upper side light blocking film via a second contact hole which is opened to penetrate the upper side insulating film, the gate insulating film, and the lower side insulating film.

According to the electric optical device in an aspect of the invention, for example, an image signal is controlled from the data line to the pixel electrode, and thus image display is possible in a so-called active matrix type. The image signal is supplied from the data line to the pixel electrode via the transistor at a predetermined time by the transistor electrically connected between the data line and the pixel electrode being turned on or off. The pixel electrode is a transparent electrode made of a transparent conductive material such as, for example, ITO (indium tin oxide), and is provided in plurality, for example, in a matrix, at a region forming a display region on a substrate, corresponding to the intersection of the data line and the scan line which intersect each other on the substrate.

The transistor has the semiconductor layer and the gate electrode. The semiconductor layer includes the first source/drain region, the second source/drain region, and the channel region. The first source/drain region is electrically connected to the data line, and the second source/drain region is electrically connected to the pixel electrode. The transistor outputs the image signal which is supplied to the first source/drain region from the data line to the pixel electrode electrically connected to the second source/drain region, according to the switching-on and off operations.

The gate electrode is disposed so as to be opposed to the channel region via the gate insulating film. The gate electrode is formed to overlap with the channel region, for example; in a plan view on the substrate. For this reason, when the electric optical device according to an aspect of the invention is manufactured, the gate electrode is used as a mask when impurities are implanted into the semiconductor layer by an ion implantation method.

The upper side light blocking film according to an aspect of the invention is formed further to the upper layer side than the gate electrode via the upper side insulating film. Thereby, light from a light source which comes from the upper side can be blocked from entering the semiconductor layer, and a light leakage current is suppressed from being generated in the semiconductor layer. In an aspect of the invention, particularly, the upper side light blocking film is formed to have a part overlapping with the gate electrode in a plan view on the substrate, and thus it is possible to more efficiently suppress the generation of the light leakage current.

The upper side light blocking film is electrically connected to the gate electrode via the first contact hole which is opened in the upper side insulating film which is provided between the upper side light blocking film and the gate electrode. For this reason, the upper side light blocking film is applied with the same voltage as the gate electrode, and, that is, the upper side light blocking film functions as a portion of the gate electrode.

The lower side light blocking film according to an aspect of the invention is formed further to the lower layer side than the semiconductor layer via the lower side light blocking film. For this reason, light from a light source which comes from the lower side can be blocked from entering the semiconductor layer, and a light leakage current is suppressed from being generated in the semiconductor layer.

The lower side light blocking film is electrically connected to the upper side light blocking film via the second contact hole. The second contact hole which is opened so as to penetrate the upper side insulating film, the gate electrode, and the lower side insulating film, and the upper side light blocking film makes an electric connection between the gate electrode and the lower side light blocking film as a relay layer, due to the upper side light blocking film formed along the inner walls of the second contact hole.

Here, since the upper side light blocking film is formed along the inner walls of the second contact hole, light from a light source which comes from the lateral side can be blocked from entering the semiconductor layer. In other words, of the upper side light blocking film, the part which is provided in the second contact hole functions as a wall-shaped light blocking body, thus can block incident light which is obliquely incident from entering the semiconductor layer, and it is possible to further block the light from entering the semiconductor layer.

In the electric optical device according to an aspect of the invention which has such a laminated structure on the substrate, during the manufacturing thereof, when the transistor is formed, the upper side light blocking film can be formed after the completion of the annealing process for activating the impurities which has been implanted into the semiconductor layer. Thereby, the upper side light blocking film is not exposed to high temperatures during the manufacturing, and the OD value thereof is not lowered. As a result, the upper side light blocking film having a good light blocking property is provided, and thus it is possible to efficiently suppress the light leakage current from being generated in the semiconductor layer. In addition, a manufacturing method of the electric optical device according to an aspect of the invention will be described later.

As described above, according to an aspect of the invention, it is possible to implement the electric optical device provided with the transistor which can be formed in a self-aligning manner and has a good light blocking performance.

In the electric optical device, the gate electrode and the upper side light blocking film may include the same material.

In the electric optical device, the upper side light blocking film electrically connected to the gate electrode may be made of the same material as the gate electrode. Thereby, a periphery of an attached portion between the gate electrode and the upper side light blocking film can be appropriately formed, and a contact resistance in the attached portion can be suppressed.

In the electric optical device, the semiconductor layer may include a junction region formed between the second source/drain region and the channel region, and the upper side light blocking film may be formed to surround the junction region.

In the electric optical device, the semiconductor layer may include a junction region. The junction region means a PN junction region, specifically, for example, when the transistor is formed as a PNP transistor or an NPN transistor (that is, an N channel transistor or a P channel transistor). Alternatively, the junction region means an LDD region when the transistor has an LDD structure (that is, an impurity region which is formed in the semiconductor layer through an impurity implantation by an ion implantation method).

If the junction region is irradiated with light, a light leakage current may be generated in the transistor. Therefore, as described above, the upper side light blocking film is formed to surround the junction region, and thereby it is possible to enhance the light blocking for the semiconductor layer and to efficiently suppress the generation of the light leakage current.

In addition, a junction region may be formed between the first source/drain region and the channel region. In this case, as compared with a case where the junction region formed between the first source/drain region and the channel region is irradiated with light, the light leakage current may be easily generated in the transistor in a case where the junction region formed between the second source/drain region and the channel region is irradiated with light. Therefore, as described above, the upper side light blocking film is formed to focus on and surround the junction area formed between the second source/drain region and the channel region, and thus it is possible to efficiently suppress the leakage current and to prevent reduction in an aperture ratio more than is necessary.

In the electric optical device, the second contact hole may be formed along the semiconductor layer from a flank of a part where the upper light blocking film overlaps with the channel region in a plan view.

In the electric optical device, typically, the gate electrode is formed on a substrate along the semiconductor layer from a flank of a part overlapping with the channel region of the semiconductor layer in a plan view or in a three-dimensional view (hereinafter, a portion protruding along the elongated direction of the semiconductor layer is appropriately referred to as a “protruding portion.”).

Here, “the flank overlapping with the channel region” may mean both flanks, that is, a pair of protruding portions may protrude from both flanks of the semiconductor layer which extends in the elongate shape. Alternatively, “the flank overlapping with the channel region” may mean one flank. In addition, “the flank overlapping with the channel region” has some distance from the channel region in the direction perpendicular to the elongated direction of the semiconductor layer and means that the protruding portion protrudes from the semiconductor layer with some distance in its origin side.

In addition, the protruding portion may protrude from one flank or both flanks of the semiconductor layer towards the source region, or may protrude from one flank or both flanks of the semiconductor layer towards the drain region. The protruding portion may protrude towards both the source region and the drain region. In other words, the protruding portions may protrude from the four flanks of a single semiconductor layer up to a maximum of four.

In the electric optical device, the upper side light blocking film may have an OD value of two or more.

In the electric optical device, during the manufacturing thereof, when the transistor is formed, the upper side light blocking film can be formed after the completion of the annealing process for activating impurities implanted into the semiconductor layer. Therefore, the upper side light blocking film is formed without an affect by the annealing process performed for the semiconductor layer, and thus has a good light blocking property with an OD value of two or more.

In the electric optical device, the first contact hole may be integrally formed with the second contact hole.

In the electric optical device, there is no gap between the first contact hole and the second contact hole. Therefore, the upper side light blocking film formed so as to fill in the first contact hole and the second contact hole integrally functions as a wall-shaped light blocking film for the semiconductor layer and can further improve the light blocking performance.

According to an aspect of the invention, there is provided a manufacturing method of an electric optical device including a data line and a scan line intersecting each other on a substrate, a pixel electrode provided in a pixel corresponding to an intersection of the data line and the scan line, and a transistor including (i) a semiconductor layer having a first source/drain region electrically connected to the data line, a second source/drain region electrically connected to the pixel electrode, and a channel region provided between the first source/drain region and the second source/drain region, and (ii) a gate electrode disposed so as to be opposed to the channel region via a gate insulating film, the method including a first step of forming a lower side light blocking film on the substrate; a second step of forming a lower side insulating film on the lower side light blocking film; a third step of forming the semiconductor layer, the gate insulating film, and the gate electrode on the lower side insulating film, a fourth step of implanting an impurity into the semiconductor layer using the gate electrode as a mask and activating the implanted impurity through an annealing process; a fifth step of forming an upper side insulating film on the gate electrode and forming a first contact hole in the upper side insulating film; a sixth step of forming a second contact hole so as to penetrate the lower side insulating film, the gate insulating film, and the upper side insulating film; and a seventh step of forming an upper side light blocking film such that the upper side light blocking film is electrically connected to the gate electrode via the first contact hole and the second contact hole, in a plan view on the substrate.

According to the invention, it is possible to appropriately manufacture the above-described electric optical device (including the various aspects).

In the invention, particularly, the annealing process is performed in the fourth step before the fifth step of forming the upper side light blocking film on the substrate. Therefore, the upper side light blocking film is not exposed to high temperatures due to the annealing process. Specifically, in the related art, due to the structural limit thereof, since the upper side light blocking film is required to be formed before the annealing process, the upper side light blocking film is exposed to high temperatures due to the annealing process, and thus it is difficult to obtain a sufficient light blocking property. In contrast, in the invention, since the annealing process is completed before the upper side light blocking film is formed, it is possible to manufacture the electric optical device including the upper side light blocking film having a sufficient light blocking property (typically, having a high OD value of two or more).

In addition, in the sixth step, the upper side light blocking film may be made of the same material as the gate electrode. Further, the first contact hole and the second contact hole may be formed together. The first contact hole and the second contact hole may be integrally formed with each other.

An electronic device in an aspect of the invention includes the electric optical device according to an aspect of the invention, and thus it is possible to implement various kinds of electronic devices capable of displaying high quality images such as a projection type display device, a television set, a portable telephone, an electronic diary, a portable audio player, a word processor, a digital camera, a view finder type or a monitor direct view type video tape recorder, a workstation, a video phone, a POS terminal, a device including a touch panel, and the like.

Operations and other advantages of the invention will be apparent from the embodiments described below.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Each example of the electric optical device, a manufacturing method thereof, and an electronic device according to an embodiment of the invention will be described with reference to the accompanying drawings. In addition, in this embodiment, a TFT active matrix driving type liquid crystal display in which driving circuits are embedded will be described as an example of the electric optical device.

First, an entire configuration of the liquid crystal display according to this embodiment will be described with reference toFIGS. 1 and 2.FIG. 1is a plan view illustrating a TFT array substrate along with respective constituent elements provided thereon when seen from an opposite substrate side, andFIG. 2is a cross-sectional view taken along the line II-II inFIG. 1.

InFIGS. 1 and 2, in the liquid crystal display according to this embodiment, a TFT array substrate10and an opposite substrate20are disposed opposite to each other. The TFT array substrate10is formed of a transparent substrate such as, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the opposite substrate20is formed of a transparent substrate such as, for example, a quartz substrate or a glass substrate. A liquid crystal layer50is interposed between the TFT array substrate10and the opposite substrate20. The TFT array substrate10and the opposite substrate20are attached to each other by a sealing member52provided in a sealing region which is positioned in the periphery of an image display region10acorresponding to a region in which a plurality of pixels100care provided.

The sealing member52is made of, for example, a UV curing resin, or a thermoset resin, or UV curing and thermoset resin, or the like, in order to attach both the substrates together, and is applied on the TFT array substrate10in the manufacturing step, and then is cured by UV irradiation, heating, or the like. In the sealing member52, gap materials such as glass fibers or glass beads for maintaining the gap between the TFT array substrate10and the opposite substrate20to be a predetermined value are dispersed. Also, the gap materials may be mixed with or added to the sealing member52, or may replace the sealing member52, and then may be disposed in the image display region10aor in the peripheral region around the image display region10a.

InFIG. 1, a frame light blocking film53which has a light blocking property and defines a frame region of the image display region10ais provided on the opposite substrate20side along the inside of the sealing region in which the sealing member52is disposed. However, a portion or the entirety of the frame light blocking film53may be provided as a light blocking film embedded in the TFT array substrate10side.

Of the periphery region, in a region positioned outside the sealing region where the sealing member52is disposed of the peripheral region, data line driving circuits101and external circuit connection terminals102are provided along one side of the TFT array substrate10. A sampling circuit7is provided in the inner side than the sealing region along the one side so as to be covered by the frame light blocking film53. Scan line driving circuits104are provided inside the sealing region along two sides adjacent the one side so as to be covered by the frame light blocking film53.

On the TFT array substrate10, upper and lower connecting terminals106are provided regions facing four corners of the opposite substrate20so as to make a connection between both the substrates using upper and lower connecting materials107. Thereby, the TFT array substrate10can be electrically connected to the opposite substrate20. In addition, drawing wires90are formed to make an electric connection between the external circuit connection terminals102, the data line driving circuits101, the scan line driving circuits104, the upper and lower connecting terminals106, and the like.

InFIG. 2, a laminated structure including TFTs which are used to switch pixels, and wires such as scan lines, data lines, and the like is formed on the TFT array substrate10. Although a detailed configuration of the laminated structure is omitted inFIG. 2, a pixel electrode9a, made of a transparent material such as ITO, is formed in an island shape with a predetermined pattern for each pixel, on the laminated structure.

The pixel electrode9ais formed in the image display region10aon the TFT array substrate10so as to be opposed to an opposite electrode21described later. An alignment layer16is formed on a surface in the TFT array substrate10coming into contact with the liquid crystal layer50, that is, on the pixel electrodes9aso as to cover the pixel electrodes9a.

A light blocking film23is formed on an opposite surface to the TFT array substrate10in the opposite substrate20. The light blocking film23is formed in a reticular pattern, for example, when seen from the opposite surface in the opposite substrate20, that is, in a plan view. In the opposite substrate20, non-aperture regions are defined by the light blocking film23, and regions partitioned by the light blocking film23form aperture regions through which light emitted from, for example, lamps for a projector or backlight for direct views. In addition, the light blocking film23may be formed in a stripe shape, and the non-aperture regions may be defined by various kinds of constituent elements such as the light blocking film23and the data lines provided on the TFT array substrate10side.

Opposite electrodes21made of a transparent material such as ITO are formed to be opposed to the plurality of pixel electrodes9aon the light blocking film23. On the light blocking film23, color filters (not shown inFIG. 2) may be formed in the aperture regions and regions including a portion of the non-aperture regions, for color display in the image display region10a. An alignment layer22is formed on the opposite electrodes21in the opposite surface of the opposite substrate20.

Further, on the TFT array substrate10shown inFIGS. 1 and 2, in addition to the data line driving circuits101, the scan line driving circuits104, the sampling circuit7, and the like, a pre-charge circuit which supplies a pre-charge signal with a predetermined voltage level to the plurality of data lines6apreceding the image signal, an inspection circuit used to inspect quality, defects, and the like of the corresponding liquid crystal display whilst manufacturing the liquid crystal display or at the time of the shipment thereof, may be formed.

Next, an electric configuration of the pixel portion of the liquid crystal display according to this embodiment will be described with reference toFIG. 3. Here,FIG. 3shows an equivalent circuit diagram of various kinds of elements and wires in the plurality of pixels which forms the image display region of the liquid crystal display and are formed in a matrix.

InFIG. 3, the pixel electrode9a, and the TFT30, which is an example of a “transistor” according to an embodiment of the invention, are formed for each of the pixels forming the image display region10A and formed in the matrix. The TFT30is electrically connected to the pixel electrode9aand controls the switching of the pixel electrode9aduring operation of the liquid crystal display. The data line6asupplied with an image signal is electrically connected to a source terminal of the TFT30. The image signals S1, S2, . . . , and Sn written in the data lines6amay be sequentially supplied one by one, or may be supplied for each group including adjacent data lines6a.

Also, the scan lines11are electrically connected to gate terminals of the TFTs30, and, in the liquid crystal display, scan signals G1, G2, . . . , and Gm are sequentially applied to the scan lines11one by one in a pulse form at predetermined timings. The pixel electrodes9aare electrically connected to drain terminals of the TFTs30, and the TFTs30, which are switching elements, are turned on during constant periods, and thus the image signals S1, S2, . . . , and Sn supplied from the data lines6aare written in the pixel electrodes9aat predetermined timings. The image signals S1, S2, . . . , and Sn with predetermined levels written in the liquid crystal, which is an example of an electric optical material, via the pixel electrodes9aare stored between the liquid crystal and the opposite electrodes formed on the opposite substrate over a fixed period.

The liquid crystal forming the liquid crystal layer50(refer toFIG. 2) alters alignment or order of molecular sets due to applied voltage levels, and thereby light can be modulated and a grayscale display can be performed. If the liquid crystal is in a normally white mode, the transmittance of incident light decreases, and if the liquid crystal is in a normally black mode, the transmittance of incident light increases according to a voltage applied to each pixel. Therefore, light having the contrast corresponding to the image signals is emitted from the entire liquid crystal display.

Here, in order to prevent the stored image signals from being leaked, an accumulation capacitor70is formed in parallel to a liquid crystal capacitor formed between the pixel electrode9aand the opposite electrode21(refer toFIG. 2). The accumulation capacitor70is a capacitive element functioning as a storage capacitor which temporarily maintains a potential at each pixel electrode9aaccording to the supply of the image signals. One electrode of the accumulation capacitor70is connected to the drain terminal of the TFT30in parallel to the pixel electrode9a, and the other electrode thereof is connected to a capacitance line300so as to have a constant value. Due to the accumulation capacitor70, the voltage maintaining characteristic in the pixel electrode9acan be improved, and the display characteristics such as improvement in contrast or reduction in flickering can be improved. In addition, the accumulation capacitor70functions as an internal light blocking film which blocks light from entering the TFT30as described later.

Next, the shape of the gate electrode of the liquid crystal display according to this embodiment will be described with reference toFIGS. 4 to 6. Here,FIG. 4is a plan view illustrating a planar shape of the gate electrode of the liquid crystal display according to this embodiment.FIG. 5is a cross-sectional view taken along the line V-V inFIG. 4, andFIG. 6is a cross-sectional view taken along the line VI-VI inFIG. 4.

In addition, inFIGS. 4 to 6, for better recognition of respective layers and members, the respective layers and members are different from each other in scale in the figures. Further, inFIGS. 4 to 6, for convenience of description, constituent elements positioned on the conductive light blocking film710are not shown in the figures.

InFIG. 4, the scan line11extends in the X direction, and the data line6a(not shown) extends in the Y direction so as to intersect the scan line11. The TFT30for pixel switching is provided at the intersection of the scan line11and the data line6a.

The scan line11, the data line6a, the conductive light blocking film710, and the TFT30are disposed in the non-aperture regions which surround the aperture region (that is, a region through or from which light actually contributing to the display in each pixel is transmitted or reflected) of each pixel corresponding to the pixel electrode9a(not shown) in a plan view on the TFT array substrate10. In other words, the scan line11, the data line6a, the conductive light blocking film710, and the TFT30are disposed in the non-aperture regions so as not to hinder the display.

InFIGS. 4 and 6, the TFT30includes a semiconductor layer1aand a gate electrode31.

The semiconductor layer1ais made of, for example, polysilicon, and includes a channel region1a′ having a channel length in the Y direction, a data line side LDD region1b, a pixel electrode side LDD region1c, a data line side source/drain region1d, and a pixel electrode side source/drain region1e.That is to say, the TFT30has an LDD structure. Here, the data line side source/drain region1bis an example of a “first source/drain electrode” according to an embodiment of the invention, and the pixel electrode side source/drain region1eis an example of a “second source/drain region” according to an embodiment of the invention. In addition, the pixel electrode side LDD region1cis an example of a “junction region” according to an embodiment of the invention.

The data line side source/drain region1dand the pixel electrode side source/drain region1eare nearly mirror-symmetrical with respect to the channel region1a′ in the Y direction. The data line side LDD region1bis formed between the channel region1a′ and the data line side source/drain region1d. The pixel electrode side LDD region1cis formed between the channel region1a′ and the pixel electrode side source/drain region1e.

The data line side LDD region1band the pixel electrode side LDD region1care respectively formed by impurity regions having a lower concentration of impurities than the data line side source/drain region1dand the pixel electrode side source/drain region1e. Due to the impurity regions, it is possible to reduce an off current flowing through the source/drain regions during non-operation of the TFT30and suppress the reduction in an on current flowing during operation of the TFT30. In this embodiment, particularly, the TFT30is a self-aligning transistor formed by implanting impurities with high concentration by an ion implantation method using the gate electrode31as a mask.

As shown inFIGS. 5 and 6, the gate electrode31is disposed over the semiconductor layer1a, and is made of, for example, a light blocking conductive material with a relatively high OD value such as, titanium nitride (TiN) or tungsten silicide (WSi). The gate electrode31functions as a mask when impurities are implanted into the semiconductor layer1a, and thus the length thereof corresponds with the length of the channel region1a′ in the Y direction as shown inFIG. 4. In addition, an insulating film2(refer toFIGS. 5 and 6) which is an example of a “gate insulating film” according to an embodiment of the invention makes an insulation between the gate electrode31and the semiconductor layer1a.

As shown inFIGS. 5 and 6, the conductive light blocking film710is disposed on the upper layer side via an interlayer insulating film41(refer toFIG. 6) which is an example of an “upper side insulating film” according to an embodiment of the invention when seen from the TFT30on the TFT array substrate10, and is made of the same material as the gate electrode31, for example, a light blocking conductive material with a relatively high OD value such as, titanium nitride (TiN) or tungsten silicide (WSi).

As shown inFIG. 4, the conductive light blocking film710has an extending portion710awhich is provided extending along both sides of the pixel electrode side LDD region1c. In other words, the conductive light blocking film710has a shape which overlaps with the gate electrode31and partially surrounds both sides of the pixel electrode side LDD region1c(that is, a reverse U shape). In addition, the conductive light blocking film710is an example of an “upper side light blocking film” according to an embodiment of the invention. Further, as shown inFIGS. 4 and 5, a groove810which is an example of a “second contact hole” according to an embodiment of the invention is formed in an insulating film2and a bottom insulating film12.

As shown inFIG. 6, the conductive light blocking film710is electrically connected to the gate electrode31via a contact hole820formed in the interlayer insulating film41. Thereby, the conductive light blocking film710is applied with the same potential as the gate electrode31. In addition, the contact hole820is an example of a “first contact hole” according to an embodiment of the invention.

As shown inFIG. 4, in this embodiment, the groove portion810and the contact hole820are integrally formed with each other, and thus there is no gap between the groove portion810and the contact hole820. Therefore, the conductive light blocking film710, which is formed to fill in the groove portion810and the contact hole820, integrally functions as a wall-shaped light blocking film for the semiconductor layer1a, and thus can further improve the light blocking performance.

The bottom insulating film12is an example of a “lower side insulating film” according to an embodiment of the invention. In addition to the function of insulating the TFT30from the scan line11, the bottom insulating film12is formed on the entire surface of the TFT array substrate10, and thus has a function of preventing the roughness during the polishing of the surface of the TFT array substrate10or preventing deterioration in the characteristics of the TFT30for the pixel switching due to pollutants remaining after the cleaning.

The groove portion810reaches the scan line11by penetrating the insulating film2and the bottom insulating film12, and the conductive light blocking film710formed in the groove portion810is electrically connected to the scan line11. Thereby, the conductive light blocking film710formed in the groove portion810is formed as a wall-shaped light blocking body along the pixel electrode side LDD region1cof the semiconductor layer1ain a three-dimensional view.

Therefore, incident light (that is, incident light having components traveling in the X direction or the Y direction inFIG. 4) which is obliquely incident to the pixel electrode side LDD region1ccan be blocked by the conductive light blocking film710formed in the groove portion810. In other words, due to the conductive light blocking film710formed in the groove portion810as the wall-shaped light blocking body disposed around the pixel electrode side LDD region1c, it is possible to enhance light blocking performance regarding the incident light which is obliquely incident to the pixel electrode side LDD region1c. As a result, it is possible to suppress the light leakage current in the semiconductor layer1aand to reduce flickering or pixel unevenness during the image display.

On the other hand, the groove portion810may be formed in one side of the pixel electrode side LDD region1c(the left side or the right side inFIG. 5), and the conductive light blocking film710may be formed only in one side of the pixel electrode side LDD region1c. In this case as well, it is possible to enhance the light blocking performance for the incident light which is obliquely incident to the pixel electrode side LDD region1c, accordingly. However, from the viewpoint of enhancing the light blocking performance, the conductive light blocking film710is preferably formed in both sides of the pixel electrode side LDD region1cas in this embodiment.

As shown inFIGS. 5 and 6, the scan line11is disposed under the semiconductor layer1avia the bottom insulating film12, and, is made of, for example, a light blocking conductive material such as high-melting metal materials including tungsten (W), titanium (Ti), and titanium nitride (TiN). The scan line11includes a main line portion11xwhich is patterned in a stripe shape in the X direction and an extending portion11ywhich extends from the main line portion11xin the Y direction, in a plan view on the TFT array substrate10.

As shown inFIG. 4, the scan line11includes regions opposite to the channel region1a′, the data line side LDD region1b, the pixel electrode side LDD region1c, the data line side source/drain region1d, and the pixel electrode side source/drain region1e, of the TFT30. Therefore, the scan line11can completely or nearly completely block returning light such as light reflected from the rear surface of the TFT array substrate10, or light which is generated from other liquid crystal display in a double-plate type projector or the like and passes through a synthesis optical system, from entering the channel region1a′ of the TFT30. In other words, the scan line11functions as a wire supplying the scan signal and can block the returning light from entering the TFT30. Therefore, the light leakage current in the TFT30is reduced during operation of the liquid crystal display, and thus it is possible to increase the contrast ratio and realize high definition image display.

Further, as shown inFIG. 4, the conductive light blocking film710surrounds the pixel electrode side LDD region1c. Thereby, the conductive light blocking film710, the gate electrode31, and the scan line11can block most of light from entering the pixel electrode side LDD region1c.

Here, during operation of the TFT30, the light leakage current may be relatively easily generated in the pixel electrode side LDD region1cas compared with the data line side LDD region1b. In other words, during operation of the TFT30, in a case where light enters the pixel electrode side LDD region1c, the light leakage current is easily generated in the TFT30as compared with a case where light enters the data line side LDD region1b. Therefore, as described above, due to the formation of the conductive light blocking film710, it is possible to increase the light blocking performance for the pixel electrode side LDD region1cin which the light leakage current is relatively easily generated and to efficiently reduce the light leakage current flowing through the TFT30.

As shown inFIG. 6, on the upper layer side of the conductive light blocking film710, a relay electrode720which is electrically connected to the data line side source/drain region1dvia the contact hole81is formed and a relay electrode730which is electrically connected to the pixel electrode side source/drain region1evia the contact hole83is formed, via an interlayer insulating film42.

Due to the formation of the relay electrodes720and730, it is possible to reduce an electric resistance between, for example, the data line6aor the pixel electrode9awhich is disposed on the upper layer side of the relay electrodes720and730, and the semiconductor layer1a, or to prevent disconnection of the lines.

As described above, in the liquid crystal display having the laminated structure, during the manufacturing thereof, when the TFT30is formed, the conductive light blocking film710can be formed after the completion of the annealing process for activating the impurities implanted into the semiconductor layer1a. For this reason, the conductive light blocking film710is not exposed to high temperatures, and the OD value thereof is not lowered. As a result, since the conductive light blocking film710having a good light blocking property is provided, it is possible to efficiently suppress the light leakage current from being generated in the semiconductor layer1a.

Manufacturing Method

With reference toFIGS. 7A to 7F, a manufacturing method of the liquid crystal display according to this embodiment described above will be described.FIGS. 7A to 7Fare cross-sectional views illustrating respective steps in a manufacturing method according to a manufacturing order, based on the configurations of the cross-sections shown inFIGS. 5 and 6.

InFIG. 7A, a substrate10such as, for example, a silicon substrate, a quartz substrate, or a glass substrate is prepared. Here, preferably, a pre-process is performed for the substrate10through heat treatment under an inert gas atmosphere of N2(nitrogen) at a high temperature of about 850 to 1300° C. and more preferably 1000° C. such that distortion occurring in the substrate10in a subsequent high-temperature process decreases.

Next, using metal such as, for example, Ti, Cr, W, Ta, Mo, or Pd, or a metal alloy film such as metal silicide, a light blocking layer with the film thickness of about 100 to 500 nm and preferably about 200 nm is formed on the entire surface of the substrate10having undergone the process by a sputtering method or the like, and then the scan line11having the pattern as shown inFIG. 4is formed by, for example, a photolithography method and an etching process.

Thereafter, the bottom insulating film12made of silicon nitride film, silicon oxide film, or the like is formed on the scan line11by, for example, an atmospheric pressure CVD, a low pressure CVD, or the like. In addition, a polysilicon film forming the semiconductor layer1ais grown in a solid phase on the bottom insulating film12, and the semiconductor layer1ahaving a predetermined pattern shown inFIG. 4is formed by, for example, a photolithography method and an etching process. The insulating film2forming a gate insulating film is formed on the semiconductor layer1a.

A conductive layer forming the gate electrode31made of a light blocking conductive material with a relatively high OD value such as titanium nitride (TiN), tungsten silicide (WSi), or the like is formed on the insulating film2. The conductive layer is formed as the gate electrode31having a predetermined pattern shown inFIG. 4by, for example, a photolithography method and an etching process.

Thereafter, as shown inFIG. 7B, a resist film60is formed on the gate electrode31, and, an impurity is implanted from the upper layer side using the resist film60as a mask by, for example, an ion implantation method. In a plan view on the TFT array substrate10, the impurity is blocked by the resist film60in the region overlapping with the resist film60, and thus a concentration difference in the impurity to be implanted occurs between the regions corresponding to the data line side source/drain region1dand the pixel electrode side source/drain region1eand other regions.

Next, as shown inFIG. 7C, after the resist film60is removed, an impurity is implanted from the upper layer side using the gate electrode31as a mask by, for example, an ion implantation method, thereby forming the data line side LDD region1b, the pixel electrode side LDD region1c, the data line side source/drain region1d, the pixel electrode side source/drain region1e, and the channel region1a′ in a self-aligning method.

Thereafter, an annealing process is performed for the semiconductor layer1ainto which the impurity has been implanted, so as to activate the impurity implanted into the semiconductor layer1a, thereby forming the data line side LDD region1b, the pixel electrode side LDD region1c, the data line side source/drain region1d, the pixel electrode side source/drain region1e, and the channel region1a′.

Next, as shown inFIG. 7D, the interlayer insulating film41is formed on the TFT30, and the groove portion810and the contact hole820are formed by, for example, a photolithography method and an etching process. The groove portion810is deeply formed such that the bottom of the groove portion810exposes the surface of the scan line11. In addition, the contact hole820is deeply formed such that the bottom of the contact hole820exposes the surface of the gate electrode31.

Thereafter, as shown inFIG. 7E, a conductive film forming the conductive light blocking film710is formed on the upper layer side so as to fill in the groove portion810and the contact hole820(that is, so as to cover at least the inner walls). The conductive film is made of a conductive material with a relative high OD value such as, for example, titanium nitride (TiN), or tungsten silicide (WSi). The conductive film is formed as the conductive light blocking film710having a predetermined pattern shown inFIGS. 4 to 6by, for example, a photolithography method and an etching process.

In this way, since the conductive light blocking film710is formed after the annealing process performed for the semiconductor layer1ais finished, it is not exposed to high temperatures. For this reason, the OD value of the light blocking material such as, for example, titanium nitride (TiN) or tungsten silicide (WSi) is not lowered. Therefore, it is possible to form the conductive light blocking film710having a good light blocking property and to efficiently suppress the light leakage current from being generated in the semiconductor layer1a.

Thereafter, as shown inFIG. 7F, the interlayer insulating film42is formed on the conductive light blocking film710, and the contact holes81and83are formed in the interlayer insulating film42. Further, the relay electrodes720and730are formed so as to fill in the contact holes81and83, thereby completing the liquid crystal display according to this embodiment.

Electronic Device

With reference toFIG. 8, a case of applying the above-described liquid crystal display to a projector which is an example of an electronic device will be described. The liquid crystal display is used as a light valve of the projector.FIG. 8is a plan view illustrating a configuration example of the projector.

As shown inFIG. 8, a lamp unit1102including a white light source such as a halogen lamp is provided inside the projector1100. Projection light emitted from the lamp unit1102is divided into the three primary colors light of RGB by four mirrors1106and two dichroic mirrors1108which are disposed in a light guide1104, and then is incident to liquid crystal panels1110R,1110B and1110G which are light values corresponding to the respective primary colors.

A configuration of each of the liquid crystal panels1110R,1110B and1110G is the same as the configuration of the above-described liquid crystal display, and they are driven using primary color signals of R, G and B supplied from an image signal processing circuit. The light modulated by the liquid crystal panels is incident to a dichroic prism1112in three directions. In the dichroic prism1112, the R and B light is refracted by 90 degrees and the G light travels in a straight line. Therefore, as a result of synthesis of images of the respective colors, a color image is projected onto a screen or the like via a projection lens1114.

In terms of images displayed by the respective liquid crystal panels1110R,1110B and1110G, images displayed by the liquid crystal panels1110R and1110B are required to be mirror-reverse to images displayed by the liquid crystal panel1110G.

In addition, since light beams corresponding to the primary colors R, G and B are incident to the respective liquid crystal panels1110R,1110B and1110G, there is no need for color filters.

In addition to the electronic device described above with reference toFIG. 8, the electronic device includes a mobile type personal computer, a portable telephone, a liquid crystal television set, a view finder type or a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic diary, an electronic calculator, a word processor, a workstation, a video phone, a POS terminal, a device including a touch panel, and the like. The invention is also applicable to these various kinds of electronic devices.

The invention is not limited to the above-described embodiment but may be appropriately modified without departing from or being contrary to the scope and spirit of the invention which are readable from the appended claims and the specification, and thus a substrate for an electric optical device, an electric optical device, and an electronic device are also included in the technical scope of the invention.

The entire disclosure of Japanese Patent Application No. 2010-050233, filed Mar. 8, 2010 is expressly incorporated by reference herein.