THIN FILM TRANSISTOR, DISPLAY DEVICE, AND THIN FILM TRANSISTOR MANUFACTURING METHOD

Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.

TECHNIC FIELD

The present invention relates to a bottom-gate thin film transistor, a display apparatus, and a method for manufacturing a thin film transistor.

BACKGROUND ART

Thin film transistors (TFTs) are for example widely used as switching elements for pixels in display apparatuses such as liquid-crystal displays and organic electro-luminescence (EL) displays.

The thin film transistors have a configuration in which a gate electrode, an insulating layer, a semiconductor layer (a channel layer), a source electrode, and a drain electrode are formed on a substrate. In particular, bottom-gate thin film transistors are characterized in that the gate electrode is located closer to the substrate than the channel layer.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

Manufacturing of bottom-gate thin film transistors as channel-etched thin film transistors involves the following problem. That is, etching of channel layers, which is performed in a process of the manufacturing, makes it difficult to control a remaining film amount in the channel layers, and consequently there is relatively great variation in characteristics among the thus manufactured thin film transistors.

The present invention has been made in view of the circumstances described above, and an object thereof is to provide thin film transistors that show little characteristic variation, a display apparatus including such thin film transistors, and a method for manufacturing such thin film transistors.

Solution to Problem

A thin film transistor according to the present application includes a gate electrode, a gate insulating film, a semiconductor layer, an etch stop layer, and a source electrode and a drain electrode. The gate electrode is disposed on a substrate. The gate insulating film covers the gate electrode. The semiconductor layer is disposed on the gate insulating film. The semiconductor layer includes a polysilicon film located within a range defined by the gate electrode in a plan view. The etch stop layer is disposed on the polysilicon film. The source electrode and the drain electrode are disposed on the semiconductor layer with a space therebetween. The polysilicon film has first and second regions that are not covered by the etch stop layer. A portion of the source electrode is located over the first region, and a portion of the drain electrode is located over the second region.

A display apparatus according to the present application includes a plurality of display elements and a plurality of thin film transistors that select or drive the respective display elements. Each of the thin film transistors is the thin film transistor according to the present application described above. Each of the thin film transistors selects or drives the corresponding display element when the display element is to be displayed.

A method for manufacturing a thin film transistor according to an aspect of the present application includes: forming a gate electrode on a substrate; forming a gate insulating film to cover the gate electrode; forming a semiconductor layer including an amorphous silicon film on the gate insulating film; forming an etch stop layer on the semiconductor layer; forming a polysilicon film within a range defined by the gate electrode in a plan view by irradiating a portion of the amorphous silicon film with energy beams from above through the etch stop layer; removing portions of the etch stop layer so that the polysilicon film has first and second regions that are not covered by the etch stop layer; and forming a source electrode and a drain electrode on the semiconductor layer with a space therebetween so that a portion of one of the source electrode and the drain electrode is located over the first region, and a portion of another of the source electrode and the drain electrode is located over the second region.

A method for manufacturing a thin film transistor according to another aspect of the present application includes: forming a gate electrode on a substrate; forming a gate insulating film to cover the gate electrode; forming a semiconductor layer including an amorphous silicon film on the gate insulating film; forming a polysilicon film within a range defined by the gate electrode in a plan view by irradiating a portion of the amorphous silicon film with energy beams; forming an etch stop layer on the semiconductor layer; removing portions of the etch stop layer so that the polysilicon film has first and second regions that are not covered by the etch stop layer; and forming a source electrode and a drain electrode on the semiconductor layer with a space therebetween so that a portion of one of the source electrode and the drain electrode is located over the first region, and a portion of another of the source electrode and the drain electrode is located over the second region.

Advantageous Effects of Invention

The present invention allows control of a remaining film amount in channel layers and reduction in characteristic variation.

DESCRIPTION OF EMBODIMENTS

The following describes embodiments of the present invention in detail based on the drawings.

FIG. 1is a cross-sectional view schematically illustrating a configuration of a thin film transistor according to Embodiment 1.FIG. 2is a plan view schematically illustrating a configuration of main elements of the thin film transistor. The thin film transistor according to Embodiment 1 includes a gate electrode2, a gate insulating film3, a semiconductor layer (a channel layer)4, an etch stop layer5A, a source electrode6, and a drain electrode7. Note thatFIG. 2, which is a plan view, illustrates a positional relationship between the gate electrode2, a polysilicon film42, the etch stop layer5A, the source electrode6, and the drain electrode7, and does not show other elements of configuration of the thin film transistor in order to simplify the drawing.

The gate electrode2is formed on a surface of a substrate1by patterning. Examples of materials that can be used for formation of the gate electrode2include metals such as Al, Mo, Cr, Ta, Cu, and Ti; alloys containing at least one of the metals as a main component; and metal oxides. An insulating substrate such as a glass substrate is for example used as the substrate1.

The gate insulating film3is formed so as to cover the gate electrode2on the substrate1. The gate insulating film3may be an insulating film of an organic material or an insulating film of an inorganic material. For example, tetraethyl orthosilicate (TOS) can be used for the insulating film of an organic material. For example, SiO2, SiO2/SiN, SiN, and SiON can be used for the insulating film of an inorganic material.

The semiconductor layer4includes a first amorphous silicon film41, the polysilicon film42, a second amorphous silicon film43, and an n+silicon film44. The first amorphous silicon film41is formed on the gate insulating film3and has a thickness of at least 250 Å. The polysilicon film42is formed on the gate insulating film3as well as the first amorphous silicon film41and resides in the same layer as the first amorphous silicon film41. The polysilicon film42contains polycrystalline silicon microcrystalline silicon, which has a smaller grain size than the polycrystalline silicon, or monocrystalline silicon. In a plan view of the present embodiment, the polysilicon film42is located within a range defined by the gate electrode2(a range defined by a perimeter of the gate electrode2, which in an example illustrated inFIG. 2is a rectangular region).

The second amorphous silicon film43is formed on the first amorphous silicon film41and the polysilicon film42, and has a thickness of approximately 500 to 900 Å. The n+silicon film44is a semiconductor film containing a high concentration of impurity such as phosphorus and arsenic. The n+silicon film44is formed on the second amorphous silicon film43.

The etch stop layer5A is an insular film formed on the polysilicon film42. The etch stop layer5A can for example be formed using a material such as SiO2. According to the present embodiment, the polysilicon film42extends beyond a range of the etch stop layer5A, having regions421and422that are not covered by the etch stop layer5A. That is, in a plan view, the regions421and422of the polysilicon film42are located outside a range defined by the etch stop layer5A (a range defined by a perimeter of the etch stop layer5A). The regions421and422protrude from the etch stop layer5A by protrusion lengths D1and D2, respectively, and the protrusion lengths D1and D2are preferably each at least 3 μm. Note that the protrusion length D1does not have to be equal to the protrusion length D2so long as the protrusion lengths D1and D2are each at least 3 μm. The protrusion lengths and D2may be each less than 3 μm. In such a configuration, the protrusion length D1is preferably equal to the protrusion length D2.

The source electrode6and the drain electrode7each having a desired pattern are formed on the semiconductor layer4(the n+silicon film44) with a space therebetween. Examples of materials that can be used for formation of the source electrode6and the drain electrode7include metals such as Al, Mo, Cr, Ta, Cu, and Ti; alloys containing at least one of the metals as a main component; and metal oxides.

According to the present embodiment, the source electrode6and the drain electrode7are respectively located toward the region421(a first region) and the region422(a second region) that are not covered by the etch stop layer5A of the polysilicon film42. In other words, a portion of the source electrode6is located over the region421, and a portion of the drain electrode7is located over the region422.

FIG. 3is a graph illustrating characteristics of the thin film transistor. The graph shown inFIG. 3illustrates a relationship between the protrusion lengths D1and D2by which the polysilicon film42protrudes from the etch stop layer5A and a value of electric current that flows between the source electrode6and the drain electrode7when the thin film transistor is on. The protrusion length D1at the source electrode6is equal to the protrusion length D2at the drain electrode7. The horizontal axis of the graph shown inFIG. 3represents one of the protrusion lengths D1(D2), and the vertical axis represents the electric current value between the source electrode6and the drain electrode7when the thin film transistor is on.

The graph shown in FIG,3indicates that almost no electric current flows between the source electrode6and the drain electrode7in a configuration in which the polysilicon film42barely extends beyond the range of the etch stop layer5A, that is, in a configuration in which the protrusion lengths D1and D2of the polysilicon film42are each substantially zero.

By contrast, electric current flows between the source electrode6and the drain electrode7when the thin film transistor is on as long as the polysilicon film42extends beyond the range of the etch stop layer5A, that is, as long as the protrusion lengths D1and D2of the polysilicon film42are each a finite length.

The value of the electric current that flows between the source electrode6and the drain electrode7when the thin film transistor is on is proportional to the protrusion lengths D1and D2on condition that the protrusion lengths D1and D2of the polysilicon film42are each less than 3 μm. That is, in a configuration in which the protrusion lengths D1and D2are each less than 3 μm but the protrusion lengths D1and D2are different from each other, the value of the electric current that flows from the source electrode6to the drain electrode7through the semiconductor layer4differs from the value of the electric current that flows from the drain electrode7to the source electrode6, which may cause characteristic variation among thin film transistors. The protrusion lengths D1and D2are therefore preferably equal to each other in a configuration in which the protrusion lengths D1and D2of the polysilicon film42are each less than 3 μm.

The value of the electric current that flows between the source electrode6and the drain electrode7is approximately constant without dependence on the protrusion lengths D1and D2on condition that the protrusion lengths D1and D2of the polysilicon film42are each greater than or equal to 3 μm. Therefore, the protrusion lengths D1and D2do not have to be equal to each other in a configuration in which the protrusion. lengths D1and D2of the polysilicon film42are each greater than or equal to 3 μm.

FIGS. 4A to 4Dare cross-sectional views schematically illustrating a manufacturing method of the thin film transistor according to Embodiment 1. First, a metal film is deposited by sputtering on the surface of the insulating substrate1such as a glass substrate using, as a material, a metal such as Al, Mo, Cr, Ta, Cu, and Ti, an alloy containing at least one of the metals as a main component, or a metal oxide. The gate electrode2is formed by patterning through photolithography with a photomask, dry etching of the metal film, photoresist removal, and washing.

Next, a film is deposited by chemical vapor deposition ((ND) using a material such as SiO2and SiN to form the gate insulating film3so as to cover the gate electrode2on the substrate1.

Next, an amorphous silicon film having a thickness of approximately 500 to 700 Å is deposited by CVD to form the first amorphous silicon film41as an upper layer of the gate insulating film3. Also, an SiO2film having a thickness of approximately 500 to 1,000 Å is deposited by CVD to form the etch stop layer5A as an upper layer of the first amorphous silicon film41.FIG. 4Aillustrates a phase in which the etch stop layer5A has been formed.

Next, dehydrogenation is caused to give a hydrogen concentration of no greater than 2% in the first amorphous silicon film41, and annealing is performed on the first amorphous silicon film41by irradiation within the range defined by the gate electrode2in a plan view with laser light (for example, energy beams such as an excimer laser) from above through the etch stop layer5A. As a result of the annealing, a portion of amorphous silicon in the first amorphous silicon film41turns polycrystalline silicon to form the polysilicon film42in the same layer as the first amorphous silicon film41.FIG. 4Billustrates a phase in which the polysilicon film42has been formed.

Next, the etch stop layer5A is formed insular through photolithography with a photomask, dry etching of the etch stop layer5A, photoresist removal, and washing. The photolithography with a photomask is carried out and dry etching of the first amorphous silicon film41is also carried out so that the thickness of the first amorphous silicon film41is at least 250 Å and the polysilicon film42has regions that are not covered by the etch stop layer5A (the polysilicon film42extends beyond the range of the etch stop layer5A, according to the present embodiment).FIG. 4Cillustrates a phase in which the insular etch stop layer5A has been formed.

Next, an amorphous silicon film having a thickness of approximately 500 to 900 Å is deposited by CVD to form the second amorphous silicon film43. Also, an amorphous silicon film containing a high concentration of impurity such as phosphorus and arsenic is deposited by CVD to form the n+silicon film44as an upper layer of the second amorphous silicon film43.

Next, a metal film is deposited by sputtering using, as a material, a metal such as Al, Mo, Cr, Ta, Cu, and Ti, an alloy containing at least one of the metals as a main component, or a metal oxide. The source electrode6and the drain electrode7are formed as an upper layer of the semiconductor layer4by patterning through photolithography with a photomask, dry etching of the metal film, photoresist removal, and washing. The photolithography with a photomask and the dry etching of the metal film are carried out so that the source electrode6and the drain electrode7in the upper layer of the semiconductor layer4are spaced, and the source electrode6and the drain electrode7are respectively located toward the region421and the region422that are not covered by the etch stop layer5A of the polysilicon film42.FIG. 4Dillustrates a phase in which the source electrode6and the drain electrode7have been formed.

In order to apply the thin film transistor according to Embodiment 1 to a liquid-crystal display apparatus as a switching element, a passivation film, an organic film, and a pixel electrode are formed in order as upper layers of the source electrode6and the drain electrode7.

The passivation film is for example formed as an upper layer of the source electrode6and the drain electrode7by CVD using a material such as SiN. The organic film is formed as an upper layer of the passivation film using a material such as JAS including acrylic resin. Thereafter, a contact hole for the drain electrode7is formed by patterning through photolithography, dry etching, photoresist removal, and washing. Also, an indium tin oxide (ITO) film is deposited as an upper layer of the organic layer by sputtering and patterned to form the pixel electrode.

As described above, according to Embodiment 1, the etch stop layer5A provided as the upper layer of the polysilicon film42prevents the thickness of the polysilicon film42from being reduced due to a process such as the etching in the patterning for the source electrode6and the drain electrode7. That is, according to Embodiment 1, it is possible to control the film thickness in a channel section. Accordingly, it is possible to manufacture thin film transistors that show little characteristic variation even by a low temperature poly-silicon (UPS) process that leaves smaller areas of films having stable characteristics.

Embodiment 1 has been described referring to a configuration in which the insular etch stop layer5A is provided as the upper layer of the polysilicon film42. However, the etch stop layer does not have to be an insular layer.

Embodiment 2 will be described referring to a configuration in which an etch stop layer having a contact hole structure is provided as the upper layer of the polysilicon filet42.

FIG. 5is a cross-sectional view schematically illustrating a configuration of a thin film transistor according to Embodiment 2.FIG. 6is a plan view schematically illustrating a configuration of main elements of the thin film transistor according to Embodiment 2. The thin film transistor according to Embodiment 2 includes the gate electrode2, the gate insulating film3, the semiconductor layer (the channel layer)4, an etch stop layer5B, the source electrode6, and the drain electrode7. Note thatFIG. 6, which is a plan view, illustrates a positional relationship between the gate electrode2, the polysilicon film42, the etch stop layer5B, the source electrode6, and the drain electrode7, and does not show other elements of configuration of the thin film transistor in order to simplify the drawing.

The substrate1is for example a glass substrate. The gate electrode2is formed on the surface of the substrate1by patterning. Examples of materials that can be used for formation of the gate electrode2include metals such as Al, Mo, Cr, Ta, Cu, and Ti; alloys containing at least one of the metals as a main component; and metal oxides.

The gate insulating film3is formed so as to cover the gate electrode2on the substrate1. The gate insulating film3may be an insulating film of an organic material or an insulating film of an inorganic material. For example, TEOS can be used for the insulating film of an organic material. For example, SiO2, SiO2/SiN, SiN, and SiON can he used for the insulating film of an inorganic material.

The semiconductor layer4includes the first amorphous silicon film41, the polysilicon film42, the second amorphous silicon film43, and the n+silicon film44. The first amorphous silicon film41is formed on the gate insulating film3and has a thickness of at least 250 Å. The polysilicon film42is formed on the gate insulating film3as well as the first amorphous silicon film41and resides in the same layer as the first amorphous silicon film41. The polysilicon film42contains polycrystalline silicon, microcrystalline silicon, which has a smaller grain size than the polycrystalline silicon, or monocrystalline silicon. In a plan view of the present embodiment, the polysilicon film42is located within the range defined by the gate electrode2(a rectangular region in an example illustrated inFIG. 6). As in Embodiment 1, the polysilicon film42according to Embodiment 2 is formed by partially performing annealing on the first amorphous silicon film41by irradiation within the range defined by the gate electrode2in a plan view with laser light (for example, energy beams such as from an excimer laser).

The second amorphous silicon film43is formed on the first amorphous silicon film41and the polysilicon film42, and has a thickness of approximately 500 to 900 Å. The n+silicon film44is a semiconductor film containing a high concentration of impurity such as phosphorus and arsenic. The n+silicon film44is formed on the second amorphous silicon film43.

The etch stop layer5B having contact holes51and52is formed on the polysilicon film42. The etch stop layer5B is for example formed by CVD using a material such as SiO2. The contact holes51and52of the etch stop layer5B are formed through processes such as photolithography with a photomask and dry etching of the etch stop layer5B.

The polysilicon film42resides right under the etch stop layer5B. Since the etch stop layer5B has the contact holes51and52, the polysilicon film42has regions423and424that are not covered by the etch stop layer5B. That is, the regions423and424of the polysilicon film42are located within a range defined by the etch stop layer5B (a range defined by a perimeter of the etch stop layer5B) in a plan view. Preferably, lengths D3and D4of the respective regions423and424in a direction in which the source electrode6and the drain electrode7are spaced are each at least 3 μm. Note that the length D3does not have to be equal to the length D4so long as the lengths D3and D4are each at least 3 μm. The lengths D3and D4may be each less than 3 μm. In such a configuration, the length D3is preferably equal to the length D4.

The source electrode6and the drain electrode7each having a desired pattern are formed on the semiconductor layer4(the n+silicon film44) with a space therebetween. Examples of materials that can be used for formation of the source electrode6and the drain electrode7include metals such as Al, Mo, Cr, Ta, Cu, and Ti; alloys containing at least one of the metals as a main component; and metal oxides.

According to the present embodiment, the source electrode6and the drain electrode7are respectively located toward the region423(the first region) and the region424(the second region) that are not covered by the etch stop layer5B of the polysilicon film42. In other words, a portion of the source electrode6is located over the region423, and a portion of the drain electrode7is located over the region424.

A manufacturing method of the thin film transistor according to Embodiment 2 is similar to the manufacturing method according to Embodiment 1. According to Embodiment 2, the etch stop layer5B provided as the upper layer of the polysilicon film42prevents the thickness of the polysilicon film42from being reduced due to a process such as the etching in the patterning for the source electrode6and the drain electrode7. That is, it is possible to control the film thickness in the channel section, Accordingly, it is possible to manufacture thin film transistors that show little characteristic variation even by an LTPS process that leaves smaller areas of films having stable characteristics.

Embodiment 1 has a configuration in which the polysilicon film42is formed by partially irradiating the first amorphous silicon film41with laser light after the etch stop layer5A has been formed. However, the irradiation of the first amorphous silicon film41with laser light may be performed before the etch stop layer5A is formed.

Embodiment 3 will be described referring to a method in which the polysilicon film42is formed by partially irradiating the first amorphous silicon film41with laser light before the etch stop layer5A is formed.

FIGS. 7A to 8are cross-sectional views schematically illustrating a manufacturing method of a thin film transistor according to Embodiment 3. First, a metal film is deposited by sputtering on the surface of the insulating substrate1such as a glass substrate using, as a material, a metal such as Al, Mo, Cr, Ta, Cu, and Ti, an alloy containing at least one of the metals as a main component, or a metal oxide. The gate electrode2is formed by patterning through photolithography with a photomask, dry etching of the metal film, photoresist removal, and washing.

Next, a film is deposited by CVD using a material such as SiO2and SiN to form the gate insulating film3so as to cover the gate electrode2on the substrate1. Also, an amorphous silicon film having a thickness of approximately 500 to 700 Å is deposited by CVD to form the first amorphous silicon film41as an upper layer of the gate insulating film3.FIG. 7Aillustrates a phase in which the gate electrode2, the gate insulating film3, and the first amorphous silicon film41have been formed on the substrate1.

Next, dehydrogenation is caused to give a hydrogen concentration of no greater than 2% in the first amorphous silicon film41, and annealing is performed on the first amorphous silicon film41by irradiation within the range defined by the gate electrode2in a plan view with laser light (for example, energy beams such as from an excimer laser). As a result of the annealing, a portion of amorphous silicon in the first amorphous silicon film41turns polycrystalline silicon to form the polysilicon film42in the same layer as the first amorphous silicon film41.FIG. 7Billustrates a phase in which the polysilicon film42has been formed.

Next, an SiO2film having a thickness of approximately 500 to 1,000 Å is deposited by CVD to form the etch stop layer5A as an upper layer of the first amorphous silicon film41and the polysilicon film42.FIG. 7Cillustrates a phase in which the etch stop layer5A has been formed.

Next, the etch stop layer5A is formed insular through photolithography with a photomask, dry etching of the etch stop layer5A, photoresist removal, and washing. The photolithography with a photomask is carried out and dry etching of the first amorphous silicon film41is also carried out so that the thickness of the first amorphous silicon film41is at least 250 Å and the polysilicon film42has regions that are not covered by the etch stop layer5A (the polysilicon film42extends beyond the range of the etch stop layer5A, according to the present embodiment).FIG. 7Dillustrates phase in which the insular etch stop layer5A has been formed.

Next, an amorphous silicon film having a thickness of approximately 500 to 900 Å is deposited by CVD to form the second amorphous silicon film43. An amorphous silicon film containing a high concentration of impurity such as phosphorus and arsenic is deposited by CVD to form the n+silicon film44as an upper layer of the second amorphous silicon film43.

Next, a metal film is deposited by sputtering using, as a material, a metal such as Al, Cr, Ta, Cu, and Ti, an alloy containing at least one of the metals as a main component, or a metal oxide. The source electrode6and the drain electrode7are formed as an upper layer of the semiconductor layer4by patterning through photolithography with a photomask, dry etching of the metal film, photoresist removal, and washing. The photolithography with a photomask and the dry etching of the metal film are carried out so that the source electrode6and the drain electrode7in the upper layer of the semiconductor layer4are spaced, and the source electrode6and the drain electrode7are respectively located toward the region421and the region422that are not covered by the etch stop layer5A of the polysilicon film42.FIG. 8illustrates a phase in which the source electrode6and the drain electrode7have been formed.

In order to apply the thin film transistor manufactured as described above to a liquid-crystal display apparatus as a switching element, a passivation film, an organic film, and a pixel electrode are formed in order as upper layers of the source electrode6and the drain electrode7.

Although the present embodiment has been described referring to a configuration in which the etch stop layer5A is formed insular through photolithography with a photomask, dry etching of the etch stop layer5A, photoresist removal, and washing, the present embodiment may have a configuration in which the etch stop layer5B having a contact hole structure is formed as in Embodiment 2.

Although the present embodiment has been described referring to a configuration in Which the etch stop layer5A is formed by depositing an SiO2film as the upper layer of the first amorphous silicon film41and the polysilicon film42, the present embodiment may alternatively have a configuration in which the insular etch stop layer5A or the etch stop layer5B having a contact hole structure is formed by applying photosensitive spin on glass (SOG) as the upper layer of the first amorphous silicon film41and the polysilicon film42and carrying out photolithography with a photomask. Such a configuration eliminates the need for the etching of the etch stop layer5A or5B, and thus further facilitates control of the film thickness in a contact section.

A display apparatus having a configuration adopting the thin film transistor according to any of the above-described embodiments is described as Embodiment 4.

FIG. 9is a block diagram illustrating the configuration of the display apparatus according to Embodiment 4. The display apparatus illustrated inFIG. 9is an example of a liquid-crystal display apparatus and includes a liquid-crystal display panel100, a gate driver101, a source driver102, a power supply circuit103, image memory104, and a control circuit105.

The control circuit105outputs control signals for separately controlling the gate driver101, the source driver102, the power supply circuit103, and the image memory104in synchronization with an externally input synchronization signal.

The image memory104temporarily stores therein picture data of a display target and outputs the picture data to the source driver102in accordance with a memory control signal input from the control circuit105. The image memory104may be incorporated in the control circuit105and configured to output the picture data to the source driver102after internal processing in the control circuit105.

The power supply circuit103generates voltages such as a drive voltage for the gate driver101and a drive voltage for the source driver102, and supplies the drive voltages to the gate driver101and the source driver102, respectively, in accordance with a power supply control signal input from the control circuit105.

The gate driver101generates a scanning signal for turning on or off switching elements11(seeFIG. 10) of respective pixels10arranged in a matrix in the liquid-crystal display panel100and sequentially applies the generated scanning signal to gate lines connected to the gate driver in accordance with a gate driver control signal input from the control circuit105.

The source driver102generates a data signal corresponding to the picture data input from the image memory104and sequentially applies the generated data signal to source lines connected to the source driver102in accordance with a source driver control signal input from the control circuit105. The data signal applied by the source driver102through the source lines are written to pixels10for which corresponding switching elements11are on.

The present embodiment has been described referring to a configuration in which the gate driver101and the source driver102are provided externally to the liquid-crystal display panel100. However, the present embodiment may alternatively have a configuration in which the gate driver101and the source driver102are mounted on a periphery of the liquid-crystal display panel100.

FIG. 10is a circuit diagram illustrating an example of a configuration of each pixel10. Each pixel10includes a switching element11and a pixel electrode12. The switching element11is for example thin film transistor according to any of Embodiments 1 to 3. The source electrode6is connected to a source line and the drain electrode7is connected to the pixel electrode12. The gate electrode2of the switching element11is connected to a gate line. The switching element11is switched between being on and being off in accordance with the scanning signal supplied to the gate line, and is capable of electrically disconnecting the pixel electrode12from the source line and electrically connecting the pixel electrode12to the source line.

The liquid-crystal display panel100includes a counter electrode13opposed to the pixel electrode12. A liquid crystal substance is enclosed between the pixel electrode12and the counter electrode13thereby to form a liquid crystal capacitor C1, The counter electrode13is connected to a common voltage generator circuit, not shown, and is for example maintained at a fixed potential through application of a common voltage Vcomby the common voltage generator circuit.

Each pixel10includes a storage capacitor C2parallely connected with the liquid crystal capacitor C1. The storage capacitor C2is also charged when a voltage is applied to the pixel electrode12. Thus, a value of the voltage of the pixel10can be maintained by the fixed potential of the storage capacitor C2even while no data voltage is applied through the corresponding source line.

The control circuit105of the liquid-crystal display apparatus controls the transmittance of the liquid crystal substance in each pixel10by controlling the magnitude of the voltage to be applied between the pixel electrode12and the counter electrode13through relevant elements such as the gate driver101and the source driver102. Thus, the control circuit105adjusts the amount of light that passes through the liquid crystal substance for displaying a picture.

The use of the thin film transistor according to any of Embodiments 1 to 3 as the switching element11of each pixel10enables reduction of variation in characteristics among thin film transistors in the liquid-crystal display panel100. It is therefore possible to maintain a good display quality of the liquid-crystal display panel100.

Note that although the liquid-crystal display apparatus is described as an example of the display apparatus according to Embodiment 4, the display device according to Embodiment 4 may have a configuration including the thin film transistors according to any of Embodiments 1 to 3 as switching elements for pixel selection or as switching elements for pixel driving in an organic EL display.

The presently disclosed embodiments are merely examples in all aspects and should not be construed to be limiting. The scope of the present invention is indicated by the claims, rather than by the description given above, and includes all variations that are equivalent in meaning and scope to the claims.

REFERENCE SIGNS LIST