Apparatus and method for controlling voltage and frequency

A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system. The apparatus includes a hardware module, adapted to receive at least one indication of a load of the system and to determine a voltage level and a clock signal frequency to be provided to the system, and a software module, adapted to configure a voltage source and a clock signal source in response to the determination. The method includes: (i) receiving, at a hardware module, indication of a load of a system; (ii) determining, by the hardware module, a voltage level and a clock signal frequency to be provided to the system; and (iii) configuring, by a software module, a voltage source and a clock signal source in response to the determination.

FIELD OF THE INVENTION

The present invention relates to apparatuses and methods for controlling supply voltage and clock signal frequency within a processor based device and.

BACKGROUND OF THE INVENTION

Mobile devices, such as but not limited to personal data appliances, cellular phones, radios, pagers, lap top computers, and the like are required to operate for relatively long periods before being recharged. These mobile devices usually include one or more processors as well as multiple memory modules and other peripheral devices.

In order to reduce the power consumption of mobile devices various power consumption control techniques were suggested. A first technique includes reducing the clock frequency of the mobile device. A second technique is known as dynamic voltage scaling (DVS) or alternatively is known as dynamic voltage and frequency scaling (DVFS) and includes altering the voltage that is supplied to a processor as well as altering the frequency of a clock signal that is provided to the processor in response to the computational load demands (also referred to as throughput) of the processor. Higher voltage levels are associated with higher operating frequencies and higher computational load but are also associated with higher energy consumption.

DVS can be implemented by software. A disadvantage of software based application results from timing issues and the computational load that an execution of such software imposes on a processor.

DVS can also be implemented by hardware. A disadvantage of hardware-based solution resides on their inflexibility and complexity.

Various DVS systems and method are provided at U.S. Pat. No. 6,584,571 of Fung, titled “system and method of computer operating mode clock control for power consumption reduction”, U.S. Pat. No. 6,079,025 of Fung titled “system and method of computer operating mode control for power consumption reduction”, U.S. patent application 20020042887 of Chauvel et al., titled “Dynamic hardware configuration for energy management systems using task attributes”, all being incorporated herein by reference.

There is a need to provide a trade off between software and hardware based DVS apparatuses.

SUMMARY OF THE PRESENT INVENTION

The invention provides a method and an apparatus for controlling voltage level and clock signal frequency supplied to a system. The apparatus includes a hardware module, adapted to receive at least one activity related signal representative of an activity of at least one component of the system and to determine a voltage level and a clock signal frequency to be provided to the system, and a software module, adapted to configure a voltage source and a clock signal source in response to the determination.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following description related to a system that includes a single frequency region. It is noted that this can be applied to a system that includes multiple frequency regions. Typically, multiple frequency regions require separate control for each frequency region.

FIG. 1is a schematic illustration of a system100that includes multiple components such as processor110, memory bank120, I/O modules130, interrupt request controller140, clock signal source220, voltage source210, synchronization control unit230. System100also includes a hardware module200. Conveniently, processor110executes a software module300that with the hardware module200forms apparatus232.

It is noted that system100can have various configurations and that the components illustrated inFIG. 1represent only a single exemplary configuration of system100. Typically system100is includes within a mobile device such as a cellular phone.

The hardware module200is adapted to receive one or more activity related signals representative of an activity of at least one component of the system100and in response determine whether to alter the voltage/frequency provided to the components of system100. Such signals may include, for example, memory access signals (read/write), cache hit/miss signals, bus related signals, processor IDLE signal, various processor instructions, interrupt requests, I/O access, and the like.

Apparatus232is capable of determining the supply voltage and clock signal frequency supplied to system100(said characteristic pair is referred to as voltage/frequency) under various timing constraints that include, for example: the decision period of apparatus232, voltage supply and clock signal supply stabilization period, and system's100and especially processor's110load change rate.

When the load of system100decreases a significant decrement of the voltage/frequency can amount in large power consumption reduction. Nevertheless, the reduction of voltage/frequency shall take into account the next (lower) voltage/frequency to supply to system100.

When the load of system100increases, the voltage/frequency must be increased relatively fast in order to prevent performance penalties that are especially critical when the system100executes a real time program such as a video processing program.

In both cases the apparatus232must track the load of system100in a relatively fast manner but without introducing too many voltage/frequency changes.

The apparatus232can be adapted to apply a first policy when deciding to increase the frequency/voltage supplied to system100and a second policy, that conveniently differs from the first policy, when deciding to decrease the voltage/frequency supplied to system100. It is noted that apparatus232can apply various policies, even the same or substantially the same policies when deciding to increase or decrease the supplied voltage/frequency.

Conveniently, applying different voltage/frequency increment and decrement policies are implemented, for example, by setting different average load thresholds (Nup and Ndown, Lp and Ldown) to various load related events. Those of skill in the art will appreciate that using the same (or substantially the same) voltage/frequency increment and decrement policies can include using the same average load thresholds, but this is not necessarily so.

FIG. 2illustrates apparatus232, according to an embodiment of the invention.

The various tasks associated with controlling and providing voltage and clock signals to system100were divided between the hardware module200and the software module300of apparatus232. The hardware module200receives one or usually multiple activity related signals, applies a load tracking algorithm such as but not limited to the exponential moving average (EMA) algorithm and determine when to alter the voltage/frequency supplied to system100.

The software module300configures the voltage source210and the clock signal source220.

Optionally, the apparatus232includes a prediction module520that predicts how to alter the voltage/frequency in response to previous exponential moving average load estimates. The hardware module200includes programmable components thus allowing alterations of the decision process.

The control of the voltage source210and clock signal source220is relatively simple and does not load the processor110. Furthermore, its simplicity allows components having limited processing capabilities, such as DMA modules and simple controllers, to execute the voltage and clock signal source configuration module310. In addition, various existing processors have the capability of setting voltage and clock signal frequency, thus utilizing this capability further increases the efficiency of apparatus232and system100as a whole.

The apparatus232samples the activity related signals by the clock signal CLK supplied to the system or by a clock signal having a lower frequency, such as CLK_3that is a derivative of CLK.

Said sampling provides a more accurate load level tracking than a system that uses a real time clock that is not influenced by the changes of clock signals provided to the monitored system.

System100receives a supply voltage V(t) as well as a clock signal CLK of a certain frequency F(t) from a synchronization control unit230that synchronizes the levels of V(t) and F(t) such as to prevent, for example, a case in which the supplied voltage V(t) does not allow the system100to operate at a the frequency F(t) of the clock signal. The synchronization control unit230is connected to a clock signal source220for receiving the clock signal and is also connected to a voltage source210for receiving the supply voltage. Conveniently, the clock signal source220includes two phase locked loops, whereas while one is supplying a current clock signal of a current frequency the other can be tuned to supply the next clock signal having a next frequency. The voltage source can also include two voltage sources but this is not necessarily so.

Apparatus232includes a hardware module200that includes a system/processor load tracking unit402, a processing module404and a load tracking frequency/voltage update request module406. The software module300includes a voltage and clock signal source configuration module310.FIG. 2also illustrates two optional modules such as prediction module520and user configures module530, each can be a hardware module, a software module or a combination of both hardware and software.

The voltage and clock signal source configuration module310is capable of configuring the clock signal source220as well as the voltage source210by various prior art methods, such as writing control values to registers accessed by these sources.

The voltage and clock signal source configuration module310is capable of receiving a requests to alter the voltage/frequency from load tracking frequency/voltage update request module406and to convert the request to a format that can be understood by and accessible to the clock signal source220as well as the voltage source210.

Conveniently, the voltage and clock signal source configuration module310receives also a request to alter the voltage/frequency from a prediction module520. According to another embodiment of the invention the voltage and clock signal source configuration module310is also adapted to receive requests from a user-configured module530.

When requests can be provided to the voltage and clock signal source configuration module310from more that a single module it may apply various decision processes to decide how to alter the voltage/frequency. Each request can be assigned with a certain priority and/or weight and any combination of at least one of the requests can be applied. For example, a request of the prediction module520can override a request of the load tracking frequency/voltage update request module406, and a request from the user-configured module530can override both.

System/processor load tracking unit402received multiple activity related signal and is capable of assigning a predefined weight to each signal. Conveniently, the system/processor load tracking unit402tracks the activity of the processor100by monitoring at least one signal such as an IDLE signal and also is also capable of tracking the activity of other components of system.

The a system/processor load tracking module402provides an indication of the activities of various components to a processing module404that outputs a load indication and an exponential moving average load estimate to the load tracking frequency/voltage update request module406and also provides the exponential moving average load estimate to the prediction module520.

FIG. 3is a schematic diagram of various modules402-406of the apparatus232, according to an embodiment of the invention.

System/processor load tracking module402includes modules410and430. Processor load sampling module410samples the IDLE or NON-IDLE (BUSY) signal of processor110. The IDLE or NON-IDLE (BUSY) signal is sampled by CLK and creates IDLE′ sampled signal. Thes IDLE′ sampled signal is provided to a processor load pre-averaging module420that belongs to processing module404. The processor load pre-averaging module420calculates a ratio R between the amounts of clock signals (CLK) during a certain averaging period and between the amount of sampled signal IDLE′ provided by processor load sampling module410during that certain averaging period. The length of the averaging period is programmable. Conveniently, either module410or module420can multiple either IDLE′ or R by a programmable weight W_IDLE. Conveniently, the averaging periods do not overlap, but this is not necessarily so.

Conveniently, processor load pre-averaging module420also divides CLK to generate a slower clock signal CLK_3that is provided to various modules such as modules430and440-490.

System load sampling and weighting module430receives multiple activity related signals from other components of system100, although it can also receive one or more signals (other than IDLE) from processor110. The system load sampling and weighting module430samples the received signals by CLK_3and multiplies each sampled activity related signal by a corresponding programmable weight to provide multiple weighted system activity related signals SL_1-SL_K.

R is also provided to a log buffer560, and conveniently said log buffer560can also receive at least one of the load indication system load indication signals.

Processing module404includes modules420,440and450. Adder module440adds R to the multiple weighted system activity related signals SL_1-SL_K to provide a load indication LL(t).

The load indication LL(t) is provided to a bypass module500as well to a exponential moving average (EMA) module450.

The EMA module450applies an exponential moving average module algorithm that is responsive to at least one programmable parameter α. Basically, EMA performs the following equation: EMA(t)=α*LL(t)+(1−α)*EMA(t−Δt), whereas EMA(t) is an exponential moving average load estimate, α=1/(W+1), W is a positive integer representative of an amount of samples that are taken into account within a programmable window and EMA(t−Δt) is a result of the previous iteration of an EMA calculation. Typically, Δt is responsive to CLK_3and to an amount of clock cycles required for the calculation of EMA(t).

The inventors used an eight bit α, but this is not necessarily so. When α is increased the current value of LL(t) is more dominant thus rapid changes of LL(t) can be tracked. When α is decreased previous samples are more relevant and a more stable tracking process is achieved.

Load tracking frequency/voltage update request module406is adapted to apply different voltage/frequency increment and decrement policies. These different policies are applied by setting different thresholds like Lup and Ldown as well as using two different counters for counting consecutive EMA_higher_than_Lup signals and EMA_lower_than_Ldown signals. According to another embodiment of the invention the load tracking frequency/voltage update request can apply the same (or substantially the same) policies, for example by using a single threshold instead of using a lower threshold and an upper threshold, but this is not necessarily so.

Load tracking frequency/voltage update request module406receives exponential moving average load estimate EMA(t) and compares it in parallel to a upper average load threshold Lup and to a lower average load threshold Ldown. Both load thresholds are programmable. Higher Lup values lead to a slower voltage/frequency update process while lower Ldown values lead to an unstable voltage/frequency update process.

Each time EMA(t) exceeds Lup the dual threshold comparison module460generates a EMA_higher_than_Lup signal. The EMA_higher_than_Lup signal is sent to a first counter module470that counts the amount of consecutive EMA_higher_than_Lup signals. The first counter module470generates a request to increase the voltage/frequency (Req_up(t)) if more than a programmable amount (N_up) of consequent EMA_higher_than_Lup signals were received.

Each time EMA(t) is below Ldown the dual threshold comparison module460generates a EMA_lower_than_Ldown signal. The EMA_lower_than_Ldown signal is sent to a second counter module480that counts the amount of consecutive EMA_lower_than_Ldown signals. The second counter module480generates a request to decrease the voltage/frequency (Req_down(t)) if more than a programmable amount (N_down) of consequent EMA_lower_than_Ldown signals were received.

Req_up(t) and Req_down(t) signals are provided to interfacing logic490that sets various status bits, accessible by software module300, to reflect a received request to alter voltage/frequency. Interfacing logic can also send a request to interrupt request controller140(or directly to processor110) to initiate an interrupt request that enables processor110to execute voltage and clock signal source configuration module310. The voltage and clock signal source configuration module310converts requests to increase or decrease voltage/frequency to commands that control the clock signal source220and the voltage source210accordingly.

The bypass module500receives LL(t) and compares it to a predefined load threshold. If said load threshold is exceeded the bypass module500can send a request to increase the voltage/frequency to interfacing logic490, regardless of the output of modules450-480. The bypass module500allows the apparatus232to respond quickly to sudden system overload situations.

The prediction module520can predict power consumption based upon previously stored load indications, for example the load indications stored at the log buffer560.

According to other embodiments of the invention the prediction module520can response to instructions being executed by processor100. For example, it may predict the load when processor110executes loops, by monitoring various commands, flow changes an/or loop commands fetched by processor110. The prediction module520can include software components, hardware components or a combination of both.

According to an embodiment of the invention the programmable values provided to the apparatus232can be responsive to previously provided values and even to the tasks that are executes by system100and especially processor110. For example, when system100mainly processes video the system100and especially processor110can load a first set of programmable values to the apparatus232, while when executing other tasks, another set of programmable values can be loaded. The programmable values can be also programmed in response to previous voltage/frequency alterations. For example very frequent voltage/frequency alterations can indicate that a slower tracking process is required and vice verse. The programmable values can also be responsive to other parameters such as operating conditions (such as temperature, battery level) of system100and the like.

FIG. 4is a flow chart of a method600for controlling voltage level and clock signal frequency supplied to a system.

Method600starts by stage610of receiving, at a hardware module, at least one activity related signal. Conveniently, stage610includes assigning a weight to each activity related signal.

Referring to the example illustrated byFIG. 1-FIG.3, the processor load sampling module410and the system load sampling and weighting module430receive multiple signals representative of the activities of various components of system100including processor110.

Stage610is followed by stage620of determining, by the hardware module, a voltage level and a clock signal frequency to be provided to the system.

Conveniently, stage620includes calculating an exponential moving average load estimate. Preferably, the exponential moving average load estimate is compared to an upper average load threshold and to a lower average load threshold. Referring to the example illustrated byFIG. 1-FIG.3, said determination is responsive to a calculation process applied by modules420-480. According to another embodiment of the invention the method can include applying the same (or substantially the same) voltage/frequency policies, for example by using a single threshold instead of using an lower average threshold and an upper average threshold, but this is not necessarily so.

Conveniently, stage620further includes comparing a load indication to a load threshold and generating a request to increase the voltage level and clock signal frequency if the load indication exceeds the load threshold. Referring to the example set forth inFIG. 1-FIG.3, this stage can be implemented by bypass module500.

According to an embodiment of the invention stage620is followed by a stage of storing load indications.

According to yet another embodiment of the invention stage620includes estimating future load in response to the stored load indications.

Conveniently, the hardware module applies a first policy for increasing the voltage level and clock signal frequency and a second policy for decreasing the voltage level and clock signal frequency.

Stage620is followed by stage630of configuring, by a software module, a voltage source and a clock signal source in response to the determination. According to a further embodiment of the invention method600includes providing the clock signal to a first portion of the hardware module and providing another clock signal of a lower frequency to a second portion of the hardware module.

Conveniently, method600includes programming at least one programmable parameter of the hardware module.