High-speed resistor-based charge pump for active loop filter-based phase-locked loops

Techniques are described for increasing the speed of a resistor-based charge pump for an active loop filter-based phase-locked loop (PLL). The techniques may include placing a low-resistance discharge path between respective nodes of a current source and sink in a charge pump, and selectively activating the low-resistance discharge path when the charge pump is turned off. The low-resistance discharge path may have a resistance that is lower than the resistance of other current paths between the respective nodes in the charge pump (e.g., current paths formed by the resistors included in the current source and sink of the charge pump), thereby reducing the amount of time needed to reset the charge on the respective nodes when the charge pump is turned off. In this way, the speed of a resistor-based charge pump may be increased, thereby allowing the overall speed of an active filter-based PLL to be increased.

TECHNICAL FIELD

The disclosure relates to electrical circuits, and more particularly, to charge pump-based phase-locked loop (PLL) circuits.

BACKGROUND

Phase-locked loops (PLLs) may be used in a variety of different systems including communication and multimedia systems. PLLs may be used for frequency synthesis, deskewing, clock generation, clock distribution, clock recovery, and other signal processing, timing and/or synchronization purposes.

A PLL may operate as a feedback control system that generates an output signal based on an input signal such that a substantially constant phase delay is maintained between the input and output signals for a given frequency. Designing PLL control loops that can operate at high-speeds may present significant design challenges, particularly in low-voltage applications.

SUMMARY

According to this disclosure, an integrated circuit includes a phase-frequency detector (PFD) having a first output and a second output. The integrated circuit further includes a current source having a control terminal coupled to the first output of the PFD, and an output terminal. The integrated circuit further includes a current sink having a control terminal coupled to the second output of the PFD, and an output terminal coupled to the output terminal of the current source. The integrated circuit further includes a switch having a first conduction electrode coupled to a first node in the current source, a second conduction electrode coupled to a second node in the current sink, and a control electrode. The integrated circuit further includes a control circuit having a first input coupled to the first output of the PFD, a second input coupled to the second output of the PFD, and an output coupled to the control electrode of the switch.

According to this disclosure, an integrated circuit includes a charge pump. The charge pump includes an output terminal. The charge pump further includes a current source including one or more resistors coupled between a first node and the output terminal. The charge pump further includes a current sink including one or more resistors coupled between a second node and the output terminal. The charge pump further includes a switch including a first terminal coupled to the first node of the current source and a second terminal coupled to the second node of the current sink.

According to additional aspects of this disclosure, a method includes selectively closing a switch that connects a first node in a current source of a charge pump to a second node in a current sink of the charge pump based on whether both outputs of a phase-frequency detector (PFD) indicate that a charge pump is to be deactivated.

DETAILED DESCRIPTION

This disclosure describes techniques for increasing the speed of a resistor-based charge pump for an active loop filter-based phase-locked loop (PLL). The techniques may include placing a low-resistance discharge path between respective nodes of a current source and sink in the charge pump, and selectively activating the low-resistance discharge path when the charge pump is turned off. The low-resistance discharge path may have a resistance that is lower than the resistance of other current paths between the respective nodes in the charge pump (e.g., current paths formed by the resistors included in the current source and sink of the charge pump), thereby reducing the amount of time needed to reset the charge on the respective nodes when the charge pump is turned off. In this way, the speed of operation of a resistor-based charge pump may be increased, thereby allowing the overall speed of an active filter-based PLL to be increased.

An active loop filter-based PLL may use a phase-frequency detector (PFD), a resistor-based charge pump, and an active filter to adjust the control voltage of a voltage-controlled oscillator in order to maintain a constant phase relationship between the input and output signals of the PLL. The operation amplifier (op-amp) of the active filter may regulate the output of the charge pump at a reference voltage that is between a high supply voltage and a low supply voltage (e.g., a ground potential).

The charge pump may include a current source and a current sink that each include one or more resistors which determine the level of current produced by the respective source or sink. Prior to turning on the charge pump, a first node in a current source and a second node in the current sink may be initially charged to the reference voltage provided by the active filter.

When both the current source and current sink of the charge pump are turned on, the first node in the current source may be charged to a high supply voltage, and the second node in the current sink may be discharged to a low supply voltage (e.g., a ground potential). When the charge pump is turned off, the resistors in the current source and sink may form a discharge path between the first and second nodes. The discharge path may allow the voltage at the first and second nodes to return to the regulated voltage provided by the active filter. The parasitic capacitance of the nodes and the resistances included in the discharge path may significantly delay the amount of time for the first and second nodes to return to the regulated voltage, thereby decreasing the maximum speed at which the charge pump may operate.

According to this disclosure, a low-resistance discharge path may be coupled between a first node in the current source of the charge pump and a second node in the current sink of the charge pump. The low-resistance discharge path may have a resistance that is lower than the resistance of the current path formed by the resistors in the current source and sink of the charge pump. The relatively low resistance may allow the first and second nodes to return to the regulated voltage in a shorter amount of time than would otherwise occur without the low-resistance discharge path. In this way, the speed of a resistor-based charge pump may be increased, thereby allowing the overall speed of an active filter-based PLL to be increased.

FIG. 1is a block diagram of showing an example phase-locked loop (PLL)10according to this disclosure. PLL10includes a phase-frequency detector (PFD)12, a discharge path control circuit14, a charge pump16, a loop filter18, a voltage controlled oscillator (VCO)20, a frequency divider22, and leads24,26,28,30,32,34,36,38,40. Any combination of the components inFIG. 1may be implemented entirely or partially on one or more integrated circuits.

PFD12has a reference input coupled to a reference lead24, and a feedback input coupled to a feedback lead26. PFD12further includes an UP output (U) coupled to a current source control input of charge pump16and to a first input of discharge path control circuit14via UP lead28. PFD12further includes a DOWN output (D) coupled to a current sink control input of charge pump16and to a second input of discharge path control circuit14via DOWN lead30. An output of discharge path control circuit14is coupled to a discharge path control input of charge pump16via lead32.

Charge pump16includes one or more current amplitude control inputs coupled to leads40. Leads40may be coupled to one or more current amplitude control signal sources. An output of charge pump16is coupled to loop filter18via lead34. An output of loop filter18is coupled to VCO20via lead36. An output of VCO20is coupled to frequency divider22via lead38. An output of frequency divider22is coupled to the feedback input of PFD12via feedback lead26.

In some examples, instead of including a frequency divider22as shown in the example PLL10ofFIG. 1, the output of VCO20may be directly coupled to the feedback input of PFD12via one or more leads.

PFD12is configured to receive a reference signal (or reference clock) (REF) via reference lead24, and a feedback signal (or feedback clock) (FB) via feedback lead26. PFD12is further configured to generate and output the UP and DOWN signals via the UP and DOWN outputs, respectively, based on the reference signal and the feedback signal.

PFD12may start in an initial state where both the UP and DOWN signals are deactivated (e.g., both the UP and DOWN signals are equal to a low voltage state). While in the initial state, PFD12may wait to receive a rising edge of one of the reference and feedback signals. In response to receiving a rising edge of the reference signal prior to a rising edge of the feedback signal, PFD12may activate the UP signal (e.g., transition the UP signal to a high voltage state). After activating the UP signal, PFD12may wait to receive a rising edge from the feedback signal. In response to receiving the rising edge of the feedback signal, PFD12may deactivate both of the UP and DOWN signals. In some cases, to deactivate both of the UP and DOWN signals, PFD12may briefly activate the DOWN signal such that both of the UP and DOWN signals are momentarily activated. In response to both of the UP and DOWN signals being activated, internal circuitry of PFD12may deactivate both of the UP and DOWN signals.

In response to receiving a rising edge of the feedback signal prior to a rising edge of the reference signal, PFD12may activate the DOWN signal (e.g., transition the DOWN signal to a high voltage state). After activating the DOWN signal, PFD12may wait to receive a rising edge from the reference signal. In response to receiving the rising edge of the reference signal, PFD12may deactivate both of the UP and DOWN signals. In some cases, to deactivate both of the UP and DOWN signals, PFD12may briefly activate the UP signal such that both of the UP and DOWN signals are momentarily activated. In response to both of the UP and DOWN signals being activated, internal circuitry of PFD12may deactivate both of the UP and DOWN signals.

The example PFD12described above uses rising edge detection and active high outputs. In other example PLLs, PFD12may include falling edge detection and/or one or more active low outputs.

If the frequencies of the reference and feedback signals are approximately equal, then PFD12may generate the UP and DOWN signals such that the average values (or pulse widths) of the signals are indicative of a phase difference between the reference and feedback signals. For example, if the reference signal leads the feedback signal, PFD12may generate the UP signal such that the average value (or pulse width) of the UP signal is indicative of (or proportional to) the phase difference between the reference and feedback signals (e.g., the amount by which the reference signal leads the feedback signal). On the other hand, if the feedback signal leads the reference signal, PFD12may generate the DOWN signal such that the average value (or pulse width) of the DOWN signal is indicative of (or proportional to) the phase difference between the reference and feedback signals (e.g., the amount by which the feedback signal leads the reference signal). In some examples, the average value of the difference between the UP and DOWN signals may be indicative of (or proportional to) a phase difference between the reference and feedback signals.

If the frequencies of the reference and feedback signals are not equal, then PFD12may generate the UP and DOWN signals such that the UP and DOWN signals (or the average values of the UP and DOWN signals) are indicative of a frequency difference between the reference and feedback signals. For example, PFD12may activate the UP signal for a greater amount of time, on average, than the DOWN signal to indicate that the frequency of the reference signal is greater than the frequency of the feedback signal. On the other hand, PFD12may activate the DOWN signal for a greater amount of time, on average, than the UP signal to indicate that the frequency of the feedback signal is greater than the frequency of the reference signal. In some examples, the average value of the difference between the UP and DOWN signals may be indicative of (or proportional to) a frequency difference between the reference and feedback signals.

Discharge path control circuit14is configured to receive the UP signal via UP lead28and the DOWN signal via DOWN lead30, to generate a discharge path control signal based on the UP and DOWN signals, and to output the discharge path control signal via lead32. Discharge path control circuit14may determine whether both of the UP and DOWN signals are deactivated, and generate the discharge path control signal based on whether both of the UP and DOWN signals are deactivated. For example, discharge path control circuit14may activate the discharge path control signal in response to determining that both of the UP and DOWN signals are deactivated, and deactivate the discharge path control signal in response to determining that at least one of the UP and DOWN signals is activated.

In some examples, discharge path control circuit14may be implemented with a logic gate where the inputs of the logic gate are coupled to the outputs of PFD12, respectively, via leads28,30, and the output of the logic gate is coupled to a discharge path control input of charge pump16via lead32. In cases where the UP and DOWN signals and the discharge path control signal are active high, discharge path control circuit14may be implemented, e.g., with a NOR gate. In cases where the UP and DOWN signals are active low and the discharge path control signal is active high, discharge path control circuit14may be implemented, e.g., with a NAND gate.

Charge pump16may include a current source and a current sink, and may be configured to receive the UP and DOWN signals via leads28,30, and to selectively activate and deactivate the current source and current sink based on the UP and DOWN signals. For example, charge pump16may selectively activate and deactivate the current source in charge pump16based on the UP signal, and selectively activate and deactivate the current sink in charge pump16based on the DOWN signal.

Selectively activating and deactivating the current source in charge pump16based on the UP signal may include activating the current source in response to the UP signal being activated, and deactivating the current source in response to the UP signal being deactivated. Selectively activating and deactivating the current sink in charge pump16based on the DOWN signal may include activating the current sink in response to the DOWN signal being activated, and deactivating the current sink in response to the DOWN signal being deactivated.

Charge pump16may be configured to receive a current amplitude signal from one or more current amplitude control signal sources via leads40. The current amplitude signal may be indicative of a target current amplitude for the current source and current sink in charge pump16. Charge pump16may program one or more switches in the current source and one or more switches in the current sink based on the current amplitude signal. In some examples, the current amplitude signal may include a plurality of signals where each of the signals indicates whether a respective switch in the current source or sink is closed or open.

The current amplitude control signal sources may be internal to or external to an integrated circuit that implements PLL10. The signal sources may include active signal sources or passive signal sources (e.g., switches) that allow the current amplitudes produced by the current source and sink in charge pump16to be programmed.

Charge pump16may output a current via lead34that is determined based on the UP and DOWN signals. The polarity of the current may depend on which of the UP and DOWN signals is activated. In response to the UP signal being activated and the DOWN signal being deactivated, charge pump16may source current at the output of the charge pump16. In response to the DOWN signal being activated and the UP signal being deactivated, charge pump16may sink current at the output of the charge pump16. In response to both of the UP and DOWN signals being activated, charge pump16may source and sink approximately equal amounts of current at the output of charge pump16, thereby outputting approximately no current (i.e., no current or a slight amount of current). In response to both of the UP and DOWN signals being deactivated, charge pump16may output approximately no current.

Charge pump16may be a resistor-based charge pump16. In a resistor-based charge pump, one or both of the current source and current sink may use sets of one or more resistors to generate the output currents.

According to this disclosure, charge pump16may include a high-speed discharge path, and be configured to selectively activate and deactivate the high-speed discharge path based on a discharge path control signal. The high-speed discharge path may, when activated, couple a first node in the current source of charge pump16to a second node in the current sink of charge pump16via a relatively low resistance path, thereby allowing the first and second nodes to discharge in a relatively quick manner and without significantly affecting the output voltage of loop filter18.

Charge pump16may activate the high-speed discharge path in response to the discharge path control signal being activated (e.g., in response to both of the UP and DOWN signals being deactivated and/or in response to both the current source and current sink of charge pump16being deactivated). Charge pump16may deactivate the high-speed discharge path in response to the discharge path control signal being deactivated (e.g., in response to at least one of the UP and DOWN signals being activated and/or in response to at least one of the current source and current sink in charge pump16being activated).

Loop filter18is configured to receive the current generated by charge pump16via lead34, generate a voltage based on the current, and output the voltage via lead36. In some examples, loop filter18may be a low-pass filter, and the voltage at the output of loop filter18may be a low-pass filtered version of the current received from charge pump16. In further examples, loop filter18may be an integrator, and the voltage at the output of loop filter18may be an integrated version of the current received from charge pump16.

In some examples, loop filter18may be an active filter. In such examples, the active filter may regulate the output of charge pump16(e.g., via lead34) at a reference voltage. In examples where charge pump16is a resistor-based charge pump, charge pump16may use the regulated output voltage in conjunction with the resistors included in the resistor-based charge pump to generate a current having a target current amplitude.

VCO20is configured to receive a voltage via lead36, generate an oscillating signal based on the received voltage, and output the oscillating signal via lead38. VCO20may generate the oscillating signal such that the frequency of the oscillating signal varies as a function of the received voltage. In some examples, the frequency of the oscillating signal may be a linear function of the received voltage over a target frequency range.

Frequency divider22is configured to receive the oscillating signal from VCO20, generate a frequency-divided version of the oscillating signal, and output the frequency-divided version of the oscillating signal on feedback lead26. The frequency-divided version of the oscillating signal may be a signal that has a frequency that is equal to the frequency of the oscillating signal divided by an integer or fraction. In some examples, frequency divider22may be omitted, and the oscillating signal from VCO20may be directly provided to the feedback input of PFD12.

During operation, when the frequency and phase between the reference and feedback signals are locked, the UP and DOWN signals may generally remain deactivated. In response to the UP and DOWN signals being deactivated, charge pump16may deactivate both the current source and current sink of charge pump16. Also in response to the UP and DOWN signals being deactivated, discharge path control circuit14may activate the discharge path control signal, thereby causing charge pump16to activate the high-speed discharge path in charge pump16. The high-speed discharge path in charge pump16may rapidly discharge various nodes in the current source and current sink of charge pump16. Charge pump16may output approximately no current (or a small amount of current) to loop filter18. Loop filter18may regulate the output of charge pump16at a reference voltage, and maintain the output voltage of loop filter18at an approximately constant value. VCO20may maintain the frequency of the oscillating signal at an approximately constant value.

If the phase of one of the reference or feedback signals increases relative to the other (or if frequency of either of the reference and feedback signals increases relative to the other), PFD12may detect the phase or frequency difference and activate one of the UP and DOWN signals depending on which signal is leading. If the reference signal leads the feedback signal (or the reference signal has a greater frequency than the feedback signal), then PFD12may activate the UP signal for a duration of time. In response to the UP signal being activated for a duration of time, charge pump16may activate the current source in charge pump16for the duration of time. In response to the UP signal being activated, discharge path control circuit14may deactivate the discharge path control signal, thereby causing charge pump16to deactivate the high-speed discharge path in charge pump16. The current source in charge pump16may source current into loop filter18via lead34. Loop filter18receives the source current carried by lead34, and may charge one or more capacitors in loop filter18for the duration of time. The charging of the capacitor may increase the output voltage of loop filter18. VCO20changes the frequency (e.g., increases or decreases the frequency) of the oscillating signal produced by VCO20in response to receiving the increased voltage from loop filter18. Changing the frequency of the oscillating signal may reduce the amount of phase or frequency difference between the reference and feedback signals.

If the feedback signal leads the reference signal (or the feedback signal has a greater frequency than the reference signal), then PFD12may activate the DOWN signal for a duration of time. In response to the DOWN signal being activated for a duration of time, charge pump16may activate the current sink in charge pump16for the duration of time. In response to the DOWN signal being activated, discharge path control circuit14may deactivate the discharge path control signal, thereby causing charge pump16to deactivate the high-speed discharge path in charge pump16. The current sink may sink current from loop filter18via lead34. Loop filter18receives the sink current carried by lead34, and may discharge one or more capacitors in loop filter18for the duration of time. The discharging of the capacitor may decrease the output voltage of loop filter18. VCO20changes the frequency (e.g., increases or decreases the frequency) of the oscillating signal produced by VCO20in response to receiving the decreased voltage from loop filter18. Changing the frequency may reduce the amount of phase or frequency difference between the reference and feedback signals.

The frequency and/or phase of the output signal may be changed until PLL10returns to a phase-locked condition. Upon returning to the phase-lock condition, discharge path control circuit14may activate, the discharge path control signal, thereby causing charge pump16to activate the high-speed discharge path.

As discussed above, charge pump16may include a low-resistance discharge path between respective nodes of a current source and sink in charge pump16, and charge pump16may selectively activate the low-resistance discharge path when charge pump16is turned off (e.g., when both the current source and current sink in charge pump16are deactivated). The low-resistance discharge path may have a resistance that is lower than the resistance of other current paths between the respective nodes in the charge pump (e.g., current paths formed by the resistors included in the current source and sink of the charge pump), thereby reducing the amount of time needed to reset the charge on the respective nodes when the charge pump is turned off. In this way, the speed of resistor-based charge pump16may be increased, thereby allowing the overall speed of active filter-based PLL10to be increased.

FIG. 2is a schematic diagram showing an example charge pump16according to this disclosure. Charge pump16includes transistors42,44,46,48,50,52,54,56,58,60, resistors62,64,66,68,70,72, nodes74,76,78, a power rail80, a ground rail82, and leads84,86,88,90,92,94,96,98,100,102.

A source electrode of transistor42is coupled to power rail80. A gate electrode of transistor42is coupled to lead88. Lead88may be coupled or connected to the UP output of PFD12via UP lead28. In cases where the UP output of PFD12is active high, an inverter may be coupled between the UP output of PFD12and lead88. A drain electrode of transistor42is coupled to node74.

Respective source electrodes of transistors46,48,50are each coupled to node74. Respective drain electrodes of transistors46,48,50are each coupled to a first terminal of a respective one of resistors62,64,66. Respective gate electrodes of transistors46,48,50are coupled to leads92,94,96, respectively. Respective second terminals of resistors62,64,66are each coupled to output node78.

A source electrode of transistor44is coupled to ground rail82. A gate electrode of transistor44is coupled to lead90. Lead90may be coupled to the DOWN output of PFD12via DOWN lead30. A drain electrode of transistor44is coupled to node76.

Respective source electrodes of transistors52,54,56are each coupled to node76. Respective drain electrodes of transistors52,54,56are each coupled to a first terminal of a respective one of resistors68,70,72. Respective gate electrodes of transistors52,54,56are coupled to leads98,100,102, respectively. Respective second terminals of resistors68,70,72are each coupled to output node78.

A source electrode of transistor58is coupled to a drain electrode of transistor60. The source electrode of transistor58and the drain electrode of transistor60are coupled to node74. A drain electrode of transistor58is coupled to a source electrode of transistor60. The drain electrode of transistor58and the source electrode of transistor60are coupled to node76. A gate electrode of transistor58is coupled to lead84. A gate electrode of transistor60is coupled to lead86.

Leads84,86may both be coupled to an output of discharge path control circuit14via lead32. In cases where the discharge path control signal is active high, an inverter may be coupled between the output of discharge path control circuit14and lead84.

In the example charge pump16ofFIG. 2, transistors42,46,48,50,58are p-type metal-oxide-semiconductor (PMOS) transistors, and transistors44,52,54,56,60are n-type MOS (NMOS) transistors. In other examples, any combination of the same or different types of transistors may be used with the same or different conductivity types. Transistors42,44,46,48,50,52,54,56,58,60may be examples of switches and/or controlled current sources (e.g., voltage-controlled current sources) where the gate electrodes correspond to the control electrodes, and the source and drain electrodes correspond to current conduction electrodes. In other examples, one or more of transistors42,44,46,48,50,52,54,56,58,60may be replaced with combinations of the same or different types of switches and/or controlled current sources (e.g., voltage or current-controlled current sources).

Transistors42,46,48,50and resistors62,64,66may collectively form a source current path between power rail80and output node78. The source current path and power rail80may form a current source. The source current path may be a selectively-enabled, programmable amplitude source current path. Similarly, the current source may be a selectively-enabled, programmable amplitude current source.

A first portion of the source current path may be formed by transistor42, and may be coupled between power rail80and node74. A second portion of the source current path may be formed by one or more of transistors46,48,50and resistors62,64,66, and may be coupled between node74and output node78. The second portion of the source current path may include a plurality of source current path branches, where each of the source current path branches includes a respective one of transistors46,48,50coupled in series with a respective one of resistors62,64,66.

Leads92,94,96may be coupled to a current amplitude signal, and the second portion of the source current path may be programmable based on the current amplitude signal. To program the source current path, charge pump16may selectively activate and deactivate various combinations of source current path branches based on the current amplitude signal. Transistors46,48,50may act as switches, and leads92,94,96may act as respective control signals for the switches. The current amplitude signal may include a bit (or voltage) for each of the switches that indicate whether the respective switch is to be open or closed. Charge pump16may activate a particular combination of current source path branches by turning on a combination of transistors46,48,50(i.e., closing a set of switches) that correspond to the combination of current source path branches. Charge pump16may deactivate a current source path by turning off one of transistors46,48,50that corresponds to the current source path branch. Resistors62,64,66may have the same or different resistance values.

By activating and deactivating different combinations of source current path branches, the effective resistance through the source current path may be varied. When output node78is regulated at a substantially constant reference voltage (e.g., by loop filter18(FIG. 1)), varying the resistance of the source current path may vary the magnitude of current produced by the current source. In this way, the current source may be said to have a programmable amplitude or magnitude.

Transistor42may form an activation switch (or enable switch) for the current source. Charge pump16may selectively activate the current source based on the UP signal by selectively turning on and off transistor42(i.e., closing and opening the switch). When transistor42is turned on, current may flow through the source current path between power rail80and output node78. When transistor42is turned off, substantially no current may flow between power rail80and output node78. Transistor42may allow the current source to be a selectively-enabled current source.

Transistors44,52,54,56and resistors68,70,72may collectively form a sink current path between ground rail82and output node78. The sink current path and ground rail82may form a current sink. The sink current path may be a selectively-enabled, programmable amplitude sink current path. Similarly, the current sink may be a selectively-enabled, programmable amplitude current sink.

A first portion of the sink current path may be formed by transistor44, and may be coupled between ground rail82and node76. A second portion of the sink current path may be formed by one or more of transistors52,54,56and resistors68,70,72, and may be coupled between node76and output node78. The second portion of the sink current path may include a plurality of sink current path branches, where each of the sink current path branches includes a respective one of transistors52,54,56coupled in series with a respective one of resistors68,70,72.

Leads98,100,102may be coupled to a current amplitude signal, and the second portion of the sink current path may be programmable based on the current amplitude signal. To program the sink current path, charge pump16may selectively activate and deactivate various combinations of sink current path branches based on the current amplitude signal in a similar fashion to the current source. By activating and deactivating different combinations of sink current path branches, the effective resistance through the sink current path may be varied. When output node78is regulated at a substantially constant reference voltage (e.g., by loop filter18(FIG. 1)), varying the resistance of the sink current path may vary the magnitude of current produced by the current sink. In this way, the current sink may be said to have a programmable amplitude or magnitude. In some examples, charge pump16may program the current source and current sink to source or sink the same amplitude of current.

Transistor44may form an activation switch (or enable switch) for the current sink. Charge pump16may selectively activate the current sink based on the DOWN signal by selectively turning on and off transistor44(i.e., closing and opening the switch). In this way, the current sink may be said to be a selectively-enabled current sink.

Transistors58,60may form a transmission gate, or more generally, a switch that selectively couples node74to node76based on a discharge path control signal received via leads84,86. In response to the discharge path control signal being activated, the transmission gate formed by transistors58,60may close, thereby coupling node74to node76. In response to the discharge path control signal being deactivated, the transmission gate formed by transistors58,60may open, thereby decoupling node74from node76.

Although the example charge pump16inFIG. 2is shown as having three source current path branches and three sink current path branches, greater or fewer numbers of current path branches may be used for both the current source and current sink. In some examples, a single current path branch may be used for both the current source and current sink. In additional examples, the number of source current path branches in the current source may be different than the number of sink current path branches in the current sink.

During operation, output node78may be regulated at a substantially constant reference voltage (e.g., by loop filter18inFIG. 1). In some examples, the reference voltage may be approximately equal to the average of the voltages supplied by power rail80and the ground voltage supplied by ground rail82.

During operation, charge pump16may initially be deactivated (or turned off). Charge pump16may be said to be deactivated when both the current source (formed by transistors42,46,48,50, resistors62,64,66and power rail80) is deactivated and the current sink (formed by transistors44,52,54,56, resistors62,64,66and ground rail82) are deactivated. When charge pump16is deactivated, the discharge path control signal may be activated (by discharge path control circuit14(FIG. 1)), thereby closing the transmission gate formed by transistors58,60and forming a discharge path (or current path) between node74and node76. The voltages at nodes74,76,78may all be substantially equal to each other and to the reference voltage at which output node78is regulated.

Once PFD12(FIG. 1) detects a rising edge in either the reference signal or the feedback signal, PFD12may activate one of the UP signal or the DOWN signal. If PFD12first detects a rising edge in the reference signal, PFD12may activate the UP signal. Once the UP signal is activated, charge pump16may activate the current source, which may include turning on transistor42to activate the source current path between power rail80and output node78. Also if the UP signal is activated, discharge path control circuit14(FIG. 1) may deactivate the discharge path control signal, thereby causing charge pump16to open the transmission gate formed by transistors58,60and to disconnect (or decouple) node74from node76.

Power rail80may charge node74(e.g., a parasitic capacitance between node74and ground) to a voltage approximately equal (or slightly less) than the voltage at power rail80. Output node78continues to be regulated at the reference voltage. The voltage difference between node74and output node78causes a current to flow through the activated source current path branches and to loop filter18via output node78. Charge pump16may continue to supply current to the loop filter18until PFD12detects a rising edge in the feedback signal.

In response to detecting a rising edge in the feedback signal, PFD12may activate the DOWN signal for a brief period of time to make sure that charge pump16is dead-zone free, and then deactivate both the UP and DOWN signals. Once the DOWN signal is activated, charge pump16may activate the current sink, which may include turning on transistor44to activate the sink current path between node76and output node78. Ground rail82may discharge node76(e.g., a parasitic capacitance between node76and ground) to a voltage approximately equal (or slightly greater) than the voltage at ground rail82. Output node78continues to be regulated at the reference voltage. The voltage difference between node76and output node78may cause a current to be drawn from loop filter18via output node78and flow through the activated sink current path. Charge pump16may continue to sink current until PFD12deactivates the UP and DOWN signals.

In response to PFD12deactivating the UP and DOWN signals, discharge path control circuit14may activate the discharge path control signal, thereby causing charge pump16to close the transmission gate formed by transistors58,60and to connect (or couple) node74to node76. The closed transmission gate may form a low-resistance current path between nodes74,76, and nodes74,76may transfer charge between each other via the low-resistance current path such that the resulting voltage at each of nodes74,76is approximately equal to the reference voltage.

The low-resistance discharge path formed by transistors58,60may have a resistance that is lower than the resistance of the current path formed by resistors62,64,66,68,70,72in the current source and current sink of charge pump16. The relatively low resistance may allow nodes74,76to return to the regulated voltage in a shorter amount of time than would otherwise occur without the low-resistance discharge path. In this way, the speed of resistor-based charge pump16may be increased, thereby allowing the overall speed of an active filter-based PLL10to be increased.

FIG. 3is a schematic diagram showing an example charge pump110without a high-speed discharge path according to this disclosure. Charge pump110includes parasitic capacitances112,114where parasitic capacitance112models an effective parasitic capacitance between node74and ground, and parasitic capacitance114models an effective parasitic capacitance between node76and ground. The effective parasitic capacitances may include junction capacitances associated with transistors42,44,46,48,50,52,54,56. For example, parasitic capacitance112may model the junction capacitances associated with transistors42,46,48,50and node74(e.g., the gate-drain junction capacitance and the drain-bulk junction capacitance for transistor42, and the gate-source junction capacitance and the source-bulk junction capacitance for each of transistors46,48,50.

When both the current source and current sink of charge pump16are activated, parasitic capacitance112may be charged to a voltage approximately equal to the voltage at power rail80, and parasitic capacitance114may be discharged to a voltage approximately equal to the voltage at ground rail82. When the current source and sink are deactivated, loop filter18may continue to regulate output node78at a reference voltage. Regulating output node78at the reference voltage may cause parasitic capacitance112to discharge to the reference voltage, and parasitic capacitance114to charge to the reference voltage. This may generate an effective discharge path116between parasitic capacitance112and parasitic capacitance114that passes through the activated branches of the source current path and the sink current path.

The amount of time needed to discharge and charge, respectively, parasitic capacitances112,114to the reference voltage may depend on the amount of parasitic capacitance present and on the resistance values of resistors62,64,66,68,70,72for the activated current paths. The relatively high parasitic capacitance values and/or resistance values may delay the resetting of the voltages at nodes74,76, thereby slowing down the operation of charge pump16and consequently PLL10.

FIG. 4is a schematic diagram showing an example discharge path118for the example charge pump16ofFIG. 2according to this disclosure. Unlike charge pump110ofFIG. 3, charge pump16includes a discharge path that is selectively activated when both the current source and current sink are deactivated. The discharge path may have an effective resistance that is less than an effective resistance of a current path formed between node74and node76that passes through one or more of resistors62,64,66, one or more of resistors68,70,72, and output node78. The relatively low resistance of discharge path118may allow the first and second nodes to return to the regulated voltage in a shorter amount of time than would otherwise occur without the low-resistance discharge path. In this way, the speed of resistor-based charge pump16may be increased, thereby allowing the overall speed of an active filter-based PLL10to be increased.

FIG. 5is a schematic diagram showing an example active loop filter18according to this disclosure. Loop filter18includes an operational amplifier120, a capacitor122, and leads34,36,124. A non-inverting input of operational amplifier120is coupled to a reference voltage via lead124. Capacitor122is coupled between an output of operational amplifier120and an inverting input of operational amplifier120. The inverting input of operational amplifier120is coupled to an output of charge pump16via lead34. The output of operational amplifier120is coupled to an input of VCO20via lead36.

During operation, loop filter18may regulate the voltage at lead34(at the output of charge pump16) at a substantially constant voltage that is approximately equal to the reference voltage (VREF) carried by lead124. Also during operation, capacitor122may charge and discharge based on a current supplied by charge pump16to loop filter18via lead34. The charging and discharging of capacitor122may increase and decrease the output voltage on lead36. The loop filter18inFIG. 5is an example of an integrator.

FIG. 6is a schematic diagram showing another example active filter18according to this disclosure. In addition to the components included in the active filter18ofFIG. 5, the active filter18shown inFIG. 6includes an additional feedback path. The additional feedback path includes a resistor126and a capacitor128. A first terminal of resistor126is coupled to an inverting terminal of operational amplifier120. A second terminal of resistor126is coupled to a first terminal of capacitor128. A second terminal of capacitor128is coupled to the output of operational amplifier120. The loop filter18inFIG. 6is an example of a low-pass filter.

The example active loop filters18shown inFIGS. 5 and 6are merely examples of active filters that may be used in a PLL10according to this disclosure. Other types of active filters, low-pass filters, and integrators may also be used.

FIG. 7is a flow diagram illustrating an example technique for increasing the speed of a resistor-based charge pump according to this disclosure. PLL10monitors charge pump control signals (200). For example, the charge pump control signals may include the UP and DOWN signals, and discharge path control circuit14may monitor the UP and DOWN signals.

PLL10determines whether the charge pump is deactivated (202). For example, discharge path control circuit14may generate a control signal (e.g., by using one or more combination logic gates) indicative of whether both the current source and current sink in charge pump16are deactivated.

PLL10closes a discharge path switch (e.g., the transmission gate formed by transistors58,60) in response to both of the outputs of PFD12indicating that charge pump16is to be deactivated (204). The outputs of PFD12may indicate that charge pump16is to be deactivated when the outputs of PFD12indicate that both the current source and the current sink in charge pump16are to be deactivated.

PLL10opens the switch (e.g., the transmission gate formed by transistors58,60) in response the outputs of PFD12indicating that charge pump16is to be activated (206). The outputs of PFD12may indicate that charge pump16is to be activated when the outputs of PFD12indicate that at least one of the current source and the current sink in charge pump16is to be activated.

The technique shown inFIG. 6allows PLL10to selectively close a switch that connects a first node in a current source of charge pump16to a second node in a current sink of charge pump16based on whether both outputs of PFD12indicate that a charge pump is to be deactivated. In this way, a high-speed, low-resistance discharge path may be selectively activated to increase the speed of the charge transfer when charge pump16is deactivated, while avoiding interference with the operation of charge pump16when charge pump16is activated.

Example embodiments will now be described. In some examples, an integrated circuit includes a phase-frequency detector (PFD) (12) having a first output (U) and a second output (D). The integrated circuit further includes a current source (42,46,48,50,62,64,66,80) having a control terminal (88) coupled to the first output (U) of the PFD, and an output terminal (78). The integrated circuit includes a current sink (44,52,54,56,68,70,72,82) having a control terminal (90) coupled to the second output (D) of the PFD, and an output terminal (78) coupled to the output terminal (78) of the current source. The integrated circuit further includes a switch (58,60) having a first conduction electrode (source of transistor58and drain of transistor60) coupled to a node (74) in the current source, a second conduction electrode (drain of transistor58and source of transistor60) coupled to a node (76) in the current sink, and a control electrode (gates of transistors58,60). The integrated circuit further includes a control circuit (14) having a first input coupled to the first output (U) of the PFD, a second input coupled to the second output (D) of the PFD, and an output (32) coupled to the control electrode of the switch.

In some examples, the control circuit (32) is configured to generate a control signal at the output (32) of the control circuit based on a first PFD signal (U) received at the first input of the control circuit and a second PFD signal (D) received at the second input of the control circuit. In such examples, the control circuit (32) may be configured to generate a control signal that causes the switch (58,60) to close when both the current source and the current sink are deactivated, and that causes the switch to open when at least one of the current source and the current sink is activated.

In further examples, the PFD (12) is configured to generate an UP signal at the first output of the PFD, and a DOWN signal at the second output of the PFD, and the control circuit (14) is configured to generate a control signal based on the UP signal and the DOWN signal. In such examples, the control circuit (14) may be configured to generate a control signal that causes the switch (58,60) to close in response to the UP and DOWN signals indicating that both the current source and the current sink are to be deactivated. The control signal may further cause the switch (58,60) to open in response to at least one of the UP signal indicating the current source is to be activated and the DOWN signal indicating that the current sink is to be activated.

In some examples, the current source includes a source current path (42,46,48,50,62,64,66) coupled to the output terminal. The source current path includes a plurality of source current path branches (46,62;48,64;50,66) coupled in parallel between a first node (74) of the source current path and the output terminal (78). Each of the source current path branches includes a respective one of a first plurality of resistors (62,64,66) coupled in series with a respective one of a first plurality of current source configuration switches (46,48,50).

In such examples, the current sink includes a sink current path (44,52,54,56,68,70,72) coupled to the output terminal (78). The sink current path includes a plurality of sink current path branches (52,68;54,70;56,72) coupled in parallel between a second node (76) of the sink current path and the output terminal (78). Each of the sink current path branches includes a respective one of a second plurality of resistors (68,70,72) coupled in series with a respective one of a second plurality of current sink configuration switches (52,54,56).

In additional examples, the integrated circuit includes an active low-pass filter (18) having an input coupled to the output terminals (78) of the current source and the current sink. In such examples, the active low-pass filter (18) may be configured to regulate the voltage at the output terminals of the current source and the current sink at a reference voltage (VREF).

In some examples, an integrated circuit includes a charge pump (16) that includes an output terminal (78). The charge pump further includes a current source (42,46,48,50,62,64,66,80) including one or more resistors (62,64,66) coupled between a first node (74) and the output terminal (78). The charge pump further includes a current sink (44,52,54,56,68,70,72,82) including one or more resistors (68,70,72) coupled between a second node (76) and the output terminal (78). The charge pump further includes a switch (58,60) including a first terminal (source of transistor58and drain of transistor60) coupled to the first node (74) of the current source and a second terminal (drain of transistor58and source of transistor60) coupled to the second node (76) of the current sink.

In some examples, the on-resistance of the switch is less than a lowest resistance of the resistors in the current source and the resistors in the current sink. In further examples, the effective resistance of a current path formed by the switch between the first and second nodes is less than an effective resistance of a current path between the first and second nodes that passes through one or more of the source resistors (62,64,66), one or more of the sink resistors (52,54,56), and a node (78) coupled to the output terminal.

In some examples, the switch (58,60) is a transmission gate. In further examples, the switch, when closed, forms a current path that is free of connection to the output terminal (78) of the charge pump.

In additional examples, the switch includes a control electrode (gates of transistors58,60), and the integrated circuit further includes a phase-frequency detector (PFD) (12) having a first output (U) and a second output (D). The integrated circuit further includes a control circuit (14) having a first input coupled to the first output (U) of the PFD, a second input coupled to the second output (D) of the PFD, and an output (32) coupled to the control electrode of the switch.

In further examples, current source includes a first power rail (80), and a first control switch (42) coupled between the first power rail (80) and the first node (74). In such examples, the current sink includes a second power rail (ground rail82), and a second control switch (44) coupled between the second power rail (82) and the second node (78). A control electrode (88) of the first control switch (42) is coupled to the first output (U) of the PFD (e.g., with an intervening inverter), and a control electrode (90) of the second control switch (44) is coupled to the second output (D) of the PFD.

In some examples, the current source includes a plurality of source current path branches (46,62;48,64;50,66) coupled in parallel between the first node (74) of the current source and the output terminal (78). Each of the source current path branches includes a respective one of the resistors (62,64,66) in the current source coupled in series with a respective one of a first plurality of current source configuration switches (46,48,50).

In such examples, the current sink includes a plurality of sink current path branches (52,68;54,70;56,72) coupled in parallel between the second node (76) of the current sink and the output terminal (78). Each of the sink current path branches includes a respective one of the resistors (68,70,72) in the current sink coupled in series with a respective one of a second plurality of current sink configuration switches (52,54,56).

In some examples, the current source is an adjustable-amplitude current source with a hardware-programmable current amplitude. In such examples, the current sink may be an adjustable-amplitude current sink with a hardware-programmable current amplitude. In further examples, integrated circuit includes an active low-pass filter (18) having a first input coupled to the output terminal (78) of the charge pump, and a second input coupled to a reference voltage lead (124).

This disclosure describes a high-speed resistor-based charge pump for active loop filter-based PLLs with improved leakage performance. The architecture of a resistor-based charge pump without a high-speed, low-resistance discharge path is shown inFIG. 3. This architecture may have a slow discharge path for charge built up on parasitic capacitances when the charge pump is turned OFF. This slow discharge path for leakage current may limit the maximum speed of operation of the charge pump.

One technique for speeding up the charging and discharging of the parasitic capacitors is to couple reduced swing inverters between the activation inputs of the current source and sink and nodes with parasitic capacitances. The reduced swing inverters may be used to discharge or charge the parasitic junction caps to a replica reference voltage. However, for low voltage processes, it may be difficult to obtain acceptable drive on the reduced swing inverters.

According, to this disclosure, a control circuit (14) may generate one or two additional signals from a PFD, and an additional high speed discharge path may be placed in the charge pump. This discharge path may be enabled when the charge pump is turned OFF, thereby discharging the charge built up on parasitic capacitances quickly. The discharge path may be disabled when the charge pump is turned on so as not to interfere with the operation of the charge pump. Selectively activing the discharge path may increase the maximum speed of operation of the charge pump.

Resistor-based charge pumps may have better current matching characteristics than some types of non-resistor based charge pumps. A resistor-based charge pump with programmable resistances (e.g., programmable current path branches) may allow the corner frequency of the control loop and/or the lock acquisition speed to be programmed for a target application. Moreover, a resistor-based charge pump with programmable resistances may allow a PLL to adjust the bandwidth of the PLL and to select a trade-off between the amount of VCO noise allowed by the PLL and the amount of input clock noise allowed by the PLL.

The techniques and circuitry described in this disclosure may, in some examples, be implemented on any combination of one or more integrated circuits or other devices. Although illustrative examples have been shown and described by way of example, a wide range of alternative examples are possible within the scope of the foregoing disclosure.