Apparatus and a method for detecting the coincidence of two signal levels

An apparatus for detecting the coincidence of two input signals comprises a first unit for deciding elevation between two input signals, a second unit for connecting a low level signal selected from the input signals to one output path for the low level signal and connecting a high level signal selected from the input signals to another output path for the high level signal as determined by the decision output, a third unit for producing a tolerance level for deciding one input signal level is coincident with another input signal level, a fourth unit for adding the low level signal form the output path to the tolerance level, and a fifth unit for comparing the adding output with the high level signal from the output path, and deciding one input signal level is coincident with another input signal level if a level of the addition output is higher than a level of the high level signal.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to an apparatus and a method for deciding 
whether one signal level is coincident with another signal level or not. 
Detecting or deciding elevation or coincidence of two signal levels is 
required in various fields. For example, the diversity reception system in 
a mobile communication system uses plural reception systems having little 
correlation with each other and has to select one of the reception systems 
that has a higher signal level than the other reception system. In such a 
case, it is necessary to detect elevation of the signal levels to change 
the reception systems and also coincidence thereof to start processes 
corresponding to detection of the coincidence. 
2. Description of the Related Art 
It is possible to detect the coincidence of two signal levels by using 
electrical devices, e.g., an analog to digital (A/D) converter, a digital 
comparator, etc. Namely, the A/D converter converts an analog input signal 
to a digital value of n bits. The digital comparator compares the digital 
values from two A/D converters and decides whether one digital value is 
coincident with another digital value or not. 
However, the conventional system as described above has to use two A/D 
converters for two analog inputs, thereby a circuit scale of the system 
becomes large. Recently, the most significant priority for design of an 
apparatus is the miniaturization of the apparatus, therefore parts and 
circuit scale of the apparatus must be small in size. However, the system 
as described above cannot satisfy the requirement of the miniaturization. 
Further, the A/D converter has an adjusting circuit for adjusting its 
full-scale and a zero-point so that the circuit of the system is larger by 
adding the adjusting circuit. Furthermore, there is a problem that it is 
not easy to match the tolerance between the A/D converters so as not to 
decrease their detection accuracy by addition of the adjusting circuit. 
SUMMARY OF THE INVENTION 
The purpose of the present invention is to provide a detector for deciding 
the coincidence of two signal levels, which has a small scale circuit and 
no adjustment for the circuit, in order to solve the problems described 
above. 
According to the present invention an apparatus for detecting the 
coincidence of two input signals comprises a first means for deciding the 
elevation between two input signals, a second means for connecting a low 
level signal selected from the input signals to one output path for the 
low level signal and connecting a high level signal selected from the 
input signals to another output path for the high level signal by a 
decision output from the first means, a third means for producing a 
tolerance level for deciding one input signal level is coincident with 
another input signal level, a fourth means for adding the low level signal 
from the output path of the second means to the tolerance level from the 
third means, and a fifth means for comparing the added output from the 
fourth means with the high level signal from the output path of the second 
means and deciding one input signal is coincident with another input 
signal if the level of the added output is higher than the level of the 
high level signal. 
Further, according to the present invention a method for detecting the 
coincidence of two input signals comprises the steps of deciding the 
elevation difference between two input signals, adding a low level signal 
selected from the input signals by the decision to a tolerance level 
signal for deciding one input signal level is coincident with another 
input signal level, comparing the result of the addition with a high level 
signal selected from the input signals by the decision, and deciding one 
input signal level is coincident with another input signal level if the 
level of the result of addition is higher than the level of the high level 
signal by the comparison.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Before describing the preferred embodiments according to the present 
invention, an example of the related art is provided with reference to 
accompanying the drawings (FIG. 1). 
FIG. 1 shows an example of a conventional detector for deciding one input 
signal level is coincident with another input signal level. 
In FIG. 1, two A/D converters 10, 12 convert analog input signals V.sub.A, 
V.sub.B to digital values of n bits and then provide each digital value to 
a digital comparator 18. The digital comparator 18 decides whether one 
digital value is coincident with the other digital value or not. The 
conventional detector provides simplicity and high resolution, and also 
permits variable tolerance in the decision of the coincidence of two input 
signal levels by providing a simple way of comparing the digital values 
while excluding some of the lower bits of the digital values. 
However, in the detector described above there are some problems in that 
the detector has to use two A/D converters 10, 12 so that the circuit 
scale of the detector becomes large, and each A/D converter 10, 12 has to 
use an adjusting circuit 14, 16 respectively to adjust its full-scale and 
a zero-point so that the circuit becomes even larger by adding the 
adjusting circuit 14, 16. Further, it is not easy to match the tolerance 
between the A/D converters 10, 12 by the adjusting circuit 14, 16 so as 
not to decrease in their detection accuracy. 
FIG. 2 shows a block diagram of a detector for detecting the coincidence of 
two input signal levels according to the present invention. 
In FIG. 2, a level comparator 21 compares one analog input signal V.sub.A 
with another analog input signal V.sub.B, and decides the elevation of the 
two signal levels. A path switching circuit 22 has an interchangeable path 
switched by an output signal S.sub.2 from the level comparator 21, through 
which each signal V.sub.A, V.sub.B is connected to either of an output 
path P.sub.L Or P.sub.H. The output path P.sub.L terminates the lower 
level signal selected from the input signals V.sub.A, V.sub.B and the 
output path P.sub.H terminates the other higher level signal by the output 
signal S.sub.2. A tolerance generator 23 produces a reference voltage 
V.sub.REF that corresponds to a tolerance level for deciding one input 
signal (V.sub.A or V.sub.B) level is coincident with another input signal 
(V.sub.B or V.sub.A) level. 
A addition circuit 24 adds the reference voltage V.sub.REF to the lower 
level signal from the output path P.sub.L. A coincidence decision circuit 
25 compares the level of the addition output from the addition circuit 24 
with the level of the high level signal from the output path P.sub.H, and 
if the output level from the addition circuit 24 is higher than the level 
of the high level signal from the output pass P.sub.H, that is V.sub.B 
&gt;V.sub.A, V.sub.A +V.sub.REF &gt;V.sub.B Or V.sub.A &gt;V.sub.B, V.sub.B 
+V.sub.REF &gt;V.sub.A, the coincidence decision circuit 25 decides one input 
signal level is coincident with the other input signal level (V.sub.A 
=V.sub.B). 
FIG. 3 is an explanatory view showing performance characteristics of the 
detector in FIG. 2. 
In FIG. 3, it is assumed that one input signal V.sub.A is a constant and 
another input signal V.sub.B varies as shown by a broken solid line, and 
until a time t.sub.I the signal level V.sub.A is higher than the signal 
level V.sub.B (V.sub.A &gt;V.sub.B) and after the time t.sub.1 the signal 
level V.sub.A is lower than the signal level V.sub.B (V.sub.A &lt;V.sub.B). 
Until the time t.sub.1, the level comparator 21 decides V.sub.A &gt;V.sub.B 
and outputs a high level signal S.sub.2 (H), and conversely, after the 
time t.sub.1 the level comparator 21 decides V.sub.A &lt;V.sub.B and outputs 
a low level signal S.sub.2 (L). The path switching circuit 22 is provided 
with the signal S.sub.2. If the signal S.sub.2 is high (V.sub.A &gt;V.sub.B), 
the path switching circuit 22 connects the low level signal V.sub.B to the 
output path P.sub.L and connects the high level signal V.sub.A to the 
output path P.sub.H. 
Then the addition circuit 24 adds the reference voltage V.sub.REF as a 
tolerance for the coincident decision to the signal V.sub.B from the 
output path P.sub.L. The coincidence decision circuit 25 compares the 
level of an addition output signal (V.sub.B +V.sub.REF) from the addition 
circuit 24 with the level of the high level signal V.sub.A from the output 
path P.sub.H, and decides whether the addition signal level is higher than 
the high level signal (V.sub.B +V.sub.REF &gt;V.sub.A) or not. If V.sub.A 
&gt;V.sub.B and V.sub.B +V.sub.REF &gt;V.sub.B, the coincidence decision circuit 
25 decides the signal V.sub.A is coincident with the signal V.sub.B. 
Similarly, if V.sub.A &lt;V.sub.B and V.sub.A +V.sub.REF &gt;V.sub.B, the 
coincidence decision circuit 25 decides the signal V.sub.A is coincident 
with the signal V.sub.B. 
Therefore, until a time t.sub.0 a decision of the coincidence decision 
circuit 25 is NO (V.sub.A is not coincident with V.sub.B) because V.sub.A 
&gt;V.sub.B and V.sub.B +V.sub.REF &lt;V.sub.A, and the coincidence decision 
circuit 25 outputs a low level signal S.sub.1 (L). After the time to the 
decision is YES (V.sub.A is coincident with V.sub.B) because V.sub.A 
&lt;V.sub.B and V.sub.A +V.sub.REF &gt;V.sub.B, and the coincidence decision 
circuit 25 outputs a high level signal S.sub.1 (H). 
At the time t.sub.1, the signal V.sub.B crosses the signal V.sub.A, and the 
signal S.sub.2 from the level comparator 21 becomes low (V.sub.A 
&lt;V.sub.B). Thereby, the path switching circuit 22 connects the low level 
signal V.sub.A to the output path P.sub.L and connects the high level 
signal V.sub.B to the output path P.sub.H respectively. The addition 
circuit 24 outputs a signal V.sub.A +V.sub.REF. The coincidence decision 
circuit 25 compares the signal V.sub.A +V.sub.REF with the signal V.sub.B 
and decides whether V.sub.A +V.sub.REF &gt;V.sub.B or not. From the time 
t.sub.1 to time t.sub.2 the decision is YES because V.sub.B &gt;V.sub.A and 
V.sub.A +V.sub.REF &gt;V.sub.B, and the coincidence decision circuit 25 
outputs a high level signal S.sub.1 (H). After the time t.sub.2 the 
decision is NO since V.sub.B &gt;V.sub.A and V.sub.A +V.sub.REF &lt;V.sub.B, and 
the coincidence decision circuit 25 outputs a low level signal S.sub.l 
(L). 
Thus, the coincidence decision circuit 25 decides the signal V.sub.A is 
coincident with the signal V.sub.B during the time from t.sub.0 to 
t.sub.2. The basis of the decision of the coincidence of the two signal 
levels is that the signal level from the output path P.sub.H is smaller 
than the signal level from the addition circuit 26, and the reference 
voltage V.sub.REF provides a tolerance of coincidence. This is generally 
written as follows V(P.sub.H)&gt;V(P.sub.L), and V(P.sub.L)+V.sub.REF 
&gt;V(P.sub.H). It is possible to arrange the circuit of FIG. 1 by using a 
general use operational amplifier and comparator and to provide a small 
circuit with no adjustment. 
FIG. 4 shows a preferred embodiment of a circuit according to the present 
invention. In FIG. 4, the level comparator 21 consists of an analog 
comparator using an operational amplifier A.sub.1 and resistors R.sub.1 
and R.sub.2, and outputs a high level signal S.sub.2 (H) when an input 
signal level V.sub.A is higher than an input signal level V.sub.B (V.sub.A 
&gt;V.sub.B) or outputs a low level signal S.sub.2 (L) when V.sub.A &lt;V.sub.B. 
The path switching circuit 22 consists of plural analog switches SW.sub.1 
-SW.sub.4. When the signal S.sub.2 is high the switches SW.sub.1, SW.sub.3 
turn on and the switches SW.sub.2, SW.sub.4 turn off. In that case 
(V.sub.A &gt;V.sub.B), the output path P.sub.L is provided with the low level 
signal V.sub.B and the output path P.sub.H is provided with the high level 
signal V.sub.A. Conversely, when the signal S.sub.2 is low (V.sub.A 
&lt;V.sub.B), the switches SW.sub.2, SW.sub. 4 turn on and the switches 
SW.sub.1, SW.sub.3 turn off, and thereby the output path P.sub.L is 
provided with the low level signal V.sub.A and the output path P.sub.H is 
provided with the high level signal V.sub.B. The analog switch consists of 
a CMOS transistor that is constructed by a parallel combination of a PMOS 
transistor and an NMOS transistor. 
The tolerance generator 23 consists of a voltage divider comprised of 
resistors R.sub.3 and R.sub.4 and an operational amplifier A.sub.2 as a 
voltage-follower circuit. The voltage divider produces the reference 
voltage V.sub.REF by dividing a power supply voltage V.sub.a and the 
amplifier A.sub.2 outputs the reference voltage V.sub.REF only through 
impedance conversion. Similarly, each the operational amplifiers A.sub.3 
and A.sub.4 has an arrangement of a voltage-follower circuit with 100% 
negative-feedback of its output, and outputs the signal V.sub.A or V.sub.B 
from output path P.sub.H and output path P.sub.L respectively. The 
addition circuit 24 consists of resistors R.sub.5 -R.sub.8 and an 
operational amplifier A.sub.5, and adds the reference voltage V.sub.REF to 
the output voltage V.sub.A or V.sub.B from the output path P.sub.L. 
The coincidence decision circuit 25 consists of an analog comparator using 
resistors R.sub.9, R.sub.10 and an operational amplifier A.sub.6. If the 
output signal level from the addition circuit 24 (V.sub.A, or V.sub.B 
+V.sub.REF) is higher than the output signal level from the output path 
P.sub.H (V.sub.B or V.sub.A), the coincidence decision circuit 25 outputs 
a high level signal S.sub.1 (H), or if the output signal level from the 
addition circuit 24 is lower than the output signal level from the output 
pass P.sub.H, the coincidence decision circuit 25 outputs a low level 
signal S.sub.1 (L). 
FIG. 5(A) and FIG. 5(B) are explanatory views that schematically show the 
operation of the coincidence decision circuit 25 as described above. FIG. 
5(A) shows the case of V.sub.A &gt;V.sub.B, therefore the coincidence 
decision circuit 25 outputs a low level signal (L) in a state 1 (V.sub.B 
+V.sub.REF &lt;V.sub.A) or conversely outputs a high level signal (H) in a 
state 2 (V.sub.B +V.sub.REF &gt;V.sub.A). FIG. 5(B) shows the case of V.sub.B 
&gt;V.sub.A, and the coincidence decision circuit 25 outputs the low level 
signal (L) in a state 1 (V.sub.A +V.sub.REF &lt;V.sub.B) and outputs the high 
level signal (H) in a state 2 (V.sub.A +V.sub.REF &gt;V.sub.B). 
FIG. 6 shows an example of timing diagrams of output signals in FIG. 4. In 
a section 1 the time base, V.sub.A &gt;V.sub.B and the output signal S.sub.2 
from the level comparator 21 becomes high (H), in response to the signal 
S.sub.2 the path switching circuit 22 connects the input signal V.sub.A to 
the output path P.sub.H and the input signal V.sub.B into the output path 
P.sub.L respectively. The addition circuit 24 adds the signal V.sub.B to 
the signal V.sub.REF and outputs a signal V.sub.B +V.sub.REF. Since 
V.sub.B +V.sub.REF &lt;V.sub.A in the section 1, the output signal S.sub.1 
from the coincidence decision circuit 25 is low (L), and although V.sub.A 
&gt;V.sub.B in section 2, by increasing the signal V.sub.B a level of the 
signal V.sub.B +V.sub.REF becomes higher than a level of the signal 
V.sub.A (V.sub.B +V.sub.REF &gt;V.sub.A) and then the output signal S.sub.1 
is high (H). When the signal V.sub.B crosses the signal V.sub.A (V.sub.A 
&lt;V.sub.B), the level comparator 21 exchanges the connection from the input 
signals V.sub.A, V.sub.B to the output paths P.sub.L, P.sub.H, and 
thereby, the input signal V.sub.A is connected to the output paths P.sub.L 
and the input signal V.sub.B is connected to the output paths P.sub.H. The 
addition circuit 24 outputs a signal V.sub.A +V.sub.REF. The coincidence 
decision circuit 25 compares the signal V.sub.A +V.sub.REF with the signal 
V.sub.B. Therefore, the signal V.sub.A becomes lower than the signal 
V.sub.B in a section 3 (V.sub.A &lt;V.sub.B), and the output signal S.sub.1 
remains high (H) (V.sub.A +V.sub.REF &gt;V.sub.B). Then the coincidence 
decision circuit 25 outputs a low level signal (L) in a section 4 because 
V.sub.A &lt;V.sub.B and V.sub.A +V.sub.REF &lt;V.sub.B. 
As described above, the detector according to the present invention is able 
to vary the decision range of coincidence by adjusting the reference 
voltage V.sub.REF precisely so that it is possible to decide the 
coincidence of two input signals V.sub.A, V.sub.B under the condition that 
the input signal V.sub.A is nearly equal to the input signal V.sub.B, by 
reducing the reference voltage V.sub.REF. Conversely, it is possible to 
decide the coincidence of two input signals V.sub.A, V.sub.B under the 
condition that the signal V.sub.A is quite different from the signal 
V.sub.B by increasing the reference voltage V.sub.REF. Therefore, an 
extent of approximation for the decision can be set up optionally. To vary 
the reference voltage V.sub.REF a variable resistor may be used instead of 
the resistor R.sub.3 or R.sub.4. Further, by using an integrated circuit 
(IC) which has four operational amplifiers in a package, the detector can 
be remarkably reduced in terms of circuit scale to less than the 
conventional system described above and thereby the circuit in FIG. 4 can 
be constructed using only two small analog ICs. 
As described above, the detector according to the present invention 
normally watches for elevation of two signal levels, and by an 
approximation of the difference between the two signal levels by 
comparison of the signal levels, decides whether one signal level is 
coincident with the other signal level when the extent of approximation is 
within the limit of a predetermined reference voltage. Therefore, the 
detector according to the present invention has a distinct advantage of 
being able to make a decision on coincidence by simple comparison. 
Further, the detector according to the present invention can be made 
cheaply by using a general use operational amplifier and a comparator, and 
the detector can be miniaturized by not adding an adjusting circuit.