FIN TO FIN TRENCH CONTACT THROUGH A METAL GATE CUT

Embodiments described herein may be related to apparatuses, processes, and techniques related to manufacturing a gate structure that includes adjacent gates that are coupled with the first fin and a second fin, with a metal gate cut across the adjacent gates and a trench connector between the adjacent gates that electrically couples the first fin and the second fin. Other embodiments may be described and/or claimed.

FIELD

Embodiments of the present disclosure generally relate to the field of semiconductor packaging, and in particular to metal gate cuts within a transistor structure.

BACKGROUND

Continued growth in virtual machines, cloud computing, and portable devices will continue to increase the demand for high density transistors within chips and packages.

DETAILED DESCRIPTION

Embodiments described herein may be related to apparatuses, processes, and techniques directed to manufacturing a gate structure that includes adjacent gates that are coupled with the first fin and a second fin, with a metal gate cut across the adjacent gates and a trench connector (TCN) between the adjacent gates that electrically couples the first fin and the second fin. In embodiments, after a metal gate cut is implemented across the adjacent gates, an etchable material is grown between the faces of the cuts in the respective gates, a dielectric is regrown in a volume of the dielectric removed by the metal gate cut, and another dielectric replaces the etchable material. A TCN may then be placed within the dielectric between the two cuts in the adjacent gates. Other process embodiments may be disclosed herein.

In embodiments, a TCN pass-through may be enabled by a cell designer even though a metal gate cut is used across multiple gates. In embodiments, the process flows described herein may comport with known self-aligned contact (SAC) processes. For example, in embodiments, once a dielectric on dielectric deposition is performed within the metal gate cut, the manufacturing process may revert to known SAC processes, for example using nitride as a block during an oxide etch.

As complementary metal oxide semiconductor (CMOS) technology scales further, edge placement error (EPE) in a direction perpendicular to a gate may be facilitated by a SAC process scheme. Concurrently, the use of metal gate cuts in a direction perpendicular to a fin may facilitate scaling and increased component density, allowing for tighter Gate Extension past Fin critical dimension as well as tighter cut. In addition, a TCN implemented as a pass-through that allows a TCN to be routed past a metal gate cut to electrically couple one or more fins will further facilitate cell design, freeing interconnect at metal 0 or above from having to perform that connection.

Various Figures herein may depict one or more layers of one or more package assemblies. The layers depicted herein are depicted as examples of relative positions of the layers of the different package assemblies. The layers are depicted for the purposes of explanation, and are not drawn to scale. Therefore, comparative sizes of layers should not be assumed from the Figures, and sizes, thicknesses, or dimensions may be assumed for some embodiments only where specifically indicated or discussed.

FIG.1illustrates legacy implementation of a metal gate cut with a TCN within a transistor structure. Transistor structure100illustrates a perspective view of a legacy gate structure that includes a silicon substrate102that is coupled with one or more fins104with a dielectric106separating the fins104. A gate108is positioned across the plurality of fins104, that separates a source side104aof a fin104from a drain side104bof a fin104.

Transistor structure120shows a top-down view of a legacy structure that includes a number of metal gate cuts122through gates124, which may be similar to gate108, that are perpendicular to fins126, which may be similar to fins104.

Transistor structure140shows a side view along the cut of A-A′ of transistor structure120top-down view. Transistor structure140shows a metal gate cut142, which may be similar to metal gate cut122, through gate144, which may be similar to gate124. The metal gate cut142goes completely through the gate144, and is substantially parallel to the fins146, which may be similar to fins126.

Transistor structure160shows a side view along the cut of B-B′ of transistor structure120top-down view. Transistor structure160shows a TCN pass-through168that has been placed over the metal gate cut142. This proves that in that legacy process, the dielectric TCN patterning etches both silicon nitride and silicon oxide. The top of the TCN is located in a horizontal plane above the top of the metal gate of transistor structure140. These features are indication that the patterning of the TCN was performed with no specific self-alignment scheme with respect to the gates.

Transistor structure180shows a side view along the cut of C-C′ of transistor structure120top-down view. Transistor structure180shows metal gate cut142and two separate TCNs167,169.

Transistor structure190shows a diagram that includes multiple fins196, which may be similar to fins146, gates194, which may be similar to gates124, and metal gate cuts192, which may be similar to metal gate cuts122. As shown, a TCN198, which may be similar to TCN168goes over the MGC.

FIGS.2A-2Fillustrate manufacturing stages of a transistor structure in a legacy implementation of a self-aligned contact (SAC) process.FIG.2Ashows a top view200and a cross section205that includes a metal gate202with a gate cap204and that is surrounded by a gate spacer206. The gate spacers206are separated by a dielectric208. Epitaxies212, which serve as a source or a drain, are positioned as raised extension of a fin structure214.FIG.2Arepresents a manufacturing stage after a gate formation and subsequent replacement metal gate process has been applied.

FIG.2Bshows a top view210and a cross-section215where a photoresist216is applied to a top of the transistor structure prior to etching.

FIG.2Cshows a top view220, and a cross-section225, where a selective SiO2etch has been applied to etch the dielectric208to expose the epitaxy212. Note that the gate cap204and gate spacer206are unaffected since the etch selectively removes SiO2only. This step is called Self-Aligned Contact (SAC) etch since the resulting contact pattern between gates is not directly set by the opening in the resist resulting from photolithography but instead is self-aligned to the gate due to the selective nature of the etch. Implementing a SAC process for gate pitches smaller than 50 nm will significantly reduce yield loss due to contact to gate electrical shorts.

FIG.2Dshows a top view230and a cross-section235where the photoresist216has been removed.

FIG.2Eshows a top view240and a cross-section245, where a contact metal fill218has been applied.

FIG.2Fshows a result of the transistor structure after a contact polish, where the contact metal fill222is coupled with the epitaxy212. In embodiments, the contact metal fill222may serve as a TCN, as discussed further below.

FIGS.3A-3Cillustrate manufacturing stages in a legacy implementation of a self-aligned contact process that includes a metal gate cut.FIGS.3A-3Crepresent alternative manufacturing stages toFIGS.2D-2Fas described above.

FIG.3Ashows a top view300of the transistor structure, that may be similar to top view230ofFIG.2D. A metal gate302with a gate cap304is surrounded by a gate spacer306. The gate spacers306are separated by a dielectric308. Epitaxies312, which serve as a source or a drain, are positioned as raised extensions of a fin structure314. These may be similar to metal gate202, gate cap204, a gate spacer206, dielectric208, epitaxies212, and fin structure214ofFIGS.2A-2F. A metal gate cut317is placed as shown in the B-B′ cut line and refilled with silicon nitride (SiN). The transistor structure is also shown at a A-A′ cross-section305and a B-B′ cross-section307.

FIG.3Bshows a top view320and a cross-section at A-A′328, where a contact metal fill318is deposited onto the transistor structure.

FIG.3Cshows a top view330, a cross-section at A-A′335, and a cross section at B-B′337, after a contact polish has been performed. As shown, the resulting TCN332has been significantly encroached into by the metal gate cut317. In other implementations, a metal gate cut such as317that was applied to multiple gates302would completely sever a TCN such as TCN332. It should be noted that legacy SAC implementation requiring the contact etch to be selective to the gate cap, and by the same token to the material used to refill the metal gate cut, is not compatible as-is with the fabrication of a TCN pass-through.

FIG.4illustrates a legacy implementation of a transistor structure with a broken TCN due to a metal gate cut. Transistor structure top-down view400, which is similar to the transistor structure shown with respect toFIG.3C, shows a metal gate cut417that cuts multiple gates402in a direction that is parallel to multiple fins414. A trench connector432, that is similar to trench connector332ofFIG.3C, in this case is completely severed by the metal gate cut417, resulting in an electrical disconnection between two of the fins414. InFIG.3C, for clarity, the contacts are not shown as extending laterally to be in contact with the outer sides of the spacers; however, in embodiments, they may be in contact.

FIG.5shows a transistor structure with a TCN coupling two fins where the TCN is between a metal gate cut in two gates, in accordance with various embodiments. Transistor structure top-down view500shows a plurality of gates502that include cuts517within the gates502. The gates502are substantially perpendicular with a plurality of fins514. A TCN532is located in between the cuts517in the gates502, and is shown as completely connecting two of the fins514. The cuts517may be filled with a silicon nitride (SiN), in embodiments as discussed further below.

FIGS.6A-6Hillustrate manufacturing stages in a self-aligned contact process to implement metal gate cuts across adjacent gates that includes dielectric refill between the adjacent gates, in accordance with various embodiments.

FIG.6Ashows a top-down view of a transistor structure that includes a plurality of metal gates602that are in contact with a plurality of fins614with a dielectric608interspersed between the fins614and the metal gates602. In embodiments, the top-down view of transistor structure ofFIG.6Ais after a replacement metal gate process has been applied. Metal is therefore exposed at the top of the gate after the polishing.

FIG.6Bshows metal gate cuts617, which may be similar to metal gate cut417ofFIG.4, applied to cut the one or more metal gates602. In embodiments, the metal gate cut process may be a nonselective metal gate cut that removes all material, including dielectric material608and metal gate602material including a gate, gate dielectric, gate spacer and gate metal. UnlikeFIG.4that shows the process after the cuts have been refilled by a dielectric,FIG.6Brepresents the top view after the etch. The cuts617expose the silicon substrate at the base of the cuts. In embodiments, the width of the cuts may typically be in a range of 8 nm to 50 nm, or more narrowly be in a range of 12 nm to 20 nm.

FIG.6Cshows top-down transistor structure view600that shows an organic passivation619grown on exposed metal of the gate602after the metal gate cut617. In embodiments, this may be a passivation material that may be subsequently etched. View605shows a top-down transistor structure view just below the organic passivation619at the very top of the transistor structure. In embodiments, the passivation619may continue to be grown until the passivation layer619on either side of the metal gate602grow together as discussed below.

FIG.6Dshows a transistor structure top-down view610, that shows the passivation layer619, as well as the portion of the passivation layer621that has grown together at the level of the cuts in the metal gates602. As shown, a dielectric material623has been deposited to fill in holes in the dielectric608that were made by the metal gate cut617. In embodiments, the dielectric material623will fill in those areas other than the areas already refilled in by the passivation619. Transistor structure top-down view615shows a top-down view just under the top passivation layer621. In embodiments, the dielectric material623may be a silicon dioxide (SiO2) material grown selectively on the dielectric608. SiO2material using a dielectric on dielectric selective atomic-layer deposition technique.

FIG.6Eshows a top-down view620and a top-down view just under the top passivation layer625of a continuation of the process described with respect toFIG.6D, where the dielectric deposition623continues to fill in areas within the metal gate cut617that are not already filled in by the passivation layer deposition621.

FIG.6Fshows a transistor structure top-down view630, and top-down view635just below the top layer of the transition structure, where the passivation619has been stripped to leave cavities629between the cuts in the gate602made by the metal gate cut617. In embodiments, an atomic layer deposition (ALD) SiO2deposition followed by isotropic SiO2etch, may be used to fill any seams and to widen the cavity629. In embodiments, this may be done to prevent future shorts between a TCN to be deposited as described below, and the gate602.

FIG.6Gshows a top-down view of a transistor structure where a gate cut plug631has been deposited into the cavity629ofFIG.6F. In embodiments, the gate cut plug631may be a conformal silicon nitride deposited using an Atomic-Layer Deposition (ALD) technique.FIG.6Galso shows the result of a chemical mechanical polish applied to the top of the transistor structure and used to polish away the excess ALD SiN deposited on top of the structure.

FIG.6Hshows a gate cap633, which may be similar to gate cap304ofFIG.3. To manufacture this gate cap633, a controlled selective metal etch has been applied to recess the gate stack followed by a SiN refill and a polishing. In embodiments, after the manufacturing stage showed with respect toFIG.6H, a regular SAC process may be continued to further manufacture the transistor structure. This is because only oxide is now present in between the gates, and as seen from above the gates are covered, including at the location of the cuts, by silicon nitride, allowing to use a selective oxide etch to self-aligned TCN trenches with respect to gates and not rely on lithography to perform the pattern of each individual contact, in a manner similar to the one illustrated inFIG.2. TCN pass-through can be manufactured even in between gate cuts.

FIGS.7A-7Fillustrate manufacturing stages in another self-aligned contact process to implement metal gate cuts across adjacent gates that includes dielectric refill between the adjacent gates, in accordance with various embodiments.

FIG.7Ashows a top-down view of a transistor structure that includes a plurality of metal gates702that are in contact with a plurality of fins714with a dielectric708interspersed between the fins714and the metal gates702. In embodiments, the top-down view of transistor structure ofFIG.7Ais after a replacement metal gate process has been applied. Thereafter, the metal gates have been recessed and a SiN cap204processed in the recessed gate, as previously shown in cross section inFIG.2A.

FIG.7Bshows metal gate cuts717, which may be similar to metal gate cut417ofFIG.4, applied to cut the one or more metal gates702. In embodiments, the metal gate cut process may be a nonselective metal gate cut that removes all material, including dielectric material708, gate spacer706and metal gate702material including a gate, gate dielectric, and gate metal.

FIG.7Cshows top-down transistor structure view that shows a sacrificial metal719grown on exposed metal of the gate702after the metal gate cut717, using a selective metal-on-metal Atomic-Layer-Deposition process. In embodiments, this may be a sacrificial Tungsten film that may be subsequently etched. In embodiments, the sacrificial metal719may continue to be grown until the sacrificial metal719on either side of the metal gate702grows together as discussed below.

FIG.7Dshows a transistor structure top-down view, that shows the sacrificial metal719that has grown together between the cuts in the metal gates702. As shown, a dielectric material723has been grown using a selective dielectric on dielectric atomic-layer deposition process to fill in holes in the dielectric708that were made by the metal gate cut717. In embodiments, the dielectric material723will fill in those areas other than the areas filled in by the sacrificial metal719.

FIG.7Eshows a transistor structure top-down view where the sacrificial metal719has been etched selectively to the gate cap and to the dielectric708and the grown dielectric723to leave cavities729between the cuts in the gate702made originally by the non-selective metal gate cut717. In embodiments, an anisotropic tungsten (W) etch may be performed.

FIG.7Fshows a top-down view of a transistor structure where a gate cut plug731has been deposited into the cavity729ofFIG.7E. In embodiments, the gate cut plug731material may be a conformal silicon nitride deposited using an Atomic-Layer Deposition technique.FIG.7Falso shows the result of a chemical mechanical polish applied to the top of the transistor structure so as to remove the silicon nitride that had been deposited by the ALD on top of the structure. A regular SAC process may be continued to further manufacture the transistor structure.

FIG.8illustrates an example process for manufacturing a transistor structure with metal gate cuts across adjacent gates that include dielectric refill and TCN between the adjacent gates, in accordance with various embodiments.

At block802, the process may include identifying a gate structure above a channel structure, the gate structure comprising a first gate and a second gate separated by a trench dielectric, the gate structure coupled with one or more fins.

At block804, the process may further include applying a non-selective metal gate cut from a top of the gate structure through the first gate and through the second gate, the metal gate cut substantially parallel to the one or more fins, the gate cut removing a portion of the first gate, a portion of the second gate, and a portion of the dielectric proximate to the portion of first gate and the portion of second gate, the metal gate cut physically and electrically isolating a first part of the first gate from a second part of the second gate and physically and electrically isolating a first part of the second gate from a second part of the second gate.

At block806, the process may further include depositing a cut material into the removed portion of the first gate and into the removed portion of the second gate.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or gate-all-around transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only Finfet transistors, it should be noted that the invention may also be carried out using planar transistors.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

In some implementations of the invention, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

FIG.9illustrates a computing device900in accordance with one implementation of the invention. The computing device900houses a board902. The board902may include a number of components, including but not limited to a processor904and at least one communication chip906. The processor904is physically and electrically coupled to the board902. In some implementations the at least one communication chip906is also physically and electrically coupled to the board902. In further implementations, the communication chip906is part of the processor904.

The processor904of the computing device900includes an integrated circuit die packaged within the processor904. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip906also includes an integrated circuit die packaged within the communication chip906. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

In further implementations, another component housed within the computing device900may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

FIG.10illustrates an interposer1000that includes one or more embodiments of the invention. The interposer1000is an intervening substrate used to bridge a first substrate1002to a second substrate1004. The first substrate1002may be, for instance, an integrated circuit die. The second substrate1004may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer1000is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer1000may couple an integrated circuit die to a ball grid array (BGA)1006that can subsequently be coupled to the second substrate1004. In some embodiments, the first and second substrates1002/1004are attached to opposing sides of the interposer1000. In other embodiments, the first and second substrates1002/1004are attached to the same side of the interposer1000. And in further embodiments, three or more substrates are interconnected by way of the interposer1000.

The interposer1000may include metal interconnects1008and vias1010, including but not limited to through-silicon vias (TSVs)1012. The interposer1000may further include embedded devices1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer1000. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer1000.

The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit embodiments to the precise forms disclosed. While specific embodiments are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the embodiments, as those skilled in the relevant art will recognize.

These modifications may be made to the embodiments in light of the above detailed description. The terms used in the following claims should not be construed to limit the embodiments to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

EXAMPLES

Example 1 is an integrated circuit structure, comprising: a gate structure having a first gate and a second gate, the first gate and the second gate substantially parallel and separated by a dielectric material, a pitch between the first gate and the second gate less than 50 nm, and wherein the gates include a cap; a first cut region in the first gate that physically and electrically isolates a first portion of the first gate from a second portion of the first gate, wherein the first portion of the first gate is coupled with a first fin, and the second portion of the first gate is coupled with a second fin; a second cut region in the second gate that physically and electrically isolates a first portion of the second gate from a second portion of the second gate, wherein the first portion of the second gate is coupled with the first fin, and the second portion of the second transistor gate is coupled with the second fin; wherein the first cut and the second cut are physically separated by the dielectric; and a trench contact located completely within the dielectric and between the first cut region in the first gate and the second cut region in the second gate, wherein the trench contact couples the first fin and the second fin.

Example 2 may include the integrated circuit structure of example 1, wherein the first cut region and the second cut region are filled with a cut dielectric.

Example 3 may include the integrated circuit structure of example 2, wherein the cut dielectric includes silicon and nitrogen.

Example 4 includes the integrated circuit structure of example 1, wherein the trench contact is electrically coupled with the first fin and the second fin.

Example 5 includes the integrated circuit structure of example 1, wherein the first cut region in the first gate extends completely through the first gate, and wherein the second cut region in the second gate extends completely through the second gate.

Example 6 includes the integrated circuit structure example 1, wherein the first cut region and the second cut region are substantially parallel to the first fin or to the second fin.

Example 7 includes the integrated circuit structure example 1, wherein the first cut region and the second cut region extend into a substrate beneath the first gate and the second gate.

Example 8 includes the integrated circuit structure of example 1, wherein the trench connector is electrically coupled with a third fin.

Example 9 includes the integrated circuit structure of example 1, wherein a material of the cap includes a selected one of: the dielectric or a metal oxide.

Example 10 includes the integrated circuit structure of example 1, wherein a material of the first gate and the second gate include Lanthanum.

Example 11 includes the integrated circuit structure of example 1, where a material of the trench contact includes a selected one or more of: Cobalt, Molybdenum, Tungsten, or Ruthenium.

Example 12 includes the integrated circuit structure of example 1 wherein a width of the trench contact is less than 15 nm.

Example 13 includes the integrated circuit structure of any one of examples 1-12, wherein a width of gate cut width is smaller than 18 nm.

Example 14 includes a method, comprising: identifying a gate structure above a channel structure, the gate structure comprising a first gate and a second gate each with a dielectric cap, wherein the first gate and the second gate are separated by a trench dielectric and have a gate pitch smaller than 50 nm, and wherein the gate structure is coupled with one or more fins; applying a metal gate cut from a top of the gate structure through the first gate and through the second gate, the metal gate cut substantially parallel to the one or more fins, the gate cut removing a portion of the first gate, a portion of the second gate, and a portion of the dielectric proximate to the portion of first gate and the portion of second gate, the metal gate cut physically and electrically isolating a first part of the first gate from a second part of the second gate and physically and electrically isolating a first part of the second gate from a second part of the second gate; and depositing a cut material into the removed portion of the first gate and into the removed portion of the second gate.

Example 15 includes the method of example 14, wherein depositing the cut material into the removed portion of the first gate and into the removed portion of the second gate further comprises: depositing a first material between a first face and a second face of the metal gate cut of the first gate and between a first face and a second face of the metal gate cut of the second gate, wherein the first material between the first face in the second face of the metal gate cut are directly physically coupled; selectively depositing a second material in the removed portion of the dielectric proximate to the removed portion of the first gate and the removed portion of the second gate; removing the first material; and depositing the cut material into a volume created by the removed first material.

Example 16 includes the method of any one of examples 14-15, wherein the first material is an organic passivation layer.

Example 17 includes the method of any one of examples 14-15, wherein the second material includes silicon and oxygen.

Example 18 includes the method of example 17, wherein the second material is grown on a trench dielectric.

Example 19 includes the method of any one of examples 14-18, wherein the first material is a metal.

Example 20 includes the method of any one of examples 14-18, wherein the cut material includes silicon or nitrogen.

Example 21 includes a package comprising: a plurality of transistor structures, a transistor structure comprising: a gate structure having a first gate and a second gate, the first gate and the second gate substantially parallel and separated by a dielectric material; a first cut region in the first gate that physically and electrically isolates a first portion of the first gate from a second portion of the first gate, wherein the first portion of the first gate is coupled with a first fin, and the second portion of the first gate is coupled with a second fin; a second cut region in the second gate that physically and electrically isolates a first portion of the second gate from a second portion of the second gate, wherein the first portion of the second gate is coupled with the first fin, and the second portion of the second gate is coupled with the second fin; wherein the first cut and the second cut are physically separated by the dielectric; and a trench contact located completely within the dielectric and between the first cut region in the first gate and the second cut region in the second gate; and a computing device coupled with the integrated circuit structure.

Example 22 includes the package of example 21, wherein the first fin and the second fin are part of a FinFET.

Example 23 includes the package of example 21, wherein the first cut region and the second cut region are filled with silicon or nitrogen.

Example 24 includes the package of example 21, further comprising: a device electrically coupled with the plurality of transistor structures, wherein the plurality of transistor structures control electrical signals sent to the device.

Example 25 includes the package of example 21, wherein the first gate and the second gate includes silicon.