Cascaded viterbi bitstream generator

A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application is a national stage entry, under 35 U.S.C. §371, of PCT International Patent Application No. PCT/US2013/022321 filed on Jan. 18, 2013, the complete disclosure of which is expressly incorporated herein by reference in its entirety for all purposes.

BACKGROUND

Delta-sigma (ΔΣ) modulation, sometimes referred to as sigma-delta (ΣΔ) modulation, is a well-known technique for converting (i.e., encoding) analog signals into digital signals, or converting higher-resolution digital signals into lower-resolution digital signals. Delta-sigma modulators (or converters) essentially employ oversampling to reduce the in-band power of quantization noise, and use feedback to shape this noise and move it out-of-band. The intrinsic tolerance of delta-sigma converters to analog circuitry inaccuracy renders them very well-suited for the on-chip design of high-resolution interfaces in mixed-signal application-specific integrated circuits (ASICs).

Delta-sigma modulators of various types have been used for analog-to-digital and digital-to-analog conversion over the last several decades. Moreover, delta-sigma modulators have been used in high-efficiency switching power amplifiers (SWPAs), including, for example, class-D SWPAs, commonly used for digital audio applications, and class-S SWPAs, commonly used for radio-frequency (RF) applications.

It is well-known that higher-order (e.g., an order greater than two) one-bit, single-loop delta-sigma modulators suffer from instabilities. To address this shortcoming, cascaded delta-sigma modulators have been proposed which are constructed by cascading a chain of stable, lower-order (usually one-bit) modulators to build a stable higher-order modulator. The output of a cascaded modulator, fabricated from one-bit modulators, forms a multiple-bit bitstream.

More recently, delta-sigma modulators using Viterbi decoders as quantizers with memory were introduced for digital audio applications. (See, e.g., H. Kato, “Trellis Noise-shaping Converters and 1-bit Digital Audio,”Proceedings of the AES112th Convention, Munich, preprint 5615, May 10-13, 2002, and P. Harpe, “Trellis-type Sigma-delta Modulators for Super Audio CD Applications,”Research Report, Philips Research, Jan. 29, 2003, the disclosures of which are incorporated herein by reference in their entireties for all purposes.) As regular (i.e., memory-less or non-Viterbi) higher-order one-bit, single-loop delta-sigma modulators are known to suffer from instabilities, higher-order one-bit, single-loop Viterbi bitstream generators are also more prone to instabilities than lower-order one-bit, single-loop Viterbi bitstream generators.

SUMMARY

Embodiments of the invention provide techniques for forming a stable higher-order (e.g., greater than two) bitstream generator using a plurality of cascaded lower-order bitstream generators.

In accordance with an embodiment of the invention, a bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder adapted to receive an input signal supplied to the bitstream generator and operative to generate a first error signal indicative of a difference between the input signal and a first bitstream candidate that represents a closest approximation to the input signal among a plurality of bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder adapted to receive the first error signal generated by the first adder and operative to generate a second error signal indicative of a difference between the first error signal and a second bitstream candidate that represents a closest approximation to the input signal among a plurality of bitstream candidates generated by the second bitstream generator stage. The bitstream generator further includes a third adder adapted to receive the first and second bitstream candidates generated by the first and second bitstream generator stages, respectively, and operative to generate an output signal that more closely approximates the input signal compared to the first bitstream candidate.

In accordance with an embodiment of the invention, a method for forming a stable higher-order bitstream generator using a plurality of lower-order bitstream generators includes steps of: providing at least first and second bitstream generator stages; connecting the first and second bitstream generator stages in a cascaded arrangement, the first bitstream generator stage including a first adder adapted to receive an input signal supplied to the bitstream generator and operative to generate a first error signal indicative of a difference between the input signal and a first bitstream candidate that represents a closest approximation to the input signal among a plurality of bitstream candidates generated by the first bitstream generator stage, the second bitstream generator stage including a second adder adapted to receive the first error signal generated by the first adder and operative to generate a second error signal indicative of a difference between the first error signal and a second bitstream candidate that represents a closest approximation to the input signal among a plurality of bitstream candidates generated by the second bitstream generator stage; and adding the first and second bitstream candidates generated by the first and second bitstream generator stages, respectively, to thereby generate an output signal of the bitstream generator that more closely approximates the input signal compared to the first bitstream candidate.

Embodiments of the invention will become apparent from the following detailed description thereof, which is to be read in connection with the accompanying drawings.

DETAILED DESCRIPTION

Embodiments of the invention will be described herein in the context of illustrative delta-sigma modulators and Viterbi bitstream generators. It should be understood, however, that embodiments of the invention are not limited to these or any other particular bitstream generators. Rather, embodiments of the invention are more broadly related to techniques for forming a stable Viterbi bitstream generator using a plurality of cascaded single-loop bitstream generators. In this regard, embodiments of the invention provide techniques for forming stable higher-order (e.g., greater than two) bitstream generators. Moreover, it will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the illustrative embodiments shown that are within the scope of the claimed invention. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.

As a preliminary matter, for purposes of clarifying and describing embodiments of the invention, the following table provides a summary of certain acronyms and their corresponding definitions, as the terms are used herein:

Table of Acronym DefinitionsAcronymDefinitionASICApplication-specific integrated circuitSWPASwitching power amplifierRFRadio frequencySTFSignal transfer functionNTFNoise transfer functionMASHMulti-stage noise shapingWCDMAWideband code division multiple accessdBFSSignal level in dB relative to digital full scale

FIG. 1Ais a block diagram depicting an exemplary single-loop delta-sigma modulator100. The delta-sigma modulator100includes an adder102, a loop filter104, or alternative filter circuit, and a bit-quantizer106(or alternative truncator, comparator, slicer, etc.). The adder102comprises a first input adapted to receive an input signal, x1, and a second input adapted to receive a bitstream candidate, y1. The adder102is operative to generate an output signal, x2, which is equal to x1−y1. The loop filter104is adapted to receive, as an input, the signal x2from the adder102and to generate, as an output, a signal x3which is supplied to a first input of the bit-quantizer106. A second input of the bit-quantizer106is adapted to receive an error signal, e1. The error signal e1is the truncation (or quantization) error of the bit-quantizer106and it is given by the difference between the output and input of the bit-quantizer. The bit-quantizer106is operative to generate the output y1, which is indicative of a bitstream candidate that most closely approximates the sampled input signal as a function of the error signal e1and previous bitstream candidates.

FIG. 1Bis a block diagram depicting an exemplary single-loop delta-sigma modulator150. The delta-sigma modulator150is a linearized model of the illustrative delta-sigma modulator100shown inFIG. 1A. In this example, the bit-quantizer106is implemented using an adder108having a first input adapted to receive signal x3generated by loop filter104, and a second input adapted to receive truncation error signal e1. Thus, the bitstream candidate fed back to adder102will be a sum of the error signal e1and the signal x3(i.e., y1=e1+x3) for a given sample period. Output signal y1generated by the adder108, as inFIG. 1A, represents a bitstream candidate that closely approximates the sampled input signal x1in the frequency band of interest where x1has its energy concentrated.

The output signal y1, represented in the z-domain as Y1, can be determined as follows:
Y1=(X1−Y1)·H+E1,  (1)
where H is the transfer function of the modulator's loop filter104. Rearranging terms in equation (1) yields the following derivation:

Y1·(1+H)=X1·H+E1⁢⁢Y1=H1+H·X1+11+H·E1(2)
In equation (2) above, a signal transfer function (STF) of the delta-sigma modulator150can be defined as

STF=H1+H,
and a noise transfer function (NTF) of the delta-sigma modulator can be defined as

NTF=11+H.
Using these definitions for STF and NTF, the output signal Y1can be expressed as follows:
Y1=STF·X1+NTF·E1
Note, that the STF and NTF are based on a linearized model of the delta-sigma modulator150, which is merely an approximation and does not accurately describe the non-linear modulator under all circumstances.

As previously stated, it is well known that higher-order (e.g., greater than two) one-bit, single-loop delta-sigma modulators suffer from instabilities. To address this shortcoming, cascaded delta-sigma modulators have been proposed which are constructed by cascading multiple stable, lower-order modulators (usually one-bit) to build a stable higher-order modulator (see, e.g., Steven R. Norsworthy, Richard Schreier, and Gabor C. Temes, “Delta-Sigma Data Converters: Theory, Design, and Simulation,” IEEE Press, 1997, the disclosure of which is incorporated herein by reference). An output of a cascaded modulator, fabricated from one-bit modulators, forms a multiple-bit bitstream, as will be described in conjunction withFIG. 2.

Specifically,FIG. 2is a block diagram depicting an exemplary third-order delta-sigma modulator200formed using a plurality of cascaded stable one-bit, single-loop delta-sigma modulators. The delta-sigma modulator200employs a multi-stage noise shaping (MASH) architecture, and thus can be referred to as a MASH-III digital delta-sigma modulator. Delta-sigma modulator200includes three stages,202,204and206, each stage comprising a low-order noise-shaping filter and a bit-quantizer (e.g., a comparator or slicer), whose respective outputs are combined, using, for example, a first adder208, so that the low-order filters operate in cascade to provide a higher-order noise-shaping filter.

More particularly, a first stage202includes a second adder210, an amplifier a1coupled with the second adder, a first filter212coupled with an output of amplifier a1, a first bit-quantizer214coupled with an output of the first filter, and a first delay element216coupled with an output of the first bit-quantizer Adder210includes a first input adapted to receive an input signal, u, supplied to the bitstream generator200, and a second input for receiving a bitstream candidate, v1, generated by bit-quantizer214. The adder210is operative to generate an output signal which is equal to the input signal u minus the bitstream candidate v1. The signal generated by adder210is fed to an input of amplifier a1, which in this example has a gain of one (i.e., unity gain). A signal generated by amplifier a1is fed to an input of the filter212which, in this example, has a transfer function

H⁡(z)=z-11-z-1.
The bit-quantizer214is operative to receive the signal generated by the filter212and a first error signal, e1, and to generate the bitstream candidate v1which is supplied to delay element216. The delay element216has a delay of z−2associated therewith, using z-domain representation. The first error signal e1is generated by a third adder218which is operative to subtract the signal generated by filter212from the bitstream candidate v1. The first error signal e1is supplied as an input to the second stage204.

The second stage204includes a fourth adder220, an amplifier a2coupled with the fourth adder, a second filter222coupled with an output of amplifier a2, a second bit-quantizer224coupled with an output of the second filter, and a third digital filter226coupled with an output of the second bit-quantizer. Adder220includes a first input adapted to receive the first error signal e1, and a second input for receiving a bitstream candidate, v2, generated by bit-quantizer224. The adder220is operative to generate an output signal which is equal to the input signal e1minus the bitstream candidate v2. The signal generated by adder220is fed to an input of amplifier a2, which in this example has a gain of one. A signal generated by amplifier a2is fed to an input of the filter222which, in this example, has a transfer function

H⁡(z)=z-11-z-1.
The bit-quantizer224is operative to receive the signal generated by the filter222and a second error signal, e2, and to generate the bitstream candidate v2which is supplied to filter226. The filter226has a transfer function of z−1. (1−z−1) associated therewith, using z-domain representation. The second error signal e2is generated by a fifth adder228which is operative to subtract the signal generated by filter222from the bitstream candidate v2. The second error signal e2is supplied as an input to the third stage206.

Likewise, the third stage206includes a sixth adder230, an amplifier a3coupled with the sixth adder, a fourth filter232coupled with an output of amplifier a3, a third bit-quantizer234coupled with an output of the fourth filter, and a fifth digital filter236coupled with an output of the third bit-quantizer. Adder230includes a first input adapted to receive the second error signal e2, and a second input for receiving a bitstream candidate, v3, generated by bit-quantizer234. The adder230is operative to generate an output signal which is equal to the input error signal e2minus the bitstream candidate v3. The signal generated by adder230is fed to an input of amplifier a3, which in this example has a gain of one. A signal generated by amplifier a3is fed to an input of the filter232which, in this example, has a transfer function

H⁡(z)=z-11-z-1.
The bit-quantizer234is operative to receive the signal generated by the filter232and a third error signal, e3, and to generate the bitstream candidate v3which is supplied to filter236. The filter236has a transfer function of (1−z−1)2associated therewith, using z-domain representation. The truncation error (i.e., quantization error) of the bit-quantizer234, represented by signal e3, can be obtained by subtracting the output of234from the input of234.

As previously described, the respective output signals generated by each of the modulator stages202,204and206are combined by adder208. Specifically, adder208includes a first input adapted to receive a first signal generated by delay element216in the first stage202, a second input adapted to receive a second signal generated by filter226in the second stage204, and a third input adapted to receive a third signal generated by filter236in the third stage206. The adder208is operative to generate an output signal, v, of the bitstream generator200which is equal to a sum of the first and third signals from the first stage202and third stage206, respectively, minus the second signal from the second stage204.

With reference toFIG. 2, the bitstream candidates v1, v2and v3, represented in the z-domain as V1, V2and V3, respectively, can be determined using the following derivation:

V1=(U-V1)·a1·z-11-z-1+E1⁢⁢V1⁡(1-z-1)=a1⁢z-1·U-z-1·V1+(1-z-1)⁢E1⁢⁢V1⁡(1-z-1+a1⁢z-1)=a1⁢z-1·U+(1-z-1)⁢E1⁢⁢V1=a1⁢z-11+(a1-1)⁢z-1·U+1-z-11+(a1-1)⁢z-1·E1(3)
where a1represents the gain of amplifier a1in the first stage202, E1represents the error signal e1in the z-domain, and U represents the input signal u in the z-domain. Assuming a1is equal to one (i.e., unity gain amplifier), equation (3) above reduces to the following expression for determining the bitstream candidate v1:
V1=z−1·U+(1−z−1)E1(4)

In a similar manner, bitstream candidates v2and v3can be determined using the following expressions in the z-domain, assuming gains a2and a3of amplifiers a2and a3, respectively, are also equal to one:
V2=z−1·E1+(1−z−1)E2(5)
V3=z−1·E2+(1−z−1)E3(6)

Using equations (4) through (6) above, and incorporating the respective contributions of the delay element216and the digital filters226and236, the modulator output signal, v, can be determined using the following derivation, in z-domain representation:
V=z−2·V1+z−1·(1−z−1)(−1)·V2+(1−z−1)2·V3
V=z−3·U(1−z−1)3·E3(7)
It is evident from equation (7) that the output signal v is indicative of a third-order, one-bit delta-sigma modulator. Note, that the cascaded output shows only contributions from the truncation error e3of the third stage, while the truncation error e2of the second stage and the truncation error e1of the first stage are cancelled. Therefore, the cascaded delta-sigma modulator effectively eliminates the truncation error of the first one or more stages and improves noise shaping of the truncation error of the last stage.

Delta-sigma modulators (or, more generally, bitstream generators) can be implemented using Viterbi decoders as truncators. With reference now toFIG. 3A, a block diagram depicts an illustrative one-bit, single-loop Viterbi bitstream generator300. In bitstream generator300, the truncator is implemented as a Viterbi decoder which provides bitstream candidates yC1through yCN. These bitstream candidates yC1through yCNare subtracted from an input x supplied to the modulator to generate corresponding sum signals s1through sN; signals s1through sNare then filtered by a loop filter which generates corresponding filtered error signals e1through eN. Each bitstream candidate y1produces a corresponding filtered error signal e1, i=1 . . . N. These filtered error signals e1through eNare sorted by a sorter and the best bitstream candidate of the plurality of candidates, yC, is selected as an output y of the bitstream generator.

More particularly, the bitstream generator300comprises an adder302, a loop filter304, a sorter306, and a Viterbi decoder308, connected in a closed-loop feedback configuration. The adder302is operative to combine bitstream candidates, y1through yN, generated by the Viterbi decoder308with an input signal, x, supplied to the modulator300, and to generate respective output signals, s1through sN, with each output signal being indicative of a subtraction of a corresponding bitstream candidate from the input signal x, where N is an integer greater than one (e.g., s1=x−yC1; sN=x−yCN).

Each of the output signals s1through sNis passed through the filter304, having a transfer function H(z), to generate a plurality of corresponding error signals, e1through eN, referred to collectively herein as error e. Thus, each of the error signals e1through eNrepresents a difference between the input signal x and a corresponding one of the bitstream candidates yC1through yCN, respectively. These error signals are then sorted in order of magnitude of error by the sorter306. The Viterbi decoder308uses this error signal to control how the bitstream candidates are generated. A “best” bitstream candidate310, indicative of a bitstream candidate having a smallest error among a prescribed number of previously stored candidates, is selected as the output signal y of the modulator300.

An output signal Y of the modulator300, in z-domain representation, can be determined using the following derivation:

(X-YC)·H=E;Y=YC,where⁢⁢E⁢⁢is⁢⁢minimum⁢⁢Y=X-E·1H⁢⁢Y=X·STF-E·NTF(8)
In equation (8) above, an STF of the modulator300is assumed to be equal to one (i.e., STF=1), and an NTF is assumed to be equal to 1/H. The error signal E is assumed to be white and uncorrelated with input signal X.

FIG. 3Bis a block diagram depicting an exemplary one-bit, single-loop Viterbi bitstream generator350. The bitstream generator350is merely an alternative representation of the illustrative bitstream generator300shown inFIG. 3A. The N-wire wide signals shown inFIG. 3Aare merely combined into N-wire wide signal busses inFIG. 3B.

A Viterbi decoder can be implemented using various known algorithms. One possibility is to use a full-trellis implementation of the Viterbi algorithm (see, e.g., Andrew Viterbi, “Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm,”IEEE Transactions on Information Theory, Vol. 13, No. 2, pp. 260-269, April 1967, the disclosure of which is incorporated by reference herein in its entirety). An alternative possibility is to use a sub-optimal algorithm such as an M-algorithm (see, e.g., R.-K. Gopalan and O. M. Collins, “An Optimization Approach to Single-Bit Quantization,”IEEE Transactions on Circuits and Systems—Part I, Vol. 56, Issue 2, pp. 2655-2668, December 2009, the disclosure of which is incorporated by reference herein in its entirety). The M-algorithm trades signal-to-noise (SNR) performance of the encoded signal with complexity of the digital hardware implementation. With an increased number of M states used in the M-algorithm, both the SNR performance and the digital hardware complexity of the Viterbi bitstream generator improve.

The stability of a delta-sigma modulator or a Viterbi bitstream generator depends on one or more factors, such as, for example:An order of a transfer function, H(z), of the digital loop filter in the delta-sigma modulator or Viterbi bitstream generator. A higher order H(z) exhibits more fragile stability than a lower order H(z).A frequency response of H(z), which can be characterized by the out-of-band gain of H(z) and by the sharpness of the frequency response of H(z). The sharper the frequency response of H(z), the noise shaping is said to be more aggressive and the delta-sigma modulator or Viterbi bitstream generator is more prone to instability (i.e., it has a fragile stability). Also, the sharper the frequency response of H(z), the longer it takes the impulse response h(t) to effectively settle in the time domain; therefore, a larger value is needed for M when the Viterbi bitstream generator is implemented via the M-algorithm

In general, a higher order H(z) also exhibits better SNR performance than a lower order H(z), and, furthermore, a sharper H(z) exhibits better SNR performance than a less sharp H(z).

The stability of the Viterbi bitstream generator also depends on an implementation of the Viterbi decoder. Since the digital hardware complexity of a full-trellis Viterbi decoder is usually impractical when used as a bitstream generator, the M-algorithm implementation provides a good compromise between SNR performance and hardware complexity. Hence, there is a tradeoff between SNR performance, hardware complexity and stability when designing bitstream generators.

As previously stated, one disadvantage of a high-order one-bit, single-loop bitstream generator such as300(or350) is that it suffers from instabilities. To address this shortcoming, embodiments of the invention provide a cascaded Viterbi bitstream generator architecture. The cascaded Viterbi bitstream generator architecture according to embodiments of the invention employs a plurality of stable lower-order bitstream generators to fabricate a stable higher-order bitstream generator. As will be described in further detail below, the cascaded Viterbi bitstream generator in accordance with embodiments of the invention preserves the robust stability of the first stage and keeps the high SNR performance of the second stage via the beneficial cascading architecture.

FIG. 4is a block diagram depicting at least a portion of an exemplary cascaded Viterbi bitstream generator400, according to an embodiment of the invention. The bitstream generator400comprises two single-loop bitstream generators,402and404, connected in a cascade configuration. While two single-loop bitstream generators are shown inFIG. 4, it is to be appreciated that embodiments of the invention are not limited to any specific number of cascaded single-loop bitstream generator stages employed. Rather, techniques according to embodiments of the invention can be extended in a similar manner to cascade more than two low-order and stable Viterbi bitstream generators, as will become apparent to those skilled in the art given the teachings herein.

More particularly, a first single-loop bitstream generator stage402includes an adder406, a loop filter408, a sorter (SORT 1)410, and a Viterbi decoder (VITERBI 1)412, connected in a closed-loop feedback configuration. It is to be understood that one or more functional blocks in the first bitstream generator stage402may be combined into a single functional block and/or integrated with one or more other blocks. Furthermore, it is to be appreciated that one or more functional blocks in the first bitstream generator stage402may be implemented in hardware, in software, or in a combination of hardware and software (e.g., firmware), according to embodiments of the invention.

The adder406is operative to combine a bitstream candidate signal, yC1i, generated by the Viterbi decoder412with an input signal, x1, supplied to the bitstream generator400, and to generate a combined output signal, x2, indicative of a subtraction of the bitstream candidate signal yC1ifrom the input signal x1(i.e., x2=x1−yC1i). The bitstream candidate signal yC1irepresents a quantized estimate of the input signal x1. Signal x2, which represents an error between the input signal x1and the quantized estimate of the input signal, is then passed through loop filter408having a transfer function H1(z). The loop filter408is operative to receive the signal x2and to generate a filtered error signal, e1. The filtered error signal e1is fed to the sorter410which arranges the bitstream candidates as a function of a magnitude of error and selects a bitstream candidate, y1, having a minimum error value among the candidates. Thus, the sorter410, in conjunction with the Viterbi decoder412, is operative to select a bitstream candidate, among a plurality of candidates yC1i(i=1 through N, where N is an integer), which has a smallest error value (“BEST” candidate) and therefore represents a closer approximation to the input signal x1compared to other bitstream candidates processed by the first single-loop bitstream generator stage402.

Similarly, a second single-loop bitstream generator stage404includes an adder416, a loop filter418, a sorter (SORT 2)420, and a Viterbi decoder (VITERBI 2)422, connected in a closed-loop feedback configuration. The adder416is operative to combine a bitstream candidate signal, yC2i, generated by the Viterbi decoder422with an input signal, which in this case is the error signal x2generated by the adder406in the first bitstream generator stage402, and to generate a combined output signal, x3, indicative of a subtraction of the bitstream candidate signal yC2ifrom the input signal x2(i.e., x3=x2−yC2i). The bitstream candidate signal yC2irepresents a more accurate quantization of the error compared to the bitstream candidate signal yC1i.

Signal x3, which represents a difference between signal x2and the bitstream candidate signal yC2i, is then passed through loop filter418having a transfer function H2(z). The loop filter418is operative to receive the signal x3and to generate a filtered error signal, e2. The filtered error signal e2is fed to the sorter420which arranges bitstream candidates as a function of a magnitude of error and selects a bitstream candidate, y2, having a minimum error value among the candidates. The sorter420, in conjunction with the Viterbi decoder422, is operative to select a bitstream candidate, among a plurality of candidates yC2i(i=1 through N), having a smallest error value (“BEST” candidate) and therefore represents a closer approximation to the signal x2compared to other bitstream candidates processed by the second single-loop bitstream generator stage404.

It is to be appreciated that, although shown as separate functional modules for clarity purposes, it is contemplated that one or more modules in the cascaded Viterbi bitstream generator400can be combined together and/or integrated with one or more other modules, with the resulting module(s) incorporating the respective functions of the combined modules. For example, the Viterbi decoder412can be combined with the sorter410, according to embodiments of the invention, to implement a Viterbi decoder that incorporates a sorting function therein.

A global output signal, y, generated by the cascaded Viterbi bitstream generator400is produced by combining the respective outputs from the individual single-loop bitstream generator stages402and404. To accomplish this, the cascaded bitstream generator400includes an adder424, or alternative combination circuitry, operative to add the bitstream signal y2generated by the second bitstream generator stage404from the bitstream signal y1generated by the first bitstream generator stage402(i.e., y=y1+y2). The output signal y beneficially provides a more accurate approximation to the input signal x1than the individual bitstream signal y1output by the first bitstream generator stage402.

The output signal y of the cascaded Viterbi bitstream generator400, in z-domain representation, is calculated using the following derivation, where capital letters are used to denote corresponding signals in the z-domain:
(X1−YC1i)·H1=E1,
where Y1=YC1i|E1=minimum, which leads to

Y1=X1-1H⁢⁢1·E1Y2=X2-1H⁢⁢2·E2X2=1H⁢⁢1·E1
The output Y is given by Y=Y1+Y2, and therefore

Y=Y1+Y2=(X1-1H⁢⁢1·E1)+(X2-1H⁢⁢2·E2)⁢⁢Y=X1-1H⁢⁢2·E2(9)
In equation (9) above, the output Y of the cascaded Viterbi bitstream generator400includes only the noise-shaped truncation error terms from the second stage

1H⁢⁢2·E2,
and the noise-shaped truncation error terms from the first stage, namely,

1H⁢⁢1·E1,
are beneficially cancelled (or at least reduced).

The above derivations provide guidance on how to design the digital filter transfer functions H1 and H2, as described in further detail below with reference to the exemplary Viterbi bitstream generator400shown inFIG. 4. Illustrative examples of these transfer functions can be deduced from MATLAB® (a registered trademark of The Math Works, Inc.) simulation results shown inFIGS. 6 through 10, according to embodiments of the invention.

Specifically, the transfer function H1(z) of filter408in the first stage402is designed, in accordance with an embodiment of the invention, having good stability for full-scale amplitude input signals, but with modest signal-to-noise ratio (SNR) performance (e.g., about 30 to 50 dB). The second stage404quantizes the noise-shaped error term of the first stage402, namely,

1H⁢⁢1·E1,
which was relatively small power (e.g., about −40 to −30 decibels relative to digital full scale (dBFS)) in the frequency band of interest. Therefore, the transfer function H2(z) of filter418in the second stage404should be designed having good stability for small input signals (e.g., about −40 to −30 dBFS), but should exhibit very good SNR performance (e.g., about 60 to 80 dB). Such a Viterbi bitstream generator with very good SNR performance (e.g., about 60 to 80 dB) for small input signals (e.g., about −40 to −30 dBFS) would have poor stability for large input signals (e.g., about −10 to 0 dBFS). Thus, the first stage402trades SNR performance for large input signal stability, while the second stage404trades large input signal stability for SNR performance. The resulting cascaded output Y exhibits the full-scale (i.e., about 0 dBFS) stability of the first stage402and the very good SNR performance of the second stage404, therefore keeping the best characteristics of each stage, cancels the undesired high truncation error terms of the first stage

(1H⁢⁢1·E1),
and outputs the low truncation error terms of the second stage

(1H⁢⁢2·E2),
as shown above in equation (9).

FIG. 5is a block diagram depicting at least a portion of an exemplary cascaded Viterbi bitstream generator500, according to another embodiment of the invention. Bitstream generator500essentially extends principles utilized in the illustrative bitstream generator400shown inFIG. 4by cascading a third single-loop bitstream generator stage502to the first and second single-loop bitstream generator stages402and404, respectively, described above in conjunction withFIG. 4.

With continued reference again toFIG. 5, like each of the first and second single-loop bitstream generator stages402and404, respectively, previously described in conjunction withFIG. 4, a third single-loop bitstream generator stage502includes an adder506, a loop filter508, a sorter (SORT 3)510, and a Viterbi decoder (VITERBI 3)512, connected in a closed-loop feedback configuration. The adder506is operative to combine a bitstream candidate signal, yC3i, generated by the Viterbi decoder512with an input signal, which in this case is the error signal x3generated by the adder416in the second bitstream generator stage404, and to generate a combined output signal, x4, indicative of a subtraction of the bitstream candidate signal yC3ifrom the input signal x3(i.e., x4=x3−yC3i).

Signal x4, which represents a difference between signal x3and the bitstream candidate signal yC3i, is then passed through loop filter508having a transfer function H3(z). The loop filter508is operative to receive the signal x4and to generate a filtered error signal, e3. The filtered error signal e3is fed to the sorter510which is operative to arrange bitstream candidates as a function of a magnitude of error, and to select a bitstream candidate, y3, having a minimum error value among the stored candidates. The sorter510, in conjunction with the Viterbi decoder512, is operative to select a bitstream candidate, among a plurality of candidates yC3i(i=1 through N, where N is an integer), having a smallest error value (“BEST” candidate) and therefore represents a closer approximation to the input signal x4compared to other bitstream candidates processed by the third single-loop bitstream generator stage502.

An output signal, y, generated by the cascaded Viterbi bitstream generator500is produced by combining the respective outputs from the individual single-loop bitstream generator stages402,404and502. To accomplish this, the bitstream generator500includes an adder514, or alternative combination circuitry, operative to add the bitstream signals y2and y3generated by the second and third bitstream generator stages404and502, respectively, to the bitstream signal y1generated by the first bitstream generator stage402(i.e., y=y1+y2+y3). The output signal y generated by the bitstream generator500, which includes three cascaded single-loop bitstream generator stages, beneficially provides a more accurate approximation to the input signal x1than the individual bitstream signal output y1generated by the first bitstream generator stage402.

Moreover, the output signal y generated by the bitstream generator500shown inFIG. 5, which includes three cascaded single-loop bitstream generator stages, generally provides a beneficially more accurate approximation to the input signal x1compared to the Viterbi bitstream generator400shown inFIG. 4, which includes two cascaded single-loop bitstream generator stages. Hence, the number of cascaded single-loop bitstream generator stages in the Viterbi bitstream generator can be advantageously controlled to produce a required level of accuracy of the output signal, according to embodiments of the invention.

The output signal y of the cascaded Viterbi bitstream generator500, in z-domain representation, is calculated using the following derivation, where, as in the expressions above, capital letters are used to denote corresponding signals in the z-domain:

Y1=X1-1H⁢⁢1·E1Y2=X2-1H⁢⁢2·E2Y3=X3-1H⁢⁢3·E3X2=1H⁢⁢1·E1X3=1H⁢⁢2·E2
The output Y is given by Y=Y1+Y2+Y3, and therefore

As apparent from equation (10) above, the output Y of the cascaded Viterbi bitstream generator500includes only the noise-shaped truncation error terms from the third stage,

1H⁢⁢3·E3,
and the noise-shaped truncation error terms from the first stage, namely,

1H⁢⁢1·E1,
and from the second stage, namely,

1H⁢⁢2·E2,
are both beneficially cancelled.

By way of example only and without loss of generality,FIGS. 6 through 10depict MATLAB® simulation results for the illustrative cascaded Viterbi bitstream generator400shown inFIG. 4. The exemplary waveforms shown inFIGS. 6-10were obtained using a sampling frequency of 4.17792 gigahertz (GHz). The input signal (x1) was chosen to be a 40-megahertz (MHz) wide composite modulated signal with eight carriers, each modulated by 5-MHz wideband code division multiple access (WCDMA) signals. The composite modulated signal has undergone a crest-factor reduction (CFR) to 6.5 dB. Spectra of the signals y1, y2(=x1−y1), and y (=y1+y2) are shown inFIGS. 6, 7 and 8, respectively. The performance improvement in excess of 10 dB due to cascading is shown inFIGS. 9 and 10.

At least a portion of the techniques according to embodiments of the present invention may be implemented in an integrated circuit. In forming integrated circuits, identical die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Each die includes a device described herein, and may include other structures and/or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Any of the exemplary circuits illustrated in the accompanying figures, or portions thereof, may be part of an integrated circuit. Integrated circuits so manufactured are considered part of embodiments of the invention.

An integrated circuit in accordance with embodiments of the invention can be employed in essentially any application and/or electronic system in which digital coding and/or modulation/demodulation is utilized. Suitable systems for implementing embodiments of the invention may include, but are not limited, to power amplifiers (e.g., SWPAs), transmitters, receivers, signal generators, communication networks, electronic instruments (e.g., measurement equipment), etc. Systems incorporating such integrated circuits are considered part of embodiments of the invention. Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the embodiments of the invention.

The illustrations of embodiments of the invention described herein are intended to provide a general understanding of the structure of various embodiments, and they are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the structures described herein. Many other embodiments will become apparent to those skilled in the art given the teachings herein; other embodiments are utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of this disclosure. The drawings are also merely representational and are not drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of embodiments of the invention. Although illustrative embodiments of the invention have been described herein with reference to the accompanying drawings, it is to be understood that embodiments of the invention are not limited to those precise embodiments, and that various other changes and modifications are made therein by one skilled in the art without departing from the scope of the appended claims.