High-voltage input receiver using low-voltage devices

An input receiver for stepping down a high-voltage domain input signal into a low-voltage-domain stepped-down signal includes a waveform chopper. The waveform chopper chops the high-voltage domain input signal into a first chopped signal and a second chopped signal. A high-voltage-domain receiver combines the first chopped signal and the second chopped signal into a high-voltage-domain combined signal. A step-down device converts the high-voltage-domain combined signal into a stepped-down low-voltage-domain signal.

TECHNICAL FIELD

This application relates to receivers, and more particularly for a receiver that converts a high-voltage-domain input signal into a received low-voltage-domain signal.

BACKGROUND

As semiconductor technology has advanced into the deep submicron regime, the power supply voltage is scaled down in concert with the scaling down of transistor dimensions. Nevertheless, input/output (I/O) standards from higher-voltage regimes may still need to be supported. But the thick-oxide transistors in modern high-density integrated circuits may not be able to accommodate any voltage higher than some maximum level such as two volts across their gate-source, gate-drain, or source-drain junctions. To safely receive input signals with voltages that exceed such maximum levels, it is conventional to use native transistors in the integrated circuit's input receiver.

An example conventional input receiver100is shown inFIG. 1A. A native NMOS pass transistor105has its gate driven by the internal power supply voltage VDD. This internal voltage VDD is lower than a power supply voltage VDDX that is cycled to by a VDDX-domain input signal102received at a drain of native pass transistor105. The level for VDDX depends upon the signaling protocol for input signal102. For example, one signaling protocol may have input signal102cycle between 0 and 3.3V (VDDX) according to its frequency. In contrast, VDD may equal 1.8V or 1.65 V, which is a safer level for modern devices. In that regard, if 3.3V were impressed across any pair of terminals for native pass transistor105(drain-to-source, gate-to-source, or gate-to-drain), native pass transistor105may fail. More generally, VDD equals approximately one-half of VDDX, regardless of the level for VDDX as determined by the signaling protocol.

As input signal102rises to VDD, it passes through to the drain of native pass transistor105since its voltage threshold is zero volts. The gate-to-source voltage for native pass transistor105eventually drops to zero, which prevents the source of native pass transistor from rising higher than VDD. Although the drain continues to rise to 3.3V in a cycle of input signal voltage102, native pass transistor105is not strained since there is no more than a VDD voltage difference between its drain and source. Similarly, there is never more than a VDD voltage difference between the gate and drain or between the gate and source of native pass transistor105.

A receiver such as an inverter110powered by the VDD power supply voltage inverts the source voltage to produce a VDD-domain or stepped-down output signal115from VDDX-domain input signal102. Inverter110drives output signal115to internal circuitry (not illustrated) of the integrated circuit that includes input receiver100. Although native pass transistor105avoids voltage strain problems in converting VDDX-domain input signal102into a VDD-domain output signal115, input receiver100suffers from a number of problems. For example, an external source drives input signal102. Input receiver100has no control over this external source. Native pass transistor105thus passes whatever duty cycle and slew rate it receives through to inverter110. The duty cycle and slew rate for VDD-domain output signal115from inverter110may thus be unacceptably distorted. In addition, further distortion results from input signal102oscillating between voltage minimums and voltage maximums that differ from the desired levels of ground and VDDX. Moreover, native devices such as native pass transistor105are very sensitive to process variations. Use of input receiver100is thus limited to relatively low input signal frequencies such as in the tens of MHz to satisfy a +/−5% duty cycle error requirement.

Accordingly, there is a need in the art for step-down input receivers providing more accurate performance in higher frequency domains.

SUMMARY

An input receiver is provided that includes a waveform chopper for receiving an input signal. The waveform chopper chops the input signal into a first chopped signal and a second shopped signal with regard to a threshold voltage such as an internal power supply voltage VDD. The waveform chopper passes the input signal to drive the first chopped signal when the input signal cycles above VDD. However, the waveform chopper clamps the first chopped signal at VDD when the input signal cycles below VDD. Similarly, the waveform chopper passes the input signal to drive the second chopped signal when the input signal cycles below VDD but clamps the second chopped signal at VDD when the input signal cycles above VDD.

A VDDX-domain receiver combines the chopped signals into a VDDX-domain combined signal. VDDX is a power supply voltage of approximately twice VDD. The VDDX-domain receiver charges the combined signal to VDDX when the first chopped signal is clamped at VDD. Conversely, the VDDX-domain receiver discharges the combined signal to ground when the second chopped signal is clamped at VDD.

DETAILED DESCRIPTION

An input receiver200illustrated inFIG. 2steps down a high-voltage-domain (VDDX) input signal102into a reduced-voltage-domain (VDD) output signal225with improved duty cycle, slew rate, and voltage minimum and maximum levels. To do so, input receiver200receives VDDX-domain input signal102at a waveform chopper205. In contrast, conventional receiver100discussed with regard toFIG. 1receives input signal102at native pass transistor105. Input signal102is intended to cycle between 0 volts and the high-voltage-domain supply voltage VDDX although it may be off from these minimum and maximum voltage levels due to inaccuracies in the input signal source (not illustrated). In that regard, input receiver200has no control over the quality of input signal102with regard to its slew rate, duty cycle, and maximum and minimum voltage levels since the external source (not illustrated) generates input signal102and drives it to the die (not illustrated) that includes input receiver200. Waveform chopper205chops input signal102with regard to a threshold voltage such as an internal power supply voltage VDD that equals approximately VDDX/2. For example, in one embodiment VDDX may equal 3.3 V whereas VDD may equal 1.8 V or 1.65 V. The VDD voltage level is low enough such that low-voltage domain devices (not illustrated) downstream from input receiver200are not damaged by it. For example, the die containing input receiver200may include both thick-gate-oxide devices as well as thin-gate-oxide devices. The thick-gate-oxide devices are robust to the relatively high level for VDD such as 1.8V. In contrast, the thin-gate oxide devices are not robust to such voltage levels but instead can withstand only reduced voltage levels such as 1 V or lower.

The devices in input receiver200may comprise thick-gate-oxide devices so that they are robust to VDD voltage levels. However, these devices are not robust to VDDX voltage differences. Although input receiver receives VDDX-domain input signal102, the design of input receiver200ensures that each device in input receiver200never has an unsafe voltage level (e.g., VDDX) across any of its terminals (gate-to-source, gate-to-drain, and drain-to-sources) as will be explained further herein.

Waveform chopper205produces two chopped signals: a first chopped signal (padsig_p)230that cycles between VDD and VDDX, and a second chopped signal (padsig_n)240that cycles between 0 V and VDD. Waveform chopper205forms first and second chopped signals padsig_p230and padsig_n240with regard to, for example, VDD. More generally, VDD is representative of a threshold voltage for the chopping performed by waveform chopper205. In that regard, note again that input signal102cycles (ideally) between 0 V and VDDX. Each cycle of input signal102will thus include a lower-half cycle in which input signal102cycles between ground and VDD and an upper-half cycle in which input signal102cycles between VDD and VDDX. Waveform chopper205substantially passes each upper-half cycle of input signal102as first chopped signal padsig_p230. But waveform chopper205clamps first chopped signal padsig_p230at VDD when input signal102drops below VDD in its lower-half cycles. Each cycle of first chopped signal padsig_p230will thus include a clamped half-cycle and a non-clamped half-cycle. The clamped half-cycles correspond to the lower-half cycles for input signal102. The non-clamped half-cycles correspond to the upper-half cycles for input signal102. In the clamped half-cycles, first chopped signal padsig_p230is clamped at VDD during that portion of the lower-half cycle for input signal102when it drops below VDD. In the remaining portions of the clamped half-cycles, first chopped signal padsig_p230substantially equals input signal102as it rises from VDD or falls toward VDD. Similarly, in the non-clamped half-cycles, first chopped signal padsig_p230substantially equals input signal102as it rises and falls between VDD and VDDX in its upper-half cycles.

Similarly, waveform chopper205substantially passes each lower-half cycle of input signal102as a non-clamped half cycle of second chopped signal padsig_n240. However, waveform chopper205clamps second chopped signal padsig_n240at VDD when input signal102rises above VDD in its upper-half cycles. The upper-half cycles for input signal102thus correspond to the clamped half cycles for second chopped input signal padsig_n240. As discussed above, input receiver200has no control over the quality of input signal102. So the upper-half cycles for input signal102may not reach the desired or intended voltage level of VDDX. Similarly, the lower-half cycles for input signal102may not reach 0 V or ground (VSS). Nevertheless, one can be reasonably confident that input signal102is above VDD for a majority of the time in each upper-half cycle. First chopped signal padsig_p230will thus be clamped at VDD for most (or at least an appreciable portion) of each of its clamped half cycles. Similarly, one can be reasonably confident that input signal102is below VDD for a majority of the time in each lower-half cycle. Second chopped signal padsig_n240will thus be clamped at VDD for most (or at least an appreciable portion) of each of its clamped half cycles.

One can therefore appreciate that a “combined” signal that cycles between 0 V and VDDX may be advantageously reconstructed from the clamped half cycles for first and second chopped signals padsig_p230and padsig_n240. For example, suppose that such a combined signal was driven to VDDX whenever first chopped signal padsig_p230is clamped at VDD. Similarly, suppose that the combined signal was grounded whenever second chopped signal padsig_n240is clamped at VDD. Since first chopped signal padsig_p is clamped at VDD as input signal102drops from VDD to ground whereas second chopped signal padsig_n240is clamped at VDD as input signal102rises from VDD to VDDX, the resulting combined signal is inverted or 180 degrees out of phase with input signal102. Generating a combined signal in this fashion is quite advantageous because the combined signal will then have the desired minimum and maximum voltage levels. In contrast, these minimum and maximum voltage levels cannot be guaranteed for input signal102. Moreover, because the clamped VDD levels occur for most of (or at least an appreciable portion of) each clamped half cycle for first and second chopped signals padsig_p230and padsig_n240, the resulting combined signal would then have a desirable duty factor and slew rate. In contrast, the duty cycle and slew rates for input signal102have no such guarantee of a desirable duty factor, slew rate, or maximum and minimum voltage levels.

Referring again toFIG. 2, a VDDX-domain chopped waveform receiver210processes the first and second chopped signals padsig_p230and padsig_n240to produce a combined signal235that cycles as just described to achieve these advantages. The result is that input signal102, which ideally cycles between 0 and VDDX, is processed to produce combined signal235that also cycles between 0 and VDDX. But note that input signal102is not merely reproduced to form combined signal235. Instead, the combination of waveform chopper205and VDDX-domain chopped waveform receiver210improves the slew rate, duty cycle, and enforces the desired minimum and maximum voltage levels for combined signal235as discussed above.

Given these improvements in slew rate, duty cycle, and the signal voltage minimum and maximum levels, a step-down device215such as a native pass transistor may then be used to form a VDD-domain output signal245from combined signal235. As discussed analogously with regard to native pass transistor105ofFIG. 1, step-down device215may comprises an NMOS native pass transistor (not illustrated) that receives VDDX-domain combined signal235at one drain/source terminal to pass a VDD-domain output signal245at its remaining drain/source terminal as controlled by VDD being applied to its gate. There is no voltage threshold loss in a native transistor so VDD-domain output signal245may saturate at VDD (as opposed to VDD minus some threshold voltage) when combined signal235cycles above VDD.

In some embodiments, a hysteresis circuit220such as a Schmitt trigger may further process VDD-domain output signal245to form a final VDD-domain output signal225as discussed further herein. Alternatively, VDD-domain output signal245may be used as an output signal without any hysteresis treatment.

Because of the slew rate and duty cycle adjustment and the enforcement of the desired voltage maximum and minimum levels by the combination of waveform chopper205and VDDX-domain chopped waveform receiver210, input signal102may have a relatively high frequency such as hundreds of MHz or higher yet it may be stepped down from the VDDX domain to the VDD domain without loss of fidelity. These advantageous features may be better appreciated with reference to the following example embodiments.

A circuit diagram for an example waveform chopper205is shown inFIG. 3. A voltage divider formed by a capacitor300in series with a resistor305receives input signal102at a first terminal302of capacitor300. Resistor305couples between a power supply node supplying the internal power supply voltage VDD and a remaining second terminal301for capacitor300. Should input signal102be grounded, a voltage (designated as Vbias) for second terminal301will thus settle to VDD. As input signal102rises to VDD, Vbias will rise slightly higher than VDD but to a level lower than VDDX before settling again to VDD as input signal102continues to rise to VDDX. The actual amount of voltage increase over VDD for Vbias depends upon the voltage division as determined by the resistance of resistor305and capacitance of capacitor300. Conversely, as input signal102falls from VDDX to VDD, Vbias will be pulled temporarily lower than VDD before again settling to its default level of VDD as input signal continues to cycle towards ground and then back towards VDD.

These temporary increases and decreases of Vbias with respect to its default level of VDD are advantageous because Vbias biases the gates of a PMOS pass transistor310and an NMOS pass transistor315in waveform chopper205. The drain/source terminals for PMOS pass transistor310couple between first terminal302of capacitor300and an output node320for carrying first chopped signal padsig_p230. Similarly, the drain/source terminals for NMOS pass transistor315couple between first terminal302and an output node325for carrying second chopped signal padsig_n240. The operation of NMOS pass transistor315will be discussed first.

As input signal102rises from 0 V to VDD, Vbias will jump slightly higher than VDD as discussed above. This rise in the gate voltage on NMOS pass transistor315assists it to pass as much as possible of the rising edge of input signal102through to second chopped signal padsig_n240. But note that NMOS pass transistor315is not a native transistor. This is advantageous in that process variations for second chopped signal padsig_n240are reduced but at the cost of a threshold voltage loss in the rising edge of second chopped signal padsig_n240in comparison to the rising edge of input signal102. This threshold voltage loss is reduced by having Vbias drive the gate of NMOS pass transistor315as opposed to simply biasing this gate with VDD. In addition, an NMOS clamping transistor330has a source coupled to output node325and a drain coupled to a power supply node providing VDD. The gate of NMOS clamping transistor330is driven by the input signal102. Although clamping NMOS transistor330is also a non-native transistor, its gate voltage will rise toward VDDX as input signal102rises to VDDX. Thus, even with a threshold voltage loss, clamping NMOS transistor330may readily clamp second chopped signal padsig_n240at VDD as input signal102rises above VDD towards VDDX.

Operation of PMOS pass transistor310is analogous. As input signal102rises to VDDX, Vbias on the gate of PMOS pass transistor310becomes a virtual ground since Vbias will settle to VDD. As known in the PMOS arts, PMOS transistors pass a strong logic 1. Thus PMOS pass transistor310has no issue with regard to passing the rising edge of input signal102through to first chopped signal padsig_p230as input signal102rises from VDD to VDDX. However, PMOS transistors in general will pass a weak logic 0. To mitigate a resulting distortion on passing the falling edge of input signal102as it falls from VDDX to VDD, Vbias is temporarily pulled below VDD due to the effect of capacitor300as input signal102falls from VDDX to VDD. In this fashion, PMOS pass transistor310may pass more of the falling edge for input signal102through to first chopped signal padsig_p230as input signal102drops to VDD. In addition, a clamping PMOS transistor335has a source coupled to output node320and a remaining drain to a power supply node carrying VDD. The gate of clamping PMOS transistor335is driven by input signal102. Clamping PMOS transistor335will thus be switched on while input signal102drops below VDD to clamp second chopped signal padsig_p230at VDD.

Transistors310,315,330, and335may all comprise thick-gate-oxide transistors such that they are robust to VDD-level voltage differences across their terminals. The biasing of the gates of pass transistors310and315with Vbias protects these transistors as input signal102rises to VDDX. Similarly, the biasing for both the source of clamping transistor335and the drain of clamping transistor330to VDD protects the clamping transistors as input signal102rises to VDDX.

An example waveform for input signal102is shown inFIG. 4along with waveforms for corresponding first and second chopped signals padsig_p230and padsig_n240. Second chopped signal padsig_n240is clamped at VDD for most of each upper-half cycle of input signal102as input signal102rises above VDD. Similarly, first chopped signal padsig_p230is clamped at VDD for most of each lower-half cycle for input signal102as input signal102falls below VDD. One can thus appreciate that the clamped half cycles in which first chopped signal padsig_p230is clamped at VDD and the clamped half cycles in which second chopped signal padsig_n240is clamped at VDD have relatively attractive duty cycles. As will be explained below, chopped waveform receiver210advantageously combines the clamped half cycles—in other words, while first chopped signal padsig_p230is at its VDD clamped level, combined signal235is driven to a logical one level (VDDX) whereas combined signal235is discharged to a logical zero level (VSS) while second chopped signal padsig_n240is clamped at VDD. The “good” half-cycles in chopped signals padsig_p230and padsig_n240are retained (the clamped half cycles) whereas their “bad” half-cycles are discarded (the non-clamped half cycles). In this fashion, the problems discussed earlier with regard to the prior art are conquered—input signal102may have an undesirable slew rate and minimum/maximum levels yet it is processed into combined signal235having the desired minimum level (VSS or ground), the desired maximum level (VDDX or 2*VDD), a desirable slew rate, and a desirable duty cycle.

An example chopped waveform receiver210is shown inFIG. 5. First chopped signal padsig_p230controls a first switch such as a PMOS transistor500. The source of PMOS transistor500is tied to a power supply node for providing VDDX whereas its gate is driven by first chopped signal padsig_p230. The clamped level of VDD for first chopped signal padsig_p230thus acts as a virtual ground for PMOS transistor500and switches this transistor fully on so that it charges its drain to VDDX when first chopped signal padsig_p230is clamped at VDD. A PMOS transistor505couples between the drain of PMOS transistor500and a resistor R1. The bias signal Vbias drives the gate of PMOS transistor505so that PMOS transistor505is also fully on when first chopped signal padsig_p230clamps at VDD.

Second chopped signal padsig_n240controls a second switch such an NMOS transistor515. The source of NMOS transistor515is tied to ground and its gate driven by second chopped signal padsig_n240. As shown inFIG. 4, second chopped signal padsig_n240cycles down to VSS while first chopped signal padsig_p230is clamped at VDD. Thus, when PMOS transistor500is switched on, NMOS transistor515is switched off. The drain of NMOS transistor515couples to a source of another NMOS transistor510having a gate driven by Vbias. Thus, NMOS transistor510will also be off when NMOS transistor515is off. The drain of NMOS transistor510couples to a resistor R2in series with resistor R1. Output signal235is driven from a node between resistors R1and R2. In general, downstream devices (not illustrated) that process combined signal235have a high input impedance such that relatively little current ever flows through resistors R1or R2. The result is that when PMOS transistors500and505are switched on and transistor515switched off, combined signal235is driven to VDDX since there is effectively no resistive voltage drop across resistor R1.

When second chopped signal padsig_n240is clamped at VDD, both NMOS transistors510and515are switched on whereas PMOS transistors505and500are off. Combined signal235is thus discharged to ground in response to chopped signal padsig_n240being clamped at VDD. A PMOS transistor520couples between a power supply node providing VDD and the drain of PMOS transistor500. PMOS transistor520is thus driven on when second chopped signal padsig_n240is clamped at VDD (which discharges combined signal235) to protect PMOS transistor500from unsafe voltage levels. In that regard, PMOS transistor500has its source tied to VDDX and thus cannot have zero volts at its drain or it would be damaged. PMOS transistor520prevents the drain of PMOS transistor505from falling below VDD. Similarly, an NMOS transistor525has its source coupled to a power supply node providing VDD and its drain coupled to the drain of NMOS transistor515. When first chopped signal padsig_p230is clamped at VDD, NMOS transistor525is switched on to charge the source of NMOS transistor510to VDD. In this fashion, NMOS transistor510is protected from excessive voltage levels since its drain is charged to VDDX at that time.

In one embodiment, chopped waveform receiver210may be deemed to comprise a means for combining first chopped signal padsig_p230and the second chopped signal padsig_p240into combined signal235that is charged to VDDX when first chopped signal padsig_p230equals VDD and that is grounded when second chopped signal padsig_n240equals VDD.

Optional hysteresis generator220may comprise a Schmitt trigger or other suitable device. The resulting hysteresis is beneficial to alleviate the “shoulders” shown inFIG. 4for first and second chopped signals padsig_p230and padsig_n240as these signals approach their clamped levels of VDD. These irregularities in voltage occur due to pass transistors310and315being non-native and thus having non-zero threshold voltages. Hysteresis generator220has a high voltage threshold that input signal102must cross for final output signal225to be driven high to VDD. This high voltage threshold may be higher than VDD so that hysteresis generator220is not influenced by the irregularity in first chopped signal padsig_p230as first chopped signal padsig_p230falls towards VDD. Similarly, hysteresis generator220may have a low voltage threshold that is lower than VDD so that hysteresis generator220is not influenced by the irregularity in second chopped signal padsig_n240as second chopped signal padsig_n240rises to VDD. In this fashion, the duty cycle for final output signal225may be improved.

FIG. 6is a flowchart for an example method of operation for an input receiver in accordance with an embodiment of the disclosure. The method begins with a step600of receiving an input signal that cycles between approximately ground and VDDX, VDDX being approximately twice an internal power supply voltage VDD. A step605comprises chopping the input signal into a first chopped signal that substantially equals the input signal when the input signal is greater than VDD and equals VDD when the input signal is less than VDD. Similarly, the method includes a step610of chopping the input signal into a second chopped signal that substantially equals the input signal when the input signal is less than VDD and equals VDD when the input signal is greater than VDD. Finally, the method includes a step615of combining the first chopped signal and the second chopped signal into a combined signal by charging the combined signal to VDDX when the first chopped signal equals VDD and by grounding the combined signal when the second chopped signal equals VDD.