Instruction processing method, instruction processing apparatus, and instruction processing program

An instruction processing method includes generating a translated code block for an instruction, among instructions included in a target program to be executed and for which a number of executions through sequential interpretation is greater than or equal to a threshold, and storing the generated translated code block in a first storage unit and removing part or all of the translated code block from the first storage unit at a given timing, wherein the generating reduces the threshold with respect to the number of executions over a given period of time after the part or all of the translated code block is removed.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2011-61324, filed on Mar. 18, 2011, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to an instruction processing method, an instruction processing apparatus, and an instruction processing program.

BACKGROUND

An interpreter and a just-in-time compiler (hereinafter referred to as the “JIT compiler”) may be used to emulate the operation of a given central processing unit (CPU) when using a CPU having a different architecture. While sequentially interpreting instructions issued by a program, the interpreter monitors how often each instruction is executed. The interpreter inputs a request to translate an instruction having a high frequency of execution into machine code to the JIT compiler. The JIT compiler translates (compiles) the instruction associated with the request into machine code, and records the code obtained through the translation (hereinafter referred to as “translated code”) in a memory area called a code cache. Thereafter, the translated code recorded in the code cache is executed when the instruction is to be executed. Consequently, the speed at which the program is executed is increased.

In general, interpreters measure the number of executions for each instruction, and make a translation request if the number of executions exceeds a given threshold. Interpreters may also increase the threshold if JIT compilers receive a large number of translation requests. For example, if a translation request from an interpreter is managed with a queue, a threshold may be changed in accordance with the length of the queue.

If a given amount or more of translated code is recorded in a code cache, some or all of the existing translated code is removed from the code cache in order to allow new translated code to be recorded. A process for removing translated code from a code cache (that is, for ensuring sufficient available space in the code cache) is generally called garbage collection (GC).

At the time of execution of an instruction after the execution of GC, the probability that no translated code for the instruction to be executed exists increases. Therefore, an instruction which has been executed at a high speed using translated code before the execution of GC may be subjected to sequential interpretation, and performance may be reduced.

The recovery of the performance of an instruction, which has been removed from a code cache by GC, to the extent that existed before the execution of GC involves waiting for the time taken for the number of executions of the instruction to again be greater than or equal to the threshold.

The following are examples of related art: Japanese National Publication of International Patent Application No. 2003-526135, and Japanese National Publication of International Patent Application No. 2002-519752.

SUMMARY

According to an aspect of the invention, an instruction processing method includes generating a translated code block for an instruction, among instructions included in a target program to be executed and for which a number of executions through sequential interpretation is greater than or equal to a threshold, and storing the generated translated code block in a first storage unit and removing part or all of the translated code block from the first storage unit at a given timing, wherein the generating reduces the threshold with respect to the number of executions over a given period of time after the part or all of the translated code block is removed.

DESCRIPTION OF EMBODIMENTS

Embodiments will be described hereinafter with reference to the drawings.FIG. 1is a diagram illustrating an example hardware configuration of an information processing apparatus10according to an embodiment. The information processing apparatus10illustrated inFIG. 1includes a drive device100, an auxiliary storage device102, a memory device103, a CPU104, an interface device105, and any other suitable device, which are connected to one another via a bus B.

A program for implementing a process to be performed in the information processing apparatus10is provided by a recording medium101. When the recording medium101on which a program is recorded is set in the drive device100, the program may be installed into the auxiliary storage device102from the recording medium101through the drive device100. Instead of installing the program from the recording medium101, the program may be downloaded from another computer via a network. The auxiliary storage device102stores an installed program, and also stores files, data, and other desired information.

If there is an instruction for starting a program, the memory device103reads the program from the auxiliary storage device102, and stores the read program. The CPU104executes functions of the information processing apparatus10in accordance with the program stored in the memory device103. The interface device105is used as an interface for connecting to a network.

Examples of the recording medium101may include portable recording media such as a compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), and a universal serial bus (USB) memory. Examples of the auxiliary storage device102may include a hard disk drive (HDD) and a flash memory. The recording medium101and the auxiliary storage device102correspond to computer-readable recording media.

FIG. 2is a diagram illustrating an example functional configuration of an information processing apparatus10according to a first embodiment. InFIG. 2, the information processing apparatus10includes a sequential interpreter11, a translation request queue12, a translator13, a code cache unit14, a translated code remover15, and any other suitable element. The sequential interpreter11, the translator13, and the translated code remover15are implemented by a process that a program installed in the information processing apparatus10causes the CPU104to execute. The translation request queue12and the code cache unit14may be implemented using, for example, the memory device103.

The sequential interpreter11sequentially interprets each instruction of source code or intermediate representation (intermediate code) of a target program being executed Tp, and executes the interpreted instruction. The target program being executed Tp is a set of data representing a program which is used as a target program being executed in this embodiment and which has been loaded into the memory device103. The sequential interpreter11measures, for each instruction included in the target program being executed Tp, the number of executions of the instruction through sequential interpretation (that is, the number of times sequential interpretation has been executed). If an instruction for which the number of executions is greater than or equal to a threshold has occurred, the sequential interpreter11specifies the address of the instruction (that is, information about the position of the instruction in the target program being executed Tp), and enters a translation request in the translation request queue12. The translation request queue12holds translation requests in a form such as a first-in first-out (FIFO) list.

More specifically, the number of executions is measured for a branch destination of each branch instruction included in the target program being executed Tp. Since the numbers of executions of a group of instructions included in a branch instruction match the number of executions measured for the branch destination of each branch instruction, there is no need to measure the number of executions for each instruction. Therefore, a branch destination address is specified in a translation request.

The translator13retrieves a translation request from the translation request queue12, and translates a group of instructions associated with the addresses specified in the retrieved translation request into machine native code. For example, a group of instructions (or an instruction) that exists from an instruction associated with the address specified in the translation request up to the next branch instruction is translated. The code translated (or generated) by the translator13is hereinafter referred to as “translated code”. The translator13stores the translated code in the code cache unit14.

The code cache unit14stores translated code, a management table for storing management information about the translated code, and any other suitable information.

The translated code remover15executes garbage collection (GC) for the code cache unit14. Specifically, the translated code remover15removes (deletes), for example, some or all of all the translated code stored in the code cache unit14and some or all of all the management information stored in the code cache unit14at a desired timing to ensure sufficient space is available in the code cache unit14.

The sequential interpreter11may be implemented by using an “interpreter” program. The translator13may be implemented by using a “just-in-time compiler” program. Further, the translated code remover15may be implemented by using a “garbage collector” program. Each of the sequential interpreter11, the translator13, and the translated code remover15may be composed by a CPU, a digital signal processor (DSP), a processor, or the like.

A processing procedure executed by the information processing apparatus10will now be described.FIG. 3is a diagram depicting an example of a processing procedure executed by the information processing apparatus10according to the first embodiment.

When a target program being executed Tp is loaded into the memory device103and the execution of the target program being executed Tp is started, the following processing procedure is repeatedly executed until the target program being executed Tp has been completed.

First, the sequential interpreter11reads an instruction in the target program being executed Tp (S1). If the read instruction is not a branch instruction, the sequential interpreter11sequentially interprets the instruction, and causes the CPU104to execute the interpreted instruction (S2). If the read instruction is a branch instruction and translated code for a branch destination address corresponding to the branch instruction has not been generated in the code cache unit14, the sequential interpreter11sequentially interprets each instruction corresponding to the branch destination address, and causes the CPU104to execute the interpreted instruction (S2).

If the read instruction is a branch instruction and translated code for a branch destination address has been generated in the code cache unit14, the sequential interpreter11causes the CPU104to execute the translated code (S3). When the execution of the translated code is completed, processing control is returned to the sequential interpreter11(S4).

Whether or not translated code for a branch destination address has been generated as well as the position (address) of translated code in the code cache unit14are determined by, for example, referring to the management table in the code cache unit14.

FIG. 4is a diagram illustrating an example configuration of a management table14Ta according to the first embodiment. InFIG. 4, the management table14Ta stores an address, a number of executions, a translated/untranslated flag, a translated code address, and any other suitable information.

The “address” referred to in the above example configuration of the management table14Ta indicates a branch destination address of an instruction. Not including the address in the management table14Ta may be desirable. The association between the address and each record of the management table14Ta may be managed separately. The “number of executions” indicates the number of sequential executions of a group of instructions associated with the address. The “translated/untranslated flag” is information indicating whether or not translated code for the group of instructions associated with the address has been generated. For example, the value “true” indicates that translated code has been generated (translated), and the value “false” indicates that translated code has not been generated (untranslated). The “translated code address” indicates the position (address) at which translated code is stored in the code cache unit14. The number of executions may be managed elsewhere than the code cache unit14(that is, managed in a form other than the management table14Ta).

Accordingly, if the translated/untranslated flag in the management table14Ta corresponding to a branch destination address is “true”, the sequential interpreter11determines that translated code for the branch destination address has been generated. In this case, the sequential interpreter11specifies the stored position of the translated code based on the translated code address corresponding to the branch destination address.

However, whether or not translated code for a branch destination address has been generated may also be determined based on the translated code address instead of the translated/untranslated flag. Specifically, if a value has been recorded in a translated code address corresponding to the branch destination address, that translated code for the branch destination address has been generated may be determined. In this case, not including the translated/untranslated flag in the management table14Ta may be desirable.

If the instruction read is a branch instruction, in S2, the sequential interpreter11adds 1 to the number of executions for the corresponding branch destination address in the management table14Ta. However, if no record exists for the branch destination address, the sequential interpreter11adds a record corresponding to the branch destination address to the management table14Ta, and records 1 in the number of executions corresponding to the record added.

Referring back toFIG. 3, if the number of executions is greater than or equal to a threshold as a result of the addition of 1, the sequential interpreter11enters a translation request in the translation request queue12(S5). In the translation request, a branch destination address is specified. In the translation request queue12illustrated inFIG. 3, each rectangular shape represents a translation request.

The translator13retrieves the translation requests, which were entered in the translation request queue12, in ascending order by time (S6). The translator13executes a translation process on a group of instructions associated with an address specified in a retrieved translation request (S7). The translated code for the group of instructions is generated through the translation process. The translator13stores the generated translated code in the code cache unit14(S8). In the management table14Ta, the translator13further updates the translated/untranslated flag corresponding to the address specified in the received translation quest to “true”, and records the address at which the translated code is stored in a translated code address corresponding to the address specified in the received translation request.

If the amount of available space in the code cache unit14becomes less than or equal to a given value as a result of, for example, adding a new record to the management table14Ta or storing new translated code in the code cache unit14, a request to execute GC is sent to the translated code remover15(S11or S12).

The translated code remover15executes GC in response to the request (S13). Specifically, the translated code remover15removes (deletes) some or all of all the translated code stored in the code cache unit14and some or all of all the records in the management table14Ta from the code cache unit14(S13). Consequently, the memory space that the removed translated code and the removed records were occupying is released.

If the data to be removed is limited to part of all of the translated code, each record corresponding to the translated code to be removed is to be removed from the management table14Ta. That is, each record that includes a translated code address which corresponds to an address of the translated code to be removed is removed.

Subsequently, the translated code remover15records the time when translated code and other information were removed (hereinafter referred to as the “GC execution time”) in, for example, the memory device103(S14).

The GC execution time may be used to allow the sequential interpreter11to dynamically change the threshold for the number of executions. In S2described above, the sequential interpreter11effectively reduces the threshold over a given period of time from the GC execution time. The reduction of the threshold allows translated code, which may have a smaller number of executions than usual, to be generated over the given period of time from the GC execution time. Therefore, translated code for a group of instructions having a high frequency of execution may be re-generated earlier than if the threshold was not reduced. Thus, the period of time over which the low performance caused by the execution of GC continues may be reduced.

The processing procedure of the sequential interpreter11inFIG. 3will be described in further detail.FIG. 5is a flowchart depicting an example of the processing procedure of the sequential interpreter11according to the first embodiment.FIG. 5illustrates the processing procedure performed when the instruction read is a branch instruction.

The sequential interpreter11refers to the management table14Ta and determines whether or not translated code for a branch destination address that corresponds to the branch instruction exists (S110). If a record corresponding to the branch destination address exists in the management table14Ta and if the value of the translated/untranslated flag corresponding to the record is “true”, the sequential interpreter11determines that the translated code exists. If a record corresponding to the branch destination address does not exist in the management table14Ta or if a record corresponding to the branch destination address exists in the management table14Ta and the value of the translated/untranslated flag corresponding to the record is “false”, the sequential interpreter11determines that the translated code does not exist.

If the translated code does not exist (No in S110), the sequential interpreter11sequentially interprets one or more instructions associated with the branch destination address, and causes the CPU104to execute the interpreted instruction (S120). Subsequently, the sequential interpreter11adds 1 to the number of executions in a record corresponding to the branch destination address in the management table14Ta (S130). If a record corresponding to the branch destination address does not exist, the sequential interpreter11adds a record corresponding to the branch destination address in the management table14Ta, and records 1 in the number of executions corresponding to the record. The number of executions in S170, described below, is equal to the number of executions updated or recorded in S130.

Subsequently, the sequential interpreter11determines whether or not the GC execution time has been recorded in the memory device103(S140). That is, whether or not GC has been executed after the execution of the target program being executed Tp was started is determined. If the GC execution time has been recorded in the memory device103(that is, if GC has been executed) (Yes in S140), the sequential interpreter11calculates the difference between the current time and the GC execution time (that is, the elapsed time after the GC execution time) (S150). The calculation result is assigned to a variable named after_gc_time. If the GC execution time has not been recorded in the memory device103(that is, if GC has not been executed) (No in S140), the sequential interpreter11assigns MAX_GC_TIME to the variable after_gc_time (S160). MAX_GC_TIME represents a period of time after the execution of GC during which the threshold for the number of executions is reduced. This period of time (MAX_GC_TIME) is determined in advance, and is recorded in, for example, the auxiliary storage device102.

After S150or S160is completed, the sequential interpreter11determines whether or not a value represented by expression (1) below is greater than or equal to a threshold (S170):
MAX_GC_TIME×number of executions/min(after—gc_time,MAX_GC_TIME),  (1)

where min(x, y) denotes the minimum value of x and y. If after_gc_time <MAX_GC_TIME (that is, if the elapsed time after the GC execution time is less than MAX_GC_TIME), the value of min (after_gc_time, MAX_GC_TIME) is after_gc_time. If after_gc_time ≧MAX_GC_TIME (that is, if the elapsed time after the GC execution time is greater than or equal to MAX_GC_TIME), the value of min(after_gc_time, MAX_GC_TIME) is MAX_GC_TIME.

Accordingly, in S170, if the elapsed time after the GC execution time is less than MAX_GC_TIME, the value represented by expression (1) is larger than the actual number of executions. If the elapsed time after the GC execution time is greater than or equal to MAX_GC_TIME, the value represented by expression (1) is equal to the actual number of executions. Therefore, if the elapsed time after the GC execution time is less than MAX_GC_TIME, the threshold is effectively reduced, and the shorter the elapsed time, the larger the effective reduction to the threshold. If the elapsed time after the GC execution time is greater than or equal to MAX_GC_TIME, the threshold is equal to the original value.

If the value represented by expression (1) is greater than or equal to the threshold (Yes in S170), the sequential interpreter11generates a translation request in which the branch destination address is specified, and enters the translation request in the translation request queue12(S180), If the value represented by expression (1) is less than the threshold (No in S170), S180is skipped.

If translated code for the branch destination address exists (Yes in S110), the sequential interpreter11causes the CPU104to execute the translated code stored at the translated code address in the management table14Ta associated with the branch destination address (S190).

In the foregoing description, by way of example, the GC execution time is recorded. Alternatively, a timer for measuring a time may be used. In this case, in S14inFIG. 3, the translated code remover15initializes the value of the timer to 0. In S150inFIG. 5, the sequential interpreter11assigns the current value of the timer to after_gc_time.

Next, a second embodiment will be described. The following description will be given of portions of the second embodiment different from those of the first embodiment. For other details not described here, reference may be made to the description of the first embodiment.

FIG. 6is a diagram depicting an example of a processing procedure executed by an information processing apparatus according to the second embodiment. InFIG. 6, portions that are substantially the same as those inFIG. 3are designated by the same reference signs, and a description thereof is omitted.

InFIG. 6, S14areplaces S14inFIG. 3. In S14a, the translated code remover15records the amount of translated code remaining in the code cache unit14at the time of execution of GC (that is, at a time substantially immediately after the execution of GC) (hereinafter referred to as the “amount of translated code at GC execution time”) in, for example, the memory device103.

The amount of translated code at GC execution time may be used to allow the sequential interpreter11to dynamically change the threshold for the number of executions. In S2inFIG. 6, the sequential interpreter11reduces the threshold until the amount of translated code generated changes from the amount of translated code at GC execution time to a given amount of translated code (that is, until the amount of translation performed after the execution of GC has become a given value). Consequently, advantages similar to those in the first embodiment may be achieved. In this manner, the given period of time after the execution of GC may be measured using, instead of time, any other index that changes with time, such as an amount of translated code.

The processing procedure according to the first embodiment illustrated inFIG. 5may be replaced by that illustrated inFIG. 7.FIG. 7is a flowchart depicting an example of a processing procedure of a sequential interpreter11according to the second embodiment. InFIG. 7, portions that are substantially the same as those inFIG. 5are designated by the same reference signs, and a description thereof is omitted. InFIG. 7, S140a, S150a, S160a, and S170areplace S140, S150, S160, and S170inFIG. 5, respectively.

In S140a, the sequential interpreter11determines whether or not the amount of translated code at GC execution time has been recorded in the memory device103. If the amount of translated code at GC execution time has been recorded in the memory device103(that is, if GC has been executed) (Yes in S140a), the sequential interpreter11calculates the difference between the current amount of translated code in the code cache unit14and the amount of translated code at GC execution time (that is, the amount of translated code that has been obtained since the time of execution of GC) (S150a). The calculation result is assigned to a variable named after_gc_vol.

If the amount of translated code at GC execution time has not been recorded in the memory device103(that is, if GC has not been executed) (No in S140a), the sequential interpreter11assigns MAX_GC_VOL to the variable after_gc_vol (S160a). In the second embodiment, as described above, the threshold is effectively reduced until the amount of translation performed after the execution of GC has become a given value. The given value may be MAX_GC_VOL. MAX_GC_VOL is determined in advance, and is recorded in, for example, the auxiliary storage device102.

After S150aor S160ais completed, the sequential interpreter11determines whether or not the value represented by expression (2) below is greater than or equal to a threshold (S170a):
MAX_GC_VOL×number of executions/min(after—gc_vol,MAX_GC_VOL).  (2)

Expression (2) is obtained by replacing after_gc_time and MAX_GC_TIME in expression (1) in the first embodiment by after_gc_vol and MAX_GC_VOL, respectively. Therefore, if the amount of translated code that has been obtained since the time of execution of GC is less than MAX_GC_VOL, the threshold is effectively reduced, and the smaller the amount of translated code that has been obtained since the time of execution of GC, the greater the effective reduction to the threshold. If the amount of translated code that has been obtained since the time of execution of GC is greater than or equal to MAX_GC_VOL, the threshold is equal to the original value.

In the first and second embodiments, if the elapsed time after the GC execution time is less than MAX_GC_TIME or if the amount of translated code that has been obtained since the time of execution of GC is less than MAX_GC_VOL, the value represented by expression (1) or (2) may a fixed value. In this case, for example, the value after_gc_time in expression (1) or the value after_gc_vol in expression (2) may be given by MAX_GC_TIME/n or MAX_GC_VOL/n, where n>1. As a result, if the elapsed time after the GC execution time is less than MAX_GC_TIME or if the amount of translated code that has been obtained since the time of execution of GC is less than MAX_GC_VOL, the degree to which the threshold is reduced may be a given value.

In the first and second embodiments, furthermore, an example in which a threshold is reduced by overestimating the number of executions of an instruction over a given period of time has been described, but the threshold may be dynamically changed. For example, the threshold may be changed in accordance with the number of translation requests stored in the translation request queue12. In this case, the threshold used in S170or S170amay be calculated using, for example, the following expression (3).
Threshold=(number of translation requests stored in the translation request queue 12×constantA)+constantB(3)

The threshold may be calculated by applying, for example, constant A=1024 and constant B=1 to expression (3).

Next, a third embodiment will be described. The following description will be given for portions of the third embodiment different from those of the first embodiment. For other details not described here, reference may be made to the description of the first embodiment.

In the third embodiment, that an inconsistency may occur between translated code and a target program being executed Tp is taken into account. The occurrence of such an inconsistency is particularly apparent when the target program being executed Tp is a program for emulating a CPU with a different architecture from the CPU104. That is, the third embodiment is suitable when the target program being executed Tp, the sequential interpreter11, the code cache unit14, and the translated code remover15function as an emulator for emulating a CPU with a different architecture from the CPU104. However, the third embodiment may be applied in other cases.

An inconsistency in translated code occurs, for example, in a situation as illustrated inFIG. 8.FIG. 8is a diagram depicting an example situation where an inconsistency in translated code occurs.

InFIG. 8, an example of self modification is illustrated. An instruction P that is part of a target program being executed Tp may be dynamically altered or modified due to the execution of an instruction in the target program being executed Tp (sequential execution or execution using translated code that includes the instruction). Modification of an instruction in a program by the program itself when the program is being executed is referred to as “self modification”. InFIG. 8, translated code Cp that includes the instruction P, which has been modified, is different to the current state of the target program being executed Tp. Thus, an inconsistency has occurred in the translated code Cp.

Avoiding execution of the translated code Cp in which an inconsistency has occurred is desirable. Accordingly, the sequential interpreter11associates information indicating invalidity with the translated code Cp in which an inconsistency has occurred. In order to associate the information indicating invalidity, a management table14Tb according to the third embodiment has, for example, a configuration as illustrated inFIG. 9.

FIG. 9is a diagram illustrating an example configuration of the management table14Tb according to the third embodiment. InFIG. 9, the management table14Tb stores an invalidation flag in association with an address. The “invalidation flag” is information indicating whether or not translated code associated with the address is invalid. The initial value of the invalidation flag is “false”. If an inconsistency has occurred or could have occurred in the translated code, the value of the invalidation flag is updated to “true”. In this embodiment, the update of the invalidation flag to “true” for translated code is referred to as “invalidation of the translated code”.

If the value of the invalidation flag for a branch destination address is “true”, the sequential interpreter11sequentially executes each branch destination instruction corresponding to the branch destination address without regarding the translated code as code to be executed.

In this embodiment, the sequential interpreter11updates the invalidation flag. In order to detect an inconsistency occurring in a block of translated code, the sequential interpreter11or the translator13sets page table access privilege to “Read Only” for a page of the target program being executed Tp to which an instruction whose translated code has been generated belongs. That is, writing to the page of the target program being executed Tp to which an instruction whose translated code has been generated belongs is prohibited. Afterwards, if a page of the target program being executed Tp to which an instruction whose translated code has been generated belongs is to be self-modified by the execution of an instruction in the target program being executed Tp, an exception regarding access violation occurs. The sequential interpreter11detects the occurrence of the exception through a handler for handling (catching) the exception. Upon detection of the occurrence of the exception, the sequential interpreter11updates the invalidation flag in the management table14Tb to “true” for the one or more addresses associated with the translated code belonging to a page that includes the address notified with the exception.

An inconsistency in translated code may also occur in response to a desire to change mapping between virtual addresses and physical addresses such as when a new process is generated or when swapping has occurred. In response to the desire, the sequential interpreter11sets the invalidation flag for affected translated code to “true”.

Here, the relationship between invalidated translated code and GC, and translated code that has not been invalidated (effective translated code) and GC will be described. Invalidated translated code is undesirable translated code that is not usable later. Therefore, difficulties in performance caused by executing GC for the invalidated translated code may be relatively small. In contrast, effective translated code is translated code that is usable later or might be used later. Therefore, difficulties in performance caused by executing GC for the effective translated code may be relatively high.

In light of the above description, in the third embodiment, thresholds for the number of executions after the execution of GC may differ between invalidated translated code and effective translated code. Specifically, the threshold for effective translated code may be reduced to provide earlier recovery.

In order to realize the above control, an information processing apparatus10according to the third embodiment has, for example, a functional configuration as illustrated inFIG. 10.

FIG. 10is a diagram illustrating an example functional configuration of the information processing apparatus10according to the third embodiment. InFIG. 10, the information processing apparatus10further includes a forced removal flag storage unit16. The forced removal flag storage unit16may be implemented using; for example, the memory device103or the auxiliary storage device102.

The forced removal flag storage unit16stores information (hereinafter referred to as the “forced removal flag”) for identifying effective translated code that has been forced to be removed by the execution of GC. However, management of the forced removal flag for each piece of translated code leads to an increase in the amount of management information. In this embodiment, the forced removal flag is managed for each page of the target program being executed Tp.

FIG. 11is a diagram illustrating an example configuration of the forced removal flag storage unit16. As illustrated inFIG. 11, the forced removal flag storage unit16stores a forced removal flag for each page address. The page address is the start address of each page. Since the size of each page is given, a range of each page is specified based on the start address. The size of each page may not match the size of each page that is managed by an operating system (OS).

At the GC execution time, the value “false” is recorded in the forced removal flag for pages including translated code that had already been invalidated, and the value “true” is recorded in the forced removal flag for pages including only effective translated code. The forced removal flag is an example of information that indicates translated code whose instructions have not been updated in the target program being executed Tp after the generation of the translated code.

A processing procedure according to the third embodiment will now be described.FIG. 12is a flowchart depicting an example of a processing procedure for a process for executing GC according to the third embodiment.FIG. 12illustrates a process which is executed in a single GC run (that is, in one execution of S13inFIG. 3).

In S201, the translated code remover15initializes the values of the forced removal flag for all the page addresses in the forced removal flag storage unit16to “false”. Subsequently, the translated code remover15determines a group of translated code blocks to be removed (S202). The group of translated code blocks to be removed may be determined using an existing method. Some or all of all the translated code may be determined to be removed.

If a group of translated code blocks to be removed exists (Yes in S203), the translated code remover15sets one translated code block in the group of translated code blocks as a target to be processed (hereinafter referred to as the “target translated code block”) (S204). Subsequently, the translated code remover15refers to the invalidation flag in the management table14Tb for the record corresponding to the target translated code block, and determines whether or not the target translated code block has been invalidated (S205). That is, whether the invalidation flag is “true” or “false” is checked.

If the target translated code block has not been invalidated (No in S205), the translated code remover15determines the address of one or more pages to which the target translated code block belongs among the pages of the target program being executed Tp (S206). Subsequently, the translated code remover15updates the value of the forced removal flag in the forced removal flag storage unit16for the address of the one or more pages to “true” (S207). That is, information about the target translated code block, indicating that the instruction corresponding to the target translated code block has not been updated in the target program being executed Tp after the generation of the target translated code block, is recorded in the forced removal flag storage unit16. The term “update”, as used herein, refers to update made by, for example, self modification.

Subsequently, the translated code remover15removes data such as the target translated code block, and the record in the management table14Tb corresponding to the target translated code block from the code cache unit14(S208). If the target translated code block has been invalidated (Yes in S205), the target translated code block and the corresponding information are removed without updating the forced removal flag (S208).

Subsequently, the translated code remover15repeatedly performs S203and the subsequent processing thereof on all the translated code blocks belonging to the group of translated code blocks to be removed.

As a result of the process illustrated inFIG. 12, the forced removal flag storage unit16stores the value “true” for the page or pages including only effective translated code.

Next, a processing procedure of the sequential interpreter11according to the third embodiment will be described.FIG. 13is a flowchart depicting an example of the processing procedure of the sequential interpreter11according to the third embodiment. InFIG. 13, portions that are substantially the same as those inFIG. 5are designated by the same reference signs, and a description thereof is omitted. InFIGS. 13, S132and S133have been added.

In S132, the sequential interpreter11acquires from the forced removal flag storage unit16the value of the forced removal flag for a page that includes the branch destination address. If the acquired value of the forced removal flag is “true” (Yes in S133), S140and the subsequent processing thereof are executed. That is, the threshold is reduced over a given period of time after the execution of GC. If the acquired value of the forced removal flag is “false” (No in S133), S160and the subsequent processing thereof are executed. That is, the threshold may not be reduced.

Note that S140, S150, S160, and S170inFIG. 13may also be replaced by S140a, S150a, S160a, and S170ainFIG. 7, respectively. That is, as in the second embodiment, the given period of time after the execution of GC may be measured using the amount of translated code.

In the foregoing description, by way of example, the forced removal flag is managed for each page. Alternatively, the forced removal flag may be managed for each piece of translated code (for each branch destination address). In this case, the thresholds of invalidated translated code and effective translated code may be changed in more detail.

According to the third embodiment, therefore, the time of recovery for translated code that might be used after the execution of GC may be accelerated compared to that for translated code that might not be used. Thus, the period of time over which the low performance caused by the removal of translated code continues may be reduced.

Next, a fourth embodiment will be described. The following description will be given of portions of the fourth embodiment different from those of the first embodiment. For other details not described here, reference may be made to the description of the first embodiment.

FIG. 14is a diagram illustrating an example functional configuration of an information processing apparatus10according to the fourth embodiment. InFIG. 14, the information processing apparatus10includes two code cache units: a code cache unit14aand a code cache unit14b.

The code cache units14aand14bmay be implemented by dividing the code cache unit14according to the first embodiment into two sections, or may be two code cache units each corresponding to the code cache unit14according to the first embodiment.

A processing procedure according to the fourth embodiment will now be described.FIG. 15is a diagram illustrating an example of a processing procedure for an initialization process of a translated code remover15according to the fourth embodiment. The processing procedure illustrated inFIG. 15is executed when the translated code remover15is initially started for a single execution of the target program being executed Tp.

In S301, the translated code remover15records information indicating that the code cache unit14ais a current code cache in the memory device103. For example, the start address of the code cache unit14ais assigned to a variable for specifying the current code cache. The term “current code cache” is used to refer to a code cache unit being used.

FIG. 16is a flowchart depicting an example of a processing procedure for a process for executing. GC according to the fourth embodiment.FIG. 16illustrates a process executed in one GC run (that is, during one execution of S13inFIG. 3).

In S311, the translated code remover15records information indicating that the current code cache is the last code cache in the memory device103. For example, the value of a variable for specifying the current code cache is assigned to a variable for specifying the last code cache. The term “last code cache” is used to refer to a code cache unit that was last used.

Subsequently, the translated code remover15records information indicating that one of the code cache units14aand14bwhich is not the last code cache is the current code cache in the memory device103(S312). That is, in S311and S312, the current code cache and the last code cache are interchanged. Specifically, one of the code cache units14aand14bwhich has not been being used since the previous execution of GC is set as the code cache unit to use (that is, the current code cache).

Subsequently, the translated code remover15executes GC for the current code cache (S313).

For example, assume that the code cache unit14ais the current code cache at the time of the start of the processing procedure illustrated inFIG. 16. Since the code cache unit14ahas been used until the execution of GC, translated code, a management table14Ta, and any other suitable information has been recorded on the code cache unit14a.

Through the execution of S311and S312, the code cache unit14abecomes the last code cache, and the code cache unit14bbecomes the current code cache. Therefore, in S313, GC is performed on the code cache unit14b. Consequently, the content recorded on the code cache unit14ais saved (or stored).

In the fourth embodiment, therefore, the content recorded on the current code cache is saved until GC is executed.

FIG. 17is a flowchart depicting an example of a processing procedure of a translator13according to the fourth embodiment. InFIG. 17, portions that are substantially the same as those inFIG. 3(i.e., S6and S7) are designated by the same reference signs, and a description thereof is omitted.

InFIG. 17, S8ais executed instead of S8. In S8a, the translator13stores the generated translated code in the current code cache. In the management table14Ta of the current code cache, the translator13further updates the value of the translated/untranslated flag corresponding to an address specified in the translation request to “true”, and records an address at which the translated code is stored in the translated code address corresponding to the address specified in the translation request.

FIG. 18is a flowchart depicting an example of a processing procedure of a sequential interpreter11according to the fourth embodiment. InFIG. 18, portions that are substantially the same as those inFIG. 5are designated by the same reference signs, and a description thereof is omitted. InFIG. 13, S110areplaces S110inFIG. 5and S131has been added.

In S110a, the sequential interpreter11refers to the management table14Ta in the current code cache, and determines whether or not translated code for a branch destination address exists.

In S131, the sequential interpreter11refers to the management table14Ta in the last code cache, and determines whether or not translated code for the branch destination address exists. If translated code for the branch destination address exists in the last code cache (Yes in S131), S140and the subsequent processing thereof are executed. That is, the threshold is reduced over a given period of time after the execution of GC. If the translated code for the branch destination address does not exist in the last code cache (No in S131), S160and the subsequent processing thereof are executed. That is, the threshold may not be reduced.

Note that S140, S150, S160, and S170inFIG. 18may be replaced by S140a, S150a, S160a, and S170ainFIG. 7, respectively. That is, as in the second embodiment, the given period of time after the execution of GC may be measured using the amount of translated code.

In the foregoing description, an example was depicted of saving the current code cache's content by interchanging the code cache unit14aand14bwith respect to the current code cache and the last code cache. Instead, the code cache unit14amay be set to always be the target of use (that is, the current code cache). In this case, a process for copying the content in the code cache unit14ato the code cache unit14bmay be executed instead of S311and S312inFIG. 16. Consequently, the content in the code cache unit14abefore the execution of GC may be saved. Not saving the entirety of the content stored in the current code cache is acceptable. Information capable of identifying a group of instructions for which translated code has been generated may be saved. In this embodiment, the value of the addresses in the management table14Ta may be saved.

According to the fourth embodiment, therefore, the threshold of a group of instructions for which translated code has previously been generated may be reduced. Thus, the group of instructions may be preferentially translated. A group of instructions for which translated code has previously been generated may tend to have a high frequency of execution. Accelerated re-generation of translated code for the group of instructions may reduce the period of time during which there is low performance caused by the removal of translated code.

In addition, an increase in the amount of translated code may be restrained compared to the case where thresholds of all the groups of instructions are uniformly reduced.

In S131, whether or not the number of executions for a branch destination address is greater than or equal to a threshold a instead of whether or not translated code for the branch destination address exists may be determined. If the number of executions for the branch destination address is greater than or equal to the threshold α, S140and the subsequent processing thereof may be executed. If the number of executions for the branch destination address is less than the threshold α, S160and the subsequent processing thereof may be executed. Therefore, the range of instructions to be translated may be limited to a group of instructions with a higher frequency of execution. In this case, a value representing the number of executions for the translated code corresponding to the branch destination address, in addition to the value of the address in the management table14Ta, may be saved. The threshold a may or may not be the same as the threshold used in S170.

Next, a fifth embodiment will be described. The fifth embodiment is a combination of the third embodiment and the fourth embodiment. A sequential interpreter11according to the fifth embodiment executes a process illustrated inFIG. 19.

FIG. 19is a flowchart depicting an example of a processing procedure of the sequential interpreter11according to the fifth embodiment. In the processing procedure illustrated inFIG. 19, S132and S133fromFIG. 16are added after S131fromFIG. 18. The processing procedure illustrated inFIG. 19may be anticipated from the description with reference toFIGS. 16 and 18and any other suitable figure, and a description thereof is thus omitted.

According to the fifth embodiment, the advantages of both the third and fourth embodiments may be achieved.

In the foregoing embodiments, the translator13is an example of a generator. The translated code remover15is an example of a remover. The code cache unit14is an example of a first storage unit. The forced removal flag storage unit16is an example of a second storage unit.

While several embodiments have been described in detail, embodiments are not limited to the foregoing specific embodiments, and a variety of modifications and changes may be made within the scope of the disclosure as defined in the claims.