Voltage drive system with hysteretic current control and method of operating the same

A voltage drive system is provided having a plurality of modulators and a plurality of cascaded switching circuits which collectively generate a single-phase output signal to a load. Each modulator receives a phase current error and has an adder which generates a modulated phase current error based on the phase current error and based on a signal having a phase. For each respective modulator, the phase of the respective signal is different. Each respective modulator changes a respective gate input when the respective modulated phase current error changes from being within a predetermined current range to being outside of the predetermined current range. Each respective switching circuit receives the respective gate input and generates a respective output terminal voltage based on the respective gate input. The change in the respective gate input effectively causes a switching event of the respective switching circuit.

FIELD OF INVENTION

*The present invention generally relates to a voltage drive system. More particularly, the present invention relates to a voltage drive system employing an improved hysteretic current control technique.

Typically, variable frequency voltage drive systems are used to control variable speed, medium voltage motors to drive systems requiring 5 MW to 75 MW of power. These conventional voltage drive systems usually operate at medium voltages of 1.5 kV to 13.2 kV, as operation at low voltages leads to excessive currents and losses. While these drives can be manufactured using high voltage devices, the selection and availability of such devices is limited and they are severely lacking in switching speed. This limitation is significant, as the switching frequency determines the bandwidth of the voltage drive system, which in turn dictates the output waveform quality.

Certain conventional medium voltage drive systems (such as depicted inFIGS. 1-3) employ lower voltage devices with specialized connections between the devices. The low voltage devices in these conventional voltage drive systems (e.g.,100inFIG. 1) are typically “H-bridges” (such as the H-bridge200shown inFIG. 2) that can be switched at faster rates, yielding an improvement in output waveform quality. However, the conventional voltage drive systems100typically employ a deterministic controller (e.g.,120inFIG. 1) that switches the H-bridges at constant or regular time intervals based on a reference voltage input, resulting in a fixed switching rate regardless of the slew rate of the reference voltage input to the deterministic controller.

Conventional voltage drive systems100that employ a deterministic controller120to switch H-bridges in order to drive a three-phase load101will now be explained in further detail to illustrate the fixed switching rate problem and other problems with these conventional voltage drives. As shown inFIG. 1, a conventional voltage drive system100employing H-bridges106A1-106An,106B1-106Bn, and106C1-106Cnand a deterministic controller120to control the switching of the H-bridges also typically include an input transformer102; phase output lines104A,104B, and104C; current feedback circuits108A,108B, and108C; an ac filter110; a speed or voltage control loop circuit114; a torque/flux controller116; and a current regulator118. The input transformer102includes a primary winding circuit122and secondary winding circuits124A1-124An,124B1-124Bn, and124C1-124Cn. Each of the phase output lines104A,104B, and104C are coupled to and driven by a respective number (n) of cascaded H-bridges106A1-106An,106B1-106Bn, and106C1-106Cn. The output of each of the respective secondary winding circuits124A1-124An,124B1-124Bn, and124C1-124Cnis fed to a respective one of the H-bridges106A1-106An,106B1-106Bn, and106C1-106Cn(each of which is configured consistent with the H-bridge200inFIG. 2) as one of three single-phase power inputs202a-202c.

A typical H-bridge200employed in conventional voltage drive systems100is shown inFIG. 2. The H-bridge200receives the three single-phase power inputs202a-202c, which are rectified (via a rectifier204) to produce a dc supply voltage that is then filtered by the capacitor206. The filtered dc supply voltage serves as the supply voltage for the four power switches208a-208d. Each of the power switches208a-208dhas a respective gate210a-210dthat is controlled by the deterministic controller120of the conventional voltage drive system100.

Returning toFIG. 1, the gate inputs to the four gates210a-210dof each H-bridge106A1-106An,106B1-106Bn, and106C1-106Cnare generated by the deterministic controller120using the limited fixed switching rate as further described below. First, the speed or voltage control loop circuit114generates a dc torque command and a dc flux command that are fed to the torque/flux regulator116. The torque/flux regulator116then synthesizes current commands in the d, q reference frame based on the torque and flux commands. The current commands are input to the current regulator118. The current regulator118also receives current feedback signals126a,126b, and126cgenerated by current feedback circuits108A,108B, and108C based on a respective phase output line104A,104B, and104C. The current regulator118generates phase voltage references128a,128b, and128cin the a, b, c reference frame based on the d, q current commands and the current feedback signals. The phase voltage references128a,128b, and128care typically sinusoidally varying at the desired output electrical frequency of the conventional voltage drive system100.

The phase voltage references128a,128b, and128care input to the deterministic controller120. In response to the phase voltage references128a,128b, and128c, the deterministic controller120generates a plurality of sets of four gate inputs130a1-130an,130b1-130bn, and130c1-130cnto the H-bridges106A1-106An,106B1-106Bn, and106C1-106Cn. As shown inFIG. 2, depending on which of the four power switches108a-108dare gated active by the deterministic controller120, the voltage between the output terminals212and214(also referred to herein as the output terminal voltage) of the respective H-bridge106A1-106An,106B1-106Bn, and106C1-106Cnmay be either the supply voltage used to the power the power switches108a-108d, the negative of the supply voltage, or zero.

Each group of the H-bridges106A1-106An,106B1-106Bn, and106C1-106Cnare cascaded; that is, their output terminals (e.g.,112and114inFIG. 2) are electrically connected, such that the respective H-bridges106A1-106An,106B1-106Bn, and106C1-106Cnin each group collectively generate a single-phase output signal on the respective phase output lines104A,104B, and104C. The H-bridges106A1-106An,106B1-106Bn, and106C1-106Cnare cascaded such that the voltages of the respective single-phase output signals are equal to the sum of the voltages between the output terminals212and214of the respective H-bridges106A1-106An,106B1-106Bn, and106C1-106Cn. Thus, the timing of the gating of the H-bridge power switches by the deterministic controller120employed in conventional voltage drive systems100is important for synthesizing an output waveform at various frequencies.

The deterministic controller120typically employed in the conventional voltage drive system100implements a pulse width modulation (“PWM”) technique in order to gate the four power switches108a-108dof each H-bridge and control the voltages of the single-phase output signals generated by the H-bridge. More specifically, the deterministic controller120selectively switches the gate inputs130a1-130an,130b1-130bn, and130c1-130cnthat are fed to the gates210a-210dof each of the H-bridges106A1-106An,106B1-106Bn, and106C1-106Cnin order to cause a corresponding switching event for one or more of the power switches108a-108din each gated H-bridge106A1-106An,106B1-106Bn, and106C1-106Cn. These switching events, in turn, cause the voltages between the output terminals212and214of the H-bridges106A1-106An,106B1-106Bn, and106C1-106Cnto change to a corresponding state (e.g., +supply voltage, −supply voltage, or zero voltage).

In order to provide acceptably low distortion output waveforms, the voltage waveforms of the single-phase output signals should be switched at a PWM frequency of 60 times the desired output frequency. To achieve this result, the gate inputs130a1-130an,130b1-130bn, and130c1-130cnto the H-bridges106A1-106An,106B1-106Bn, and106C1-106Cncoupled to the respective phase output lines104A,104B, and104C may be switched at differing times. This temporal shifting of the switching instances causes the effective switching rates of the respective single-phase output signals to be multiplied by 2·n, or twice the number of H-bridges in each of the cascades. For example, low voltage H-bridges in commercially available conventional voltage drive systems100are typically switched at about 600 Hz. If a four-H-bridge cascade is used in each phase output line104A,104B,104C, and if the four H-bridges in each cascade are all switched at differing times, the effective switching rate of each single-phase output signal will be eight times the individual H-bridge switching rate, or approximately 4800 Hz. This value is approximately 80 times the fundamental frequency of 60 Hz of the output waveform (and, thus, the frequency of phase voltage references128a,128b, and128c) required to drive a standard speed motor drive in a typical application. Hence, the conventional voltage drive system100may provide low distortion output waveforms (i.e., on the phase output lines104A,104B and104C) at high switch rates when the fundamental frequency of the phase voltage references128a,128b, and128cto the deterministic controller120is at 60 Hz or lower. However, the conventional deterministic controller120causes significant distortion of the output waveforms when the fundamental frequency of the output waveform to be synthesized and the corresponding frequency phase voltage references128a,128b, and128cis significantly higher than 60 Hz, such as a fundamental frequency of 600 Hz. This problem with conventional voltage drive systems100employing a deterministic controller120is discussed in further detail below.

As previously noted, the deterministic controller120typically employed in conventional voltage drive systems100switches the gate inputs130a1-130an,130b1-130bn, and130c1-130cnthat are fed to the power switches of each H-bridge106A1-106An,106B1-106Bn, and106C1-106Cnat regular time intervals such that all pulses of the voltage waveforms of the single-phase output signals occur at regular time intervals. For example, one conventional system disclosed in U.S. Pat. No. 5,625,545 to Hammond is based on well-known sine-triangle modulation, in which a sinusoidal modulating waveform is compared to a triangular carrier waveform to generate H-bridge gate inputs. An example of such deterministic control is shown inFIG. 3, which illustrates a block diagram of the deterministic controller120as typically used in conventional voltage drive systems200. The components of the deterministic controller120that correspond to each of the phase output lines104A,104B, and104C are the same, and for simplicity and brevity in the discussion, only those components corresponding to the phase output line104A and used to generate the gate inputs130a1-130anto control the H-bridges106A1-106Anare described. Two duplicate sets of components corresponding to the phase output lines104B and104C may be employed in a similar manner in the deterministic controller120to generate the gate inputs130b1-130bnand130c1-130cn, respectively, to control the H-bridges106B1-106Bnand106C1-106Cn, respectively.

InFIG. 3, the phase voltage reference128afrom the current regulator118is input to each of n modulators3021-302n. An inverse phase voltage reference332a, which is generated by an inverter304, is also input to each of the n modulators3021-302n. In each of the n modulators3021-302n, signal generators3061-306ngenerate zero-average triangular signals3071-307nhaving the same amplitude and frequency as the waveform of the phase voltage reference128a. The triangular signals3071-307nare phase-shifted from one another by 180/n degrees so that the gate inputs130a1-130anthat are generated cause the H-bridges106A1-106Anin the phase output line104A,104B, or104C to switch at differing times. Adders3081-308nsubtract the triangular signals3071-307nfrom the phase voltage reference128a, and adders3101-310nsubtract the triangular signals3071-307nfrom the inverse phase voltage reference332a.

The differences3091-309nfrom adders3081-308nare input to comparators3121-312nand the differences3111-311nfrom adders3101-310nare input to comparators3141-314n. Each of comparators3121-312nand3141-314noutputs a positive voltage if the input it receives exceeds zero volts and a negative voltage if the input it receives is less than zero volts. The output voltage from each of comparators3121-312nand3141-314nis used to generate two gate inputs of a respective one of the plurality of sets of four gate inputs130a1-1-130an-4and130a1-1-130an-4; one gate input is equal to the comparator output voltage, and the second gate input is the inverse of the comparator output voltage as generated by one of inverters3161-316nand3181-318n. The four gate inputs130a1-130angenerated by each of the modulators3021-302nis input to a respective one of the H-bridges106A1-106Anas shown inFIG. 1. Because the gate inputs130a1-130anvary in time solely based on a comparison of the phase voltage reference128aor inverse phase voltage reference332ato a triangular signal3071-307n, they switch at regular time intervals. Thus, the voltages of the single-phase output signals generated by the cascaded H-bridges106A1-106Anare also switched or pulsed at regular time intervals.

A major shortcoming of such deterministic control is apparent when the conventional voltage drive system100is used to synthesize waveforms having high frequencies, such as 600 Hz. In order to switch the voltage waveform of the single-phase output signal at a PWM frequency of 60 times the desired output frequency, the effective switching rate of the single-phase output signal needs to be 36 kHz. Thus, each of the H-bridges106A1-106An,106B1-106Bn, or106C1-106Cnconnected to the phase output line104A,104B, or104C is required to be switched at one-eighth that frequency, or 4.5 kHz. Switching the H-bridges106A1-106An,106B1-106Bn, or106C1-106Cnat this rate is difficult because high switching losses are introduced. These switching losses are particularly pronounced when current flow through the H-bridges106A1-106An,106B1-106Bn, or106C1-106Cnis highest, which occurs at times corresponding to the peaks of the voltage waveform of the single-phase output signal generated by the cascaded H-bridges.

Moreover, as a result of a fixed switching rate, the output waveform generated by cascaded H-bridges106A1-106An,106B1-106Bn, or106C1-106Cncontrolled by the deterministic controller120has significant distortion at times corresponding to the high slew rate portions and low slew rate portions of the waveform of the phase voltage reference128a,128b, or128csupplied to the deterministic controller120. This distortion occurs because the fixed switching rate is too low at the high slew rate portions of the waveform of the phase voltage reference128a,128b, or128cand too high at the low slew rate portions of the waveform of the phase voltage reference128a,128b, or128c. The distortion at these respective times can be observed at the zero crossings and peaks, respectively, of the output waveform generated by cascaded H-bridges106A1-106An,106B1-106Bn, or106C1-106Cn.

FIG. 4illustrates a voltage waveform400of a single-phase output signal synthesized by a conventional voltage drive system (e.g.,100inFIG. 2) using a deterministic controller (e.g.,120inFIG. 2) as described above to switch the H-bridges106A1-106An,106B1-106Bn, and106C1-106Cnat constant intervals or fixed rates. The voltage waveform400suffers from an unduly high amount of distortion near both its zero crossings and its peaks. Furthermore, known voltage drive systems employing the above-described deterministic control produce clearly defined tones at multiples of the fixed H-bridge switching frequency in the spectra (not shown) of the voltage and current of the single-phase output signals generated by the cascaded H-bridges106A1-106An,106B1-106Bn, or106C1-106Cn. These tones often result in undesirable noise in applications where stringent acoustic specifications need to be met.

One possible method to improve the quality of the voltage waveform400involves increasing the switching frequency of the H-bridges106A1-106An,106B1-106Bn, and106C1-106Cnin an open-loop fashion at times corresponding to the high slew rate portions of the voltage waveform of the single-phase output signal. However, such open-loop incrementing of the switching frequency can introduce discontinuities and non-linearities in the single-phase output signal of the respective group of cascaded H-bridges.

Another conventional system disclosed in U.S. Pat. No. 5,933,339 to Duba et al. includes the injection of harmonic and non-harmonic content into the waveform of a phase voltage reference in order to vary the H-bridge switching rate at particular times and reduce the clearly defined tones in the spectrum of the output voltage and current. Injection of harmonic and non-harmonic components into the reference waveform could be construed as a type of non-deterministic modulation. However, the resulting switching pattern is fundamentally deterministic since the injected components are generated from within the control itself and are not a product of external events related to instantaneous source and/or load conditions.

Therefore, there is a need for a medium voltage drive system that overcomes the problems noted above and others previously experienced for synthesizing medium voltage phased output signals using H-bridges or other switched low voltage devices.

SUMMARY OF INVENTION

Systems and articles of manufacture consistent with the present invention provide a voltage drive system having a single-phase output signal to drive a load, such as a variable speed motor. The voltage drive system comprises a plurality of modulators and a plurality of switching circuits. A first of the modulators includes a first signal generator and a first adder. The first modulator receives a phase current error that reflects on a difference between a current reference and a current value of the single-phase output signal, and generates a first gate input based on the phase current error. The first switching circuit receives the first gate input and generates a first output terminal voltage based on the first gate input. The first signal generator generates a first reference signal having a first phase. The first adder receives the phase current error and the first reference signal and generates a first modulated phase current error based on the regulated phase current error and the first reference signal. The first modulator changes the first gate input from a first voltage level to a second voltage level to effectively cause a first switching event of the first switching circuit when the first modulated phase current error changes from being within a predetermined current range to being outside of the predetermined current range. A second of the modulators includes a second signal generator and a second adder. The second modulator receives the regulated phase current error and generates a second gate input. A second of the switching circuits receives the second gate input and generates a second output terminal voltage based on the second gate input. The second signal generator generates a second reference signal having a second phase different from the first phase of the first reference signal. The second adder receives the regulated phase current error and the second reference signal and generates a second modulated phase current error based on the regulated phase current error and the second reference signal. The second modulator changes the second gate input from a third voltage level to a fourth voltage level to effectively cause a second switching event of the second switching circuit when the second modulated current changes from being within the predetermined current range to being outside of the predetermined current range. The first reference signal and the second reference signal are generated such that the first switching event and the second switching event are separated by a time interval. The switching circuits are cascaded such that the switching circuits of the switching circuits collectively generate the single-phase output signal to the load. A voltage of the single-phase output signal is equal to a sum of an output terminal voltage of each of the plurality of switching circuits.

Systems and articles of manufacture consistent with the present invention provide another voltage drive system having a single-phase output signal to drive a load. The voltage drive system comprises a multi-level comparator, a decoder, and a plurality of switching circuits. The multi-level comparator receives a phase current error and generates a drive-state output corresponding to one of a plurality of predetermined voltage levels. The phase current error is based on a difference between a current reference and a current value of the single-phase output signal. The multi-level comparator changes the drive-state output to effectively cause a first switching event of the plurality of switching circuits when the phase current error changes from being within a first predetermined current range to being outside of the first predetermined current range. The multi-level comparator changes the drive-state output to effectively cause a second switching event of the plurality of switching circuits when the phase current error changes from being within a second predetermined current range to being outside of the second predetermined current range. The decoder receives the drive-state output and generates a plurality of gate inputs based on the drive-state output. Each of the plurality of switching circuits receives a respective one of the gate inputs and generates a respective output terminal voltage based on the respective one gate input. The switching circuits are cascaded such that the switching circuits collectively generate the single-phase output signal to the load. A voltage of the single-phase output signal is equal to a sum of the respective output terminal voltages of the plurality of switching circuits.

The present invention also provides a method in a voltage drive system for controlling a plurality of switching circuits to generate a single-phase output signal to drive a load. The method includes receiving a phase current error. The phase current error is based on a difference between a current reference and a current value of the single-phase output signal. The method further includes generating a first modulated phase current error based on the phase current error and a first reference signal having a first phase. The method further includes generating a second modulated phase current error based on the phase current error and a second reference signal having a second phase different from the first phase of the first reference signal. The method further includes changing a first gate input from a first voltage level to a second voltage level when the first modulated phase current error changes from being within a predetermined current range to being outside of the predetermined current range. The method further includes changing a second gate input from a third voltage level to a fourth voltage level when the second modulated phase current error changes from being within the predetermined current range to being outside of the predetermined current range. The method further includes providing the first gate input and the second gate input to a plurality of switching circuits. Changing the first gate input effectively causes a first switching event of a first of the switching circuits. Changing the second gate input effectively causes a second switching event of a second of the switching circuits. The first reference signal and the second reference signal are such that the first switching event and the second switching event are separated by a time interval. The method further includes generating an output terminal voltage of each of the plurality of switching circuits. The plurality of switching circuits is cascaded such that the switching circuits of the plurality of switching circuits collectively generate the single-phase output signal to the load. A voltage of the single-phase output signal is equal to a sum of an output terminal voltage of each of the plurality of switching circuits.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to implementations in accordance with methods, systems, and products consistent with the present invention as illustrated in the accompanying drawings.

FIG. 5illustrates a block diagram of an exemplary voltage drive system500consistent with the present invention. In the implementation shown inFIG. 5, the voltage drive system500is depicted as driving a three-phase load101. For example, the three-phase load101may be a medium voltage pulse modulated, induction, or synchronous motor requiring three phase, alternate current at variable frequency to control the speed of the motor. However, as described in detail herein, voltage drive systems500and900consistent with the present invention may be configured to generate one or more single-phase output signals to control or drive a motor or other load.

The voltage drive system500includes phase output lines502A,502B, and502C (which respectively represent Phase A, Phase B, and Phase C single-phase output signals); a hysteretic non-deterministic controller504(hereinafter “the hysteretic controller”); current feedback circuits506A,506B, and506C; and a plurality of cascaded groups of H-bridges508A1-508An,508B1-508Bn, and508C1-508Cn. The voltage drive system500may also include an input transformer102; an ac filter509to filter the one or more single-phase output signals generated on phase output lines502A,502B, and502C in accordance with the present invention; a speed or voltage control loop circuit510; and a torque/flux controller512. As discussed in detail below, the hysteretic controller504employed in the voltage drive system500enables the switching rates of H-bridges508A1-508An,508B1-508Bn, and508C1-508Cnto be increased at times corresponding to the zero crossings of the voltage waveforms of the single-phase output signals and decreased at times corresponding to the peaks of the voltage waveforms of the single-phase output signals generated by the respective cascaded groups of H-bridges508A1-508An,508B1-508Bn, and508C1-508Cnon respective phase output lines502A,502B and502C.

The input transformer102may include a primary winding circuit122and secondary winding circuits124A1-124An,124B1-124Bn, and124C1-124Cn. In operation, three-phase ac input power is supplied to the primary winding circuit122of input transformer102. The primary winding circuit122may be arranged in either a wye or delta configuration. The primary winding circuit122energizes each of the secondary winding circuits124A1-124An,124B1-124Bn, and124C1-124Cn. Each of the secondary winding circuits124A1-124An,124B1-124Bn, and124C1-124Cnmay also be arranged in either a wye or delta configuration. In one implementation, the secondary winding circuits124A1-124Anare phase-shifted from the secondary winding circuits124B1-124Bn, which are in turn phase-shifted from the secondary winding circuits124C1-124Cn, in order to improve the quality of the waveforms delivered by the secondary winding circuits124A1-124An,124B1-124Bn, and124C1-124Cnand distribute power to the H-bridges508A1-508An,508B1-508Bn, and508C1-508Cn. In the implementation shown inFIG. 5, the output of each of the respective secondary winding circuits124A1-124An,124B1-124Bn, and124C1-124Cnprovides three single-phase power inputs to a respective one of the H-bridges508A1-508An,508B1-508Bn, and508C1-508Cn.

Alternatively, three-phase active rectifier front ends (not shown in the figures) can be used to achieve regeneration and control of the harmonics in the waveforms delivered by the secondary winding circuits124A1-124An,124B1-124Bn, and124C1-124Cn, thereby eliminating the need for phase shifting the secondary winding circuits124A1-124An,124B1-124Bn, and124C1-124Cnin the manner described above. Isolated dc power supplies (not shown in the figures) may also be used in place of the input transformer102, with no requirement of phase shifting.

Each of the phase output lines502A,502B, and502C are coupled to and driven by a respective number (n) of cascaded switching circuits. In the implementation shown inFIG. 5, the switching circuits are H-bridges, and the respective phase output lines502A,502B, and502C are coupled to and driven by a respective number (n) of cascaded H-bridges508A1-508An,508B1-508Bn, and508C1-508Cn. In this implementation, the phase output line502A is coupled to a first H-bridge508A1and each subsequent H-bridge (e.g., a second H-bridge508A2or last H-Bridge508An) is cascaded with the previous H-Bridge (e.g., the second H-bridge508A2is cascaded with the first H-bridge508A1and the last H-bridge508Anis cascaded with the second H-bridge508A2). The phase output lines502B and502C are similarly coupled to a respective first H-bridge508B1or508C1, a second H-bridge508Bnor508Cncascaded with the first H-bridge508B1or508C1and a next H-bridge508Bnor508Cncascaded with the second H-bridge508B2or508C2

In one implementation in which each H-bridges508A1-508An,508B1-508Bn, and508C1-508Cnis implemented consistent with H-bridges200, the output terminals212and214of the H-bridges508A1-508Anare electrically connected in a “daisy-chained” manner such that output terminal214of a first H-bridge508A1is electrically connected to output terminal212of the second H-bridge508A1, the output terminal214of the second H-bridge508A2is electrically connected to the output terminal212of the next or last H-bridge508An. H-bridges106B1-106Bnand106C1-106Cnmay be cascaded in the same manner. In this implementation, the output terminal214of the last H-bridge508An,508Bnand508Cnof each cascaded group of H-bridges508A1-508An,508B1-508Bn, and508C1-508Cnare joined by a WYE connection to form a floating neutral point514.

As shown inFIG. 5, the voltage drive system500does not require a current regulator118as employed in conventional voltage drive systems100because the hysteretic controller504operates directly on phase current references, and not on phase voltage references. The hysteretic controller504receives, from the torque/flux controller512, phase current references518a,518b, and518ccorresponding to each of the single-phase output signals to be generated on a respective phase output line502A,502B, and502C. The phase current references518a,518b, and518cmay be provided in the standard A, B, C reference frame. It is preferable to keep the phase current references in the A, B, C reference frame because converting to the d, q reference frame introduces latencies and delays. Additionally, current feedback circuits506A,506B, and506C generate phase current feedbacks520a,520b, and520cin the A, B, C reference frame, and not the d, q reference frame. Each current feedback circuit506A,506B, and506C is configured to generate a respective phase current feedback520a,520b, or520cbased on the value of the current of the single-phase output signal present on the respective phase output line502A,502B, or502C as driven by the respective group of cascaded H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn. In one implementation, the waveform of each phase current feedback520a,520b, and520chas an amplitude equal to that of a corresponding one of the phase current references518a,518b, and518c. The phase current feedbacks520a-520care input to the hysteretic controller504.

In one implementation, each of the H-bridges508A1-508An,508B1-508Bn, and508C1-508Cnmay be implemented consistent with the H-bridge200. In this implementation, each of the H-bridges508A1-508An,508B1-508Bn, and508C1-508Cnreceives, from the hysteretic controller504, a respective one set of a plurality of sets of four gate inputs522a1-522an,522b1-522bn, and522c1-522cnand generates a voltage between the respective H-bridge's output terminals212and214based on the four gate inputs (e.g.,522a1) that are received by the respective H-bridge (e.g.,508A1) from the hysteretic controller504. In one implementation, for each of the H-bridges508A1-508An,508B1-508Bn, and508C1-508Cn, if power switches108aand108dof the respective H-bridge are active, the voltage between the output terminals212and214of the respective H-bridge will be the supply voltage used to power the power switches108a-108d. If power switches108band108care active, the voltage between the output terminals212and214of the respective H-bridge will be the negative of the supply voltage. If power switches108aand108care active, or if power switches108band108dare active, the voltage between the output terminals212and214of the H-bridge will be zero volts.

The power switches may be bipolar junction transistors, metal-oxide-semiconductor field effect transistors, insulated-gate bipolar transistors, integrated gate commutated thyristors, or any suitable type of power switch.

The H-bridges508A1-508An,508B1-508Bn, and508C1-508Cnare cascaded; that is, their output terminals are electrically connected, such that the respective H-bridges508A1-508An,508B1-508Bn, and508C1-508Cncollectively generate the respective single-phase output signals on the respective phase output lines502A,502B, and502C. More particularly, the groups of H-bridges508A1-508An,508B1-508Bn, and508C1-508Cnare cascaded such that the voltage of the respective single-phase output signal collectively generated by the respective group of H-bridges are equal to the sums of the voltages between the output terminals212and214of the each H-bridge in the cascaded group of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn. In one implementation, the H-bridges508A1-508An,508B1-508Bn, and508C1-508Cnmay be cascaded in the same manner as the H-bridges106A1-106An,106B1-106Bn, and106C1-106CninFIG. 1. In the implementation shown inFIG. 5, the three single-phase output signals generated by the H-bridges508A1-508An,508B1-508Bn, and508C1-508Cnpresent on the phase output lines502A,502B, and502C are used to drive the three-phase load101.

The hysteretic controller504controls the operation of the voltage drive system500.FIG. 6illustrates a block diagram of one implementation of the hysteretic controller504. The components of the hysteretic controller504shown inFIG. 6correspond to the components for controlling one group of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnto generate a single-phase output signal on a corresponding one of the phase output lines502A,502B, or502C in accordance with the present invention. However, two duplicate sets of components as shown inFIG. 6may be employed in the hysteretic controller504to control the other two groups of H-bridges in a similar manner. Therefore, for simplicity and brevity in the discussion, only those components corresponding to one group of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnand one of the phase output lines502A,502B, or502C are shown and described herein.

For each phase output line502A,502B, and502C, the hysteretic controller504includes a first adder602, a proportional integral current regulator604, a first inverter606, and one or more hysteretic modulators6081-608n(e.g., first hysteretic modulator6081and second hysteretic modulator608n). Each hysteretic modulator6081-608nincludes a second adder6101-620n, a third adder6121-612n, a first hysteretic comparator6141-614n, a second hysteretic comparator6161-616n, a signal generator6181-618n, a second inverter6201-620n, and a third inverter6221-622n.

As shown inFIG. 6, the output of the first adder602is electrically coupled to the input of the proportional integral current regulator604. The output of the proportional integral current regulator604is electrically coupled to the input of the first inverter606and an input of each of the hysteretic modulators6081-608n. Within each of the hysteretic modulators6081-608n, the output of the respective signal generators6181-618nare electrically coupled to an input of the respective second adders6101-610nand an input of the respective third adders6121-612n. The output of the second adder6101or610nemployed in each hysteretic modulator is electrically coupled to the input of the respective first hysteretic comparator6141or614n. The output of the third adder6121or612nemployed in each hysteretic modulator is electrically coupled to the input of the respective second hysteretic comparator6161or616n. The output of the first hysteretic comparator6141or614nemployed in each hysteretic modulator6081-608nis electrically coupled to a corresponding second inverter6201or620n. Similarly, the output of the second hysteretic comparator6161or616nemployed in each hysteretic modulator6081-608nis electrically coupled to a corresponding third inverter6221or622n.

With continued reference toFIG. 6, the operation of the hysteretic controller504will be described in further detail. For each phase output line502A,502B, and502C, the first adder602receives as input a respective one of the phase current references518a,518b, and518c(e.g.,518ais shown as input to the adder602inFIG. 6) from the torque/flux controller512and a respective one of the phase current feedbacks520a,520b, and520cfrom a respective one of the current feedback circuits506A,506B, and506C. The first adder602generates and outputs to the proportional integral current regulator604a phase current error603corresponding to a difference between the phase current reference518a,518b, or518cand the corresponding phase current feedback520a,520b, or520c(e.g.,520ais as input to the adder602inFIG. 6). The output605of the proportional integral current regulator604is based on and proportional to the phase current error603. The output605of the proportional integral current regulator604will be referred to herein as a regulated phase current error605. In one implementation, the proportional integral current regulator604may be omitted. In this implementation, the phase current error603output by the first adder602would be the regulated phase current error.

The first inverter606generates an inverse607of the regulated phase current error605. The regulated phase current error605and the inverse regulated phase current error607are input to each of the hysteretic modulators6081-608n.

Each of the hysteretic modulators6081-608nreceives the regulated phase current error605and the inverse regulated phase current error607and generates a respective one of the plurality of sets of four gate inputs522a1-1-522a1-4. . .522aN-1-522an-4,522b1-1-522b1-4. . .522bN-1-522bn-4, or522c1-1-522c1-4. . .522cN-1-522cn-4to drive a respective one of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnas discussed in further detail herein. The regulated phase current error605and the inverse regulated phase current error607are each modulated via the second adders6101-610nand the third adders6121-612n, respectively, and via zero-average reference signals (e.g., triangular waveform signals)6191-619ngenerated by each of the signal generators6181-618n, to generate currents which will be collectively referred to herein as modulated phase current errors6111-611n, as shown inFIG. 6. For example, a first modulated phase current error6111is generated in the first hysteretic modulator6081and a second modulated phase current error611nis generated in the second hysteretic modulator608n. In the implementation shown inFIG. 6, the second adder6101-610nemployed in each hysteretic modulator6081-608nreceives the regulated phase current error605(or the phase current error603if the proportional integral current regulator604is omitted) and a respective reference or triangular signal6191or619nfrom the signal generator6181or618nand generates a respective modulated phase current error6111or611nbased on a difference between the regulated phase current error605and the respective reference or triangular signal6191or619n.

The third adder6121-612nof each hysteretic modulator6081-608nreceives the inverse regulated phase current error607and the reference or triangular signal6191or619nand generates a corresponding modulated inverse phase current error6131or613nbased on a difference between the inverse regulated phase current error605and the respective reference or triangular signal6191or619n. Thus, for example, a first modulated inverse phase current error6131is generated in the first hysteretic modulator6081via the third adder6121. Alternatively, because each of the respective reference or triangular signals6191-619noutput by the signal generators6181-618nis a zero-average signal, the modulated phase current errors6111-611nand the modulated inverse phase current errors6131-613nmay also be based on sums, not differences, of these inputs to adders6101-610nand6121-612n.

As shown inFIG. 6, each of the modulated phase current errors6111-611ngenerated based on the regulated phase current error605(or the phase current error603) is input to a respective first hysteretic comparator6141-614n. Each of the modulated inverse phase current errors6131-613ngenerated based on the inverse regulated phase current error607(or the inverse of the phase current error603) is input to a respective second hysteretic comparator6161-616n. The output of each of the respective first hysteretic comparators6141-614nis used to generate two gate inputs (e.g.,522a1-1and522a1-2or522aN-1and522an-2) of the respective set of four gate inputs522a1-1-522a1-4. . .522aN-1-522an-4, to control cascaded H-bridges508A1-508An. As previously noted, two duplicate sets of the components shown inFIG. 6may be employed in the hysteretic controller504to generate the gate inputs522b1-1-522b1-4. . .522bN-1-522bn-4and522c1-1-522c1-4. . .522cN-1-522cn-4to control cascaded H-bridges508B1-508Bnand508C1-508Cn, respectively. Each gate input is input to the gate or base of one power switch of the respective one of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn. One gate input (e.g.,552a1-1or522n1-1) is simply the output of the respective first hysteretic comparator6141or614n, and the other gate input (e.g.,522a1-2or522n1-2) is the inverse of that output as generated by a respective one of the second inverters6201or620n. In the same manner, the output of each of the respective second hysteretic comparators6161-616nis used to generate the two additional gate inputs (e.g.,522a1-3and522a1-4or522aN-3and522an-4) of the respective set of four gate inputs522a1-522anto control cascaded H-bridges508A1-508An. The gate inputs522b1-522bnand522c1-522cnof the other cascaded H-bridges508B1-508Bnand508C1-508Cnmay be generated in the hysteretic controller504using duplicate sets of components as previously discussed. One gate input (e.g.,522a1-3or522n1-3) is simply the output of the respective second hysteretic comparator6161or616n, and the other gate input (e.g.,522a1-4or522n1-4) is the inverse of that output as generated by a respective one of the third inverters6221-622n.

Each of the first hysteretic comparators6141-614nand each of the second hysteretic comparators6161-616ncompares the modulated phase current error (e.g.,6111or611n) or the modulated inverse phase current error (e.g.,6131or613n) received by the respective hysteretic comparator to a predetermined current range defined by a predetermined lower current limit, such as a minimum current (e.g., −h), and a predetermined upper current limit, such as a maximum current (e.g., +h). The predetermined current range may also be referred to as a predetermined hysteresis band. In one implementation, the predetermined lower current limit is the negative of the predetermined upper current limit.

Each of the first hysteretic comparators6141-614nand each of the second hysteretic comparators6161-616nis operatively configured to switch its output to a high (e.g., logic “1”) output voltage if the modulated phase current error (e.g.,6111or611n) or the modulated inverse phase current error (e.g.,6131or613n) received by the respective hysteretic comparator changes from being within the predetermined current range to being greater than the predetermined upper current limit (e.g., +h) of the predetermined current range.

Each of the first hysteretic comparators6141-614nand each of the second hysteretic comparators6161-616nis operatively configured to switch its output to a low (e.g., logic “0”) output voltage if the modulated phase current error (e.g.,6111or611n) or the modulated inverse phase current error (e.g.,6131or613n) received by the respective hysteretic comparator changes from being within the predetermined current range to being less than the predetermined lower current limit (e.g., −h) of the predetermined current range.

In both of the above situations, each of the two gate inputs of the respective set of four gate inputs522a1-522an,522b1-522bn, or522c1-522cnwhich are generated by the respective hysteretic comparator6141,6161,614nor616nare changed from a first voltage level to a second voltage level. This change in gate input voltage effectively causes a switching event of a respective one of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn. Switching event, as that term is used herein, means a change in the voltage between the output terminals212and214of one of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cncaused by a change in a respective set of four gate inputs522a1-522an,522b1-522bn, or522c1-522cnto the H-bridge under the control of the hysteretic controller504.

In one implementation, however, the change in gate input voltage does not cause a switching event of the respective one of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnbecause the change in gate input voltage results in a redundant state of the respective one of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn. For example, Table 1 indicates the voltage between the output terminals212and214of one of the H-bridges (e.g.,508A1) as caused by each possible state of the respective set of four gate inputs (e.g.,522a1-1-522a1-4) to the one H-bridge (e.g.,508A1) generated by a corresponding first hysteretic comparator (e.g.,6141) and a corresponding second hysteretic comparator (e.g.,6161).

As shown in Table 1, states 0 and 3 of the respective set of four gate inputs (e.g.,522a1) are redundant states which both result in zero voltage between the output terminals212and214of the one H-bridge (e.g.,508A1). Accordingly, it will be seen that if the two gate inputs (e.g.,522a1-1and522a1-2) of the respective set of four gate inputs (e.g.,522a1) generated by the corresponding first hysteretic comparator (e.g.,6141) change from logic “0” (for the first gate input) and logic “1” (for the second gate input), or vice versa, to logic “1” (for the first gate input) and logic “0” (for the second gate input), and the two gate inputs (e.g.,522a1-3and522a1-4) of the respective set of four gate inputs (e.g.,522a1) generated by the corresponding second hysteretic comparator (e.g.,6161) undergo the same change at the same time, no switching event of the respective one of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnoccurs.

Moreover, in one implementation, if the output of the respective hysteretic comparator6161,6141,614nor616nis already at a high (e.g., logic “1”) output voltage, the respective hysteretic comparator will maintain its output at the high output voltage if the modulated phase current error (e.g.,6111or611n) or the modulated inverse phase current error (e.g.,6131or613n) received by the respective hysteretic comparator changes from being within the predetermined current range to being greater than the predetermined upper current limit (e.g., +h) of the predetermined current range. In this implementation, the respective hysteretic comparator6161,6141,614nor616neffectively determines that the phase current error603still exceeds the upper current limit of the hysteresis band (i.e., greater than +h) and the corresponding power switch (e.g.,208a) of the H-bridge (e.g.,508A1) still needs to output the positive supply voltage and not be switched off or to the negative supply voltage.

Similarly, in one implementation, if the output of the respective hysteretic comparator6161,6141,614nor616nis already at a low (e.g., logic “0”) output voltage, the respective hysteretic comparator will maintain its output at the low output voltage if the modulated phase current error (e.g.,6111or611n) or the modulated inverse phase current error (e.g.,6131or613n) received by the respective hysteretic comparator changes from being within the predetermined current range to being less than the predetermined lower current limit (e.g., −h) of the predetermined current range. In this implementation, the respective hysteretic comparator6161,6141,614nor616neffectively determines that the phase current error603still exceeds the lower current limit of the hysteresis band (i.e., less than −h) and the corresponding power switch (e.g.,208a) of the H-bridge (e.g.,508A1) still needs to output the negative supply voltage and not be switched off or to the positive supply voltage. Accordingly, in these two situations, no switching event of the respective one of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnoccurs under the control of the hysteretic controller504.

Each of the first hysteretic comparators6141-614nand each of the second hysteretic comparators6161-616nis further operatively configured to maintain its output voltage, and therefore the two gate inputs of the respective set of four gate inputs522a1-522an,522b1-522bn, or522c1-522cnwhich are generated by the respective hysteretic comparator, at the level last generated by the respective hysteretic comparator if the modulated phase current error (e.g.,6111or611n) or the modulated inverse phase current error (e.g.,6131or613n) received by the respective hysteretic comparator is within the predetermined current range or hysteresis band.

At the low slew rate portions (such as the sinusoidal peaks) of the waveforms of each of the phase current references518a,518b, and518c, the values of the corresponding modulated phase current errors6111-611nand the values of the corresponding modulated inverse phase current errors6131-613n(and corresponding phase current error603) typically exceed the predetermined current range or hysteresis band (+/−h) less frequently because the low slew rate portions of the waveform of the respective phase current reference518a,518b, or518care those portions at which the phase current reference518a,518b, or518c, on which the values of the modulated phase current errors and the modulated inverse phase current errors ultimately depend, changes more slowly. Conversely, at the high slew rate portions (such as the zero-crossings) of the waveforms of each of the phase current references518a,518b, and518c, the values of the modulated phase current errors6111-611nand the values of the modulated inverse phase current errors6131-613ntypically exceed the predetermined current range or hysteresis band (+/−h) more frequently because the respective phase current reference518a,518b, or518cchanges more rapidly. Moreover, the low slew rate portions and high slew rate portions, respectively, of the waveform of each of the phase current references518a,518b, and518coccur at the same times as would the low slew rate portions and high slew rate portions, respectively, of the waveform of each of the phase voltage references received by the deterministic controller120employed in the conventional voltage drive system100. As will be recognized by one of ordinary skill in the art, this correspondence occurs because the two waveforms are proportional to one another. As will be further recognized by one of ordinary skill in the art, the low slew rate portions and high slew rate portions, respectively, of the waveform of the phase voltage reference occur at approximately the same times as do the low slew rate portions and high slew rate portions, respectively, of the voltage waveform of the single-phase output signal on the respective phase output line502A,502B, or502C.

Given this correspondence, the above-described behavior also occurs because at the low slew rate portions of the waveform of the phase current reference518a,518b, or518c, the current value of the single-phase output signal on the respective phase output line502A,502B, or502C—on which the values of the modulated phase current errors and the values of the modulated inverse phase current errors ultimately depend—changes less rapidly. This less rapid change occurs because the low slew rate portions of the waveform of the phase current reference518a,518b, or518ccorrespond to the low slew rate portions—that is, the peaks—of the voltage waveform of the single-phase output signal, at which a lesser voltage differential exists between the voltage value of the single-phase output signal on the respective phase output line502A,502B, or502C and the supply voltages to the respective H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn. Conversely, at the high slew rate portions of the waveform of the phase current reference518a,518b, or518c, the current value of the single-phase output signal on the respective phase output line502A,502B, or502C changes more rapidly—thus further contributing to the above-described behavior—because a greater voltage differential exists between the voltage value of the single-phase output signal on the respective phase output line502A,502B, or502C and the supply voltages to the respective H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn.

In view of the above-described behavior, the hysteretic non-deterministic control scheme employed by the hysteretic controller504to change the gate inputs522a1-522an,522b1-522bn, and522c1-522cn, as described herein, has the desired result of causing an increase in the frequency of the switching events of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnat times corresponding to the high slew rate portions of the voltage waveform of the single-phase output signal on the respective phase output line502A,502B, or502C and causing a decrease in the frequency of the switching events of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnat times corresponding to the low slew rate portions of the voltage waveform of the single-phase output signal on the respective phase output line502A,502B, or502C. Thus, by changing the gate inputs522a1-522an,522b1-522bn, and522c1-522cnto the H-bridges in accordance with the hysteretic non-deterministic control scheme as described herein, the hysteretic controller504is able to prevent the above-described distortions resulting from too high of a switching rate at the low slew rate portions, and too low of a switching rate at the high slew rate portions, of the voltage waveform of the single-phase output signal on the respective phase output line502A,502B, or502C. Unlike conventional deterministic controllers120that provide for fixed rate H-bridge switching, the hysteretic controller504is also able to reduce H-bridge switching losses because of the decrease in switching frequency at times of high current flow through the H-bridges106A1-106An,106B1-106Bn, or106C1-106Cn. Moreover, the spreading of energy resulting from the increases and decreases in switching frequency allows the hysteretic controller504to eliminate the clearly defined tones in the spectrum (not shown) of the single-phase output voltage and single-phase output current. Additionally, the use of a closed-loop system of the voltage drive system500to both increase and decrease the switching events of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnprevents the discontinuities and non-linearities that result from open-loop control, as discussed above.

The use of an appropriately sized predetermined current range or hysteresis band by the hysteretic controller504introduces an appropriate degree of hysteresis in the phase current error603(reflecting the hysteresis in the switching of the gate inputs522a1-522an,522b1-522bn, or522c1-522cncorresponding to the respective H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn) and allows the requisite effective switching rate to be achieved by the hysteretic controller504without the excessive switching of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnthat would result if the predetermined current range or hysteresis band were too small. In one implementation, the size of the predetermined current range or hysteresis band is proportional or equal to the amplitude of the waveform of the phase current reference518a,518b, or518c.

Moreover, because a switching event of one of the cascaded H-bridges (e.g.,508A1) under the control of the hysteretic controller504includes a change in the voltage between the output terminals212and214of the one H-bridge (e.g.,508A1), the corresponding single-phase output signal on the respective phase output line (e.g.,502A) changes as a result of the switching event. More particularly, as will be recognized by one of ordinary skill in the art upon review of the present application and with particular reference to Table 1, because the switching event is effectively caused by a change in the value of a respective modulated phase current error (e.g.,6111) or a respective modulated inverse phase current error (e.g.,6131), which change may in turn be caused by a change in the phase current error603, which change may in turn be caused by a change in the corresponding phase current reference518a,518b, or518c, the switching event allows the corresponding single-phase output signal on the respective phase output line (e.g.,502A) to track the corresponding phase current reference518a,518b, or518c.

This tracking occurs because the switching event, under the control of the hysteretic controller504, causes the corresponding single-phase output signal collectively generated on the respective phase output line (e.g.,502A) by the one H-bridge (e.g.,508A1) and the other H-bridges (e.g.,508A2-508An) with which the one H-bridge is cascaded to decrease in voltage, such that the corresponding single-phase output signal is equal in voltage to a predetermined voltage level, when the respective modulated phase current error (e.g.,6111) or the respective modulated inverse phase current error (e.g.,6131) changes from being within the predetermined current range to being less than the predetermined lower current limit of the predetermined current range (corresponding to a decrease in the phase current error603caused by a decrease in the corresponding phase current reference518a,518b, or518c). The decrease in voltage of the corresponding single-phase output signal occurs because the voltage between the output terminals212and214of the one H-bridge (e.g.,508A1) decreases in response to the change in the respective modulated phase current error (e.g.,6111) or the respective modulated inverse phase current error (e.g.,6131), as discussed above and shown in Table 1.

Conversely, the switching event, under the control of the hysteretic controller504, causes the corresponding single-phase output signal collectively generated on the respective phase output line (e.g.,502A) by the one H-bridge (e.g.,508A1) and the other H-bridges (e.g.,508A2-508An) with which the one H-bridge is cascaded to increase in voltage, such that the corresponding single-phase output signal is equal in voltage to a predetermined voltage level, when the respective modulated phase current error (e.g.,6111) or the respective modulated inverse phase current error (e.g.,6131) changes from being within the predetermined current range to being greater than the predetermined upper current limit of the predetermined current range (corresponding to an increase in the phase current error603caused by an increase in the corresponding phase current reference518a,518b, or518c). The increase in voltage of the corresponding single-phase output signal occurs because the voltage between the output terminals212and214of the one H-bridge (e.g.,508A1) increases in response to the change in the respective modulated phase current error (e.g.,6111) or the respective modulated inverse phase current error (e.g.,6131), as discussed above and shown in Table 1.

As will be further recognized by one of ordinary skill in the art upon review of the present application, the first hysteretic comparators6141-614nand the second hysteretic comparators6161-616nof the hysteretic controller504control the switching events of the respective H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnsuch that the values of the respective modulated phase current errors6111-611nand the values of the respective modulated inverse phase current errors6131-613nare forced to about zero amperes (or to the center of the predetermined current range) upon any fluctuation in the respective modulated phase current errors6111-611nor the respective modulated inverse phase current errors6131-613n(and thus in the phase current error603). This result occurs because, as discussed above and as shown in Table 1, each of the first hysteretic comparators6141-614nand the second hysteretic comparators6161-616nof the hysteretic controller504changes its output such that the voltage between the output terminals212and214of a respective one of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cndecreases when the modulated phase current error6111-611nor modulated inverse phase current error6131-613nreceived by the respective hysteretic comparator changes from being within the predetermined current range to being less than the predetermined lower current limit of the predetermined current range. Because the voltage between the output terminals212and214of the respective one of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cndecreases, the voltage of the single-phase output signal on the respective phase output line502A,502B, or502C decreases. Consequently, the corresponding phase current feedback520a,520b, or520cdecreases, which in turn causes the phase current error603and thus the modulated phase current error6111-611nor modulated inverse phase current error6131-613nreceived by the respective hysteretic comparator to increase, thereby correcting the prior decrease in the modulated phase current error6111-611nor modulated inverse phase current error6131-613nreceived by the respective hysteretic comparator. Specifically, the corresponding current feedback circuit506A,506B, or506C may be implemented such that the decrease in the corresponding phase current feedback520a,520b, or520ctypically forces the modulated phase current error6111-611nor modulated inverse phase current error6131-613nback to about zero (or to the center of the predetermined range).

Conversely, as discussed above and as shown in Table 1, each of the first hysteretic comparators6141-614nand the second hysteretic comparators6161-616nof the hysteretic controller504changes its output such that the voltage between the output terminals212and214of a respective one of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnincreases when the modulated phase current error6111-611nor modulated inverse phase current error6131-613nreceived by the respective hysteretic comparator changes from being within the predetermined current range to being greater than the predetermined upper current limit of the predetermined current range. Because the voltage between the output terminals212and214of the respective one of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnincreases, the voltage of the single-phase output signal on the respective phase output line502A,502B, or502C increases. Consequently, the corresponding phase current feedback520a,520b, or520cincreases, which in turn causes the phase current error603and thus the modulated phase current error6111-611nor modulated inverse phase current error6131-613nreceived by the respective hysteretic comparator to decrease, thereby correcting the prior increase in the modulated phase current error6111-611nor modulated inverse phase current error6131-613nreceived by the respective hysteretic comparator. Specifically, the corresponding current feedback circuit506A,506B, or506C may be implemented such that the increase in the corresponding phase current feedback520a,520b, or520ctypically forces the modulated phase current error6111-611nor modulated inverse phase current error6131-613nback to about zero (or to the center of the predetermined range).

Because the values of the modulated phase current errors6111-611nand modulated inverse phase current errors6131-613nare forced to about zero amperes (or to the center of the predetermined current range), the fluctuation of the modulated phase current errors6111-611nand modulated inverse phase current errors6131-613nfrom the predetermined current range may continue, thereby continuing to cause the switching events of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnunder the control of the hysteretic controller504in the manner described above.

The modulation of the phase current error603via the reference or triangular signals6191-619nproduced by the signal generators6181-618nwill now be explained in detail. The reference or triangular signals6191-619ngenerated by the signal generators6181-618nhave a common amplitude, are periodic with a common frequency, and otherwise equal except that each of the reference or triangular signals6191-619nhas a phase different from the phase of each of the other reference or triangular signals6191-619n. In one implementation, the reference or triangular signal6192is shifted from the reference or triangular signal6191by 180/n degrees, where n is the number of cascaded H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnin each phase output line502A,502B, and502C. In this implementation, the reference or triangular signal6193is further shifted from the reference or triangular signal6192by an additional 180/n degrees, and so on for each successive one of the reference or triangular signals6191-619n. Because of this phase differential, each of the modulated phase current errors6111-611nand each of the modulated inverse phase current errors6131-613n, respectively, is a phase-shifted version of each of the other modulated phase current errors6111-611nand each of the other modulated inverse phase current errors6131-613n, respectively, such that each hysteretic modulator6081-608nreceives and processes a particular portion of the phase current error603at different times within a period corresponding to a frequency of the reference or triangular signals6191-619n. Thus, the switching events of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnare based on, among other things, the phase current error603and the reference or triangular signals6191-619n. More particularly, the reference or triangular signals6191-619nare separated in phase such that the switching events of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnare separated from one another by corresponding non-zero time intervals. As will be recognized by one of ordinary skill in the art, the non-zero time intervals increase as the common amplitude of the reference or triangular signals6191-619nincreases. Appropriate sizing of the common amplitude of the reference or triangular signals6191-619nprevents an excessive switching frequency of the single-phase output signal produced by the cascaded H-bridges508A1-508An,508B1-508Bn, or508C1-508Cncontrolled by the hysteretic modulators6081-608n. As previously discussed, the signal generators6181-618nmay also generate non-triangular signals. Any set of n signals which are periodic and have phase relationships which cause the switching events of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnto be separated from one another by non-zero time intervals may be employed in the hysteretic controller504. For example, but not by way of limitation, the signals6191-619ngenerated by signal generators6181-618nmay be square wave signals or sinusoidal signals.

Another alternative embodiment employs a time slice based controller (not shown in figures) in lieu of each signal generator6181-618nto accomplish the interleaving of the switching events of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn. A time slice based controller provides each of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnwith a slice of time in a predetermined period in which the respective H-bridge is allowed to switch.

Because each reference or triangular signal6191-619nis a zero-average signal, as discussed above, it will be recognized by one of ordinary skill in the art that the addition or subtraction of the respective reference or triangular signal6191-619nto or from the regulated phase current error605and the inverse regulated phase current error607, respectively, does not prevent the modulated phase current errors6111-611nand the modulated inverse phase current errors6131-613n(which correspond to the phase current error603), respectively, from exceeding the predetermined current range less frequently at the low slew rate portions of the waveform of the phase current reference518a,518b, or518cand more frequently at the high slew rate portions of the waveform of the phase current reference518a,518b, or518c. Rather, the reference or triangular signals6191-619nare simply used to enable the hysteretic controller504to scatter or space in time the switching events (e.g., the changes in the output voltages of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cncaused by changes in the respective sets of four gate inputs522a1-522an,522b1-522bn, or522c1-522cnto the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn). As discussed with respect toFIG. 2, this temporal scattering of the switching events causes the effective switching rate at the output of the phase output line502A,502B, or502C to be multiplied by 2·n, thereby allowing lower switching rates of each individual H-bridge508A1-508An,508B1-508Bn, or508C1-508Cn.

Referring now toFIG. 7, a block diagram of an exemplary hysteretic comparator700suitable for implementing each of the first hysteretic comparators6141-614nand the second hysteretic comparators6161-616nis shown. The hysteretic comparator700includes an analog-to-digital (A/D) converter702, a state machine704, a program memory706, and a digital-to-analog (D/A) converter708. The program memory706may be flash memory or other non-volatile memory device. The state machine704may be, for example, a central processing unit (CPU) having an internal memory709and operatively configured to access and execute instructions from program memory706. The internal memory709may be, for example, an internal RAM, ROM, cache memory, flash memory or other memory storage device. In one implementation, the state machine704, alone or in combination with one or more of the A/D converter702, the program memory706, and the D/A converter708, may be implemented in hardware alone (e.g., using an Application Specific Integrated Circuit (ASIC) or a combination of a programmable logic array and discrete components).

As shown inFIG. 7, the hysteretic comparator700may store a last state710of the output of the state machine704in the internal memory709or in the program memory706. The program memory706includes a hysteresis band module714that stores the predetermined lower current limit (−h) and predetermined upper current limit (+h) of the predetermined current range or hysteresis band (+/−h) discussed above with respect toFIG. 6. The program memory706also includes a hysteresis band comparator module716which includes instructions accessible and executable by the state machine704(or the CPU therein) for comparing a digital signal718input to the state machine704to the predetermined current range or hysteresis band (+/−h) stored in memory706in the manner described above with respect toFIG. 6. The executable instructions may correspond to portions of the steps shown below in the process flow ofFIG. 12. Alternatively, one or more of the predetermined lower current limit (−h) and predetermined upper current limit (+h) of the predetermined current range or hysteresis band (+/−h) and the executable instructions for comparing an input to the state machine704to the predetermined current range or hysteresis band (+/−h) may be stored in the internal memory709of the state machine704.

The A/D converter702receives a respective one701of the modulated phase current errors (e.g.,6111or611n) or modulated inverse phase current errors (e.g.,6131or613n) and converts the respective modulated phase current error or modulated inverse phase current error701into the digital signal718. The digital signal718is then output by the A/D converter702to the state machine704. The state machine704accesses the executable instructions stored in the hysteresis band comparator module716, and the predetermined lower current limit and predetermined upper current limit of the predetermined current range or hysteresis band as stored in the hysteresis band module714to process the digital signal718and, if stored in the internal memory709or program memory706as discussed above, the last state710of the output of the state machine704. The state machine704performs this processing to generate a next state720of the output of the state machine704. The next state720of the output of the state machine704is input to the D/A converter708to generate a gate input (e.g.,522a1-1as shown inFIG. 6) of the respective set of four gate inputs522a1,522an,522b1,522bn,522c1or522cnto a respective one of the H-bridges508A1,508An,508B1,508Bn,508C1or508Cnin the manner described herein.

FIG. 8illustrates a voltage waveform800of a single-phase output signal synthesized and output on a phase output line502A,502B, or502C by a voltage drive system consistent with the present invention (such as, for example, the voltage drive system500ofFIGS. 5-7) that employs a hysteretic non-deterministic controller (e.g.,504inFIG. 5). As compared to the output waveform400ofFIG. 4generated by conventional voltage drive systems100employing a deterministic controller120, the voltage waveform800is considerably smoother because the switching rates of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnare increased by the hysteretic non-deterministic controller504at times corresponding to the zero crossings of the voltage waveform800(and the waveform of the associated phase current reference518a,518b, or518c) and decreased at times corresponding to the peaks of the voltage waveform800(and the waveform of the associated phase current reference518a,518b, or518c). Moreover, switching losses are reduced and the clearly defined tones in the spectrum (not shown) of the single-phase output signal are reduced because of the spreading of energy resulting from the variation of the switching rates of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnby the hysteretic non-deterministic controller504.

FIG. 9is a block diagram of another voltage drive system900consistent with the present invention. The voltage drive system900produces a similar single-phase output signal voltage waveform as that depicted inFIG. 8on each of the phase output lines502A,502B, and502C. The voltage drive system900includes the components of the voltage drive system500except that the hysteretic controller504is replaced with a multi-level hysteretic non-deterministic controller902(hereinafter the multi-level hysteretic controller902). Each of the common components of the voltage drive system500and the voltage drive system900operates in the same manner in each system500and900except as altered by the multi-level hysteretic controller902in the manner described below.

FIG. 10illustrates a block diagram of the multi-level hysteretic controller902. The components of the multi-level hysteretic controller902shown inFIG. 10correspond to the components for controlling one group of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnto generate a single-phase output signal on a corresponding one of the phase output lines502A,502B, or502C in accordance with the present invention. However, two duplicate sets of components as shown inFIG. 10may be employed in the multi-level hysteretic controller902to control the other two groups of H-bridges in a similar manner. Therefore, for simplicity, only those components corresponding to one group of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnand one of the phase output lines502A,502B, or502C are shown and discussed herein. For each phase output line502A,502B, and502C, the multi-level hysteretic controller902includes an adder1002, a proportional integral current regulator1004, a multi-level hysteretic comparator1006, and a decoder1008.

In operation, for each phase output line502A,502B, and502C, the adder1002receives as input a respective one of the phase current references518a,518b, and518cfrom the torque/flux controller512and a respective one of the phase current feedbacks520a,520b, and520cfrom a respective one of the current feedback circuits506A,506B, and506C. The adder1002computes a difference between the received phase current reference518a,518b, or518cand the received phase current feedback520a,520b, or520cto generate a phase current error1003, which is output to the proportional integral current regulator1004. The output of the proportional integral current regulator1004is based on and proportional to the phase current error1003. The output of the proportional integral current regulator1004will be referred to as a regulated phase current error1005. The regulated phase current error1005is input to the multi-level hysteretic comparator1006. In one implementation, the proportional integral current regulator1004may be omitted and the phase current error1003input directly to the multi-level hysteretic comparator1006.

The multi-level hysteretic comparator1006receives the regulated phase current error1005(or phase current error1003) and generates a drive-state output1007corresponding to one of a plurality of predetermined voltage levels based on the phase current error1003or1005. Specifically, the multi-level hysteretic comparator1006compares the phase current error1003or1005to a plurality of predetermined current ranges or hysteresis bands (e.g., (+/−h, +/−2 h, +/−3 h and +/−4 h). In one implementation, the number of predetermined current ranges in the plurality of predetermined current ranges is equal to 2·n (where n represents the total number of H-bridges), although any suitable number of predetermined current ranges or hysteresis bands may be used. Each predetermined current range is defined by a predetermined lower current limit, such as a minimum current, and a predetermined upper current limit, such as a maximum current. In one implementation, the predetermined lower current limit of each respective predetermined current range is the negative of the predetermined upper current limit of the respective predetermined current range. The magnitudes of the predetermined lower current limits and the predetermined upper current limits increase for each successive predetermined current range. Thus, a second predetermined current range includes a first predetermined current range, a third predetermined current range includes the first predetermined current range and the second predetermined current range, and so forth. In one implementation, the magnitudes of the predetermined lower current limits and the predetermined upper current limits are successive integer multiples of the magnitude of the predetermined lower current limit and predetermined upper current limit of the first predetermined current range. For example, in this implementation, the first predetermined current range or hysteresis band spans the current values −h to +h, the second predetermined current range or hysteresis band spans the current values −2 h to +2 h, the third predetermined current range spans the current values −3 h to +3 h, and so forth. InFIG. 10, the predetermined current ranges or hysteresis bands (e.g., (+/−h, +/−2 h, +/−3 h and +/−4 h) as implemented in the multi-level hysteretic comparator1006are graphically illustrated in comparison to an exemplary phase current error1003or1005.

The multi-level hysteretic comparator1006will generate the same drive-state output1007it last generated (e.g., for a previous phase current error1003or regulated phase current error1005) if either of the following circumstances exist: (i) the regulated phase current error1005(or phase current error1003) received at the multi-level hysteretic comparator1006is within one of the predetermined current ranges and has not exited any of the predetermined current ranges since the last drive-state output1007was generated by the multi-level hysteretic comparator1006, or (ii) the regulated phase current error1005received by the multi-level hysteretic comparator1006is not within any of the predetermined current ranges and has not exited any of the predetermined current ranges since the last drive-state output1005was generated. In this circumstance, the multi-level hysteretic comparator1006has already generated a drive-state output1007corresponding to a maximum or minimum one of the predetermined voltage levels that a respective H-bridge (e.g.,508A1) may be switched to generate.

If, however, the regulated phase current error1005(or phase current error1003) changes from being within one of the predetermined current ranges (e.g., at point1020in the +/−2 h range) to being outside of that predetermined current range (e.g., at point1030outside the +/−2 h range), the multi-level hysteretic comparator1006will change the drive-state output1007to effectively cause, as described in further detail below, a switching event or events of the cascaded H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnsuch that the group of cascaded H-bridges collectively generates the corresponding single-phase output signal on the respective phase output line502A,502B, or502C to have a voltage corresponding to the one predetermined voltage level to which the changed drive-state output1007corresponds. Thus, and as described in further detail herein, the subsequent phase current error1003is driven within the predetermined current range or hysteresis band (e.g., +/−2 h range).

Specifically, when the regulated phase current error1005(or phase current error1003) changes from being within one of the predetermined current ranges (e.g., at point1020in the +/−2 h range) to being less than the predetermined lower current limit (e.g., at point1030, which is less than −2 h) of that predetermined current range (e.g., +/−2 h), the multi-level hysteretic comparator1006will change the drive-state output1007such that the drive-state output1007corresponds to a next higher one of the plurality of predetermined voltage levels in order to drive the phase current error1003back within that predetermined current range (e.g., +/−2 h) and towards zero voltage. Conversely, when the regulated phase current error1005(or phase current error1003) changes from being within one of the predetermined current ranges (e.g., at point1040in the +/−2 h range) to being greater than the predetermined upper current limit (e.g., at point1050, which is greater than +2 h) of that predetermined current range (e.g., +/−2 h), the multi-level hysteretic comparator1006will change the drive-state output1007such that the drive-state output1007corresponds to a next lower one of the plurality of predetermined voltage levels in order to drive the phase current error1003back within that predetermined current range (e.g., +/−2 h) and towards zero voltage. Control of the drive-state output1007in this manner enables the corresponding single-phase output signal on the respective phase output line (e.g.,502A) to track the corresponding phase current reference518a,518b, or518c, as discussed in detail herein.

FIG. 11illustrates a block diagram of the multi-level hysteretic comparator1006as employed in each of the phase output lines502A,502B, or502C. The multi-level hysteretic comparator1006includes an analog-to-digital (A/D) converter1102, a state machine1104, a program memory1106, and a digital-to-analog (D/A) converter1108. The program memory1106may be flash memory or other non-volatile memory. The state machine1104may be, for example, a central processing unit (CPU) having an internal memory1109and operatively configured to access and execute instructions from program memory1106. The internal memory1109may be, for example, RAM, ROM, cache memory, flash memory or other memory storage device. In one implementation, the state machine1104, alone or in combination with one or more of the A/D converter1102, program memory1106, and D/A converter1108, may be implemented in hardware alone (e.g., using an ASIC or a combination of a programmable logic array and discrete components).

In one implementation, the multi-level hysteretic comparator1006may store a last state1110of the output of the state machine1104in the internal memory1109or in the program memory1106. Moreover, in one implementation, the multi-level hysteretic comparator1006may store, in the internal memory1109or in the program memory1106, a list1112of possible next states of the output of the state machine1104. The program memory1106includes a hysteresis band module1114that stores the predetermined lower current limits (e.g., −h, −2 h, −3 h and −4 h) and predetermined upper current limits (e.g., +h, +2 h, +3 h and +4 h) of the plurality of predetermined current ranges or hysteresis bands discussed above with respect toFIG. 10. The program memory1106also includes a hysteresis band comparator module1116which includes executable instructions for comparing a digital signal1118input to the state machine1104to the plurality of predetermined current ranges or hysteresis bands (e.g., +/−h, +/−2 h, +/−3 h and +/−4 h) in the manner described above with respect toFIG. 10. The executable instructions may correspond to portions of the steps shown below in the process flow ofFIG. 13. Alternatively, one or more of the predetermined lower current limits and predetermined upper current limits of the plurality of predetermined current ranges or hysteresis bands and the executable instructions for comparing an input to the state machine1104to the plurality of predetermined current ranges or hysteresis bands may be stored in the internal memory1109of the state machine1104.

The A/D converter1102receives the regulated phase current error1005(or the phase current error1003if the current regulator1004is omitted) and converts the regulated phase current error1005(or phase current error1003) into the digital signal1118. The digital signal1118is then output by the A/D converter1102to the state machine1104. The state machine1104accesses the executable instructions stored in the hysteresis band comparator module1116, and the predetermined lower current limits and predetermined upper current limits of the plurality of predetermined current ranges or hysteresis bands (e.g., +/−h, +/−2 h, +/−3 h and +/−4 h) as stored in the hysteresis band module1114as well as the last state1110of the output of the state machine1104, and the list1112of possible next states of the output of the state machine1104to process the digital signal1118. The state machine1104performs this processing to generate a next state1105of the output of the state machine1105. The next state (e.g.,1105) of the output of the state machine1104corresponds to one of the possible next states of the output of the state machine1104included in the list112. The next state of the output of the state machine1104is input to the D/A converter1108to generate the drive-state output1007in the manner described above.

Referring back toFIG. 10, the decoder1008generates a respective set of four gate inputs1010a1-1010an,1010b1-1010bn, or1010cn-1010cnfor each H-bridge of the respective group of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnthat are cascaded together to produce a respective single-phase output signal (such as depicted inFIG. 8). Each gate input of the respective set of four gate inputs1010a1-1010an,1010b1-1010bn, or1010cn-1010cn(e.g., four gate inputs referenced as1010a1-1-1010a1-4) is input to the gate or base of a corresponding one power switch (e.g.,108a-108d) of the respective H-bridges (e.g.,508A1). The decoder1008generates the respective sets of four gate inputs1010a1-1010an,1010b1-1010bn, or1010c1-1010cnbased on the drive-state output1007so that the group of cascaded H-bridges508A1-508An,508B1-508Bn, or508C1-508Cncollectively generate the single-phase output signal on the phase output line502A,502B, or502C to have a voltage equal to the one predetermined voltage level to which the drive-state output1007corresponds.

Accordingly, when the drive-state output1007is changed to correspond to a next lower one of the plurality of predetermined voltage levels, the decoder1008changes the respective sets of four gate inputs1010a1-1010an,1010b1-1010bn, or1010c1-1010cnsuch that the voltage between the output terminals212and214of at least one of the cascaded H-bridges (e.g.,508A1) decreases. Conversely, when the drive-state output1007is changed to correspond to a next higher one of the plurality of predetermined voltage levels, the decoder1008changes the respective sets of four gate inputs1010a1-1010an,1010b1-1010bn, or1010c1-1010cnsuch that the voltage between the output terminals212and214of at least one of the cascaded H-bridges (e.g.,508A1) increases.

Because the voltage of the single-phase output signal generated by a cascaded group of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnis equal to the sum of the voltages between the output terminals212and214of each of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnthat are cascaded together, the same voltage of the single-phase output signal may be obtained from a number of different states of the cascaded H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn, where a state of the cascaded group of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cncorresponds to a particular combination or state of the plurality of sets of four gate inputs1010a1-1010an,1010b1-1010bn, or1010c1-1010cngenerated by the decoder1008of the multi-level hysteretic controller902to switch the respective H-bridge (e.g.,508A1). Thus, while the decoder1008may generate the plurality of sets of four gate inputs1010a1-1010an,1010b1-1010bn, and1010c1-1010cnbased solely on the drive-state output1007. In one implementation, the decoder1008generates the plurality of sets of four gate inputs1010a1-1010an,1010b1-1010bn, and1010c1-1010cnbased on the drive-state output1007and a last state of the cascaded group of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn.

To achieve this functionality, the decoder1008may include a processor (CPU)1011and a memory1013holding a look-up table (LUT)1015. The look-up table1015stores each configuration of the plurality of sets of four gate inputs1010a1-1010an,1010b1-1010bn, or1010c1-1010cnfor a group of cascaded H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn. In this implementation, the processor1011is operatively configured to use the received drive-state output1007from the multi-level hysteretic comparator1006to index the look-up table1015to identify the state or combination of gate inputs (e.g.,1010a1-1010an) for switching the corresponding cascaded group of H-bridges (e.g.,508A1-508An). In one implementation, the look-up table1015stores multiple redundant states or combinations of gate inputs (e.g.,1010a1-1010an) that each correspond to the same drive-state output1007and cause the corresponding cascaded group of H-bridges (e.g.,508A1-508An) to collectively output the same voltage for the respective single-phase output signal. In this implementation, the decoder1008stores the last state of the cascaded group of H-bridges (e.g.,508A1-508An) and is configured to select one of the redundant states or combinations for output to the cascaded group of H-bridges (e.g.,508A1-508An) that limits or minimizes the number of power switches108a-108dwithin the cascaded group of H-bridges (e.g.,508A1-508An) that need to be switched from the last state to the redundant state.

For example, the look-up table1015may be implemented consistent with Table 2 as shown and described below. Table 2 indicates, for a cascaded group of two H-bridges508A1and508An, the voltage of the single-phase output signal on the phase output line502A,502B, or502C as caused by each possible state of the respective sets of four gate inputs (e.g.,1010a1and1010an) to the two H-bridges508A1and508Angenerated by the decoder1008.

As shown in Table 2, for example, the voltage of the single-phase output signal on the phase output line502A,502B, or502C is equal to the supply voltage to the two H-bridges508A1and508Anwhen the respective sets of four gate inputs (e.g.,1010a1and1010an) are in state 8. Thus, if the multi-level hysteretic comparator1006changes the drive-state output1007to correspond to a predetermined voltage level equal to zero, the decoder1008may accomplish the required change in the plurality of sets of four gate inputs (e.g.,1010a1and1010an) by changing the plurality of sets of four gate inputs (e.g.,1010a1and1010an) to one of states 0, 3, 6, 9, 12, and 15.

Changing the plurality of sets of four gate inputs (e.g.,1010a1and1010an) to state 0, for example, only requires changing two gate inputs of the first set of four gate inputs (e.g.,1010a1). Specifically, the gate inputs1010a1-1and1010a1-4to power switches108aand108bof H-bridge508A1must be changed from logic “1” and logic “0,” respectively, to logic “0” and logic “1,” respectively. Thus, a switching event of the H-bridge508A1occurs, but no switching event of the H-bridge508Anoccurs.

However, changing the plurality of sets of four gate inputs (e.g.,1010a1and1010an) to state 6, for example, requires changing all four gate inputs of the first set of four gate inputs (e.g.,1010a1) and two gate inputs of the second set of four gate inputs (e.g.,1010an). Specifically, the gate inputs1010a1-0,1010a1-1,1010a1-2, and1010a1-3to power switches108a,108b,108c, and108dof H-bridge508A1must be changed from logic “1,” logic “0,” logic “0,” and logic “1,” respectively, to logic “0,” logic “1,” logic “1,” and logic “0,” respectively. Thus, a switching event of the H-bridge508A1occurs. Similarly, the gate inputs1010an-0and1010an-1to power switches108aand108bof H-bridge508Anmust be changed from logic “0” and logic “1,” respectively, to logic “1” and logic “0,” respectively. Thus, a switching event of the H-bridge508Analso occurs, and a total of two switching events and six changes to the plurality of sets of four gate inputs (e.g.,1010a1and1010an) are required to change to state 6. Accordingly, the decoder1008will choose to change the plurality of sets of four gate inputs (e.g.,1010a1and1010an) to, for example, state 0 instead of state 6.

Although the decoder1008is described as including a programmed processor1011and memory1013for storing the look-up table1015accessed by the processor1011, the decoder1008may be implemented through hardware alone (e.g., an ASIC chip) or through a combination of hardware and software.

In one implementation, the decoder1008also may select a combination of gate inputs1010a1-1010an,1010b1-1010bn, and1010c1-1010cnfrom redundant combinations such that each of the H-bridges in the respective cascaded group of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnhas equal average switching and conduction losses and such that each of the respective cascaded group of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cndraws equal power from the respective secondary winding circuits124A1-124An,124B1-124Bn, or124C1-124Cnof the input transformer102. For example, in one implementation in which three H-bridges508A1,508A2, and508Anare cascaded together to collectively generate a single-phase output signal on the phase output line502A, and assuming the drive-state output1007corresponds to a predetermined voltage level equal to the supply voltage to the H-bridges508A1,508A2, and508An, the decoder may select a redundant state or combination of gate inputs1010a1,1010a2, and1010anwhere the first H-bridge508A1is switched to output a positive supply voltage, the second H-bridge508A2is switched to output a negative supply voltage that negates the output of the first H-bridge508A1, and the third H-bridge508Anis switched to also output a positive supply voltage. In this exemplary implementation, each of the three H-bridges508A1,508A2, and508Andraws power equally from the secondary winding circuits124A1,124A2, and124Anrather than having only one of the three H-bridges508A1,508A2, and508Anprovide the required output voltage.

In another embodiment which further prevents unnecessary switching of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn, the decoder1008may employ predictive modeling techniques to generate the plurality of sets of four gate inputs1010a1-1010an,1010b1-1010bn, and1010c1-1010cnbased on the drive-state output1007from the hysteretic comparator1006, the last state of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn, and the expected future states of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnas determined based on, for example, the waveform of the phase current reference518a,518b, or518c.

Continuing withFIG. 10, as with the values of the modulated phase current errors6111-611nand the values of the modulated inverse phase current errors6131-613nreceived by the first hysteretic comparators6141-614nand6161-616nof the hysteretic controller504, the value of the regulated phase current error1005(and the corresponding value of the phase current error1003) typically exceeds each of the predetermined current ranges or hysteresis bands (e.g., +/−h, +/−2 h, . . . ) less frequently at the low slew rate portions (such as the sinusoidal peaks) of the waveform of the phase current reference518a,518b, or518cand the voltage waveform of the single-phase output signal as shown, for example, inFIG. 8. This behavior occurs because the low slew rate portions of the waveform of the respective phase current reference518a,518b, or518care those portions at which the phase current reference518a,518b, or518c, on which the value of the regulated phase current error1005ultimately depends, changes more slowly. As with the values of the modulated phase current errors6111-611nand the values of the modulated inverse phase current errors6131-613n, the converse is also true. Namely, the value of the regulated phase current error1005typically exceeds each of the predetermined current ranges more frequently at the high slew rate portions (such as the zero-crossings) of the waveform of the respective phase current reference518a,518b, or518cand the voltage waveform of the single-phase output signal as shown, for example, inFIG. 8. Moreover, this behavior also occurs because at the low slew rate portions of the waveform of the respective phase current reference518a,518b, or518c, the current value of the single-phase output signal on the respective phase output line502A,502B, or502C—on which the value of the regulated phase current error1005ultimately depends—changes less rapidly. Conversely, at the high slew rate portions of the waveform of the respective phase current reference518a,518b, or518c, the current value of the single-phase output signal on the respective phase output line502A,502B, or502C changes more rapidly, thus further contributing to the above-described behavior.

In view of the above-described behavior, the hysteretic non-deterministic control scheme described and implemented by the multi-level hysteretic controller902produces the same desired increases and decreases in the frequency of the switching events of H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnas does the hysteretic non-deterministic control scheme described and implemented by the hysteretic controller504. Because a switching event or events occurs when the regulated phase current error1005changes from being within any one (e.g., +/−2 h) of the predetermined current ranges (e.g., +/−h, +/−2 h, +/−3 h and +/−4 h) to being outside of that predetermined current range, the use of multiple predetermined current ranges allows the requisite effective switching rate of the corresponding group of cascaded H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnto be achieved.

Moreover, as with the hysteretic controller504, by appropriately sizing the predetermined current ranges to introduce an appropriate degree of hysteresis in the phase current error1003(reflecting the hysteresis in the switching of the respective H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn), this requisite effective switching rate can be achieved without causing excessive switching of the corresponding group of cascaded H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn. Specifically, in one implementation, the size of the largest predetermined current range, which includes all other predetermined current ranges as discussed above, is proportional or equal to the amplitude of the waveform of the respective phase current reference518a,518b, or518c.

Continuing withFIG. 10, each switching event of one of the cascaded H-bridges508A1-508An,508B1-508Bn, or508C1-508Cn(e.g.,508A1), under the control of the multi-level hysteretic comparator1006of the multi-level hysteretic controller902, allows the corresponding single-phase output signal on the respective phase output line (e.g.,502A) to track the corresponding phase current reference518a,518b, or518cfor similar reasons as discussed above with respect to the voltage drive system500.

For example, this tracking occurs because each switching event, under the control of the multi-level hysteretic comparator1006of the multi-level hysteretic controller902, causes the corresponding single-phase output signal collectively generated on the respective phase output line (e.g.,502A) by the one H-bridge (e.g.,508A1) and the other H-bridges (e.g.,508A2-508An) with which the one H-bridge is cascaded to decrease in voltage, such that the corresponding single-phase output signal is equal in voltage to the one predetermined voltage level to which the changed drive-state output1007corresponds, when the regulated phase current error1005changes from being within one of the plurality of predetermined current ranges to being greater than the predetermined upper current limit of that predetermined current range (e.g., due to an decrease in voltage of the phase current reference518a,518b, or518c). As discussed above with respect to the voltage drive system500, the multi-level hysteretic controller902causes the group of H-bridges (e.g.,508A1-508An) to switch to outputting a lower voltage corresponding to an increase in the phase current error1003above the respective predetermined upper current limit of that predetermined current range, which is in turn caused by a decrease in the corresponding phase current reference518a,518b, or518c. Thus, the multi-level hysteretic controller902effectively causes the decrease in voltage of the corresponding single-phase output signal on the respective phase output line502A,502B or502C to track the decrease in the corresponding phase current reference518a,518b, or518c.

Conversely, each switching event, under the control of the multi-level hysteretic comparator1006of the multi-level hysteretic controller902, causes the corresponding single-phase output signal collectively generated on the respective phase output line (e.g.,502A) by the one H-bridge (e.g.,508A1) and the other H-bridges (e.g.,508A2-508An) with which the one H-bridge is cascaded to increase in voltage, such that the corresponding single-phase output signal is equal in voltage to the one predetermined voltage level to which the changed drive-state output1007corresponds, when the regulated phase current error1005changes from being within one of the plurality of predetermined current ranges to being less than the predetermined lower current limit of that predetermined current range. As discussed above with respect to the voltage drive system500, the multi-level hysteretic controller902causes the group of H-bridges (e.g.,508A1-508An) to switch to outputting a higher voltage corresponding to a decrease in the phase current error1003below the respective predetermined lower current limit of that predetermined current range, which is in turn caused by an increase in the corresponding phase current reference518a,518b, or518c). Thus, the multi-level hysteretic controller902effectively causes the increase in voltage of the corresponding single-phase output signal on the respective phase output line502A,502B or502C to track the increase in the corresponding phase current reference518a,518b, or518c.

As will be further recognized by one of ordinary skill in the art upon review of the present application, the multi-level hysteretic comparator1006of the multi-level hysteretic controller902controls the switching events of the respective H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnsuch that the value of the regulated phase current error1005(and the value of the phase current error1003) is forced to about zero amperes (or to the center of each of the plurality of predetermined current ranges) upon any fluctuation in the regulated phase current error1005(and thus in the phase current error1003). This result occurs because, as discussed above, the multi-level hysteretic comparator1006changes the drive-state output1007such that the voltage between the output terminals212and214of at least one of the cascaded H-bridges (e.g.,508A1-508An) decreases when the regulated phase current error1005received by the multi-level hysteretic comparator1006changes from being within one of the plurality of predetermined current ranges to being greater than the predetermined upper current limit of that predetermined current range. Because the voltage between the output terminals212and214of at least one of the cascaded H-bridges (e.g.,508A1-508An) decreases, the voltage of the single-phase output signal on the respective phase output line502A,502B, or502C decreases. Consequently, the corresponding phase current feedback520a,520b, or520cdecreases, which in turn causes the phase current error1003and thus the regulated phase current error1005received by the multi-level hysteretic comparator1006to decrease relative to the respective phase reference518a,518bor518c, thereby correcting the prior positive increase in the regulated phase current error1005received by the multi-level hysteretic comparator1006. Specifically, the corresponding current feedback circuit506A,506B, or506C may be implemented such that the decrease in the corresponding phase current feedback520a,520b, or520cforces the regulated phase current error1005back to about zero (or to the center of the predetermined range).

Conversely, as discussed above, the multi-level hysteretic comparator1006of the multi-level hysteretic controller902changes the drive-state output1007such that the voltage between the output terminals212and214of at least one of the cascaded H-bridges (e.g.,508A1-508An) increases when the regulated phase current error1005received by the multi-level hysteretic comparator1006changes from being within one of the plurality of predetermined current ranges to being less than the predetermined lower current limit of that predetermined current range. Because the voltage between the output terminals212and214of at least one of the cascaded H-bridges (e.g.,508A1-508An) increases, the voltage of the single-phase output signal on the respective phase output line502A,502B, or502C increases. Consequently, the corresponding phase current feedback520a,520b, or520cincreases, which in turn causes the phase current error1003and thus the regulated phase current error1005received by the multi-level hysteretic comparator1006to decrease relative to the respective phase reference518a,518bor518c, thereby correcting the prior negative increase in the regulated phase current error1005received by the multi-level hysteretic comparator1006. Specifically, the corresponding current feedback circuit506A,506B, or506C may be implemented such that the increase in the corresponding phase current feedback520a,520b, or520cforces the regulated phase current error1005back to about zero (or to the center of the predetermined range).

Because the value of the regulated phase current error1005is forced to about zero amperes (or to the center of each of the plurality of predetermined current ranges), the fluctuation of the regulated phase current error1005from the plurality of predetermined current ranges may continue, thereby continuing to cause the switching events of the H-bridges508A1-508An,508B1-508Bn, or508C1-508Cnunder the control of the hysteretic controller902in the manner described above.

FIG. 12is a flow chart illustrating an exemplary process1200performed in the voltage drive system500ofFIG. 5to control a plurality of switching circuits (e.g., H-bridges508A1-508An, H-bridges508B1-508Bnand H-bridges508C1-508Cn) to generate one or more single-phase output signals, in accordance with the present invention, to drive a variable speed motor or other load requiring single or multi-phase, medium voltage input power. Initially, each of the hysteretic comparators6141-614nand6161-616n, employed in the hysteretic controller504may initialize the last state710of the four gate inputs (e.g.,522a1-1-522a1-4or522n1-1-522n1-4inFIG. 6) provided by the respective hysteretic comparator6141,6161,614nor616nto the respective switching circuit or H-bridge (step1202). This step may be omitted from the process1200if each of the hysteretic comparators6141-614nand6161-616ngenerate respective gate inputs (e.g.,522a1-1-522a1-4or522n1-1-522n1-4) based on whether the regulated phase current error1005(or the phase current error1003) received by the respective hysteretic comparator is within the predetermined current range or hysteresis band (e.g., +/−h) without regard to the last state of the gate inputs.

Next, as described with respect toFIG. 6, each of the hysteretic modulators6081-608nemployed in the hysteretic controller504receives a phase current error603or a regulated phase current error605(step1204). In addition, each of the hysteretic modulators6081-608nemployed in the hysteretic controller504receives an inverse607of the phase current error603or a regulated phase current error605(step1206).

A first of the hysteretic modulators (e.g.,6081) then generates a first modulated phase current error (e.g.,6111) based on the received phase current error603or regulated phase current error605and a reference or triangular signal6191having a first phase (e.g., phase=0); a second of the hysteretic modulators (e.g.,608n) also generates a second modulated phase current error (e.g.,611n) based on the same received phase current error603and a reference or triangular signal619nhaving a second phase offset from the first phase by a predetermined fraction of each reference signal's cycle or frequency (e.g., second phase=(n−1)(n/180)); and so on until each of the hysteretic modulators6081-608ngenerates a modulated phase current error6111or611nbased on the received phase current error603and a corresponding reference signal6191or619nhaving a respective phase such that each of the modulated phase current errors6111-611nis a phase-shifted version of each of the other modulated phase current errors6111-611n(step1208). In one implementation, each of the reference signals6191-619nis a zero-average signal, has a common amplitude, and is periodic with a common frequency.

Next, each of the hysteretic modulators6081-608ngenerates a respective modulated inverse phase current error6131or613nbased on a difference between the inverse regulated phase current error607and a respective reference signal6191or619n(step1210). Thus, each of the hysteretic modulators6081-608nalso generates a modulated phase current errors6131-613nthat is a phase-shifted version of each of the other modulated inverse phase current errors.

Each of the hysteretic comparators6141-614nand6161-616nemployed by a respective hysteretic modulator6081-608nthen determines whether the modulated phase current error or the modulated inverse phase current error (e.g.,6131or613n) input to the respective comparator6141,6161,614nor616nhas, since the most recent state of the gate inputs was initialized, exited a predetermined current range (e.g., +/−h) (step1212). Since each of the reference signals6191or619nare a phase-shifted version of each other and are, thus, separated by a respective time interval (e.g., corresponding to a phase offset of n/180), each of the hysteretic comparators6141-614nand6161-616ndetermines (at a respective time interval associated with the phase of the first reference signal6191) whether the respective modulated phase current error (e.g.,6111or611n) or the modulated inverse phase current error (e.g.,6131or613n) has changed from being within the predetermined current range (e.g., +/−h) to being outside of the predetermined current range. If such a change has not occurred, either because the respective modulated phase current error or modulated inverse phase current error is within the predetermined current range at the time the determination is made or because the respective modulated phase current error or modulated inverse phase current error is outside of the predetermined current range and was outside of the predetermined current range at the time the most recent state of the gate inputs was initialized, processing may continue at step1214. If such a change has occurred, processing may continue at step1218.

In the event that processing continues at step1214, each of the hysteretic comparators6141-614nand6161-616nthat has determined that the respective modulated phase current error (e.g.,6111or611n) or the respective modulated inverse phase current error (e.g.,6131or613n) has not changed from being within the predetermined current range (e.g., +/−h) to being outside of the predetermined current range will then maintain its respective gate inputs (e.g., gate inputs522a1-1and522a1-2for comparator6141and gate inputs522a1-3and522a1-4for comparator614n) will be maintained in their last state before continuing processing at step1216.

In the event that processing continues at step1216, each of the hysteretic comparators6141-614nand6161-616nthat has determined that the respective modulated phase current error (e.g.,6111or611n) or the respective modulated inverse phase current error (e.g.,6131or613n) has changed from being within the predetermined current range (e.g., +/−h) to being outside of the predetermined current range will then change its respective gate inputs (e.g., gate inputs522a1-1and522a1-2for comparator6141and gate inputs522a1-3and522a1-4for comparator614n) will be changed from their last state (i.e., corresponding to a first voltage level output of the H-bridge to which the gate inputs are connected) to a next state corresponding to a second voltage level output of the H-bridge to which the gate inputs are connected before continuing processing at step1216. The generation of the gate inputs based on the respective one of the modulated phase current errors or modulated inverse phase current errors is described above with respect toFIG. 6. Changing these gate inputs effectively causes a switching event of one of the plurality of switching circuits which receives the gate inputs (e.g., one of H-bridges in the respective group of cascaded H-bridges508A1-508An, H-bridges508B1-508Bnor H-bridges508C1-508Cn). The switching event causes the single-phase output signal generated by the cascaded switching circuits or H-bridges to be equal in voltage to a predetermined voltage level. As further discussed above with respect toFIG. 6, the switching event causes the single-phase output signal to decrease in voltage when the respective one of the modulated phase current errors or modulated inverse phase current errors changes from being within the predetermined current range to being greater than the predetermined upper current limit. When the respective one of the modulated phase current errors or modulated inverse phase current errors changes from being within the predetermined current range to being less than the predetermined lower current limit, the switching event causes the single-phase output signal to increase in voltage. Moreover, because the plurality of signals shares the characteristics of the reference signals6191-619ndiscussed with respect toFIG. 6, a first switching event of a first of the switching circuits will be separated from a second switching event of a second of the switching circuits by a predetermined time interval. The time interval increases as the common amplitude of the reference signals6191-619nincreases.

As still further discussed above with respect toFIG. 6, the control or modulation scheme implemented by the hysteretic controller504(and the comparators6141-614nand6161-616nemployed therein) has the desired result of increasing the frequency of switching events at times corresponding to the high slew rate portions of the voltage waveform of the single-phase output signal by the group of cascaded H-bridges controlled by the hysteretic controller504and decreasing the frequency of switching events at times corresponding to the low slew rate portions of the voltage waveform of the same single-phase output signal.

Next, at step1218, each of the hysteretic comparators6141-614nand6161-616nprovides its gate inputs to the corresponding switching circuit (e.g., one of H-bridges in the respective group of cascaded H-bridges508A1-508An, H-bridges508B1-508Bnor H-bridges508C1-508Cn). For example, the modulated phase current error and the modulated inverse phase current error generated based on the first reference signal6191are each used to generate two gate inputs (e.g., gate inputs522a1-1and522a1-2for comparator6141and gate inputs522a1-3an522a1-4for comparator614n) as discussed herein. The four gate inputs (e.g.,522a1-1,522a1-2,522a1-3and522a1-4) obtained from this modulated phase current error6111and modulated inverse phase current error6131are provided to a first switching circuit508A1as illustrated inFIGS. 5 and 6. Similarly, four gate inputs (e.g.,522n1-1,522n1-2,522n1-3and522n1-4) are obtained from the modulated phase current error611nand the modulated inverse phase current error613ngenerated based on the second reference signal619n. These four gate inputs are provided to a second switching circuit508Anthat is cascaded with the first switching circuit508A1to collectively generate the respective single-phase output signal on the phase output line502A.

When the changed gate inputs are provided by the hysteretic comparators employed in the hysteretic controller504to the corresponding switching circuits (e.g., a corresponding group of cascaded H-bridges508A1-508An, H-bridges508B1-508Bnor H-bridges508C1-508Cn), each of the switching circuits generates an output terminal voltage (e.g., the voltage between the output terminals212and214if each of the plurality of switching circuits is implemented consistent with the H-bridge200inFIG. 1) based on the four gate inputs received by the respective switching circuit (step1220). As previously discussed herein, the switching circuits (H-bridges508A1-508An, H-bridges508B1-508Bnor H-bridges508C1-508Cn) are cascaded such that the switching circuits collectively generate the single-phase output signal to the load.

Next, the hysteretic controller504determines whether to continue to generate the single-phase output signal (step1222). In one implementation, this determination is made based on whether an external power switch (not shown in the drawings) is in an ON state or an OFF state. If the hysteretic controller504determines not to continue to generate the single-phase output signal, the process ends. If the hysteretic controller504determines that the single-phase output signal is to be continued to be generated, processing may continue at step1204.

FIG. 13is a flow chart illustrating an exemplary process1300performed in the voltage drive system900ofFIG. 9to control a plurality of switching circuits (e.g., H-bridges508A1-508An, H-bridges508B1-508Bnand H-bridges508C1-508Cn) to generate one or more single-phase output signals to drive a variable speed motor or other load requiring phased, medium voltage input power in accordance with the present invention. Initially, in step1302, the multi-level hysteretic comparator1006employed in the multi-level hysteretic non-deterministic controller902initializes the last state of the drive-state output1007and the decoder1008(also employed in the controller902) initializes the last state of the gate inputs provided to each of a plurality of switching circuits (e.g., H-bridges such as the H-bridge200inFIG. 1).

Next, the multi-level hysteretic comparator1006receives a phase current error1003or a regulated phase current error1005(step1304).

In step1306, the multi-level hysteretic comparator1006(via the state machine1104) then determines whether a phase current error1003or a regulated phase current error1005has, since the last state of the drive-state output1007was initialized in step1302, exited one of a plurality of predetermined current ranges (e.g., +/−h, +/−2 h, +/−3 h and +/−4 h). As previously described, the multi-level hysteretic comparator1006is operatively configured to determine whether the phase current error1003or the regulated phase current error1005has changed from being within one (e.g., +/−2 h) of the plurality of predetermined current ranges (+/−h, +/−2 h, +/−3 h or +/−4 h) to being outside of the one predetermined current range (e.g., +/−2 h). The plurality of predetermined current ranges may be, for example, the plurality of predetermined current ranges discussed with respect toFIG. 10. If such a change in the phase current error1003or the regulated phase current error1005has not occurred, processing may continue at step1308. If such a change in the phase current error1003or the regulated phase current error1005has occurred, processing may continue at step1310.

In the event that processing continues at step1308, the multi-level hysteretic comparator1006maintains the drive-state output1007to the decoder1008in its last state before continuing processing at step1312. As discussed herein, the drive-state output1007corresponds to one of a plurality of predetermined voltage levels that may be generated by the group of cascaded switching circuits or H-bridges used to collectively generate the single-phase output signal on the corresponding phase output line502A,502B, or502C of the voltage drive system900.

In the event that processing continues at step1310, the multi-level hysteretic comparator1006will change the drive-state output1007to correspond to a new one of the plurality of predetermined voltage levels in the manner described with respect toFIG. 10before continuing processing at step1312.

At step1312, the decoder1008generates the four gate inputs (e.g.,1010a1-1-1010a1-4or1010n1-1-1010n1-4) to each of the plurality of switching circuits (e.g.,506A1-506An) based on the drive-state output1007from the multi-level hysteretic comparator1006. In one implementation, the decoder1008generates the four gate inputs (e.g.,1010a1-1-1010a1-4or1010n1-1-1010n1-4) to each of the plurality of switching circuits (e.g.,506A1-506An) based on the drive-state output1007from the multi-level hysteretic comparator1006and the last state of the gate inputs to the switching circuits (e.g.,506A1-506An).

Next, the decoder1008provides the gate inputs (e.g.,1010a1-1-1010a1-4through1010n1-1-1010n1-4) to the switching circuits (e.g.,506A1-506An) (step1314). The decoder1008generates the gate inputs1010a1-1-1010a1-4through1010n1-1-1010n1-4based on the drive-state output1007so that the switching circuits506A1-506Ancollectively generate the single-phase output signal to have a voltage equal to the one predetermined voltage level to which the drive-state output1007corresponds. Thus, and as discussed herein, changing the drive-state output1007in step1310effectively causes, via the decoder1008, a switching event of the plurality of switching circuits506A1-506An. As further discussed with respect toFIG. 10, the switching event causes the single-phase output signal to decrease in voltage when the phase current error1003changes from being within one of the predetermined current ranges to being greater than a predetermined higher current limit of that predetermined current range. When the regulated phase current error changes from being within one of the predetermined current ranges to being less than a predetermined lower current limit of that predetermined current range, the switching event causes the single-phase output signal to increase in voltage. In both instances, the phase current error1003is subsequently driven back within that predetermined current range and towards zero voltage.

As still further discussed above with respect toFIG. 10, this control scheme implemented by the multi-level hysteretic controller902(and the comparator1006and decoder1008employed therein) has the desired result of increasing the frequency of switching events at times corresponding to the high slew rate portions of the voltage waveform of the single-phase output signal and decreasing the frequency of switching events at times corresponding to the low slew rate portions of the voltage waveform of the single-phase output signal as depicted inFIG. 8.

Next, each of the plurality of switching circuits506A1-506Angenerates an output terminal voltage (e.g., the voltage between the output terminals212and214if each of the plurality of switching circuits is implemented consistent with the H-bridge200inFIG. 1) based on the four gate inputs received by respective the switching circuit (step1380). The plurality of switching circuits is cascaded such that the switching circuits of the plurality of switching circuits collectively generate the single-phase output signal to the load. More particularly, the switching circuits are cascaded such that the voltage of the singe-phase output signal is equal to the sum of the output terminal voltages of each of the plurality of switching circuits. In one implementation, the plurality of switching circuits may be cascaded in the same manner as the H-bridges106A1-106An,106B1-106Bn, and106C1-106CninFIG. 2.

Next, the multi-level hysteretic controller902determines whether to continue to generate the single-phase output signal (step1318). In one implementation, this determination is made based on whether an external power switch (not shown in the drawings) is in an ON state or an OFF state. If the multi-level hysteretic controller902determines not to continue to generate the single-phase output signal, processing ends. If the multi-level hysteretic controller902determines that the single-phase output signal is to be continued to be generated, processing continues at step1304.

In view of the foregoing teaching, the present invention provides numerous advantages over known systems, articles of manufacture, and methods. For example, one or more embodiments of the present invention remedy the deficiencies of conventional voltage drive systems employing deterministic control. Such systems suffer from a lack of bandwidth when used to synthesize high-frequency waveforms. As a result, the waveforms produced by such conventional voltage drive systems have an unduly high amount of distortion, especially at their peaks and zero crossings. Such waveforms also include clearly-defined tones in the spectra of the voltage and current. Moreover, because of needlessly high switching frequencies at times of high current flow through such conventional voltage drive systems, switching losses are needlessly high. One or more embodiments of the present invention, however, remedy the distortion, tones, and high switching losses of deterministic control systems by providing for appropriate timing of increases and decreases in the switching frequency of the respective single-phase output signal.

Moreover, because the switching frequency is increased at certain times and decreased at others, the same average switching frequency is obtained by voltage drive systems consistent with the present invention as compared to a conventional system employing deterministic control. The hysteretic controller504and the multi-level hysteretic controller902also provide robust current limit capability, improved performance with multiple paralleled systems, inherent ac filter damping because the inductors of the ac filter509appear as current sources, improved overall system stability, improved current control for permanent magnet motors, improved harmonic injection and regulation performance, and improved performance at zero hertz. Yet another benefit provided by one or more embodiments of the present invention is inherent regulation of zero sequence current. Because current regulation is performed completely in the a, b, c reference frame, independent phase current regulation of both differential and common mode components is obtained. This feature has value in cases where voltage drive outputs are directly paralleled without transformer isolation or where a finite impedance exists between the source and load neutrals.