Input/output electrostatic discharge protection for devices with multiple individual power groups

An electrostatic discharge protection system for an integrated circuit device, such as a solid state memory device or any other integrated circuit device having a plurality of individual power groups, includes a loop of an electrically conductive material that is disposed on the device defining a electrostatic discharge path portion, a plurality of first punch-through devices which connect the input/output pins of different power groups of the integrated circuit device to the power sources of the associated power group, and a plurality of second punch-through devices which connect all of the input/output pins of the integrated circuit device to the electrostatic discharge path portion, thereby providing a discharge path that is common to all of the power groups of the integrated circuit device.

FIELD OF THE INVENTION 
The present invention relates to electrostatic discharge protection 
arrangements for integrated circuit devices, and more particularly, to an 
electrostatic discharge protection system and method for protecting 
integrated circuit devices with multiple individual power groups. 
BACKGROUND OF THE INVENTION 
It is well known that during handling and/or testing of the integrated 
circuit devices, electrostatic charges can be applied inadvertently to 
input/output pins of the device, held temporarily and subsequently 
discharged through the device, damaging the device. One method for 
preventing damage to integrated circuit devices from electrostatic 
discharge events (ESD) is to connect protection devices, such as diodes or 
"punch-through" devices, between the input/output pins of the integrated 
circuit device and the power supply circuits of the devices. Such 
protection devices clamp or limit positive and negative potentials applied 
to the input and/or output (I/O) pins to the positive and negative supply 
voltage levels, respectively. However, such arrangements provide 
protection from high voltage electrostatic discharge only for integrated 
circuit devices that provide a common power source for all of the circuits 
on the integrated circuit device. 
To minimize the effects of noise in integrated circuit devices, it is 
common to localize related circuit portions of the integrated circuit 
device into a plurality of individual power groups, each including a 
source of operating voltages for circuit portions of the integrated 
circuit device for that power group. Typically, the individual power 
groups are not located adjacent one another and the power groups are not 
electrically interconnected. Therefore, no intentional electrostatic 
discharge path is provided between the individual I/O pins of different 
power groups of the circuit device. 
If an electrostatic discharge is applied to and held at an input/output pin 
of an integrated circuit device, such as during insertion into or removal 
from a test fixture during testing, for example, the static charge must be 
discharged eternally of the integrated circuit device and the discharge 
current will take the shortest path and being conducted out through an 
external input/output pin of the integrated circuit device. If the first 
pin touched by the input/output pin holding the static charge is not in 
the same power group, usually the static charge will be discharged over a 
path that includes circuit portions of the integrated circuit device, 
causing damage to the integrated circuit device. 
For the reasons stated above, and for other reasons stated below which will 
become apparent to those skilled in the art upon reading and understanding 
the present specification, there is a need in the art for an electrostatic 
discharge protection system for integrated circuit devices that include 
multiple individual power groups. 
SUMMARY OF THE INVENTION 
The present invention provides an electrostatic discharge protection system 
for an integrated circuit device having at least first and second 
individual power groups, each including power supply and at least one 
input/output pin. The protection system includes a first protection 
circuit formed on the integrated circuit interposed between the 
input/output pins and the power supply of the first power group and a 
second protection circuit formed on the integrated circuit interposed 
between the input/output pins and the power supply of the second power 
group. A third protection circuit formed on the integrated circuit 
includes first and second protection devices each having first and second 
terminals, with the first terminal of the first protection device being 
connected to the input/output pin of the first power group and the first 
terminal of the second protection device being connected to the 
input/output pin of the second power group. The second terminals of the 
first and second protection devices are electrically interconnected by 
electrically conductive material providing a discharge path portion that 
is common to at least the power source and the input/output pins of the 
first and second individual power groups. In a preferred embodiment, the 
electrically conductive material is formed on the integrated circuit 
device during the fabrication of the device. 
Further in accordance with the invention, there is provided a method for 
providing electrostatic discharge protection for an integrated circuit 
device having at least first and second power groups having at least one 
input/output pin. The method comprises forming a plurality of first 
protection devices on the integrated circuit device which connect at least 
first and second groups of the input/output pins to the power sources of 
the first and second power groups, respectively; forming a plurality of 
second protection devices on the integrated circuit with the second 
protection devices having terminals connected to all of the input/output 
pins of the first and second groups; and electrically interconnecting 
second terminals of the second protection devices to thereby provide a 
discharge path portion that is common to the power sources and the 
input/output pins of the first and second groups individual power groups 
of the integrated circuit device.

DESCRIPTION OF PREFERRED EMBODIMENTS 
In the following detailed description of the preferred embodiments, 
reference is made to the accompanying drawings that form a part hereof, 
and in which are shown by way of illustration specific embodiments in 
which the invention may be practiced. It is to be understood that other 
embodiments may be utilized and structural changes may be made without 
departing from the scope of the present invention. 
Referring to the drawings, FIG. 1, which is labelled "Prior Art", is a 
schematic representation of an integrated circuit device 100. The 
integrated circuit device 100 can be a DRAM memory system, an SRAM memory 
system or any type of circuit device that has multiple drivers. The 
integrated circuit has four power groups 101-104 which include four power 
sources 111-114 which are individually associated with circuits 115-118, 
respectively, which are produced on a die 108 using conventional 
integrated circuit processing techniques. The integrated circuit device 
100 has sixteen input/output pins 121-136 formed on the upper surface of 
the die 108 and arranged in groups of four pins. Pins 121-124 are in power 
group 101 and pins 125-128 are in power group 102. Pins 129-132 are in 
power group 103 and pins 133-136 are in power group 104. 
The power groups 101-104 are individual in that the power groups are not 
located adjacent to one another and are not electrically interconnected. 
The power source 111 of power group 101 provides voltages V.sub.D1 and 
V.sub.S1 and power source 112 of power group 102 provides voltages 
V.sub.D2 and V.sub.S2. Power source 113 of power group 103 provides 
voltages V.sub.D3 and V.sub.S3 and power source 114 of power group 104 
provides voltages V.sub.D4 and V.sub.S4. The integrated circuit device 
includes a conventional electrostatic protection arrangement for 
protecting the integrated circuit device from electrostatic events. The 
protection arrangement includes four protection circuits 141-144, 
including a protection circuit for each power group. 
Each protection circuit, such as protection circuit 141, includes four 
protection devices 151-154, each including a pair of electrostatic 
discharge punch-through devices 156 and 158, that are interposed between 
the input/output pins of the integrated circuit device and the power 
source of the associated power group. The protection devices clamp 
positive and negative potentials applied to the I/O pins of the integrated 
circuit device to the supply voltage levels V.sub.D1 and V.sub.S1, 
respectively. Each electrostatic discharge punch-through device is a 
bipolar NPN transistor in the exemplary embodiment. Transistor 156 has its 
emitter connected at node 159 to the I/O pin 124 and its collector 
connected to the source of voltage V.sub.D1. The base of transistor 156 is 
connected to a common substrate of the integrated circuit device 100 which 
is turn is connected to a source of a bias signal V.sub.b which can be 
ground potential or a D.C. potential. Transistor 158 has its collector 
connected at node 159 to the I/O pin 124 and its emitter connected to the 
source of voltage V.sub.S1. The base of the transistor 158 is connected to 
the common substrate and thus to bias source V.sub.b. 
The protection arrangement provides protection against ESD events occurring 
at the I/O pins of the integrated circuit device 100. However, because the 
integrated circuit device includes four individual power groups and became 
there is no reference in common between the power groups, no intentional 
paths for electrostatic discharge are provided between the power groups. 
Thus, for example, if an electrostatic discharge is applied to and held at 
input/output pin 124 of the integrated circuit device 100, such as during 
removal of the device from a test fixture during post fabrication testing 
of the integrated circuit device, the static charge must be discharged 
eternally of the integrated circuit device. Also, the discharge current 
will take the shortest path and will be conducted out through an external 
input/output pin of the integrated circuit device. By way of example, it 
is assumed that during reinsertion of the integrated circuit device into a 
test fixture that the first pin touched by the input/output pin 124 that 
is holding the static charge is pin 125, which is not in the same power 
group. The protection circuit 154 associated with input/output pin 124 is 
ineffective. Moreover, became there is no reference in common for 
input/output pins of different power groups, the static charge will be 
discharged over a path that includes pin 125 and the circuit portions of 
the integrated circuit device that are connected to pin 125, causing 
damage to the integrated circuit device. 
Referring to FIG. 2, there is illustrated an integrated circuit device 200 
having a plurality of power groups and which incorporates the ESD 
protection system provided by the invention. The integrated circuit device 
200 can be a DRAM memory system, an SRAM memory system or any type of 
circuit device that has multiple drivers. The ESD protection system of the 
present invention is described with reference to an application in an 
integrated circuit device such as integrated circuit device 100 shown in 
FIG. 1, and elements of the integrated circuit device 200 have been given 
the same reference number as corresponding elements of device 100. 
In accordance with the invention, the protection system of the present 
invention includes protection circuits 141-144. Each protection circuit, 
such as protection circuit 141, includes four protection devices 151-154, 
each including a pair of electrostatic discharge punch-through devices 156 
and 158, that are interposed between the input/output pins of the 
integrated circuit device and the power source of the associated power 
group. The protection devices clamp positive and negative potentials 
applied to the I/O pins of the integrated circuit device to the supply 
voltage levels V.sub.D1 and V.sub.S1, respectively. Each electrostatic 
discharge punch-through device is an NPN transistor in the preferred 
embodiment. However, those skilled in the art will appreciate that the 
electrostatic discharge punch-through devices can be PNP transistors, 
breakdown diodes, silicon controlled switches, or any other suitable 
bipolar device, or field-effect devices, for example. 
The protection system of the present invention further includes four 
protection circuits 211-214 which are interconnected by a closed loop or 
ring of electrically conductive material 216, forming a closed loop 
discharge path portion within the integrated circuit device. Each of the 
four protection circuits 211-214 is individually associated with a 
different one of the power groups 101-104. Each protection circuit 
connects the I/O pins of its associated power group to the conductive loop 
216 so that a reference is provided that is common to all of the power 
groups. The conductive loop 216 is independent of the wiring that supplies 
power to the integrated circuit, and is, thus, unbiased. 
More specifically, referring to FIG. 3, each protection circuit 211-214, 
such as protection circuit 211, includes four punch-through devices 
221-224, each individually associated with a different one of the four I/O 
pins 121-124 of the power group 101. In the exemplary embodiment, each 
protection device, such as protection device 224, is an electrostatic 
discharge punch-through device embodied as an NPN transistor having its 
emitter, which forms one terminal of the device, connected directed at 
node 159 to I/O pin 124. The collector of the transistor, which forms 
another terminal of the device, is electrically connected to the 
conductive loop 216. Such connection is made during fabrication of the 
integrated circuit device. The base of the transistor is formed on the 
common substrate which is connected to bias source V.sub.b, in common with 
the bases of the transistors, such as transistors 156 and 158 (FIG. 1) of 
the protection circuits 141-144. The protection circuits 211-214 are 
formed on the die 208 during the formation of the protection circuits 
141-144 and the other circuits of the integrated circuit device, so that 
no additional process steps are required to provide the protection 
circuits 211-214. 
Referring again to FIG. 2, in the preferred embodiment, the conductive loop 
216 is made of aluminum, or some other electrically conductive material. 
The loop of conductive material is formed on the substrate of the 
integrated circuit device during fabrication of the device and at the time 
that the metal for the "live" circuits is being deposited on the die 208 
so that no additional process steps are required. The location of the loop 
of conductive material is determined in part by the layout of the 
conductors of the "live" circuits and is formed so as to minimize the 
mount of conductive material needed to interconnect all of the protection 
circuits 211-214. The width and thickness of the conductive material 216 
is preferably about the same as the width and thickness as the other metal 
of the "live" circuit of the integrated circuit device 200. It will be 
appreciated by those skilled in the art that the conductive material that 
interconnects the protection circuits 211-214 does not have to be in the 
form of a closed loop and, for example, can be a straight conductor 218 as 
illustrated in FIG. 4, or can have some other configuration. Moreover, the 
collectors of the transistors or the protection circuits 211-214 can be 
connected to pins or terminals (not shown) formed on the die 208 with such 
pins or terminals being connected together by a discrete conductive 
element that is applied to such pins or terminals prior to or after 
passivation of the integrated circuit device. 
For purposes of illustration of the protection system of the present 
invention, it is assumed that while handling the integrated circuit device 
200, such as during testing after fabrication, a static charge is applied 
inadvertently to and held by I/O pin 124 of power group 101. Subsequently, 
the integrated circuit device is to be mounted in a test fixture (not 
shown) having external input/output pins by which power is applied to the 
power groups 101-104 of the integrated circuit device 200. Under normal 
conditions, as the integrated circuit device is mounted in the test 
fixture, the pins of the integrated circuit are aligned so that each of 
the four pin groups is connected to the proper power groups. Thus, 
generally, the static charge will be discharged via protection circuit 154 
to the source of voltage V.sub.D1, (or to the source of the voltage 
V.sub.S1, depending on the polarity of the voltage), and out of the 
integrated circuit device through the external input/output pins of the 
test fixture that connect power to the integrated circuit device. 
If on the other hand, the first pin touched by the I/O pin 124 is pin 125, 
a pin that is in power group 102, for example, the protection device 154 
of the associated protection circuit 142 is ineffective because no 
discharge path can be established to the source of voltage V.sub.D1 or 
voltage V.sub.S1. In such case, the NPN transistor of the protection 
device 224 of protection circuit 211 will conduct, connecting node the 
input/output pin 125 to the discharge loop 216, and the discharge current 
will flow over a discharge path portion that includes pin 125 and 
protection device 154 of protection circuit 211 to the I/O pin 124 of 
power group 101, allowing a discharge path to be completed to the external 
input/output pins of the test fixture. Therefore, the discharge current 
will be conducted from input/output pin 125 to the external input/output 
pin that supplies power to power group 101. As has been indicated, in the 
preferred embodiment, the electrostatic discharge punch-through devices 
221-224 of the protection circuits 211-214 is an NPN transistor in the 
preferred embodiment. However, it is apparent that the electrostatic 
discharge punch-through devices can be PNP transistors, breakdown diodes, 
silicon controlled switches, or any other suitable bipolar device, or 
field-effect devices, for example. 
Conclusion 
Thus, an electrostatic discharge protection system has been described which 
provides an electrostatic discharge protection system for an integrated 
circuit device having a plurality of individual power groups. The 
protection system includes a plurality of electrostatic discharge 
punch-through devices which connect the input/output pins of all of the 
power groups to a common conductive media, providing a electrostatic 
discharge path portion which is common to all of the power groups. Each 
electrostatic discharge punch-through device is an NPN transistor in the 
preferred embodiment. However, those skilled in the art will appreciate 
that the electrostatic discharge punch-through devices can be PNP 
transistors, breakdown diodes, silicon controlled switches, or any other 
suitable bipolar device, or field-effect devices, for example. Moreover, 
in the preferred embodiment, the common electrostatic discharge path 
portion is provided by a closed loop of an electrically conductive 
material that is formed on the integrated circuit device during 
fabrication of the metal for the "live" circuits. However, it will be 
appreciated by those skilled in the art that the conductive material that 
interconnects the protection circuits does not have to be in the form of a 
closed loop and, for example, can be a straight conductor or can have some 
other configuration. Further, the terminals of the punch-through devices 
of the protection circuits can be connected to pins or terminals formed on 
the die with such pins or terminals being connected together by a discrete 
conductive element that is applied to such pins or terminals prior to or 
after passivation of the integrated circuit device. 
The electrostatic discharge protection system has been described with 
reference to a preferred application in an integrated circuit device, such 
as a DRAM memory system, an SRAM memory system or any type of circuit 
device that has multiple drivers, but can be employed in numerous 
applications in many types of integrated circuits. Thus, although specific 
embodiments have been illustrated and described herein, it will be 
appreciated by those of ordinary skill in the art that any arrangement 
which is calculated to achieve the same purpose may be substituted for the 
specific embodiment shown. This application is intended to cover any 
adaptations or variations of the present invention. Therefore, it is 
manifestly intended that this invention be limited only by the claims and 
the equivalents thereof.