Integrated circuit package system with interconnect lock

An integrated circuit package system includes: mounting a device structure over a package carrier; connecting an internal interconnect between the device structure and the package carrier; forming an interconnect lock over the internal interconnect over the device structure with interconnect lock exposing the device structure; and forming a package encapsulation adjacent to the interconnect lock and over the package carrier.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application contains subject matter related to concurrently filed U.S. patent application Ser. No. 11/954,601. The related application is assigned to STATS ChipPAC Ltd.

The present application also contains subject matter related to concurrently filed U.S. patent application Ser. No. 11/954,613. The related application is assigned to STATS ChipPAC Ltd.

The present application further contains subject matter related to concurrently filed U.S. patent application Ser. No. 11/954,603. The related application is assigned to STATS ChipPAC Ltd.

TECHNICAL FIELD

The present invention relates generally to an integrated circuit package system and more particularly to an encapsulated integrated circuit package system.

BACKGROUND ART

In order to interface an integrated circuit with other circuitry, it is common to mount it on a lead frame or substrate. Each integrated circuit has bonding pads that are individually connected to the substrate's contact or terminal pads using extremely fine gold or aluminum wires or conductive balls, such as solder balls. The assemblies are then packaged by individually encapsulating them in molded plastic or ceramic bodies to create an integrated circuit package.

Integrated circuit packaging technology has seen an increase in the number of integrated circuits mounted on a single circuit board or substrate. The new packaging designs are more compact form factors, such as the physical size and shape of a packaged integrated circuit, and providing a significant increase in overall integrated circuit density.

However, integrated circuit density continues to be limited by the “real estate” available for mounting individual integrated circuits on a substrate. Even larger form factor systems, such as personal computers (PC's), compute servers, and storage servers, need more integrated circuits in the same or smaller “real estate”. Particularly acute, the needs for portable personal electronics, such as cell phones, digital cameras, music players, personal digital assistants (PDA's), and location-based devices, have further driven the need for increased integrated circuit density.

This increased integrated circuit density has led to the development of multi-chip packages in which more than one integrated circuit can be packaged. Each package provides mechanical support for the individual integrated circuits and one or more layers of interconnect lines that enable the integrated circuits to be connected electrically to surrounding circuitry.

Current multi-chip packages, also commonly referred to as multi-chip modules, typically consist of a printed circuit board (PCB) substrate onto which a set of separate integrated circuit components are directly attached. Such multi-chip packages have been found to increase integrated circuit density and miniaturization, improve signal propagation speed, reduce overall integrated circuit size and weight, improve performance, and lower costs—all primary goals of the computer industry.

Multi-chip packages whether vertically or horizontally arranged, can also present problems because they usually must be pre-assembled before the integrated circuit and integrated circuit connections can be tested. Thus, when integrated circuits are mounted and connected in a multi-chip module, individual integrated circuits and connections cannot be tested individually, and it is not possible to identify known-good-die (“KGD”) before being assembled into larger circuits. Consequently, conventional multi-chip packages lead to assembly process yield problems. This fabrication process, which does not identify KGD, is therefore less reliable and more prone to assembly defects.

Moreover, vertically stacked integrated circuits in typical multi-chip packages can present problems beyond those of horizontally arranged integrated circuit packages, further complicating the manufacturing process. It is more difficult to test and thus determine the actual failure mode of the individual integrated circuits. Moreover, the substrate and integrated circuit are often damaged during assembly or testing, complicating the manufacturing process and increasing costs.

For both vertical and horizontal multi-chip packages, assembly of the multi-chip packages must have reliable electrical and mechanical attachments between the multiple integrated circuits, the stacked packaged integrated circuits, or a combination thereof. For example, the encapsulating process for forming the packaged integrated circuit may cause contamination, such as mold flash or bleed, impeding reliable attachments. Another example, for integrated circuit packages having a recess in the encapsulation, contoured mold chase are used to form the recess which increases the risk of mold flashes, damage to the package structure from contact with the contoured portion of the mold chase, and the manufacturing cost to design specific mold chase for the desired recess in the encapsulation.

Thus, a need still remains for an integrated circuit package system providing low cost manufacturing, improved yield, improved reliability, and greater flexibility to offer more functionality and fewer footprints on the printed circuit board. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.

DISCLOSURE OF THE INVENTION

The present invention provides an integrated circuit package system including: mounting a device structure over a package carrier; connecting an internal interconnect between the device structure and the package carrier; forming an interconnect lock over the internal interconnect over the device structure with interconnect lock exposing the device structure; and forming a package encapsulation adjacent to the interconnect lock and over the package carrier.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs. Generally, the invention can be operated in any orientation.

For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the integrated circuit, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements. The term “processing” as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and/or removal of the material or as required in forming a described structure. The term “system” as used herein means and refers to the method and to the apparatus of the present invention in accordance with the context in which the term is used.

Referring now toFIG. 1, therein is shown a top view of an integrated circuit package system100in a first embodiment of the present invention. The integrated circuit package system100includes a package encapsulation102, such as an epoxy molding compound, surrounding an interconnect lock104. The interconnect lock104may be formed from with different materials and different structures. For example the interconnect lock104may be a non-conductive epoxy, an encapsulant in a configuration of a dam structure, a sealant, a polymeric material, a resin material, a wire-in-film adhesive, or other equivalent characteristic materials.

The interconnect lock104may form a recess106exposing a device structure108, such as an interposer or a laminated substrate. Contact pads110of the device structure108are also shown exposed in the recess106formed by the interconnect lock104and the package encapsulation102. Components114, such as discrete passive components or an integrated circuit device, are shown mounted over the device structure108.

Referring now toFIG. 2, therein is shown a cross-sectional view of the integrated circuit package system100along line2-2ofFIG. 1. The cross-sectional view depicts an integrated circuit die216mounted over a package carrier218, such as a laminated substrate. First internal interconnects220, such as bond wires or ribbon bond wires, connect the integrated circuit die216and the package carrier218.

An inner encapsulation222, such as an epoxy molding compound, covers the integrated circuit die216and the first internal interconnects220over the package carrier218. The device structure108mounts over the inner encapsulation222with an adhesive224, such as an adhesive film. Second internal interconnects226, such as bond wires or ribbon bond wires, connect the device structure108and the package carrier218.

The interconnect lock104covers a portion of the second internal interconnects226over the device structure108. The interconnect lock104may be deposited over the device structure108. The interconnect lock104may function to mitigate or eliminate wire sweep of the second internal interconnects226inadvertently creating shorts or breaking the mechanical connections of the second internal interconnects226with the device structure108, the package carrier218, or a combination thereof.

The interconnect lock104is not formed to follow the contour of the second internal interconnects226over the device structure108. The interconnect lock104may be formed at the periphery of the device structure108covering the second internal interconnects226without requiring detailed location information of the second internal interconnects226allowing use of lower cost manufacturing equipments without require additional processing of the second internal interconnects226thereby reducing manufacturing steps, complexity, and cost.

It has been discovered that the present invention provides the integrated circuit package system having the interconnect lock with improved yield and lower cost manufacturing. The interconnect lock prevents or mitigates wire sweeps or connection breakage of the bond wires by holding the bond wires in place. This improves manufacturing yield. The application of the interconnect lock is around the peripheral portion of the interposer and the bond wires over the interposer without requiring precision locations of the bond wires or preprocessed bond wires having reinforcements. This reduces the manufacturing cost.

The package encapsulation102covers the second internal interconnects226and the inner encapsulation222over the package carrier218. The package encapsulation102partially covers the interconnect lock104and the device structure108such that the recess106of the interconnect lock104exposes the device structure108. The components114are shown mounted over the device structure108. External interconnects228, such as solder balls, may attach to and below the package carrier218.

Referring now toFIG. 3, therein is a cross-sectional view of an integrated circuit package system300exemplified by the top view ofFIG. 1in a second embodiment of the present invention. The integrated circuit package system300includes structural similarities to the integrated circuit package system100ofFIG. 2. The cross-sectional view depicts an integrated circuit die316mounted over a package carrier318, such as a laminated substrate. First internal interconnects320, such as bond wires or ribbon bond wires, connect the integrated circuit die316and the package carrier318.

An inner encapsulation322, such as an epoxy molding compound, covers the integrated circuit die316and the first internal interconnects320over the package carrier318. A device structure308, such as an interposer or a laminated substrate, mounts over the inner encapsulation322with an adhesive324, such as an adhesive film. Second internal interconnects326, such as bond wires or ribbon bond wires, connect the device structure308and the package carrier318.

An interconnect lock304, such as a wire-in-film, covers a portion of the second internal interconnects326over the device structure308. The interconnect lock304may be deposited over the device structure308. The interconnect lock304may be formed in a configuration of a dam structure. The interconnect lock304may function to mitigate or eliminate wire sweep of the second internal interconnects326inadvertently creating shorts or breaking the mechanical connections of the second internal interconnects326with the device structure308, the package carrier318, or a combination thereof.

The interconnect lock304is not formed to follow the contour of the second internal interconnects326over the device structure308. The interconnect lock304may be formed at the periphery of the device structure308covering the second internal interconnects326without requiring detailed location information of the second internal interconnects326allowing use of lower cost manufacturing equipments without require additional processing of the second internal interconnects326thereby reducing manufacturing steps, complexity, and cost.

A package encapsulation302covers the second internal interconnects326and the inner encapsulation322over the package carrier318. The package encapsulation302is preferably adjacent to the interconnect lock304and partially covers the device structure308. A recess306of the interconnect lock304exposes the device structure308. External interconnects328, such as solder balls, may attach to and below the package carrier318.

Referring now toFIG. 4, therein is shown a top view of an integrated circuit package system400in a third embodiment of the present invention. The integrated circuit package system400includes a package encapsulation402, such as an epoxy molding compound, surrounding an interconnect lock404. The interconnect lock404may be formed from with different materials and different structures. For example the interconnect lock404may be a non-conductive epoxy, an encapsulant in a dam structure, a sealant, a polymeric material, a resin material, a wire-in-film adhesive, or other equivalent characteristic materials. The interconnect lock404may form a recess406exposing a device structure408, such as an image or sensor integrated circuit.

Referring now toFIG. 5, therein is shown a cross-sectional view of the integrated circuit package system400along line5-5ofFIG. 4. The cross-sectional view depicts an integrated circuit die516mounted over a package carrier518, such as a laminated substrate. First internal interconnects520, such as bond wires or ribbon bond wires, connect the integrated circuit die516and the package carrier518.

An inner encapsulation522, such as an epoxy molding compound, covers the integrated circuit die516and the first internal interconnects520over the package carrier518. The device structure408mounts over the inner encapsulation522with an adhesive524, such as a die-attach adhesive or an adhesive film, in between. Second internal interconnects526, such as bond wires or ribbon bond wires, connect the device structure408and the package carrier518.

The interconnect lock404covers a portion of the second internal interconnects526over the device structure408. The interconnect lock404may be deposited over the device structure408. The interconnect lock404may function to mitigate or eliminate wire sweep of the second internal interconnects526inadvertently creating shorts or breaking the mechanical connections of the second internal interconnects526with the device structure408, the package carrier518, or a combination thereof.

The interconnect lock404is not formed to follow the contour of the second internal interconnects526over the device structure408. The interconnect lock404may be formed at the periphery of the device structure408covering the second internal interconnects526without requiring detailed location information of the second internal interconnects526allowing use of lower cost manufacturing equipments without require additional processing of the second internal interconnects526thereby reducing manufacturing steps, complexity, and cost.

It has been discovered that the present invention provides the integrated circuit package system having the interconnect lock with improved yield and lower cost manufacturing. The interconnect lock protects the integrated circuit device from compression forces found typically with contoured mold chase to form the recess. This improves manufacturing yield and reduces the manufacturing cost.

The package encapsulation402covers the second internal interconnects526and the inner encapsulation522over the package carrier518. The package encapsulation402partially covers the interconnect lock404and the device structure408such that the recess406of the interconnect lock404exposes the device structure408. External interconnects528, such as solder balls, may attach to and below the package carrier518.

Referring now toFIG. 6, therein is shown a cross-sectional view of the integrated circuit package system100ofFIG. 1in a step for molding an intermediate structure. The interconnect lock104allows using of fine wires for the second internal interconnects226without wire sweep. The interconnect lock104can serve as a dam to prevent mold flash contamination of the contact pads110of the device structure108.

The interconnect lock104may cushion the clamping force from a mold chase602during molding process and thus prevents damage to the electrical layers of the device structure108or the device structure408ofFIG. 5. The interconnect lock104also includes resilient properties to compensate for coplanarity errors due to package structure tilting during assembly process.

The ability to use the mold chase602of a flat panel-standard instead of having dedicated contoured or cavity-type mold chase improves productivity and lowers tooling cost. The mold chase602of the flat panel-standard also allows mounting of passive components and/or thin profile devices onto the device structure108prior to the molding process further simplifying the manufacturing process, increasing productivity, and reducing cost.

Referring now toFIG. 7, therein is shown a flow chart of an integrated circuit package system700for manufacturing the integrated circuit package system100in an embodiment of the present invention. The system700includes mounting a device structure over a package carrier in a block702; connecting an internal interconnect between the device structure and the package carrier in a block704; forming an interconnect lock over the internal interconnect over the device structure with interconnect lock exposing the device structure in a block706; and forming a package encapsulation adjacent to the interconnect lock and over the package carrier in a block708.

Thus, it has been discovered that the integrated circuit package system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for improving yield, increasing reliability, and reducing cost of circuit system. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.