Supporting partial recycle in a pipelined microprocessor

A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.

BACKGROUND OF THE INVENTION

This invention relates generally to partial instruction recycling in a pipelined microprocessor, and more particularly to providing virtual instruction packets for supporting performance features of a microprocessor during partial instruction recycling.

Speculative execution is performed by some microprocessors to optimize performance. Speculative execution executes subsequent instructions before a first instruction completes in hopes that the early results of the first instruction are resolved to be correct.

Performing speculative execution in conjunction with a recycle mechanism minimizes the effect of execution dependencies. In one example, speculation may be performed on a result of data cache (DCache) access. In the case where the speculation is incorrect (a DCache miss), the instruction is repeated or recycled. This method allows for a performance gain over always stalling the pipeline until the result (e.g. fetched DCache data address) of an operation is known for certain. To recycle the instruction, a side recycle queue maintains a copy of the instruction for pending instructions until the instruction is past a certain recycle point.

For further optimization, partial recycles can be performed on operations of a multicycle instruction. For example, when a reject operation occurs in the middle of processing a multicycle instruction, the rejected operation is repeated from the point of the reject. This advantageous over restarting the entire instruction, and sometimes needed for forward progress, where a multi-cycle instruction may be interrupted/rejected many times during execution. This partial restart can not be supported by the information in the recycle queue which only supports full recycle and would have been removed at this point. The processing elements that are dependent on the instruction information from the recycle queue are unable to operate.

It would be advantageous to be able to maintain instruction information for use by processing elements such as, Address Generation Interlock (AGI) and Reliability, Availability, and Serviceability (RAS) checking.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment includes a computer processing system. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.

Another exemplary embodiment includes a method of processing instructions. The method includes writing a subset of information to a first datastore based on an execution of an operation associated with a processor instruction; and initiating reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.

A further exemplary embodiment includes a computer program product for processing instructions. The computer program product includes a computer-readable storage medium for storing instructions for executing instruction processing. The instruction processing includes a method of: writing a subset of information to a first datastore based on an execution of an operation associated with a processor instruction; and initiating reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.

Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

An exemplary embodiment of the present invention provides tracking a virtual packet relating to a partially recycled operation of an instruction through a pipeline of a processor. The virtual packet stores information to enable AGI and RAS checking to be performed on the instruction before completion of the instruction.

Turning now toFIG. 1, a block diagram illustrates an exemplary computing system100that includes a partial recycle support system in accordance with the present disclosure. The computing system100is shown to include a computer101. As can be appreciated, the computing system100can include any computing device, including but not limited to, a desktop computer, a laptop, a server, a portable handheld device, or any other electronic device. For ease of the discussion, the disclosure will be discussed in the context of the computer101.

The computer101is shown to include a processor102, memory104coupled to a memory controller106, one or more input and/or output (I/O) devices108,110(or peripherals) that are communicatively coupled via a local input/output controller112, and a display controller114coupled to a display116. In an exemplary embodiment, the system100can further include a network interface118for coupling to a network120. The network120transmits and receives data between the computer101and external systems. In an exemplary embodiment, a conventional keyboard122and mouse124can be coupled to the input/output controller112.

In various embodiments, the memory104stores instructions that can be executed by the processor102. The instructions stored in memory104may include one or more separate programs, each of which comprises an ordered listing of executable instructions for implementing logical functions. In the example ofFIG. 1, the instructions stored in the memory104include a suitable operating system (OS)126. The operating system126essentially controls the execution of other computer programs and provides scheduling, input-output control, file and data management, memory management, and communication control and related services.

When the computer101is in operation, the processor102is configured to execute the instructions stored within the memory104, to communicate data to and from the memory104, and to generally control operations of the computer101pursuant to the instructions. The processor102can be any custom made or commercially available processor, a central processing unit (CPU), an auxiliary processor among several processors associated with the computer101, a semiconductor based microprocessor (in the form of a microchip or chip set), a macroprocessor, or generally any device for executing instructions. The processor102includes the partial recycle systems and methods as described herein.

Turning now toFIG. 2, the processor102ofFIG. 1is illustrated in accordance with an exemplary embodiment. The processor102includes one or more pipeline stages. In various embodiments, the processor102may support multiple pipeline paths for instruction execution, e.g., a superscaler architecture. For ease of the discussion, the disclosure will be discussed in the context of single pipeline path as illustrated inFIG. 2.

As shown inFIG. 2, the pipeline stages can include, but are not limited to, an instruction fetch stage210, a decode stage214, a group and dispatch stage216, an address generation (AGEN) and data cache access stage218, an execution stage222, a recycle stage226, and a writeback stage228. As can be appreciated, the operations of the pipeline stages can be combined and/or further partitioned into other pipeline stages, not shown.

In various embodiments, the instruction fetch stage210acquires instructions to be processed from an instruction cache212and passes the instructions to the instruction decode stage214. The instruction decode stage214performs full instruction decodes, generating instruction processing information which is passed to the group and dispatch stage216. The group and dispatch stage216groups and detects dependencies (e.g., AGI) and passes the instructions in a stream to the AGEN and cache access stage218once these dependencies have been resolved. To facilitate reprocessing of an instruction, if needed, the group and dispatch stage stores the instructions in a recycle queue217. The recycle queue217can be, for example, an X deep (e.g., X=ten) entry recycle queue such that the instruction information is preserved until the instruction passes through the execution stage222.

The AGEN and cache access stage218calculates an address of a data cache220, performs data cache access operations (e.g., fetch and store), performs cache data formatting, and routes the information to the execution stage222. The execution stage222performs the function of the instructions based on the data from the data cache220. The execution stage222further stores instruction information in a virtual packet224to assist with partial recycling of a multicycle instruction.

The recycle stage226determines whether the execution is rejected and if rejected, whether a partial recycle or a full recycle is needed. A full recycle is needed, for example, when a data cache access occurs on a single cycle operation. A partial recycle is needed, for example, when a data cache miss occurs sometime after the first cycle/access of a multicycle operation. If a recycle is needed, the instruction is re-processed through the pipeline stages using the information stored in either the recycle queue217or the virtual packet224. If a recycle is not needed, the recycle stage226can remove the instruction information from the recycle queue217. Once the instruction has completed processing, the writeback stage228writes the results of the execution to one or more registers and performs RAS checking.

In one example, when a full recycle is needed, the entire instruction is recycled. The instruction is acquired from the recycle queue217and used by the group and dispatch stage216to initiate reprocessing of the instruction. In another example, when a partial recycle is needed, the instruction is recycled from the reject point (i.e., only the rejected operation is recycled). The instruction information stored in the virtual packet224is used by the group and dispatch stage216to initiate reprocessing of the operation. The virtual packet224maintains the processing information for the remainder of the processing of the instruction, allowing any instruction dependent features to operate during or after the partial recycle. Such features can include, but are not limited to, AGI and RAS checking.

Turning now toFIG. 3, in one example, the virtual packet224stores information including, but not limited to, a validity indicator, an instruction type, an instruction state, parity information, and general purpose register (GPR) information. As shown inFIG. 3, an exemplary embodiment stores a packet valid bit (VB)310, an instruction type (IT)312, an instruction type parity (ITP)313, an instruction state (IS)314, an instruction state parity (ISP)316, a general purpose register target (GPRT)318, a general purpose register parity (GPRP)320, a general purpose register write upper indicator (GPRU)322, a general purpose register write lower indicator (GPRL)324, a general purpose register write pair indicator (GPRPR)326, and an AGI type (AGIT)328.

The valid bit310can be a single bit indicating the validity of the data in the packet and can trigger partial recycle action on this data by the group and dispatch stage216(FIG. 2). The instruction type312can be multiple bits (e.g., 4 bits) that indicate the type of instruction and can, for example, differentiate functional units (e.g. fixed-point vs. floating-point) used to execute the remainder of the instruction. The instruction state314can be multiple bits (e.g. 4 bits) that indicate the state of the instruction at the point of partial recycle, creating expectations as to the processing of the instruction once operation restarts. This could include the number of execution cycles that have elapsed or that remain. The general purpose register information, GPRT318, GPRU320, and GPRL322, specify the register and section (e.g., upper and/or lower 32-bits) that will be updated by the partially recycled instruction. This is utilized by the Address Generation Interlock (AGI) logic in conjunction with the AGIT328to facilitate the tracking of targets through the processor pipeline. There parity information, ITP313, ISP316, and GPRP320, are stored together with the associated fields to provide RAS checking coverage in case there is a bit-flip error in any of the fields of the packet.

Turning now toFIG. 4, a flowchart illustrates a partial recycle support method in accordance with an exemplary embodiment. As can be appreciated in light of the disclosure, the order of operation within the method is not limited to the sequential execution as illustrated inFIG. 4, but may be performed in one or more varying orders as applicable and in accordance with the present disclosure. In various embodiments, the method may be scheduled to run based on certain events and/or scheduled to run continually during processor operation.

In one example, the method may begin at400. The instructions are grouped and AGI checking and resolution is performed at402. Upon dispatch of the instructions at404, the instruction is stored in the recycle queue217(FIG. 2) at406. Address generation, and data cache accesses are performed at408. The function of the instruction is executed at410. After each cycle of execution, the instruction information as discussed above is stored in the virtual packet224(FIG. 2) at412in preparation for a potential partial recycle from that point.

If, however, the execution of the operation is rejected as detected at414and the instruction requires a full recycle at416, the instruction from the recycle queue217(FIG. 2) is retrieved at418and re-processing of the entire instruction is performed at402-412. If the execution of the operation is rejected at414and the instruction does not require a full recycle rather, but instead a partial recycle at416, the information stored in the virtual packet224(FIG. 2) is retrieved at420and re-processing is performed based on the virtual packet information at402-412at the point of reject.

If the execution of the operation is not rejected at414, however, and the operation being processed is the head or front of the instruction, the instruction is removed from the recycle queue217(FIG. 2) as the instruction can no longer be fully recycled at424and the instruction is evaluated to determine if the processing is complete at426. If the processing is complete at426, RAS checking is performed at428and the write to a register is performed at430. Thereafter, the method may end at432. If, however, the processing is not complete (e.g., a multicycle instruction) at426, further processing is performed at408-412.