Semiconductor device and method therefor including multiple cap layers with amorphous layer

A semiconductor crystal substrate includes a substrate, a first semiconductor layer including a nitride semiconductor and formed over the substrate, a second semiconductor layer including a nitride semiconductor and formed over the first semiconductor layer, a first cap layer formed on the second semiconductor layer, and a second cap layer formed on the first cap layer. Each of the first semiconductor layer and the second semiconductor layer has a single-crystal structure, the first cap layer has one of a single-crystal structure and a polycrystalline structure, and the second cap layer has an amorphous structure.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of Japanese Patent Application No. 2015-213395 filed on Oct. 29, 2015, the entire contents of which are incorporated herein by reference.

FIELD

An aspect of this disclosure relates to a semiconductor crystal substrate, a semiconductor device, a method for producing the semiconductor crystal substrate, and a method for producing the semiconductor device.

BACKGROUND

Application of nitride semiconductors having a high saturation electron velocity and a wide band gap to high-withstand-voltage, high-power semiconductor devices is being considered. For example, GaN, which is a nitride semiconductor, has a band gap of 3.4 eV that is greater than the band gap 1.1 eV of Si and the band gap 1.4 eV of GaAs, and has a high breakdown field strength. For this reason, a nitride semiconductor such as GaN is a very promising material for a high-voltage-operation, high-power semiconductor device for a power supply.

Many reports have been made on field effect transistors, particularly, high electron mobility transistors (HEMT), which are examples of semiconductor devices using nitride semiconductors. For example, as a GaN HEMT, an AlGaN/GaN HEMT, which uses GaN as an electron transit layer and AlGaN as an electron supply layer, is getting attention. In an AlGaN/GaN HEMT, distortion occurs in AlGaN due to a difference between the lattice constants of GaN and AlGaN. The distortion causes piezoelectric polarization and a spontaneous polarization difference of AlGaN, which in turn generate a high-density two-dimensional electron gas (2DEG).

Development of InAlN/GaN HEMTs using InAlN as the electron supply layer has been active in recent years. An InAlN/GaN HEMT has a performance that surpasses the performance of a HEMT using AlGaN as the electron transit layer. In an InAlN/GaN HEMT, the lattice matching between In and GaN can be achieved and a high-quality crystal film can be obtained by setting the composition ratio of In at 17 to 18%. Also, when InAlN is formed with such a composition ratio, the formed InAlN has very high spontaneous polarization. Therefore, an InAlN/GaN HEMT can generate a two-dimensional electron gas (2DEG) having a density that is two to three times greater than the density of the two-dimensional electron gas generated by an AlGaN/GaN HEMT using AlGaN as an electron transit layer. For the above reasons, HEMTs using InAlN as the electron supply layer are getting attention as next-generation high-power devices (see, for example, Japanese Laid-Open Patent Publication No. 2013-89970 and Japanese Laid-Open Patent Publication No. 2013-33877).

SUMMARY

According to an aspect of this disclosure, there is provided a semiconductor crystal substrate that includes a substrate, a first semiconductor layer including a nitride semiconductor and formed over the substrate, a second semiconductor layer including a nitride semiconductor and formed over the first semiconductor layer, a first cap layer formed on the second semiconductor layer, and a second cap layer formed on the first cap layer. Each of the first semiconductor layer and the second semiconductor layer has a single-crystal structure, the first cap layer has one of a single-crystal structure and a polycrystalline structure, and the second cap layer has an amorphous structure.

DESCRIPTION OF EMBODIMENTS

Compared with GaAs HEMTs, AlGaN/GaN HEMTs and InAlN/GaN HEMTs have very high gate leakage currents. This is particularly true in the case of InAlN/GaN HEMTs.

Accordingly, there is a demand for a semiconductor device using nitride semiconductors and having a low gate leakage current.

Embodiments of the present invention are described below with reference to the accompanying drawings. The same reference numbers are assigned to the same components throughout the drawings, and repeated descriptions of those components are omitted.

First, a gate leakage current in a HEMT using nitride semiconductors is described. A HEMT ofFIG. 1includes a substrate910, and a buffer layer911, an electron transit layer921, and an electron supply layer922that are stacked on the substrate910and include nitride semiconductors.

A gate electrode931, a source electrode932, and a drain electrode933are formed on the electron supply layer922. The electron transit layer921is formed of GaN, and the electron supply layer922is formed of, for example, AlGaN or InAlN. In the HEMT with this configuration, a 2DEG921ais generated in the electron transit layer921near the interface between the electron transit layer921and the electron supply layer922. The electron density of the generated 2DEG921ain the case where the electron supply layer922is formed of InAlN is greater than that in the case where the electron supply layer922is formed of AlGaN.

A gate leakage current is generated when a negative voltage is applied to the gate electrode931with respect to the source electrode932, and electrons flow from the gate electrode931in the direction indicated by an arrow A inFIG. 1.FIG. 2is a graph illustrating a relationship between a gate voltage and the current density of a gate leakage current. InFIG. 2, a characteristic2A indicates the characteristic of a HEMT including an electron supply layer formed of AlGaN, and a characteristic2B indicates the characteristic of a HEMT including an electron supply later formed of InAlN. As illustrated inFIG. 2, the gate leakage current indicated by the characteristic2B of the HEMT including the electron supply layer formed of InAlN is about five orders of magnitude greater than the gate leakage current indicated by the characteristic2A of the HEMT including the electron supply layer formed of AlGaN. When the gate leakage current is large, the long-term reliability, the withstand voltage, and the operation efficiency of a device may be reduced.

Crystalline AlN has a wide band gap and can function as an insulating film. In a semiconductor device illustrated byFIG. 3, a cap layer923is formed with single-crystal AlN on the electron supply layer922and the gate electrode931is formed on the cap layer923to reduce the leakage current. The semiconductor device ofFIG. 3also includes a spacer layer924between the electron transit layer921and the electron supply layer922. The spacer layer924is formed of AlN, and the electron supply layer922is formed of InAlGaN.

FIG. 4is a graph illustrating a relationship between a gate voltage and the current density of a gate leakage current. InFIG. 4, a characteristic4A indicates the characteristic of a HEMT including the cap layer923formed of single-crystal AlN, and a characteristic4B indicates the characteristic of a HEMT including no cap layer. That is, the characteristic4B indicates the characteristic of a HEMT having a configuration as illustrated byFIG. 5where no cap layer is formed and the gate electrode931is formed on the electron supply layer922. As illustrated byFIG. 4, the gate leakage current indicated by the characteristic4A of the HEMT including the cap layer923formed of single-crystal AlN is not greatly different from the gate leakage current indicated by the characteristic4B of the HEMT including no cap layer, and is even greater than the gate leakage current indicated by the characteristic4B at a high voltage.

This is because when the cap layer923of single-crystal AlN is formed on the electron supply layer922of InAlGaN, the barrier performance of the cap layer923is reduced due to the polarization electric field. That is, when single-crystal AlN with a wide band gap is used for the cap layer923, although a high Schottky barrier height φbcan be achieved as illustrated inFIG. 6, the barrier shape of the cap layer923is greatly distorted into a triangular shape due to an extremely strong polarization electric field. For this reason, the effective barrier performance of the cap layer923is greatly reduced. In single-crystal AlN, the polarization electric field increases due to strong spontaneous polarization of the single-crystal AlN itself, tensile distortion resulting from the single-crystalline structure of AlN, and piezoelectric polarization caused by the tensile distortion. Thus, the gate leakage current cannot be reduced by using the cap layer923formed of single-crystal AlN.FIG. 6illustrates a band structure indicating the Fermi level of the gate electrode931, the cap layer923, and the bottoms of conduction bands of the electron supply layer922and the electron transit layer921. InFIG. 6, the spacer layer924is omitted for brevity.

Next, the characteristics of polycrystalline AlN and amorphous AlN are described.FIG. 7is a graph illustrating a relationship between a voltage and the current density of a current (leakage current) that flows when the voltage is applied in the film thickness direction to each of a polycrystalline AlN film and an amorphous AlN film. InFIG. 7, a characteristic7A indicates the characteristic of the polycrystalline AlN film, and a characteristic7B indicates the characteristic of the amorphous AlN film. As illustrated inFIG. 7, the current that flows through the polycrystalline AlN film indicated by the characteristic7A is greater than the current that flows through the amorphous AlN film indicated by the characteristic7B. For example, in a comparatively-high voltage range between 15 V and 25 V, the current that flows through the polycrystalline AlN film is about eight orders of magnitude greater than the current that flows through the amorphous AlN film. Thus, a larger amount of leakage current flows through the polycrystalline AlN film when a voltage is applied. This is supposed to be due to the presence of crystalline interfaces in polycrystalline AlN.

As described above, through experiments, the inventors of the present invention have found out that a cap layer needs to be formed of amorphous AlN to reduce the gate leakage current. However, when the cap layer923of amorphous AlN is formed directly on the electron supply layer922of single-crystal InAlGaN, defects tend to be formed at the interface between the electron supply layer922and the cap layer923. This is due to the differences in materials and crystal structures between the electron supply layer922and the cap layer923. That is, it is assumed that defects are formed because both the continuity of the crystal structure and the continuity of the material are broken at the interface between the electron supply layer922and the cap layer923. If many defects are formed at the interface, electrons are trapped by the defects and a current collapse phenomenon tends to occur.

First Embodiment

Next, a semiconductor device according to a first embodiment is described. As illustrated byFIG. 8, the semiconductor device of the first embodiment includes a substrate10, and a nucleation layer (not shown), a buffer layer11, an electron transit layer21, a spacer layer22, an electron supply layer23, a first cap layer24, and a second cap layer25that are formed on the substrate10. A gate electrode31is formed on the second cap layer25, and a source electrode32and a drain electrode33are formed on the electron supply layer23. In the present application, a semiconductor crystal substrate may indicate a structure where the nucleation layer (not shown), the buffer layer11, the electron transit layer21, the spacer layer22, the electron supply layer23, the first cap layer24, and the second cap layer25are formed on the substrate10. Also in the present application, the electron transit layer21may be referred to as a “first semiconductor layer”, the electron supply layer23may be referred to as a “second semiconductor layer”, and the spacer layer22may be referred to as a “third semiconductor layer”.

The substrate10may be implemented by an Si substrate. However, the substrate10may instead be formed of SiC, sapphire, or GaN. The nucleation layer may be formed of AlN and have a thickness of about 160 nm. The buffer layer11may be formed of AlGaN. The electron transit layer21may be formed of i-GaN and have a thickness of about 3 μm. The spacer layer22may be formed of AlN and have a thickness of about 1 μm. The electron supply layer23may be formed of InAlGaN and have a thickness of about 10 μm. The electron supply layer23may instead be formed of InAlN or AlGaN. With this configuration, a 2DEG21ais generated in the electron transit layer21near the interface between the electron transit layer21and the spacer layer22.

The first cap layer24may be formed of single-crystal or polycrystalline AlN and have a thickness of about 2 nm. The second cap layer25may be formed of amorphous AlN and have a thickness of about 4 nm. The thickness of the first cap layer24is preferably greater than or equal to 1 nm and less than or equal to 3 nm. The thickness of the second cap layer25is preferably greater than or equal to 2 nm and less than or equal to 5 nm. Also, the thickness of the second cap layer25is preferably greater than the thickness of the first cap layer24. If the first cap layer24and the second cap layer25are too thick, their high frequency characteristics are reduced. Therefore, the thicknesses of the first cap layer24and the second cap layer25are preferably small. On the other hand, the first cap layer24and the second cap layer25need to have certain thicknesses so that the continuity of the crystal structure of the first cap layer24can be maintained and a desired insulation performance of the second cap layer25can be achieved. For these reasons, the thicknesses of the first cap layer24and the second cap layer25are preferably within the above ranges.

The first cap layer24may be formed of a material that has a band gap wider than the band gap of the electron supply layer23and has a single-crystal or polycrystalline structure. For example, the first cap layer24may be formed of an oxide, a nitride, or an oxynitride such as Al2O3, SiN, or SiO2. The second cap layer25may be formed of a material that has a band gap wider than the band gap of the electron supply layer23and has an amorphous structure. For example, the second cap layer25may be formed of an oxide, a nitride, or an oxynitride such as Al2O3, SiN, or SiO2. To maintain the continuity between the first cap layer24and the second cap layer25, the first cap layer24and the second cap layer25are preferably formed of the same material. Also, the first cap layer24and the second cap layer25are preferably formed of AlN including elements that are the same as elements included in the electron supply layer23.

Nitride semiconductor films including the nucleation layer (not shown), the buffer layer11, the electron transit layer21, the spacer layer22, the electron supply layer23, the first cap layer24, and the second cap layer25are formed by metal organic chemical vapor deposition (MOCVD).

Next, a gate leakage current in the semiconductor device of the first embodiment is described.FIG. 9is a graph illustrating a relationship between a gate voltage and the current density of a gate leakage current. InFIG. 9, a characteristic9A indicates the characteristic of a HEMT that is the semiconductor device of the first embodiment, and a characteristic4B indicates the characteristic of a HEMT of a comparative example that includes no cap layer. As illustrated inFIG. 9, the gate leakage current indicated by the characteristic9A of the HEMT of the first embodiment is about four orders of magnitude less than the gate leakage current indicated by the characteristic4B of the HEMT including no cap layer.

This is because amorphous AlN forming the second cap layer25has a low crystal orientation, and both of spontaneous polarization and piezoelectric polarization disappear from the second cap layer25. Accordingly, as illustrated inFIG. 10, the barrier shape of the second cap layer25is not greatly distorted into a triangular shape, and the original Schottky barrier height φbof AlN is maintained. Thus, the second cap layer25can dramatically reduce the electron tunneling probability, and the gate leakage current of the semiconductor device of the first embodiment can be reduced.FIG. 10illustrates a band structure indicating the Fermi level of the gate electrode31, the second cap layer25, the first cap layer24, and the bottoms of conduction bands of the electron supply layer23and the electron transit layer21. InFIG. 10, the spacer layer22is omitted for brevity.

Next, a current collapse phenomenon in the semiconductor device of the first embodiment is described.FIG. 11is a graph illustrating a relationship (Ids−Vdscharacteristics) between a drain voltage and a drain current of the semiconductor device of the first embodiment.FIG. 12is a graph illustrating a relationship (Ids−Vdscharacteristics) between a drain voltage and a drain current of the semiconductor device ofFIG. 5that includes no cap layer.FIGS. 11 and 12illustrate the Ids−Vdscharacteristics for each of the cases where a gate voltage Vgis 0 V and −2 V. InFIGS. 11 and 12, a solid line indicates a characteristic obtained by direct-current voltage measurement (DC measurement) and ◯ indicates a characteristic obtained by pulse measurement. In the pulse measurement, the characteristic is measured by instantaneously changing the voltage from a stress bias to a measurement voltage. The stress bias is set at “off stress”, Vgsis set at −5 V, and Vdsis set at 50 V for the measurement. It can be determined that the current collapse phenomenon is more effectively suppressed as the difference between the current measured by the DC measurement and the current measured by the pulse measurement becomes smaller (the current measured by the pulse measurement is less than the current measured by the DC measurement).

As illustrated byFIG. 11, in the case of the semiconductor device of the first embodiment, the difference between the current measured by the DC measurement and the current measured by the pulse measurement is very small. On the other hand, as illustrated byFIG. 12, in the case of the semiconductor device ofFIG. 5including no cap layer, the difference between the current measured by the DC measurement and the current measured by the pulse measurement is large. Accordingly, compared with the semiconductor device ofFIG. 5including no cap layer, the current collapse phenomenon is more effectively suppressed in the semiconductor device of the first embodiment.

It is supposed that the current collapse phenomenon is suppressed because at least one of the continuity of the crystal structure and the continuity of the material is maintained at the interface between the electron supply layer23and the first cap layer24and at the interface between the first cap layer24and the second cap layer25. That is, at the interface between the electron supply layer23and the first cap layer24, although the continuity of the material is broken, the continuity of the crystal structure is maintained. Also, at the interface between the first cap layer24and the second cap layer25, although the continuity of the crystal structure is broken, the continuity of the material is maintained. Maintaining at least one of the continuity of the crystal structure and the continuity of the material at an interface makes it possible to reduce defects formed at the interface, to greatly reduce electrons trapped by the defects, and to suppress the current collapse phenomenon.

<Method of Producing Semiconductor Device>

Next, an exemplary method of producing a semiconductor device according to the first embodiment is described with reference toFIGS. 13A through 14C. In the method of producing the semiconductor device of the first embodiment, nitride semiconductor films are formed by epitaxial growth on the substrate10such as a silicon substrate. The semiconductor device produced here includes nitride semiconductor films formed by MOCVD and also includes a passivation film. In forming nitride semiconductor films by MOCVD, trimethylindium (TMI) is used as a source gas for In, trimethylaluminum (TMA) is used as a source gas for Al, and trimethylgallium (TMG) is used as a source gas for Ga. Also, ammonia (NH3) is used as a source gas for N.

First, as illustrated byFIG. 13A, the nucleation layer (not shown), the buffer layer11, the electron transit layer21, the spacer layer22, the electron supply layer23, the first cap layer24, and the second cap layer25are sequentially formed with nitride semiconductors on the substrate10such as a semi-insulating SiC substrate. As a result, a semiconductor crystal substrate of the first embodiment is produced.

The nucleation layer is formed by growing an AlN film with a thickness of about 160 nm under the conditions of a substrate temperature of about 1000° C., a V/III ratio between 1000 and 2000, and a pressure of about 50 Torr in the chamber of a MOCVD apparatus. At this step, TMA and NH3are supplied into the chamber of the MOCVD apparatus.

The buffer layer11is formed by growing an AlGaN film with a thickness of about 500 nm under the conditions of a substrate temperature of about 1000° C., a V/III ratio between 500 and 1000, and a pressure of about 50 Torr in the chamber of the MOCVD apparatus. At this step, TMA, TMG, and NH3are supplied into the chamber of the MOCVD apparatus. The buffer layer11may also be formed by stacking three AlGaN films with different composition ratios. For example, by adjusting the amounts of TMA and TMG supplied into the chamber, an Al0.8Ga0.2N film, and Al0.5Ga0.5N film, and an Al0.2Ga0.8N film may be sequentially formed and stacked.

The electron transit layer21is formed by growing a GaN film with a thickness of about 3 μm under the conditions of a substrate temperature of about 1000° C., a V/III ratio between 500 and 3000, and a pressure of about 200 Torr in the chamber of the MOCVD apparatus. At this step, TMG and NH3are supplied into the chamber of the MOCVD apparatus.

The spacer layer22is formed by supplying TMA and NH3into the chamber of the MOCVD apparatus and thereby growing an AlN film with a thickness of about 1 nm.

The electron supply layer23is formed by growing an In0.17Al0.83N film with a thickness of about 10 nm under the conditions of a substrate temperature between 680° C., and 750° C., a V/III ratio between 1000 and 3000, and a pressure of about 50 Torr in the chamber of the MOCVD apparatus. At this step, TMI, TMA, and NH3are supplied into the chamber of the MOCVD apparatus.

The first cap layer24is formed by growing an AlN film with a thickness of about 2 nm under the conditions of a substrate temperature between 680° C. and 750° C. and a pressure of about 50 Torr in the chamber of the MOCVD apparatus. The AlN film formed under these conditions has a single-crystal structure. At this step, TMA and NH3are supplied into the chamber of the MOCVD apparatus.

The second cap layer25is formed by growing an AlN film with a thickness of about 4 nm under the conditions of a substrate temperature between 400° C., and 500° C., and a pressure of about 50 Torr in the chamber of the MOCVD apparatus. The AlN film formed under these conditions has an amorphous structure. At this step, TMA and NH3are supplied into the chamber of the MOCVD apparatus.

In the first embodiment, the electron supply layer23, the first cap layer24, and the second cap layer25may be consecutively formed by crystal growth without taking the substrate10out of the chamber of the MOCVD apparatus. This method makes it possible to prevent contamination of the interface between the electron supply layer23and the first cap layer24and the interface between the first cap layer24and the second cap layer25. That is, this method makes it possible to prevent the entry of, for example, C, O, and Si into the interfaces, and to prevent formation of defects at the interfaces. The second cap layer25may also be formed by atomic layer deposition (ALD).

In the semiconductor device of the first embodiment, although the electron supply layer23and the first cap layer24are formed of different materials, the continuity of the crystal structure is maintained because the electron supply layer23and the first cap layer24are formed by the same epitaxial growth. Accordingly, the defect density at the interface between the electron supply layer23and the first cap layer24is very low. Also, although the first cap layer24and the second cap layer25have different crystal structures, they are formed of the same material and the continuity of the material is maintained. Accordingly, the defect density at the interface between the first cap layer24and the second cap layer25is very low.

Next, as illustrated byFIG. 13B, portions of the first cap layer24and the second cap layer25, which correspond to areas where the source electrode32and the drain electrode33are to be formed, are removed to form openings24aand24bthat expose the electron supply layer23. More specifically, a photoresist is applied to the second cap layer25, and the photoresist is exposed and developed by an exposure apparatus to form a resist pattern (not shown) having openings in areas where the source electrode32and the drain electrode33are to be formed. Next, portions of the first cap layer24and the second cap layer25not covered by the resist pattern are removed by, for example, dry etching to expose portions of the electron supply layer23and form the openings24aand24b. Then, the resist pattern is removed by using, for example, an organic solvent.

Next, as illustrated byFIG. 13C, the source electrode32and the drain electrode33are formed on the electron supply layer23. More specifically, a photoresist is applied to the electron supply layer23and the second cap layer25, and the photoresist is exposed and developed by an exposure apparatus to form a resist pattern (not shown) having openings in areas where the source electrode32and the drain electrode33are to be formed. Next, a metal laminated film including a Ti film (thickness: 20 nm) and an Al film (thickness: 200 nm) is formed by, for example, vacuum deposition, and the metal laminated film is immersed in an organic solvent to remove a portion of the metal laminated film formed on the resist pattern by a lift-off technique. The remaining portions of the metal laminated film including Ti and Al form the source electrode32and the drain electrode33. Then, a heat treatment is performed on the source electrode32and the drain electrode33at a temperature between 400° C., and 1000° C., for example, at 550° C., to form ohmic contacts between the electron supply layer23and the source electrode32and the drain electrode33.

Next, as illustrated byFIG. 14A, a passivation film40is formed on the source electrode32, the drain electrode33, and the second cap layer25. More specifically, the passivation film40with a thickness between 2 nm and 500 nm, for example, 100 nm, is formed by plasma chemical vapor deposition (CVD). The passivation film40may also be formed by ALD or sputtering. The passivation film40is preferably formed of an oxide, a nitride, or an oxynitride of Si, Al, Hf, Zr, Ti, Ta, or W, and is more preferably formed of SiN.

Next, as illustrated byFIG. 14B, a portion of the passivation film40in an area where the gate electrode31is to be formed is removed to form an opening40a. More specifically, a photoresist is applied to the passivation film40, and the photoresist is exposed and developed by an exposure apparatus to form a resist pattern (not shown) having an opening in an area where the opening40ais to be formed. Next, a portion of the passivation film40not covered by the resist pattern is removed by dry etching using a chlorine gas or a fluorine gas as an etching gas to expose a portion of the second cap layer25and form the opening40a. Then, the resist pattern is removed by using, for example, an organic solvent. Alternatively, the opening40aof the passivation film40may be formed by wet etching using, for example, hydrofluoric acid or buffered hydrofluoric acid.

Next, as illustrated byFIG. 14C, the gate electrode31is formed on an area including the exposed portion of the second cap layer25. More specifically, a photoresist is applied to the second cap layer25and the passivation film40, and the photoresist is exposed and developed by an exposure apparatus to form a resist pattern (not shown) having an opening in an area where the gate electrode31is to be formed. Next, a metal laminated film including an Ni film (thickness: 30 nm) and an Au film (thickness: 400 nm) is formed by, for example, vacuum deposition, and the metal laminated film is immersed in an organic solvent to remove a portion of the metal laminated film formed on the resist pattern by a lift-off technique. The remaining portion of the metal laminated film including Ni and Au forms the gate electrode31. Through the above process, the semiconductor device of the first embodiment is produced.

The layer structures of the gate electrode31, the source electrode32, and the drain electrode33illustrated inFIGS. 13A through 14Care just examples. Each of the gate electrode31, the source electrode32, and the drain electrode33may have a single-layer structure or a multilayer structure. Also, the gate electrode31, the source electrode32, and the drain electrode33may be formed by any other methods. In the first embodiment, a heat treatment is performed on the source electrode32and the drain electrode33after they are formed. However, the heat treatment may be omitted as long as ohmic characteristics are obtained. Also, a heat treatment may be performed on the gate electrode31. Although the semiconductor device of the first embodiment employs a Schottky gate structure, a metal-insulator-semiconductor (MIS) gate structure may instead be used.

Although a semi-insulating SiC substrate is used as the substrate10in the first embodiment, any other type of substrate may also be used as long as nitride semiconductors are used for an epitaxial structure that functions as a field-effect transistor. Also, the substrate10may have either a semi-insulating property or a conductive property.

The above-described configuration of the semiconductor device is an example, and the semiconductor device may have any other appropriate configuration as a field-effect transistor. For example, a GaN or AlN cap layer may be formed as the uppermost layer of the semiconductor device. In the first embodiment, Si is used as an n-type impurity element. However, Ge or Sn may be used instead of Si.

Second Embodiment

Next, a second embodiment is described. In the second embodiment, a packaged semiconductor device, a power-supply device, and a high-frequency amplifier are described.

The packaged semiconductor device of the second embodiment is produced by discretely packaging the semiconductor device of the first embodiment. The discretely-packaged semiconductor device is described with reference toFIG. 15.FIG. 15is a schematic diagram illustrating the internal configuration of the discretely-packaged semiconductor device. The arrangement of electrodes in the packaged semiconductor device is different from that in the semiconductor device of the first embodiment.

First, a semiconductor device is produced according to the first embodiment and is diced to obtain a semiconductor chip410that is a HEMT including a GaN semiconductor material. The semiconductor chip410is fixed to a lead frame420via a die attach material430such as solder. The semiconductor chip410corresponds to the semiconductor device of the first embodiment.

Next, a gate electrode411is connected via a bonding wire431to a gate lead421, a source electrode412is connected via a bonding wire432to a source lead422, and a drain electrode413is connected via a bonding wire433to a drain lead423. The bonding wires431,432, and433are formed of a metal material such as Al. In the second embodiment, the gate electrode411is a gate electrode pad and is connected to the gate electrode31of the semiconductor device of the first embodiment. The source electrode412is a source electrode pad and is connected to the source electrode32of the semiconductor device of the first embodiment. The drain electrode413is a drain electrode pad and is connected to the drain electrode33of the semiconductor device of the first embodiment.

Then, the semiconductor chip410is sealed with a molding resin440by transfer molding. Through the above process, a discretely-packaged semiconductor device of a HEMT including a GaN semiconductor material is produced.

Next, a power-supply device and a high-frequency amplifier of the second embodiment are described. Each of the power-supply device and the high-frequency amplifier includes the semiconductor device of the first embodiment.

First, a power-supply device460of the second embodiment is described with reference toFIG. 16. The power-supply device460includes a high-voltage primary circuit461, a low-voltage secondary circuit462, and a transformer463disposed between the primary circuit461and the secondary circuit462. The primary circuit461includes an alternator464, a bridge rectifier circuit465, multiple (in this example, four) switching elements466, and a switching element467. The secondary circuit462includes multiple (in this example, three) switching elements468. In the example ofFIG. 16, each of the switching elements466and467of the primary circuit461may be implemented by the semiconductor device of the first embodiment. Each of the switching elements466and467of the primary circuit461is preferably implemented by a “normally off” semiconductor device. Each of the switching elements468of the secondary circuit462may be implemented by a metal insulator semiconductor field effect transistor (MISFET).

Next, a high-frequency amplifier470of the second embodiment is described with reference toFIG. 17. The high-frequency amplifier470may be used, for example, for a power amplifier of a base station in a cell-phone system. The high-frequency amplifier470includes a digital predistortion circuit471, mixers472, a power amplifier473, and a directional coupler474. The digital predistortion circuit471compensates for the nonlinear distortion of an input signal. Each mixer472mixes the input signal whose non-linear distortion is compensated for with an alternating current signal. The power amplifier473amplifies the input signal mixed with the alternating current signal. In the example ofFIG. 17, the power amplifier473includes the semiconductor device of the first embodiment. The directional coupler474, for example, monitors input signals and output signals. With the circuit ofFIG. 17, for example, an output signal can be switched to the mixer472and mixed with an alternating-current signal, and the mixed signal can be output to the digital predistortion circuit471.

An aspect of this disclosure provides a semiconductor crystal substrate that can reduces the gate leakage current of a semiconductor device.