System and method for reducing trapped charge effects in a CMOS photodetector

A system and method for reducing image lag in a complementary metal oxide semiconductor (CMOS) photodetector is disclosed. In one embodiment, the invention is a a method for reducing image lag in an array of complementary metal oxide semiconductor (CMOS) photodetectors by forward biasing the photodetectors during a first time period to charge charge traps in the photodetectors, and reverse biasing the photodetectors during a second time period to remove charge from the photodetectors except the charge trapped in the charge traps.

TECHNICAL FIELD

The invention relates generally to light-capturing devices, and, more particularly, to a system and method for reducing trapped charge effects in a complementary metal oxide semiconductor (CMOS) photodetector.

BACKGROUND OF THE INVENTION

Electronic image sensors are widely used in a variety of electronic cameras and scanners. Historically, most of these sensors have been implemented as charge-coupled devices (CCD). A CCD converts photons captured in individual picture elements (pixels) into electrical charge. In a CCD, complicated clock voltages and high voltage potentials are required to transfer the electric charge that results from the absorption of photons out of the pixel. More recently CMOS active pixel sensors (APS) have been developed. A CMOS active pixel sensor is preferred over a CCD because the circuit that generates the requisite timing signals can be integrated on the same chip with the pixel circuit and because a CMOS active pixel sensor operates at a lower voltage level and consumes less power than a CCD. In a CMOS APS each pixel contains a light-sensitive element, such as a photodetector that can be implemented as a photodiode (pd), and several transistors integrated on the same substrate, referred to as being integrated on the same “chip.” The chip comprises multiple layers of semiconductor material formed over a substrate. The elements of the pixel are formed by growing or depositing layers of semiconductor material over the substrate and selectively etching the layers of semiconductor material to form the elements. The pixels are typically arranged in an array having rows and columns to form an image sensor.

In one common implementation, the pixel contains a photodiode and three transistors. Such an implementation is shown in FIG.1.FIG. 1is a schematic view of a conventional CMOS pixel1. The pixel1comprises a photodiode2and transistors4,6and7. Each of the transistors4,6and7can be a CMOS field effect transistor (CMOSFET). The transistor4functions as a reset switch, the transistor6functions as a source follower buffer amplifier, referred to as a “source follower,” and the transistor7functions as a row select switch. The reset transistor4is used to initialize the photodiode2in a reverse-biased state by coupling the photodiode2to voltage source Vdd when the reset transistor4is on via a signal on the gate terminal8. The source follower transistor6buffers the output signal of the photodiode2, and the row select transistor7is responsive to a row select signal and connects the output of the pixel on line11to a column line that is connected to a column processing circuit (not shown).

One disadvantage of a CMOS APS is that the light sensitive area of the pixel (the light capturing area of the photodiode) is only a small fraction of the total area of the pixel. This disadvantage can be overcome by locating the photodiode in a layer other than the layer in which the transistors are formed, thus maximizing the light capturing area of the photodiode. One way to create such a pixel is to form the transistors in one or more layers of crystalline silicon and then form a layer of α-Si:H (hydrogenated amorphous silicon) over the layer of crystalline silicon in which the transistors are formed. The photodiode is then formed in the layer of α-Si:H. Photodiodes that are formed in this layer of α-Si:H are almost as large as the overall pixel dimensions, and therefore have a larger light sensitive area. A simplified layer structure that includes the transistors and photodiode ofFIG. 1is shown in FIG.2. The layer structure20includes a layer21of crystalline silicon in which the transistors4,6and7are formed and a layer of hydrogenated amorphous silicon22in which the photodiode2is formed.

FIG. 3is a schematic diagram illustrating a simplified image sensor30formed using a plurality of the pixels of FIG.1. The image sensor30includes a pixel array32that comprises a plurality of pixels1arranged in a row and column format. All of the pixels in a row are coupled to a row select line, an exemplary one of which is illustrated using reference numeral34. All of the pixels in a column are coupled to a common column line, an exemplary one of which is illustrated using reference numeral36. A reset line is coupled to each pixel in each row, and is omitted for simplicity. In this manner, a row select signal supplied over a row select line by circuitry that is not shown can be used to activate the pixels in a particular row. In response to the row select signal, each of the pixels in a row reads out accumulated charge via its respective column line.

FIG. 4is a schematic diagram illustrating the operating cycles of two rows of pixels of FIG.3. For example, during a reset period41the pixels in row n will be reset by turning on the reset transistor4(FIG. 1) in each pixel. After the reset period41, the photodiode2collects light and accumulates charge during the accumulate period42. At the end of the accumulate period42, the accumulated charge is read out of each pixel1(FIG. 1) in row n during read period44by turning on the row select transistor7(FIG. 1) of the pixel. Activating the row select transistor7couples the output of the photodiode2to a corresponding column line, such as column line36in FIG.3. Although omitted for simplicity, each column line inFIG. 3is coupled to circuitry for sampling and holding the value of the charge from each pixel. The reset period41, accumulate period42and the read period44comprise one operating cycle, also referred to as a “row period,” of the pixels in row n. The row period is the time required to read one row of pixels. A frame period is the time required to read all rows in an array.

Unfortunately, while forming the photodiode in a layer of hydrogenated amorphous silicon increases the capture area of the photodiode, the hydrogenated amorphous silicon layer leads to a condition in which some of the light-induced charge in the photodiode cannot be removed during one operating cycle of the pixel. Dangling bonds present in the hydrogenated amorphous silicon and trap charge in the photodiode. The dangling bonds constitute what are referred to as “charge traps” in the photodiode. Hydrogenation of the amorphous silicon reduces the number of dangling bonds by attaching hydrogen atoms to them, but some dangling bonds remain. When the photodiode is exposed to photons of light, electron-hole pairs are created and the charge of the electron is stored in the photodiode. If the photodiode has many of these so called “charge traps,” some portion of the electric charge in the photodiode is trapped in the charge traps and will not be released in a single operating cycle. Because the trapped electric charge cannot be released from the photodiode in a single operating cycle, the electric charge is released over a period of successive operating frames.

When combined over an image sensor having many pixels, the effect of electric charge trapped in the photodiode and released over successive operating frames gives rise to a condition referred to as “image lag.” When an image sensor suffers from image lag, information from one frame will persist in many subsequent frames. This phenomenon is most noticeable when the image sensor is implemented in a camera. When the camera pans across a bright object in an otherwise dark scene, image lag manifests as a bright trail in an otherwise dark image.

Therefore, it would be desirable to minimize the effect of electric charge trapped in a CMOS photodetector.

SUMMARY OF THE INVENTION

The invention provides several embodiments of a system and method for reducing the effects of electric charge trapped in a CMOS photodetector. In one embodiment, the invention is a system for reducing illumination-dependent trapped charge effects in a complementary metal oxide semiconductor (CMOS) photodetector. The system comprises a negative-polarity voltage source connected to the photodetector via a first switch operable during a first time period to forward bias the photodetector. Forward biasing the photodetector charges charge traps in the photodetector. The system additionally comprises a positive-polarity voltage source connected to the photodetector via a second switch operable during a second time period to reverse bias the photodetector. Reverse biasing the photodetector removes charge from the photodetector except the charge trapped in the charge traps.

In the manner just described, the invention operates to reduce illumination-dependent trapped charge effects in a photodetector by forward biasing the photodetector before the photodetector is reset and begins to accumulate electric charge. The forward biasing charges all the charge traps in the photodetector, rendering the charge traps substantially incapable of storing the illumination-dependent charge that is later generated by the photodetector in response to incident illumination. The signal component contributed to the output signal of the photodetector by the charge traps is therefore independent of the incident illumination.

Embodiments of the invention also provide a method for reducing image lag in an array of complementary metal oxide semiconductor (CMOS) photodetectors. The method comprises forward biasing the photodetectors during a first time period to charge traps in the photodetectors, and reverse biasing the photodetectors during a second time period to remove charge from the photodetectors except the charge trapped in the charge traps.

The invention operates to reduce image lag in the array of photodetectors by forward biasing the photodetectors before the photodetectors are reset and begin to accumulate electric charge. The forward biasing charges the charge traps in all of the photodetectors and renders the charge traps substantially incapable of storing the illumination-dependent charge that is later generated by the photodetectors in response to incident illumination. The signal component contributed to the output signal of the array by the charge traps is therefore independent of the illumination of the individual photodetectors. The signal component is therefore devoid of image information and the perception of image lag is therefore substantially reduced.

Other features and advantages in addition to or in lieu of the foregoing are provided by certain embodiments of the invention, as is apparent from the description below with reference to the following drawings.

DETAILED DESCRIPTION

FIG. 5is a schematic diagram illustrating a first embodiment of a pixel100constructed in accordance with the invention. The pixel100includes a photodetector114, a pair of transistor switches106and108, a resistor112, a transistor116, a transistor122, a negative-polarity voltage source102and a positive-polarity voltage source104. Although not shown inFIG. 5, the photodetector114is fabricated in a semiconductor layer comprising hydrogenated amorphous silicon, while the transistor switches106and108, the resistor112and the transistors116and122are fabricated in a semiconductor layer comprising crystalline silicon.

The anode of the photodetector114is connected to ground. The negative-polarity voltage source102is coupled to the cathode of the photodetector114via the transistor switch108and a resistor112. Specifically, the source of the transistor switch108is connected to the negative-polarity voltage source102and the drain is connected to the resistor112. The transistor switch108constitutes a switch with no more than a single pole connected between the negative-polarity voltage source102and the photodetector114.

The positive-polarity voltage source104is coupled to the cathode of the photodetector114via the transistor switch106. Specifically, the drain of the transistor switch106is connected to the positive-polarity voltage source104and the source is connected to the cathode of the photodetector114.

The cathode of the photodetector114is also connected to the gate of transistor116. The transistor116is configured as a source follower buffer amplifier. The drain of the transistor116is connected to the positive-polarity voltage source104and the source of the transistor116is supplied to the drain of the row select transistor122. The output of the row select transistor122is the source on connection118and is connected to a column line of the image sensor of which the pixel100forms a part, as described above with respect toFIGS. 1 and 3.

It should be mentioned that, while illustrated using CMOS field effect transistors, any type of transistor may be used to implement the transistor switches106,108and the transistors116and122.

In accordance with an aspect of the invention, the circuit described inFIG. 5operates to reduce illumination-dependent trapped charge effects in a photodetector by forward biasing the photodetector114prior to the time that the photodetector is reset and begins to accumulate electric charge. Forward biasing the photodetector114charges all of the charge traps in the photodetector and renders the charged charge traps substantially incapable of storing any of the illumination-dependent charge that is generated by the photodetector as a result of exposing the photodetector to light. Rendering the charge traps in the photodetector substantially incapable of trapping illumination-dependent charge reduces illumination-dependent trapped charge effects in the photodetector. The charge trapped in the photodetector114contributes a small-trapped charge component to the charge that is read out from the photodetector to the column line after the photodetector has been exposed to light. However, the trapped charge component is independent of the illumination of the photodetector, and can therefore be cancelled, if necessary, by subsequent electrical processing. For example, the trapped charge component can be subtracted from the charge read out from the photodetector by circuitry (not shown) coupled to the respective column line or elsewhere.

In accordance with the invention, an image sensor composed of an array of photodetectors similar to the photodetector114, a substantially uniform amount of electric charge remains trapped in the charge traps in each of the photodetectors114in the array after the photodetectors have been reset as just described. When the image sensor is exposed to light and the charge that accumulates in each photodetector is then read out, the charge read out from each photodetector includes a small charge trap component as just described. Since the charge traps of all the photodetectors in the image sensor are uniformly charged, the charge trap component contributed by each photodetector is substantially uniform over the image sensor and is substantially independent of the illumination of the photodetector. The charge trap components uniformly increase the black level of the image signal generated by the image sensor. If desired, the uniformly increased black level can be subtracted from the image signal by the circuitry (not shown) coupled to each column line in the image sensor or elsewhere.

Even if the charge trap density is not completely uniform over all the photodetectors in the image sensor, an image component generated in response to the charge trap components is static. A static image component is harder for the human eye to detect than an image that moves or otherwise temporally changes.

At the beginning of an operating cycle of the pixel100, the transistor switch108closes to connect the photodetector114to the negative polarity voltage source102to forward bias the photodetector. Current flow is limited by the resistor112. Forward biasing photodetector114charges all the charge traps within the photodetector114.

The transistor switch108then opens and the transistor switch106closes to connect the photodetector114to positive-polarity voltage source104. The transistor switch106acts as a reset switch to remove from the photodetector114all charge except that which is trapped in the charge traps. In other words, after the photodetector114has been reset, only the charge trapped in the charge traps remains in the photodetector. The transistor switch106then opens, and the photodetector114accumulates charge in response to light incident on the photodetector.

FIG. 6is a schematic diagram illustrating the operating cycles of two rows of pixels of FIG.5. Referring additionally toFIG. 5, the row period152includes a forward-bias period154, during which the photodetector114is forward biased and the charge traps within the photodetector114are charged. The forward-bias period154immediately precedes the reset period156. At the start of row period152, the forward-bias period154begins with the transistor switch108closing to forward bias the photodetector114, which charges all the charge traps in the photodetector1114.

At the end of the forward-bias period154, the transistor switch108opens and the transistor switch106closes to begin the reset period156in which the photodetector114is reverse biased. During the reset period156, all the electric charges except that which is trapped in the charge traps is removed from the photodetector114. At the end of the reset period156, the transistor switch106opens and the accumulate period158begins. During the accumulate period158, the photodetector114generates charge in response to the light to which it is exposed. At the end of the accumulate period158, the row select transistor122closes to begin the read period160. During the read period160, charge accumulated by the photodetector114, buffered by the transistor116, is read out via the connection118onto the column line (not shown) of the pixel100. Row select transistor122opens at the end of the read period.

FIG. 7is a schematic diagram illustrating a second embodiment200of a pixel constructed in accordance with the invention. A possible drawback of the pixel100ofFIG. 5when implemented using CMOS technology is that it uses two voltage sources having opposite polarities to forward bias and to reset the photodetector114. InFIG. 7, a single voltage source204charges a capacitor216with charge that is later used to forward bias the photodetector114and charge the charge traps in the photodetector114. The single voltage source204is also used to reset the photodetector114. The pixel200includes transistor switches206,208,212,214and218.

The cathode of the photodetector114is connected to the drain of transistor switch214, to the source of transistor switch218and to the gate of transistor116. The anode of the photodetector114is connected to ground. The drain of transistor switch218is connected to the voltage source204. The drain of transistor switch206is connected to the voltage source204and the source is connected to the drain of the transistor switch212and to one side of capacitor216. The source of the transistor switch214and the drain of the transistor switch208are connected to the other side of capacitor216. The sources of transistor switches208and212are connected to ground.

When the transistor switches206and208are closed, the capacitor216is charged to the voltage Vdd of the voltage source204. When the capacitor216is fully charged, the transistor switches206and208open and the transistor switches212and214close. When the transistor switches212and214close, the charge stored in the capacitor216forward biases the photodetector114, which charges the charge traps in the photodetector114. The transistor switches206,208,212and214collectively constitute a double-pole change-over switch arranged to connect the capacitor216to the voltage source204when the switches206and208close and the switches212and214open, and to connect the capacitor to the photodetector with a reversed polarity when the switches206and208open and the switches212and214close.

Forward biasing the photodetector114by discharging the capacitor216charges all the charge traps in the photodetector114. The transistor switches212and214then open and the transistor switch218closes. Closing the transistor switch218connects the photodetector114to the voltage source204. This reverse biases the photodetector114and thus performs the reset function. Resetting the photodetector114removes all the electric charge from the photodetector114except that which is trapped in the charge traps, as described above. When the transistor switch218opens, the photodetector114begins accumulating charge, which is buffered by the transistor116. The charge accumulated in the photodetector is read out through row select transistor122and connection118to a column line as described above.

FIG. 8is a schematic diagram illustrating the operating cycles of two rows of the pixels of FIG.7. At the beginning of a charge period253, the transistor switches206and208close to charge the capacitor216to the voltage of the voltage source204. At the end of the charge period253, the transistor switches206and208open. At the beginning of the forward-bias period254, the transistor switches212and214close to forward bias the photodetector114. During the forward-bias period254, the charge stored in the capacitor216injects current into the photodetector114to charge the charge traps in the photodetector114. At the end of the forward-bias period254, the transistor switches212and214open. At the beginning of the reset period256, the transistor switch218closes to connect the photodetector114to the voltage source204. This resets the photodetector and removes all the electric charge from the photodetector114except the electric charge trapped in the charge traps in the photodetector114. At the end of the reset period256, the transistor switch218opens. This also marks the beginning of the accumulate period258. During the accumulate period258, the photodetector114generates charge in response to the light to which it is exposed. At the end of the accumulate period258, the row select transistor122closes to begin the read period260. During the read period260, charge accumulated by the photodetector114and buffered by the transistor116is read out via the connection118onto the column line (not shown) of the pixel200.

FIG. 9is a schematic diagram illustrating an image sensor300constructed using a two-dimensional array of the pixels100of FIG.5. The image sensor300includes a two-dimensional pixel array302that comprises a plurality of pixels100arranged in a row and column format. All the pixels in a row are coupled to a respective row select line, reset line and forward bias line, exemplary ones of which are indicated using reference numerals304,310and312, respectively. All the pixels in the array are connected to a trace or set of traces314that supplies a negative voltage to each of the pixels. All the pixels in the array are connected to a trace or set of traces316that supplies a positive voltage to each of the pixels. A row-wise arrangement of traces is shown as an example. However, this is not critical to the invention. The traces may have a column-wise arrangement, an array-wise arrangement, a row-wise arrangement and a column-wise arrangement or another arrangement.

All the pixels in a column are coupled to a respective column line, an exemplary one of which is indicated using reference numeral306. A row select signal supplied over a row select line by circuitry that is not shown causes each of the pixels in the row to read out any charge accumulated therein to its respective column line.

In accordance with the invention, a forward bias signal is applied to a pixel100via forward bias line312prior to the reset signal being applied via reset line310. As described above, assertion of the forward bias signal defines a forward bias period, during which the photodetector in the pixel100is connected to a trace supplying the negative voltage to forward bias the photodetector. During the forward bias period154(FIG. 6) all charge traps within the photodetector are charged with electric charge. At the end of the forward bias period, a reset signal is applied via the reset line310. During the reset period, the photodetector is connected to a trace supplying the positive voltage, which reverse biases the photodetector in the pixel100. During the reset period, all the electric charge, except the electric charge trapped in the charge traps, is removed from the photodetector in the pixel100. Homogenizing the amount of electric charge trapped in the photodetector in each pixel in the array prior to resetting the photodetector disables the mechanism that would creates image lag in the image sensor.

An embodiment of the image sensor300constructed using a two-dimensional array of the pixels200ofFIG. 7lacks a trace or set of traces that supplies a negative voltage to each of the pixels. Such embodiment additionally includes an additional line coupled to all the pixels in each row to control the transistor switches206and208to charge the capacitor216during the charge period253(FIG.8).

It will be apparent to those skilled in the art that many modifications and variations may be made to the above-described embodiments of the present invention without departing substantially from the principles of the present invention. All such modifications and variations are intended to be included herein within the scope of the present invention, as defined in the claims that follow.