Switching power source

A control circuit 8 of a switching power source comprises a voltage detector 31 for detecting a voltage VDC of a DC power supply 1 to produce a detection voltage VDT; a comparator 41 for producing an output signal VCP when detection voltage VDT from voltage detector 31 exceeds a reference voltage VR2; a bottom voltage detector 51 for detecting a bottom point of voltage VDS across a MOS-FET 3 after energy has been discharged from transformer 2; and a switching controller 61 for selectively turning MOS-FET 3 on depending on existence or absence of the output signal VCP from comparator 41. When the input voltage VDC from DC power supply 1 so rises that detection voltage VDT of voltage detector 31 is above the reference voltage VR2, switching controller 61 serves to late turn MOS-FET 3 on at the time bottom voltage detector 51 detects the second or later bottom point of the voltage VDS across MOS-FET 3, extending the off period of MOS-FET 3 to reduce switching frequency of MOS-FET 3.

TECHNICAL FIELD

This invention relates to a switching power source capable of improving the conversion efficiency in a wide variation range of power voltage.

BACKGROUND OF THE INVENTION

Prior art switching power sources of flyback pseudo resonance (partial voltage resonance) type have been utilized in wide applications because they advantageously have a simplified circuit structure with the high conversion efficiency and less operating noise. For example, Japanese Patent Disclosure No. 2003-61345 discloses a switching power source of such a pseudo resonance type which, however, has their defect in that change in input voltage from commercial AC power source fluctuates switching frequency of a switching element under the constant load. For example, in a switching power source applicable to power source voltages all over the world with 100 watts of rating output power and 85 to 264 volts of commercial AC input voltage, the switching element is operated with 50 kHz of switching frequency under the commercial AC input voltage of 85 volts, however, it increases the switching frequency up to 100 kHz with 264 volts of commercial AC input voltage.

In such a switching power source, as the on period of the switching element is shortened with elevation of power voltage applied on a primary winding of transformer, power voltage supply in a high range (185 to 264 volts) increases the switching frequency and thereby switching number of the switching element. Accordingly, a problem arises that the power source gives rise to increase in switching loss and deterioration in conversion efficiency under the power voltage supply in the high range.

Japanese Patent Disclosure No. 2001-231257 exhibits a DC-DC converter capable of changing either pseudo resonance or frequency reduction by switching minimum off period of the switching element based on load condition on the secondary side. This DC-DC converter controls increase in switching number of switching element per time under the light load condition by shifting to pseudo resonance under the heavy load condition and shifting to frequency reduction under the light load condition. However, the power supply of high voltage range increases switching frequency and switching number per time of switching element for the above-mentioned reason, causing increase in switching loss and deterioration in conversion efficiency in this DC-DC converter. Also, in the transition from pseudo resonance to frequency reduction or vice versa, a peak value of electric current flowing through transformer changes in a wide range depending on discontinuously varying oscillation frequency of transformer. Accordingly, under some load conditions, vibration of transformer undesirably produces acoustic sound or noise.

An object of the present invention is to provide a switching power source which improves the conversion efficiency under the power voltage supply of wide range. Another object of the present invention is to provide a switching power source capable of controlling noise resulted from transformer etc.

SUMMARY OF THE INVENTION

The switching power source according to the present invention comprises a DC power supply (1); a transformer (2) having primary and secondary windings (2a,2b); a switching element (3) connected to the DC power supply (1) through the primary winding (2a) of the transformer (2); a rectifying smoother (6) connected to the secondary winding (2b) of the transformer (2) to produce a DC output voltage (VOUT); and a control circuit (8) for producing drive signals (VG) to the switching element (3) to turn the switching element (3) on and off in order to keep the DC output voltage (VOUT) substantially constant. The control circuit (8) comprises a voltage detector (31) for detecting a voltage (VDC) of the DC power supply (1) to produce a detection voltage (VDT); a comparator (41) for producing an output signal (VCP) when the detection voltage (VDT) from the voltage detector (31) exceeds a reference voltage (VR2); a bottom voltage detector (51) for detecting a bottom point of the voltage (VDS) across the switching element (3) after energy has been discharged from the transformer (2); and a switching controller (61) for selectively turning the switching element (3) on depending on existence or absence of the output signal (VCP) from the comparator (41). Specifically, when the comparator (41) does not produce the output signal (VCP), and the bottom voltage detector (51) detects a first bottom point of the voltage, the switching controller (61) serves to turn the switching element (3) on. Otherwise, when the comparator (41) produces the output signal (VCP), and the bottom voltage detector (51) detects plural bottom points of the voltage, the switching controller (61) serves to turn the switching element (3) on.

Under the low input voltage (VDC) from the DC power supply (1), the switching element (3) is turned on at the time the bottom voltage detector (51) detects a first bottom point of the voltage (VDS) across the switching element (3). In other words, when voltage (VDS) across the switching element (3) comes to the bottom point after energy has been released from the transformer (2), pseudo resonance action is performed to turn the switching element (3) from the off to the on condition. Meanwhile, when the input voltage (VDC) from the DC power supply (1) so rises that detection voltage (VDT) of the voltage detector (31) is above the reference voltage (VR2), the switching controller (61) serves to late turn the switching element (3) on at the time the bottom voltage detector (51) detects the second or later bottom point of the voltage (VDS) across the switching element (3), extending the off period of the switching element (3) to reduce the switching frequency of the switching element (3). Accordingly, the power source enables decrease in switching loss by diminishing the switching number of the switching element (3) under the elevated input voltage to improve the conversion efficiency of the power source in a wide fluctuation range of the power voltage.

Accordingly, the switching power source can be applied to any of various worldwide power voltages with less switching loss. Moreover, the power source can be shifted either to the pseudo resonance mode or the reduction mode of switching frequency depending on the input voltage level to fix it in one of these modes in practical use in order to control or restrict noise produced from transformer or the like upon shifting the power source between the pseudo resonance and frequency reduction modes.

BEST MODE FOR CARRYING OUT THE INVENTION

Five embodiments of the switching power source according to the present invention are described hereinafter with reference toFIGS. 1 to 20of the accompanying drawings.

FIG. 1shows a first embodiment of the switching power source according to the present invention which comprises a DC power supply1; a primary winding2aof a transformer2and a MOS-FET (MOS type Field Effect Transistor)3as a switching element connected in series to DC power supply1; an output rectifying smoother6which has an output rectifying diode4and an output smoothing capacitor5connected to a secondary winding2bof transformer2to produce a DC output voltage VOUT; an output voltage detector7for detecting DC output voltage VOUT; a control circuit8which includes a drive circuit24for producing drive signals VGto MOS-FET3based on detection signals VFBfrom output voltage detector7to keep DC output voltage VOUTon a substantially constant level; and a current detecting resistor9for detecting electric current IDflowing through primary winding2aof transformer2or MOS-FET3as a corresponding voltage to produce a detection signal VOCPto control circuit8. Then, control circuit8comprises an input voltage detector31for detecting DC input voltage VDCfrom DC power supply1; a comparator41for comparing detection voltage VDTfrom input voltage detector31with reference voltage VR2to produce output signal VCPof high or low level H or L; a bottom voltage detector51for detecting a bottom point in ringing voltage VRGproduced in a drive winding2cof transformer2; and a switching controller61for producing output signals VONto turn MOS-FET3on. Ringing voltage VRGis similar in shape to drain-source voltage VDSof MOS-FET3after energy has been released from transformer2. The present invention is characterized in that switching controller61produces output signals VONto turn MOS-FET3at the time or each time bottom voltage detector51detects a first or each bottom point in ringing voltage VRGfrom drive winding2cwhen comparator41produces output signals VCPof high voltage level H, however, switching controller61produces output signals VONto turn MOS-FET3at the time or each time bottom voltage detector51detects a second or every other bottom point in ringing voltage VRG.

FIG. 2illustrates a detailed circuit diagram of the switching power source shown inFIG. 1. As understood fromFIG. 2, DC power source1comprises a rectifying bridge circuit1cconnected to an AC power source1athrough an input filter circuit1b; and an input smoothing capacitor1dconnected to output terminals of rectifying bridge circuit1c. A trigger resistor10is connected between rectifying bridge circuit1cand control circuit8to supply electric power through trigger resistor10to control circuit8. Drive winding2cis electro-magnetically coupled to primary and secondary windings2aand2bin transformer2, and connected to an auxiliary rectifying smoother13for producing DC voltage VINto control circuit8. Detection signals by output voltage detector7are transmitted to the primary side of transformer2through a photo-coupler14of light emitting element14aand light receiving element14bto generate associated voltages VFBon junction of light receiving element14and a pull-up resistor15so that associated voltages VFBare supplied as indicating detection signals from output voltage detector7to a driving circuit or driver24of control circuit8.

Driver24comprises a first normal power source16for producing a reference voltage VR1to regulate a maximum value of electric current flowing through primary winding2aof transformer2or MOS-FET3; an overcurrent restrictive comparator17for producing signals V1of high voltage level H to turn MOS-FET3off when current detecting resistor9detects detection signals VOCPequal to or above associated voltages VFBfrom output voltage detector7; an OR gate19for outputting logical sum signals of an output signal V1from overcurrent restrictive comparator17and an output signal V2from mode control comparator18; a pulse generator20for producing a pulse signal V4each time a period of time has elapsed since turning-off of MOS-FET3; an RS-flip flop21which is turned to the set condition by output signal VONfrom a switching controller61for producing drive signals VGof high voltage level H to gate terminal of MOS-FET3through a buffer amplifier22, but is turned to the reset condition by logical sum signal V3from OR gate19for producing drive signals VGof low voltage level L to gate terminal of MOS-FET3through buffer amplifier22; and a power regulator23for supplying DC power to each element in control circuit8when DC voltage VINfrom trigger resistor10or auxiliary rectifying smoother13reaches an operable level and ceasing power supply to each element when DC voltage VINdrops to a shutdown level.

Input voltage detector31comprises two voltage-dividing resistors32and33connected in parallel to an output smoothing capacitor1din DC power supply1to produce a divided voltage VDTof DC input voltage VDCfrom junction of dividing resistors32and33. Comparator41comprises a second normal power source42for producing a reference voltage VR2to regulate a voltage level for shifting switching control modes in response to DC input voltage VDC; an comparing circuit43for producing output signals of low voltage level L and high voltage level H when input voltage detector31produces detection voltage VDTrespectively beneath and equal to or over reference voltage VR2of second normal power source42; and an inverter44for producing an inverted signal of output from comparing circuit43as a comparative signal VCP. In comparator41shown inFIG. 2, when detection voltage VDTfrom input voltage detector31does not reach reference voltage VR2of second normal power source42under the AC voltage in a low range (85 to 135 volts) from AC power source1a, comparing circuit43produces an output of low voltage level L so that inverter44produces a comparative signal VCPof high voltage level H as shown inFIG. 7(D). When detection voltage VDTfrom input voltage detector31exceeds reference voltage VR2of second normal power source42under the AC voltage in a high range (185 to 264 volts) from AC power source1a, comparing circuit43produces an output of high voltage level H so that inverter44produces a comparative signal VCPof low voltage level L as shown inFIG. 8(D).

As shown inFIG. 3, bottom voltage detector51comprises a clipping diode52and voltage-dividing resistors53and54connected in series to both ends of drive winding2cof transformer2; a capacitor55connected in parallel to lower resistor54; a third normal power source56for producing a threshold voltage VTH; and a detection comparator57for producing output voltages VBDof low voltage level L and high voltage level H respectively when charged voltage VBMof capacitor55is lower than and equal to or higher than threshold voltage VTHof third normal power source56. Specifically, in operation, drive winding2cof transformer2produces ringing voltage VRGsimilar in shape to drain-source voltage VDSof MOS-FET3shown inFIG. 4(A)during the off period of MOS-FET3to then shape the waveform of ringing voltage VRGthrough clipping diode52, dividing resistors53and54and capacitor55to signals VBMshown inFIG. 4(C), which is further transformed into pulse array voltages VBDshown inFIG. 4(D)by comparing charged voltage VBMof capacitor55with threshold voltage VTHof third normal power source56by detection comparator57. Accordingly, switching controller61can detect the trailing or drop edge of pulse array voltages VBDfrom detection comparator57as a bottom or minimum point in drain-source voltage VDSof MOS-FET3as shown inFIGS. 4(A) to 4(D).

Bottom voltage detector51may be formed in another arrangement shown inFIG. 5. In detail, the arrangement comprises voltage-dividing resistors53and54connected to both ends of drive winding2cof transformer2; a third normal power source56for producing threshold voltage VTH; a detection comparator57for producing output voltages VBDof low voltage level L and high voltage level H respectively when divided voltage VBMbetween resistors53and54is lower than and equal to or higher than threshold voltage VTHof third normal power source56; and a delay circuit58for retarding pulse array voltages VBDfrom detection comparator57by a period of time tD. In operation, drive winding2cof transformer2produces ringing voltage VRGsimilar in shape to drain-source voltage VDSof MOS-FET3shown inFIG. 6(A)during the off period of MOS-FET3to then divide by resistors53and54ringing voltage VRGinto divided voltage VBMshown inFIG. 6(C)on junction between resistors53and54; divided voltage VBMis shaped into pulse array voltages VBDshown inFIG. 6(D)by comparing divided voltage VBMwith threshold voltage VTHof third normal power source56by detection comparator57; then delay circuit58retards pulse array voltages VBDby a period of time tDto thereby cause the trailing edge in pulse array voltages VBDfrom detection comparator57to coincide with bottom point in drain-source voltage VDSof MOS-FET3as shown inFIGS. 6(A) to 6(D). In this way, switching controller61can also detect the trailing or drop edge of pulse array voltages VBDfrom detection comparator57as a bottom or minimum point in drain-source voltage VDSof MOS-FET3utilizing bottom voltage detector51shown inFIG. 5.

As exhibited inFIG. 2, switching controller61comprises first and second D-flip flops62and63each having a reset terminal R to reset D-flip flops62and63by applying rising edge of drive signals VGfrom RS-flip flop21to reset terminal R. Output signals VBDfrom bottom voltage detector51is supplied to each clock input terminal CLK of first and second flip flops62and63, and input terminal D of first D-flip flop62is retained on high voltage level H (REG). Signal input terminal D of second D-flip flop63is connected to output terminal Q of first D-flip flop62, and input terminals of OR gate65are connected to output terminal Q of second D-flip flop63, output terminals of pulse generator20and an AND gate64. One and the other input terminals of AND gate64are respectively connected to output terminal Q of first D-flip flop62and inverter44of comparator41. Output terminal of OR gate65is connected to a set terminal S of RS-flip flop21. First D-flip flop62produces an output signal VDF1of high voltage level H synchronously with a first trailing edge of output signal VBDsent from bottom voltage detector51to clock input terminal CLK of first D-flip flop62. Second D-flip flop63produces an output signal VDF2of high voltage level H synchronously with a second trailing edge of output signal VBDsent from bottom voltage detector51to clock input terminal CLK of second D-flip flop63. When AD power source1aproduces AC voltage of low range (85 to 135 volts), comparator41produces output signal VCPof high voltage level H. Bottom voltage detector51forwards output signal VBDto clock input terminal CLK of first D-flip flop62which then produces output signal VDF1of high voltage level H synchronously with first trailing edge of output signal VBDfrom bottom voltage detector51so that AND gate64produces output signal VADof high voltage level H. Output signal VADfrom AND gate64is supplied through OR gate65to set terminal S of RS-flip flop21which therefore is turned to the set condition to provide gate terminal of MOS-FET3with drive signal VGof high voltage level H through buffer amplifier22. Thus, under the AC power voltage in the low range, MOS-FET3is turned on when bottom voltage detector51detects the first bottom or minimum voltage. When AC power source1aproduces AC voltage of high range (185 to 264 volts), comparator41produces output signal VCPof low voltage level L so that AND gate64produces output signal VADof low voltage level L, and therefore, RS-flip flop21is not turned to the set condition. On the other hand, second D-flip flop63produces output signal VDF2of high voltage level H synchronously with a second trailing edge of output signal VBDfrom bottom voltage detector51to clock input terminal CLK of second D-flip flop63. Accordingly, output signal VDF2from second D-flip flop63is supplied through OR gate65to set terminal of RS-flip flop21to provide gate terminal of MOS-FET3with drive signal VGof high voltage level H. Thus, under the AC power voltage in the high range, MOS-FET3is turned on when bottom voltage detector51detects the second bottom or minimum voltage.

In operation of the switching power source shown inFIG. 2, when AC power source1aproduces AC voltage in the low range (85 to 135 volts), comparator41produces comparative signal VCPof high voltage level H from inverter44as shown inFIG. 7(D). Also, during the off period of MOS-FET3, drain-source voltage VDSstarts descending at the same time transformer2has completed to discharge flyback energy stored therein, and bottom voltage detector51changes output signal VBDfrom high voltage level H to low voltage level L around the bottom voltage of drain-source voltage VDSas shown inFIG. 7(C). In this way, first D-flip flop62produces output signal VDF1of high voltage level H from output terminal Q in synchronization with first trailing edge of output signal VBDfrom bottom voltage detector51. Therefore, in response to first drop edge of output signal VBDfrom bottom voltage detector51, AND gate64generates logical product signal VADof high voltage level H, while second D-flip flop63produces signal VDF2of low voltage level L from output terminal Q. Accordingly, concurrently with first drop edge of output signal VBDfrom bottom voltage detector51, OR gate65sends logical sum signal VONof high voltage level H to set terminal of RS-flip flop21which therefore is shifted to the set condition. Thus, in synchronization with first trailing edge of output signal VBDfrom bottom voltage detector51shown inFIG. 7(C), RS-flip flop21causes buffer amplifier22to forward drive signal VGof high voltage level H to gate terminal of MOS-FET3to turn MOS-FET3on. For that reason, drain current IDthrough MOS-FET3linearly increases as graphed inFIG. 7(A). Accordingly, drain current IDflowing through MOS-FET3linearly increases as shown inFIG. 8(A). When detection voltage VOCPacross current detection resistor9reaches voltage level of detection signal VFBfrom output voltage detector7, mode control comparator18produces a signal V2of high voltage level H to reset RS-flip flop21which therefore causes buffer amplifier22to produce drive signal VGof low voltage level L to gate terminal of MOS-FET3to turn MOS-FET3off. In this way, under the power source voltage in the low range, the switching power source repeats the foregoing operation to perform pseudo resonance to turn MOS-FET3on when drain-source voltage VDSof MOS-FET3reaches the bottom point after transformer2has completed to exhaust stored flyback energy therein.

When AC power source1agenerates AC voltage in a high range (185 to 264 volts), drain-source voltage VDSacross MOS-FET3is retained on the high level during the off period of MOS-FET3, but starts to fall at the same time transformer2has completed to discharge stored flyback energy as shown inFIG. 8(B)to switch output signal VBDfrom bottom voltage detector51from high voltage level H to low voltage level L as shown inFIG. 8(C)around the bottom or minimum point in drain-source voltage VDS. At this time, as inverter44of comparator41keeps to produce comparative signal VCPof low voltage level L as shown inFIG. 8(D), AND gate64is kept in the off condition although first D-flip flop62produces signal VDF1of high voltage level H from output terminal Q to AND gate64in synchronization with initial trailing edge in output signal VBDfrom bottom voltage detector51. Therefore, AND gate only produces logical product signal VADof low voltage level L to OR gate65. On the other hand, concurrently with a second trailing edge of output signal VBDfrom bottom voltage detector51, second D-flip flop63produces signal VDF2of high voltage level H at the output terminal Q to OR gate65which then forwards logical sum signal VONof high voltage level H to turn RS-flip flop21to the set condition. Accordingly, synchronously with a second trailing edge of output signal VBDfrom bottom voltage detector51shown inFIG. 8(C), RS-flip flop21causes buffer amplifier22to give drive signal VGof high voltage level H to gate terminal of MOS-FET3to turn MOS-FET3on.

FIG. 9is a graph showing the switching frequency characteristics of MOS-FET3with AC input voltage from AC power source1aof the switching power source. AC input voltage from AC power source1ain the low range for example from 85 to 160 volts indicates pseudo resonance which increases switching frequency of MOS-FET3in an exponential function from 50 kHz with elevation of AC input voltage. When AC input voltage from AC power source1areaches 160 volts, the operation moves from pseudo resonance to frequency reduction to rapidly reduce switching frequency of MOS-FET3. When AC input voltage from AC power source1acomes to the high voltage range from 160 to 264 volts, switching frequency of MOS-FET3rises as an exponential function to 80 kHz with boost of AC input voltage. In an AC input voltage range from AC power source1afrom 85 to 264 volts, prior art switching power sources increase their switching frequency as an exponential function from 50 to 100 kHz. However, the switching power source according to the embodiment of the invention shown inFIG. 2can control the switching frequency in an elevated range from 50 to 80 kHz by shifting the operation form pseudo resonance to frequency reduction at the moment AC input voltage from AC power source1areaches for example 160 volts.

As mentioned above, the first embodiment of the invention is characterized in that pseudo resonance is carried out to turn MOS-FET3on at the first bottom voltage in drain-source voltage VDSacross MOS-FET3after release of energy from transformer2under the AC input voltage from AC power source1ain the low range (85 to 135 volts). Also, under the AC input voltage from AC power source1ain the high range (185 to 264 volts), MOS-FET3is late turned on by switching controller61at the moment bottom voltage detector51detects second bottom point in drain-source voltage VDSacross MOS-FET3when detection voltage VDTfrom input voltage detector31exceeds reference voltage VR2to thereby extend the off period of MOS-FET3and reduce switching frequency of MOS-FET3. In this way, the switching power source can diminish switching number of MOS-FET3to decrease switching loss and improve conversion efficiency in a wide fluctuation range of power source voltage. Also, the power source can be shifted either to the pseudo resonance mode or the reduction mode of switching frequency depending on the input voltage level to fix it in one of these modes in practical use in order to control or restrict noise produced from transformer2or the like upon shifting the power source between the pseudo resonance and frequency reduction modes.

The first embodiment shown inFIG. 2can be modified. For example,FIG. 10shows a second embodiment of the switching power source according to the present invention. In the second embodiment shown inFIG. 10, dividing resistors32and33of input voltage detector31shown inFIG. 2are connected between output terminal of input filter circuit1band ground on the primary side, and RS-flip flop45and one shot pulse generator46are substituted for inverter44of comparator41shown inFIG. 2. Input voltage detector31ofFIG. 10is designed to divide by resistors32and33AC input voltage VACapplied from AC power source1athrough input filter circuit1band to output detection voltage VDTfrom junction of resistors32and33. RS-flip flop45is set by output signal of high voltage level H from comparing circuit43of comparator41, and reset by a single pulsatile signal from one shot pulse generator46upon starting of the power source. Other components shown inFIG. 10are similar to those in the first embodiment shown inFIG. 2.

In the embodiment shown inFIG. 10, when AC voltage in a low range (85 to 135 volts) is applied from AC power source1ato input voltage detector31, detection voltage VDTon junction of resistors32and33does not indicate a peak value over reference voltage VR2of second normal power source42, and therefore, comparing circuit43produces output signal of low voltage level L unable to set RS-flip flop45. Since a single pulse is applied upon starting from one shot pulse generator46to reset terminal R of RS-flip flop45, it remains in the reset condition to produce comparative signal VCPof high voltage level H from the inverted output terminal. After that, the power source ofFIG. 10performs its pseudo resonance operation similar to that in the first embodiment shown inFIG. 2to turn MOS-FET3on at the moment drain-source voltage VDSof MOS-FET3has reached the bottom point after complete release of flyback energy from transformer2.

When AC voltage in a high range (185 to 265 volts) is applied from AC power source1ato input voltage detector31, detection voltage VDTon junction of resistors32and33includes a peak value over reference voltage VR2of second normal power source42, and therefore, comparing circuit43produces output signal of high voltage level H which sets RS-flip flop45to produce comparative signal VCPof low voltage level L from the inverted output terminal. Consequently, RS-flip flop45is retained in the set condition until one shot pulse generator46again generates a single pulsatile signal to reset terminal R of RS-flip flop45. After that, the power source ofFIG. 10performs its frequency reduction operation similar to that in the first embodiment shown inFIG. 2to turn MOS-FET3on at the moment drain-source voltage VDSof MOS-FET3has reached a second bottom point during the off period of MOS-FET3to extend the off period of MOS-FET3and decrease switching frequency of MOS-FET3.

Second embodiment shown inFIG. 10is advantageous in that RS-flip flop45can certainly keep the voltage level of comparative output signal from comparing circuit43to minimize power loss by input voltage detector31and further improve conversion efficiency in a wide fluctuation range of power source voltage. Incidentally, similar effects can be obtained in comparing an average or effective value of detection voltage VDTfrom AC input voltage VACwith reference voltage VR2in lieu of comparing a peak value of detection voltage VDTfrom AC input voltage VACwith reference voltage VR2.

FIG. 11represents a third embodiment of the switching power source according to the present invention. This power source comprises a level shift circuit34as an input voltage detector for detecting voltage VRGappearing on drive winding2cof transformer2during the on period of MOS-FET3, and a D-flip flop47adopted in place of inverter44in comparator41shown inFIG. 2. Level shift circuit34comprises level-shifting resistors35and36connected between output of power regulator23and anode terminal of rectifying diode11in auxiliary rectifying smoother13connected to drive winding2cto produce from junction of resistors35and36a detection voltage VDTfrom drive winding2cas detection voltage VDTis obtained by level-shifting in the positive direction the negative voltage VRGappearing on drive winding2cof transformer2during the on period of MOS-FET3. D-flip flop47receives output signal from comparing circuit43at the input terminal D, and outputs the received signal from comparing circuit43as a comparative signal VCPfrom output terminal Q synchronously with trailing edge of output signal VGfrom RS-flip flop21applied on clock input terminal CLK of D-flip flop47. Other components inFIG. 11are similar to those in the first embodiment shown inFIG. 2.

In the third embodiment shown inFIG. 11, drain current IDpassing through MOS-FET3directly increases during the on period of MOS-FET3as graphed inFIG. 12(A), and simultaneously drain-source voltage VDSacross MOS-FET3drops to substantially zero volt as shown inFIG. 12(B). At this time, as shown inFIG. 12(C), drive winding2cof transformer2produces a negative voltage VRGsubstantially similar in shape to drain-source voltage VDSof MOS-FET3shown inFIG. 12(B). Here, when AC voltage in a low range (85 to 135 volts) is applied from AC power source1a, drive winding2cof transformer2produces negative voltage VRGof high level as shown inFIG. 12(C)during the on period of MOS-FET3. Accordingly, detection voltage VDTfrom drive winding2con junction of resistors35and36exceeds reference voltage VR2of second normal power source42so that comparing circuit43produces output signal of high voltage level H. In this case, D-flip flop47produces comparative signal VCPfrom output terminal Q as shown inFIG. 12(E)synchronously with trailing edge of output signal VGfrom RS-flip flop21as shown inFIG. 12(D). After that, the power source performs the operation similar to that of the first embodiment shown inFIG. 2. Then, under the power input voltage in a low range, the power source does pseudo resonance to turn MOS-FET3on upon the bottom point of drain-source voltage VDSacross MOS-FET3as shown inFIG. 12(B)after transformer2has finished discharge of flyback energy stored therein.

When AC voltage in a high range (185 to 264 volts) is applied from AC power source1a, negative voltage VRGon drive winding2cis lowered during the on period of MOS-FET3as shown inFIG. 13(C). Therefore, detection voltage VDTon junction of resistors35and36is beneath reference voltage VR2of second normal power source42so that comparing circuit43produces output signal of low voltage level L. Because of this, D-flip flop47produces comparative signal VCPof low voltage level L as shown inFIG. 13(E)from the output terminal Q synchronously with trailing edge of output signal VGshown inFIG. 13(D)from RS-flip flop21. After that, the power source does the operation substantially similar to that of the power source shown inFIG. 2. Accordingly, when power input voltage in a high range is applied, the power source performs frequency reduction action to turn MOS-FET3on at the second bottom point in drain-source voltage VDSduring the off period of MOS-FET3as shown inFIG. 13(D)to extend the off period of MOS-FET3and diminish switching frequency of MOS-FET3.

In the third embodiment, during the on period of MOS-FET3, drive winding2cof transformer2produces voltage VRGproportional to AC voltage supplied from AC power source1a, and therefore, switching frequency of MOS-FET3can be controlled to an optimal frequency in response to AC voltage supplied from AC power source1aby level-shifting circuit34which detects voltage VRGon drive winding2cof transformer2. As trailing edge of output signal VGfrom RS-flip flop21appears on the order of 50 to 500 nanoseconds earlier than turning off of MOS-FET3, it is possible to avoid malfunction of comparator41resulted from switching noise occurring at the time of turning on or off of MOS-FET3by detecting voltage VRGfrom drive winding2cof transformer2synchronously with trailing edge of output signal VGfrom RS-flip flop21and before turning on or off of MOS-FET3.

FIG. 14shows a fourth embodiment of the switching power source according to the present invention wherein hysteretic comparator71is substituted for comparing circuit43shown inFIG. 2. Hysteretic comparator71comprises a first reference voltage for shifting output signal from low voltage level L to high voltage level H; and a second reference voltage for shifting output signal from high voltage level H to low voltage level L, and the first and second reference voltages are different from each other to provide the hysteretic characteristics. For example, a first reference voltage VRHof second normal power source42is higher than a second reference voltage VRL. In the circuit shown inFIG. 14, first reference voltage VRHis nearly equal to detection voltage VDTwhen input voltage detector31detects an AC voltage of 170 volts from AC power source1a, and second reference voltage VRLis nearly equal to detection voltage VDTwhen input voltage detector31detects an AC voltage of 150 volts from AC power source1a. Other components shown inFIG. 14are substantially similar to those in the embodiment shown inFIG. 2.

In the fourth embodiment shown inFIG. 14, when AC input voltage from AC power source1ais elevated from 85 volts to 170 volts, hysteretic comparator71produces output of low voltage level L to produce output signal VCPof high voltage level H from comparator41so that the power source performs pseudo resonance action to increase switching frequency of MOS-FET3from 50 kHz in an exponential function with elevation of AC input voltage as shown inFIG. 15. When AC input voltage from AC power source1areaches 170 volts, hysteretic comparator71changes the output signal from low voltage level L to high voltage level H to shift the operation mode from pseudo resonance to frequency reduction, and therefore, switching frequency of MOS-FET3rapidly drops as shown by dotted line A inFIG. 15. Further, when AC input voltage from AC power source1arises from 170 volts to 264 volts, switching frequency of MOS-FET3increases up to around 80 kHz in exponential function with elevation of AC input voltage under the frequency reduction action as shown inFIG. 15. When AC input voltage from AC power source1afalls from 264 volts to 150 volts, hysteretic comparator71changes output signal from high voltage level H to low voltage level L to shift the operation mode from frequency reduction to pseudo resonance, rapidly increasing switching frequency of MOS-FET3as shown by dotted line B inFIG. 15. When AC input voltage from AC power source1afalls beneath 150 volts, switching frequency declines in exponential function with reduction of AC input voltage under the pseudo resonance action.

In the fourth embodiment, the power source can stably be operated in a wide variation range of power voltage by hysteretic action between 150 volts and 170 volts of AC input voltage from AC power source1aunder the smooth control of switching frequency for MOS-FET3with variation of power source voltage.

FIG. 16shows a fifth embodiment of the switching power source according to the present invention wherein control circuit8comprises a voltage-dividing resistor37connected between resistor33and ground on the primary side to form an input voltage detector31for producing first and second detection voltages VDT1and VDT2respectively from first and second junctions between resistors32and33and between resistors33and37; a second comparing circuit48and a second inverter49connected in parallel to first comparing circuit43and first inverter44shown inFIG. 2to form a comparator41for producing first and second comparative signals VCP1and VCP2from first and second inverters44and49; a third D-flip flop66connected in series to first and second D-flip flops62and63in switching controller61shown inFIG. 2; and a second AND gate67for producing a logical product signal VAD2of output signal VDF2from second D-flip flop63and output signal VCP2from second inverter49. Other components inFIG. 16are generally similar to those shown inFIG. 2.

In operation of the fifth embodiment shown inFIG. 16, when AC input voltage in a low range (85 to 135 volts) is supplied from AC power source1a, both of first and second detection voltages VDT1and VDT2on first and second junctions do not exceed reference voltage VR2of second normal power source42, and therefore, first and second comparative signals VCP1and VCP2generated from first and second inverters44and49through first and second comparing circuits43and48are on high voltage level as shown inFIGS. 17(D) and 17(E). Meanwhile, drain-source voltage VDSacross MOS-FET3is retained substantially constant during the off period of MOS-FET3, but begins to fall just at the moment transformer2has completed release of flyback energy contained therein as shown inFIG. 17(B), and output signal VBDfrom bottom voltage detector51is switched from the high level H to the low level L around a bottom point of drain-source voltage VDSas shown inFIG. 17(C). Accordingly, first D-flip flop62produces signal VDF1of high voltage level H from output terminal Q synchronously with a first trailing edge of output signal VBDfrom bottom voltage detector51, and simultaneously first AND gate64produces first logical product signal VAD1of high voltage level H. In this case, second and third D-flip flops63and66produce signals VDF2and VDF3of both low voltage level L from output terminals Q, and second AND gate67produces second logical product signal VAD2of low voltage level. Accordingly, OR gate65produces logical sum signal VONof high voltage level H to set RS-flip flop21. Accordingly, RS-flip flop21provides gate terminal of MOS-FET3with drive signal VGof high voltage level H through buffer amplifier22to turn MOS-FET3on in synchronization with first trailing edge of output signal VBDfrom bottom voltage detector51. Then, drain current IDflowing through MOS-FET3linearly increases as shown inFIG. 17(A), and when detection voltage VOCPacross current detection resistor9reaches detection signal VFBfrom output voltage detector7, mode control comparator18produces signal V2of high voltage level H to reset RS-flip flop21. Therefore, RS-flip flop21provides gate terminal of MOS-FET3with drive signal VGof low voltage level L through buffer amplifier22to turn MOS-FET3off. This process is repeated for carrying out pseudo resonance action to turn MOS-FET3on at the same time drain-source voltage VDSacross MOS-FET3indicates the bottom point after completion of flyback energy exhaustion from transformer2in the low range of power input voltage.

When AC input voltage in an intermediate range (165 to 200 volts) is supplied from AC power source1a, first detection voltage VDT1on first junction between resistors32and33exceeds reference voltage VR2of second normal power source42so that first comparing circuit43and first inverter44produce first comparative signal VCP1of low voltage level L as shown inFIG. 18(D). Meanwhile, second detection voltage VDT2on second junction between resistors33and37does not exceed reference voltage VR2of second normal power source42so that second comparative signal VCP2generated through second comparing circuit48and second inverter49remains on high voltage level H as shown inFIG. 18(E). Also, drain-source voltage VDSis retained nearly constant during the off period of MOS-FET3, but starts dropping immediately upon completion of flybak energy discharge from transformer2as shown inFIG. 18(B)to switch output signal VBDfrom bottom voltage detector51from high voltage level H to low voltage level L around the bottom point of drain-source voltage VDS. Therefore, first comparing circuit43and first inverter44produce first comparative signal VCP1of low voltage level L to keep first AND gate64off although first D-flip flop62produces signal VDF1of high voltage level H on output terminal Q in synchronization with first trailing edge of output signal VBDfrom bottom voltage detector51. Accordingly, first AND gate64produces first logical product signal VAD1of low voltage level L to OR gate65. Also, second D-flip flop63produces signal VDF2of high voltage level H at output terminal Q synchronously with a second trailing edge of output signal VBDfrom bottom voltage detector51shown inFIG. 18(C). In another aspect, second comparing circuit48and second inverter49produce second comparative signal VCP2of high voltage level H so that second AND gate67produces second logical product signal VAD2of high voltage level H to OR gate65. In addition, third D-flip flop66produces signal VDF3of low voltage level L from output terminal Q to OR gate65which then generates logical sum signal VONof high voltage level H to set RS-flip flop21. Accordingly, RS-flip flop21and buffer amplifier22provide gate terminal of MOS-FET3with drive signal VGof high voltage level H to turn MOS-FET3on synchronously with a second trailing edge of output signal VBDfrom bottom voltage detector51. Thus, drain current IDflowing through MOS-FET3directly increases as shown inFIG. 18(A). When detection voltage VOCPacross current detection resistor9comes up to detection signal VFBfrom output voltage detector7, mode control comparator18produces signal V2of high voltage level H to set RS-flip flop21. And, RS-flip flop21and buffer amplifier22forward drive signal VGof low voltage level L to gate terminal of MOS-FET3to turn MOS-FET3off. Thus, in the intermediate range of power voltage supply, the power source performs the frequency reduction action with the short off period of MOS-FET3to turn MOS-FET3concurrently with detection of the second bottom point in drain-source voltage VDSduring the off period of MOS-FET3.

In the high range of AC input voltage (220 to 264 volts) from AC power source1a, both of first and second detection voltages VDT1and VDT2on first and second junctions are over reference voltage VR2of second normal power source42, and first and second comparing circuits43and48and first and second inverters44and49produce first and second comparative signals VCP1and VCP2of low voltage level as shown inFIGS. 19(D) and 19(E). In addition, drain-source voltage VDSacross MOS-FET3is kept on the high level during the off period of MOS-FET3, but starts dropping coincidentally with completion of flyback energy release from transformer2as shown inFIG. 19(B)to switch output signal VBDfrom bottom voltage detector51from high voltage level H to low voltage level L around a bottom point in drain-source voltage VDSas shown inFIG. 19(C). Since first and second comparing circuits43and44and first and second inverters44and49produce first and second comparative signals VCP1and VCP2of low voltage level L, first and second AND gates64and67are retained off to bar signals VDF1and VDF2of high voltage level H from output terminals Q of first and second D-flip flops62and64. Accordingly, first and second AND gates64and67produce first and second logical product signals VAD1and VAD2of low voltage level L to OR gate65. Also, third D-flip flop66produces signal VDF3of high voltage level H to OR gate65synchronously with detection of third trailing edge in output signal VBDfrom bottom voltage detector51so that OR gate65sends RS-flip flop21logical sum signal VONto set RS-flip flop21. Accordingly, RS-flip flop21causes buffer amplifier22to produce drive signal VGof high voltage level H to gate terminal of MOS-FET3to turn MOS-FET3on. Consequently, drain current IDstarts flowing through MOS-FET3to linearly increase as shown inFIG. 19(A). When detection voltage VOCPacross current detection resistor9comes up to detection signal VFBfrom output voltage detector7, mode control comparator18produces signal V2of high voltage level H to reset RS-flip flop21. Therefore, RS-flip flop21makes buffer amplifier22produce drive signal VGof low voltage level L to gate terminal of MOS-FET3to turn MOS-FET3off. Thus, in the high range of power input supply, the power source performs the frequency reduction action with the long off period of MOS-FET3to turn MOS-FET3on synchronously with detection of third bottom point in drain-source voltage VDSduring the off period of MOS-FET3.

FIG. 20shows a switching frequency characteristics of MOS-FET3with AC input voltage from AC power source1ain the fifth switching power source shown inFIG. 16. The power source performs pseudo resonance action in the low range of AC input voltage from 85 volts to 135 volts to increase in exponential function the switching frequency of MOS-FET3from 50 kHz with elevation of AC input voltage. When AC input voltage reaches 150 volts, the switching frequency of MOS-FET3rapidly drops to move from pseudo resonance action to frequency reduction action with the short off period of MOS-FET3in an intermediate range of AC input voltage from 165 volts to 200 volts, also increasing the switching frequency of MOS-FET3in exponential function with elevation of AC input voltage. When AC input voltage from AC power source1areaches 210 volts, control circuit8rapidly reduces the switching frequency of MOS-FET3to move from frequency reduction with the short off period of MOS-FET3to frequency reduction with the long off period of MOS-FET3. Moreover, in a high range from 220 volts to 264 volts of AC input voltage from AC power source1a, control circuit8performs frequency reduction action with the long off period of MOS-FET3to increase switching frequency up to around 70 kHz in exponential function with elevation of AC input voltage.

The fifth embodiment has the feature of two stage reduction in switching frequency for MOS-FET3in a relatively high range (165 to 264 volts) of AC input voltage from AC power source1ato provide MOS-FET3with the switching control mode for narrower variation ranges and finer control of switching frequency than that in the first embodiment.

The embodiments of the present invention may be varied in various ways without limitation to the foregoing five embodiments. For example, structural features in fourth and fifth embodiment may be applied to second or third embodiment in lieu of first embodiment. Also, AC voltage from AC power source1afor switching the control mode of MOS-FET3shown in each of first to fifth embodiments may be of optional values from 85 to 264 volts without restriction to the foregoing values. Also, control circuit8can comprises four or more stage of D-flip flops in the fifth embodiment. In this case, increase in the stage number of D-flip flops provides narrower variation range of switching frequency in changing the control mode for switching frequency of MOS-FET3for finer control of switching frequency with more stage number of D-flip flops. Moreover, in lieu of indirectly detecting bottom points in ringing voltage VRGappearing on drive winding2cof transformer2during the off period of MOS-FET3to pick out bottom points in drain-source voltage VDSof MOS-FET3, bottom voltage detector51may directly detect bottom points in drain-source voltage VDSof MOS-FET3during the off period of MOS-FET3. The above-mentioned embodiments utilizes MOS-FET3as a switching element, but available switching element3may include J-FET (Junction Type Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), SIT (Static Induction Transistor), PNP and NPN bipolar transistors. Switching power sources according to the present invention are effectively available in a wide variation range of power input voltage.