Tile-based routing method of a multi-layer circuit board

A routing method for routing a plurality of signal traces out of a plurality of corresponding bumper pads in a multi-layer circuit board. The multi-layer circuit board includes at least a first layer and a second layer. The method includes arranging the plurality of bumper pads based on a plurality of triangle units, routing a plurality of signal traces out of a plurality of corresponding bumper pads of in the first layer, routing a plurality of signal traces out of a plurality of corresponding bumper pads in the second layer not to be vertically parallel with the plurality of signal traces routed in the first layer, and arranging a plurality of shielding traces among the plurality of signal traces in the first layer and in the second layer.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to a routing method for routing a plurality of signal traces out of corresponding bumper pads in a multi-layer circuit board, and more particularly, to a tile-based routing method for routing a plurality of signal traces and a plurality of shielding traces in the multi-layer circuit board.

2. Description of the Prior Art

In modern society with developed computer technology, the computer system, which comprises a plurality of integrated circuits, has been utilized in a broad spectrum of fields. For example, household appliances with automatic control systems, mobile communication devices, and personal computers utilize integrated circuits to perform certain functions. The main body of the IC is a die manufactured by a prior-art semiconductor process. The manufacturing process of the die starts from forming a wafer. Each wafer is divided into a plurality of regions. On each region, many circuits are formed through the prior art semiconductor process. In the end, each processed region on the wafer is sliced to generate a plurality of dies. After the required die is obtained, it requires a specific way to electrically connect the processed die with a circuit board such as a printed circuit board (PCB). Therefore, the die is capable of acquiring its operating voltage from the PCB for performing a predetermined operation. For instance, suppose that the IC die corresponds to an encoder circuit. After the encoder circuit is provided with an appropriate operating voltage, the IC die (encoder circuit) is capable of encoding data inputted from the circuit board, and then returns the encoded data to the circuit board.

Certain IC dies, called wire-bond IC dies, are fabricated with metal bonding pads only along their periphery. These peripheral pads serve as terminals for connecting the die to external signals, including control signals, power and ground. Typically, the wire-bond IC die is mounted within a plastic or ceramic package having multiple pins, and wire connections are made between the die's bonding pads and the package's pins. However, the above-mentioned packaging method has its limitations. First, because only the periphery of the die is used for external connection pads, the number of such pads for a given sized die is limited. In particular, advances in technology which permit more and more gates to be placed within a given die area have resulted in an increased demand for such pads, particularly power and ground pads. In certain cases, the design requires more pads than can be provided solely at the die's periphery. Second, when all the pads are provided only at the die's periphery, additional routing is required to bring the corresponding signals, particularly power and ground signals, to the interior logic of the die. Third, in wire-bond dies, the wire connections between the die and the package pins introduce additional resistance and inductance, which sometimes may spoil the die's performance.

The flip-chip packaging, which is developed to overcome the above-mentioned problems, has become a more preferable packaging method nowadays. The flip-chip packaging technology allows the overall package size to be made significantly compact. The connections between the IC die and the exterior electrical components offer a lower inductance and resistance electrical connection than wire-bond packaging. In addition, the shorter connection path of power and ground improves the power supplement quality. However, even based on the flip-chip packaging technique, a basic and inevitable principle is that the die size should be subject to the size and quantity of the spreading bumpers. Due to that nowadays, companies developing and manufacturing electronic products are challenged by a blooming market demand for smaller, more efficient, and a higher performance product, bringing down the relative die size to meet the cost concern becomes a crucial issue.

For achieving the space-saving advantage, a multi-layer substrate (circuit board) should also be included in an electrical system. The current fabrication process of the multi-layer substrate could be sorted into different methods, including a laminated substrate, and a build-up substrate. The build-up substrate among them would be the most suitable one for a high pin-count application to extend the density capability of the conventional circuit board due to its thin signal trace (30Î¼m). Please refer to bothFIG. 1andFIG. 2.FIG. 1is a schematic diagram showing a typical arrangement of a die10located on a 6-layer build-up substrate12, andFIG. 2is a schematic diagram of an embodiment of the 6-layer build-up substrate12shown inFIG. 1. The 6-layer build-up substrate12includes 4 build-up layers (layers12A,12B,12E, and12F) for routing a plurality of signal traces. Each build-up layer provides a 25/25Î¼m trace width/space, and an 110Î¼m via12G. The other two traditional layers C, D respectively provides a 100/100Î¼m trace width/space and a 440Î¼m via12H. Due to the structure of the 6-layer build-up substrate12, when the 6-layer build-up substrate12is actually implemented, only the 4 build-up layers (layers12A,12B,12E, and12F) would be used for signal-trace routing functions. The remaining layers (two traditional layers12C,12D) can be used to provide power and ground spreading due to that the wide via (440Î¼m)12H between the layer12C and the layer12D is unfavorable for many signal traces to pass through. Please refer toFIG. 3, which is a detailed schematic diagram describing the region14shown inFIG. 1. The embodiment inFIG. 3shows a plurality of signal traces18spread from the die10and routed in the 6-layer build-up substrate12shown inFIG. 2. The embodiment inFIG. 3shows that all the signal traces18are designed to be routed in the build-up layers12A,12B. Therefore, all the signal traces18can be classified into first-layer traces18(1) and second-layer traces18(2), respectively representing the signal traces18routed in the build-up layers12A and in the build-up layers12B. Please also refer toFIG. 4, which is a schematic diagram illustrating a plurality of bumper pads20arranged over the die10as shown inFIG. 1andFIG. 3. The plurality of bumper pads20will be used as the input/output terminals for the die10. The signal traces18as shown inFIG. 1orFIG. 3can be routed out of a plurality of corresponding bumper pads20located on either a periphery area of the die10, called die periphery22, or a center area24of the die10.

Please return to refer toFIG. 1andFIG. 2. When those signal traces18start to fan out from the bumper pads20of the die10, the assumed area16is not so wide to accommodate so huge wide vias12H. Therefore, there would be very few signal traces18being routed down to the build-up layers12E,12F. That also explains why the signal traces18are almost routed in the build-up layers12A,12B (top2layers) as shown inFIG. 3. As you can see in theFIG. 4, when using flip-chip techniques, a typical IC die10often will contain hundreds of bumper pads20. Routing the signal traces18from each of these bumper pads20to the appropriate position on the die10can therefore become a complicated task. In addition, these large amounts of bumper pads20have to be assigned closer to get a more effective use of the routing space on the substrate12. In the meanwhile, the (6-layer) build-up substrate12is required to provide a more aggressive signal routing density within a certain area and higher flexibility of fanning out the signal traces18. However, the higher signal trace density and lower die size will also introduce the smaller space among all the signal traces18, which would worsen the cross-talk effect (mostly the capacitive cross-talk) between signals and bring down the signal quality.

SUMMARY OF INVENTION

It is therefore a primary objective of the claimed invention to provide a tile-based routing method for routing a plurality of signal traces and a plurality of shielding traces in the multi-layer circuit board to solve the above-mentioned problems.

In the claimed invention, a routing method for routing a plurality of signal traces out of a plurality of corresponding bumper pads in a multi-layer substrate (circuit board) is proposed. According to a specific arranging principle, those bumper pads are grouped into a plurality of bumper-tile blocks. When being implemented, the plurality of signal traces are only routed in the first layer and the second layer of the multi-layer substrate. The third layer of multi-layer substrate is used for power and ground connections. In addition, a plurality of shielding traces are arranged among the plurality of signal traces in the first layer and in the second layer for providing shielding functions.

In the claimed invention, based on a specific arrangement of bumper pads in each bumper-tile block, a plurality of first-layer traces are routed straight forward, while a plurality of second-layer traces are routed with a turn not to be vertically parallel with the plurality of first-layer traces. The easy and useful arrangements of assigning bumper pads and routing signal traces out of the bumper pads are derived.

According to the claimed invention, a routing method for routing a plurality of signal traces out of a plurality of corresponding bumper pads in a multi-layer circuit board is disclosed. The multi-layer circuit board comprises at least a first layer and a second layer, and the method comprises arranging the plurality of bumper pads based on a plurality of triangle units; routing a plurality of signal traces out of a plurality of corresponding bumper pads of in the first layer; routing a plurality of signal traces out of a plurality of corresponding bumper pads in the second layer not to be vertically parallel with the plurality of signal traces routed in the first layer; and arranging a plurality of shielding traces among the plurality of signal traces in the first layer and in the second layer.

According to the claimed invention, a tile-based routing method for routing a plurality of signal traces out of a plurality of corresponding bumper pads in a multi-layer circuit board is disclosed. The multi-layer circuit board comprises at least a first layer and a second layer. The method comprises arranging the plurality of bumper pads as a bumper-tile block by a specific forming process; assigning a plurality of signal traces corresponding to a plurality of bumper pads of the bumper-tile block as a plurality of first-layer traces being routed in the first layer; assigning a plurality of signal traces corresponding to a plurality of bumper pads of the bumper-tile block as a plurality of second-layer traces being routed in the second layer; routing the plurality of first-layer traces straight forward; routing the plurality of second-layer traces with a turn not to be vertically parallel with the plurality of first-layer traces; and shielding the plurality of first-layer traces and the plurality of second-layer traces.

According to the claimed invention, a method for routing a plurality of signal traces out of a plurality of corresponding bumper pads for implementation of a die on a multi-layer circuit board is disclosed. The method comprises utilizing the plurality of bumper pads positioned in a periphery area of the die; utilizing a plurality of power/ground bumper pads positioned in a center area of the die; arranging the plurality of bumper pads in a specific forming process; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of first-layer traces being routed in a first layer of the multi-layer circuit board; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of second-layer traces being routed in a second layer of the multi-layer circuit board wherein the second layer is vertically beneath the first layer; routing the plurality of first-layer traces straight away from the die; routing the plurality of second-layer traces with a turn not to be vertically underneath the first-layer traces; and shielding the plurality of first-layer traces and the plurality of second-layer traces by routing a plurality of shielding traces out of the plurality of power/ground bumper pads.

DETAILED DESCRIPTION

Please refer toFIG. 5, which is a schematic diagram showing a first arrangement of partial bumper pads31–38and a plurality of corresponding signal traces39–46. The arrangement of the bumper pads is highly relevant to a die size of a high pin count chip. With the flip chip packaging, the die size (the embodiment of die10is shown inFIG. 1andFIG. 4) is subject to 2 items, quantity of the bumper pads and a required area in which the plurality of corresponding signal traces are routed. As shown inFIG. 5, the bumper pads3138are assigned on a multi-layer substrate82. The multi-layer substrate82comprises at least a first layer82A and a second layer82B (the second layer82B is vertically underneath the first layer82A). The multi-layer substrate82can be the 6-layer build-up substrate12described inFIG. 2(the first layer82A corresponds to the build-up layer12A, and the second layer82B corresponds to the build-up layer12B) or any other multi-layer circuit board. The distance between each bumper pad, named bumper pitch, is minimum distance, 227Î¼m, under the current fabrication process. The width of each bumper pad is 110Î¼m under the current fabrication process. A plurality of signal traces3942are respectively routed out of the bumper pads31,32,35and36in the first layer82A of the multi-layer substrate82. The minimum width of the signal trace is 25Î¼m and the minimum space between adjacent signal traces is also 25Î¼m. After easy calculation, the space between the bumper pad31and the bumper pad35is 112Î¼m (227−115=112), which only allows one signal trace to pass through. Therefore, the signal traces43-46corresponding to the bumper pads33,34,37and39could only be assigned to occupy the second layer82B, and those signal traces43–46in the second layer82B are drawn in dotted lines. Please notice that the bumper pad31or35cannot be assigned as a power or ground pad. If the bumper pads31and35are occupied by power or ground functions, the two corresponding signal traces would be lost. Thus, more bumper pads are required, and a larger die periphery (as the die periphery22shown inFIG. 4) is required to fit these bumper pads in. Therefore, the above-mentioned method is not a cost saving way. Due to the above-mentioned problem, an effective arrangement of bumper pads favorable for die size minimization can refer toFIG. 4, which is a schematic diagram illustrating a plurality of bumper pads20arranged over a die10as shown inFIG. 1. The die periphery22contains the bumper pads corresponding to all input/output signal traces of the die10. That is, all signal traces related to the input/output signal applications are assigned to occupy all the peripheral area of the die10, the die periphery22. The center area24of the die10belongs to the power/ground bumper-pad occupation.

According to the embodiment of arrangement of the plurality of bumper pads31–38as shown inFIG. 5, all signal traces39–46will be arranged to come out closely from the die periphery22for avoiding losing any available space. Under very high routing density, before the signal traces start to fall apart from each other, the space between two adjacent signal traces is very close (the above-mentioned minimum space is only 25Î¼m). Therefore, the electromagnetic interference between signal traces would become a significant factor to influence the transmitting signal quality. Please refer toFIG. 5. The signal traces39–46routed either in the same layer or in different layers are parallel arranged. Thus the interference source for each signal trace will not only come from the adjacent signal traces routed in the same layer, but also come from the adjacent signal traces routed in the different layers. In the same layer, taking the first layer82A for instance, the signal traces39–42would be significantly interfered by the neighboring signal traces due to the close space and no shielding protection. Taking both layers (the first layer82A and the second layer82B) into consideration, there is not any shielding trace allowed to be installed for providing signal-quality protection due to the insufficient space. Please refer toFIG. 6, which is a schematic diagram showing a 3-dimensional drawing of a portion of the multi-layer substrate82as shown inFIG. 5. The signal traces3941are routed in the first layer82A of the multi-layer substrate82, and other three signal traces4345are routed in the second layer82B of the multi-layer substrate82. There is another layer47representing the dialectical material between the first layer82A and the second layer82B. When the signal traces39,41, and44are switched to operate simultaneously, the signal trace40is significantly interfered by the three adjacent signal traces39,41, and44in both vertical and horizontal directions. The interference effects among the signal traces will be worsen in a build-up substrate12as shown inFIG. 2, since the distance between the first layer82A and the second layer82B is only 30Î¼m. Therefore, a whole new arrangement of bumper pads and routing pattern should be provided to improve the signal quality on the premise that the corresponding die size can be reduced or at least not significantly increased.

Based on the above-mentioned limitations concerning widths and spaces under current fabrication process, the present invention addresses proper ways related to assigning bumper pads, power/ground bumpers, and the routing of signal trace from the bumper pads in the multi-layer substrate82. Please refer back toFIG. 5. As in the previous descriptions, only one signal trace is allowed to pass through two adjacent bumper pads with minimum bumper pitch (227Î¼m). For clarifying the difference between a novel bumper-pad arrangement and the above-mentioned bumper-pad arrangement shown inFIG. 5, a bumper-tile block is introduced and defined. Please refer toFIG. 7, which is a schematic diagram showing both a second arrangement of a plurality of bumper pads51–58and the first arrangement of the 8 bumper pads31–38shown inFIG. 5. The 8 bumper pads31–38can be treated as a first bumper-tile block84corresponding to the first arrangement, and another 8 bumper pads51–58can be treated as a second bumper-tile block86corresponding to the second arrangement. Each bumper-tile block, either the first bumper-tile block84or the second bumper-tile block86, includes 8 bumper pads and is capable of carrying8signal traces in the first layer82A and the second layer82B of the multi-layer substrate82(as the 6-layer build-up substrate12shown inFIG. 2). Please notice that the novel second arrangement of the 8 bumper pads51–58is just an embodiment of the present invention regarding the arrangement of bumper pads51–58, and a little modifications toward the second bumper-tile block86are included in the characteristics of the present invention. The following descriptions will detail the evolution from the first bumper-tile block84to the second bumper-tile block86.

First of all, each bumper-tile block can be treated to be composed of a plurality of units of various shapes. Please refer toFIG. 7. Originally, the first bumper-tile block84can be treated to be composed of a plurality of square units84a, and the related characteristics of the first arrangement have described in the previous embodiment as shown inFIG. 5. According to the present invention, the shape of each unit, which determines the shape of the corresponding bumper-tile block, is changed to be triangle as shown inFIG. 7. Those triangle units86aare with equal lengths of each side. All the bumper pitches remain the same as those in the first bumper-tile block84. However, when the shape of each unit changes, the occupation area of the corresponding bumper-tile block, which determines the die size, is also changed. A first block width of the first bumper-tile block84is about 342Î¼m (minimum bumper pitch+pad width: 227+115=342(Î¼m)), and a first block height is about 796Î¼m (3×minimum bumper pitch+pad width: 681+115=796(Î¼m)). After the new arrangement, A second block width of the second bumper-tile block86is about 455.5Î¼m (1.5×minimum bumper pitch+pad width: 340.5+115=455.5(Î¼m)), and a second block height is 7001Î¼m (1.5*â*minimum bumper pitch+pad width: 590+115=700(Î¼m)). The above-mentioned easy calculations show that the arrangement of the second bumper-tile block86leads to an increase in block width but a cutback in block height comparing to the arrangement of the first bumper-tile block84. The new arrangement of the second bumper-tile block86will not cause much extra die size and will bring the characteristics of the present invention into full play.

Based on the arrangement of the second bumper-tile block86, a routing method for routing a plurality of (8) signal traces out of the corresponding (8) bumper pads of the second bumper-tile block86in the multi-layer substrate82can be disclosed. As previous mentions, the signal traces are routed in the first layer82A and the second layer82B of the multi-layer substrate82. Please refer toFIG. 8, which is a flowchart of an embodiment of the present invention based on the second bumper-tile block86shown inFIG. 7. The operating steps are as follows:

Step100: arrange the plurality of bumper pads based on a plurality of triangle units;

Step101: route a plurality of signal traces out of a plurality of corresponding bumper pads in the first layer;

Step102: route a plurality of signal traces out of a plurality of corresponding bumper pads in the second layer not to be vertically parallel with the plurality of signal traces routed in the first layer;

Step103: Arrange a plurality of shielding traces among the plurality of signal traces in the first layer and in the second layer.

Please notice that the shape of each unit should not be limited as an equilateral triangle, and various types of triangles are acceptable for designing the shape of each unit according to the invention. In addition, the quantity of bumper pads in the second bumper-tile block86should not be limited as 8, and the quantity of bumper pads in the second bumper-tile block86can be adjusted according to the practical requirements. Please refer toFIG. 9, which is a schematic diagram showing the second bumper-tile block86shown inFIG. 7combined with corresponding signal traces and shielding traces. As shown inFIG. 9, the bumper pads5158are assigned on the multi-layer substrate82. A plurality of signal traces5962are respectively routed out of the bumper pads51,52,55and56in the first layer82A of the multi-layer substrate82. The other 4 signal traces63–66corresponding to the bumper pads53,54,57and59will be assigned to occupy the second layer82B, and those signal traces in the second layer82B is filled with slanted lines. Please notice that in the first layer82A,4shielding traces6770(thin lines) are arranged among the 4 signal traces5962for providing shielding functions between the adjacent signal traces in the first layer82A. Similarly, in the second layer82B, another 4 shielding traces7174(thin lines filled with slanted lines) are arranged among the 4 signal traces6366for providing shielding functions between the adjacent signal traces in the second layer82B.

The routing method as shown inFIG. 9can be evolved from the embodiment shown inFIG. 5step by step. Please refer toFIG. 10, which is a schematic diagram showing evolution from the embodiment shown inFIG. 5to the embodiment shown inFIG. 9.FIG. 10includes 5 embodiments A–E, including the embodiment shown inFIG. 5and the embodiment shown inFIG. 9, and the embodiment E is totally the same as the embodiment shown inFIG. 9. The embodiment A is modified from the embodiment shown inFIG. 5. The signal traces4346in the second layer82B make turns immediately after depart from bumper pads33,34,37,38to prevent being routed parallel with the signal traces3942in the first layer82A. Afterwards, in the embodiment B, the bumper-tile block is modified to be the same as the second bumper-tile block86shown inFIG. 7andFIG. 9. In the meanwhile, a routing principle is built for routing all the signal traces18: “the signal traces in the first layer82A going straight forward, and the signal traces in the second layer82B turn when starting to fan out”. Therefore, all the signal traces will fall apart to avoid from parallel routing in different layers. Until now, only one problem, the vertical interference, is solved. The horizontal interference among signal traces in the same layer requires a more aggressive method, which is adding shielding traces. Please refer to the embodiment C, which shows routing of signal traces in the first (upper) layer, the shielding traces67–70are routed between the signal traces5962in the first layer82A. Similarly, please refer to the embodiment D, which shows routing of signal traces in the second (lower) layer82B, the shielding traces71–74are routed between the signal traces6366in the second layer82B. After combining the characteristics of the embodiment C and the embodiment D, the desired embodiment E is generated.

Based on the embodiment E shown inFIG. 10and the above-mentioned routing principle, another detailed embodiment of routing method for routing a plurality of (8) signal traces out of the corresponding (8) bumper pads of the second bumper-tile block86in the multi-layer substrate82can be disclosed. Please refer toFIG. 11, which is a flowchart of another embodiment of the present invention based on the embodiment E shown inFIG. 10. The operating steps are as follows:

Step200: arrange the plurality of bumper pads as a bumper-tile block by a specific forming process, and the plurality of bumper pads are composed of a plurality of triangle units;

Step201: assign a plurality of signal traces corresponding to a plurality of bumper pads of the bumper-tile block as a plurality of first-layer traces being routed in the first layer. In the embodiment E shown inFIG. 10, the first-layer traces are signal traces59–62;

Step202: assign a plurality of signal traces corresponding to a plurality of bumper pads of the bumper-tile block as a plurality of second-layer traces being routed in the second layer. In the embodiment E shown inFIG. 10, the second-layer traces are signal traces63–66;

Step203: route the plurality of first-layer traces straight forward;

Step204: route the plurality of second-layer traces with a turn not to be vertically parallel with the plurality of first-layer traces;

Step205: arrange a first-layer shielding trace between every two adjacent first-layer traces in the first layer. In the embodiment E shown inFIG. 10, the first-layer shielding traces are shielding traces67–70;

Step206: arrange a second-layer shielding trace between every two adjacent second-layer traces in the second layer. In the embodiment E shown inFIG. 10, the second-layer shielding traces are shielding traces71–74.

The derived easy and useful routing principle “the signal traces in the first layer82A going straight forward, and the signal traces in the second layer82B turn when starting to fan out” gives an instruction to solve a complicated task of routing the signal traces out of a large amount of bump pads on a die80(the die80can corresponds to the die10shown inFIG. 1). For clearly emphasizing the structure of the present invention,FIG. 12is introduced for the explanation.FIG. 12is a cross-section diagram of the embodiment E shown inFIG. 10as well as the embodiment shown inFIG. 9. Obviously, the multi-layer substrate82further comprises a third layer82C beneath the second layer82B used as a ground plane. The signal traces59,60are the first-layer traces (defined inFIG. 11) routed in the first layer82A of the multi-layer substrate82. The signal traces63,64are the second-layer traces18(2) routed in the second layer82B of the multi-layer substrate82. The signal trace60is shielded by two first-layer shielding traces67,68at both side and a second-layer shielding trace72underneath. Therefore, each signal trace in the first layer82A, except a plurality of marginal signal traces (as the signal trace59), is surrounded by 3 shielding traces, two of which are horizontally parallel with the signal trace and the other is vertically parallel with the signal trace. Similar to the second-layer signal traces, taking the signal trace63as example, both sides of it are respectively shielded by two second-layer shielding traces71,72. In addition, a first-layer shielding trace705lies above it, and the third layer82C lies beneath it. Therefore, each signal trace in the second layer82B is surrounded not only by 3 shielding traces but also a ground plane beneath (the third layer82C). According to the present invention, all of the signal traces can be completely and well protected, and then the capacitive interference would be reduced significantly.

After all, all the bumper pads related to the signal traces should be combined to form a die periphery92. Please refer toFIG. 13, which is a schematic diagram illustrating a plurality of bumper pads90with the corresponding routed first-layer tracers88arranged over a die80according to the present invention. The die80comprises a center area94and a die periphery92. The embodiment shown inFIG. 13, which is similar with the embodiment as shown inFIG. 4, adapts the characteristics of the above-mentioned embodiments of the present invention. All signal traces (including the first-layer tracers88) are routed uniformly and interlaced with (ground) shielding traces, and theFIG. 13only shows first-layer shielding traces89drawn in dotted lines. Regarding each side of the die80edge, each first-layer tracer88goes forward parallel with shielding traces89until it reaches its via to be connected to the corresponding soldering ball. Moreover, all signal traces (including the first-layer tracers88) are routed out of the corresponding bumper pads90located on the die periphery92, and other bumper pads related to power/ground functions are positioned in the center area24of the die80.

In the present invention, a novel routing method, which is applied to a flip chip packaging technique, for routing a plurality of signal traces out of a plurality of corresponding bumper pads in a multi-layer substrate is proposed. The bumper pads are grouped into a plurality of bumper-tile blocks and arranged based on a plurality of triangle units. When being implemented, the plurality of signal traces are only routed in the first layer and the second layer of the multi-layer substrate. The third layer of multi-layer substrate is used for power and ground connections. In addition, a plurality of shielding traces are arranged among the plurality of signal traces in the first layer and in the second layer for providing shielding functions without the requirement of extra space occupation.