Semiconductor device having barrier region and edge termination region enclosing barrier region

A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface, wherein each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer, and each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to <11-20> direction of crystal orientations of the semiconductor substrate.

BACKGROUND

1. Technical Field

The present disclosure relates to semiconductor devices and methods for manufacturing the same. In particular, the present disclosure relates to semiconductor devices including silicon carbide, and to methods for manufacturing the same.

2. Description of the Related Art

Silicon carbide (SiC) is a semiconductor material having a larger bandgap and a higher hardness than silicon (Si). For example, SiC is used in power devices such as switching devices and rectifying devices. SiC power devices have advantages over Si power devices such as low power loss.

Some typical semiconductor devices using SiC are metal-insulator-semiconductor field-effect transistors (MISFETs) and Schottky-barrier diodes (SBDs). Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of MISFETs, and junction-barrier Schottky diodes (JBSs) are a type of SBDs.

A JBS includes a first conductivity type semiconductor layer, a plurality of second conductivity type regions disposed in contact with the first conductivity type semiconductor layer, and a Schottky electrode forming a Schottky junction with the first conductivity type semiconductor layer. Because of having a plurality of second conductivity type regions, the JBS achieves a reduction in leakage current when reverse-biased as compared to an SBD (see, for example, Japanese Unexamined Patent Application Publication No. 2014-60276).

SUMMARY

In one general aspect, the techniques disclosed here feature a semiconductor device including a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface of the semiconductor substrate, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions as viewed in a direction normal to the principal surface, a first electrode disposed on the silicon carbide semiconductor layer and forming a Schottky junction with the silicon carbide semiconductor layer, and a second electrode disposed on the back surface of the semiconductor substrate and forming an ohmic junction with the semiconductor substrate; wherein the first electrode has a surface in contact with the silicon carbide semiconductor layer, the first electrode is in contact with the edge termination region along an edge portion of the surface of the first electrode in contact with the silicon carbide semiconductor layer, each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer as viewed in the direction normal to the principal surface, each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to <11-20> direction of crystal orientations of the semiconductor substrate, the barrier regions are arranged periodically as viewed in the direction normal to the principal surface, and at least two of the barrier regions are separated from each other in the <11-20> direction of the crystal orientations of the semiconductor substrate.

DETAILED DESCRIPTION

Aspects of the present disclosure reside in the following items,

A semiconductor device including a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface of the semiconductor substrate, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions as viewed in a direction normal to the principal surface, a first electrode disposed on the silicon carbide semiconductor layer and forming a Schottky junction with the silicon carbide semiconductor layer, and a second electrode disposed on the back surface of the semiconductor substrate and forming an ohmic junction with the semiconductor substrate; wherein the first electrode has a surface in contact with the silicon carbide semiconductor layer, the first electrode is in contact with the edge termination region along an edge portion of the surface of the first electrode in contact with the silicon carbide semiconductor layer, each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer as viewed in the direction normal to the principal surface, each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to <11-20> direction of crystal orientations of the semiconductor substrate, the barrier regions are arranged periodically as viewed in the direction normal to the principal surface, and at least two of the barrier regions are separated from each other in the <11-20> direction of the crystal orientations of the semiconductor substrate.

With this configuration, the semiconductor device achieves a higher breakdown voltage than when the boundaries between the barrier region and the silicon carbide semiconductor layer include sides parallel to <1-100> direction of the crystal orientations of the semiconductor substrate. Further, the portion of the silicon carbide semiconductor layer that is enclosed by the edge termination region has an increased area of the barrier-free sections as compared to when the barrier regions have no separation in <11-20> direction, and it is therefore possible to increase the forward current in the semiconductor device and to reduce the forward on-state voltage of the semiconductor device.

In the semiconductor device according to one aspect of the present disclosure, the polygonal boundary may have a rounded corner.

The semiconductor device described in Item 1, wherein the polygonal boundary has an inner angle of 60° or 120°.

With this configuration, all the sides of the boundaries between the barrier region and the silicon carbide semiconductor layer extend in a direction equivalent to <11-20> direction, and consequently the breakdown voltage of the semiconductor device can be enhanced as compared to when the boundaries include sides parallel to <1-100> direction of the crystal orientations of the semiconductor substrate.

The semiconductor device described in Item 1 or 2, wherein the polygonal boundary is parallelogrammatic or hexagonal.

With this configuration, the portion of the silicon carbide semiconductor layer that is enclosed by the edge termination region has an increased area of the barrier-free sections, and it is therefore possible to increase the forward current in the semiconductor device and to reduce the forward on-state voltage of the semiconductor device.

The semiconductor device described in any of Items 1 to 3, wherein the edge termination region and the barrier regions each include a pair of a high-concentration region disposed in contact with a surface of the silicon carbide semiconductor layer and a low-concentration region disposed between the semiconductor substrate and the high-concentration region; the high-concentration regions and the low-concentration regions each include a second conductivity type impurity; and an impurity concentration in the high-concentration regions is higher than an impurity concentration in the low-concentration regions.

With this configuration, a further enhancement in the breakdown voltage of the semiconductor device can be obtained.

The semiconductor device described in Item 4, wherein each pair of the high-concentration region and the low-concentration region have an identical outline as viewed in the direction normal to the principal surface.

With this configuration, the high-concentration region and the low-concentration region can be formed at the same time, and consequently the production process can be simplified.

The semiconductor device described in any of Items 1 to 5, wherein the edge termination region includes a guard ring subregion having the second conductivity type and disposed in contact with the first electrode, and a floating subregion having the second conductivity type and disposed out of contact with the guard ring subregion, the floating subregion enclosing the guard ring subregion as viewed in the direction normal to the principal surface.

With this configuration, the breakdown voltage of the semiconductor device can be controlled to a high breakdown voltage of, for example, 900 V or above by changing the number of the floating subregions.

The semiconductor device described in Item 4 or 5, wherein the impurity concentration in a direction of depth of the low-concentration regions has a profile including an upward curve.

With this configuration, crystal defects occurring in the pn junctions between the silicon carbide semiconductor layer, and the edge termination region and barrier regions have a relatively small size, and consequently the leakage current from the pn junctions can be reduced.

The semiconductor device described in Item 7, wherein the impurity concentration in the high-concentration regions is not less than 1×1019cm−3and the impurity concentration in the low-concentration regions is less than 1×1019cm−3.

With this configuration, the electric field concentration in the edge termination region is further reduced, and the semiconductor device achieves a higher breakdown voltage.

The semiconductor device described in Item 7, wherein the impurity concentration in the high-concentration regions is not less than 1×1020cm−3and the impurity concentration in the low-concentration regions is less than 1×1020cm−3.

With this configuration, the electric field concentration in the edge termination region is still further reduced, and the semiconductor device achieves a still higher breakdown voltage,

The semiconductor device described in any of Items 1 to 9, wherein the first electrode includes a metal selected from the group consisting of Ti, Ni and Mo.

With this configuration, the first electrode can easily form a Schottky junction with the silicon carbide semiconductor layer.

A semiconductor device including a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface of the semiconductor substrate, a barrier region having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier region as viewed in a direction normal to the principal surface, a first electrode disposed on the silicon carbide semiconductor layer and forming a Schottky junction with the silicon carbide semiconductor layer, and a second electrode disposed on the back surface of the semiconductor substrate and forming an ohmic junction with the semiconductor substrate, wherein the first electrode has a surface in contact with the silicon carbide semiconductor layer, the first electrode is in contact with the edge termination region along an edge portion of the surface of the first electrode in contact with the silicon carbide semiconductor layer, the barrier region has a polygonal boundary with the silicon carbide semiconductor layer as viewed in the direction normal to the principal surface, each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to <11-20> direction of crystal orientations of the semiconductor substrate, the barrier region encloses a portion of a surface of the silicon carbide semiconductor layer as viewed in the direction normal to the principal surface.

With this configuration, the semiconductor device achieves a higher breakdown voltage than when the boundaries between the barrier region and the silicon carbide semiconductor layer include sides parallel to <1-100> direction of the crystal orientations of the semiconductor substrate.

In the semiconductor device according to one aspect of the present disclosure, the polygonal boundary may have a rounded corner.

The semiconductor device described in Item11, wherein the polygonal boundary has an inner angle of 60° or 120°.

With this configuration, all the sides of the boundaries between the barrier region and the silicon carbide semiconductor layer extend in a direction equivalent to <11-20> direction, and consequently the breakdown voltage of the semiconductor device can be enhanced as compared to when the boundaries include sides parallel to <1-100> direction of the crystal orientations of the semiconductor substrate.

The semiconductor device described in Item 11 or 12, wherein the polygonal boundary is parallelogrammatic or hexagonal.

With this configuration, the portion of the silicon carbide semiconductor layer that is enclosed by the edge termination region has an increased area of the barrier-free sections, and it is therefore possible to increase the forward current in the semiconductor device and to reduce the forward on-state voltage of the semiconductor device.

The semiconductor device described in any of Items 11 to 13, wherein the edge termination region and the barrier region each include a pair of a high-concentration region disposed in contact with the surface of the silicon carbide semiconductor layer and a low-concentration region disposed between the semiconductor substrate and the high-concentration region, the high-concentration regions and the low-concentration regions each include a second conductivity type impurity, and an impurity concentration in the high-concentration regions is higher than an impurity concentration in the low-concentration regions.

With this configuration, a further enhancement in the breakdown voltage of the semiconductor device can be obtained.

The semiconductor device described in Item 14, wherein each pair of the high-concentration region and the low-concentration region have an identical outline as viewed in the direction normal to the principal surface.

With this configuration, the high-concentration region and the low-concentration region can be formed at the same time, and consequently the production process can be simplified.

The semiconductor device described in any of Items 11 to 15, wherein the edge termination region includes a guard ring subregion having the second conductivity type and disposed in contact with the first electrode, and a floating subregion having the second conductivity type and disposed out of contact with the guard ring subregion, the floating subregion enclosing the guard ring subregion as viewed in the direction normal to the principal surface.

With this configuration, the breakdown voltage of the semiconductor device can be controlled to a high breakdown voltage of, for example, 900 V or above by changing the number of the floating subregions.

The semiconductor device described in Item 14 or 15, wherein the impurity concentration in a direction of depth of the low-concentration regions has a profile including an upward curve.

With this configuration, crystal defects occurring in the pn junctions between the silicon carbide semiconductor layer, and the edge termination region and barrier region have a relatively small size, and consequently the leakage current from the pn junctions can be reduced.

The semiconductor device described in Item 17, wherein the impurity concentration in the high-concentration regions is not less than 1×1019cm−3and the impurity concentration in the low-concentration regions is less than 1×1019cm−3.

With this configuration, the electric field concentration in the edge termination region is further reduced, and the semiconductor device achieves a higher breakdown voltage.

The semiconductor device described in Item 17, wherein the impurity concentration in the high-concentration regions is not less than 1×1020cm−3and the impurity concentration in the low-concentration regions is less than 1×1020cm−3.

With this configuration, the electric field concentration in the edge termination region is still further reduced, and the semiconductor device achieves a still higher breakdown voltage.

The semiconductor device described in any of Items 11 to 19, wherein the first electrode includes a metal selected from the group consisting of Ti, Ni and Mo.

With this configuration, the first electrode can easily form a Schottky junction with the silicon carbide semiconductor layer.

A semiconductor device manufacturing method including providing a first conductivity type semiconductor substrate having a principal surface and a back surface; forming a first conductivity type silicon carbide semiconductor layer onto the principal surface of the semiconductor substrate; forming a second conductivity type edge termination region within the silicon carbide semiconductor layer; forming a plurality of second conductivity type barrier regions within the silicon carbide semiconductor layer; forming a second electrode onto the back surface of the semiconductor substrate in ohmic contact with the semiconductor substrate; and forming a first electrode onto the silicon carbide semiconductor layer in Schottky contact with the silicon carbide semiconductor layer; the edge termination region being formed so as to enclose the plurality of barrier regions as viewed in a direction normal to the principal surface; each of the plurality of barrier regions having a polygonal boundary with the silicon carbide semiconductor layer as viewed in the direction normal to the principal surface; each of the sides of the polygonal boundary having an angle of 0° to 5° inclusive relative to <11-20> direction of crystal orientations of the semiconductor substrate; the plurality of barrier regions being arranged periodically as viewed in the direction normal to the principal surface; at least two of the plurality of barrier regions being separated from each other in <11-20> direction of the crystal orientations of the semiconductor substrate.

By this method, a semiconductor device can be manufactured which achieves a higher breakdown voltage than when the boundaries between the barrier region and the silicon carbide semiconductor layer include sides parallel to <1-100> direction of the crystal orientations of the semiconductor substrate. Further, because the portion of the silicon carbide semiconductor layer that is enclosed by the edge termination region has an increased area of the barrier-free sections as compared to when the barrier regions have no separation in <11-20> direction, it is possible to produce a semiconductor device having an increased forward current and a reduced forward on-state voltage.

A semiconductor device manufacturing method including providing a first conductivity type semiconductor substrate having a principal surface and a back surface; forming a first conductivity type silicon carbide semiconductor layer onto the principal surface of the semiconductor substrate; forming a second conductivity type edge termination region within the silicon carbide semiconductor layer; forming a second conductivity type barrier region within the silicon carbide semiconductor layer; forming a second electrode onto the back surface of the semiconductor substrate in ohmic contact with the semiconductor substrate; and forming a first electrode onto the silicon carbide semiconductor layer in Schottky contact with the silicon carbide semiconductor layer; the edge termination region being formed so as to enclose the barrier region as viewed in a direction normal to the principal surface; the barrier region having a polygonal boundary with the silicon carbide semiconductor layer as viewed in the direction normal to the principal surface; each of the sides of the polygonal boundary having an angle of 0° to 5° inclusive relative to <11-20> direction of crystal orientations of the semiconductor substrate; the barrier region being formed so as to enclose a portion of the surface of the silicon carbide semiconductor layer as viewed in the direction normal to the principal surface.

By this method, a semiconductor device can be manufactured which achieves a higher breakdown voltage than when the boundaries between the barrier region and the silicon carbide semiconductor layer include sides parallel to <1-100> direction of the crystal orientations of the semiconductor substrate. Further, because the portion of the silicon carbide semiconductor layer that is enclosed by the edge termination region has an increased area of the section occupied by the barrier region as compared to when the configuration is inverted, it is possible to produce a semiconductor device having a reduced amount of leakage current in the reverse direction,

The semiconductor device manufacturing method described in Item 21 or 22, wherein the edge termination region and the plurality of barrier regions or the barrier region are formed at the same time,

This configuration allows the semiconductor device manufacturing process to be simplified.

Hereinbelow, the first embodiment of the present disclosure will be described with reference to the drawings. While the first embodiment illustrates the first conductivity type as being n-type and the second conductivity type as p-type, the conductivity types in the first embodiment are not limited thereto and the first conductivity type may be p-type and the second conductivity type may be n-type.

A semiconductor device201according to the first embodiment of the present disclosure will be described with reference toFIGS. 1 to 11.FIG. 1is a sectional view schematically illustrating the semiconductor device201according to the present embodiment. The semiconductor device201includes a semiconductor substrate101a silicon carbide semiconductor layer102, a plurality of barrier regions151, an edge termination region152, a first electrode159and a second electrode110.

The semiconductor substrate101is a first conductivity type silicon carbide semiconductor substrate. The semiconductor substrate101has a principal surface121and a back surface123.

The silicon carbide semiconductor layer102has the first conductivity type and is disposed on the principal surface121of the semiconductor substrate101. The semiconductor device201may include a buffer layer132between the semiconductor substrate101and the silicon carbide semiconductor layer102. The silicon carbide semiconductor layer102has a surface122opposite to the semiconductor substrate101.FIG. 2is a plan view of the surface122of the silicon carbide semiconductor layer102as viewed in the direction normal to the principal surface121of the semiconductor substrate101. The sectional view inFIG. 1shows a cross section taken along line I-I inFIG. 2.

The plurality of barrier regions151are disposed within the silicon carbide semiconductor layer102. As illustrated inFIGS. 1 and 2, the plurality of barrier regions151are exposed on portions of the surface122of the silicon carbide semiconductor layer102, and extend from the surface122toward the inside of the silicon carbide semiconductor layer102. In the present embodiment, the barrier regions151have a stripe shape on the surface122. The barrier regions151will be described in detail later.

The edge termination region152is disposed within the silicon carbide semiconductor layer102. As illustrated inFIGS. 1 and 2, the edge termination region152encloses the plurality of barrier regions151as viewed in the direction normal to the principal surface121of the semiconductor substrate101,

The edge termination region152includes a guard ring subregion154enclosing the barrier regions151on the surface122, and an FLR (field limiting ring) subregion156that is a floating subregion enclosing the guard ring subregion154. In the present embodiment, the semiconductor device201includes four FLR subregions156. The four FLR subregions156enclose the barrier regions151at different distances from the center of the surface122.

The barrier regions151, the guard ring subregion154and the FLR subregions156each contain a second conductivity type impurity. Specifically, the barrier regions151, the guard ring subregion154and the FLR subregions156each include a high-concentration region153disposed in contact with the surface122of the silicon carbide semiconductor layer102and containing a second conductivity type impurity, and a low-concentration region155disposed nearer to the semiconductor substrate101than is the high-concentration region153and containing the second conductivity type impurity in a concentration lower than the impurity concentration in the high-concentration region153. As illustrated inFIGS. 1 and 2, each pair of the high-concentration region153and the low-concentration region155have an identical outline as viewed in the direction normal to the principal surface121of the semiconductor substrate101. The guard ring subregion154and the FLR subregions156are separated from each other and are out of contact with each other.

The first electrode159is disposed on the surface122of the silicon carbide semiconductor layer102, and forms a Schottky junction with the silicon carbide semiconductor layer102. Further, the first electrode159has an edge162that defines the outer periphery of the electrode surface in contact with the surface122. The edge162of the first electrode159is in contact with the guard ring subregion154of the edge termination region152on the surface122.

An insulating layer111is disposed on the portion of the surface122of the silicon carbide semiconductor layer102that is out of contact with the first electrode159. That is, the insulating layer111covers the FLR subregions156and a portion of the guard ring subregion154on the surface122.

An upper electrode112is disposed on the first electrode159. The side surface of the upper electrode112is disposed on the insulating layer111. The upper electrode112covers the upper surface and the side surface of the first electrode159.

A passivation layer114is disposed on a portion of the insulating layer111and a portion of the upper electrode112. The passivation layer114covers the side surface and a portion of the upper surface of the upper electrode112.

The second electrode110is disposed on the back surface123of the semiconductor substrate101, and forms an ohmic junction with the semiconductor substrate. Further, a backside electrode113is disposed on the surface of the second electrode110opposite to the semiconductor substrate101.

Next, the barrier regions151and the edge termination region152will be described in detail with reference toFIG. 2. As mentioned above, the barrier regions151have a stripe shape on the surface122of the silicon carbide semiconductor layer102. More specifically, the plurality of barrier regions151include a plurality of first barrier regions351and a plurality of second barrier regions352. Each of the first barrier regions351is a continuous stripe. Each of the second barrier regions352consists of at least two segments of one stripe divided in the direction in which the stripe extends. That is, the at least two segments of each of the plurality of second barrier regions352are separated in the direction in which the stripe extends. In the example illustrated inFIG. 2, the second barrier region352is divided by a region353.

In the example illustrated inFIG. 2, the plurality of first barrier regions351and the plurality of second barrier regions352are arranged alternately and periodically in the direction perpendicular to the direction in which the stripes extend. For example, the width301of the barrier region151is 2 μm, and the spacing302is 4 μm.

For example, the principal surface121of the semiconductor substrate101is (0001) Si face of 4H-SiC. In the case of a commercial semiconductor substrate101, the principal surface121may be offcut toward <11-20> direction or <1-100> direction. As indicated in the drawing,FIG. 2assumes that the direction extending to the right of the paper sheet is <11-20> direction, and the direction extending to the top of the paper sheet is <1-100> direction. The hyphen “-” in these directions indicates a “bar” on the figure that follows the hyphen in the Miller index. Each of these directions includes equivalent directions. For example, <11-20> direction includes [11-20], [−12-10], [−2110], [−1-120], [1-210]and [2-1-10].

Boundaries133on the surface122between the barrier region151and the silicon carbide semiconductor layer102are parallel to <11-20> direction. Here, the term “parallel” means that the angle formed between any side of the boundary133and <11-20> direction is within ±5°. The edge termination region152has a square shape, and the sides thereof are parallel to <11-20> direction or to <1-100> direction.

FIG. 29is an enlarged plan view illustrating part of the barrier regions151on the surface122of the silicon carbide semiconductor layer102. As mentioned above, the first barrier region351is a continuous stripe. The boundary133between the first barrier region351and the silicon carbide semiconductor layer102is parallel to <11-20> direction. The second barrier region352includes two segments of one stripe divided by the region353. The two segments of the second barrier region352are separated from each other in <11-20> direction. As illustrated inFIG. 29, the boundary133on the surface122between the first barrier region351and the silicon carbide semiconductor layer102is composed solely of lines parallel to the direction in which the stripe extends. On the other hand, the boundary133on the surface122between the second barrier region352and the silicon carbide semiconductor layer102forms an angle of 60° in the region353relative to the direction in which the stripe extends. As will be described in detail in modified examples later, the silicon carbide semiconductor belongs to the hexagonal system and therefore the directions having an angle of 60° or 120° relative to the direction in which the stripe extends are equivalent to the direction of the extension of the stripe. Thus, the boundary133on the surface122between the second barrier region352and the silicon carbide semiconductor layer102is also composed solely of lines parallel to <11-20> direction.

Reverse-biasing a metal-semiconductor Schottky junction or a semiconductor pn junction causes the depletion layer at the Schottky junction or the pn junction to extend. When the reverse-basing voltage is increased and the field intensity at the junction interface reaches a threshold, an avalanche current flows in the depletion layer and it becomes impossible to further increase the reverse bias. In the present disclosure, the voltage which causes the avalanche current to flow is simply referred to as the breakdown voltage.

The description hereinbelow assumes that the first conductivity type is n-type and the second conductivity type is p-type. The semiconductor device201in the first embodiment of the present disclosure has a JBS structure. When a negative voltage is applied to the first electrode159relative to the second electrode110, a depletion layer formed between the first electrode159and the n-type silicon carbide semiconductor layer102extends toward the n-type semiconductor substrate101. Further, a pn junction is formed between the p-type barrier region151and the n-type silicon carbide semiconductor layer102, and the biasing causes the depletion layer at the pn junction to extend mainly toward the silicon carbide semiconductor layer102. The depletion layers extending from the pn junctions of the adjacent barrier regions151interrupt the leakage current from the Schottky junctions present between the adjacent barrier regions151, and consequently the leakage current in the semiconductor device201is reduced. The breakdown voltage is exceeded when the field intensity at a junction interface of a Schottky junction or a pn junction reaches a threshold. The edge termination region152is provided in order to reduce the field intensity on the surface122of the silicon carbide semiconductor layer102.

For the purposes of simplifying the process and thereby saving the production costs, the semiconductor device201in the first embodiment of the present disclosure has a structure that allows the edge termination region152and the barrier regions151to be formed at the same time. The edge termination region152and the barrier regions151are formed by implanting ions, for example, Al ions into the silicon carbide semiconductor layer102. The edge termination region152and the barrier regions151are formed at the same time so as to include the high-concentration regions153and the low-concentration regions155by implanting Al ions a plurality of times using different magnitudes of implantation energy.FIG. 3illustrates an exemplary profile of the impurity concentration in the direction of depth. The high-concentration regions153and the low-concentration regions155in the edge termination region152and the barrier regions151are collectively written as implanted regions157. In the example illustrated inFIG. 3, the implanted regions157are formed using four levels of implantation energy. As illustrated inFIG. 3, the high-concentration regions153may be defined as regions that extend from the surface122of the silicon carbide semiconductor layer102to the border of the low-concentration regions155, namely, regions that contain a second conductivity type impurity in a concentration not less than the prescribed concentration, and the low-concentration regions155may be defined as regions that contain the second conductivity type impurity in a concentration less than the prescribed concentration. The concentration profile of the low-concentration regions155may include an upward curve when the concentration is represented on the ordinate on the log scale and the depth is represented on the abscissa on the linear scale. The upward curve in the concentration profile includes not only a peak and a sub peak, but also a shoulder. The shoulder is a segment in which the slope of the profile, specifically, the rate of the decrease in concentration becomes slow as the depth is increased. For example, the prescribed concentration is 1×1019cm−3or 1×1020cm−3.

When, for example, the prescribed concentration is 1×1019cm−3, the high-concentration regions153in the profile illustrated inFIG. 3are regions extending from the surface to a depth of about 0.3 μm, and the low-concentration regions155are regions at greater depths than the high-concentration regions153.

In order to demonstrate the effects obtained by configuring each of the barrier regions to have a boundary with the silicon carbide semiconductor layer that is parallel to <11-20> direction on the surface of the silicon carbide semiconductor layer, semiconductor devices205illustrated inFIGS. 27 and 28were fabricated.FIGS. 27 and 28are a sectional view of the semiconductor device205and a plan view of a surface122of a silicon carbide semiconductor layer102, respectively. The semiconductor device205differs from the semiconductor device201in that a plurality of barrier regions251do not include any second barrier regions352segmented in <11-20> direction. Except for this difference, the configuration of the semiconductor device205is the same as that of the semiconductor device201and thus will not be described anew.

As comparative examples, semiconductor devices202and semiconductor devices203were provided.FIGS. 4 and 5are a sectional view of the semiconductor device202and a plan view of a surface122of a silicon carbide semiconductor layer102, respectively. In the semiconductor device202, high-concentration regions153and low-concentration regions155in barrier regions161have the same impurity concentration profile as in the semiconductor device201.

As illustrated inFIG. 5, the plurality of barrier regions161of the semiconductor device202extend in the longitudinal direction of the paper sheet on the surface122, and a boundary134between the barrier region161and the silicon carbide semiconductor layer102is perpendicular to <11-20> direction. For example, the width301of the barrier region161is 2 μm and the spacing302between the adjacent barrier regions161is 4 μm.

FIGS. 6 and 7are a sectional view of the semiconductor device203and a plan view of a surface122of a silicon carbide semiconductor layer102, respectively. In the semiconductor device203, high-concentration regions153and low-concentration regions155in barrier regions171have the same impurity concentration profile as in the semiconductor device201.

As illustrated inFIG. 7, the barrier regions171of the semiconductor device203each have a square shape on the surface122, and are arranged two dimensionally (in the longitudinal direction and the traverse direction) while being separated from one another. For example, the barrier regions171each have a regular square shape on the surface122, and the length301of each side of the regular square is 2 μm. For example, the spacings302between the barrier regions171adjacent to each other in the longitudinal direction and the traverse direction are each 3 μm. A side135and a side136of the boundary between the barrier region171and the silicon carbide semiconductor layer102are parallel to <11-20> direction and <1-100> direction, respectively, on the surface122. That is, the side136of the boundary is perpendicular to <11-20> direction.

The semiconductor devices205,202and203differing in the configuration of the barrier regions were fabricated on a 4H—SiC wafer as the semiconductor substrate101, and were tested to determine the breakdown voltage. The results are described inFIG. 8. In order to reduce the influence caused by differences in the process conditions, the semiconductor devices205,202and203were formed on the single wafer close to one another. The breakdown voltage is measured by applying a negative voltage to an upper electrode112relative to a backside electrode113. In the graph shown inFIG. 8, the abscissa indicates the distance from the center of the silicon carbide substrate, and the negative marks are distances on the orientation flat side of the silicon carbide substrate and the positive marks are distances on the side opposite to the orientation flat side. The reason why the breakdown voltage has a distribution depending on the distance from the center of the wafer is because the silicon carbide semiconductor layer102formed on the semiconductor substrate101has an in-plane concentration distribution. For example, the concentration of n-type (first conductivity type) impurity is higher on the wafer periphery than in the inner side of the wafer.

As shown inFIG. 8, the semiconductor devices205exhibited the highest breakdown voltage and the semiconductor devices203had the lowest breakdown voltage in all the range of distances from the center of the semiconductor substrate. FromFIG. 8, the median values of breakdown voltage of the semiconductor devices205,202and203are calculated to be 2015 V, 1975 V and 1960 V, respectively. As mentioned above, these semiconductor devices were formed on the single 3-inch wafer close to one another. It is therefore reasonable to assume that the semiconductor devices205,202and203located at the same distance from the wafer center are very similar to one another in terms of the concentration and thickness of the silicon carbide semiconductor layer102and also in terms of the concentration profile in the implanted regions157. That is, it can be said that the difference in breakdown voltage among the semiconductor devices205,202and203is ascribed to the manners of arrangement and the shapes of the barrier regions251,161and171.

In particular, the comparison of the semiconductor device205to the semiconductor device202will be discussed. These two semiconductor devices have the same width of the barrier regions and the same spacing between the barrier regions, and are different from each other only in that the barrier regions251and the barrier regions161both in the form of stripes extend in different directions. Thus, the above results have shown that a higher breakdown voltage can be obtained when the barrier regions in the form of stripes are such that, as is the case in the barrier regions251, the boundaries133between the barrier region251and the silicon carbide semiconductor layer102are parallel to <11-20> direction on the surface122of the silicon carbide semiconductor layer102than when, as is the case in the barrier regions161, the boundaries134between the barrier region161and the silicon carbide semiconductor layer102are parallel to <1-100> direction on the surface122of the silicon carbide semiconductor layer102.

Further, it has been shown that the semiconductor device203has a lower breakdown voltage than the semiconductor device205and compares substantially equally or slightly unfavorably to the semiconductor device202in terms of breakdown voltage. As illustrated inFIG. 7, the barrier regions171in the semiconductor device203have a square shape on the surface122. In the case of square barrier regions, the boundaries between the barrier region and the silicon carbide semiconductor layer are made up of lines that extend in two perpendicular directions on the surface of the silicon carbide semiconductor layer. In the barrier regions171, the side135of the boundary between the barrier region171and the silicon carbide semiconductor layer102is parallel to <11-20> direction on the surface122of the silicon carbide semiconductor layer102, and the side136of the boundary is parallel to <1-100> direction. Thus, similarly to the case of the semiconductor device202, the barrier regions171in the semiconductor device203have boundaries whose sides are parallel to <1-100> direction.

From the foregoing discussion, it has been shown that the breakdown voltage of the semiconductor devices is decreased when the boundaries between the barrier region and the silicon carbide semiconductor layer include sides parallel to <1-100> direction. That is, it has been shown that the breakdown voltage of the semiconductor devices can be increased when all the sides of the boundaries between the barrier region and the silicon carbide semiconductor layer are parallel to <11-20> direction, as compared to when the semiconductor devices include such boundaries having sides parallel to <1-100> direction.

Next, the discussion focuses on the edge termination region. As illustrated inFIGS. 28, 5 and 7, the edge termination region152includes square rings. Thus, the boundaries between the edge termination region152and the silicon carbide semiconductor layer102include sides parallel to <11-20> direction and sides parallel to <1-100> direction on the surface122of the silicon carbide semiconductor layer102. Because the configuration of the edge termination region152is common in the semiconductor devices205,202and203, it is reasonable to assume that the directions of the boundaries of the edge termination region152do not affect the breakdown voltage of the semiconductor devices.

To confirm this assumption, a semiconductor device204was fabricated which was the same as the semiconductor device205except that the semiconductor device204had no barrier regions251.FIGS. 9 and 10are a sectional view of the semiconductor device204and a plan view of a surface122of a silicon carbide semiconductor layer102, respectively. As illustrated inFIG. 11, measurement has shown that the semiconductor device204has substantially the same level of breakdown voltage as the semiconductor device205.

Based on the results described above, it has been shown that the breakdown voltage of the semiconductor devices discussed in the present embodiment is reduced if the boundaries between the barrier region and the silicon carbide semiconductor layer102include sides parallel to <1-100> direction on the surface122of the silicon carbide semiconductor layer102, and is enhanced when all the sides of the boundaries are parallel to <11-20> direction.

As discussed above, the semiconductor devices having different types of barrier regions exhibit different levels of breakdown voltage even when the concentrations and thicknesses of the silicon carbide semiconductor layers102are similar. Thus, controlling the configuration of the barrier regions makes it possible to realize semiconductor devices having a high breakdown voltage, and also makes it possible to reduce the forward on-state voltage of the semiconductor devices while ensuring a sufficient level of breakdown voltage. In the manufacturing of, for example, semiconductor devices that can withstand a reverse voltage of 1700 V, it is often the case that the semiconductor devices are designed so that the breakdown voltage will be, for example, about 2000 V in consideration of the in-plane distributions of concentration and thickness in the silicon carbide semiconductor layer102, and the variation in such properties among the silicon carbide semiconductor layers. Assume that, for example, a breakdown voltage of 2000 V is realized by employing the configuration of the semiconductor device203having the barrier regions171illustrated inFIGS. 6 and 7. Here, the concentration and the thickness of the silicon carbide semiconductor layer102are written as n and d, respectively. When the semiconductor device201having the barrier regions151is fabricated with the same concentration and thickness of the silicon carbide semiconductor layer102as in the semiconductor device203, the breakdown voltage is expected to be increased to, for example, about 2050 V. in this case, the breakdown voltage is controlled to approximately 2000 V by reselecting the concentration and/or the thickness of the silicon carbide semiconductor layer102. Because there is a margin of about 50 V by which a decrease in breakdown voltage is acceptable, it is possible to, for example, increase the concentration in the silicon carbide semiconductor layer or to reduce the thickness of the silicon carbide semiconductor layer. The increase in concentration and the reduction in thickness of the silicon carbide semiconductor layer both result in a decrease in drift resistance. That is, the semiconductor device201, which in this case has the same breakdown voltage as the semiconductor device203, exhibits a lower resistance in the forward direction by virtue of the increase in concentration or the reduction in thickness of the silicon carbide semiconductor layer. Thus, the on-state voltage of the semiconductor device can be reduced.

Further, because the semiconductor device201of the present embodiment is such that some of the barrier regions151include segments separated in <11-20> direction, the barrier regions151represent a reduced proportion of the area enclosed by the guard ring subregion154as compared to the semiconductor device205illustrated inFIGS. 27 and 28. This configuration of the semiconductor device201allows a current to flow in an increased amount at a certain voltage applied in the forward direction, namely, when a certain positive voltage is applied to the upper electrode112relative to the backside electrode113, thus resulting in a decrease in the on-state voltage of the semiconductor device201.

(Methods for Manufacturing Semiconductor Devices)

Next, a method for manufacturing the semiconductor device201according to the present embodiment will be described with reference toFIGS. 12 to 20.FIGS. 12 to 20are sectional views illustrating steps in the method for manufacturing the semiconductor device201according to the present embodiment.

First, a semiconductor substrate101is provided. For example, the semiconductor substrate101is a low-resistance n-type 4H—SiC (0001) offcut substrate having a resistivity of about 0.02 Ωcm. For example, the offcut direction is <11-20> direction. The orientation flat in the semiconductor substrate101is parallel to <11-20> direction, and photomasks used in the formation of the semiconductor device201are aligned with reference to the orientation flat.

As illustrated inFIG. 12, a high-resistance n-type silicon carbide semiconductor layer102is epitaxially grown on the semiconductor substrate101. Prior to the formation of the silicon carbide semiconductor layer102, an n-type SiC buffer layer132having a high impurity concentration may be deposited on the semiconductor substrate101. The impurity concentration in the buffer layer132is, for example, 1×1018cm−3, and the thickness of the buffer layer132is, for example, 1 μm. For example, the silicon carbide semiconductor layer102is formed of n-type 4H—SiC, and has an impurity concentration of 1×1016cm−3and a thickness of 10 μm.

Next, as illustrated inFIG. 13, a mask190made of, for example, SiO2that has a pattern for defining barrier regions151and an edge termination region152is formed on the silicon carbide semiconductor layer102. Thereafter, ions, for example, Al ions are implanted into the silicon carbide semiconductor layer102through the mask190to form ion implanted regions191,192,194and196. For example, the magnitudes of ion implantation energy, and the doses are controlled so that the Al ions implanted will have a concentration profile similar to that illustrated inFIG. 3, that is, the ion implanted regions191,192,194and196will include high-concentration implanted regions193on the surface side and low-concentration implanted regions195at greater depths than the high-concentration implanted regions193.

The high-concentration implanted regions193and the low-concentration implanted regions195formed in this step will define high-concentration regions153and low-concentration regions155in the final semiconductor device201, Further, the ion implanted regions191,192,194and196will define barrier regions151, an edge termination region152, a guard ring subregion154and FLR subregions156, respectively, later in the process. By implanting the ions into the regions at the same time, the profile of the impurity concentration in the direction perpendicular to the principal surface of the semiconductor substrate101is rendered identical between the edge termination region152and the barrier regions151. Further, because the high-concentration regions153and the low-concentration regions155are formed at the same time using the single mask190, the outlines of the paired high-concentration regions153and low-concentration regions155in the edge termination region152and in the barrier regions151each become identical as viewed in the direction perpendicular to the principal surface of the semiconductor substrate101.

In the above step, the mask190is aligned so that on the surface122of the silicon carbide semiconductor layer102, the ion implanted regions191will have boundaries with the silicon carbide semiconductor layer102which are parallel to <11-20> direction that represents crystal orientations in the semiconductor substrate101.

Although not illustrated, an n-type impurity may be implanted into the back surface of the semiconductor substrate101as required to further increase the n-type concentration on the backside.

Next, as illustrated inFIG. 14, the mask190is removed and the structure on the semiconductor substrate101is heat treated at a temperature of about 1500° C. to 1900° C. to form barrier regions151and an edge termination region152including a guard ring subregion154and FLR subregions156which each have a high-concentration region153and a low-concentration region155. In an embodiment, a carbon film may be deposited on the surface of the silicon carbide semiconductor layer102before the heat treatment and may be removed after the heat treatment. In this case, a thermal oxide film may be formed on the surface122of the silicon carbide semiconductor layer102after the removal and the thermal oxide film may be removed by etching to clean the surface122of the silicon carbide semiconductor layer102. Referring toFIG. 2, the width301of the barrier region151is, for example, 2 μm, and the spacing302is, for example, 4 μm. The width of the guard ring subregion154is, for example, about 15 μm. The spacing between the barrier region151and the guard ring subregion154inFIG. 2is, for example, 3 μm. The spacing between the guard ring subregion154and the innermost FLR subregion156is, for example, 1 μm.

Next, as illustrated inFIG. 15, a second electrode110is formed on the back surface123of the semiconductor substrate101by depositing, for example, Ni in a thickness of about 200 nm and heat treating the Ni layer at about 1000° C. The second electrode110forms an ohmic junction with the back surface123of the semiconductor substrate101.

Next, an insulating layer made of, for example, SiO2is formed on the surface122of the silicon carbide semiconductor layer102. For example, the thickness of the insulating layer is 300 nm. Next, a photoresist mask is formed and the insulating layer is treated by, for example, wet etching so as to expose a portion of the guard ring subregion154, and the portion of the silicon carbide semiconductor layer102enclosed by the guard ring subregion154. Thereafter, the mask is removed. In this manner, as illustrated inFIG. 16, an insulating layer111having an opening is formed.

Next, an electrode layer is deposited so as to cover the entire surface of the insulating layer111and the silicon carbide semiconductor layer102exposed in the opening. The electrode layer includes, for example, a metal such as Ti, Ni or Mo. For example, the thickness of the electrode layer is 200 nm. After the deposition, a photoresist mask is formed, and the electrode layer is patterned so that the resultant pattern covers at least the silicon carbide semiconductor layer102exposed from the insulating layer111. A patterned electrode layer is thus formed as illustrated inFIG. 17. The periphery of the electrode layer is disposed on the insulating layer111. The electrode layer is in contact with the portion of the surface122of the silicon carbide semiconductor layer102and the portion of the guard ring subregion154that are exposed from the insulating layer111. The edge of the surface of the electrode layer in contact with the silicon carbide semiconductor layer102is disposed on the guard ring subregion154.

Subsequently, the structure on the semiconductor substrate101is heat treated at a temperature of 100° C. to 700° C. to form a first electrode159. The first electrode159forms a Schottky junction with the silicon carbide semiconductor layer102.

Next, an electrode layer is deposited on the first electrode159and the insulating layer111. For example, the electrode layer is a metal film including Al and having a thickness of about 4 μm. A mask is formed on the electrode layer, and a portion of the insulating layer111is exposed by etching the undesired portion of the electrode layer. When the electrode layer is treated by wet etching, the etching conditions may be controlled so that the first electrode159will not be exposed. After the undesired portion of the electrode layer is removed by etching, the mask is removed. Consequently, an upper electrode112illustrated inFIG. 18is formed.

Next, a passivation layer illustrated inFIG. 19is formed as required. First, a passivation layer made of, for example, SiN is formed on the exposed insulating layer111and the upper electrode112. Thereafter, a mask is provided which has an opening that exposes a portion of the passivation layer located above the upper electrode112, and the portion of the passivation layer is removed by, for example, dry etching to expose the corresponding portion of the upper electrode112. Thereafter, the mask is removed. In this manner, as illustrated inFIG. 19, a passivation layer114is formed which is partially perforated on the upper electrode112. Any materials other than SiN may be used for the formation of the passivation layer114as long as the materials are insulators. For example, the material of the passivation layer114may be SiO2or an organic material such as polyimide.

Next, as illustrated inFIG. 20, a backside electrode113is formed as required. The backside electrode may be formed before the formation of the passivation layer114, or before the formation of the upper electrode112. For example, the backside electrode113may be formed by depositing Ti, Ni and Ag in this order onto the second electrode110. The thicknesses of these metal layers are, for example, 0.1 μm, 0.3 μm and 0.7 μm, respectively.

A semiconductor device201is manufactured through the steps described above.

Hereinbelow, modified examples of the present embodiment will be described. In the semiconductor device201illustrated inFIGS. 1 and 2, the barrier regions151are stripes parallel to <11-20> direction on the surface122of the silicon carbide semiconductor layer102. The barrier regions may have other shapes as long as all the sides of the boundaries are parallel to <11-20> direction on the surface122of the silicon carbide semiconductor layer102.

For example, as illustrated inFIG. 21, barrier regions181may have parallelogrammatic boundaries182on the surface122of the silicon carbide semiconductor layer102. As illustrated inFIG. 21, the parallelogrammatic boundary182is composed of a pair of sides parallel to <11-20> direction and a pair of sides having an angle of 60° relative to <11-20> direction. That is, the inner angles of the parallelogram are 120° or 60°. In the portion of the surface122enclosed by the guard ring subregion154, the barrier regions181are arranged periodically in <11-20> direction and in <1-100> direction perpendicular to <11-20> direction. The barrier regions181are separated from one another in <11-20> direction on the surface122.

For example, the width303in <11-20> direction and the width304in <1-100> direction of the barrier region181are 10 μm and 2 μm, respectively. For example, the spacing305in <11-20> direction and the spacing306in <1-100> direction between the barrier regions181are 3 μm and 4 μm, respectively.

The silicon carbide semiconductor belongs to the hexagonal system. In a plane including [11-20] direction and [1-100] direction, those directions having an angle of 60° or 120° relative to [11-20] are crystal orientations equivalent to [11-20] and are all <11-20> directions. Therefore, all the four sides of the parallelogram illustrated inFIG. 21are parallel to <11-20> direction. That is, the barrier regions181exclusively have boundaries whose all sides are parallel to <11-20> direction on the surface122of the silicon carbide semiconductor layer102.

In the structure described above, the barrier regions181are separated from one another in <11-20> direction, and therefore the barrier regions181represent a reduced proportion of the area enclosed by the guard ring subregion154as compared to the semiconductor device201illustrated inFIGS. 1 and 2. Thus, this modified configuration of the semiconductor device allows a current to flow in an increased amount at a certain voltage applied in the forward direction, namely, when a certain positive voltage is applied to the upper electrode112relative to the backside electrode113, thus resulting in a decrease in on-state voltage. Further, because the barrier regions181exclusively have boundaries whose all sides are parallel to <11-20> direction on the surface122of the silicon carbide semiconductor layer102, the semiconductor device is prevented from a decrease in breakdown voltage.

The arrangement of the barrier regions181on the surface122is not limited to the example illustrated inFIG. 21. For example, as illustrated inFIG. 22, the barrier regions181may be staggered in <1-100> direction by half the cycle.

The shape of the boundaries of the barrier regions181may be hexagonal on the surface122of the silicon carbide semiconductor layer102.FIG. 23illustrates the barrier regions181as having regular hexagonal boundaries182on the surface122. The six sides of the regular hexagon are parallel to directions equivalent to [11-20] direction and are all parallel to <11-20> direction. All the inner angles are 120°. As illustrated inFIG. 23, the plurality of barrier regions181are staggered in <1-100> direction by half the cycle.

Further, as illustrated inFIG. 24, the barrier regions181may have hexagonal boundaries182that extend in one direction on the surface122. As illustrated inFIG. 24, the six sides of the hexagon are parallel to directions equivalent to [11-20] direction and are all parallel to <11-20> direction. InFIG. 24, the plurality of barrier regions181are staggered in <1-100> direction by half the cycle.

As described hereinabove, the decrease in the breakdown voltage of the semiconductor device can be suppressed by ensuring that the boundaries between the barrier region151or181and the silicon carbide semiconductor layer102are parallel to <11-20> direction.FIG. 25illustrates an arrangement of the silicon carbide semiconductor layer102and the barrier region that is an inverted version of the arrangement of the silicon carbide semiconductor layer102and the barrier regions181illustrated inFIG. 21. As illustrated inFIG. 25, the barrier region183has boundaries184that define parallelogrammatic blanks on the surface122of the silicon carbide semiconductor layer102. The silicon carbide semiconductor layer102is exposed in the regions enclosed by the boundaries184. The four sides of the boundary184form a parallelogram and are all parallel to <11-20> direction. The barrier region183encloses the exposed portions of the silicon carbide semiconductor layer102.

In the structure described above, the barrier region183represents an increased proportion of the area enclosed by the guard ring subregion154as compared to when the semiconductor device has the barrier regions181illustrated inFIG. 21. Thus, the barrier region183illustrated inFIG. 25allows the semiconductor device to achieve a reduction in leakage current in the reverse direction, namely, when a negative voltage is applied to the upper electrode112relative to the backside electrode113. Further, because the barrier region183exclusively has boundaries whose all sides are parallel to <11-20> direction on the surface122of the silicon carbide semiconductor layer102, the semiconductor device is prevented from a decrease in breakdown voltage.

FIG. 26illustrates an arrangement of the silicon carbide semiconductor layer102and the barrier region that is inverted from the arrangement of the silicon carbide semiconductor layer102and the barrier regions181illustrated inFIG. 24. The barrier region183has hexagonal boundaries184on the surface122of the silicon carbide semiconductor layer102, and the silicon carbide semiconductor layer102is exposed inside the boundaries184. All the six sides of the boundary184are parallel to <11-20> direction. Further, the barrier region183encloses the exposed portions of the silicon carbide semiconductor layer102. With this configuration, the semiconductor device is prevented from a decrease in breakdown voltage.

In the present embodiment, as illustrated inFIG. 1the implanted regions157include the high-concentration regions153and the low-concentration regions155. As illustrated inFIG. 1, the high-concentration regions153are disposed near the surface122of the silicon carbide semiconductor layer102, and the low-concentration regions155are disposed nearer to the semiconductor substrate101than are the high-concentration regions153. Each pair of the high-concentration region153and the low-concentration region155have an identical outline as viewed in the direction normal to the principal surface121of the semiconductor substrate101. With this configuration, the semiconductor device achieves a high breakdown voltage. It is, however, possible to obtain the aforementioned effects of preventing the decrease in breakdown voltage also in JBS semiconductor devices in which the implanted regions include only either of the high-concentration regions and the low-concentration regions, by forming the implanted regions so that the barrier regions will have boundaries with the silicon carbide semiconductor layer102which are parallel to <11-20> direction on the surface122of the silicon carbide semiconductor layer102. In this case too, the decrease in breakdown voltage can be suppressed as compared to when the semiconductor devices include barrier regions having boundaries parallel to <1-100> direction.

While the present embodiment has illustrated the first electrode as including Ti, Ni or Mo, the first electrode may be formed of a material selected from the group consisting of other metals capable of forming a Schottky junction with the silicon carbide semiconductor layer102, and alloys and compounds of such metals.

The widths of the barrier regions and the spacings between the barrier regions are not particularly limited as long as the boundaries between the barrier region and the silicon carbide semiconductor layer are parallel to <11-20> direction. The shape of the barrier regions as viewed from above the surface may be changed appropriately. For example, whileFIG. 21illustrates the barrier regions181as having a parallelogrammatic shape on the surface122, the barrier regions181may have a rhombus shape.

In an embodiment, a barrier film including, for example, TiN may be formed between the first electrode159and the upper electrode112. The thickness of the barrier film is, for example, 50 nm.

While the embodiments of the present disclosure have illustrated the silicon carbide as being 4H—SiC, the silicon carbide is not limited thereto and may be other polytype such as 6H—SiC. Further, while the embodiments of the present disclosure have illustrated the principal surface of the SiC substrate as being offcut relative to (0001) plane, the principal surface of the SiC substrate may be (000-1) plane or a plane with an offcut relative to (000-1) plane.