Semiconductor structure and manufacturing method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.

BACKGROUND

With the advancement of modem technologies, integrated circuits having more functions and greater performance are increasingly demanded. In the packaging of integrated circuits, semiconductor dies are packaged onto package components, which include the circuitry used to route electrical signals. In the conventional flow, the package components is picked and placed on the fan-out structure before the laser drill and clean process, so the subsequently formed bump is easy to crack due to the high warpage issue and the yield of the packaging process is adversely affected. Therefore, there is the need for more creative packaging techniques.

DETAILED DESCRIPTION

FIGS. 1A-1Hare schematic cross-sectional views of various stages of manufacturing a semiconductor structure in accordance with some embodiments, andFIGS. 2A-2Hare schematic top views corresponding toFIGS. 1A-1Hin accordance with some embodiments.

Referring toFIGS. 1A and 2A, a redistribution structure100is formed over a temporary carrier TC. For example, the temporary carrier TC includes glass, silicon, metal, ceramic, combinations thereof, multi-layers thereof, and/or the like. In some embodiments, the temporary carrier TC is provided in a wafer form. Alternatively, the temporary carrier TC may have a rectangular shape or other suitable shape. The temporary carrier TC may be planar to accommodate the formation of features subsequently formed thereon. In some embodiments, the temporary carrier TC is provided with a release layer RL to facilitate a subsequent de-bonding of the temporary carrier TC. The release layer RL may include a layer of light-to-heat-conversion (LTHC) release coating and a layer of associated adhesive. Other suitable release material (e.g., pressure sensitive adhesives, radiation curable adhesives, combinations of these, etc.), which may be removed along with the temporary carrier TC from the overlying structures that will be formed in subsequent steps, may be used. Alternatively, the release layer RL is omitted.

In some embodiments, the formation of the redistribution structure100includes at least the following steps. A first conductive pattern RDL1may be formed over the temporary carrier TC. In some embodiments in which the temporary carrier TC is provided with the release layer RL, the first conductive pattern RDL1is deposited on the release layer RL. For example, a seed layer (not shown) is initially formed on the release layer RL. The seed layer may be a Ti/Cu bilayer, a copper layer, or other suitable metal layer, and may be deposited using any suitable deposition technique such as physical vapor deposition (PVD), e.g., sputtering, evaporation, etc. Next, a patterned photoresist layer having openings (also not shown) may be formed to partially cover the seed layer using such as a spin-coating process, lithography and etching processes, or the like. A conductive material may be formed on the seed layer within the openings of the patterned photoresist layer. The conductive material may include copper, titanium, tungsten, aluminum, another metal, the like, or a combination thereof, and may be formed by such as electroplating or electroless plating, or the like. Subsequently, the patterned photoresist layer may be removed by a suitable removal process such as ashing, stripping, or the like.

After the removal of the patterned photoresist layer, those portions of the seed layer that were covered by the patterned photoresist layer may be removed by any suitable process (e.g., wet etching, dry etching, or the like), and the conductive material may serve as an etch mask during the removal process of the seed layer. The remaining portions of the seed layer and the conductive material thereon collectively form the first conductive pattern RDL1. The first conductive pattern RDL1may be or may include under-bump metallization (UBM) pads for the subsequently formed element landing thereon. In some embodiments, the first conductive pattern RDL1is referred to as a first UBM pattern UBM1in the disclosure. In a top-down view, the first UBM pattern UBM1may be formed in a desired shape, such as a circular, oval, square, rectangular, or polygonal shape, although any desired shape may alternatively be formed.

In some embodiments, after forming the first conductive pattern RDL1, a first conductive via V1is formed on the first conductive pattern RDL1. The material of the first conductive via V1may be similar to the first conductive pattern RDL1. For example, a patterned photoresist layer (not shown) is formed on the release layer RL to partially cover the first conductive pattern RDL1. The openings of the patterned photoresist layer may accessibly reveal desired parts of the first conductive pattern RDL1. Next, the conductive material may be formed on the first conductive pattern RDL1within the openings of the patterned photoresist layer by such as electroplating, electroless plating, or other suitable deposition process. Subsequently, the patterned photoresist layer may be removed. The conductive material plated on the first conductive pattern RDL1may form the first conductive via V1. In some embodiments, the first conductive pattern RDL1and the first conductive via V1are collectively viewed as a redistribution layer at the first level of the redistribution structure100.

In some embodiments, after forming the first conductive via V1, a first dielectric layer PM1is formed over the temporary carrier TC to cover the first conductive pattern RDL1and the first conductive via V1. For example, a dielectric material is formed on the release layer RL by a process such as lamination, spin-coating, CVD, a combination thereof, etc. The dielectric material may be or may include polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), prepreg, Ajinomoto build-up film (ABF), an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a photosensitive polymer material, a combination thereof, and/or the like. The dielectric material is optionally planarized, such as by a chemical mechanical polish (CMP) or a mechanical grinding, to form the first dielectric layer PM1. For example, the first dielectric layer PM1laterally covers the first conductive via V1. In some embodiments, the top surface Ps1of the first dielectric layer PM1is substantially leveled with the first conductive vias V1. In some embodiments, the first conductive vias V1includes substantially vertical sidewalls relative to the top surface of the underlying first conductive pattern RDL1. In some embodiments, the first conductive pattern RDL1and the first conductive via V1embedded in the first dielectric layer PM1are collectively viewed as the first level of the redistribution structure100.

Continue toFIG. 1A, a second conductive pattern RDL2, second conductive vias V2, and a second dielectric layer PM2are then formed on the first conductive vias V1and the first dielectric layer PM1. The second conductive pattern RDL2and the second conductive vias V2are collectively viewed as a redistribution layer at the second level to provide additional routing. In some embodiments, the second conductive pattern RDL2is initially formed on the first conductive vias V1and may extend onto the first dielectric layer PM1using the processes similar to the formation of the first conductive pattern RDL1. Next, the second conductive vias V2is formed on the second conductive pattern RDL2using the processes similar to the formation of the first conductive vias V1. The materials of the second conductive pattern RDL2and the second conductive vias V2may be similar to those of the first conductive pattern RDL1and the first conductive vias V1. Subsequently, the second dielectric layer PM2is formed on the first dielectric layer PM1to cover the second conductive vias V2and the second conductive pattern RDL2using the processes similar to the formation of the first dielectric layer PM1. The material of the second dielectric layer PM2may be similar to or different from the first dielectric layer PM1depending on product and process requirements.

In some alternative embodiments, the first dielectric layer PM1having openings is formed over the temporary carrier TC, and then the first conductive vias V1may be formed on the first conductive pattern RDL1within the openings of the first dielectric layer PM1. In some embodiments, the first conductive vias V1includes inclined sidewalls relative to the top surface of the underlying first conductive pattern RDL1. The second conductive pattern RDL2and the first conductive vias V1may be formed during the same step. Under this scenario, the planarization process may be omitted, and there is no visible interface between the second conductive pattern RDL2and the underlying first conductive vias V1.

Still referring toFIG. 1A, additional conductive patterns (e.g., RDL3, RDL4, RDL5, RDL6, and RDL7), conductive vias (e.g., V3, V4, V5, and V6), and dielectric layers (e.g., PM3, PM4, PM5, PM6, and PM7) may be formed over the second conductive vias V2and the second dielectric layer PM2to provide additional routing. The dielectric layers and the redistribution layers may be alternately formed, and may be formed using processes and materials similar to those used for the underlying dielectric layer or the redistribution layers. The steps of forming the conductive patterns, the conductive vias, and the dielectric layers may be repeated to form the redistribution structure100. It is noted that the redistribution structure100shown inFIG. 1Ais merely an example and may have any suitable number of dielectric layers or redistribution layers. For example, the redistribution structure100includes an N-th conductive pattern and an N-th conductive via that are embedded by an N-th polymer layer, where N is a positive integer. In other embodiments, the redistribution structure100is formed in a different process than described herein.

Still referring toFIG. 1A, in some embodiments, the bottommost conductive via (e.g., the first conductive via V1) may have a critical dimension greater than the critical dimension of the topmost conductive via (e.g., the sixth conductive via V6). For example, the critical dimension (or diameter) Vd1of the first conductive via V1is greater than the critical dimension (or diameter) Vd6of the sixth conductive via V6. For example, the critical dimension Vd1of the first conductive via V1is in a range of about 30 μm and about 1000 μm. The critical dimension Vd6of the sixth conductive via V6may range from about 0.5 μm to about 50 μm. In some embodiments, the diameters of the conductive vias are gradually reduced layer by layer from the bottommost level of the redistribution structure100to the topmost level of the redistribution structure100. It is also noted that the arrangement of the conductive vias V1-V6shown inFIG. 1Ais merely an example, and the conductive vias V1-V6may be fully staggered or partially staggered in the cross-sectional view. In some embodiments, the redistribution structure100is a fan-out structure. The redistribution layers in the redistribution structure100may be fan-out from the topmost level (e.g., RDL7) to the bottommost level (e.g., RDL1). For example, the spacing SP1of the first conductive pattern RDL1at the bottommost level of the redistribution structure100is greater than the spacing SP7of the seventh conductive pattern RDL7at the topmost level of the redistribution structure100. For example, the spacing SP1of the first conductive pattern RDL1is in a range of about 30 μm and about 1000 μm. The spacing SP7of the seventh conductive pattern RDL7at the topmost level of the redistribution structure100may range from about 0.1 μm to about 30 μm.

In some embodiments, at least the topmost dielectric layer (e.g., the seventh dielectric layer PM7) is formed differently from the underlying dielectric layer (e.g., the sixth dielectric layers PM6) or any other dielectric layer below the topmost dielectric layer. For example, the topmost dielectric layer (e.g., the seventh dielectric layer PM7) is formed of a polymer material such as PBO, PI, or the like, and the dielectric layers below the topmost dielectric layer may be formed of a different material, such as by being formed of an ABF or a prepreg material. In some embodiments, the topmost dielectric layer (e.g., the seventh dielectric layer PM7) has a larger thickness than the underlying dielectric layer (e.g., the sixth dielectric layers PM6). However, any combination of materials and thicknesses may be utilized.

Still referring toFIG. 1Aand with reference toFIG. 2A, in some embodiments, the topmost dielectric layer (e.g., the seventh dielectric layer PM7) includes openings OP7accessibly exposing at least a portion of the underlying conductive pattern (e.g., the seventh conductive pattern RDL7) for further electrical connection. In some embodiments, the redistribution layers including the conductive vias and the conductive patterns are formed within a plurality of circuit regions CR. For example, in a top-down view, the circuit regions CR are arranged in an array over the temporary carrier TC. The openings OP7of the topmost dielectric layer (e.g., the seventh dielectric layer PM7) may be distributed within the circuit regions CR. In some embodiments, the neighboring circuit regions CR are separated by a scribe line region SR. During the subsequent singulation process, scribe lines may be located in the scribe line region SR. Each of the circuit regions CR may be similarly sized and shaped, although in other embodiments the circuit regions CR may have different sizes and shapes.

Referring toFIGS. 1B and 2B, a second UBM pattern UBM2and conductive terminals110may be sequentially formed in the openings OP7of the topmost dielectric layer (e.g., the seventh dielectric layer PM7) for further electrical connection. The second UBM pattern UBM2may be a single layer or may include a plurality of layers conformally formed in the openings OP7and on the topmost dielectric layer (e.g., the seventh dielectric layer PM7). In some embodiments, the second UBM pattern UBM2has a recessed top surface UBMt corresponding to each of the openings OP7. For example, the second UBM pattern UBM2includes multiple layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. In such embodiments, the layer of titanium is conformally formed on the topmost dielectric layer (e.g., the seventh dielectric layer PM7) to be in physical and electrical contact with the conductive pattern (e.g., the seventh conductive pattern RDL7) exposed by the openings OP7of the topmost dielectric layer (e.g., the seventh dielectric layer PM7), and then the layer of copper and the layer of nickel are sequentially formed on the layer of titanium. In some embodiments, the second UBM pattern UBM2includes an arrangement of titanium/titanium tungsten/copper, an arrangement of copper/nickel/gold, or other materials or layers of material. Each layer of the second UBM pattern UBM2may be formed by such as plating sputtering, evaporation, or other suitable deposition process depending upon the desired materials. After deposition of the desired layers, lithography and etching processes may be performed to form the second UBM pattern UBM2in a desired shape. For example, the shape of the second UBM pattern UBM2may be circular, oval, square, rectangular, polygon, etc.

In some embodiments, the conductive terminals110are formed on the second UBM pattern UBM2. For example, a pitch110P of the adjacent conductive terminals110is less than 130 μm. In some embodiments, the pitch110P of the adjacent conductive terminals110is less than 10 μm. It is noted that the pitches of the conductive terminals110may be adjusted depending on I/O connectors of a semiconductor device (e.g., the semiconductor device500shown inFIG. 11) that is to be mounted thereon. The conductive terminals110may be or may include solder balls, ball grid array (BGA) connectors, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bumps, or the like. For example, the conductive terminals110are formed by such as plating, ball placement, evaporation, printing, etc. In some embodiments, the conductive terminals110includes solder bump formed by landing solder balls on the recessed top surface UBMt of the second UBM pattern UBM2, and then reflowing the solder material. In some embodiments, the respective conductive terminal110includes a lead-free pre-solder layer, Sn-Ag, or solder material including alloys of tin, lead, nickel, bismuth, silver, copper, combinations thereof, or the like. In some embodiments, the conductive terminals110are formed by plating a solder layer with lithography process followed by reflowing process to reshape the solder layer into the desired bump shapes. In some embodiments, the reflow process is omitted. Alternatively, the second UBM pattern UBM2is omitted, and the conductive terminals110are in physical and electrical contact with the underlying conductive pattern (e.g., the seventh conductive pattern RDL7). The conductive terminals110and the second UBM pattern UBM2may be formed in a different process as will be described later in other embodiments.

Referring toFIGS. 1C and 2Cand also with reference toFIG. 1B, the temporary carrier TC may be de-bonded from the redistribution structure100, and the redistribution structure100may be placed on a tape frame TP. In some embodiments, the temporary carrier TC and the release layer RL are physically separated and removed from the redistribution structure100, so that the first dielectric layer PM1and the first conductive pattern RDL1(i.e. the first UBM pattern UBM1) are exposed for further processing. In some embodiments, the exposed surface Ps2of the first dielectric layer PM1and the exposed surface Rs2of the first conductive pattern RDL1are planar surfaces. For example, the exposed surface Ps2of the first dielectric layer PM1and the exposed surface Rs2of the first conductive pattern RDL1are substantially leveled. The first conductive pattern RDL1(i.e. the first UBM pattern UBM1) exposed by the first dielectric layer PM1may be formed in a desired shape, such as a circular, oval, square, rectangular, or polygonal shape, although any desired shape may alternatively be formed.

The temporary carrier TC may be removed from the redistribution structure100by a thermal process, a mechanical peel-off process, a grinding process, an etching process, combinations of these, and may include additional cleaning process. In some embodiments, suitable energy source, e.g., UV light, UV laser, etc., is applied to weaken the bonds of the release layer RL, so that the temporary carrier TC may be separated from the remaining structure. Next, the resulting structure may be flipped over, and the conductive terminals110may be attached to the tape frame TP. The topmost dielectric layer (e.g., the seventh dielectric layer PM7) may face the tape frame TP. In some embodiments, the topmost dielectric layer (e.g., the seventh dielectric layer PM7) is in physical contact with the tape frame TP. Alternatively, the topmost dielectric layer (e.g., the seventh dielectric layer PM7) is spatially separated from the tape frame TP. In some embodiments, the step of attaching the structure to the tape frame TP is performed prior to the step of de-bonding the temporary carrier.

Referring toFIGS. 1D and 2D, a conductive material layer CM may be formed on the first conductive pattern RDL1(i.e. the first UBM pattern UBM1) of the redistribution structure100. In some embodiments, the conductive material layer CM is formed by printing, dispensing, or other suitable deposition techniques. For example, a stencil having apertures (not shown) is placed over the redistribution structure100, where the apertures of the stencil may be aligned to the exposed surface Rs2of the first conductive pattern RDL1. The apertures may be circular in shape, although through-holes in other stencils may have any shape, such as, oval, rectangular, and the like. After the stencil is placed, a conductive material may be then applied on the stencil and into the through holes of the stencil. In some embodiments, the conductive material is conductive paste including metal particles mixed with an adhesive. For example, the solder paste is utilized. Next, the stencil is removed, and the conductive material left on the exposed surface Rs2of the first conductive pattern RDL1forms the conductive material layer CM.

In some embodiments, the conductive material layer CM is solder flux applied to the first conductive pattern RDL1. The flux may serve primarily to aid the flow of the solder, such that the subsequently formed solder balls may make good contact with the first conductive pattern RDL1. The solder flux may be applied through brushing, spraying, printing, or the like. In some embodiments, the conductive material layer CM is formed on the first conductive pattern RDL1(i.e. the first UBM pattern UBM1) within each of the circuit regions CR as shown inFIG. 2D. It is noted that the shape of the conductive material layer CM shown inFIGS. 1D and 2Dis merely an example and construes no limitation in the disclosure.

Referring toFIGS. 1E and 2E, a circuit substrate120is disposed over and coupled to the redistribution structure100. For example, the circuit substrate120is placed into contact with the conductive material layer CM on the first conductive pattern RDL1(i.e. the first UBM pattern UBM1), and then a high temperature process, such as reflow or thermal compression bonding, may be performed to melt the conductive material layer CM on the first conductive pattern RDL1and/or the solder connectors (not shown) on the circuit substrate120. The melted solder layer may thus join the circuit substrate120and the redistribution structure100together. In some embodiments, reflowed regions formed by melting the solder layer are referred to as conductive joints129. The conductive joints129may be referred to as solder joints in accordance with some embodiments. In some embodiments, the critical dimension and the pitch129P of adjacent conductive joints129are greater than the critical dimension and the pitch of adjacent conductive terminals110. For example, the pitch129P of the adjacent conductive joints129ranges from about 100 μm to about 1000 μm.

For example, at least one of the circuit substrate120is arranged within the respective circuit region CR as shown inFIG. 2E. In some embodiments, multiple circuit substrates120are disposed within the respective circuit region CR. It is noted that the size and the number of the circuit substrate120may be adjusted depending on product requirements and should construe no limitation in the disclosure. In some embodiments, the respective circuit substrate120includes a core layer122, a first build-up layer123and a second build-up layer124disposed on two opposing sides of the core layer122. In some embodiments, the core layer122includes a core dielectric layer1221, a first core conductive layer1222and a second core conductive layer1223disposed on two opposing sides of the core dielectric layer1221. The core dielectric layer1221may be or may include prepreg (e.g., containing epoxy, resin, and/or glass fiber), PI, a combination thereof, or the like. However, other dielectric materials may also be used. The materials of the first core conductive layer1222and the second core conductive layer1223may include copper, gold, tungsten, aluminum, silver, gold, a combination thereof, or the like. In some embodiments, the first core conductive layer1222and the second core conductive layer1223are copper foils coated or plated on the opposite sides of the core dielectric layer1222. In some embodiments, a plurality of conductive through holes1224penetrating through the core layer122provide electrical paths between the electrical circuits located on the opposite sides of the core layer122. The first build-up layer1231may be physically and electrically connected to the second build-up layer1232through the conductive through holes1224.

In some embodiments, the first build-up layer123includes a plurality of first dielectric layers1231and a plurality of first conductive patterns1232alternately stacked over the first side of the core layer122. The second build-up layer124may include a plurality of second dielectric layers1241and a plurality of second conductive patterns1242alternately stacked over the second side of the core layer122. The via portions of the first conductive patterns1232and the via portions of the second conductive patterns1242may be tapered toward the core layer122. Although only two layers of conductive patterns and two layers of dielectric layers are illustrated for each of the first build-up layer123and the second build-up layer124, the scope of the disclosure is not limited thereto. The materials of the first and second dielectric layers1231and1241may be or may include prepreg, PI, PBO, BCB, silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like. In some embodiments, the materials of the first and second conductive patterns1232and1242may be or may include metal, such as aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof.

In some embodiments, the circuit substrate120includes a first mask layer125disposed on the outermost one of the first dielectric layer1231to cover the first conductive patterns1232, and a second mask layer126disposed on the outermost one of the second dielectric layer1241to cover the second conductive patterns1242. The second mask layer126may include a plurality of openings that partially expose the outermost one of the second conductive pattern1242. In some embodiments, the first mask layer125may also include openings (not shown) that partially expose the outermost one of the first conductive pattern1232for further electrical connection. In some embodiments, the materials of the first and second mask layers125and126may be or may include a chemical composition of silica, barium sulfate and epoxy resin, and/or the like. The first and second mask layers125and126may serve as solder masks and may be selected to prevent short, corrosion or contamination of the circuit pattern and protect circuits of the circuit substrate120from external impacts and chemicals. In some embodiments, the conductive joints129are disposed in the openings of the second mask layer126to be in physical and electrical contact with the second conductive pattern1242. Alternatively, the first mask layer125and/or the second mask layer126may be omitted.

In some embodiments, the circuit substrate120may be or may include a printed circuit board (PCB) such as a laminate substrate formed as a stack of multiple thin layers (or laminates) of a polymer material such as bismaleimide triazine (BT), FR-4, ABF, or the like. However, any other suitable substrate, such as a silicon interposer, a silicon substrate, organic substrate, a ceramic substrate, or the like, may also be utilized, and all such redistributive substrates that provide support and connectivity to the redistribution structure100are fully intended to be included within the scope of the embodiments.

Variations of the circuit substrate120will be described later in other embodiments.

Referring toFIGS. 1F and 2F, an insulating encapsulation130is formed on the redistribution structure100to cover the circuit substrate120. The material of the insulating encapsulation130may be or may include a molding compound, an epoxy, a resin, a dispensed molding underfill (DMUF), or a combination thereof, or the like. The insulating encapsulation130may be dispensed using such as a molding process (e.g., a transfer molding process), an injection process, a combination thereof, or the like. In some embodiments, the formation of the insulating encapsulation130includes at least the following steps. A molding chase (not shown) may be disposed over the redistribution structure100, where the circuit substrates120are accommodated in the space defined by the molding chase. For example, blank areas BA, where no circuit region CR is arranged, may be blocked by the molding chase. The insulating material may be injected into the space and spread to mold the circuit substrates120. Since the blank areas BA are masked by the molding chase, the insulating material may be confined within the space. Thus, no insulating material is formed in the blank areas BA. In such embodiments, less amount of the insulating material can be applied. It is noted that the blank areas shown inFIG. 2Fare merely embodiments that are schematically illustrated, and the molding chase may block other regions besides the circuit regions. Alternatively, the blank areas BA are not covered by the molding chase, and after the molding process, the insulating material covers the circuit substrates120and also spreads in the blank areas BA. In some embodiments, the insulating material may be dispensed into the gaps G between the second mask layer126of the circuit substrate120and the first dielectric layer PM1of the redistribution structure100in the cross-sectional view. Next, the insulating material may be cured. After the curing, the molding chase may be removed, and the insulating encapsulation130is formed on the redistribution structure100to encapsulate the circuit substrates120and the conductive joints129.

For example, the insulating encapsulation130may laterally cover the conductive joints129for protection. In some embodiments in which the first dielectric layer PM1is substantially leveled with the first conductive pattern RDL1(i.e. the first UBM pattern UBM1), the insulating encapsulation130is disposed on the first dielectric layer PM1and may further extend to cover the portion of the first conductive pattern RDL1on which the conductive joints129are not formed. In some embodiments, the insulating encapsulation130is formed between neighboring circuit substrates120and extends along the sidewalls120sof the respective circuit substrate120. In some embodiments, the top surface130tof the insulating encapsulation130is substantially leveled with the top surfaces120tof the circuit substrates120. For example, a planarization process (e.g., CMP, grinding, etching, combinations of these, etc.) is performed to level the insulating encapsulation130and the circuit substrates120. In other embodiments, the planarization process is omitted. The insulating encapsulation130may partially cover the sidewalls120sof the circuit substrate120. In some embodiments, the insulating encapsulation130may be rigid enough to provide structural support for the structure. In some embodiments, an underfill layer (not shown) is formed to cover the conductive joints129prior to forming the insulating encapsulation130. The detailed descriptions of the underfill layer will be described later in accompany withFIGS. 3D-3G

Referring toFIGS. 1G and 2G, a singulation process may be performed to separate the structure into a plurality of semiconductor structures10. The singulation process may be performed using any suitable dicing tool (e.g., a blade, a saw, a laser drill, an etching process, combinations thereof, etc.) to cut through and/or remove materials of the different layers of the structure. For example, the dicing tool may cut along scribe lines SL to separate the circuit regions CR so as to form the semiconductor structures10. In some embodiments, the insulating encapsulation130and the underlying redistribution structure100are cut through to form substantially coterminous sidewalls10sof the semiconductor structure10.

Referring toFIGS. 1H and 2Hand also with reference toFIG. 1G, after the singulation process, the semiconductor structures10are separated from the tape frame TP and then placed on a tray cassette TS. The semiconductor structures10on the tray cassette TS may await to transfer to the next station or may ship to customers. As shown inFIG. 1H, the respective semiconductor structure10includes the redistribution structure100, the circuit substrate120disposed on a first side100aof the redistribution structure100, the conductive terminals110distributed on a second side100bof the redistribution structure100opposite to the first side100a, the insulating encapsulation130disposed on the first side100aof the redistribution structure100to at least laterally cover the circuit substrate120. The circuit substrate120is electrically connected to the redistribution structure100through the conductive joints129, and the conductive joints129are formed on the first conductive pattern RDL1(i.e. the first UBM pattern UBM1). The conductive terminals110may be electrically coupled to the circuit substrate120through the redistribution structure100.

In some embodiments, the first conductive pattern RDL1(i.e. the first UBM pattern UBM1) is substantially flush with the first dielectric layer PM1. In some embodiments, a critical dimension of the conductive features in the redistribution structure100close to the first side100ais greater than that of the conductive features in the redistribution structure100away from the first side100a(or close to the second side100b). For example, the spacing SP1of the first conductive pattern RDL1close to the first side100aof the redistribution structure100is greater than the spacing SP7of the seventh conductive pattern RDL7close to the second side100bof the redistribution structure100. The critical dimension of the first conductive via V1close to the first side100aof the redistribution structure100may be greater than the critical dimension of the sixth conductive via V6close to the second side100bof the redistribution structure100. In some embodiments, the pitch110P of the adjacent conductive terminals110is less than the pitch129P of the adjacent conductive joints129. The critical dimension of the respective conductive terminal110may be less than that of the respective conductive joint129.

In some embodiments, since the conductive terminals110are formed on the redistribution structure100prior to mounting the circuit substrate120on the redistribution structure100, a laser drilling process and a ball placement process may be omitted to simplify the manufacturing steps. The warpage of the semiconductor structure10may be reduced by omitting the steps of laser drilling and/or ball placement. In some embodiments, since the blank areas (seeFIG. 2F) are blocked by the molding chase, the dummy substrate is unnecessary to be placed on these blank areas for blocking, and the amount of the insulating material that is used to form the insulating encapsulation130may be reduced. The manufacturing method described above may meet the requirements of lower process costs and prevention of cracking issue causing by high warpage degrees.

FIGS. 3A-3Gare schematic cross-sectional views of various stages of manufacturing a semiconductor structure in accordance with some embodiments, andFIGS. 4A-4Gare schematic top views corresponding toFIGS. 3A-3Gin accordance with some embodiments. Unless specified otherwise, the materials and the formation methods of the components described herein are essentially the same as the like components, which are denoted by like reference numerals shown inFIGS. 1H-2H.

Referring toFIGS. 3A and 4A, the redistribution structure100is formed over the temporary carrier TC, and a plurality of conductive terminals210may be formed on the redistribution structure100. In some embodiments, the redistribution structure100including the conductive patterns (e.g., RDL1-RDL7), the conductive vias (e.g., V1-V6), and dielectric layers (e.g., PM1-PM7) is formed over the temporary carrier TC, and then the second UBM pattern UBM2is formed in the openings OP7of the topmost dielectric layer (e.g., the seventh dielectric layer PM7), and the conductive terminals210are then formed on the second UBM pattern UBM2. The details regarding the formation process and the materials of the redistribution structure100and the second UBM pattern UBM2may be found in the discussion of the embodiments shown inFIGS. 1A and 2A, so the detailed descriptions are not repeated for the sake of brevity.

In some embodiments, the respective conductive terminal210includes a pre-solder layer and a solder layer formed on the pre-solder layer. For example, a pre-solder layer is formed on the second UBM pattern UBM2by plating, sputtering, printing, CVD, or other depositions. The pre-solder layer may be formed of eutectic materials such as an alloy including tin and lead, and/or the like. A solder layer may then be formed by plating, where during the plating the pre-solder layer may serve as a seed layer. The solder layer may be a lead based solder such as Pb or Pb/Sn, a lead free solder such as Sn, Sn/Ag, Sn/Ag/Cu, or other eutectic materials used as lead free solder. The pre-solder layer and the solder layer are optionally subjected to a reflow process to form the conductive terminal210. In some embodiments, before forming the pre-solder layer, a mask layer (e.g., photoresist) is formed and patterned, so that portions of the second UBM pattern UBM2are exposed. Next, the pre-solder layer and the solder layer may be plated in the openings of the mask layer and over the second UBM pattern UBM2. Subsequently, the mask layer is removed.

In some embodiments, the conductive terminals210are formed of non-reflowable materials that do not melt under the melting temperature of solder material. Under this scenario, the sidewalls of the conductive terminals210may remain to be substantially vertical after the reflow process. In some embodiments, the sidewalls210sof the conductive terminals210may be substantially leveled with the sidewalls UBMs of the underlying second UBM pattern UBM2on the top surface of the outermost one of the dielectric layers (e.g., the seventh dielectric layer PM7). In some embodiments, the respective conductive terminal210has a substantially planar top surface210tconnected to the sidewalls210s. Alternatively, the conductive terminals210have rounded top surfaces after the reflow process. Other methods for forming the conductive terminals210may be used. For example, a pitch210P of the adjacent conductive terminals210is less than 130 μm. In some embodiments, the pitch210P of the adjacent conductive terminals210is less than 10 μm. It is noted that the pitches210P of the conductive terminals210may be adjusted depending on I/O connectors of a semiconductor device (e.g., the semiconductor device500shown inFIG. 11) that is to be mounted thereon.

Referring toFIGS. 3B and 4Band also with reference toFIG. 3A, the temporary carrier TC may be removed, and the redistribution structure100may be placed on the tape frame TP. For example, the first dielectric layer PM1and the first conductive pattern RDL1(i.e. the first UBM pattern UBM1) are exposed after removing the temporary carrier TC. In some embodiments, the exposed surface Ps2of the first dielectric layer PM1is substantially flush with the exposed surface Rs2of the first conductive pattern RDL1. In some embodiments, after de-bonding the temporary carrier TC, the resulting structure is overturned to be placed on the tape frame TP. For example, the conductive terminals210are attached to the tape frame, and the first dielectric layer PM1and the first conductive pattern RDL1of the redistribution structure100may face outwardly for further processing. In some embodiments, the redistribution structure100(e.g., the seventh dielectric layer PM7) is in contact with the tape frame TP after placement or during the subsequent processing. In some embodiments, the redistribution structure100(e.g., the seventh dielectric layer PM7) is spaced apart from the tape frame TP. The de-bonding process of the temporary carrier TC and the placement process of the structure on the tape frame TP may be similar to the processes described inFIGS. 1C and 2C, so the detailed descriptions are not repeated for simplicity.

Referring toFIGS. 3C and 4C, a circuit substrate220are coupled to the redistribution structure100. The mounting process of the circuit substrate220may be similar to the mounting process of the circuit substrate120described inFIGS. 1D-1Eand2D-2E, so the detailed descriptions are simplified for the sake of brevity. For example, the conductive material layer is formed on the first conductive pattern RDL1of the redistribution structure100, and then the circuit substrate220is placed into contact with the conductive material layer through a pick-and-place process. Subsequently, the reflow process may be performed to form the conductive joints129coupling the circuit substrate220to the redistribution structure100. In some embodiments, one of the circuit substrates220is disposed on each circuit region CR as shown inFIG. 4C. In some other embodiments, multiple circuit substrates220are disposed within each of the circuit regions CR.

In some embodiments, the circuit substrate220is a coreless circuit board. For example, the circuit substrate220is similar to the circuit substrate120described inFIG. 1E, except that the circuit substrate220is formed without the core layer. In some embodiments, the circuit substrate220includes the first build-up layer123and the second build-up layer124stacked upon one another. In some embodiments, the first dielectric layers1231and the first conductive patterns1232of the first build-up layer123are alternately stacked. The second dielectric layers1241and the second conductive patterns1242of the second build-up layer124may be alternately stacked, where the topmost one of the second conductive patterns1242is physically and electrically connected to the bottommost one of the first conductive patterns1232, and the bottommost one of the first dielectric layers1231is overlaid the topmost one of the second dielectric layers1241. In some embodiments, the via portions of the first conductive patterns1232are tapered toward the second build-up layer124, and the via portions of the second conductive patterns1242may be tapered toward the first build-up layer123. Although only two layers of conductive patterns and two layers of dielectric layers are illustrated for each of the first build-up layer123and the second build-up layer124, the scope of the disclosure is not limited thereto.

In some embodiments, the first mask layer125of the circuit substrate220is disposed on the outermost one of the first dielectric layer1231to cover the first conductive patterns1232, and the second mask layer126may be disposed on the outermost one of the second dielectric layer1241to cover the second conductive patterns1242. In some embodiments, the conductive joints129are disposed in the openings of the second mask layer126to be in physical and electrical contact with the second conductive pattern1242. In some embodiments, the first mask layer125may also include openings (not shown) that partially expose the outermost one of the first conductive pattern1232for further electrical connection. It is noted that the circuit substrate shown inFIG. 3Cis merely an example, and the circuit substrate220may be replaced with the circuit substrate120or may include additional elements or fewer elements.

Referring toFIGS. 3D and 4D, an underfill layer232may be formed on the redistribution structure100to surround the conductive joints129. For example, the underfill layer232is formed on the first dielectric layer PM1by a capillary flow process after the circuit substrate220is mounted on the redistribution structure100. Other method (e.g., a molding process, an injection process, combinations of these, or the like) may be used. In some other embodiments, the underfill layer232may be formed by a suitable deposition method before the circuit substrate220is mounted. The underfill layer232may be or may include a mold underfill, a polymer underfill, a dispensed molding underfill, a resin, or the like. In some embodiments, a liquid epoxy is dispensed between the gap G between the first side100aof the redistribution structure100and the second mask layer126of the circuit substrate220, and then the liquid epoxy is cured to harden. The underfill layer232may provide a certain degree of protection to the conductive joints129.

In some embodiments, a sufficient amount of the underfill layer232is deposited on the first dielectric layer PM1of the redistribution structure100. The underfill layer232may cover the conductive joints129and the first conductive pattern RDL1(i.e. the first UBM pattern UBM1) exposed by the first dielectric layer PM1. In some embodiments, a portion of the underfill layer232extends beyond the gap G and climbs up to cover at least a portion of the sidewalls220sof the circuit substrate220. In some embodiments, the underfill layer232spreads within the respective circuit region CR in the top-down view. In some other embodiments, the underfill layer232extends beyond the area defined by the respective circuit region CR. In the top-down view, the underfill layer232formed in each circuit region CR may be separated from one another or may be completely or partially linked together, depending on how much the amount of the material is deposited. In other embodiments, no underfill layer is formed.

Referring toFIGS. 3E and 4E, an insulating encapsulation234is formed over the first side100aof the redistribution structure100to cover the circuit substrate220and the underfill layer232. The material of the insulating encapsulation234may be similar to that of the insulating encapsulation130described inFIGS. 1F and 2F. In some embodiments, the insulating encapsulation234is formed by such as a molding process, an injection process, combinations of these, or the like. The formation process of the insulating encapsulation234may be similar to that of the insulating encapsulation130described inFIGS. 1F and 2F, except that the blank areas BA may be unmasked. The insulating encapsulation234may be formed over the redistribution structure100to cover the circuit substrates220and the underfill layer232and may also spread in the blank areas BA as shown inFIG. 4E. In some embodiments, the insulating encapsulation234is interposed between neighboring circuit substrates220and may extend along the rest portion of the sidewalls220sof the respective circuit substrate220which is not covered by the underfill layer232. In some embodiments, the top surface234tof the insulating encapsulation234is substantially leveled with the top surfaces220tof the circuit substrates220. For example, the planarization process is performed to level the insulating encapsulation234and the circuit substrates220. Alternatively, the planarization process is omitted.

Referring toFIGS. 3F and 4F, a singulation process may be performed to cut along the scribe lines SL to form a plurality of semiconductor structures20. The singulation process may be similar to the process described inFIGS. 1G and 2G, so the detailed descriptions are not repeated for the sake of brevity. For example, the insulating encapsulation234and the underlying redistribution structure100are cut through to form substantially coterminous sidewalls20sof the semiconductor structure20. In some embodiments, the dicing tool may cut through the insulating encapsulation234, the underlying underfill layer232, and the underlying redistribution structure100to form substantially coterminous sidewalls20sof the semiconductor structure20.

Referring toFIGS. 3G and 4Gand also with reference toFIG. 3F, after the singulation process, the semiconductor structures20are removed from the tape frame TP and then accommodated on the tray cassette TS. For example, the respective semiconductor structure20includes the redistribution structure100, the circuit substrate220disposed over the first side100aof the redistribution structure100and coupled to the redistribution structure100through the conductive joints129, the conductive terminals210distributed on the second side100bof the redistribution structure100opposite to the conductive joints129, the underfill layer232disposed between the redistribution structure100and the circuit substrate220to cover the conductive joints129, the insulating encapsulation234disposed on the first side100aof the redistribution structure100to cover the circuit substrate220and the underfill layer232.

The redistribution structure100may include first conductive pattern RDL1(i.e. the first UBM pattern UBM1) at the first side100aand the second UBM pattern UBM2at the second side100b. The first conductive pattern RDL1may be substantially leveled with the first dielectric layer PM1, and the conductive joints129are formed on the first conductive pattern RDL1. The second UBM pattern UBM2may have a portion disposed on the top surface of the outermost one of the dielectric layers (e.g., the seventh dielectric layer PM7), and the conductive terminals210are formed on the second UBM pattern UBM2. The circuit substrate220may be a coreless circuit board or may be replaced with other types of the support substrate (e.g., PCB, a system board, or the like).

FIGS. 5-10are schematic cross-sectional views of variations of a semiconductor structure in accordance with some embodiments. Unless specified otherwise, the materials and the formation methods of the components described herein are essentially the same as the like components, which are denoted by like reference numerals shown inFIGS. 1-4.

Referring toFIGS. 5-6, semiconductor structures30and40are respectively provided. The semiconductor structures30and40may be similar to the semiconductor structure10described inFIG. 1Hand/or the semiconductor structure20described inFIG. 3G. For example, the semiconductor structure30includes the redistribution structure100, the circuit substrate320coupled to the first side100aof the redistribution structure100through the conductive joints129, the insulating encapsulation130disposed on the first side100aof the redistribution structure100to cover the circuit substrate320, and the conductive terminals310coupled to the second side100bof the redistribution structure100through the second UBM pattern UBM2. The details regarding the circuit substrate320are not shown inFIG. 5, but it should be noted that the circuit substrate320may be similar to the circuit substrate (120or220) or other types of support substrate. In some embodiments, the insulating encapsulation130may be replaced with the underfill layer232and the insulating encapsulation234described inFIG. 3G.

The first conductive pattern RDL1(i.e. the first UBM pattern UBM1) may be substantially coplanar with the first dielectric layer PM1. In some embodiments, a portion of the first conductive pattern RDL1is connected to the conductive joints129and the rest portion of the first conductive pattern RDL1may be covered by the insulating encapsulation130. The topmost one of the conductive patterns (e.g., the seventh conductive pattern RDL7) may be covered by the topmost one of the dielectric layers (e.g., the seventh dielectric layer PM7), and the second UBM pattern UBM2may be formed on the topmost one of the conductive patterns (e.g., the seventh conductive pattern RDL7) inside the openings of the topmost one of the dielectric layers (e.g., the seventh dielectric layer PM7). The second UBM pattern UBM2may be conformally formed on the topmost one of the dielectric layers (e.g., the seventh dielectric layer PM7) and into the openings of the topmost one of the dielectric layers (e.g., the seventh dielectric layer PM7) to be in physical and electrical contact with the topmost one of the conductive patterns (e.g., the seventh conductive pattern RDL7). For example, the second UBM pattern UBM2has the recessed top surface UBMt. A portion of the second UBM pattern UBM2may extend from the openings of the topmost one of the dielectric layers (e.g., the seventh dielectric layer PM7) to the top surface of the seventh dielectric layer PM7.

The respective conductive terminal310may include a pillar portion312formed on the second UBM pattern UBM2and a cap portion314overlying the pillar portion312. For example, the pillar portion312is formed over and electrically couple to the top surface of the second UBM pattern UBM2. The pillar portions312and/or the cap portion314may be formed through plating. For example, the material of the pillar portions312may include copper, a copper alloy, or the like. The cap portions314may be formed on the top surface of the pillar portions312, and may include a material different from the underlying pillar portions312. In some embodiments, the cap portions314include solder materials (e.g., lead-free or lead-containing eutectic alloy). In some embodiments, the cap portions314include nickel, palladium, platinum, gold or the like and alloys such as ENEPIG (electroless nickel, electroless palladium, immersion gold), ENIG (electroless nickel, immersion gold), or other suitable conductive material. In some embodiments, the formation of the cap portions314includes plating a solder layer over each of the pillar portions312. A reflow process is optionally performed on the solder layer to form the cap portions314. The pillar portions312may be formed of non-reflowable materials, and the sidewalls of the pillar portions312may remain to be substantially vertical after the reflow. In some embodiments, the cap portion314and the underlying pillar portion312may have coterminous sidewalls. For example, the sidewalls of the cap portion314may be substantially vertical. In some embodiments, the cap portion314has a substantially planar top surface314tconnected to the vertical sidewalls.

Continue toFIG. 6, the semiconductor structure40is similar to the semiconductor structure30shown inFIG. 5, except that the cap portions414of the conductive terminals410have rounded top surfaces414t. For example, the cap portions414may be formed by plating, ball placement, or other suitable deposition techniques. In some embodiments, the reflow process is performed to form the pillar portions312with the cap portions414overlying the pillar portions312. During the reflow process, the cap portions414may be reshaped into the desired bump shape.

Referring toFIGS. 7-8, semiconductor structures50and60are respectively provided. The semiconductor structures50and60may be similar to the semiconductor structure10described inFIG. 1Hand/or the semiconductor structure20described inFIG. 3G. For example, the semiconductor structure50includes a redistribution structure200, the circuit substrate320coupled to the first conductive pattern RDL1(i.e. the first UBM pattern UBM1) of the redistribution structure200through the conductive joints129, the insulating encapsulation130disposed on the first side200aof the redistribution structure100to cover the circuit substrate320, and the conductive terminals210coupled to the second side100bof the redistribution structure100through the second UBM pattern UBM2. In some embodiments, the insulating encapsulation130may be replaced with the underfill layer232and the insulating encapsulation234described inFIG. 3G. The circuit substrate320may be replaced with the circuit substrate (120or220) or other types of support substrate.

The redistribution structure200may be similar to the redistribution structure100described above, except that the redistribution structure200further includes a polymer layer PM0disposed at the first side200a. For example, the polymer layer PM0underlying the first dielectric layer PM1includes openings (not labeled) accessibly revealing at least a portion of the first conductive pattern RDL1(i.e. the first UBM pattern UBM1), and a portion of the conductive joints129are formed in the openings of the polymer layer PM0to be physically and electrically connected to the first conductive pattern RDL1(i.e. first UBM pattern UBM1). For example, the portion of the conductive joints129is laterally covered by the polymer layer PM0and the rest portion of the conductive joints129is laterally covered by the insulating encapsulation130. In some embodiments, the first dielectric layer PM1is substantially leveled with the first conductive pattern RDL1, and the polymer layer PM0is formed on the first dielectric layer PM1and the first conductive pattern RDL1. A first interface IF1of the first dielectric layer PM1and the polymer layer PM0may be substantially leveled with a second interface IF2of first conductive pattern RDL1and the polymer layer PM0. In some embodiments, the material of the polymer layer PM0is the same or similar to the material of the overlying first dielectric layer PM1. Alternatively, the material of the polymer layer PM0is different from the material of the overlying first dielectric layer PM1. In some embodiments, the thickness of the polymer layer PM0is less than the thickness of the overlying first dielectric layer PM1. Alternatively, the thickness of the polymer layer PM0is substantially equal to or greater than the thickness of the overlying first dielectric layer PM1.

In some embodiments, the polymer material is initially formed on the release layer over the temporary carrier by such as lamination, spin-coating, CVD, a combination thereof, or the like, and then the first conductive pattern RDL1is formed on the polymer material and the first conductive via V1is subsequently formed on the first conductive pattern RDL1. Next, the first dielectric layer PM1is formed on the polymer material to cover the first conductive pattern RDL1and the first conductive via V1. Additional conductive patterns (e.g., RDL2-RDL7), conductive vias (e.g., V2-V6), and dielectric layers (e.g., PM2-PM7) are formed on the first dielectric layer PM1and the first conductive via V1. The formation step may be similar to the processes described inFIG. 1A. Next, the second UBM pattern UBM2and the conductive terminals210may be sequentially formed on the seventh dielectric layer PM7and may be electrically coupled to the underlying conductive patterns. After forming the conductive terminals210, the temporary carrier and the release layer may be removed to expose the polymer material. The resulting structure may be flipped over to be placed on the tape frame for further processing. At this stage, the polymer material may face outwardly for processing. Subsequently, a portion of the polymer material is removed to form the polymer layer PM0with openings accessibly exposing at least a portion of the first conductive pattern RDL1. The openings of the polymer layer PM0may be formed by such as laser drilling, lithography and etching, or other suitable processes. The circuit substrate320may be mounted on the redistribution structure200with the conductive joints129partially disposed in the openings of the polymer layer PM0to be in physical and electrical contact with the first conductive pattern RDL1. The mounting step and the subsequent steps may be similar to the processes shown inFIG. 3C-3G.

In some embodiments, the polymer layer PM0is formed before mounting the circuit substrate320. For example, a part of the redistribution structure200including the dielectric layers (e.g., PM1-PM7), the conductive patterns (e.g., RDL1-RDL7), and the conductive vias (e.g., V1-V6) is formed over the temporary carrier, and then the second UBM pattern UBM2and the conductive terminals210are subsequently formed at the second side200bof the part of the redistribution structure200. The formation step may be similar to the process shown inFIG. 3A. Next, the temporary carrier is de-bonded to expose the first dielectric layer PM1and the first conductive pattern RDL1, and then the structure may be turned upside down to be placed on the tape frame for further processing. The de-bonding step and the placement step may be similar to the processes shown inFIG. 3B. Subsequently, the polymer layer PM0may be formed on the first dielectric layer PM1and the first conductive pattern RDL1. For example, the polymer material is deposited on the first dielectric layer PM1and the first conductive pattern RDL1by such as lamination, spin-coating, CVD, a combination thereof, or the like, and then a portion of the polymer material is removed to accessibly expose the underlying first conductive pattern RDL1by such as laser drilling. Other removal process (e.g., lithography and etching processes) may be used. After forming the polymer layer PM0, the circuit substrate320may be mounted on the redistribution structure200through the conductive joints129. The bottoms of the conductive joints129may be confined within the openings of the polymer layer PM0. The mounting step and the subsequent steps may be similar to the processes shown inFIG. 3C-3G.

Continue toFIG. 8, the semiconductor structure60is similar to the semiconductor structure50, except that the conductive terminals110are formed over the redistribution structure200. For example, the conductive terminals110have cured top surfaces110t, while the conductive terminals210of the semiconductor structure50shown inFIG. 7have substantially planar top surfaces210t. The conductive terminals110are similar to the conductive terminals110described inFIG. 1B, so the detailed descriptions are not repeated for the sake of brevity.

Referring toFIGS. 9-10, semiconductor structures70and80are respectively provided. The semiconductor structures70and80may be similar to the semiconductor structures50and60described inFIGS. 7-8, except for the conductive terminals formed on the redistribution structure200. For example, the semiconductor structure70includes the redistribution structure200having the first side200aand the second side200bopposite to each other, the conductive terminals310formed on the second UBM pattern UBM2at the second side200b, the conductive joints129formed at the first side200aand coupling the first UBM pattern UBM1of the redistribution structure200and the circuit substrate320, and the insulating encapsulation130formed on the polymer layer PM0of the redistribution structure200at the first side200ato cover the circuit substrate320. In some embodiments, the insulating encapsulation130may be replaced with the underfill layer232and the insulating encapsulation234described inFIG. 3G. The circuit substrate320may be replaced with the circuit substrate (120or220) or other types of support substrate. The respective conductive terminal310may include the pillar portion312formed on the second UBM pattern UBM2and the cap portion314overlying the pillar portion312. The cap portion314may have the substantially planar top surface314t. The conductive terminals310may be similar to the conductive terminals310described inFIG. 5, so the detailed descriptions are not repeated for the sake of brevity.

Continue toFIG. 10, the semiconductor structure80is similar to the semiconductor structure70, except for the conductive terminals410. For example, the respective conductive terminal410may include the pillar portion312formed on the second UBM pattern UBM2and the cap portion414overlying the pillar portion312. The cap portion414may have the curved top surface414t. The conductive terminals410may be similar to the conductive terminals410described inFIG. 6, so the detailed descriptions are not repeated for the sake of brevity.

FIG. 11is a schematic cross-sectional view of an application of a semiconductor structure in accordance with some embodiments. Like reference numbers are used to designate like elements.

Referring toFIG. 11, a system package1000is provided. For example, the system package1000includes the semiconductor structure10and a semiconductor device500disposed on the redistribution structure100. The semiconductor device500may be coupled to the semiconductor structure10through the conductive terminals110. For example, the semiconductor device500including active and/or passive components is electrically coupled to the circuit substrate120through the conductive terminals110and the redistribution structure100. The semiconductor structure10may be similar to the semiconductor structure10described inFIG. 1H. The semiconductor structure10of the system package1000may be replaced with any one of the semiconductor structure discussed elsewhere in the disclosure (e.g., the semiconductor structure20shown inFIG. 3F, the semiconductor structure30shown inFIG. 5, the semiconductor structure40shown inFIG. 6, the semiconductor structure50shown inFIG. 7, the semiconductor structure60shown inFIG. 8, the semiconductor structure70shown inFIG. 9, or the semiconductor structure80shown inFIG. 10).

In some embodiments, the semiconductor structure10and the semiconductor device500are separately fabricated. The semiconductor device500may be placed on the conductive terminals110by such as a pick-and-place process, a flip-chip process, or other suitable techniques. In some embodiments, the semiconductor device500is placed and in physical contact with the conductive terminals110, and then a reflow process may be performed to bond the conductive terminals110of the semiconductor structure10to the semiconductor device500. However, any suitable bonding technique may be used to couple the semiconductor device500and the semiconductor structure10.

In some embodiments, the semiconductor device500includes integrated circuit devices, such as transistors, capacitors, inductors, resistors, metallization layers, external connectors, and the like, therein, as desired for a particular functionality. The semiconductor device500may be or may include at least one die(s). For example, the semiconductor device500may be or may include a logic die, a microprocessor die (e.g., a central processing unit (CPU) die), a memory die (e.g., a DRAM die, SRAM die, a stacked memory die, a high-bandwidth memory (HBM) die, etc.), an RF die, a mixed signal die, I/O die, combination of these, or the like. The semiconductor device500may include more than one of the same types of die, or may include different dies. In some embodiments, the semiconductor device500may be or may include package component(s). For example, the semiconductor device500may be or may an integrated fan-out (InFO) package, a system-on-a-chip device, a chip-on-wafer device, the like, or a combination thereof. For example, the semiconductor device500includes at least one die encapsulated by a molding compound and redistribution structures disposed on the molding compound and the die. In some embodiments, the conductive terminals110of the semiconductor structure10may be electrically coupled to the die of the semiconductor device500through the redistribution structures of the semiconductor device500. It is noted that the types of the semiconductor device500construe no limitation in the disclosure.

According to some embodiments, a semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first UBM pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.

According to some alternative embodiments, a manufacturing method of a semiconductor structure e includes at least the following steps. A redistribution structure having a first side and a second side is formed, and forming the redistribution structure includes covering a first UBM pattern by a first dielectric layer to form the first side with a planar surface. A conductive terminal is formed on the second side of the redistribution structure. A circuit substrate is coupled to the redistribution structure through a conductive joint formed on the first UBM pattern at the first side of the redistribution structure. An insulating encapsulation is formed on the redistribution structure to cover the circuit substrate.

According to some alternative embodiments, a manufacturing method of a semiconductor structure e includes at least the following steps. A redistribution structure is formed within a plurality of circuit regions. A plurality of conductive terminals is formed on a side of the redistribution structure within each of the plurality of circuit regions. A plurality of circuit substrates is coupled to an opposing side of the redistribution structure, where at least one of the plurality of circuit substrates is disposed within each of the plurality of circuit regions. An insulating encapsulation is formed on the opposing side of the redistribution structure to cover the plurality of circuit substrates, where other region besides the plurality of circuit regions is blocked so that the insulating encapsulation is formed in the plurality of circuit regions.