Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transistors

A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or carbonated silicon is provided over the substrate of the pixel cell to reduce the dark current leakage.

The present invention relates generally to semiconductor devices, and more particularly, to photodiode transistor isolation technology for use in semiconductor devices, including CMOS image sensors.

BACKGROUND OF THE INVENTION

CMOS image sensors are increasingly being used as low cost imaging devices. A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells includes a photogate, photoconductor, or photodiode having an associated charge accumulation region within a substrate for accumulating photo-generated charge. Each pixel cell may include a transistor for transferring charge from the charge accumulation region to a sensing node, and a transistor, for resetting the sensing node to a predetermined charge level prior to charge transference. The pixel cell may also include a source follower transistor for receiving and amplifying charge from the sensing node and an access transistor for controlling the readout of the cell contents from the source follower transistor.

In a CMOS image sensor, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the sensing node accompanied by charge amplification; (4) resetting the sensing node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge from the sensing node.

CMOS image sensors of the type discussed above are generally known as discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994). See also U.S. Pat. Nos. 6,177,333 and 6,204,524, which describe the operation of conventional CMOS image sensors and are assigned to Micron Technology, Inc., the contents of which are incorporated herein by reference.

A schematic diagram of a conventional CMOS pixel cell10is shown inFIG. 1. The illustrated CMOS pixel cell10is a four transistor (4T) cell. The CMOS pixel cell10generally comprises a photo-conversion device23for generating and collecting charge generated by light incident on the pixel cell10, and a transfer transistor17for transferring photoelectric charges from the photo-conversion device23to a sensing node, typically a floating diffusion region5. The floating diffusion region5is electrically connected to the gate of an output source follower transistor19. The pixel cell10also includes a reset transistor16for resetting the floating diffusion region5to a predetermined voltage; and a row select transistor18for outputting a signal from the source follower transistor19to an output terminal in response to an address signal.

FIG. 2is a cross-sectional view of a portion of the pixel cell10ofFIG. 1showing the photo-conversion device23, transfer transistor17and reset transistor16. The exemplary CMOS pixel cell10has a photo-conversion device23may be formed as a pinned photodiode. The photodiode23has a p-n-p construction comprising a p-type surface layer22and an n-type photodiode region21within a p-type active layer11. The photodiode23is adjacent to and partially underneath the transfer transistor17. The reset transistor16is on a side of the transfer transistor17opposite the photodiode23. As shown inFIG. 2, the reset transistor16includes a source/drain region2. The floating diffusion region5is between the transfer and reset transistors17,16.

In the CMOS pixel cell10depicted inFIGS. 1 and 2, electrons are generated by light incident on the photo-conversion device23and are stored in the n-type photodiode region21. These charges are transferred to the floating diffusion region5by the transfer transistor17when the transfer transistor17is activated. The source follower transistor19produces an output signal from the transferred charges. A maximum output signal is proportional to the number of electrons extracted from the n-type photodiode region21.

Conventionally, a shallow trench isolation (STI) region3adjacent to the charge collection region21is used to isolate the pixel cell10from other pixel cells and devices of the image sensor. The STI region3is typically formed using a conventional STI process. The STI region3is typically lined with an oxide liner38and filled with a dielectric material37. Also, the STI region3can include a nitride liner39. The nitride liner39provides several benefits, including improved corner rounding near the STI region3corners, reduced stress adjacent the STI region3, and reduced leakage for the transfer transistor17.

A common problem associated with a pixel cell is dark current—the discharge of the pixel cell's capacitance even though there is no light over the pixel. Dark current may be caused by many different factors, including: photodiode junction leakage, leakage along isolation edges, transistor sub-threshold leakage, drain induced barrier lower leakage, gate induced drain leakage, trap assisted tunneling, and other pixel defects. The obvious trend in the industry is to scale down the size of transistors in terms of both gate length and gate width (i.e., “scaling”). As devices are increasingly scaled down, dark current effect generally increases.

Therefore, it is desirable to have an improved isolation structure for reducing dark current and fixed pattern noise.

BRIEF SUMMARY OF THE INVENTION

A pixel cell is provided having a substrate with an isolation channel of higher carbon concentrate SiC provided in an exemplary embodiments of the invention. The channel comprising SiC or carbonated silicon is provided above the layer of Si in the substrate of the pixel cell to reduce the leakage of dark current.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and illustrate specific embodiments in which the invention may be practiced. In the drawings, like reference numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

The terms “wafer” and “substrate” are to be understood as including silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-nothing (SON) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, or gallium-arsenide.

The term “pixel” or “pixel cell” refers to a picture element unit cell containing a photo-conversion device and transistors for converting electromagnetic radiation to an electrical signal. For purposes of illustration, a portion of a representative pixel cell is illustrated in the figures and description herein, and typically fabrication of all pixel cells in an image sensor will proceed concurrently and in a similar fashion.

FIG. 3is a cross-sectional view of a pixel cell300according to an exemplary embodiment of the invention. The pixel cell300is similar to the pixel cell10depicted inFIGS. 1 and 2, except that the pixel cell300includes an isolation channel301above the silicon layer311. The isolation channel301is preferably constructed of SiC or channeled carbonated Silicon. The use of a carbon rich layer of material increases the bandgap of the device. Isolation channel301has a higher bandgap than Si, typically sixteen (16) orders of magnitude lower than Si, and the resulting pixel cell300has a lower intrinsic carrier concentration. Therefore, the isolation channel301reduces the dark current level.

Until recently, growing high quality SiC substrates was prohibitively expensive and therefore SiC was used only in selective applications. Recent advances in growing SiC epitaxially have made it less expensive and decreased the defect densities. These advances have made it more possible to use SiC substrates in conventional applications. As the SiC channel can be built or grown on conventional Si layer and as part of a conventional Si process, it can be incorporated in a process that also forms a CMOS photodiode. Recent technological advances in forming the SiC layers can be found, for example, in “A new Si:C epitaxial channel nMosfet Architecture with improved drivability and short-channel characteristics”, T. Ernest et al, 2003Symposium on VLSI Technology Digest of Technical Papers, pp. 2-93; “Fabrication of a novel strained SiGe:C-channel planar 55 nm nMosfet for High Performance CMOS”, T. Ernest et al, 2002Symposium on VLSI Technology Digest of Technical Papers, pp. 92-93; and “Selective growth of high-quality 3C—SiC using a SiO2 sacrificial layer technique”,Thin Solid Films, Vol. 345 (2) (1999), pp. 19-99.

The use of SiC or Carbonated Silicon Channels as an isolation channel in a pixel cell reduces dark current levels. Because dark current levels are reduced, the present invention permits greater scaling in the pixel cells arrays. Greater scaling enables a larger fill factor.

The use of SiC or Carbonated Silicon Channels as an isolation channel in a pixel cell also creates additional advantages because of the inherent properties of the materials. Specifically, carbonated silicon materials permit a high temperature operation and enable a pixel cell the ability to sustain high electric fields. Additionally, these materials also have the property of effectively dissipating heat.

FIGS. 4A-4Jdepict the formation of pixel cell300according to an exemplary embodiment of the invention. The steps described herein need not be performed in any particular order, except for those logically requiring the results of prior actions. Accordingly, while the steps below are described as being performed in a general order, the order is exemplary only and can be altered if desired.

As illustrated inFIG. 4A, a pad oxide layer441, which can be a thermally grown oxide, is formed on the substrate311. A sacrificial layer442is formed on the pad oxide layer441. The sacrificial layer442can be a nitride or dielectric anti-reflective coating (DARC) layer.

FIG. 4Bdepicts the formation of a trench430in the substrate11and through the layers441,442on the substrate311. The trench430can be formed by any known technique. For example, a patterned photoresist layer (not shown) is used as a mask for an etching process. The first etch is conducted utilizing dry plasma conditions and difloromethane/carbon tetrafluoride (CH2F2/CF4) chemistry. Such etching effectively etches both silicon nitride layer442and pad oxide layer441to form an opening extending therethrough which stops upon reaching the substrate311. A second etch is conducted to extend the openings into the substrate311. The second etch is a dry plasma etch utilizing difloromethane/hydrogen bromide (CH2F2/HBr) chemistry. The timing of the etch is adjusted to form the trench430within substrate311to the desired depth. A shorter etch time results in a shallower trench430. The photoresist mask (not shown) is removed using standard photoresist stripping techniques, preferably by a plasma etch.

A thin insulator layer338, between approximately 50 Å and approximately 250 Å thick, is formed on the trench430sidewalls336a,336band bottom308, as shown inFIG. 4C. In the embodiment depicted inFIG. 4C, the insulator layer338is an oxide layer338is preferably grown by thermal oxidization.

The trench430can be lined with a barrier film339. In the embodiment shown inFIG. 4C, the barrier film339is a nitride liner, for example, silicon nitride. The nitride liner339is formed by any suitable technique, to a thickness within the range of approximately 50 Å to approximately 250 Å. Silicon nitride liner339can be formed by depositing ammonia (NH3) and silane (SiH4), as is known in the art.

The trench430is filled with a dielectric material337as shown inFIG. 4C. The dielectric material337may be an oxide material, for example a silicon oxide, such as SiO or silicon dioxide (SiO2); oxynitride; a nitride material, such as silicon nitride; silicon carbide; a high temperature polymer; or other suitable dielectric material. In the illustrated embodiment, the dielectric material337is a high density plasma (HDP) oxide.

A chemical mechanical polish (CMP) step is conducted to remove the nitride layer339over the surface of the substrate311outside the trench430and the nitride layer442, as shown inFIG. 4E. Also, the pad oxide layer441is removed, for example, using a field wet buffered-oxide etch step and a clean step.

FIG. 4Fdepicts the formation of isolation channel301. The epitaxial isolation channel301is preferably grown by conventional means (e.g., the method outlined by Ernst, supra.). In a preferred embodiment, the epitaxial channel is grown at a low temperature. The isolation channel301in a preferred embodiment is preferably SiC or Carbonated Channel Silicon. The isolation channel301need not be grown uniformly; therefore, the depth of the isolation channel301over the field regions (e.g., trench430) may be smaller than the depth of the layer of isolation channel over the non-field regions.

In a preferred embodiment, the carbon concentration is the isolation channel301is adjusted. It is known that controlling the temperature at which the Si:C is grown affects the carbon concentration of the isolation channel301.

In one embodiment of the invention, the isolation channel is only located in the transistor region. In another embodiment of the invention, the isolation channel is grown over another region of the substrate, e.g., a photo diode region. In yet another embodiment, the isolation channel is grown over the periphery array of the intended cell. In yet another embodiment, the isolation channel is grown over several regions, i.e., combinations of previously mentioned locations, for example, as shown inFIGS. 5 and 6as described below. Although not shown, a nitride layer is formed prior to the formation of the isolation channel. The nitride deposition is patterned to expose particular areas to the formation of the isolation channel301depending on the aspect of the invention.

A planarization is conducted on the isolation channel301, resulting in a relatively uniform height of the layer as seen inFIG. 4G. The layer height can range from 100 Å to 500 Å, where the typical height is approximately 250 Å. In one embodiment of the invention, the height of the isolation channel301is approximately 250 Å above the non-field region and the height of the isolation channel301is less than approximately 250 Å above the field regions.

Following the planarization step, the nitride layer deposited prior to the formation of the isolation channel301is removed by a chemical mechanical polish (CMP) step. The nitride may be selectively removed depending on the embodiment of the invention. For example, in a certain embodiment, it may be desirable not to remove the nitride layer along the periphery of the cell.

FIG. 4Hdepicts the formation of the transfer transistor317(FIG. 3) gate stack407and the reset transistor316(FIG. 3) gate stack406. Although not shown, the source follower and row select transistors19,18(FIG. 1), respectively, can be formed concurrently with the transfer and reset transistors317,316as described below.

To form the transistor gate stacks407,406as shown inFIG. 4H, a first insulating layer401aof, for example, silicon oxide is grown or deposited on the substrate311. In a preferred embodiment, the gate oxidation is formed by either rapid thermal oxidation (“RTO”) or in-site stem generation (ISSG). The first insulating layer401aserves as the gate oxide layer for the subsequently formed transistor gate401b. Next, a layer of conductive material401bis deposited over the oxide layer401a. The conductive layer401bserves as the gate electrode for the transistors317,316(FIG. 3). The conductive layer401bmay be a layer of polysilicon, which may be doped to a second conductivity type, e.g., n-type. A second insulating layer401cis deposited over the conductive layer401b. The second insulating layer401cmay be formed of, for example, an oxide (SiO2), a nitride (silicon nitride), an oxynitride (silicon oxynitride), ON (oxide-nitride), NO (nitride-oxide), or ONO (oxide-nitride-oxide).

The gate stack layers401a,401b,401cmay be formed by conventional deposition methods, such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD), among others. The layers401a,401b,401care then patterned and etched to form the multilayer gate stacks407,406shown inFIG. 4F.

The invention is not limited to the structure of the gate stacks407,406described above. Additional layers may be added or the gate stacks407,406may be altered as is desired and known in the art. For example, a silicide layer (not shown) may be formed between the gate electrodes401band the second insulating layers401c. The silicide layer may be included in the gate stacks407,406, or in all of the transistor gate stack structures in an image sensor circuit, and may be titanium silicide, tungsten silicide, cobalt silicide, molybdenum silicide, or tantalum silicide. This additional conductive layer may also be a barrier layer/refractor metal, such as titanium nitride/tungsten (TiN/W) or tungsten nitride/tungsten (WNx/W), or it could be formed entirely of tungsten nitride (WNx).

Doped p-type wells334,335are implanted into the substrate311as shown inFIG. 4I. The first p-well334is formed in the substrate311surrounding the isolation region333and extending below the isolation region333. The second p-well335is formed in the substrate311from a point below the transfer gate stack407extending in a direction in the substrate311away from where the photodiode323(FIG. 3) is to be formed.

The p-wells334,335are formed by known methods. For example, a layer of photoresist (not shown) can be patterned over the substrate311having an opening over the area where the p-wells,334,335are to be formed. A p-type dopant, such as boron, can be implanted into the substrate311through the opening in the photoresist. The p-wells334,335are formed having a p-type dopant concentration that is higher than adjacent portions of the substrate311. Alternatively, the p-wells334,335can be formed prior to the formation of the trench430.

As depicted inFIG. 4J, a doped n-type region321is implanted in the substrate311(for the photodiode323ofFIG. 3). For example, a layer of photoresist (not shown) may be patterned over the substrate311having an opening over the surface of the substrate311where photodiode323(FIG. 3) is to be formed. An n-type dopant, such as phosphorus, arsenic, or antimony, may be implanted through the opening and into the substrate311. Multiple implants may be used to tailor the profile of region321. If desired, an angled implantation may be conducted to form the doped region321, whereby the implantation is carried out at angles other than 90 degrees relative to the surface of the substrate311.

As shown inFIG. 4J, the n-type region321is formed from a point adjacent the transfer gate stack407and extending in the substrate311between the gate stack407and the isolation region333. The region321forms a photosensitive charge accumulating region for collecting photo-generated charge.

The floating diffusion region305and source/drain region302are implanted by known methods to achieve the structure shown inFIG. 4J. The floating diffusion region305and source/drain region302are formed as n-type regions. Any suitable n-type dopant, such as phosphorus, arsenic, or antimony, may be used. The floating diffusion region305is formed on the side of the transfer gate stack407opposite the n-type photodiode region321. The source/drain region302is formed on a side of the reset gate stack406opposite the floating diffusion region305.

FIG. 4Kdepicts the formation of a dielectric layer307. Illustratively, layer307is an oxide layer, but layer307may be any appropriate dielectric material, such as silicon dioxide, silicon nitride, an oxynitride, or tetraethyl orthosilicate (TEOS), among others, formed by methods known in the art.

The doped surface layer322for the photodiode323is implanted, as illustrated inFIG. 4L. Doped surface layer322is formed as a highly doped p-type surface layer and is formed to a depth of approximately 0.1 μm. A p-type dopant, such as boron, indium, or any other suitable p-type dopant, may be used to form the p-type surface layer322.

The p-type surface layer322may be formed by known techniques. For example, layer322may be formed by implanting p-type ions through openings in a layer of photoresist. Alternatively, layer322may be formed by a gas source plasma doping process, or by diffusing a p-type dopant into the substrate311from an in-situ doped layer or a doped oxide layer deposited over the area where layer322is to be formed.

The oxide layer307is etched such that remaining portions form a sidewall spacer on a sidewall of the reset gate stack406. The layer307remains over the transfer gate stack407, the photodiode323, the floating diffusion region305, and a portion of the reset gate stack406to achieve the structure shown inFIG. 3. Alternatively, a dry etch step can be conducted to etch portions of the oxide layer307such that only sidewall spacers (not shown) remain on the transfer gate stack407and the reset gate stack406.

Conventional processing methods can be used to form other structures of the pixel300. For example, insulating, shielding, and metallization layers to connect gate lines, and other connections to the pixel300may be formed. Also, the entire surface may be covered with a passivation layer (not shown) of, for example, silicon dioxide, borosilicate glass (BSG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG), which is CMP planarized and etched to provide contact holes, which are then metallized to provide contacts. Conventional layers of conductors and insulators may also be used to interconnect the structures and to connect pixel300to peripheral circuitry.

FIG. 5depicts a pixel cell500in accordance with another exemplary embodiment of the invention. The pixel cell500is similar to the pixel cell300(FIG. 3) except that isolation channel507is only applied to a portion of the image sensor array of pixel cell500.

FIG. 6depicts a pixel cell501in accordance with another exemplary embodiment of the invention. The pixel cell501is similar to the pixel cell300(FIG. 3) except that isolation channel517is only applied to a portion of the image sensor array of pixel cell501. In a preferred embodiment, the isolation channel517is applied to the source drain regions surrounding the array transistor and on the surface region of the photodiode303, as seen inFIG. 6.

While the above embodiments are described in connection with the formation of p-n-p-type photodiodes the invention is not limited to these embodiments. The invention also has applicability to other types of photo-conversion devices, such as a photodiode formed from n-p or n-p-n regions in a substrate, a photogate, or a photoconductor. If an n-p-n-type photodiode is formed the dopant and conductivity types of all structures would change accordingly.

Although the above embodiments are described in connection with 4T pixel cell300, the configuration of pixel cell300is only exemplary and the invention may also be incorporated into other pixel circuits having different numbers of transistors. Without being limiting, such a circuit may include a three-transistor (3T) pixel cell, a five-transistor (5T) pixel cell, a six-transistor (6T) pixel cell, and a seven-transistor pixel cell (7T). A 3T cell omits the transfer transistor, but may have a reset transistor adjacent to a photodiode. The 5T, 6T, and 7T pixel cells differ from the 4T pixel cell by the addition of one, two, or three transistors, respectively, such as a shutter transistor, a CMOS photogate transistor, and an anti-blooming transistor. Further, while the above embodiments are described in connection with CMOS pixel cell300the invention is also applicable to pixel cells in a charge coupled device (CCD) image sensor.

A typical single chip CMOS image sensor600is illustrated by the block diagram ofFIG. 7. The image sensor600includes a pixel cell array680having one or more pixel cell300,500, or501(FIGS. 3,5, or6respectively) described above. The pixel cells of array680are arranged in a predetermined number of columns and rows.

The rows of pixel cells in array680are read out one by one. Accordingly, pixel cells in a row of array680are all selected for readout at the same time by a row select line, and each pixel cell in a selected row provides a signal representative of received light to a readout line for its column. In the array680, each column also has a select line, and the pixel cells of each column are selectively read out in response to the column select lines.

The row lines in the array680are selectively activated by a row driver682in response to row address decoder681. The column select lines are selectively activated by a column driver684in response to column address decoder685. The array680is operated by the timing and control circuit683, which controls address decoders681,685for selecting the appropriate row and column lines for pixel signal readout.

The signals on the column readout lines typically include a pixel reset signal (Vrst) and a pixel image signal (Vphoto) for each pixel cell. Both signals are read into a sample and hold circuit (S/H)686in response to the column driver684. A differential signal (Vrst−Vphoto) is produced by differential amplifier (AMP)687for each pixel cell, and each pixel cell's differential signal is digitized by analog-to-digital converter (ADC)688. The analog-to-digital converter688supplies the digitized pixel signals to an image processor689, which performs appropriate image processing before providing digital signals defining an image output.

FIG. 8illustrates a processor-based system700including the image sensor600ofFIG. 7. The processor-based system700is exemplary of a system having digital circuits that could include image sensor devices. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, and other systems requiring image acquisition.

The processor-based system700, for example a camera system, generally comprises a central processing unit (CPU)795, such as a microprocessor, that communicates with an input/output (I/O) device791over a bus793. Image sensor600also communicates with the CPU795over bus793. The processor-based system700also includes random access memory (RAM)792, and can include removable memory794, such as flash memory, which also communicate with CPU795over the bus793. Image sensor600may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, with or without memory storage on a single integrated circuit or on a different chip than the processor.

It is again noted that the above description and drawings are exemplary and illustrate preferred embodiments that achieve the objects, features and advantages of the present invention. It is not intended that the present invention be limited to the illustrated embodiments. Any modification of the present invention which comes within the spirit and scope of the following claims should be considered part of the present invention. For example, although described the exemplary embodiment is described with reference to a CMOS p-n-p pixel cell, the invention is not limited to that structure (e.g., and is applicable to other configurations of pixel cells, both active and passive), nor is the invention limited to that technology (e.g., and is applicable to CCD technology as well).