Insulated gate power device using a MOSFET for turning off

An insulated gate turn-off (IGTO) device has a PNPN layered structure so that vertical NPN and PNP transistors are formed. Trench gates are formed extending into the intermediate P-layer. The device is formed of an array of cells. A P-channel MOSFET, having a trenched gate, is formed in some of the cells. The control terminal of the IGTO device is connected to the insulated gates of all cells, including to the gate of the P-channel MOSFET, and to the intermediate P-layer. To turn the device on, a positive voltage is applied to the control terminal to turn on the NPN transistor by forward biasing its base-emitter. To turn off the IGTO device, a negative voltage is applied to the control terminal to turn on the P-channel MOSFET to short the NPN base to its emitter.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on provisional application Ser. No. 62/102,864, filed Jan. 13, 2015, by Vladimir Rodov et al., assigned to the present assignee and incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates to insulated gate turn-off (IGTO) devices and, more particularly, to IGTO devices that include improved turn-off and turn-on features.

BACKGROUND

U.S. Pat. No. 8,878,238, assigned to the present assignee and incorporated herein by reference, describes an IGTO device using trench gates and having PNPN layers which form vertical NPN and PNP bipolar transistors. When the gate is biased sufficiently high, the beta of the NPN transistor increases due to its base being narrowed by the gate field, causing the product of the betas of the NPN and PNP transistors to be greater than one. This condition initiates the turn-on of the IGTO device. To turn the device off, the gate is grounded, increasing the base width of the NPN transistor. No negative gate voltage is needed to turn off the device. This device works well but, with high currents, latch-up may occur, preventing the device to be turned off by grounding the gate. Further, the turn on and off voltages are susceptible to variations from lot to lot.

What is needed is an IGTO device with improved turn on and turn off characteristics.

SUMMARY

In one embodiment, a turn-off structure is included in a trench-gate IGTO device, where the turn off structure comprises a vertical P-channel MOSFET that is only turned on when its gate is sufficiently negative relative to the cathode (the top terminal). The IGTO device comprises a vertical PNPN structure plus the P-channel MOSFET. The PNPN structure forms a vertical NPN transistor and a vertical PNP transistor.

In one embodiment, the IGTO device is turned on by applying a positive bias to a diode coupled to the base of the NPN transistor to forward bias its base-emitter junction to turn it on and inject positive carriers (holes) into the base. The P-type base is also the source of the P-channel MOSFET. The diode allows current to flow into the NPN transistor base while the device is turned on but prevents current from flowing into the control terminal when the P-channel MOSFET gate is made negative for turning the P-channel MOSFET on, which turns off the IGTO device, since the diode is reversed biased in this condition.

Turning on of the P-channel MOSFET (with the negative gate voltage) effectively shorts the emitter and base of the NPN transistor together to force the NPN transistor to turn off, which immediately shuts off the IGTO device. At the same time, the positive voltage applied to the base of the NPN transistor is removed.

In another embodiment, an N-channel MOSFET is used to inject carriers (electrons) into the base of the PNP transistor in the IGTO device to initiate turn on of the IGTO device when a positive control voltage is applied to the IGTO device. This N-channel MOSFET may be formed along the sidewall of an insulated trench gate. The P-channel MOSFET, previously described, is turned on by a negative control voltage to force the NPN transistor off, which turns off the IGTO device.

The P-channel MOSFET and N-channel MOSFET do not need to be adjacent every trench gate, but can be distributed throughout the array of gates.

Each of the two embodiments may be realized as a 3 terminal device (anode, cathode, control terminal), or the device may be a 4-teminal device where the transistor base may be connected to an independent control voltage.

Other embodiments are described.

Elements that are the same or equivalent are labelled with the same numerals.

DETAILED DESCRIPTION

The IGTO devices of the various embodiments may be packaged circuits formed on a single chip. The chip may have 3 or 4 terminals.

FIG. 1illustrates a small portion of an IGTO device10.FIG. 1shows a trenched gate12, such as doped polysilicon, oxide14insulating the gate12, a P+ region16(a drain region for a P-channel MOSFET), an N-region18(an emitter for a vertical NPN transistor), an N+ contact20for the N-region18, a cathode metal22shorting the N-region18to the P+ region16, a P-layer24(a base of the NPN transistor), an N−-layer26(a collector of the NPN transistor), an N-buffer layer28(part of the collector layer), a P+ layer30(the silicon growth substrate and an emitter for a vertical PNP transistor), an anode metal31contacting the P+ layer30, a P+ contact region32for the P− layer24, a cathode terminal34, an anode terminal36, a control terminal38connected to all the gates12, and a diode40connected between the control terminal38and the P+ contact region32. The diode40may be integrated in the IGTO device chip or may be an external component for a 4-terminal device. The diode40may instead be separate from the IGTO chip but packaged in the same package as the chip.

A resistor may also be included in series with the diode40to adjust the voltage applied to the P+ contact region32.

The various regions' relative dopant levels are identified above by the + or − designation after the conductivity type. The P-layer24may be an epitaxial layer doped while growing, or a doped starting wafer with regions diffused in one or both surfaces, or may be an implanted well.

The particular configurations of the regions inFIG. 1are used to rapidly turn off the IGTO device with a very repeatable negative gate threshold voltage irrespective of whether the device is in a high-current latch-up condition.

The various regions and gates12shown inFIG. 1may repeat to form an array of cells in the silicon chip, or the configuration ofFIG. 1may be distributed throughout a large array of cells where, for most of the cells, there is only an N-emitter layer between the trenched gates (as depicted inFIG. 3).

FIG. 2shows an equivalent circuit with certain lines labeled with the element numbers inFIG. 1to show the corresponding regions and gates.

It is assumed that a positive voltage is connected to the anode terminal36and a negative voltage (relative to the positive voltage) is connected to the cathode terminal34. A load may have one terminal connected to the cathode terminal34and another terminal connected to ground so that turning on of the IGTO device10conducts current through the load.

When a sufficiently high positive voltage (relative to the cathode voltage) is applied to the control terminal38, such as 2-5 volts, the IGTO device10is turned on as follows. (The threshold voltage is dependent on the dopant levels and configurations of the various layers and regions.) The operation of the IGTO device10will be explained with reference to the equivalent circuit ofFIG. 2.

A bipolar PNP transistor44is formed by the P+ layer30(emitter), the N− layers26/28(base), and the P-layer24(collector). A bipolar NPN transistor46is formed by the N-region20/18(emitter), the P-layer24(base), and N-layers26/28(collector).

The positive voltage applied to the control terminal38positively biases the P-type layer24, via the P+ contact region32and the diode40, which forward biases the base-emitter of the NPN transistor46to turn on the NPN transistor. This injects positive carriers (holes) into the base of the NPN transistor and initiates the turn on of the IGTO device to start the flow of current between the cathode terminal34and the anode terminal36. The IGTO device on-resistance is further reduced as the carriers are injected into the various layers to reduce the on-resistance of the lightly-doped layers24,26, and28.

When the gate voltage is sufficiently negative (e.g. −5 volts) to turn on the P-channel MOSFET50(formed of the gate12, the P+ region16, the N-region18, and the P-layer24), the P-channel MOSFET50effectively shorts the emitter and base of the NPN transistor46to immediately turn it off, even if there was a high-current latch-up condition. The threshold voltage for the P-channel MOSFET50is easily repeatable from lot to lot, so the turn-off voltage for the IGTO device is very predictable.

The diode40is connected between the control terminal38and the P+ contact region32for the P-layer24(part of the base of the NPN transistor), where the P-layer24is also the source of the P-channel MOSFET50. The diode40allows current to flow into the NPN base while the IGTO device is turned on with a positive control terminal38voltage but blocks any current when the control terminal38is made negative when turning off the IGTO device. The diode40also limits the level of the gate control voltage with respect to the NPN transistor base voltage. The diode40can be integrated on the same chip as the IGTO device10or can be external to the chip.

The dopant levels and the dimensions of the various regions and layers are dependent on the current and breakdown voltage requirements of the IGTO device. Suitable dimensions for a particular application can be determined by simulation by one skilled in the art without undue experimentation.

The P+ region16reduces the NPN transistor emitter area, so the P-channel MOSFET50structures need not be in every cell. The IGTO device may have strips of the P+ regions16parallel to strips of the trenched gates to form an array cells, and the cells are connected in parallel by the cathode and anode metal layers. All the cells may be formed in the common P-layer24. All trench gates are electrically connected together, such as with a polysilicon bus, and are controlled by the control terminal38. Every nth cell (e.g., every tenth cell) may include the P-channel MOSFET50to turn off the IGTO device. Turning on the distributed P-channel MOSFET50will sufficiently short the emitters and bases of all the NPN transistors formed in the cell array, assuming they all share the common P-layer24.

FIG. 3is a top down view of a small repeating portion of an IGTO device56, which incorporates the structure ofFIG. 1, showing an array of trench gates12A-12D and the top doped areas of the device56. The cells are arranged in horizontal stripes, but other shapes of the cells can be used, such as hexagons, squares, etc. The regions are labeled with the same numerals used inFIG. 1. Note that the center area (a single cell) between gates12B and12C is the same structure shown inFIG. 1. The cells above and below the center area do not include the P-channel MOSFET50(FIG. 2) but include a continuous N+ region58A and58B, acting as an emitter for the NPN transistor. Such cells have a higher current density than the ones with the P-channel MOSFET since they have a larger emitter.

The conductivity types inFIGS. 1-3may be reversed and the control voltages would be the opposite polarity.

In one embodiment, the IGTO device is a 3-terminal device where the control terminal is connected to all the gates. In another embodiment, the IGTO device is a 4-terminal device with one control terminal coupled to all the gates and another terminal coupled to the diode40and the P+ contact region32. This configuration allows some added control of the timing of the turn off, such as applying the turn off signals to the two control terminals at different times, making the turn off more gradual to reduce EMI. Making the control terminals independent also allows the control voltages to be different to allow optimal control voltages to be applied to the gates and to the P+ region32. The control voltages may be ramped or stepped to control the turn-on/off characteristics.

FIG. 4illustrates an alternative “turn-on” feature for an IGTO device. The cell structure on the right side ofFIG. 4may be the same as the cell structure ofFIG. 1, and the regions/layers are labeled with the same numerals. The vertical N-channel MOSFET60on the left side ofFIG. 4extends through the P-layer24and into the N−-layer26. This structure can be obtained by making the P-layer24shallower or making the trench gate deeper. When the gate62is at a positive voltage for turning on the IGTO device, the channel between the N+ region64and the N−-layer26is inverted so that current flows between the control terminal38and the N−-layer26through the diode66. This structure injects electrons into the base (N− layers26/28) of the PNP transistor and, in turn, injects holes into the base of the NPN transistor, which initiates a full turn on of the IGTO device. The N-channel MOSFET60causes the turn on to occur at a repeatable and precise level. The device is shut off by turning on the P-channel MOSFET50(FIG. 5) with a negative gate12voltage. The N-channel MOSFET60may be distributed around the array of cells, such as every tenth cell.

FIG. 5is an equivalent circuit ofFIG. 4showing the N-channel MOSFET60, where turning on the N-channel MOSFET60with a sufficiently positive gate voltage electrically connects the N+ region64to the N−-layer26to start the flow of current between the cathode terminal34and anode terminal36.

The diode66is connected between the control terminal38and the N+ region64to allow current to flow into the N−-layer26when the IGTO device is turned on but blocks any current when the control terminal38is made negative when turning off the IGTO device. The diode66can be integrated on the same chip as the IGTO device or can be external to the chip.

The diode66may be optional if the negative voltage on the control terminal38will not draw significant current through the N+ region64in the IGTO device's off state.FIG. 6is identical toFIG. 4but without the diode66.

Since the turn on of the IGTO device is initiated by the injection of carriers into the N-layer26by the turning on of the N-channel MOSFET60, there is no reason to couple the control terminal38to the P-layer24(the base of the NPN transistor) to forward bias the base-emitter of the NPN transistor46, as shown inFIG. 1.

AlthoughFIGS. 4-6illustrate a 3-terminal device, the control terminal for the two gates12/64can be separate, to form a 4-terminal device, to provide more optimal control over the turn on and turn off of the device. A resistor may be added in series with the diode40(FIG. 1) to create a desired voltage drop between the control terminal voltage and the P+ contact region32when turning on the IGTO device.