HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME

A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode on the p-type semiconductor layer, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. Preferably, the buffer layer further includes a bottom portion having a first carbon concentration and a top portion having a second carbon concentration, in which the second carbon concentration is less than the first carbon concentration and a thickness of the bottom portion is less than a thickness of the top portion.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a high electron mobility transistor (HEMT) and fabrication method thereof.

2. Description of the Prior Art

High electron mobility transistor (HEMT) fabricated from GaN-based materials have various advantages in electrical, mechanical, and chemical aspects of the field. For instance, advantages including wide band gap, high break down voltage, high electron mobility, high elastic modulus, high piezoelectric and piezoresistive coefficients, and chemical inertness. All of these advantages allow GaN-based materials to be used in numerous applications including high intensity light emitting diodes (LEDs), power switching devices, regulators, battery protectors, display panel drivers, and communication devices.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode on the p-type semiconductor layer, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. Preferably, the buffer layer further includes a bottom portion having a first carbon concentration and a top portion having a second carbon concentration, in which the second carbon concentration is less than the first carbon concentration and a thickness of the bottom portion is less than a thickness of the top portion.

According to another aspect of the present invention, a high electron mobility transistor (HEMT) includes a buffer layer on a substrate and a barrier layer on the buffer layer. Preferably, the buffer layer includes a bottom portion having a first carbon concentration and a top portion having a second carbon concentration.

DETAILED DESCRIPTION

Referring toFIGS.1-3,FIGS.1-3illustrate a method for fabricating a HEMT according to an embodiment of the present invention. As shown inFIG.1, a substrate12such as a substrate made from silicon, silicon carbide, or aluminum oxide (or also referred to as sapphire) is provided, in which the substrate12could be a single-layered substrate, a multi-layered substrate, gradient substrate, or combination thereof. According to other embodiment of the present invention, the substrate12could also include a silicon-on-insulator (SOI) substrate.

Next, a selective nucleation layer (not shown), a superlattice stack layer14, and a buffer layer16are formed on the substrate12. According to an embodiment of the present invention, the nucleation layer preferably includes aluminum nitride (AlN), the superlattice stack layer14includes a composite layer made of alternating AlN and AlxGa1-xN, and the buffer layer16is preferably made of III-V semiconductors such as gallium nitride (GaN), in which a thickness of the buffer layer16could be between 0.5 microns to 10 microns. According to an embodiment of the present invention, the formation of the superlattice stack layer14and the buffer layer16on the substrate12could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.

As shown inFIG.2, the buffer layer16from bottom to top includes a bottom portion18, a top portion20, and a channel region22, in which the bottom portion18, the top portion20, and the channel region22are essentially made of GaN while the bottom portion18and the top portion20are doped with higher concentration of carbon atoms whereas the channel region22is doped with lower concentration of carbon atoms or not doped at all (undoped). The thickness of the bottom portion18is also slightly less than the thickness of the top portion20.

It should be noted that the carbon concentration of the bottom portion18is preferably different from or more specifically greater than the carbon concentration of the top portion20and the carbon concentration of the channel region22is less than the carbon concentration of the bottom portion18and the top portion20. Specifically, the bottom portion18includes a first carbon concentration, the top portion20includes a second carbon concentration, and the channel region22includes a third carbon concentration, in which the third carbon concentration of the channel region22is less than the second carbon concentration of the top portion20and the first carbon concentration of the bottom portion18while the second carbon concentration of the top portion20is also less than the first carbon concentration of the bottom portion18. In other words, the first carbon concentration is greater than the second carbon concentration and both the first carbon concentration and second carbon concentration are greater than the third carbon concentration. According to an embodiment of the present invention, the first carbon concentration is between 5.0×1018atoms/cm3to 1.0×1019atoms/cm3, the second carbon concentration is between 1.0×1018atoms/cm3to 4.0×1018atoms/cm3, and the third carbon concentration is between 1.0×1016atoms/cm3to 1.0×1017atoms/cm3.

Next, as shown inFIG.3, a barrier layer24is formed on the surface of the buffer layer16or UID buffer layer. In this embodiment, the barrier layer24is preferably made of III-V semiconductor such as n-type or n-graded aluminum gallium nitride (AlxGa1-xN), in which 0<x<1, the barrier layer24preferably includes an epitaxial layer formed through epitaxial growth process, and the barrier layer24could include dopants such as silicon or germanium. Similar to the buffer layer16, the formation of the barrier layer24could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.

Next, a p-type semiconductor layer26is formed on the barrier layer24, a passivation layer28is formed on the barrier layer24and the p-type semiconductor layer26, a gate electrode is formed on the p-type semiconductor layer26, and a source electrode32and a drain electrode34are formed adjacent to two sides of the gate electrode30, in which the p-type semiconductor layer26and the gate electrode30could constitute a gate structure altogether. In this embodiment, the p-type semiconductor layer26is a III-V compound semiconductor layer preferably including p-type GaN (pGaN) and the formation of the p-type semiconductor layer26on the barrier layer24could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.

According to an embodiment of the present invention, it would be desirable to first form a p-type semiconductor layer26on the barrier layer24and then conduct a photo-etching process to remove part of the p-type semiconductor layer26for forming a patterned p-type semiconductor layer26. After depositing a passivation layer28on the patterned p-type semiconductor layer26and the barrier layer24, a photo-etching process could be conducted to remove part of the passivation layer28for forming a recess (not shown), a gate electrode30is formed in the recess directly on the p-type semiconductor layer26, another photo-etching process is conducted to remove part of the passivation layer28adjacent to two sides of the p-type semiconductor layer26for forming additional recesses (not shown), and then a source electrode32and a drain electrode34are formed in the recesses adjacent to two sides of the gate electrode30.

In this embodiment, the gate electrode30, the source electrode32, and the drain electrode34are preferably made of metal, in which the gate electrode30is preferably made of Schottky metal while the source electrode32and the drain electrode34are preferably made of ohmic contact metals. According to an embodiment of the present invention, each of the gate electrode30, source electrode32, and drain electrode34could include gold (Au), Silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), palladium (Pd), or combination thereof. Preferably, it would be desirable to conduct an electroplating process, sputtering process, resistance heating evaporation process, electron beam evaporation process, physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, or combination thereof to form electrode materials in the aforementioned openings, and then pattern the electrode materials through one or more etching processes to form the gate electrode30, source electrode32, and the drain electrode34. This completes the fabrication of a HEMT according to an embodiment of the present invention.

Typically, a heterojunction is formed at the interface between the buffer layer16and barrier layer24as a result of the bandgap difference between the two layers. Essentially a quantum well is formed in the banding portion of the conduction band of the heterojunction to constrain the electrons generated by piezoelectricity so that a channel region or two-dimensional electron gas (2DEG) is formed at the junction between the buffer layer and barrier layer to form conductive current.

However in current design of the buffer layer, the corresponding top portion such as the top portion20of the buffer layer is also made of GaN doped with carbon atoms while the bottom portion18of the buffer layer is made of undoped GaN or GaN having no dopants whatsoever. Since the GaN buffer layer having no dopants typically has lower potential well, electrons in the channel region are more likely to be injected into deeper or bottom portion18of the buffer layer to initiate a discharge effect thereby lowering 2DEG and increasing resistance.

To resolve this issue the present adjusts the carbon concentrations of the bottom portion18and top portion20of the buffer layer so that the carbon concentration of the bottom portion18is slightly higher than the carbon concentration of the top portion20. By creating a step-profile increase of carbon concentration from the top portion20to the bottom portion18, it would be desirable to inhibit the formation of potential well and prevent carriers from entering the lower level or bottom portion20of the buffer layer thereby lowering discharge of the device.