Real time reconfigurable logic device and semiconductor package having the same

According to example embodiments, a logic device includes a first functional block configured to perform a first operation according to first operation information and a second operation according to second operation information, and a second functional block configured to perform a third operation according to the first operation information and a fourth operation according to the second operation information. The first functional block is configured to receive configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the first or second operation based on the selected first or second operation information. The second functional block is configured to receive the configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the third or fourth operation based on the selected first or second operation information.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2011-0062480, filed on Jun. 27, 2011, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Example embodiments relate to a logic device and a semiconductor package including the same, and more particularly, to a logic device that is reconfigurable in real time by using a non-volatile memory device.

2. Description of the Related Art

Recently, the use of reconfigurable logic devices, e.g., a programmable logic device (PLD) that can be easily and arbitrarily designed by a user, has become widespread. A user may reconfigure a logic device to perform a desired operation by controlling signal routings among interconnection lines included in the logic device.

SUMMARY

Example embodiments relate to a logic device that is reconfigurable quickly and a semiconductor package including the same.

According to example embodiments, a logic device includes a first functional block and a second functional block. The first functional block is configured to perform a first operation according to first operation information and to perform a second operation according to second operation information. The first functional block is configured to receive configuration information and select one of the first operation information and the second operation information based on the configuration information, and to perform the one of the first and the second operation based on the selected one of the first and second operation information. The second functional block is configured to perform a third operation according to the first operation information and to perform a fourth operation according to the second operation information. The second functional block is configured to receive the configuration information and to select one of the first operation information and the second operation information based on the configuration information, and to perform the one of the third and fourth operation based on the selected one of the first and second operation information.

The first functional block may be configured to receive a first input signal containing the configuration information, and to generate a first output signal according to the one of the first operation and the second operation.

The first functional block may include a plurality of first storage devices. The first functional block may be configured to perform first operation using a part of the plurality of first storage devices, and the first functional block may be configured to perform the second operation using a second part of the plurality of first storage devices.

The second functional block may be configured to receive a second input signal containing the configuration information, generate a second output signal according to the one of the third operation and the fourth operation. The second functional block may include a plurality of second storage devices. The second functional block may be configured to perform the third operation using a first part of the plurality of second storage devices, and to perform the fourth operation using a second part of the plurality of second storage devices.

Each of the plurality of first storage devices may include a plurality of reconfigurable non-volatile memory devices.

The plurality of reconfigurable non-volatile memory devices may be arranged in an array.

The logic device may further include an interconnection unit configured to connect the first functional block and the second functional block based on a plurality of pieces of interconnection information. The interconnection unit may be configured to receive the configuration information, select one piece of interconnection information from among the plurality of pieces of interconnection information, and to connect the first functional block and the second functional block based on the selected interconnection information.

The interconnection unit may include a switch device configured to connect the first functional block and the second functional block according to a control signal, and a configuration unit configured to generate the control signal.

The configuration unit may include a plurality of third storage devices configured to store the plurality of pieces of interconnection information. The plurality of third storage devices may include a plurality of non-volatile memory devices.

The configuration unit may further include a selector connected to the plurality of third storage devices. The selector may be configured to select one of the plurality of third storage devices based on the configuration information so as to read the plurality of pieces of interconnection information.

The configuration unit may further include a latch configured to read the plurality of pieces of interconnection information from the plurality of third storage devices and to store the read interconnection information of the plurality of pieces of interconnection information.

The latch may include a first inverter including a first pull-up transistor connected to a power supply voltage terminal and a first pull-down transistor connected in series to the first pull-up transistor; a second inverter including a second pull-up transistor connected to the power supply voltage terminal and a second pull-down transistor connected in series to the second pull-up transistor, wherein the second inverter and the first inverter are cross-linked to each other; and an equalizer configured to connect a gate of the first pull-down transistor and a gate of the second pull-down transistor, based on an enable bar signal.

A control terminal of the switch device may be connected to a node between the first pull-up transistor and the first pull-down transistor.

The plurality of third storage devices may be connected between a source of the first pull-down transistor and a ground voltage terminal.

The configuration unit may further include a bias transistor connected between a source of the second pull-down transistor and the ground voltage terminal.

According to example embodiments, a semiconductor package includes a semiconductor chip containing the foregoing logic device and a printed circuit board (PCB) on which the semiconductor chip is mounted.

The PCB may include an external terminal configured to receive the configuration information.

The logic device may be one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), and a generic array logic (GAL).

According to example embodiments, a logic device includes a plurality of logic blocks. Each of the plurality of logic blocks include a plurality of functional blocks. Each of the functional blocks is configured to perform a plurality of operations according to a plurality of pieces of operation information. Each of the functional blocks is configured to receive configuration information, select a piece of operation information from among the plurality of pieces of operation information based on the configuration information, and to perform one of the plurality of operations based on the selected operation information.

Each of the plurality of logic blocks may include at least one interconnection unit configured to connect the plurality of functional blocks based on a plurality of pieces of interconnection information. The interconnection unit may be configured to receive the configuration information, to select a piece of interconnection information from among the plurality of pieces of interconnection information based on the configuration information, and to connect the plurality of functional blocks based on the selected interconnection information.

The interconnection unit may include a first switch device and a first configuration unit. The first configuration unit may include a plurality of storage devices configured to store the plurality of pieces of interconnection information, and a selector connected to the plurality of storage devices. The selector may be configured to select one of the plurality of storage devices based on the configuration information to read the plurality of pieces of interconnection information.

The logic device may further include a connection block including a plurality of connection units configured to connect the plurality of logic blocks, based on a plurality of pieces of connection information. Each of the plurality of connection units may be configured to receive the configuration information, to select one piece of connection information from among the plurality of pieces of connection information based on the configuration information, and to connect the plurality of logic blocks based on the selected connection information.

Each of the plurality of connection units may include a second switch device and a second configuration unit. The second configuration unit may include a plurality of storage devices configured to store the plurality of pieces of connection information, and a selector connected to the plurality of storage devices. The selector may be configured to select one of the plurality of storage devices based on the configuration information to read the plurality of pieces of connection information.

The logic device may further include a plurality of connection blocks configured to connect the plurality of logic blocks, and a routing block including a plurality of routing units configured to connect the plurality of connection blocks based on a plurality of pieces of routing information. Each of the plurality of routing units may be configured to receive the configuration information, to select a piece of routing information from among the plurality of pieces of routing information based on the configuration information, and to connect the plurality of connection blocks based on the selected routing information.

Each of the plurality of routing units may include a first transmission unit configured to transmit a signal in a direction from a first terminal to a second terminal, and a second transmission unit configured to transmit a signal in a direction from the second terminal to the first terminal.

Each of the first transmission unit and the second transmission unit may include a third configuration unit. The third configuration unit may include a plurality of storage devices configured to store the plurality of pieces of routing information, and a selector connected to the plurality of storage devices. The selector may be configured to select one of the plurality of storage devices based on the configuration information to read the plurality of pieces of routing information.

According to example embodiments, a semiconductor package includes a semiconductor chip including a logic device; and a printed circuit board (PCB) on which the semiconductor chip is mounted. The logic device includes a connection block including a connection unit configured to connect a plurality of logic blocks based on a plurality of pieces of connection information. The connection unit is configured to receive configuration information, to select a piece of connection information from among the plurality of pieces of connection information based on the configuration information, and to connect the plurality of logic blocks based on the selected connection information.

According to example embodiments, a logic device includes at least one logic block that includes a first functional block adjacent to a second functional block. The first and second functional blocks are configured to store data in a storage device, to receive an input signal containing configuration information, perform at least one operation using a part of the storage device, the at least one operation selected from a plurality of operations based on the configuration information, and generate an output signal according to the last one operation performed.

The input signal may further include external information. The first and second functional blocks may each be configured to select the part of the storage device used to perform at least one operation based on the configuration information, and the first and second functional blocks are each configured to access a portion of data in the selected part of the storage device, the portion of data being selected based on the external information contained in the input signal. The first and second functional blocks are each configured to output the portion of data accessed as the output signal.

At least one of the first and second functional blocks are configured to receive the input signal as an 8-bit signal containing the configuration information as a 2-bit signal, and to perform one of a ECC operation, an ALU operation, a compression operation, and a security operation in response to the 2-bit signal of configuration information.

The storage device of the at least one of the first and second functional blocks may include a plurality of reconfigurable non-volatile memory devices separated into first to fourth groups. The at least one of the first and second functional blocks may be configured to use the first group for performing the ECC operation, the second group for performing the ALU operation, the third group for performing the compression operation, and the fourth group for performing the security operation.

The first and second functional blocks may be each configured to receive the input signal containing the configuration information as a 1-bit signal, and to perform two operations in response to the 1-bit signal of configuration information.

Each logic may further include an interconnection unit that is configured to connect the first and second functional blocks based on a plurality of pieces of interconnection information. The interconnection unit may be configured to receive the configuration information, to select one piece of interconnection information from among the plurality of pieces of interconnection information, and to connect the first and second functional blocks based on the selected piece of interconnection information.

The logic device may include a plurality of the logic blocks, and further include a plurality of connection blocks including a plurality of connection units configured to connect the plurality of logic blocks, based on a plurality of pieces of connection information. Each of the plurality of plurality of connection units may be configured to receive the configuration information, to select one piece of connection information from among the plurality of pieces of connection information based on the configuration information, and to connect the plurality of logic blocks based on the selected connection information.

The logic device may include at least one routing block including a plurality of routing units configured to connect the plurality of connection blocks based on a plurality of pieces of routing information. Each of the plurality of routing units may be configured to receive the configuration information, to select a piece of routing information from among the plurality of pieces of routing information based on the configuration information, and to connect the plurality of connection blocks based on the selected routing information.

According to example embodiments, a semiconductor chip may include the foregoing logic device and at least one external terminal connected to the semiconductor chip and configured to receive the input signal containing configuration information.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown, wherein like reference numerals refer to like elements throughout. Example embodiments, may however, be embodiments in many forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of example embodiments to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus their description may be omitted.

FIG. 1is a schematic block diagram of an electronic circuit module1including a general logic device10and an external memory device15. Referring toFIG. 1, the electronic circuit module1may include the logic device10having a plurality of logic blocks11,12,13, and14, and the external memory device15. The logic device10is a programmable logic device (PLD), e.g., a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), or a generic array logic (GAL). The external memory device15stores connection information regarding interconnections lines between the plurality of logic blocks11to14included in the logic device10. The external memory device15may be, for example, flash memory or read-only memory (ROM).

When power is supplied to the electronic circuit module1, the connection information stored in the external memory device15is loaded into the logic device10. The plurality of logic blocks11to14are connected to one another based on the connection information. An operation of the logic device10is defined according to a connection between the plurality of logic blocks11to14. Thus, in order to define an operation of the logic device10, the connection information regarding the interconnection lines between the plurality of logic blocks11to14should be programmed, the programmed connection information should be stored in the external memory device15, and the stored connection information should be loaded into the logic device10. Thus, reconfiguring the logic device10in real time may be limited. Also, in order to operate the logic device10, the external memory device15should be included in the logic device10, which increases the size of the electronic circuit module1and manufacturing costs thereof.

FIG. 2is a schematic block diagram of an electronic circuit module2including a logic device20according to example embodiments. Referring toFIG. 2, the electronic circuit module2may include a logic device20having a plurality of logic blocks21,22,23, and24. The logic device20may include a plurality of non-volatile memory devices (not shown). The plurality of non-volatile memory devices may be respectively disposed in regions where interconnection lines between the plurality of logic blocks21to24intersect one another or in regions where interconnection lines between a plurality of functional blocks (not shown) included in each of the plurality of logic blocks21to24intersect one another. Routing may be controlled between the interconnection lines between the plurality of logic blocks21to24or between the interconnection lines between the plurality of functional blocks included in each of the plurality of logic blocks21to24by writing, e.g., programming, data regarding the plurality of non-volatile memory devices, e.g., interconnection information, connection information, and routing information.

As described above, since the logic device20includes the plurality of non-volatile memory devices, the electronic circuit module2does not need an external memory device, unlike in the electronic circuit module1. Thus, in order to redefine an operation of the logic device20, e.g., in order to reconfigure the operation of the logic device20, the connection information regarding the interconnection lines between the plurality of logic blocks21to24or between the plurality of functional blocks included in each of the plurality of logic blocks21to24may be programmed in the plurality of non-volatile memory devices in real time and the plurality of logic blocks21to24or the functional blocks included in each of the plurality of logic blocks21to24may be connected to one another based on the programmed connection information. Accordingly, the logic device20may be more easily reconfigured in real time, and may not include an external memory device, thereby reducing the size of the electronic circuit module2.

FIGS. 3 and 4are schematic block diagrams respectively illustrating functional blocks30and30aincluded in a logic device (not shown), according to example embodiments. The logic device may include a plurality of logic blocks, each of which may have a plurality of functional blocks30. Here, the functional block30may be defined as a block that may be transformed from one data format to another data format.

More specifically, the functional block30may include a plurality of storage units (not shown), and may store all possible output signals related to an input signal in the plurality of storage units in the form of a table. The functional block30may perform an operation based on such information stored in the form of a table. For example, the functional block30may receive an input signal and access and output information stored in the form of a table according to the input signal. The functional block30may be embodied as an Intellectual Property (IP) block or a Look-Up Table (LUT) block. It is assumed inFIGS. 3 and 4that the functional blocks30and30aare LUT blocks.

Referring toFIG. 3, the functional block30may receive an input signal containing configuration information and may perform various operations based on the configuration information. In general, a functional block receives an input signal for performing one operation and outputs information accessed according to the input signal, as an output signal. However, it should be noted that the functional block30may receive an input signal for performing various operations, e.g., an input signal containing configuration information.

In other words, in the functional block30according to example embodiments (or a logic device including the functional block30), each storage unit is divided into a configuration area and a data area. The functional block30receives the input signal containing the configuration information, accesses only the data region according to the configuration information, and outputs a result of the accessing as an output signal. Thus, according to example embodiments, the functional block30may perform various operations. For example, if the configuration information is a 2-bit signal, operation information may be defined as indicated in Table 1.

Referring to Table 1, the functional block30may perform an operation according to first operation information, e.g., ECC, an operation according to second operation information, e.g., an ALU, an operation according to third operation information, e.g., compression, and an operation according to fourth operation information, e.g., security.

In this case, the functional block30may receive configuration information, select one of the first to fourth operation information, and perform the operation corresponding to the selected operation information. Although not shown, the functional block30may include a plurality of storage devices, and the operations corresponding to the first to fourth operation information may be performed using the plurality of storage devices.

For example, if configuration information contained in an input signal is ‘00’, data stored in a first 6-bit LUT F0may be accessed from among four 6-bit LUTs F0, F1, F2, and F3. Thus, the functional block30may perform the operation corresponding to the first operation information, e.g., the ECC. This operation may be performed based on a first part of the plurality of storage devices.

If the configuration information contained in the input signal is ‘01’, data stored in the second 6-bit LUT F1may be accessed from among the four 6-bit LUTs F0, F1, F2, and F3. Thus, the functional block30may perform the operation corresponding to the second operation information, e.g., the ALU. This operation may be performed based on a second part of the plurality of storage devices.

If the configuration information contained in the input signal is ‘10’, data stored in the third 6-bit LUT F2may be accessed from among the four 6-bit LUTs F0, F1, F2, and F3. Thus, the functional block30may perform the operation corresponding to the third operation information, e.g., compression. This operation may be performed based on a third part of the plurality of storage devices.

If the configuration information contained in the input signal is ‘11’, data stored in the fourth 6-bit LUT F3may be accessed from among four 6-bit LUTs F0, F1, F2, and F3. Thus, the functional block30may perform the operation corresponding to the fourth operation information, e.g., security. This operation may be performed based on a fourth part of the plurality of storage devices.

According to example embodiments, the functional block30may receive a first input signal containing configuration information and external information, and may generate an output signal according to an operation selected from among a plurality of operations. Even if a general functional block and a general logic device are reconfigurable, the general functional block should be individually reconfigured to perform various operations, and such a reconfiguration needs a large amount of time. However, according to example embodiments, a functional block30and a logic device including the functional block30according to example embodiments may be set to perform various operations according to configuration information without having to be additionally reconfigured. Thus, the functional block30according to example embodiments may perform various operations within a shorter time compared to the general functional block.

One such operation of the functional block30may be illustrated as in the block diagram of the functional block30ainFIG. 4. First, data stored in four 6-bit LUTs F0, F1, F2, and F3are accessed based on external information contained in an input signal, and only data selected from among the accessed data stored in the four 6-bit LUTs F0to F3by a multiplexer that receives configuration information is output as an output signal. It will be apparent to those of ordinary skill in the art that althoughFIGS. 3 and 4illustrate operations of a functional block differently, e.g., in a different sequence, a result of performing the operations is the same.

FIG. 5is a schematic block diagram of a functional block30bincluded in a logic device, according to example embodiments. As described with reference toFIG. 3, the functional block30bmay include a plurality of storage devices (not shown). The plurality of storage devices may include, e.g., reconfigurable non-volatile memory devices.

FIG. 5illustrates the functional block30bincluding non-volatile memory devices35arranged in an array, according to example embodiments. The non-volatile memory devices35store data based on operation information (see Table 1). The stored data may be accessed according to an input signal and be output as an output signal. In this case, the input signal may be used as a type of address signal.

The input signal may include not only an external signal for performing an operation but also configuration information for selecting an operation from among a plurality of operations. For example, if the input signal is an 8-bit signal, first two bits of the 8-bit signal may include configuration information and the other six bits of the 8-bit input signal may include external information. In this case, the total number of non-volatile memory devices may be 256 and may be accessed according to the 8-bit input signal.

Referring toFIG. 3, the non-volatile memory devices may be divided into four parts, each of which may include 64 memory devices, e.g., a 6-bit LUT. For example, from among the four parts, a first part may be non-volatile memory devices for performing an operation related to an ECC, a second part may be non-volatile memory devices for performing an operation related to an ALU, a third part may be non-volatile memory devices for performing an operation related to compression, and a fourth part may be non-volatile memory devices for performing an operation related to security.

In this case, some of the first to fourth parts may be selected based on 2-bit configuration information, and data stored in the selected part may be output as an output signal according to 6-bit external information. Such an operation may be performed using a decoder that receives an input signal containing configuration information and external information and accesses data stored in a non-volatile memory device. As shown inFIG. 5, the decoder may be connected to rows of nonvolatile memory devices35through wordlines WL and the decoder may be connected to columns of nonvolatile memory devices35through bitlines. Reference characters CS indicate a common source CS. The common source CS may be a ground to which a reference voltage is provided.

While example embodiments have been described with respect to the functional block30bincluding a plurality of non-volatile memory devices, but example embodiments are not limited thereto. According to example embodiments, various operations may be performed by storing operations corresponding to a plurality of pieces of operation information in the functional block30b, receiving configuration information, and accessing data according to the configuration information from among the stored operation information. It will be apparent to those of ordinary skill in the art that the functional block30bmay include, for example, a plurality of static random access memories (SRAMs) instead of a plurality of non-volatile memory devices.

FIG. 6is a schematic block diagram of a logic block50included in a logic device, according to example embodiments. A description ofFIG. 6, which is the same as that ofFIG. 3, will not be provided again here.

Referring toFIG. 6, the logic block50in the logic device may include a first functional block30-1and a second functional block30-2.

The first functional block30-1may perform a first operation according to first operation information and a second operation according to second operation information. The first or second operation information may be selected by receiving configuration information, and the first or second operation may be performed based on the selected operation information.

More specifically, the first functional block30-1receives a first input signal containing configuration information and first external information. Although not shown, the first input signal may further contain information regarding an output signal of another functional block (not shown). Whether the first input signal contains information regarding an output signal of another functional block (not shown) may be determined based on a connection between interconnection units.

The first functional block30-1may include a plurality of first storage devices35as in the functional block ofFIG. 5. The plurality of first storage devices may be accessed according to the first input signal. If the configuration information is a 1-bit signal, the first functional block30-1may perform two operations, e.g., the first and second operations. In this case, the first operation may be performed using some of the plurality of first storage devices and the second operation may be performed using the other first storage devices. The first functional block30-1may output a first output signal as a result of performing the first or second operation.

The second functional block30-2may perform a third operation according to the first operation information and a fourth operation according to the second operation information. The first or second operation information may be selected by receiving configuration information, and the third or fourth operation may be performed based on the selected operation information, e.g., first operation information or second operation information.

More specifically, the second functional block30-2receives a second input signal containing configuration information and second external information. Optionally, the second input signal may further contain information regarding the first output signal. Whether the second input signal contains the information regarding the first output signal may be determined based on a connection between interconnection units. This will be described in detail with reference toFIG. 8later.

The second functional block30-2may include a plurality of second storage devices (not shown) as in the functional block ofFIG. 5. The plurality of second storage devices may be accessed according to the second input signal. If the configuration information is a 1-bit signal, the second functional block30-2may perform two operations, e.g., the third and fourth operations. In this case, the third operation may be performed using some of the plurality of second storage devices and the fourth operation may be performed using the other second storage devices. The second functional block30-2may output a second output signal as a result of performing the third or fourth operation.

FIG. 7is a schematic cross-sectional view of a semiconductor package1000according to example embodiments. The semiconductor package1000may be a modified example of the logic device ofFIG. 6, and thus, a description of the features ofFIG. 7that are the same as that ofFIG. 6will not be provided again here.

Referring toFIG. 7, the semiconductor package1000may include a semiconductor chip1100and a printed circuit board (PCB)1200.

In the semiconductor chip1100, a logic device (not shown) may be included. For example, the logic device may be as described above with reference toFIGS. 2 to 6.

The semiconductor chip1100may be mounted on the PCB1200. The PCB1200may include external terminals1250, such as solder balls. In particular, the external terminals1250may receive configuration information. The configuration information received via the external terminals1250may be transmitted to the logic device in the semiconductor chip1100via an internal interconnection unit1270and a wire1280.

If the semiconductor chip1100or the semiconductor package1000includes a general logic unit, the external terminals1250that receives configuration information are not mounted thereon. A logic device, a semiconductor chip1100, and a semiconductor package1000according to example embodiments may receive configuration information via the external terminals1250and may perform various operations based on the configuration information. Thus, it will be apparent to those of ordinary skill in the art that if the external terminals1250that receive configuration information for setting various operations are included in a product's specifications, it may be considered a semiconductor package according example embodiments.

FIG. 8is a schematic block diagram of a logic block50aincluded in a logic device, according to example embodiments. The description ofFIG. 8will only focus on the differences betweenFIG. 8andFIG. 6.

Referring toFIG. 8, the logic block50amay further include an interconnection unit70for connecting a first functional block30-1and a second functional block30-2.

The interconnection unit70may receive configuration information and select one from among a plurality of pieces of interconnection information. The interconnection unit70may connect first functional block30-1and the second functional block30-2, based on the selected interconnection information. Here, interconnection information may be determined by an operation of the logic device.

The interconnection unit70may include a switch device73and a configuration unit75so as to connect the first functional block30-1and the second functional block30-2based on the selected interconnection information.

The switch device73connects the first functional block30-1and the second functional block30-2according to a control signal, and may be embodied as, for example, an N-type transistor. If the switch device73is the N-type transistor, a gate of the N-type transistor may function as a control terminal for determining whether the first functional block30-1and the second functional block30-2are to be connected to each other.

The configuration unit75may store the interconnection information and may generate the control signal based on the interconnection information. The structure of the configuration unit75will be described in detail with reference toFIG. 9.

FIG. 9is a circuit diagram of a logic block50bin which a non-limiting example of an interconnection block70is illustrated. Referring toFIG. 9, a configuration unit75may include a plurality of third storage devices110, a selector120, a latch130, a first write transistor WTR1, a second write transistor WTR2, and a bias transistor BTR.

Each of the plurality of third storage devices110may store interconnection information and may include, for example, a non-volatile memory device. If the logic device performs, for example, four operations corresponding to an ECC, an ALU, compression, and security (see Table 1), the plurality of third storage devices110may include four non-volatile memory devices. During a read operation, the plurality of third storage devices110may be connected between a source of a first pull-down transistor PDTR1and a ground voltage VSS terminal.

The selector120may be connected to the plurality third storage devices110and may select one from among the plurality of third storage devices110. To this end, the selector120may include a plurality of selection transistors STR and a decoder. The plurality of selection transistors STR may be respectively connected to the plurality of third storage devices110, and may respectively receive selection signals CF<0>, CF<1>, CF<2>, and CF<3> decoded by the decoder plurality third storage devices110so as to connect one of the plurality third storage devices110to the ground voltage VSS terminal.

In the read mode, one of the plurality of third storage devices110may be selected by the selector120based on configuration information, and interconnection information may be read by the selected third storage device110. In a write mode, one of the plurality of third storage devices110may be selected by the selector120based on the configuration information, and the interconnection information may be written by the selected third storage device110. Operations of the selector120in the read mode and the write mode will be described in detail with reference toFIGS. 10 to 13later.

The latch130may read interconnection information from the plurality of third storage devices110and store the read interconnection information therein. The latch130may include a first inverter INV1and a second inverter INV2.

The first inverter INV1may include a first pull-up transistor PUTR1connected to a power supply voltage VDD terminal, and a first pull-down transistor PDTR1connected in series to the first pull-up transistor PUTR1. More specifically, the first pull-up transistor PUTR1may be a P-type transistor having a source connected to the power supply voltage VDD terminal, a drain connected to a first node N1, and a gate connected to a second node N2. The first pull-down transistor PDTR1may be an N-type transistor having a source connected to the plurality of third storage devices110, a drain connected to the first node N1, and a gate connected to the second node N2. Here, a control terminal, e.g., a gate, of the switch device73may be connected to a node, e.g., the first node N1, between the first pull-up transistor PUTR1and the first pull-down transistor PDTR1.

The second inverter INV2may include a second pull-up transistor PUTR2connected to the power supply voltage VDD terminal, and a second pull-down transistor PDTR2connected in series to the second pull-up transistor PUTR2. More specifically, the second pull-up transistor PUTR2may be a P-type transistor having a source connected to the power supply voltage VDD terminal, a drain connected to the second node N2, and a gate connected to the first node N1. The second pull-down transistor PDTR2may be an N-type transistor having a source connected to the bias transistor BTR, a drain connected to the second node N2, and a gate connected to the first node N1.

The first inverter INV1and the second inverter INV2may be cross-linked to each other by connecting the gates of the first pull-up transistor PUTR1and the first pull-down transistor PDTR1to the second node N2and connecting the gates of the second pull-up transistor PUTR2and the second pull-down transistor PDTR2to the first node N1, thereby manufacturing the latch130.

Optionally, the latch130may further include an equalizer EQ. The equalizer EQ may connect the gate of the first pull-down transistor PDTR1and the gate of the second pull-down transistor PDTR2, based on an enable bar signal nEN. More specifically, the equalizer EQ may be an N-type transistor having a source connected to the gate of the first pull-down transistor PDTR1, a drain connected to the gate of the second pull-down transistor PDTR2, and a gate via which the enable bar signal nEN is received.

The first write transistor WTR1may be connected to one end of the third storage device110, and the second write transistor WTR2may be connected to another end of the third storage device110. In the write mode, if a write signal WS is supplied to the first and second write transistors WTR1and WTR2, the first and second write transistors WTR1and WTR2may be turned on to write interconnection information received via a data line Din and interconnection information received via a data line nDin to the third storage device110.

The bias transistor BTR may provide a reference resistance value while interconnection information is read from one of the plurality of third storage devices110. For example, if a resistance value stored in the third storage device110is 1 kΩ when the interconnection information denotes a disconnection state, e.g., ‘0’, and is 1 MΩ when the interconnection information denotes a connection state, e.g., ‘1’, then the bias transistor BTR may be set to have a resistance value of 50 kΩ. During the read mode, the bias transistor BTR may be connected to the source of the second pull-down transistor PDTR2and the ground voltage VSS terminal. Although the bias transistor BTR, which is an active device, is illustrated inFIG. 9, a resistance device, which is a passive device, may be used to provide the reference resistance value.

AlthoughFIG. 9has been described with respect to the plurality of third storage devices110including a plurality of non-volatile memory devices, example embodiments are not limited thereto. According to example embodiments, various operations may be performed using the first and second functional blocks30-1and30-2by storing a plurality of pieces of interconnection information corresponding to a plurality of pieces of operation information in the plurality of third storage devices110, receiving configuration information, and accessing the interconnection information according to the configuration information from among the stored operation information. It will be apparent to those of ordinary skill in the art that the plurality of third storage devices110may include, for example, a plurality of SRAMs instead of a plurality of non-volatile memory devices.

FIG. 10is a circuit diagram illustrating a case where the interconnection unit70ofFIG. 9is in a read mode, according to example embodiments.FIG. 11is a timing diagram of signals used in the read mode, according to example embodiments.

Referring toFIGS. 10 and 11, in the read mode, an enable signal EN is deactivated to ‘0’ and an enable bar signal nEN is activated to ‘1’. A write signal WS is deactivated to ‘0’.

If the enable bar signal nEN is activated to ‘1’, the equalizer EQ may be turned on and the gate of the first pull-down transistor PDTR1may be connected to the gate of the second pull-down transistor PDTR2. Thus, the gates of the first pull-down transistor PDTR1and the second pull-down transistor PDTR2are equal to each other, and both the first pull-down transistor PDTR1and the second pull-down transistor PDTR2are thus turned on.

The selection transistor STR may be turned on according to a selection signal, e.g., the selection signal CF<0>, which is decoded based on configuration information before the equalizer EQ is turned on. If the selection transistor STR is turned on, then a voltage corresponding to a resistance value of the third storage device110is applied to the source of the first pull-down transistor PDTR1. For example, when the third storage device110is in a high resistance state denoting a connection state, the third storage device110has a higher resistance value than that of the bias transistor BTR and a high voltage is applied to the source of the first pull-down transistor PDTR1. Since the resistance value of the bias transistor BTR is relatively low, a low voltage is applied to the source of the second pull-down transistor PDTR2.

Then, when the equalizer EQ is turned on, voltages of the first node N1and the second node N2become the same. Next, when the enable signal EN is activated to ‘1’ and the enable bar signal nEN is deactivated to ‘0’, the high voltage applied to the source of the first pull-down transistor PDTR1is transferred to the first node N1, and the low voltage applied to the source of the second pull-down transistor PDTR2is transferred to the second node N2. That is, since the resistance value of the third storage device110connected to the ground voltage VSS terminal is greater than that of the bias transistor BTR connected to the ground voltage VSS terminal, the second node N2is connected to the ground voltage VSS terminal and the voltages of the second node N2and the first node N1thus respectively become ‘0’ and ‘1’. Thus, a voltage of ‘1’ is applied to the control terminal of the switch device connected to the first node N1, the switch device73is turned on, and the first functional block30-1and the second functional block30-2are connected to each other.

If the third storage device110is in a low resistance state denoting a disconnection state, the third storage device110has a lower resistance value than that of the bias transistor BTR and a low voltage is thus applied to the source of the first pull-down transistor PDTR1. Since the bias transistor BTR has a relatively high resistance value, a high voltage is applied to the source of the second pull-down transistor PDTR2.

Then, when the equalizer EQ is turned on, voltages of the first node N1and the second node N2become the same. Next, when the enable signal EN is activated to ‘1’ and the enable bar signal nEN is deactivated to ‘0’, the low voltage applied to the source of the first pull-down transistor PDTR1is transferred to the first node N1and the high voltage applied to the source of the second pull-down transistor PDTR2is transferred to the second node N2. Thus, a voltage of ‘0’ is applied to the control terminal of the switch device connected to the first node N1, the switch device73is turned off, and the first functional block30-1and the second functional block30-2are not connected to each other.

FIG. 12is a circuit diagram illustrating a case where the interconnection unit70ofFIG. 9is in a write mode, according to example embodiments.FIG. 13is a timing diagram of signals used in the write mode, according to example embodiments.

Referring toFIGS. 12 and 13, in the write mode, an enable signal EN is deactivated to ‘0’ and an enable bar signal nEN is activated to ‘1’. Also, a write signal WS is activated to ‘1’.

The selection transistor STR may be turned on according to a selection signal, e.g., a selection signal CF<0> decoded based on configuration information. If the selection transistor STR is turned on, one of the plurality of third storage devices110is selected and the selected third storage device110is ready to write interconnection information.

Then, interconnection information received via the data lines Din and nDin is written to the selected third storage device110. If the first functional block30-1and the second functional block30-2need to be connected to each other while a logic device that performs, for example, four operations corresponding to an ECC, an ALU, compression, and security (see Table 1), performs the operation corresponding to the ECC, then interconnection information, e.g., a signal activated to ‘1’, for allowing the third storage device110to be in a high resistance state may be written to the third storage device110selected according to the selection signal CF<0>.

FIG. 14is a schematic block diagram of a logic device according to example embodiments. Referring toFIG. 14, the logic device may include a plurality of logic blocks50-1and50-2, an interconnection unit70, and a connection block100.

The logic block50-1may include a plurality of functional blocks30-1and30-2, and the logic block50-2may include a plurality of functional blocks30-3and30-4.

Each of the functional blocks30-1to30-4may perform a plurality of operations according to a plurality of pieces of operation information. Each of the functional blocks30-1to30-4may receive configuration information, select one of the plurality of pieces of operation information, and perform one of the plurality of operations based on the selected operation information, as described above with reference toFIGS. 2 to 7.

The interconnection unit70may connect either the functional blocks30-1and30-2or the functional blocks30-3and30-4, based on a plurality of pieces of interconnection information. Specifically, as described above with reference toFIGS. 8 and 9, the interconnection unit70may receive configuration information, select one of the plurality of pieces of interconnection information based on the configuration information, and may connect either the functional blocks30-1and30-2or the functional blocks30-3and30-4, based on the selected interconnection information. To this end, the interconnection unit70may include a first switch device73and a first configuration unit75.

The connection block100may include a plurality of connection units90, and the plurality of connection units90may connect the plurality of logic blocks50-1and50-2based on a plurality of pieces of pieces connection information. The plurality of connection units90may receive the plurality of pieces of configuration information, select one of the plurality of pieces of connection information, and connect the plurality of logic blocks50-1and50-2based on the selected connection information. The plurality of connection units90may have substantially the same circuit construction as the interconnection unit70. For example, each of the plurality of connection units90may include a second switch device93and a second configuration unit95.

The interconnection unit70may connect either the functional blocks30-1and30-2included in the first logic block50-1or the functional blocks30-3and30-4included in the second logic block50-2, whereas the plurality of connection units90may connect the plurality of logic blocks50-1and50-2.

FIG. 15is a schematic block diagram of a logic device according to example embodiments. The logic device ofFIG. 15may be a modified example of the logic device ofFIG. 14, and thus, a description of the embodiment ofFIG. 15that is the same as that of the embodiment ofFIG. 14will not be provided again here.

Referring toFIG. 15, the logic device may include a plurality of logic blocks50, a plurality of connection blocks100, a plurality of routing blocks150, and a plurality of input/output (I/O) terminals.

The plurality of logic blocks50may be arranged in a matrix. The plurality of connection blocks100may be disposed between adjacent logic blocks50arranged in a matrix to connect the plurality of logic blocks50. Each of the plurality of connection blocks100may include the plurality of connection units90ofFIG. 14, and each of the plurality of connection units90may include the second switch device73and the second configuration unit75ofFIG. 14, as described above with reference toFIG. 14.

Each of the plurality of routing blocks150may include a plurality of routing units170illustrated inFIG. 18. Each of the plurality of routing units170may receive a plurality of pieces of configuration information, select one of a plurality of pieces of routing information based on the plurality of pieces of configuration information, and connect the plurality of connection blocks100based on the selected routing information.

The plurality of I/O terminals may be connected to the plurality of connection blocks100or the plurality of logic blocks50to transmit the plurality of pieces of configuration information to either the plurality of connection units90in the plurality of connection blocks100and particularly, storage devices in connection units90or functional blocks (or interconnection units) in the logic blocks50. Also, the I/O terminals may transmit output signals from the logic blocks50to the outside. The I/O terminals may be embodied as, for example, chip pads of semiconductor chips where a logic device is implemented therein.

FIG. 16is a block diagram specifically illustrating the connection block100, the logic block50, and the I/O terminal illustrated inFIG. 15. Referring toFIG. 16, the connection block100may include a plurality of interconnection units70or may include a plurality of connection units90. In the logic block50, each of functional blocks30may receive configuration information and external information via the interconnection units70, and may be connected to the other functional blocks30included in the logic block50. Also, each of the functional blocks30may be connected to functional blocks included in another logic block (not shown) via the connection units90.

An output terminal of each of the functional blocks30may be connected to one of the I/O terminals. A D flip flop (DFF) and a multiplexer (MUX) may be connected to the output terminal of each of the functional blocks30and the corresponding I/O terminal. The DFF and the MUX may determine whether an output signal of the functional block30is to be output according to sequential logic or combinational logic. A unit80including at least one switch device and at least one configuration unit may further be included between the output terminal of each of the functional block30and the corresponding I/O terminal.

FIG. 17is a schematic diagram illustrating a case where the logic device ofFIG. 16is configured to function as the logic device ofFIG. 6. Referring toFIG. 17, a first functional block30-1may receive a first input signal containing first external information and configuration information. The first functional block30-1may output a first output signal from the first input signal, and the first output signal may be transmitted as a second input signal to a second functional block30-2. Thus, the second functional block30-2may receive a second input signal containing the first output signal, second external information, and the configuration information. An output terminal of the second functional block30-2may be connected to an I/O terminal. Thus, the second output signal may be output via the I/O terminal.

FIG. 18is a block diagram specifically illustrating the routing block150illustrated inFIG. 15, according to example embodiments.FIG. 19is a circuit diagram specifically illustrating first and second transmission units180and190included in each of a plurality of routing units170in the routing block150illustrated inFIG. 15, according to example embodiments.

Referring toFIGS. 18 and 19, each of the plurality of routing units170may include the first transmission unit180and the second transmission unit190. The first transmission unit180may transmit a signal in a direction from a first terminal T1to a second terminal T2, and the second transmission unit190may transmit a signal in a direction from the second terminal T2to the first terminal T1. Whether a signal is to be transmitted and a direction in which the signal is to be transmitted may be determined according to configuration information. Thus, the connection blocks100ofFIG. 15may be appropriately connected via the plurality of routing units170.

More specifically, the first transmission unit180may include a third configuration unit185and transistors187. The third configuration unit185may receive configuration information and output a signal indicating whether a connection state or a disconnection state is required. For example, the third configuration unit185may output ‘1’ when the connection state from the first terminal T1to the second terminal T2is required and may output ‘0’ when the disconnection state is required, based on routing information. A circuit construction of the third configuration unit185may be the same as that of the configuration unit75ofFIG. 9.

If routing information stored in the third configuration unit185denotes the connection state and the third configuration unit185outputs ‘1’, a first N-type transistor NTR1and a first P-type transistor PTR1may be turned on. Thus, a signal may be transmitted in the direction from the first terminal T1to the second terminal T2. If the routing information stored in the third configuration unit185denotes the disconnection state and the third configuration unit185outputs ‘0’, the first N-type transistor NTR1and the first P-type transistor PTR1may be turned off. Thus, a signal may not be transmitted in the direction from the first terminal T1to the second terminal T2.

Such a circuit construction and operation may also be applied to the second transmission unit190. Thus, signal transmission of the routing unit170may be classified as follows:

In a general reconfigurable logic device, functional blocks and connection blocks should be individually reconfigured to perform various operations, which results in a long time being taken to perform the operations. However, in a logic device according to example embodiments, information for performing various operations has been previously stored. That is, various operations may be set according to configuration information, and such reconfiguration is not needed. Thus, various operations may be performed within a short time.

FIGS. 20A and 20Bare diagrams illustrating non-limiting examples of connections between functional blocks in logic blocks according to example embodiments.

Referring toFIG. 20A, a logic block according to example embodiments may be configured to function as an AND gate by connecting a first functional block NA1to a second function block NA2. For example, an interconnection unit (not shown inFIG. 20A) may be configured to connect the first NA1and second NA2functional blocks. The first NA1and second NA2functional blocks may be non-volatile memory devices, but example embodiments are not limited thereto. The first functional block30-1and the second functional block30-2described above with reference toFIG. 5may be used as the first functional block NA1and the second functional block NA2, respectively.

Referring toFIG. 20B, a logic block according to example embodiments may be configured to function as an OR gate when the first functional block NA1and the second functional block NA2are not connected to each other. An interconnection unit (not shown inFIG. 20B) may be configured to not connect the first NA1and second NA2functional blocks.