Output buffer with slew rate control and a selection circuit

An output buffer having a controlled output slew rate comprises a first predriver circuit having a first RC circuit and a first output node and a second predriver circuit having a second RC circuit and a second output node. A buffer input node is coupled to the first and second predriver circuits. The output buffer further includes an output circuit having first and second input nodes and a third output node, where the first and second input nodes are coupled, respectively, to the first and second output nodes. The time constants of the RC circuits control a signal slew rate at the third output node of the output circuit, and the value of R may be selected to provide a predetermined, controlled slew rate range at the third output node. A selection circuit aids in the selection of an appropriate value for R.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is generally directed to the field of integrated circuits, and, more particularly, to an integrated circuit having an output buffer with slew rate control and a selection circuit for producing a desired slew rate in the output buffer.

2. Description of the Related Art

Integrated circuit devices have become quite commonplace in the modern world. A modern computer system may include hundreds, if not thousands, of integrated circuit devices. Over the years, the individual integrated circuit devices themselves have become extremely complex, and their interaction with one another, for example in a modern computer system, has also become much more complex. The timing of various signals between integrated circuit devices in a computer system, for example, is now much more critical than in early computer systems. Standards have been promulgated to govern the timing of signals between integrated circuit devices. Various bus architectures used in personal computers, for example, have specifications controlling the timing of various signals as well as the speed with which various signals must become “valid.” As an example, some bus specifications require that a signal become “valid” within a specified period of time following a triggering event.

To meet such timing requirements, many integrated circuits that provide output signals employ some form of “slew rate” control. “Slew rate” is the rate at which an output voltage, for example, transitions from a “low” value to a “high” value, or from a “high” value to a “low” value. Some devices have attempted to control the slew rate by restricting the range of process variables, voltage and temperature. Other devices attempt to control the slew rate by turning on the output signal in stages. That is, an output signal from a particular integrated circuit device may be driven by two or more output stages, and the two or more stages will be turned on in sequence to control the slew rate. Many Universal Serial Bus drivers use a capacitive feedback from the output to the predriver stage. These devices attempt to use the gain of the output stage to make the capacitance at the predriver node appear to be very large. In essence, this technique attempts to desensitize the output driver to variations in the output capacitance, allowing greater variation of the output capacitance without undue effect on the slew rate.

However, variation in the output capacitance is not the only factor that affects the slew rate. Variations in manufacturing process parameters, voltage levels in the integrated circuit device and temperature at which the device is operating all contribute to variations in the slew rate at the output stage. In particular, in light of the many factors affecting slew rate, as the load capacitance and process being driven by the output circuit varies through a permitted range, the slew rate of the output signal may fall outside the range required by an applicable specification.

The present invention is directed to solving, or at least reducing, some or all of the aforementioned problems.

SUMMARY OF THE INVENTION

In one aspect of the present invention, an output buffer comprises a predriver circuit having first and second transistors and an RC circuit, the RC circuit being coupled between the first and second transistors. The output buffer further comprises an output circuit coupled to the predriver circuit, the output circuit having an input node and an output node, the output node including a capacitor coupled between the input node and the output node. The RC circuit is selected to provide a controlled signal slew rate at the output node of the output circuit.

In another aspect of the present invention, a selection circuit comprises a first integrating stage having a first comparator coupled to a first delay circuit, the first integrating stage having an input node and a first output node. The selection circuit further comprises a second integrating stage having a second comparator coupled to a second delay circuit, the second integrating stage having an input node and a second output node. The selection circuit includes an input node coupled to the input nodes of the first and second integrating stages and a time reference node coupled to the first and second comparators.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described with reference toFIGS. 1,2A–2D and3A–3B. In the illustrative example shown in FIGS.1and2A–2D, CMOS circuitry is employed. However, as will be readily apparent to those skilled in the art upon a complete reading of the present application, the present invention may be realized utilizing a variety of technologies, for example, NMOS, PMOS, CMOS, etc. Moreover, the present invention may be used in a variety of integrated circuit devices that supply an output signal, including, but not limited to, logic devices, memory devices, etc.

FIG. 1depicts one illustrative embodiment of an output buffer utilizing aspects of the present invention. The output buffer100includes a first predriver circuit101and a second predriver circuit103. In addition, the output buffer100includes an output circuit105. The output buffer100receives a signal at an input node102and provides an output signal at an output node154. The output node154may be coupled to an output pad104, for example, of a packaged integrated circuit device. The output pad104will typically be coupled to a capacitive load106that will receive the output signal from the output buffer100. While the illustrative embodiment employs first and second predriver circuits101,103, it will become apparent to a person of ordinary skill upon a complete reading of this disclosure that a single predriver circuit may be employed or multiple predriver circuits may be used.

The first predriver circuit101includes a first transistor110and a second transistor112coupled in series between a first power supply node114and a second power supply node116. The first transistor110in the illustrative embodiment is a P-channel transistor, while the second transistor112is an N-channel transistor. As a person of ordinary skill in the art will appreciate upon a complete reading of this disclosure, the illustrative embodiment ofFIG. 1is a CMOS implementation of the present invention. The first power supply node114in the illustrative embodiment may be coupled to a positive power supply potential of approximately 3.0 volts DC, while the second power supply node116may be coupled to an electrical ground potential.

Coupled between the first transistor110and the second transistor112is an RC circuit107. A resistor118is coupled in parallel to a capacitor128between a node124of the first transistor110and a node126of the second transistor112. Thus, the RC circuit107is coupled in series with the first transistor110and the second transistor112between the first power supply node114and the second power supply116. A gate terminal120of the first transistor110and a gate terminal122of the second transistor112are each coupled to the input node102. The node124is coupled to the output circuit105, as will be more fully explained below.

The second predriver circuit103includes a first transistor130and a second transistor132coupled in series between the first power supply node114and the second power supply node116. In the illustrative embodiment ofFIG. 1, the transistor130is a P-channel transistor, and the second transistor132is an N-channel transistor. A gate terminal140of the first transistor130and a gate terminal142of the second transistor132are each coupled to the input node102. An RC circuit109is coupled in series between the first transistor130and the second transistor132. Thus, the first transistor130, the RC circuit109and the second transistor132are coupled in series between the first power supply node114and the second power supply node116. The RC circuit109includes a resistor138and a capacitor148coupled in series between a node144of the first transistor130and a node146of the second transistor132. The node146is coupled to the output circuit105as will be explained further below.

The output circuit105comprises a first transistor150coupled in series with a second transistor152between the first power supply node114and the second power supply node116. In the illustrative embodiment ofFIG. 1, the first transistor150is a P-channel transistor, and the second transistor152is an N-channel transistor. The output node154is a common node between the first transistor150and the second transistor152. A gate terminal160of the first transistor150is coupled to the node124of the first predriver circuit101. A gate terminal162of the second transistor152is coupled to the node146of the second predriver circuit103. A capacitor164is coupled between the gate terminal160of the first transistor150and the output node154. Another capacitor166is coupled between the gate terminal162of the second transistor152and the output node154. Table 1 sets forth the approximate sizes and values of the various components of the illustrative circuit ofFIG. 1.

Briefly, the output buffer100operates as follows: each of the predriver circuits101,103performs an inverter function, with their respective outputs124,146being a logical inverse of their input102. Thus, as an input signal at node102transitions from low to high, the output signals at nodes124,146will transition from high to low, and vice versa. The values of the resistors118,138and capacitors128,148will affect the rates at which the output signals at nodes124,146will transition from high to low and from low to high. As the output signals at nodes124,146transition from high to low, the output signal at the node154will transition from low to high. The values of the capacitors164,166, together with the value of the capacitive load106, will affect the rate at which the output signal at the node154will transition from low to high and from high to low. Also, the rates at which the output signals at the nodes124,146transition will affect the rate at which the output signal at the node154will transition.

For example, the function of the capacitor128may be understood by first considering the upper portion of the circuit ofFIG. 1assuming, for illustrative purposes, that the capacitor128is absent. For a low-to-high transition, the total capacitance on the node124is discharged through the resistor118and the transistor112. The voltage on node124, V124(t), follows V124(t)=3.3*(1−e−t/τ), where τ=R118*Ceff,124. When the voltage on the node124is discharged sufficiently to turn on the transistor160, the voltage on the node154begins to rise. The discharge current, limited by the resistor118, sees a larger effective capacitance at164(Ceff,164=(1−Av)C164), slowing the discharge rate of the voltage at node124and creating a voltage plateau. The relatively constant current through resistor118creates a linear voltage ramp at node154(I=dV/dt=Vplateau/R118). In the illustrated embodiment, however, the capacitor128is present and thus provides a feed-forward or voltage-divider path from the node124to node126. This reduces the delay from waiting for the voltage at node124to discharge to the threshold of transistor160.

For a given value of RC in the predriver circuits101,103, the output slew rate can be controlled within a range as the value of the capacitive load106varies. Thus, by selecting appropriate values for the resistors118,138and the capacitors128,148, the output slew rate can be controlled within a desired range as the value of the capacitive load106varies over a specified range. In certain applications of the present invention, the specified range over which the capacitive load106may vary is from approximately 15 pf to approximately 40 pf, or a range of about 2.67:1. In those applications, it is desirable to control the output slew rate to a range from approximately 0.4 volts/ns to approximately 1.0 volts/ns, or a range of about 2.5:1. Utilizing the present invention, this goal may be achieved.

Due to variations inherent in typical semiconductor manufacturing processes, the values of many of the components described above will vary. For example, in the illustrative output buffer100ofFIG. 1, the values of the resistors118,138and the capacitors128,148, and therefore the RC product, will normally vary from chip to chip. To allow a wider process range for R and C, the RC product may be adjusted. For example, the RC product may be adjusted by using switched resistors118,138. For another example, the RC product may be adjusted by using different values for the capacitors128,148.

FIGS. 2A–2Ddepict one illustrative embodiment of a selection circuit that may be used in conjunction with the output buffer100ofFIG. 1to determine an RC product that may produce an output slew rate that is in a desirable range. The selection circuit200comprises four integrating stages201,203,205and207. Each of the integrating stages201,203,205,207comprises a delay circuit (201A,203A,205A,207A) and a comparator (201B,203B,205B,207B), and each is similar in structure to the others. although the sizes of various features of certain of the devices (i.e., transistors, resistors and capacitors) vary from one stage to another as will be explained. Thus, each of the integrating stages201,203,205,207will provide a unique time delay between a given input signal at an input terminal222and the respective output signal from the particular integrating stage201,203,205,207, as will be seen below.

Considering the delay circuit201A (FIG. 2A) in the integrating stage201, a first transistor202, a resistor210and a second transistor204are coupled in series between a first power supply node206and a second power supply node208. In the illustrative embodiment ofFIG. 2A, the first transistor202is a P-channel transistor, and the second transistor204is an N-channel transistor. The first power supply node206in this illustrative embodiment may be coupled to a positive power supply potential of approximately 3.0 volts. The second power supply node208may be coupled to an electrical ground potential. A gate terminal218of the first transistor202and a gate terminal220of the second transistor204are each coupled to an input terminal222. A capacitor212is coupled in parallel with the resistor210between a node214and a node216. The transistors202,204, the resistor210and the capacitor212comprise a predriver circuit with a time delay between the input node222and the output node214, the delay being determined, at least in part, by the RC time constant of the resistor210/capacitor212combination.

Also in the delay circuit201A, a third transistor232and a fourth transistor234are coupled in series between the first power supply node206and the second power supply node208. In the illustrative embodiment ofFIG. 2A, the third transistor232is a P-channel transistor, and the fourth transistor234is an N-channel transistor. A gate terminal236of the third transistor232is coupled to the node214. A capacitor240is coupled between the gate terminal236of the third transistor232and the common node242between the third transistor232and the fourth transistor234. The transistors232,234and the capacitor240comprise an inverter circuit with capacitive feedback from the inverter output node242to the inverter input node214. However, the transistors232,234and the capacitor240need not comprise an inverter circuit, but may comprise a non-inverting circuit, for example. A fifth transistor244is coupled between the first power supply node206and the node242. The fifth transistor244is connected as a capacitor, such that its drain and source terminals are coupled together and together are coupled to the first power supply node206. A gate terminal246of the fifth transistor244is coupled to the node242. A gate terminal238of the fourth transistor234is coupled to receive a signal from the output terminal of an inverter230. The inverter230is a CMOS inverter, having a P-channel pull-up transistor and an N-channel pull-down transistor, and its input terminal is coupled to the input terminal222.

In the comparator201B, a differential amplifier250has a first input terminal coupled to the node242and a second input terminal coupled to receive a reference voltage from a reference voltage terminal252. An output terminal from the differential amplifier250is coupled to an input node of an inverter260. The inverter260is a CMOS inverter, having a P-channel pull-up transistor and an N-channel pull-down transistor, and its output node is coupled to a first output terminal271of the selection circuit200.

As depicted inFIGS. 2B–2D, respectively, each of the integrating stages203,205,207includes transistors, resistors, capacitors, inverters and a differential amplifier arranged and interconnected in the same manner as in the integrating stage201ofFIG. 2A. The input terminal222is coupled to the integrating stages203,205,207in the manner it is coupled to the integrating stage201. As already stated, the sizes of various features of certain of the component devices that make up each of the integrating stages201,203,205,207differ. More particularly, in the illustrative selection circuit200ofFIGS. 2A–2D, all corresponding transistors, capacitors and inverters in the integrating stages201,203,205,207are of substantially the same size. For example, the transistor202in the integrating stage201and the corresponding transistors302,402,502in the integrating stages203,205,207, respectively, are each of substantially the same size. Likewise, the capacitor212in the integrating stage201and the corresponding capacitors312,412,512in the integrating stages203,205,207, respectively, are each of substantially the same size and value. Table 2 below sets forth the nominal sizes and values of the various components of the integrating stages201,203,205,207.

However, the size and value of the resistor used in each of the integrating stages201,203,205,207varies. That is, the resistor210in the integrating stage201and the corresponding resistors310,410,510in the integrating stages203,205,207, respectively, are each of different sizes and values. Table 2 sets forth the approximate sizes and values of the resistors in the integrating stages201,203,205,207for one illustrative embodiment of the present invention. The different resistive values yield different RC time constants in each integrating stage. For example, the resistor210/capacitor212combination in the integrating stage201will have an RC time constant that differs from the resistor310/capacitor312combination in the integrating stage203. Consequently, the integrating stage201will have a longer delay between its input and its output than the integrating stage203. Likewise, the resistor410/capacitor412combination in the integrating stage205will have an RC time constant that differs from the resistor510/capacitor512combination in the integrating stage207, from the resistor310/capacitor312combination, and from the resistor210/capacitor212combination. The integrating stage203will have a longer delay between its input and its output than the integrating stage205, and the integrating stage205will have a longer delay than the integrating stage207. Thus, in one embodiment, the four integrating stages201,203,205,207will have progressively shorter time delays between input and output, with the integrating stage201having the longest of the four delays and the integrating stage207having the shortest. The magnitude of the difference in delay from one stage to another need not be the same in all cases.

The selection circuit200may be fabricated on the same integrated circuit chip as the output buffer100such that any variation due to feature size, process variation or other manufacturing artifact will affect the selection circuit200and the output buffer100in approximately the same manner and to approximately the same extent. In one specific implementation of the output buffer100and the selection circuit200on the same integrated circuit chip, a known clock circuit (not shown) has been utilized in conjunction with the selection circuit200to aid in selecting appropriate values for the resistors118and138in the output buffer100(seeFIG. 1) such that the slew rate of a signal on the node154(FIG. 1) will be within certain specified limits.

In one embodiment, by applying a periodic signal of approximately 3.0 volts at the input terminal222, the amount of delay introduced by each of the four integrating stages201,203,205,207may be measured. For example, a periodic step voltage that varies between approximately zero volts and approximately 3 volts may be applied at the input terminal222. A known clock circuit operating at a frequency of approximately 14.318 MHz may be used to supply the periodic step voltage, and the period of the known clock circuit (in this instance, approximately 70 ns) may be compared to the lengths of delays introduced by each of the integrating stages201,203,205,207. The particular integrating stage that introduces a delay most closely matched with the known clock period may be used to determine appropriate sizes for the resistors118,138in the output circuit. As will be appreciated by a person of ordinary skill in the art having the benefit of this disclosure, because of variations in semiconductor manufacturing processes and/or operating conditions, different ones of the integrating stages201,203,205,207will most closely match the 70 nanosecond clock period on different integrated circuit chips.

In the illustrative implementation, assuming for purposes of explanation that the integrating stage203in a particular integrated circuit chip introduces a delay most closely matching the known clock period, the sizes of the resistors118,138in the output buffer100may be selected. In the event the longest delay (integrating stage201, for example) is shorter than the known clock period, the integrating stage201will be used to select appropriate resistor sizes for the output buffer100. In the event the shortest delay (integrating stage207, for example) is longer than the known clock period, the integrating stage207will be used to select appropriate resistor sizes for the output buffer100.

The number of integrating stages in the selection circuit200may be increased or decreased, depending on, among other things, the number of steps desired to control the output slew rate to a desired limit and/or the number of switch points the chip designer desires. In the illustrative selection circuit200, two integrating stages define a “switch point” by providing a hysteresis, as discussed in more detail below. For example, the integrating stages201,203define a first switch point, while the integrating stages205,207define a second switch point. Any number of switch points may be defined to provide a granularity sufficient to achieve the desired output slew rate range. In alternative embodiments, the hysteresis may be achieved by other means or may be omitted.

FIG. 3Aillustrates integrator curves that correspond to the four integrating stages201,203,205,207of the illustrated selection circuit200. As can be seen, each curve shows the variation of the slew rate for each value of RC and for “high” (40 pf) and “low” (15 pf) values of the capacitive load106. That is, curves602,604and606illustrate the variation of the output slew rate (from approximately 0.4 volts/ns to approximately 0.8 volts/ns) for three ranges of the RC constant where the capacitive load106is approximately 15 pf. Curve602represents an RC time constant range of about +10% to about +40% of “RC nom,” curve604represents an RC time constant range of about +15% to about −15% of “RC nom,” and curve606represents an RC time constant range of about −10% to about –40% of “RC nom.” The curves612,614,616illustrate the variation of the output slew rate (from approximately 0.6 volts/ns to approximately 1.0 volts/ns) for the same three ranges of the RC time constant where the capacitive load106is approximately 40 pf. Thus, curve612represents an RC time constant range of about +10% to about +40% of “RC nom,” curve614represents an RC time constant range of about +15% to about −15% of “RC nom,” and curve616represents an RC time constant range of about −10% to about −40% of “RC nom.” The curves602,604,606overlap slightly, as do the curves612,614,616. The overlap may be used to create the aforementioned hysteresis, if so desired. InFIG. 3A, “RC nom” represents the value of RC at nominal process voltage and temperature.

FIG. 3Bgraphically illustrates switch points702,704that correspond to the illustrative selection circuit200ofFIGS. 2A–2D. As seen, two switch points702,704having hysteresis are defined, a first switch point702occurring at approximately −25% and −30% of “tnorm,” and a second switch point704occurring at approximately +25% and +30% of “tnorm.” Each switch point702,704includes a range correlating to the overlap of the curves illustrated inFIG. 3A. The vertical axis of the graph ofFIG. 3Bdepicts the value of the resistors118,138of the output buffer100ofFIG. 1. In the illustrative embodiment, the “Rnom,” or nominal resistor value, may be approximately 1200 ohms. The value of “R” may be assigned a value of approximately 600 ohms at and below the first switch point, and it may be assigned a value of approximately 1800 ohms at and above the second switch point. From the curves depicted inFIG. 3A, it can be seen that these values of “R” will yield a value of RC that will provide the desired output slew rate over the specified range of the capacitive load106.