Method for manufacturing non-volatile memory

A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 96132740, filed on Sep. 3, 2007. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing an isolation structure and a memory, and in particular, to a method for manufacturing a trench isolation structure and a non-volatile memory.

2. Description of Related Art

A memory is a semiconductor device designed to store data. As the microprocessors in computers become more powerful than ever to be compatible with growingly massive amount of programs and calculations executed by the software, the capacity of the memory needs to be increased accordingly. The developments of memories move toward manufacturing large-storage and low-cost memories to meet the requirements in the semiconductor manufacture.

Among various kinds of memory products, the non-volatile memory is a kind of memory characterized by the advantages that it allows multiple data storing, reading or erasing operations and the stored data therein will be retained after the device is not powered. Hence, the non-volatile memory has become a widely adopted memory device in personal computers and electronic equipments.

In regard to the operation of the non-volatile memory, generally, if the coupling ratio of a device is large, the work voltage required for operating the device is low. The method of increasing the coupling ratio includes increasing an overlap area between the floating gate and the control gate, reducing the thickness of the dielectric layer between the floating gate and the control gate, and increasing the dielectric constant of the dielectric layer between the floating gate and the control gate. However, the general non-volatile memory usually has a problem of an overly low coupling ratio. The problem affects the electron flowing efficiency when a programming operation or an erasing operation is performed. Therefore, the work efficiency of the non-volatile memory is reduced.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a method for manufacturing a non-volatile memory, which can increase the coupling ratio of a device efficiently.

The present invention is further directed to a method for manufacturing a trench isolation structure, by which a layer in a subsequent process can be filled into a place under the surface of the substrate.

The present invention provides a method for manufacturing a non-volatile memory. The method includes providing a substrate having a trench formed therein at first. Then, an isolation structure is formed in the trench. Next, a portion of the isolation structure is removed to form a recess between the top portion of the trench and the isolation structure. After that, a first dielectric layer is formed on the substrate. Thereafter, a first conductive layer is formed on the first dielectric layer, and the first dielectric layer completely fills the recess. Afterwards, a plurality of bar-shaped cap layers is formed on the substrate, wherein the extending direction of the bar-shaped cap layers is across that of the isolation structure. Then, the first conductive layer not covered by the bar-shaped cap layers is removed to form a plurality of first gate structures. Next, a second dielectric layer is formed on sidewalls of the first gate structures. After that, a third dielectric layer is formed on the substrate between the first gate structures. Then, a second conductive layer is formed on the third dielectric layer, and the second conductive layer completely fills the recess. Afterwards, the bar-shaped cap layers and a portion of the first conductive layer are removed to form a plurality of second gate structures. Then, a doped region is formed in the substrate at two sides of each of the second gate structures.

According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory, the method of removing a portion of the isolation structure includes performing a wet etching process, for example.

According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory, the method of forming the trench includes, for example, sequentially forming a pad layer and a hard mask layer on the substrate at first. Then, a patterning process is performed.

According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory, the method of forming the isolation structure includes, for example, forming an isolation material on the substrate at first, wherein the isolation material completely fills the trench. Then, a planarization process is performed for removing the isolation material on the hard mask layer. After that, the hard mask layer is removed.

According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory, the method of forming the first dielectric layer includes performing a thermal oxidation process, for example.

According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory, the method of forming the first conductive layer includes, for example, forming a conductive material layer on the substrate at first, wherein the conductive material layer covers the isolation structure and completely fills the recess. Then, a planarization process is performed to remove a portion of the conductive material layer until the isolation structure is exposed.

According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory, an etching back process can be performed to remove a portion of the isolation structure after the bar-shaped cap layers are formed but before the first conductive layer not covered by the bar-shaped cap layers is removed.

According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory, the method of forming the second dielectric layer includes, for example, conformally forming a dielectric material layer on the substrate at first. Then, a dry etching process is performed.

According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory, the method of forming the third dielectric layer includes performing a thermal oxidation process, for example.

According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory, the method of forming the second conductive layer includes, for example, forming a conductive material layer on the substrate at first, wherein the conductive material layer fills the gap between the first gate structures. Then, a planarization process is performed to remove a portion of the conductive material layer until the first gate structures are exposed.

According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory, a portion of the second conductive layer can be removed at first after the second conductive layer is formed but before the bar-shaped cap layers and a portion of the first conductive layer are removed. Then, an oxidation process is performed on the remaining second conductive layer to form a cap layer thereon. After that, a metal hard mask layer is formed on the cap layer.

According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory, the method of forming the second gate structures further includes, for example, a first oxidation process is performed on the first conductive layer and forming a spacer on the sidewall of the second conductive layer after removing the bar-shaped cap layers but before removing a portion of the first conductive layer. After that, a portion of the first conductive layer is removed by using the spacer as a mask. Thereafter, a second oxidation process is performed on the remaining first conductive layer.

According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory, an etching back process can be performed to remove a portion of the isolation structure after the spacer is formed but before a portion of the first conductive layer is removed.

According an embodiment of the present invention, in the method for manufacturing the non-volatile memory, the top of the isolation structure is at a level higher than the surface of the substrate.

The present invention further provides a method for manufacturing a trench isolation structure. The method includes forming a trench in the substrate at first. Then, an isolation structure is formed in the trench. After that, a wet etching process is performed to remove a portion of the isolation structure for forming a recess between the top portion of the trench and the isolation structure.

According to an embodiment of the present invention, in the method for manufacturing the trench isolation structure, the method of forming the trench includes, for example, sequentially forming a pad layer and a hard mask layer on the substrate at first. Then, a patterning process is performed.

According to an embodiment of the present invention, the method for manufacturing the trench isolation structure includes, for example, forming an isolation material on the substrate at first, wherein the isolation material completely fills the trench. Then, a planarization process is performed for removing the isolation material on the hard mask layer. After that, the hard mask layer is removed.

According to an embodiment of the present embodiment, in the method for manufacturing the trench isolation structure, the top of the isolation structure is at a level higher than the surface of the substrate.

According to the present invention, after the isolation structure is formed in the trench, a portion of the isolation structure is removed by performing the wet etching process to form a recess between the top portion of the trench and the isolation structure, and thereby the conductive layers which respectively serve as the floating gate and the control gate can be filled into the recess for forming the floating gate and the control gate with a larger size, so as to increase the overlap area between the floating gate and the control gate, and to increase the coupling ratio of a device and improve operation efficiency of the device.

In order to make the aforementioned features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described in detail below.

DESCRIPTION OF EMBODIMENTS

Referring toFIGS. 1A,2A and3A at first, a substrate100having a trench102formed therein is provided. The method of forming the trench102includes, for example, forming a pad layer104and a hard mask layer106on the substrate sequentially. Then, a photolithography process and an etching process are performed to pattern the hard mask layer106, the pad layer104and the substrate100. The material of the pad layer104includes, for example, silicon oxide. The method of forming the pad layer104includes, for example, a thermal oxidation process. The material of the hard mask layer106includes, for example, silicon nitride. The method of forming the hard mask layer106includes performing a chemical vapor deposition process, for example.

Referring toFIGS. 1A,2A and3A, an isolation material (not shown) is formed on the substrate100by performing a high density plasma chemical vapor deposition (HDPCVD) process, for example. The isolation material completely fills the trench102. The isolation material is constituted by silicon oxide, for example. Then, a planarization process is performed to remove excessive isolation material on the hard mask layer106by using a chemical-mechanical polishing process, so as to form an isolation structure108in the trench102. The isolation structure108is a so-called shallow trench isolation (STI) structure.

After that, referring toFIGS. 1B,2B and3B, the hard mask layer106is removed. Thereafter, a wet etching process is performed to remove a portion of the isolation structure108for forming a recess110between the top portion of the trench102and the isolation structure108. In details, in order to fill spaces around the isolation structures108with sufficient amount of material in a subsequent process after the hard mask layer106is removed, the wet etching process is performed to remove a portion of the isolation structure108at the top portion of the trench102, and thereby the material of the layer in the subsequent process can be filled into the formed recess110. Of course, the depth of the formed recess should be determined depending on the actual situation, so as to prevent the isolation structure from being over etched, and thereby the size of the subsequently formed floating gate and control gate is overly small, so that the deduction of the coupling ratio is avoided.

Then, referring toFIGS. 1C,2C and3C, a dielectric layer112is formed on the substrate100. The material of the dielectric layer112includes silicon oxide, for example. The dielectric layer112is formed by performing the thermal oxidation process, for example. The dielectric layer112is used as the tunneling dielectric layer in the non-volatile memory. After that, a conductive layer114is provided on top of the dielectric layer112and completely fills the recess110. The conductive layer114is formed by forming a conductive material layer (not shown) on the substrate100at first. The conductive material layer, being sandwiched by two adjacent isolation structures108and on top of the substrate100, covers the dielectric layer112and completely fills the recess110. The material of the conductive material layer includes, for example, doped polysilicon. Then, a planarization process is performed to remove a portion of the conductive material layer by using the chemical-mechanical polishing process until the isolation structure108is exposed.

Referring toFIGS. 1C,2C and3C, a cap layer116is formed on the substrate. The material of the cap layer116includes silicon nitride, for example. The cap layer is formed by, for example, performing a chemical vapor deposition process. Thereafter, a photolithography process is performed to form a patterned photoresist layer118on the cap layer116, so as to define a control gate area.

After that, referring toFIGS. 1D,2D,3D and4A, an etching process is performed to remove the cap layer116not covered by the patterned photoresist layer118by using the patterned photoresist layer118as a mask, so as to form bar-shaped cap layers116a. The extending direction of the bar-shaped cap layers116ais across that of the isolation structure108. According to the present embodiment, the extending direction of the bar-shaped cap layers116ais perpendicular to that of the isolation structure108, for example. Then, the patterned photoresist layer118is removed. Next, an etching back process is performed to remove a portion of the isolation structure108. Thereafter, an etching process is performed by using the bar-shaped cap layers116aas the mask for removing the conductive layer114not covered by the bar-shaped cap layers116a, so as to form gate structures120. Thereby, when removing the conductive layer114not covered by the bar-shaped cap layers116ain the subsequent process, the isolation structure108is not overly high and the conductive layer114can be removed completely. Therefore, the conductive layer114does not remain at the bottom to affect a device.

Referring toFIGS. 1E,2E,3E and4B, a dielectric material layer (not shown) is conformally formed on the substrate100. According to the present embodiment, the dielectric material layer is constituted by a silicon oxide/silicon nitride/silicon oxide composite layer. The dielectric material layer is formed by, for example, forming a first silicon oxide layer by performing a thermal oxidation process at first. Then, a silicon nitride layer is formed on the first silicon oxide layer by performing a chemical vapor deposition process. After that, a second silicon nitride layer is formed on the silicon nitride layer by performing another thermal oxidation process. Certainly, in a different embodiment, the dielectric material layer can be constituted only by silicon oxide. Then, a portion of both the dielectric material layer and the dielectric layer112thereunder are removed by, for example, performing a dry etching process, so as to form a dielectric layer122on the sidewalls of the gate structures120, and to expose the substrate100between the gate structures120. The dielectric layer122at the sidewalls of the gate structures120is used as the inter-gate dielectric layer in the non-volatile memory.

Referring toFIGS. 1E,2E,3E and4B, a dielectric layer124is formed on the substrate100between the gate structures120by performing a thermal oxidation process. The dielectric layer124is used as the gate dielectric layer in the non-volatile memory. Then, a conductive material layer (not shown) constituted by doped polysilicon is deposited on the substrate100, wherein the conductive material layer completely fills the gap between the gate structures120and the recess110. After that, a planarization process is performed by using the chemical-mechanical polishing process until the gate structures120are exposed, so as to form the conductive layer126used as the control gate in the non-volatile memory on the dielectric layer124.

Referring toFIGS. 1E,2E,3E and4B, an etching back process is performed to remove a portion of the conductive layer126. Then, an oxidation process is performed on the remaining second conductive layer126to form a cap layer128thereon. The material of the cap layer128includes silicon oxide, for example. The cap layer128is formed by performing a thermal oxidation process, for example. After that, a metal hard mask layer130is formed on the cap layer128. The material of the metal hard mask layer130includes, for example, polysilicon. The metal hard mask layer130is used as an etching mask when removing the bar-shaped cap layers116aand a portion of the isolation structure108in the subsequent process. The cap layer128is used as an etching mask when forming the floating gate subsequently.

Thereafter, referring toFIGS. 1F,2F,3F and4C, the bar-shaped cap layers116aare removed. After that, a first oxidation process is performed on the conductive layer114, so as to form an oxidation layer132on the conductive layer114. Afterwards, a spacer material layer (not shown) is conformally formed on the substrate100. The material of the spacer material layer includes, for example, silicon nitride. Then, a portion of the spacer material layer is removed by performing a dry etching process, so as to form a spacer134on the sidewalls of the conductive layer126. Next, an etching back process is performed to remove a portion of the isolation structure108. Thereby, when removing a portion of the conductive layer126to form the floating gate by performing an etching process subsequently, the isolation structure108is not overly high, such that the conductive layer126can be removed completely. Therefore, the conductive layer126does not remain at the bottom to affect the device.

After that, referring toFIGS. 1G,2G,3G and4D, an etching process is performed by using the spacer134as the mask, so as to remove a portion of the oxidation layer132, the conductive layer114and the dielectric layer112thereunder for exposing the substrate100, and a conductive layer114aused as the floating gate in the non-volatile memory and a dielectric layer112aused as the tunneling dielectric layer in the non-volatile memory are simultaneously formed. Certainly, the metal hard mask layer130is also removed in the aforesaid etching process. Then, an oxidation process is performed on the conductive layer114ato form an oxidation layer136, so that manufacture of a gate structure138in the non-volatile memory is completed. Afterwards, an ion implanting process is performed on the substrate100at two sides of the gate structure138, so as to form a doped region140in the substrate100at two sides of the gate structure138. Thereby, manufacture of the non-volatile memory is completed.

In light of the above, according to the present invention, after the isolation structure is formed in the trench, a portion of the isolation structure is removed by performing the wet etching process to form the recess between the top portion of the trench and the isolation structure, and thereby the conductive layers respectively used as the floating gate and the control gate can be filled into the recess for forming the floating gate and the control gate with a larger size in the subsequent process, so as to increase the overlap area between the floating gate and the control gate, to increase the coupling ratio of the device and to improve the operation efficiency of the device.