Solid state drive, electronic device including solid state drive, and method of managing solid state drive

An electronic device includes: a power supply to supply a first power and a second power; a first solid state drive (SSD) backplane and a second SSD backplane to receive the first power from the power supply, each of the first solid state drive (SSD) backplane and the second SSD backplane including two or more SSDs; and a baseboard to receive the second power from the power supply, to independently power on and power off the first SSD backplane and the second SSD backplane, and to access the SSDs of an SSD backplane that is in a power-on state from among the first SSD backplane and the second SSD backplane. In response to an increase in temperature of an SSD backplane that is in a power-off state, at least one SSD of the SSD backplane that is in the power-off state may be powered on.

CROSS-REFERENCE TO RELATED APPLICATIONS

Korean Patent Application No. 10-2020-0086230, filed on Jul. 13, 2020, in the Korean Intellectual Property Office, and entitled: “Solid State Drive, Electronic Device Including Solid State Drive, and Method of Managing Solid State Drive,” is incorporated by reference herein in its entirety.

BACKGROUND

Embodiments relate to an electronic device, and more particular, relate to a solid state drive, an electronic device including the solid state drive, and a method of managing the solid state drive.

2. Description of the Related Art

A solid state drive may include a nonvolatile memory. The solid state drive may store data in the nonvolatile memory, and provide data read from the nonvolatile memory. The nonvolatile memory may include a flash memory, a phase-change memory, a ferroelectric memory, a magnetic memory, a resistive memory, and the like.

SUMMARY

Embodiments are directed to an electronic device, including: a power supply configured to supply a first power and a second power; a first solid state drive (SSD) backplane and a second SSD backplane configured to receive the first power from the power supply, each of the first solid state drive (SSD) backplane and the second SSD backplane including two or more SSDs; and a baseboard configured to receive the second power from the power supply, to independently power on and power off the first SSD backplane and the second SSD backplane, and to access the SSDs of an SSD backplane that is in a power-on state from among the first SSD backplane and the second SSD backplane. In response to an increase in temperature of an SSD backplane that is in a power-off state from among the first SSD backplane and the second SSD backplane, at least one SSD of the SSD backplane that is in the power-off state may be powered on.

Embodiments are also directed to a method of managing a solid state drive (SSD), the method including: powering off the SSD; powering on the SSD in response to an increase in an ambient temperature of the SSD; and performing a retention recovery operation at the SSD.

Embodiments are also directed to a solid state drive, including: a nonvolatile memory device including a plurality of memory blocks each including a plurality of memory cells; and a controller including a temperature sensor and configured to perform a retention recovery operation on the plurality of memory blocks when a temperature sensed by the temperature sensor is greater than a critical value. In a power-on, the controller may perform the retention recovery operation in response to no communication initialization with an external host device, or, after the power-on, the controller may perform the retention recovery operation in response to a request of the external host device.

DETAILED DESCRIPTION

FIG.1illustrates an electronic device100according to an example embodiment.

Referring toFIG.1, the electronic device100may be, e.g., a server. The electronic device100may include a power supply110and a power receiver120. The power supply110may generate a power PWR from an external power, and may supply the generated power PWR to the power receiver120. The power PWR may be provided in the form of two or more different voltages.

The power receiver120may receive the power PWR from the power supply110, and may operate based on the power PWR. The power receiver120may include a baseboard130, a first solid state drive (SSD) backplane140, a second SSD backplane150, a third SSD backplane160, a cooling control board170, coolers180, and sensors190.

The baseboard130may include a first central processing unit (CPU)131, a second CPU132, first memories133and second memories134connected with the first CPU131, third memories135and fourth memories136connected with the second CPU132, and a baseboard management controller (BMC)137. The baseboard130may supply the power PWR received from the power supply110to the first CPU131, the second CPU132, the first memories133, the second memories134, the third memories135, and the fourth memories136.

The first CPU131may use the first memories133and the second memories134as working memories. The second CPU132may use the third memories135and the fourth memories136as working memories. The first CPU131and the second CPU132may execute an operating system and various applications. The first CPU131and the second CPU132may control components of the power receiver120. For example, the first CPU131and the second CPU132may control the components of the power receiver120based on PCIe.

The first CPU131and the second CPU132may access the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160. For example, the first CPU131and the second CPU132may access the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160based on NVMe. The first memories133, the second memories134, the third memories135, and the fourth memories136may include DIMM memories installed in DIMM slots.

The BMC137may be a separate system that is separate from an operating system of the first CPU131and the second CPU132. The BMC137may collect information from the components of the electronic device100, and may access the components. The BMC137may be based on a separate communication interface that is separate from communication interfaces (e.g., PCIe) of the first CPU131and the second CPU132. For example, the BMC137may be based on an intelligent platform management interface (IPMI). The communication interface of the BMC137may communicate with the communication interfaces of the first CPU131and the second CPU132.

The first SSD backplane140may receive the power PWR from the power supply110, may exchange signals SIG with the baseboard130, and may receive power signals PS from the baseboard130. The first SSD backplane140may exchange the signals SIG with the first CPU131, the second CPU132, or the BMC137of the baseboard130, and may receive the power signals PS therefrom. A plurality of SSDs may be installed in the first SSD backplane140. This may mean that the first SSD backplane140includes a plurality of SSDs.

The first CPU131and the second CPU132of the baseboard130may access (e.g., write, read, and erase) the SSDs of the first SSD backplane140through the signals SIG. The BMC137of the baseboard130may monitor the first SSD backplane140through the signals SIG, and may access and control the first SSD backplane140. The first CPU131, the second CPU132, or the BMC137of the baseboard130may power on or power off the first SSD backplane140by using the power signals PS.

Structures and operations of the second SSD backplane150and the third SSD backplane160may be the same as the structure and the operation of the first SSD backplane140. Thus, additional description will be omitted to avoid redundancy.

The baseboard130may power on and power off the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160independently of each other. For example, services that are supported by using the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160may be different. While the electronic device100does not provide a specific service, an SSD backplane corresponding to the specific service may be powered off, and the remaining SSD backplane(s) may be powered on.

For example, the frequencies of use of the services that are supported by using the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160may be different for each time zone. In a time zone when the frequencies of use of the services that are supported by using the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160are low, at least one of the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160may be powered off.

The cooling control board170may receive the power PWR from the power supply110. The cooling control board170may control the coolers180under control of the baseboard130. For example, the cooling control board170may control the coolers180under control of the first CPU131, the second CPU132, or the BMC137of the baseboard130. The cooling control board170may control operation activation and deactivation of the coolers180and the intensity (e.g., fan speed RPM) of cooling.

The coolers180may receive the power PWR from the power supply110. The coolers180may perform cooling under control of the cooling control board170such that a temperature of the electronic device100decreases. The coolers180may include fans, but embodiments are not limited thereto. The coolers180are not limited to the case where the coolers180are collectively disposed at one place. For example, the coolers180may be distributed and disposed at two or more places. A part of the coolers180may be attached to a chassis of the electronic device100and may inject an external air into the electronic device100. The rest of the coolers180may be disposed at a specific component and may take full charge of cooling of the specific component.

The sensors (SENS)190may receive the power PWR from the power supply110. The sensors190may be disposed adjacent to the components of the electronic device100. The sensors190may collect a variety of information under control of the baseboard130, and may provide the collected information to the baseboard130.

For example, the sensors190may collect information under control of the BMC137of the baseboard130, and may provide the collected information to the BMC137. The sensors190may provide the collected information to the BMC137through sensor data repository (SDR) of the IPMI. For example, different record IDs may be assigned to the sensors190. The sensors190may provide information to the BMC137based on different record IDs. The sensors190may include various sensors such as a temperature sensor, a humidity sensor, and a vibration sensor.

An example is illustrated inFIG.1as a specific number of CPUs and a specific number of memories are installed in the baseboard130, but the number of CPUs and the number of memories are not limited thereto. A specific number of SSD backplanes are illustrated inFIG.1, but the number of SSD backplanes is not limited thereto. Specific kinds of coolers are illustrated inFIG.1as much as a specific number, but kinds of coolers and the number of coolers are not limited thereto. A specific number of sensors are illustrated inFIG.1, but kinds of sensors and the number of sensors are not limited thereto.

FIG.2illustrates an example in which SSDs are installed in the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160. Referring toFIGS.1and2, to reduce the size of the electronic device100, SSDs may be closely installed in each of the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160. Also, to reduce the size of the electronic device100, the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160may be in close contact with each other.

When one of the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160is in a power-off state, the remaining SSD backplanes may be in a power-on state. A temperature of the SSD backplane being in the power-off state may increase due to heat generated at the SSD backplanes being in the power-on state. A temperature of the SSD backplane being in the power-off state may increase due to heat convected by the coolers180.

When a temperature of the SSD backplane that is in the powered-off state increases, the increased temperature may accelerate a reduction of retention of the SSDs installed in the powered-off SSD backplane. The reduction of retention may be recovered by a retention recovery operation. However, the retention recovery operation is not performed when the SSD backplane is in the power-off state. Accordingly, due to the reduction of retention, a data loss may occur at the SSDs installed in the SSD backplane being in the power-off state. As such, the electronic device100according to an example embodiment may power on at least one of SSDs installed in an SSD backplane that is in a power-off state in response to an increase in a temperature of the powered-off SSD backplane. The powered-on SSD(s) may perform the retention recovery operation to recover the reduction of retention. Accordingly, data can be prevented from being lost due to the reduction of retention accelerated by a high temperature at an SSD backplane being in a power-off state.

FIG.3illustrates an SSD backplane200according to a first example embodiment.

The SSD backplane200may correspond to the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160ofFIG.1. Referring toFIGS.1and3, the SSD backplane200may include first through fourth SSD slots211,212,213, and214. However, the number of slots is not limited. A respective SSD may be installed in each of the first SSD slot211, the second SSD slot212, the third SSD slot213, and the fourth SSD slot214. The SSDs may exchange the signals SIG with the baseboard130through signal lines.

The SSD backplane200may include first through fourth bi-metals221,222,223, and224respectively corresponding to the first through fourth SSD slots211,212,213, and214, and may include first through fourth regulators231,232,233, and234respectively corresponding to the first through fourth SSD slots211,212,213, and214.

Each of the first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224may include two separate materials (or metals) joined together and having different thermal expansion coefficients. In response to an increase of temperature, a material having a greater thermal expansion coefficient may expand more than a material having a smaller thermal expansion coefficient. Accordingly, each of the first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224may be bent toward a material having a smaller thermal expansion coefficient upon heating. Conversely, in response to a decrease of temperature, a material having a greater thermal expansion coefficient may contract more than a material having a smaller thermal expansion coefficient. Accordingly, each of the first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224may be bent toward a material having a greater thermal expansion coefficient upon cooling.

Each of the first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224may be respectively disposed adjacent to the first SSD slot211, the second SSD slot212, the third SSD slot213, and the fourth SSD slot214, such that the first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224may be bent in response to temperatures of the first SSD slot211, the second SSD slot212, the third SSD slot213, and the fourth SSD slot214.

The first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224may respectively receive voltages from the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234. In response to an increase of temperature, the first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224may be bent so as to be connected to (or spaced or disconnected from (e.g., the contacts may be normally open or normally closed, and appropriate logic may be implemented in accordance therewith)) terminals of the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234. Accordingly, the first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224may return (or may not return) the voltages received from the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234to the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234. Conversely, in response to a decrease of temperature, the first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224may be bent so as to be spaced from (or attached to) the terminals of the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234. Accordingly, the first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224may not return (or may return) the voltages received from the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234to the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234.

The SSD backplane200may be powered on or powered off in response to the power signals PS from the baseboard130. When the SSD backplane200is powered on, the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234may supply a power to the SSDs of the first SSD slot211, the second SSD slot212, the third SSD slot213, and the fourth SSD slot214. When the SSD backplane200is powered off, the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234may block the power from being supplied to the SSDs of the first SSD slot211, the second SSD slot212, the third SSD slot213, and the fourth SSD slot214.

When the SSD backplane200is powered off, the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234may monitor whether voltages are transferred from the first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224. When the voltages are not transferred (or are transferred), the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234may maintain power interruption. When the voltages are transferred (or are not transferred), the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234may supply the power to the SSDs of the first SSD slot211, the second SSD slot212, the third SSD slot213, and the fourth SSD slot214.

Each of the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234may include a capacitor “C” that stores power. When an ambient temperature is sufficiently high that a voltage is transferred from one of the first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224(or that a voltage is not transferred therefrom), the corresponding regulator may supply a power to the corresponding SSD. In the case where a voltage is not transferred (or is transferred) from one bi-metal as an ambient temperature decreases before the retention recovery operation of the corresponding SSD is completed, the corresponding regulator may block power from being supplied to the corresponding SSD. In this case, the corresponding SSD may complete the retention recovery operation by using a power stored in the capacitor “C”. For example, the capacitor “C” may be connected with an output terminal of the corresponding regulator, from which the power PWR is output.

In an example embodiment, the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234may block or supply a power in response to a common power signal PS. In another implementation, the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234may independently block or supply a power in response to respectively different power signals PS.

The first regulator231, the second regulator232, the third regulator233, and the fourth regulator234may be powered on or powered off in response to the power signals PS from the first CPU131, the second CPU132, or the BMC137of the baseboard130. The first regulator231, the second regulator232, the third regulator233, and the fourth regulator234may be integrated into one regulator.

In an example embodiment, the first regulator231, the second regulator232, the third regulator233, and the fourth regulator234may be replaced with power switches that operate in response to the power signals PS and the voltages from the first bi-metal221, the second bi-metal222, the third bi-metal223, and the fourth bi-metal224.

FIG.4illustrates a first example of an operating method of the electronic device100according to an example embodiment. An operating method for an SSD installed in one SSD slot (e.g., the first SSD slot211) is illustrated inFIG.4.

Referring toFIGS.1,3, and4, in operation S110, the baseboard130may request a power-off from an SSD backplane (e.g.,140) through the power signal PS. The power signal PS may be transferred based on one of various communication interfaces such as PCIe, NVMe, and IPMI.

In operation S120, the first SSD backplane140may block power from being supplied to the SSDs so as to be powered off. While the SSDs are powered off, in operation S130, a regulator (e.g., the first regulator231) may supply a voltage to the first bi-metal221disposed adjacent to the first SSD slot211, and may determine whether the voltage is transferred or is not transferred from the first bi-metal221.

When a voltage is not transferred (or is transferred) from the first bi-metal221and thus a bi-metal signal is deactivated, the first regulator231may maintain power interruption. When a voltage is transferred (or is not transferred) from the first bi-metal221and thus the bi-metal signal is activated, operation S140is performed. In operation S140, the first regulator231may supply a power to the SSD of the first SSD slot211so as to be powered on.

In operation S150, in response to that the SSDs are powered on, the SSDs may perform communication initialization with the baseboard130. The communication initialization may be the following initialization for performing communication of the signals SIG between the baseboard130and the SSDs: timing adjustment, termination resistance adjustment, and signal intensity adjustment. Before or in parallel with the communication initialization, the SSDs may perform internal initialization. The internal initialization may be the following initialization for internal operations of the SSDs: loading firmware and setting internal voltage level.

In operation S160, the powered-on SSDs may perform the retention recovery operation as a background operation. For example, the retention recovery operation may include a detection operation of detecting retention-reduced data through a read operation, and a reclaim operation of again writing the retention-reduced data at any other location. The SSDs may schedule the retention recovery operation in compliance with an internally given algorithm, and may perform the retention recovery operation depending on the schedule.

The operations ofFIG.4may be performed in parallel on respective SSDs belonging to an SSD backplane that is powered off. As a temperature decreases while the background operation is performed, a power may be blocked. In this case, each SSD may perform the retention recovery operation by using the power charged in the capacitor “C”. In the case where a power is continuously supplied as a high temperature is maintained, the SSDs may perform the retention recovery operation based on the internally given algorithm two or more times.

In an example embodiment, each SSD may include a temperature sensor. Each SSD may schedule the retention recovery operation in compliance with the internally given algorithm based on the temperature sensed by the temperature sensor, and may perform the retention recovery operation depending on the schedule.

FIG.5illustrates a second example of an operating method of the electronic device100according to an example embodiment.

Referring toFIGS.1,3, and5, operation S210, operation S220, operation S230, and operation S240are performed in the same scheme as operation S110, operation S120, operation S130, and operation S140ofFIG.4. Thus, additional description will be omitted to avoid redundancy.

After a regulator (e.g., the first regulator231) powers on SSDs installed in the first SSD slot211, the baseboard130may not perform communication initialization with the SSDs. In an example embodiment, even though the communication initialization is requested by the SSDs (or an SSD backplane) powered off by the baseboard130or a procedure for communication initialization is performed, the baseboard130may ignore the request or procedure for communication initialization.

In operation S250, in response to no communication initialization, the SSDs may perform the retention recovery operation. The SSDs may identify temporary power-on due to an increase of temperature in response to no communication initialization. Immediately after being powered on, the SSDs may perform the retention recovery operation and may quickly detect the reduction of retention, thus quickly preventing a data loss due to the reduction of retention.

In another example embodiment, even though the communication initialization is not performed, each SSD may schedule the retention recovery operation as a background operation in compliance with the internally given algorithm, and may perform the scheduled retention recovery operation.

FIG.6illustrates a third example of an operating method of the electronic device100according to an example embodiment.

Referring toFIGS.1,3, and6, operation S310, operation S320, operation S330, operation S340, and operation S350are performed in the same scheme as operation S110, operation S120, operation S130, operation S140, and operation S150ofFIG.4. Thus, additional description will be omitted to avoid redundancy.

In response to the communication initialization in operation S350, the first CPU131, the second CPU132, or the BMC137of the baseboard130may recognize that SSDs installed in an SSD slot (e.g., the first SSD slot211) are powered on. In response to that the SSDs of the powered-off SSD backplane (e.g., the first SSD backplane140) are powered on, the baseboard130may recognize that the SSDs are powered on due to an increase of temperature.

In operation S360, the baseboard130may request the retention recovery operation from the powered-on SSDs. The baseboard130may request the retention recovery operation from the powered-on SSDs through the signals SIG. In operation S370, the powered-on SSDs may perform the retention recovery operation in response to the request from the baseboard130.

In the above description, the baseboard130recognizes an increase of temperature through the communication initialization (operation S350). However, a means by which the baseboard130recognizes an increase of temperature is not limited. For example, in response to that the bi-metal signal is activated (operation S330), a regulator (e.g., the first regulator231) may notify an increase of temperature of the baseboard130through a separate signal line. The separate signal line may be based on one of various communication interfaces such as PCIe, NVMe, and IPMI.

When the baseboard130transfers a request for retention recovery in operation S360, the baseboard130may transfer additional information to the powered-on SSDs. For example, the baseboard130may provide the powered-on SSDs with environment information, such as temperature information, and additional information influencing the retention of the powered-on SSDs. The powered-on SSDs may perform the retention recovery operation based on the information from the baseboard130.

In an example embodiment, as an increase of temperature is recognized, in operation S395, the baseboard130may allow the cooling control board170to reinforce cooling of the coolers180. In an example embodiment, a reference temperature for reinforcing cooling may be different from a reference temperature for powering on SSDs. The reference temperature for cooling and the reference temperature for power-on may be differently implemented by providing a bi-metal corresponding to the reference temperature for cooling and a bi-metal corresponding to the reference temperature for power-on separately. The reference temperature for cooling may be lower or higher than the reference temperature for power-on.

FIG.7illustrates an SSD backplane300according to a second example embodiment.

The SSD backplane300may correspond to the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160ofFIG.1. Referring toFIGS.1and7, the SSD backplane300may include first through fourth SSD slots311,312,313, and314. SSDs installed in the first through fourth SSD slots311,312,313, and314may exchange the signals SIG with the baseboard130through signal lines.

Compared toFIG.3, one bi-metal321or322may be disposed adjacent to two SSD slots311and312or313and314. Also, one regulator331or332may supply the power PWR to two SSD slots311and312or313and314, may supply a voltage to one bi-metal321or322, and may determine whether a voltage is received from one bi-metal321or322.

Thus, when a temperature increases in a state where the SSD backplane300is in a power-off state, two or more SSDs may be powered on together. Each of the powered-on SSDs may perform the retention recovery operation. Afterwards, when a temperature again decreases, the two or more SSDs may be powered off together. When the retention recovery operation of at least one of the two or more SSDs is not completed, the at least one SSD may continue the retention recovery operation by using a power stored in the capacitor “C”.

FIG.8illustrates an SSD backplane400according to a third example embodiment. The SSD backplane400may correspond to the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160ofFIG.1.

Referring toFIGS.1and8, the SSD backplane400may include first through fourth SSD slots411,412,413, and414. However, the number of slots is not limited. SSDs may be installed in each of the first SSD slot411, the second SSD slot412, the third SSD slot413, and the fourth SSD slot414. The SSDs may exchange the signals SIG with the baseboard130through signal lines.

The SSD backplane400may include first through fourth sensors421,422,423, and424respectively corresponding to the first through fourth SSD slots411,412,413, and414, and may include first through fourth regulators431,432,433, and434respectively corresponding to the first through fourth SSD slots411,412,413, and414. The first sensor421, the second sensor422, the third sensor423, and the fourth sensor424may be temperature sensors. Each of the first sensor421, the second sensor422, the third sensor423, and the fourth sensor424may periodically sense an ambient temperature, and may transfer information about the sensed temperature to the baseboard130.

For example, each of the first sensor421, the second sensor422, the third sensor423, and the fourth sensor424may transfer temperature information to the BMC137of the baseboard130based on the communication interface of the IPMI. The temperature information may be transferred to the BMC137through a sensor data repository (SDR) field of a message of the IPMI. In an example embodiment, the first sensor421, the second sensor422, the third sensor423, and the fourth sensor424may be sensors disposed at the SSD backplane400from among the sensors190ofFIG.1.

The SSD backplane400may be powered on or powered off in response to the power signals PS from the baseboard130. When the SSD backplane400is powered on, the first regulator431, the second regulator432, the third regulator433, and the fourth regulator434may supply a power to the SSDs of the first SSD slot411, the second SSD slot412, the third SSD slot413, and the fourth SSD slot414. When the SSD backplane400is powered off, the first regulator431, the second regulator432, the third regulator433, and the fourth regulator434may block the power from being supplied to the SSDs of the first SSD slot411, the second SSD slot412, the third SSD slot413, and the fourth SSD slot414.

The BMC137may monitor whether temperatures of the SSDs are greater than a critical value, based on the temperature information transferred from the first sensor421, the second sensor422, the third sensor423, and the fourth sensor424. When the temperatures of the SSDs are equal to smaller than the critical value, the SSDs of the powered-off SSD backplane400may maintain a power-off state. When a temperature of a specific SSD is greater than the critical value, the first CPU131, the second CPU132, or the BMC137of the baseboard130may control the corresponding regulator through the corresponding one of the power signals PS such that a power is supplied to the specific SSD.

Each of the first regulator431, the second regulator432, the third regulator433, and the fourth regulator434may include the capacitor “C” to store power. When an ambient temperature is higher than the critical value, the corresponding regulator may supply a power to the corresponding SSD. In the case where an ambient temperature decreases before the retention recovery operation of the corresponding SSD is completed, the corresponding regulator may block power from being supplied to the corresponding SSD. In this case, the corresponding SSD may complete the retention recovery operation by using a power stored in the capacitor “C”. Thus, the capacitor “C” may be connected with an output terminal of the corresponding regulator, from which the power PWR is output.

In an example embodiment, the first regulator431, the second regulator432, the third regulator433, and the fourth regulator434may be replaced with power switches operating in response to the power signals PS.

FIG.9illustrates a fourth example of an operating method of the electronic device100according to an example embodiment. In an example embodiment, an operating method for an SSD installed in one SSD slot (e.g., the first SSD slot411) is illustrated inFIG.9.

Referring toFIGS.1,8, and9, in operation S410, the baseboard130may request a power-off from an SSD backplane (e.g., the first SSD backplane140) through the power signal PS. The power signal PS may be transferred based on one of various communication interfaces such as PCIe, NVMe, and IPMI.

In operation S420, the first SSD backplane140may block power from being supplied to the SSDs so as to be powered off. While the SSDs are powered off, in operation S430, a sensor (e.g., the first sensor421) installed in the SSD backplane400may periodically transfer temperature information to the BMC137of the baseboard130. The BMC137may receive the temperature information, and may log the received temperature information.

In operation S440, the first CPU131, the second CPU132, or the BMC137of the baseboard130may determine whether a temperature of an SSD is greater than the critical value. When the temperature of the SSD is not greater than the critical value, the baseboard130may not perform a separate control on the SSD backplane400.

When the temperature of the SSD is greater than the critical value, in operation S450, the baseboard130may request a power-on of the SSD from the SSD backplane400. The power-on request may be transferred by using the power signal PS. In operation S460, the first regulator431may supply a power to the SSDs of the first SSD slot411so as to be powered on.

In operation S470, in response to the SSDs being powered on, the SSDs may perform communication initialization with the baseboard130. Before, after, or in parallel with the communication initialization, the SSDs may perform internal initialization.

In operation S480, the powered-on SSDs may perform the retention recovery operation as a background operation. For example, the retention recovery operation may include a detection operation of detecting retention-reduced data through a read operation, and a reclaim operation of again writing the retention-reduced data at any other location. The SSDs may schedule the retention recovery operation based on an internally given algorithm, and may perform the retention recovery operation depending on the schedule.

The operations ofFIG.9may be performed in parallel on respective SSDs belonging to an SSD backplane being powered off. As a temperature decreases while the background operation is performed, a power may be blocked. In this case, each SSD may perform the retention recovery operation by using the power charged in the capacitor “C”. In the case where a power is continuously supplied as a high temperature is maintained, the SSDs may perform the retention recovery operation based on the internally given algorithm two or more times.

In an example embodiment, each SSD may include a temperature sensor. Each SSD may schedule the retention recovery operation in compliance with the internally given algorithm based on the temperature sensed by the temperature sensor, and may perform the retention recovery operation depending on the schedule.

In an example embodiment, as an increase of temperature is recognized, in operation S495, the baseboard130may allow the cooling control board170to reinforce cooling of the coolers180. In an example embodiment, a reference temperature for reinforcing cooling may be different from a reference temperature for powering on SSDs. The baseboard130may compare a temperature of an SSD with two different critical values such that the reference temperature for cooling and the reference temperature for power-on are differently implemented. The reference temperature for cooling may be lower or higher than the reference temperature for power-on.

FIG.10illustrates a fifth example of an operating method of the electronic device100according to an example embodiment. Referring toFIGS.1,8, and10, operation S510, operation S520, operation S530, operation S540, operation S550, operation S560, and operation S595are performed to be identical to operation S410, operation S420, operation S430, operation S440, operation S450, operation S460, and operation S495ofFIG.9. Thus, additional description will be omitted to avoid redundancy.

After a regulator (e.g., the first regulator431) powers off SSDs installed in the first SSD slot411, the baseboard130may not perform communication initialization with the SSDs. In an example embodiment, even though the communication initialization is requested by the SSDs powered off due to an increase of temperature or when a procedure for communication initialization is performed, the baseboard130may ignore the request or procedure for communication initialization.

In operation S570, in response to no communication initialization, the SSDs may perform the retention recovery operation. The SSDs may identify temporary power-on due to an increase of temperature in response to no communication initialization. Immediately after being powered on, the SSDs may perform the retention recovery operation and may quickly detect the reduction of retention, thus quickly preventing a data loss due to the reduction of retention.

In another example embodiment, even though the communication initialization is not performed, each SSD may schedule the retention recovery operation as a background operation in compliance with the internally given algorithm, and may perform the scheduled retention recovery operation.

FIG.11illustrates a sixth example of an operating method of the electronic device100according to an example embodiment. Referring toFIGS.1,8, and11, operation S610, operation S620, operation S630, operation S640, operation S650, operation S660, operation S670, and operation S695are performed to be identical to operation S410, operation S420, operation S430, operation S440, operation S450, operation S460, operation S470, and operation S495ofFIG.9. Thus, additional description will be omitted to avoid redundancy.

In operation S680, the baseboard130may request the retention recovery operation from the powered-on SSDs. The baseboard130may request the retention recovery operation from the powered-on SSDs through the signals SIG. In operation S690, the powered-on SSDs may perform the retention recovery operation in response to the request from the baseboard130.

When the baseboard130transfers a request for retention recovery in operation S680, the baseboard130may transfer additional information to the powered-on SSDs. For example, the baseboard130may provide the powered-on SSDs with environment information, such as temperature information, and additional information influencing the retention of the powered-on SSDs. The powered-on SSDs may perform the retention recovery operation based on the information from the baseboard130.

FIG.12illustrates a seventh example of an operating method of the electronic device100according to an example embodiment. Referring toFIGS.1,8, and12, operation S710, operation S720, operation S730, operation S750, operation S760, operation S770, operation S780, and operation S795are performed to be identical to operation S410, operation S420, operation S430, operation S450, operation S460, operation S470, operation S480, and operation S495ofFIG.9. Thus, additional description will be omitted to avoid redundancy.

Before powering off the SSD backplane400, in operation S701, the first CPU131, the second CPU132, or the BMC137of the baseboard130may request wear information from an SSD. In operation S702, the SSD may transfer the wear information to the baseboard130. Afterwards, the baseboard130may perform a power-off in operation S710.

The wear information may be information indicating that the SSD is worn due to operations such as a program operation and an erase operation. As the wear progresses, a retention characteristic of the SSD may decrease. Before powering off the SSD, the baseboard130may collect wear information of the SSD and may adjust a critical value based on the wear information. Afterwards, when it is determined in operation S740that a temperature is greater than the adjusted critical value, the baseboard130may request a power-on of the SSD (operation S750).

In an example embodiment, the wear information may include SMART (Self-Monitoring Analysis and Reporting Technology) information of the SSD. The wear information may be collected based on the IPMI. In detail, the wear information may be collected by using an SDR field of a message of the IPMI.

In an example embodiment, a configuration to collect wear information in operation S701and operation S702and a configuration to use an adjusted critical value in operation S740may also be applied to the embodiments ofFIGS.10and11.

FIG.13illustrates an example of program/erase (PE) cycles and adjusted critical values as an example of wear information. Referring toFIGS.1and13, the critical value may be 80 when the number of PE cycles are equal to or less than 0.1K, may be 70 when the number of PE cycles exceeds 0.1K and is equal to or less than 1K, may be 60 when the number of PE cycles exceeds 1K and is equal to or less than 3K, may be 50 when the number of PE cycles exceeds 3K and is equal to or less than 5K, may be 40 when the number of PE cycles exceeds 5K and is equal to or less than 7K, and may be 30 when the number of PE cycles exceeds 7K and is equal to or less than 10K. As the number of PE cycles increases, a wear level of an SSD may increase, and a critical value may decrease.

The baseboard130according to an example embodiment may further compare a temperature with a cautious value, which is smaller than the critical value. The cautious value may be 70 when the number of PE cycles are equal to or less than 0.1K, may be 60 when the number of PE cycles exceeds 0.1K and is equal to or less than 1K, may be 50 when the number of PE cycles exceeds 1K and is equal to or less than 3K, may be 40 when the number of PE cycles exceeds 3K and is equal to or less than 5K, may be 30 when the number of PE cycles exceeds 5K and is equal to or less than 7K, and may be 20 when the number of PE cycles exceeds 7K and is equal to or less than 10K.

In an example embodiment, when a temperature of an SSD is equal to or less than a critical value, and an amount of time when the temperature of the SSD is greater than the cautious value exceeds a given time period, the baseboard130may power on the SSD to instruct the retention recovery operation of the SSD (or to request the retention recovery operation from the SSD). Accordingly, there may be detected the reduction of retention of an SSD occurring when a temperature of the SSD is equal to or less than the critical value but the SSD is left alone at a temperature close to the critical value for a long time, and a data loss due to the reduction of retention may be prevented.

FIG.14illustrates an eighth example of an operating method of the electronic device100according to an example embodiment.

Referring toFIGS.1,8, and14, in operation S810, the baseboard130may receive temperature information from the first sensor421adjacent to one SSD slot (e.g., the first SSD slot411) of the SSD backplane400.

In operation S820, the baseboard130may determine whether a temperature of an SSD belongs to a range of the cautious value. For example, the baseboard130may determine whether the temperature of the SSD is equal to or less than the critical value and is greater than the cautious value. When the temperature of the SSD belongs to the range of the cautious value, in operation S830, the baseboard130may increase a count of the SSD.

In operation S840, the baseboard130may determine whether the count of the SSD is greater than a threshold value. When the count of the SSD is not greater than the threshold value, the baseboard130may not perform a separate control on the SSD. When the count of the SSD is greater than the threshold value, in operation S850, the baseboard130may request a power-on of the SSD. In operation S860, the baseboard130may reset the count of the SSD.

Operation S850may correspond to operation S450ofFIG.9, operation S550ofFIG.10, operation S650ofFIG.11, and operation S750ofFIG.12. Operations following operation S450ofFIG.9, operations following operation S550ofFIG.10, operations following operation S650ofFIG.11, or operations following operation S750ofFIG.12may be performed next to operation S850.

When it is determined in operation S820that the temperature of the SSD does not belong to the range of the cautious value, in operation S870, the baseboard130may determine whether the temperature of the SSD belongs to a range of the critical value. For example, the baseboard130may determine whether the temperature of the SSD is greater than the critical value. When the temperature is greater than the critical value, operation S850may be performed.

When the temperature is not greater than the critical value, the baseboard130may not perform a separate control on the SSD. When the temperature is greater than the critical value, in operation S850, the baseboard130may request a power-on of the SSD. In operation S860, the baseboard130may reset the count of the SSD.

The operations ofFIG.14may be performed whenever temperature information is received from a sensor (e.g., the first sensor421) corresponding to one SSD slot (e.g., the first SSD slot411) of the SSD backplane400. In another implementation, the first sensor421may transfer temperature information to the baseboard130based on a first period. The baseboard130may perform the operations ofFIG.14by using a lately transferred temperature, based on a second period. The second period may be longer than the first period.

FIG.15illustrates an SSD backplane500according to a fourth example embodiment. The SSD backplane500may correspond to the first SSD backplane140, the second SSD backplane150, and the third SSD backplane160ofFIG.1.

Referring toFIGS.1and15, the SSD backplane500may include first through fourth SSD slots511,512,513, and514. SSDs installed in the first through fourth SSD slots511,512,513, and514may exchange the signals SIG with the baseboard130through signal lines.

Compared toFIG.8, one sensor521or522may be disposed adjacent to two SSD slots511and512or513and514. Also, one regulator531or532may supply the power PWR to two SSD slots511and512or513and514.

Thus, when a temperature increases in a state where the SSD backplane500is in a power-off state, two or more SSDs may be powered on together. Each of the powered-on SSDs may perform the retention recovery operation. Afterwards, when a temperature again decreases, the two or more SSDs may be powered off together. When the retention recovery operation of at least one of the two or more SSDs is not completed, the at least one SSD may continue the retention recovery operation by using a power stored in the capacitor “C”.

FIG.16illustrates an SSD600according to an example embodiment.

Referring toFIG.16, the SSD600may include a nonvolatile memory device610, a memory controller620, and a buffer memory630. The nonvolatile memory device610may include a plurality of memory cells. Each of the plurality of memory cells may store two or more bits. For example, the nonvolatile memory device610may include at least one of various nonvolatile memory devices such as a flash memory device, a phase change memory device, a ferroelectric memory device, a magnetic memory device, and a resistive memory device.

The memory controller620may receive various requests for writing data in the nonvolatile memory device610or reading data from the nonvolatile memory device610from the electronic device100. The memory controller620may store (or buffer) user data for communication with the electronic device100in the buffer memory630, and may store meta data for managing the SSD600in the buffer memory630.

The memory controller620may access the nonvolatile memory device610through a first channel CH1and a second channel CH2. For example, the memory controller620may transmit a command and an address to the nonvolatile memory device610through the first channel CH1. The memory controller620may exchange data with the nonvolatile memory device610through the first channel CH1.

The memory controller620may transmit a first control signal to the nonvolatile memory device610through the second channel CH2. The memory controller620may receive a second control signal from the nonvolatile memory device610through the second channel CH2.

In an example embodiment, the memory controller620may be configured to control two or more nonvolatile memory devices. The memory controller620may provide first different channels and second different channels for each of two or more nonvolatile memory devices.

In another example embodiment, the memory controller620may share one first channel with respect to two or more nonvolatile memory devices. The memory controller620may share a portion of the second channel CH2with regard to two or more nonvolatile memory devices, and may separately provide the remaining portion thereof.

The buffer memory630may include a random access memory. For example, the buffer memory630may include at least one of a dynamic random access memory, a phase change random access memory, a ferroelectric random access memory, a magnetic random access memory, or a resistive random access memory.

The memory controller620may include a bus621, a host interface622, an internal buffer623, a processor624, a buffer controller626, a memory manager627, and an error correction code (ECC) block628.

The bus621may provide communication channels between components in the memory controller620. The host interface622may receive various requests from the electronic device100, and may parse the received requests. The host interface622may store the parsed requests to the internal buffer623.

The host interface622may transmit various responses to the electronic device100. The host interface622may exchange signals with the electronic device100in compliance with a given communication protocol. The internal buffer623may include a random access memory. For example, the internal buffer623may include a static random access memory or a dynamic random access memory.

The processor624may drive an operating system or firmware for driving the memory controller620. The processor624may read the parsed requests stored in the internal buffer623, and may generate commands and addresses for controlling the nonvolatile memory device610. The processor624may transfer the generated commands and addresses to the memory manager627.

The processor624may store various meta information for managing the SSD600to the internal buffer623. The processor624may access the buffer memory630through the buffer controller626. The processor624may control the buffer controller626and the memory manager627such that the user data stored in the buffer memory630are transmitted to the nonvolatile memory device610.

The processor624may control the host interface622and the buffer controller626such that the data stored in the buffer memory630are transmitted to the electronic device100. The processor624may control the buffer controller626and the memory manager627such that data received from the nonvolatile memory device610are stored to the buffer memory630. The processor624may control the host interface622and the buffer controller626such that data received from the electronic device100are stored to the buffer memory630.

The processor624may include a retention controller (RC)625. The retention controller625may control the retention recovery operation. The retention recovery operation may include detection read and reclaim. The retention controller625may perform the detection read of detecting whether the retention of data written in the nonvolatile memory device610is reduced. For example, the retention controller625may schedule the detection read in compliance with an internally given algorithm and may perform the scheduled detection read.

In an example embodiment, the retention controller625may schedule the detection read based on temperature information obtained by a sensor629, management information of the nonvolatile memory device610including wear information included in metadata, and environment information capable of being transferred from the electronic device100. When the reduction of retention is detected in the detection read, the retention controller625may schedule a reclaim associated with the corresponding data. The reclaim may include general read of reading the corresponding data and general write of writing the read data in any other storage space. The detection read may be performed in a manner different from that of the general read.

In power-on, the retention controller625may detect whether power-on is made by the electronic device100due to an increase of temperature. For example, when communication initialization is not performed, the retention controller625may recognize that the power-on is made due to an increase of temperature. In this case, the retention controller625may perform the detection read of the retention recovery operation immediately. In another implementation, in response to a request for retention recovery received from the electronic device100, the retention controller625may perform the detection read of the retention recovery operation.

Under control of the processor624, the buffer controller626may write data in the buffer memory630or may read data from the buffer memory630. The memory manager627may communicate with the nonvolatile memory device610through the first channel CH1and the second channel CH2under control of the processor624.

The error correction code block628may perform error correction encoding on data to be transmitted to the nonvolatile memory device610by using an error correction code ECC. The error correction code block628may perform error correction decoding on data received from the nonvolatile memory device610by using the error correction code ECC.

In an example embodiment, the SSD600may not include the buffer memory630and the buffer controller626. When the buffer memory630and the buffer controller626are not included in the SSD600, the above functions of the buffer memory630and the buffer controller626may be performed by the internal buffer623.

In the above embodiments, components are described by using the terms “first”, “second”, “third”, and the like. However, the terms “first”, “second”, “third”, and the like may be used to distinguish components from each other and conc. For example, the terms “first”, “second”, “third”, and the like do not involve an order or a numerical meaning of any form.

In the above embodiments, components are described by using blocks. The blocks may be implemented with various hardware devices, such as an integrated circuit, an application specific IC (ASIC), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as an application, or a combination of a hardware device and software. Also, the blocks may include circuits implemented with semiconductor elements in an integrated circuit or circuits enrolled as intellectual property (IP).

By way of summation and review, a characteristic that data stored in a nonvolatile memory is retained is called “retention”. A flash memory may store data in the form of a threshold voltage, and a phase-change memory, a ferroelectric memory, a magnetic memory, and a resistive memory may store data in the form of a resistance value. When a threshold voltage or a resistance value is retained within an intended range in a write operation, the retention may be maintained. When the threshold voltage or the resistance value is out of the intended range over time, the retention may be reduced.

A solid state drive may detect the reduction of retention, and may perform a retention recovery operation of recovering the reduced retention. Through the retention recovery operation, the solid state drive may prevent data stored in the nonvolatile memory from being lost due to the reduction of retention. However, in the case where the solid state drive is left alone in a power-off state, the retention recovery operation may not be performed. This may mean that data stored in the nonvolatile memory is lost due to the reduction of retention.

According to an example embodiment, a solid state drive that is in a high-temperature state where the reduction of retention is accelerated may be powered on, and the powered-on solid state drive may perform a retention recovery operation. Accordingly, a solid state drive preventing a data loss due to the reduction of retention, an electronic device including the solid state drive, and a method of managing the solid state drive are provided.

As described above, embodiments may provide a solid state drive that avoids a retention loss due to an external temperature, an electronic device including the solid state drive, and a method of managing the solid state drive. Embodiments may provide a solid state drive preventing a data loss due to the reduction of retention while left alone in a power-off state, an electronic device including the solid state drive, and a method of managing the solid state drive.