Semiconductor component and method of manufacture

In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead, a second lead, and a third lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

TECHNICAL FIELD

The present invention relates, in general, to electronics and, more particularly, to semiconductor structures thereof, and methods of forming semiconductor devices.

BACKGROUND

In the past, semiconductor manufacturers have used a combination of silicon semiconductor materials and III-N semiconductor materials to manufacture cascoded devices, such as a normally-on III-N depletion mode HEMT cascoded with a silicon device. Using this combination of materials helps achieve a normally-off state using a III-N depletion mode device that is normally-on. In cascoded devices configured as switches, the silicon device often operates in avalanche mode due to high leakage currents of the III-N device that is operating under a high drain bias. In the avalanche operating mode, the gate of the III-N device is under a large stress in which the absolute gate to source voltage exceeds the devices pinch-off voltage. Hard stress conditions such as operating the silicon device in the avalanche mode degrades device reliability, lowers the breakdown voltage, and increases leakage currents. Cascoded semiconductor devices have been described in U.S. Patent Application Publication Number 2013/0088280 A1 by Rakesh K. Lal et al. and published on Apr. 11, 2013.

After manufacturing cascoded devices from different semiconductor substrate materials, semiconductor component manufacturers typically protect the silicon device and the depletion mode devices in separate packages and connect the devices in the separate packages together via leadframe leads to form a cascoded device. A drawback with this approach is that increasing the number of packages increases the cost of a cascoded semiconductor component and degrades the performance of the cascoded devices because of increased parasitics such as parasitic capacitance and parasitic inductance.

Accordingly, it would be advantageous to have a cascoded semiconductor device and a method for manufacturing the cascoded semiconductor device. It would be of further advantage for the structure and method to be cost efficient to implement.

For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain n-channel or p-channel devices, or certain n-type or p-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action and the initial action. The use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten per cent (10%) (and up to twenty per cent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of being exactly as described.

DETAILED DESCRIPTION

FIG. 1is a top view of a semiconductor chip10suitable for use in manufacturing a semiconductor component in accordance with an embodiment of the present invention. Semiconductor chip10has a top surface12and a bottom surface14(shown inFIGS. 6 and 7), wherein a gate bond pad16is formed on or from a portion of top surface12, a source bond pad18is formed on or from another portion of top surface12, and a drain bond pad20formed on or from another portion of top surface12. In accordance with an embodiment, semiconductor chip10is a rectangular shaped silicon based semiconductor material, wherein the semiconductor material may be referred to as a body of semiconductor material. Gate bond pad16is a square shaped electrically conductive structure that is electrically connected to a drain region of a semiconductor device and formed in a corner of the rectangular shaped silicon based semiconductor material. Source bond pad18is an electrically conductive material that has a rectangular shape with two opposing sides, wherein a notch22is formed in a corner of the source bond pad18. Gate bond pad16is formed in the region of notch22. On the side of source bond pad18opposite the side from which notch22has been formed a rectangularly shaped notch24is formed, leaving rectangularly shaped extensions26and28. Rectangularly shaped drain bond pad20is formed in the region of notch24, i.e., between extensions26and28.

FIG. 2is a top view of a semiconductor chip50suitable for use in manufacturing a semiconductor component in accordance with an embodiment of the present invention. Semiconductor chip50has a top surface52and a bottom surface54(shown in at leastFIGS. 20 and 21), wherein a gate bond pad56is formed on or from a portion of top surface52, a source bond pad58is formed on or from another portion of top surface52, and a drain bond pad60is formed on or from another portion of top surface52. In accordance with an embodiment, semiconductor chip50is a rectangular shaped silicon based semiconductor material, wherein the semiconductor material may be referred to as a body of semiconductor material. Gate bond pad56is a square shaped electrically conductive structure that is formed in a corner of the rectangular shaped silicon based semiconductor material. Source bond pad58is an electrically conductive material that has a rectangular shape with two opposing sides, wherein a notch62is formed in a side of the source bond pad58and an extension64extends from a side of source bond pad58that is opposite the side of source bond pad58from which gate bond pad56is formed. Gate bond pad56is formed in the region of notch62. A notch66is formed in the side of source bond pad58that is opposite the side from which notch62is formed. Extension64remains after notch66is formed. Rectangularly shaped drain bond pad60is formed in notch66.

FIG. 3is a top view of a semiconductor chip70suitable for use in manufacturing a semiconductor component in accordance with an embodiment of the present invention. Semiconductor chip70has a top surface72and a bottom surface74(shown in at leastFIGS. 6 and 7), wherein gate bond pads76A and76B are formed on or from a portion of top surface72, a source bond pad78is formed on or from another portion of top surface72, and a drain bond pad80is formed on or from another portion of top surface72. In accordance with an embodiment, semiconductor chip70is fabricated from a compound semiconductor material such as, for example, a III-nitride semiconductor material. Thus, semiconductor chip70may be referred to as a III-nitride semiconductor chip, i.e., the substrate material of III-nitride semiconductor chip70comprises a III-nitride material such as, for example, gallium nitride. A III-nitride semiconductor material may be referred to as a III-N semiconductor material, a III-nitride based semiconductor material, a III-N based semiconductor material, or the like. This material may be referred to as a body of semiconductor material. A semiconductor chip such as, for example, semiconductor chip70, may be referred to as a semiconductor die.

FIG. 4is a top view of a semiconductor chip84suitable for use in manufacturing a semiconductor component in accordance with an embodiment of the present invention. Semiconductor chip84has a top surface85and a bottom surface87(shown in at leastFIGS. 20 and 21), wherein a gate bond pad86is formed on or from a portion of top surface85, a source bond pad88is formed on or from another portion of top surface85, and a drain bond pad90formed on or from another portion of top surface85. In accordance with an embodiment, semiconductor chip84is fabricated from a compound semiconductor material such as, for example, a III-nitride semiconductor material. Thus, semiconductor chip84may be referred to as a III-nitride semiconductor chip, i.e., the substrate material of III-nitride semiconductor chip84comprises a III-nitride material such as, for example, gallium nitride. A III-nitride semiconductor material may be referred to as a III-N semiconductor material, a III-nitride based semiconductor material, a III-N based semiconductor material, or the like. This material may be referred to as a body of semiconductor material. A semiconductor chip such as, for example, semiconductor chip84, may be referred to as a semiconductor die.

FIG. 5is a circuit schematic81of a semiconductor component in a cascode configuration. The semiconductor component includes transistors89and83, where transistor89has a gate electrode89G, a source electrode89S, and a drain electrode89D and transistor83has a gate electrode83G, a source electrode83S, a drain electrode83D, and a body/substrate terminal83B. Drain electrode89D is electrically connected to source electrode83S and source electrode89S is electrically connected to gate electrode83G. Drain electrode83D may be coupled for receiving a first source of operating potential such as, for example, a potential VDD, for the cascoded semiconductor component of circuit schematic81, gate electrode89G serves as an input terminal for the cascoded semiconductor component of circuit schematic81, and source electrode89S is coupled for receiving a second source of operating potential such as, for example potential VSS. By way of example, potential VSSis ground. It should be noted that the substrate of III-N transistor83is floating, thus semiconductor component81may be referred to as being in a floating configuration or substrate floating configuration.

FIG. 6is a circuit schematic95of a semiconductor component in a cascode configuration. The semiconductor component includes transistors89and83, where transistor89has a gate electrode89G, a source electrode89S, and a drain electrode89D and transistor83has a gate electrode83G, a source electrode83S, a drain electrode83D, and a body/substrate terminal83B. Drain electrode89D is electrically connected to source electrode83S and source electrode89S is electrically connected to gate electrode83G. Drain electrode83D may be coupled for receiving a first source of operating potential such as, for example, potential VDD, for the cascoded semiconductor component of circuit schematic95, gate electrode89G serves as an input terminal for the cascoded semiconductor component of circuit schematic95, and source electrode89S is coupled for the receiving a second source of operating potential such as, for example, a potential VSS. By way of example, potential VSSis a ground potential. Substrate terminal83B of transistor83is electrically connected to source electrode83S of transistor83and to the drain electrode of transistor83. Thus, the substrate of transistor83is coupled to the same potential as source electrode83S of transistor83or drain electrode89D of transistor89.

FIG. 7is a circuit schematic97of a semiconductor component in a cascode configuration. The semiconductor component includes transistors89and83, where transistor89has a gate electrode89G, a source electrode89S, and a drain electrode89D and transistor83has a gate electrode83G, a source electrode83S, a drain electrode83D, and a body/substrate terminal83B. Drain electrode89D of transistor89is electrically connected to source electrode83S of transistor83and source electrode89S of transistor89is electrically connected to gate electrode83G of transistor83. Drain electrode83D may be coupled for receiving a first source of operating potential such as, for example potential VDD, for the cascoded semiconductor component of circuit schematic97, gate electrode89G serves as an input terminal for the cascoded semiconductor component of circuit schematic97, and source electrode89S is coupled for receiving a second source of operating potential such as for example potential VSS. By way of example potential VSSis a ground potential. Substrate terminal83B of transistor83is electrically connected to source electrode89S of transistor89. Thus, the substrate of transistor83is coupled to the same potential as source electrode89S of transistor89.

FIG. 8is a top view of a semiconductor component100comprising a support102to which a semiconductor chip10and a semiconductor chip70are mounted in accordance with an embodiment of the present invention.FIG. 9is a cross-sectional view of semiconductor component100taken along section line9-9ofFIG. 8;FIG. 10is a cross-sectional view of semiconductor component100taken along section line10-10ofFIG. 8;FIG. 11is a cross-sectional view of semiconductor component100taken along section line11-11ofFIG. 8; andFIG. 12is a cross-sectional view of semiconductor component100taken along section line12-12ofFIG. 8. For the sake of clarity,FIGS. 8-12are described together. Support102includes a device receiving structure104, a device receiving structure106, a gate lead108, a kelvin lead110, and a source lead112and is configured to be packaged in a QFN package. Device receiving structure104is comprised of a square shaped electrically conductive structure having a major surface104A opposite and spaced apart from a major surface104B by a distance D1. Device receiving structure104has opposing edges104C and104D. Device receiving structure106is comprised of a rectangularly shaped electrically conductive structure having a major surface106A opposite and spaced apart from a major surface106B by a distance D2. Device receiving structure106has an edge106C. By way of example, distance D1is less than distance D2. Gate lead108is comprised of a rectangularly shaped electrically conductive structure having an edge108C. Kelvin lead110is comprised of a rectangularly shaped electrically conductive structure having a major surface110A opposite and spaced apart from a major surface110B by a distance D3. Kelvin lead110has an edge110C. Source lead112is comprised of a rectangularly shaped electrically conductive structure having a major surface112A opposite and spaced apart from a major surface112B by a distance D4. Device receiving structure112has an edge112C. By way of example, distances D2, D3, and D4are substantially the same; edge104C faces edge106C, edge108C faces edge104D, edge110C faces edge104D, and edge112C faces edge104D. Suitable materials for device receiving structure104, device receiving structure106, gate lead108, source lead110, and drain lead112include copper, aluminum, or the like.

Support102is configured so that device receiving structure104is laterally positioned between device receiving structure106and leads108,110, and112such that edge104D is adjacent to or faces edge106C, edge108C is adjacent to or faces edge104D, edge110C is adjacent to or faces edge104D, and edge112C is adjacent to or faces edge104D. Device receiving structure104is positioned such that surface104B and edges104C and104D contact a thermally enhanced mold compound120. In addition edge106C of device receiving structure106and edges108C,110C, and112C of leads108,110, and112, respectively, contact thermally enhanced mold compound120. Thus, device receiving structure104is partially embedded in thermally enhanced mold compound120. In accordance with an embodiment, device receiving structure104is positioned with respect to device receiving structure106such that surfaces104A and106A are not coplanar but vertically separated by a distance D5.

Semiconductor chip10is mounted to or bonded to device receiving structure104. More particularly, a layer of die attach material130is formed on surface104A of device receiving structure104and surface14of semiconductor chip10is placed in die attach material130. A bonding agent132is formed on source bond pad18including rectangularly shaped extensions26and28, drain pad20, source lead112, and device receiving structure106. Suitable materials for bonding agent132include solder, an electrically conductive adhesive, an electrically conductive die attach material, or the like. In accordance with an embodiment, distance D5is set so that surface12of silicon chip20is substantially coplanar with surface106A of device receiving structure106.

Semiconductor chip70is bonded to semiconductor chip10and device receiving structure106in a flip-chip configuration. Thus, gate bond pad76A of semiconductor chip70is bonded to extension28, gate bond pad76B of semiconductor chip70is bonded to extension26, and source bond78of semiconductor chip70is bonded to drain bond pad20of semiconductor chip10.

A clip133having terminals133A and133B electrically connects source bond pad18with source lead112. Terminal133A is connected to source lead112through bonding agent132and terminal133B is connected to source contact18through bonding agent132. Suitable materials for bonding agent132have been described above. Source bond pad18is electrically connected to Kelvin lead110through a bonding wire134and gate bond pad16is electrically connected to gate lead108through a bonding wire136. Bonding wires such as bonding wires134and136may be referred to as wirebonds.

As those skilled in the art are aware, support102, including surfaces104A and106A of device receiving structures104and106, respectively, semiconductor chip10, semiconductor chip70, and clip133may be encapsulated in a protective material such as, for example a mold compound (not shown). Mold compound120may be a portion of the mold compound in which semiconductor chip10, semiconductor chip70, and clip133may be encapsulated. Semiconductor component100shown inFIGS. 8-12may be represented schematically by circuit schematic81shown inFIG. 5, where the substrate of III-N semiconductor chip70is floating. For the sake of convenience, semiconductor chip70may be referred to as a semiconductor chip.

FIG. 13is a top view of a semiconductor component200comprising support102to which semiconductor chip10and a semiconductor chip70are mounted in accordance with an embodiment of the present invention.FIG. 14is a cross-sectional view of semiconductor component200taken along section line14-14ofFIG. 13andFIG. 15is a cross-sectional view of semiconductor component200taken along section line15-15ofFIG. 13. For the sake of clarity,FIGS. 13-15are described together. Support102including semiconductor chips10and70have been described with reference toFIGS. 8-12. As discussed above, support102is configured for use in a QFN package. Semiconductor component200differs from semiconductor component100in that bonding wire134and clip133are absent from semiconductor component200and source bond pad18is electrically coupled to Kelvin lead110and source lead112through an electrically conductive clip202. More particularly, electrically conductive clip202has a terminal202A and a terminal202B where terminal202A is electrically connected to source lead112through a bonding agent132and terminal202B is electrically connected to Kelvin lead110through bonding agent132. Semiconductor component200shown inFIGS. 13-15may be represented schematically by circuit schematic81shown inFIG. 5, where the substrate of III-N semiconductor chip70is floating. For the sake of convenience, semiconductor chip70may be referred to as a semiconductor device.

FIG. 16is a top view of a semiconductor component250comprising support102A to which semiconductor chip10and a semiconductor chip70are mounted in accordance with an embodiment of the present invention.FIG. 17is a cross-sectional view of semiconductor component250taken along section line17-17ofFIG. 16andFIG. 18is a cross-sectional view of semiconductor component250taken along section line18-18ofFIG. 16. For the sake of clarity,FIGS. 16-18are described together. Support102A is similar to support102except that device receiving structure106of support102is replaced with a pedestal structure252having a surface252A that corresponds to surface106A of support102and a surface252B that corresponds to surface106B of support102. Thus, semiconductor component250shown inFIGS. 16-18may be represented schematically by circuit schematic81shown inFIG. 5, where the substrate of III-N semiconductor chip70is floating.

FIG. 19is a top view of a semiconductor component300comprising a support102to which a semiconductor chip10and a semiconductor chip70are mounted in accordance with an embodiment of the present invention.FIG. 20is a cross-sectional view of semiconductor component300taken along section line20-20ofFIG. 19andFIG. 21is a cross-sectional view of semiconductor component300taken along section line21-21ofFIG. 19. For the sake of clarity,FIGS. 19-21are described together. Semiconductor component300is similar to semiconductor component100described with reference toFIGS. 8-12, except that semiconductor component300includes a clip302that connects the drain of silicon semiconductor chip10to surface74of the body/substrate of semiconductor material of semiconductor chip70. More particularly, clip302has terminals302A and302B where terminal302A is connected to drain bond pad20through a bonding agent132and terminal302B is bonded to surface74of the body of semiconductor material of semiconductor chip70.

As those skilled in the art are aware, support102, including surfaces104A and106A of device receiving structures104and106, respectively, semiconductor chip10, semiconductor chip70, and clips133and302may be encapsulated in a protection material such as, for example a mold compound. Mold compound120may be a portion of the protection material.

Semiconductor component300shown inFIGS. 19-21may be represented schematically by circuit schematic95shown inFIG. 6, where the substrate of III-N semiconductor chip70is coupled to the drain of semiconductor chip10and to the source of semiconductor chip70.

FIG. 22is a top view of a semiconductor component350comprising a support102to which a semiconductor chip50and a semiconductor chip84are mounted in accordance with an embodiment of the present invention.FIG. 23is a cross-sectional view of semiconductor component350taken along section line23-23ofFIG. 22andFIG. 24is a cross-sectional view of semiconductor component350taken along section line24-24ofFIG. 22. For the sake of clarity,FIGS. 22-24are described together. Support102includes a device receiving structure104, a device receiving structure106, a gate lead108, a source lead110, and a drain lead112and has been described with reference toFIGS. 8-12. As described above, support102is configured for packaging in a QFN package.

Semiconductor chip50is mounted to or bonded to device receiving structure104. More particularly, a layer of die attach material130is formed on surface104A of device receiving structure104and surface54of semiconductor chip50is placed in die attach material130. A bonding agent132is formed on source bond pad58including rectangularly shaped extension64, drain bond pad60, source lead112, and device receiving structure106. Suitable materials for bonding agent132include solder, an electrically conductive adhesive, an electrically conductive die attach material, or the like.

A clip133having terminals133A and133B electrically connects source bond pad18with source lead112. Suitable materials for bonding agent132have been described above. Source bond pad58is electrically connected to Kelvin lead110through a bonding wire134and gate bond pad56is electrically connected to gate lead108through a bonding wire136. Bonding wires such as bonding wires134and136may be referred to as wirebonds.

As those skilled in the art are aware, support102, including surfaces104A and106A of device receiving structures104and106, respectively, semiconductor chip50, semiconductor chip84, and clip133may be encapsulated in a protection material (not shown) such as, for example a mold compound. Mold compound120may be a portion of the protection material.

FIG. 25is a top view of a semiconductor component375comprising a support102to which a semiconductor chip50and a semiconductor chip84are mounted in accordance with an embodiment of the present invention.FIG. 26is a cross-sectional view of semiconductor component375taken along section line26-26ofFIG. 25andFIG. 27is a cross-sectional view of semiconductor component375taken along section line27-27ofFIG. 25. For the sake of clarity,FIGS. 25-27are described together. Semiconductor component375is similar to semiconductor component350described with reference toFIGS. 22-24, except that semiconductor component375includes a clip376that connects drain bond pad60of silicon semiconductor chip50to surface87of the body of semiconductor material of semiconductor chip84. More particularly, clip376has terminals376A and376B where terminal376A is bonded to drain bond pad60through a bonding agent132and terminal376B is bonded to surface87of the body of semiconductor material of semiconductor chip84.

As those skilled in the art are aware, support102, including surfaces104A and106A of device receiving structures104and106, respectively, semiconductor chip50, semiconductor chip84, and clips133and376may be encapsulated in a protection material (not shown) such as, for example a mold compound. Mold compound120may be a portion of the protection material. Support102is configured for packaging in a QFN package.

Semiconductor component375shown inFIGS. 25-27may be represented schematically by circuit schematic95shown inFIG. 6, where the substrate of III-N semiconductor chip84is coupled to the drain of semiconductor chip50and to the source of semiconductor chip84.

FIG. 28is a top view of a semiconductor component377comprising support102to which semiconductor chip50and a semiconductor chip84are mounted in accordance with an embodiment of the present invention. As discussed above, support102is configured for use in a QFN package. Semiconductor component377differs from semiconductor component375in that electrically conductive clip376of semiconductor component375is replaced by an electrically conductive clip379that electrically connects the body/substrate of III-N semiconductor chip84to source bond pad58of semiconductor chip50. More particularly, clip379has terminals379A and379B where terminal379A is connected to source bond pad58through bonding agent132and electrically conductive clip133, and terminal379B is bonded to surface87of the body or substrate of the semiconductor material of III-N semiconductor chip84

Semiconductor component377shown inFIG. 28may be represented schematically by circuit schematic97shown inFIG. 7, where the substrate of III-N semiconductor chip84is coupled to the source of semiconductor chip50.

FIG. 29is a top view of a semiconductor component400comprising a support402to which a semiconductor chip10and a semiconductor chip70are mounted in accordance with an embodiment of the present invention.FIG. 30is a cross-sectional view of semiconductor component400taken along section line30-30ofFIG. 29;FIG. 31is a cross-sectional view of semiconductor component400taken along section line31-31ofFIG. 29; andFIG. 32is a cross-sectional view of semiconductor component400taken along section line32-32ofFIG. 29. For the sake of clarity,FIGS. 29-32are described together. Support402includes a device receiving structure404, a device receiving structure406, a gate lead408, a Kelvin lead410, a source lead412and configured for packaging in a QFN package. Device receiving structure404is comprised of an electrically insulating material such as, for example, a thermally enhanced mold compound having a major surface404A. Gate lead408, Kelvin lead410, and source lead412may be referred to as electrically conductive leads.

Device receiving structure406is comprised of an electrically conductive structure414having an end region414A, a central region414B, and an end region414C. End region414A and central region414B have a thickness T1and end region414C has a thickness T2, wherein thickness T2is greater than thickness T1. Thus, end region14C is thicker than regions414A and414B and forms a pedestal portion.

Device receiving structure406further includes an electrically conductive structure420A that serves as a gate lead, an electrically conductive structure420B that serves as another gate lead, and an electrically conductive structure422that serves as a source lead. Electrically conductive structures420A,420B, and422are electrically isolated from each other.

Semiconductor chip10is mounted to or bonded to device receiving structure404. More particularly, a layer of die attach material130is formed on surface404A of device receiving structure404and surface14of semiconductor chip10is placed in die attach material130. A bonding agent132is formed on source bond pad18including rectangularly shaped extensions26and28, drain bond pad20, source lead422, and device receiving structure406. Suitable materials for bonding agent132include solder, an electrically conductive adhesive, an electrically conductive die attach material, or the like.

Semiconductor chip70is bonded to device receiving structure406in a flip-chip configuration. Thus, gate bond pad76A of semiconductor chip70is bonded to gate lead420B, gate bond pad76B is bonded to gate bond pad420A, source bond pad78is bonded to source lead422, and drain bond pad80is bonded to end region414C of device receiving structure406. In accordance with an embodiment, gate bond pads76A and76B are tied to the same potential through the metallization system of semiconductor chip70.

A clip430having terminals430A and430B electrically connects drain bond pad20of semiconductor die10to source lead422of semiconductor chip70. More particularly, terminal430A is bonded to drain20of semiconductor die10using a bonding agent132and terminal430B is bonded to source lead422using a bonding agent132. Suitable materials for bonding agent132have been described above. Source bond pad18is electrically connected to gate leads420A and420B through bonding wires432and434, respectively. Gate bond pad16is electrically connected to gate lead408through a bonding wire436; Kelvin lead410is electrically connected to source bond pad18of semiconductor chip10through a bonding wire438, and source lead412is electrically connected to source bond pad18thought bonding wires440. Bonding wires such as bonding wires432,434,436,438, and440may be referred to as wirebonds.

As those skilled in the art are aware, support402, including device receiving structures404and406, semiconductor chip10, semiconductor chip70, and clip430may be encapsulated in a protection material such as, for example a mold compound. A mold compound120is illustrated that may be a portion of the protection material.

FIG. 33is a top view of a semiconductor component450comprising a support452to which a semiconductor chip50and a semiconductor chip84are mounted in accordance with an embodiment of the present invention.FIG. 34is a cross-sectional view of semiconductor component450taken along section line34-34ofFIG. 33. For the sake of clarity,FIGS. 33 and 34are described together. Support452includes a device receiving structure454, a device receiving structure456, a gate lead458, a Kelvin lead460, and a source lead462. Leads458,460, and462may be referred to as electrically conductive leads or electrically conductive structures. Device receiving structure454is comprised of an electrically insulating material such as, for example, a thermally enhanced mold compound having a major surface454A.

Device receiving structure456is comprised of an electrically conductive structure468having an end region468A, a central region468B, and an end region468C. End region468A and central region468B have a thickness T1and end region468C has a thickness T2, wherein thickness T2is greater than thickness T1. Thus, end region468C is thicker than regions468A and468B and forms a pedestal portion.

Device receiving structure456further includes an electrically conductive lead470that serves as a gate lead and an electrically conductive lead472that serves as a source lead.

Semiconductor chip50is mounted to or bonded to device receiving structure454. More particularly, a layer of die attach material130is formed on surface454A of device receiving structure454and surface54of semiconductor chip50is placed in die attach material130. A bonding agent132is formed on drain bond pad60of semiconductor chip50, gate lead470and source lead472. Suitable materials for bonding agent132have been described above.

Semiconductor chip84is bonded to device receiving structure456in a flip-chip configuration. Thus, gate bond pad86of semiconductor chip84is bonded to gate lead470, source bond pad88is bonded to source lead472, and drain bond pad90is bonded to end region468C.

A clip430having terminals430A and430B electrically connects drain60of semiconductor die50to source lead88of semiconductor chip84. More particularly, terminal430A is bonded to drain bond pad60of semiconductor die50using a bonding agent132and terminal430B is bonded to source lead472using a bonding agent132. Suitable materials for bonding agent132have been described above. Source bond pad58is electrically connected gate lead470through a bonding wire485. Gate bond pad56is electrically connected to gate lead458through a bonding wire487; Kelvin lead460is electrically connected to source bond pad58of semiconductor chip50through a bonding wire489, and source lead462is electrically connected to source bond pad58thought bonding wires491. Bonding wires such as bonding wires485,487,489, and491may be referred to as wirebonds.

As those skilled in the art are aware, support452, including device receiving structures454and456, semiconductor chip50, semiconductor chip84, and clip430may be encapsulated in a protection material such as, for example a mold compound. Portion120of the mold compound is illustrated inFIG. 34.

FIG. 35is a top view of a semiconductor component500comprising a support452to which a semiconductor chip50and a semiconductor chip84are mounted in accordance with an embodiment of the present invention.FIG. 36is a cross-sectional view of semiconductor component500taken along section line36-36ofFIG. 35. For the sake of clarity,FIGS. 35 and 36are described together. Support452includes a device receiving structure454, a device receiving structure456, a gate lead458, a Kelvin lead460, and a source lead462and has been described with reference toFIGS. 29 and 30. Support452is configured for packaging in a QFN package.

Semiconductor component500is similar to semiconductor component450described with reference toFIGS. 33 and 34except that semiconductor component500includes a clip502that electrically connects drain bond pad60of silicon semiconductor chip50to surface87of the body of semiconductor material of semiconductor chip84. More particularly, clip502has terminals502A and502B where terminal502A is connected to drain bond pad60through a bonding agent132and terminal430A of clip430and terminal502B is bonded to surface87of the body of semiconductor material of semiconductor chip70using an electrically conductive die attach material130.

Semiconductor component500shown inFIGS. 35-36may be represented schematically by circuit schematic95shown inFIG. 6, where the substrate of III-N semiconductor chip84is electrically connected to drain bond pad60of semiconductor chip50and to the source bond pad88of semiconductor chip84.

FIG. 37is a top view of a semiconductor component600comprising a support602to which a semiconductor chip10and a semiconductor chip70are mounted in accordance with an embodiment of the present invention.FIG. 38is a cross-sectional view of semiconductor component600taken along section line38-38ofFIG. 37andFIG. 39is a cross-sectional view of semiconductor component600taken along section line39-39ofFIG. 37. For the sake of clarity,FIGS. 37-39are described together. Support602includes a device receiving structure604and a device receiving structure606. Device receiving structure604is comprised of a layer of an electrically conductive material such as, for example, copper and has a major surface604A. Support602further includes electrically conductive leads608,610, and612that serve as a gate lead, a Kelvin lead, and a source lead, respectively.

Device receiving structure606is comprised of an electrically conductive structure614having an end region614A, a central region614B, and an end region614C, which end region614C serves as a drain lead and may be referred to as a drain lead. End region614C has opposing surfaces614CAand614CB. End region614A and central region614B have a thickness T1and end region614C has a thickness T2, wherein thickness T2is greater than thickness T1. Thus, end region614C is thicker than regions614A and614B and forms a pedestal portion.

Device receiving structure606further includes an electrically conductive lead620A that serves as a gate lead, an electrically conductive structure620B that serves as another gate lead, and an electrically conductive lead622that serves as a source lead.

In accordance with an embodiment, a layer of ceramic material626is formed at least on regions614A and614B and electrically conductive layer604and gate leads620A and620B and source lead622are bonded to ceramic layer626. By way of example, regions614A,614B, ceramic layer626, gate leads620A and620B, and source lead622form a direct bonded copper structure628.

Semiconductor chip10is mounted to or bonded to device receiving structure604. More particularly, a layer of die attach material130is formed on surface604A of device receiving structure604and surface54of semiconductor chip10is placed in die attach material130. A bonding agent132is formed on source bond pad18including rectangularly shaped extensions26and28, drain bond pad20, device receiving structure106, gate leads620A and620B, source lead622, and surface614CAof end614C. Suitable materials for bonding agent132have been described above.

Semiconductor chip70is bonded to device receiving structure606in a flip-chip configuration. Thus, gate bond pad76A of semiconductor chip70is bonded to gate lead620B, gate bond pad76B is bonded to gate bond pad620A, source bond pad78is bonded to source lead622, and drain bond pad80is bonded to surface614CTof end region614C of device receiving structure606.

A clip630having terminals630A and630B electrically connects drain20of semiconductor die10to source lead622of semiconductor chip70. More particularly, terminal630A is bonded to drain20of semiconductor die10using a bonding agent132and terminal630B is bonded to source lead622using a bonding agent132. Suitable materials for bonding agent132have been described above. Source bond pad18is electrically connected to gate lead620A through a bonding wire432and to gate lead620B through a bonding wire434. Gate bond pad16is electrically connected to gate lead608through a bonding wire436; Kelvin lead610is electrically connected to source bond pad18of semiconductor chip10through a bonding wire438, and source lead612is electrically connected to source bond pad18thought bonding wires440. Bonding wires such as bonding wires432,434,436,438, and440may be referred to as wirebonds.

As those skilled in the art are aware, support602, including device receiving structures604and606, semiconductor chip10, semiconductor chip70, and clip630may be encapsulated in a protection material such as, for example a mold compound138. Mold compound138is shown inFIG. 33by a broken line or a dashed line.

FIG. 40is a top view of a semiconductor component700comprising a support702that includes a device receiving structure704in accordance with an embodiment of the present invention.FIG. 41is a cross-sectional view of semiconductor component700taken along section line41-41ofFIG. 40. Device receiving structure704is a rectangularly shaped electrically conductive pad that includes a region704A separated from a region704C by a pedestal region704B. Region704A has a surface704AS, region704B has a region704BS, and region704C has a region704CS, wherein surfaces704ASand704CSare substantially coplanar, and surface704BSis in a plane above the coplanar plane in which surfaces704ASand704CSare located.

Support702is further configured to have a rectangularly shaped electrically conductive structure708adjacent to but electrically isolated from device receiving structure704. In accordance with another embodiment, rectangularly shaped electrically conductive structure708serves as a gate lead.

Support702is further configured to have a rectangularly shaped electrically conductive structure710adjacent to but electrically isolated from device receiving structure704. In accordance with another embodiment, rectangularly shaped electrically conductive structure710serves as a Kelvin lead.

Support702is further configured to have an electrically conductive structure712adjacent to but electrically isolated from device receiving structure702. Electrically conductive structure712serves as a source lead. By way of example, source lead712is comprised of a rectangular portion712A and a rectangular portion712B, wherein portions712A and712B form a “T-shape.”

Support702is further configured to have a rectangularly shaped electrically conductive structure714adjacent to but electrically isolated from device receiving structure704. In accordance with another embodiment, rectangularly shaped electrically conductive structure714serves as a sense lead.

Device receiving structure702has an extension716extending from a corner of rectangularly shaped support702, wherein extension716serves as a drain lead.

An electrically insulating material730is formed on a region704A of device region704. By way of example, electrically insulating material730is ceramic. A layer of electrically conductive material732is formed on electrically insulating material730. By way of example, electrically conductive layer732is copper. It should be noted that region704A, ceramic layer730, electrically conductive layer732may be configured to form a direct bonded copper structure.

Semiconductor chip10is mounted to or bonded to device receiving structure704. More particularly, a layer of die attach material130is formed on the surface of electrically conductive layer732and surface14of semiconductor chip10is placed in die attach material130. A bonding agent132is formed on source bond pad18including rectangularly shaped extensions26and28, gate bond pad16, and surface704BSof region704B.

Semiconductor chip70is bonded to semiconductor chip10and to surface706B of region706in a flip-chip configuration. Thus, gate bond pad76A of semiconductor chip70is bonded to extension26of source bond pad18, gate bond pad76B is bonded to extension28of source bond pad18, source bond pad78of semiconductor chip70is bonded to drain bond pad20of semiconductor chip10, and drain bond pad80is bonded to surface704BSof region704B. It should be noted that pedestal704B has a height H1and that height H1is configured so that the thickness of direct bonded structure705and semiconductor die10is substantially equal to height H1.

A clip740electrically connects source bond pad18of semiconductor die10to source lead712and to Kelvin lead710. More particularly, clip740has a body region740A, a terminal740B and a terminal740C, wherein terminals740B and740C extend from body region740A, terminal740B is bonded to Kelvin lead710using a bonding agent132and terminal740C is bonded to source lead712using bonding agent132. Suitable materials for bonding agent132have been described above. Sense lead714is electrically connected to electrically conductive layer732, and thus to the body of semiconductor material of semiconductor chip10through a bonding wire736. A bonding wire such as bonding wire736may be referred to as a wirebond.

As those skilled in the art are aware, support702, including device receiving structures704and706, semiconductor chip10, semiconductor chip70, and clip740may be encapsulated in a protection material such as, for example a mold compound. It should be appreciated that semiconductor component700may be configured for mounting in a through hole package having, for example, a TO-220outline, a TO-247outline, a TO-264outline, a TO-257outline, or the like.

FIG. 42is a top view of a semiconductor component750comprising a support752having a semiconductor chip10and a semiconductor chip70bonded thereto in accordance with an embodiment of the present invention. What is shown inFIG. 38is a rectangularly shaped, electrically conductive, support or support structure752having a surface754. Semiconductor component750further includes a gate lead756, a drain lead758, and a source lead760, where gate lead756and source lead760are electrically isolated from support752and drain lead758extends from support752. Thus, support752and drain lead758form a unitary structure. Semiconductor component750is configured so that drain lead758is between gate lead756and source lead760. It should be appreciated that semiconductor component750may be configured for mounting in a through hole package having, for example, a TO-220outline, a TO-247outline, a TO-264outline, a TO-257outline, or the like. Thus, support structure752is at different level than leads756and760and at a different level than a portion of lead758.

A direct bonded copper substrate766having a surface766A is bonded to a portion of surface754and a direct bonded copper substrate768having a surface768A is bonded to another portion of surface754. A semiconductor chip10is mounted to or bonded to surface766A and a semiconductor chip70is mounted to or bonded to surface768A. More particularly, a layer of die attach material is formed on surface766A and on surface768A and surface14of semiconductor chip10is placed in the die attach material that is on surface766A and surface74is placed in the die attach material that is on surface768A.

Drain bond pad80of semiconductor chip70is electrically connected to support752by one or more bonding wires770; gate bond pads76A and76B are electrically connected to extensions26and28of source bond pad18by bonding wires772and774, respectively, and source bond pad78of semiconductor chip70is electrically connected to drain bond pad20of semiconductor chip10by one or more bonding wires776. Gate bond pad16of semiconductor chip10is electrically connected to gate lead756by a bonding wire778and source bond pad18is electrically connected to source lead760by one or more bonding wires780. Bonding wires such as bonding wires770,772,774,776,778, and780may be referred to as wirebonds.

It should be noted that bonding wires770may be replaced by an electrically conductive clip or interconnect, bonding wires772and774may be replaced by an electrically conductive clip or interconnect, bonding wires776may be replaced by an electrically conductive clip or interconnect, bonding wire778may be replaced by an electrically conductive clip or interconnect, and bonding wires780may be replaced by an electrically conductive clip or interconnect.

As those skilled in the art are aware, support770, including support752, direct bonded copper substrates766and768, and bonding wires770-780may be encapsulated in a protection material such as, for example a mold compound. Although an insulated metal substrate such as, for example, direct bonded copper substrates766and768have been described as being bonded to support752, this is not a limitation of the present invention. Alternatively, layers of electrically insulating material may be formed on portions of support770. Then, a layer of electrically conductive material may be formed on the layers of insulating material. By way of example, the layers of electrically conductive material is copper. Techniques for forming an insulating material on an electrically conductive substrate such as a leadframe and for forming an electrically conductive material on an insulating material are known to those skilled in the art.

FIG. 43is a top view of a semiconductor component800comprising a support802having a semiconductor chip10and a semiconductor chip70bonded thereto in accordance with an embodiment of the present invention. What is shown inFIG. 39is a rectangularly shaped, electrically conductive, support or support structure802having a surface804. Semiconductor component800further includes a gate lead806, a drain lead808, and a source lead810, where gate lead806and source lead810are electrically isolated from support802and drain lead808extends from support802. Thus, support802and drain lead808form a unitary structure. Semiconductor component800is configured so that source lead810is between gate lead806and drain lead808. It should be appreciated that semiconductor component800may be configured for mounting in a through hole package having, for example, a TO-220outline, a TO-247outline, a TO-264outline, a TO-257outline, or the like. Thus, support structure802is at different level than leads806and810and at a different level than a portion of lead808.

A direct bonded copper substrate766having a surface766A is bonded to a portion of surface804and a direct bonded copper substrate768having a surface768A is bonded to another portion of surface804. A semiconductor chip10is mounted to or bonded to surface766A and a semiconductor chip70is mounted to or bonded to surface768A. More particularly, a layer of die attach material is formed on surface766A and on surface768A and surface14of semiconductor chip10is placed in the die attach material that is on surface766A and surface74is placed in the die attach material that is on surface768A. As those skilled in the art are aware, a direct bonded copper substrate such as, for example, direct bonded copper substrates766and768may be comprised of a ceramic material having opposing surfaces wherein a layer of copper is formed on one of the opposing surfaces and another layer of copper is formed on the other of the opposing surfaces.

Drain bond pad80of semiconductor chip70is electrically connected to support802by one or more bonding wires770; gate bond pads76A and78A are electrically connected to extensions26and28of source bond pad18by bonding wires772and774, respectively, and source bond pad78of semiconductor chip70is electrically connected to drain bond pad20of semiconductor chip10by one or more bonding wires776. Gate bond pad16of semiconductor chip10is electrically connected to gate lead756by a bonding wire778and source bond pad18is electrically connected to source lead760by one or more bonding wires780. Bonding wires such as bonding wires770,772,774,776,778, and780may be referred to as wirebonds.

It should be noted that bonding wires770may be replaced by an electrically conductive clip or interconnect, bonding wires772and774may be replaced by an electrically conductive clip or interconnect, bonding wires776may be replaced by an electrically conductive clip or interconnect, bonding wire778may be replaced by an electrically conductive clip or interconnect, and bonding wires780may be replaced by an electrically conductive clip or interconnect.

As those skilled in the art are aware, support802, direct bonded copper substrates766and768, and bonding wires770-780may be encapsulated in a protection material such as, for example a mold compound. Although an insulated metal substrate such as, for example, direct bonded copper substrates766and768are described as being bonded to support802, this is not a limitation of the present invention. Alternatively, layers of electrically insulating material may be formed on portions of support802. Then, a layer of electrically conductive material may be formed on the layers of insulating material. By way of example, the layers of electrically conductive material is copper. Techniques for forming an insulating material on an electrically conductive substrate such as a leadframe and for forming an electrically conductive material on an insulating material are known to those skilled in the art.

FIG. 44is a top view of a semiconductor component850comprising a support852having a semiconductor chip10and a semiconductor chip70bonded thereto in accordance with an embodiment of the present invention. What is shown inFIG. 40is a rectangularly shaped, electrically conductive, support or support structure852having a surface854. Semiconductor component850further includes a gate lead856, a Kelvin lead858, and a source lead860, where gate lead856, Kelvin lead858, and source lead860are electrically isolated from support852. A bottom surface of support852serves as a drain lead of semiconductor component850. Semiconductor component850is configured so that Kelvin lead858is between gate lead856and source lead860. Support852is configured to be packaged in a QFN package.

A direct bonded copper substrate766having a surface766A is bonded to a portion of surface854and a direct bonded copper substrate768having a surface768A is bonded to another portion of surface854. A semiconductor chip10is mounted to or bonded to surface766A and a semiconductor chip70is mounted to or bonded to surface768A. More particularly, a layer of die attach material130is formed on surface766A and on surface768A and surface14of semiconductor chip10is placed in die attach material130that is on surface766A and surface74is placed in die attach material130that is on surface768A.

Drain bond pad80of semiconductor chip70is electrically connected to support852by one or more bonding wires770; gate bond pads76A and78A are electrically connected to extensions26and28of source bond pad18by bonding wires772and774, respectively, and source bond pad78of semiconductor chip70is electrically connected to drain bond pad20of semiconductor chip10by one or more bonding wires776. Gate bond pad16of semiconductor chip10is electrically connected to gate lead856by a bonding wire778and source bond pad18is electrically connected to source lead860by one or more bonding wires780, and source bond pad18of semiconductor chip10is electrically connected to Kelvin lead858by a bonding wire782. Bonding wires such as bonding wires770,772,774,776,778,780, and782may be referred to as wirebonds.

It should be noted that bonding wires770may be replaced by an electrically conductive clip or interconnect, bonding wires772and774may be replaced by an electrically conductive clip or interconnect, bonding wires776may be replaced by an electrically conductive clip or interconnect, bonding wire778may be replaced by an electrically conductive clip or interconnect, bonding wires780may be replaced by an electrically conductive clip or interconnect, and bonding wire782may be replaced by an electrically conductive clip or interconnect.

As those skilled in the art are aware, support852, direct bonded copper substrates766and768, and bonding wires770-782may be encapsulated in a protection material such as, for example a mold compound. Although an insulated metal substrate such as, for example, direct bonded copper substrates766and768are described as being bonded to support852, this is not a limitation of the present invention. Alternatively, layers of electrically insulating material may be formed on portions of support802. Then, a layer of electrically conductive material may be formed on the layers of insulating material. By way of example, the layer of electrically conductive material is copper. Techniques for forming an insulating material on an electrically conductive substrate such as a leadframe and for forming an electrically conductive material on an insulating material are known to those skilled in the art.