Methods and apparatus for reading a full-swing memory array

Techniques for reducing power when reading a full-swing memory array are disclosed. The full-swing memory array includes a plurality of local bit lines and a global bit line. In order to reduce power consumption, a method of driving the global bit line includes the step of coupling the plurality of local bit lines to the global bit line through a plurality of tri-state devices. The method further includes the steps of generating a global select signal to enable one of the plurality of tri-state devices and selecting a corresponding local bit line to drive the output of the enabled tri-state device. In this way, the global bit line is statically driven so that consecutive reads of bits having the same value read over the global bit line do not result in transitioning the state of the global bit line.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to improvements related to reading a full-swing memory array, and, more particularly, to advantageous techniques for statically driving a global bit line in the full-swing memory array.

2. Relevant Background

Full-swing memory arrays utilize a dynamic precharge and discharge technique when reading bits stored in a memory cell. This conventional technique is typically divided into two levels to minimize diffusion capacitance carried on bit lines within a full-swing memory array. The first level of a full-swing memory array includes storage cells, pass transistors, and local bit lines. A storage cell stores a binary value. The pass transistor is driven by a read word line to discharge a local bit line based on a memory cell's content. The local bit line is typically shared by multiple read word lines. The local bit line is precharged high so that a transition on a memory read can be recognized. The local bit line provides input to the second level.

The second level of a full-swing memory array typically includes a number of inverters and pull-down transistor pairs where each pair is provided input by one local bit line. The pull-down transistors connect to a dynamically precharged global bit line. This memory array is termed full-swing because the local and global bit lines need to be pulled to ground in order to recognize a 0 value stored in a memory cell. When reading consecutive 0 values from a memory cell, a conventional lull-swing memory array requires pre-charging and discharging of the local and global bit lines. The pre-charging of the local and global bit lines must occur before a read word line signal is asserted. The discharging occurs as a 0 value is propagated through the second level. In this way, power is consumed by the pre-charging and discharging of both the local and global bit lines during a read when consecutive 0 values are propagated over the global bit line.

Furthermore, in conventional full-swing memory arrays, a holding circuit or dynamic-to-static converter is typically added to the output of the global bit line to ensure that the output holds the evaluated value of the global bit line. This additional circuitry consumes silicon real estate on which the memory array is disposed.

SUMMARY OF THE DISCLOSURE

Among its several aspects, the present invention recognizes the problem of extraneous power consumption caused by the pre-charging and discharging of the global bit line in conventional full-swing arrays during consecutive reads of memory cells which have a 0 value. To this end, an embodiment of the present invention includes statically switching global bit lines. Such a technique reduces power consumption during consecutive reads of 0 values and does so, in a manner, which removes the need for a holding circuit or dynamic-to-static converter circuit at the output.

In one embodiment, a method of driving a global bit line is disclosed. The method includes the step of coupling the plurality of local bit lines to the global bit line through a plurality of tri-state devices. The method further includes the steps of generating a global select signal to enable one of the plurality of tri-state devices, and selecting a corresponding local bit line to drive the output of the enabled tri-state device. In this way, the global bit line is statically driven so that consecutive reads of bits having the same value read over the global bit line do not result in transitioning the state of the global bit line.

DETAILED DESCRIPTION

FIG. 1shows an exemplary wireless communication system100in which an embodiment of the invention may be advantageously employed. For purposes of illustration,FIG. 1shows three remote units120,130, and150and two base stations140. It will be recognized that typical wireless communication systems may have many more remote units and base stations. Remote units120,130, and150include improved full-swing memory arrays125A,125B, and125C, respectively, which are embodiments of the invention as discussed further below.FIG. 1shows forward link signals180from the base stations140and the remote units12,13, and15and reverse link signals190from the remote units12,13, and15to base stations140.

InFIG. 1, remote unit120is shown as a mobile telephone, remote unit130is shown as a portable computer, and remote unit150is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be cell phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, or fixed location data units such as meter reading equipment. AlthoughFIG. 1illustrates remote units according to the teachings of the invention, the invention is not limited to these exemplary illustrated units. The invention may be suitably employed in any device which includes a full-swing memory array.

FIG. 2is a circuit diagram of a read portion of a full-swing memory array system200in accordance with the embodiment of the invention. The read portion of the full-swing memory array system200includes optional sets of read word line drivers210A-210B, distributed dynamic OR component220, and a full-swing memory array230modified according to the teachings of the invention. The sets of read word line drivers210A and210B receive an active low, fully decoded, read word line signal and respectively couple to the distributed dynamic OR component220and the full-swing memory array230. The distributed dynamic OR component220couples to the full-swing memory array230. The sets of read word line drivers210A-210B are optional if the read word line signal is active high.

For the sake of simplicity, only the set of read word line drivers210A and the distributed dynamic OR component220will be described in detail here. The set of read word line drivers210A includes up to eight inverters such as inverter215. Inverter215, for example, receives a read word line signal205where the active-low read word line signal205is inverted and propagated to the distributed dynamic OR component220and the full-swing memory array230. The distributed dynamic OR component220includes sixteen pull-down transistors, such as pull-down transistor222, where eight of the pull-down transistors222terminate their outputs to a common node227A and eight other of pull-down transistors222have their outputs coupled to a common node227B and to four pull-up transistors226A,226B,224A and224B. Outputs of pull-up transistors226A and224A terminate to the common node227A. Outputs of pull-up transistors226B and224B terminate to the common node227B. Distributed dynamic OR component220also includes a NAND gate228. NAND gate228is coupled in parallel with keeper transistors224A and224B. Common nodes227A and227B couple to NAND gate228which produces as its output a global select signal over global select line250.

The distributed dynamic OR component220receives as input an active-low precharge pulse223to precharge common node227A through pull-up transistor226A. Once common node227A is precharged and signal223transitions high, the keeper transistor224A keeps the common node227A at a logic 1 so that the transition to active logic 0 can be recognized.

Alternatively, common nodes227A and227B may be de-coupled by replacing NAND gate228with an inverter as shown in an alternative embodiment described in connection withFIG. 5. However, as will be recognized when discussing the embodiment ofFIG. 5, by coupling common nodes227A and227B through NAND gate228, the number of global select lines are reduced in half. It is recognized that other couplings between more than two distributed dynamic OR components to reduce the number of global select lines further are contemplated by the teachings of the present invention, and that other logic designs can be implemented to achieve the same results given these teachings.

It should be noted that multiple dynamic OR components such as multiple dynamic OR component220may be manufactured in silicon to place common nodes227A and227B inline with each other as illustrated inFIG. 2. In so doing, a single routing channel is etched along a coincidental path which advantageously reduces the overall number of routing channels.

The full-swing memory array230includes an array of random access memory (RAM) cells such as RAM cell235. Each row of RAM cells is coupled to the same read word line. The RAM cells in a column of RAM cells are coupled to different read word lines. As illustrated inFIG. 2, a sub-column of eight RAM cells terminate to local bit line240A. Similarly a second sub-column of eight RAM cells are coupled to a different set of read word lines and terminate to local bit line240B.

The full-swing memory array230also includes a number of pull-up transistors such as pull-up transistor245, a number of tri-state devices such as tri-state NAND gate255, and an optional keeper cell260. The pull-up transistor245receives an active-low local bit line precharge pulse243to precharge the local bit line240A. The pull-up transistor245keeps local bit line240A at logic 1, when precharged, until a logic 0 is read from a RAM cell. The tri-state devices propagate output to global bit line253. The tri-state devices receive input from two local bit lines such as local bit lines240A and240B. The local bit lines propagate the contents of a read RAM cell when the appropriate read word line is activated. Tri-state devices are enabled by their respective global select signal. For example, tri-state NAND gate255is suitably enabled by global select signal250.

The number of tri-state devices utilized in a full-swing memory array according to the teachings of the invention varies with the full-swing memory size and the number of RAM cells terminating to a tri-state device. In general, the total number of tri-state devices, nt, may be expressed as follows:
nt=(R*C)/br,   (1)
where R is the number of rows of the full-swing memory array, C is the number of columns of the full-swing memory array, and bris the number of RAM cells terminated to a tri-state device. For example, in a tri-state NAND gate embodiment of a 32×32 full-swing memory array system, ntwould equal 32 rows times 32 columns divided by 16 RAM cells per tri-state NAND gate for a total of 64 tri-state NAND devices. For a 64×32 full-swing memory array configuration, 128 tri-state NAND devices would be utilized. The number of tri-state NAND devices utilized in a particular column, nc, is expressed as follows:
nc=R/br(2)
Incidentally, ncalso equals the number of global select lines utilized in the system.

Assuming thatFIG. 2illustrates a 64×32 configuration, the full-swing memory array230would contain 64 read lines where each set of read word line drivers has eight inverters to couple to eight read word lines, thus, a total of eight sets of eight word line drivers. Two sets of word line drivers would couple to a corresponding dynamic OR component having a total of sixteen pull down transistors and to sixteen rows of 32 RAM cells. A local bit line would couple eight RAM cells. Each column of the full-swing memory array230would contain eight local bit lines, thus, a total of 256 local bit lines. Each column of the full-swing memory array230would also contain one global bit line for a total of 32 global bit lines where each global bit line couples to eight local bit lines through four tri-state NAND gates. It should be noted that different size configurations of the full-swing memory system are supported without limiting the embodiments of the invention.

When reading a row of memory, one read word line signal is asserted such as read word line signal205. By way of example, inverter215inverts read word line signal205and propagates the inverted signal225which is active high to pull-down transistor222and to read a corresponding row of RAM cells including RAM cell235. Assuming common node227A has been initially precharged through pull-up transistor226A, pull-down transistor222is activated which brings down the common node227A to ground or logic 0, for example. Assuming only one read word line at most is active at any instant and, thus, common node227B is held at logic 1, NAND gate228propagates logic 0 from common node227A to logic 1 to enable tri-state NAND gate255.

Concurrently, the contents of RAM cell235are propagated on local bit line240A. Assuming pull-up transistor245has precharged local bit line240A by precharge signal243, if the content of RAM cell235is logic 0, the local bit line is discharged to logic 0. The enabled tri-state NAND gate255then propagates logic 0 from local bit line240A to logic 1 on global bit line253. The inverter in the keeper cell260inverts the logic 1 to logic 0 and propagates logic 0 to output265. If the next read signal received which utilizes global bit line253results in reading a RAM cell containing a logic 0, the global bit line253remains at logic 1 without having to transition, thus, saving power consumption. The operation of the read portion of a full-swing memory array system200will be described in further detail in connection with the discussion ofFIG. 3.

FIG. 3is a timing diagram300illustrating the static nature of a global bit line such as global bit line253ofFIG. 2in accordance with an embodiment of the invention. Timing diagram300illustrates five signals including read word line signal225, local bit line (LBL) precharge signal243, LBL240A, global select signal on global select line250, and the signal on global bit line (GBL)253.

By way of example,FIG. 3will be described in combination withFIG. 2for the situation where two logic 0s are consecutively read from full swing memory230. To begin, pull-up transistor245fully precharges local bit line240to logic 1 at time305. Similarly, pull-up transistors226A and226B fully precharge common nodes227A and227B to logic 1. Read word line225is now asserted at time310which results in two concurrent occurrences. First, common node227A is brought to logic 0 by discharging through pull-down transistor222. Second, the contents of RAM cell235, which is assumed to be logic 0, are read, discharging LBL240A to logic 0.

Returning to the first occurrence, NAND gate228receives as an input a logic 0 from common node227A and, since common node227B has not been discharged, it stays at a logic 1. Thus, at time315, global select signal250goes active to enable tri-state NAND gate255, after LBL240A has been evaluated at time312.

Now that tri-state NAND gate255is enabled and receives as an input a logic 0 over local bit line240A and, since no read word lines corresponding to word line driver set210B have been activated, local bit line240B remains at logic 1. Consequently, at time320, global bit line253transitions to logic 1 and the RAM data output265transitions to logic 0 to correspond to the contents of RAM cell235.

At time321, the global bit line select signal250is disabled before the local bit line precharge signal243is enabled at time322. At time323, the local bit line240A has completed precharging through pull-up transistor245, thus, being preconditioned to logic 1 for the next active read word line signal. At time325, a subsequent read word line signal is activated which again results in two concurrent occurrences. First, common node227A is brought to logic 0. Second, the contents of RAM cell235, which continues to be logic 0, are read, discharging pull-up transistor245and transitioning LBL240A to logic 0 at time330.

Returning to the first occurrence, NAND gate228receives as an input a logic 0 from common node227A and, since pull-up transistor226B has not been discharged, a logic 1 from common node227B. Thus, at time333, global select signal250goes active to enable tri-state NAND gate255. The output of NAND gate255remains at logic 1. Thus, global bit line253remains at logic 1 without transitioning as it did at time320which results in saving power between consecutive reads over the same global bit line where the value read is0. This behavior of the global bit line253is referred to as static behavior. In contrast, local bit line240A, like conventional global bit lines, dynamically transitions on each read due to the precharging and discharging of the local bit line capacitance regardless of the previous read data.

It should be noted that although the above example was described in the context of two consecutive reads from the same RAM cell, the global bit line253will remain high for consecutive reads of any RAM cell with the same data, which terminates at any tri-state NAND gate coupled to the same global bit line.

FIG. 4illustrates details for one suitable embodiment of the tri-state NAND gate255shown inFIG. 2. Tri-state NAND gate255includes inverters405, an OR gate410, a NAND gate420, an AND gate430, and an output transistor stack including a pull-up transistor440, and a pull-down transistor450. As described above, the NAND gate255receives as inputs the global select signal250and local bit lines240A and240B and produces its output on global bit line253. Global bit line253couples to pull-up transistor440and pull-down transistor450.

Pull-up transistor440couples to the output of NAND gate420. NAND gate420couples to the output of OR gate410and global select signal250. OR gate410couples to inverters405. Inverters405couple to local bit lines240A and240B.

Pull-down transistor450couples to the output of AND gate430. AND gate430couples to the global select signal250and local bit lines240A and240B. Global bit line253is logic 1 when either local bit line240A or240B are at logic 0 and global select signal250is at logic 1. Global bit line253is logic 0 when local bit lines240A and240B and global select signal250are at logic 1. In any other combination of values inputted to NAND gate255, the value of global bit line253will be determined by an enabled NAND gate which is also coupled to it. If none of the NAND gates coupled to the global bit line253are enabled, global bit line253will maintain the last value read over it due to keeper cell260.

By utilizing an output stack comprising two transistors, the physical dimensions of the transistors are smaller for a given global bit line load than conventional output stacks having more than two output transistors. Such an advantage reduces the footprint size and the self-capacitance on the global bit line due to the output transistors of the tri-state device.

FIG. 5is an alternative embodiment of a read portion of a full-swing memory array system200in accordance with another embodiment of the invention. The read portion of a full-swing memory array system500includes read word line drivers510, a dynamic OR component520and a full-swing memory array530modified according to the teachings of the invention. The read word line drivers510couple to both the dynamic OR component520and the full-swing memory array530. The dynamic OR component520couples to the full-swing memory array530through global select line550.

The full-swing memory array system500differs from the full-swing memory array system200in that one set of word line drivers510provides inputs to the dynamic OR component520. One local bit line540couples to global bit line553through tri-state inverter555and a separate global select line such as global select line550is used for each local bit line. The operation of full-swing memory array system500is similar to full-swing memory array system200. If the reference numbers are changed to correspond to elements inFIG. 5, the discussion of the timing diagram ofFIG. 3applies toFIG. 5as well.

FIG. 6illustrates details of a tri-state device suitable for use as tri-state inverter555shown inFIG. 5. Tri-state inverter555includes inverter605, a NAND gate620, and an AND gate630, a pull-up transistor640, and a pull-down transistor650. The tri-state inverter gate555receives as inputs the global select signal550and local bit line540and produces its output on global bit line553. Global bit line553couples to pull-up transistor640and pull-down transistor650.

Pull-up transistor640couples to the output of NAND gate620. NAND gate620couples to the output of inverter605and global select signal550. Inverter605couples to local bit line540. Pull-down transistor650couples to the output of AND gate630. AND gate630couples to the global select signal550and local bit line540.

Global bit line553is logic 1 when local bit line540is at logic 0 and global select signal550is at logic 1. Global bit line553is logic 0 when local bit line540and global select signal550are at logic 1. In any other combination of values inputted to tri-state inverter555, the value of global bit line553will be determined by an enabled tri-state inverter, such as tri-state inverter555, for example, which is also coupled to the global bit line553. If none of the tri-state inverters coupled to the global bit line553are enabled, global bit line553will maintain the last value read over it due to keeper cell560.

FIG. 7illustrates an alternative exemplary arrangement for generating a global select signal in accordance with an embodiment of the invention. The alternative embodiment may be used to generate a global select signal by using an encoded memory address rather than a decoded address and the dynamic OR components ofFIGS. 2 and 5. The exemplary embodiment shown inFIG. 7illustrates the read portion of a 32×32 full-swing memory array system700. The system700includes a 5×32 decoder705, sets of read word line drivers such as word line driver710, and a 32×32 full-swing memory array730modified according to the teachings of the invention.

The 5×32 decoder couples with the sets of read word line drivers. For purposes of simplicity of illustration only one set of word line drivers710is shown inFIG. 7. The sets of read word line drivers couple to the full swing memory array730. The 5×32 decoder receives an encoded memory address, S5-S1bits. The most significant bit, S5, for example, is coupled to tri-state NAND gate755through inverter720to generate a global select signal on global select line750A. Although not shown, global select line750A is also coupled to tri-state NAND gates corresponding to the other 31 bits in a 32 bit row in order to propagate an entire 32 bit word when a single read word line is activated. Tri-state NAND gate755couples to two local bit lines where each local bit line supports eight RAM cells. As such, global select line750A enables tri-state NAND gates which support the lower order, S5=0, 16 rows of memory.

The most significant bit, S5, is also directly coupled to tri-state NAND gate758which is also coupled to global select line750B. It should be noted that global select line750B also couples to tri-state NAND gates, not shown, which correspond to the other 31 bits in a 32 bit row. As such, global select line750B enables tri-state NAND gates which support the higher order, S5=1, 16 rows of memory.

It should be noted that other logical combinations of encoded address bits for generating global select signals are contemplated by the present invention and may differ according to different full swing memory array configurations. For example, a 64×32 full-swing memory array would utilize a 6×64 decoder. When utilizing a tri-state NAND gate embodiment such asFIG. 2, the two most significant bits of the six encoded address bits of the 6×64 decoder would be used to drive all the tri-state NAND gates. In general, the number of most significant address bits needed to control the tri-state NAND gates, n, is determined by the expression:
n=log2(R/br),   (3)
where R is the number of rows of the full-swing memory array and bris the number of RAM cells serviced by a tri-state device. For example, in a tri-state NAND gate embodiment of a 64×32 full-swing memory array system, n would equal log2(64 rows/16 RAM cells per tri-state NAND gate), which is 2 bits. By way of a tri-state inverter embodiment of a 64×32 full-swing memory array system, n would equal log2(64 rows/8 RAM cells per tri-state inverter gate), which is 3 bits.

FIG. 8is a flow chart illustrating a method800for statically switching a global bit line in accordance with an embodiment of the invention. At step810, a plurality of local bit lines is coupled to a global bit line through a plurality of tri-state devices. InFIG. 2, for example, two local bit lines couple through a tri-state NAND gate: to a global bit line. InFIG. 5, for example, one local bit line couples through a tri-state; inverter to a global bit line. At step820, a global select signal is generated to enable one of the plurality of tri-state devices. InFIG. 2, for example, the global select signal for a tri-state NAND gate is generated when one read word line out of two sets of word line drivers is activated. InFIG. 5, for example, the global select signal for a tri-state inverter is generated when one of the corresponding set of read word lines is activated.

At step830, a corresponding local bit line is selected to drive the output of the enable tri-state device. In the embodiment ofFIG. 2, the tri-state NAND propagates the active local bit line as described. In the embodiment ofFIG. 5, the tri-state inverter propagates the corresponding local bit line as described.

FIG. 9is a flow chart illustrating a method of reducing power when consecutively reading bits having the same value over a global bit line within memory in accordance with an embodiment of the invention. At step910, a global select signal is generated to transition the global bit line to a first level. Referring to time315of FIG.3, for example, global select signal250transitions to an active high level to enable tri-state NAND gate255, after local bit line240A has evaluated at time312. At step920, a first bit is read from memory. Referring to time320ofFIG. 3, for example, global bit line253transitions to a high value after NAND gate255has evaluated. At step930, a second bit from memory is read. The value of the second bit is the same value as the first bit read. Referring to time333ofFIG. 3, for example, global select signal250transitions to the active high level to again enable tri-state NAND gate255. At step940, the global bit line is maintained at the first level during the reading of the second bit without transitioning. Referring to time333ofFIG. 3, for example, global bit line253stays at the same level as it was at time320.

While the invention is disclosed in the context of a number of embodiments, it will be recognized that a wide variety of implementations may be employed by persons of ordinary skill in the art consistent with the above discussion and the claims which follow below.