Apparatus and method for controlling disk drive spin up

Disk drives in a storage system are spun up in sequential stages. During each sequential stage a number of disk drives is spun up based on parameters related to the power requirements of the system. The parameters include the maximum current for the storage system, the number of disk drives currently in steady state, the steady state current required for a disk drive, and the spin up current required for a disk drive. High availability features are provided as further aspects of the spin up mechanism.

FIELD OF THE INVENTION

The present invention relates generally to the field of storage systems, and particularly to mechanisms for controlling the timing of disk drive spin up in a storage system that supports many disk drives.

BACKGROUND OF THE INVENTION

Today's storage systems are used in computing environments for generating and storing large amounts of critical data. The storage capacity of these systems has increased over time such that some storage systems support many—sometimes hundreds—of disk drives. Because disk drives are mechanical devices, they have higher peak power requirements than the other electronic devices in the system. In today's market it is important to design the power subsystem portion of a storage system to support the maximum and peak power requirements of the system while minimizing the cost of the system.

A typical disk drive consists of circuit board logic and a Hard Disk Assembly (HDA). The HDA portion of the disk drive includes the spindles platters, head arm and motor that make up the mechanical portion of the disk drive. When power is applied to the disk drive, the circuit board logic powers up and the HDA spins up. During spin up, the HDA requires a higher current than when it is in steady state—i.e. already spun up. This extra current is typically more than two times the steady state current. Therefore, if a storage system at power up attempts to spin up all the drives in the system at the same time, the system is required to support a peak power level that is much greater than the maximum power required to operate at steady state. The more disk drives the system supports, the greater the peak power requirement. It is too expensive to provide a power subsystem that can support enough peak power to power up all disk drives at once, especially when the excess power is not otherwise needed.

Some types of disk drives offer a separate HDA power input but no built in control over the timing of the application of power to the HDA. Some other types offer limited control. For example, Fibre Channel disk drives compliant with the SFF-8045 rev. 4.7 standard allow the timing of HDA spin up to be controlled via two signal pins, Start_1and Start_2, that allow the HDA to spin up based on three different conditions. Depending on the state of the Start—1 and Start—2 signals, the disk drive HDA will start drawing current either 1) immediately; 2) after it receives its first SCSI command, or 3) based on its arbitrated loop physical address (ALPA). This provides limited means to stagger the timing of spin up amongst all the drives such that system peak power requirements can be minimized.

However, it is difficult for system software to use SCSI commands to control drive spin up timing, because insert and power control signals from the drives are asserted much faster than software can respond. The ALPA address method is also disadvantageous in some circumstances. Consider a storage system capable of supporting 48 disk drives. If a user plugs a single disk drive into the 48thslot in a system wherein the other drives are all at steady state, there is no reason why the drive should not spin up immediately. But because its spin up timing depends on its ALPA address, it will nonetheless take several minutes to spin up.

What is needed is a mechanism for controlling the application of power to the HDA portion of disk drives in a storage system. The mechanism must be more efficient than current methods and applicable regardless of the type of disk drives employed.

SUMMARY OF THE INVENTION

In accordance with the principles of the invention, disk drives in a storage system are spun up in sequential stages. During each sequential stage a number of disk drives are spun up based on parameters related to the power requirements of the system. The parameters include the maximum current for the storage system, the number of disk drives currently in steady state, the steady state current required for a disk drive, and the spin up current required for a disk drive.

More particularly, the number of disk drives to spin up in a stage is calculated as: (the maximum current for the storage system minus current used by logic in the system−(the number of disk drives currently in steady state times the steady state current required for a disk drive)) divided by the spin up current required for a disk drive.

Control logic for spinning up the drives produces Spin-up signals, wherein one of the Spin-up signals is asserted in each sequential stage. The Spin-up signal asserted in a stage causes a number of disk drives of the plurality of disk drives to spin up during the stage.

According to an aspect of the invention, second control logic produces second Spin-up signals corresponding to the first Spin-up signals. The second Spin-up signals are wire-or'd with the first Spin-up signals.

According to another aspect of the invention, the first control logic further includes registers corresponding to the Spin-up signals. Each Spin-up signal is an output from a corresponding register. A redundant plurality of power rails and a plurality of drivers are provided. Each Spin-up signal is coupled to one or more drivers. A first group of drivers is coupled to a first of the plurality of power rails and a second group of drivers is coupled to a second of the plurality of power rails.

According to a further aspect of the invention, disk drives inserted into an already powered up system are spun up in stages. Each disk drive provides a presence signal that is asserted when the disk drive is present. The first control logic provides a power control signal for each disk drive that causes power to be applied to the disk drive when the power control signal is asserted. The first control logic operates to monitor the presence signals. For each disk drive, if the presence signal is deasserted, the power control signal is deasserted. If any deasserted presence signal becomes asserted for a disk drive, assert the power control signal for the disk drive. If more than two deasserted presence signals become asserted for more than two corresponding disk drives, the first control logic asserts the power control signals for the corresponding drives in sequential stages.

The various aspects of the invention are employed to spin up groups of drives sequentially, and is applicable to all types of drives. Features of the invention provide high availability for the system during drive spin up.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Referring toFIG. 1, there is shown an example of a rack mount system10in which the present invention can be employed. A rack mount cabinet12includes several storage systems14. Each storage system14has installed therein several disk drives16. The amount of storage in the multi-chassis system can be increased by adding new storage systems14to the rack mount system10, and by adding more disk drives16to one or more of the storage systems14.

A functional block diagram of one of the storage systems14is shown inFIG. 2. The storage system14includes two redundant control cards18aand18bto provide high availability of the system. The control cards18a,bare coupled to a midplane20. Disk drives16, herein shown as15disk drives16.0–16.14, are also coupled to the midplane20. Each control card18a,bcommunicates with all the drives16.0–16.14via the midplane20. Power is supplied to the control cards18a,b, the midplane20, and the disk drives16by a redundant set of power supplies22a,b.

Since each storage system14can include up to15disk drives16, it is not reasonable to provide power supplies22a,bwith enough peak power to spin up all 15 disk drives at once. Therefore, in accordance with the principles of the invention, the disk drives16are spun up in sequential stages. During each sequential stage a certain number of disk drives16are spun up based on parameters related to the power requirements of the system as will be further described. This allows the system14to stagger the timing of spin up amongst all the drives16such that system peak power requirements can be minimized.

More particularly, in accordance with the invention, a certain number of disk drives16are spun up in each of several successive stages. The control logic26controls the timing of disk drive spin up. For example, as shown inFIG. 3, during a first stage, the control logic26causes a first number of disk drives16to spin up (step32). The control logic26then waits for a period of time, typically about 12 seconds, sufficient for the disk drives16to reach steady state (step34). During a next stage a second number of disk drives16is spun up (step36). The remaining drives16are spun up during successive sequential stages until all drives have been spun up (step38). Various system parameters are input to a formula that determines how many drives16should be spun up during a stage. The formula takes into account: the maximum steady state current in a system14; the peak available current in a system14; the number of drives16to be powered up in the system14; the spin up current requirement per drive16; the steady state current per drive16; and the current used by the control boards18a,18b. The following formula is iteratively solved to calculate the number of drives that should be spun up in each successive stage:

Cpeak=peak current available in chassis

Cmax=maximum steady state current in chassis

Ccc=control card current

Nc=number of drives currently on at steady state

Css=steady state current per drive

Csu=spin up current per drive

Nn=number of drives to spin up in next stage
Nn=Integer((Cmax−Ccc−(Nc*Css))/Csu)  (24)

In the generalized embodiment shown inFIG. 2, each controller board18a,18bincludes identical control logic26for driving Spin-up signals Spin-up_A–Spin-up_N to drivers28on the midplane20. The disk drives16are herein shown to be Fibre Channel drives. A Fibre Channel drive accepts as input two Start signals that switch on power to the HDA portion of the drive. (Start signals are referred to collectively; individual Start signals are referred to with a suffix.) The drivers28on the midplane20drive these pairs of Start signals to each of the drives. As shown, signals Start_8_1and Start_8_2are coupled to disk drive16.8, Start_9_1and Start_9_2are coupled to disk drive16.9. The remaining drives are coupled to their corresponding Start signals in a similar manner. When both Start signals for a given drive are asserted, the HDA portion of the drive spins up. The control logic26asserts each of the Spin-up signals Spin-up_A–Spin-up_N during successive stages in accordance with the above formula24. (Spin-up signals are referred to collectively; individual Spin-up signals are referred to with a capital letter suffix.) The Spin-up signals are used to drive the Start signals that control the spin up of the HDA portions of the drives16.

Referring toFIG. 4, there is shown one example embodiment of the invention. In this embodiment, the initial parameters are as follows:

Cpeak=42 A

Cmax=34 A

Ccc=2 (1 A per control card)

Css=1.6 A

Csu=4 A

In this embodiment, the system has sufficient maximum power (Cmax) to initially spin up 8 drives at once. (8 drives*4 A per drive=32 A<34A) Therefore drives16.0–16.7are shown coupled directly to power. The remaining drives16.8–16.14are spun up in a staggered manner in subsequent stages in accordance with the above formula. Solving for Nn shows that 3 subsequent stages are needed to power up all the drives. InFIG. 5, all 4 stages resulting from the solution to the formula are shown. The first, labeled “t0”, is the stage in which the initial 8 drives are spun up. During the next stage, “t1”, 4 additional drives can be spun up. Then, in stage “t2”, 2 more drives can be spun up. In the final stage “t3”, the last drive can be spun up.

InFIG. 4there is shown the control logic26and drivers28ofFIG. 2as implemented for this embodiment. Since the control logic26on the control cards18aand18bis the same, only one example of control logic26is shown in detail. In the embodiment shown, the Spin-up_A–Spin-up_C and Start—8—1–Start—14—2 signals are active low. Control logic26includes spin up logic40coupled to single bit registers42a–42c. Registers42a–42care coupled to inverters44a–44c. The inverters44a–44cdrive the signals Spin-up_A–Spin-up_C to the drivers28on the midplane20. The Spin-up_A–Spin-up_C signals from each controller board18aand18bare wire-or'd together on the midplane20. Therefore, it is preferable to implement the inverters44a–44cas open collector driver devices with pulled up outputs, particularly in an environment to be later described wherein the control cards18aand18bare hot-pluggable. The Spin-up_A signal is coupled to drivers28.1,28.2,28.3,28.4,28.5,28.6,28.7, and28.8which respectively drive the Start signals Start_8_1, Start_8_2, Start_9_1, and Start_9_2, Start_10_1, Start_10_2, Start_11_1and Start_11_2to the disk drives16.8,16.9,16.10, and16.11. The Spin-up_B signal is coupled to drivers28.9,28.10,28.11, and28.12, which respectively drive the Start signals Start_12_1, Start_12_2, Start_13_1, and Start_13_2to the disk drives16.12and16.13. The Spin-up_C signal is coupled to drivers28.13and18.14, which respectively drive the Start signals Start_14_1and Start_14_2to the disk drive16.14. The drives16.0–16.14are preferably hot-pluggable; therefore, the drivers28.1–28.14are also preferably open collector drivers with pulled-up outputs. After the initial 8 drives16.0–16.7are spun up during stage “t0”, the control logic26sequences the assertion of each of the Spin-up signals Spin-up_A–Spin-up_C such that each is asserted one stage after the last, in accordance with the control logic26functionality shown inFIG. 3. Drives16.8–16.14are thereby spun up in stages as shown inFIG. 5. Thus, as shown inFIGS. 3 and 5and at the bottom ofFIG. 4, the first 8 drives16.0–16.7are spun up during stage “t0” (step32). Then, during stage “t1”, the control logic26aasserts the signal Spin-up_A (step36), resulting in the assertion of the signals Start_8_1, Start_8_2, Start_9_1, Start_9_2, Start_10_1, Start_10_2, Start_11_1, and Start_11_2and thus the spin up of drives16.8,16.9,16.10, and16.11. During stage “t2”, the control logic asserts the signal Spin-up_B (step36), resulting in the assertion of the signals Start_12_1, Start_12_2, Start_13_1, and Start_13_2and thus the spin up of drives16.12and16.13. During “t3” (step36), the control logic asserts the signal Spin-up_C, resulting in the assertion of the signals Start_14_1and Start_14_2and thus the spin up of the final drive16.14.

In accordance with further aspects of the invention, the system includes several high availability features. First of all, system peak power (Cpeak), though not part of the formula24, is sufficient to power up extra drives16in case of a short or a stuck bit. Cpeak is therefore a parameter to be considered for high availability purposes. For example, in the system ofFIG. 4, if the signals Spin-up_A and Spin-up_B are shorted together, then two extra drives16.12and16.13will power up during stage “t1”. Or, if Spin-up_B is stuck low, then the two extra drives16.12and16.13will power up during stage “t0”. In either case, 8 additional amps will be drawn to spin up drives16.12and16.11. Note that since peak current (Cpeak) is 8 amps greater than maximum current (Cmax), and because staging of spin up has been designed not to exceed maximum current, there will be sufficient peak power to support spin up of the extra two drives16.12and16.13. Thus, no system failures will occur if one of the Spin-up bits Spin-up_A–Spin-up_C is stuck asserted or shorted to one of the others. Furthermore, if any of the outputs of the drivers28.1–28.14are stuck asserted, potentially causing a drive to spin up, sufficient peak current is available to prevent a system failure.

For further high availability, each bit register42and inverter44is implemented as a separate single bit part, rather than as a bit element of a multi-bit register or inverter. So, if a register42or inverter44fails such that its output is stuck asserted, the result is the same as was described with regard to the Spin-up signals: the resulting spin-up of extra drives16again draws less than peak available current and system failures are avoided.

To provide even further high availability, power is provided to the drivers28on the midplane20on separate power rails. Referring back toFIG. 2, recall that power is provided to the system14via two power supplies22aand22b. The power supplies are designed such that, when both are operating, each supply22aand22bprovides half the power for the system. But if one supply22aor22bfails, the other supply can provide full power for the system.

It can be seen that the previously presented formula for staging spin up of drives still applies in this environment. As shown inFIG. 6, each supply22a(labeled “Power Branch A”) and22b(labeled “Power Branch B”) supplies one half of Cmax and Cpeak, and supports half the control card18a,bamps. Each supply also provides half the total drive16current—or enough current to power 8 drives. Thus, as shown, each supply can initially spin up 4 drives during stage “t0”, 2 during stage “t1”, 1 during stage “t2”, and 1 during stage “t3”. Thus when both supplies are combined in the system the staging of spin up matches that shown inFIG. 5.

The use of two power supplies22aand22bfor supplying power on separate power rails provides an extra high availability advantage as shown inFIG. 7. In this arrangement, adjacent pairs of drives16receive their Start bits from different rails. As labeled at the bottom ofFIG. 7, the Start bits for drives16.2,16.3,16.6,16.7,16.10,16.11, and16.14are powered by Power Branch A, while the Start bits for drives16.0,16.1,16.4,16.5,16.8,16.9,16.12, and16.13are powered by Power Branch B. InFIG. 7A, driver49adrives the Start bits for drives16,2,16,3,16,6, and16,7from Power Branch A. Drive48bdrives the Start bits for drives16.0,16.1,16,4, and16.5from Power Branch B. InFIG. 7B, each package of drivers,50a,50b, and50cis for example implemented as a Texas Instruments 74LVC06, including 4 or 6 drivers28. Power rails and Spin-up_A–Spin-up_C signals are coupled to the driver packages50a–csuch that the Start bits to the drives are driven off the power rails Power Branch A or Power Branch B as described. Note that in the example ofFIG. 7, the Spin-up_C signal is coupled to the driver package50bso that the Start—14—1 and Start—14—2 signals are driven from Power Branch A.

It should be noted that the examples shown inFIGS. 4 and 7minimize the number of stages needed to spin up all the drives16in the system by spinning up as many drives16per stage as maximum current will allow. In other words, the results of the formula provide a maximum number of drives16than can be spun up per stage. There may be reasons other than power considerations for controlling the timing and order in which the drives16are spun up. For example, a design may require that certain pairs or groups of drives16spin up together. In accordance with the invention, drives16can be spun up in any number of stages as long as the maximum number of drives16spinning up in any given stage does not exceed the maximum provided by the formula24. In the example shown inFIGS. 8 and 9, the initial system parameters are the same as those forFIG. 7, but the drives16are spun up over two extra stages.

In this example, only six drives,16.0–16.5, are spun up in stage “t0”. The remaining 9 drives16.6–16.14are spun up over 5 successive stages. Control logic26includes spin up logic40coupled to registers42a–42e. Registers42a–42eare coupled to inverters44a–44e. The inverters44a–44edrive the signals Spin-up_A–Spin-up_E to the drivers28on the midplane20. Again, the Spin-up_A–Spin-up_E signals from each controller card18aand18bare wire-or'd together on the midplane20. The Spin-up_A signal is coupled to drivers28.1,28.2,28.3, and28.4, which respectively drive the Start signals Start_6_1, Start_6_2, Start_7_1, and Start_7_2to the disk drives16.6and16.7. The Spin-up_B signal is coupled to drivers28.5,28.6,28.7, and28.8, which respectively drive the Start signals Start_8_1, Start_8_2, Start_9_1, and Start_9_2to the disk drives16.8and16.9. The Spin-up_C signal is coupled to drivers28.9,28.10,28.13, and28.14, which respectively drive the Start signals Start_10_1, Start_10_2, Start_12_1, and Start_12_2to the disk drives16.10and16.12. The Spin-up_D signal is coupled to drivers28.11,28.12,28.15, and28.16, which respectively drive the Start signals Start_11_1, Start_11_2, Start_13_1, and Start_13_2to the disk drives16.11and16.13. The Spin-up_E signal is coupled to drivers28.17and28.18, which respectively drive the Start signals Start_14_1and Start_14_2to the disk drive16.14.

After the initial 6 drives16.0–16.5are spun up during stage “t0”, the control logic26sequences the assertion of each of the Spin-up signals Spin-up_A–Spin-up_E such that each is asserted one stage after the last. Drives16.6–16.14are thereby spun up in stages as shown inFIG. 8and at the bottom ofFIG. 9. The first 6 drives16.0–16.5are spun up during “t0”. Then, during “t1”, the spin up logic asserts the signal Spin-up_A, resulting in the assertion of the signals Start_6_1, Start_6_2, Start_7_1, and Start_7_2and the spin up of drives16.6and16.7. During “t2”, the spin up logic asserts the signal Spin-up_B, resulting in the assertion of the signals Start_8_1, Start_8_2, Start_9_1, and Start_9_2and thus the spin up of drives16.8and16.9. During “t3”, the spin up logic asserts the signal Spin-up_C, resulting in the assertion of the signals Start_10_1, Start_10_2, Start_11_1, and Start_11_2and thus the spin up of drives16.10and16.11. During “t4”, the spin up logic asserts the signal Spin-up_D, resulting in the assertion of the signals Start_12_1, Start_12_2, Start_13_1, and Start_13_2and thus the spin up of drives16.12and16.13. Finally during “t5” the signal Spin-up_E is asserted, resulting in the assertion of the signals Start_14_1and Start_14_2and thus the spin up of the final drive16.14.

The example ofFIG. 9also implements the high availability features ofFIG. 7. The Spin-up signals are coupled to separate single bit registers42and inverters44, and the driver packages50are coupled to different power rails “Power Branch A” and “Power Branch B”.

The control logic26of the previous examples can be implemented to perform the staging of the Spin-up signals in several ways. When all parameters used by the formula24are known to begin with, the formula can be used to pre-compute the minimum number of stages required and the maximum number of drives16that can be spun up in each stage. The control logic26can then be pre-configured to perform the resultant staging. Alternatively, the control logic26can be designed to measure the input parameters and execute the formula24dynamically. In this case, changes in the system14over time (e.g. number of control cards, maximum current, etc.) will by dynamically accounted for and staging will be configured in response to current system parameters.

The example ofFIG. 9will now be used to demonstrate the robustness of the spin up strategy of the invention. The system is preferably designed such that the control cards18aand18bcan be hot-plugged. That is, when the system is powered up, control cards can be plugged into and unplugged from the system. No failures should result in either scenario.

InFIG. 10, the drive spin up sequence is shown as performed by each of the two control cards18aand18bwhen the control card18bis plugged in after the control card18ahas begun the spin up sequencing. Remember that the Spin-up bits Spin-up_A–Spin-up_E from each control card are wire-or'd together on the midplane20. This means that the first control card18aor18bto assert a Spin-up bit causes the spin up of the drives16associated with that Spin-up bit. InFIG. 10, the control card18bis inserted half a stage time period after the first control card18apowered up. For example, if control card18astarts sequencing at “t0”, then control card18bstarts sequencing at “t0+6 seconds”. Half stage increments are therefore shown in the Figure for example as “t0.5”, “t1.5”, etc.

At “t0” the first 6 drives16.0–16.5spin up as previously described. At “t1” the signal Spin-up_A is asserted by the control card18aresulting in spin up of drives16.6and16.7. At “t2” the signal Spin-up_B is asserted by the control card18aresulting in spin up of drives16.8and16.9, and the sequencing of the Spin-up bits continues through Spin-up_E as previously described until all drives have spun up. Meanwhile, after the control card18aasserts Spin-up_A at “t1”, the control card18basserts Spin-up_A at “t1+0.5”. The re-assertion of Spin-up_A by the control card18bhas no effect on the already asserted Spin-up_A signal or on the already spinning up drives16.6and16.7. Likewise, the control card18bcontinues to assert the Spin-up signals after the control card18ahas already asserted them, having no effect on the system. Operation of disk drive spin up thus occurs within required power parameters during a hot plug.

Now consider what happens when a user pulls the first control card18aout of the system after the second control card18bhas been plugged in. The result is shown inFIG. 11. The first control card18ais unplugged at “t3”. After this, only the second control card18bdrives the Spin-up bits. As a result, the spin up of drives x.10–x.14is harmlessly delayed by half a stage.

In accordance with another aspect of the invention, a method is provided for controlling the spin up of drives16after the system14has initially powered up. The drives16in the system are preferably hot pluggable, meaning that drives16can be plugged into the system not only prior to power up but also at any time after it has been powered up. After the system has been powered up and after the requisite number of spin up stages has occurred, all Start bits are asserted. Other means is therefore provided for controlling spin up of newly inserted drives.

Drives16in accordance with the 8045 specification accept an input called Pwr_control. When the Pwr_control signal is asserted, power is provided to the entire drive16, including the logic board and HDA portions. When Pwr_control is deasserted, no power is provided to either the logic board or HDA. If the drive Start inputs are asserted, and the Pwr_control input is deasserted, the drive will not spin up. On the other hand, if the start bits are asserted, and then the Pwr_control input is asserted, the drive will spin up immediately in response to the assertion of Pwr_control.

As shown inFIG. 12, the system includes the control logic as shown inFIG. 2. The control logic26produces in addition Pctl signals Pctl_A–Pctl_O, which are used to drive Pwr_ctl—0–Pwer_ctl—14 signals to the drives16.0–16.14respectively. Each drive16.0–16.14provides a corresponding presence signal Drive_Insert_0–Drive_Insert_14, each of which is driven to the control logic26on each control card18a,18b. When a drive is inserted into the system, the corresponding Drive_Insert signal is asserted.

The additional control logic26functionality is shown inFIG. 13. When a control card18aor18bpowers up, the control logic26first checks all Drive_Insert—0–Drive Insert—14 signals. The control logic26de-asserts all Pwr_ctl signals for drives that are not inserted—i.e. drives whose Drive_Insert signals are deasserted (step60). Spin up sequencing as previously described is then performed. If any drives16are inserted after all Start bits have been asserted, those drives16will not spin up because their corresponding Pwr_ctl bits are deasserted.

Note particularly that, as previously described with regard to the current examples, a certain number of drives, for example drives16.0–16.5, are spun up immediately. However, if any of these drives are not installed, their corresponding Drive_Insert signals will be deasserted, causing their corresponding Pwr_ctl signals to be deasserted. If any such drives are later inserted, they are spun up as follows.

After sequencing is complete (step62), the control logic26monitors the Drive_Insert signals from the drives16. When the control logic26detects the deassertion of a previously asserted Drive_Insert signal (step63), it deasserts the corresponding pwr_ctl signal for the drive slot (step65). When the control logic26detects the assertion of a previously deasserted Drive_Insert signal (step64), it waits for a time period t (step66) to see if further drives are inserted. Upon expiration of the time period, the control logic asserts the Pwr_ctl signals for up to two newly inserted drives (step68). If more than two drives were inserted during the time period t (step70), then the Pwr_ctl signals corresponding to the newly inserted drives are asserted in stages two at a time until all inserted drives have been spun up. Particularly, after the initial two drives are spun up, the logic26waits for the expiration of the stage time period, again typically about 12 seconds (step72). Up to two Pwr_ctl signals are asserted for the newly asserted drives16(step74). This process continues until all newly inserted drives16have spun up (step76). The control logic26then continues to monitor for newly installed or removed drives (steps63,64).

More particularly, as shown inFIG. 14, the control logic26further includes power control logic78. The power control logic78accepts as input the Drive_Insert—14–Drive_Insert—0 signals from the disk drives16. The power control logic78drives registers80a–80o. Each register80a–80odrives a corresponding inverter82a–82o. The inverters produce as output P_Ctl signals P_Ctl_A–P_Ctl_O. Each signal P_Ctl_A–P_Ctl_O is input to a corresponding driver84a–84oon the midplane20. The other control card18balso produces the signals P_Ctl_A–P_Ctl_O, and these signals are wire-or'd to the corresponding signals from the control card18a. The inverters82a–82oare therefore preferably open collector drivers with pulled up outputs. The drivers84a–84ooutput Pwr_Ctl signals Pwr_Ctl_0–Pwr_Ctl_14, the Pwr_control signals for corresponding disk drives16.0–16.14. These drivers are also preferably pulled-up open collector drivers. The control logic78operates as shown inFIG. 13to assert groups of the P_Ctl signals in stages as disk drives16are inserted into the system. Corresponding Pwr_Ctl signals are asserted in response to cause the newly inserted drives16to spin up in stages in groups of two.

By example, referring toFIGS. 13 and 14, a system is initialized with drive slots16.8,16.9,16,10, and16.11empty. At power up the control logic26responds to the deasserted signals Drive_Insert_8–Drive_Insert_11by deasserting the P_Ctl_I, P_Ctl_J, P_Ctl_K, P_Ctl_L signals. The Pwr_Ctl—8, Pwr_Ctl—9, Pwr_Ctl—10, and Pwr_Ctl—11 signals are deasserted on the midplane20in response, preventing the drives—16.8–16.11from spinning up. Later, the four drives16.8–16.11are plugged into the system. The signals Drive_Insert_8–Drive_Insert_11are now asserted. In response to the assertion of the signals Drive_Insert_8–Drive_Insert_11, the control logic26asserts the signals P_Ctl_I, P_Ctl_J. The signals Pwr_Ctl_8and Pwr_Ctl_9are asserted in response, causing the Drives16.8and16.9spin up. After waiting for the stage period of time, the control logic26asserts the signals P_Ctl_K and, P_Ctl_L. The signals Pwr_Ctl_10and Pwr_Ctl_11are asserted in response, causing the Drives16.10and16.11to spin up.

High availability mechanisms are again employed in this example. Single bit registers and inverters are used. Separate power rails, though not shown, can be incorporated in a manner similar to the example ofFIG. 7.

The invention as shown inFIGS. 13 and 14is also useful for power toggling the drives16.0–16.14. This application is advantageous for example during error recovery. When one or more drives are inaccessible or otherwise not properly operating, software can attempt to reset the one or more drives by power-toggling them. In this case, if more than two drives are power-toggled, the staging mechanisms ofFIGS. 13 and 14will ensure that no more than two spin up at once.

The present invention is not to be limited in scope by the specific embodiments described herein. Various modifications of the present invention, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. For example, the embodiments shown use Fibre Channel drives. It will be clear to the skilled artisan that the principles of the invention can be used with any type of drive that allows separate power up of the HDA portion of the drive, and this indeed is one of the advantages of the invention. Furthermore, though the systems in the examples each support 15 disk drives, the formulas and other mechanisms of the invention clearly scale to any size storage system. All such modifications are intended to fall within the scope of the invention. Further, although aspects of the present invention have been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present invention can be beneficially implemented in any number of environments for any number of purposes.