Semiconductor memory device comprising three-dimensional memory cell array

A semiconductor memory device includes a substantially planar substrate, a memory string vertical to the substrate, the memory string comprising a plurality of storage cells, and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2009-0028159, filed on Apr. 1, 2009, and to Korean Patent Application No. 10-2009-0079243, filed on Aug. 26, 2009, the contents of which are incorporated by reference herein in their entireties.

BACKGROUND

The present disclosure relates to semiconductor devices, and more particularly, to semiconductor memory devices having an improved three-dimensional structure with distributed contact pads.

As the semiconductor industry continues its advance, higher integration of semiconductor devices, less power consumption and/or higher speeds may be required. In particular, since higher integration can increase the specifications of various electronic devices, and this is an important factor in determining product price, the importance of higher integration has been increasing. Thus, to realize such highly integrated semiconductor devices, semiconductor technology has advanced to permit semiconductor devices of diverse structures to be manufactured, thereby departing from traditional substantially flat or two-dimensional semiconductor devices.

As semiconductor devices become highly integrated and diverse semiconductor device structures emerge, it is increasingly difficult to secure process margins for connecting diverse and complex patterns in semiconductor devices to conductive lines and other patterns. If a failure occurs in a semiconductor device manufacturing process, the reliability of the semiconductor device decreases, which may cause lower performance of an electronic device incorporating the semiconductor device. Accordingly, it is desirable to enhance the reliability of highly integrated semiconductor devices by securing the process margins in semiconductor devices having complex patterns.

SUMMARY

One concept of the present disclosure relates to the connection between a cell array and a circuitry outside of the cell array. Therefore, the inventive concept of the present application should not be limited to vertical NAND or VNAND, and shall be understood to apply to three-dimensional memory devices such as RRAM, MRAM, PRAM, and the like. The present disclosure provides a formation method and resulting semiconductor device in accordance with the following exemplary embodiments.

According to an exemplary embodiment, a semiconductor memory device comprises a substantially planar substrate, a substantially planar substrate, a memory string vertical to the substrate, the memory string comprising a plurality of storage cells and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

A word line of the first group and a word line of the second group of word lines are alternatingly positioned with each other in the direction from top to bottom of the memory string. The inclination of the elongated memory string can be substantially 90 degrees relative to the planar substrate. The first side of the memory string may be opposite to the second side of the memory string.

The first portions of each of the plurality of word lines can be parallel to each other, respectively. The second portions of each of the plurality of word lines at the first side of the memory string can be parallel to each other, respectively, and the second portions of each of the plurality of word lines at the second side of the memory string can be parallel to each other, respectively.

The first alternating word lines can be disposed on odd numbered storage cells counting from top to bottom of the memory string, respectively, and the second alternating word lines can be disposed on even numbered storage cells counting from top to bottom of the memory string, respectively.

The device may further comprise insulating caps disposed at the elevated ends of the second portions of even numbered word lines at the first side of the memory string, and at the elevated ends of the second portions of odd numbered word lines at the second side of the memory string.

The device may further comprise a third group of word lines connected to a third conductive line disposed on a third side of the memory string, wherein the first group of word lines connect to modulus three remainder one numbered storage cells counting from top to bottom of the memory string, respectively, the second group of word lines connect to modulus three remainder two numbered storage cells counting from top to bottom of the memory string, respectively, and the third group of word lines connect to modulus three remainder zero numbered storage cells counting from top to bottom of the memory string, respectively.

Each of the plurality of storage cells and corresponding word lines may occupy a different plane disposed parallel to the plane of the substrate. Contiguous portions of a word line disposed in the same plane on different sides of the memory string can be electrically connected as one word line. The substrate can be horizontal when the memory string is vertical, and the device may further comprise a peripheral area disposed on a surface at or above the top of the vertical memory string.

The device may further comprise a plurality of conductive patterns for contact pads between the first alternating word lines and the first conductive lines, and between the second alternating word lines and the second conductive lines. The device may further comprise a peripheral area disposed above the planar substrate.

The peripheral area can be disposed in the same level as the lower surface of conductive patterns, or on top of the chamber. The inclined second portions of the word lines can be disposed at an inclination angle between about 50 and about 90 degrees relative to the substrate. Inclined second portions may extend from both ends of the first portion of each word line, and one of each pair of inclined second portions from each word line can be terminated with an insulating cap.

The device may further comprise a plurality of bit lines disposed substantially perpendicular to each of the memory string and the word lines. The device may further comprise a chamber having a silicon (Si) recess in the substrate, where the elongated memory string and elongated word lines can be disposed in the Si recess.

The device may further comprise a chamber having an insulating wall disposed on top of the substrate, where the elongated memory string and elongated word lines can be disposed within the periphery of the insulating wall. The elongated word lines may comprise metal or silicide. The memory string structure comprising the plurality of storage cells can be substantially columnar, pillar, tubular, or bar-sided.

The device may further comprise at least two row decoders, one row decoder disposed on the side of the odd numbered storage cells and another row decoder disposed on the side of the even numbered storage cells. A first of the two row decoders can be connected to either even or odd string select lines (SSLs) and even word lines, and a second row decoder of the two can be connected to either odd or even SSLs and odd word lines, respectively. A first row decoder of the two may be connected to all of the string select lines (SSLs) and either even or odd word lines, and a second row decoder of the two is connected to either odd or even word lines, respectively.

The substrate can comprise Si, the insulating layers can comprise SiO2, and the word lines can comprise metal. Each storage cell may comprise a control gate, a first insulating region, a charge storage region and a second insulating region. Each storage cell may comprise a metal gate as a control gate, a high-k region as a blocking layer, a nitride region as a charge storage layer, an oxide region as a tunnel layer.

According to an exemplary embodiment, a method of forming a semiconductor memory device comprises providing a substrate, forming a chamber on the substrate, depositing a plurality of alternating insulating layers and sacrificial layers in the chamber, each layer having a horizontal first portion and at least one inclined second portion, forming a hole substantially normal to the substrate and extending through the layers to the substrate, depositing a vertically inclined memory string into the hole, the memory string comprising a plurality of storage cells, replacing the sacrificial layers with conductive layers to form a plurality of elongated word lines, respectively, and connecting first alternating word lines of the plurality to conductive lines disposed at a first side of the memory string, and second alternating word lines of the plurality to conductive lines disposed at a second side of the memory string.

The method may further comprise forming a peripheral area on a surface at the level of the top of the memory string. The vertical memory string can be bar-sided; the method may further comprise forming a trench for x-cut to divide the memory string into two parallel strings. The substrate can comprise Si, the insulating layers can comprise SiO2, and the word lines can comprise metal. The chamber can be recessed directly into the substrate.

The chamber can be formed on top of the substrate by forming insulating sidewalls thereon. Each storage cell may comprise a metal gate as a control gate, a first insulating region, a charge storage region and a second insulating region. Each storage cell may comprise a metal gate as a control gate, a high-K region as a blocking layer, a nitride region as a charge storage layer and an oxide region as a tunnel layer.

According to an embodiment, a semiconductor memory device may comprise a substrate, a memory string disposed on and substantially normal to the substrate, the memory string comprising a plurality of storage cells, and a plurality of word lines, each word line includes a first portion substantially parallel to the substrate and coupled to the memory string and a second portion substantially inclined relative to the substrate and extending upwardly, wherein first alternating word lines of the plurality are electrically connected to first conductive lines disposed at a first side of the memory string, and second alternating word lines of the plurality are electrically connected to second conductive lines disposed at a second side of the memory string.

According to an exemplary embodiment, a semiconductor memory device comprises a substrate, a memory string disposed on and substantially normal to the substrate, the memory string comprising a plurality of storage cells, and a plurality of word lines, each word line includes a first portion substantially parallel to the substrate and coupled to the memory string and a second portion substantially inclined relative to the substrate and extending upwardly, wherein the word lines comprise first word lines selectively connected to first conductive lines disposed at a first side of the memory string, and second word lines selectively connected to second conductive lines disposed at a second side of the memory string.

The word lines may comprise at least one dummy word line. The first side may have a first row decoder and the second side may have a second row decoder.

According to an exemplary embodiment, a semiconductor memory device may comprise a substrate, a memory string disposed on and substantially normal to the substrate, the memory string comprising a plurality of storage cells, a plurality of word lines; and at least two row decoders, wherein word lines have a first group of word lines electrically connected to one row decoder at a first side of the memory string and a second group of word lines electrically connected to the other row decoder at a second side of the memory string. In the device as one embodiment of the present disclosure, the first row decoder is connected to one group of string select lines (SSLs) at a first side of the memory string, and the second row decoders is connected to another group of SSLs at a second side of the memory string. Alternatively, in the device of the present disclosure, either one of the two row decoders may be connected to all of the string select lines (SSLs).

According to an exemplary embodiment, a method of forming a semiconductor memory device comprises providing a substrate, forming a chamber on the substrate, depositing a plurality of alternating insulating layers and conductive layers in the chamber, the conductive layers forming a plurality of word lines, each layer having a horizontal first portion and at least one inclined second portion, forming a hole substantially normal to the substrate and extending through the layers to the substrate, depositing a vertically inclined memory string into the hole, the memory string comprising a plurality of storage cells, and connecting first alternating word lines of the plurality to contact pads disposed at a first side of the memory string, and second alternating word lines of the plurality to contact pads disposed at a second side of the memory string.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Exemplary embodiments of the present disclosure provide three-dimensional semiconductor memory structures with improved and distributed contact area margins. Particularly preferred embodiments exhibit improved contact process margins for greater reliability. In addition, the present disclosure provides a layout of connections between either word lines or word lines and string select lines, and at least two row decoders

Exemplary embodiments of the inventive concept are described in greater detail with reference to the accompanying drawings. The inventive concept may, however, be embodied in different forms and shall not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the inventive concept to those skilled in the art. In addition, since reference indicia such as numerals and/or characters are used for the exemplary embodiments, such reference numerals and/or characters provided according to the order of the explanation are not necessarily limited to that order. In the figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or feature, such as a layer or a film, is referred to as being ‘on’ another element or feature, such as another layer or a substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

A semiconductor device according to a first embodiment of the inventive concept will now be described.FIGS. 1A through 1Bshow a plan view for explaining a semiconductor device according to an embodiment of the inventive concept, andFIG. 2Ais a sectional view taken along the line I-I′ ofFIGS. 1A through 1B.

The semiconductor device of the present disclosure includes a memory cell array region, a row decoder, a column decoder, an interconnection to connect the memory cell array to outside element of the semiconductor device, for example a voltage generator or generating unit and a control unit. Interconnection may be connected to conductive via or plug, pad that vertically extends to other layers, patterns, or lines.

The semiconductor device of the present disclosure includes three dimensionally a plurality of memory cells. As one of our embodiment of the disclosure, the memory device includes a memory string that vertically extends on the planar substrate. The memory string may include a control gate, a first insulating layer, a charge storage layer, a second insulating layer, and an active region where a channel will be formed. A charge storage layer may be an insulating layer or nano-dots that can trap charges or any other information storage region may be changeable. The insulating layer for charge storage comprises silicon nitride or silicon oxy-nitride wherein the content of nitride is sufficiently richer that that of oxygen. A first insulating layer is positioned between the active region and the charge storage layer. The first insulating layer may comprise silicon oxide or thin (e.g., between about 5 and about 150 angstroms) multilayers comprising any of silicon oxide, silicon oxy-nitride and silicon nitride. The second insulating layer may be positioned between the charge storage layer and the control gate. The second insulating layer may be any of silicon oxide, high-k material, aluminum oxide and combination thereof.

The active region may be of various types. For example, the shape may be of pillar or columnar, tubular, or bar-sided shape. The tubular active region may surround a core of insulating material.

Referring toFIGS. 1A through 1Band2A, a substrate101is provided. The substrate101may be a semiconductor-based substrate and may be substantially planar. The substrate may be of silicon, preferably of monocrystalline Si. The substrate101may include a doped region for example a well that includes a first type dopant. A source region may be disposed in the substrate101. Some group of memory strings can share one source line, a common source line. The common source region may be disposed in a plate form or some portion within a cell region of the substrate. The common source region may include a high concentration of a second conductive type, which is different from the conductive type of the dopant included in the well. For example, in the case where the well includes a p-type dopant, the common source region may include a high concentration of n-type dopant.

The substrate101may be horizontally planar. The protruded portion may be formed on the substrate101. The protruded portion may be deposited on the substrate101. The material of the protruded portion may be of silicon or of insulating layer. The resultant surface includes a concave portion A, or a chamber from the planar substrate101and convex portion B from the protruded portion. The concave portion A may include a bottom surface103, and first and second sidewalls105and106facing each other. The resultant substrate101may include a convex portion or portions B extended from the first and second sidewalls105and106. A top surface of the convex portion B may be in parallel with the bottom surface103of the concave portion A. The concave portion A and the convex portion B may be alternatively formed by etching a portion of a semiconductor substrate corresponding to the concave portion A and leaving a portion of the semiconductor substrate corresponding to the convex portion B. In this case, the substrate101may be one body substrate. A memory cell may be disposed in the concave portion A. If the protruded portion may be formed of an insulating layer and peripheral circuitry is to be formed on the protruded portion, silicon layer is further formed on the protruded portion for Silicon on Insulator (SOI) type.

Next, the memory cell will be described. The concave portion A forming a chamber may have a first contact region CR1adjacent to the first sidewall105, and a second contact region CR2adjacent to the second sidewall106. A cell array region CAR may be disposed between the first contact region CR1and the second contact region CR2. That is, the first contact region CR1and the second contact region CR2may be spaced apart from each other with the cell array region CAR in-between. Conductive patterns GSL, WL1-WL4, SSL spaced apart from one another may be disposed on the substrate101. The conductive patterns GSL, WL1-WL4, SSL may include a ground select line GSL, word lines WL1-WL4, and a string select line (SSL), respectively on the concave portion A of the substrate101, which may be formed by sequentially stacking them along a resultant surface. Moreover, interlayer insulators may be disposed between the adjacent word lines for inhibiting unwanted short between such adjacent conductive patterns. The memory device of the present disclosure may comprise dummy word lines near GSL and/or SSL or between word lines. The word lines, GSL and SSL may be formed by stacking conductive lines and interlayer insulating layers. In another embodiment, stacking word lines, GSL and SSL and interlayer insulating layers may be conducted multiple times.

The memory array may be of three dimensional, which means that a plurality of memory cells that can store information may be disposed on and/or above the planar substrate. A switching element for activating a memory cell may be of a transistor or a diode type. The type of a memory cell may be volatile or non-volatile. For example, the memory device of the present disclosure may be a flash memory device.

The active memory string structure region for a three-dimensional memory may be parallel or vertical to the planar substrate101. Preferably, the active memory string structure may be vertical on the planar substrate. The active memory string structure may be formed of silicon; the shape of the active memory string structure may be columnar, pillar, tubular or bar-sided. The active memory string structure may be formed of monocrystalline silicon, polycrystalline silicon, or the like. The active memory string structure may be formed with amorphous silicon then transforming to polycrystalline silicon.

A memory string is vertical to the planar substrate, comprising a control gate, a first insulating layer, a charge storage layer, a second insulating layer, and an active memory string. A memory string has a first side and a second side. The insulating layer for charge storage comprises silicon nitride or silicon oxy-nitride wherein the content of nitride is sufficiently richer that that of oxygen. A first insulating layer is positioned between the active region and the charge storage layer. The first insulating layer may comprise silicon oxide or thin (e.g., between about 5 and about 150 angstroms) multilayers comprising any of silicon oxide, silicon oxy-nitride and silicon nitride. The second insulating layer may be positioned between the charge storage layer and the control gate. The second insulating layer may be any of silicon oxide, high-k material, aluminum oxide and combination thereof.

The conductive patterns GSL, for example, WL1-WL4, SSL are spaced apart from one another with inter-gate insulating layers111-116in-between. For example, the ground select line GSL, the first inter-gate insulating layer111, the first word line WL1, the second inter-gate insulating layer112, the second word line WL2, the third inter-gate insulating layer113, the third word line WL3, the fourth inter-gate insulating layer114, the fourth word line WL4, the fifth inter-gate insulating layer115and the string select line SSL may be sequentially stacked.

A ground select insulating layer110are disposed between the bottom surface103of the concave portion A, the first and second sidewalls105,106, and the ground select line GSL. A string select insulating layer116may be disposed on the string select line SSL. The insulating layers110-115include bottom portions above the bottom surface103of the concave portion A, and sidewall portions extended over the first sidewall105and the second sidewall106from the bottom portions thereof.

The conductive patterns GSL, WL1-WL4, SSL include bottom portions BP disposed above the bottom surface103of the concave portion A. The bottom portions BP may be in parallel with the bottom surface103.

The conductive patterns GSL, WL1-WL4, SSL may include upwardly inclining portions. The upwardly inclining portion may include contact inclining portion CT, which is extended over one of the first sidewall105and the second sidewall106from one ends of the bottom portions BP. A contact region where the inclining portion of any one of the conductive patterns is disposed may be different from a contact region where the inclining portion of another conductive pattern adjacent to the any one of the conductive patterns. For example, in the case where the contact inclining portion CT of the ground select line GSL is disposed in the first contact region CR1, the contact inclining portion CT of the first word line WL1adjacent to the ground select line GSL may be disposed in the second contact region CR2.

An extended line of the contact inclining portion CT may cross the bottom surface103. For example, the extended line may cross the bottom surface103at a right angle. In one embodiment of the present disclosure, a top surface of the contact inclining portion CT may be coplanar with the top surface of the convex portion B. An angle between the inclining portion CT and the bottom portion BP may be 50 to 90°.

The conductive patterns GSL, WL1-WL4, SSL may also include dummy inclining portions DCT extended over the other one of the first sidewall105and the second sidewall106from the other ends of the bottom portions BP on the bottom surface103. A contact region where the dummy inclining portion of any one of the conductive patterns GSL, WL1-WL4, SSL is disposed may be different from a contact region where the dummy inclining portion of another conductive pattern adjacent to the any one of the conductive patterns. For example, in the case where the dummy inclining portion DCT of the string select line SSL is disposed in the first contact region CR1, the dummy inclining portion DCT of the fourth word line WL4adjacent to the string select line SSL may be disposed in the second contact region CR2.

Each of the conductive patterns GSL, WL1-WL4, SSL may include one contact inclining portion CT and one dummy inclining portion DCT. In one of the conductive patterns GSL, WL1-WL4, SSL, a length of the dummy inclining portion DCT may be shorter than that of the contact inclining portion CT. The contact inclining portion CT may be disposed between the dummy inclining portions DCT adjacent to each other. The contact inclining portions CT adjacent to one of the dummy inclining portions DCT may be spaced apart from each other by the sidewalls of the insulating layers interposed therebetween. In other words, some group of word lines are connected to conductive lines at a first side of the memory string, and some group of word lines are connected to conductive lines at a second side of the memory string, thereby obtaining more contact margin for interconnection.

A dummy insulating layer pattern124may be disposed on the dummy inclining portion DCT. A top surface of the dummy insulating layer pattern124may be coplanar with the top surface of the convex portion B. The top surface of the dummy insulating layer pattern124may be coplanar with a top surface of the string select insulating layer116. Sidewalls of the dummy insulating layer pattern124may be coplanar with sidewalls of the dummy inclining portion DCT. The dummy insulating layer pattern124may include the same material as the insulating layers110-116.

Conductive plugs may be disposed on the contact inclining portions CT of the word lines WL1-WL4, respectively. The conductive plugs may be word line contact plugs CP. The word lines WL1-WL4may be electrically connected with the word line contact plugs CP, respectively. Widths of the word line contact plugs CP may be wider than those of the top surfaces of the contact inclining portions CT of the word lines WL1-WL4. The widths of word line contact plugs CP may be greater than widths between the dummy inclining portions DCT adjacent to the contact inclining portions CT of the word lines WL1-WL4. The word line contact plugs CP may penetrate a first interlayer insulating layer160. First conductive lines ML1may be disposed on the word line contact plugs CP and the first interlayer insulating layer160. The word line contact plugs CP may be electrically connected with the first conductive lines ML1. Some of the first conductive lines ML1may extend in a first direction. Other first conductive lines ML1may extend in a second direction opposite to the first direction. For example, the first conductive lines ML1connected with the word lines WL2, WL4positioned at odd-numbered layers of the conductive patterns above the substrate101may extend in the first direction, and the first conductive lines ML1connected with the word lines WL1, WL3positioned at even-numbered layers of the conductive patterns above the substrate101may extend in the second direction. The first direction may be a direction from I′ to I. The first conductive lines ML1may be electrically connected with the word lines WL1-WL4through the word line contact plugs CP. Alternatively, the first conductive lines ML1may be directly connected with the word lines WL1-WL4. A second interlayer insulating layer170covering the first conductive lines ML1may be disposed. The first and second interlayer insulating layers160and170may include the same material.

A conductive plug may be disposed on the contact inclining portion CT of the ground select line GSL. The conductive plug may be a ground select contact plug GCP. The ground select line GSL may be electrically connected with the ground select contact plug GCP. A width of the ground select contact plug GCP may be wider than a width of a top surface of the contact inclining portion CT of the ground select line GSL. The ground select contact plug GCP may penetrate the first interlayer insulating layer160. A second conductive line ML2may be disposed on the ground select contact plug GCP and the first interlayer insulating layer160. The ground select contact plug GCP may be electrically connected with the second conductive line ML2. The second conductive line ML2may extend in the first direction. The second conductive line ML2may be electrically connected with the ground select line GSL through the ground select contact plug GCP. Alternatively, the ground select line GSL may be directly connected with the second conductive line ML2. The second interlayer insulating layer170may cover the second conductive line ML2.

A conductive plug may be disposed on the contact inclining portion CT of the string select line SSL. The conductive plug may be a string select contact plug SCP. The string select line SSL may be electrically connected with the string select contact plug SCP. A width of the string select contact plug SCP may be wider than a width of a top surface of the contact inclining portion CT of the string select line SSL. The string select contact plug SCP may penetrate the first interlayer insulating layer160and the second interlayer insulating layer170. A third conductive line ML3may be disposed on the string select contact plug SCP, the second interlayer insulating layer170. The string select contact plug SCP may be electrically connected with the third conductive line ML3. The third conductive line ML3may extend in the second direction. Referring toFIG. 1B, a plurality of the string select line SSL may dispose in the concave portion. And the third conductive lines ML3of the string select lines SSL adjacent to each other may extend different direction. In another embodiment of the present disclosure, conductive pads may be interposed between a contact pad and contact inclining portion CT.

The conductive lines ML1-ML3may extend separated in the first and second directions with the cell array region CAR in-between. For example, the conductive lines ML1, ML2connected with the conductive patterns GSL, WL2, WL4of which the contact inclining portions CT are disposed in the first contact region CR1may extend in the first direction, and the conductive lines ML2, ML3connected with the conductive patterns WL1, WL3, SSL of which the contact inclining portions CT are disposed in the second contact region CR2may extend in the second direction.

As one embodiment of the present disclosure, an active memory string structure extending upward from the bottom surface103of the concave portion A may be disposed. The active memory string structure extends vertical to the substrate101, penetrating the conductive patterns GSL, WL1-WL4, SSL so that one end of the active memory string structure may be electrically connected with the common source region. A drain region D may be disposed at the other end of the active memory string structure. The drain region D may be a region doped with a high concentration of dopant. For example, the active memory string structure may be of n doped type.

A bit line contact plug BLCP may be disposed on the drain region D of the active memory string structure. The bit line contact plug BLCP may be electrically connected with the drain region D and penetrate the first interlayer insulating layer160. A bit line BL may be disposed on the bit line contact plug BLCP. The bit line BL may be connected with the drain region D of the active memory string structure through the bit line contact plug BLCP. Unlike this, the bit line BL may be directly connected with the drain region D. The bit line BL may extend in a third direction crossing the first and the second direction. The third direction may cross the first and second direction at a right angle. The bit line BL may cross the string select line SSL.

An information storage layer132may be disposed between a sidewall of the active memory string structure and the conductive patterns GSL, WL1-WL4, SSL. The information storage layer132may be provided in a cylindrical type penetrating the conductive patterns GSL, WL1-WL4, SSL. The information storage layer132may be provided to surround the active memory string structure. The information storage layer132may be disposed between the sidewall of the active memory string structure and the conductive patterns GSL, WL1-WL4, SSL and the insulating layers110-116.

The active memory string, the information storage layer and the conductive patterns according to a first embodiment of the inventive concept will be specifically described.FIG. 3is a view for explaining an information storage layer according to a first embodiment of the inventive concept.

Referring toFIG. 3, the information storage layer132may include a tunnel insulating layer136, a charge storage layer135and a blocking layer134.

Referring toFIGS. 1A and 1B, an interconnection, extending outside one edge of the cell array portion, is electrically connected to contact inclining portion of a word line at one side, whereas another interconnection, extending outside the other edge of the cell array portion, is electrically connected to contact inclining portion of a word line at another side. According toFIG. 1A, all SSLs are connected to interconnections at either side, whereas some SSLs are connected to interconnections at one side, and some SSLs are connected to interconnections at another side forFIG. 1B. The word line may be chosen alternatingly. That is, odd numbered word lines from bottom to top direction of a string for example, first, third, fifth word lines are connected to interconnections at one side of a string, and even numbered word lines for example, second, fourth, sixth word lines connected to interconnections at the other side of a string.

The tunnel insulating layer136may cover the sidewalls of the active memory string structure. The tunnel insulating layer136may have a single layer structure or a multilayer structure. The tunnel insulating layer136may include at least one selected from the group consisting of a silicon oxy-nitride layer, a silicon nitride layer, a silicon oxide layer and a metal oxide layer.

The charge storage layer135may cover the tunnel insulating layer136. The charge storage layer135may be spaced apart from the active memory string structure by the tunnel insulating layer136. The charge storage layer135may include charge trap sites, which can store charges. For example, the charge storage layer135may include at least one selected from the group consisting of a silicon nitride layer, a metal nitride layer, a metal oxy-nitride layer, a metal silicon oxide layer, a metal silicon oxy-nitride layer and nanodots.

The blocking layer134may be disposed between the charge storage layer135and the conductive patterns GSL, WL1-WL4, SSL. The blocking layer134may be disposed between the charge storage layer135and the insulating layers110-116. The blocking layer134may cover the charge storage layer135. The blocking layer134may include at least one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer and high-k dielectric. The high-k insulating layers may include hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), lanthanum (La), Cerium (Ce), praseodymium (Pr) or the like. A dielectric constant of the blocking layer134may be higher than that of the tunnel insulating layer136.

A modified example of the first embodiment of the inventive concept will now be described.FIG. 2Bis a sectional view taken along line I-I′ ofFIG. 1, for explaining a modified example of the first embodiment of the inventive concept.

Referring toFIGS. 1 and 2B, a substrate100is provided. A common source region may be disposed in the substrate100. The substrate100may include a concave portion A. The concave portion A may include a bottom surface103, and first and second sidewalls105and106facing each other. The substrate100may include a convex portion B extending from the first and second sidewalls105and106. The convex portion B may be defined by an insulating layer104on the substrate100.

A memory cell may be disposed in the concave portion A. The concave portion A may include a first contact region CR1adjacent to the first sidewall105, and a second contact region CR2adjacent to the second sidewall106. The memory cell may be the memory cell explained with reference toFIG. 2A.

A semiconductor device according to another modified example of the first embodiment of the inventive concept will now be described.FIG. 2Cis a sectional view taken along line I-I′ ofFIG. 1AthroughFIG. 1B, for showing another modified example of the first embodiment of the inventive concept.

Referring toFIGS. 1A through 1Band2C, a substrate101is provided. A common source region may be disposed in the substrate101. The substrate101may include a concave portion A. The concave portion A may include a bottom surface103, and first and second sidewalls105and106facing each other. Any one of the first and second sidewalls105and106may be inclined to the bottom surface103of the concave portion A. For example, the first sidewall105and the second sidewall106may have an angle, which is 50° to 90° with respect to the bottom surface103. A slope of the first sidewall105with respect to the bottom surface103may be equal to that of the second sidewall106with respect to the bottom surface103. Alternatively, the slope of the first sidewall105with respect to the bottom surface103may be different from that of the second sidewall106with respect to the bottom surface103. The substrate101may include a convex portion B extending from the first and second sidewalls105and106. A top surface of the convex portion B may be in parallel with the bottom surface103of the concave portion A. The concave portion A and the convex portion B of the substrate101may be defined through an etching process. Alternatively, as described with reference toFIG. 2B, the convex portion B may be defined by the insulating layer104on the substrate100.

A memory cell may be disposed in the concave portion A. The memory cell will now be described. The memory cell may be the memory cell explained with reference toFIG. 2A. The concave portion A may have a first contact region CR1adjacent to the first sidewall105, and a second contact region CR2adjacent to the second sidewall106. A contact inclining portion CT and a dummy inclining portion DCT of any one of the conductive patterns GSL, WL1-WL4, SSL may have an inclined slope with respect to a bottom portion BP.

An angle between the sidewall adjacent to the contact region where the contact inclining portion CT is disposed and the bottom surface103may be equal to an angle between the contact inclining portion CT and the bottom portion BP. For example, in the case of the first word line WL1, a slope of the contact inclining portion CT with respect to the bottom portion BP may be equal to a slope of the second sidewall106with respect to the bottom surface103. When the slopes of the first sidewall105and the second sidewall106with respect to the bottom surface103are different from each other, in any one conductive pattern, the slope of the contact inclining portion with respect to the bottom portion BP may be different from the slope of the dummy inclining portion DCT with respect to the bottom portion BP.

FIG. 1aillustrates a memory device wherein the memory device comprises at least two row decoder assigned to a cell array and all of the string select lines (SSL) are connected to one row decoder whereasFIG. 1billustrates a memory device wherein the even string select lines are connected to one row decoder and the odd string select lines are connected to the other row decoder.

A semiconductor device according to a second embodiment of the inventive concept will now be described.FIG. 4AthroughFIG. 4Bis a plan view for explaining a semiconductor device according to a second embodiment of the inventive concept, andFIG. 5Ais a sectional view taken along line II-II′ ofFIGS. 4A through 4B.

Referring toFIGS. 4A through 4Band5A, a substrate201is provided. The substrate201may be a semiconductor-based substrate. The substrate201may include a doped well. The well may include a first conductive type dopant. A common source region202may be disposed in the substrate201. The common source region202may be disposed in a plate form within a cell region of the substrate201. The common source region202may include a high concentration of dopant. The dopant included in the common source region202may have a second conductive type, which is different from the conductive type of the dopant included in the well. For example, in the case where the well includes a p-type dopant, the common source region202may include a high concentration of n-type dopant.

The substrate201may include a concave portion A. The concave portion A may include a bottom surface203, and first and second sidewalls205and206facing each other. The substrate201may include a convex portion B extended from the first and second sidewalls205and206. A top surface of the convex portion B may be in parallel with the bottom surface of the concave portion A. The concave portion A and the convex portion B may be formed by etching a portion of a semiconductor substrate corresponding to the concave portion A and leaving a portion of the semiconductor substrate corresponding to the convex portion B. In this case, the substrate201may be one body substrate. A memory cell may be disposed in the concave portion A.

The concave portion A may include a first contact region CR1adjacent to the first sidewall205, and a second contact region CR2adjacent to the second sidewall206. A cell array region CAR may be disposed between the first contact region CR1and the second contact region CR2. The first contact region CR1and the second contact region CR2may be spaced apart from each other with the cell array region CAR in-between.

Conductive patterns GSL, WL1-WL4, SSL spaced apart from one another may be disposed on the substrate201. The conductive patterns GSL, WL1-WL4, SSL may include a ground select line GSL, word lines WL1-WL4, and a string select line SSL, which are sequentially stacked on the concave portion A of the substrate201. The conductive patterns GSL, WL1-WL4, SSL may be spaced apart from one another with inter-gate insulating layers210-214in-between. For example, the ground select line GSL, the first inter-gate insulating layer210, the first word line WL1, the second inter-gate insulating layer211, the second word line WL2, the third inter-gate insulating layer212, the third word line WL3, the fourth inter-gate insulating layer213, the fourth word line WL4, the fifth inter-gate insulating layer214and the string select line SSL may be sequentially stacked. The insulating layers210-214may include bottom portions above the bottom surface203of the concave portion A of the substrate201, and sidewall portions extended over the first sidewall205and the second sidewall206from the bottom portions thereof. A string select insulating layer215may be disposed on the string select line SSL. The conductive patterns GSL, WL1-WL4, SSL may have a line form extending in a first direction. The first direction may be a direction of line II-II′. That is, the memory device of this embodiment is the device that includes a trench for x-cut thereby separating word line plate in a cell array memory. The separated word lines of substantially same level are electrically connected each other and will act as one word line plate.

The conductive patterns GSL, WL1-WL4, SSL may include bottom portions BP disposed above the bottom surface203of the concave portion A. Lengths of the bottom portions BP may be shortened as it goes far from the concave portion A of the substrate201. The bottom portions BP may be in parallel with the bottom surface203. The bottom portions BP may be in parallel with the top surface of the convex portion B.

The conductive patterns GSL, WL1-WL4, SSL may include contact inclining portions CT extended over one of the first sidewall205and the second sidewall206from one ends of the bottom portions BP. A contact region where the contact inclining portion of any one of the conductive patterns is disposed may be different from a contact region where the contact inclining portion of another conductive pattern adjacent to the any one of the conductive patterns. For example, in the case where the contact inclining portion CT of the ground select line GSL is disposed in the first contact region CR1, the contact inclining portion CT of the first word line WL1adjacent to the ground select line GSL may be disposed in the second contact region CR2.

An extended line of the contact inclining portion CT may cross the bottom surface203, for example, at a right angle. A length of the contact inclining portion CT may be decreased as it goes far from the concave portion A. A top surface of the contact inclining portion CT may be coplanar with the top surface of the convex portion B. An angle between the contact inclining portion CT and the bottom portion BP may be 90°.

The conductive patterns GSL, WL1-WL4, SSL may include dummy inclining portions DCT extended over the other one of the first sidewall205and the second sidewall206from the other ends of the bottom portions BP on the bottom surface203. A contact region where the dummy inclining portion of any one of the conductive patterns GSL, WL1-WL4, SSL is disposed may be different from a contact region where the dummy inclining portion of another conductive pattern adjacent to the any one of the conductive patterns. For example, in the case where the dummy inclining portion DCT of the string select line SSL is disposed in the first contact region CR1, the dummy inclining portion DCT of the fourth word line WL4adjacent to the string select line SSL may be disposed in the second contact region CR2.

Each of the conductive patterns GSL, WL1-WL4, SSL may include one contact inclining portion CT and one dummy inclining portion DCT. In one of the conductive patterns GSL, WL1-WL4, SSL, a length of the dummy inclining portion DCT may be shorter than that of the contact inclining portion CT. The contact inclining portion CT may be disposed between the dummy inclining portions DCT adjacent to each other. The contact inclining portions CT adjacent to one of the dummy inclining portions DCT may be spaced apart from each other by the sidewalls of the insulating layers interposed therebetween.

A dummy insulating layer pattern264may be disposed on the dummy inclining portion DCT. A top surface of the dummy insulating layer pattern264may be coplanar with the top surface of the convex portion B. The top surface of the dummy insulating layer pattern264may be coplanar with a top surface of the string select insulating layer215. Sidewalls of the dummy insulating layer pattern264may be coplanar with sidewalls of the dummy inclining portion DCT. The dummy insulating layer pattern264may include the same material as the insulating layers210-215.

Conductive plugs may be disposed on the contact inclining portions CT of the word lines WL1-WL4, respectively. The conductive plugs may be word line contact plugs CP. The word lines WL1-WL4may be electrically connected with the word line contact plugs CP, respectively. Widths of the word line contact plugs CP may be wider than those of the top surfaces of the contact inclining portions CT of the word lines WL1-WL4. The widths of the word line contact plugs CP may be wider than widths between the dummy inclining portions DCT adjacent to the contact inclining portions of the word lines WL1-WL4. The word line contact plugs may penetrate a first interlayer insulating layer280. First conductive lines ML1may be disposed on the word line contact plugs CP and the first interlayer insulating layer280. The word line contact plugs CP may be electrically connected with the first conductive lines ML1. The first conductive lines ML1may extend in a second direction crossing the first direction. The first conductive lines ML1may be electrically connected with the word lines WL1-WL4through the word line contact plugs CP. Unlike this, the first conductive lines ML1may be directly connected with the word lines WL1-WL4. A second interlayer insulating layer290covering the first conductive lines ML1may be disposed. The first and second interlayer insulating layers280and290may include the same material.

A conductive plug may be disposed on the contact inclining portion CT of the ground select line GSL. The conductive plug may be a ground select contact plug GCP. The ground select line GSL may be electrically connected with the ground select contact plug GCP. A width of the ground select contact plug GCP may be wider than a width of a top surface of the contact inclining portion CT of the ground select line GSL. The ground select contact plug GCP may penetrate the first interlayer insulating layer280. A second conductive line ML2may be disposed on the ground select contact plug GCP and the first interlayer insulating layer280. The ground select contact plug GCP may be electrically connected with the second conductive line ML2. The second conductive line ML2may extend in the second direction. The second conductive line ML2may be electrically connected with the ground select line GSL through the ground select contact plug GCP. Unlike this, the ground select line GSL may be directly connected with the second conductive line ML2. The second interlayer insulating layer290may cover the second conductive line ML2.

A conductive plug may be disposed on the contact inclining portion CT of the string select line SSL. The conductive plug may be a string select contact plug SCP. The string select line SSL may be electrically connected with the string select contact plug SCP. A width of the string select contact plug SCP may be wider than a width of a top surface of the contact inclining portion CT of the string select line SSL. The string select contact plug SCP may penetrate the first interlayer insulating layer280and the second interlayer insulating layer290. A third conductive line ML3may be disposed on the string select contact plug SCP and the second interlayer insulating layer290. The string select contact plug SCP may be electrically connected with the third conductive line ML3. The third conductive line ML3may extend in the first direction. Referring to theFIG. 4B, a plurality of the string select line SSL may dispose in the concave portion. And the third conductive lines ML3of the string select lines SSL adjacent to each other may extend different direction.

The conductive lines ML1, ML2may be disposed separated in both sides with the cell array region CAR in-between. The conductive line connected with one of the conductive patterns GSL, WL1-WL4may be disposed in a contact region different from the conductive line connected with the conductive pattern adjacent to the one conductive pattern. For example, the first conductive line ML1connected with the first word line WL1may be disposed in the second contact region CR2, and the second conductive line ML2and the first conductive line ML1respectively connected with the ground select line GSL and the second word line WL2adjacent to the first word line WL1may be disposed in the first contact region CR1.

An active memory string structure extending upward from the bottom surface203of the concave portion A may be disposed. The active memory string structure may extend perpendicular to the substrate201. The active memory string structure may penetrate the conductive patterns GSL, WL1-WL4, SSL. Unlike this, the active memory string structure faces the sidewalls of the conductive patterns GSL, WL1-WL4, SSL. One end of the active memory string structure may be electrically connected with the common source region202. A drain region D may be disposed at the other end of the active memory string. The drain region D may be a region doped with a high concentration of dopant. The active memory string structure may include a single crystalline semiconductor.

A bit line contact plug BLCP may be disposed on the drain region D of the active memory string structure. The bit line contact plug BLCP may be electrically connected with the drain region D and penetrate the first interlayer insulating layer280. A bit line BL may be disposed on the bit line contact plug BLCP. The bit line BL may be connected with the drain region D of the active memory string structure through the bit line contact plug BLCP. Unlike this, the bit line BL may be directly connected with the drain region D. The bit line BL may extend in the second direction. The bit line BL may cross the third conductive line ML3.

An information storage layer240may be disposed between the sidewall of the active memory string structure and the conductive patterns GSL, WL1-WL4, SSL. The information storage layer240may be disposed between the conductive patterns GSL, WL1-WL4, SSL and the insulating layers210-215.

The active memory string, the information storage layer and the conductive patterns according to a second embodiment of the inventive concept will be specifically described.FIG. 6Ais a view for explaining an information storage layer according to a second embodiment of the inventive concept.

FIG. 4aillustrates a memory device wherein the memory device comprises at least two row decoder assigned to a cell array and all of the string select lines (SSL) are connected to one row decoder whereasFIG. 4billustrates a memory device wherein the even string select lines are connected to one row decoder and the odd string select lines are connected to the other row decoder.

Referring toFIG. 6A, the information storage layer240may include a tunnel insulating layer242, a charge storage layer244and a blocking layer246.

The tunnel insulating layer242may cover the sidewall of the active memory string structure. The tunnel insulating layer242may have a single layer structure or a multilayer structure. For example, the tunnel insulating layer242may include at least one selected from the group consisting of a silicon oxy-nitride layer, a silicon nitride layer, a silicon oxide layer and a metal oxide layer.

The charge storage layer244may cover the tunnel insulating layer242. The charge storage layer244may be spaced apart from the active memory string structure by the tunnel insulating layer242. The charge storage layer244may include charge trap sites, which can store charges. For example, the charge storage layer244may include at least one selected from the group consisting of a silicon nitride layer, a metal nitride layer, a metal oxy-nitride layer, a metal silicon oxide layer, a metal silicon oxy-nitride layer and nanodots.

The blocking layer246may be disposed between the charge storage layer244and the conductive patterns GSL, WL1-WL4, SSL. The blocking layer246may be disposed between the charge storage layer244and the insulating layers210-215. The blocking layer246may cover the charge storage layer244. The blocking layer246may include at least one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer and high-k insulating layers. The high-k insulating layers may include hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), lanthanum (La), Cerium (Ce), praseodymium (Pr) or the like. A dielectric constant of the blocking layer246may be higher than that of the tunnel insulating layer242.

A modified example of the active according to the second embodiment of the inventive concept will be described.FIG. 6Bis a partial perspective view for explaining an active according to a modified example of the second embodiment of the inventive concept.

Referring toFIG. 6B, an information storage layer240including the tunnel insulating layer242, the charge storage layer244and the blocking layer246described with reference toFIG. 6Ais disposed between the conductive patterns WL1, GSL and the active memory string structure. The active memory string structure may face sidewalls of the bottom portions BP of the conductive patterns GSL, WL1.

A modified example of the second embodiment of the inventive concept will now be described.FIG. 5Bis a sectional view taken along line II-II′ ofFIGS. 4A through 4B, for explaining a modified example of the second embodiment of the inventive concept.

Referring toFIGS. 4 and 5B, a substrate200is provided. A common source region202may be disposed in the substrate200. The substrate200may include a concave portion A. The concave portion A may include a bottom surface203, and first and second sidewalls205and206facing each other. The substrate200may include a convex portion B extending from the first and second sidewalls205and206. A top surface of the convex portion B may be in parallel with the bottom surface203of the concave portion A. The convex portion B may be defined by an insulating layer204disposed on the substrate200.

A memory cell may be disposed in the concave portion A. The concave portion A may include a first contact region CR1adjacent to the first sidewall205, and a second contact region CR2adjacent to the second sidewall206. The memory cell may be the memory cell explained with reference toFIG. 5A.

A semiconductor device according to another modified example of the second embodiment of the inventive concept will now be described.FIG. 5Cis a sectional view taken along line II-II′ ofFIG. 4, for showing another modified example of the second embodiment of the inventive concept.

Referring toFIGS. 4 and 5C, a substrate201is provided. A common source region202may be disposed in the substrate201. The substrate201may include a concave portion A. The concave portion A may include a bottom surface203, and first and second sidewalls205and206facing each other. Any one of the first and second sidewalls205and206may be inclined to the bottom surface203of the concave portion A. For example, the first sidewall205and the second sidewall206may have an angle, which is 50° and less than 90° with respect to the bottom surface203. A slope of the first sidewall205with respect to the bottom surface203may be equal to that of the second sidewall206with respect to the bottom surface203. Alternatively, the slope of the first sidewall205with respect to the bottom surface203may be different from that of the second sidewall206with respect to the bottom surface203. The substrate201may include a convex portion B extending away from the first and second sidewalls205and206. A top surface of the convex portion B may be in parallel with the bottom surface203of the concave portion A. The concave portion A and the convex portion B of the substrate201may be defined through an etching process. Alternatively, as described with reference toFIG. 5B, the convex portion B may be defined by the insulating layer204on the substrate200.

A memory cell may be disposed in the concave portion A. The memory cell will now be described. The memory cell may be the memory cell explained with reference toFIG. 5A. The concave portion A may have a first contact region CR1adjacent to the first sidewall205, and a second contact region CR2adjacent to the second sidewall206. A contact inclining portion CT and a dummy inclining portion DCT of any one of the conductive patterns GSL, WL1-WL4, SSL may have an inclined slope with respect to a bottom portion BP.

An angle between the sidewall adjacent to the contact region where the contact inclining portion CT is disposed and the bottom surface203may be equal to an angle between the contact inclining portion CT and the bottom portion BP. For example, in the case of the first word line WL1, a slope of the contact inclining portion CT with respect to the bottom portion BP may be equal to a slope of the second sidewall206with respect to the bottom surface203. When the slopes of the first sidewall205and the second sidewall206with respect to the bottom surface203are different from each other, in any one conductive pattern, the slope of the contact inclining portion with respect to the bottom portion BP may be different from the slope of the dummy inclining portion DCT with respect to the bottom portion BP.

Referring toFIGS. 6aand6b, an active may be formed of silicon, the shape of the active region may be of pillar, tubular or bar-sided shape. The active may be formed of monocrystalline silicon, polycrystalline silicon. The active may be formed with amorphous silicon then transforming to polycrystalline silicon.FIG. 6bshows a vertical active memory string of bar-sided shapes. The inventive concept of the present disclosure is not limited to the shape of the actives. Thus, the active memory string of tubular type or pillar type can be applied to the memory devices ofFIG. 1andFIG. 4.

A semiconductor device according to a third embodiment of the inventive concept will now be described.FIG. 7is a plan view for explaining a semiconductor device according to a third embodiment of the inventive concept, andFIG. 8Ais a sectional view taken along line of III-III′FIG. 7.

Referring toFIGS. 7 and 8A, a substrate301is provided. The substrate301may be a semiconductor-based substrate. The substrate301may include a well. The well may include a first conductive type dopant. A common source region302may be disposed in the substrate301. The common source region302may be disposed in a plate form within a cell region of the substrate301. The common source region302may include a high concentration of dopant. The dopant included in the common source region302may have a second conductive type, which is different from the conductive type of the dopant included in the well. For example, in the case where the well includes a p-type dopant, the common source region302may include a high concentration of n-type dopant.

The substrate301may include a concave portion A. The concave portion A may include a bottom surface303, and a first sidewall306. The substrate301may include a convex portion B extended from the first sidewall306. A top surface of the convex portion B may be in parallel with the bottom surface of the concave portion A. The concave portion A and the convex portion B may be formed by etching a portion of a semiconductor substrate corresponding to the concave portion A and leaving a portion of the semiconductor substrate corresponding to the convex portion B. In this case, the substrate301may be one body substrate.

The substrate301may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. The cell region α may include the concave portion A and the convex portion B. In the peripheral circuit region β, a peripheral circuit may be disposed. The peripheral circuit region β may include the convex portion B.

The cell region α of the substrate301will now be described.

Conductive patterns GSL, WL1-WL4, SSL spaced apart from one another may be disposed on the concave portion A of the substrate301. The conductive patterns GSL, WL1-WL4, SSL may include a ground select line GSL, word lines WL1-WL4, and a string select line SSL, which are sequentially stacked on the concave portion A of the substrate301. The conductive patterns GSL, WL1-WL4, SSL may be spaced apart from one another with inter-gate insulating layers311-315in-between. For example, the ground select line GSL, the first inter-gate insulating layer311, the first word line WL1, the second inter-gate insulating layer312, the second word line WL2, the third inter-gate insulating layer313, the third word line WL3, the fourth inter-gate insulating layer314, the fourth word line WL4, the fifth inter-gate insulating layer315and the string select line SSL may be sequentially stacked.

A ground select insulating layer310may be disposed between the bottom surface303of the concave portion A of the substrate301, the first sidewall306, and the ground select line GSL. A string select insulating layer316may be disposed on the string select line SSL. The insulating layers310-315may include bottom portions above the bottom surface303of the concave portion A, and sidewall portions extended over the first sidewall306from the bottom portions thereof.

The conductive patterns GSL, WL1-WL4, SSL may include bottom portions BP disposed above the bottom surface303of the concave portion A. Lengths of the bottom portions BP may be shortened as it goes far from the concave portion A of the substrate301. The bottom portions BP may be in parallel with the bottom surface303. The bottom portions BP may be in parallel with the top surface of the convex portion B.

The conductive patterns GSL, WL1-WL4, SSL may include contact inclining portions CT extended over the first sidewall306from one ends of the bottom portions BP. An extended line of the contact inclining portion CT may cross the bottom surface303. For example, the extended line may cross the bottom surface at a right angle. A length of the contact inclining portion CT may be decreased as it goes far from the concave portion A. A top surface of the contact inclining portion CT may be coplanar with the top surface of the convex portion B. An angle between the contact inclining portion CT and the bottom portion BP may be 90°.

Conductive plugs may be disposed on the contact inclining portions CT of the word lines WL1-WL4, respectively. The conductive plugs may be word line contact plugs CP. The word lines WL1-WL4may be electrically connected with the word line contact plugs CP, respectively. The word line contact plugs may penetrate a first interlayer insulating layer360. First conductive lines ML1may be disposed on the word line contact plugs CP and the first interlayer insulating layer360. The first conductive line ML1may extend in a first direction. The first direction may be the III-III′ direction. The word line contact plugs CP may be electrically connected with the first conductive lines ML1. The first conductive lines ML1may extend in a first direction. The first conductive lines ML1may be electrically connected with the word lines WL1-WL4through the word line contact plugs CP. Unlike this, the first conductive lines ML1may be directly connected with the word lines WL1-WL4. A second interlayer insulating layer370covering the first conductive lines ML1may be disposed. The first and second interlayer insulating layers360and370may include the same material.

A conductive plug may be disposed on the contact inclining portion CT of the ground select line GSL. The conductive plug may be a ground select contact plug GCP. The ground select line GSL may be electrically connected with the ground select contact plug GCP. A second conductive line ML2may be disposed on the ground select contact plug GCP and the first interlayer insulating layer360. The ground select contact plug GCP may be electrically connected with the second conductive line ML2. The second conductive line ML2may extend in a first direction. The second conductive line ML2may be electrically connected with the ground select line GSL through the ground select contact plug GCP. Unlike this, the second conductive line ML2may be directly connected with the ground select line GSL. The second interlayer insulating layer370may cover the second conductive line ML2.

A conductive plug may be disposed on the contact inclining portion CT of the string select line SSL. The conductive plug may be a string select contact plug SCP. The string select line SSL may be electrically connected with the string select contact plug SCP. The string select contact plug SCP may penetrate the first interlayer insulating layer360and the second interlayer insulating layer370. A third conductive line ML3may be disposed on the string select contact plug SCP and the second interlayer insulating layer370. The string select contact plug SCP may be electrically connected with the third conductive line ML3. The third conductive line ML3may extend in the first direction.

An active memory string structure extending upward from the bottom surface303of the concave portion A may be disposed. The active memory string structure may extend perpendicular to the substrate301. The active memory string structure may penetrate the conductive patterns GSL, WL1-WL4, SSL so that one end of the active memory string structure may be electrically connected with the common source region302. A drain region D may be disposed at the other end of the active memory string. The drain region D may be a region doped with a high concentration of dopant. The active memory string structure may include a single crystalline semiconductor.

A bit line contact plug BLCP may be disposed on the drain region D of the active memory string structure. The bit line contact plug BLCP may be electrically connected with the drain region D and penetrate the first interlayer insulating layer360. A bit line BL may be disposed on the bit line contact plug BLCP. The bit line BL may be connected with the drain region D of the active memory string structure through the bit line contact plug BLCP. Unlike this, the bit line BL may be directly connected with the drain region D. The bit line BL may extend in the second direction crossing the first direction. The bit line BL may cross the third conductive line ML3.

An information storage layer332may be disposed between the sidewall of the active memory string structure and the conductive patterns GSL, WL1-WL4, SSL. The information storage layer332may be provided in a cylindrical type penetrating the conductive patterns GSL, WL1-WL4, SSL. The information storage layer332may be provided to surround the active memory string structure. The information storage layer332may be disposed between the sidewall of the active memory string structure and the conductive patterns GSL, WL1-WL4, SSL and the insulating layers310-316.

The information storage layer332according to the third embodiment of the inventive concept may be the information storage layer described with reference toFIG. 3.

The peripheral circuit region β of the substrate301will now be described.

A peripheral circuit may be disposed on a top surface of the convex portion B of the peripheral circuit region β. A gate insulating layer354may be disposed on the top surface of the convex portion B. The gate insulating layer354may include a silicon oxide layer. The gate insulating layer354may include a portion formed by thermally oxidizing the top surface of the convex portion B. A gate electrode356may be disposed on the gate insulating layer354. The gate electrode356may include one selected from the group consisting of doped polysilicon, metal and metal silicide. A spacer358may be disposed on both sidewalls of the gate electrode356. Source and drain regions353may be disposed in the convex portion B at both sides of the gate electrode356. The source and drain regions353may be regions doped with a high concentration of dopant. A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer360may be disposed on the gate electrode356and the source and drain regions353. A fourth conductive line ML4may be disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer370may be disposed on the fourth conductive line ML4.

A modified example of the third embodiment of the inventive concept will now be described.FIG. 8Bis a sectional view taken along line III-III′ ofFIG. 7, for explaining a modified example of the third embodiment of the inventive concept.

Referring toFIGS. 7 and 8B, a substrate300is provided. A common source region302may be disposed in the substrate300. The substrate300may include a concave portion A. The concave portion A may include a bottom surface303, and a first sidewall306. The substrate300may include a convex portion B extending from the first sidewall306. A top surface of the convex portion B may be in parallel with the bottom surface303of the concave portion A. The convex portion B may be defined by an insulating layer304on the substrate300.

The substrate300may include a cell region cc and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. In the peripheral circuit region β, a peripheral circuit may be disposed.

The cell region α of the substrate300will now be described.

In the cell region α of the substrate300, the memory cell described with reference toFIG. 8Amay be disposed.

The peripheral circuit region β of the substrate300will now be described.

A peripheral circuit may be disposed on a top surface of the convex portion B of the peripheral circuit region β. A semiconductor layer352may be disposed on a top surface of the insulating layer304. The semiconductor layer352may include semiconductor materials including polysilicon, crystalline silicon and single crystalline silicon. A gate insulating layer354may be disposed on the semiconductor layer352. The gate insulating layer354may include a silicon oxide layer. The gate insulating layer354may include a portion formed by thermally oxidizing the semiconductor layer352. A gate electrode356may be disposed on the gate insulating layer354. The gate electrode356may include one selected from the group consisting of doped polysilicon, metal and metal silicide. A spacer358may be disposed on both sidewalls of the gate electrode356. Source and drain regions353may be disposed in the semiconductor layer352at both sides of the gate electrode356. The source and drain regions353may be regions doped with a high concentration of dopant.

A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer360may be disposed on the gate electrode356and the source and drain regions353. A fourth conductive line ML4may be disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer370may be disposed on the fourth conductive line ML4.

A semiconductor device according to another modified example of the third embodiment of the inventive concept will now be described.FIG. 8Cis a sectional view taken along line III-III′ ofFIG. 7, for showing another modified example of the third embodiment of the inventive concept.

Referring toFIGS. 7 and 8C, a substrate301is provided. A common source region302may be disposed in the substrate301. The substrate301may include a concave portion A. The concave portion A may include a bottom surface303, and a first sidewall306. The first sidewall306may be inclined to the bottom surface303of the concave portion A. For example, the first sidewall306may have an angle, which is 50 to 90 degrees with respect to the bottom surface303. The substrate301may include a convex portion B extending from the first sidewall306. A top surface of the convex portion B may be in parallel with the bottom surface303of the concave portion A. The concave portion A and the convex portion B of the substrate301may be defined through an etching process. Alternatively, as described with reference toFIG. 8B, the convex portion B may be defined by the insulating layer304on the substrate300.

The substrate301may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. In the peripheral circuit region β, a peripheral circuit may be disposed.

The cell region α of the substrate301will now be described.

In the concave portion A of the cell region α, the memory cell described with reference toFIG. 8Amay be disposed. A contact inclining portions CT of the conductive patterns GSL, WL1-WL4, SSL may have an inclined slope with respect to the bottom surface303. An angle between the contact inclining portions CT of the conductive patterns GSL, WL1-WL4, SSL and the bottom surface303may be equal to the angle between the first sidewall306and the bottom surface303.

The peripheral circuit region β of the substrate301will now be described.

In the peripheral circuit region β of the substrate301, the peripheral circuit described with reference toFIG. 8Amay be disposed. Alternatively, as aforementioned, in the case where the substrate is the substrate described with reference toFIG. 8B, a semiconductor layer352may be added.

A semiconductor device according to a fourth embodiment of the inventive concept will now be described.FIG. 9is a plan view for explaining a semiconductor device according to a fourth embodiment of the inventive concept, andFIG. 10Ais a sectional view taken along line IV-IV′ ofFIG. 9.

Referring toFIGS. 9 and 10A, a substrate401is provided. The substrate401may be a semiconductor-based substrate. The substrate401may include a well. The well may include a first conductive type dopant. A common source region402may be disposed in the substrate401. The common source region402may be disposed in a plate form within a cell region of the substrate401. The common source region402may include a high concentration of dopant. The dopant included in the common source region402may have a second conductive type, which is different from the conductive type of the dopant included in the well. For example, in the case where the well includes a p-type dopant, the common source region402may include a high concentration of n-type dopant.

The substrate401may include a concave portion A. The concave portion A may include a bottom surface403, and a first sidewall406. The substrate401may include a convex portion B extended from the first sidewall406. A top surface of the convex portion B may be in parallel with the bottom surface of the concave portion A. The concave portion A and the convex portion B may be formed by etching a portion of a semiconductor substrate corresponding to the concave portion A and leaving a portion of the semiconductor substrate corresponding to the convex portion B. In this case, the substrate401may be one body substrate.

The substrate401may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. The cell region α may include the concave portion A and the convex portion B. In the peripheral circuit region β, a peripheral circuit may be disposed. The peripheral circuit region β may include the convex portion B.

The cell region α of the substrate401will now be described.

Conductive patterns GSL, WL1-WL4, SSL spaced apart from one another may be disposed on the concave portion A of the cell region α of the substrate401. The conductive patterns GSL, WL1-WL4, SSL may include a ground select line GSL, word lines WL1-WL4, and a string select line SSL, which are sequentially stacked on the concave portion A of the substrate401. The conductive patterns GSL, WL1-WL4, SSL may be spaced apart from one another with inter-gate insulating layers410-414in-between. For example, the ground select line GSL, the first inter-gate insulating layer410, the first word line WL1, the second inter-gate insulating layer411, the second word line WL2, the third inter-gate insulating layer412, the third word line WL3, the fourth inter-gate insulating layer413, the fourth word line WL4, the fifth inter-gate insulating layer414and the string select line SSL may be sequentially stacked.

A string select insulating layer415may be disposed on the string select line SSL. The insulating layers410-414may include bottom portions above the bottom surface403of the concave portion A, and sidewall portions extended over the first sidewall406from the bottom portions thereof. The conductive patterns GSL, WL1-WL4, SSL may have a line form extending in a first direction. The first direction may be a direction of line IV-IV′.

The conductive patterns GSL, WL1-WL4, SSL may include bottom portions BP disposed above the bottom surface403of the concave portion A. Lengths of the bottom portions BP may be shortened as it goes far from the concave portion A of the substrate401. The bottom portions BP may be in parallel with the bottom surface403. The bottom portions BP may be in parallel with the top surface of the convex portion B.

The conductive patterns GSL, WL1-WL4, SSL may include contact inclining portions CT extended over the first sidewall406from one ends of the bottom portions BP. An extended line of the contact inclining portion CT may cross the bottom surface403. For example, the extended line may cross the bottom surface at a right angle. A length of the contact inclining portion CT may be decreased as it goes far from the concave portion A. A top surface of the contact inclining portion CT may be coplanar with the top surface of the convex portion B. An angle between the contact inclining portion CT and the bottom portion BP may be 90°.

Conductive plugs may be disposed on the contact inclining portions CT of the word lines WL1-WL4, respectively. The conductive plugs may be word line contact plugs CP. The word lines WL1-WL4may be electrically connected with the word line contact plugs CP, respectively. The word line contact plugs CP may penetrate a first interlayer insulating layer480. First conductive lines ML1may be disposed on the word line contact plugs CP and the first interlayer insulating layer480. The word line contact plugs CP may be electrically connected with the first conductive lines ML1. The first conductive lines ML1may extend in a second direction crossing the first direction. The first conductive lines ML1may be electrically connected with the word lines WL1-WL4through the word line contact plugs CP. Unlike this, the first conductive lines ML1may be directly connected with the word lines WL1-WL4. A second interlayer insulating layer490covering the first conductive lines ML1may be disposed. The first and second interlayer insulating layers480and490may include the same material.

A conductive plug may be disposed on the contact inclining portion CT of the ground select line GSL. The conductive plug may be a ground select contact plug GCP. The ground select line GSL may be electrically connected with the ground select contact plug GCP. The ground select contact plug GCP may penetrate the first interlayer insulating layer480. A second conductive line ML2may be disposed on the ground select contact plug GCP and the first interlayer insulating layer480. The ground select contact plug GCP may be electrically connected with the second conductive line ML2. The second conductive line ML2may extend in the second direction. The second conductive line ML2may be electrically connected with the ground select line GSL through the ground select contact plug GCP. Unlike this, the second conductive line ML2may be directly connected with the ground select line GSL. The second interlayer insulating layer490may cover the second conductive line ML2.

A conductive plug may be disposed on the contact inclining portion CT of the string select line SSL. The conductive plug may be a string select contact plug SCP. The string select line SSL may be electrically connected with the string select contact plug SCP. The string select contact plug SCP may penetrate the first interlayer insulating layer480and the second interlayer insulating layer490. A third conductive line ML3may be disposed on the string select contact plug SCP and the second interlayer insulating layer490. The string select contact plug SCP may be electrically connected with the third conductive line ML3. The third conductive line ML3may extend in the first direction.

An active memory string structure extending upward from the bottom surface403of the concave portion A of the substrate401may be disposed. The active memory string structure may extend perpendicular to the substrate401. The active memory string structure may penetrate the conductive patterns GSL, WL1-WL4, SSL. Unlike this, as described with reference toFIG. 6B, the active memory string structure may face the sidewalls of the conductive patterns GSL, WL1-WL4, SSL. One end of the active memory string structure may be electrically connected with the common source region402. A drain region423may be disposed at the other end of the active memory string. The drain region423may be a region doped with a high concentration of dopant. The active memory string structure may include a single crystalline semiconductor.

A bit line contact plug BLCP may be disposed on the drain region423of the active memory string structure. The bit line contact plug BLCP may be electrically connected with the drain region D and penetrate the first interlayer insulating layer480. A bit line BL may be disposed on the bit line contact plug BLCP. The bit line BL may be connected with the drain region423of the active memory string structure through the bit line contact plug BLCP. Unlike this, the bit line BL may be directly connected with the drain region423. The bit line BL may extend in the second direction. The bit line BL may cross the string select line SSL.

An information storage layer440may be disposed between the sidewall of the active memory string structure and the conductive patterns GSL, WL1-WL4, SSL. The information storage layer440may be disposed between the conductive patterns GSL, WL1-WL4, SSL and the insulating layers410-415.

The peripheral circuit region β of the substrate401will now be described.

A peripheral circuit may be disposed on a top surface of the convex portion B of the peripheral circuit region β. A gate insulating layer474may be disposed on the top surface of the convex portion B. The gate insulating layer474may include a silicon oxide layer. The gate insulating layer474may include a portion formed by thermally oxidizing the substrate401. A gate electrode476may be disposed on the gate insulating layer474. The gate electrode476may include one selected from the group consisting of doped polysilicon, metal and metal silicide. A gate spacer478may be disposed on both sidewalls of the gate electrode476. Source and drain regions473may be disposed in the convex portion B at both sides of the gate electrode476. The source and drain regions473may be regions doped with a high concentration of dopant. A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer480may be disposed on the gate electrode476and the source and drain regions473. A fourth conductive line ML4may be disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer490may be disposed on the fourth conductive line ML4.

A modified example of the fourth embodiment of the inventive concept will now be described.FIG. 10Bis a sectional view taken along line IV-IV′ ofFIG. 9, for explaining a modified example of the fourth embodiment of the inventive concept.

Referring toFIGS. 9 and 10B, a substrate400is provided. A common source region402may be disposed in the substrate400. The substrate400may include a concave portion A. The concave portion A may include a bottom surface403, and a first sidewall406. The substrate400may include a convex portion B extending from the first sidewall406. A top surface of the convex portion B may be in parallel with the bottom surface403of the concave portion A. The convex portion B may be defined by an insulating layer404on the substrate400.

The substrate400may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. In the peripheral circuit region β, a peripheral circuit may be disposed.

The cell region α of the substrate400will now be described.

In the concave portion A of the cell region α, the memory cell described with reference toFIG. 10Amay be disposed.

The peripheral circuit region β of the substrate400will now be described.

A peripheral circuit may be disposed on a top surface of the convex portion B of the peripheral circuit region β. A semiconductor layer472may be disposed on a top surface of the insulating layer404. The semiconductor layer472may include semiconductor materials including polysilicon, crystalline silicon and single crystalline silicon. A gate insulating layer474may be disposed on the semiconductor layer472. The gate insulating layer474may include a silicon oxide layer. The gate insulating layer474may include a portion formed by thermally oxidizing the semiconductor layer472. A gate electrode476may be disposed on the gate insulating layer474. The gate electrode476may include at least one selected from the group consisting of doped polysilicon, metal and metal silicide. A spacer478may be disposed on both sidewalls of the gate electrode476. Source and drain regions473may be disposed in the semiconductor layer472at both sides of the gate electrode476. The source and drain regions473may be regions doped with a high concentration of dopant.

A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer480may be disposed on the gate electrode476and the source and drain regions473. A fourth conductive line ML4may be disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer490may be disposed on the fourth conductive line ML4.

A semiconductor device according to another modified example of the fourth embodiment of the inventive concept will now be described.FIG. 10Cis a sectional view taken along line IV-IV′ ofFIG. 9, for showing another modified example of the fourth embodiment of the inventive concept.

Referring toFIGS. 9 and 10C, a substrate401is provided. A common source region402may be disposed in the substrate401. The substrate401may include a concave portion A. The concave portion A may include a bottom surface403, and a first sidewall406. The first sidewall406may be inclined to the bottom surface403of the concave portion A. For example, the first sidewall406may have an angle, which is 50 to 90 degrees with respect to the bottom surface403. The substrate401may include a convex portion B extending from the first sidewall406. A top surface of the convex portion B may be in parallel with the bottom surface403of the concave portion A. The concave portion A and the convex portion B of the substrate401may be defined through an etching process. Alternatively, as described with reference toFIG. 10B, the convex portion B may be defined by the insulating layer404on the substrate400.

The substrate401may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. The peripheral circuit region β may include a peripheral circuit.

The cell region α of the substrate401will now be described.

In the concave portion A of the cell region α, the memory cell described with reference toFIG. 10Amay be disposed. A contact inclining portions CT of the conductive patterns GSL, WL1-WL4, SSL may have an inclined slope with respect to the bottom surface403. An angle between the contact inclining portions CT of the conductive patterns GSL, WL1-WL4, SSL and the bottom surface403may be equal to the angle between the first sidewall406and the bottom surface403.

The peripheral circuit region β of the substrate401will now be described.

In the peripheral circuit region β of the substrate401, the peripheral circuit described with reference toFIG. 10Amay be disposed. Alternatively, as aforementioned, in the case where the substrate is the substrate described with reference toFIG. 10B, a semiconductor layer472may be added.

A semiconductor device according to a fifth embodiment of the inventive concept will now be described.FIG. 11AthroughFIG. 11Bis a plan view for explaining a semiconductor device according to a fifth embodiment of the inventive concept, andFIG. 12Ais a sectional view taken along line V-V′ ofFIG. 11AthroughFIG. 11B.

Referring toFIGS. 11A through 11Band12A, a substrate501is provided. The substrate501may be a semiconductor-based substrate. The substrate501may include a well. The well may include a first conductive type dopant. A common source region502may be disposed in the substrate501. The common source region502may be disposed in a plate form within a cell region of the substrate501. The common source region502may include a high concentration of dopant. The dopant included in the common source region502may have a second conductive type, which is different from the conductive type of the dopant included in the well. For example, in the case where the well includes a p-type dopant, the common source region502may include a high concentration of n-type dopant.

The substrate501may include a concave portion A. The concave portion A may include a bottom surface503, and first and second sidewalls505and506facing each other. The substrate501may include a convex portion B extended from the first and second sidewalls505and506. A top surface of the convex portion B may be in parallel with the bottom surface of the concave portion A. The concave portion A and the convex portion B may be formed by etching a portion of a semiconductor substrate corresponding to the concave portion A and leaving a portion of the semiconductor substrate corresponding to the convex portion B. In this case, the substrate501may be one body substrate.

The substrate501may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. The cell region α may include the concave portion A and the convex portion B. In the peripheral circuit region β, a peripheral circuit may be disposed. The peripheral circuit region β may include the convex portion B.

The cell region α of the substrate501will now be described.

The cell region α may include a first contact region CR1adjacent to the first sidewall505of the concave portion A, and a second contact region CR2adjacent to the second sidewall506. A cell array region CAR may be disposed between the first contact region CR1and the second contact region CR2. That is, the first contact region CR1and the second contact region CR2may be spaced apart from each other with the cell array region CAR in-between.

Conductive patterns GSL, WL1-WL4, SSL spaced apart from one another may be disposed on the substrate501. The conductive patterns GSL, WL1-WL4, SSL may include a ground select line GSL, word lines WL1-WL4, and a string select line SSL, which are sequentially stacked on the concave portion A of the substrate501. The conductive patterns GSL, WL1-WL4, SSL may be spaced apart from one another with inter-gate insulating layers511-515in-between. For example, the ground select line GSL, the first inter-gate insulating layer511, the first word line WL1, the second inter-gate insulating layer512, the second word line WL2, the third inter-gate insulating layer513, the third word line WL3, the fourth inter-gate insulating layer514, the fourth word line WL4, the fifth inter-gate insulating layer515and the string select line SSL may be sequentially stacked. The insulating layers511-515may include bottom portions above the bottom surface503of the concave portion A of the substrate501, and sidewall portions extended over the first sidewall505and the second sidewall506from the bottom portions thereof.

A ground select insulating layer510may be disposed between the bottom surface503of the concave portion A of the substrate501, the first and second sidewalls505,506, and the ground select line GSL. A string select insulating layer516may be disposed on the string select line SSL. The word lines WL1-WL4may have a plate form parallel to the concave portion A.

The conductive patterns GSL, WL1-WL4, SSL may include bottom portions BP disposed above the bottom surface503of the concave portion A. Lengths of the bottom portions BP may be shortened as it goes far from the concave portion A of the substrate501. The bottom portions BP may be in parallel with the bottom surface503. The bottom portions BP may be in parallel with the top surface of the convex portion B.

The conductive patterns GSL, WL1-WL4, SSL may include contact inclining portions CT extended over one of the first sidewall505and the second sidewall506from one ends of the bottom portions BP. A contact region where the contact inclining portion of any one of the conductive patterns is disposed may be different from a contact region where the contact inclining portion of another conductive pattern adjacent to the any one of the conductive patterns. For example, in the case where the contact inclining portion CT of the ground select line GSL is disposed in the first contact region CR1, the contact inclining portion CT of the first word line WL1adjacent to the ground select line GSL may be disposed in the second contact region CR2. An extended line of the contact inclining portion CT may cross the bottom surface503. The extended line may cross the bottom surface503at a right angle. A length of the contact inclining portion CT may be decreased as it goes far from the concave portion A. A top surface of the contact inclining portion CT may be coplanar with the top surface of the convex portion B. An angle between the contact inclining portion CT and the bottom portion BP may be 90°.

The conductive patterns GSL, WL1-WL4, SSL may include dummy inclining portions DCT extended over the other one of the first sidewall505and the second sidewall506from the other ends of the bottom portions BP above the bottom surface503. A contact region where the dummy inclining portion of any one of the conductive patterns GSL, WL1-WL4, SSL is disposed may be different from a contact region where the dummy inclining portion of another conductive pattern adjacent to the any one of the conductive patterns. For example, in the case where the dummy inclining portion DCT of the string select line SSL is disposed in the first contact region CR1, the dummy inclining portion DCT of the fourth word line WL4adjacent to the string select line SSL may be disposed in the second contact region CR2. Each of the conductive patterns GSL, WL1-WL4, SSL may include one contact inclining portion CT and one dummy inclining portion DCT. In one of the conductive patterns GSL, WL1-WL4, SSL, a length of the dummy inclining portion DCT may be shorter than that of the contact inclining portion CT. The contact inclining portion CT may be disposed between the dummy inclining portions DCT adjacent to each other. The contact inclining portions CT adjacent to one of the dummy inclining portions DCT may be spaced apart from each other by the sidewalls of the insulating layers interposed therebetween.

A dummy insulating layer pattern524may be disposed on the dummy inclining portion DCT. A top surface of the dummy insulating layer pattern524may be coplanar with the top surface of the convex portion B. The top surface of the dummy insulating layer pattern524may be coplanar with a top surface of the string select insulating layer516. Sidewalls of the dummy insulating layer pattern524may be coplanar with sidewalls of the dummy inclining portion DCT. The dummy insulating layer pattern524may include the same material as the insulating layers510-516.

Conductive plugs may be disposed on the contact inclining portions CT of the word lines WL1-WL4, respectively. The conductive plugs may be word line contact plugs CP. The word lines WL1-WL4may be electrically connected with the word line contact plugs CP, respectively. Widths of the word line contact plugs CP may be wider than those of the top surfaces of the contact inclining portions CT of the word lines WL1-WL4. The widths of the word line contact plugs CP may be wider than widths between the dummy inclining portions DCT adjacent to the contact inclining portions of the word lines WL1-WL4. The word line contact plugs may penetrate a first interlayer insulating layer560. First conductive lines ML1may be disposed on the word line contact plugs CP and the first interlayer insulating layer560. The word line contact plugs CP may be electrically connected with the first conductive lines ML1. Some of the first conductive lines ML1may extend in a first direction. Another some of the first conductive lines ML1may extend in a second direction opposite to the first direction. For example, the first conductive lines ML1connected with the word lines WL2, WL4positioned at odd-numbered layers of the conductive patterns above the substrate101may extend in the first direction, and the first conductive lines ML1connected with the word lines WL1, WL3positioned at even-numbered layers of the conductive patterns above the substrate101may extend in the second direction. The first direction may be a direction of line V′-V. The first conductive lines ML1may be electrically connected with the word lines WL1-WL4through the word line contact plugs CP. Unlike this, the first conductive lines ML1may be directly connected with the word lines WL1-WL4. A second interlayer insulating layer570covering the first conductive lines ML1may be disposed. The first and second interlayer insulating layers560and570may include the same material.

The first conductive lines ML1may extend in a second direction crossing the first direction. The first conductive lines ML1may be electrically connected with the word lines WL1-WL4through the word line contact plugs CP. Unlike this, the first conductive lines ML1may be directly connected with the word lines WL1-WL4. A second interlayer insulating layer570covering the first conductive lines ML1may be disposed. The first and second interlayer insulating layers560and570may include the same material.

A conductive plug may be disposed on the contact inclining portion CT of the ground select line GSL. The conductive plug may be a ground select contact plug GCP. The ground select line GSL may be electrically connected with the ground select contact plug GCP. A width of the ground select contact plug GCP may be wider than a width of a top surface of the contact inclining portion CT of the ground select line GSL. The ground select contact plug GCP may penetrate the first interlayer insulating layer560. A second conductive line ML2may be disposed on the ground select contact plug GCP and the first interlayer insulating layer560. The ground select contact plug GCP may be electrically connected with the second conductive line ML2. The second conductive line ML2may extend in the first direction. The second conductive line ML2may be electrically connected with the ground select line GSL through the ground select contact plug GCP. Unlike this, the second conductive line ML2may be directly connected with the ground select line GSL. The second interlayer insulating layer570may cover the second conductive line ML2.

A conductive plug may be disposed on the contact inclining portion CT of the string select line SSL. The conductive plug may be a string select contact plug SCP. The string select line SSL may be electrically connected with the string select contact plug SCP. A width of the string select contact plug SCP may be wider than a width of a top surface of the contact inclining portion CT of the string select line SSL. The string select contact plug SCP may penetrate the first interlayer insulating layer560and the second interlayer insulating layer570. A third conductive line ML3may be disposed on the string select contact plug SCP and the second interlayer insulating layer570. The string select contact plug SCP may be electrically connected with the third conductive line ML3. The third conductive line ML3may extend in the second direction. The second interlayer insulating layer570may cover the third conductive line ML3. Referring to theFIG. 10B, a plurality of the string select line SSL may dispose in the concave portion. And the third conductive lines ML3of the string select lines SSL adjacent to each other may extend different direction.

The conductive lines ML1, ML2, ML3may be extended separated in the first direction and the second direction sides with the cell array region CAR in-between. For example, the conductive lines ML2, ML1connected with the conductive patterns GSL, WL2, WL4of which the contact inclining portions CT are disposed in the first contact region may extend in the first direction, and the conductive lines ML1, ML3connected with the conductive patterns WL1, WL3, SSL of which the contact inclining portions CT are disposed in the second contact region may extend in the second direction.

An active memory string structure extending upward from the bottom surface503of the concave portion A may be disposed. The active memory string structure may extend perpendicular to the substrate501. The active memory string structure may penetrate the conductive patterns GSL, WL1-WL4, SSL so that one end of the active memory string structure may be electrically connected with the common source region502. A drain region D may be disposed at the other end of the active memory string. The drain region D may be a region doped with a high concentration of dopant. The active memory string structure may include a single crystalline semiconductor.

A bit line contact plug BLCP may be disposed on the drain region D of the active memory string structure. The bit line contact plug BLCP may be electrically connected with the drain region D and penetrate the first interlayer insulating layer560. A bit line BL may be disposed on the bit line contact plug BLCP. The bit line BL may be connected with the drain region D of the active memory string structure through the bit line contact plug BLCP. Unlike this, the bit line BL may be directly connected with the drain region D. The bit line BL may extend in the first direction, and a third direction crossing the second direction. The third direction may cross the first and second directions at a right angle. The bit line BL may cross the string select line SSL.

An information storage layer532may be disposed between the sidewall of the active memory string structure and the conductive patterns GSL, WL1-WL4, SSL. The information storage layer532may be provided in a cylindrical type penetrating the conductive patterns GSL, WL1-WL4, SSL. The information storage layer532may be provided to surround the active memory string structure. The information storage layer532may be disposed between the sidewall of the active memory string structure and the conductive patterns GSL, WL1-WL4, SSL and the insulating layers510-516.

The information storage layer532according to the fifth embodiment of the inventive concept may be the information storage layer described with reference toFIG. 3.

The peripheral circuit region β of the substrate501will now be described.

A peripheral circuit may be disposed on a top surface of the convex portion B of the peripheral circuit region β. A gate insulating layer554may be disposed on the top surface of the convex portion B. The gate insulating layer554may include a silicon oxide layer. The gate insulating layer554may include a portion formed by thermally oxidizing the top surface of the convex portion B. A gate electrode556may be disposed on the gate insulating layer554. The gate electrode556may include one selected from the group consisting of doped polysilicon, metal and metal silicide. A spacer558may be disposed on both sidewalls of the gate electrode556. Source and drain regions553may be disposed in the convex portion B at both sides of the gate electrode556. The source and drain regions553may be regions doped with a high concentration of dopant.

A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer560may be disposed on the gate electrode556and the source and drain regions553. A fourth conductive line ML4may be disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer570may be disposed on the fourth conductive line ML4.

A modified example of the fifth embodiment of the inventive concept will now be described.FIG. 12Bis a sectional view taken along line V-V′ ofFIG. 11AthroughFIG. 11B, for explaining a modified example of the fifth embodiment of the inventive concept.

Referring toFIGS. 11A through 11Band12B, a substrate500is provided. A common source region502may be disposed in the substrate500. The substrate500may include a concave portion A. The concave portion A may include a bottom surface503, and first and second sidewalls505and506facing each other. The substrate500may include a convex portion B extending from the first and second sidewalls505and506. A top surface of the convex portion B may be in parallel with the bottom surface503of the concave portion A. The convex portion B may be defined by an insulating layer504disposed on the substrate500.

The substrate500may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. In the peripheral circuit region β, a peripheral circuit may be disposed.

The cell region α of the substrate500will now be described.

The cell region α may include a first contact region CR1adjacent to the first sidewall505of the concave portion A, and a second contact region CR2adjacent to the second sidewall506. The memory cell explained with reference toFIG. 12Amay be disposed in the cell region α of the substrate500.

The peripheral circuit region β of the substrate500will now be described.

A peripheral circuit may be disposed on a top surface of the convex portion B of the peripheral circuit region β. A semiconductor layer552may be disposed on a top surface of the insulating layer504. The semiconductor layer552may be semiconductor materials including polysilicon, crystalline silicon and single crystalline silicon. A gate insulating layer554may be disposed on the semiconductor layer552. The gate insulating layer554may include a silicon oxide layer. The gate insulating layer554may include a portion formed by thermally oxidizing the semiconductor layer552. A gate electrode556may be disposed on the gate insulating layer554. The gate electrode556may include one selected from the group consisting of doped polysilicon, metal and metal silicide. A spacer558may be disposed on both sidewalls of the gate electrode556. Source and drain regions553may be disposed in the semiconductor layer552at both sides of the gate electrode556. The source and drain regions553may be regions doped with a high concentration of dopant.

A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer560may be disposed on the gate electrode556and the source and drain regions553. A fourth conductive line ML4may be disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer570may be disposed on the fourth conductive line ML4.

A semiconductor device according to another modified example of the fifth embodiment of the inventive concept will now be described.FIG. 12Cis a sectional view taken along line V-V′ ofFIG. 11A through 11B, for showing another modified example of the fifth embodiment of the inventive concept.

Referring toFIGS. 11A through 11Band12C, a substrate501is provided. A common source region502may be disposed in the substrate501. The substrate501may include a concave portion A. The concave portion A may include a bottom surface503, and first and second sidewalls505and506facing each other. Any one of the first and second sidewalls505and506may be inclined to the bottom surface503of the concave portion A. For example, the first sidewall505and the second sidewall506may have an angle, which is 50 to 90 degrees with respect to the bottom surface503. A slope of the first sidewall505with respect to the bottom surface503may be equal to that of the second sidewall506with respect to the bottom surface503. Alternatively, the slope of the first sidewall505with respect to the bottom surface503may be different from that of the second sidewall506with respect to the bottom surface503. The substrate501may include a convex portion B extending from the first and second sidewalls505and506. A top surface of the convex portion B may be in parallel with the bottom surface503of the concave portion A. The concave portion A and the convex portion B of the substrate501may be defined through an etching process. Alternatively, as described with reference toFIG. 12B, the convex portion B may be defined by the insulating layer504on the substrate501.

The substrate501may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. The peripheral circuit region β may include a peripheral circuit.

The cell region α of the substrate501will now be described.

The cell region α may include a first contact region CR1adjacent to the first sidewall505of the concave portion A, and a second contact region CR2adjacent to the second sidewall506. The memory cell explained with reference toFIG. 12Amay be disposed in the cell region α of the substrate501. A contact inclining portion CT and a dummy inclining portion DCT of any one of the conductive patterns GSL, WL1-WL4, SSL may have an inclined slope with respect to a bottom portion BP.

An angle between the sidewall adjacent to the contact region where the contact inclining portion CT is disposed, and the bottom surface503may be equal to an angle between the contact inclining portion CT and the bottom portion BP. For example, in the case of the first word line WL1, a slope of the contact inclining portion CT with respect to the bottom portion BP may be equal to a slope of the second sidewall506with respect to the bottom surface503. When the slopes of the first sidewall505and the second sidewall506with respect to the bottom surface503are different from each other, the slope of the contact inclining portion with respect to the bottom portion BP in any one conductive pattern may be different from the slope of the dummy inclining portion DCT with respect to the bottom portion BP.

The peripheral circuit region βof the substrate501will now be described.

In the peripheral circuit region β of the substrate501, the peripheral circuit described with reference toFIG. 12Amay be disposed. Alternatively, as aforementioned, in the case where the substrate is the substrate described with reference toFIG. 12B, a semiconductor layer552may be added.

A method for forming a semiconductor device according to the fifth embodiment will now be described.FIGS. 13A to 13Hare cross-sectional views for explaining a method for forming a semiconductor device according to the fifth embodiment of the inventive concept.

Referring toFIG. 13A, a substrate501is provided. The substrate501may include a concave portion A. The concave portion A may include a bottom surface503, and first and second sidewalls505and506facing each other. The substrate501may include a convex portion B extended from the first and second sidewalls505and506. A top surface of the convex portion B may be in parallel with the bottom surface of the concave portion A. A forming of the concave portion A and the convex portion B of the substrate501may include etching a portion of a substrate corresponding to the concave portion A and leaving a portion of the substrate corresponding to the convex portion B.

The substrate501may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. The cell region α may include the concave portion A and the convex portion B. The peripheral circuit region β may include a peripheral circuit. The peripheral circuit region β may include the convex portion B.

The cell region α may include a first contact region CR1adjacent to the first sidewall505of the concave portion A, and a second contact region CR2adjacent to the second sidewall506. A cell array region CAR may be disposed between the first contact region CR1and the second contact region CR2. That is, the first contact region CR1and the second contact region CR2may be spaced apart from each other with the cell array region CAR in-between.

The substrate501may be a single crystalline semiconductor substrate (e.g., p-type silicon wafer). The substrate501may include a well. The well may be formed by introducing a dopant into the substrate501. The dopant may be introduced by a doping process including an ion implantation or a plasma implantation. A common source region502may be provided in an upper portion of the substrate501. The common source region502may be formed by doping a dopant into the well. The common source region502may include a dopant having a conductive type, which is different from the conductive type of the well. For example, the well may include a p-type dopant and the common source region502may include an n-type dopant.

Referring toFIG. 13B, conductive patterns GSL, WL1-WL4, SSL and insulating layers510-516may be alternatingly formed on the concave portion A of the substrate501. For example, the ground select insulating layer510, the ground select line GSL, the first inter-gate insulating layer511, the first word line WL1, the second inter-gate insulating layer512, the second word line WL2, the third inter-gate insulating layer513, the third word line WL3, the fourth inter-gate insulating layer514, the fourth word line WL4, the fifth inter-gate insulating layer515, the string select line SSL and the string select insulating layer516may be sequentially deposited. The conductive patterns GSL, WL1-WL4, SSL and the insulating layer510-516may be also formed on the top surface of the convex portion B. The conductive patterns GSL, WL1-WL4, SSL may include metal or polycrystalline semiconductor material. The insulating layers510-516may include a silicon oxide layer.

A planarizing process may be performed by using the top surface of the convex portion B as an etch stop layer. The planarizing process may be performed by using any of an etch-back or a chemical mechanical polishing (CMP). By the planarizing process, the conductive patterns GSL, WL1-WL4, SSL and the insulating layers510-516formed on the convex portion B may be removed.

The conductive patterns GSL, WL1-WL4, SSL may include bottom portions BP disposed above the bottom surface503of the concave portion A. The conductive patterns GSL, WL1-WL4, SSL may include contact inclining portions CT extended over one of the first sidewall505and the second sidewall506from one ends of the bottom portions BP. A contact region where the contact inclining portion of any one of the conductive patterns is disposed may be different from a contact region where the contact inclining portion of another conductive pattern adjacent to the any one of the conductive patterns. An exposed top surface of the contact inclining portion CT may be coplanar with the top surface of the convex portion B.

The conductive patterns GSL, WL1-WL4, SSL may include dummy inclining portions DCT extended over the other one of the first sidewall505and the second sidewall506from the other ends of the bottom portions BP above the bottom surface503. A contact region where the dummy inclining portion of any one of the conductive patterns GSL, WL1-WL4, SSL is disposed may be different from a contact region where the dummy inclining portion of another conductive pattern adjacent to the any one of the conductive patterns. Each of the conductive patterns GSL, WL1-WL4, SSL may include one contact inclining portion CT and one dummy inclining portion DCT.

A mask pattern520covering the exposed top surface of the contact inclining portions is covered. The mask pattern520exposes the dummy inclining portions DCT.

The covering of the mask pattern520may include forming a mask layer on the substrate501, and patterning the mask layer. The mask pattern520may include a material having an etch selectivity with respect to the conductive patterns GSL, WL1-WL4, SSL and the insulating layers510-516. For example, the mask pattern520may include a silicon nitride layer or a photoresist pattern.

Referring toFIG. 13C, the dummy inclining portions DCT may be partially etched by using the mask pattern520as an etch mask. As a result, dummy recess portions522may be formed. Lengths of the dummy inclining portions DCT may be shorter than lengths of the contact inclining portions CT. Due to the dummy recess portions522, sidewalls of the insulating layers510-516may be partially exposed. The etching of the dummy inclining portions DCT may be performed by using an etch recipe in which the etch rate of the conductive patterns GSL, WL1-WL4, SSL is higher than that of the mask pattern520and the insulating layers510-516. Thereafter, the mask pattern520may be removed.

The string select line SSL may be patterned in a line form extending in a first direction. The first direction may be a direction of line V-V′.

Referring toFIG. 13D, a dummy insulating layer pattern524filling the dummy recess portions522may be formed. The forming of the dummy insulating layer pattern524may include forming a dummy insulating layer on the substrate, and performing a planarizing process by using the top surface of the convex portion B or a top surface of the string select insulating layer516as an etch stop layer. A top surface of the dummy insulating layer pattern524may be coplanar with the top surface of the convex portion B. The top surface of the dummy insulating layer pattern524may be coplanar with the top surface of the string select insulating layer516. Sidewalls of the dummy insulating layer pattern524may be coplanar with sidewalls of the insulating layers510-516.

Active openings530exposing the common source region502positioned at the bottom surface503of the concave portion may be formed by etching the conductive patterns GSL, WL1-WL4, SSL and the insulating layers510-516. The active memory string openings530may expose sidewalls of the conductive patterns GSL, WL1-WL4, SSL and sidewalls of the insulating layers510-516. The etching of the conductive patterns GSL, WL1-WL4, SSL and the insulating layers510-516may be performed by using an anisotropic etching.

Referring toFIG. 13E, an information storage layer532covering the sidewalls of the conductive patterns GSL, WL1-WL4, SSL and the sidewalls of the insulating layers510-516exposed by the active memory string openings530may be formed. Layers containing the information storage layer532may cover the common source region502exposed by the active memory string openings530. Layers containing the information storage layer532may be formed on the top surface of the convex portion B, the top surface of the string select insulating layer516, the sidewalls of the insulating layers510-516, the top surface of the dummy insulating layer pattern524, and the top surface of the contact inclining portions CT.

Again referring toFIG. 3, a method of forming the information storage layer532will be described. The forming of the information storage layer532may include forming a blocking layer134in the active memory string openings530, forming a charge storage layer135covering the blocking layer134, and forming a tunnel insulating layer136covering the charge storage layer135. The shape of an active may be pillar or tubular wherein the core of the opening is filled with a insulating material.

Again referring toFIG. 13E, a spacer534may be formed in the active memory string openings530. The spacer534may partially cover the information storage layer532formed on sidewalls of the active memory string openings530and the information storage layer532formed on the bottom surface of the active memory string openings530. The forming of the spacer534may include forming a spacer layer on the substrate, and anisotropically etching a bottomed portion. The spacer534may include silicon. The spacer534may include a material having an etch selectivity with respect to the information storage layer532. The anisotropic etching will expose the bottomed portion where the spacer534does not cover. Some portion of layers including information storage layer on the bottomed portion of the opening may remain after etching.

Referring toFIG. 13F, the information storage layer532not exposed by the spacer534may be etched by using the spacer534as an etch mask. During the etching, the surface of the substrate503may be exposed. The information storage layer532formed on the top surface of the convex portion B, the top surface of the string select insulating layer516, the top surfaces of the insulating layers510-515, the top surface of the dummy insulating layer pattern524and the top surfaces of the contact inclining portions CT may be removed. In the case where the spacer534includes polysilicon, the spacer534may be removed or not removed and used as a portion of active region. In the case where the spacer534is an insulator, the spacer534may be removed and semiconductor material for an active region may be formed on the side and bottom of the resultant opening.

Actives filling the active memory string openings530may be formed. The active memory string structure may include, but is not limited to, a single crystalline semiconductor. In the case where the active memory string structure includes a single crystalline semiconductor, the active memory string structure may be formed by an epitaxial growth which uses the substrate501as a seed layer. Alternatively, the active memory string structure may be formed by forming a polycrystalline or amorphous semiconductor layer filling the active memory string openings530and then performing a phase transition of the formed polycrystalline or amorphous semiconductor layer through a heat or laser treatment. In the case where the spacer534is not removed, the active memory string structure may include the same material as the spacer534. The active memory string structure may be formed in a form filling the active memory string opening530, or in a hollow cylindrical form.

A drain region D may be formed at an upper portion of the active memory string structure. The drain region D may be formed by doping the upper portion of the active memory string structure. The drain region D may be a region where dopants having a conductive type different from that of the well are included at a high concentration. For example, the drain region D may include a high concentration of n-type dopant. The drain region may be of pad shape of tubular shape.

Referring toFIG. 13G, a gate insulating layer554may be formed on the top surface of the convex portion B. The forming of the gate insulating layer554may include thermally oxidizing the semiconductor layer552. In the case where the gate insulating layer554is formed by a thermal oxidation, an oxide layer may be formed on the top surface of the contact inclining portion CT. Therefore, prior to forming of the gate insulating layer554, a mask layer covering the concave portion A and exposing the convex portion B may be additively formed. The mask layer may be an insulating layer.

The gate insulating layer554may include a silicon oxide layer. A gate electrode556may be formed on the gate insulating layer554. Source and drain regions553may be formed in the semiconductor layer552at both sides of the gate electrode556. The source and drain regions553may be formed by implanting an impurity into the semiconductor layer552.

Referring toFIG. 13H, a gate spacer558may be formed on both sidewalls of the gate electrode556. A first interlayer insulating layer560may be formed on the substrate501. The first interlayer insulating layer560may cover a peripheral circuit on the convex portion B. The first interlayer insulating layer560may include a silicon oxide layer.

A contact opening562, a bit line opening564and a peripheral circuit opening566respectively exposing the contact inclining portions CT of the conductive patterns GSL, WL1-WL4, the drain region D of the active and a top surface of the gate electrode556of the peripheral circuit may be formed by etching the first interlayer insulating layer560. At this time, an opening exposing the source and drain regions553of the peripheral circuit region β may be also formed. The etching of the first interlayer insulating layer560may be performed by using an anisotropic etching.

As aforementioned, in the case where the gate insulating layer554is formed by a thermal oxidation process and thus an oxide layer is formed on the top surfaces of the contact inclining portions CT of the conductive patterns GSL, WL1-WL4, SSL of the cell region α, the mask layer may be etched to expose the contact inclining portions CT while the first interlayer insulating layer560is etched. Unlike this, in the case where the gate insulating layer554is formed by a thermal oxidation process but an oxide layer is formed on the top surfaces of the contact inclining portions CT of the conductive patterns GSL, WL1-WL4, SSL because a mask layer is not formed on the top surfaces of the contact inclining portions CT of the conductive patterns GSL, WL1-WL4, SSL, the oxide layer may be etched while the first interlayer insulating layer560is etched.

Again referring toFIG. 12A, contact plugs GCP, CP, bit line contact plugs BLCP and a peripheral circuit contact plug PCP respectively filling the contact opening562, the bit line opening564and the peripheral circuit opening566may be formed.

The ground select contact plug GCP may be electrically connected with the contact inclining portion CT of the ground select line GSL. The word line contact plugs CP may be electrically connected with the word lines WL1-WL4. Each of the contact plugs GCP, CP may include a material having conductivity higher than the conductive patterns GSL, WL1-WL4. The peripheral circuit contact plug PCP may be electrically connected with the gate electrode556. The peripheral circuit contact plug PCP may include a material having conductivity higher than the gate electrode556. For example, the contact plugs GCP, CP, the bit line contact plug BLCP and the peripheral circuit contact plug PCP may include tungsten.

A second conductive line ML2may be formed on the ground select contact plug GCP. A first conductive line ML1may be formed on the word line contact plug CP. A bit line BL may be formed on the bit line contact plug BLCP. A fourth conductive line ML4may be formed on the peripheral circuit contact plug PCP. The forming of the second conductive line ML2, the first conductive line ML1, the bit line BL and the fourth conductive line ML4may include forming a conductive layer on the first interlayer insulating layer560and patterning the conductive layer.

A second interlayer insulating layer570covering the second conductive line ML2, the first conductive line ML1and the fourth conductive line ML4may be formed. The second interlayer insulating layer570may include the same material as the first interlayer insulating layer560. A string select contact plug SCP penetrating the second interlayer insulating layer570and the first interlayer insulating layer580and filling an opening exposing the contact inclining portion of the string select line SSL may be formed. The string select contact plug SCP may include a material having conductivity higher than the string select line SSL. A third conductive line ML3may be formed on the string select contact plug SCP. The forming of the third conductive line ML3may include forming a conductive layer on the second interlayer insulating layer570and patterning the conductive layer. By doing so, the semiconductor device described with reference toFIG. 12Amay be provided.

A method for forming a semiconductor device according to the modified example of the fifth embodiment of the inventive concept, described with reference toFIG. 12Bwill now be described.

Referring toFIG. 12B, in the method of forming a semiconductor device described with reference toFIGS. 13A to 13H, andFIG. 12A, the concave portion A and the convex portion B may be defined by forming an insulating layer504on the substrate500, etching a portion of the insulating layer504corresponding to the concave portion A and leaving a portion of the insulating layer504corresponding to the convex portion B.

A semiconductor layer552may be formed on the convex portion B of the peripheral circuit region β. The forming of the semiconductor layer552may include bonding the semiconductor layer552on the top surface of the convex portion B or growing the semiconductor layer552. The semiconductor layer552may include silicon. A gate insulating layer554may be formed on the semiconductor layer552. Thereafter, a peripheral circuit may be formed by the method of forming the peripheral circuit described with reference toFIGS. 13G to 13H.

A method for forming a semiconductor device according to another modified example of the fifth embodiment of the inventive concept, described with reference toFIG. 12Cwill now be described.

Referring toFIG. 12C, in the method for forming a semiconductor device described with reference toFIGS. 13A to 13HandFIG. 12A, at least one of the first sidewall505and the second sidewall506may be formed inclined with respect to the bottom surface503. In this case, the contact inclining portions CT and the dummy inclining portions DCT may be formed inclined with respect to the bottom surface503and the bottom portions BP. The sidewall portions of the insulating layers510-516may be formed inclined with respect to the bottom surface503.

A semiconductor device according to a sixth embodiment of the inventive concept will now be described.FIG. 14AFIG. 14Bis a plan view for explaining a semiconductor device according to a sixth embodiment of the inventive concept, andFIG. 15Ais a sectional view taken along line VI-VI′ ofFIG. 14.

Referring toFIGS. 14A through 14Band15A, a substrate601is provided. The substrate601may be a semiconductor-based substrate. The substrate601may include a well. The well may include a first conductive type dopant. A common source region602may be disposed in the substrate601. The common source region602may be disposed in a plate form within a cell region of the substrate601. Alternatively, the common source region may be of line type on the substrate. For example, the common source region may be formed by implanting a trench formed for gate replacement process. The common source region602may include a high concentration of dopant. The dopant included in the common source region602may have a second conductive type, which is different from the conductive type of the dopant included in the well. For example, in the case where the well includes a p-type dopant, the common source region602may include a high concentration of n-type dopant.

The substrate601may include a concave portion A. The concave portion A may include a bottom surface603, and first and second sidewalls605and606facing each other. The substrate601may include a convex portion B extended from the first and second sidewalls605and606. A top surface of the convex portion B may be in parallel with the bottom surface of the concave portion A. The concave portion A and the convex portion B may be formed by etching a portion of a semiconductor substrate corresponding to the concave portion A and leaving a portion of the semiconductor substrate corresponding to the convex portion B. In this case, the substrate601may be one body substrate.

The substrate601may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. The cell region α may include the concave portion A and the convex portion B. In the peripheral circuit region β, a peripheral circuit may be disposed.

The cell region α of the substrate601will now be described.

The cell region α may include a first contact region CR1adjacent to the first sidewall605of the concave portion A, and a second contact region CR2adjacent to the second sidewall606. A cell array region CAR may be disposed between the first contact region CR1and the second contact region CR2. That is, the first contact region CR1and the second contact region CR2may be spaced apart from each other with the cell array region CAR in-between.

Conductive patterns GSL, WL1-WL4, SSL spaced apart from one another may be disposed on the substrate601. The conductive patterns GSL, WL1-WL4, SSL may include a ground select line GSL, word lines WL1-WL4, and a string select line SSL, which are sequentially stacked on the concave portion A of the substrate601. The conductive patterns GSL, WL1-WL4, SSL may be spaced apart from one another with inter-gate insulating layers610-614in-between. For example, the ground select line GSL, the first inter-gate insulating layer610, the first word line WL1, the second inter-gate insulating layer611, the second word line WL2, the third inter-gate insulating layer612, the third word line WL3, the fourth inter-gate insulating layer613, the fourth word line WL4, the fifth inter-gate insulating layer614and the string select line SSL may be sequentially stacked. The insulating layers610-614may include bottom portions above the bottom surface603of the concave portion A of the substrate601, and sidewall portions extended over the first sidewall605and the second sidewall606from the bottom portions thereof. A string select insulating layer615may be disposed on the string select line SSL. The conductive patterns GSL, WL1-WL4, SSL may have a line form extending in a first direction. The first direction may be a direction of line VI-VI′.

The conductive patterns GSL, WL1-WL4, SSL may include bottom portions BP disposed above the bottom surface603of the concave portion A. Lengths of the bottom portions BP may be shortened as it goes far from the concave portion A of the substrate601. The bottom portions BP may be in parallel with the bottom surface603. The bottom portions BP may be in parallel with the top surface of the convex portion B.

The conductive patterns GSL, WL1-WL4, SSL may include contact inclining portions CT extended over any of the first sidewall605and the second sidewall606from one ends of the bottom portions BP. A contact region where the contact inclining portion of any one of the conductive patterns is disposed may be different from a contact region where the contact inclining portion of another conductive pattern adjacent to the any one of the conductive patterns. For example, in the case where the contact inclining portion CT of the ground select line GSL is disposed in the first contact region CR1, the contact inclining portion CT of the first word line WL1adjacent to the ground select line GSL may be disposed in the second contact region CR2.

An extended line of the contact inclining portion CT may cross the bottom surface603. The extended line may cross the bottom surface603at a right angle. A length of the contact inclining portion CT may be decreased as it goes far from the concave portion A. A top surface of the contact inclining portion CT may be coplanar with the top surface of the convex portion B. An angle between the contact inclining portion CT and the bottom portion BP may be 90°.

The conductive patterns GSL, WL1-WL4, SSL may include dummy inclining portions DCT extended over the other one of the first sidewall605and the second sidewall606from the other ends of the bottom portions BP above the bottom surface603. A contact region where the dummy inclining portion of any one of the conductive patterns GSL, WL1-WL4, SSL is disposed may be different from a contact region where the dummy inclining portion of another conductive pattern adjacent to the any one of the conductive patterns. For example, in the case where the dummy inclining portion DCT of the string select line SSL is disposed in the first contact region CR1, the dummy inclining portion DCT of the fourth word line WL4adjacent to the string select line SSL may be disposed in the second contact region CR2.

Each of the conductive patterns GSL, WL1-WL4, SSL may include one contact inclining portion CT and one dummy inclining portion DCT. In one of the conductive patterns GSL, WL1-WL4, SSL, a length of the dummy inclining portion DCT may be shorter than that of the contact inclining portion CT. The contact inclining portion CT may be disposed between the dummy inclining portions DCT adjacent to each other. The contact inclining portions CT adjacent to one of the dummy inclining portions DCT may be spaced apart from each other by the sidewalls of the insulating layers interposed therebetween.

A dummy insulating layer pattern664may be disposed on the dummy inclining portion DCT. A top surface of the dummy insulating layer pattern664may be coplanar with the top surface of the convex portion B. The top surface of the dummy insulating layer pattern664may be coplanar with a top surface of the string select insulating layer615. Sidewalls of the dummy insulating layer pattern664may be coplanar with sidewalls of the dummy inclining portion DCT. The dummy insulating layer pattern664may include the same material as the insulating layers610-615.

Conductive plugs may be disposed on the contact inclining portions CT of the word lines WL1-WL4, respectively. The conductive plugs may be word line contact plugs CP. The word lines WL1-WL4may be electrically connected with the word line contact plugs CP, respectively. Widths of the word line contact plugs CP may be wider than those of the top surfaces of the contact inclining portions CT of the word lines WL1-WL4. The widths of the word line contact plugs CP may be greater than widths between the dummy inclining portions DCT adjacent to the contact inclining portions of the word lines WL1-WL4. The word line contact plugs may penetrate a first interlayer insulating layer680. First conductive lines ML1may be disposed on the word line contact plugs CP and the first interlayer insulating layer680. The word line contact plugs CP may be electrically connected with the first conductive lines ML1. The first conductive lines ML1may extend in a second direction crossing the first direction. The first conductive lines ML1may be electrically connected with the word lines WL1-WL4through the word line contact plugs CP. Unlike this, the first conductive lines ML1may be directly connected with the word lines WL1-WL4. A second interlayer insulating layer690covering the first conductive lines ML1may be disposed. The first and second interlayer insulating layers680and690may include the same material.

A conductive plug may be disposed on the contact inclining portion CT of the ground select line GSL. The conductive plug may be a ground select contact plug GCP. The ground select line GSL may be electrically connected with the ground select contact plug GCP. A width of the ground select contact plug GCP may be wider than a width of a top surface of the contact inclining portion CT of the ground select line GSL. The ground select contact plug GCP may penetrate the first interlayer insulating layer680. A second conductive line ML2may be disposed on the ground select contact plug GCP and the first interlayer insulating layer680. The ground select contact plug GCP may be electrically connected with the second conductive line ML2. The second conductive line ML2may extend in the second direction. The second conductive line ML2may be electrically connected with the ground select line GSL through the ground select contact plug GCP. Unlike this, the second conductive line ML2may be directly connected with the ground select line GSL. The second interlayer insulating layer690may cover the second conductive line ML2.

A conductive plug may be disposed on the contact inclining portion CT of the string select line SSL. The conductive plug may be a string select contact plug SCP. The string select line SSL may be electrically connected with the string select contact plug SCP. A width of the string select contact plug SCP may be wider than a width of a top surface of the contact inclining portion CT of the string select line SSL. The string select contact plug SCP may penetrate the first interlayer insulating layer680and the second interlayer insulating layer690. A third conductive line ML3may be disposed on the string select contact plug SCP and the second interlayer insulating layer690. The string select contact plug SCP may be electrically connected with the third conductive line ML3. The third conductive line ML3may extend in the first direction. Referring to theFIG. 14B, a plurality of the string select line SSL may dispose in the concave portion. And the third conductive lines ML3of the string select lines SSL adjacent to each other may extend different direction.

The conductive lines ML1, ML2may be disposed separated in both sides with the cell array region CAR in-between. The conductive line connected with one of the conductive patterns GSL, WL1-WL4may be disposed in a contact region different from the conductive line connected with the conductive pattern adjacent to the one conductive pattern. For example, the first conductive line ML1connected with the first word line WL1may be disposed in the second contact region CR2, and the second conductive line ML2and the first conductive line ML1respectively connected with the ground select line GSL adjacent to the first word line WL1and the second word line WL2may be disposed in the first contact region CR1. In this embodiment, trenches for cutting the conductive patterns WL1-WL4, GSL and integrate layers are formed. The trenches will be used for gate replacement and filling layers including information storage layer.

An active memory string structure extending upward from the bottom surface603of the concave portion A may be disposed. The active memory string structure may extend perpendicular to the substrate601. The active memory string structure may penetrate the conductive patterns GSL, WL1-WL4, SSL. Alternatively, the active memory string structure may face sidewalls of the conductive patterns GSL, WL1-WL4, SSL. One end of the active memory string structure may be electrically connected with the common source region602. A drain region D may be disposed at the other end of the active memory string structure. The drain region D may be a region doped with a high concentration of dopant. The active memory string structure may include a single crystalline semiconductor.

A bit line contact plug BLCP may be disposed on the drain region623of the active memory string structure. The bit line contact plug BLCP may be electrically connected with the drain region623and penetrate the first interlayer insulating layer680. A bit line BL may be disposed on the bit line contact plug BLCP. The bit line BL may be connected with the drain region623of the active memory string structure through the bit line contact plug BLCP. Unlike this, the bit line BL may be directly connected with the drain region623. The bit line BL may extend in the second direction crossing the first direction. The bit line BL may cross the third conductive line ML3.

An information storage layer640may be disposed between the sidewall of the active memory string structure and the conductive patterns GSL, WL1-WL4, SSL. Layers containing the information storage layer640may be disposed between the conductive patterns GSL, WL1-WL4, SSL and the insulating layers610-615.

The information storage layer640according to the sixth embodiment of the inventive concept may be the information storage layer described with reference toFIG. 6Aor6B.

The peripheral circuit region β of the substrate601will now be described.

A peripheral circuit may be disposed on a top surface of the convex portion B of the peripheral circuit region β. A gate insulating layer654may be disposed on the top surface of the convex portion B. The gate insulating layer654may include a silicon oxide layer. The gate insulating layer654may include a portion formed by thermally oxidizing the top surface of the convex portion B. A gate electrode656may be disposed on the gate insulating layer654. The gate electrode656may include one selected from the group consisting of doped polysilicon, metal and metal silicide. A spacer658may be disposed on both sidewalls of the gate electrode656. Source and drain regions653may be disposed in the convex portion B at both sides of the gate electrode656. The source and drain regions653may be regions doped with a high concentration of dopant.

A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer680may be disposed on the gate electrode656and the source and drain regions653. A fourth conductive line ML4may be disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer690may be disposed on the fourth conductive line ML4.

A modified example of the sixth embodiment of the inventive concept will now be described.FIG. 15Bis a sectional view taken along line VI-VI′ ofFIG. 14AthroughFIG. 14B, for explaining a modified example of the sixth embodiment of the inventive concept.

Referring toFIGS. 14A through 14Band15B, a substrate600is provided. A common source region602may be disposed in the substrate600. The substrate600may include a concave portion A. The concave portion A may include a bottom surface603, and first and second sidewalls605and606facing each other. The substrate600may include a convex portion B extending from the first and second sidewalls605and606. A top surface of the convex portion B may be in parallel with the bottom surface603of the concave portion A. The convex portion B may be defined by an insulating layer604disposed on the substrate600.

Referring toFIGS. 14A and 14B, as inFIGS. 1A and 1B, an interconnection, extending outside one edge of the cell array portion, is electrically connected to contact inclining portion of a word line at one side, whereas another interconnection, extending outside the other edge of the cell array portion, is electrically connected to contact inclining portion of a word line at another side. According toFIG. 14A, all SSLs are connected to interconnections at either side, whereas some SSLs are connected to interconnections at one side, and some SSLs are connected to interconnections at another side forFIG. 14B. The word line may be chosen alternatingly. That is, odd numbered word lines from bottom to top direction of a string for example, first, third, fifth word lines are connected to interconnections at one side of a string, and even numbered word lines for example, second, fourth, sixth word lines connected to interconnections at the other side of a string.

The substrate600may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. In the peripheral circuit region β, a peripheral circuit may be disposed.

The cell region α of the substrate600will now be described.

The cell region α may include a first contact region CR1adjacent to the first sidewall605of the concave portion A, and a second contact region CR2adjacent to the second sidewall606. The memory cell explained with reference toFIG. 15Amay be disposed in the cell region α of the substrate600.

The peripheral circuit region β of the substrate600will now be described.

A peripheral circuit may be disposed on a top surface of the convex portion B of the peripheral circuit region β. A semiconductor layer672may be disposed on a top surface of the insulating layer604. The semiconductor layer672may be semiconductor materials including polysilicon, crystalline silicon and single crystalline silicon. A gate insulating layer674may be disposed on the semiconductor layer672. The gate insulating layer674may include a silicon oxide layer. The gate insulating layer674may include a portion formed by thermally oxidizing the semiconductor layer672. A gate electrode676may be disposed on the gate insulating layer674. The gate electrode676may include one selected from the group consisting of doped polysilicon, metal and metal silicide. A gate spacer678may be disposed on both sidewalls of the gate electrode676. Source and drain regions673may be disposed in the semiconductor layer672at both sides of the gate electrode676. The source and drain regions673may be regions doped with a high concentration of dopant.

A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer680may be disposed on the gate electrode676and the source and drain regions673. A fourth conductive line ML4may be disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer690may be disposed on the fourth conductive line ML4.

A semiconductor device according to another modified example of the sixth embodiment of the inventive concept will now be described. This exemplary embodiment is modified to be inclined.FIG. 15Cis a sectional view taken along line VI-VI′ ofFIG. 14, for showing this other modified example of the sixth embodiment of the inventive concept.

Referring toFIGS. 14 and 15C, a substrate601is provided. A common source region602may be disposed in the substrate601. The substrate601may include a concave portion A. The concave portion A may include a bottom surface603, and first and second sidewalls605and606facing each other. Any one of the first and second sidewalls605and606may be inclined to the bottom surface603of the concave portion A. For example, the first sidewall605and the second sidewall606may have an angle, which is 50 to 90 degrees with respect to the bottom surface603. A slope of the first sidewall605with respect to the bottom surface603may be equal to that of the second sidewall606with respect to the bottom surface603. Alternatively, the slope of the first sidewall605with respect to the bottom surface603may be different from that of the second sidewall606with respect to the bottom surface603. The substrate601may include a convex portion B extending from the first and second sidewalls605and606. A top surface of the convex portion B may be in parallel with the bottom surface603of the concave portion A. The concave portion A and the convex portion B of the substrate601may be defined through an etching process of the substrate601. Alternatively, as described with reference toFIG. 15B, the convex portion B may be defined by the insulating layer604on the substrate601.

The substrate601may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. The peripheral circuit region β may include a peripheral circuit.

The cell region α of the substrate601will now be described.

The cell region α may include a first contact region CR1adjacent to the first sidewall605of the concave portion A, and a second contact region CR2adjacent to the second sidewall606. The memory cell explained with reference toFIG. 15Amay be disposed in the cell region α of the substrate601. A contact inclining portion CT and a dummy inclining portion DCT of any one of the conductive patterns GSL, WL1-WL4, SSL may have an inclined slope with respect to a bottom portion BP.

An angle between the sidewall adjacent to the contact region where the contact inclining portion CT is disposed, and the bottom surface603may be equal to an angle between the contact inclining portion CT and the bottom portion BP. For example, in the case of the first word line WL1, a slope of the contact inclining portion CT with respect to the bottom portion BP may be equal to a slope of the second sidewall606with respect to the bottom surface603. When the slopes of the first sidewall605and the second sidewall606with respect to the bottom surface603are different from each other, the slope of the contact inclining portion with respect to the bottom portion BP in any one conductive pattern may be different from the slope of the dummy inclining portion DCT with respect to the bottom portion BP.

The peripheral circuit region β of the substrate601will now be described.

In the peripheral circuit region β of the substrate601, the peripheral circuit described with reference toFIG. 15Amay be disposed. Alternatively, as aforementioned, in the case where the substrate is the substrate described with reference toFIG. 15B, a semiconductor layer672may be added.

A method for forming a semiconductor device according to the sixth embodiment will now be described.FIGS. 16A to 16Iare cross-sectional views for explaining a method for forming a semiconductor device according to the sixth embodiment of the inventive concept.

Referring toFIG. 16A, a substrate601is provided. The substrate601may include a concave portion A. The concave portion A may include a bottom surface603, and first and second sidewalls605and606facing each other. The substrate601may include a convex portion B extended from the first and second sidewalls605and606. A top surface of the convex portion B may be in parallel with the bottom surface of the concave portion A. The concave portion A and the convex portion B of the substrate601may be defined by partially etching a portion of a substrate corresponding to the concave portion A. In this case, the substrate600may be a single body substrate.

The substrate601may include a cell region α and a peripheral circuit region β. In the cell region α, a memory cell may be disposed. The cell region α may include the concave portion A and the convex portion B. The peripheral circuit region β may include a peripheral circuit. The peripheral circuit region β may include the convex portion B.

The cell region α may include a first contact region CR1adjacent to the first sidewall605of the concave portion A, and a second contact region CR2adjacent to the second sidewall606. A cell array region CAR may be disposed between the first contact region CR1and the second contact region CR2. That is, the first contact region CR1and the second contact region CR2may be spaced apart from each other with the cell array region CAR in-between.

The substrate601may be a single crystalline semiconductor substrate (e.g., p-type silicon wafer). The substrate601may include a well. The well may be formed by introducing a dopant into the substrate601. The dopant may be introduced by a doping process including an ion implantation or a plasma implantation. A common source region602may be provided in an upper portion of the substrate601. The common source region602may be formed by doping a dopant into the well. The common source region602may include a dopant having a conductive type, which is different from the conductive type of the well. In one embodiment of the present disclosure, the common source region may be formed in the bottomed region of the trench. For example, the well may include a p-type dopant and the common source region602may include an n-type dopant.

Sacrificial layers SC1-SC6and insulating layers610-615may be alternatingly stacked on the concave portion A of the substrate601. For example, the first sacrificial layer SC1, the first inter-gate insulating layer610, the second sacrificial layer SC2, the second inter-gate insulating layer611, the third sacrificial layer SC3, the third inter-gate insulating layer612, the fourth sacrificial layer SC4, the fourth inter-gate insulating layer613, the fifth sacrificial layer SC5, the fifth inter-gate insulating layer614, the sixth sacrificial layer SC6and the string select insulating layer615may be sequentially formed. The sacrificial layers SC1-SC6and the insulating layers610-615may be also formed on the top surface of the convex portion B. Each of the sacrificial layers SC1-SC6and the insulating layers610-615may include a bottom portion on the bottom surface603of the concave portion A, and a sidewall portion extended over the first sidewall605and the second sidewall606. The material of the sacrificial layers may be a material that can be selectively removed. For example, the sacrificial layer comprises silicon nitride, which can be selectively removed by phosphoric acid or phosphor containing acid.

The insulating layers610-615may include a silicon oxide layer. The sacrificial layers SC1-SC6may be formed of materials that can minimize an etching of the insulating layers610-615and be selectively etched. For example, the sacrificial layers SC1-SC6may include a silicon nitride layer.

A planarizing process may be performed by using the top surface of the convex portion B as an etch stop layer. The planarizing process may be performed by using any of an etch-back or a chemical mechanical polishing (CMP). The top surface of the convex portion B may be coplanar with top surfaces of the sidewall portions of the insulating layers610-615. Top surfaces of the sidewall portions of the sacrificial layers SC1-SC6may be coplanar with the top surfaces of the sidewall portions of the insulating layers610-615and the top surface of the convex portion B.

Referring toFIG. 16B, first openings620exposing the bottom surface603of the concave portion A of the substrate601may be formed by patterning the alternatingly stacked insulating layers610-615and sacrificial layers SC1-SC6. The patterning for forming the openings620may be performed by an anisotropic etching technique. The first openings620may expose the bottom surface603of the concave portion A, sidewalls of the insulating layers610-615, and sidewalls of the sacrificial layers SC1-SC6.

Referring toFIG. 16C, active memory string structures covering inner walls of the openings620may be formed. The active memory string structures may be formed by conformably covering the inner walls of the openings620using a chemical vapor deposition or atomic layer deposition (ALD). The active memory string structures may be formed in the same conductive type as the substrate601which the active memory string structures contact, so that the active memory string structures may be electrically connected with the substrate601. For example, the active memory string structure may include a single crystalline silicon which is continuous with the substrate601without any crystal defect. For this purpose, the active memory string structures may be grown from the exposed substrate601by using one of epitaxial techniques. The remaining spaces of the first openings620may be filled with an insulating material624(e.g., silicon oxide, silicon nitride or air). A drain region623may be formed at an upper portion of the active memory string structure. The shape of active may be pillar, tubular or bar-sided.

A preliminary gate separating region exposing the bottom surface603of the concave portion A of the substrate601may be formed by patterning the insulating layers610-615and the sacrificial layers SC1-SC6. The preliminary gate separating region may be formed between the active memory string structures adjacent in the second direction (SeeFIG. 14). Sidewalls of the insulating layers610-615and sidewalls of the sacrificial layers SC1-SC6may be exposed by the preliminary gate separating region. The forming of the preliminary gate separating region may be the same as that of the first opening620.

Referring toFIG. 16D, the sacrificial layers SC1-SC6exposed by the preliminary gate separating region may be removed. Trenches for exposing sacrificial layers may be formed and removing the sacrificial layers is conducted by using the area formed by trenches. Gate regions630exposing the sidewalls of the active memory string structures may be formed between the insulating layers610-615. The removing of the sacrificial layers SC1-SC6may be performed by using an etch recipe having an etch selectivity with respect to the insulating material624. The removing of the sacrificial layers SC1-SC6may be performed by using a dry or wet etch, an isotropic etch, or both. At this time, filled active memory string structure and core portion of an insulating material may act as a supporter for sustaining insulating layers610-615for inter-gate layer.

Referring toFIG. 16E, layers including an information storage layer640may be conformably formed on the resultant substrate in which the gate regions630are formed. The information storage layer640may be formed on the sidewalls of the active memory string structures exposed by the gate regions630. Layers including the information storage layer640may be formed on the top surface of the convex portion B, the top surface of the string select insulating layer615, and portions of the insulating layers610-615exposed by the gate regions630.

A method for forming the information storage layer640will now be described again with reference toFIG. 6. The forming of the information storage layer640may include forming a tunnel insulating layer242covering the sidewalls of the active memory string structures, forming a charge storage layer244covering the tunnel insulating layer242, and forming a blocking layer covering the charge storage layer244.

Again referring toFIG. 16E, a preliminary gate conductive layer650filling the preliminary gate separating regions and the gate regions may be formed on the information storage layer640. The preliminary gate conductive layer650may include at least one selected from the group consisting of a polycrystalline silicon layer, silicide layers and metal layers, which are formed by using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) providing a superior step coverage. Meanwhile, since the information storage layer640is also formed on the substrate601, the preliminary gate conductive layer650may be electrically separated from the substrate601.

Referring toFIG. 16F, after the preliminary gate conductive layer650is formed, an etch process may be performed. The etch process may be performed by using a wet etch, dry etch or both. The preliminary gate conductive layer650and the information storage layer640on the top surface of the convex portion B may be removed. The preliminary gate conductive layer650of the preliminary gate separating region may be removed.

Next processes in this embodiment may be similar to those in the embodiment as demonstrated inFIGS. 13F to 13G.

By patterning the preliminary gate conductive layer650, conductive patterns GSL, WL1-WL4, SSL may be formed.

The conductive patterns GSL, WL1-WL4, SSL may include bottom portions BP disposed above the bottom surface603of the concave portion A. The conductive patterns GSL, WL1-WL4, SSL may include contact inclining portions CT extended over one of the first sidewall605and the second sidewall606from one ends of the bottom portions BP. A contact region where the contact inclining portion of any one of the conductive patterns is disposed may be different from a contact region where the contact inclining portion of another conductive pattern adjacent to the any one of the conductive patterns. An exposed top surface of the contact inclining portion CT may be coplanar with the top surface of the convex portion B.

The conductive patterns GSL, WL1-WL4, SSL may include dummy inclining portions DCT extended over the other one of the first sidewall605and the second sidewall606from the other ends of the bottom portions BP above the bottom surface603. A contact region where the dummy inclining portion of any one of the conductive patterns GSL, WL1-WL4, SSL is disposed may be different from a contact region where the dummy inclining portion of another conductive pattern adjacent to the any one of the conductive patterns. Each of the conductive patterns GSL, WL1-WL4, SSL may include one contact inclining portion CT and one dummy inclining portion DCT.

A mask pattern660covering the exposed top surface of the contact inclining portions may be formed. The mask pattern660may expose the dummy inclining portions DCT. The forming of the mask pattern660may include forming a mask layer on the substrate601, and patterning the mask layer. The mask pattern660may include a material having an etch selectivity with respect to the conductive patterns GSL, WL1-WL4, SSL and the insulating layers610-615. For example, the mask pattern660may include a silicon nitride layer or a photoresist pattern.

Referring toFIG. 16G, the dummy inclining portions DCT may be partially etched by using the mask pattern660as an etch mask. As a result, dummy recess portions662may be formed. Lengths of the dummy inclining portions DCT may be shorter than lengths of the contact inclining portions CT. Due to the dummy recess portions522, sidewalls of the insulating layers610-615may be partially exposed. The etching of the dummy inclining portions DCT may be performed by using an etch recipe in which the etch rate of the conductive patterns GSL, WL1-WL4, SSL is higher than that of the mask pattern660and the insulating layers610-615. Thereafter, the mask pattern660may be removed.

Referring toFIG. 16H, a dummy insulating layer pattern664filling the dummy recess portions662may be formed. The forming of the dummy insulating layer pattern664may include forming a dummy insulating layer on the substrate601, and performing a planarizing process by using the top surface of the convex portion B or a top surface of the string select insulating layer615as an etch stop layer. A top surface of the dummy insulating layer pattern664may be coplanar with the top surface of the convex portion B. The top surface of the dummy insulating layer pattern664may be coplanar with the top surfaces of the string select insulating layer615and the contact inclining portion CT.

A gate insulating layer674may be formed on the top surface of the convex portion B. The gate insulating layer674may be formed through a thermal oxidation process. The gate insulating layer674may include a silicon oxide layer having a thickness ranging from about 40 angstroms to about 300 angstroms. In the case where the gate insulating layer674is formed by a thermal oxidation process, an oxide layer may be formed on the top surface of the contact inclining portion CT of the conductive patterns GSL, WL1-WL4, SSL of the exposed cell region α. Therefore, prior to forming of the gate insulating layer674, a mask layer covering the concave portion A and exposing the convex portion B may be additively formed. The mask layer may be an insulating layer.

A gate electrode676may be formed on the gate insulating layer674. Source and drain regions673may be formed in the convex portion B at both sides of the gate electrode676. The source and drain regions673may be regions doped with a high concentration of dopant.

Referring toFIG. 16I, a gate spacer678may be formed on both sidewalls of the gate electrode676. A first interlayer insulating layer680covering an entire surface of the substrate601may be formed. The first interlayer insulating layer680may include a silicon oxide layer. A contact opening686exposing the top surface of the contact inclining portions CT, a bit line opening684exposing the drain region623and a peripheral circuit opening686exposing the gate electrode676of the peripheral circuit region β may be formed by etching the first interlayer insulating layer680. An opening exposing the source and drain regions673of the peripheral circuit region β may be also formed. The etching of the first interlayer insulating layer680may include etching the first interlayer insulating layer680using an anisotropic etching.

As aforementioned, in the case where the gate insulating layer674is formed by a thermal oxidation process and the mask layer is formed on the top surface of the contact inclining portions CT of the conductive patterns GSL, WL1-WL4, SSL of the cell region α, the mask layer may be etched to expose the contact inclining portions CT while the first interlayer insulating layer680is etched. Unlike this, in the case where the gate insulating layer674is formed by a thermal oxidation process but an oxide layer is formed on the top surfaces of the contact inclining portions CT of the conductive patterns GSL, WL1-WL4, SSL because a mask layer is not formed on the top surfaces of the contact inclining portions CT of the conductive patterns GSL, WL1-WL4, SSL, the oxide layer may be etched to expose the contact inclining portion CT while the first interlayer insulating layer680is etched.

Again referring toFIG. 15A, contact plugs GCP, CP, bit line contact plugs BLCP and a peripheral circuit contact plug PCP respectively filling the contact opening682, the bit line opening684and the peripheral circuit opening686may be formed.

The ground select contact plug GCP may be electrically connected with the contact inclining portion CT of the ground select line GSL. The word line contact plugs CP may be electrically connected with the word lines WL1-WL4. Each of the contact plugs GCP, CP may include a material having conductivity higher than the conductive patterns GSL, WL1-WL4. The peripheral circuit contact plug PCP may be electrically connected with the gate electrode676. The peripheral circuit contact plug PCP may include a material having conductivity higher than the gate electrode676. For example, the contact plugs GCP, CP, the bit line contact plug BLCP and the peripheral circuit contact plug PCP may include tungsten.

A second conductive line ML2may be formed on the ground select contact plug GCP. A first conductive line ML1may be formed on the word line contact plug CP. A bit line BL may be formed on the bit line contact plug BLCP. A fourth conductive line ML4may be formed on the peripheral circuit contact plug PCP. The forming of the second conductive line ML2, the first conductive line ML1, the bit line BL and the fourth conductive line ML4may include forming a conductive layer on the first interlayer insulating layer680and patterning the conductive layer.

A second interlayer insulating layer690covering the second conductive line ML2, the first conductive line ML1and the fourth conductive line ML4may be formed. The second interlayer insulating layer690may include the same material as the first interlayer insulating layer680. A string select contact plug SCP penetrating the second interlayer insulating layer690and filling an opening exposing the contact inclining portion of the string select line SSL may be formed. The string select contact plug SCP may include a material having conductivity higher than the string select line SSL. A third conductive line ML3may be formed on the string select contact plug SCP. The forming of the third conductive line ML3may include forming a conductive layer on the second interlayer insulating layer690and patterning the conductive layer. By doing so, the semiconductor device described with reference toFIG. 15Amay be provided.

Methods for forming semiconductor devices according to modified examples are now addressed.

A method for forming a semiconductor device according to the modified example of the six embodiment of the inventive concept, described with reference toFIG. 15Bwill now be described.

Referring toFIG. 15B, in the method of forming a semiconductor device described with reference toFIGS. 16A to 16I, andFIG. 15A, the forming of the concave portion A and the convex portion B of the substrate600may include forming an insulating layer604on the substrate600, etching the insulating layer604on the concave portion A, and leaving the insulating layer604on the convex portion B.

In the method for forming the peripheral circuit described with reference toFIG. 15B, a semiconductor layer672may be formed on the convex portion B of the peripheral circuit region β. For example, the semiconductor layer672may be formed by bonding the semiconductor layer672on the insulating layer604of the convex portion B or growing the semiconductor layer672. For example, the semiconductor layer672may include a single crystalline silicon or polycrystalline silicon. A gate insulating layer674may be formed on the semiconductor layer672.

A method for forming a semiconductor device according to another modified example of the sixth embodiment of the inventive concept, described with reference toFIG. 15Cwill now be described.

Referring toFIG. 15C, in the method for forming a semiconductor device described with reference toFIGS. 16A to 16IandFIG. 15A, at least one of the first sidewall605and the second sidewall606may be formed inclined with respect to the bottom surface603. In this case, the contact inclining portions CT and the dummy inclining portions DCT may be formed inclined with respect to the bottom surface603and the bottom portions BP. The sidewall portions of the insulating layers510-615may be formed inclined with respect to the bottom surface603.

The semiconductor devices according to the first to third embodiments of the inventive concept may be formed with reference to the methods for forming a semiconductor device described with reference to the foregoingFIGS. 12A to 12CandFIGS. 13A to 13H.

The semiconductor devices according to the second embodiment and the fourth embodiment of the inventive concept may be formed with reference to the methods for forming a semiconductor device described with reference to the foregoingFIGS. 15A to 15CandFIGS. 16A to 16I.

Application examples of the inventive concept will now be described.

FIG. 17is a block diagram of a memory system including a semiconductor device according to embodiments of the inventive concept.

Referring toFIG. 17, a memory system1100is applicable to personal data assistants (PDAs), portable computers, web tablets, wireless phones, mobile phones, digital music players, memory cards, and any other device capable of transmitting and/or receiving data wireless environments.

The memory system1100includes a controller1110, an input/output device1120(e.g., a keypad, keyboard, and a display), a memory1130, an interface1140, and a bus1150. The memory1130and the interface1140communicate with each other through the bus1150.

The controller1110includes at least one microprocessor, a digital signal processor, a microcontroller, or other similar processor devices. The memory1130may be used to store commands executed by the controller1110. The input/output device1120may receive/output data or signals from/to an external device of the memory system1100. For example, the input/output device1120may include a keyboard, a keypad, or a display device.

The memory1130includes a nonvolatile memory device according to the embodiments of the inventive concept. The memory1130may further include random-access nonvolatile memories and other types of memories.

The interface1140serves to transmit/receive data to/from a communication network.

FIG. 18is a block diagram of an example of a memory card having a semiconductor device according to embodiments of the inventive concept.

Referring toFIG. 18, a memory card1200for supporting high-capacity data storage is mounted with a flash memory device1210according to the inventive concept. The memory card1200includes a memory controller1220for controlling data exchange between a host and the flash memory device1210.

An SRAM1221is used as a working memory of a processing unit1222. A host interface1223has a data exchange protocol for the host connected to a memory card1200. An error correction block1224detects and corrects an error in data read from the multi-bit flash memory device1210. A memory interface1225interfaces with the flash memory device1210. The processing unit1222performs control operations for data exchange of the memory controller1220. Although not illustrated inFIG. 18, those skilled in the art will readily understand that the memory card1200may further include a ROM storing code data for interfacing with the host.

FIG. 19is a block diagram of an example of an information processing system mounted with a semiconductor device according to the inventive concept.

Referring toFIG. 19, a flash memory device1310of the inventive concept is mounted on an information processing system1300such as a mobile device or a desktop computer. The information processing system1300includes a flash memory system1310, a modem1320, a central processing unit (CPU)1330, a random access memory (RAM)1340, and a user interface1350that are electrically to a system bus1360. The flash memory system1310may be configured in substantially the same structure as the afore-mentioned memory system or flash memory system. Data, which are processed by the CPU1330or received from an external device, are stored in the flash memory system1310. Herein, the flash memory system1310may be configured to include a solid state drive (SSD). In this case, the information processing system1300can stably store a large amount of data in the flash memory system1310. According to an increase in reliability, the flash memory system1310can reduce resources taken for error correction, thus providing a high-speed data exchange function to the information processing system1300. Although not illustrated inFIG. 19, those skilled in the art will readily understand that the information processing system1300may further include an application chipset, a camera image processor (CIS), and an input/output device.

Furthermore, the flash memory or flash memory system according to embodiments of the inventive concept may be mounted in various types of packages. Examples of the packages of the flash memory or flash memory systems according to embodiments of the inventive concept may include package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), a plastic leaded chip carrier (PLCC), a plastic dual in-line package (PDIP), a multi chip package (MCP), a wafer-level package (WP), a wafer-level fabricated package (WFP), a wafer-level processed stack package (WSP), a die in waffle pack, a die in wafer form, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat pack (MQFP), a thin quad flat pack (TQFP), a small outline package (SOP), a shrink small outline package (SSOP), a thin small outline package (TSOP), a thin quad flat package (TQFP), a system in package (SIP) and so on.

FIG. 20is a block diagram of a nonvolatile memory device according to the inventive concept. Referring toFIG. 20, a nonvolatile memory device1400according to the inventive concept includes a memory cell array1430, a control logic circuit1440, a voltage generator1410, a decoding circuit1420(e.g., a row decoder) disposed on each side of the cell array1430, and a page buffer1450. The semiconductor memory device may comprises a substrate, a memory string disposed on and substantially normal to the substrate, the memory string comprising a plurality of storage cells, a plurality of word lines; and at least two row decoders. The plurality of word lines have a first group of word lines electrically connected to one row decoder at a first side of the memory string and a second group of word lines electrically connected to the other row decoder at a second side of the memory string. The interconnections, extending outside one edge of the cell array portion at one and the other side may be connected to row decoders at both sides. In this regard, the first row decoder may be connected to one group of string select lines (SSLs) at a first side of the memory string, and the second row decoders is connected to another group of SSLs at a second side of the memory string. Alternatively, either one of the two row decoders is connected to all of the string select lines (SSLs). The memory cell array1400includes memory cells that are arranged in a matrix configuration of rows or word lines and columns or bit lines. The memory cells may be arranged to have a NAND or a NOR structure. In the NAND structure, each memory cell string includes transistors that are connected in series. It will be easily understood that this inventive concept may be applied to a semiconductor device having word lines WL1-WLn, the edge of which are formed in staircase form so as to the conductive plug to connect each word line.

The control logic circuit1440is configured to control an overall operation of the nonvolatile memory device1400. In an exemplary embodiment, the control logic circuit1440controls a series of program-related operations. For example, the control logic circuit1440may be a state machine storing a program sequence. However, it will be apparent to those skilled in the art that the control logic circuit1440is not limited to the contents disclosed herein. For example, the control logic circuit1440may be configured to control an erase operation and a read operation.

Under the control of the control logic circuit1440, the voltage generator1410generates voltages to be applied to a selected word line, an unselected word line, a string select line SSL, a ground select line GSL, and a common source line CSL. Also, the voltage generator1410may generate a program voltage Vpgm, a pass voltage Vpass, a read voltage Vread, and a verify read voltage Vvfy.

Under the control of the control logic circuit1440drives a selected word line, unselected word lines, a string select line SSL, a ground select line GSL, and a common source line CSL in response to a row address.

The decoding circuit1420drives the above lines by using the voltages generated by the voltage generator1410. For example, in a program operation, the decoding circuit1420applies a program voltage Vpgm and a pass voltage Vpass respectively to a selected word line and an unselected word line.

The page buffer1450operates as a sense amplifier or a write driver. In a read operation, the page buffer1450reads data from the memory cell array1430. Specifically, the page buffer1450senses a bit line voltage, discriminates data according to the level of the bit line voltage, and stores the discriminated data therein.

According to the embodiments of the inventive concept, at least two active bars can be uniformly stacked on a semiconductor substrate without an electrical connection failure. Accordingly, dispersion of a plurality of cells formed in such a structure can be improved. In other words, nonvolatile memory devices configured to be suitable for high integration and having enhanced electrical characteristics can be realized.