Light emitting device, light emitting module, and method for manufacturing light emitting device

According to one embodiment, a light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a first insulating layer, a p-side interconnect layer, an n-side interconnect layer, and a second insulating layer. The portion of the second p-side interconnect layer has the L-shaped cross section being configured to include a p-side external terminal exposed from the first insulating layer and the second insulating layer at a third surface having a plane orientation different from the first surface and the second surface. The portion of the second n-side interconnect layer has the L-shaped cross section being configured to include an n-side external terminal exposed from the first insulating layer and the second insulating layer at the third surface.

FIELD

Embodiments described herein relate generally to a light emitting device, a light emitting module, and a method for manufacturing a light emitting device.

BACKGROUND

Applications of semiconductor light emitting devices capable of emitting visible light or white light are expanding to illumination apparatuses, backlight light sources of liquid crystal display apparatuses, display apparatuses, etc. The need to downsize in such applications is increasing more and more; and there is a need to further increase the suitability for mass production and decrease the price of the semiconductor light emitting devices.

DETAILED DESCRIPTION

According to one embodiment, a light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a first insulating layer, a p-side interconnect layer, an n-side interconnect layer, and a second insulating layer. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side electrode is provided on the second surface in a region including the light emitting layer. The n-side electrode is provided on the second surface in a region not including the light emitting layer. The first insulating layer is provided on the second surface side. The first insulating layer has a first via communicating with the p-side electrode and a second via communicating with the n-side electrode. The p-side interconnect layer includes a first p-side interconnect layer electrically connected to the p-side electrode through the first via, and a second p-side interconnect layer electrically connected to the first p-side interconnect layer and provided on an interconnect surface provided on a side of the first insulating layer opposite to the semiconductor layer. The second p-side interconnect layer includes a portion having an L-shaped cross section perpendicular to the first surface. The n-side interconnect layer includes a first n-side interconnect layer electrically connected to the n-side electrode through the second via, and a second n-side interconnect layer electrically connected to the first n-side interconnect layer, separated from the p-side interconnect layer and provided on the interconnect surface. The second n-side interconnect layer includes a portion having an L-shaped cross section perpendicular to the first surface. The second insulating layer is provided between the p-side interconnect layer and the n-side interconnect layer. The portion of the second p-side interconnect layer has the L-shaped cross section being configured to include a p-side external terminal exposed from the first insulating layer and the second insulating layer at a third surface having a plane orientation different from the first surface and the second surface. The portion of the second n-side interconnect layer has the L-shaped cross section being configured to include an n-side external terminal exposed from the first insulating layer and the second insulating layer at the third surface.

Embodiments will now be described with reference to the drawings.

Similar components in the drawings are marked with like reference numerals. A region of a portion of a wafer including multiple semiconductor layers15(chips) is illustrated in the drawings that illustrate manufacturing processes.

First Embodiment

The light emitting device10aincludes the semiconductor layer15. The semiconductor layer15includes a first surface15aand a second surface formed on the side opposite to the first surface15a. Electrodes and interconnect layers described below are provided on the second surface side; and light is emitted to the outside mainly from the first surface15aopposite to the second surface.

The semiconductor layer15includes a first semiconductor layer11and a second semiconductor layer12. The first semiconductor layer11and the second semiconductor layer12include, for example, a nitride semiconductor. The first semiconductor layer11includes, for example, a foundation buffer layer, an n-type layer, etc.; and the n-type layer functions as a lateral-direction path of current. The second semiconductor layer12includes a stacked structure in which a light emitting layer (an active layer)13is interposed between an n-type layer and a p-type layer.

The second surface side of the semiconductor layer15is patterned into an uneven configuration. The protruding portion formed on the second surface side includes the light emitting layer13. A p-side electrode16is provided on the top surface of the second semiconductor layer12, i.e., the top surface of the protruding portion. The p-side electrode16is provided in the region including the light emitting layer13.

A region without the second semiconductor layer12is provided beside the protruding portion on the second surface side of the semiconductor layer15; and an n-side electrode17is provided on the top surface of the first semiconductor layer11of the region. In other words, an n-side electrode17is provided in the region not including the light emitting layer13.

On the second surface side of the semiconductor layer15as illustrated inFIG. 5B, the surface area of the second semiconductor layer12including the light emitting layer13is greater than the surface area of the first semiconductor layer11not including the light emitting layer13.

In one of the semiconductor layers15as illustrated inFIG. 6B, the p-side electrode16provided in the region including the light emitting layer13has a surface area greater than that of the n-side electrode17not including the light emitting layer13. Thereby, a wide light emitting region is obtained. The layout of the p-side electrode16and the n-side electrode17illustrated inFIG. 6Bis an example and is not limited to the layout.

A first insulating layer (hereinbelow called simply the insulating layer)18is provided on the second surface side of the semiconductor layer15. The insulating layer18covers the semiconductor layer15, the p-side electrode16, and the n-side electrode17. There are cases where another insulating film (e.g., a silicon oxide film) is provided between the insulating layer18and the semiconductor layer15. The insulating layer18is, for example, a resin such as polyimide having excellent patternability of ultra-fine openings. Alternatively, an inorganic substance such as silicon oxide, silicon nitride, etc., may be used as the insulating layer18.

The insulating layer18includes an interconnect surface18con the side opposite to the semiconductor layer15. A first p-side interconnect layer (an inner p-side interconnect layer)21and a first n-side interconnect layer (an inner n-side interconnect layer)22are provided apart from each other on the interconnect surface18c.

The first p-side interconnect layer21is provided also inside a first via18amade in the insulating layer18to reach the p-side electrode16and is electrically connected to the p-side electrode16. It is not always necessary for the first p-side interconnect layer21to be formed on the lower surface of the insulating layer18. For example, a structure may be used in which the first p-side interconnect layer21is provided only on the p-side electrode16and the first p-side interconnect layer21is not provided outside the first via18aof the insulating layer18.

The first n-side interconnect layer22is provided also inside a second via18bmade in the insulating layer18to reach the n-side electrode17and is electrically connected to the n-side electrode17.

A second p-side interconnect layer23is provided on the surface of the first p-side interconnect layer21on the side opposite to the p-side electrode16. The first p-side interconnect layer21and the second p-side interconnect layer23are included in the p-side interconnect layer of the embodiment.

The p-side interconnect layer includes a portion provided in a configuration along the interconnect surface18cof the insulating layer18and a portion provided in a configuration along a third surface30of the plane orientation different from the first surface15aand the second surface. The cross section of the p-side interconnect layer from the portion provided along the interconnect surface18cto the portion provided along the third surface30is formed in, for example, an L-shaped configuration as illustrated inFIG. 1C. The cross section illustrated inFIG. 1Cis perpendicular to the first surface15a, the second surface and the third surface30.

The first p-side interconnect layer21is provided along the interconnect surface18con the interconnect surface18c. The second p-side interconnect layer23includes a p-side connection unit23band a p-side external terminal23a.

The p-side connection unit23bis provided along the interconnect surface18con the first p-side interconnect layer21. As illustrated inFIG. 1C, the portion having the L-shaped cross section is formed of the p-side connection unit23band the p-side external terminal23a. In other words, the second p-side interconnect layer23has a portion having an L-shaped cross section; and a portion thereof (the p-side external terminal23a) is used to form an external terminal.

The second p-side interconnect layer23is formed in a recessed configuration having the p-side connection unit23bas a bottom. The p-side external terminal23ais included in a portion of the side wall of the recessed configuration (the U-shaped configuration). That is, as illustrated inFIG. 1C, the cross-sectional configuration of the second p-side interconnect layer23is a U-shaped configuration; and a portion of the U-shaped configuration is an L-shaped configuration.

The cross-sectional configuration of the second p-side interconnect layer23is a U-shaped configuration at the cross section of the surface that intersects the interconnect surface18cand is perpendicular to the third surface30such as that illustrated inFIG. 1C. Also, as illustrated inFIG. 1B, the cross section of the second p-side interconnect layer23has a U-shaped configuration at the cross section of the surface parallel to the third surface30. As described below, the cross-sectional configuration of the second p-side interconnect layer23has a U-shaped configuration in the cross-sectional view illustrated inFIGS. 1B and 1Cbecause the second p-side interconnect layer23has a cup-like configuration.

A second n-side interconnect layer24is provided on the surface of the first n-side interconnect layer22on the side opposite to the n-side electrode17. The first n-side interconnect layer22and the second n-side interconnect layer24are included in the n-side interconnect layer of the embodiment.

The n-side interconnect layer includes a portion provided in a configuration along the interconnect surface18cof the insulating layer18and a portion provided in a configuration along the third surface30of a plane orientation different from the first surface15aand the second surface. The n-side interconnect layer from the portion provided along the interconnect surface18cto the portion provided along the third surface30is formed in, for example, an L-shaped configuration.

The first n-side interconnect layer22is provided along the interconnect surface18con the interconnect surface18c. The second n-side interconnect layer24includes an n-side connection unit24band an n-side external terminal24a.

The n-side connection unit24bis provided along the interconnect surface18con the first n-side interconnect layer22. A portion having an L-shaped cross section is formed of the n-side connection unit24band the n-side external terminal24ain the cross-sectional view parallel to the cross section illustrated inFIG. 1C. In other words, the second n-side interconnect layer24includes a portion having an L-shaped cross section; and a portion thereof (the n-side external terminal24a) is used to form an external terminal.

The second n-side interconnect layer24is formed in a recessed configuration having the n-side connection unit24bas a bottom. The n-side external terminal24ais included in a portion of the side wall of the recessed configuration (the U-shaped configuration). That is, the cross section configuration of the second n-side interconnect layer24has a U-shaped configuration; and a portion of the U-shaped configuration is an L-shaped configuration.

The cross-sectional configuration of the second n-side interconnect layer24has a U-shaped configuration at a cross-sectional view parallel to the cross-sectional view illustrated inFIG. 1Cwhich is the cross-sectional view of a surface that intersects the interconnect surface18cand is perpendicular to the third surface30. Also, as illustrated inFIG. 1B, the cross section of the second n-side interconnect layer24has a U-shaped configuration at the cross-sectional view of a surface parallel to the third surface30. As described below, the cross-sectional configuration of the second n-side interconnect layer24has a U-shaped configuration in cross-sectional views at cross sections parallel to the cross-sectional view illustrated inFIG. 1Band the cross-sectional view illustrated inFIG. 1Cbecause the second n-side interconnect layer24has a cup-like configuration.

A resin layer25is provided as a second insulating layer on the interconnect surface18cof the insulating layer18. The resin layer25covers the first p-side interconnect layer21and the first n-side interconnect layer22. However, as illustrated inFIG. 1A, a side surface21aof a portion of the first p-side interconnect layer21and a side surface22aof a portion of the first n-side interconnect layer22are exposed from the resin layer25and the insulating layer18without being covered with the resin layer25and the insulating layer18.

The resin layer25is filled between the second p-side interconnect layer23and the second n-side interconnect layer24. The side walls of the second p-side interconnect layer23other than the p-side external terminal23aare covered with the resin layer25. The side walls of the second n-side interconnect layer24other than the n-side external terminal24aare covered with the resin layer25.

The end portion of the second p-side interconnect layer23on the side opposite to the first p-side interconnect layer21also is covered with the resin layer25. Similarly, the end portion of the second n-side interconnect layer24on the side opposite to the first n-side interconnect layer22also is covered with the resin layer25.

A resin layer35is filled as a third insulating layer inside the recessed configuration (the U-shaped configuration) of the second p-side interconnect layer23and similarly inside the recessed configuration (the U-shaped configuration) of the second n-side interconnect layer24.

The end portion of the resin layer35on the side opposite to the first p-side interconnect layer21is covered with the resin layer25. Accordingly, the second p-side interconnect layer23and the resin layer25are provided around the resin layer35provided inside the second p-side interconnect layer23. Similarly, the second n-side interconnect layer24and the resin layer25are provided around the resin layer35provided inside the second n-side interconnect layer24. The second p-side interconnect layer23and the second n-side interconnect layer24are covered with the resin layer25and the resin layer35.

The light emitting device10aillustrated inFIGS. 1A to 1Cis mounted such that the third surface30is the mounting surface (the surface opposing the mounting substrate) as illustrated inFIG. 2. In such a case, the p-side external terminal23a, the exposed surface21aof the first p-side interconnect layer21, and a metal film20between the p-side external terminal23aand the surface21aare used as the external terminal of the p side.

The film thickness of the metal film20is about several nanometers; and the surface area of the metal film20exposed at the third surface30is smaller than that of the exposed surface21aof the first p-side interconnect layer21. The height-direction thickness of the exposed surface21aof the first p-side interconnect layer21inFIGS. 1B and 1Cis smaller than that of the p-side external terminal23a. Therefore, the surface area of the exposed surface21aof the first p-side interconnect layer21exposed at the third surface30is smaller than that of the p-side external terminal23a.

Similarly for the n side, the metal film20, the exposed surface22aof the first n-side interconnect layer22, and the n-side external terminal24ahave surface areas exposed at the third surface30that increase in this order.

As illustrated inFIGS. 1A and 1C, the side surface of a portion of the second p-side interconnect layer23is exposed from the insulating layer18and the resin layer25at the third surface30of the plane orientation different from the first surface15aand the second surface of the semiconductor layer15. This exposed surface functions as the p-side external terminal23afor mounting to an external mounting substrate. The p-side external terminal23ais formed to spread along the third surface30from one end portion of the p-side connection unit23b.

Herein, the third surface30is a surface substantially perpendicular to the first surface15aand the second surface. The resin layer25has four side surfaces having, for example, rectangular configurations; and one of the side surfaces having a relatively long side is used as the third surface30.

The side surface of a portion of the second n-side interconnect layer24is exposed from the insulating layer18and the resin layer25at the same third surface30. The exposed surface functions as the n-side external terminal24afor mounting to the external mounting substrate. The n-side external terminal24ais formed to spread along the third surface30from one end portion of the n-side connection unit24b.

As illustrated inFIG. 1A, the side surface21aof a portion of the first p-side interconnect layer21functions as the p-side external terminal by being exposed from the insulating layer18and the resin layer25at the third surface30. Similarly, the side surface22aof a portion of the first n-side interconnect layer22functions as the n-side external terminal by being exposed from the insulating layer18and the resin layer25at the third surface30.

For the p-side interconnect layer, which includes the first p-side interconnect layer21and the second p-side interconnect layer23, the portions other than the portions21aand23aexposed at the third surface30are covered with the insulating layer18or the resin layer25. For the n-side interconnect layer, which includes the first n-side interconnect layer22and the second n-side interconnect layer24, the portions other than the portions22aand24aexposed at the third surface30are covered with the insulating layer18or the resin layer25. The structure of the embodiment is an example; and the p-side interconnect layer and the n-side interconnect layer may be partially exposed elsewhere than the third surface30.

As illustrated inFIG. 8B, the distance between the side surface21aof the first p-side interconnect layer21exposed at the third surface30and the side surface22aof the first n-side interconnect layer22exposed at the third surface30are greater than the distance between the first p-side interconnect layer21and the first n-side interconnect layer22on the interconnect surface18cof the insulating layer18.

The surface area of the first p-side interconnect layer21can be increased by reducing the distance on the interconnect surface18cof the insulating layer18between the first p-side interconnect layer21and the first n-side interconnect layer22covered with the resin layer25. The planar size of the first p-side interconnect layer21is larger than the planar size of the p-side connection unit23bof the second p-side interconnect layer23. The first p-side interconnect layer21can be formed using a low-resistance metal such as, for example, copper. Therefore, it is possible to supply current with a more uniform distribution to the second semiconductor layer12including the light emitting layer13as the surface area of the first p-side interconnect layer21is increased. Further, the thermal conductivity of the first p-side interconnect layer21also can be increased; and it is possible to efficiently release the heat generated at the second semiconductor layer12.

The p-side electrode16spreads in a region including the light emitting layer13. Accordingly, by connecting the first p-side interconnect layer21to the p-side electrode16through a plurality of the first vias18a, the current distribution to the light emitting layer13can be improved; and the heat dissipation of the heat generated at the light emitting layer13also can be improved.

The side surface21aof the first p-side interconnect layer21exposed at the third surface30is separated from the side surface22aof the first n-side interconnect layer22exposed at the third surface30by a distance such that the side surface21aand the side surface22aare not shorted to each other by a bonding agent such as solder when mounting to the mounting substrate.

A contact area between the first n-side interconnect layer22and the n-side connection unit24bof the second n-side interconnect layer24is greater than a contact area between the first n-side interconnect layer22and the n-side electrode17. A portion of the first n-side interconnect layer22extends over the interconnect surface18cof the insulating layer18to an overlaying position under the light emitting layer13.

Thereby, a wider lead electrode can be formed from the n-side electrode17provided in a narrow region not including the light emitting layer13via the first n-side interconnect layer22while obtaining a high light output due to the light emitting layer13being formed over a wide region.

A contact area between the first p-side interconnect layer21and the p-side connection unit23bof the second p-side interconnect layer23may be greater than or less than a contact area between the first p-side interconnect layer21and the p-side electrode16.

The first semiconductor layer11is electrically connected to the second n-side interconnect layer24including the n-side external terminal24avia the n-side electrode17and the first n-side interconnect layer22. The second semiconductor layer12including the light emitting layer13is electrically connected to the second p-side interconnect layer23including the p-side external terminal23avia the p-side electrode16and the first p-side interconnect layer21.

The resin layer25is thicker than the thickness (the height) of the p-side interconnect structure portion including the first p-side interconnect layer21, the second p-side interconnect layer23, and the resin layer35provided inside the second p-side interconnect layer23. Similarly, the resin layer25is thicker than the thickness (the height) of the n-side interconnect structure portion including the first n-side interconnect layer22, the second n-side interconnect layer24, and the resin layer35provided inside the second n-side interconnect layer24. The p-side interconnect structure portion and the n-side interconnect structure portion are thicker than the semiconductor layer15. Therefore, the mechanical strength of the light emitting device10acan be increased by the p-side interconnect structure portion, the n-side interconnect structure portion, and the resin layer25even without a substrate supporting the semiconductor layer15.

The materials of the first p-side interconnect layer21, the first n-side interconnect layer22, the second p-side interconnect layer23, and the second n-side interconnect layer24may include copper, gold, nickel, silver, etc. Of these, good thermal conductivity, high migration resistance, and excellent adhesion with insulating materials are obtained when copper is used.

The resin layer25reinforces the p-side interconnect structure portion and the n-side interconnect structure portion described above. It is notable for the resin layer25to have a coefficient of thermal expansion near to or the same as that of the mounting substrate. Examples of such a resin layer25include, for example, an epoxy resin, a silicone resin, a fluorocarbon resin, etc. Also, it is notable for the resin layer35to have a coefficient of thermal expansion near to or the same as that of the mounting substrate; and the same material as that of the resin layer25can be used.

A lens26and a phosphor layer27are provided on the first surface15aof the semiconductor layer15as a transparent body transparent to the light emitted from the light emitting layer13. The lens26is provided on the first surface15a; and the phosphor layer27is provided to cover the lens26.

The planar size of the stacked body including each of the components described above provided on the second surface side of the semiconductor layer15is substantially the same as the planar size of the phosphor layer27. The lens26and the phosphor layer27do not obstruct the mounting onto a mounting substrate100of the light emitting device10aillustrated inFIG. 2because the lens26and the phosphor layer27do not jut into the third surface30side.

The phosphor layer27includes a transparent resin and a phosphor dispersed in the transparent resin. The phosphor layer27is capable of absorbing the light emitted from the light emitting layer13and emitting wavelength-converted light. Therefore, the light emitting device10ais capable of emitting a mixed light of the light from the light emitting layer13and the wavelength-converted light of the phosphor layer27.

For example, white, lamp, etc., can be obtained as the mixed color of a blue light from the light emitting layer13and a yellow light which is the wavelength-converted light of the phosphor layer27in the case where the light emitting layer13is a nitride semiconductor and the phosphor is a yellow phosphor configured to emit yellow light. The phosphor layer27may have a configuration including multiple types of phosphors (e.g., a red phosphor configured to emit red light and a green phosphor configured to emit green light).

The light emitted from the light emitting layer13is emitted to the outside mainly by traveling through the first semiconductor layer11, the first surface15a, the lens26, and the phosphor layer27. The lens26may be provided on the phosphor layer27.

FIG. 2is a schematic cross-sectional view of the light emitting module having a configuration in which the light emitting device10adescribed above is mounted on the mounting substrate100.

The number of the light emitting devices10amounted on the mounting substrate100is arbitrary and may be single or multiple. Multiple light emitting devices10amay be included in a line-shaped light source by being arranged along some one direction.

The light emitting device10ais mounted with an orientation in which the third surface30faces a mounting surface103of the mounting substrate100. The p-side external terminal23aand the n-side external terminal24aexposed at the third surface30are bonded respectively to pads101formed in the mounting surface103via solder102. An interconnect pattern also is formed in the mounting surface103of the mounting substrate100; and the pads101are connected to the interconnect pattern. Other metals or electrically conductive materials other than solder may be used instead of the solder102.

The third surface30is substantially perpendicular to the first surface15awhich is the main emitting surface of the light. Accordingly, the first surface15ais configured to face the lateral direction instead of upward from the mounting surface103when the third surface30faces downward toward the mounting surface103side. In other words, a so-called side-view type light emitting device10aand light emitting module are obtained in which the light is emitted in the lateral direction in the case where the mounting surface103is taken to be a horizontal surface.

In the embodiment, the stress applied to the semiconductor layer15via the solder102in the state in which the light emitting device10ais mounted to the mounting substrate100can be relieved by being absorbed by the resin layer35filled inside the second p-side interconnect layer23and inside the second n-side interconnect layer24. The resin layer35is more flexible than metal; and a high stress relieving effect is obtained.

The substance inside the second p-side interconnect layer23and inside the second n-side interconnect layer24is not limited to a resin; and an insulator or a metal of a material different from the second p-side interconnect layer23and the second n-side interconnect layer24may be filled. It is sufficient for the material filled inside the second p-side interconnect layer23and inside the second n-side interconnect layer24to be more flexible than the second p-side interconnect layer23the second n-side interconnect layer24.

The stress relieving effect described above is obtained if, for example, a metal more flexible than the second p-side interconnect layer23and the second n-side interconnect layer24is selected as the material filled inside the second p-side interconnect layer23and inside the second n-side interconnect layer24. It is also possible to select a metal film easily formed into a conformal film as the second p-side interconnect layer23and the second n-side interconnect layer24and to form an easily-fillable metal instead of the resin layer35.

From the aspects of stress relief, productivity, and cost, it is notable for the resin to be filled inside the second p-side interconnect layer23and inside the second n-side interconnect layer24.

The planar configuration of the light emitting device10aof the embodiment is a rectangular configuration as viewed from a direction perpendicular to the first surface15a; and the third surface30is a surface including the long side of the rectangular configuration.

A method for manufacturing the light emitting device10aof the embodiment will now be described with reference toFIG. 3AtoFIG. 16B. A region of a portion of the wafer state is illustrated in the drawings that illustrate processes.

FIG. 3Aillustrates a stacked body in which the first semiconductor layer11and the second semiconductor layer12are formed on a major surface of a substrate5.FIG. 3Bcorresponds to the bottom view ofFIG. 3A.

The first semiconductor layer11is formed on the major surface of the substrate5; and the second semiconductor layer12including the light emitting layer13is formed on the first semiconductor layer11. In the case where the first semiconductor layer11and the second semiconductor layer12are, for example, nitride semiconductors, crystal growth of the first semiconductor layer11and the second semiconductor layer12can be performed by, for example, metal organic chemical vapor deposition (MOCVD) on a sapphire substrate.

For example, the first semiconductor layer11includes a foundation buffer layer and an n-type GaN layer. The second semiconductor layer12includes the light emitting layer (the active layer)13and a p-type GaN layer. The light emitting layer13may include a substance configured to emit blue, violet, bluish-violet, and ultraviolet light, etc.

The surface of the first semiconductor layer11contacting the substrate5is the first surface15aof the semiconductor layer15; and the top surface of the second semiconductor layer12is a second surface15bof the semiconductor layer15.

Then, as illustrated inFIG. 4AandFIG. 4Bwhich is the bottom view thereof, a trench is made in dicing regions d1and d2to reach the substrate5by piercing the semiconductor layer15by, for example, Reactive Ion Etching (RIE) using a not-illustrated resist. The dicing regions d1and d2are formed in, for example, a lattice configuration on the substrate5of the wafer state. The trench made in the dicing regions d1and d2also is made in a lattice configuration to separate the semiconductor layer15into multiple chips.

The process of multiply separating the semiconductor layer15may be performed after the selective removal of the second semiconductor layer12or after the formation of the electrodes described below.

Then, as illustrated inFIG. 5AandFIG. 5Bwhich is the bottom view thereof, a portion of the first semiconductor layer11is exposed by removing a portion of the second semiconductor layer12by, for example, RIE using a not-illustrated resist. The region where the first semiconductor layer11is exposed does not include the light emitting layer13.

In the case where one subdivided semiconductor layer15made of the first semiconductor layer11, the second semiconductor layer12, and the light emitting layer (the active layer)13is used as one light emitting element, each of the four light emitting elements subdivided by the dicing region d1in the lateral direction inFIG. 5Bis subdivided by the dicing region d2to be arranged as two light emitting elements in the vertical direction.

Then, as illustrated inFIG. 6AandFIG. 6Bwhich is the bottom view thereof, the p-side electrode16and the n-side electrode17are formed on the second surface. The p-side electrode16is formed on the top surface of the second semiconductor layer12. The n-side electrode17is formed on the exposed surface of the first semiconductor layer11.

The p-side electrode16and the n-side electrode17are formed using, for example, sputtering, vapor deposition, etc. Either one of the p-side electrode16and the n-side electrode17may be formed first; and the p-side electrode16and the n-side electrode17may be formed simultaneously from the same material.

The p-side electrode16is reflective with respect to the light emitted from the light emitting layer13and includes, for example, silver, silver alloy, aluminum, aluminum alloy, etc. A configuration including a metal protective film also may be used to prevent sulfidization and oxidization of the p-side electrode16.

For example, a silicon nitride film or a silicon oxide film may be formed as a passivation film between the p-side electrode16and the n-side electrode17, and on the end surface (the side surface) of the light emitting layer13by using chemical vapor deposition (CVD). Activation annealing, etc., are implemented if necessary to provide ohmic contact between the electrodes and the semiconductor layer.

Then, as illustrated inFIG. 7A, all of the exposed portions on the major surface of the substrate5are covered with the insulating layer18; and subsequently, the first via18aand the second via18bare made selectively in the insulating layer18by patterning the insulating layer18using, for example, wet etching. The first via18areaches the p-side electrode16. The second via18breaches the n-side electrode17.

An organic material such as, for example, photosensitive polyimide, benzocyclobutene, etc., can be used as the insulating layer18. In such a case, the insulating layer18may be directly exposed and developed without using a resist. Alternatively, an inorganic film such as a silicon nitride film, a silicon oxide film, etc., may be used as the insulating layer18. In the case of the inorganic film, the first via18aand the second via18bare made using etching after the resist is patterned.

Then, as illustrated inFIG. 7B, a metal film19that functions as a seed metal during the plating described below is formed on the interconnect surface18c(the lower surface inFIG. 7A) which is the surface of the insulating layer18on the side opposite to the semiconductor layer15. The metal film19is formed also on the inner wall and the bottom of the first via18aand on the inner wall and the bottom of the second via18b.

The metal film19is formed using, for example, sputtering. The metal film19includes, for example, a stacked film of titanium (Ti) and copper (Cu) stacked in order from the insulating layer18side.

Then, as illustrated inFIG. 7C, a resist41is selectively formed on the metal film19; and subsequently, Cu electroplating is performed using the metal film19as a current path.

Thereby, as illustrated inFIG. 8AandFIG. 8Bwhich is the bottom view thereof, the first p-side interconnect layer21and the first n-side interconnect layer22are formed selectively on the interconnect surface18cof the insulating layer18. The first p-side interconnect layer21and the first n-side interconnect layer22are made of, for example, a copper material formed simultaneously using plating.

The first p-side interconnect layer21is formed also inside the first via18aand is electrically connected to the p-side electrode16via the metal film19. The first n-side interconnect layer22is formed also inside the second via18band is electrically connected to the n-side electrode17via the metal film19.

The resist41used in the plating of the first p-side interconnect layer21and the first n-side interconnect layer22is removed using a solvent or oxygen plasma (FIG. 9A).

Then, as illustrated inFIG. 9B, a resist42is formed on the interconnect surface18cside of the insulating layer18. The resist42is thicker than the resist41described above. The resist41may remain without being removed in the previous process; and the resist42may be formed to overlay the resist41. A recess42aand a recess42bare formed in the resist42.

Continuing, the metal film20that functions as a seed metal during the plating is formed on the inner walls of the recesses42aand42bwhich include the top surface of the resist42, the top surface of the first p-side interconnect layer21exposed at the recess42a, and the top surface of the first n-side interconnect layer22exposed at the recess42b. The metal film20includes, for example, copper.

Then, Cu electroplating is performed using the metal film20as a current path. Thereby, as illustrated inFIG. 10AandFIG. 10Bwhich is the bottom view thereof, a metal film50is formed on the metal film20.

The broken lines ofFIG. 10Billustrate the edges of the recesses42aand42bmade in the resist42. A notch is made in a corner portion of a portion of the recess42awhen viewed in plan; and the metal film20and the metal film50are not formed on the insulating layer18under the notch. Therefore, as described below referring toFIG. 12B, a notch90is made in the corner portion of a portion of the second p-side interconnect layer23.

This plating is conformal plating in which Cu precipitates with a substantially uniform rate to conform to the uneven configuration of the metal film20and the resist42which is the foundation. Accordingly, the metal film50is formed to conform to the uneven configuration of the foundation; and the recess42aand the recess42bare not filled with the metal film50. Accordingly, the plating time and the costs can be reduced compared to the case where the recess42aand the recess42bare filled with a metal.

The metal film50is formed with substantially the same film thickness at the portions on the first p-side interconnect layer21(the bottom of the recess42a), on the first n-side interconnect layer22(the bottom of the recess42b), on the side wall of the recess42a, and on the side wall of the recess42b.

As illustrated inFIG. 10B, the metal film50is formed along the side wall of the recess42ain a closed pattern that encloses the central side of the recess42a. Similarly, the metal film50is formed along the side wall of the recess42bin a closed pattern that encloses the central side of the recess42b.

Then, as illustrated inFIG. 11AandFIG. 11Bwhich is the bottom view thereof, the resin layer35is formed inside the recess42a, inside the recess42b, and on the resist42using, for example, printing, molding, etc. The resin layer35is filled inside the recess42aand inside the recess42b.

The resin layer35is insulative. The resin layer35may be provided with a light-shielding property with respect to the light emitted from the light emitting layer by containing, for example, carbon black. The resin layer35may contain a powder that is reflective with respect to the light emitted from the light emitting layer.

Then, the end portion of the metal film50formed on the side walls of the recess42aand the recess42bis exposed by polishing the top surface side (the lower surface side ofFIG. 11A) of the resin layer35. The state is illustrated inFIG. 12AandFIG. 12Bwhich is the bottom view thereof.

Thereby, the portion of the metal film50inside the recess42ais partitioned from the portion of the metal film50inside the recess42b. The metal film50remaining inside the recess42ais used to form the second p-side interconnect layer23. The metal film50remaining inside the recess42bis used to form the second n-side interconnect layer24.

The second p-side interconnect layer23is connected to the first p-side interconnect layer21via the metal film20. Alternatively, the metal film20may be included in the second p-side interconnect layer of the embodiment.

The second n-side interconnect layer24is connected to the first n-side interconnect layer22via the metal film20. Alternatively, the metal film20may be included in the second n-side interconnect layer of the embodiment.

The side wall of a portion of the second p-side interconnect layer23is used to form the p-side external terminal23aexposed at the third surface30after the dicing. The side wall of a portion of the second n-side interconnect layer24is used to form the n-side external terminal24aexposed at the third surface30after the dicing.

As illustrated inFIG. 12B, the embodiment has a layout in which the p-side external terminal23aand the n-side external terminal24ajut onto the dicing region d2extending in a direction along the third surface30described above. Single dot-dash lines e1and e2ofFIG. 12Billustrate the two edges of the dicing blade respectively.

The notch90is made in the corner portion of a portion of the second p-side interconnect layer23on the second n-side interconnect layer24side. The notch90is formed between the p-side external terminal23aand the n-side external terminal24a. Therefore, the separation distance between the p-side external terminal23aand the n-side external terminal24aexposed to the outside after the dicing can be a distance sufficient to avoid shorts due to solder, etc., when mounting.

The portions of the second p-side interconnect layer23where the notch90is not made can be proximal to the second n-side interconnect layer24to the limitations of the processes; and the surface area of the second p-side interconnect layer23can be increased. As a result, the current distribution and the heat dissipation can be improved.

The p-side external terminal23aand the n-side external terminal24aexist on both width-direction sides of the dicing region d2without existing with a bias toward one width-direction side of the dicing region d2. In other words, the p-side external terminal23aand the n-side external terminal24a, which are metals, do not exist with a bias toward one width-direction edge side of the dicing blade.

The case where the dicing region d2is subdivided using a blade from left to right for a wafer including a layout such as that illustrated inFIG. 12Bwill now be described.

In the case where one light emitting element is taken to be a pair of one second p-side interconnect layer23and one second n-side interconnect layer24, the light emitting elements are arranged inFIG. 12Bwith four in the lateral direction and two in the vertical direction.

InFIG. 12B, the light emitting element at the leftmost top and the light emitting element second from the right at the top have a portion of the second p-side interconnect layer23(the lower side) and a portion of the second n-side interconnect layer24(the lower side) that exist in the dicing region d2. InFIG. 12B, the light emitting element at the rightmost bottom and the light emitting element second from the left at the bottom have a portion of the second p-side interconnect layer23(the upper side) and a portion of the second n-side interconnect layer24(the upper side) that exist in the dicing region d2.

In the case where the dicing region d2is subdivided using a blade from left to right, the upper side of the blade inFIG. 12Bhas a higher proportion in contact with metal than does the lower side when cutting between the leftmost light emitting elements on the top and the bottom; and when cutting between the light emitting elements second from the left on the top and the bottom, this is the reverse of that of the leftmost, and the lower side of the blade inFIG. 12Bhas a higher proportion in contact with metal than does the upper side. Therefore, the occurrence of clogging, damage, etc., due to an excessive load on one width-direction edge of the dicing blade when dicing can be suppressed.

Although the p-side external terminal23aand the n-side external terminal24aexisting on the edge e1side are arranged alternately with the p-side external terminal23aand the n-side external terminal24aexisting on the edge e2side as viewed from the direction in which the dicing region d2extends inFIG. 12B, this is not limited to such a layout. It is sufficient for the p-side external terminal23aand the n-side external terminal24anot to exist with a bias toward the side of one selected from the edge e1and the edge e2.

Even in the case where the p-side external terminal23aand the n-side external terminal24aexist with a bias toward one side of one selected from the edge e1and the edge e2, the clogging, damage, etc., of the blade when dicing can be suppressed by increasing the replacement frequency of the blade, etc.

By exposing the end portion of the second p-side interconnect layer23on the lower side ofFIG. 12Aand the end portion of the second n-side interconnect layer24on the lower side ofFIG. 12A, various inspections can be performed by causing the light emitting device to emit light by supplying a current by bringing measurement probes of different polarities into contact with the end portions respectively. Inspections may be performed at the wafer level for which handling is easy.

Then, the resist42is removed using, for example, a solvent or oxygen plasma (FIG. 13A). The resin layer35enclosed with the second p-side interconnect layer23and a resin layer34enclosed with the second n-side interconnect layer24remain.

Subsequently, the exposed portions of the metal film19formed on the interconnect surface18care removed by wet etching using the p-side interconnect structure portion including the first p-side interconnect layer21, the second p-side interconnect layer23, and the resin layer35, and the n-side interconnect structure portion including the first n-side interconnect layer22, the second n-side interconnect layer24, and the resin layer35as a mask. Thereby, as illustrated inFIG. 13B, the electrical connection between the first p-side interconnect layer21and the first n-side interconnect layer22via the metal film19is broken.

Then, as illustrated inFIG. 14A, the resin layer25is stacked on the insulating layer18. The resin layer25covers the p-side interconnect structure portion and the n-side interconnect structure portion described above.

The resin layer25is insulative. The resin layer25may be provided with a light-shielding property with respect to the light emitted from the light emitting layer by the resin layer25containing, for example, carbon black. The resin layer25may contain a powder that is reflective with respect to the light emitted from the light emitting layer. The adhesion strength between the resin layer25and the resin layer35can be increased and the reliability can be increased by forming the resin layer25and the resin layer35of the same material.

Then, as illustrated inFIG. 14B, the substrate5is removed. The substrate5is removed by, for example, laser lift-off. Specifically, laser light is irradiated from the back surface side of the substrate5toward the first semiconductor layer11. The laser light is transmissive with respect to the substrate5and has a wavelength in the absorption region of the first semiconductor layer11.

When the laser light reaches the interface between the substrate5and the first semiconductor layer11, the first semiconductor layer11proximal to the interface decomposes by absorbing the energy of the laser light. For example, in the case where the first semiconductor layer11is GaN, the first semiconductor layer11decomposes into gallium (Ga) and nitrogen gas. A micro gap is made between the substrate5and the first semiconductor layer11by the decomposition reaction; and the substrate5and the first semiconductor layer11separate.

The irradiation of the laser light is performed over the entire wafer by performing multiply for every set region; and the substrate5is removed.

Because the stacked body described above formed on the major surface of the substrate5is reinforced by the thick resin layer25, it is possible to maintain the wafer state even in the case where there is no substrate5. The resin layers25and35and the metals included in the interconnect layers are materials more flexible than the semiconductor layer15. Therefore, destruction of the device can be avoided even in the case where the large internal stress generated in the epitaxial process that forms the semiconductor layer15on the substrate5is relieved all at once when peeling the substrate5.

The first surface15aof the semiconductor layer15from which the substrate5is removed is cleaned. For example, the gallium (Ga) adhered to the first surface15ais removed using hydrochloric acid, etc.

Etching (frosting) is performed on the first surface15ausing, for example, a KOH (potassium hydroxide) aqueous solution, TMAH (tetramethylammonium hydroxide), etc. Thereby, an unevenness is formed in the first surface15adue to the difference of the etching rates that depend on the crystal plane orientation (FIG. 15A). Alternatively, the unevenness may be formed in the first surface15aby performing etching after the patterning using the resist. The light extraction efficiency can be increased by the unevenness being formed in the first surface15a.

Then, as illustrated inFIG. 15B, the lens26is formed on the first surface15a. The lens26is transparent to the light emitted from the light emitting layer and may include, for example, a silicone resin, an acrylic resin, glass, etc. The lens26may be formed by etching using, for example, a grayscale mask or imprinting.

Then, the phosphor layer27is formed on the first surface15aand on the insulating layer18exposed between the mutually-adjacent semiconductor layers15to cover the lens26. For example, a liquid transparent resin in which phosphor particles are dispersed is supplied using a method such as printing, potting, molding, compression molding, etc., and is subsequently thermally cured. The transparent resin is transmissive with respect to the light emitted from the light emitting layer and the light emitted by the fluorescer and may include a material such as, for example, a silicone resin, an acrylic resin, liquid glass, etc.

Continuing as illustrated inFIG. 16AandFIG. 16Bwhich is the bottom view thereof, singulation into the multiple light emitting devices10ais performed by cutting the phosphor layer27, the insulating layer18, and the resin layer25at the positions of the dicing regions d1and d2formed in the lattice configuration. For example, the cutting is performed using a dicing blade. Alternatively, the cutting may be performed using laser irradiation.

At this time, the portions of the second p-side interconnect layer23and the second n-side interconnect layer24jutting into the dicing region d2extending in the direction along the third surface30are cut. Thereby, the p-side external terminal23aand the n-side external terminal24aare exposed at the third surface30.

Because the metal film20used as the seed metal during the plating described above is thin, the metal film20formed on the p-side external terminal23aand the n-side external terminal24ais removed when dicing.

Similarly, if portions of the first p-side interconnect layer21and the first n-side interconnect layer22jut into the dicing region d2, such portions jutting into the dicing region d2are cut. Thereby, the side surface21aof the first p-side interconnect layer21and the side surface22aof the first n-side interconnect layer22also are exposed at the third surface30.

Alternatively, because the film thickness of the first p-side interconnect layer21and the film thickness of the first n-side interconnect layer22are thin, the exposed surface area of the third surface30is extremely small compared to the p-side external terminal23aand the n-side external terminal24a. Accordingly, the first p-side interconnect layer21and the first n-side interconnect layer22may not be exposed at the third surface30. The function of the external terminals is sufficiently provided by just the p-side external terminal23aand the n-side external terminal24a.

The layout illustrated inFIG. 31is notable in the case where a portion of the first p-side interconnect layer21and a portion of the first n-side interconnect layer22are exposed at the third surface30.

InFIG. 31, the dicing region d2extends in a direction (inFIG. 31, the lateral direction) along the side surface21aof the first p-side interconnect layer21and the side surface22aof the first n-side interconnect layer22exposed at the third surface30. The side surface21aand the side surface22ajut onto the dicing region d2. InFIG. 31, the single dot-dash lines e1and e2illustrate the two edges of the dicing blade respectively.

A notch21bis made in a portion of the first p-side interconnect layer21on the first n-side interconnect layer22side and on the side surface21aside. The notch21bis formed between the side surface21aand the side surface22a. Therefore, the separation distance between the side surface21aand the side surface22aexposed to the outside after the dicing can be a distance sufficient to avoid shorts due to solder, etc., when mounting.

In the portion where the notch21bis not made, the first p-side interconnect layer21can be proximal to the first n-side interconnect layer22to the limitations of the processes; and the surface area of the first p-side interconnect layer21can be increased. As a result, the first p-side interconnect layer21and the p-side electrode16can be connected through the multiple first vias18a; and the current distribution and the heat dissipation can be improved.

The side surface21aand the side surface22aexist on both width-direction sides of the dicing region d2without existing with a bias toward one width-direction side of the dicing region d2. In other words, the side surface21aand the side surface22a, which are metals, do not exist with a bias toward one width-direction edge side of the dicing blade. Therefore, the occurrence of clogging, damage, etc., due to an excessive load on one width-direction edge of the dicing blade when dicing can be suppressed.

Although the side surface21aand the side surface22aexisting on the edge e1side are arranged alternately with the side surface21aand the side surface22aexisting on the edge e2side as viewed from the direction in which the dicing region d2extends inFIG. 31, this is not limited to such a layout. It is sufficient for the side surface21aand the side surface22anot to exist with a bias toward one side of one selected from the edge e1and the edge e2.

Even in the case where the side surface21aand the side surface22aexist with a bias toward one side of one selected from the edge e1and the edge e2, the clogging, damage, etc., of the blade when dicing can be suppressed by increasing the replacement frequency of the blade, etc.

The substrate5is already removed when dicing. Further, the damage to the semiconductor layer15when dicing can be avoided because the semiconductor layer15does not exist in the dicing regions d1and d2. After the singulation, a structure is obtained in which the end portion (the side surface) of the semiconductor layer15is protected by being covered with the resin.

The singulated light emitting device10amay have a single-chip structure including one semiconductor layer15or a multi-chip structure including multiple semiconductor layers15.

Because each of the processes described above until the dicing can be performed collectively in the wafer state, it is unnecessary to perform the interconnects and the packaging for every singulated individual device; and it becomes possible to drastically reduce the production costs. In other words, the interconnects and the packaging are already complete in the singulated state. Therefore, the productivity can be increased; and as a result, price reductions become easy.

As in the light emitting device10billustrated inFIG. 17A, a structure may be used in which the lens is not provided on the first surface15aside.

As in the light emitting device10cillustrated inFIG. 17B, the substrate5may thinly remain on the first surface15a. For example, the substrate5can be polished using a grinder for polishing a semiconductor wafer back surface, etc.

The substrate5is, for example, a sapphire substrate and is transmissive with respect to the light emitted from the nitride semiconductor-based light emitting layer. Because there is no phosphor layer in such a case, light having the same wavelength as the light emitted from the light emitting layer is emitted to the outside from the light emitting device10c. Of course, the phosphor layer may be formed on the substrate5. By leaving the substrate5, the mechanical strength can be increased; and a structure having high reliability may be provided.

When dicing, the substrate5can be subdivided using laser irradiation after performing a half-cut using the dicing blade from the resin layer25side. Alternatively, all of the portions may be cut using laser irradiation.

Second Embodiment

FIG. 18Ais a schematic perspective view as viewed from the third surface30side of a light emitting device10dof a second embodiment.

FIG. 18Bis a schematic perspective view as viewed from the light emitting surface side of the light emitting device10d.

The light emitting device10dof this embodiment differs from the light emitting device10aof the first embodiment by including a reflective film51.

The reflective film51is reflective with respect to the light emitted from the light emitting layer and emitted by the phosphor and is, for example, a metal film. The reflective film51is formed on the side surface of the phosphor layer27and the side surface of the insulating layer18. The reflective film51is not formed on the surface of the phosphor layer27on the side opposite to the first surface15a.

FIG. 20is a schematic cross-sectional view of a light emitting module having a configuration in which the light emitting device10dof this embodiment is mounted on the mounting substrate100.

Similarly to the first embodiment, the light emitting device10dis mounted with an orientation in which the third surface30faces the mounting surface103of the mounting substrate100. The p-side external terminal23aand the n-side external terminal24aexposed at the third surface30are bonded respectively to the pads101formed in the mounting surface103via the solder102, etc.

The third surface30is substantially perpendicular to the first surface15awhich is the main emitting surface of the light. Accordingly, the first surface15ais configured to face the lateral direction instead of upward from the mounting surface103when the third surface30faces downward toward the mounting surface103side. In other words, a so-called side-view type light emitting device10dand light emitting module are obtained in which the light is emitted in the lateral direction in the case where the mounting surface103is taken to be a horizontal surface.

Because the side surfaces of the insulating layer18and the phosphor layer27are covered with the reflective film51, the light is emitted by being concentrated in the lateral direction.

A method for manufacturing the light emitting device10dof this embodiment will now be described with reference toFIG. 21AtoFIG. 23B.

FIG. 21Aillustrates the state in which the substrate5is removed and the phosphor layer27is formed on the first surface15a. Up to this process, the processes may progress similarly to the first embodiment described above.

Then, half-cut dicing is performed on the stacked body illustrated inFIG. 21Afrom the phosphor layer27side. Specifically, the phosphor layer27and the insulating layer18are cut at the positions of the dicing regions d1and d2. For example, the cutting is performed using a dicing blade or laser irradiation. Thereby, a trench52(FIG. 21B) is made in the dicing regions d1and d2.

Continuing, the reflective film51is formed on the exposed surface using, for example, sputtering. As illustrated inFIG. 22A, the reflective film51is formed on the top surface of the phosphor layer27and on the bottom and the inner wall of the trench52.

For example, silver, aluminum, gold, silicon, a dielectric multilayered film, etc., may be used as the reflective film51. Alternatively, a resin including a reflective powder may be used as the reflective film51.

Then, as illustrated inFIG. 22B, the reflective film51formed in the top surface of the phosphor layer27is removed by polishing. For example, a grinder, etc., for polishing a semiconductor wafer back surface may be used. Alternatively, the reflective film51formed on the top surface of the phosphor layer27may be removed using RIE. The reflective film51remains on the side surface of the phosphor layer27and the side surface of the insulating layer18.

Continuing as illustrated inFIG. 23AandFIG. 23Bwhich is the bottom view thereof, the resin layer25under the trench52is cut. For example, the cutting is performed using a dicing blade. Alternatively, the cutting may be performed using laser irradiation. Thereby, singulation into the multiple light emitting devices10dis performed.

At this time as well, similarly to the first embodiment, the portions of the second p-side interconnect layer23and the second n-side interconnect layer24that jut into the dicing region d2extending in the direction along the third surface30are cut. Thereby, the p-side external terminal23aand the n-side external terminal24aare exposed at the third surface30.

In this embodiment as well, the dicing can be easy and the productivity can be increased because the resin is cut. Because the semiconductor layer15is not cut, damage to the semiconductor layer15when dicing can be avoided.

Third Embodiment

In the light emitting device10eof this embodiment, a portion of the second p-side interconnect layer23is provided inside the first via18awithout providing the first p-side interconnect layer21of the embodiment recited above. Also, a portion of the second n-side interconnect layer24is provided inside the second via18bwithout providing the first n-side interconnect layer22. In other words, the p-side interconnect layer includes the second p-side interconnect layer23; and the n-side interconnect layer includes the second n-side interconnect layer24.

Processes can be eliminated and costs can be reduced by the first p-side interconnect layer21and the first n-side interconnect layer22not being provided.

FIG. 25is a schematic cross-sectional view of a light emitting module having a configuration in which the light emitting device10eof this embodiment is mounted on the mounting substrate100.

In this embodiment as well, the light emitting device10eis mounted with an orientation in which the third surface30faces the mounting surface103of the mounting substrate100. The p-side external terminal23aand the n-side external terminal24aexposed at the third surface30are bonded respectively to the pads101formed in the mounting surface103via the solder102, etc.

The third surface30is substantially perpendicular to the first surface15awhich is the main emitting surface of the light. Accordingly, the first surface15ais configured to face the lateral direction instead of upward from the mounting surface103when the third surface30faces downward toward the mounting surface103side. In other words, a so-called side-view type light emitting device10eand light emitting module are obtained in which light is emitted in the lateral direction in the case where the mounting surface103is taken to be a horizontal surface.

Fourth Embodiment

The third surface30of the light emitting device10fof this embodiment is neither perpendicular nor parallel to the first surface15abut is tilted with respect to the first surface15a.

The third surface30is tilted such that the exterior form of the resin layer25has an inverted trapezoidal configuration in the cross section ofFIG. 26Ccorresponding to the B-B cross section ofFIG. 26A.

The p-side external terminal23aof the second p-side interconnect layer23, the n-side external terminal24aof the second n-side interconnect layer24, the side surface21aof the first p-side interconnect layer21, and the side surface22aof the first n-side interconnect layer22exposed at the third surface30are tilted to conform to the tilt of the third surface30.

FIG. 27is a schematic cross-sectional view of a light emitting module having a configuration in which the light emitting device10fof this embodiment is mounted on the mounting substrate100.

The light emitting device10fis mounted with an orientation in which the third surface30faces the mounting surface103of the mounting substrate100. The p-side external terminal23aand the n-side external terminal24aexposed at the third surface30are bonded respectively to the pads101formed in the mounting surface103via the solder102, etc.

In this embodiment as well, the p-side external terminal23aand the n-side external terminal24aare exposed at the third surface30of the plane orientation different from the first surface15aand the second surface on the side opposite to the first surface15a. Therefore, a side-view type light emitting device10fand light emitting module are obtained in which light is emitted in the lateral direction in the state in which the mounting surface faces downward.

Also, the first surface15afaces obliquely upward when the third surface30faces downward toward the mounting surface103side because the third surface30is tilted with respect to the first surface15a. In other words, the light is emitted obliquely upward in the case where the mounting surface103is taken to be a horizontal surface.

A method for manufacturing the light emitting device10fof this embodiment will now be described with reference toFIG. 28AtoFIG. 29B.

As illustrated inFIG. 28A, the processes may progress similarly to the first embodiment up to the process of forming the phosphor layer27.

Then, the resin layer25is cut at the position of the dicing region d2illustrated inFIG. 12Bdescribed above using a blade of which, for example, both width-direction side surfaces are formed with tapers. Thereby, as illustrated inFIG. 28B, a trench55is made under the dicing region d2. The trench55reaches the insulating layer18by piercing the resin layer25. The trench55widens gradually away from the insulating layer18side.

In this embodiment as well, the p-side external terminal23aand the n-side external terminal24ajut into the dicing region d2. Accordingly, the p-side external terminal23aand the n-side external terminal24aare exposed at the trench55.

Then, the insulating layer18and the phosphor layer27on the trench55are cut along the dicing region d2. Further, the phosphor layer27, the insulating layer18, and the resin layer25are cut along the dicing region d1orthogonal to the dicing region d2. Thereby, as illustrated inFIGS. 29A and 29B, singulation into the multiple light emitting devices10fis performed.

In the direction along the dicing region d1as well, the side surface of the resin layer25illustrated inFIG. 29Amay be tilted by dicing using a blade of which both width-direction side surfaces are formed with tapers.

FIG. 30Bis a schematic view of a specific example in which the light emitting module of the embodiment is used as, for example, a backlight of a liquid crystal display apparatus.

Here, a light emitting device10mounted on the mounting substrate100is illustrated as one typical light emitting device selected from the embodiments described above.

The mounting substrate100is provided on a frame151. Because the light emitting device10is the side-view type, the light is emitted in the lateral direction as illustrated by the white arrow of the drawing in the state in which the mounting substrate100faces downward.

The mounting substrate100is formed, for example, in a rectangular plate configuration extending into the page surface; and the multiple light emitting devices10are mounted in the longitudinal direction of the mounting substrate100.

A light guide plate201is provided beside the light emitting module. The light guide plate201is transmissive with respect to the light emitted from the light emitting device10and is made of, for example, a resin material. The light emitting surface of the light emitting device10opposes a light incident surface201aof the light guide plate201.

A reflector153is provided below the light guide plate201; and a liquid crystal panel202is provided above the light guide plate201. A reflector154is provided above the light emitting device10. The reflectors153and154are reflective with respect to the light emitted from the light emitting device10.

The light emitted in the lateral direction from the light emitting device10is incident on the light incident surface201aof the light guide plate201. The light entering the light guide plate201from the light incident surface201aspreads in the surface direction of the light guide plate201and is incident on the liquid crystal panel202. The light emitted from the light guide plate201on the side opposite to the liquid crystal panel202is guided into the liquid crystal panel202by being reflected by the reflector153.

FIG. 30Ais a schematic view of a backlight using a light emitting module of a comparative example as the light source.

The light emitting device300of the light emitting module of this comparative example is a so-called top-view type. In other words, the light is emitted upward from the mounting surface of the mounting substrate100. Accordingly, the mounting substrate100is supported by a frame152provided to oppose the light incident surface201ato cause the light emitting surface of the light emitting device300to oppose the light incident surface201aof the light guide plate201.

Therefore, the mounting substrate100having the rectangular plate configuration is disposed upright with an orientation in which the mounting surface faces the light incident surface201a; and this may lead to an increase of not only the thickness of the light guide plate201but also the thickness of the entire backlight unit.

Conversely, in the embodiment illustrated inFIG. 30B, not only the light guide plate201but also the entire backlight unit can be thinner because it is unnecessary for the mounting substrate100to be upright to face the light incident surface201aof the light guide plate201.

The red phosphor layer, the yellow phosphor layer, the green phosphor layer, and the blue phosphor layer described below can be used as the phosphor layer described above.

The red phosphor layer can contain, for example, a nitride-based phosphor of CaAlSiN3:Eu or a SiAlON-based phosphor.

In the case where a SiAlON-based phosphor is used,
(M1-x,Rx)a1AlSib1Oc1Nd1Compositional Formula (1)
can be used (where M is at least one type of metal element excluding Si and Al, and it is notable for M to be at least one selected from Ca and Sr; R is a light emission center element, and it is notable for R to be Eu; and x, a1, b1, c1, and d1 satisfy the following relationships: x is larger than 0 and 1 or less, a1 is larger than 0.6 and less than 0.95, b1 is larger than 2 and less than 3.9, c1 is larger than 0.25 and less than 0.45, and d1 is larger than 4 and less than 5.7).

By using the SiAlON-based phosphor of Compositional Formula (1), the temperature characteristics of the wavelength conversion efficiency can be improved; and the efficiency in the high current density region can be increased further.

The yellow phosphor layer can contain, for example, a silicate-based phosphor of (Sr, Ca, Ba)2SiO4:Eu.

The green phosphor layer can contain, for example, a halophosphate-based phosphor of (Ba, Ca, Mg)10(PO4)6Cl2:Eu or a SiAlON-based phosphor.

In the case where a SiAlON-based phosphor is used,
(M1-x,Rx)a2AlSib2Oc2Nd2Compositional Formula (2)
can be used (where M is at least one type of metal element excluding Si and Al, and it is notable for M to be at least one selected from Ca and Sr; R is a light emission center element, and it is notable for R to be Eu; and x, a2, b2, c2, and d2 satisfy the following relationships: x is larger than 0 and 1 or less, a2 is larger than 0.93 and less than 1.3, b2 is larger than 4.0 and less than 5.8, c2 is larger than 0.6 and less than 1, and d2 is larger than 6 and less than 11).

By using the SiAlON-based phosphor of Compositional Formula (2), the temperature characteristics of the wavelength conversion efficiency can be improved; and the efficiency in the high current density region can be increased further.

The blue phosphor layer can contain, for example, an oxide-based phosphor of BaMgAl10O17:Eu.