Semiconductor device and manufacturing method of the same

One aspect of the present invention is a semiconductor device including: a semiconductor substrate; a first wiring that is formed on the semiconductor substrate; a second wiring that is formed to cross over the first wiring with a space interposed therebetween at a cross portion in which the first wiring and the second wiring cross each other; a protective film that is formed on the semiconductor substrate to cover at least a part of the first wiring, the part being located under the second wiring in the cross portion; and an insulator film that is formed in an island shape on the protective film under the second wiring in the cross portion to be located between edges of the protective film and to cover the first wiring in the cross portion.

INCORPORATION BY REFERENCE

This application is based upon and claims the benefit of priority from Japanese patent application No. 2009-106207, filed on Apr. 24, 2009, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

1. Field of the Invention

The present invention relates to a semiconductor device, especially to a semiconductor device having a cross-wiring portion in which wirings cross each other.

2. Description of Related Art

When a transistor and an integrated circuit including the transistor operate in a frequency band higher than 10 GHz, it is necessary to reduce a parasitic capacitance around a gate electrode as much as possible in order to ensure a desired performance such as a characteristic or gain in the transistor.

In the transistor used in the high frequency band as described above, especially a transistor using a compound semiconductor device such as GaAs, an oxide film and a nitride film are formed as protective films to stabilize the operation of the transistor. However, the protective films such as the oxide film and the nitride film are required to have a thickness equal to or less than 0.2 um to reduce the parasitic capacitance, and an interlayer film is generally not applied. In the transistor and the integrated circuit as describe above, a technique is widely used in which a cross-wiring portion is not supported by the interlayer film and wirings are separated with an air interposed therebetween. This structure is called an air-bridge structure.

The air-bridge structure has a problem in that an upper layered wiring is deformed due to a thermal stress, mechanical vibration between the wiring layers, and an external force applied to the wiring structure during manufacturing processes, thereby contacting with a lover layered wiring. Japanese Unexamined Patent Application Publication Nos. 11-186381 and 10-12722 disclose a semiconductor device having a structure which prevents the wirings from contacting with each other due to deformation of an upper layered wiring.

FIG. 9is a diagram showing a configuration of the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 11-186381. In the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 11-186381, a lower layered wiring71extending in the longitudinal direction of the drawing sheet is formed on a semiconductor substrate70. An upper layered wiring74crossing the lower layered wiring71is formed to straddle the lower layered wiring71with a space73interposed therebetween. Further, a supporting column72of an insulator film is formed on the lower layered wiring71to prevent a short from occurring due to a contact between the upper layered wiring74and the lower layered wiring71.

However, in the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 11-186381, the supporting column72partially supports the upper and lower layered wirings but it is insufficient to prevent a short from occurring. Specifically, a wafer surface comes into contact with the supporting column72in a polishing process for a rear surface and a pelletizing process executed after the air-bridge structure is formed. When an external force is applied to the semiconductor device in the above processes, the upper layered wiring74positioned in an area where the supporting column72is not formed is pressed, thereby occasionally causing a short due to the contact between the upper layered wiring74and the lower layered wiring71.

Further, even if the short does not occur, a capacitance between the wirings becomes larger, thereby causing a phase of the transistor to deviate from the designed phase when the distance between the wirings is reduced to around 0.1 um. Therefore, a phase matching condition in the design stage cannot be satisfied. Further, because an amount of deformation of the upper layered wiring caused by the above factors varies to a large extent, an amount of change of the phase also varies to a large extent. As a result, a desired performance cannot be obtained and the yield of a product decreases.

On the other hand, as shown inFIG. 10Japanese Unexamined Patent Application Publication No. 10-12722 discloses a technique in which an insulator film75with a large thickness is formed on the lower layered wiring71to ensure a distance between the wirings, and an insulator film76with a small thickness is formed on the lower layered wiring71and the semiconductor substrate70to prevent the short from occurring due to the contact between the upper layered wiring74and the lower layered wiring71.

SUMMARY

The present inventor has found the following problem. In the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 10-12722, when the insulator film75formed on the lower layered wiring71is made by a patterning process in which the insulator film75is etched with the same profile as the lower layered wiring71after a depositing process in which insulating material is deposited by CVD (Chemical Vapor Deposition), for example, the lower layered wiring71is damaged during etching. Therefore, there is a problem that a desired performance cannot be obtained.

A first exemplary aspect of the present invention is a semiconductor device including: a semiconductor substrate; a first wiring that is formed on the semiconductor substrate; a second wiring that is formed to cross the first wiring with a space interposed therebetween at a cross portion in which the first wiring and the second wiring cross each other; a protective film that is formed on the semiconductor substrate to cover at least a part of the first wiring, the part being located under the second wiring in the cross portion; and an insulator film that is formed in an island shape on the protective film under the second wiring in the cross portion to be located between edges of the protective film and to cover the first wiring in the cross portion.

As described above, in the semiconductor device including the air-bridge structure, the insulator film having an island shape is formed on the protective film under the second wiring to be located between edges of the protective film and to cover the first wiring in the cross portion. Therefore, the protective film protects the first wiring of the lower layer under the insulator film and prevents the first wiring from being damaged at the time of forming the insulator film.

A second exemplary aspect of the present invention is a manufacturing method of a semiconductor device, including: forming a first wiring on a semiconductor substrate; forming a second wiring to cross the first wiring with a space interposed therebetween at a cross portion in which the first wiring and the second wiring cross each other; forming a protective film on the semiconductor substrate to cover at least a part of the first wiring, the part being located under the second wiring in the cross portion; and forming an insulator film in an island shape on the protective film under the second wiring in the cross portion to be located between edges of the protective film and to cover the first wiring in the cross portion.

As described above, in the semiconductor device including the air-bridge structure, the insulator film having an island shape is formed on the protective film under the second wiring to be located between edges of the protective film and to cover the first wiring in the cross portion. Therefore, the protect film protects the first wiring of the lower layer under the insulator film and prevents the first wiring from being damaged at the time of forming the insulator film.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Hereinafter, referring to attached drawings, a semiconductor device and a manufacturing process of the same according to preferable embodiments of the present invention will described.

First Exemplary Embodiment

FIG. 1is a plan view showing a portion of a semiconductor device according to a first exemplary embodiment of the present invention, andFIG. 2is a cross sectional view taken along line II-II inFIG. 1. In the first exemplary embodiment, a gate electrode is configured as a first wiring of a lower layered wiring and a source electrode is configured as a second wiring of an upper layered wiring. Hereinafter, referring toFIGS. 1 and 2, a configuration of the semiconductor device according to the first exemplary embodiment will be described.

As shown inFIG. 1, the semiconductor device includes a gate electrode pad7, a drain electrode pad10, and source electrodes6. The drain electrode pad10is connected to a drain electrode4. The drain electrode4is formed to extend in longitudinal direction of the drawing sheet. The source electrodes6are located to sandwich the drain electrode4. Both sides of the source electrodes6are connected to each other by a second wiring2and are supplied with the same voltage. The insulator film3is formed in an island shape on the protective film under the second wiring2in the cross portion to be located between edges of the protective film and to cover the first wiring in the cross portion.

The gate electrode pad7is connected to gate electrodes5with a first wiring1interposed therebetween. The first wiring1is formed to extend in the longitudinal direction of the drawing sheet. One of the gate electrode5is formed between the source electrode6located on the left side inFIG. 1and the drain electrode4, and the other of the gate electrode5is formed between the source electrode6located on the right side and the drain electrode4. The gate electrodes5are located to sandwich the drain electrode4and are supplied with the same voltage through the first wiring1.

The first wiring1extending in the longitudinal direction of the drawing sheet and the second wiring2extending in the horizontal direction of the drawing sheet cross each other at a cross portion. The second wiring2is formed at the cross portion to straddle the first wiring1with a predetermined space interposed therebetween. That is, the semiconductor device according to this exemplary embodiment has an air-bridge structure in which the wirings cross each other with a space interposed therebetween. Hereinafter, an area where the first wiring1and the second wiring2cross each other in the plane view is called “a cross portion”. In the cross portion, an insulator film3having an island shape is formed between the first wiring1and the second wiring2in order to cover the first wiring1. The insulator film3is formed on an upper surface and side surfaces of the first wiring1with an approximately uniform thickness.

Using a sectional view shown inFIG. 2, the present exemplary embodiment will be explained. As described above, in the cross portion with the first wiring1formed on a semiconductor substrate11, the second wiring2is formed to straddle the first wiring1with a space9interposed therebetween.

Under the second wiring2in the cross portion, that is, inside of the cross portion, a protective film8is formed on the semiconductor substrate11to cover at least a part of the first wiring1. An illustration of the protective film8is omitted inFIG. 1. The protective film8is formed to protect the semiconductor element such as a transistor or the like which is formed on the semiconductor substrate11. The protective film8may be made of a SiN film. It is preferred that a thickness of the protective film8be equal to or less than 0.2 um to decrease a capacitance value of a parasitic capacitor made up of the first wiring1, the protective film8, and the second wiring2. For example, the thickness of the protective film8is designed to be 0.1 um.

On the protective film8under the second wiring2in the cross portion, the insulator film3having an island shape is formed by patterning to be located between edges of the protective film8and to cover the first wiring1in the cross portion. That is, the protective film8, the insulator film3and the space9are located between the first wiring1and the second wiring2.

It is preferred that a distance d between the first wiring and the second wiring2be equal to or more than 0.1 um to ensure a sufficient space. In this explanation, it is assumed that the distance d between the wirings is equal to or more than 0.2 um, which is equivalent to the thickness of the insulator film3, to ensure a predetermined space. However, the distance d between the wirings is not limited thereto, and can be designed to be any distance according the thickness of the insulator film3.

The insulator film3is made of a low dielectric film. It is preferred that a relative permittivity ∈r of the insulator film3be equal to or less than 3.5 to decrease a capacitance value of a parasitic capacitor made up of the first wiring1, the insulator film3, and the second wiring2. It is preferred that the thickness of the insulator film3be formed to be thicker than the thickness of the protective film8. It is preferred that the thickness of the insulator film3be equal to or more than 0.5 um to sufficiently ensure the distance between the wirings and to decrease a capacitance between wirings. For example, the thickness of the insulator film3is designed to be less than 0.2 um.

The insulator film3covers the first wiring1and extends outwardly about several um from an edge of the cross portion, and is not applied to a transistor portion15. This configuration is employed to prevent a false operation of the transistor from being caused by the parasitic capacitance or the like made up of the first wiring1, the insulator film3, and the second wiring2. It is preferred that the insulator film3be formed of spin-coating material formed by spin-coating process or a printed material formed by a printing process. For example, the insulator film3may be made of benzocyclobutene (BCB) having relative permittivity ∈r=2.7. Note, the insulator film3does not necessarily have a photosensitivity.

Next, a manufacturing method of the semiconductor device configured as described above will be described.FIGS. 3A,3B,4A, and4B are diagrams showing the manufacturing process of the semiconductor device according to the first exemplary embodiment of the present invention. As shown inFIG. 3A, after the source electrode6, the drain electrode4, the gate electrode5, and the first wiring1of the transistor (not shown) formed on the semiconductor substrate11are formed, the protective film8of the transistor portion15is entirely applied.

As shown inFIG. 3B, after the BCB having photosensitivity is applied as a low dielectric film, and the insulator film3is formed above the first wiring1in the cross portion by an exposure process, a development process, and a cure process so that the insulator film3has a thickness of 2.0 um. At this time, a patterning process is performed so that the insulator film3entirely covers the first wiring1in the cross portion and extends outwardly around several um from the first wiring1. In the other words, the insulator film3is formed in an island shape on the protective film8in the cross portion by the patterning process so that the insulator film3is located inside of the edges of the protective film8and covers the first wiring1in the cross portion.

As shown inFIG. 4A, a resist12having a thickness of 2.5 um thickness is applied to protect the insulator film3. The resist12is patterned into a desired profile by an exposure process and a development process. Next, a general manufacturing process of the air-bridge structure including a forming process of a voltage supply layer, a plate process, a milling process, and a removing process of the resist12are performed, thereby forming the cross portion including the second wiring2(SeeFIG. 4B).

Next, advantages of the semiconductor device according to the first exemplary embodiment of the present invention will be described. In the first exemplary embodiment, even if the second wiring2receives a mechanical external force in the case of forming the second wiring2or the like in the manufacturing process, the second wiring2is supported by the insulator film3located just under the second wiring2. Therefore, it is ensured that the distance between the first wiring1and the second wiring2is not equal to or less than a minimum distance equivalent to the thickness of the insulator film3. In the other words, it is ensured that a capacitance value of the parasitic capacitor made up of the first wiring1, the insulator film3, and the second wiring2is not equal to or more than a predetermined capacitance value. Because the insulator film3is formed on the upper surface and side surfaces of the first wiring1with a uniform thickness, the predetermined distance between the wirings can be ensured not only at the upper surface of the first wiring1but also at the side surfaces of the first wiring1.

Here, the capacitance value between the wirings depends on the distance d between the electrodes. That is, when the second wiring2receives the external force, the capacitance value between the wirings depends on the thickness of the insulator film3. However, when the thickness of the insulator film3is designed to be equal to or more than 0.5 um, the capacitance value can be sufficiently reduced. It is more preferred that the thickness of the insulator film3be equal to or more than 2.0 um to reduce the capacitance value to be equal to or less than 10 fF.

In the related art, one of factors causing deformation of the upper layered wiring is that the mechanical external force is applied during the manufacturing process under the condition that a wafer surface is in contact with a supporting member or the like. Therefore, in the related art, a deformation amount of the second wiring2varies to a large extent depending on a value of an external force applied during the manufacturing process. Because the capacitance value between the wirings is approximately in inverse proportion to the distance d between the wirings, the variation in the deformation amount of the second wiring2causes a variation in the capacitance between the wirings.

As a result, when the gate electrode and the source electrode cross each other as shown in the first exemplary embodiment, a variation occurs in a capacitance Cgs between the gate electrode and the source electrode, thereby causing a variation in a phase S11of the transistor. On the other hand, when the drain electrode and the source electrode cross each other, a variation occurs in a capacitance Cds between the drain electrode and the source electrode, thereby causing a variation in a phase S22of the transistor.

FIG. 5shows a dependency characteristic of the capacitance between the wirings on the distance between the wirings. The distance d between the wirings is generally designed to be around 2 um. However, the distance d between the wirings may be around 0.1 um due to variation in manufacturing process. As a result, the capacitance value between the wirings increases by around 100 fF. This is equivalent to an increase of 30 angular degrees which is an amount of change in the phase S11of the transistor at f=30 GHz. This is a main factor of the variation in the phase S11of the transistor.

On the other hand, in this present exemplary embodiment, because the insulator film3is formed between the wirings, the capacitance between the wirings becomes larger. However, because the relative permittivity ∈r of the insulator film3is designed to be less than 3.0 and the thickness of the insulator film3is designed to be equal to or more than 1 um as shown inFIG. 6, an increase of the capacitance value can be reduced to be equal to or less than 20 fF. Further, if the thickness of the insulator film3is designed to be equal to or more than 2.0 um, the increase of the capacitance value can be reduced to be equal to or less than 10 fF. Furthermore, the relative permittivity ∈r of the insulator film3is designed to be equal to or less than 3.5, the capacitance value can be sufficiently reduced.

In the first exemplary embodiment, because the second wiring2is supported by the insulator film3, the distance between the first wiring1and the second wiring2and the capacitance value between the wirings are constant. That is, as a result of that, the phases S11and S22of the transistor are also constant. Therefore, in the semiconductor device according to the first exemplary embodiment, because the distance between the wirings is ensured, the factor of the variation can be eliminated and the variations in the phases S11and S12can be substantially reduced.

FIG. 7Ashows a distribution of the phase S11of the transistor at f=30 GHz in the first exemplary embodiment andFIG. 7Bshows that of the transistor in the related art. The increase of the capacitance value of the wiring portion appears not as an increase in the capacitance of the transistor portion15but as an increase in the capacitance in an external area of the transistor portion15. That is, the increase of the capacitance value causes only a change in parameters of a matching circuit necessary for impedance matching but does not causes any deterioration in characteristics of an amplifier.

Further, in the semiconductor device according to the exemplary embodiment, because the insulator film3is formed in an inner side of the protective film8under the second wiring2in the cross portion, the first wiring1can be protected by the protective film3when the insulator film3is patterned along the outline of the first wiring1. This prevents the first wiring1from being damaged and improves the yield ratio of the product.

Further, in the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 10-12722, the insulator film is formed of SiO2or Si3N4. Here, SiO2and Si3N4are generally deposited with a predetermined thickness over the wafer by CVD and the insulator film having the same thickness is formed on the transistor portion15. Therefore, when the insulator film on the transistor portion15is removed so that the insulator film is left only on the first wiring of the lower layered wiring, dry etching or the like is used for removing the insulator film, thereby damaging the transistor portion15.

On the other hand, in the semiconductor device according to the present first exemplary embodiment, because the insulator film3is formed of the insulating material which has a photosensitivity and is formed by spin-coating process, no etching process is required at the time of patterning process of the insulator film3, thereby preventing the transistor portion15from being damaged. Therefore, the yield ratio of the product can be improved.

In the first exemplary embodiment, a positional relationship between the source electrode and the gate electrode in the cross portion can be reversed. That is, a configuration may be applied in which the source electrode is designed as the lower layered wiring and the gate electrode is designed as the upper layered wiring.

Second Exemplary Embodiment

Referring next toFIG. 8, a semiconductor device according to as a second exemplary embodiment of the present invention will be described.FIG. 8is a plan view showing a configuration around the transistor portion15of the semiconductor device according to the second exemplary embodiment of the present invention. In the second exemplary embodiment, the drain electrode is formed as a first wiring21of a lower layered wiring and the source electrode is formed as a second wiring22of the upper layered wiring.

In an inside of a cross portion in which the first wiring21and the second wiring22cross each other, the first wiring21is covered by the protective film8(for example, which is made of a SiN film) of the transistor portion15. The first wiring21is also covered by the insulator film3. For example, the insulator film3may be formed of a BCB film serving as a the low dielectric film having the relative permittivity ∈r of approximately 2.7.

For example, a thickness of the insulator film3is designed to be 2.0 um. The insulator film3covers the first wiring21and extends outwardly about several um from the cross portion, and is not applied to the transistor portion15.

A manufacturing method and advantages of the second exemplary embodiment are almost the same as the first exemplary embodiment and an explanation thereof is omitted. Further, a configuration may be applied to the second exemplary embodiment in which the source electrode is formed of the first wiring which is the lower layered wiring and the drain electrode is formed of the second wiring which is the upper layered wiring.

The first and second exemplary embodiments can be combined as desirable by one of ordinary skill in the art.

While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above.