Display panel and manufacturing method thereof

A display panel includes a substrate, a plurality of thin film transistors (TFTs), a plurality common electrodes, a plurality of common electrode lines, a plurality of coupling electrodes, and a plurality of pixel electrodes. Each of the TFTs comprises a gate, a source, a drain and a channel layer coupling the source to the drain. The gate, the common electrodes, and the common electrode lines are formed on a surface of the substrate and are separated from each other. Each of the coupling electrodes couples a corresponding common electrode to a corresponding common electrode line, and a space is defined between the corresponding common electrode and the corresponding common electrode line.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. 201410434066.1 filed on Aug. 29, 2014, the contents of which are incorporated by reference herein.

FIELD

The subject matter herein generally relates to a display panel a method for manufacturing the display panel.

BACKGROUND

In-plane switching (IPS) mode liquid crystal display (LCD) panels are becoming more and more popular because they can present a wider viewing angle to a viewer than twisted nematic (TN) mode LCD panels. Generally, in a method for manufacturing the IPS mode LCD panel, a plurality of photomask may be used in different photo etching processes (PEPs) to form different circuit patterns of the IPS mode LCD panel.

DETAILED DESCRIPTION

The present disclosure is described in relation to a display panel and a method for manufacturing the same.

Referring toFIG. 1andFIG. 2,FIG. 1illustrates a partial plan view of a display panel1,FIG. 2is a cross-sectional view taken along line II-II ofFIG. 1. In at least one embodiment, the display panel1can include a substrate11, a plurality of gate lines10, a plurality of data lines12, a plurality of thin film transistors (TFTs)13, a plurality of common electrodes14, a plurality of common electrode lines15, a plurality of coupling electrodes16, and a plurality of pixel electrodes17. The display panel1can be composed of a display area AA and a border area BB (also called non-display area or non-active area) surrounding the display area AA.

The gate lines10and the data lines12are intersected with each other to define a plurality of pixel units40within the display area AA. At least one of the common electrode line15is located in each of the pixel units40. In at least one embodiment, the gate lines10are arranged in parallel, the data lines12are arrange in parallel as well as the gate lines10, and the common electrode lines15are also arranged in parallel. The common electrode lines15can be in parallel with the data lines12. The gate lines10can extend along a first direction while the data lines12can extend along a second direction perpendicular with the first direction. Thus, the pixel unit40is rectangular. Each pixel electrode17is located within a corresponding pixel unit40and is electrically coupled to corresponding TFT13. The pixel electrode17can be made of transparent materials, such as indium tin oxide (ITO).

The common electrode14can be located in the display area AA of the display panel1. The common electrode14is coupled to the at least one common electrode line15within a corresponding pixel unit40via a corresponding electrode16, but the common electrode14is not contacted with the at least one common electrode line15within the corresponding pixel unit40. In this embodiment, since short circuit issues may happen in the border area BB if the common electrode lines15extend to the border area BB, the common electrode lines15are located within the display area AA.

Each of the TFTs13is located in a corresponding pixel unit40and is coupled to a corresponding gate line10and a corresponding data line12. Each TFT13can include a gate130, a gate insulation layer132, a source134, a drain136, a channel layer137and a flat layer138. The channel layer137is coupled between the source134and the drain136. In at least one embodiment, the TFTs13can be bottom-gate TFTs.

The gate130is formed on the substrate11and is coupled with a corresponding data line10. The common electrodes14and the common electrodes lines15both are formed on the substrate11as well as the gate130. The gate130, the common electrodes14, and the common electrode lines15are separated from each other to avoid electrical connections therebetween. The gate insulation layer132is coated on the substrate11and covers the gate130of each TFT13, the common electrodes14, and the common electrode1lines15.

The channel layer137is located on the gate insulation layer132and corresponds with the gate130. The source134and the drain135are formed on the gate insulation layer132and are respectively coupled at opposite sides of the channel layer137. The source134is coupled to a corresponding data line12.

The flat layer138is coated on the gate insulation layer132and covers the channel layer137, the source134and the drain136. The flat layer138defines a plurality of first contact holes1380and a plurality of second contact holes1382respectively corresponding with the drain136of each of the TFTs13and the common electrode lines15. The pixel electrode17is coupled to the drain136via the first contact hole1380. The coupling electrode16is coupled between a corresponding common electrode14and a corresponding common electrode line15via the second contact hole1382. In this embodiment, as shown inFIG. 3, a space S is defined between the corresponding common electrode14and the corresponding common electrode line15, thereby separating the corresponding common electrode14from the corresponding common electrode line15.

Each pixel electrode17defines a plurality of slits170to corporate with the common electrode14within a corresponding pixel unit40to form a parallel electrical field. Thus, the display panel1can be an in-plane switching (IPS) mode liquid crystal display (LCD) panel.

FIG. 4illustrates a flowchart of a method for manufacturing the display panel1ofFIG. 1andFIG. 2. The method is provided by way of example, as there are a variety of ways to carry out the method. Each block shown inFIG. 4represents one or more processes, methods, or subroutines which are carried out in the example method. Furthermore, the order of blocks is illustrative only and the order of the blocks can change. Additional blocks can be added or fewer blocks may be utilized without departing from the scope of this disclosure. The example method can begin at block301.

At block301, a substrate11is provided. The substrate can be a transparent substrate such as glass substrate or a plastic substrate. In other embodiments, the substrate11can be a translucent substrate, a non-transparent substrate or a flexible substrate.

At block302, as shown inFIG. 5, a metal layer22is formed on the substrate11and a first photoresist layer25is formed on the metal layer22

At block303, referring toFIG. 6andFIG. 7, the first photoresist layer25is patterned by an exposure and development process using a photomask23to form a plurality of photoresist patterns250on the metal layer22. The photomask23can be made of metal materials.

At block304, as shownFIG. 8, the metal layer22is etched to form a plurality of gates130and a plurality of common electrode lines15on the substrate11which are covered the photoresist patterns250. In this embodiment, only one gate130and one common electrode line15are shown inFIG. 8. Each gate130and each electrode line15are covered by the photoresist patterns250. In at least one embodiment, the metal layer22can be etched by an over etching process. Thus, an area of the gate130is less than an area of a corresponding photoresist pattern250which covers the gate130. For example, as shown inFIG. 8, a distance β is defined between an edge the gate130and a corresponding edge of the photoresist pattern250which covers the gate130. Accordingly, an area of the common electrode line15is less than that of a corresponding photoresist pattern250which covers the common electrode line15.

At block305, as shown inFIG. 9, a layer of conductive materials140is coated on the substrate11and the photoresist patterns250. In this embodiment, the layer of conductive materials140is coated on surfaces of the photoresist patterns250away from the substrate and is coated on a portion of a surface of the substrate11which is not covered by the photoresist patterns250. The conductive materials140can be transparent conductive materials, such as transparent conductive films made of indium tin oxide (ITO). The conductive materials140serve as common electrodes14of the display panel1. Since a distance β is defined between an edge of the gate130and a corresponding edge of the photoresist pattern250which covers the gate130, the conductive materials140will not contact with the gates130. Further, since the area of the common electrode line15is less than that of a corresponding photoresist pattern250covering the common electrode line15, the conductive materials140will not contact with the gates130.

At block306, as shown inFIG. 10, the photoresist patterns250and a portion of the conductive materials140on the photoresist pattern250are removed from the substrate11. Thus, the other portion of the conductive materials140maintained on the substrate11form the common electrodes14.

At block307, as shown inFIG. 11, a second photoresist layer35is formed on the substrate11and covers the gates130, the common electrodes14, and the common electrode lines15.

At block308, as shown inFIG. 12, a portion of the second photoresist layer35corresponding with the border area BB is removed. In at least one embodiment, an exposure process is first performed to expose the second photoresist layer35from a side of the substrate11away from the second photoresist layer35using an ultraviolet photomask26, and then a development process is utilized to remove the portion of the second photoresist layer35corresponding with the border area BB.

At block309, as shown inFIG. 13, a portion of the conductive materials140corresponding with the border area BB is removed by an etching process. Then, the other portion of the second photoresist layer35coated on the substrate11corresponding with the display area AA is removed to expose the common electrodes14in the display area AA.

At block310, a gate insulation layer132is formed on the substrate11to cover the gates130, the common electrodes14, and the common electrode lines15.

At block311, a plurality of channel layers137are formed on the gate insulation layer132corresponding with the gates130.

At block312, a plurality of sources134and drains136of the TFTs13are respectively formed on the gate insulation layer132. The source134and the drain136are respectively coupled at opposite sides of a corresponding channel layer137.

At block313, a flat layer138is formed on the gate insulation layer132to cover the channel layers137, the sources134, and the drains136.

At block314, a plurality of first contact holes1380corresponding with the drains136and a plurality of second contact holes1382corresponding with the common electrode lines15and the common electrodes14are formed on the flat layer138.

At block315, a plurality of pixel electrodes17and a plurality of coupling electrodes16are formed on the flat layer138. Each pixel electrode17is electrically coupled with a corresponding drain via a corresponding first contact hole1380. Each coupling electrode16is coupled with a corresponding common electrode14and a corresponding common electrode line15via a corresponding second contact hole1382, thereby making an electrical connection between the corresponding common electrode14and the corresponding common electrode line15.

As described above, the gates130and the common electrodes14can be formed in a same exposure process using the photomask22. Therefore, the cost for manufacturing the display panel1in the above mentioned method can be decreased compared with a traditional manufacturing method of the display panel1.