Semiconductor package having a plurality of chips and method of manufacturing the same

A semiconductor package includes a first interconnect substrate on a first redistribution substrate and having a first opening penetrating the first interconnect substrate. A first semiconductor chip is on the first redistribution substrate and the first opening of the first interconnect substrate. A second redistribution substrate is on the first interconnect substrate and the first semiconductor chip. A second interconnect substrate is on the second redistribution substrate and has a second opening penetrating the second interconnect substrate. A second semiconductor chip is on the second redistribution substrate and in the second opening of the second interconnect substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C § 119 of Korean Patent Application No. 10-2017-0070933, filed on Jun. 7, 2017, the entire contents of which are hereby incorporated by reference.

FIELD

One or more embodiments described herein relate to a semiconductor package and a method for manufacturing a semiconductor package.

BACKGROUND

A semiconductor package is provided to implement an integrated circuit chip for use in electronic products. In one type of semiconductor package, a semiconductor chip is mounted on a printed circuit board, and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board.

Attempts are continually being made to reduce the size, weight, and cost of manufacturing semiconductor packages. The sizes of semiconductor chips in the packages may be made smaller as integration increases. However, it may be difficult to adhere, handle, and/or test solder balls of a semiconductor chip of reduced size. Additionally, there are problems of acquiring a diversified mount board in accordance with the size of the semiconductor chip.

SUMMARY

In accordance with one or more embodiments, a semiconductor package includes a first redistribution substrate; a first interconnect substrate on the first redistribution substrate and having a first opening penetrating the first interconnect substrate; a first semiconductor chip on the first redistribution substrate and in the first opening of the first interconnect substrate; a second redistribution substrate on the first interconnect substrate and the first semiconductor chip; a second interconnect substrate on the second redistribution substrate and having a second opening penetrating the second interconnect substrate; and a second semiconductor chip on the second redistribution substrate and in the second opening of the second interconnect substrate.

In accordance with one or more other embodiments, a method for manufacturing a semiconductor package includes forming a first opening in and penetrating a first interconnect substrate; providing a first carrier substrate on a bottom surface of the first interconnect substrate; providing a first semiconductor chip in the first opening; removing the first carrier substrate to expose a bottom surface of the first semiconductor chip and the bottom surface of the first interconnect substrate; forming a first redistribution substrate on the bottom surface of the first semiconductor chip and the bottom surface of the first interconnect substrate; forming a second opening in a second interconnect substrate, the second opening penetrating the second interconnect substrate; providing a second carrier substrate on a bottom surface of the second interconnect substrate; providing a second semiconductor chip in the second opening; adhering the second interconnect substrate onto a bottom surface of the first redistribution substrate; removing the second carrier substrate to expose a bottom surface of the second semiconductor chip and the bottom surface of the second interconnect substrate; and forming a second redistribution substrate on the bottom surface of the second semiconductor chip and the bottom surface of the second interconnect substrate.

In accordance with one or more other embodiments, a semiconductor package, comprising: a first substrate; a first semiconductor chip on the first substrate; a first interconnect substrate on the first substrate and laterally spaced apart from the first semiconductor chip, the first semiconductor chip surrounded by the first interconnect substrate in a plan view; a second substrate electrically connected to the first interconnect substrate and covering the first interconnect substrate and the first semiconductor chip; a second semiconductor chip on the second substrate; and a second interconnect substrate on the second substrate and laterally spaced apart from the second semiconductor chip, the second semiconductor chip surrounded by the second interconnect substrate, in a plan view, wherein each of the first and second interconnect substrates comprises a base layer and a conductive member in the base layer.

DETAILED DESCRIPTION OF EMBODIMENTS

FIGS. 1, 2, and 3illustrate cross-sectional views of various embodiments of a semiconductor package. Referring toFIG. 1, a semiconductor package P100includes a first substrate100which, for example, may be a redistribution substrate. The first substrate100may include first insulating patterns110and first conductive patterns120. The first conductive patterns120may include one or more conductive layers between the first insulating patterns110and one or more vias penetrating the first insulating patterns110.

The first insulating patterns110may include an inorganic insulating layer such as silicon oxide or silicon nitride. In one embodiment, the first insulating patterns110may include a polymer material. The first conductive patterns120may be surrounded by or adjacent to the first insulating patterns110. The first conductive patterns120may redistribute a first semiconductor chip310mounted on the first substrate100.

The semiconductor package P100may have a fan-out structure by the first substrate100. The first conductive patterns120may include metal and may be connected to first pads125on a bottom surface of the first substrate100. A first protective layer130may be on the bottom surface of the first substrate100and may include, for example, an inorganic material, an organic material, an ABF (Ajinomoto Build-up Film), or an insulating polymer such as an epoxy-based polymer. External terminals140may be attached to the bottom surface of the first substrate100and may be disposed on the first pads125. The external terminals140may be electrically connected through the first pads125to the first conductive patterns120.

A first interconnect substrate200may be on the first substrate100and may include a first opening201penetrating therethrough. For example, the first opening201may have an open hole shape that connects the bottom surface200aof the first interconnect substrate200to the top surface200bof the first interconnect substrate200. The bottom surface200aof the first interconnect substrate200may be in contact with a top surface of the first substrate100. The first interconnect substrate200may include a first conductive member220in a first base layer210. The first base layer210may include, for example, silicon oxide. The first opening201may occupy an inner side of the first interconnect substrate200, and the first conductive member220may occupy an outer side of the first interconnect substrate200.

The first conductive member220may include first lower pads222, first through vias221, and first upper pads223. The first lower pads222may be disposed in a lower portion of the first interconnect substrate200. The first lower pads222may not protrude beyond the bottom surface of the first base layer210, e.g., the first lower pads222may be embedded in the first interconnect substrate200. The first lower pads222may be mechanically coupled and electrically connected to the first conductive patterns120. The first upper pads223may be in an upper portion of the first interconnect substrate200. The first upper pads223may not protrude beyond a top surface of the first base layer210, e.g., the first upper pads223may be embedded in the first interconnect substrate200. The number of the first upper pads223may be different from the number of the external terminals140. The first through vias221may penetrate the first base layer210and electrically connect the first lower pads222to the first upper pads223.

The first semiconductor chip310may be on the first substrate100and may reside in the first opening201of the first interconnect substrate200. In a plan view, the first semiconductor chip310may have a planar shape smaller than that of the first opening201. For example, the first semiconductor chip310may be spaced apart from an inner wall of the first opening201. The first semiconductor chip310may have a bottom surface310afacing the first substrate100and a top surface310bopposite the bottom surface310a. The bottom surface310aof the first semiconductor chip310may be an active surface. The bottom surface310aof the first semiconductor chip310may be in contact with the top surface of the first substrate100. In this configuration, the bottom surface310aof the first semiconductor chip310may be at the same level as that of the bottom surface200aof the first interconnect substrate200. The top surface310bof the first semiconductor chip310may be at the same or a lower level than the top surface200bof the first interconnect substrate200.

The first semiconductor chip310has a lower portion which includes first chip pads311. The first chip pads311may be electrically connected to the first conductive patterns120of the first substrate100. The first semiconductor chip310may be, for example, a memory chip or an application processor (AP) chip. In one embodiment, a plurality of first semiconductor chips310may reside in the first opening201. For example, the plurality of first semiconductor chips310may be placed side-by-side on the first substrate100. In this case, the plurality of first semiconductor chips310may be spaced apart from each other.

A first insulating layer230may be on the first substrate100and may be located in (or fill) an area between the first interconnect substrate200and the first semiconductor chip310. The first insulating layer230may have a lowermost bottom surface in contact with the top surface of the first substrate100. The lowermost bottom surface of the first insulating layer230may be at the same level as that of the bottom surface200aof the first interconnect substrate200. The first insulating layer230may include, for example, an insulating polymer, a thermosetting resin, or an ABF.

A second substrate400may be on the first interconnect substrate200and, for example, may cover the top surface200bof the first interconnect substrate200and the top surface310bof the first semiconductor chip310. The second substrate400may be a redistribution substrate. For example, the second substrate400may include second insulating patterns410and second conductive patterns420. The second insulating patterns410may include, for example, silicon oxide. The second conductive patterns420may include one or more conductive layers between the second insulating patterns410and one or more vias penetrating the second insulating patterns410. The second conductive patterns420may be connected to second pads425in a lower portion of the second substrate400. The second pads425may be exposed from a bottom surface of the second substrate400.

In a plan view, the second pads425may not overlap the first semiconductor chip310. For example, the second substrate400may be electrically connected to the first semiconductor chip310and the first substrate100through the first interconnect substrate200connected to the second pads425. Thus, the second pads425may be on the top surface200bof the first interconnect substrate200and outside the first semiconductor chip310. The second pads425may be coupled to the first upper pads223of the first interconnect substrate200.

The second conductive patterns420may redistribute a second semiconductor chip320mounted on the second substrate400. The second conductive patterns420may be electrically connected through the second pads425to the first upper pads223of the first interconnect substrate200. In a plan view, the second pads425may be more densely distributed than the external terminals140. The second conductive patterns420may include metal. InFIG. 1, the second pads425of the second substrate400are directly connected to first upper pads223.

FIG. 2illustrates another embodiment of a semiconductor package P200. As illustrated inFIG. 2, the second substrate400may further include a second protective layer430and one or more interconnect terminals440. The second protective layer430may include an ABF or an insulating polymer such as an epoxy-based polymer. The second protective layer430may be on the bottom surface of the second substrate400. The interconnect terminals440may be between the second conductive patterns420and the first upper pads223, to electrically connect the second conductive patterns420to the first upper pads223. The semiconductor package P200may be substantially the same as the semiconductor package P100ofFIG. 1, except for the second substrate400.

FIG. 3illustrates another embodiment of a semiconductor package P300. As illustrated inFIG. 3, a glue layer312may further be included between the second substrate400and the top surface310bof the first semiconductor chip310. The glue layer312may include, for example, silicon resin. In one embodiment, in order to enhance heat radiation, the glue layer312may include a thermal interface material (TIM) such as thermal grease. The second substrate400may be rigidly adhered through the glue layer312to the first semiconductor chip310. The glue layer312may include an insulating material The glue layer312may insulate the first semiconductor chip310from the second substrate400. The semiconductor package P300may be substantially the same as the semiconductor package P100ofFIG. 1, except from the glue layer312described above.

Referring back toFIG. 1, a second interconnect substrate500may be on the second substrate400and may include a second opening501penetrating therethrough.FIG. 1illustrates that the second opening501of the second interconnect substrate500vertically overlaps the first opening201of the first interconnect substrate200. In one embodiment, the second interconnect substrate500may have a bottom surface500ain contact with a top surface of the second substrate400.

The second interconnect substrate500may include a second base layer510and a second conductive member520in the second base layer510. The second base layer510may include, for example, silicon oxide. The second opening501may occupy an inner side of the second interconnect substrate500, and the second conducive member520may occupy an outer side of the second interconnect substrate500.

The second conductive member520may include second lower pads522, second through vias521, and second upper pads523. The second lower pads522may be in a lower portion of the second interconnect substrate500. The second lower pads522may be mechanically coupled and electrically connected to the second conductive patterns420of the second substrate400. The second upper pads523may be in an upper portion of the second interconnect substrate500. The second through vias521may penetrate the second base layer510and electrically connect the second lower pads522to the second upper pads523.

A second semiconductor chip320may be on the second substrate400and may reside in the second opening501of the second interconnect substrate500. In a plan view, the second semiconductor chip320may have a planar shape smaller than that of the second opening501. For example, the second semiconductor chip320may be spaced apart from an inner wall of the second opening501.

The second semiconductor chip320may have a bottom surface320afacing the second substrate400and a top surface320bopposite the bottom surface320a. The bottom surface320aof the second semiconductor chip320may be an active surface. The bottom surface320aof the second semiconductor chip320may be in contact with the top surface of the second substrate400. In this configuration, the bottom surface320aof the second semiconductor chip320may be at the same level as that of the bottom surface500aof the second interconnect substrate500.

The second semiconductor chip320may include second chip pads321in a lower portion thereof. The second chip pads321may be electrically connected to the second conductive patterns420of the second substrate400. The second semiconductor chip320may be, for example, a memory chip or an application processor chip. In other embodiment, a plurality of second semiconductor chips320may reside in the second opening501.

A second insulating layer530may be on the second substrate400and may be located in (or fill) an area between the second interconnect substrate500and the second semiconductor chip320. The second insulating layer530may have a lowermost bottom surface in contact with the top surface of the second substrate400. The lowermost bottom surface of the second insulating layer530may be at the same level as that of the bottom surface500aof the second interconnect substrate500. The second insulating layer530may include an insulating polymer, a thermosetting resin, or an ABF.

A molding layer600may be on the second substrate400. For example, the molding layer600may cover the top surface500bof the second interconnect substrate500and the top surface320bof the second semiconductor chip320. The molding layer600may include, for example, an insulating polymer such as an epoxy-based polymer or a high molecular material such as a thermosetting resin. In other embodiments, the second upper pads523of the second interconnect substrate500may be exposed to an opening in the molding layer600.

The semiconductor packages P100to P300of the aforementioned embodiments may have a structure in which a plurality of fan-out panel level packages (FO-PLP) is stacked. The semiconductor packages P100to P300may not require separate interconnect terminals to electrically connect the stacked semiconductor chips310and320to each other, and instead may utilize the plate-shaped substrates200and500and the conductive members220and520(which are outside the semiconductor chips310and320) to electrically connect the stacked semiconductor chips310and320to each other.

Accordingly, each of the semiconductor packages P100to P300includes a plurality of the stacked semiconductor chips310and320and may have reduced thickness and size. It therefore may be possible to enhance integration of devices, each of which includes at least one of the semiconductor packages P100to P300. In addition, an electrical path may be reduced between the semiconductor chips310and320, and thereby the semiconductor packages P100to P300may have excellent electrical characteristics.

The semiconductor packages P100to P300of the aforementioned embodiments may have a multi-stack structure in which three or more semiconductor chips are stacked. For example, the semiconductor packages P100to P300may further include a third semiconductor chip stacked on the second semiconductor chip320.

FIG. 4illustrates a cross-sectional of another embodiment of a semiconductor package P400which may include a third substrate700, a third interconnect substrate800, and a third semiconductor chip330, all of which are between the second interconnect substrate500and the molding layer600. The third substrate700and the third interconnect substrate800may be configured substantially the same as the second substrate400and the second interconnect substrate500, respectively. The semiconductor package P400may be substantially the same as at least one of the semiconductor packages P100to P300discussed with reference toFIGS. 1 to 3, except of the aforementioned description.

FIG. 5illustrates an embodiment of a method for manufacturing a semiconductor package, which, for example, may correspond to any of the aforementioned embodiments. FIGS.6A to6K are cross-sectional views illustrating various stages of the method for manufacturing a semiconductor package according to exemplary embodiments.FIGS. 6A to 6Kcorrespond to cross-sectional views taken along line I-I′ inFIG. 5.

Referring toFIGS. 5 and 6A, a second interconnect substrate500includes a second conductive member520in a second base layer510. The second conductive member520may include second lower pads522, second through vias521, and second upper pads523. For example, the second base layer510may be etched and its inside may be filled with a conductive material to form the second through vias521, the second lower pads522, and the second upper pads523.

Referring toFIGS. 5 and 6B, a second opening501may be formed in the second interconnect substrate500. A portion of the second interconnect substrate500may be removed to form the second opening501penetrating therethrough. The second opening501may be formed, for example, by an etching process such as drilling, laser ablation, or laser cutting. The removed portion of the second interconnect substrate500may be a zone in which a second semiconductor chip320is provided in a subsequent process.

Referring toFIGS. 5 and 6C, the second interconnect substrate500may be attached onto a first carrier substrate910. The first carrier substrate910may be, for example, an insulating substrate including glass or polymer or a conductive substrate including metal.

The first carrier substrate910may have a top surface which includes an adhesive member used to adhere the first carrier substrate910to a bottom surface500aof the second interconnect substrate500. The adhesive member may include, for example, glue tape.

Referring toFIGS. 5 and 6D, a second semiconductor chip320may be on the first carrier substrate910and in the second opening501of second interconnect substrate500. At this stage, the second semiconductor chip320may be adhered to the first carrier substrate910. The second semiconductor chip320may have a lower portion with second chip pads321.

Referring toFIGS. 5 and 6E, a second insulating layer530may be formed on the first carrier substrate910and may be located (or fill) an area between the second interconnect substrate500and the second semiconductor chip320. For example, an insulating material may be injected between the second interconnect substrate500and the second semiconductor chip320, and then cured to form the second insulating layer530. The insulating material may include, for example, an insulating polymer or a thermosetting resin.

Referring toFIGS. 5 and 6F, a support substrate920may be provided on the second interconnect substrate500. The support substrate920may be, for example, an insulating substrate such as glass substrate. A carrier glue layer921may be used to adhere the support substrate920to a top surface500bof the second interconnect substrate500and a top surface320bof the second semiconductor chip320. The carrier glue layer921may a resin film.

The first carrier substrate910may be removed. The first carrier substrate910may be removed as designated by a dotted line, to thereby expose the bottom surface500aof the second interconnect substrate200and a bottom surface320aof the second semiconductor chip320. The first carrier substrate910may be removed by applying a shear stress or by chemically treating the adhesive member discussed with reference toFIGS. 5 and 6C.

Referring toFIGS. 5 and 6G, a second substrate400may be formed on the bottom surface320aof the second semiconductor chip320and the bottom surface500aof the second interconnect substrate500. For example, second insulating patterns410, second conductive patterns420, and second pads425may be foamed on the bottom surface320aof the second semiconductor chip320and the bottom surface500aof the second interconnect substrate500. As a result, the second substrate400may be fabricated.

An insulating layer (e.g., a silicon oxide layer) may be formed on the bottom surface320aof the second semiconductor chip320and the bottom surface500aof the second interconnect substrate500, and then patterned to form a portion of a second insulating pattern410. The second chip pad321and the second lower pad522may be exposed through the second insulating pattern410. A conductive layer may be formed on a bottom surface of the second insulating pattern410, and then patterned to form the second conductive patterns420and the second pads425. The second conductive pattern420may be electrically connected to one of the second chip pad321of the second semiconductor chip320and the second lower pad522of the second interconnect substrate500. An insulating layer may be formed on bottom surfaces of the second conductive patterns420and then patterned to form other portion of the second insulating pattern410. At this stage, the second pads425may be exposed through the second insulating pattern410.

Referring toFIGS. 5 and 6H, a first interconnect substrate200and a first semiconductor chip310may be provided on a bottom surface of the second substrate400, for example, in the same manner as discussed with reference toFIGS. 6A to 6E. For example, a first opening201may be formed in the first interconnect substrate200. The first interconnect substrate200may be adhered onto a second carrier substrate930. The first semiconductor chip310may be provided on the second carrier substrate930. The first semiconductor chip310may be positioned in the first opening201of the first interconnect substrate200. A first insulating layer230may be provided to fill an area between the first interconnect substrate200and the first semiconductor chip310. Thereafter, the first interconnect substrate200may be adhered onto the bottom surface of the second substrate400. At this stage, first upper pads223of the first interconnect substrate200may be mechanically coupled and electrically connected to the second pads425of the second substrate400.

Referring toFIGS. 5 and 6I, the second carrier substrate930may be removed, for example, by applying a shear stress or by chemically treating an adhesive layer between the second carrier substrate930and the second substrate400. The second carrier substrate930may be removed as designated by a dotted line, to thereby expose a bottom surface200aof the first interconnect substrate200and a bottom surface310aof the first semiconductor chip310.

Referring toFIGS. 5 and 6J, a first substrate100may be formed beneath the first semiconductor chip310and the first interconnect substrate200. First insulating patterns110, first conductive patterns120, and first pads125may be formed on the bottom surface310aof the first semiconductor chip310and the bottom surface200aof the first interconnect substrate200. As a result, the first substrate100may be fabricated. The first substrate100may be formed, for example, by a redistribution layer (RDL) process, a damascene process, a dual damascene process, or a back end of line (BEOL) process.

The first conductive pattern120may be coupled to first chip pads311of the first semiconductor chip310and first lower pads222of the first interconnect substrate200. A first protective layer130may be formed on a bottom surface of the first substrate100. The first protective layer130may be patterned to expose the first pads125. External terminals140may be formed on the exposed first pads125and electrically connected to the first upper pads223through the first conductive patterns120of the first substrate100, the first lower pads222of the first interconnect substrate200, and first through vias221of the first interconnect substrate200.

Referring toFIGS. 5 and 6K, the support substrate920may be removed. Then a molding layer600may be formed on the second substrate400. For example, a molding member may be coated on the second interconnect substrate500and the second semiconductor chip320and then cured to form the molding layer600. The molding member may include, for example, an ABF, an insulating polymer such as an epoxy-based polymer, or a high molecular material such as a thermosetting resin. The molding member may be cured, for example, by heat treatment at a temperature more than about 180° C. The molding layer600may cover the top surface500bof the second interconnect substrate500and the top surface320bof the second semiconductor chip320.

Referring again toFIGS. 1 and 5, a sawing process may be performed to dice the first substrate100, the first interconnect substrate200, the second substrate400, and the second interconnect substrate500into individual semiconductor packages P100. When the sawing process is performed, the first substrate100, the first interconnect substrate200, the second substrate400, and the second interconnect substrate500may be cut along a sawing line SL shown inFIG. 6K.

In accordance with one or more of the aforementioned embodiments, a semiconductor package includes a plurality of stacked semiconductor chips with reduced thickness and therefore decreased size. Accordingly, it may be possible to increase integration of devices each including the semiconductor package.