Technologies for providing adaptive memory media management

Technologies for providing adaptive memory media management include media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry. The media access circuitry is further to manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.

BACKGROUND

Typically, a memory controller may track memory access operations that have been performed on a memory media (e.g., the device or material on which the data is retained), and modify future memory access operations based on the record of the previous memory access operations. For example, by tracking the amount of time that has elapsed since a memory cell (e.g., a unit of the memory media capable of retaining a data value) was written to, the memory controller may adjust a reference voltage usable to determine whether a voltage at that memory cell is representative of a one or a zero (or other value) due to a drift (e.g., a gradual change) in the voltage over time. Similarly, the tracked memory accesses may be usable in performing wear leveling (e.g., distributing memory access operations across the available memory cells of the memory media) to reduce the likelihood that a subset of the available memory cells of the memory media will be used more, and thereby fail sooner, than other memory cells of the memory media.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring now toFIG. 1, a compute device100for providing adaptive memory media management includes a processor102, memory104, an input/output (I/O) subsystem112, a data storage device114, and communication circuitry122. Of course, in other embodiments, the compute device100may include other or additional components, such as those commonly found in a computer (e.g., a display, peripheral devices, etc.). Additionally, in some embodiments, one or more of the illustrative components may be incorporated in, or otherwise form a portion of, another component. As explained in more detail herein, the media access circuitry108, in the illustrative embodiment, is local to (e.g., on the same die, in the same package, etc.) the memory media110and may perform compute operations on data from the memory media110, thereby eliminating the need for data to be sent (e.g., through a bus) to the processor102or another component of the compute device100for computations to be performed on the data. Additionally, the compute device100, and in particular, the memory104of the compute device100, selectively disables or enables management, by the memory controller106(e.g., by a media management logic unit152, which may be embodied as any device or circuitry, such as reconfigurable circuitry, an application specific integrated circuit (ASIC), etc. configured to perform management of memory media), of memory access operations performed on the memory media110. In particular, and as described in more detail herein, in performing compute operations on data in the memory media110, the media access circuitry108may perform multiple reads and/or writes to the memory media110. As such, rather than reporting each memory access operation to the memory controller106(e.g., through a bus that consumes time and energy to transmit data), management of the memory media110by the memory controller106is temporarily disabled and management of the memory access operations is performed by the media access circuitry108(e.g., by a media management logic unit150, which may be embodied as any device or circuitry, such as reconfigurable circuitry, an application specific integrated circuit (ASIC), etc. configured to perform management of the memory media110).

In the illustrative embodiment, when the memory access operations are complete (e.g., when the in-memory compute operation has finished), the media access circuitry108(e.g., the media management logic unit150) re-enables the ability of the memory controller106(e.g., the media management logic unit152) to manage (e.g., control the operations of) the memory media110. The media access circuitry108(e.g., the media management logic unit150) may also provide, to the memory controller106, memory media usage data that is indicative of the memory access operations that were performed during the time the media access circuitry108(e.g., the media management logic unit150) was exclusively managing the memory access operations and, as such, may be usable by memory controller106to perform wear leveling and/or to adjust a reference voltage used in determining the value, such as one or zero, at a particular memory cell in the memory media110in any subsequent memory access operations (i.e., operations that the memory controller106has not been prevented from managing). As compared to other systems, by performing the adaptive media management described above and in more detail below, the compute device100reduces energy use, improves bandwidth and latency for in-memory compute operations (e.g., matrix operations), and reduces the possibility that the memory controller106will inadvertently interrupt an on-going operation (e.g., by issuing a command that changes or stops an in-memory compute operation that the memory controller106was unaware of).

The memory media110, in the illustrative embodiment, has a three-dimensional cross point architecture that has data access characteristics that differ from other memory architectures (e.g., dynamic random access memory (DRAM)), such as enabling access to one bit per tile and incurring time delays between reads or writes to the same partition or other partitions. The media access circuitry108is configured to make efficient use (e.g., in terms of power usage and speed) of the architecture of the memory media110, such as by accessing multiple tiles in parallel within a given partition, utilizing scratch pads (e.g., relatively small, low latency memory) to temporarily retain and operate on data read from the memory media110, and broadcasting data read from one partition to other portions of the memory104to enable matrix calculations (e.g., tensor operations) to be performed in parallel within the memory104. Additionally, in the illustrative embodiment, instead of sending read or write requests to the memory104to access matrix data, the processor102may send a higher-level request (e.g., a type of matrix calculation to perform) and provide the locations and dimensions (e.g., in memory) of the matrices to be utilized in the requested operation (e.g., an input matrix, a weight matrix, and an output matrix). Further, rather than sending back the resulting data to the processor102, the memory104may merely send back an acknowledgement (e.g., “Done”), indicating that the requested operation has been completed. As such, many compute operations, such as artificial intelligence operations (e.g., tensor operations involving matrix calculations) can be performed in memory104, with minimal usage of the bus between the processor102and the memory104. In some embodiments the media access circuitry108is included in the same die as the memory media110. In other embodiments, the media access circuitry108is on a separate die but in the same package as the memory media110. In yet other embodiments, the media access circuitry108is in a separate die and separate package but on the same dual in-line memory module (DIMM) or board as the memory media110.

The processor102may be embodied as any device or circuitry (e.g., a multi-core processor(s), a microcontroller, or other processor or processing/controlling circuit) capable of performing operations described herein, such as executing an application (e.g., an artificial intelligence related application that may utilize a neural network or other machine learning structure to learn and make inferences). In some embodiments, the processor102may be embodied as, include, or be coupled to an FPGA, an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein.

The memory104, which may include a non-volatile memory (e.g., a far memory in a two-level system main memory scheme), includes the memory media110and the media access circuitry108(e.g., a device or circuitry, such as integrated circuitry constructed from complementary metal-oxide-semiconductors (CMOS) or other materials) underneath (e.g., at a lower location) and coupled to the memory media110. The media access circuitry108is also connected to the memory controller106, which may be embodied as any device or circuitry (e.g., a processor, a co-processor, dedicated circuitry, etc.) configured to selectively read from and/or write to the memory media110in response to corresponding requests (e.g., from the processor102which may be executing an artificial intelligence related application that relies on tensor operations to train a neural network and/or to make inferences). Further, and as described above and in more detail below, the memory controller106may temporarily hand off management of memory access operations to the media access circuitry108(e.g., when the media access circuitry108is managing an in-memory compute operation). Referring briefly toFIG. 2, the memory media110, in the illustrative embodiment, includes a tile architecture, also referred to herein as a cross point architecture (e.g., an architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance), in which each tile (e.g., memory cell) is addressable by an x parameter and a y parameter (e.g., a column and a row). The memory media110includes multiple partitions, each of which includes the tile architecture. The partitions may be stacked as layers202,204,206to form a three-dimensional cross point architecture (e.g., Intel 3D XPoint™ memory, Intel Optane™ memory, or QuantX™ memory). Unlike typical memory devices, in which only fixed-size multiple-bit data structures (e.g., byte, words, etc.) are addressable, the media access circuitry108is configured to read individual bits, or other units of data, from the memory media110at the request of the memory controller106, which may produce the request in response to receiving a corresponding request from the processor102.

Referring back toFIG. 1, the media access circuitry108, in the illustrative embodiment, includes a tensor logic unit130, which may be embodied as any device or circuitry (e.g., CMOS circuitry) configured to offload the performance of tensor operations from other portions of the media access circuitry108. The tensor logic unit130, in the illustrative embodiment, includes multiple memory scratch pads132, each of which may be embodied as any device or circuitry (e.g., static random access memories (SRAMs), register files, etc.) usable to provide relatively fast (e.g., low latency) access to data (e.g., matrix data) that has been read from the memory media110. In the illustrative embodiment, the scratch pads132provide faster read and write access times than the memory media110which has comparatively slower access times and a larger capacity. The tensor logic unit130may also include an error correction code (ECC) logic unit134, which may be embodied as any device or circuitry (e.g., reconfigurable circuitry, an ASIC, etc.) configured to perform an error correction algorithm (e.g., a Reed-Solomon algorithm, a Bose-Chaudhuri-Hocquenghem (BCH) algorithm, etc.) on data written to and read from the memory media110to detect and correct any errors (e.g., due to corruption). Additionally, in the illustrative embodiment, the tensor logic unit130includes multiple compute logic units136each of which may be embodied as any device or circuitry (e.g., reconfigurable circuitry, ASICs, etc.) configured to perform compute operations on data read from the memory media110(e.g., after the ECC logic unit134has performed an error correction process on the data).

Referring briefly toFIG. 3, in the illustrative embodiment, components of the memory104are divided into clusters310,320,330(e.g., groupings of components). The cluster310includes multiple partitions311of the memory media110, a set of scratch pads312,314,316, each similar to the scratch pads132ofFIG. 1, and a corresponding compute logic unit318, similar to the compute logic unit136ofFIG. 1. Similarly, the cluster320includes another set of partitions321of the memory media110, a corresponding set of scratch pads322,324,326, and a corresponding compute logic unit328. The cluster330also includes a set of partitions331of the memory media110, a corresponding set of scratch pads332,334,336, and a compute logic unit338. In the illustrative embodiment, in operation, the compute logic unit318reads a subset of matrix data (e.g., one value of an input matrix A from the set of partitions (e.g., partitions311)) and provides the read data to the ECC logic unit134to perform an error correction process to correct any errors in the data. The compute logic unit318may additionally write the data (e.g., after the error correction process has been performed) into the corresponding scratch pad312and may broadcast that same subset of the matrix data to the corresponding scratch pads of the other clusters (e.g., to the scratch pads322,332). Similarly, the compute logic unit328may read, from the corresponding set of partitions321another subset of the matrix data (e.g., another value of the input matrix A) into the corresponding scratch pad322, utilizing the ECC logic unit134to correct any errors, and broadcast that subset of the matrix data to the other scratch pads that are to store data for that matrix (e.g., to the scratch pads312,332). The compute logic unit338may perform similar operations.

By broadcasting, to the other scratch pads, matrix data that has been read from a corresponding set of partitions of the memory media110, the media access circuitry108reduces the number of times that a given section (e.g., set of partitions) of the memory media110must be accessed to obtain the same matrix data (e.g., the read matrix data may be broadcast to multiple scratch pads after being read from the memory media110once, rather than reading the same matrix data from the memory media110multiple times). Further, by utilizing multiple compute logic units318,328,338that are each associated with corresponding scratch pads312,314,316,322,224,226,232,234,236, the media access circuitry108may perform the portions of a tensor operation (e.g., matrix multiply and accumulate) concurrently (e.g., in parallel). It should be understood that while three clusters310,320,330are shown inFIG. 3for simplicity, the actual number of clusters and corresponding partitions, scratch pads, and compute logic units may differ depending on the particular embodiment.

Referring briefly toFIG. 4, an example of a matrix multiplication (e.g., matrix multiply and accumulate) operation400that may be performed by the memory104is shown. As illustrated, matrix data in an input matrix A is multiplied by matrix data in another matrix B (e.g., weight data for a layer of a convolutional neural network) and the resultant data is written to the output matrix C. Each matrix represented inFIG. 4is temporarily stored as matrix data in the scratch pads132of the media access circuitry108. In some embodiments, the output matrix C may be utilized as an input matrix for a subsequent tensor operation (e.g., as an input matrix for a subsequent layer of a convolutional neural network).

Referring back toFIG. 1, the memory104may include non-volatile memory and volatile memory. The non-volatile memory may be embodied as any type of data storage capable of storing data in a persistent manner (even if power is interrupted to the non-volatile memory). For example, the non-volatile memory may be embodied as one or more non-volatile memory devices. The non-volatile memory devices may include one or more memory devices configured in a cross point architecture that enables bit-level addressability (e.g., the ability to read from and/or write to individual bits of data, rather than bytes or other larger units of data), and are illustratively embodied as three-dimensional (3D) cross point memory. In some embodiments, the non-volatile memory may additionally include other types of memory, including any combination of memory devices that use chalcogenide phase change material (e.g., chalcogenide glass), ferroelectric transistor random-access memory (FeTRAM), nanowire-based non-volatile memory, phase change memory (PCM), memory that incorporates memristor technology, Magnetoresistive random-access memory (MRAM) or Spin Transfer Torque (STT)-MRAM. The volatile memory may be embodied as any type of data storage capable of storing data while power is supplied volatile memory. For example, the volatile memory may be embodied as one or more volatile memory devices, and is periodically referred to hereinafter as volatile memory with the understanding that the volatile memory may be embodied as other types of non-persistent data storage in other embodiments. The volatile memory may have an architecture that enables bit-level addressability, similar to the architecture described above.

The processor102and the memory104are communicatively coupled to other components of the compute device100via the I/O subsystem112, which may be embodied as circuitry and/or components to facilitate input/output operations with the processor102and/or the main memory104and other components of the compute device100. For example, the I/O subsystem112may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem112may form a portion of a system-on-a-chip (SoC) and be incorporated, along with one or more of the processor102, the main memory104, and other components of the compute device100, in a single chip.

The data storage device114may be embodied as any type of device configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage device. In the illustrative embodiment, the data storage device114includes a memory controller116, similar to the memory controller106, a media management logic unit162, similar to the media management logic unit152, storage media120, similar to the memory media110, and media access circuitry118, similar to the media access circuitry108, including a tensor logic unit140, similar to the tensor logic unit130, scratch pads142, similar to the scratch pads132, an ECC logic unit144, similar to the ECC logic unit134, compute logic units146, similar to the compute logic units136, and a media management logic unit160, similar to the media management logic unit150. As such, the data storage device114is capable of selectively disabling or enabling management, by the memory controller116, of memory access operations and handing off exclusive management of the memory access operations to the media access circuitry, such as during an in-memory compute operation (e.g., a matrix operation performed in the media access circuitry118on data in the storage media120). The data storage device114may include a system partition that stores data and firmware code for the data storage device114and one or more operating system partitions that store data files and executables for operating systems.

The communication circuitry122may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications over a network between the compute device100and another device. The communication circuitry122may be configured to use any one or more communication technology (e.g., wired or wireless communications) and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, etc.) to effect such communication.

The illustrative communication circuitry122includes a network interface controller (NIC)124, which may also be referred to as a host fabric interface (HFI). The NIC124may be embodied as one or more add-in-boards, daughter cards, network interface cards, controller chips, chipsets, or other devices that may be used by the compute device100to connect with another compute device. In some embodiments, the NIC124may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC124may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC124. In such embodiments, the local processor of the NIC124may be capable of performing one or more of the functions of the processor102. Additionally or alternatively, in such embodiments, the local memory of the NIC124may be integrated into one or more components of the compute device100at the board level, socket level, chip level, and/or other levels.

Referring now toFIG. 5, the compute device100, in operation, may execute a method500for providing adaptive memory media management. The method500is described with reference to the memory104. However, it should be understood that the method500could be additionally or alternatively performed using the memory of the data storage device114. The method500begins with block502in which the compute device100(e.g., the memory104) determines whether to enable adaptive memory media management. The compute device100may enable adaptive memory media management in response to a determination that a configuration setting (e.g., in a configuration file) indicates to enable adaptive memory media management, in response to a determination that media management logic units150,152are present, and/or based on other factors. Regardless, in response to a determination to enable adaptive memory media management, the method500advances to block504, in which the compute device100(e.g., the memory104) may receive a request to perform one or more memory access operations (e.g., from the processor102executing an application). As indicated in block506, the memory104may receive a request to be managed by a workload aware media access circuitry (e.g., the media access circuitry108) connected to the memory media110. The media access circuitry108is workload aware because it is integral to (e.g., coordinates and utilizes components of the media access circuitry108to perform) in-memory compute operations that may be performed in association with a workload (e.g., the application executed by the processor102). As indicated in block508, the request may be a request to be managed by a complementary metal-oxide semiconductor (CMOS) connected to the memory media110(e.g., to be managed by the media access circuitry108, which may be formed from a CMOS). The request may be a request to be managed by a media access circuitry located in the same die (e.g., semiconductor die) or package (e.g., semiconductor package) as the memory media110(e.g., to be managed by the media access circuitry108, which may be integrated into the same die or the same package as the memory media110), as indicated in block510.

In some embodiments, the request is a request to perform multiple memory access operations (e.g., multiple writes, multiple reads, etc.), as indicated in block512. As indicated in block514, the request may be a request to perform one or more in-memory compute operations. For example, and as indicated in block516, the request may be to perform one or more matrix operations (e.g., a matrix multiplication operation similar to the operation400ofFIG. 4). As indicated in block518, the request may be to perform one or more artificial intelligence operations (e.g., operations relating to training a neural network, producing an inference with a neural network, etc.). Alternatively, the request may be a request that is to be managed by the memory controller106, as indicated in block520(e.g., the request does not require an awareness of multiple read and/or write operations performed within the memory104). For example, and as indicated in block522, the request may be to perform a single memory access operation (e.g., to write data or to read data). In the illustrative embodiment, and as indicated in block524, the request is a request to perform one or more memory access operations on a memory media having a cross point architecture (e.g., an architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance). Further, and as indicated in block526, the request may be a request to perform one or more media access operations on a memory media having a three dimensional cross point architecture (e.g., an architecture in which sets of tiles are stacked as layers, as described with reference toFIG. 2). In other embodiments, the request may be to perform the memory access operations on a memory media having a different architecture. In block528, the compute device100(e.g., the memory104) determines the subsequent course of action based on whether a request to perform one or more memory operations was received. If not, the method500loops back to block504to potentially receive a request to perform one or more memory access operations. Otherwise (e.g., if a request was received), the method500advances to block530ofFIG. 6, in which the compute device100(e.g., the memory104) determines the subsequent course of action based on whether the received request is to be managed by a workload aware media access circuitry (e.g., the media access circuitry108) or not.

Referring now toFIG. 6, if the request is not to be managed by the workload aware media access circuitry (e.g., the media access circuitry108), the method500advances to block532, in which the compute device100manages the requested memory access operation with the memory controller106. In doing so, and as indicated in block534, the compute device100may read from the memory media as indicated in block534. Alternatively, the compute device100may write to the memory media110, as indicated in block536. As indicated in block538, the compute device100(e.g., the memory controller106) may update memory media usage data, which may be embodied as any data indicative of access operations that have been performed on the memory media110over time. In doing so, the memory controller106may write, to the memory media usage data, a record of the memory access operation that was just performed, including the memory cell(s) that were accessed, a timestamp of when the memory access operation occurred, and the type of access operation that was performed (e.g., read or write).

Referring back to block530, if the request is instead to be managed by workload aware media access circuitry, the method500advances to block540, in which the compute device100(e.g., the media access circuitry108) manages the requested memory access operation(s). In doing so, and as indicated in block542, the media access circuitry108disables memory controller management of the memory media (e.g., prevents the memory controller106from issuing commands that may interrupt the requested memory operation(s), prevents data, such as notifications of completions of operations and/or other status data, from being reported from the memory media110and/or the media access circuitry108to the memory controller106, etc.). As indicated in block544, the media access circuitry108may disable the memory controller management of the memory media110by providing a command to the memory controller to disable management of the memory media. As indicated in block546, the media access circuitry108may provide the command in response to a determination that multiple memory access operations are to be performed (e.g., the media access circuitry108is to manage the request because multiple memory access operations to be performed in association with the request). In some embodiments, the media access circuitry108may provide the command to the memory controller106in response to a determination that an in-memory compute operation is to be performed (e.g., the request is to be managed by the media access circuitry108because the request is to perform an in-memory compute operation), as indicated in block548. As another example, the media access circuitry108may provide the command to the memory controller106in response to a determination that the received request includes an instruction that was not understood by (e.g., not within an instruction set of) the memory controller106(e.g., the memory controller106may pass the request on to the media access circuitry108with data indicating that the request was not understood by the memory controller106), as indicated in block550. For example, a specific type of in-memory compute operation indicated in the request may be within the instruction set of the media access circuitry108but not within the instruction set of the memory controller106. As indicated in block552, the media access circuitry108may additionally adjust a block size (e.g., from a default size that is typically used) that is usable to access data in the memory media110. In doing so, and as indicated in block554, the media access circuitry108may adjust the block size to a predefined size that is usable for accessing matrix data. For example, the media access circuitry108may adjust the block size to 512×512 bits, as indicated in block556.

Referring now toFIG. 7, the media access circuitry108, in managing the requested memory access operation(s), performs the requested memory access operation(s), as indicated in block558. In doing so, and as indicated in block560, the media access circuitry108may perform memory access operations to facilitate an in-memory compute operation. For example, and as indicated in block562, the media access circuitry108may perform memory access operations to facilitate a matrix operation (e.g., a matrix multiplication operation, similar to the operation400ofFIG. 4), such as reading matrix elements, multiplying them, and writing a result back to the memory media110one or more times. As indicated in block564, the media access circuitry108may perform the memory access operations during the performance of an artificial intelligence related operation (e.g., training a neural network, producing an inference with a neural network, etc.). As indicated in block566, the media access circuitry108may perform multiple writes to the memory media110. Additionally or alternatively, and as indicated in block568, the media access circuitry108may perform multiple reads from the memory media110. Further, in performing the memory access operations, the media access circuitry108may distribute memory accesses (e.g., writes and reads) across the memory media110to level the wear on the memory cells (e.g., to avoid using the same memory cells repeatedly, causing those memory cells to fail faster than other memory cells in the memory media), as indicated in block570. As indicated in block572, the media access circuitry108, in the illustrative embodiment, tracks the memory access operation(s) (e.g., updates memory media usage data using a process similar to that described with reference to block538ofFIG. 6).

Subsequently (e.g., after the requested memory access operations have been completed), the media access circuitry108, in the illustrative embodiment, provides, to the memory controller106, memory media usage data indicative of the memory access operations that were managed by the media access circuitry108(e.g., the memory access operations tracked in block572), as indicated in block574. Further, and as indicated in block576, the media access circuitry108, in the illustrative embodiment, re-enables memory controller management of the memory media110(e.g., by sending an instruction to the memory controller106to re-enable management of the memory media110, etc.). As indicated in block578, the media access circuitry108may adjust the memory access block size. For example, and as indicated in block580, the media access circuitry108may adjust the memory access block size to be different from 512×512 bits. After the media access circuitry108has performed block578, or after the memory controller106has performed block532, the method500may proceed to block582, in which the memory104updates, as a function of the memory media usage data, reference voltage data usable to determine data values present in the memory media (e.g., by accounting for the amount of time that has elapsed since a value was written to a given memory cell and the rate at which the voltage drifts from its initial voltage). Subsequently, the method500loops back to block502ofFIG. 5in which the compute device100determines whether to continue to enable adaptive media management.

EXAMPLES

Example 1 includes a memory comprising media access circuitry connected to a memory media, wherein the media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry; and manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.

Example 2 includes the subject matter of Example 1, and wherein the media access circuitry is further to re-enable memory controller management of the memory media after the at least one memory access operation has been performed.

Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to manage the requested at least one memory access operation comprises to track, with the media access circuitry, the at least one memory access operation; and the media access circuitry is further to provide, to the memory controller and after the at least one memory access operation has been performed, memory media usage data indicative of the memory access operations that were managed by the media access circuitry.

Example 4 includes the subject matter of any of Examples 1-3, and wherein the media access circuitry is further to update, as a function of the memory media usage data, reference voltage data usable to determine data values present in the memory media.

Example 5 includes the subject matter of any of Examples 1-4, and wherein to manage the requested at least one memory access operation comprises to adjust a block size usable to access data in the memory media.

Example 6 includes the subject matter of any of Examples 1-5, and wherein to adjust the block size comprises to adjust the block size to a predefined size usable to access matrix data.

Example 7 includes the subject matter of any of Examples 1-6, and wherein the media access circuitry is further to re-adjust the block size after the at least one memory access operation has been performed.

Example 8 includes the subject matter of any of Examples 1-7, and wherein to receive a request to perform at least one memory access operation to be managed by the media access circuitry comprises to receive a request to perform multiple memory access operations.

Example 9 includes the subject matter of any of Examples 1-8, and wherein to receive a request to perform at least one memory access operation to be managed by the media access circuitry comprises to receive a request to perform at least one in-memory compute operation.

Example 10 includes the subject matter of any of Examples 1-9, and wherein to receive a request to perform at least one memory access operation to be managed by the media access circuitry comprises to receive a request to perform one or more matrix operations.

Example 11 includes the subject matter of any of Examples 1-10, and wherein to receive a request to perform at least one memory access operation to be managed by the media access circuitry comprises to receive a request to perform one or more artificial intelligence operations.

Example 12 includes the subject matter of any of Examples 1-11, and wherein the media access circuitry is formed from a complementary metal-oxide-semiconductor.

Example 13 includes the subject matter of any of Examples 1-12, and wherein the memory media has a cross point architecture.

Example 14 includes the subject matter of any of Examples 1-13, and wherein the memory media has a three dimensional cross point architecture.

Example 15 includes a method comprising receiving, by a media access circuitry connected to a memory media, a request to perform at least one memory access operation to be managed by the media access circuitry; and managing, by the media access circuitry, the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.

Example 16 includes the subject matter of Example 15, and further including re-enabling, by the media access circuitry, memory controller management of the memory media after the at least one memory access operation has been performed.

Example 17 includes the subject matter of any of Examples 15 and 16, and wherein managing the requested at least one memory access operation comprises tracking, with the media access circuitry, the at least one memory access operation; the method further comprising providing, to the memory controller and after the at least one memory access operation has been performed, memory media usage data indicative of the memory access operations that were managed by the media access circuitry.

Example 18 includes the subject matter of any of Examples 15-17, and further including updating, by the media access circuitry and as a function of the memory media usage data, reference voltage data usable to determine data values present in the memory media.

Example 19 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause media access circuitry connected to a memory media to receive a request to perform at least one memory access operation to be managed by the media access circuitry; and manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.

Example 20 includes the subject matter of Example 19, and wherein the instructions further cause the media access circuitry to re-enable memory controller management of the memory media after the at least one memory access operation has been performed.