Low phase noise recursive direct digital synthesis with automatic gain control gain stabilization

Disclosed is a recursive, direct digital synthesizer includes an accumulator module and a Coordinate Rotation Digital Computer (CORDIC) module coupled to the accumulator module. The CORDIC module rotates a signal according to a desired rotation angle specified by the accumulator module. An automatic gain control module is coupled to the CORDIC module. The automatic gain control module can apply a level of gain to the rotated signal.

FIELD OF THE INVENTION

The embodiments disclosed herein relate to the creation of high quality sinusoidal signals within digital environments. More particularly, the embodiments relate to direct digital synthesis.

BACKGROUND OF THE INVENTION

Many digital signal processing (DSP) functions, such as those found within communication systems, require the generation of a high-quality sinusoidal signal. A “high quality sinusoidal signal” or “high quality sinusoid,” as used herein, can refer to a sinusoidal signal that is spectrally pure, e.g., one with harmonics, or spurs, lower than a predetermined threshold with respect to the primary or carrier frequency. For example, a high quality sinusoid may have harmonic levels that are at least 60 dB below that of the primary frequency.

Examples of DSP functions that rely upon sinusoids can include, but are not limited to, discrete Fourier transform (DFT) functions, fast Fourier transform (FFT) functions, digital up converters, digital down converters, carrier recovery loops, and the like. Within digital up or digital down converters, for instance, the sinusoid is used as the local oscillator which drives the DSP function.

One technique for generating a high quality sinusoid involves storing sinusoid samples in a lookup table. A time-varying phase argument is generated using an overflow accumulator. The value obtained for the angle at a given point in time is used to index into the lookup table. Sample values can be read out of the lookup table according to the angle generated from the overflow accumulator over time to generate the sinusoid. A significant number of samples must be stored to generate a high quality sinusoid, e.g., one with low phase noise on the order of approximately greater than −120 dB. For example, in the typical case, the lookup table must be large enough to store several million samples. Storing such a large amount of data can be problematic for systems implemented within smaller devices, e.g., integrated circuits, where memory resources are limited.

Another technique for generating a high quality sinusoid is to utilize a recursive filter structure. While such structures do not require significant memory to store sinusoid samples, recursive filter structures suffer from stability issues. It is not theoretically possible to determine filter values, e.g. poles, which result in a stable system without an external amplitude stabilizing, (automatic gain control, AGC). AGC requires a high level of numerical accuracy which in real world systems is not easily accomplished.

SUMMARY OF THE INVENTION

The embodiments disclosed herein relate to direct digital synthesis (DDS) for the creation of high quality sinusoidal signals. One embodiment of the present invention can include a recursive DDS system including an accumulator module, a Coordinate Rotation Digital Computer (CORDIC) module coupled to the accumulator module, and an automatic gain control (AGC) module coupled to the CORDIC module. The CORDIC module can rotate a signal according to a desired rotation angle specified by the accumulator module. The AGC module can apply a level of gain to the rotated signal.

The accumulator module can include a sign bit removal (SGN) module that can determine a sign from a signal. The AGC module can dynamically control the level of gain applied to the rotated signal output from the CORDIC module. For example, the AGC module can adjust the level of gain according, at least in part, to an amplitude error and a pole position error.

The AGC module can include an AGC circuit receiving a first output signal and a second output signal of the CORDIC module. The AGC module can include a first multiplier receiving the first output signal of the CORDIC module and multiplying the first output signal according to the level of gain, as well as a second multiplier receiving the second output signal of the CORDIC module and multiplying the second output signal according to the level of gain. The level of gain, denoted as g, can be determined according to

The CORDIC module can include a butterfly structure receiving a butterfly error value. The butterfly error value can be initially set to 2−k, where k represents a number of rotations performed by the CORDIC module. The butterfly error value can be changed to a remainder angle of the accumulator module after a predetermined number of iterations of the CORDIC module.

Another embodiment of the present invention can include a programmable logic device including a recursive DDS. The recursive DDS can include an accumulator module, a CORDIC module coupled to the accumulator module, and an AGC module coupled to the CORDIC module. The CORDIC module can rotate a signal according to a desired rotation angle specified by the accumulator module. The automatic gain control module can apply a level of gain to the rotated signal. The recursive DDS can be implemented using programmable logic.

Yet another embodiment of the present invention can include a computer program product including a computer-usable medium having computer-usable program code that, when executed by an information processing system, can implement the structures disclosed herein within an integrated circuit.

DETAILED DESCRIPTION

The embodiments disclosed herein relate to direct digital synthesis (DDS) for the creation of high quality sinusoidal signals. More particularly, the embodiments relate to a stabilized, recursive DDS architecture. An automatic gain control (AGC) module can be utilized with a recursive filter structure, e.g., a recursive Coordinate Rotation Digital Computer (CORDIC) structure. The AGC module can dynamically adjust gain, e.g., increase, decrease, or provide unity gain, to the recursive DDS system output. Accordingly, a high quality sinusoid can be generated without the need for a large lookup table for storing sinusoid samples and without the stability issues typically found with conventional DDS implementations that utilize recursive filter structures.

The FIGURE is a block diagram illustrating a recursive, DDS system (system)100in accordance with one embodiment of the present invention. The system100can produce a high quality sinusoidal signal of a specified frequency. As shown, the system100can include an accumulator module105, a CORDIC module125, and an AGC module190.

The accumulator module105can be implemented as a phase accumulator. The accumulator module105can include an adder110, a delay115, as well as a sign bit removal (SGN) module120. The adder110can receive an input signal from a multiplier135which is part of the CORDIC module125to be described herein in greater detail. The adder110can receive a feedback signal taken from the output of delay115and add the feedback signal with the signal received from the multiplier135. The delay115can receive the signal output from the adder110and delay the signal by one sample. The output from the delay115can be provided to the SGN module120. The SGN module120can extract the sign bit from the signal received from delay115, e.g., the current value within the accumulator module105, and provide an output signal specifying the sign bit to the CORDIC module125.

The CORDIC module125can convert the phase output from the accumulator module105into a complex sinusoidal signal. The CORDIC module125can perform vector rotation where a signal denoted as [x(n−1), y(n−1)] can be rotated through an angle θ yielding a rotated vector [{circumflex over (x)}(n), ŷ(n)]. The CORDIC module125can implement the vector rotation as a sequence of successively smaller rotations, each of angle arctan(2−k), where k indicates the number of rotations to be performed. The CORDIC module125can be implemented as a recursive structure including multiple feedback paths. As shown, the CORDIC module125can include an arctangent (atan) table130, a butterfly structure192, a plurality of delays180and185, and a plurality of adders160and165.

The atan table130can store a plurality of values of arctan(2k), where k represents the number of rotations performed by the CORDIC module125. The atan table130can provide a value selected from the table as output to the multiplier135. The multiplier135can multiply the value obtained from the atan table130with a feedback signal that can be taken from the output of the accumulator module105, and more particularly, from the SGN module120.

The output signal from the SGN module120can be provided to the butterfly structure192of the CORDIC module125. The butterfly structure192can include the multipliers140,145,150, and155. The output signal from the SGN module120can be split and provided to each of multipliers140and145. Multiplier140can multiply the signal from the SGN module120with a feedback signal that is output from the delay180. The delay180can delay the signal xnby one sample to output signal xn-1, where n indicates a particular sample and, thus, a reference to a particular time. The signal that is output from multiplier140can be provided to multiplier155, which can multiply the received signal with a butterfly error value198. The signal that is output from multiplier155can be provided to adder165. Adder165can add the received signal with a feedback signal taken from the delay185to produce an output signal168, e.g., ŷn. The delay185can delay the signal ynby one sample to produce an output signal yn-1.

Similarly, the multiplier145can multiply the signal from SGN120with a feedback signal that is output from delay185(yn-1). The output signal from multiplier145can be provided to multiplier150, which can multiply the received signal with the butterfly error value198. The signal that is output from multiplier150can be provided to adder160. Adder160can add the received signal with the feedback signal taken from delay180(xn-1) to produce an output signal162, e.g., {circumflex over (x)}n.

The CORDIC module125implements a recursive filter structure. To achieve stability, the pole of a recursive filter must be located on the unit circle or within the unit circle. As is known, a pole located within the unit circle results in a sinusoid of decreasing amplitude. A pole located outside the unit circle produces a sinusoid of increasing amplitude. In either case, the amplitude of the complex sinusoid is, for each sample value, corrected back to unity by the AGC module. A theoretical value for a pole, which is a transcendental number, can be calculated such that the pole will be located on the unit circle. Since the value of the pole is calculated in a digital system using finite precision numbers, the resulting value for the pole will not place the pole precisely upon the unit circle. As the CORDIC module125iterates, the pole will likely migrate to locations within the unit circle, on the unit circle, and/or beyond the unit circle.

Within a conventional recursive DDS having a CORDIC module, signals162and168typically are provided as output after being modified by a cos(θk) multiplication operation. The cos(θk) multiplication operation serves to correct an amplitude error introduced into the system as a consequence of phase correction. The AGC module190can be positioned to process the output from the CORDIC module125. More particularly, the AGC module190can receive signal162and signal168. The AGC module190can dynamically adjust the amount of gain applied to each of signals162and168to generate signal172, e.g., xn, and signal178, e.g., yn, respectively.

The gain applied by the AGC module190can continually compensate for the pole value(s) being located off of the unit circle. Due to the inclusion of the AGC module190, the module that calculates the cos(θk) multiplication operation typically included within a recursive CORDIC module can be eliminated. The AGC module190can be configured to provide an amount of gain that accounts for the removed cos(θk) multiplication operation as well as for pole compensation.

The AGC module190can include an AGC circuit195which can receive rotated signals162and168. The AGC module190further can include multipliers170and175. The AGC circuit195can, responsive to receiving signals162and168, provide a gain signal to each of multipliers170and175. Accordingly, the CORDIC module125can output signal172from multiplier170which is signal162adjusted according to the gain signal from the AGC circuit195. The CORDIC module125further can output a signal178from multiplier175which is signal168adjusted by the gain signal from the AGC circuit195.

In general, input samples [x(n−1), y(n−1)] can be rotated by the CORDIC module125to produce rotated sample[{circumflex over (x)}(n), ŷ(n)]. The 2-tuple [{circumflex over (x)}(n), ŷ(n)] can be further processed by the AGC module190to produce gain corrected output sample [x(n), y(n)]. In operation, the delay115can be initialized with a value corresponding to −θ, where θ represents the desired rotation angle of the CORDIC module125. The CORDIC module125can perform a selected number of iterations, e.g., “k+1.” For purposes of illustration, the CORDIC module125can perform 10 binary shifts and additions of the ordered pair [x(n−1), y(n−1)], though any desired number of iterations can be performed. The CORDIC module125can iterate while trying to zero the content of the accumulator module105, e.g., the value loaded into delay115, by adding or subtracting selected angles stored in the atan table130. The butterfly error value198initially can be set to 2−k.

In one embodiment, the gain, denoted as g, of the AGC module190can be set to a value of 1 for the first “k” iterations, e.g., 9 iterations. At iteration k+1, e.g., iteration 10, the gain can be set to a value of 1/1.646759. The product of the cosine scale factors can be applied once at the end of the rotation cycle rather than one time per rotation. After iteration k+1, a non-zero residual angle θREMwill remain in the accumulator module105, e.g., the delay115. One additional rotation can be performed by replacing the butterfly error value198of 2−kwith the residual angle θREMfrom the accumulator module105.

Amplitude correction can be performed via the AGC module190. In determining the level of gain to be applied, it can be assumed that the rotation process results in an unknown amplitude increase ε relative to 1. This relationship can be expressed as: {circumflex over (x)}2(n)+ŷ2(n)={1+ε}, where {circumflex over (x)} represents the real portion and ŷ represents the imaginary portion of the vector [{circumflex over (x)}, ŷ]. It should be appreciated that signals162and168, taken collectively, define the vector [{circumflex over (x)}, ŷ], where signal162corresponds to the real ({circumflex over (x)}) portion and signal168corresponds to the imaginary (ŷ) portion.

The gain of the AGC module190can be applied to the output signals162and168which specify the final rotation to obtain gain adjusted final rotation signals172and178corresponding to [x(n), y(n)]. Applying the gain g to the above relationship provides: [{circumflex over (x)}2(n)+ŷ2(n)]g2={1+ε}g2=1. Solving for g, the relationships listed below can be determined.

Solving for ε using the above equations, the relationships listed below can be determined.
ε=[{circumflex over (x)}2(n)+ŷ2(n)]−1

⁢g=1-ɛ2=1-[x^2⁢(n)+y^2⁡(n)]-12g=3-[x^2⁡(n)+y^2⁡(n)]2
The AGC module190can apply gain signals having a level of gain g that can be calculated as shown above. The gain g can be applied to the output of the tan rotate and angle correction rotate to correct the amplitude error caused by the phase correction as well the amplitude increase or decrease due to the pole position error relative to the unit circle. Signals172and178output from the AGC module190define the resulting high quality sinusoidal signal from system100.

In one embodiment, for a fixed frequency sinusoid, the accumulator module105can be initialized with the same angle value for each successive time sample. Thus, the sequence of add-subtract iterations in the CORDIC module125can be identical for each computed trig sample. The memory of the CORDIC module125effectively resides in the filter states rather than in a traditional phase accumulator which forms and presents a sequence of phase angles modulo 2π to a CORDIC servo accumulator. Thus, the phase sequence is a constant for the recursive CORDIC module125. For example, the same angle error will always reside in the accumulator module105.

In consequence, there is no line structure in the spectrum of the recursive CORDIC structure disclosed herein. Further, the phase error correction is not applied to suppress phase error artifacts, but rather to complete the phase rotation left incomplete due to the residual phase term in the accumulator module105.

Quantizers between the summing junction feeding the CORDIC registers and the registers are included. The truncation circulates in the registers and contributes a DC term thereby causing a spectral line for the complex sinusoid. This DC term can be suppressed by using a sigma delta feedback loop to feedback the truncated segments of the sums.

The embodiments disclosed herein can be implemented as a plurality of discrete components or within an integrated circuit. In one embodiment, for example, the embodiments can be implemented within a programmable logic device such as a field programmable gate array. The circuit structures disclosed herein can be implemented using programmable logic of the programmable logic device or field programmable gate array as the case may be. It should be appreciated, however, that the embodiments disclosed herein are not intended to be limited to any one type of device for implementation.

In another embodiment, the system disclosed herein can be specified in programmatic form. For example, the system can be implemented as a predeveloped block known as a macro. The macro may exist within a macro library available within or included as part of an electronic design automation (EDA) tool. The macro may be specified as a netlist, using a hardware description language, or in other computer-readable form. The macro, when incorporated into a circuit design, can be processed by the EDA tool and transformed into a bitstream. The bitstream, when loaded into a target PLD, can configure the target device to implement the structures described herein.

Embodiments of the present invention further can be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein. The computer program product can include a computer-usable or computer-readable medium having computer-usable program code which, when loaded in a computer system, causes the computer system to perform the functions described herein or configure logic that implements the various circuit structures disclosed herein. Examples of computer-usable or computer-readable media can include, but are not limited to, optical media, magnetic media, magneto-optical media, computer memory, one or more portions of a wired or wireless network through which computer-usable program code can be propagated, or the like.

The terms “computer program,” “software,” “application,” “computer-usable program code,” variants and/or combinations thereof, in the present context, mean any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form. For example, a computer program can include, but is not limited to, a bitstream, a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system.

The terms “a” and “an,” as used herein, are defined as one or more than one. The term “plurality,” as used herein, is defined as two or more than two. The term “another,” as used herein, is defined as at least a second or more. The terms “including” and/or “having,” as used herein, are defined as comprising, i.e., open language. The term “coupled,” as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically, e.g., communicatively linked through a communication channel or pathway or another component or system.