Constructing persistent file system from scattered persistent regions

Methods and apparatus related to constructing a persistent file system from scattered persistent regions are described. In one embodiment, stored information in a storage unit corresponds to one or more persistent memory regions that are scattered amongst one or more non-volatile memory devices. The one or more persistent memory regions are byte addressable. Also, the one or more persistent memory regions are used to form a virtual contiguous region. Other embodiments are also disclosed and claimed.

FIELD

The present disclosure generally relates to the field of electronics. More particularly, some embodiments of the invention generally relate to constructing a persistent file system from scattered persistent regions.

BACKGROUND

Generally, memory used to store data in a computing system can be volatile (to store volatile information) or non-volatile (to store persistent information). Volatile data structures stored in volatile memory are generally used for temporary or intermediate information that is required to support the functionality of a program during the run-time of the program. On the other hand, persistent data structures stored in non-volatile memory are available beyond the run-time of a program and can be reused. Moreover, new data is typically generated as volatile data first, before the user or programmer decides to make the data persistent. For example, programmers or users may cause mapping (i.e., instantiating) of volatile structures in volatile main memory that is directly accessible by a processor. Persistent data structures, on the other hand, are instantiated on non-volatile storage devices like rotating disks attached to Input/Output (I/O or IO) buses or non-volatile memory based devices like flash memory.

As processing capabilities are enhanced in processors, one concern is the speed at which memory may be accessed by a processor. For example, to process data, a processor may need to first fetch data from a memory. After completion of the data processing, the results may need to be stored in the memory. Therefore, the memory speed can have a direct effect on overall system performance.

Another important consideration is power consumption. For example, in mobile computing devices that rely on battery power, it is very important to reduce power consumption to allow for the device to operate while mobile. Power consumption is also important for non-mobile computing devices as excess power consumption may increase costs (e.g., due to additional power usage, increasing cooling requirements, etc.), shorten component life, limit locations at which a device may be used, etc.

Hard disk drives provide a relatively low-cost storage solution and are used in many computing devices to provide non-volatile storage. Disk drives however use a lot of power when compared to flash memory since a disk drive needs to spin its disks at a relatively high speed and move disk heads relative to the spinning disks to read/write data. All this physical movement generates heat and increases power consumption. To this end, some higher end mobile devices are migrating towards flash memory devices that are non-volatile.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, various embodiments of the invention may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments of the invention. Further, various aspects of embodiments of the invention may be performed using various means, such as integrated semiconductor circuits (“hardware”), computer-readable instructions organized into one or more programs (“software”), or some combination of hardware and software. For the purposes of this disclosure reference to “logic” shall mean either hardware, software, firmware, or some combination thereof.

Some embodiments provide techniques for constructing a persistent file system from scattered persistent regions, e.g., on Non-Volatile Memory (NVM) devices. An embodiment provides a solution for platforms that support byte addressable persistent (i.e., non-volatile) memory (e.g., based on 3D (3-Dimentional Cross Point Memory such as Phase Change Memory (PCM) technology or a device based on any other non-volatile memory technology), allowing accessibility to the storage class memory via the memory bus. Generally, byte addressability of the NVM refers to accessibility of individual bytes of the NVM, e.g., directly by a processor or processor core (or other components of a computing system such as the components discussed with reference toFIGS. 1 and 5-7). Furthermore, accessibility of persistent memory via the memory bus may co-exist with traditional DRAM (Dynamic Random Access Memory) based volatile memory.

In various embodiments, the NVM devices discussed herein include flash memory, Spin Torque Transfer Random Access Memory (STTRAM), Resistive Random Access Memory, 3D (3-Dimensional) Cross Point Memory such as Phase Change Memory (PCM), etc.

Furthermore, the physically addressable persistent memory region(s) may have multiple segments scattered within a platform's physical address range. The order in which these persistent memory segments are exposed to the OS (Operating System), e.g., by the BIOS (Basic Input/Output System), may change from system boot to system boot due to addition and/or removal of DRAM memory and/or other configuration changes to memory in general. In order for the OS to reconstruct the persistent data stored on these scattered persistent segments, the segments themselves need to be mapped in proper and correct order by the OS. To this end, some embodiments communicate information to the OS regarding the scattered regions of persistent memory (e.g., via the BIOS) and may also help the OS to reconstruct a contiguous region from the (e.g., randomly ordered) scattered persistent regions without losing the persistent data. The OS may in turn utilize the information regarding the contiguous persistent region (i.e., no matter how these scattered persistent regions are reported to OS by the BIOS) to construct the persistent file system data. Another embodiment applies to building persistent non-volatile system data to construct memory block device.

Moreover, the memory techniques discussed herein may be provided in various computing systems (e.g., including smart phones, tablets, portable game consoles, Ultra-Mobile Personal Computers (UMPCs), etc.), such as those discussed with reference toFIGS. 1-7. More particularly,FIG. 1illustrates a block diagram of a computing system100, according to an embodiment of the invention. The system100includes one or more processors102-1through102-N (generally referred to herein as “processors102” or “processor102”). The processors102may communicate via an interconnection or bus104. Each processor may include various components some of which are only discussed with reference to processor102-1for clarity. Accordingly, each of the remaining processors102-2through102-N may include the same or similar components discussed with reference to the processor102-1.

In an embodiment, the processor102-1may include one or more processor cores106-1through106-M (referred to herein as “cores106,” or more generally as “core106”), a cache108(which may be a shared cache or a private cache in various embodiments), and/or a router110. The processor cores106may be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and/or private caches (such as cache108), buses or interconnections (such as a bus or interconnection112), logic120, logic150, memory controllers (such as those discussed with reference toFIGS. 5 and 6), NVM152, or other components.

In one embodiment, the router110may be used to communicate between various components of the processor102-1and/or system100. Moreover, the processor102-1may include more than one router110. Furthermore, the multitude of routers110may be in communication to enable data routing between various components inside or outside of the processor102-1.

The cache108may store data (e.g., including instructions) that are utilized by one or more components of the processor102-1, such as the cores106. For example, the cache108may locally cache data stored in a volatile memory114for faster access by the components of the processor102. As shown inFIG. 1, the memory114may be in communication with the processors102via the interconnection104. In an embodiment, the cache108(that may be shared) may have various levels, for example, the cache108may be a mid-level cache and/or a last-level cache (LLC). Also, each of the cores106may include a level 1 (L1) cache (116-1) (generally referred to herein as “L1 cache116”). Various components of the processor102-1may communicate with the cache108directly, through a bus (e.g., the bus112), and/or a memory controller or hub.

As shown inFIG. 1, memory114may be coupled to other components of system100through a volatile memory controller120. System100also includes NVM memory controller logic150to couple NVM memory152to various components of the system100. Memory152includes non-volatile memory such as flash memory, STTRAM, Resistive Random Access Memory, 3D Cross Point Memory such as PCM, etc. in some embodiments. Even though the memory controller150is shown to be coupled between the interconnection104and the memory152, the logic150may be located elsewhere in system100. For example, logic150(or portions of it) may be provided within one of the processors102, controller120, etc. in various embodiments. Moreover, logic150controls access to one or more NVM devices152(e.g., where the one or more NVM devices are provided on the same integrated circuit die in some embodiments), as discussed herein with respect to various embodiments.

Furthermore, some embodiments help reconstruct the persistent data residing on scattered persistent 3D Cross Point Memory devices (e.g., DIMMs (Dual In-line Memory Modules) by the operating system and have one or more of the following three components: (1) the BIOS describing the scattered persistent regions to OS; (2) the OS initializing the scattered regions with hidden markers and mapping them for the first time; and/or (3) the OS reconstructing a contiguous persistent region on successive reboots.

As for item (1) above (i.e., the BIOS to describing the scattered persistent regions to OS), an embodiment utilizes a platform BIOS that provides the ability to partition the (e.g., 3D Cross Point Memory based) persistent memory into volatile (e.g., with DRAM as cache, a.k.a. 2LM (two Level system main Memory)) and non-volatile (e.g., persistent memory) regions. Users who wish to have the persistent memory usage may enter the BIOS utility and specify the intended size of this persistent memory. The platform BIOS may satisfy these users' options by carving out the specified size (either contiguous or scattered region) from the installed (e.g., 3D Cross Point Memory based) persistent memory. Furthermore, during boot, the platform BIOS can describe the carved out region of persistent memory (also referred to herein as “$NVM”) to the OS via Advanced Configuration and Power Interface (ACPI) tables (which may be in accordance with ACPI Specification, Revision 5.0, December 2011). Table 1 below illustrates some sample values for such an ACPI table in accordance with an embodiment. Of course, other values may be utilized depending on the implementation.

The above $NVM region table describes an $NVM base address and the $NVM length. Based on the $NVM region Table length field at offset 4, OS can determine the number of $NVM regions described by the BIOS. Bit0of the flags field at offset 0x34 conveys the persistent nature of the memory. The above base address, length, and flags may be provided for each persistent memory region which indicates whether a given persistent memory region has a persistent mode, an optimized block mode, or an emulated block mode.

Regarding item (2) above (i.e., the OS initializing scattered regions with hidden markers and mapping them for the first time), the persistent memory region is used to construct a file system (such as a pmfs file system, where “pmfs” refers to a byte addressable persistent storage class memory file system). In an embodiment, creation of a file system for the first time on a persistent memory can be performed in response to a special parameter (e.g., Boolean “init=1” that may accompany or be associated with a “mount” command for the storage device) to cause mounting of the persistent file system.

One example of such a mount command may be “mount—t pmfs init=1 none/mnt/$NVM” in an embodiment. Such command line parameters (e.g., “init=1” that is passed in the mount command line) may be in turn passed to the pmfs file system registered mount function callback by the OS. Hence, some embodiments parse the command line parameters, and if the parameter passed is found to be “init=1” then the pmfs file system is constructed from the scattered persistent memory for the first time as described below.

FIGS. 2-3illustrate block diagrams of scattered memory regions, according to some embodiments. When the file system is constructed for the first time (e.g. with the “init=1” passed in the command line of mount command), the pmfs file system driver's mount function callback is called with $NVM regions as reported by the BIOS. In this callback function, for each of the reported $NVM regions, a page may be hidden at the beginning and end of the region as shown inFIG. 2. In each of the above regions, a page that is hidden at the beginning of the region (i.e., on the left side of the region) is called “SegmentPageRegionBegin” and a page that is hidden at the end of each region (i.e., on the right side of the region) is called “SegmentPageRegionEnd”. For simplicity of discussion, only three $NVM persistent regions are shown with each of the regions having “SegmentPageRegionBegin” and “SegmentPageRegionEnd”.

Moreover, the mount callback function of the pmfs file system will tag the “SegmentPageRegionEnd” of $NVM region1and the “SegmentPageRegionBegin” of $NVM region2with the same tag, and so on. For simplicity inFIG. 2, this is marked as “1”. Similarly, for all of the hidden “SegmentPageRegions{Begin|End}” pages, tagging is constructed so that this data is used currently (and in subsequent boots) to construct the ordered $NVM regions for the OS usage. This ordered $NVM region described (constructed from the tagging information minus hidden “SegmentPageRegionXXX”) is then mapped into contiguous virtual memory on top of which the pmfs file system is constructed.

Regarding item (3) above (i.e., the OS reconstructing contiguous region on successive boots), once the file system is built on the persistent (e.g., 3D CROSS POINT MEMORY such as PCM) memory as explained above, it is possible for the OS to have created some files on this storage class memory. The next time OS is booted, it is expected that the file system be intact and hold all the persistent data/files that were created in the previous boot. As explained before, it is possible for BIOS to reorder these $NVM regions due to various reasons such as addition, deletion of other volatile memory, and/or change in some memory configurations.FIG. 3shows one such re-ordered $NVM regions and shows how OS can reconstruct the contiguous persistent region.

Moreover, inFIG. 3, BIOS is describing $NVM Region3, $NVM Region1and $NVM Region2in order as opposed to previous boot's order of $NVM Region1, $NVM Region2, and $NVM Region3(shown inFIG. 2). As mentioned above, a hidden marker exists at the beginning and end of each $NVM segment region called “SegmentPageRegionBegin” and “SegmentPageRegionEnd”, respectively which hold the tag information that is used to construct the previous order.

In our case of persistent file systems, during mount callback of the pmfs file system, the $NVM regions are detected/determined as reported to OS by the BIOS by walking the $NVM region table. For each of the regions, “SegmentPageRegionBegin” and “SegmentPageRegionEnd” are considered and mapping the tag values are started to construct the ordered $NVM segments. Once the ordered segments are obtained, this ordered segments are mapped to form the contiguous persistent memory region which is subsequently presented to the file system.

One embodiment may include additional information in the SegmentPageRegion{Begin|End} fields. For simplicity,FIGS. 2-3show the SegmentPageRegion{Begin|End} to include tagging values, but other information such as physical DIMM UUID (Universally Unique Identifier), row, column bank, a checksum, etc. may also be included in the SegmentPageRegion{Begin|End} fields.

In accordance with one embodiment, each of the $NVM regions include a (e.g., hidden) page at the beginning of the region (“SegmentPageRegionStart”) and another (e.g., hidden) page at the end of the region (“SegmentPageRegionEnd”). During the first time construction of the persistent file system, the tagging/marker on these SegmentPageRegions are initialized such that the adjacent SegmentPage marker shares the same tag value (see, e.g.,FIG. 2). During the next successive reboots, OS uses these markers/tagging to reconstruct the correct order of segments and to construct the contiguous virtual region which is then presented to file system layer for its file system consistency checks, etc.

Moreover, in some current kernel designs, one has to hide the memory from the OS via kernel command line option(s) and remember this address and use it to create a file system or a RAM disk. By contrast, some embodiments provide BIOS options and an ACPI-based method to report to OS about the persistent regions of memory and allow for a way for the OS to reorder these scattered persistent segments to render the previously stored data usable.

FIG. 4illustrates a flow diagram of a method400to construct a persistent file system from scattered persistent region, according to an embodiment. In various embodiments, one or more operations of method400can be performed by one or more components discussed with reference to the other figures.

Referring toFIG. 4, after an operation402(e.g., at system power-on), a user can enter the BIOS setup option/utility by pressing a special key (such as F2) at operation404. Once the BIOS setup option is invoked, the user can create a persistent memory region at operation406with the desired size and save the configuration and continue to boot the OS. The BIOS in turn presents the OS with information about the $NVM region at operation408, e.g., via the ACPI $NVM region table that describes the multiple $NVM regions detailing the desired size of persistent memory. At the start of the file system mount (e.g., if the init=1 option is passed to file system at operation410), the file system reconstructs the tagging information for the hidden SegmentPageRegion{Begin|End} at operation412. If the init=1 is not passed at operation410, then the system tries to construct the correct order of the $NVM segments from the tagging information available from the hidden SegmentPageRegion{Begin|End}. Once the system correctly orders the $NVM region at operation414, a contiguous virtual region is established using OS memory map techniques from the physically scattered persistent memory regions at operation416. At operation418, this virtually contiguous region of persistent memory is used for file system to present the persistent data to the OS and/or software applications.

Accordingly, the tagging information in the SegmentPageRegionBegin and SegmentPageRegionEnd fields are not only useful for constructing the ordered segments but are also helpful to know if any segments are missing, e.g., as a result of hot or erroneous removal of the persistent memory module(s).

FIG. 5illustrates a block diagram of a computing system500in accordance with an embodiment of the invention. The computing system500may include one or more central processing unit(s) (CPUs)502or processors that communicate via an interconnection network (or bus)504. The processors502may include a general purpose processor, a network processor (that processes data communicated over a computer network503), an application processor (such as those used in cell phones, smart phones, etc.), or other types of a processor (including a reduced instruction set computer (RISC) processor or a complex instruction set computer (CISC)). Various types of computer networks503may be utilized including wired (e.g., Ethernet, Gigabit, Fiber, etc.) or wireless networks (such as cellular, 3G (Third-Generation Cell-Phone Technology or 3rd Generation Wireless Format (UWCC)), 5G, Low Power Embedded (LPE), etc.). Moreover, the processors502may have a single or multiple core design. The processors502with a multiple core design may integrate different types of processor cores on the same integrated circuit (IC) die. Also, the processors502with a multiple core design may be implemented as symmetrical or asymmetrical multiprocessors.

In an embodiment, one or more of the processors502may be the same or similar to the processors102ofFIG. 1. For example, one or more of the processors502may include one or more of the cores106and/or cache108. Also, the operations discussed with reference toFIGS. 1-4may be performed by one or more components of the system500.

A chipset506may also communicate with the interconnection network504. The chipset506may include a graphics and memory control hub (GMCH)508. The GMCH508may include a memory controller510(which may be the same or similar to the memory controller120ofFIG. 1in an embodiment) that communicates with the memory114. System500may also include logic150(e.g., coupled to NVM152) in various locations (such as those shown inFIG. 5but can be in other locations within system500(not shown)). The memory114may store data, including sequences of instructions that are executed by the CPU502, or any other device included in the computing system500. In one embodiment of the invention, the memory114may include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or other types of storage devices. Nonvolatile memory may also be utilized such as a hard disk, flash, 3D Cross Point Memory (such as PCM), Resistive Random Access Memory, and STTRAM. Additional devices may communicate via the interconnection network504, such as multiple CPUs and/or multiple system memories.

The GMCH508may also include a graphics interface514that communicates with a graphics accelerator516. In one embodiment of the invention, the graphics interface514may communicate with the graphics accelerator516via an accelerated graphics port (AGP). In an embodiment of the invention, a display517(such as a flat panel display, touch screen, etc.) may communicate with the graphics interface514through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by the display. The display signals produced by the display device may pass through various control devices before being interpreted by and subsequently displayed on the display517.

A hub interface518may allow the GMCH508and an input/output control hub (ICH)520to communicate. The ICH520may provide an interface to I/O devices that communicate with the computing system500. The ICH520may communicate with a bus522through a peripheral bridge (or controller)524, such as a peripheral component interconnect (PCI) bridge, a universal serial bus (USB) controller, or other types of peripheral bridges or controllers. The bridge524may provide a data path between the CPU502and peripheral devices. Other types of topologies may be utilized. Also, multiple buses may communicate with the ICH520, e.g., through multiple bridges or controllers. Moreover, other peripherals in communication with the ICH520may include, in various embodiments of the invention, integrated drive electronics (IDE) or small computer system interface (SCSI) hard drive(s), USB port(s), a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), or other devices.

The bus522may communicate with an audio device526, one or more disk drive(s)528, and a network interface device530(which is in communication with the computer network503, e.g., via a wired or wireless interface). As shown, the network interface device530may be coupled to an antenna531to wirelessly (e.g., via an Institute of Electrical and Electronics Engineers (IEEE) 802.11 interface (including IEEE 802.11a/b/g/n, etc.), cellular interface, 3G, 5G, LPE, etc.) communicate with the network503. Other devices may communicate via the bus522. Also, various components (such as the network interface device530) may communicate with the GMCH508in some embodiments of the invention. In addition, the processor502and the GMCH508may be combined to form a single chip. Furthermore, the graphics accelerator516may be included within the GMCH508in other embodiments of the invention.

Furthermore, the computing system500may include volatile and/or nonvolatile memory (or storage). For example, nonvolatile memory may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a disk drive (e.g.,528), a floppy disk, a compact disk ROM (CD-ROM), a digital versatile disk (DVD), flash memory, a magneto-optical disk, or other types of nonvolatile machine-readable media that are capable of storing electronic data (e.g., including instructions).

FIG. 6illustrates a computing system600that is arranged in a point-to-point (PtP) configuration, according to an embodiment of the invention. In particular,FIG. 6shows a system where processors, memory, and input/output devices are interconnected by a number of point-to-point interfaces. The operations discussed with reference toFIGS. 1-5may be performed by one or more components of the system600.

As illustrated inFIG. 6, the system600may include several processors, of which only two, processors602and604are shown for clarity. The processors602and604may each include a local memory controller hub (MCH)606and608to enable communication with memories610and612. The memories610and/or612may store various data such as those discussed with reference to the memory114or NVM152ofFIGS. 1 and/or 5. Also, MCH606and608may include the memory controller120and/or logic150ofFIG. 1in some embodiments.

In an embodiment, the processors602and604may be one of the processors502discussed with reference toFIG. 5. The processors602and604may exchange data via a point-to-point (PtP) interface614using PtP interface circuits616and618, respectively. Also, the processors602and604may each exchange data with a chipset620via individual PtP interfaces622and624using point-to-point interface circuits626,628,630, and632. The chipset620may further exchange data with a high-performance graphics circuit634via a high-performance graphics interface636, e.g., using a PtP interface circuit637. As discussed with reference toFIG. 5, the graphics interface636may be coupled to a display device (e.g., display517) in some embodiments.

As shown inFIG. 6, one or more of the cores106and/or cache108ofFIG. 1may be located within the processors602and604. Other embodiments of the invention, however, may exist in other circuits, logic units, or devices within the system600ofFIG. 6. Furthermore, other embodiments of the invention may be distributed throughout several circuits, logic units, or devices illustrated inFIG. 6.

The chipset620may communicate with a bus640using a PtP interface circuit641. The bus640may have one or more devices that communicate with it, such as a bus bridge642and I/O devices643. Via a bus644, the bus bridge642may communicate with other devices such as a keyboard/mouse645, communication devices646(such as modems, network interface devices, or other communication devices that may communicate with the computer network503, as discussed with reference to network interface device530for example, including via antenna531), audio I/O device, and/or a data storage device648. The data storage device648may store code649that may be executed by the processors602and/or604.

In some embodiments, one or more of the components discussed herein can be embodied as a System On Chip (SOC) device.FIG. 7illustrates a block diagram of an SOC package in accordance with an embodiment. As illustrated inFIG. 7, SOC702includes one or more Central Processing Unit (CPU) cores720, one or more Graphics Processor Unit (GPU) cores730, an Input/Output (I/O) interface740, and a memory controller742. Various components of the SOC package702may be coupled to an interconnect or bus such as discussed herein with reference to the other figures. Also, the SOC package702may include more or less components, such as those discussed herein with reference to the other figures. Further, each component of the SOC package720may include one or more other components, e.g., as discussed with reference to the other figures herein. In one embodiment, SOC package702(and its components) is provided on one or more Integrated Circuit (IC) die, e.g., which are packaged onto a single semiconductor device.

As illustrated inFIG. 7, SOC package702is coupled to a memory760(which may be similar to or the same as memory discussed herein with reference to the other figures) via the memory controller742. In an embodiment, the memory760(or a portion of it) can be integrated on the SOC package702.

The I/O interface740may be coupled to one or more I/O devices770, e.g., via an interconnect and/or bus such as discussed herein with reference to other figures. I/O device(s)770may include one or more of a keyboard, a mouse, a touchpad, a display, an image/video capture device (such as a camera or camcorder/video recorder), a touch screen, a speaker, or the like. Furthermore, SOC package702may include/integrate the logic150in an embodiment. Alternatively, the logic150may be provided outside of the SOC package702(i.e., as a discrete logic).

The following examples pertain to further embodiments. Example 1 includes an apparatus comprising: a storage unit to store information corresponding to one or more persistent memory regions that are scattered amongst one or more non-volatile memory devices, wherein the one or more persistent memory regions are byte addressable and wherein the one or more persistent memory regions are to form a virtual contiguous region. Example 2 includes the apparatus of example 1, comprising logic to form the virtual contiguous region from the one or more persistent memory regions based on a plurality of tags. Example 3 includes the apparatus of example 1, wherein the storage unit is to store the information in a table in accordance with Advanced Configuration and Power Interface (ACPI). Example 4 includes the apparatus of example 1, wherein a Basic Input Output System (BIOS) is to describe the one or more persistent memory regions to an Operating System (OS) via the stored information. Example 5 includes the apparatus of example 4, comprising logic to allow the OS to initialize the one or more persistent memory regions with a plurality of tags. Example 6 includes the apparatus of example 5, comprising logic to allow the OS to reconstruct the virtual contiguous region. Example 7 includes the apparatus of example 1, wherein the stored information is to comprise one or more of: header signature, length, revision, checksum, Original Equipment Manufacturer (OEM) Identifier (ID), OEM table ID, OEM revision, creator ID, creator revision, persistent memory region base address, persistent memory region length, and one or more persistent memory region flags. Example 8 includes the apparatus of example 1, wherein the stored information is to comprise one or more persistent memory region base addresses, persistent memory region lengths, and one or more persistent memory region flags to indicate whether a persistent memory region has a persistent mode, an optimized block mode, or an emulated block mode. Example 9 includes the apparatus of example 1, wherein the one or more non-volatile memory devices are to comprise one or more of: flash memory, Phase Change Memory (PCM), 3D (3-Dimensional) Cross Point Memory, Resistive Random Access Memory, and Spin Torque Transfer Random Access Memory (STTRAM). Example 10 includes the apparatus of example 1, wherein the one or more non-volatile memory devices are on a same integrated circuit die. Example 11 includes the apparatus of example 1, wherein one or more of a controller logic, a memory, the one or more non-volatile memory devices, and a processor core are on a same integrated circuit die. Example 12 includes the apparatus of example 11, wherein a memory controller is to comprise the controller logic.

Example 13 includes method comprising: storing information in a storage unit, wherein the stored information corresponds to one or more persistent memory regions that are scattered amongst one or more non-volatile memory devices, wherein the one or more persistent memory regions are byte addressable, wherein the one or more persistent memory regions are to form a virtual contiguous region. Example 14 includes the method of example 13, further comprising forming the virtual contiguous region from the one or more persistent memory regions based on a plurality of tags. Example 15 includes the method of example 13, further comprising the storage unit storing the information in a table in accordance with Advanced Configuration and Power Interface (ACPI). Example 16 includes the method of example 13, further comprising describing the one or more persistent memory regions to an Operating System (OS) via the stored information. Example 17 includes the method of example 16, further comprising the OS causing initialization of the one or more persistent memory regions with a plurality of tags. Example 18 includes the method of example 16, further comprising the OS causing reconstruction of the virtual contiguous region. Example 19 includes the method of example 13, wherein the one or more non-volatile memory devices comprise one or more of: flash memory, Phase Change Memory (PCM), 3D Cross Point Memory, Resistive Random Access Memory, and Spin Torque Transfer Random Access Memory (STTRAM).

Example 20 includes a system comprising: one or more non-volatile memory devices; a processor to access data stored on the one or more non-volatile memory devices via controller logic; the controller logic to control access to the one or more non-volatile memory devices; a storage unit to store information corresponding to one or more persistent memory regions that are scattered amongst the one or more non-volatile memory devices, wherein the one or more persistent memory regions are byte addressable and wherein the one or more persistent memory regions are to form a virtual contiguous region. Example 21 includes the system of example 20, wherein the one or more non-volatile memory devices are to comprise one or more of: flash memory, Phase Change Memory (PCM), 3D Cross Point Memory, Resistive Random Access Memory, and Spin Torque Transfer Random Access Memory (STTRAM). Example 22 includes the system of example 20, comprising logic to form the virtual contiguous region from the one or more persistent memory regions based on a plurality of tags. Example 23 includes the system of example 20, wherein the storage unit is to store the information in a table in accordance with Advanced Configuration and Power Interface (ACPI). Example 24 includes the system of example 20, wherein a Basic Input Output System (BIOS) is to describe the one or more persistent memory regions to an Operating System (OS) via the stored information. Example 25 includes the system of example 20, wherein the stored information is to comprise one or more persistent memory region base addresses, persistent memory region lengths, and one or more persistent memory region flags to indicate whether a persistent memory region has a persistent mode, an optimized block mode, or an emulated block mode.

Example 26 includes an apparatus comprising: means for accessing one or more non-volatile memory devices; and means for storing information in a storage unit, wherein the stored information corresponds to one or more persistent memory regions that are scattered amongst one or more non-volatile memory devices, wherein the one or more persistent memory regions are byte addressable, wherein the one or more persistent memory regions are to form a virtual contiguous region. Example 27 includes the apparatus of example 26, further comprising means for forming the virtual contiguous region from the one or more persistent memory regions based on a plurality of tags. Example 28 includes the apparatus of example 26, further comprising means for storing the information in a table in accordance with Advanced Configuration and Power Interface (ACPI). Example 29 includes the apparatus of example 26, further comprising means for describing the one or more persistent memory regions to an Operating System (OS) via the stored information. Example 30 includes the apparatus of example 26, further comprising means for causing initialization of the one or more persistent memory regions with a plurality of tags. Example 31 includes the apparatus of example 26, further comprising means for causing reconstruction of the virtual contiguous region. Example 32 includes the apparatus of example 26, wherein the one or more non-volatile memory devices comprise one or more of: flash memory, Phase Change Memory (PCM), 3D Cross Point Memory, Resistive Random Access Memory, and Spin Torque Transfer Random Access Memory (STTRAM).

Example 33 includes a computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations of any of examples 13 to 19.

Additionally, such tangible computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals (such as in a carrier wave or other propagation medium) via a communication link (e.g., a bus, a modem, or a network connection).

Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.