ARRAY SUBSTRATE AND DISPLAY PANEL

The present application provides an array substrate and a display panel; the array substrate includes a display unit and a light sensing unit. A first electrode plate and a second electrode plate of a first capacitor of the light sensing unit are both transparent electrode plates, the first electrode plate is formed from a newly-added transparent conductive layer, the second electrode plate is served by a common electrode of the display unit, and the display unit and the light sensing unit work alternately in time-division within a time period of one frame to alleviate a problem of low aperture ratio in an existing display panel.

FIELD OF INVENTION

The present application relates to the field of display technology, and in particular to an array substrate and a display panel.

BACKGROUND

With development of display technology, remote interaction technology that integrates a light control sensor into a display panel and uses a laser as a control source has attracted people's attention. The light control sensor mainly includes a light-sensitive thin film transistor (TFT), a storage capacitor, etc. The light-sensitive thin film transistor generates a photocurrent after being exposed to light, and a storage capacitor is used to temporarily store an amount of electricity generated by the light-sensitive thin film transistor after the exposure. A size of the storage capacitor needs to be matched with the changed amount of electricity, and in order to match this amount of electricity, an area of the storage capacitor needs to be made relatively large. Meanwhile, due to opacity of the storage capacitor, a larger storage capacitor occupies a larger display area, which reduces an aperture ratio of the display panel.

Therefore, there is a need to solve the technical problem of low aperture ratio of the existing display panel.

SUMMARY OF INVENTION

Technical Problem

The present application provides an array substrate and a display panel to alleviate the technical problem of low aperture ratio in the existing display panel.

Technical Solution

In order to solve the above problem, the technical solutions provided by the present application are as follows:

An embodiment of the present application provides an array substrate, which includes a base substrate and a pixel circuit disposed on the base substrate, wherein the pixel circuit includes a driving circuit and a light sensing circuit, and the light sensing circuit includes a first transistor, a second transistor, and a first capacitor,wherein a gate of the first transistor is connected to a first control signal line, a first electrode of the first transistor is connected to a first power line, and a second electrode of the first transistor is connected to a first electrode of the second transistor;wherein the first capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is connected to the second electrode of the first transistor and the first electrode of the second transistor, and the second electrode plate is connected to a common voltage signal line; andwherein the first electrode plate and the second electrode plate are both transparent electrode plates, and the driving circuit and the light sensing circuit share the common voltage signal line.

In the array substrate provided by an embodiment of the present application, the light sensing circuit further includes a readout circuit, a second electrode of the second transistor is connected to the readout circuit, and a gate of the second transistor is connected to a second control signal line.

In the array substrate provided by an embodiment of the present application, the array substrate further includes a light sensing unit, the light sensing circuit is disposed in the light sensing unit, the first transistor and the second transistor are disposed in a same level, and the first capacitor is disposed at a side of the first transistor and the second transistor away from the base substrate.

In the array substrate provided by an embodiment of the present application, the array substrate further includes:a first inorganic layer disposed on the side of the first transistor and the second transistor away from the base substrate;a second inorganic layer disposed on a side of the first inorganic layer away from the first transistor and located between the first electrode plate and the second electrode plate.

In the array substrate provided by an embodiment of the present application, the array substrate further includes a display unit, the driving circuit is disposed in the display unit, and the display unit includes:a third transistor disposed in the same level as the first transistor;a pixel electrode disposed in a same level as the first electrode plate or the second electrode plate; anda common electrode also serving as the second electrode plate.

In the array substrate provided by an embodiment of the present application, the first electrode plate is disposed on the first inorganic layer, and the second electrode plate is disposed on the second inorganic layer.

In the array substrate provided by an embodiment of the present application, the second electrode plate is disposed on the first inorganic layer, and the first electrode plate is disposed on the second inorganic layer.

In the array substrate provided by an embodiment of the present application, the first electrode plate, the common electrode, and the pixel electrode are made of a same material.

In the array substrate provided by an embodiment of the present application, the array substrate further includes a display unit, the driving circuit is disposed in the display unit, and the display unit includes:a third transistor disposed in the same level as the first transistor;a pixel electrode disposed above the third transistor and electrically connected to the third transistor; anda common electrode also serving as the second electrode plate,wherein the pixel electrode is disposed in a level different from the first electrode plate and the second electrode plate.

In the array substrate provided by an embodiment of the present application, the common voltage signal line and the gate of the first transistor are disposed in a same level.

Another embodiment of the present application also provides a display panel, which includes an array substrate, the array substrate includes a base substrate and a pixel circuit disposed on the base substrate, the pixel circuit includes a driving circuit and a light sensing circuit, and the light sensing circuit includes a first transistor, a second transistor, and a first capacitor,wherein a gate of the first transistor is connected to a first control signal line, a first electrode of the first transistor is connected to a first power line, and a second electrode of the first transistor is connected to a first electrode of the second transistor;wherein the first capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is connected to the second electrode of the first transistor and the first electrode of the second transistor, and the second electrode plate is connected to a common voltage signal line; andwherein the first electrode plate and the second electrode plate are both transparent electrode plates, and the driving circuit and the light sensing circuit share the common voltage signal line.

In the display panel provided by the embodiment of the present application, the light sensing circuit further includes a readout circuit, a second electrode of the second transistor is connected to the readout circuit, and a gate of the second transistor is connected to a second control signal line.

In the display panel provided by the embodiment of the present application, the array substrate further includes a light sensing unit, the light sensing circuit is disposed in the light sensing unit, the first transistor and the second transistor are disposed in a same level, and the first capacitor is disposed at a side of the first transistor and the second transistor away from the base substrate.

In the display panel provided by the embodiment of the present application, the array substrate further includes:a first inorganic layer disposed on the side of the first transistor and the second transistor away from the base substrate;a second inorganic layer disposed on a side of the first inorganic layer away from the first transistor and located between the first electrode plate and the second electrode plate.

In the display panel provided by the embodiment of the present application, the array substrate further includes a display unit, the driving circuit is disposed in the display unit, and the display unit includes:a third transistor disposed in the same level as the first transistor;a pixel electrode disposed in a same level as the first electrode plate or the second electrode plate; anda common electrode also serving as the second electrode plate,wherein the display panel is time-divided into a display stage and a light sensing stage within a time period of one frame, the display unit is used to work in the display stage, and the light sensing unit is used to work in the light sensing stage.

In the display panel provided by the embodiment of the present application, the first electrode plate is disposed on the first inorganic layer, and the second electrode plate is disposed on the second inorganic layer.

In the display panel provided by the embodiment of the present application, the second electrode plate is disposed on the first inorganic layer, and the first electrode plate is disposed on the second inorganic layer.

In the display panel provided by the embodiment of the present application, the first electrode plate, the common electrode, and the pixel electrode are made of a same material.

In the display panel provided by the embodiment of the present application, the array substrate further includes a display unit, the driving circuit is disposed in the display unit, and the display unit includes:a third transistor disposed in the same level as the first transistor;a pixel electrode disposed above the third transistor and electrically connected to the third transistor; anda common electrode also serving as the second electrode plate,wherein the pixel electrode is disposed in a level different from the first electrode plate and the second electrode plate.

In the display panel provided by the embodiment of the present application, the common voltage signal line and the gate of the first transistor are disposed in a same level.

Advantageous Effect

The first electrode plate and the second electrode plate of the first capacitor in the array substrate and the display panel provided by the present application are both transparent electrode plates, the first electrode plate is formed from a newly-added transparent conductive layer, the second electrode plate is served by the common electrode of the display unit, and the display unit and the light sensing unit work alternately in a time-sharing manner within a time period of one frame, so that the first capacitor can transmit light without occupying additional display area and without impacting display of the display panel, thereby improving the aperture ratio and display effect of the display panel. Meanwhile, since the electrode plate of the first capacitor is a transparent electrode plate, it can be arranged in the display area without impacting the display, so a larger area of the first capacitor can be arranged, which improves the light sensing effect.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following description of the various embodiments is provided to illustrate the specific embodiments of the invention. Directional terms mentioned in the present invention, such as “vertical”, “horizontal”, “upper”, “bottom”, “pre”, “post”, “left”, “right”, “inside”, “outside”, “side”, etc., only refer to the direction of the additional drawing. Therefore, the directional terminology used is for the purpose of illustration and understanding of the invention. In the drawings, structurally similar elements are denoted by the same reference numerals. In the drawings, the thickness of some layers and regions is exaggerated for clear understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the application is not limited thereto.

Referring toFIG.1toFIG.3,FIG.1is a schematic diagram of a frame structure of a pixel circuit provided by an embodiment of the present application,FIG.2is a schematic diagram of a circuit structure of a light sensing circuit provided by an embodiment of the present application, andFIG.3is a schematic cross-sectional view of a first film structure of an array substrate provided by an embodiment of the present application. The array substrate100includes a base substrate10and a pixel circuit PC disposed on the base substrate10. The pixel circuit PC includes a driving circuit DC and a light sensing circuit LC. The array substrate100further includes a display unit20and a light sensing unit30disposed on the base substrate10, and the driving circuit DC is disposed in the display unit20for driving pixels in the display unit20to display. The light-sensing circuit LC is disposed in the light-sensing unit30, and is used to enable the light-sensing unit30to realize functions such as touch control, fingerprint recognition, and remote optical interaction by sensing changes in light intensity.

Optionally, the light sensing circuit LC includes a first transistor T1, a second transistor T2, and a first capacitor C1. A gate M1of the first transistor T1is connected to a first control signal line SVGG, a first electrode S1of the first transistor T1is connected to a first power line SVDD, and a second electrode D1of the first transistor T1is connected to a first electrode S2of the second transistor T2. The first capacitor C1includes a first electrode plate11and a second electrode plate12, the first electrode plate11is connected to the second electrode D1of the first transistor T1and the first electrode S2of the second transistor T2, and the second electrode plate12is connected to a common voltage signal line Vcom. The first electrode plate11and the second electrode plate12are both transparent electrode plates, and the driving circuit DC and the light sensing circuit LC share the common voltage signal line Vcom.

Further, the light sensing circuit LC further includes a readout circuit, the second electrode D2of the second transistor T2is connected to the readout circuit, and a gate M2of the second transistor T2is connected to a second control signal line Gate.

Optionally, the readout circuit includes an operational amplifier FD, a second capacitor C2, and a first switch Sr. The operational amplifier FD includes an inverting input terminal, a non-inverting input terminal, and an output terminal (wherein the inverting input terminal is marked by a symbol “−” and the non-inverting input terminal is marked by a symbol “+” inFIG.2). The non-inverting input terminal is connected to a comparison voltage Vref, and the inverting input terminal is connected to the second electrode D2of the second transistor T2. The second capacitor C2and the first switch Sr are both connected to the operational amplifier FD in parallel. Specifically, one terminal of the second capacitor C2and one terminal of the first switch Sr are both connected to the operational amplifier FD, and another terminal of the second capacitor C2and another terminal of the first switch Sr are both connected to an output terminal of the operational amplifier FD. The output terminal of the operational amplifier FD is also connected to a readout line Readout, and the readout line Readout is used to output a light sensing signal.

It should be noted that the first electrode of the transistor of the present application can be a source of the transistor, and the second electrode of the transistor can be a drain of the transistor. For example, the first electrode S1of the first transistor T1is the source of the transistor T1, and the second electrode D1of the first transistor T1is the drain of the first transistor T1, but the present application is not limited thereto. In addition, in the present application, the first capacitor C1is a storage capacitor, the second capacitor C2is an integrating capacitor, the first transistor T1is a phototransistor, and the second transistor T2is a switching transistor.

The working process of the light sensing circuit LC includes: the first control signal line SVGG provides a voltage to the gate M1of the first transistor T1, so that the first electrode S1of the first transistor T1and the second electrode D1of the first transistor T1are turned on, and a channel of the first transistor T1generates a light-induced leakage current due to irradiation by light, and generates different degrees of leakage current according to an intensity of the light. An electrical signal of the first power supply line SVDD flows from the first electrode S1of the first transistor T1to the second electrode D1, reaches the first electrode plate11of the first capacitor C1, and changes due to the light-induced leakage current generated by the first transistor T1. The second electrode plate12of the first capacitor C1is connected to the common voltage signal line Vcom, and meanwhile the first capacitor C1is in a charged state, and the charged electrical signal includes light sensing information.

Meanwhile, the first electrode plate11of the first capacitor C1is also connected to the first electrode S2of the second transistor T2. When the second control signal line Gate provides a voltage to the gate M2of the second transistor T2to turn on the first electrode S2and the second electrode D2of the second transistor T2, a charge stored in the first capacitor C1flows to the second electrode D2of the second transistor T2through the first electrode S2of the second transistor T2, so that the first capacitor C1discharges through the second transistor T2.

The second electrode D2of the second transistor T2is connected to the readout circuit, and the readout circuit receives the charge flowing out of the second electrode D2of the second transistor T2and converts the charge into a voltage signal for output.

Still referring toFIG.3, the array substrate100includes a display unit20and a light sensing unit30. The first transistor T1and the second transistor T2of the light sensing unit30are arranged in the same level, and the first capacitor C1is arranged at a side of the first transistor T1and the second transistor T2away from the base substrate10. The display unit20includes a third transistor T3, a pixel electrode13, and a common electrode14. The third transistor T3is arranged in the same level as the first transistor T1and the second transistor T2, and the pixel electrode13is arranged above the third transistor T3and electrically connected to the third transistor T3, the common electrode14and the pixel electrode13are arranged in the same level, and the common electrode14also serves as the second electrode plate12of the first capacitor C1, that is, the pixel electrode13and the second electrode plate12of the first capacitor C1are arranged in the same level.

It should be noted that the first transistor T1, the second transistor T2, and the third transistor T3are arranged in the same level, which means that in a preparation process of each of layers of the first transistor T1, the second transistor T2, and the third transistor T3, the layers formed of the same material are patterned to obtain at least two different features. For example, in this embodiment, the pixel electrode13and the common electrode14are obtained by patterning a same transparent conductive layer, so that the pixel electrode13and the common electrode14are provided in the same level.

Optionally, the array substrate100includes a first metal layer, a gate insulating layer40, a semiconductor layer, and a second metal layer stacked on the base substrate10in sequence. The first metal layer is patterned to form the gate M1of the first transistor T1, the gate M2of the second transistor T2, the gate M3of the third transistor T3, and the common voltage signal line Vcom. The semiconductor layer is patterned to form an active layer21of the first transistor T1, an active layer22of the second transistor T2, and an active layer23of the third transistor T3; and the second metal layer is patterned to form the first electrode S1and the second electrode D1of the first transistor T1, the first electrode S2and the second electrode D2of the second transistor T2, the first electrode S3and the second electrode D3of the third transistor T3, and a connection trace24for connecting the second electrode D1of the first transistor T1and the first electrode S2of the second transistor T2.

It should be noted that the semiconductor layer and the second metal layer can be subjected to a photolithography process through the same photomask to simultaneously form the first electrode, the second electrode, the connection trace, and a pattern of the active layer of the transistor. Specifically, the semiconductor layer and the second metal layer are sequentially stacked and deposited on the gate insulating layer, then a half-tone mask (HTM) or gray tone mask (GTM) is used to perform a photolithography process on the semiconductor layer and the second metal layer, and a required pattern structure is formed through multiple exposure, development, and etching processes.

The first electrode S1and the second electrode D1of the first transistor T1are in direct contact with the active layer21of the first transistor T1, there is a gap between the first electrode S1and the second electrode D2of the first transistor T1, and a portion of the active layer21corresponding to the gap is a channel of the first transistor T1. The first electrode S2and the second electrode D2of the second transistor T2are in direct contact with the active layer22of the second transistor T2, there is a gap between the first electrode S2and the second electrode D2of the second transistor T2, and a portion of the active layer22corresponding to the gap is a channel of the second transistor T2. The first electrode S3and the second electrode D3of the third transistor T3are in direct contact with the active layer23of the third transistor T3, and there is a gap between the first electrode S3and the second electrode D3of the third transistor T3, and a portion of the active layer23corresponding to the gap is a channel of the third transistor T3. Of course, parts of the first electrode and the second electrode of the transistor in contact with the active layer may also be provided with an ohmic contact layer to reduce impedance.

Further, the array substrate100further includes a first inorganic layer50and a second inorganic layer60. The first inorganic layer50is disposed at a side of the first transistor T1and the second transistor T2away from the base substrate10; and the second inorganic layer60is disposed on the side of the first inorganic layer50away from the first transistor T1and is located between the first electrode plate11and the second electrode plate12.

Specifically, the first inorganic layer50covers the first electrode S1and the second electrode D1of the first transistor T1and the first electrode S2and the second electrode D2of the second transistor T2, and covers the gate insulating layer40. The first inorganic layer50is patterned to form a first opening, and the first opening penetrates the first inorganic layer50to the connection trace24to expose a part of the connection trace24. A material of the first inorganic layer50includes an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiNO), etc.

The first electrode plate11of the first capacitor C1is disposed on the first inorganic layer50, and the second electrode plate12of the first capacitor C1is disposed on the second inorganic layer60. Specifically, a first transparent conductive layer is provided on the first inorganic layer50, and the first transparent conductive layer is patterned to form the first electrode plate11of the first capacitor C1, and the first electrode plate11is connected to the connection trace through a first via hole of the first inorganic layer50, that is, the first electrode plate11is connected to the second electrode D1of the first transistor T1and the first electrode S2of the second transistor T2. A material of the first transparent conductive layer includes a transparent conductive material such as indium tin oxide (ITO) and so on.

The second inorganic layer60covers the first electrode plate11and the first inorganic layer50, and the second inorganic layer60is patterned to form a second opening and a third opening. The second opening penetrates the second inorganic layer60, the first inorganic layer50, and the gate insulating layer40to the common voltage signal line Vcom to expose a part of the common voltage signal line Vcom. The third opening penetrates through the second inorganic layer60and the first inorganic layer50to the second electrode D3of the third transistor T3to expose a part of the second electrode D3of the third transistor T3. A material of the first inorganic layer50includes an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiNO), etc.

A second transparent conductive layer is provided on the second inorganic layer60, the second transparent conductive layer is patterned to form the pixel electrode13and the common electrode14of the display unit20, the common electrode14is connected to the common voltage signal line Vcom through a second via hole, and the common electrode14also serves as the second electrode plate12of the first capacitor C1, wherein the common voltage signal line Vcom provides a constant regulated voltage signal. The pixel electrode13is connected to the second electrode D3of the third transistor T3through a third via hole. A material of the second transparent conductive layer includes a transparent conductive material such as indium tin oxide (ITO) and so on.

In this embodiment, a separate transparent conductive film is added on the array substrate100as the first electrode plate11of the first capacitor C1of the photosensitive unit30, and the common electrode14of the display unit20also serves as the second electrode plate12of the first capacitor C1, so that the first capacitor C1can transmit light without occupying additional area of the display area, and will not impact normal display of the display panel using the array substrate100, thereby improving the aperture ratio and display effect of the display panel. Meanwhile, since the electrode plate of the first capacitor C1is a transparent electrode plate, it can be arranged in the display area without impacting display, and therefore the first capacitor C1having a larger area can be arranged, thus improving the light sensing effect.

In an embodiment, refer toFIG.4, which is a schematic cross-sectional view of a second film structure of an array substrate provided by an embodiment of the present application. A difference from the foregoing embodiment is that in the light sensing unit30of the array substrate101, the second electrode plate12of the first capacitor C1is disposed on the first inorganic layer50, and the first electrode plate11is disposed on the second inorganic layer60. In addition, the pixel electrode13of the display unit20and the first electrode plate11of the first capacitor C1are arranged in the same level, and the common electrode14also serves as the second electrode plate12of the first capacitor C1.

Specifically, the array substrate100further includes a third inorganic layer70, the first electrode plate11of the first capacitor C1is disposed on the first inorganic layer50, the common electrode14is disposed on the second inorganic layer60, the pixel electrode13is disposed on the third inorganic layer70, and a material of the third inorganic layer70may be the same as a material of the first inorganic material and/or a material of the second inorganic layer60. The common electrode14can be provided as a blanket electrode, so that more pixel electrodes13can be arranged to improve the resolution. Other descriptions can be referred to the above-mentioned embodiments, which will not be repeated herein for brevity.

Another embodiment of the present application also provides a display panel. The display panel includes the array substrate provided by one of the above embodiments, wherein the display panel is time-divided into a display stage and a light sensing stage within a time period of one frame, the display unit20is used to work in the display stage, and the light sensing unit30is used to work in the light sensing stage.

Specifically, referring toFIG.3,FIG.6, andFIG.7, whereinFIG.6is a schematic cross-sectional view of a display panel provided by an embodiment of the present application, andFIG.7is a schematic timing diagram of a time-sharing multiplexing of a display panel provided by an embodiment of the present application. The display panel1000is a liquid crystal display (LCD) panel. The display panel1000includes an array substrate100, a color filter substrate200disposed opposite to the array substrate100, a color filter substrate200disposed on the array substrate100and the array substrate100, and a liquid crystal layer300disposed between the color filter substrates200.

Since the light sensing unit30is integrated on the array substrate100, the display panel1000including the array substrate100can realize functions such as touch control, fingerprint recognition, and remote optical interaction, and meanwhile, the light sensing unit30is integrated into the display panel1000, and an overall thickness of the display panel1000can also be reduced.

The light sensing unit30and the display unit20are integrated on the array substrate100. In order not to impact the display of the display panel1000, the display unit20and the light sensing unit30work alternately in a time-sharing manner within a time period of one frame. Specifically, referring toFIG.7, the display panel1000is time-divided into a display phase DD and a light sensing phase SD within a time period of one frame. During the display phase DD, the gate scan lines sequentially provide scan signals (G1to Gn−2, Gn−1, Gn, etc. inFIG.7) to control the transistors of the display unit20to turn on and off, so as to realize the display function of the display panel1000. In the light sensing stage SD, the gate scan lines stop scanning, and G1to Gn−2, Gn−1, and Gn as shown inFIG.7are all set to low level in the light sensing stage DD to turn off the display function of the display panel1000, so that the light sensing unit30works in the light sensing stage SD. As such, the display unit20and the light sensing unit30of the display panel1000can work alternately in a time-sharing manner within a time period of one frame, which can realize functions such as touch control, fingerprint recognition, and remote optical interaction of the display panel1000without impacting the normal display of the display panel1000.

An embodiment of the present application also provides a display device, which includes the display panel provided by one of the foregoing embodiments, a device, such as a circuit board and so on, bound to the display panel, a cover plate covering the display panel, and the like. The display device includes an electronic equipment such as a mobile phone, a television, a notebook computer, etc.

According to the above embodiments:

The first electrode plate and the second electrode plate of the first capacitor in the array substrate and the display panel provided by the present application are both transparent electrode plates, the first electrode plate is formed from a newly-added transparent conductive layer, the second electrode plate is served by the common electrode of the display unit, and the display unit and the light sensing unit work alternately in a time-sharing manner within a time period of one frame, so that the first capacitor can transmit light without occupying additional display area and without impacting display of the display panel, thereby improving the aperture ratio and display effect of the display panel. Meanwhile, since the electrode plate of the first capacitor is a transparent electrode plate, it can be arranged in the display area without impacting the display, so a larger area of the first capacitor can be arranged, which improves the light sensing effect.

In the above embodiments, the descriptions of each embodiment have their own emphasis. The parts that are not described in detail in an embodiment can be referred to the detailed descriptions in other embodiments above, which will not be repeated herein for brevity.

The embodiments of the present application have been described in detail above. Specific examples are used in this text to explain the principles and implementation of the present invention. The descriptions of the above embodiments are only for understanding the method of the present invention and its core ideas, to help understand the technical solution of the present application and its core ideas, and a person of ordinary skill in the art should understand that it can still modify the technical solution described in the foregoing embodiments, or equivalently replace some of the technical features. Such modifications or replacements do not depart the spirit of the corresponding technical solutions beyond the scope of the technical solutions of the embodiments of the present application.