Multi-semiconductor solid state power controllers and method for managing inductive switching transients thereof

Provided is a method and system that includes a direct current solid state power controller that includes a plurality of switching devices connected in parallel for performing switching, one or more main transient voltage suppressors (TVSs) to perform voltage clamping, a plurality of parasitic inductances each connected in series with a switching device of the plurality of switching devices, and a plurality of local TVSs each connected in parallel with a series connection of a switching device and at least one parasitic inductor of the plurality of parasitic inductances, to dissipate energy stored within the at least one parasitic inductor of the plurality of parasitic inductances.

TECHNICAL FIELD

The present invention relates generally to multi-semiconductor solid state power controllers (SSPCs). In particular, the present invention relates to managing inductive switching transients in SSPCs.

BACKGROUND

In electrical power distribution systems, electrical faults can occur in any of the devices included therein. To mitigate this problem, the electrical power distribution systems typically employ protection circuits to protect against these electrical faults.

There is an increasing demand for electrical power in systems (e.g., aircraft systems) which has driven the need for increasing line voltages. High power SSPCs are employed within the power distribution systems of the aircraft to allow for fast and controlled electrical fault protection. As current ratings are increased, there is a corresponding increase in the number of current carrying semiconductors. Accordingly, multiple semiconductor devices, such as metal oxide semiconductor field-effect transistors (MOSFETs), are typically used in the SSPCs.

FIG. 1illustrates a typical MOSFET-based, Direct Current (DC) SSPC10of a power supply circuit. The SSPC10includes a voltage source (Vsrc)12, a load (Zload)14, an upstream wiring inductor (Lup)16connected to the voltage source12, and a downstream load inductor (Ldn)18. The SSPC10further includes switching devices (Q1, Q2, Qn)20connected in parallel to perform switching, gate resistors (Rg1, Rg2, Rgn)22and a gate voltage driver (Vgate)24to allow the switching devices10to turn on and off. During operation, opening of the SSPC, a flywheel diode (Dfwd)26recirculates the SSPC load current from the load inductor18.

Two main transient voltage suppressors (TVSs) (Dtvsmain1and Dtvsmain2)30are employed to perform voltage clamping to protect the switching devices20. Switching currents in the order of hundreds of amperes cause high magnitude electrical voltage transients that must be clamped to prevent damage to the switching devices20. The TVSs30are used to provide this clamping.

Due to the number of switching devices, the physical area occupied by these devices is large. As a result, distributed parasitic inductance is present between the main TVSs30and the switching device (Qn)20, most distant from the main TVSs30. The TVSs30have a parasitic inductance Ltvs32which can allow a voltage greater than the clamp voltage, across the terminals of the switching devices20. This condition can cause avalanche breakdown in the switching devices20due to their parasitic inductances (Lpara1, Lpara2, Lpara3, Lpara4)34.

BRIEF DESCRIPTION

Given the aforementioned deficiencies, a need exists to manage transients in multi-semiconductor SSPCs. Aspects of the present invention provide SSPC modules for power distribution systems and methods for managing transients in the SSPC modules.

Aspects of the present invention provide an approach for managing transients in multi-semiconductor SSPC modules. More particularly, the aspects provide approaches for protecting switching semiconductors from parasitic inductance. The additional use of smaller low-cost TVS devices, in addition to bulk TVS devices provides a low cost and scalable approach to managing electrical transients in multi-semiconductor SSPC modules.

In certain circumstances, aspects of the present invention provide a system including a DC solid state power controller. The DC solid state power controller includes a plurality of switching devices connected in parallel to perform switching. Also included is a pair of main TVSs to perform voltage clamping, a plurality of parasitic inductances each connected in series with a switching device of the plurality of switching devices, and a plurality of local TVSs. Each of the plurality of local TVSs is connected in parallel with the series combination of the switching device and at least one parasitic inductance of the plurality of parasitic inductances to dissipate energy stored within the at least one parasitic inductor of the plurality of parasitic inductances.

The foregoing has broadly outlined some of the aspects and features of various examples, which should be construed to be merely illustrative of various potential applications of the disclosure. Other beneficial results can be obtained by applying the disclosed information in a different manner or by combining various aspects of the disclosed examples. Accordingly, other aspects and a more comprehensive understanding may be obtained by referring to the detailed description of the exemplary examples taken in conjunction with the accompanying drawings, in addition to the scope defined by the claims.

The drawings are only for purposes of illustrating embodiments and are not to be construed as limiting the disclosure. Given the following enabling description of the drawings, the novel aspects of the present disclosure should become evident to a person of ordinary skill in the art. This detailed description uses numerical and letter designations to refer to features in the drawings. Like or similar designations in the drawings and description have been used to refer to like or similar parts of embodiments of the invention.

DETAILED DESCRIPTION

As required, detailed embodiments are disclosed herein. It must be understood that the disclosed embodiments are merely exemplary of various and alternative forms. As used herein, the word “exemplary” is used expansively to refer to embodiments that serve as illustrations, specimens, models, or patterns. The figures are not necessarily to scale and some features may be exaggerated or minimized to show details of particular components. In other instances, well-known components, systems, materials, or methods that are known to those having ordinary skill in the art have not been described in detail in order to avoid obscuring the present disclosure. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art.

Embodiments of the present invention, for example, the embodiment illustrated inFIG. 2, use local TVS devices with lower power ratings to dissipate the energy stored in the parasitic circuit inductances. Depending on the SSPC layout, as demonstrated below, and magnitude of the resulting parasitic inductances, the number of TVSs can be as many as one TVS per switching semiconductor. Ultimately, fewer TVS devices can be used to optimize performance and reduce unit cost.

In particular,FIG. 2is a circuit diagram illustrating an SSPC100for DC applications in accordance with the embodiments. By way of example, the SSPC100is suitable for use in aircraft systems. The present invention, however, is not limited to implementation within any particular type of system. The present invention can be implemented within any type of land, sea or air vehicle.

The SSPC100includes a voltage source (Vsrc)102, a load (Zload)104, an upstream wiring inductor (Lup)106connected to the voltage source102, and a downstream load inductor (Ldn)108connected to the load104. The SSPC100further includes a plurality of switching devices (Q1, Q2, Qn)120(e.g., MOSFETs) connected in parallel to perform switching. Also included is a plurality of gate resistors (Rg1, Rg2, Rgn)122, each corresponding to a respective switching device120and connected to the gate of the respective switching device120. Although the switching devices depicted inFIG. 2are MOSFETs, the present invention is not limited hereto. Thus, any type of switching device suitable for the purposes set forth herein may be implemented.

A gate voltage driver (Vgate)123is also included to drive the switching devices120to turn on and off. The gate resistors122control input voltage from the gate voltage driver123.

A flywheel diode (Dfwd)126is connected to the load inductor108to recirculate load current therefrom.

The SSPC100further includes a pair of main TVSs (Dtvsmain1and Dtvsmain2)130for performing voltage clamping to protect the switching devices120to not exceed a predetermined gate threshold voltage. The TVSs130are connected in series with a parasitic TVS inductance Ltvs132.

The switching devices120are connected in parallel with a plurality of parasitic inductances (Lpara1, Lpara2, Lpara3, Lpara4)134a-134d. And the SSPC100further includes a plurality of local TVSs136a,136bcorresponding to the plurality of switching devices120.

Each switching device120is connected in parallel with a corresponding local TVS136a,136b. The number of local TVSs can be varied such that each switching device120has a corresponding local TVS136. The local TVSs136a,136bhave lower power ratings to dissipate energy stored in the inductances134a-134d. As shown inFIG. 2, the TVS136adissipates energy stored in the inductances134aand134cand the TVS136bdissipates energy stored in the parasitic inductances134band134d.

In the embodiments, the combined maximum clamp voltages of the TVSs130are less than a minimum breakdown voltage of the switching devices120. Further, the TVSs136aand136bhave a minimum breakdown voltage greater than the maximum combined clamp voltages of the TVSs130and less than the minimum breakdown voltage of the switching devices120. Therefore, the TVSs136aand136bonly manage energy stored in the parasitic inductances134a-134d. TVSs136aand136bdo not manage the energy stored in the upstream and downstream inductors106and108. The majority of the energy stored in the upstream and downstream inductors106and108is dissipated in the bulk TVS components130. In large SSPCs containing many switching devices, it is impractical to achieve close proximity of the TVS devices130to all of the switching devices120. By fitting the distributed TVS devices136a136b, any parasitic inductances are dissipated in the TVS devices136a136brather than in the switching devices120.

FIG. 3illustrates an SSPC200according to another embodiment of the present invention. The SSPC200includes similar features as that of SSPC100shown inFIG. 2. The SSPC200, however, also includes a local TVS236a-236cconnected in series with a bias resistor (Rb)235a-235ccorresponding to each switching device220to further dissipate energy stored in corresponding parasitic inductances234a-234d.

As shown inFIG. 3, the SSPC200includes a voltage source202, a load204, an upstream inductor206and a downstream inductor208respectively connected to the voltage source202and the load204. The SSPC200further includes a plurality of switching devices220for performing switching, and a plurality of gate resistors222whereby each gate resistor222is connected to the gate of each switching device220. A gate voltage driver223is connected to the gate resistors222such that the gate resistors222control the input voltage from the gate voltage driver223to the switching devices220, to thereby control the switching devices220to turn on and off.

A flywheel diode226is connected to the downstream inductor208to recirculate the load current from the load204. The SSPC200further includes a pair of main TVSs230and corresponding parasitic TVS inductance232.

Further, the plurality of parasitic inductances234a-234dare connected to each switching device220. The plurality of bias resistors (Rb1, Rb2, Rbn)235a-235care provided and correspond to each switching device220. The plurality of local TVSs (D1, D2, Dn)236a-236care each connected in series with a corresponding one of the bias resistors235a-235cto only dissipate the energy stored in the parasitic inductances234a-234d. Alternatively, the TVSs236a-236ccan be replaced by two small signal series connected back-to-back Zener diodes.

According to embodiments of the present invention, the combined maximum clamp voltages of the main TVSs230are less than the minimum breakdown voltage of the switching devices220. Further, the threshold voltage of the switching devices220can sum up with the clamp voltage of each local TVS236a-236c. This summing results in a clamp voltage higher than the breakdown voltage of the local TVSs236a-236c. This summing also results in a minimum clamp voltage which is greater than the maximum clamp voltage of the main TVS devices230.

The present invention is not limited to DC applications and can be applied to AC applications as depicted inFIGS. 4 and 5. More specifically, the SSPCs300and400inFIGS. 4 and 5are bi-directional AC equivalents to the DC SSPCs100and200inFIGS. 2 and 3.

As shown inFIG. 4, the SSPC300includes a voltage source302, a load304, an upstream inductor306and a downstream inductor308. A plurality of switching devices (Q1a, Q1b, Q2a, Q2b, Qna, Qnb)320a-320fare also provided for performing switching. A plurality of gate resistors (Rg1a, Rg2b, Rg2a, Rg2b, Rgna, Rgnb)322a-322fare also provided corresponding to each switching device320a-320frespectively and connected to a gate thereof.

The gate resistors322a-322fare connected between each gate and a gate voltage driver323for driving voltage input to the switching devices320. A pair of flywheel diodes (Dfwda and Dfwdb)326aand326bare provided and respectively corresponding to the upstream inductor306and the downstream inductor308to perform recirculation of DC load currents during opening of the SSPC300.

A pair of main TVSs330are provided to perform voltage clamping at the switching devices320a-320f. The TVSs330include a parasitic inductor (Ltvs)332.

Further, a plurality of parasitic inductances334a-334dare connected in series with, and corresponding to, the switching devices320a-320d. For example, the parasitic inductances334aand334crespectively correspond to the switching devices320aand320b.

The SSPC300also includes a plurality of local TVSs336aand336bprovided in parallel with the switching devices320a-320f, and in series with the parasitic inductances334a-334d. The local TVSs336aand336bdissipate the energy from the parasitic inductances334a-334dsuch that the TVS336adissipates energy from the parasitic inductances334band334d.

InFIG. 5, the SSPC400includes similar features as the SSPC300shown inFIG. 4. Additionally, the SSPC400includes a voltage source402, a load404, an upstream inductor406and a downstream inductor408, and a plurality of switching devices420a-420fconnected with a plurality of gate resistors422a-422fat gates thereof. The plurality of gate resistors423a-423fare connected between the gates of the switching devices420a-420fand a voltage gate driver423, to control the input voltage at the gates.

A pair of flywheel diodes426aand426bare also provided to recirculate load current at the load404. The SSPC400further includes a plurality of local TVSs436a-436feach connected in series with one of a plurality of bias resistors (Rb1a, Rb1b, Rb2a, Rb2b, Rbna, Rbnb)438a-438fand connected to the parasitic inductances434a-434dto dissipate the energy stored therein. Alternatively, the TVSs436a-436fcan be replaced by two small signal series connected back-to-back Zener diodes in accordance with other embodiments.

FIG. 6is a graph illustrating exemplary operation of the SSPC200shown inFIG. 2. The details of the graph600will be discussed with reference toFIG. 2. As shown in the graph600, and by way of example only and not limitation, prior to point (1) a voltage across the SSPC100is 270 VDC, indicating that the SSPC100is open. At point (1) the SSPC100is closed and current rises up to 1250 A.

At point (2) on the graph600, the SSPC current passes1250A and the SSPC is tripped to open. In the case where only the main TVSs130are fitted, at point (2), the drain-source voltage across the switching devices120reaches the avalanche breakdown voltage at 1200V thus causing damage. When local TVSs136aand136bare employed, at point (2), the drain-source voltage across the MOSFET devices reaches a secondary clamp voltage of approximately 1000V.

Shortly after point (2), the parasitic inductances134a-134dand main TVS inductances132are dissipated, and the main TVS130takes over clamping at 850V. Therefore, the local TVSs136aand136bonly manage a small amount of the energy stored in the parasitic inductances234a-234d. At point (3) the main TVS current falls to zero and all of the inductive energy is dissipated.