Semiconductor device including a signal generator activated upon occurring of a timing signal

A mode decode/latch circuit decodes an input signal based on a latch timing signal to output a test mode signal to a test execution circuit. Test mode signal line includes a high-resistance portion extending from the mode decode/latch circuit toward the vicinity of the test execution circuit and a low-resistance portion connecting together the distal end of the high-resistance portion and the input of the test execution circuit. A latch circuit for latching the test mode signal based on the latch timing signal is inserted in the low-resistance portion.

This application is based upon and claims the benefit of priority from Japanese patent application No. 2006-336590 the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a semiconductor device including a signal generator which delivers a fixed output signal in a specific mode, and is activated upon occurring of a timing signal to change the output signal thereof.

(b) Description of the Related Art

Some semiconductor devices include a signal generator which operates upon occurring of a timing signal and does not deliver an active output during a period other than the period of occurring of the timing signal. Examples of such a signal generator include a test-mode signal generator which outputs a test mode signal for starting a test mode of the semiconductor device. In general, an ordinary signal line in a semiconductor device experiences a signal transition thereon along with a normal operation of a circuit component of the semiconductor device. On the other hand, the test mode signal output from the test-mode signal generator is irrelevant to the normal operation, and does not change the level thereof in the normal operation.

A normal signal line, which is active during the normal operation mode of the semiconductor device, is generally made of a low resistance material such as aluminum. On the other hand, a specific signal line, which is inactive in the normal operation mode, such as a test-mode signal line, is often made of a high resistance material such as tungsten. The specific signal line e.g., test-mode signal line may extend in a long distance between the mode-signal generation circuit and a signal receiving circuit such as a test execution circuit. The configuration wherein the specific signal line such as a test-mode signal line is made of the high resistive material is described in Patent Publications JP-1999-163065A and -1994-177251A, for example.

FIG. 3shows a known semiconductor device including the test-mode signal generator. In this figure, a portion of the semiconductor device is expressed by an equivalent circuit including a coupling capacitance between the test-mode signal line and the normal signal line. A mode decode/latch circuit201decodes a code (command) input through an external signal terminal IAi for instructing start of a test mode. The mode decode/latch circuit201decodes the input command based on a latch timing signal TMRS occurring at the test mode, and generates a test-mode signal TEST1based on the contents thus decoded. A signal line204is a normal signal line irrelevant to the test mode signal, and in this example, transmits a normal signal /SIG1, which is generated in a buffer205by reversing a normal signal SIG1.

A test execution circuit202receives the test-mode signal TEST1output from the mode decode/latch circuit201and is controlled thereby. The test-mode signal TEST1is received by a buffer206, which outputs a test mode signal /TEST1after reversing the test-mode signal TEST1, and is used in the test execution circuit202. A test-mode signal line (TEST1signal line)203for transmitting the test-mode signal TEST1extends over a long distance from the mode decode/latch circuit201to the test execution circuit202, which is controlled by the test-mode signal TEST1to execute the test operation of the semiconductor device. The test-mode signal line203includes a first portion203awhich is made of a high-resistance material, such as tungsten, and extends over a long distance extending from the mode decode/latch circuit201to the vicinity of the test execution circuit202, and a second portion203bwhich is made of a low-resistance material, such as aluminum, and connects the distal end of the first portion203ato the input of the test execution circuit202.

Since the TEST1signal line203has a higher resistance, the TEST1signal line203is susceptive to a transition noise occurring on an adjacent signal line. If a normal signal line such as /SIG1normal signal line204is disposed adjacent to the first portion203aor second portion203bof the TEST1signal line203, the TEST1signal line203receives a transition noise from the adjacent /SIG1normal signal line204upon a transition of the signal thereon and is affected by the transition noise to have a significant potential fluctuation.

FIG. 4shows the waveform of the above situation in the semiconductor device200shown inFIG. 3. In the example ofFIG. 3, the test-mode signals TEST1and /TEST1are fixed at L-level and H-level, respectively, to maintain the semiconductor device200in a normal mode before occurring of a signal transition of the normal signal /SIG1. When the normal signal /SIG1rises to an H-level during the normal operation mode, the test-mode signal line203is affected by the signal transition of the adjacent /SIG1normal signal line204in the vicinity of the distal end, i.e., node N21, of the test-mode signal line203due to a capacitive coupling. This causes a potential fluctuation of the test-mode signal TEST1, and if the range of potential fluctuation is large enough to cause a logical inversion of the test-mode signal TEST1from an L-level to an H-level, as shown by a left dotted circle inFIG. 4, the test execution circuit202interprets the logical inversion as occurring of a test mode to control the semiconductor device200to operate in the test mode, thereby incurring an error.

On the other hand, if the test-mode signal TEST1is fixed at an H-level, due to occurring a test mode, the test execution circuit202allows the semiconductor device200to operate in a test mode. When the normal signal SIG1rises from an L-level to an H-level in the normal operation, the test-mode signal line203is affected by the signal transition of the adjacent /SIG1normal signal line204at the distal end. This causes a potential fluctuation of the test-mode signal TEST1, and if the range of potential fluctuation is large enough to cause a logical inversion of the test-mode signal TEST1from an H-level to an L-level, as shown by a right dotted circle inFIG. 4, the test execution circuit202interprets the logical inversion as occurring of a normal mode to control the semiconductor device200to operate in the normal mode, thereby incurring an error.

In general, a typical semiconductor device employs a design configuration wherein the test-mode signal line used for transferring a test mode signal is disposed separately from the normal signal lines, thereby preventing the influence by the operation of the normal signal lines during a normal operation mode. In an alternative or in addition thereto, a shield line is interposed between the test-mode signal line and the normal signal lines, or a buffer is interposed at the interface between the high resistance first portion203aand the low resistance second portion203bof the test-mode signal line203, or the vicinity of the test executing circuit202to suppress the fluctuation of the potential of test-mode signal line203.

FIG. 5shows an example for suppressing the level fluctuation of the test-mode signal line, as described above. In a portion of the semiconductor device200a, a shield line207fixed at a specific potential, e.g. ground potential, is interposed between the low resistance second portion203bof the TEST1signal line203and the /SIG1normal signal line204. In another portion, a buffer208is interposed between the high resistance first portion203aand another low resistance second portion203cof the TEST1signal line203or the vicinity thereofFIG. 6is a waveform diagram showing operation of the semiconductor device200ashown inFIG. 5. If /SIG1normal signal line204changes the signal level thereof in the normal operation, node N23of the adjacent shield line207may change the potential thereof in response to the influence by the transition noise from /SIG1normal signal line204. The potential of node N21of TEST1signal line203also fluctuates due to the influence by the potential fluctuation of /SIG1normal signal line204and shield line207; however, the range of potential fluctuation of /TEST1signal line203is by far lower inFIG. 5than in the case where the shield line207is not interposed between /SIG1normal signal line204and /TEST1signal line203, as shown by a left dotted circle inFIG. 6. Thus, a logical inversion of/TEST1signal line203does not occur whereby an erroneous operation can be avoided.

In the vicinity of input of the test execution circuit202b, if /SIG1normal signal line204changes the potential thereof in the normal operation, the potential of node N22of the adjacent TEST1signal line203fluctuates due to the transition noise of/SIG1normal signal line204. However, since node N22of the low resistance second portion203cdrives the test execution circuit202b, the range of potential fluctuation of node N22is smaller inFIG. 5compared to the case where the buffer208is not interposed, whereby erroneous operation can be avoided, as shown in the right dotted line inFIG. 6.

In the technique wherein the test-mode signal line is disposed separately from the normal signal lines as well as the technique using a shield line between the test-mode signal line and the normal signal lines, there is a problem that the layout design of the signal lines consumes a longer time length due to the extraction of each of the test-mode signal lines. There is also a risk wherein it is difficult to correctly extract all the test mode lines from the normal signal lines.

In the technique using a buffer between the high resistance first portion and the low resistance second portion of the test-mode signal line or in the vicinity of the test execution circuit, there is a problem that it is difficult to find a space sufficient for disposing the buffer in the very vicinity of the test execution circuit.

SUMMARY OF THE INVENTION

In view of the above problems in the conventional technique, it is an object of the present invention to provide a semiconductor device including a signal generator which delivers a fixed output signal in a mode, and is activated upon occurring of a timing signal to change the output signal, and which is capable of suppressing the erroneous operation of a signal receiving circuit receiving the specific signal.

The present invention provides a semiconductor device including: a signal generator for generating a specific signal at a timing specified by a timing signal; a signal receiving circuit for receiving the specific signal to execute a specific operation specified by the specific signal; a signal line for transferring the specific signal from the signal generator to the receiving circuit, the signal line including a first portion having a first end connected to the output of the signal generator and a second end, and a second portion having a resistance lower than a resistance of the first portion and connecting together the second end of the first portion and an input of the signal receiving circuit; and a latch circuit inserted in the second portion to latch the specific signal at a timing specified by the timing signal.

PREFERRED EMBODIMENT OF THE INVENTION

Now, an exemplary embodiment of the present invention will be described with reference to accompanying drawings, wherein similar constituent elements are designated by similar or related reference numerals throughout the drawings.

FIG. 1shows a semiconductor device according to the embodiment of the present invention. The semiconductor device, generally designated by numeral100, is configured as a semiconductor memory device, and includes a mode decode/latch circuit (signal generator)101, test execution circuit (signal receiving circuit)102, and a latch circuit105. The mode decode/latch circuit101receives an external input signal, i.e., command signal, input through an external input terminal IAi, latches the command at a timing of occurring of a one-shot latch timing signal TMRS indicating start of a test mode, and decodes the command to generate a test-mode signal TEST1based on the contents of the command.

The test-mode signal TEST1generated by the mode decode/latch circuit101is input to the test execution circuit102via a TEST1signal line103transferring the test-mode signal TEST1. In general, a variety of normal signal lines including control signal lines, data lines, address lines, etc. which are used for normal operation are made from a metallic material having a lower resistance, such as aluminum, whereas test-mode signal lines used for controlling the test mode are configured by a metallic line having a higher resistance, such as tungsten, tungsten nitride, titanium nitride etc. In this configuration, it is considered that the test-mode signal lines are not required to operate the semiconductor device at a high speed. The test execution circuit102receives the test-mode signal TEST1output from the mode decode/latch circuit101, and executes a specific test processing. The test execution circuit102receives the test-mode signal TEST1via a buffer (inverter)107as an inverted test mode signal /TEST1.

The TEST1signal line103includes a high-resistance portion103aextending from the mode decode/latch circuit101toward the vicinity of the test execution circuit102over a long distance, and a low-resistance portion inserted between the distal end of the high resistance first portion103aand the input of the test execution circuit102. A /SIG1normal signal line104is irrelevant to the test mode operation, and transfers a normal signal /SIG1obtained in a buffer106by reversing a normal signal SIG1.

In the present embodiment, a latch circuit105which latches the test mode signal TEST1output from the mode decode/latch circuit101is inserted in the low resistance second portion103bof TEST1signal line103. The latch circuit105latches the test-mode signal TEST1based on the timing of a latch timing signal TMRS. In this text, a first section of the low-resistance portion disposed on the input side of the latch circuit105is referred to as a first low resistance potion103b, whereas a second section of the low-resistance portion disposed on the output side of the latch circuit105is referred to as a second low-resistance portion103b. The latch circuit105may be inserted at any position of the low-resistance portion, and may be located at a position significantly apart from the input of the latch circuit105.

The latch circuit105includes a switching buffer151such as configured by a clocked inverter, and a flip-flop (FF)152cascaded from the switching buffer151. The switching buffer151receives a latch timing signal /TMRS at the control input thereof via a buffer (inverter)108which reverses the latch timing signal TMRS, to be activated by the latch timing signal /TMRS. The switching buffer151outputs test-mode signal /TEST1, which is obtained by reversing test-mode signal TEST1output from the mode decode/latch circuit101, in an active state thereof. The switching buffer151does not output test-mode signal /TEST1in an inactive state thereof, and assumes a high-impedance state. In other word, the switching buffer151outputs an inverted test-mode signal /TEST1during only a time interval in which the latch timing signal TMRS assumes an H-level.

The /TMRS signal line109transferring the latch timing signal /TMRS from the buffer108to the switching buffer151is configured by a high resistance signal line such as made of tungsten. In the present embodiment, the length of the /TMRS signal line109is equivalent to the length of the TEST1signal line (103), whereby the skew of the test-mode signal TEST1is matched with the skew of the latch timing signal /TMRS. A shield line may be disposed adjacent to /TMRS signal line for alleviating the influence by noise from a normal signal line adjacent to the /TMRS signal line. This configuration prevents the switching buffer151from being activated in an inadvertent or undesirable timing.

The flip-flop152includes a buffer (inverter)153which reverses the input signal thereof and another inverter154which reverses the output of inverter153to resume the original input signal of inverter153. In consideration of the transition noise from the adjacent signal line, the size of inverters153and154is determined such that the flip-flop152has a relatively lower output impedance. More specifically, the degree of lower output impedance is such that if a transition noise enters from /SIG1normal signal line104to the second low-resistance portion103cof the test-mode signal line103, the potential fluctuation of the second low-resistance portion103cdoes not cause a logical inversion of test-mode signal /TEST1on the input of the test execution circuit102.

The flip-flop152reverses the signal output from the switching buffer151, and maintains the inverted signal therein. Thus, if the switching buffer151is in an active state, the flip-flop152outputs an inverted signal of the test-mode signal TEST1output from the switching buffer151, whereas if the switching buffer151is in an inactive state or high impedance state thereof, the flip-flop152holds the inverted test-mode signal /TEST1.

FIG. 2is a waveform diagram showing operation in the semiconductor device100ofFIG. 1. It is to be noted that node N1of the first low-resistance portion103bof the test-mode signal line103and node N2of the second low-resistance portion103care disposed adjacent to /SIG1signal line104, the transition noise of which have an influence on the nodes N1and N2due to the capacitive coupling. InFIG. 2, the semiconductor device100is operating in the normal mode, wherein the latch timing signal TMRS assumes an L-level, and the test-mode signal TEST1output from the mode decode/latch circuit101is maintained at an L-level.

When the normal signal /SIG1changes from an H-level to an L-level or from an H-level to an L-level, the potential of node N1on the distal end of TEST1signal line103as viewed from the mode decode/latch circuit101fluctuates due to the transition noise from /SIG1signal line104. However, since the latch timing signal TMRS assumes an L-level, the switching buffer151of the latch circuit105is in an inactive state. Thus, even if the potential of node N1has a large fluctuation to cause a logical inversion thereof, the logical inversion does not incur the logical inversion of output of the switching buffer151and flip-flop152. Thus, the output of flip-flop152is maintained at an L-level.

The potential of node N2of TEST1signal line103between the output of the latch circuit105and the test execution circuit102may also fluctuate due to the influence of transition noise from /SIG1signal line. However, since the second low-resistance portion103cbetween the output of the latch circuit105and the test execution circuit102is fixed at an L-level by the flip-flop152in the latch circuit105, and the latch circuit105has a lower output impedance, the potential fluctuation of node N2is small, whereby the potential of node N2is not inverted by the potential fluctuation. Accordingly, the transition noise of /SIG1signal line104does not incur an erroneous operation of the test execution circuit102.

Upon a shift of the semiconductor device to a test mode, a one-shot pulse is generated in the latch timing signal TMRS, and the mode decode/latch circuit101decodes the input command at this timing, to raise the test-mode signal TEST1to an H-level. In the latch circuit105, the switching buffer151assumes an active state during the H-level of the latch timing signal TMRS, whereby the output of switching buffer151falls to an L-level after the mode decode/latch circuit101raises the test-mode signal TEST1to an H-level.

In general, the timing at which a pulse in generated in the latch timing signal TMRS, SIG1normal signal line does not change the signal level thereof. Therefore, the potential of node N1on the input side of the latch circuit105is not subjected to the transition noise from SIG1normal signal line104during occurring of the pulse in the latch timing signal TMRS. The flip-flop152of the latch circuit105changes the output thereof to an H-level upon the fall of output of the switching buffer151to an L-level. The test execution circuit102starts the test operation due to an H-level of the test-mode signal TEST1input via TEST1signal line103, which allows the test-mode signal /TEST1to assume an L-level.

If the latch timing signal TMRS falls to an L-level, the switching buffer151in the latch circuit105is inactivated, and the flip-flop152maintains the output thereof at an H-level due to the function of inverters153and154therein. In this state, if the potential of /SIG1normal signal line104changes from an L-level to an H-level or from an H-level to an L-level, the potential of node N1may significantly fluctuate due to the transition noise from /SIG1normal signal line104. However, since the latch timing signal TMRS assumes an L-level, and the switching buffer151is in an inactive state, as in the case of the normal mode, the potential fluctuation of node N1does not affect operation of the flip-flop152.

In addition, the potential of node N2is maintained at an L-level by the flip-flop152at an L-level, although the signal level of node N2may fluctuate due to the transition noise from /SIG1normal signal line104. The relatively lower output impedance of the latch circuit105reduces the potential fluctuation of node N2. As a result, the output of buffer107in the test execution circuit102is not reversed by the potential fluctuation of node N2. Therefore, the test execution circuit102is not caused to operate in a malfunction by the influence of the transition noise of from /SIG1normal signal line104, as in the case of normal mode.

In the present embodiment, the latch circuit105for latching the test-mode signal TEST1based on the latch timing signal TMRS is inserted in the low-resistance portion of TEST1signal line103, which is connected to the input of the test execution circuit102receiving the test-mode signal TEST1. When the mode decode/latch circuit101is inactive, i.e., when the test-mode signal TEST1assumes an L-level, the switching buffer151in the latch circuit105is inactive to thereby allow the level of output of the latch circuit105to be fixed irrespective of the potential fluctuation of the input thereof. This suppresses the influence by the transition noise from the adjacent signal lines. In addition, since the latch circuit105has a lower output impedance, the output of the latch circuit105has a lower potential fluctuation. Thus, the test execution circuit102does not operate in a malfunction even if the normal signal lines are disposed adjacent to the TEST1signal line.

In the present embodiment, the switching buffer151is inactivated to prevent the potential fluctuation of the input of the latch circuit105from affecting the output thereof. Thus, if the potential fluctuation of the low-resistance portion of the test mode signal line exceeds the threshold to cause the logical inversion, the potential fluctuation doers not cause a malfunction of the test execution circuit102. Thus, the test mode signal line may be disposed adjacent to the normal signal lines without incurring a malfunction. This prevents an increase in the difficulty of layout design for the semiconductor device. The location of the latch circuit105is not limited to the interface between the high-resistance portion and the low-resistance portion or vicinity thereof, and the latch circuit may be inserted at any position of the low-resistance portion. This removes the difficulty in the layout design of the semiconductor device.

While the invention has been particularly shown and described with reference to exemplary embodiment and modifications thereof, the invention is not limited to these embodiment and modifications. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined in the claims.