Fin field-effect transistor (FinFET) and method of production thereof

Methods of forming a CT pillar with reduced width and increased distance from neighboring fins and the resulting devices are provided. Embodiments include providing a first pair of fins and a second pair of fins in an oxide layer, wherein the first and second pair of fins include Si; and forming a CT pillar including SiN between the first and second pair of fins and over a portion of the oxide layer, wherein width of the CT pillar and distance between the CT pillar and the first and second pair of fins are inversely proportional.

TECHNICAL FIELD

The present disclosure relates to a fin field-effect transistor (FinFET) method of production thereof. The present disclosure is particularly applicable to the 7 nanometer (nm) technology node and beyond.

BACKGROUND

With aggressive scaling of the FinFET technology design rule, use of a gate cut (CT) pillar for gate (PC) isolation becomes increasingly challenging. For example, in 7 nm technology, an incomplete CT is observed after the poly-open-chemical-mechanical-polishing (POC), thereby resulting in a PC to PC short. Though increasing the process time for a CT reactive-ion etching (RIE) may resolve this issue, it causes an increase in critical dimension (CD) of a CT. A large CD of CT reduces the process margin that may result in voids during work function (WF) metal fill.

A need, therefore, exists for devices with improved CT process margins with increased distance between the CT pillar and the fins in PC tip-to-tip, and for enabling methodology.

SUMMARY

An aspect of the present disclosure is a device including a CT pillar with reduced width and increased distance from neighboring fins.

Another aspect of the present disclosure is a method of forming a CT pillar with reduced width and increased distance from neighboring fins.

According to the present disclosure, some technical effects may be achieved in part by a device including: a first pair of fins and a second pair of fins in an oxide layer, wherein the first and second pair of fins includes silicon (Si); and a CT pillar includes silicon nitride (SiN) between the first and second pair of fins and over a portion of the oxide layer, wherein width of the CT pillar and distance between the CT pillar and the first and second pair of fins are inversely proportional.

Another aspect of the present disclosure is a method including providing a first pair of fins and a second pair of fins in an oxide layer, wherein the first and second pair of fins includes Si; and forming a CT pillar that includes SiN between the first and second pair of fins and over a portion of the oxide layer, wherein width of the CT pillar and distance between the CT pillar and the first and second pair of fins are inversely proportional.

A further aspect of the present disclosure is a device including a first pair of fins and a second pair of fins having a thickness of 5 nm to 22 nm in an oxide layer, wherein the first and second pair of fins includes Si; and a CT pillar that includes SiN between the first and second pair of fins and over a portion of the oxide layer, wherein width of the CT pillar is 12 nm to 40 nm and distance between the CT pillar and the first and second pair of fins is 10 nm to 35 nm.

DETAILED DESCRIPTION

The present disclosure addresses and solves the current problem of PC to PC short and reduced process margin attendant upon incomplete CT process or increased CT RIE process time. The problem is solved, inter alia, by implementing a stronger CT RIE process and oxidation of polysilicon (Poly-Si) gate.

Methodology in accordance with embodiments of the present disclosure includes providing a first pair of fins and a second pair of fins in an oxide layer, wherein the first and second pair of fins includes Si. A CT pillar that includes SiN is then formed between the first and second pair of fins and over a portion of the oxide layer, wherein width of the CT pillar and distance between the CT pillar and the first and second pair of fins are inversely proportional.

FIGS. 1A, 1B through 7A, 7B, respectively, schematically illustrate cross-sectional views of a process flow for forming a CT pillar having a reduced width along the cut line1A-1A′,1B-1B′ through7A-7A′,7B-7B′, respectively of101through701, respectively ofFIGS. 1C through 7C, respectively, andFIGS. 1C through 7Care top views showing the cut lines forFIGS. 1A, 1B through 7A, 7B, respectively. Referring toFIGS. 1A and 1B, a hardmask103, e.g., formed of SiN or any other materials with similar functional properties, and a low-K (LK) layer105are provided over and on sidewalls of a Poly-Si gate107, respectively, and the Poly-Si gate107is provided over the oxide layer109and the fins111and113formed in the oxide layer109. Next, a portion of the Poly-Si gate107is removed, e.g., by RIE or any other similar etching processes, through the hardmask103, thereby forming hardmask103′, Poly-Si gate107′ and a cavity115having a width, e.g., of 12 nm to 40 nm. Thereafter, inFIGS. 2A and 2B, the surface and the sidewalls of the cavity115are oxidized, e.g., by thermal oxidation or any other similar oxidation processes, forming an oxide spacer203having a thickness, e.g., of 2 nm to 6 nm.

As illustrated inFIGS. 3A and 3B, a portion of the spacer203and the Poly-Si gate107′ is removed, e.g., by known etching processes, through the cavity115down to the oxide layer109, thereby forming spacer203′, Poly-Si gate107″ and a trench303having a depth, e.g., of 70 nm to 140 nm, and a width, e.g., of 12 nm to 40 nm. Referring toFIGS. 4A and 4B, a SiN layer403is formed in the trench303and the cavity115, the upper surface of the SiN layer403is substantially coplanar to the upper surface of the hardmask103′. In one instance, any other materials with similar functional properties to SiN may be formed in the trench303and the cavity115. As depicted inFIGS. 5A and 5B, the SiN layer403and the hardmask103′ are planarized, e.g., by chemical mechanical planarization (CMP) or RIE, down to the Poly-Si gate107″, forming a CT pillar403′ having a width, e.g., of 12 nm to 40 nm. Subsequently, a portion of the Poly-Si gate107″ is removed, e.g., by wet etching or isotropic dry etching, thereby exposing spacer203′ on the sidewall portions of the CT pillar403′ and forming Poly-Si gate107′″.

Referring toFIGS. 6A and 6B, the spacer203′ is removed. Thereafter inFIGS. 7A and 7B, the Poly-Si gate107′″ is removed, e.g., by wet etching or isotropic dry etching, exposing the CT pillar403′ and fins111and113. The resultant CT pillar403′ has a reduced width as represented by703and an increased distance from fins111and113as represented by705. In this instance, the distance between the CT pillar403′ and the fins111and113is 10 nm to 35 nm.

FIGS. 8A, 8B through 15A, 15B, respectively, schematically illustrate cross-sectional views of a process flow for forming a T-shaped CT pillar having a reduced width along the cut line8A-8A′,8B-8B′ through15A-15A′,15B-15B′, respectively of801through1501, respectively ofFIGS. 8C through 15C, respectively, andFIGS. 8C through 15Care top views showing the cut lines forFIGS. 8A, 8B through 15A, 15B, respectively. The process steps forFIGS. 8A, 8B through 10A, 10Bare similar to the process steps forFIGS. 1A, 1B through 3A, 3B. Referring toFIGS. 8A and 8B, a hardmask803, e.g., formed of SiN or any other materials with similar functional properties, and a LK layer805are provided over and on sidewalls of a Poly-Si gate807, respectively, and the Poly-Si gate807is provided over the oxide layer809and the fins811and813formed in the oxide layer809. Next, a portion of the Poly-Si gate807is removed, e.g., by RIE or any other similar etching processes, through the hardmask803, thereby forming hardmask803′, Poly-Si gate807′ and a cavity815having a width, e.g., of 12 nm to 40. Thereafter, inFIGS. 9A and 9B, the surface and the sidewalls of the cavity815are oxidized, e.g., by thermal oxidation or any other similar oxidation processes, forming oxide spacer903having a thickness, e.g., of 2 nm to 6 nm.

As illustrated inFIGS. 10A and 10B, a portion of the spacer903and the Poly-Si gate807′ is removed, e.g., by known etching processes, through the cavity815down to the oxide layer809, thereby forming spacer903′, Poly-Si gate807″ and a trench1003having a depth, e.g., of 70 nm to 140 nm, and a width, e.g., of 12 nm to 40 nm. Thereafter inFIGS. 11A and 11B, a spacer1103is formed, e.g., by oxidation to a width of 2 nm to 6 nm, along the sidewalls of a lower portion of the trench1003, wherein the spacer1103reduces the width of the lower portion of the trench1003.

The process steps forFIGS. 12A, 12B and 13A, 13Bare similar to the process steps forFIGS. 4A, 4B and 5A, 5B. Referring toFIGS. 12A and 12B, a SiN layer1203is formed in the trench1003and the cavity815, the upper surface of the SiN layer1203is substantially coplanar to the upper surface of the hardmask803′. In one instance, any other materials with similar functional properties to SiN may be formed in the trench1003and the cavity815. As depicted inFIGS. 13A and 13B, the SiN layer1203and the hardmask803′ are planarized, e.g., by CMP or RIE, down to the Poly-Si gate807″, forming a T-shaped CT pillar1203′, wherein the upper portion of the T-shaped CT pillar1203′ has a width, e.g., of 12 nm to 40 nm, and the lower portion of the T-shaped CT pillar1203′ has a width, e.g., of 8 nm to 30 nm. Subsequently, a portion of the Poly-Si gate807″ is removed, e.g., by wet etching or isotropic dry etching, thereby exposing spacer903′ and a portion of the spacer1103and forming Poly-Si gate807′″.

Referring toFIGS. 14A and 14B, the spacer903′ and the exposed portion of the spacer1103are removed, thereby forming spacer1103′. Thereafter inFIGS. 15A and 15B, the Poly-Si gate807′″ is removed, e.g., by wet etching or isotropic dry etching, thereby exposing the T-shaped CT pillar1203′, the spacer1103′ and fins811and813. Subsequently, a portion of the width of the spacer1103′ is removed, e.g., by known etching processes, thereby forming spacer1103″. The resultant T-shaped CT pillar1203′ has a reduced width as represented by1503and an increased distance from fins811and813as represented by1505. In this instance, the distance between the CT pillar1203′ and the fins811and813is 10 nm to 35 nm.

The embodiments of the present disclosure can achieve several technical effects, such as smaller CT CD and increased distance between the CT pillar and the neighboring fins. Devices formed in accordance with embodiments of the present disclosure enjoy utility in various industrial applications, e.g., microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure enjoys industrial applicability in any of various types of semiconductor devices, particularly in the 7 nm technology node and beyond.