Gate-clocked domino circuits with reduced leakage current

A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.

FIELD

The present invention relates to digital circuits, and more particularly, to domino logic circuits with reduced current leakage.

BACKGROUND

Domino (or dynamic) logic circuits are often employed in high performance systems. For example, consider a computer system, such as that illustrated in FIG.1. InFIG. 1, microprocessor die102comprises many sub-blocks, such as arithmetic logic unit (ALU)104and on-chip cache106. Microprocessor102may also communicate to other levels of cache, such as off-chip cache108. Higher memory hierarchy levels, such as system memory110, are accessed via host bus112and chipset114. In addition, other off-chip functional units, such as graphics accelerator116and network interface controller (NIC)118, to name just a few, may communicate with microprocessor102via appropriate busses or ports.

Some or all of the functional units making up a computer system as described above may comprise domino logic circuits. Some of these domino circuits may employ clock gating, where they are put into an inactive state when not needed so as to reduce wasted power. However, for deep sub-micron process technology, wasted power due to current leakage may nevertheless present problems in clock gated domino circuits if not properly taken into account. Various techniques have been proposed for reducing leakage current, such as, for example, using dynamic threshold scaling or providing multiple supply voltages. Such techniques often introduce a performance penalty or additional hardware cost and complexity. The use of long channel length transistors in clock-gated domino circuits has also been contemplated for reducing current leakage. However, to the best of our knowledge, such previously considered techniques for using long channel length transistors in clock gated domino logic circuits have introduced a penalty in performance.

DESCRIPTION OF EMBODIMENTS

By clock gating during an evaluation phase instead of a pre-charge phase, and by utilizing long channel length transistors in the pre-charge path, embodiments of the present invention achieve leakage reduction in domino logic blocks without introducing any significant performance loss. A domino logic stage in an embodiment of the present invention at the circuit level is provided in FIG.2. In practice, more than one such domino logic stage is usually used in a domino logic block.

InFIG. 2, the clock signal is represented by φ. During a pre-charge phase, the clock signal is LOW so that pull-up pMOSFET (p-Metal Oxide Semiconductor Field Effect Transistor)202is ON and nMOSFET204is OFF. With pMOSFET202ON, a low impedance path is provided between node206and supply rail208to charge node206HIGH (VCC). During an evaluation phase, the clock signal is HIGH so that pMOSFET202is OFF and nMOSFET204is ON. Depending upon the input voltages at input ports201, the combination of nMOS pull-down logic212and nMOSFET204provides a conditional low impedance path between node206and supply rail214. In this way, node206is conditionally pulled LOW (VSS) during an evaluation phase, depending upon the input voltages.

Half-keeper216, comprising inverter218and pull-up pMOSFET220, is sized to ideally maintain node206HIGH during an evaluation phase unless it is otherwise pulled LOW by nMOS pull-down logic212and nMOSFET204. (Logic gates other than inverter218, such as a NOR gate, may be utilized in half-keeper216.) Upon completing an evaluation, the output signal at output port222propagates through other domino logic stages (not shown) and is eventually captured by a latch or other dynamic stage. The logic function realized by the domino stage ofFIG. 2depends upon the particular combination of nMOSFETs (not shown) making up n-MOS pull-down logic212.

The domino stage ofFIG. 2may be used as a boundary stage because of the presence of pull-down nMOSFET204, which isolates node206from supply rail214during a pre-charge phase regardless of the input voltages to nMOS pull-down logic212. For a domino stage not on a boundary, a pull-down nMOSFET between its nMOS pull-down logic and supply rail214may not be needed provided its input voltages are LOW during a pre-charge phase. Note that the output voltage at output port222is LOW during a pre-charge phase, so that output port222may drive the input ports of non-boundary type domino stages.

It is to be understood that the term “supply rail” as used in the above discussion is in general some kind of conductive material, such as a copper interconnect, power plane, doped polysilicon, or the integrated circuit substrate itself upon which the circuit ofFIG. 2is formed. The voltage VSSof supply rail214may not necessarily refer to the substrate voltage, and it may not necessarily be a ground voltage by which other voltages are referenced to.

Pull-up pMOSFET202, pull-up pMOSFET220, and pull-down nMOSFET224are sized to have long channel lengths. That is, the particular technology used to create the circuit ofFIG. 2on die102supports some minimum channel length L0, and a long channel length L is larger than L0, where L=(1+r)L0. As one example, r=0.05, so that L is 5% larger than the minimum channel length L0. Note that transistors202,220, and224are in the pre-charge paths of the domino stage. That is, when the domino stage ofFIG. 2is in a pre-charge phase, pMOSFET202is ON so that node206is pulled HIGH, which in turn causes nMOSFET224to turn ON to pull node222LOW, and causes pMOSFET220to turn ON. Because the pre-charge path is a non-critical path, it is expected that using long channel length transistors in the pre-charge paths should not penalize performance.

For an embodiment of the present invention, when a domino block is placed in an inactive state, the clock signal for each domino stage making up the domino block is gated so that it is HIGH, and each domino stage within the domino block is put into a discharged state. In this way, leakage current during an inactive state is reduced. One method to discharge all the stages in a domino block, is to discharge the boundary stages, which will cause all subsequent domino stages in the domino block to discharge. One way to discharge a boundary stage during an inactive stage is to ensure that its input voltages are maintained HIGH. This will be described in more detail below with reference to FIG.2.

Suppose the domino stage ofFIG. 2is a boundary stage. If during an inactive state the input voltages at input ports210are maintained HIGH, then node206will discharge (if it has not already been discharged) because pull-up pMOSFET202will be OFF and nMOS pull-down logic212and pull-down nMOSFET204will both be ON. Consequently, nMOSFET224is OFF and pMOSFET226is ON, which in turn ensures that pull-up pMOSFET220is OFF and output port222HIGH. The only transistors having a non-zero drain-source voltage are precisely those transistors in the pre-charge path, i.e., transistors202,224, and220. But because these transistors are all OFF and have long channel lengths, leakage current is significantly reduced when compared to the case in which they are not sized to have long channel lengths. Furthermore, note that because output port222is HIGH, the input port of the next domino stage connected to output port222will be HIGH. Consequently, discharging the boundary stages in a domino block will cause all subsequent domino stages to discharge during an inactive state.

A high-level abstraction of an embodiment of the present invention is provided inFIG. 3, showing domino logic block302, a bank of sampling elements304for providing input voltages to domino logic block302, a bank of sampling elements306for latching the output voltages of domino logic block302, and gated clock logic308. A clock signal and enable signal is provided to gated clock logic308. Gated clock logic308provides the gated clock signal φ, where the gated clock signal φ is held HIGH when the enable signal indicates that domino logic block302is to be put in its inactive state. The gated clock signal φ and enable signal are provided to sampling elements304. The voltages latched by sampling elements304are set HIGH when the enable signal indicates that domino logic block302is to be put in its inactive state, so that the domino stages in domino logic block302are discharged as discussed earlier.

For the embodiment ofFIG. 3, sampling elements304may be realized by any number of known latches compatible with domino logic, modified so that the latched voltages are forced HIGH when the enable signal indicates an inactive state. These modifications are relatively straightforward. As one example, a static-to-domino sampling element is shown inFIG. 4, where pull-down nMOSFETs402and404discharge node406when both the enable signal at port408and the clock signal φ are HIGH.

Various modifications may be made to the disclosed embodiments without departing from the scope of the invention as claimed below. For an example, in other embodiments, sampling elements304may be any known latch compatible with domino logic, where the latched voltages need not be HIGH provided the boundary domino stages are forced to discharge during an inactive state when the clock signal is gated HIGH. Discharging a domino stage is straightforward. For example, for the domino stage ofFIG. 2, pull-down nMOSFETs may be introduced between node206and supply rail214, similar to nMOSFETs402and404inFIG. 4, to discharge node206when the clock signal is gated HIGH and the enable signal indicates an inactive state.

As another example, in other embodiments, not all of transistors202,224, and220in a domino stage may be long channel length transistors. For example, transistors202and224may be long channel length transistors, but transistor220may not be a long channel length transistor. More generally, it is not necessary that each channel for transistors202,224, and220have the same length. Furthermore, even without using long channel length transistors, leakage current may nevertheless be reduced by discharging the domino stage and putting it in an evaluation phase during an inactive state. That is, in other embodiments, pMOSFET202, pMOSFET220, and nMOSFET224may have the same channel lengths as other transistors, but where the clock is gated so that the domino stage is in an evaluation phase when inactive, and where the domino stage is discharged when put into its inactive state.