Erase operation in a flash memory device

A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verified. Adjacent cells are programmed and verified. The parasitic capacitance between the target cells and the adjacent cells causes the threshold voltage of the target cell to increase to a new threshold voltage with the programming of the adjacent cells. A difference between the new threshold voltage and the first threshold voltage is determined. If the difference is greater than or equal to a predetermined threshold, the target cell is soft programmed until the difference is less than the predetermined threshold.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices.

BACKGROUND OF THE INVENTION

Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.

Two common types of flash memory array architectures are the “NOR” and “NAND” architectures. The architecture names refer to the resemblance that the memory cell configuration of each architecture has to a basic NOR or NAND gate circuit, respectively.

In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are connected by rows to word select lines (word lines) and their drains are connected to column bit lines. The source of each floating gate memory cell is typically connected to a common source line.

A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are connected by rows to word lines. Each memory cell, however, is not directly connected to a source line and a column bit line. The memory cells of the array are instead arranged together in strings. Each string typically comprises 8, 16, 32, or more cells. The memory cells in the string are connected together in series, source to drain, between a common sourceline and a column bitline.

As the performance of electronic systems increase, the performance of flash memory devices in the systems should increase as well. A performance increase can include improving both the speed and the memory density of the devices. One way to accomplish both of these criteria is to reduce the memory device size.

One problem with decreasing the size of a NAND flash memory device is the floating gate-to-floating gate coupling that occurs as the memory cells get closer together. For example, one cell's threshold voltage can be increased by increasing the threshold voltage of adjacent cells. The increased capacitive coupling between the floating gates can affect the verification, reading, and erasing of adjacent cells.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to reduce the effect of capacitive coupling between adjacent floating gates on memory operations.

SUMMARY

The above-mentioned problems with floating gate capacitive coupling and other problems are addressed by the present invention and will be understood by reading and studying the following specification.

The embodiments of the present invention encompass a method for erasing a non-volatile memory device. The memory device has a plurality of cells organized in rows and columns. The method comprises programming a first cell of the plurality of cells to a first threshold voltage. The first cell is located in a first row and a first column. At least one adjacent cell is programmed. A second threshold voltage for the first cell is measured. A threshold voltage difference is determined in response to the first and second threshold voltages. If the threshold voltage difference is greater than or equal to a predetermined threshold, a soft programming operation is performed on the first cell until the threshold voltage difference is less than the predetermined threshold.

Further embodiments of the invention include methods and apparatus of varying scope.

DETAILED DESCRIPTION

FIG. 1illustrates a simplified diagram of one embodiment for a NAND flash memory array of the present invention. The memory array ofFIG. 1, for purposes of clarity, does not show all of the elements typically required in a memory array. For example, only two bit lines are shown (BL1and BL2) when the number of bit lines required actually depends upon the memory density. The bit lines are subsequently referred to as (BL1-BLN).

The array is comprised of an array of floating gate cells101arranged in series strings104,105. Each of the floating gate cells101are coupled drain to source in each series chain104,105. A word line (WL0-WL31) that spans across multiple series strings104,105is coupled to the control gates of every floating gate cell in a row in order to control their operation. The bit lines (BL1-BLN) are eventually coupled to sense amplifiers (not shown) that detect the state of each cell.

In operation, the word lines (WL0-WL31) select the individual floating gate memory cells in the series chain104,105to be written to or read from and operate the remaining floating gate memory cells in each series string104,105in a pass through mode. Each series string104,105of floating gate memory cells is coupled to a source line106by a source select gate116,117and to an individual bit line (BL1-BLN) by a drain select gate112,113. The source select gates116,117are controlled by a source select gate control line SG(S)118coupled to their control gates. The drain select gates112,113are controlled by a drain select gate control line SG(D)114.

Each cell can be programmed as a single bit per cell (i.e., single level cell—SLC) or multiple bits per cell (i.e., multilevel cell—MLC). Each cell's threshold voltage (Vt) determines the data that is stored in the cell. For example, in a single bit per cell, a Vtof 0.5V might indicate a programmed cell while a Vtof −0.5V might indicate an erased cell. The multilevel cell may have multiple Vtwindows that each indicate a different state. Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell.

During a typical programming operation, a selected word line for the flash memory cell to be programmed is biased with a series of programming pulses that start at a predetermined voltage (e.g., 16V) and increase by a predetermined incremental voltage until the cell is programmed. A verification operation with a word line voltage of 0V is then performed to determine if the floating gate has been programmed. The unselected word lines for the remaining cells are typically biased at approximately 10V during the program operation.

This programming method is for purposes of illustration only. The voltages and steps discussed may be different for different embodiments.

FIG. 1illustrates four adjacent memory cells120-123of the array. The capacitive coupling of adjacent cells can occur along the same bit line or along the same word line. For example, the floating gates of cells120,122or121,123along bit line104or105, respectively can interact. Additionally, cells120,121or122,123along word lines WL28or WL29, respectively, can also be capacitively coupled.

FIG. 2illustrates the capacitive coupling in a cross-sectional view of one embodiment of the memory array ofFIG. 1. This view shows the floating gate cells fabricated on a substrate200. Each cell is comprised of a floating gate201-203formed over the substrate200. A control gate210,211is formed over the floating gates. Each control gate210,211is coupled to a word line. Shallow trench isolation (STI)212is formed between the cells and the substrate200.

For purposes of illustration, the center cell202is considered to be the target cell as discussed subsequently. This cell202is capacitively coupled to the adjacent cells201,203along the same word line210as well as the adjacent cells220-222coupled to the adjacent word lines211.

In one embodiment, programming the target cell202increases the threshold voltage (Vt) of the cell to 0.5V. After the adjacent cells201,203,220-222are programmed, the capacitive coupling increases the threshold voltage of the target cell202. This may cause problems during memory operations. For example, an erase operation may assume that the cell has a programmed Vtof 1.0V and attempt to erase the cell based on this voltage. However, since the actual Vtis larger than the assumed voltage, the erase will probably require additional erase pulses than initially planned.

FIG. 3illustrates a flowchart of one embodiment of a method of the present invention for erasing a memory array taking into account capacitive coupling of adjacent floating gates. The method begins with a block erase operation that includes an erase verify301. Since flash memory devices are typically erased a block at a time, in one embodiment the entire block containing the memory cell or cells to be programmed is erased by applying a predetermined negative voltage on the word lines of the rows to be erased. This forces the floating gates of the block to lose their charge and erases the block. In one embodiment, the erased cells have a Vtof −4.0V. Alternate embodiments use other voltages.

The block is then soft programmed303. A soft programming pulse is generated to bias the word line of the cell to be programmed in order to raise its Vtfrom the −4.0V erased voltage to −3.0V. The soft programming may be accomplished by a shorter than normal programming pulse and/or programming pulse having a lower voltage. The cells of the block are still erased but the soft programming operation starts all of the cells of the block at a substantially uniform erased threshold voltage since the erase operation may over-erase some of the cells.

An erase verification operation303is performed on the erase block to verify that the cells are at the proper erase Vt. Any cells that are not at the proper Vtare biased with another soft programming pulse until the cells in the erase block have substantially uniform threshold voltages.

In one embodiment, the verification operation biases the selected word lines with 1.0V during verification and the unselected wordlines are biased at 4.5V. Alternate embodiments may use other voltage levels for both the selected and unselected wordlines.

In one embodiment, the erase verification operation of the present invention can be performed with a lock-out function. The lock-out function prohibits the reading of memory cells that have been locked from access by lock bits. In one embodiment, the lock bits are stored by the memory device controller into status/control registers on the chip. These cells can be locked by the manufacturer or by the end user to protect important information.

The target memory cell is then programmed and verified307. The target cell is programmed and verified to a predetermined threshold voltage, Vt1. The programming may be a single cell as the result of a bit programming. In another embodiment, a byte or more of data can be programmed such that the target cell as well as other cells of a page are programmed.

In one embodiment, the programming operation is comprised of generating a plurality of programming pulses that start at a predetermined voltage (e.g., 16V) and incremented by a predetermined voltage for each pulse until the cell is verified as programmed at Vt1.

The adjacent cells to the target cell are then programmed and verified309. This operation may program each of the cells that are adjacent to the target cell such as in both the adjacent word lines and the adjacent bit lines. In an alternate embodiment, only one of the adjacent cells is programmed and verified. As described previously, this operation changes the Vtof the target cell by ΔVt.

The size of ΔVtis determined by the amount of parasitic capacitance in the array. The array structure, fabrication materials, and fabrication techniques determines the amount of parasitic capacitance.

The Vtof the target cell is then measured311. The measurement operation, in one embodiment, is accomplished by selecting the cell and the sense amplifier measuring the resulting voltage. For purposes of illustration, the new Vtis referred to as Vt2.

The erase threshold voltage (i.e., ΔVt) is determined by subtracting the original Vt1from Vt2(i.e., Vt2−Vt=ΔVt). If ΔVtis greater than or equal to a predetermined threshold313, the Erase Vtis too low and another soft programming operation303is required in order to raise the Vtof the target cell.

In one embodiment, the predetermined threshold is 50 mV. This threshold is determined by the chip manufacturer by empirical testing of a large number of memory devices to determine what voltage level cut-off provides the best point at which additional soft programming pulses are required. The embodiments of the present invention, however, are not limited to only the threshold voltage of 50 mV. Alternate embodiments may use other predetermined threshold voltages.

Having an Erase Vtthat is too low can cause problems later when it desired to program the cell. The other cells in the erase block that have higher Erase Vt's would require fewer program pulses to be programmed. Thus the cells with the Erase Vt's that are too low might not be programmed since the programming operation may stop programming after a predetermined maximum quantity of programming pulses. A tighter threshold voltage distribution is desired so that the cells in the memory block program substantially evenly.

If the ΔVtis less than the predetermined threshold313, the Erase Vtis high enough and the erase operation has been completed315. In this case, all of the cells have substantially the same or relatively close threshold voltages and further soft programming is not required.

In one embodiment, the erase method ofFIG. 3can be performed with either adjacent word line cells or adjacent bit line cells. In another embodiment, the method can be performed on both the adjacent word line cells and the adjacent bit line cells. In still another embodiment, the method can be performed on those cells that are in the middle of the NAND string as illustrated inFIG. 1. For example, only cells on word lines 4-27 are erased with the erase method of the present invention.

FIG. 6illustrates a flow chart of another embodiment of the erase method of the present invention for erasing a memory array. The method begins with a block erase operation that includes an erase verify601. This embodiment repeats the step of performing a block erase and verify operation601until the operation passes.

Once the first erase and verify operation601has passed, the block is then soft programmed and erase verified603. A soft programming pulse is generated to bias the word line of the cell to be programmed in order to raise its Vtfrom the −4.0V erased voltage to −3.0V. The soft programming may be accomplished by a shorter than normal programming pulse and/or programming pulse having a lower voltage. The cells of the block are still erased but the soft programming operation starts all of the cells of the block at a substantially uniform erased threshold voltage since the erase operation may over-erase some of the cells.

An erase verification operation603is performed on the erase block to verify that the cells are at the proper erase Vt. Any cells that are not at the proper Vtare biased with another soft programming pulse until the cells in the erase block have substantially uniform threshold voltages. If the erase verify operation603fails, the method returns to the initial step of the block erase and verification601. This loop is repeated until the operation passes.

In one embodiment, the verification operation biases the selected word lines with 1.0V during verification and the unselected word lines are biased at 4.5V. Alternate embodiments may use other voltage levels for both the selected and unselected word lines.

In one embodiment, the erase verification operation of the present invention can be performed with a lock-out function. The lock-out function prohibits the reading of memory cells that have been locked from access by lock bits. In one embodiment, the lock bits are stored by the memory device controller into status/control registers on the chip. These cells can be locked by the manufacturer or by the end user to protect important information.

The target memory cell is then programmed and verified607. The target cell is programmed and verified to a predetermined threshold voltage, Vt1. The programming may be a single cell as the result of a bit programming. In another embodiment, a byte or more of data can be programmed such that the target cell as well as other cells of a page are programmed.

In one embodiment, the programming operation is comprised of generating a plurality of programming pulses that start at a predetermined voltage (e.g., 16V) and incremented by a predetermined voltage for each pulse until the cell is verified as programmed at Vt1.

The adjacent cells to the target cell are then programmed and verified609. This operation may program each of the cells that are adjacent to the target cell such as in both the adjacent word lines and the adjacent bit lines. In an alternate embodiment, only one of the adjacent cells is programmed and verified. As described previously, this operation changes the Vtof the target cell by ΔVt.

The size of ΔVtis determined by the amount of parasitic capacitance in the array. The array structure, fabrication materials, and fabrication techniques determines the amount of parasitic capacitance.

The Vtof the target cell is then measured611. The measurement operation, in one embodiment, is accomplished by selecting the cell and the sense amplifier measuring the resulting voltage. For purposes of illustration, the new Vtis referred to as Vt2.

The erase threshold voltage (i.e., ΔVt) is determined by subtracting the original Vt1from Vt2(i.e., Vt2−Vt=ΔVt). If ΔVtis greater than or equal to a predetermined threshold613, the Erase Vtis too low and another soft programming operation603is required in order to raise the Vtof the target cell.

In one embodiment, the predetermined threshold is 50 mV. This threshold is determined by the chip manufacturer by empirical testing of a large number of memory devices to determine what voltage level cut-off provides the best point at which additional soft programming pulses are required. The embodiments of the present invention, however, are not limited to only the threshold voltage of 50 mV. Alternate embodiments may use other predetermined threshold voltages.

Having an Erase Vtthat is too low can cause problems later when it desired to program the cell. The other cells in the erase block that have higher Erase Vt's would require fewer program pulses to be programmed. Thus the cells with the Erase Vt's that are too low might not be programmed since the programming operation may stop programming after a predetermined maximum quantity of programming pulses. A tighter threshold voltage distribution is desired so that the cells in the memory block program substantially evenly.

If the ΔVtis less than the predetermined threshold613, the Erase Vtis high enough and the erase operation has been completed615. In this case, all of the cells have substantially the same or relatively close threshold voltages and further soft programming is not required. If the ΔVtis greater than or equal to the threshold613, the soft programming and erase verify603are performed again.

In one embodiment, the erase method ofFIG. 6can be performed with either adjacent word line cells or adjacent bit line cells. In another embodiment, the method can be performed on both the adjacent word line cells and the adjacent bit line cells. In still another embodiment, the method can be performed on those cells that are in the middle of the NAND string as illustrated inFIG. 1. For example, only cells on word lines 4-27 are erased with the erase method of the present invention.

FIG. 7illustrates a flow chart of yet another embodiment of the erase method of the present invention. This embodiment is substantially similar to the embodiments illustrated inFIGS. 3 and 6. However, this embodiment performs a block erase and erase verify701until the verify operation passes. Then a soft program operation without the erase verify703is performed.

FIG. 4illustrates a functional block diagram of a memory device400that can incorporate floating gate flash memory cells. The memory device400is coupled to a processor410. The processor410may be a microprocessor or some other type of controlling circuitry. The memory device400and the processor410form part of an electronic system420. The memory device400has been simplified to focus on features of the memory that are helpful in understanding the present invention.

The memory device includes an array of flash memory cells430. The memory array430is arranged in banks of rows and columns. The control gates of each row of memory cells is coupled with a word line while the drain and source connections of the memory cells are coupled to bit lines. As is well known in the art, the connection of the cells to the bit lines depends on whether the array is a NAND architecture or a NOR architecture. The memory cells of the present invention can be arranged in either a NAND or NOR architecture as well as other architectures.

An address buffer circuit440is provided to latch address signals provided on address input connections A0-Ax442. Address signals are received and decoded by a row decoder444and a column decoder446to access the memory array430. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array430. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.

The memory device400reads data in the memory array430by sensing voltage or current changes in the memory array columns using sense amplifier/buffer circuitry450. The sense amplifier/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array430. Data input and output buffer circuitry460is included for bi-directional data communication over a plurality of data connections462with the controller410. Write circuitry455is provided to write data to the memory array.

Control circuitry470decodes signals provided on control connections472from the processor410. These signals are used to control the operations on the memory array430, including data read, data write, and erase operations. The control circuitry470may be a state machine, a sequencer, or some other type of controller. In one embodiment, the control circuitry470is a state machine that performs the embodiments of the method for erasing of the present invention.

The flash memory device illustrated inFIG. 4has been simplified to facilitate a basic understanding of the features of the memory and is for purposes of illustration only. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art. Alternate embodiments may include the flash memory cell of the present invention in other types of electronic systems.

FIG. 5is an illustration of a memory module500. Although memory module500is illustrated as a memory card, the concepts discussed with reference to memory module500are applicable to other types of removable or portable memory, e.g., USB flash drives. In addition, although one example form factor is depicted inFIG. 5, these concepts are applicable to other form factors as well.

Memory module500includes a housing505to enclose one or more memory devices510. At least one memory device510is comprised of floating gate memory cells of the present invention. The housing505includes one or more contacts515for communication with a host device. Examples of host devices include digital cameras, digital recording and playback devices, PDAs, personal computers, memory card readers, interface hubs and the like. For some embodiment, the contacts515are in the form of a standardized interface. For example, with a USB flash drive, the contacts515might be in the form of a USB Type-A male connector. For some embodiments, the contacts515are in the form of a semi-proprietary interface, such as might be found on COMPACTFLASH™ memory cards licensed by SanDisk Corporation, MEMORYSTICK™ memory cards licensed by Sony Corporation, SD SECURE DIGITAL™ memory cards licensed by Toshiba Corporation and the like. In general, however, contacts515provide an interface for passing control, address and/or data signals between the memory module500and a host having compatible receptors for the contacts515.

The memory module500may optionally include additional circuitry520. For some embodiments, the additional circuitry520may include a memory controller for controlling access across multiple memory devices510and/or for providing a translation layer between an external host and a memory device510. For example, there may not be a one-to-one correspondence between the number of contacts515and a number of I/O connections to the one or more memory devices510. Thus, a memory controller could selectively couple an I/O connection (not shown inFIG. 5) of a memory device510to receive the appropriate signal at the appropriate I/O connection at the appropriate time or to provide the appropriate signal at the appropriate contact515at the appropriate time. Similarly, the communication protocol between a host and the memory module100may be different than what is required for access of a memory device510. A memory controller could then translate the command sequences received from a host into the appropriate command sequences to achieve the desired access to the memory device510. Such translation may further include changes in signal voltage levels in addition to command sequences.

The additional circuitry520may further include functionality unrelated to control of a memory device510. The additional circuitry520may include circuitry to restrict read or write access to the memory module500, such as password protection, biometrics or the like. The additional circuitry520may include circuitry to indicate a status of the memory module500. For example, the additional circuitry520may include functionality to determine whether power is being supplied to the memory module500and whether the memory module500is currently being accessed, and to display an indication of its status, such as a solid light while powered and a flashing light while being accessed. The additional circuitry520may further include passive devices, such as decoupling capacitors to help regulate power requirements within the memory module500.

FIG. 8illustrates a non-volatile memory device (i.e., NAND flash memory)800that comprises the memory array801of the present invention. Within the memory array801are a plurality of memory blocks805. Each memory block805is comprised of a plurality of word lines or pages806. One section of the memory block805comprises the erase Vtchecking area809. This area is shown in one location for purposes of illustration. Alternate embodiments can locate this area in other locations.

CONCLUSION

In summary, embodiments of the erase method of the present invention provide for a tighter threshold voltage distribution and better control over non-volatile memory operations such as erase and read. This is accomplished by programming a target cell as well as a certain number of adjacent cells. The difference the threshold voltage of the target cell moves in response to the parasitic capacitance of the adjacent cells is determined. If this difference is greater than or equal to a predetermined threshold voltage, the target cell goes through another soft program operation until the difference is less than the predetermined threshold voltage.