Methods of forming semiconductor devices having multiple channel MOS transistors

In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 2003-82824, filed on Nov. 21, 2003, the disclosure of which is incorporated herein by reference as if set forth in its entirety.

FIELD OF THE INVENTION

The present invention relates to methods of manufacturing semiconductor devices and, more particularly, to methods of manufacturing MOS transistor semiconductor devices.

BACKGROUND OF THE INVENTION

As semiconductor devices become more highly integrated, the size of the active region of the device on which circuits are formed becomes smaller. As a result, the channel length of a MOS transistor that is formed on the active region is reduced. It will be understood by those having skill in the art that as used herein, the term “MOS” refers to any insulated gate field effect transistor, the gate of which comprises metal and/or nonmetal (such as polysilicon) and the insulator of which comprises oxide and/or other insulators (such as high dielectric constant insulators).

As the channel length of the MOS transistor is reduced, the source and drain may have an increased effect on the electric field/electric potential in the channel region. This phenomenon is referred to as the short channel effect. Additionally, when the width of the channel is narrowed as the size of the active region is reduced, the threshold voltage of the MOS transistor may be lowered. This phenomenon is referred to as a reverse narrow width effect.

Methods for reducing the size of semiconductor devices and for improving the performance of such devices have been developed. For example, U.S. Pat. No. 6,413,802 discloses methods for providing a vertical MOS transistor having a fin structure that comprises a plurality of thin channel fins between a pair of source/drain regions and a gate electrode that is formed on both sides of the channel fins. U.S. Pat. No. 4,996,574 discloses a MOS transistor having a DELTA structure that has a channel layer that includes a vertically protruded portion which is surrounded by a gate electrode. MOS transistor having a gate all around (GAA) structure have also been proposed. In these transistors, an active pattern as an SOI layer may be formed on a substrate. A gate electrode surrounds the channel region of the active pattern, on which an insulation layer is formed.

SUMMARY OF THE INVENTION

Pursuant to embodiments of the present invention, methods of manufacturing a MOS transistor are provided in which a stacked structure comprising a first semiconductor layer on a substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer and a fourth semiconductor layer on the third semiconductor layer is formed. A hard mask pattern is formed on at least a portion of the fourth semiconductor layer. The first, second, third and fourth semiconductor layers are partially etched, and then trimmed to form an active pattern that extends above the upper surface of the substrate and has first and second sidewalls that are substantially vertical. A semiconductor layer is grown on the first and second sidewalls of the active pattern to form a pair of source/drain regions, and then portions of the first and third semiconductor layers are selectively etched to form a pair of tunnels in the active pattern that extend from the front to the rear side of the pattern. A conductive gate is then formed on the top surface of the active pattern and in the tunnels.

In some embodiments, the first and third semiconductor layers may have an etching selectivity with respect to the second and fourth semiconductor layers. The trimming process may trim the width of the first, second, third and fourth semiconductor layers to a width that is less than the width of a lower surface of the hard mask pattern. In still other embodiments, a spacer may be formed on opposing sidewalls of the hard mask pattern. In these embodiments, the etched first, second, third and fourth semiconductor layers may be trimmed to have a width that is less than the combined width of a lower surface of the hard mask pattern and the spacer. The trimming may be performed by isotropically etching the etched first, second, third and fourth semiconductor layers using an etchant that has little etching selectivity between the first, second, third and fourth semiconductor layers.

In certain embodiments, the hard mask pattern may have a trapezoidal shape. The method may also include removing the hard mask pattern and thereafter forming spacers on the top surface of the source/drain regions. A gate insulation layer may also be formed on an inner surface of each tunnel, on a sidewall of each spacer and on the active pattern.

According to further embodiments of the present invention, methods of manufacturing a semiconductor device are provided in which a preliminary active pattern is formed on a substrate. The preliminary active pattern includes at least two gate layers and at least two channel layers that are alternatively stacked. A hard mask may be formed on the preliminary active pattern, and then the preliminary active pattern may be partially etched using the hard mask as an etching mask. Thereafter, the width of the etched preliminary active pattern may be trimmed to form an active channel pattern, and a semiconductor layer is grown on first and second exposed sides of the active channel pattern and a top surface of the substrate to form source/drain regions. Additionally, the gate layers may be selectively etched to form tunnels therethrough, and an upper gate is formed on the upper face of the active channel pattern and a lower gate is formed on the front and rear sides of the active channel pattern and in the tunnels.

In certain embodiments of these methods, the channel layers and the gate layers are formed of different materials that have an etching selectivity with respect to each other, such as silicon and germanium or silicon-germanium. During formation of the source/drain regions first impurities may be implanted into portions of the semiconductor layer grown on the first and second exposed side faces of the active channel pattern and the top surface of the substrate. A top surface portion of the substrate that is positioned beneath the lowest gate layer may be doped with second impurities to form a channel isolation region, where the second impurities have a conductivity type that is opposite the conductivity type of the first impurities.

In these methods, the upper width of the hard mask may be less than the lower width of the hard mask. The hard mask may be formed by successively stacking an etch stop layer and a dummy gate layer on the preliminary active pattern and then partially etching these layers to form a hard mask having a side face inclined to an upper face of the hard mask. A spacer that has an etch selectivity with respect to the dummy gate layer may also be formed on a side face of the hard mask. The spacer and the etch stop layer may be formed of substantially identical materials.

Pursuant to still further embodiments of the present invention, intermediate structures are provided that are formed during the fabrication of multi-channel MOS transistors. The intermediate structure comprises an active channel pattern on a substrate, the active channel pattern comprising a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer and a fourth semiconductor layer on the third semiconductor layer. The first and third semiconductor layers have an etching selectivity with respect to the second and fourth semiconductor layers. A hard mask is provided on the active channel pattern, where the width of a lower portion of the hard mask exceeds the width of an upper portion of the hard mask.

In certain embodiments of these intermediate structures, the width of the active channel pattern may be less than the width of the hard mask. The hard mask may comprise a stacked structure that includes a dummy gate pattern on an etch stop layer pattern. The hard mask may have a trapezoidal-shaped cross-section. In other embodiments, the hard mask may comprise a dummy gate pattern on an etch stop layer pattern, and first and second spacers that are provided on sidewalls of the dummy gate pattern and the etch stop layer pattern. The active channel pattern may have substantially vertical sidewalls that extend above an upper surface of the substrate. Source/drain regions may also be provided on the sidewalls of the active channel pattern. The intermediate structure may also include an insulation layer on the active channel pattern, the first and second semiconductor source/drain regions and the hard mask.

DETAILED DESCRIPTION

It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (i.e., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. Herein the substrate is described as a lower or the lowest layer of the devices described herein, but it will be appreciated that the substrate could be positioned in a different orientation without departing from the scope of the present invention.

FIG. 1Ais a perspective view illustrating an active pattern40of a multi-channel MOS transistor. The active pattern40is formed on a semiconductor substrate (not shown), and includes an active channel pattern36that has multiple, vertically-disposed, channel regions. The active channel pattern36has vertical side faces. The active pattern40also includes source/drain layers26that are formed on the side faces of the active channel pattern36and a surface of the substrate.

Tunnels38, which define the channel regions are provided through the active channel pattern36. The active channel pattern36is doped with N-type impurities or P-type impurities in accordance with the type of the transistor. For example, to form an N-type transistor, the active channel pattern36is doped with a low concentration of P-type impurities.

In the embodiment depicted inFIG. 1A, two tunnels38are formed through the active channel pattern36. A lower gate is formed in each tunnel. It will be appreciated by those of skill in the art that a single tunnel38or three or more tunnels38may be included in alternative embodiments of the present invention.

The source/drain layers26are doped with impurities that are the opposite to the impurity type used to dope the channel regions. For example, when the transistor is an N-type transistor, the source/drain layers26are doped with N-type impurities.

As shown inFIG. 1A, the active pattern40includes a protruded central portion having an upper face and side faces that are substantially perpendicular to the upper face. The tunnels38are formed through the protruded central portion to define the channel regions of the transistor.

Referring toFIGS. 1B and 2, a gate50surrounds the channel regions and extends into, and in some embodiments, fills, the tunnels38. The gate50also extends above the upper face of the active pattern40.

The gate50includes a gate insulation layer42that is formed on inner faces of the tunnels38and the upper face of the active pattern40. The gate insulation layer42may comprise, for example, a thermal oxide layer, an oxide/nitride/oxide (ONO) layer, etc. The gate50further includes a conductive layer pattern44that is formed on the gate insulation layer42. The conductive layer pattern44may, for example, comprise a polysilicon and/or metal layer.

Herein, the portion of the gate50that extends from the upper face of the active pattern40is referred to as the upper gate50a. The remaining portions of the gate50, including the portions formed in the tunnels38, are referred to as the lower gate50b. A metal layer or a metal silicide layer52may be formed on an upper face of the upper gate50a. The layer52may facilitate reducing the gate resistance. An oxide spacer34, such as, for example, a silicon oxide spacer, may be formed on side faces of the upper gate50a.

When the semiconductor substrate is a bulk silicon substrate, a channel isolation region12may be provided beneath the lowest tunnel38. The channel isolation region12may comprise a portion of the substrate that is doped with impurities that are the opposite of the impurities used to dope the source/drain layers26. When the semiconductor substrate comprises an SOI substrate or an SGOI substrate, an insulator may be used to form the channel isolation region12. The channel isolation region12may reduce or prevent a channel from forming beneath the lowest tunnel38, thereby reducing the short channel effect.

The active channel pattern36may comprise a single crystalline semiconductor layer or layers. In embodiments of the present invention, the active channel pattern36comprises a single crystalline silicon layer(s). The source/drain layers26may be a single crystalline semiconductor layer, such as, for example, a silicon layer. Additionally, the metal layer or metal silicide layer52(seeFIG. 2) may also be formed on surfaces of the source/drain layers26to reduce the resistance of the source/drain regions26.

In certain embodiments of the present invention, the source/drain layers26may have a uniform doping profile in a direction substantially perpendicular to the length direction of the channel regions. Accordingly, although the length of the channel regions is increased, a relatively uniform source/drain junction capacitance may be maintained. As a result, the speed of the semiconductor device may be improved by increasing the current and reducing the junction capacitance.

Hereinafter, methods of manufacturing a semiconductor device in accordance with some embodiments of the present invention are discussed in detail.

FIGS. 3A to 3Oare cross sectional views that illustrate methods of manufacturing a semiconductor device in accordance with certain embodiments of the present invention.FIGS. 4A to 4Care perspective views which further illustrate these methods of manufacturing a semiconductor device.

Referring toFIG. 3A, a semiconductor substrate10is provided. The semiconductor substrate10may, for example, comprise a bulk silicon substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate or various other substrates.

As shown inFIG. 3A, impurities may be implanted into the surface of the semiconductor substrate10to form a channel isolation region12. These impurities are of a conductivity type that is the opposite of the conductivity type of the impurities that are implanted into the source/drain regions of the transistor. The channel isolation region12may serve to reduce and/or minimize the short channel effect in transistors formed on bulk semiconductor substrates.

When the semiconductor substrate10comprises a bulk silicon substrate or a silicon germanium substrate, the process for forming the channel isolation region12may be performed. However, when the semiconductor substrate10comprises a silicon-on-insulator substrate or a silicon-germanium-on-insulator substrate, the process for forming the channel isolation region12may be omitted and the insulator may be used as the channel isolation region.

Referring toFIG. 3B, gate layers14and channel layers16are alternatively formed on the semiconductor substrate10. In some embodiments, a first gate layer14ais formed on the substrate10, and a first channel layer16ais formed on the first gate layer14a. A second gate layer14bis then formed on the first channel layer16a, and a second channel layer16bis formed on the second gate layer14b.

In certain embodiments of the present invention, the channel layers16a,16bmay comprise a first single crystalline semiconductor material and the gate layers14a,14bmay comprise a second single crystalline semiconductor material that has an etching selectivity with respect to the first single crystalline semiconductor material. By way of example, the channel layers16a,16bmay comprise silicon layers having a thickness of about 300 Å and the gate layers14a,14bmay comprise germanium layers or silicon-germanium layers having a thickness of about 300 Å. In alternative embodiments, the channel layers16a,16band the gate layers14a,14bmay be formed by an epitaxial growth process and may be formed of materials that may or may not have etch selectivity with respect to each other.

The thickness and the number of the channel layers16a,16band gate layers14a,14bmay be varied. In the present embodiment, the entire thickness of the channel layers16a,16band the gate layers14a,14bis about 1,000 Å to about 1,500 Å. The channel layers16a,16bmay be doped, for example, by implanting impurities or by forming the channel layers16a,16busing doped single crystalline silicon layers.

Referring toFIG. 3C, the channel layers16a,16b, the gate layers14a,14band portions of the substrate10under the channel isolation region12are etched to form an isolation trench. An oxide layer may then be formed on the second channel layer16band in the isolation trench. The oxide layer is planarized to expose a surface of the second channel layer16busing, for example, a chemical mechanical polishing (CMP) process or an etch-back process to form field oxide layers18defining an active region and a field region. The planarization process also forms a preliminary active pattern that includes the gate layers14a,14band the channel layers16a,16b. The active region may have an island pattern.

Referring toFIG. 3D, an etch stop layer (not shown) is formed on the second channel layer16b. A dummy gate layer (not shown) is formed on the etch stop layer.

The etch stop layer may comprise an insulation material such as silicon nitride that has an etch selectivity with respect to the dummy gate layer. In embodiments of the present invention, the etch stop layer may have a thickness of about 100 Å to about 200 Å. The etch stop layer may reduce or prevent etching of the second channel layer16bduring the process that etches the dummy gate layer. The dummy gate layer may be used to define a gate region. The dummy gate layer may comprise, for example, a silicon oxide layer having a thickness of about 1,000 Å to about 3,000 Å.

The dummy gate layer and the etch stop layer are subsequently etched using, for example, a dry etch process to form a gate hard mask20that includes an etch stop layer pattern20aand a dummy gate pattern20b. The etching process may be performed so as to provide the etch stop layer and the dummy gate layer with sloped sides. As a result, the gate hard mask20may have a trapezoidal cross-section that has a lower side which is wider than the upper side.

Referring toFIG. 3E, the preliminary active pattern may be etched using the gate hard mask20as an etching mask. This etching process may be used to expose a portion of the substrate10and to form channel layer patterns16a′16b′ and gate layer patterns14a′,14b′. Portions of the substrate may be etched so that the channel isolation region12extends above the top surface of the remainder of the substrate10in the active region.

Referring toFIG. 3F, the channel layer patterns16a′,16b′ and the gate layer patterns14a′,14b′ may be isotropically etched to form an active channel pattern24. The active channel pattern24may have a width that is less than the width of the etched preliminary active pattern. The isotropic etching process is referred to as a trimming process because the channel length may be determined through the isotropic etching process.

To form the vertical side profile of the active channel pattern24, the isotropic etching process may be carried out using an etching gas that has little etching selectivity between the channel layer patterns16a′,16b′ and the gate layer patterns14a′,14b′. The isotropic etching process may comprise, for example, a chemical dry etching process that uses radicals in the etching gas. The active channel pattern24formed by such a chemical etching process may have a pattern size that is less than the pattern size resulting from a photolithography process.

As shown inFIG. 3G, a selective epitaxial single crystalline layer may be grown to a thickness of, for example, about 300 Å to about 400 Å on the exposed surface of the semiconductor substrate10and sidewalls of the active channel pattern24to form source/drain layers.

As shown inFIG. 3G, the active channel pattern24may have a width that is less than the lower width of the gate hard mask20. As a result, the active channel pattern24may be masked by the gate hard mask20. When the source/drain layers26are epitaxially grown from both sides of the active channel pattern24, growth of the source/drain layers26is suppressed in a direction substantially parallel to both sides of the active channel pattern24. Thus, the source/drain layers26mostly grow in a direction substantially perpendicular to the sides of the active channel pattern24. Accordingly, the source/drain layers26have a profile that is substantially perpendicular to the substrate10. This may facilitate formation of a silicide layer on an upper face of the source/drain layers26in a subsequent process.

Impurities may then be implanted into the source/drain layers26. The impurities may be implanted in a slanted direction or a vertical direction to form doped source/drain regions26. The impurities may have uniform concentration.

Referring toFIG. 3H, a silicon nitride layer30may be formed on the field region18, the source/drain regions26and the gate hard mask20. A top portion of the silicon nitride layer30may then be removed by, for example, a CMP process to expose the upper face of the dummy gate pattern20b.

Referring toFIG. 3I, the dummy gate pattern20bmay then be removed. The etch stop layer pattern20amay be partially etched to form a gate trench32defining a region in which an upper gate is formed. Here, since the etch stop layer20ahas a high etching selectivity with respect to the dummy gate pattern20b, the second channel layer pattern16b′ may not be removed.

As described above, the gate hard mask20may have a trapezoidal cross-section. As a result, the upper width of the gate trench32is less than the lower width of the gate trench32.

Referring toFIG. 3J, a silicon oxide layer (not shown) is formed on sidewalls of the silicon nitride layer30, on the source/drain layers26and on the second channel layer pattern16b″. The silicon oxide layer may then be anisotropically etched to form an inner oxide spacer34on the sidewalls of the gate trench32.

The inner oxide spacer34narrows the width of the gate trench32(and hence the length of the upper gate). Since the lower portion of the oxide spacer34is thicker than the upper portion, the sidewalls of the gate trench32may have a substantially vertical profile. Accordingly, the upper gate has a length that is substantially similar to the length of the lower gate.

In further embodiments of the present invention, the impurities may be implanted into the channel layer pattern16a″ and16b″ after forming the inner oxide spacer34, instead of implanting them in the manner described above.

As shown inFIG. 4A, at this point in the process the field region18may be exposed through front and rear sides of the active channel pattern24. As shown inFIGS. 3K,4B and4C, the exposed field region18may then be partially etched to expose the front and rear sides of the active channel pattern24(seeFIG. 4B). The gate layer patterns14a″,14b″ may then be partially removed using, for example, an isotropic etching process, to form tunnels38through the active channel pattern24(seeFIG. 4C). An active pattern40that includes the active channel pattern24having the tunnels38and the source/drain layers26is formed via this isotropic etching process. The active pattern40may have a protruded central portion that has vertical sides.

Referring toFIG. 3L, the substrate10may then be thermally oxidized to form a gate insulation layer42. In embodiments of the present invention, the gate insulation layer42may have a thickness of about 10 Å to about 70 Å on inner faces of the tunnels38, on the silicon nitride layer30and on sidewalls of the inner oxide spacer34. The gate insulation layer42may comprise, for example, a silicon oxide layer or a silicon oxynitride layer. The substrate10may be thermally treated at a high temperature under, for example, a hydrogen atmosphere or an argon atmosphere to improve surface roughness of the exposed layers before forming the gate insulation layer42.

Referring toFIG. 3M, a gate conductive layer44is formed to fill the tunnels38, the etched field region and the gate trench32. A gate50that includes the gate insulation layer42and the gate conductive layer44is formed by this process. In embodiments of the present invention, the gate conductive layer44may be formed as follows. A conductive layer (not shown) such as, for example, a polysilicon or metal layer is formed on the gate insulation layer42to fill the tunnels38, the etched field region and the gate trench32. Portions of the conductive layer may then be removed by, for example, a CMP process which exposes the silicon nitride layer30and forms the gate conductive layer44.

The portion of the gate50that extends from the upper face of the active pattern40is referred to herein as the upper gate50a. The portion of the gate50that are formed in and adjacent the tunnels38is referred to herein as the lower gate50b.

As shown inFIG. 3N, the silicon nitride layer30may then be removed to form the active pattern40, the upper gate50aand the lower gate50b. The upper gate50ais positioned on the upper face of the active pattern40. The lower gate50bis disposed in a vertical direction in the active pattern40. The oxide spacer34is positioned on sidewalls of the upper gate50a.

Additionally, impurities having a high concentration may be implanted into the source/drain layers26after the silicon nitride layer30is removed.

As shown inFIG. 3O, when polysilicon is used to form the gate electrode, a metal silicide layer52may be partially formed on the upper gate50aand the source/drain layers26. A first portion of the metal silicide layer52on the upper gate50amay facilitate reducing the resistance of the upper gate50a. A second portion of the metal silicide layer52on the source/drain layers26may likewise facilitate reducing the resistances of the source/drain layers26and a contact that is formed by a successive process. The metal silicide layer52is not formed on the sides of the upper gate50adue to the oxide spacer34. Thus, a short between the first and second portions of the metal silicide layer52may be prevented.

FIGS. 5A to 5Lare cross sectional views illustrating methods of manufacturing a semiconductor device in accordance with further embodiments of the present invention.

Referring toFIG. 5A, a channel isolation region112is formed on a substrate110. The substrate110may be divided into an active region and a field region118by processes substantially identical to the processes that are discussed above with reference toFIGS. 3A to 3C. Impurities may be implanted into the substrate110to form channel isolation region112. A gate layer114including first and second gate layers114a,114b, and a channel layer116including first and second channel layers116a,116bare alternatively stacked on the channel isolation region112.

The channel layer116may comprise a first single crystalline semiconductor material, and the gate layer114may comprise a second single crystalline semiconductor material that has an etching selectivity with respect to the first single crystalline semiconductor material. The channel layer116may comprise, for example, a single crystalline silicon layer having a thickness of about 300 Å. The gate layer114may comprise, for example, a single crystalline germanium layer or a single crystalline silicon-germanium layer having a thickness of about 300 Å.

The channel layers116a,116b, the gate layers114a,114band portions of the substrate110under the channel isolation region112are then etched to form an isolation trench. The isolation trench may be filled with, for example, a silicon oxide layer to divide the substrate110into the active region and the field region118. By the above-described process, a preliminary active pattern including the gate layer114and the channel layer116may be formed.

Referring toFIG. 5B, an etch stop layer (not shown) is formed on the second channel layer16b. A dummy gate layer (not shown) is formed on the etch stop layer.

The etch stop layer may comprise an insulation material such as, for example, silicon nitride that has an etching selectivity with respect to the dummy gate layer. The etch stop layer may have a thickness, for example, of about 100 Å to about 200 Å. The etch stop layer may be used to prevent the second channel layer16bfrom being etched during the etching of the dummy gate layer. The dummy gate layer may be used to define a gate region. The dummy gate layer may comprise, for example, a silicon oxide layer having a thickness of about 1,000 Å to about 3,000 Å.

The dummy gate layer and the etch stop layer may then be etched to form a gate hard mask120that includes an etch stop layer pattern120aand a dummy gate pattern120b.

A silicon nitride layer (not shown) may then be formed on the gate hard mask120and the second channel layer116b. The silicon nitride layer may then be anisotropically etched to form a nitride spacer122on the sides of the gate hard mask120.

As shown inFIG. 5C, the channel layer116and the gate layer114may then be etched using the gate hard mask120as an etching mask to expose a portion of the substrate110and to form a preliminary active pattern124. The preliminary active pattern124includes channel layer patterns116a′,116b′ and gate layer patterns114a′,114b′.

Referring toFIG. 5D, the channel layer patterns116a′,116b′ and the gate layer patterns114a′,114b′ may be isotropically etched to form an active channel pattern128that has a width that is less than the width of the etched preliminary active pattern124. This isotropic etching process is referred to as a trimming process because a channel length may be determined through the isotropic etching process.

The isotropic etching process may be carried out using an etching gas that has little etching selectivity between the channel layer pattern116and the gate layer pattern114. The isotropic etching process may include a chemical dry etching process using radicals in the etching gas. The active channel pattern128formed by the chemical etching process may have a pattern size that is less than the pattern size that would result if a photolithography process was used.

As shown inFIG. 5E, a selective epitaxial single crystalline layer may be grown to a thickness of about 300 Å to about 400 Å on the exposed surface of the semiconductor substrate110and both sides of the active channel pattern128to form source/drain layers130. The active channel pattern128may have a width that is less than the lower width of the gate hard mask120so that the active channel pattern128is masked by the gate hard mask120. When the source/drain layers130epitaxially grow from the both sides of the active channel pattern128, growth of the source/drain layers130may be suppressed in a direction substantially parallel to the both sides of the active channel pattern128.

Impurities may then be implanted into the source/drain layers130in, for example, a slant direction or in a vertical direction, to complete formation of the source/drain regions.

A silicon nitride layer132may then be formed on the field region118, the source/drain layers130and the gate hard mask120to fill the space between the source/drain layers130and the field region118. Portions of the silicon nitride layer132may thereafter be removed by a CMP process to expose the upper face of the dummy gate pattern120b. Here, since the nitride spacer122includes a material substantially identical to that of the silicon nitride layer132, the nitride spacer122may not be differentiated from the silicon nitride layer132.

As shown inFIG. 5F, the dummy gate pattern120bmay then be removed. The etch stop layer pattern120ais partially etched to form a gate trench134.

In further embodiments of the present invention, the impurities may not be implanted into the channel layer patterns116a″,116b″ in the process described above. In such embodiments, the impurities may instead be implanted into the channel layer patterns116a″,116b″ after forming the gate trench134.

Referring toFIG. 5G, the exposed field region112is partially etched to expose the front and rear sides of the active channel pattern128. The gate layer patterns114a″,114b″ may then be partially removed, for example, by an isotropic etching process to form the tunnels138through the active channel pattern128.

An active pattern142that includes the active channel pattern128with the tunnels138and the source/drain layers130is formed by the isotropic etching process. The active pattern142includes a protruded central portion having vertical sides that extends from the top surface of the substrate110.

Referring toFIG. 5H, the substrate110is thermally oxidized to form a gate insulation layer144having, for example, a thickness of about 10 Å to about 70 Å. The gate insulation layer144may be formed on the inner faces of the tunnels138and on the gate trench134. A gate conductive layer146is formed that fills the tunnels138, the etched field region118and the gate trench134. A gate150including an upper gate150aon the active pattern142and a lower gate150bhorizontally penetrating through the active pattern142may be formed by the above-described process.

Referring toFIG. 5I, the silicon nitride layer132may then be partially etched to expose a surface of the field region118and to form an etched silicon nitride layer132a. Thus, the upper gate150aextends above the silicon spacer132a.

Referring toFIG. 5J, a silicon oxide layer (not shown) is formed on both sides of the upper gate150aand on the etched silicon nitride layer132a. As shown inFIG. 5J, the silicon oxide layer may then be anisotropically etched to form an oxide spacer152on both sides of the upper gate150a.

Referring toFIG. 5K, the etched silicon nitride layer132amay then be removed to form the active pattern142, the lower gate150bhorizontally disposed in the active pattern142, and the upper gate150aon the active pattern142. The upper gate150ais positioned on the upper face of the active pattern142. The oxide spacer152is positioned on the upper gate150a. Additionally, impurities may be implanted into the source/drain layers26after removing the silicon nitride layer130.

As shown inFIG. 5L, when polysilicon is used to form the a gate electrode, a metal silicide layer154may be selectively formed on the upper gate150aand the source/drain layers130.

According to embodiments of the present invention, semiconductor devices having a single active pattern that may include thin channels enclosed by the gate are provided. Since the thin channels are formed in a vertical direction, the source/drain regions may occupy a relatively smaller area within the active region.

The source/drain regions of the devices may also have a doping profile in a vertical direction with respect to the channels so that a junction capacitance of the source/drain regions may, in some instances, be maintained relatively constant regardless of the number and/or the area of the channels. This may facilitate rapid device operation.

In further embodiments of the present invention, growth of the epitaxial layer may be suppressed by the trimming process so that the source/drain layers may have an improved shape. Also, since the active pattern has the vertical side profile, the silicide layer may have uniform thickness so that the resistance of the source/drain layers may be reduced.

Additionally, although not depicted in the figures, it is noted that a highly-integrated vertical MOS transistor having multiple channels may be embodied by combining above-mentioned embodiments with each other.