Radiation tolerant device structure

Techniques for producing radiation tolerant device structures are provided. In one aspect, a method for forming a radiation-hardened device includes the steps of: forming fin masks on a SOI layer of an SOI wafer, wherein the SOI wafer includes the SOI layer separated from a substrate by a buried insulator; patterning fins in the SOI layer using the fin masks; and implanting at least one dopant into exposed portions of the buried insulator between the fins to increase a radiation hardness of the device structure by providing a path in the buried insulator for charge to dissipate, wherein the fin masks are left in place during the implanting step to prevent damage to the fins. Implementations with a bulk substrate, as well as the resulting devices, are also provided.

FIELD OF THE INVENTION

The present invention relates to techniques for increasing radiation hardness, and more particularly, to using the periodic nature of a Fin Field Effect Transistor (FinFET) structure to implant selected atoms or ions in a buried insulator between the fins and thereby increase the radiation hardness of the structure by providing a leakage path for charge to dissipate.

BACKGROUND OF THE INVENTION

Techniques for improving the radiation hardness of substrates have included implanting atoms or ions, such as silicon, into a buried oxide in the substrate. This serves to create electron traps/recombination centers in the buried oxide. See, for example, U.S. Pat. No. 5,795,813 issued to Hughes et al., entitled “Radiation-Hardening of SOT by Ion Implantation into the buried oxide layer” (hereinafter “U.S. Pat. No. 5,795,813”).

With techniques such as those described in U.S. Pat. No. 5,795,813, care must be taken not to damage the active layer of the wafer during the implantation process. Damage can be controlled by regulating the dose. However, that leaves only a limited window between doses which are too high and will overly damage the active layer and those that are too low and will not be effective for radiation hardening.

Accordingly, improved techniques for producing radiation hardened substrates would be desirable.

SUMMARY OF THE INVENTION

The present invention provides techniques for producing radiation tolerant device structures. In one aspect of the invention, a method for forming a radiation-hardened device is provided. The method includes the steps of: forming fin masks on a silicon-on-insulator (SOI) layer of an SOI wafer, wherein the SOI wafer includes the SOI layer separated from a substrate by a buried insulator; patterning fins in the SOI layer using the fin masks; and implanting at least one dopant into exposed portions of the buried insulator between the fins to increase a radiation hardness of the device structure by providing a path in the buried insulator for charge to dissipate, wherein the fin masks are left in place during the implanting step to prevent damage to the fins.

In another aspect of the invention, a radiation-hardened device is provided. The radiation-hardened device includes: fins patterned in an SOI layer of an SOI wafer, wherein the SOI wafer includes the SOI layer separated from a substrate by a buried insulator; fin masks covering each of the fins; and at least one dopant implanted into exposed portions of the buried insulator between the fins which increases a radiation hardness of the device structure by providing a path in the buried insulator for charge to dissipate.

In yet another aspect of the invention, another method for forming a radiation-hardened device is provided. The method includes the steps of: forming fin masks on a bulk substrate; patterning fins in the bulk substrate using the fin masks; depositing an insulator in between the fins; and implanting at least one dopant into the insulator between the fins to increase a radiation hardness of the device structure by providing a path in the insulator for charge to dissipate, wherein the fin masks are left in place during the implanting step to prevent damage to the fins.

In still yet another aspect of the invention, another radiation-hardened device is provided. The radiation-hardened device includes: fins patterned in a bulk substrate; fin masks covering each of the fins; an insulator in between the fins; and at least one dopant implanted into the insulator between the fins which increases a radiation hardness of the device structure by providing a path in the insulator for charge to dissipate.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Provided herein are techniques for producing radiation hardened substrates which leverage the periodic nature of a Fin Field Effect Transistor (FinFET) structure to enable a low cost and effective radiation tolerant substrate. As will be described in detail below, the present techniques feature a dopant implant to damage the substrate's buried insulator to create a leakage path for charge to dissipate. Unlike conventional processes, the implant is performed post fin patterning but with the fin masks still in place in order to prevent damage to the fins.

The present techniques generally apply in the same manner whether the starting substrate is a silicon-on-insulator (SOI) wafer or a bulk substrate. The first exemplary embodiment described employs an SOI wafer. A second exemplary embodiment involving a bulk substrate is also provided below.

As shown inFIG. 1, the starting platform in this case is a SOI wafer. As is known in the art, an SOI wafer typically includes a SOI layer (e.g., SOI layer102) separated from a substrate (e.g., substrate106) by a buried insulator (e.g., buried insulator104). When the buried insulator is an oxide (such as silicon dioxide (SiO2)), it is commonly referred to as a buried oxide or BOX. Suitable SOI layer materials include, but are not limited to, silicon (Si), strained Si, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), silicon-germanium-carbon (SiGeC), Si alloys, Ge alloys, gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or any combination thereof.

A plurality of fins is next patterned in the SOI layer102. The fin patterning can be carried out in a number of different ways. In one exemplary embodiment, the fins are patterned directly using standard lithography and etching techniques with a patterned fin hardmask. This exemplary embodiment is described by way of reference toFIGS. 2 and 3, below. Alternatively, according to another exemplary embodiment, the fins are patterned in the SOI layer102using a sidewall image transfer or SIT process. An exemplary embodiment employing SIT for fin patterning is described by way of reference toFIGS. 4 and 5, below.

To directly pattern the fins, as shown inFIG. 2, a hardmask material202is first blanket deposited onto the SOI layer102. Suitable hardmask materials include, but are not limited to, nitride hardmask materials such as silicon nitride (SiN). Standard lithography and etching techniques can then be used to pattern the hardmask material202into one or more individual fin hardmasks302. SeeFIG. 3. The fin hardmasks302mark the footprint and location of the fins.

An etch through the fin hardmasks302can then be used to form fins402in the SOI layer102. SeeFIG. 4. By way example only, a suitable etching process for forming fins402in the SOI layer102includes an anisotropic etching process such as reactive ion etching or RIE. The fin hardmasks302are left in place over the fins at least through the implantation step (see below). This will serve to protect the fins from damage.

Alternatively, as highlighted above, a SIT process may be used to pattern the fins. An SIT process advantageously permits patterning features at a sub-lithographic scale. Thus, if the device being produced requires a scaled fin pitch it may be desirable to employ an SIT process. The SIT process involves first patterning one or more mandrels502on the SOI layer102. SeeFIG. 5. According to an exemplary embodiment, the mandrels502are formed by depositing a suitable mandrel material onto the SOI layer102, and then using standard lithography and etching techniques to pattern the material into one or more of the individual mandrels502. An anisotropic etching process, such as reactive ion etching (RIE), may be used to form the mandrels502. Suitable mandrel materials include, but are not limited to, amorphous silicon.

Spacers602are then formed on opposite sides of each of the mandrels502. SeeFIG. 6. To form the spacers602, a spacer material is deposited onto the SOI layer102, burying the mandrels502. The material is then patterned into one or more of the individual spacers602using standard lithography and etching techniques. An anisotropic etching process, such as RIE, may be used to form the spacers602. Suitable spacer materials include, but are not limited to, silicon dioxide (SiO2).

Next, the mandrels502are removed selective to the spacers602. SeeFIG. 7. As will be described in detail below, the spacers will be used as fin masks to pattern the fins in the SOI layer102. By use of the SIT process, the pitch achievable during the mandrel patterning is doubled. Namely, by using the mandrels502to place the spacers602, once the mandrels502are removed there are two spacers602present for each one mandrel502—thus effectively doubling the pitch. The mandrels502can be removed using a selective wet etching process.

The spacers602are then used as masks to pattern fins802in the SOI layer102. SeeFIG. 8. The spacers602are left in place over the fins at least through the implantation step (see below). As provided above, this will θserve to protect the fins from damage.

The remainder of the process is the same regardless of what techniques are used to pattern the fins. Thus, the process depicted inFIGS. 9 and 10may follow from either the structure ofFIG. 4or that ofFIG. 8.

As shown inFIG. 9, one or more dopants are implanted into the buried insulator104. As provided above, the purpose of implanting the dopants is to increase the radiation tolerance (also referred to herein as the radiation hardness) of the device. Namely, when an SOI semiconductor device is exposed to ionizing radiation, a high density of electron hole pairs are generated in the buried insulator. These charges are mobile and tend to migrate to the interface between the SOI layer and the buried insulator. If these charges are allowed to accumulate/build up in the buried insulator, the performance of the device can become severely degraded. For instance, charge accumulation at the SOI layer/buried insulator interface can undesirably lower the threshold voltage of the device. The dopants employed herein are capable of bonding with free electrons. Thus, by implanting these dopants into the buried insulator, a path is created for charge to dissipate rather than accumulate in the buried insulator. Suitable dopants include, but are not limited to, silicon (Si), nitrogen (N), xenon (Xe), germanium (Ge), arsenic (As), phosphorous (P), indium (In), boron (B), boron difluoride (BF2), and combinations thereof. By way of example only, the implantation dose is from about 1×1015to about 8×1016, and ranges therebetween. This dopant implantation step damages the buried insulator. By damage, it is meant that the implanted elements disrupt (or damage) the structure of the target material. For instance, implantation damage can cause point defects in the target material.

It has been advantageously found herein that by performing this radiation hardening implant after the fin patterning, one can leverage the periodic nature of the fins to gain access to the underlying buried insulator thereby enabling radiation hardening implants to be introduced into the buried insulator across the entire device. However, as highlighted above, the fin masks are left in place during the radiation hardening implantation. This prevents any damage to the fins from occurring during the implantation process. The present devices, which are tolerant to higher levels of radiation than conventional semiconductor devices, are referred to herein as radiation tolerant or radiation hardened devices.

As a result of the present radiation hardening implantation process, damaged regions1002of the buried insulator will be present in between each of the fins (i.e., in the exposed portions of the buried insulator104between each of the fins). SeeFIG. 10. As described above, these damaged regions1002will provide a leakage path to reduce charge build-up in the buried insulator104. The result is a radiation-hardened device structure.

FIG. 10further illustrates an optional feature of the present techniques. Namely, as shown inFIG. 10, spacers1004can be formed on opposite sides of each of the fins to protect the fin sidewalls during the implantation process. The spacers1004can be formed on the fin sidewalls from a conformal dielectric film such as silicon nitride (SiN).

The present radiation-hardened structure can be used for a variety of different device applications. For illustrative purposes only, a non-limiting example is now described by way of reference toFIGS. 11-15wherein the present radiation-hardened structure is used as the starting platform for the formation of a fin field effect transistor (FET) device. The device structure ofFIG. 10is used in the following example. As noted above, embodiments are also provided herein where a bulk substrate (i.e., rather than an SOI wafer) is used. The techniques now described by way of reference toFIGS. 11-15would however be applied in the same manner regardless of whether a bulk fin structure or SOI device structure is used.

In this example, a gate-last approach is employed. With a gate-last process, a sacrificial or dummy gate is initially placed over the channel region of the device. Source and drain region processing can be performed, after which the dummy gate can be removed and replaced with the final or replacement gate of the device. This process flow protects the (replacement) gate stack materials from potentially damaging processing conditions (such as elevated temperatures) used in forming the source and drain regions, since the replacement gate is fabricated at the end of the process.

In the example shown, the fin masks are now removed from the fins. However, the fin masks do not impact the dummy gate process, and can be left in place until later, especially if further processing of the fins will be performed post dummy gate removal (for which the fin masks serve to protect the fins).

As shown inFIG. 11, to begin the gate formation process at least one dummy gate1102is formed over the fins. As highlighted above, the dummy gate1102is formed over a portion of each of the fins that will serve as a channel region of the finFET device. The portions of the fins extending out from either side of the dummy gate1102will serve as the source and drain regions of the finFET device. See below. Prior to forming the dummy gate, a dummy gate oxide (not shown) such as SiO2is preferably formed on the fins which will act as a stopping layer and protect the fins during the dummy gate removal later on in the process.

The dummy gate1102can be formed by first blanket depositing a suitable dummy gate material onto the wafer, burying the fins. Suitable dummy gate materials include, but are not limited to, poly-silicon or poly-Si. Standard lithography and etching techniques may be employed to pattern the dummy gate material into one or more individual dummy gates1102.

As shown inFIG. 11, dummy gate spacers1104are preferably formed on opposite sides of the dummy gate1102. The dummy gate spacers1104will be formed on all sides of the dummy gate1102and will serve to offset the gate from what will be the source and drain regions of the finFET device.

Namely, referring to the three-dimensional view of the device (i.e., from a viewpoint A—seeFIG. 11) shown inFIG. 12, formation of doped source and drain regions1202of the device is now described. According to an exemplary embodiment, doped source and drain regions1202are formed from an in-situ doped epitaxial material such as in-situ doped epitaxial Si. Suitable n-type dopants include but are not limited to phosphorous (P), and suitable p-type dopants include but are not limited to boron (B). The use of an in-situ doping process is merely an example, and one may instead employ an ex-situ process such as ion implantation to introduce dopants into the source and drain regions1202of the device. It is also notable that, as shown inFIG. 12, the dummy gate spacers1104are present on all four sides of the dummy gate1102.

The dummy gate1102is then buried in a dielectric material1302. SeeFIG. 13. Placement of the dielectric material1302will permit removal of the dummy gate1102from the channel region of the device and the formation of a replacement gate in its place. In order to permit the dummy gate1102to be removed selective to the dielectric material1302, the dielectric material1302is preferably polished down to, and exposing, a top surface of the dummy gate1102. SeeFIG. 13.

The dummy gate1102is then removed selective to the dielectric material1302and dummy gate spacers1104, forming a trench in the dielectric material1302over the portion of the fins that serve as the channel region of the device. SeeFIG. 14. Since the replacement gate will be formed in the trench, this trench is also referred to herein as a gate trench. SeeFIG. 14. As provided above, the dummy gate1102can be formed from poly-Si. In that case, a poly-Si selective etching process can be used to remove the dummy gate1102selective to the dielectric material1302and the dummy gate spacers1104.

A replacement gate1502is then formed in the gate trench over the portion of the fins that serve as the channel region of the device. SeeFIG. 15. According to an exemplary embodiment, the replacement gate is a metal gate, i.e., what is described is a replacement metal gate process. Prior to placing the replacement gate1502, a gate dielectric (not shown) is preferably formed on the fins, so as to separate the fins from the replacement gate1502. By way of example, in the case of a metal gate, a suitable gate dielectric includes high-κ materials such as hafnium oxide (HfO2) and lanthanum oxide (La2O3). The term “high-κ” as used herein refers to a material having a relative dielectric constant κ which is much higher than that of silicon dioxide (e.g., a dielectric constant κ=25 for hafnium oxide rather than 4 for silicon dioxide).

To form the replacement gate1502, a gate material or combination of materials is/are then deposited into the gate trench on the gate dielectric. By way of example only, in the case of a metal gate, a combination of gate metals may be used. For instance, a workfunction setting metal layer may be deposited onto the gate dielectric, followed by a filler metal layer. Suitable workfunction setting metals include, but are not limited to, n-type workfunction setting metals such as titanium nitride (TiN) and tantalum nitride (TaN), and p-type workfunction setting metals such as tungsten (W). Suitable filler metals include, but are not limited to, aluminum (Al).

The replacement gate is now formed. Any further processing, if so desired, can be performed to complete the device.

As described above, the use of an SOI wafer is merely an example, and the present techniques may be employed in the same general manner as described above when starting with a bulk substrate. The process with a bulk substrate differs only in the sense that isolation between the fins is achieved using, e.g., shallow trench isolation (STI), as opposed to a buried insulator. The present dopant implants can then be performed in the STI regions. For clarity, an illustration of the present process in the context of a bulk substrate is now described by way of reference toFIGS. 16-18.

As shown inFIG. 16, the starting platform in this case is a bulk substrate1602. Suitable materials for the bulk substrate1602include, but are not limited to, Si, strained Si, SiC, Ge, SiGe, SiGeC, Si alloys, Ge alloys, GaAs, InAs, InP, or any combination thereof.

A plurality of fins1604is next patterned in the bulk substrate1602. In the same manner as described above, the fins may be directly patterned using standard lithography and etching techniques, or using a pitch doubling technique such as SIT. Both of these processes were described in detail above. Each uses fin masks1606(i.e., a hardmask in the case of a direct patterning process and a mandrel-placed spacer in the case of a SIT process—see above) to pattern the fins1604. These fin masks1606are left in place over the fins at least through the implantation step (see below). This will serve to protect the fins from damage.

In order to form an isolation region between the fins1604, an insulator1702is deposited onto the substrate1602and in between the fins1604. SeeFIG. 17. By way of example only, the insulator1702can be an oxide material, such as a conventional shallow trench isolation or STI oxide.

Next, in the same manner as described above, one or more dopants are implanted into the insulator1702to increase the radiation tolerance (hardness) of the device by creating a path for charge to dissipate. The details for this implantation step were provided above, including suitable dopants, dose, etc. As above, the fin masks1606are left in place during the dopant implant to protect the fins.

As a result of the present radiation hardening implantation process, damaged regions1802of the insulator1702will be present in between each of the fins1604. SeeFIG. 18. As described above, these damaged regions1802will provide a leakage path to reduce charge build-up in the insulator1702. The result is a radiation-hardened device structure.

FIG. 18further illustrates an optional feature of the present techniques. Namely, as shown inFIG. 18, spacers1804can be formed on opposite sides of each of the fins1604to protect the fin sidewalls during the implantation process. The spacers1804can be formed on the fin sidewalls from a conformal dielectric film such as silicon nitride (SiN).