Fin field effect transistor (FinFET) device structure with air gap and method for forming the same

A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method for forming a FinFET device structure also includes forming a first spacer over a sidewall of the gate structure and forming a second spacer over the first spacer. The method for forming a FinFET device structure further includes etching the second spacer to form a gap and forming a mask layer over the gate structure and the first spacer after the gap is formed. In addition, the mask layer extends into the gap in such a way that the mask layer and the fin structure are separated by an air gap in the gap.

BACKGROUND

As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin vertical “fin” (or fin structure) extending from a substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over the fin. The advantages of a FinFET may include reducing the short channel effect and providing a higher current flow.

Although existing FinFET devices and methods of fabricating FinFET devices have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The method for forming the FinFET device structure may include forming an air gap between a gate structure and a contact, such that the capacitance between the gate structure and the contact may be reduced. In addition, the air gap and the gate structure may be covered by a mask layer. Therefore, the air gap and the gate structure may be protected during the subsequent etching process.

FIGS. 1A-1Nare perspective representations of various stages of forming a FinFET device structure100a, in accordance with some embodiments of the disclosure.FIGS. 2A-2Gare cross-sectional representations of various stages of forming the FinFET device structure100ashown inFIG. 1H-1N, in accordance with some embodiments of the disclosure.FIGS. 2A-2Gare cross-sectional representations taken along line a-a′ ofFIGS. 1H-1N.

A substrate102is provided as shown inFIG. 1Ain accordance with some embodiments. The substrate102may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, the substrate102may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP. In some embodiments, the substrate102includes an epitaxial layer. For example, the substrate102has an epitaxial layer overlying a bulk semiconductor.

Afterwards, a dielectric layer104and a mask layer106are formed over the substrate102, and a patterned photoresist layer108is formed over the mask layer106, as shown inFIG. 1Ain accordance with some embodiments. The patterned photoresist layer108may be formed by a deposition process and a patterning process.

The deposition process for forming the patterned photoresist layer108may include a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, a sputtering process, or another applicable process. The patterning process for forming the patterned photoresist layer108may include a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

Moreover, the dielectric layer104may be a buffer layer between the substrate102and the mask layer106. In some embodiments, the dielectric layer104is used as a stop layer when the mask layer106is removed. The dielectric layer104may be made of silicon oxide. The mask layer106may be made of silicon oxide, silicon nitride, silicon oxynitride, or another applicable material. In some other embodiments, more than one mask layer106is formed over the dielectric layer104.

The dielectric layer104and the mask layer106may be formed by deposition processes, which may include a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, a sputtering process, or another applicable process.

After the patterned photoresist layer108is formed, the dielectric layer104and the mask layer106are patterned by using the patterned photoresist layer108as a mask, as shown inFIG. 1Bin accordance with some embodiments. As a result, a patterned pad layer105and a patterned mask layer107are obtained. Afterwards, the patterned photoresist layer108is removed.

Next, an etching process is performed on the substrate102to form a fin structure110by using the patterned dielectric layer105and the patterned mask layer107as a mask. The etching process may be a dry etching process or a wet etching process.

In some embodiments, the substrate102is etched by a dry etching process. The dry etching process includes using a fluorine-based etchant gas, such as SF6, CxFy, NF3or a combination thereof. The etching process may be a time-controlled process, and continue until the fin structure110reaches a predetermined height. In some other embodiments, the fin structure110has a width that gradually increases from the top portion to the lower portion.

After the fin structure110is formed, an insulating layer112is formed to cover the fin structure110, the patterned pad layer105, and the patterned mask layer107over the substrate102, as shown inFIG. 1Cin accordance with some embodiments.

In some embodiments, the insulating layer112is made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or another low-k dielectric material. The insulating layer112may be deposited by a chemical vapor deposition (CVD) process, a spin-on-glass process, or another applicable process.

Next, the insulating layer112is thinned or planarized to expose the top surface of the patterned mask layer107. In some embodiments, the insulating layer112is thinned by a chemical mechanical polishing (CMP) process. Afterwards, the patterned dielectric layer105and the patterned mask layer107are removed.

After the patterned dielectric layer105and the patterned mask layer107are removed, an upper portion of the insulating layer112is removed to form an isolation structure114, as shown inFIG. 1Din accordance with some embodiments. The isolation structure114may be a shallow trench isolation (STI) structure surrounding the fin structure110.

In some embodiments, a portion of the fin structure110is embedded in the isolation structure114. More specifically, a lower portion of the fin structure110is surrounded by the isolation structure114, while an upper portion of the fin structure110protrudes from the isolation structure114. The isolation structure114is configured to prevent electrical interference or crosstalk.

After the isolation structure114is formed, dummy gate structures120are formed across the fin structure110and extends over the isolation structure114, as shown inFIG. 1Ein accordance with some embodiments. In some embodiments, each of the dummy gate structures120includes a dummy gate dielectric layer116and a dummy gate electrode layer118formed over the dummy gate dielectric layer116.

After the dummy gate structures120are formed, first spacers122, second spacers124and third spacers126are formed on opposite sidewalls of each of the dummy gate structures120. More specifically, a pair of first spacers122is formed on opposite sidewalls of each of the dummy gate structures120, a pair of second spacers124is formed over the first spacers122, and a pair of third spacers126is formed over the second spacers124.

In order to improve the speed of the FinFET device structure100a, the first spacers122, the second spacers124, and the third spacers126are made of low-k dielectric materials. In some embodiments, the low-k dielectric materials have a dielectric constant (k value) less than about 4. Examples of low-k dielectric materials include, but are not limited to, silicon oxide, silicon nitride, silicon carbonitride (SiCN), silicon oxide carbonitride (SiOCN), fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide.

In some other embodiments, the first spacers122, the second spacers124, and the third spacers126are made of extreme low-k (ELK) dielectric materials with a dielectric constant less than about 2.5. In some embodiments, ELK dielectric materials include carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), polytetrafluoroethylene (PTFE) (Teflon), or silicon oxycarbide polymers (SiOC). In some embodiments, ELK dielectric materials include a porous version of an existing dielectric material, such as hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon oxide (SiO2).

In some embodiments, the first spacers122and the third spacers126are made of the same material, and the material of the second spacers124is different from the material of the first spacers122and the third spacers126. For example, the first spacers122and the third spacers126are made of nitride, and the second spacers124are made of oxide. In addition, the first spacers122, the second spacers124, and the third spacers126are deposited by deposition processes, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a spin coating process, or another applicable process.

Afterwards, source/drain (S/D) structures130are formed over the fin structure110. In some embodiments, portions of the fin structure110adjacent to the dummy gate structures120are recessed to form recesses at two sides of the fin structure110, and a strained material is grown in the recesses by an epitaxial (epi) process to form the S/D structures130. In addition, the lattice constant of the strained material may be different from the lattice constant of the substrate102. In some embodiments, the S/D structures130include Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, or the like.

After the source/drain (S/D) structures130are formed, a contact etch stop layer (CESL)131is formed over the substrate102, and an inter-layer dielectric (ILD) structure132is formed over the CESL131. More specifically, the CESL131is formed over the S/D structures130, the isolation structure114, and the sidewalls of the third spacers126. In some embodiments, the CESL131is made of silicon nitride, silicon oxynitride, and/or other applicable materials. Moreover, the CESL131may be formed by plasma enhanced CVD, low-pressure CVD, atomic layer deposition (ALD), or other applicable processes.

In some embodiments, the ILD structure132includes multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. In addition, the ILD structure132may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), spin-on coating, or another applicable process.

Afterwards, a planarizing process is performed on the ILD structure132until the top surfaces of the dummy gate structures120are exposed, as shown inFIG. 1Ein accordance with some embodiments. After the planarizing process, the top surfaces of the dummy gate structures120may be substantially level with the top surfaces of the first spacers122, the second spacers124, the third spacers126, and the ILD structure132. In some embodiments, the planarizing process includes a grinding process, a chemical mechanical polishing (CMP) process, an etching process, another applicable process, or a combination thereof.

Next, the dummy gate structures120are removed to form trenches134in the ILD structure132, as shown inFIG. 1Fin accordance with some embodiments. More specifically, each of the trenches134is formed between each pair of first spacers122, and the fin structure110is exposed by the trenches134. The dummy gate dielectric layer116and the dummy gate electrode layer118are removed by an etching process, such as a dry etching process or a wet etching process.

After the trenches134are formed, gate structures140are formed in the trenches134, as shown inFIG. 1Gin accordance with some embodiments. In some embodiments, each of the gate structures140includes a gate dielectric layer136and a gate electrode layer138. In addition, each of the gate structures140may include a work function layer (not shown) between the gate dielectric layer136and the gate electrode layer138.

Each of the gate dielectric layers136may be a single layer or multiple layers. In some embodiments, the gate dielectric layers136are made of silicon oxide, silicon nitride, silicon oxynitride (SiON), dielectric material(s) with high dielectric constant (high-k), or a combination thereof. In some embodiments, the gate dielectric layers136are deposited by a plasma enhanced chemical vapor deposition (PECVD) process or a spin coating process.

Moreover, the gate electrode layers138are made of a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or another applicable material, in accordance with some embodiments. The gate electrode layers138may be formed by a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a high density plasma CVD (HDPCVD) process, a metal organic CVD (MOCVD) process, or a plasma enhanced CVD (PECVD) process.

The work function layers (not shown) may be made of metal materials, and the metal materials may include N-work-function metal or P-work-function metal. The N-work-function metal may include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr) or a combination thereof. The P-work-function metal may include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru) or a combination thereof.

After the gate structures140are formed, a top portion of each of the gate structures140is removed, as shown inFIGS. 1H and 2Ain accordance with some embodiments. In some embodiments, the top portion of each of the gate dielectric layer136and the gate electrode layer138are removed by an etching process, such as a dry etching process. The dry etching process may include a plasma etching process. Therefore, first openings142are formed above the remaining gate structures140′, and sidewalls of the first spacers122are exposed by the first openings142.

After the first openings142are formed, the first spacers122, the second spacers124, and the third spacers126have a first height H1above the top surface of the fin structure110, and the remaining gate structures140′ have a second height H2above the top surface of the fin structure110. In some embodiments, a ratio (H1/H2) of the first height H1to the second height H2is in a range from about 1.5 to about 2.5. In some embodiments, the first height H1is in a range from about 45 nm to about 135 nm, and the second height H2is in a range from about 30 nm to about 55 nm.

Moreover, the first spacers122have a first width W1, the second spacers124have a second width W2, and the third spacers126have a third width W3. In some embodiments, each of the first width W1, the second width W2, and the third width W3is in a range from about 1 nm to about 10 nm. In some embodiments, the first width W1, the second width W2, and the third width W3are substantially the same.

Next, the first spacers122, the second spacers124, and the third spacers126are partially removed through the first openings142, as shown inFIGS. 1I and 2Bin accordance with some embodiments. More specifically, a top portion of each of the first spacers122, a top portion of each of the second spacers124, and a top portion of each of the third spacers126are removed by an etching process, such as a dry etching process. As a result, a portion of the sidewalls of the CESL131are exposed, and the first spacers122′, the second spacers124′ and the third spacers126′ are left.

Moreover, in some embodiments, the top surfaces of the first spacers122′, the second spacers124′, and the third spacers126′ are substantially coplanar with each other. In some embodiments, the first spacers122′, the second spacers124′, and the third spacers126′ have the second height H2, which is substantially the same as the height of the remaining gate structures140′.

Afterwards, a top portion of each of the remaining gate structures140′ is removed such that second openings143are formed below the first openings142, as shown inFIGS. 1J and 2Cin accordance with some embodiments.

More specifically, after the top portions of the first spacers122, the second spacers124, and the third spacers126are removed through the first openings142, the top portion of each of the remaining gate structures140′ exposed by the first openings142are removed by an etching process, such as a dry etching process. Therefore, the second openings143are formed below the first openings142and above the remaining gate structures140″, and a portion of the sidewalls of the first spacers122′ are exposed through the second openings143.

It should be noted that, the remaining gate structures140″ below the second openings143have a third height H3above the top surface of the fin structure110. In some embodiments, a ratio (H1/H3) of the first height H1to the third height H3is in a range from about 4 to about 7. In some embodiments, the third height H3is in a range from about 10 nm to about 30 nm.

When the ratio (H1/H3) of the first height H1to the third height H3is too large, the third height H3of the remaining gate structures140″ may be too small, and high leakage current may occur. When the ratio (H1/H3) of the first height H1to the third height H3is too small, the third height H3of the remaining gate structures140″ may be too large, and the remaining gate structures140″ may not be fully protected by the mask layer146(formed subsequently) during the self-aligned etching for forming the contact openings148in the subsequent processes.

After the second openings143are formed, the second spacers124′ are removed, as shown inFIGS. 1K and 2Din accordance with some embodiments. The second spacers124′ are removed by an etching process, such as a dry etching process. As a result, gaps144between the first spacers122′ and the third spacers126′ are obtained, and a portion of the fin structure110is exposed by the gaps144.

As described previously, the material for forming the first spacers122′ and the third spacers126′ may be the same, and the material for forming the first spacers122′ and the third spacers126′ may be different. In some embodiments, the etching selectivity of the first spacers122′ with respect to the second spacers124′ and the etching selectivity of the third spacers126′ with respect to the second spacers124′ are relatively high. Therefore, the second spacers124′ are removed by the etching process while the first spacers122′ and the third spacers126′ may be substantially left, such that the gaps144are formed.

The term of “selectivity” or “etching selectivity” is defined as the ratio of etching rate of one material (the reference material) relative to another material (the material of interest). An increase in etching selectivity means that the selected material, or material of interest, is harder to etch. A decrease in etching selectivity means that the selected material is easier to etch. More specifically, the high etching selectivity of the first spacers122′ and the third spacers126′ means that the first spacers122′ and the third spacers126′ are not easy to damage or etch during the etching process of the second spacers124′.

In some embodiments, a top portion of each of the first spacers122′ is simultaneously removed during the etching process of the second spacers124′. In this case, the top surfaces of the third spacers126′ are higher than the top surfaces of the first spacers122′ after the etching process of the second spacers124′ is performed. However, the top surfaces of the third spacers126′ and the top surfaces of the first spacers122′ are still higher than the top surfaces of the remaining gate structures140′ after the second spacers124′ are removed.

Next, a mask layer146is formed over the remaining gate structures140″, the first spacers122′, and the third spacers126′, as shown inFIGS. 1L and 2Ein accordance with some embodiments. The mask layer146is used as a mask for performing a self-aligned etching process to form contacts electrically connected to the S/D structures130, which will be described in more detail later. The first openings142and the second openings143are filled by the mask layer146. In should be noted that, the gaps144are covered by the mask layer146such that air gaps145are formed in the gaps144.

In some embodiments, the mask layer146extends into the gaps144such that the mask layer146and the fin structure110are separated by the air gaps145in the gaps144. It should be noted that, a top portion of each of the first spacers122′ is embedded in the mask layer146. More specifically, the top surfaces of the first spacers122′ are higher than the interfaces between the mask layer146and the air gaps145. In some embodiments, the interfaces between the mask layer146and the air gaps145are higher than the top surfaces of the remaining gate structures140″.

The mask layer146has a fourth height H4over the remaining gate structures140″. In some embodiments, a ratio (H1/H4) of the first height H1to the fourth height H4is in a range from about 4 to about 5. In some embodiments, the fourth height H4is in a range from about 10 nm to about 30 nm. In some other embodiments, the fourth height H4is in a range from about 30 nm to about 60 nm.

When the ratio (H1/H4) of the first height H1to the fourth height H4is too large, the fourth height H4of the mask layer146may be too small, and the mask layer146may not be able to protect the remaining gate structures140″ from damage during the subsequent etching processes. When the ratio (H1/H4) of the first height H1to the fourth height H4is too small, the remaining gate structures140″ may be too small, and high leakage current may occur.

Moreover, the remaining gate structures140″ have a fourth width W4, and the mask layer146has a fifth width W5. In some embodiments, the fifth width W5is greater than the fourth width W4, and the difference between the fifth width W5and the fourth width W4is in a range from about 5 nm to about 10 nm. In some embodiments, a ratio (W5/W4) of the fifth width W5to the fourth width W4is in a range from about 1.5 to about 2.

When the ratio (W5/W4) of the fifth width W5to the fourth width W4is too large, the fourth width W4of the remaining gate structures140″ may be too small, and high leakage current may occur. When the ratio (W5/W4) of the fifth width W5to the fourth width W4is too small, the air gaps145may be too narrow, and the capacitance between the remaining gate structures140″ and the contacts152(formed subsequently) may not be reduced efficiently.

In some embodiments, the mask layer146is made of oxide or silicon nitride. In some other embodiments, the mask layer146is made of silicon oxide, silicon carbonitride (SiCN), silicon oxide carbonitride (SiOCN), or SiLK. It should be noted that the material of the mask layer146is different from the material of the ILD structure132. In some embodiments, the mask layer146may be formed by deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or another applicable process. In addition, the mask layer146may be formed by a single deposition process or multiple deposition processes.

After the mask layer146is formed, a portion of the ILD structure132is removed to form contact openings148, as shown inFIGS. 1M and 2Fin accordance with some embodiments. Specifically, the ILD structure132and the CESL131are partially removed by an etching process, such as a dry etching process. As a result, a portion of each of the S/D structures130is exposed by the contact openings148.

It should be noted that, the etching selectivity of the ILD structure132with respect to the mask layer146is high. Therefore, the etching process for forming the contact openings148is a self-aligned etching process. More specifically, the portion of the ILD structure132is removed by the etching process while the mask layer146is not removed. Since the remaining gate structures140″ are protected by the mask layer146, the remaining gate structures140″ are not damaged by the etchant during the etching process for forming the contact openings148.

In some embodiments, the width of each of the air gaps145is the same as the second width W2of the second spacers124′, and the air gaps145have a fifth height H5above the top surface of the fin structure110. In some embodiments, an aspect ratio (H5/W2) of each of the air gaps145is in a range from about 3 to about 6.

When the aspect ratios of the air gaps145are too large, the capacitances between the remaining gate structures140″ and the contacts152may not be reduced efficiently. When the aspect ratios of the air gaps145are too small, the air gaps145may be filled up by the mask layer146easily, such that the capacitances between the remaining gate structures140″ and the contacts152may not be reduced efficiently as well.

In some other embodiments, the second spacers124′ are not entirely removed. For example, portions of the second spacers124′ are left after the etching process of the second spacers124′. In this case, the width of each of the air gaps145may be different from the second width W2of the second spacers124′, and the width of each of the air gaps145may be in a range from about 1 nm to about 5 nm. For example, the width of each of the air gaps145may be about 3 nm.

Furthermore, in some embodiments, the fifth height H5of the air gaps145is greater than the third height H3of the remaining gate structures140′. In some embodiments, a difference between the fifth height H5and the third height H3is in a range from about 1 nm to about 5 nm. For example, a difference between the fifth height H5and the third height H3is about 3 nm.

In addition, even if the top portions of the first spacers122′ are slightly etched during the etching process of the second spacers124′, the height of the first spacers122′ is similar to the second height H2of the third spacers126′. In some embodiments, a ratio (H2/H3) of the second height H2to the third height H3is in a range from about 2 to about 3.

When the ratio (H2/H3) of the second height H2to the third height H3is too large, the remaining gate structures140″ may be too small, and high leakage current may occur. When the ratio (H2/H3) of the second height H2to the third height H3is too small, the remaining gate structures140″ may not be fully protected by the mask layer146during the self-aligned etching for forming the contact openings148in the subsequent processes.

Afterwards, a barrier layer150is formed over the bottom surface and the sidewalls of each of the contact openings148, and a contact152is formed over each of the barrier layer150, as shown inFIGS. 1N and 2Gin accordance with some embodiments. Each of the barrier layers150surrounds each of the contacts152, and the ILD structure132surrounds the barrier layers150. The contacts152are electrically connected to the S/D structures130.

In some embodiments, the barrier layers150are made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW) or another applicable material. In some embodiments, the barrier layers150are made of Ti/TiN/W, and tungsten (W) in the barrier layers150has a smaller grain size than the grain size of the contacts152when the contacts152are made of tungsten (W). In some embodiments, the barrier layers150are formed by a deposition process, such as a chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, plating process or another application process.

In some embodiments, the contacts152are made of tungsten (W), cobalt (Co), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), platinum (Pt), molybdenum (Mo), silver (Ag), manganese (Mn), zirconium (Zr), ruthenium (Ru), or another application material. In some embodiments, the contacts152are formed by a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a plating process, or another application process.

In addition, a glue layer may optionally be formed between each of the barrier layers150and each of the contacts152. The glue layers are used to improve adhesion between the barrier layers150and the contacts152. After the contacts152are formed, the FinFET device structure100ais obtained.

Moreover, in order to protect the remaining gate structures140″, the mask layer146is formed to cover the top surfaces of the remaining gate structures140″, and the fifth width W5of the mask layer146is greater than the fourth width W4of the remaining gate structures140″. In addition, the top surfaces of the first spacers122′ are higher than the top surfaces of the remaining gate structures140″, and the top portions of the first spacers122′ are embedded in the mask layer146. As a result, the remaining gate structures140″ will not be damaged by the etching etchant which is used for forming the contact openings148.

It should be noted that, in order to reduce the capacitances between the remaining gate structures140″ and the contacts152, the air gaps145, which have a dielectric constant (about 1) lower than that of the first spacers122′ and the third spacers126′, are formed between the remaining gate structures140″ and the contacts152. As a result, the performance of the FinFET device structure100amay be increased.

FIG. 3is a cross-sectional representation of a modified FinFET device structure100b, in accordance with some embodiments of the disclosure. The FinFET device structure100bis similar to the FinFET device structure100aofFIG. 2G, and the difference betweenFIG. 3andFIG. 2Gis that the third spacers126′ are not formed inFIG. 3. Therefore, the air gaps145are sandwiched between the CESL131and the first spacers122′.

FIG. 4is a cross-sectional representation of a modified FinFET device structure100c, in accordance with some embodiments of the disclosure. The FinFET device structure100cis similar to the FinFET device structure100aofFIG. 2G, and the difference betweenFIG. 4andFIG. 2Gis that the heights of the air gaps145inFIG. 4are smaller than the heights of the air gaps145inFIG. 2G.

More specifically, the air gaps145inFIG. 4have a sixth height H6above the top surface of the fin structure110, which is greater than the fifth height H5of the air gaps145inFIG. 2G. Therefore, the top surfaces of the remaining gate structures140″ are higher than the interfaces between the mask layer146and the air gaps145inFIG. 4.

FIG. 5is a cross-sectional representation of a modified FinFET device structure100d, in accordance with some embodiments of the disclosure. The FinFET device structure100dis similar to the FinFET device structure100aofFIG. 2G, and the difference betweenFIG. 5andFIG. 2Gis that the second spacers124′ are partially left after the etching process of the second spacers124′ is performed.

As a result, the fin structures110are covered by remaining portions124″ of the second spacers124′, and the mask layer146is separated from the remaining portions124″ of the second spacers124′ by the air gaps145.

FIG. 6is a cross-sectional representation of a modified FinFET device structure100e, in accordance with some embodiments of the disclosure. The FinFET device structure100eis similar to the FinFET device structure100aofFIG. 2G, and the difference betweenFIG. 6andFIG. 2Gis that some of the gaps144between the first spacers122′ and the third spacers126′ are entirely filled by the mask layer146.

For example, the mask layer146is separated from the fin structure110by one of the air gaps145at the left side of the left remaining gate structure140″, while the mask layer146is in direct contact with the fin structure110at the right side of the left remaining gate structure140″.

FIG. 7is a cross-sectional representation of a modified FinFET device structure100f, in accordance with some embodiments of the disclosure. The FinFET device structure100fis similar to the FinFET device structure100dofFIG. 5, and the difference betweenFIG. 7andFIG. 5is that some of the gaps144between the first spacers122′ and the third spacers126′ are entirely filled by the mask layer146.

For example, the mask layer146is separated from the remaining portions124″ of the second spacers124′ by one of the air gaps145at the left side of the left remaining gate structure140″, while the mask layer146is in direct contact with the remaining portions124″ of the second spacers124′ at the right side of the left remaining gate structure140″.

FIG. 8is a cross-sectional representation of a modified FinFET device structure100g, in accordance with some embodiments of the disclosure. The FinFET device structure100gis similar to the FinFET device structure100aofFIG. 2G, and the difference betweenFIG. 8andFIG. 2Gis that the mask layer146is replaced with a first mask layer146′ and a second mask layer146″ inFIG. 8.

More specifically, the first mask layer146′ is conformally formed covering the first spacers122′, the third spacers126′, the bottom surface and sidewalls of the gaps144between the first spacers122′ and the third spacers126′, and the sidewalls of the CESL131. After the first mask layer146′ is formed, the second mask layer146″ is formed over the first mask layer146′. As a result, the air gaps145are enclosed by the first mask layer146′ and the second mask layer146″.

In some embodiments, the first mask layer146′ is made of silicon, nitride, silicon nitride or another applicable material. In some embodiments, the first mask layer146is formed by a deposition process, such as an atomic layer deposition (ALD) process or another applicable process.

In some embodiments, the second mask layer146″ is made of oxide, silicon oxide or another applicable material. In some embodiments, the second mask layer146″ is formed by a deposition process, such as a chemical vapor deposition (CVD) process or another applicable process.

As described previously, the first spacers122′ are formed over the sidewalls of the remaining gate structures140″ and the second spacers124′ are formed over the sidewalls of the first spacers122′. The second spacers124′ are removed by etching such that gaps144are formed between the first spacers122′ and the contact etch stop layer (CESL)131adjacent to the remaining gate structures140″. After the second spacers124′ are removed, the mask layer146is formed over the remaining gate structures140″ and the first spacers122′. The mask layer146extends into upper portions of the gaps144such that lower portions of the gaps144forms air gaps145. Therefore, the remaining gate structures140″ may be protected by the mask layer146during the subsequent processes. Moreover, the air gaps145covered by the mask layer146may be used to reduce the capacitance between the remaining gate structures140″ and the contacts152, which are electrically connected to the source/drain (S/D) structures130.

Embodiments of a FinFET device structure and method for forming the same are provided. The method for forming the FinFET device structure includes forming a first spacer and a second spacer over a sidewall of the gate structure, and forming a gap by etching the second spacer. After the gap is formed, a mask layer is formed covering the gate structure, the first spacer and the gap, such that an air gap is formed adjacent to the gate structure. Since the dielectric constant of the air gap is lower than that of the first spacer, the capacitance between the gate structure and the adjacent contact may be reduced, and the performance of the FinFET device structure may be increased.

In some embodiments, a method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method for forming a FinFET device structure also includes forming a first spacer over a sidewall of the gate structure and forming a second spacer over the first spacer. The method for forming a FinFET device structure further includes etching the second spacer to form a gap and forming a mask layer over the gate structure and the first spacer after the gap is formed. In addition, the mask layer extends into the gap such that the mask layer and the fin structure are separated by an air gap in the gap.

In some embodiments, a method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method for forming a FinFET device structure also includes forming a first spacer over a sidewall of the gate structure and forming a second spacer over a sidewall of the first spacer. The method for forming a FinFET device structure further includes removing a first portion of the gate structure to form a first opening and partially removing the first spacer and the second spacer through the first opening. In addition, the method for forming a FinFET device structure includes removing a second portion of the gate structure to form a second opening below the first opening and etching the second spacer to form a gap after the second opening is formed. The method for forming a FinFET device structure also includes forming a mask layer covering the gate structure, the first spacer and the gap such that an air gap is formed in the gap.

In some embodiments, a FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure formed over the fin structure. The FinFET device structure also includes a first spacer formed on a sidewall of the gate structure and a contact formed over the fin structure and adjacent to the gate structure. The contact and the first spacer have an air gap therebetween. The FinFET device structure further includes a mask layer formed over the gate structure, the first spacer and the air gap. The top surface of the first spacer is higher than the interface between the mask layer and the air gap.