Debugging module for electronic device and method thereof

A debugging module for connecting an IC to a JTAG debugger device includes a JTAG interface, an earphone circuit, a USB interface, a switching unit, and a reset circuit. The earphone circuit is electrically connected to the JTAG interface via the switching unit. The USB interface and the reset circuit are electrically connected to the JTAG interface. When a JTAG debugger device is connected to the earphone circuit and the USB interface, the earphone circuit and the USB interface, respectively, can establish a connection between the JTAG debugger device and the JTAG interface.

BACKGROUND

1. Technical Field

The disclosure generally relates to debugging modules for electronic device, particularly to a Joint Test Action Group (JTAG) interface debugging module and method thereof for electronic devices.

2. Description of Related Art

The use of various functional component (blocks) and component libraries to create a complex integrated circuit (IC) in portable electronic devices is becoming increasingly common. These complex ICs are difficult to test. Traditionally, these ICs incorporate a JTAG interface as a mechanism for emulating and debugging an IC during testing. The JTAG interface is used to download debugging or other testing software from an external device, e.g., a JTAG debugger device, to the functional blocks located on the IC during testing. This standard has been adopted by the Institute of Electrical and Electronics Engineers and is now defined as IEEE Standard 1149.1. During testing, pins of the JTAG interface electrically connect with the JTAG debugger device via welding a wire from the JTAG interface to the JTAG debugger device.

Therefore, there is room for improvement within the art.

DETAILED DESCRIPTION

Referring toFIGS. 1-2, a debugging module100includes a JTAG interface10, an earphone circuit20, a switching unit30, a USB interface40, and a reset circuit50. The earphone circuit20is electrically connected to the JTAG interface10via the switching unit30. The USB interface40and the reset circuit50are electrically connected to the JTAG interface10.

The JTAG interface10includes eight pins. The eight pins are contacts on an IC of a portable electronic device for connecting the portable electronic device to a JTAG debugger device200. The eight pins are VDD pin11, grounding (GND) pin12, test data input (TDI) pin13, test data output (TDO) pin14, test clock input (TCK) pin15, test mode selection input (TMS) pin16, a first test reset input (RST) pin17and a second test reset input (TRST) pin18. The GND pin12is electrically connected to ground. The TDI pin13, TDO pin14, and TCK pin15are electrically connected to the switching unit30. The VDD pin11, TMS pin16, and the RST pin17are electrically connected to the USB interface40. The TDI pin13, TDO pin14, TCK pin15, VDD pin11, TMS pin16, and the RST pin17can be all connected to the JTAG debugger device200via the earphone circuit20and the USB interface40. The TRST pin18is electrically connected to the reset circuit50.

The earphone circuit20include a grounding (GND) pin21, an audio input (MIC) pin22, two left audio output (EAR_L0, EAR_L1) pins23,24, two right audio output (EAR_R0, EAR_R1) pins25,26. The GND pin21is electrically connected to ground. The MIC pin22, EAR_L0pin23, EAR_L1pin24, the EAR_R025, and the EAR_R126are electrically connected to audio wires of the portable electronic device to input or output audio signals. The MIC pin22, the EAR-L0pin23, and the EAR_R1pin26are electrically connected to the switching unit30. The earphone circuit20includes an earphone jack (not shown) set on the portable electronic device for connecting a JTAG debugger device200.

The switching unit30includes a grounding (GND) pin301, a power (VDD) pin302, three input (YA, YB, YC) pins303˜305, and six output (IA0, IA1, IB0, IB1, IC0, IC1) pins306˜311. The GND pin301is electrically connected to ground. The VDDpin302is electrically connected to a power VO. The YA pin303, YB pin304, and the YC pin305forms a first pin group correspondingly connected to the MIC pin22, the EAR_L0pin23, and the EAR_R1pin26of the earphone circuit20. The IA0pin306, IB0pin308, IC0pin310form a second pin group correspondingly connected to the TDI pin13, TDO pin14, and the TCK pin15of the JTAG interface10. The IA1pin307, IB1pin309, and IC1pin311form a third pin group correspondingly connected to the MIC pin22, EAR_L0pin23and the EAR_R1pin26of the earphone circuit20. The second pin group connects to the third pin group when the first pin group detects a JTAG debugger device200is electrically connected to the earphone circuit20. The earphone circuit20establishes a connection between the JTAG interface10and the JTAG debugger device200.

The USB interface40is a mini USB interface including a GND pin41, a VCCpin42, an ID pin43, a D+ pin44, and a D− pin45. The GND pin41is electrically connected to ground. The VCCpin42is electrically connected to a power VUSBfor inputting power. The ID pin43is for identifying. The D+ pin44and the D− pin45are for transmitting data. The ID pin43, the D+ pin44, and the D− pin45are respectively connected to the VDDpin11, TMS pin16and the RST pin17.

The reset circuit50is formed by a resistance with zero ohm. One end of the resistance is electrically connected to the TRST pin18. Another end of the resistance is electrically connected to an IC of the portable electronic device to receive an initial signal.

During test, the earphone circuit30and the USB interface40establish a connection between the JTAG debugger device200and the JTAG interface10. Therefore, testers can conveniently and safely operate an emulation of an IC by connecting a plug of a common JTAG debugger device200to the jack of the earphone circuit20and USB interface40without welding any pins of the JTAG interface10.