EEPROM device and forming method and erasing method thereof

An EEPROM device, a forming method thereof, and a method for implementing an erase operation to the device are provided. The EEPROM device includes: a semiconductor substrate having active regions therein; a word line disposed on a first active region; float gate dielectric layers disposed on second active regions; float gates disposed on the float gate dielectric layers, wherein each of the float gates has a width larger than that of the second active region; control gates disposed on control gate dielectric layers which are disposed on the float gates; an isolation oxide layer disposed between the word line and the float gates along with the control gates; and bit line doping regions disposed on third active regions. Accordingly, an erase operation can be implemented from a bit line, and coupling ratios of a float gate to a control gate and to a bit line doping region can be improved.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Chinese patent application No. 201410081177.9, filed on Mar. 6, 2014, and entitled “EEPROM DEVICE AND FORMING METHOD AND ERASING METHOD THEREOF”, the entire disclosure of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure generally relates to memory devices, and more particularly, to an Electrically Erasable and Programmable Read Only Memory (EEPROM) device, a method for forming the EEPROM device, and a method for implementing an erase operation to the EEPROM device.

BACKGROUND

Read Only Memory (ROM) devices are non-volatile memory devices, thus information and data stored therein will not be lost when power supplies are shut off. Erasable and Programmable Read Only Memory (EPROM) devices have expanded applications of the ROM devices to achieve an erase operation and a re-write operation. However, ultraviolet rays are required to achieve the erase operation, thus manufacturing costs of the EPROM devices are high. Furthermore, when implementing an erase operation to revise data, all programs or data stored in the EPROM device will be erased. Thus, after the erase operation, the EPROM device should be reprogrammed which is time-consuming.

Electrically Erasable and Programmable Read Only Memory (EEPROM) devices can achieve erase operations without above recited deficiencies of the EPROM devices. When erasing data from or re-writing data into an EEPROM device, the erase operation or the re-write operation can be implemented in a manner of one storage unit by another. Therefore, data can be stored into, read out from or eased from the memory devices for more than one time.

Referring toFIG. 1, an existing EEPROM device is illustrated. The EEPROM device includes: a semiconductor substrate200; an erase gate201disposed on a first portion of the semiconductor substrate200; two float gate dielectric layers202disposed on a second and a third portion of the semiconductor substrate200respectively, wherein the first portion is between the second portion and the third portion; two float gates203respectively disposed on the float gate dielectric layers202; two control gate dielectric layers204respectively disposed on the float gates203; two control gates205respectively disposed on the control gate dielectric layers204; a tunneling oxide layer206disposed between the word line201and a first sidewall formed by the float gates203and the control gates205, a spacer210disposed on a second sidewall formed by the float gates203and the control gates205; a selecting dielectric layer207disposed beside the spacer210; a selecting gate disposed on the selecting dielectric layer207; a first doping region209disposed beside the selecting gate208; and a second doping region211disposed under the erase gate201.

Accordingly, in existing EEPROM devices, dimensions (specifically, the widths) of the erase gate and the float gate are substantially the same, thus an area of the contact surface therebetween is fixed. Therefore, a coupling ratio of the float gate to the control gate is limited. As a result, efficiency and stability of the EEPROM device during the erase operation may be reduced, that is, erasing performance of the EEPROM device is not satisfactory.

Furthermore, when implementing an erasing operation to the EEPROM device, all float gates disposed along the same line with the erasing gate will be erased. In other words, each float gate can not be erased separately.

Therefore, erasing performance of the existing EEPROM devices needs to be improved. Furthermore, an EEPROM device whose float gates can be separately erased is demanded.

SUMMARY

According to one embodiment of the present disclosure, a method for forming an EEPROM device is provided, including:providing a semiconductor substrate formed with a plurality of active regions therein, wherein each active region extends along a first direction, and the plurality of active regions are arranged one after another along a second direction vertical with the first direction;forming float gate polycrystalline silicon layers extending along the first direction and respectively disposed on the active regions, where each float polycrystalline silicon layer has a width larger than that of the active region disposed thereunder;forming control gate dielectric material layers respectively overlaying the float gate polycrystalline silicon layers;forming a control gate polycrystalline silicon layer overlaying exposed part of the semiconductor substrate and the control gate dielectric material layers;forming a hard mask layer disposed on the control gate polycrystalline silicon layer and having a plurality of first openings formed therein, wherein each of the first openings extends along the second direction and exposes a part of a top surface of the control gate polycrystalline silicon layer, wherein the first openings are arranged one after another along the first direction;forming first spacers respectively on sidewalls of each of the first openings;etching the control gate polycrystalline silicon layer, the control gate dielectric material layers, and the float gate polycrystalline silicon layers by taking the first spacers of the first openings and the hard mask layer as masks, so as to form second openings;forming an isolation oxide layer overlaying inner surfaces of each second opening;forming a word line in each second opening and on the isolation oxide layer;removing the hard mask layer; andetching, by taking the first spacers and the word lines as masks, the control gate polycrystalline silicon layer, the control gate dielectric material layers, and the float gate polycrystalline silicon layers, so as to form a memory unit corresponding to each word line, wherein the remained float gate polycrystalline silicon layers disposed on two sides of the word line constitute two float gates of the memory unit, the remained control gate dielectric material layers disposed on two sides of the word line and respectively on the two float gates constitute two control gate dielectric layers of the memory unit, and the remained control gate polycrystalline silicon layers disposed on two sides of the word line and respectively on the two control gate dielectric layers constitute two control gates of the memory unit.

In some embodiments, the plurality of active regions are formed by:etching the semiconductor substrate to form a plurality of grooves therein, wherein each groove extends along the first direction, and the plurality of grooves are arranged one after another along the second direction vertical with the first direction; andfilling up the plurality of grooves with isolation material to form shallow trench isolation structures, such that portions of the semiconductor substrate between the shallow trench isolation structures constitute the active regions.

In some embodiments, forming the float gate polycrystalline silicon layers includes:forming a plurality of float gate dielectric layers respectively on the active regions, wherein each float gate dielectric layer extends along the first direction, and the plurality of float gate dielectric layers are arranged one after another along the second direction;forming a first polycrystalline silicon layer overlaying the float gate dielectric layers and the shallow trench isolation structures; andetching the first polycrystalline silicon layer, so as to from the float gate polycrystalline silicon layers each of which covers the corresponding float gate dielectric layer and portion of the shallow trench isolation structures.

In some embodiments, a distance between edges of the float gate polycrystalline silicon layer and the active region on the same side ranges from 0.05 micrometer to 0.25 micrometer.

In some embodiments, the method further includes: forming a second spacer covering lateral surfaces of each float gate and each control gate, wherein the lateral surfaces are not covered by the isolation oxide layer

In some embodiments, the method further includes: forming two bit line doping regions in the active regions on two sides of each memory unit.

In some embodiments, the bit line doping region has a width smaller than that of the float gate.

In some embodiments, the two bit line doping regions of the active region are respectively connected with two bit lines.

According to one embodiment of the present disclosure, an EEPROM device is provided, including:a semiconductor substrate formed with a plurality of active regions therein, wherein each active region extends along a first direction, and the plurality of active regions are arranged one after another along a second direction vertical with the first direction;a word line disposed on one of the active regions and extends along the second direction;float gate dielectric layers respectively disposed on two sides of the word line;float gates respectively disposed on the float gate dielectric layers, wherein each float gate has a width larger than that of the active region disposed thereunder;control gate dielectric layers respectively disposed on the float gates;control gates respectively disposed on the control gate dielectric layers;an isolation oxide layer disposed between the word line and lateral surfaces of the float gates and the control gates; andbit line doping regions disposed in the active region beside the float gates and the control gates, and away from the word line.

In some embodiments, a distance between edges of the float gate polycrystalline silicon layer and the active region on the same side ranges from 0.05 micrometer to 0.25 micrometer.

In some embodiments, the device further includes a shallow trench isolation structure disposed in the semiconductor substrate and between two neighboring active regions.

In some embodiments, the bit line doping regions of the active region are respectively connected with different bit lines.

According to one embodiment of the present disclosure, a method for implementing an erase operation to the EEPROM device is provided, including:applying a first zero voltage to the word line;applying a negative voltage to a first control gate disposed on a first side of the word line;applying a second zero voltage to a second control gate disposed on a second side of the word line;applying a positive voltage to a first bit line doping region disposed beside the first control gate; andapplying a third zero voltage to a second bit line doping region disposed beside the second control gate, thus the erase operation can be implemented to the float gate disposed underneath the first control gate.

In some embodiments, the negative voltage applied to the first control gate ranges from −6V to −8V.

In some embodiments, the positive voltage applied to the first bit line doping region ranges from 3V to 5V.

According to one embodiment of the present disclosure, a method for implementing an program operation to the EEPROM device recited above is provided, including:applying a first positive voltage, to the word line;applying a second positive voltage to a first control gate disposed on a first side of the word line, wherein the second positive voltage is larger than the first positive voltage;applying a third positive voltage to a second control gate disposed on a second side of the word line, wherein the third positive voltage is larger than the first positive voltage and smaller than the second positive voltage;applying a forth voltage to a first bit line doping region disposed on a third side of the first control gate, wherein the forth positive voltage is larger than the first positive voltage and smaller than the second positive voltage; andapplying a zero voltage to a second bit line doping region disposed on a forth side of the second control gate, thus the program operation can be implemented to the float gate disposed underneath the first control gate.

According to one embodiment of the present disclosure, a method for implementing an read operation to the EEPROM device recited above is provided, including:applying a first positive voltage to the word line;applying a first zero voltage to a first control gate disposed on a first side of the word line;applying a second positive voltage to a second control gate disposed on a second side of the word line, wherein the second positive voltage is smaller than the first positive voltage;applying a third voltage to a first bit line doping region disposed on a third side of the first control gate, wherein the third positive voltage is smaller than the second positive voltage; andapplying a second zero voltage to a second bit line doping region disposed on a forth side of the second control gate through a metal line, thus the read operation can be implemented to the float gate disposed underneath the first control gate.

Accordingly, the float gate polycrystalline silicon layer has a width larger than that of the active region disposed thereunder, thus the float gate formed thereafter will have a width larger than that of the active region as well. Therefore, the float gate formed may have a larger volume (or a surface area) without changing an integration level of the EEPROM device. Furthermore, a contact surface between the float gate and a control gate can be enlarged, thus a coupling ratio of the float gate to the control gate (a ratio of a first capacitance formed between the float gate and the control gate to a second capacitance formed between the float gate and the outside) can be enlarged. Thus, operation voltages required on control gate when implementing an erase operation or a program operation to the EEPROM device can be reduced. Therefore, stability and efficiency of the EEPROM device during the erase operation and the program operation can be improved. At the same time, power consumed can be reduced as well.

Furthermore, the bit line doping region formed has a width equal to that of the active region, and the float gate has a width larger than that of the active region. Accordingly, the bit line doping region has an area smaller than that of the float gate. Thus, a coupling ratio of the bit line doping region to the float gate can be reduced. Therefore, when an erase operation is implemented to the float gate, a voltage difference between the bit line doping region and the float gate can be enlarged, thus FN tunneling tend to be occurred so as to erase electrons in the float gate easily.

In addition, as bit line doping regions are connected to different bit lines, an erase operation can be just implemented to one single float gate.

DETAILED DESCRIPTION

In order to clarify the objects, characteristics and advantages of the present disclosure, embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings. The disclosure will be described with reference to certain embodiments. Accordingly, the present disclosure is not limited to the embodiments disclosed. It will be understood by those skilled in the art that various changes may be made without departing from the spirit or scope of the disclosure.

Referring toFIGS. 2-17, a process for forming an EEPROM device is illustrated. The process include following steps from S101to S115.

S101, referring toFIG. 2, providing a semiconductor substrate300formed with a plurality of active regions302therein, wherein each active region302extends along a first direction, and the plurality of active regions302are arranged one after another along a second direction vertical with the first direction.

In some embodiments, the semiconductor substrate300may be made of silicon (Si), germanium (Ge), silicon germanium (SiGe), or silicon carbide (SiC). In some embodiments, the semiconductor substrate300may be made of silicon on insulator (SOI) or germanium on insulator (GOI). In some embodiments, the semiconductor substrate300may be made of other materials, such as III-V group compounds, for example, the semiconductor substrate300may be made of gallium arsenide. In some embodiments, a doping process may be implemented to the semiconductor substrate300, so as to change electrical parameters of the semiconductor substrate300.

The semiconductor substrate300further includes one or more shallow trench isolation structures301which are arranged along the first direction as well. Wherein the shallow trench isolation structures301and the active regions302are arranged in a staggered pattern. The shallow trench isolation structures301are used for electrical isolating two neighboring active regions302.

Each active region302may have a width ranging from 0.1 micrometer to 0.3 micrometer. The active regions302are used for forming the EEPROM device thereon in following steps.

The active regions302and the shallow trench isolation structures301may be formed by: forming a hard mask layer (not shown inFIG. 2) on the semiconductor substrate300; forming a plurality of openings on the hard mask layer to expose a plurality portions of the semiconductor substrate300respectively, wherein positions of the openings are corresponded to positions of grooves formed in following steps; etching the semiconductor substrate300by taking the openings as masks, so as to forming a plurality of grooves which are extended along the first direction and parallel to each other; and filling up the grooves with isolation material, so as to form the shallow trench isolation structures301. Accordingly, the active regions302are defined between two shallow trench isolation structures301.

The isolation material may be silicon oxide, silicon nitride, or the like. The isolation material may be configured to have a single layer structure or a double-layer stacked structure.

Filling up the grooves with the isolation material may be implemented by a Chemical Vapor Deposition (CVD) process. After filling up the grooves with the isolation material, a chemical mechanical planarization process may be implemented to remove the isolation material on a surface of the semiconductor substrate300, and to remove the hard mask layer. Accordingly, the shallow trench isolation structures301are formed in the grooves.

S103, referring toFIG. 3, forming a float gate dielectric layer304extending along the first direction and respectively disposed on the active regions302; and forming a first polycrystalline silicon layer303overlaying the float gate dielectric layers304and the shallow trench isolation structures301.

The float gate dielectric layers304may be made of silicon oxide. In some embodiments, the float gate dielectric layers304may be formed by a thermal oxidation process or a wet oxidation process. In some embodiments, the float gate dielectric layers304may be formed by a deposition process.

The first polycrystalline silicon layer303formed is used for forming a float gate polycrystalline silicon layer in following steps. The first polycrystalline silicon layer303may have a thickness ranging from 300 angstrom to 600 angstrom.

S105, referring toFIG. 4, etching the first polycrystalline silicon layer303(referring toFIG. 3), so as to form a float gate polycrystalline silicon layer305on each of the float gate dielectric layers304. The float gate polycrystalline silicon layer305may also disposed on a portion of the shallow trench isolation structures301, thus the float gate polycrystalline silicon layer305has a width larger than that of the active region302.

The float gate polycrystalline silicon layers305are used for forming float gates of the EEPROM device in following steps.

Accordingly, a plurality of float gate polycrystalline silicon layers305are formed along the first direction, and two neighboring float gate polycrystalline silicon layers305are isolated from each other.

Referring toFIG. 5, a top view ofFIG. 4is illustrated.FIG. 4is a sectional view ofFIG. 5along cutting line AB. The float gate polycrystalline silicon layers305are disposed along the first direction (y direction as shown inFIG. 5). The float gate polycrystalline silicon layer305has a width larger than that of the corresponding active region302disposed thereunder. In other words, the float gate polycrystalline silicon layer305not only overlays the corresponding active region302(or the float gate dielectric layer304), but also overlays portion of the shallow trench isolation structures301. It should be noted that, the width of the float gate polycrystalline silicon layer305and the width of the active region302refer to corresponding dimensions along x direction.

Since the float gate polycrystalline silicon layer305has a width larger than that of the corresponding active region302, float gate formed in following steps will have a width larger than that of the corresponding active region302as well. Accordingly, float gate formed can have a larger volume (or a surface area) without changing an integration level of the EEPROM device. Therefore, a contact surface between the float gate and a control gate formed later can be enlarged, thus a coupling ratio of the float gate to the control gate (a ratio of a first capacitance formed between the float gate and the control gate to a second capacitance formed between the float gate and the outside) can be enlarged as well. Accordingly, operation voltages required on the control gate when implementing an erase operation or a program operation to the EEPROM device can be reduced. Therefore, stability and efficiency of the EEPROM device during the erase operation and the program operation can be improved.

An edge of the float gate polycrystalline silicon layer305and an edge of the active region302define a distance W ranging from 0.05 micrometer to 0.2 micrometer.

Referring toFIG. 6, a sectional view ofFIG. 5along cutting line CD is illustrated. As shown, the float gate dielectric layers304are formed on the active regions302, and the float gate polycrystalline silicon layers305are formed on the float gate dielectric layers304.

S107, referring toFIG. 7, forming a control gate dielectric material layer306overlaying each of the float gate polycrystalline silicon layers305, wherein the control gate dielectric material layer306is formed on sidewalls and top surface of the corresponding float gate polycrystalline silicon layer305; and forming a control gate polycrystalline silicon layer307overlaying the exposed semiconductor substrate300and the control gate dielectric material layer306.

The control gate dielectric material layer306may be configured to have a multi-layer stacked structure. For example, the control gate dielectric material layer306may be a three-layer stacked structure consisting of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer.

In some embodiments, the control gate dielectric material layer306may overlay the sidewalls and the top surface of the corresponding float gate polycrystalline silicon layer305. In some embodiments, the control gate dielectric material layer306may also overlay the exposed semiconductor substrate and the shallow trench isolation structures.

The control gate polycrystalline silicon layer307is used for forming a control gate of the EEPROM device in following steps.

Referring toFIG. 8, forming the control gate dielectric material layer306on the float gate polycrystalline silicon layer305showed inFIG. 6, and forming the control gate polycrystalline silicon layer307on the control gate dielectric material layer306are illustrated.

In some embodiments, the control gate polycrystalline silicon layer307may have a thickness ranging from 500 angstrom to 700 angstrom.

Referring toFIG. 9andFIG. 10, a hard mask layer308is formed on the control gate polycrystalline silicon layer307, wherein the hard mask layer308has a plurality of first openings309each of which extends along a second direction and exposes a part of a top surface of the control gate polycrystalline silicon layer307, wherein the first openings309are arranged one after another along the first direction vertical with the second direction; a first spacer310is formed on inner surface of each first opening. It should be noted that,FIG. 9is a sectional view ofFIG. 10along cutting line CD.

It should be noted that,FIG. 9is a sectional view ofFIG. 10along cutting line CD. In some embodiments, the second direction is x direction as shown inFIG. 10. The first spacer310is not showed inFIG. 10.

The hard mask layer308may be made of silicon nitride. The first spacer310may be made of material different from the hard mask layer308. For example, the first spacer310may be made of silicon oxide.

The first spacers310may be made by: forming a spacer material layer on bottom surfaces of the openings309and a top surface of the hard mask layer308; implementing an etching process to the spacer material layer to form the first spacers310on sidewalls of the openings309, wherein the etching process is implemented by a mask-less etching process.

S109, referring toFIG. 11, etching the control gate polycrystalline silicon layer307, the control gate dielectric material layer306, and the float gate polycrystalline silicon layer305by taking the first spacers310of the first openings309and the hard mask layer308as masks, so as to form a plurality of second openings318.

A dry etching process may be employed to etch the control gate polycrystalline silicon layer307, the control gate dielectric material layer306, and the float gate polycrystalline silicon layer305. Etching gas of the dry etching may include at least one selected from a group consisting of HBr, Cl2, and SF6. Thereafter, a wet etching process may be implemented to the float gate304left on the active region302.

It should be noted that, the second openings318include corresponding first openings309. Specifically, when the second openings318are formed, the first openings309are extended into the second openings318.

S111, referring toFIG. 12, forming an isolation oxide layer311overlaying inner surface of each second opening318.

In some embodiments, the isolation oxide layer311may be formed by a CVD process, such as an Atomic layer deposition (ALD) process. In some embodiments, the isolation oxide layer311may be formed by an oxidation process.

In some embodiments, the isolation oxide layer311may also overlay the first spacers310and the top surface of the hard mask layer308.

S113, referring toFIG. 13, forming word lines312in the second openings318and on the isolation oxide layer311.

The word lines312may be made of polycrystalline silicon.

The word lines312may be formed by: forming a third polycrystalline silicon layer to fill up the second openings318, wherein the third polycrystalline silicon layer overlays the isolation oxide layer311and the hard mask layer308; implementing a Chemical Mechanical Planarization (CPM) process to remove the third polycrystalline silicon layer and the isolation oxide layer311formed on the hard mask layer308until surface of the hard mask layer308is exposed. Accordingly, the word lines312are formed in the second openings318.

Thereafter, a protective layer (not shown inFIG. 13) may be formed on surface of each word line312. The protective layer may be made of silicon oxide. The protective layers can be used for preventing word lines312from being etched when implementing an etching process to the control gate polycrystalline silicon layer307and the float gate polycrystalline silicon layer305in following steps. Therefore, performance of the EEPROM formed can be improved.

The protective layer may be formed by a thermal oxidation process. Thus, silicon oxide layers (the protective layer) can be formed on the word lines312in a self-aligned and selective manner. Therefore, steps for forming the protective layer can be simplified, and accuracy of the process can be improved.

S115, referring toFIG. 14, removing the hard mask layer308(referring toFIG. 13); etching, by taking the first spacers310as masks, the remained control gate polycrystalline silicon layer307, the control gate dielectric material layer306, the float gate polycrystalline silicon layer305, and the float gate dielectric layers304, so as to form a float gate313on each active region302respectively disposed on two sides of the word line312, a control gate dielectric layer314on the float gate313, and the control gate on the control gate dielectric layer314.

In some embodiments, a wet etching process may be employed to remove the hard mask layer308. For example, the hard mask layer308may be removed by phosphoric acid solution.

A dry etching process may be employed to etch the remained control gate polycrystalline silicon layer307, the control gate dielectric material layer306, the float gate polycrystalline silicon layer305, and the float gate dielectric layers304. An etching gas of the dry etching process may include at least one selected from a group consisting of HBr, Cl2, and SF6.

Referring toFIG. 15toFIG. 17,FIG. 15is a sectional view ofFIG. 16along a cutting line CD, andFIG. 17is a sectional view ofFIG. 16along a cutting line AB. S117, forming a second spacer316covering lateral surfaces of each float gate313and each control gate315, wherein the lateral surfaces are not covered by the isolation oxide layer, wherein the lateral surfaces are far way from the word lines312; and forming two bit line doping regions317in the active region on two sides of each word lines312.

The second spacer316may be configured to have a single-layer structure or a multi-layer stacked structure. For example, the second spacer316may be configured to be a double stacked structure including a silicon oxide layer and a silicon nitride layer.

The bit line doping region317may be formed by an ion injecting process with certain angle.

In some embodiments, a portion of the bit line doping region317is disposed underneath the float gate313. The bit line doping region317has a width (along x direction) equal to that of the active region302, and the float gate313has a width larger than that of the active region302. Accordingly, the bit line doping region317has an area smaller than that of the float gate313. Thus, a coupling ratio of the bit line doping region317to the float gate313is reduced. Therefore, when an erase operation is implemented to the float gate313, a voltage difference between the bit line doping region317and the float gate313can be enlarged, FN tunneling tends to be occurred so as to erase electrons in the float gate313easily.

Referring toFIG. 15, a memory unit of the EEPROM device is illustrated. The memory unit includes: a word line312disposed on one of the active regions302(or the semiconductor substrate) along the second direction; two float gates313respectively disposed on two sides of the word line312and on the active region302; control gate dielectric layers314respectively disposed on the float gates313; control gates315respectively disposed on the control gate dielectric layers314; an isolation oxide layer311disposed between the word line312and lateral surfaces of the float gate313and the control gate315; float gate dielectric layers304respectively disposed between the float gates313and the active region302; and two bit line doping regions317respectively disposed beside the float gates313and the control gates315.

Referring toFIG. 16, an EEPROM device including a plurality of memory units11is illustrated, wherein the memory units11are arranged in an array.

Two bit line doping regions of each storage unit are electrically connected with different bit lines, so as to implement an erase operation to one single float gate313in each memory unit. Each of the bit lines includes: metal lines (317ato317f), and plugs (not labeled but indicated by blocks with crossed diagonals therein as shown inFIG. 16) for connecting the metal lines to the bit line doping regions respectively. For example, as shown inFIG. 16, one bit line doping region of the memory unit disposed on the first line and the first row is connected to the metal line317athrough a first plug, another bit line doping region of the storage unit is connected to the metal line317bthrough a second plug. Therefore, when implementing the erase operation to one float gate313of the memory unit11, a voltage can be applied to corresponding bit line doping region through metal line317aor metal line317b, so as to implement the erase operation to the corresponding float gate313.

Referring toFIG. 16andFIG. 17, in the EEPROM device, the control gates315of different memory units disposed along a same line (along x direction or the second direction) are connected together. For example, the control gate315awhich belongs to different memory units is an integral structure. The same is true with control gates315bto315d. In addition, the word lines312of different memory units disposed on the same line (along x direction or the second direction) are also connected together. For example, the word line312awhich belongs to different memory units is a integral structure. The same is true with word line312b.

Referring still toFIG. 15toFIG. 17, an EEPROM device according to above recited method is illustrated. The EEPROM device includes follow parts.

A semiconductor substrate300formed with a plurality of active regions302therein, wherein each active region302extends along a first direction (y direction), and the plurality of active regions302are arranged one after another along a second direction (x direction) vertical with the first direction.

A word line312disposed on the active region302, wherein the word line312extends along the second direction.

Two float gate dielectric layers304respectively disposed on two sides of the word line312and disposed on the active region; float gates313disposed on the float gate dielectric layers304respectively; control gate dielectric layers314disposed on the float gates313respectively; and control gates315disposed on the control gate dielectric layers314respectively, wherein the float gate313has a width larger than that of the active region302disposed thereunder.

An isolation oxide layer311disposed between the word line312and lateral surfaces of the float gates313and the control gates315.

Bit line doping regions317respectively disposed on the active regions which are disposed beside the float gates313and the control gates315and away from the word line312.

In some embodiments, an edge of the float gate313and an edge of the second active region302define a distance W ranging from 0.05 micrometer to 0.25 micrometer. Accordingly, a coupling ratio of the float gate to the control gate can be enlarged, a coupling ratio of the bit line doping region to the float gate can be reduce as well, without changing an integration level of the EEPROM device. Therefore, stability and efficiency of the EEPROM device during the erase operation and the program operation can be improved.

In some embodiments, the semiconductor substrate300further has shallow trench isolation (STI) structures301disposed between neighboring active regions302.

In some embodiments, the bit line doping region317may have a width smaller than that of the float gate302.

A method for implementing an erase operation to the EEPROM device is provided.

The method includes: applying a first zero voltage to the word line; applying a negative voltage to a first control gate disposed on a first side of the word line; applying a second zero voltage to a second control gate disposed on a second side of the word line; applying a positive voltage to a first bit line doping region disposed beside the first control gate; applying a third zero voltage to a second bit line doping region disposed beside the second control gate. Accordingly, the erase operation can be implemented to the float gate disposed underneath the first control gate.

It should be noted that, the zero voltages are defined as the first zero voltage, the second voltage and the third voltage, which is used for distinguishing the zero voltages applied to different structures from each other and can not be taken as limitations. The same is true for the first and second control gates, and the first and second bit line doping regions.

In some embodiments, the negative voltage applied to the first control gate ranges from −6V to −8V, the positive voltage applied to the first bit line doping region ranges from 3V to 5V.

Referring toFIG. 18, an example for implementing the erase operation to a target float gate31is illustrated, wherein the target float gate31refers the float gate that the erase operation implemented to. Specifically, a first zero voltage is applied to the word line312a; a first negative voltage, such as −7 V, is applied to a first control gate315bdisposed on a first side of the word line312a; a second zero voltage is applied to a second control gate315adisposed on a second side of the word line312a; a first positive voltage, such as 4V, is applied to a first bit line doping region disposed beside the first control gate315bthrough metal line317d; a third zero voltage is applied to a second bit line doping region disposed beside the second control gate315athrough metal line317c. Accordingly, the erase operation can be implemented to the target float gate31disposed underneath the first control gate315b.

When implementing the erase operation to the target float gate31, other word lines (such as word line312b), other control gates (such as control gate315cand control gate315d), and other bit lines or metal lines (such as metal lines317a,317b,317e, and317f) are all applied to a zero voltage or suspended.

Accordingly, though the method recited above, the erase operation can be implemented to a single float gate of the EEPROM device.

Furthermore, a method for implementing a program operation to the EEPROM device is illustrated. Referring toFIG. 19, taking the target float gate31where the program operation is implemented to for an example. The method includes: applying a first positive voltage, such as 1.5 V, to the word line312a; applying a second positive voltage to a first control gate315bdisposed on a first side of the word line312a, wherein the second positive voltage is larger than the first positive voltage, such as 7V; applying a third positive voltage to a second control gate315adisposed on a second side of the word line312a, wherein the third positive voltage is larger than the first positive voltage and smaller than the second positive voltage, such as 4V; applying a forth voltage to a first bit line doping region disposed on a third side of the first control gate315bthrough a metal line317d, wherein the forth positive voltage is larger than the first positive voltage and smaller than the second positive voltage, such as 4V; applying a zero voltage to a second bit line doping region disposed on a forth side of the second control gate315athrough a metal line317c. Accordingly, the program operation can be implemented to the target float gate31disposed underneath the first control gate315b.

When implementing the program operation to the target float gate31, other word lines (such as word line312b), other control gates (such as control gate315cand control gate315d), and other bit lines or metal lines (such as metal lines317a,317b,317e, and317f) are all applied to a zero voltage or suspended.

Furthermore, a method for implementing a read operation to the EEPROM device is illustrated. Referring toFIG. 20, taking the target float gate31where the read operation is implemented to for an example. The method includes: applying a first positive voltage, such as 2.5 V, to the word line312a; applying a first zero voltage to a first control gate315bdisposed on a first side of the word line312a; applying a second positive voltage to a second control gate315adisposed on a second side of the word line312a, wherein the second positive voltage is smaller than the first positive voltage, such as 2V; applying a third voltage to a first bit line doping region disposed on a third side of the first control gate315bthrough a metal line317d, wherein the third positive voltage is smaller than the second positive voltage, such as 1V; applying a second zero voltage to a second bit line doping region disposed on a forth side of the second control gate315athrough a metal line317c.

Accordingly, the read operation can be implemented to the target float gate31disposed underneath the first control gate315b.

When implementing the read operation to the target float gate31, other word lines (such as word line312b), other control gates (such as control gate315cand control gate315d), and other bit lines or metal lines (such as metal lines317a,317b,317e, and317f) are all applied to a zero voltage or suspended.

Although the present disclosure has been disclosed above with reference to preferred embodiments thereof, it should be understood by those skilled in the art that various changes may be made without departing from the spirit or scope of the disclosure. Accordingly, the present disclosure is not limited to the embodiments disclosed.