Symbol timing recovery with multi-core processor

A method of performing timing error detection includes receiving, by a multi-core processor, a data stream and up-sampling the data stream by a plurality of processing cores of the multi-core processor. The up-sampling is performed in parallel by the plurality of processing cores. The method includes selecting one sample per symbol of the data stream to generate a sampled data output. The method also includes performing symbol timing recovery based on the sampled data output to adjust a resampling point.

BACKGROUND

Exemplary embodiments of the present invention relate to symbol timing recovery and, in particular, to symbol timing recovery with a multi-core processor.

2. Description of the Related Art

In communications systems, a transmitter sends information to a receiver over time in the form of a data stream made up of symbols, such as bits of data. To accurately interpret the data, the receiver and transmitter should operate according to a common clock. However, while the receiver knows the transmission frequency, the receiver clock is typically not truly synchronized with the transmitter clock. When data is transmitted over a wireless communication channel, it is corrupted due to various types of noise, such as fading, oscillator drift, frequency and phase offset, and receiver thermal noise. At the receiver, the system is subject to noise and timing jitter in time domain. As a result, the receiver needs to correctly recover the clock associated with the received signal from the signal itself. The process of recovering the correct clock signal or synchronization information from the received signal of transmitted symbols is called symbol timing recovery (STR).

A timing recovery subsystem must be able to sample the data at a correct instant and detect its peak for correct symbol timing recovery. Sampling just once at the receiver is ineffective due to noise—e.g., additive white Gaussian noise (AWGN). However, a matched filter (MF) can limit the noise at the receiver and provide a high signal-to-noise ratio (SNR) sampling point (due to correlation gain).

The matched filter is a time-reversed and delayed version of the transmitted waveform. To maximize the signal-to-noise ratio for the detection, a demodulator must form inner-products between the incoming signal and a reference signal. That means it must time-align the locally generated reference signal with the received signal. Since the inner-product is formed in a convolving filter, the demodulator must determine the precise time position to sample the input and output of the filter.

Various methods have been tried to implement receivers that not only detect but correct an incoming signal. These methods were first introduced in the analog domain. However, with the availability of digital integrated circuits, the process has been converted over to the digital domain using transformation methods. A typical process for correcting an incoming signal at a receiver employs a phase-locked loop (PLL), which has 3 major components: 1. a timing error detection (TED) circuit; 2. loop filter (LF) for averaging the error; and 3. a controlled oscillator, such as a numerically controlled oscillator (NCO), to advance or retard the timing so that the peak of the incoming signal is matched with the reference signal. There are several widely used methods in timing error detection. The goal of timing-error detection is a TED that yields a high signal-to-noise ratio, and is resource-efficient while maintaining the lowest possible sampling rate (ideally, 1 sample per symbol (spS)).

Maximum-likelihood TED is one example of TED that seeks to meet this goal. Maximum-likelihood TED seeks the peak of correlation output using derivative matched filter (dMF). Other examples of methods used in timing error detection include early-late gate algorithm (ELGA), which essentially finds the derivative by approximation using early, current, and late samples; and Mueller and Muller algorithm, which requires 1 spS but its carrier recovery must be performed before symbol timing recovery. In embodiments of the present invention, matched filter operation is combined with poly-phase filter operation, and in particular with a poly-phase up-sample operation to create a poly-phase matched filter which performs up-sampling and filtering at the same time for timing error detection.

Graphics processing units (GPUs) enable efficient heterogeneous computing. Modern GPU platforms comprise one or more CPU cores and one or more GPUs, which have many powerful arithmetic engines capable of simultaneously running large numbers of lightweight threads. For example, some GPUs presently have 216 processor cores, which collectively allow for more than 165,000 active threads. GPUs process active threads concurrently and to enhance the efficiency of such concurrent execution, no swapping or sharing among concurrent threads occurs. The threads are allocated separately and remain that way until they complete execution.

To efficiently utilize a GPU platform, the programmer must structure the implementation such that GPU threads are kept as busy as possible. This means that opportunities for independent parallel execution must be identified, and spread across the GPU for effective resource utilization.

SUMMARY

Embodiments of the invention include method of performing timing error detection including receiving, by a multi-core processor, a data stream and up-sampling the data stream by a plurality of processing cores of the multi-core processor. The up-sampling is performed in parallel by the plurality of processing cores. The method includes selecting one sample per symbol of the data stream to generate a resampled data output. The method also includes performing symbol timing recovery based on the sampled data output to adjust the resampling point.

Additional aspects of the invention relate to a multi-core processor including a timing error generating circuit and a symbol timing recovery circuit. The timing error generating circuit is configured to receive as an input a data stream, to up-sample the data stream, by a plurality of cores of the multi-core processor, to generate an up-sampled signal, and to down-sample the up-sampled signal to generate a sampled signal. The symbol timing recovery circuit is configured to perform parallel symbol timing recovery of a plurality of sample signals of the data stream by a plurality of processing cores of the multi-core processor based on timing error signals generated based on the respective plurality of sample signals.

DETAILED DESCRIPTION

Symbol timing recovery of a received signal controls a sample rate at which samples are taken of the received signal, and the symbol timing recovery is used to synchronize a transmitter and receiver using the transmitted signal. Embodiments of the invention utilize a multi-core processor, such as a graphics processing unit (GPU), to accelerate symbol timing recovery by performing timing error detection and symbol timing recovery calculations in parallel by processing cores or threads of the multi-core processor.

FIG. 1illustrates a block diagram of symbol timing recovery system100according to an embodiment of the invention. In one embodiment, the block diagram ofFIG. 1illustrates a configuration of circuitry in a multi-core processor, such as a graphics processing unit including multiple processing cores. In addition, the block diagram ofFIG. 1may represent the programming of the multi-core processor by software to control the multi-core processor to receive data, process the data, and output the data. In one embodiment, the symbol timing recovery system100is a receiver that receives a signal, such as a waveform.

InFIG. 1, the symbol timing recovery system100receives a signal or data stream x[n] having a sampling rate of at least 2 samples per symbol (spS). In other words, each symbol, or bit, of data-to-be-transmitted is sampled twice and then transmitted to the symbol timing recovery system100, such that each symbol is represented by two bits of transmitted data in the data stream x[n]. In embodiments of the invention, the signal x[n] may be received by wire or wirelessly through the air via an antenna. While a sampling rate of 2 spS is provided inFIG. 1for the data stream x[n], embodiments of the invention are not limited to this sampling rate.

The received signal x[n] is input to a poly-phase matched filter101and a poly-phase derivative matched filter102. The poly-phase matched filter101and the poly-phase derivative matched filter102up-sample the received signal x[n]. The samplers103and104select a sample point for each symbol of the up-sampled outputs of the matched filters101and103, respectively, and discard the remaining samples. A desired sampling point is determined by analyzing a slope of the outputs of the matched filters101and102. For example, if a slope of the matched filters is positive, then it may be determined that the timing estimate for the sampling is too early. In contrast, if the slope of the outputs of the matched filters is negative, then it may be determined that the timing estimate for the sampling is too late. The timing estimate is continuously adjusted such that the slope reaches zero where the optimal sampling instance is found. The timing phase is adjusted by a timing recovery circuit106to select the correct sample points in this feedback based system. Similarly, a feed-forward system can be used, which would replace the feedback circuit106with a direct estimation circuit where timing error is averaged and resampling instance is calculated without requiring circuit106.

Once the correct sample point has been selected at the output of the matched filters101and102, respectively, the remaining interpolated samples generated by the matched filters101and102are discarded. For example, in the data stream or input signal x[n] ofFIG. 1at 2 spS, if the data stream is up-sampled the matched filters101and102at 1:32 interpolation, then there are 64 samples to choose from for each symbol at the outputs of the matched filters101and102. The samplers103and104sample once at the peak and discard the remaining 63 samples. The sampled value y[n], or output symbol, is provided as an output r[n] to subsequent processing circuitry. For example, the sampled value y[n] may be provided to error correction circuitry or other receiver circuitry downstream from the symbol timing recovery system100. The sampled value y[n] is also combined with the derivative sample y′[n] by the summing circuit105to generate a timing error signal.

An example implementation of a poly-phase interpolation is provided below. However, it is understood that embodiments of the invention are not limited to the particular example provided. By using a poly-phase interpolator to interpolate at a very high rate to achieve arbitrary re-sampler-like performance, and by carefully mapping the filter operations into efficient parallel realizations on the GPU, the TED is mapped onto a targeted multi-core processor architecture. The filter equation has two parts, one for multiply-and-accumulate (MAC) operations to perform the inner-product between two vectors—the input array and filter coefficients, and the other for indexing through the filterbanks.

A typical poly-phase interpolator implementation can be described as shown in Algorithm 1.

Here, h is the filter array, r is an array of input samples, P is the interpolation rate, and M is the length of a sub-filter. Thus, the original filter length is N=P×M.

According to another embodiment, sample interpolation is performed by a multi-core processor including the matched filters101and102using a poly-phase filter matrix. An example of an implementation of a poly-phase filter matrix P×M is provided below. Due to its 2-dimensional structure, double for-loops are used to accomplish this filtering task, which serially indexes through the filter taps and input samples. Multiple forms of parallelism are utilized by the multi-core processor to implement the sampling interpolation using the poly-phase filter matrix. Specifically, the multi-core processor performs parallelization across the filterbanks (outer loop, jj index), across the filter (inner loop, ii index), and at a higher level, across the filter and the filterbanks.

To parallelize across the filterbanks, the multi-core processor may utilize the independence of accumulation across the filterbanks. An example of a computation structure for interpolation using the poly-phase filter matrix P×M is described in Algorithm 2.

As shown in Algorithm 2, jj of Algorithm 1 is replaced with iy, which is the poly-phase filterbank index, and one filterbank is placed in each block in the multi-core processor. Thus, each bank produces one interpolated value or an interpolant. In addition, parallelization may be performed across the filter (ii index) itself. In such an embodiment, one multiply operation is assigned to one thread in a block. Accordingly, the term ii in Algorithm 1 is replaced with ix, which is the thread index of the block. A resulting computational structure is described below in Algorithm 3.

In this embodiment, the filter is accessed via thread index ix and bank index, iy, and the threads may be synchronized.

The symbol timing recovery system100includes the timing recovery circuit106that receives the timing error signal from the multiplication circuit105and adjusts the poly-phase filter bank indexing of the matched filters101and102at the same time that the output sample value y[n] is being generated.

The timing recovery circuit106includes a loop filter107and a numerically-controlled oscillator (NCO)108. The loop filter107averages the timing error over time. In one embodiment, the loop filter107is also a sequential system that multiplies the detected timing error by loop filter gains to track the timing error over time. As illustrated inFIG. 1, the loop filter107includes gain elements109and110, combination elements111and113, and a delay element112

The NCO108counts at a predetermined rate, and the NCO varies the predetermined rate according to the timing error. The NCO108turns the averaged error from the loop filter107into filter indexing using the filter bank index117. The indexed values are provided to the matched filters101and102to adjust the sampling rates of the matched filters101and102. In one embodiment, the NCO108is a sequential system that counts up at a certain rate and wraps around after it reaches its peak. In one embodiment, the NCO108includes an embedded control circuit scale the output of the loop filter107so that the NCO108speeds up or down depending on the error value relative to the peak. As illustrated inFIG. 1, the NCO108includes a summing circuit114, a delay element115, and a modulo or mod operation circuit116that outputs the remainder of division by the number of spS times the up-sample rate. For example, since the data stream x[n] inFIG. 1has 2 spS, if the data stream x[n] is up-sampled by P, the mod is given as (2*P) to get the remainder which would be translated to poly-phase filterbank index. In one embodiment, the timing error is mapped by the timing recovery circuit106over a plurality of processing cores operating simultaneously and in parallel.

The timing error in a maximum-likelihood (ML)-based timing error detection (TED) method is defined as: terror[n]=y′[n]*y[n], where y[n] is the output of the matched filter101and y′[n] is the output of the derivative filter102. Although the equation is particularly for low signal-to-noise ratio, it may be applied to any signal-to-noise ratio.

The number of interpolation points generated by the matched filters101and102corresponds to the number of filter banks. Therefore, with increasing numbers of filter banks, higher interpolation rates are achieved. In addition, since the loop filter107and the NCO108are run at 1 spS, a reference symbol, or matched filtered data, is aligned to the received data. Re-sampling is maintained and the reference symbol is re-aligned with the received sample. Detection time of the sample point is decreased, and throughput of the system is increased by performing faster locking of the sample.

FIG. 2illustrates a method of parallel processing for symbol timing recovery according to an embodiment of the invention. As illustrated inFIG. 2, an input array201of samples is provided, corresponding to up-sampled signals output from the poly-phase matched filters101and102ofFIG. 1. A multi-core processor executes operations according to blocks (Block 0, Block 1, . . . , Block P−1), each block made up of a predetermined number of threads. In one embodiment, the threads correspond to streams of instructions executed by a processing core, and in some embodiments a single processing core can simultaneously execute multiple threads. The multi-core processor is configured to execute the blocks (Block 0, Block 1, . . . , Block P−1) simultaneously. The multi-core processor further divides the input array201into sub-blocks of M samples, and each sub-block of samples is configured to be executed simultaneously with sub-blocks being executed in the other blocks (Block 0, Block 1, . . . , Block P−1).

In embodiments of the invention, the multi-core processor simultaneously processes multiple sub-blocks of samples to perform symbol timing recovery based on the samples of the particular sub-block being processed. In other words, instead of waiting for a group of samples to process, the multi-core processor performs symbol timing recovery of multiple sub-blocks of samples at the same time to generate a timing error quickly and to adjust the resampling index quickly.

Embodiments of the invention include multi-core or multi-threading processors and methods of performing symbol timing recovery by executing calculations in parallel with the multi-core, or multi-threading processor, such as a graphics processing unit. Embodiments encompass receiving a data stream, up-sampling the data stream, then selecting a sample point for each symbol in the data stream among the interpolated samples. In one embodiment, the up-sampling is performed by one or more poly-phase matched filters, and in one embodiment one or more of the up-sampling and sample selection is performed in parallel by multiple threads executing simultaneously on the multi-core processor.

Embodiments further include symbol timing recovery by using a timing error to adjust a sample rate, and in one embodiment the sample rate is adjusted by indexing the timing error over time to a sample bank index. While embodiments of the invention have been described with reference to a receiver, it is understood that embodiments of the invention also encompass transmitters.

Embodiments of the invention may be implemented in any computing system that transmits or receives data to or from a processing unit capable of separating a data stream and executing symbol timing recovery operations in parallel simultaneously.FIG. 3illustrates a block diagram of a computing device301including a central processing unit302and a graphics processing unit (GPU)303, where the GPU303is configured as a receiver to receive a data stream and perform symbol timing recovery of data in the data stream.

The computing device300includes a processing system301including the CPU302and the GPU303. The CPU302is associated with memory306which may include volatile and non-volatile memory for storing instructions and data to be operated on. The GPU303is associated with memory309, which may also include volatile and non-volatile memory for storing instructions and data to be operated on. The CPU302includes a processing core304and cache memory305. The cache memory305typically functions as a short-term memory for storing data to be accessed quickly by the processing core304. In some embodiments, the CPU302includes multiple processing cores304.

The GPU303includes multiple processing cores307ato307nconfigured to operate in parallel. Each processing core307ato307nmay further be associated with dedicated local memory308ato308nfor that particular processing core. In embodiments of the invention, the processing cores307ato307nmay simultaneously run separate threads, and in some embodiments each processing core307ato307nruns multiple threads simultaneously. In embodiments of the invention, the multiple processing cores307ato307nsimultaneously perform symbol timing recovery calculations. In one embodiment, the simultaneous performance of the symbol timing recovery calculations includes simultaneous generation of timing error signals based on processing samples of a data stream.

The processing system301further includes a bus310for facilitating communications between the CPU302and GPU303, as well as between the CPU302, GPU303, and external devices, such as transmitters, receivers, additional computing devices, or any other devices capable of transmitting or receiving data.

Embodiments of the invention relate to using a multi-core system to perform multiple timing error detection operations simultaneously using sub-block or sub-grouping of threads in a multi-core processor to speed up the timing recovery process. Embodiments of the invention also relate to using a multi-core processor to process multiple input streams to perform simultaneous timing recovery on different input streams. Embodiments of the invention also relate to using a multi-core processor itself or in conjunction with another processor to perform timing recovery. Embodiments relate to using a feedback or feed-forward architecture in a multi-core processor to perform timing recovery, and in particular, to using multiple cores to accelerate the timing error detection used in either configuration.

While embodiments of the invention have been described, it will be understood that those of ordinary skill in the art may make various improvements and enhancements which fall within the scope of the claims which follow.