Method of forming a doped portion of a semiconductor and method of forming a transistor

A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.

FIELD OF THE INVENTION

The present invention relates to a method of forming a doped portion as well as to a method of forming a transistor.

BACKGROUND

Although in the following, mainly memory devices and their manufacturing method are explained as an illustrative example, the invention can be applied to a broad scope of semiconductor devices, including, but not limited to memories, logic and wireless applications. Since tilted implants are mainly used to define the properties of MOS transistors, a preferred field of application of the invention is, e.g., halo implants of transistors. For example, these transistors may be surrounded by a patterned area comprising patterns in which pattern densities are locally varying over the chip. However, the invention is not limited to DRAM. The tilted implants may even have other functions than the definition of halo implants, such as, e.g., the definition of contacts, the definition of single sided buried straps, contact implants and others. Descriptions in the later text citing the formation of a transistor structure are not meant to narrow the applicability of the invention.

Memory devices such as dynamic random access memories (DRAM), non-volatile memories and other well known memory devices generally comprise a memory cell array as well as a peripheral portion in which circuits for driving the memory cell array and for performing reading and writing operations are disposed. Usually, the circuits in the peripheral portion as well as each of the memory cells comprise transistors which are at least partially formed in a semiconductor substrate. Generally, each of these transistors comprises a first and a second source/drain region, a channel which is disposed between the first and second source/drain regions and a gate electrode. The gate electrode controls the conductivity of the channel. A transistor may further comprise a halo doped portion which is disposed between the channel and the first and second source/drain regions. The halo doped portion is doped with a dopant of a conductivity type which is opposite to the conductivity type of the first and second source/drain regions. This halo doped portion suppresses short-channel effects.

Usually, for forming an array transistor or peripheral transistor, first, the gate electrodes are formed by patterning a conductive layer stack. Thereafter, doping steps are performed for defining the first and second source/drain portions. In particular, this doping step usually is performed as an ion implantation step. During this ion implantation step, the gate electrodes as well as a patterned photoresist layer are taken as an implantation mask so that the ions are implanted only in predetermined substrate portions.

To illustrate the effects typically visible when performing a tilted implant on a wafer having protruding portions of varying density over a wafer surface,FIG. 1shows an exemplary cross-sectional view of a semiconductor substrate1. On the surface10of the semiconductor substrate1, gate electrodes2as an example of protruding portions are disposed. In particular, the gate electrodes2have been defined by a conventional method, in which, first, a layer stack comprising at least one conductive layer, is deposited and patterned in accordance with the circuitry to be formed. On top of the resulting surface, thereafter, a photoresist layer34is deposited and patterned so that portions of the substrate surface10are uncovered. Usually, after correspondingly patterning the photoresist layer34, a tilted ion implantation step is performed taking the photoresist mask34as well as the gate electrodes2as a shadowing mask.

Thereby, the halo doped portion42as is shown inFIG. 1is defined. As can be gathered fromFIG. 1, the lateral extent of the doped portion depends on the height h of the photoresist layer34.

SUMMARY

The present invention provides a method of forming a doped portion, comprising providing a semiconductor substrate having a surface, defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height, providing a pattern layer above the substrate surface, removing portions of the pattern layer from predetermined substrate portions, performing an ion implantation step, wherein an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions being doped with the ions, and removing the pattern layer.

Moreover, one method of forming a transistor according to the invention comprises providing a semiconductor substrate having a surface, providing a gate electrode on the substrate surface, providing a pattern layer above the substrate surface, removing portions of the pattern layer from predetermined positions, forming a first and a second source/drain region in the semiconductor substrate, performing an angled ion implantation step wherein an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the gate electrode, predetermined substrate portions being doped with the ions, and removing the pattern layer.

DETAILED DESCRIPTION

FIGS. 2 to 5show a first embodiment of the present invention. As is shown inFIG. 2, first, a plurality of protruding portions is defined on the surface of a substrate1. The semiconductor substrate1can in particular be a silicon substrate which may, e.g., be p-doped. Other doped portions can be provided in the semiconductor substrate1, and, in addition, further components can be defined in the substrate. On the surface10of the substrate surface1, arbitrary kinds of protrusions may be formed. For example, if a transistor is to be formed, preferably, the protruding portions are the gate electrodes2of the transistors to be formed. The gate electrodes2can be defined by, first, depositing a gate insulating layer25on the substrate surface10, followed by a conductive layered stack. Thereafter, the layer stack is patterned, e.g., by using a photolithographic method as is generally known. As a result, as is shown inFIG. 2, protruding portions2,41are formed on the surface10of the semiconductor substrate1. The gate electrodes2can have, e.g., a height of 100 to 500 nm and a minimum distance of 20 to 120 nm from each other.

According to an embodiment of the invention, first, a sacrificial layer, in particular, a spacer layer which is made of an insulating material such as silicon dioxide which is formed by using TEOS (tetraethylorthosilicate) as a starting material is deposited. The silicon dioxide layer31can have, e.g., a thickness of approximately 5 to 30 nm, e.g., 10 nm.

Thereafter, a pattern layer32is deposited. The pattern layer has, for example, a thickness of 5 to 10 nm. The material of the pattern layer can be arbitrarily selected. Nevertheless, the material of the pattern layer32should be able to be etched selectively with respect to the sacrificial layer. Silicon nitride, for example, can be chosen as the material of the sacrificial layer. Further examples comprise tungsten or TiN. As is shown inFIG. 3, e.g., the sacrificial layer31as well as the pattern layer32may preferably be deposited conformally on the surface10of the semiconductor substrate1. As a result, the thickness of the pattern layer is homogenous and independent from the pattern density of the protruding portions.

Thereafter, a photoresist layer33is deposited on the resulting surface and patterned using a standard photolithographic method. Taking the patterned photoresist layer33as an etching mask, in the next step the pattern layer32is patterned in accordance with the pattern of the photoresist mask33. An anisotropic etching step, for example, can be performed so that only the horizontal portions of the pattern layer32are removed; vertical portions of the pattern layer32remaining on the sidewalls of the gate electrodes2. Nevertheless, the etching step for etching the pattern layer can as well be an isotropic etching step.

The resulting structure is shown inFIG. 3. As can be seen, gate electrodes2are formed on the surface10of the semiconductor substrate. A silicon dioxide layer32is conformally deposited on the surface of the semiconductor substrate1including the gate electrodes2. Moreover, Si3N4spacers32aare formed on the sidewalls2aof the gate electrodes. Part of the surface is covered with the photoresist layer33. As can be seen, the thickness of the photoresist layer33is much larger than the thickness of the sacrificial layer31and the thickness of pattern layer32.

In the next step, the remaining portions of the photoresist layer33are removed. Optionally, the exposed portions of the sacrificial layer may be removed completely or partially. For example, the upper portion of the sacrificial layer may be removed so that approximately 1 to 2 nm of the sacrificial layer remains. Thereafter, an ion implantation step is performed so as to provide the first and second source/drain regions. For example, this doping step comprises an ion implantation step wherein the ions impinge perpendicularly onto the substrate surface10. Thereby, the first and second source/drain regions are provided. During this ion implantation step the gate electrodes as well as the portions of the pattern layer32are taken as an implantation mask. The ion implantation step with the ions impinging perpendicularly with respect to the substrate surface is performed using n dopants, e.g., P or As ions. Thereafter, an angled implantation step is performed, using p dopants, e.g., B or BF2ions. An exemplary energy amount of the ions is approximately 10 keV. This angled ion implantation step provides a halo doping of the substrate.

FIG. 4shows a cross-sectional view of the substrate during this ion implantation step. As can be seen, the ions35impinge at an angle α onto the substrate surface. For example, the angle α may be 55 to 75°. According to an embodiment of the invention, the angle α of the ions with respect to the substrate surface may be 55 to 70°, e.g., 62°. As can be seen fromFIG. 4, the ions are stopped by the pattern layer32and by the protruding portions2. Nevertheless, the ions penetrate through the sacrificial layer31. As can be gathered fromFIG. 4, by adjusting the angle α of the ions and by adjusting the thickness of the pattern layer32as well as by defining openings in the pattern layer32, the position and the lateral extension of the halo doped regions42can be adjusted.

Thereafter, the pattern layer32is removed. In particular, if silicon nitride is taken as the material of the pattern layer32, the silicon nitride mask can be removed with hot phosphoric acid.

Accordingly,FIG. 5shows a cross-sectional view of the completed array of transistors23. For example, a transistor23as shown inFIG. 5comprises a first source/drain region21, a second source/drain region22as well as a channel24which is disposed between the first and second source/drain regions. The first and second source/drain regions21,22are adjacent to the substrate surface10. A gate electrode2is disposed above the channel24and insulated from the channel by a gate insulating layer25. The gate electrode2controls the conductivity of the channel24. A halo doped region42is disposed adjacent to the first source/drain region21at a position next to the gate electrode2. The lateral extension of the halo doped region42has been adjusted by the thickness of the sidewall spacer corresponding to the sum of the thicknesses of the sacrificial layer31and the thickness of the pattern layer32. On the other side, the lateral extension of the halo doped region42is adjusted by the thickness of the pattern layer32and the angle of the angled ion implantation step. As can be seen in the right hand portion ofFIG. 5, there is also a halo doped region42which is disposed between the doped portion4and the protruding portion41. Also in this case the lateral extension of the halo doped region42is adjusted by the thicknesses of the sacrificial layer31, the thickness of the pattern layer32, and, on the other side, by the thickness of the pattern layer32and the angle α of the ion implantation step.

Although the method of the present invention has been described in combination with a method of forming a transistor, it is clearly to be understood that the method of forming a doped region of a substrate can be used for forming any kind of doped region, as is also shown in the right hand side ofFIG. 5.

As is clearly to be understood the above method can as well be implemented without the use of the sacrificial layer31. Moreover, according to an embodiment, the thickness of the pattern layer may be less than the minimum height of the protruding portions. Accordingly, the pattern layer can be deposited as a conformal layer. By way of example, the thickness of the sacrificial layer is less than the minimum height of the protruding portions.

FIGS. 6 to 10illustrate a further embodiment of the present invention. The starting point for implementing the second embodiment of the present invention is the structure shown inFIG. 2. In particular, on the surface10of a semiconductor substrate, in particular, a p-doped silicon substrate, a plurality of gate electrodes2as an example of protruding portions are formed. The height of each of the gate electrodes is approximately 100 to 500 nm depending on the minimal structural feature size of the technology employed. In a first step, a planarizing layer is deposited so as to entirely cover the gate electrodes2. A carbon layer51, e.g., is deposited by a chemical vapor deposition method. In particular, such a carbon layer is a layer which is made of elementary carbon, e.g., amorphous carbon, and which may optionally comprise hydrogen. Such a carbon layer may be deposited by physical vapor deposition or chemical vapor deposition.

As an alternative, also the bottom resist of a bi-layer resist system as is commonly used can be employed. In particular, such a bottom layer comprises aromatic carbon compounds, such as polymers, in particular, polymers on a novolak, polyhydroxystyrene, Naphtalene or/and Phenyl methacrylate basis. The thickness of the planarizing layer is such that the layer thickness is constant, independently from the loading density of the gate electrodes. For example, a layer thickness may be approximately 100 to 600 nm. The planarizing layer, e.g., may as well act as an antireflective coating.

The resulting structure is shown inFIG. 6. As can be seen, the entire surface of the substrate is covered with a planarizing layer51. The planarizing layer51, e.g., may be applied by spin coating, so that a homogeneous layer thickness is obtained.

In the next step, a recess etching step or a CMP step can be performed so that the layer thickness of the planarizing layer51is reduced. By way of example, the recess etching step may stop on the surface of the gate electrodes2.FIG. 7shows a cross-sectional view of the resulting structure, wherein the height of the recess etch52is shown. As is shown inFIG. 7, the upper surface of the layer51may be disposed above the upper surface of the gate electrodes2.

In the next step, an imaging layer53is deposited on the surface of the planarizing layer51. The imaging layer may have the thickness, e.g., of approximately 50 to 250 nm. Moreover, the imaging layer may comprise photoactive components so that it can be patterned using normal photolithographic methods. For example, the top resist layer of a bi-layer resist system as is usually employed may be taken. Such a top resist layer usually is made of a material which is not completely etched when etching the bottom layer. If the bottom layer, e.g., of a bi-layer resist system is etched using a reactive ion etching method, the top layer becomes insensitive with respect to this reactive ion etching and the top layer is etched at a much slower etch rate. Preferably, the imaging layer53further includes an additive so as to enhance the stopping power during the ion implantation step which is to follow. By way of example, such a top resist layer may include an additive such as silicon which is reacted to SiO2during the reactive ion etching step using O2as an etching gas. In particular, the imaging layer may comprise an organic compound, e.g., a hydrocarbon compound, including silicon at least in the main chains or side chains. In particular, if the imaging layer53includes silicon, the silicon is reacted during the ion implantation step to SiO2and, thus, has an increased stopping power with respect to the ions which are implanted. Optionally, the imaging layer53may also comprise titanium so as to further increase the stopping power. By way of example, the thickness of the imaging layer53may be reduced during the ion implantation step.

The resulting structure is shown inFIG. 8. As can be seen fromFIG. 8, on the surface10of a semiconductor substrate gate electrodes2are formed. The gate electrodes2are entirely covered with the planarizing layer51. On top of the planarizing layer51, the imaging layer53is disposed. In the next step, the layer stack comprising the planarizing layer51and the imaging layer53is patterned in accordance with the portions of the substrate surface10which are to be exposed. In particular, the imaging layer53is patterned using a photolithographic method that is well known in the art, thereby removing predetermined portions of the imaging or pattern layer. In addition, an etching step is performed so as to remove the planarizing layer51from those portions from which the imaging layer53has been removed during the photolithographic step. After patterning this layer stack, an ion implantation step is performed for defining the first and second source/drain regions. In particular, this ion implantation step is an ion implantation step during which the ions perpendicularly impinge onto substrate surface10. N dopants such as P or As ions, e.g., may be doped during this implantation step.

Thereafter, an angled ion implantation step35is performed. Preferably, an angle of the ions is 55 to 75°, e.g., 55 to 70° and, as a further example, 62° with respect to the substrate surface10. This implantation step, e.g., may be performed with a p-dopant for example BF2or B ions. During this implantation step the planarizing layer51and, optionally, the imaging layer53act as an implantation stopping layer. As a result, only those portions which are not shadowed by the layer stack comprising the planarizing layer and the imaging layer53or by the gate electrodes2are implanted with the angled implantation step. If a bottom resist of a commonly used bi-layer resist system is taken as the planarizing layer, an improved stopping activity of this layer is obtained.

If such a bi-layer resist system is taken as an ion implantation mask, the sidewalls of the opened portions are steeper and better defined than in the usually employed photoresist material. Since the imaging layer53is scarcely eroded by the implantation step, the region in which the ions are implanted is defined more precisely. Since the layer stack comprising the planarizing layer51and the imaging layer53has a high stopping power with respect to the ions, the thickness of the layer stack can be reduced. As a consequence, even with reduced ground rules the method of the present invention can be implemented.

FIG. 9shows a cross-sectional view of the ion implantation step. As can be seen, the ions impinge onto the substrate surface10in the opened regions at an angle α.

Thereafter, the imaging layer as well as the planarizing layer51are removed from the substrate surface. As a result, the cross-sectional view shown inFIG. 10is obtained. As can be seen, a plurality of transistors are formed. Each of the transistors comprise a first and a second source/drain regions21,22, a gate electrode2, and a channel24which is disposed between the first and second source/drain regions. The first and second source/drain regions are adjacent to the substrate surface10. The gate electrode is insulated from the channel by a gate insulating layer25. At the boundary of the first and second source/drain regions21,22and the channel24, the doped portion42is provided. The doped portion42is slightly p-doped so as to suppress short channel effects. Thereafter, the transistor array as is shown inFIG. 10is completed in a conventional manner by providing the corresponding contacts and higher metallization layers.

LIST OF REFERENCE SYMBOLS