SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a wiring substrate and a first semiconductor chip. The first semiconductor chip has a first surface facing the wiring substrate. The first surface has a groove. The groove extends across the first surface and divides the first surface into a first portion and a second portion. A first bonding layer is between the first portion of the first surface and the wiring substrate. A second bonding layer is between the second portion of the first surface and the wiring substrate. A second semiconductor chip is on the wiring substrate. The second semiconductor chip has a portion inside the groove of the first semiconductor chip. A third bonding layer is between the bottom of the groove and a second surface of the second semiconductor chip.

CROSS-REFERENCE TO RELATED APPLICATION (S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-191649, filed Nov. 30, 2022, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

There is a semiconductor device having multiple chips stacked above a controller chip. In some instances, when a controller chip and stacked chips are sealed using an insulating sealing member, the space filling by the insulating sealing member may be insufficient.

DETAILED DESCRIPTION

Embodiments concern a semiconductor device for which insufficient filling properties of a sealing resin can be avoided.

In general, according to one embodiment, a semiconductor device includes a wiring substrate and a first semiconductor chip. The first semiconductor chip has a first surface facing the wiring substrate. The first surface has a groove. The groove extends across the first surface and divides the first surface into a first portion and a second portion. A first bonding layer is between the first portion of the first surface and the wiring substrate. A second bonding layer is between the second portion of the first surface and the wiring substrate. A second semiconductor chip is on the wiring substrate. The second semiconductor chip has a portion inside the groove of the first semiconductor chip. A third bonding layer is between the bottom of the groove and a second surface of the second semiconductor chip.

Hereinafter, certain example embodiments will be described by referring to the drawings. In order to facilitate understanding of the description, identical reference symbols will be applied, as far as possible, to identical or substantially similar components in the drawings, and redundant description may be omitted.

In each drawing, an X-axis, a Y-axis, and a Z-axis may be shown. The X-axis, the Y-axis, and the Z-axis form right-handed, three-dimensional Cartesian coordinates. The +direction along the Z-axis and the −direction along the Z-axis may be called “upward” and “downward” directions, respectively. Also, planes perpendicular to the X-axis, the Y-axis, or the Z-axis may be called a YZ plane, a ZX plane, or an XY plane, respectively.

First Embodiment

FIG.1is a plan view in which a semiconductor device10according to the first embodiment is seen from above.FIG.2is a cross-sectional view along a section line II-II shown inFIG.1.FIG.3is a cross-sectional view along a section line III-III shown inFIG.1.

As shown inFIGS.1to3, the semiconductor device10includes a wiring substrate25, stacked chip bodies40and50, bonding wires61and62, a semiconductor chip63, sealing resins65and67, and a die attach film68. In order to facilitate understanding of the description, the sealing resins65and67are not specifically depicted inFIG.1.

The stacked chip body40includes die attach films41aa,41ab,41b,41c,and41dand semiconductor chips42a,42b,42c,and42d.Hereafter, each of the die attach films41aa,41ab,41b,41c,and41dmay be called a die attach film41. Each of the semiconductor chips42a,42b,42c,and42dmay be called a semiconductor chip42.

The stacked chip body50includes die attach films51a,51b,51c,and51dand semiconductor chips52a,52b,52c,and52d.Hereafter, each of the die attach films51a,51b,51c,and51dmay be called a die attach film51. Each of the semiconductor chips52a,52b,52c,and52dmay be called a semiconductor chip52.

The semiconductor chips42and52are, for example, semiconductor memory chips. Specifically, the semiconductor chips42and52are NAND flash memory chips in this example. At least one of the semiconductor chips42and52may be a DRAM chip, or may be a chip having another function. A form of the semiconductor chips42bto42dand52is a plate form whose upper and lower faces are both faces approximately parallel to the XY plane. A long side and a short side of the face are approximately parallel to the X-axis and the Y-axis respectively.

FIG.4is a plan view in which the semiconductor chip42ais seen from below. As shown inFIGS.1to4, the semiconductor chip42ahas a lower main surface side31aapproximately parallel to the XY plane. The lower main surface side31ais, for example, rectangular. A long side and a short side of the lower main surface side31aare approximately parallel to the X-axis and the Y-axis respectively.

The semiconductor chip42ahas a groove portion31dthat divides the lower main surface side31ainto a face portion31band a face portion31c.The groove portion31dextends approximately parallel to the short side of the lower main surface side31a,that is, approximately parallel to the Y-axis. The groove portion31dhas a bottom face31ethat is approximately parallel to the XY plane. The groove portion31dhas a side face31f(sidewall) and a side face31g(sidewall) approximately parallel to the YZ plane.

The groove portion31ddivides the main face31ain such a way that, for example, the face portions31band31care rectangular. The form and an area of the face portion31bare approximately the same as the form and area of the face portion31c.

An upper face31hof the semiconductor chip42ahas a rectangular form. The long side and the short side of the face31hare approximately parallel to the X-axis and the Y-axis respectively.

A distance between the bottom face31eand the face31h,that is, a thickness of the semiconductor chip42din the groove portion31d,is, for example, 50 μm. Also, a distance between the main face31aand the face31his, for example, 150 to 200 μm.

The wiring substrate25has a face25athat opposes the face portions31band31cof the semiconductor chip42a.The face25ais, for example, rectangular. The long side and the short side of the face25aare approximately parallel to the X-axis and the Y-axis, respectively.

The die attach film41aais provided between the face portion31bof the semiconductor chip42aand the face25aof the wiring substrate25. An upper face and a lower face of the die attach film41aaare bonded to the face portion31band the face25a,respectively, whereby the semiconductor chip42ais fixed to the wiring substrate25.

The die attach film41abis provided between the face portion31cof the semiconductor chip42aand the face25aof the wiring substrate25. An upper face and a lower face of the die attach film41abare bonded to the face portion31cand the face25arespectively, whereby the semiconductor chip42ais fixed to the wiring substrate25. A thickness of the die attach films41aaand41abis, for example, several tens of micrometers.

A hole portion32is formed by the groove portion31dof the semiconductor chip42aand the face25aof the wiring substrate25, and both ends are open.

Specifically, an inner wall of the hole portion32is formed by the bottom face31eand the side faces31fand31gof the groove portion31and one portion of the face25a.

The hole portion32extends approximately parallel to the Y-axis, and has an approximately rectangular cross-section. The hole portion32has aperture portions32aand32balong Y-axis direction.

At least a portion of the semiconductor chip63is provided in the hole portion32. In the present embodiment, all of the semiconductor chip63is provided in the hole portion32. The semiconductor chip63is, for example, a semiconductor memory controller chip. The semiconductor chip63is electrically connected to the semiconductor chips42and52and controls the semiconductor chips42and52.

The semiconductor chip63has an upper face63athat opposes the bottom face31eof the groove portion31d.The face63ais, for example, rectangular. The long side and the short side of the face63aare approximately parallel to the Y-axis and the X-axis, respectively.

FIG.5is an enlarged view of a region where the semiconductor chip63and the wiring substrate25are connected. As shown inFIGS.1to5, the wiring substrate25has multiple substrate electrodes25bprovided on the face25a.

Multiple solder balls64are provided on a lower face of the wiring substrate25. Also, an electrode pattern (not separately depicted) is formed on the wiring substrate25. Some of the substrate electrodes25bcan be electrically connected to the multiple solder balls64via the electrode pattern of the wiring substrate25. Some of the substrate electrodes25bcan be electrically connected to a substrate electrode26or27via the electrode pattern of the wiring substrate25. Some of the substrate electrodes25bmay be in an electrically floating state.

The semiconductor chip63has, on a lower face, multiple chip electrodes63brespectively provided opposing each one of the multiple substrate electrodes25b.

The multiple substrate electrodes25bon the wiring substrate25and the multiple chip electrodes63bon the semiconductor chip63are connected via a bump73. That is, the semiconductor chip63is flip chip-connected to the wiring substrate25. In this manner, the multiple solder balls64and the semiconductor chip63can be electrically connected.

The sealing resin67seals (covers) the semiconductor chip63, the substrate electrode25b,the chip electrode63b,and the bump73. The semiconductor chip63, the substrate electrode25b,the chip electrode63b,and the bump73are insulated and sealed by the sealing resin67.

The die attach film68is provided between at least one portion of the bottom face31eof the groove portion31dand at least one portion of the upper face63aof the semiconductor chip63.

The present embodiment is such that when the semiconductor chip63is seen in plan view in direction perpendicular to the face63a,the die attach film68is provided in a region where the bottom face31eand the face63acoincide. Specifically, when seen in plan view, the region is a range within which the face63aof the semiconductor chip63is positioned. The die attach film68is provided in the region.

An upper face and a lower face of the die attach film68are bonded to the bottom face31eand the face63arespectively, whereby the semiconductor chip42ais fixed to the semiconductor chip63. A thickness of the die attach film68is, for example, several tens of micrometers.

As shown inFIGS.1and3, the wiring substrate25includes the multiple substrate electrodes26. The multiple substrate electrodes26are provided arrayed on a straight line approximately parallel to the X-axis in a vicinity of an edge in the +Y-axis direction of the wiring substrate25.

The semiconductor chips42a,42b,42c,and42dinclude multiple chip electrodes43a,43b,43c,and43drespectively.

The bonding wire61electrically connects the substrate electrode26and the chip electrodes43a,43b,43c,and43d.

The multiple chip electrodes43aare provided on the upper face31hof the semiconductor chip42a,farther to a vicinity of an edge31ion the aperture portion32aside than to an edge31jon the aperture portion32bside. The multiple chip electrodes43aare arrayed on a straight line approximately parallel to the X-axis.

Specifically, the face31hincludes a face31ha,which is a face on a side opposite the bottom face31eof the groove portion31d,a face31hb,which is a face on a side opposite the face portion31b,and a face31hc,which is a face on a side opposite the face portion31c.

A chip electrode43aa,which is one of the multiple chip electrodes43a,is provided in a vicinity of the edge31iof the face31ha.The bonding wire61connected to the chip electrode43aa,that is, a bonding wire61a,electrically connects a substrate electrode26aand the chip electrodes43aa,43b,43c,and43d.

A chip electrode43ab,which is another one of the multiple chip electrodes43a,is provided in a vicinity of the edge31iof the face31hb.The bonding wire61connected to the chip electrode43ab,that is, a bonding wire61b,electrically connects a substrate electrode26band the chip electrodes43ab,43b,43c,and43d.

A chip electrode43ac,which is another one of the multiple chip electrodes43a,is provided in a vicinity of the edge31iof the face31hc.The bonding wire61connected to the chip electrode43ac,that is, a bonding wire61c,electrically connects a substrate electrode26cand the chip electrodes43ac,43b,43c,and43d.

The substrate electrode26that is not connected to the bonding wire61may be provided on the wiring substrate25. Also, the chip electrode43a,43b,43c,or43dthat is not connected to the bonding wire61may be provided on the semiconductor chip42a,42b,42c,or42drespectively.

The wiring substrate25includes the multiple substrate electrodes27. The multiple substrate electrodes27are provided arrayed on a straight line approximately parallel to the X-axis in a vicinity of an edge in the −Y-axis direction of the wiring substrate25.

The semiconductor chips52a,52b,52c,and52dinclude multiple chip electrodes53a,53b,53c,and53drespectively. The bonding wire62electrically connects the substrate electrode27and the chip electrodes53a,53b,53c,and53d.

The substrate electrode27that is not connected to the bonding wire62may be provided on the wiring substrate25. Also, the chip electrode53a,53b,53c,or53dthat is not connected to the bonding wire62may be provided on the semiconductor chip52a,52b,52c,or52drespectively.

As shown inFIGS.1to3, external forms of the semiconductor chips42and52seen from when above are approximately the same. Thicknesses of the semiconductor chips42bto42dand52bto52dare approximately the same. The thicknesses of the semiconductor chips42bto42dand52bto52dare less than a thickness of a portion of the semiconductor chip42ain which the groove portion31dis not formed, and less than a thickness of the semiconductor chip52a.

The semiconductor chip42bis provided on the upper face31hof the semiconductor chip42ain such a way that the chip electrodes43aa,43ab,and43acare exposed.

Specifically, end faces in the +X-axis direction of the semiconductor chips42ato42dand the semiconductor chips52ato52dare aligned. End faces in the −X-axis direction of the semiconductor chips42ato42dand the semiconductor chips52ato52dare aligned.

Both Y-axis direction end faces of the semiconductor chip42bdeviate (offset) in the −Y-axis direction from the Y-axis direction end faces of the semiconductor chip42a.Both Y-axis direction end faces of the semiconductor chip42cdeviate (offset) in the −Y-axis direction from the Y-axis direction end faces of the semiconductor chip42b.Both Y-axis direction end faces of the semiconductor chip42ddeviate (offset) in the −Y-axis direction from the Y-axis direction end faces of the semiconductor chip42c.Both Y-axis direction end faces of the semiconductor chip52adeviate (offset) in the −Y-axis direction from the Y-axis direction end faces of the semiconductor chip42d.

That is, the semiconductor chips42ato42d,when seen from the −X-axis direction going toward the +X-axis direction, are stacked in a stepped (staggered) form that deviates farther in the −Y-axis direction the higher the semiconductor chip42is in the stack. The chip electrodes43bto43dare provided on an exposed portion of the upper face of the semiconductor chips42bto42d,respectively.

Both Y-axis direction end faces of the semiconductor chip52bdeviate (offset) in the +Y-axis direction from the Y-axis direction end faces of the semiconductor chip52a.Both Y-axis direction end faces of the semiconductor chip52cdeviate (offset) in the +Y-axis direction from the Y-axis direction end faces of the semiconductor chip52b.Both Y-axis direction end faces of the semiconductor chip52ddeviate (offset) in the +Y-axis direction from the Y-axis direction end faces of the semiconductor chip52c.

That is, the semiconductor chips52ato52d,when seen from the −X-axis direction going toward the +X-axis direction, are stacked in a stepped (staggered) form that deviates farther in the +Y-axis direction the higher the semiconductor chip52is in the stack. The chip electrodes53ato53dare provided on an exposed portion of the upper face of the semiconductor chips52ato52d,respectively.

The sealing resin65seals at least the semiconductor chip42a.Specifically, the sealing resin65buries the stacked chip bodies40and50and the bonding wires61and62above the wiring substrate25. The stacked chip bodies40and50and the bonding wires61and62are insulated and sealed by the sealing resin65.

Also, the sealing resin65is also disposed in an interior of the hole portion32. Specifically, the sealing resin65enters an internal space in the hole portion32from at least one of the aperture portions32aand32b,whereby the internal space is filled. At this time, the sealing resin65buries the semiconductor chip63, the die attach film68, and the sealing resin67. The semiconductor chip63, the die attach film68, and the sealing resin67are insulated and sealed by the sealing resin65.

The sealing resin65comes into contact with at least one portion of the one side face31fof the groove portion31dand at least one portion of the side face63cof the semiconductor chip63opposing the side face31f,and comes into contact with at least one portion of the other side face31gof the groove portion31dand at least one portion of the side face63dof the semiconductor chip63opposing the side face31g.

Also, when the semiconductor chip63is seen in plan view from a direction orthogonal to the face63a,the sealing resin65is provided in a region where the bottom face31eof the groove portion31dand the face63acoincide.

When seen in plan view, the relevant region is the range within which the face63aof the semiconductor chip63is positioned, as heretofore described. When seen in plan view, the sealing resin65is positioned in such a way as to enclose the die attach film68in this region.

Semiconductor Device Manufacturing Method

Hereafter, a method of manufacturing the semiconductor device10will be described as one example of a semiconductor device manufacturing method according to the present embodiment. Firstly, as shown inFIG.6A, a memory circuit101ais formed on an upper face of a semiconductor wafer101.

Next, as shown inFIG.6B, a thickness of the semiconductor wafer101is reduced by a lower portion of the semiconductor wafer101being removed. Specifically, a face on which the memory circuit101ais not formed, that is, a lower face of the semiconductor wafer101, is ground using a grinding wheel. By so doing, the thickness of the semiconductor wafer101is reduced.

Next, as shown inFIG.6C, the die attach film41ais attached to a lower face of the semiconductor wafer101.

Next, as shown inFIG.6D, the groove portion31dis formed in the lower face of the semiconductor wafer101. In the present embodiment, for example, a blade102is inserted several times into the semiconductor wafer101in the Y-axis direction in such a way that the groove portion31dis of a predetermined width. By so doing, a portion of the semiconductor wafer101is removed together with the die attach film41a,whereby the groove portion31dis formed.

Next, as shown inFIG.6E, the semiconductor wafer101is diced on the upper face of the semiconductor wafer101using a blade103. A dicing line104is on the semiconductor wafer101between dotted lines that indicate a position of the groove portion31d(formed in the lower face). A dicing line104is formed along the Y-axis direction. Also, although not specifically depicted, a dicing line104is also formed along the X-axis direction. The semiconductor wafer101is divided into the multiple semiconductor chips42aby dicing. After this process, the die attach film41ais divided into the die attach films41aaand41ab.

Next, as shown inFIG.6F, the semiconductor chip63is flip chip-connected to the wiring substrate25. Further, the sealing resin67is applied. The semiconductor chip63, the substrate electrode25b,the chip electrode63b,and the bump73are insulated and sealed by the sealing resin67.

Next, as shown inFIG.6G, die attach film68is disposed on the upper face63aof the semiconductor chip63.

Next, as shown inFIG.6H, the semiconductor chip42aafter having been detached from the semiconductor wafer101is disposed on the wiring substrate25. Specifically, the semiconductor chip42ais bonded to the face25aof the wiring substrate25by the die attach films41aaand41ab,and bonded to the face63aof the semiconductor chip63by the die attach film68.

Next, as shown inFIGS.1to3, the semiconductor chips42bto42dare stacked above the semiconductor chip42a.Furthermore, the bonding wire (s)61is formed.

Next, the semiconductor chips52ato52dare stacked above the semiconductor chip42d.Furthermore, the bonding wire (s)62is formed.

Next, filling with the sealing resin65is carried out. The stacked chip bodies40and50, the bonding wires61and62, the semiconductor chip63, the die attach film68, and the sealing resin67are insulated and sealed (covered) by the sealing resin65.

Advantages

The semiconductor device10is such that the space in which the semiconductor chip63is housed can be within the groove portion31dformed under the semiconductor chip42a.

Also, a distance between the face63aof the semiconductor chip63and the bottom face31eof the groove portion31dof the semiconductor chip42amay be reduced in order to reduce a Z-axis direction thickness of a package of the semiconductor device10.

If the die attach film68is not provided between the semiconductor chip63and the semiconductor chip42a,a narrow space may be formed/left between the semiconductor chip63and the semiconductor chip42a.

The filling of this kind of narrow space with the sealing resin65is difficult. As such, a void is likely to be left unfilled by the sealing resin65. When there is a void of this type, a vapor blowout or the like may occur at the void location during the carrying out a reflow process (high temperature processing), which is not desirable.

In response to this concern, the semiconductor device10includes the die attach film68between the semiconductor chip63and the semiconductor chip42ato mitigate such a potential problem. Because of this, formation of a void can be avoided, meaning that a good package for the semiconductor device10can be achieved.

Second Embodiment

A semiconductor device according to a second embodiment will be described. For the second embodiment, additional description of those aspects that are the same as (or substantially so) in the first embodiment will be omitted, and differing points will primarily be described. In general, the operational advantages for the first and second embodiments are similar.

FIGS.7and8are cross-sectional views of a semiconductor device according to the second embodiment.FIGS.7and8correspond in position within the semiconductor device in a similar manner asFIGS.2and3, respectively.

As shown inFIGS.7and8, compared with the semiconductor device10shown inFIGS.1to5, the semiconductor device11differs from the semiconductor device10according to the first embodiment in that, when the semiconductor chip63is seen in plan view in a direction orthogonal to the face63a,there is a portion68awhere the die attach film68protrudes beyond the face63a.

In the second embodiment, the protruding portion68aprotrudes in the +X-axis direction, −X-axis direction, the +Y-axis direction, and −Y-axis direction for the die attach film68. In some examples, the protruding portion68aprotrudes may protruded less than all directions and may protrude in just the direction along the X-axis or Y-axis.

Also, the protruding portion68adroops downward. A drooping portion of the protruding portion68acan be in contact with a side face of the semiconductor chip63. Not being limited to a configuration that droops downward from above, the protruding portion68amay be of a configuration that spreads while coming into contact with the bottom face31eof the groove portion31din the semiconductor chip42a,or may be of a configuration that spreads without coming into contact with either the side face of the semiconductor chip63or the bottom face31e.

Third Embodiment

A semiconductor device according to a third embodiment will be described.FIG.9is an enlarged view of a semiconductor chip and wiring substrate connection portion according to the third embodiment. As shown inFIG.9, as compared with the semiconductor device10shown inFIGS.1to5, the semiconductor device12differs from the semiconductor device10according to the first embodiment in that an electrical connection of the semiconductor chip63and the wiring substrate25is carried out via a bonding wire81.

Compared with the semiconductor device10shown inFIGS.1to5, the semiconductor device12includes a substrate electrode25c,a chip electrode63e,the bonding wire81, and a die attach film82instead of the substrate electrode25b,the chip electrode63b,the sealing resin67, and the bump73.

A lower face of the semiconductor chip63is bonded to the face25aof the wiring substrate25by the die attach film82.

The substrate electrode25cis provided on the face25aof the wiring substrate25. The chip electrode63eis provided on the upper face63aof the semiconductor chip63. The bonding wire81electrically connects the substrate electrode25cand the chip electrode63e.

In the third embodiment, the set of the substrate electrode25c,the chip electrode63e,and the bonding wire81is provided on each of the −X-axis direction and the +X-axis direction sides of the semiconductor chip63.

Multiple sets of the substrate electrode25c,the chip electrode63e,and the bonding wire81may be provided on the X-axis direction sides. Multiple sets of the substrate electrode25c,the chip electrode63e,and the bonding wire81may also or instead be provided on the Y-axis direction sides of the semiconductor chip63.

Fourth Embodiment

A semiconductor device according to a fourth embodiment will be described.FIG.10is a plan view in which a semiconductor device according to the fourth embodiment is seen from above.FIG.11is a cross-sectional view along a section line XI-XI shown inFIG.10. As shown inFIGS.10and11, compared with the semiconductor device10shown inFIGS.1to5, the semiconductor device13differs from the semiconductor device10according to the first embodiment in that one portion in the −Y-axis direction of the semiconductor chip63protrudes from the hole portion32through the aperture portion32b.

Compared with the semiconductor device10shown inFIGS.1to5, the semiconductor device13further includes die attach films35and37and a spacer36.

For example, the semiconductor chip63may be provided in a position partially separated from the substrate electrode25cin order to simplify the electrode pattern on the wiring substrate25.

In such a case, one portion in the −Y-axis direction of the face63aprotrudes beyond the semiconductor chip42awhen the semiconductor chip63is seen in plan view in a direction orthogonal to the face63a.That is, one portion in the semiconductor chip63is exposed by protruding from the hole portion32through the aperture portion32b.

However, as a space is now generated in the +Y-axis direction of the semiconductor chip63, support below the semiconductor chip42ais weakened. The die attach films35and37and the spacer36support the semiconductor chip42afrom below by being provided in the +Y-axis direction from the semiconductor chip63.

At least a portion of the spacer36may be provided on the aperture portion32aside of the hole portion32. Specifically, the spacer36is, for example, a semiconductor substrate formed by a semiconductor wafer being diced. A form of the spacer36is a plate form whose upper and lower faces are respectively faces36aand36bapproximately parallel to the XY plane.

The faces36aand36bare, for example, rectangular. A long side and a short side of each of the faces36aand36bare, for example, approximately parallel to the X-axis and the Y-axis respectively.

One portion in the +Y-axis direction of the face36aprotrudes from the semiconductor chip42awhen the spacer36is seen in plan view in a direction perpendicular to the face36a.That is, one portion in the Y-axis +direction of the spacer36is exposed by protruding from the hole portion32through the aperture portion32a.

The die attach film35is provided between the spacer36and the face25aof the wiring substrate25. The lower face36bof the spacer36is bonded to the face25aof the wiring substrate25by the die attach film35.

The die attach film37is provided between the spacer36and the bottom face31eof the groove portion31d.The upper face36aof the spacer36is bonded to the bottom face31eof the groove portion31din the semiconductor chip42aby the die attach film37.

Fifth Embodiment

A semiconductor device according to a fifth embodiment will be described.FIG.12is a plan view in which a semiconductor device according to the fifth embodiment is seen from above.FIG.13is a cross-sectional view along a section line XIII-XIII shown inFIG.12. As shown inFIGS.12and13, compared with the semiconductor device10shown inFIGS.1to5, the semiconductor device14differs from the semiconductor device10according to the first embodiment in that portions of the semiconductor chip63protrude from the hole portion32through the aperture portions32aand32b,respectively.

In some examples, a Y-axis direction width may decrease due to integration (miniaturization) of the semiconductor chips42and52improving. When the width of the semiconductor chip42abecomes small, both of the +Y-axis and −Y-axis direction ends of the semiconductor chip63may be allowed to protrude from the hole portion32through the aperture portions32aand32b,respectively.

A portion the face63aprotrudes in the +Y-axis direction from the semiconductor chip42awhen the semiconductor chip63is seen in plan view in a direction orthogonal to the face63a.That is, a portion of the semiconductor chip63is exposed by protruding from the hole portion32through the aperture portion32a.

Also, when seen in plan view, a portion of the face63aalso protrudes from the semiconductor chip42ain the −Y-axis direction. That is, a portion of the semiconductor chip63is exposed by protruding from the hole portion32through the aperture portion32b.

In certain example embodiments, a configuration in which the groove portion31dis formed in the Y-axis direction is described, but this is not limiting. A configuration in which the groove portion31dis formed in any other direction may be adopted.

In certain example embodiments, a configuration in which the stacked chip body40is formed in a stepped shape that deviates more the farther upward the semiconductor chip42is in the stack is described, but this is not limiting. A configuration in which the stacked chip body40is formed in such a way that both the X-axis direction and the Y-axis direction end faces of each semiconductor chip42coincide, without each semiconductor chip42being deviated (offset) in the Y-axis direction may be adopted. The same applies to the stacked chip body50.

In the certain example embodiments, a configuration in which the other semiconductor chips42are stacked above the semiconductor chip42ais described, but this is not limiting. A configuration without any other semiconductor chips42being stacked above the semiconductor chip42amay be adopted.

In certain example the embodiments, a configuration in which four semiconductor chips42are stacked in the stacked chip body40is described, but this is not limiting. A configuration with any number of stacked semiconductor chips42in the stacked chip body40may be adopted. In the same way, a configuration with any number of stacked semiconductor chips52in the stacked chip body50may be adopted.

In certain example embodiments, a configuration in which the semiconductor chip42in the stacked chip body40is electrically connected to the wiring substrate25by the bonding wire61ais described, but this is not limiting. A configuration in which the semiconductor chip42is electrically connected to the wiring substrate25using another connection method may be adopted. For example, the semiconductor chip42acan be electrically connected to the wiring substrate25by a flip chip connection or the like. The semiconductor chips42bto42dcan be electrically connected to the wiring substrate25using a through-silicon via that penetrates the semiconductor chip42a,or the like.

A semiconductor device manufacturing method according to the present disclosure is such that a semiconductor memory in which an electrode is provided on a first face of a semiconductor wafer is formed, a first bonding layer is disposed on a second face of the semiconductor wafer, a groove portion is formed by removing one portion of the first bonding layer and one portion of the second face of the semiconductor wafer, a semiconductor memory chip is formed by dicing the semiconductor wafer, a semiconductor memory controller chip is disposed on a wiring substrate, a second bonding layer is disposed on the semiconductor memory controller chip, the semiconductor memory chip is disposed on the wiring substrate in such a way that a bottom face of the groove portion formed in the semiconductor memory chip and the second bonding layer on the semiconductor memory controller chip come into contact and the wiring substrate and the first bonding layer come into contact, and at least the semiconductor memory chip is sealed using a sealing resin.

A semiconductor device according to the present disclosure includes a first semiconductor chip, which is a first semiconductor chip having a main face in which a groove portion that divides the main face into a first face and a second face is formed, a wiring substrate having a third face that opposes the first face and the second face of the first semiconductor chip, a first bonding layer provided between the first face of the first semiconductor chip and the third face of the wiring substrate, a second bonding layer provided between the second face of the first semiconductor chip and the third face of the wiring substrate, a second semiconductor chip of which at least one portion is disposed in a hole portion, which is a hole portion formed by the groove portion of the first semiconductor chip and the third face of the wiring substrate and which has a first aperture portion and a second aperture portion at either end, a third bonding layer provided between at least one portion of a bottom face of the groove portion and at least one portion of a fourth face of the second semiconductor chip that opposes the bottom face, and a sealing resin that seals at least the first semiconductor chip, in which the main face is rectangular, the groove portion divides the main face in such a way that the first face and the second face are rectangular, an area of the first face and an area of the second face are approximately the same, and the groove portion extends approximately parallel to a short side of the rectangle.