Method and apparatus for low latency proportional path in a digitally controlled system

A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO).

BACKGROUND

1. Technical Field

The present invention relates to latency reduction is a digitally controlled circuit and more particularly to a method and apparatus for latency reduction in digital phase locked loops (DPLLs) and digital delay locked loops (DDLLs).

2. Description of the Related Art

A proportional path is an important component of a proportional-integral-derivative (PID) controller. Digital PID controllers are used in digital phase locked loops (DPLL), digital delay locked loops (DDLL), hard disk drive read channels, and many other control systems. Note that application of the proportional control is not limited to PID controllers, it can be a part of a far more general control system. It is well known that delay in the proportional path is detrimental to the overall performance of the system.

In analog control systems (charge pump PLLs, for example), this problem is typically addressed by utilizing dual-loop controls with a high-bandwidth proportional path. In digitally controlled systems, like DPLL, the problem of lowering latency in the proportional path is particularly important since processing (weighting and applying) of the proportional control typically requires a few clock cycles. It should be noted that, unlike other components of the control system (the integral or differential paths, for example), the proportional path does not depend on the history of the error detector output.

FIG. 1illustrates an example of a proportional-integral (PI) loop filter in a DPLL. A digital phase-frequency error signal (ERROR) is first multiplied by the weight “P” of a proportional path by a multiplier12. Then, the output is combined by an adder14with an integral path control I which is multiplied by with ERROR by multiplier16and integrated by integrator18. The combined output is optionally scaled (Gain) and is finally applied to a digitally controlled oscillator (DCO)20.

Each of these operations requires one or more clock cycles and increases latency in the proportional path. Various techniques can be used to lower the latency of the digital blocks in the signal flow from the error input to the DCO controls. However, the state of the art approach inherently has non-zero latency which cannot be reduced below a certain limit.

SUMMARY

A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO).

A digitally controlled circuit and method includes an error input coupled to a proportional path and an integral path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO). The integral path includes a multiplier and integrator for processing an integrator weight for the DCO.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present principles provide embodiments uniquely suited for a high-bandwidth, low latency implementation of proportional paths. A method of processing a proportional digital control in accordance with the present principles does not need multiple clock cycles to process (processing may be performed in one or less cycles), thus achieving virtually zero latency. The present principles apply the proportional control directly to a digitally controlled oscillator (DCO), weighting the error signal off the critical path and using the DCO structure itself as a final adder.

Embodiments of the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment including both hardware and software elements. In a preferred embodiment, the present invention is implemented in hardware but may include software elements. Alternately, embodiments may be designed, modeled or otherwise implemented in software, which includes but is not limited to firmware, resident software, microcode, etc.

Referring now to the drawings in which like numerals represent the same or similar elements and initially toFIG. 2, an illustrative schematic diagram of a circuit100with a low latency proportional path102is shown in accordance with one embodiment. The proportional path102may be a component of a proportional-integral-derivative (PID) controller.FIG. 2illustrates an example of a proportional-integral (PI) loop filter in a digital phase locked loop (DPLL), although other circuits may be employed (e.g., a digital delay locked loop (DDLL), etc.). A digital phase-frequency error signal (ERROR) is input to two paths. The ERROR signal may be binary or non-binary. A proportional path101and an integral path103are shown. Proportional control is advantageously applied with near-zero delay, limited only by the time of flight from an error input104to a digitally controlled oscillator (DCO)106control.

In the case of a proportional-integral (PT) loop filter of a digital phase locked loop (DPLL), a proportional control (P) is weighted off the critical path (in this case from outside of proportional path101) by using a selector108(or multiplexer (MUX)). Outputs of the selector108can be binary weighted or use some other encoding (e.g., thermometer input, etc.). A digital error signal (ERROR) is directly applied to a select input of the selector108. The ERROR signal is also multiplied by I using a multiplier112and integrated with an integrator114. The output of the selector108is based on already settled (static or slowly changing) bits of the “P” inputs. The output of the selector108is a resulting weighted proportional control signal110which is immediately applied to the DCO106(e.g., as soon as the error signal (ERROR) arrives, no clock signals are needed).

For example, the DCO106includes a plurality of elements used to control its output. The elements may include delay elements, capacitors, inverters or the like. The number of elements activated is in accordance with the value of P. If the ERROR signal is binary (0, 1 or −1, 1), the value of P may respectively by (0, P or −P, P). The ERROR signal enables the selector108to output the needed value of “P”. The ERROR signal can be non-binary (or even analog) or include a binary word such that a more complicated output may be provided from selector108. For example, the selector108may select values such as ½P, 3P, −5P, etc. depending on the application and the DCO adjustment needed. An output from the selector108may be proportional to a feature of the error signal such as its magnitude.

Internal structure of the DCO108then takes care of a final addition of the integral (I) and proportional (P) controls. Reduction of delay will automatically result in an increase in performance of a digitally controlled system. An additional benefit of this new approach is a reduction in complexity, power dissipation and area of a digitally controlled system.

Referring toFIG. 3, an example circuit implementation of one illustrative embodiment is shown. A digitally controlled LC-tank oscillator circuit200is shown having a proportional control weight set by a choice of corresponding capacitors202,204and205. The capacitors202,204and205are formed from NFET transistors (varactors)206. Capacitors202and204are for course and fast control, respectively and capacitor205is for integral (I) control. An inductor207is employed in the LC circuit200.

Control transistors210and212, which are respectively PFETs (210) and NFETs (212) in this example, provide connections to power (VDDA) or ground. The addition of an integral control (I)222and proportional controls (course control201and fast control203) is performed by DCO dynamics and a DCO236is controlled using the controls201,203and222. Tail current is limited by a tail current limiting circuit233.

Fast proportional control203changes a capacitance value of varactors206and that in turn changes the overall frequency of the LC-tank oscillator. Since the resonance frequency is set by the total L and total C of the tank, the addition of the capacitance controls what happens inside the DCO236with little or no latency. Weighting of the proportional path gain is done by selecting the number of and/or sizes of capacitors204and/or varactors206to which the fast proportional control203is applied. This is provided by employing a selector225, which is responsive to an ERROR signal (or other signal). In accordance with the ERROR signal, a number (e.g., P) of capacitors204are activated to control the DCO236with little or no latency.

Another example includes a ring-oscillator based DCO, where the frequency tuning is achieved by either controlling the strength of the core delay elements or by simply turning on and off tri-state inverters. In other words, instead of a number of capacitors being activated as inFIG. 3, a number of inverters (e.g., tri-state inverters) are activated. In a ring-DCO, the fast proportional path control is applied directly to tri-state inverters inside the DCO. The gain of the proportional path is set by selecting how many tri-state inverters in the DCO are controlled by the proportional path and/or by the relative sizes of those inverters. The tri-state inverters are connected at the input and output to the main DCO phases thus directly contributing to the delays in the ring oscillator and changing its frequency. Similar to the LC-tank DCO example above, the addition of the effects of the integral and proportional paths controls what happens inside the DCO in an analog manner with virtually no delay, and no special digital hardware to achieve the effect of addition.

The present invention is not limited to a particular implementation of a proportional path control in a phase-locked loop. One extension is a microprocessor clock management unit, which is dynamically controlled by a critical path monitor (CPM). The CPM-based control can be realized as a PID-control, with the proportional path control using the absolute minimum delay. The DCO can have several fast proportional control inputs, differently weighted and representing different control loops.

Another example includes a DPLL system with DCO being controlled by several (two in this example) different control blocks (e.g., a Loop Filter and CPM Compensation), each representing various parts of different PID control systems. Note that the combined effect of all those controls is added in the DCO, in an analog manner and allows the fast proportional path implementation for each of these PID controls.

Referring toFIG. 4, a schematic diagram shows an illustrative example of a circuit having a DCO246controlled by two (or more) control loops. An ERROR1 signal is employed to control a fast proportional path251. A selector242selects a number of elements to activate in the DCO246. An ERROR2 signal is employed to control a second fast proportional path261. A selector244selects a number of elements to activate in the DCO246. Each of paths251and261provide control of the DCO246. The two paths251and261may have different time constants or provide different types of magnitudes of control. The outputs of selectors242and244may be combined or employed during different time periods of operation. Although two integration paths (I) are depicted, the two integration paths may not be needed.

Referring toFIG. 5, a method for reducing latency and power dissipation in a digitally controlled circuit is illustratively shown. In block302, an error signal is input to a proportional path and an integral path. In block304, the error signal is received as a select signal for a selector. In block306, a proportional control weight is received from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO). The proportional control weight is input to the DCO with near-zero delay. The near-zero delay may include only a time of flight from the error input to the DCO. This may be, e.g., less than one clock cycle.

In block308, a plurality of proportional control weights may be employed at the selector for input to the DCO. This depends on the design and the application of the circuit.

In block310, an integral weight is processed on the integral path for the DCO. In block312, the proportional control weight and an integral path signal are added in the DCO (e.g., the final addition). By providing, this structure at least one of latency, power dissipation and complexity are improved.