Memory device using semiconductor elements

Provided on a substrate are an N+ layer connecting to a source line SL and an N+ layer connecting to a bit line BL that are located at opposite ends of a Si pillar standing in an upright position along the vertical direction, an N layer continuous with the N+ layer, an N layer continuous with the N+ layer, a first gate insulating layer surrounding the Si pillar, a first gate conductor layer surrounding the first gate insulating layer and connecting to a plate line PL, and a second gate conductor layer surrounding a second gate insulating layer surrounding the Si pillar and connecting to a word line WL. A voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL is controlled to perform a data retention operation for retaining holes, which have been generated through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel region of the Si pillar, and a data erase operation for removing the holes from the channel region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to PCT/JP2021/017858, filed May 11, 2021, the entire content of which is incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a memory device using semiconductor elements.

BACKGROUND ART

In recent years, a higher degree of integration and higher performance of memory devices have been demanded in the development of the LSI (Large Scale Integration) technology.

In a common planar MOS transistor, a channel extends in the horizontal direction along the upper surface of a semiconductor substrate. In contrast, a channel of a SGT extends in a direction perpendicular to the upper surface of a semiconductor substrate (for example, see Patent Literature 1 and Non Patent Literature 1). Therefore, when SGTs are used, the density of a semiconductor device can be increased more than when planar MOS transistors are used. Using such SGTs as selection transistors can achieve a high degree of integration of, for example, DRAM (Dynamic Random Access Memory) with a capacitor connected thereto (for example, see Non Patent Literature 2), PCM (Phase Change Memory) with a variable resistance element connected thereto (for example, see Non Patent Literature 3), RRAM (Resistive Random Access Memory; for example, see Non Patent Literature 4), and MRAM (Magneto-resistive Random Access Memory) whose resistance is changed by changing the direction of a magnetic spin using a current (for example, see Non Patent Literature 5). There is also known a capacitorless DRAM memory cell including a single MOS transistor (see Non Patent Literature 6), for example. The present application relates to dynamic flash memory that can be formed with only a MOS transistor and without a variable resistance element or a capacitor.

FIGS.7A to7Dillustrate a write operation for the aforementioned capacitorless DRAM memory cell including a single MOS transistor,FIGS.8A and8Billustrate problems with the operation thereof, andFIGS.9A to9Cillustrate a read operation (see Non Patent Literatures 7 to 10).

FIGS.7A to7Dillustrate a write operation for the DRAM memory cell.FIG.7Aillustrates a “1” written state. Herein, the memory cell includes a source N+layer103(hereinafter, a semiconductor region containing a high concentration of donor impurities shall be referred to as an “N+layer”) connecting to a source line SL and a drain N+layer104connecting to a bit line BL, each formed in a SOI substrate100; a gate conductive layer105connecting to a word line WL; and a floating body102of a MOS transistor110a. The DRAM memory cell does not include a capacitor, and is formed with a single MOS transistor110a. It should be noted that the floating body102is in contact with a SiO2layer101of the SOI substrate immediately below the floating body102. When “1” is written to such a memory cell including a single MOS transistor110a, the MOS transistor110ais operated in the saturation region. That is, a channel107for electrons extending from the source N+layer103has a pinch-off point108, and thus does not reach the drain N+layer104connecting to the bit line. When the MOS transistor110ais operated while each of the bit line BL connected to the drain N+layer104and the word line WL connected to the gate conductive layer105is set at a high voltage and the gate voltage is set at a level of about ½ that of the drain voltage, the intensity of an electric field becomes maximum at the pinch-off point108around the drain N+layer104. Consequently, accelerated electrons flowing from the source N+layer103to the drain N+layer104collide with Si lattices, and electron-hole pairs are generated due to the kinetic energy lost during the collision (i.e., an impact ionization phenomenon). Most of the generated electrons (not illustrated) reach the drain N+layer104. Meanwhile, only some of the electrons that are very hot reach the gate conductive layer105beyond a gate oxide film109. In addition, holes106generated at the same time charge the floating body102. In such a case, since the floating body102is p-type Si, the generated holes contribute to increasing the majority carriers. When the floating body102is filled with the generated holes106and the voltage of the floating body102becomes higher than that of the source N+layer103, specifically, Vb or greater, the generated holes are further released to the source N+layer103. Herein, Vb is the built-in voltage of a P-N junction between the source N+layer103and the floating body102as the P-layer, and is about 0.7 V.FIG.7Billustrates a view in which the floating body102is saturated with and charged with the generated holes106.

Next, an operation of writing “0” to the memory cell110will be described with reference toFIG.7C. With respect to a common selected word line WL, there randomly exist memory cells110ato which “1” is written and memory cells110bto which “0” is written.FIG.7Cillustrates a view in which the state of the memory cell110changes from the “1” written state to the “0” written state. When “0” is written, the bit line BL is set at a negative bias voltage so that a P-N junction between the drain N+layer104and the floating body102as the P-layer is forward-biased. Consequently, the holes106, which have been generated in the floating body102in advance in the previous cycle, flow to the drain N+layer104connected to the bit line BL. When the write operation is complete, two states of the memory cells are obtained that include the memory cells110afilled with the generated holes106(FIG.7B) and the memory cells110bfrom which the generated holes have been discharged (FIG.7C). The potential of the floating body102in the memory cell110afilled with the holes106is higher than that of the floating body102without holes generated therein. Thus, the threshold voltage of the memory cell110ais lower than the threshold voltage of the memory cell110b.FIG.7Dillustrates such a state.

Next, problems with the operation of such a memory cell including a single MOS transistor will be described with reference toFIGS.8A and8B. As illustrated inFIG.8A, the capacitance CFBof the floating body102is equal to the sum of the capacitance OWL between the gate connecting to the word line and the floating body102, the junction capacitance CSLof the P-N junction between the source N+layer103connecting to the source line and the floating body102, and the junction capacitance CBLof the P-N junction between the drain N+layer104connecting to the bit line and the floating body102, and is represented as follows.
CFB=CWL+CBL+CSL(1)

Thus, when the voltage VWLof the word line oscillates during writing, the voltage of the floating body102as a storage node (i.e., a node) of the memory cell is also influenced.FIG.8Billustrates such a state. When the voltage VWLof the word line rises from 0 V to VProgWLduring writing, the voltage VFBof the floating body102rises from the voltage VFB1in the initial state before the voltage of the word line has changed to VFB2due to capacitive coupling with the word line. The amount of change in the voltage ΔVFBis represented as follows.
ΔVFB=VFB2−VFB1
=CWL/(CWL+CBL+CSL)×VProgWL(2)

Herein, β, which is referred to as a coupling ratio, is represented as follows.
β=CWL/(CWL+CBL+CSL)  (3)

In such a memory cell, the contribution rate of CWLis high, and, for example, CWL:CBL:CSL=8:1:1. In such a case, β=0.8. When the voltage of the word line has changed from 5 V during writing to 0 V at the completion of the writing, for example, the floating body102receives oscillation noise with 5 V×β=4 V due to the capacitive coupling between the word line and the floating body102. Therefore, there has been a problem in that a sufficient margin cannot be provided for the potential difference between the potentials of the floating body when “1” is written thereto and “0” is written thereto.

FIGS.9A to9Cillustrate a read operation. Specifically,FIG.9Aillustrates a “1” written state andFIG.9Billustrates a “0” written state. However, in practice, even when Vb has been written to the floating body102during writing of “1,” the floating body102is negative-biased once the voltage of the word line returns to 0 V at the completion of the writing. When “0” is written, the floating body102is negative-biased further deeply. Thus, as illustrated inFIG.9C, it would be impossible to provide a sufficient margin for the potential difference between when “1” is written and when “0” is written. Such a small operation margin has been a big problem with the present DRAM memory cell. In addition, it is also demanded to increase the density of such a DRAM memory cell.

CITATION LIST

Patent Literature

Non Patent Literature

SUMMARY OF INVENTION

Technical Problem

In a memory device using SGTs, each capacitorless single-transistor DRAM (i.e., a gain cell) involves strong capacitive coupling between a word line and a body of the SGT in a floating state, and thus has a problem in that when the potential of the word line is oscillated during data reading or data writing, the oscillation is directly transmitted as noise to the body of the SGT. Consequently, problems, such as erroneous reading and erroneous rewriting of memory data, occur, making it difficult to put the capacitorless single-transistor DRAM (i.e., the gain cell) into practical use. In addition to solving such problems, it is also necessary to increase the density of the DRAM memory cell.

Solution to Problem

To solve the aforementioned problems, a memory device according to the present invention includes

a semiconductor base material provided on a substrate in a manner standing in an upright position along a vertical direction or extending in a horizontal direction with respect to the substrate;

a first impurity layer and a second impurity layer having the same conductivity type and continuous with opposite ends of the semiconductor base material;

a first gate insulating layer partially or entirely surrounding a side face of the semiconductor base material on a side of the first impurity layer;

a second gate insulating layer continuous with the first gate insulating layer, and partially or entirely surrounding the side face of the semiconductor base material on a side of the second impurity layer;

a first gate conductor layer covering the first gate insulating layer;

a second gate conductor layer covering the second gate insulating layer; and

a third impurity layer provided between one or each of the first impurity layer and the second impurity layer and the semiconductor base material, the third impurity layer being provided in, in a central axis direction of the semiconductor base material, one or each of a region between the first gate conductor layer and the first impurity layer and a region between the second gate conductor layer and the second impurity layer, the third impurity layer having the same conductivity type as the first impurity layer and the second impurity layer, and being in contact with one or each of the first impurity layer and the second impurity layer,

in which:

each of a memory write operation, a memory read operation, and a memory erase operation is performed by controlling a voltage applied to each of the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer (first invention).

In the aforementioned first invention, a concentration of impurities in the third impurity layer is lower than a concentration of impurities in each of the first impurity layer and the second impurity layer and is higher than a concentration of impurities in the semiconductor base material (second invention).

In the aforementioned first invention, the third impurity layer is formed at a position continuous with the second impurity layer (third invention).

In the aforementioned first invention, the third impurity layer is formed at a position continuous with the first impurity layer (fourth invention).

In the aforementioned first invention, the third impurity layer is formed at each of a position continuous with the first impurity layer and a position continuous with the second impurity layer (fifth invention).

In the aforementioned first invention, a first gate capacitance between the first gate conductor layer and the semiconductor base material is larger than a second gate capacitance between the second gate conductor layer and the semiconductor base material (sixth invention).

The third impurity layer extends to an end portion of the semiconductor base material and to an outer peripheral portion continuous with the end portion (seventh invention).

In the aforementioned seventh invention, the semiconductor base material stands in an upright position along the vertical direction with respect to the substrate, and the first impurity layer and the third impurity layer continuous with the semiconductor base material extend to an outer side of the semiconductor base material as seen in plan view (eighth invention).

In the aforementioned first invention, the memory write operation is performed by controlling a voltage applied to each of the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer to perform an operation of generating electrons and holes in the semiconductor base material through an impact ionization phenomenon based on a current flowed between the first impurity layer and the second impurity layer or using a gate induced drain leakage current, to perform an operation of removing, from among the generated electrons and holes, the electrons or the holes that are minority carriers in the semiconductor base material, and to perform an operation of causing the electrons or the holes that are majority carriers in the semiconductor base material to partially or entirely remain in the semiconductor base material, and

the memory erase operation is performed by controlling a voltage applied to each of the first impurity layer, the second impurity layer, the first gate conductor layer, and the first gate conductor layer to remove from the semiconductor base material the electrons or the holes that are the majority carriers remaining in the semiconductor base material (ninth invention).

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the structure, a driving scheme, and a production method for a memory device using semiconductor elements (hereinafter referred to as dynamic flash memory) according to the present invention will be described with reference to the drawings.

First Embodiment

The structure, the operation mechanism, and a production method for a dynamic flash memory cell according to a first embodiment of the present invention will be described with reference toFIGS.1to5HA-5HC. The structure of the dynamic flash memory cell will be described with reference toFIG.1. Then, a data erasing mechanism will be described with reference toFIGS.2A to2C, a data writing mechanism will be described with reference toFIGS.3A to3C, and a data reading mechanism will be described with reference toFIGS.4AA to4AC. Then, a method for producing the dynamic flash memory will be described with reference toFIGS.5AA to5HC.

FIG.1illustrates the structure of the dynamic flash memory cell according to the first embodiment of the present invention. An N+layer3a(which is an example of a “first impurity layer” in the claims) is provided on a substrate1(which is an example of a “substrate” in the claims). A silicon semiconductor pillar2with p-type or i-type (intrinsic) conductivity containing acceptor impurities (which is an example of a “semiconductor base material” in the claims) (hereinafter, the silicon semiconductor pillar shall be referred to as a “Si pillar”) is provided on the N+layer3a. An N layer8a(which is an example of a “third impurity layer” in the claims) is provided at the bottom of the Si pillar2, and an N layer8b(which is an example of the “third impurity layer” in the claims) is provided at the top of the Si pillar2. An N+layer3b(which is an example of a “second impurity layer” in the claims) is provided on the N layer8b. The concentration of donor impurities in each of the N layers8aand8bis lower than that in each of the N+layers3aand3b. A portion of the Si pillar2between the N layers8aand8bis a channel region7. A first gate insulating layer4a(which is an example of a “first gate insulating layer” in the claims) and a second gate insulating layer4b(which is an example of a “second gate insulating layer” in the claims) are provided in this order from the lower side so as to surround the channel region7. The first gate insulating layer4aand the second gate insulating layer4bare respectively in contact with or located in proximity to the N layers8aand8b. A first gate conductor layer5a(which is an example of a “first gate conductor layer” in the claims) is provided so as to surround the first gate insulating layer4a, and a second gate conductor layer5b(which is an example of a “second gate conductor layer” in the claims) is provided so as to surround the second gate insulating layer4b. The first gate conductor layer5aand the second gate conductor layer5bare separated by an insulating layer6. The channel region7, which is the portion of the Si pillar2between the N layers8aand8b, includes a first channel region7asurrounded by the first gate insulating layer4aand a second channel region7bsurrounded by the second gate insulating layer4b. Accordingly, a dynamic flash memory cell is formed that includes the N+layers3aand3b, the N layers8aand8b, the channel region7, the first gate insulating layer4a, the second gate insulating layer4b, the first gate conductor layer5a, and the second gate conductor layer5b. The N+layer3aconnects to a source line SL (which is an example of a “source line” in the claims), the N+layer3bconnects to a bit line BL (which is an example of a “bit line” in the claims), the first gate conductor layer5aconnects to a plate line PL (which is an example of a “first drive control line” in the claims), and the second gate conductor layer5bconnects to a word line WL (which is an example of a “word line” in the claims). The N layers8aand8brespectively suppress the flow of unwanted electrons into the channel region7from the N+layer3aconnecting to the source line SL and the N+layer3bconnecting to the bit line BL in the dynamic flash memory due to the voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL. The dynamic flash memory cell desirably has such a structure that the gate capacitance of the first gate conductor layer5aconnecting to the plate line PL is larger than the gate capacitance of the second gate conductor layer5bconnecting to the word line WL. In the memory device, the aforementioned plurality of dynamic flash memory cells are two-dimensionally arranged on the substrate1.

It should be noted that inFIG.1, the gate length of the first gate conductor layer5ais set longer than the gate length of the second gate conductor layer5bsuch that the gate capacitance of the first gate conductor layer5aconnected to the plate line PL becomes larger than the gate capacitance of the second gate conductor layer5bconnected to the word line WL. However, it is also possible to, without setting the gate length of the first gate conductor layer5ato be longer than the gate length of the second gate conductor layer5b, make the thickness of the gate insulating film for the first gate insulating layer4ato be thinner than the thickness of the gate insulating film for the second gate insulating layer4b. Alternatively, it is also possible to set the dielectric constant of the first gate insulating layer4ato be higher than the dielectric constant of the second gate insulating layer4b. As a further alternative, it is also possible to combine any of the lengths of the gate conductor layers5aand5band the thicknesses and dielectric constants of the gate insulating layers4aand4bso that the gate capacitance of the first gate conductor layer5abecomes larger than the gate capacitance of the second gate conductor layer5b.

The position of the upper end of the N layer8ain the vertical direction may be located either above or below the position of the lower end of the first gate conductor layer5a. Similarly, the position of the lower end of the N layer8bmay be located either above or below the position of the upper end of the second gate conductor layer5b.

The first gate conductor layer5amay be split into two or more conductor layers, and the resulting two or more conductor layers may be operated synchronously or asynchronously as conductor electrodes for the plate line. Similarly, the second gate conductor layer5bmay be split into two or more conductor layers, and the resulting two or more conductor layers may be operated synchronously or asynchronously as conductor electrodes for the word line. Even with such a structure, the dynamic flash memory operation can be performed.

The dynamic flash memory operation can also be performed with a structure obtained by reversing the polarity of the conductivity of each of the N+layers3aand3b, the N layers8aand8b, and the p-type Si pillar2. In such a case, the majority carriers in the n-type Si pillar are electrons. Thus, electrons generated through impact ionization are stored in the channel region7, and the channel region7is thus set to the state “1.”

FIGS.2A to2Cillustrate the mechanism of an erase operation. The channel region7between the N layers8aand8bis electrically isolated from the substrate, and functions as a floating body.FIG.2Aillustrates a state in which holes11generated through impact ionization in a previous cycle are stored in the channel region7before the erase operation is started. As illustrated inFIG.2B, during the erase operation, the voltage of the source line SL is set to a negative voltage VERA. Herein VERAis −3 V, for example. Consequently, the P-N junction between the N+layer3aserving as a source connecting to the source line SL and the N layer8aand the channel region7is forward-biased regardless of the value of the initial potential of the channel region7. Thus, the holes11generated through impact ionization in the previous cycle and stored in the channel region7are sucked into the N+layer3aserving as the source portion and the N layer8a, and then, the potential VFBof the channel region7becomes VFB=VERA+Vb. Herein, Vb is the built-in voltage of the P-N junction, and is about 0.7 V. Thus, when VERA=−3 V, the potential of the channel region7becomes −2.3 V. Such a value corresponds to the potential level of the channel region7in the erase state. Therefore, when the potential of the channel region7functioning as the floating body becomes a negative voltage, the threshold voltage of the N-channel MOS transistor in the dynamic flash memory cell becomes high due to the substrate bias effect. Accordingly, as illustrated inFIG.2C, the threshold voltage of the second gate conductor layer5bconnecting to the word line WL becomes high. Such an erase state of the channel region7corresponds to logical memory data “0.” It should be noted that in reading data, setting the voltage applied to the first gate conductor layer5aconnecting to the plate line PL to be higher than the threshold voltage corresponding to the logical memory data “1” and lower than the threshold voltage corresponding to the logical memory data “0” can obtain such characteristics that no current flows even when the voltage of the word line WL is set high for reading the logical memory data “0” as illustrated inFIG.2C. The aforementioned conditions of the voltages applied to the bit line BL, the source line SL, the word line WL, and the plate line PL are only examples for performing an erase operation. Thus, other operating conditions may also be employed as long as an erase operation can be performed. For example, an erase operation may be performed by providing a voltage difference between the bit line BL and the source line SL.

FIGS.3A to3Cillustrate a write operation for the dynamic flash memory cell according to the first embodiment of the present invention. As illustrated inFIG.3A, 0 V, for example, is input to the N+layer3aconnecting to the source line SL, 3 V, for example, is input to the N+layer3bconnecting to the bit line BL, 2 V, for example, is input to the first gate conductor layer5aconnecting to the plate line PL, and 5 V, for example, is input to the second gate conductor layer5bconnecting to the word line WL. Consequently, as illustrated inFIG.3A, an annular inversion layer12ais formed in the first channel region7aon the inner side of the first gate conductor layer5aconnecting to the plate line PL, and a first N-channel MOS transistor region including the channel region7asurrounded by the first gate conductor layer5a(seeFIG.1) is operated in the saturation region. Thus, the inversion layer12aon the inner side of the first gate conductor layer5aconnecting to the plate line PL has a pinch-off point13. Meanwhile, a second N-channel MOS transistor region including the channel region7bsurrounded by the second gate conductor layer5bconnecting to the word line WL (seeFIG.1) is operated in the linear region. Thus, the second channel region7bon the inner side of the second gate conductor layer5bconnecting to the word line WL has no pinch-off point, and an inversion layer12bis formed on the entire surface. The inversion layer12bformed on the entire surface on the inner side of the second gate conductor layer5bconnecting to the word line WL functions as a substantial drain of the second N-channel MOS transistor region including the second gate conductor layer5b. Thus, an electric field in a first boundary region of the channel region7between the first N-channel MOS transistor region including the first gate conductor layer5aand the second N-channel MOS transistor region including the second gate conductor layer5b, which are connected in series, becomes maximum, and an impact ionization phenomenon occurs in the region. Such a region is a region on the source side as seen from the second N-channel MOS transistor region including the second gate conductor layer5bconnecting to the word line WL. Thus, such a phenomenon is called a source-side impact ionization phenomenon. Due to the source-side impact ionization phenomenon, electrons flow from the N+layer3aconnecting to the source line SL and the N layer8ato the N+layer3bconnecting to the bit line BL and the N layer8b. The accelerated electrons collide with Si lattice atoms, and electron-hole pairs are generated due to the kinetic energy. Some of the generated electrons flow into the first gate conductor layer5aand the second gate conductor layer5b, but most of them flow into the N+layer3bconnecting to the bit line BL. To write “1,” it is also possible to generate electron-hole pairs using a gate induced drain leakage (GIDL) current, and then fill the floating body FB with the generated holes (see Non Patent Literature 14). It should be noted that it is also possible to generate electron-hole pairs through an impact ionization phenomenon at the boundary between the N layer8aand the channel region7or the boundary between the N layer8band the channel region7.

As illustrated inFIG.3B, the generated holes11are the majority carriers in the channel region7, and charge the channel region7in a positively biased manner. Since the N+layer3aconnecting to the source line SL is at 0 V, the channel region7is charged up to the built-in voltage Vb (about 0.7 V) of the P-N junction between the N+layer3aconnecting to the source line SL and the N layer8aand the channel region7. When the channel region7is charged in a positively biased manner, the threshold voltage of each of the first N-channel MOS transistor region and the second N-channel MOS transistor region becomes low due to the substrate bias effect. Accordingly, as illustrated inFIG.3C, the threshold voltage of the N-channel MOS transistor in the second channel region7bconnecting to the word line WL becomes low. Such a written state of the channel region7is allocated as logical memory data “1.”

It should be noted that during the write operation, it is also possible to generate electron-hole pairs through an impact ionization phenomenon or using a GIDL current not in the aforementioned first boundary region but in a second boundary region between the N layer8aand the first channel semiconductor layer7aor a third boundary region between the N layer8band the second channel semiconductor layer7b, and then charge the channel region7with the generated holes11. It should be also noted that the aforementioned conditions of the voltages applied to the bit line BL, the source line SL, the word line WL, and the plate line PL are only examples for performing a write operation. Thus, other operating conditions may also be employed as long as a write operation can be performed.

A read operation for the dynamic flash memory cell according to the first embodiment of the present invention will be described with reference toFIGS.4AA-4AC to4BA-4BD. A read operation for the dynamic flash memory cell will be described with reference toFIGS.4AA to4AC. As illustrated inFIG.4AA, when the channel region7is charged up to the built-in voltage Vb (about 0.7 V), the threshold voltage of the N-channel MOS transistor drops due to the substrate bias effect. Such a state is allocated as the logical memory data “1.” As illustrated inFIG.4AB, in a memory block selected before a write operation is performed, the floating voltage VFBof the channel region7, which has been set to the erase state “0” in advance, is VERA+Vb. Through a write operation, the written state “1” is randomly stored. Consequently, logical memory data at logic levels “0” and “1” are created for the word line WL. As illustrated inFIG.4AC, reading is performed with a sense amplifier by utilizing the difference in level between the two threshold voltages for the word line WL. It should be noted that in reading data, setting the voltage applied to the first gate conductor layer5aconnecting to the plate line PL to be higher than the threshold voltage corresponding to the logical memory data “1” and lower than the threshold voltage corresponding to the logical memory data “0” can obtain such characteristics that no current flows even when the voltage of the word line WL is set high for reading the logical memory data “0” as illustrated inFIG.4AC.

The magnitude relationship between the gate capacitances of the first gate conductor layer5aand the second gate conductor layer5bduring a read operation for the dynamic flash memory cell according to the first embodiment of the present invention, and an operation related thereto will be described with reference toFIGS.4BA to4BD. It is desirable that the gate capacitance of the second gate conductor layer5bconnecting to the word line WL be designed to be smaller than the gate capacitance of the first gate conductor layer5aconnecting to the plate line PL. As illustrated inFIG.4BA, the length in the central axis direction of the first gate conductor layer5aconnecting to the plate line PL is set longer than the length in the central axis direction of the second gate conductor layer5bconnecting to the word line WL so that the gate capacitance of the second gate conductor layer5bconnecting to the word line WL becomes smaller than the gate capacitance of the first gate conductor layer5aconnecting to the plate line PL.FIG.4BBillustrates an equivalent circuit of a single cell of the dynamic flash memory inFIG.4BA. In addition,FIG.4BCillustrates the relationship among the coupled capacitances of the dynamic flash memory. Herein, CWL, represents the capacitance of the second gate conductor layer5b, CPLrepresents the capacitance of the first gate conductor layer5a, CBLrepresents the capacitance of the P-N junction between the N+layer3band the N layer8bserving as the drain and the second channel region7b, and CSLrepresents the capacitance of the P-N junction between the N+layer3aand the N layer8aserving as the source and the first channel region7a. As illustrated inFIG.4BD, when the voltage of the word line WL oscillates, the operation has influence as noise on the channel region7. Potential fluctuation ΔVFBof the channel region7at this time is represented as follows.
ΔVFB=CWL/(CPL+CWL+CBL+CSL)×VReadWL(1)

Herein, VReadWLis the oscillating potential of the word line WL during reading. As is obvious from Expression (1), ΔVFBcan be made small by setting the contribution rate of CWLlow in comparison with the entire capacitance CBL+CWL+CBL+CBLof the channel region7. CBL+CSLis the capacitance of the P-N junctions. To increase such capacitance, for example, the diameter of the Si pillar2is increased, which is, however, undesirable for downsizing the memory cell. In contrast, it is also possible to further reduce ΔVFBby setting the length in the central axis direction of the first gate conductor layer5aconnecting to the plate line PL to be further longer than the length in the central axis direction of the second gate conductor layer5bconnecting to the word line WL, without decreasing the degree of integration of the memory cell as seen in plan view. It should be noted that the aforementioned conditions of the voltages applied to the bit line BL, the source line SL, the word line WL, and the plate line PL are only examples for performing a read operation. Thus, other operating conditions may also be employed as long as a read operation can be performed. Such read operation may also be performed through a bipolar operation

A method for producing the dynamic flash memory of the present embodiment will be illustrated with reference toFIGS.5AA-5AC to5HA-5HC. In each drawing, (A) illustrates a plan view, (B) illustrates a cross-sectional view along line X-X′ in (A), (C) illustrates a cross-sectional view along line Y-Y′ in (A), and (D) in each ofFIGS.5FA to5FD and5GA to5GDillustrates a cross-sectional view along line X1-X1′. It should be noted that in the actual memory device, more than four dynamic flash memory cells are arranged in a matrix on a substrate20.

As illustrated inFIGS.5AA to5AC, an N+layer21, an N layer25A, a P layer22of Si, an N layer25B, and an N+layer23are formed in this order from the lower side on a substrate20. In addition, mask material layers24a,24b,24c, and24d, which are circular in shape as seen in plan view, are formed. It should be noted that the substrate20may be formed using SOI (Silicon On Insulator), single-layer or multi-layer Si, or other semiconductor materials. Alternatively, the substrate20may be a well layer including a single N layer, a single P layer, multiple N layers, or multiple P layers. It should be noted that the concentration of donor impurities in each of the N layers25A and25B is lower than that in each of the N+layers21and23and is higher than the concentration of acceptor impurities in the P layer.

Next, as illustrated inFIGS.5BA to5BC, the N+layer23, the N layer25B, the P layer22, and the upper portion of the N layer25A are etched using the mask material layers24ato24das masks so that an N layer25a, Si pillars22a,22b,22c, and22d(not illustrated), N layers25ba,25bb,25bc, and25bd(not illustrated), and N+layers23a,23b,23c, and23d(not illustrated) are formed on the N+layer21. It should be noted that in the aforementioned etching, the bottoms of the outer peripheries of the Si pillars22ato22dmay be located in the N+layer21.

Next, as illustrated inFIGS.5CA to5CC, a SiO2layer26is formed on the N layer25aon the outer peripheries of the Si pillars22ato22d. Then, a gate insulating layer HfO2layer27is formed covering the entire surface, using ALD (Atomic Layer Deposition), for example. Then, a TiN layer (not illustrated) to serve as a gate conductor layer is formed covering the entire surface. Then, the TiN layer is polished through CMP (Chemical Mechanical Polishing) so that its upper surface position is located at the level of the upper surfaces of the mask material layers24ato24d. Then, the TiN layer is etched through RIE (Reactive Ion Etching) so that its upper surface position in the vertical direction is located closer to the upper portions of the Si pillars22ato22dthan to the intermediate positions thereof, whereby a TiN layer28is formed. It should be noted that the HfO2layer27may be other insulating layers including a single layer or multiple layers as long as such an insulating layer functions as a gate insulating layer. In addition, as the TiN layer28, other conductor layers including a single layer or multiple layers may be used as long as such a conductor layer has the function of a gate conductor layer.

Next, as illustrated inFIGS.5DA to5DC, a SiO2layer33is formed on the TiN layer28.

Next, as illustrated inFIGS.5EA to5EC, a portion of the HfO2layer27at a level above the SiO2layer33is etched so that a HfO2layer27ais formed. Then, a HfO2layer27bis formed on the entire surface. Then, a TiN layer (not illustrated) is formed covering the entire surface using the CVD method. Then, the TiN layer is polished using the CMP method so that its upper surface position is located at the level of the upper surfaces of the mask material layers24ato24d. Then, the TiN layer is etched using the RIE method so that its upper surface position is located at a level around the lower ends of the N layers25bato25bd. Then, a SiN layer37a, which surrounds the side faces of the N layers25baand25bb, the N+layers23aand23b, and the mask material layers24aand24band is continuous, is formed. Similarly, a SiN layer37b, which surrounds the side faces of the N layers25bcand25bd, the N+layers23cand23d, and the mask material layers24cand24dand is continuous, is formed. Then, the TiN layer is etched using the SiN layers37aand37bas masks so that TiN layers36aand36bare formed. Herein, the distance L1between two intersections between line X-X′ and the outer circumferential lines of the HfO2layer27bsurrounding the Si pillars22aand22bis set shorter than twice the width L2of each of the SiN layers37aand37balong line Y-Y′, and the distance L3between two intersections between line Y-Y′ and the outer circumferential lines of the HfO2layer27bsurrounding the Si pillars22aand22cis set longer than twice the width L2. Accordingly, the SiN layer37acan be formed such that it is continuous around the Si pillars22aand22band is separated from the SiN layer37b. Similarly, the SiN layer37bis formed such that it is continuous around the Si pillars22cand22dand is separated from the SiN layer37a.

Next, as illustrated inFIGS.5FA to5FD, a SiO2layer39is formed that includes voids41aa,41ab,41ac,41ba,41bb,41bc,41ca,41cb, and41ccbetween the side faces of and around the TiN layers36aand36band the SiN layers37aand37b. It should be noted that the voids41aa,41ab,41ac,41ba,41bb,41bc,41ca,41cb, and41ccare formed such that their upper end positions are located at a level lower than the upper end positions of the TiN layers36aand36bindicated by the dotted line inFIG.5FD.

Next, as illustrated inFIGS.5GA to5GD, the mask material layers24ato24dare etched so that contact holes40a,40b,40c, and40dare formed.

Next, as illustrated inFIGS.5HA to5HC, a conductor layer42aof a bit line BL1is formed that connects to the N+layers23aand23cvia the contact holes40aand40c, respectively, and also, a conductor layer42bof a bit line BL2is formed that connects to the N+layers23band23dvia the contact holes40band40d, respectively. Then, a SiO2layer43is formed that includes voids44a,44b, and44cbetween and on the opposite sides of the conductor layer42aof the bit line BL1and the conductor layer42bof the bit line BL2. Accordingly, dynamic flash memory is formed on the substrate20. The TiN layers36aand36brespectively serve as conductor layers of word lines WL1and WL2. The TiN layer28serves as a conductor layer of the plate line PL that also serves as a gate conductor layer. The N+layer21serves as a conductor layer of the source line SL that also serves as a source impurity layer. Accordingly, dynamic flash memory is formed on the substrate20.

It should be noted that it is acceptable as long as the present dynamic flash memory element described in the present embodiment has a structure that satisfies the condition that the holes11generated through an impact ionization phenomenon or using a gate induced drain leakage current are retained in the channel region7. To this end, it is acceptable as long as the channel region7has a floating body structure isolated from the substrate1. Accordingly, even when the semiconductor base material of the channel region is formed horizontally on the substrate1using the GAA (Gate All Around; for example, see Non Patent Literature 11) technology, which is one of SGTs, or the nanosheet technology (for example, see Non Patent Literature 12), for example, the aforementioned dynamic flash memory operation can be performed. Alternatively, a device structure using SOI (Silicon On Insulator; for example, see Non Patent Literatures 7 to 10) may also be used. In such a device structure, the bottom of the channel region is in contact with an insulating layer of a SOI substrate, and the channel region is surrounded by a gate insulating layer and element isolation insulating layers together with other channel regions. Even in such a structure, the channel region has a floating body structure. In this manner, it is acceptable as long as the dynamic flash memory element provided by the present embodiment satisfies the condition that its channel region has a floating body structure. Further, even with a structure in which a Fin transistor (for example, see Non Patent Literature 13) is formed on a SOI substrate, the present dynamic flash memory operation can be performed as long as its channel region has a floating body structure.

It should be noted that inFIG.1, the length in the central axis direction of the first gate conductor layer5aconnecting to the plate line PL is set further longer than the length in the central axis direction of the second gate conductor layer5bconnecting to the word line WL so that CBL>CWL. However, it is possible to reduce the capacitive coupling ratio (CWL(CBL+CWL+CBL+CSL)) of the word line WL to the channel region7only by adding the plate line PL. Consequently, potential fluctuation ΔVFBof the channel region7as the floating body becomes small.

In addition, a fixed voltage of 2 V, for example, may be applied as the voltage VErasePLof the plate line PL regardless of each operation mode. In addition, 0 V, for example, may be applied as the voltage VErasePLof the plate line PL only during erasing. Further, a fixed voltage or a voltage that changes with time may be applied as the voltage VErasePLof the plate line PL as long as such a voltage satisfies the condition that the dynamic flash memory operation can be performed.

Although description has been made with reference toFIGS.5AA-5AC to5HA-5HCusing the Si pillars22ato22dwith rectangular vertical cross-sections, the Si pillars22ato22dmay also have trapezoidal vertical cross-sections. In addition, portions of the Si pillars22ato22dsurrounded by the HfO2layer27aand those surrounded by the HfO2layer27bmay have different vertical cross-sectional shapes, such as a rectangular shape and a trapezoidal shape. This is also true of a case where the Si pillars are horizontal with respect to the substrate20.

InFIG.1, in a portion of the channel region7surrounded by the insulating layer6, potential distributions of the first channel region7aand the second channel region7bare formed continuously. Accordingly, the channel region7including the first channel region7aand the second channel region7bis continuous in the vertical direction across its region surrounded by the insulating layer6.

In addition, as illustrated inFIGS.5HA to5HC, the N+layer21also serves as a wire conductor layer of the source line SL. As the source line SL, it is also possible to use a conductor layer, such as a W layer, for example, formed between portions of the N+layer21at the bottoms of the Si pillars22ato22d. Further, it is also possible to form a conductor layer of metal, such as a W layer, or alloy, for example, on the N+layer21on the outer side of the region where more Si pillars22ato22dare formed two-dimensionally.

InFIG.1, the first gate conductor layer5aconnecting to the plate line PL is provided adjacent to the N+layer3aconnecting to the source line SL, and the second gate conductor layer5bconnecting to the word line WL is provided adjacent to the N+layer3bconnecting to the bit line BL, but it is also possible to connect the first gate conductor layer5ato the word line WL and connect the second gate conductor layer5bto the plate line PL. Further, one or both of the first gate conductor layer5aand the second gate conductor layer5bmay be split into a plurality of conductor layers.

The present embodiment has the following features.

In the dynamic flash memory cell according to the first embodiment of the present invention, the voltage of the word line WL oscillates up and down while a write operation or a read operation is performed on the dynamic flash memory cell. At this time, the plate line PL performs the role of reducing the capacitive coupling ratio between the word line WL and the channel region7. Consequently, it is possible to significantly suppress the influence of changes in the voltage of the channel region7when the voltage of the word line WL oscillates up and down. Accordingly, it is possible to increase the difference between the threshold voltages corresponding to logic levels of “0” and “1.” This leads to an increased operation margin of the dynamic flash memory cell.

The N layers8aand8binFIG.1suppress the flow of unwanted electrons into the channel region7from one or both of the N+layer3aconnecting to the source line SL and the N+layer3bconnecting to the bit line BL in the dynamic flash memory due to the voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL or due to the influence of noise of capacitive coupling with the neighboring memory cells. In addition, as the intensity of an electric field in each of the regions of the N layers8aand8bcan be made lower than when the N layers8aand8bare not provided, leakage current can be reduced. This leads to an improvement in the data retention characteristics. Accordingly, a stable operation of the dynamic flash memory can be achieved, leading to higher performance.

The N layer25aillustrated inFIGS.5HA to5HCperforms the role of suppressing the flow of unwanted electrons into the Si pillars22ato22dfrom the N+layer21and also performs the role of the sources or drains of the respective SGT transistors having the Si pillars22ato22das their channels. In addition, the N+layer21also performs the role of a low-resistance connection electrode for the N layer25aserving as the sources or drains. As illustrated inFIGS.5HA to5HC, the N layer25aand the N+layer21are located below the Si pillars22ato22dand on the entire surface of the substrate20. In addition, the N+layer21connects to a metal or alloy conductor layer provided in a region between or on the outer sides of the Si pillars22ato22d. Providing the N+layer21allows the voltage of the source line SL to be applied more uniformly to the N layer25abelow the Si pillars22ato22d. Accordingly, a stable data retention operation can be performed with the dynamic flash memory, leading to higher performance.

Second Embodiment

Dynamic flash memory of a second embodiment will be described with reference toFIG.6. InFIG.6, portions identical to or similar to those inFIG.1are denoted by identical reference signs.

As illustrated inFIG.6, the N layer8binFIG.1is not provided between the N+layer3bat the top of the Si pillar2and the channel region7inFIG.1. The other portions are the same as those inFIG.1.

The present embodiment has the following features.

As in the first embodiment, the N layer8asuppresses the flow of unwanted electrons into the channel region7from the N+layer3aconnecting to the source line SL in the dynamic flash memory due to the voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL or due to the influence of noise of capacitive coupling with the neighboring memory cells. In addition, since the N layer8binFIG.1, which becomes series resistance, is not provided between the N+layer3band the channel region7, a higher-speed operation of the dynamic flash memory can be achieved. In this manner, a stable operation of the dynamic flash memory can be achieved, and higher performance can be achieved.

Alternatively, even when the N layer8ais not provided and the N layer8binFIG.1is provided between the channel region7and the N+layer3b, advantageous effects similar to those described above can be obtained. In this manner, providing the N layer8aor the N layer8bin contact with the N+layer3aor3bcan achieve a stable operation of the dynamic flash memory and also achieve higher performance.

Other Embodiments

Although the Si pillars2and22ato22dare formed in the aforementioned embodiments, it is also possible to form semiconductor pillars of a semiconductor material other than Si. This is also true of the other embodiments according to the present invention.

Each of the N+layers3a,3b,21, and23in the first embodiment may also be formed of a layer of Si or other semiconductor materials containing donor impurities. In addition, the N+layers3a,3b,21, and23may be formed of layers of different semiconductor materials. The N+layers may be formed using the epitaxial crystal growth method or other methods. Meanwhile, each of the N layers25a,25ba,25bb,25bc, and25bdmay also be formed of a layer of Si or other semiconductor materials containing donor impurities. The N layers may be formed using the epitaxial crystal growth method or other methods. Each of the N layers8a,8b, and25bato25bdneed not be uniform in the channel direction. This is also true of the other embodiments according to the present invention.

In the first embodiment, the TiN layer28is used as the plate line PL and the gate conductor layer5aconnecting to the plate line PL. In contrast, it is also possible to use a single conductor material layer or multiple conductor material layers combined together instead of the TiN layer28. Likewise, the TiN layers36aand36bare used as the word lines WL and the gate conductor layers5bconnecting to the respective word lines WL. In contrast, it is also possible to use a single conductor material layer or multiple conductor material layers combined together instead of each of the TiN layers36a, and36b. In addition, the outer side of each gate TiN layer may connect to a wire metal layer of W, for example. This is also true of the other embodiments according to the present invention.

InFIGS.5AA-5AC to5HA-5HC, it is also possible to use low-resistance doped poly-Si instead of the TiN layer28, and oxidize the upper surface thereof to form a SiO2layer as an interlayer dielectric between the gate conductor layer (which corresponds to the TiN layer28) and each of the TiN layers36aand36b. In such a case, it is also possible to use two layers including a thin TiN layer and a thick low-resistance doped poly-Si layer as the gate conductor layer. This is also true of the other embodiments according to the present invention. In addition, it is also possible to use other conductor layers instead of low-resistance doped poly-Si. This is also true of the other embodiments according to the present invention.

In the first embodiment, the shape of each of the Si pillars22ato22das seen from its central axis direction is circular. However, it may be circular, elliptical, or a shape elongated in one direction, for example. It is also possible to form Si pillars with different shapes as seen in plan view in a mixed manner in a logic circuit region, which is formed away from the region of the dynamic flash memory cells, in accordance with the logic circuit design. This is also true of the other embodiments according to the present invention.

RegardingFIG.1, description has been made using the Si pillar2with a rectangular vertical cross-section. However, the vertical cross-sectional shape may also be trapezoidal. Further, the vertical cross-sectional shape of a portion of the Si pillar2surrounded by the first gate insulating layer4aand that surrounded by the second gate insulating layer4bmay differ, such as a rectangular shape and a trapezoidal shape. This is also true of the other embodiments according to the present invention.

In the description of the first embodiment, the source line SL is negative-biased during an erase operation so that holes in the channel region7functioning as the floating body FB are pulled out. However, it is also possible to perform an erase operation by negative-biasing the bit line BL instead of the source line SL, or negative-biasing the source line SL and the bit line BL. Alternatively, an erase operation may be performed under other voltage conditions. This is also true of the other embodiments according to the present invention.

In the steps illustrated inFIGS.5AA-5AC to5HA-5HC, the N layers25aand25bato25bdare formed using the epitaxial growth method. In contrast, the N layers25aand25bato25bdmay also be formed using the ion implantation method. Alternatively, it is also possible to form the N layers25aand25bato25bdby diffusing donor impurities from the N+layers21and23ato23dthrough heat treatment. Such heat treatment may be performed through rapid thermal annealing treatment in a short time. In such a case, the N layers25A and25B need not be formed in the step ofFIGS.5AA to5AC. This is also true of the other embodiments according to the present invention.

In addition, inFIGS.5AA-5AC to5HA-5HC, the bottom N layer25aand N+layer21connecting to the source line SL are formed such that they are continuous at the bottoms of the Si pillars22ato22d. In contrast, it is also possible to form as the bottom N layer and N+layer connecting to the source line SL, as seen in plan view, an N layer and an N+layer that are continuous at the bottoms of the Si pillars22aand22b, and an N layer and an N+layer that are electrically isolated therefrom and are continuous at the bottoms of the Si pillars22cand22d. In addition, it is also possible to form as the bottom N layer and N+layer connecting to the source line SL, as seen in plan view, an N layer and an N+layer that are continuous at the bottoms of the Si pillars22aand22c, and an N layer and an N+layer that are electrically isolated therefrom and are continuous at the bottoms of the Si pillars22band22d. The electrical isolation between such N layers and N+layers connecting to the source line SL is achieved using a well structure or SOI, for example. Accordingly, the source line connecting to the N layer and the N+layer at the bottoms of the Si pillars22aand22band the source line SL connecting to the N layer and the N+layer at the bottoms of the Si pillars22cand22dcan be driven independently. Alternatively, the source line connecting to the N layer and the N+layer at the bottoms of the Si pillars22aand22cand the source line SL connecting to the N layer and the N+layer at the bottoms of the Si pillars22band22dcan be driven independently. In such a case, it is desirable to provide a conductor layer of metal or alloy, for example, such that it connects to both the isolated N layers and N+layers or the isolated N+layers. This is also true of the other embodiments according to the present invention.

In addition, inFIGS.5AA-5AC to5HA-5HC, the TiN layer28is formed continuous around the Si pillars22ato22d. In contrast, it is also possible to separately form as the TiN layer a gate conductor layer that is continuous around the Si pillars22aand22band a gate conductor layer that is continuous around the Si pillars22cand22d. Accordingly, the separate gate conductor layers can be driven independently. This is also true of the other embodiments according to the present invention.

Further, inFIG.1, the position of the upper end of the N layer8ain the channel direction may overlap the first gate conductor layer5a. Similarly, the position of the lower end of the N layer8bin the channel direction may overlap the second gate conductor layer5b. This is also true of the other embodiments according to the present invention.

The present invention can be implemented in various embodiments and modifications without departing from the broad spirit and scope of the present invention. In addition, each of the aforementioned embodiments only describes an example of the present invention and is not intended to limit the scope of the present invention. The aforementioned examples and modified examples can be combined as appropriate. Further, even if some of the components of the aforementioned embodiments are removed as needed, the resulting structure is within the technical idea of the present invention.

INDUSTRIAL APPLICABILITY

With the memory device using the semiconductor elements according to the present invention, it is possible to obtain high-density and high-performance dynamic flash memory.