Semiconductor device with solder on pillar

A semiconductor die includes a substrate including a semiconductor surface including circuitry electrically connected to die bond pads that include a first die bond pad exposed by a passivation layer, a top dielectric layer over the passivation layer, and a metal layer electrically connected to the first die bond pad. A pillar is on the metal layer over the first die bond pad, and a solder cap is on a top side of the pillar. The solder cap includes an essentially vertical sidewall portion generally beginning at a top corner edge of the pillar.

FIELD

This Disclosure relates to semiconductor devices having pillars on bond pads, with solder on the pillars.

BACKGROUND

One semiconductor technology is known as “wafer level chip scale packaging” with the packages known as wafer level chip scale packages (“WCSPs”), which are also known as WCSP die. Using a WCSP, unpackaged semiconductor dies without any surrounding layer of protective encapsulation such as a mold compound, are generally mounted on printed circuit boards (PCB). The structures needed for electrical connection of a WCSP to a PCB are usually fabricated on one surface of the semiconductor die while the plurality of semiconductor die are still integrally connected together on a single wafer.

For example, in a conventional form of WCSP, various layers including contact pads and then solder bumps thereon are formed on respective dies at the wafer level. For this purpose, at least one redistribution layer (RDL) is used which is an extra metal layer on a semiconductor die above the top metal layer that makes the input/output (I/O) pads of an integrated circuit (IC) available in other locations. After wafer singulation the WCSP may be attached, solder bumped top side down, onto a PCB. WCSPs have the advantage of being considerably smaller in size as compared to conventionally packaged IC dies and are thus suited for certain applications, such as cellular phones and digital tablets, where the associated PCB is often constrained to have a small footprint.

FIG.1shows a portion of conventional WCSP100shown as a bump on pad copper on anything (BOPCOA) structure including a solder ball128for an electrical connection to the bond pads108of the WCSP100. A passivation (overcoat) layer112is generally formed in the wafer fabrication facility over the top metal layer that includes the bond pads108, where the passivation layer112includes apertures to expose the bond pads108that are electrically connected to nodes in the circuitry180. There are 3 additional layers described below (besides the seed layers) that electrically contact the bond pad108which are added on top of the passivation layer112that is performed during the wafer level bump processing.

There is a first seed layer121under a RDL122that generally comprises copper, and a dielectric layer123typically comprising a polyamide (PI) that is on the RDL122. There is a second seed layer124above the dielectric layer123. There is pillar125on the second seed layer124, and a solder ball128(also called a solder cap) on top of the pillar125. In the case of a flipchip on lead device, such as a flipchip quad flat no lead (QFN) package, the pillar125is generally substantially taller (such as 50-100 μm) as compared to the pillar height in the case of a WCSP100(such as 10-30 μm). The solder ball128can be seen to have a conventional hemispherical geometry throughout that flattens slightly after reflow.

SUMMARY

Disclosed aspects recognize for forming solder balls a mount stud on stencil is conventionally used for ball drop purposes. For smaller sized die, a mount stud is defined to be within the die to avoid alignment offsets. However, for smaller and more aggressive die layouts that have solder ball placement relatively close together, such as a ball to ball (B2B) minimum spacing of 60 μm, there is insufficient space to place a mount stud.

Disclosed methods include forming solder caps on top of pillars that are on bond pads of a die, that includes changing the process flow from a conventional photoresist strip/etch before solder ball drop to the photoresist strip/etch after the solder ball drop. A heat resistant (or thermo resistant) material, such as a high temperature resistant photoresist, is used which enables removal of the heat resistant material after solder ball drop, since it can withstand the reflow processing. The heat resistant material defines a cavity around the bond pads that can improve solder ball placement (by being within the cavity) and also the solder reflow.

Disclosed aspects include a semiconductor die that includes a substrate including a semiconductor surface including circuitry electrically connected to die bond pads including a first die bond pad exposed by a passivation layer, a top dielectric layer over the passivation layer, and a metal layer, such as an RDL, that is electrically connected to the first die bond pad. A pillar is on the metal layer over the first die bond pad, and a solder cap is on a top side of the pillar. The solder cap includes an essentially vertical sidewall portion generally beginning at a top corner edge of the pillar.

DETAILED DESCRIPTION

Also, the terms “connected to” or “connected with” (and the like) as used herein without further qualification are intended to describe either an indirect or direct electrical connection. Thus, if a first device “connects” to a second device, that connection can be through a direct electrical connection where there are only parasitics in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect connecting, the intervening item generally does not modify the information of a signal but may adjust its current level, voltage level, and/or power level.

FIGS.2A-Hare successive views of an in-process semiconductor die shown by example as an WCSP die corresponding to results following steps in an example method of forming a semiconductor die having a solder cap on the pillars, wherein the solder cap has a base (lower) portion that is essentially vertical, according to an example aspect.FIG.2Ashows results after forming a RDL122over a first die bond pad108on a substrate105comprising a semiconductor surface including circuitry180electrically connected to die bond pads including the first die bond pad108exposed by a passivation layer112. A seed layer generally used under the RDL122is not shown for simplicity. The RDL122includes a first trace (not shown) electrically connected to a portion that may be referred to as being a contact pad over the RDL122which is on top of the first die bond pad108.FIG.2Bshows results after forming a top dielectric layer211(generally comprising a polyimide) over the passivation layer112with an aperture over the first die bond pad108.

FIG.2Cshows results after forming a seed layer124then a heat resistant coating237(that is generally a photoresist) on the seed layer124, andFIG.2Dshows results after patterning the heat resistant coating237to define a cavity237awith an essentially vertical sidewall again meaning the sidewall is an angle of 85 deg+/−5 degs relative to a top surface of the substrate105, wherein the cavity237ais over a top surface of the first die bond pad108, and then forming a pillar225that electrically contacts the RDL122. The cavity237aaround the bond pads can improve solder ball placement by being within the cavity and also the solder reflow. The typical reflow temperature range for Pb-Free (Sn/Ag) solder is generally 240-250° C. with 40-80 seconds at a temperature over 220° C.

The heat resistant coating237can be a material other than photoresist, such as a silicon compound, for example, silicon oxide. As used herein, a heat resistant coating is a coating that can withstand a temperature of at least 250° C. without measurable deformation, and also can be removed after reflow. In the case of a photoresist, the heat resistant coating in one specific example can be the material marketed as THB-151N (a negative tone photoresist) obtainable from JSR Micro Inc.

FIG.2Eshows results after a solder ball228is formed on a top surface of the pillar225andFIG.2Fshows results following a reflow step that due to solder reflow conforms the solder to the shape of the cavity237a(which has 85 deg+/−5 deg sidewalls), where the solder after reflow is now referred to as being a solder cap229. The solder cap229can be seen to have taken on its shape having essentially vertical sidewalls beginning at a top corner edge of the pillar225from the cavity237adescribed above defined by the heat resistant coating237.

FIG.2G. shows the solder cap229having a mushroom shape, the presence of this feature depending on the thickness of the heat resistant coating237. If the thickness of the heat resistant coating237is >100 μm, then no mushroom shape will generally be present since the solder volume will generally not be enough to flow over the surface of the heat resistant coating237, as shown inFIG.2G. If the thickness of the heat resistant coating237is <100 μm, then, depending on how much heat resistant coating is <100 μm, one can generally expect either a slight rounding of the top of the solder cap229, as shown inFIG.2F, or a mushroom shape of the solder cap229, as shown inFIG.2G, when the heat resist coating237is less than it is inFIG.2F. Moreover, the same flatness, rounding or mushrooming of the tip surface of solder cap229could also be obtained by varying the amount of solder in proportion to the thickness of the heat resistant coating237.

After the reflow step that generally includes a peak temperature of at least 240° C., as shown inFIG.2Has being semiconductor die250which adds another identical bonding structure as inFIG.2Eincluding a disclosed solder cap229, the heat resistant coating237is removed, and the seed layer124is etched. The solder cap229as noted above due to the presence of the cavity237abeing a confining structure at the time of the reflow still includes the essentially vertical sidewall portion beginning at a top corner edge of the pillar225. The minimum distance between the respective solder caps229can be no more than 60 μm. When this distance is less than 60 μm, there may be solder ball drop challenges both in the hardware process and in the integrity (ball to ball isolation) of the solder ball placement.

FIG.3Ais a cross-sectional view of an example flipchip package300including a semiconductor die320including pillars225on an RDL122on bond pads108of a substrate105having circuitry180, with a solder cap229that has a base portion that is essentially vertical on top of the pillars225, according to an example aspect. The package300is shown mounted on bonding features (metal pads)315a1,315a2,315a3of a top layer of a multi-level package substrate310including a top metal layer315ahaving an associated top dielectric layer315band vias315v. The flipchip package300also includes a mold material386covering the semiconductor die320and a top surface of package substrate310.

FIG.3A(andFIG.3Bdescribed below) show the optional feature of the straight sidewalls on the solder caps229being maintained (not deformed) even after another reflow process is implemented, in the case of flipchip package300to reflow the solder in solder caps229to attach to metal pads315a1,315a2,315a3of the multi-level packet substrate retention. The straight sidewall portion of the solder caps229can be deformed by this subsequent reflow. There are also methods to maintain the straight wall structures for the solder cap229after the subsequent reflow, one example being to limit the flux dip depth (such as a depth between 10 and 40 μm) to only wet around the tip of solder instead of submerging the whole solder structure. The subsequent reflow will generally remove the mushroom shape of the solder cap229if it is present at the subsequent reflow.

The multi-level package substrate310can be a printed circuit board (PCB). The multi-level package substrate310also includes a bottom layer including a bottom metal layer316aincluding metal features having an associated bottom dielectric layer316band vias316v.

FIG.3Bis a cross-sectional view of an example flipchip package350including pillars shown as225a(having an “a” added to the reference number due to their relatively tall height relative to the pillars225described above), on an RDL122on bond pads108of a substrate105having circuitry180, with a solder cap229that has a base portion that is essentially vertical on top of the pillars225a, according to an example aspect. The flipchip package350is shown including a leadframe including leads231shown by example as being a flipchip on lead package. The flipchip package350also includes mold material291covering substrate105, an outer surface of passivation layer112, at least two side surfaces of dielectric layer211, pillars225a, solder caps229and portions of leads231attached to solder caps229. Besides flipchip packages disclosed aspects can also be applied to the flipchip bonding portion for hybrid wirebond/flipchip packages.

Disclosed aspects can be identified by the solder cap structure on the pillar where the base (lower portion) of the solder cap is essentially vertical since the solder cap is formed from a reflow process performed before removal of temperature resistant photoresist or other temperature resistant material that provided a cavity with essentially vertical walls over the pillar for the solder ball placement.

Disclosed aspects can be integrated into a variety of assembly flows to form a variety of different semiconductor packages and related products. The semiconductor package can comprise single IC die or multiple IC die, such as configurations comprising a plurality of stacked IC die, or laterally positioned IC die. A variety of package substrates may be used. The IC die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the IC die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.

Those skilled in the art to which this Disclosure relates will appreciate that many variations of disclosed aspects are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the above-described aspects without departing from the scope of this Disclosure.