Memory cells with ferroelectric capacitors separate from transistor gate stacks

Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

BACKGROUND

Embedded memory is important for future generation microprocessors and system-on-a-chip (SoC) technology. Thin-film ferroelectric (FE) materials pave the way for a promising technology that can enable viable embedded memory solutions.

DETAILED DESCRIPTION

Overview

Described herein are FE memory cells and corresponding methods and devices. FE memory refers to a memory technology employing FE materials. A FE material is a material that exhibits, over some range of temperatures, a spontaneous electric polarization, i.e., displacement of positive and negative charges from their original position, where a given polarization can be reversed or reoriented by application of an electric field. Because the displacement of the charges in FE materials can be maintained for some time even in the absence of an electric field, such materials may be used to implement memory cells. The term “ferroelectric” is said to be adopted to convey the similarity of FE memories to ferromagnetic memories, despite the fact that there is typically no iron (Fe) present in FE materials. Furthermore, as used herein, the term “ferroelectric” is used to describe both materials that exhibit ferroelectric behavior as well as materials that exhibit antiferroelectric behavior (with the relation between ferroelectricity and antiferroelectricity being analogous to the relation between ferromagnetism and antiferromagnetism).

FE memories have the potential for adequate non-volatility, short programming time, low power consumption, high endurance, and high-speed writing. In addition, FE memories have the potential to be manufactured using processes compatible with the standard complementary metal-oxide-semiconductor (CMOS) technology. Therefore, over the last few years, these types of memories have emerged as promising candidates for many growing applications, e.g., digital cameras and contactless smart cards.

Commercial viability of a FE memory cell may depend on the number of factors. One factor is cell's performance characteristics. Another factor is the ability to manufacture dense memory arrays using simple, low-cost process additions.

Some state-of-the-art FE memory cells suffer from endurance issues due to including a FE material in a gate stack of a transistor (referred to, in such a configuration, as a “FE transistor”), where the switching voltage requirement of the FE transistor may degrade the dielectric buffer material also included in the gate stack, impacting the transistor reliability. Other state-of-the-art FE memory cells suffer from endurance issues due to charging at the FE-semiconductor interface that may take place when a FE material is provided directly on top of a semiconductor material. Some state-of-the-art FE memory cells involve complex fabrication sequences, increasing fabrication costs and hindering large-scale adoption of the technology. Improvements on one or more of these challenges would be desirable.

FE memory cells disclosed herein include transistors, e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs), having gate stacks separate from FE capacitors of these cells (i.e., the FE capacitors are not integrated with the transistor gates of the transistors included in the memory cells). An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate), a field-effect transistor (FET) provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode. In some embodiments, the gate stack may include a gate dielectric material provided over at least a portion of a semiconductor material (e.g., the semiconductor material of the support structure, or the semiconductor material provided over the support structure), and a gate electrode material provided over the gate dielectric material. A portion of the semiconductor material over which the gate stack is provided may serve as a channel material (i.e., a material in which, during operation of the transistor, one or more conductive channels may be formed). The term “FE capacitor” arises from the fact that the first and second capacitor electrodes are separated by the FE material. The FE capacitor of such a memory cell may be described as being “separate” from a transistor gate because, unlike memory cell designs where a FE capacitor is integrated with a transistor gate in that a first capacitor electrode is provided over a gate dielectric material and the FE capacitor is provided in place of a typical gate electrode metal of a conventional MOSFET, the FE capacitor of the memory cells described herein is not integrated with the transistor gate and is coupled to the transistor gate by an interconnect structure. The transistor may be used to control both READ and WRITE access to the FE capacitor and may be referred to as an “access transistor.”

Various embodiments of FE memory cells described herein may achieve one or more advantages compared to state-of-the-art FE memory cells. One advantage is that separating the FE material from the gate stack of the access transistor may improve transistor reliability by reducing the impact of the switching voltage for the FE material on the dielectric buffer material of the gate stack. Furthermore, separating the FE material of the FE capacitor from the dielectric buffer material of the gate stack of the access transistor may allow separately controlling the dielectric buffer area and thickness in the transistor and the ferroelectric area and thickness in the FE capacitor structure. The gate voltage may then be divided according to the ratio of these two capacitors, i.e., the dielectric capacitor of the gate stack and the FE capacitor coupled thereto. The capacitance of the gate stack may be sufficiently large so that a large portion of voltage across the gate stack may be used for polarization reversal of the FE capacitance. Thus, separating the FE capacitor from the gate stack may allow increasing the dielectric capacitor (i.e., the capacitance of the gate stack) and reduce the FE capacitor to 1) reduce the FE polarization and depolarization fields, and 2) increase the dielectric capacitor area to maximize the voltage across the FE layer of the FE capacitor. Another advantage is that separating the FE material of the FE capacitor from the semiconductor channel material of the access transistor eliminates the FE-semiconductor interface that may cause endurance issues in some state-of-the-art FE memory cells. Yet other advantages may include the ability to fabricate FE memory cells described herein using relatively simple, low-cost fabrication processes, eliminating the need for a large capacitor and a very-low leakage transistor, and so on. Other technical effects will be evident from various embodiments described here.

In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected or an indirect electrical or magnetic connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The terms “gate stack” and “gate” may be used interchangeably. As used herein, a “logic state” of a FE memory cell refers to one of a finite number of states that the cell can have, e.g., logic states “1” and “0,” each state represented by a different polarization of the FE material of the cell. As used herein, a “READ” and “WRITE” memory access or operations refer to, respectively, determining/sensing a logic state of a memory cell and programming/setting a logic state of a memory cell. In various embodiments, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., while the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art.

The drawings are intended to show relative arrangements of the elements therein, and the device assemblies of these figures may include other elements that are not specifically illustrated (e.g., various interfacial layers). Similarly, although particular arrangements of materials are discussed with reference to the drawings, intermediate materials may be included in the devices and assemblies of these drawings. Still further, although some elements of the various device views are illustrated in the drawings as being planar rectangles or formed of rectangular solids and although some schematic illustrations of example structures are shown with precise right angles and straight lines, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies. Therefore, it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using e.g., Physical Failure Analysis (PFA) would allow determination of presence of one or more memory cells having FE capacitors separate from transistor gates as described herein.

Memory cells having FE capacitors separate from transistor gates as described herein may be implemented in one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

Electric Circuit Diagram of a Unit Memory Cell

FIG.1is an electric circuit diagram of a memory cell (unit cell)100that may be implemented with a FE capacitor being separate from a transistor gate, according to some embodiments of the present disclosure. As shown, the memory cell100may include a transistor110and a FE capacitor120.

The transistor110has a gate terminal, a source terminal, and a drain terminal, indicated in the example ofFIG.1as terminals G, S, and D, respectively. As is commonly known, source and drain terminals may be interchangeable in transistors. Therefore, while the example ofFIG.1illustrates a source terminal on the left side of the drawing and a drain terminal on the right side, in other embodiments, this arrangement may be reversed. Together, source and drain terminals of a transistor may be referred to a “transistor terminal pair,” where the individual ones of these two terminals may be referred to as a “first source or drain (S/D) terminal” and a “second S/D terminal” (e.g., when the first S/D terminal is a source terminal, then the second S/D terminal is a drain terminal, and vice versa).

In various embodiments, the transistor110may be any metal-oxide-semiconductor (MOS) transistors which include drain, source, and gate terminals. Embodiments of the present disclosure are explained below with reference to FET. The transistor110may be either an N-type metal-oxide-semiconductor (NMOS), N-type MOSFET transistor, or a P-type metal-oxide-semiconductor (PMOS), P-type MOSFET transistor. Furthermore, in various embodiments, transistor110can have planar or non-planar architecture, as suitable for a particular implementation. Recently, transistors with non-planar architecture, e.g., double-gate transistors, finFETs, nanoribbon transistors, or nanowire transistors have been extensively explored as promising alternatives to transistors with planar architecture. Therefore, embodiments of the present disclosure are explained below and illustrated with reference, but are not limited, to the transistor110being a finFET. However, these explanations can be easily extended to embodiments of non-planar transistors having architecture other than finFET, e.g., to nanowire or nanoribbon transistors, as well as to embodiments of transistors having planar architecture, all of which embodiments being, therefore, within the scope of the present disclosure.

A finFET refers to a FET having a non-planar architecture where a fin, formed of one or more semiconductor materials, extends away from a base. FinFETs are sometimes interchangeably referred to as “tri-gate transistors,” where the name “tri-gate” originates from the fact that, in use, such a transistor may form conducting channels on three “sides” of the fin. However, in general, a finFET can be such that less than three conducting channels are formed during operation.

In a finFET, sides of a portion of a fin that is closest to a base are enclosed by a dielectric material, typically an oxide, commonly referred to as a “shallow trench isolation” (STI). In a conventional finFET, a gate stack that includes a stack of one or more gate electrode metals and a stack of one or more gate dielectrics is provided over the top and sides of the remaining upper portion of the fin (i.e., the portion that extends above the STI), thus wrapping around the upper portion of the fin and forming a three-sided gate of a finFET. The portion of the fin that is enclosed by the STI is referred to as a “sub-fin” while the portion of the fin over which the gate stack wraps around is referred to as a “channel” or a “channel portion.” A semiconductor material of which the channel portion of the fin is formed is commonly referred to as a “semiconductor channel material” or, simply, a “channel material.” A source region and a drain region are provided on the opposite ends of the fin, on either side of the gate stack, forming, respectively, a source and a drain of such a transistor.

As shown inFIG.1, the FE capacitor120may be coupled to the gate stack of the transistor110. The FE capacitor120includes first and second capacitor electrodes, separated from one another by a FE material. Thus, instead of a regular dielectric material used in conventional dielectric (i.e., not FE) capacitors, the FE capacitor120includes a FE material, separating conductors of the first and second capacitor electrodes. In contrast to some state-of-the-art implementations where the first capacitor electrode could be provided between the one or more gate dielectrics of the gate stack of the transistor110and the FE material, while the FE material is provided between the first and second capacitor electrodes, both electrodes and the FE material of the FE capacitor120is provided separate from the gate stack of the transistor110, e.g., as shown inFIG.2and described in greater detail below. In this manner, the FE capacitor120of the memory cell100is not integrated into a transistor gate of the transistor110, but is separate from the gate. Furthermore, in the memory cell100, the FE material is separated from the semiconductor channel material of the transistor110by at least the bottom capacitor electrode, which may provide an improvement with respect to endurance limitations experienced by some FE memory cells where an FE material is provided directly on the semiconductor channel material.

As shown inFIG.1, in the memory cell100, the first capacitor electrode of the FE capacitor120may be coupled to the gate terminal of the transistor110, while the second capacitor electrode may be coupled to a word-line (WL)150, the first S/D terminal (e.g., a source terminal) of the transistor110may be coupled to a bit-line (BL)140, and the second S/D terminal (e.g., a drain terminal) of the transistor110may be coupled to a select-line (SL)160. As described in greater detail below, together, the WL150, the BL140, and the SL160may be used to read and program the FE capacitor120. Each of the WL150, the BL140, and the SL160may be made of the same or different electrically conductive materials, alloys, or stacks of multiple electrically conductive materials. In some embodiments, various electrically conductive materials that may be used for the WL150, the BL140, and the SL160may include one or more metals or metal alloys, with metals such as copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, various electrically conductive materials that may be used for the WL150, the BL140, and the SL160may include one or more electrically conductive alloys oxides or carbides of one or more metals.

Also shown inFIG.1is the storage node (SN), described in greater detail below, which may also be referred to as a floating node (FN)135, also described in greater detail below, which may include/be the bottom capacitor electrode of the FE capacitor120, and may also be coupled to the gate of the transistor110.

Example Layout of a Unit Memory Cell with a FE Capacitor Separate from a Transistor Gate

FIG.2is a cross-sectional side view (e.g., an y-z plane of a reference coordinate system x-y-z) of an IC device200that illustrates one example layout implementation of the memory cell100ofFIG.1, with the FE capacitor120being separate from a gate stack of the transistor110and being implemented in the back end of line (BEOL), according to some embodiments of the present disclosure. The IC device200illustrates a memory cell implementing one particular example transistor architecture, namely, finFET architecture, but these descriptions may be extended to other transistor architectures for the transistors110of the memory cell100. A number of elements labeled inFIG.1with reference numerals, as well as some further reference numerals of elements are indicated inFIG.2with different patterns in order to not clutter the drawing, with a legend showing the correspondence between the reference numerals and patterns being provided at the bottom ofFIG.2. For example, the legend illustrates thatFIG.2uses different patterns to show the support structure202, the semiconductor material204, the gate electrode material206, etc.

As shown inFIG.2, the IC device200includes a support structure202, on which a semiconductor material204for forming a channel of the transistor110is provided.

Implementations of the present disclosure may be formed or carried out on any suitable support structure202, such as a substrate, a die, a wafer, or a chip. The support structure202may, e.g., be the wafer2000ofFIG.8A, discussed below, and may be, or be included in, a die, e.g., the singulated die2002ofFIG.8B, discussed below. The support structure202may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide, or other combinations of group III-V materials (i.e., materials from groups III and V of the periodic system of elements), group II-VI (i.e., materials from groups II and IV of the periodic system of elements), or group IV materials (i.e., materials from group IV of the periodic system of elements). In some embodiments, the substrate may be non-crystalline. In some embodiments, the support structure202may be a printed circuit board (PCB) substrate. Although a few examples of materials from which the support structure202may be formed are described here, any material that may serve as a foundation upon which an IC device implementing any of the memory cells as described herein may be built falls within the spirit and scope of the present disclosure.

Although shown inFIG.2to be separate from the support structure202, in some embodiments, the semiconductor material204may be a part of the support structure202. In other embodiments, the semiconductor material204may be provided over the support structure202. In some embodiments, the semiconductor material204may be formed as a fin, extending away from the support structure202. The transistor110may be formed on the basis of the semiconductor material204by having a gate stack210wrap around at least a portion of the semiconductor material204referred to as a “channel portion” and by having source and drain regions, shown inFIG.2as a first source or drain (S/D) region214-1and a second S/D region214-2be provided within the semiconductor material204on either side of the gate stack210.

In some embodiments, the channel portion of the semiconductor material204may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the channel portion of the semiconductor material204may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel portion of the semiconductor material204may include a combination of semiconductor materials. In some embodiments, the channel portion of the semiconductor material204may include a monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the channel portion of the semiconductor material204may include a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb).

For some example N-type transistor embodiments (i.e., for the embodiments where the transistor110is an NMOS transistor), the channel portion of the semiconductor material204may advantageously include a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel portion of the semiconductor material204may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). In some embodiments with highest mobility, the channel portion of the semiconductor material204may be an intrinsic III-V material, i.e., a III-V semiconductor material not intentionally doped with any electrically active impurity. In alternate embodiments, a nominal impurity dopant level may be present within the channel portion of the semiconductor material204, for example to further fine-tune a threshold voltage Vt, or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion of the semiconductor material204may be relatively low, for example below 1015dopant atoms per cubic centimeter (cm−3), and advantageously below 1013cm−3.

For some example P-type transistor embodiments (i.e., for the embodiments where the transistor110is a PMOS transistor), the channel portion of the semiconductor material204may advantageously be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel portion of the semiconductor material204may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments with highest mobility, the channel portion of the semiconductor material204may be intrinsic III-V (or IV for P-type devices) material and not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel portion of the semiconductor material204, for example to further set a threshold voltage (Vt), or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion is relatively low, for example below 1015cm−3, and advantageously below 1013cm−3.

The S/D regions214of the transistor110may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the semiconductor material204to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the semiconductor material204may follow the ion implantation process. In the latter process, portions of the semiconductor material204may first be etched to form recesses at the locations of the future S/D regions214. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions214. In some implementations, the S/D regions214may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the S/D regions214may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions214.

Turning to the gate stack210, in some embodiments, the gate stack210may include a gate electrode material206and, optionally, a gate dielectric material208.

The gate electrode material206may include at least one P-type work function metal or N-type work function metal, depending on whether the transistor110is a PMOS transistor or an NMOS transistor (P-type work function metal used as the gate electrode material206when the transistor110is a PMOS transistor and N-type work function metal used as the gate electrode material206when the transistor110is an NMOS transistor). For a PMOS transistor, metals that may be used for the gate electrode material206may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode material206include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material206may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further layers may be included next to the gate electrode material206for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.

In some embodiments, the gate dielectric material208may include one or more high-k dielectric materials. For example, in some embodiments, the gate dielectric material208may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for this purpose may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In other embodiments, the gate dielectric material208may also include one or more low-k dielectric materials. For example, in some embodiments, a thin layer of silicon oxide or silicon oxynitride may be formed below the high-k dielectric of the gate stack. In some embodiments, an annealing process may be carried out on the gate dielectric material208during manufacture of the transistor110to improve the quality of the gate dielectric material208. The gate dielectric material208may have a thickness that may, in some embodiments, be between about 0.5 nanometers and 3 nanometers, including all values and ranges therein (e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers).

In some embodiments, the gate stack210may be surrounded by an insulating material212. The insulating material212may be any suitable dielectric material, e.g., any suitable interlayer dielectric (ILD) material, configured to provide separation between the gate stack210and S/D contacts216of the transistor110. In some embodiments, the insulating material212may include one or more high-k dielectric materials, e.g., any of those described with reference to the materials of the gate dielectric material208. In other embodiments, the insulating material212may include one or more low-k dielectric materials. Some examples of low-k dielectric materials include, but are not limited to, silicon dioxide, carbon-doped oxide, silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fused silica glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The S/D contacts216may include any of the electrically conductive materials described with reference to the WL150, the BL140, and the SL160. In particular, one of the S/D contacts216may be implemented as the BL140and one of the S/D contacts216may be implemented as the SL160. For example, because, as described above, the first S/D region214-1is coupled to the BL140, the S/D contact216shown to the left of the gate stack210of the IC device200may be a part of the BL140. In this case, because the second S/D region214-2is coupled to the SL160, the S/D contact216shown to the right of the gate stack210of the IC device200may be a part of the SL160.

Turning to the FE capacitor120of the IC device200,FIG.2illustrates that, in some embodiments, the memory cell100may be implemented so that the FE capacitor120is provided above the transistor110, e.g., in the BEOL layer220. The FE capacitor120may include a first capacitor electrode222, a second capacitor electrode224, and a capacitor insulator226that includes a FE material between the first capacitor electrode222and the second capacitor electrode224. Each of the first and second capacitor electrodes222,224may include any of the electrically conductive materials described with reference to the WL150, the BL140, and the SL160. The FE material employed in the capacitor insulator226of the FE capacitor120may be one of the novel materials exhibiting ferroelectric or antiferroelectric behavior at thin dimensions, such as hafnium zirconium oxide (HfZrO, also referred to as HZO, which is a material that includes hafnium, zirconium, and oxygen), silicon-doped (Si-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and silicon), germanium-doped (Ge-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and germanium), aluminum-doped (Al-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and aluminum), yttrium-doped (Y-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and yttrium), and a perovskite material (e.g., lead zirconate titanate (PZT), PbTiO3 (PTO), or barium titanate (BTO)). However, in other embodiments, any other materials which exhibit ferroelectric or antiferroelectric behavior at thin dimensions may be used as the capacitor insulator226and are within the scope of the present disclosure.

As shown inFIG.2, the first capacitor electrode222may be coupled to the gate stack210using an interconnect structure228. The interconnect structure228may include any of the electrically conductive materials described with reference to the WL150, the BL140, and the SL160. In some embodiments, the center axis of the interconnect structure228may be substantially aligned with the center axis of the gate stack210, as shown inFIG.2, where the dash-dotted line232illustrates a center axis. The second capacitor electrode224may be coupled to the WL150, as described above (not specifically shown inFIG.2).

In some embodiments, the FE capacitor120and the interconnect structure228may be surrounded by an insulating material230, which may include any of the materials described with reference to the insulating material212. When the FE capacitor120is provided in the BEOL layer220, it may be provided in an opening (e.g., a trench opening) in the insulating material230of the BEOL layer220. The first capacitor electrode222may then be provided as a liner of a first electrically conductive material on sidewalls and a bottom of the opening in the BEOL layer220, and then the capacitor insulator226may be provided as a liner of the FE material on sidewalls and a bottom of the opening lined with the first electrically conductive material that formed the first capacitor electrode222. In some embodiments, the layer of the first capacitor electrode222may have a thickness between about 5 nanometers and 30 nanometers, including all values and ranges therein (e.g., between about 10 and 28 nanometers, or between about 15 and 25 nanometers). In some embodiments, the layer of the capacitor insulator226may have a thickness between about 0.5 nanometers and 20 nanometers, including all values and ranges therein (e.g., between about 1 and 15 nanometers, or between about 0.5 and 5 nanometers). The second capacitor electrode224may be provided as a second electrically conductive material filling at least a portion of the opening lined with the first electrically conductive material and with the FE material, as shown inFIG.2. In such embodiments, the interconnect structure228is also in the BEOL layer220, as shown inFIG.2. In some embodiments, a center axis of the opening for the FE capacitor120may be substantially aligned with the center axis232of the gate stack210and/or with the center axis of the interconnect structure228.

FIG.2illustrates that the FE capacitor120of the IC device200is provided in the BEOL layer220. However, in other embodiments of the IC device200, the FE capacitor120may be provided separate from the gate stack210of the transistor110by being provided in the front-end of line (FEOL) layer, e.g., in an opening (e.g., a trench opening) in the semiconductor material204, in an opening (e.g., a trench opening) in the insulating material212, and/or in an opening (e.g., a trench opening) that extends both through the semiconductor material204and the insulating material212.

Arrays of Unit Cells with FE Capacitors Separate from Transistor Gates

The memory cell100as shown inFIG.1(e.g., the layout of the IC device200shown inFIG.2) is a “unit cell,” where a plurality of such unit cells may be arranged in an array to implement a memory device.FIG.3provides a schematic illustration of a plurality of the memory cells100, namely four cells, arranged in an array300, according to some embodiments of the present disclosure. Each memory cell shown inFIG.3could be any one of the memory cells having a FE capacitor being separate from a transistor gate as described herein, e.g., any of the embodiments of the memory cell100(e.g., any of the embodiments of the implementation shown inFIG.2). Individual memory cells100are illustrated inFIG.3to be within one of the dashed boxes labeled100-11,100-12,100-21, and100-22. While only four memory cells100are shown inFIG.3, in other embodiments, the array300may, and typically would, include many more memory cells. Furthermore, in other embodiments, the memory cells100may be arranged in arrays in a manner other than what is shown inFIG.3, e.g., in any suitable manner of arranging memory cells into arrays as known in the art, all of which being within the scope of the present disclosure.

In some embodiments, each of the BL140, the WL150, and the SL160can be shared among multiple, possibly different subsets of, memory cells100.FIG.3illustrates one such embodiment where, as shown, the BL140can be shared among multiple memory cells100in a column, and each of the WL150and the SL160can be shared among multiple memory cells100in a row. As is conventionally used in context of memory, the terms “row” and “column” do not reflect the, respectively, horizontal and vertical orientation on a page of a drawing illustrating a memory array but, instead, reflect on how individual memory cells are addressed. Namely, memory cells100sharing a single BL are said to be in the same column, while memory cells sharing a single WL are said to be on the same row. Thus, inFIG.3, the horizontal lines refer to columns while vertical lines refer to rows. Different instances of each line (BL, WL, and FL) are indicated inFIG.3with different reference numerals, e.g., BL1and BL2are the two different instances of the BL140as described herein. The same reference numeral on the different lines WL and SL indicates that those lines are used to address/control the memory cells in a single row, e.g., WL1and SL1are used to address/control the memory cells100in row1, and so on. Each memory cell100may then be addressed by using the BL corresponding to the column of the cell and by using the WL and SL corresponding to the row of the cell. For example, as shown inFIG.3, the memory cell100-11is controlled by BL1, WL1, and SL1, the memory cell100-12is controlled by BL1, WL2, and SL2, and so on.

FIG.4is a cross-sectional side view of an example IC device400having two memory cells of the array ofFIG.3, in particular the memory cells100-11and100-21, according to some embodiments of the present disclosure. The IC device400illustrates a view similar to that shown inFIG.2, where the same reference numerals refer to the same or analogous elements/materials. Thus, if the semiconductor material204is shaped as a fin, then the memory cells100-11and100-21are provided along a single fin, as shown inFIG.4.

In the IC device400, the memory cell100-11may be substantially the same as the memory cell shown inFIG.2, while the memory cell100-21may be a mirror image of that memory cell (i.e., for the memory cell100-21, the S/D region214of the transistor110that is coupled to the SL160is to the left of the gate stack210of that transistor, while the S/D region214of the transistor110that is coupled to the BL140is to the right of the gate stack210of that transistor. As shown inFIG.4, in some embodiments, the second S/D region214-2of the transistor110of the memory cell100-11may be shared with the second S/D region214-2of the transistor110of the memory cell100-21, and this shared S/D region214-2may be coupled to a single SL140(the SL1, shown inFIG.4). Thus, the S/D contact216shown inFIG.4to be between the gate stacks210of the memory cells100-11and100-21may be a part of the SL140, e.g., the SL1ofFIG.4. On the other hand, the S/D contact216shown to the left of the gate stack210of the memory cell100-11may be a part of a first BL140, e.g., BL1ofFIG.4, while the S/D contact216shown to the right of the gate stack210of the memory cell100-21may be a part of a second BL140, e.g., BL2ofFIG.4. Although not specifically shown inFIG.5, the second capacitor electrode224of the memory cell100-11may be coupled to the second capacitor electrode224of the memory cell100-21, e.g., by virtue of both of them being coupled to a single WL, e.g., WL1ofFIG.4.

Operating a Memory Cell with a FE Capacitor Being Separate from a Transistor Gate

Next, methods of operating the memory cell100as described herein will be explained, with reference to associated FIGS. In particular,FIGS.5and6illustrate, respectively, a WRITE operation and a READ operation.

FIG.5is a flow diagram of an example method500for operating a memory cell having a FE capacitor being separate from a transistor gate, e.g., the memory cell100, in particular, for programming (i.e., writing to) such a memory cell, in accordance with various embodiments.

At502shown inFIG.5, the WL connected to the memory cell100may be asserted to turn on the transistor110for writing the logic state “1” to the memory cell100. To this end, e.g., the WL150may transition from logic low to logic high to turn on the transistor110, e.g., by applying voltage (e.g., WL=Vdd) sufficient to turn on the transistor110, e.g., 1.0 Volts (V). For writing the logic state “0” to the memory cell, the transistor110is not turned on (i.e., WL=0 Volts (V)) and502is omitted from the method500.

At504shown inFIG.5, the BL140connected to the memory cell100is asserted to charge or discharge the FN135, while the SL160is connected to Vss or 0V, to set the desired polarization state of the FE material of the capacitor insulator226in the memory cell100in order to set a desired logic state. For a WRITE operation, an electric field is applied across the FE material of the capacitor insulator226in order to polarize the FE material in a direction corresponding to the desired logic state. Such an electric field may be applied by changing the voltage on the BL and/or on the SL coupled to the memory cell100(while WL coupled to the memory cell100is asserted). In some embodiments, to program a logic state “1,” WL=Vdd, BL=0V, and SL=0V, while to program a logic state “0,” WL=0, BL=Vdd, and SL=0V or Vdd, the later may enable a stronger WRITE. More specifically, in order to ensure that the polarization of the FE material in the capacitor120is set to the desired state, an electric field of suitable magnitude and direction may be applied across the FE material of the capacitor insulator226, which is done by applying voltage of sufficiently high magnitude and a predefined polarity at the BL140at504, for a time period that is equal to or greater than a minimum transition duration (e.g., about 1 to 100 nanoseconds (ns)). The term “minimum transition duration” here generally refers to a suitable duration of time during which a voltage (e.g., due to the voltages on the BL and WL, possibly in combination with the charge on the FN135) is applied to the FE material of the capacitor insulator226to cause the FE material to be polarized and to store a polarization charge according to the applied voltage. The minimum transition duration may be a predetermined value depending on the materials used in the FE material stack of the capacitor insulator226and their thicknesses. Some embodiments described herein may use the minimum transition duration of 100 ns, however, this parameter should not be understood to be limiting as the minimum transition duration could be designed to be substantially shorter or longer based upon application-specific requirements. In general, longer minimum transition times can enable lower voltage operation, higher read signals, longer FE retention.

At506, if the WL150was switched on at502(i.e., if logic state “1” was written), the WL150may be switched off, i.e., de-asserted. In some embodiments of506, the SL160may be switched off as well.

FIG.6is a flow diagram of an example method600for reading a memory cell having a FE capacitor being separate from a transistor gate, e.g., the memory cell100. The method600may be preceded by the method500, where, as a result of performing the method500, the BL140connected to the memory cell100may be pre-charged to Vdd to set the FE capacitor120to the desired logic state represented by the polarization state set in the FE material of the capacitor insulator226.

The method600may begin with602, where the WL150connected to the memory cell100is asserted (e.g., the WL150transitions from logic low to logic high to turn on the transistor110), e.g., by applying voltage sufficient to turn on the transistor110, e.g., 1.0 Volts (V). Once the transistor110is switched on, current can flow through it, between the first S/D region214-1and the second S/D region214-2. Because the FE capacitor120is connected in series with the gate of the transistor110, the current flowing between the first S/D region214-1and the second S/D region214-2is modulated (i.e., affected/changed) by the polarization state of the FE material of the capacitor insulator226in the FE capacitor120. As described above, the first S/D region214-1of the transistor110is coupled to the BL140, and the second S/D region214-2of the transistor110is coupled to the SL160. At604shown inFIG.6, a sense amplifier coupled to the BL140senses the current or voltage on the BL140to determine change in current/voltage as a result of the polarization state of the FE capacitor120affecting the drain current of the transistor110(e.g., if the BL140discharges, the bit was “1,” if it does not discharge, then the bit can be assumed to be “0”).

Referring, again, to the example memory array300shown inFIG.3, during a READ operation of a given memory cell, e.g., according to the method shown inFIG.6, for unselected words in the array, the WL remains de-asserted (e.g., the WL remains or is transitioned from logic HIGH to logic LOW, e.g., 0V) and the transistors of the array having gate terminals coupled to such WL remain turned off. This will enable clear sensing of the selected memory cell by reducing the current through the unselected memory cells which may be connected to the same BL. For example, during the READ of the memory cell100-11shown inFIG.3, WL1is asserted so that the transistor110of the memory cell100-11turns on and a sense amplifier senses current or voltage on the BL1to determine the logic state of the memory cell100-11. The memory cell100-12is connected to the same bit-line BL1and, therefore, could, in principle, affect the current or voltage on BL1. However, because WL2is de-asserted when WL1is asserted to READ the memory cell100-11, the transistor of the memory cell100-12is off and there is no current flowing through the transistor110of the memory cell100-12and affecting the reading of the memory cell100-11. As a result of asserting WL1, the transistor110of the memory cell100-21also turns on, but since reading of the memory cell100-11is performed with a sense amplifier senses current or voltage on the BL1, change in voltage/current on BL2has no effect on reading the logic state of the memory cell100-11.

Fabricating a Memory Cell with a FE Capacitor Being Separate from a Transistor Gate

Various embodiments of the memory cells100disclosed herein may be manufactured using any suitable techniques. For example,FIG.7is a flow diagram of an example method700of manufacturing a memory cell with a FE capacitor being separate from a transistor gate, in accordance with various embodiments.

Although the operations of the method700are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel, e.g., to manufacture multiple memory cells substantially simultaneously, or/and to manufacture the transistors and the FE capacitors of the memory cells substantially simultaneously. In another example, the operations may be performed in a different order to reflect the structure of a memory device in which the memory cell will be included. In yet another example, some operations may be combined into a single operation, and some operations may be subdivided into more operations than what is shown inFIG.7.

At702, a transistor may be provided over a support structure, the transistor including a semiconductor channel material, S/D regions, S/D contacts, and a gate stack. The transistor provided at702may take any embodiments of the transistor110, described herein, and may be manufactured using any known processes for fabricating transistors.

At704, a metal interconnect may be provided, the metal interconnect electrically connected to the gate stack of the transistor provided at702. The metal interconnect provided at704may take any embodiments of the metal interconnect228, described herein, and may be manufactured using any known processes for fabricating metal interconnects.

At706, a FE capacitor may be provided, the FE capacitor having one of its capacitor electrodes electrically connected to the metal interconnect provided at704. The FE capacitor provided at706may take any embodiments of the FE capacitor120, described herein. The order of704and706shown inFIG.7may be particularly useful if the FE capacitor120is implemented in the BEOL220, i.e., where the metal interconnect228is provided first, and then the FE capacitor120is provided above the metal interconnect228. In other embodiments, the order of704and706may be different. For example, if the FE capacitor120is provided in the FEOL (as described above for the further embodiments of the IC device200), then the FE capacitor may be provided first, and then the metal interconnect228may be provided to couple the first capacitor electrode222of the FE capacitor120to the gate stack210of the transistor110provided at702.

In some embodiments, the FE capacitor may be manufactured at706as follows. First, an opening may be formed (e.g., an opening in the insulating material230, the insulating material212, or the semiconductor material204, depending on where the FE capacitor120is being placed). The opening may be formed using, e.g., any suitable etching techniques, possibly in combination with any suitable patterning technique such as photolithographic patterning, e-beam patterning, etc. Then the electrically conductive material of the first capacitor electrode222may be deposited to line sidewalls and a bottom of the opening. In some embodiments, the electrically conductive material of the first capacitor electrode222may be deposited using any suitable conformal deposition process, e.g., atomic layer deposition (ALD) or chemical vapor deposition (CVD), so that all exposed surfaces of the opening could be covered with the electrically conductive material of the first capacitor electrode222. Next, the capacitor insulator226may be deposited into the opening lined with the electrically conductive material of the first capacitor electrode222, e.g., using any suitable conformal deposition process, e.g., ALD or CVD. Finally, the electrically conductive material of the second capacitor electrode224may be deposited to at least partially fill the remaining space in the opening lined with the electrically conductive material of the first capacitor electrode222and with the capacitor insulator226. In some embodiments, the electrically conductive material of the second capacitor electrode224may be deposited using any suitable deposition process (which may, but does not have to be a conformal deposition process), such as ALD, CVD, plasma-enhanced CVD (PECVD), or physical vapor deposition (PVD).

Although not specifically shown inFIG.7, the method700may further include processes for coupling the memory cell100to READ and/or WRITE control lines. Such coupling may take the form of any of the embodiments of the transistor110and the FE capacitor120coupled to the WL, SL, and BL disclosed herein (e.g., any of the embodiments discussed herein with reference to the coupling as shown in the present drawings).

In various embodiments, the manufacturing method700may include other operations, not specifically shown inFIG.7.

For example, in some embodiments, the IC device200or the memory cell100may be cleaned prior to or/and after any of the processes of the method700described herein, e.g., to remove surface-bound organic and metallic contaminants, as well as subsurface contamination, to promote adhesion, and/or to decrease interdiffusion of materials. In some embodiments, cleaning may be carried out using e.g., a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g., using hydrofluoric acid (HF)). In some embodiments, cleaning may be carried out using chemical or plasma clean, or applying heat in a controlled environment.

In another example, the method700may include operations that include depositing sacrificial materials and providing openings in the sacrificial materials. A sacrificial material may include any material that has sufficient etch selectivity with respect to the surrounding materials so that, after the sacrificial material is deposited, a portion of the sacrificial material can be removed without substantially removing the surrounding materials. As known in the art, two materials are said to have “sufficient etch selectivity” when etchants used to etch one material do not substantially etch the other, enabling selective etching of one material but not the other. In some embodiments, a sacrificial material may be a sacrificial dielectric material. Some examples of such materials include silicon oxide (i.e., a compound comprising silicon and oxygen, e.g., SiO2), hafnium oxide (i.e., a compound comprising hafnium and oxygen e.g., HfO2), silicon nitride (i.e., a compound comprising silicon and nitrogen, e.g., SiN), silicon oxynitride (i.e., a compound comprising silicon, oxygen, and nitrogen, e.g., SiON), aluminum oxide (i.e., a compound comprising aluminum and oxygen, e.g., Al2O3), aluminum hafnium oxide (i.e., a compound comprising aluminum, hafnium, and oxygen, e.g., AlHfO), carbon-doped oxide (i.e., a compound comprising carbon and oxygen), organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, FSG, and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. Besides appropriate etching characteristics, some other considerations in selecting a suitable sacrificial material may include e.g., possibilities of smooth film formation, low shrinkage and outgassing, and good dielectric properties (such as low electrical leakage, suitable value of a dielectric constant, and thermal stability). Any suitable deposition techniques may be used to provide the sacrificial material, such as spin-coating, dip-coating, ALD, CVD, PECVD, and thermal oxidation.

In yet another example, the method700may include any suitable planarization/polishing techniques to remove excess or overburden of materials deposited in a given process. Planarization may be performed using either wet or dry planarization processes. In one embodiment, planarization may be performed using chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden of the desired material.

Example Devices and Components

Memory cells and arrays with FE capacitors separate from transistor gates as disclosed herein may be included in any suitable electronic device.FIGS.8-14illustrate various examples of devices and components that may include one or more memory cells having FE capacitors separate from transistor gate stacks as disclosed herein.

FIGS.8A-8Bare top views of a wafer2000and dies2002that may include one or more memory cells having FE capacitors separate from transistor gates in accordance with any of the embodiments disclosed herein. In some embodiments, the dies2002may be included in an IC package, in accordance with any of the embodiments disclosed herein. For example, any of the dies2002may serve as any of the dies2256in an IC package2200shown inFIG.10. The wafer2000may be composed of semiconductor material and may include one or more dies2002having IC structures formed on a surface of the wafer2000. Each of the dies2002may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more memory cells having FE capacitors separate from transistor gates as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more memory cells having FE capacitors separate from transistor gates as described herein), the wafer2000may undergo a singulation process in which each of the dies2002is separated from one another to provide discrete “chips” of the semiconductor product. In particular, devices that include one or more memory cells having FE capacitors separate from transistor gates as disclosed herein may take the form of the wafer2000(e.g., not singulated) or the form of the die2002(e.g., singulated). The die2002may include one or more transistors (e.g., one or more transistors110and/or one or more of conventional logic transistors, discussed below), one or more FE capacitors (e.g., one or more FE capacitors120), and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer2000or the die2002may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. In some embodiments, the wafer2000or the die2002may include a memory device with a plurality of memory cells having FE capacitors separate from transistor gates, as described herein. Multiple ones of these devices may be combined on a single die2002. For example, a memory array formed by multiple memory devices, e.g., formed by multiple memory cells having FE capacitors separate from transistor gates as described herein, may be formed on a same die2002as a processing device (e.g., the processing device2402ofFIG.12) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG.9is a cross-sectional side view of an IC device2100that may include one or more memory cells having FE capacitors separate from transistor gates in accordance with any of the embodiments disclosed herein. In some embodiments, the IC device2100may serve as any of the dies2256in the IC package2300shown inFIG.11.

As shown inFIG.9, the IC device2100may be formed on a substrate2102(e.g., the wafer2000ofFIG.8A) and may be included in a die (e.g., the die2002ofFIG.8B). The substrate2102may include any material that may serve as a foundation/support structure for an IC device2100. The substrate2102may be a semiconductor substrate, and may be implemented as any of the examples provided above with reference to the support structure202of the IC device200. Although a few examples of the substrate2102are described here, any material or structure that may serve as a foundation upon which an IC device2100may be built falls within the spirit and scope of the present disclosure. The substrate2102may be part of a singulated die (e.g., the die2002ofFIG.8B) or a wafer (e.g., the wafer2000ofFIG.8A).

The IC device2100may include one or more device layers2104disposed on the substrate2102. The device layer2104may include features of one or more transistors2140(e.g., MOSFETs) formed on the substrate2102. The device layer2104may include, for example, one or more S/D regions2120, a gate2122to control current flow in the transistors2140between the S/D regions2120, and one or more S/D contacts2124to route electrical signals to/from the S/D regions2120. The transistors2140may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like.

Each transistor2140may include a gate2122that includes a gate electrode layer and, in some embodiments, may further include an optional gate dielectric layer. Generally, the gate dielectric layer of a transistor2140may include one layer or a stack of layers, and may include any of the materials described above with reference to the gate dielectric322. In some embodiments, an annealing process may be carried out on the gate dielectric of the gate2122to improve its quality when a high-k material is used.

The gate electrode may be formed on the gate dielectric and may include at least one P-type work function metal or N-type work function metal, depending on whether the transistor2140is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. The gate electrode of the gate2122may include any of the materials described above with reference to the gate electrode material206.

In some embodiments, when viewed as a cross-section of the transistor2140along the source-channel-drain direction, the gate electrode of the gate2122may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may include a V-shaped structure (e.g., when the fin of a finFET does not have a “flat” upper surface, but instead has a rounded peak).

The S/D regions2120may be formed within the substrate2102, e.g., adjacent to the gate of each transistor2140. The S/D regions2120may be formed using an implantation/diffusion process or an etching/deposition process, for example any of the processes described with reference to the S/D regions214.

Various transistors2140are not limited to the type and configuration depicted inFIG.9and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Any of the transistors2140may be implemented as, or replaced with, the transistors110of the memory cells100, described herein.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors2140of the device layer2104through one or more interconnect layers disposed on the device layer2104(illustrated inFIG.9as interconnect layers2106-2110). For example, electrically conductive features of the device layer2104(e.g., the gate2122and the S/D contacts2124) may be electrically coupled with the interconnect structures2128of the interconnect layers2106-2110. The one or more interconnect layers2106-2110may form an ILD stack2119of the IC device2100.

The interconnect structures2128may be arranged within the interconnect layers2106-1210to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures2128depicted inFIG.9). Although a particular number of interconnect layers2106-1210is depicted inFIG.9, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures2128may include trench structures2128a(sometimes referred to as “lines”) and/or via structures2128b(sometimes referred to as “holes”) filled with an electrically conductive material such as a metal. The trench structures2128amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate2102upon which the device layer2104is formed. For example, the trench structures2128amay route electrical signals in a direction in and out of the page from the perspective ofFIG.9. The via structures2128bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate2102upon which the device layer2104is formed. In some embodiments, the via structures2128bmay electrically couple trench structures2128aof different interconnect layers2106-2110together.

The interconnect layers2106-2110may include a dielectric material2126disposed between the interconnect structures2128, as shown inFIG.9. In some embodiments, the dielectric material2126disposed between the interconnect structures2128in different ones of the interconnect layers2106-2110may have different compositions; in other embodiments, the composition of the dielectric material2126between different interconnect layers2106-2110may be the same.

A first interconnect layer2106(referred to as Metal 1 or “M1”) may be formed directly on the device layer2104. In some embodiments, the first interconnect layer2106may include trench structures2128aand/or via structures2128b, as shown. The trench structures2128aof the first interconnect layer2106may be coupled with contacts (e.g., the S/D contacts2124) of the device layer2104.

A second interconnect layer2108(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer2106. In some embodiments, the second interconnect layer2108may include via structures2128bto couple the trench structures2128aof the second interconnect layer2108with the trench structures2128aof the first interconnect layer2106. Although the trench structures2128aand the via structures2128bare structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer2108) for the sake of clarity, the trench structures2128aand the via structures2128bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

A third interconnect layer2110(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer2108according to similar techniques and configurations described in connection with the second interconnect layer2108or the first interconnect layer2106.

The IC device2100may include a solder resist material2134(e.g., polyimide or similar material) and one or more bond pads2136formed on the interconnect layers2106-2110. The bond pads2136may be electrically coupled with the interconnect structures2128and configured to route the electrical signals of the transistor(s)2140to other external devices. For example, solder bonds may be formed on the one or more bond pads2136to mechanically and/or electrically couple a chip including the IC device2100with another component (e.g., a circuit board). The IC device2100may have other alternative configurations to route the electrical signals from the interconnect layers2106-2110than depicted in other embodiments. For example, the bond pads2136may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

FIG.10is a side, cross-sectional view of an example IC package2200that may include one or more memory cells having FE capacitors separate from transistor gates in accordance with any of the embodiments disclosed herein. In some embodiments, the IC package2200may be a system-in-package (SiP).

The package substrate2252may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, etc.), and may have conductive pathways extending through the dielectric material between the face2272and the face2274, or between different locations on the face2272, and/or between different locations on the face2274. These conductive pathways may take the form of any of the interconnect structures2128discussed above with reference toFIG.9.

The package substrate2252may include conductive contacts2263that are coupled to conductive pathways2262through the package substrate2252, allowing circuitry within the dies2256and/or the interposer2257to electrically couple to various ones of the conductive contacts2264(or to other devices included in the package substrate2252, not shown).

The IC package2200may include an interposer2257coupled to the package substrate2252via conductive contacts2261of the interposer2257, first-level interconnects2265, and the conductive contacts2263of the package substrate2252. The first-level interconnects2265illustrated inFIG.10are solder bumps, but any suitable first-level interconnects2265may be used. In some embodiments, no interposer2257may be included in the IC package2200; instead, the dies2256may be coupled directly to the conductive contacts2263at the face2272by first-level interconnects2265.

The IC package2200may include one or more dies2256coupled to the interposer2257via conductive contacts2254of the dies2256, first-level interconnects2258, and conductive contacts2260of the interposer2257. The conductive contacts2260may be coupled to conductive pathways (not shown) through the interposer2257, allowing circuitry within the dies2256to electrically couple to various ones of the conductive contacts2261(or to other devices included in the interposer2257, not shown). The first-level interconnects2258illustrated inFIG.10are solder bumps, but any suitable first-level interconnects2258may be used. As used herein, a “conductive contact” may refer to a portion of electrically conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

In some embodiments, an underfill material2266may be disposed between the package substrate2252and the interposer2257around the first-level interconnects2265, and a mold compound2268may be disposed around the dies2256and the interposer2257and in contact with the package substrate2252. In some embodiments, the underfill material2266may be the same as the mold compound2268. Example materials that may be used for the underfill material2266and the mold compound2268are epoxy mold materials, as suitable. Second-level interconnects2270may be coupled to the conductive contacts2264. The second-level interconnects2270illustrated inFIG.10are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects22770may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects2270may be used to couple the IC package2200to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference toFIG.11.

The dies2256may take the form of any of the embodiments of the die2002discussed herein (e.g., may include any of the embodiments of the IC device2100). In embodiments in which the IC package2200includes multiple dies2256, the IC package2200may be referred to as a multi-chip package (MCP). The dies2256may include circuitry to perform any desired functionality. For example, one or more of the dies2256may be logic dies (e.g., silicon-based dies), and one or more of the dies2256may be memory dies (e.g., high bandwidth memory, and/or dies implementing one or more memory cells having FE capacitors separate from transistor gates). In some embodiments, any of the dies2256may include one or more memory cells having FE capacitors separate from transistor gates, e.g., as discussed above with reference toFIG.9; in some embodiments, at least some of the dies2256may not include any memory cells having FE capacitors separate from transistor gates.

The IC package2200illustrated inFIG.10may be a flip chip package, although other package architectures may be used. For example, the IC package2200may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package2200may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies2256are illustrated in the IC package2200ofFIG.10, an IC package2200may include any desired number of the dies2256. An IC package2200may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face2272or the second face2274of the package substrate2252, or on either face of the interposer2257. More generally, an IC package2200may include any other active or passive components known in the art.

FIG.11is a cross-sectional side view of an IC device assembly2300that may include components having one or more memory cells having FE capacitors separate from transistor gates in accordance with any of the embodiments disclosed herein. The IC device assembly2300includes a number of components disposed on a circuit board2302(which may be, e.g., a motherboard). The IC device assembly2300includes components disposed on a first face2340of the circuit board2302and an opposing second face2342of the circuit board2302; generally, components may be disposed on one or both faces2340and2342. In particular, any suitable ones of the components of the IC device assembly2300may include any of one or more memory cells having FE capacitors separate from transistor gates in accordance with any of the embodiments disclosed herein; e.g., any of the IC packages discussed below with reference to the IC device assembly2300may take the form of any of the embodiments of the IC package2200discussed above with reference toFIG.10(e.g., may include one or more memory cells having FE capacitors separate from transistor gates on/over/in a die2256).

The IC device assembly2300illustrated inFIG.11includes a package-on-interposer structure2336coupled to the first face2340of the circuit board2302by coupling components2316. The coupling components2316may electrically and mechanically couple the package-on-interposer structure2336to the circuit board2302, and may include solder balls (e.g., as shown inFIG.11), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure2336may include an IC package2320coupled to an interposer2304by coupling components2318. The coupling components2318may take any suitable form for the application, such as the forms discussed above with reference to the coupling components2316. The IC package2320may be or include, for example, a die (the die2002ofFIG.8B), an IC device (e.g., the IC device2100ofFIG.9), or any other suitable component. In particular, the IC package2320may include one or more memory cells having FE capacitors separate from transistor gates as described herein. Although a single IC package2320is shown inFIG.11, multiple IC packages may be coupled to the interposer2304; indeed, additional interposers may be coupled to the interposer2304. The interposer2304may provide an intervening substrate used to bridge the circuit board2302and the IC package2320. Generally, the interposer2304may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer2304may couple the IC package2320(e.g., a die) to a BGA of the coupling components2316for coupling to the circuit board2302. In the embodiment illustrated inFIG.11, the IC package2320and the circuit board2302are attached to opposing sides of the interposer2304; in other embodiments, the IC package2320and the circuit board2302may be attached to a same side of the interposer2304. In some embodiments, three or more components may be interconnected by way of the interposer2304.

The interposer2304may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer2304may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer2304may include metal interconnects2308and vias2310, including but not limited to through-silicon vias (TSVs)2306. The interposer2304may further include embedded devices2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. In particular, one or more thermal contacts as described herein may be thermally coupled to at least some of the embedded devices2314. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer2304. The package-on-interposer structure2336may take the form of any of the package-on-interposer structures known in the art. In some embodiments, the interposer2304may include one or more thermal contacts as described herein.

The IC device assembly2300may include an IC package2324coupled to the first face2340of the circuit board2302by coupling components2322. The coupling components2322may take the form of any of the embodiments discussed above with reference to the coupling components2316, and the IC package2324may take the form of any of the embodiments discussed above with reference to the IC package2320.

The IC device assembly2300illustrated inFIG.11includes a package-on-package structure2334coupled to the second face2342of the circuit board2302by coupling components2328. The package-on-package structure2334may include an IC package2326and an IC package2332coupled together by coupling components2330such that the IC package2326is disposed between the circuit board2302and the IC package2332. The coupling components2328and2330may take the form of any of the embodiments of the coupling components2316discussed above, and the IC packages2326and2332may take the form of any of the embodiments of the IC package2320discussed above. The package-on-package structure2334may be configured in accordance with any of the package-on-package structures known in the art.

FIG.12is a block diagram of an example computing device2400that may include one or more components with one or more memory cells having FE capacitors separate from transistor gates in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device2400may include a die (e.g., the die2002(FIG.8B)) including one or more memory cells having FE capacitors separate from transistor gates in accordance with any of the embodiments disclosed herein. Any of the components of the computing device2400may include an IC device2100(FIG.9) and/or an IC package2200(FIG.10). Any of the components of the computing device2400may include an IC device assembly2300(FIG.11).

A number of components are illustrated inFIG.12as included in the computing device2400, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device2400may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single SoC die.

Additionally, in various embodiments, the computing device2400may not include one or more of the components illustrated inFIG.12, but the computing device2400may include interface circuitry for coupling to the one or more components. For example, the computing device2400may not include a display device2406, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device2406may be coupled. In another set of examples, the computing device2400may not include an audio input device2418or an audio output device2408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device2418or audio output device2408may be coupled.

The computing device2400may include a processing device2402(e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device2402may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device2400may include a memory2404, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory2404may include memory that shares a die with the processing device2402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM). In various embodiments, any one of the processing device2402and the memory2404may include one or more memory cells having FE capacitors separate from transistor gates as described herein.

In some embodiments, the communication chip2412may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip2412may include multiple communication chips. For instance, a first communication chip2412may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip2412may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip2412may be dedicated to wireless communications, and a second communication chip2412may be dedicated to wired communications.

The computing device2400may include battery/power circuitry2414. The battery/power circuitry2414may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device2400to an energy source separate from the computing device2400(e.g., AC line power).

The computing device2400may include a display device2406(or corresponding interface circuitry, as discussed above). The display device2406may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device2400may include an audio output device2408(or corresponding interface circuitry, as discussed above). The audio output device2408may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device2400may include an audio input device2418(or corresponding interface circuitry, as discussed above). The audio input device2418may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device2400may include a GPS device2416(or corresponding interface circuitry, as discussed above). The GPS device2416may be in communication with a satellite-based system and may receive a location of the computing device2400, as known in the art.

The computing device2400may include an other output device2410(or corresponding interface circuitry, as discussed above). Examples of the other output device2410may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

Select Examples

Example 1 provides an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure, the transistor comprising a gate stack. The IC device also includes a FE capacitor, including a first capacitor electrode, a second capacitor electrode, and a capacitor insulator that includes a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack) and an interconnect structure is configured to electrically couple the gate stack and the first capacitor electrode.

Example 2 provides the IC device according to example 1, where the IC device further includes a BEOL layer over the gate stack, the first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the BEOL layer, the capacitor insulator is a liner of the FE material on sidewalls and a bottom of the opening lined with the first electrically conductive material, the second capacitor electrode is a second electrically conductive material filling at least a portion of the opening lined with the first electrically conductive material and with the FE material, and the interconnect structure is in the BEOL layer.

Example 3 provides the IC device according to example 2, where a center axis of the opening in the BEOL layer is substantially aligned with a center axis of the gate stack.

Example 4 provides the IC device according to examples 2 or 3, where a center axis of the opening is substantially aligned with a center axis of the interconnect structure.

Example 5 provides the IC device according to example 4, where the interconnect structure is a via filled or lined with one or more electrically conductive materials.

Example 6 provides the IC device according to any one of examples 2-5, where the transistor is a first transistor, and the IC device further includes a second transistor provided over the support structure, the second transistor including a gate stack, the BEOL is over the gate stack of the second transistor, the FE capacitor is a first capacitor, and the IC device further includes a second FE capacitor, the interconnect structure is a first interconnect structure, and the IC device further includes a second interconnect structure, configured to electrically connect the gate stack of the second transistor and a first capacitor electrode of the second capacitor.

Example 7 provides the IC device according to example 6, where a source or drain (S/D) terminal of the first transistor is coupled to a S/D terminal of the second transistor.

Example 8 provides the IC device according to any one of the preceding examples, where the gate stack includes a gate electrode material, and the interconnect structure is configured to electrically connect the gate electrode material and the first capacitor electrode.

Example 9 provides the IC device according to any one of the preceding examples, where the second capacitor electrode of the FE capacitor is coupled to a WL.

Example 10 provides the IC device according to any one of the preceding examples, where the transistor includes a first source/drain (S/D) terminal coupled to a BL, and a second S/D terminal coupled to a SL. In some examples, the first S/D terminal (i.e., the terminal coupled to the BL) is a source terminal, while the second S/D terminal (i.e., the terminal coupled to the SL) is a drain terminal.

Example 11 provides the IC device according to any one of the preceding examples, where the transistor includes a semiconductor material shaped as a fin extending away from a base (i.e., the transistor is a fin-FET).

Example 12 provides the IC device according to any one of the preceding examples, where the FE material includes one or more of a material including hafnium, zirconium, and oxygen (e.g., hafnium zirconium oxide), a material including silicon, hafnium, and oxygen (e.g., silicon-doped hafnium oxide), a material including germanium, hafnium, and oxygen (e.g., germanium-doped hafnium oxide), a material including aluminum, hafnium, and oxygen (e.g., aluminum-doped hafnium oxide), a material including yttrium, hafnium, and oxygen (e.g., yttrium-doped hafnium oxide), and a perovskite material (e.g., lead zirconate titanate (PZT), PbTiO3 (PTO), or barium titanate (BTO)).

Example 13 provides the IC device according to any one of the preceding examples, where the FE material is a thin-film FE material.

Example 15 provides the IC package according to example 14, where the further component is one of a package substrate, a flexible substrate, or an interposer.

Example 16 provides the IC package according to examples 14 or 15, where the further component is coupled to the IC die via one or more first-level interconnects.

Example 17 provides the IC package according to example 16, where the one or more first-level interconnects include one or more solder bumps, solder posts, or bond wires.

Example 18 provides a method for fabricating an IC device, the method including providing a FET provided over a support structure (e.g., a substrate), the transistor including a gate stack; providing a BEOL layer over the gate stack; providing a ferroelectric (FE) capacitor, including a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first capacitor electrode and the second capacitor electrode, where the first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the BEOL layer, the capacitor insulator is a liner of a FE material on sidewalls and a bottom of the opening lined with the first electrically conductive material, and the second capacitor electrode is a second electrically conductive material filling at least a portion of the opening lined with the first electrically conductive material and with the FE material; and providing an interconnect structure in the BEOL layer, configured to electrically connect the gate stack and the first capacitor electrode.

Example 19 provides the method according to example 18, where providing the interconnect structure includes forming a via opening in the BEOL layer, the via opening exposing a gate electrode material of the gate stack, and filling or lining the via opening with one or more electrically conductive materials.

Example 20 provides the method according to example 19, where providing the FE capacitor includes forming the opening in the BEOL layer, the opening exposing the one or more electrically conductive materials filling or lining the via opening, depositing the liner of the first electrically conductive material on the sidewalls and the bottom of the opening, depositing the liner of the FE material on the sidewalls and the bottom of the opening lined with the first electrically conductive material, and filling or lining the opening lined with the first electrically conductive material and with the FE material with the second electrically conductive material.