Liquid crystal display device and fabricating method thereof

A thin film transistor substrate of a LCD device and a fabricating method thereof are disclosed for simplifying a fabricating process and enlarging a capacitance value of a storage capacitor without any reduction of aperture ratio. The LCD device includes: a double-layered gate line having a first transparent conductive layer and a second opaque conductive layer, the second opaque conductive layer have a step coverage; a gate insulation layer film on the gate line; a data line crossing the gate line to define a pixel region; a TFT connected to the gate line and the data line; a pixel electrode connected to the TFT via a contact hole of a protective film on the TFT; and a storage capacitor overlapping the pixel electrode and having a lower storage electrode formed of the first transparent conductive layer.

This application claims the benefit of Korean Patent Application No. P2004-37770 filed in Korea on May. 27, 2004, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a thin film transistor substrate applied to a display device, and more particularly to a thin film transistor substrate and a fabricating method thereof that are adaptive for simplifying a process.

2. Discussion of the Related Art

Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal using an electric field to thereby display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

The liquid crystal display panel includes a thin film transistor substrate and a color filter substrate opposed to each other, a liquid crystal injected between two substrates, and a spacer maintaining cell gap between the two substrates.

The thin film transistor substrate includes gate lines, data lines, thin film transistors formed as switching devices for each crossing between the gate lines and the data lines, pixel electrodes formed for each liquid crystal cell and connected to the thin film transistor, and alignment films formed thereon. The gate lines and the data lines receive signals from the driving circuits via each pad portion. The thin film transistor applies a pixel signal fed to the data line to the pixel electrode in response to a scanning signal fed to the gate line.

The color filter substrate includes color filters formed for each liquid crystal cell, black matrices for dividing color filters and reflecting an external light, common electrodes for commonly applying reference voltages to the liquid crystal cells, and an alignment film formed thereon.

The liquid crystal display panel is completed by preparing the thin film array substrate and the color filter substrate individually to join them and then injecting a liquid crystal between them and sealing it.

In such a liquid crystal display device, the thin film transistor substrate has a complicated fabrication process that leads to a major rise in a manufacturing cost of the liquid crystal display panel because it involves a semiconductor process and needs a plurality of mask processes. In order to solve this, the thin film transistor substrate has been developed toward a reduction in the number of mask processes. This is because one mask process includes processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes, etc. Recently, there has been highlighted a four-mask process excluding one mask process from the existent five-round mask process that was a standard mask process of the thin film transistor.

FIG. 1is a plan view illustrating a thin film transistor substrate using a four-mask process, andFIG. 2is a section view of the thin film transistor substrate taken along the I-I′ line inFIG. 1.

InFIG. 1andFIG. 2, the thin film transistor substrate includes a gate line2and a data line4provided on a lower substrate42in such a manner to cross each other while with having a gate insulating film44therebetween, a thin film transistor6provided at each crossing, and a pixel electrode18provided at a cell area having the crossing structure. Further, the thin film transistor substrate includes a storage capacitor20provided at an overlapped portion between the pixel electrode18and a previous gate line2, a gate pad26connected to the gate line2, and a data pad34connected to the data line4.

The thin film transistor6allows a pixel signal applied to the data line4to be charged into the pixel electrode18and kept in response to a scanning signal applied to the gate line2. To this end, the thin film transistor6includes a gate electrode8connected to the gate line2, a source electrode10connected to the data line4, a drain electrode12connected to the pixel electrode18, and an active layer14overlapping with the gate electrode8and defining a channel between the source electrode10and the drain electrode12.

The active layer14overlapping with the source electrode10and the drain electrode12and having a channel portion between the source electrode10and the drain electrode12also overlaps with the data line4, a lower data pad electrode36and a storage electrode22. On the active layer14, an ohmic contact layer48for making an ohmic contact with the data line4, the source electrode10, the drain electrode12, the lower data pad electrode36and the storage electrode22are further provided.

The pixel electrode18is connected, via a first contact hole16passing through a passivation film50, to the drain electrode12of the thin film transistor6. The pixel electrode18generates a potential difference with respect to a common electrode provided at an upper substrate (not shown) by the charged pixel signal. This potential difference rotates a liquid crystal positioned between the thin film transistor substrate and the upper substrate owing to a dielectric anisotropy and transmits a light input, via the pixel electrode18, from a light source (not shown) toward the upper substrate.

The storage capacitor20includes a previous gate line2, a upper storage electrode22overlapping the gate line2and having the gate insulating film44, the active layer14and the ohmic contact layer48therebetween, and a pixel electrode18overlapping the upper storage electrode22and having the passivation film50therebetween and connected via a second contact hole24passing through the passivation film50. The storage capacitor20allows a pixel signal charged in the pixel electrode18to be stably maintained until a next pixel voltage is charged.

The gate line2is connected, via the gate pad26, to a gate driver (not shown). The gate pad26consists of a lower gate pad electrode28extended from the gate line2, and an upper gate pad electrode32connected, via a third contact hole30passing through the gate insulating film44and the passivation film50, to the lower gate pad electrode28.

The data line4is connected, via the data pad34, to the data driver (not shown). The data pad34includes a lower data pad electrode36extended from the data line4, and an upper data pad electrode40connected, via a fourth contact hole38passing through the passivation film50, to the lower data pad electrode36.

Hereinafter, a method of fabricating the thin film transistor substrate having the above-mentioned structure using the four-mask process will be described in detail with reference toFIG. 3AtoFIG. 3D.

InFIG. 3A, a gate pattern including the gate line2, the gate electrode8and the lower gate pad electrode28is provided on the lower substrate42by the first mask process.

More specifically, a gate metal layer is formed on the lower substrate42by a deposition technique such as sputtering. Then, the gate metal layer is patterned by a photolithography and etching process using a first mask to thereby form a gate pattern including the gate line2, the gate electrode8and the lower gate pad electrode28. The gate metal layer may have a single-layer or double-layer structure of chrome (Cr), molybdenum (Mo) or an aluminum group metal, etc.

InFIG. 3B, the gate insulating film44is formed on the lower substrate42provided with the gate pattern. Further, a semiconductor pattern including the active layer14and the ohmic contact layer48and source/drain pattern including the data line4, the source electrode10, the drain electrode12, the lower data pad electrode36and the storage electrode22are sequentially provided on the gate insulating film44by the second mask process.

More specifically, the gate insulating film44, an amorphous silicon layer, a n+amorphous silicon layer and a source/drain metal layer are sequentially provided on the lower substrate42provided with the gate pattern by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and sputtering, etc. Herein, the gate insulating film44is formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The source/drain metal may be selected from molybdenum (Mo) or a molybdenum alloy, etc.

Then, a photo-resist pattern is formed on the source/drain metal layer by the photolithography using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used as a second mask, thereby allowing a photo-resist pattern of the channel portion to have a lower height than other source/drain pattern portion.

Subsequently, the source/drain metal layer is patterned by a wet etching process using the photo-resist pattern to thereby provide the source/drain pattern including the data line4, the source electrode10, the drain electrode12being integral to the source electrode10and the storage electrode22.

Next, the n+amorphous silicon layer and the amorphous silicon layer are patterned at the same time by a dry etching process using the same photo-resist pattern to thereby provide the ohmic contact layer48and the active layer14.

The photo-resist pattern having a relatively low height is removed from the channel portion by a ashing process and thereafter the source/drain pattern and the ohmic contact layer48of the channel portion are etched by the dry etching process. Thus, the active layer14of the channel portion is exposed to disconnect the source electrode10from the drain electrode12.

Then, the photo-resist pattern left on the source/drain metal pattern group is removed by a stripping process.

InFIG. 3C, the passivation film50including the first to fourth contact holes16,24,30and38are formed on the gate insulating film44provided with the source/drain pattern.

More specifically, the passivation film50is formed entirely on the gate insulating film44provided with the source/drain pattern by a deposition technique such as the plasma enhanced chemical vapor deposition (PECVD). Then, the passivation film50is patterned by the photolithography and etching process using a third mask to thereby define the first to fourth contact holes16,24,30and38. The first contact hole16is formed in such a manner to pass through the passivation film50and expose the drain electrode12, whereas the second contact hole24is formed in such a manner as to pass through the passivation film50and expose the upper storage electrode22. The third contact hole30is formed in such a manner as to pass through the passivation film50and the gate insulating film44and expose the lower gate pad electrode28. The fourth contact hole38is formed in such a manner as to pass through the passivation film50and expose the upper data pad electrode36.

The passivation film50is formed of an inorganic insulating material identical to the gate insulating film44, or an organic insulating material such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.

InFIG. 3D, a transparent conductive pattern including the pixel electrode18, the upper gate pad electrode32and the upper data pad electrode40is provided on the passivation film50by the fourth mask process.

A transparent conductive layer is formed on the passivation film50by a deposition technique such as sputtering, etc. Then, the transparent conductive layer is patterned by photolithography and an etching process using a fourth mask to thereby provide the transparent conductive pattern including the pixel electrode18, the upper gate pad electrode32and the upper data pad electrode40. The pixel electrode18is electrically connected, via the first contact hole16, to the drain electrode12while being electrically connected, via the second contact hole24, to the upper storage electrode22overlapping with a previous gate line2. The upper gate pad electrode32is electrically connected, via the third contact hole30, to the lower gate pad electrode28. The upper data pad electrode40is electrically connected, via the fourth contact hole38, to the lower data pad electrode36. Herein, the transparent conductive layer is formed of indium-tin-oxide (ITO), etc.

As described above, the related art thin film transistor substrate and the fabricating method uses a four-mask process, thereby reducing the number of processes and hence reducing manufacturing costs in proportion to the reduction in the number of processes.

However, in the related art thin film transistor substrate, the upper and lower electrodes of the storage capacitor20are formed of an opaque source/drain metal and an opaque gate metal, respectively. Thus, the problem arises in that, when an overlapping area between the upper storage electrode22and the gate line2is enlarged so as to increase a capacitance of the storage capacitor20, an aperture ratio of the pixel electrode18is reduced.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to liquid crystal display device and fabricating method thereof that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

An advantage of the present invention to provide a thin film transistor substrate and a fabricating method thereof that are adaptive for simplifying a process as well as enlarging a capacitance value of a storage capacitor without any reduction of aperture ratio.

In order to achieve these and other advantages of the invention, a liquid crystal display device according to an embodiment of the present invention includes: a double-layered gate line having a first transparent conductive layer and a second opaque conductive layer, the second opaque conductive layer having a step coverage; a gate insulation film on the gate line; a data line crossing the gate line to define a pixel region; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor via a contact hole of a protective film on the thin film transistor; and a storage capacitor overlapping the pixel electrode and having a lower storage electrode formed of the first transparent conductive layer.

In another embodiment of the present invention, a method of fabricating a liquid crystal display device includes: forming a gate pattern including a gate line, a gate electrode and a lower storage electrode on a substrate using a first mask, the gate line and the gate electrode being formed of a double-layer having a transparent conductive layer, and the lower storage electrode being formed of the transparent conductive layer; forming a gate insulating film on the gate pattern; forming a semiconductor pattern and a source/drain pattern having a data line and source and drain electrodes on the gate insulating film using a second mask, the data line defining a pixel region with the gate line; forming a protective film on the source and drain electrodes, and forming a contact hole exposing the drain electrode using a third mask; and forming a pixel electrode connected to the drain electrode via the contact hole on the protective film and overlapping with the lower storage electrode using a fourth mask.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

FIG. 4is a plan view showing a portion of a thin film transistor substrate according to an embodiment of the present invention, andFIG. 5is a section view of the thin film transistor substrate taken along the II-II′, III-III′ and IV-IV′ lines inFIG. 4.

InFIG. 4andFIG. 5, the thin film transistor substrate includes a gate line102and a data line104provided on a lower substrate142in such a manner as to cross each other, the data line104and gate line102having a gate insulating film144therebetween, a thin film transistor106being adjacent to each crossing, and a pixel electrode118provided at a pixel area defined by the crossing structure. Further, the thin film transistor substrate includes a storage capacitor120provided at an overlapped portion between the pixel electrode118and a lower storage electrode122connected to a previous gate line102, a gate pad126connected to the gate line102, and a data pad134connected to the data line104.

The thin film transistor106allows a pixel signal applied to the data line104to be charged into the pixel electrode118and be kept in response to a scanning signal applied to the gate line102. To this end, the thin film transistor106includes a gate electrode108connected to the gate line102, a source electrode110connected to the data line104, a drain electrode112positioned opposite the source electrode110and connected to the pixel electrode118, an active layer114overlapping with the gate electrode108with having the gate insulating film144therebetween to define a channel between the source electrode110and the drain electrode112, and an ohmic contact layer146formed on the active layer114other than the channel portion to make an ohmic contact with the source electrode110and the drain electrode112.

Herein, the gate line102and the gate electrode108have a double-layered structure in which a first conductive layer101formed from a transparent conductive layer and a second conductive layer103formed from a metal layer thereon are disposed.

Further, the semiconductor pattern148including the active layer114and the ohmic contact layer146also overlap with the data line104.

A pixel area defined by a crossing between the gate line102and the data line104is provided with a pixel electrode118. The pixel electrode118is connected, via a first contact hole116passing through the passivation film150, to the drain electrode112. Such a pixel electrode118charges a pixel signal supplied from the thin film transistor106to thereby generate a potential difference with respect to a common electrode provided at a color filter substrate (not shown). This potential difference rotates a liquid crystal positioned between the thin film transistor substrate and the color filter substrate based on a dielectric anisotropy and controls an amount of a light input, via the pixel electrode118, from a light source (not shown) to thereby transmit it into the color filter substrate.

The storage capacitor120is formed such that the lower storage electrode122protruded from the first conductive layer101toward the pixel area overlaps with the pixel electrode118with the gate insulating film144and the passivation film150therebetween. The lower storage electrode122is formed from the first conductive layer101, that is, a transparent conductive layer, so that an overlapping area between it and the pixel area can be enlarged without a reduction of aperture ratio. Accordingly, it becomes possible to increase a capacitance of the storage capacitor120without any reduction of aperture ratio, and hence to keep the signal charged in the pixel electrode118more stable.

The gate line102is connected, via the gate pad126, to a gate driver (not shown). The gate pad126includes a lower gate pad electrode128extended from the gate line102, and an upper gate pad electrode132connected, via a second contact hole130passing through the passivation film150and the gate insulating film144, to the lower gate pad electrode128. The lower gate pad electrode128has a double-layered structure in which the first and second conductive layers101and103are formed like the gate line102.

The data line104is connected, via a data pad134, to a data driver (not shown). The data pad134consists of a lower data pad electrode136extended from the data line104, and an upper data pad electrode140connected, via a third contact hole138passing through the passivation film150, to the lower data pad electrode136. The semiconductor layer148including the ohmic contact layer146and the active layer114is formed under the lower data pad electrode136in such a manner to overlap with it.

As described above, the thin film transistor substrate according to the embodiment of the present invention forms the lower storage electrode122, overlapped by the pixel electrode118, from a transparent conductive layer, so that a capacitance of the storage capacitor120can be increased without any reduction of aperture ratio. Accordingly, a line width of the gate line102can be reduced independently of an overlapping area between the gate line102and the pixel electrode118, thereby having an advantage in making a high definition.

The thin film transistor substrate according to the embodiment of the present invention having the above-mentioned structure is formed by the following four-mask process.

FIG. 6AandFIG. 6Bare a plan view and a section view, respectively, for explaining a first mask process in a method of fabricating the thin film transistor substrate according to the embodiment of the present invention, andFIG. 7AtoFIG. 7Eare section views specifically explaining the first mask process.

A gate pattern including the gate line102, the gate electrode108connected to the gate line102, the lower gate pad electrode128and the lower storage electrode122is formed on the lower substrate142by a first mask process. The gate line102, the gate electrode108and the lower gate pad electrode128have a double-layered structure in which the first and second conductive layers101and103are formed, whereas the lower storage electrode122has a single-layered structure in which the first conductive layer101of the gate line102is extended. The gate pattern having the above-mentioned double-layered and single-layered structure is formed by a single mask process using a half tone mask160.

More specifically, as shown inFIG. 7A, the first and second conductive layers101and103are formed on the lower substrate142by a deposition technique such as sputtering, and a photo-resist176is formed thereon. The first conductive layer101is formed of a transparent conductive material such as indium-tin-oxide (ITO), tin-oxide (TO), indium-zinc-oxide (IZO) or the like. The second conductive layer103is formed of a metal material such as Mo, Cu, Al, Ti, Cr, MoW or AlNd, etc.

Next, the photo-resist167is exposed to light and developed by photolithography using a half tone mask160, thereby forming a photo-resist pattern168having a step coverage as shown inFIG. 7B.

The half tone mask160includes a transparent quartz (SiO2) substrate166, and a shielding layer162and a partial transmitting layer164formed thereon. Herein, the shielding layer162is positioned at an area to be provided with a gate pattern to shut off an ultraviolet ray (UV), thereby leaving a first photo-resist pattern168A after a development thereof. The partial transmitting layer164is positioned at an area to be provided with the lower storage electrode to partially transmit the UV, thereby leaving a second photo-resist pattern168B thinner than the first photo-resist pattern168A. To this end, the shielding layer162is formed of a metal such as Cr, CrOxor the like, whereas the partial transmitting layer164is made from MoSix. Besides the half tone mask, a diffractive exposure mask also is applicable.

Subsequently, the first and second conductive layers101and103are patterned by an etching process using the photo-resist pattern168having a step coverage to thereby provide a double-layer structure of gate pattern as shown inFIG. 7C.

Then, the photo-resist pattern168is ashed by an ashing process using an oxygen (O2) plasma to thereby thin the thickness of the first photo-resist pattern168A and remove the second photo-resist pattern168B as shown inFIG. 7D. Further, the second conductive layer103on the lower storage electrode122is removed by an etching process using the ashed first photo-resist pattern168A. Thus, the lower storage electrode122can be formed from only the first conductive layer101without a miss-alignment to the second conductive layer103included in the gate line102. At this time, each side of the second conductive layer103patterned along the ashed first photo-resist pattern168A is once more etched, thereby allowing the first and second conductive layers101and103of the gate pattern to have a certain step coverage in a stepwise shape. Accordingly, when the side surfaces of the first and second conductive layers101and103have a high steep slope, it becomes possible to prevent a breakage badness of the source/drain metal layer that may be generated thereon.

Meanwhile, the etching process of the first and second conductive layers101and103may selectively employ wet etching or dry etching. For instance, if all the first and second conductive layers101and103are etched, then the etching process of the first and second layers101and103as shown inFIG. 7C; and the ashing process of the photo-resist pattern and the etching process of the exposed second conductive layer103as shown inFIG. 7Dare successively performed at the same chamber, so that an advantage of a process simplification can be obtained.

Alternatively, the etching process of the exposed second conductive layer103may employ wet etching. In another example, the first and second conductive layers101and103may employ wet etching as shown inFIG. 7C, and both the ashing process and the etching process of the exposed second conductive layer103may employ a dry etching or the etching process of the exposed second conductive layer103only may employ a wet etching as shown inFIG. 7D. Otherwise, the second conductive layer103performs a wet etching while the first conductive layer101performs a dry etching, or the second conductive layer103performs a dry etching and the first conductive layer101performs a wet etching; and thereafter both the ashing process and the etching process of the exposed second conductive layer103employ a dry etching or only the etching process of the exposed second conductive layer103employs a wet etching.

Accordingly, dry etching is advantageous when it is applied to a high-definition model, whereas wet etching is advantageous when it is applied to a high-dimension model. Further, dry etching is advantageous when the second conductive layer103is formed of Mo, whereas a wet etching is advantageous when the second conductive layer103is made from Cu or Al.

Consequently, the photo-resist pattern168A left on the gate pattern is removed by the stripping process as shown inFIG. 7E.

FIG. 8AandFIG. 8Bare a plan view and a section view for explaining a second mask process, respectively, in a method of fabricating the thin film transistor substrate according to an embodiment of the present invention, andFIG. 9AtoFIG. 9Eare section views explaining the second mask process in detail.

First, the gate insulating film144is formed on the lower substrate142provided with the gate pattern. Further, the source/drain pattern including the data line104, the source electrode110, the drain electrode112and the lower data pad electrode136and the semiconductor pattern148including the active layer114and the ohmic contact layer146overlapping each other along the rear side of the source/drain pattern are formed thereon by the second mask process. The semiconductor pattern148and the source/drain pattern are formed by a single mask process using a diffractive exposure mask.

More specifically, as illustrated inFIG. 9A, the gate insulating film144, an amorphous silicon layer115, an amorphous silicon layer145being doped with n+or p+impurity and the source/drain metal layer105are sequentially formed on the lower substrate142provided with the gate pattern. For instance, the gate insulating film144, the amorphous silicon layer115and the amorphous silicon doped with the impurity may be formed by PECVD, whereas the source/drain metal layer105is formed by sputtering. The gate insulating film144is formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), whereas the source/drain metal layer105is formed of Cr, MoW, Al/Cr, Cu, Al(Nd), Al/Mo, Al(Nd)/Al, Al(Nd)/Cr, Mo/Al(Nd)/Mo, Cu/Mo or Ti/Al(Nd)/Ti, etc. For example, a double layer of Al/Cr means that Cr should be formed first and Al should be formed later.

Further, a photo-resist219is formed on the source/drain metal layer105and then is exposed to the light and developed by photolithography using a diffractive exposure mask210, thereby providing a photo-resist pattern220having a step coverage as shown inFIG. 9B.

The diffractive exposure mask210includes a transparent quartz substrate212, a shielding layer214formed from a metal layer such as Cr, CrOxor the like, and a diffractive exposure slit216. The shielding layer214is positioned at an area to be provided with the semiconductor pattern and the source/drain pattern to shut off an ultraviolet ray (UV), thereby leaving a first photo-resist pattern220A after a development thereof. The diffractive exposure slit216is positioned at an area to be provided with a channel of the thin film transistor to diffract the UV, thereby leaving a second photo-resist pattern220B thinner than the first photo-resist pattern220A.

Subsequently, the source/drain metal layer105is patterned by an etching process using the photo-resist pattern220having a step coverage to thereby provide the source/drain pattern and the semiconductor pattern148under it as shown inFIG. 9C. In this case, the source electrode110and the drain electrode112of this source/drain pattern have an integral structure.

Then, the photo-resist pattern220is ashed by the ashing process using an oxygen (O2) plasma to thereby thin the thickness of the first photo-resist pattern220A and remove the second photo-resist pattern220B as shown inFIG. 9D. Further, the source/drain pattern exposed by a removal of the second photo-resist pattern220B and the ohmic contact layer under it is removed by an etching process using the ashed first photo-resist pattern220A, thereby disconnecting the source electrode110from the drain electrode112and exposing the active layer114. Thus, a channel consisting of the active layer114is provided between the source electrode110and the drain electrode112. At this time, each side of the source/drain pattern is once more etched along the ashed first photo-resist pattern220A to provide the source/drain pattern and semiconductor pattern148having a step coverage in a stepwise shape.

Consequently, the photo-resist pattern220A left on the source/drain pattern is removed by a stripping process as shown inFIG. 9E.

FIG. 10AtoFIG. 10Care a plan view and section views for explaining a third mask process in a method of fabricating the thin film transistor substrate according to the embodiment of the present invention.

The passivation film150having a plurality of contact holes116,130and138is formed by the gate insulating film144provided with the source/drain pattern by the third mask process.

The passivation film150is formed on the gate insulating film144provided with the source/drain pattern by a technique such as the PECVD and spin coating, etc. The passivation film150is formed of an inorganic insulating material identical to the gate insulating film144, or an organic insulating material such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc. Then, the passivation film150is patterned by the photolithography process and the etching process to thereby provide the first contact hole exposing the drain electrode112, the second contact hole130exposing the lower gate pad electrode128and the third contact hole138exposing the lower data pad electrode136.

Meanwhile, when the source/drain metal is selected from Mo, the first and third contact holes116and138are formed in such a manner to pass through the active layer114as shown inFIG. 10C.

FIG. 11AandFIG. 11Bare a plan view and a section view explaining a fourth mask process in a method of fabricating the thin film transistor substrate according to the embodiment of the present invention

A transparent conductive pattern including the pixel electrode118, the upper gate pad electrode132and the upper data pad electrode140is formed on the passivation film150by the fourth mask process.

The transparent conductive pattern is formed by preparing a transparent conductive layer using a deposition technique such as the sputtering, etc. and patterning it by the photolithography and the etching process. The transparent conductive layer is formed of ITO, TO or IZO, etc. similar to the first conductive layer101of the above-mentioned gate pattern. The pixel electrode118is connected, via the first contact hole116, to the drain electrode112; the upper gate pad electrode132is connected, via the second contact hole130, to the lower gate pad electrode128; and the upper data pad electrode140is connected, via the third contact hole138, to the lower data pad electrode136.

As described above, the method of fabricating the thin film transistor substrate according to the embodiment of the present invention forms the gate pattern having a double-layer structure and the lower storage electrode122having a single-layer structure using the half-tone mask, thereby simplifying a process by the four-mask process. Furthermore, the method of fabricating the thin film transistor substrate according to the embodiment of the present invention uses the half tone mask when it is intended to thinly form the photo-resist pattern corresponding to a relatively wide area like the lower storage electrode122while using the diffractive exposure mask when it is intended to thinly form the photo-resist pattern corresponding to a relatively narrow area like the channel of the thin film transistor106, thereby improving a process efficiency.

FIG. 12is a section view showing only a gate pattern formed by a first mask process in a thin film transistor substrate according to a second embodiment of the present invention.

The gate pattern shown inFIG. 12includes a gate line202, a gate electrode208and a lower gate pad electrode228having a triple-layer structure in which the first to third conductive layers201,203and205are disposed, and a lower storage electrode222provided such that the first conductive layer201of the gate line202is extended into a pixel area. The gate pattern having the above-mentioned triple-layer and single-layer structure is formed by a single mask process using a half tone mask. The gate pattern having the triple-layer structure has a reduced line resistance such that it is may be used for a large-dimension or high-definition panel. The first conductive layer201is formed of a transparent conductive material such as indium-tin-oxide (ITO), tin-oxide (TO), indium-zinc-oxide (IZO) or the like. The second conductive layer203is formed of a metal material such as Mo, Ti, Cu or Al(Nd) group, etc. The third conductive layer205is formed from a metal material such as Cu, Al, Ti, Mo or Al(Nd) group, etc., and the second and third conductive layers203and205may be formed of a combination of these groups. For instance, they may be formed of Mo/ITO, Al(Nd)/ITO, Cu/ITO, Cu/Ti/ITO, Cu/Mo/ITO, Cu/Mo/ITO, Cu/Mo+Ti/ITO or Al(Nd)/Mo/ITO, etc. Herein, a more than double layer of Mo/ITO means that ITO should be formed first and Mo should be formed later.

FIG. 13is a plan view showing a portion of a thin film transistor substrate according to a third embodiment of the present invention, andFIG. 14is a section view of the thin film transistor substrate taken along the II-II′, III-II′, IV-IV′ and V-V′ lines inFIG. 13.

The thin film transistor substrate shown inFIG. 13andFIG. 14has the same elements as the thin film transistor substrate shown inFIG. 4andFIG. 5except that it further includes a redundancy line overlapping with the data line104. Therefore, an explanation as to the same elements will be omitted.

The redundancy line170is connected to the data line104by a welding technique using a laser or the like upon a breakage or defection of the data line104to thereby repair the broken data line104. The redundancy line170may be formed as a single-layer structure like the lower storage electrode122or a double-layer (or triple-layer) structure like the gate line102, along with the gate pattern including the gate line102, the gate electrode108, the lower gate pad electrode128and the lower storage electrode122, by the half tone mask process. Further, the redundancy line170is formed independently between the gate lines102and floated such that it is not shorted with respect to the gate line102provided at the same layer.

FIG. 15is a plan view showing a portion of a thin film transistor substrate according to a fourth embodiment of the present invention, andFIG. 16is a section view of the thin film transistor substrate taken along the III-III′, IV-IV′ and VI-VI′ lines inFIG. 15.

The thin film transistor substrate shown inFIG. 15andFIG. 16has the same elements as the thin film transistor substrate shown inFIG. 4andFIG. 5except that it further includes a light-shielding pattern172overlapping with each side of the pixel electrode118. Therefore, an explanation as to the same elements will be omitted.

The light-shielding pattern172is formed such that the second conductive layer103is extended from the gate line102to thereby overlap with each side of the pixel electrode118, whereas the lower storage electrode122is formed in such a manner as to overlap with the light-shielding pattern172for the sake of a process. The light-shielding pattern172prevents a light leakage between the data line104and the pixel electrode118when it is intended to enlarge a distance between the data line104and the pixel electrode118for the purpose of reducing a parasitic capacitor. The light-shielding pattern172is formed from the second conductive layer102, along with the gate pattern including the gate line102, the gate electrode108, the lower gate pad electrode128and the lower storage electrode122, by the half tone mask process. The lower portion of the light-shielding pattern172overlaps with the lower storage electrode122that is the first conductive layer101.

FIG. 17is a plan view showing a portion of a thin film transistor substrate according to a fifth embodiment of the present invention, andFIG. 18is a section view of the thin film transistor substrate taken along the III-III′, IV-IV′ and VII-VII′ lines inFIG. 17.

The thin film transistor substrate shown inFIG. 17andFIG. 18has the same elements as the thin film transistor substrate shown inFIG. 4andFIG. 5except that a storage capacitor180is formed by an overlap between the common line182and the pixel electrode118. Therefore, an explanation as to the same elements will be omitted.

The storage capacitor180is formed such that the common line182is overlapped by the pixel electrode118having the gate insulating film144and the passivation film150therebetween. The common line182crosses the pixel electrode118and the data line104substantially parallel to the gate line102. The common line182is formed, along with the gate pattern including the gate line102, the gate electrode198and the lower gate pad electrode128, by the halftone mask process. At this time, the common line182is formed from only the first conductive layer101that is a transparent conductive layer unlike a double-layer (or triple-layer) structure of gate pattern by utilizing a partial transmitting part of the half tone mask. Accordingly, both the pixel electrode118and the common line182that are the upper and lower electrodes of the storage capacitor180, respectively, are formed from a transparent conductive layer, so that it becomes possible to enlarge an overlap area between two electrodes118and182without any reduction of aperture ratio and hence to increase a capacitance value of the storage capacitor180.

FIG. 19is a plan view showing a portion of a thin film transistor substrate according to a sixth embodiment of the present invention, andFIG. 20is a section view of the thin film transistor substrate taken along the III-III′, IV-IV′ and VIII-VII′ lines inFIG. 19.

The thin film transistor substrate shown inFIG. 19andFIG. 20has the same elements as the thin film transistor substrate shown inFIG. 4andFIG. 5except that a storage capacitor190is formed by an overlap among the common line182, the lower storage electrode194connected thereto and the pixel electrode118. Therefore, an explanation as to the same elements will be omitted.

The storage capacitor190is formed such that the common line192and the lower storage electrode194are overlapped by the pixel electrode118with the gate insulating film144and the passivation film150therebetween. The common line192is formed by a double-layer (or triple-layer) structure crossing the pixel electrode118and the data line104substantially parallel to the gate line102. The lower storage electrode194is formed by a protrusion of the first conductive layer101, that is, the transparent conductive layer, of the common line192at each pixel area. The common line182and the lower storage electrode194are formed, along with the gate pattern including the gate line102, the gate electrode198and the lower gate pad electrode128, by the half tone mask process. At this time, the lower storage electrode194is formed from only the first conductive layer101that is a transparent conductive layer unlike a double-layer (or triple-layer) structure of gate pattern and the common line192by utilizing a partial transmitting part of the half tone mask. Accordingly, an overlap area between the lower storage electrode194and the pixel electrode118can be enlarged without any reduction of aperture ratio to increase a capacitance value of the storage capacitor190. Furthermore, the common line192takes a double-layer (or triple-layer) structure like the gate pattern to reduce a line resistance, so that a line width of the common line192can be reduced to minimize a parasitic capacitor caused by an intersection between the common line192and the data line104.

As described above, according to the present invention, both the upper and lower electrodes of the storage capacitor are formed from a transparent conductive layer, so that it becomes possible to enlarge an overlap area between two electrodes without any reduction of aperture ratio and hence to increase a capacitance value of the storage capacitor.

Particularly, according to the present invention, a single-layer structure of a lower storage electrode (or common line) is formed, along with a double-layer (or triple-layer) structure of gate pattern, by utilizing the half tone mask, thereby simplifying a process. Furthermore, according to the present invention, the first and second conductive layers of the gate pattern taking a double-layer (or triple-layer) structure has a constant step coverage in a stepwise shape by the half-tone mask process, so that it becomes possible to prevent a breakage of the source/drain pattern caused by an inclination of the first and second conductive layers.

Moreover, according to the present invention, the half tone mask is used when it is intended to relatively thinly define the wide photo-resist pattern, whereas the diffractive exposure mask is used when it is intended to relatively thinly define the narrow photo-resist pattern. Thus, it becomes possible to improve the process efficiency.

Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.