Volatile memory erasure by the randomization of data stored in memory cells

The present invention discloses an erasure circuitry, a method for erasing a volatile memory, a volatile memory and a processing unit coupled with an operating system, where the erasure circuitry is adapted to erase the volatile memory at occurrence of a predefined event. The erasure circuitry includes a control unit for initiating a dummy operation to randomize data of one or more memory cells at the occurrence of a predefined event. The control unit is adapted to receive the addresses of the memory blocks from a processing unit via an operating system.

FIELD OF THE INVENTION

The present invention relates generally to volatile memory erasure and more particularly to a method, an erasure circuitry, and a volatile memory adapted for erasing the data stored inside one or more memory banks of the memory.

BACKGROUND OF THE INVENTION

In the cloud virtualized infrastructure, multiple tenants may co-exist in the same physical host, sharing the host's physical DRAM memory and disk storage. Virtualization technology used in the cloud creates the illusion of having multiple virtual machines (VMs) within the same physical host by means of sharing and multiplexing the host resources which include its multiple CPU cores, physical memory, and hard disk.FIG. 1shows three VMs which belong to different users that are allocated portions of physical memory and hard disk.

In the cloud, the VMs are allocated on demand and dynamically to different users. A VM may stay running for some period of time (minutes, hours, or days) and then get terminated by a user. Once terminated, its resources are re-allocated to a newly provisioned VM. Each time a new VM is allocated, its resources are allocated from the older VM resources, as shown inFIG. 2.

FIG. 2illustrates resource allocation after termination of VM2and provisioning of VM4.FIG. 2(a)shows that the memory and disk resources of VM2are available for use after VM2termination. InFIG. 2(b), a new virtual machine is provisioned by user4(VM4) and has been allocated the memory and disk resources of VM2. Once VM4is running, the user of this VM can have access to the content of DRAM and disk storage which was used by the older user. The new user can simply take memory images and snapshots and then perform offline forensic analysis to extract sensitive information of the older user. This indeed poses a serious data privacy problem.

As has been illustrated, a critical security problem and data privacy issue can exist if the DRAM content is not sanitized or wiped out before being allocated to a newly provisioned VM. The cloud provider has to provide a total isolation and protection of user data during run time and after termination. If the data in physical memory and hard disk are not properly sanitized and deleted at run time and after deletion, sensitive information can be leaked, thereby jeopardizing the privacy of the cloud users and their data. Sensitive information may include confidential documents and images, passwords, encryption keys, personal information and records, banking and credit card information, metadata, etc.

The cloud computing platform is just one example of contexts where physical memory is shared between multiple users. A single physical machine can also provide access to multiple users in a sequential manner such that different sessions are initiated and terminated for different users. If data stored on the physical memory by one user is not deleted, this data can be accessed by a subsequent user accessing the machine.

To date, wiping out the DRAM and disk storage, if done, is performed using software by means of zeroing out DRAM content using software. At boot time of the newly provisioned VM, the software would write zeroes or random data to the DRAM. The zeroing out method involves the CPU to carry out sequential memory-write operations of zeros to all physical memory locations. This is considerably slow and expensive operation especially. For a small size, it may take a few seconds to wipe out 1 GB DRAM. For larger-size VMs, the DRAM portion can be as big as 64 GB or more. For this, wiping out the memory using software may take a few minutes. Such time is not acceptable in some contexts such as by the cloud user as it prolongs the launch and boot time of VM instances.

Other methods can zero out the memory using software at user session/VM termination (and not at boot time). Still, this solution is not adequate and will slow down enormously the availability of the freed memory to be allocated to newly provisioned users/VMs.

In short, software solutions that deal with zeroing out the physical memory at boot up or after termination are not adequate solutions, due to the computation overhead cost. That is, such software solutions will be considerably slow considering the size of the allocated RAM which can be in tens of gigabytes. Such solutions may take minutes, and will stretch the bootup time enormously. Equally, it is also imperative to shorten the termination time of a machine (such as a VM) so that freed resources can be allocated quickly to newly provisioned VMs.

Further, it will be understood to the persons skilled in the art that DRAM provides maximum memory density at cost of access time. Basic DRAM cell3consists of one nMOS transistor and one capacitor (FIG. 3). The transistor is used to control access to the storage element (capacitor). The memory state is stored as charge on the capacitor. Since the charge on the capacitor can leak away hence, the need for refreshing when DRAM is used. The refreshing time is determined by the time the capacitor can maintain enough charge to indicate logic one. In addition to refreshing DRAM, read access is destructive which means when the cell gets access for read the data stored is disturbed and another operation need to be performed to re-store data.

Memory controller keeps track of memory array access and refreshing times. It is proposed to utilize this hardware feature that already exists to zeroing DRAM content. This provides hardware managed solution which is much faster than the software counterpart. The implementation of the proposed scheme can vary based on the tradeoff between memory availability, area overhead, and design complexity.

The array size can be static for all programs and will depend on the total memory size or it can be dynamic based on number of programs and overall system performance.FIG. 4depicts a typical memory array organization with a major interface where N+M are address bits and D is the data interface.

SUMMARY OF THE INVENTION

The present invention aims to overcome the above mentioned limitations and other problems associated with the prior art.

The present invention provides an erasure circuitry, a method for erasing a volatile memory, a volatile memory and a processing unit coupled with an operating system, where the erasure circuitry is adapted to erase the memory at occurrence of a predefined event. The erasure circuitry includes a control unit which is adapted to initiate a dummy operation to randomize data of one or more memory cells at the occurrence of a predefined event.

In an embodiment of the present invention, the erasure circuitry further includes a controller associated with the control unit and a processing unit which is associated with the controller such that the control unit is adapted to receive the addresses of one or more memory cells from the processing unit via the operating system.

In an embodiment of the present invention, the volatile memory is connected to the processing unit which is accessible by multiple users, processes, applications or services such that the predefined event is before switching between first user, process, application or service and a subsequent user, process, application or service such that any data stored inside the memory by the first user is erased by the randomizing of data in the one or more memory cells by the control unit of the erasure circuitry.

In an embodiment of the present invention, the processing unit is part of a virtual machine in a cloud computing platform.

In an embodiment of the present invention, the processing unit is part of an electronic device or a server.

In an embodiment of the present invention, the volatile memory is dynamically allocated to multiple processing units and the predefined event occurs before reallocation of the memory from a first processing unit to a second processing unit such that any data stored inside the memory using the first processing unit gets erased by the randomizing of data in the one or more memory cells by the control unit of the erasure circuitry.

In an embodiment of the present invention, the processing units are part of one or more virtual machines in a cloud computing platform.

In an embodiment of the present invention, the volatile memory for erasure is one or more memory banks of a dynamic random access memory (DRAM).

In an embodiment of the present invention, the controller is a DRAM controller.

In another aspect, the present invention provides a volatile memory which includes a control unit adapted to initiate a dummy operation for randomizing the data stored in the memory cells at occurrence of a predefined event.

In yet another aspect, the present invention provides a method for erasing a volatile memory having a plurality of memory cells. The method involves the initiation of a dummy operation for randomizing the data stored in the memory cells at the occurrence of a predefined event.

Like numerals refer to like elements throughout the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

The exemplary embodiments described herein for illustrative purposes are subject to many variations in structure and design. It should be emphasized, however, that the present invention is not limited to method for erasing data from a volatile memory. It is understood that various omissions and substitutions of equivalents are contemplated as circumstances may suggest or render expedient, but these are intended to cover the application or implementation without departing from the spirit or scope of the present invention.

The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item.

The terms “having”, “comprising”, “including”, and variations thereof signify the presence of a component.

The present invention provides a software-hardware based technique to erase the data stored on volatile memory. It will be understood for the persons skilled in the art that the volatile memory needs to be refreshed regularly in order to preserve data from leakage. Therefore, the volatile memory may be having a refresh circuitry to ensure that purpose.

The present invention proposes a method (seeFIGS. 5-6), an erasure circuitry32adapted to erase the memory by initiating a dummy operation to randomize data in the memory cells (seeFIG. 3b). There is also proposed a volatile memory including the erasure circuitry (FIG. 11aandFIG. 11b). A computer encoded medium which includes an erasure module38(seeFIG. 10) has also been disclosed.

As a first aspect of the invention, as illustrated inFIG. 3b, there is provided an erasure circuitry32for erasing volatile memory cells of the volatile memory. The erasure circuitry32includes a control unit34. The control unit34is adapted to initiate a dummy operation to the memory cells. The said dummy operation includes the randomization of data in one or more of the memory cells. The randomization of data means corrupting the data stored in the memory cells.

A volatile memory is a set of multiple memory cells. The control unit34comprises transistors adapted to be connected the worldliness of the volatile memory for conducting a dummy read on the wordlines at the receipt of a signal to this effect.

In the preferred embodiment, the transistors are nMOS and pMOS transistors. The MOS transistors work in pair, such that each pair of transistors comprises one nMOS transistor and one pMOS transistor connected therebetween and to the volatile memory wordlines in such a manner that one of the transistors imposes a dummy read logic on the wordlines at the receipt of a signal by the other transistor. Preferably, the pMOS transistor imposes a 1 logic on all the wordlines connected thereto when the nMOS transistor turns 1 logic. When both nMOS and pMOS transistors are 0 logic, the wordlines continue operation as usual.

The dummy operation is conducted by using the one or more transistor pairs connected to the wordlines of the volatile memory. As many transistor pairs as desired can be added to the wordlines of a volatile memory, based on the resolution (controllability degree) desired. The more transistor pairs added, higher the resolution is, however the cost increases in consequence.

Adding one transistor pair per wordline allows controlling each wordline independently from the other such that a dummy read on one wordline does not affect another wordline. However, the drawback is that the cost will be increased proportionally with the number of transistor pairs required as a single volatile memory can have thousands of wordlines therefore requiring an equal number of transistor pairs. For the purpose of reducing costs, one transistor pair can be connected to a group of wordlines. In this case, a dummy read will affect collectively all the wordlines in that same group. The resolution (controllability degree) is reduced in this case (with respect to a single transistor pair/wordline), however cost is also reduced. The number of transistor pairs required is a design choice which is to be taken based on the requirements of each application where the resolution requirements is to be counter-balanced with costs.

FIG. 13aillustrates an example where one nMOS transistor is used for a group of wordlines. In this case, one pMOS transistor per wordline is used M2and one nMOS transistor M1are added to multiple wordlines of a volatile memory. When the clean signal value is low, both the M1and M2are in off state, the wordline functions as normal. When the clean signal is high, then the M1stops the pull down and the M2turns on and the value of all the wordlines becomes 1.

FIG. 13billustrates an example where one transistor pair is used for each wordline. In this case, one pMOS and one nMOS are added to each wordline of a memory cell. When the clean signal value is low, both the M1and M2are in off state, the wordline functions as normal. When the clean signal is high, then the M1stops the pull down and the M2turns on and the value of the wordlines becomes 1.

In an embodiment of the invention, the control unit34is controlled by controller36of the erasure circuitry32. In an embodiment, the controller36is embodied in a DRAM controller. In another embodiment, the controller36is a DRAM controller.

In an embodiment of the invention, the addresses of the memory blocks from which the data is to be erased are provided by the processing unit33via the operating system. The addresses are provided to the control unit34.

In another embodiment, an erasure module38is provided which consists of computer readable instructions to provide instructions to the erasure circuitry32regarding the occurrence of a predefined event.

The erasure module38includes computer instructions adapted to instruct the erasure circuitry32regarding the occurrence of a predefined event (explained later). The controller36of the erasure circuitry32is adapted to receive such instruction from the erasure module38and in due course the addresses of the memory blocks are provided to the control unit34for initiating the dummy operation for randomizing data of the memory cells.

As illustrated inFIG. 5, there is provided a method of erasing a volatile memory requiring, the erasure method comprising controlling the control unit34for initiating the dummy operation at the occurrence of a predefined event.

According to this method, the first step is to monitor the occurrence of the predefined event at step10. Once the predefined event occurs, the second step12is to manage the control unit for initiating the dummy operation for randomizing data of one or more of the memory cells at the occurrence of a predefined event.

The predefined event can be any event pre-configured by a user which when it occurs, data stored on the volatile memory30needs to be deleted. When the memory30is used by users, processes, applications, and/or services, the predefined event can be for example at the time of use or termination and/or switching between the different users, processes, applications and/or services respectively. For example, when the volatile memory30is accessed/shared by multiple users, the predefined event can be after termination of a first user session and/or at the time of switching between one user and another (after session termination of a first user and before session commencement of a subsequent user). This is in order to clean/erase the data stored by a first user on the memory before a second user is granted access to the memory.

Sharing volatile memory30between multiple users can happen in various contexts, such as for example in computing clouds where virtual machines accessing a same volatile memory30are accessed by multiple users. Computing clouds are not the only environments where memory is shared between users. When the volatile memory30is accessed by different processes, applications and/or services (related or not to different users), the predefined event can be at the time of termination of a first process, application and/or service respectively and/or at the time of switching between different processes, applications and/or services.

This can also happen for example in the case of a single machine with multiple user accounts. Once a first user uses the machine, data is normally stored on the volatile memory30and is not deleted until the machine is rebooted. Where the machine is not rebooted, a subsequent user accessing the machine can have access to the data stored inside the volatile memory30. This also poses a risk of privacy breach. The predefined event can be in this case at the termination of the first user session. In this case, data stored on the volatile memory30is erased before the commencement of the second user session.

As illustrated inFIG. 7, according to an embodiment of the invention, the first step is to monitor the termination of the first user session at step14. Once the first user session is terminated, at step16the volatile memory is erased by the dummy operation initiated by control unit34. The dummy operation randomizes the data of the memory cells and hence erasing the data from the previous user. Then, at step18the subsequent user is provided access to the memory which is already erased. In this case, there will be no need to reboot the machine to delete the data stored on the memory by the first user or use erasure software which can be time consuming. Erasing the memory using the method of this invention occurs very quickly (in the order of milliseconds).

As illustrated inFIG. 7, the volatile memory30can for example be connected to a processing unit20accessible by multiple users. In this case, the predefined event is before switching between a first user and a subsequent user such that any data stored inside the memory30by the first user is erased by the dummy operation initiated by control unit34. The dummy operation randomizes the data of the memory cells and hence erasing the data from the previous user.

The predefined event is preconfigured using computer readable instructions inside the erasure module38or via the operating system. The erasure module38can run on the same processing unit20or on a different processing unit depending on the application. The erasure module38is connected to the erasure circuitry32which in turn is connected to the volatile memory30. Once the predefined event occurs, the erasure module38provides instructions to the controller36of the erasure circuitry32which in turn manages the control unit for initiating the dummy operation on the memory cells for randomizing data of the memory cells.

In an embodiment of the invention, the processing unit20is part of a virtual machine in a computing cloud.

In another embodiment of the invention, the processing unit20is part of an electronic device or server.

As illustrated inFIG. 8, the volatile memory30can be connected to multiple processing units (40,42, and44) for dynamically allocating the volatile memory30to the multiple processing units (40,42, and44). In this case, the predefined event is before reallocation of the memory30from a first processing unit to a second processing unit such that any data stored inside the memory using the first processing unit is erased by the effect of randomizing of data by the control unit34before the second processing unit is being reallocated the memory30. The predefined event is preconfigured using computer readable instructions inside the erasure module34. The erasure module38can run on any one of the processing units (40,32, and44) or on a different processing unit depending on the application. The erasure module38is connected to the erasure circuitry32which in turn is connected to the volatile memory30. Once the predefined event occurs, erasure module38provides instructions to the controller36which in turn manages the control unit34for initiating the dummy operation on the memory cells for randomizing data of the memory cells.

In an embodiment of the invention, the processing units (40,42, and44) are part of one or more virtual machines in a computing cloud.

FIG. 9illustrates the application of this invention in the context of a computing cloud comprising multiple virtual machines (50,52, and54) and a host machine60comprising a hypervisor62. The volatile memory30and the erasure circuitry32are connected to the host machine (50,52, and54) for storing data originating from the use of the virtual machines (50,52, and54) by different users. According to this embodiment, the erasure module38is adapted to run on the host machine60for controlling the method of erasing data from inside the volatile memory30at the occurrence of predefined events such as the switching between different users.

In an embodiment of the invention, the volatile memory30for erasure is one or more memory banks of a dynamic random access memory (DRAM). The volatile memory30can be DRAM or any other type requiring refreshment of data to maintain storage existing now or in the future. When the volatile memory30is DRAM, the controller36is normally a DRAM controller.

In an embodiment of the invention, as illustrated inFIG. 10, there is provided a computer readable medium62encoded with an erasure module38comprising processor executable instructions for execution by a processing unit for controlling the controller36of the erasure circuitry32connected to a volatile memory30such that the controller36further manages the control unit34for initiating the dummy operation on the memory cells for randomizing of data at the occurrence of a predefined event.

In an embodiment of the invention, the erasure module38includes processor executable instructions for controlling the controller36. When the volatile memory30is in a computing cloud, in an embodiment of the invention, the processor executable instructions are adapted to be run by a hypervisor62running one or more virtual machines as described above.

As a further aspect of the invention, as illustrated inFIGS. 11(a) and (b), there is provided an erasure circuitry32adapted to be connected to a volatile memory30, for erasing data of one or more memory cells depending on the occurrence of a predefined event.

The erasure circuitry32can be part of the volatile module30(seeFIG. 11(a)) or alternatively in an external circuit (seeFIG. 11(b)).

As another aspect of the invention, there is provided a volatile memory30comprising an erasure circuitry32adapted to initiate a dummy operation to the memory cells for randomizing data at the occurrence of a predefined event. The erasure circuitry32is adapted to be connected to an erasure module38comprising computer instructions for controlling the erasure circuitry32at the occurrence of the predefined event. In an embodiment of the invention, the volatile memory30is a DRAM.

In an embodiment of the present invention, the control unit34may receive the addresses of the memory blocks to be erased from the processing unit33via the operating system37.

FIG. 12illustrates a block diagram regarding the operation of the control unit34with respect to the volatile memory30and the controller36. It is known in the prior art that the controller may be a separate chip from the main memory or it can be integrated with the main memory. The controller36controls the initiation of the control unit34regarding the initiation of the dummy operation for randomizing of data in the memory cells of the volatile memory at the occurrence of a predefined event.