VERTICAL FIN FIELD EFFECT TRANSISTOR, VERTICAL FIN FIELD EFFECT TRANSISTOR ARRANGEMENT, AND METHOD FOR FORMING A VERTICAL FIN FIELD EFFECT TRANSISTOR

A vertical fin field-effect transistor. The transistor has a semiconductor fin, an n-doped source region, an n-doped drift region, an n-doped channel region in the semiconductor fin situated vertically between the source region and the drift region, a gate region horizontally adjacent to the channel region, a gate dielectric electrically insulating the gate region from the channel region, a boundary surface between the gate dielectric and the channel region having negative boundary surface charges, a p-doped gate shielding region situated below the gate region so that, given the vertical projection, the gate shielding region is situated within a surface limited by the gate dielectric, a source contact electrically conductively connected to the source region, and an electrically conductive region between the gate region and the p-doped gate shielding region. The p-doped gate shielding region is electrically conductively connected to the source contact by the electrically conductive region.

FIELD

The present invention relates to a vertical fin field-effect transistor (FinFET), a vertical fin field-effect transistor system, and a method for forming a vertical fin field-effect transistor.

BACKGROUND INFORMATION

For the use of semiconductors having a wide band gap (e.g. SiC or GaN) in power electronics, power MOSFETs having a vertical channel region are typically used. Here, the channel region is formed adjacent to a trench, so that this type of MOSFET is also referred to as a trench MOSFET (TMOSFET). Through suitable choice of geometry and doping concentrations of epitaxial, channel, and shielding regions, a relatively low switching resistance and a relatively high breakdown voltage can be achieved.

According to the related art, a power trench MOSFET has a deep p+implantation as shielding region and a trench that are periodically combined in alternating fashion to form a cell field made up of a plurality of individual MOSFETs, also referred to as cells. The proportions of the trench, p+shielding region, and a channel region formed between them that is switchable by an insulated gate results from the demands of achieving a switching resistance that is as low as possible, a maximum field load at the gate dielectric that is as low as possible, a saturation current in case of short-circuit that is as low as possible, and a breakdown voltage that is as high as possible. A distance between structures of the same type of adjacent MOSFETs (pitch) is here limited by the technical possibilities of forming the trench, contacting the various regions, and realizing the p+implantation.

A channel resistance of the TMOSFET is determined by the charge carrier distribution in the channel and the mobility thereof. These two variables are decisively determined by boundary surface charges at a boundary surface between the semiconductor material in the channel region and the gate dielectric, or by charges in the gate dielectric and by the channel doping. The cell pitch is decisively determined by the p+shielding region, because in order to produce it high energy implantations are required that in turn presuppose a sufficiently thick mask. The thickness of this mask limits the smallest dimension that can be opened, and via this limits the cell pitch.

SUMMARY

In various exemplary embodiments of the present invention, a vertical fin field-effect transistor (vertical FinFET, or FinFET for short; in a FinFET, the switchable component is made up of a narrow semiconductor fin) is provided having a trench contact for a shielding structure. Graphically described, in the vertical fin field-effect transistor the shielding structure is situated directly below the trench, and is connected in electrically conductive fashion to an electrically conductive contact formed in the trench.

Through its geometry and through a suitable choice of material and manufacturing process of the gate dielectric, a particularly low channel resistance can be enabled.

The contacting of the shielding structure by the trench can enable a particularly small cell pitch.

The FinFET can for example be used as a power FinFET. Accordingly, in various exemplary embodiments a switching resistance of the power FinFET with the trench contact can be significantly lower than in a MOSFET or MISFET based on silicon carbide (SiC) or gallium nitride (GaN) according to the existing art. From this there result lower losses during operation of the overall component.

In various exemplary embodiments of the present invention, a power FinFET is provided having a trench contact to a shielding structure. Dimensions, dopings, and boundary surface charges at a gate dielectric (e.g. gate oxide) can, as explained in more detail below, be set up such that a low switching resistance, a high breakdown voltage, a low short-circuit current, and a low maximum field loading at the gate dielectric can be achieved.

In addition, a method is provided for forming such a FinFET, a relative positioning of the trench and of the shielding structure taking place in self-adjusting fashion. This means that a high degree of relative positioning accuracy can be achieved with simple manufacturing.

Developments of the aspects of the present invention are disclosed herein. Specific embodiments of the present invention are shown in the Figures and are explained in more detail in the following description.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG.1shows a schematic cross-sectional view of a vertical FinFET100according to various exemplary embodiments.

Vertical fin field-effect transistor100can have an n-doped semiconductor fin14(or “fin” for short) that can extend vertically between an n-doped source region30(above or in the upper end of fin14) and an n-doped drift region10,12(below fin14) of the FinFET. Drift region10,12can have an n-doped drift region10and an n-doped spreading region12. In various exemplary embodiments, a doping concentration can be higher in spreading region12than in drift region10situated below it, and can be higher than in the n-channel region situated above it in semiconductor fin14. In an exemplary embodiment, the dopings can be for example 1016cm−3in drift region10, 1017cm−3in spreading region12, and 4·1016cm−3in the channel region in fin14. The n-doped semiconductor material of drift region10,12and of fin14can be provided as an epitaxially grown material, e.g. grown on a substrate, if appropriate having a buffer layer situated between drift region10,12and the substrate. On a rear side of the substrate, a drain contact can be situated. The substrate, drain contact, and, if present, buffer layer can be produced in a conventional or substantially conventional manner.

In addition, vertical fin field-effect transistor100can have at least one gate region24that is horizontally adjacent to the channel region. In the exemplary embodiment ofFIG.1, two gate regions24are formed horizontally adjacent to fin14, which gate regions can be electrically insulated from fin14by a gate dielectric32, and from a source contact28situated above it by a further dielectric26. Gate region24can include a conductive material, for example polysilicon. In various exemplary embodiments, on the surface thereof the further dielectric26can be formed by re-oxidation as an insulation to source contact28.

Negative boundary surface charges may be present at a boundary surface between gate dielectric32and channel region14, or in gate dielectric32itself.

Properties of a FinFET having such a design100are shown inFIGS.2A and2B, and inFIGS.3A through3D.

InFIG.2A, an illustration200shows threshold voltages Vt in FinFETs as a function of a channel doping concentration and of a boundary surface charge.FIG.2Bshows, in a diagram202, switching resistances in FinFETs as a function of a channel doping concentration and of a boundary surface charge.FIG.3Ashows a current density (top) and a cumulative current density (bottom) as a function of a distance from an SiC/oxide boundary surface in a FinFET for the case of p-channel doping and positive boundary surface charge (quadrant I inFIG.2) as the channel is used according to the related art for a TMOSFET.FIG.3Bshows a current density and a cumulative current density as a function of a distance from the SiC/oxide boundary surface in a FinFET for the case of n-channel doping and negative boundary surface charge (quadrant III inFIG.2) according to various exemplary embodiments.FIG.3Cshows the electron mobility, electron density, and conductivity corresponding toFIG.3Aas a function of a distance from the SiC/oxide boundary surface, andFIG.3Dshows the electron mobility, electron density, and conductivity corresponding toFIG.3Bas a function of a distance from a SiC/oxide boundary surface.

The channel resistance can be significantly reduced if a transition takes place from a p-doped inversion channel, as is used according to the related art and is shown at the right inFIG.2AandFIG.2B, and is shown inFIGS.3A and3C, to an n-doped accumulation channel that is shown at the left inFIG.2AandFIG.2B, and is shown inFIG.3BandFIG.3D.

FIG.2Bsymbolically shows a variable of an ON resistor, i.e. for a FinFET in the switched-on state, for a parameter field of channel dopings and boundary surface charges of the FinFET having fins 300 nm wide, and a cell pitch of 800 nm. If, as gate oxide, a silicon dioxide tempered in a nitrogen oxide atmosphere is used (as in the existing art), an inversion channel is formed having a positive boundary surface charge. This corresponds to circle36in the first quadrant (top right) inFIG.2AandFIG.2B. If, instead, an accumulation channel is formed having a positive boundary surface charge (circle34in the fourth quadrant at top left), then the ON resistance is reduced by approximately a factor of two. However, FinFETs having n-channel doping and positive boundary surface charge have a threshold voltage<0 V, as is shown inFIG.2Ain the fourth quadrant at top left. This is connected to the fact that positive boundary surface charges shift the threshold voltage towards smaller values. Through the selection of a gate dielectric or gate dielectric stack, or of a suitable pre- or post-treatment method, a boundary surface channel-semiconductor material/gate dielectric having negative boundary surface charges can be produced, or negative charges can be built into the gate dielectric.

This can have the result that combinations of boundary surface charges and channel dopings can be ascertained that supply both a suitable positive threshold voltage (e.g. 3 V, black line inFIG.2B) and also a lower ON resistance than a FinFET having an SiC/gate dielectric boundary surface according to the existing art. These combinations can be found for example in the second and third quadrants, both for inversion (second quadrant) and for accumulation (third quadrant), e.g. along the black line in the second or third quadrant.

In particular, FinFETs that are to be assigned to the third quadrant, e.g. having parameters that are marked by the two stars38there, have the advantages described above. In the FinFET100according to various exemplary embodiments, the boundary surface charges and the channel doping concentration can be selected according to the simulation results shown in the third quadrant, taking into account the desired threshold voltage, e.g. for 3 V along the black line.

As gate dielectric32, in various exemplary embodiments a wet-oxidated thermal oxide at 1150° C. can be used, post-treated if appropriate with an NO tempering at 1150° C., or a gate dielectric stack made up of SiO2and Si3N4or SiO2and Al2O3can be used.

As mentioned above, a reason for the reduction of the ON resistance is the charge bearer distribution in the channel, and its mobility. This is illustrated on the basis of a comparison of current densities for inversion channels (FIG.3A,FIG.3C) and accumulation channels (FIG.3B,FIG.3D), each having 3 V threshold voltage, in the cross-section of fin14.

While the current density in the inversion channel (FIG.3A,FIG.3C) is carried exclusively in the first 5-10 nm to the SiC/gate oxide boundary surface, i.e. assumes significant values only there, the current distribution in the accumulation channel (FIG.3B,3D) goes much deeper into fin14. There, as can be seen inFIG.3C and3Dat the bottom, the conductivity is significantly higher. There thus results a higher conductivity in the channel that extends almost over the entire fin width wC (seeFIG.1).

Vertical fin field-effect transistor100can in addition have a p-doped gate shielding region16that is situated below gate region24in such a way that, given a vertical projection, the gate shielding region16lies within a surface limited by gate dielectric32at least partly, for example for the most part, almost completely, or completely, e.g. with at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95% of its projected surface. Gate shielding region16can be used to shield gate dielectric32on the trench floor from excessively large electrical fields.

Source contact28can be connected in electrically conductive fashion to source region30, and an electrically conductive region18,20can be situated between gate region24and p-doped gate shielding region16, p-doped gate shielding region16being capable of being electrically conductively connected to source contact28by electrically conductive region18,20.

A second parameter that can influence the channel resistance is the cell distance (pitch) P, a smaller pitch P making the channel resistance smaller.

According to the existing art, a shielding region is typically realized by a deep p-implantation. For this implantation, a relatively thick (e.g. approximately 1.5 μm) oxide mask is required, which limits the smallest opening that can be achieved, and thus limits the pitch P.

In various exemplary embodiments, a production method is provided for a FinFET100having a reduced cell pitch P. In the method, a shielding structure is provided in that the lithography process that limits the cell pitch is not carried out between two trenches; rather, gate shielding region16is formed below the trenches.

In various exemplary embodiments, the same mask can be used for the trench formation and for the shielding implantation. That is, first the trenches are formed, and subsequently a p-doping is implanted into the trenches. In this way, gate shielding region16can be formed underneath the trenches.

This means that, using a simple method, according to various exemplary embodiments gate shielding region16can be formed in self-adjusting fashion in such a way that a base of fin14and corners of the trench are protected.

During the doping process for forming gate shielding region16, it can happen that a p-doped layer is also formed in the trench side walls. In various exemplary embodiments, this can be oxidized away in the subsequent fin formation process, so that no p-doping is left over in the actual fin14. Alternatively, a narrow (e.g. a few 10 nm thick) p-doped zone can be left over on the edge of fin14.

A surface ratio of p-doped gate shielding region16to n-doped spreading region12, their doping concentrations and geometric configuration, and a thickness (depth) of gate shielding region16can be determined by a compromise of shielding (maximum field in gate dielectric32, sufficiently small short-circuit current, and sufficiently high breakdown voltage) and conductivity, with a low (ON resistance) [sic]. In particular, in a specific embodiment spreading region12can have a plurality of different doping concentrations, for example 2·1017cm−3below and around a lower region of shielding region16, and 5·1017cm−3between the shielding regions below fin14, shown inFIG.1as an optional second spreading region12aextending for example up to the dash-dotted line. This can be helpful in order to find a suitable compromise between low switching resistance (high doping between the shielding regions) and high breakdown voltage (low doping underneath the shielding region).

Moreover, in a specific embodiment spreading region12can extend into the lower region of fin14, in particular in the region next to the electrically conductive region18,20that contacts gate shielding region16. Due to a high doping in this region, this region is conductive even when gate24is switched off, and therefore does not have to be switched on by the electrical field of gate24.

In various exemplary embodiments, p-doped gate shielding region16can be connected directly to a source potential (source contact28) through a contact in the floor of the trench, i.e. electrically conductive region18,20. In various exemplary embodiments, electrically conductive region18,20can have a contact layer18(for example nickel-silicide). Contact layer18, or more generally electrically conductive region18,20, can be connected to the source metal through a conductive material (for example a doped, or in situ doped, polysilicon). In various exemplary embodiments, electrically conductive region18,20can be electrically insulated from gate region14by a dielectric layer22. In various exemplary embodiments, dielectric layer22can be an oxide layer that can be formed for example by thermal oxidation of electrically conductive region20, for example in a case in which electrically conductive region20includes polysilicon. In various exemplary embodiments, the connection (not shown) to the source metal can be realized, analogously to a conventional procedure in the gate connection, via a so-called supercell lead out at the end of the cell field.

In various exemplary embodiments, it can be advantageous to keep a leading out of the connection of gate shielding region16to source contact28as short as possible in order to reduce the resistance. This has the advantage that the Joule heating is reduced, and the time constant for charging and discharging the shielding region is kept small. Both of these increase the power efficiency of the component. The latter is advantageous in particular for fast switching of the component. In addition, the current path from source contact28via electrically conductive region20and shielding region16into drift region10represents a diode that, in diode operation, has to carry current. Therefore, for the functioning of this so-called body diode a low resistance, due to a short leading out of the connection of shielding region16, can also be helpful.

In various exemplary embodiments, electrically conductive region18,20can be formed completely of metal, e.g. copper or a copper alloy. In this case, metal layer18,20and gate region24can be separated from one another by a dielectric22that is deposited (e.g. at low temperatures). Metallic layer18,20can be deposited for example according to, or based on, a conventional damascene process. FinFET100, having electrically conductive region18,20, can have increased robustness against high current densities.

In order to achieve still better shielding, and in particular a higher resistance, with high drain voltages, and thus a low short-circuit current, in various exemplary embodiments vertical FinFET100shown inFIG.5can in addition have a trenched p-doped layer56. Trenched p-doped layer56can be in contact with gate shielding region16. In this way, the shielding underneath the trench is made up of gate shielding region16and trenched layer56. In this way, for example an overall depth in the vertical direction of shielding structure16,56of approximately 1 μm can be achieved, in that approximately 500 nm thickness of gate shielding region16and approximately 500 nm thickness of trenched layer56are combined with one another without having to enlarge cell pitch P.

In various exemplary embodiments, in addition a vertical FinFET system can be provided that has a plurality of vertical FinFETs100as described above for various exemplary embodiments. This was already indicated inFIG.1,FIGS.4A through4S, andFIG.5through the plurality of fins14, trenches, etc.

Fins14(and correspondingly also the trenches and the gate shielding regions16formed below the trenches) can be configured parallel to one another. They can have an elongated geometry, and can be configured parallel to one another along their longitudinal axes. Fins14, trenches, and gate shielding regions16can extend in a first direction.

In order to avoid alignment problems between trenched layer56and the structures of FinFETs100, the trenched p-doped region56can have at least one elongated region, e.g. a plurality of elongated regions56parallel to one another, that extend(s) in a second direction different from the first direction. In other words, trenched regions56can be periodically continued in a direction that is different from the direction in which the trenches are periodically continued (see for exampleFIG.5; here the angle between the first direction and the second direction is 90°).

FIGS.4A through4Sshow a schematic illustration of a method for forming a vertical FinFET100according to an exemplary embodiment. Properties of elements and other features here may correspond to those described above with reference to vertical FinFET100.

FIG.4A: First, an n-doped drift region10, an n-doped spreading region12, and an n-doped region (from which fin14is later formed) are provided, e.g. by epitaxy. In various exemplary embodiments, fin14can extend into spreading region12. Appropriate doping concentrations here can be for example 1016cm−3in drift region10, 1017cm−3in spreading region12, and 4·1016cm−3in the channel region in fin14. There subsequently follows a flat n-contact (source region30), e.g. having a doping concentration of e.g. 1019cm−3, which is either implanted into the channel region or is also provided as an epitaxial layer.FIG.4B: subsequently, trenches42are produced by an etching process using a structured mask40(e.g. oxide hard mask), the trenches having widths of approximately 800 nm and a depth of approximately 1.4 μm, which can either extend into spreading region12or stop before it. During the process, a part of mask40can be worn away.FIG.4C: the remaining thickness of approximately 800 nm can be used as an implantation mask, thus enabling a self-adjusting implantation of gate shielding region16through the trench42. An implantation depth in trench42of approximately 500 nm and a doping of 5·1019cm−3can be achieved with a 0° implantation. Subsequently, mask40can be removed, and a contact metal18(for example nickel) can be deposited on the surface and alloyed in (e.g. NiSi contact formation using an established RTA process).

FIG.4D: to form fins14, first a protection for the trench floor can be provided, by producing a structure (FIG.4E) via a Si3N4(reference character44) and polysilicon (reference character46) deposition and polysilicon46back-etching, the structure subsequently permitting a wet etching of the Si3N444, so that Si3N4remains only on the floor of the trench (FIG.4E). The poly-Si46is then also removed (FIG.4F). Now, if the alloyed-in contact metal is oxidizable (e.g. NiSi), through alternating oxidation and oxide etching trench42can be laterally enlarged, so that at the end there remain only fins14between trenches42. If the contact metal is not oxidizable, then the alloyed-in contact metal can be selectively removed, before this step (FIG.4G), selectively to the Si3N4and the wafer material (e.g. SiC), for example by wet etching. Because the Si3N444on the trench floor acts as an oxidation barrier, because it oxidizes significantly more slowly than SiC, contact18on the floor remains protected. The etching of the oxidized regions simultaneously also removes the oxidized p-implanted regions on the wafer surface and on the trench side wall, which are not wanted (FIG.4G,FIG.4H). The Si3N4protection44on the trench floor is subsequently selectively removed, and gate dielectric32is produced (FIG.4I).

The opening for the connection of p-shielding16in turn requires some process steps.FIG.4J,FIG.4K: Si3N4can be deposited in such a way (preferably by PECVD or sputter deposition) that overhangs54result on fins14. This is a conventional method having well-understood process windows (process gases, process gas conducting, process pressure, generator frequency and power) for forming overhangs54close to the surface on free-standing structures having particular aspect ratios. Using directed etching (taking advantage of collimator effects, for example reactive ion etching (RIE) or ion beam etching (IBE)), gate oxide32can then be opened in the floor of trench42(FIG.4L). Alternatively, using a poly-Si mask52, work can be done in trench42in order to modify the aspect ratio of trench42. In this way, the formation of overhangs54can be adapted and the trench side walls can be better protected. In order to expand the contact surface on the floor of the trench, gate oxide32, which is opened only through the access region on the floor of trench42, can be wet-etched temporarily in an optional process (FIG.4Mis grayed out for this reason) until most of the floor, but not yet the side wall, is exposed.

After the Si3N454and, if appropriate, the poly-Si mask52have been removed, contact20to gate shielding region16and gate24, including insulating layers22,26, can be made in trench42(FIGS.4O through4S). This can be done for example using double polysilicon deposition, polysilicon back-etching, polysilicon re-oxidation, or for example using a damascene process. In the end (FIG.4S), front side contact28and a rear side contact are formed. For this purpose, the oxide was previously (FIG.4R) removed above source region30.

FIG.6is a flow diagram600of a method for forming a vertical FinFET according to various exemplary embodiments.

The method can include a formation of a plurality of trenches in an n-doped semiconductor region, in such a way that between each two of the trenches a semiconductor fin is formed having an n-doped channel region that extends (610) between an n-doped drift region and an n-doped source region, a p-doping of semiconductor regions on the floor of each of the trenches for the formation of p-doped shielding regions (620), a formation of a dielectric layer on the side walls of the trenches (630), a situation in the trenches (640) of electrically conductive material that is in electrically conductive contact with the shielding region situated thereunder in each case, and a formation in each trench of a gate region via the electrically conductive material and electrically insulated therefrom (650).