Data input buffer and semiconductor apparatus including the same

A semiconductor apparatus includes a data input buffer configured to generate write data by receiving data that is input through a data input/output unit during a write operation section and configured to generate an output level detection signal by detecting a voltage level of the data I/O unit during a read operation section.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2020-0135318, filed on Oct. 19, 2020, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments may generally relate to a semiconductor circuit, and more particularly, to a data input buffer and a semiconductor apparatus including the same.

2. Related Art

Semiconductor apparatuses include data buffers configured to output data to the outside of the semiconductor apparatuses or input data from the outside of the semiconductor apparatuses.

Characteristics of data output from data buffers may depend on impedance control methods of the data buffers, and thus there is a need for a method for more efficiently and accurately controlling impedance.

SUMMARY

In an embodiment of the present disclosure, a semiconductor apparatus may include: a data input buffer configured to generate write data by receiving data that is input through a data input/output unit during a write operation section of the semiconductor apparatus and configured to generate an output level detection signal by detecting a voltage level of the data I/O unit during a read operation section of the semiconductor apparatus.

In an embodiment of the present disclosure, a semiconductor apparatus may include a data input buffer which includes a first multiplexer configured to select one of a first reference voltage and a second reference voltage based on a data output enable signal and configured to output the selected reference voltage; and a first buffer configured to output write data by comparing a voltage level of a data input/output unit to a voltage level of the reference voltage that is output from the first multiplexer during an activation section of a data input enable signal and configured to output a first output level detection signal by comparing the voltage level of the data I/O unit to the voltage level of the reference voltage that is output from the first multiplexer during an activation section of the data output enable signal.

In an embodiment of the present disclosure, a semiconductor apparatus may include: a data input buffer configured to generate write data by receiving data that is input through a data input/output unit during a write operation section and configured to generate first and second output level detection signals by detecting a voltage level of the data I/O unit during a read operation section; an impedance adjustment circuit configured to perform an impedance adjustment operation that adjusts at least one value of the first and second impedance adjustment signals based on an impedance of an external resistor based on an impedance adjustment command during an initialization section and configured to perform an impedance readjustment operation that readjusts at least one value of the first and second impedance adjustment signals based on the first and second output level detection signals during the read operation section; and a data output buffer configured to output read data through the data I/O unit by driving the read data with an output impedance that is determined based on the first and second impedance adjustment signals.

DETAILED DESCRIPTION

Various embodiments of the present teachings are described in detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments (and intermediate structures). As such, variations from the configurations and shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the described embodiments should not be construed as being limited to the particular configurations and shapes illustrated herein but may include deviations in configurations and shapes which do not depart from the spirit and scope of the present teachings as defined in the appended claims.

The present teachings are described herein with reference to cross-section and/or plan illustrations of idealized embodiments of the present teachings. However, embodiments of the present teachings should not be construed as limiting the present teachings. Although a few embodiments of the present teachings are shown and described, it will be appreciated by those of ordinary skill in the art that changes may be made in these embodiments without departing from the principles and spirit of the present teachings.

Embodiments are provided to a data input buffer capable of improving output data characteristics and a semiconductor apparatus including the same.

FIG.1is a diagram illustrating a configuration of a semiconductor apparatus10according to an embodiment of the present disclosure.

Referring toFIG.1, the semiconductor apparatus10may include a memory region11, a data input/output unit13, an impedance adjustment circuit100, a data input buffer200, and a data output buffer300.

The memory region11may output read data RDATA based on a read command and store write data WDATA input based on a write command. The memory region11may block an input of the write data WDATA to the memory region11according to the read command. The read data RDATA and the write data WDATA may include a plurality of data bits respectively. The data input/output unit13may include a plurality of data input/output pads.

Data input and output between the semiconductor apparatus10and an external system of the semiconductor apparatus10(for example, a memory controller) may be accomplished through the data I/O unit13.

The impedance adjustment circuit100may perform an impedance adjustment operation that adjusts at least one value of first and second impedance adjustment signals PCODE<0:N> and NCODE<0:N> based on an impedance of an external resistor RZQ based on an impedance adjust command ZQC during a first section.

The impedance adjustment circuit100may perform the impedance adjustment operation that adjusts the at least one value of the first and second impedance adjustment signals PCODE<0:N> and NCODE<0:N> based on the impedance adjustment command ZQC during the first section so that an output impedance of the semiconductor apparatus10coincides with the impedance of the external resistor RZQ.

The first section may be determined based on the impedance adjustment command ZQC.

The impedance adjustment section may be included in a separate section from a read operation section and a write operation section of the semiconductor apparatus10, for example, an initialization section.

The impedance adjustment circuit100may perform an impedance readjustment operation that readjusts at least one value of the first and second impedance adjustment signals PCODE<0:N> and NCODE<0:N> based on a data output enable signal DOEN and first and second output level detection signals CDN and CUP during a second section.

The second section may be an activation section of the data output enable signal DOEN and may be included in the read operation section of the semiconductor apparatus10.

The data input buffer200may generate the write data WDATA by receiving data that is input through the data I/O unit13during the write operation section of the semiconductor apparatus10.

The data input buffer200may generate the write data WDATA by receiving the data that is input through the data I/O unit13during an activation section of a data input enable signal DIEN.

The activation section of the data input enable signal DIEN may be included in the write operation section of the semiconductor apparatus10.

The data input buffer200may generate the first and second output level detection signals CDN and CUP by detecting a voltage level of the data I/O unit13during the read operation section of the semiconductor apparatus10.

The data input buffer200may generate the first and second output level detection signals CDN and CUP by detecting the voltage level of the data I/O unit13during the activation section of the data output enable signal DOEN.

An output impedance of the data output buffer300may be varied based on the first and second impedance adjustment signals PCODE<0:N> and NCODE<0:N>, and the data output buffer300may output the read data RDATA through the data I/O unit13by driving the read data RDATA with the output impedance that is determined based on the first and second impedance adjustment signals PCODE<0:N> and NCODE<0:N>.

The data output buffer300may include a plurality of pre-pull-up drivers (PDRVUP)301, a plurality of pre-pull-down drivers (PDRVDN)302, a plurality of main pull-up drivers (MDRVUP)401, and a plurality of main pull-down drivers (MDRVDN)402.

The plurality of pre-pull-up drivers301may generate a pull-up control signal PU<0:M> by driving the read data RDATA based on the first impedance adjustment signal PCODE<0:N>.

The plurality of pre-pull-down drivers302may generate a pull down control signal PD<0:M> by driving the read data RDATA based on the second impedance adjustment signal NCODE<0:N>.

The plurality of main pull-up drivers401may drive the data I/O unit13with an impedance that is determined based on the pull-up control signal PU<0:M>.

The plurality of main pull-down drivers402may drive the data I/O unit13with an impedance that is determined based on the pull-down control signal PD<0:M>.

FIG.2is a diagram illustrating a configuration of the impedance adjustment circuit100ofFIG.1.

Referring toFIG.2, the impedance adjustment circuit100may include a controller101, a timer counter102, and an impedance adjustment signal generator103.

The controller101may generate a plurality of internal commands ZQINIT and ZQOPER, which define the performing of the impedance adjustment operation, in response to the impedance adjustment command ZQC.

According to operation standards of semiconductor memories that are related to impedance adjustment, the impedance adjustment command ZQC may be generated by a combination of control signals, such as a chip enable signal/CS, a row address strobe signal/RAS, a column address strobe signal/CAS, and a write enable signal/WE.

The time counter102may generate an operation control signal CAL_OPER, which sets impedance adjustment operation times corresponding to the plurality of internal commands ZQINIT and ZQOPER, by using a clock signal CLK.

The impedance adjustment signal generator103may operate during a time that is determined by the operation control signal CAL_OPER to generate the first and second impedance adjustment signals PCODE<0:N> and NCODE<0:N>.

The impedance adjustment signal generator103may include a first comparator110, a first counter120, a first adjuster130, a first digital-analog converter (DAC)140, a second comparator150, a second counter160, a second adjuster170, a second DAC180, and a third DAC190.

The first comparator110may compare a first reference voltage VREF1and a voltage of a first node and may output a comparison result during an activation section of the operation control signal CAL_OPER based on the impedance adjustment command ZQC. The first node may be coupled to an external resistor pad ZQ.

The first counter120may adjust the value of the first impedance adjustment signal PCODE<0:N> by performing up/down counting based on an output of the first comparator110.

The first adjuster130may readjust the value of the first impedance adjustment signal PCODE<0:N> based on the data output enable signal DOEN and the first output level detection signal CDN.

The first DAC140may convert the digital code type of the first impedance adjustment signal PCODE<0:N> to an analog voltage level and may apply the analog voltage level to the first node.

The first DAC140may include a resistor and a plurality of PMOS transistors that are coupled between a power voltage VDDQ terminal and one terminal of the resistor, in common. The other terminal of the resistor may be coupled to the external resistor pad ZQ.

The first DAC140may include a circuit configuration in which the plurality of main pull-up drivers401of the data output buffer300are duplicated.

The first DAC140may be coupled to the external resistor RZQ through the external resistor pad ZQ.

The second comparator150may compare the first reference voltage VREF1and a voltage of a second node NA and may output a comparison result during the activation section of the operation control signal CAL_OPER based on the impedance adjustment command ZQC.

The second counter160may adjust the value of the second impedance adjustment signal NCODE<0:N> by performing up/down counting based on an output of the second comparator150.

The second adjuster170may readjust the value of the second impedance adjustment signal NCODE<0:N> based on the data output enable signal DOEN and the second output level detection signal CUP.

The second DAC180may convert the digital code type of the first impedance adjustment signal PCODE<0:N> to an analog voltage level and may apply the analog voltage level to the second node NA.

The second DAC180may include a resistor and a plurality of PMOS transistors that are coupled between the power voltage VDDQ terminal and one terminal of the resistor in common. The other terminal of the resistor may be coupled to the second node NA.

The second DAC180may include a circuit configuration in which the plurality of main pull-up drivers401of the data output buffer300are duplicated.

The third DAC190may convert the digital code type of the second impedance adjustment signal NCODE<0:N> to an analog voltage level and may apply the analog voltage level to the second node NA.

The third DAC190may include a resistor and a plurality of NMOS transistors that are coupled between a ground terminal and one terminal of the resistor in common. The other terminal of the resistor may be coupled to the second node NA.

The third DAC190may include a circuit configuration in which a plurality of main pull-down drivers402of the data output buffer300are duplicated.

FIG.3is a diagram illustrating a configuration of the first adjuster130ofFIG.2.

Referring toFIG.3, the first adjuster130may include a first logic gate131and a plurality of second logic gates132-0to132-N.

The first logic gate131may perform a logic AND operation on the data output enable signal DOEN and the first output level detection signal CDN and may output a logic AND operation result.

The plurality of second logic gates132-0to132-N may perform logic OR operations on signal bits of the first impedance adjustment signal PCODE<0:N> and an output signal of the first logic gate131, bit by bit, and may output logic OR operation results.

When both the data output enable signal DOEN and the first output level detection signal CDN are activation levels, for example, logic high, the first adjuster130may output all the signal bits of the first impedance adjustment signal PCODE<0:N> as logic high, irrespective of the original values of the signal bits of the first impedance adjustment signal PCODE<0:N>.

FIG.4is a diagram illustrating a configuration of the second adjuster170ofFIG.2.

Referring toFIG.4, the second adjuster170may include a first logic gate171and a plurality of second logic gates172-0to172-N.

The first logic gate171may perform a logic AND operation on the data output enable signal DOEN and the second output level detection signal CUP and may output a logic AND operation result.

The plurality of second logic gates172-0to172-N may perform logic OR operations on signal bits of the second impedance adjustment signal NCODE<0:N> and an output signal of the first logic gate171, bit by bit, and may output logic OR operation results.

When the data output enable signal DOEN and the second output level detection signal CUP are activation levels, for example, logic high, the second adjuster170may output all the signal bits of the second impedance adjustment signal NCODE<0:N> as logic high, irrespective of the original values of the signal bits of the second impedance adjustment signal NCODE<0:N>.

FIG.5is a diagram illustrating a configuration of the data input buffer200ofFIG.1.

Referring toFIG.5, the data input circuit200may include a logic gate201, a first multiplexer202, a second multiplexer203, a plurality of buffers204-0-204-k, and first to fourth switches206to209. An embodiment of the present invention according to theFIG.5is a configuration example of a part of the plurality of buffers, for example, a first buffer (204-0) and a second buffer (204-1) to perform an original operation (data write operation) and to perform an additional operation (generating a first and a second output level detection signals CDN, CUP. The rest buffers (204-2-204-K) may perform only the data write operation.

The logic gate201may perform a logic OR operation on the data output enable signal DOEN and the data input enable signal DIEN and may output a logic OR operation result as a data I/O enable signal DIOEN.

The first multiplexer202may select one of the first reference voltage VREF1and a second reference voltage VREF2based on the data output enable signal DOEN and may output the selected reference voltage.

The first multiplexer202may select the first reference voltage VREF1of the first reference voltage VREF1and the second reference voltage VREF2when the data output enable signal DOEN is at a low level and may output the selected first reference voltage VREF1.

The first multiplexer202may select the second reference voltage VREF2of the first reference voltage VREF1and the second reference voltage VREF2when the data output enable signal DOEN is at a high level and may output the selected second reference voltage VREF2.

The second multiplexer203may select one of the first reference voltage VREF1and a third reference voltage VREF3based on the data output enable signal DOEN and may output the selected reference voltage.

For example, the voltage level of the first reference voltage VREF1may be a value that corresponds to a half of the power voltage VDDQ, for example, 0.5 VDDQ.

The voltage level of the second reference voltage VREF2may be at a higher value than the first reference voltage VREF1, for example, 0.65 VDDQ.

The voltage level of the third reference voltage VREF3may be at a lower level than the first reference voltage VREF1, for example, 0.35 VDDQ.

The above-described voltage levels of the first to third reference voltages VREF1to VREF3are exemplary. The voltage levels of the first to third reference voltages VREF1to VREF3may be adjusted within a range that satisfies the condition that the second reference voltage VREF2has a higher voltage level than the first reference voltage VREF1, and the third reference voltage VREF3has a lower voltage level than the first reference voltage VREF1.

The second multiplexer203may select the first reference voltage VREF1of the first reference voltage VREF1and the third reference voltage VREF3when the data output enable signal DOEN is at a low level and may output the selected first reference voltage VREF1.

The second multiplexer203may select the third reference voltage VREF3of the first reference voltage VREF1and the third reference voltage VREF3when the data output enable signal DOEN is at a high level and may output the selected third reference voltage VREF3.

The first buffer204-0may compare the voltage level of the data I/O unit13and a voltage level of an output signal that is output from the first multiplexer202and may perform an operation of outputting a comparison result as the write data WDATA and perform an operation of outputting the comparison result as the first output level detection signal CDN.

During the write operation section (DOEN=L and DIEN=H) of the semiconductor apparatus10, the first buffer204-0may output the write data WDATA with a high level when the voltage level of the data I/O unit13is higher than the first reference voltage VREF1and may output the write data WDATA with a low level when the voltage level of the data I/O unit13is lower than the first reference voltage VREF1.

During the read operation section (DOEN=H and DIEN=L) of the semiconductor apparatus10, the first buffer204-0may output the first output level detection signal CDN with a high level when the voltage level of the data I/O unit13is higher than the second reference voltage VREF2and may output the first output level detection signal CDN with a low level when the voltage level of the data I/O unit13is lower than the second reference voltage VREF2.

The second buffer204-1may compare the voltage level of the output signal that is output from the second multiplexer203and the voltage level of the data I/O unit13and may perform a operation of output a comparison result as the write data WDATA perform a operation of output the comparison result as the second output level detection signal CUP.

During the write operation section (DOEN=L and DIEN=H) of the semiconductor apparatus10, the second buffer204-1may output the write data WDATA with a high level when the voltage level of the data I/O unit13is higher than the first reference voltage VREF1and may output the write data WDATA with a low level when the voltage level of the data I/O unit13is lower than the first reference voltage VREF1.

During the read operation section (DOEN=H and DIEN=L) of the semiconductor apparatus10, the second buffer204-1may output the second output level detection signal CUP with a high level when the voltage level of the third voltage level VREF3is higher than the voltage level of the data I/O unit13and may output the second output level detection signal CUP with a low level when the voltage level of the third voltage level VREF3is lower than the voltage level of the data I/O unit13.

The first switch206may couple or separate a first current path of the first buffer204-0based on the data input enable signal DIEN.

The second switch207may couple or separate a second current path of the first buffer204-0based on the data I/O enable signal DIOEN.

Since both the data input enable signal DIEN and the data I/O enable signal DIOEN have a high level in a data write operation, both the first switch206and the second switch207may turn on.

A current amount when both the first switch206and the second switch207turn on to couple the first current path and the second current path of the first buffer204-0may be equal to the first current amount, for example, a target current amount that is set to be suitable for the data write operation.

In a data read operation, since the data input enable signal DIEN has a low level and the data I/O enable signal DIOEN has a high level, the first switch206may turn off and the second switch207may turn on.

A second current amount when only the second switch207of the first switch206and the second switch207turns on to couple the second current path of the first buffer204-0may be lower than the first current amount.

The first buffer204-0may perform the data write operation, which is an original operation, and an additional operation, which is an output level detection operation for generating the first output level detection signal CDN, which is performed in the data read operation section.

The first buffer204-0may be designed to operate by using the first current amount in the data write operation and may operate by using a second current amount (a relatively small current amount compared to the first current amount) in the output level detection operation.

The third switch208may couple or separate a first current path of the second buffer204-1based on the data input enable signal DIEN.

The fourth switch209may couple or separate a second current path of the second buffer204-1based on the data I/O enable signal DIEON.

Since both the data input enable signal DIEN and the data I/O enable signal DIOEN have a high level in the data write operation, both the third switch208and the fourth switch209may turn on.

A current amount when both the third switch208and the fourth switch209turn on to couple the first current path and the second current path of the second buffer204-1may be equal to the first current amount, for example, the target current amount that is set to be suitable for the data write operation.

In the data read operation, since the data input enable signal DIEN has a low level and the data I/O enable signal DIOEN has a high level, the third switch208may turn off and the fourth switch209may turn on.

A second current amount when only the fourth switch209of the third switch208and the fourth switch209turns on to couple the second current path of the second buffer204-1may be lower than the first current amount.

The second buffer204-1may perform the data write operation, which is an original operation, and an additional operation, which is an output level detection operation for generating the second output level detection signal CUP, which is performed in the data read operation section.

The second buffer204-1may be designed to operate by using the first current amount in the data write operation and may operate by using a relatively small current amount (for example, second current amount) in the output level detection operation.

FIG.6is a diagram illustrating a configuration of the pre-pull-up driver (PDRVUP)301ofFIG.1.

Referring toFIG.6, the pre-pull-up driver301may include a plurality of pre-pull-up driving circuits301-0to301-M.

The plurality of pre-pull-up driving circuits301-0to301-M may generate, respectively, signal bits PU<0> to PU<M> constituting the pull-up control signal PU<0:M> by driving the read data RDATA based on the first impedance adjustment signal PCODE<0:N>.

FIG.7is a diagram illustrating a configuration of a pre-pull-down driver (PDRVDN)302ofFIG.1.

Referring toFIG.7, the pre-pull-down driver302may include a plurality of pre-pull-down driving circuits302-0to302-M.

The plurality of pre-pull-down driving circuits302-0to302-M may generate, respectively, signal bits PD<0> to PD<M> constituting the pull-down control signal PD<0:M> by driving the read data RDATA based on the second impedance adjustment signal NCODE<0:N>.

FIG.8is a diagram illustrating a configuration of a main pull-down driver (MDRVUP)401ofFIG.1.

Referring toFIG.8, the main pull-up driver401may include a plurality of transistors401-0to401-M and a resistor RP.

Source terminals of the plurality of transistors401-0to401-M may be coupled to a power voltage terminal, in common, drain terminals thereof may be coupled to one terminal of the resistor RP, in common, and gates thereof may receive the plurality of signal bits of the pull-up control signal PU<0:M>, bit by bit.

The other terminal of the resistor RP may be coupled to the data I/O unit13.

As the number of signal bits with a high level in the pull-up control signal PU<0:M> is increased, an output impedance of the output buffer300may be increased, and as the number of signal bits with a low level in the pull-up control signals PU<0:M> is increased, the output impedance of the output buffer300may be reduced.

FIG.9is a diagram illustrating a configuration of a main pull-down driver (MDRVDN)402ofFIG.1.

Referring toFIG.9, the main pull-down driver402may include a plurality of transistors402-0to402-M and a resistor RD.

Drain terminals of the plurality of transistors402-0to402-M may be coupled to the data I/O unit13, in common, source terminals thereof may be coupled to one terminal of the resistor RD, in common, and gates thereof may receive the plurality of signal bits of the pull-down control signal PD<0:M>, bit by bit.

The other terminal of the resistor RD may be coupled to a ground terminal.

As the number of signal bits with a high level in the pull-down control signal PD<0:M> is increased, the output impedance of the output buffer300may be increased, and as the number of signal bits with a low level in the pull-down control signal PD<0:M> is increased, the output impedance of the output buffer300may be reduced.

An operation of the semiconductor apparatus10with the above-described configuration according to an embodiment will be described below.

First, an impedance adjustment operation performed during the first section that is included in the initialization process of the semiconductor apparatus10will be described below.

Since both the data input enable signal DIEN and the data output enable signal DOEN have a low level in the initialization process of the semiconductor apparatus10, the operation of the data input buffer200may be stopped.

As the impedance adjustment command ZQC is input in the first section, the operation control signal CAL_OPER may be activated.

Since the operation control signal CAL_OPER is activated, the first and second comparators110and150and the first and second counter120and160may operate.

The impedance adjustment circuit100may adjust the value of the first impedance adjustment signal PCODE<0:N> so that the voltage level to which the digital code type of the first impedance adjustment signal PCODE<0:N> is converted through the first DAC140, for example, the voltage of the first node coincides with the first reference voltage VREF1.

In a state that the first impedance adjustment signal PCODE<0:N> is input to the second DAC180, the impedance adjustment circuit100may adjust the value of the second impedance adjustment signal NCODE<0:N> so that the voltage level to which the digital code type of the second impedance adjustment signal NCODE<0:N> is converted through the third DAC190, for example, the voltage of the second node NA coincides with the first reference voltage VREF1.

The impedance adjustment signals PCODE<0:N> and NCODE<0:N> to which impedance adjustment is completed through the above-described process may be provided to the data output buffer300so that the output impedance of the data output buffer300may coincide with the impedance of the external resistor RZQ.

Next, the data write operation of the semiconductor apparatus10will be described below.

During the write operation section of the semiconductor apparatus10, the impedance adjustment command ZQC might not be input, the operation control signal CAL_OPER may be deactivated, the data input enable signal DIEN may be activated to a high level, and the data output enable signal DOEN may be deactivated to a low level.

Since the operation control signal CAL_OPER is deactivated, operations of the first and second comparators110and150and the first and second counters120and160may be stopped.

Since the data output enable signal DOEN is at a low level, the values of the first and second impedance adjustment signals PCODE<0:N> and NCODE<0:N> may be maintained as values that are adjusted in a previous impedance adjustment operation as described above with reference toFIGS.3and4.

The data input buffer200may generate the write data WDATA by receiving data that is input through the data I/O unit13from a device outside of the semiconductor apparatus10.

Since the data output enable signal DOEN is at a low level, the data input buffer200may generate the write data WDATA by comparing the voltage level of the data I/O unit13and the first reference voltage VREF1.

As described above with reference toFIG.5, since the data input enable signal DIEN is at a high level, the data input buffer200may perform the write data WDATA generation operation by using the first current amount.

Next, the impedance readjustment operation to be performed in the second section that is included in the read operation section of the semiconductor apparatus10will be described below.

During the read operation section of the semiconductor apparatus10, the impedance adjustment command ZQC might not be input, the operation control signal CAL_OPER may be deactivated, the data input enable signal DIEN may be deactivated to a low level, and the data output enable signal DOEN may be activated to a high level.

Since the operation control signal CAL_OPER is deactivated, operations of the first and second comparators110and150and the first and second counters120and160may be stopped.

The data output buffer300may output the read data RDATA through the data I/O pad13by driving the read data RDATA with an output impedance that corresponds to the first and second impedance adjustment signals PCODE<0:N> and NCODE<0:N>.

The data input buffer200may generate the first and second output level detection signals CDN and CUP by performing the output level detection operation.

Since the data output enable signal DOEN is at a high level, the data input buffer200may generate the first and second output level detection signals CDN and CUP by comparing the voltage level of the data I/O unit13with the second reference voltage VREF2and the third reference voltage VREF3.

As described above with reference toFIG.5, since the data input enable signal DIEN is at a low level and the data output enable signal DOEN is at a high level, the data input buffer200may perform the output level detection operation by using the second current amount that is lower than the first current amount.

For example, when the data output enable signal DOEN is at a high level and the first output level detection signal CDN is at a high level, all the signal bits of the first impedance adjustment signal PCODE<0:N> may be changed to logic high, irrespective of the original values of the signal bits of the first impedance adjustment signal PCODE<0:N> as described above with reference toFIG.3.

In this example, the first output level detection signal CDN with a high level means that the voltage level of the data I/O unit13is higher than the second reference voltage VREF2.

Since the second reference voltage VREF2has a higher voltage level than the first reference voltage VREF1that is used as a reference of the impedance adjustment operation, this means that the voltage level of the data I/O unit13has risen as opposed to being at a target level.

Accordingly, the output impedance of the data output buffer300may be increased to match the rise in the voltage level of the data I/O unit13by adjusting the value of the first impedance adjustment signal PCODE<0:N>.

As the number of signal bits of logic high among the signal bits of the first impedance adjustment signal PCODE<0:N> is increased, the number of PMOS transistors which turn off among the PMOS transistors401-0to401-M may be increased as described above with reference toFIG.8and the impedance may be increased.

When the first output level detection signal CDN is at a high level, the second output level detection signal CUP may be a low level. Accordingly, as described above with reference toFIG.4, the value of the second impedance adjustment signal NCODE<0:N> may be maintained as the value determined through the impedance adjustment operation of the initialization process of the semiconductor apparatus10.

For example, when the data output enable signal DOEN is at a high level and the second output level detection signal CUP is at a high level, all the signal bits of the second impedance adjustment signal NCODE<0:N> may be changed to logic high, irrespective of the original values of the signal bits in the second impedance adjustment signal NCODE<0:N> as described above with reference toFIG.4.

For example, the second output level detection signal CUP with a high level means that the voltage level of the data I/O unit13is lower than the third reference voltage VREF3.

Since the third reference voltage VREF3has a lower voltage level than the first reference voltage VREF1that is used as the reference of the impedance adjustment operation, this means that the voltage level of the data I/O unit13is dropped as opposed to being at the target level.

Accordingly, the output impedance of the data output buffer300may be reduced to match the drop in the voltage level of the data I/O unit13by adjusting the value of the second impedance adjustment signal NCODE<0:N>.

As the number of signal bits of logic high among the signal bits of the second impedance adjustment signals NCODE<0:N> is increased, the number of NMOS transistors that turn on among the NMOS transistors402-0to402-M may be increased as described above with reference toFIG.9and the impedance may be reduced.

When the second output level detection signal CUP is at a high level, the first output level detection signal CDN may be at a low level. Accordingly, as described above with reference toFIG.3, the value of the first impedance adjustment signal PCODE<0:N> may be maintained as the value that is determined through the impedance adjustment operation of the initialization process of the semiconductor apparatus10.

The above described embodiments of the present invention are intended to illustrate and not to limit the present invention. Various alternatives and equivalents are possible. The invention is not limited by the embodiments described herein. Nor is the invention limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.