Display device and multi-display system

A display device includes: a video playback unit configured to play video media including multiple frames; a first memory unit configured to store a video signal of the video media that is being played; an acquisition unit configured to acquire a readout control signal representing a readout timing for playing each frame in the video media in a first display device different from an own display device in a multi-display system formed from multiple display devices; a readout control unit configured to cause frames of the video signal corresponding to the readout controls signal to be sequentially read out from the first memory unit in accordance with the acquired readout control signal; and a display control circuit configured to display, on a display unit, the frames of the video signal that have been read out.

TECHNICAL FIELD

The present invention relates to a display device and a multi-display system.

The present application claims priority on the basis of PCT/JP2018/010200, filed Mar. 15, 2018, the disclosure of which is incorporated herein by reference.

BACKGROUND ART

There are multi-display systems in which multiple display devices such as projectors and monitors are used, and a single screen to be displayed is divided between and projected by the respective display devices, thereby constructing a single large screen (see, for example, Patent Document 1). Such display devices are, for example, connected in a daisy chain. Furthermore, a video signal is input to a master display device from a video signal supply device for supplying video content. The master display device supplies the video signal to a slave display device that is connected downstream. This video signal is transmitted sequentially to downstream display devices. Then, the multiple display devices each enlarge and display a target area displayed by own display device, in the video signal, thereby displaying a single video signal by means of multiple display devices.

Additionally, display devices include display devices that have a video playback function for playing video media in addition to the function for receiving and displaying video signals from external sources. In such display devices, it is possible to contemplate storing, as video media, the area of a video signal assigned to each own display device, and displaying the area at the original size. In this case, the video signals can be generated in the respective display devices without being sent through daisy chained signal lines. Thus, the video signals can be prevented from deteriorating. Additionally, there is the merit of not needing to perform an enlargement process.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Problem to be Solved by the Invention

However, when using the screens of the respective display devices forming a multi-display to display a single screen of content, there is the problem that, if video signals are separately played by the video playback functions of the respective display devices, then the display timings in the respective display devices may not be synchronized.

Means for Solving the Problem

According to one aspect of the present invention, a display device includes: a first memory unit configured to store a video signal input from a video playback device; an acquisition unit configured to acquire a readout control signal, indicating a readout timing, output with a period within one frame constituting the video signal, from a first display device different from an own display device in a multi-display system formed from multiple display devices; a readout control unit configured to cause the video signal to be read out from the first memory unit in accordance with the timing; and a display unit configured to display video based on the video signal read out from the first memory unit.

According to one aspect of the present invention, a display device includes: a memory unit configured to store a video signal input from a video playback device; an output unit configured to output, to another display device, with a period within one frame, a readout control signal indicating a timing for reading out a frame constituting a video signal in an own display device in a multi-display system formed from multiple display devices; a readout control unit configured to cause a video signal corresponding to the readout control signal to be read out from the first memory unit in accordance with the readout control signal; and a display unit configured to display the read-out video signal.

According to one aspect of the present invention, a display device includes: a first memory unit configured to store a video signal input from a video playback device; a second memory unit configured to store a video signal corresponding to the video playback device, the video signal being input from a first display device different from an own display device in a multi-display system formed from multiple display devices; a comparison unit configured to compare, frame by frame, the video signal read out from the first memory unit and the video signal read out from the second memory unit; a readout control unit configured to cause the video signal input from the video playback device, stored in the first memory unit, to be read out based on a comparison result in the comparison unit; and a display unit configured to display video based on the video signal read out from the first memory unit.

According to one aspect of the present invention, a multi-display system includes: a first display device having a first memory unit configured to store a video signal input from a video playback device, an output unit configured to output, to another display device, with a period within one frame, a readout control signal indicating a timing for reading out a frame constituting a video signal in an own first display device in the multi-display system formed from multiple display devices, a readout control unit configured to cause a video signal corresponding to the readout control signal to be read out from the first memory unit in accordance with the readout control signal, and a display unit configured to display the read-out video signal; and a second display device having a second memory unit configured to store a video signal corresponding to the video signal input from the first display device, a third memory unit configured to store a video signal input from a video playback device connected to an own second display device, an acquisition unit configured to acquire a readout control signal, indicating a readout timing, output with a period within one frame constituting the video signal, from the first display device, a readout control unit configured to cause a video signal corresponding to the readout control signal to be read out from the third memory unit in accordance with the acquired readout control signal, and a display unit configured to display video based on the video signal read out from the third memory unit.

According to one aspect of the present invention, a display method includes: storing, by a first memory unit, a video signal input from a video playback device; acquiring, by an acquisition unit, a readout control signal, indicating a readout timing, output with a period within one frame constituting the video signal, from a first display device different from an own display device in a multi-display system formed from multiple display devices; causing, by a readout control unit, the video signal to be read out from the first memory unit in accordance with the timing; and displaying, by a display unit, video based on the video signal read out from the first memory unit.

According to one embodiment of the present invention, a display method includes: storing, by a memory unit, a video signal input from a video playback device; outputting, by an output unit, to another display device, with a period within one frame, a readout control signal indicating a timing for reading out a frame constituting a video signal in an own display device in a multi-display system formed from multiple display devices; causing, by a readout control unit, a video signal corresponding to the readout control signal to be read out from the first memory unit in accordance with the readout control signal; and displaying, by a display unit, the read-out video signal.

According to one aspect of the present invention, a display method includes: storing, by a first memory unit, a video signal input from a video playback device; storing, by a second memory unit, a video signal corresponding to the video playback device, the video signal being input from a first display device different from an own display device in a multi-display system formed from multiple display devices; comparing, by a comparison unit, frame by frame, the video signal read out from the first memory unit and the video signal read out from the second memory unit; causing, by a readout control unit, the video signal input from the video playback device stored in the first memory unit to be read out based on a comparison result in the comparison unit.

Advantageous Effects of Invention

According to the present invention, even when video signals are played separately by means of the video playback functions of the respective display devices forming a multi-display, the video signals can be displayed with the display timing synchronized in the respective display devices.

DESCRIPTION OF EMBODIMENTS

Hereinafter, a display system1according to an embodiment of the present invention will be explained with reference to the drawings.FIG.1is a schematic structural diagram illustrating the structure of a multi-display system100according to a first embodiment of the present invention.

The multi-display system100has a display device1, a display device2, a display device3and a display device4that are daisy chained by means of video signal lines. Additionally, in this multi-display system100, a signal source5is connected to the display device1. The signal source5is a device for supplying a video signal and may, for example, be a computer, a video playback device or the like. The signal source5is electrically connected to the display device1by means of a video signal line61. The signal source5outputs video signals to the display device1by means of the video signal line61.

The display device1is connected to the display device2via the video signal line62. The display device2is connected to the display device3via the video signal line63. The display device3is connected to the display device4via the video signal line64.

In this way, the signal source5, the display device1, the display device2, the display device3and the display device4are daisy chained by the video signal line61, the video signal line62, the video signal line63and the video signal line64.

In this case, the display device1, the display device2, the display device3and the display device4are each provided with a media player (hereinafter also referred to as an MP) and a synchronization circuit. The display device1is provided with an MP10and a synchronization circuit15, the display device2is provided with an MP20and a synchronization circuit25, the display device3is provided with an MP30and a synchronization circuit35, and the display device4is provided with an MP40and a synchronization circuit45. The MP10, the MP20, the MP30and the MP40play video media so that a single video is played on the four display screens of the display device1, the display device2, the display device3and the display device4. In this case, when a display image1ais displayed on the display device1, a display image2dis displayed on the display device2, a display image3ais displayed on the display device3, and a display image4ais displayed on the display device4, these display images are combined to be displayed as a single video as illustrated inFIG.2.

Additionally, in this case, when displaying the images as a single video, the timing by which the display images are displayed on the display devices must be synchronized. The synchronization circuit15in the display device1, the synchronization circuit25in the display device2, the synchronization circuit35in the display device3and the synchronization circuit45in the display device4have the function of synchronizing the timing by which the display images are displayed with the other display devices. By synchronizing the display timing in this way, even if different video media are separately played in the respective display devices, they will be displayed so as to form a single video on the entire multi-display system100.

When the video media is played on the MPs (MP10, MP20, MP30and MP40), the signal source5does not need to supply a video signal to the display device1. In this case, the video signal does not need to be supplied from the signal source5to the display device1via the video signal line61. Meanwhile, the video signal line62, the video signal line63and the video signal line64are connected between the respective display devices in order to form the daisy chain connection when constructing the multi-display system100. Thus, the present embodiment makes use of the video signal line62, the video signal line63and the video signal line64.

FIG.3is a schematic functional block diagram for explaining the functions of the display device1.

The MP10plays video media and outputs the played video signal. Video data that is to be generated may be pre-stored in a memory device in the display device1, or video data that is stored in a recording medium may be read out. Additionally, the MP10may perform a function similar to the signal source5.

A selector (hereinafter also referred to as a SEL)11selects either a video signal input from the video signal line61or a video signal output from the MP10, and outputs the selected video signal to the video processing circuit12and also to an output unit18.

Regarding which video signal is to be selected, the SEL11, for example, acquires instructions from an external source regarding whether the content to be displayed is a video signal from the signal source5or a video signal played by the MP10, and selects the video signal in accordance with those instructions. The instructions from the external source may, for example, be from a remote control device or the like of the display device1.

The video processing circuit12implements processing for writing the video signal input from the SEL11into a frame memory unit13. Additionally, the video processing circuit12has a synchronization circuit111. The synchronization circuit111generates various timing signals for writing the video signal into the frame memory unit13based on a horizontal synchronization signal or a vertical synchronization signal in the video signal.

The frame memory unit13stores the video signal that is written from the video processing circuit12and outputs (reads out) the stored video signal to a drive circuit16.

An SEL14selects either the signal supplied from the video signal line61or the signal supplied from the MP10and outputs the selected signal to the synchronization circuit15. In this case, among the display devices in the multi-display system100, if the own display device (display device1) is the display device that is furthest upstream in the daisy chain (the display device that is connected first to the signal source5), then the SEL14selects the video signal output from the MP10, and if it is not the display device that is the furthest upstream, then the SEL14selects the signal output from the video signal line61. In this case, the display device1is the display device that is the furthest upstream in the daisy chain, so the SEL14selects the signal output from the MP10. Regarding whether or not the own display device is the display device that is the furthest upstream, it is possible to use a control signal to detect whether or not there are display devices connected upstream or downstream from the own display device at the time the display devices are daisy chained to form the multi-display system100.

In this case, the video signal obtained from the MP10need only be a signal from which it is possible to recognize the timing by which the MP10is to play the video signal. For example, a timing signal for starting to play a chapter in video media being played by the MP10, a timing signal for displaying a specific frame of a video when playing video media, or the like are may be used.

The synchronization circuit15reads out and outputs a readout control signal for controlling the timing for causing the drive circuit16to read out the video signal from the frame memory unit13, based on the timing signal output from the SEL14. By reading out a video signal of a frame that is to be read out (a frame that is to be displayed) at a timing in accordance with the timing signal, the synchronization circuit15can supply the video signal from the frame memory unit13to the drive circuit16at a timing in accordance with the readout control signal.

For example, the synchronization circuit15generates a readout control signal representing the timing by which a video signal is to be read out from the frame memory unit13based on a horizontal synchronization signal or a vertical synchronization signal in the video signal, and outputs the readout control signal to the frame memory unit13. As this readout control signal, a synchronization signal contained in the video signal may be used. The synchronization signal is a signal representing the timing at which each frame of video media is to be read out. For example, the synchronization signal represents the timing by which each frame of video media is to be sequentially read out at regular intervals.

The drive circuit16causes a display device unit17to display a video signal that has been read out from the frame memory unit13in accordance with the readout control signal. For example, the drive circuit16causes the display device unit17to draw a video signal by driving the display element of each pixel in the display device unit17.

The output unit18selects either the video signal input from the SEL11or the video signal input from the video signal line61and outputs the selected signal to a downstream display device (display device2) through the video signal line62. When the SEL11selects the video signal from the signal source5(when the content to be displayed is the video signal from the signal source5), the output unit18selects the video signal input from the video signal line61, and when the content to be displayed is the video signal played by the MP10, the output unit18selects the video signal input from the SEL11. The video signal line62is connected to the output terminal of the output unit18. Thus, the output unit18can output, to a display device that is connected downstream, via the daisy chained video signal line, a readout control signal representing the playback timing (for example, the display timing for displaying the video signal of the video media) for playing the video media on the own display device.

Next,FIG.4is a schematic functional block diagram for explaining the functions of the display device2. Some of the functions of the display device2are the same as the functions in the display device1. The explanations of the same parts will be omitted and the differences will mainly be explained.

The MP20plays video media and outputs the video signal being played.

An SEL21selects either a video signal input from the video signal line62or the video signal input from the MP20, and outputs the selected video signal to a video processing circuit22and also to an output unit28.

Regarding which video signal is to be selected, for example, the SEL21acquires, from an external source, instructions regarding whether the content to be displayed is the video signal from the signal source5or the video signal played by the MP20, and selects the video signal in accordance with those instructions. The instructions from the external source may, for example, be from a remote control device or the like of the display device1.

A video processing circuit22implements processing for writing the video signal input from the SEL21into a frame memory unit23. Additionally, the video processing circuit22has a synchronization circuit211. The synchronization circuit211generates various timing signals for writing the video signal into the frame memory unit13based on a horizontal synchronization signal or a vertical synchronization signal in the video signal.

The frame memory unit23stores video signals that are written from the video processing circuit12, and outputs (reads out) the stored video signals to a drive circuit26. Here, the case in which the video processing circuit22writes a video signal into the frame memory unit33will be explained, but it is also possible for another functional unit (for example, a writing unit) to write a video signal output from the video processing circuit22into the frame memory unit23.

The SEL24selects either the video signal supplied from the video signal line62or the video signal supplied from the MP20and outputs the selected signal to the synchronization circuit25. Here, among the display devices in the multi-display system100, if the own display device (display device2) is the display device that is furthest upstream in the daisy chain, then the SEL24selects the signal output from the MP20, and if it is not the display device that is the furthest upstream, then the SEL24selects the signal supplied from the video signal line62. In this case, the display device2is not the display device that is furthest upstream in the daisy chain, so the SEL24selects the video signal supplied from the video signal line62.

In this case, the video signal obtained through the video signal line62is the video signal output from the output unit of the display device (the display device1in the present case) that is connected upstream.

The synchronization circuit25generates a readout control signal representing the timing by which the video signal is to be read out from the frame memory unit13based on a horizontal synchronization signal or a vertical synchronization signal in the video signal output from the SEL24, and outputs the readout control signal to the frame memory unit23. As a result thereof, the video signal can be supplied from the frame memory unit23to the drive circuit26at a timing in accordance with the readout control signal.

In this case, the video signal of the video media played by the MP20is temporarily stored in the frame memory unit23, and the timing by which the video signal is read out follows the readout control signal from the synchronization circuit25, in other words, the readout control signal obtained from the display device connected upstream from the own display device. Thus, the video signal can be read out from the frame memory unit and displayed on the display device unit in the own display device in synchronization with the timing by which a display device that is connected upstream reads out a video signal from a frame memory unit and displays the video signal on a display device unit.

Additionally, in this case, a synchronization signal included in a video signal played on an MP in the display device that is furthest upstream stage in the daisy chain can be supplied to the display devices connected to a stage subsequent to a second stage. Thus, by using, as a readout control signal, a synchronization signal included in the same video signal in the display device that is furthest upstream and in the display devices further downstream than the second display device, the display timings in the respective display devices can be synchronized.

The drive circuit26displays, on a display device unit27, a video signal that has been read out from the frame memory unit23in accordance with the readout control signal. The display device unit27displays the video signal.

The output unit28selects either the video signal input from the SEL21or the video signal input from the video signal line62and outputs the selected signal to a downstream display device (the display device3in this case) through the video signal line63. When the SEL21selects the video signal from the signal source5(when the content to be displayed is the video signal from the signal source5), the output unit28selects the video signal input from the SEL21, and when the content to be displayed is the video signal played by the MP20, the output unit28selects the video signal input from the video signal line62. The video signal line63is connected to the output terminal of the output unit28. Thus, the output unit28can output, to display devices that are connected downstream, via the daisy chained video signal lines, the video signal obtained from the display device that is connected upstream.

By having this output unit28, in accordance with whether or not the own display device is the display device that is furthest upstream among the multiple daisy chained display devices, it is possible to output, to a downstream display device, either a video signal from the signal source5or the video signal played by the MP in the display device that is furthest upstream. Additionally, by using the output unit28, it is possible to make use of the video signal lines to supply the video signal being played by the MP in the display device that is furthest upstream to each of the display devices connected further downstream than the third display device.

Next, the structures of the display device3and the display device4are similar to the structure of the display device2. Regarding the display device4, a display device is not connected downstream therefrom. Thus, a display device is not connected to the output terminal of the selector of the display device4.

Additionally, according to the above-described structures, all of the display devices have the same structures in terms of the MP, the two SELs, the output unit, the video processing circuit, the synchronization circuit, the frame memory unit, the drive circuit and the display device unit provided in the display device. For this reason, as long as an instruction is obtained as to whether the video signal from the signal source5is to be displayed or the video signal from the MP is to be displayed, the signal can be appropriately selected by the SELs in accordance with whether or not the own display device is the display device that is furthest upstream in the daisy chain. Thus, by preparing and daisy chaining multiple display devices as inFIG.3orFIG.4, it is possible to obtain functions in accordance with whether or not a display device is the display device that is furthest upstream, without performing any special processes.

Next, the operations of the display device will be explained.FIG.5is a flow chart for explaining the operations in the display device.

Each display device, for example, selects a video signal in accordance with instructions from an external device such as a remote control device or an input switching button or the like provided in the display device (step S101). In this case, the video signal from the MP is selected.

Each MP outputs a video signal to the video processing circuit by playing video media (step S102). The video processing circuit writes the video signal into the frame memory unit (step S103).

Meanwhile, the SEL selects either a signal supplied from a video signal line or the signal supplied from the MP (step S104). In this case, if the own display device is the display device that is furthest upstream, then the SEL14selects the signal output from the MP10. If the own display device is not the display device that is furthest upstream, for example, if the own display device is the display device2, then the SEL24selects the video signal supplied from the video signal line61.

In step S104, when the signal is selected by the SEL, the synchronization circuit (15,25,35,45) generates a readout control signal based on the video signal supplied from the SEL connected upstream with respect to the own display device, and outputs the readout control signal to the frame memory unit (step S105).

The output unit outputs the video signal to a downstream display device (step S106). In this case, the video signal to be displayed in each display device is the video signal supplied from the MP. Thus, the output unit of the display device that is furthest upstream outputs the video signal played by the MP10to a downstream display device, and the display devices further downstream than the second display device select the video signal played by the MP of the display device that is furthest upstream, which has arrived via the video signal lines, and outputs the video signal to downstream display devices via the video signal lines.

Meanwhile, the synchronization circuit generates a readout control signal based on the video signal obtained from the SEL and outputs the readout control signal to the frame memory unit, thereby causing the video signal to be read out from the frame memory unit (step S107). The drive circuit displays the video signal that has been read out on a display device unit (step S108).

According to the embodiment explained above, a readout control signal used in the display device1is also commonly used by the display device2, the display device3and the display device4other than the display device1. Thus, even when video media is played by the MPs in each of the display devices, the display of the video signals can be synchronized. Additionally, when synchronizing the display of the video signals, the daisy chained signal lines (video signal lines) are used, so there is no need to provide special lines for synchronization in addition to the daisy chained signal lines. Additionally, while the video media is being played by the MP, there is no need for the video signal lines to transmit the video signal from the signal source5, so they can be used for transmitting the readout control signals.

Additionally, in the display devices further downstream than the second display device, when a synchronization signal from the video signal of the display device that is furthest upstream in the daisy chain is obtained, it is preferably within the range of the deviation in the playback timing within a single frame in the video signal of the video media being played in each display device.

FIG.6is a schematic block diagram representing the structure of the display device1aaccording to a second embodiment. The display device1adiffers from the display device1in the first embodiment in that it further has a real-time clock (hereinafter referred to as an RTC)19. The RTC19has the function of generating time information. Additionally, the RTC19instructs the MP10regarding the timing for outputting the video signal based on a readout control signal obtained from the synchronization circuit15and the generated time information. On the basis thereof, the MP10outputs a video signal in accordance with the timing obtained from the RTC19. In this case, each of the display devices connected further downstream than the second display device have the same function as the RTC19. Thus, by synchronizing the times in the multiple display devices, it is possible to synchronize or to bring, closer together, the timings by which the video signals are output by the MPs provided in the own display devices. As a result thereof, large deviations in the timings for playing video signals can be reduced in the respective display devices, thereby allowing the amounts of video signals collected in the frame memory units to be reduced. As a result thereof, it is possible to reduce the required capacity of the frame memory units.

As the readout control signal, it is possible to use not only the readout control signal of the display device that is furthest upstream, but also a readout control signal of an external signal source5. For example, as the readout control signal obtained from the external source, it is possible to use time information obtained by NTP (network time protocol). By sharing such time information between the display devices, the timing by which video media is played by the MP in each display device can be synchronized. As a result thereof, it is possible to reduce the capacity of the frame memory unit.

FIG.7is a schematic block diagram representing the functions of the display device1bin a third embodiment.

A video playback unit10bplays video media. A memory unit13bstores video signals of video media that is to be played. An acquisition unit14bacquires a readout control signal representing the playback timing of the video media in a first display device different from the own display device in a multi-display system formed from multiple display devices. The readout control unit15bcauses the video signals from the memory unit13bto be read in accordance with the acquired readout control signal. The display control circuit16causes the display unit17bto display the read-out video signals.

FIG.8is a schematic block diagram representing the functions of the display device1cin a fourth embodiment.

A video playback unit10cplays video media.

A memory unit13cstores video signals of video media that is being played.

An output unit18coutputs, to other display devices, a readout control signal representing the playback timing by which video media is to be played in a own display device in a multi-display system formed from multiple display devices. The readout control unit15ccauses video signals to be read out from the memory unit in accordance with the readout control signal. The display control circuit16ccauses the display unit17cto display the read-out video signals.

In this case, a multi-display system may be constructed by daisy chaining at least one display device1baccording to the third embodiment downstream from a display device1caccording the fourth embodiment.

FIG.9is a schematic block diagram representing the functions of the display device1din a fifth embodiment. Some of the functions of this display device1dare the same as the functions in the display device1illustrated inFIG.3. The parts that are the same will be assigned the same reference numbers as those inFIG.3, their explanations will be omitted, and the explanation will mainly focus on the differences.

A control unit101controls the units in the display device1d. For example, when synchronizing the display timings in the display devices in the multi-display, the control unit101plays a test video signal, which is a display-synchronizing video signal, by means of an MP10. In this embodiment, by playing the test video signal in the display device1d, it is possible to use the test signal in downstream display devices and generate readout control signals by means of a control signal generation unit.

This test video signal may be stored in an internal memory in the MP10, may be stored in an internal memory in the control unit101, or may be supplied from a signal source5via a video signal line61. In this embodiment, as one example, the case in which the test video signal is stored in the MP10will be explained.

Additionally, the test video signal is a video signal including multiple frames, and the number of frames is within a predetermined number. Additionally, this test video signal is a video signal in which the display content is different in each frame.

Additionally, when the test video signal is played by the MP10, the control unit101outputs, to a drive circuit16a, an instruction that this test video signal should not be displayed.

When an instruction indicating that the test video signal should not be displayed is input from the control unit101, the drive circuit16adoes not display the frames of the test video signal on the display device unit17. In other words, the drive circuit16adoes not display the test video signal even if frame data of the test video signal is output from a frame memory unit13.

An output unit18ais connected, via a video signal line62, to a downstream display device (in this case, the display device2d). As this video signal line62, it is possible to use a communication cable that can transmit at least a video signal and a control signal. The video signal line62may, for example, utilize a communication cable compliant with standards such as DisplayPort or HDMI (registered trademark). In this embodiment, the display devices are connected by means of communication cables similar to the video signal line62.

By using this communication cable, in the multi-display, an upstream-side display device can supply a video signal and a control signal to a display device that is connected downstream.

In this case, when playing the test video signal, the control unit101outputs the test video signal from the MP10and outputs a control signal indicating that the video signal being played is a test signal. Thus, when the video signal from the MP10is selected by the SEL11, a control signal is supplied to the output unit18atogether with the test video signal output from the MP10, and the output unit18aoutputs, to a downstream display device, the test video signal and the control signal indicating that the video signal being played is a test signal.

Additionally, the test video signal may be supplied from the signal source5.

FIG.10is a schematic block diagram representing the functions of the display device2din the fifth embodiment. Some of the functions of this display device2dare the same as the functions in the display device2illustrated inFIG.4. The parts that are the same will be assigned the same reference numbers as those inFIG.4, their explanations will be omitted, and the explanation will mainly focus on the differences.

A writing unit32is electrically connected to a video signal line63, receives a video signal output from an output unit28, and writes this video signal into a frame memory unit33.

The frame memory unit33stores the video signal that is written by the writing unit32.

A difference computation unit34determines the difference between a video signal frame stored in either the frame memory unit23or the frame memory unit33and a video signal frame stored in the other memory unit for multiple cases while changing the playback timing of the frames in the video signal stored in one of the memory units relative to the playback timing of the frames in the video signal stored in the other memory unit.

When determining the difference, the difference computation unit34may determine the difference by a method of determining how much the frame of the video signal stored in the frame memory unit33differs from the frame of the video signal stored in the frame memory unit23, or of determining how much the frame of the video signal stored in the frame memory unit23differs from the frame of the video signal stored in the frame memory unit33.

A summation unit35determines the sum of the differences computed by the difference computation unit34.

A control signal generation unit36generates a readout control signal for the video signal stored in the frame memory unit23on the basis of the sum computed by the summation unit35. The control signal generation unit36supplies the generated readout control signal to the synchronization circuit25a.

Additionally, the control signal generation unit36may, instead of supplying the generated readout control signal to the synchronization circuit25a, supply the readout control signal to another unit.

For example, the control signal generation unit36may generate a readout control signal for the video signal stored in the frame memory unit23based on the sum computed by the summation unit35, and may supply the generated readout control signal to the MP20. In this case, the MP20changes (sets) the timing at which the video signal is output, based on the readout control signal supplied from the control signal generation unit36, so that the difference in the display timing is within a single frame.

Additionally, for example, the control signal generation unit36generates a readout control signal for the video signal stored in the frame memory unit23based on the sum computed by the summation unit35, and can supply the generated readout control signal to the video processing circuit22or a synchronization circuit221. In this case, the video processing circuit22or the synchronization circuit221to which the readout control signal has been supplied changes the timing of writing into the frame memory unit23so that the difference in the display timing is within a single frame. In this case, a frame memory unit is provided inside the video processing circuit22. Then, a video signal obtained from the SEL21is temporarily stored in the frame memory unit inside the video processing circuit22, and in accordance with the timing by which the readout control signal is supplied, the video processing circuit22or the synchronization circuit221writes the temporarily stored video signal into the frame memory unit23at a timing such that the difference in the display timing is within a single frame.

The synchronization circuit25ahas the function of a synchronization circuit25, and also has the function of supplying, to a frame memory unit23, a readout control signal generated by the control signal generation unit36. Thus, the synchronization circuit25acan cause a frame of the video signal, corresponding to the readout control signal generated by the control signal generation unit36, to be read.

The control unit201controls the units in the display device2d. For example, the control unit201determines whether or not the video signal input from the video signal line63is a test video signal. For example, the control unit201can determine whether or not the video signal is a test video signal by determining whether or not it contains a control signal indicating that a test video signal is to be played.

If it is determined that the video signal is a test video signal, then the control unit201outputs, to the drive circuit26a, instructions indicating that the video signal should not be displayed. If it is determined that the video signal is not a test video signal, then the control unit201does not output instructions indicating that the video signal should not be displayed.

The drive circuit26adoes not display the frames of a test video signal on the display device unit27. In other words, the drive circuit26abecomes non-displaying for the test video signal when an instruction indicating that a video signal should not be displayed is input from the control unit201. For example, if an instruction indicating that the video signal from the control unit201should not be displayed is input, then the drive circuit26amay become non-displaying by suspending the output of the drive signal to the display device unit17.

Additionally, when an instruction that the video signal should be not displayed is not input from the control unit201, the drive circuit26adisplays the video signal on the display device unit27. Thus, the drive circuit26adoes not display, on the display device unit27, frames that are used by the control signal generation unit36to generate the readout control signal.

Additionally, the drive circuit26amay display a fixed video signal on the display device unit27when an instruction indicating that a video signal should not be displayed is input from the control unit201. The fixed video signal may, for example, be a video signal for displaying the entire screen in a specific color. The specific color may be black or white. When displaying the fixed video signal, the drive circuit26adisplays the fixed signal regardless of the video signal being read out from the frame memory unit.

Additionally, the drive circuit26amay mute the display of the video signal when an instruction indicating that the video signal should not be displayed is input from the control unit201.

FIG.11is a flow chart for explaining the operations in the display device1inFIG.9.

The SEL11selects a video signal to input (step S201). In this case, the SEL11selects the video signal supplied from the MP10.

Next, when a command to output a video signal from the MP10is issued by a remote control device of the display device1dor a scheduling function provided in the display device1d(step S202), the control unit101acquires said command. Upon acquiring this command, the control unit101outputs, to the MP10, instructions to play the test video signal, and outputs, to the drive circuit16a, instructions indicating that the drive circuit16ashould not display the video signal.

Upon acquiring the test video signal playback instruction from the control unit101, the MP10outputs the test video signal, as a display-synchronizing video signal, for a standard time (step S203). The SEL11selects the test video signal supplied from the MP10. In this case, the number of frames included in the test video signal is predetermined. Thus, by playing the test video signal that is to be played, the test video signal can be output, via the SEL11, to the video processing circuit12and the output unit18afor a standard time.

The output unit18aoutputs the test video signal obtained from the SEL11to a downstream display device (in this case, the display device2d) via the video signal line62. Due to the test video signal being output from the output unit18a, the display device2dcan determine the timing by which the frames of video signals are to be displayed by using the synchronization signal in this test video signal.

When the test video signal is input from the SEL11, the video processing circuit12uses the synchronization signal contained in the test video signal to generate a video signal for each frame in accordance with a timing corresponding to this synchronization signal, and writes the video signal into the frame memory unit13(step S204). This synchronization signal is a signal representing the timing by which it is possible to generate a first frame image based, for example, on a horizontal synchronization signal or a vertical synchronization signal. For example, the synchronization signal is a signal representing the timing by which each frame of video media is to be read out. Additionally, the synchronization signal represents the timing by which each frame of the video media is sequentially read out at fixed intervals.

On the other hand, the SEL14selects the test video signal output from the MP10and outputs the test video signal to the synchronization circuit15.

When the test video signal is input from the SEL14, the synchronization circuit15generates a readout control signal representing the timing by which the video signal is to be read out from the frame memory unit13based on a timing in accordance with a horizontal synchronization signal or a vertical synchronization signal in this test video signal (step S205).

The frame memory unit13outputs, frame by frame, a video signal stored in that frame memory unit13in accordance with the readout control signal output from the synchronization circuit15(step S206).

The drive circuit16ahas received, as an input, an instruction indicating that the video signal from the control unit101should not be displayed, and thus does not cause to be displayed, on the display device unit17, frames that are output from the frame memory unit13while this instruction is being input.

On the other hand, when the output of the test video signal ends, the MP10outputs a video signal that is to be actually displayed on the display device unit17(step S207). By a timing at which the video signal being played by the MP10switches from the test video signal to the video signal that is to be actually displayed on the display device unit17, the control unit101suspends the outputting, to the drive circuit16a, of instructions indicating that the video signal should not be displayed. Thus, the video signal is written into the frame memory unit13by the video processing circuit12. Additionally, when the video signal that is to be actually displayed on the display device unit17is supplied from the SEL14, the synchronization circuit15generates a readout control signal indicating the timing for reading out the video signal from the frame memory unit13based on a timing in accordance with a horizontal synchronization signal or a vertical synchronization signal in this video signal.

The frame memory unit13outputs, frame by frame, a video signal stored in that frame memory unit13based on the readout control signal output from the synchronization circuit15. The drive circuit16adisplays, on the display device unit17, the video signal of each frame output from the frame memory unit13(step S208).

Thereafter, the procedure from step S204to step S208is repeated, thereby the video signal is displayed on the display device unit17.

Thus, while the test video signal is being played, the test video signal is not displayed on the display device unit17, and when the video signal switches from the test video signal to the video signal that is to be actually displayed, the video signal is displayed on the display device unit17.

Next, the operations in the display device2dwill be explained by using the flow chart inFIG.12.

The SEL21selects a video signal to input (step S301). In this case, the SEL21selects the video signal supplied from the MP20.

Next, when a command to output a video signal from the MP20is issued by a remote control device of the display device2dor a scheduling function provided in the display device2d(step S302), the MP20acquires said command and outputs the test video signal for a standard time in accordance with this command (step S303). Additionally, the summation unit35resets the summation result. This reset may be performed at the timing of step S303, or at the timing the command to output the video signal is issued in step S302.

Additionally, in this case, the number of frames included in the test video signal is predetermined. Thus, by playing the test video signal that is to be played, the test video signal can be output, via the SEL21, to the video processing circuit22and the output unit28for a standard time.

The output unit28outputs the test video signal via the video signal line63. The test video signal output from the output unit28is supplied to the frame memory unit33, the control unit201, and a downstream display device. The frame memory unit33stores a test video signal output from the output unit28. In this case, the storage capacity of the frame memory unit33is a capacity allowing the respective frames of the test video signal to be stored. For example, if the test video signal is a video signal that is five frames long, then the frame memory unit33has enough storage area to store five frames of a video signal. The number of frames of a video signal contained in the test video signal may be set in accordance with the number of frames that can be stored in the frame memory unit33.

The control unit201determines whether or not the video signal output from the output unit28is a test video signal. In this case, the control unit201determines that the video signal output from the output unit28is a test video signal, and outputs, to the drive circuit26a, instructions indicating that a video signal should not be displayed. As a result thereof, after the test video signal is output from the output unit28, the drive circuit26adoes not display the video signal on the display device unit17until a video signal that is not a test video signal (a video signal that is to be actually displayed) is output from the output unit28. Thus, the test video signal can be kept from being displayed on the display device unit17while the test video signal is used to generate a synchronization signal.

When the test video signal is input from the SEL21, the video processing circuit22uses the synchronization signal contained in the test video signal to generate a video signal for each frame in accordance with a timing corresponding to this synchronization signal, and writes the video signal into the frame memory unit23(step S304). This synchronization signal is, for example, a signal representing the timing by which it is possible to generate a single frame image, based on a horizontal synchronization signal or a vertical synchronization signal. In this case, the storage capacity of the frame memory unit23is a capacity allowing the respective frames of the test video signal to be stored. For example, if the test video signal is a video signal that is five frames long, then the frame memory unit23has a storage area capable of storing five frames of a video signal. The number of frames of a video signal included in the test video signal may be set in accordance with the number of frames that can be stored in the frame memory unit23.

The SEL24selects the video signal supplied from the video signal line62and supplies the video signal to the synchronization circuit25a. In this case, the test video signal is supplied from the SEL24to the synchronization circuit25a. The synchronization circuit25agenerates a readout control signal representing the timing by which the video signal is to be read out from the frame memory unit23based on the timing of a horizontal synchronization signal or a vertical synchronization signal in the video signal obtained from the SEL24(step S305).

The frame memory unit23outputs, frame by frame, a video signal stored in that frame memory unit23in accordance with the readout control signal output from the synchronization circuit25a(step S306). The video signal of each frame is supplied to the drive circuit26aand the difference computation unit34.

Meanwhile, when the video signal of each frame is supplied form the frame memory unit23, the difference computation unit34computes the difference between the video signal of each frame stored in the frame memory unit33and the video signal of each frame supplied from the frame memory unit23. The summation unit35sums the obtained differences and stores the summation results (step S307).

Furthermore, the difference computation unit34repeatedly performs the procedure from step S303to step S307. In this case, each time the difference computation unit34repeats the procedure from step S303to step S307, it generates a readout control signal in which the readout from the frame memory unit23in step S305is delayed by one frame relative to the previous time (step S308). The summation unit35computes the sum value each time the procedure from step S303to step S307is performed, and stores each computed sum value.

The difference computation unit34determines the number of times that the procedure from step S303to step S307is to be repeatedly performed in accordance with the number of frames in the test video signal stored in the frame memory unit23, and repeatedly performs the procedure in accordance with the determined number of times (step S309). In this case, there are five frames in the test video signal, and the frame memory unit23stores a video signal that is five frames long. Thus, the procedure is repeated five times. As a result thereof, for example, when step S308is performed five times, the sum of the differences is determined after generating a readout control signal at a timing delayed by five frames.

For example, the relationship between the frame memory unit23and the frame memory unit33when executing step S307for the first time is shown inFIG.13A. When executing step S307for the second time, as illustrated inFIG.13B, the differences between the frames in the frame memory unit23and the frame memory unit33are determined for the case in which the frames in the frame memory unit23are played at a timing that is delayed, relative to the frames in the frame memory unit33, by the time of one frame with respect to the playback timing of the frames in the frame memory unit23during the previous time (first time).

Similarly, the third and fourth times that the procedure is performed, the differences between the frames in the frame memory unit23and the frame memory unit33are determined for the cases in which the frames are played at a timing that is further delayed, respectively, by a time equivalent to one frame in the video signal in the frame memory unit23.

Furthermore, the relationship between the frame memory unit23and the frame memory unit33when step S307is performed for the fifth time is illustrated inFIG.13C.

Thus, the summation unit35determines the difference sum values (d1a, d2a, d3a, d4aand d5a) for the cases in which step S307is performed for the first to the fifth times.

When there is a frame in the frame memory unit33corresponding to the playback time of a frame in the frame memory unit23, the differences may be determined between the corresponding frames. If there is no frame in the frame memory unit33corresponding to the playback time of a frame in the frame memory unit23, then it can be determined that there is a time difference of at least six frames, and it is possible to not use this playback timing to generate a readout control signal.

Next, the difference computation unit34returns the readout control signal for reading the frame memory unit23to the first timing, and after doing so, delays the readout from the frame memory unit33by one frame, computes the difference between the video signal of each frame stored in the frame memory unit33and the video signal of each frame supplied from the frame memory unit23, and determines the difference obtained each time there is a difference. The summation unit35determines the difference sum values and stores the summation results (step S310).

Furthermore, the difference computation unit34repeatedly performs the difference sum value computation process. This difference sum value computation process is similar to the process from step S303to step S307above. In this case, the difference computation unit34does not change the readout control signal in step S305and performs the difference sum value computation process by delaying the readout control signal for the frame memory unit33by one frame relative to the previous time (step S311).

The difference computation unit34repeatedly performs the difference sum value computation process in accordance with the number of frames of the test video signal stored in the frame memory unit33(step S312). In this case, the process is repeated one less time than the number of frames stored in the frame memory unit33. More specifically, if there are five test video signal frames stored in the frame memory unit33, then the process is repeated four times. As a result thereof, for example, when step S308is performed four times, the difference summation is computed after generating a readout control signal at a timing delayed by four frames.

For example, the relationship between the frame memory unit23and the frame memory unit33when executing step S310for the first time is shown inFIG.14A. When executing step S310for the second time, as illustrated inFIG.14B, the differences between the frames in the frame memory unit23and the frame memory unit33are determined for the case in which the frames in the frame memory unit33are played at a timing that is delayed, with reference to the frames in the frame memory unit23, by the time of one frame with respect to the playback timing of the frames in the frame memory unit23during the previous time (first time).

Similarly, the third time the procedure is performed, the differences between the frames in the frame memory unit23and the frame memory unit33are determined for the case in which the frames are played at a timing that is delayed by a time equivalent to a frame in the video signal in the frame memory unit23.

Furthermore, the relationship between the frame memory unit23and the frame memory unit33when step S310is performed for the fourth time is illustrated inFIG.14C.

Thus, the summation unit35determines the difference sum values (d2b, d2b, d3band d4b(no corresponding frame)) for the cases in which step S307is performed for the first to the fifth times.

Additionally, the difference determined in step S310may be determined, in the case in which there is a frame in the frame memory unit33corresponding to the playback time of a frame in the frame memory unit23, as the difference between the corresponding frames. If there is no frame in the frame memory unit33corresponding to the playback time of a frame in the frame memory unit23, then it can be determined that there is a time difference of six frames or more, and it is possible to not use this playback timing to generate a readout control signal.

Additionally, if there is no frame in the frame memory unit33corresponding to the playback time of a frame in the frame memory unit23, then the difference computation unit34may determine the difference by using, as the frame in the frame memory unit33, a prescribed frame such that the difference becomes greater than the difference between frames when there is a frame in the frame memory unit33corresponding to the playback time of a frame in the frame memory unit23. As the prescribed frame, for example, it is possible to use a frame in which black is displayed in the entire area (an all-black frame).

Additionally, if there is no frame in the frame memory unit33corresponding to the playback time of a frame in the frame memory unit23, then the difference computation unit34may detect that there is no corresponding frame, and may output information indicating a difference greater than the difference between frames when there is a frame in the frame memory unit33corresponding to the playback time of a frame in the frame memory unit23.

Next, the frame memory unit33returns the readout control signal for reading out video signals recorded in that frame memory unit33to the timing for the first time (step S313). The timing for the first time refers to the timing of the readout control signal when step S310is first executed.

The summation unit35outputs the stored sum values to the control signal generation unit36.

The control signal generation unit36determines whether or not, among the sum values (a total of nine in the above-described example), there is a value corresponding to the case in which the timing of a video signal obtained from the video signal line63connected to the output unit28is the same as that of a video signal66output from the frame memory unit23, and if there is a value corresponding to the case in which the timing is the same, then the readout control signal at that time is generated as the readout control signal for the frame memory unit23(step S314).

In this case, the number of frames contained in the test video signal and the content of the video in each frame is known. For this reason, when computing the differences between the respective frames in the frame memory unit23and the frame memory unit33, cumulative values of the differences of the frames in the frame memory unit23with respect to the frames in the frame memory unit33are calculated beforehand as cumulative values for the respective cases in which the frames in the frame memory unit33are delayed by one to five frames with respect to the frames in the frame memory unit33, and the respective cumulative values are pre-stored in a memory unit inside the control signal generation unit36. Furthermore, the cumulative values of the differences of the frames in the frame memory unit33with respect to the frames in the frame memory unit23are pre-calculated for the respective cases in which the frames in the frame memory unit23are delayed with respect to the frames in the frame memory unit33by one to four frames, and the respective cumulative values are pre-stored in the memory unit inside the control signal generation unit36. After doing so, the control signal generation unit36pre-stores the cumulative value, among the respective cumulative values, at which the cumulative value is that for the case in which a frame in the frame memory unit23is the same as a frame in the frame memory unit33.

Then, if there is a cumulative value, among the cumulative values determined in step S314, that is the same as the cumulative value for the case in which a frame in the frame memory unit23is the same as a frame in the frame memory unit33, the control signal generation unit36can generate a readout control signal based on the playback timing of the frame memory unit33and the frame memory unit23when that cumulative value was determined. As a result thereof, the playback timing of the own display device can be synchronized with that of the display device that is furthest upstream.

Additionally, there may be cases in which a cumulative value that is the same as the cumulative value when a frame in the frame memory unit23is the same as a frame in the frame memory unit33is not obtained in step S314. In such a case, among the multiple pre-stored cumulative values, a cumulative value that is the same as a cumulative value for a combination of frames at which the playback timing is as close as possible to the playback timing when a frame in the frame memory unit23is the same as a frame in the frame memory unit33is selected. Furthermore, a readout control signal is generated on the basis of the combination of frames in the frame memory unit23and the frame memory unit23at which the selected cumulative value was computed. As a result thereof, the deviation in the playback timing of the own display device relative to the display device that is furthest upstream can be held to approximately a few frames.

When the readout control signal is generated, the MP20outputs a video signal that is to form the content to be actually displayed (step S315). In this case, the control signal generation unit36can generate a readout control signal in accordance with the sum values determined by the summation unit35while the test video signal is being played. Thus, in the display device1dand the display device2d, the playback timing of the video signal that is to be actually displayed is preferably of a level that there is not too much deviation between the MP10and the MP20. The SEL21supplies the video signal played by the MP20to the video processing circuit22and the output unit28. The output unit28is supplied the video signal from the SEL21. However, the video signal is played by the MP20, so the video signal supplied from the video signal line62is selected, and the video signal is output to a downstream display device. As a result thereof, in the downstream display device, it is possible to read, from the frame memory unit, the video played by the MP using the synchronization signal in the video signal supplied from the first display device.

Additionally, after the readout control signal has been generated, the display device2dmay continuously perform processes for outputting a video signal that is to form the content to be actually displayed. Additionally, after performing the synchronization process for synchronizing the display timing of video signals based onFIG.12and generating a readout control signal, the display device2dmay perform a process for outputting the video signal that is to form the content to be actually displayed in accordance with a timing at which a playback instruction is input from an external source.

After the downstream display devices in the multi-display system, such as the display device2d, have performed synchronization processes for synchronizing the display timing of the video signal based onFIG.12, the display devices in the entire multi-display system enter a synchronized state. For this reason, when displaying the video signal that is to form the content to be actually displayed, it can be displayed by synchronizing (matching the display timing) of the entire multi-display system.

Additionally, the display devices in the multi-display system can execute the synchronization process explained inFIG.5after the synchronization process explained inFIG.12has been performed. As a result thereof, by performing the synchronization process inFIG.12, the deviation in the display timing can be held to within one frame, and after doing so, by performing the synchronization process explained inFIG.5, the deviation in the display timing can be made even smaller.

The video processing circuit22generates frames in a video signal being played by the MP20in accordance with a synchronization signal contained in this video signal, and stores each frame separately in the frame memory unit23.

The synchronization circuit25acauses the video signal to be read from the frame memory unit23, frame by frame, in accordance with the readout control signal generated by the control signal generation unit36. As a result thereof, the frames of the video signal are supplied sequentially from the frame memory unit23to the drive circuit26ain accordance with a readout control signal generated by the control signal generation unit36. The drive circuit26adisplays by the display device unit27, frame by frame, the video signal supplied from the frame memory unit23(step S316).

By summing the differences between multiple frames of a video signal stored in the frame memory unit23and the frame memory unit33in this way, it is possible to determine whether the display timing is synchronized within the range of those multiple frames. As a result thereof, even if there is a difference of a few frames in the display timing, the display timing can be synchronized.

Additionally, the range over which the display timing can be synchronized is not limited to being a difference within one frame. For example, as illustrated inFIG.15, even if there is a difference in the frame display timing of two or more frames between the display device1d(frame memory unit13) and the frame device2d(frame memory unit23), the display timing can be synchronized as long as it is within a range of a few frames.

Additionally, even if there is not a timing that is the same within the range of these multiple frames, the degree of deviation in the display timing can be held to within one frame or to within a few frames.

FIG.16is a schematic block diagram representing the functions of a display device2eaccording to a sixth embodiment. This display device2ehas some parts that are the same as a portion of the display device2din the fifth embodiment. The parts that are the same will be assigned the same reference numbers and their explanations will be omitted.

A comparison unit37compares, frame by frame, a video signal read from the frame memory unit23and a video signal read from the frame memory unit33. For example, the comparison unit37compares a frame of the video signal read from the frame memory unit23with a frame of the video signal read from the frame memory unit33, and if there is no difference between the frames or the difference is a threshold value or less, then it is determined that the frames are the same. In this case, the video signals stored in the frame memory unit23and the frame memory unit33may be synchronizing video signals, which are test signals used for synchronization.

The control signal generation unit36agenerates a control signal for reading out a video signal stored in the frame memory unit23based on the comparison results from the comparison unit37. For example, the control signal generation unit36agenerates a control signal for reading out a video signal when the comparison results from the comparison unit37indicate a match or that the difference is the threshold value or less.

The synchronization circuit25asupplies the control signal generated by the control signal36ato the frame memory unit23. As a result thereof, the synchronization circuit25acan cause a frame of a video signal, corresponding to the control signal generated by the control signal generation unit36, to be read.

Additionally, if there is no frame in the frame memory unit33corresponding to the playback time of a frame in the frame memory unit23, then the comparison unit37may perform the comparison by using, as the frame in the frame memory unit33, a prescribed frame such that the difference becomes greater than the difference between frames when there is a frame in the frame memory unit33corresponding to the playback time of a frame in the frame memory unit23. As the prescribed frame, for example, it is possible to use a frame in which black is displayed in the entire area (an all-black frame).

Additionally, if there is no frame in the frame memory unit33corresponding to the playback time of a frame in the frame memory unit23, then the comparison unit37may detect that there is no corresponding frame, and may output information indicating a difference greater than the difference between frames when there is a frame in the frame memory unit33corresponding to the playback time of a frame in the frame memory unit23.

FIG.17is a schematic block diagram representing the functions of a display device2faccording to a seventh embodiment.

A memory unit23fstores a video signal input from a video playback device. This video playback device may be connected externally with respect to the display device2f.

A memory unit33fstores a video signal that corresponds to the video playback device and that is a video signal input from a first display device, different from the own display device, among those in a multi-display system formed from multiple display devices.

A comparison unit37fcompares, frame by frame, the video signal read from the memory unit23fand the video signal read from the memory unit33f.

A readout control unit25fcauses the video signal input from the video playback device stored in the memory unit23fto be read out on the basis of the comparison results in the comparison unit37f.

A display unit27fdisplays video of the video signal read out from the memory unit23.

In the above-described embodiments, the case in which the MP inFIG.1,FIG.3,FIG.4,FIG.6,FIG.9,FIG.10andFIG.16, and the video playback unit inFIG.7andFIG.8are provided inside the video display devices was explained. However, these may be provided external to the display devices.

Additionally, a program for performing the functions of the display device inFIG.3,FIG.4,FIG.6,FIG.7orFIG.8may be recorded on a computer-readable recording medium, and the display process may be performed by reading the program recorded on this recording medium into a computer system and executing the program. The “computer system” in this case includes an OS and hardware such as peripheral devices.

Additionally, if the “computer system” uses a www-based system, then it includes a webpage-presenting environment (or a display environment).

Additionally, the “computer-readable recording medium” refers to portable media such as flexible disks, magneto-optic disks, ROMs and CD-ROMs, and storage devices, such as hard disks, contained in computer systems. Furthermore, the “computer-readable recording medium” includes those that hold the program for a certain time, such as volatile memory inside a computer system serving as a server or a client. Additionally, the above-mentioned program may be for executing just some of the aforementioned functions, and furthermore, the aforementioned functions may be executed in combination with a program that is already recorded in a computer system. Additionally, the above-mentioned program may be stored on a prescribed server, and said program may be distributed (downloaded or the like) through a communication line in response to requests from other devices.

While embodiments of the present invention have been explained in detail with reference to the drawings above, the specific structure is not limited to these embodiments, and designs or the like not departing from the spirit of this invention are also included.