A semiconductor device includes a second oxide film and a pad electrode on a first oxide film that is formed on a front surface of a semiconductor substrate, a contact electrode and a first barrier layer formed in the second oxide film and connected to the pad electrode, a silicide portion formed between the contact electrode and a through-hole electrode layer and connected to the contact electrode and the first barrier layer, a via hole extending from a back surface of the semiconductor substrate to reach the silicide portion and the second oxide film, a third oxide film formed on a sidewall of the via hole and on the back surface of the semiconductor substrate, and a second barrier layer (H) and a rewiring layer formed inside the via hole and on the back surface of the semiconductor substrate and connected to the silicide portion.

TECHNICAL FIELD

The present invention relates to a semiconductor device having a through-hole electrode layer formed in a semiconductor substrate, and a manufacturing method of the semiconductor device.

BACKGROUND ART

In recent years, miniaturization is demanded of a package (a semiconductor device) in an integrated circuit used in an electronic device. As one example of achieving miniaturization, a through-hole electrode penetrating through a semiconductor substrate is replacing conventional wire bonding.

FIG. 17is a cross-sectional view showing one example a conventional semiconductor device.

InFIG. 17, a semiconductor device101is substantially structured with a semiconductor substrate102made of silicon or the like, a via hole107, a second oxide film109, a barrier layer110, and a rewiring layer111. The via hole107extends from a back surface102bof the semiconductor substrate102to reach a pad electrode105. The second oxide film109is formed on the sidewall of the via hole107and on the back surface102bof the semiconductor substrate102. The barrier layer110and the rewiring layer111are formed inside the via hole107and on the back surface102bof the semiconductor substrate102.

FIG. 18is a flowchart showing a manufacturing method of the conventional semiconductor device.FIGS. 19 to 26are each a cross-sectional view showing the state at each step in the manufacturing method of the conventional semiconductor device.

First, as shown inFIG. 19, on a first oxide film106on a front surface102aof the semiconductor substrate102where a circuit (not shown) is formed, the pad electrode105and a passivation film104are formed. Thereafter, on the passivation film104, a supporting substrate103is attached through an adhesive (not shown) (step S101inFIG. 18).

Next, as shown inFIG. 20, on the back surface102bof the semiconductor substrate102, a resist112is formed for providing an opening at a position corresponding to the pad electrode105(step S102inFIG. 18).

Then, as shown inFIG. 21, by etching the semiconductor substrate102using the resist112as an etching-purpose mask, the via hole107reaching the first oxide film106is formed (step S103inFIG. 18).

Subsequently, as shown inFIG. 22, by etching the first oxide film106using the resist112as an etching-purpose mask, the via hole107reaching the pad electrode105is formed (step S104inFIG. 18).

Then, as shown inFIG. 24, the second oxide film109is formed inside the via hole107and on the back surface102bof the semiconductor substrate102(step S106inFIG. 18).

Next, as shown inFIG. 25, by etching the second oxide film109at the bottom of the via hole107, the pad electrode105is exposed again (step S107inFIG. 18).

Subsequently, as shown inFIG. 26, the barrier layer110and the rewiring layer111are formed on the second oxide film109in order (step S108inFIG. 18).

The pad electrode105is electrically connected to the back surface102bof the semiconductor substrate102through a through-hole electrode108which is structured with the barrier layer110and the rewiring layer111.

The pad electrode105and the through-hole electrode108contact each other by a contact area corresponding to a diameter of the via hole107. The resistance value between the bad electrode105and the through-hole electrode108is determined by the contact area (for example, see Patent Literature 1).

With the conventional semiconductor device, for example, in a case where the pad electrode105is reduced in size for the purpose of achieving miniaturization of a chip, the diameter of the via hole107must be reduced accordingly. As a result, the aspect ratio of the via hole107is increased, and the manufacturing cost increases.

CITATION LIST

Patent Literature

SUMMARY OF THE INVENTION

Technical Problem

With the conventional structure, the resistance value between the pad electrode105and the through-hole electrode108is dependent on the diameter of the via hole107. Accordingly, it involves such an issue that the variations in diameter of the via hole107invite fluctuations in the resistance value between the pad electrode105and the through-hole electrode108.

The present invention resolves the conventional issue, and an object thereof is to provide a highly reliable semiconductor device, and a manufacturing method of the semiconductor device, in which the resistance value between the pad electrode and the through-hole electrode layer is independent of the variations in diameter of the via hole, and variations in resistance value are small.

Solution to Problem

In order to achieve the object described above, the present invention is structured as follows.

A semiconductor device manufacturing method according to one aspect of the present invention is characterized in comprising:

forming a first insulating film on a front surface of a semiconductor substrate;

forming an electrode section in the first insulating film;

forming a barrier layer that covers the electrode section;

forming a silicide layer that is connected to the electrode section;

forming a via hole penetrating to the front surface from a back surface of the semiconductor substrate;

forming a second insulating film on a sidewall of the via hole and on the back surface of the semiconductor substrate;

etching the second insulating film to expose the silicide layer and the first insulating film in the via hole; and

forming a through-hole electrode layer at the second insulating film on the sidewall of the via hole, the second insulating film on the back surface of the semiconductor substrate, the first insulating film on a bottom surface of the via hole, and the silicide layer.

Further, a semiconductor device according to another aspect of the present invention is characterized in comprising:

a first insulating film that is formed on a front surface of a semiconductor substrate;

an electrode section that is formed in the first insulating film and that is covered by a barrier layer;

a via hole penetrating to the front surface from a back surface of the semiconductor substrate;

a second insulating film that is formed on a sidewall of the via hole and on the back surface of the semiconductor substrate;

a through-hole electrode layer formed at the second insulating film on the sidewall of the via hole, the second insulating film on the back surface of the semiconductor substrate, and the first insulating film on a bottom surface the via hole; and

a silicide layer that is formed in the first insulating film and between the electrode section and the through-hole electrode layer, and that is connected to the electrode section and to the through-hole electrode layer, wherein

a relationship between a width A of the silicide layer and a width B of a bottom of the via hole in a cross section taken along a plane including a center axis of the via hole satisfies A≦B.

Effects of the Invention

As described in the foregoing, according to a semiconductor device and a semiconductor device manufacturing method of the present invention, the resistance value between the pad electrode and the through-hole electrode layer is independent of variations in diameter or in the width of the via hole. Therefore, a highly reliable semiconductor device with small variations in resistance value, and a manufacturing method of the semiconductor device can be provided.

DESCRIPTION OF EMBODIMENTS

In the following, with reference to the drawings, description will be given of an embodiment of the present invention. It is to be noted that, in the following description, identical symbols are allotted to the identical structures, and the description thereof will not be provided as necessary.

First Embodiment

FIG. 1is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

InFIG. 1, a semiconductor device1according to the first embodiment is structured to include a semiconductor substrate2, a pad electrode5, a contact electrode6, a first oxide film8, a second oxide film9, a third oxide film13, a silicide portion10, a via hole11, a first barrier layer7, a second barrier layer14, and a rewiring layer15. The contact electrode6is one example of an electrode section, and has an external connection terminal. The second oxide film9is one example of a first insulating film. The third oxide film13is one example of a second insulating film. The silicide portion10is one example of a silicide layer. The second barrier layer14and the rewiring layer15structure a through-hole electrode layer12.

The second oxide film9is formed on the first oxide film8that is formed on a front surface2aof the semiconductor substrate2. Further, the contact electrode6is disposed in a circular hole9aprovided at the second oxide film9, and is electrically connected to the pad electrode5that is provided on the second oxide film9. The first barrier layer7covers the contact electrode6so as to enhance adhesion of the second oxide film9and the contact electrode6. The silicide portion10is disposed in the circular hole9aprovided at the second oxide film9so as to be electrically connected to the first barrier layer7covering the contact electrode6, and is formed between the contact electrode6and the through-hole electrode layer12. The via hole11is formed to extend from a back surface2bof the semiconductor substrate2to reach the silicide portion10and the second oxide film9. The third oxide film13is formed on the sidewall of the via hole11and on the back surface2bof the semiconductor substrate2. The second barrier layer14and the rewiring layer15are formed inside the via hole11(i.e., on the sidewall and on the bottom surface) and on the back surface2bof the semiconductor substrate2in order. The second barrier layer14contacts the silicide portion10to establish an electrical connection therebetween.

The pad electrode5and the through-hole electrode layer12are electrically connected to each other via the contact electrode6, the first barrier layer7, and the silicide portion10. Further, the pad electrode5and the through-hole electrode layer12are electrically insulated by the second oxide film9at the portion where the contact electrode6, the first barrier layer7, and the silicide portion10are not interposed.

Further, the semiconductor substrate2and the through-hole electrode layer12are electrically insulated by the third oxide film13formed on the sidewall of the via hole11and on the back surface2bof the semiconductor substrate2.

Subsequently, description will be given of the materials for the constituents of the semiconductor device1according to the first embodiment.

As to the pad electrode5and the contact electrode6, any materials which exhibit low resistance between the pad electrode5and the contact electrode6will suffice. For example, there is used as the pad electrode5, aluminum, copper or an alloy thereof, titanium, titanium nitride, tantalum, tantalum nitride, a high melting point metal, or a compound thereof, or the like is used. Used as the contact electrode6is tungsten, aluminum or an alloy thereof, copper, or the like. It is to be noted that, the contact electrode6may be of a single contact form, or may be of a form structured with a plurality of contacts as shown inFIGS. 15 and 16. The diameter of the contact electrode6may be as great as or greater than the diameter of the pad electrode5.

There is used as the first barrier layer7, for the purpose of enhancing adhesion of the second oxide film9and the contact electrode6, titanium, titanium nitride, titanium tungsten, tantalum, tantalumnitride, a high melting point metal, or a lamination film made up thereof, or the like.

As the silicide portion10, which is formed on the front surface2aof the semiconductor substrate2, for the purpose of reducing the resistance, there is used tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, or the like.

Used as the second barrier layer14is, for the purpose of enhancing adhesion of the silicide portion10and the rewiring layer15, titanium, titanium nitride, titanium tungsten, tantalum, tantalumnitride, a high melting point metal, or a lamination film made up thereof, or the like.

As the rewiring layer15, Cu or the like is used.

As the first oxide film8and the second oxide film9, there is used SiO2, an oxynitride film, a nitride film, or the like.

The material for the supporting substrate3is silicon glass. The supporting substrate3is attached to the passivation film4, through an adhesive or by joining. As each of the passivation film4and the third oxide film13, there is used SiO2, an oxynitride film, a nitride film, an organic film made of polyimide or the like.

In a cross section taken along a plane including the center axis of the via hole11, a diameter A of the silicide portion10is adjusted such that the following relationship of (Expression 1) is established between itself and a diameter B of the via hole11. Then, the silicide portion10is formed with the diameter A of the silicide portion10adjusted in this manner. It is to be noted that, in a case where the silicide portion10and the via hole11are both in a circular shape, the comparison is based on their diameters; in a case where the silicide portion10and the via hole11are both in a quadrilateral shape, the comparison is based on their width dimensions.
A≦B  (Expression 1)

Here, the reason why the condition of the above-stated (Expression 1) is defined is to reduce variations in resistance value of the through-hole electrode layer12. In the first embodiment, by satisfying the condition of the above-stated (Expression 1), the diameter A of the silicide portion10whose shape is uniquely determined makes it possible to define the resistance value of the through-hole electrode layer12, and to reduce the variations in resistance value of the through-hole electrode layer12. In contrast thereto, with the conventional structure in which the resistance value is defined by the diameter B of the via hole11, the shape of the via hole11of the through-hole electrode obtained by etching may possibly vary. Hence, the variations in resistance value of the through-hole electrode may possibly occur.

It is to be noted that, for the purpose of allowing the third oxide film13and the second barrier layer14to closely adhere to each other, preferably, the thickness of the second barrier layer14on the bottom surface of the via hole11is uniform. Accordingly, in the first embodiment, the bottom surface of the via hole11is in a flat shape.

Next, with reference to the drawings, description will be given of a manufacturing method of the semiconductor device1described above.FIG. 2is a flowchart showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.FIGS. 3 to 11are each a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

First, as shown inFIG. 3, on the front surface2aof the semiconductor substrate2where a circuit (not shown) is formed, the first oxide film8is formed. Subsequently, on the first oxide film8, the second oxide film9and a polysilicon film17are formed. Then, as shown inFIG. 3, on the polysilicon film17and in the circular hole9aof the second oxide film9, the silicide portion10, the first barrier layer7, and the contact electrode6are formed in order. Thereafter, the pad electrode5is formed on the second oxide film9and the contact electrode6, and the passivation film4is formed on the second oxide film9and the pad electrode5(step S1inFIG. 2). As a result, the silicide portion10, the first barrier layer7, and the contact electrode6are disposed in the circular hole9athat is provided at the second oxide film9.

The first oxide film8is thick enough to electrically insulate the semiconductor substrate2and the polysilicon film17from each other.

The pad electrode5is electrically connected to the polysilicon film17via the silicide portion10, the first barrier layer7, and the contact electrode6. Further, because the semiconductor substrate2and the polysilicon film17are electrically insulated from each other, the pad electrode5is electrically insulated from the semiconductor substrate2. Accordingly, using a measuring terminal or the like to probe the pad electrode5, in a state before the via hole11is formed as shown inFIG. 3, using the electrode section (specifically, by establishing an electrical connection among the silicide portion10, the first barrier layer7, and the contact electrode6via the pad electrode5), it becomes possible to measure the electrical characteristic of the circuit formed on the semiconductor substrate2. This makes it possible to determine whether the circuit of the semiconductor substrate2is acceptable or defective, before the semiconductor device1is completed.

In a cross section taken along a plane including the center axis of the via hole11, a diameter C of the polysilicon film17is set such that the following relationship of (Expression 2) is established between itself and the diameter A of the silicide portion10. It is to be noted that, in a case where the polysilicon film17and the silicide portion10are both circular, the comparison is based on their diameters; in a case where the polysilicon film17and the silicide portion10are both quadrilateral, the comparison is based on their width dimensions.
C≧A  (Expression 2)

Here, the reason why the condition of the above-stated (Expression 2) is defined is to further reduce the variations in resistance value of the through-hole electrode layer12. In the first embodiment, by satisfying the condition of the above-stated (Expression 2), the diameter A of the silicide portion10whose shape is uniquely determined makes it possible to define the resistance value of the through-hole electrode layer12, and to reduce the variations in resistance value of the through-hole electrode layer12. In contrast thereto, with the conventional structure in which the resistance value is defined by the diameter C of the polysilicon film17, the shape of the polysilicon film17may possibly vary. Hence, the variations in resistance value of the through-hole electrode may possibly occur.

As the silicide portion10, a layer formed through a thermal reaction of the first barrier layer7is used. Alternatively, it is possible to use, as the silicide portion10, a layer made of tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, or the like, which is formed through a thermal reaction after another film (e.g., made of tungsten, titanium, cobalt, nickel, or the like) is deposited on the polysilicon film17. In the case where the silicide portion10is formed on the polysilicon film17by allowing the first barrier layer7to thermally react, the diameter of the silicide portion10is equal to the hole diameter of the contact electrode6.

Then, on the passivation film4, the supporting substrate3is attached through an adhesive (not shown).

Next, as shown inFIG. 4, on the back surface2bof the semiconductor substrate2, a resist16having an opening portion16ais formed for providing an opening at a position corresponding to the pad electrode5(step S2inFIG. 2).

Then, as shown inFIG. 5, by etching the semiconductor substrate2using the resist16as an etching-purpose mask, the via hole11reaching the first oxide film8is formed (step S3inFIG. 2). The first oxide film8serves as an etching stopper layer for the semiconductor substrate2, and the shape of the bottom surface of the via hole11becomes flat. The diameter B of the via hole11is adjusted such that the above-stated relationship of (Expression 1) is established between itself and the diameter A of the silicide portion10. It is to be noted that, from the viewpoint of the adhesion of the second barrier layer14, the diameter B of the via hole11is desirably equal to or less than the diameter C of the polysilicon film17. However, so long as it falls within the range in which the above-stated relationship of (Expression 2) is satisfied, the diameter B of the via hole11may be greater than the diameter C of the polysilicon film17.

Next, as shown inFIG. 6, by etching the first oxide film8, the via hole11reaching the polysilicon film17is formed (step S4inFIG. 2). The polysilicon film17serves as an etching stopper layer of the first oxide film8, and the shape of the bottom surface of the via hole11becomes flat.

Subsequently, as shown inFIG. 7, by etching the polysilicon film17, the via hole11reaching the silicide portion10and the second oxide film9is formed (step S5inFIG. 2). The silicide portion10and the second oxide film9each serve as an etching stopper layer for the polysilicon film17, and the shape of the bottom surface of the via hole11becomes flat. The etching of the polysilicon film17is desirably carried out by dry etching.

It is to be noted that, in a case where the polysilicon film17is used as part of the through-hole electrode layer12, the etching of the polysilicon film17is not necessary. Desirably, the polysilicon film17in this case has its resistance reduced by doping. While n-type doping is desirable, it may be of the p-type. However, in a case where the polysilicon film17is used as part of the electrode as it is, the polysilicon film17may not be etched. In that case, it is desirable that the polysilicon film17is doped.

Next, as shown inFIG. 8, the resist16is removed from the back surface2bof the semiconductor substrate2(step S6inFIG. 2). For carrying out the removal of the resist16, wet processing or dry processing is used.

Then, as shown inFIG. 9, inside the via hole11(i.e., on the sidewall and on the bottom surface) and on the back surface2bof the semiconductor substrate2, the third oxide film13is formed (step S7inFIG. 2). In forming the third oxide film13, thermal oxidation, CVD, or sputtering is used.

Next, as shown inFIG. 10, by etching the third oxide film13positioned on the bottom surface of the via hole11, that is, the third oxide film13positioned on the silicide portion10and the second oxide film9, so as to remove the same, the silicide portion10and the second oxide film9are exposed again (step S8inFIG. 2). By etching the third oxide film13by a thickness of the third oxide film13on the silicide portion10and on the second oxide film9, the shape of the bottom surface of the via hole11is kept flat. The etching of the third oxide film13is desirably carried out by dry etching. The third oxide film13on the sidewall of the via hole11and on the back surface2bof the semiconductor substrate2just slightly reduces in thickness and remains mostly.

Subsequently, as shown inFIG. 11, the second barrier layer14and the rewiring layer15are formed on the third oxide film13(step S9inFIG. 2). In forming the second barrier layer14, CVD or sputtering is used. Because the shape of the bottom surface of the via hole11is flat, the thickness of the second barrier layer14on the bottom surface of the via hole11becomes uniform, and the second barrier layer14which exhibits excellent adhesion to the third oxide film13is formed. Further, the second barrier layer14on the bottom surface of the via hole11suppresses diffusion of the material structuring the rewiring layer15(e.g., Cu) into the semiconductor substrate2. In the case where the thickness of the second barrier layer14is uniform, the second barrier layer14can be thinned. Desirably, the rewiring layer15is formed by plating, while the rewiring layer15may be formed by CVD, sputtering, or any combination thereof. The rewiring layer15is shaped such that the via hole11is buried incompletely (i.e., partially) or buried completely (i.e., entirely).

With the structure of the first embodiment, the resistance value between the pad electrode5and the through-hole electrode layer12is dependent on the diameter of the silicide portion10, and not on the diameter of the via hole11. Accordingly, the resistance value between the pad electrode5and the through-hole electrode layer12will not be affected by the variations in diameter of the via hole11. The via hole11and the silicide portion10are different in processing accuracy. The processing variation in diameter of the via hole11is approximately 1 μm, whereas the processing variation in diameter of the silicide portion10is approximately 1 nm. Accordingly, with the semiconductor device1and the manufacturing method thereof according to the first embodiment, the variations in resistance value between the pad electrode5and the through-hole electrode layer12can be reduced as compared to the conventional manner.

Further, with the semiconductor device1and the manufacturing method thereof according to the first embodiment, the diameter of the via hole11can be set to be greater than the diameter of the pad electrode5. Therefore, the aspect ratio of the via hole11can be reduced, thereby to reduce the manufacturing cost. Furthermore, a reduction in size of the pad electrode5makes it possible to reduce the area of the semiconductor chip.

Still further, with the semiconductor device1and the manufacturing method thereof according to the first embodiment, the shape of the bottom surface of the via hole11becomes flat. This allows the thickness of the second barrier layer14on the bottom surface of the via hole11to be uniform. Because the thickness of the second barrier layer14on the bottom surface of the via hole11becomes uniform, the second barrier layer14exhibiting excellent adhesion to the third oxide film13can be formed.

It is to be noted that, the same effect can be achieved using an amorphous silicon film in place of the polysilicon film17according to the first embodiment.

Here, with reference toFIGS. 15 and 16, description will be given of a case where the contact electrode6is structured with a plurality of contact members.

FIG. 15is a cross-sectional view of a semiconductor device of a first example according to the first embodiment, in which the contact electrode6is structured with a plurality of disc-like or quadrilateral plate-like contact members6bin the second oxide film9. In the semiconductor device shown inFIG. 15, before the contact electrodes6bare formed, one silicide portion10is formed in one hole9dat the second oxide film9. Thereafter, the plurality of disc-like or quadrilateral plate-like contact members6bare disposed in a plurality of small holes9bat the second oxide film9. It is to be noted that, at this time, the plurality of disc-like or quadrilateral plate-like contact members6bare disposed so as to each contact the silicide portion10.

Further,FIG. 16is a cross-sectional view of a semiconductor device of a second example according to the first embodiment, in which the contact electrode6is structured with a plurality of disc-like or quadrilateral plate-like contact members6cin the second oxide film9. In the semiconductor device shown inFIG. 16, the contact electrodes6care respectively formed in a plurality of holes9cat the second oxide film9. Thereafter, silicide portions10care formed in the holes9c, respectively. It is to be noted that, at this time, the silicide portions10care formed so as to contact the contact electrodes6cin the plurality of holes9c, respectively.

With the semiconductor devices having the structure shown inFIGS. 15 and 16also, the resistance value between the pad electrode5and the through-hole electrode layer12is independent of the variations in diameter of the via hole11. Accordingly, the semiconductor device having the structure shown inFIGS. 15 and 16is also highly reliable with small variations in resistance value.

First Modified Example of the First Embodiment

In the first embodiment, the first barrier layer7and the contact electrode6are separately formed. However, the present invention is not limited thereto. Instead, as a first modified example of the first embodiment, as shown inFIG. 12, the first barrier layer7and the contact electrode6may integrally be formed as a contact electrode6A. That is, the first barrier layer7may be thinned or may be omitted. In giving description of the first modified example, a laminated film in which a TiN layer and a Ti layer are laminated is used as one example of the first barrier layer7.

The Ti layer of the first barrier layer7has a function of forming an ohmic contact with the polysilicon film17, and a function of improving adhesion of the second oxide film9to the TiN layer of the first barrier layer7. In connection with the function of forming the ohmic contact, for example, by forming the silicide portion10of TiSi2by a thermal reaction between Ti of the Ti layer and Si of the polysilicon film17, the ohmic contact can be obtained. It is to be noted that, in a case where the silicide portion10is formed at a portion other than the first barrier layer7, the Ti layer can be omitted.

Further, provided that any contact electrode material that does not diffuse into the polysilicon film17and the semiconductor substrate2can be used in the contact electrode6, the TiN layer of the first barrier layer7becomes unnecessary.

Accordingly, as described above, when the silicide portion10is formed at a portion other than the first barrier layer7, the first barrier layer7can be structured solely with the TiN layer, while omitting the Ti layer. Further, use of any contact electrode material that does not diffuse into the semiconductor substrate2and the polysilicon film17and that possesses excellent adhesion force, in the contact electrode6makes it possible to omit the TiN layer of the first barrier layer7, such that the first barrier layer7can be formed solely with the Ti layer. Further, in the case where the silicide portion10is formed at a portion other than the first barrier layer7and where any contact material that does not diffuse into the polysilicon film17and the semiconductor substrate2and that possesses excellent adhesion force is used in the contact electrode6, as shown inFIG. 12, the contact electrode6solely can be formed as the contact electrode6A, without the necessity of forming the first barrier layer7itself.

Second Modified Example of the First Embodiment

In the first embodiment, the first barrier layer7, the contact electrode6, and the pad electrode5are separately formed. However, the present invention is not limited thereto. As a second modified example of the first embodiment, as shown inFIG. 13, the first barrier layer7, the contact electrode6, and the pad electrode5may be integrated so as to be formed as a single pad electrode5A. Because integration of the first barrier layer7and the contact electrode6is the same as that of the first modified example, description will chiefly be given of the integration of the contact electrode6and the pad electrode5.

In the first embodiment, the contact electrode6is connected to the polysilicon film17and the pad electrode5at low resistance. The pad electrode5is connected to the contact electrode6at low resistance. They are necessary from the viewpoint of securing a flat portion when wire bonding is carried out. That is, provision of the pad electrode5separately from the contact electrode6makes it possible to improve flatness, as compared to a case where the contact electrode6solely is employed as an external electrode terminal. However, when the contact electrode6and the pad electrode5are connected to the polysilicon film17at low resistance Kin other words, when the contact electrode6and the pad electrode5are integrated so as to form the pad electrode5A as in the second modified example), as shown inFIG. 13, it becomes possible to form a flat plane, forming a vertical cross section of the pad electrode5A into a convex shape. Further, in a case where wire bonding is not used, the pad electrode5A is not necessarily flat.

In the first embodiment, the first barrier layer7, the contact electrode6, and the pad electrode5are separately formed as one resolution to the aforementioned issue in the manufacturing method. Therefore, in a case where such an issue can be resolved, it is also possible to form the pad electrode5A by integrating the first barrier layer7, the contact electrode6, and the pad electrode5as in the second modified example.

Third Modified Example of the First Embodiment

In the first embodiment, the second barrier layer14and the rewiring layer15are separately formed. However, the present invention is not limited thereto. As a third modified example of the first embodiment, as shown inFIG. 14, the second barrier layer14and the rewiring layer15may be integrated so as to be formed as a rewiring layer15A. It is to be noted that, whileFIG. 14shows an application of the third modified example to the second modified example shown inFIG. 13, the present invention is not limited thereto. The third modified example can be also applied to the first modified example.

In the first embodiment, the second barrier layer14(e.g., the layer structured with Ti) has a function of preventing diffusion of the rewiring layer15into the semiconductor substrate2and the polysilicon film17, and a function of improving adhesion force of the third oxide film13and the rewiring layer15. Further, the rewiring layer15(e.g., the layer structured with Cu) is low resistant, and has a function of bearing a solder ball. It is to be noted that, so long as it is possible to use as the rewiring layer15a rewiring material that can possess the function of preventing diffusion into the semiconductor substrate2and the polysilicon film17and that exhibits excellent adhesion force, similarly to the third modified example, as shown inFIG. 14, the rewiring layer15can be formed as the rewiring layer15solely, while omitting the second barrier layer14.

In the first embodiment, the second barrier layer14and the rewiring layer15are separately formed as one resolution to the aforementioned issue in the manufacturing method. Therefore, in a case where such an issue can be resolved, it is also possible to form the rewiring layer15A by integrating the second barrier layer14and the rewiring layer15as in the third modified example.

It is to be noted that, the semiconductor substrate2is made of a material such as silicon, and it may be electrically conductive, insulating, or semi-insulating.

It is to be noted that, the polysilicon film17may remain in the final product in some cases depending on a manufacturing method which will be described later, but may not remain in the final product in other cases.

It to be noted that the polysilicon film17is formed desirably before the second oxide film9is formed. Alternatively, the polysilicon film17may be formed after the second oxide film9is formed.

It is to be noted that, by appropriately combining any of the above-described various embodiments and modified examples, their respective effects can be exerted.

INDUSTRIAL APPLICABILITY

The semiconductor device and the semiconductor device manufacturing method of the present invention provide a through-hole electrode layer whose variations in resistance value are small. The present invention can be widely applied to a semiconductor device in which a through-hole electrode layer is formed in a semiconductor substrate, and to a manufacturing method of the semiconductor device.