Package structure and method for forming the same

Package structures and methods for forming the package structures are provided. A package structure includes a molding compound having a surface. The package structure also includes an integrated circuit die in the molding compound. The integrated circuit die has a portion protruding from the surface. The package structure further includes a planarization layer covering the surface. The planarization layer surrounds the portion of the integrated circuit die. In addition, the package structure includes a redistribution layer electrically connected to the integrated circuit die. The redistribution layer covers the planarization layer and the integrated circuit die.

BACKGROUND

With the constant evolution of semiconductor technology, semiconductor dies are becoming increasingly smaller. More functions, however, need to be integrated into these semiconductor dies. Accordingly, these semiconductor dies have increasingly greater numbers of I/O pads, and the density of the I/O pads is quickly rising. As a result, the packaging of semiconductor dies is becoming more challenging.

Package technologies can be divided into multiple categories. In one of the categories, dies are sawed first, and then the “known-good-dies” are placed on a temporary wafer or panel-like carrier. Redistribution layers (RDLs) are made onto the “re-configured” wafer or panel after encapsulation or molding of the dies. Afterwards, conductive balls are attached, and then the “re-configured” wafer or panel is sawed to get a singulated package. The RDLs can “fan-out” the I/O pads to the area outside of the die area so as to accommodate high I/O devices for a given ball pitch requirement.

New packaging technologies have been developed to further improve the density and functions of semiconductor dies. These relatively new types of packaging technologies for semiconductor dies face manufacturing challenges, and they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

Some embodiments of the disclosure are described.FIGS. 1A-1Gare cross-sectional views of various stages of a process for forming a package structure, in accordance with some embodiments. Additional operations can be provided before, during, and/or after the stages described inFIGS. 1A-1G. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the package structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.

As shown inFIG. 1A, a carrier substrate100is provided, in accordance with some embodiments. In some embodiments, the carrier substrate100is used as a temporary substrate. The carrier substrate100provides mechanical and structural support during subsequent processing steps. Afterwards, the carrier substrate100may be removed.

In some embodiments, the carrier substrate100includes a glass substrate, a ceramic substrate, a polymer substrate, another suitable supporting material, or a combination thereof. In some embodiments, the carrier substrate100is a glass wafer or another suitable wafer.

Afterwards, an adhesive layer110is deposited over the carrier substrate100, in accordance with some embodiments. The adhesive layer110may be referred to as a temporary adhesive layer or a release layer.

The adhesive layer110may be made of glue, or may be a lamination material, such as a tape. In some embodiments, the adhesive layer110is photosensitive and is easily detached from the carrier substrate100by light irradiation. For example, shining ultra-violet (UV) light or laser light on the carrier substrate100can detach the adhesive layer110. In some embodiments, the adhesive layer110is a light-to-heat-conversion (LTHC) coating. In some other embodiments, the adhesive layer110is heat-sensitive and is easily detached from the carrier substrate100when it is exposed to heat.

As shown inFIG. 1A, one or more integrated circuit dies120are placed over the adhesive layer110, in accordance with some embodiments. In some embodiments, the integrated circuit dies120are sawed from one or more integrated circuit wafers. The integrated circuit dies120may be “known-good-dies”. In some embodiments, the integrated circuit dies120are device dies including transistors, diodes, or another suitable integrated circuit element. The device dies may also include capacitors, inductors, resistors, another integrated circuit element, or a combination thereof. In some embodiments, the integrated circuit dies120are sensor dies, logic dies, central processing unit (CPU) dies, memory dies, or other suitable dies.

In some embodiments, the integrated circuit dies120have an active surface120A and a non-active surface120B that is opposite to the active surface120A. In some embodiments, the active surface120A faces the adhesive layer110. In some embodiments, each of the integrated circuit dies120includes a semiconductor substrate130, a dielectric layer140, conductive pads150and a passivation layer160.

The semiconductor substrate130is adjacent to the non-active surface120B of the integrated circuit dies120. In some embodiments, the semiconductor substrate130includes silicon or another elementary semiconductor material such as germanium. In some other embodiments, the semiconductor substrate130includes a compound semiconductor. The compound semiconductor may include gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable compound semiconductor, or a combination thereof.

In some embodiments, the semiconductor substrate130includes a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a wafer bonding process, a silicon film transfer process, a separation by implantation of oxygen (SIMOX) process, another applicable method, or a combination thereof.

Various device elements (not shown) are formed in and/or over the semiconductor substrate130, in accordance with some embodiments. Examples of the various device elements include transistors, diodes, another suitable element, or a combination thereof. For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n channel field effect transistors (PFETs/NFETs), etc.

In some embodiments, the dielectric layer140is over the semiconductor substrate130. The dielectric layer140may cover the device elements over the semiconductor substrate130. The dielectric layer140may include an interlayer dielectric (ILD) layer and inter-metal dielectric (IMD) layers. Multiple conductive features (not shown) are in the ILD layer and IMD layers and electrically connected to the device elements in and/or over the semiconductor substrate130. The conductive features may include conductive contacts, conductive lines and/or conductive vias.

In some embodiments, the dielectric layer140is made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-K material, porous dielectric material, another suitable dielectric material, or a combination thereof. The material of the dielectric layer140is selected to minimize size, propagation delays, and crosstalk between nearby conductive features.

In some embodiments, the conductive pads150are positioned over the dielectric layer140. The conductive pads150are electrically connected to the device elements in and/or over the semiconductor substrate130through the conductive features in the dielectric layer140. In some embodiments, there is no conductive feature, such as a conductive bump or pillar, on the conductive pads150.

In some embodiments, the passivation layer160is positioned over the dielectric layer140and adjacent to the active surface120A of the integrated circuit dies120. The passivation layer160partially covers the conductive pads150. As a result, each of the conductive pads150is partially exposed from the passivation layer160.

As shown inFIG. 1A, each of the conductive pads150has opposite surfaces150A and150B, and the passivation layer160has opposite surfaces160A and160B. The surface150B of the conductive pads150may be substantially coplanar with the surface160B of the passivation layer160. The surface150A of the conductive pads150may be non-coplanar with the surface160A of the passivation layer160. The surface150A may be between the surface160A and the surface150B.

In some embodiments, the integrated circuit dies120are reversed and placed over the adhesive layer110. As a result, the surface150A of the conductive pads150and the surface160A of the passivation layer160face the adhesive layer110. In some embodiments, the surface150A of the conductive pads150is in direct contact with the adhesive layer110. In some embodiments, the surface160A of the passivation layer160is in direct contact with the adhesive layer110.

The passivation layer160may include multiple sub-layers. In some embodiments, the total thickness of the passivation layer160and the dielectric layer140is in a range from about 1 μm to about 30 μm. However, embodiments of the disclosure are not limited thereto.

In some embodiments, the passivation layer160is made of a polymer material. In some embodiments, the passivation layer160includes polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), silicone, acrylates, siloxane, another suitable material, or a combination thereof. In some other embodiments, the passivation layer160includes non-organic materials. The non-organic materials may include silicon oxide, un-doped silicate glass, silicon oxynitride, solder resist (SR), silicon nitride, silicon carbide, hexamethyldisilazane (HMDS), another suitable material, or a combination thereof.

As shown inFIG. 1A, the integrated circuit dies120slightly or partially sink into the adhesive layer110, in accordance with some embodiments. As a result, the adhesive layer110partially surrounds the integrated circuit dies120. In some embodiments, the integrated circuit dies120are not deeply sink into the adhesive layer110and are not completely immersed in the adhesive layer110.

In some embodiments, the active surface120A of the integrated circuit dies120is embedded in the adhesive layer110, and is non-coplanar with the top surface110A of the adhesive layer110. In some embodiments, the integrated circuit dies120are spaced apart from the bottom surface110B of the adhesive layer110. As a result, the active surface120A is non-coplanar with the bottom surface110B of the adhesive layer110. The active surface120A is positioned between the top surface110A and the bottom surface110B of the adhesive layer110.

In some embodiments, the sidewall120C of the integrated circuit dies120is partially covered by the adhesive layer110. AlthoughFIG. 1Ashows that the top surface110A of the adhesive layer110is substantially perpendicular to the sidewall120C of the integrated circuit dies120, embodiments of the disclosure are not limited thereto. In some other embodiments, the top surface110A of the adhesive layer110is inclined to the sidewall120C of the integrated circuit dies120. The top surface110A of the adhesive layer110may be curved.

In some embodiments, one or more portions of the adhesive layer110are pressed and squeezed by the integrated circuit dies120. As a result, one or more portions of the adhesive layer110are recessed from the top surface110A towards the bottom surface110B along the sidewall120C. Recesses may be formed between the recessed top surface110A of the adhesive layer110and the sidewall120C of the integrated circuit dies120. The recesses may gradually shrink along the sidewall120C. Alternatively, one or more portions of the adhesive layer110may protrude from the top surface110A along the sidewall120C. The protrusions may gradually shrink along the sidewall120C.

As shown inFIG. 1A, the integrated circuit dies120sink into the adhesive layer110by a depth D. In some embodiments, the depth D is in a range from about 1 μm to about 20 μm. However, embodiments of the disclosure are not limited thereto. The depth D may vary according to the material of the adhesive layer110and/or the placement of the integrated circuit dies120.

In some embodiments, the passivation layer160and the conductive pads150of the integrated circuit dies120are partially or completely dipped into the adhesive layer110. In some embodiments, the dielectric layer140is partially or completely immersed in the adhesive layer110. The adhesive layer110may enclose the passivation layer160, the conductive pads150, the dielectric layer140and/or the semiconductor substrate130. The top surface110A of the adhesive layer110may or may not be coplanar with the surface160B of the passivation layer160.

As shown inFIG. 1B, a package layer170is deposited over the top surface110A of the adhesive layer110, in accordance with some embodiments. The package layer170covers the top surface110A of the adhesive layer110and the non-active surface120B of the integrated circuit dies120. The package layer170continuously encircles the integrated circuit dies120. In some embodiments, the package layer170is in direct contact with the adhesive layer110.

As shown inFIG. 1B, the package layer170partially wraps the integrated circuit dies120, in accordance with some embodiments. In other words, the package layer170and the adhesive layer110together completely wrap the integrated circuit dies120. In some embodiments, the dielectric layer140and/or the semiconductor substrate130are partially or completely surrounded by the package layer170. The package layer170is separated from the passivation layer160so that the conductive pads150in the passivation layer160are not surrounded by the package layer170.

Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the passivation layer160is partially surrounded by the package layer170, and the conductive pads150are partially or completely surrounded by the package layer170.

As mentioned above, the adhesive layer110has recesses and/or protrusions along the sidewall120C of the integrated circuit dies120, in accordance with some embodiments. The package layer170may fill up the recesses. The package layer170may cover and surround the protrusions.

In some embodiments, the package layer170includes a polymer material. In some embodiments, the package layer170includes a molding compound. In some embodiments, the package layer170includes fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof. In some embodiments, the package layer170is formed by a compression molding process, an immersion molding process, another applicable process, or a combination thereof.

In some embodiments, the integrated circuit dies120are dipped further into the adhesive layer110during the formation of the package layer170or another subsequent process. As a result, the depth D is increased. The depth D may vary according to the processes used.

Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the depth D remains substantially the same during the formation of the package layer170and/or subsequent processes.

As shown inFIG. 1C, the carrier substrate100is removed from the adhesive layer110, in accordance with some embodiments. As a result, the bottom surface110B of the adhesive layer110is exposed. In some embodiments, the carrier substrate100is separated from the adhesive layer110by light irradiation or heating.

As shown inFIG. 1D, the adhesive layer110is peeled off and removed, in accordance with some embodiments. As a result, the integrated circuit dies120are partially exposed. For example, the surface160A of the passivation layer160and the surface150A of the conductive pads150are exposed. The sidewall120C of the integrated circuit dies120becomes exposed after the removal of the adhesive layer110. In some embodiments, the sidewall of the passivation layer160is partially or completely exposed. In some embodiments, the sidewall of the dielectric layer140is partially or completely exposed.

The package layer170has opposite surfaces170A and170B. The surface170A covers the integrated circuit dies120. The surface170B becomes exposed after the removal of the adhesive layer110. The integrated circuit dies120protrude from the exposed surface170B, as shown inFIG. 1D. As a result, a gap172is formed between the exposed surface170B and the active surface120A. In some embodiments, the depth D of the gap172is in a range from about 1 μm to about 20 μm. However, embodiments of the disclosure are not limited thereto.

As mentioned above, the package layer170fills up the recesses of the adhesive layer110and/or covers the protrusions of the adhesive layer110, in accordance with some embodiments. As a result, the package layer170may have recesses and/or protrusions along the sidewall120C of the integrated circuit dies120due to the removal of the adhesive layer110. The recesses and/or protrusions may gradually shrink along the sidewall120C. In other words, the gap172may extend into the package layer170due to the recesses of the package layer170or may be separated from the integrated circuit dies120by the protrusions of the package layer170.

As shown inFIG. 1E, a planarization layer180is deposited over the exposed surface170B of the package layer170, in accordance with some embodiments. In some embodiments, the planarization layer180fills the gap172. The gap172may be completely or partially filled with the planarization layer180. In some embodiments, the planarization layer180is in direct contact with the package layer170.

In some embodiments, the planarization layer180continuously surrounds the integrated circuit dies120and extends between the integrated circuit dies120. In some embodiments, the planarization layer180does not cover or extend over the active surface120A of the integrated circuit dies120. In some embodiments, the planarization layer180does not cover the surface160A of the passivation layer160and/or the surface150A of the conductive pads150. In some embodiments, the planarization layer180is in direct contact with the passivation layer160and/or the dielectric layer140.

As shown inFIG. 1E, there is an interface174between the planarization layer180and the package layer170, in accordance with some embodiments. The planarization layer180has a surface180A that is opposite to the interface174. In some embodiments, the surface180A of the planarization layer180is substantially coplanar with the active surface120A of the integrated circuit dies120or the surface160A of the passivation layer160. The surface180A may be non-coplanar with the surface160A but closer enough to the surface160A. As a result, the surface180A and the surface160A together form a substantially flat surface. In some embodiments, the active surface120A is closer to the interface174than the non-active surface120B.

In some embodiments, there is an interface176between the planarization layer180and the passivation layer160. AlthoughFIG. 1Eshows that the surface180A of the planarization layer180is substantially perpendicular to the interface176, embodiments of the disclosure are not limited thereto. In some other embodiments, the surface180A of the planarization layer180is inclined to the interface176. In some other embodiments, a portion of the package layer170is sandwiched between the planarization layer180and the passivation layer160. There may be no interface between the planarization layer180and the passivation layer160.

As mentioned above, the package layer170has recesses and/or protrusions along the sidewall120C of the integrated circuit dies120, in accordance with some embodiments. As a result, the planarization layer180on the package layer170may fill up the recesses and/or may cover and surround the protrusions.

In some embodiments, the planarization layer180has a thickness that is substantially the same as the depth D. In some embodiments, the planarization layer180is made of an insulating material. In some embodiments, the planarization layer180includes polybenzoxazole (PBO), polyimide (PI), another suitable material, or a combination thereof. In some embodiments, the material of the planarization layer180is different from that of the package layer170.

Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the material of the planarization layer180is substantially the same as that of the package layer170. In some other embodiments, the planarization layer180includes an underfill material. The underfill material includes fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof. The fillers in the planarization layer180may be substantially the same as or different from those in the package layer170. In some embodiments, the size of the fillers in the planarization layer180is less than that of the fillers in the package layer170.

As shown inFIG. 1E, a dispensing process182is performed over the surface170B of the package layer170so as to deposit the planarization layer180, in accordance with some embodiments. In some embodiments, the dispensing process182is performed along the gap172, as shown inFIG. 1E. In some embodiments, the material of the planarization layer180is not deposited over the active surface120A of the integrated circuit dies120during the dispensing process182. As a result, the conductive pads150remain exposed during the dispensing process182and are not covered by the planarization layer180.

Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the planarization layer180is deposited using a spin-on process, a spray coating process, a lamination process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, another applicable process, or a combination thereof.

In some embodiments, a curing process is subsequently performed to cure the planarization layer180. In some embodiments, a planarization process is subsequently performed over the surface180A of the planarization layer180. The planarization process includes a grinding process, a chemical mechanical polishing (CM)) process, an etching process, another applicable process, or a combination thereof. In some other embodiments, the planarization process is not performed over the surface180A of the planarization layer180.

As shown inFIG. 1F, a patterned redistribution layer190is formed over the surface180A of the planarization layer180and the surface160A of the passivation layer160, in accordance with some embodiments. The redistribution layer190extends to the surface150A of the conductive pads150and is electrically connected to the conductive pads150of the integrated circuit dies120. In some embodiments, the redistribution layer190is in direct contact with the surface150A of the conductive pads150.

In some embodiments, a portion of the planarization layer180is sandwiched between the redistribution layer190and the package layer170. In some embodiments, the redistribution layer190extends across the interface176between the planarization layer180and the passivation layer160. The redistribution layer190extends from the surface180A of the planarization layer180to the surface160A of the passivation layer160. As a result, the redistribution layer190extends across the interface176along a direction that is substantially parallel to the surface180A of the planarization layer180.

In some embodiments, the redistribution layer190does not extend into the gap172. The redistribution layer190is separated from the package layer170by the planarization layer180in the gap172. In some embodiments, the redistribution layer190does not bend to the package layer170. In some embodiments, the redistribution layer190includes flat and straight lines or traces as viewed from a cross-sectional view. The cross-sectional view is taken along a plane that is perpendicular to the main surface of the integrated circuit dies120. The main surface of the integrated circuit dies120may be the active surface120A of the integrated circuit dies120.

In some embodiments, the line width and/or the line space of the redistribution layer190is in a range from about 1 μm to about 10 μm. However, embodiments of the disclosure are not limited thereto.

In some embodiments, the redistribution layer190is made of a metal material. The metal material includes copper (Cu), aluminum (Al), tungsten (W), gold (Au), another suitable material, or a combination thereof. In some embodiments, the metal material is deposited using an electroplating process, an electroless plating process, a sputtering process, another applicable process, or a combination thereof. An etching process may be used to pattern the metal material to form the redistribution layer190.

As shown inFIG. 1G, a passivation layer200with openings is formed over the planarization layer180and the passivation layer160, in accordance with some embodiments. The passivation layer200covers the redistribution layer190. The redistribution layer190is partially exposed from the openings of the passivation layer200.

In some embodiments, the passivation layer200is in direct contact with the planarization layer180. In some embodiments, the passivation layer200does not fill or extend into the gap172. In some embodiments, the passivation layer200is separated from the package layer170by the planarization layer180in the gap172.

In some embodiments, the passivation layer200is made of PBO, BCB, silicone, acrylates, siloxane, another suitable material, or a combination thereof. In some other embodiments, the passivation layer200is made of non-organic materials. The non-organic materials includes silicon oxide, un-doped silicate glass, silicon oxynitride, SR, silicon nitride, silicon carbide, HMDS, another suitable material, or a combination thereof.

Multiple deposition, coating, and/or etching processes may be used to form the passivation layer200with the openings. For example, a CVD process or a spin-on coating process may be used to deposit the passivation layer200. Afterwards, an etching process may be used to form the openings of the passivation layer200.

Subsequently, a patterned redistribution layer210is formed over the passivation layer200, as shown inFIG. 1G. The redistribution layer210extends into the openings of the passivation layer200and is electrically connected to the redistribution layer190.

Afterwards, a passivation layer220with openings, a patterned redistribution layer230, and a passivation layer240with openings are sequentially formed over the redistribution layer210, as shown inFIG. 1G. The passivation layer220partially covers the redistribution layer210. The redistribution layer230extends into the openings of the passivation layer220and is electrically connected to the redistribution layer210. The passivation layer240partially covers the redistribution layer230.

In some embodiments, the materials and/or formation methods of the redistribution layers210and230are similar to those of the redistribution layer190. In some embodiments, the materials and/or formation methods of the passivation layers220and240are similar to those of the passivation layer200.

As shown inFIG. 1G, an under-bump metallization (UBM) element250is formed in the openings of the passivation layer240, in accordance with some embodiments. In some embodiments, the UBM element250includes a diffusion barrier layer and a solderable layer. The diffusion barrier layer may include tantalum nitride, titanium nitride, tantalum, titanium, another suitable diffusion barrier material, or a combination thereof. The solderable layer may be a copper layer on the diffusion barrier layer. In addition to copper, the solderable layer may be a stacking-layer including copper, chromium, nickel, tin, or gold. However, embodiments of the disclosure are not limited thereto.

As shown inFIG. 1G, connectors260are formed over the passivation layer240, in accordance with some embodiments. The connectors260are attached to the UBM element250and fill up the openings of the passivation layer240.

In some embodiments, each of the connectors260includes conductive structures, such as conductive balls or other suitable connectors. In some embodiments, the connectors260include solder, another suitable conductive material, or a combination thereof.

In some embodiments, the connectors260are placed in the openings of the passivation layer240. Afterwards, a reflow process is performed to bond the connectors260and the UBM element250together.

Afterwards, a singulation process is performed to form a single package unit (package structure). Each package unit includes one or more integrated circuit dies120embedded in the package layer170and the planarization layer180. The package unit may be a fan-out chip package. In some embodiments, the singulation process includes a dicing process to cut the package layer170and the planarization layer180along scribe lines by a saw blade or laser beam. However, embodiments of the disclosure are not limited thereto.

Many variations and/or modifications can be made to embodiments of the disclosure.FIGS. 2A and 2Bare cross-sectional views of various stages of a process for forming a package structure, in accordance with some embodiments. In some embodiments, the materials and/or formation methods of the package structure shown inFIGS. 2A and 2Bare similar to those of the package structure shown inFIGS. 1A-1G.

As shown inFIG. 2A, the structure shown inFIG. 1Dis provided. The planarization layer180is then deposited over the surface170B of the package layer170so as to fill up the gap172. In some embodiments, the planarization layer180covers and extends over the active surface120A of the integrated circuit dies120. As a result, the planarization layer180covers the surface160A of the passivation layer160and the surface150A of the conductive pads150.

In some embodiments, the planarization layer180is made of a photosensitive material. Therefore, the planarization layer180is photopatternable and can be patterned by using exposure and developing processes without an etching process. In some embodiments, the planarization layer180includes PBO, PI, another suitable material, or a combination thereof. In some embodiments, the material of the planarization layer180is different from that of the package layer170.

As shown inFIG. 2A, a deposition process184is performed over the surface170B of the package layer170so as to deposit the planarization layer180, in accordance with some embodiments. In some embodiments, the planarization layer180is deposited on the active surface120A of the integrated circuit dies120during the deposition process184. As a result, the conductive pads150become covered by the planarization layer180during the deposition process184.

In some embodiments, the deposition process184includes a spin-on process, a spray coating process, a lamination process, a CVD process, a PVD process, another applicable process, or a combination thereof.

As shown inFIG. 2B, a planarization process186is performed over the surface180A of the planarization layer180, in accordance with some embodiments. As a result, the planarization layer180is thinned. In some embodiments, the planarization process186is performed until the active surface120A of the integrated circuit dies120is exposed. In some embodiments, the planarization layer180is partially removed until the surface150A of the conductive pads150is exposed.

In some embodiments, the planarization process186includes a grinding process, a CMP process, an etching process, another applicable process, or a combination thereof. In some other embodiments, the planarization process186includes exposure and developing processes, another applicable process, or a combination thereof. In some embodiments, exposure and developing processes are used to pattern and thin the planarization layer180. As a result, there is substantially no residue of the planarization layer180on the surface150A of the conductive pads150.

After the planarization process186, the surface180A of the planarization layer180is substantially coplanar with (or substantially aligned to) the active surface120A of the integrated circuit dies120or the surface160A of the passivation layer160. As a result, the surface180A and the surface160A together form a substantially flat surface.

Subsequently, the steps described inFIGS. 1F and 1Gare performed to form the structure shown inFIG. 1G. Afterwards, a singulation process is performed over the structure shown inFIG. 1Gto form a single package unit.

Embodiments of the disclosure provide a package structure with a planarization layer. A die is placed on a temporary adhesive layer. A package layer surrounds the die on the temporary adhesive layer. In some cases, the die would slightly sink into the temporary adhesive layer. After the temporary adhesive layer is removed, a step gap would be formed between the die and the package layer.

In accordance with some embodiments, the step gap is mitigated or eliminated by filling the planarization layer. As a result, a substantially flat surface is provided to form a patterned redistribution layer. Due to the planarization layer, the redistribution layer does not bend or curve towards the package layer. Accordingly, the redistribution layer is prevented from being vulnerable to crack. Therefore, the reliability of the package structure is significantly enhanced.

Furthermore, since the redistribution layer can be formed on a planarized surface, it provides more flexibility in the arrangement of the redistribution layer. For example, the line width and/or the line space of the redistribution layer can be reduced even further. Accordingly, the number of input and output (I/O) connections is greatly increased, in accordance with some embodiments. Therefore, the design flexibility of the package structure is improved and the package structure is suitable for high-end applications with high I/O requirements.

Many variations and/or modifications can be made to embodiments of the disclosure. For example, although the described embodiments provide a package structure having a “fan-out” feature, embodiments of the disclosure are not limited thereto. Embodiments of the disclosure may be applied to any suitable package structure for any suitable technology generation.

In accordance with some embodiments, a package structure is provided. The package structure includes a molding compound having a surface. The package structure also includes an integrated circuit die in the molding compound. The integrated circuit die has a portion protruding from the surface. The package structure further includes a planarization layer covering the surface. The planarization layer surrounds the portion of the integrated circuit die. In addition, the package structure includes a redistribution layer electrically connected to the integrated circuit die. The redistribution layer covers the planarization layer and the integrated circuit die.

In accordance with some embodiments, a package structure is provided. The package structure includes a semiconductor substrate. The package structure also includes a dielectric layer over the semiconductor substrate. The package structure further includes a conductive pad over the dielectric layer. In addition, the package structure includes a passivation layer over the dielectric layer. The conductive pad is partially exposed from a surface of the passivation layer. The package structure also includes a package layer surrounding the semiconductor substrate. The package structure further includes a planarization layer covering the package layer. The planarization layer surrounds the passivation layer and the conductive pad. Furthermore, the package structure includes a redistribution layer electrically connected to the conductive pad. The redistribution layer covers the planarization layer and the surface of the passivation layer.

In accordance with some embodiments, a method for forming a package structure is provided. The method includes providing a carrier substrate. The method also includes forming an adhesive layer over the carrier substrate. The method further includes placing an integrated circuit die over the adhesive layer. The integrated circuit die sinks into the adhesive layer. In addition, the method includes forming a package layer covering the integrated circuit die and the adhesive layer. The method also includes removing the adhesive layer and the carrier substrate. A gap is formed between the integrated circuit die and the package layer. The method further includes forming a planarization layer to fill the gap. Furthermore, the method includes forming a redistribution layer covering the planarization layer and the integrated circuit die.