Semiconductor device having multiple element formation regions and manufacturing method thereof

In a manufacturing of a semiconductor device, at least one of elements is formed in each of element formation regions of a substrate having a main side and a rear side, and the substrate is thinned by polished from a rear side of the substrate, and then, multiple trenches are formed on the rear side of the substrate, so that each trench reaches the main side of the substrate. After that, an insulating material is deposited over an inner surface of each trench to form an insulating layer in the trench, so that the element formation regions are isolated. Thereby, generation of cracks and structural steps in the substrate and separation of element formation regions from the substrate can be suppressed.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based on Japanese Patent Applications No. 2007-220240 filed on Aug. 27, 2007, and No. 2008-106014 filed on Apr. 15, 2008, the disclosures of which are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device having multiple element formation regions and a manufacturing method thereof.

BACKGROUND OF THE INVENTION

According to a manufacturing method of the semiconductor device disclosed in JP-A-2001-144173 corresponding to U.S. Pat. No. 6,524,890 and U.S. Pat. No. 6,879,029, a wafer for forming elements is prepared, and trenches each having a predetermined depth from a main side of the wafer are formed firstly. Subsequently, the trenches are filled with an insulating layer, and then, the wafer is thinned by chemical mechanical polishing from a rear side of the wafer, so that the insulating layer is exposed. Thereby, the insulating layer penetrates the wafer and element formation regions can be isolated by the insulating layer.

In the above-mentioned manufacturing method, after the trenches each having the predetermined depth from the main side of the wafer is filled with the insulating layer, the wafer is thinned by chemical mechanical polishing from the rear side of the wafer. Thus, a surface including both a silicon substrate configuring the wafer and the insulating layer made of such as an oxide film needs to be polished. Therefore, stress due to polishing is concentrated at an interface between the silicon substrate and the insulating layer, and cracks may generate in the silicon substrate, for example. In addition, in case that the wafer is thinned by etching not polishing, structural steps may generate over the rear side of the wafer due to the difference of etching rate between the silicon substrate and the insulating layer.

Moreover, in case that the trenches are not filled sufficiently with the insulating layer, the element formation regions may separate from the wafer by force applied to the element formation regions while the wafer is thinned.

SUMMARY OF THE INVENTION

It is an object of the present disclosure to provide a manufacturing method of a semiconductor device having multiple element formation regions. It is another object of the present disclosure to provide a semiconductor device having multiple element formation regions.

According to a first aspect of the present disclosure, a method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a main side and a rear side; forming at least one of an active element and a passive element in each of a plurality of element formation regions of the substrate at the main side of the substrate; forming an insulating film over the main side of the substrate; thinning the substrate from the rear side of the substrate; forming a plurality of trenches on the rear side of the substrate in such a manner that each trench reaches the insulating film and surrounds a corresponding one of the plurality of element formation regions after the thinning the substrate; and depositing an insulating material over an inner surface of each trench to form an insulating layer in the trench, so that the plurality of element formation regions are isolated from each other.

According to the above configuration, a manufacturing method of a semiconductor device having multiple element formation regions, which suppresses generation of cracks and structural steps and separation of element formation regions, and a semiconductor device formed by the manufacturing method can be obtained.

According to a second aspect of the present disclosure, a semiconductor device includes a semiconductor substrate having a main side and a rear side; a plurality of element formation regions disposed in the substrate; a plurality of trenches, each of which penetrates the substrate, and surrounds a corresponding element formation region; an insulating layer arranged over an inner surface of each trench for isolating the plurality of element formation regions from each other; and at least one of an active element and a passive element arranged in each of the plurality of element formation regions at the main side of the substrate. The insulating layer is arranged over the rear side of the substrate. The insulating layer in each trench is continuously connected to the insulating layer over the rear side.

According to the above configuration, a manufacturing method of a semiconductor device having multiple element formation regions, which suppresses generation of cracks and structural steps and separation of element formation regions, and a semiconductor device formed by the manufacturing method can be obtained.

According to a third aspect of the present disclosure, a method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a main side and a rear side; forming at least one of an active element and a passive element in each of a plurality of element formation regions of the substrate at the main side of the substrate; forming an insulating film over the main side of the substrate; forming a conductive body over the insulating film; thinning the substrate from the rear side of the substrate; forming a plurality of trenches on the rear side of the substrate after the thinning the substrate, wherein each trench reaches the insulating film; depositing an insulating material over a sidewall of each trench to form an insulating layer with a void in the trench, so that the plurality of element formation regions are isolated, wherein the void is formed in the insulating layer around a central axis of the trench; depositing the insulating material over the rear side of the substrate; removing the insulating film over one of the trenches, so that the conductive body is exposed from the rear side of the substrate; depositing a conductive material in the void in each trench and in the one of the trenches; and depositing the conductive material over the rear side of the substrate. The conductive body is electrically coupled with the conductive material over the rear side of the substrate through the conductive material in the one of the trenches.

According to the above configuration, a manufacturing method of a semiconductor device having multiple element formation regions, which suppresses generation of cracks and structural steps and separation of element formation regions, and a semiconductor device formed by the manufacturing method can be obtained.

According to a fourth aspect of the present disclosure, a semiconductor device includes a semiconductor substrate having a main side and a rear side; a plurality of element formation regions disposed in the substrate; a plurality of trenches, each of which penetrates the substrate, and surrounds a corresponding element formation region; an insulating layer arranged at least over a sidewall of each trench for isolating the plurality of element formation regions from each other, and arranged over the rear side of the substrate; a conductive material arranged on the insulating layer in each trench to fill the trench; at least one of an active element and a passive element arranged in each of the plurality of element formation regions at the main side of the substrate; and a conductive body arranged over the main side of the substrate. The conductive material is arranged over the rear side of the substrate and the conductive material in each trench is continuously connected to the conductive material over the rear side. The conductive material in at least one of the trenches contacts the conductive body, and the conductive body is electrically coupled with the conductive material over the rear side of the substrate through the conductive material in the at least one of the trenches.

According to the above configuration, a manufacturing method of a semiconductor device having multiple element formation regions, which suppresses generation of cracks and structural steps and separation of element formation regions, and a semiconductor device formed by the manufacturing method can be obtained.

According to a fifth aspect of the present disclosure, a method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a main side and a rear side; forming at least one of an active element and a passive element in each of a plurality of element formation regions of the substrate at the main side of the substrate; forming an insulating film over the main side of the substrate; thinning the substrate from the rear side of the substrate; forming a plurality of trenches on the rear side of the substrate after the thinning the substrate, wherein each trench reaches the insulating film; depositing a first insulating material over a sidewall of each trench to form a first insulating layer with a first void in the trench, so that the plurality of element formation regions are isolated, wherein the first void is formed in the first insulating layer around a central axis of the trench; and depositing a first conductive material in the first void in each trench and over the rear side of the substrate. The plurality of element formation regions are electrically shielded by fixing a potential of the first conductive material in each trench and over the rear side of the substrate.

According to the above configuration, a manufacturing method of a semiconductor device having multiple element formation regions, which suppresses generation of cracks and structural steps and separation of element formation regions, and a semiconductor device formed by the manufacturing method can be obtained.

According to a sixth aspect of the present disclosure, a semiconductor device includes a semiconductor substrate having a main side and a rear side; a plurality of element formation regions disposed in the substrate; a plurality of trenches, each of which penetrates the substrate, and surrounds a corresponding element formation region; a first insulating layer arranged at least over a sidewall of each trench for isolating the plurality of element formation regions from each other, and arranged over the rear side of the substrate; a first conductive material arranged on the first insulating layer in each trench to fill the trench; and at least one of an active element and a passive element arranged in each of the plurality of element formation regions at the main side of the substrate. The first conductive material is arranged over the rear side of the substrate, and the first conductive material in each trench is continuously connected to the first conductive material over the rear side. The plurality of element formation regions are electrically shielded by fixing a potential of the first conductive material in each trench and over the rear side of the substrate.

According to the above configuration, a manufacturing method of a semiconductor device having multiple element formation regions, which suppresses generation of cracks and structural steps and separation of element formation regions, and a semiconductor device formed by the manufacturing method can be obtained.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.FIG. 1is a cross sectional view showing a structure of a substantial portion of a semiconductor device having an element isolation structure according to a first embodiment.

As shown inFIG. 1, a semiconductor device includes a plurality of isolated element formation regions5over a wafer substrate2for forming elements, which is made of a silicon substrate. At least one of active elements (a transistor and a diode or the like) and passive elements (a resistor and a capacitor or the like) using the silicon substrate as a semiconductor substrate (a wafer substrate) is formed in each of the plurality of element formation regions5. For example, in case of the transistor, impurity regions7are formed by implanting an impurity appropriately, which has opposite conductive type from the silicon substrate, from the main side of the silicon substrate. The impurity regions7function as a source region and a drain region. By applying voltage to a gate electrode9, a channel is formed between the source region and the drain region, so that current flows therebetween.

Trenches3are formed to surround the plurality of element formation regions5. An insulating material such as silicon oxide is deposited, so that an insulating layer4is formed inside the trenches3and over a rear side of the wafer substrate2. The plurality of element formation regions5are isolated each other by the insulating layer4.

The trenches3which are filled with the insulating layer4are formed by etching from the rear side of the wafer substrate2as described below. In the etching process, LOCOS (i.e., local oxidation of silicon) films6as insulating films formed in a surface portion of the wafer substrate2are used as etching stoppers. Thus, each of bottoms of the trenches3(each of end portions at the main side of the silicon substrate) contacts the corresponding LOCOS film to terminate. STI (i.e., shallow trench isolation) films may be used as the etching stoppers not LOCOS films. It is possible to use interlayer insulating films such as BPSG (i.e., boro-phospho silicate glass) films as etching stoppers. However, it is preferable to use insulating oxide films such as the above-mentioned LOCOS films and STI films, which have the thickness greater than or equal to sub-microns, in order to improve etching selectivity with the silicon substrate.

A thermal oxide film8is formed over the main side of the wafer substrate2after forming the above-mentioned active elements and passive elements. The above-mentioned gate electrode9is formed over the thermal oxide film8. The gate electrode9is made from a conductive body such as polysilicon, tungsten and aluminum. After that, an interlayer insulating film10such as a BPSG film and an NSG film is deposited and formed over the thermal oxide film8or the gate electrode9. Moreover, electrodes11and pads12of the active elements and the passive elements, which are formed in the plurality of element formation regions5, are formed at portions in which the interlayer insulating film10and the thermal oxide film8are removed by etching.

Next, a manufacturing method of the semiconductor device1having the above-mentioned structure will be described with reference toFIGS. 2A to 2E.

As shown inFIG. 2A, the wafer substrate2for forming elements, which is made of the silicon substrate, is prepared firstly. Desired elements are formed in each of the element formation regions5from the main side of the silicon substrate. After that, the thermal oxide film8, the gate electrode9, the interlayer insulating films10, electrodes11, and a passivation films13or the like are formed. According to the manufacturing method of the present embodiment, the semiconductor elements each having the foregoing structure are formed firstly over a plurality of regions of the wafer substrate2.

Next, as shown inFIG. 2B, the wafer substrate2is thinned by mechanical polishing from the rear side of the wafer substrate2(thinning step). In this case, unlike the conventional way that a surface including both a semiconductor substrate and an insulating layer is polished, a surface including only a semiconductor substrate is polished. Thus, the rear side of the wafer substrate2can be polished uniformly without generating cracks and structural steps by ordinaly mechanical polishing. Polishing is not limited to the mechanical polishing. Techniques such as chemical mechanical polishing, wet etching and dry etching may be used.

Moreover, in the thinning process, the wafer substrate2is polished until the thickness of the wafer substrate2becomes less than or equal to 150 μm, for example. Thereby, it becomes easy to form the trenches3and to deposit the insulating material inside the trenches3. However, as the thickness of the wafer substrate2becomes thin, the mechanical strength of the wafer substrate2decreases. Therefore, cracks may generate in the wafer substrate2and handling the wafer substrate2may become difficult.

Therefore, it is common that the wafer substrate2is thinned with a supporting base attached to the main side of the wafer substrate2for keeping the mechanical strength when the wafer substrate2is thinned by polishing from the rear side of the wafer substrate2. Alternatively, the supporting base may not be attached. In this case, it is preferable that only a central region2asurrounded by outer regions2bis polished, not a whole surface of the wafer substrate2. Hereby, only the central region2ais thinned, and the outer regions2bremain without being thinned the thickness thereof. As a result, the decrease of the mechanical strength can be suppressed even if the wafer substrate2is thinned.

Moreover, in the process that the supporting base is attached, it becomes difficult to perform the process in the atmosphere greater than or equal to 200 degree Celsius because of the restriction of the retention temperature of an adhesive used for the attachment. However, as described above, the supporting base is not needed when the outer regions2bof the wafer substrate2remain without being thinned, it becomes possible to perform in the atmosphere greater than or equal to 200 degree Celsius. It is preferable that the thickness of the outer regions2bare greater than or equal to 250 μm to suppress the decrease of the mechanical strength.

Next, as shown inFIG. 2C, the trenches3are formed by dry etching from the rear side of the wafer substrate2, which is thinned. The trenches3are formed to surround each of the element formation regions5. The etching stops by the insulating films when the trenches3reach the insulating films (the LOCOS films6) in the surface portion of the wafer substrate2.

In the present embodiment, when the trenches3are formed, the thermal oxide film8, the interlayer insulating films10have been already formed over the wafer substrate2. Although the trenches3penetrating the wafer substrate2are formed to surround each of the plurality of element formation regions5, each of the regions of the wafer substrate2including the plurality of element formation regions5remains to couple with the semiconductor elements through the thermal oxide film8formed over the surface of the wafer substrate2. Therefore, separation of the element formation regions5can be prevented.

Next, as shown inFIG. 2D, an insulating material such as silicon oxide is deposited from the rear side of the wafer substrate2by direct oxidation, chemical vapor deposition or the like. The trenches3are filled with the insulating material, so that the insulating layer4is formed inside the trenches3. Therefore, the insulating layer4is arranged between two adjacent element formation regions5in the wafer substrate2, and the adjacent element formation regions5are isolated. Moreover, the insulating material continued from the inside the trenches3is deposited also over the rear side of the wafer substrate2, so that the insulating layer4is formed. Thereby, protection of the rear side of the wafer substrate2and the insulation property can be ensured.

In the present embodiment, as described above, since each of the regions of the wafer substrate2can remain to couple with the semiconductor elements by the thermal oxide film8or the like formed over the main side of the wafer substrate2, being coupling with each of the regions of the wafer substrate2by filling the trenches3with the insulating layer4is not always needed. For example, the insulating material is deposited over inner surfaces of the trenches3, and voids may remain in vicinity of central axes inside the trenches3.

Finally, as shown inFIG. 2E, the wafer substrate2is divided into a plurality of chips20by die cutting (the separation process). In the separation process, the outer regions2bremaining without being thinned are separated from the plurality of chips20. A semiconductor chip20having an element isolation structure according to the present embodiment is completed through the above-mentioned steps.

Second Embodiment

Next, a second embodiment of the present disclosure will be described.FIG. 3is a cross sectional view showing a structure of a substantial portion of a semiconductor device having an element isolation structure according to the second embodiment.

The differences between the first embodiment and the second embodiment are that, an insulating material is deposited over surfaces of sidewalls of trenches3, voids in vicinity of central axes of the trenches3aare filled with a conductive material14made of metal having relatively low melting point, for example, less than or equal to 1100 degree Celsius (such as copper or aluminum), and the conductive material14in a portion of the trenches3is electrically coupled with an electrode9aformed over a surface of a wafer substrate2, in a semiconductor device of the second embodiment. However, polysilicon having relatively high melting point may be used as the conductive material14. The structure of the semiconductor device and the manufacturing method thereof according to the second embodiment are similar to those according to the first embodiment.

The insulating layer4is formed between each of two adjacent element formation regions5, and the DC component of the electrical signal generated in each of the element formation regions5can be blocked. However, since the AC component of the electrical signal can not be blocked completely, a malfunction may occur by propagation of the AC component. However, the interference of electric potential by the AC component between the adjacent element formation regions5can be prevented by fixing electric potential of the conductive material14in the trenches3surrounding the element formation regions5, as shown in the above-mentioned configuration.

It is noted that the structure which can obtain the electrical shield between the isolated element formation regions is disclosed in JP-A-H04-154147 corresponding to U.S. Pat. No. 5,442,223. Specifically, a plurality of element formation regions are formed over an SOI substrate, and trenches between the element formation regions covered by an oxide film are filled with a polysilicon film.

However, in the element isolation structure like this, a conductive layer has already been formed over lower sides and lateral sides of the element formation regions in the semiconductor element forming steps. Therefore, in order to stand high temperature thermal treatment in the element forming steps, polysilicon or a high melting point metal such as tungsten needs to be used as the conductive layer, and the resistivity of the conductive layer becomes high. Moreover, in the conventional element isolation structure, the SOI substrate is used to arrange the conductive layer over lower sides of the element formation regions. In addition to using the conductive layer having high melting point, the manufacturing cost becomes high.

On the other hand, in the present embodiment, trenches3can be filled with the conductive material14after forming elements in the plurality of element formation regions5. Therefore, metal having relatively low melting point such as aluminum or copper can be used for the conductive material14. Moreover, the conductive material14can surround the plurality of element formation regions5by just depositing the conductive material14, so that the manufacturing cost can be decreased.

In order to fill trenches3with the conductive material14, firstly, voids remain in vicinity of central axes of the trenches3and the insulating material is deposited over surfaces of sidewalls of the trenches3, so that the insulating layer4is formed over inner surfaces of the trenches3. At this time, the insulating material is deposited and the insulating layer4is formed over the rear side of the wafer substrate2.

Next, in one of the trenches3which is arranged opposite to the electrode9aformed over the main side of the wafer substrate2through the thermal oxide film8, in case that an insulating material is deposited over a bottom of the one of the trenches3at the main side of the wafer substrate2, the insulating material and the thermal oxide film8are removed by anisotropic etching such as ion beam etching, so that the electrode9ais exposed at the bottom of the one of the trenches3. And then, voids located in vicinity of central axes of the trenches3including the one of the trenches3, in which the electrode9ais exposed, are filled with the conductive material14, and the conductive material14is deposited over the rear side of the wafer substrate2. Thereby, the electrode9aover the main side of the wafer substrate2can be electrically coupled with the conductive material14over the rear side of the wafer substrate2through the conductive material14inside the one of the trenches3. Thereby, the conductive material14which is terminated in other trenches of trenches3except the one of the trenches3can also be electrically coupled with the electrode9aover the main side of the wafer substrate2.

In this structure, when applying a predetermined potential to the electrode9aover the main side of the wafer substrate2, the conductive material14arranged inside the trenches3and over the rear side of the wafer substrate2, which is electrically coupled with the electrode9a, is fixed to the predetermined potential. Therefore, the interference of electric potential by the AC component between the adjacent element formation regions5can be prevented. It is preferred that the predetermined potential is fixed to the ground potential. Thereby, the electric power consumption can be reduced and the interference of electric potential between the adjacent element formation regions can be prevented.

Third Embodiment

Next, a third embodiment of the present disclosure will be described.FIG. 4is a cross sectional view showing a structure of a substantial portion of a semiconductor device having an element isolation structure according to the third embodiment.

In the present embodiment, one of the element formation regions5is replaced by a vertical element formation region16, and a surface electrode9bis formed over a main side of a wafer substrate2, and a back surface electrode15is formed over a rear side of the wafer substrate2. Moreover, the back surface electrode15is joined to a conductive plate19through a conductive joining member18. Although not shown in the drawings, the other structures of the semiconductor device of the third embodiment are same as those of the second embodiment including a structure that the conductive material14arranged inside the trenches3and over the rear side of the wafer substrate2is fixed to the predetermined potential by the electrode9aformed over the main side of the wafer substrate2.

The back surface electrode15deposited over the rear side of the wafer substrate2is formed by the same material with the conductive material14, for example. An insulating layer17is formed between the back surface electrode15and the conductive material14for obtaining isolation. In order to obtain the structure having the back surface electrode, firstly, the conductive material14having a predetermined thickness is deposited over the rear side of the wafer substrate2. After that, a portion of the conductive material14, in which the back surface electrode15of the vertical element formation region16is formed later, and a region surrounding the portion are removed by etching. Next, an insulating material such as silicon oxide is deposited by chemical vapor deposition or the like to form the insulating layer17. And then, a portion of the insulating layer17, in which the back surface electrode15is formed later, is removed by etching, and another conductive material is deposited over the rear side of the wafer substrate2to form the back surface electrode15. When the portion of the insulating layer17, in which the back surface electrode15is formed later, is removed, an insulating layer4, which has already been formed, is also removed.

After that, the back surface electrode15is joined to the conductive plate19with the joining member18made of such as solder, silver paste or metallic nanoparticle, for example. The conductive plate19is a metal frame supporting a semiconductor chip20when the semiconductor ship20is packaged, or a copper foil provided over a surface of a mother board when the semiconductor chip20is mounted on the mother board.

That is, in the semiconductor device of the third embodiment, two conductive materials are laminated over the rear side of the wafer substrate2through the insulating layer17, the conductive material14for electrically shielding the element formation regions5is isolated from the layers including the conductive materials such as the joining member18and the conductive plate19, which are formed over an opposite surface to a surface attached to the wafer substrate2, by the insulating layer17. On the other hand, the conducting material for providing the back surface electrode15of the vertical element formation region16penetrates the insulating layer17so that the back surface electrode15is electrically coupled with the layers including the conductive materials, which are formed over the opposite surface. Therefore, the layers including the conductive materials become a part of the back surface electrode15.

According to the semiconductor device of the third embodiment configured as described above, even if the back surface electrode15of the vertical element formation region16is formed over the rear side of the wafer substrate2, with respect to the element formation regions5other than the vertical element formation region16, the conductive material14for electrically shielding each of the element formation regions5can be formed over the rear side of the wafer substrate2. The conductive plate19can be used as a connecting terminal of the back surface electrode15by joining the conductive plate19to the back surface electrode15. Moreover, the conductive plate19promotes heat release of the element formation regions5and16, and heat release property can be improved.

Next, a modification of the third embodiment will be described.FIG. 5is a cross sectional view showing a structure of a substantial portion of a semiconductor device according to the modification of the third embodiment. In the above-mentioned third embodiment, two conductive materials are laminated with the insulating layer17interposed therebetween. On the other hand, in the modification shown inFIG. 5, the conductive material14for electrically shielding the element formation regions5is a single-layered structure, and a back surface electrode15aof the vertical element formation region16is formed to be thicker than the conductive material14. An insulating layer17ahaving a thickness which equals to the difference between the back surface electrode15aand the conductive material14is formed over the conductive material14. Therefore, the back surface electrode15aand the insulating layer17aprovide the same surface opposite to the surface attached to the wafer substrate2. The surface configured by the back surface electrode15aand the insulating layer17ais joined to the conductive plate19through the conductive joining member18.

In this structure, the back surface electrode15ais isolated from the conductive material14by the insulating layer17a. Since the thickness of the back surface electrode15aof the vertical element formation region16is larger than that of the conductive material14for electrically shielding the element formation regions5, the conductive plate19is electrically coupled with only the back surface electrode15a. Therefore, the conductive plate19can be used as the connecting terminal of the back surface electrode15a.

Fourth Embodiment

Next, a fourth embodiment of the present disclosure will be described. In the above-mentioned second and third embodiments, potential of the conductive material14in the trenches3and over the rear side of the wafer substrate2are fixed to the predetermined potential by conducting the electrode9aformed over the main side of the wafer substrate2with the conductive material14in the trenches3. However, since electrode wirings of each of elements or the like need to be formed over the main side of the wafer substrate2, a space for providing the electrode9ais limited. Thus, radiuses of the conductive material14in the trenches3are small, and impedance becomes relatively high. Particularly, potential of the conductive material14in the trenches3, which are not coupled with the electrode9adirectly, may not be fixed to the predetermined potential stably.

In a semiconductor device of the present embodiment, the conductive material14inside the trenches3and over the rear side of the wafer substrate2is fixed to the predetermined potential by using the conductive plate19joined to the rear side of the wafer substrate2.

FIG. 6is a cross sectional view showing a structure of a substantial portion of the semiconductor device having an element isolation structure according to the fourth embodiment. As shown inFIG. 6, the conductive material14is formed inside the trenches3and over the rear side of the wafer substrate2. In the present embodiment, the conductive plate19is joined to the conductive material14formed over the rear side of the wafer substrate2, which is formed in this manner, through the conductive bonding member18. The ground potential is applied to the conductive plate19as the predetermined potential. Thereby, the potential of the conductive material14inside the trenches3and over the rear side of the wafer substrate2through the conductive plate19can be fixed to the predetermined potential.

Particularly, in the present embodiment, the potential of the conductive material14is fixed by the conductive plate19, which covers at least portions in which at least the trenches3are formed. In other words, since the potential of the conductive material14in one of the trenches3needs not to be fixed to the predetermined potential via the conductive material14having thin radius in another one of the trenches, the electrical connection with low impedance can become possible. Therefore, the potential of the conductive material14inside the trenches3and over the rear side of the wafer substrate2can be kept to the predetermined potential stably.

Next, a modification of the fourth embodiment will be described.FIG. 7is a cross sectional view showing a structure of a substantial portion of a semiconductor device according to a modification of the fourth embodiment. In the modification shown inFIG. 7, one of the element formation regions5is replaced by a vertical element formation region16. The back surface electrode15of the vertical element formation region16is arranged at the rear side of the wafer substrate2. The conductive plate19is divided into an electrode plate19acoupled with the back surface electrode15and a conductive plate19bcoupled with the conductive material14in order to applying a predetermined potential to the conductive material14in the trenches3and over the rear side of the wafer substrate2by using the conducive plate19over the rear side of the wafer substrate2. An insulating portion19cis arranged between the electrode plate19aand the conductive plate19b, and the electrode plate19aand the conductive plate19bare isolated from each other.

In this configuration, the conductive material14in the trenches3and over the rear side of the wafer substrate2can be fixed, and the back surface electrode15of the vertical element formation region16can function as the connecting terminal by using the conductive plate19.

As the conductive plate19, a plate, in which the electrode plate19acouples with the conductive plate19bthrough the insulating portion19c, may be prepared in advance, and then the plate is joined to the wafer substrate2. Alternatively, after the conductive plate19is joined to the wafer substrate2, a portion corresponding to the insulating portion19cmay be removed and an insulating material may be inserted to the removed portion.

Although the preferable embodiments are described, the present invention does not limit to the above-mentioned embodiments, and various modifications may be made without departing from the scope of the invention.

For example, as shown inFIG. 8, after the conductive material14is deposited in the trenches3, voids may remain in vicinity of central axes inside the trenches3. It takes a long time to fill the trenches3completely with the conductive material14, so that the manufacturing cost increases. Moreover, since the conductive material14in the trenches3are arranged to prevent the interference of electric potential between the adjacent element formation regions5, some voids do not disturb the function of the trenches3.

Moreover, as shown inFIG. 9, when the trenches3is formed in the wafer substrate2, the trenches3may intersect with an impurity diffusion layer7ain the element formation regions5. Thereby, the dimensions of the elements, and the cost of the semiconductor chips20can be reduced.

In addition, the trenches3are formed to surround the element formation regions5, for example. In case that the insulating layer4is formed inside the trenches3to isolate elements, various arrangements of the element formation regions are possible.

For example, inFIG. 10, an element formation region21is surrounded by a trench22, in which an insulating film is formed, and without contacting other element formation regions with a separation region (a field region)23interposed therebetween. In this case, testing for confirming insulating property of the trench22can be performed by applying voltage between the field region23and the element formation region21. Moreover, the interference of electric potential of the element formation region21can be suppressed by fixing the potential of the field region23.

Moreover, a plurality of element formation regions24may be arranged adjacent to each other by being separated with one trench25. In this case, the element formation regions24can be arranged in the high density, and therefore, more semiconductor chips can be obtained from a wafer substrate2.

In addition, an element formation region26may be isolated by being separated with a plurality of trenches27and28. In this case, voltage can be shared by the plurality of trenches27and28, and therefore, an element, to which the high voltage is applied, can be arranged in the element formation region26.