Amplifier with enhanced linearity

An apparatus includes a first amplifier that includes a transistor that is coupled to an input terminal of the first amplifier. The transistor is biased to operate in a first mode based on a first operating point. The apparatus also includes a second amplifier coupled in parallel with the first amplifier. The second amplifier includes a second transistor coupled to an input terminal of the second amplifier. The second transistor is biased to operate in a second mode based on a second operating point that is temperature-dependent.

The present disclosure is generally related to enhancing linearity of an amplifier.

III. DESCRIPTION OF RELATED ART

Wireless telephones may include amplifiers (e.g., driver amplifiers and power amplifiers) to amplify transmission signals (e.g., signals to be transmitted over a wireless network). Transmission signal quality (e.g., error vector magnitude (EVM)) and spectrum emission regulations (e.g., adjacent channel leakage ratio (ACLR)) may be affected by the linearity of the amplifiers. For example, an amplifier with relatively high linearity may achieve efficient EVM and ACLR. Amplifiers utilizing a multi-gated transistor (MGTR) topology (e.g., a superposition linearization technique) may achieve relatively high linearity; however, MGTR topologies are sensitive to temperature changes and process variations. As a result, performance (e.g., linearity) of MGTR topologies may be satisfactory under specific operating conditions (e.g., specific temperatures and/or process variations) and may significantly degrade when the specific operations conditions change.

V. DETAILED DESCRIPTION

The detailed description set forth below is intended as a description of exemplary designs of the present disclosure and is not intended to represent the only designs in which the present disclosure can be practiced. The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other designs. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary designs of the present disclosure. It will be apparent to those skilled in the art that the exemplary designs described herein may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary designs presented herein.

FIG. 1shows a wireless device110communicating with a wireless communication system120. Wireless communication system120may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a wireless local area network (WLAN) system, or some other wireless system. A CDMA system may implement Wideband CDMA (WCDMA), CDMA 1×, Evolution-Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity,FIG. 1shows wireless communication system120including two base stations130and132and one system controller140. In general, a wireless system may include any number of base stations and any set of network entities.

Wireless device110may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. Wireless device110may be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a cordless phone, a wireless local loop (WLL) station, a Bluetooth device, etc. Wireless device110may communicate with wireless system120. Wireless device110may also receive signals from broadcast stations (e.g., a broadcast station134), signals from satellites (e.g., a satellite150) in one or more global navigation satellite systems (GNSS), etc. Wireless device110may support one or more radio technologies for wireless communication such as LTE, WCDMA, CDMA 1×, EVDO, TD-SCDMA, GSM, 802.11, etc.

FIG. 2shows a block diagram of an exemplary design of wireless device110inFIG. 1. In this exemplary design, wireless device110includes a transceiver220coupled to a primary antenna210, a transceiver222coupled to a secondary antenna212, and a data processor/controller280. Transceiver220includes multiple (K) receivers230pato230pkand multiple (K) transmitters250pato250pkto support multiple frequency bands, multiple radio technologies, carrier aggregation, etc. Transceiver222includes multiple (L) receivers230sato230sland multiple (L) transmitters250sato250slto support multiple frequency bands, multiple radio technologies, carrier aggregation, receive diversity, multiple-input multiple-output (MIMO) transmission from multiple transmit antennas to multiple receive antennas, etc.

In the exemplary design shown inFIG. 2, each receiver230pa,230pk,230sa,230slincludes an LNA240pa,240pk,240sa,240sland a receive circuit242pa,242pk,242sa,242sl, respectively. For data reception, antenna210receives signals from base stations and/or other transmitter stations and provides a received RF signal, which is routed through an antenna interface circuit224and presented as an input RF signal to a selected receiver. Antenna interface circuit224may include switches, duplexers, transmit filters, receive filters, matching circuits, etc. The description below assumes that receiver230pais the selected receiver. Within receiver230pa, an LNA240paamplifies the input RF signal and provides an output RF signal. Receive circuits242padownconvert the output RF signal from RF to baseband, amplify and filter the downconverted signal, and provide an analog input signal to data processor280. Receive circuits242pamay include mixers, filters, amplifiers, matching circuits, an oscillator, a local oscillator (LO) generator, a phase locked loop (PLL), etc. Each remaining receiver230in transceivers220and222may operate in similar manner as receiver230pa.

In the exemplary design shown inFIG. 2, each transmitter250pa,250pk,250sa,250slincludes a transmit circuit252pa,252pk,252sa,252sland a power amplifier (PA)254pa,254pk,254sa,254sl, respectively. For data transmission, data processor280processes (e.g., encodes and modulates) data to be transmitted and provides an analog output signal to a selected transmitter. The description below assumes that transmitter250pais the selected transmitter. Within transmitter250pa, transmit circuits252paamplify, filter, and upconvert the analog output signal from baseband to RF and provide a modulated RF signal. Transmit circuits252pamay include amplifiers, filters, mixers, matching circuits, an oscillator, an LO generator, a PLL, etc. A PA254pareceives and amplifies the modulated RF signal and provides a transmit RF signal having the proper output power level. The transmit RF signal is routed through antenna interface circuit224and transmitted via antenna210. Each remaining transmitter250in transceivers220and222may operate in similar manner as transmitter250pa.

FIG. 2shows an exemplary design of receiver230and transmitter250. A receiver and a transmitter may also include other circuits not shown inFIG. 2, such as filters, matching circuits, etc. All or a portion of transceivers220and222may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. For example, LNAs240and receive circuits242may be implemented on one module, which may be an RFIC, etc. The circuits in transceivers220and222may also be implemented in other manners.

In an exemplary embodiment, the transmit circuits252pa,252pk,252sa,252slmay include driver amplifiers290pa,290pk,290sa,290sl, respectively. The driver amplifiers290pa,290pk,290sa,290slmay receive transmission signals (e.g., input signals) from the controller280. Each driver amplifier290pa,290pk,290sa,290slmay include a first amplifier and a second amplifier coupled in parallel with the first amplifier. The first amplifier may include a first transistor and the second amplifier may include a second transistor. The first transistor may be biased to operate in a first mode based on a first voltage signal, and the second transistor may be biased to operate in a second mode based on a second voltage signal, as described in greater detail with respect toFIGS. 3-8.

In an exemplary embodiment, the power amplifiers254pa,254pk,254sa,254slmay receive output signals from the driver amplifiers290pa,290pk,290sa,290sl, respectively. One or more of the power amplifiers254pa,254pk,254sa,254sland/or one or more of the driver amplifiers290pa,290pk,290sa,290slmay include a first amplifier (e.g., the first amplifier306ofFIG. 3) and a second amplifier (e.g., the second amplifier308ofFIG. 3) coupled in parallel with the first amplifier. The first amplifier may include a first transistor (e.g., the first transistor316ofFIG. 3) and the second amplifier may include a second transistor (e.g., the second transistor326ofFIG. 3). The first transistor may be biased to operate in a first mode based on a first voltage signal (e.g., a first operating point), and the second transistor may be biased to operate in a second mode based on a second voltage signal (e.g., a second operating point), as described in greater detail with respect toFIGS. 3-8. For example, the amplification circuitry302ofFIG. 3may correspond to one or more of the power amplifiers254pa,254pk,254sa,254sland/or one or more of the driver amplifiers290pa,290pk,290sa,290sl.

Data processor/controller280may perform various functions for wireless device110. For example, data processor280may perform processing for data being received via receivers230and data being transmitted via transmitters250. Controller280may control the operation of the various circuits within transceivers220and222. For example, the controller280may include biasing and control circuitry284(e.g., the biasing and control circuitry304ofFIG. 3) to bias the first transistor and the second transistor to operate in the first mode or the second mode, respectively. A memory282may store program codes and data for data processor/controller280. Data processor/controller280may be implemented on one or more application specific integrated circuits (ASICs) and/or other ICs.

Wireless device110may support multiple band groups, multiple radio technologies, and/or multiple antennas. Wireless device110may include a number of LNAs to support reception via the multiple band groups, multiple radio technologies, and/or multiple antennas.

Referring toFIG. 3, a diagram of a system300that is operable to enhance linearity of an amplifier is shown. The system300includes amplification circuitry302and biasing and control circuitry304. In an exemplary embodiment, the amplification circuitry302may be included in a power amplifier or a driver amplifier. For example, the amplification circuitry302may be one or more of the power amplifiers254pa,254pk,254sa,254slofFIG. 2. In addition, or alternatively, the amplification circuitry302may be one or more of the driver amplifiers290pa,290pk,290sa,290slofFIG. 2. The biasing and control circuitry304may be included on a “chip” associated with the transceivers220,222ofFIG. 2and/or may be included in the controller280ofFIG. 2.

The amplification circuitry302includes a first amplifier306and a second amplifier308coupled in parallel with the first amplifier306. The first amplifier306may include multiple branches (e.g., unit cells). For example, the first amplifier306may include a first branch310, a second branch312, and an Nthbranch314. In an exemplary embodiment, N is any integer greater than zero. For example, if N is equal to two, the first amplifier306would include two branches. In a similar manner, the second amplifier308may include multiple branches. For example, the second amplifier308may include a first branch320, a second branch322, and a Kthbranch324. In an exemplary embodiment, K is any integer greater than zero. For example, if K is equal to seven, the second amplifier308would include seven branches.

The first branch310may include a first transistor316and a first switch318(e.g., a pair of cascoded transistors). In an exemplary embodiment, the first transistor316and the first switch318are n-type metal oxide semiconductor (NMOS) transistors. A source of the first transistor316may be coupled to ground, and a drain of the first transistor316may be coupled to a source of the first switch318. A drain of the first switch318may be coupled to a supply voltage (Vdd) via a first inductor (L1). A gate of the first transistor316may be coupled to receive a first portion of an input signal (IN) via a first capacitor (C1). In an exemplary embodiment, the input signal (IN) is a transmission signal (e.g., a voltage signal). For example, the input signal (IN) may be the transmission signal292pa,292pk,292sa,292slprovided to the driver amplifiers290pa,290pk,290sa,290slofFIG. 2, the output signal294pa,294pk,294sa,294slof the driver amplifiers290pa,290pk,290sa,290slprovided to the power amplifiers254pa,254pk,254sa,254slofFIG. 2, or any combination thereof. As explained below, the gate of the first transistor316may also be biased based on a first voltage signal (V1). A gate of the first switch318may be coupled to receive a first control signal (ENM). In an exemplary embodiment, the first control signal (ENM) is a multi-bit digital code that selectively causes the first switch318to conduct (e.g., selectively activates the first branch310), as explained in further detail with respect toFIG. 5.

Each branch312-314may be coupled in parallel and may have a substantially similar configuration as the first branch310. For example, the second branch312and the Nthbranch314may include a second transistor (not shown) and an Nthtransistor (not shown), respectively. The second branch312and the Nthbranch314may also include a second switch (not shown) and an Nthswitch (not shown), respectively. The gates of the second transistor and the Nthtransistor may be coupled to receive the first portion of the input signal (IN), and the gates of the second switch and the Nthswitch may be coupled to receive the first control signal (ENM). In an exemplary embodiment, each switch of the first amplifier306may be coupled to receive voltage signals that correspond to different bits of the first control signal (ENM) so that the first control signal (ENM) may selectively activate particular branches310-314and selectively deactivate other branches310-314. For example, the first switch318may be coupled to receive a first voltage signal corresponding to a first bit of the first control signal (ENM), the second switch may be coupled to receive a second voltage signal corresponding to a second bit of the first control signal (ENM), etc.

The first branch320may include a second transistor326and a first switch328(e.g., a pair of cascoded transistors). In an exemplary embodiment, the second transistor326and the first switch328are NMOS transistors. A source of the second transistor326may be coupled to ground, and a drain of the second transistor326may be coupled to a source of the first switch328. A drain of the first switch328may be coupled to the supply voltage (Vdd) via the first inductor (L1). A gate of the second transistor326may be coupled to receive a second portion of the input signal (IN) via a second capacitor (C2). As explained below, the gate of the second transistor326may also be biased based on a second voltage signal (V2) (e.g., a temperature-dependent voltage signal). A gate of the first switch318may be coupled to receive a second control signal (ENA). In an exemplary embodiment, the second control signal (ENA) is a multi-bit digital code that selectively causes the first switch328to conduct (e.g., selectively activates the first branch320).

Each branch322-324may be coupled in parallel and may have a substantially similar configuration as the first branch320. For example, the second branch322and the Kthbranch324may include a transistor (not shown) and a Kthtransistor (not shown), respectively. The second branch322and the Kthbranch324may also include a second switch (not shown) and a Kthswitch (not shown), respectively. The gates of the second transistor and the Kthtransistor may be coupled to receive the second portion of the input signal (IN), and the gates of the second switch and the Kthswitch may be coupled to receive the second control signal (ENA). In an exemplary embodiment, each switch of the second amplifier308may be coupled to receive voltage signals that correspond to different bits of the second control signal (ENA) such that the second control signal (ENA) may selectively activate particular branches320-324and selectively deactivate other branches320-324.

The biasing and control circuitry304includes a process monitor340, a ratio arbitrator342, a temperature sensor344, and an offset bias generator346. In a first exemplary embodiment, the process monitor340may include circuitry to monitor process variations of the system300. For example, the process monitor340may dynamically monitor (e.g., monitor “on the fly”) characteristics (e.g., process speeds) of the system300to determine a process corner of the system300(e.g., process variations of a transceiver chip). The process corner may be provided to the ratio arbitrator342as process data (Pdata). For example, the process data (Pdata) may indicate whether the process corner of the system300is fast-fast (FF, corresponding to fast process, typical-typical (TT, corresponding to typical process), slow-slow (SS, corresponding to slow process), or some relative information normalized to a known reference process corner.

Referring toFIG. 9, an illustrative embodiment of a third-order derivative of a transistor I-V curve900is shown. Each trace on the curve900illustrates the positive peaks and negative peaks of the third-order derivative for a transistor (e.g., a transistor in the first amplifier306or a transistor in the second amplifier308) for different process corners. As explained below, the non-zero peak values may affect linearity of the amplification circuitry302. MGTR scheme nulls out the negative peak of one transistor through the positive peak of an offset biased auxiliary transistor for linearity improvement. A first trace illustrates positive peaks (+) and negative peaks (−) for a FF process corner, a second trace illustrates positive peaks and negative peaks for a TT process corner, and a third trace illustrates positive peaks and negative peaks for a SS process corner. The relative peak value of the positive and negative peaks may vary over process corners. This leads to process dependent performance variation of the amplifiers. The performance degradation can be mitigated through the ratio adjustment between main and auxiliary path utilizing the biasing and control circuitry304.

In a second exemplary embodiment, the process monitor340may provide a fixed value for the process data. For example, the process corner of the system300may be determined during manufacturing of the system300. In the second exemplary embodiment, the process monitor340may be implemented as a one-time programmable cell (or as a fuse). For example, the voltage across the one-time programmable cell may be provided to the ratio arbitrator342as the process data (Pdata) to indicate the process corner of the system300.

The temperature sensor344may be configured to measure the temperature of the system300. For example, the temperature sensor344may include a temperature-dependent sensing element, such as a thermistor (e.g., a resistor that has a resistance that varies with temperature), to generate temperature measurements of the system300. The temperature measurements may be provided to the ratio arbitrator342and to the offset bias generator346as temperature data (Tdata).

Referring toFIG. 9, an illustrative embodiment of a third-order derivative of a transistor I-V curve902is shown. Each trace on the curve902illustrates the positive peaks (+) and negative peaks (−) of the third-order derivative for a transistor (e.g., a transistor in the first amplifier306or a transistor in the second amplifier308) for different temperatures. As explained below, the peak values may affect linearity of the amplification circuitry302. A first trace illustrates positive peaks and negative peaks for a temperature of −30° Celsius, a second trace illustrates positive peaks and negative peaks for a temperature of 20° Celsius, a third trace illustrates positive peaks and negative peaks for a temperature of 70° Celsius, and a fourth trace illustrates positive peaks and negative peaks for a temperature of 120° Celsius. The voltage offset between a transistor positive peak and a negative peak may be a function of temperature. In addition, the relative peak value of the positive and negative peaks may vary over different temperatures. These effects can be alleviated through a temperature dependent biasing scheme and ratio adjustment.

Linearity of the amplification circuitry302may be compromised due to process variations and temperature variations. The ratio arbitrator342may control a ratio of active branches310-314to active branches320-324based on the process data (Pdata) and the temperature data (Tdata) to enhance linearity of the amplification circuitry302. In an exemplary embodiment, the ratio arbitrator342may be implemented as a lookup table. For example, based on the process corner indicated by the process data (Pdata) and the temperature indicated by the temperature data (Tdata), the ratio arbitrator342may be configured to control the ratio of active branches310-314to active branches320-324. In another exemplary embodiment, the ratio arbitrator342may be implemented as one or more processing elements configured to determine the ratio by inserting the process data (Pdata) and the temperature data (Tdata) into one or more empirical equations.

The ratio arbitrator342is configured to generate the first control signal (ENM) to selectively activate branches310-314, and the ratio arbitrator342is configured to generate the second control signal (ENA) to selectively activate branches320-324. For example, each bit of the first control signal (ENM) (e.g., a multi-bit digital code) may be provided to a switch of a corresponding branch of the branches310-314. To illustrate, a first bit of the first control signal (ENM) may be provided to the gate of the first switch318of the first branch310, a second bit of the first control signal (ENM) may be provided to the gate of the second switch of the second branch312, etc. The first bit of the first control signal (ENM) may selectively activate the first branch310(e.g., enable current from the supply voltage (Vdd) to ground via the first branch310). For example, a logical high voltage signal may activate the first switch318(e.g., enable conduction) when the first bit of the first control signal (ENM) has a logical “1” value, and a logical low voltage signal may deactivate the first switch318(e.g., disable conduction) when the first bit of the first control signal (ENM) has a logical “0” value.

In a substantially similar manner, each bit of the second control signal (ENA) may be provided to a switch in a corresponding branch of the branches320-324. To illustrate, a first bit of the second control signal (ENA) may be provided to the gate of the first switch328of the first branch320, a second bit of the second control signal (ENA) may be provided to the gate of the second switch of the second branch322, etc. The first bit of the second control signal (ENA) may selectively activate the first branch320. For example, a logical high voltage signal may activate the first switch328when the first bit of the second control signal (ENA) has a logical “1” value, and a logical low voltage signal may deactivate the first switch328when the first bit of the first control signal (ENA) has a logical “0” value.

By selectively activating the branches310-314and the branches320-324, an amount of current provided to the matching network330may be adjusted to compensate for process variations and temperature variations. Adjusting the amount of current provided by the branches310-314and the branches320-324, respectively, may lead to cancellation of nonlinear current to the matching network330, which in turn, may adjust (e.g., enhance) linearity and reduce degradation of the input signal (IN) during amplification. For example, the nonlinear components of an output current generated by the branches310-314can be nulled out when activating a proper number of unit cells in the branches320-324with an appropriate offset bias voltage.

Adjusting the amount of current provided to the matching network330(e.g., a load including inductors, capacitors, etc.) may adjust the nonlinear components of the output signal (OUT). High linearity (e.g., increasing the power level of the input signal (IN) with relatively small degradation) may be achieved by adjusting the amount of current provided to the matching network330so that the output signal (OUT) corresponds to an amplified version of the input signal (IN) with relatively small degradation (e.g., content alteration). The adjustment may be made based on process and temperature information to maintain the superior linearity of the output signal (OUT), so is the offset bias voltage.

The first transistor316may be biased to operate in a first mode based on the first voltage signal (V1). For example, the gate of the first transistor316may be biased at the first voltage signal (V1) through a first resistor (R1). The first mode may correspond to a saturation mode (e.g., a strong-inversion mode) of operation. For example, the voltage applied to the gate of the first transistor316may exceed the threshold voltage of the first transistor316(e.g., the gate-to-source voltage is greater than the threshold voltage). Biasing the first transistor316to operate in the first mode may adjust an amount of current flowing through the first branch310, which as described above, may adjust linearity and degradation.

As explained below, the offset bias generator346may be configured to generate the second voltage signal (V2) (e.g., a temperature-dependent voltage signal) and bias the transistors in the branches320-324based on the second voltage signal (V2). For example, the offset bias generator346may be configured to control a voltage offset (e.g., a voltage difference between the first voltage signal (V1) and the second voltage signal (V2)) based on the temperature data (Tdata).

Referring toFIG. 4, an exemplary embodiment of the offset bias generator346is shown. The offset bias generator346may include an operational amplifier402, a temperature-dependent resistor404(e.g., a thermistor), and a temperature-dependent current source406. The temperature-dependent resistor404may have a resistance (R0) that varies with temperature, and the temperature-dependent current source406generates a current (I0) that varies with temperature.

The first voltage signal (V1) may be provided to a positive input terminal of the operational amplifier402. The operational amplifier402may be configured to generate the second voltage signal (V2) based on a feedback path associated with temperature-dependent resistor404and the temperature-dependent current source406. For example, the temperature-dependent resistor404may be coupled to an output of the operational amplifier402and to a negative input terminal of the operational amplifier402. The temperature-dependent current source406may be coupled to provide the current (I0) through the temperature-dependent resistor404. The output of the operational amplifier402may be coupled to provide the second voltage signal (V2) such that the second voltage (V2) is approximately equal to the first voltage of the first voltage signal (V1) minus the product of the resistance (R0) and the current (I0) (e.g., V2=V1−I0*R0).

A first embodiment410of the temperature-dependent current source406includes a reference current source412and a proportional to absolute temperature (PTAT) current source414. The reference current source412may be configured to generate a reference current (IREF) (e.g., a substantially constant current) and provide the reference current (IREF) to a summing node416. The PTAT current source414may be configured to generate a PTAT current (IPTAT) (e.g., a current that varies with temperature) and provide the PTAT current (IPTAT) to the summing node416. The current mixer416may combine the reference current (IREF) with the PTAT current (IPTAT) to generate the current (I0).

A second embodiment420of the temperature-dependent current source406includes an operational amplifier422, a reference resistor424, a first transistor426, and an array of transistors428. A reference voltage (VREF) may be provided to a positive input terminal of the operational amplifier422. A first terminal of the reference resistor424may be coupled to ground, and a second terminal of the reference resistor424may be coupled to a negative input terminal of the operational amplifier422. A gate of the first transistor426may be coupled to an output of the operational amplifier422, and a drain of the first transistor426may be coupled to the second terminal of the reference resistor424. A source of the first transistor426may be coupled to a supply voltage.

The array of transistors428may include multiple transistors that are selectively enabled based on the temperature data (Tdata) to vary the amount of current (I0). For example, the temperature data (Tdata) may a multi-bit digital code configured to selectively activate transistors in the array of transistors428(e.g., increase the current (I0)) and selectively deactivate transistors in the array of transistors428(e.g., decrease the current (I0)). Thus, the current (I0) may be digitally controlled such that a number of active branches (e.g., transistors in the array of transistors428) are programmed based on the temperature data (Tdata).

Referring back toFIG. 3, the second transistor326may be biased to operate in a second mode based on the second voltage signal (V2). For example, the gate of the second transistor326may be biased by the sum of the second voltage of the second voltage signal (V2) and a voltage across a second resistor (R2). The second mode may correspond to a weak-inversion mode or a triode mode of operation. For example, the voltage applied to the gate of the second transistor326may be such that the gate voltage of the second transistor326is close to or less than the threshold voltage of the second transistor326(e.g., the gate-to-source voltage is less than the threshold voltage). Biasing the second transistor326to operate in the second mode may adjust an amount of current flowing through first branch320, which as described above, may adjust linearity and degradation.

For simplicity of illustration, one second amplifier308is depicted inFIG. 3. However, the techniques described above may be extended such that additional auxiliary amplifiers may be added to the amplification circuitry302. For example, additional auxiliary amplifiers may be coupled in parallel to the first amplifier306and the second amplifier308. To illustrate, an auxiliary amplifier (not shown) including one or more branches may include transistors that are biased to operate in a third mode based on a third voltage signal. A voltage of the third voltage signal may be smaller than the second voltage of the second voltage signal (V2) such that the third mode corresponds to an inversion mode having a smaller conduction (e.g., source-to-drain current) than the second mode. Each branch of the auxiliary amplifier may be selectively activated via control signals based on the process data (Pdata) and the temperature data (Tdata) to adjust an amount of current propagating through the auxiliary amplifier. Additional auxiliary amplifiers may enable “wider” linearity tuning range. For example, the amount of linear current provided to the matching network330may be higher based on auxiliary amplifiers configured to provide additional linearity enhancement (e.g., based on transistors in auxiliary amplifiers operating in decreased conductance inversion modes), thereby the linear output power level can be improved.

In another exemplary embodiment, a balloon amplifier (not shown) may be coupled to receive output signals (e.g., voltages) from the first amplifier306and the second amplifier308. The balloon amplifier may be configured to combine the output signals and provide the combined output signals to the matching network330.

Although the system300is described with respect to a single-ended topology, the application of the techniques described above may also be extended to differential topologies. For example, the system300may include two first amplifiers and two second amplifiers. In this case, the ratio arbitrator342may generate a pair of control signals (ENM) for the first amplifiers and a pair of control signal (ENA) for the second amplifiers. Additionally, the offset bias generator346may bias transistors of the second amplifiers based on the second voltage signal (V2).

The system300ofFIG. 3may enhance linearity and reduce degradation of the input signal (IN) during amplification for multi-gated transistor amplification systems. Enhancing linearity may also improve an adjacent channel leakage ratio (ACLR) (e.g., the ratio of the mean power centered on an adjacent channel frequency compared to the mean power centered on the channel frequency associated with the amplification circuitry302). In a particular embodiment, based on temperature-dependent voltage biasing via the offset bias generator346, ACLR may be improved approximately between 3.5 decibels (dBs) and 8 dBs for a Long Term Evolution (LTE) 20 megahertz (MHz) signal across an operational temperature range (e.g., between −30 degrees Celsius and 120 degrees Celsius). Equivalently, power consumption may be reduced by more than 20 percent based on the invented temperature dependent biasing scheme. Additional ACLR improvement and power consumption savings may be realized by adjusting the ratio of active branches310-314to active branches320-324(e.g., adjusting the transistor size ratio).

Referring toFIG. 5, an exemplary embodiment of a circuit500that is configured to selectively activate the first branch310based on process variations and temperature variation is shown. The circuit500may include the first transistor316of the first branch310and the first switch318of the first branch310.

A first bit of the first control signal (ENM) may be provided to a buffer502. Based on a bit value of the first bit of the first control signal (ENM), the buffer502may provide a logical high voltage signal (e.g., a cascoded voltage signal (VCASC)) to the gate of the first switch318or a logical low voltage signal (e.g., a ground voltage) to the gate of the first switch318. For example, the buffer502may provide the cascoded voltage signal (VCASC) to the gate of the first switch318when the bit value of the first bit is a logical “1.” Based on the cascoded voltage signal (VCASC), the first switch318may conduct (e.g., current may flow from source to drain) and the first branch310may be activated. Alternatively, the buffer502may provide the ground voltage to the gate of the first switch318when the bit value of the first bit is a logical “0.” Based on the ground voltage, conduction by the first switch318may be disabled and the first branch310may be deactivated. In a similar manner, a second bit of the first control signal (ENM) may be provided to a buffer (not shown) to selectively activate the second branch312ofFIG. 3.

Although the circuit500ofFIG. 5depicts components of the first branch310, a similar topology may be used to selectively activate other branches of the first amplifier306and branches of the second amplifier308.

Referring toFIG. 6, an exemplary embodiment of a circuit600that is configured to selectively activate a branch610based on process variations and temperature variation is shown. In an exemplary embodiment, the branch610may be alternate embodiment of the first branch310ofFIG. 1. The circuit600may include the first transistor316, the first switch318, and the buffer502. The first transistor316, the first switch318, and the buffer502may operate in a substantially similar manner as described with respect toFIG. 5.

The circuit600may also include a first p-type metal oxide semiconductor (PMOS) transistor616, a first PMOS switch618, and a second buffer602. The input signal (IN) may be provided to a gate of the first PMOS transistor616via the first capacitor (C1). The gate of the first PMOS transistor616may be biased based on the first voltage signal (V1) in a substantially similar manner as the gate of the first transistor316.

An inverted first control signal (ENM′) may be provided to the second buffer602. Based on a bit value of the inverted first control signal (ENM′), the second buffer602may provide a logical high voltage signal (e.g., a cascoded voltage signal (VCASC)) to the gate of the first PMOS switch618or a logical low voltage signal (e.g., a ground voltage) to the gate of the first PMOS switch618. For example, the second buffer602may provide the cascoded voltage signal (VCASC) to the gate of the first PMOS switch618when the bit value of the inverted first control signal (ENM′) is a logical “0.” Based on the cascoded voltage signal (VCASC), the first PMOS switch618may conduct (e.g., current may flow from source to drain) and the branch610may be activated. Alternatively, the second buffer602may provide the supply voltage (Vdd) to the gate of the first PMOS switch618when the bit value of the inverted first control signal (ENM′) is a logical “1.” Based on the supply voltage (Vdd), conduction may be disabled and the branch610may be deactivated.

The circuit600ofFIG. 6may enable the techniques described with respect toFIGS. 3-5to enable “push-pull” amplifiers. For example, the PMOS transistors616,618(e.g., “push-up” transistors) and NMOS transistors316,318(e.g. “pull-down” transistors) may be implemented within a unit cell (e.g., the branch610) to operate in a substantially similar manner as the first branch310ofFIG. 3. Although the circuit600ofFIG. 6depicts components of the branch610, a similar topology may be used to selectively activate other branches of the first amplifier306and branches of the second amplifier308.

Referring toFIG. 7, another exemplary embodiment of a circuit700configured to selectively activate a branch710based on process variations and temperature variation is shown. In an exemplary embodiment, the branch710may be alternate embodiment of the first branch310ofFIG. 1. The branch710may include the first transistor316and the first PMOS transistor616.

A first bit of the first control signal (ENM) may be provided to a first buffer702. Based on a bit value of the first bit of the first control signal (ENM), the first buffer702may pass the first voltage signal (V1) or a logical low voltage signal (e.g., a ground voltage). The first buffer702may pass the first voltage signal (V1) to bias the gate of the first transistor316based on the first voltage signal (V1) when the bit value of the first bit is a logical “1.” For example, the gate of the first transistor316may be biased by the sum of the first voltage signal (V1) and the voltage across the first resistor (R1). Alternatively, the first buffer702may pass the ground voltage to bias the gate of the first transistor316based on the ground voltage when the bit value of the first bit is a logical “0.” Based on the ground voltage, conduction may be disabled and the branch710may be deactivated.

A first bit of the first inverted control signal (ENM′) may be provided to a second buffer704. Based on a bit value of the first bit of the first inverted control signal (ENM′), the second buffer704may pass the first voltage signal (V1) or the supply voltage (Vdd). The second buffer704may pass the first voltage signal (V1) to bias the gate of the first PMOS transistor616based on the first voltage signal (V1) when the bit value of the first bit of the first inverted control signal (ENM′) is a logical “0.” For example, the gate of the first PMOS transistor616may be biased by the sum of the first voltage signal (V1) and the voltage across the first resistor (R1). Alternatively, the second buffer704may pass the supply voltage (Vdd) to bias the gate of the first PMOS transistor616based on the supply voltage (Vdd) when the bit value of the first bit of the first inverted control signal (ENM′) is a logical “1.” Based on the supply voltage (Vdd), conduction may be disabled and the branch710may be deactivated.

The circuit700ofFIG. 7may selectively activate the branch710without using a cascode topology. For example, the buffers702,704may selectively pass the first voltage signal (V1) to bias the gates of the transistors316,616, respectively, based on the first voltage signal (V1). Additionally, the buffers702,704may selectively pass the ground voltage and the supply voltage (Vdd) to the transistors316,616, respectively, to deactivate the branch710.

Referring toFIG. 8, a flowchart that illustrates an exemplary embodiment of a method800of operating a circuit that includes a first amplifier and a second amplifier is shown. In an illustrative embodiment, the method800may be performed using the wireless device110ofFIGS. 1-2, the system300ofFIG. 3, the offset bias generator ofFIG. 4, the first embodiment410of the circuit to generate the current (I0) ofFIG. 4, the second embodiment420of the circuit to generate the current (I0) ofFIG. 4, the circuit500ofFIG. 5, the circuit600ofFIG. 6, the circuit700ofFIG. 7, or any combination thereof.

The method800includes receiving an input signal at a circuit that includes a first amplifier and a second amplifier, at802. For example, referring toFIG. 3, the input signal (IN) may be provided to the first amplifier306via the first capacitor (C1) and to the second amplifier308via the second capacitor (C2).

A transistor of the first amplifier may be biased to operate in a first mode based on a first operating point, at804. For example, referring toFIG. 3, the first transistor316may be biased to operate in the first mode based on the first voltage signal (V1). The gate of the first transistor316may be biased by the sum of the first voltage of the first voltage signal (V1) and a voltage across the first resistor (R1). The first mode may correspond to a saturation mode (e.g., a strong-inversion mode) of operation. For example, the voltage applied to the gate of the first transistor316may be such that the gate voltage of the first transistor316is greater than the threshold voltage of the first transistor316(e.g., the gate-to-source voltage is greater than the threshold voltage). Biasing the first transistor316to operate in the first mode may adjust an amount of current flowing through first branch310, which may adjust linearity and degradation.

A second transistor of the second amplifier may be biased to operate in a second mode based on a second operating point that is temperature-dependent, at806. For example, referring toFIG. 3, the offset bias generator346may generate the second voltage signal (V2) (e.g., a temperature-dependent voltage signal) and bias the transistors in the branches320-324based on the second voltage signal (V2). The second transistor326may be biased to operate in the second mode based on the second voltage signal (V2). For example, the gate of the second transistor326may be biased at the second voltage of the second voltage signal (V2) through the second resistor (R2). The second mode may correspond to a weak-inversion mode or a sub-threshold operation (e.g., the bias voltage is lower than the threshold voltage to turn on a transistor). For example, the voltage applied to the gate of the second transistor326may be such that the gate voltage of the second transistor326is less than the threshold voltage of the second transistor326(e.g., the gate-to-source voltage is less than the threshold voltage). Biasing the second transistor326to operate in the second mode may adjust an amount of current flowing through first branch320, which may adjust linearity and degradation.

The method800ofFIG. 8may enhance linearity (e.g., ACLR) and reduce degradation for multi-gated transistors amplification systems. For example, based on temperature-dependent voltage biasing via the offset bias generator346, ACLR may be improved approximately between 3.5 decibels (dBs) and 8 dBs for LTE 20 megahertz (MHz) signal across an operational temperature range (e.g., between −30 degrees Celsius and 120 degrees Celsius). Equivalently, power consumption may be reduced by more than 20 percent to achieve a similar linearity performance.

In conjunction with the described embodiments, an apparatus includes means for amplifying a first portion of an input signal. For example, the means for amplifying the first portion of the input signal may include the first amplifier306ofFIG. 3, the first branch310ofFIGS. 3 and 6, the second branch312ofFIG. 3, the Nthbranch314ofFIG. 3, the first transistor316ofFIG. 3, the branch610ofFIG. 6, the branch710ofFIG. 7, one or more other devices, circuits, modules, or any combination thereof. The means for amplifying the first portion of the input signal may be biased to operate in a first mode based on a first voltage signal.

The apparatus may also include means for amplifying a second portion of the input signal. The means for amplifying the second portion of the input signal may include the second amplifier308ofFIG. 3, the first branch320ofFIG. 3, the second branch322ofFIG. 3, the Kthbranch324ofFIG. 3, the second transistor326ofFIG. 3, the branch610ofFIG. 6, the branch710ofFIG. 7, one or more other devices, circuits, modules, or any combination thereof. The means for amplifying the second portion of the input signal may be biased to operate in a second mode based on a second voltage signal that is temperature-dependent.