VARIABLE GAIN LOW NOISE AMPLIFIER AND METHOD FOR CONTROLLING GAIN OF VARIABLE GAIN LOW NOISE AMPLIFIER

A variable gain low noise amplifier (LNA) and a method for controlling a gain of the variable gain LNA are provided. The variable gain LNA may include a first transistor, a first degeneration inductor, a second transistor and a second degeneration inductor, wherein the first degeneration inductor is coupled to a source terminal of the first transistor, and the second degeneration inductor is coupled to a source terminal of the second transistor. Gate terminals of the first transistor and the second transistor are configured to receive an input signal. The first transistor and the first degeneration inductor belong to a first branch of the variable gain LNA, and the second transistor and the second degeneration inductor belong to a second branch of the variable gain LNA. More particularly, a gain of the variable gain LNA is determined by controlling whether to turn off the second branch.

BACKGROUND

The present invention is related to low noise amplifiers (LNAs), and more particularly, to a variable gain LNA and a method for controlling a gain of the variable gain LNA.

For an LNA, certain architecture is proposed to optimize performances related to noise figure and gain step (e.g., gain tuning) stability in a related art. However, with this architecture, input matching and input linearity requirements become challenging. For example, parameters of components within the LNA are typically optimized under a condition where the LNA operates in a high gain mode, but input matching and input linearity of the LNA will degrade when the LNA operates in a low gain mode if these parameters are unchanged. In specific, even though the LNA is optimized under the high gain mode condition, when the LNA is switched to the low gain mode, input impedance of the LNA may change, which causes that the input matching condition is no longer optimized. In addition, as the input matching condition changes, the input linearity is thereby impacted.

One of related arts further implements an auxiliary amplifier which is optimized with respect to the low gain mode. However, an additional path provided by the auxiliary amplifier may introduce extra loading for overall architecture, and thereby impact the noise figure. In addition, tracking between two amplifiers may be required for a purpose of gain step stability, where the two amplifiers are independent, which makes the tracking be challenging.

Thus, there is a need for a novel architecture and related method, which can make the LNA properly operate at the optimized condition under all gain gears, or make the performance be less likely to degrade when the LNA operates in the low gain mode condition.

SUMMARY

An objective of the present invention is to provide a variable gain low noise amplifier (LNA) and a method for controlling a gain of the variable gain LNA, which can optimize the input matching condition and input linearity under all gain gears without introducing any side effect or in a way that is less likely to introduce side effects.

At least one embodiment of the present invention provides a variable gain LNA. The variable gain LNA may comprise a first transistor, a first degeneration inductor, a second transistor and a second degeneration inductor, wherein the first degeneration inductor is coupled to a source terminal of the first transistor, and the second degeneration inductor is coupled to a source terminal of the second transistor. Gate terminals of the first transistor and the second transistor are configured to receive an input signal. The first transistor and the first degeneration inductor belong to a first branch of the variable gain LNA, and the second transistor and the second degeneration inductor belong to a second branch of the variable gain LNA. More particularly, a gain of the variable gain LNA is determined by controlling whether to turn off the second branch.

At least one embodiment of the present invention provides a method for controlling a gain of a variable gain LNA. The method may comprise: utilizing a gate terminal of a first transistor to receive an input signal, wherein a first degeneration inductor is coupled to a source terminal of the first transistor, and the first transistor and the first degeneration inductor belong to a first branch of the variable gain LNA; utilizing a gate terminal of a second transistor to receive the input signal, wherein a second degeneration inductor is coupled to a source terminal of the second transistor, and the second transistor and the second degeneration inductor belong to a second branch of the variable gain LNA; and controlling whether to turn off the second branch, to determine a gain of the variable gain LNA.

The variable gain LNA and the method provided by the embodiments of the present invention not only slice the transistors, but also slice the degeneration inductors, which allows the input matching and the input linearity to be optimized over all gain gears. In addition, the embodiments of the present invention will not greatly increase additional costs. Thus, the present invention can solve the problem of the related art without introducing any side effect or in a way that is less likely to introduce side effects.

DETAILED DESCRIPTION

FIG.1is a diagram illustrating a variable gain low noise amplifier (LNA)10according to an embodiment of the present invention. As shown inFIG.1, the variable gain LNA10may comprise a first transistor such as a transistor Mon, a first degeneration inductor such as a degeneration inductor Ls,on, a second transistor such as a transistor Moff, and a second degeneration inductor such as a degeneration inductor Ls,off, where the degeneration inductor Ls,onis coupled to a source terminal of the transistor Mon, and the degeneration inductor Ls,offis coupled to a source terminal of the transistor Moff. In this embodiment, the variable gain LNA10may further comprise transistors Mc,onand Mc,offrespectively coupled to drain terminals of the transistors Monand Mofffor a purpose of cascade stages, but the present invention is not limited thereto.

In this embodiment, gate terminals of the transistors Monand Moffare configured to receive an input signal Vin. For example, the input signal Vin may be transmitted to the gate terminals of the transistors Monand Moffvia a resistor Rgand an inductor Lg. The variable gain LNA10may generate an output signal Vout on an output load Zoaccording to the input signal Vin, and more particularly, may amplify the input signal with a gain of the variable gain LNA10to generate the output signal Vout. As shown inFIG.1, the transistors Mc,onand Monand the degeneration inductor Ls,onbelong to a first branch110of the variable gain LNA10, and the transistors Mc,offand Moffand the degeneration inductor Ls,offbelong to a second branch120of the variable gain LNA10, where the gain of the variable gain LNA10is determined by controlling whether to turn off the second branch120. For example, the transistor Mc,onmay be configured to control whether to turn on or off the first branch110, and the transistor Mc,offmay be configured to control whether to turn on or off the second branch120. A gate terminal of the transistor Mc,onmay be fixed at a voltage level VH (e.g., a voltage level of a supply voltage VDD) to make the first branch110kept turned on, and a gate terminal of the transistor Mc,offmay be controlled to be either the voltage level VH or a voltage level VL (e.g., a voltage level of a ground voltage GND). When the gate terminal of the transistor Mc,offis set at the voltage level VH, the second branch120is turned on. When the gate terminal of the transistor Mc,offis set at the voltage level VL, the second branch120is turned off.

In this embodiment, the variable gain LNA10may further comprise a resistor Rs,offand a switch SWR, where the resistor Rs,offis coupled to the degeneration inductor Ls,off, and the switch SWRis coupled across the resistor Rs,off. As shown inFIG.1, the resistor Rs,offand the switch SWRbelong to the second branch120, where the switch SWRmay be controlled according to whether to turn off the second branch120. For example, the switch SWRmay be controlled by a control signal, wherein the control signal may indicate whether the second branch120is turned off or not. For example, when the second branch120is turned on (e.g., by setting the voltage level of the gate terminal of the transistor Mc,offto the voltage level VH), the control signal may be pulled to the voltage level VH which may represent a first logic value (e.g., a logic value “1”) to turn on the switch SWR, and the resistor Rs,offis therefore bypassed and does not take effect, making an effective source load of the transistor Moffcomprise the inductor Ls,offonly. When the second branch120is turned off (e.g., by setting the voltage level of the gate terminal of the transistor Mc,offto the voltage level VL), the control signal may be pulled to the voltage level VL which may represent a second logic value (e.g., a logic value “0”) to turn off the switch SWR, and the resistor Rs,offtherefore takes effect, making the effective source load of the transistor Moffcomprise a network of the inductor Ls,offand the resistor Rs,offconnected in series.

In general, the variable gain LNA10may comprise multiple branches, and any branch (e.g., each branch) of the multiple branches may comprise a cascode transistor (e.g., Mc,onand Mc,off), an input transistor (e.g., Monand Moff) and a source degeneration inductor (e.g Ls,off) as illustrated by one of the first branch110and the second branch120, and more particularly, each branch which is able to be selectively turned off may further comprise a resistor (e.g., Rs,off) and a switch (e.g., SWR) as illustrated by the second branch120. To better understand performance of the variable gain LNA10under different gain gears, assume that the first branch110represents an entirety of branches being turned on, and the second branch120represents an entirety of branches being turned off, where a percentage of turned-off branches among the multiple branches is α. A transconductance introduced by the transistor Moffis “α×gm”, a transconductance introduced by the transistor Monis “(1−a)×gm”, a gate-to-source capacitance introduced by transistor Moffis “α×Cgs”, a gate-to-source capacitance introduced by transistor Monis “(1−α)×Cgs”, the source degeneration inductor Ls,offis “Ls/α”, and the source degeneration inductor Ls,onis “Ls/(1−α)”, where “gm” represents an overall transconductance of the variable gain LNA10based on a high gain mode (e.g., under a condition where all branches are turned on), “Cgs” represents an overall gate-to-source capacitance of the variable gain LNA10based on the high gain mode (e.g., a total capacitance introduced by the transistors Monand Moffconnected in parallel), and “Ls” represents an overall degeneration inductance of the variable gain LNA10based on the high gain mode (e.g., a total inductance introduced by the degeneration inductors Ls,onand Ls,offconnected in parallel). Thus, a gain of the variable gain LNA10may be obtained as follows:

In the above expression, “w” represents a frequency parameter, and “j” represents a unit imaginary number. By making a resistance of the resistor Rs,offbe “(1/α)×(gm×Ls/Cgs)”, an input impedance Zinof the variable gain LNA10can be obtained as follows:

As shown above, the input impedance Zindoes not contain the parameter a, which means the input impedance Zincan be substantially unchanged over different gain gears. When an input linearity of the variable gain LNA10is limited by a maximum output voltage Vo,MAXof the output signal Vout, a maximum input voltage Vin,MAX,Vo-limitedwhich indicates the input linearity can be obtained as follows:

When the input linearity of the variable gain LNA10is limited by a maximum gate-to-source voltage Vgs,MAXof the transistor Mon, a maximum input voltage Vin,MAX,Vgs-limitedwhich indicates the input linearity can be obtained as follows:

Thus, an overall linearity of the variable gain LNA10may be represented by a minimum among the maximum input voltages Vin,MAX,Vo-limitedand Vin,MAX,Vgs-limited.

In view of above analysis, when parameters of components are designed for a purpose of optimizing performances (e.g., noise figure related performance, gain step stability, input matching, input linearity) of the variable gain LNA10operating in the high gain mode, input matching can be substantially kept at an optimized condition (e.g., having a S11 parameter equal or substantially equal to “−∞”) over all gain gears. For example, the input matching can be substantially kept at an optimized condition when the variable gain LNA10operates in a low gain mode (e.g., a condition of the second branch120being turned off). Accordingly, the maximum input voltages Vin,MAX,Vo-limitedcan be increased by 1 decibel (dB) in response to the gain of the variable gain LNA10being decreased by 1 dB, which substantially meets an ideal relationship between the maximum input voltages Vin,MAX,Vo-limitedand the gain of the variable gain LNA10.

It should be noted thatFIG.1takes two-branch architecture for illustrative purpose only, and is not meant to be a limitation of the present invention. Those skilled in this art should understand how to extend the concept illustrated by the embodiment ofFIG.1to an architecture having more branches, and related details are omitted here for brevity.

FIG.2is a diagram illustrating a variable gain LNA20according to an embodiment of the present invention, where the variable gain LNA20may be an example of the variable gain LNA10shown inFIG.1. As shown inFIG.2, the variable gain LNA20may comprise transistors Mc0, Mc1, Mc2, Mc3, M0, M1, M2and M3, resistors Rs1, Rs2and Rs3, switches SW1, SW2and SW3, and degeneration inductors L0, L1, L2and L3. For brevity, the resistor Rg, the inductor Lgand the output load Zoare not shown inFIG.2for brevity. In this embodiment, a branch comprising the transistors Mc0and M0, and the degeneration inductor L0may be an example of the first branch110shown inFIG.1. In addition, any (e.g., each) of a branch comprising the transistors Mc1and M1, the resistor Rs1, the switch SW1and the degeneration inductor L1, a branch comprising the transistors Mc2and M2, the resistor Rs2, the switch SW2and the degeneration inductor L2, and a branch comprising the transistors Mc3and M3, the resistor Rs3, the switch SW3and the degeneration inductor L3may be an example of the second branch120shown inFIG.1. More particularly, any of the switches SW1, SW2and SW3may be an example of the switch SWRshown inFIG.1, where the switches SW1, SW2and SW3are connected in parallel with the resistors Rs1, Rs2and Rs3, respectively, and gate terminals of the transistors Mc0, Mc1, Mc2and Mc3are controlled by control signals Vc0, Vc1, Vc2and Vc3, respectively. As shown inFIG.2, the switch SW1is coupled between a source terminal of the transistor M1and the degeneration inductor L1, where the switch SW1is controlled according to whether to turn off the branch comprising the transistor M1and the inductor L1(e.g., according to whether the control voltage Vc1is pulled down to the voltage level VL). The switch SW2is coupled between a source terminal of the transistor M2and the degeneration inductor L2, where the switch SW2is controlled according to whether to turn off the branch comprising the transistor M2and the inductor L2(e.g., according to whether the control voltage Vc2is pulled down to the voltage level VL). The switch SW3is coupled between a source terminal of the transistor M3and the degeneration inductor L3, where the switch SW3is controlled according to whether to turn off the branch comprising the transistor M3and the inductor L3(e.g., according to whether the control voltage Vc3is pulled down to the voltage level VL).

FIG.3is a diagram illustrating a variable gain LNA30according to an embodiment of the present invention, where the variable gain LNA30may be another example of the variable gain LNA10shown inFIG.1, and more particularly, may be an alternative design with respect to the variable gain LNA20shown inFIG.2. In the embodiment ofFIG.3, the switch SW1and the resistor Rs1are coupled between the degeneration inductor L1and a reference terminal such as an alternating current (AC) ground terminal, where the switch SW1is controlled according to whether to turn off the branch comprising the transistor M1and the inductor L1(e.g., according to whether the control voltage Vc1is pulled down to the voltage level VL). The switch SW2and the resistor Rs2are coupled between the degeneration inductor L2and the AC ground terminal, where the switch SW2is controlled according to whether to turn off the branch comprising the transistor M2and the inductor L2(e.g., according to whether the control voltage Vc2is pulled down to the voltage level VL). The switch SW3and the resistor Rs3are coupled between the degeneration inductor L3and the AC ground terminal, where the switch SW3is controlled according to whether to turn off the branch comprising the transistor M3and the inductor L3(e.g., according to whether the control voltage Vc3is pulled down to the voltage level VL).

FIG.4is a diagram illustrating a variable gain LNA40according to an embodiment of the present invention, where the variable gain LNA40may be another example of the variable gain LNA10shown inFIG.1, and more particularly, may be an alternative design with respect to the variable gain LNA20shown inFIG.2. In the embodiment ofFIG.3, the degeneration inductors L0and L1may be combined to be one degeneration inductor such as L0′, where the degeneration inductor L0′ may be an example of the degeneration inductor Ls,onshown inFIG.1, and the transistor M0may be an example of the transistor Monshown inFIG.1. In addition, the variable gain LNA40may comprise a third transistor such as the transistor M1, where a gate terminal of the transistor M1is configured to receive the input signal Vin, and the degeneration inductor L0′ is coupled to a source terminal of the transistor M1.

FIG.5is a diagram illustrating a variable gain LNA50according to an embodiment of the present invention, where the variable gain LNA50may be another example of the variable gain LNA10shown inFIG.1, and more particularly, may be an alternative design with respect to the variable gain LNA40shown inFIG.4. In the embodiment ofFIG.5, the switch SW2and the resistor Rs2are coupled between the degeneration inductor L2and the AC ground terminal, where the switch SW2is controlled according to whether to turn off the branch comprising the transistor M2and the inductor L2(e.g., according to whether the control voltage Vc2is pulled down to the voltage level VL). The switch SW3and the resistor Rs3are coupled between the degeneration inductor L3and the AC ground terminal, where the switch SW3is controlled according to whether to turn off the branch comprising the transistor M3and the inductor L3(e.g., according to whether the control voltage Vc3is pulled down to the voltage level VL).

FIG.6is a diagram illustrating a layout of degeneration inductors such as the degeneration inductors L0, L1, L2and L3mentioned in the previous embodiments according to an embodiment of the present invention. As shown inFIG.6, a region surrounded by the degeneration inductor L0, a region surrounded by the degeneration inductor L1, a region surrounded by the degeneration inductor L2and a region surrounded by the degeneration inductor L3are non-overlapping. In some embodiments, the degeneration inductors L0, L1, L2and L3may be implemented on the same metal layer. In some embodiments, the degeneration inductors L0, L1, L2and L3may be implemented on different metal layers. In this embodiment, any of the degeneration inductors L0, L1, L2and L3may be connected to at least one routing wire different from the metal layer thereof, but the present invention is not limited thereto.

FIG.7is a diagram illustrating a layout of degeneration inductors such as the degeneration inductors L0, L1, L2and L3mentioned in the previous embodiments according to another embodiment of the present invention. As shown inFIG.7, a region surrounded by the degeneration inductor L0, a region surrounded by the degeneration inductor L1, a region surrounded by the degeneration inductor L2and a region surrounded by the degeneration inductor L3overlaps one another. In practice, any two of the degeneration inductors L0, L1, L2and L3may have a mutual inductance among them, which needs to be considered during optimizing the matching condition mentioned above. In some embodiments, the degeneration inductors L0, L1, L2and L3may be implemented on the same metal layer. In some embodiments, the degeneration inductors L0, L1, L2and L3may be implemented on different metal layers. In this embodiment, any of the degeneration inductors L0, L1, L2and L3may be connected to at least one routing wire different from the metal layer thereof, but the present invention is not limited thereto.

FIG.8is a diagram illustrating a working flow of a method for controlling a gain of a variable gain LNA (e.g., the variable gain LNA10shown inFIG.1) according to an embodiment of the present invention. It should be noted that the working flow shown inFIG.8is for illustrative purposes only, and is not meant to be a limitation of the present invention. One or more steps may be added, deleted or modified in the working flow shown inFIG.8if a same result can be obtained. In addition, these steps do not have to be executed in the exact order shown inFIG.8.

In Step S810, the variable gain LNA may utilize a gate terminal of a first transistor (e.g., the transistor Mon) to receive an input signal, wherein a first degeneration inductor (e.g., the degeneration inductor Ls,on) is coupled to a source terminal of the first transistor, and the first transistor and the first degeneration inductor belong to a first branch of the variable gain LNA.

In Step S820, the variable gain LNA may utilize a gate terminal of a second transistor (e.g., the transistor Moff) to receive the input signal, wherein a second degeneration inductor (e.g., the degeneration inductor Ls,off) is coupled to a source terminal of the second transistor, and the second transistor and the second degeneration inductor belong to a second branch of the variable gain LNA.

In Step S830, the variable gain LNA may control whether to turn off the second branch, to determine the gain of the variable gain LNA. For example, the second branch may be turned on by controlling a voltage level of a gate terminal of a cascode transistor (e.g., the transistor Mc,off) belonging to the second branch to be the voltage level VH, and the second branch may be turned off by controlling the voltage level of the gate terminal of the cascode transistor belonging to the second branch to be the voltage level VL.

To summarize, the variable gain LNA and the method provided by the embodiments of the present invention not only slice the transistors, but also slice the degeneration inductors, which ensures that the input matching can be kept at the optimized condition, making the input linearity be optimized over all gain gears. In addition, the embodiments of the present invention will not greatly increase additional costs. Thus, the present invention can solve the problem of the related art without introducing any side effect or in a way that is less likely to introduce side effects.