DOHERTY AMPLIFIER

A Doherty amplifier includes a first amplifier that includes first output fingers and a first output electrode connected to the first output fingers, a second amplifier that includes second output fingers and a second output electrode connected to the second output fingers, a first bonding wire connected between a first region in the first output electrode and a second region in the second output electrode, a second bonding wire connected between a third region in the first output electrode and a fourth region in the second output electrode, and at least one of a first capacitor connected in series with the first bonding wire, and a second capacitor connected in parallel with the second bonding wire, wherein the first and the third regions are regions to which the first output fingers are connected, and the second and the fourth regions are regions to which second output fingers are connected.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority based on Japanese Patent Application No. 2021-102587, filed on Jun. 21, 2021, and the entire contents of the Japanese patent applications are incorporated herein by reference.

FIELD

The present disclosure relates to a Doherty amplifier.

BACKGROUND

There has been known a Doherty amplifier as an amplifier that amplifies high-frequency signals such as microwaves. In the Doherty amplifier, a main amplifier and a peak amplifier amplify input signals in parallel, and the amplified signals is synthesized by a synthesizer. In the synthesizer, a quarter wavelength line is provided between the main amplifier and a synthesis point. It is known to use an output capacitance and a bonding wire in the main amplifier instead of the quarter wavelength line (for example, Patent Document 1: U.S. Pat. No. 8,228,123).

SUMMARY

A Doherty amplifier according to the present disclosure includes: a first amplifier that includes a plurality of first output fingers and a first output electrode connected to the plurality of first output fingers, amplifies one of two signals into which an input signal is distributed, and outputs an amplified signal to the first output electrode; a second amplifier that includes a plurality of second output fingers and a second output electrode connected to the plurality of second output fingers, amplifies another one of the two signals, and outputs an amplified signal to the second output electrode; a first bonding wire connected between a first region in the first output electrode and a second region in the second output electrode; a second bonding wire connected between a third region in the first output electrode closer to the second output electrode than the first region and a fourth region in the second output electrode closer to the first output electrode than the second region; and at least one of a first capacitor connected in series with the first bonding wire between the first region and the second region, and a second capacitor connected in parallel with the second bonding wire between the third region and the fourth region; wherein the first region and the third region are regions to which the plurality of first output fingers are connected, the second region and the fourth region are regions to which the plurality of second output fingers are connected, and the first amplifier and the second amplifier are arranged in a direction intersecting extension directions of the first output fingers and the second output fingers, respectively.

DETAILED DESCRIPTION OF EMBODIMENTS

The synthesizer may be formed by connecting an output electrode of the main amplifier to an output electrode of the peak amplifier using the bonding wire. However, when the output electrodes of the main amplifier and peak amplifier are wide, a plurality of bonding wires are connected between the output electrodes. In this case, electrical lengths between the main amplifier and the synthesis point via the plurality of bonding wires may differ from each other. This may deviate from the conditions of the ideal synthesizer and degrade the characteristics.

It is an object of the present disclosure to provide a Doherty amplifier that can improve characteristics.

Description of Embodiments of the Present Disclosure

First, the contents of the embodiments of this disclosure are listed and explained.

(1) A Doherty amplifier according to the present disclosure includes: a first amplifier that includes a plurality of first output fingers and a first output electrode connected to the plurality of first output fingers, amplifies one of two signals into which an input signal is distributed, and outputs an amplified signal to the first output electrode; a second amplifier that includes a plurality of second output fingers and a second output electrode connected to the plurality of second output fingers, amplifies another one of the two signals, and outputs an amplified signal to the second output electrode; a first bonding wire connected between a first region in the first output electrode and a second region in the second output electrode; a second bonding wire connected between a third region in the first output electrode closer to the second output electrode than the first region and a fourth region in the second output electrode closer to the first output electrode than the second region; and at least one of a first capacitor connected in series with the first bonding wire between the first region and the second region, and a second capacitor connected in parallel with the second bonding wire between the third region and the fourth region; wherein the first region and the third region are regions to which the plurality of first output fingers are connected, the second region and the fourth region are regions to which the plurality of second output fingers are connected, and the first amplifier and the second amplifier are arranged in a direction intersecting extension directions of the first output fingers and the second output fingers, respectively. This makes it possible to improve the characteristics of the Doherty amplifier.

(2) The first output electrode may be separated between the first region and the third region, and the second output electrode may be separated between the second region and the fourth region.

(3) The first bonding wire may not intersect with the second bonding wire.

(4) The first region and the second region may be connected to each other without through the third region and the fourth region, and the third region and the fourth region may be connected to each other without through the first region and the second region.

(5) A signal output by the first amplifier and a signal output by the second amplifier may be synthesized in the second output electrode.

(6) The Doherty amplifier further may include a harmonic processing circuit that is connected to the second output electrode and processes a harmonic component of the signals amplified by the first amplifier and the second amplifier.

(7) A capacitor included in the Doherty amplifier may be the first capacitor.

(8) A capacitor included in the Doherty amplifier may be the second capacitor.

(9) Capacitors included in the Doherty amplifier may be the first capacitor and the second capacitor.

Details of Embodiments of the Present Disclosure

Specific examples of a Doherty amplifier in accordance with embodiments of the present disclosure are described below with reference to the drawings. The present disclosure is not limited to these examples, but is indicated by the claims, which are intended to include all modifications within the meaning and scope of the claims.

First Embodiment

FIG.1is a block diagram of a Doherty amplifier according to a first embodiment. As illustrated inFIG.1, in the Doherty amplifier, a main amplifier10and a peak amplifier11are connected in parallel between an input terminal Tin and an output terminal Tout. A high frequency signal is input to the input terminal Tin as an input signal. A distributor16distributes the input signal into two signals. One of the distributed signals is input to the main amplifier10. The main amplifier10(first amplifier) amplifies the input one of the distributed signals and outputs it to a synthesizer14. The other signal distributed by the distributor16is input to the peak amplifier11via a quarter wavelength line15. The synthesizer14synthesizes an output signal from the main amplifier10and an output signal from the peak amplifier11, and outputs a synthesized signal to the output terminal Tout.

The main amplifier10and the peak amplifier11include, for example, FETs (Field Effect Transistors)12and13, respectively. In the FETs12and13, a source S is grounded, a high frequency signal is input to a gate G, and a signal is output from a drain D. The FETs12and13are, for example, a GaN FET or an LDMOS (Laterally Diffused Metal Oxide Semiconductor). The main amplifier10and the peak amplifier11may be provided with multi-stage FETs12and13, respectively. The FETs12and13have drain source capacities Cds1and Cds2, respectively. The drain source capacitances Cds1and Cds2are internal capacitances of the FETs12and13, but are described by using dotted lines inFIG.1. The synthesizer14includes a drain source capacitance Cds1of the main amplifier10, an inductor L0, and a synthesis point N1. The drain source capacitance Cds1and the inductor L0function as an impedance inverter at a center frequency in a band of the Doherty amplifier and are used instead of the quarter wavelength line. At the synthesis point N1, the signal amplified by the main amplifier10and the signal amplified by the peak amplifier11are synthesized.

The main amplifier10operates in class AB or class B, and the peak amplifier11operates in class C. Thereby, when an input power is small, the main amplifier10mainly amplifies the input signal. When the input power becomes large, the main amplifier10and the peak amplifier11amplify the input signal. Matching circuits may be connected between the distributor16and the main amplifier10, between the distributor16and the peak amplifier11, and between the synthesizer14and the output terminal Tout. When the peak amplifier11operates in a state where the input power of the high frequency signal input to the input terminal Tin is large, the main amplifier10and the peak amplifier11are set to operate optimally at a saturation power (for example, the efficiency is maximized). When the peak amplifier11does not operate in a state where the input power is small, the main amplifier10is set to operate optimally (for example, efficiency is maximized) at the saturation power.

FIG.2is a circuit diagram of the Doherty amplifier according to the first embodiment. As illustrated inFIG.2, in the FET12, a plurality of FETs12ato12dare connected in parallel, and in the FET13, a plurality of FETs13ato13dare connected in parallel. The FETs12and13are multi-finger FETs, and the FETs12ato12dand the FETs13ato13dare schematically representations of multi-finger FETs. The FETs12ato12dand the FETs13ato13dhave drain source capacities Cds1ato Cds1dand Cds2ato Cds2d, respectively.

An inductor L1and a capacitor C1(first capacitor) are connected in series between the drains of the FETs12aand12band the drains of the FETs13cand13d. An inductor L2and a capacitor C2(second capacitor) are connected in parallel between the drains of the FETs12cand12dand the drains of the FETs13aand13b. The drain source capacitances Cds1aand Cds1bof the FETs12aand12b, the inductor L1and the capacitor C1form a synthesizer14a. The drain source capacitances Cds1cand Cds1dof the FETs12cand12d, the inductor L2and the capacitor C2form a synthesizer14b.

FIG.3is a plan view of the Doherty amplifier according to the first embodiment. As illustrated inFIG.3, the FETs12and13are provided on a semiconductor chip40and are arranged in a Y direction. The FET12is a multi-finger FET having a plurality of source fingers23, a plurality of gate fingers24, and a plurality of drain fingers25. The source fingers23, the gate fingers24and the drain fingers25extend in an X direction. The plurality of drain fingers25are connected to a drain electrode20. The plurality of gate fingers24are connected to a gate electrode22. The source fingers23are connected to a ground on a lower surface of the semiconductor chip40by via holes. The FET13includes a plurality of source fingers33, a plurality of gate fingers34, a plurality of drain fingers35, a drain electrode30, and a gate electrode32. The configurations of the source fingers33, the gate fingers34, the drain fingers35, the drain electrode30, and the gate electrode32in the FET13are the same as those in the FET12, and the description thereof will be omitted. Since the source fingers23and33, the gate fingers24and34, and the drain fingers25and35are arranged in the Y direction, the drain electrodes20and30and the gate electrodes22and32are widened in the Y direction.

In the drain electrode20of the FET12, a region far from the drain electrode30of the FET13is a first region20a, and a region close to the drain electrode30is a third region20b. In the drain electrode30of the FET13, a region far from the drain electrode20of the FET12is a second region30a, and a region close to the drain electrode20is a fourth region30b.

A pad26connected to the region20ais provided on a +X side of the region20a. A pad36connected to the region30ais provided on the +X side of the region30a. A pad38is provided in a +Y side of the pad36. The capacitor C1is connected between the pads36and38. The pads26and38are connected by bonding wires41. Regions where the bonding wires41bond to the pads26and38are regions20cand30c, respectively. The regions20aand30aare connected to each other via the pad26, the bonding wires41, the pad38, the capacitor C1and the pad36. Distances D4(electrical length) between the region20cand the plurality of drain fingers25connected to the region20aare substantially the same as each other. Distances D5between the region30cand the plurality of drain fingers35connected to the region30aare substantially the same as each other.

The regions20band30bare connected by bonding wires42. Regions where the bonding wires42bond to the drain electrodes20and30are regions20dand30d, respectively. The capacitor C2is connected in parallel with the bonding wires42between the regions20dand30d. Distances D3between the region20dand the plurality of drain fingers25connected to the region20bare substantially the same as each other. Another distances D3between the region30dand the plurality of drain fingers35connected to the region30bare substantially the same as each other.

Each of the capacitors C1and C2is a MIM (Metal Insulator Metal) capacitor having an upper electrode44, a lower electrode46, and a dielectric film45. The drain electrode30is connected to a matching circuit18via bonding wires43. A region where the bonding wires43bond to the drain electrode30is a region30e. The matching circuit18is connected to the output terminal Tout. The drain electrodes20,30, the gate electrodes22,32, the pads26,36and38, the upper electrode44, and the lower electrode46are metal layers such as a gold layer. Bonding wires are connected between the distributor16and the gate electrode22and between the quarter wavelength line15and the gate electrode32, but the illustration of the bonding wires is omitted.

FIG.4is a cross-sectional view of the capacitor in the first embodiment. As illustrated inFIG.4, the drain electrode20and the pad38(and the drain electrode30) are provided on the semiconductor chip40. The drain electrode20is connected to the upper electrode44, and the pad38(and the drain electrode30) is connected to the lower electrode46. In the capacitor C1(and C2), the dielectric film45is provided between the upper electrode44and the lower electrode46. The dielectric film45is an inorganic dielectric film such as a silicon nitride film or a silicon oxide film. An insulating film45ais provided so as to cover the upper electrode44. Both ends of the bonding wire41(and42) are bonded to the regions20c(and20d) and the regions30c(and30d). The drain electrode20may be connected to the lower electrode46and the pad38(and the drain electrode30) may be connected to the upper electrode44.

First Comparative Example

FIG.5is a plan view of a Doherty amplifier in a first comparative example. As illustrated inFIG.5, in the first comparative example, the capacitors C1and C2are not provided. The regions20cand30cto which the bonding wires41are bonded are between the regions20aand20band between the regions30aand30b, respectively. The bonding wires42are not provided. Other configurations are the same as those in the first embodiment.

In the first comparative example, the phases of the signals are almost the same at points where the plurality of drain fingers25(and35) are connected to the drain electrodes20(and30). The distance D1between the regions20c(and30c) and the drain fingers25(and35) far from the regions20c(and30c) is longer than the distance D2between the regions20c(and30c) and the drain fingers25(and35) close to the regions20c(and30c). Thereby, the phases of the signals output from the drain fingers25(and35) to be synthesized in the regions20c(and30c) are different from each other. Therefore, the loss increases.

Second Comparative Example

FIG.6is a plan view of a Doherty amplifier in a second comparative example. As illustrated inFIG.6, the bonding wires41and42are provided. The regions20cand30cto which the bonding wires41are bonded are provided in the regions20aand30b, respectively. The regions20dand30dto which the bonding wires42are bonded are provided in the regions20band30b, respectively. A reason why the bonding wires41connect the regions20cand30cand the bonding wires42connect the regions20dand30dis to make the lengths of the bonding wires41and42the same and make the respective inductances the same, which prevents the phases of the signals flowing through the bonding wires41and42from deviating from each other. Other configurations are the same as those in the first comparative example.

In the second comparative example, the regions20cand20d(or30aand30b) are provided near the centers of the regions20aand20b(or30cand30d). Therefore, the distances D3between the drain finger25(or35) and the regions20cand20d(or30cand30d) are almost the same as each other. Therefore, the phases of the signals output from the drain fingers25(or35) to be synthesized in the regions20cand20d(or30cand30d) are almost the same as each other. Thereby, the loss can be suppressed. Although the example in which the regions20aand20b(or30aand30b) are provided for two drain fingers25(or35) is described, the regions20aand20b(or30aand30b) may be provided for three drain fingers25(or35). Even in that case, the phases of the signals synthesized in the regions20cand20d(or30cand30d) can be aligned in the second comparative example, as compared with the first comparative example. However, in the second comparative example, in order to align the lengths of the bonding wires41and42to be the same, the bonding wires41and42are connected so as to intersect each other. However, due to the proximity effect, the resistance values of the bonding wires41and42increase, and the Q values of the bonding wires41and42(that is, the inductors L1and L2) decrease.

Third Comparative Example

FIG.7is a circuit diagram of a Doherty amplifier in a third comparative example.FIG.8is a plan view of the Doherty amplifier in the third comparative example. As illustrated inFIGS.7and8, in the third comparative example, the regions20cand30cto which the bonding wires41are bonded are provided in the regions20aand30a, respectively. The regions20dand30dto which the bonding wires42are bonded are provided in the regions20band30b, respectively. The bonding wires41and42correspond to the inductors L1and L2, respectively. Other configurations are the same as those in the second comparative example.

The distances D3between the drain finger25and the regions20cand20dare almost the same as each other. Thereby, the phases of the signals in the regions20cand20dare almost aligned. Similarly, the distances D3between the drain finger35and the regions30cand30dare almost the same each other, and the phases of the signals in regions30cand30dare almost aligned. However, the lengths of the bonding wires41and42are different from each other, and the inductances of inductors L1and L2are different from each other. Further, the electric length from the region20ato the region30evia the bonding wires41and the region30aare different from the electric length from the region20bto the region30evia the bonding wires42and the region30b. This makes it difficult to set both of the synthesizers14aand14bto have an electrical length of the quarter wavelength at the center frequency of the band. Even if the lengths of the bonding wires41and42are about the same as each other, the electrical length between the region20aand the synthesis point N1and the electrical length between the region20band the synthesis point N1are different from each other.

According to the first embodiment, as illustrated inFIG.3, the bonding wires41(first bonding wire) are connected between the region20a(first region) in the drain electrode20(first output electrode) and the region30a(second region) in the drain electrode30(second output electrode). The bonding wires42(second bonding wire) are connected between the region20b(third region) different from the region20ain the drain electrode20and the region30b(fourth region) different from the region30ain the drain electrode30. In this way, when the different regions20aand20bin the drain electrode20are connected to the different regions30aand30bin the drain electrode30, respectively, the electrical lengths of the synthesizers14aand14bare different from each other, and the characteristics of the Dougherty amplifier are deteriorated. Therefore, the capacitor C1(first capacitor) connected in series or in parallel with the bonding wires41is provided between the regions20aand30a. The capacitor C2(second capacitor) connected in series or in parallel with the bonding wires42is provided between the regions20band30b. Thereby, the electric lengths of the synthesizers14aand14bcan be made substantially the same. Therefore, the deterioration of the characteristics of the Doherty amplifier can be suppressed.

The region20bis closer to the drain electrode30than the region20a, and the region30bis closer to the drain electrode20than the region30a. At this time, the distance between the region20aand the synthesis point N1is longer than the distance between the region20band the synthesis point N1. For this reason, the capacitor C1is connected in series with the bonding wires41between the regions20aand the regions30a. The capacitor C2is connected in parallel with the bonding wires42between the regions20band the regions30b. Thereby, a total electrical length of the connection between the region20aand the synthesis point N1via the series connection of the bonding wires41and the capacitor C1can be substantially shorter than the total electrical length in the case where the capacitor C1is not included between the region20aand the synthesis point N1. The total electrical length of the connection between the region20band the synthesis point N1via the parallel connection of the bonding wires42and capacitor C2can be substantially longer than the total electrical length in the case where the capacitor C2is not included. Therefore, the electrical length between the region20aand the synthesis point N1and the electrical length between the region20band the synthesis point N1can be almost the same as each other.

The main amplifier10includes the plurality of drain fingers25(first output fingers), and the regions20aand20bare regions to which the plurality of drain fingers25are connected. Further, the peak amplifier11includes the plurality of drain fingers35(second output fingers), and the regions30aand30bare regions to which the plurality of drain fingers35are connected. In such multi-finger FETs, the phases are substantially the same as each other in the regions20aand20bto which the drain fingers25are connected. Therefore, when the electrical length between the region20aand the synthesis point N1is different from the electrical length between the region20band the synthesis point N1, the characteristics of the Doherty amplifier deteriorate. Therefore, it is preferable to provide capacitors C1and C2.

In the multi-finger FET, the widths of the drain electrodes20and30in a direction intersecting the extension direction (X direction) of the drain fingers25and35are widened. Therefore, when the main amplifier10and the peak amplifier11are arranged in the direction intersecting the extension direction of the drain fingers25and the drain fingers35, respectively, the electrical length between the region20aand the synthesis point N1and the electrical length between the region20band the synthesis point N1easily differ from each other. Therefore, it is preferable to provide capacitors C1and C2.

The regions20dand30dto which the bonding wires42are bonded are provided in the regions20band30b, respectively. On the other hand, the pads26and36for pulling out the regions20aand30ain the +X direction are provided, respectively, and the bonding wires41are bonded in the regions20cand30cwhich are arranged in the +X direction from the regions20aand30a. Thereby, it is possible to prevent the bonding wires41and42from intersecting with each other. Therefore, it is possible to suppress a decrease in the Q value as illustrated in the second comparative example.

Further, the signal output by the main amplifier10and the signal output by the peak amplifier11are synthesized in the drain electrode30. Thereby, a difference easily occurs between the electric length between the region20aand the synthesis point N1and the electric length between the region20band the synthesis point N1. Therefore, it is preferable to provide the capacitors C1and C2.

When the regions20aand30aare connected to each other via the region20b, the signal from the drain finger25connected to the region20aand the signal from the drain finger25connected to the region20bare synthesized in the region20b. Thereby, the signals having different phases are synthesized and the loss occurs. Similarly, when the regions20aand30aare connected to each other via the region30b, the signals having different phases are synthesized in the region30band the loss occurs. According to the first embodiment, the regions20aand30aare connected to each other without through the regions20band30b, and the regions20band30bare connected to each other without through the regions20aand30a. Thereby, the loss can be suppressed.

First Variation of First Embodiment

FIG.9is a plan view of a Doherty amplifier in a first variation of the first embodiment. As illustrated inFIG.9, the pad36is pulled out from the region30ain the +X direction and further bent in the +Y direction. The region30cto which the bonding wire41is bonded is provided on the pad36. The capacitor C1is not connected in series or in parallel with the bonding wire41between the regions20aand30a. The capacitor C2is connected in parallel with the bonding wires42between the regions20band30b. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted. Only the capacitor C2among the capacitors C1and C2may be provided as in the first variation of the first embodiment.

Second Variation of First Embodiment

FIG.10is a plan view of a Doherty amplifier in a second variation of the first embodiment. As illustrated inFIG.10, the capacitor C1is connected in series with the bonding wires41between the regions20aand30a. The capacitor C2is not connected in series or in parallel with the bonding wires42between the regions20band30b. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted. Only the capacitor C1among the capacitors C1and C2may be provided as in the second variation of the first embodiment.

At least one of the capacitors C1and C2may be provided as in the first embodiment and the first and second variations thereof. Whether both of the capacitors C1and C2are provided or any one of the capacitors C1and C2are provided can be appropriately designed so that the electrical length between the region20aand the synthesis point N1is almost the same as the electrical length between the region20band the synthesis point N1.

Although the example in which the FETs12and13are provided on the same semiconductor chip40is described, the FETs12and13may be provided on different semiconductor chips. Although the example in which the main amplifier10and the peak amplifier11include the FETs12and13, respectively, is described, the main amplifier10and the peak amplifier11may include transistors other than the FETs. Although the example of using the MIM capacitors as the capacitors C1and C2is described, capacitors other than the MIM capacitors may be used.

An example in which the drain electrode20is set to the two regions20aand20band the drain electrode30is set to the two regions30aand30bis described. However, the drain electrode20may be set to three or more regions and the drain electrode30may be set to three or more regions. For example, the region between the regions20aand20bin the drain electrode20and the region between the regions30aand30bin the drain electrode30may be connected by bonding wires other than the bonding wires41and42.

Although the examples of the main amplifier10and the peak amplifier11are described as the first amplifier and the second amplifier, respectively, the first amplifier and the second amplifier may be the peak amplifier11and the main amplifier10, respectively.

Second Embodiment

FIG.11is a plan view of a Doherty amplifier in a second embodiment.

As illustrated inFIG.11, the regions20aand20bin the drain electrode20are divided by a division region29. The regions30aand30bin the drain electrode30are divided by a division region39. The region30band the pad36are electrically connected to each other via the lower electrode46of the capacitor C1and without via the region30a. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.

First Variation of Second Embodiment

FIG.12is a plan view of a Doherty amplifier in a first variation of the second embodiment. As illustrated inFIG.12, the capacitor C1is not connected in series or in parallel with the bonding wires41between the regions20aand30a. The division regions29and39in the drain electrodes20and30are provided. The regions30aand30bare not directly connected to each other, but are connected to each other via the pad36. The capacitor C2is connected in parallel with the bonding wires42between the regions20band30b. Other configurations are the same as those in the second embodiment, and the description thereof will be omitted. Only the capacitor C2among the capacitors C1and C2may be provided as in the first variation of the second embodiment.

Second Variation of Second Embodiment

FIG.13is a plan view of a Doherty amplifier in a second variation of the second embodiment. As illustrated inFIG.13, the capacitor C1is connected in series with the bonding wires41between the regions20aand30a. The capacitor C2is not connected in series or in parallel with the bonding wires42between the regions20band30b. Other configurations are the same as those in the second embodiment, and the description thereof will be omitted. Only the capacitor C1among the capacitors C1and C2may be provided as in the second variation of the second embodiment.

When the regions20aand20bare connected and the regions30aand30bare connected as in the first embodiment and the variations thereof, the characteristics are improved, but oscillation is likely to occur. Therefore, the regions20aand20bare separated and the regions30aand30bare separated as in the second embodiment and the variations thereof. Thereby, the oscillation can be suppressed.

Third Embodiment

FIG.14is a circuit diagram of a Doherty amplifier in a third embodiment. As illustrated inFIG.14, a harmonic processing circuit48is connected between the synthesis point N1and the ground. The harmonic processing circuit48includes an inductor L3and a capacitor C3that are connected in series between the synthesis point N1and the ground. The inductor L3and the capacitor C3form a series resonant circuit and have a resonant frequency in a harmonic frequency band in a band of the Doherty amplifier. Other circuit configurations are the same as those inFIG.2of the second embodiment, and the description thereof will be omitted.

FIG.15is a plan view of the Doherty amplifier in the third embodiment. As illustrated inFIG.15, the capacitor C3includes a dielectric film49, an upper electrode51, and a lower electrode (not illustrated). A bonding wire47corresponds to the inductor L3and connects the drain electrode30and the upper electrode51. The lower electrode is connected to the ground. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.

According to the third embodiment, the harmonic processing circuit48is connected to the drain electrode30and processes the harmonic components of the signals amplified by the main amplifier10and the peak amplifier11. By providing the harmonic processing circuit48in the drain electrode30corresponding to the synthesis point N1, the single harmonic processing circuit48can be used to process the harmonics of both the main amplifier10and the peak amplifier11. Therefore, the Doherty amplifier can be reduced in size. The harmonic processing circuit48may be provided in the variations of the first embodiment, the second embodiment and the variations of the second embodiment.

The embodiments disclosed here should be considered illustrative in all respects and not restrictive. The present disclosure is not limited to the specific embodiments described above, but various variations and changes are possible within the scope of the gist of the present disclosure as described in the claims.