SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Provided is a semiconductor device including: a drift region of a first conductivity type provided in a semiconductor substrate; a collector region of a second conductivity type provided on a back surface of the semiconductor substrate; a cathode region of the first conductivity type provided on the back surface of the semiconductor substrate and having a higher doping concentration than the drift region; a plurality of trench portions provided on a front surface of the semiconductor substrate; and a lifetime control portion provided in the semiconductor substrate and containing a lifetime killer, in which the lifetime control portion includes: a main region provided in a diode portion; and a decay region provided to extend from the main region in a direction parallel to the front surface of the semiconductor substrate and having a lifetime killer concentration that has decayed more than a lifetime killer concentration of the main region.

The contents of the following patent application(s) are incorporated herein by reference:NO. 2022-165979 filed in JP on Oct. 17, 2022

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device and a manufacturing method of a semiconductor device.

2. Related Art

Conventionally. there is known a semiconductor device including a transistor portion and a diode portion (see, for example, Patent Documents 1 to 3).Patent Document 1: Japanese Patent Application Publication No. 2013-149909Patent Document 2: WO 2012/169053Patent Document 3: Japanese Patent Application Publication No. 2021-190496

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, embodiments of the present invention will be described. However, the following embodiments are not for limiting the invention according to the claims. In addition, not all of the combinations of features described in the embodiments are essential to the solving means of the invention.

As used herein, one side in a direction parallel to a depth direction of a semiconductor substrate is referred to as “upper” and the other side is referred to as “lower”. One surface of two principal surfaces of a substrate, a layer, or other member is referred to as an upper surface, and the other surface is referred to as a lower surface. “Upper” and “lower” directions are not limited to a direction of gravity, or a direction in which a semiconductor device is mounted.

In the present specification, technical matters may be described using orthogonal coordinate axes of an X axis, a Y axis, and a Z axis. The orthogonal coordinate axes specify relative positions of components, and do not limit a specific direction. For example, the Z axis is not limited to indicate the height direction with respect to the ground. Note that a +Z axis direction and a −Z axis direction are directions opposite to each other. When the Z axis direction is described without the signs, it means that the direction is parallel to the +Z axis and the −Z axis.

In the present specification, orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are referred to as the X axis and the Y axis. Further, an axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is referred to as the Z axis. In the present specification, the direction of the Z axis may be referred to as the depth direction. Further, in the present specification, a direction parallel to the upper surface and the lower surface of the semiconductor substrate may be referred to as a horizontal direction, including an X axis direction and a Y axis direction.

In the present specification, a case where a term such as “same” or “equal” is mentioned may include a case where an error due to a variation in manufacturing or the like is included. This error is, for example, within 10%.

In the present specification, a conductivity type of a doping region where doping has been carried out with an impurity is described as a P type or an N type. In the present specification, the impurity may particularly mean either a donor of the N type or an acceptor of the P type, and may be described as a dopant. In the present specification, doping means introducing the donor or the acceptor into the semiconductor substrate and turning it into a semiconductor showing a conductivity type of the N type, or a semiconductor showing a conductivity type of the P type.

In the present specification, a doping concentration means a concentration of the donor or a concentration of the acceptor in a thermal equilibrium state. In the present specification, a net doping concentration means a net concentration obtained by adding the donor concentration set as a positive ion concentration to the acceptor concentration set as a negative ion concentration, taking polarities of charges into account. As an example, when the donor concentration is referred to as NDand the acceptor concentration is referred to as NA, the net doping concentration at any position is given as ND−NA. In the present specification, the net doping concentration may simply be referred to as the doping concentration.

The donor has a function of supplying electrons to a semiconductor. The acceptor has a function of receiving electrons from the semiconductor. The donor and acceptor are not limited to the impurities themselves. For example, a VOH defect which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) existing in the semiconductor, an Si-i-H defect which is a combination of interstitial silicon (Si-i) and hydrogen, or a CiOi-H defect which is a combination of interstitial carbon (Ci), interstitial oxygen (Oi), and hydrogen functions as the donor that supplies electrons. In the present specification, these defects may be referred to as the hydrogen donor.

A P+ type or an N+ type described in the present specification means a doping concentration higher than that of the P type or the N type, and a P− type or an N− type described herein means a doping concentration lower than that of the P type or the N type. Furthermore, a P++ type or an N++ type described in the present specification means a higher doping concentration than that of the P+ type or the N+ type.

A chemical concentration in the present specification indicates an atomic density of an impurity measured regardless of an electrical activation state. The chemical concentration can be measured by, for example, secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by capacitance-voltage profiling method (CV method). Furthermore, a carrier concentration measured by a spreading resistance profiling method (SRP method) may be set as the net doping concentration. A carrier means an electron charge carrier or a hole charge carrier. The carrier concentration measured by the CV method or the SRP method may be set as a value in a thermal equilibrium state. Furthermore, in a region of an N type, the donor concentration is sufficiently higher than the acceptor concentration, and therefore, the carrier concentration in the region may be set as the donor concentration. Similarly, in a region of a P type, the carrier concentration in the region may be set as the acceptor concentration. In the present specification, the doping concentration of the N type region may be referred to as the donor concentration, and the doping concentration of the P type region may be referred to as the acceptor concentration.

Furthermore, when a concentration distribution of the donor, acceptor, or net doping has a peak, a value of the peak may be set as the concentration of the donor, acceptor, or net doping in the region. When the concentration of the donor, acceptor, or net doping is approximately uniform in a region, or the like, an average value of the concentration of the donor, acceptor, or net doping in the region may be set as the concentration of the donor, acceptor, or net doping.

The carrier concentration measured by the SRP method may be lower than the concentration of the donor or the acceptor. In a range where a current flows when a spreading resistance is measured, the carrier mobility of the semiconductor substrate may be lower than a value of that in a crystalline state. The fall in carrier mobility occurs when carriers are scattered due to disorder (disorder) of a crystal structure due to a lattice defect or the like. The carrier concentration becomes lower for the following reason. In the SRP method, a spreading resistance is measured, and a carrier concentration is converted from a measurement value of the spreading resistance. At this time, mobility of the crystalline state is used as the carrier mobility. Meanwhile, despite the fact that carrier mobility is reduced at a position where the lattice defect is introduced, the carrier concentration is calculated by using the carrier mobility of the crystalline state. Therefore, a value smaller than the actual carrier concentration, that is, the donor or acceptor concentration is obtained.

The concentration of the donor or the acceptor calculated from the carrier concentration measured by the CV method or the SRP method may be lower than a chemical concentration of an element representing the donor or the acceptor. As an example, in a silicon semiconductor, a donor concentration of phosphorus or arsenic serving as a donor or an acceptor concentration of boron (boron) serving as an acceptor is approximately 99% of chemical concentrations of these. On the other hand, in the silicon semiconductor, a donor concentration of hydrogen serving as a donor is approximately 0.1% to 10% of a chemical concentration of hydrogen. In the present specification, an SI unit system is adopted. In the present specification, a unit of a distance or length may be represented by cm (centimeter). In this case, various calculations may be converted into m (meter) to be calculated. Regarding indication of numerical values meaning a power of 10, for example, indication of 1E+16 means 1×1016, and indication of 1E-16 means 1×10−16.

FIG.1Ashows an example of a top view of a semiconductor device100.FIG.1Ashows a position at which each member is projected on an upper surface of a semiconductor substrate10.FIG.1Ashows merely some members of the semiconductor device100, and omits some members. The semiconductor device100is a semiconductor chip including a transistor portion70and a diode portion80.

The transistor portion70includes a transistor such as an IGBT (Insulated Gate Bipolar Transistor). The diode portion80includes a diode such as a free wheel diode (FWD). The semiconductor device100of the present example is a reverse conducting IGBT (RC-IGBT) having a transistor portion70and a diode portion80on the same chip.

The semiconductor substrate10is a substrate that is formed of a semiconductor material. The semiconductor substrate10may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate or the like such as a gallium nitride semiconductor substrate. The semiconductor substrate10in the present example is a silicon substrate. The semiconductor substrate10may be a wafer cut out from a semiconductor ingot, or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by any of a Chokralsky method (CZ method), a magnetic field applied Chokralsky method (MCZ method), or a float zone method (FZ method).

The semiconductor substrate10has end sides102in a top view. When merely referred to as the top view in the present specification, it means that the semiconductor substrate10is viewed from an upper surface side. The semiconductor substrate10of the present example includes two sets of end sides102facing each other in the top view. InFIG.1A, the X axis and the Y axis are parallel to any of the end sides102. In addition, the Z axis is perpendicular to the upper surface of the semiconductor substrate10. The semiconductor substrate10includes an active portion160and an edge termination structure portion170.

The active portion160is a region where a main current flows in the depth direction between the upper surface and a lower surface of the semiconductor substrate10when the semiconductor device100operates. An emitter electrode is provided above the active portion160, but is omitted inFIG.1A.

The active portion160is provided with at least one of the transistor portion70including a transistor element such as an IGBT, or the diode portion80including a diode element such as a free wheel diode (FWD). In the example ofFIG.1A, the transistor portion70and the diode portion80are alternately arranged along a predetermined array direction (the X axis direction in the present example) on the upper surface of the semiconductor substrate10. The active portion160in another example may be provided with only one of the transistor portion70or the diode portion80.

InFIG.1A, a region where the transistor portion70is arranged is denoted by a symbol “I”, and a region where the diode portion80is arranged is denoted by a symbol F. In the present specification, a direction perpendicular to the array direction in the top view may be referred to as an extending direction (the Y axis direction inFIG.1A). Each of the transistor portions70and the diode portions80may have a longitudinal length in the extending direction. In other words, the length of each of the transistor portions70in the Y axis direction is larger than the width in the X axis direction. Similarly, the length of each of the diode portions80in the Y axis direction is larger than the width in the X axis direction. The extending direction of the transistor portion70and the diode portion80, and the longitudinal direction of each trench portion described below may be the same.

Each of the diode portions80includes a cathode region of an N+ type in a region in contact with the lower surface of the semiconductor substrate10. In the present specification, a region where the cathode region is provided is referred to as the diode portion80. In other words, the diode portion80is a region that overlaps with the cathode region in the top view. On the lower surface of the semiconductor substrate10, a collector region of a P+ type may be provided in a region other than the cathode region.

The transistor portion70includes the collector region of the P+ type in a region in contact with the lower surface of the semiconductor substrate10. In addition, in the transistor portion70, there is periodically arranged a gate structure which includes an N type emitter region, a P type base region, a gate conductive portion, and a gate dielectric film, on the upper surface side of the semiconductor substrate10.

The semiconductor device100may have one or more pads above the semiconductor substrate10. The semiconductor device100of the present example has a gate pad112. The semiconductor device100may have a pad such as an anode pad, a cathode pad, and a current detection pad. Each pad is arranged in the vicinity of the end side102. The vicinity of the end side102refers to a region between the end side102and the emitter electrode in the top view. When the semiconductor device100is mounted, each pad may be connected to an external circuit via a wiring such as a wire.

A gate potential is applied to the gate pad112. The gate pad112is electrically connected to the conductive portion of the gate trench portion of the active portion160. The semiconductor device100includes a gate runner130that connects the gate pad112and the gate trench portion.

The gate runner130is electrically connected to the gate conductive portion of the transistor portion70and applies a gate voltage to the transistor portion70. The gate runner130is provided so as to enclose an outer circumference of the active portion160in the top view. The gate runner130is electrically connected to the gate pad112provided in the edge termination structure portion170. The gate runner130may be provided between the transistor portion70and the diode portion80in the top view.

Further, the semiconductor device100may include a temperature sensing portion (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detection portion (not shown) that simulates an operation of the transistor portion provided in the active portion160.

The semiconductor device100of the present example includes the edge termination structure portion170between the active portion160and the end side102in the top view. The edge termination structure portion170of the present example is arranged between the gate runner130and the end side102. The edge termination structure portion170reduces an electric field strength on the upper surface side of the semiconductor substrate10. The edge termination structure portion170may include at least one of a guard ring, a field plate, or a RESURF which is annularly provided to enclose the active portion160.

FIG.1Bis an enlarged view of a region A inFIG.1A. The region A is a region including the transistor portion70, the diode portion80, and the gate runner130. The gate runner130of the present example includes a gate metal layer50and a gate runner portion51.

A boundary region90is provided between the transistor portion70and the diode portion80on the front surface of the semiconductor substrate10. The front surface21of the semiconductor substrate10refers to one of the two principal surfaces opposite to each other in the semiconductor substrate10. The front surface21will be described below.

The semiconductor device100of the present example includes a gate trench portion40, a dummy trench portion30, a well region17, an emitter region12, a base region14, and a contact region15that are formed inside the front surface21side of the semiconductor substrate10. In addition, the semiconductor device100of the present example includes an emitter electrode52and a gate metal layer50provided above the front surface21of the semiconductor substrate10. The emitter electrode52and the gate metal layer50are provided separate from each other.

An interlayer dielectric film is formed between the emitter electrode52and the gate metal layer50, and the front surface21of the semiconductor substrate10, but the interlayer dielectric film is omitted inFIG.18. In the interlayer dielectric film of the present example, a contact hole54, a contact hole55, and a contact hole56are formed to penetrate through the interlayer dielectric film.

The emitter electrode52is electrically connected to the emitter region12, the contact region15, and the base region14on the front surface21of the semiconductor substrate10via the contact hole54formed in the interlayer dielectric film. Also, the emitter electrode52is connected to the dummy conductive portion of the dummy trench portion30via the contact hole56. Between the emitter electrode52and the dummy conductive portion, a connection portion25formed of a conductive material such as polysilicon doped with impurities may be provided.

The gate metal layer50is in contact with the gate runner portion51via the contact hole55. The gate runner portion51is formed of a semiconductor such as polysilicon doped with impurities. The gate runner portion51is connected to a gate conductive portion in the gate trench portion40on the front surface of the semiconductor substrate10.

The emitter electrode52and the gate metal layer50are formed of a material including metal. For example, at least a partial region of each electrode may be formed of metal such as aluminum (Al) or a metal alloy such as an aluminum-silicon alloy (AlSi) and an aluminum-silicon-copper alloy (AlSiCu). Each electrode may have, in an under layer of the region formed of aluminum or the like, barrier metal which is formed of titanium, titanium compounds, or the like. Further, each electrode may include a plug, which is formed by embedding tungsten or the like so as to be in contact with the barrier metal and aluminum or the like, in the contact hole.

The well region17is provided so as to overlap with the gate metal layer50and the gate runner portion51. The well region17is provided to extend at a predetermined width also in a range not overlapping with the gate metal layer50and the gate runner portion51. The well region17of the present example is provided apart from an end of the contact hole54in the Y axis direction toward the gate metal layer50. The well region17is a region of a second conductivity type in which the doping concentration is higher than that of the base region14. The base region14of the present example is of the P− type, and the well region17is of the P+ type.

Each of the transistor portion70and the diode portion80includes a plurality of trench portions arrayed in an array direction on the front surface21of the semiconductor substrate10. In the transistor portion70of the present example, one or more gate trench portions40and one or more dummy trench portions30are alternately provided along the array direction. In the diode portion80of the present example, the plurality of dummy trench portions30are provided along the array direction. In the diode portion80of the present example, the gate trench portion40is not provided.

In the transistor portion70, one or more gate trench portions40are arrayed at a predetermined interval along the array direction of each trench. The gate conductive portion inside the gate trench portion40is electrically connected to the gate metal layer50to be applied by a gate potential. In the transistor portion70, one or more dummy trench portions30may be arrayed at a predetermined interval along the array direction. A potential different from the gate potential is applied to the dummy conductive portion inside the dummy trench portion30. The dummy conductive portion of the present example is electrically connected to the emitter electrode52to be applied by an emitter potential.

In the transistor portion70, one or more gate trench portions40and one or more dummy trench portions30may be formed alternately along the array direction. Also, the dummy trench portions30are arrayed in the diode portion80and the boundary region90at a predetermined interval along the array direction. Note that the transistor portion70may alternatively be constituted only by the gate trench portion40without the dummy trench portion30being provided.

The gate trench portion40of the present example may have two extending portions41extending along the extending direction perpendicular to the array direction (portions of a trench that are linear along the extending direction), and a connecting portion43connecting the two extending portions41. The extending direction inFIG.1Bis the Y axis direction.

Preferably, at least a part of the connecting portion43is provided in a curved shape in the top view. By connecting the end portions of the two extending portions41in the Y axis direction by the connecting portion43, an electric field strength at the end portions of the extending portions41can be reduced.

In the transistor portion70, the dummy trench portions30are provided between the respective extending portions41of the gate trench portions40. One dummy trench portion30may be provided or a plurality of dummy trench portions30may be provided between the respective extending portions41. The dummy trench portion30may have a linear shape extending in the extending direction, or may have extending portions31and a connecting portion33similar to the gate trench portion40. The semiconductor device100shown inFIG.1Bincludes both the linear dummy trench portion30not having the connecting portion33and the dummy trench portion30having the connecting portion33. A direction in which the extending portions41of the gate trench portion40or the extending portions31of the dummy trench portion30extend to be long in the extending direction is referred to as a longitudinal direction of the trench portion. The longitudinal direction of the gate trench portion40or the dummy trench portion30may match with the extending direction. In the present example, the extending direction and the longitudinal direction are the Y axis direction. The array direction in which the plurality of gate trench portions40or dummy trench portions30are arrayed is referred to as a lateral direction of the trench portion. The lateral direction may match with the array direction. The lateral direction may also be perpendicular to the longitudinal direction. In the present example, the lateral direction is perpendicular to the longitudinal direction. In the present example, the array direction and the lateral direction are the X axis direction.

In the connecting portion43at an edge of the gate trench portion40, the gate conductive portion inside the gate trench portion40is connected to the gate runner portion51. The gate trench portion40may be provided protrusively from the dummy trench portion30toward the gate runner portion51side in the extending direction (the Y axis direction). The protruding portion of the gate trench portion40is connected to the gate runner portion51.

A diffusion depth of the well region17may be deeper than the depth of the gate trench portion40and the dummy trench portion30. The end portions of the gate trench portion40and the dummy trench portion30in the Y axis direction are provided in the well region17in a top view. In other words, the bottom in the depth direction of each trench portion is covered with the well region17at the end portion of each trench portion in the Y axis direction. With this configuration, the electric field strength in the bottom of each trench portion can be reduced.

A mesa portion is provided between the respective trench portions in the array direction. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate10. As an example, an upper end of the mesa portion is the upper surface of the semiconductor substrate10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion of the present example is provided extending in the extending direction (the Y axis direction) along the trench portion, on the upper surface of the semiconductor substrate10.

The boundary region90is provided in direct contact with the diode portion80in the transistor portion70. The boundary region90is a region where the emitter region12of the first conductivity type is not provided in the mesa portion on the front surface side of the semiconductor substrate10, and where the collector region22is provided on the back surface side of the semiconductor substrate10. The boundary region90may include the base region14on the front surface21. Note that inFIG.1B, regarding the cathode region82provided on the back surface side of the semiconductor substrate10, a position thereof when projected on the front surface side is shown. The boundary region90is provided with the dummy trench portion30.

The mesa portion71, the mesa portion81, and the mesa portion91are mesa portions respectively provided in the transistor portion70, the diode portion80, and the boundary region90. When merely referred to as the mesa portion in the present specification, it indicates each of the mesa portion71, the mesa portion81, and the mesa portion91. The mesa portion is a portion of the semiconductor substrate10interposed between two trench portions adjacent to each other, and may be a portion ranging from the front surface21of the semiconductor substrate10to the depth of the lowermost bottom portion of each trench portion. The extending portions of each trench portion may be regarded as one trench portion. That is, the region sandwiched between two extending portions may be set to be a mesa portion.

Each mesa portion is provided with the base region14. Of the base regions14exposed on the upper surface of the semiconductor substrate10in the mesa portion, the region arranged closest to the gate metal layer50is referred to as a base region14-e. WhileFIG.1Bshows the base region14-earranged at one end portion of each mesa portion in the extending direction, the base region14-eis also arranged at the other end portion of each mesa portion. In each mesa portion, at least one of the emitter region12of the first conductivity type or the contact region15of the second conductivity type may be provided in a region sandwiched between the base regions14-ein a top view. The emitter region12of the present example is of an N+ type, and the contact region15is of a P+ type. The emitter region12and the contact region15may be provided between the base region14and the upper surface of the semiconductor substrate10in the depth direction.

The mesa portion71of the transistor portion70includes the emitter region12exposed on the upper surface of the semiconductor substrate10. The emitter region12is provided in contact with the gate trench portion40. The mesa portion71in contact with the gate trench portion40may be provided with the contact region15exposed on the upper surface of the semiconductor substrate10.

Each of the contact region15and the emitter region12in the mesa portion71is provided from one trench portion to the other trench portion in the X axis direction. As an example, the contact region15and the emitter region12in the mesa portion71are alternately arranged along the extending direction of the trench portion (the Y axis direction).

In another example, the contact region15and the emitter region12in the mesa portion71may be provided in a stripe shape along the extending direction of the trench portion (the Y axis direction). For example, the emitter region12is provided in a region in contact with the trench portion, and the contact region15is provided in a region sandwiched between the emitter regions12.

The emitter region12is not provided in the mesa portion81of the diode portion80. The base region14and the contact region15may be provided on an upper surface of the mesa portion81. The contact region15may be provided in contact with each of the base regions14-ein a region sandwiched between the base regions14-eon the upper surface of the mesa portion81. The base region14may be provided in a region sandwiched between the contact regions15on the upper surface of the mesa portion81. The base region14may be arranged in an entire region sandwiched between the contact regions15.

The contact hole54is provided above each mesa portion. The contact hole54is arranged in the region sandwiched between the base regions14-e. The contact hole54of the present example is provided above each region of the contact region15, the base region14, and the emitter region12. The contact hole54is not provided in regions corresponding to the base region14-eand the well region17. The contact hole54may be arranged at the center of the mesa portion71in the array direction (the X axis direction).

In the diode portion80, an N+ type cathode region82is provided in a region adjacent to the lower surface of the semiconductor substrate10. The doping concentration of the cathode region82is higher than the doping concentration of the drift region18. On the lower surface of the semiconductor substrate10, a P+ type collector region22may be provided in a region where the cathode region82is not provided. The cathode region82and the collector region22are provided between the back surface23of the semiconductor substrate10and the buffer region20. InFIG.1B, a boundary62between the cathode region82and the collector region22is indicated by a dotted line.

The cathode region82is arranged apart from the well region17in the Y axis direction. With this configuration, it is possible to secure a distance between the P type region (the well region17) that has a relatively high doping concentration and is formed to a deep position and the cathode region82, improve a breakdown voltage, and suppress implantation of holes from the well region17. In the present example, an end portion of the cathode region82in the Y axis direction is arranged farther away from the well region17than an end portion of the contact hole54in the Y axis direction. In another example, the end portion of the cathode region82in the Y axis direction may be arranged between the well region17and the contact hole54.

FIG.2Ais a diagram showing an example of an XZ cross section including a cross section a-a′ inFIG.1B. The XZ cross section including the cross section a-a′ is an XZ plane that passes through the emitter region12in the transistor portion70. The semiconductor device100in the present example has the semiconductor substrate10, the interlayer dielectric film38, the emitter electrode52, and the collector electrode24in the XZ cross section including the cross section a-a′. The emitter electrode52is formed above the semiconductor substrate10and the interlayer dielectric film38.

The drift region18is a region of the first conductivity type, which is provided in the semiconductor substrate10. The drift region18in the present example is of the N− type as an example. The drift region18may be a region that has remained without other doping regions being formed in the semiconductor substrate10. That is, the doping concentration of the drift region18may be a doping concentration of the semiconductor substrate10.

The buffer region20is a region of the first conductivity type, which is provided below the drift region18. The buffer region20of the present example is provided closer to the back surface23of the semiconductor substrate10than a center of the semiconductor substrate10in the depth direction. The buffer region20in the present example is of the N type as an example. The doping concentration of the buffer region20is higher than the doping concentration of the drift region18. The buffer region20may function as a field-stop layer which prevents a depletion layer expanding from the lower surface side of the base region14from reaching the collector region22of the second conductivity type and the cathode region82of the first conductivity type.

The collector region22and the cathode region82are provided on the back surface23of the semiconductor substrate10. The collector region22is provided below the buffer region20in the transistor portion70. The cathode region82is provided below the buffer region20in the diode portion80. The boundary62between the collector region22and the cathode region82may be a boundary between the transistor portion70and the diode portion80.

The collector electrode24is formed on the back surface23of the semiconductor substrate10. The collector electrode24is formed of a conductive material such as metal.

For example, at least a partial region of the collector electrode24may be formed of metal such as aluminum (Al) or a metal alloy such as an aluminum-silicon alloy (AlSi) and an aluminum-silicon-copper alloy (AlSiCu).

The base region14is a region of the second conductivity type, which is provided above the drift region18in the mesa portion71, the mesa portion91, and the mesa portion81. The base region14is provided in contact with the gate trench portion40. The base region14may be provided in contact with the dummy trench portion30.

The emitter region12is provided between the base region14and the front surface21in the mesa portion71. The emitter region12is provided in contact with the gate trench portion40. The emitter region12may or may not be in contact with the dummy trench portion30. Note that the emitter region12may not be provided in the mesa portion91.

The contact region15is provided above the base region14in the mesa portion91. The contact region15is provided in contact with the gate trench portion40in the mesa portion91. In another cross section, the contact region15may be provided on the front surface21in the mesa portion71.

The accumulation region16is a region of the first conductivity type, which is provided closer to the front surface21of the semiconductor substrate10than the drift region18. The accumulation region16in the present example is of the N+ type as an example. The accumulation region16is provided in the mesa portion71. The accumulation region16may also be provided in the mesa portion81and the mesa portion91.

In addition, the accumulation region16is provided in contact with the gate trench portion40. The accumulation region16may or may not be in contact with the dummy trench portion30. The doping concentration of the accumulation region16is higher than the doping concentration of the drift region18. Providing the accumulation region16can enhance the carrier injection enhancement effect (IE effect) to reduce an ON voltage of the transistor portion70.

One or more gate trench portions40and one or more dummy trench portions30are provided on the front surface21. Each trench portion is provided from the front surface21to the drift region18. In a region where at least any of the emitter region12, the base region14, the contact region15, or the accumulation region16is provided, each trench portion also penetrates through these regions to reach the drift region18. The configuration of the trench portion penetrating through the doping region is not limited to that manufactured in the order of forming the doping region and then forming the trench portion. The configuration of the trench portion penetrating through the doping region also includes a configuration of the doping region being formed between the trench portions after forming the trench portion.

The gate trench portion40has a gate trench, a gate dielectric film42, and a gate conductive portion44which are formed in the front surface21. The gate dielectric film42is formed to cover an inner wall of the gate trench. The gate dielectric film42may be formed by oxidizing or nitriding a semiconductor on the inner wall of the gate trench. The gate dielectric film42is formed inside the gate trench, and the gate conductive portion44is formed on an inner side of the gate dielectric film42. The gate dielectric film42insulates the gate conductive portion44from the semiconductor substrate10. The gate conductive portion44is formed of a conductive material such as polysilicon. The gate trench portion40is covered by the interlayer dielectric film38on the front surface21.

The gate conductive portion44includes a region opposing the adjacent base region14on the mesa portion71side with the gate dielectric film42interposed therebetween in a depth direction of the semiconductor substrate10. When a predetermined voltage is applied to the gate conductive portion44, a channel is formed to a surface layer being at a boundary within the base region14and in direct contact with the gate trench, due to an electron inversion layer.

The dummy trench portion30may have the same structure as the gate trench portion40. The dummy trench portion30has a dummy trench, a dummy dielectric film32, and a dummy conductive portion34which are formed in the front surface21side. The dummy dielectric film32is formed to cover the inner wall of the dummy trench. The dummy conductive portion34is formed inside the dummy trench and also formed on the inner side of the dummy dielectric film32. The dummy dielectric film32insulates the dummy conductive portion34from the semiconductor substrate10. The dummy trench portion30is covered by the interlayer dielectric film38in the front surface21.

The interlayer dielectric film38is provided at the front surface21. The emitter electrode52is provided above the interlayer dielectric film38. In the interlayer dielectric film38, one or more contact holes54are provided for electrically connecting the emitter electrode52to the semiconductor substrate10. Similarly, the contact hole55and the contact hole56may be provided to penetrate through the interlayer dielectric film38.

The lifetime control portion150is provided in the semiconductor substrate10and contains a lifetime killer. The lifetime control portion150may be a region where a lifetime killer is intentionally formed by implanting an impurity into the semiconductor substrate10, or the like. In one example, the lifetime control portion150is formed by implanting helium into the semiconductor substrate10. By providing the lifetime control portion150, a turn-off time is reduced and a tail current is suppressed, and thus losses during switching can be reduced.

The lifetime killer is a recombination center of carriers. The lifetime killer may be a lattice defect. For example, the lifetime killer may be a vacancy, a divacancy, a defect complex of these with elements configuring the semiconductor substrate10, or dislocation. Furthermore, the lifetime killer may be a noble gas element such as helium and neon, a metal element such as platinum, or the like. The lifetime killer may be a recombination center formed closer to an implantation surface of the semiconductor substrate10than hydrogen that has stopped, after hydrogen ions are implanted into the implantation surface. An electron beam may be used for forming the lattice defect. An impurity dose amount for forming the lifetime control portion150may be 0.5 E10 cm−2or more and 1.0 E13 cm−2or less, or may be 5.0 E10 cm−2or more and 5.0 E11 cm−2or less. Acceleration energy for forming the lifetime control portion150may be 100 keV or more and 100 MeV or less.

A lifetime killer concentration is a concentration at the recombination center of carriers. The lifetime killer concentration may be a concentration of the lattice defect. For example, the lifetime killer concentration may be a vacancy concentration of a vacancy, a divacancy, or the like, may be a defect complex concentration of these vacancies with elements configuring the semiconductor substrate10, or may be a dislocation concentration. Alternatively, the lifetime killer concentration may be a chemical concentration of the noble gas element such as helium and neon, or may be a chemical concentration of the metal element such as platinum.

The lifetime control portion150includes at least one of a front surface side lifetime control region151or a back surface side lifetime control region152. The lifetime control portion150includes a main region156and a decay region157.

The front surface side lifetime control region151is provided closer to the front surface21than the center of the semiconductor substrate10in the depth direction. The front surface side lifetime control region151may include the main region156and the decay region157.

The back surface side lifetime control region152is provided closer to the back surface23than the center of the semiconductor substrate10in the depth direction. The back surface side lifetime control region152of the present example is provided in the buffer region20. The back surface side lifetime control region152may include the main region156and the decay region157.

The lifetime control portion150may be formed by implanting impurity ions for forming a lifetime killer from the back surface23side. The impurity ions for forming a lifetime killer may simply be referred to as the impurity ions. The impurity ions are, for example, helium ions. With this configuration, an effect on the front surface21side of the semiconductor device100can be avoided. For example, the lifetime control portion150is formed by implanting helium ions from the back surface23side. Herein, which of the front surface21side and the back surface23side the implantation is performed from for forming the lifetime control portion150can be determined by acquiring a state on the front surface21side by the SRP method or a measurement of a leak current.

The method of forming the front surface side lifetime control region151and that of the back surface side lifetime control region152may be the same or may differ. Both of the front surface side lifetime control region151and the back surface side lifetime control region152may be formed by implanting impurity ions from the back surface23side. The front surface side lifetime control region151may be formed by implanting impurity ions from the front surface21side, and the back surface side lifetime control region152may be formed by implanting impurity ions from the back surface23side. Both of the front surface side lifetime control region151and the back surface side lifetime control region152may be formed by implanting impurity ions from the front surface21side. The impurity ion dose amounts when respectively forming the front surface side lifetime control region151and the back surface side lifetime control region152may be the same or may differ.

The main region156is provided in the diode portion80. The main region156may be a region obtained by directly implanting impurity ions. For example, when forming the lifetime control portion150using a mask, the main region156is a region not covered by the mask. The main region156of the front surface side lifetime control region151and that of the back surface side lifetime control region152may be provided in the same region in a top view, or may be provided in different regions.

The decay region157is provided to extend from the main region156in a direction parallel to the front surface21of the semiconductor substrate10. The decay region157is a region where the lifetime killer concentration has decayed more than in the main region156. The decay region157may be a region formed by a thermal diffusion of the implanted impurity instead of the region implanted with the impurity ions. The decay region157of the front surface side lifetime control region151and that of the back surface side lifetime control region152may be provided in the same region in a top view, or may be provided in different regions.

The decay region157of the present example is provided to extend from the main region156in the direction parallel to the front surface21of the semiconductor substrate10in the diode portion80. That is, the diode portion80includes the main region156and the decay region157. The decay region157of the present example extends from the main region156to the boundary62between the collector region22and the cathode region82in the array direction. The decay region157may extend from the main region156to the boundary62between the collector region22and the cathode region82in the array direction, and be terminated at the boundary62.

Herein, a width of the diode portion80in the trench array direction is represented by Wa, a width of the decay region157in the trench array direction is represented by Wb, and a width of the main region156in the trench array direction is represented by Wc. In this case, Wa>Wc may be satisfied, or (Wa−2Wb)>Wc may be satisfied. The width Wc of the main region156in the trench array direction may be smaller than the width Wa of the diode portion80in the trench array direction. The main region156may be formed inside the diode portion80. Note that the width Wb of the decay region157in the trench array direction may be the same as a diffusion half width at half maximum Wh of the lifetime killer for forming the lifetime control portion150in the direction parallel to the front surface21of the semiconductor substrate10. The diffusion half width at half maximum Wh will be described below.

The main region156may occupy 80% or more of the width of the diode portion80in the trench array direction. That is, 0.8 (Wa−2Wb)/Wa<1.0 may be satisfied.

FIG.2Bis an example of a lifetime killer concentration in a cross section m-m′ inFIG.2A. The cross section m-m′ passes through the front surface side lifetime control region151in the X axis direction. The lifetime killer concentration distribution in the main region156may be uniform. The decay region157is a region where the lifetime killer concentration decays. The lifetime killer concentration distribution in the decay region157may be a Gaussian distribution.

Positions x1and x1′ of end portions of the lifetime control portion150are positions at which the lifetime killer concentration of the decay region157becomes half of a maximum value or average concentration of the lifetime killer concentration in the main region156. Positions x2and x2′ are positions at which the lifetime killer concentration of the main region156starts to decay in the horizontal direction (the X axis direction). That is, the positions x2and x2′ are positions of end portions of the main region156. The width We of the main region156is a distance between the position x2and the position x2′. The width Wb of the decay region157is a distance between the position x1and the position x2or a distance between the position x1′ and the position x2′. The width Wb of the decay region157is a half width at half maximum (HWHM) of the lifetime killer concentration distribution. The half width at half maximum may be a diffusion half width at half maximum Wh.

In the lifetime killer concentration distribution, a portion having a concentration lower than a concentration at the position x1or the position x1′ is set as a seeping portion158. The positions x1and x1′ of the end portions of the lifetime control portion150in the present example each match with the boundary62. That is, the seeping portion158of the lifetime killer concentration distribution may be positioned in the boundary region90, or may be positioned in the transistor portion70.

FIG.3Ais an XZ cross section including the cross section a-a′ and shows a modified example of the semiconductor device100. The semiconductor device100of the present example includes the lifetime control portion150in a different region from the semiconductor device100shown inFIG.2A. In the present example, differences with the semiconductor device100shown inFIG.2Awill be described in particular.

The front surface side lifetime control region151and the back surface side lifetime control region152are provided in different regions in a top view. The front surface side lifetime control region151of the present example includes the main region156and the decay region157. The back surface side lifetime control region152does not need to include the decay region157. The lifetime control portion150of the present example may or may not include at least one of the front surface side lifetime control region151or the back surface side lifetime control region152.

The front surface side lifetime control region151and the back surface side lifetime control region152may be provided in the same region. That is, the main region156of the front surface side lifetime control region151may be provided in the same region as the main region156of the back surface side lifetime control region152in the top view. The decay region157of the front surface side lifetime control region151may be provided in the same region as the decay region157of the back surface side lifetime control region152in the top view. Note that the front surface side lifetime control region151and the back surface side lifetime control region152may alternatively be provided in different regions.

The main region156is terminated without extending from above the cathode region82to the boundary62between the collector region22and the cathode region82in the trench array direction. The decay region157extends from the main region156to above the collector region22beyond the boundary62between the collector region22and the cathode region82. The decay region157of the present example extends from the main region156to an inside of the boundary region90, but may alternatively extend beyond the boundary region90. Herein, descriptions are given as the main region156and the decay region157of the front surface side lifetime control region151. Note that similarly, the back surface side lifetime control region152may also include the main region156and the decay region157at positions respectively corresponding to the main region156and the decay region157of the present example.

FIG.3Bis an example of the lifetime killer concentration in the cross section m-m′ inFIG.3A. In the present example, differences with the semiconductor device100shown inFIGS.2Aand2B will be described in particular. The boundary62of the present example is positioned between the position x1(or x1′) of the end portion of the lifetime control portion150and the position x2(or x2′) of the end portion of the main region156. In other words, the boundary62is positioned in the decay region157. The seeping portion158of the lifetime killer concentration distribution may be positioned apart from the boundary62toward an outer side. The seeping portion158may be positioned in the boundary region90, or may be positioned in the transistor portion70.

FIG.4Ais an XZ cross section including the cross section a-a′ and shows a modified example of the semiconductor device100. The semiconductor device100of the present example includes the lifetime control portion150in a different region from the semiconductor device100shown inFIGS.2A and3A. In the present example, differences with the semiconductor device100shown inFIGS.2A and3Awill be described in particular.

The lifetime control portion150is provided in the diode portion80, and does not need to be provided in the transistor portion70. In the present example, both of the front surface side lifetime control region151and the back surface side lifetime control region152are provided in the diode portion80and are not provided in the transistor portion70. One of the front surface side lifetime control region151or the back surface side lifetime control region152may be omitted.

The front surface side lifetime control region151and the back surface side lifetime control region152may be provided in the same region. That is, the main region156of the front surface side lifetime control region151may be provided in the same region as the main region156of the back surface side lifetime control region152in the top view. The decay region157of the front surface side lifetime control region151may be provided in the same region as the decay region157of the back surface side lifetime control region152in the top view. Note that the front surface side lifetime control region151and the back surface side lifetime control region152may alternatively be provided in different regions.

The main region156extends in the trench array direction above the cathode region82, and is terminated without extending to the boundary62between the collector region22and the cathode region82. The decay region157extends from the main region156in the trench array direction, and is terminated without extending to the boundary62between the collector region22and the cathode region82. That is, the semiconductor device100of the present example has a distance Wd between the end portion of the decay region157and the boundary62. The distance Wd of the present example is a distance in the trench array direction, but the distance Wd may also be provided in the trench extending direction. The distance Wd may be smaller than the width Wb, may be the same as the width Wb, or may be larger than the width Wb.

In the present example, the width Wa of the diode portion80in the trench array direction may be larger than the width Wc of the main region156in the trench array direction. That is, Wa>Wc may be satisfied. Further, the width Wa of the diode portion80in the trench array direction may be larger than the width Wc+2Wb of the lifetime control portion150. That is, Wa>Wc+2Wb may be satisfied.

FIG.4Bis an example of the lifetime killer concentration in the cross section m-m′ inFIG.4A. In the present example, differences with the semiconductor device100shown inFIGS.3A and3Bwill be described in particular. The boundary62of the present example is positioned apart from the position x1(or x1′) of the end portion of the lifetime control portion150toward the outer side. The seeping portion158of the lifetime killer concentration distribution may be positioned in the diode portion80. Alternatively, the seeping portion158may extend from the inside of the diode portion80to the boundary62. An end portion of the seeping portion158may be the boundary62. The boundary62may be positioned more on the outer side toward the transistor side than the position x1(or x1′).

FIG.5Ais an XZ cross section including the cross section a-a′ and shows a modified example of the semiconductor device100. The semiconductor device100of the present example includes the lifetime control portion150in a different region from the semiconductor device100shown inFIG.3A. In the present example, differences with the semiconductor device100shown inFIG.3Awill be described in particular.

The back surface side lifetime control region152of the present example is provided across the entire surface of the semiconductor substrate10. The back surface side lifetime control region152of the present example is provided across the entire surface of the semiconductor substrate10in the XY plane, and can be formed without using a mask. Since the back surface side lifetime control region152of the present example is formed by implanting an impurity across the entire surface of the back surface23, the main region156is provided across the entire surface of the semiconductor substrate10. On the other hand, in the case of the present example, the back surface side lifetime control region152does not include the decay region157.

The front surface side lifetime control region151is provided in a different region from the back surface side lifetime control region152in the top view. The front surface side lifetime control region151of the present example includes the main region156and the decay region157.

The main region156is terminated without extending from above the cathode region82to the boundary62between the collector region22and the cathode region82in the trench array direction. The decay region157of the present example extends from the main region156to above the collector region22beyond the boundary62between the collector region22and the cathode region82. As in the other examples, the decay region157may be terminated without extending beyond the boundary62between the collector region22and the cathode region82, or may be terminated at the boundary62between the collector region22and the cathode region82.

Note that the front surface side lifetime control region151and the back surface side lifetime control region152are not limited to the examples described above. For example, the front surface side lifetime control region151may be the example shown inFIG.2A, and the back surface side lifetime control region152may be the example shown inFIG.3Aor the example shown inFIG.4A. Alternatively, the front surface side lifetime control region151may be the example shown inFIG.3A, and the back surface side lifetime control region152may be the example shown inFIG.2Aor the example shown inFIG.4A. Alternatively, the front surface side lifetime control region151may be the example shown inFIG.4A, and the back surface side lifetime control region152may be the example shown inFIG.2Aor the example shown inFIG.3A.

FIG.5Bis an example of the lifetime killer concentration in the cross section m-m′ inFIG.5A.FIG.5Bis the same asFIG.3B.

FIG.6shows an example of the doping concentration distribution of the buffer region20. The back surface side lifetime control region152of the present example is formed by implanting helium ions, but the method of forming the back surface side lifetime control region152is not limited to this. Herein, an effect of forming the back surface side lifetime control region152, on the buffer region20will be described.

The solid line indicates the doping concentration distribution of the buffer region20in a case where the back surface side lifetime control region152is provided. The broken line indicates the doping concentration distribution of the buffer region20in a case where the back surface side lifetime control region152is not provided.

The buffer region20has one or more peaks of the doping concentration in the depth direction of the semiconductor substrate10. The buffer region20of the present example has four peaks of the doping concentration in the depth direction of the semiconductor substrate10. The buffer region20has the peaks in the stated order of a first peak121, a second peak122, a third peak123, and a fourth peak124from the back surface23in the depth direction of the semiconductor substrate10. Depth positions D1to D4respectively indicate distances of the first peak121to the fourth peak124from the back surface23in the depth direction. The buffer region20may be formed by implanting hydrogen ions. That is, the buffer region20may contain a hydrogen donor. The semiconductor substrate10of the present example is formed by using the MCZ method, but the present invention is not limited to this.

The chain double-dashed line indicates the lifetime killer concentration when forming the back surface side lifetime control region152. A depth position Dk indicates a distance between the back surface23and a peak of the back surface side lifetime control region152in the depth direction of the semiconductor substrate10. The back surface side lifetime control region152may be provided between the second peak122and the third peak123in the depth direction of the semiconductor substrate10. That is, the depth position Dk of the back surface side lifetime control region152from the back surface23may be larger than a depth position D2of the second peak122from the back surface23and smaller than a depth position D3of the third peak123from the back surface23. The back surface side lifetime control region152of the present example has a peak of the lifetime killer concentration at a position that is 10 μm or more and 15 μm or less from the back surface23of the semiconductor substrate10in the depth direction of the semiconductor substrate10.

The depth position Dk of the back surface side lifetime control region152from the back surface23may be deeper than a peak formed at a shallowest position from the back surface23in the buffer region20. That is, the depth position Dk may be larger than the depth position D1. The depth position Dk of the back surface side lifetime control region152from the back surface23may be shallower than a peak formed at a deepest position from the back surface23in the buffer region20. That is, when the buffer region20has four peaks as in the present example, the depth position Dk may be smaller than the depth position D4.

Herein, in the transistor portion70, by providing the back surface side lifetime control region152, a recombination center may be formed to inhibit implantation of holes from the back surface23and thus lower a back surface avalanche withstand capability. Further, by forming the back surface side lifetime control region152, the concentration of the one or more peaks of the buffer region20formed by hydrogen may become high. In the present example, the doping concentration between the third peak123and the fourth peak124has become high by the formation of the lifetime killer. When the doping concentration of the buffer region20becomes high, implantation of holes from the back surface23may be inhibited to thus lower the back surface avalanche withstand capability.

By providing the main region156implanted with the lifetime killer inside the diode portion80in the semiconductor device100, a fall of the back surface avalanche withstand capability can be suppressed. Even when using an MCZ substrate with which the concentration of the buffer region20is apt to become high in the semiconductor device100of the present example, it is possible to avoid a situation where the concentration of the buffer region20becomes high and suppress a fall of the back surface avalanche withstand capability. Moreover, by not providing the lifetime control portion150in the transistor portion70in the semiconductor device100, an increase in leak current and thermal runaway of elements can be suppressed.

FIG.7Ashows a relationship between a collector-emitter shutdown current Ices and an implantation region of the front surface side lifetime control region151. The collector-emitter shutdown current Ices is a collector-emitter leak current that is caused when a predetermined voltage is applied between the collector and the emitter in a state where gate-emitter is short-circuited.

Example 1 is an example of a case where the front surface side lifetime control region151is provided only in the diode portion80, and the overlapping width Wo=10 μm. The overlapping width Wo indicates a width by which the mask for forming the lifetime control portion150overlaps with the diode portion80. The overlapping width Wo will be described below.

Example 2 is an example of a case where the front surface side lifetime control region151is provided only in the diode portion80, and the overlapping width Wo=0 μm. Comparative Example 1 is an example of a case where the front surface side lifetime control region151is implanted across the entire surface of the semiconductor substrate10.

When the collector-emitter shutdown current Ices of Example 2 is 100%, Ices of Comparative Example 1 was 620%, and Ices of Example 1 was 97%. In this manner, by providing the front surface side lifetime control region151in only the diode portion80, a leak current can be significantly reduced.

FIG.7Bshows a relationship between the collector-emitter shutdown current Ices and an implantation region of the back surface side lifetime control region152.

Example 3 is an example of a case where the back surface side lifetime control region152is not provided. Example 4 is an example of a case where the back surface side lifetime control region152is provided in only the diode portion80. Example 5 is an example of a case where the back surface side lifetime control region152is implanted across the entire surface of the semiconductor substrate10.

When the collector-emitter shutdown current Ices of Example 5 is 100%, Ices of Example 3 was 80%, and Ices of Example 4 was 85%. In this manner, by changing the implantation region of the back surface side lifetime control region152, a leak current amount can be adjusted. The region to provide the back surface side lifetime control region152may be determined as appropriate considering a trade-off with a switching loss and the like.

FIG.7Cshows a relationship between a high-current short circuit withstand capability and the implantation region of the back surface side lifetime control region152. As an example, the high-current short circuit withstand capability is a maximum gate-emitter voltage value that can be shut off safely when the gate-emitter voltage is increased to +15 V or more and the semiconductor device100is caused to short-circuit.

Example 6 is an example of a case where the back surface side lifetime control region152is provided in only the diode portion80. Example 7 is an example of a case where the back surface side lifetime control region152is implanted across the entire surface of the semiconductor substrate10.

When the high-current short circuit withstand capability of Example 7 is 100%, the high-current short circuit withstand capability of Example 6 was 167%. In this manner, by changing the implantation region of the back surface side lifetime control region152, the high-current short circuit withstand capability can be adjusted. The region to provide the back surface side lifetime control region152may be determined as appropriate considering a trade-off with a switching loss and the like.

FIG.8shows an example of a helium ion implantation process that uses a mask210. In the present example, the lifetime control portion150is selectively formed using the mask210.

The mask210is formed on the front surface21or the back surface23of the semiconductor substrate10for forming the lifetime control portion150. The mask210of the present example is provided on the back surface23side and suppresses implantation of helium ions into the semiconductor substrate10. When helium ions are implanted from the front surface21side, the mask210is provided on the front surface21side. The lifetime control portion150is formed by implanting helium ions via a mask opening portion of the mask210. That is, the mask opening portion of the mask210is provided in a region corresponding to the main region156where helium ions are to be implanted. On the other hand, the decay region157is covered by the mask210.

In the present example, a lifetime killer is implanted via a uniform mask opening portion where the mask210is not formed. The mask210of the present example is not provided in the main region156. Therefore, the main region156has a uniform doping concentration in a direction parallel to the front surface21of the semiconductor substrate10. The uniform mask opening portion refers to a mask opening portion not having a repetitive structure in which an opened portion and an unopened portion of the mask are repetitively arranged as in a checkerboard pattern. On the other hand, when the repetitive structure such as a checkerboard pattern is provided in the main region156to form the lifetime control portion150, the doping concentration of the lifetime control portion150may not become uniform.

The overlapping width Wo indicates a width by which the mask210overlaps with the diode portion80. The overlapping width Wo may be equal to or larger than the diffusion half width at half maximum Wh by which the lifetime killer is diffused. The overlapping width Wo may be equal to a sum of the width Wb of the decay region157in the trench array direction and the distance Wd between the end portion of the decay region157and the boundary62. In other words, of the overlapping width Wo of the mask210covering the diode portion80, a width by which the lifetime killer is diffused is the width Wb, and the rest is the distance Wd.

Note that although the overlapping width Wo of the present example indicates the width by which the mask210overlaps with the diode portion80in the trench array direction, a width by which the mask210overlaps with the diode portion80in the trench extending direction may also be of a similar size.

FIG.9Ais a diagram for describing the diffusion half width at half maximum Wh by which the lifetime killer is diffused. The diffusion half width at half maximum Wh may be a half width at half maximum (HWHM) of the lifetime killer concentration distribution after diffusion. The lifetime killer concentration of the main region156implanted with the lifetime killer becomes a lifetime killer concentration corresponding to a peak of the distribution. The decay region157not implanted with the lifetime killer has a lifetime killer concentration that has decayed along the lifetime killer concentration distribution shown in the present figure.

That is, the width Wb of the decay region157is the diffusion half width at half maximum Wh by which the lifetime killer for forming the main region156is diffused. The width Wb of the decay region157may be 0.1 μm or more and 10.0 μm or less. The width Wb of the decay region157may be the same in the trench array direction and the trench extending direction.

FIG.9Bis another example of the lifetime killer concentration distribution in the cross section m-m′ inFIG.2Aand the like. The lifetime killer concentration in the main region156may vary around the average concentration. Regarding a variation ratio of the lifetime killer concentration, a minimum value in the main region156may be 50% or more of a maximum value. Regarding the variation ratio of the lifetime killer concentration, a width between the maximum value and the minimum value may be 50% or less of the average concentration of the lifetime killer concentration in the main region156. In such a case, the lifetime killer concentration distribution in the main region156may be assumed to be substantially flat or substantially uniform.

FIG.10shows an example of a top view of the semiconductor device100. The present example shows regions where the main region156and the decay region157are provided in the top view of the semiconductor device100shown inFIG.1A.

The main region156may be sandwiched between the decay regions157in the trench array direction. The main region156may be sandwiched between the decay regions157in the trench extending direction. The main region156of the present example is sandwiched between the decay regions157in each of the trench array direction and the trench extending direction. That is, the main region156of the present example is enclosed by the decay regions157in the direction parallel to the front surface21of the semiconductor substrate10. The main region156and the decay region157may be the front surface side lifetime control region151, or may be the back surface side lifetime control region152.

The main region156may be provided in the same region as the diode portion80. That is, the main region156may be provided in the same region as the cathode region82in the top view. The decay region157may be provided inside the transistor portion70. That is, the decay region157may be provided to overlap with the collector region22in the top view. In this manner, in the present example, the mask opening portion of the mask210is provided in a region corresponding to the diode portion80in the top view, and the lifetime killer is then implanted, to thus form the main region156in the diode portion80and form the decay regions157around the diode portion80.

FIG.11Ais a top view showing a modified example of the semiconductor device100. The present example differs from the top view of the semiconductor device100shown inFIG.1Bin that the positions of the main region156and the decay region157are illustrated. In the present example, differences with the semiconductor device100shown inFIG.1Bwill be described in particular.

The main region156extends from the inside of the cathode region82to the boundary62between the collector region22and the cathode region82in the top view. The main region156of the present example extends from the inside of the cathode region82to the boundary62between the collector region22and the cathode region82in both the trench array direction and the trench extending direction.

The decay region157extends from the boundary62between the collector region22and the cathode region82to the inside of the collector region22in the top view. The decay region157of the present example extends from the boundary62between the collector region22and the cathode region82to the inside of the collector region22in both the trench array direction and the trench extending direction. The width of the decay region157may be the same in the trench array direction and the trench extending direction. The width of the decay region157in the trench array direction and the width thereof in the trench extending direction may both be the diffusion half width at half maximum Wh.

FIG.11Bis a top view showing a modified example of the semiconductor device100. In the present example, the positions of the main region156and the decay region157differ from those in the top view of the semiconductor device100shown inFIG.11A. In the present example, differences with the semiconductor device100shown inFIG.11Awill be described in particular.

The main region156extends from the inside of the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10in the top view, and is terminated without extending to the boundary62between the collector region22and the cathode region82. In both the trench array direction and the trench extending direction, the main region156of the present example extends from the inside of the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10, and is terminated without extending to the boundary62between the collector region22and the cathode region82.

The decay region157extends from the main region156to the inside of the collector region22beyond the boundary62between the collector region22and the cathode region82in the top view. In both the trench array direction and the trench extending direction, the decay region157of the present example extends from the main region156to the inside of the collector region22beyond the boundary62between the collector region22and the cathode region82.

FIG.11Cis a top view showing a modified example of the semiconductor device100. In the present example, the positions of the main region156and the decay region157differ from those in the top view of the semiconductor device100shown inFIGS.11A and11B. In the present example, differences with the semiconductor device100shown inFIGS.11A and11Bwill be described in particular.

The main region156extends from the inside of the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10in the top view, and is terminated without extending to the boundary62between the collector region22and the cathode region82. In both the trench array direction and the trench extending direction, the main region156of the present example extends from the inside of the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10, and is terminated without extending to the boundary62between the collector region22and the cathode region82.

The decay region157extends from the main region156to the boundary62between the collector region22and the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10in the top view, and is terminated at the boundary62. In both the trench array direction and the trench extending direction, the decay region157of the present example extends from the main region156to the boundary62between the collector region22and the cathode region82, and is terminated at the boundary62.

FIG.11Dis a top view showing a modified example of the semiconductor device100. In the present example, the positions of the main region156and the decay region157differ from those in the top view of the semiconductor device100shown inFIGS.11A to11C. In the present example, differences with the semiconductor device100shown inFIGS.11A to11Cwill be described in particular.

The main region156extends from the inside of the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10in the top view, and is terminated without extending to the boundary62between the collector region22and the cathode region82. In both the trench array direction and the trench extending direction, the main region156of the present example extends from the inside of the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10, and is terminated without extending to the boundary62between the collector region22and the cathode region82.

The decay region157extends from the main region156in the direction parallel to the front surface21of the semiconductor substrate10in the top view, and is terminated without extending to the boundary62between the collector region22and the cathode region82. In both the trench array direction and the trench extending direction, the decay region157of the present example extends from the main region156in the direction parallel to the front surface21of the semiconductor substrate10, and is terminated without extending to the boundary62between the collector region22and the cathode region82.

The distance between the boundary62and the decay region157may be the same in the trench array direction and the trench extending direction, or may differ between the trench array direction and the trench extending direction. The distance between the boundary62and the decay region157may be the same as the diffusion half width at half maximum Wh, may be larger than the diffusion half width at half maximum Wh, or may be smaller than the diffusion half width at half maximum Wh.

FIG.12Ais a top view showing a modified example of the semiconductor device100. In the present example, the positions of the main region156and the decay region157in the trench extending direction differ from those in the top view of the semiconductor device100shown inFIG.11A. In the present example, differences with the semiconductor device100shown inFIG.11Awill be described in particular.

The main region156extends from the inside of the cathode region82to the inside of the collector region22beyond the boundary62between the collector region22and the cathode region82in the trench extending direction. On the other hand, the main region156extends from the inside of the cathode region82to the boundary62between the collector region22and the cathode region82in the trench array direction. In this manner, the main region156may be provided to extend to different positions in the trench array direction and the trench extending direction regarding the relationship with the boundary62.

The decay region157extends from the main region156in the direction parallel to the front surface21of the semiconductor substrate10in the trench extending direction, and is terminated inside the collector region22. On the other hand, the decay region157extends from the boundary62between the collector region22and the cathode region82to the inside of the collector region22in the trench array direction. The width of the decay region157may be the same in the trench array direction and the trench extending direction. The decay region157may be provided to extend to different positions in the trench array direction and the trench extending direction regarding the relationship with the boundary62.

In the semiconductor device100of the present example, by providing the lifetime control portion150such that it extends beyond the boundary62at the end portion of the diode portion80in the trench extending direction, it becomes easy to avoid a destructive failure of elements during reverse recovery.

FIG.12Bis a top view showing a modified example of the semiconductor device100. In the present example, the positions of the main region156and the decay region157in the trench extending direction differ from those in the top view of the semiconductor device100shown inFIG.11B. In the present example, differences with the semiconductor device100shown inFIG.11Bwill be described in particular.

The main region156extends from the inside of the cathode region82to the inside of the collector region22beyond the boundary62between the collector region22and the cathode region82in the trench extending direction. On the other hand, the main region156extends from the inside of the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10in the trench array direction, and is terminated without extending to the boundary62between the collector region22and the cathode region82. In this manner, the main region156may be provided to extend to different positions in the trench array direction and the trench extending direction regarding the relationship with the boundary62.

The decay region157extends from the main region156in the direction parallel to the front surface21of the semiconductor substrate10in the trench extending direction, and is terminated inside the collector region22. On the other hand, the decay region157extends from the main region156to the inside of the collector region22beyond the boundary62between the collector region22and the cathode region82in the trench array direction. The width of the decay region157may be the same in the trench array direction and the trench extending direction. The decay region157may be provided to extend to different positions in the trench array direction and the trench extending direction regarding the relationship with the boundary62.

FIG.12Cis a top view showing a modified example of the semiconductor device100. In the present example, the positions of the main region156and the decay region157in the trench extending direction differ from those in the top view of the semiconductor device100shown inFIG.11C. In the present example, differences with the semiconductor device100shown inFIG.11Cwill be described in particular.

The main region156extends from the inside of the cathode region82to the inside of the collector region22beyond the boundary62between the collector region22and the cathode region82in the trench extending direction. On the other hand, the main region156extends from the inside of the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10in the trench array direction, and is terminated without extending to the boundary62between the collector region22and the cathode region82. In this manner, the main region156may be provided to extend to different positions in the trench array direction and the trench extending direction regarding the relationship with the boundary62.

The decay region157extends from the main region156in the direction parallel to the front surface21of the semiconductor substrate10in the trench extending direction, and is terminated inside the collector region22. On the other hand, the decay region157extends from the main region156to the boundary62between the collector region22and the cathode region82in the trench array direction, and is terminated at the boundary62. The width of the decay region157may be the same in the trench array direction and the trench extending direction. The decay region157may be provided to extend to different positions in the trench array direction and the trench extending direction regarding the relationship with the boundary62.

FIG.12Dis a top view showing a modified example of the semiconductor device100. In the present example, the positions of the main region156and the decay region157in the trench extending direction differ from those in the top view of the semiconductor device100shown inFIG.11D. In the present example, differences with the semiconductor device100shown inFIG.11Dwill be described in particular.

The main region156extends from the inside of the cathode region82to the inside of the collector region22beyond the boundary62between the collector region22and the cathode region82in the trench extending direction. On the other hand, the main region156extends from the inside of the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10in the trench array direction, and is terminated without extending to the boundary62between the collector region22and the cathode region82. In this manner, the main region156may be provided to extend to different positions in the trench array direction and the trench extending direction regarding the relationship with the boundary62.

The decay region157extends from the main region156in the direction parallel to the front surface21of the semiconductor substrate10in the trench extending direction, and is terminated inside the collector region22. On the other hand, the decay region157extends from the main region156in the direction parallel to the front surface21of the semiconductor substrate10in the trench array direction, and is terminated without extending to the boundary62between the collector region22and the cathode region82. The width of the decay region157may be the same in the trench array direction and the trench extending direction. The decay region157may be provided to extend to different positions in the trench array direction and the trench extending direction regarding the relationship with the boundary62.

FIG.13Ais a top view showing a modified example of the semiconductor device100. The present example differs from the top view of the semiconductor device100shown inFIG.11Ain that the boundary region90includes the contact region15. In the present example, differences with the semiconductor device100shown inFIG.11Awill be described in particular.

The boundary region90includes the contact region15on the front surface21of the mesa portion91. The mesa portion91of the present example includes only the contact region15in a region sandwiched between the base regions14-ein the top view. Note that the mesa portion91may include both the base region14and the contact region15in the region sandwiched between the base regions14-ein the top view.

The main region156extends from the inside of the cathode region82to the boundary62between the collector region22and the cathode region82in both the trench array direction and the trench extending direction. The decay region157extends from the boundary62between the collector region22and the cathode region82to the inside of the collector region22in both the trench array direction and the trench extending direction. The decay region157of the present example extends to the mesa portion91in the trench array direction in the top view, and is also provided in a region overlapping with the contact region15.

FIG.13Bis a top view showing a modified example of the semiconductor device100. The present example differs from the top view of the semiconductor device100shown inFIG.11Bin that the boundary region90includes the contact region15. In the present example, differences with the semiconductor device100shown inFIG.11Bwill be described in particular.

In both the trench array direction and the trench extending direction, the main region156extends from the inside of the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10, and is terminated without extending to the boundary62between the collector region22and the cathode region82. In both the trench array direction and the trench extending direction, the decay region157extends from the main region156to the inside of the collector region22beyond the boundary62between the collector region22and the cathode region82.

FIG.13Cis a top view showing a modified example of the semiconductor device100. The present example differs from the top view of the semiconductor device100shown inFIG.11Cin that the boundary region90includes the contact region15. In the present example, differences with the semiconductor device100shown inFIG.11Cwill be described in particular.

In both the trench array direction and the trench extending direction, the main region156extends from the inside of the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10, and is terminated without extending to the boundary62between the collector region22and the cathode region82. In both the trench array direction and the trench extending direction, the decay region157extends from the main region156to the boundary62between the collector region22and the cathode region82, and is terminated at the boundary62.

FIG.13Dis a top view showing a modified example of the semiconductor device100. The present example differs from the top view of the semiconductor device100shown inFIG.11Din that the boundary region90includes the contact region15. In the present example, differences with the semiconductor device100shown inFIG.11Dwill be described in particular.

In both the trench array direction and the trench extending direction, the main region156extends from the inside of the cathode region82in the direction parallel to the front surface21of the semiconductor substrate10, and is terminated without extending to the boundary62between the collector region22and the cathode region82. In both the trench array direction and the trench extending direction, the decay region157extends from the main region156in the direction parallel to the front surface21of the semiconductor substrate10, and is terminated without extending to the boundary62between the collector region22and the cathode region82.

FIG.14Ais a top view showing a modified example of the semiconductor device100. The present example differs from the top view of the semiconductor device100shown inFIG.12Ain that the boundary region90includes the contact region15. In the present example, differences with the semiconductor device100shown inFIG.12Awill be described in particular. Similar toFIG.13A, the semiconductor device100of the present example includes the contact region15in the mesa portion91of the boundary region90.

The main region156extends from the inside of the cathode region82to the boundary62between the collector region22and the cathode region82in the trench array direction. The decay region157extends from the boundary62between the collector region22and the cathode region82to the inside of the collector region22in the trench array direction. The decay region157of the present example extends to the mesa portion91in the trench array direction in the top view, and is also provided in a region overlapping with the contact region15.

FIG.14Bis a top view showing a modified example of the semiconductor device100. The present example differs from the top view of the semiconductor device100shown inFIG.12Bin that the boundary region90includes the contact region15.

The main region156is terminated without extending to the boundary62between the collector region22and the cathode region82in the trench array direction, but extends to the inside of the collector region22beyond the boundary62between the collector region22and the cathode region82in the trench extending direction.

The decay region157extends to the inside of the collector region22beyond the boundary62between the collector region22and the cathode region82in the trench array direction, and extends from the main region156in the direction parallel to the front surface21of the semiconductor substrate10to be terminated inside the collector region22in the trench extending direction.

FIG.14Cis a top view showing a modified example of the semiconductor device100. The present example differs from the top view of the semiconductor device100shown inFIG.12Cin that the boundary region90includes the contact region15.

The main region156is terminated without extending to the boundary62between the collector region22and the cathode region82in the trench array direction, but extends to the inside of the collector region22beyond the boundary62between the collector region22and the cathode region82in the trench extending direction.

The decay region157extends from the main region156to the boundary62between the collector region22and the cathode region82to be terminated at the boundary62in the trench array direction, but extends from the main region156in the direction parallel to the front surface21of the semiconductor substrate10to be terminated inside the collector region22in the trench extending direction.

FIG.14Dis a top view showing a modified example of the semiconductor device100. The present example differs from the top view of the semiconductor device100shown inFIG.12Din that the boundary region90includes the contact region15.

The main region156is terminated without extending to the boundary62between the collector region22and the cathode region82in the trench array direction, but extends to the inside of the collector region22beyond the boundary62between the collector region22and the cathode region82in the trench extending direction.

The decay region157is terminated without extending to the boundary62between the collector region22and the cathode region82in the trench array direction, and extends from the main region156in the direction parallel to the front surface21of the semiconductor substrate10to be terminated inside the collector region22in the trench extending direction.

In this manner, in the semiconductor device100, the main region156and the decay region157can be arranged in various forms as disclosed in the examples shown inFIGS.11A to14D. The lifetime control portion150disclosed in the examples shown inFIGS.11A to14Dmay be the front surface side lifetime control region151, may be the back surface side lifetime control region152, or may be both of the front surface side lifetime control region151and the back surface side lifetime control region152. When the lifetime control portion150is the front surface side lifetime control region151, the back surface side lifetime control region152may be provided across the entire surface of the semiconductor substrate10, or may be omitted.

While the present invention has been described with the embodiments, the technical scope of the present invention is not limited to the above-described embodiments. It is apparent to persons skilled in the art that various alterations and improvements can be added to the above-described embodiments. It is also apparent from the description of the claims that the embodiments to which such alterations or improvements are made can be included in the technical scope of the present invention.

EXPLANATION OF REFERENCES