Display panel and driving method thereof

A display panel includes a plurality of scanning lines, a plurality of conductive lines, a plurality of data lines, a first pixel, a second pixel, a third pixel and a fourth pixel. The data lines and the conductive lines are parallel. Each of the conductive lines is electrically coupled to one of the scanning lines, so as to transmit at least one gate pulse. The first pixel and the second pixel are located between a first data line and a first conductive line. The first pixel is electrically coupled to the first data line and a first scanning line. The second pixel is electrically coupled to the first pixel and a second scanning line. The third pixel and the fourth pixel are located between the first data line and a second conductive line. The third pixel is electrically coupled to the first data line and a third scanning line. The fourth pixel is electrically coupled to the third pixel and a fourth scanning line.

BACKGROUND

Technical Field

The present invention relates to a display panel, and in particular, to a display panel and a driving method thereof.

Related Art

Liquid crystal display (LCD) apparatus has features such as thin shape, low power consumption, and no radiation pollution, and therefore is widely applied to electronic products such as computer screen, mobile phone, personal digital assistant (PDA), and flat screen television.

In pixel array structures of current LCD panels, there is one type of pixel array structures that is called half source driving (HSD) architecture. The HSD architecture can reduce the number of source lines by a half, so as to achieve an objective of reducing the number of source drivers by a half. Therefore, costs of panel modules can be substantially reduced. Besides, there is a pixel array structure called one third source driving (OTSD) architecture, which reduces the number of source lines to one third of source lines of original architecture, so as to save more production costs.

SUMMARY

Different from architecture of a conventional display panel, an objective of the present invention is to provide a display panel, comprising: a plurality of scanning lines, a plurality of conductive lines, a plurality of data lines, a first pixel, a second pixel, a third pixel, and a fourth pixel. The plurality of scanning lines is located along a first direction. The plurality of conductive lines is located along a second direction. The data lines and the conductive lines are parallel. Each of the conductive lines is configured to electrically couple to one of the scanning lines, so as to transmit at least one gate pulse. The first pixel is located between a first data line in the data lines and a first conductive line in the conductive lines, and is configured to electrically couple to the first data line and a first scanning line in the scanning lines. The second pixel is located between the first data line and the first conductive line, is configured to electrically couple to the first pixel, and electrically couple to a second scanning line in the scanning lines. The third pixel is located between the first data line and a second conductive line, and is configured to electrically couple to the first data line and a third scanning line in the scanning lines, wherein the first conductive line W1and the second conductive line W2are two adjacent conductive lines and are located on different sides of the first data line respectively. The fourth pixel is located between the first data line and the second conductive line, is configured to electrically couple to the third pixel, and electrically couple to a fourth scanning line in the scanning lines. An objective of the present invention is to provide a driving method of a display panel. The driving method of a display panel is provided, the display panel comprises a plurality of scanning lines, a plurality of conductive lines, a plurality of data lines, a first pixel, a second pixel, a third pixel, and a fourth pixel, wherein the scanning lines are located along a first direction, the conductive lines are located along a second direction, the data lines are substantially parallel to the conductive lines, each of the conductive lines is configured to electrically couple to one of the scanning lines, so as to transmit at least one gate pulse, the first pixel is configured to electrically couple to a first scanning line, the second pixel is configured to electrically couple to a second scanning line, the third pixel is configured to electrically couple to a third scanning line, and the fourth pixel is configured to electrically couple to a fourth scanning line, and the driving method comprises: transmitting data to the first pixel through a first data line in the data lines, and transmitting the data to the second pixel through the first pixel, wherein the first pixel and the second pixel are arranged between the first data line and a first conductive line in the conductive lines; and transmitting data to the third pixel through the first data line, and transmitting the data to the fourth pixel through the third pixel, wherein the third pixel and the fourth pixel are arranged between the first data line and a second conductive line, the first conductive line and the second conductive line are two adjacent conductive lines, the first conductive line and the second conductive line are located on different sides of the first data line respectively, and each of the first scanning line, the second scanning line, the third scanning line, and the fourth scanning line receives a first gate pulse and a second gate pulse through a corresponding conductive line.

The display panel in the present invention uses a pixel array structure with quarter source driving (QSD) architecture, so as to charge four pixels by means of one data line. With this architecture, the number of source lines is reduced to a quarter of the number of source lines of original architecture, thereby saving production costs. In addition, a gate driving circuit and a source driving circuit are located on a same side, or a gate driving circuit and a source driving circuit are located on opposite sides of a pixel array, which facilitates application of a narrow bezel technology to a display panel. Further, the display panel in the present invention uses a pixel array structure with QSD architecture, four pixels are located between every two conductive lines, and only one data line is located between two adjacent conductive lines. In this way, wiring of conductive lines and data lines causes no overlapping and interleaving, that is, there is no need to wire the conductive lines and the data lines in different circuit layers, which saves more production costs. Besides, a decrease in wires also achieves a superior aperture ratio.

DETAILED DESCRIPTION

FIG. 1shows a display panel100according to an embodiment of the present invention, including: a plurality of scanning lines, a plurality of conductive lines, a plurality of data lines, and a plurality of pixels. The plurality of scanning lines is located along a first direction, the plurality of conductive lines is located along a second direction, and the data lines are substantially parallel to the conductive lines. In the embodiments of the present invention, a gate driving circuit and a source driving circuit are located on a same side, or a gate driving circuit and a source driving circuit are located on two opposite sides of a pixel array, so that each conductive line is electrically coupled to one of the scanning lines, so as to transmit a gate pulse to the scanning line.

In the embodiments of the present invention, description is made by using a first conductive line W1, a second conductive line W2, a first data line D1, a first scanning line21, a second scanning line22, a third scanning line23, a fourth scanning line24, a first pixel11, a second pixel12, a third pixel13, and a fourth pixel14as examples, so that arrangements of the plurality of scanning lines, the plurality of conductive lines, the plurality of data lines, and a plurality of pixel array structures of the display panel in the present invention can be known. The first pixel11is located between the first data line D1in the data lines and the first conductive line W1in the conductive lines, and is configured to electrically couple to the first data line D1and the first scanning line21in the scanning lines. A control terminal of the first pixel11is coupled to the first scanning line21, a first terminal is coupled to the first data line D1, and a second terminal is coupled to a pixel capacitor. The second pixel12is located between the first data line D1and the first conductive line W1. The second pixel12is electrically coupled to the first pixel11and is electrically coupled to the second scanning line22in the scanning lines. A control terminal of the second pixel12is coupled to the second scanning line22, a first terminal is coupled to a second terminal of the first pixel11, and a second terminal is coupled to a pixel capacitor. The third pixel13is located between the first data line D1and the second conductive line W2in the conductive lines. The third pixel13is electrically coupled to the first data line D1and the third scanning line23in the scanning lines. A control terminal of the third pixel13is coupled to the third scanning line23, a first terminal is coupled to the first data line D1, and a second terminal is coupled to a pixel capacitor. The fourth pixel14is located between the first data line D1and the second conductive line W2. The fourth pixel14is electrically coupled to the third pixel13and is electrically coupled to the fourth scanning line24in the scanning lines. Besides, the first pixel11and the second pixel12are located at different pixel rows, the third pixel13and the fourth pixel14are located at different pixel rows, the first conductive line W1and the second conductive line W2are two adjacent conductive lines in the conductive lines, and the first conductive line W1and the second conductive line W2are located on different sides of the first data line D1respectively.

FIG. 2shows a signal timing diagram of the display panel according toFIG. 1. Refer toFIG. 1andFIG. 2together, in the display panel100according to the first embodiment, the driving method of the display panel is described by using scanning lines G3-G6as examples, wherein the scanning line G5is used as the first scanning line21, the scanning line G3is used as the second scanning line22, the scanning line G6is used as the third scanning line23, and the scanning line G4is used as the fourth scanning line24. Each of the scanning lines G3-G6receives a first gate pulse P1and a second gate pulse P2through a corresponding conductive line. In the first embodiment, when one of the first gate pulses P1and the second gate pulses P2of the first scanning line21and the second scanning line22is at an enable level, the first gate pulses P1and the second gate pulses P2of the third scanning line23and the fourth scanning line24are disabled, and when one of the first gate pulses P1and the second gate pulses P2of the third scanning line23and the fourth scanning line24is at an enable level, the first gate pulses P1and the second gate pulses P2of the first scanning line21and the second scanning line22are disabled. Enable periods of the first gate pulses P1are less than enable periods of the second gate pulses P2, each of the first gate pulses P1is earlier than the corresponding second gate pulse P2, the first gate pulse P1of the scanning line G5and the second gate pulse P2of the scanning line G3are synchronously switched to enable levels, and the first gate pulse P1of the scanning line G6and the second gate pulse P2of the scanning line G4are synchronously switched to enable levels.

In a period that the first gate pulse P1of the scanning line G5and the second gate pulse P2of the scanning line G3are synchronously switched to enable levels, the first pixel11and the second pixel12are turned on, the first data line D1transmits data to the first pixel11, and transmits the data to the second pixel12through the first pixel11, so as to charge the second pixel12. Subsequently, the first gate pulse P1of the scanning line G5is disabled, the first data line D1cannot charge the second pixel12through the first pixel11, and therefore, a voltage of the second pixel12is fixed. At this time, the second gate pulse P2of the scanning line G3is still enabled, so as to keep charging the pixel31until the second gate pulse P2of the scanning line G3is disabled. The second pixel12and the third pixel31are turned off after the second gate pulse P2of the scanning line G3is disabled, and therefore, the voltages of the second pixel12and the pixel31do not change.

After the second gate pulse P2of the scanning line G3is disabled, the first gate pulse P1of the scanning line G6and the second gate pulse P2of the scanning line G4are synchronously enabled, in a period that the first gate pulse P1of the scanning line G6and the second gate pulse P2of the scanning line G4are switched to enable levels, the third pixel13and the fourth pixel14are turned on, the first data line D1transmits data to the third pixel13, and transmits data to the fourth pixel14through the third pixel13, so as to charge the fourth pixel14. Subsequently, the first gate pulse P1of the scanning line G6is disabled, the first data line D1cannot charge the fourth pixel14through the third pixel13, and therefore, a voltage of the fourth pixel14is fixed. At this time, the second gate pulse P2of the scanning line G4is still enabled, so as to keep charging the pixel32until the second gate pulse P2of the scanning line G4is disabled. The fourth pixel14and the pixel32that are turned on through the scanning line G4are turned off after the second gate pulse P2of the scanning line G4is disabled, and therefore, the voltages of the fourth pixel14and the pixel32do not change.

By means of the foregoing description of the driving method of the display panel100according to the first embodiment, it can be known that the first data line D1charges the second pixel12, the fourth pixel14, the pixel31, and the pixel32. Besides, after the second gate pulse P2of the scanning line G4is disabled, the first gate pulse P1(not shown in the figures) of the scanning line G7and the second gate pulse P2of the scanning line G5are synchronously enabled, and the first data line D1charges the first pixel11, the third pixel13, the pixel33, and the pixel34through four scanning lines G5-G8.

FIG. 3shows a display panel300according to a second embodiment, the display panel300differs from the display panel100in that, the scanning line G5is used as the first scanning line21, the scanning line G3is used as the second scanning line22, the scanning line G4is used as the third scanning line23, and the scanning line G6is used as the fourth scanning line24.FIG. 4shows a signal timing diagram of the display panel300according toFIG. 3. In the second embodiment, enable periods of first gate pulses P1are less than enable periods of second gate pulses P2, each of the first gate pulses P1of the first scanning line21and the second scanning line22is earlier than the corresponding second gate pulse P2, each of the second gate pulses P2of the third scanning line23and the fourth scanning line24is earlier than the corresponding first gate pulse P1, the first gate pulse P1of the first scanning line21and the second gate pulse P2of the second scanning line22are synchronously switched to enable levels, and the first gate pulse P1of the third scanning line23and the second gate pulse P2of the fourth scanning line24are synchronously switched to enable levels.

Subsequently, referring toFIG. 3andFIG. 4together, in a period that the first gate pulse P1of the scanning line G2and the second gate pulse P2of the scanning line G4are synchronously switched to the enable levels, the pixel35and the pixel36are turned on, the first data line D1transmits data to the pixel35, and transmits the data to the pixel36through the pixel35, so as to charge the pixel36. Subsequently, the first gate pulse P1of the scanning line G2is disabled, and the first data line D1cannot charge the pixel36through the pixel35. The pixel35that is turned on through the scanning line G2is turned off after the first gate pulse P1is disabled, and therefore, the voltages of the pixel35and the pixel36that is charged through the pixel35do not change. After the second gate pulse P2of the scanning line G4is disabled, in the period that the first gate pulse P1of the scanning line G5and the second gate pulse P2of the scanning line G3are synchronously switched to the enable levels, the first pixel11and the second pixel12are turned on, the first data line D1transmits data to the first pixel11, and transmits the data to the second pixel12through the first pixel11, so as to charge the second pixel12. Subsequently, the first gate pulse P1of the scanning line G5is disabled, the first data line D1cannot charge the second pixel12through the first pixel11, and therefore, a voltage of the second pixel12is fixed. At this time, the second gate pulse P2of the scanning line G3is still enabled, so as to keep charging the pixel37until the second gate pulse P2of the scanning line G3is disabled. The second pixel12and the pixel37that are turned on through the scanning line G3are turned off after the second gate pulse P2of the scanning line G3is disabled, and therefore, the voltages of the second pixel12and the pixel37are fixed.

After the second gate pulse P2of the scanning line G3is disabled, the first gate pulse P1of the scanning line G4and the second gate pulse P2of the scanning line G6are synchronously enabled, in a period that the first gate pulse P1of the scanning line G4and the second gate pulse P2of the scanning line G6are switched to the enable levels, the third pixel13and the fourth pixel14are turned on, the first data line D1transmits data to the third pixel13, and transmits data to the fourth pixel14through the third pixel13, so as to charge the fourth pixel14. Subsequently, the first gate pulse P1of the scanning line G4is disabled, and the first data line D1cannot charge the fourth pixel14through the third pixel13. The third pixel13that is turned on through the scanning line G4is turned off after the first gate pulse P1of the scanning line G4is disabled, and therefore, the voltages of the third pixel13and the fourth pixel14are fixed.

By means of the foregoing description of the driving method of the display panel300according to the second embodiment, it can be known how to use the first data line D1to charge the second pixel12, the third pixel13, the pixel36, and the pixel37, and it can be known that after the second gate pulse P2of the scanning line G6is disabled, the first gate pulse P1(not shown in the figures) of the scanning line G7and the second gate pulse P2of the scanning line G5are synchronously enabled. Therefore, the first data line D1further charges four pixels of the next row by means of the foregoing manner.

FIG. 5shows a display panel500according to a third embodiment, the display panel500differs from the display panel100and the display panel300in that, the scanning line G3is used as the first scanning line21, the scanning line G5is used as the second scanning line22, the scanning line G4is used as the third scanning line23, and the scanning line G6is used as the fourth scanning line24.FIG. 6shows a signal timing diagram of the display panel500according toFIG. 5. In the third embodiment, enable periods of first gate pulses P1are greater than enable periods of second gate pulses P2, each of the first gate pulses P1is earlier than the corresponding second gate pulse P2, the second gate pulse P2of the first scanning line21and the first gate pulse P1of the second scanning line22are synchronously switched to enable levels, and the second gate pulse P2of the third scanning line23and the first gate pulse P1of the fourth scanning line24are synchronously switched to enable levels.

Subsequently, referring toFIG. 5andFIG. 6together, in a period that the second gate pulse P2of the scanning line G3and the first gate pulse P1of the scanning line G5are synchronously switched to enable levels, the first pixel11and the second pixel12are turned on, the first data line D1transmits data to the first pixel11, and transmits the data to the second pixel12through the first pixel11, so as to charge the second pixel12. Subsequently, the second gate pulse P2of the scanning line G3is disabled, the first data line D1cannot charge the second pixel12through the first pixel11. In addition, the first pixel11is turned off after the second gate pulse P2of the scanning line G3is disabled, and therefore, the voltages of the first pixel11and the second pixel12do not change.

After the first gate pulse P1of the scanning line G5is disabled, in a period that the second gate pulse P2of the scanning line G4and the first gate pulse P1of the scanning line G6are synchronously switched to the enable levels, the third pixel13and the fourth pixel14are turned on, the first data line D1transmits data to the third pixel13, and transmits the data to the fourth pixel14through the third pixel13, so as to charge the fourth pixel14. Subsequently, the second gate pulse P2of the scanning line G4is disabled, the first data line D1cannot charge the fourth pixel14through the third pixel13. In addition, the third pixel13is turned off after the second gate pulse P2of the scanning line G4is disabled, and therefore, the voltages of the third pixel13and the fourth pixel14do not change.

By means of the description of the driving method of the display panel500according to the third embodiment that is made by using the scanning lines G3-G6, it can be known how to use the first data line D1to charge the first pixel11, the second pixel12, the third pixel13, and the fourth pixel14. Therefore, it can be known that after the first gate pulse P1of the scanning line G6is disabled, the first gate pulse P1(not shown in the figures) of the scanning line G7and the second gate pulse P2of the scanning line G5are synchronously enabled, and the first data line D1can charge another four pixels through four scanning lines by means of the foregoing manner.

FIG. 7shows a display panel700according to a fourth embodiment, the display panel700differs from the display panel100, the display panel300, and the display panel500in that, the scanning line G3is used as the first scanning line21, the scanning line G5is used as the second scanning line22, the scanning line G6is used as the third scanning line23, and the scanning line G4is used as the fourth scanning line24.FIG. 8shows a signal timing diagram of the display panel700according toFIG. 7. In the fourth embodiment, enable periods of first gate pulses P1are less than enable periods of second gate pulses P2, each of the second gate pulses P2of the first scanning line21and the second scanning line22is earlier than the corresponding first gate pulse P1, each of the first gate pulses P1of the third scanning line23and the fourth scanning line24is earlier than the corresponding second gate pulse P2, the first gate pulse P1of the first scanning line21and the second gate pulse P2of the second scanning line22are synchronously switched to enable levels, and the first gate pulse P1of the third scanning line23and the second gate pulse P2of the fourth scanning line24are synchronously switched to enable levels.

In a period that the first gate pulse P1of the scanning line G3and the second gate pulse P2of the scanning line G5are synchronously switched to enable levels, the first pixel11and the second pixel12are turned on, the first data line D1transmits data to the first pixel11, and transmits the data to the second pixel12through the first pixel11, so as to charge the second pixel12. Subsequently, the first gate pulse P1of the scanning line G3is disabled, the first data line D1cannot charge the second pixel12through the first pixel11. In addition, the first pixel11is turned off after the first gate pulse P1of the scanning line G3is disabled, and therefore, the voltages of the first pixel11and the second pixel12do not change.

After the second gate pulse P2of the scanning line G5is disabled, the second gate pulse P2of the scanning line G4and the first gate pulse P1of the scanning line G6are synchronously enabled, in a period that the second gate pulse P2of the scanning line G4and the first gate pulse P1of the scanning line G6are of the enable voltages, the third pixel13and the fourth pixel14are turned on, the first data line D1transmits data to the third pixel13, and transmits the data to the fourth pixel14through the third pixel13, so as to charge the fourth pixel14. Subsequently, the first gate pulse P1of the scanning line G6is disabled, the first data line D1cannot charge the fourth pixel14through the third pixel13, and therefore, a voltage of the fourth pixel14is fixed. At this time, the second gate pulse P2of the scanning line G4is still enabled, so as to keep charging the pixel38until the second gate pulse P2of the scanning line G4is disabled. The fourth pixel14and the pixel38that are turned on through the scanning line G4are turned off after the second gate pulse P2of the scanning line G4is disabled, and therefore, the voltages of the fourth pixel14and the pixel38do not change.

By means of the description of the driving method of the display panel700according to the fourth embodiment that is made by using the scanning lines G3-G6, it can be known how to use the first data line D1to charge the first pixel11, the second pixel12, the fourth pixel14, and the pixel38. Therefore, it can be known that after the second gate pulse P2of the scanning line G4is disabled, the second gate pulse P2(not shown in the figures) of the scanning line G7and the first gate pulse P1of the scanning line G5are synchronously enabled, and the first data line D1can charge another four pixels through four scanning lines by means of the foregoing manner.

The display panel in the present invention uses a pixel array structure with QSD architecture, so as to charge four pixels by means of one data line. With this architecture, the number of source lines is reduced to a quarter of the number of source lines of original architecture, thereby saving production costs. In addition, a gate driving circuit and a source driving circuit are located on a same side, or a gate driving circuit and a source driving circuit are located on opposite sides of a pixel array, which facilitates application of a narrow bezel technology to a display panel. Further, the display panel in the present invention uses a pixel array structure with QSD architecture, four pixels are located between every two conductive lines, and only one data line is located between two adjacent conductive lines. In this way, wiring of conductive lines and data lines causes no overlapping and interleaving, that is, there is no need to wire the conductive lines and the data lines in different circuit layers, which saves more production costs. Besides, a decrease in wires also achieves a superior aperture ratio.

Although the present invention is described above by means of the preferred embodiments, the above description is not intended to limit the present invention. A person skilled in the art can make variations and modifications without departing from the spirit and scope of the present invention, and therefore, the protection scope of the present invention is as defined in the appended claims.