Package structures and methods of forming the same

Package structures and methods of forming the same are disclosed. A package structure includes at least one first integrated circuit, at least one second integrated circuit, at least one dummy substrate and an encapsulant. The at least one second integrated circuit is disposed on the at least one dummy substrate in a first direction, and the at least one first integrated circuit and the at least one dummy substrate are separated by a distance in a second direction perpendicular to the first direction. The encapsulant is aside the at least one first integrated circuit, the at least one second integrated circuit and the at least one dummy substrate.

BACKGROUND

In recent years, the semiconductor industry has experienced rapid growth due to continuous improvement in integration density of various electronic components, e.g., transistors, diodes, resistors, capacitors, etc. For the most part, this improvement in integration density has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area.

These smaller electronic components also require smaller packages that occupy less area than previous packages. Examples of the type of packages for semiconductors include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chips (FC), three-dimensional integrated circuits (3DICs), wafer level packages (WLPs), and package on package (PoP) devices. Some 3DICs are prepared by placing chips over chips on a semiconductor wafer level. The 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked chips. However, there are many challenges related to 3DICs.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below for the purposes of conveying the present disclosure in a simplified manner. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the same reference numerals and/or letters may be used to refer to the same or similar parts in the various examples the present disclosure. The repeated use of the reference numerals is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

FIG. 1illustrates a flow chart of a method of forming a package structure in accordance with some embodiments.FIG. 2AtoFIG. 2Iillustrate cross-sectional views of a method of forming a package structure in accordance with some embodiments.

In some embodiments, the carrier100has a package area101including an integrated circuit area102and a periphery area104aside the integrated circuit area102. In some embodiments, the periphery area104surrounds the integrated circuit area102. In some embodiments, the carrier100may have a glue layer (not shown) thereon for de-bond usage. In some embodiments, the carrier100may be a glass carrier, and the glue layer may be a Ultra-Violet (UV) glue layer or a Light-to-Heat Conversion (LTHC) glue layer. In some embodiments, the glue layer is even protected by forming a polymer layer thereon. The polymer material may be a photo-sensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a combination thereof and/or the like.

Referring toFIG. 1andFIG. 2B, at step20, at least one dummy substrate DS is placed on the carrier100.

In some embodiments, the dummy substrate DS includes a group IV element or a group III-V semiconductor compound, such as Si, Ge, SiGe, GaAs, InAs, InGaAs, or the like. In some embodiments, the dummy substrate DS includes silicon substrate or a substrate formed of other suitable semiconductor materials. In some embodiments, the dummy substrate DS is provided with a glue layer110. In some embodiments, the glue layer110is formed of an adhesive such as a die attach film (DAF), epoxy, silver paste, or the like, although other types of adhesives may be used.

Referring toFIG. 1andFIG. 2C, at step30, at least one first integrated circuit C1is placed on the carrier100in a manner such that a bottom b1of the first integrated circuit C1and a bottom b2of the dummy substrate DS are arranged to together form a rotationally symmetrical shape sp (shown inFIG. 3). In some embodiments, in a first direction D1, the first integrated circuit C1is picked and placed on the carrier100. In some embodiments, the first integrated circuit C1is provided with a glue layer112. In some embodiments, the first integrated circuit C1and the dummy substrate DS are separated by a distance d in a second direction D2perpendicular to the first direction D1. In some embodiments, the step of placing the first integrated circuit C1is after the dummy substrate DS is placed on the carrier100. In alternative embodiments, the step of placing the first integrated circuit C1is before the dummy substrate DS is placed on the carrier100.

Referring toFIG. 1andFIG. 2C, at step40, at least one second integrated circuit C2is placed on the dummy substrate DS. In some embodiments, in the first direction D1, the second integrated circuit C2is picked and placed on the dummy substrate DS. In some embodiments, the second integrated circuit C2is provided with a glue layer114. In some embodiments, the step of placing the second integrated circuit C2is after the first integrated circuit C1is placed on the carrier100. In alternative embodiments, the step of placing the second integrated circuit C2is before the first integrated circuit C1is placed on the carrier100.

In some embodiments, each of the first and second integrated circuits C1, C2is, for example, a die, and includes an interconnection122, a pad124and a connector126. The interconnection122is formed over a substrate120. In some embodiments, the glue layer114is disposed between the substrate120of the second integrated circuit C2and the dummy substrate DS. The substrate120includes, for example but not limited to, bulk silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The pad124is formed over and electrically connected to the interconnection122. In some embodiments, each of the first and second integrated circuits C1, C2includes an active surface (not shown), the pad124is distributed on the active surface. The connector126is formed over and electrically connected to the pad124. In some embodiments, the connector126is formed as the top portion of each of the first and second integrated circuits C1, C2. The connector126protrudes from the remaining portion or lower portion of each of the first and second integrated circuits C1, C2. The connector126can be electrical connectors, dummy connectors or both. The connector126include solder bumps, gold bumps, copper posts or the like. In some embodiments, the connector126is a copper bump. In some embodiments, the pad124is partially exposed by a passivation layer128, and the connector126is encapsulated by a protection layer130.

In some embodiments, a coefficient of thermal expansion (CTE) of the dummy substrate DS is similar to a CTE of the substrate120of at least one of the first integrated circuit C1disposed adjacent thereto and the second integrated circuit C2disposed thereon. In some embodiments, the CTE of the dummy substrate DS is, for example, substantially equal to the CTE of the substrate120of at least one of the first and second integrated circuits C1, C2. In some embodiments, a material of the dummy substrate DS may be the same with the substrate120of at least one of the first and second integrated circuits C1, C2. In alternative embodiments, a material of the dummy substrate DS may be different from the substrate120of at least one of the first and second integrated circuits C1, C2. In alternative embodiments, the dummy substrate DS may have a CTE similar to or substantially equal to an effective CTE of at least one of the first and second integrated circuits C1, C2.

In some embodiments, a thickness T1of the first integrated circuit C1is substantially equal to a total thickness of a thickness T of the dummy substrate DS, a thickness T2of the second integrated circuit C2disposed thereon and a thickness T3of the glue layer114, that is, T1=T2+T+T3. In some embodiments, before placing the first and second integrated circuits C1, C2, a grinding process is performed on at least one of the first and second integrated circuits C1, C2. In alternative embodiments, each of the first and second integrated circuits C1, C2is a package having a die and an encapsulant aside the die and having a determined thickness.

FIG. 3illustrates a simplified view of a package structure ofFIG. 2Cin accordance with some embodiments. Referring toFIG. 3, the bottom of the first integrated circuit C1and the bottom of the dummy substrate DS are arranged to together form the rotationally symmetrical shape sp. It is note that the term “the rotationally symmetrical shape” means a shape substantially having rotational symmetry and a shape substantially composed of a shape of the bottom of the first integrated circuit C1, a shape of the bottom of the dummy substrate DS and a shape of a gap therebetween. In some embodiments, the rotationally symmetrical shape sp is substantially a rectangle. In alternative embodiments, the rotationally symmetrical shape sp may be a square or a regular polygon. In some embodiments, the package area101is substantially a rotationally symmetrical shape such as a rectangle. In some embodiments, a center of the rotationally symmetrical shape sp forming by the bottom of the first integrated circuit C1and the bottom of the dummy substrate DS is overlapped with a center of the package area101. Accordingly, distances between the rotationally symmetrical shape sp and opposite borders101a-101dof the package area101are respectively the same. In detail, the package area101has borders101a-101d, the border101ais opposite to the border101b, and the border101cis opposite to the border101d. In some embodiments, a distance d1between the border101aand the rotationally symmetrical shape sp is substantially equal to a distance d1′ between the opposite border101band the rotationally symmetrical shape sp. In some embodiments, a distance d2′ between the border101cand the rotationally symmetrical shape sp is substantially equal to a distance d2between the opposite border101dand the rotationally symmetrical shape sp. In alternative embodiments, for better wafer and package warpage control, the distances d1, d1′, d2, d2′ between the borders101a-101dand the rotationally symmetrical shape sp are the same, that is, d1=d1′=d2=d2′.

In some embodiments, in a third direction D3perpendicular to the second direction D2, a width W1of the first integrated circuit C1is, for example, larger than a width W2of the second integrated circuit C2. In some embodiments, in the third direction D3, a width W of the dummy substrate DS is, for example, substantially equal to the width W1of the first integrated circuit C1.

In some embodiments, the first integrated circuit C1includes a first side s1, a second side s2adjacent to the first side s1, and a third side s3opposite to the second side s2, wherein the first side s1has the width W1. The dummy substrate DS includes a first side s1, a second side s2adjacent to the first side s1, and a third side s3opposite to the second side s2, wherein the first side s1has the width W. In some embodiments, the first integrated circuit C1and the dummy substrate DS are arranged together form the rotationally symmetrical shape sp by aligning the second side s2of the first integrated circuit C1and the second side s2of the dummy substrate DS in the second direction D2with the distance d therebetween. Accordingly, a distance d1between the border101aof the package area101and the second side s2of the first integrated circuit C1is substantially equal to a distance d1between the border101aof the package area101and the second side s2of the dummy substrate DS. In some embodiments, the distance d1′ between the border101bof the package area101and the third side s3of the first integrated circuit C1is substantially equal to a distance d1′ between the border101bof the package area101and the third side s3of the first integrated circuit C1. In some embodiments, the distance d1is substantially equal to the distance d1′. In some embodiments, a distance d2between the border101dof the package area101and the first side s1of the first integrated circuit C1is substantially equal to a distance d2′ between the border101cof the package area101and the first side s1of the dummy substrate DS.

Referring toFIG. 1andFIG. 2D, at step50, an encapsulant140is formed in the integrated circuit area102and the periphery area104to encapsulate the first integrated circuit C1, the second integrated circuit C2and the dummy substrate DS. A material of the encapsulant140may include molding compound materials including resin and filler, a photo-sensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), any combination thereof and/or the like. In alternative embodiments, the insulating material may be formed of a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), any combination thereof and/or the like. In some embodiments, the CTE of the dummy substrate DS is significantly lower than a CTE of the encapsulant140.

In some embodiments, a forming method of the encapsulant140includes the following steps. An insulating material is formed on the carrier100across the integrated circuit area102and the periphery area104, to cover the first and second integrated circuits C1, C2and the dummy substrate DS. In some embodiments, the insulating material is a molding compound formed by molding process. Then, the insulating material is grinded until the top surfaces of the connectors126and the top surfaces of the protection layers130are exposed. After the insulating material is grinded, an encapsulant140is formed. In some embodiments, the connectors126and the protection layers130of the first and second integrated circuits C1, C2are not revealed and are well protected by the insulating material during the formation of the insulating material. As shown inFIG. 2D, it is noted that the top surface of the encapsulant140, the top surfaces of the connectors126, and the top surfaces of the protection layers130are substantially coplanar. In alternative embodiments, the protective layer130may cover the top surfaces of the connectors126, and the portions of the protection layer130are grinded during the grinding process of the insulating material.

Referring toFIG. 2E, a dielectric layer150is formed on the top surfaces of the first and second integrated circuits C1, C2and the top surface of the encapsulant140. The dielectric layer150includes at least one contact opening152. In some embodiments, a plurality of contact opening152for exposing the top surfaces of the connectors126are formed in the dielectric layer150. It is noted that the number of the contact openings152is corresponding to the number of the connectors126. In some embodiments, the dielectric layer150is a polybenzoxazole (PBO) layer, for example.

Then, a plurality of conductive through vias160is formed on the dielectric layer150to electrically connect to the connectors126through the contact openings152. In some embodiments, the plurality of conductive through vias160is formed by photolithography, plating, and photoresist stripping process. For example, the conductive through vias160include copper posts.

Referring toFIG. 1andFIG. 2F, at step60, at least one third integrated circuit C3is placed over the first and second integrated circuits C1, C2. In some embodiments, the third integrated circuit C3is picked and placed on the dielectric layer150. In some embodiments, the third integrated circuit C3is provided with a glue layer170. Then, an encapsulant180is formed over the dielectric layer150to cover the third integrated circuit C3and the conductive through vias160. In some embodiments, the third integrated circuit C3is a die having a structure similar to the first and second integrated circuits C1, C2. In alternative embodiments, the third integrated circuit C3is a package having a die and an encapsulant aside the die. In some embodiments, the method of forming the encapsulant180is similar to the method of forming the encapsulant140, so the details are not iterated herein. As shown inFIG. 2F, it is noted that the top surfaces of the conductive through vias160, the top surface of the encapsulant180, and the top surfaces of the connector126and the protection layer130of the third integrated circuit C3are substantially coplanar.

As shown inFIG. 2EandFIG. 2F, the third integrated circuit C3is picked and placed on the dielectric layer150after the formation of the conductive through vias160. However, the disclosure is not limited thereto. In alternative embodiments, the third integrated circuit C3is picked and placed on the dielectric layer150before the formation of the conductive through vias160. In some embodiments, the first, second and third integrated circuits C1, C2, C3may be memory chips, such as a DRAM, SRAM, NVRAM, or logic circuits. In this embodiment, the first and second integrated circuits C1, C2are memory chips, and the third integrated circuit C3is a logic circuit.

Referring toFIG. 2G, after the encapsulant180is formed, a redistribution circuit structure RDL electrically connected to the connector126of the third integrated circuit C3is formed on the top surfaces of the conductive through vias160, the top surface of the encapsulant180, the top surface of the connectors126, and the top surface of the protection layer130. The redistribution circuit structure RDL is fabricated to electrically connect with at least one connector underneath. Here, the afore-said connector(s) may be the connector126of the third integrated circuit C3and/or the conductive through vias160in the encapsulant180. The fabrication of the redistribution circuit structure RDL includes the following steps. First, a dielectric layer200-1is formed on the encapsulant180and the protection layer130, wherein openings200in the dielectric layer200-1expose the connector126and the conductive through vias160. Then, patterned conductive layers210-1are formed in the openings200of the dielectric layer200-1to electrically connect to the connector126and the conductive through vias160, respectively. In some embodiments, a dielectric layer200-2is formed on the dielectric layer200-1, wherein openings200in the dielectric layer200-2expose the patterned conductive layers210-1. Thereafter, patterned conductive layers210-2are formed in the openings200of the dielectric layer200-2to electrically connect to the patterned conductive layers210-1. In some embodiments, a dielectric layer200-3is formed on the dielectric layer200-2, and an opening200in the dielectric layer200-3exposes the patterned conductive layer210-2. In other words, after the dielectric layer200-1and the patterned conductive layer210-1are formed, steps of forming the dielectric layer and the patterned conductive layers can be repeated at least one time so as to fabricate the redistribution circuit structure RDL over the third integrated circuit C3and the encapsulant180. The redistribution circuit structure RDL includes a plurality of dielectric layers and a plurality of patterned conductive layers stacked alternately.

As shown inFIG. 2G, in some embodiments, the topmost patterned conductive layer of the redistribution circuit structure RDL may include at least one under-ball metallurgy (UBM) pattern212for electrically connecting with conductive ball and/or at least one connection pad (not shown) for electrically connecting with at least one passive component. The number of the under-ball metallurgy pattern212and the connection pad is not limited in this disclosure.

Referring toFIG. 2H, after the redistribution circuit structure RDL is formed, a conductive ball214is placed on the under-ball metallurgy pattern212, and a plurality of passive components (not shown) are mounted on the connection pads. In some embodiments, the conductive ball214may be placed on the under-ball metallurgy pattern212by ball placement process, and the passive components may be mounted on the connection pads through reflow process.

In some embodiments, the third integrated circuit C3, the encapsulant180, the redistribution circuit structure RDL and the conductive ball214are sequentially formed over the carrier100. However, the disclosure is not limited thereto. In alternative embodiments, a package structure including the third integrated circuit C3, the encapsulant180, the redistribution circuit structure RDL and the conductive ball214are pre-formed on another carrier, and the package structure is de-bonded from the carrier and electrically connected to a package structure ofFIG. 2D.

Referring toFIG. 2HandFIG. 2I, after the conductive ball214is formed, the carrier100is removed. In some embodiments, the formed structure is de-bonded from the glue layers (not shown) such that the formed structure is separated from the carrier100. In some embodiments, the formed structure is peeled from the carrier100and the glue layer110and the glue layer112are retained underneath the dummy substrate DS and the first integrated circuit C1respectively. In alternative embodiments, the formed structure de-bonded from the carrier100may be electrically connected to another package.

Conventionally, packaging the integrated circuits having different sizes may induce asymmetric wafer warpage and surface defects such as crystal originated pits. In some embodiments, by adding the dummy substrate and arranging the dummy substrate and the first integrated circuit to together form the rotationally symmetrical shape, the size difference between the first and second integrated circuits is compensated. Accordingly, a better wafer warpage is obtained and surface defects such as crystal originated pits are prevented.

FIG. 4illustrates a simplified top view of a package structure in accordance with alternative embodiments. Referring toFIG. 4, in some embodiments, a package structure includes a first integrated circuit C1, a plurality of second integrated circuits C2and a plurality of dummy substrates DS. In some embodiments, the first integrated circuit C1and the second integrated circuits C2have different widths from one other, wherein the second integrated circuits C2are respectively disposed over the dummy substrates DS. In some embodiments, the first integrated circuit C1and the dummy substrates DS are arranged to together form a rotationally symmetrical shape sp. In some embodiments, the rotationally symmetrical shape sp is a rectangle, for example. In some embodiments, distances d1, d1′, d2, d2′ between the rotationally symmetrical shape sp and borders101a,101b,101dand101cof a package region101are respectively constant. In some embodiments, the distance d1is substantially equal to the distance d1′, and the distance d2is substantially equal to the distance d2′. In some embodiments, one first integrated circuit C1is disposed on the carrier100. However, the number of the first integrated circuit C1is not limited in this disclosure. In alternative embodiments, a plurality of the first integrated circuits C1and at least one dummy substrates DS are arranged to together form a rotationally symmetrical shape. In alternative embodiments, for better wafer and package warpage control, the distances d1, d1′, d2, d2′ between the borders101a-101dand the rotationally symmetrical shape sp are the same, that is, d1=d1′=d2=d2′.

In some embodiments, by adding the dummy substrates and arranging the dummy substrates and the first integrated circuit to together form the rotationally symmetrical shape, the size difference between the first and second integrated circuits is compensated. Accordingly, a better wafer warpage is obtained and surface defects such as crystal originated pits are prevented.

The above embodiments illustrate examples where the first integrated circuit C1on the carrier100and the second integrated circuit C2on the dummy substrate DS have different sizes (e.g., widths). However, it should be noted that the disclosure is not limited thereto.FIG. 5Aillustrates a cross-sectional view of a package structure in accordance with alternative embodiments, andFIG. 5Billustrates a simplified top view of a package structure ofFIG. 5A. Referring toFIG. 5AandFIG. 5B, in some embodiments, a package structure includes at least one first integrated circuit C1, at least one second integrated circuit C2and at least one dummy substrate DS disposed in an integrated circuit region102. In some embodiments, the first integrated circuit C1and the second integrated circuit C2have a substantially identical width W, W1and have different thicknesses T1, T2. In some embodiments, the second integrated circuit C2having a smaller thickness T2than the first integrated circuit C1is disposed on the dummy substrate DS having a thickness T. In some embodiments, the thickness T of the dummy substrate DS is substantially equal to a thickness difference between the first and second integrated circuits C1, C2subtracting a thickness T3of the glue layer114. In some embodiments, the dummy substrate DS and the second integrated circuit C2have a substantially identical width W. In other words, a total thickness of the thickness T of the dummy substrate DS, the thickness T2of the second integrated circuit C2and the thickness T3of the glue layer114is substantially equal to the thickness T1of the first integrated circuit C1, that is, T1=T2+T+T3. Accordingly, a top surface of the second integrated circuit C2is substantially coplanar with a top surface of the first integrated circuit C1. In some embodiments, each of the first and second integrated circuits C1, C2is a package or a chip having a determined thickness and difficult to be processed by reducing thickness process such as grinding. In alternative embodiments, the first and second integrated circuits C1, C2are dies.

In some embodiments, the dummy substrate DS compensates the thickness difference between the first and second integrated circuits C1, C2, and thus subsequent processes such as placing a third integrated circuit C3thereon may be performed on a substantially planar surface.

The above embodiments illustrate examples where the connector126of the first and second integrated circuit C1, C2is directly connected to the through vias160. However, it should be noted that the disclosure is not limited thereto. In some embodiments, as shown inFIG. 6, a redistribution circuit structure RDL′ is further disposed between the connector126of the first and second integrated circuit C1, C2and the through vias160. In some embodiments, the redistribution circuit structure RDL′ includes a first dielectric layer300-1and patterned conductive layers310-1disposed therein and thereon. In some embodiments, the method of forming the redistribution circuit structure RDL′ is similar to the method of forming the redistribution circuit structure RDL, so the details are not iterated herein.

In view of the above, the present disclosure provides a package structure including at least one first integrated circuit, at least one second integrated circuit and at least one dummy substrate, wherein the second integrated circuit is disposed on the dummy substrate. In some embodiments, the first and second integrated circuits have different sizes, and the dummy substrate and the first integrated circuit are arranged to together form a rotationally symmetrical shape. Therefore, the size difference between the first and second integrated circuits is compensated by the dummy substrate. Accordingly, a better wafer warpage is obtained and surface defects such as crystal originated pits are prevented. In alternative embodiments, the first and second integrated circuits have different thickness, and a total thickness of the dummy substrate and the second integrated circuit is substantially equal to a thickness of the first integrated circuit. Accordingly, top surfaces of the first and second integrated circuits are substantially coplanar with one another since the dummy substrate compensates the thickness difference between the first and second integrated circuits, and subsequent processes may be performed on a substantially planar surface.

In accordance with some embodiments of the present disclosure, a package structure includes at least one first integrated circuit, at least one second integrated circuit, at least one dummy substrate and an encapsulant. The at least one second integrated circuit is disposed on the at least one dummy substrate in a first direction, and the at least one first integrated circuit and the at least one dummy substrate are separated by a distance in a second direction perpendicular to the first direction. The encapsulant is aside the at least one first integrated circuit, the at least one second integrated circuit and the at least one dummy substrate.

In accordance with alternative embodiments of the present disclosure, a package structure includes at least one first integrated circuit, at least one second integrated circuit, at least one dummy substrate and an encapsulant. The at least one second integrated circuit is disposed on the at least one dummy substrate, and a bottom of the at least one first integrated circuit and a bottom of the at least one dummy substrate are arranged to together form a rotationally symmetrical shape. The encapsulant is aside the at least one first integrated circuit, the at least one second integrated circuit and the at least one dummy substrate.

In accordance with yet alternative embodiments of the present disclosure, a method of forming a package structure includes at least the following steps. At least one dummy substrate is placed on a carrier. At least one first integrated circuit is placed on the carrier in a manner such that a bottom of the at least one first integrated circuit and a bottom of the at least one dummy substrate are arranged to together form a rotationally symmetrical shape. At least one second integrated circuit is placed on the at least one dummy substrate. An encapsulant is formed to encapsulate the first integrated circuit, the second integrated circuit and the dummy substrate.