Apparatus and method of page program operation for memory devices with mirror back-up of data

An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices. More particularly, the present invention relates to an apparatus and a method for page program operation for memory devices.

BACKGROUND

Electronic equipment uses memory devices, for example, flash memories, for storing data or information. In a memory system, a memory controller programs a selected flash memory device by transmitting data to a page buffer in a selected flash memory device where it is stored temporarily. Programming of the data from the page buffer into in the flash memory commences and the programming result is verified and a verify result is produced as “pass” or “fail”. Program and verify operations are performed several times for a “program time” specified period. After the program time, in the event of failure, the data is re-loaded from the memory controller to resume the page program operation in the same selected device.

A drawback is that flash memories require a long program time, for example, to verify the program status. The memory inside of the memory controller must hold the initial program data in order to recover the original program data in the event of program failure. The initial program data occupies space in the memory of the memory controller, with the result that the memory space can not be used for other purposes.

SUMMARY

According to one aspect of the present invention, there is provided an apparatus for controlling a plurality of memory devices interconnected in-series, each of the memory devices having a page buffer and memory cells. The apparatus comprises a data processor configured to execute a page program operation with a mirror back-up of data by: writing data to the page buffer of a selected memory device of the plurality of memory devices and to the page buffer of another memory device of the plurality of memory devices; instructing the selected memory device to program the data loaded in its page buffer into its memory cells; and determining whether the data is not successfully programmed into the memory cells of the selected memory device, recover the data from the page buffer of the another memory device.

For example, the data processor is configured to recover the data from the page buffer of the another memory device by: reading back the data from the page buffer of the another memory device without programming the data into the memory cells of the another memory device.

The apparatus may further comprise data storage for storing the data prior to writing the data to the page buffer of the selected memory device and to the page buffer of the another memory device.

According to another aspect of the present invention, there is provided a system comprising: a plurality of memory devices that are interconnected in-series, each memory device having a page buffer and memory cells; and an apparatus for controlling the plurality of memory devices, the apparatus comprising a data processor configured to execute a page program operation with a mirror back-up for data by: writing data to the page buffer of a selected memory device of the plurality of memory devices and to the page buffer of another memory device of the plurality of memory devices; instructing the selected memory device to program the data loaded in its page buffer into its memory cells; and if the data is not successfully programmed into the memory cells of the selected memory device, recover the data from the page buffer of the another memory device.

According to another aspect of the present invention, there is provided a method for controlling a plurality of memory devices that are interconnected in-series, each memory device having a page buffer and memory cells. The method comprises: transmitting data to the page buffer of a selected memory device of the plurality of memory devices and to the page buffer of another memory device of the plurality of memory devices; instructing the selected memory device to program the data loaded in its page buffer into its memory cells; and if the data is not successfully programmed into the memory cells of the selected memory device, recovering the data from the page buffer of the another memory device.

For example, the step of recovering the data from the page buffer of the another memory device comprises reading back the data from the page buffer of the another memory device without programming the data into the memory cells of the another memory device.

The method may further comprise storing the data prior to writing the data to the page buffer of the selected memory device and to the page buffer of the another memory device; freeing up space where the data is occupied before determining whether the data has been successfully programmed into the memory cells of the selected memory device.

According to another aspect of the present invention, there is provided a memory device for use as one of a set of memory devices connected in-series. The memory device comprises: an input connection; an output connection; an identification of a device address of the memory device; and a device controller configured to: receive messages to enter and exit a multi-address detection mode, and enter and exit the multi-address detection mode accordingly; receive a command over the input connection, the command comprising a device address; while not in the multi-address detection mode, process the command only if the device address of the command matches the device address of the device; and while in the multi-address detection mode: i) process the command if the device address of the command is the same as the device address of the device and ii) process the command if the device address of the command is the same as the device address of at least one other predetermined device.

According to another aspect of the present invention, there is provided a method in a memory device forming part of a set of memory devices connected in-series, the method comprising: maintaining a device address; receiving messages to enter and exit a multi-address detection mode; receiving a command comprising a device address; while not in the multi-address detection mode, processing the command only if the destination address matches the device address; and while in the multi-address detection mode: processing the command if the device address of the command is the same as the device address of the device; and processing the command if the device address of the command is the same as the device address of at least one other predetermined device.

DETAILED DESCRIPTION

FIG. 1shows a system according to an embodiment of the present invention. Referring toFIG. 1, a system150includes a memory controller151and a serial interconnection of a plurality (M) of memory devices154-1,154-2,154-3, . . . , and154-M that are connected in-series, M being an integer greater than one. The memory controller151and the memory devices are interconnected via links having data width n, where n is an integer greater than or equal to one. In a case of n being one, the interconnection link will be a serial link and in a case of n being more than one, the interconnection link will be a parallel link. The memory controller151is connected to the first memory device154-1of the serial interconnection. The last memory device154-M is also connected to the memory controller151so that first, second, third, . . . , and M-th memory devices154-1,154-2,154-3, . . . , and154-M of the serial interconnection together with the memory controller151form a ring connection structure. In the illustrated example, the memory devices154-1-154-M are flash memory devices. Subsequent examples are also specific to flash memory. However, it is to be understood that embodiments of the present invention are also applicable to other types of non-volatile memory devices.

In the particular example shown inFIG. 1, each of the series-connected memory devices154-1-154-M is a flash memory device, such as, for example, a NAND flash device. The flash memory device has a page buffer for temporary storing information on data. The stored information is written into flash memory cells of the device in accordance with page programming. Once programmed, the information stored in the page buffer is corrupted due to the verification process of the programmed cells.

The memory controller151has a data storage152and a processor153. The data storage152stores various data that includes information on operation instructions, addresses and memory data to be processed and to be stored in the series-connected memory devices. The information on operation instructions is used for controlling the series-connected memory devices. The data storage152is, for example, a static random access memory (SRAM) or any type of embedded memory. More generally, any appropriate data storage may be implemented. The processor153performs operations of data processing and controlling of the memory devices accessing the data stored in the data storage152. The memory controller151has a plurality of connections: a command signal output connection CIO, a command signal input connection COI, an input strobe connection CSIO, an output strobe connection DSIO and a clock output connection CKO.

In operation, the memory controller151sends a command input (CI) signal SC1through the command signal output connection CIO to the first device154-1and receives a command output (CO) signal SC(M+1)from the last device154-M of the serial interconnection, through the command signal input connection COI. Also, the memory controller151provides a command strobe input (CSI) signal SCS1through the input strobe connection CSIO and a data strobe input (DSI) signal SDS1through the output strobe connection DSIO to the first device154-1. Furthermore, the memory controller151provides a clock signal CK through the clock output connection CKO to all of the devices154-1-154-M in a common clock source fashion.

The memory devices154-1,154-2,154-3, . . . , and154-M have page buffers158-1,158-2,158-3, . . . , and158-M, respectively, and flash memory cells159-1,159-2,159-3, . . . , and159-M, respectively. Each of the memory devices154-1-154-M has a signal input connection CI for receiving the CI signal SCi(i=1 to M) from a previous device; a signal output connection CO for providing the CI signal SC(i+1)to a succeeding device; an input strobe input connection CSI for receiving the CSI signal SCSifrom a previous device; an input strobe output connection CSO for sending an output CSI signal SCS(i+1)to the succeeding device; an output strobe input connection DSI for receiving the DSI signal SDSifrom the previous device; and an output strobe output connection DSO for sending an output DSI signal SDS(i+1)to the succeeding device.

Each of the memory devices154-1-154-M has a unique device address (DA) that is hard wired or pre-assigned, so that one device can be selected or designated at a time in normal operation. Example details of an architecture featuring devices connected in-series are provided in U.S. patent application Ser. No. 11/594,564 entitled “Daisy Chain Cascading Devices” filed Jul. 31, 2006, the disclosure of which is hereby incorporated by reference in its entirety. Other example details of an architecture feature devices connected in-series are provided in U.S. Provisional Patent Application Ser. No. 60/868,773 entitled “System and Method of Operating Memory Devices of Varying Type” filed Dec. 6, 2006, the disclosure of which is hereby incorporated by reference in its entirety. Examples of the device address assignment in a plurality of memory devices that are connected in-series are provided in U.S. Provisional Patent Application No. 60/787,710, filed Mar. 28, 2006; U.S. patent application Ser. No. 11/521,734 filed Sep. 15, 2006; U.S. Provisional Patent Application No. 60/802,645, filed May 23, 2006; and U.S. patent application Ser. No. 11/750,649 filed May 18, 2007, the disclosures of which are incorporated by reference in their entirety.

In the normal operation, the memory controller151sends the CI signal SC1containing commands. A command includes a device address (DA) and an operation code (hereinafter OP code) representing an operation instruction. Some commands additionally include address information, and some commands additionally include data. Each OP code is associated with a respective operation. Each command is also referred to herein as having a type that is associated with the OP code contained in the command. For example, a command containing a read OP code is referred to as a “read command”. Each of the memory devices154-1-154-M receives commands via its respective CI either directly from the memory controller in the case that a given device is the memory device connected directly to the memory controller (device154-1in the illustrated example), or from an adjacent preceding memory device for other devices. Each of the memory devices154-1-154-M uses its respective CO for forwarding on commands either to the memory controller151in the case that a given device is the one having its output connected to the memory controller (device154-M in the illustrated example), or to an adjacent following device. A command containing a write OP code addressed to a particular flash memory device results in data being written to a page buffer of that device, and then transferred from the page buffer to the flash memory cells of the memory device. A command containing a read OP code addressed to a particular flash memory device results in data being read from the flash memory cells of the memory device to the page buffer of the memory device and then being transferred out of the page buffer.

The memory controller151issues commands, each of which include a device address (DA), a command operation code (hereinafter OP code). Some commands may additionally include address information, and some commands may additionally include data. Each OP code is associated with a respective operation. Each command is also referred to herein as having a type that is associated with the OP code contained in the command. For example, a command containing a read OP code may be referred to as a “read command”. For example, commands for use in the series-connected devices are flexible modular commands, the structure of which is shown in Table I:

In Table I, DA is a device address; OP code is an operation code; RA is a row address; CA is a column address; and DATA is write data. Examples of commands associated with OP codes are a “burst data load” command and a “burst data read” command. There are cases of: (i) either of row address or column address; (ii) neither row address nor column address; (iii) no data.

FIG. 2is a schematic of example command formats for the memory devices interconnected in-series. Referring now toFIG. 2, a first command format109-1includes an ID number and an OP code. The ID number is used to uniquely identify a selected memory device, while the OP code field contains the OP code to be executed by the selected device. Commands with the first command format109-1may for example be used for commands containing OP codes for reading a register value. A second command format109-2includes an ID number, an OP code and data. Commands with the second command format109-2may for example be used for commands containing OP codes for writing data to a register. A third command format109-3includes an ID number, an OP code, and additional addresses. The additional addresses may for example include row and/or column addresses for addressing a location in memory cells. Commands with the third command format109-3may for example be used for commands containing OP codes for reading data from memory cells of a selected memory device. A fourth command format109-4includes an ID number, an OP code, additional addresses, and data. Commands with the fourth command format109-4may for example be used for commands containing OP codes for writing data to the memory cells of a selected memory device. Note that all four example command formats109-1,109-2,109-3,109-4start with an ID number for addressing purposes. It should be understood from the foregoing that the term “command” as used herein does not merely refer to a command OP code, as a command may include an ID number, an OP code, additional addresses, data, or any other information relating to the control of an arrangement of memory devices interconnected in-series.

A particular example of the above-referenced command structures are taught in commonly assigned and co-pending U.S. patent application Ser. No. 11/840,692 filed on Aug. 17, 2007 and U.S. Provisional Patent Application No. 60/892,705 filed on Mar. 2, 2007, the contents of which are hereby incorporated by reference in their entirety. The applications disclose different command structures to distinguish core access operations that involve relatively long processing times from page buffer access operations that involve relatively short access times. Further details of the modular command structure are provided below under the heading “Modular Command Structure”.

Referring back toFIG. 1, each of the memory devices154-1,154-2,154-3, . . . , and154-M receives commands via its respective CI either directly from the memory controller in the case that a given device is the memory device connected directly to the memory controller (device154-1in the illustrated example), or from an adjacent preceding device for other devices. Each memory device uses its respective CO for forwarding on commands either to the memory controller in the case that a given device is the one having its output connected to the memory controller (device154-M in the illustrated example), or to an adjacent following device. With conventional command structures, a command containing a read OP code addressed to a particular flash memory device results in data being read from the flash memory cells of the memory device to the page buffer of the memory device and then being transferred out of the page buffer. A command containing a write OP code addressed to a particular a flash memory device results in data being written to a page buffer of that device, and then transferred from the page buffer to the flash memory cells of the memory device.

FIG. 3shows an example procedure for page programming and verification. Referring toFIGS. 1-3, an example of how a write operation is performed will be described. It is assumed that data is to be written to the memory device154-2. Data to be programmed (e.g., 100110 . . . 0100) is loaded into the page buffer158of memory device154-2from storage elements152of the memory controller151(step112-1). Programming of the data into in an assigned row address (page direction) of the flash memory commences (step112-2). The programming result is verified (step112-3). A verify result is produced in the page buffer that overwrites the page buffer contents that were written to the flash memory core with ‘1’ states indicating pass and ‘0’ states indicating failure. The programming operation may not pass because of defects on memory cells, wearing out of cell gate oxide or other defects. Internally, program and verify operations are performed several times for a specified period that is called a program time. As indicated at112-4, the final contents of the page buffer158become all ‘1’ states if all cells of the selected row (page direction) are programmed correctly. After the program time, if any ‘0’ value in the page buffer158of device154-2still exists, then the page program has failed as indicated at112-5. In the event of failure, the data is re-loaded from the storage elements152of the memory controller151to resume the page program operation to a different row address (page direction) of the same selected device.

In general, flash memories have a fundamental limitation of long program time due to cell characteristics and time used to verify the program status. Because of the fail probability of the page program operation, the data storage elements152of the memory controller151hold the initial program data in order to allow the recovery of the original program data in the event of program failure. The result is that the initial program data occupies space in the data storage elements151thereby preventing the space from being used for other purposes. It may result in having to wait until the page program operation and verification has completed before performing other page program operations. A possible approach to improving performance may be to increase the capacity of the storage elements in the memory controller, but this can be costly.

In the example system150shown inFIG. 1, when performing a page program operation with a selected memory device, the memory controller151loads the data into the page buffer158of the selected memory device and also into the page buffer of another memory device in order to store a back-up copy of the data. In this example, it is assumed that the selected memory device is the first memory device154-1and the other memory device is the second memory device154-2. More generally, the selected memory device and the other memory device may be any two of the memory devices154-1,154-2,154-3, . . . , and154-M. In the event that the data is not successfully programmed into the memory cells of the selected memory device154-1, then the memory controller151recovers the data from the page buffer158of the second memory device154-2. The page buffer158of the second memory device154-2is accessed independently of the program operation. This allows the data to be recovered without having to program the data into the memory cells of the second memory device154-2. Since a copy of the data is stored in the page buffer158of the second memory device154-2, the memory controller151does not need to locally store the data in its data storage elements152. Therefore, the memory controller151can free up space in its data storage elements152where the data is stored before determining whether the data has been successfully programmed into the memory cells of the selected memory device154-1.

In the particular example, for the purpose of allowing the page buffers to operate as a mirror back-up, in accordance with an embodiment of the invention, three “modular” memory device access commands are used. The first is referred to as a “burst data load” command and contains a burst data load OP code. This causes data to be written to the page buffer, but this command alone does not cause the data to be transferred to the flash memory cells. In the examples that follow, 4Xh and 5Xh are used for this, but more generally the command structure would be defined on an implementation specific basis. The second is referred to as a “burst data read” command and contains a burst data read OP code. This causes data to be read directly from the page buffer without first reading from the flash memory cells. In the examples that follow, 2Xh is used for this, but more generally, the command structure would be defined on an implementation specific basis. The third is referred to as a “page program” command and contains a page program OP code. This causes data that was previously stored in the page buffer to be written to the flash memory, destroying the contents of the page buffer in the process for verification purposes. In the examples that follow, 6Xh is used for this, but more generally, the command structure would be defined on an implementation specific basis.

FIG. 4shows two memory devices shown inFIG. 1. Referring toFIGS. 1 and 4, two devices120and127represent two devices in the system150and two devices are adjacent to or remote from each other in the interconnection configuration. One of the two devices120and127is used as a mirror back-up for data.

The first memory device120has an input connection139, an output connection140, flash memory cells121, a page buffer122and a device controller126. Similarly, the second memory device127has an input connection141, an output connection142, flash memory cells128, a page buffer129and a device controller130. The two memory devices120,127are any two memory devices that form part of an architecture featuring devices interconnected in-series. For the particular example, one of the two memory devices120and127is used as a mirror back-up for data. The device controllers126and130include any appropriate circuitry for facilitating processing of commands. Subsequent examples will not refer to any device controllers; however, it is to be understood that they would include circuitry for processing commands.

In operation, the page buffer122of the first memory device120is loaded with data by the burst data load command (4Xh and 5Xh) through the input connection139as indicated at123. In this example, the data is also loaded into the page buffer129of the second memory device127through the input connection141as indicated at137. Page programming within memory device120is accomplished by a page program command (6Xh) as indicated at124. The page buffer122is read through the output connection140using the ‘Read Device Status (D0h)’ as indicated at125to verify whether the page programming operation was successful or not. The second memory device127is used as a mirror back-up for page program operation in the event that page programming is unsuccessful for the first memory device120. A memory controller (not shown) keeps track of which memory device is being used as the mirror back-up. In the event of program failure, the data can be recovered from the mirror back-up through the output connection142as indicated at138. This removes the need for the memory controller to store the contents in its storage elements. Thus, the location used by the memory controller to store the data prior to its being programmed to the page buffers122,129can be freed up for other purposes.

The mirror function of page buffer for systems having an architecture in which devices are interconnected in-series will now be described with reference toFIGS. 5 and 6.FIG. 5provides an example where the same data is to written to two different page buffers using two separate write commands (i.e., one for each page buffer). In another implementation, a single write command is used to write the same data to two or more page buffers. An example of this is provided below with reference toFIG. 6.

FIG. 5shows a system having an architecture featuring devices connected in-series in which a page buffer is used as a mirror backup for data. Referring first toFIG. 5, a system190having a memory controller191and a plurality of memory devices193-1,193-2,193-3, . . . , and193-15that are connected in-series. In the particular example, the system190includes 15 memory devices. More generally two or more may be provided. The memory controller191has data storage elements192and a data processor203. The memory controller191also has an output connection CIO for connecting with the first memory device193-1, and an input connection COI for connecting with the last memory device199-15. The memory devices193-1,193-2,193-3, . . . , and193-15have page buffers194,196,198and190, respectively, and each of the memory devices193-1,193-2,193-3, . . . , and193-15has memory cells (not shown).

The memory controller191and the memory devices193-1,193-2,193-3, . . . , and193-15are interconnected with serial links. Other examples described herein are also specific to serial links between consecutive devices. However, it is to be understood that embodiments of the invention are also applicable to architectures featuring parallel links between consecutive devices. More generally, embodiments of the invention are applicable to architectures featuring series links between consecutive devices. The series links may be serial links, or parallel links. The system190uses a page buffer as a mirror backup for data. In the illustrated example, two devices are interconnected by a link having one I/O pin. Alternatively, a link can include a plurality of I/O pins. The memory devices193-1,193-2,193-3, . . . , and193-15has respective processing circuitry for processing a signal through the CI connection from a previous device and outputting processed result though the CO connection to a next device. For simplicity, such circuitry is shown by a representing D-type flip-flop (D-FF).

For this example, it is assumed that the memory controller191needs to write data to the memory cells of memory device193-1, and that the page buffer194-2of the memory device193-2is available for use as a mirror backup. In operation, the memory controller191issues a first write command in order to load data from the data storage elements192into the page buffer194-1of the first memory device193-1. The loading of the data into the page buffer194-1is generally indicated at201. In order to keep a back-up copy of the data in the event that the page programming fails, the memory controller191also issues a write command (page buffer load) in order to load the same data into the page buffer194-2of the second memory device193-2. The loading of the data into the page buffer194-2is generally indicated at202. The memory controller191then issues a page program command to program the data that has been loaded into the page buffer194-1into the memory cells (not shown) of the first memory device193-1. In the illustrated example, the data is not programmed into the memory cells of the second memory device193-2. Instead, the data is maintained in the page buffer194-1as a mirror back-up copy of the data in case the page programming for the first memory device193-1fails.

The memory controller191keeps track of which memory device193-2is being used as the mirror back-up. In the event of program failure, the data can be recovered from the mirror back-up. This removes the need for the memory controller191to store the contents in its data storage elements192. Therefore, as soon as the page buffer loads are done, the data storage elements192previously used to store the data are freed up for other uses. The memory controller keeps track of which data storage elements192are free, and which are in use. In the event of success in the page programming operation, the locations in the page buffer194-2being used as a mirror back-up are freed up.

Note that the first memory device193-1and the second memory device193-2are selected by the memory controller191. The memory controller191can alternatively select different memory devices. Each write command is addressed to a target memory device by DA.

Note that for the devices connected in-series, there is a clock cycle based latency delay between memory devices to synchronize output result (CO) from input (CI). The latency can be determined according to the system and device specification. All examples assume a one clock cycle latency between input and output. Therefore, between two adjacent memory devices, there is a one cycle difference when input data is captured. However, it is to be understood that the clock cycle latency may alternatively be smaller such as a half cycle, or greater such as over two cycles. Regardless, the memory devices take input streams with the latency delay.

FIG. 6shows another system having an architecture featuring devices connected in-series in which a page buffer is used as a mirror backup for data. Referring toFIG. 6, a system210using a page buffer214-2as a mirror backup for data. The system210has a memory controller211and a plurality of memory devices213-1,213-2,213-3, . . . , and213-15. The memory controller211has data storage elements212, which is, for example, an SRAM. The memory controller211also has a data processor209, an output connection CIO for connecting with the first memory device213-1, and an input connection COI for connecting with the last memory device213-15. The memory devices213-1,213-2,213-3, . . . , and213-15have page buffers214-1,214-2,214-3, . . . , and214-15, respectively, and each of the memory devices has memory cells (not shown). The memory controller211and the memory devices213-1,213-2,213-3, . . . , and213-15are interconnected with links. A detailed example of mirror backup operation for the system ofFIG. 6is described further below.

In an example system, a memory device that is to function as a mirror backup for a given memory device is statically defined. A particular example of such a static definition is defined in the tables below in which it is assumed that: for a given device having an even device address, the device that is to function as a mirror backup for the given device is the device having an address one greater than that of the given device (see Table 2) and for a given device having an odd address, the device that is to function as mirror backup for the given device is the device having an address one less than that of the given memory device (see Table 3).

TABLE 2For even device addresses, static association between DesignatedTarget Address (DAt) and Mirror Address (MA) defined by:MA = DAt + 1Designated Target Address (DAt)Mirror Address (MA)000000010010001101000101————1010101111001101

TABLE 3For odd device addresses, static association between DesignatedTarget Address (DAt) and Mirror Address (MA) defined by:MA = DAt − 1Designated Target Address (DAt)Mirror Address (MA)000100000011001001010100————1011101011011100

In the examples defined by Tables 2 and 3 above, the designated target device and the mirror device share common addresses with the exception of the LSB (least significant bit). More generally, in some examples, the relationship between the designated target device and the mirror device is used to efficiently address the two devices without requiring two separate commands to be sent.

A specific example of this applies to the mirror backup device definitions in Tables 2 and 3 in which a new mode of operation referred to as “ignore LSB mode” in which all devices compare all bits of the address of each incoming command except the LSB to corresponding bits of the device's device address (namely all of the bits except the LSB). In such a mode, both a device having a given designated target address, and an appropriate mirror device will process the command. In some implementations, a command is first sent to turn on ignore LSB mode. This can be done using an address that is processed by all devices, referred to as a broadcast address. This is followed by a command to load data to the page buffer, this resulting in the data being loaded to the page buffer of both a designated target device and the mirror device. After this, ignore LSB mode is turned off again, and a command to write the contents of the page buffer of the designated target device to the core memory is sent and processed only by the designated target device. In another example, a different OP code is defined that signifies ignore LSB mode for that command. In another embodiment, ignore LSB mode is only active for at most one following command and as such, there is no need to turn off ignore LSB mode if such a command has been sent. In another embodiment, another field in a command is used to signify ignore LSB mode.

An example of this will now be described with reference toFIG. 6where it is assumed that the memory controller211has determined to write data to the memory cells of memory device213-1, while using the page buffer214-2of the memory device213-2as a mirror backup. This example differs from the example ofFIG. 5in that the memory controller211issues a single write command in order to load data from the data storage elements212to both the page buffer214-1of the first memory device213-1and the page buffer214-2of the second memory device213-2. This is accomplished during an “ignore LSB mode”, where the memory devices ignore the LSB of the target device address found in the single write command. In this example, the memory controller211sends an ‘ignore LSB’ command to all memory devices213-1,213-2,213-3, . . . , and213-15of the devices connected in-series to inform them to ignore the LSB of the target device address of subsequently received commands. The ignore LSB command is, for example, a ‘Write Link Configuration Register’ command with an OP code of FFh that is sent to a broadcast address that is processed by all memory devices. Any appropriate structure for such a broadcast command may be used; more generally, any appropriate mechanism for enabling the ignore LSB mode can be implemented. Various examples have been provided above.

Once the ignore LSB mode is enabled, two memory devices are selected by a single target address. For example, a page buffer load command having a target address of “0000” will be processed by both the first memory device213-1having a device address (DA) of “0000” and the second memory device213-2having a device address of “0001”. Note that the first and second memory devices213-1and213-2have identical device addresses with exception to the LSB. One of the two memory devices213-1and213-2(e.g., the first memory device213-1) is used as a “designated target device”, while the other memory device (e.g., the memory device213-2) is used as a “mirror device”, the page buffer of which stores mirror program data. Once the page buffer load command is issued, data loading starts. The page buffers214-1and214-2of two selected devices213-1and213-2store the data thereinto. The loading of the data into the page buffers214-1and214-2is generally indicated at221and222. Prior to programming, the ignore LSB mode is reset and normal operation where only one memory device is selected at a time resumes. This is, for example, accomplished by issuing another broadcasting command. Example timing details of the enabling and disabling of the ignore LSB mode for the system210are provided below with reference toFIG. 7.

FIG. 7shows an example timing diagram of enabling and disabling of an LSB ignore mode for the system ofFIG. 6. Referring toFIGS. 6 and 7, the memory controller211outputs three signals: a clock signal CK; a command strobe input signal CSI and a command input signal CI. Note that the CSI signal is asserted during three stages, namely, first, second and third stages.

The first stage is indicated at281. The memory controller211sends an ‘ignore LSB’ command to inform the memory devices to ignore the LSB of the target device address of subsequently received commands. The command contains a broadcast DA and an OP code for enabling ignore LSB mode. Here is assumed that ‘FF’ is a broadcast address that results in all of the memory devices in the devices connected in-series accepting and processing this command.

The second stage is indicated at282. The memory controller211transmits a command for loading data into the page buffers214-1and214-2of the first two memory devices213-1and213-2. The command includes the device identifier (ID) for the first memory device213-1and the burst data load instruction (CMD). Since ignore LSB mode has been enabled, both the first and second memory devices213-1and213-2process the command and load the data into their page buffers214-1and214-2.

The third stage is indicated at283. The memory controller211transmits a command for disabling the ignore LSB mode. The ID is again the broadcast ID ‘FF’.

Once the ignore LSB mode has been disabled, the memory controller211issues a page program command to program the data that has been loaded in the page buffer214-1into the memory cells (not shown) of the first memory device213-1. In the illustrated example, the data is not programmed into the memory cells (not shown) of the second memory device213-2. Instead, the data is maintained in the page buffer214-2of the second memory device213-2as a mirror back-up copy of the data in case the page programming for the first memory device213-1fails. The second memory device213-2should not be accessed for any core operations using the page buffer214-2. However, register based commands, such as status, configuration register read or write are possible. Other memory devices213-3, . . . , and213-15can be freely accessed.

FIG. 8shows the system210ofFIG. 6in which a data recovery is performed after program failure. Referring now toFIG. 8, a data path for the data recovery is generally shown at223. At first, the program data in mirror buffer214-2of the second memory device213-2is transmitted to the data storage elements212of the memory controller211to thereby allow the memory controller211to recover the initial program data that may not have been kept in the data storage element212due to its being used for other purpose. Next, the program data recovered from the mirror buffer214-2is sent to a new page address by performing a page buffer load and page program. This may be to another page on the first memory device213-1or a page on another memory device. If it is another memory device, the process starts from scratch by reloading the data into two page buffers. Alternatively, the data loaded into the mirror buffer214-2can be maintained while the recovered data is loaded into the page buffer of another memory device. The memory controller211keeps track of, and does not use, failed pages. In the example depicted inFIG. 8, the program data recovered from the mirror buffer214-2is sent to the page buffer214-1of another memory device213-1as indicated at224.

In the illustrated examples provided above, specific details of the memory devices for implementing the ignore LSB feature are not provided. It is to be understood that the memory devices can be implemented with any appropriate control circuitry for accomplishing the ignore LSB feature. A specific implementation is provided below with reference toFIGS. 9 and 10for exemplary purposes.

FIG. 9shows part of the series-connected memory devices shown inFIG. 1. As shown, command input signal SCiinput to a device154-ifrom a previous device154-(i−1) can be transmitted to the next device154-(i+1).

FIG. 10shows memory device circuitry for use in a memory device of the devices connected in-series. The memory device circuitry implements the Ignore LSB feature. Referring toFIG. 10, a memory device154-ihas a plurality of inputs including a clock input CLK for receiving the clock signal CK, a command strobe input CSI for receiving the command strobe signal SCSi, a data strobe input DSI for receiving the data strobe signal SDSiand a command input CI for receiving the command input signal SCi. The memory device154-ihas a plurality of outputs including a command strobe output CSO for outputting the command strobe signal SCS(i+1), a data strobe output DSO for outputting the data strobe signal SDS(i+1)and the command output CO for outputting the command input signal SC(i+1)to the next device154-(i+1).

The clock signal CK, the command strobe signal SCSi, the command input signal SCiand the data strobe signal SDSiare buffered by respective input buffers281,282,283and284. The buffered clock signal and command input signal are fed to a clock generator264which outputs internally generated clock signals: an ID clock signal Clkid, an OP code clock signal Clkop, an address clock signal Clkad and a data clock signal Clkda. The ID clock signal Clkid, the OP code clock signal Clkop, the address clock signal Clkad and the data clock signal Clkda are fed to an ID register265, an OP code register266, an address register268and a data register269. The appropriate fields of the command of the command input signal SCiare input to the ID register265, the OP code register266, the address register268and the data register269in response to the respective clock signals. The OP code held in the OP code register266is fed to the OP code decoder267for decoding. The OP code decoder267outputs one-bit signal SIGB to a one-bit register276and a multi-bit (m-bits: e.g., three-bit) decoded OP code signal SDOP to core logic and memory circuitry285. The core logic and memory circuitry285also receives the buffered data strobe signal.

The command input signal SCiis latched by a D-FF251, the output of which is buffered again to produce command input signal SC(i+1)to be forwarded on to the next memory device154-(i+1).

The memory device154-iincludes exclusive NOR (XNOR) logic circuitry272that receives as input the n-bit output of the ID register265and n-bit contents of a device ID register273for holding a value of the device address (DA). The XNOR logic circuitry272has n XNOR gates that perform bitwidth XNOR operation between the n-bit output of the ID register265and the n-bit contents of the device ID register273and produces an n-bit output. The LSB of the n-bit output the XNOR logic circuitry272is input to one input of an OR gate274, and the remaining bits of the n-bit output of the XNOR logic circuitry272are input to AND logic circuitry275. The one-bit register276is provided for registering the “ignore LSB enable bit” (in the signal SIGB) from the OP code decoder267. The output of the one-bit register276is input as a second input to the OR gate274, and the output of the OR gate274is fed as another input to the AND logic circuitry275. The operation of these components is described below.

In operation, the memory device154-ireceives a command in the command input signal SCi. Based on the timing of the command strobe signal SCSitogether with the clock signal CK, the clock generator264generates internal clock signals for appropriately latching the contents of the command to the appropriate registers. More specifically, the ID register265registers the ID of the command. The OP code register266registers the OP code. The address register268registers the column/row addresses. The data register269registers any data included in the command. In addition, the OP code decoder267receives the command registered in the OP code register266and decodes it. The buffered clock signal is provided to D-FFs in the circuitry (clock signal paths are not shown).

In the event the command is either a command containing a broadcast DA, or a command addressed to the specific device, the OP code is decoded and processed by the device. With the broadcast DA, all devices are to be asserted and ready to receive a command. Upon receipt of a command to enter the ignore LSB mode as determined by the OP code decoder266, the one-bit register276is set and thus, the “ignore LSB enable bit” is set to enable LSB ignore mode.

The ID register265outputs the registered DA, which is the target DA, in parallel as n-bit data. The XNOR logic circuitry272compares the target DA (that is represented by the ID number contained in the command) with the device ID held in the device ID register273on a bit for bit basis. If the target DA and the device ID are identical, then the output of the XNOR logic circuitry272will be all ‘1’s. The LSB of the comparison is fed into the OR gate274, while the other bits are fed into the AND logic circuitry275. The LSB of the comparison being “high” is sufficient for the OR gate274to have a “high” output. The OR gate274is also fed with the “ignore LSB enable bit” of the one-bit register276. The “ignore LSB enable bit” of the one-bit register276being “high” is also sufficient for the OR gate274to have a “high” output. Therefore, if the “ignore LSB enable bit” of the one-bit register276is high, then it does not matter whether the LSB of the target DA matches the LSB of the device ID. Rather, the non-LSB bits matter. The AND logic circuitry275outputs an ID match signal277that indicates whether there is a match between the target DA and the device ID. This will be true if all of the n inputs to the AND logic are high. During ignore LSB mode, this will be true if other (n−1) bits except for the LSB match during the ignore LSB mode. When not in ignore LSB mode, this will be true if all n bits match. The ID match signal277from the AND logic circuitry275determines whether the memory device154-iexecutes the command. Upon receipt of a command to exit the ignore LSB mode, the one-bit register276is cleared. The ID match signal277is provided to the core logic and memory circuitry285and an AND gate278. The output of the one-bit register276is input to an inverter279, the inverted output signal of which is provided to the AND gate278, the AND logic output signal of which is fed to multiplexers254and256.

When there is no match between the target DA and the device ID, the ID match signal ID match signal277is “low” and the multiplexer254is selected to its “0” input. Therefore, the latched command input signal is provided as the command input signal SC(i+1) to the next device154-(i+1). Also, the latched command strobe signal is provided through the multiplexer256as the command strobe signal SCS(i+1) to the next device154-(i+1). Thus, there is no ID match, the device154-1is not the target device and the command input signal SCi and the command strobe signal SCSi are forwarded to the next device154-(i+1). If the data strobe signal is input (e.g., in the data read mode operation), the latched data strobe signal is provided through the multiplexer255as the data strobe signal SDS(i+1) to the next device154-(i+1), regardless of the status of the ID match signal ID match signal277. With no ID match, the core logic and memory circuitry285is not activated.

When there is a match between the target DA and the device ID during ignore LSB mode (i.e., the output of the one-bit register276is “high”), the ID match signal277is “high”, the core logic and memory circuitry285is activated. However, the output signal of the inverter279is “low” and the “0” inputs of the multiplexers254and256are selected. The input signal is provided as the command input signal SC(i+1)to the next device154-(i+1). Also, the command strobe signal is provided as the command strobe signal SCS(i+1)to the next device154-(i+1).

When there is a match between the target DA and the device ID during non-ignore LSB mode (i.e., the output of the one-bit register276is “low”), the ID match signal277is “high”, the core logic and memory circuitry285is activated and the decoded OP code of the decoded signal SDOP from the OP code decoder267is executed to operate in accordance with the command instruction. The output signal of the inverter279is “high” and the AND logic output signal of the AND gate278is “high”. The “1” inputs of the multiplexers254and256are selected. If the instruction is a data read, the core logic and memory circuitry285executes the read command and in accordance with the addresses of row and/or column, data is read from the memory therein (not shown). The output data DATAout from the core logic and memory circuitry285is provided as the command input signal SC(i+1)to the next device154-(i+1).

The examples presented above show how two memory devices can process a single command when they have identical device addresses with exception to the least significant bit. This is accomplished while the memory devices are in an ignore LSB mode. More generally, embodiments of the invention allow for two or more memory devices to process a single command based on the target address of the single command. For example, in another embodiment, the memory devices enter a multi-address detection mode. This may occur for example if the memory controller broadcasts a first message instructing each memory device to enter the multi-address detection mode. While in the multi-address detection mode, upon receiving a command having a destination address that differs from the device address, the memory device conditionally processes the command based on the destination address. At some later time, the memory devices exit the multi-address detection mode. This may occur for example if the memory controller broadcasts a second message instructing each memory device to exit the multi-address detection mode. The messages broadcasted for entering and exiting the multi-address detection mode are, for example, a write link configuration register command comprising an op-code of FFh.

There are many ways for a memory device to conditionally process the command based on the destination address. In some implementations, the memory device maintains an identification of an alternative device address. If the target device address of the received command matches the alternative device address, then the memory device processes the command. In other implementations, the memory device conditionally processes the command if the destination address differs from the device address in a predefined manner. For example, the memory device processes the command if the destination address differs from the device address only by a single predefined bit. The single predefined bit can be the least significant bit, examples of which have been provided above. Alternatively, the single predefined bit is some other bit.

FIG. 11shows a method of program operation with a mirror back-up. This method can be implemented by a memory controller, for example by the memory controller211shown inFIG. 6.

Referring toFIGS. 6 and 11, at step311the memory controller211sends an “ignore LSB” command to all memory devices213-1,213-2,213-3, . . . , and213-15connected in-series to inform them to ignore the LSB of the target device address to be received. In step312, the memory controller211sends a target device address as part of a command to write to the page buffer. In a particular example, assume that the target device address is ‘0000’, namely the device address of device213-1ofFIG. 6. With that address, both devices213-1and213-2will process the command while in ignore LSB mode. More generally, for a given target device address, two of the devices will process the command. The command to write to the page buffer includes data to be written. With device address matching, the data is latched by both memory device213-1and memory device213-2. Thus, the transmitted data is loaded into the page buffers of both devices only (step312). This is accomplished using a single command.

Subsequently, the memory controller211sends a “normal DA set” command to all memory devices213-1,213-2,213-3, . . . , and213-15to inform them to no longer ignore the LSB of the target device address found in received commands (step313). Then, the memory controller211starts page programming for the designated device by sending a page program addressed to that device (step314). If the memory controller211determines that the page programming is successful (YES at step315), then processing ends. The page programming determination is performed by reading the program status from the page buffer. If the memory controller211determines that there is a program failure (NO at step315), then the memory controller211re-loads the program data from the page buffer of the mirror memory device213-2(step316). The program data is stored locally within data storage elements of the memory controller.

Next, the memory controller211loads the program data back into the page buffer of the designated memory device at step317. Processing continues at step314by retrying to program the data into the memory cells of the designated memory device, details of which have also been provided above. In this example, it is assumed that another attempt to program the data into the same memory device is made. Alternatively, the data can be programmed into the memory cells of another memory device. Also, in this example, it is assumed that the mirror backup copy is maintained in the same place (device213-2for this example) until a successful page program operation is completed. Alternatively, a mirror backup copy can be made in a different location.

In some examples, the systems described herein are implemented using a flexible modular command structure, example details of which have already been provided. Further example details are provided in this section with reference toFIGS. 12 through 20. It is to be understood that the details provided in this section are very specific for exemplary purposes only.

FIG. 12is a table of an example command set for flash memory with modular command in byte mode. The table includes 15 operations: Page Read, Page Read for Copy, Burst Data Read, Burst Data Load Start, Burst Data Load, Page Program, Block Erase Address Input, Page-pair Erase Address Input, Erase, Operation Abort, Read Device Status, Read Device Information Register, Read Link Configuration Register, and Write Link Configuration Register (device specific), and Write Link Configuration (broadcast). Each operation has a command including a Device Address (DA) (1 Byte) and an Operation (OP) Code (1 Byte). Some commands include a Row Address (3 Bytes), a Column Address (2 Bytes), and some commands include Input Data (1 to 2112 Bytes). ‘X’ is ‘0h’ for “Bank 0”. ‘X’ is ‘1h’ for “Bank 1” where it is assumed for this specific example that each device has two memory banks. More generally each device has at least one memory bank. For the last command in the table, namely the write link configuration (broadcast), the device address is set to “FFh” to indicate a “broadcasting” command.

FIG. 13is an example operation table. The table includes modes for each of a plurality of combinations of /RST (complement of a reset signal), /CE (complement of a chip enable signal), CSI (command strobe input), and DSI (data strobe input). The modes include Command Data Packet, Read Data Packet, NOP (NO Operation), Standby, and Reset.

All commands, addresses, and data are shifted in and out of the memory device, starting with the most significant bit (MSB). Command input (CI) signal is sampled at the positive or negative clock edge (i.e., at the crossing point of clocks—CK and /CK) while the command strobe input (CSI) signal is “high”. Each command includes a 1-byte device address (DA) and 1-byte OP code and/or column-address/row-address/data-input bytes if necessary. Once the CSI transits logic “high”, the 1-byte DA (Device Address) is shifted into a DA register, and then the 1-byte OP code is shifted into an OP code register. In so doing, the most significant bit (MSB) starts first on the CI signal and each bit is latched at the crossing of clocks CK and /CK while CSI is logic-HIGH state. However every input sequence in byte mode starts at a rising edge of clock CK (=falling edge of /CK). Depending on the command, the OP Code are followed by address bytes, data bytes, both or none as shown inFIG. 12. For this example, the address cycle has a 2-byte column address and 3-byte row address.FIG. 14shows a definition of an example command and address format including the position of each bit.

For the memory devices connected in-series, a special device address (=FFh) is assigned for “Broadcast” operation. More generally, the address that is defined for broadcast mode operation can be defined on an implementation specific basis. This “Broadcast Device Address” may be used with any command. However, using the broadcast device address (FFh) along with the “read-type” commands is not recommended because the read data from the last device is the only valid output data.

In some implementations, the signal bus on a modular command Flash device is fully multiplexed as command, address and data all share the same pin(s). The CSI signal's logic-high state validates the command input (CI) signal which can be an n-bit wide signal containing multiplexed command/address/data information for the memory device. If the CSI signal stays in logic-low state, device ignores signal inputs from CI pins. The command input sequence normally consists of one-byte DA (Device Address) latch cycles, one-byte command latch cycles, address latch cycles (=3-bytes for row address or 2-bytes for column addresses) and/or data-input latch cycles up to 2,112 bytes. In 1-bit link mode, four clock-cycles at DDR (double data rate) make one byte of a serial packet. In 2-bit link mode, two clock-cycles at DDR (double data rate) make one byte of a serial packet. In 4-bit link mode, one clock-cycle at DDR (double data rate) makes one byte of a serial packet. Every set of command instructions may be followed by two extra CK and /CK transitions after CSI makes a HIGH to LOW transition. In some embodiments, an extra number of CK and /CK transitions after CSI transitions to low are used that are equal in number to 2+# of devices in the architecture with devices connected together in-series. Every input sequence defined inFIG. 12is “byte-based”, which means that CSI and CI should be valid for the unit of 8-latch cycles (=4 clock cycles at double data rate). If CSI makes a HIGH to LOW transition before the completion of byte, corresponding command and/or address sequences will be ignored by device. For the case of data input sequence, the last incomplete byte of input data will be ignored, but prior complete byte(s) of input data will be valid.

FIG. 15is an example timing diagram showing basic input timing. All DA/Command/Address/Data-Inputs are asserted continuously through CI port(s) and captured on the crossing of clocks CK and /CK when /CE is “low” and the CSI signal is “high”. The input data is shifted into the memory device, most significant bit (MSB) first on CI, each bit being latched at the crossing of clocks CK and /CK. An input sequence of bit streams is shown inFIG. 16. Every input sequence in byte mode starts at rising edge of clock CK as shown. Any input with incomplete byte will be ignored.

FIG. 17is an example timing diagram showing basic output timing. The output on the command output (CO) is synchronously shifted out at the crossing of clocks CK and /CK when /CE is “low”, and the DSI signal is “high”.FIG. 18shows an example output sequence in byte mode. The output data is shifted from the memory device, most significant bit (MSB) first on the CO signal, each bit being synchronized at the crossing of clocks CK and /CK. The DSI signal is activated referenced to the rising edge of CK so that every output sequence in byte mode starts at rising edge of CK with 1 clock read latency (=tOL) as shown inFIG. 17.

Two representative commands to show the feature of modular commands are described below, namely a Page Read (DA & 0Xh) and a Burst Data Read (DA & 2Xh) command.FIG. 19shows a flowchart involving the use of these commands, andFIG. 20shows an example command sequence.

With reference toFIG. 19, to enter the Page Read mode, at step411the memory controller issues the PAGE READ (DA & 0Xh) command to the command register over the CI along with three row address bytes. Issuing DA & 0Xh to the command register starts the address latch cycles at step412. Three bytes of row address are input next. The internal page read operation starts once the address latch cycles are finished. The 2,112 bytes of data within the selected page are sensed and transferred to the page buffers in less than tR (transfer time from cell array to page buffers). The status register can be checked at step413. After tR, a BURST DATA READ (DA & 2Xh) command (described in further detail below) along with two bytes of column address can be issued at step414and then the DSI signal can be enabled in order to read out page buffers' data, starting from the given column address, over the CO until the DSI signal goes low. If a user wants to monitor the internal page read status to determine whether the transfer from the cell array to page buffers is complete or not, the READ DEVICE STATUS (DA & D0h) command can be issued. Modular command flash has an 8-bit status register that the software can read during device operation.

The core access operations such as page read, page program and block erase take long time and their processing times are varied according to PVT (Process/Voltage/Temperature) change. So, whenever issuing core access commands, a user can monitor the status of each operation after asserting command without interrupting internal operations. The other purpose of the status register is to check whether or not the page program and block erase are performed without fail. In case of fail, a new row position is determined by the memory controller and it issues a new command containing new row address to write the same data that was written to the old row location that failed to be written. Without monitoring the status register, the memory controller does not know that the program and erase operations are done without fail.

After READ DEVICE STATUS (DA & D0h) command, using DSI, all 8-bit status is read from the status register until DSI goes to low. After the BURST DATA READ (DA & 2Xh) command has been issued and then DSI goes to high, the serial output timing as shown inFIG. 20will result in outputting data at step415, starting from the initial column address. The column address will be automatically increased during outputting data. At step416, there is ECC generation. If the ECC is verified at step417, then the page read is completed. Otherwise, at step418there is an error.

The BURST DATA READ (DA & 2Xh) command referred to above enables the user to specify a column address so the data at the page buffers can be read starting from the given column address within the selected page size while DSI is high. The burst data read mode is enabled after a normal PAGE READ (DA & 0Xh) command and page loading time (=tR). The BURST DATA READ (DA & 2Xh) command can be issued without limit within the page. Every BURST DATA READ command can have same or different column address from the previous BURST DATA READ command. Only data on the current page buffers can be read. If a different page is to be read, a new PAGE READ (DA & 0Xh) command should be issued. And after tR, a new BURST DATA READ (DA & 2Xh) command can be issued to access new page data.

In the embodiments described above, the device elements and circuits are connected to each other as shown in the figures, for the sake of simplicity. In practical applications of the present invention, elements, circuits, etc. may be connected directly to each other. As well, elements, circuits etc. may be connected indirectly to each other through other elements, circuits, etc., necessary for operation of the memory devices or apparatus. Thus, in actual configuration of devices and apparatus, the elements and circuits are directly or indirectly coupled with or connected to each other.