Wideband low distortion/low power

A differential circuit is described having first, second, third and fourth devices, each device having a control terminal and first and second terminals. The first and second devices are arranged to receive a differential input signal at their respective control terminals and each drive an end of a load in communication with a second terminal of the first and second devices. The third and fourth devices are in communication, via their first terminals, with the second terminal of a respective one of the first and second devices and with a respective one of the first and second input signals via their control terminals. The third and fourth devices each have second terminals biased with an impedance arranged so that variations in load current requirements are accommodated by the third and fourth devices and current through the first and second devices is substantially constant.

BACKGROUND

Driver or buffer circuits are often used to help isolate outputs and match output impedance to expected load impedances. An example of one known differential output driver100is illustrated inFIG. 1. The driver100includes a pair of transistors Q1, Q2in a push-pull configuration driving a resistive load RL. A direct current (DC) bias circuit102maintains a constant DC current through the transistors Q1, Q2. The DC bias circuit includes a pair of transistors M1, M2with gates tied to the gate of a transistor M0driven by a current source I0. Unfortunately, this type of driver can generate undesirable amounts of distortion.

As the input voltages Vpand Vmchange during operation of the driver100, the output voltages of Q1and Q2, Vopand Vom, respectively, change. In this example, the current through RLmay be calculated as IL=(Vop−Vom)/RL. The change in load current ILis accommodated by a change in the current through the transistors Q1and Q2because the DC bias circuit102maintains a fixed Ip2and Im2. As shown inFIG. 2, when Vop−Vomis at a maximum, Ip1is at a maximum and Im1is at a minimum. Similarly, when Vop−Vomis at a minimum, Im1is at a maximum and Ip1is at a minimum. The current swing of Ip1and Im1is offset by Ip2and Im2.

The modulation index for this swing in transistor current may be defined as IQ(max, min)/IQ(DC), where IQ(max, min) is the maximum or minimum total current through the transistor (i.e., bias current +/−load current) and IQ(DC) is the bias current through the transistor, which is substantially constant. Even a small change in load current ILmay lead to distortion because the change in load current is reflected by a proportional change in transistor current for the output transistors Q1, Q2. The larger the load current swing, the larger the modulation index, and the larger the distortion. This is because the transconductance of Q1and Q2varies as the current through these transistors varies. A variation in transconductance results in a variable gain because the base-emitter voltage drop in Q1and Q2varies with changes in transistor current.

One way to reduce the modulation index in the driver ofFIG. 1is to increase the DC bias current. By increasing the DC bias, the significance of variations in the load current can be reduced. Although the modulation index can be reduced in this manner, it merely masks the continuing problem of the distortion in the driver10. Also, reducing distortion by increasing DC bias involves greater power consumption and may be unacceptable in low power applications.

SUMMARY

The present invention is defined by the attached claims, and nothing in this section should be taken as a limitation on those claims. In order to address the drawbacks discussed above, described below is a low distortion, low power differential driver and method. According to one aspect, a differential circuit includes first, second, third and fourth devices each having a control terminal, a first terminal and a second terminal. A first input terminal is in communication with the control terminal of the first device and with the control terminal of the fourth device. A second input terminal is in communication with the control terminal of the second device and with the control terminal of the third device. A first output terminal is in communication with the second terminal of the first device and the first terminal of the third device. A second output terminal is in communication with the second terminal of the second device and the first terminal of the fourth device. Also, a biasing element is in communication with the second terminal of the third and fourth devices, where an impedance of the biasing element is substantially equal to an impedance of an expected load between the first and second output terminals. The biasing element may be a shared resistive or complex impedance. The biasing element may also be divided into separate biasing elements in communication with the second terminal of the third and fourth devices, respectively. The impedance of the biasing element, or the sum of the impedances of the separate biasing elements, is selected to match an impedance of the expected load between the first and second output terminals. In other implementations, the differential circuit may include fifth and sixth devices each comprising a control terminal, a first terminal and a second terminal, where the first input terminal is in communication with the control terminal of the fifth device and the control terminal of the fourth device is in communication with the first input terminal via the fifth device. In this implementation, the second input terminal is in communication with the control terminal of the sixth device, and the control terminal of the third device is in communication with the second input terminal via the sixth device.

According to another aspect of the invention, a differential circuit is disclosed having first and second devices each comprising a control terminal, a first terminal and a second terminal. A first input terminal is in communication with the control terminal of the first device, where the first terminal of the first device is configured for communication with a supply voltage and the second terminal of the first device defines a first output configured for communication with a first terminal of a load. A second input terminal is in communication with the control terminal of the second device, where the first terminal of the second device is configured for communication with the supply voltage and the second terminal of the second device defines a second output configured for communication with a second terminal of the load. A biasing network is in communication with the first and second input terminals, and with the second terminal of each of the first and second devices, where the biasing network is adapted to maintain a DC bias current in each of the first and second devices. The biasing network is further adapted to be responsive to changes in input voltage at the first or second input terminals to supply drive current to the load while maintaining a substantially constant current through the first and second devices.

In yet another aspect, a differential circuit includes first and second devices each comprising a control terminal, a first terminal and a second terminal. A first input terminal is in communication with the control terminal of the first device, where the first terminal of the first device is configured for communication with a supply voltage and the second terminal of the first device defines a first output configured for communication with a first end of a load. A second input terminal is in communication with the control terminal of the second device, where the first terminal of the second device is configured for communication with the supply voltage and the second terminal of the second device defining a second output configured for communication with a second end of the load. The differential circuit further includes means for maintaining a DC bias current in each of the first and second devices, as well as means for supplying drive current to the load in response to changes in input voltage at the first and second input terminals while maintaining a substantially constant current through the first and second devices.

In another aspect of the invention, a method is disclosed for driving a differential circuit. A first input signal is received at a first device in the differential circuit and a second input signal is received at a second device of the differential circuit. A load current is provided to a load in communication with the first and second devices. A substantially constant device current in each of the first and second devices is maintained when the load current changes. In one implementation, maintaining a substantially constant device current may be accomplished by automatically adjusting the load current via a load current drive circuit in response to a change in the first or second input signals.

The following description will now be described with reference to the attached drawings.

DETAILED DESCRIPTION

Referring toFIG. 3, a driver circuit300is shown. The driver circuit300is a differential driver with a positive input terminal Vpand a negative input terminal Vm. The positive input terminal Vpis connected to the base of transistors Q3and Q4. The negative input terminal Vmis connected with the base of transistors Q5and Q6. Transistors Q4and Q5are each arranged in an emitter-follower arrangement with the positive output terminal Vopconnected to the emitter of Q4in the negative output terminal Vomconnected to the emitter of Q5. Transistors Q3, Q4, Q5, and Q6are shown as bipolar junction transistors however other devices, such as three terminal devices, are also contemplated. Additionally, other types of transistors, for example field effect transistors, may be used.

Each of the transistors Q3, Q4, Q5, and Q6is coupled to respective DC bias transistors M4, M5, M6and M7. Although illustrated as field effect transistors, other device types, such as bipolar junction transistors, are also contemplated. Transistors M4, M5, M6and M7each have their gate connected to the gate of transistor M3. The current source Iprog, which may be a fixed or programmable current source, is connected with the drain of transistor M3and with the gates of each of transistors M3, M4, M5, M6and M7. Each of transistors M4through M7sets the DC bias current necessary to operate transistors Q3through Q6, respectively.

In addition to acting as the biasing circuitry for transistors Q4, Q5, transistors M5, M6are also arranged to act as a current driver for a load RL. To achieve this, the output Vop1of transistor Q3, which shares the same input signal Vpat its base with transistor Q4, is capacitively coupled to the gate of transistor M6. The drain of M6is coupled with the emitter of transistor Q5. Similarly, the emitter of transistor Q6, where transistors Q6and Q5share the same base input of Vm, is capacitively coupled to the gate of transistor M5. The drain of transistor M5is coupled with the emitter of Q4.

In operation, transistors Q4and Q5function as emitter followers and transistors M5and M6function to minimize transconductance variance in transistors Q4and Q5by shifting the burden of driving the load RLin response to changes at the input terminals Vpand Vmto transistors M5and M6. Assuming a sinusoidal input signal applied at the positive and negative input terminals Vp, Vm, and a load RLconnected across the output terminals Vop, Vom, the driver circuit300functions as described below. As the positive input terminal Vpgoes high and negative input terminal Vmgoes low, load current ILgoes high. Transistor Q4pushes current to load RLat output terminal Vopwhile transistor M6pulls current from the load at the negative output terminal Vom. This will result in Ip2going low and Im2going high to compensate for variations in IL. At the same time, Vgmwill follow Vpgoing high and Vgpwill follow Vmgoing low. Conversely, when the negative input terminal Vmgoes high and positive input terminal Vpgoes low, load current ILgoes low. In this instance, transistor Q5pushes current to the load via output terminal Vomand transistor M5pulls current from the load RLvia output terminal Vop. This will result in Ip2going high and Im2going low to compensate for variations in L. At the same time Vgmwill follow Vpgoing low and Vgpwill follow Vmgoing high. The compensation of ILby Ip2and Im2helps to minimize variations in Ip1and Im1and thus maintain a more constant transconductance in transistors Q4and Q5. Q4and Q5are preferably not turned off at any time during operation. As the current through transistors M5and M6varies, it may reach low enough levels that M5and/or M6are in a near off state. Although the driver circuit may operate in instances where M5and/or M6turn off during operation, it is preferred that M5and M6are biased such that they do not completely turn off. In the event that M5and/or M6turn off at some point during operation, it may take more time for these transistors to recover.

Using the arrangement of combination bias and drive transistors M5and M6, a pair of separate current loops may be defined through the load RL. The first loop, through output transistors Q4and Q5, may be defined by the relationship (Vop−Vom)/RL. A second current loop through the combination drive and bias transistors M5and M6may be defined by the relation (Vgm−Vgp)/2RE, where Vgmis the gate voltage of transistor M6, Vgpis the gate voltage of transistor M5and REis the value of the resistor connected to the source of transmitters M5and the source of transistor M6. In this example, it is assumed that resistors REPand REmare equal in value. Recognizing that the two current loops, one through the output transistor Q4and RL, and output transistor Q5and a second loop defined through REp, transistor M5, RL, transistor M6and REm, must be equal, the following relationship may be developed:

Vop-VomRL=Vgm-Vgp2⁢RE.
Assuming that the source voltage at M5and M6(VREpand VREm, respectively) equals the difference between Vgmand Vgp, then the difference between the output voltages at the emitters of transistors Q3and Q6(Vop1and Vom1) may be said to equal Vop−Vom. Thus Vop−Vomequals Vgm−Vgpand RL=2RE. Accordingly, the bias transistors M5and M6may be biased such that variations in the load current ILwill be accommodated by increases or decreases in Ip2and Im2, the current through transistors M5and M6, rather than by changes in Ip1, or Im1, the current through transistors Q3and Q4by selecting the value of resistors REPand REmto have a combined value substantially equal to that of the expected load RL.

If currents Ip2and Im2respond to changes at the input terminals Vpand Vm, such that an increase of ILwill cause a proportional drop in Ip2and an increase in Im2, then any change in current through output transistors Q4and Q5is minimized, and ideally equal to zero. It then follows that a substantially constant Ip1and Im1would yield a modulation index closer to 1 such that distortion is substantially lower. An idealized relationship of the voltage at the input terminals Vp, Vmand the corresponding swings in current through the combination drive and bias transistors M5and M6(Ip2and Im2) is illustrated inFIG. 4. Here, ideally, Ip1and Im1are essentially constant so that the transconductance, and therefore output impedance, of Q4and Q5is constant. Not only should distortion be reduced, but a substantially constant output impedance may be achieved.

In other embodiments, the transistors M3through M7may be the same type of transistors as that used in transistors Q3through Q6. Additionally, in another variation, where the specific load RLmay not be known in advance, the source resistors REp, REmof transistors M5and M6may be programmable impedance networks such as resistor networks. Programmable impedance networks may allow for the differential driver circuit300to be adapted for use with various loads or may be adjusted to compensate for minor mismatches between the load RLand variations in the differential driver circuit300itself. Although the various transistors inFIG. 3are illustrated as bipolar junction transistors and field effect transistors, any bipolar junction transistor may be substituted with a field effect transistor and any field effect transistor may be substituted with a bipolar junction transistor. For example, one or all of the bipolar transistors illustrated for Q3-Q6may be replaced with MOSFET devices.

Also, the differential driver300may be implemented without transistors Q3and Q6. In this variation of the differential driver circuit300of FIG.3, the gates of M6and M5would be capacitively coupled directly to input terminals Vpand Vm, respectively. Transistors Q3and Q6may be helpful if the differential input signal at input terminals Vpand Vmare too weak to drive transistors M6and M5without assistance, and can help to compensate for the phase delay at Vopand Vomcaused by transistors Q4and Q5. However, transistors Q3and Q6may be omitted and a similar reduction in distortion achieved. In this variation of the differential driver300ofFIG. 3where Q3and Q6are omitted, DC bias current devices M4and M7are also omitted, and may further reduce power consumption.

In yet other embodiments, it is contemplated that the combined utilization of transistors M5and M6for both DC biasing the output transistors Q4and Q5, as well as driving current to the load RLin response to changes in Vpand Vm, may be divided out into separate functional circuits. As seen in the differential driver circuit500ofFIG. 5, the devices driving the load RL, here Q11and Q12are arranged as the output load current driving devices, with transistors M8-M11, providing DC bias to each of the each of transistors Q7through Q12. Although transistors Q7-Q12are illustrated as bipolar junction transistors, while transistors M8-M11are shown as the field effect transistors, bipolar junction transistors may be substituted for any of the field effect transistors M8-M11and field effect transistors may be used in place of any of the bipolar junction transistors Q7-Q12. For example, one or all of the bipolar junction transistors illustrated for Q7-Q12may be replaced with MOSFET devices.

As shown in the differential driver circuit500ofFIG. 5, the load current driving circuitry of Q11and Q12is DC coupled to the input terminals Vp, Vmvia transistors Q7and Q10, respectively. This differs from the AC coupled transistors M5and M6in the example ofFIG. 3and allows differential driver circuit500to act as a truly push-pull unity buffer. In one embodiment, the transconductance of output transistor Q8and load current drive transistor Q11, and similarly output transistor Q9and load current transistor Q12, are matched. Similar to the differential driver circuit300ofFIG. 3, the differential driver circuit500inFIG. 5may be optimized to reduce or eliminate variations in current through transistors Q8and Q9by providing loads REp, REmto each of the emitters of driver transistors Q11and Q12so that the sum of the emitter resistors REp, REmequals the load resistance RL.

Also, in the same manner as discussed with reference to the differential driver300, the differential driver500illustrated inFIG. 5may be implemented without transistors Q7and Q10. In this variation of the differential driver circuit500ofFIG. 5, the bases of Q12and Q11would be DC coupled directly to input terminals Vpand Vm, respectively. Transistors Q7and Q10may be helpful if the differential input signal at input terminals Vpand Vmare too weak to directly drive Q12and Q11without assistance, and can help to compensate for the phase delay at Vopand Vomcaused by transistors Q8and Q9. However, transistors Q7and Q10may be omitted and a similar reduction in distortion achieved. In this variation of the differential driver500ofFIG. 5where Q7and Q10are omitted, DC bias current devices M8and M10are also omitted, and may further reduce power consumption.

An alternative embodiment of a differential driver circuit600is illustrated inFIG. 6. In this embodiment, only field effect transistors, M12-M22, are used throughout the circuit600. Also, rather than using the drive transistors M16and M17to provide both the drive and bias current, as was the case with the combination bias and drive transistors M5and M6inFIG. 3, separate bias transistors M20and M21help control bias current. Furthermore, using the same analysis described above, a single resistor, RB, may be used rather than separate resistors REpand REmshown in the examples ofFIGS. 3 and 5. RBis preferably selected to have the same value as the expected load RLso that variations in input signals Vpand Vm, and variations in the load current ILmay be compensated for by drive transistors M16and M17. Also, RBmay be a variable resistor to permit adjustment for fine tuning or to permit for versatility in application of the driver circuit to a range of loads. In yet another embodiment, the differential driver circuit600may be configured without an internal impedance RBand, instead, include terminals to receive an external resistance or complex impedance for RB. With an external RB, a user may have the ability to emulate a more exact match between RBand RLby, for example, using a dummy load as RB. Similarly, one or both of REpand REmin the differential drivers300,500ofFIGS. 3 and 5may be externally connected rather than internally provided, such that the sum of REpand REmmay be more closely matched to RL.

While the differential driver circuits300,500,600ofFIGS. 3,5and6illustrate a load between outputs Vopand Vomas resistive, such as RLshown inFIGS. 3,5and6, the load may instead be a complex impedance having capacitive and/or inductive elements. Just as the above calculation of a load current loop through the driving devices Q11, Q12(FIG. 5) or M5, M6(FIG. 3) shows the relationship of the bias resistors REp, REmto a load RL, a complex load may be driven in the same manner. More specifically, the differential driver circuits300,500ofFIGS. 3 and 5may provide the same low power/low distortion features to a complex load by substituting complex bias impedances for the resistive bias REp, REm. Similarly, the single bias resistor RBofFIG. 6may be replaced with a complex impedance matched to the complex impedance of a load RL. Referring to the embodiment ofFIG. 3, although the combination bias/load current driver transistors M5, M6would need complex impedance bias, the remaining DC bias devices M3, M4and M7would not require complex impedance compensation (e.g. capacitive and/or inductive elements) as the DC bias current should not be affected by the complex load on the outputs Vop, Vom.

It is contemplated that the differential driver circuits described above may be implemented in any of a number of electronic devices to reduce distortion and power consumption. The differential driver circuits may be integrated in such electronic devices to drive internal loads or loads external to the electronic device. By implementing programmable bias loads REp, REm, or a single programmable bias load RB, for the load current drive devices (again, as described above, these bias loads may be complex bias loads), as well as a programmable current source Iprog, it is contemplated that a multipurpose integrated or discrete differential driver assembly may be fabricated. Such a programmable differential driver may be produced as an integrated circuit package that may be used for a number of different devices, and that may provide for implementation in devices having user adjustable modes that allow for switching between types of expected loads.

Examples of electronic devices where the differential driver described above may be utilized are illustrated in.FIGS. 7A-7G. As shown inFIG. 7A, the present invention can be implemented in a hard disk drive (HDD)700. The present invention may be implemented in either or both of the signal processing and/or control circuits, which are generally identified inFIG. 7Aat702. Another implementation of the low power/low distortion driver circuit in the HDD is in the magnetic sensor or read/write head associated with the magnetic storage medium706. In some implementations, the signal processing and/or control circuit702and/or other circuits within which the above described driver circuit is integrated (not shown) in the HDD700may process data, perform coding and/or encryption, perform calculations, and/or format data that is output to and/or received from a magnetic storage medium706.

The HDD700may communicate with a host device (not shown) such as a computer, mobile computing devices such as personal digital assistants, cellular phones, media or MP3 players and the like, and/or other devices via one or more wired or wireless communication links708. The HDD700may be connected to memory709such as random access memory (RAM), low latency nonvolatile memory such as flash memory, read only memory (ROM) and/or other suitable electronic data storage.

Referring now toFIG. 7B, the present invention can be implemented in a digital versatile disc (DVD) drive710. The present invention may implement and/or be implemented in either or both signal processing and/or control circuits, which are generally identified inFIG. 7Bat712, and/or mass data storage718of the DVD drive710. The signal processing and/or control circuit712and/or other circuits (not shown) in the DVD drive710may process data, perform coding and/or encryption, perform calculations, and/or format data that is read from and/or data written to an optical storage medium716. The differential driver circuits disclosed herein may be integrated into one or more components of the DVD drive710to handle various tasks such as buffering digital clock signals. In some implementations, the signal processing and/or control circuit712and/or other circuits (not shown) in the DVD drive710can also perform other functions such as encoding and/or decoding and/or any other signal processing functions associated with a DVD drive.

The DVD drive710may communicate with an output device (not shown) such as a computer, television or other device via one or more wired or wireless communication links717. The DVD drive710may communicate with mass data storage718that stores data in a nonvolatile manner. The mass data storage718may include a hard disk drive (HDD). The HDD may have the configuration shown inFIG. 7A. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The DVD drive710may be connected to memory719such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.

Referring now toFIG. 7C, the present invention can be implemented in a high definition television (HDTV)720. The present invention may implement and/or be implemented in either or both signal processing and/or control circuits, which are generally identified inFIG. 7Eat722. The HDTV720receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display726. The driver circuits described above may be part of buffered multiplexers integrated into the HDTV720for video applications, such as those needed when multiplexing signals from two video sources. In some other implementations, signal processing circuit and/or control circuit722and/or other circuits integrating driver circuits of the type described above (not shown) may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required.

The HDTV720may communicate with mass data storage727that stores data in a nonvolatile manner such as in optical and/or magnetic storage devices, for example a hard disk drive (HDD). At least one HDD may have the configuration shown inFIG. 7Aand/or at least one DVD may have the configuration shown inFIG. 7B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″The HDTV720may be connected to memory728such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The HDTV720also may support connections with a WLAN via a WLAN network interface729.

Referring now toFIG. 7D, the present invention may implement and/or be implemented in a control system of a vehicle730, a WLAN interface748, mass data storage746of the vehicle control system and/or a power supply733. In some implementations, the differential driver circuits described herein may be implemented in a powertrain control system732to buffer signals in or from one or more sensors such as temperature sensors, pressure sensors, rotational sensors, airflow sensors and/or any other suitable sensors and/or that generates one or more output control signals such as engine operating parameters, transmission operating parameters, and/or other control signals.

The present invention may also be implemented in other control systems740of the vehicle730. The control system740may likewise receive signals from input sensors742and/or output control signals to one or more output devices744. In some implementations, the control system740may be part of an anti-lock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc and the like. Each of these systems, or communication links between the systems, may integrate the differential driver circuitry described above to handle internal or external loads. Still other implementations are contemplated.

The powertrain control system732may communicate with mass data storage746that stores data in a nonvolatile manner. The mass data storage746may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown inFIG. 7Aand/or at least one DVD may have the configuration shown inFIG. 7B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″The powertrain control system732may be connected to memory747such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The powertrain control system732also may support connections with a WLAN via a WLAN network interface748. The control system740may also include mass data storage, memory and/or a WLAN interface (all not shown).

Referring now toFIG. 7E, the present invention can be implemented in a cellular phone750that may include a cellular antenna751. Because of the lower power consumption aspect of the differential driver circuits discussed herein, they may be particularly well-suited to battery powered devices such as cell phones. The disclosed differential driver may be implemented in either or both signal processing and/or control circuits, which are generally identified inFIG. 7Eat752, a WLAN interface768, and/or mass data storage764of the cellular phone750. In some implementations, the cellular phone750includes a microphone756, an audio output758such as a speaker and/or audio output jack, a display760and/or an input device762such as a keypad, pointing device, voice actuation and/or other input device incorporating the driver circuitry. The signal processing and/or control circuits752and/or other circuits (not shown) in the cellular phone750may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular phone functions.

The cellular phone750may communicate with mass data storage764that stores data in a nonvolatile manner such as optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown inFIG. 7Aand/or at least one DVD may have the configuration shown inFIG. 7B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″The cellular phone750may be connected to memory766such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The cellular phone750also may support connections with a WLAN via a WLAN network interface768.

Referring now toFIG. 7F, the present invention can be implemented in a set top box780. The differential driver discussed above may be implemented in either or both of the signal processing and/or control circuits, which are generally identified inFIG. 7Fat784, a WLAN interface796, and/or a mass data storage790of the set top box780. The set top box780receives signals from a source such as a broadband source and may output standard and/or high definition audio/video signals, via differential driver circuits integrated in the set top box780, suitable for a display788such as a television and/or monitor and/or other video and/or audio output devices. The signal processing and/or control circuits784and/or other circuits (not shown) of the set top box780utilizing the differential driver circuitry may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function.

The set top box780may communicate with mass data storage790that stores data in a nonvolatile manner. The mass data storage790may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown inFIG. 7Aand/or at least one DVD may have the configuration shown inFIG. 7B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″The set top box780may be connected to memory794such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The set top box780also may support connections with a WLAN via a WLAN network interface796.

Referring now toFIG. 7G, the disclosed differential driver may also be implemented in a media player800. The differential driver may be implemented in either or both of the signal processing and/or control circuits, which are generally identified inFIG. 7Gat804, a WLAN interface816, and/or a mass data storage810of the media player800. In some implementations, the media player800includes a display807and/or a user input808such as a keypad, touchpad and the like integrating one or more differential driver circuits as discussed above. In some implementations, the media player800may employ a graphical user interface (GUI) that typically employs menus, drop down menus, icons and/or a point-and-click interface via the display807and/or user input808. The media player800further includes an audio output809such as a speaker and/or audio output jack. The signal processing and/or control circuits804and/or other circuits (not shown) of the media player800may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function.

The media player800may communicate with mass data storage810that stores data such as compressed audio and/or video content in a nonvolatile manner. In some implementations, the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats. The mass data storage may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown inFIG. 7Aand/or at least one DVD may have the configuration shown inFIG. 7B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″The media player800may be connected to memory814such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The media player800also may support connections with a WLAN via a WLAN network interface816. Still other implementations in addition to those described above are contemplated.

It is intended that the foregoing detailed description be understood as an illustration of selected forms that the invention can take and not as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of this invention.