There is provided a circuit capable of speeding up a signal that has a positive slope, dv/dt>0. The circuit detects or senses the slope, amplifies the slope and feeds back a signal to enforce the pull up of the positive going signal. The circuit is also capable of handling complementary signals and when the positive going signal is being pulled up its complement is pulled down. The positive going signal is capacitively coupled into the circuit.

This invention relates, in general, to speed-up circuits, and more 
particularly, to those speed-up circuit useful in speeding up bit sense 
signals in digital memories. 
It is often desirable to speed-up the transition of a signal, especially, 
in high density integrated circuits such as random access memories (RAM). 
As the number of components on an integrated circuit chip increases, the 
capacitance of lines on the integrated circuit also increases. The 
capacitance on the lines tends to reduce the speed of the circuit by 
causing the signals on the lines to take longer to change voltage levels. 
On most static RAMs a pair of bit sense lines come from the array of 
storage cells through a column decoder to bit sense column (BSC and BSC) 
lines. This pair of lines then goes to a sense amplifier which drives an 
output section. Voltage transitions on these BSC lines typically move very 
slowly due to the capacitance associated with the line. The signal on the 
BSC lines are complements of each other and must cross over before the 
sense amplifier can detect a change in voltage level of the signals on the 
BSC lines. 
Many different high gain differential amplifiers could be used to detect 
the crossing of BSC and BSC, however, the amplifier cannot start to 
generate a new output until after the BSC and BSC signals have crossed 
each other or at least approached each other quite closely. If a signal 
could be generated that could detect the start of the transition of the 
signal on the BSC lines, the operating speed of RAMs and/or ROM could be 
made much faster. 
Accordingly, it is an object of the present invention to provide a circuit 
for speeding up the transition of a signal. 
Another object of the present invention is to provide a speed-up circuit 
useful in digital memories for faster sensing of signals. 
SUMMARY OF THE INVENTION 
In carrying out the above and other objects and advantages of the present 
invention, there is provided a speed-up circuit useful for speeding up the 
transition of a signal. Means are provided for sensing a transition of a 
signal and for providing an output indicative of the transition. 
Capacitive means are used for coupling the transition from a line carrying 
the transition to the means for sensing. The output of the means for 
sensing is amplified through an amplifier and fed back to the line 
carrying the transition to reinforce the transition and thereby speed up 
the transition. 
The present invention is particularly useful for speeding the transition of 
BSC and BSC signals on bit sense column lines. 
The subject matter which is regarded as the invention is set forth in the 
appended claims. The invention itself, however, together with further 
objects and advantages thereof, may be better understood by referring to 
the following detailed description taken in conjunction with the 
accompanying drawings.

DETAILED DESCRIPTION OF THE DRAWINGS 
The present invention is illustrated in FIG. 1 as speeding up the 
transition of two complementary signals, BSC and BSC which are 
capacitively coupled into the speed-up circuit by capacitor 10 and 
capacitor 11, respectively. Capacitors 10 and 11 are preferably depletion 
type capacitors. The BSC signal is coupled by capacitor 10 to node 12, 
which is connected to a gate electrode of transistor 18. Transistor 18 is 
in series with a depletion type transistor 19. Transistors 18 and 19 serve 
as sensors for sensing a positive transition of the BSC signal and 
providing an output at node 13. There are three transistors 15, 16, and 17 
in parallel with each other between nodes 12 and 13. Transistor 15 has its 
gate electrode connected to voltage terminal V.sub.DD, which will enable 
transistor 15, thereby maintaining nodes 12 and 13 at the same potential 
when transistors 18 and 19 are in a non-sensing state. Node 13 is coupled 
to a gate electrode of transistor 21. Series connected transistors 21 and 
22 serve as amplifiers for amplifying a signal at node 13 and provide an 
output at node 23. Transistor 22 is a depletion type transistor having its 
gate electrode connected to its source electrode forming node 23. The 
drain electrode of transistor 22 is coupled to voltage potential terminal 
V.sub.DD, and the source electrode of transistor 21 is coupled to voltage 
potential terminal V.sub.SS. Node 23 is connected to the gate electrode of 
depletion type transistor 25, to the gate electrode of transistor 17, to 
the gate electrode of transistor 35, and to the gate electrode of 
transistors 27 and 28. Transistor 25 has its drain electrode connected to 
a load device illustrated as transistor 26. Transistor 26 has its gate and 
drain electrodes coupled to voltage terminal V.sub.DD. The source of 
transistor 25 is connected back to the same line carrying the input signal 
BSC. 
Transistors 27 and 28 are in series between voltage potential terminal 
V.sub.SS and the BSC input line. Transistor 29 serves as a threshold 
adjust device and has its gate electrode connected to the drain electrode 
of transistor 28, its source electrode connected to the source electrode 
of transistor 28, and its drain electrode connected to voltage terminal 
V.sub.DD. 
When a transition on input line BSC starts to go positive, capacitor 10 
couples the positive transition to node 12 which is connected to the gate 
electrode of transistor 18. Transistor 18 is enabled thereby driving node 
13 low, towards voltage potential V.sub.SS. As node 13 goes low, 
transistor 21 is disabled so that node 23 goes high. As node 23 goes high, 
transistor 17 is enabled thereby equalizing nodes 12 and 13, and bringing 
the circuit back to its stable operating point. Node 23 is also coupled to 
the gate electrode of depletion type transistor 25, and as node 23 goes 
high conduction of transistor 25 increases thereby applying the positive 
voltage from transistor 26 to input signal line BSC. As node 23 goes high 
transistors 27 and 28 are also enabled thereby driving the BSC signal line 
low. In summary, as capacitor 10 couples a positive going transition from 
BSC into the speed-up circuit, feedback transistor 25 becomes enabled 
thereby reinforcing the BSC signal by positive voltage while at the same 
time transistors 27 and 28 become enabled thereby reinforcing BSC with a 
low voltage. 
The remaining portion of the circuitry of FIG. 1 monitors the BSC signal 
for positive transitions. The line carrying BSC is coupled by capacitor 11 
to node 31. Node 31 is coupled to the gate electrode of transistor 37. 
Transistors 37 and 38 are in series between voltage terminal V.sub.SS and 
voltage terminal V.sub.DD and serve as means for sensing a positive 
transition of BSC. Transistor 38 is a depletion type transistor having its 
gate electrode connected to its source electrode at node 32. Three 
transistors 33, 34, and 35 are in parallel between nodes 31 and 32. 
Transistor 33 has its gate electrode connected to voltage terminal 
V.sub.DD and serves to equalize the potential between nodes 31 and 32 when 
transistors 37 and 38 are in a non-amplifying or non-sensing state. The 
gate electrode of transistor 35 is connected to node 23 and will become 
conductive when node 23 goes high. The purpose of transistor 35 is to 
equalize nodes 31 and 32 when node 23 is going high which means that BSC 
is experiencing a positive transition. Transistors 40 and 41, which are 
connected in series between voltage terminal V.sub.SS and voltage terminal 
V.sub.DD, serve as an amplifier to amplify a signal at node 32. Node 32 is 
connected to the gate electrode of transistor 40, and depletion type 
transistor 41 has its gate electrode connected to its source electrode 
forming node 42. Node 42 is connected to the gate electrodes of 
transistors 34 and 16, the gate electrode of transistor 43, and the gate 
electrodes of transistors 45 and 46. As node 42 goes positive, in response 
to a positive going transition of BSC, transistor 34 is enabled thereby 
equalizing nodes 31 and 32 and transistor 16 is enabled thereby equalizing 
nodes 12 and 13. When transistors 16, 34 or 17, 35 are enabled, the whole 
circuit is brought back to its stable operating point thereby making the 
circuit ready for any more transitions of BSC or BSC. 
As node 42 goes positive, depletion type transistor 43 is enabled thereby 
supplying a positive going pulse to the BSC line. Transistor 43 is 
supplied a positive voltage from its load device 26. Load device 26 along 
with transistor 25 form a feedback means for the BSC line while transistor 
26 and transistor 43 form a feedback means for the BSC line. As node 42 
goes high, transistors 45 and 46 are enabled thereby coupling the 
potential from terminal V.sub.SS to the BSC line thereby speeding up the 
decline of the signal on the BSC line. Transistor 47 has its source 
connected to the source of transistor 46, and its gate electrode connected 
to the drain electrode of transistor 46 and serves as a threshold adjust 
device for transistor 46. The drain electrode of transistor 47 is coupled 
to voltage terminal V.sub.DD. 
The operation of the speed-up circuit coupled by capacitor 11 to the BSC 
line is the same as the speed-up circuit coupled to the BSC line by 
capacitor 10. Capacitor 11 will couple a positive going transition from 
the BSC line to node 31 where it is sensed and amplified by transistors 37 
and 38 and provides an output at node 32. The output from node 32 is 
amplified by transistors 40 and 41 and coupled by feedback means 43 to the 
BSC line to reinforce the BSC signal by positive voltage. At the same time 
transistors 45 and 46 reinforce the BSC signal by a low voltage. 
The benefits derived from the circuit of FIG. 1 are graphically illustrated 
in the voltage versus time graph of FIG. 2. The solid BSC and BSC lines 
illustrate the normal crossover response of these signals without the 
benefit of the present invention. The dotted portion of the BSC and BSC 
lines illustrates the sharper crossover transition of the signals in 
response to the assistance of the present speed-up circuit. Note that the 
earlier crossover results in increased operating speed of the circuit. The 
crossover transition is sharper and occurs .DELTA.T sooner. 
By now it should be appreciated that there has been provided a speed-up 
circuit which responds to an input signal having a positive slope, dv/dt 
&gt;0. When the slope is detected it is amplified and fed back to reinforce 
the pullup of the positive going signal. The circuit also has the 
capability of pulling down a signal which is a complement to the signal 
having the positive slope. Although the circuit has been illustrated as 
having a specific application for speeding up complementary BSC and BSC 
signals associated with digital memories it will be appreciated that the 
circuit is capable of speeding up any slow responding signal undergoing a 
voltage transition. However, the gain of the feedback loop must be chosen 
such that noise will not trip the circuit, yet, sensitive enough to trip 
when BSC or BSC is changing. The feedback pulldown of the opposite BSC 
line must be made such that if BSC is rising BSC is not pulled down so far 
that after the circuit resets itself, the BSC line rises and trips the 
opposite reaction.