DISPLAY APPARATUS

A display apparatus includes a first display element including a first pixel electrode and emitting light of a first color, a first conductive pattern layer and a second conductive pattern layer extending in a first direction and spaced apart from each other, and a first connection pattern layer extending in the first direction and electrically connecting the first conductive pattern layer to the second conductive pattern layer, the first connection pattern layer at least partially overlapping the first pixel electrode of the first display element, wherein the first conductive pattern layer and the second conductive pattern layer are disposed on a same layer between the first display element and the first connection pattern layer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to and benefits of Korean Patent Application No. 10-2022-0174196, under 35 U.S.C. § 119, filed on Dec. 13, 2022, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

One or more embodiments relate to a display apparatus.

2. Description of the Related Art

Display apparatuses display images based on data. A display apparatus is used as a screen for a small product such as a mobile phone or is used as a screen for a large product such as a television.

A display apparatus includes pixels that emit light by receiving an electrical signal to display an image to the outside. Each pixel includes a display element. For example, an organic light-emitting display apparatus includes an organic light-emitting diode (OLED) as a display element. In an organic light-emitting display apparatus, a thin-film transistor and an OLED are formed on a substrate, and the OLED emits light by itself.

As display apparatuses have recently been used for various purposes, various designs have been developed to improve the quality of display apparatuses.

SUMMARY

One or more embodiments include a display apparatus capable of preventing or minimizing stains from occurring in a display area.

According to one or more embodiments, a display apparatus may include a first display element including a first pixel electrode and that emits light of a first color, a first conductive pattern layer and a second conductive pattern layer extending in a first direction and spaced apart from each other, and a first connection pattern layer extending in the first direction and electrically connecting the first conductive pattern layer to the second conductive pattern layer, the first connection pattern layer at least partially overlapping the first pixel electrode of the first display element, wherein the first conductive pattern layer and the second conductive pattern layer may be disposed on a same layer between the first display element and the first connection pattern layer.

The display apparatus may further include a first data line that transmits a first data voltage, the first data line including the first conductive pattern layer, the second conductive pattern layer, and the first connection pattern layer, and a first pixel circuit electrically connected to the first data line and that receives the first data voltage through the first data line and drives the first display element.

The first display element may include a first emission area that emits light of the first color, and in a plan view, the first pixel circuit and the first emission area of the first display element may be spaced apart from each other.

The display apparatus may further include a second display element including a second emission area and a second pixel electrode, the second emission area that emits light of a second color different from the first color, a second data line that transmits a second data voltage, the second data line including a third conductive pattern layer extending in the first direction, a fourth conductive pattern layer extending in the first direction and being spaced apart from the third conductive pattern layer, and a second connection pattern layer extending in the first direction, electrically connecting the third conductive pattern layer to the fourth conductive pattern layer, and at least partially overlapping the second pixel electrode of the second display element, and a second pixel circuit electrically connected to the second data line and that receives the second data voltage and drives the second display element, wherein the third conductive pattern layer and the fourth conductive pattern layer may be disposed on a same layer between the second display element and the second connection pattern layer, wherein, in a plan view, the second pixel circuit and the second emission area of the second display element may at least partially overlap each other.

The second pixel electrode of the second display element may include a first electrode portion and a second electrode portion, and a third electrode portion, wherein the first electrode portion and the second electrode portion may extend in the first direction and spaced apart from each other with the second data line between the first electrode portion and the second electrode portion, and the third electrode portion may electrically connect the first electrode portion to the second electrode portion and may at least partially overlap the second connection pattern layer.

The second emission area of the second display element may include a first light-emitting portion overlapping the first electrode portion in a plan view and a second light-emitting portion overlapping the second electrode portion in a plan view, wherein the first light-emitting portion overlaps the first pixel circuit in a plan view, and the second light-emitting portion may overlap the second pixel circuit in a plan view.

The third electrode portion may electrically connect an end portion of the first electrode portion to an end portion of the second electrode portion.

The third electrode portion may electrically connect a central portion of the first electrode portion to a central portion of the second electrode portion.

The display apparatus may further include a first shield electrode at least partially overlapping the first connection pattern layer, and a second shield electrode at least partially overlapping the second connection pattern layer, wherein the first shield electrode, the first conductive pattern layer, and the second conductive pattern layer may be disposed on a same layer, and the second shield electrode, the third conductive pattern layer, and the fourth conductive pattern layer may be disposed on a same layer.

The display apparatus may further include a first conductive line that transmits a first voltage, the first conductive line extending in the first direction, and a second conductive line that transmits a second voltage, the second conductive line extending in the first direction, wherein the first shield electrode may extend from the first conductive line in a second direction intersecting the first direction, and the second shield electrode may extend from the second conductive line in the second direction.

The first voltage and the second voltage may be different from each other.

The first pixel circuit may include a first transistor that controls a magnitude of a driving current flowing through the first display element, a second transistor that transmits the first data voltage to the first transistor in response to a first scan signal, and a third transistor that transmits an initialization voltage to the first pixel electrode of the first display element in response to a second scan signal, wherein a frequency of the first scan signal may be different from a frequency of the second scan signal.

The frequency of the second scan signal may be higher than the frequency of the first scan signal.

In a plan view, the first conductive pattern layer and the second conductive pattern layer may be spaced apart from the first pixel electrode of the first display element.

The display apparatus may further include a shield electrode that transmits a voltage, and at least partially overlaps the first connection pattern layer, wherein the shield electrode, the first conductive pattern layer, and the second conductive pattern layer may be disposed on a same layer.

The display apparatus may further include a conductive line that transmits the voltage, the conductive line extending in the first direction, wherein the shield electrode may extend from the conductive line in a second direction intersecting the first direction, and the shield electrode and the conductive line may be integral with each other.

According to one or more embodiments, a display apparatus may include a data line including a first conductive pattern layer extend in a first direction, a second conductive pattern layer extend in the first direction and spaced apart from the first conductive pattern layer, and a connection pattern layer extending in the first direction and electrically connecting the first conductive pattern layer to the second conductive pattern layer, and a pixel electrode including a first electrode portion and a second electrode portion spaced apart from each other with the data line between the first electrode portion and the second electrode portion, and a third electrode portion electrically connecting the first electrode portion to the second electrode portion and at least partially overlapping the connection pattern layer, wherein the first conductive pattern layer and the second conductive pattern layer may be disposed on a same layer between the pixel electrode and the connection pattern layer.

The display apparatus may further include a display element including the pixel electrode, and a pixel circuit that drives the display element, wherein the pixel circuit may include a first transistor that controls a magnitude of a driving current flowing through the display element, a second transistor that electrically connects the data line to the first transistor in response to a first scan signal, and a third transistor that transmits an initialization voltage to the pixel electrode of the display element in response to a second scan signal, and a frequency of the first scan signal may be different from a frequency of the second scan signal.

The frequency of the second scan signal may be higher than the frequency of the first scan signal.

In a plan view, the pixel circuit may at least partially overlap the first electrode portion or the second electrode portion.

The third electrode portion may electrically connect an end portion of the first electrode portion to an end portion of the second electrode portion.

The third electrode portion may electrically connect a central portion of the first electrode portion to a central portion of the second electrode portion.

In a plan view, the first conductive pattern layer and the second conductive pattern layer may be spaced apart from the pixel electrode.

The display apparatus may further include a shield electrode that transmits a voltage and at least partially overlaps the connection pattern layer.

The display apparatus may further include a conductive line that transmits the voltage, the conductive line extending in the first direction, wherein the shield electrode may extend from the conductive line in a second direction intersecting the first direction, and the shield electrode and the conductive line may be integral with each other.

Other aspects, features, and advantages of the disclosure will become more apparent from the detailed description, the claims, and the drawings.

These general and specific embodiments may be implemented by using a system, a method, a computer program, or a combination thereof.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG.1is a schematic plan view of a display apparatus according to an embodiment.

Referring toFIG.1, a display apparatus1may include a display area DA where an image is displayed and a peripheral area PA surrounding at least a part of the display area DA. The display apparatus1may provide an image to the outside by using light emitted from the display area DA. Because the display apparatus1includes a substrate100, the substrate100may include the display area DA and the peripheral area PA. For example, the display area DA and the peripheral area PA may be defined on the substrate100.

The substrate100may include any of various materials, for example, glass, a metal, or plastic. According to an embodiment, the substrate100may include a flexible material. The flexible material may include a material that is well bendable, foldable, or rollable. The substrate100including the flexible material may include ultra-thin glass, metal, or plastic.

The display area DA may have a rectangular shape as shown inFIG.1. In another example, the display area DA may have a polygonal shape (e.g., a triangular shape, a pentagonal shape, or a hexagonal shape), a circular shape, an elliptical shape, or an irregular shape.

Pixels PX including various display elements such as organic light-emitting diodes (OLEDs) may be positioned in the display area DA of the substrate100. Pixels PX may be provided (or formed), and the pixels PX may be arranged in any of various types such as a stripe type, a PenTile® type, or a mosaic type to form an image. Hereinafter, each pixel PX may include a sub-pixel that emits light of a different color, and may be one of, for example, a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

Although the display apparatus1according to an embodiment is an organic light-emitting display apparatus, the display apparatus is not limited thereto. In another example, the display apparatus1may be an inorganic light-emitting display apparatus or an inorganic electroluminescent (EL) display apparatus, or a quantum dot light-emitting display apparatus. For example, an emission layer of a display element provided in the display apparatus may include an organic material, may include an inorganic material, may include quantum dots, may include an organic material and quantum dots, may include an inorganic material and quantum dots, or may include an organic material, an inorganic material, and quantum dots.

The peripheral area PA of the substrate100positioned (or disposed) around the display area DA may be an area where an image is not displayed. Various wirings for transmitting electric signals to be applied to the display area DA, and pads to which a printed circuit board or a driver integrated circuit (IC) chip is attached may be positioned in the peripheral area PA.

FIG.2is a schematic diagram of an equivalent circuit of a pixel included in the display apparatus ofFIG.1.

Referring toFIG.2, a pixel (or a single pixel) PX may include a pixel circuit PC and a display element electrically connected to the pixel circuit PC. The display element may be an organic light-emitting diode OLED including an anode (or a pixel electrode) and a cathode (or a counter electrode).

For example, the pixel circuit PC may include first to eighth transistors T1to T8and a storage capacitor Cst, as shown inFIG.2. The first to eighth transistors T1to T8and the storage capacitor Cst may be connected (e.g., electrically connected) to first to fourth scan lines GWL, GCL, GIL, and GBL that respectively transmit first to fourth scan signals GW, GC, GI, and GB, a data line DL that transmits a data voltage Dm, an emission control line EML that transmits an emission control signal EM, a power supply line PL that transmits a first driving voltage ELVDD, a first voltage line VL1that transmits a first initialization voltage VINT, a second voltage line VL2that transmits a second initialization voltage VAINT, a third voltage line VL3that transmits a bias voltage VOBS, and a common electrode to which a second driving voltage ELVSS is applied.

The first transistor T1may be a driving transistor in which a magnitude of drain current is determined according to a gate-source voltage, and the second to eighth transistors T2to T8may be switching transistors that are turned on or off according to a gate-source voltage, substantially, a gate voltage. The first to eighth transistors T1to T8may be thin-film transistors.

In an embodiment, some of the first to eighth transistors T1to T8may be provided as n-channel MOSFETs (NMOSs) and the rest may be provided as p-channel MOSFETs (PMOSs). For example, as shown inFIG.2, the third transistor T3and the fourth transistor T4may be provided as NMOSs, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8may be provided as PMOSs.

In another example, the first to eighth transistors T1to T8may be provided as PMOSs. In another example, the first to eighth transistors T1to T8may be provided as NMOSs.

In an embodiment, some semiconductor layers of the first to eighth transistors T1to T8may be formed of low temperature polysilicon (LTPS), and other semiconductor layers may be formed of an oxide semiconductor (e.g., IGZO).

In another example, each of the first to eighth transistors T1to T8may include a semiconductor layer including silicon. For example, each of the first to eighth transistors T1to T8may include a semiconductor layer including LTPS. A polysilicon material may have a high electron mobility (e.g., 100 cm2/Vs or more), and thus may have low energy consumption and excellent reliability.

In another example, semiconductor layers of the first to eighth transistors T1to T8may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layer may be an InSnZnO (ITZO) semiconductor layer or an InGaZnO (IGZO) semiconductor layer.

The storage capacitor Cst may be connected between the power supply line PL and a gate of the first transistor T1. The storage capacitor Cst may include a lower electrode CE1connected to the gate of the first transistor T1and an upper electrode CE2connected to the power supply line PL.

The first transistor T1may control a magnitude of a driving current Id flowing from the power supply line PL to the organic light-emitting diode OLED according to a gate-source voltage. The first transistor T1may include the gate connected to the lower electrode CE1of the storage capacitor Cst, a source S connected to the power supply line PL through the fifth transistor T5, and a drain D connected to the organic light-emitting diode OLED through the sixth transistor T6.

The first transistor T1may output the driving current Id to the organic light-emitting diode OLED according to a gate-source voltage. A magnitude of the driving current Id may be determined based on a difference between a threshold voltage and the gate-source voltage of the first transistor T1. The organic light-emitting diode OLED may receive the driving current Id from the first transistor T1, and may emit light at a luminance according to the magnitude of the driving current Id.

The second transistor T2may connect (e.g., electrically connect) the data line DL to the first transistor T1in response to the first scan signal GW. The second transistor T2may transmit the data voltage Dm to the first transistor T1in response to the first scan signal GW. For example, the second transistor T2may connect (e.g., electrically connect) the data line DL to the source S of the first transistor T1in response to the first scan signal GW. The second transistor T2may transmit the data voltage Dm to the source S of the first transistor T1in response to the first scan signal GW.

The third transistor T3may connect (e.g., electrically connect) the gate and the drain D of the first transistor T1to each other in response to the second scan signal GC. The third transistor T3may be connected in series between the gate and the drain D of the first transistor T1.

The fourth transistor T4may connect (e.g., electrically connect) the first voltage line VL1to the gate of the first transistor T1in response to the third scan signal GI. The fourth transistor T4may transmit the first initialization voltage VINT to the gate of the first transistor T1in response to the third scan signal GI.

The fifth transistor T5may connect (e.g., electrically connect) the power supply line PL to the source S of the first transistor T1in response to the emission control signal EM. The fifth transistor T5may connect (e.g., electrically connect) the power supply line PL to the source S of the first transistor T1in response to the emission control signal EM. The fifth transistor T5may transmit the first driving voltage ELVDD to the source S of the first transistor T1in response to the emission control signal EM.

The sixth transistor T6may connect (e.g., electrically connect) the drain D of the first transistor T1to the anode of the organic light-emitting diode OLED in response to the emission control signal EM. The sixth transistor T6may connect (e.g., electrically connect) the drain D of the first transistor T1to the anode of the organic light-emitting diode OLED in response to the emission control signal EM.

Although the fifth transistor T5and the sixth transistor T6operate in response to the same emission control signal EM inFIG.2, in another example, the fifth transistor T5and the sixth transistor T6may operate in response to different emission control signals.

The seventh transistor T7may connect (e.g., electrically connect) the second voltage line VL2to the anode of the organic light-emitting diode OLED in response to the fourth scan signal GB. The seventh transistor T7may transmit the second initialization voltage VAINT to the anode of the organic light-emitting diode OLED in response to the fourth scan signal GB.

The eighth transistor T8may connect (e.g., electrically connect) the third voltage line VL3to the source S of the first transistor T1in response to the fourth scan signal GB. The eighth transistor T8may transmit the bias voltage VOBS to the source S of the first transistor T1in response to the fourth scan signal GB.

Although the seventh transistor T7and the eighth transistor T8operate in response to the same fourth scan signal GB inFIG.2, in another example, the seventh transistor T7and the eighth transistor T8may operate in response different scan signals.

In an embodiment, a frequency of the first scan signal GW may be different from a frequency of the fourth scan signal GB. For example, a frequency of the fourth scan signal GB may be higher than a frequency of the first scan signal GW. A frequency of the fourth scan signal GB may be twice a frequency of the first scan signal GW.

In an embodiment, the second scan signal GC may be substantially synchronized with the first scan signal GW. The third scan signal GI may be substantially synchronized with the first scan signal GW of a previous row.

Although the pixel circuit PC includes eight transistors and one capacitor inFIG.2, the number of transistors and the number of capacitors included in the pixel circuit PC may be changed. For example, the pixel circuit PC may include seven transistors and one capacitor.

FIG.3is an enlarged schematic plan view of a portion of a display apparatus according to an embodiment.

Referring toFIG.3, the display apparatus1may include first to third pixel circuits PC1. PC2, and PC3, first to third display elements DE1, DE2, and DE3, first to third data lines DL1, DL2, and DL3, first to third connection electrodes1001,1002, and1003, and first to third conductive lines1101,1102, and1103.

The first to third pixel circuits PC1, PC2, and PC3may be electrically connected to the first to third display elements DE1, DE2, and DE3, respectively. The first to third pixel circuits PC1, PC2, and PC3may respectively drive the first to third display elements DE1, DE2, and DE3. For example, the first pixel circuit PC1may be connected (e.g., electrically connected) to the first display element DE1through the first connection electrode1001and a first contact hole cnt1. The second pixel circuit PC2may be connected (e.g., electrically connected) to the second display element DE2through the second connection electrode1002and a second contact hole cnt2. The third pixel circuit PC3may be connected (e.g., electrically connected) to the third display element DE3through the third connection electrode1003and a third contact hole cnt3. The description of the pixel circuit PC ofFIG.2may be applied to the first to third pixel circuits PC1, PC2, and PC3.

The first display element DE1may emit light of a first color and may include a first pixel electrode210a. The second display element DE2may emit light of a second color and may include a second pixel electrode210b. The third display element DE3may emit light of a third color and may include a third pixel electrode210c. The first to third pixel electrodes210a,210b, and210cmay be semi-transmissive electrodes, transmissive electrodes or reflective electrodes. In an embodiment, the first color may be red, the second color may be blue, and the third color may be green.

In an embodiment, the second pixel electrode210bof the second display element DE2may include a first electrode portion210ba, a second electrode portion210bb, and a third electrode portion210bc. The first electrode portion210baand the second electrode portion210bbmay extend in a first direction (e.g., +y-axis direction). The first electrode portion210baand the second electrode portion210bbmay be spaced apart from each other with the second data line DL2therebetween. The third electrode portion210bcmay connect (e.g., electrically connect) the first electrode portion210bato the second electrode portion210bb. The third electrode portion210bcmay connect (e.g., electrically connect) an end portion of the first electrode portion210bato an end portion of the second electrode portion210bb. Because only the third electrode portion210bcoverlaps the second data line DL2, an overlapping ratio (or overlapping size/area) between the second data line DL2and the second pixel electrode210bmay decrease.

Although the third electrode portion210bcconnects an end portion of the first electrode portion210bato an end portion of the second electrode portion210bbinFIG.3, in another example, as shown inFIG.12, the third electrode portion210bcmay connect (e.g., electrically connect) a central portion of the first electrode portion210bato a central portion of the second electrode portion210bb.

The first display element DE1may include a first emission area EA1emitting light of the first color, the second display element DE2may include a second emission area EA2emitting light of the second color, and the third display element DE3may include a third emission area EA3emitting light of the third color. The first emission area EA1may be defined by a first opening OP1through which at least a part of the first pixel electrode210ais exposed. The second emission area EA2may bd defined by a second opening OP2through which at least a part of the second pixel electrode210bis exposed. The third emission area EA3may be defined by a third opening OP3through which at least a part of the third pixel electrode210cis exposed. The first to third openings OP1, OP2, and OP3may be formed in a pixel-defining film125ofFIG.4described below.

In an embodiment, the second emission area EA2of the second display element DE2may include a first light-emitting portion EA2aand a second light-emitting portion EA2b. In a plan view, the first light-emitting portion EA2amay overlap the first electrode portion210ba, and the second light-emitting portion EA2bmay overlap the second electrode portion210bb. The first light-emitting portion EA2amay be defined by a second-first opening OP2athrough which at least a part of the first electrode portion210bais exposed, and the second light-emitting portion EA2bmay be defined by a second-second opening OP2bthrough which at least a part of the second electrode portion210bbis exposed.

In an embodiment, in a plan view, an emission area of a display element may be spaced apart from or at least partially overlap a pixel circuit that drives the display element. For example, as shown inFIG.3, in a plan view, the first emission area EA1of the first display element DE1may be spaced apart from the first pixel circuit PC1. The first emission area EA1of the first display element DE1may not overlap the first pixel circuit PC1. The first emission area EA1of the first display element DE1may overlap the third pixel circuit PC3. The second emission area EA2of the second display element DE2may at least partially overlap the first pixel circuit PC1and the second pixel circuit PC2. The first light-emitting portion EA2aof the second emission area EA2may overlap the first pixel circuit PC1, and the second light-emitting portion EA2bof the second emission area EA2may overlap the second pixel circuit PC2. The third emission area EA3may overlap the third pixel circuit PC3.

Although the first to third display elements DE1, DE2, and DE3are arranged in an s-stripe type inFIG.3, in another example, the first to third display elements DE1, DE2, and DE3may be arranged in any of various types such as a stripe type or a PenTile® type.

The first to third data lines DL1, DL2, and DL3may extend in the first direction (e.g., +y-axis direction). First to third data voltages Dm1, Dm2, and Dm3may be respectively applied to the first to third data lines DL1, DL2, and DL3. The first data line DL1may be connected (e.g., electrically connected) to the first pixel circuit PC1through a fourth contact hole cnt4, the second data line DL2may be connected (e.g., electrically connected) to the second pixel circuit PC2through a fifth contact hole cnt5, and the third data line DL3may be connected (e.g., electrically connected) to the third pixel circuit PC3through a sixth contact hole cnt6. The first pixel circuit PC1may receive the first data voltage Dm1from the first data line DL1, the second pixel circuit PC2may receive the second data voltage Dm2from the second data line DL2, and the third pixel circuit PC3may receive the third data voltage Dm3from the third data line DL3.

In an embodiment, the first data line DL1may include a first conductive pattern layer DL1a, a second conductive pattern layer DL1b, and a first connection pattern layer DL1c. The first conductive pattern layer DL1aand the second conductive pattern layer DL1bmay extend in the first direction (e.g., +y-axis direction) and may be spaced apart from each other. The first connection pattern layer DL1cmay extend in the first direction (e.g., +y-axis direction) to connect (e.g., electrically connect) the first conductive pattern layer DL1ato the second conductive pattern layer DL1b. An end portion of the first connection pattern layer DL1cmay be connected (e.g., electrically connected) to the first conductive pattern layer DL1athrough a seventh contact hole cnt7, and another end portion of the first connection pattern layer DL1cmay be connected (e.g., electrically connected) to the second conductive pattern layer DL1bthrough an eighth contact hole cnt8. In a plan view, the first conductive pattern layer DL1aand the second conductive pattern layer DL1bmay be spaced apart from (or may not overlap) the first pixel electrode210a, and the first connection pattern layer DL1cmay at least partially overlap the first pixel electrode210a.

As described below with reference toFIG.4, the first conductive pattern layer DL1aand the second conductive pattern layer DL1bmay be positioned on the same layer (e.g., sixth insulating layer121) between the first display element DE1and the first connection pattern layer DL1c. The first conductive pattern layer DL1aand the second conductive pattern layer DL1bmay be positioned on the same layer (e.g., sixth insulating layer121) between the first pixel electrode210aand the first connection pattern layer DL1c. For example, a distance between the first data line DL1and the first pixel electrode210amay increase at a portion where the first data line DL1and the first pixel electrode210aoverlap each other. Thus, a capacitance value formed between the first data line DL1and the first pixel electrode210amay decrease.

The first to third pixel circuits PC1, PC2, and PC3and the first to third display elements DE1, DE2, and DE3ofFIG.3may constitute a unit (or a single unit). There may be a plurality of units, and the plurality of units may be arranged in a matrix. The first data line DL1may include the first connection pattern layer DL1coverlapping the first pixel electrode210aof the first display element DE1included in each of the plurality of units. That is, there may be a plurality of first connection pattern layers DL1c, and the plurality of first connection pattern layers DL1cmay be arranged in a matrix.

The first to third conductive lines1101,1102, and1103may extend in the first direction (e.g., +y-axis direction). The first to third conductive lines1101,1102, and1103may transmit preset (or certain) voltages to the first to third pixel circuits PC1, PC2, and PC3. For example, the first driving voltage ELVDD ofFIG.2may be applied to the first conductive line1101. The second driving voltage ELVSS ofFIG.2may be applied to the second conductive line1102. The first initialization voltage VINT, the second initialization voltage VAINT, or the bias voltage VOBS ofFIG.2may be applied to the third conductive line1103.

FIG.4is a cross-sectional view of a pixel electrode and a data line ofFIG.3, taken along line I-I′.FIG.4illustrates the first pixel circuit PC1and the first display element DE1ofFIG.3. AlthoughFIG.4is described based on the first pixel circuit PC1and the first display element DE1, the description may be applied to the second pixel circuit PC2, the third pixel circuit PC3, the second display element DE2, and the third display element DE3ofFIG.3.

Referring toFIG.4, the first pixel circuit PC1may include a first thin-film transistor TFT1, a second thin-film transistor TFT2, and a storage capacitor Cst. The first thin-film transistor TFT1may include a first semiconductor layer Act1and a first gate electrode GE1, the second thin-film transistor TFT2may include a second semiconductor layer Act2and a second gate electrode GE2, and the storage capacitor Cst may include a lower electrode CE1and an upper electrode CE2. The first thin-film transistor TFT1may correspond to the first transistor T1ofFIG.2, and the second thin-film transistor TFT2may correspond to the third transistor T3or the fourth transistor T4ofFIG.2.

The first conductive pattern layer DL1aand the second conductive pattern layer DL1bmay be positioned on the same layer (e.g., sixth insulating layer121) between the first display element DE1and the first connection pattern layer DL1c. The first conductive pattern layer DL1aand the second conductive pattern layer DL1bmay be positioned on the same layer (e.g., sixth insulating layer121) between the first pixel electrode210aand the first connection pattern layer DL1c. For example, a distance d between the first data line DL1and the first pixel electrode210amay increase at a portion where the first data line DL1and the first pixel electrode210aoverlap each other. Thus, a capacitance value formed between the first data line DL1and the first pixel electrode210amay decrease.

Elements included in a display apparatus will be described according to a stacked structure with reference toFIG.4.

The substrate100may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. In case that the substrate100is flexible or bendable, the substrate100may include a polymer resin such as a polyethersulfone (PES), polyacrylate, polyetherimide, polyethylene naphthalate (PEN), polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate100may have a single structure or a multi-layer structure including the above material, and in case that the substrate100has a multi-layer structure, the substrate100may further include an inorganic layer. In some embodiments, the substrate100may have a structure including an organic material, an inorganic material, and an organic material.

A buffer layer110may reduce or block penetration of a foreign material, moisture, or external air from the bottom (or lower surface) of the substrate100, and may planarize the substrate100. The buffer layer110may include an inorganic material such as oxide or nitride, an organic material, or a combination of an organic material and an inorganic material, and may have a single structure or a multi-layer structure including an inorganic material and an organic material.

A barrier layer may be further provided between the substrate100and the buffer layer110. The barrier layer may prevent or minimize penetration of impurities from the substrate100or the like into the first semiconductor layer Act1and the second semiconductor layer Act2. The barrier layer may include an inorganic material such as oxide or nitride, an organic material, or a combination of an organic material and an inorganic material, and may have a single structure or a multi-layer structure including an inorganic material and an organic material.

The first semiconductor layer Act1may be positioned on the buffer layer110. The first semiconductor layer Act1may include amorphous silicon or polysilicon. The first semiconductor layer Act1may include a channel region, and a source region and a drain region positioned on sides (e.g., opposite sides) of the channel region. The source region and the drain region may be regions doped by adding dopants. The first semiconductor layer Act1may have a single structure or a multi-layer structure.

A first insulating layer111and a second insulating layer113may be stacked on the substrate100to cover the first semiconductor layer Act1. Each of the first insulating layer111and the second insulating layer113may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnOX). Zinc oxide (ZnOX) may be zinc oxide (ZnO) and/or zinc peroxide (ZnO2).

The first gate electrode GE1may be positioned on the first insulating layer111. The first gate electrode GE1may at least partially overlap the first semiconductor layer Act1. The first gate electrode GE1may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single structure or a multi-layer structure including the above material. For example, the first gate electrode GE1may have a single-layer structure including Mo.

The upper electrode CE2may be positioned on the second insulating layer113. The upper electrode CE2may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single structure or a multi-layer structure including the above material. For example, the upper electrode CE2may have a single-layer structure including Mo.

In an embodiment, the storage capacitor Cst may include the lower electrode CE1and the upper electrode CE2, and may overlap the first thin-film transistor TFT1as shown inFIG.4. For example, the first gate electrode GE1of the first thin-film transistor TFT1may function as the lower electrode CE1of the storage capacitor Cst. In another example, the storage capacitor Cst may not overlap the first thin-film transistor TFT1and may be separately positioned.

The upper electrode CE2of the storage capacitor Cst may overlap the lower electrode CE1with the second insulating layer113therebetween, to form capacitance. For example, the second insulating layer113may function as a dielectric layer of the storage capacitor Cst.

A third insulating layer115may be positioned on the second insulating layer113to cover the upper electrode CE2. The third insulating layer115may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnOX). Zinc oxide (ZnOX) may be zinc oxide (ZnO) and/or zinc peroxide (ZnO2).

The second semiconductor layer Act2may be positioned on the third insulating layer115. The second semiconductor layer Act2may include an oxide semiconductor material. The second semiconductor layer Act2may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

For example, the second semiconductor layer Act2may be an InSnZnO (ITZO) semiconductor layer or an InGaZnO (IGZO) semiconductor layer. Because an oxide semiconductor has a wide band gap (e.g., about 3.1 eV), a high carrier mobility, and low leakage current, a voltage drop may not be large even in case that a driving time is long. Accordingly, a luminance change due to a voltage drop may not be large even during low-frequency operation.

The second semiconductor layer Act2may include a channel region, and a source region and a drain region positioned on sides (e.g., opposite sides) of the channel region The second semiconductor layer Act2may have a single structure or a multi-layer structure.

A fourth insulating layer117may be positioned on the third insulating layer115to cover the second semiconductor layer Act2. The fourth insulating layer117may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnOX). Zinc oxide (ZnOX) may be zinc oxide (ZnO) and/or zinc peroxide (ZnO2).

Although the fourth insulating layer117is positioned over an entire surface of the substrate100to cover the second semiconductor layer Act2inFIG.4, in another example, the fourth insulating layer117may be patterned to overlap a part of the second semiconductor layer Act2. For example, the fourth insulating layer117may be patterned to overlap the channel region of the second semiconductor layer Act2.

The second gate electrode GE2may be positioned on the fourth insulating layer117. The second gate electrode GE2may at least partially overlap the second semiconductor layer Act2. The second gate electrode GE2may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single structure or a multi-layer structure including the above material. For example, the second gate electrode GE2may have a single-layer structure including Mo.

Although the first thin-film transistor TFT1and the second thin-film transistor TFT2are positioned on different layers inFIG.4, in another example, the first thin-film transistor TFT1and the second thin-film transistor TFT2may be positioned on the same layer. For example, the second semiconductor layer Act2of the second thin-film transistor TFT2may be positioned between the buffer layer110and the first insulating layer111, and the second gate electrode GE2may be positioned between the first insulating layer111and the second insulating layer113. For example, the first semiconductor layer Act1of the first thin-film transistor TFT1and the second semiconductor layer Act2of the second thin-film transistor TFT2may include the same material. In another example, some insulating layers may be omitted.

A fifth insulating layer119may be positioned on the fourth insulating layer117to cover the second gate electrode GE2. The fifth insulating layer119may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnOX). Zinc oxide (ZnOX) may be zinc oxide (ZnO) and/or zinc peroxide (ZnO2).

A fourth connection electrode2001and the first connection pattern layer DL1cmay be positioned on the fifth insulating layer119. Each of the fourth connection electrode2001and the first connection pattern layer DL1cmay include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single structure or a multi-layer structure including the above material. For example, each of the fourth connection electrode2001and the first connection pattern layer DL1cmay have a multi-layer structure including Ti/Al/Ti.

The fourth connection electrode2001may be connected (e.g., electrically connected) to the first semiconductor layer Act1through contact holes formed in the first to fifth insulating layers111,113,115,117, and119. A part of the fourth connection electrode2001may be buried (or filled) in the contact holes, and the fourth connection electrode2001and the first semiconductor layer Act1may be connected (e.g., electrically connected) to each other.

A sixth insulating layer121and a seventh insulating layer123may be stacked on the fifth insulating layer119. Each of the sixth insulating layer121and the seventh insulating layer123may have a single structure or a multi-layer structure including an organic material to provide a flat top surface (or flat upper surface). For example, each of the sixth insulating layer121and the seventh insulating layer123may include benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), a general-purpose polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol-based group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorinated polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

The first connection electrode1001, the first conductive pattern layer DL1a, and the second conductive pattern layer DL1bmay be positioned on the sixth insulating layer121. Each of the first connection electrode1001, the first conductive pattern layer DL1a, and the second conductive pattern layer DL1bmay include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single structure or a multi-layer structure including the above material. For example, each of the first connection electrode1001, the first conductive pattern layer DL1a, and the second conductive pattern layer DL1bmay have a multi-layer structure including Ti/Al/Ti.

The first connection electrode1001may be connected (e.g., electrically connected) to the fourth connection electrode2001through a contact hole formed in the sixth insulating layer121. A part of the first connection electrode1001may be buried (or filled) in the contact hole, and the first connection electrode1001and the fourth connection electrode2001may be connected (e.g., electrically connected) to each other. The first connection electrode1001may be connected (e.g., electrically connected) to the first semiconductor layer Act1through the fourth connection electrode2001.

The first conductive pattern layer DL1amay be connected (e.g., electrically connected) to an end portion of the first connection pattern layer DL1cthrough the seventh contact hole cnt7formed in the sixth insulating layer121. A part of the first conductive pattern layer DL1amay be buried (or filled) in the seventh contact hole cnt7, and the first conductive pattern layer DL1aand the first connection pattern layer DL1cmay be connected (e.g., electrically connected) to each other.

The second conductive pattern layer DL1bmay be connected (e.g., electrically connected) to another end portion of the first connection pattern layer DL1cthrough the eighth contact hole cnt8formed in the sixth insulating layer121. A part of the second conductive pattern layer DL1bmay be buried (or filled) in the eighth contact hole cnt8, and the second conductive pattern layer DL1band the first connection pattern layer DL1cmay be connected (e.g., electrically connected) to each other.

The first display element DE1may be positioned on the seventh insulating layer123. The first display element DE1may include a first pixel electrode210a, an intermediate layer220including an organic emission layer, and a counter electrode230.

The first pixel electrode210amay be a semi-transmissive electrode, a transmissive electrode, or a reflective electrode. In some embodiments, the first pixel electrode210amay include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent electrode layer or a semi-transparent electrode layer formed on the reflective layer. The transparent electrode layer or a semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the first pixel electrode210amay include ITO/Ag/ITO.

The first pixel electrode210amay be connected (e.g., electrically connected) to the first connection electrode1001through the first contact hole cnt1formed in the seventh insulating layer123. A part of the first pixel electrode210amay be buried (or filled) in the first contact hole cnt1, and the first pixel electrode210aand the first connection electrode1001may be connected (e.g., electrically connected) to each other. The first pixel electrode210amay be electrically connected to the first semiconductor layer Act1through the first connection electrode1001and the fourth connection electrode2001.

The pixel-defining film125may be positioned on the seventh insulating layer123. For example, the pixel-defining film125may increase a distance between an edge portion of the first pixel electrode210aand the counter electrode230positioned over the first pixel electrode210a, to prevent an arc or the like from occurring on the edge portion of the first pixel electrode210a.

The pixel-defining film125may be formed of at least one organic insulating material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin by using spin coating or the like. The pixel-defining film125may include an organic insulating material. In another example, the pixel-defining film125may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. In another example, the pixel-defining film125may include an organic insulating material and an inorganic insulating material. In some embodiments, the pixel-defining film125may include a light-blocking material, and may be black. The light-blocking material may include carbon black, carbon nanotubes, a resin or paste including a black dye, metal particles such as nickel, aluminum, molybdenum, or an alloy thereof, metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride). In case that the pixel-defining film125includes a light-blocking material, reflection of external light by metal structures positioned under the pixel-defining film125may be reduced.

The intermediate layer220may be positioned in the first opening OP1formed by the pixel-defining film125. The first opening OP1may define the first emission area EA1of the first display element DE1. The intermediate layer220may include an organic emission layer. The organic emission layer may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic emission layer may be formed of a low-molecular-weight organic material or a high-molecular-weight organic material. A functional layer such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) may be selectively further positioned under or over the organic emission layer.

The intermediate layer220may be positioned to correspond to each of first pixel electrodes210a. However, embodiments are not limited thereto. Various modifications may be made. For example, the intermediate layer220may include an integrated layer over the first pixel electrodes210a.

The counter electrode230may be a light-transmitting electrode or a reflective electrode. In some embodiments, the counter electrode230may be a transparent electrode or a semi-transparent electrode and may include a metal thin film having a low work function including lithium (Li), calcium (Ca), LiF/Ca, LiF/Al, aluminum (Al), silver (Ag), magnesium (Mg), or a compound thereof. For example, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3may be further positioned on the metal thin film. The counter electrode230may be positioned over the display area DA (seeFIG.1), and may be positioned on the intermediate layer220and the pixel-defining film125. The counter electrode230may be integrally formed in first display elements DE1to correspond to the first pixel electrodes210a.

The first display element DE1may be covered by an encapsulation layer. The encapsulation layer may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. The at least one inorganic encapsulation layer may include at least one inorganic material from among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The at least one inorganic encapsulation layer may have a single structure or a multi-layer structure including the above material. The at least one organic encapsulation layer may include a polymer-based material. Examples of the polymer-based material may include an acrylic resin such as polymethylmethacrylate or polyacrylic acid, an epoxy resin, polyimide, and polyethylene. In an embodiment, the at least one organic encapsulation layer may include an acrylate polymer.

FIG.5is a schematic cross-sectional view of a pixel electrode and a data line ofFIG.3, taken along line I-I′. The embodiment ofFIG.5, as a modification of the embodiment ofFIG.4, is different fromFIG.4in a structure of the first data line DL1. The same description as that made with reference toFIG.4will be omitted, and a difference will be described.

Referring toFIG.5, the display apparatus1may further include an eighth insulating layer124. The eighth insulating layer124may be positioned between the seventh insulating layer123and the pixel-defining film125. The eighth insulating layer124may have a single structure or a multi-layer structure including an organic material to provide a flat top surface (or flat upper surface). The eighth insulating layer124may include benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), a general-purpose polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol-based group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorinated polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

A first connection pattern layer DL1c′ may be positioned between the sixth insulating layer121and the seventh insulating layer123, and a first conductive pattern layer DL1a′ and a second conductive pattern layer DL1b′ may be positioned between the seventh insulating layer123and the eighth insulating layer124.

The first conductive pattern layer DL1a′ may be connected (e.g., electrically connected) to an end portion of the first connection pattern layer DL1c′ through a seventh contact hole cnt7′ formed in the seventh insulating layer123. A part of the first conductive pattern layer DL1a′ may be buried (or filled) in the seventh contact hole ent7′, and the first conductive pattern layer DL1a′ and the first connection pattern layer DL1c′ may be connected (e.g., electrically connected) to each other.

The second conductive pattern layer DL1b′ may be connected (e.g., electrically connected) to another end portion of the first connection pattern layer DL1c′ through an eighth contact hole cnt8′ formed in the seventh insulating layer123. A part of the second conductive pattern layer DL1b′ may be buried (or filled) in the eighth contact hole cnt8′, and the second conductive pattern layer DL1b′ and the first connection pattern layer DL1c′ may be connected (e.g., electrically connected) to each other.

For example, the first conductive pattern layer DL1a′ and the second conductive pattern layer DL1b′ may be positioned on the same layer (e.g., seventh insulating layer123) between the first pixel electrode210aand the first connection pattern layer DL1c′. For example, a distance d′ between the first data line DL1and the first pixel electrode210amay increase at a portion where the first data line DL1and the first pixel electrode210aoverlap each other. Thus, a capacitance value formed between the first data line DL1and the first pixel electrode210amay decrease.

FIG.6is a schematic cross-sectional view of a pixel electrode and a data line ofFIG.3, taken along line I-I′. The embodiment ofFIG.6, as a modification of the embodiment ofFIG.5, is different fromFIG.5in a structure of the first data line DL1. The same description as that made with reference toFIG.5will be omitted, and a difference will be described.

Referring toFIG.6, a first connection pattern layer DL1c″ may be positioned between the fifth insulating layer119and the sixth insulating layer121, and a first conductive pattern layer DL1a″ and a second conductive pattern layer DL1b″ may be positioned between the seventh insulating layer123and the eighth insulating layer124.

The first conductive pattern layer DL1a″ may be connected (e.g., electrically connected) to an end portion of the first connection pattern layer DL1c″ through a seventh contact hole cnt7″ formed in the sixth insulating layer121and the seventh insulating layer123. A part of the first conductive pattern layer DL1a″ may be buried (or filled) in the seventh contact hole cnt7″, and the first conductive pattern layer DL1a″ and the first connection pattern layer DL1c″ may be connected (e.g., electrically connected) to each other.

The second conductive pattern layer DL1b″ may be connected (e.g., electrically connected) to another end portion of the first connection pattern layer DL1c″ through an eighth contact hole cnt8″ formed in the sixth insulating layer121and the seventh insulating layer123. A part of the second conductive pattern layer DL1b″ may be buried (or filled) in the eighth contact hole cnt8″, and the second conductive pattern layer DL1b″ and the first connection pattern layer DL1c″ may be connected (e.g., electrically connected) to each other.

For example, the first conductive pattern layer DL1a″ and the second conductive pattern layer DL1b″ may be positioned on the same layer (e.g., seventh insulating layer123) between the first pixel electrode210aand the first connection pattern layer DL1c“. For example, a distance d” between the first data line DL1and the first pixel electrode210amay increase at a portion where the first data line DL1and the first pixel electrode210aoverlap each other. Thus, a capacitance value formed between the first data line DL1and the first pixel electrode210amay decrease.

FIG.7is a schematic view of an operation of a display apparatus according to an embodiment.

Referring to a circuit diagram shown on the right side ofFIG.7, a capacitor Cda may be formed between the data line DL and the anode of the organic light-emitting diode OLED. The anode of the organic light-emitting diode OLED may be capacitively coupled to the data line DL by the capacitor Cda. In case that the seventh transistor T7is turned on in response to the fourth scan signal GB and the second initialization voltage VAINT is applied to the anode of the organic light-emitting diode OLED, the anode of the organic light-emitting diode OLED may not be capacitively coupled to the data line DL by the capacitor Cda.

Referring to a timing diagram shown on the left side ofFIG.7, a cycle (see a dashed diagonal line) in which the seventh transistor T7is turned on in response to the fourth scan signal GB may be repeated twice for one frame. For example, in case that the display apparatus1is driven at 120 Hz, a frequency of the fourth scan signal GB may be 240 Hz. For example, the display area DA of the display apparatus1may be divided into a first area AR1where the seventh transistor T7is turned on and a second area AR2where the seventh transistor T7is turned off, in response to the fourth scan signal GB, in case that a black voltage is applied to the data line DL (e.g., in case that the data voltage Dm has a rising edge). A potential of the anode of the organic light-emitting diode positioned in the first area AR1is not affected by the rising edge of the data voltage Dm in case that the black voltage is applied to the data line DL to turn on the seventh transistor T7, but may decrease by a potential change amount ΔV due to a falling edge of the data voltage Dm by the capacitor Cda. Because the seventh transistor T7is turned off in case that the black voltage is applied to the data line DL, a potential of the anode of the organic light-emitting diode OLED positioned in the second area AR2may increase due to the rising edge of the data voltage Dm and may decrease due to the falling edge of the data voltage Dm by the capacitor Cda. Accordingly, a first anode initial voltage VAR1of the first area AR1may be a value VAINT-ΔV obtained by subtracting the potential change amount ΔV from the second initialization voltage VAINT, and a second anode initial voltage VAR2of the second area AR2may be the second initialization voltage VAINT. There is an anode initial voltage difference between the first area AR1and the second area AR2, and stains may occur in the display area DA due to the anode initial voltage difference.

As described with reference toFIGS.3to6according to an embodiment, a capacitance value formed between the data line DL and the organic light-emitting diode OLED may decrease. In case that the capacitance value formed between the data line DL and the anode of the organic light-emitting diode OLED decreases, the potential change amount ΔV may decrease, and an anode initial voltage difference between the first area AR1and the second area AR2may decrease. Accordingly, stains may be prevented from occurring in the display area DA due to an anode initial voltage difference.

FIG.8is an enlarged schematic plan view of a portion of a display apparatus according to an embodiment. The embodiment ofFIG.8, as a modification of the embodiment ofFIG.3, is different fromFIG.3in a structure of a shield electrode. The same description as that made with reference toFIG.3will be omitted, and a difference will be described.

Referring toFIG.8, the display apparatus1may further include a first shield electrode1104. The first shield electrode1104may be positioned between the first display element DE1and the first connection pattern layer DL1c. The first shield electrode1104may be positioned between the first pixel electrode210aand the first connection pattern layer DL1c. The first shield electrode1104, the first conductive pattern layer DL1a, and the second conductive pattern layer DL1bmay be positioned on the same layer.

The first shield electrode1104may at least partially overlap the first connection pattern layer DL1c. The first shield electrode1104may at least partially overlap the first pixel electrode210a. A preset (or certain) voltage may be applied to the first shield electrode1104. For example, the first shield electrode1104may extend from the third conductive line1103in a second direction (e.g., ±x-axis direction). The first shield electrode1104and the third conductive line1103may be integral (or integrally formed) with each other. As described with reference toFIG.3, because the first initialization voltage VINT, the second initialization voltage VAINT, or the bias voltage VOBS ofFIG.2may be applied to the third conductive line1103, the first initialization voltage VINT, the second initialization voltage VAINT, or the bias voltage VOBS may be applied to the first shield electrode1104.

As in an embodiment, in case that the first shield electrode1104to which a preset (or certain) voltage is applied is positioned between the first pixel electrode210aand the first connection pattern layer DL1c, a capacitance value formed between the first data line DL1and the first pixel electrode210amay decrease. As the capacitance value formed between the first data line DL1and the first pixel electrode210adecreases, stains may be prevented from occurring in the display area DA (seeFIG.1).

Although the first shield electrode1104and the third conductive line1103are integral (or integrally formed) with each other inFIG.8, in another example, the first shield electrode1104and the third conductive line1103may be separated from each other. The first shield electrode1104may be electrically connected to the first conductive line1101or the second conductive line1102so that a preset (or certain) voltage may be applied to the first shield electrode1104.

FIG.9is a schematic cross-sectional view of a pixel electrode, a data line, and a shield electrode ofFIG.8, taken along line II-II′. InFIG.9, the same members as those inFIG.4are denoted by the same reference numerals, and thus, a redundant description thereof will be omitted for descriptive convenience.

Referring toFIG.9, the first shield electrode1104may be positioned between the first pixel electrode210aand the first connection pattern layer DL1c. The first shield electrode1104, the first conductive pattern layer DL1a, and the second conductive pattern layer DL1bmay be positioned on the same layer. For example, as shown inFIG.9, the first shield electrode1104may be positioned between the sixth insulating layer121and the seventh insulating layer123.

Although the first shield electrode1104is positioned between the sixth insulating layer121and the seventh insulating layer123inFIG.9, in another example according toFIGS.5and6, the first shield electrode1104may be positioned between the seventh insulating layer123and the eighth insulating layer124.

FIG.10is an enlarged schematic plan view of a portion of a display apparatus1according to an embodiment. The embodiment ofFIG.10, as a modification of the embodiment ofFIG.3, is different fromFIG.3in structures of the first data line DL1′ and the second data line DL2′. The same description as that made with reference toFIG.3will be omitted, and a difference will be described.

Referring toFIG.10, the first data line DL1′ may continuously extend in the first direction (e.g., ±y-axis direction), like the third data line DL3. A second data line DL2′ may include a third conductive pattern layer DL2a, a fourth conductive pattern layer DL2b, and a second connection pattern layer DL2c. The third conductive pattern layer DL2aand a fourth conductive pattern layer DL2bmay extend in the first direction (e.g., ±y-axis direction) to be spaced apart from each other. The second connection pattern layer DL2cmay extend in the first direction (e.g., ±y-axis direction) to connect (e.g., electrically connect) the third conductive pattern layer DL2ato the fourth conductive pattern layer DL2b. An end portion of the second connection pattern layer DL2cmay be connected (e.g., electrically connected) to the third conductive pattern layer DL2athrough a ninth contact hole cnt9, and another end portion of the second connection pattern layer DL2cmay be connected (e.g., electrically connected) to the fourth conductive pattern layer DL2bthrough a tenth contact hole cnt10. In a plan view, the third conductive pattern layer DL2aand the fourth conductive pattern layer DL2bmay be spaced apart from (may not overlap) the second pixel electrode210b, and the second connection pattern layer DL2cmay at least partially overlap the second pixel electrode210b. The second connection pattern layer DL2cmay at least partially overlap the third electrode portion210bcof the second pixel electrode210b.

As shown inFIG.11, the third conductive pattern layer DL2aand the fourth conductive pattern layer DL2bmay be positioned on the same layer (e.g., sixth insulating layer121) between the second pixel electrode210band the second connection pattern layer DL2c. For example, a distance between the second data line DL2′ and the second pixel electrode210bmay increase at a portion where the second data line DL2′ and the second pixel electrode210boverlap each other. Thus, a capacitance value formed between the second data line DL2′ and the second pixel electrode210bmay decrease. For example, in case that the second pixel electrode210bincludes the first electrode portion210baand the second electrode portion210bbthat are spaced apart from each other with the second data line DL2′ therebetween, an overlapping ratio (or overlapping size/area) between the second data line DL2′ and the second pixel electrode210bmay decrease, and thus, the capacitance value formed between the second data line DL2′ and the second pixel electrode210bmay decrease. As the capacitance value formed between the second data line DL2′ and the second pixel electrode210bdecreases, stains may be prevented from occurring in the display area DA (seeFIG.1).

FIG.11is a schematic cross-sectional view of a pixel electrode and a data line ofFIG.10, taken along line III-III′. InFIG.11, the same members as those inFIG.4are denoted by the same reference numerals, and thus, a redundant description thereof will be omitted for descriptive convenience.

Referring toFIG.11, the second connection pattern layer DL2cmay be positioned between the fifth insulating layer119and the sixth insulating layer121, and the third conductive pattern layer DL2aand the fourth conductive pattern layer DL2bmay be positioned between the sixth insulating layer121and the seventh insulating layer123.

The third conductive pattern layer DL2amay be connected (e.g., electrically connected) to an end portion of the second connection pattern layer DL2cthrough the ninth contact hole cnt9formed in the sixth insulating layer121. A part of the third conductive pattern layer DL2amay be buried (or filled) in the ninth contact hole cnt9, and the third conductive pattern layer DL2aand the second connection pattern layer DL2cmay be connected (e.g., electrically connected) to each other.

The fourth conductive pattern layer DL2bmay be connected (e.g., electrically connected) to another end portion of the second connection pattern layer DL2cthrough the tenth contact hole cnt10formed in the sixth insulating layer121. A part of the fourth conductive pattern layer DL2bmay be buried (or filled) in the tenth contact hole cnt10, and the fourth conductive pattern layer DL2band the second connection pattern layer DL2cmay be connected (e.g., electrically connected) to each other.

Referring toFIG.11, the second connection pattern layer DL2cmay be positioned between the fifth insulating layer119and the sixth insulating layer121, and the third conductive pattern layer DL2aand the fourth conductive pattern layer DL2bmay be positioned between the sixth insulating layer121and the seventh insulating layer123inFIG.11. In another example, as shown inFIG.5, the second connection pattern layer DL2cmay be positioned between the sixth insulating layer121and the seventh insulating layer123, and the third conductive pattern layer DL2aand the fourth conductive pattern layer DL2bmay be positioned between the seventh insulating layer123and the eighth insulating layer124. For example, the ninth contact hole cnt9and the tenth contact hole cnt10may be formed in the seventh insulating layer123.

In another example, as shown inFIG.6, the second connection pattern layer DL2cmay be positioned between the fifth insulating layer119and the sixth insulating layer121and the third conductive pattern layer DL2aand the fourth conductive pattern layer DL2bmay be positioned between the seventh insulating layer123and the eighth insulating layer124. For example, the ninth contact hole cnt9and the tenth contact hole cnt10may be formed in the sixth insulating layer121and the seventh insulating layer123.

FIG.12is an enlarged schematic plan view of a portion of a display apparatus according to an embodiment. The embodiment ofFIG.12, as a modification of the embodiment ofFIG.10, is different fromFIG.10in a structure of the second display element DE2. The same description as that made with reference toFIG.10will be omitted, and a difference will be described.

Referring toFIG.12, the second pixel electrode210bof the second display element DE2may include the first electrode portion210ba, the second electrode portion210bb, and the third electrode portion210bc. The first electrode portion210baand the second electrode portion210bbmay extend in the first direction (e.g., +y-axis direction). The first electrode portion210baand the second electrode portion210bbmay be spaced apart from each other with the second data line DL2′ therebetween. The third electrode portion210bcmay connect (e.g., electrically connect) the first electrode portion210bato the second electrode portion210bb. The third electrode portion210bcmay connect (e.g., electrically connect) a central portion of the first electrode portion210bato a central portion of the second electrode portion210bb.

For example, because only the third electrode portion210bcoverlaps the second data line DL2′, an overlapping ratio (or overlapping size/area) between the second data line DL2′ and the second pixel electrode210bmay decrease. Because an overlapping ratio (or overlapping size/area) between the second data line DL2′ and the second pixel electrode210bdecreases, a capacitance value formed between the second data line DL2′ and the second pixel electrode210bmay decrease. As the capacitance value formed between the second data line DL2′ and the second pixel electrode210bdecreases, stains may be prevented from occurring in the display area DA (seeFIG.1).

FIG.13is an enlarged schematic plan view of a portion of a display apparatus according to an embodiment. The embodiment ofFIG.13, as a modification of the embodiment ofFIG.10, is different fromFIG.10in a structure of a shield electrode. The same description as that made with reference toFIG.10will be omitted, and a difference will be described.

Referring toFIG.13, the display apparatus1may further include a second shield electrode1105. The second shield electrode1105may be positioned between the second display element DE2and the second connection pattern layer DL2c. The second shield electrode1105may be positioned between the second pixel electrode210band the second connection pattern layer DL2c. The second shield electrode1105, the third conductive pattern layer DL2a, and the fourth conductive pattern layer DL2bmay be positioned on the same layer.

The second shield electrode1105may at least partially overlap the second connection pattern layer DL2c. The second shield electrode1105may at least partially overlap the second pixel electrode210b. A preset (or certain) voltage may be applied to the second shield electrode1105. For example, the second shield electrode1105may extend from the second conductive line1102in the second direction (e.g., +x-axis direction). The second shield electrode1105and the second conductive line1102may be integral (or integrally formed) with each other. As described with reference toFIG.3, because the second driving voltage ELVSS may be applied to the third conductive line1103, the second driving voltage ELVSS may be applied to the second shield electrode1105.

As in an embodiment, in case that the second shield electrode1105is positioned between the second pixel electrode210band the second connection pattern layer DL2c, a capacitance value formed between the second data line DL2′ and the second pixel electrode210bmay decrease. As the capacitance value formed between the second data line DL2′ and the second pixel electrode210bdecreases, stains may be prevented from occurring in the display area DA (seeFIG.1).

Although the second shield electrode1105and the second conductive line1102are integral (or integrally formed) with each other inFIG.13, in another example, the second shield electrode1105and the second conductive line1102may be separated from each other. The second shield electrode1105may be electrically connected to the first conductive line1101or the third conductive line1103so that a preset (or certain) voltage may be applied to the second shield electrode1105.

FIG.14is a schematic cross-sectional view of a pixel electrode, a data line, and a shield electrode ofFIG.13, taken along line IV-IV′. InFIG.14, the same members as those inFIG.4are denoted by the same reference numerals, and thus, a redundant description thereof will be omitted for descriptive convenience.

Referring toFIG.14, the second shield electrode1105may be positioned between the third electrode portion210bcof the second pixel electrode210band the second connection pattern layer DL2c. The second shield electrode1105, the third conductive pattern layer DL2a, and the fourth conductive pattern layer DL2bmay be positioned on the same layer. For example, as shown inFIG.14, the second shield electrode1105may be positioned between the sixth insulating layer121and the seventh insulating layer123.

Referring toFIG.14, the second shield electrode1105may be positioned between the sixth insulating layer121and the seventh insulating layer123inFIG.14. In another example, according toFIGS.5and6, the second shield electrode1105may be positioned between the seventh insulating layer123and the eighth insulating layer124.

FIG.15is an enlarged schematic plan view of a portion of a display apparatus according to an embodiment. The embodiment ofFIG.15, as a modification of the embodiment ofFIG.3, is different fromFIG.3in a structure of the second data line DL2′. The same description as that made with reference toFIG.3will be omitted, and a difference will be described.

Referring toFIG.15, an embodiment ofFIG.3and an embodiment ofFIG.10may be applied together. The first data line DL1may include the first conductive pattern layer DL1a, the second conductive pattern layer DL1b, and the first connection pattern layer DL1c. The first conductive pattern layer DL1aand the second conductive pattern layer DL1bmay extend in the first direction (e.g., +y-axis direction) to be spaced apart from each other. The first connection pattern layer DL1cmay extend in the first direction (e.g., +y-axis direction) to connect (e.g., electrically connect) the first conductive pattern layer DL1ato the second conductive pattern layer DL1b. An end portion of the first connection pattern layer DL1cmay be connected (e.g., electrically connected) to the first conductive pattern layer DL1athrough the seventh contact hole cnt7, and another end portion of the first connection pattern layer DL1cmay be connected (e.g., electrically connected) to the second conductive pattern layer DL1bthrough the eighth contact hole cnt8. In a plan view, the first conductive pattern layer DL1aand the second conductive pattern layer DL1bmay be spaced apart from (may not overlap) the first pixel electrode210a, and the first connection pattern layer DL1cmay at least partially overlap the first pixel electrode210a.

The second data line DL2′ may include the third conductive pattern layer DL2a, the fourth conductive pattern layer DL2b, and the second connection pattern layer DL2c. The third conductive pattern layer DL2aand the fourth conductive pattern layer DL2bmay extend in the first direction (e.g., +y-axis direction) to be spaced apart from each other. The second connection pattern layer DL2cmay extend in the first direction (e.g., +y-axis direction) to connect (e.g., electrically connect) the third conductive pattern layer DL2ato the fourth conductive pattern layer DL2b. An end portion of the second connection pattern layer DL2cmay be connected (e.g., electrically connected) to the third conductive pattern layer DL2athrough the ninth contact hole cnt9, and another end portion of the second connection pattern layer DL2cmay be connected (e.g., electrically connected) to the fourth conductive pattern layer DL2bthrough the tenth contact hole cnt10. In a plan view, the third conductive pattern layer DL2aand the fourth conductive pattern layer DL2bmay be spaced apart from (may not overlap) the second pixel electrode210b, and the second connection pattern layer DL2cmay at least partially overlap the second pixel electrode210b. The second connection pattern layer DL2cmay at least partially overlap the third electrode portion210bcof the second pixel electrode210b.

FIG.16is an enlarged schematic plan view of a portion of a display apparatus according to an embodiment. The embodiment ofFIG.16, as a modification of the embodiment of FIG.15, is different fromFIG.15in a structure of a shield electrode. The same description as that made with reference toFIG.15will be omitted, and a difference will be described.

Referring toFIG.16, an embodiment ofFIG.8and an embodiment ofFIG.13may be applied together. The display apparatus1may further include the first shield electrode1104and the second shield electrode1105.

The first shield electrode1104may be positioned between the first display element DE1and the first connection pattern layer DL1c. The first shield electrode1104may be positioned between the first pixel electrode210aand the first connection pattern layer DL1c. The first shield electrode1104, the first conductive pattern layer DL1a, and the second conductive pattern layer DL1bmay be positioned on the same layer. The first shield electrode1104may at least partially overlap the first connection pattern layer DL1c. The first shield electrode1104may at least partially overlap the first pixel electrode210a. A first voltage may be applied to the first shield electrode1104. For example, the first shield electrode1104may extend from the third conductive line1103in the second direction (e.g., +x-axis direction). The first shield electrode1104and the third conductive line1103may be integral (or integrally formed) with each other. As described with reference toFIG.3, because the first initialization voltage VINT, the second initialization voltage VAINT, or the bias voltage VOBS may be applied to the third conductive line1103, the first initialization voltage VINT, the second initialization voltage VAINT, or the bias voltage VOBS may be applied to the first shield electrode1104.

The second shield electrode1105may be positioned between the second display element DE2and the second connection pattern layer DL2c. The second shield electrode1105may be positioned between the second pixel electrode210band the second connection pattern layer DL2c. The second shield electrode1105may be positioned on the same layer as the third conductive pattern layer DL2aand the fourth conductive pattern layer DL2b. The second shield electrode1105may at least partially overlap the second connection pattern layer DL2c. The second shield electrode1105may at least partially overlap the second pixel electrode210b. A second voltage may be applied to the second shield electrode1105. For example, the second shield electrode1105may extend from the second conductive line1102in the second direction (e.g., ±x-axis direction). The second shield electrode1105and the second conductive line1102may be integral (or integrally formed) with each other. As described with reference toFIG.3, the second driving voltage ELVSS ofFIG.2may be applied to the third conductive line1103, the second driving voltage ELVSS may be applied to the second shield electrode1105.

In an embodiment, the first voltage and the second voltage may be different from each other. For example, the first voltage may be the first initialization voltage VINT, the second initialization voltage VAINT, or the bias voltage VOBS, and the second voltage may be the second driving voltage ELVSS.

Although the first shield electrode1104and the third conductive line1103are integral (or integrally formed) with each other inFIG.16, in another example, the first shield electrode1104and the third conductive line1103may be separated from each other. The first shield electrode1104may be electrically connected to the first conductive line1101or the second conductive line1102so that the first voltage may be applied to the first shield electrode1104. Although the second shield electrode1105and the second conductive line1102are integral (or integrally formed) with each other inFIG.16, in another example, the second shield electrode1105and the second conductive line1102may be separated from each other. The second shield electrode1105may be electrically connected to the first conductive line1101or the third conductive line1103so that the second voltage may be applied to the second shield electrode1105.

A display apparatus1has been described, but embodiments are not limited thereto. For example, a method of manufacturing the display apparatus1may fall within the scope of the disclosure.

According to various embodiments, stains may be prevented from occurring in a display area. Accordingly, defects of a display apparatus may be prevented. However, the scope of the disclosure is not limited by these effects.