A semiconductor device includes: a first semiconductor chip on which a first alignment mark, a second alignment mark, first and second terminals for measuring conduction, a wiring that electrically connects the first alignment mark and the first terminal, and a wiring that electrically connects the second alignment mark and the second terminal are provided; and a second semiconductor chip on which a third alignment mark, a fourth alignment mark, and a wiring that electrically connects the third alignment mark and the fourth alignment mark are provided and which is bonded to the first semiconductor chip in such a way that the first alignment mark and the third alignment mark overlap each other, and the second alignment mark and the fourth alignment mark overlap each other.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2022-158227 filed on Sep. 30, 2022, the disclosures of which are incorporated by reference herein.

BACKGROUND

Technical Field

The present disclosure relates to a semiconductor device, a base-side semiconductor chip, and a bonding-side semiconductor chip.

Related Art

Japanese Patent Application Laid-Open (JP-A) No. 2002-111148 (Patent Literature 1) discloses a technology that enables highly reliable flip-chip mounting. In addition, Japanese Patent Application Laid-Open (JP-A) No. 2004-20550 (Patent Literature 2) discloses a technology capable of inspecting electrical connection between a plurality of semiconductor integrated circuit chips in a state where the semiconductor integrated circuit chips are bonded.

Here, in an inspection method of inspecting electrical connection between semiconductor integrated circuit chips according to the related art, inspection is performed by operating an internal circuit included in a semiconductor chip, and it takes time to end the inspection.

SUMMARY

Therefore, an object of the present disclosure is to reduce an inspection time for inspecting electrical connection between a plurality of semiconductor chips in a state where the semiconductor chips are bonded.

A semiconductor device of the present disclosure includes: a first semiconductor chip on which a first alignment mark, a second alignment mark, first and second terminals for measuring conduction, a wiring that electrically connects the first alignment mark and the first terminal, and a wiring that electrically connects the second alignment mark and the second terminal are provided; and a second semiconductor chip on which a third alignment mark, a fourth alignment mark, and a wiring that electrically connects the third alignment mark and the fourth alignment mark are provided and which is bonded to the first semiconductor chip in such a way that the first alignment mark and the third alignment mark overlap each other, and the second alignment mark and the fourth alignment mark overlap each other.

A base-side semiconductor chip of the disclosure includes: a plurality of base-side alignment marks; measurement terminals for measuring conduction; and wirings that electrically connect the base-side alignment marks and the measurement terminals, in which the measurement terminals are configured to measure conduction in a case where a bonding-side semiconductor chip is bonded in such a way that the base-side alignment marks and a plurality of bonding-side alignment marks provided on the bonding-side semiconductor chip overlap each other.

A bonding-side semiconductor chip of the disclosure includes: a plurality of bonding-side alignment marks; and a wiring that electrically connects the bonding-side alignment marks to each other, in which in a case where the bonding-side semiconductor chip is bonded to a base-side semiconductor chip in such a way that the bonding-side alignment marks and a plurality of base-side alignment marks provided on the base-side semiconductor chip and electrically connected to measurement terminals for measuring conduction overlap each other, the wiring electrically connects the base-side alignment marks to each other.

According to the present disclosure, it is possible to reduce an inspection time for inspecting electrical connection between a plurality of semiconductor chips in a state where the semiconductor chips are bonded.

DETAILED DESCRIPTION

Hereinafter, examples of an embodiment of the present disclosure will be described with reference to the drawings. In the drawings, the same or equivalent components and portions are denoted by the same reference signs. In addition, dimensional ratios in the drawings are exaggerated for convenience of explanation, and may be different from actual ratios.

FIG.1is a plan view of a base-side semiconductor chip (hereinafter, referred to as a “base-side chip20”).

As illustrated inFIG.1, in the base-side chip20, a first alignment mark22arranged on the lower left side in the drawing, a second alignment mark23arranged on the upper right side in the drawing, measurement terminals24for measuring conduction, and a connection terminal27for connection to a bonding-side semiconductor chip (hereinafter, referred to as a “bonding-side chip30”) are provided on one surface of a semiconductor laminated body21having a rectangular shape of which a long side is along the horizontal direction in the drawing and a short side is along the vertical direction in the drawing. The measurement terminals24include a first terminal24A and a second terminal24B. The first alignment mark22and the first terminal24A are electrically connected by a wiring25, and the second alignment mark23and the second terminal24B are electrically connected by a wiring26. The base-side chip20is an example of a “first semiconductor chip” and the “base-side semiconductor chip”, the first alignment mark22and the second alignment mark23are an example of “base-side alignment marks”, and the wiring25and the wiring26are an example of “wirings that electrically connect the base-side alignment marks and the measurement terminals”.

The first alignment mark22and the second alignment mark23are made of copper (Cu) and have a cross shape.

The measurement terminal24is made of a conductor such as aluminum or aluminum to which copper is added, and has a square shape. Among the measurement terminals24, the first terminal24A is arranged on the left side of the first alignment mark22inFIG.1, and the second terminal24B is arranged on the right side of the second alignment mark23inFIG.1.

The connection terminal27is made of copper and has a circular shape. As an example, a plurality of connection terminals27are arranged side by side in the vertical direction in the drawing at the central portion of one surface of the laminated body21. Although only three connection terminals27are illustrated inFIG.1for convenience of explanation, the number of connection terminals27provided on the base-side chip20is not limited.

Although methods for manufacturing the first alignment mark22, the second alignment mark23, the measurement terminals24, the wiring25, the wiring26, and the connection terminal27are not described above, these manufacturing methods are not particularly limited, and known technologies are used if appropriate.

FIG.2is a plan view of a bonding-side chip30.

As illustrated inFIG.2, in the bonding-side chip30, a third alignment mark32arranged at the lower right in the figure, a fourth alignment mark33arranged on the upper left side in the drawing, and a connection terminal35for connection to the base-side chip20are provided on one surface of a semiconductor laminated body31having a rectangular shape of which a long side is along the horizontal direction in the drawing and a short side is along the vertical direction in the drawing. The third alignment mark32and the fourth alignment mark33are electrically connected by a wiring34.

The bonding-side chip30is an example of a “second semiconductor chip” and the “bonding-side semiconductor chip”, the third alignment mark32and the fourth alignment mark33are an example of “bonding-side alignment marks”, and the wiring34is an example of a “wiring electrically connecting the bonding-side alignment marks”.

The third alignment mark32and the fourth alignment mark33are made of copper, and have a cross shape similarly to the first alignment mark22and the second alignment mark23. The dimensions of the third alignment mark32and the fourth alignment mark33are substantially the same as the dimensions of the first alignment mark22and the second alignment mark23.

The third alignment mark32and the fourth alignment mark33are arranged in such a way that the first alignment mark22and the third alignment mark32overlap each other, and the second alignment mark23and the fourth alignment mark33overlap each other in a case where the bonding-side chip30is reversed from the state illustrated inFIG.2and overlaps the base-side chip20.

The wiring34is arranged outside a semiconductor element region36provided at the central portion of the bonding-side chip30. Although not illustrated, a semiconductor or the like necessary for operation of a semiconductor device10in which the bonding-side chip30is bonded to the base-side chip20is arranged in the element region36.

The connection terminal35is made of copper and has a circular shape similarly to the connection terminal27. As an example, a plurality of connection terminals35are arranged side by side in the vertical direction in the drawing at the central portion of one surface of the laminated body31. The connection terminal35is arranged in such a way that the connection terminal27and the connection terminal35overlap each other in a case where the bonding-side chip30is reversed from the state illustrated inFIG.2and overlaps the base-side chip20. Although only three connection terminals35are illustrated inFIG.2for convenience of explanation, the number of connection terminals35provided on the bonding-side chip30is not limited.

Although methods for manufacturing the third alignment mark32, the fourth alignment mark33, the wiring34, and the connection terminal35are not described above, these manufacturing methods are not particularly limited, and known technologies are used if appropriate.

FIG.3is a plan view of the semiconductor device10in which the bonding-side chip30is bonded to the base-side chip20.

The base-side chip20and the bonding-side chip30are bonded (joined) by, for example, Cu—Cu bonding between the connection terminal27and the connection terminal35. In a state where the bonding-side chip30is bonded to the base-side chip20, the first alignment mark22and the third alignment mark32overlap each other, and the second alignment mark23and the fourth alignment mark33overlap each other. The alignment between the first alignment mark22and the third alignment mark32and the alignment between the second alignment mark23and the fourth alignment mark33are achieved using a known technology if appropriate.

Here, in the semiconductor device10, in a case where the bonding-side chip30is bonded to the base-side chip20as described above, conduction can be measured using the measurement terminals24. Specifically, as illustrated inFIG.3, in the semiconductor device10, as the bonding-side chip30is bonded to the base-side chip20, the wiring34of the bonding-side chip30can electrically connect the first alignment mark22and the second alignment mark23to each other. In the semiconductor device10, the measurement terminals24(the first terminal24A and the second terminal24B) are electrically connected to each other in a case where the first alignment mark22and the second alignment mark23are electrically connected to each other.

Incidentally, in a case where the semiconductor device10is manufactured by bonding a plurality of semiconductor chips to each other as in the present embodiment, it is desirable to inspect (test) whether or not the semiconductor chips are electrically connected to each other. Then, in the semiconductor device10in which the base-side chip20and the bonding-side chip30are bonded to each other by Cu—Cu bonding, copper is flattened by a chemical mechanical polishing (CMP) process, and thus, it is possible to confirm electrical connection between all the other connection terminals27and35by confirming electrical connection between a set of connection terminals27and35.

In the embodiment, whether or not the base-side chip20and the bonding-side chip30are electrically connected to each other is inspected using a probe card (not illustrated) including a needle that is brought into contact with the measurement terminal24to input an electric signal to the measurement terminal24. Specifically, in the embodiment, when a positive (+) voltage (for example, 1 V) is applied to the first terminal24A and a voltage similar to the voltage applied to the first terminal24A is measured at the second terminal24B, it is determined that the base-side chip20and the bonding-side chip30are electrically connected to each other. In a case where it is determined that the base-side chip20and the bonding-side chip30are electrically connected to each other, a slight error between the voltage applied to the first terminal24A and the voltage measured at the second terminal24B is allowed. On the other hand, in the embodiment, in a case where the voltage measured at the second terminal24B deviates from the voltage applied to the first terminal24A by more than the above-described error, it is determined that the base-side chip20and the bonding-side chip30are not electrically connected to each other.

Here, examples of a conventional inspection method of inspecting whether or not a plurality of bonded semiconductor chips are electrically connected to each other include a method of performing inspection by operating an internal circuit included in a semiconductor chip. For example, in the inspection method, an external device inputs a predetermined signal between a plurality of semiconductor chips, logical computation is performed in an internal circuit included in the semiconductor chip based on the input signal, and whether or not the plurality of semiconductor chips are electrically connected to each other is determined according to the computation result. In this case, it takes time to end the inspection because, for example, the external device is controlled to input the predetermined signal between the plurality of semiconductor chips and the logic computation is performed in the internal circuit included in the semiconductor chip in the inspection method.

On the other hand, in the semiconductor device10, it is possible to confirm whether or not the base-side chip20and the bonding-side chip30are electrically connected to each other only by applying a positive (+) voltage to one (first terminal24A) of the measurement terminals24and measuring a voltage at the other one (second terminal24B) of the measurement terminals24. Therefore, with the semiconductor device10, it is possible to reduce an inspection time for inspecting electrical connection between the plurality of semiconductor chips in a state where the semiconductor chips are bonded as compared with the conventional inspection method.

In the semiconductor device10, the first alignment mark22, the second alignment mark23, the third alignment mark32, and the fourth alignment mark33are different in shape from the connection terminal27, the connection terminal35, and the measurement terminal24. As a result, with the semiconductor device10, it is possible to reduce erroneous image recognition in a case where the bonding-side chip30is bonded to the base-side chip20.

In the semiconductor device10, the first terminal24A and the second terminal24B as the measurement terminals24have smaller dimensions than other terminals (not illustrated) required for the operation of the semiconductor device10. Examples of the other terminals include a bonding pad for connecting a bonding wire. As a result, with the semiconductor device10, it is possible to reduce an influence of provision of the measurement terminal24as compared with a case where the measurement terminal24and the other terminals have the same size.

In the semiconductor device10, the wiring34that electrically connects the third alignment mark32and the fourth alignment mark33is arranged outside the semiconductor element region36in the bonding-side chip30. Therefore, with the semiconductor device10, it is possible to prevent the wiring34from hindering formation of a semiconductor in the element region36.

The material of each member in the above embodiment is not particularly limited. For example, in the above embodiment, the first alignment mark22, the second alignment mark23, the third alignment mark32, the fourth alignment mark33, the connection terminal27, and the connection terminal35are formed of copper, but are not limited thereto, and may be formed of another metal such as gold (Au).

The shape of each member in the above embodiment is not particularly limited. For example, in the above embodiment, the first alignment mark22, the second alignment mark23, the third alignment mark32, and the fourth alignment mark33are formed in a cross shape. However, the disclosure is not limited thereto, and the first alignment mark22, the second alignment mark23, the third alignment mark32, and the fourth alignment mark33may be formed in another shape generally used as an alignment mark, such as a circular shape or a ring shape.