Display apparatus

A display apparatus including a substrate having a display area, a plurality of pixel circuits arranged in the display area, each of the pixel circuits including a thin-film transistor, a plurality of display elements respectively connected to the pixel circuits, and a composite layer disposed between the pixel circuits and the display elements, the composite layer including a first inorganic insulating layer, a first organic insulating layer, and a second inorganic insulating layer, which are sequentially stacked.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 10-2020-0081671, filed on Jul. 2, 2020, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND

Field

Embodiments of the invention relate generally to a display apparatus.

Discussion of the Background

Generally, a display apparatus includes a display element, and electronic devices configured to control electrical signals to be applied to the display element. The electronic devices include a thin-film transistor (TFT), a storage capacitor, and a plurality of wirings.

Recently, the usage of display apparatuses has diversified. Also, display apparatuses have become thinner and lighter, and thus, the uses of display apparatuses have expanded. As display apparatuses are used in various ways, various methods of designing the shape of display apparatuses are increasing.

SUMMARY

Display devices constructed according to embodiments of the invention are capable of improving robustness and flexibility against external impacts.

A display apparatus according to an embodiment includes a substrate having a display area, a plurality of pixel circuits arranged in the display area, each of the pixel circuits including a thin-film transistor, a plurality of display elements respectively connected to the pixel circuits, and a composite layer disposed between the pixel circuits and the display elements, the composite layer comprising a first inorganic insulating layer, a first organic insulating layer, and a second inorganic insulating layer, which are sequentially stacked.

A thickness of each of the first inorganic insulating layer and the second inorganic insulating layer may be in a range of about 1,000 Å to about 3,000 Å, and a thickness of the first organic insulating layer may be in a range of about 10,000 Å to about 20,000 Å.

A strength of each of the first inorganic insulating layer and the second inorganic insulating layer may be in a range of about 80 GPa to about 200 GPa, and a strength of the first organic insulating layer may be in a range of about 1 GPa to about 10 GPa.

The composite layer may further include a lower organic insulating layer disposed between the pixel circuit and the first inorganic insulating layer.

The composite layer may further include an upper organic insulating layer disposed between the second inorganic insulating layer and the display elements.

The composite layer may further include a second organic insulating layer and a third inorganic insulating layer, which are sequentially stacked.

The display apparatus may further include an inorganic material layer disposed in the display area and including an opening or a groove in an area between the pixel circuits, and an organic material layer filling the opening or the groove.

The opening or the groove may surround each of the pixel circuits.

The opening or the groove may surround at least a portion of the pixel circuits.

The display apparatus may further include an inorganic material layer disposed provided in the display area and including an opening or a groove in an area between the pixel circuits, and an organic interlayer insulating layer disposed on substantially the entire display area and filling the opening or the groove.

A display apparatus according to another embodiment includes a substrate including a display area and a peripheral area outside the display area, a circuit layer arranged in the display area of the substrate, the circuit layer including a first pixel circuit and a second pixel circuit, a display element layer arranged on the circuit layer, the display element layer including a first display element connected to the first pixel circuit and a second display element connected to the second pixel circuit, and a composite layer disposed between the circuit layer and the display element layer, the composite layer including a first inorganic insulating layer, a first organic insulating layer, and a second inorganic insulating layer, in which the circuit layer further includes an inorganic material layer having an opening or a groove in an area between the first pixel circuit and the second pixel circuit.

The first organic insulating layer may be disposed between the first inorganic insulating layer and the second inorganic insulating layer.

The display apparatus may further include an organic material layer filling the opening or the groove.

The display apparatus may further include a connection line arranged on the organic material layer to overlap the opening or the groove, in which the connection line may extend to an upper surface of the inorganic material layer.

The display apparatus may further include an organic interlayer insulating layer disposed over substantially the entire display area and filling the opening or the groove.

The opening or the groove may surround each of the first pixel circuit and the second pixel circuit in a plan view.

The opening or the groove may surround at least the first pixel circuit and the second pixel circuit together.

The composite layer may further include an additional organic insulating layer.

A thickness of each of the first inorganic insulating layer and the second inorganic insulating layer may be in a range of about 1,000 Å to about 3,000 Å, and a thickness of the first organic insulating layer may be in a range of about 10,000 Å to about 20,000 Å.

A strength of each of the first inorganic insulating layer and the second inorganic insulating layer may be in a range of about 80 GPa to about 200 GPa, and a strength of the first organic insulating layer may be in a range of about 1 GPa to about 10 GPa.

It is to be understood that both the foregoing general description and the following detailed description are and explanatory and are intended to provide further explanation of the invention as claimed.

DETAILED DESCRIPTION

FIG.1is a schematic plan view of a display apparatus10according to an embodiment.

Referring toFIG.1, various elements forming the display apparatus10are arranged on a substrate100. The substrate100may include a display area DA and a peripheral area DPA surrounding the display area DA.

Pixels P are arranged in the display area DA of the substrate100. The pixels P may each be implemented as a display element, such as an organic light-emitting diode (OLED). The pixels P may each emit, for example, red light, green light, blue light, or white light. The display area DA may be covered with a sealing member so as to be protected from external air or moisture.

Pixel circuits for driving the pixels P may be electrically connected to external circuits arranged in the peripheral area DPA. A first scan driving circuit SDRV1, a second scan driving circuit SDRV2, a terminal PAD, a driving voltage supply line11, and a common voltage supply line13may be arranged in the peripheral area DPA.

The first scan driving circuit SDRV1may apply a scan signal to each of the pixel circuits for driving the pixels P via a scan line SL. In addition, the first scan driving circuit

SDRV1may apply an emission control signal to each of the pixel circuits via an emission control line EL. The second scan driving circuit SDRV2may be opposite to the first scan driving circuit SDRV1with the display area DA therebetween. The second scan driving circuit SDRV2may be substantially parallel to the first scan driving circuit SDRV1. Some pixel circuits of the pixels P may be electrically connected to the first scan driving circuit SDRV1, and the remaining ones thereof may be electrically connected to the second scan driving circuit SDRV2. In some embodiments, the second scan driving circuit SDRV2may be omitted.

The terminal PAD may be arranged at one side of the substrate100. The terminal PAD may be exposed without being covered with an insulating layer and be electrically connected to a display circuit board30. A display driver32may be arranged on the display circuit board30.

The display driver32may generate a control signal to be transmitted to the first scan driving circuit SDRV1and the second scan driving circuit SDRV2. The display driver32may generate a data signal and transmit the generated data signal to the pixel circuits of the pixels P via a fan-out wiring FW and a data line DL connected to the fan-out wiring FW.

The display driver32may supply a driving voltage ELVDD to the driving voltage supply line11and may supply a common voltage ELVSS to the common voltage supply line13. The driving voltage ELVDD may be applied to the pixel circuits of the pixels P via a driving voltage line PL connected to the driving voltage supply line11, and the common voltage ELVSS may be applied to an opposite electrode of the display element connected to the common voltage supply line13.

The driving voltage supply line11may extend from the lower side of the display area DA in the x-direction. The common voltage supply line13may partially surround the display area DA while having one side of the display area DA opened.

FIGS.2A and2Bare equivalent circuit diagrams of pixel circuits PC for driving a pixel P according to embodiments.

Referring toFIG.2A, the pixel circuit PC may be connected to a display element ED to implement light emission of pixels. The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2is connected to a scan line SL and a data line DL, and is configured to transmit, to the driving thin-film transistor T1, a data signal Dm input via the data line DL according to a scan signal Sn input via the scan line SL.

The storage capacitor Cst is connected to the switching thin-film transistor T2and the driving voltage line PL, and is configured to store a voltage corresponding to a difference between a voltage received from the switching thin-film transistor T2and a driving voltage ELVDD supplied to the driving voltage line PL.

The driving thin-film transistor T1may be connected to the driving voltage line PL and the storage capacitor Cst, and may be configured to control a driving current flowing from the driving voltage line PL to the display element ED according to a voltage value stored in the storage capacitor Cst. The display element ED may emit light having a certain luminance according to the driving current.

FIG.2Aillustrates the pixel circuit PC including two thin-film transistors and one storage capacitor, but the inventive concepts are not limited thereto.

Referring toFIG.2B, the pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensating thin-film transistor T3, a first initializing thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initializing thin-film transistor T7.

AlthoughFIG.2Billustrates a pixel circuit PC including signal lines SL, SL−1, SL+1, EL, and DL, an initializing voltage line VL, and a driving voltage line PL are provided for each pixel circuit PC, the inventive concepts are not limited thereto. In another embodiment, at least one of the signal lines, namely, the scan line SL, the previous scan line SL−1, the next scan line SL+1, the emission control line EL, and the data line DL, and/or the initializing voltage line VL may be shared with neighboring pixel circuits.

A drain electrode of the driving thin-film transistor T1may be electrically connected to the display element ED via the emission control thin-film transistor T6. The driving thin-film transistor T1is configured to receive a data signal Dm and supply a driving current to the display element ED according to a switching operation of the switching thin-film transistor T2.

A gate electrode of the switching thin-film transistor T2is connected to the scan line Sn, and a source electrode of the switching thin-film transistor T2is connected to the data line DL. A drain electrode of the switching thin-film transistor T2may be connected to a source electrode of the driving thin-film transistor T1and connected to the driving voltage line PL via the operation control thin-film transistor T5.

The switching thin-film transistor T2is turned on according to a scan signal Sn received via the scan line SL and performs a switching operation of transmitting the data signal Dm received from the data line DL to the source electrode of the driving thin-film transistor T1.

A gate electrode of the compensating thin-film transistor T3may be connected to the scan line SL. A source electrode of the compensating thin-film transistor T3may be connected to the drain electrode of the driving thin-film transistor T1and connected to a pixel electrode of the display element ED via the emission control thin-film transistor T6. A drain electrode of the compensating thin-film transistor T3may be connected to any one electrode of the storage capacitor Cst, a source electrode of the first initializing thin-film transistor T4, and a gate electrode of the driving thin-film transistor T1. The compensating thin-film transistor T3is turned on according to the scan signal Sn received via the scan line SL, and connects the gate electrode and the drain electrode of the driving thin-film transistor T1to each other to provide diode-connection of the driving thin-film transistor T1.

A gate electrode of the first initializing thin-film transistor T4may be connected to a previous scan line SL−1. A drain electrode of the first initializing thin-film transistor T4may be connected to the initializing voltage line VL. The source electrode of the first initializing thin-film transistor T4may be connected to any one electrode of the storage capacitor Cst, the drain electrode of the compensating thin-film transistor T3, and the gate electrode of the driving thin-film transistor T1. The first initializing thin-film transistor T4may be turned on according to a previous scan signal Sn−1 received via the previous scan line SL−1 and performs an initializing operation of transmitting an initializing voltage Vint to the gate electrode of the driving thin-film transistor T1so as to initialize the voltage of the gate electrode of the driving thin-film transistor T1.

A gate electrode of the operation control thin-film transistor T5may be connected to the emission control line EL. A source electrode of the operation control thin-film transistor T5may be connected to the driving voltage line PL. A drain electrode of the operation control thin-film transistor T5is connected to the source electrode of the driving thin-film transistor T1and the drain electrode of the switching thin-film transistor T2.

A gate electrode of the emission control thin-film transistor T6may be connected to the emission control line EL. A source electrode of the emission control thin-film transistor T6may be connected to the drain electrode of the driving thin-film transistor T1and the source electrode of the compensating thin-film transistor T3. A drain electrode of the emission control thin-film transistor T6may be electrically connected to the pixel electrode of the display element ED. The operation control thin-film transistor T5and the emission control thin-film transistor T6are simultaneously turned on according to an emission control signal En received via the emission control line EL, and transmits the driving voltage ELVDD to the display element ED such that the driving current flows through the display element ED.

A gate electrode of the second initializing thin-film transistor T7may be connected to a next scan line SL+1. A source electrode of the second initializing thin-film transistor T7may be connected to the pixel electrode of the display element ED. A drain electrode of the second initializing thin-film transistor T7may be connected to the initializing voltage line VL. The second initializing thin-film transistor T7may be turned on according to a next scan signal Sn+1 received via the next scan line SL+1 and initializes the pixel electrode of the display element ED.

AlthoughFIG.2Billustrates that the first initializing thin-film transistor T4and the second initializing thin-film transistor T7are connected to the previous scan line SL−1 and the next scan line SL+1, respectively, the inventive concepts are not limited thereto. In another embodiment, each of the first initializing thin-film transistor T4and the second initializing thin-film transistor T7may be connected to the previous scan line SL−1 and may be driven according to a previous scan signal Sn−1.

The other electrode of the storage capacitor Cst may be connected to the driving voltage line PL. Any one electrode of the storage capacitor Cst may be connected to the gate electrode of the driving thin-film transistor T1, the drain electrode of the compensating thin-film transistor T3, and the source electrode of the first initializing thin-film transistor T4.

An opposite electrode (e.g., a cathode) of the display element ED receives a common voltage ELVSS. The display element ED receives a driving current from the driving thin-film transistor T1and emits light.

The inventive concepts are not limited to a particular number and a particular circuit design of the thin-film transistors and the storage capacitors in the pixel circuit PC, and in other embodiments, the number and the circuit design of the thin-film transistors and the storage capacitors in the pixel circuit PC may be variously changed.

FIG.3is a schematic cross-sectional view taken along line I-I′ ofFIG.1according to an embodiment.

Referring toFIG.3, a plurality of pixels P1and P2may be arranged in the display area DA of the display apparatus10. The pixels P1and P2may include a first pixel P1and a second pixel P2. The first pixel P1may include a first pixel circuit PC1, and a first organic light-emitting diode OLED1that functions as a display element connected to the first pixel circuit PC1. The second pixel P2may include a second pixel circuit PC2, and a second organic light-emitting diode OLED2that functions as a display element connected to the second pixel circuit PC2. The first organic light-emitting diode OLED1may include a first pixel electrode121a, a first emission layer122a, and an opposite electrode123, and the second organic light-emitting diode OLED2may include a second pixel electrode121b, a second emission layer122b, and the opposite electrode123.

In the illustrated embodiment, the display element is illustrated as an organic light-emitting diode, but in another embodiment, various display elements such as an inorganic light-emitting device or a quantum dot light-emitting device may be employed as the display element.

The display apparatus10according to the illustrated embodiment includes a composite layer200between the first and second pixel circuits PC1and PC2and the first and second organic light-emitting diodes OLED1and OLED2. The composite layer200includes a first inorganic insulating layer210, a first organic insulating layer220, and a second inorganic insulating layer230, which are sequentially stacked. The composite layer200may be configured to significantly reduce the transmission of external impacts to the first and second pixel circuits PC1and PC2. The composite layer200will be described in detail below.

Hereinafter, the elements included in the display apparatus10will be described. The display apparatus10may include a substrate100, a barrier layer101, a buffer layer111, a circuit layer PCL, the composite layer200, and a display element layer EDL, which are sequentially stacked.

The substrate100may include an insulating material such as glass, quartz, or a polymer resin. In some embodiments, the substrate100may include inorganic insulating layers and organic insulating layers, which are alternately arranged. The substrate100may include a flexible substrate that is bendable, foldable, or rollable.

The buffer layer111may be disposed on the substrate100and may reduce or prevent influence of a foreign material, moisture, or ambient air from below the substrate100, and may provide a flat surface on the substrate100. The buffer layer111may include an inorganic material, such as an oxide or nitride, an organic material, or an organic-inorganic composite material, and may have a single layer structure or a multilayer structure including an inorganic material or an organic material. In some embodiments, the buffer layer111may include silicon oxide (SiOx) or silicon nitride (SiNx). In some embodiments, the buffer layer111may include a stack of silicon oxide (SiOx) or silicon nitride (SiNx).

The barrier layer101may be disposed between the substrate100and the buffer layer111so as to block penetration of external air. The barrier layer101may include silicon oxide (SiOx) or silicon nitride (SiNx).

The circuit layer PCL may be arranged on the buffer layer111and may include first and second pixel circuits PC1and PC2, a first gate insulating layer112, a second gate insulating layer113, an interlayer insulating layer115, and a planarization layer117. The first pixel circuit PC1may include a first thin-film transistor TFT1and a first storage capacitor Cst1. The second pixel circuit PC2may include a second thin-film transistor TFT2and a second storage capacitor Cst2. The configuration of the second pixel circuit PC2is substantially the same as the configuration of the first pixel circuit PC1, and thus, the descriptions of the first pixel circuit PC1may apply to the second pixel circuit PC2.

The first thin-film transistor TFT1may be arranged on the buffer layer111. The first thin-film transistor TFT1includes a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first thin-film transistor TFT1may be connected to the first organic light-emitting diode OLED1and may be configured to drive the first organic light-emitting diode OLED1.

The first semiconductor layer A1may be arranged on the buffer layer111and may include polysilicon. In another embodiment, the first semiconductor layer A1may include amorphous silicon. In still another embodiment, the first semiconductor layer A1may include an oxide of at least one selected from indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The first semiconductor layer A1may include a channel region, and a source region, and a drain region doped with impurities.

The first gate insulating layer112may cover the first semiconductor layer A1. The first gate insulating layer112may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The first gate insulating layer112may include a single layer or a multilayer including the above-described inorganic insulating material.

The first gate electrode G1may be arranged on the first gate insulating layer112such that the first gate electrode G1overlaps the first semiconductor layer A1. The first gate electrode G1may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single layer or a multilayer. For example, the first gate electrode G1may include a single Mo layer.

The second gate insulating layer113may cover the first gate electrode G1. The second gate insulating layer113may include an inorganic insulating material, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The second gate insulating layer113may include a single layer or a multilayer including the above-described inorganic insulating material.

A first upper electrode CE2of the first storage capacitor Cst1may be arranged on the second gate insulating layer113. The first upper electrode CE2may overlap the first gate electrode G1arranged thereunder. The first gate electrode G1and the first upper electrode CE2, which overlap each other with the second gate insulating layer113therebetween, may constitute the first storage capacitor Cst1. In this case, the first gate electrode G1may function as a first lower electrode CE1of the first storage capacitor Cst1.

The first upper electrode CE2may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu), and may include a single layer or a multilayer including the above-described material. In some embodiments, the first upper electrode CE2may include a single Mo layer.

The interlayer insulating layer115may cover the first upper electrode CE2. The interlayer insulating layer115may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The interlayer insulating layer115may include a single layer or a multilayer including the above-described inorganic insulating material.

A data line DL, a first source electrode S1, and a first drain electrode D1may be arranged on the interlayer insulating layer115. The data line DL, the first source electrode S1, and the first drain electrode D1may each include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and may each include a single layer or a multilayer including the above-described material. For example, the data line DL, the first source electrode S1, and the first drain electrode D1may each have a multilayer structure of Ti/Al/Ti.

The planarization layer117may be arranged to cover the data line DL, the first source electrode S1, and the first drain electrode D1. The planarization layer117may provide a flat upper surface such that the elements arranged thereon are formed on the flat surface.

The planarization layer117may include an organic material or an inorganic material, and may have a single layer structure or a multilayer structure. The planarization layer117may include a general-purpose polymer (e.g., benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS)), a polymer derivative having a phenol-based group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, or a vinyl alcohol-based polymer. The planarization layer117may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). When the planarization layer117is formed, a layer may be formed and chemical mechanical polishing may be performed on the layer so as to provide a flat upper surface.

A first connection electrode CM1, a second connection electrode CM2, and a wiring WL may be arranged on the planarization layer117. Due to the composite layer200, the wiring WL may be further arranged on the planarization layer117, which may be advantageous for high integration. The first connection electrode CM1may be configured to connect the first pixel circuit PC1to the first organic light-emitting diode OLED1. More particularly, the planarization layer117may include a via hole exposing one of the first source electrode S1and the first drain electrode D1, and the first connection electrode CM1may be in contact with the first source electrode S1or the first drain electrode D1via the via hole, such that the first connection electrode CM1is electrically connected to the first thin-film transistor TFT1. Also, the first pixel electrode121aof the first organic light-emitting diode OLED1may be connected to the first connection electrode CM1. Similarly, the second connection electrode CM2may be configured to connect the second pixel circuit PC2to the second organic light-emitting diode OLED2.

The composite layer200may be arranged on the circuit layer PCL. The composite layer200may cover the first connection electrode CM1, the second connection electrode CM2, and the wiring WL, which are arranged on the planarization layer117. The composite layer200may include the first inorganic insulating layer210, the first organic insulating layer220, and the second inorganic insulating layer230, which are sequentially stacked. More particularly, the composite layer200may have a structure in which an organic insulating layer is sandwiched between inorganic insulating layers.

The composite layer200may prevent external impacts from being transmitted to the first and second pixel circuits PC1and PC2. The composite layer200may be disposed between the first and second pixel circuits PC1and PC2and the first and second organic light-emitting diodes OLED1and OLED2, which are the display elements, such that impacts transmitted from above the display elements are prevented from being transmitted to the first and second pixel circuits PC1and PC2.

When only the organic insulating layer is disposed between the first and second pixel circuits PC1and PC2and the first and second organic light-emitting diodes OLED1and OLED2, impacts may be absorbed to some extent due to characteristics thereof. However, large impacts may not be completely absorbed and some impacts may be transmitted to the first and second pixel circuits PC1and PC2.

In the illustrated embodiment, the composite layer200includes the first inorganic insulating layer210and the second inorganic insulating layer230, each having high strength, below and above the first organic insulating layer220, respectively. In this manner, before impacts are transmitted to the lower portion of the composite layer200, the first inorganic insulating layer210and the second inorganic insulating layer230may absorb and disperse the impacts. In this case, the first organic insulating layer220may provide a flat upper surface and absorb impacts.

In some embodiments, the strength of each of the first inorganic insulating layer210and the second inorganic insulating layer230may be in a range of about 80 GPa to about 200 GPa, and the strength of the first organic insulating layer220may be in a range of about 1 GPa to about 10 GPa. In this manner, the composite layer200may disperse and absorb impacts.

In some embodiments, the thickness of each of the first inorganic insulating layer210and the second inorganic insulating layer230may be in a range of about 1,000 Å to about 3,000 Å, and the thickness of the first organic insulating layer220may be in a range of about 10,000 Å to about 20,000 Å. In this manner, the composite layer200may disperse and absorb impacts.

The composite layer200may include a first contact hole CNT1exposing the first connection electrode CM1and a second contact hole CNT2exposing the second connection electrode CM2. The first organic light-emitting diode OLED1and the second organic light-emitting diode OLED2may be respectively connected to the first pixel circuit PC1and the second pixel circuit PC2via the first contact hole CNT1and the second contact hole CNT2. The first contact hole CNT1and the second contact hole CNT2may be formed by stacking the first inorganic insulating layer210, the first organic insulating layer220, and the second inorganic insulating layer230, and performing photoresist patterning and etching processes thereon.

A display element layer EDL is arranged on the composite layer200. A first organic light-emitting diode OLED1and a second organic light-emitting diode OLED2may be arranged on the display element layer EDL.

The first pixel electrode121aand the second pixel electrode121bmay each include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The first pixel electrode121aand the second pixel electrode121bmay each include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any compounds thereof. For example, the first pixel electrode121aand the second pixel electrode121bmay each have a structure in which layers including ITO, IZO, ZnO, or In2O3are arranged above and/or below the reflective layer. In this case, the first pixel electrode121aand the second pixel electrode121bmay each have a stack structure of ITO/Ag/ITO.

The first pixel electrode121amay be connected to the first connection electrode CM1via the first contact hole CNT1defined in the composite layer200. The second pixel electrode121bmay be connected to the second connection electrode CM2via the second contact hole CNT2defined in the composite layer200.

The pixel defining layer119may include a first opening OP1and a second opening OP2respectively covering edges of the first pixel electrode121aand the second pixel electrode121band exposing central portions of the first pixel electrode121aand the second pixel electrode121b. The first opening OP1and the second opening OP2define the sizes and shapes of emission areas of the first and second organic light-emitting diodes OLED1and OLED2, that is, the pixels P1and P2, respectively.

The pixel defining layer119increases a distance between the edges of the first and second pixel electrodes121aand121band the opposite electrodes123above the first and second pixel electrodes121aand121b, thereby preventing arcs or the like from occurring at the edges of the first and second pixel electrodes121aand121b. The pixel defining layer119may include at least one organic insulating material such as polyimide, polyamide, an acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and a phenol resin, and may be formed by spin coating or the like.

A first emission layer122aand a second emission layer122brespectively formed to correspond to the first pixel electrode121aand the second pixel electrode121bmay be arranged in the first opening OP1and the second opening OP2of the pixel defining layer119, respectively. The first emission layer122aand the second emission layer122bmay each include a high molecular weight material or a low molecular weight material, and may each emit red light, green light, blue light, or white light.

Organic functional layers may be arranged above and/or below the first emission layer122aand the second emission layer122b. The organic functional layers may each include a single layer or a multilayer including an organic material. The organic functional layers may include a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer

(ETL), and/or an electron injection layer (EIL). The organic functional layers may be integrally formed to correspond to the first and second organic light-emitting diodes OLED1and OLED2arranged in the display area.

Opposite electrodes123are arranged on the first emission layer122aand the second emission layer122b. The opposite electrode123may include a conductive material having a low work function. For example, the opposite electrode123may include a (semi)transparent layer including, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the opposite electrodes123may each further include a layer, such as ITO, IZO, ZnO, or In2O3on the (semi)transparent layer including the above-mentioned material. The opposite electrodes123may be integrally formed to correspond to the first and second organic light-emitting diodes OLED1and OLED2arranged in the display area.

A capping layer including an organic material may be arranged on the opposite electrodes123. The capping layer may protect the opposite electrodes123and increase light extraction efficiency. The capping layer may include an organic material having a refractive index greater than that of the opposite electrode123.

Also, a thin-film encapsulation layer may be arranged on the display element layer EDL as a sealing member. In this manner, the first and second organic light-emitting diodes OLED1and OLED2may be sealed by the thin-film encapsulation layer. The thin-film encapsulation layer may prevent external moisture or foreign material from penetrating into the first and second organic light-emitting diodes OLED1and OLED2. The thin-film encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In some embodiments, the thin-film encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, which are sequentially stacked.

The first inorganic encapsulation layer and the second inorganic encapsulation layer may each include at least one inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), and may each be formed by chemical vapor deposition (CVD). The organic encapsulation layer may include a polymer-based material. The polymer-based material may include a silicon-based resin, an acrylic resin, an epoxy-based resin, polyimide, polyethylene, and the like.

FIG.4is a schematic cross-sectional view of a portion of a display apparatus according to an embodiment. InFIG.4, the elements that are substantially the same as those inFIG.3will be given the same reference numerals.

The display apparatus according to the illustrated embodiment includes first and second pixel circuits PC1and PC2arranged in a display area of a substrate100, first and second organic light-emitting diodes OLED1and OLED2respectively connected to the first and second pixel circuits PC1and PC2, a composite layer200between the first and second pixel circuits PC1and PC2, and the first and second organic light-emitting diodes OLED1and OLED2. The composite layer200includes a first inorganic insulating layer210, a first organic insulating layer220, and a second inorganic insulating layer230, which are sequentially stacked.

In the illustrated embodiment, the composite layer200may further include a lower organic insulating layer221below the first inorganic insulating layer210. The lower organic insulating layer221may be arranged on a planarization layer117to cover connection lines CM1and CM2. As the composite layer200further includes the lower organic insulating layer221, impact absorption and flatness of the upper surface of the composite layer200may be improved.

In some embodiments, the strength of each of the first inorganic insulating layer210and the second inorganic insulating layer230may be in a range of about 80 GPa to about 200 GPa, and the strength of each of the first organic insulating layer220and the lower organic insulating layer221may be in a range of about 1 GPa to about 10 GPa. In this manner, the composite layer200may disperse and absorb impacts.

In some embodiments, the thickness of each of the first inorganic insulating layer210and the second inorganic insulating layer230may be in a range of about 1,000 Å to about 3,000 Å, and the thickness of each of the first organic insulating layer220and the lower organic insulating layer221may be in a range of about 10,000 Å to about 20,000 Å. In this manner, the composite layer200may disperse and absorb impacts.

FIG.5is a schematic cross-sectional view of a portion of a display apparatus according to an embodiment. InFIG.5, the elements that are substantially the same as those inFIG.3will be given the same reference numerals.

The display apparatus according to the illustrated embodiment includes first and second pixel circuits PC1and PC2arranged in a display area of a substrate100, first and second organic light-emitting diodes OLED1and OLED2respectively connected to the first and second pixel circuits PC1and PC2, a composite layer200between the first and second pixel circuits PC1and PC2, and the first and second organic light-emitting diodes OLED1and OLED2. The composite layer200includes a first inorganic insulating layer210, a first organic insulating layer220, and a second inorganic insulating layer230, which are sequentially stacked.

In the illustrated embodiment, the composite layer200may further include an upper organic insulating layer223above the second inorganic insulating layer230. The upper organic insulating layer223may be disposed between the second inorganic insulating layer230and first and second pixel electrodes121aand121bof the first and second organic light-emitting diodes OLED1and OLED2. As the composite layer200further includes the upper organic insulating layer223, impact absorption and flatness of the upper surface of the composite layer200may be improved.

In some embodiments, the strength of each of the first inorganic insulating layer210and the second inorganic insulating layer230may be in a range of about 80 GPa to about 200 GPa, and the strength of each of the first organic insulating layer220and the upper organic insulating layer223may be in a range of about 1 GPa to about 10 GPa. In this manner, the composite layer200may disperse and absorb impacts.

In some embodiments, the thickness of each of the first inorganic insulating layer210and the second inorganic insulating layer230may be in a range of about 1,000 Å to about 3,000 Å, and the thickness of each of the first organic insulating layer220and the upper organic insulating layer223may be in a range of about 10,000 Å to about 20,000 Å. In this manner, the composite layer200may disperse and absorb impacts.

FIG.6is a schematic cross-sectional view of a portion of a display apparatus according to an embodiment. InFIG.6, the elements that are substantially the same as those inFIG.3will be given the same reference numerals.

The display apparatus according to the illustrated embodiment includes first and second pixel circuits PC1and PC2arranged in a display area of a substrate100, first and second organic light-emitting diodes OLED1and OLED2respectively connected to the first and second pixel circuits PC1and PC2, a composite layer200between the first and second pixel circuits PC1and PC2, and the first and second organic light-emitting diodes OLED1and OLED2.

The composite layer200according to the illustrated embodiment may include a first inorganic insulating layer210, a first organic insulating layer220, a second inorganic insulating layer230, a second organic insulating layer240, and a third inorganic insulating layer250, which are sequentially stacked.

As the composite layer200further includes the second organic insulating layer240and the third inorganic insulating layer250, impact dispersion and flatness of the upper surface of the composite layer200may be improved.

In some embodiments, the strength of each of the first inorganic insulating layer210, the second inorganic insulating layer230, and the third inorganic insulating layer250may be in a range of about 80 GPa to about 200 GPa, and the strength of each of the first organic insulating layer220and the second organic insulating layer240may be in a range of about 1 GPa to about 10 GPa. In this manner, the composite layer200may disperse and absorb impacts.

In some embodiments, the thickness of each of the first inorganic insulating layer210, the second inorganic insulating layer230, and the third inorganic insulating layer250may be in a range of about 1,000 Å to about 3,000 Å, and the thickness of each of the first organic insulating layer220and the second organic insulating layer240may be in a range of about 10,000 Å to about 20,000 Å. In this manner, the composite layer200may disperse and absorb impacts.

However, the inventive concepts are not limited thereto. The composite layer200in other embodiments may further include additional organic insulating layers and additional inorganic insulating layers alternately arranged one over another.

FIG.7is a schematic cross-sectional view of a portion of a display apparatus according to an embodiment. InFIG.7, the elements that are substantially the same as those inFIG.3will be given the same reference numerals.

The display apparatus according to the illustrated embodiment includes first and second pixel circuits PC1and PC2arranged in a display area of a substrate100, first and second organic light-emitting diodes OLED1and OLED2respectively connected to the first and second pixel circuits PC1and PC2, a composite layer200between the first and second pixel circuits PC1and PC2, and the first and second organic light-emitting diodes OLED1and OLED2. The composite layer200includes a first inorganic insulating layer210, a first organic insulating layer220, and a second inorganic insulating layer230, which are sequentially stacked.

The display apparatus according to the illustrated embodiment further includes an inorganic material layer IL having an opening or a groove GR in an area between pixel circuits PC1and PC2, and an organic material layer161may fill the opening or the groove GR. Also, a connection line140may be arranged on the organic material layer161.

In an embodiment, a barrier layer101, a buffer layer111, a first gate insulating layer112, a second gate insulating layer113, and an interlayer insulating layer115, which are arranged below the connection line140and include an inorganic material, may be collectively referred to as the inorganic material layer IL. The inorganic material layer IL has an opening or a groove GR in an area between neighboring pixel circuits.

FIG.7illustrates that the inorganic material layer IL has the groove GR. More particularly, the barrier layer101may be continuous across a first pixel circuit PC1and a second pixel circuit PC2of neighboring pixels. The buffer layer111, the first gate insulating layer112, the second gate insulating layer113, and the interlayer insulating layer115may have openings111a,112a,113a, and115ain an area between the neighboring pixels, respectively.

As such, the barrier layer101, the buffer layer111, the first gate insulating layer112, the second gate insulating layer113, and the interlayer insulating layer115may have a groove GR in an area between the neighboring pixels, respectively. The groove GR may refer to a trench formed in the inorganic material layer IL.

The opening of the inorganic material layer IL may refer that openings are formed in each of the barrier layer101, the buffer layer111, the first gate insulating layer112, the second gate insulating layer113, and the interlayer insulating layer115, such that the substrate110is exposed.

The inorganic material layer IL may include various different types of grooves in other embodiments. For example, a portion of the upper surface of the barrier layer101may also be removed, or the lower surface of the buffer layer111may be retained without being removed.

A width of the groove GR of the inorganic material layer IL may be several μm. For example, a width GRW of the groove GR of the inorganic material layer IL may have be in a range of about 5 μm to about 10 μm.

The opening or the groove GR may be formed by performing a separate mask process and an etching process on the interlayer insulating layer115. The openings111a,112a,113a, and115aof the buffer layer111, the first gate insulating layer112, the second gate insulating layer113, and the interlayer insulating layer115may be formed by the etching process. The etching process may be a dry etching process.

The groove GR of the inorganic insulating layer may be filled with an organic material layer161. The connection line140is located above the organic material layer161where the organic material layer161is present. The opening or the groove GR of the inorganic material layer IL and the organic material layer161may be at least partially disposed between adjacent pixel circuits.

The openings or the grooves GR of the inorganic insulating layer and the organic material layer161may significantly reduce the influence of external impacts on the display apparatus. The inorganic insulating layer has the opening or the groove GR in the area between the pixel circuits, and the organic material layer161fills the opening or the groove GR. As such, even when there are external impacts, the probability of crack propagation becomes extremely low. In addition, since the organic material layer161has a hardness lower than that of the inorganic material layer, the organic material layer161absorbs stress caused by external impacts. Accordingly, stress concentration on the connection line140located on the organic material layer161may be significantly reduced in an effective manner.

The organic material layer161fills at least a portion of the groove GR of the inorganic insulating layer between the first pixel circuit PC1and the second pixel circuit PC2. In some embodiments, the organic material layer161may not completely fill the groove GR, or may not fill a portion of the groove GR.

However, in order for the organic material layer161to absorb external impacts, the organic material layer161may completely fill the groove GR. In some embodiments, the organic material layer161may extend to the upper surface of the inorganic insulating layer. In this case, due to the characteristics of the organic material layer161, the upper surface of the organic material layer161may have a convex shape. More particularly, a maximum height h of the organic material layer161may be greater than a depth d of the groove GR.

An angle between the upper surface of the organic material layer161and the upper surface of the inorganic material layer IL may be within 45°. When a slope of a boundary area where the upper surface of the inorganic insulating layer and the upper surface of the organic material layer161meet is not gentle, the conductive material may remain in a corresponding region without being removed from the boundary region during the process of forming the connection line140by patterning the conductive layer. In this case, the remaining conductive material may cause a short circuit between other conductive layers. Therefore, the upper surface of the organic material layer161may be formed to have a gentle slope with respect to the upper surface of the inorganic insulating layer.

The connection line140may be arranged on the organic material layer161and configured to connect the first and second pixel circuits PC1and PC2to each other. The connection line140may also be located on the inorganic insulating layer in an area where the organic material layer161is not present. The connection line140may function as a wiring to transmit electrical signals to the first and second pixel circuits PC1and PC2.

As the connection line140includes a material having high elongation, it is possible to prevent defects such as cracking or disconnection from occurring in the connection line140. In some embodiments, the connection line140may have a stack structure of Ti/Al/Ti. In some embodiments, the elongation of the connection line140may be greater than the elongation of the conductive layers arranged thereunder.

FIG.8is a schematic cross-sectional view of a portion of a display apparatus according to an embodiment. InFIG.8, the elements that are substantially the same as those inFIGS.3and7will be given the same reference numerals.

The display apparatus according to the illustrated embodiment includes first and second pixel circuits PC1and PC2arranged in a display area of a substrate100, first and second organic light-emitting diodes OLED1and OLED2respectively connected to the first and second pixel circuits PC1and PC2, a composite layer200between the first and second pixel circuits PC1and PC2, and the first and second organic light-emitting diodes OLED1and OLED2. The composite layer200includes a first inorganic insulating layer210, a first organic insulating layer220, and a second inorganic insulating layer230, which are sequentially stacked.

The display apparatus according to the illustrated embodiment additionally includes an inorganic material layer IL′ having an opening or a groove GR′ in an area between the first and second pixel circuits PC1and PC2, and an organic interlayer insulating layer115′ arranged on the front surface of the substrate100to fill the groove GR′.

In an embodiment, a barrier layer101, a buffer layer111, a first gate insulating layer112, and a second gate insulating layer113, which include an inorganic material, may be collectively referred to as an inorganic material layer IL′. The inorganic material layer IL′ has an opening or a groove GR′ in an area between neighboring pixel circuits.

FIG.8illustrates that the inorganic material layer IL′ has the groove GR′. More particularly, the barrier layer101may be continuous across a first pixel circuit PC1and a second pixel circuit PC2of neighboring pixels. The buffer layer111, the first gate insulating layer112, and the second gate insulating layer113may have openings111a,112a, and113ain an area between the neighboring pixels, respectively.

The opening of the inorganic material layer IL' may refer that openings are formed in each of the barrier layer101, the buffer layer111, the first gate insulating layer112, and the second gate insulating layer113, such that the upper surface of the substrate100is exposed. The inorganic material layer IL′ may include various different types of grooves. For example, a portion of the upper surface of the barrier layer101may also be removed, or the lower surface of the buffer layer111may be retained without being removed.

The organic interlayer insulating layer115′ may cover storage capacitors Cst1and Cst2above the second gate insulating layer113. Also, the organic interlayer insulating layer115′ may fill the groove GR′ to prevent propagation of cracks.

In the illustrated embodiment, the connection line140may be arranged on the organic interlayer insulating layer115′ and connect the first and second pixel circuits PC1and PC2to each other. When the organic interlayer insulating layer115′ provides a flat upper surface, the connection line140may also have a flat upper surface. The connection line140may function as a wiring to transmit electrical signals to the first and second pixel circuits PC1and PC2.

FIGS.9and10are plan views illustrating grooves GR and GR′ ofFIG.7or8according to embodiments.

The openings or the grooves GR and GR′ of the inorganic insulating layer may be arranged to at least partially surround the periphery of the pixel circuits. Referring toFIG.9, the openings or the grooves GR and GR′ of the inorganic insulating layer may be arranged to surround the periphery of the first pixel circuit PC1and the second pixel circuit PC2. Alternatively, referring toFIG.10, openings or grooves GR and GR′ of an inorganic insulating layer may be arranged to surround a plurality of pixel circuits. For example, the openings or the grooves GR and GR′ of the inorganic insulating layer are arranged to surround two pixel circuits, that is, a first pixel circuit PC1and a second pixel circuit PC2, as shown inFIG.10. The number of pixels grouped by the grooves GR and GR′ may be variously changed in other embodiments.

The number of pixel circuits grouped by the grooves GR and GR′ may be the same in one display apparatus, or may be changed according to positions. For example, the opening or the groove GR of the inorganic insulating layer may be arranged to surround one pixel circuit in an area where there is a high risk of cracking or stress, and may be arranged to surround a plurality of pixel circuits in other areas. Alternatively, the opening or the groove GR of the inorganic insulating layer may be partially formed in a display area.

FIGS.11and12are schematic diagrams of display apparatuses according to embodiments.FIG.11illustrates that a display area is folded, andFIG.12illustrates that a display area is rolled.

The display apparatuses according to embodiments are robust against external impacts, and thus, the display area DA may be foldable or rollable as shown inFIGS.11and12.

More particularly, because a composite layer configured to distribute and absorb external impacts is between a pixel circuit and a display element, external impacts may be prevented or at least suppressed from being transmitted to the pixel circuit even when the display area DA is folded or rolled. Also, when the opening or the groove GR of the inorganic insulating layer is provided, an organic material layer or an organic interlayer insulating layer filling the groove GR may absorb tensile stress caused by bending.

FIG.13illustrates a result of testing impact resistance of the display apparatus according to an embodiment.FIG.13shows data obtained by measuring a leakage current between the semiconductor layer and the gate electrode while a pen is dropped on the display area DA from a predetermined height.

(a) ofFIG.13shows test data for a display apparatus of Comparative Example that does not include a composite layer or a groove in an inorganic insulating layer, (b) ofFIG.13shows test data for a display apparatus that includes the composite layer ofFIG.3, and (c) ofFIG.13shows test data for a display apparatus that includes a composite layer and a groove in an inorganic insulating layer as illustrated inFIG.7.

In the case of Comparative Example as shown in (a) ofFIG.13, a leakage current of 10 pA or more occurred when the pen was dropped from a height of 3 cm or more, but in the case of (b) ofFIG.13, a leakage current of 10 pA or more does not occur even when the pen is dropped from a height of 5 cm. Also, in the case of (c) ofFIG.13, it can be confirmed that even when the pen is dropped from a height of 8 cm, a leakage current of 10 pA or more does not occur. As such, it can be confirmed that the display apparatus according to embodiment is robust against external impacts.

As described above, because the composite layer in which the first inorganic insulating layer, the first organic insulating layer, and the second inorganic insulating layer are stacked is between the pixel circuit and the display element, the display apparatuses according to embodiments may be robust against external impacts.

Also, because the display apparatuses according to the embodiments include the inorganic insulating layer having the opening or the groove in an area between the pixels, and the organic material layer filling the opening or the groove, the display apparatuses according to the embodiments may be flexible and robust against external impacts.