Determination of worst case voltage in a power supply loop

Various systems, methods, and programs embodied in a computer readable medium are provided for determining a worst-case impedance and worst-case voltage of a power supply loop coupled to a power input of a die. In various embodiments, the worst-case impedance of a power supply loop is determined and a reference voltage at the power input of the die associated with an average current generated at a power supply included in the power supply loop. A maximum change in a current at the power input of the die is also measured and an estimate of a worst-case voltage at the power input of the die is calculated based upon the worst-case impedance, the reference voltage, and the maximum change in the current.

BACKGROUND

Development of microprocessor technology has seen decreasing power supply voltages that are more susceptible to interference by noise, decreasing signal transition times, decreasing die sizes, increasing power supply currents, and increasing clock speeds. As a result, ever more significant demands are placed upon the power supplies of microprocessor circuits. Such demands typically result in significant voltage and current variation between power and ground conductors.

Knowledge as to the nature of the extreme voltages that occur between a microprocessor power and ground due to the operation of a microprocessor or other type of circuit is useful for estimating power distribution performance and for predicting signal integrity in a microprocessor. However, current approaches are inadequate to determine such extreme voltages.

DETAILED DESCRIPTION

With reference toFIG. 1, shown is a schematic block diagram of a central processing unit (CPU) circuit board100upon which is mounted a CPU package103. The CPU package103comprises packaging106and at least one semiconductor die109. In addition, a power supply113is also included on the CPU circuit board100. In other embodiments, the power supply113may be located within the CPU package103. The power supply113may be, for example, a voltage regulator or other appropriate device or circuit as can be appreciated by those with ordinary skill in the art. The power supply113generates voltage Vsupplyand current Iddthat is seen at a power input116of the die109. The CPU package103includes test points119that facilitate measuring the voltage V across the power input116of the die109. Specifically, the voltage V is the difference between the voltage Vddand the common Vss.

The power supply113generates system voltage VSupplythat is supplied to the die109during operation of the die109. The voltage VSupplyis the voltage between power and ground. A power supply loop exists that includes the power supply113and the conductors121that couple the power supply113to the power input116of the die109. Such conductors121may include, for example, a ground plane (i.e. solid or grid), a power plane (i.e. solid or grid), vias, traces, de-coupling capacitors, bumps, and/or other circuit elements. The voltage V is seen at the power input116of the die109, where V=Vdd−Vss. In this respect, the voltage V may not equal the voltage VSupplydue to the impedance in the conductors between the power supply113and the power input of the die109and due to other circumstances as can be appreciated by those with ordinary skill in the art. The power supply113may also provide voltage and current to other components (not shown) in the packaging106and on the CPU circuit board100.

In order to allow a user to measure the voltage V across Vddand Vss, conductors are provided that link Vddand Vssto the test points119. These conductors make up a transmission line123between the voltage V input of the die109to the test points119. The transmission line123includes resistance RTL1.

A differential probe126is employed to obtain a measure of the voltage V. The differential probe126includes cables or other conductors that make up a transmission line129that is coupled to the inputs of a comparator133. The transmission line129includes resistance RTL2. The transmission line129is configured to contact the test points119on the CPU package103. Together, the transmission lines123and129make up a transmission line131between the power input116of the die109and the inputs of the comparator133of the differential probe126. In this respect, the resistance of the transmission line131is noted as RTLwhich is the sum of the resistances RTL1and RTL2. In this respect, the characteristic impedance of the transmission lines123and129are matched as close a possible so as to minimize reflections at the junction between the transmission lines123and129as can be appreciated.

The differential probe126may include a terminal resistance RTERMthat is coupled across the inputs to the comparator133. The output of the differential probe126is applied to an oscilloscope136to view the resulting waveform. A voltage Vwis specified as the voltage across the terminal resistor RTERMthat is input into the comparator133.

The differential probe126is employed, for example, to measure the voltage V at the power input of the die109. The resistance of the termination resistance RTERMis calculated so as to minimize reflection of the voltage signals reaching the comparator133. However, given that such reflections are generally of high frequency, the termination resistance RTERMmay not be necessary if high frequency reflections or noise is of no concern. In such a case, the high frequency noise may be filtered out of the signal obtained as will be described. To measure the voltage V, the conductor that make up the transmission line129are coupled to the test points119. In the case that the termination resistance RTERMis employed, the voltage Vwis measured over a period of time (Vw(t)) and is stored in a memory associated, for example, with the oscilloscope136. The voltage V(t) may then be calculated from the voltage Vw(t), the termination resistance RTERM, and the transmission line resistance RTLof the transmission line131.

If the termination resistance RTERMis not employed, then the voltage V may be measured and stored as a function of time (V(t)) in a memory associated, for example, with the oscilloscope136. In such case, it is assumed that the voltage V(t) is the same as the voltage Vw(t) measured across the inputs of the comparator133since the comparator133includes a near infinite input resistance and there is negligible current on the transmission line131. The voltage V(t) may be stored, for example, on a computer readable medium that is accessed for further analysis and calculation as will be discussed. In addition, the voltage V(t) may be subjected to filter to eliminate or minimize any unwanted high frequency components as mentioned above when the voltage V(t) is measured without the termination resistance RTERM. For a more detailed discussion of the measuring of the voltage V as described herein, reference is made to US Patent Application entitled “Measuring Current on a Die” filed on Dec. 22, 2003 and assigned Ser. No. 10/745,101.

Any one of a number of processes may be executed on the die109while various measurements of the voltage and current at the power supply113and the power input116of the die109are obtained. For example, one such process is defined herein as a “cold” process that includes any algorithm that generates a low power requirement on the die109resulting in a relatively low constant current Iddwhen executed on the die109. Such a cold process may be, for example, a process that merely includes the running of a clock associated with the die109at a relatively low frequency. In this respect, the current Iddincreases or decreases with a corresponding increase or decrease in the clock frequency. The low current Iddgenerated by the cold process may experience some fluctuation. Consequently, it is understood that to be “relatively constant” as contemplated herein means to be constant to the extent practicable under the circumstances. Alternatively, other algorithms may be employed that effectively serve as cold processes to generate the relatively low constant current Iddas contemplated herein.

A “hot” process is any algorithm that generates a high power requirement on the die109resulting in a relatively high constant current Iddwhen executed on the die109. In this respect, the relatively high constant current Iddis generally greater than the relatively low constant current Iddgenerated by the cold process. For example, a hot process may be a process that runs a clock associated with the die109at a relatively high frequency given that the current Iddgenerally increases with an increase in the clock frequency. Also, such an algorithm may include repeated instructions such as repeated AND instructions, repeated OR instructions, or other repeated instructions. The repeated instructions and the high frequency clock that occur during the execution of a hot process results in the relatively high constant current Idd. Alternatively, other algorithms may be employed that effectively serve as hot processes as contemplated herein.

An “aggressive” process involves an algorithm that results in significant fluctuation of the current Iddwhen executed on the die109. In this respect, an aggressive process may involve switching of memories, control of I/O, and other operations that maximize the change in the current Idd.

In addition, a “constant” process as described herein involves an algorithm that results in a relatively constant current Idd, regardless of the magnitude of the current Idd. In this respect, both the hot or cold processes as described above are also “constant” processes. Also, a constant process may be implemented that generates a current Iddthat is neither high or low. Ultimately, a constant current is one in which the fluctuation of the current Iddis minimized to the extent practicable. Various processes that qualify as the hot, cold, aggressive, and constant process may be commercially available.

According to various embodiments of the present invention, any one of the hot, cold, aggressive, or constant processes may be executed in the die109from time to time to obtain measurement of current and voltage at various points as will be described. In addition, an alternating hot and cold process may be executed on the die109that results in an input current Iddat the power input116that mimics a periodic waveform. In this respect, an alternating hot and cold process is one that periodically alternates between the execution of a hot process and a cold process.

With reference toFIG. 2, shown is one example of a method for calculating a worst-case voltage experienced at the power input116(FIG. 1) of the die109(FIG. 1). Beginning with step139, a worst-case impedance Rwof the power supply loop that is coupled to the power input116of the die109is determined. The determination of the worst-case impedance Rwinvolves several steps as will be described. Once the worst-case impedance Rwis determined, then in step141a reference voltage VREFat the power input116of the die109is determined. In this respect, the reference voltage VREFis associated with an average current IAVGthat is generated by the power supply113in the power supply loop during the execution of a constant process such as a hot process on the die109as will be described. A more detailed description of the determination of the reference voltage VREFis provided in the discussion that follows.

Once the reference voltage VREFhas been determined, then the method proceeds to step143in which an estimate is determined of a maximum change in the current Idd, denoted herein as ΔIdd, Max, that is experienced at the power input116of the die109. In this respect, an aggressive process is executed on the die109that causes maximum fluctuation in the current Iddat the power input116. A measure of the current Iddis derived from the measure of the voltage V(t) obtained during the execution of the aggressive process in the die109and a measure of the impedance Zfof the power supply loop. The estimate of the maximum change in the current ΔIdd, Maxis determined from the measure of the current Iddtaken while the aggressive process is executed on the die109. The aggressive process may be, for example, any one of a number of commercially available aggressive processes. Where a number of aggressive processes are available, one may determine the aggressive process that generates the greatest change in the current Iddby trial and error.

To obtain a measure of the current Iddfrom the measure of the voltage V(t), reference is made to co-pending U.S. patent application entitled “Measuring Current on a Die”, filed on Dec. 22, 2003 and assigned Ser. No. 10/745,101, which is incorporated herein by reference. Alternatively, other approaches may be employed to obtain an adequate measure of the current Iddas is known by those with ordinary skill in the art.

Next, in step146, the maximum worst-case voltage V experienced at the power input116is calculated as
Vwc,max=VREF+Rw(ΔIdd,max),
where VREFis the reference voltage, Rwis the worst-case impedance, and ΔIdd,max, is the maximum change in the current Idddetermined while running the aggressive process executed in step143above. Thereafter, in step149the minimum worst-case voltage is calculated as
tiVwc,min=VREF−Rw(ΔIdd,max).
Thereafter, the method ends as shown.

With reference toFIG. 3, shown is a flow chart that illustrates one approach that may be taken to determine the worst-case impedance Rwof the power supply loop coupled to the power input116as set forth in step139(FIG. 2) above according to an embodiment of the present invention. Beginning with step153, first a measure is taken of the impedance of the power supply loop as a function of frequency, denoted herein as impedance Zf(ω). In this respect, the impedance Zf(ω) is determined as a function of frequency and is expressed in both magnitude and phase. In order to determine the impedance Zf(ω), the approaches may be employed as described in U.S. patent application entitled “System and Method of Measuring Low Impedance” filed on Oct. 21, 2002 and assigned Ser. No. 10/274,611, and U.S. patent application entitled “System and Method of Measuring Well Impedances” filed on Oct. 21, 2002 and assigned Ser. No. 10/274,787, both of which are incorporated herein by reference. Alternatively, the impedance Zf(ω) of the power supply loop may be ascertained using other approaches as can be appreciated with ordinary skill in the art.

With reference toFIG. 4, shown is a graph that depicts an example of a measure of the impedance Zf(ω) of the power supply loop as a function of frequency. Once a measure of the impedance Zf(ω) of the power supply loop is obtained and stored in step153, then in step156the frequency f1of the right-most peak corresponding to a resonance in the power supply loop is identified in the impedance profile of the impedance Zf(ω) measured in box153. In this respect, a number of resonances may exist in the frequency spectrum of the impedance Zf(ω). However, the frequency of the right-most peak of resonance is selected. Note that peaks that are the result of noise such as, for example, those seen in ripples or other peaks resulting from noise are disregarded.

Referring back toFIG. 3, next in step159, an alternating hot and cold process is executed on the die109, thereby resulting in an alternating current Iddexperienced at the power input116of the die109due to the periodic varying load presented by the alternating hot and cold process. In this regard, the current Idd(FIG. 1) experienced at the power input116of the die109mimics a periodic waveform. The alternating hot and cold process is configured such that the resulting periodic waveform has a period T that is specified as
T>A/f1,
where A is approximately equal to 20. Alternatively, A may be greater or less than 20. In this respect, A is specified so as to make sure that a half-period of the periodic waveform is large enough so that all significant minimum and maximum voltages can be measured as will be described.

Then, in step163, a measure is taken of the voltage V(t) at the power input116of the die109between Vddand Vssfor at least one half-period of the periodic waveform while the alternating hot and cold process is executed on the die109. In this respect, the voltage V(t) may approximate a periodic waveform. The measure of the voltage V(t) taken in step163is stored in an appropriate memory. Next, in step166, a half-period of the measure of the voltage V(t) is isolated for further scrutiny. In this respect, the half-period may exist after a positive voltage transition in the periodic waveform or during a negative voltage transition in the periodic waveform. Next, in box169, if it is determined that the half-period isolated in box166has occurred after a positive voltage transition, then the method proceeds to box173. Otherwise, the present method proceeds to box176.

To facilitate further discussion of the method described inFIG. 4, reference is made toFIG. 5that shows a graph of a half-period of the periodic waveform of the current Idd(t) generated at the power input116of the die109by virtue of the execution of the alternating hot and cold process. In this respect, the current Idd(t) as shown is an ideal estimate of the actual current Idd(t) that may include a certain amount of noise and other fluctuation as can be appreciated with ordinary skill in the art.

Superimposed over the waveform showing the current Idd(t) is the voltage V(t) that illustrates the response of the voltage V(t) during the half cycle of the current Idd(t) while the alternating hot and cold process is executed on the die109. The response of the voltage V(t) includes a number of significant maximum and minimum voltages V1−Nas the voltage V(t) experiences oscillation in what is an underdamped response. The voltage V0is the voltage V(t) before the respective negative or positive transition of the current Idd(t). The voltages V0−Nare ultimately measured and stored in order to be used to calculate the worst-case impedance Rwas will be described.

Given that that the period T of the periodic waveform is approximately equal to 20 times the period of the right-most peak frequency f1on the impedance profile of Zfas described above, then all significant minimum and maximum voltages V1−Nof the response of the voltage V(t) should appear within the half cycle, where the voltage V0appears just before the transition at the beginning of the half-cycle. In this respect, the voltage V0is defined herein as a pre-transition voltage. Thus, if a positive transition is experienced in the voltage V(t) at the beginning of the half-period, then the last measured voltage VNshould be a maximum voltage. Correspondingly, if a negative voltage transition is experienced in the voltage V(t) at the beginning of the half-period, then the last measured voltage VNshould be a minimum voltage. In any event, the total number of measured voltages VNshould be an even number, where N is odd. The total number of measured voltages VNis specified so as to ensure that an adequate amount of information is obtained from the response of the voltage V(t) to provide for a meaningful estimate of the worst-case impedance Rwas will be described. To the extent that an even number of measured voltages VNare not achieved, then the period T needs to be increased, where
T>A/f1.

Referring back toFIG. 4, assuming that the voltage transition before the half-period is a positive voltage transition, then in step173it is determined whether the last measured voltage VNof the response of the voltage V(t) during the half-period is a maximum voltage. If so, then the present method progresses to step179. Otherwise, the present method proceeds to step183.

Assuming that the last measured voltage VNidentified in step173, then in step183the period T of the alternating hot and cold process is increased by a predefined amount of time. In this respect, the half-period is extended so that the last measured voltage VNof the response of the voltage V(t) is a maximum voltage. Then, in step186the alternating hot and cold process is re-executed on the die109and the method reverts back to step163to obtain a new measure of the voltage V(t) that is then stored as described above.

With reference back to step169, if the transition of the voltage V(t) before the half-period is a negative voltage transition, then the method proceeds to step176in which it is determined whether the last measured voltage VNof the response of the voltage V(t) is a minimum voltage. If not, then the method reverts to step183as shown. Otherwise, the method proceeds to step179. In this respect, whether a positive or negative transition in the voltage V(t) before the half-period occurs, the last measured voltage VNshould be a maximum or minimum that matches the transition or the period T needs to be increased.

In step179, the pre-transition voltage V0and all of the maximums and minimums of the voltage response of the voltage V(t) that occur in the isolated half-period of the periodic waveform of the current Idd(t) resulting from the alternating hot and cold process are identified and stored in a memory for further use. Then, in step189, a measure of the average current Iddexperienced at the power input116of the die109is obtained while a hot process is executed in the die109. This average current is denoted as current Idd, Hot. This step may involve, for example, averaging of samples of the current Iddmeasured over a period of time to obtain the average current Iddto further minimize any fluctuation that may be experienced. Next, in box191, a measure of the average current Iddexperienced at the power input116of the die109is obtained while a cold process is executed in the die109. This average current is denoted herein as current Idd, Cold. This step may involve, for example, averaging of samples of the current Iddmeasured over a period of time to obtain the average current Iddto further minimize any fluctuation that may be experienced. Then, in step193, the difference in the current Idd, between the current Idd, Hotand Idd, Cold, denoted herein as ΔIdd, is determined.

Next, in box196, the worst-case impedance Rwis calculated using the pre-transition voltage V0which is the voltage V before the transition at the beginning of the half-period, the recorded maximum and minimum voltages V1−NOf the response of the voltage V(t) in the isolated half-period, and the estimate of the change in the current ΔIddat the power input116of the die109according to the following equation

Rw=∑i=0M⁢V2⁢i-V2⁢i+1Δ⁢⁢Idd.
where M is equal to (N+1)/2, where N is the total number of measured voltages V0−N. Thereafter, the method for determining the worst-case impedance Rwends as shown.

With reference toFIG. 6, shown is a flow chart that illustrates an example of the steps taken to determine the reference voltage in step141ofFIG. 2described above according to an embodiment of the present invention. To begin, in step199, a constant process is executed on the die109that results in the generation of a constant current Icat the power input116(FIG. 1) of the die109(FIG. 1). Next, in step203the constant current Icis measured at the power supply113. In order to measure the current Icat the power supply113(FIG. 1), various approaches may be employed, including, for example, measuring a voltage drop across a known resistance and calculating the current therefrom or some other approach may be employed.

Thereafter, in step206, the voltage V(t) at the power input116of the die109is measured during the execution of the constant process that generates the constant current IC. The measure of the voltage V(t) is stored for future use as will be described.

Next, in step209, the resistance RSLof the power supply loop coupled to the power input116of the die109is calculated. In this respect, the voltage generated by the power supply113denoted herein as VSupplyis known, the voltage at the power input116is known, and the current Icis known. Consequently, the resistance RSLof the power supply loop is calculated as

RSL=(VSupply-V)Ic,
where VSupplyis the voltage generated by the power supply113.

Next, in step213an aggressive process is executed on the die109to generate the current Iddthat experiences significant fluctuation or change at the power input116of the die109.

Then, in step216, the average current IAVGis measured at the power supply113while the aggressive process is executed as was discussed in step213. In this respect, the current is measured at the power supply113and the resulting samples of current are averaged over time to obtain the average current IAVG.

Next, in box219, the reference voltage VREFat the power input116of the die109is calculated according to the following equation
VREF=VSupply−IAVG(RSL),
where VSupplyis the voltage generated at the power supply113. Thereafter, the method for determining the reference voltage VREFends as shown.

In addition, it is understood that while the steps of the method depicted in the flow charts ofFIGS. 2,3, and5appear in a predefined order, it is understood that the order of the steps may vary from that depicted.

With reference toFIG. 7, shown is a block diagram of a computer system250according to an embodiment of the present invention. In this respect, the computer system250may be, for example, a desktop, laptop, personal digital assistant, or other type of system with like capability as can be appreciated with those with ordinary skill in the art.

The computer system250includes a central processing unit251that includes a processor circuit having a processor253and a memory256, both of which are coupled to a local interface259. In this respect, the local interface259may comprise, for example, a data bus with an accompanying control/address bus as can be appreciated by those with ordinary skill in the art. In addition, the computer system250may include a display device263, a keyboard266, and a mouse269. In addition, the computer system250may include other peripheral devices such as, for example, keypad, touch pad, touch screen, microphone, scanner, joystick, or one or more push buttons, etc. The peripheral devices may also include additional display devices, indicator lights, speakers, printers, etc. The display device263may be, for example, a cathode ray tube (CRT), liquid crystal display screen, gas plasma-based flat panel display, or other type of display device, etc.

Stored on the memory256and executable by the processor253are an operating system273and a worst-case voltage calculator276. In addition, other applications and processes may be stored in the memory256and executed by the processor253as can be appreciated. A number of data files are stored in the memory256and are accessed and/or manipulated by the worst-case voltage calculator276. These data files include, for example, a hot/cold process voltage V(t) data file279, a cold process Idd(t) data file281, a hot process Idd(t) data file283, and an aggressive process Idd(t) data file286. The data files279,281,283,286are accessed by the worst-case voltage calculator276as is appropriate to calculate a worst-case impedance Rwand the worst-case voltage V(t) as will be described.

As contemplated herein, the term “executable” means a program file that is in a form that can run by the processor or transformed into a format that can ultimately be run by the processor253. Examples of executable programs may be, for example, a compiled program that can be translated into machine code in a format that can be loaded into a random access portion of the memory256and run by the processor253, or source code that may be expressed in proper format such as object code that is capable of being loaded into a of random access portion of the memory256and executed by the processor253, etc. An executable program may be stored in any portion or component of the memory256including, for example, random access memory, read-only memory, a hard drive, compact disk (CD), floppy disk, or other memory components.

In addition, the processor253may represent multiple processors and the memory256may represent multiple memories that operate in parallel. In such a case, the local interface259may be an appropriate network that facilitates communication between any two of the multiple processors, between any processor and any one of the memories, or between any two of the memories etc. The processor253may be of electrical, optical, or molecular construction, or of some other construction as can be appreciated by those with ordinary skill in the art.

The operating system273is executed to control the allocation and usage of hardware resources such as the memory, processing time and peripheral devices in the computer system250. In this manner, the operating system273serves as the foundation on which applications depend as is generally known by those with ordinary skill in the art.

Referring next toFIG. 8, shown is a flow chart that provides one example of the operation of the worst-case voltage calculator276according to an embodiment of the present invention. Alternatively, the flow chart ofFIG. 8may be viewed as depicting steps of an example of a method implemented in the computer system100to determine a worst-case impedance Rwand a worst-case voltage V. The functionality of the worst-case voltage calculator276as depicted by the example flow chart ofFIG. 8may be implemented, for example, in an object oriented design or in some other programming architecture. Assuming the functionality is implemented in an object oriented design, then each block represents functionality that may be implemented in one or more methods that are encapsulated in one or more objects. The worst-case voltage calculator276may be implemented using any one of a number of programming languages such as, for example, C, C++, Assembly Language, or other programming languages.

Beginning with box303, the period T (FIG. 5) of the alternating hot and cold process that is executed on the die109(FIG. 1) as illustrated inFIG. 5above is input by the worst-case voltage calculator276. To input the period T, the worst-case voltage calculator276may generate an appropriate user interface on the display device263, for example, that facilitates a user input of the period T using input devices such as the keyboard266(FIG. 7) or the mouse269(FIG. 7). Similarly, the worst-case voltage calculator276may generate other user interfaces on the display device263that may facilitate a user input of other information and data files that are employed by the worst-case voltage calculator276as will be described.

Next, in box306, the worst-case voltage calculator276inputs the hot and cold process voltage V(t) data file279(FIG. 7) for use in calculation to follow. In this respect, the hot and cold process voltage process V(t) data file279includes data that represents the voltage V(t) that approximates a periodic waveform as described above with reference toFIG. 5. The hot and cold process voltage V(t) data file279is generated during the execution of the alternating hot and cold process on the die109as described above. To input the hot and cold process voltage V(t) data file279, a user may manipulate an appropriate interface on the display device263to specify a position in the memory256of the data file itself using a browse function for access by the worst-case voltage calculator276.

Thereafter, in box309, the worst-case voltage calculator276inputs the cold process current Idd(t) data file281for future manipulation. Then, in box311, the worst-case voltage calculator276inputs the hot process current Idd(t) data file283. The inputting of the hot and cold process current Idd(t) data files281and283is performed in a manner similar to the hot and cold process voltage V(t) data file279discussed above. The hot and cold process Idd(t) data files281and283each include data that represents the current at the power input116of the die109during the execution of the hot process and the cold process on the die109, respectively, as was described with reference to the method ofFIG. 4.

Thereafter, in box313, the worst-case voltage calculator276determines a worst-case impedance Rwof the power supply loop coupled to the power input116(FIG. 1) of the die109. An example of specific functionality executed to determine the worst-case impedance Rwdescribed in box313will be described with reference toFIG. 9. Next, in box316, the worst-case voltage calculator276inputs the aggressive process current Idd(t) data file286(FIG. 7) that includes data that represents the current Iddat the power input116of the die109while the aggressive process is executed on the die109as described with regard to the method ofFIG. 2above.

Next, in box319, a reference voltage VREFis input into the worst-case voltage calculator276. In this respect, the reference voltage VREFmay be determined as was described with reference toFIG. 6or using some other approach. Next, in box323, an estimate of a maximum change in the current Idd, denoted herein as the change of current ΔIdd, Max, is determined from the aggressive process current Idd(t) data file286. In this respect, the maximum change in the current ΔIdd, Maxis determined from the aggressive process current Idd(t) data file286that includes data that embodies the current Idd(t) measured as the aggressive process is executed on the die109. In this respect, the aggressive process current Idd(t) data file286provides the best estimate of the current Idd(t) from which the maximum change in the current ΔIdd, Maxmay be determined in box323. In this respect, the maximum change in the current ΔIdd, Maxmay be determined by measuring the magnitude of the difference between the highest and lowest current in the current Idd(t).

Next, in box326, the worst-case voltage calculator276calculates an estimate of the maximum worst-case voltage V as
Vwc,max=VREF+Rw(ΔIdd,Max),
where VREFis the reference voltage, Rwis the worst-case impedance, and ΔIdd,max, is the maximum change in the current Idd(t) determined from the aggressive process current Idd(t) data file286Thereafter, in box329, an estimate of the minimum worst-case voltage V is calculated as
Vwc,min=VREF−Rw(ΔIdd,Max).

In this respect, the calculation of the estimates of the maximum worst-case voltage Vwc, Maxand the minimum worst-case voltages Vwc, Minis thus based upon a number of factors including the worst-case impedance Rw, the estimated maximum change in the current ΔIdd, Maxat the power input116of the die109, and the reference voltage VREFat the power input of the die109. In this respect, the reference voltage VREFis associated with the average current IAVGgenerated at the power supply113(FIG. 1).

Next, in box333, the worst-case voltage calculator276renders the maximum worst-case voltage Vwc, maxand the minimum worst-case voltages Vwc, minto the user, for example, by display on the display device263in an appropriate user interface, by printing on an appropriate print medium using a printer, or by using some other approach, etc. Thereafter, the worst-case voltage calculator276ends as shown.

Referring next toFIG. 9, shown is a flow chart that provides one example of the operation of a portion of the worst-case voltage calculator276in determining the worst-case impedance Rwof the power supply loop coupled to the power input116(FIG. 1) of the die109(FIG. 1) according to an embodiment of the present invention. Alternatively, the flow chart ofFIG. 9may be viewed as depicting steps of an example of a method implemented in the computer system250to determine the worst-case impedance Rwof the power supply loop coupled to the power input116(FIG. 1) of the die109(FIG. 1). The functionality of the portion of the worst-case voltage calculator276as depicted by the example flow chart ofFIG. 9may be implemented, for example, in an object oriented design or in some other programming architecture. Assuming the functionality is implemented in an object oriented design, then each block represents functionality that may be implemented in one or more methods that are encapsulated in one or more objects. The portion of the worst-case voltage calculator276described inFIG. 9may be implemented using any one of a number of programming languages such as, for example, C, C++, Assembler, or other programming languages.

Beginning with box353, the worst-case voltage calculator276isolates a half-period of a voltage V(t) expressed in the hot and cold process voltage V(t) data file279to be examined to obtain the pre-transition voltage V0and the minimum and maximum voltages V1−Nfor the response of the voltage V(t). Thereafter, in box356the pre-transition voltage V0and all maximum and minimum voltages V1−Nof the response of the voltage V(t) in the half-period are identified. The pre-transition voltage V0and the maximum and minimum voltages V1−Nare identified in the voltage V(t) as was described with reference toFIG. 5above.

Thereafter, in box359, the worst-case voltage calculator276determines whether the voltage transition at the beginning of the half-period of the voltage V(t) is a positive voltage transition. If so, then the worst-case voltage calculator276proceeds to box363. Otherwise, the worst-case voltage calculator276progresses to box366. This determination may be made, for example, by comparing the magnitude of the voltage V(t) near the end of the half-period with the magnitude of the voltage V(t) just before the transition. If the change in the voltage V(t) between these two points is positive, then the transition is a positive transition. If the change is negative, then the transition is a negative transition.

Assuming the transition to be positive, then in box366the worst-case voltage calculator276determines whether the last measured voltage VNof the response of the voltage V(t) is a maximum. If not, then the worst-case voltage calculator276proceeds to box369. Otherwise, the worst-case voltage calculator276progresses to box373. In box369, an appropriate message is displayed to the user or otherwise rendered for the user that informs the user that the analysis could not be completed as the period T (FIG. 5) of the periodic waveform presented by the hot and cold process executed on the die109is too small. Thereafter, the worst-case voltage calculator276ends.

Assuming that the transition is determined to be a negative voltage transition in box359, then in box366, the worst-case voltage calculator276determines whether the last measured voltage VNin the response of the voltage V(t) in the half-period is a minimum. If so then the worst-case voltage calculator276proceeds to box373. Otherwise, the worst-case voltage calculator276reverts to box369as shown.

In box373, the pre-transition voltage V0and all maximum voltages and minimum voltages of the response of the voltage V(t) within the half-period are stored in the memory256. Thereafter, in box376the worst-case voltage calculator276determines the average current Idd-Coldfrom the cold process current Idd(t) data file281by averaging a number of samples of the cold process current Idd(t) data file281over time. Similarly, in box279, the worst-case voltage calculator276determines the average current Idd-Hotfrom the hot process current Idd(t) data file283by averaging a number of samples of the cold process current Idd(t) data file283over time. The averaging functions performed in box276and279server to further minimize any fluctuation in the hot and cold process current Idd(t). Then, in box383, the difference between the hot and cold average currents Idd-Hotand Idd-Cold, denoted as current ΔIdd, is calculated. Thereafter, in box386, the worst-case impedance Rwof the power supply loop that is coupled to the power input116of the die109is calculated from the pre-transition voltage, the maximum voltages and the minimum voltages of the response of the voltage V(t), and the estimate of the change in the current ΔIddat the power input116of the die109. In this respect, the calculation of the worst-case impedance Rwmay be performed using the following equation

Rw=∑i=0M⁢V2⁢i-V2⁢i+1Δ⁢⁢Idd,
where Rwis the worst-case impedance, M is equal to (N+1)/2, where N is the total number of measured voltages V0−N, Vxis the magnitude of the respective measured voltages of the response, and ΔIddis the estimate of the change in the current at the power input of the die. Thereafter, the portion of the worst-case voltage calculator276that determines the worst-case impedance Rwends as shown.

Although the worst-case voltage calculator276is embodied in software or code executed by general purpose hardware as discussed above, as an alternative it may also be embodied in dedicated hardware or a combination of software/general purpose hardware and dedicated hardware. If embodied in dedicated hardware, the worst-case voltage calculator276can be implemented as a circuit or state machine that employs any one of or a combination of a number of technologies. These technologies may include, but are not limited to, discrete logic circuits having logic gates for implementing various logic functions upon an application of one or more data signals, application specific integrated circuits having appropriate logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), or other components, etc. Such technologies are generally well known by those skilled in the art and, consequently, are not described in detail herein.

The flow charts ofFIGS. 8 and 9show the architecture, functionality, and operation of an implementation of the worst-case voltage calculator276. If embodied in software, each block may represent a module, segment, or portion of code that comprises program instructions to implement the specified logical function(s). The program instructions may be embodied in the form of source code that comprises human-readable statements written in a programming language or machine code that comprises numerical instructions recognizable by a suitable execution system such as a processor in a computer system or other system. The machine code may be converted from the source code, etc. If embodied in hardware, each block may represent a circuit or a number of interconnected circuits to implement the specified logical function(s).

Also, where the worst-case voltage calculator276comprises software or code, it can be embodied in any computer-readable medium for use by or in connection with an instruction execution system such as, for example, a processor in a computer system or other system. In this sense, the logic may comprise, for example, statements including instructions and declarations that can be fetched from the computer-readable medium and executed by the instruction execution system. In the context of the present invention, a “computer-readable medium” can be any medium that can contain, store, or maintain the worst-case voltage calculator276for use by or in connection with the instruction execution system. The computer readable medium can comprise any one of many physical media such as, for example, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor media. More specific examples of a suitable computer-readable medium would include, but are not limited to, magnetic tapes, magnetic floppy diskettes, magnetic hard drives, or compact discs. Also, the computer-readable medium may be a random access memory (RAM) including, for example, static random access memory (SRAM) and dynamic random access memory (DRAM), or magnetic random access memory (MRAM). In addition, the computer-readable medium may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or other type of memory device.