Frequency doubler

A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different phases, and an XOR circuit receiving the N signals and outputting a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority from Korean Patent Application No. 10-2014-0106070, filed on Aug. 14, 2014 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The present inventive concepts relate to a frequency doubler, and more particularly a frequency doubler having a voltage controlled oscillator and an XOR gate.

2. Description of the Related Art

A phase locked loop (PLL) is typically used in various kinds of electronic circuits. In particular, the phase locked loop is important to a communication circuit. In a wireless communication system, a wireless device (e.g., a cellular phone) generally uses a clock signal in the case of a digital circuit, and uses an LO signal in the case of a transmitter and receiver circuit. The clock signal and the LO signal are generated by using a voltage-controlled oscillator (VCO) that mainly operates in the PLL.

The phase locked loop generally includes a phase frequency detector, a charge pump, a loop filter, a VCO, and an XOR gate. In general, the phase frequency detector, the charge pump, and the loop filter detect a phase error between a reference signal and a clock signal, which are obtained from the VCO, and generates a control signal Vctrl for the VCO. The control signal controls the frequency of the VCO so that the clock signal is synchronized with the reference signal. The XOR gate may receive a multi-phase signal to double the frequency of the VCO.

SUMMARY

In one aspect, embodiments of the present inventive concepts provide a frequency doubler which has a low deterministic jitter regardless of a change of a process.

In another aspect, embodiments of the present inventive concepts provide an XOR gate which is included in a frequency doubler which has a low deterministic jitter regardless of a change of a process.

According to an aspect of the present inventive concepts, there is provided a frequency doubler including a voltage controlled oscillator configured to output N signals having a first period and having different phases, N being a natural number, and an XOR circuit configured to receive the N signals and output a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node.

According to another aspect of the present inventive concepts, there is provided an XOR gate including a first input inverter including a first PMOS transistor and a first NMOS transistor, a second input inverter including the first PMOS transistor and a second NMOS transistor that is different from the first NMOS transistor, a third input inverter including a second PMOS transistor and a third NMOS transistor, and a fourth input inverter including the second PMOS transistor and a fourth NMOS transistor that is different from the third NMOS transistor, a first output inverter connected to a drain of the first PMOS transistor and including a third PMOS transistor and a fifth NMOS transistor, and a second output inverter connected to a drain of the second PMOS transistor and including the third PMOS transistor and a sixth NMOS transistor that is different from the fifth NMOS transistor, wherein outputs of the first and second input inverters are connected to an input of the first output inverter, and outputs of the third and fourth input inverters are connected to an input of the second output inverter.

According to still another aspect of the present inventive concepts, there is provided A frequency doubler including a voltage controlled oscillator configured to output first to fourth signals having a first period and having different phases, the first to fourth signals being corresponding to first to fourth nodes, and an XOR circuit configured to receive the first to fourth signals and output a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes a first stage including a first inverter unit configured to invert a signal of the first node and output the inverted signal to the second node, a second inverter unit configured to invert a signal of the third node that is different from the first node and output the inverted signal to the fourth node that is different from the second node, and a third inverter unit configured to invert a signal of the second node to output the inverted signal to the fourth node, or invert a signal of the fourth node to output the inverted signal to the second node, and a second stage including a fourth inverter unit configured to invert the signal of the second node and output the inverted signal to the third node, a fifth inverter unit configured to invert the signal of the fourth node and output the inverted signal to the first node, and a sixth inverter unit configured to invert the signal of the third node to output the inverted signal to the first node, or invert the signal of the first node to output the inverted signal to the third node, and the XOR circuit includes a first unit block set including first to fourth unit blocks that are connected to a first output node and correspond to the first to fourth nodes, respectively, and a second unit block set including fifth to eighth unit blocks that are connected to a second output node and correspond to the first to fourth nodes, respectively, wherein the first unit block set and the second unit block set have substantially the same circuit configurations.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, referring toFIGS. 1 to 18, a semiconductor device according to exemplary embodiments of the present inventive concepts and a phase locked loop including the same will be described.

FIG. 1is a block diagram illustrating a phase locked loop according to exemplary embodiments of the present inventive concepts.

Referring toFIG. 1, according to exemplary embodiments of the present inventive concepts, a phase locked loop may include a phase frequency detector (PFD)10, a charge pump (CP)20, a loop filter (LF)30, a voltage controlled oscillator (VCO)100, a divider50, and an XOR gate200.

The phase frequency detector10may receive a reference signal Ref from a reference oscillator (not shown inFIG. 1), and may receive a clock signal Clk from the divider50. The phase frequency detector10compares phases of the received reference signal Ref with the clock signal Clk, and provides an up signal UP and a down signal DN that indicate a phase error or a phase difference between the reference signal Ref and the clock signal Clk.

The clock signal Clk may be called a divided clock signal or a feedback signal. Further, the up signal UP and the down signal DN may be called an early signal and a late signal, or a forward signal and a delay signal. More specifically, the phase frequency detector10of the phase locked loop generates a pair of signals that are generally called the up signal UP and the down signal DN. The pair of signals may be generally in a turn-on state for a longer time than the turn-on time of the reference signal Ref in each clock cycle depending on whether the clock signal Clk is leading or lagging in comparison to the reference signal Ref.

The charge pump20receives the up signal UP and the down signal DN, and generates an output signal Icp, and the output signal Icp is a current signal that indicates the detected phase error.

The loop filter30may generate a control signal Vctrl for the VCO100by filtering the output signal Icp from the charge pump20. The loop filter30may control the control signal Vctrl so that the phase or frequency of the clock signal Clk is synchronized with the phase or frequency of the reference signal Ref. The loop filter30may have a selected frequency response to achieve a preferable closed-loop response with respect to the PLL110. For example, the frequency response of the loop filter30may be selected on the basis of a gain and a tradeoff between a tracking performance and a PLL noise performance. However, the present inventive concepts are not limited thereto. The loop filter30may include a low pass filter LPF.

The voltage controlled oscillator100may generate an oscillator signal having a frequency that is determined by the control signal Vctrl generated from the loop filter30. The voltage controlled oscillator100may output N (where, N is a natural number) signals having different phases.

The XOR gate200may receive the oscillator signal that is output from the voltage controlled oscillator100, and may output a signal having a frequency that is double the frequency of the oscillator signal.

The divider50supplies the clock signal Clk, which is obtained by dividing the frequency of the oscillator signal output from the voltage controlled oscillator100by an integer factor N or N+1, to the phase frequency detector10. In general, N may be a certain positive integer value.

The phase locked loop according to exemplary embodiments of the present inventive concepts may be used in various kinds of circuits, such as an integer-N PLL, a fraction-N PLL, a multi-modulus device (MMD), and a sigma-delta frequency synthesizer. The integer-N PLL divides the frequency of the oscillator signal from the voltage controlled oscillator by an integer divider ratio N, and in this case, N is N>1. The fraction-N PLL divides the frequency of the oscillator signal by a divider ratio R that is not an integer, for example, by N in a certain case, or by N+1 in another case, and in this case, N is N<R<N+1. The sigma-delta frequency synthesizer may use a sigma-delta modulator (not illustrated) in order to generate the divider ratio R that is not an integer.

FIG. 2is a block diagram of a frequency doubler according to an exemplary embodiment of the present inventive concepts.

Referring toFIG. 2, a frequency doubler1according to an exemplary embodiment of the present inventive concepts may include a voltage controlled oscillator100and an XOR gate200.

The voltage controlled oscillator100may generate a signal having an output frequency Fo that corresponds to the input voltage Vctrl. The voltage controlled oscillator100may output N (where, N is a natural number) signals which have a first period and different phases. For example, the voltage controlled oscillator100may output first to fourth signals having different phases. However, the present inventive concepts are not limited thereto.

There may be a phase difference of 1/N period between the N-th signal and the (N−1)-th signal output from the voltage controlled oscillator100. For example, in the case of the voltage controlled oscillator100that outputs the first to fourth signals, there may be a phase difference of 90° between the first signal and the second signal. That is, the first signal may have a phase of 0°, and the second signal may have a phase of 90°. Further, the third signal may have a phase of 180°, and the fourth signal may have a phase of 270°. In this case, the third signal corresponds to an inverted signal of the first signal, and the fourth signal corresponds to an inverted signal of the second signal. However, the present inventive concepts are not limited thereto.

Although not illustrated, the voltage controlled oscillator100may include a ring VCO (not illustrated). An output frequency of the ring VCO (not illustrated) may be determined by time delays of respective delay cells and the number of stages. Accordingly, in order to design a high-speed voltage controlled oscillator, it is required to reduce the number of stages and a unit time delay. Once a semiconductor process is determined, the maximum frequency may be limited by the minimum time delay of a delay element. In order to generate an output frequency that is equal to or higher than the frequency that is limited to the minimum time delay, there may be a multiplying method using a ring VCO that outputs a multi-phase signal.

The XOR gate200may receive N signals that are output from the voltage controlled oscillator100and may output a signal having a second period that corresponds to a half of the first period. That is, the XOR gate may output an output signal 2×Fo that is double the output frequency Fo output from the voltage controlled oscillator100. The XOR gate200may double the output frequency of the ring VCO that outputs the multi-phase signal. However, if two input signals that are input to the XOR gate200do not have the same propagation delay, the time delay between the input signals may differ, and thus the value of a deterministic jitter (DJ) may be increased. The deterministic jitter (DJ) of the frequency doubler1that includes the voltage controlled oscillator100and the XOR gate200may be changed due to differences in 1) uniformity of time delays between delay units, 2) uniformity of propagation delays between the delay units, and 3) R/C time constant between metal lines from the delay unit to the XOR gate200.

FIG. 3is a block diagram illustrating a voltage controlled oscillator according to an exemplary embodiment of the present inventive concepts, andFIG. 4is a circuit diagram illustrating an inverter that is included in an inverter unit of a voltage controlled oscillator according to an exemplary embodiment of the present inventive concepts.

Referring toFIGS. 2 and 4, the voltage controlled oscillator100according to an exemplary embodiment of the present inventive concepts may include a first stage182and a second stage184. The voltage controlled oscillator100may include N nodes that correspond to N signals having different N phases, and a plurality of inverter units connected to the N nodes, respectively.

For example, the voltage controlled oscillator100may output first to fourth signals having different phases, and may include first to fourth nodes BB, A, B and AB that correspond to the first to fourth signals. In this case, a signal having a phase of 0° may be output at the second node A172, and a signal having a phase of 90° may be output at the third node (B174. Further, a signal having a phase of 180° may be output at the fourth node AB176, and a signal having a phase of 270° may be output at the first node BB178. However, the present inventive concepts are not limited thereto, but the phases of the respective signals may vary in a predetermined ratio. However, the phase difference between the respective signals may be kept constant.

That is, the voltage controlled oscillator100may include a 2-stage ring oscillator circuit that generates four multi-phase clocks having the phases of 0°, 90°, 180°, and 270°. The four multi-phase clocks may correspond to the first to fourth signals of the N nodes BB, A, B and AB. However, the present inventive concepts are not limited thereto.

The voltage controlled oscillator100may include the plurality of inverter units110to160. The first stage182may include the first inverter unit110that inverts the signal of the first node BB to output the inverted signal to the second node A, the second inverter unit120that inverts the signal of the third node B to output the inverted signal to the fourth node AB, and the third inverter unit130that inverts the signal of the second node A to output the inverted signal to the fourth node AB or inverts the signal of the fourth node AB to output the inverted signal to the second node A.

The second stage184may include the fourth inverter unit140that inverts the signal of the second node A to output the inverted signal to the third node B, the fifth inverter unit150that inverts the signal of the fourth node AB to output the inverted signal to the first node BB, and the sixth inverter unit160that inverts the signal of the third node B to output the inverted signal to the first node BB or inverts the signal of the first node BB to output the inverted signal to the third node B.

Each of the first inverter unit110and the second inverter unit120of the first stage182may include a pair of inverters that share the same input node and output node. That is, a first inverter112and a second inverter114of the first inverter unit110may have input terminals connected to the first node BB and output terminals connected to the second node A. In the same manner, a first inverter122and a second inverter124of the second inverter unit120may have input terminals connected to the first node BB and output terminals connected to the second node A.

The third inverter unit130may include a first inverter132that inverts the signal of the second node A to output the inverted signal to the fourth node AB and a second inverter134that inverts the signal of the fourth node AB to output the inverted signal to the second node A.

Each of the fourth inverter unit140and the fifth inverter unit150of the second stage184may include a pair of inverters that share the same input node and output node. That is, a first inverter142and a second inverter144of the fourth inverter unit140may have input terminals connected to the second node A and output terminals connected to the third node B. In the same manner, a first inverter152and a second inverter154of the fifth inverter unit150may have input terminals connected to the fourth node AB and output terminals connected to the first node BB.

The sixth inverter unit160may include a first inverter162that inverts the signal of the third node B to output the inverted signal to the first node BB and a second inverter164that inverts the signal of the first node BB to output the inverted signal to the third node B.

The first stage182and the second stage184may be configured substantially in the same manner, and may be symmetrically arranged on a substrate.

The plurality of inverter units110to160may be connected between the N nodes BB, A, B and AB corresponding to the N signals, each of which is generated by an inverter chain having a same number of the plurality of inverter units110to160. The voltage controlled oscillator100includes a plurality of inverter units connected to N nodes corresponding to the N signals, each of the N signals being generated by a same number of the plurality of inverter units on a recursive path. In other words, the N nodes BB, A, B and AB may be arranged so that, if a signal that starts from any one start node of the N nodes BB, A, B and AB passes through the same number of inverter units, it recurs to the corresponding start node.

For example, if the signal that starts from the second node A sequentially passes through the fourth inverter unit140, the sixth inverter unit160, and the first inverter unit110, it recurs to the second node A. In the same manner, if the signal that starts from the third node B sequentially passes through the second inverter unit120, the third inverter130, and the fourth inverter unit140, it recurs to the third node B. According to the voltage controlled oscillator100having the four nodes BB, A, B and AB according to an exemplary embodiment of the present inventive concepts as described above, if the signal passes through three inverter units, it recurs to its start node. This means that the signals that are output from the respective nodes may have equal time delays.

Further, the voltage controlled oscillator100may include a same type inverters to provide substantially equal time delays between phases. As described above, each of the first to sixth inverter units110to160may include a same type of two inverters.

Referring toFIG. 4, the first to sixth inverter units110to160may be composed of same inverters. The inverter (e.g.,112) may include a PMOS transistor TR1and an NMOS transistor TR2. A source of the PMOS transistor TR1is connected to a VDD terminal, and a drain thereof is connected to a drain of the NMOS transistor TR2. The source of the NMOS transistor TR2is connected to a VSS terminal. The gates of the PMOS transistor TR1and the NMOS transistor TR2are connected to the same input terminal IN, the drains of the PMOS transistor TR1and the NMOS transistor TR2are connected to the same output terminal OUT. However, the configuration of the inverters according to the present inventive concepts is not limited thereto.

FIG. 5is a block diagram illustrating the voltage controlled oscillator ofFIG. 3in another way, andFIG. 6is a diagram illustrating a plurality of metal lines connected to a voltage controlled oscillator according to an exemplary embodiment of the present inventive concepts. Hereinafter, for convenience in explanation, the duplicate explanation of the same terms as those according to the above-described embodiment will be omitted, and explanation will be made around different points between the exemplary embodiments.

FIG. 5illustrates a schematic and layout pattern of the voltage controlled oscillator100that can reduce the mismatch between the transistors and the R/C time constant mismatch. The voltage controlled oscillator100may include 12 inverters having the same size. Further, the first to sixth inverter units110to160, each of which may include a pair of inverters, may be arranged in a common centroid manner to reduce certain random mismatch effects of the transistors.

As described above, the plurality of inverter units110to160may be connected between the N nodes BB, A, B and AB corresponding to the N signals, each of which is generated by an inverter chain having a same number of the plurality of inverter units110to160. That is, the inverter units110to160may be arranged so that, if a signal that starts from any one start node of the respective nodes passes through the same number of the inverter units, it recurs to the corresponding start node. In this case, since the signals that are output from the respective nodes have the same routing paths, the mismatch between the transistors and the R/C time constant mismatch can be reduced.

Specifically, the first inverter unit110and the second inverter unit120of the first stage182may be symmetrically arranged about the third inverter unit130. In the same manner, the fourth inverter unit140and the sixth inverter unit160of the second stage184may be symmetrically arranged about the fifth inverter unit150. The first stage182and the second stage184may be configured substantially in the same manner, and may be symmetrically arranged with each other on a substrate. However, the present inventive concepts are not limited thereto.

Referring toFIG. 6, each of the first stage182and the second stage184may include first to fourth nodes BB, A, B and AB. The node of the first stage182and the node of the second stage184may be connected to the plurality of metal lines.

The plurality of metal lines may include a plurality of horizontal-axis metal lines L1to L8and a plurality of vertical-axis metal lines V1to V4. The plurality of horizontal-axis metal lines L1to L8may include a plurality of metal lines which are horizontally arranged and have the same length, and the plurality of vertical-axis metal lines V1to V4may include a plurality of metal lines which are vertically arranged and have the same length. For example, a first plurality of horizontal-axis metal lines L1to L4may be arranged at predetermined intervals to overlap the first to third inverter units110,120and130of the first stage182. In the same manner, a second plurality of horizontal-axis metal lines L5to L8may be arranged at predetermined intervals to overlap the fourth to sixth inverter units140,150and160. However, the present inventive concepts are not limited thereto.

The plurality of vertical-axis metal lines V1to V4may be arranged to pass the centers of the first stage182and the second stage184. For example, the plurality of vertical-axis metal lines V1to V4may be arranged at predetermined intervals to overlap the third inverter unit130and the sixth inverter unit160. However, the present inventive concepts are not limited thereto.

The first plurality of horizontal-axis metal lines L1to L4may be connected to the first to fourth nodes of the first stage182, respectively. For example, a first horizontal-axis metal line L1may be connected to the second node A, and a second horizontal-axis metal line L2may be connected to the fourth node AB. However, the present inventive concepts are not limited thereto. In the same manner, the second plurality of horizontal-axis metal lines L5to L8may be connected to the first to fourth nodes of the second stage184, respectively.

Each of the plurality of vertical-axis metal lines V1to V4may connect the first plurality of horizontal-axis metal lines L1to L4and the second plurality of horizontal-axis metal lines L5to L8at the first to fourth nodes BB, A, B and AB. For example, a first vertical-axis metal line V1may be connected to the first horizontal-axis metal line L1and a fifth horizontal-axis metal line L5that are connected to the second node A, and a second vertical-axis metal line V2may be connected to a fourth horizontal-axis metal line L4and a seventh horizontal-axis metal line L7that are connected to the first node BB. However, the present inventive concepts are not limited thereto.

Further, the plurality of metal lines L1to L8and V1to V4may be arranged in a matrix form to equally maintain the line lengths, widths, thicknesses or distances of the plurality of metal lines L1to L8and V1to V4. As a result, the signals that are output from the respective nodes BB, A, B and AB may have the same routing paths, and thus the mismatch between the transistors and the R/C time constant mismatch can be reduced.

FIG. 7is a circuit diagram illustrating an XOR gate according to an exemplary embodiment of the present inventive concepts, andFIG. 8is a timing diagram illustrating an operation of an XOR gate according to an exemplary embodiment of the present inventive concepts.

Referring toFIGS. 7 and 8, an XOR gate200may have a same propagation delay for all input nodes BB, A, B, AB to an output node OUT. The XOR gate200may include first to fourth input inverters210,220,230and240and first and second output inverters250and260.

The first input inverter210may include a first PMOS transistor P1and a first NMOS transistor N1. The second input inverter220may include the first PMOS transistor P1and a second NMOS transistor N2. The third input inverter230may include a second PMOS transistor P3and a third NMOS transistor N3. The fourth input inverter240that includes the second PMOS transistor P3and a fourth NMOS transistor N4. The first output inverter250may be connected to the drain of the first PMOS transistor P1and may include a third PMOS transistor P2and a fifth NMOS transistor N5. The second output inverter260may be connected to the drain of the second PMOS transistor P3and may include the third PMOS transistor P2and a sixth NMOS transistor N6. That is, the first input inverter210and the second input inverter220may share the first PMOS transistor P1, and the third input inverter230and the fourth input inverter240may share the second PMOS transistor P3. The first output inverter250and the second output inverter260may share the third PMOS transistor P2.

An output of the first inverter210and an output of the second input inverters220may be connected to an input of the first output inverter250at node Q1, and an output of the third input inverter230and an output of the fourth input inverters240may be connected to an input of the second output inverter260at node Q2.

In this case, a second signal of a second node A having a first period may be input to the first NMOS transistor N1, and a third signal of a third node B that is different from the second signal of the second node A having the first period may be input to the second NMOS transistor N2. Further, a first signal of a first node BB may be an inverted signal of the third signal of the third node B and may be input to the third NMOS transistor N3. a fourth signal of a fourth node AB may be an inverted signal of the second signal of the second node A and may be input to the fourth NMOS transistor N4. A phase difference of ¼ period may exist between the first signal of the first node BB and the second signal of the second node A. However, the present inventive concepts are not limited thereto.

An enable signal ENB that controls the first to third PMOS transistors P1to P3may be equally applied to the gate terminals of the first to third PMOS transistors P1to P3. If the enable signal ENB is low, the XOR gate200can operate. In contrast, if the enable signal ENB is high, the XOR gate does not operate.

Each source of the first to third PMOS transistors P1to P3may be connected to the VDD. A drain of the first PMOS transistor P1may be connected to a node Q1272. The node Q1272may be connected to a drain of the first NMOS transistor N1, a drain of the second NMOS transistor N2, and a gate of the fifth NMOS transistor N5.

In the same manner, a drain of the second PMOS transistor P3may be connected to a node Q2274. The node Q2274may be connected to a drain of the third NMOS transistor N3, a drain of the fourth NMOS transistor N4, and a gate of the sixth NMOS transistor N6.

The first output inverter250and the second output inverter260may share the output node OUT. The output node OUT may output an oscillating signal having the second period that corresponds to a half of the first period of the signal that is input from the voltage controlled oscillator100. That is, The XOR gate200may output a signal having a frequency that is double the input signal frequency of the voltage controlled oscillator100.

The circuit of the first input inverter210and the second input inverter220, which are connected to the first output inverter250, and the circuit of the third input inverter230and the fourth input inverter240, which are connected to the second output inverter260, may be arranged on a substrate (not illustrated) in the substantially same manner. That is, the XOR gate200according to an exemplary embodiment of the present inventive concepts may be symmetrically arranged about the output node OUT on the substrate (not illustrated).

The XOR gate200according to the present inventive concepts, there are only two transistors at maximum connected between VDD and VSS, and thus the operating speed can be increased. Further, by reducing the number of elements that are used, the XOR gate200may be less affected by a change of the semiconductor manufacturing process. Further, since the signals that are output through the respective inputs have the same routing paths, the mismatch between the transistors and the R/C time constant mismatch can be reduced. That is, the uniformity of the propagation delay from the input to the output can be secured.

FIG. 8is a timing diagram of the XOR gate200. The XOR gate200may receive the first to fourth signals of the first to fourth nodes BB, A, B and AB having multi-phases of the voltage controlled oscillator100. The first to fourth signals may have a phase difference of 90° with each other. The node Q1272ofFIG. 7may have a low-level value when one of signals of the second node A and the first node BB becomes high. The node Q2274may have a low-level value when one of the signals of the third node B and the fourth node AB becomes high. The first to third PMOS transistors P1to P3may always operate in a turn-on state, and if the XOR gate200does not operate, the first to third PMOS transistor P1to P3may be turn off using the enable signal ENB. The outputs of the node Q1272and the node Q2274may be expressed as in Equation 1 below.
Q1=(A+BB)=Ā·B,Q2=(AB+B)=A·B[Equation 1]

The output node OUT may be in a high state when both the node Q1272and the node Q2274become low. For example, in the case of a time period S2, both the node Q1272and the node Q2274become low, and thus the output node OUT has a high-level value. In the case of time periods S4, S6, and S8, the output node OUT has a high-level value in the same manner.

The output of the output node OUT may be expressed as in Equation 2 below.
OUT=Q1+Q2=Q1+Q2=Ā·B+A·B[Equation 2]

As can be known through Equation 1 and Equation 2 as described above, the output signal of the output node OUT may be defined as an XOR function of the node A and the node B.

The signals of the first to fourth nodes BB, A, B and AB that are provided from the voltage controlled oscillator100may have a first period T1, whereas the signal that is output from the XOR gate200may have a second period T2that corresponds to a half of the first period. As a result, the XOR gate200can provide the output signal having a frequency that is double the frequency of the input signal.

FIG. 9is a block diagram illustrating an XOR gate according to an exemplary embodiment of the present inventive concepts, andFIG. 10is a block diagram illustrating metal lines connected to an XOR gate according to an exemplary embodiment of the present inventive concepts. Hereinafter, for convenience in explanation, the duplicate explanation of the same terms as those according to the above-described embodiment will be omitted, and explanation will be made around different points between the exemplary embodiments.

Referring toFIG. 9, an XOR gate202according to an exemplary embodiment of the present inventive concepts includes a first unit block set292and a second unit block set294.

The first unit block set292may be connected to an output node OUT and may include N unit blocks, each of which is connected to the node OUT and is connected to one of N nodes, respectively. For example, the first unit block set292may include first to fourth unit blocks B3, B1, B2and B4, each of which is connected to each of the first to fourth nodes BB, A, B and BB, respectively. However, the present inventive concepts are not limited thereto.

The first unit block set292and the second unit block set294may include substantially the same configuration as the configuration of the XOR gate200as described above with reference toFIG. 7. The second unit block set294may be formed to be substantially the same as the first unit block set292. The second unit block set294may share the output node OUT with the first unit block set292. That is, the first unit block set292and the second unit block set294may be symmetrically arranged about the output node OUT on a substrate (not illustrated).

Specifically, the first unit block set292may include the first to fourth unit blocks B3, B1, B2and B4, and the second unit block set294may include fifth to eighth unit blocks B6, B8, B7and B5. Each of the first to fourth unit blocks B3, B1, B2and B4may be connected to each of first to fourth signals of the first to fourth node BB, A, B and BB having different phases, respectively. In the same manner, each of the fifth to eighth unit blocks B6, B8, B7and B5may be connected to the first to fourth signals of the first to fourth node BB, A, B and BB having different phases, respectively.

Further, each of the unit blocks B1to B8may include an input inverter to which any one of the first to fourth signals is input, and an output inverter that receives an output of the input inverter as its input. For example, the second unit block B1may include a first input inverter210and a first output inverter250, and the first unit block B3may include a second input inverter220and a first output inverter250. However, the present inventive concepts are not limited thereto.

The second signal of the second node A may be input to the second unit block B1, and the third signal of the third node B that is different from the first signal BB may be input to the second unit block B2. Further, the first signal of the first node BB that corresponds to an inverted signal of the third signal of the third node B may be input to the third unit block B3, and the fourth signal of the fourth node AB that corresponds to an inverted signal of the first signal of the second node A may be input to the fourth block B4.

Further, the second unit block B1and the first unit block B3may share the node Q1272that connects the input inverters210and220, and the output inverters250to each other, and the second unit block B2and the fourth unit block B4may share the node Q2274that connects the input inverters230and240, and the output inverters260to each other. The second unit block set294may include fifth to eighth unit block B6, B8, B7and B5that are connected to each other in the same manner as described above about the first unit block set292.

FIG. 10illustrates connections of signals of the nodes BB, A, B, and AB having different phases, which are input from the voltage controlled oscillator100.

The XOR gate202includes a plurality of vertical-axis metal lines V1to V4and a plurality of connection metal lines H1to H8. The plurality of vertical-axis metal lines V1to V4may be arranged at predetermined intervals in the center of the XOR gate202.

A first plurality of connection metal lines H1to H4may connect inputs of the first to fourth unit blocks B3, B1, B2and B4to the plurality of vertical-axis metal lines V1to V4. In the same manner, a second plurality of connection metal lines H5to H8may connect inputs of the fifth to eighth unit blocks B6, B8, B7and B5to the plurality of vertical-axis metal lines V1to V4. The first plurality of connection metal lines H1to H4and the second plurality of connection metal lines H5to H8may be symmetrically arranged about the plurality of vertical-axis metal lines V1to V4. The first plurality of connection metal lines H1to H4and the second plurality of connection metal lines H5to H8may be formed to have the same length, the same width, and the same thickness. However, the present inventive concepts are not limited thereto.

The XOR gate202is configured to have the same routing paths of the metal lines for the respective unit blocks, and thus a characteristic mismatch of transistors and a R/C time constant mismatch can be reduced.

According to the XOR gate200according to an exemplary embodiment of the present inventive concepts as described above with reference toFIG. 7, when a random mismatch occurs between the transistors, deviation occurs between propagation delays to heighten a deterministic jitter (DJ). In contrast, according to the XOR gate202according to an exemplary embodiment of the present inventive concepts as described above with reference toFIG. 10, the elements can be arranged in a common centroid manner. That is, in the XOR gate202, inverters, each of which is composed of two transistors, are arranged in a common centroid manner on a plane, and thus the occurrence of the random mismatch of the process can be reduced. Further, by providing two or more paths for an input signal of each of the first to fourth nodes BB, A, B, and AB having four phases and arranging all outputs to be centered on the output node OUT, the occurrence of mismatch between the moving paths can be reduced.

FIG. 11is a block diagram illustrating metal lines of a frequency doubler according to an exemplary embodiment of the present inventive concept. Hereinafter, for convenience in explanation, the duplicate explanation of the same terms as those according to the above-described embodiment will be omitted, and explanation will be made around different points between the exemplary embodiments.

FIG. 11illustrates a frequency doubler1in which the voltage controlled oscillator100as described above with reference toFIG. 6and the XOR gate202as described above with reference toFIG. 10are connected to each other.

The frequency doubler1includes the voltage controlled oscillator100that includes inverters, and the XOR gate202. The voltage controlled oscillator100and the XOR gate202may be arranged in a common centroid manner on a substrate (not illustrated). For this, the frequency doubler1may be configured so that all elements connected to a plurality of vertical-axis metal lines V1to V4have the same routing paths. Further, since the frequency doubler1can secure uniformity of the time delay between the delay units and uniformity of the propagation delay from the inputs of the nodes BB, A, B and AB to the output of the node OUTPUT of the XOR gate202, and can reduce the difference in R/C time constant between the metal lines from the delay unit to the XOR gate202, the deterministic jitter (DJ) due to the phase mismatch can be reduced.

FIG. 12is a graph explaining simulation results of five process corners of a frequency doubler according to exemplary embodiments of the present inventive concepts, andFIG. 13is a graph explaining the simulation result of a Monte-Carlo simulation of a frequency doubler according to exemplary embodiments of the present inventive concepts. The X-axis inFIG. 12is a period of an output of the frequency doubler1, and the Y-axis is a number of occurrence of the period of the output of the frequency doubler1.

Referring toFIG. 12, (a) to (e) ofFIG. 12are graphs illustrating deterministic jitters (DJ) of the frequency doubler1for specific process corners (e.g., NN/FF/SS/SF/FS). As the result of performing simulations which do not consider the mismatch of the transistors, the deterministic jitter (DJ) appears to have a value between 0.03 ps to 0.3 ps. Through this, it can be known that the R/C delay mismatch between the metal lines is very small in the frequency doubler1according to exemplary embodiments of the present inventive concepts.

FIG. 13a graph illustrating the result of performing the Monte-Carlo simulation for testing the operation through a random change of the process in the frequency doubler1. The X-axis inFIG. 13is period difference from a center of the period of the output of the frequency doubler1, and the Y-axis is a number of occurrence of the period difference.

As the results of performing the Monte-Carlo simulations 1000 times, the frequency doubler1according to exemplary embodiments of the present inventive concepts showed the deterministic jitter (DJ) value of 2.1 ps at maximum. However, in a semiconductor device that includes the actually manufactured frequency doubler1, much smaller deterministic jitter (DJ) value of 0.3 ps was showed. This is because in the case of the Monte-Carlo simulation, very large mismatch may be generated even between two neighboring elements, whereas in the case of the semiconductor device including the actually implemented frequency doubler1, the performance deviation between the two adjacent elements is very small enough to be disregarded. Typically, deviation of about 1-sigma is considered in the Monte-Carlo simulation, and thus it can be predicted that the actually manufactured semiconductor device has the deterministic jitter (DJ) value of less than 0.7 ps at maximum even in consideration of all mismatch situations.

FIG. 14is a block diagram of a wireless device that includes a frequency doubler according to embodiments of the present inventive concepts.

Referring toFIG. 14, a wireless device800may be a cellular phone, a terminal, a PDA (Personal Digital Assistant), a handset, or any other device. A wireless communication system may include a code division multiple access (CDMA) system, a time division multiple access (TDMA) system, a frequency division multiple access (FDMA) system, a mobile communication globalization (GSM) system, an orthogonal frequency division multiple access (OFDMA) system, and a wireless LAN (WLAN).

The wireless device800includes a digital processor810that supports bidirectional communications and a transceiver830. The digital processor810may be implemented by one or more application specific integrated circuits (ASIC). The transceiver830may be implemented by one or more wireless frequency integrated circuits (RFIC).

For data transmission, an encoder812processes (e.g., formats, encodes, and interleaves) data to be transmitted, and a modulator814processes (e.g., modulates and scrambles) coded data to generate a data chip. In the transceiver830, a transmission (TX) baseband device832performs baseband process, such as digital-to-analog conversion, filtering, and amplification. A mixer834up-converts a baseband signal into a radio frequency (RF). A TX RF device836performs signal conditioning, such as filtering and power amplification, and generates an RF modulated signal that is transmitted through an antenna840.

For data reception, a reception (RX) RF device842receives an input RF signal from the antenna840, and performs signal conditioning, such as low-noise amplification and filtering. A mixer844down-converts the conditioned RF signal into a baseband signal. A RX baseband device846performs baseband process, such as filtering, amplification, and analog-to-digital conversion. A demodulator816processes (descrambles and demodulates) input samples from the RX baseband device846to provide symbol estimate. A decoder818processes (de-interleaves and decodes) the symbol estimate and provides decoded data. In general, the processes performed by the data processor810and the transceiver830may differ according to designs of the wireless system.

A processor820may support various applications, such as video, audio, graphics, and others. A controller/processor860instructs operations of various processing devices in the wireless device800. A memory862stores program codes and data for the wireless device800.

A VCO/PLL822generates a clock signal with respect to processing devices in the digital processor810. A VCO/PLL850generates a transmission LO signal that is used by a mixer834for frequency up-conversion, and generates a reception LO signal that is used by a mixer844for frequency down-conversion. The VCO/PLL822and the VCO/PLL850use a linear phase frequency detector and a charge pump to improve the performance. A reference oscillator864generates and provides a reference signal to the VCO/PLL822and/or the VCO/PLL850. The reference oscillator864may be a crystal oscillator XO, a voltage controlled XO (VCXO), a temperature compensated XO (TCXO), or any other kind of oscillator.

The phase frequency detector, the charge pump, and the PLL described herein may be implemented in an analog IC, a RFIC, an ASIC, a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a processor, a controller, a microcontroller, a microprocessor, and other electronic devices. The phase frequency detector, the charge pump, and the PLL may be manufactured by various IC process techniques, such as N-MOS, P-MOS, CMOS, BJT, GaAs, and others. Further, the phase frequency detector, the charge pump, and the PLL may be implemented by individual components.

Next, referring toFIG. 15, an electronic system that includes a frequency doubler1according to embodiments of the present inventive concepts will be described.

FIG. 15is a block diagram of an electronic system that includes a frequency doubler according to embodiments of the present inventive concepts.

Referring toFIG. 15, an electronic system900according to an exemplary embodiment of the present inventive concepts may include a controller910, an input/output (I/O) device920, a memory930, an interface940, and a bus950. The controller910, the I/O device920, the memory930, and/or the interface940may be coupled to one another through the bus950. The bus950corresponds to paths through which data is transferred.

The controller910may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements that can perform similar functions. The I/O device920may include a keypad, a keyboard, and a display device. The memory930may store data and/or commands. The interface940may function to transfer the data to a communication network or receive the data from the communication network. The interface940may be of a wired or wireless type. For example, the interface940may include an antenna or a wire/wireless transceiver.

Although not illustrated, the electronic system900may further include a high-speed DRAM and/or SRAM as an operating memory for improving the operation of the controller910. In this case, as the operating memory, a semiconductor device99baccording to an exemplary embodiment of the present inventive concepts may be adopted. Further, a semiconductor device98baccording to an exemplary embodiment of the present inventive concepts may be provided in the memory930, or may be provided as a part of the controller910or the I/O device920.

The electronic system900may be applied to a PDA (Personal Digital Assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or all electronic devices that can transmit and/or receive information in wireless environments.

FIGS. 16 to 18are views of exemplary semiconductor systems to which a frequency doubler according to exemplary embodiments of the present inventive concepts can be applied.

FIG. 16illustrates a tablet PC1000,FIG. 17illustrates a notebook computer1100, andFIG. 18illustrates a smart phone1200. The frequency doubler1according to an exemplary embodiment of the present inventive concepts may be used in the tablet PC1000, the notebook computer1100, or the smart phone1200.

Further, it is apparent to those of skilled in the art that the frequency doubler1according to exemplary embodiments of the present inventive concepts can also be applied to other integrated circuit devices that have not been exemplified. That is, although the tablet PC1000, the notebook computer1100, and the smart phone1200have been indicated as examples of the semiconductor system that includes the frequency doubler1according to this embodiment, the examples of the semiconductor system that includes the frequency doubler1according to this embodiment are not limited thereto. In exemplary embodiments of the present inventive concepts, the semiconductor system may be implemented as a computer, UMPC (Ultra Mobile PC), workstation, net-book, PDA (Personal Digital Assistant), portable computer, wireless phone, mobile phone, e-book, PMP (Portable Multimedia Player), portable game machine, navigation device, black box, digital camera, 3D television set, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, or digital video player.