Semiconductor devices and methods of manufacturing the same

A semiconductor package includes a first semiconductor component, a second semiconductor component, and a connecting element. The first semiconductor component includes a first substrate, and a first bonding pad disposed adjacent to a first surface of the first substrate, and at least one conductive via structure extending from a second surface of the first substrate to the first bonding pad. The second semiconductor component includes a second substrate, a redistribution layer disposed adjacent to a first surface of the second substrate, and a second bonding pad disposed on the redistribution layer. The connecting element is disposed between the first bonding pad and the second bonding pad.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor package and method of manufacturing the same, and, more particularly, to a semiconductor package including at least two semiconductor components and method of manufacturing the same.

2. Description of the Related Art

There is a continuing desire to incorporate more than one semiconductor component into a single semiconductor package to reduce dimensions of the package. A semiconductor package incorporating multiple semiconductor components may be referred to as a system in package (SiP). Because semiconductor components may have different sizes and different coefficients of thermal expansion (CTE), warpage or cracking may occur in a semiconductor package incorporating multiple semiconductor components.

SUMMARY

In an embodiment, a semiconductor package includes a first semiconductor component, a second semiconductor component, and a connecting element. The first semiconductor component includes a first substrate, and a first bonding pad disposed adjacent to a first surface of the first substrate, and at least one conductive via structure extending from a second surface of the first substrate to the first bonding pad. The second semiconductor component includes a second substrate, a redistribution layer disposed adjacent to a first surface of the second substrate, and a second bonding pad disposed on the redistribution layer. The connecting element is disposed between the first bonding pad and the second bonding pad.

In an embodiment, a semiconductor package includes a wafer and multiple semiconductor components disposed adjacent to a first surface of the wafer. Each semiconductor component includes a substrate having a first surface and a second surface opposite to the first surface. Each semiconductor component further includes at least one bonding pad disposed adjacent to the first surface of the substrate and at least one conductive via structure extending from the second surface of the substrate to the bonding pad. Each semiconductor component is electrically connected to the first surface of the wafer through the bonding pad.

In an embodiment, a method of manufacturing includes (a) providing a first semiconductor component comprising a first substrate having a first surface and a second surface opposite to the first surface, the first semiconductor component further comprising at least one first bonding pad disposed adjacent to the first surface of the substrate; (b) providing a second semiconductor component comprising a second substrate and at least one second bonding pad disposed adjacent to a surface of the second substrate; (c) electrically connecting the first semiconductor component to the second semiconductor component through the first bonding pad and the second bonding pad; (d) disposing a protection layer on at least a portion of the second surface of the first substrate; and (e) forming at least one conductive via structure extending from a surface of the protection layer to the first bonding pad.

DETAILED DESCRIPTION

Spatial descriptions, such as “above,” “below,” “top,” “bottom,” “side,” “over,” “under,” “upper,” “lower” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated by such arrangement.

FIG. 1illustrates a cross-sectional view of a semiconductor package100according to embodiments of the present disclosure. The semiconductor package100includes a first semiconductor component102, a protection layer104, a second semiconductor component106, an underfill108and external connecting structures110.

The first semiconductor component102may be any semiconductor component including, for example, a chip, a package, an interposer, or a combination thereof. In the embodiment illustrated inFIG. 1, the first semiconductor component102includes a first substrate112, at least one first bonding pad114, a first insulation layer116, at least one first conductive connector118, and at least one conductive via structure120.

The first substrate112has a first surface112a, a second surface112b, and a side surface112c. The first surface112ais opposite to the second surface112b. The side surface112cextends between the first surface112aand the second surface112b.

The first bonding pad114is disposed adjacent to the first surface112aof the first substrate112. The first bonding pad114may be, for example, a contact pad of a trace. In the embodiment ofFIG. 1, the first surface112ais an active surface, the first bonding pad114is a contact pad, and the first bonding pad114is disposed directly (e.g., in physical contact) on the first surface112aof the first substrate112. The first bonding pad112may include, for example, copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc, other metals, metal alloys, or a combination of two or more thereof.

The first insulation layer116covers a portion of each of the first bonding pads114and the first surface112aof the first substrate112not covered by the first bonding pads114. The first insulation layer116has a first surface116a, a second surface116b, a side surface116c, and the first insulation layer116defines at least one opening116d. The first surface116ais opposite to the second surface116b. The side surface116cextends between the first surface116aand the second surface116b. Each opening116dexposes at least a portion of a respective first bonding pad114. The first insulation layer116may be, for example, a solder mask (the material of which is, for example, polyimide (PI)) or a passivation layer (the material of which is, for example, a metal oxide).

The first conductive connector118is disposed in the opening116dand contacts the first bonding pad114. The first conductive connector118may be, for example, a pillar structure, which may include an under bump metallization (UBM) layer, a pillar, a barrier layer, a solder layer, or a combination of two or more thereof. As illustrated inFIG. 1, the first conductive connector118is a pillar structure which includes a first UBM layer118aand a first pillar118b. The first UBM layer118ais disposed in the opening116dand contacts the first bonding pad114. The first pillar118bis disposed on the first UBM layer118aand is electrically connected to the first bonding pad114. In some embodiments, one or both of a barrier layer and a solder layer are included in the first pillar118b. In an embodiment, the first pillar118bmay include copper, another metal, a metal alloy, or a combination thereof. In an embodiment, the first UBM layer118amay include a metal, metal alloy, a multi-metal stack, a multi-alloy stack, or a combination thereof. For example, a multi-metal stack can include layers of copper, nickel, vanadium, chromium, and/or gold, and a multi-alloy stack can include layers of alloys of copper, nickel, vanadium, chromium, and/or gold.

The conductive via structure120electrically connects the first bonding pad114of the first semiconductor component102to the external connecting structure110. The conductive via structure120includes a via120a, a first dielectric layer120b, a conductive layer120c, and a second dielectric layer120d. The via102ais an opening that extends through the protection layer104and the first substrate112to the first bonding pad114. The first dielectric layer120bcovers at least a portion of an inner side wall of the via120a. In the embodiment ofFIG. 1, the first dielectric layer120bextends from an upper surface of the protection layer104to the first bonding pad114, and further extends along the upper surface of the protection layer104. The conductive layer120cis disposed on the first dielectric layer120bin the via120a, on the first bonding pad114, and on a portion of the first dielectric layer120bextending along the upper surface of the protection layer104. The conductive layer120celectrically connects the first bonding pad114to the external connecting structure110.

The second dielectric layer120dcovers exposed portions of the conductive layer120cand the first dielectric layer120b, and further covers the second surface112bof the first substrate112not covered by the conductive layer120cand the first dielectric layer120b. In the embodiment ofFIG. 1, the second dielectric layer120dfurther fills a portion of the via120anot filled by the first dielectric layer120band the conductive layer120c. In other embodiments, the conductive layer120c, rather than the second dielectric layer120d, fills the via120a. The second dielectric layer120ddefines at least one opening121. Each opening121exposes a portion of the conductive layer120c.

The first dielectric layer120bmay be, for example, formed of a photosensitive material (such as PI). The second dielectric layer120dmay be, for example, formed of a photosensitive material (such as PI) or a passivation layer (the material of which is a metal oxide or a polymer).

The external connecting structure110is disposed on the second dielectric layer120dand in the opening121for electrical connection to the conductive layer120c. The external connecting structure110can thus be electrically connected to the first bonding pad114by way of the conductive layer120cthrough the conductive via structure120. The external connecting structures110may be, for example, copper pillars or solder/stud bumps. In the embodiment illustrated inFIG. 1, the external connecting structure110includes a UBM layer110band a pillar110a.

The second semiconductor component106may be any semiconductor component including, for example, a chip, a package, an interposer, or a combination thereof. In the embodiment illustrated inFIG. 1, the second semiconductor component106includes a second substrate126, at least one redistribution layer (RDL)128, at least one second bonding pad130, a second insulation layer132, and at least one second conductive connector134.

The second substrate126has a first surface126a, a second surface126b, and a side surface126c. The first surface126ais opposite to the second surface126b. The side surface126cextends between the first surface126aand the second surface126b. The second substrate126includes a protrusion portion127extending from the side surface126c. The protrusion portion127may extend from the side surface126caround a periphery of the semiconductor package100, or the protrusion portion127may be omitted.

The RDL128is disposed adjacent to the first surface126aof the second substrate126. The RDL128has a first surface128a, a second surface128b, and a side surface128c. The first surface128ais opposite to the second surface128b. The side surface128cextends between the first surface128aand the second surface128b. The second surface128bof the RDL128faces the first surface126aof the second substrate126. The RDL128includes a dielectric layer128dand a patterned conductive layer128e.

The second bonding pad130is disposed adjacent to the first surface128aof the RDL128. The second bonding pad130may be, for example, a contact pad of a trace. In the embodiment ofFIG. 1, the second semiconductor component106is a chip, the first surface126ais an active surface, the second bonding pad130is a contact pad, and the second bonding pad130is disposed directly (e.g., in physical contact) on the first surface128aof the RDL128. The second bonding pad130may include, for example, copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc, other metals, metal alloys, or a combination of two or more thereof.

The second insulation layer132covers a portion of each of the second bonding pads130and further covers the first surface128aof the RDL128. The second insulation layer132defines at least one opening132a. The opening132aexposes at least a portion of the second bonding pad130. The second insulation layer132may be, for example, a solder mask (the material of which is, for example, PI) or a passivation layer (the material of which is, for example, a metal oxide).

The second conductive connector134is disposed in the opening132aand contacts the second bonding pad130. The structures and components of the second conductive connector134may be similar to those described above with respect to the first conductive connector118. In the embodiment ofFIG. 1, the second conductive connector134is a pillar structure including a second UBM layer134aand a second pillar134b.

The second semiconductor component106may be electrically connected to the first semiconductor component102, such as through wire bonds, pillars, solder bumps, solder pillars, or other connections. The second semiconductor component106may be electrically connected to the first semiconductor component102through the first conductive connector118and the second conductive connector134. In the embodiment ofFIG. 1, each first conductive connector118is electrically connected to and aligned with a respective second conductive connector134. In this embodiment, the first conductive connector118is bonded to the second conductive connector134directly and together they form a connection element124. The first conductive connector118may be bonded to the second conductive connector134by a metal fusion bonding technique or a metal eutectic bonding technique so there may not be a discernable interface between the first conductive connector118and the second conductive connector134after bonding. Accordingly, the dotted line between the first conductive connector118and the second conductive connector134inFIG. 1is provided by way of illustration, and does not necessarily represent an actual interface. The bonding technique of the first conductive connector118and the second conductive connector134may reduce or eliminate use of a solder.

The underfill108is disposed between the first semiconductor component102and the second semiconductor component106to protect the connection elements124from oxidation, moisture, and other environmental conditions. In some embodiments, the underfill108is omitted.

The protection layer104encapsulates portions of the first semiconductor component102and the second semiconductor component106. The protection layer104covers at least a portion of the second surface112bof the first substrate112. The protection layer104above the second surface112bof the first substrate112is substantially flat so that drilling or etching for forming the via120aof the conductive via structure120can be facilitated. The protection layer104further covers a portion of the side surface112cof the first substrate112and at least a portion of the underfill108, and may extend to cover portions of the second semiconductor component106, including covering portions of the second surface126bof the second substrate126. In this manner, the first semiconductor component102, and the electrical connection between the first semiconductor component102and the second semiconductor component106, may be protected from oxidation, moisture, and other environmental conditions. In addition, the extension of the protection layer104from the second surface112bof the first substrate112to the second semiconductor component106can assist in compensating for differences in CTE between the first semiconductor component102and the second semiconductor component106, thus reducing warpage and cracking.

In the embodiment ofFIG. 1, the protection layer104covers portions of the second surface112bof the first substrate112, portions of the side surface112cof the first substrate112, portions of the underfill108, portions of the second insulation layer132(e.g., a side surface and a portion of a top surface), and the side surface128cof the RDL128. The protection layer104may surround the first semiconductor component102and the underfill108, and may further surround the second semiconductor component106(not shown) or portions thereof. In the embodiment ofFIG. 1, the protection layer104extends from the second surface112bof the first substrate112to the first surface126aof the second substrate126.

FIG. 2illustrates a cross-sectional view of a semiconductor package200according to an embodiment of the present disclosure. The semiconductor package200ofFIG. 2includes first semiconductor components102, a protection layer204, a semiconductor component206, an underfill208, and external connecting structures110.

The first semiconductor component102illustrated inFIG. 2is similar to the first semiconductor component102illustrated inFIG. 1and described above. Therefore, for the sake of conciseness, the first semiconductor component102illustrated inFIG. 2is not described again with respect toFIG. 2.

The protection layer204illustrated inFIG. 2is similar to the protection layer104illustrated inFIG. 1and described above except that the protection layer204covers at least a portion of more than one first semiconductor component102. As described above with respect to the protection layer104, the protection layer204protects against oxidation, moisture, and other environmental conditions, and further assists in compensating for CTE differences between the first semiconductor components102and between the first semiconductor components102and the semiconductor component206.

The protection layer204above the second surfaces112bof the first substrates112is substantially flat so that drilling or etching for forming the vias120aof the conductive via structures120will not be affected by differences in dimensions of the first semiconductor components102(e.g., differences in height or thickness of the first semiconductor components102or the first substrates112of the first semiconductor components102).

The semiconductor component206may be, for example, a wafer. In the embodiment ofFIG. 2, the semiconductor component206is a wafer including multiple dies. Each die may be similar to the second semiconductor component106illustrated inFIG. 1. The semiconductor component206includes a second substrate226, at least one RDL228, at least one bonding pad230, an insulation layer232, and at least one second conductive connector234.

The RDL228is disposed adjacent to an upper surface (in the orientation shown) of the second substrate226.

The bonding pad230is disposed adjacent to an upper surface (in the orientation shown) of the RDL228and is electrically connected to the RDL228.

The insulation layer232covers a portion of each of the bonding pads230and further covers the upper surface of the RDL228. The insulation layer232defines at least one opening exposing at least a portion of a bonding pad230.

The second conductive connector234is disposed in the opening defined by the insulation layer232and contacts the bonding pad230.

The underfill208may optionally be disposed between the first semiconductor components102and the semiconductor component206. External connecting structures110may be disposed on the first semiconductor components102as described with respect toFIG. 1.

FIG. 3illustrates a cross-sectional view of a semiconductor package300according to an embodiment of the present disclosure. The semiconductor package300inFIG. 3is similar to the semiconductor package100inFIG. 1, with differences including that the second semiconductor component106further includes a protection layer305disposed adjacent to the second surface126bof the second substrate126and at least one external bonding pad330, and may include a UBM layer335.

The external bonding pad330is disposed adjacent to the second surface126bof the second substrate126.

The protection layer305covers a portion of the external bonding pad330and further covers the second surface126bof the second substrate126. The protection layer305defines at least one opening305aexposing at least a portion of the external bonding pad330for external electrical connection, such as connection to a copper pillar, solder or stud bump. The UBM layer335is optionally disposed in the opening305a, and optionally extends onto a lower surface of the protection layer305. The protection layer305may be, for example, a solder mask (the material of which is, for example, PI) or a passivation layer (the material of which, for example, is a metal oxide). By providing both the external connecting structures110and the external bonding pads330, the semiconductor package300may have enhanced design flexibility due to the possibility for providing external electrical connection from both a top side and a bottom side of the semiconductor package300.

FIGS. 4A-4Dillustrate a method for partially manufacturing the first semiconductor component102according to an embodiment of the present disclosure.

Referring toFIG. 4A, a substrate412is provided. In one or more embodiments, the substrate is a wafer. The substrate412has a first surface412aand a second surface412b. The first surface412ais opposite to the second surface412b. In the embodiment ofFIG. 4A, the first surface412ais an active surface.

Referring toFIG. 4B, at least one first bonding pad114is disposed on the first surface412aof the substrate412. The first bonding pad114may be formed, for example, by photolithography in combination with etching and electroplating or physical vapor deposition.

Referring toFIG. 4C, a first insulation layer416is disposed on the first surface412aof the substrate412, such as by lamination or adhesion. The first insulation layer416covers a portion of the first bonding pad114and further covers the first surface412aof the substrate412. The first insulation layer416defines at least one opening416dexposing at least a portion of the first bonding pad114. The first insulation layer416may include a photosensitive material, such as a PI, so that the opening416dcan be formed by a photolithography and etching processes.

Referring toFIG. 4D, a first conductive connector118is disposed in the opening416dand contacts the first bonding pad114. In the embodiment ofFIG. 4D, the first conductive connector118is a pillar structure including a UBM layer118aand a pillar118b. The first conductive connector118may be formed, for example, by photolithography in combination with etching and electroplating or physical vapor deposition.

Subsequently, the substrate412may be thinned from the second surface412bto obtain a desired thickness, and a singulation process (e.g., sawing) is performed to obtain individual semiconductor component units (e.g., a semiconductor device602as is illustrated inFIG. 6A).

FIGS. 5A-5Dillustrate a method for manufacturing the semiconductor component206ofFIG. 2according to an embodiment of the present disclosure.

Referring toFIG. 5A, a second substrate226is provided. In one or more embodiments, the second substrate226is a wafer. The second substrate226has a first surface226aand a second surface226b. The first surface226ais opposite to the second surface226b. In the embodiment ofFIG. 5A, the first surface226ais an active surface.

Referring toFIG. 5B, an RDL228is disposed adjacent to the first surface226aof the second substrate226. The RDL228has a first surface228aand a second surface228bopposite to the first surface228a. The second surface228bfaces the first surface226aof the second substrate226. The RDL228includes a dielectric layer228dand a patterned conductive layer228e. At least one bonding pad230is disposed adjacent to the first surface228aof the RDL228and is electrically connected to the patterned conductive layer228eof the RDL228through a conductive via228f. The bonding pad230may be, for example, a contact pad of a trace. In the embodiment ofFIG. 5B, the bonding pad230is a contact pad, and the bonding pad230is disposed directly on (e.g., physically contacting) the first surface228aof the RDL228.

Referring toFIG. 5C, an insulation layer232is disposed on the first surface228aof the RDL228, such as by lamination or adhesion. The insulation layer232covers a portion of the bonding pad230and further covers the first surface228aof the RDL228. The insulation layer232defines at least one opening232aexposing at least a portion of the bonding pad230. The insulation layer232may be formed of a photosensitive material, such as a PI, so that the opening232acan be formed by photolithography and etching, for example.

Referring toFIG. 5D, a second conductive connector234is disposed in the opening232aand contacts the bonding pad230. In the embodiment ofFIG. 5D, the second conductive connector234is a pillar structure including a UBM layer234aand a pillar234b. The second conductive connector234may be formed by photolithography in combination with etching process and electroplating or physical vapor deposition. By the method ofFIGS. 5A-5D, the semiconductor component206inFIG. 2can be obtained.

The second substrate226may be thinned from the second surface226bto obtain a desired thickness. After that, a singulation process, such as sawing, may be performed to obtain individual semiconductor component units.

FIGS. 6A-6Hillustrate a method for manufacturing a semiconductor package such as the semiconductor package100ofFIG. 1according to an embodiment of the present disclosure.

Referring toFIG. 6A, at least one semiconductor device602(e.g., obtained in accordance with the embodiment illustrated inFIGS. 4A-4D) and a semiconductor component206(e.g., obtained in accordance with the embodiment illustrated inFIGS. 5A-5D) are provided. A first conductive connector118of the semiconductor device602is aligned with and bonded to a second conductive connector234of the semiconductor component206.

The semiconductor devices602ofFIG. 6Aare each substantially similar to the individual semiconductor component unit illustrated inFIG. 4D. The semiconductor device602includes a substrate412(including a first surface412aand a second surface412b), at least one first bonding pad114, a first insulation layer416, and a first conductive connector118. The first bonding pad114is disposed on the first surface412aof the substrate412. The first insulation layer416is disposed on the first surface412aof the substrate412and covers a portion of the first bonding pad114and further covers a portion of the first surface412a. The first insulation layer416defines at least one opening416dexposing at least a portion of the first bonding pad114. The first conductive connector118is disposed in the opening416dand contacts the first bonding pad114.

The semiconductor component206ofFIG. 6Ais substantially similar to the semiconductor component206ofFIG. 5D. The semiconductor component206ofFIG. 6Aincludes a second substrate226(including a first surface226aand a second surface226b), at least one RDL228, at least one bonding pad230, an insulation layer232, and a second conductive connector234. The RDL228is disposed adjacent to the first surface226aof the second substrate226. The second bonding pad230is disposed adjacent to the first surface228aof the RDL228. The insulation layer232is disposed on the first surface228aof the RDL228. The second conductive connector234is disposed in an opening defined by the second insulation layer232and contacts the bonding pad230.

A bond between the first conductive connector118and the second conductive connector234may be formed by thermo-compression bonding to form connection elements124as illustrated inFIG. 1. During thermo-compression bonding, an operation pressure may be from about 2 Newtons (Nt) to about 70 Nt, such as from about 3 Nt to about 60 Nt, or from about 5 Nt to about 50 Nt; an operation temperature may be from about 180° C. to about 280° C., such as from about 190° C. to about 270° C., or from about 200° C. to about 260° C.; and an operation period can be from about 2 seconds to about 40 seconds, such as from about 3 seconds to about 35 seconds, or from about 4 seconds to about 30 seconds.

Referring toFIG. 6B, an underfill208is applied so as to be disposed between the semiconductor device602and the semiconductor component206to protect the connection elements124from oxidation, moisture, and other environmental conditions. The underfill208is the same as the underfill208illustrated inFIG. 2, and may cover at least a portion of a side surface of the semiconductor device602and the surface of the insulation layer232of the semiconductor component206.

Referring toFIG. 6C, a protection material (e.g., a photosensitive material, such as a PI) is disposed over the semiconductor device602to form a protection layer604. The protection layer604covers at least a portion of the second surface412bof the substrate412of the semiconductor device602and may further cover at least a portion of a side surface412cof the semiconductor device602, at least a portion of the underfill208, and at least a portion of the semiconductor component206. In the embodiment ofFIG. 6C, the protection layer604covers at least a portion of the second surface412bof the substrate412, at least a portion of the side surface412cof the substrate412, at least a portion of the underfill208, at least a portion of a side surface232cof the insulation layer232, and at least a portion of a side surface228cof the RDL228of the semiconductor component206. In the embodiment ofFIG. 6C, the protection layer604extends from the second surface412bof the substrate412of the semiconductor device602to the side surface228cof the RDL228.

The protection layer604defines at least one opening604aexposing a portion of the second surface412bof the substrate412of the semiconductor device602. The opening604adefines a location for drilling or etching for forming a via.

Referring toFIG. 6D, a via120aextending from the second surface412bof the substrate412of the semiconductor device602to the first bonding pad114is formed, such as by drilling or etching.

Referring toFIG. 6E, a first dielectric layer120bis disposed in the via120a. The first dielectric layer120bcovers an inner side wall of the via120a. In the embodiment ofFIG. 6E, the first dielectric layer120bcontacts the first bonding pad114and extends from the bottom of the via120ato an upper surface of the protection layer604and onto the upper surface of the protection layer604. The first dielectric layer120bmay be formed, for example, by photolithography in combination with etching.

Referring toFIG. 6F, a conductive layer120cis disposed on the first dielectric layer120bwhere it extends over the upper surface of the protection layer604and is disposed on the first dielectric layer120bwithin the via120a. The conductive layer120cis further disposed on the first bonding pad114. The conductive layer120cmay include a contact pad (e.g., a bonding pad for a solder ball or a pillar) for electrical connection, such as to an external connection (e.g., the external connecting structure110inFIG. 1).

Referring toFIG. 6G, a second dielectric layer120dis disposed on the conductive layer120c. The second dielectric layer120dcovers a portion of the conductive layer120cand may further cover a portion of the first dielectric layer120b. The second dielectric layer120ddefines at least one opening121exposing a portion of the conductive layer120c. In the embodiment ofFIG. 6G, the second dielectric layer120dfills the via120a. As seen inFIG. 6G, the second dielectric layer120dextends over a portion of the surface of the conductive layer120c. The second dielectric layer120dmay be formed, for example, by photolithography in combination with etching.

Referring toFIG. 6H, an external connecting structure110is disposed in the opening121and contacts the conductive layer120c(e.g., through a bonding pad). The external connecting structure110may be formed, for example, by photolithography in combination with etching. In the embodiment ofFIG. 6H, the external connecting structure110is a pillar structure including a UBM layer110aand a pillar110b. By the technique ofFIGS. 6A-6H, the semiconductor package200illustrated inFIG. 2can be obtained.

Subsequently, a separation technique (e.g., sawing) is performed to obtain individual semiconductor packages such as the semiconductor package100ofFIG. 1. The separation technique may include two cutting passes, where a cutting tool for the first pass should have a lesser degree of hardness than the cutting tool for the second pass, and the cutting tool for the first pass should have a wider blade than the cutting tool for the second pass, so that a crack may be avoided during separation (singulation). In embodiments where such a two-pass separation technique is used, a protrusion portion (e.g., the protrusion portion127ofFIG. 1) may be produced by the technique.

As used herein and not otherwise defined, the terms “substantially” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a line or a plane can be substantially flat if a peak or depression of the line or plane is no greater than 5 μm, no greater than 1 μm, or no greater than 0.5 μm.