Fast transient response voltage regulator with pre-boosting

A circuit and a method for supplying a regulated voltage to a target circuit characterized by fast changes in current loading are described. A voltage regulator supplies the regulated voltage to an output node. The voltage regulator has a transistor having a gate, a first terminal connected to a power supply terminal, and a second terminal connected to the output node of the voltage regulator. A voltage transition generator is capacitively coupled to the gate of the transistor to increase or decrease its driving power upon occurrence of an event in the target circuit indicating a change in current loading. The change in current loading can have an expected magnitude, and the voltage transition can have a magnitude that is a function of an expected magnitude of the increase or decrease in current loading.

BACKGROUND

Technical Field

The present invention relates to voltage regulators, including voltage regulators used in integrated circuits having rapidly changing loads.

Description of Related Art

Voltage regulators are utilized in integrated circuit design to provide a supply voltage to internal circuitry that can be more stable than an external power supply.

In integrated circuits having rapidly changing loads, the transient response of the voltage regulators can be a limiting property. If the current load of the target circuit changes rapidly, such as on the order of the transient response of the voltage regulator, then the regulated voltage provided can spike, overshoot, undershoot or fluctuate during the transition. These spikes or fluctuations can limit the effectiveness of the target circuit.

For example, a voltage regulator, in a class of regulators known as low dropout LDO voltage regulators, comprises a power MOSFET that is connected between an external power supply and the output node of the regulator. The gate of the power MOSFET is driven by an amplifier with a feedback loop to maintain constant voltage on the output node. The power MOSFET can be very large, and have a large gate capacitance. This large gate capacitance increases the time constant of the feedback loop, and makes the transient response of a typical LDO relatively slow compared to nanosecond scale switching in electronic circuits. As a result, a target circuit can be exposed to spikes or fluctuations in the regulated voltage during events that cause a change in current loading by the target circuit.

It is desirable to provide a voltage regulator suitable for use in integrated circuits, with a stable output voltage during fast transitions in current loading in a target circuit.

SUMMARY

A circuit and a method are described for supplying a regulated voltage to a target circuit characterized by fast changes in current loading. Circuits described herein include a voltage regulator to supply the regulated voltage to an output node. The voltage regulator has a transistor having a gate, a first terminal connected to a power supply terminal, and a second terminal connected to the output node of the voltage regulator. A voltage transition generator is capacitively coupled to the gate of the transistor. Logic circuitry is coupled to the voltage transition generator to induce a voltage transition at the gate upon occurrence of an event in the target circuit indicating a change in current loading, and thereby increase or decrease the gate-to-source voltage of the transistor, to change its driving power in a way that reduces fluctuations in the output voltage. The change in current loading can have an expected magnitude, and the voltage transition can have a magnitude that is a function of an expected magnitude of the increase or decrease in current loading.

The voltage transition generator can produce a stepped waveform, or other waveform shapes having fast transitions, synchronized with events indicating changes in current loading in the target circuit. The logic can be configured to cause a positive transition that increases the gate-to-source voltage magnitude in response to an event indicating an increase in current loading and a negative transition that decreases the gate-to-source voltage magnitude in response to an event indicating a decrease in current loading.

Thus, for example, an integrated circuit can include circuits such as state machines or processors that perform logic operations having predictable mode changes that cause rapid increases and decreases in current loading on the voltage regulator. The boosting circuit as described herein can be enabled to apply gate voltage adjustments upon transitions in current loading so that fluctuations in the regulated supply voltage upon occurrence of an event in the mode change are reduced or eliminated

A method for supplying a regulated voltage to a target circuit characterized by fast changes in current loading is also described. The method in one aspect comprises supplying the regulated voltage on an output node coupled to the target circuit, using a transistor having a gate, a first terminal connected to a power supply terminal, and a second terminal connected to the output node. By causing a voltage transition at the gate upon occurrence of an event in the target circuit, expected to cause a change in current loading, fluctuations in the regulated voltage are reduced or eliminated. The voltage transition is executed in some embodiments in response to the logic signal indicating occurrence of an event expected to cause the change in current loading. Causing the voltage transition can include generating a waveform having a voltage transition synchronized with events causing changes in current loading in the target circuit.

Other aspects and advantages of the present technology can be seen on review of the drawings, the detailed description and the claims, which follow.

DETAILED DESCRIPTION

A detailed description of embodiments of the present invention is provided with reference to theFIGS. 1-4.

FIG. 1illustrates a voltage regulator10connected to a target circuit12. The voltage regulator10, such as an LDO voltage regulator, is connected to a predictive boost circuit15. The voltage regulator10supplies a regulated voltage VDD_INT generated by the voltage regulator10as an internal supply voltage on an output node11to the target circuit12. The target circuit12includes a current sink13and control logic14. The control logic14can supply mode change signals M(i), where i is an index for a set of signals, to the current sink13which causes a fast change in current loading by the target circuit12. Also, the control logic14can supply one or more signals P(j), where j is an index for a set of signals, to predictive boost circuits15. The signals P(j) indicate events such as the events indicated by signals M(i), expected to cause changes in current loading in the current sink13. Although, as illustrated, the signals P(j) include at least one signal provided by the control logic14in the target circuit. In other configurations, logic outside the target circuit can produce the signals P(j). Also, the signals P(j) can be the same as the signals M(i) in some embodiments.

In one example, the target circuit12comprises an integrated circuit memory. The target circuit12can comprise a variety of circuits other than integrated circuit memory.

In the integrated circuit memory example, the current sink13includes a memory array and peripheral circuits used during operation of the memory array. The control logic14can include a state machine or other logic circuitry used to change the operating modes of the memory. For example, the memory can include a page read mode with error correction. A transition in mode change signal M(1) can be an event indicating a beginning of a page read operation. A transition in signal M(2) can be an event indicating the timing of a predicted transition in which there is a fast increase in current loading during the read operation. For example, during a page read operation with error correction, it can be predicted that there will be a rapid increase in current loading when error correction operations are initiated as the data is retrieved from the memory array. By way of example, the increase in current loading can occur on a nanosecond scale as the error correction circuits are engaged to process a page of data retrieved from the memory. A corresponding decrease in current loading can occur when the error correction operation completes. A signal M(3) can indicate the timing of a predicted transition in which there is a fast decrease in current loading during the read operation. The control logic14can provide signals P(1), P(2) and P(3) to the boost circuit15synchronized with corresponding signals M(1), M(2) and M(3), respectively. The control logic14can provide signals P(1), P(2) and P(3) in advance of the actual expected change in current loading, so that the voltage transition can be timed effectively to coincide with the expected current loading change.

FIG. 2is a circuit diagram of an embodiment of a voltage regulator with fast transient response according to the technology described herein. The circuit inFIG. 3includes an LDO voltage regulator that comprises an operational amplifier80coupled to an external power supply VDD_EXT, a transistor81, which is an n-channel power MOSFET in this example, having a drain coupled to the external power supply VDD_EXT and having a source coupled to the output node86. The operational amplifier80supplies a gate voltage VG on line84to the gate of transistor81. A feedback circuit is coupled between the output node and the “−” input of the operational amplifier. A voltage reference supplies VREF on line79to the “+” input of the operational amplifier. The voltage reference can be a bandgap reference.

The feedback circuit in this example includes resistors82and83in series between the output node86and ground, and connector85connecting a node between resistors82and83, at which a feedback voltage VFB is generated, to the “−” input. The resistors82,83have values R1and R2which can be set to determine the level of the internal supply voltage VDD_INT generated on the output node86.

The transistor81has a gate capacitance. The gate capacitance CC can be large in some embodiments, resulting in longer time constants for the feedback loop, and slower transient responses at the output node. A capacitor88is connected to the gate and to a node in the boost circuit15at which voltage transition signals are provided.

The output node86supplies the power supply voltage VDD_INT, and is connected to a target circuit, which can include system circuits87for an integrated circuit which are powered by VDD_INT. A gate boost circuit90is connected to the gate node (line84) by capacitive coupling via discrete capacitor88to the node.

The system circuits87in this example generate control signals P(i) which are used to control timing of the signals produced by the boost circuit90. The boost circuit can comprise a switching circuit having switches which boost voltage to a terminal of the capacitor88with a timing in response to the signals P(i). The boost voltage can have a magnitude that is a function of the expected change in current loading in the target circuit. The boost voltage can have a variable magnitude, or a magnitude selected from one of a plurality of fixed voltages, according to various implementations.

FIG. 2Ashows one example voltage switching circuit, suitable for use with gate boost circuit90. The switching circuit includes switch transistors151,152,153, which are connected at one terminal to corresponding voltage sources161,162,163having different voltage levels. The different voltage levels provided by voltage sources161,162,163can be set as appropriate for a given implementation, with examples shown in the figure set at 0.15 volts, 0.2 volts and 0.3 volts respectively. The transistors151,152,153are connected in common at another terminal to a node188, which can be connected to one plate of the capacitor88ofFIG. 2. The signals P(i) from system circuits87are applied to the gates of transistors151,152,153. In this example, P1is connected to the gate of transistor151. P2is connected to the gate of transistor152. P3is connected to the gate of transistor153.

The embodiment ofFIG. 2uses an LDO with an n-channel power transistor81. In alternative embodiments, an LDO with a p-channel power transistor can be used.

FIG. 3is a timing diagram referred to for the purposes of describing operation of the circuit ofFIGS. 1 and 2.

In general, the circuit shown inFIG. 2is an example that comprises an LDO voltage regulator supplying a regulated voltage on an output node. A gate boosting circuit is connected to the gate of a transistor driving the output node of the LDO voltage regulator. Logic is applied to cause the gate boosting circuit to apply a first voltage boost to the gate upon occurrence of, or synchronized with, a first event that increases current loading in the target circuit. Also, the logic causes the gate boosting circuit to apply a second voltage boost to the gate upon the occurrence of, or synchronized with, a second event that decreases current loading in the target circuit.

FIG. 3is a timing diagram referred to for the purpose of describing the operation of the circuits ofFIG. 1andFIG. 2. It includes a timing diagram (upper graph) for the logic signals M(1), M(2) and M(3) generated in a control logic which indicate mode changes for transitions between modes in the time intervals17,18and19during which transitions in current loading in the target circuit12are expected.FIG. 3also includes a timing diagram (middle graph) for current loading on the output node of the voltage regulator, in which a baseline current100is drawn by the voltage regulator, the current loading increases during the interval101upon assertion of the logic signal M(1), increases again during interval102upon assertion of the logic signal M(2), and decreases during interval103upon assertion of the logic signal M(3).

FIG. 3also includes the timing diagram (lower graph) for the boost voltage generated by the boost circuits. In this example, a signal P1corresponds with the first transition of the signal M1. This causes a positive transition in the voltage output by the boosting circuit, in order to boost the gate-to-source voltage of the transistor in the voltage regulator by a positive amount which corresponds with the expected increase in current loading upon transition to the interval101. A signal P2corresponds with the first transition of the signal M2. This causes a positive transition in the voltage output by the boosting circuit, in order to boost the gate-to-source voltage of the transistor in the voltage regulator by a positive amount which corresponds with the expected increase in current loading upon transition to the interval102. A signal P3corresponds with the first transition of the signal M3. This causes a negative transition in the voltage output by the boosting circuit, in order to boost the gate-to-source voltage by a negative amount which corresponds to the expected decrease in current loading upon transition to the interval103. The signal P4corresponds with the second transition of the signal M3in this example, causing a negative transition in the voltage output by the boosting circuit, in order to boost the gate-to-source voltage by a negative amount which corresponds to the expected decrease in current loading upon transition back to the baseline100.

Of course, the actual current levels occurring during the various modes of the target circuit may vary over time, and the transition amounts may differ from one instance of the mode change to another. However, the expected transition in current loading can be predicted based on simulation of the circuit designs, or empirical data.

Preferably, the transitions in the boost voltage corresponding with signals P1-P4precede the transitions in current loading indicated by the signals M1-M3. The timing of the transitions in the boost voltage should correspond with the changes in current loading within a time interval that is short relative to the frequency response of the amplifier and feedback loop of the voltage regulator.

In the example illustrated inFIG. 3, the boost voltage is a stepped waveform, with steps corresponding with expected changes in current loading.

FIG. 4illustrates a timing diagram referred to for the purpose of describing the operation of the circuits ofFIG. 1andFIG. 2using an alternative boosting circuit. It includes a timing diagram for the logic signals M(1), M(2) and M(3) generated in a control logic which indicate mode changes for transitions between modes in the time intervals47,48and49during which transitions in current loading in the target circuit12are expected.FIG. 4also includes a timing diagram for current loading on the output node of the voltage regulator, in which a baseline current200is drawn by the voltage regulator, the current loading increases during the interval201upon assertion of the logic signal M(1), increases again during interval202upon assertion of the logic signal M(2), and decreases during interval203upon assertion of the logic signal M(3).FIG. 4also includes the timing diagram for the boost voltage generated by the boost circuits. In this example, a signal P1corresponds with the first transition of the signal M1. This causes a positive transition in the voltage output by the boosting circuit, in order to boost the gate-to-source voltage of the transistor in the voltage regulator by a positive amount which corresponds with the expected increase in current loading upon transition to the interval201. The voltage output by the boost circuit ramps from its peak during the transition back to a baseline before the next transition. A signal P2corresponds with the first transition of the signal M2. This causes a positive transition in the voltage output by the boosting circuit, in order to boost the gate-to-source voltage of the transistor in the voltage regulator by a positive amount which corresponds with the expected increase in current loading upon transition to the interval202. Again, the voltage output by the boosting circuit ramps back to the baseline amount during the interval202before the next transition. A signal P3corresponds with the first transition of the signal M3. This causes a negative transition in the voltage output by the boosting circuit, in order to boost the gate-to-source voltage by a negative amount which corresponds to the expected decrease in current loading upon transition to the interval203. The voltage then ramps back up to the baseline for the next transition in current loading. The signal P4corresponds with the second transition of the signal M3in this example, causing a negative transition in the voltage output by the boosting circuit, in order to boost the gate-to-source voltage by a negative amount which corresponds to the expected decrease in current loading upon transition back to the baseline200.

Allowing the voltage applied by the boost circuit to return to the baseline between transitions can reduce the load on the feedback loop in the voltage regulator caused by the boost circuit, and can allow the boost circuit to operate with a narrower range of voltage magnitudes.

Of course, the actual current levels occurring during the various modes of the target circuit may vary over time, and the transition amounts may differ from one instance of the mode change to another. However, the expected transition can be predicted based on simulation of the circuit designs, or empirical data.

As mentioned with respect toFIG. 3the transitions in the boost voltage corresponding with signals P1-P4are synchronized with the transitions in current loading indicated by the signals M1-M3. The timing of the transitions in the boost voltage should correspond with the changes in current loading within a time interval that is short relative to the frequency response of the amplifier and feedback loop of the voltage regulator.

For the purposes of this description, the voltage boosting is applied “upon occurrence of an event” when it is applied on a timescale corresponding to the transient response of the voltage regulator, so that fluctuations in the regulated voltage as a result of the changes in loading current in the target circuits are reduced or eliminated. For the purposes of this description, an event is synchronized with another event when its timing is dependent on said other event, such as when controlled by a transition of a common logic signal.

Technology is described for producing a regulated voltage for circuits having fast changes in current loading that includes predictive circuits to boost the response time of the regulator, so that the regulated voltage will have a more stable value.