Method of forming split-gate flash memory cell with spacer defined floating gate and discretely formed polysilicon gates

A method of forming a memory device that includes forming a first polysilicon layer using a first polysilicon deposition over a semiconductor substrate, forming an insulation spacer on the first polysilicon layer, and removing some of the first polysilicon layer to leave a first polysilicon block under the insulation spacer. A source region is formed in the substrate adjacent a first side surface of the first polysilicon block. A second polysilicon layer is formed using a second polysilicon deposition. The second polysilicon layer is partially removed to leave a second polysilicon block over the substrate and adjacent to a second side surface of the first polysilicon block. A third polysilicon layer is formed using a third polysilicon deposition. The third polysilicon layer is partially removed to leave a third polysilicon block over the source region. A drain region is formed in the substrate adjacent to the second polysilicon block.

RELATED APPLICATION

This application claims the benefit of Chinese Patent Application No. 201910598339.9, as filed on Jul. 4, 2019, entitled “Method Of Forming Split-Gate Flash Memory Cell With Spacer Defined Floating Gate And Discretely Formed Polysilicon Gates.”

FIELD OF THE INVENTION

The present invention relates to split gate non-volatile memory cells

BACKGROUND OF THE INVENTION

Split gate non-volatile memory cells with three gates are known. See for example U.S. Pat. No. 7,315,056, which discloses split gate memory cells each having source and drain regions in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a control gate (also called a word line gate) over a second portion of the channel region, and a program/erase (P/E) gate over the source region.

Fabrication method improvements are needed to better control the formation of various elements of the memory cells.

BRIEF SUMMARY OF THE INVENTION

The aforementioned problems and needs are addressed a method of forming a memory device that includes:

forming a first polysilicon layer using a first polysilicon deposition over and insulated from a semiconductor substrate;

forming an insulation spacer on the first polysilicon layer;

removing some of the first polysilicon layer so as to leave a block of the first polysilicon layer under the insulation spacer, wherein the block of the first polysilicon layer has opposing first and second side surfaces;

forming a source region in the substrate adjacent the first side surface;

forming a second polysilicon layer using a second polysilicon deposition over the substrate;

removing some of the second polysilicon layer so as to leave a block of the second polysilicon layer that is over and insulated from the substrate, and adjacent to and insulated from the second side surface;

forming a third polysilicon layer using a third polysilicon deposition over the substrate;

removing some of the third polysilicon layer so as to leave a block of the third polysilicon layer that is over and insulated from the source region; and

forming a drain region in the substrate adjacent to the block of the second polysilicon layer.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is an improved method of forming non-volatile split gate memory cells having three gates per memory cell. While the figures show only a pair of memory cells being formed, it should be appreciated that an array of such memory cells are formed during the process. The process begins by first forming isolation regions, starting with forming an insulation layer12such as silicon dioxide (also referred to herein as “oxide”) on the upper surface of a semiconductor substrate10. A conductive layer14such as polysilicon (also referred to herein as “poly”) is formed on oxide layer12. An insulation layer16such as silicon nitride (also referred to herein as “nitride”) is formed on poly layer14. These layers are shown inFIG. 1A.

Photoresist is formed over the structure and patterned using a photolithography (masking) process (i.e., photoresist formation, selective exposure of the photoresist, removal of selective portions of the photoresist leaving portions of the underlying material exposed). Here, portions of the nitride layer16are left exposed. A series of etches are performed in those areas left exposed by the photoresist, to form trenches that extend through nitride layer16, poly layer14, oxide layer12and into the substrate10. The trenches are then filled with insulation material18(e.g. oxide) by oxide deposition and by oxide chemical mechanical polish, as shown inFIG. 1B(after photoresist removal). An oxide dry or wet etch polish is used to lower the tops of oxide18. A nitride etch is then used to remove nitride16, as shown inFIG. 1C. The tops of oxide18are preferably even with or slightly lower than the top surface of poly layer14. Oxide18, formed in trenches in this manner, is known in the art as shallow trench isolation (STI), and is used to define columns of active areas of the substrate10, with adjacent active area columns being insulated from each other by the STI oxide18.

Blocks of insulation material20(e.g. nitride) are formed on the poly layer14in each of the active regions. Each block20(to be used to form a pair of memory cells) can be formed, for example, by forming a layer of nitride on poly layer14, and performing a masking step to selectively cover portions the nitride layer with photoresist while leaving other portions exposed, and removing the exposed portions of the nitride layer using an anisotropic nitride etch, leaving blocks20on poly layer14. A polysilicon sloped etch is then used to etch the upper surface of poly layer14, creating a sloped upper surface for the poly layer14where the upper surface slopes upwardly as it approaches each block of nitride20. If desired, to control the floating gate threshold voltage, an implantation can then performed on the exposed portions of the poly layer14. The resulting structure for one of the nitride blocks is shown inFIG. 2A, which is a partial cross sectional view of one of the active regions (i.e. an orthogonal cross sectional view to that ofFIGS. 1A-1C).

Insulation spacers22(e.g., formed of oxide) are formed on the poly layer14. Formation of spacers is well known, and involves the deposition of material followed by an anisotropic etch of the material, whereby the material is removed except for portions thereof abutting vertically oriented structures. The upper surface of the spacer is typically rounded. In this case, oxide is deposited, followed by an anisotropic oxide etch leaving oxide spacers22abutting the side walls of nitride block20. A poly etch is performed to remove the portions of the poly layer14not protected by the oxide spacers22and nitride block20, as shown inFIG. 2B. To control the word line threshold voltage, an implant into the portions of the substrate10not protected by the nitride block20and oxide spacers22can be performed at this time (using oxide layer12on the substrate surface as a buffer layer).

Insulation spacers24are formed on the exposed ends of the poly layer14, which eventually will be the main isolation between the floating gates and word line gates of the finished memory cells. Insulation spacers24can be formed of oxide (by performing oxide deposition such as high temperature oxide (HTO) deposition and an anisotropic oxide etch). Insulation spacers24could instead be formed of a combination of oxide and nitride (by performing a nitride deposition and etch after the oxide deposition and etch). Insulation spacers24on disposed at the first ends (i.e., along first side surfaces15a) of the poly layer14. Conductive spacers26are then formed on the outer sides of spacers22/24, preferably by a polysilicon deposition and a polysilicon etch. The formation of conductive spacers26can include a buffer oxide deposition and oxide etch after the formation of the poly layer14and before the polysilicon spacer etch. The resulting structure is shown inFIG. 2C.

A nitride etch is performed to remove nitride block20, leaving the portion of poly layer14between oxide spacers22exposed. A poly etch is then performed to remove that exposed portion of the poly layer14, leaving distinct poly blocks14aunder the oxide spacers22. Each poly block14ahas an upwardly sloping upper surface that terminates in a sharp edge14bat an end of second side surface15bopposite the first side surface15a. An implant process follows for forming the source region28in the substrate10between the oxide spacers22and between poly blocks14a(i.e., the source region28is formed under a gap that exists between the oxide spacers22and a gap that exists between the poly blocks14a). An anneal can be performed at this point or later on, which will cause the source region28to extend partially under the poly blocks14a. An oxide layer30is then deposited on the structure, including on the exposed ends of the poly blocks14aadjacent the sharp edges14b. Oxide layer30can be referred to as a tunnel oxide layer, because electrons will tunnel through this layer during the erase operation for the finished memory cells. The resulting structure is shown inFIG. 2D.

A layer of polysilicon is then formed over the structure. This poly layer can be concurrently formed in a logic area of the same substrate (i.e., an area of the same substrate in which logic devices are formed). If it is desirous for the poly layer thickness to be thicker in the memory array area (in which the memory cells) than in the logic area, a cap oxide layer can be formed on the polysilicon layer and patterned to remove the cap oxide layer from the memory area of the device, followed by the deposition of additional polysilicon to thicken the poly layer in the memory area. The additional polysilicon on the cap oxide layer in the logic area can later be removed by a poly chemical mechanical polish (CMP). A poly etch is then performed to remove the poly layer in the memory array area, except for a block32of the poly layer disposed between the oxide spacers22. An implantation is then performed to form drain regions34in the substrate adjacent the poly spacers26, as shown inFIG. 2E.

As shown inFIG. 2E, the above described method forms pairs of memory cells36. Each memory cell pair includes a shared source region28and two drain regions34, with two channel regions38each extending between the source region28and one of the drain regions34. An erase gate32is disposed over and insulated from the source region28by oxide layers12and30. Each memory cell36includes a floating gate14adisposed over and insulated from (and controlling the conductivity of) a first portion of the channel region38, and a word line gate26disposed over and insulated from (and controlling the conductivity of) a second portion of the channel region38. The floating gate14ahas a sharp tip14b(resulting from the sloping surface) that faces a notch32aformed in the erase gate32. The sharp tip14bis insulated from the erase gate32by the tunnel oxide layer30. The overall insulation (oxide layers12and30) under erase gate32is greater than the overall insulation (oxide layer12) under floating gate14a.

Exemplary (non-limiting) operating voltages and current are summarized in Table 1 below, where voltages/current applied to the memory cell being programmed, erased or read (selected-SEL), and voltages applied to other memory cells (unselected-UnSEL), are indicated.

The above described process of forming pairs of memory cells36has several advantages. The floating gates14are self-aligned to the STI oxide18, and have dimensions in the channel direction that are defined by oxide spacers22(for better control). The word line gates26are self-aligned to the floating gates14a. Each memory cell36has three conductive gates (14a,26,32), each formed using a different polysilicon layer deposition, so the height of each can be independently optimized. The floating gate14ahas a sharp edge14bfacing the erase gate32for enhanced erase performance. The length of each word line gate26(in the direction of the channel region) is determined by spacer formation of the gate itself for better dimension control and without requiring a separate masking step. The isolation (oxide or oxide/nitride) between the floating gate14aand word line gate26can be independently optimized by spacer formation. Finally, the tunnel oxide30is formed as a single layer wrapping around the sharp tip14bof the floating gate14a. Using the above method, erase efficiency and word line gate performance can be independently optimized.

FIGS. 3A-3Cillustrate an alternate embodiment for forming the STI oxide18. The process begins by forming the same layers as shown inFIG. 1A, but without the poly layer14between the nitride layer16and oxide layer12, as shown inFIG. 3A. The nitride layer16is patterned (photoresist formation, exposure, selective removal, nitride etch), followed by oxide and silicon etches to form trenches that extend through nitride layer16, oxide layer12and into the substrate10. The trenches are then filled with insulation material18(e.g. oxide), as shown inFIG. 3B(after photoresist removal). A nitride etch is used to remove nitride layer16, and a poly layer14is formed on oxide layer12between the STI oxide18by poly deposition and etch. An oxide etch and/or chemical mechanical polish is used to lower the tops of STI oxide18even with, or slightly lower than, the top surface of poly layer14, as shown inFIG. 3C, which is equivalent to the structure shown inFIG. 1C.

FIGS. 4A-4Dillustrate an alternative embodiment for forming memory cells36, which begins with the same structure ofFIG. 2C, except without the formation of poly spacers26, as shown inFIG. 4A. A layer of polysilicon40is formed over the structure. A masked step is performed to cover the poly layer40with photoresist except for that portion over the nitride block20, as well as an additional portion over part of oxide spacers22adjacent nitride block20, which is left exposed. This exposed portion of poly layer40is removed by poly etch, as shown inFIG. 4B(after photoresist removal). A nitride etch is then performed to remove nitride block20, leaving the portion of poly layer14between oxide spacers22exposed. A poly etch is then performed to remove that exposed portion of the poly layer14, leaving distinct poly blocks14aunder the oxide spacers22. An implant process follows for forming the source region28in the substrate10between the oxide spacers22and poly blocks14a. An anneal can be performed at this point, or later on, which will cause the source region28to extend partially under the poly blocks14a. Oxide layer30is then deposited on the structure, including on the exposed ends of the poly blocks14aadjacent the sharp edges14b, and on the exposed surfaces of poly layer40. A layer of polysilicon42is then formed over the structure. The resulting structure is shown inFIG. 4C. Polysilicon and oxide etches are then used to remove polysilicon layers40and42, and portions of oxide layer30, except for poly block42aas the remaining portion of poly layer42between the oxide spacers22, and poly spacers40aon the outer sides of spacers22/24as the remaining portions of poly layer40, leaving portions of the substrate exposed for drain implantation. An oxide layer44is formed over the structure. An implantation is then performed to form the drain regions34in the substrate10adjacent the poly spacers40a. The final structure is shown inFIG. 4D.

FIGS. 5A-5Cillustrate another alternative embodiment for forming memory cells36, which begins with the structure ofFIG. 4C. A chemical mechanical polish (CMP) is used to planarize the top surface of the structure, down to the top surface of oxide spacers22(so there is no polysilicon on at least a portion of each oxide spacer22thus defining the distinct poly block42aas the remaining portion of poly layer42between oxide spacers22), as shownFIG. 5A. A masking step is performed to cover the poly block42aand portions of poly layer40with photoresist46, but leaving the rest of the structure exposed. Poly and oxide etches are performed to remove exposed portions of poly layers42/40and oxide layer30, leaving poly blocks40bas the remaining portions of poly layer40on the outer sides of spacers22/24, as shown inFIG. 5B. After photoresist removal, an oxide layer48is formed over the structure. An implantation is then performed to form the drain regions34in the substrate adjacent the poly blocks40b. The final structure is shown inFIG. 5C. While this embodiment includes an additional masking step, it provides word line gates with lengths in the channel region direction that are defined by the lithography masking process.

FIGS. 6A-6Dillustrate another alternate embodiment for forming memory cells36, which begins with the structure ofFIG. 4A. A layer of polysilicon52is formed over the structure. An oxide layer54is formed on poly layer52. A chemical mechanical polish is then used to remove portions of the oxide54and poly52that are over nitride block20and over oxide spacers22, as shown inFIG. 6A. The structure is optionally oxidized to form an oxide layer56on the exposed top portions of poly layer52, to protect poly layer52from the subsequent etch of poly layer14described below. If oxide layer56is omitted, the etch of poly layer14will result in top portions of poly layer52being removed, and therefore will result in shorter word line gates from poly layer52. A nitride etch is performed to remove nitride block20, leaving the portion of poly layer14between oxide spacers22exposed. A poly etch is then performed to remove that exposed portion of the poly layer14, leaving distinct poly blocks14aunder the oxide spacers22. An implant process follows for forming the source region28in the substrate10between the oxide spacers22and poly blocks14a. An anneal can be performed at this point, or later on, which will cause the source region28to extend partially under the poly blocks14a. The resulting structure is shown inFIG. 6B.

Oxide layer30is then deposited on the structure, including on the exposed ends of the poly blocks14aadjacent the sharp edges14b. A layer of polysilicon is then formed over the structure, followed by a poly etch that removes this polysilicon layer except for poly block58disposed between spacers22, as shown inFIG. 6C. A masking step is performed to cover the poly block58and portions of poly layer52with photoresist, but leaving the rest of the structure exposed. Poly and oxide etches are performed to remove exposed portions of poly layer52and oxide layers56/54, leaving poly blocks52aas the remaining portions of poly layer52on the outer sides of spacers22/24. After photoresist removal, an implantation is then performed to form the drain regions34in the substrate adjacent the poly blocks52a. The final structure is shown inFIG. 6D.

It should be noted that while the slope etch of the top surface of the floating gate14ais preferable to enhance erase efficiency, the slope etch can be omitted if enhanced erase efficiency is not desired. For example, if the slope etch described above with respect toFIG. 2Ais omitted, then the final memory cell structure shown inFIG. 2Ewould instead be that shown inFIG. 7, where floating gate14ahas a planar upper surface. Similarly, the final memory cell structure shown inFIG. 4Dwould instead be that shown inFIG. 8, the final memory cell structure shown inFIG. 5Cwould instead be that shown inFIG. 9, and the final memory cell structure shown inFIG. 6Dwould instead be that shown inFIG. 10.

It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of any claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the non-volatile memory cells of the present invention. Single layers of material could be formed as multiple layers of such or similar materials, and vice versa. Lastly, the terms “forming” and “formed” as used herein shall include material deposition, material growth, or any other technique in providing the material as disclosed or claimed.

It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed there between) and “indirectly on” (intermediate materials, elements or space disposed there between). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed there between) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.