Normally off III nitride transistor

A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

FIELD OF THE INVENTION

This invention relates to the field of semiconductor devices. More particularly, this invention relates to III-N field effect transistors in semiconductor devices.

BACKGROUND OF THE INVENTION

An enhancement mode gallium nitride field effect transistor (GaN FET) includes a recessed gate extending into a stressor layer and barrier layer, and vertically separated from a low-doped gallium nitride (GaN) layer. Forming the gate recess by etching to have a desired vertical separation from the low-doped GaN layer is problematic. Timed etching results in unacceptable variation in the separation from the low-doped GaN layer. Forming the gate recess using etch-blocking layers produces defects in the barrier layer and/or the stressor layer.

SUMMARY OF THE INVENTION

A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack including a low-doped GaN layer, a barrier layer including aluminum disposed over the low-doped GaN layer, a stressor layer including indium disposed over the barrier layer, and a cap layer including aluminum disposed over the stressor layer. A gate recess of the enhancement mode GaN FET extends through the cap layer and the stressor layer, but not through the barrier layer. A gate dielectric layer is disposed in the gate recess and a gate is disposed on the gate dielectric layer.

The semiconductor device is formed by forming the barrier layer with a high temperature metal organic chemical vapor deposition (MOCVD) process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack including a low-doped GaN layer, a barrier layer including aluminum disposed over the low-doped GaN layer, a stressor layer including indium disposed over the barrier layer, and a cap layer including aluminum disposed over the stressor layer. A gate recess of the enhancement mode GaN FET extends through the cap layer and the stressor layer, but not through the barrier layer. A gate dielectric layer is disposed in the gate recess and a gate is disposed on the gate dielectric layer.

The semiconductor device may also include a depletion mode GaN FET with a planar gate over the cap layer and stressor layer. A gate dielectric layer and the planar gate of the depletion mode GaN FET may be formed concurrently with the gate dielectric layer and the gate of the enhancement mode GaN FET.

The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer. The stressor layer may be oxidized by an anodic oxidation process in the gate recess to facilitate removal by the second etch step.

For the purposes of this description, the term “III-N material” is understood to refer to semiconductor materials in which group III elements, that is, aluminum, gallium and indium, and possibly boron, provide a portion of the atoms in the semiconductor material and nitrogen atoms provide the remainder of the atoms in the semiconductor material. Examples of III-N semiconductor materials are gallium nitride, boron gallium nitride, aluminum gallium nitride, indium nitride, and indium aluminum gallium nitride. Terms such as aluminum gallium nitride describing elemental compositions of materials do not imply a particular stoichiometry of the elements. For the purposes of this description, the term GaN FET is understood to refer to a field effect transistor which includes III-N semiconductor materials.

FIG. 1is a cross section of an example semiconductor device. The semiconductor device100includes an enhancement mode GaN FET102and a depletion mode GaN FET104. The semiconductor device100includes a substrate106which may be a wafer of silicon or other semiconductor material. A buffer layer108of III-N material is disposed over the substrate106. The buffer layer108may include for example, 100 to 300 nanometers of aluminum nitride on the substrate106and 1 to 7 microns of graded layers of AlxGa1-xN which is aluminum rich at a bottom surface, on the aluminum nitride, and gallium rich at a top surface of the buffer layer (108). An electrical isolation layer (110) is disposed on the buffer layer (108). The electrical isolation layer (110) may be, for example, 300 to 2000 nanometers of semi-insulating gallium nitride. The electrical isolation layer (110) may be, for example, semi-insulating to provide a desired level of electrical isolation between layers below the electrical isolation layer (110) and layers above the electrical isolation layer (110). Alternatively, the electrical isolation layer (110) may be doped with n-type or p-type dopants to reduce undesired effects of charge trapping on current density in the semiconductor device (100). A low-doped layer (112) is disposed on the electrical isolation layer (110). The low-doped layer (112) may be, for example, 25 to 1000 nanometers of gallium nitride. The low-doped layer (112) may be formed so as to minimize crystal defects which may have an adverse effect on electron mobility. The method of formation of the low-doped layer (112) may result in the low-doped layer (112) being doped with carbon, iron or other dopant species, for example with a net doping density less than 1017cm−3.

A barrier layer114is disposed over the low-doped layer112. The barrier layer114may be primarily aluminum gallium nitride, with less than 1 atomic percent indium. The barrier layer114may have a stoichiometry of Al0.10Ga0.90N to Al0.30Ga0.70N, and a thickness of 1 nanometers to 5 nanometers. A minimum thickness of the barrier layer114may be selected to provide ease and reproducibility of fabrication; a maximum thickness may be selected to provide a desired off-state current in the enhancement mode GaN FET102, where increasing the thickness of the barrier layer114increases the off-state current. The thickness may depend on a stoichiometry of the barrier layer114. For example, an instance of the barrier layer114with a stoichiometry of Al0.10Ga0.90N to Al0.30Ga0.70N may have a thickness of 1.5 nanometers to 2.0 nanometers.

A stressor layer116is disposed over the barrier layer114. The stressor layer116is primarily indium aluminum nitride, with a stoichiometry of In0.05Al0.95N to In0.30Al0.70N, and a thickness of 1 nanometers to 5 nanometers. In one version of the instant example, the stressor layer116may have a stoichiometry of In0.16Al0.84N to In0.18Al0.82N and a thickness of 3.5 nanometers to 4.5 nanometers, which may provide a desired balance between providing a desired charge density in a two-dimensional electron gas (2DEG), which decreases with indium content, and providing a desired etch selectivity to the underlying barrier layer114, which increases with indium content. The stoichiometry of In0.16Al0.84N to In0.18Al0.82N may also provide a desired lattice match to the low-doped layer112.

A cap layer118is disposed over the stressor layer116. The cap layer118has less than 1 atomic percent indium, and may be primarily aluminum gallium nitride. A thickness of the cap layer is selected to prevent oxidation of the stressor layer116during subsequent fabrication steps. An example cap layer118may have a stoichiometry of Al0.05Ga0.95N to Al0.30Ga0.70N, and a thickness of 4 nanometers to 20 nanometers. The cap layer118advantageously prevents oxidation of the indium in the stressor layer116.

A gate recess120extends through the cap layer118and the stressor layer116in the enhancement mode GaN FET102. The gate recess120may extend completely through the stressor layer116and not extend into the barrier layer114, as depicted inFIG. 1. Alternatively, the gate recess120may extend partway into the barrier layer114, or may extend only partway through the stressor layer116and stop short of the barrier layer114.

An enhancement mode gate dielectric layer122is disposed in the gate recess120in the enhancement mode GaN FET102. A depletion mode gate dielectric layer124is disposed over the cap layer in the depletion mode GaN FET104. The enhancement mode gate dielectric layer122and the depletion mode gate dielectric layer124may be 5 nanometers to 50 nanometers thick and may include one or more layers of silicon dioxide, silicon nitride and/or aluminum oxide. In one version of the instant example, the enhancement mode gate dielectric layer122and the depletion mode gate dielectric layer124may have substantially equal thicknesses and compositions, possibly as a result of being formed concurrently. In an alternate version, the enhancement mode gate dielectric layer122and the depletion mode gate dielectric layer124may have different thicknesses and compositions, so as to separately optimize performance of the enhancement mode GaN FET102and the depletion mode GaN FET104.

A field plate dielectric layer126may optionally be disposed over the cap layer118and under the enhancement mode gate dielectric layer122adjacent to the gate recess120and under the depletion mode gate dielectric layer124adjacent to a gate area in the depletion mode GaN FET104. The field plate dielectric layer126may include one or more layers of silicon dioxide and/or silicon nitride, and may be, for example, 10 nanometers to 100 nanometers thick. In an alternate version of the instant example, the field plate dielectric layer126may be disposed over the enhancement mode gate dielectric layer122and the depletion mode gate dielectric layer124.

An enhancement mode gate128is disposed over the enhancement mode gate dielectric layer122in the gate recess120. The enhancement mode gate128may overlap the field plate dielectric layer126in the enhancement mode GaN FET102, as depicted inFIG. 1. A depletion mode gate130is disposed over the depletion mode gate dielectric layer124in the gate area of the depletion mode GaN FET104and may overlap the field plate dielectric layer126in the depletion mode GaN FET104, as depicted inFIG. 1. The enhancement mode gate128and the depletion mode gate130may have substantially equal compositions, possibly as a result of being formed concurrently.

Dielectric isolation structures132extend through the cap layer118, the stressor layer116and the barrier layer114and possibly through the low-doped layer (112), so as to laterally isolate the enhancement mode GaN FET (102) and the depletion mode GaN FET (104). The dielectric isolation structures132may include, for example, silicon dioxide and/or silicon nitride.

A source contact134and a drain contact136provide electrical connections to a 2DEG in the enhancement mode GaN FET102. A source contact138and a drain contact140provide electrical connections to a 2DEG in the depletion mode GaN FET104.

During operation of the semiconductor device100, the barrier layer114advantageously provides a low carrier density in the 2DEG of the enhancement mode GaN FET102under the gate recess120, so as to provide a desired off-state current. The stressor layer116advantageously provides a desired high carrier density in the 2DEG of the enhancement mode GaN FET102in the access regions between the gate recess120and the source contact134and the drain contact136, so as to provide a desired on-state current. The configuration of the gate recess120extending through the stressor layer116advantageously contributes to the low carrier density in the 2DEG of the enhancement mode GaN FET102under the gate recess120. The stressor layer116extending under the depletion mode gate130advantageously provides a desired on-state current in the depletion mode GaN FET104.

FIG. 2AthroughFIG. 2Iare cross sections of the semiconductor device ofFIG. 1depicted in successive stages of an example fabrication sequence. Referring toFIG. 2A, the buffer layer108is formed over the substrate106. The electrical isolation layer (110) is formed over the buffer layer (108), and the low-doped layer (112) is formed over the electrical isolation layer (110). The buffer layer108, the electrical isolation layer (110) and the low-doped layer (112) may be formed, for example, by a series of MOCVD processes.

In the instant example, process parameters will be described for a case wherein the substrate106is a 150 millimeter substrate. The substrate106is placed on a susceptor142, possibly of graphite, in an MOCVD chamber144. The susceptor142is heated, for example by heating coils, to a temperature of 900° C. to 1100° C. A carrier gas such as hydrogen (H2) as indicated inFIG. 2Ais flowed into the MOCVD chamber144at a flow rate of 80 standard liters per minute (slm) to 120 slm, and a nitrogen source such as ammonia (NH3) as indicated inFIG. 2Ais flowed into the MOCVD chamber144at a flow rate of 5 slm to 30 slm. An aluminum precursor such as trimethylaluminum (TMAl) as indicated inFIG. 2A, or triethylaluminum, is flowed into the MOCVD chamber144at a rate of 80 standard cubic centimeters per minute (sccm) to 130 sccm and a gallium precursor such as trimethylgallium (TMGa) as indicated inFIG. 2A, or triethylgallium, is flowed into the MOCVD chamber144at a rate of 40 sccm to 60 sccm. A pressure in the MOCVD chamber144is maintained at 50 torr to 200 torr. The nitrogen source, the aluminum precursor and the gallium precursor react at the existing surface of the semiconductor device100to form the barrier layer114over the low-doped layer112in the areas for the enhancement mode GaN FET102and the depletion mode GaN FET104. Forming the barrier layer114at a temperature of 900° C. to 1100° C. advantageously provides fewer defects and hence higher reliability for the semiconductor device100compared to a barrier layer formed at a lower temperature. In the instant example, substantially no indium precursor is flowed into the MOCVD chamber144while the barrier layer114is formed. In an alternate version of the instant example, the barrier layer114may include a quaternary III-N material, that is, may include another element in addition to aluminum, gallium and nitrogen. The barrier layer114may be formed in situ after the low-doped layer (112) to advantageously reduce defects in the semiconductor device (100).

Referring toFIG. 2B, the substrate106remains on the susceptor142in the MOCVD chamber144. The susceptor142is heated to a temperature of 700° C. to 850° C. A carrier gas, indicated inFIG. 2Bas nitrogen (N2), is flowed into the MOCVD chamber144at a flow rate of 60 slm to 100 slm, and a nitrogen source, indicated inFIG. 2Bas ammonia (NH3), is flowed into the MOCVD chamber144at a flow rate of 5 slm to 40 slm. An aluminum precursor, indicated inFIG. 2Bas trimethylaluminum (TMAl), is flowed into the MOCVD chamber144at a rate of 80 sccm to 130 sccm and an indium precursor such as trimethylindium (TMIn) as indicated inFIG. 2B, or triethylindium, is flowed into the MOCVD chamber144at a rate of 100 sccm to 300 sccm. A pressure in the MOCVD chamber144is maintained at 100 torr to 400 torr. The nitrogen source, the aluminum precursor and the indium precursor react at the existing surface of the semiconductor device100to form the stressor layer116over the barrier layer114in the areas for the enhancement mode GaN FET102and the depletion mode GaN FET104. Forming the stressor layer116at a minimum temperature of 700° C. may advantageously enable a desired concentration of indium and uniform distribution of indium in the stressor layer116compared to forming at a lower temperature. Forming the stressor layer116at a maximum temperature 850° C. may advantageously reduce indium diffusion into the barrier layer114compared to forming at a higher temperature. In the instant example, substantially no aluminum precursor is flowed into the MOCVD chamber144while the stressor layer116is formed. In an alternate version of the instant example, the stressor layer116may include a quaternary III-N material. Forming the stressor layer116in situ with the barrier layer114may advantageously reduce defects in the semiconductor device (100).

Referring toFIG. 2C, the substrate106remains on the susceptor142in the MOCVD chamber144. The susceptor142is heated to a temperature of 750° C. to 900° C. A carrier gas, indicated inFIG. 2Cas hydrogen (H2), is flowed into the MOCVD chamber144at a flow rate of 80 slm to 120 slm, and a nitrogen source, indicated inFIG. 2Cas ammonia (NH3), is flowed into the MOCVD chamber144at a flow rate of 5 slm to 35 slm. An aluminum precursor, indicated inFIG. 2Cas trimethylaluminum (TMAl), is flowed into the MOCVD chamber144at a rate of 80 sccm to 130 sccm and a gallium precursor, indicated inFIG. 2Cas trimethylgallium (TMGa), is flowed into the MOCVD chamber144at a rate of 40 sccm to 60 sccm. A pressure in the MOCVD chamber144is maintained at 50 torr to 200 torr. The nitrogen source, the aluminum precursor and the gallium precursor react at the existing surface of the semiconductor device100to form the cap layer118over the stressor layer116in the areas for the enhancement mode GaN FET102and the depletion mode GaN FET104. Forming the cap layer118at a maximum temperature of 900° C. may advantageously reduce indium diffusion into the barrier layer114and the cap layer118compared to forming at a higher temperature. In the instant example, substantially no indium precursor is flowed into the MOCVD chamber144while the cap layer118is formed. The cap layer118may be formed in situ after the stressor layer (116) to advantageously reduce defects in the semiconductor device (100).

Referring toFIG. 2D, the field plate dielectric layer126is formed over the cap layer118. The field plate dielectric layer126may be formed, for example, by forming a layer of dielectric material containing silicon dioxide and/or silicon nitride over the cap layer by a plasma enhanced chemical vapor deposition (PECVD) process. A field plate mask146is formed over the layer of dielectric material so as to expose gate areas for the enhancement mode GaN FET102and the depletion mode GaN FET104. The layer of dielectric material is removed where exposed by the field plate mask146by an etch process such as a plasma etch process at over 100 torr, forming the field plate dielectric layer126with sloped sides as depicted inFIG. 2D.

Referring toFIG. 2E, a recess mask148is formed over the cap layer118to expose an area in the enhancement mode GaN FET102for the gate recess120. The recess mask148may include photoresist and may be formed by a photolithographic process. The recess mask148may further include an antireflection layer such as an organic bottom antireflection coating (BARC) and/or a hard mask layer such as silicon dioxide or silicon nitride. The recess mask148covers the area for the depletion mode GaN FET104.

A first etch process150such as a plasma etch process using chlorine radicals removes the cap layer118in the area exposed by the recess mask148to form a portion of the gate recess120. The indium in the stressor layer116has a lower etch rate in the first etch process150than the cap layer118, so at least a portion of the stressor layer116remains in the area for the gate recess120after the first etch process150is completed. The first etch process150may be, for example, an inductively-coupled plasma reactive ion etch (ICP-RIE) process using chlorine (Cl2) gas sulfur hexafluoride (SF6) gas, which has been demonstrated to desirably provide an etch selectivity of gallium aluminum nitride to indium aluminum nitride greater than 1.0. Forming the cap layer118at a maximum temperature of 900° C., in combination with the indium content in the stressor layer116, may advantageously increase the etch selectivity for the first etch process150so as to reduce the amount, if any, of the stressor layer116removed by the first etch process150.

Referring toFIG. 2F, a second etch process152removes the stressor layer116in the gate recess120to form the complete gate recess120. The second etch process152has a different chemistry than the first etch process150ofFIG. 2E. The barrier layer114has a lower etch rate in the second etch process152than the stressor layer116, so at least a portion, and possibly all, of the barrier layer114remains under the gate recess120after the second etch process152is completed. The second etch process152may include, for example, a wet etch process using a 1 molar aqueous solution of 1,2 diaminoethane, which has been demonstrated to desirable provide an etch selectivity of indium aluminum nitride to gallium aluminum nitride eater than 1.0 at room temperature. The first etch process150may provide a desirably rough surface on the exposed stressor layer116which may advantageously provide a more uniform initial etch rate for the second etch process152.

Referring toFIG. 2G, there may be a remaining portion154of the stressor layer116in the gate recess120, possibly a transition layer154which includes elements of the underlying barrier layer114. An oxidizing liquid156oxidizes the remaining portion154of the stressor layer116in the gate recess120. The remaining portion154of the stressor layer116may be oxidized by an anodic oxidation process in which electrical current is passed through the oxidizing liquid156. For example, the oxidizing liquid156may be an aqueous solution of nitriloacetic acid and 0.3 molar potassium hydroxide (KOH) with a pH value of 8.5. The electrical current may have a value of about 20 microamperes per square centimeter of exposed stressor layer116. The oxidized remaining portion154may be subsequently removed, for example by a wet etch process using a dilute aqueous acidic solution, such as a dilute nitric acid solution or a citric acid solution. The recess mask148is removed, possibly after the wet etch process152ofFIG. 2Fis completed, or possibly earlier.

Referring toFIG. 2H, a layer of gate dielectric material158is formed over the field plate dielectric layer126, extending into the gate recess120and overlying the barrier layer114at a bottom of the gate recess120. In the instant example, the layer of gate dielectric material158extends over the cap layer118in the depletion mode GaN FET104. The layer of gate dielectric material158may include one or more layers of silicon dioxide and/or silicon nitride, formed, for example, by PECVD processes. A layer of gate material160is formed over the layer of gate dielectric material158. The layer of gate material160may include, for example, gallium nitride or other III-N material, or may include polycrystalline silicon, referred to as polysilicon, or may include metal. In the instant example, the layer of gate material160is formed in the areas for the gates of both the enhancement mode GaN FET102and the depletion mode GaN FET104.

Referring toFIG. 2I, the layer of gate material160ofFIG. 2His patterned to concurrently form the enhancement mode gate128and the depletion mode gate130. The enhancement mode gate128and the depletion mode gate130may be formed by an etch process: forming an etch mask over the layer of gate material160which covers area for the enhancement mode gate128and the depletion mode gate130, and subsequently removing the layer of gate material160where exposed by the etch mask. Alternatively, the enhancement mode gate128and the depletion mode gate130may be formed by a liftoff process: forming a liftoff mask of solvent-soluble organic material such as photoresist which exposes the layer of gate dielectric material158in the areas for the enhancement mode gate128and the depletion mode gate130, forming the layer of gate material160over the liftoff mask, and subsequently removing the liftoff mask and the overlying layer of gate material160, leaving the layer of gate material160in the areas exposed by the liftoff mask to provide the enhancement mode gate128and the depletion mode gate130. Forming the enhancement mode gate128and the depletion mode gate130concurrently may advantageously reduce fabrication cost and complexity of the semiconductor device100. In an alternate version of the instant example, the enhancement mode gate128and the depletion mode gate130may be formed separately, of materials with different work functions, to increase performance of both the enhancement mode GaN FET102and the depletion mode GaN FET104. After forming the enhancement mode GaN FET102and the depletion mode GaN FET104, fabrication is continued to provide the structure ofFIG. 1.

FIG. 3AandFIG. 3Bare cross sections of the semiconductor device ofFIG. 1depicted in an alternate process sequence for forming the gate recess. Referring toFIG. 3A, the recess mask148is formed over the cap layer118. The cap layer118is removed in the area exposed by the recess mask148to form a portion of the gate recess120, as described in reference toFIG. 2E. An oxidizing liquid162, for example an anodizing aqueous solution containing an aqueous solution of nitriloacetic acid and 0.3 molar KOH with a pH value of 8.5 with an electrical current of about 20 microamperes per square centimeter of exposed stressor layer116, oxidizes the stressor layer116where exposed by the cap layer118in the gate recess120to form an oxidized stressor layer164which includes indium oxide. In the instant example, the barrier layer114may include a layer of gallium nitride (GaN) 1 nanometer to 3 nanometers thick immediately below the stressor layer116to prevent oxidation of the aluminum gallium nitride in the barrier layer114. At least a portion of the barrier layer114under the stressor layer116in the gate recess120is not oxidized.

Referring toFIG. 3B, a second etch process166removes the oxidized stressor layer164ofFIG. 3Ato form the gate recess120, while leaving at least a portion, and possibly all, of the barrier layer114under the gate recess120. The second etch process166may include, for example, a dilute aqueous solution of nitric acid, phosphoric acid, and/or hydrochloric acid, or an aqueous solution of an organic acid such as citric acid. The oxidation process described in reference toFIG. 3Aand the second etch process ofFIG. 3Bmay be repeated to completely remove the stressor layer116from the gate recess120. The recess mask148is removed and fabrication is continued as described in reference toFIG. 2G.