SEMICONDUCTOR DEVICE HAVING DIE RING CONDUCTOR

An apparatus that includes first and second circuit blocks integrated on a semiconductor chip, and a die ring conductor provided along edges of the semiconductor chip so as to surround the first and second circuit blocks. The first circuit block includes a first die ring controller. The second circuit block includes a second die ring controller. One of the first and second die ring controllers is coupled to the die ring conductor such that another of the first and second die ring controllers is isolated from the die ring conductor.

BACKGROUND

Some semiconductor devices include a die ring provided along the peripheral edge of a chip. When a crack is generated on the periphery of a chip during dicing of a wafer, the die ring is isolated. Accordingly, the crack generated on the chip can be detected.

DETAILED DESCRIPTION

Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects, and various embodiments of the present disclosure. The detailed description provides sufficient detail to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

FIG.1is a schematic plan view for explaining a configuration of a semiconductor device10according to one embodiment of the present disclosure. The semiconductor device10shown inFIG.1is integrated on a semiconductor chip20made of silicon, or the like. The semiconductor chip20includes edges21and22extending in an X direction, and edges23and24extending in a Y direction. In some examples, the X direction may be perpendicular to the Y direction. The semiconductor device10includes two channels CHA and CHB that can operate independently of each other.

As shown inFIG.2, the channels CHA and CHB respectively include DRAMs (Dynamic Random Access Memories)40A and40B in the present embodiment. External terminals41A to44A allocated to the channel CHA are coupled to the DRAM40A constituting the channel CHA, and external terminals41B to44B allocated to the channel CHB are coupled to the DRAM40B constituting the channel CHB. Command address signals CAA and CAB are input to the external terminals41A and41B, respectively. User data DQA and DQB are input/output to/from the external terminals42A and42B, respectively. External power potentials VDDA and VDDB are supplied to the external terminals43A and43B, respectively. Ground potentials VSSA and VSSB are supplied to the external terminals44A and44B, respectively. A power line supplied with the external power potential VDDA and a power line supplied with the external power potential VDDB are independent of each other without being coupled to each other inside the semiconductor chip20. Similarly, a power line supplied with the ground potential VSSA and a power line supplied with the ground potential VSSB are independent of each other without being coupled to each other inside the semiconductor chip20. The channels CHA and CHB have internal power-up circuits45A and45B, respectively. The internal power-up circuit45A generates an internal power potential VintA on the basis of the external power potential VDDA and the ground potential VSSA. The internal power-up circuit45B generates an internal power potential VintB on the basis of the external power potential VDDB and the ground potential VSSB. The internal power potentials VintA and VintB are used as operating power for the DRAMs40A and40B, respectively. A power line supplied with the internal power potential VintA and a power line supplied with the internal power potential VintB are also independent of each other without being coupled to each other inside the semiconductor chip20. The internal power-up circuit45A activates a power-up signal PUPA to a high level when supplied with the external power potential VDDA. Similarly, the internal power-up circuit45B activates a power-up signal PUPB to a high level when supplied with the external power potential VDDB. When the power-up signals PUPA and PUPB are activated, the DRAMs40A and40B are initialized, respectively.

As shown inFIG.1, the channels CHA and CHB are surrounded by a die ring30extending along the edges21to24. The die ring30includes a section31surrounding the channel CHA, and a section32surrounding the channel CHB. The section31extends along the edges21to23. The section32extends along the edges21,22, and24. The section31of the die ring30bifurcates at ends311and313. The end311is coupled to a signal node N1of a die ring controller51via a switch61and is coupled to a signal node N7of a buffer circuit54via a switch67. The end313is coupled to a signal node N5of a buffer circuit53via a switch65and is coupled to a signal node N3of a die ring controller52via a switch63. The section32of the die ring30bifurcates at ends322and324. The end322is coupled to a signal node N2of the die ring controller51via a switch62and is coupled to a signal node N8of the buffer circuit54via a switch68. The end324is coupled to a signal node N6of the buffer circuit53via a switch66and is coupled to a signal node N4of the die ring controller52via a switch64. The die ring controllers51and52are circuits for detecting isolation of the die ring30and belong to the channels CHA and CHB, respectively. The buffer circuits53and54are circuits for buffering signals output from the die ring controllers51and52and belong to the channels CHA and CHB, respectively.

FIG.3is a schematic diagram for explaining an example of a configuration of the die ring30. In the example shown inFIG.3, the die ring30is constituted of six conductor layers including a polysilicon layer P and metal layers M0to M4. The section31of the die ring30is constituted of three lines including a clock line31C, a sense line31S, and an enable line31E. Similarly, the section32of the die ring30is constituted of three lines including a clock line32C, a sense line32S, and an enable line32E. The clock lines31C and32C are mainly formed in the metal layers M1and M4, the sense lines31S and32S are mainly formed in the metal layers M0and M3, and the enable lines31E and32E are mainly formed in the polysilicon layer P and the metal layer M2. In this way, the die ring30constitutes a wall-like conductor group including the six conductor layers. Since this wall-like conductor group is provided along the edges21to24of the semiconductor chip20, the die ring30is isolated when a crack is generated on the periphery of the semiconductor chip20during dicing of a wafer. Isolation of the die ring30is detected by the die ring controller51or52.

As shown inFIG.1, the switches61,62,65, and66belonging to the channel CHA are turned on when an enable signal CHAEn is activated, and the switches63,64,67, and68belonging to the channel CHB are turned on when an enable signal CHBEn is activated. The enable signal CHAEn is generated by an enable circuit71belonging to the channel CHA, and the enable signal CHBEn is generated by an enable circuit72belonging to the channel CHB.FIG.4is a circuit diagram of the enable circuits71and72. As shown inFIG.4, the enable circuit72includes a complex gate that receives the power-up signals PUPA and PUPB. The enable circuit72activates the enable signal CHBEn to a high level when the power-up signal PUPA has a low level and the power-up signal PUPB has a high level. The enable circuit71includes a complex gate that receives the power-up signal PUPA and the enable signal CHBEn. The enable circuit71activates the enable signal CHAEn to a high level when the power-up signal PUPA has a high level and the enable signal CHBEn has a low level. Accordingly, when the power-up signal PUPA is activated to a high level, the enable signal CHAEn is activated to a high level irrespective of the power-up signal PUPB. The enable signal CHBEn is activated to a high level only when the power-up signal PUPA is deactivated to a low level and the power-up signal PUPB is activated to a high level. In this way, the enable signal CHAEn is configured to be activated in priority to the enable signal CHBEn. Not both the enable signal CHAEn and the enable signal CHBEn are activated.

When the enable signal CHAEn is activated, the switches61,62,65, and66are all turned on. Accordingly, the die ring controller51and the buffer circuit53are circularly coupled via the sections31and32of the die ring30as shown inFIG.5. Therefore, when the die ring30is isolated due to a crack generated on the semiconductor chip20, this is detected by the die ring controller51. When an input signal IN is activated, the die ring controller51inputs and outputs a bidirectional sense signal to and from the sense lines31S and32S and outputs an enable signal and a clock signal to the enable lines31E and32E and the clock lines31C and32C, respectively. The sense signal is a signal for detecting the state of the die ring30. The enable signal is a signal for activating internal circuits included in the die ring controller51and the buffer circuit53. The clock signal is a timing signal for a circuit that performs a digital operation among the internal circuits included in the die ring controller51and the buffer circuit53. The die ring controller51detects whether the die ring30is isolated using the sense signal, the enable signal, and the clock signal and outputs the detection result as an output signal OUT. Since the sense signal is a bidirectional signal, which of the sections31and32includes isolation of the die ring30can also be determined. The same holds for a case in which the enable signal CHBEn is activated. Since the switches63,64,67, and68are all turned on, the die ring controller52and the buffer circuit54are circularly coupled via the sections31and32of the die ring30.

With this circuit configuration, when the operation of the channel CHA is started with activation of the power-up signal PUPA, the enable signal CHAEn is activated, whereby the die ring controller51and the buffer circuit53are coupled to the die ring30while the die ring controller52and the buffer circuit54are isolated from the die ring30. The die ring controller51and the buffer circuit53both belong to the channel CHA and operate with a voltage between the external power potential VDDA or the internal power potential VintA, and the ground potential VSSA. The same holds for a case in which both the operations of the channels CHA and CHB are started with activation of both the power-up signals PUPA and PUPB. In contrast thereto, when only the power-up signal PUPB is activated without activation of the power-up signal PUPA and accordingly only the channel CHB starts operating, the enable signal CHBEn is activated, whereby the die ring controller52and the buffer circuit54are coupled to the di ring30while the die ring controller51and the buffer circuit53are isolated from the die ring30. The die ring controller52and the buffer circuit54both belong to the channel CHB and operate with a voltage between the external power potential VDDB or the internal power potential VintB, and the ground potential VSSB.

As described above, the semiconductor device10according to the present embodiment includes the two channels CHA and CHB that can operate independently of each other, and power supplies used by these channels CHA and CHB are independent of each other. However, since either of the power supplies is used for control of the die ring30, an unexpected malfunction can be prevented. Even when one of the channels CHA and CHB has a defect and only the other channel operates, the properly-operating channel automatically executes control of the die ring30. Alternatively, the die ring30may be fixedly coupled to one of the channels using a so-called “metal option”. In a semiconductor device11shown inFIG.6, the die ring30is fixedly coupled to the die ring controller51and the buffer circuit53by isolating lines between the end311and the switch67, between the end313and the switch63, between the end322and the switch68, and between the end324and the switch64with metal options. In this way, the channel coupled to the die ring30may be switched using metal options.

Although the embodiment has been explained above with an example of the semiconductor device10including the two channels CHA and CHB, the number of channels integrated on one semiconductor chip20is not limited to two, and three or more channels may be included. Further, the channels do not need to be DRAMs and may be any circuit blocks operating independently of each other.

Although various embodiments have been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the embodiments and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this disclosure will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments. Thus, it is intended that the scope of at least some of the present disclosure should not be limited by the particular disclosed embodiments described above.