METHOD OF FORMING LOW RESISTIVITY TaNx/Ta DIFFUSION BARRIERS FOR BACKEND INTERCONNECTS

The present disclosure relates diffusion barrier layers for backend layers for interconnects and their methods of manufacturing. A TaNx/Ta diffusion barrier layer used for backend interconnect is formed at a temperature between about 150-450° C. wherein the Ta film exhibits a body-centered-cubic (BCC) structure and a lower electrical resistivity. Other embodiments are described and claimed.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present disclosure. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.

A Cu interconnect typically uses single or dual damascene process, which etches a series of openings called trenches and vias in the insulating layer between different metal layers. Trenches are depressions or grooves, typically extending parallel to the top surface of the Si chip, that are patterned to connect circuits on the same level of the backend of the process. Vias are holes, typically extending perpendicular to the surface, that are patterned to connect the metal hues from different metal layers. Trenches and vias can be formed using standard photolithography and etch processes commonly known to a person having ordinary skill in the semiconductor field. Subsequently, they are filled with a diffusion barrier layer and a conducting material such as Cu. After Cu fill, chemical mechanical polishing process is used to remove the overfill material above the openings. Refractory metals and their nitrides, such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN), are well known as diffusion barriers due to their chemical and thermal stability. For example, Ta film deposited on a TaN template has been widely used as a barrier layer for Cu metallization. Tantalum exists in two crystalline phases: alpha and beta. The alpha phase has a body-centered cubic (BCC) structure (space group Im3m, lattice constant a=0.33058 nm) and a relatively lower electrical resistivity of 15-60 μΩ-cm. The beta phase has a tetragonal crystal structure (space group P42/mnm, a=1.0194 nm, c=0.5313 nm) and a relatively higher electrical resistivity of 170-210 μΩ-cm. The beta phase is metastable and readily converts to the alpha phase upon heating to a temperature above 500-700° C. Although bulk Ta is almost entirely alpha phase, Ta thin film (<30 nm) used for diffusion barrier usually exists in a beta phase and therefore, has >100× higher electrical resistivity than Cu. Even, when the thin Ta film is annealed at a temperature above 500-700° C., the beta phase will not convert to the alpha phase. Due to a relatively higher resistivity compared with Cu, there is a consistent trend to reduce the thickness of the diffusion barrier layer. However, a minimum thickness of 3-5 nm is probably required in order to provide effective barrier to Cu diffusion. As a result, the ratio of barrier layer/Cu starts to increase as the via/trench size continues to shrink and the high electrical resistivity of the barrier layer becomes a significant obstacle to reduce interconnect resistance.

FIG. 1is a schematic diagram showing a backend interconnect structure100in an IC chip in accordance with one or more embodiments. Substrate101may be a bulk semiconductor wafer, such as silicon, germanium, silicon-germanium, gallium arsenide, or other III-V semiconductor material, or it may have a semiconductor-on-insulator configuration such as silicon-on-insulator, germanium-on-insulator, silicon-germanium-on-insulator, or indium phosphide-on-insulator. Substrate101is shown with a field effect transistor having source102and drain104in the substrate and gate108and gate dielectric106above top surface103. Dielectric layers116,124, and134are used to separate different metal levels (3 in this embodiment) and may comprise one or more of the conventional dielectric materials commonly used in the IC applications, such as oxides, doped oxides, nitrides, organic polymers, fluorosilicate glasses, and organosilicates. The dielectric material may also be a low-k dielectric material with pores or other voids to further reduce the dielectric constant, although the scope of the claimed subject matter is not limited in this respect. In one embodiment, each of the dielectric layers116,124, and134may comprise one or more layers of materials. The thickness of dielectric layers116,124, and134varies and in some example embodiments may be in the range of 50-5,000 nm. Via and trench openings111,113, and115in the dielectric layer116are filled with conducting material110,112, and114, typically tungsten (W). Top surface117is planarized using chemical mechanical polishing. Via and trench openings119,121, and123in the dielectric layer124are filled with conducting materials118,120, and122, such as Cu, Cu alloys, other conducting metals or conductors. A diffusion barrier layer (not shown) may be formed on the bottoms and/or sidewalls of via and trench openings119,121, and123prior to the filing with conducting materials118,120, and122. Top surface125is planarized using chemical mechanical polishing. In case Cu or Cu alloy is used as interconnect metal, etch stop/cap layer126, such as silicon nitride, is deposited over top surface125. Trench and via openings129,131, and133in dielectric layer134are filled with conducting materials128,130, and132, such as Cu, Cu alloys, other conducting metals or conductors. A diffusion barrier layer (not shown) may be formed on the bottoms and/or sidewalls of the via and trench openings129,131, and133prior to the filing with conducting materials128,130, and132, Top surface135is planarized before another metal layer is built above it. Backend interconnect structure100can be used to connect circuits, components, and transistors at the same or different metal levels.

Although Cu has very favorable electrical properties for backend interconnect applications, it also has several drawbacks: (1) Copper is prone to oxidation and corrosion when it comes in contact with some commonly-used processing chemicals. (2) Copper is very mobile and tends to migrate to other regions of the device during subsequent processes of the Si chip. (3) Copper has weak bonding with many dielectric materials which causes delamination and reliability issues. In order to overcome these problems, a diffusion barrier layer and an adhesion layer (or liner) are usually deposited on the bottom and/or sidewalls of the trench and via before Cu fill. A diffusion barrier layer may comprise one or more layers of materials which may also provide adequate adhesion with Cu and serves as an adhesion layer. One such example is TaNx/Ta layer which is widely used in Cu interconnect as diffusion barrier.

FIGS. 2(a)-(e) are schematic diagrams showing processing steps to fabricate a backend interconnect in accordance with one or more embodiments.FIG. 2(a) provides via/trench opening236in interlayer dielectric (ILD)234, which may be formed by photolithography and etch techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment via/trench opening236may have rounded corners. In another embodiment, via/trench opening236may have asymmetrical sidewalls. In yet another embodiment, portion of the bottom of via/trench opening236may extend into ILD224. In general, the via/trench opening236has a width in the approximate range of 0.005 microns (“μm”) to 5 μm, and the depth in the approximate range of 0.005 μm to 10 μm. Etch stop layer226exists between ILD234and ILD224, which may be formed from a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbide, or other dielectric material. ILD234and224may comprise one or more of the conventional dielectric materials commonly used in IC applications, such as oxides (e.g., silicon oxide, carbon doped oxide), nitrides, organic polymers (e.g., perfluorocyclobutane or polytetrafluoroethylene), spin-on low-k dielectrics, fluorosilicate glasses, and organosilicates (e.g., silsesquioxane, siloxane, or organosilicate glass). The ILD material may also be a low-k dielectric material with pores or voids to further reduce the dielectric constant, although the scope of the claimed subject matter is not limited in this respect. In one embodiment, ILD234and224may comprise one or more layers of materials. ILD234and224may be deposited using any suitable deposition technique such as chemical vapor deposition (CVD), sputtering, and spin-on deposition. Thickness of the ILD234and ILD224may be in the range of 50 nm-5 μm.

FIG. 2(b) provides deposition of diffusion barrier layer238on the sidewalls and bottom of via/trench opening236. Diffusion barrier layer238may comprise a conducting material, such as Ta, Ti, Ru, Co, Pt, Ir, Pd, Re, Rh or combinations thereof. It may also comprise a nitride or an oxy-nitride of each of the above element, or combinations thereof. Any suitable technique, such as atomic layer deposition (ALD), CVD, sputtering, physical vapor deposition (PVD), electroplating, and electroless plating may be used to deposit diffusion barrier layer238, usually with a thickness in the range of 1-100 nm. Diffusion barrier layer238may also serve as an adhesion layer and may comprise one or more layers of different materials to achieve the intended purposes. AlthoughFIG. 2(b) shows a continuous, uniform diffusion barrier layer236that covers the entire surface of via/trench opening236, in some cases, it may be discontinuous and/or may not cover every surface of via/trench opening236. In one embodiment, diffusion barrier layer236has a non-uniform thickness.

In one embodiment according to current description, diffusion barrier layer238is a TaNx/Ta layer. A TaNxfilm, where x is in the approximate range of about 0.05-2.0 and preferably in the range of 0.05-0.35, is first deposited onto at least one surface of via/trench opening236by any suitable technique such as sputtering, CVD, ALD, plating, and electroless deposition at room temperature. The thickness of the TaNxfilm is in the range of about 0.5-5.0 nm. A Ta film in the thickness range of about 0.5-30 nm is subsequently deposited onto the TaNxfilm at room temperature. Based on X-ray diffractometry (XRD) pattern (not shown), the Ta film exhibits a beta phase Ta which has a tetragonal crystal structure and a typical electrical resistivity of 170-210 μΩ-cm.

In another embodiment according to current description, the diffusion barrier layer238is a TaNx/Ta layer. A TaNxfilm, where x is in the approximate range of about 0.05-2.0 and preferably in the range of 0.05-0.35, is first deposited onto at least one surface of via/trench opening236by any suitable technique at a temperature between about 150-450° C. The thickness of the TaNxfilm is in the range of about 0.5-5.0 nm. A Ta film in the thickness range of about 0.5-30 nm and preferably in the range of about 1-20 nm is subsequently deposited onto the TaNxfilm by sputter deposition (sputtering) at a temperature between about 150-450° C. with a re-sputter rate between about 1.0-10 and preferably between 1.0-1.35.

Sputter deposition is a process whereby atoms are ejected from a solid target by energetic particles, usually plasma, and re-deposited onto a substrate to form a thin film. It is commonly used in the semiconductor industry to form a metal layer such as Ta. Argon (Ar) plasma is usually used to dislodge Ta atoms from a solid Ta target, which are then deposited onto a substrate. The substrate can be heated to a higher temperature or maintained at room temperature during deposition. Re-sputter is a process that involves re-emission of the deposited material due to bombardment of energetic particles. Re-sputter rate is defined as the thickness of the barrier layer deposited without an AC bias divided by the thickness of the barrier layer deposited with an AC bias. The AC bias is normally between 0.01-100 GHz and preferably at approximately 13.56 MHz. A thin film deposited with an AC bias has a better conformality and step coverage than one without an AC bias. Based on X-ray diffractometry (XRD) pattern (not shown), the deposited Ta film exhibits an alpha phase Ta which has a body-centered cubic (BCC) structure and an electrical resistivity of 15-60 μΩ-cm. This is significantly lower than the electrical resistivity of a typical beta phase Ta film. Other deposition techniques that are known to the semiconductor industry can also be used to produce an alpha phase BCC Ta film. For example, Ta films can be deposited at about 150-450° C. on a TaNxlayer using hallow cathode magnetron (HCM) or electron cyclotron resonance (ECR) deposition technique. The HCM design includes a hollow cathode structure surrounding a planar magnetron cathode while the ECR technique uses ECR to generate plasma. Both techniques can produce high energy plasma and high particle flux and, therefore, a high metal ionization during deposition. A Ta film prepared by either technique at about 150-450° C. exhibits the alpha phase. It shall be noted that ILD layer234,224, and etch stop layer224does not affect the formation of the alpha phase Ta and any suitable material and structure can be used for the ILD layers and the etch stop layer.

In yet another embodiment according to current description, the diffusion barrier layer238is a TaNx/Ta layer. A TaNxfilm, where x is in the approximate range of about 0.05-2.0 and preferably in the range of0.05-0.35, is first deposited onto at least one surface of via/trench opening236by reactive sputtering at a temperature between about 150-450° C.

Reactive sputtering occurs when the deposited film is formed through a chemical reaction between the target material and a gas (N2, in this case) which is introduced to the process chamber during deposition. After a desired film thickness between about 0.5-5.0 nm is achieved, the plasma is turned off and N2gas is pumped out of the process chamber. Without breaking the vacuum, a Ta film in the thickness range of about 0.5-30 nm and preferably in the range of about 1-20 nm is subsequently deposited onto the TaNxfilm by sputtering in the same process chamber. The Ta film is deposited at a temperature between about 150-450° C. with a re-sputter rate between about 1.0-10 and preferably between 1.0-1.35. Based on XRD, the Ta film exhibits an alpha phase, BCC structure with a low resistivity of 15-60 μΩ-cm. The ILD layer234,224, and etch stop layer224does not affect the formation of the alpha phase Ta and any suitable material and structure may be used for the ILD layers and the etch stop layer.

FIG. 2(c) shows a subsequent formation of one or more conducting layers, Cu alloy layer240and Cu seed layer242in this embodiment, on top of diffusion barrier layer238. Copper alloy layer240and Cu seed layer242can be formed using any suitable thin film technique known to one of ordinary skill in the art of semiconductor manufacturing, e.g., sputtering, ALD, CVD, electroplating, electroless plating, and the like. The thickness of Cu alloy layer240and Cu seed layer242is in the range of 1.0-100 nm. Cu alloy layer240and Cu seed layer242may comprise one or more dopants and may be continuous or discontinuous. The discontinuous Cu seed layer allows a thinner seed layer to be deposited and potentially avoids pinching off features in situations in which small features are to be filled with a metal. If a feature becomes pinched off, then an unwanted gap in the metal of the interconnect can form, which may lead to device failure. Cu alloy layer240and Cu seed layer242may have an uniform or non-uniform thickness. In one embodiment, other materials besides Cu may be used for layers240and242, such as ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W). Vanadium (V), Molybdenum (Mo), palladium (Pd), gold (Au), silver (Ag), platinum (Pt), or combinations thereof.FIG. 2(d) shows filling of via/trench opening236with conducting material244, Cu in this embodiment, and subsequent planarization of Cu layer244. Electroplating is typically used to deposit Cu and fill via/trench opening236. An electroplating process comprises the deposition of a metal onto a semiconductor substrate from an electrolytic solution that comprises ions of the metal to be deposited. The electrolyte solution can be referred to as a plating bath or an electroplating bath. The substrate to be plated is immersed in the plating bath with a negative bias placed on the substrate. The positive ions of the metal are attracted to the negatively biased substrate, which are reduced to form a metal layer on the substrate. Copper layer244may also comprise one or more dopants. In one embodiment, other material besides Cu may be used for conducting material244, such as ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), Vanadium (V), Molybdenum (Mo), palladium (Pd), gold (Au), silver (Ag), platinum (Pt), or combinations thereof. Any other suitable thin film technique known to a person having ordinary skill in the field may be used to deposit conducting material244. Such technique includes sputtering, CVD, electroless plating, and the like. Finally, chemical mechanical polishing is used to remove portions of conducting material244, conducting layers242and240, and diffusion barrier layer238from the top surface of ILD234to planarize the top surface for subsequent processing.

AlthoughFIG. 2shows an interconnect structure within one metal level, more than one level of interconnect structures may be fabricated in an IC chip to connect circuits, components, or transistors. To fabricate more than one level of interconnect, similar process and structure as described inFIG. 2(a)-(d) may be repeated. The via/trench opening in each metal level may have the same or different width and depth. In one embodiment, the alpha phase Ta may be used as diffusion barrier for all metal levels. In another embodiment, one or more metal levels comprise alpha phase Ta and one or more metal levels comprise beta phase Ta. For example, in an embodiment where the size of the via/trench at lower metal levels is smaller than that at higher metal levels, one or more of the tower metal levels may have alpha phase Ta and one or more larger upper metal levels may have beta phase Ta at higher metal levels, although the scope of the claimed subject matter is not limited in this respect.

Kelvin tests were used to compare electrical resistance of via chains comprising TaNx/Ta barrier layer deposited at either room temperature or a higher temperature. The results show at least 26% reduction in electrical resistance when TaNx/Ta barrier layer is deposited at a temperature between 150-450° C., indicating the formation of a lower-resistivity BCC Ta phase. With a continued focus on smaller device size and faster device speed, reduction in electrical resistance of diffusion barriers is extremely important. When the critical dimension (CD) of the geometrical features in the semiconductor processes reaches 100 nm or less and the depth of the via is less than 100 nm, use of low-resistivity alpha Ta for barrier layer may be particularly helpful. For an embodiment with a total thickness of the Ta and/or TaNxof about 10 nm and a width of teach of about 100 nm, the alpha phase Ta and/or TaNxwould take up roughly 20% (as there is Ta on both sides of the trench) of the side-to-side distance of the trench. As features get smaller, the alpha phase Ta and/or TaNxtake up more and more of the via, such as 25%, 30% or even more. A via with a horizontal cross section having a layer or layers comprising Ta in alpha phase and taking up at least 20% of the via is thus within the scope of some embodiments.

FIG. 3describes a process for forming a Cu backend interconnect in accordance with one or more embodiments. In step302, an opening is formed in a dielectric layer. A TaNxlayer (x=0.05-2.0) is formed at 150-450° C. in step304on at least one surface of the bottom and sidewalls of the opening. Subsequently in step306, a Ta layer is formed on top of the TaNxlayer at 150-450° C. with a re-sputter rate between 1.0-10. The Ta film exhibits an alpha BCC phase with a lower electrical resistivity. A Cu alloy layer and a Cu seed layer are then formed on top of the Ta layer in step408. Finally in step310, Cu is deposited to fill the opening and the top surface is planarized by chemical mechanical polishing.

FIG. 4illustrates a computing device400in accordance with one or more embodiments of the current disclosure. The computing device400houses a board402. The board402may include a number of components, including but not limited to a processor404and at least one communication chip406. The processor404is physically and electrically coupled to the board402. In some implementations the at least one communication chip406is also physically and electrically coupled to the board402. In further implementations, the communication chip406is part of the processor404.

The processor404of the computing device400includes an integrated circuit die packaged within the processor404. In some implementations of the invention, the integrated circuit die of the processor includes backend interconnects that comprise a TaNx/Ta diffusion barrier layer fabricated according to the structures and processes as described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip406also includes an integrated circuit die packaged within the communication chip406. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes backend interconnects that comprise a TaNx/Ta diffusion barrier layer fabricated according to the structures and processes as described herein.

In further implementations, another component housed within the computing device400may contain an integrated circuit die that includes backend interconnects comprising a TaNx/Ta diffusion barrier layer fabricated according to the structures and processes as described herein. In various implementations, the computing device400may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device460may be any other electronic device that processes data.

The above description of illustrated implementations of the claimed subject matter, including what is described in the Abstract, is not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed. While specific implementations of, and examples for, the claimed subject matter are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. It should also be understood that the subject matter defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the subject matter, but does not necessarily denote that they are present in every embodiment. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Various additional layers and or structures may be included and or described features may be omitted in other embodiments.