Semiconductor device comprising a first gate trench and a second gate trench

A semiconductor device includes a first gate trench and a second gate trench in a first main surface of a semiconductor substrate. A mesa is arranged between the first gate trench and the second gate trench. The mesa separates the first gate trench from the second gate trench. Each of the first and second gate trenches includes first sections extending in a first direction and second sections connecting adjacent ones of the first sections. The second sections of the first gate trench are disposed opposite to the second sections of the second gate trench with respect to a plane perpendicular to the first direction.

BACKGROUND

Power transistors are commonly employed in automotive and industrial electronics as switches. Generally, such transistors require a low on-state resistance (Ron·A), while securing a high voltage blocking capability. For example, a MOS (metal oxide semiconductor) power transistor should be capable—depending upon application requirements—to block drain to source voltages Vdsof some tens to some hundreds or even thousands of volts. MOS power transistors typically conduct a very large current which may be up to some hundreds of Amperes at typically gate-source voltages of about 2 to 20 V.

In trench power devices, components of the transistors such as the gate electrode are typically disposed in trench structures formed in a main surface of a semiconductor substrate. Such trench power devices typically implement vertical transistors in which a current flow mainly takes place from a first side, e.g. a top surface of the semiconductor substrate to a second side, e.g. a bottom surface of the semiconductor substrate. Charge balanced shielded gate trench MOSFETs (metal oxide semiconductor field effect transistors) are, e.g. used for several DC/DC power conversion applications. In particular, power MOSFETs based on this technology allow to reach a high efficiency by optimizing both conduction and switching losses coming from the power MOSFET itself.

Further investigations are being made for improving trench power MOSFETs.

SUMMARY

According to an embodiment, a semiconductor device comprises a first gate trench and a second gate trench in a first main surface of a semiconductor substrate. A mesa is arranged between the first gate trench and the second gate trench, the mesa separating the first gate trench from the second gate trench. Each of the first and second gate trenches comprises first sections extending in a first direction and second sections connecting adjacent ones of the first sections. The second sections of the first gate trench are disposed opposite to the second sections of the second gate trench with respect to a plane perpendicular to the first direction.

According to a further embodiment, a semiconductor device comprises a first gate trench and a second gate trench in a first main surface of a semiconductor substrate. A mesa is arranged between the first gate trench and the second gate trench and separates the first gate trench from the second gate trench. Each of the first and second gate trenches comprises first sections extending in a first direction and second sections connecting adjacent ones of the first sections. The first sections of the first gate trench are disposed between adjacent ones of the first sections of the second gate trench and vice versa.

According to an embodiment, a semiconductor device comprises a first gate trench and a second gate trench in a first main surface of a semiconductor substrate. A mesa is arranged between the first gate trench and the second gate trench and separates the first gate trench from the second gate trench. The mesa comprises first regions extending in first direction and second regions connecting adjacent ones of the first regions. The mesa is implemented as a path.

DETAILED DESCRIPTION

In the following detailed description reference is made to the accompanying drawings, which form a part hereof and in which are illustrated by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as “top”, “bottom”, “front”, “back”, “leading”, “trailing” etc. is used with reference to the orientation of the Figures being described. Since components of embodiments of the invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims.

The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.

The terms “wafer”, “substrate” or “semiconductor substrate” used in the following description may include any semiconductor-based structure that has a semiconductor surface. Wafer and structure are to be understood to include silicon, silicon-on-insulator (SOI), silicon-on sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. The semiconductor need not be silicon-based. The semiconductor could as well be silicon-germanium, germanium, or gallium arsenide. According to other embodiments, silicon carbide (SiC) or gallium nitride (GaN) may form the semiconductor substrate material.

The terms “lateral” and “horizontal” as used in this specification intends to describe an orientation parallel to a first surface of a semiconductor substrate or semiconductor body. This can be for instance the surface of a wafer or a die.

The term “vertical” as used in this specification intends to describe an orientation which is arranged perpendicular to the first surface of the semiconductor substrate or semiconductor body.

As employed in this specification, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together—intervening elements may be provided between the “coupled” or “electrically coupled” elements. The term “electrically connected” intends to describe a low-ohmic electric connection between the elements electrically connected together.

FIG. 1shows a horizontal cross-sectional view of a semiconductor device1000according to an embodiment. The horizontal cross-sectional view taken in a plane parallel to a first main surface of a semiconductor substrate. The semiconductor device1000comprises a first gate trench100and second gate trench200in the first main surface of a semiconductor substrate. A mesa300is arranged between the first gate trench100and the second gate trench200, the mesa300separating the first gate trench300from the second gate trench200. The first gate trench100comprises first sections110extending in a first direction, e.g. the y-direction and second sections120connecting adjacent ones of the first sections110. The second gate trench200comprises first sections210extending in the first direction, e.g. the y-direction, and second sections220connecting adjacent ones of the first sections210. The second sections120of the first gate trench100are disposed opposite to the second sections220of the second gate trench200with respect to a plane115perpendicular to the first direction. For example, the plane115may run in a second direction, e.g. the x-direction and may be perpendicular to first main surface of the semiconductor substrate.

As is specifically illustrated inFIG. 1, the first gate trench100is separated from the second gate trench200, i.e. the first gate trench100is not connected with the second gate trench200. In other words, the first sections110of the first gate trench100are not structurally connected with any of the first sections210of the second gate trench200or the second sections220of the second gate trench200. Further, the second sections120are not structurally connected with any of the first sections210of the second gate trench200or the second sections220of the second gate trench200. The first and the second gate trenches100,200may be identical in shape or at least a part of the first gate trench100and the second gate trench200may be identical to each other. The second gate trench200may be rotated by 180° in a plane parallel to the first main surface of the semiconductor substrate. The first sections110of the first gate trench100may be identical with the first sections210of the second gate trench200. The second sections120of the first gate trench100may be identical with the second sections220of the second gate trench200.

The second sections120of the first trench100connect adjacent ones of the first sections110of the first trench100. The second sections220of the second gate trench200connect adjacent ones of the first sections210of the second gate trench200. The second sections120,220may run in a second direction which is perpendicular to the first direction. The second direction may for example be the x-direction. Further, the second sections may have a curved shape. According to further embodiments, the second sections may comprise a straight or linear portion, e.g. linearly extending in the second direction and may have a curved or slanted connection portion to the first sections110. The first gate trench100and the second gate trench200are separated from each by means of the mesa300.

According to an alternative interpretation, the semiconductor device1000may comprise a first gate trench100and a second gate trench200in a first main surface of semiconductor substrate. A mesa300is arranged between the first gate trench100and the second gate trench200and separates the first gate trench100from the second gate trench200. The first gate trench100comprises first sections110extending in a first direction, e.g. the y-direction and second sections120connecting adjacent ones of the first sections110. The second gate trench200comprises first sections210extending in the first direction and second sections220connecting adjacent ones of the first sections210. The first sections110of the first gate trench100are disposed between adjacent ones of the first sections210of the second gate trench200and vice versa. The first sections110of the first gate trench100may be parallel to the first sections210of the second gate trench200. As has been discussed above, the second gate trench200may be identical to the first gate trench or may have sections which are identical to those of the first gate trench. The second gate trench200may be or rotated by 180° in a plane parallel to the first main surface.

For example, the first gate trench100and the second gate trench200may have a comb-like structure, wherein the first sections110,210correspond to the teeth of the comb whereas the concatenation of second sections120,220corresponds to the shaft of the comb. The first comb implementing the first gate trench100and the second comb implementing the second gate trench200are inserted into each other or assembled in such a manner that the shaft and outer teeth of the first gate trench and of the second gate trench form the outer contour of the arrangement of first gate trench100and second gate trench200.

The arrangement of the first gate trench100and the second gate trench200forms a pattern of interdigitated fingers, wherein the transistor cells of the transistor are disposed between the single fingers of the first gate trench100and the second gate trench200.

The mesa300separates the first gate trench100and the second gate trench200from each other. The mesa300may be regarded as comprising first regions390extending in the first direction and second regions395connecting adjacent first regions390. The mesa300is implemented as a path. In the context of the present specification, the term “path” is to be understood as being different from a loop which means that the path has an initial point which is different from a terminal point. In contrast, a loop has an initial point which may be equal to the terminal point of the loop. The mesa300forms kind of meander in the first main surface of the semiconductor substrate and continuously extends across the cell array. The first regions390may run in the y-direction. The second regions395that connect adjacent ones of the first regions390may run in the direction which is perpendicular to the first direction, e.g. into the x-direction. According to a further embodiment, the second regions395may be curved or slanted or may comprise straight portions and rounded portions. For example, the mesa may have a shape so that a width of the mesa is approximately equal throughout its length.

FIG. 1further shows a gate contact415. The gate contact415is disposed in a peripheral portion of the semiconductor device1000. Generally, the semiconductor device1000comprises a transistor cell array400and a peripheral portion outside the transistor cell array400. The first gate trench100and the second gate trench200are assembled so that the outermost first section of the first and second gate trenches100,200and the concatenation of second sections of the first and second gate trenches100,200forms an outer contour of the transistor cell array400. The gate contact415may be arranged outside the cell array400and outside the contour formed by the combined first gate trench100and second gate trench200. The gate contact415electrically connects the gate electrode to a gate terminal via a gate conductive layer, e.g. a gate metallization layer, as will be explained below.

According to one or more embodiments, the first sections110of the first gate trench100are disposed at a first pitch, and the first sections210of the second gate trench200may be disposed at the first pitch. Further, sections390of the mesa300may be disposed at a second pitch. The sections390of the mesa300extend in the first direction, e.g. the y-direction. The sections of the mesa separate the first sections110of the first trench from the first sections210of the second trench. The second pitch may be equal to half the first pitch.

FIG. 2Ashows schematic plan view of the semiconductor device1000. The semiconductor device1000comprises a first gate trench100and a second gate trench200which may have the same shape and structure as illustrated inFIG. 1. The semiconductor device further comprises a mesa300arranged between the first gate trench100and the second gate trench200. The mesa300has a shape as has been discussed with reference toFIG. 1.FIG. 2Afurther shows gate contact areas410that are disposed in a peripheral area outside the cell array400which is defined by the first gate trench100and the second to trench200. Gate contacts415are disposed in the gate contact area410.FIG. 2Afurther shows schematically gate conductive layer portions510,520which are disposed outside the cell array400. According to an embodiment, the first gate conductive layer portion510and the second gate conductive layer portion520may be connected to a common gate terminal515.

As is further illustrated inFIG. 2A, a field plate contact area420may be disposed at an end portion of the first sections110,210. The end portions of the first sections110of the first gate trench are arranged remote from the second sections120of the first gate trench. Likewise, the end portions of the first sections210of the second gate trench are arranged remote from the second sections220of the second gate trench200. The end portions of the first sections110of the first gate trench100are facing the second sections220of the second gate trench. The end portions of the first sections210of the second gate trench200are facing the second sections120of the first gate trench100. As will be explained in more detail with reference to the following Figures, the field plate contacts425are formed at these end portions.

The mesa portions surrounding the end portions of the first sections110,210are also referred to as “inactive mesa portions”312. In more detail, as will be also explained with reference to the following Figures, source regions are not formed in these inactive mesa portions312. Accordingly, no vertical transistor cell is formed in these inactive mesa portions312. In particular, the inactive mesa portions are adjacent to the second sections120,220. Further, in a general transistor cell array comprising a plurality of vertical transistor cells which will be explained with reference ofFIG. 2B, the outermost first regions390of the mesa300form inactive mesa portions312. In more detail, no source regions are formed in the inactive mesa portions312.

FIG. 2Aschematically shows a boundary of a source implantation mask440. In more detail, while performing a doping process, e.g. an ion implantation process for defining the source regions, only the inner portion of the mask440is uncovered, whereas the area outside the boundary of the mask440is covered. As a result, dopants are only introduced into the first regions390of the mesa300within the boundary of the mask440.

FIG. 2Afurther shows a boundary of a gate dielectric mask430. The portion within the boundary of the gate dielectric mask430is uncovered, whereas the region outside the boundary of the gate dielectric mask430is covered during an etching step. During this etching step, a field dielectric layer is removed from an upper portion of a sidewall of the first and second gate trenches100,200at portions inside the boundary of the gate dielectric mask430, whereas the field dielectric layer remains up to the first main surface of the semiconductor substrate in the area outside the boundary of the gate dielectric mask430. In later processing steps, a gate dielectric layer will be formed in those portions of the first and second gate trenches100,200, from which the field dielectric layer has been removed.

FIG. 2Afurther shows a contour of a source conductive layer530, e.g. a source metallization layer, which is connected to the source regions of the single transistor cells and the field plate contacts425. The source conductive layer530may be arranged over the semiconductor substrate. This will be explained in more detail below.

FIG. 2Bshows a schematic cross-sectional view of two transistor cells3801,3802between IV and IV′, as is also indicated inFIG. 2A. The transistor cells3801,3802are formed in a semiconductor substrate310. For example, the semiconductor substrate310may comprise a base layer305of the first conductivity type. For example, the base layer305may be doped with n-type dopants at a high doping level to form a drain region352of the transistor. The semiconductor substrate310may further comprise an epitaxially or differently formed semiconductor layer306of the first conductivity type. A doped portion307of the second conductivity type may be disposed over the first layer306. A first gate trench100and a second gate trench200are disposed in the first main surface320of the semiconductor substrate310. A mesa300is defined between the first gate trench100and the second gate trench200. A source region351is disposed adjacent to the first main surface320of the semiconductor substrate310. For example, the source region may be of the first conductivity type. The doped portion307of the second conductivity type forms the body portion of the transistor cells3801,3802. The first layer306of the first conductivity type forms the drift zone354of the transistor cells3801,3802. The base layer305may form the drain region of the transistor. A gate electrode360may be disposed in the first and the second gate trench100,200adjacent to the body region353. The gate electrode360may be insulated from the body region353by means of a gate dielectric layer361. A field plate370may be disposed in a lower portion of the first gate trench100and of the second gate trench200. The field plate370may be insulated from the gate electrode360. Further, the field plate370may be insulated from the adjacent semiconductor material354by means of the field dielectric layer371. The source region351is electrically connected to the source conductive layer530. Further, the body region353is connected to the source conductive layer530via a body contact portion365. Due to the presence of this body contact portion365, a bipolar parasitic transistor may be deteriorated or suppressed which could otherwise be formed in this portion. Generally, a power transistor comprises a plurality of single transistor cells3801, . . .380nwhich are connected in parallel. For example, the single transistor cells3801, . . .380nmay comprise common components such as a common drain region.

When the transistor is switched on, e.g. by applying a corresponding voltage to the gate electrode360, a conductive inversion layer (conductive channel)355is formed at the boundary between the body region353and the gate dielectric layer361. Accordingly, the transistor is in a conductive state from the source region351to the drain region352via the drift zone354. In case of switching-off, charges within the drift zone354are further depleted due to the presence of the field plate370. Accordingly, a blocking of the current flow may be achieved. As has been explained above, due to the special structure of the first gate trench100and the second gate trench200, the mesa is implemented as a path continuously extending along the cell array400. As a result, the volume of the drift zone354adjacent to the field plate370does not substantially vary. As a consequence, overcompensation of the device may be avoided and the device characteristics may be improved.

Returning to the plan view ofFIG. 2A, the semiconductor device1000comprises a plurality of vertical transistor cells3801, . . . ,380nin the manner as has been explained with reference toFIG. 2B. The source regions351of the vertical transistor cells are arranged at the first main surface320, and the drain region352of the transistor is arranged at a second main surface330opposite the first main surface320. The source regions351are arranged adjacent to the first sections110,210of the first and second gate trenches100,200. The source regions351are absent from the second sections120,220. Accordingly, active mesa portions may be formed only at first sections110,210of the first and second gate trenches100,200. Active mesa portions may be formed in the first regions390of the mesa.

FIGS. 2C and 2Dillustrate embodiments according to which field plate contacts425may be arranged outside the transistor cell array400.

According to the embodiment ofFIG. 2C, gate contact trenches140may extend outside the transistor cell array400. The gate contact trenches140may be connected with the first gate trench100and the second gate trench200. Gate contacts415may be arranged in the gate contact trenches140. The gate contacts415may electrically connect the gate electrode360within the gate trench100,200with a gate terminal, e.g. via a gate conductive layer510. Further, a field plate contact425may be arranged in the gate contact trenches140. The field plate contact425may electrically connect the field plate370within the gate trench100,200with a source terminal, e.g. via a source conductive layer530. The mesa300may have a constant width which does not vary. The gate contacts415and the field plate contacts425may have a width that is larger than a width of the mesa300.

According to the embodiment ofFIG. 2D, gate contact trenches140may extend outside the transistor cell array400. The gate contact trenches140may be connected with the first gate trench100and the second gate trench200. Gate contacts415may be arranged in the gate contact trenches140. The gate contacts415may electrically connect the gate electrode360within the gate trench100,200with a gate terminal, e.g. via a gate conductive layer510. Further, a field plate contact425may be arranged in a field plate contact trench145that is connected with the first gate trench100and the second gate trench200. The field plate contact trench145may be disconnected from the gate contact trench140. The field plate contact425may electrically connect the field plate370within the gate trench100,200with a source terminal, e.g. via a source conductive layer530. The mesa300may have a constant width which does not vary. The gate contacts415and the field plate contacts425may have a width that is larger than a width of the mesa300.FIG. 2Dshows a further transistor cell array402that is shifted along the y-direction with respect to the transistor cell array400. The further transistor cell array402and the transistor cell array400may share common field plate contacts425.

FIG. 3shows a horizontal cross-sectional view of a semiconductor device according to an embodiment. The horizontal cross-sectional view is taken in a region of the cell array400, the field plate contact area420and the gate contact area410. As is shown inFIG. 3, the cell array400comprises a plurality of alternating first sections110of the first gate trench100and first sections210of the second gate trench200. The mesa comprises an inactive mesa portion312adjacent to the outermost first section110of the first gate trench100. Further, an inactive mesa portion312is disposed adjacent to the outermost first section210of the second gate trench200. The specific structure of the inactive mesa312will be explained below in more detail. Reference numeral377denotes a mask which is used for defining a gate electrode within the first gate trench100and the second gate trench200. In more detail, when forming the transistor, first, a dielectric layer lining the sidewalls of the first and second gate trenches100,200is formed, followed by forming a conductive filling. For forming the gate electrode, the conductive filling is removed from an upper portion of the first and second gate trenches100,200. No gate electrode is formed in a portion masked by the mask377. These portions will form the inactive mesa portions312.

Gate contact trenches140are arranged in contact with the first gate trench100. The gate contacts415are formed in the gate contact trenches140. As becomes apparent fromFIG. 3, a pitch of the gate contact trenches140is larger than a pitch of the first sections110,210of the first gate trench100or the second gate trench200. As a result, gate contacts to the gate contact trenches may be formed more easily. First regions390of the mesa300are disposed between adjacent ones of the first sections110of the first gate trench100and the first sections210of the second gate trench200. As can further be taken fromFIG. 3, the end portions of the first sections may have a larger width than the remaining part of the first sections110,210, the width being measured perpendicularly with respect to the first direction. According to further embodiments, the width of the end portions of the first sections need not be larger than a width of the remaining part of the first sections110,210. Reference numeral376denotes source contacts which will be described in more detail below.

FIG. 4Ashows a cross-sectional view of the semiconductor device shown inFIGS. 1 and 3. The cross-sectional view ofFIG. 4Ais taken in the cell array between I and I′, as can also be taken fromFIG. 3. The cross-sectional view intersects a plurality of transistor cells3801, . . .380n. The transistor cells may have a construction as has been explained above with reference toFIG. 2B. Accordingly, the transistor cell array comprises a plurality of first sections110of the first gate trench100and of first sections210of the second gate trench200. The first sections110of the first gate trench100and the first sections210of the second gate trench200are alternatingly disposed. An inactive trench382is disposed at a boundary of the array of first sections110,210. The inactive trench382is filled with a conductive material383. The conductive material is insulated from adjacent semiconductor material by means of the field dielectric layer381. As has been explained with reference toFIG. 2A, due to the shape of the gate dielectric mask430, the field dielectric layer381is not removed from the inactive trench382. The semiconductor portion adjacent to the inactive trench382forms the inactive mesa portion312in which no source region is formed. A source conductive layer530is disposed over the transistor cell array400. The source conductive layer530is electrically connected to the source regions351of the single transistor cells3801, . . . ,380nby means of source contacts376. An insulating layer372is disposed between the semiconductor substrate and the source conductive layer530. The first sections110,210are disposed at a distance d1.

FIG. 4Bshows a cross-sectional view of the semiconductor device in the field plate contact area420. The cross-sectional view ofFIG. 4Bis taken between II and II′, as is also illustrated inFIG. 3. The semiconductor substrate310comprises the base layer305and the first layer306of the first conductivity type. A doped portion307is disposed adjacent to the first main surface320of the semiconductor substrate310. No source regions351are disposed adjacent to the end portion of the first sections110,210of the first and second gate trenches100,200, respectively. Accordingly, an inactive mesa portion312is disposed between the first sections110of the first gate trench and the first sections210of the second gate trench. In the field plate contact area420, the first sections210of the second gate trench200are formed in such a manner that the field plate370is disposed adjacent to the first main surface320of the semiconductor substrate. Field plate contacts425are arranged so as to electrically connect the field plates370in the second gate trench200with the source conductive layer530. Moreover, the conductive material383of the inactive trench382at the edge of the array is electrically connected to the source conductive layer530.

FIG. 4Cshows a cross-sectional view of the gate contact area410. The cross-sectional view ofFIG. 4Cis taken between III and III′, as is also illustrated inFIG. 3.FIG. 4Cshows a plurality of gate contact trenches140that are disposed at a distance d2. The distance d2may be larger than the distance d1between the first sections110of the first gate trench100and the first sections210of the second gate trench200. The field plate370and the gate electrode360may be disposed in the gate contact trenches140. The field plate370and the gate electrode360are insulated by means of a field dielectric layer371from the adjacent semiconductor material. The gate electrode360of each of the gate contact trenches140is electrically connected to the gate conductive layer510,520by means of a gate contact415. An insulating layer372is disposed between the semiconductor substrate310and the gate conductive layer510,520. The semiconductor substrate may, e.g. comprise a base layer305of the first conductivity type and a first layer306of the first conductivity type.

FIG. 5shows a schematic view of an electric device1according to an embodiment. The electric device comprises the semiconductor device1000which has been explained above. Among others, the electric device1may be a power MOSFET, a DC/DC converter or a power supply.

As has been explained above, due to the special layout of the semiconductor device comprising a first gate trench and a second gate trench and a mesa between the first gate trench and the second gate trench in the manner as has been discussed above, a termination region at the end of the first region of the mesa may be avoided since the mesa is implemented as a path so as to separate the first gate trench and the second gate trench. As a result, overcompensation in the termination region which might occur when the drift zone is depleted from three different directions may be avoided. At the same time, contacts to the gate electrode may be accomplished in an easy manner. In particular, the gate contacts may be disposed outside the transistor cell array400. As a result, the contact area of the gate contacts may be increased without contacting an adjacent mesa. As a result, the feature sizes of the device, in particular, the pitch between the gate trenches may be further reduced without increasing problems of forming gate contacts. Further, due to the special structure of the end portion of the first sections, the field plate contacts may be widened so that contacts may be manufactured in a more simplified manner.

While embodiments of the invention have been described above, it is obvious that further embodiments may be implemented. For example, further embodiments may comprise any subcombination of features recited in the claims or any subcombination of elements described in the examples given above. Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.