METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A manufacturing method includes an implantation of impurities and laser irradiation. In the implantation, impurities are implanted to first and second areas so as to obtain a relationship that a total amount of the first impurities is larger than a total amount of the second impurities in a first depth range and a total amount of the second impurities is larger than a total amount of the first impurities in a second depth range (deeper range). In the irradiation, the first and second areas are irradiated with laser so that an energy density of the laser is larger on the second area than on the first area. A first conductivity type region is formed on the first area so as to be exposed on the surface, and a second conductivity type region is formed on the second area so as to be exposed on the surface.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Japanese Patent Application No. 2015-179534 filed on Sep. 11, 2015, the entire contents of which are hereby incorporated by reference into the present application.

TECHNICAL FIELD

The art disclosed herein relates to a method of manufacturing a semiconductor device.

DESCRIPTION OF RELATED ART

Japanese Patent Application Publication No. 2013-197122 discloses a semiconductor device that includes an Insulated Gate Biploar Transistor (IGBT) and a diode in a single semiconductor substrate (also known as a Reverse Conducting (RC)-IGBT). In this RC-IGBT, an n-type cathode region and a p-type collector region (which is referred to as a drain region in Japanese Patent Application Publication No. 2013-197122) are disposed so as to be exposed on a lower surface of a semiconductor substrate. In a step of manufacturing this semiconductor device, a first resist mask is formed on the lower surface of the semiconductor substrate. The first resist mask covers an area where the cathode region is to be formed. In the first resist mask, an opening is provided in an area where the collector region is to be formed. Next, p-type impurities are implanted to the semiconductor substrate via the first resist mask, consequently, the p-type collector region is formed. Subsequently, the first resist mask is removed and a second resist mask is newly formed. The second resist mask covers the collector region. In the second resist mask, an opening is provided in the area where the cathode region is to be formed. Subsequently, n-type impurities are implanted to the semiconductor substrate via the second resist mask, and consequently the n-type cathode region is formed.

BRIEF SUMMARY

As mentioned above, in the art in Japanese Patent Application Publication No. 2013-197122, by implanting impurities to the semiconductor substrate via the first and second resist masks, the n-type cathode region and the p-type collector region are formed separately. In this method, to form each of the resist masks, steps of forming a resist film, exposing the resist film to light, etching (patterning) the resist film, cleaning the semiconductor substrate, and the like are required. Moreover, to remove the used resist masks, steps of etching the resist masks, cleaning the semiconductor substrate, and the like are required. As such, if the resist masks are used to delimit an area to implant n-type impurities and an area to implant p-type impurities, a large number of steps are required, which makes it difficult to efficiently manufacture a semiconductor device. Notably, this problem occurs not only in the steps of manufacturing an RC-IGBT, but also commonly in cases of forming an n-type region and a p-type region both exposed on a surface of a semiconductor substrate. Accordingly, the present disclosure provides one or more embodiments by which an n-type region and a p-type region both exposed on a surface of a semiconductor substrate can be easily formed.

A method of manufacturing a semiconductor device disclosed herein comprises an implantation of impurities and laser irradiation. In the implantation, at least one of first impurities of a first conductivity type and second impurities of a second conductivity type is implanted into a processing area in a surface of a semiconductor substrate. The processing area includes a first area in the surface and a second area in the surface. The implantation is performed so as to obtain, in an impurity distribution along a depth direction of the semiconductor substrate, a relationship that a total amount of the first impurities is larger than a total amount of the second impurities in a first depth range between the surface and a first position and a total amount of the second impurities is larger than a total amount of the first impurities in a second depth range between the surface and a second position. The first position is located at a first depth from the surface, the second position is located at a second depth from the surface, and the second depth is deeper than the first depth. In the laser irradiation, the surface is irradiated with a laser so that an energy density of the laser on the second area is larger than an energy density of the laser on the first area. A first conductivity type region in which the first impurities exist in higher density than the second impurities is formed in the first depth range on the first area so as to be exposed on the surface. A second conductivity type region in which the second impurities exist in higher density than the first impurities is formed in the second depth range on the second area so as to be exposed on the surface.

Notably, a total amount of the impurities in the view of the impurity density distribution in the depth direction corresponds to a value obtained by integrating the impurity density in the depth direction. Moreover, the energy density means a value obtained by integrating, by time, an intensity of the laser with which the surface of the semiconductor substrate is irradiated with the laser. For example, in a case of laser irradiation having an irradiation intensity of A1 (W/cm2) to an area for t1 seconds, it is meant that the laser irradiation onto the irradiated area has an energy density of A1t1 (J/cm2).

In this manufacturing method, the first and second areas of the surface of the semiconductor substrate are irradiated with a laser during the laser irradiation. The first area is irradiated with the laser at a low energy density, and hence a shallow portion in a proximity of the surface of the semiconductor substrate (i.e., the semiconductor region in the first depth range) is heated. On the other hand, the second area is irradiated with the laser at a high energy density, and hence the semiconductor region ranging from the surface of the semiconductor substrate to a deep portion thereof is heated. In other words, on the second area, the semiconductor region in a wide depth range ranging from the shallow portion to the deep portion of the semiconductor substrate (i.e., the semiconductor region in the second depth range (which may hereinafter be referred to as a wide semiconductor region in the depth direction)) is heated. The impurities are diffused in the heated semiconductor regions (the semiconductor region in the shallow portion on the first area, and the wide semiconductor region in the depth direction on the second area). Due to the diffusion of the impurities, the impurity density distribution in each of the heated semiconductor regions comes to be more uniformized, compared with the impurity density distribution prior to the heating.

Prior to the laser irradiation, the total amount of the first impurities is larger than the total amount of the second impurities in the semiconductor region in the shallow portion (the first depth range). Therefore, when the impurities are diffused in the semiconductor region in the shallow portion in the laser irradiation, the first impurity density becomes higher than the second impurity density in a substantial entirety of the semiconductor region in the shallow portion. Accordingly, on the first area, the first conductivity type region is formed in the first depth range so as to be exposed on the surface of the semiconductor substrate.

On the other hand, prior to the laser irradiation, the total amount of the second impurities is larger than the total amount of the first impurities in the wide semiconductor region in the depth direction (the semiconductor region in the second depth range). Therefore, when the impurities are diffused in the wide semiconductor region in the depth direction in the laser irradiation, a large amount of the second impurities move from the deep portion to the shallow portion. Consequently, the second impurity density becomes higher than the first impurity density in a substantial entirety of the wide semiconductor region in the depth direction. Accordingly, on the second area, the second conductivity type region is formed in the second depth range so as to be exposed on the surface of the semiconductor substrate.

As described above, according to this method, only by implanting impurities so that predetermined density distribution in the depth direction can be obtained, and then by performing laser irradiation so that the energy density changes depending on positions, it is possible to form the first conductivity type region and the second conductivity type region so as to be exposed on the surface of the semiconductor substrate. Therefore, there is no need to form resist masks for delimiting areas where impurities are to be implanted. Moreover, it is easy to irradiate the laser to different areas at different energy densities. Therefore, according to this method, the semiconductor device can be manufactured efficiently.

DETAILED DESCRIPTION

A semiconductor device10in an embodiment shown inFIG. 1comprises a semiconductor substrate12, an upper electrode14, and a lower electrode16. The semiconductor substrate12is a substrate made of silicon. The upper electrode14is provided on an upper surface12aof the semiconductor substrate12. The lower electrode16is provided on a lower surface12bof the semiconductor substrate12.

The semiconductor substrate12comprises a plurality of IGBT regions20comprising vertical IGBT therein, and a plurality of diode regions40comprising vertical diode therein. The IGBT regions20and the diode regions40are provided so as to be arranged alternately and repeatedly in one direction parallel to the upper surface12aof the semiconductor substrate12. The upper electrode14serves as both of an emitter electrode of the IGBT and an anode electrode of the diode. The lower electrode16serves as both of a collector electrode of the IGBT and a cathode electrode of the diode.

Emitter regions22, a body region24, a drift region26, a buffer region28, and a collector region30are provided in the semiconductor substrate12in each of the IGBT regions20.

The emitter regions22are an n-type region and are disposed so as to be exposed on the upper surface12aof the semiconductor substrate12. The emitter regions22are in ohmic contact with the upper electrode14.

Each body region24is a p-type region and is in contact with the emitter regions22. The body region24is disposed so as to be exposed on the upper surface12aof the semiconductor substrate12. The body region24extends from lateral sides of the emitter regions22to undersides of the emitter regions22. The body region24has body contact regions24aand a low density body region24b. The body contact regions24ahave a high p-type impurity density. The body contact regions24aare disposed so as to be exposed on the upper surface12aof the semiconductor substrate12and in ohmic contact with the upper electrode14. The low density body region24bhas a lower p-type impurity density than the body contact regions24a. The low density body region24bis disposed on the undersides of the emitter regions22and undersides of the body contact regions24a.

The drift region26is an n-type region and in contact with the body regions24. The drift region26is disposed on an underside of the body regions24. The drift region26is separated from the emitter regions22by the body regions24.

The buffer regions28are an n-type region and in contact with the drift region26. The buffer regions28are disposed on an underside of the drift region26. An n-type impurity density in the buffer regions28is higher than an n-type impurity density in the drift region26.

The collector regions30are a p-type region and each of them is in contact with the corresponding buffer region28. The collector region30is disposed on an underside of the buffer region28. The collector regions30are disposed so as to be exposed on the lower surface12bof the semiconductor substrate12. The collector regions30are in ohmic contact with the lower electrode16. The collector regions30are separated from the body regions24by the drift region26and the buffer regions28.

A plurality of trenches is provided in the upper surface12aof the semiconductor substrate12in each of the IGBT regions20. Each of the trenches is disposed at a position adjacent to the corresponding emitter region22. Each of the trenches penetrates the body region24and reaches the drift region26.

An inner surface of each of the trenches in the IGBT regions20is covered with a gate insulating film. Moreover, a gate electrode34is disposed in each of the trenches. Each gate electrode34is insulated from the semiconductor substrate12by the corresponding gate insulating film. Each gate electrode34faces the corresponding emitter region22, the corresponding low density body region24b, and the drift region26via the gate insulating film. An interlayer insulating film is disposed on a top of each gate electrode34. Each gate electrode34is insulated from the upper electrode14by the interlayer insulating film.

An anode region42, the drift region26, and a cathode region48are disposed in the semiconductor substrate12in each of the diode regions40.

Each anode region42is disposed so as to be exposed on the upper surface12aof the semiconductor substrate12. The anode region42comprises anode contact regions42aand a low density anode region42b. The anode contact regions42ahave a high p-type impurity density. The anode contact regions42aare disposed so as to be exposed on the upper surface12aof the semiconductor substrate12, and in ohmic contact with the upper electrode14. The low density anode region42bhas a lower p-type impurity density than the anode contact regions42a. The low density anode region42bis disposed on lateral sides and undersides of the anode contact regions42a.

In each of the diode regions40, the drift region26is disposed on undersides of the anode regions42. The drift region26is in contact with the anode regions42.

The cathode regions48are an n-type region and in contact with the drift region26. The cathode regions48are disposed on the underside of the drift region26. An n-type impurity density in the cathode regions48is higher than the n-type impurity density in the drift region26. The cathode regions48are disposed so as to be exposed on the lower surface12bof the semiconductor substrate12. The cathode regions48are in ohmic contact with the lower electrode16.

A plurality of trenches is provided in the upper surface12aof the semiconductor substrate12in each of the diode regions40. Each of the trenches penetrates the corresponding anode region42and reaches the drift region26.

An inner surface of each of the trenches in the diode regions40is covered with an insulating film. Moreover, a control electrode44is disposed in each of the trenches. Each control electrode44is insulated from the semiconductor substrate12by the corresponding insulating film. Each control electrode44faces the corresponding anode region42and the drift region26via the insulating film. An interlayer insulating film is disposed on a top of the control electrode44. Each control electrode44is insulated from the upper electrode14by the corresponding interlayer insulating film.

As mentioned above, the p-type collector regions30are disposed so as to be exposed on the lower surface12bof the semiconductor substrate12in the IGBT regions20, and the n-type cathode regions48are disposed so as to be exposed on the lower surface12bof the semiconductor substrate12in the diode regions40. Accordingly, the p-type collector regions30and the n-type cathode regions48are exposed on the lower surface12bof the semiconductor substrate12. As seen along one direction parallel to the lower surface12bof the semiconductor substrate12, exposed areas of the collector regions30and exposed areas of the cathode regions48are disposed alternately and repeatedly.

FIG. 2shows impurity density distributions at a position on a line II-II inFIG. 1(i.e., impurity density distributions in the collector region30and the buffer region28along a depth direction). A vertical axis inFIG. 2represents a depth from the lower surface12bof the semiconductor substrate12. An origin inFIG. 2(i.e., the depth being zero) represents the position of the lower surface12b.

In a depth range between the lower surface12band a position53of a depth D3, the p-type impurity density is higher than the n-type impurity density. In other words, in the depth range between the lower surface12band the position53, the p-type collector region30is disposed. Moreover, in a portion of the collector region30except for its deepest portion (i.e., a depth range between a position52of a depth D2(a depth shallower than the depth D3) and the lower surface12b), the p-type impurity density is distributed at an approximately constant level, and the n-type impurity density is distributed at an approximately constant level that is lower than that of the p-type impurity density. In the deepest portion in the collector region30(i.e., a depth range between the position52and the position53), the p-type impurity density drastically decreases as the depth becomes deeper, while the n-type impurity density drastically increases as the depth becomes deeper. At the position53, the p-type impurity density and the n-type impurity density coincide with each other.

On a side deeper than the position53, the p-type impurity density is further decreases. Accordingly, on the side deeper than the position53, the n-type impurity density is higher than the p-type impurity density. In a depth range between the position53of the depth D3and a position58of a depth D8(a depth deeper than the depth D3), the n-type impurity density is relatively high. On a side deeper than the position58, the n-type impurity density is distributed at an approximately constant level that is extremely low. The semiconductor region on the side deeper than the position58is the drift region26that has a low n-type impurity density. The semiconductor region between the position53and the position58is the buffer region28that has a higher n-type impurity density than the drift region26. A peak of the n-type impurity density is at a position55of a depth D5in the buffer region28. In the buffer region28, the n-type impurity density is normally distributed, with the peak at the position55being centered.

FIG. 3shows impurity density distributions at a position on a line inFIG. 1(i.e., impurity density distributions in the cathode region48along the depth direction). Depths D4and D8inFIG. 3approximately coincide with a depth D4and the depth D8inFIG. 2, respectively.

In the diode region40, the n-type impurity density is higher than the p-type impurity density in an approximately entire region in the proximity of the lower surface12b. In a depth range between the lower surface12band the position58, the n-type impurity density is relatively high. On the side deeper than the position58, the n-type impurity density is distributed at an approximately constant level that is extremely low. The semiconductor region on the side deeper than the position58is the drift region26that has a low n-type impurity density. The semiconductor region between the lower surface12band the position58is the cathode region48that has a higher n-type impurity density than the drift region26. Moreover, in a portion in the cathode region48except for its deepest portion (i.e., a depth range between the lower surface12band a position56of a depth D6(a depth shallower than the depth D8), the n-type impurity density is distributed at an approximately constant level, and the p-type impurity density is distributed at an approximately constant level that is lower than that of the n-type impurity density. In the deepest portion in the cathode region48(i.e., a depth range between the position56and the position58), the n-type impurity density drastically decreases as the depth becomes deeper.

Next, an operation of the IGBT will be described. When the IGBT is to be turned on, a potential of the gate electrodes34is raised to a threshold value or higher. A channel is thereby formed in each body region24in the proximity of the respective gate insulating films. In this state, when a potential of the lower electrode16is raised to a potential higher than that of the upper electrode14, a current flows from the lower electrode16to the upper electrode14through the IGBT regions20. When the potential of the gate electrodes34is lowered to a potential smaller than the threshold value, the channel disappears and the IGBT is turned off. In this state, a depletion layer extends downward from a pn junction at an interface between the p-type regions on the upper surface side (i.e., the body regions24and the anode regions42) and the drift region26. When the depletion layer reaches the buffer regions28and the cathode regions48each having a high n-type impurity density, the extension of the depletion layer stops. The depletion layer is thereby prevented from reaching the lower surface12b(i.e., a so-called punch-through is prevented).

Next, an operation of the diode will be described. When the potential of the upper electrode14is raised to a potential higher than that of the lower electrode16, a forward voltage is applied to the pn junction at each interface between the anode regions42and the drift region26. The diode is thereby turned on and a current flows from the upper electrode14to the lower electrode16through the diode regions40. Moreover, a forward voltage is also applied to the pn junction at each interface between the body regions24and the drift region26in the IGBT regions20. Accordingly, a current also flows from the upper electrode14to the lower electrode16through paths between these pn junctions and the cathode regions48. Afterwards, when the potential of the upper electrode14is lowered to a potential lower than that of the lower electrode16, the diode performs a reverse recovery operation. In the reverse recovery operation, holes that exist in the drift region26are discharged into the upper electrode14via the anode regions42and the body regions24, and electrons that exist in the drift region26are discharged into the lower electrode16via the cathode regions48. Accordingly, a high reverse current (a so-called reverse recovery current) instantaneously flows through the semiconductor device10.

When the n-type cathode regions48as well as the p-type collector regions30are disposed so as to be exposed on the lower surface12bas in the semiconductor device10, an amount of electrons that flow from the lower electrode16into the drift region26while the diode is on becomes less. Therefore, an amount of electrons discharged from the drift region26into the lower electrode16during the reverse recovery operation also becomes less. According to this structure, a reverse recovery current in the diode can be suppressed. Accordingly, a loss during the reverse recovery operation in the diode can be suppressed.

Next, a method of manufacturing the semiconductor device10will be described. Initially, as shown inFIG. 4, a structure on the upper surface12aside of the semiconductor device10is formed by a conventionally-known method. At this stage, the drift region26is exposed on an entirety of the lower surface12b.

Next, an n-type impurity implantation step is performed. Here, as shown inFIG. 4, n-type impurities are implanted to the entirety of the lower surface12bof the semiconductor substrate12. Here, as shown inFIG. 6, the n-type impurities are implanted so that a peak of the n-type impurity density is at the position55of the depth D5. Performing the n-type impurity implantation step causes the n-type impurity density to be normally distributed in a depth range between the lower surface12band a position57(a position of a depth D7), with the position55being centered in its distribution.

Next, a p-type impurity implantation step is performed. Here, as shown inFIG. 5, p-type impurities are implanted to the entirety of the lower surface12bof the semiconductor substrate12. Here, as shown inFIG. 6, the p-type impurities are implanted so that a peak of the p-type impurity density is at a position51of a depth D1(a depth shallower than the depth D5). Performing the p-type impurity implantation step causes the p-type impurity density to be normally distributed, with the position51being centered in its distribution. Notably, a dose (atoms/cm2) of the p-type impurities in the p-type impurity implantation step is smaller than a dose of the n-type impurities in the n-type impurity implantation step. Here, the dose means a total amount of impurities implanted to a unit area of the lower surface12b. Moreover, the p-type impurity implantation step may be performed prior to the n-type impurity implantation step.

As mentioned above, after the n-type impurity implantation step and the p-type impurity implantation step are performed, the impurity density distributions shown inFIG. 6are obtained. Notably, the depths D2, D3, D4, D5, and D6inFIG. 6approximately coincide with the depths D2, D3, D4, D5, and D6inFIGS. 2 and 3, respectively. Moreover, at this stage, both in the IGBT regions20(i.e., at the position on the line II-II inFIG. 1) and in the diode regions40(i.e., at the position on the line inFIG. 1), the impurity densities are distributed as shown inFIG. 6. As mentioned above, the peak of the p-type impurities is at the position51of the depth D1, and the peak of the n-type impurities is at the position55of the depth D5which is deeper than the depth D1. At the position53of the depth D3which is located between the depth D1and the depth D5, the p-type impurity density and the n-type impurity density approximately coincide with each other. In a depth range in the proximity of the lower surface12bwhich includes the position51having the peak of the p-type impurity density (i.e., the depth range between the lower surface12band the position53), the p-type impurity density is higher than the n-type impurity density. In a depth range that includes the position55having the peak of the n-type impurity density, (i.e., a range deeper than the position53), the n-type impurity density is higher than the p-type impurity density.

Moreover, as mentioned above, the dose of the p-type impurities is smaller than the dose of the n-type impurities. A value obtained by integrating the p-type impurity density inFIG. 6in an entire region in the depth direction corresponds to the dose of the p-type impurities, and a value obtained by integrating the n-type impurity density inFIG. 6in the depth range between the lower surface12band the position57in the depth direction corresponds to the dose of the n-type impurities. Accordingly, inFIG. 6, the area of the graph of the p-type impurity density is smaller than the area of the graph of the n-type impurity density. Moreover, a position54of the depth D4inFIG. 6indicates a position at which the total amount of the p-type impurities that exist in a depth range between the lower surface12band the position54is equal to the total amount of the n-type impurities that exist in the depth range between the lower surface12band the position54. In other words, the area (square measure) of the graph of the p-type impurity density in the depth range between the lower surface12band the position54is equal to the area (square measure) of the graph of the n-type impurity density in the depth range between the lower surface12band the position54. Notably, although the depth D4is shallower than the depth D5in the present embodiment, the depth D4may be deeper than the depth D5.

After the p-type impurities and the n-type impurities are implanted to obtain the distributions inFIG. 6, a laser irradiation step is performed. Here, laser is irradiated onto the lower surface12bof the semiconductor substrate12to heat the semiconductor substrate12. In the laser irradiation step, as shown inFIG. 7, a laser that has a rectangular focus90is used. As shown by arrows inFIG. 7, the focus90, while being reciprocated along a y direction (one direction parallel to the lower surface12b) on the lower surface12bof the semiconductor substrate12, is moved in an x direction (a direction parallel to the lower surface12band orthogonal to the y direction). The entirety of the lower surface12bis thereby irradiated with the laser, and the semiconductor region in the proximity of the lower surface12bis heated. When the focus90is reciprocated in the y direction, an area irradiated on a forward path and an area irradiated on a return path are partially overlapped. An energy density of the laser becomes high in the portion where areas irradiated on the forward path and the return path are overlapped, whereas the energy density of the laser becomes low in a portion where the areas irradiated on the forward path and the return path are not overlapped. Here, an irradiation path of the laser is set so that the energy density becomes low in the IGBT regions20and high in the diode regions40.

In the IGBT regions20, the energy density of the laser is low, and hence the semiconductor region in a shallow portion in the proximity of the lower surface12bis heated. More specifically, a range up to the depth D2shown inFIG. 6(the depth shallower than the depths D3and D4) (i.e., the depth range between the lower surface12band the position52) is heated to a temperature equal to or higher than a melting point of silicon. Therefore, the semiconductor region in the depth range between the lower surface12band the position52is melted, and then that semiconductor region is solidified. When the semiconductor region is melted, the impurities are dispersed approximately uniformly in the melted semiconductor region. Accordingly, as shown inFIG. 2, after the heating, each of the p-type impurity density and the n-type impurity density becomes approximately constant in the depth range between the lower surface12band the position52. Moreover, as shown inFIG. 6, prior to the heating, the total amount of the p-type impurities is larger than the total amount of the n-type impurities in the depth range between the lower surface12band the position52. Accordingly, as shown inFIG. 2, after the heating, the p-type impurity density becomes higher than the n-type impurity density in an entirety of the depth range between the lower surface12band the position52. The impurities are activated in the melted semiconductor regions. Accordingly, an activated p-type region is formed in the depth range between the lower surface12band the position52. Moreover, the semiconductor region which is located deeper than the position52and is not melted is also heated by the laser. Therefore, in a range deeper than the position52, the impurities are diffused in solid silicon. In a depth range adjacent to the melted range (i.e., a depth range between the position52and the position53), the p-type impurity density is maintained higher than the n-type impurity density even after the heating. Moreover, the impurities are activated by the heating even in this depth range, and a p-type region is formed. Accordingly, in each IGBT region20, the p-type collector region30exposed on the lower surface12bis formed in the depth range between the lower surface12band the position53. In the range deeper than the position53, the n-type impurity density is maintained higher than the p-type impurity density even after the heating. It should be noted that the distribution range of the n-type impurities becomes somewhat wider due to the diffusion. Therefore, a position of an end on a deeper side of the distribution range of the n-type impurities shifts from the position57of the depth D7(seeFIG. 6) to the position58of the depth D8(seeFIG. 2), which is deeper than the depth D7. Moreover, the impurities are activated by the heating even in a depth range between the position53and the position58. Accordingly, in each IGBT region20, the n-type buffer region28is formed in a region deeper than the collector region30(in the depth range between the position53and the position58).

In each diode region40, the energy density of the laser is high, and hence the semiconductor region in the proximity of the lower surface12bis heated from its shallow portion to deep portion. More specifically, the range up to the depth D6shown inFIG. 6(the depth deeper than the depths D4and D5) (i.e., the depth range between the lower surface12band the position56) is heated to a temperature equal to or higher than the melting point of silicon. Therefore, the semiconductor region in the depth range between the lower surface12band the position56is melted, and then that semiconductor region is solidified. Accordingly, as shown inFIG. 3, after the heating, each of the p-type impurity density and the n-type impurity density becomes approximately constant in the depth range between the lower surface12band the position56. Moreover, as shown inFIG. 6, prior to the heating, the total amount of the n-type impurities is larger than the total amount of the p-type impurities in the depth range between the lower surface12band the position56. Accordingly, as shown inFIG. 3, after the melting, the n-type impurity density becomes higher than the p-type impurity density in an entirety of the depth range between the lower surface12band the position56. In other words, most of n-type impurities that exist in a high density in the deep portion of the semiconductor substrate12are diffused into the shallow portion of the semiconductor substrate12, causing the shallow portion to be converted to be n-type. Moreover, the impurities are activated in the melted semiconductor region. Furthermore, a semiconductor region which is located in a range deeper than the position56and is not melted is also heated by the laser. Therefore, the impurities are activated even in the range deeper than the position56. Accordingly, in each diode region40, the n-type cathode region48exposed on the lower surface12bis formed in the depth range between the lower surface12band the position58.

As described above, by performing the laser irradiation step, the collector regions30, the buffer regions28, and the cathode regions48are formed.

After the laser irradiation step is performed, the lower electrode16is formed on the lower surface12bof the semiconductor substrate12. The semiconductor device10shown inFIG. 1is thereby completed.

As described above, according to this method, there is no need to delimit implantation areas for p-type impurities and n-type impurities. Therefore, there is no need to form resist masks in the p-type impurity implantation step and the n-type impurity implantation step. Accordingly, a step related to formation and removal of the resist masks can be omitted. Moreover, it is easy to perform a laser irradiation so that the IGBT regions20and the diode regions40are irradiated at different energy densities, respectively. According to this method, the semiconductor device10can be manufactured efficiently. Moreover, in a case of using a resist mask, when the resist mask is removed after being used, there may be a case where residue of the resist mask remains on the surface of the semiconductor substrate. If the residue remains on the surface, there may be a case where a portion of the semiconductor substrate on which the residue remains is not sufficiently heated in the laser irradiation step, causing a failure to obtain desired electrical properties. According to the manufacturing method in the present embodiment, no resist mask is used, and hence such a problem does not occur.

Notably, in the above-mentioned embodiment, the areas irradiated with the laser on the forward path and the return path are partially overlapped so that the energy density in the diode regions40becomes higher than the energy density in the IGBT regions20. However, various methods other than the method in the embodiment can be adopted for making energy densities different between irradiated areas. For example, an irradiation intensity (W/cm2) of the laser may be made higher in the diode regions40than in the IGBT regions20. Alternatively, a speed at which the focus90of the laser is moved may be made slower in the diode regions40than in the IGBT regions20. Lowering the speed at which the focus90of the laser is moved can lengthen laser irradiation time, and hence the energy density can be increased. Moreover, these methods may be combined.

Moreover, in the above-mentioned embodiment, the collector regions30are formed in the depth range between the lower surface12band the position53. However, the depth range where the collector regions30are formed can be changed. As mentioned above, the position54inFIG. 6is a position at which the total amount of the p-type impurities that exist in the depth range between the lower surface12band the position54coincides with the total amount of the n-type impurities that exist in the same depth range. Accordingly, in a depth range between a position shallower than the depth D4and the lower surface12b, the total amount of the p-type impurities is larger than the total amount of the n-type impurities. Accordingly, in the laser irradiation step, by diffusing the impurities in a depth range between the lower surface12band one of positions shallower than the depth D4, it is possible to form a p-type region exposed on the lower surface12b.

Moreover, in the above-mentioned embodiment, the cathode regions48are formed in the depth range between the lower surface12band the position58. However, the depth range where the cathode regions48are formed can be changed. In a depth range between a position deeper than the depth D4and the lower surface12b, the total amount of the n-type impurities is larger than the total amount of the p-type impurities. Accordingly, in the laser irradiation step, by diffusing the impurities in a depth range between the lower surface12band one of positions deeper than the depth D4, it is possible to form an n-type region exposed on the lower surface12b.

Moreover, in the above-mentioned embodiment, a semiconductor region is melted in the depth range between the lower surface12band the position52in the IGBT regions20. Moreover, a semiconductor region is also melted in the depth range between the lower surface12band the position56in the diode regions40. However, a semiconductor region does not necessarily need to be melted. Even if a semiconductor region is not melted, impurities can be diffused in the semiconductor region in a solid state. However, it should be noted that, if the semiconductor region is melted, the impurities are more uniformly distributed in the melted semiconductor region. Accordingly, the collector regions30and the cathode regions48can be formed more stably. Moreover, if a semiconductor region is once melted and then solidified, a large number of crystal defects in the semiconductor region disappear. Accordingly, it is possible to form the collector regions30and the cathode regions48each having a low crystal defect density. Therefore, it is more preferable to melt a semiconductor region.

Notably, in the IGBT regions20, it is preferable to melt a depth range between a position shallower than the position53(the position at which the p-type impurity density and the n-type impurity density coincide with each other prior to the heating) and the lower surface12b. In this depth range, the p-type impurity density is higher than the n-type impurity density, and hence the collector regions30can be formed more reliably. Moreover, in the IGBT regions20, it is preferable to melt a depth range between a position deeper than the position51(a peak position of the p-type impurity density prior to the heating) and the lower surface12b. By melting the depth range that includes the peak position of the p-type impurity density as such, it is possible to form the collector regions30that have a high p-type impurity density on the lower surface12b.

Moreover, in the diode regions40, it is preferable to melt a depth range between a position deeper than the position55(a peak position of the n-type impurity density prior to the heating) and the lower surface12b. By melting the depth range that includes the peak position of the n-type impurity density as such, it is possible to form the cathode regions48that have a high n-type impurity density on the lower surface12b.

Moreover, in the above-mentioned embodiment, the n-type impurities and the p-type impurities are implanted to the lower surface12bof the semiconductor substrate12. Alternatively, an n-type semiconductor region may be formed by epitaxial growth and the like, and the p-type impurities may be implanted to that n-type semiconductor region. Moreover, a p-type semiconductor region may be formed by epitaxial growth and the like, and the n-type impurities may be implanted to that p-type semiconductor region.

Moreover, in the above-mentioned embodiment, a method of manufacturing an RC-IGBT has been described. However, in a semiconductor device that has no IGBT structure but has a diode structure, an n-type region (a cathode region) and a p-type region may be formed so as to be exposed on a lower surface of the diode. Even with such a diode, the effect of suppressing a reverse recovery loss, which is mentioned above, can be obtained. Moreover, when the n-type region and the p-type region exposed on the lower surface of the diode are formed, the manufacturing method in the above-mentioned embodiment can be used. Moreover, the art disclosed herein may be applied to a step of manufacturing other semiconductor devices having a p-type region and an n-type region exposed on a surface.

Relationships between constituent elements in the above-mentioned embodiment and constituent elements in the claims will be described. The lower surface12bin the IGBT regions20in the embodiment is one example of a first area in the claims. The lower surface12bin the diode regions40in the embodiment are one example of a second area in the claims. The position52in the embodiment is one example of a first position in the claims. The position56in the embodiment is one example of a second position in the claims. The collector regions30in the embodiment are one example of a first conductivity type region in the claims. The cathode regions48in the embodiment are one example of a second conductivity type region in the claims.

Preferable configurations of the embodiment described above will hereinafter be enumerated. Notably, each of the configurations enumerated below has utility independently.

In a configuration disclosed herein as an example, a semiconductor region in the first depth range on the first area is temporarily melted with the laser irradiation.

If the semiconductor region is temporarily melted and then solidified as such, impurities are uniformly dispersed in this semiconductor region and the impurity density becomes approximately constant. Moreover, if the semiconductor region is temporarily melted and then solidified, a large number of crystal defects disappear. Therefore, according to this method, it is possible to form the first conductivity type region having a relatively uniform impurity density and a low crystal defect density.

Notably, as described above, if the semiconductor region is temporarily melted and then solidified, the impurity density becomes approximately constant in that semiconductor region. Accordingly, by measuring the impurity density distribution in the semiconductor region, it is possible to determine whether or not the semiconductor region has been temporarily melted.

In a configuration disclosed herein as an example, a semiconductor region in the second depth range on the second area is temporarily melted with the laser irradiation.

According to this method, it is possible to form the second conductivity type region having a relatively uniform impurity density and a low crystal defect density.

In a configuration disclosed herein as an example, the first conductivity type is p-type, and the second conductivity type is n-type.

According to such a configuration, on the first area, an n-type region is formed at a position deeper than the p-type first conductivity type region (the region exposed on the surface). This n-type region can be utilized as a buffer region that stops extension of a depletion layer in an IGBT or a diode.

The embodiments have been described in detail in the above. However, these are only examples and do not limit the claims. The technology described in the claims includes various modifications and changes of the concrete examples represented above. The technical elements explained in the present description or drawings exert technical utility independently or in combination of some of them, and the combination is not limited to one described in the claims as filed. Moreover, the technology exemplified in the present description or drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of such objects.