Semiconductor device

Provided is a semiconductor device that can be manufactured at low cost and that can reduce a reverse leak current, and a manufacturing method thereof. A semiconductor device has: a source region and a drain region having a body region therebetween; a source trench that reaches the body region, penetrating the source region; a body contact region formed at the bottom of the source trench; a source electrode embedded in the source trench; and a gate electrode that faces the body region. The semiconductor device also has: an n-type region for a diode; a diode trench formed reaching the n-type region for a diode; a p+ region for a diode that forms a pn junction with the n-type region for a diode at the bottom of the diode trench; and a schottky electrode that forms a schottky junction with the n-type region for a diode at side walls of the diode trench.

This application claims the benefit of Japanese Application No. 2012-107673, filed in Japan on May 9, 2012, which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a manufacturing method thereof.

2. Description of Related Art

The semiconductor device disclosed in Patent Document 1 includes a schottky barrier diode connected between the source and the drain. More specifically, in the semiconductor device, a p-type base layer is formed in the surface portion of an n-type semiconductor layer formed on an n-type semiconductor substrate. A trench is formed from the surface of the n-type semiconductor layer so as to penetrate the p-type base layer, and on the side walls and the bottom of the trench, a gate insulating film is formed. A gate electrode is embedded in the trench. An n-type diffusion layer is formed in a surface portion of the p-type base layer.

With this configuration, this semiconductor device is equipped with a trench gate type transistor. In this transistor, the n-type diffusion layer is a source region, the n-type semiconductor layer is a drain region, and a channel is formed near the boundary between the gate insulating film and the p-type base layer formed between the n-type diffusion layer and the n-type semiconductor layer. As a result, an electric current flows between the source region and the drain region.

A metal layer is deposited on the surface of the n-type semiconductor layer. The metal layer is in contact with the n-type diffusion layer, thereby functioning as a source electrode, and also, by the metal layer being in contact with the surface of the n-type semiconductor layer in a region where the p-type base layer is not formed, a schottky junction is formed between the region and the metal layer. As described above, in this semiconductor device, a transistor and a schottky barrier diode are formed in one chip.

RELATED ART DOCUMENTS

Patent Documents

SUMMARY OF THE INVENTION

In manufacturing the semiconductor device of Patent Document 1, it is necessary to form a protective film on the entire surface of the n-type semiconductor layer before the trench for embedding the gate electrode therein is formed. In this case, after forming the trench, it is necessary to remove the protective film from a region where the schottky barrier diode is to be formed. This makes the manufacturing process of the semiconductor device complex, and as a result, it becomes difficult to manufacture a semiconductor device at low cost.

Also, in order to improve the performance of the schottky barrier diode, a reduction in reverse leak current in a reverse bias state is sought after.

One of the objects of the present invention is to provide a semiconductor device that can be manufactured at low cost and that can reduce the reverse leak current, and a manufacturing method thereof.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in the first aspect of the present invention, a semiconductor device has: a semiconductor layer of a first conductive type; a body region of a second conductive type formed in the semiconductor layer of the first conductive type; a source region and a drain region of the first conductive type formed in the semiconductor layer so as to be separated from each other across the body region; a source trench formed in the semiconductor layer, the source trench penetrating the source region and reaching the body region; a body contact region formed near a bottom of the source trench and in the semiconductor layer of the first conductive type that includes the body region, the body contact region being the second conductive type and having a higher impurity concentration than that of the body region; a source electrode embedded in the source trench; a gate electrode facing through a gate insulating layer the body region that lies between the source region and the drain region; a first conductive type region for a diode formed in the semiconductor layer; a diode trench formed in the semiconductor layer that includes the first conductive type region for a diode; a second conductive type region for a diode formed in the first conductive type region for a diode so as to be in contact with a bottom of the diode trench, the second conductive type region for a diode forming a pn junction with the first conductive type region for a diode; and a schottky electrode forming a schottky junction with the first conductive type region for a diode at side walls of the diode trench.

With this configuration, a transistor is formed in the semiconductor layer outside of the diode forming region. In the diode forming region, a pn diode is formed at the bottom of the diode trench, and a schottky barrier diode is formed at side walls of the diode trench. In this case, the source trench and the diode trench can be formed at the same time. Also, it is possible to form the body contact region at the bottom of the source trench at the same time as forming the second conductive type region for a diode at the bottom of the diode trench. Furthermore, it is possible to embed the source electrode in the source trench at the same time as forming the schottky electrode in the diode trench. In this way, the transistor and the diode can be formed at the same time, and therefore, it is possible to omit a process that would be needed if the transistor and the diode were formed in different processes (such as a process of forming a protective film on the surface of the semiconductor layer and removing the protective film in the diode region after forming the source trench). As described above, because the diode trench and the second conductive type region for a diode can be formed in the process for forming the transistor (or in other words, because a special process for forming the diode is no longer necessary), it is possible to form a semiconductor device that has a transistor and a schottky barrier diode on the same chip with a smaller number of manufacturing steps. As a result, the semiconductor device can be manufactured at low cost.

In a reverse bias state, a depletion layer spreads around the pn diode at the bottom of the diode trench, which blocks the path of an electrical current in the diode region, and as a result, the reverse leak current can be reduced.

In the second aspect of the present invention, the diode trench has the same depth as that of the source trench. With this configuration, the diode trench and the source trench can be formed in the semiconductor layer at the same time with the same etching conditions, for example.

In the third aspect of the present invention, the semiconductor device further includes: a first interlayer insulating film that insulates the gate electrode and the source electrode from each other; and a second interlayer insulating film disposed between the schottky electrode and a surface of the first conductive type region for a diode outside of the diode trench. With this configuration, it is possible to insulate the gate electrode and the source electrode from each other by the first interlayer insulating film, and it is possible to insulate the schottky electrode and the surface of the first conductive type region for a diode outside of the diode trench from each other.

In the fourth aspect of the present invention, the first interlayer insulating film and the second interlayer insulating film have the same thickness.

With this configuration, in manufacturing the semiconductor device, it is possible to form the source trench and the diode trench at the same time after an interlayer insulating film that becomes the first interlayer insulating film and the second interlayer insulating film is formed on the entire surface of the semiconductor layer. Also, the second conductive type region for a diode can be formed at the bottom of the diode trench at the same time as forming the body contact region near the bottom of the source trench. At the side walls of the diode trench, a schottky barrier diode can be formed. In this case, it is not necessary to remove the interlayer insulating film. In this configuration, the first interlayer insulating film and the second interlayer insulating film can be formed in the same step.

In the fifth aspect of the present invention, the schottky electrode has a first thickness at the side walls of the diode trench, and a second thickness that is greater than the first thickness on the second interlayer insulating film.

If the thickness of a portion of the schottky electrode forming a schottky junction with the first conductive type region for a diode differs depending on places, a plurality of schottky barrier diodes having slightly different forward voltages (Vf) are connected in parallel, which can cause the characteristics of the entire schottky barrier diodes to be unstable. By contrast, with the configuration of the invention according to claim5, only the portion of the schottky electrode having the first thickness forms the schottky junction with the first conductive type region for a diode at the side walls of the diode trench, and the portion of the schottky electrode having the second thickness does not form the schottky junction with the first conductive type region for a diode. As a result, the portion of the schottky electrode forming the schottky junction with the first conductive type region for a diode has a uniform thickness, i.e., the first thickness, and because the variation in Vf can be eliminated, the overall characteristics of the schottky barrier diode can be made stable.

In the sixth aspect of the present invention, a plurality of diode trenches are formed in the diode forming region with a gap therebetween.

In the seventh aspect of the present invention, the gap between the plurality of diode trenches is set such that depletion layers spreading from the respective pn junctions in a reverse bias state are connected to each other. With this configuration, in the reverse bias state, the depletion layers spread and are connected to each other at the bottom portions of adjacent diode trenches, which makes it possible to block the path of an electric current in the first conductive type region for a diode more reliably, and therefore, the reverse leak current can be reduced to a greater degree.

In the eighth aspect of the present invention, the schottky electrode includes a schottky/ohmic electrode layer that forms a schottky contact with the first conductive type region for a diode at side walls of the diode trench and that forms an ohmic contact with the second conductive type region for a diode at a bottom of the diode trench. With this configuration, by forming the schottky/ohmic electrode layer at the side walls and bottom of the diode trench, the schottky barrier diode and the pn diode can be formed at the same time.

In the ninth aspect of the present invention, the source electrode and the schottky electrode are made of the same electrode material. With this configuration, the source electrode and the schottky electrode can be formed in the same step by supplying the electrode material into the source trench and the diode trench.

The tenth aspect of the present invention is the semiconductor device according to any one of claims1to9, wherein the source trench is formed at a surface of the semiconductor layer in a linear shape along a first direction, and wherein the diode trench is formed at the surface of the semiconductor layer in a linear shape along a second direction that is orthogonal to the first direction.

With this configuration, by injecting impurity ions into the source trench and the diode trench at an angle relative to the second direction to form the body contact region and the second conductive type region for a diode, the body contact region is formed at the side walls and the bottom of the source trench, and the second conductive type region for a diode is formed at the bottom of the diode trench. However, because the impurity ions are not injected to a pair of side walls of the diode trench facing each other along the first direction, the second conductive type region for a diode is not formed thereat. This allows the schottky electrode to form a schottky junction at those side walls of the diode trench.

In the eleventh aspect of the present invention, the diode trench is rectangular in a plan view.

In the twelfth aspect of the present invention, the source trench is formed at a surface of the semiconductor layer in a linear shape, and two parallel sides of the diode trench that is rectangular in a plan view are orthogonal to a lengthwise direction of the source trench. With this configuration, by injecting impurity ions into the source trench and the diode trench at an angle relative to the direction orthogonal to the lengthwise direction of the source trench, to form the body contact region and the second conductive type region for a diode, the body contact region is formed at the side walls and the bottom of the source trench, and the second conductive type region for a diode is formed at the bottom of the diode trench. However, because the impurity ions are not injected into a pair of side walls of the diode trench facing each other along the direction orthogonal to the lengthwise direction of the diode trench, the second conductive type region for a diode is not formed at the side walls. This allows the schottky electrode to form a schottky junction at the side walls of the diode trench.

In the thirteen aspect of the present invention, the source region and the drain region are arranged with a gap therebetween along a thickness direction of the semiconductor layer, the source region and the drain region having the body region disposed therebetween, a gate trench that reaches the drain region through the source region and the body region is further provided, and the gate electrode is embedded in the gate trench. With this configuration, when a voltage is applied to the gate electrode, a channel is formed near the gate electrode in the body region, which causes an electric current to flow through the transistor. That is, a trench gate type transistor is constructed.

In the fourteen aspect of the present invention, the diode trench is formed shallower than the gate trench.

In the fifteenth aspect of the present invention, the source region and the drain region are arranged along the surface of the semiconductor layer with a gap therebetween. That is, the transistor is a planar transistor.

In the sixteen aspect of the present invention, a manufacturing method of a semiconductor device includes: forming, in a semiconductor layer of a first conductive type in which the transistor region and a diode region are respectively defined, a body region of a second conductive type in the transistor region, and leaving the diode region as a first conductive type region for a diode; forming a source region and a drain region of the first conductive type so as to be separated from each other across the body region; forming both a source trench in the semiconductor layer and a diode trench in the diode region at the same time, the source trench reaching the body region through the source region; injecting an impurity ion into the semiconductor layer near a bottom of the source trench and near a bottom of the diode trench to form, at the same time, a body contact region near the bottom of the source trench and in the semiconductor layer that includes the body region, and a second conductive type region for a diode near the bottom of the diode trench in the semiconductor layer, the body contact region being the second conductive type and having a higher impurity concentration than that of the body region, the second conductive type region for a diode forming a pn junction with the first conductive type region for a diode; forming a gate electrode facing through a gate insulating layer the body region that lies between the source region and the drain region; and embedding a source electrode in the source trench at the same time as forming a schottky electrode that forms a schottky junction with the first conductive type region for a diode at side walls of the diode trench.

With this method, in the completed semiconductor device, a transistor is formed in the transistor region, and in the diode region, a pn diode is formed at the bottom of the diode trench, and a schottky barrier diode is formed at the side walls of the diode trench. In this case, the source trench and the diode trench can be formed at the same time. Also, it is possible to form the body contact region at the bottom of the source trench at the same time as forming the second conductive type region for a diode at the bottom of the diode trench. Furthermore, it is possible to embed the source electrode in the source trench at the same time as forming the schottky electrode in the diode trench. In this way, the transistor and the diode can be formed at the same time, and therefore, it is possible to eliminate a process that is necessary when the transistor and the diode are formed in different processes (such as a process of forming a protective film on the surface of the semiconductor layer, and removing the protective film from the diode region after forming the source trench). As a result, the semiconductor device can be manufactured at low cost.

Also, in the completed semiconductor device, in the reverse bias state, a depletion layer spreads around the second conductive type region for a diode at the bottom of the diode trench, and because the path of an electric current in the diode region is thereby blocked, the reverse leak current can be reduced.

In the seventeenth aspect of the present invention, the manufacturing method further includes: forming, before forming the source electrode and the schottky electrode, a first interlayer insulating film for insulating the gate electrode and the source electrode from each other at the same time as forming a second interlayer insulating film interposed between the schottky electrode and the surface of the first conductive type region for a diode outside of the diode trench.

With this method, in the completed semiconductor device, the gate electrode and the source electrode can be insulated from each other by the first interlayer insulating film, and the schottky electrode and the surface of the first conductive type region for a diode outside of the diode trench can be insulated from each other by the second interlayer insulating film. Because the first and second interlayer insulating films are formed in the same step, the number of manufacturing steps can be reduced.

In the eighteenth aspect of the present invention, a plurality of diode trenches are formed in the diode region with a gap therebetween, and the gap between the plurality of diode trenches is set such that a depletion layer spreading from each pn junction is connected to one another in the reverse bias state.

With this method, in the completed semiconductor device, in the reverse bias state, the depletion layers spread and are connected to each other at the bottom of adjacent diode trenches, which makes it possible to block the path of an electric current in the first conductive type region for a diode more reliably, and therefore, the reverse leak current can be reduced to a greater degree.

In the nineteenth aspect of the present invention, the source trench is formed at a surface of the semiconductor layer in a linear shape along a first direction, and the diode trench is formed at the surface of the semiconductor layer in a linear shape along a second direction that is orthogonal to the first direction.

With this configuration, by injecting impurity ions into the source trench and the diode trench at an angle relative to the second direction, to form the body contact region and the second conductive type region for a diode, the body contact region is formed at the side walls and the bottom of the source trench, and the second conductive type region for a diode is formed at the bottom of the diode trench. However, because the impurity ions are not injected into a pair of side walls of the diode trench facing each other along the first direction, the second conductive type region for a diode is not formed at the side walls. This allows the schottky electrode to form a schottky junction at the side walls of the diode trench.

In the twentieth aspect of the present invention, the source trench is formed in a linear shape at the surface of the semiconductor layer, the diode trench is formed to be rectangular in a plan view, and two parallel sides of the diode trench that is rectangular in a plan view are orthogonal to a lengthwise direction of the source trench.

With this method, by injecting impurity ions into the source trench and the diode trench at an angle relative to the direction orthogonal to the lengthwise direction of the source trench, to form the body contact region and the second conductive type region for a diode, the body contact region is formed at the side walls and the bottom of the source trench, and the second conductive type region for a diode is formed at the bottom of the diode trench. However, because the impurity ions are not injected to a pair of side walls of the diode trench facing each other along the direction orthogonal to the lengthwise direction of the diode trench, the second conductive type region for a diode is not formed at the side walls. This allows the schottky electrode to form a schottky junction at the side walls of the diode trench.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Below, embodiments of the present invention will be explained in detail with reference to appended drawings.

FIG. 1is a schematic plan view of a semiconductor device of an embodiment of the present invention.FIG. 2is a schematic plan view of a semiconductor device of another embodiment of the present invention.

A semiconductor device1of an embodiment of the present invention is formed to be a quadrangular chip in a plan view. The length of each of the four sides of the semiconductor device1in a plan view is approximately several mm, for example.

On the surface of the semiconductor device1having a quadrangular shape in a plan view, an external connection region A is formed along one side, and in a region other than the external connection region A, an active region B is formed. The semiconductor device1includes a plurality of external electrodes2disposed in the external connection region A, a guard ring3surrounding the active region B, a plurality of diode forming regions C disposed in the active region B, and a transistor forming region D defined as a region of the active region B where the diode forming regions C are not formed.

The plurality of (seven in this example) external electrodes2are disposed along one side of the quadrangle. Each external electrode2is connected to a lead (not shown) through a bonding wire (not shown) as described below. The guard ring3separates and insulates the external connection region A and the active region B from each other.

The plurality of diode forming regions C are dispersed so as to be distributed uniformly in the entire active region B. Specifically, the plurality of diode forming regions C may be arranged in a staggered pattern with a gap therebetween as shown inFIG. 1, or may be arranged in a matrix as shown inFIG. 2.

FIG. 3is an enlarged view of a main part of the semiconductor device ofFIG. 1or2.FIG. 4is a diagram showing a modification example of the main part of the semiconductor device ofFIG. 3.

FIG. 3shows a portion surrounded by a dotted line inFIG. 1or2(one diode forming region C and the transistor forming region D therearound).

Each diode forming region C is in a square shape in a plan view. In a plan view, each diode forming region C is surrounded by the transistor forming region D.

In the diode forming region C, schottky barrier diodes10and pn diodes45are formed, and in the transistor forming region D, a plurality of transistor cells11A are formed. The plurality of transistor cells11A are connected in parallel, and form one transistor11altogether (seeFIG. 1). The transistor11includes a plurality of schottky barrier diodes10and pn diodes45(seeFIG. 1). As described above, in the active region B of the semiconductor device1, the transistor11is formed surrounding the plurality of schottky barrier diodes10and pn diodes45(seeFIG. 1). Accordingly, in the semiconductor device1, the transistor11, the schottky barrier diodes10, and the pn diodes45are formed in the same element.

For the plurality of transistor cells11A (transistor11), gate trenches12and source trenches13, which will be described later, are formed throughout substantially the entire surface of the semiconductor device1(to be more specific, a front surface22A of a semiconductor layer22to be described later) in the transistor forming region D. The gate trenches12and the source trenches13are extended in a linear shape along the first direction Y in a plan view, and are alternately arranged side by side along the second direction X that is orthogonal to the first direction Y with a gap therebetween. That is, the gate trenches12and the source trenches13are formed in a stripe pattern.

Of the gate trench12and the source trench13, the source trench13is formed nearest to the diode forming region C. The source trench13that is nearest to the diode forming region C is in a square ring shape that surrounds the entire diode forming region C. The gate trench12adjacent to the source trench13that is nearest to the diode forming region C is in a square ring shape that surrounds the entire source trench13.

As shown inFIG. 4, the gate trenches12and the source trenches13may be arranged such that the gate trench12has a mesh-like pattern, thereby partitioning each of a plurality of rectangular regions, and in each of the rectangular regions, a source trench13is extended linearly so as not to touch the gate trench12. In this case also, the source trench13that is nearest to the diode forming region C is in a square ring shape that surrounds the entire diode forming region C, and the gate trench12adjacent to this source trench13is in a square ring shape that surrounds the entire source trench13.

For the schottky barrier diodes10and the pn diodes45, diode trenches14, which will be described later, are formed at the surface of the semiconductor device1in substantially the entire diode forming region C (to be more specific, the front surface22A of the semiconductor layer22, which will be described later). The diode trenches14extend linearly along the second direction X in a plan view, and are arranged side by side along the first direction Y with a gap therebetween. That is, in a plan view, each diode trench14is formed in a narrow rectangular shape longer in the second direction X, and a plurality of diode trenches14are formed in a stripe pattern. In each diode trench14that is rectangular in a plan view, two parallel sides (two sides extending in the second direction X) H are orthogonal to the lengthwise direction (first direction Y) of the source trench13.

FIG. 5is a perspective view near a cross section along the cut line V-V ofFIG. 3or4.

For ease of explanation,FIG. 5shows the source trenches13and the diode trenches14, but omits the gate trenches12. As shown inFIG. 5, the source trenches13formed in a linear shape along the first direction Y and the diode trenches14formed in a linear shape along the second direction X extend orthogonally to each other.

FIG. 6is a cross-sectional view along the cut line V-V ofFIG. 3or4. Because the cut line V-V is bent at a right angle halfway (seeFIGS. 3 and 4), two cross sections (cross section in the diode forming region C and cross section in the transistor forming region D) orthogonally intersect with each other in the actual device, but for ease of explanation,FIG. 6shows the two cross sections along the same plane (the same is true forFIGS. 7A to 7J, andFIG. 8below).

As shown inFIG. 6, the semiconductor device1includes a semiconductor substrate20, a rear electrode21, a semiconductor layer22, a gate insulating film23, gate electrodes24, an oxide film25, an insulating layer26, a first metal film27, a second metal film29, source electrodes28, and a conductive layer30.

The semiconductor substrate20is made of an n+semiconductor (silicon, for example) with a prescribed concentration (1×1019to 5×1019atom/cm3, for example).

The rear electrode21covers the entire rear surface (lower surface inFIG. 6) of the semiconductor substrate20. The rear electrode21is made of a metal (such as gold, nickel silicide, and cobalt silicide, for example) that forms an ohmic contact with n-type silicon. Therefore, the rear electrode21forms an ohmic contact with the rear surface of the semiconductor substrate20.

The semiconductor layer22is formed on the front surface (upper surface inFIG. 6) of the semiconductor substrate20. The semiconductor layer22is made of an n−semiconductor having a lower concentration than the semiconductor substrate20(5×1015to 5×1016atom/cm3, for example). In the semiconductor layer22ofFIG. 6, the upper surface is referred to as a front surface22A and the lower surface is referred to as a rear surface22B. The thickness of the entire semiconductor layer22is 4 μm, for example. The semiconductor layer22and the semiconductor substrate20may be collectively regarded as a semiconductor layer.

In the semiconductor layer22, the diode forming region C and the transistor forming region D are defined as described above. The semiconductor layer22in the transistor forming region D is referred to as a transistor region35, and the semiconductor layer22in the diode forming region C is referred to as an n-type region for a diode.FIG. 6shows a part of the semiconductor layer22near the boundary between the diode forming region C and the transistor forming region D. The front surface22A and the rear surface22B of the semiconductor layer22are flat throughout the entire diode forming region C and the transistor forming region D, and extend parallel to each other.

In the entire surface portion of the semiconductor layer22in the transistor forming region D (transistor region35), a p−body region31having a prescribed impurity concentration (1×1016to 1×1017atom/cm3, for example) is formed. A region of the transistor region35closer to the rear surface22B than the body region31is an n−drain region34. On the other hand, the semiconductor layer22in the diode forming region C is the abovementioned n-type region40for a diode, which is of an n−type. Near the surface of the body region31, an n+source regions32having a prescribed impurity concentration (5×1019to 5×1020atom/cm3, for example) is selectively formed. Therefore, the body region31lies between the source region32and the drain region34along the thickness direction of the semiconductor layer22. In other words, in the transistor region35, the source region32and the drain region34are formed so as to be separated from each other across the body region31(along the thickness direction of the semiconductor layer22). The surface of the source region32and the surface of the body region31in a region where the source region32is not formed are flush with each other, constituting the front surface22A of the semiconductor layer22(transistor region35) in the transistor forming region D. The thickness of the source region32is approximately 0.2 μm, for example, and the thickness of a portion of the body region31closer to the rear surface22B than the source region32is approximately 0.4 μm, for example.

In the semiconductor layer22in the transistor forming region D, the above-mentioned gate trenches12are formed. Each gate trench12is recessed from the front surface22A toward the rear surface22B of the semiconductor layer22in the transistor forming region D. The gate trench12penetrates both the source region32and the body region31, reaching the inside of the drain region34. The bottom surface of the gate trench12is given the reference character12A. The trench width of the gate trench12is approximately 0.2 μm, and the depth thereof is approximately 1 μm, for example.

The gate insulating film23is made of silicon oxide (SiO2), and is formed so as to make contact with the entire inner surface (side wall surfaces and bottom wall surface) of each gate trench12. The gate insulating film23makes contact with the body region31at the side wall surfaces of the gate trench12, and makes contact with the drain region34at the bottom wall surface of the gate trench12.

The gate electrode24is made of polysilicon, for example. The gate electrode24is embedded in the gate insulating film23in each gate trench12. The gate electrode24faces surfaces (portions exposed in the gate trench12) of the body region31(between the source region32and the drain region34) and the drain region34through the gate insulating film23.

The oxide film25is made of SiO2, and covers substantially the entire front surface22A of the semiconductor layer22in the transistor forming region D and the diode forming region C.

The insulating layer26is made of glass such as BPSG (boron phosphor silicate glass), and is formed on the oxide film25. The layered oxide film25and insulating layer26constitute an interlayer insulating film48. The thickness of the interlayer insulating film48is approximately 0.5 μm, for example. The interlayer insulating film48includes a first interlayer insulating film48A formed in the transistor forming region D, and a second interlayer insulating film48B formed in the diode forming region C. The first interlayer insulating film48A and the second interlayer insulating film48B have the same thickness.

The above-mentioned source trench13is recessed from the surface of the insulating layer26(upper surface inFIG. 6), and reaches the inside of the body region31, penetrating the insulating layer26, the oxide film25(first interlayer insulating film48A), and the source region32in the semiconductor layer22. The source trenches13are formed in positions other than where the gate trenches12are formed in the semiconductor layer22in the transistor forming region D, and are recessed from the front surface22A of the semiconductor layer22in these positions. The trench width of the source trench13is approximately 0.2 μm, and the depth thereof is approximately 0.3 μm, for example. The distance P between the bottom surface13A of the source trench13and the rear surface22B of the semiconductor layer22is greater than the distance Q between the bottom surface12A of the gate trench12and the rear surface22B of the semiconductor layer22. That is, the source trench13is formed shallower than the gate trench12. In a plan view, an end of the body region31closer to the diode forming region C coincides with the center of the bottom surface13A in the width direction of the source trench13that is closest to the diode forming region C (the rightmost source trench13inFIG. 6).

At the bottom surface13A of the source trench13in the body region31and the periphery thereof (bottom portion of the source trench13), a p+body contact region33is formed. The body contact region33has a higher impurity concentration (5×1018to 5×1019atom/cm3, for example) than that of the p−body region31.

The above-mentioned diode trenches14are recessed from the front surface of the insulating layer26(upper surface inFIG. 6), and reaches the inside of the n-type region40for a diode in the semiconductor layer22, penetrating the insulating layer26and the oxide film25(second interlayer insulating film48B). As described above, the diode trench14is formed extending along the second direction X, and a plurality of diode trenches14are formed along the first direction Y with a gap therebetween in the n-type region40for a diode (seeFIGS. 3 and 4). The distance R between the bottom surface14A of each diode trench14and the rear surface22B of the semiconductor layer22is the same as the distance P between the bottom surface13A of the source trench13and the rear surface22B of the semiconductor layer22, and is greater than the distance Q between the bottom surface12A of the gate trench12and the rear surface22B of the semiconductor layer22. That is, the source trench13and the diode trench14have the same depth, and are formed shallower than the gate trench12.

At the bottom of the diode trench14(portion immediately below the bottom surface14A) in the n-type region40for a diode, a p+region41for a diode, which is of a p+type and has substantially the same impurity concentration as that of the body contact region33, is formed. The p+region41for a diode forms a pn junction with the n-type region40for a diode, which is of an n−type.

The first metal film27is made of a metal that forms a schottky junction by joining with n−-type silicon. Examples of such a metal include titanium (Ti), molybdenum (Mo), palladium (Pd), titanium nitride (TiN), titanium silicide, molybdenum silicide, tungsten silicide, and cobalt silicide. These metals form a schottky junction with an n−semiconductor, and forms an ohmic junction with n+and p+semiconductors. The first metal film27is formed to make contact with the entire front surface of the first interlayer insulating film48A (upper surface inFIG. 6) and the entire inner surfaces of each source trench13, and in this state, the first metal film27is electrically connected to the source region32and the body contact region33(forming an ohmic contact). As described above, the source trenches13are formed to make contact with the source region32and the body contact region33.

The first metal film27is also formed so as to make contact with the entire front surface of the second interlayer insulating film48B (upper surface inFIG. 6) and the entire inner surfaces of each diode trench14, and in this state, the first metal film27forms an ohmic contact with the p+region41for a diode, and forms a schottky junction with the n-type region40for a diode at side walls14B of the diode trench14.

The source electrodes28are made of tungsten, for example. The source electrode28is embedded in each source trench13so as to fill the inner space of the source trench13where the first metal film27is formed. The first metal film27in the source trench13functions as a part of the source electrode28. The first interlayer insulating film48A is formed covering the gate electrodes24, and the source electrodes28are formed in the first interlayer insulating film48A in positions where the gate electrodes24are not formed. This way, because the first interlayer insulating film48A is interposed between a gate electrode24and a source electrode28adjacent to each other, the adjacent gate electrode24and source electrode28can be insulated from each other by the first interlayer insulating film48A.

The second metal film29is made of titanium or titanium nitride, and covers the entire surface of the first metal film27and the surface of each source electrode28that is exposed from the source trench13(upper surface inFIG. 6). In the diode forming region C, the layered first metal film27and second metal film29constitute a schottky electrode42. The schottky electrode42includes the first metal film27as a schottky/ohmic electrode layer that forms a schottky contact with the n-type region40for a diode at the side walls14B of the diode trench14and that forms an ohmic contact with the p+region41for a diode at the bottom (around the bottom surface14A) of the diode trench14. The thickness of the schottky electrode42is 200 Å to 300 Å.

The front surface22A of the semiconductor layer22in a portion of the diode region where the diode trenches14are not formed is entirely covered by the second interlayer insulating film48B, and the front surface (upper surface inFIG. 6) and the side faces (constituting side walls14B of the diode trench14) of the second interlayer insulating film48B are covered by the schottky electrode42. That is, the second interlayer insulating film48B is disposed (interposed) between the schottky electrode42and the surface (front surface22A of the semiconductor layer22) of the diode region outside of the diode trenches14. By the second interlayer insulating film48B, the schottky electrode42and the surface of the diode region outside of the diode trenches14are insulated from each other.

The conductive layer30is made of an alloy of aluminum and copper (AlCu alloy), for example. The conductive layer30is layered on the second metal film29, and covers the entire surface (upper surface inFIG. 6) of the second metal film29. The conductive layer30is electrically connected to corresponding electrodes out of the plurality of external electrodes2mentioned above (seeFIGS. 1 and 2). The gate electrodes24are electrically connected to other corresponding external electrodes2via not-shown relay wiring lines.

In the transistor forming region D, the conductive layer30, the second metal film29, the source electrodes28, the first metal film27, the source region32, and the body contact region33are electrically connected. The rear electrode21, the semiconductor substrate20, and the drain region34that is formed in a region of the semiconductor layer22closer to the semiconductor substrate20than the body region31are electrically connected.

This way, in the transistor forming region D, transistor cells11A are constructed individually. The transistor cell11A (transistor11) has gate trenches12in which the gate electrodes24are embedded, and is therefore a so-called trench gate MOSFET (metal oxide semiconductor field effect transistor). In the transistor cell11A, a parasitic diode is formed by the body region31and the drain region34.

For example, in a state where the source electrodes28(conductive layer30) are grounded and a positive voltage is applied to the rear electrode21, a voltage equal to or greater than a threshold voltage is applied to the gate electrodes24. As a result, a channel is formed in a channel region X near the boundary between the body region31and the gate insulating film23outside of the gate electrodes24, allowing an electric current to flow toward the source electrode28from the rear electrode21via the channel.

In the diode forming region C, the rear electrode21forms an ohmic contact with the semiconductor substrate20, and the first metal film27(schottky electrode42) forms a schottky junction with the n-type region40for a diode at the side walls14B of the diode trench14, thereby constituting a schottky barrier diode10. The schottky barrier diode10and the transistor11are connected to each other in parallel. Also, the p+ region41for a diode at the bottom surface14A of each diode trench14forms a pn junction with the n-type region40for a diode in the diode forming region C, and with the pn junction between the p+region41for a diode and the n-type region40for a diode, a pn diode45is constituted. As described above, in one diode trench14, the pn diode45is formed at the bottom surface14A, and the schottky barrier diode10is formed at the side walls14B.

In each diode trench14in the diode forming region C, the schottky barrier diode10and the pn diode45are connected to each other in parallel. The forward voltage (Vf) of the schottky barrier diode10is lower than Vf of the pn diode45(0.6V to 0.7V, for example), and therefore, an electric current flows through the schottky barrier diode10before the pn diode45.

In a reverse bias state, a depletion layer80spreads from the pn diode45at the bottom of each diode trench14, and respective depletion layers80at the bottom of adjacent diode trenches14are connected to each other. In other words, the gap between the plurality of diode trenches14is set such that the depletion layers80each spreading from the pn junction between the p+ region41for a diode and the n-type region for a diode are connected to each other in the reverse bias state. By the depletion layers80spreading and connecting to each other near the pn diodes45at the bottom of the diode trenches14, the path of an electric current in the diode forming region is blocked, thereby making it possible to reduce the reverse leak current.

The second interlayer insulating film48B does not have to be formed, and it is also possible to omit the second insulating film48B so as to increase the area of the schottky junction between the schottky electrode42and the n-type region for a diode. However, the thickness of the schottky electrode42on the surface (front surface22A) of the n-type region for a diode, and the thickness of the schottky electrode42at the side walls14B of the diode trench14do not necessarily become equal to each other, possibly causing the characteristics to be unstable. In other words, if the thickness of a portion of the schottky electrode42that forms a schottky junction with the n-type region for a diode differs depending on places, a plurality of schottky barrier diodes10having slightly different forward voltages (Vf) are connected in parallel, which can cause the characteristics of the entire schottky barrier diodes10to be unstable.

In order to address this problem, in the semiconductor device1of the present embodiment, the second interlayer insulating film48B is left, instead of being removed. In this case, the schottky electrode42has a first thickness T at the side walls14B of the diode trench14, and has a second thickness U that is greater than the first thickness T on the second interlayer insulating film48B.

In the semiconductor device1, only the portion of the schottky electrode42having the first thickness T forms a schottky junction with the n-type region for a diode at the side walls14B of the diode trench14, and the portion of the schottky electrode42with the second thickness U does not form a schottky junction with the n-type region for a diode. As a result, the portion of the schottky electrode42that forms the schottky junction with the n-type region for a diode has a uniform thickness, i.e., the first thickness T, and because the variation in Vf can be eliminated, the overall characteristics of the schottky barrier diode10can be made stable. This makes it possible to improve the overall performance of the semiconductor device1. Also, because it is possible to omit the step of removing the second interlayer insulating film48B in manufacturing the semiconductor device1, the number of manufacturing steps can be reduced, thereby reducing the cost.

FIGS. 7A to 7Jare illustrative cross-sectional views showing a manufacturing method of the semiconductor device ofFIG. 6.

First, as shown inFIG. 7A, the semiconductor substrate20is made by a known method.

Next, as shown inFIG. 7B, on the semiconductor substrate20, the semiconductor layer22of an n−-type is formed through the epitaxial growth on the surface of the semiconductor substrate20. In the semiconductor layer22, a transistor region35corresponding to the transistor forming region D, and an n-type region40for a diode corresponding to the diode forming region C are defined.

Next, as shown inFIG. 7C, a resist pattern46covering the diode forming region C and exposing only the transistor forming region D (transistor region35) is formed on the semiconductor layer22. Next, a p-type impurity (boron, for example) is injected into a surface portion of the semiconductor layer22in the transistor forming region D (transistor region35). Thereafter, the resist pattern46is removed, and by conducting annealing, the p-type impurity is activated. As a result, as shown inFIG. 7C, the p−body region31is formed in the surface portion of the transistor region35. On the other hand, then type diode forming region remains intact. In the semiconductor layer22in the transistor forming region D, a portion closer to the semiconductor substrate20than the body region31is the drain region34.

Next, in the surface portion of the body region31, n-type impurity ions (arsenic or phosphorus, for example) are selectively injected. Thereafter, by conducting annealing, the n-type impurity is activated, and as shown inFIG. 7D, the source region32is formed in the surface portion of the body region31.

Next, through etching that uses a resist pattern (not shown) as a mask, recesses are formed in the semiconductor layer22from the front surface22A. As a result, as shown inFIG. 7E, gate trenches12are formed in the semiconductor layer22in the transistor forming region D.

Next, by the CVD (chemical vapor deposition) method, as shown inFIG. 7F, the gate insulating film23made of SiO2is formed to cover the entire inner surfaces of the gate trenches12.

Next, as shown inFIG. 7G, a gate electrode24made of polysilicon is embedded inside of the gate insulating film23in each gate trench12.

Next, by the CVD method, for example, a film made of SiO2(SiO2film)36is formed on the entire front surface22A of the semiconductor layer22in both the diode forming region C and the transistor forming region D. The SiO2film36becomes the oxide film25.

Next, by conducting CVD in high density, a layer made of glass such as BPSG (glass layer)37is formed on the SiO2film36.FIG. 7Gshows a state immediately after the glass layer37is formed. The glass layer37becomes the insulating layer26. By forming the glass layer37on the SiO2film36in this manner, the above-mentioned interlayer insulating film48is formed.

Next, by conducting etching that uses a resist pattern (not shown) as a mask, the glass layer37, the SiO2layer36, and the semiconductor layer22are etched in this order in the diode forming region C and the transistor forming region D, thereby forming recesses. In this way, as shown inFIG. 7H, a plurality of diode trenches14are formed in the diode forming region C, and at the same time, a plurality of source trenches13are formed in the transistor forming region D. The bottom surface14A of each diode trench14and the bottom surface13A of each source trench13are located at the same position in terms of the depth direction of the semiconductor layer22, and are at the same level. Because the diode trenches14and the source trenches13are formed in the same process (that is, with the same conditions), the diode trenches14and the source trenches13have the same depth.

Next, as shown inFIG. 7I, p-type impurity ions (boron, for example) are selectively injected into the surface portions of the semiconductor layer22through the bottom of each source trench13(bottom surface13A and the periphery thereof) and the bottom of each diode trench14(bottom surface14A and the periphery thereof). As indicated with the broken lines inFIG. 5, the impurity ions are injected toward the respective bottom portions of the source trenches13and the diode trenches14at a prescribed angle (approximately ±7°, for example) relative to the thickness direction of the semiconductor substrate20(in a direction inclined along the second direction X) in the plane along the second direction X (direction orthogonal to the lengthwise direction of the source trench13).

Therefore, as inFIG. 7I, when respective cross sections of the source trenches13and the diode trenches14along the respective widthwise directions are shown on the same plane, the impurity ions are injected to the source trenches13along the direction that is inclined relative to the depth direction, and the impurity ions are injected to the diode trenches14along the depth direction as indicated with the broken arrows. As a result, in each source trench13in the semiconductor layer22, the impurity ions are injected into the bottom surface13A and a pair of side walls13B facing along the widthwise direction (the above-mentioned second direction X). In each diode trench14in the semiconductor layer22, while the impurity ions are injected into the bottom surface14A and a pair of side walls14C (seeFIG. 5) facing along the lengthwise direction (the above-mentioned second direction X), almost no impurity ions are injected into a pair of side walls14B facing along the widthwise direction (the above-mentioned first direction Y).

Thereafter, by conducting annealing, the p-type impurity (ions injected in the previous step) is activated, forming the body contact region33in the body region31at the side walls13B and the bottom of each source trench13and, at the same time, forming the p+region41for a diode at the bottom of each diode trench14in the n-type region40for a diode. The p+region41for a diode is formed in a portion immediately below the bottom surface14A of the diode trench14and at the side walls14C of the diode trench14(seeFIG. 5). However, at the pair of side walls14B (facing along the above-mentioned first direction Y) of the diode trench14, the impurity ion injection was suppressed as described above, and therefore, the p+region41for the diode is not formed. This allows the schottky electrode42to form a schottky junction at the side walls14B of the diode trench14as described below.

Next, as shown inFIG. 7J, by sputtering or the like, the first metal film27made of titanium is formed on the entire inner surfaces of the source trenches13and the diode trenches14(portions of the oxide film25, the insulating layer26, and the semiconductor layer22that are exposed in each trench) and the entire surface of the insulating layer26(interlayer insulating film48).

Next, a source electrode28made of tungsten is embedded inside of the first metal film27in each source trench13.FIG. 7Jshows a state immediately after the source electrodes28are embedded.

Next, by sputtering or the like, the second metal film29made of titanium is formed on the entire surface of the first metal film27and the surface of each source electrode28that is exposed from the source trench13, and thereafter, the conductive layer30made of aluminum is formed on the second metal film29. Next, by forming the rear electrode21on the rear surface of the semiconductor substrate20, as shown inFIG. 6, each transistor cell11A (transistor11), schottky barrier diode10, and pn diode45are completed at the same time, thereby completing the semiconductor device1.

The source electrodes28(including the first metal film27in the source trenches13) and the schottky electrode42(constituted of the first metal film27and the second metal film29) may be made of the same electrode material (specifically the material of the first metal film27). In this case, the schottky electrode42is formed at the same time as embedding the source electrode28in each source trench13. That is, by supplying the electrode material into each source trench13and each diode trench14, the source electrodes28and the schottky electrode42can be formed in the same process. Also, by forming the schottky electrode42(especially the first metal film27) at the side walls14B and the bottom (bottom surface14A) of each diode trench14, the schottky barrier diode10and the pn diode45can be formed at the same time.

The schottky electrode42(first metal film27and second metal film29) is formed by sputtering or the like in which it is harder for a metal material (titanium as described above) to be deposited on the side walls14B of each diode trench14, and therefore, the thickness thereof becomes greater on the bottom surfaces14A and on the second interlayer insulating film48B than on the side walls14B.

As described above, in the semiconductor device1, the transistor11is formed in the transistor region35, which is a region of the semiconductor layer22outside of the diode forming region, and in the diode forming region, the pn diode45is formed at the bottom of each diode trench14, and the schottky barrier diode10is formed at the side walls14B of each diode trench14. In this case, the source trenches13and the diode trenches14can be formed at the same time (seeFIG. 7H). Also, it is possible to form the body contact region33at the bottom of each source trench13at the same time as forming the p+region41for a diode at the bottom of each diode trench14(seeFIG. 7I). Furthermore, it is possible to embed the source electrode28in each source trench13at the same time as forming the schottky electrode42in each diode trench14(seeFIG. 7J). As a result, the transistor11and the diodes (schottky barrier diodes10and pn diodes45) can be formed at the same time. Thus, it is possible to omit the process that would be necessary when the transistor11and the diodes were formed in different processes (such as a process of forming a protective film on the surface of the semiconductor layer22, and thereafter removing the protective film from the diode region after the source trenches13are formed). As described above, the diode trenches14and the p+region41for a diode can be formed by using the process for forming the transistor11(that is, a special process for forming the diodes is no longer needed), and therefore, it is possible to fabricate the semiconductor device1that has the transistor11and the schottky barrier diodes10on the same chip with a smaller number of manufacturing steps. As a result, the semiconductor device1can be manufactured at low cost.

As described above, when manufacturing the semiconductor device1, the interlayer insulating film48that becomes the first interlayer insulating film48A and the second interlayer insulating film48B is formed on the entire front surface22A of the semiconductor layer22(seeFIG. 7G), and next, the source trenches13and the diode trenches14are formed at the same time (seeFIG. 7H). It is possible to form the p+region41for a diode at the bottom of each diode trench14at the same time as forming the body contact region33at the bottom of each source trench13(seeFIG. 7I). At the side walls14B of the diode trench14, the schottky barrier diode10can be formed (seeFIG. 6). In this case, it is not necessary to remove the interlayer insulating film48. When forming the source trenches13and the diode trenches14, the first interlayer insulating film48A and the second interlayer insulating film48B can be formed in the same step (seeFIG. 7H), and therefore, it is possible to reduce the number of manufacturing steps. Because the first interlayer insulating film48A and the second interlayer insulating film48B are both left instead of being removed, it is possible to omit the step of removing these interlayer insulating films48.

In a plan view, the transistor forming region D surrounds the diode forming regions C (seeFIGS. 1 to 4). When the transistor11in the transistor forming region D is ON, the schottky barrier diode10in the diode forming region C is turned OFF, thereby making it possible to release heat from the semiconductor layer22through the diode forming region C. When the transistor11is OFF, it is possible to release heat from the semiconductor layer22through the transistor forming region D. This way, it is possible to prevent the temperature of the semiconductor device1from increasing. In particular, by forming the transistor forming region D so as to surround the diode forming regions C, heat from one region can be released through the other region, and therefore, it is possible to effectively mitigate an increase in temperature of the semiconductor device1. Also, because a plurality of diode forming regions C are dispersed so as to be distributed evenly with a prescribed gap therebetween, it is possible to more effectively mitigate an increase in temperature of the semiconductor device1.

FIG. 8is an illustrative cross-sectional view of a semiconductor device of another embodiment of the present invention.

Next, an embodiment differing from the embodiment above will be explained. In the embodiment below, parts corresponding to the parts described in the embodiment above are given the same reference characters, and detailed descriptions thereof are omitted. In the case ofFIG. 8, the transistor forming region D also surrounds the diode forming regions C in a plan view (seeFIGS. 1 and 2).

A transistor11(transistor cells11A) of a semiconductor device1shown inFIG. 8is a planar type MOSFET that has a different structure from that of the embodiment above, and does not have the gate trench12described above (seeFIG. 6). However, the semiconductor device1has the source trenches13and the diode trenches14.

The semiconductor device1shown inFIG. 8includes the semiconductor substrate20, the rear electrode21, the semiconductor layer22, the source electrodes28, and the conductive layer30, which were described above, and further includes a gate insulating film50, gate electrodes51, an insulating film52, and a metal film53.

The semiconductor substrate20is made of an n+semiconductor. The rear electrode21covers the entire rear surface (lower surface inFIG. 8) of the semiconductor substrate20, and forms an ohmic contact with the rear surface of the semiconductor substrate20.

The semiconductor layer22is deposited on the front surface (upper surface inFIG. 8) of the semiconductor substrate20by the epitaxial growth. The semiconductor layer22is made of an n−semiconductor that has a lower concentration than the semiconductor substrate20. In the semiconductor layer22ofFIG. 8, the upper surface will be referred to as a front surface22A and the lower surface will be referred to as a rear surface22B.FIG. 8shows a part of the semiconductor layer22near the boundary between the diode forming region C and the transistor forming region D. In the semiconductor layer22, a diode forming region corresponding to the diode forming region C, and a transistor region35corresponding to the transistor forming region D are defined.

In a surface portion of the semiconductor layer22in the transistor forming region D, p−body regions54are selectively formed. The plurality of body regions54are dispersed throughout the surface portion of the semiconductor layer22. In a surface portion of each body region54, an n+source region55is formed. A region of the semiconductor layer22in the transistor forming region D, except for the body regions54, is an n−drain region56. On the other hand, the semiconductor layer22in the diode forming region C is the abovementioned n-type region40for a diode, which is of an n−-type.

The surfaces of the source regions55, the surfaces of the body regions54where the source regions55are not formed, and the surface of the drain region56are flush with each other, forming the front surface22A of the semiconductor layer22in the transistor forming region D. At the front surface22A of the semiconductor layer22, source regions55and the drain region56are located on both sides of the respective body regions54, and are separated from each other with a gap (corresponding to the body region54between the source region55and the drain region56) therebetween along the front surface22A.

The gate insulating film50is made of SiO2, and covers portions of the front surface22A of the semiconductor layer22in the diode forming region C and the transistor forming region D. The gate insulating film50in the transistor forming region D is formed covering respective source regions55adjacent to each other with a gap therebetween at the front surface22A of the semiconductor layer22in the transistor forming region D.

The gate electrodes51are made of polysilicon, for example, and are formed on the gate insulating film50. Each gate electrode51faces through the gate insulating film50the surface of each body region54between the source region55and the drain region56.

The insulating film52is made of SiO2. The insulating film52covers the entire surface of each gate electrode51except for a portion thereof in contact with the gate insulating film50. The insulating film52is connected to the gate insulating film50.

The source trenches13are recessed from the front surface (upper surface inFIG. 8) of the insulating film52, and reach the inside of the drain region56, penetrating the insulating film52(between adjacent gate electrodes51), the gate insulating film50, and the source region55and the body region54in the semiconductor layer22. In the body region54and around the bottom of each source trench13in the drain region56, a p+body contact region58having a higher impurity concentration than the body region54is formed. The source electrode28is embedded in each source trench13.

The diode trenches14are recessed from the front surface of the insulating film52, and reach the inside of the n-type region for a diode in the semiconductor layer22. Near the bottom surface14A of each diode trench14in the n-type region for a diode (immediately below the bottom surface14A), a p+ region59for a diode is formed. The p+ region59for a diode forms a pn junction with the n-type region for a diode, which is of the n−-type.

As in the embodiment above, the source trenches13and the diode trenches14have the same depth (seeFIG. 6).

The metal film53includes a metal that forms a schottky junction by contacting n−silicon (such as titanium, molybdenum, palladium, or titanium nitride as described above). In the transistor forming region D, the metal film53covers the insulating film52and surfaces of the source electrodes28that are exposed from the source trenches13(upper surfaces inFIG. 8). In the diode forming region C, the metal film53covers the entire front surface (upper surface inFIG. 8) of the insulating film52, and is in contact with the entire inner surfaces of the diode trenches14(including the insulating film52and the gate insulating film50that are a part of the inner surfaces). In this state, the metal film53forms an ohmic contact with the p+region59for a diode, and forms a schottky junction with the n-type region for a diode at the side walls14B of each diode trench14. Portions of the metal film53that form a schottky junction with the n-type region for a diode constitute schottky electrodes70.

The conductive layer30is formed on the metal film53, and covers the entire front surface (upper surface inFIG. 8) of the metal film53. The conductive layer30is electrically connected to corresponding electrodes out of the plurality of external electrodes2mentioned above (seeFIGS. 1 and 2). The gate electrodes51are connected to other corresponding external electrodes2via not-shown relay wiring lines.

In the semiconductor device1, in the transistor forming region D, the conductive layer30, the metal film53, the source electrodes28, the body regions54, and the source regions55are electrically connected to each other. Also, in the transistor forming region D, the rear electrode21, the semiconductor substrate20, and a portion of the semiconductor layer22where the body region54or the source region55is not formed (drain region56) are electrically connected to each other.

This way, in the transistor forming region D, transistor cells11A are constructed individually. In the transistor cell11A, a parasitic diode is formed by the body region54and the drain region56.

For example, in a state where the conductive layer30is grounded, and a positive voltage is applied to the rear electrode21, a voltage equal to or greater than a threshold voltage is applied to the gate electrodes51. As a result, a channel is formed in each channel region X near the boundary between the body region54and the gate insulating film50, allowing an electric current to flow from the rear electrode21toward the conductive layer30via the channel.

In the diode forming region C, the rear electrode21forms an ohmic contact with the semiconductor substrate20, and the metal film53forms a schottky junction with the semiconductor layer22(n-type region for a diode), thereby constituting a schottky barrier diode10. The schottky barrier diode10and the transistor11are connected to each other in parallel. Also, in the diode forming region C, the p+ region59for a diode at the bottom surface14A of each diode trench14forms a pn junction with the n-type region for a diode, and with the pn junction between the p+ region59for a diode and the n-type region for a diode, the above-mentioned pn diode45is constituted. As described above, in one diode trench14, the pn diode45is formed at the bottom surface14A, and the schottky barrier diode10is formed at the side walls14B.

In each diode trench14in the diode forming region C, the schottky barrier diode10and the pn diode45are connected to each other in parallel. As described above, Vf of the schottky barrier diode10is lower than Vf of the pn diode45, and therefore, an electric current flows through the schottky barrier diode10before the pn diode45.

Also, as in the embodiment above (seeFIG. 6), in a reverse bias state, a depletion layer80spreads from the pn diode45at the bottom of each diode trench14, and respective depletion layers80at the bottom of adjacent diode trenches14are connected to each other.

The configuration of the semiconductor device1ofFIG. 6may be appropriately applied to the semiconductor device1ofFIG. 8, and in such a case, it is possible to attain effects similar to those of the semiconductor device1ofFIG. 6.

FIG. 9is a perspective view that schematically shows a semiconductor package according to an embodiment of the present invention.

As shown inFIG. 9, a semiconductor package60includes any one of the above-mentioned semiconductor devices1, a lead frame61made of a metal, and a resin package65.

The semiconductor device1is bonded to the lead frame61. The lead frame61includes a die pad62in a rectangular plate shape, leads63A disposed along one side of the die pad62with a gap therebetween, and leads63B extending from another side of the die pad62. The lead frame61has a plurality of leads63A and a plurality of leads63B (four each in this example).

In the semiconductor device1, the rear electrode21(seeFIGS. 6 and 8) is bonded to the upper surface of the die pad62, and each lead63A is connected to a corresponding external electrode2on the surface of the semiconductor device1through a bonding wire64. This way, the leads63A and63B are electrically connected to the schottky barrier diodes10, the pn diodes45, and the transistors11in the semiconductor device1(seeFIGS. 1 and 2). InFIG. 9, the rightmost external electrode2is connected to the gate electrode24, and other external electrodes2are connected to the source electrode28(see alsoFIG. 6). In this case, the rightmost lead63A inFIG. 9is a lead for the gate, and the other three leads63A are leads for the source. All of the leads63B are leads for the drain.

The semiconductor device1and the lead frame61bonded to each other are covered by the resin package65such that the respective leads63A and leads63B are exposed to the outside. The semiconductor package60can be connected (mounted) to a mounting wiring substrate (not shown) by having the respective leads63A and63B face the mounting wiring substrate.

FIG. 10is a circuit diagram of a DC-DC converter that uses the semiconductor device of the present invention.

In a DC-DC converter100shown inFIG. 10, a control part (IC)91is connected to a high side transistor92and a low side transistor93, and the semiconductor device1of the present invention can be used for the low side transistor93. In this case, the transistor11of the semiconductor device1is used as the low side transistor93, and the schottky barrier diode10connects the high side transistor92to the low side transistor93.

In addition to the above-mentioned, the present invention can be implemented in various embodiments, and various design changes can be made without departing from the scope specified by claims.

FIG. 11is a diagram showing a modification example of the main part of the semiconductor device ofFIG. 3.

Each of the diode trenches14described above extends as a straight line over the entire region of the diode forming region C, for example (seeFIGS. 3 and 4), but as shown inFIG. 11, the diode trench14may be divided into a plurality of parts on the same line extending along the second direction X. In this case also, as in the embodiment above, in a plan view, each diode trench14is formed in a rectangular shape that is longer in the second direction X. The source trenches13are formed in a linear shape along the first direction Y at the front surface22A of the semiconductor layer22as in the embodiment above, and two parallel sides (sides extending along the second direction X) H of each diode trench14that is rectangular in a plan view are orthogonal to the lengthwise direction (first direction Y) of the source trench13.

In the above embodiments, the pn diode45was formed at the bottom surface14A of each diode trench14(seeFIGS. 6 and 8), but by omitting the ion implantation on the diode trenches14(seeFIG. 7I), the schottky barrier diode10may be formed not only at the side walls14B of the diode trench14, but also at the bottom surface14A.

In the above embodiments, the first conductive type was n-type, and the second conductive type was p-type, but conversely, the first conductive type may be p-type, and the second conductive type may be n-type.

The thickness of the first interlayer insulating film48A and the thickness of the second interlayer insulating film48B may differ from each other. The depths of the gate trenches12, the source trenches13, and the diode trenches14may be changed appropriately. It is preferable that the source trenches13and the diode trenches14be orthogonal to each other in a plan view, but the intersection angle of these trenches does not necessarily have to be 90°.

It will be apparent to those skilled in the art that various modification and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover modifications and variations that come within the scope of the appended claims and their equivalents. In particular, it is explicitly contemplated that any part or whole of any two or more of the embodiments and their modifications described above can be combined and regarded within the scope of the present invention.