STACKED TRANSISTORS HAVING AN ISOLATION REGION THEREBETWEEN AND A COMMON GATE ELECTRODE, AND RELATED FABRICATION METHODS

Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

FIELD

The present disclosure generally relates to the field of semiconductor devices and, more particularly, to three-dimensional transistor structures.

BACKGROUND

The density of transistors in electronic devices has continued to increase. Though three-dimensional transistor structures can help to increase transistor density, they may experience electrical vulnerabilities, such as parasitic capacitance. For example, parasitic capacitance between a contact metal and a gate metal of a three-dimensional transistor structure can reduce device performance.

Moreover, it may be difficult to form inner spacers for three-dimensional transistor structures. And the deposition and removal of gate metal for three-dimensional transistor structures may be complicated and difficult to control.

SUMMARY

A transistor device, according to some embodiments herein, may include a substrate. The transistor device may include a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device may include an upper transistor having an upper gate and an upper channel region. The lower transistor may be between the upper transistor and the substrate. The transistor device includes an isolation region that may separate the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor may contacts the upper gate of the upper transistor.

A transistor device, according to some embodiments, may include a lower nanosheet transistor having a lower nanosheet stack and a lower gate on the lower nanosheet stack. The transistor device may include an upper nanosheet transistor on top of the lower nanosheet transistor. The upper nanosheet transistor may include an upper nanosheet stack and an upper gate on the upper nanosheet stack. The transistor device may include an isolation region that separates the lower nanosheet stack from the upper nanosheet stack. Moreover, the lower gate of the lower nanosheet transistor may contacts the upper gate of the upper nanosheet transistor.

A method of forming a transistor device, according to some embodiments, may include forming a preliminary transistor stack including a lower channel layer, an upper channel layer, and a sacrificial layer that separates the lower channel layer from the upper channel layer. The method may include forming insulating spacers between the lower channel layer and the upper channel layer. The method may include removing the sacrificial layer. The method may include forming an isolation layer in an opening formed by removing the sacrificial layer. The method may include forming a lower gate on the lower channel layer below the isolation layer and an upper gate on the upper channel layer above the isolation layer. Moreover, the upper gate may contact the lower gate.

DETAILED DESCRIPTION

Pursuant to embodiments of the present invention, transistor devices comprising a common gate and an isolation region that separates a lower channel region of a lower transistor from an upper channel region of an upper transistor are provided. Forming inner spacers for three-dimensional transistor structures may have a process restriction due to an undefined border between upper and lower transistors. For example, inner spacers may have incomplete pinchoff (e.g., removal/separation) between the upper and lower transistors. And the deposition and removal of gate metal in the middle of upper and lower devices may be restricted by vertical spaces between them and gate length, and those processes may be complicated and difficult to control.

Transistor devices and methods of forming the same pursuant to embodiments of the present invention, however, can address these issues by forming a sacrificial layer that defines a border between the upper and lower transistors. The defined border provided by the sacrificial layer can improve control of subsequent formation of inner spacers. Moreover, the sacrificial layer is subsequently replaced with an isolation layer that is part of an isolation region that will be inside a common gate for the upper and lower transistors. Forming the isolation layer inside a region where the common gate will be formed helps to control the amount and location of gate metal that is formed in the region.

Example embodiments of the present invention will be described in greater detail with reference to the attached figures.

FIGS.1A-1Dprovide views of transistor devices according to various embodiments, viewed along different axes.FIG.1Ais a plan view of a nanosheet transistor device100according to some embodiments of the present invention. The device100includes first and second transistor stacks110-1,110-2. For simplicity of illustration, only two transistor stacks110are shown inFIG.1A. In some embodiments, however, the device100may include three, four, or more transistor stacks110. For example, the two transistor stacks110-1,110-2may be a pair of transistor stacks110that are closer to each other than to any other transistor stack110in the device100.

The first transistor stack110-1includes a first nanosheet stack120-1that is between a pair of source/drain regions150-1in a first horizontal direction X. The first nanosheet stack120-1includes upper and lower nanosheets NS-U and NS-L (FIG.1B) and upper and lower gate portions G-U and G-L (FIG.1B) that are on the nanosheets NS. Though the nanosheets NS may contact the source/drain regions150-1, the gate portions G-U and G-L may be spaced apart from the source drain regions150-1in the direction X by upper and lower insulating spacers IS-U and IS-L (FIG.1C), which may be referred to herein as “inner spacers.”

Each source/drain region150-1may have a respective source/drain contact140-1adjacent thereto in a second horizontal direction Y, which may be perpendicular to the direction X. Accordingly, a pair of source/drain contacts140-1can be on opposite sides of the first nanosheet stack120-1. Each source/drain contact140-1may comprise, for example, metal.

To reduce parasitic capacitance with the source/drain contacts140-1, an insulation region160of the transistor stack110-1is provided adjacent (e.g., aligned/overlapping in the direction X with) the source/drain contact(s)140-1. The region160may also reduce parasitic capacitance with both source/drain regions150-1. Likewise, a second nanosheet stack120-2of the second transistor stack110-2is between a pair of source/drain regions150-2, and the transistor stack110-2has an insulation region160that is adjacent a source/drain contact140-2.

FIG.1Bis a cross-sectional view, taken along the direction Y, of the first transistor stack110-1of the nanosheet transistor device100ofFIG.1A. As shown inFIG.1B, the nanosheet stack120-1of the first transistor stack110-1includes a plurality of lower nanosheets NS-L of a lower transistor T-L and a plurality of upper nanosheets NS-U of an upper transistor T-U. The upper nanosheets NS-U overlap the lower nanosheets NS-L in a vertical direction Z that is perpendicular to the horizontal directions X and Y.

The lower transistor T-L further includes a lower gate G-L that is on the lower nanosheets NS-L. In the cross-sectional view ofFIG.1B, the lower gate G-L is shown on four sides of each of the lower nanosheets NS-L. The upper transistor T-U, on the other hand, further includes an upper gate G-U that is on three sides of each of the upper nanosheets NS-U in the cross-sectional view ofFIG.1B, and an insulation region160is on a fourth side of each of the upper nanosheets NS-U. Accordingly, the transistors T-L, T-U shown inFIG.1Bare a gate-all-around (“GAA”) transistor GA and a tri-gate nanosheet transistor TG, respectively.

The insulation region160may contact respective sidewalls of the upper nanosheets NS-U and may vertically overlap the lower nanosheets NS-L. The insulation region160may comprise, for example, silicon nitride or silicon oxide. In some embodiments, the insulation region160may comprise a low-k spacer, which can provide better capacitance-reduction than a higher-k insulator. As used herein, the term “low-k” refers to a material that has a smaller dielectric constant than silicon dioxide.

An isolation region IL separates the lower nanosheets NS-L from the upper nanosheets NS-U. The isolation region IL may comprise, for example, an oxide material. The insulation region160may be on an upper surface of the isolation region IL. As an example, a length of the isolation region IL in the direction Y may be equal to a combined length of the upper nanosheets NS-U and the insulation region160in the direction Y and/or equal to lengths of the lower nanosheets NS-L in the direction Y. In some embodiments, the upper gate G-U may be on opposite sidewalls of the isolation region IL. The isolation region IL may thus be inside the upper gate G-U. In other embodiments, the isolation region IL may be inside the lower gate G-L. In some embodiments, the isolation region IL may be between the upper gate G-U and the lower gate G-L.

The gates G-L, G-U may contact each other and thus may collectively provide a common gate electrode that is shared by the transistors T-L, T-U. For example,FIG.1Bshows that a lower surface of the upper gate G-U may contact an upper surface of the lower gate G-L. Moreover, each transistor stack110(FIG.1A) may, in some embodiments, be a complementary field-effect transistor (“CFET”) stack in which the lower transistor T-L and the upper transistor T-U are N-type and P-type transistors, respectively, or vice versa. Accordingly, the gates G-L, G-U may comprise different respective metals. As an example, the different metals may have different respective work functions.

Though the transistors T-L, T-U are shown inFIG.1Bas nanosheet transistors, at least one of the transistors T-L, T-U may, in some embodiments, be a vertical field-effect transistor (“VFET”) or a fin field-effect transistor (“FinFET”). For example, the lower transistor T-L may be a nanosheet transistor as shown inFIG.1B, and the upper transistor T-U may be a VFET or FinFET that may have a single channel region rather than the plurality of upper nanosheets NS-U that are shown inFIG.1B. Accordingly, the present invention is not limited to transistors that have a plurality of nanosheets NS.

The transistors T-L, T-U may be stacked on a substrate101such that the lower transistor T-L is between the upper transistor T-U and the substrate101. The substrate101may be, for example, a semiconductor substrate. In some embodiments, portions of the substrate101on opposite sides of the transistors T-L, T-U may be recessed and filled with an insulating material to provide trench isolation regions102.

According to some embodiments, an upper metal layer M-U may be on the upper gate G-U, and a lower metal layer M-L may be on the lower gate G-L. For example, each of the metal layers M-U, M-L may comprise tungsten. Portions of the metal layers M-U, M-L may vertically overlap the trench isolation regions102.

FIG.1Balso illustrates that the upper nanosheets NS-U may each have a width in the direction Y that is different from a width in the direction Y of each of the lower nanosheets NS-L. Specifically, due to the insulation region160, the width of the upper nanosheets NS-U may be narrower than the width of the lower nanosheets NS-L. The nanosheet stack120-1may thus represent a stepped nanosheet (“sNS”) structure. Example sNS structures are discussed in U.S. Provisional Patent Application Ser. No. 63/086,781, filed on Oct. 2, 2020, the disclosure of which is hereby incorporated herein in its entirety by reference.

Due to its wider nanosheet NS width, the lower transistor T-L can have fewer (e.g., two versus three) nanosheets NS than the upper transistor T-U, while still having the same total nanosheet NS cross-sectional area (and/or the same total nanosheet NS surface area) as the upper transistor T-U. Moreover, for simplicity of illustration, a gate insulation layer is omitted from view inFIG.1B. It will be understood, however, that a gate insulation layer may extend between each nanosheet NS and the gate G. For example, a gate insulation layer may be between each upper nanosheet NS-U and the upper gate G-U, and may be between each lower nanosheet NS-L and the lower gate G-L. The gate insulation layer may wrap around each nanosheet NS and may be thinner than the isolation region IL.

FIG.1Cis a cross-sectional view, taken along the direction X, of the first transistor stack110-1ofFIG.1Aaccording to some embodiments of the present invention. As shown inFIG.1C, the stack110-1may comprise upper source/drain regions150-U on sidewalls of the upper nanosheets NS-U, and lower source/drain regions150-L on sidewalls of the lower nanosheets NS-L. Each upper nanosheet NS-U may provide an upper channel region CH-U between the upper source/drain regions150-U. Likewise, each lower nanosheet NS-L may provide a lower channel region CH-L between the lower source/drain regions150-L. Upper insulating spacers IS-U may be on sidewalls of the upper gate G-U between the upper nanosheets NS-U. Similarly, lower insulating spacers IS-L may be on sidewalls of the lower gate G-L between the lower nanosheets NS-L. The isolation region IL may separate the lower nanosheets NS-L from the upper nanosheets NS-U, as well as the lower insulating spacers IS-L from the upper insulating spacers IS-U and the lower source/drain regions150-L from the upper source/drain regions150-U.

In some embodiments, the isolation region IL may have a non-uniform thickness in the direction Z. For example, the isolation region IL may have a first thickness T1that separates the lower source/drain regions150-L from the upper source/drain regions150-U. Moreover, the isolation region IL may have a second thickness T2between an uppermost one of the lower insulating spacers IS-L (and/or the lower gate G-L) and a lowermost one of the upper insulating spacers IS-U (and/or the upper gate G-U). The second thickness T2may be thinner than the first thickness T1. Moreover, the uppermost one of the lower insulating spacers IS-L may contact a lower portion (e.g., a lower surface and a side surface) of the isolation region IL, and the lowermost one of the upper insulating spacers IS-U may contact an upper portion (e.g., an upper surface and a side surface) of the isolation region IL.

As shown in the cross-sectional view inFIG.1C, the lower gate G-L may, in some embodiments, be wider, in the direction X, than the upper gate G-U. The lower insulating spacers IS-L may thus be spaced farther apart from each other, in the direction X, than the upper insulating spacers IS-U.

Referring still toFIG.1C, an upper isolation region UI may be on top of the upper source/drain regions150-U. The upper isolation region UI may comprise, for example, an oxide material. In some embodiments, the upper isolation region UI and the isolation region IL may comprise the same oxide material.

FIG.1Dis a cross-sectional view, taken along the direction X, of a modified first transistor stack110-1′ corresponding to the stack110-1ofFIG.1Aaccording to other embodiments of the present invention. The modified stack110-1′ ofFIG.1Ddiffers from the stack110-1ofFIG.1C, in that an isolation region IL of the modified stack110-1′ has a uniform thickness T2. Accordingly, the isolation region IL ofFIG.1Dseparates the lower source/drain regions150-L from the upper source/drain regions150-U by the same distance that it separates the lower gate G-L from the upper gate G-U. As a result, a bonding process can be used to bond the lower transistor T-L to the upper transistor T-U. The stack110-1shown inFIG.1C, on the other hand, can be implemented without using a bonding process.

FIGS.2A-2ANare cross-sectional views illustrating operations of forming the transistor stack110-1ofFIGS.1B and1C. Referring toFIG.2A, a plurality of sacrificial layers SL may alternate with a plurality of preliminary nanosheets NS-P in a vertical stack. The sacrificial layers SL may comprise, for example, silicon germanium (“SiGe”), and the preliminary nanosheets NS-P may each be, for example, a silicon (“Si”) sheet. In some embodiments, the sacrificial layers SL and/or the preliminary nanosheets NS-P may be epitaxially grown on a substrate101, which may comprise Si. Upper ones of the preliminary nanosheets NS-P may be referred to herein as “upper channel layers,” and lower ones of the preliminary nanosheets NS-P may be referred to herein as “lower channel layers,” as the preliminary nanosheets NS-P will be etched to form nanosheets NS that function as respective channel regions. Moreover, the sacrificial layers SL and the preliminary nanosheets NS-P may collectively be referred to herein as a “preliminary transistor stack.”

The preliminary transistor stack also includes a sacrificial layer RL that separates upper ones of the preliminary nanosheets NS-P from lower ones of the preliminary nanosheets NS-P. In some embodiments, the sacrificial layer RL and the preliminary nanosheets NS-P may be epitaxially grown. Ones of the sacrificial layers SL that are above the sacrificial layer RL are upper sacrificial layers SL-U, and ones of the sacrificial layers SL that are below the sacrificial layer RL are lower sacrificial layers SL-L. The upper ones of the preliminary nanosheets NS-P alternate with the upper sacrificial layers SL-U, and the lower ones of the preliminary nanosheets NS-P alternate with the lower sacrificial layers SL-L. Moreover, the sacrificial layer RL may contact a lowermost one of the upper sacrificial layers SL-U and an uppermost one of the lower sacrificial layers SL-L. The sacrificial layer RL may also be referred to herein as a “replacement isolation dummy layer,” as it will be replaced with an isolation layer228(FIG.2V) that is part of the isolation region IL (FIG.1B).

The sacrificial layer RL may comprise a first sacrificial material that has etch selectivity with respect to a second sacrificial material of the sacrificial layers SL (and with respect to the preliminary nanosheets NS-P). For example, the sacrificial layer RL may comprise Si, which has etch selectivity with respect to SiGe of the sacrificial layers SL, and which can be grown on the SiGe. As another example, the sacrificial layer RL may comprise SiGe having a first concentration of Ge, and the sacrificial layers SL may comprise SiGe having a second concentration of Ge, where the first concentration is higher than the second concentration. Accordingly, high-Ge SiGe can be used for the sacrificial layer RL if it has etch selectivity with respect to SiGe of the sacrificial layers SL. Moreover, the sacrificial layer RL may be thicker than each of the sacrificial layers SL.

Insulating layers203-205may be in a stack on top of the preliminary nanosheets NS-P and the sacrificial layers SL. For example, the insulating layers203,205may each comprise an oxide material, and the insulating layer204may comprise silicon nitride (“SiN”). Moreover, a hardmask layer206may be deposited on top of the insulating layers203-205. As an example, the hardmask layer206may comprise Si.

Referring toFIG.2B, a mask layer207may be formed on the hardmask layer206. The mask layer207may be patterned to be narrower than the hardmask layer206.

Referring toFIG.2C, recess regions208,209may be formed in the preliminary transistor stack by using the mask layer207and the hardmask layer206as an etch mask. After forming the recess regions208,209, the mask layer207and the hardmask layer206may be removed.

Referring toFIG.2D, dielectric regions210may be formed in the recess regions208,209and may be planarized (e.g., using chemical mechanical planarization (“CMP”)) to have upper surfaces that are coplanar with an upper surface of the insulating material204.

Referring toFIG.2E, a mask layer211may be formed on top of the preliminary transistor stack. The mask layer211may be patterned to vertically overlap a portion (e.g., one half) of the preliminary transistor stack.

Referring toFIG.2F, a recess region201may be formed in the preliminary transistor stack by using the mask layer211as an etch mask. As a result, the upper sacrificial layers SL-U and the upper ones of the preliminary nanosheets NS-P are etched to narrow the width thereof, thus exposing a portion of an upper surface of the sacrificial layer RL. For example, the recess region201may extend into (but not completely through) the sacrificial layer RL.

Referring toFIG.2G, an insulating layer212may be formed in the recess region201and planarized (e.g., using CMP). The insulating layer212may comprise, for example, SiN.

Referring toFIG.2H, the dielectric regions210may be recessed until they are below a level of the lowermost preliminary nanosheet NS-P. For example, the dielectric regions210may be recessed to have upper surfaces that are coplanar with an upper surface of the substrate101.

Referring toFIG.2I, which is a cross-sectional view taken along the direction Y, the insulating layer212may be patterned to form the insulation (e.g., dielectric) region160. Moreover, a spacer layer213may be deposited on the insulation region160, the preliminary transistor stack, and the trench isolation regions102. Also, a sacrificial material214may be formed on the spacer layer213, and a hardmask layer215may be formed on the sacrificial material214. The sacrificial material214may comprise, for example, polysilicon.

Referring toFIG.2J, which is a cross-sectional view taken along the direction X, the hardmask layer215may have spacers216on sidewalls thereof.

Referring toFIG.2K, which is a cross-sectional view taken along the direction X, the preliminary transistor stack is recessed to about the depth of the sacrificial layer RL by using the hardmask layer215and spacers216as an etch mask. As a result, the width of the upper ones of the preliminary nanosheets NS-P is narrowed, thus forming upper nanosheets NS-U. The width of the upper sacrificial layers SL-U is also narrowed, thus forming recess regions217,218alongside the upper sacrificial layers SL-U and the upper nanosheets NS-U. While forming the recess regions217,218, the sacrificial layer RL may be partially recessed, without etching completely through the sacrificial layer RL to the uppermost one of the lower sacrificial layers SL-L thereunder.

Referring toFIG.2L, which is a cross-sectional view taken along the direction X, sidewalls of the upper sacrificial layers SL-U are recessed to form recess regions219,220between the upper nanosheets NS-U, as well as between the sacrificial layer RL and a lowermost one of the upper nanosheets NS-U, and between an uppermost one of the upper nanosheets NS-U and the sacrificial material214. For example, the recess regions219,220may be formed by performing a low-Ge SiGe etch-back for the upper sacrificial layers SL-U.

Referring toFIG.2M, which is a cross-sectional view taken along the direction X, upper insulating spacers IS-U are formed in the recess regions219,220. As a result, the upper insulating spacers IS-U are on sidewalls of the upper sacrificial layers SL-U. The upper insulating spacers IS-U are (i) between the upper nanosheets NS-U, (ii) between the sacrificial layer RL and a lowermost one of the upper nanosheets NS-U, and (ii) between an uppermost one of the upper nanosheets NS-U and the sacrificial material214. The upper insulating spacers IS-U may be formed by, for example, performing a SiN deposition and etch-back.

Referring toFIG.2N, which is a cross-sectional view taken along the direction X, spacers221are deposited on sidewalls of the upper insulating spacers IS-U and on sidewalls of the spacers216. For example, the spacers221may extend continuously from sidewalls of the sacrificial layer RL to upper portions of the spacers216.

Referring toFIG.2O, which is a cross-sectional view taken along the direction X, lower side regions of the preliminary transistor stack are recessed while using the spacers216,221and the hardmask layer215as an etch mask to protect the upper nanosheets NS-U and the upper insulating spacers IS-U. As a result, the lower ones of the preliminary nanosheets NS-P are narrowed to form lower nanosheets NS-L and recess regions222,223that are adjacent the lower nanosheets NS-L. The lower sacrificial layers SL-L are also narrowed, as is a lower portion of the sacrificial layer RL.

Referring toFIG.2P, which is a cross-sectional view taken along the direction X, sidewalls of the lower sacrificial layers SL-L are recessed to form recess regions224,225between the lower nanosheets NS-L, as well as between the sacrificial layer RL and an uppermost one of the lower nanosheets NS-L therebelow, and between a lowermost one of the lower nanosheets NS-L and the substrate101. For example, the recess regions224,225may be formed by performing a SiGe etch-back for the lower sacrificial layers SL-L.

Referring toFIG.2Q, which is a cross-sectional view taken along the direction X, lower insulating spacers IS-L are formed in the recess regions224,225. As a result, the lower insulating spacers IS-L are on sidewalls of the lower sacrificial layers SL-L. The lower insulating spacers IS-L are (i) between the lower nanosheets NS-L, (ii) between the sacrificial layer RL and an uppermost one of the lower nanosheets NS-L therebelow, and (ii) between a lowermost one of the lower nanosheets NS-L and the substrate101. The lower insulating spacers IS-L may be formed by, for example, performing a SiN deposition and etch-back.

Referring toFIG.2R, which is a cross-sectional view taken along the direction X, an oxide material226is deposited in the recess regions222,223(FIG.2O) and is planarized (e.g., using CMP).

Referring toFIG.2S, which is a cross-sectional view taken along the direction X, the oxide material226is recessed to a level below the sacrificial layer RL. Accordingly, lower sidewalls of the sacrificial layer RL are exposed.

Referring toFIG.2T, which is a cross-sectional view taken along the direction Y, the sacrificial layer RL is removed, thereby forming an opening227between the upper nanosheets NS-U and the lower nanosheets NS-L.

Referring toFIG.2U, which is a cross-sectional view taken along the direction X, the opening227includes a gap between the spacers221and an uppermost pair of the lower insulating spacers IS-L. Moreover, the opening227is thicker than each of the two sacrificial layers SL that are between the upper nanosheets NS-U and the lower nanosheets NS-L.

Referring toFIG.2V, which is a cross-sectional view taken along the direction Y, an isolation layer228is formed in the opening227.

Referring toFIG.2W, which is a cross-sectional view taken along the direction X, the isolation layer228may also be formed on top of the oxide material226. The isolation layer228may comprise, for example, an oxide material that fills openings and then is planarized (e.g., using CMP).

Referring toFIG.2X, which is a cross-sectional view taken along the direction X, the isolation layer228is recessed while using the spacers216,221and the hardmask layer215as an etch mask to protect a portion of the isolation layer228that separates the upper nanosheets NS-U from the lower nanosheets NS-L. Accordingly, this recess operation removes portions of the isolation layer228that are on top of the oxide material226. The recess operation may also remove the oxide material226.

Referring toFIG.2Y, which is a cross-sectional view taken along the direction X, lower source/drain regions150-L are formed on the substrate101and on sidewalls of the lower nanosheets NS-L. An insulating material229is deposited on top of the lower source/drain regions150-L at a level of the isolation layer228(FIG.2X). The insulating material229may comprise, for example, an oxide material, and may, together with the isolation layer228, provide the isolation region IL. As an example, sidewalls of the insulating material229and sidewalls of the isolation layer228may contact each other and may comprise the same insulating material. In some embodiments, the isolation region IL may be thicker, in the vertical direction Z, than each of the nanosheets NS (and thus thicker than each channel region CH (FIG.1C) provided thereby).

Upper source/drain regions150-U are formed on sidewalls of the upper nanosheets NS-U. For example, the upper source/drain regions150-U and the lower source/drain regions150-L may be formed by epitaxial growth. Moreover, an oxide material230is deposited on top of the upper source/drain regions150-U.

Referring toFIG.2Z, which is a cross-sectional view taken along the direction Y, the hardmask layer215is removed, such as by performing a poly-open CMP.

Referring toFIG.2AA, which is a cross-sectional view taken along the direction X, the removal of the hardmask layer215exposes an upper surface of the sacrificial material214. Upper portions of the spacers216may also be removed.

Referring toFIG.2AB, which is a cross-sectional view taken along the direction Y, a poly removal operation may be performed to remove the sacrificial material214. As a result, recess regions231,232are formed and the spacer layer213is exposed.

Referring toFIG.2AC, which is a cross-sectional view taken along the direction X, the poly removal operation that forms the recess regions231,232(FIG.2AB) also forms an opening233between the spacers216. The poly removal operation also removes at least a portion of the spacer layer213. As an example,FIG.2ACshows that the poly removal operation removes a portion of the spacer layer213that is on an uppermost one of the upper sacrificial layers SL-U, thereby exposing an upper surface of the uppermost one of the upper sacrificial layers SL-U.

Referring toFIG.2AD, which is a cross-sectional view taken along the direction Y, the sacrificial layers SL are removed. For example, a SiGe removal operation may remove the sacrificial layers SL.

Referring toFIG.2AE, which is a cross-sectional view taken along the direction X, the removal of the sacrificial layers SL provides openings between respective pairs of the insulating spacers IS.

Referring toFIG.2AF, which is a cross-sectional view taken along the direction Y, a first metal material234is deposited on the nanosheets NS.

Referring toFIG.2AG, which is a cross-sectional view taken along the direction X, the first metal material234is formed in the openings between the respective pairs of the insulating spacers IS. For example, each insulating spacer IS may contact the first metal material234. Moreover, an opening235may be between sidewalls of an upper portion of the first metal material234that is between the spacers216.

Referring toFIG.2AH, which is a cross-sectional view taken along the direction Y, a second metal material236is deposited on the first metal material234. The second metal material236is then planarized (e.g., using CMP) and recessed (e.g., using chamfering) until the second metal material236remains on lower portions of the recess regions231,232(FIG.2AF) adjacent the lower nanosheets NS-L. As an example, an upper surface of the remaining second metal material236may be at a level of a lower surface of the isolation region IL. The second metal material236may comprise, for example, tungsten (“W”), which may be different from the first metal material234.

Referring toFIG.2AI, which is a cross-sectional view taken along the direction Y, the first metal material234may be removed above a level of the upper surface of the second metal material236. For example, the second metal material236may be used as an etch-stop layer when removing upper portions of the first metal material234. As a result, sidewalls of the isolation region IL may be exposed.

In some embodiments, the removal of the upper portions of the first metal material234can be performed using a wet etch that has selectivity between the first and the second metal materials234,236. As an example, the wet etch may comprise a chamfering process that stops at the second metal material236. Moreover, a result (e.g., a lowest etching depth) of the wet etch may vary based on the thickness of the first metal material234.

Referring toFIG.2AJ, which is a cross-sectional view taken along the direction X, the removal of upper portions of the first metal material234includes removing the first metal material234from sidewalls of the upper insulating spacers IS-U. As a result, openings237are formed between respective pairs of the upper insulating spacers IS-U. A recess region238is also formed between the spacers216. Moreover, remaining portions of the first metal material234provide a lower gate G-U on the lower nanosheets NS-L. Accordingly, the first metal material234is a lower gate metal.

Referring toFIG.2AK, which is a cross-sectional view taken along the direction Y, a third gate material is deposited on the upper nanosheets NS-U to provide an upper gate G-U. Accordingly, the third metal material is an upper gate metal, which may comprise a different material from the first and second metal materials234,236. In some embodiments, the upper gate G-U may also be formed on (e.g., in contact with) exposed sidewalls of the isolation region IL. In other embodiments, the lower gate G-L may be formed on (e.g., in contact with) the sidewalls of the isolation region IL. Accordingly, the isolation region IL may be inside either the upper gate G-U or the lower gate G-L. In some embodiments, the isolation region IL may be between the upper gate G-U and the lower gate G-L. Moreover, openings240,241may be on opposite sides of the upper gate G-U.

Referring toFIG.2AL, which is a cross-sectional view taken along the direction X, the formation of the upper gate G-U includes forming the upper gate G-U in the openings237(FIG.2AJ). As a result, the upper gate G-U may contact sidewalls of the upper insulating spacers IS-U. Moreover, an opening239may be between sidewalls of an upper portion of the upper gate G-U that is between the spacers216.

Referring toFIG.2AM, which is a cross-sectional view taken along the direction Y, a fourth metal material242is deposited on the upper gate G-U and in the openings240,241(FIG.2AK). The fourth metal material242is then planarized (e.g., using CMP). In some embodiments, the fourth metal material242may comprise the same material as the second metal material236. For example, the second and fourth metal materials236,242may each comprise W.

Referring toFIG.2AN, which is a cross-sectional view taken along the direction X, the formation of the fourth metal material242may include forming the fourth metal material242in the opening239(FIG.2AL) between the spacers216.

FIGS.3A-3Eare flowcharts illustrating operations of forming the transistor stack110-1ofFIGS.1B and1C. These operations correspond to operations shown in the cross-sectional views ofFIGS.2A-2AN. As shown inFIG.3A, the operations include forming (Block310) a preliminary transistor stack. Referring again toFIG.2A, the preliminary transistor stack may include preliminary nanosheets NS-P and a sacrificial layer RL that separates lower ones of the preliminary nanosheets NS-P from upper ones of the preliminary nanosheets NS-P. The preliminary transistor stack may also include sacrificial layers SL that alternate with the preliminary nanosheets NS-P.

The operations include forming (Block320) insulating spacers IS on sidewalls of the preliminary transistor stack. For example,FIGS.2M and2Qillustrate forming upper insulating spacers IS-U and lower insulating spacers IS-L, respectively.

The operations include removing (Block330) the sacrificial layer RL after forming the insulating spacers IS. As an example,FIGS.2S-2Uillustrates removing the sacrificial layer RL to form an opening227.

The operations include forming (Block340) an isolation layer228in the opening227. As shown inFIG.2X, the isolation layer228is part of the isolation region IL.

Moreover, the operations include forming (Block350) a common gate G, which may comprise a lower gate G-L and an upper gate G-U that contacts the lower gate G-L. For example, the lower gate G-L may be formed on lower nanosheets NS-L, as shown inFIG.2AI, and the upper gate G-U may be formed on upper nanosheets NS-U, as shown inFIG.2AK. Alternatively, the upper gate G-U and the lower gate G-L may be formed to be isolated from each other, such as by having the isolation region IL extend therebetween.

Though the cross-sectional views shown inFIGS.1B,1C, and2A-2ANshow transistors T that each include multiple nanosheets NS, the operations ofFIG.3Aare not limited to forming such transistors T. Rather, a transistor T formed by the operations ofFIG.3Amay comprise either multiple channel layers or a single channel layer. Accordingly, in a transistor stack110, a lower transistor T-L may include either multiple lower channel layers or a single lower channel layer, and an upper transistor T-U may include either multiple upper channel layers or a single upper channel layer. Each channel layer may comprise a semiconductor layer. In some embodiments, the semiconductor layer is provided by a nanosheet NS. In other embodiments, however, the semiconductor layer is not provided by a nanosheet NS.

Referring toFIG.3B, operations of forming (Block320ofFIG.3A) insulating spacers IS may include forming (Block320-A) upper insulating spacers IS-U (FIG.2M) on sidewalls of upper sacrificial layers SL-U and subsequently forming (Block320-B) lower insulating spacers IS-L (FIG.2Q) on sidewalls of lower sacrificial layers SL-L.

Referring toFIG.3C, operations of forming (Block350ofFIG.3A) the common gate G may include replacing (Block350-A) the lower sacrificial layers SL-L with a lower gate G-L (FIG.2AI) and subsequently replacing (Block350-B) the upper sacrificial layers SL-U with an upper gate G-U (FIG.2AK).

Referring toFIG.3D, operations of replacing (Blocks350-A,350-B ofFIG.3C) the sacrificial layers SL may include forming (Block350-A1) the lower gate G-L below isolation region IL (FIG.2AI) and subsequently forming (Block350-B1) the upper gate G-U above, and on opposite sidewalls of, the isolation region IL. Accordingly, the isolation region IL may, in some embodiments, be inside the upper gate G-U, as shown inFIG.2AK.

According to other embodiments, the isolation region IL may be inside the lower gate G-L. For example, referring toFIG.3E, operations of replacing (Blocks350-A,350-B ofFIG.3C) the sacrificial layers SL may include forming (Block350-A2) the lower gate G-L below, and on opposite sidewalls of, the isolation region IL and subsequently forming (Block350-B2) the upper gate G-U above the isolation region IL.

FIGS.4A-4Pare perspective views illustrating operations of further embodiments of forming a transistor stack. The resultant transistor stack may be similar to that which is formed by the operations ofFIGS.2A-2AN. For example, the operations ofFIGS.4A-4Pmay be used to form any of the transistor stacks shown inFIGS.1A-1D, as may the operations ofFIGS.2A-2AN. Accordingly, the following description ofFIGS.4A-4Pmay focus primarily on differences with respect to the operations ofFIGS.2A-2AN.

As shown inFIG.4A, a substrate401may have a preliminary transistor stack thereon that is covered with a liner402, which may be an oxide liner.

Referring toFIG.4B, the liner402is removed, thereby exposing the preliminary transistor stack, which includes preliminary nanosheets NS-P, upper sacrificial layers SL-U, lower sacrificial layers SL-L, and a sacrificial layer RL that is between the upper and lower sacrificial layers SL-U, SL-L. Moreover, a bottom sacrificial layer BRL may be between the lower sacrificial layers SL-L and the substrate401. The bottom sacrificial layer BRL has an etch selectivity with respect to the sacrificial layers SL. For example, the bottom sacrificial layer BRL may include the same material as the sacrificial layer RL. The sacrificial layer RL and the bottom sacrificial layer BRL may each be thicker than each of the sacrificial layers SL. Moreover, the bottom sacrificial layer BRL may be thinner than the sacrificial layer RL.

Referring toFIG.4C, the sacrificial layer RL and the bottom sacrificial layer BRL are removed, thereby forming openings403,404. For example, the sacrificial layer RL and the bottom sacrificial layer BRL may each comprise a high concentration of Ge (e.g., higher than that of the sacrificial layers SL) and may be removed by a removal process selective for high-Ge SiGe.

FIG.4Dis a side perspective view of the openings403,404.FIG.4C, on the other hand, is a front perspective view.

Referring toFIG.4E, a gate spacer material405is deposited. The operations ofFIGS.4E-4Omay be used as a repeated deposit-etch back sequence that eventually builds the isolation region IL and the insulating spacers IS.

Referring toFIG.4F, an etch-back operation is performed on the gate spacer material405, thereby forming an opening406in a region where the sacrificial layer RL had been present.

Referring toFIG.4H, an etch-back operation is performed on the gate spacer material407, thereby forming an opening408in a region where the sacrificial layer RL had been present. Due to the repeated gate spacer material formation operations, the opening408is smaller than the opening406(FIG.4F), as more of the gate spacer material407remains after its etch-back operation.

Referring toFIG.4J, an etch-back operation is performed on the gate spacer material409. Rather than forming an opening in a region where the sacrificial layer RL had been present, this etch-back operation may provide a narrowed gate spacer region410.

Referring toFIG.4K, a spacer material411is deposited. In some embodiments, the spacer material411may provide the isolation region IL (FIG.1B).

Referring toFIG.4L, an etch-back operation is performed on the spacer material411, thereby providing recess regions412beyond which the sacrificial layers SL and preliminary nanosheets NS-P protrude outwardly.

Referring toFIG.4M, a recess region413may be formed by removing the outwardly-protruding portions of the sacrificial layers SL and preliminary nanosheets NS-P.

Referring toFIG.4N, upper inner spacers IS-U and lower inner spacers IS-L may be simultaneously formed on sidewalls of the upper sacrificial layers SL-U and lower sacrificial layers SL-L (FIG.4L), respectively.

FIG.4Ois a front perspective view of the inner spacers IS-U and lower inner spacers IS-L that are formed above and below, respectively, the isolation region IL.

FIG.4Pis a front perspective view illustrating that a gate G replaces the sacrificial layers SL on sidewalls of the insulating spacers IS. As the gate G may be vertically thinner than a conventional gate, it may have a smaller surface area and thus may help reduce capacitance (e.g., with a source/drain contact414/415and/or with a source/drain region450). Also, upper source/drain regions450-U are on sidewalls of the upper nanosheets NS-U and lower source/drain regions450-L are on sidewalls of the lower nanosheets NS-L. In some embodiments, a source/drain contact414may be on each upper source/drain region450-U and a source/drain contact415may be on each lower source/drain region450-L. Moreover, a bottom isolation region416is in the space that was formerly occupied by the bottom sacrificial layer BRL (FIG.4B). The bottom isolation region416may comprise, for example, the same insulating material as the isolation region IL.

FIGS.5A and5Bare flowcharts corresponding to operations ofFIGS.4A-4P. As shown inFIGS.5A and4B, a preliminary transistor stack is formed (Block510) that includes alternating sacrificial layers SL and preliminary nanosheets NS-P. Moreover, a sacrificial layer RL separates upper sacrificial layers SL-U from lower sacrificial layers SL-L, and a bottom sacrificial layer BRL separates the lower sacrificial layers SL-L from a substrate401(FIG.4A).

Referring toFIGS.5A and4C, the sacrificial layer RL is removed (Block520) to form an opening404that separates the upper sacrificial layers SL-U from the lower sacrificial layers SL-L. Moreover, the bottom sacrificial layer BRL may be simultaneously removed to form an opening403. In other embodiments, however, the sacrificial layer RL may be removed without simultaneously removing the bottom sacrificial layer BRL.

Referring still toFIG.5A, an isolation layer is formed (Block530) in the opening404. The isolation layer may provide part of the isolation region IL (FIG.4P). As an example, a spacer material411(FIG.4K) may provide the isolation layer.

Referring toFIGS.5A and4O, insulating spacers IS are formed (Block540) on sidewalls of a stack of sacrificial layers SL. The insulating spacers IS are formed after forming the isolation layer that may provide part of the isolation region IL.

Referring toFIGS.5A and4P, a common gate G is formed (Block550) between sidewalls of the insulating spacers IS. The common gate G includes an upper gate G-U and a lower gate G-L that contacts the upper gate G-U.

Referring toFIGS.5B and4O, an operation of forming (Block540ofFIG.5A) the insulating spacers IS may include simultaneously forming (Block540S) upper insulating spacers IS-U on sidewalls of upper sacrificial layers SL-U and lower insulating spacers IS-L on sidewalls of lower sacrificial layers SL-L.

Transistor devices100(FIG.1B) and methods of forming the same according to embodiments of the present invention may provide a number of advantages. These advantages include defining a border between an upper transistor T-U (FIG.1B) and a lower transistor T-L (FIG.1B) of a transistor stack110(FIG.1B). For example, the border can be defined by forming a sacrificial layer RL (FIG.2A) that will be replaced with an isolation region IL (FIG.1B) between the stacked transistors T-U, T-L. Defining the border with the sacrificial layer RL can improve subsequent formation of insulating spacers IS (FIG.1C) that will separate a gate G (FIG.1C) from source/drain regions150(FIG.1C). This can help to address the issue of inner spacer incomplete pinchoff in a region between two transistors in a stack. As another example, by forming the isolation region IL inside the gate G, which may be a common gate having upper and lower gates G-U, G-L that contact each other, variability and control of gate-metal deposition and removal can be improved. This can help to reduce gate capacitance.

Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the teachings of this disclosure and so the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout.

Example embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes illustrated herein but may include deviations in shapes that result, for example, from manufacturing.

It should also be noted that in some alternate implementations, the functions/acts noted in flowchart blocks herein may occur out of the order noted in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Moreover, the functionality of a given block of the flowcharts and/or block diagrams may be separated into multiple blocks and/or the functionality of two or more blocks of the flowcharts and/or block diagrams may be at least partially integrated. Finally, other blocks may be added/inserted between the blocks that are illustrated, and/or blocks/operations may be omitted without departing from the scope of the present invention.