Semiconductor devices and methods of manufacturing the same

A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2011-0082715, filed on Aug. 19, 2011, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

1. Technical Field

The present inventive concept relates to semiconductor devices and methods of manufacturing the same.

2. Discussion of the Related Art

Semiconductor devices are used in almost every industrial field, including various electronic devices, vehicles, vessels and so forth. A field effect transistor (hereinafter referred to as a transistor) is a fundamental building block of modern semiconductor devices. Some transistors are packaged individually, but many more are found embedded in integrated circuits.

The transistor may include a source and a drain spaced apart from each other in a semiconductor substrate, and a gate electrode covering the top surface of a channel region between the source and the drain. The source and the drain may be formed by implanting dopant ions into the semiconductor substrate. The gate electrode may be insulated from the channel region by a gate oxide layer disposed between the semiconductor substrate and the gate electrode.

Developments have been made to achieve highly-integrated, high speed semiconductor devices. Thus, the size of a transistor becomes reduced, so that the turn-on current of the transistor may be decreased. However, the decrease in the turn-on current of the transistor may cause a decrease in the operation speed of the transistor. Thus, the reliability and the operation speed of the semiconductor device may be reduced. Accordingly, there is a need to increase the turn-on current of a transistor in a highly-integrated semiconductor device.

SUMMARY

Exemplary embodiments of the inventive concept provide semiconductor devices with improved reliability and methods of manufacturing the same.

Exemplary embodiments of the inventive concept provide semiconductor devices with high integration and methods of manufacturing the same.

Exemplary embodiments of the inventive concept provide semiconductor devices which can increase a turn-on current of a transistor, and methods of manufacturing the same.

According to an exemplary embodiment of the inventive concept, a method of manufacturing a transistor of a semiconductor device includes: forming a gate pattern on a semiconductor substrate; forming a spacer on a sidewall of the gate pattern; wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer; and wet etching the first recess to form a second recess in the semiconductor substrate.

The first recess has curved sidewalls and the second recess has tapered sidewalls.

At least one tapered sidewall has a {111} crystal plane.

A portion of the spacer adjacent to a surface of the semiconductor substrate protrudes away from the sidewall of the gate pattern.

The spacer with the protruding portion has a cantilever shape.

The method further includes performing an epitaxial growth process to form an epitaxial pattern that fills the second recess.

A surface of the epitaxial pattern is disposed over the surface of the semiconductor substrate.

A doped portion of the epitaxial pattern is a source or a drain of a transistor.

A channel region of the transistor is formed between adjacent epitaxial patterns.

The gate pattern includes a gate electrode of a transistor.

According to an exemplary embodiment of the inventive concept, a method of manufacturing a semiconductor device includes: implanting amorphization element ions into a semiconductor substrate to form an amorphous region in the semiconductor substrate; annealing the amorphous region to form a phase change region in the semiconductor substrate; wet etching the phase change region to form a first recess in the semiconductor substrate; and wet etching the first recess to form a second recess in the semiconductor substrate.

The first recess has curved sidewalls and the second recess has tapered sidewalls.

The annealing temperature is less than 500 degrees Celsius.

The annealing temperature is about 350 degrees Celsius to about 450 degrees Celsius.

According to an exemplary embodiment of the inventive concept, a method of manufacturing a semiconductor device includes: wet etching a semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess has curved sidewalls; and wet etching the first recess to form a second recess in the semiconductor substrate, wherein the second recess has tapered sidewalls.

The first recess has a concave shape.

The tapered sidewalls of the second recess are connected by a substantially straight line.

Before wet etching the semiconductor substrate to form the first recess, the method includes: implanting amorphization element ions into the semiconductor substrate to form an amorphous region in the semiconductor substrate; and annealing the amorphous region to form a phase change region in the semiconductor substrate, wherein the first recess is formed by wet etching the phase change region.

The annealing is performed at a temperature below 500 degrees Celsius.

The temperature is about 350 degrees Celsius to about 450 degrees Celsius.

The amorphization element ions are implanted into the semiconductor substrate by a vertical or tilt implantation method.

An etchant used to wet etch the semiconductor substrate to form the first recess includes at least one of hydrofluoric acid (HF), nitric acid (HNO3) and acetic acid (CH3COOH).

After wet etching the first recess to form the second recess, the method includes performing an epitaxial growth process to form an epitaxial pattern that fills the second recess.

The epitaxial pattern has a hexagon shape.

The epitaxial pattern has a different semiconductor element than the semiconductor substrate.

According to an exemplary embodiment of the inventive concept, a method of manufacturing a semiconductor device includes: implanting amorphization element ions into a semiconductor substrate to form an amorphous region in the semiconductor substrate; annealing the amorphous region to form a phase change region in the semiconductor substrate; dry etching the phase change region to form a first recess in the semiconductor substrate; and wet etching the first recess to form a second recess in the semiconductor substrate.

The first recess has curved sidewalls and the second recess has tapered sidewalls.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Certain aspects of the drawings may be exaggerated for clarity.

It will be understood that when an element such as a layer, region or substrate is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present.

Like reference numerals may denote like elements throughout the specification and drawings, unless otherwise noted.

FIGS. 1A through 1Gare cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.FIG. 2is a flowchart illustrating a method of forming a concave region according to an exemplary embodiment of the inventive concept.

Referring toFIG. 1A, a gate pattern110may be formed on a semiconductor substrate100. A device isolation pattern (not shown) may be formed on the semiconductor substrate100to define an active portion. The active portion may correspond to a portion of the semiconductor substrate100surrounded by the device isolation pattern. The gate pattern110may cross over the active portion. In some embodiments, the gate pattern110may include a gate dielectric pattern102, a gate electrode104, and a hard mask pattern106which are sequentially stacked.

The semiconductor substrate100may be formed of a semiconductor element. For example, the semiconductor substrate100may be a silicon substrate. The semiconductor substrate100may be in a single-crystalline state. The semiconductor substrate100may be doped with dopants of a first conductivity type. The gate dielectric pattern102may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), and/or a high-k dielectric (e.g., an insulating metal oxide). The gate electrode104may include at least one of a semiconductor doped with dopants (e.g., doped silicon), a metal-semiconductor compound (e.g., metal silicide), a conductive metal nitride (e.g., titanium nitride, and/or tantalum nitride) and a transition metal (e.g., titanium, and/or tantalum). The hard mask pattern106may include a nitride (e.g., silicon nitride) and/or an oxynitride (e.g., silicon oxynitride).

A dopant implantation process may be performed using the gate pattern110as a mask to form first and second source/drain extensions113aand113b. The first and second source/drain extensions113aand113bmay be formed in the semiconductor substrate100at both sides of the gate pattern110, respectively. In other words, the gate pattern110may be disposed on the semiconductor substrate100between the first and second source/drain extensions113aand113b. The first and second source/drain extensions113aand113bmay be doped with dopants of a second conductivity type. For example, one of the dopants of the first conductivity type may be P-type dopants, and one of the dopants of the second conductivity type may be N-type dopants, and vice versa.

Subsequently, a spacer layer115may be conformally formed on the semiconductor substrate100. The spacer layer115may include an insulating material. In some embodiments, an additional spacer layer117may be conformally formed on the spacer layer115. The additional spacer layer117may include an insulating material different from the spacer layer115. For example, the spacer layer115may be formed of nitride (e.g., silicon nitride), and the additional spacer layer117may be formed of oxide (e.g., silicon oxide). In this case, before the spacer layer115is formed, a buffer oxide layer (not shown) may be formed on the semiconductor substrate100. The buffer oxide layer may be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, and/or an atomic layer deposition (ALD) process. However, the inventive concept is not limited thereto. The spacer layer115may be formed of other insulating materials, except nitride. The additional spacer layer117may be thinner than the spacer layer115.

Referring toFIG. 1B, the additional spacer layer117and the spacer layer115may be successively etched by performing an etch-back process. Thus, a gate spacer115amay be formed on both sidewalls of the gate pattern110. In some embodiments, each of the gate spacers115amay include a protruding portion115pwhich laterally extends from a lower portion thereof. For example, each of the gate spacers115amay have an ‘L’ shape. The additional spacer layer117on the protruding portion115pmay serve as an etch mask during the etch-back process, so that the protruding portion115pmay be formed.

After the gate spacers115aare formed, the additional spacer layer117may be removed. The additional spacer layer117may be removed by the etch-back process. Alternatively, after the etch-back process is performed, a portion of the additional spacer layer117may remain. The remaining portion of the additional spacer layer117may be removed by a subsequent cleaning process.

Subsequently, concave regions130aand130billustrated inFIG. 1Emay be formed in the semiconductor substrate100at both sides of the gate pattern110, respectively. The method of forming the concave regions130aand130bwill be described with reference to the flowchart ofFIG. 2andFIGS. 1C through 1Ein more detail.

As illustrated inFIG. 2, a phase of a portion of the semiconductor substrate100may be changed to form a phase change region (S150). The semiconductor substrate100may be in the single-crystalline state and the phase change region may have a phase different from the single-crystalline state. In some embodiments, the formation of the phase change region (S150) may include implanting amorphization element ions into a portion of the semiconductor substrate to form an amorphous region (S155), and annealing the amorphous region (S157). Hereinafter, these processes will be described in more detail.

Referring toFIGS. 1C and 2, the amorphization element ions120may be implanted into the semiconductor substrate100using the gate pattern110and the gate spacers115aas masks (S155). Portions of the semiconductor substrate100having single-crystalline states may be amorphized by the amorphization element ions120. Thus, a first amorphous region125aand a second amorphous region125bmay be formed in the semiconductor substrate100at both sides of the gate pattern110, respectively.

An amorphization element of the amorphization element ions120may be an element capable of amorphizing portions of the semiconductor substrate100. Additionally, the amorphization element may be electrically neutral with the semiconductor substrate100. For example, the amorphization element may include at least one of germanium (Ge), silicon (Si), inert gas elements (e.g., argon (Ar), krypton (Kr), xenon (Xe), etc.), carbon (C), nitrogen (N), and oxygen (O). An implantation energy of the amorphization element ions120may be within a range of about 5 KeV to about 40 KeV. A dose of the amorphization element ions120may be within a range of about 1×1014atoms/cm2to about 1×1016atoms/cm2. However, the inventive concept is not limited to the above ranges.

In some embodiments, the amorphization element ions120may be implanted into the semiconductor substrate100by a vertical implantation method. An implantation direction of the vertical implantation method may be substantially vertical with respect to a top surface of the semiconductor substrate100. In other words, the implantation direction of the vertical implantation method may be vertical with respect to the top surface of the semiconductor substrate100or may be fractionally tilted with respect to the top surface of the semiconductor substrate100to minimize ion channeling. For example, the implantation direction of the vertical implantation method may have an angle within a range of 0 degrees to about 7 degrees with respect to a perpendicular line extending from the top surface of the semiconductor substrate100.

The amorphization element ions120may be implanted at room temperature. In this case, the amorphization element may include at least one of germanium (Ge), silicon (Si), and xenon (Xe).

Alternatively, the amorphization element ions120may be implanted at a lower process temperature within a range of about −20 degrees Celsius to about −100 degrees Celsius. In this case, even though the amorphization element ions120are implanted by the vertical implantation method, lateral components of the amorphization element ions120may increase in the semiconductor substrate100. As a result, a width of each of the amorphous regions125aand125bmay increase. When the amorphization element ions120are implanted at the lower process temperature, the amorphization element may include at least one of germanium (Ge), silicon (Si), inert gas elements (e.g. argon (Ar), krypton (Kr), xenon (Xe), etc.), carbon (C), nitrogen (N), and oxygen (O).

Referring toFIGS. 1D and 2, the first and second amorphous regions125aand125bmay be annealed by an annealing process performed on the semiconductor substrate100(S157). Thus, first and second phase change regions127aand127bmay be formed. Due to the annealing process, phases of the first and second amorphous regions125aand125bmay be changed to form the first and second phase change regions127aand127b. At least a portion of the first amorphous region125amay be changed to the first phase change region127aand at least a portion of the second amorphous region125bmay be changed to the second phase change region127bby the annealing process. In some embodiments, each of the first and second phase change regions127aand127bmay be in a micro-crystalline state. The micro-crystalline state may have a phase between an amorphous state and a poly-crystalline state. For example, the micro-crystalline state may include a plurality of crystalline nuclei.

The annealing process may be performed at a process temperature within a range of about 300 degrees Celsius to about 650 degrees Celsius. The annealing process may be performed for a process time within a range of about 0.1 second to about 5 minutes. In some embodiments, the annealing process may be performed at a process temperature of less than 500 degrees Celsius. For example, within a range of about 350 degrees Celsius to about 450 degrees Celsius. In this case, the first and second amorphous regions125aand125bmay be fully changed to form the first and second phase change regions127aand127b. Alternatively, the annealing process may be performed at a process temperature within a range of about 450 degrees Celsius to about 650 degrees Celsius. In this case, the first and second amorphous regions125aand125bmay be partially changed to form first and second phase change regions. This case will be described later.

The annealing process may be performed by at least one of a batch annealing method, a rapid thermal annealing method, a spike rapid thermal annealing method, and a flash rapid thermal annealing method.

Referring toFIGS. 1E and 2, the first phase change region127aand the second phase change region127bmay be removed to form a first concave region130aand a second concave region130b, respectively (S160).

The first and second phase change regions127aand127bmay be removed by a wet etching process. As a result, an etch selectivity between the phase change regions127aand127band the semiconductor substrate100can be improved. Additionally, an etch selectivity between the phase change regions127aand127band the gate spacers115acan be improved. In some embodiments, a ratio of an etch rate of the phase change regions127aand127bto an etch rate of the semiconductor substrate100by the wet etching process may be within a range of about 50:1 to about 300:1. Additionally, a ratio of the etch rate of the phase change regions127aand127bto an etch rate of the gate spacers115aby the wet etching process may be within a range of about 10:1 to about 100:1. The first and second phase change regions127aand127bmay be substantially isotropically etched by the wet etching process. In some embodiments, an etch selectivity between the phase change regions127aand127band the hard mask pattern106can be improved by the wet etching process. When the hard mask pattern106includes the same material as the gate spacers115a, a ratio of the etch rate of the phase change regions127aand127bto an etch rate of the hard mask pattern106by the wet etching process may be within a range of about 10:1 to about 100:1.

For example, when the semiconductor substrate100is the silicon substrate and the gate spacers115ainclude silicon nitride, an etchant of the wet etching process may include a hydrofluoric acid (HF), a nitric acid (HNO3), and an acetic acid (CH3COOH). Additionally, the etchant may further include deionized water. A content ratio of the hydrofluoric acid (HF) in the etchant may be within a range of about 0.3 wt % (weight percentage) to about 1.5 wt %. A content ratio of the nitric acid (HNO3) in the etchant may be within a range of about 40 wt % to about 60 wt %. A content ratio of the acetic acid (CH3COOH) in the etchant may be within a range of about 1 wt % to about 5 wt %. In some embodiments, the etchant may include the hydrofluoric acid (HF) of about 0.7 wt %, the nitric acid (HNO3) of about 50 wt %, the acetic acid (CH3COOH) of about 2.6 wt %, and the deionized water of about 46.7 wt %.

According to the methods of forming the concave regions130aand130bdescribed above, the amorphization element ions120may be implanted to form the amorphous regions125aand125b, and the amorphous regions125aand125bmay be annealed to form the phase change regions127aand127b. The phase change regions127aand127bmay be removed to form the concave regions130aand130b. The phase change regions127aand127bformed by the annealing process may be quickly etched in the removal process of the phase change regions127aand127b. In other words, an etch rate of the phase change regions127aand127bin the removal process may increase. Additionally, the phase change regions127aand127bmay have a different phase from the semiconductor substrate100. For example, the phase change regions127aand127bmay be in the micro-crystalline state. Thus, the etch selectivity between the phase change regions127aand127band the semiconductor substrate100can be improved.

Additionally, the phase change regions127aand127bmay be removed by the wet etching process. Thus, the etch selectivity between the phase change regions127aand127band the semiconductor substrate100can be improved. In addition, the etch selectivity between the phase change regions127aand127band the gate spacers115acan also be improved.

In some embodiments, the amorphization element ions120may be implanted at the lower process temperature within the range of about −20 degrees Celsius to about −100 degrees Celsius. In this case, inner surfaces of the concave regions130aand130bmay be smooth.

Subsequently, referring toFIG. 1F, an anisotropic wet etching process may be performed on the first and second concave regions130aand130b. Thus, first and second recess regions135aand135bmay be formed. The anisotropic wet etching process may use {111} crystal planes of the semiconductor substrate100as etch stop surfaces. In other words, an etch rate of the {111} crystal planes used in the anisotropic wet etching process may be less than those of the other crystal planes of the semiconductor substrate100. Thus, bottom surfaces and sidewalls of the concave regions130aand130bmay be etched by the anisotropic wet etching process to form the recess regions135aand135bincluding tapered undercut regions137aand137b. The first recess region135aand the second recess region135bmay include a first tapered undercut region137aand a second tapered undercut region137b, respectively. Inner surfaces of the first and second tapered undercut regions137aand137bmay be included in the {111} crystal planes. In some embodiments, if the semiconductor substrate100is the silicon substrate, the anisotropic wet etching process may use an anisotropic etchant including ammonium hydroxide (NH4OH) and/or tetramethyl ammonium hydroxide (TMAH).

The first tapered undercut region137aof the first recess region135amay have a shape laterally tapered toward a channel region under the gate pattern110, and the second tapered undercut region137bof the second recess region135bmay have a shape laterally tapered toward the channel region. In some embodiments, the first tapered undercut region137amay be substantially symmetric to the second tapered undercut region137bwith respect to the channel region. However, the inventive concept is not limited thereto.

Referring toFIG. 1G, an epitaxial growth process may be performed on the semiconductor substrate100having the first and second recess regions135aand135bto form first and second epitaxial patterns140aand140b. The first and second epitaxial patterns140aand140bmay fill the first and second recess regions135aand135b, respectively. Due to the first and second tapered undercut regions137aand137b, the first epitaxial pattern140amay include a first tapered portion142alaterally tapered toward the channel region, and the second epitaxial pattern140bmay include a second tapered portion142blaterally tapered toward the channel region. The first and second tapered portions142aand142bmay be disposed in the semiconductor substrate100. In other words, tips of the first and second tapered portions142aand142bmay be disposed below a top surface of the semiconductor substrate100under the gate pattern110.

The first and second epitaxial patterns140aand140bmay include a semiconductor element different from the semiconductor element of the semiconductor substrate100. Accordingly, the first and second epitaxial patterns140aand140bmay provide a compressive force or a tensile force to the channel region under the gate pattern110. As a result, when a transistor including the channel region is operated, the mobility of carriers in a channel generated in the channel region can increase. Because the first and second epitaxial patterns140aand140binclude the first and second tapered portions142aand142b, the compressive force or the tensile force provided to the channel region can further increase. As a result, the mobility of the carriers in the channel may further increase.

When the transistor including the channel region is a PMOS transistor, the first and second epitaxial patterns140aand140bmay provide the compressive force to the channel region. Thus, the mobility of holes in the channel can increase. To provide the compressive force to the channel region, the first and second epitaxial patterns140aand140bmay include a semiconductor element which has a larger diameter than the semiconductor element of the semiconductor substrate100. For example, when the semiconductor substrate100is the silicon substrate, the first and second epitaxial patterns140aand140bmay include silicon-germanium (SiGe) or germanium (Ge).

When the transistor including the channel region is an NMOS transistor, the first and second epitaxial patterns140aand140bmay provide a tensile force to the channel region. Thus, the mobility of electrons in the channel can increase. To provide the tensile force to the channel region, the first and second epitaxial patterns140aand140bmay include a semiconductor element which has a smaller diameter than the semiconductor element of the semiconductor substrate100. For example, when the semiconductor substrate100is the silicon substrate, the first and second epitaxial patterns140aand140bmay include silicon carbide (SiC).

In some embodiments, top surfaces of the first and second epitaxial patterns140aand140bmay be disposed above the top surface of the semiconductor substrate100under the gate pattern110. In this case, due to the protruding portions115pof the gate spacers115a, interfaces between the semiconductor substrate100and the epitaxial patterns140aand140bcan be protected. In other words, the protruding portions115pmay cover the ends of the interfaces adjacent to the top surface of the semiconductor substrate100, so that the interfaces can be protected. As a result, the reliability of the transistor can be improved.

At least a portion of each of the first and second epitaxial patterns140aand140bmay be doped with dopants of the second conductivity type. In some embodiments, the first and second epitaxial patterns140aand140bmay be doped by an in-situ method. In this case, each of the first and second epitaxial patterns140aand140bmay be fully doped with dopants of the second conductivity type. In other embodiments, after the first and second epitaxial patterns140aand140bare formed, dopant ions of the second conductivity type may implanted into the epitaxial patterns140aand140busing the gate pattern110and the gate spacers115aas masks to dope at least portions of the epitaxial patterns140aand140b. In some embodiments, the first source/drain extension113aand the doped portion of the first epitaxial pattern140amay be included in a drain region of the transistor, and the second source/drain extension113band the doped portion of the second epitaxial pattern140bmay be included in a source region of the transistor.

Subsequently, an interlayer dielectric layer145illustrated inFIG. 5may be formed on the semiconductor substrate100. First and second contact plugs147aand147bpenetrating the interlayer dielectric layer145may be formed. The first and second contact plugs147aand147bmay be electrically connected to the first and second epitaxial patterns140aand140b, respectively. Thus, the semiconductor device illustrated inFIG. 5may be realized.

As described with reference toFIGS. 1C and 1D, the amorphous regions125aand125bmay be fully changed to the phase change regions127aand127b. Alternatively, the amorphous regions125aand125bmay be partially changed. This will described with reference toFIGS. 3A and 3B.

FIGS. 3A and 3Bare cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring toFIGS. 1C and 3A, the annealing process may be performed on the semiconductor substrate100including the amorphous regions125aand125b. At this time, the process temperature of the annealing process may be within the range of about 450 degrees Celsius to about 650 degrees Celsius. In this case, portions of the first and second amorphous regions125aand125badjacent to the semiconductor substrate100may be changed into solid phase epitaxy portions EP, and other portions of the first and second amorphous regions125aand125bmay be changed into first and second phase change regions127a′ and127b′, respectively.

The solid phase epitaxy portion EP may be formed using the semiconductor substrate100adjacent to each of the amorphous regions125aand125bas a seed. The solid phase epitaxy portion EP may be in a single-crystalline state like the semiconductor substrate100. Each of the first and second phase change regions127a′ and127b′ may be in the micro-crystalline state described above.

Referring toFIG. 3B, the first and second phase change regions127a′ and127b′ may be removed by the wet etching process described with reference toFIGS. 1E and 2. Thus, first and second concave regions130a′ and130b′ may be formed. At this time, since the solid phase epitaxy portions EP have the same single-crystalline state as the semiconductor substrate100, the solid phase epitaxy portions EP may remain. Subsequently, the anisotropic wet etching process described with reference toFIG. 1Fmay be performed to form the first and second recess regions135aand135billustrated inFIG. 1F. Alternatively, since the first and second concave regions130a′ and130b′ according to the present embodiment may have different shapes than the first and second concave regions130aand130billustrated inFIG. 1E, the first and second recess regions according to the present embodiment may have different sizes, different widths, and/or different depths than the first and second recess regions135aand135billustrated inFIG. 1F. Subsequent processes may be performed in the same way as described with reference toFIGS. 1G and 5.

In addition, the gate pattern110may include the gate electrode104. In other words, after the gate electrode104is formed, the concave regions130aand130b, the recess regions135aand135b, and the epitaxial patterns140aand140bmay formed in order. Alternatively, after the epitaxial patterns140aand140bare formed, the gate electrode may be formed. This will be described with reference toFIGS. 4A to 4D.

FIGS. 4A through 4Dare cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 4A, a dummy gate pattern175may be formed on the semiconductor substrate100. Subsequently, the formation process of the source/drain extensions113aand113bthrough the formation process of the epitaxial patterns140aand140bdescribed with reference toFIGS. 1A through 1Fmay be performed. The dummy gate pattern175may include a material having an etch selectivity with respect to the gate spacers115aand subsequent lower interlayer dielectric layer. In some embodiments, the dummy gate pattern175may include a semiconductor pattern170and a capping pattern173which are sequentially stacked. When the gate spacers115aare formed of silicon nitride and the lower interlayer dielectric layer is formed of silicon oxide, the semiconductor pattern170may be formed of poly-crystalline silicon and the capping pattern173may be formed of silicon oxide. A buffer oxide layer (not shown) may be formed between the dummy gate pattern175and the semiconductor substrate100.

Referring toFIG. 4B, the lower interlayer dielectric layer145amay be formed on the semiconductor substrate100including the epitaxial patterns140aand140band the dummy gate pattern175. Subsequently, the lower interlayer dielectric layer145aand the capping pattern173may be planarized until the semiconductor pattern170of the dummy gate pattern175is exposed. The lower interlayer dielectric layer145aand the capping pattern173may be planarized by a chemical mechanical polishing (CMP) process. Upper portions of the gate spacers115amay be removed by the planarization process of the lower interlayer dielectric layer145aand the capping pattern173. As described above, the semiconductor pattern170of the dummy gate pattern175may have the etch selectivity with respect to the planarized lower dielectric layer145aand the gate spacers115a.

Referring toFIG. 4C, the exposed semiconductor pattern170may be removed to form a gate groove177. If the buffer oxide layer (not shown) is formed, after the exposed semiconductor pattern170is removed, the buffer oxide layer may be removed to expose the semiconductor substrate100under the gate groove177. A gate dielectric layer180may be formed on the semiconductor substrate100including the gate groove177, and a gate conductive layer185may be formed on the gate dielectric layer180to fill the gate groove177. The gate dielectric layer180may include an oxide, a nitride, an oxynitride, and/or a high-k dielectric. The gate dielectric layer180may be formed by a thermal oxidation process, a nitridation process, an oxy-nitridation process, an ALD process, and/or a CVD process. The gate conductive layer185may include a conductive metal nitride (e.g., titanium nitride, and/or tantalum nitride), a transition metal (e.g., titanium and/or tantalum), and/or a metal (e.g., tungsten).

Referring toFIG. 4D, the gate conductive layer185may be planarized to form a gate electrode185ain the gate groove177. In some embodiments, the gate dielectric layer180on the planarized lower interlayer dielectric layer145amay be removed during the planarization process of the gate conductive layer185. Thus, a gate dielectric pattern180amay be formed in the gate groove177. In the present embodiment, the gate electrode185amay be formed as a metal gate. Subsequently, an upper interlayer dielectric layer190illustrated inFIG. 6may be formed. First and second contact plugs147aand147bpenetrating the upper interlayer dielectric layer190and the planarized lower interlayer dielectric layer145amay be formed. Thus, a semiconductor device illustrated inFIG. 6may be realized.

FIG. 5is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. The semiconductor device ofFIG. 5may be fabricated according to the methods ofFIGS. 1A through 1G.

Referring toFIG. 5, the gate pattern110may be disposed on the semiconductor substrate100. The first and second epitaxial patterns140aand140bmay fill the first and second recess regions135aand135bformed in the semiconductor substrate100at both sides of the gate pattern110, respectively. The gate pattern110may include the gate dielectric pattern102, the gate electrode104, and the hard mask pattern106. The first and second epitaxial patterns140aand140bmay be adjacent to both sidewalls of the gate pattern110. Thus, one transistor may include the first and second epitaxial patterns140aand140band the gate pattern110disposed on the semiconductor substrate100between the first and second epitaxial patterns140aand140b.

As described with reference toFIG. 1G, the first and second epitaxial patterns140aand140bmay include a semiconductor element different from that of the semiconductor substrate100. Thus, the first and second epitaxial patterns140aand140bmay provide the compressive force or the tensile force to the channel region under the gate pattern110. The first epitaxial pattern140amay include the first tapered portion142atapered toward the channel region and the second epitaxial pattern140bmay include the second tapered portion142btapered toward the channel region. The first and second tapered portions142aand142bmay include inclined surfaces which are included in the {111} crystal planes. In some embodiments, the first tapered portion142amay be substantially symmetric to the second tapered portion142bwith respect to the channel region. In other words, the first tapered portion142amay be substantially symmetric to the second tapered portion142babout an imaginary vertical line which passes through a center of the channel region and is perpendicular to the top surface of the semiconductor substrate100. The first and second epitaxial patterns140aand140bmay include the materials described with reference toFIG. 1G.

The gate spacers115amay be disposed on both sidewalls of the gate pattern110, respectively. Each of the gate spacers115amay include the protruding portion115platerally extending from a lower portion thereof. One gate spacer115aon one sidewall of the gate pattern110may be substantially symmetric to another gate spacer115aon another sidewall of the gate pattern110with respect to the gate pattern110. Due to the protruding portions115pof the gate spacers115a, the interfaces between the epitaxial patterns140aand140band the semiconductor substrate100can be protected. Upper surfaces of the first and second epitaxial patterns140aand140bmay be disposed above the top surface of the semiconductor substrate100.

The interlayer dielectric layer145may cover the gate pattern110, gate spacers115a, and the epitaxial patterns140aand140b. The first and second contact plugs147aand147bmay penetrate the interlayer dielectric layer145to be connected to top surfaces of the first and second epitaxial patterns140aand140b, respectively. Each of the contact plugs147aand147bmay include an ohmic pattern contacting each of the epitaxial patterns140aand140b. The contact plugs147aand147bmay include a metal (e.g., tungsten), a conductive metal nitride (e.g., titanium nitride, and/or tantalum nitride), and/or a transition metal (e.g., titanium, and/or tantalum). Even though not shown, interconnections may be disposed on the interlayer dielectric layer145to be connected to the contact plugs147aand147b. In some embodiments, at least one of the first and second contact plugs147aand147bmay be omitted.

FIG. 6is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. The semiconductor device ofFIG. 6may be fabricated according to the methods ofFIGS. 1A through 1G, except that after the epitaxial patterns140aand140bare formed, the gate electrode may be formed as shown inFIGS. 4A through 4D.

Referring toFIG. 6, the gate electrode185amay be disposed over the channel region between the first and second epitaxial patterns140aand140b, and the gate dielectric pattern180amay be disposed between the gate electrode185aand the semiconductor substrate100. InFIG. 6, the gate dielectric pattern180amay extend to cover both sidewalls of the gate electrode185a. In this case, the extension of the gate dielectric pattern180amay be disposed between the gate electrode185aand the gate spacers115a. The lower interlayer dielectric layer145amay cover the epitaxial patterns140aand140b. The lower interlayer dielectric layer145amay not cover a top surface of the gate electrode185a. The upper interlayer dielectric layer190may cover the lower interlayer dielectric layer145aand the top surface of the gate electrode185a. The first and second contact plugs147aand147bmay successively penetrate the upper and lower interlayer dielectric layers190and145ato be connected to the first and second epitaxial patterns140aand140b, respectively.

FIGS. 7A through 7Eare cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 7A, amorphization element ions220may be implanted into the semiconductor substrate100using the gate pattern110and the gate spacers115aas masks. Thus, a first amorphous region225aand a second amorphous region225bmay be formed in the semiconductor substrate100at both sides of the gate pattern110, respectively. The amorphization element ions220may be implanted by a tilt implantation method.

Due to the tilt implantation method, the amorphization element ions220may be implanted to be tilted with respect to the top surface of the semiconductor substrate100. A tilt implantation direction of the tilt implantation method may be non-vertical and non-parallel with respect to the top surface of the semiconductor substrate100. In some embodiments, an angle between a vertical line that is perpendicular to the top surface of the semiconductor substrate100and the tilt implantation direction may be greater than 0 degrees, and equal to or less than about 70 degrees. In particular, the angle between the vertical line and the tilt implantation direction may be greater than about 7 degrees, and equal to or less than about 45 degrees. In the present embodiment, the amorphization element ions220may be implanted in one tilt implantation direction. Thus, the first amorphous region225amay be formed to be asymmetric to the second amorphous region225babout the channel region under the gate pattern110. In other words, the first amorphous region225amay be asymmetric to the second amorphous region225babout an imaginary vertical line which is perpendicular to the top surface of the semiconductor substrate100and passes through the center of the channel region.

In some embodiments, the first amorphous region225amay be disposed to be closer to the channel region as compared with the second amorphous region225b. The second amorphous region225bmay be disposed to be farther from the channel region as compared with the first amorphous region225a.

The amorphization element of the amorphization element ions220may include at least one of the amorphization elements used as the amorphization element ions120described with reference toFIGS. 1C and 2. A dose and an implantation energy of the amorphization element ions220may be the same as the dose and the implantation energy of the amorphization element ions120described with reference toFIG. 1C, respectively.

In some embodiments, the amorphization element ions220may be implanted at room temperature. Alternatively, as described with reference toFIGS. 1C and 2, the amorphization element ions220may be implanted at the lower process temperature within the range of about −20 degrees Celsius to about −100 degrees Celsius.

Referring toFIG. 7B, an annealing process may be performed on the semiconductor substrate100including the first and second amorphous regions225aand225bto form first and second phase change regions227aand227b. The annealing process may be performed in the same manner as the annealing process described with reference toFIGS. 1D,2, and3A. Thus, the first and second amorphous regions225aand225bmay be fully or partially changed to form the first and second phase change regions227aand227b. Each of the first and second phase change regions227aand227bmay be in the micro-crystalline state described above.

Referring toFIG. 7C, the first and second phase change regions227aand227bmay be removed to form first and second concave regions230aand230b. The first and second phase change regions227aand227bmay be removed by the wet etching process described with reference toFIGS. 1E and 2. Due to the arrangement of the first and second amorphous regions225aand225b, the first concave region230amay be asymmetric to the second concave region230babout the channel region.

Referring toFIG. 7D, the anisotropic wet etching process described with reference toFIG. 1Fmay be performed on the first and second concave regions230aand230bto form first and second recess regions235aand235b. The first recess region235amay include a first tapered undercut region237alaterally tapered toward the channel region, and the second recess region235bmay include a second tapered undercut region237blaterally tapered toward the channel region. At this time, the first recess region235amay be asymmetric to the second recess region235babout the channel region. In particular, the first tapered undercut region237amay be asymmetric to the second tapered undercut region237babout the channel region.

Referring toFIG. 7E, an epitaxial process may be performed to form first and second epitaxial patterns240aand240bfilling the first and second recess regions235aand235b, respectively. The first and second epitaxial patterns240aand240bmay be formed of the same material as the first and second epitaxial patterns140aand140bdescribed with reference toFIG. 1G. Additionally, the first and second epitaxial patterns240aand240bmay be doped by the same methods used for doping the epitaxial patterns140aand140bdescribed with reference toFIG. 1G.

Due to the first and second tapered undercut regions237aand237b, the first epitaxial pattern240amay include a first tapered portion242alaterally tapered toward the channel region, and the second epitaxial pattern240bmay include a second tapered portion242blaterally tapered toward the channel region. The first tapered portion242amay be asymmetric to the second tapered portion242babout the channel region.

In the present embodiment, the amorphization element ions220may be implanted into the semiconductor substrate100by the tilt implantation method. Thus, the first amorphous region225amay be asymmetric to the second amorphous region225babout the channel region. As a result, the first tapered portion242aof the first epitaxial pattern240acan be asymmetric to the second tapered portion242bof the second epitaxial pattern240babout the channel region. Thus, the reliability of a transistor which includes the first and second epitaxial patterns240aand240band the gate pattern110disposed between the first and second epitaxial patterns240aand240bmay be improved. This will be described in more detail later.

Further, in the present embodiment in which the first amorphous region225ais asymmetric to the second amorphous region225babout the channel region, the removal process used in the formation of the concave regions230aand230bmay be performed by other methods. In some embodiments, the phase change regions227aand227bmay be removed by an isotropic dry etching process. In other embodiments, the annealing process may be omitted and the first and second amorphous regions225aand225bmay be removed by the isotropic dry etching process to form the first and second concave regions230aand230b.

In some embodiments, the dummy gate pattern175, which is described with reference toFIGS. 4A through 4D, may also be applied to the method of manufacturing the semiconductor device according to the present embodiment.

A semiconductor device manufactured according to the present embodiment will be described with reference toFIGS. 8A and 8B.

FIG. 8Ais a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept, andFIG. 8Bis an enlarged view of a portion ‘A’ ofFIG. 8A.

Referring toFIGS. 8A and 8B, the first epitaxial pattern240aand the second epitaxial pattern240bmay fill the first recess region235aand the second recess region235bformed in the semiconductor substrate100at both sides of the gate pattern110, respectively. The first and second epitaxial patterns240aand240bmay be adjacent to both sides of the gate pattern110. Thus, the first and second epitaxial patterns240aand240band the gate pattern110on the semiconductor substrate100therebetween may be included in a transistor.

The first tapered portion242aof the first epitaxial pattern240amay be asymmetric to the second tapered portion242bof the second epitaxial pattern240babout the channel region CHR under the gate pattern110. In more detail, as illustrated inFIG. 8B, the first tapered portion242amay be asymmetric to the second tapered portion242babout an imaginary vertical line250which passes through a center of the channel region CHR and is perpendicular to a top surface of the semiconductor substrate100. A first horizontal distance D1between a tip of the first tapered portion242aand the center of the channel region CHR may be different from a second horizontal distance D2between a tip of the second tapered portion242band the center of the channel region CHR. As illustrated inFIG. 8B, the first horizontal distance D1may correspond to the shortest distance between the tip of the first tapered portion242aand the imaginary vertical line250, and the second horizontal distance D2may correspond to the shortest distance between the tip of the second tapered portion242band the imaginary vertical line250.

In some embodiments, the first horizontal distance D1may be less than the second horizontal distance D2. In this case, the doped portion of the first epitaxial pattern240aand the first source/drain extension113amay correspond to a drain region of the transistor, and the doped portion of the second epitaxial pattern240band the second source/drain extension113bmay correspond to a source region of the transistor. Due to the first tapered portion242a, the compressive force or the tensile force may be sufficiently provided to a portion of the channel region CHR adjacent to the drain region. Thus, a potential barrier of the portion of the channel region CHR adjacent to the drain region may become lower. As a result, a turn-on current of the transistor may be improved. The second tapered portion242bmay be farther from the channel region CHR as compared with the first tapered portion242a. Thus, a punch-through characteristic between the source region and the drain region (e.g., a punch-through characteristic between the first and second tapered portions242aand242b) can be improved. Additionally, the second tapered portion242bmay also provide the compressive force or the tensile force to the channel region CHR. As a result, the turn-on current of the transistor including the first and second tapered portions242aand242bmay be improved and the punch-through characteristic of the transistor may be improved.

In some embodiments, the first tapered portion242amay be overlapped with the gate pattern110, while the second tapered portion242bmay not be overlapped with the gate pattern110when viewed from a plan view. However, the inventive concept is not limited thereto.

In some embodiments, the tip of the first tapered portion242amay be disposed at substantially the same distance from the top surface of the semiconductor substrate100under the gate pattern110as the tip of the second tapered portion242b. However, the inventive concept is not limited thereto.

In some embodiments, the gate dielectric pattern180aand the gate electrode185aillustrated inFIG. 6may be replaced with the gate pattern110illustrated inFIGS. 8A and 813.

FIGS. 9A through 9Eare cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. The gate pattern110of the present embodiment may by fabricated using the processes described with reference toFIGS. 1A and 1B.

Referring toFIG. 9A, first amorphization element ions320amay be implanted into the semiconductor substrate100using the gate pattern110and the gate spacers115aas masks. The first amorphization element ions320amay be implanted by a vertical implantation method. Second amorphization element ions320bmay be implanted into the semiconductor substrate100using the gate pattern110and the gate spacers115aas masks. The second amorphization element ions320bmay be implanted by a tilt implantation method. Due to the first and second amorphization element ions320aand320b, a first amorphous region325aand a second amorphous region325bmay be formed in the semiconductor substrate100at both sides of the gate pattern110, respectively.

An implantation direction of the first amorphization element ions320amay be substantially the same as that of the amorphization element ions120described with reference toFIGS. 1C and 2. An implantation direction of the second amorphization element ions320bmay be substantially the same as that of the amorphization element ions220described with reference toFIG. 7A. An implantation energy of the first amorphization element ions320amay be greater than that of the second amorphization element ions320b.

The first amorphous region325amay include a first sidewall and a second sidewall which are opposite to each other. Similarly, the second amorphous region325bmay include a first sidewall and a second sidewall which are opposite to each other. The first sidewalls of the first and second amorphous regions325aand325bmay be adjacent to the channel region between the first and second amorphous regions325aand325b. Due to the second amorphization element ions320b, an upper portion of the first sidewall of the first amorphous region325amay laterally protrude toward the channel region more than a lower portion of the first sidewall of the first amorphous region325a. Thus, the first amorphous region325amay include a tilt implantation region300aprotruding toward the channel region. On the other hand, since the second amorphization element ions320bare implanted in one tilted direction, an upper portion of the first sidewall of the second amorphous region325bmay not protrude toward the channel region. As a result, the first sidewall of the first amorphous region325amay have a structure which is asymmetric to the first sidewall of the second amorphous region325babout the channel region between the first and second amorphous regions325aand325b.

In some embodiments, due to the second amorphization element ions320b, an upper portion of the second sidewall of the second amorphous region325bmay laterally protrude, so that the second amorphous region325bmay include a tilt implantation region300b. The tilt implantation region300bof the second amorphous region325bmay not influence the channel region between the first and second amorphous regions325aand325b. In other embodiments, if the second sidewall of the second amorphous region325bis in contact with a device isolation pattern (not shown), the tilt implantation region300bof the second amorphous region325bmay not be formed.

A first amorphization element of the first amorphization element ions320amay include at least one of the amorphization elements used as the amorphization element ions120described with reference toFIGS. 1C and 2. A second amorphization element of the second amorphization element ions320bmay include at least one of the amorphization elements used as the amorphization element ions120described with reference toFIGS. 1C and 2. The first amorphization element may be the same as the second amorphization element. Alternatively, the first amorphization element may be different from the second amorphization element. Each dose of the first and second amorphization element ions320aand320bmay be the same as the dose of the amorphization element ions120described with reference toFIG. 1C. The first and second amorphization element ions320aand320bmay be implanted at room temperature. Alternatively, the first and second amorphization element ions320aand320bmay be implanted at the lower process temperature within the range of about −20 degrees Celsius to about −100 degrees Celsius.

Referring toFIG. 9B, an annealing process may be performed on the semiconductor substrate100including the first and second amorphous regions325aand325bto form first and second phase change regions327aand327b. The annealing process may be performed in the same manner as the annealing process described with reference toFIGS. 1D,2, and3A. Thus, the first and second amorphous regions325aand325bmay be fully or partially changed to the first and second phase change regions327aand327b. Each of the first and second phase change regions327aand327bmay be in the micro-crystalline state described above.

Due to the shapes of the first and second amorphous regions325aand325b, a first sidewall of the first phase change region327amay include a protruding portion305aprotruding toward the channel region between the first and second phase change regions327aand327b, while a protruding portion is not formed at a first sidewall of the second phase change region327badjacent to the channel region. In some embodiments, due to the tilt implantation region300bof the second amorphous region325b, the second phase change region327bmay include a protruding portion305bformed at a second sidewall of the second phase change region327bopposite to the first sidewall thereof. Alternatively, the second phase change region327bmay not include the protruding portion305b.

Referring toFIG. 9C, the first and second phase change regions327aand327bmay be removed to form first and second concave regions330aand330b. In some embodiments, the first and second phase change regions327aand327bmay be removed by the wet etching process described with reference toFIGS. 1E and 2. The first concave region330amay include an undercut region310awhich is formed by removing the protruding portion305aof the first phase change region327a. The undercut region310aof the first concave region330amay have a laterally hollowed shape protruding toward the channel region between the first and second concave regions330aand330b. In other words, the first concave region330amay include a first sidewall adjacent to the channel region, and an upper portion of the first sidewall of the first concave region330amay laterally protrude toward the channel region more than a lower portion of the first sidewall of the first concave region330a. On the other hand, an undercut region is not formed at a first sidewall of the second concave region330badjacent to the channel region between the first and second concave regions330aand330b. In some embodiments, an undercut region310b, which may be formed by removing the protruding portion305bof the second phase change region327b, may be formed at a second sidewall of the second concave region330bopposite to the first sidewall thereof. Alternatively, the second concave region330bmay not include the undercut region310b.

Referring toFIG. 9D, the anisotropic wet etching process described with reference toFIG. 1Fmay be performed on the first and second concave regions330aand330b. As a result, first and second recess regions335aand335bmay be formed. The first recess region335amay include a plurality of first tapered undercut regions RTUa and RTLa which are laterally tapered toward the channel region. The plurality of first tapered undercut regions RTUa and RTLa may include an upper tapered undercut region RTUa and a lower tapered undercut region RTLa disposed under the upper tapered undercut region RTUa. An inner sidewall of the undercut region310aof the first concave region330amay be etched by the anisotropic wet etching process to form the upper tapered undercut region RTUa, and the lower portion of the first sidewall of the first concave region330adisposed under the undercut region310amay be etched by the anisotropic wet etching process to form the lower tapered undercut region RTLa. On the other hand, since an undercut region is not formed at the first sidewall of the second concave region330b, the second recess region335bmay include one tapered undercut region RTSb tapered toward the channel region. The tapered undercut region RTSb of the second recess region335bmay be referred to as a second tapered undercut region RTSb.

In some embodiments, the first recess region335amay further include one additional tapered undercut region RTSa opposite to the upper and lower tapered undercut regions RTUa and RTLa. The second recess region335bmay further include a plurality of additional tapered undercut regions RTUb and RTLb opposite to the second tapered undercut region RTSb. In other embodiments, the additional tapered undercut regions RTSa, RTUb, and RTLb of the first and second recess regions335aand335bmay be omitted.

Referring toFIG. 9E, an epitaxial process may be performed to form first and second epitaxial patterns340aand340bfilling the first and second recess regions335aand335b, respectively. The first and second epitaxial patterns340aand340bmay be formed of the same material as the first and second epitaxial patterns140aand140bdescribed with reference toFIG. 1G. Additionally, the first and second epitaxial patterns340aand340bmay doped by the same methods used for doping the epitaxial patterns140aand140bdescribed with reference toFIG. 1G.

Due to the plurality of first tapered undercut regions RTUa and RTLa of the first recess region335a, the first epitaxial pattern340amay include a plurality of first tapered portions CTUa and CTLa laterally tapered toward the channel region between the first and second epitaxial patterns340aand340b. Due to the second tapered undercut region RTSb of the second recess region335b, the second epitaxial pattern340bmay include one second tapered portion CTSb laterally tapered toward the channel region between the first and second epitaxial patterns340aand340b.

In some embodiments, the first epitaxial pattern340amay further include an additional tapered portion CTSa filling the additional tapered undercut region RTSa of the first recess regions335a. The second epitaxial pattern340bmay further include additional tapered portions CTUb and CTLb filling the additional tapered undercut regions RTUb and RTLb of the second recess region335b, respectively. In other embodiments, the additional tapered portions CTSa, CTUb, and CTLb of the first and second epitaxial patterns340aand340bmay be omitted.

Subsequently, the interlayer dielectric layer145and the contact plugs147aand147billustrated inFIG. 10Amay be formed. In some embodiments, the technique described with reference toFIGS. 4A through 4Dmay be applied to the present embodiment.

In the present embodiment, characteristics of the transistor may be optimized using the vertical implantation method and the tilt implantation method.

In addition, in the present embodiment in which the first amorphous region325ais asymmetric to the second amorphous region325babout the channel region, the removal process used in the formation of the concave regions330aand330bmay be performed by other methods. In some embodiments, the phase change regions327aand327bmay be removed by an isotropic dry etching process. In other embodiments, the annealing process may be omitted and the first and second amorphous regions325aand325bmay be removed by the isotropic dry etching process to form the first and second concave regions330aand330b.

Next, a semiconductor device manufactured according to the present embodiment will be described with reference toFIGS. 10A and 10B.

FIG. 10Ais a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept, andFIG. 10Bis an enlarged view of a portion ‘B’ ofFIG. 10A.

Referring toFIGS. 10A and 10B, the first epitaxial pattern340aand the second epitaxial pattern340bmay fill the first recess region335aand the second recess region335bformed in the semiconductor substrate100at both sides of the gate pattern110, respectively. The first and second epitaxial patterns340aand340bmay be adjacent to both sides of the gate pattern110. Thus, the first and second epitaxial patterns340aand340band the gate pattern110on the semiconductor substrate100therebetween may be included in a transistor. The first epitaxial pattern340amay be asymmetric to the second epitaxial pattern340babout the channel region CHR under the gate pattern110. In other words, the first epitaxial pattern340amay be asymmetric to the second epitaxial pattern340babout an imaginary vertical line350which passes through a center of the channel region CHR and is perpendicular to a top surface of the semiconductor substrate100.

As illustrated inFIG. 10B, the first epitaxial pattern340amay include a plurality of first tapered portions CTUa and CTLa laterally tapered toward the channel region CHR, and the second epitaxial pattern340bmay include one second tapered portion CTSb laterally tapered toward channel region CHR. The first tapered portions CTUa and CTLa may include an upper tapered portion CTUa and a lower tapered portion CTLa.

A first depth R1of a tip of the upper tapered portion CTUa may be different from a second depth R2of a tip of the second tapered portion CTSb with respect to the top surface of the semiconductor substrate100under the gate pattern110. Additionally, a depth of a tip of the lower tapered portion CTLa may be different from the second depth R2.

In some embodiments, the first depth R1may be less than the second depth R2. In this case, the doped portion of the first epitaxial pattern340aand the first source/drain extension113amay be included in a drain region of the transistor, and the doped portion of the second epitaxial pattern340band the second source/drain extension113bmay be included in a source region of the transistor. Since the first depth R1is less than the second depth R2, the upper tapered portion CTUa of the first epitaxial pattern340amay provide sufficient compressive or tensile force to a portion of the channel region CHR adjacent to the drain region. Thus, a potential barrier of the portion of the channel region CHR adjacent to the drain region may decrease, so that the turn-on current of the transistor may increase. Additionally, since the second depth R2is greater than the first depth R1, a distance between the tip of the second tapered portion CTSb and the tip of the upper tapered portion CTUa may increase, so that the punch-through characteristic between the source region and the drain region may be improved. Additionally, the second tapered portion CTSb may also provide the compressive force or the tensile force to the channel region CHR. Moreover, the lower tapered portion CTLa may provide the compressive force or the tensile force to a lower portion of the channel region CHR. Thus, the mobility of carriers in the channel generated in the channel region CHR may be improved.

In some embodiments, a first horizontal distance Da between the tip of the upper tapered portion CTUa and the center (e.g., the imaginary vertical line350) of the channel region CHR may be different from a second horizontal distance Db between the tip of the second tapered portion CTSb and the center (e.g., the imaginary vertical line350) of the channel region CHR. If the doped portion of the first epitaxial pattern340ais included in the drain region, the first horizontal distance Da may be less than the second horizontal distance Db. A third horizontal distance between the tip of the lower tapered portion CTLa and the imaginary vertical line350may be greater than the first horizontal distance Da.

In some embodiments, the gate pattern110illustrated inFIG. 10Amay be replaced with the gate dielectric pattern180aand the gate electrode185aillustrated inFIG. 6.

FIGS. 11A through 11Eare cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept, andFIGS. 12A and 12Bare cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. The gate pattern110of the present embodiment may be fabricated using the processes described with reference toFIGS. 1A and 1B.

Referring toFIG. 11A, first amorphization element ions420amay be implanted by a vertical implantation method using the gate pattern110and the gate spacers115aas masks. Second amorphization element ions420bmay be implanted by a first tilt implantation method using the gate pattern110and the gate spacers115aas masks. Third amorphization element ions420cmay be implanted by a second tilt implantation method using the gate pattern110and the gate spacers115aas masks. Since the first, second, and third amorphization element ions420a,420b, and420care implanted into the semiconductor substrate100, a first amorphous region425aand a second amorphous region425bmay be formed in the semiconductor substrate100at both sides of the gate pattern110, respectively.

An implantation direction of the first amorphization element ions420amay be substantially the same as that of the amorphization element ions120described with reference toFIGS. 1C and 2. An implantation direction of the second amorphization element ions420bmay be substantially the same as that of the amorphization element ions220described with reference toFIG. 7A. An implantation direction of the third amorphization element ions420cmay be different from the implantation direction of the second amorphization element ions420b. In some embodiments, the implantation direction of the third amorphization element ions420cmay have an angle substantially symmetric to the implantation direction of the second amorphization element ions420bwith respect to a vertical line perpendicular to the top surface of the semiconductor substrate100. For example, the implantation direction of the second amorphization element ions420bmay have a first tilt angle in a clockwise direction from the vertical line perpendicular to the top surface of the semiconductor substrate100, and the implantation direction of the third amorphization element ions420cmay have a second tilt angle in an counterclockwise direction from the vertical line. A size of the first tilt angle may be substantially the same as that of the second tilt angle.

The implantation energy of the first amorphization element ions420amay be greater than those of the second and third amorphization element ions420band420c. The implantation energy of the second amorphization element ions420bmay be substantially the same as that of the third amorphization element ions420c.

The first amorphous region425amay include a first sidewall and a second sidewall which are opposite to each other, and the second amorphous region425bmay include a first sidewall and a second sidewall which are opposite to each other. The first sidewalls of the first and second amorphous regions425aand425bmay be adjacent to the channel region between the first and second amorphous regions425aand425b. Due to the second amorphization element ions420b, an upper portion of the first sidewall of the first amorphous region425amay laterally protrude toward the channel region more than a lower portion of the first sidewall of the first amorphous region425a. Thus, the first amorphous region425amay include a first tilt implantation region400alaterally protruding toward the channel region. Due to the third amorphization element ions420c, an upper portion of the first sidewall of the second amorphous region425bmay laterally protrude toward the channel region more than a lower portion of the first sidewall of the second amorphous region425b. Thus, the second amorphous region425bmay include a second tilt implantation region402blaterally protruding toward the channel region.

In some embodiments, an additional tilt implantation region402amay be formed at an upper portion of the second sidewall of first amorphous region425aby the third amorphization element ions420c. An additional tilt implantation region400bmay be formed at an upper portion of the second sidewall of second amorphous region425bby the second amorphization element ions420b. In other embodiments, if the second sidewalls of the first and second amorphous regions425aand425bare in contact with a device isolation pattern (not shown), the additional tilt implantation regions402aand400bmay be omitted.

A first amorphization element of the first amorphization element ions420amay include at least one of the amorphization elements used as the amorphization element ions120described with reference toFIGS. 1C and 2. A second amorphization element of the second amorphization element ions420bmay include at least one of the amorphization elements used as the amorphization element ions120described with reference toFIGS. 1C and 2. A third amorphization element of the third amorphization element ions420cmay include at least one of the amorphization elements used as the amorphization element ions120described with reference toFIGS. 1C and 2. The first, second and third amorphization elements may be the same as each other. Alternatively, the first, second and third amorphization elements may be different from each other. Each dose of the first, second and third amorphization element ions420a,420band420cmay be substantially the same as the dose of the amorphization element ions120described with reference toFIGS. 1C and 2. The first, second and third amorphization element ions420a,420band420cmay be implanted at room temperature. Alternatively, the first, second and third amorphization element ions420a,420band420cmay be implanted at the lower process temperature within the range of about −20 degrees Celsius to about −100 degrees Celsius.

Referring toFIG. 11B, an annealing process may be performed on the semiconductor substrate100including the first and second amorphous regions425aand425bto form first and second phase change regions427aand427b. The annealing process may be performed in the same way as the annealing process described with reference toFIGS. 1D and 2. In some embodiments, the annealing process may be performed at the process temperature within the range of about 350 degrees Celsius to about 450 degrees Celsius. Thus, the first and second amorphous regions425aand425bmay be fully changed to the first and second phase change regions427aand427bas illustrated inFIG. 11B.

Due to the first and second tilt implantation regions400aand402b, the first and second phase change regions427aand427bmay include first and second protruding portions405aand407blaterally protruding toward the channel region between the first and second phase change regions427aand427b, respectively. In some embodiments, due to the additional tilt implantation regions402aand400b, the first and second phase change regions427aand427bmay further include additional protruding portions407aand405b, respectively. In other embodiments, the additional protruding portions407aand405bmay be omitted.

Referring toFIG. 11C, the first and second phase change regions427aand427bmay be removed to form first and second concave regions430aand430b. The first and second phase change regions427aand427bmay be removed by the wet etching process described with reference toFIGS. 1E and 2. Since the first and second protruding portions405aand407bare removed, the first concave region430amay include a first undercut region410aprotruding toward the channel region, and the second concave region430bmay include a second undercut region412bprotruding toward the channel region. In some embodiments, if the additional protruding portions407aand405bare removed, the first and second concave regions430aand430bmay include additional undercut regions412aand410b, respectively.

Referring toFIG. 11D, the anisotropic wet etching process described with reference toFIG. 1Fmay be performed on the first and second concave regions430aand430b. As a result, first and second recess regions435aand435bmay be formed. Due to the first undercut region410a, the first recess region435amay include a first upper tapered undercut region RTU1and a first lower tapered undercut region RTL1which are laterally tapered toward the channel region. Due to the second undercut region412b, the second recess region435bmay include a second upper tapered undercut region RTU2and a second lower tapered undercut region RTL2which are laterally tapered toward the channel region.

Further, the annealing process described with reference toFIG. 11Bmay be performed at the process temperature which is greater than about 450 degrees Celsius and is equal to or less than about 650 degrees Celsius. In this case, as illustrated inFIG. 12A, portions of the first and second amorphous regions425aand425badjacent to the semiconductor substrate100may be changed to solid phase epitaxy portions EP, and first and second phase change regions427a′ and427b′ may be formed on the solid phase epitaxy portions EP. The wet etching process described with reference toFIGS. 1E and 2may be performed to remove the first and second phase change regions427a′ and427b′. Thus, first and second concave regions430a′ and430b′ illustrated inFIG. 12Bmay be formed. Subsequently, the anisotropic wet etching process described with reference toFIG. 1Fmay be performed to form the first and second recess regions435aand435billustrated inFIG. 11D.

Referring toFIG. 11E, an epitaxial process may be performed to form first and second epitaxial patterns440aand440bfilling the first and second recess regions435aand435b, respectively. The first and second epitaxial patterns440aand440bmay be formed of the same material as the first and second epitaxial patterns140aand140bdescribed with reference toFIG. 1G. The first and second epitaxial patterns440aand440bmay be doped by the same methods used for doping the epitaxial patterns140aand140bdescribed with reference toFIG. 1G.

The first epitaxial pattern440amay include a first upper tapered portion CTU1and a first lower tapered portion CTL1which are laterally tapered toward the channel region, and the second epitaxial pattern440bmay include a second upper tapered portion CTU2and a second lower tapered portion CTL2which are laterally tapered toward the channel region.

Subsequently, the interlayer dielectric layer145and the contact plugs147aand147bofFIG. 13may be formed. The technique described with reference toFIGS. 4A through 4Dmay be applied to the present embodiment.

FIG. 13is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. The semiconductor device ofFIG. 13may be fabricated according to the methods ofFIGS. 11A through 11E.

Referring toFIG. 13, the first epitaxial pattern440aand the second epitaxial pattern440bmay fill the first recess region435aand the second recess region435bformed in the semiconductor substrate100, respectively. The first and second recess regions435aand435bmay be laterally spaced apart from each other. The gate pattern110may be disposed on the channel region between the first and second epitaxial patterns440aand440b. The first epitaxial pattern440amay include the first upper and lower tapered portions CTU1and CTL1tapered toward the channel region, and the second epitaxial pattern440bmay include the second upper and lower tapered portions CTU2and CTL2tapered toward the channel region. The first upper and lower tapered portions CTU1and CTL1may be substantially symmetric to the second upper and lower tapered portions CTU2and CTL2, respectively, about the channel region.

FIGS. 14A through 14Eare cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 14A, a mask pattern505having an opening510may be formed on the semiconductor substrate100. Amorphization element ions520may be implanted through the opening510to form an amorphous region525in the semiconductor substrate100. The amorphization element of the amorphization element ions520may include at least one of the amorphization elements used as the amorphization element ions120described with reference toFIGS. 1C and 2. An implantation energy, a dose, an implantation direction and a process temperature of the amorphization element ions520may be substantially the same as the implantation energy, the dose, the implantation direction and the process temperature of the amorphization element ions120described with reference toFIGS. 1C and 2, respectively.

Referring toFIG. 14B, the mask pattern505may be removed, and the annealing process described with reference toFIGS. 1D,2and3A may be performed on the semiconductor substrate100. Thus, a phase change region527may be formed.

Referring toFIG. 14C, the phase change region527may be removed to form a concave region530. The phase change region527may be removed by the wet etching process described with reference toFIGS. 1E and 2.

Referring toFIG. 14D, a gate dielectric layer may be conformally formed on the semiconductor substrate100having the concave region530, and a gate conductive layer may be formed on the gate dielectric layer to fill the concave region530. A hard mask layer may be formed on the gate conductive layer. The hard mask layer, the gate conductive layer, and the gate dielectric layer may be successively patterned to form a gate dielectric pattern535, a gate electrode540, and a hard mask pattern545that are sequentially stacked. The gate electrode540may fill the concave region530.

Referring toFIG. 14E, source/drain regions555may be formed in the semiconductor substrate100at both sides of the gate electrode540, respectively. Gate spacers550may be formed on both sidewalls of the gate electrode540, respectively.

According to the present embodiment, a recessed channel region of a transistor may be formed using the method of forming the concave region described in the flowchart ofFIG. 2.

FIGS. 15A through 15Dare cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 15A, a mask pattern605having an opening610may be formed on the semiconductor substrate100. The mask pattern605may include an oxide and/or a nitride. Amorphization element ions620may be implanted through the opening610to form an amorphous region625defining an active portion ACT in the semiconductor substrate100. The amorphization element of the amorphization element ions620may include at least one of the amorphization elements used as the amorphization element ions120described with reference toFIGS. 1C and 2. A dose, an implantation direction and a process temperature of the amorphization element ions620may be the same as the dose, the implantation direction and the process temperature of the amorphization element ions120described with reference toFIGS. 1C and 2, respectively. In some embodiments, an implantation energy of the amorphization element ions620may be within the range of about 10 KeV to about 1 MeV. However, the inventive concept is not limited thereto.

Referring toFIG. 15B, the annealing process described with reference toFIGS. 1D,2and3A may be performed on the semiconductor substrate100including the amorphous region625, thereby forming a phase change region627.

Referring toFIG. 15C, the phase change region627may be removed to form a concave region630. The phase change region627may be removed by the wet etching process described with reference toFIGS. 1E and 2.

Referring toFIG. 15D, a device isolation layer may be formed on the semiconductor substrate100to fill the concave region630. The device isolation layer may be planarized until the mask pattern605is exposed, so that a device isolation pattern635filling the concave region630may be formed. The device isolation pattern635may define the active portion ACT. After the device isolation pattern635is formed, the mask pattern605may be removed.

Subsequently, a gate dielectric pattern638, a gate electrode640, and a hard mask pattern645that are sequentially stacked on the active portion ACT may be formed. Source/drain regions655may be formed in the active portion ACT at both sides of the gate electrode640, respectively. Gate spacers650may be formed on both sidewalls of the gate electrode640, respectively.

According to the present embodiment, the device isolation pattern635defining the active portion ACT may be formed using the method of forming the concave region described in the flowchart ofFIG. 2.

The semiconductor devices according to the above-described embodiments of the inventive concept may be realized as logic devices and/or memory devices. If the semiconductor devices according to the above-described embodiments are realized as memory devices, the transistors of the semiconductor devices may be formed in peripheral circuit regions of the memory devices.

The semiconductor devices according to the above-described embodiments may be encapsulated using various packaging techniques. For example, the semiconductor devices according to the aforementioned embodiments may be encapsulated using any one of a package on package (POP) technique, a ball grid array (BGA) technique, a chip scale package (CSP) technique, a plastic leaded chip carrier (PLCC) technique, a plastic dual in-line package (PDIP) technique, a die in waffle pack technique, a die in wafer form technique, a chip-on-board (COB) technique, a ceramic dual in-line package (CERDIP) technique, a plastic metric quad flat package (PMQFP) technique, a plastic quad flat package (PQFP) technique, a small-outline integrated circuit (SOIC) package technique, a shrink small-outline package (SSOP) technique, a thin small-outline package (TSOP) technique, a thin quad flat package (TQFP) technique, a system in package (SIP) technique, a multi-chip package (MCP) technique, a wafer-level fabricated package (WFP) technique and a wafer-level processed stack package (WSP) technique.

The package in which the semiconductor device according to one of the above-described embodiments is disposed may further include a semiconductor device (e.g., a controller and/or a logic device) that controls the semiconductor device according to the one of the above-described embodiments.

FIG. 16is a block diagram illustrating an electronic system that may include semiconductor devices according to exemplary embodiments of the inventive concept.

Referring toFIG. 16, an electronic system1100according to an exemplary embodiment of the inventive concept may include a controller1110, an input/output (I/O) unit1120, a memory device1130, an interface unit1140and a data bus1150. At least two of the controller1110, the I/O unit1120, the memory device1130and the interface unit1140may communicate with each other through the data bus1150. The data bus1150may correspond to a path through which electrical signals are transmitted.

The controller1110may include at least one of a microprocessor, a digital signal processor, a microcontroller or another logic device. The other logic device may have a similar function to any one of the microprocessor, the digital signal processor and the microcontroller. When the semiconductor devices according to the above-described embodiments are realized as logic devices, the controller1110may include at least one of the semiconductor devices according to the above-described embodiments. The I/O unit1120may include a keypad, a keyboard and/or a display unit. The memory device1130may store data and/or commands. When the semiconductor devices according to the above-described embodiments are realized as memory devices, the memory device1130may include at least one of the semiconductor devices according to above-described embodiments. Additionally, the memory device1130may further include another type of semiconductor memory device which is different from the semiconductor devices according to the above-described embodiments. For example, the memory device1130may further include a non-volatile memory device (e.g., a magnetic memory device, a phase change memory device, etc.), a dynamic random access memory (DRAM) device and/or a static random access memory (SRAM) device. The interface unit1140may transmit electrical data to a communication network or may receive electrical data from a communication network. The interface unit1140may operate wirelessly or by wire. For example, the interface unit1140may include an antenna and/or transceiver for wireless communication or a physical port for wire communication. Although not shown in the drawings, the electronic system1100may further include a fast DRAM device and/or a fast SRAM device which acts as a cache memory for improving an operation of the controller1110.

The electronic system1100may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card or other electronic products. The other electronic products may receive or transmit information data wirelessly or via wire.

FIG. 17is a block diagram illustrating a memory card that may include semiconductor devices according to exemplary embodiments of the inventive concept.

Referring toFIG. 17, a memory card1200according to an exemplary embodiment of the inventive concept may include a memory device1210. When the semiconductor devices according to the embodiments described above are realized as memory devices, the memory device1210may include at least one of the semiconductor devices according to the embodiments described above. In other embodiments, the memory device1210may further include other types of semiconductor memory devices which are different from the semiconductor devices according to the embodiments described above. For example, the memory device1210may further include a non-volatile memory device (e.g., a magnetic memory device, a phase change memory device, etc.), a DRAM device and/or an SRAM device. The memory card1200may include a memory controller1220that controls data communication between a host and the memory device1210.

The memory controller1220may include a central processing unit (CPU)1222that controls overall operations of the memory card1200. In addition, the memory controller1220may include an SRAM device1221that is used as an operation memory of the CPU1222. Moreover, the memory controller1220may further include a host interface unit1223and a memory interface unit1225. The host interface unit1223may be configured to include a data communication protocol between the memory card1200and the host. The memory interface unit1225may connect the memory controller1220to the memory device1210. The memory controller1220may further include an error check and correction (ECC) block1224. The ECC block1224may detect and correct errors in data which are read out from the memory device1210. Even though not shown in the drawings, the memory card1200may further include a read only memory (ROM) device that stores code data to interface with the host. The memory card1200may be used as a portable data storage card. Alternatively, the memory card1200may realized as a solid state disk (SSD) which may be used as a hard disk of a computer system.

According to some embodiments of the inventive concept, the amorphization element ions may be implanted to form the amorphous region and the amorphous region may be annealed to form the phase change region. Thus, an etch rate of the phase change region may increase. As a result, the phase change region may be easily removed to form the concave region.

According to other embodiments of the inventive concept, the phase change region formed in the semiconductor substrate may be removed by the wet etching process. Thus, an etch selectivity between the phase change region and the semiconductor substrate may be improved to realize a semiconductor device with improved reliability.