Interrupt latency reduction

A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a clock signal frequency can be changed that is received by the processor. An interrupt service routine can be executed that corresponds to the interrupt request.

BACKGROUND

Conventional microcontrollers typically operate at frequencies that are lower than the highest clock frequencies that are available within the device. A slower clock frequency is typically used to reduce power consumption by a central processing unit (CPU) of a microcontroller. Usually within a microcontroller there is a very fast master clock signal (e.g., 100 megahertz (MHz)) that is divided down to slower rates and distributed throughout its subunits. For example, in a typical microcontroller, the CPU may operate at only 12 MHz in order to reduce its power consumption. Note that when an interrupt is received by the CPU of the microcontroller, the CPU must complete its current task and then execute an interrupt service routine (ISR) corresponding to the received interrupt. Unfortunately, the slower clocked CPU takes longer to respond to an interrupt request. Therefore, by slowing the CPU's clock to help reduce power consumption, interrupt latency of the microcontroller is increased. It is noted that the interrupt latency is the time it takes the CPU to start executing the ISR once the interrupt is signaled. In certain applications that timing can be critical. One conventional technique for keeping that latency within an acceptable limit is to constantly operate the CPU at a higher clock frequency. However, the disadvantage of this conventional technique is an increase in power consumption by the CPU.

As such, it is desirable to address one or more of the above issues.

SUMMARY

A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a clock signal frequency can be changed that is received by the processor. An interrupt service routine can be executed that corresponds to the interrupt request.

DETAILED DESCRIPTION

Reference will now be made in detail to various embodiments in accordance with the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with various embodiments, it will be understood that these various embodiments are not intended to limit the invention. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the invention as construed according to the Claims. Furthermore, in the following detailed description of various embodiments in accordance with the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be evident to one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the invention.

Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present detailed description, discussions utilizing terms such as “detecting”, “changing”, “switching”, “determining”, “increasing”, “decreasing”, “storing”, “receiving”, “executing”, “setting”, “programming”, “utilizing”, “resuming”, “producing”, “beginning”, “completing”, “outputting”, “transmitting”, or the like, can refer to the actions and processes of a processor(s) and/or electrical components, an electronic and/or electrical computing device, but is not limited to such. The computing device can manipulate and transform data represented as physical (electronic) quantities within the computing device's registers and/or memories into other data similarly represented as physical quantities within the computing device memories and/or registers or other such information storage or transmission.

FIG. 1is a block diagram of an exemplary integrated circuit100in accordance with various embodiments of the invention. It is noted that the integrated circuit100can be implemented in a wide variety of ways. For example in an embodiment, the integrated circuit100can be implemented as, but is not limited to, a microcontroller, a microprocessor, and the like. The integrated circuit100can include, but is not limited to, a clock system102, a clock controller104, an oscillator106, a frequency multiplier108, divider circuits110,112and114, a processor116, an interrupt controller120, and other digital systems118.

Specifically, in one embodiment, one of the functions of the clock system102is to reduce the interrupt latency of the integrated circuit100. It is noted that in an embodiment, the interrupt latency can be the time it takes the processor116to start executing an interrupt service routine once an interrupt signal or request (e.g.,122) is detected or received by the interrupt controller circuit120. Upon detection of the interrupt signal or request122, the clock rate (or frequency) to the processor116can be dynamically increased by the clock system102in order to decrease the interrupt latency of the integrated circuit100. The clock controller104of the clock system102can be utilized to select between a normal clock rate (or frequency) and a faster clock rate for the processor116. The clock controller104can be controlled by the interrupt controller120. Upon detection of an interrupt, the interrupt controller120can cause the clock system102to supply the faster clock signal to the processor116. Note that in an embodiment, this faster clock signal can be maintained throughout the operation of the associated interrupt service routine. In one embodiment, the faster clock signal can be supplied to the processor116just during the latency period, depending on the power constraints of the integrated circuit100. Note that one of the advantages is the reduction of the interrupt latency while still offering reduced power consumption.

WithinFIG. 1, it is pointed out that the clock controller104can change the clock signal rate or frequency received by the processor116(and possibly the other digital systems118of the integrated circuit100) in a wide variety of ways. For example, the clock controller104can dynamically change or modify the operation of the oscillator106, frequency multiplier108, divider circuit110, divider circuit112, and divider circuit114separately or in any type of combination. In one embodiment, if the oscillator106is as a crystal-less programmable oscillator, the clock controller104can dynamically increase or decrease the output clock signal frequency of the oscillator106. Furthermore, if the frequency multiplier108is implemented as a variable multiplication factor frequency multiplier, the clock controller104can dynamically increase or decrease the multiplying function of the frequency multiplier108thereby causing its output clock signal frequency to increase or decrease. Moreover, if each of the divider circuits110-114is implemented as a variable divider, the clock controller104can dynamically changing the divide ratio of each of the divider circuits110,112and114thereby causing each output clock signal frequency to increase or decrease.

The oscillator106can be implemented in a wide variety of ways. For example, the oscillator106can be, but is not limited to, a crystal oscillator, an internal oscillator inside the integrated circuit100, crystal-less programmable oscillator, it could be a quartz crystal oscillator with an external quartz crystal setting the frequency, or a ceramic resonator oscillator with an external ceramic resonator setting the frequency. The processor116can be implemented in a wide variety of ways. For example, the processor116can be implemented as a central processing unit (CPU), but is not limited to such. The frequency multiplier108can be implemented in a wide variety of ways. For example, the frequency multiplier108can be implemented as a phase lock loop (PLL), but is not limited to such.

WithinFIG. 1, in one embodiment, the clock controller104can be implemented to store two complete sets of clock configurations for controlling the other elements of the clock system102: one set of clock configurations for normal operation and another set of clock configurations for interrupt operation. In this manner, each set can include a desired combination of configurations for each of the elements of the clock system102to achieve the optimal frequency for each of the processor116and each of the other digital systems118in each operation mode.

For example in an embodiment, it may be desirable that the clock frequency signals output by the dividers112and114remain the same for both the normal operation configuration and the interrupt operation configuration while the divider110outputs two different clock frequency signals to the processor116. For instance in one embodiment, the normal operation configuration stored by the clock controller104can include the oscillator106being set at 12 megahertz (MHz), the frequency multiplier108may be set to multiply by 3, the divider110for the processor116can be set to divide by 3, the divider112can be set to divide by 4, and the divider114can be set to divide by 6. As such, during the normal operation configuration the processor116is receiving a 12 MHz clock signal, the divider112is outputting a 9 MHz clock signal to the other digital systems118, and the divider114is outputting a 6 MHz clock signal to the other digital systems118.

Furthermore, in one embodiment, the interrupt operation configuration stored by the clock controller104can include the oscillator106being set at 54 MHz, the frequency multiplier108may be set to multiply by 4, the divider110for the processor116can be set to divide by 2, the divider112can be set to divide by 24, and the divider114can be set to divide by 36. As such, during the interrupt operation configuration the processor116is receiving a 108 MHz clock signal, the divider112is still outputting a 9 MHz clock signal to the other digital systems118, and the divider114is still outputting a 6 MHz clock signal to the other digital systems118. In this manner, there are two complete groups of settings and when the interrupt is detected, a seamless change can be made from one group of settings to another. Additionally in this embodiment, the clock frequencies received by the other digital systems118may remain the same while the clock frequency signal received by the processor116is increased during the interrupt operational mode.

WithinFIG. 1, it is noted that the clock system102can be implemented in a wide variety of ways. For example in one embodiment, the clock system102can be implemented not to include any dividers and frequency multipliers while including the clock controller104and the oscillator106(that is programmable), which can be coupled to the processor116and possibly to the other digital systems118of the integrated circuit100. As such, the clock controller104can dynamically increase or decrease the output clock frequency signal of the oscillator116. In an embodiment, the clock system102can be implemented not to include any dividers while including the oscillator106and one or more frequency multipliers (e.g.,108), which can each be coupled to the processor116and possibly to the other digital systems118of the integrated circuit100. In one embodiment, the clock system102can be implemented not to include any frequency multipliers while including the oscillator106and one or more dividers110,112and114, which can each be coupled to the processor116and possibly to the other digital systems118as shown.

The integrated circuit100can include, but is not limited to, the clock system102that can be coupled to the processor116and the other digital systems118. The clock system102can include, but is not limited to, the clock controller104, the oscillator106, the frequency multiplier108, and the divider circuits110,112and114. Specifically, the clock controller104can be coupled to the oscillator106, the frequency multiplier108, the interrupt controller120, and the divider circuits110,112and114. An output of the oscillator106can be coupled to an input of the frequency multiplier108. An output of the multiplier108can be coupled to an input of divider circuit110, an input of divider circuit112, and an input of divider circuit114. An output of the divider circuit110can be coupled to a clock input of the processor116. An output of the divider circuit112can be coupled to one or more other digital systems118of the integrated circuit100. An output of the divider circuit114can be coupled to one or more other digital systems118of the integrated circuit100. An output of the interrupt controller circuit120can be coupled to an input of the processor116thereby enabling the processor116to receive the interrupt request122from the interrupt controller120. The processor116and the interrupt controller120are coupled to communicate.

WithinFIG. 1, it is understood that the integrated circuit100may not include all of the elements illustrated byFIG. 1. Additionally, the integrated circuit100can be implemented to include one or more elements not illustrated byFIG. 1.

FIG. 2is an exemplary timing diagram200in accordance with various embodiments of the invention. Note thatFIGS. 1 and 2will be discussed together in order to provide a more complete understanding of various embodiment of the invention. WithinFIG. 2, the processor116can be executing an instruction stream202that includes multiple instructions, such as, Instruction (Instr) N−1, Instruction N, Instruction N+1, and so forth. After execution of Instruction (Instr) N−1, the processor116begins execution of Instruction N. While executing Instruction N, the interrupt controller120can detect or receive an interrupt request204(as shown inFIG. 2). As such, the interrupt controller120outputs an interrupt request signal122to the processor116. Once the processor116completes the execution of Instruction N, the processor116notifies the interrupt controller120of this situation. As such, as shown by arrow206, the interrupt controller120can cause the clock controller104to increase the clock signal rate received by the processor116, as indicated by change clock208.

In an embodiment, once the clock signal frequency is increased to the processor116, the processor116can store the program counter (PC) and one or more status flags210that are associated with the instruction stream202. In one embodiment, while the clock signal frequency to the processor116is changing (e.g., being increased), the processor116can store the program counter (PC) and one or more status flags210that are associated with the instruction stream202. It is noted that the program counter and the one or more status flags can be subsequently used by the processor116to return to the point at which it stopped executing the instruction stream202. Once the program counter and the one or more status flags are stored210, the processor116can execute the interrupt service routine212corresponding with the interrupt request204. Next, the processor116can perform a restore214of the program counter and the status flags associated with the instruction stream202, thereby enabling the processor116to return and begin executing the instruction stream202. The processor116notifies the interrupt controller120of this situation. As such, the interrupt controller120can cause the clock controller104to decrease the clock signal rate or frequency received by the processor116, as indicated by change clock216. Arrow218indicates that the processor116can begin executing Instruction N+1 of the instruction stream202. When implemented in this manner, the interrupt latency220can be reduced while still enabling reduced power consumption by the processor116.

WithinFIG. 2, it is noted that the occurrence of the change (or decrease) clock rate216to the processor116can take place at a different location of timing diagram200. For example in one embodiment, the occurrence of the change (or decrease) clock rate216to the processor116can take place after the storing of the program counter and the one or more status flags210that are associated with the instruction stream202. In this manner, the execution by the processor116of the interrupt service routine212and the restoring214of the program counter and the status flags associated with the instruction stream202will occur at the slower or normal clock frequency or rate.

FIG. 3is an exemplary timing diagram300in accordance with various embodiments of the invention. Note thatFIGS. 1 and 3will be discussed together in order to provide a more complete understanding of various embodiment of the invention. WithinFIG. 3, the processor116can be executing an instruction stream202that includes multiple instructions, such as, Instruction (Instr) N−1, Instruction N, Instruction N+1, and so forth. After execution of Instruction (Instr) N−1, the processor116begins executing Instruction N. While executing Instruction N, the interrupt controller120can detect or receive an interrupt request204(as shown inFIG. 3). As such, the interrupt controller120outputs an interrupt request signal122to the processor116and causes the clock controller104, as shown by arrow302, to increase the clock signal rate received by the processor116, as indicated by change clock304.

Once the clock signal frequency is increased to the processor116, the processor116can store the program counter (PC) and one or more status flags306that are associated with the instruction stream202. It is pointed out that the program counter and the one or more status flags can be subsequently used by the processor116to return to the point at which it stopped executing Instruction N of the instruction stream202. Once the program counter and the one or more status flags are stored306, the processor116can execute the interrupt service routine308corresponding with the interrupt request204. Next, the processor116can perform a restore310of the program counter and the status flags associated with Instruction N of the instruction stream202, thereby enabling the processor116to resume executing Instruction N at the point it stopped executing it. The processor116notifies the interrupt controller120of this situation. As such, the interrupt controller120can cause the clock controller104to decrease the clock signal rate or frequency received by the processor116, as indicated by change clock312. Arrow314indicates that the processor116can resume executing the remainder of Instruction N of the instruction stream202. When implemented in this manner, the interrupt latency316can be reduced while still enabling reduced power consumption by the processor116. Note that the interrupt latency316ofFIG. 3is shorter in duration that the interrupt latency220ofFIG. 2. Specifically, the reduction in time of the interrupt latency316is the result of not waiting for the processor116to finish executing Instruction N of the instruction stream202before increasing the clock frequency to processor116.

FIG. 4is a block diagram of an exemplary integrated circuit400in accordance with various embodiments of the invention. It is noted that the integrated circuit400can be implemented in a wide variety of ways. For example in an embodiment, the integrated circuit400can be implemented as, but is not limited to, a microcontroller, a microprocessor, and the like. The integrated circuit400can include, but is not limited to, a clock system402, an oscillator404, a clock generation and distribution circuit406, a clock multiplier circuit408, a multiplexer (MUX)410, an interrupt controller circuit412, a processor414, and other digital systems418of the integrated circuit400. In one embodiment, the clock multiplier408may comprise a single clock doubler, but is not limited to such.

Specifically, in one embodiment, one of the functions of the clock system402is to reduce the interrupt latency of the integrated circuit400. Note that in an embodiment, the interrupt latency can be the time it takes the processor414to start executing an interrupt service routine once an interrupt signal or request (e.g.,416) is detected or received by the interrupt controller circuit412. Upon detection of the interrupt signal or request416, the clock rate (or frequency) to the processor414can be dynamically increased by the clock system402in order to decrease the interrupt latency of the integrated circuit400. The multiplexer410of the clock system402can be utilized by the interrupt controller412to select between a normal clock rate (or frequency) and a faster clock rate for the processor414. The multiplexer410can be controlled by the interrupt controller412. Upon detection of an interrupt, the interrupt controller412can cause the clock system402to supply the faster clock signal to the processor414. It is pointed out that in an embodiment, this increased clock signal can be maintained throughout the operation of the associated interrupt service routine. In one embodiment, the increased clock signal can be supplied to the processor414just during the latency period, depending on the power constraints of the integrated circuit400. It is noted that one of the advantages is the reduction of the interrupt latency while still offering reduced power consumption.

WithinFIG. 4, the oscillator404can output a clock frequency signal that can be received by the clock generation and distribution circuit406. It is noted that the clock generation and distribution circuit406can be implemented in a wide variety of ways. For example, the clock generation and distribution circuit406can be implemented with, but is not limited to, one or more frequency multipliers (e.g.,108), one or more variable divider circuits (e.g.,110,112and/or114), and the like. It is pointed out that one or more outputs of the clock generation and distribution circuit406can be coupled to the other digital systems418of the integrated circuit400. Furthermore, the clock generation and distribution circuit406can output a clock frequency signal to the clock multiplier circuit408and the multiplexer410. In one embodiment, the clock multiplier circuit408can then double the frequency of the clock signal received from the clock generation and distribution circuit406. As such, the clock multiplier circuit408can output the doubled frequency clock signal to the multiplexer410. Depending on the control signals received from the interrupt controller412, the multiplexer410either outputs to the processor414the clock frequency signal received from the clock generation and distribution circuit406or the doubled frequency clock signal received from the clock multiplier circuit408. It is noted that in an embodiment, the clock multiplier circuit408can be implemented to multiple the frequency of the received clock signal by any factor or value.

The oscillator404can be implemented in a wide variety of ways. For example, the oscillator404can be, but is not limited to, a crystal oscillator, an internal oscillator inside the integrated circuit400, it could be a quartz crystal oscillator with an external quartz crystal setting the frequency, or it could be a ceramic resonator oscillator with an external ceramic resonator setting the frequency. The processor414can be implemented in a wide variety of ways. For example, the processor can be implemented as a central processing unit (CPU), but is not limited to such.

WithinFIG. 4, the integrated circuit400can include, but is not limited to, the clock system402that can be coupled to the processor414, the interrupt controller circuit412, and the other digital systems418. The clock system402can include, but is not limited to, the oscillator404, the clock generation and distribution circuit406, the clock multiplier circuit408, and the multiplexer410. Specifically, an output of the oscillator404can be coupled to an input of the clock generation and distribution circuit406. An output of the clock generation and distribution circuit406can be coupled to an input of the clock multiplier circuit408and a first input of the multiplexer410. One or more outputs of the clock generation and distribution circuit406can be coupled to one or more other digital systems418of the integrated circuit400. An output of the clock multiplier circuit408can be coupled to a second input of the multiplexer410. An output of the multiplexer410can be coupled to a clock input of the processor414. A first output of the interrupt controller circuit412can be coupled to a controller input of the multiplexer410. A second output of the interrupt controller circuit412can be coupled to an input of the processor414.

WithinFIG. 4, it is understood that the integrated circuit400may not include all of the elements illustrated byFIG. 4. Additionally, the integrated circuit400can be implemented to include one or more elements not illustrated byFIG. 4.

FIG. 5is a flow diagram of a method500in accordance with various embodiments of the invention for reducing interrupt latency for an integrated circuit (e.g., microcontroller, microprocessor, or the like). Method500includes exemplary processes of various embodiments of the invention which can be carried out by a processor(s) and/or electrical components under the control of computing device readable and executable instructions (or code), e.g., software. The computing device readable and executable instructions (or code) may reside, for example, in data storage features such as volatile memory, non-volatile memory and/or mass data storage that are usable by a computing device. However, the computing device readable and executable instructions (or code) may reside in any type of computing device readable medium. Although specific operations are disclosed in method500, such operations are exemplary. Method500may not include all of the operations illustrated byFIG. 5. Also, method500may include various other operations and/or variations of the operations shown byFIG. 5. Likewise, the sequence of the operations of method500can be modified. It is noted that the operations of method500can be performed by software, by firmware, by electronic hardware, by electrical hardware, or by any combination thereof.

Specifically, method500can include a processor of an integrated circuit beginning execution of an instruction (e.g., of an instruction stream). After the instruction is executed, it can be determined whether an interrupt request has been detected. If not, the processor can begin executing the next instruction. However, if an interrupt request has been detected, the clock speed can be increased (or changed) to at least the processor and possibly to other components of the integrated circuit. The program counter and status flags associated with the instruction stream being executed by the processor can be stored for later retrieval. The processor can execute the interrupt service routine (ISR) corresponding to the detected (or received) interrupt request. Once the interrupt service routine has been executed, the program counter and the status flags associated with the instruction stream can be restored. The clock speed that is received by the processor (and possibly other components) can be decreased (or changed) to the original clock speed. The processor can begin executing the next instruction of the instruction stream that was previously interrupted. In this manner, the interrupt latency can be reduced while still enabling reduced power consumption by the processor.

At operation502ofFIG. 5, a processor (e.g.,116or414) of an integrated circuit (e.g.,100or400) can begin executing an instruction, e.g., of an instruction stream202. Note that operation502can be implemented in a wide variety of ways. For example, operation502can be implemented in any manner similar to that described herein, but is not limited to such.

At operation504, after execution of the instruction, it can be determined whether an interrupt request (e.g.,204) has been detected or received. If not, the process500can proceed to operation502where the processor can begin executing the next instruction. However, if an interrupt request has been detected or received at operation504, the process500can proceed to operation506. It is pointed out that operation504can be implemented in a wide variety of ways. For example, operation504can be implemented in any manner similar to that described herein, but is not limited to such.

At operation506ofFIG. 5, a clock signal frequency or speed can be increased or changed (e.g.,208) that is received by at least the processor and possibly other components (e.g.,118or418) of the integrated circuit. It is noted that operation506can be implemented in a wide variety of ways. For example in one embodiment, the supply voltage to the core of an integrated circuit can be increased in enable the clock frequency signal to be set to a maximum possible frequency or rate of the integrated circuit. For instance in an embodiment, an interrupt controller (e.g.,120or412) can be implemented to control both the core supply voltage to the integrated circuit in addition to controlling the clock frequency. Note that the operation506can be implemented in any manner similar to that described herein, but is not limited to such.

At operation508, a program counter and one or more status flags (e.g.,210) associated with the instruction stream being executed by the processor can be stored, for example, for later retrieval. Note operation508can be implemented in a wide variety of ways. For example, operation508can be implemented in any manner similar to that described herein, but is not limited to such.

At operation510ofFIG. 5, the processor can execute the interrupt service routine (e.g.,212) corresponding to the detected or received interrupt request. It is pointed out that that operation510can be implemented in a wide variety of ways. For example, operation510can be implemented in any manner similar to that described herein, but is not limited to such.

At operation512, once the interrupt service routine has been executed, the program counter and the one or more status flags associated with the instruction stream can be restored (e.g.,214). It is noted that operation512can be implemented in a wide variety of ways. For example, operation512can be implemented in any manner similar to that described herein, but is not limited to such.

At operation514ofFIG. 5, the clock signal frequency or speed that is received by the processor (and possibly other components) can be decreased or changed (e.g.,216) to the original clock frequency or to another clock frequency. Note that operation514can be implemented in a wide variety of ways. For example, operation514can be implemented in any manner similar to that described herein, but is not limited to such. At the completion of operation514, the process500can proceed to operation502so that the processor can begin executing another instruction, e.g., of the instruction stream that was previously interrupted. In one embodiment, at the completion of operation514, process500can be exited.

FIG. 6is a flow diagram of a method600in accordance with various embodiments of the invention for reducing interrupt latency for an integrated circuit (e.g., microcontroller, microprocessor, or the like). Method600includes exemplary processes of various embodiments of the invention which can be carried out by a processor(s) and/or electrical components under the control of computing device readable and executable instructions (or code), e.g., software. The computing device readable and executable instructions (or code) may reside, for example, in data storage features such as volatile memory, non-volatile memory and/or mass data storage that are usable by a computing device. However, the computing device readable and executable instructions (or code) may reside in any type of computing device readable medium. Although specific operations are disclosed in method600, such operations are exemplary. Method600may not include all of the operations illustrated byFIG. 6. Also, method600may include various other operations and/or variations of the operations shown byFIG. 6. Likewise, the sequence of the operations of method600can be modified. It is noted that the operations of method600can be performed by software, by firmware, by electronic hardware, by electrical hardware, or by any combination thereof.

Specifically, method600can include a processor of an integrated circuit can be executing instructions (e.g., of an instruction stream). An interrupt request can be detected or received during the execution of an instruction. Once the interrupt request is detected or received, the clock speed can be increased (or changed) to at least the processor and possibly to other components of the integrated circuit. The program counter and status flags associated with the instruction that was being executed by the processor can be stored for later retrieval. The processor can execute the interrupt service routine (ISR) corresponding to the detected or received interrupt request. Once the interrupt service routine has been executed, the program counter and the status flags associated with the instruction that was interrupted can be restored. The clock speed that is received by the processor (and possibly other components) can be decreased (or changed) to the original clock speed or to another clock speed. The processor can resume execution of the interrupted instruction. Once the instruction is completed, the processor can continue to execute instructions (e.g., of the instruction stream). In this manner, the interrupt latency can be reduced while still enabling reduced power consumption by the processor.

At operation602ofFIG. 6, a processor (e.g.,116or414) of an integrated circuit (e.g.,100or400) can be executing instructions, e.g., of an instruction stream202. Note that operation602can be implemented in a wide variety of ways. For example, operation602can be implemented in any manner similar to that described herein, but is not limited to such.

At operation604, an interrupt request (e.g.,204) can be detected or received during the execution of an instruction by the processor. It is pointed out that operation604can be implemented in a wide variety of ways. For example, operation604can be implemented in any manner similar to that described herein, but is not limited to such.

At operation606ofFIG. 6, once the interrupt request is detected or received, a clock signal frequency (or speed) can be increased or changed (e.g.,304) that is received by at least the processor and possibly other components (e.g.,118or418) of the integrated circuit. It is noted that operation606can be implemented in a wide variety of ways. For example, operation606can be implemented in any manner similar to that described herein, but is not limited to such.

At operation608, a program counter and one or more status flags (e.g.,306) associated with the instruction that was being executed by the processor can be stored, for example, for later retrieval. Note operation608can be implemented in a wide variety of ways. For example, operation608can be implemented in any manner similar to that described herein, but is not limited to such.

At operation610ofFIG. 6, the processor can execute an interrupt service routine (e.g.,308) corresponding to the detected or received interrupt request. It is pointed out that that operation610can be implemented in a wide variety of ways. For example, operation610can be implemented in any manner similar to that described herein, but is not limited to such.

At operation612, once the interrupt service routine has been executed, the program counter and the one or more status flags associated with the instruction that was interrupted can be restored (e.g.,310). It is noted that operation612can be implemented in a wide variety of ways. For example, operation612can be implemented in any manner similar to that described herein, but is not limited to such.

At operation614ofFIG. 6, the clock signal frequency or speed that is received by the processor (and possibly other components) can be decreased or changed (e.g.,312) to the original clock signal frequency or to another clock signal frequency. Note that operation614can be implemented in a wide variety of ways. For example, operation614can be implemented in any manner similar to that described herein, but is not limited to such.

At operation616, the processor can resume execution of the interrupted instruction. It is pointed out that that operation616can be implemented in a wide variety of ways. For example, operation616can be implemented in any manner similar to that described herein, but is not limited to such. At the completion of operation616, the process600can proceed to operation602to continue executing instructions. In one embodiment, at the completion of operation616, process600can be exited.

The foregoing descriptions of various specific embodiments in accordance with the invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The invention can be construed according to the Claims and their equivalents.