ROM segmented bitline circuit

A bitline structure for use in a memory device may be connected to a plurality of bit memory cells. The bitline may be segmented into segments connected to one-third of the plurality of bit memory cells and two-thirds of the bit memory cells, respectively. The segments may be electrically coupled to each other to provide an overall bitline output.

BACKGROUND OF THE INVENTION

In deep submicron technology, System-on-Chip (SoC) products may require a high-speed and low-power embedded memory to support increasing storage capability. Both random access memory (RAM) and read only memory (ROM) have been widely used. ROM may be dedicated to read operation with non-volatile stored data which is essential for boot-up processing.

The search for higher capacity and higher speed memory has intensified over the years. However, there is an evident tradeoff between the capacity and the speed. The higher the capacity, the slower the access speed.

DESCRIPTION OF THE RELATED ART

An approach to improve the performance and power consumption of a dynamic logic circuit with a bitline repeater circuit has been described in U.S. Pat. No. 6,084,810. In the prior art, an inverter R1ofFIG. 1is inserted at a mid-point of the said bitline to speed up bitline access while reducing power. The prior art also claims that transistor T1of bitline circuitFIG. 1increases performance slightly by lowering the discharge constant slightly.

SUMMARY OF EMBODIMENTS OF THE INVENTION

Embodiments of the present invention may relate to a design technique to improve the power and the access speed of a higher capacity ROM. The proposed technique may be applicable for other type of memories.

An embodiment of the invention may comprise a circuit that includes wordlines and bitlines, which may be found, e.g., in a conventional memory design; a programmable memory array; bitline segmentation at ⅓ of the said bitline; a precharge circuit inserted right before the bitline segmentation; and a bitline keeper connected in series with a shutdown transistor.

The listed features may provide improved performance and decreased power consumption compared to prior art and conventional memory circuits. Other features and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings.

FIG. 2illustrates a bitline circuitry related to various examples of embodiments of the present invention. This circuit may include a programmable ROM array whose bit cells may correspond to transistors,101,102,103,110,111,112(and possibly further or fewer cells/transistors), precharge transistors104and113, bitline keeper transistors106and115, shutdown transistors105,107,114and116, wordlines124,125,126,127,128and129(and possibly further or fewer wordlines), inverter108, output driver117and a bitline, shown segmented into bitlines A and B.

In a programmable ROM array, the content of the ROM block may be customized by a custom via layer, e.g., similar to what may be described in U.S. Pat. No. 7,157,937. Via sites118,119,120,121,122and123signify possible connections between the N-channel field effect transistors (NFETs) and the bitline. The presence of a via at a respective via site signifies that the respective NFET is connected between bitline and ground. When the wordline of the programmed (i.e., connected) NFET is activated, the bitline will be discharged to ground through the NFET. When that happens, the ROM may read out data 1, after the inversion at output driver117.

The absence of a via at a respective via site signifies that the respective NFET is not connected to the bitline. When the wordline of such an unprogrammed NFET is activated, the bitline will not be discharged to ground through that NFET, as there is no path to ground present. The bitline will, consequently, stay at the precharge state (assuming that no other NFET is programmed and activated). When that happens, the ROM may read out data 0, after the inversion at the output driver117.

FIG. 3shows a randomly programmed ROM array. Darkened sites in the figure symbolize the presence of the selected vias200,201,202and203. In this example, when wordline124is activated, the readout data is 1. In contrast, when wordline125is activated, the readout data is 0.

A read operation may commence when the wordline is activated. After the wordline is activated, the bitline may take a period of time to fully discharge to ground. The period of time taken may depend on the bitline capacitance. By partitioning the bitline into smaller portions, it may reduce the bitline capacitance proportionally. When wordline124is activated, BITLINE A may start to discharge to ground. Since BITLINE A is ⅓ of the total bitline, the time taken by BITLINE A to be discharged to ground will be reduced, and the reduction may be proportionally to the reduction in bitline length (i.e., by approximately ⅔, when BITLINE A is ⅓ of the total bitline). Additionally, an RC time constant of BITLINE A will be reduced, and this reduction may correspond to the square of the line length reduction. When BITLINE A goes to 0, the NET A goes to 1. A PFET to NFET ratio of inverter108can be skewed in such a way that the PFET has much larger drive strength and hence can switch to 1 faster.

NFET109is a transistor that may be used to pull BITLINE B down to ground. In accordance with features of this invention, the gate width of NFET109may be sized up to approximately 3× (or more) that of other pulldown NFETs, e.g.,101,102,103,110,111and112, without causing significant increase to the overall layout area and power. Increase the gate width of NFET109may increase its drive strength and significantly reduce the time taken to discharge BITLINE B.

In accordance with features of various embodiments of this invention, bitline segmentation does not need an additional NFET connecting the first bitline partition to the second bitline partition, as found in T1ofFIG. 1in the prior art. The extra NFET is a liability because it creates extra RC (delay) to BITLINE A, thus slowing down the discharge of BITLINE A. In contrast, the example ofFIG. 2may permit one to increase the drive strength of NFET109, which may thus speed up the discharge of BITLINE B.

In the example ofFIG. 2, during precharge cycle, precharge transistors104and113are activated. BITLINE A and BITLINE B will be charged up to a voltage corresponding to a logical 1. When BITLINE A goes to 1, the NET A may go to 0 (or a voltage corresponding to a logical 0), turning off NFET109. NFET109may advantageously be turned off fast enough to avoid crowbar current. In accordance with features of various embodiments of this invention, of the two precharge transistors104and113, precharge transistor104may advantageously be placed closer to the inverter108, and precharge113may advantageously be placed further from inverter108. In other words, the first precharge transistor104of the first bitline partition would thus be placed close to the end of the first bitline segmentation, and the second precharge transistor113would thus be placed close to the end of the second bitline segmentation. Positioning precharge transistor104close to inverter108may thus enable NFET109to be turned off before the drain of the NFET109is charged up to 1 by the precharge transistor113, which is positioned at the far end of the bitline inFIGS. 2 and 3. This arrangement may eliminate the need for footer devices or separate select (S1through S32) and data (D1through D32) devices, as in the prior art. With a single bitline pulldown device (101through112), the bitline discharge may be faster with a corresponding device size. This arrangement can also enable a low power version by reducing the size of the bitline pulldown devices (101through112) for the same speed as the prior art while reducing chip area for cost reduction.

In accordance with features that may be found in various embodiments of this invention, during the long cycles of idling, shutdown transistors105,107,114and116can be turned off to save power. By cutting off the power supply to the megabit or gigabit ROM transistors, it may potentially reduce the static current by, e.g., 80%.

The bitline keepers106and115may be used to maintain the bitline at level1when the ROM is not being accessed. The strength of bitline keeper may not be too strong to limit the contention that may impact the discharge rate of the bitline during a read operation. One way to weaken the transistor strength is to increase the gate length. However, increasing the gate length of bitline keepers106and115may increase the loading of inverter108and may reduce the overall speed. In accordance with features of various embodiments of this invention, the gate length of the shutdown transistors107and116, which are placed in series with bitline keepers106and115, may be increased to gate lengths that will maintain the bitline at a high level while reading a “0” and, at the same time, may serve to minimize the contention between the pulldown bit while reading a “1”. Increasing the gate length of shutdown transistors107and116may increase the effective gate length in series with the bitline keepers106and115without impacting the overall speed, since the extra capacitance of the gates of transistors107and116is not seen by inverters108and117, respectively, which are in the critical path of the read operation in the examples ofFIGS. 2 and 3.

In the example ofFIG. 4, when WL[0]300is activated, BITLINE A304will start to discharge to ground. Since BITLINE A is ⅓ of the total bitline, the time taken by BITLINE A to discharge to ground,308will be reduced proportionally. When BITLINE A goes to 0, the NET A goes to 1. When NET A goes to 1, the NFET109turns on, and BITLINE B starts to discharge to 0. The time taken for BITLINE B to discharge the remaining ⅔ of the bitline to ground is labelled as310. Since NFET109has a3X higher drive strength, the discharge time310is less than that of312.312is the time taken by NFET110to discharge BITLINE B to ground. NFETs101,102,103,110,111and112may usually have a small gate width to minimize the power and reduce layout area. Hence, the time taken by312may be significantly longer than that of310. Furthermore, the RC time constant of BITLINE B is also reduced, in view of the fact that BITLINE B is only ⅔ the original bitline length, which may thus speed up signal propagation to inverter117.

In the context of this discussion, the access time is referring to the time measured from the activation of the wordline to the time output appears at the output driver117. In accordance with features of various embodiments of this invention, the bitline may be partitioned or segmented into bitline segments corresponding to ⅓ and ⅔ of total bitline length (in terms of bit cells of the ROM array, e.g., transistors101,102, etc., ofFIGS. 2 and 3). Partitioning the bitline to ⅓ and ⅔ may balance out the access times314and315. Access time314is a summation of308,309,310and311. Access time315is a summation of312and313. Even though from WL[0] to OUT of the first bitline partition passes through more delay stages, the total delay is similar to that of WL[X] to OUT of the second bitline partition. This is due to faster BITLINE B discharge in the former case.

If, for example, the bitline is partitioned into ½ and ½ instead, the access time from WL[0] to OUT of the first bitline partition may generally be significantly slower than that of WL[X] to OUT of the second bitline partition. This may thus result in a slower overall ROM access time. If the bitline is partitioned into ¼ and ¾ instead, the access time from WL[X] to OUT of the second bitline partition may generally be much slower than that of WL[0] to OUT of the first bitline partition, which may also result in a slower overall ROM access time.

FIG. 5is an illustration of a bitline segmented into ⅓ and ⅔ in accordance with various embodiments of the present invention. In contrast,FIG. 6is an illustration of bitline segmented into ½ and ½. In both illustrations,FIGS. 5 and 6, there are 512 pull down NFET per bitline shown.

FIG. 7presents simulation data of the delay for each stage when WL[0], WL[192] and WL[256] are activated. The wordlines are mutually exclusive of each other, and hence each of them is activated at a different cycle. The unit of measurement of the delay shown inFIG. 7is in picoseconds (ps). The data of the ⅓ segmentation is in accordance with the example circuit illustrated inFIG. 5while the data of the ½ segmentation is in accordance with the example circuit illustrated inFIG. 6. From the simulation results shown inFIG. 7, the circuit inFIG. 5gives a worst-case access time of 688.9 ps, while the circuit inFIG. 6gives a worst-case access time of 782 ps. This demonstrates that ⅓ bitline partition ofFIG. 5is faster than the ½ bitline partition ofFIG. 6.

In the above discussion, the proportions of the two bitline segments are discussed, e.g., as being ⅓ and ⅔. However, in many practical devices, the number of bit cells is not divisible by 3. Hence, an exact segmentation of ⅓ and ⅔ may not be possible. In such cases, the number of bit cells may be divided by three, and the smaller (“⅓”) segment may have the resulting number of bit cell connections, rounded up to the nearest whole number (and similarly, the longer (“⅔”) segment may correspond to ⅔, rounded down). For example, for a bitline serving 512 bits, 512 divided by 3 is approximately 170.67. In this case the “⅓” segment may be set at a length of 171, and the “⅔” segment may be set at a length of 341.

Additionally, significant performance improvements over other bit segmentations are obtained for not only the ⅓-⅔ segmentation (as described above), but also for a range around the ⅓-⅔ segmentation. In particular, segmentations corresponding to ⅓±5% (and the corresponding range about ⅔) may provide significant performance improvements over other segmentations (e.g., ½ and ½ or ¼ and ¾ segmentations) and may be almost as good as the ⅓-⅔ segmentation (again, with rounding as may be needed).

The above techniques may also be used as part of a method of fabricating a memory device. The method may include providing a bitline and a plurality of connections to bit memory cells, wherein the bitline is segmented as described above.

Various embodiments of the invention have now been discussed in detail; however, the invention should not be understood as being limited to these embodiments. It should also be appreciated that various modifications, adaptations, and alternative embodiments thereof may be made within the scope and spirit of the present invention. For example, one skilled in the art would understand that different signal and/or logic polarities, different transistor types and/or numbers, and/or other corresponding components may be substituted in the above examples and may provide corresponding results. Thus, again, the invention is not intended to be limited to any such particular example embodiment.