BANDWIDTH EFFICIENT INSTRUCTION-DRIVEN MULTIPLICATION ENGINE

Multiplication engines and multiplication methods are provided for a digital processor. A multiplication engine includes multipliers, each receiving a first operand and a second operand; a local operand register having locations to hold the first operands for respective multipliers; a first operand bus coupled to the local operand register to supply the first operands from a compute register file to the local operand register; a second operand bus coupled to the plurality of multipliers to supply one or more of to the second operands from the compute register file to respective multipliers; and a control unit responsive to a digital processor instruction to supply the first operands from the local operand register to respective multipliers, to supply the second operands from the compute register file to respective multipliers on the second operand bus and to multiply the first operands by the respective second operands in the respective multipliers, wherein one or more of the first operands in the local operand register are reused by the multipliers in two or more multiplication operations.

DETAILED DESCRIPTION

A block diagram of an example of a digital signal processor (DSP)10suitable for incorporation of the present invention is shown inFIG. 1. The digital signal processor may be the TigerSharc digital signal processor manufactured and sold by Analog Devices, Inc., Norwood, Mass., for example. The digital signal processor10may include a compute X block12, a compute Y block14, an instruction sequencer16, memory blocks20,22,24, an integer ALU30and an I/O processor or DMA controller32. The elements of DSP10are interconnected by data and address buses40a,40b,40cand40d.

An example of compute blocks12and14is shown inFIG. 2. The compute block includes a compute register file50and several computation units. The computation units include an ALU52, a multiplier54, a shifter56and an accelerator58. Compute register file50receives data on buses40aand40band supplies operands to the computation units on operand buses64and66. The results of the computations are supplied on result buses70,72,74,76and78to compute register file50. The results may be written to memory from compute register file50or supplied to the computation units for subsequent computations.

A multiplication engine100in accordance with an embodiment of the invention is shown inFIGS. 3-5. Multiplication engine100may correspond to multiplier54shown inFIG. 2, may be used in accelerator58, or both. The multiplication engine100includes multiplier units110,112, . . .118. In the embodiment ofFIGS. 3-5, multiplication engine100includes 16 multiplier units. Multiplication engine100further includes a local operand register130coupled to each of multiplier units110,112, . . .118. The outputs of multiplier units110,112, . . .118are supplied to accumulators150,152, . . .158, respectively. Each accumulator may include a summing unit and an accumulation register. In some embodiments, each of accumulators150,152, . . .158includes two accumulation registers for enhanced performance. Thus, accumulator150includes a summing unit160and an accumulation register170, and may include a second accumulation register171(FIG. 4). Multiplication engine100further includes a control unit180that controls the components of multiplication engine100in response to instructions being executed.

Multiplication engine100receives operands from compute register file50(FIG. 2) on a first operand bus190and a second operand bus192. Results are returned to compute register file50on a result bus196. First operand bus190is coupled to local operand register130and to each of multiplier units110,112, . . .118. Second operand bus192is coupled to each of multiplier units110,112, . . .118.

Each of the multiplier units110,112, . . .118can be configured in response to an instruction being executed. In one configuration, each of the multiplier units is configured as eight multipliers of 16 bits by 2 bits. In another configuration, each of the multiplier units is configured as a single multiplier of 16 bits by 16 bits.

Local operand register130provides local storage of operands used by multiplier units110,112, . . .118. Local operand register130is useful where operands are reused by the multiplier units for two or more calculations. In some configurations, the same operands are used for two or more consecutive computations by the same multiplier units. In other configurations, operands are reused by different multiplier units for consecutive computations and the operands in local operand register130are shifted after completion of a computation. By holding operands that are reused in local operand register130, transfer of data on operand buses190and192is reduced and operating efficiency is increased.

As shown inFIG. 5, the multiplier units of multiplication engine100may be configured as complex multipliers510, each of which receives a first operand from local operand register130(THR register) and real and imaginary parts of a second operand from an Rms register512in compute register file50. For example, the second operand may be an input data value and the first operand may be a coefficient. The multiplication engine100further includes complex summing units520, each of which performs complex addition of a value output by complex multiplier510and a previous value. In particular, the output of each multiplier510is summed with a previous value in an accumulation register522to provide a current value that is placed in the accumulation register. In the embodiment ofFIG. 5, multiplication engine100includes eight complex multipliers510and eight complex summing units520. The complex multipliers correspond to the multiplier units110,112, . . .118shown inFIG. 3, the complex summing units correspond to summing units160,162, . . .168shown inFIG. 3, and the accumulation registers522correspond to accumulation registers170,172, . . .178shown inFIG. 3.

In the embodiment ofFIG. 5, Rms registers512may be located in compute register file50(FIG. 2). Local operand register130and accumulation registers522may be located in close proximity to complex multipliers510. Local operand register130is configured to perform shift operations as described below.

In the embodiment ofFIG. 5, local operand register130includes eight operands, each having 16 bits, including 8 bits real and 8 bits imaginary. Control circuit180(FIG. 3) causes operands to be loaded into local operand register130from compute register file50when operands are needed for multiply instructions. The operands in local operand register130are used to execute a multiply instruction as shown inFIG. 5. After the multiply instruction has been executed, control circuit180causes the operands in local operand register130to be shifted to the right. In the case of 16-bit operands, the operands are shifted 16 bits to the right by control circuit180. In addition, a new operand value is loaded from compute register file50to local operand register130. Then, a second multiply instruction is executed with the shifted operands in local operand register130. This process can be repeated until all computations have been completed. In each calculation, the operands contained in local operand register130are multiplied by operands supplied from the Rms registers512in compute register file50. If necessary, a new set of operands can be loaded into local operand register130by control circuit180. Thus, two or more multiply instructions can be executed without reloading local operand register130with a complete set of new operands after each multiply instruction.

The multiplication engine can be used to execute an FIR filter instruction as follows.

Rms—is an input single short coefficient.THRo—is an octal register data—inhabits 16 data numbers.THR7h—is the msb short in the THR7:0 registers.Rss—is a short operand which is loaded into the msb THR.j—for conjugate multiplication option.clr—clears the TR accumulators.sho—for real 8 bit multiplications.mhl—high/low Rmsshl—high/low Rss

The instruction makes 16 complex multiplications and afterwards shifts the contents of local operand register130(THR 7:0) by 16 bits to the right and updates the THR7h location by the new short word data from the compute register file.

The data d15:d0 is stored in the THR7:0 (each data number is 16b only). The coefficient c0 is being loaded by Rms and multiplied by all the data numbers. Then the data in the THR is shifted to the right and d16 is loaded to the THR7h. Thus, the data in the THR7:0 inhabits data numbers d16:d1 and is ready for step 2.

FromFIG. 7one may observe that in order to calculate the 4×4 matrix multiplication we need to make a 4 matrix accumulations. While each one of those matrix is the dot products of:

That means that in order to calculate matrixAwe don't need to load 16 data numbers and 16 coefficients and then to multiply them, but we can bring only 4 data numbers and 4 coefficients and multiply each of the data numbers by each of the coefficients to accept the dot product. That method utilizes all the 16 multipliers and saves bus bandwidth.