MRAM over sloped pillar

An apparatus including a pillar located over a substrate and having at least one sloped surface oriented at an acute angle relative to the substrate. The apparatus also includes an MRAM stack substantially conforming to the sloped surface, the MRAM stack thereby also oriented at the acute angle relative to the substrate. The MRAM stack may comprise a plurality of substantially planar, parallel layers each oriented at an acute angle relative to the substrate.

RELATED APPLICATION

The present application is related to U.S. Provisional Patent Application No. 60/601,281, filed Aug. 13, 2004, entitled “MRAM CELL HAVING SHARED CONFIGURATION,” and U.S. patent application Ser. No. 11/053,379, filed Feb. 8, 2005, now U.S. Pat. No. 7,221,584, issued May 22, 2007, entitled “MRAM CELL HAVING SHARED CONFIGURATION,” having common inventorship and ownership and filed concurrently herewith.

BACKGROUND

A magnetic random access memory (MRAM) device may include an MRAM stack having a dielectric layer interposing a fixed or pinned magnetic layer and a free magnetic layer. Each of the MRAM stack layers is substantially planar and oriented parallel to a surface over which the MRAM device is formed. However, cell density of integrated circuits and other devices incorporating one or more such MRAM devices is limited by the parallel orientation of the MRAM stack layers and the predetermined amount of surface area required at the interfaces between the MRAM stack layers (i.e., the lateral dimensions of each MRAM stack).

It follows that cell density may be increased by orienting each of the MRAM stack layers perpendicular to the underlying substrate. However, such embodiments introduce substantial complexity into existing manufacturing processes. Turning the MRAM stacks on-end also increases the overall height of the integrated circuit or other device incorporating such vertical MRAM stacks.

DETAILED DESCRIPTION

Referring toFIG. 1, illustrated is a block diagram of one embodiment of an integrated circuit50that is one example of a circuit that can benefit from aspects of the present disclosure. The integrated circuit50includes a memory cell array52that can be controlled by an array logic54through an interface55. It is well known in the art that various logic circuitry, such as row and column decoders and sense amplifiers, can be included in the array logic54, and that the interface55may include one or more bit lines, gate lines, digit lines, control lines, word lines, and other communication paths to interconnect the memory cell array52with the array logic54. The integrated circuit can further include other logic56, such as counters, clock circuits, and processing circuits, and input/output circuitry58, such as buffers and drivers.

Referring toFIG. 2, the memory cell array52ofFIG. 1may include one or more magnetic random access memory (MRAM) cells60. Each MRAM cell60does not need to be commonly configured, but for the sake of example, can be generically described as including a configuration of MRAM stacks in MTJ devices62and a switching device64. Examples of various embodiments of the MTJ devices62are discussed in further detail below, and examples of the switching device64include a metal oxide semiconductor (MOS) transistor, an MOS diode, and/or a bipolar transistor. The memory cell60can store 1, 2, 3, 4 or more bits.

The MRAM cell60may include three terminals, a first terminal66, a second terminal68, and a third terminal70. For the sake of example, the first terminal66is connected to one or more bit lines and produces an output voltage in a read operation, which is provided to the bit line(s). The second terminal68is connected to one or more word lines, which can activate the cell60for a read or write operation. The third terminal70may be proximate a control line, such as a gate or digit line, and can provide a current for producing a magnetic field to effect the MTJ configuration62. It is understood that the arrangement of bit lines, word lines, control lines, and other communication signals can vary for different circuit designs, and the present discussion is only providing one example of such an arrangement.

Referring toFIG. 3a, illustrated is a sectional view of at least a portion of one embodiment of an apparatus300in an intermediate stage of manufacture according to aspects of the present disclosure. The apparatus300may include one or more pillars310,315formed over a substrate305. The apparatus300may also include more than the two pillars310,315shown inFIG. 3. The pillars310,315may be formed directly on the substrate305, although one or more other layers, features, or components may also interpose the substrate305and one or both of the pillars310,315.

The substrate may comprise silicon, gallium arsenide, and/or other materials. In one embodiment, the substrate305is or comprises a silicon-on-insulator (SOI) substrate, such as a substrate comprising an epitaxially grown or otherwise formed semiconductor layer on an insulator layer. The substrate305may also comprise one or more conductive and/or insulating layers located thereon, such as those that may be employed to form active and/or passive devices and/or a device interconnect structure. Thus, reference herein to the substrate305may refer to a wafer on which a plurality of layers are formed, such as a silicon ingot, but may also refer to one or more such layers which may be formed on or over such a wafer.

The pillars310,315may comprise one or more electrically conductive materials such as aluminum, gold, tungsten, alloys thereof, and/or other electrically conductive materials. The pillars310,315may also or alternatively comprise one or more dielectric materials such as silicon dioxide, tetraethylorthosilicate (TEOS), glass, SILK (a product of Dow Chemical), BLACK DIAMOND (a product of Applied Materials), and/or other electrically insulating materials. The pillars310,315may also or alternatively comprise one or more magnetic materials, including ferromagnetic, anti-ferromagnetic, and/or hard-magnetic materials. For example, the pillars310,315may comprise NiFe, NiFeCo, CoFe, Fe, Co, Ni, alloys or compounds thereof, and/or other magnetic materials.

The pillars310,315may be formed by chemical-vapor deposition (CVD), rapid thermal CVD (RTCVD), plasma enhanced CVD (PECVD), sputtering, and/or other processes, including processes other than CVD-type processes. The pillars310,315may be selectively deposited or blanket deposited accompanied by subsequent patterning, such as by wet or dry etching. The thickness of the pillars310,315may range between about 50 nm and about 1000 nm, although other thicknesses are also within the scope of the present disclosure.

The pillars310,315have surfaces312,317that are sloped relative to the substrate. The sloped surfaces312,317of the pillars310,315may be oriented at an acute angle relative to the substrate305. For example, the surfaces312,317may be angularly offset from the substrate305by an angle ranging between about 60 degrees and about 88 degrees. In one embodiment, the angular offset of the surfaces312,317relative to the substrate305may range between about 70 and 80 degrees. For example, in the embodiment shown inFIG. 3a, the angular offset of the surfaces312,317relative to the substrate305is about 70 degrees. However, each of the surfaces312,317of the pillars310,315may not be angularly offset from the substrate305by the same angle. That is, while each surface312,317may be angularly offset from the substrate305by an acute angle, the surface312may be angularly offset from the substrate305by an acute angle different than the angular offset of the surface317. In one embodiment, only one of the surfaces312,317may be angularly offset from the substrate305, wherein the other of the surface312,317may be substantially perpendicular to the substrate305.

Referring toFIG. 3b, illustrated is a sectional view of the apparatus300shown inFIG. 3ain a subsequent stage of manufacture in which a magnetic layer320has been formed over the pillars310,315, the sloped surface312,317of the pillars310,315, and a portion of the substrate305exposed between the pillars310,315. The magnetic layer320may have a thickness ranging between about 1 nm and about 20 nm, although other thickness are within the scope of the present disclosure. Also, while the magnetic layer320is illustrated as being formed directly on the sloped pillar surfaces312,317, other layers, features, or components may interpose the pillars310,315and the magnetic layer320.

The magnetic layer320may comprise NiFe, NiFeCo, CoFe, Fe, Co, Ni, alloys or compounds thereof, and/or other magnetic materials and, as such, may be employed to subsequently form a free or pinned magnetic layer. The magnetic layer320may also comprise a plurality of layers, such as a Ru spacer interposing two or more magnetic layers or other combinations forming a synthetic anti-ferromagnetic (SAF) layer. Although not limited within the scope of the present disclosure, the magnetic layer320may be formed by blanket deposition employing such processes as CVD, RTCVD, PECVD, sputtering, and/or other processes, including processes other than CVD-type processes.

Referring toFIG. 3c, illustrated is a sectional view of the apparatus300shown inFIG. 3bin a subsequent stage of manufacture in which at least a portion of the magnetic layer320has been removed to form magnetic MRAM stack layers330,335. For example, one or more isotropic and/or anisotropic etching processes may be performed to define the magnetic MRAM stack layers330,335, possibly employing a patterned photoresist or other mask. Such material removal may employ the pillars310,315and/or the substrate305for end-point detection. Moreover, although not shown in the illustrated embodiment, the material removal process(es) employed to define the magnetic MRAM stack layers330,335from the magnetic layer320may leave one or more of the distal edges of the magnetic MRAM stack layers330,335relative to the substrate305(e.g., upper edges inFIG. 3c) with a rounded profile.

By forming the magnetic MRAM stack layers330,335in the above-described manner, the magnetic MRAM stack layers330,335may substantially conform to the sloped surfaces312,317of the pillars310,315. However, processes other than those described above may also or alternatively be employed to form the magnetic MRAM stack layers330,335. For example, chemical-mechanical planarizing and/or polishing (hereafter collectively referred to as CMP) may be employed to removed portions of the magnetic layer320from over the pillars310,315, possibly employing the pillars310,315for end-point detection. The magnetic MRAM stack layers330,335may also or alternatively be formed by selective deposition on or over the sloped pillar surfaces312,317. Nonetheless, in some embodiments, one or both of the distal ends of each of the magnetic MRAM stack layers330,335may be substantially coplanar with or otherwise aligned with the upper and lower surfaces of the pillars310,315, relative to the illustration inFIG. 3c.

Because the magnetic MRAM stack layers330,335may substantially conform to the sloped pillar surfaces312,317, the magnetic MRAM stack layers330,335may also be oriented at an acute angle relative to the substrate305, such as at an angle ranging between about 60 degrees and about 88 degrees. In one embodiment, the magnetic MRAM stack layers330,335are oriented at an angle ranging between about 70 degrees and about 80 degrees.

In some embodiments, the lateral surfaces of one or both of the magnetic MRAM stack layers330,335may not be mutually substantially parallel or individually planar. In such embodiments, the orientation of the magnetic MRAM stack layers330,335at an acute angle relative to the substrate305may be measured from one of the sidewall surfaces of the corresponding one of the magnetic MRAM stack layers330,335that is substantially planar. Such orientation may also be measured from a best-fit plane of one of the sidewall surfaces of the corresponding one of the magnetic MRAM stack layers330,335that may not be substantially planar. The angular offset may also be measured from a hypothetical center plane of the corresponding one of the magnetic MRAM stack layers330,335, wherein the center plane may represent a weighted or other average of the sidewall surfaces of the corresponding one of the magnetic MRAM stack layers330,335. In one embodiment, at least one of the sloped surfaces312,317may be substantially cylindrical, wherein the angular offset thereof may be measured from the center-line axis of the cylindrical surface.

Referring toFIG. 3d, illustrated is a sectional view of the apparatus300shown inFIG. 3cin a subsequent stage of manufacture in which dielectric MRAM stack layers340,345have been formed adjacent the magnetic MRAM stack layers330,335. The dielectric MRAM stack layers340,345may be formed by one or more of the processes described above that may be employed to form the magnetic layer320. For example, the dielectric MRAM stack layers340,345may be formed by CVD followed by an etch or other material removal process. The dielectric MRAM stack layers340,345may also each comprise more than one layer. Also, while the dielectric MRAM stack layers340,345are illustrated as being formed directly on the magnetic MRAM stack layers330,335, other layers, features, or components may interpose the dielectric MRAM stack layers340,345and the magnetic MRAM stack layers330,335.

One or both of the dielectric MRAM stack layers340,345may be a tunneling layer or other dielectric layer. For example, the dielectric MRAM stack layers340,345may comprise SiOx, SiNx, SiOxNy, AlOx, TOx, TiOx, AlNx, alloys or compounds thereof, and/or other electrically insulating materials. The dielectric MRAM stack layers340,345may have a thickness ranging between about 0.5 nm and about 2 nm, possibly measured in a direction substantially perpendicular to one of the sloped pillar surfaces312,317. Moreover, the dielectric MRAM stack layers340,345may substantially conform to a corresponding one of the magnetic MRAM stack layers330,335, such that the dielectric MRAM stack layers340,345may be similarly oriented at an acute angle relative to the substrate305.

Referring toFIG. 3e, illustrated is a sectional view of the apparatus300shown inFIG. 3din a subsequent stage of manufacture in which magnetic MRAM stack layers350,355have been formed adjacent the dielectric MRAM stack layers340,345. While the magnetic MRAM stack layers350,355are illustrated as being formed directly on the dielectric MRAM stack layers340,345, other layers, features, or components may interpose the magnetic MRAM stack layer350,355and the dielectric MRAM stack layers340,345.

The completion of the magnetic MRAM stack layers350,355may complete MRAM stacks360,365. That is, the MRAM stack360may comprise the magnetic MRAM stack layer330, the dielectric MRAM stack layer340, and the magnetic MRAM stack layer350, wherein one of the magnetic MRAM stack layers330,350may be a free magnetic layer and the other of the magnetic MRAM stack layers330,350may be a fixed or pinned magnetic layer. Similarly, the MRAM stack365may comprise the magnetic MRAM stack layer335, the dielectric MRAM stack layer345, and the magnetic MRAM stack layer355, wherein one of the magnetic MRAM stack layers335,355may be a free magnetic layer and the other of the magnetic MRAM stack layers335,355may be a fixed or pinned magnetic layer. However, in some embodiments, the MRAM stacks360,365may comprise alternative or additional layers.

The magnetic MRAM stack layers350,355may comprise NiFe, NiFeCo, CoFe, Fe, Co, Ni, alloys or compounds thereof, and/or other magnetic materials, including ferromagnetic or anti-ferromagnetic materials. Also, as described above, the magnetic MRAM stack layers350,355may also each be or comprise a free or pinned magnetic layer.

One or both of the magnetic MRAM stack layers350,355may also comprise a plurality of layers, such as a Ru spacer interposing two or more magnetic layers or other combinations forming a synthetic anti-ferromagnetic (SAF) layer. The thickness of the magnetic MRAM stack layers350,355may also be substantially similar to the thickness of the magnetic MRAM stack layers330,335. Although not limited within the scope of the present disclosure, the magnetic MRAM stack layers350,355may be substantially similar in manufacture to the magnetic MRAM stack layers330,335, with the exception that the magnetic MRAM stack layers330,335,350,355collectively form corresponding pairs of free and pinned magnetic MRAM stack layers as necessary to form MTJ MRAM stacks.

The magnetic MRAM stack layers350,355may substantially conform to a corresponding one of the magnetic MRAM stack layers330,335, such that the dielectric MRAM stack layers350,355may be similarly oriented at an acute angle relative to the substrate305. Consequently, the MRAM stacks360,365may also be oriented an acute angle relative to the substrate305. For example, the MRAM stacks360,365may each be angularly offset from the substrate305by an angle ranging between about 60 degrees and about 88 degrees. In one embodiment, one or both of the MRAM stacks360,365may be angularly offset from the substrate305by an angle ranging between about 70 degrees and about 80 degrees.

Referring toFIG. 3f, illustrated is a sectional view of the apparatus300shown inFIG. 3ein a subsequent stage of manufacture in which a central member370has been formed interposing and contacting the MRAM stacks360,365. The central member370may comprise one or more electrically conductive materials such as aluminum, gold, tungsten, alloys thereof, and/or other electrically conductive materials. The central member370may also or alternatively comprise one or more dielectric materials such as silicon dioxide, tetraethylorthosilicate (TEOS), glass, BLACK DIAMOND, and/or other electrically insulating materials. The central member370may also or alternatively comprise one or more magnetic materials, including ferromagnetic, anti-ferromagnetic, and/or hard-magnetic materials. For example, the central member370may comprise NiFe, NiFeCo, CoFe, Fe, Co, Ni, alloys or compounds thereof, and/or other magnetic materials.

The central member370may be formed by CVD, RTCVD, PECVD, sputtering, and/or other processes, including processes other than CVD-type processes. The central member370may be selectively deposited or blanket deposited accompanied by CMP. The thickness of the central member370may range between about 10 nm and about 1000 nm, or otherwise substantially similar to the thickness of one or both of the pillars310,315, although other thicknesses are also within the scope of the present disclosure. The central member370and/or the pillars310,315may be employed in the interconnection of the MRAM stacks360,365, possibly in conjunction an interconnect structure contacting the central member370and/or the pillars310,315.

Referring toFIG. 4, illustrated is a sectional view of at least a portion of another embodiment of the apparatus300shown inFIG. 3f, herein designated by the reference number400. The apparatus400is substantially similar to the apparatus300shown inFIG. 3f. However, the apparatus400may be employed as a one-bit memory cell, whereas the apparatus300shown inFIG. 3fmay be employed as a memory cell comprising two bits. That is, the recess between proximate pillars310,315in the apparatus400may contain only one MRAM stack360, whereas the recess between proximate pillars310,315in the apparatus300may contain two or more MRAM stacks360,365. Moreover, although the pillars310,315in the apparatus400are illustrated as each having a sloped surface, the pillar315to which the MRAM stack360does not substantially conform may not have a sloped surface.

Referring toFIG. 5, illustrated is a sectional view of at least a portion of another embodiment of the apparatus300shown inFIG. 3f, herein designated by the reference number500. The apparatus500is substantially similar to the apparatus300shown inFIG. 3f. However, the apparatus500may be employed as a multi-bit memory cell, or as more than one memory cell. That is, the recess between proximate pillars310,315in the apparatus500may contain a plurality of MRAM stacks360,365. For example, the illustrated portion of the apparatus500includes four MRAM stacks360,365, as well as portions of additional, neighboring MRAM stacks. The apparatus500may also include additional dielectric layers510interposing proximate ones of the MRAM stacks360,365. The dielectric layers510may each be substantially similar in composition and manufacture to the dielectric MRAM stack layers340,345described above, although other types of materials and processes may also be employed to form the dielectric layers510.

Referring toFIG. 6, illustrated is a top view of at least a portion of one embodiment of the apparatus300shown inFIG. 3f, herein designated by the reference numeral600. The apparatus600includes one or more MRAM stacks660,665, each of which may be substantially similar in composition and manufacture to one of the MRAM stacks360,365shown inFIG. 3f. In the embodiment shown inFIG. 6, the apparatus600includes two MRAM stacks660,665. However, in other embodiments, the apparatus600may include only one of the MRAM stacks660,665, or may include more than the two MRAM stacks660,665shown inFIG. 6.

The apparatus600also includes one or more pillars610formed over a substrate, and which may be substantially similar in composition and manufacture to the pillars310,315described above. The pillars610may have a substantially cylindrical surface having a center axis oriented at an acute angle relative to the underlying substrate. In the illustrated embodiment, the pillar610includes an elongated, oval-shaped recess, wherein the ends of the recess are sloped relative to the underlying substrate, thereby forming substantially cylindrical surfaces angularly offset from the underlying substrate. The MRAM stacks660,665are formed over the sloped, cylindrical surfaces of the pillar610. In another embodiment, individual pillars may be employed to provide each substantially cylindrical, angularly offset surface on or over which an MRAM stack is formed.

Moreover, although not visible inFIG. 6, each of the MRAM stacks660,665may substantially conform to the angularly offset, substantially cylindrical surfaces of the pillars610, such that each of the MRAM stacks660,665are also oriented at an acute angle relative to the substrate and may have a semi-circular or otherwise arcuate footprint. For example, in the illustrated embodiment, each of the MRAM stacks660,665comprise a plurality of substantially concentric MRAM stack layers630each having a semi-circular footprint.

The apparatus600may also include a central member670interposing and contacting the MRAM stacks660,665. The central member670may be substantially similar in composition and manufacture to the central member370described above. For example, the central member670may comprise magnetic, electrically conductive, and/or dielectric material, as may be needed to interconnect the MRAM stacks660,665.

Referring toFIG. 7, illustrated is a perspective view of at least a portion of one embodiment of the apparatus300shown inFIG. 3f, herein designated by the reference numeral700. The apparatus700includes one or more MRAM stacks760,765, each of which may be substantially similar in composition and manufacture to one of the MRAM stacks360,365shown inFIG. 3f. In the embodiment shown inFIG. 7, the apparatus700includes two MRAM stacks760,765. However, in other embodiments, the apparatus700may include only one of the MRAM stacks760,765, or may include more than the two MRAM stacks760,765shown inFIG. 7.

The apparatus700also includes one or more pillars710,715formed over a substrate705, and which may be substantially similar in composition and manufacture to the pillars310,315described above. The pillars710,715may each have a substantially planar surface oriented at an acute angle relative to the substrate705. In the illustrated embodiment, the pillars710,715defined an elongated, rectilinear recess having a substantially trapezoidal cross-sectional shape, wherein the sides of the recess are sloped relative to the substrate705, thereby forming substantially planar surfaces angularly offset from the substrate705.

The MRAM stacks760,765are formed over the sloped, substantially planar surfaces of the pillars710,715. Thus, each of the MRAM stacks760,765may substantially conform to the angularly offset, substantially planar surfaces of the pillars710,715, such that each of the MRAM stacks760,765are also oriented at an acute angle relative to the substrate, and may have a substantially linear or rectilinear footprint. For example, in the illustrated embodiment, each of the MRAM stacks760,765comprise a plurality of substantially parallel MRAM stack layers730each having a rectilinear footprint.

The apparatus700may also include a central member770interposing and contacting the MRAM stacks760,765. The central member770may be substantially similar in composition and manufacture to the central member370described above. For example, the central member770may comprise magnetic, electrically conductive, and/or dielectric material, as may be needed to interconnect the MRAM stacks760,765.

The apparatus700may also include one or more microelectronic devices790, possibly interconnected with one or more of the MRAM stacks760,765. For example, in the illustrated embodiment, the microelectronic devices790are field effect transistors each having source/drain regions792formed in the substrate705and gate electrodes794formed in a dielectric layer796formed over the substrate705. However, other types of microelectronic devices790may also be employed within the scope of the present disclosure. For example, the microelectronic devices790may be or comprise transistors other than field effect transistors, or other active or passive microelectronic devices. The apparatus700may also include conventional or future-developed interconnects798interconnecting the MRAM stacks760,765and/or the microelectronic devices790. As such, the apparatus700may be or comprise a memory cell array and/or other type of integrated circuit device.

Referring toFIG. 8, illustrated is a perspective view of at least a portion of one embodiment of an apparatus800according to aspects of the present disclosure. The apparatus800is one environment in which any of the above-described apparatus300,400,500,600,700may be implemented. The apparatus800includes one or more memory cells each including one or more MRAM stacks860,865, each of which may be substantially similar in composition and manufacture to one of the MRAM stacks360,365shown inFIG. 3f.

The apparatus800also includes one or more pillars810,815formed over a substrate805, each of which may be substantially similar in composition and manufacture to the pillars310,315described above. The pillars810,815may each have one or more surfaces oriented at an acute angle relative to the substrate805. Such angularly offset surfaces may be substantially planar, as illustrated inFIG. 7, or substantially cylindrical, as described with regard toFIG. 6. However, the sloped surfaces of the pillars810,815may also have configurations other than the substantially planar and substantially cylindrical configurations described above. Ones of the pillars810,815may also have more than one sloped surface, such as the pillar810/815indicated inFIG. 8.

The MRAM stacks860,865are formed over the sloped surfaces of the pillars810,815. That is, the MRAM stacks860,865may be formed on the sloped surfaces of the pillars810,815or, in some embodiments, one or more additional layers, features, or components may interpose the MRAM stacks860,865and their corresponding pillars810,815. Each of the MRAM stacks860,865may substantially conform to the angularly offset surfaces of the pillars810,815, such that each of the MRAM stacks860,865are also oriented at an acute angle relative to the substrate

The apparatus800may also include one or more central members870each interposing and possibly contacting proximate ones of the MRAM stacks860,865. The central members870may each be substantially similar in composition and manufacture to the central member370described above. For example, the central members870may each comprise magnetic, electrically conductive, and/or dielectric material, as may be needed to interconnect the MRAM stacks860,865. Moreover, each of the central members870need not have identical compositions, such that one or more of the central members870may be electrically conductive whereas one of more other central members870may substantially comprise dielectric material.

The apparatus800may also include one or more microelectronic devices890, possibly interconnected with one or more of the MRAM stacks860,865. For example, in the illustrated embodiment, the microelectronic devices890are field effect transistors each having source/drain regions892formed in the substrate805and gate electrodes894formed in a dielectric layer896formed over the substrate805. However, other types of microelectronic devices890may also be employed within the scope of the present disclosure. For example, the microelectronic devices890may be or comprise transistors other than field effect transistors, or other active or passive microelectronic devices.

The apparatus800may also include isolation structures898interposing ones of the source/drain regions892and/or other components of the microelectronic devices890. The isolation structures898may be or comprise field oxide regions, shallow trench isolation, local oxidation of silicon (LOCOS), and/or other conventional or future-developed isolation structures. As such, the isolation structures898may comprise silicon dioxide and/or other dielectric materials.

The apparatus800may also include conventional or future-developed interconnects898interconnecting the MRAM stacks860,865and/or the microelectronic devices890. As such, the apparatus800may be or comprise an integrated circuit device. The apparatus800may also include interconnects899which may be formed in the pillars810,815prior to forming the sloped surfaces of the pillars810,815or the MRAM stacks860,865.

Thus, the present disclosure provides an apparatus comprising, in at least one embodiment, a pillar located over a substrate and having at least one sloped surface oriented at an acute angle relative to the substrate. The apparatus may also comprise an MRAM stack substantially conforming to the sloped surface, the MRAM stack thereby also oriented at the acute angle relative to the substrate. In one embodiment, the sloped surface may be a sloped sidewall of the pillar. The MRAM stack may comprise a plurality of substantially planar, parallel layers each oriented at an acute angle relative to the substrate.

The present disclosure also introduces an apparatus comprising, in at least one embodiment, first and second substantially coplanar pillars located over a substrate and laterally opposing an MRAM stack having a plurality of layers. At least one of the plurality of MRAM stack layers substantially conforms to a surface of one of the first and second pillars that is oriented at an acute angle relative to the substrate.

Another embodiment of an apparatus according to aspects of the present disclosure comprises a first pillar located over a substrate and having a first surface oriented at a first acute angle relative to the substrate, and a second pillar located over the substrate and having a second surface oriented at a second acute angle relative to the substrate. Such an embodiment also includes a first MRAM stack interposing the first and second pillars and including a first plurality of layers, wherein at least one of the first plurality of layers substantially conforms to the first surface of the first pillar, and a second MRAM stack interposing the first MRAM stack and the second pillar and including a second plurality of layers, wherein at least one of the second plurality of layers substantially conforms to the second surface of the second pillar.

A method which may be employed, for example, in the formation of an apparatus comprising an angularly oriented MRAM stack is also provided in the present disclosure. In at least one embodiment, the method includes forming a pillar over a substrate, the pillar having a sloped surface oriented at an acute angle relative to the substrate. The method also includes forming an MRAM stack having a plurality of layers, wherein at least one of the plurality of layers substantially conforms to the pillar surface oriented at an acute angle relative to the substrate.

The foregoing has outlined features of several embodiments according to aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that these and other such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.