High thermal release interposer

An integrated circuit package having an interposer with increased thermal conductivity and techniques for fabricating such an integrated circuit package are provided. One example integrated circuit package generally includes a package substrate, at least one semiconductor die disposed above the package substrate, and an interposer disposed above the at least one semiconductor die. The interposer includes a dielectric layer, and a metallic plate disposed adjacent to a first portion of the dielectric layer. The height of the metallic plate is greater than a height of the dielectric layer.

TECHNICAL FIELD

Certain aspects of the present disclosure generally relate to integrated circuits (ICs) and, more particularly, to integrated circuit packaging with one or more high thermal release interposers, e.g., for improved heat dissipation away from integrated circuits within the integrated circuit packaging.

BACKGROUND

Electronic devices (e.g., computers, laptops, tablets, copiers, digital cameras, smart phones, and the like) often employ integrated circuits (ICs, also known as “chips”). These integrated circuits are typically implemented as semiconductor dies packaged in integrated circuit packages. The semiconductor dies may include memory, logic, and/or any of various other suitable circuit types.

Many integrated circuits and other semiconductor devices utilize an arrangement of bumps, such as a ball grid array (BGA), for surface mounting packages to a circuit board (e.g., printed circuit board (PCB)). Any of various suitable package pin structures, such as controlled collapse chip connection (C4) bumps or microbumps (as used in stacked silicon interconnect (SSI) applications), may be used to conduct electrical signals between a channel on an integrated circuit (IC) die (or other package device) and the circuit board on which the package is mounted.

As the density of active components in integrated circuit dies continues to rise, the integrated circuit dies produce an ever-increasing amount of heat during operation. This heat is typically thermally conducted from the integrated circuit dies through multiple thermal bar vias to a heat sink to facilitate heat dissipation away from the integrated circuit dies. In some cases, heat spreaders (e.g., vapor chambers) may be used to spread heat from a concentrated heat source, such as an integrated circuit die, to a larger heat sink.

SUMMARY

Certain aspects of the present disclosure generally relate to integrated circuit packaging that includes an interposer structure that allows for improved heat management (e.g., greater heat dissipation away from integrated circuit dies) within the integrated circuit packaging.

Certain aspects of the present disclosure are directed to an integrated circuit package. The integrated circuit package includes a package substrate, at least one semiconductor die disposed above the package substrate, and an interposer disposed above the at least one semiconductor die. The interposer includes a dielectric layer and a metallic plate disposed adjacent to a first portion of the dielectric layer. A height of the metallic plate is greater than a height of the dielectric layer.

Certain aspects of the present disclosure are directed to a method for fabricating an integrated circuit package. The method includes forming a package substrate, forming at least one semiconductor die above the package substrate, and forming an interposer above the at least one semiconductor die. Forming the interposer includes forming a dielectric layer and forming a metallic plate adjacent to a first portion of the dielectric layer, wherein a height of the metallic plate is greater than a height of the dielectric layer.

DETAILED DESCRIPTION

Aspects of the present disclosure provide structures for high thermal release interposers suitable for integrated circuit (IC) packaging. More specifically, aspects presented herein provide various IC packages that include one or more semiconductor dies and an interposer disposed above the semiconductor die(s). The interposer may include a dielectric (or insulation) layer and a metallic plate disposed adjacent to the dielectric layer, where the height of the metallic plate is greater than the height of the dielectric layer. By placing such an interposer structure within IC packaging, aspects can substantially improve the thermal efficiency (e.g., provide greater heat dissipation) within the IC packaging, as compared to IC packaging having interposers without the metallic plate.

As used herein, the term “connected with” in the various tenses of the verb “connect” may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element B). In the case of electrical components, the term “connected with” may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween).

FIG. 1illustrates a cross-sectional view of an example IC package100. The IC package100includes a package substrate102, an IC die110(also referred to as a “chip” or semiconductor die) connected to the package substrate102, and an interposer104(also referred to as an interposer substrate). In some cases, the package substrate102may be a multi-layered substrate. Although a single IC die110is shown inFIG. 1, the IC package100may include multiple IC dies connected to the package substrate102. The package substrate102may be mounted and connected to a printed circuit board (PCB) (not shown), utilizing metallic (e.g., copper (Cu)) core balls140, a set of solder balls (e.g., in a ball grid array (BGA)), wire bonding, or any other suitable technique. The package substrate102may include silicon (Si), for example.

The IC die110may be a programmable logic device (e.g., field programmable gate array (FPGA)), memory device, optical device, processor, or other IC structure. Optical devices include photodetectors, lasers, optical sources, and the like. In this example, the IC die110is mounted to the top surface of the package substrate102via multiple microbumps112. The microbumps112electrically connect the circuitry of the IC die110to the package substrate102, e.g., to enable communication of the IC die110with the PCB (not shown).

The interposer104may include circuitry for electrically connecting one or more additional IC dies (e.g., mounted above the interposer104via microbumps) (not shown) to the package substrate102. The additional IC die(s) may include one or more of programmable logic devices, memory devices, optical devices, etc. In some cases, the interposer104may also include circuitry for interconnecting IC die(s) so that the IC die(s) may communicate with each other (e.g., in a horizontal configuration rather than vertical). As shown, the interposer104includes a dielectric layer (or insulation layer)118, a metallic layer116disposed below the dielectric layer118, a metallic layer120disposed above the dielectric layer118, a photo solder resist layer114disposed below the metallic layer116, and a photo solder resist layer122disposed above the metallic layer120. The dielectric layer118may include any of various suitable dielectric materials, such as silicon dioxide (SiO2).

In some examples, the interposer104may be passive and include interconnects (not shown) and/or through-silicon vias (TSVs) (not shown) for connecting one of the IC die(s) to another and/or for connecting the additional IC die(s) above the interposer to the IC die(s) beneath. In some examples, the interposer104may be active and include transistors. Metallic (e.g., Cu) core balls108or a set of solder balls may be utilized to provide an electrical connection between the circuitry of the interposer104and the circuitry of the package substrate102. Each of the metallic core balls108may be enclosed within a thin other metallic (e.g., tin (Sn)) layer124. While two metallic core balls108are shown inFIG. 1, the IC package100may include any number (e.g., greater than two) of metallic core balls108disposed between the interposer104and the package substrate102.

As the density of active components in IC die(s) continues to rise, the IC dies may produce an ever-increasing amount of heat during operation. This increased heat can reduce the thermal efficiency, and in turn, the performance of the IC package. In some cases, the interposer of an IC package may facilitate heat dissipation within the IC package. However, conventional interposers, such as the interposer104within IC package100, generally do not have a structure that allows for efficient thermal heat spreading and low thermal resistance. For example, techniques that use TSV(s) within the interposer (e.g., interposer104) to release heat are typically inefficient and cost-intensive.

Certain aspects of the present disclosure provide various structures for interposers that allow for improved heat management within IC packages. For example, as described in more detail below, the IC package may include an interposer that is disposed above at least one IC die. The interposer may include a dielectric layer, and a metallic plate that is disposed adjacent to the dielectric layer. The height of the metallic plate may be greater than a height of the dielectric layer. By including such an interposer structure within an IC package, the interposer can substantially increase heat dissipation away from the at least one IC die of the IC package (e.g., relative to conventional interposers, such as interposer104).

FIG. 2illustrates a cross-sectional view of an example IC package200that includes a high thermal release interposer, in accordance with certain aspects of the present disclosure. The IC package200includes a package substrate102, an IC die110connected to the package substrate102, and an interposer204. Although a single IC die110is shown inFIG. 1, the IC package200may include multiple IC dies connected to the package substrate102.

The interposer204may include circuitry for electrically connecting one or more additional IC dies (e.g., mounted above or on the interposer204via microbumps) (not shown) to the package substrate102. As shown, the interposer204includes a dielectric layer218, a metallic layer220disposed above the dielectric layer218, a metallic layer216disposed below the dielectric layer218, a photo solder resist layer214disposed below the metallic layer216, and a photo solder resist layer222disposed above the metallic layer220. The dielectric layer218may include SiO2, for example. The metallic layers216and220may include Cu, for example.

The interposer204further includes a metallic (e.g., Cu) plate240disposed above the IC die110and on photo solder resist layer214. The metallic plate240is exposed at an upper surface of the interposer204. In some aspects, the metallic plate240may be further disposed adjacent to at least one portion of each of the dielectric layer218, metallic layer220, metallic layer216, and photo solder resist layer222. In this particular example, the metallic plate240is disposed between a portion246of the dielectric layer218and a portion234of the dielectric layer218, between a portion244of the metallic layer220and a portion232of the metallic layer220, between a portion248of the metallic layer216and a portion236of the metallic layer216, and between a portion242of the photo solder resist layer222and a portion230of the photo solder resist layer222. By placing the metallic plate240of the interposer204over at least a portion of the IC die110, the interposer204can increase the thermal dissipation away from the IC die110(e.g., as illustrated by arrows260). Although the metallic plate240is centered above the IC die110and covers a majority of the IC die inFIG. 2, the metallic plate may be skewed with respect to the center of the IC die, cover the entire IC die, extend beyond the IC die, and/or cover less than the majority of the IC die in other aspects.

As shown, a height (or thickness) of the metallic plate240is greater than a height (or thickness) of the dielectric layer218. In some aspects, as shown, the height of the metallic plate240may be approximately equal to a sum of the heights of the dielectric layer218, the metallic layer220, and the metallic layer216. The photo solder resist layer222may not cover the metallic plate240, as shown inFIG. 2, for increased heat conduction to the ambient environment. Note that whileFIG. 2depicts the metallic plate240being disposed between portions246and234of the dielectric layer218, between portions244and232of the metallic layer220, between portions248and236of the metallic layer216, and between portions242and230of the photo solder resist layer222, in some aspects, the metallic plate240may be disposed adjacent to a single portion of each of the dielectric layer218, metallic layer220, metallic layer216, and photo solder resist layer222. For example, the metallic plate240may be disposed on one side of the interposer204.

FIG. 3illustrates a top view310and a cross-sectional view320of the interposer204of the IC package200, in accordance with certain aspects of the present disclosure. As shown in the cross-sectional view320, the metallic plate240may be a full metallic plate (e.g., including metal, such as Cu, throughout an entire thickness of the metallic plate). Additionally, in some aspects, the photo solder resist layer222may be patterned to expose the top surface of the metallic plate240for thermal coupling with IC die(s) disposed above the top surface and/or the photo solder resist layer214may be patterned to expose the bottom surface of the metallic plate240for thermal coupling with IC die(s) disposed below the bottom surface. For example, as shown in cross-sectional view320ofFIG. 3, the top surface and bottom surface of the metallic plate240are exposed.

FIG. 4illustrates a cross-sectional view of an example IC package400that includes a high thermal release interposer, in accordance with certain aspects of the present disclosure. The IC package400is similar to the IC package200, but the IC package400includes an interposer404with a metallic (e.g., Cu) plate440that is disposed above the IC die110, between portions246and234of the dielectric layer218, between portions244and232of the metallic layer220, between portions248and236of the metallic layer216, between portions242and230of the photo solder resist layer222, and between portions406and402of the photo solder resist layer214. Additionally, the interposer404of the IC package400is exposed at both a top surface and a bottom surface of the interposer404(e.g., for thermal coupling with IC die(s)110and/or IC die(s) disposed above interposer404(not shown)). The height of the interposer404may be approximately equal to a sum of heights of the dielectric layer218, the metallic layer216, the metallic layer220, the photo solder resist layer214, and the photo solder resist layer222. By increasing the height of the interposer404(e.g., compared to the height of the interposer204) such that the bottom surface of the interposer404is exposed to the IC die(s)110, the interposer404may further increase the heat dissipation away from the IC die(s)110within the IC package400.

FIG. 5illustrates a cross-sectional view of an example IC package500that includes a high thermal release interposer, in accordance with certain aspects of the present disclosure. The IC package500is similar to the IC package200, but the IC package500further includes a thermal interface material (TIM) layer510disposed between the interposer204and the IC die110. As shown in this particular example, the TIM layer510is disposed between the metallic plate240of the interposer204and the IC die110.

The TIM layer510may be used to provide a thermally conductive path between the interposer204and the IC die110. Example of materials suitable for use as the TIM layer510include adhesives, thermal grease, thermally conductive epoxy, phase-change materials (PCMs), conductive tapes, and silicone-coated fabrics among other suitable materials. The TIM layer510may be a soft or compliant adhesive to allow compensation between mismatched heights of neighboring IC die(s)110within the IC package500. In one example, the TIM layer510may be a thermal gel or thermal epoxy. Utilizing a metallic plate240within the interposer204in addition to a TIM layer510disposed between the interposer204and IC die(s)110of the IC package500can further increase (e.g., relative to IC packages200and400) the amount of heat dissipation within the IC package500. The increased heat dissipation, in turn, can increase the thermal performance of the IC package500. Note, that whileFIG. 5depicts a TIM layer510disposed between the interposer204and the IC die(s)110, in some aspects, a TIM layer510may be disposed between the interposer404and the IC die(s)110ofFIG. 4.

FIGS. 6A-6Hillustrate example processes for fabricating the high thermal release interposer204within the IC package200ofFIG. 2, in accordance with certain aspects of the present disclosure. Although these processes are illustrated and described herein for interposer204, the reader will understand that similar processes may be followed for fabricating any of the interposers (e.g., interposer404) described herein by making appropriate adjustments and/or substitution of materials thereto.

As illustrated inFIG. 6A, a substrate604may be formed, and a chip carrier602(e.g., Detach Carrier Foil (DCF)) may be formed over the substrate604. As illustrated inFIG. 6B, a metallic (e.g., Cu) layer606may be formed over the chip carrier602, and subsequently patterned. As illustrated inFIG. 6C, a metallic (e.g., Cu) plate608may be formed over a portion of the metallic layer606. In some aspects, the metallic plate608may be formed over the portion of the metallic layer606that overlaps at least a portion of the IC die(s)110.

As illustrated inFIG. 6D, a dielectric (or insulation) layer610may be formed (e.g., via a pre-impregnated lamination process) over the exposed portions of the chip carrier602, the metallic layer606, and the metallic plate608. As illustrated inFIG. 6E, portions of the dielectric layer610and metallic plate608may be removed (e.g., via a grinding process). As illustrated inFIG. 6F, a metallic layer612may be formed over the dielectric layer610and the metallic plate608, and subsequently patterned. The dielectric layer610may include SiO2, for example.

As illustrated inFIG. 6G, the metallic layer606, metallic plate608, metallic layer612, and dielectric layer610may be separated from the chip carrier602. The metallic plate608, the portion of the metallic layer606on which the metallic plate608is formed, and the portion of the metallic layer612formed on the metallic plate608may be used to form metallic plate240of interposer204. As illustrated inFIG. 6H, a photo solder resist layer614may be formed on a top surface of the dielectric layer610and metallic layer606, and subsequently patterned, e.g., to form photo solder resist layer222of the interposer204. Similarly, a photo solder resist layer616may be formed on a bottom surface of the dielectric layer610and metallic layer612, and subsequently patterned, e.g., to form photo solder resist layer214of the interposer204.

FIG. 7is a flow diagram of example operations700for fabricating a IC package with a high thermal release interposer, in accordance with certain aspects of the present disclosure. The operations700may be performed, for example, by a semiconductor processing chamber.

The operations700begin, at block702, by forming a package substrate (e.g., package substrate102), and at block704, forming at least one semiconductor die (e.g., IC die(s)110) above the package substrate. At block706, an interposer (e.g., interposer204) is formed above the at least one semiconductor die. The interposer may be formed by forming a dielectric layer (e.g., dielectric layer218), and forming a metallic plate (e.g., metallic plate240) adjacent to a first portion (e.g., portion234or portion246) of the dielectric layer. A height of the metallic plate is greater than a height of the dielectric layer. In some aspects, operations700may include forming the metallic plate between the first portion (e.g., portion246) of the dielectric layer and a second portion (e.g., portion234) of the dielectric layer, e.g., as shown inFIG. 2.

According to certain aspects, operations700may further include forming a first metallic layer (e.g., metallic layer216) below the dielectric layer, and forming a second metallic layer (e.g., metallic layer220) above the dielectric layer. In this aspect, operations700may include forming the metallic plate adjacent to a first portion (e.g., portion248or portion236) of the first metallic layer and a first portion (e.g., portion244or portion232) of the second metallic layer. In some cases, the metallic plate240may be disposed between the portions248and244of the metallic layers216and220, respectively, and the portions236and232of the metallic layers216and220, respectively, e.g., as shown inFIG. 2. In this aspect, the height of the metallic plate may be approximately equal to a sum of heights of the first metallic layer, the dielectric layer, and the second metallic layer.

According to certain aspects, operations700may further include forming a first solder resist layer (e.g., photo solder resist layer214) below the first metallic layer (e.g., metallic layer216), and forming a second solder resist layer (e.g., photo solder resist layer222) above the second metallic layer (e.g., metallic layer220). In some aspects, operations700may include forming the metallic plate adjacent to a first portion (e.g., portion242or portion230) of the second solder resist layer, e.g., as shown inFIG. 2. In some aspects, operations700may include forming the metallic plate adjacent to a first portion (e.g., portion242or portion230) of the second solder resist layer and a first portion (e.g., portion406or portion402) of the first solder resist layer, e.g., as shown inFIG. 4. In some cases, e.g., as shown inFIG. 4, the height of the metallic plate may be equal to a sum of heights of the first metallic layer, the first solder resist layer, the dielectric layer, and the second solder resist layer.

According to certain aspects, operations700may include forming at least one adhesive layer (e.g., TIM layer510) above the at least one semiconductor die and below the metallic plate. In some aspects, the metallic plate may overlap at least a portion of the at least one semiconductor die. In some aspects, operations700may include forming a first set of metallic (e.g., Cu) core balls (e.g., metallic core balls108) (or a set of solder balls) above the package substrate and below a first portion (e.g., portion246) of the dielectric layer, and forming a second set of metallic (e.g., Cu) core balls (e.g., metallic core balls108) (or a set of solder balls) above the package substrate and below a second portion (e.g., portion234) of the dielectric layer.

In some aspects, operations700may further include forming multiple metallic (e.g., Cu) core balls (e.g., metallic core balls140) below the package substrate. In some aspects, forming the metallic plate may include at least one of exposing the metallic plate at a bottom surface of the interposer for thermal coupling with the at least one semiconductor die, or exposing the metallic plate at an upper (top) surface of the interposer.

FIG. 8is an example thermal simulation800, which shows the thermal performance of different IC packages (e.g., for a central processing unit (CPU)-intensive process), in accordance with certain aspects of the present disclosure. In thermal simulation800, curve802represents the thermal performance of a “baseline” IC package (e.g., IC package100) with a conventional interposer, curve804represents the thermal performance of an “enhanced 1” IC package (e.g., IC package200) with an interposer that includes a metallic plate, and curve806represents the thermal performance of an “enhanced 2” IC package (e.g., IC package500) that includes an interposer (e.g., with a metallic plate) and a TIM layer disposed between the interposer and the IC die(s). As shown, as the logic die temperature increases, the “enhanced 1” IC package may extend the transient time-to-throttle (TTT) compared to the “baseline” IC package, and the “enhanced 2” IC package may extend the transient TTT compared to the “baseline” IC package and “enhanced 1” IC package.

FIG. 9is an example thermal simulation900, which shows the thermal performance of different IC packages (e.g., for a graphics processing unit (GPU)-intensive process), in accordance with certain aspects of the present disclosure. In thermal simulation900, curve902represents the thermal performance of a “baseline” IC package (e.g., IC package100) with a conventional interposer, curve904represents the thermal performance of an “enhanced 1” IC package (e.g., IC package200) with an interposer that includes a metallic plate, and curve906represents the thermal performance of an “enhanced 2” IC package (e.g., IC package500) that includes an interposer (e.g., with a metallic plate) and a TIM layer disposed between the interposer and the IC die(s). As shown, as the logic die temperature increases, the “enhanced 1” IC package may extend the transient TTT compared to the “baseline” IC package, and the “enhanced 2” IC package may extend the transient TTT compared to the “baseline” IC package and “enhanced 1” IC package.