Modulating germanium percentage in MOS devices

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.

BACKGROUND

Metal-Oxide Semiconductor (MOS) devices are key components of integrated circuits. The performance of MOS devices affects the performance of the entire integrated circuits in which the MOS devices are located. Therefore, methods for improving the performance of the MOS devices have been studied.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Reduction of the size and the inherent features of semiconductor devices (e.g., Metal-Oxide Semiconductor (MOS) devices) has enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the MOS devices and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and drain of a MOS device alters a resistance associated with the channel region, thereby affecting a performance of the MOS device. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the MOS device, which, assuming other parameters are maintained relatively constant, may allow an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the MOS device.

To further enhance the performance of MOS devices, stress may be introduced in the channel region of a MOS device to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (“NMOS”) device in a source-to-drain direction, and to induce a compressive stress in the channel region of a p-type MOS (“PMOS”) device in a source-to-drain direction.

An available method for applying compressive stress to the channel regions of PMOS devices is growing SiGe stressors in the source and drain regions. Such a method typically includes the steps of forming a gate stack on a semiconductor substrate, forming spacers on sidewalls of the gate stack, forming recesses in the silicon substrate along gate spacers, epitaxially growing SiGe stressors in the recesses, and annealing. Since SiGe has a lattice constant greater than that of silicon, it applies a compressive stress to the channel region, which is located between a source SiGe stressor and a drain SiGe stressor.

A process for forming a Metal-Oxide-Semiconductor (MOS) device with stressors is provided in accordance with various exemplary embodiments. The intermediate stages of forming the MOS device are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIG. 1illustrates substrate20, which is a portion of wafer10. Substrate20may be a bulk semiconductor substrate such as a silicon substrate, or may have a composite structure such as a Silicon-On-Insulator (SOI) structure. Alternatively, other semiconductor materials that include group III, group IV, and/or group V elements may also be comprised in substrate20, which semiconductor materials may include silicon germanium, silicon carbon, and/or III-V compound semiconductor materials.

Gate stacks22are formed over substrate20, and include gate dielectrics24and gate electrodes26. Gate dielectrics24may comprise silicon oxide and/or a high-k material having a high k value, for example, higher than about 7. Gate electrodes26may include commonly used conductive materials such as doped polysilicon, metals, metal silicides, metal nitrides, and combinations thereof. Gate stacks22may also include hard masks28, which may comprise silicon nitride, for example, although other materials such as silicon carbide, silicon oxynitride, and the like may also be used.

As shown inFIG. 2, Lightly Doped Drain/source (LDD) regions30are formed, for example, by implanting a p-type impurity such as boron and/or indium into substrate20. Gate stacks22and hard masks28act as implantation masks so that the inner edges of LDD regions30are substantially aligned with the edges of gate stacks22, respectively. The LDD implantation may be performed using energies in a range between about 1 keV and about 10 keV, and a dosage in a range between about 1×1013/cm2and about 1×1016/cm2. It is appreciated, however, that the values recited throughout the description are merely examples, and may be changed to different values. The LDD implantation may be tilted or vertical, with the tilt angle in a range between about 0 degree and about 30 degrees. In addition, pocket regions32may also be formed, for example, by implanting an n-type impurity such as arsenic, phosphorous, or the like into substrate20. The pocket implantation may be tilted, with the tilt angle greater than the tilt angle of the LDD implantation. In some embodiments, the tilt angle of the pocket implantation is in a range between about 15 degree and about 45 degrees. For clarity, pocket regions32are not illustrated in subsequent drawings.

Referring toFIG. 3, gate spacers34are formed on the sidewalls of gate dielectrics24and gate electrodes26. In some embodiments, each of gate spacers34includes a silicon oxide layer (not shown) and a silicon nitride layer over the silicon oxide layer, wherein the silicon oxide layer may have a thickness in a range between about 15 Å and about 50 Å, and the thickness of the silicon nitride layer may be in a range between about 50 Å and about 200 Å. In alternative embodiments, gate spacers34include one or more layers, each comprising silicon oxide, silicon nitride, silicon oxynitride, and/or other dielectric materials. The available formation methods include Plasma Enhanced Chemical Vapor Deposition (PECVD), Low-Pressure Chemical Vapor Deposition (LPCVD), Sub-Atmospheric Chemical Vapor Deposition (SACVD), and other deposition methods.

As also shown inFIG. 3, in accordance with some embodiments, an isotropic etch may be performed to form openings36in substrate20. The isotropic etch may be a dry etch, wherein the etching gas may be selected from CF4, Cl2, NF3, SF6, and combinations thereof. Depth D1 of opening36may be in a range between about 150 Å and about 500 Å, for example. In alternative embodiments, the isotropic etch step inFIG. 3is skipped, and the step inFIG. 4is formed to form openings36as shown inFIG. 4.

Next, as shown inFIG. 4, a wet etch is performed to expand openings36, The wet etching may be performed, for example, using Tetra-Methyl Ammonium Hydroxide (TMAH), a potassium hydroxide (KOH) solution, or the like. In some exemplary embodiments, the TMAH solution has a concentration in a range between about 1 percent and about 30 percent. After the wet etching, facets may be formed in openings36, which facets include (111) planes of substrate20. In some exemplary embodiments, after the wet etching, depth D2 of openings36may be in a range between about 300 Å and about 800 Å, for example.

A pre-clean may be performed, for example, using an HF-based gas or a SiCoNi-based gas. The pre-clean may remove any undesirable silicon oxide that is formed as a result of the nature oxidation of the exposed surfaces in openings36.

FIG. 5illustrates the formation of epitaxy regions38. During the epitaxy, a semiconductor material such as silicon germanium (SiGe) is epitaxially grown in openings36(FIG. 4) through Selective Epitaxial Growth (SEG), forming epitaxy region(s)38. Hence, throughout the description, epitaxy regions38are also referred to as SiGe regions38. The process gases may include H2, N2, dichloro-silane (DCS), SiH4, GeH4, and/or the like. The temperature of wafer10during the epitaxy may be in a range between about 500° C. and about 900° C. In some embodiments, an etching gas is added to promote the selective growth on the exposed surfaces of substrate20, but not on dielectrics such as gate spacers34and hard masks28. The pressure of the process gases may be in a range between about 10 torr and about 200 torr.

During the epitaxy, desired p-type impurities may be doped while the growth proceeds. For example, when boron is to be doped, B2H6may be included in the process gases. In some embodiments, the impurity concentration of the p-type impurities in epitaxy regions38is between about 5E18/cm3and about 5E21/cm3. In alternative embodiments, during the epitaxy of SiGe regions38, no p-type impurity is in-situ doped, or substantially no p-type impurity (for example, with a p-type impurity concentration lower than about 1014/cm3) is doped. In these embodiments, the source and drain regions of the respective MOS device are formed in a subsequent step through implantation. Epitaxy regions38may have a first germanium atomic percentage in a range between about 30 percent and about 60 percent, for example, although different germanium percentages may also be used. In some embodiments, the top surfaces of epitaxy regions38are level with or higher than the interface between substrate20and gate dielectrics24.

Referring toFIG. 6, epitaxy layers42are grown over epitaxy regions38through an epitaxy process. In some embodiments, epitaxy layers42are SiGe layers, which have a germanium atomic percentage higher than the germanium atomic percentage in epitaxy regions38. In some embodiments, epitaxy layers42have a second germanium atomic percentage in a range between about 35 percent and about 80 percent. Throughout the description, epitaxy layers42are also referred to as piled-up SiGe regions due to their high germanium percentage. The difference between the germanium atomic percentage of piled-up SiGe regions42and SiGe regions38may also be greater than about 5 percent. The difference may also be in the range between about 5 percent and about 20 percent. The process conditions for forming piled-up SiGe regions42may be similar to the process conditions for forming epitaxy regions38, except that the ratios of silicon-containing gases to germanium-containing gases are adjusted differently. Epitaxy regions38and42in combination form parts of the source and drain regions (and also the source or drain stressors) of a MOS device, which also includes one gate stack22as its gate. Piled-up SiGe regions42have a small thickness T1, which may be smaller than about 10 nm. Thickness T1 may also be between about 1 nm and about 10 nm in some embodiments.

Furthermore, during the epitaxy for forming piled-up SiGe regions42, a p-type impurity may be in-situ doped with the proceeding of the epitaxy. In alternative embodiments, during the epitaxy of SiGe layers42, no p-type impurity is in-situ doped, or substantially no p-type impurity (for example, with a p-type impurity concentration lower than about 1014/cm3) is doped.

In some embodiments, in each of epitaxy regions38and42, the germanium percentage is substantially uniform. In alternative embodiments, either one or both of epitaxy regions38and42has a gradually and continuously changed germanium percentage. During the respective epitaxy, the flow rate of the germanium-containing precursor (such as GeH4) may be gradually and continuously changed. In these embodiments, in the layer in which the germanium percentage gradually changes, the lower portions of the layer have germanium percentages lower than the germanium percentages of the upper layers.

After the formation of piled-up SiGe regions42, capping layers44are formed over piled-up SiGe regions42through epitaxy, as shown inFIG. 7. Capping layers44may have a composition (including the elements contained therein and the percentages of the elements) different from the composition of piled-up SiGe regions42. Capping layers44may be pure silicon layers with no germanium comprised therein, or substantially pure silicon layers with, for example, less than 2 percent, or 1 percent, germanium. Accordingly, capping layers44are alternatively referred to as silicon caps throughout the description. Capping layer44may be in-situ doped with p-type impurities with the proceeding of the epitaxy, or not in-situ doped. In the embodiments that no p-type impurity or substantially no p-type impurity is doped during the epitaxy of SiGe regions38,42, and/or capping layers44, a p-type impurity implantation may be performed to form source and drain regions for the respective MOS device.

FIG. 11schematically illustrates the germanium profile (line64) in the illustrated regions inFIG. 7, wherein the profile represents the germanium percentage along the path of arrow62inFIG. 7. The respective regions38,42, and44are also illustrated to show the correspondence between the germanium percentages and the respective regions. The X-axis represents the depth measured starting from the top surface of capping layers44(FIG. 7). The Y-axis indicates the germanium percentage. SinceFIG. 11is schematic, the values of the X-axis and the Y-axis are not marked. As shown inFIG. 11, the germanium percentage in capping layers44is very low, and may be equal to zero percent. In piled-up SiGe regions42, the germanium percentage is significantly higher than that in capping layers44and the underlying epitaxy regions38. The germanium percentage in piled-up SiGe regions42is higher than the germanium percentage in epitaxy layer38by a difference AP, which may be in the range from about 5 percent to about 20 percent.

Referring back toFIG. 7, epitaxy regions42have thickness T1, and capping layers44have thickness T2 greater than thickness T1. Thickness T2 may also be significantly greater than thickness T1, for example, with ratio T2/T1 being greater than about 2. Ratio T2/T1 may also be in the range between about 2 and about 10 in some exemplary embodiments. Maintaining thickness T2 greater than thickness T1 is beneficial for reducing the morphology degradation in the resulting source and drain silicide regions. If thickness T2 is equal to or smaller than thickness T1, due to the high germanium percentage, the morphology degradation in the resulting silicide region caused by the silicidation of piled-up regions42is severe, and may cause segregation in the silicide region, and in turn cause reliability problems.

Next, hard masks28, if any, are removed, and replacement gates are formed to replace gate dielectrics24and gate electrodes26in accordance with some embodiments, as shown inFIG. 8. In alternative embodiments, gate dielectrics24and gate electrodes26(FIG. 7) are not replaced with replacement gates. In the embodiments replacement gates are formed, gate dielectrics24and gate electrodes26act as dummy gates.FIG. 8illustrates an exemplary structure including the replacement gates. The formation process may include forming Inter-Layer Dielectric (ILD)46, performing a CMP to level the top surfaces of ILD46with the top surface of gate electrodes26or hard mask28(if any), and removing the dummy gates. A gate dielectric layer and a gate electrode layer may then be formed to fill the openings left by the removed dummy gates, followed by a CMP to remove excess portions of the gate dielectric layer and the gate electrode layer. The remaining replacement gates include gate dielectrics24′ and gate electrodes26′. Gate dielectrics24′ may comprise a high-k dielectric material with a k value greater than about 7.0, for example, and gate electrodes26′ may comprise a metal or a metal alloy. ILD46may be formed of a dielectric material such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), or the like. Next, contact openings48are formed, exposing underlying capping layers44.

FIG. 9illustrates the formation of source/drain silicide regions52. Silicide regions52may be formed by depositing a thin layer (not shown) of a silicide metal, such as titanium, cobalt, nickel, tungsten, or the like, over the devices, including the exposed surfaces of capping layers44. Wafer10is then heated, which causes the silicide reaction to occur wherever the metal is in contact with silicon. As a result of the reaction, a layer of metal silicide is formed between silicon/SiGe and the metal. The un-reacted metal is selectively removed through the use of an etchant that attacks metal but does not attack silicide. As a result of the silicidation, source/drain silicide regions52extend into and penetrate through capping layers44. Source/drain silicide regions52may be in contact with piled-up SiGe regions42. In some exemplary embodiments, a top layer of each of piled-up SiGe regions42is silicided, while a bottom layer of each of piled-up SiGe regions42remains un-silicided. Accordingly, the bottom layers of piled-up SiGe regions42have top surfaces contacting the bottom surfaces of source/drain silicide regions52, and bottom surfaces contacting the top surfaces of epitaxy regions38. Furthermore, the top layers of epitaxy regions42may be level with, and on a side of, the respective adjacent silicide regions52.

FIG. 10illustrates the formation of source/drain contact plugs54, which are formed by filling a conductive material such as tungsten, copper, aluminum, titanium, cobalt, silicon, germanium, and/or the like, into openings48(FIG. 9), and performing a CMP to level the top surface of contact plugs54with the top surface of ILD46. The formation of MOS transistor60is thus finished. MOS transistor60includes epitaxy regions38,42, and possibly the remaining portions of capping layers44as the source and drain regions.

FIG. 12schematically illustrates the germanium profile (line64) in the source and drain regions and source/drain silicide regions of MOS device60. Line64represents the germanium percentage along the path of arrow62inFIG. 10. The respective regions38,42, and44/52inFIG. 10are also illustrated inFIG. 12to show the correspondence between the germanium percentages and the respective regions. The X-axis illustrates the depth measured starting from the top surface of silicide regions52(FIG. 10). The Y-axis indicates the schematic germanium percentage. SinceFIG. 12is schematic, the values of the X-axis and the Y-axis are not marked. As shown inFIG. 12, the germanium percentage (line64) in the top portion of silicide regions52is very low.

FIG. 12also schematically illustrates the metal profile (line66) in the source and drain regions of MOS device60, wherein line66reflects the relative amount of the silicide metal (for example, nickel or cobalt). In the example shownFIG. 12, silicide regions52is formed by siliciding capping layers44, and substantially no piled-up SiGe regions42are silicided. Accordingly, inFIG. 12, the amount of silicide metal significantly reduces going into piled-up SiGe regions42. In alternative embodiments, the amount of silicide metal may reduce at an intermediate level of piled-up SiGe regions42.

In the embodiments of the present disclosure, source/drain silicide regions are formed to have bottom surfaces contacting the underlying piled-up SiGe layers, which have a high germanium percent. As a result, the Schottky barrier height between the source/drain silicide regions and the respective underlying piled-up SiGe layers is reduced compared to the barrier height between the source/drain silicide regions and a SiGe layer with a lower germanium percentage. The contact resistance of the source/drain contact is thus reduced. The increased germanium percentage, however, causes the morphology in the resulting silicide to degrade, which may cause metal segregation in the silicide region. In the embodiments of the present disclosure, however, the thickness of the pile-up SiGe layer that has the high germanium percentage is very small, and the respective silicide formed due to the silicidation of the pile-up SiGe layer is very thin, and hence the degradation in morphology has minimized effect on the quality of the source/drain silicide.

In accordance with some embodiments, an integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.

In accordance with other embodiments, an integrated circuit structure includes a semiconductor substrate, and a gate stack over the semiconductor substrate, wherein the gate stack is comprised in a MOS device. A source/drain region of the MOS device extends into the semiconductor substrate. The source/drain region includes a first silicon germanium region, which has a first germanium percentage. The source/drain region further includes a second silicon germanium region over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap is over and contacting the second silicon germanium region. A metal silicide region penetrates through the silicon cap to contact the second silicon germanium region.

In accordance with yet other embodiments, a method includes forming a gate stack over a semiconductor substrate, and forming an opening extending into the semiconductor substrate, wherein the opening is on a side of the gate stack. A first epitaxy is performed to grow a first silicon germanium region in the opening, wherein the first silicon germanium region has a first germanium percentage. A second epitaxy is performed to grow a second silicon germanium region over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. The method further includes forming silicon cap substantially free from germanium over and contacting the second silicon germanium region.