Bit reordering for memory devices

The present disclosure discloses a memory device including a controller for bit reordering. The controller receives an input bit sequence including a plurality of bits with a first bit order. The controller identifies a physical location of a non-volatile memory element in the memory device and determines a correspondence between the first bit order and a second bit order based on the physical location. The controller generates an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

BACKGROUND OF THE DISCLOSURE

Field of the Disclosure

Embodiments of the present disclosure generally relate to bit reordering for memory devices such as solid state drives (SSDs).

Description of the Related Art

Flash memory SSDs have advantages over traditional hard disk drives (HDDs) in that SDDs have a higher throughput, lower read/write latency and lower power consumption. NAND flash memories in particular have a low price and a large capacity compared to other non-volatile memories (NVMs).

In a SSD system, NAND dies are connected to a memory controller, e.g., a NAND controller, via parallel data buses. Each data bus includes multiple bus lines to connect the NAND dies to the NAND controller. Crossing-over of the bus lines may require extra vertical interconnect accesses (VIAs) and board layers, and thus may increase the manufacturing costs of the SSD system. In order to avoid crossing-over of the bus lines, there is a need to reorder the bits transmitted on the data buses between the NAND dies and the NAND controller.

The bit reordering can be performed at the NAND die. One approach for bit reordering is using a swap circuit integrated in each NAND die. The swap circuit can reorder the bits at the bus interface of a NAND die according to a predetermined bit order, e.g., the swap circuit can reorder the most significant bit (MSB) as the least significant bit (LSB). However, the swap circuit integrated in each NAND die cannot reorder the bits in any arbitrary bit order.

Therefore, there is a need to arbitrarily reorder the bits transmitted on the data buses between the NAND dies and the NAND controller.

SUMMARY OF THE DISCLOSURE

One embodiment of the present disclosure discloses a memory device. The memory device comprises a plurality of non-volatile memory elements configured to process a plurality of read and/or write operations and a controller connected to the plurality of non-volatile memory elements via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of non-volatile memory elements to the controller. The controller is configured to: receive an input bit sequence including a plurality of bits with a first bit order, wherein the controller writes the input bit sequence to one of the plurality of non-volatile memory elements; identify a physical location of the non-volatile memory element in the memory device; determine a correspondence between the first bit order and a second bit order based on the physical location; and generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

Another embodiment of the present disclosure discloses a memory device. The memory device comprises a plurality of processing means configured to process a plurality of read and/or write operations and a controlling means connected to the plurality of processing means via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of processing means to the controlling means. The controlling means is configured to: receive an input bit sequence including a plurality of bits with a first bit order, wherein the controlling means writes the input bit sequence to one of the plurality of processing means; identify a physical location of the processing means in the memory device; determine a correspondence between the first bit order and a second bit order based on the physical location; and generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

Another embodiment of the present disclosure discloses a memory device. The memory device comprises a plurality of non-volatile memory elements configured to process a plurality of read and/or write operations and a controller connected to the plurality of non-volatile memory elements via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of non-volatile memory elements to the controller. The controller is configured to: receive an input bit sequence including a plurality of bits with a first bit order, wherein the controller reads the input bit sequence from one of the plurality of non-volatile memory elements; identify a physical location of the non-volatile memory element in the memory device; determine a correspondence between the first bit order and a second bit order based on the physical location; generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence; and transmit the output bit sequence to a processor in the controller for processing.

Another embodiment of the present disclosure discloses a memory device. The memory device comprises a plurality of processing means configured to process a plurality of read and/or write operations and a controlling means connected to the plurality of processing means via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of processing means to the controlling means. The controlling means is configured to: receive an input bit sequence including a plurality of bits with a first bit order, wherein the controlling means reads the input bit sequence from one of the plurality of processing means; identify a physical location of the processing means in the memory device; determine a correspondence between the first bit order and a second bit order based on the physical location; generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence; and transmit the output bit sequence to a processor in the controlling means for processing.

Another embodiment of the present disclosure discloses a method. The method comprises, receiving, by a controller in a memory device, an input bit sequence including a plurality of bits with a first bit order, wherein the controller writes the input bit sequence to one of a plurality of non-volatile memory elements in the memory device; identifying a physical location of the non-volatile memory element in the memory device; determining a correspondence between the first bit order and a second bit order based on the physical location; and generating an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

Another embodiment of the present disclosure discloses a method. The method comprises, receiving, by a controller in a memory device, an input bit sequence including a plurality of bits with a first bit order, wherein the controller reads the input bit sequence from one of a plurality of non-volatile memory elements in the memory device; identifying a physical location of the non-volatile memory element in the memory device; determining a correspondence between the first bit order and a second bit order based on the physical location; generating an output bit sequence including the plurality of bits with the second bit order based on the correspondence; and transmitting the output bit sequence to a processor in the controller for processing.

DETAILED DESCRIPTION

FIG. 1illustrates a SSD system100according to one embodiment herein. As shown inFIG. 1, the SSD system100includes a controller101and multiple dies, e.g., two dies111and112. In one embodiment, the controller101is a NAND controller and the dies111and112are NAND dies. The dies111and112are connected to the controller101via a shared data bus120. That is, the die111and the die112communicate data with the controller101via the bus120at different time periods, but not simultaneously. The shared data bus120includes 8 bus lines that construct an 8-bit channel between the dies111,112and the controller101. Thus, in each bus transaction (e.g., one data transmission via the bus120in a time period), 8 bits are transmitted on the bus120either from a die111,112to the controller101or from the controller101to a die111,112.

The dies111,112communicate 8 bits in each bus transaction with the controller101using 8 endpoints, e.g., I/O pads or terminals, at the bus interface of the dies111,112. For example, as shown inFIG. 1, the die111uses 8 endpoints P30-P37to communicate 8 bits in each bus transaction with the controller101via the bus120. Similarly, the die112uses 8 endpoints P40-P47to communicate 8 bits in each bus transaction with the controller101via the bus120.

Each of the 8 endpoints used by each die111,112is corresponding to an unique bit significance. For example, as shown inFIG. 1, P30on die111is corresponding to the MSB, as denoted by DQ(7), and P37on die111is corresponding to the LSB, as denoted by DQ(0). P31-P36are corresponding to bit significances from DQ(6) to DQ(1), respectively. That is, the bit order of P30-P37is from the MSB to the LSB (from DQ(7) to DQ(0)). Thus, for example, when the die111transmits an 8-bit sequence “00100111” (a byte with a value 39 in decimal) using P30-P37to the controller101via the bus120(e.g. a read operation), P30transmits “0”, P31transmits “0”, P32transmits “1”, P33transmits “0”, P34transmits “0”, P35transmits “1”, P36transmits “1”, and P37transmits “1”. Similarly, each of P40-P47also has the respective unique bit significance. In one embodiment, the bit significance for each endpoint on the dies111,112is predetermined or preconfigured by the manufacturer of the dies111,112, which is unchangeable after the dies111,112are manufactured.

As shown inFIG. 1, the controller101also uses 8 endpoints P20-P27at the bus interface to communicate data with the 8 endpoints on the dies111,112. Similarly, each of the 8 endpoints P20-P27used by the controller101is corresponding to a unique bit significance. In one embodiment, the bit significance for each of P20-P27is predetermined or preconfigured by the manufacturer of the SSD system100, which is unchangeable after the SSD system is manufactured. In one example, P20on controller101is corresponding to the LSB and P27on controller101is corresponding to the MSB. That is, as shown inFIG. 1, the bit order of P20-P27is from the LSB to the MSB (from DQ(0) to DQ(7)). In this example, in order to communicate data correctly between the NAND die111and the controller101, one approach is to connect P20with P37using a bus line of the bus120because P20and P37are both corresponding to the LSB and connect P27with P30using another bus line of the bus120because P27and P30are both corresponding to the MSB. However, the aforementioned approach causes crossing-over of the bus lines that connect the die111to the controller101, which is not desired.

In one embodiment of the present disclosure, the 8 endpoints on the die111or the die112can connect to P20-P27on the controller101via the bus120in any arbitrary way to avoid or reduce crossing-over of the bus lines. This is achieved by bit reordering performed by the controller101, which is described in detail below.

As shown inFIG. 1, the controller101includes a processor102, a memory103and a swap unit104. The processor102may be any computer processor capable of performing the functions described herein. The memory103may include one or more blocks of memory associated with physical addresses, such as random access memory (RAM). The swap unit104reorders the 8 bits transmitted on the bus120between the die111,112and the controller101.

As shown inFIG. 1, in one embodiment, to avoid crossing-over of the bus lines, P30is connected to P20, P31is connected to P21, P32is connected to P22, P33is connected to P23, P34is connected to P24, P35is connected to P25, P36is connected to P26and P37is connected to P27. In this way, there is no crossing-over of the bus lines that connect the die111to the controller101. As shown inFIG. 1, three are only straight bus line connections between the die111and the controller101. Similarly as shown inFIG. 1, there is no crossing-over of the bus lines that connect the die112to the controller101.

However, with the bus line connections as shown inFIG. 1, the 8 bits received at P20-P27are not in the correct bit order for the processor102to process. For example, when the die111transmits an 8-bit sequence “00100111” using P30-P37to the controller101via the bus120, P20receives “0”, P21receives “0”, P22receives “1”, P23receives “0”, P24receives “0”, P25receives “1”, P26receives “1”, and P27receives “1”. Because the bit order of P20-P27is from DQ(0) to DQ(7), the controller101receives an 8-bit sequence “11100100” at P20-P27. Thus, if the processor102directly processes the 8-bit sequence received at P20-P27, the processor102will process “11100100” (from P27-P20) while the die111actually transmits “00100111” (from P30-P37) to the controller101, which causes errors.

In one embodiment, the swap unit104reorders the 8-bit sequence received at P20-P27with the correct bit order for the processor102to process. In one embodiment, the correct bit order is the same as the bit order of the die111,112, e.g., the bit order of P30-P37for die111. The processor102checks a look-up table (LUT)105in the memory103for the bit order of P30-P37. In one embodiment, the LUT105stores a mapping or a correspondence between the bit order of P30-P37and the bit order of P20-P27, based on the die address, i.e., the physical location, of the die111in the SSD system100.

In one embodiment, the processor102sends the die address of the die111as an input to the LUT105and the LUT105outputs the bit order of P30-P37to the swap unit104. The swap unit104reorders the 8-bit sequence received at P20-P27according to the bit order of P30-P37provided by the LUT105. For example, the 8-bit sequence received at P20-P27is “11100100” according to the bit order of P20-P27, the swap unit104reorders “11100100” to generate “00100111” according to the correct bit order, i.e., the bit order of P30-P37provided by the LUT105. For example, the LSB bit “0” received at P20is reordered as the MSB (DQ(7)) and the MSB bit “1” received at P27is reordered as the LSB (DQ(0)). In this way, after the reordering, “11100100” is reordered as “00100111”.

As shown inFIG. 1, after generating the reordered 8-bit sequence, the swap unit105uses 8 endpoints P10-P17to send the reordered 8-bit sequence to the processor102. In one embodiment, the bit order of P10-P17is predetermined, e.g., from DQ(7) to DQ(0) as shown inFIG. 1. Thus, the swap unit105sends “00100111” from P10-P17to the processor102.

FIG. 1shows only one embodiment. In other embodiments, the bit order of P10-P17can be from DQ(0) to DQ(7), the bit order of P20-P27can be from DQ(7) to DQ(0), and the bit order of P30-P37can be from DQ(0) to DQ(7). In another embodiment, the die112transmits an 8-bit sequence from P40-P47to P20-P27via the bus120. The swap unit104reorders the 8-bit sequence received at P20-P27similarly as described above. The bit order of P40-P47can be the same or different from the bit order of P30-P37. In another embodiment, the 8 endpoints of die111or die112can connect to P20-P27on the controller101in arbitrary ways to avoid or reduce crossing-over of the bus lines.

The embodiments above describe the bit reordering for a read operation, e.g. the 8-bit sequence is transmitted from the die111to the controller101. In another embodiment, the 8-bit sequence is transmitted from the controller101to a die111,112, e.g., the die111, for a write operation. In this embodiment, the 8-bit sequence is transmitted from the processor102to P10-P17, the swap unit104reorders the 8-bit sequence received at P10-P17with the correct bit order and uses P20-P27to transmit the reordered 8-bit sequence to P30-P37, as described in detail below.

FIG. 2illustrates a SSD system200according to one embodiment herein. The SSD system200includes a controller201. The controller201is connected to 128 dies via 8 buses, i.e. from BUS0to BUS7, as shown inFIG. 2. In one embodiment, each of the 8 buses constructs an 8-bit channel, as described above. That is, each bus inFIG. 2includes 8 bus lines.

In one embodiment, the 128 dies are packaged in four ball grid array (BGA) packages denoted as211,212,213and214inFIG. 2. Each BGA package includes 32 dies that are connected to the controller201via 2 buses. For example, the 32 dies in BGA package211are connected to the controller201via BUS0and BUS1. In one embodiment, 16 dies in each BGA package share the same bus. For example, the 16 dies in the upper part of the BGA package211share BUS0and the 16 dies in the lower part of the BGA package211share BUS1. In one embodiment, each of the 128 dies uses its respective 8 endpoints to connect to the controller201via the corresponding shared bus, similarly as P30-P37and P40-P47described inFIG. 1. The endpoints on each die are not shown inFIG. 2for simplicity of illustration.

In one embodiment, for each bus, the controller201uses 8 endpoints to connect to the respective 8 endpoints on each of the 16 dies sharing the bus, similarly as P20-P27described inFIG. 1. Thus, in one embodiment, the controller201has totally 64 endpoints for the 8 buses. The endpoints on the controller201are not shown inFIG. 2for simplicity of illustration.

In one embodiment, for each bus, the controller201includes a respective LUT220-227and a respective swap unit230-237. For example, for BUS0, the controller201includes LUT220stored in a memory of the SSD system200and swap unit230. The memory of the SSD system200is not shown inFIG. 2for simplicity of illustration. By using the LUT and the swap unit for each bus, each of the 16 dies sharing the bus can connect to the controller201in any arbitrary way to avoid or reduce crossing-over of the bus lines that connect the die to the controller201.

In one embodiment, when one of the 16 dies transmits an 8-bit sequence to the controller201via the shared bus for a read operation, the controller201reorders the received 8-bit sequence by using the respective LUT and the swap unit, similarly as described above inFIG. 1. For example, when one of the 16 dies sharing BUS0transmits an 8-bit sequence to the controller201via an arbitrary bus line connection. The processor in the SSD system200(not shown inFIG. 2) sends the die address of the die as an input to the LUT220and the LUT220outputs the correct bit order of the die to the swap unit230. The swap unit230reorders the received 8-bit sequence to generate the 8-bit sequence with the correct bit order and sends the reordered 8-bit sequence to the processor.

In another embodiment, when the controller201transmits an 8-bit sequence to one of the 16 dies via the shared bus for a write operation, the controller201reorders the transmitted 8-bit sequence by using the respective LUT and the swap unit to generate the 8-bit sequence with the correct bit order and sends the reordered 8-bit sequence to the die.

FIG. 2shows only one embodiment. In other embodiments, the controller201can connect to a different number of dies via a different number of buses. In other embodiments, each BGA package can include a different number of dies and the dies are wired inside the BGA package. In other embodiments, each bus is shared by a different number of dies.

FIG. 3illustrates a LUT300, according to one embodiment herein. InFIG. 3, the LUT300is for one bus. For example, it is assumed that the LUT300is for the bus102inFIG. 1. That is, the LUT300is the LUT105inFIG. 1. In one embodiment, the LUT300stores a correspondence between an input bit order and an output bit order for each of the multiple dies (e.g., the dies111and112) connecting to the controller101via bus102. In one embodiment, the correspondence between an input bit order and an output bit order for a die is determined based on the die address, i.e., the physical location of the die in the SSD system100. The dies at different physical locations connect to the controller101with different bus line connections to avoid or reduce crossing-over of the bus lines. Thus, the dies at different physical locations have different correspondences between the input bit order and the output bit order.

In one embodiment, the LUT300stores a correspondence between an input bit order and an output bit order for each of the dies connecting to the controller101via bus102for read operations. For example, when the die111transmits an 8-bit sequence to the controller101, the processor102can identify that the 8-bit sequence is from the die111and the die111has address1, e.g., based on the information in the command and/or address phases. The processor102sends address1to the LUT300to retrieve the correspondence for the die111. As shown inFIG. 3, for address1, the input bit order is from DQ(0) to DQ(7), denoted as DQ(01234567), and the corresponding output bit order is from DQ(7) to DQ(0), denoted as DQ(76543210). That is, DQ(0) in the input bit sequence is reordered as DQ(7) in the output bit sequence, DQ(1) in the input bit sequence is reordered as DQ(6) in the output bit sequence, DQ(2) in the input bit sequence is reordered as DQ(5) in the output bit sequence, DQ(3) in the input bit sequence is reordered as DQ(4) in the output bit sequence, DQ(4) in the input bit sequence is reordered as DQ(3) in the output bit sequence, DQ(5) in the input bit sequence is reordered as DQ(2) in the output bit sequence, DQ(6) in the input bit sequence is reordered as DQ(1) in the output bit sequence, and DQ(7) in the input bit sequence is reordered as DQ(0) in the output bit sequence. Thus, in one embodiment, the correspondence is a bit-to-bit correspondence between each bit in the input bit sequence and each bit in the output bit sequence.

The LUT300provides the correspondence for the die with address1, i.e. the die111, to the swap unit104to reorder the input bit sequence to generate the correct output bit sequence. For example, the die111transmits an 8-bit sequence “00100111” from P30-P37to the controller101. The controller101receives an 8-bit input sequence “11100100” at P20-P27from the die111(the MSB “1” is received at P27and the LSB “0” is received at P20). Based on the correspondence for address1in LUT300, the 8-bit output sequence to the processor102is “00100111”, which is the same as the actually transmitted 8-bit sequence from the die111. Thus, the swap unit104transmits “00100111” to the processor102(the MSB “0” is transmitted at P10and the LSB “1” is transmitted at P17).

In another embodiment, the LUT300stores a correspondence between an input bit order and an output bit order for each of the dies connecting to the controller101via bus102for write operations. For example, when the controller101transmits an 8-bit sequence “00100111” from the processor102to the die111, P10-P17receive the 8-bit input sequence “00100111” (the MSB “0” is received at P10and the LSB “1” is received at P17). Based on the correspondence for address1in LUT300, the 8-bit output sequence is “11100100”. Thus, P20-P27transmits “11100100” to P30-P37(the MSB “1” is transmitted at P27and the LSB “0” is transmitted at P20). Therefore, P30-P37receive “00100111”, which is the same as the actually transmitted 8-bit sequence from the processor102.

In LUT300, the address2(the address of die112) has a different correspondence. As shown inFIG. 3, for address2, the input bit order is from DQ(0) to DQ(7), denoted as DQ(01234567), and the corresponding output bit order is also from DQ(0) to DQ(7), denoted as DQ(01234567). As explained above, the die112can connect to the controller101using a different bus line connection. Thus, the die112has a different correspondence from the die111.

The correspondence can be an arbitrary correspondence. For example, as shown inFIG. 3, for a die with an address3, the input bit order can be from DQ(0) to DQ(7), denoted as DQ(01234567), and the corresponding output bit order can be: DQ(3), DQ(4), DQ(7), DQ(5), DQ(1), DQ(2), DQ(0), DQ(6), denoted as DQ(34751206). That is, DQ(0) in the input bit sequence is reordered to be DQ(3) in the output bit sequence and DQ(7) in the input bit sequence is reordered to be DQ(6) in the output bit sequence.

In one embodiment, the LUT300is programmed into the memory103of the NAND controller101when the layout of the SSD system100is designed. For example, when designing the layout of SSD system100, the way of bus line connections (e.g., wiring) for each die to avoid or reduce crossing-over of the bus lines depends on the physical location (the die address) of the die in the SSD system100. Also, the way of bus line connections for each die determines the correspondence for bit reordering for the die. Thus, when the layout of the SSD system100is designed, the die addresses and the correspondences for bit reordering can be determined and stored into the memory103of the controller101for future use. When memory103is initialized, the LUT300is ready to use. Therefore, the controller101does not need to create the LUT300when the NAND controller101needs to perform bit reordering.

FIG. 3shows only one embodiment for either read operations or write operations. In other embodiments, the LUT300includes two different sub-tables for read operations and write operations, respectively. In other embodiments, the LUT300can include correspondences for more than two dies. For example, the LUT300can include 16 correspondences for the 16 dies in BGA211connecting to the controller201via BUS0, as shown inFIG. 2. That is, the LUT300is the LUT220inFIG. 2. In other embodiments, the LUT300can include any arbitrary correspondence between an input bit order and an output bit order.

FIG. 4Aillustrates a swap circuit400for read operations, according to one embodiment herein. The swap circuit400is included in the swap unit, e.g., the swap unit104inFIG. 1or the swap unit220inFIG. 2. The swap circuit400includes 8 selectors, e.g., the selector401and the selector408, as shown inFIG. 4A(other 6 selectors are not shown inFIG. 4Afor simplicity of illustration). In one embodiment, each of the 8 selectors includes a 1 of 8 selector to generate one output bit. For example, the selector401generates the output bit for DQ(0) (i.e., the LSB) in the 8-bit output sequence and the selector408generates the output bit for DQ(7) (i.e., the MSB) in the 8-bit output sequence. In one embodiment, the swap circuit400reorders the 8-bit input sequence based on one or more die addresses input to the LUT300.

In one example as described below, it is assumed that the swap circuit400is included in the swap unit104for read operations between the die111and the controller101, as described inFIG. 1. The 8-bit input sequence is input from the die111to each of the 8 selectors in the swap circuit400with an bit order from DQ(7) to DQ(0), as shown inFIG. 4A. The 8-bit input sequence is received at P20-P27. The processor102can identify that the die111has address1and sends address1to the LUT300. The LUT300provides the respective bit-to-bit correspondence for address1to each of the 8 selectors. For example, the LUT300provides the respective bit-to-bit correspondence to the selector401, as indicated by arrow411. A shown inFIG. 3, for address1, the input bit DQ(7) in the input 8-bit sequence is corresponding to the output bit DQ(0) in the output 8-bit sequence. Thus, the selector401selects the input bit DQ(7) in the 8-bit input sequence as the output bit DQ(0) in the 8-bit output sequence. Similarly, the LUT300provides the respective bit-to-bit correspondence to the selector408, as indicated by arrow418. The selector408selects the input bit DQ(0) in the 8-bit input sequence as the output bit DQ(7) in the 8-bit output sequence. For example, if the 8-bit input sequence received at P20-P27is “11100100”, the selector401selects the input bit1(DQ(7)) in “11100100” as the output bit DQ(0) in the 8-bit output sequence and the selector408selects the input bit0(DQ(0)) in “11100100” as the output bit DQ(7) in the 8-bit output sequence. Each of the other 6 selectors generates the respective output bit similarly. Thus, the swap circuit400generates the 8-bit output sequence “00100111” and sends the 8-bit output sequence from P10-P17to the processor102for a read operation.

FIG. 4Ashows only one embodiment. In other embodiments, based on the bit-to-bit correspondences provided by the LUT300, each selector in the swap circuit400can generate an output bit according to any arbitrary bit-to-bit correspondence between an input bit in the input bit sequence and the output bit in the output bit sequence, as understood by an ordinary person in the art.

FIG. 4Billustrates a swap circuit420for write operations, according to one embodiment herein. The swap circuit420is also included in the swap unit, e.g., the swap unit104inFIG. 1or the swap unit220inFIG. 2. Similarly as inFIG. 4A, the swap circuit420includes 8 selectors, e.g., the selector421and the selector428, as shown inFIG. 4B(other 6 selectors are not shown inFIG. 4Bfor simplicity of illustration). In one embodiment, each of the 8 selectors includes a 1 of 8 selector to generate one output bit. For example, the selector421generates the output bit for DQ(7) (i.e., the MSB) in the 8-bit output sequence and the selector428generates the output bit for DQ(0) (i.e., the LSB) in the 8-bit output sequence. In one embodiment, the swap circuit420reorders the 8-bit input sequence based on one or more die addresses input to the LUT300.

In one example as described below, it is assumed that the swap circuit420is included in the swap unit104for write operations between the NAND die111and the NAND controller101, as described inFIG. 1. The 8-bit input sequence is input from the processor102to each of the 8 selectors in the swap circuit420with an bit order from DQ(0) to DQ(7), as shown inFIG. 4B. The 8-bit input sequence is received at P10-P17. The processor102sends address1of the NAND die111to the LUT300. The LUT300provides the respective bit-to-bit correspondence for address1to each of the 8 selectors. For example, the LUT300provides the respective bit-to-bit correspondence to the selector421, as indicated by arrow431. Based on the bit-to-bit correspondence, the selector421selects the input bit DQ(0) in the 8-bit input sequence as the output bit DQ(7) in the 8-bit output sequence. Similarly, the LUT300provides the respective bit-to-bit correspondence to the selector428, as indicated by arrow438. The selector428selects the DQ(7) in the 8-bit input sequence as the output bit DQ(0) in the 8-bit output sequence. For example, if the 8-bit input sequence received at P10-P17is “01000111”, the selector421selects the input bit1(DQ(0)) in “01000111” as the output bit DQ(7) in the 8-bit output sequence and the selector428selects the input bit0(DQ(7)) in “01000111” as the output bit DQ(0) in the 8-bit output sequence. Each of the other 6 selectors generates the respective output bit similarly. The swap circuit420generates the 8-bit output sequence “11100010” and sends the 8-bit output sequence from P20-P27to the NAND die111for a write operation.

FIG. 4Bshows only one embodiment. In other embodiments, based on the bit-to-bit correspondences provided by the LUT300, each selector in the swap circuit420can generate an output bit according to any arbitrary bit-to-bit correspondence between an input bit in the input bit sequence and the output bit in the output bit sequence, as understood by an ordinary person in the art.

In one embodiment, for a read operation, the controller first sends the bits in the command and the address phases to the die and then receives the bits in the data phase from the die. When sending the bits in the command and the address phases to the die, the controller uses the swap circuit420to generate the output bit sequence to send to the die. When receiving the bits in the data phase from the die, the controller uses the swap circuit400to generate the output bit sequence to send to the processor in the controller. Thus, for a read operation, the controller uses both the swap circuit400and the swap circuit420in the swap unit. In another embodiment, for a write operation, the controller sends the bits in the command, the address and the data phases to the die by using the swap circuit420.

FIG. 5illustrates a flowchart showing a method500for bit reordering, according to one embodiment herein. At block501, the controller in a memory device receives an input bit sequence including a plurality of bits with a first bit order. For example, the controller101in the SSD system100receives an input bit sequence from the die111with a first bit order, e.g., “11100100”. At block502, the controller identifies a physical location of a non-volatile memory element in the memory device. For example, the processor102in the controller101identifies that the 111 has address1. At block503, the controller determines a correspondence between the first bit order and a second bit order based on the physical location. For example, the LUT105in the controller101determines a correspondence between the first bit order and a second bit order based on address1and provides the correspondence to the swap unit104. At block504, the controller generates an output bit sequence including the plurality of bits with the second bit order based on the correspondence. For example, the swap unit104reorders the input bit sequence based on the correspondence provided by the LUT105and generates an output bit sequence with a second bit order, e.g., “00100111”. The swap unit104sends the generated output bit sequence to the processor102.

By using the swap unit and the LUT, the controller can arbitrarily reorder the bits transmitted on the data buses between the dies and the controller. Thus, crossing-over of bus lines can be avoided or reduced, which saves the manufacturing costs of the SSD system.