Test method, test program, and test device of data processing system

A connection characteristics determination unit determines whether connection mechanisms provided in a data processing system have differences in connection characteristics in terms of hardware implementation or not. If there is no difference in the connection characteristics of the connection mechanisms, a first load test execution unit determines, for all processors, a load test combination program of a test program and a load program having a load effect, and allocates them to the processors so as to execute a load test. If there is a difference in the connection characteristics of the connection mechanisms, a second load test execution unit determines, for each of a plurality of processor groups sorted in accordance with the difference of the connection characteristics, a load test combination program of a test program and a load program having a load effect, and allocates them to a plurality of processors so as to execute a load test.

This application is a priority based on prior application No. JP 2006-161911, filed Jun. 12, 2006, in Japan.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a test method, a test program, and a test device of a data processing system which is formed as a symmetric multiprocessor which logically equivalently accesses shared devices such as memories by a plurality of processors, and particularly relates to a test method, a test program, and a test device of a data processing system which determines a combination of a test program and a load program having a high load effect and performs a long-time load test in order to examine the operation of connection mechanisms.

2. Description of the Related Arts

Conventionally, in a data processing system known as a symmetric multiprocessor, a plurality of processors on which cache devices are mounted are mutually connected by one or plural connection mechanisms, and access can be made logically and symmetrically between memory devices disposed as shared devices and the cache devices provided in the processors via the connection mechanisms. In such a data processing system, a plurality of reference operations of data and data write operations from certain processors to memory devices, operations of referencing the data which is present in the cache devices of other processors, etc. may occur simultaneously. In this case, if operation requests from the processors are generated more than the simultaneous processing capability that the connection mechanisms have, the operation requests are temporarily caused to be in an execution waiting state and sequentially processed. A long-time load test is performed for such a data processing system in order to examine the operation of the connection mechanisms in accordance with needs for example when building the system. The load test for the connection mechanism for operation examination is executed by combining a test program which confirms validity of the data referenced by processors and a load program which outputs operation requests which are more than the simultaneous processing capability to the connection mechanisms along with execution of the test program to generate a loaded state. Therefore, the test program which examines the data referencing and write operations is designed in accordance with the logic specification of the processors, the load program is designed in accordance with the hardware implementation specification of the connection mechanisms, and a combination of the load program and the test program which is expected to have a load effect is determined based on intuition and experiences upon designing, so as to execute the load test.

However, since the combination of the test program and the load program has been determined based on intuition and experiences upon designing in such a conventional test method of a data processing system, the determined combination has not been ensured to be the best combination for the operation examination of the connection mechanism, and there has been a possibility that sufficient reliability may not be obtained for the operation examination of the connection mechanisms.

SUMMARY OF THE INVENTION

According to the present invention to provide a test method, a test program, and a test device of a data processing system which enable highly reliable operation examination of connection mechanisms in a short time by automatically determining a best combination of a test program and a load program having a high load effect and performing a long-time load test with the high load.

The present invention provides a test method of a data processing device. In the present invention, the test method of the data processing system in which a plurality of processors are mutually connected by one or a plurality of connection mechanisms, the test method characterized by including

a connection characteristics determination step in which whether the connection mechanisms have a difference in connection characteristics in terms of hardware implementation or not is determined;

a first load test execution step in which, if the connection characteristics of the connection mechanisms have no difference therebetween, a load test combination program in which a test program and a load program having a load effect are combined is determined for all the processors, so as to execute a long-time load test; and

a second load test execution step in which, if the connection characteristics of the connection mechanisms have a difference therebetween, a load test combination program in which a test program and a load program having a load effect are combined is determined for each of a plurality of processor groups which are sorted in accordance with the difference of the connection characteristics, so as to execute a long-time load test.

Herein, the first load test execution step of the case in which the connection characteristics of the connection mechanisms have no difference therebetween includes

a load test combination determination step in which execution time of a no-load state in which merely the test program is executed by all the processors is compared with execution time of a loaded state of the test program when the test program is executed by one of the processors and the load program is executed by all the remaining plural processors at the same time, wherein, if the execution time of the loaded state is longer than the execution time of the no-load state, the load program is determined to have a load effect, and a load test combination program in which the test program and the load program are combined is determined;

a tuning step in which, with respect to the load test combination program, one of the processors is caused to execute the test program, the remaining processors are caused to execute the load program while changing the number of the processors, the minimum number of the processors at which the execution time of the test program is saturated and not changed even when the number of the load program execution processors is increased is obtained, and the minimum number of the processors and the determination result are added to the load test combination program so as to perform tuning; and

a load test allocating step in which, in accordance with the tuned load test combination program, the test program and load program having a high load effect are prioritized in allocation to the plurality of processors, so as to execute a long-time load test.

The load test allocating step includes

a first load test allocating step in which, if the minimum number of the processors of the tuned load test combination program fully uses all the processors which can execute the load program, or if not all the processors are fully used and there is merely one said test program, the test program is allocated to one of the processors, and the load program is allocated to all the remaining processors, so as to execute a long-time load test; and

a second load test allocating step in which, if the minimum number of the processors of the tuned load test combination program does not fully use all the processors which can execute the load program and a plurality of the test programs which belong to the load test combination program of the same configuration are present, the plurality of test programs are allocated to the plurality of processors and the load program is allocated to all the remaining processors, so as to execute a long-time load test.

The second load test execution step of the case in which the connection characteristics of the connection mechanisms have a difference therebetween includes

a load test combination determination step in which execution time of a no-load state in which merely the test program is executed by all the processors is compared with execution time of a loaded-state of the test program when the test program is executed by one of the processors and, at the same time, the load program is executed by the remaining plurality of processors while sequentially changing the processors which execute the load program, wherein, if the execution time of the loaded state is longer than the execution time of the no-load state, the load program is determined to have a load effect, and the load test combination program in which the test program and the load program are combined is determined;

a connection characteristics sorting step in which, with respect to the load test combination program, execution time of the test program is measured while changing the processor which executes the load program, and the processors of which execution time is in particular ranges are grouped and sorted into a plurality of processor groups;

a tuning step in which, with respect to the load test combination program, for each of the processor groups, one of the processors is caused to execute the test program, the remaining processors are caused to execute the load program while changing the number of the processors, the minimum number of the processors at which the execution time of the test program is saturated and not changed even when the number of the load program execution processors is increased is obtained, and the minimum number of the processors is added to the load test combination program so as to perform tuning; and

a load test allocating step in which, in accordance with the tuned load test combination program, the test program and load program having a high load effect are prioritized in allocation to the plurality of processors, so as to execute a long-time load test.

The load test allocating step is characterized by including

a first load test allocating step in which, if the minimum number of the processors of the tuned load test combination program of the processor group in which the test program is present fully uses all the processors which can execute the load program, or if not all the processors are fully used and there is merely one said test program, the test program is allocated to one of the processors of the processor group, and the load program is allocated to all the remaining processors, and, in the remaining processor groups, the load program of the respective tuned load test combination program is allocated to all the processors, so as to execute a long-time load test;

a second load test allocating step in which, if the minimum number of the processors of the tuned load test combination program of the processor group in which the test program is present does not fully use all the processors which can execute the load program and a plurality of the test programs which belong to the load test combination program of the same configuration are present, the plurality of test programs are allocated to the plurality of processors and the load program is allocated to all the remaining processors, and, in the remaining processor group, the load program of the respective tuned load test combination program is allocated to all the processors, so as to execute a long-time load test.

In the connection characteristics sorting step, a minimum integral multiple E of 2nis derived from the numbers of the processors of the plurality of the processor groups which are sorted in accordance with the execution time of the particular ranges, and the number of the processors of each of the processor groups is corrected such that the number is an integral multiple of the integral multiple E.

In the connection characteristics sorting step, if the numbers of the processors of the plurality of processor groups which are sorted in accordance with the execution time of the particular ranges are not integral multiples of the integral multiple E, the numbers of the processors are corrected by moving the processor having execution time close to the adjacent processor group on a time axis.

The load program may include at least two load programs having different load effects so as to enhance the load effect.

The test program is a program which measures the execution time by executing a test command which examines data referencing and data write by the processor; and the load program is a program which executes a load command which exerts influence in terms of hardware operation by outputting operation requests including memory exclusive control, memory interleave control, bus arbitration control, and external input/output control from the processor to the connection mechanism.

As another mode of the present invention, a test method of a data processing system in which a plurality of processors are mutually connected by one or a plurality of connection mechanisms having no difference in connection characteristics in terms of hardware implementation, is characterized by including

a load test combination determination step in which execution time of a no-load state in which merely the test program is executed by all the processors is compared with execution time of a loaded state of the test program when the test program is executed by one of the processors and the load program is executed by all the remaining plural processors at the same time, wherein, if the execution time of the loaded state is longer than the execution time of the no-load state, the load program is determined to have a load effect, and a load test combination program in which the test program and the load program are combined is determined;

a tuning step in which, with respect to the load test combination program, one of the processors is caused to execute the test program, the remaining processors are caused to execute the load program while changing the number of the processors, the minimum number of the processors at which the execution time of the test program is saturated and not changed even when the number of the load program execution processors is increased is obtained, and the minimum number of the processors is added to the load test combination program so as to perform tuning; and

a load test allocating step in which, in accordance with the tuned load test combination program, the test program and load program having a high load effect are prioritized in allocation to the plurality of processors, so as to execute a long-time load test.

In another mode of the present invention, a test method of a data processing system in which a plurality of processors are mutually connected by a plurality of connection mechanisms having a difference in connection characteristics in terms of hardware implementation, is characterized by including

a load test combination determination step in which execution time of a no-load state in which merely the test program is executed by all the processors is compared with execution time of a loaded state of the test program when the test program is executed by one of the processors and the load program is executed by all the remaining plural processors at the same time while sequentially changing the executing processors, wherein, if the execution time of the loaded state is longer than the execution time of the no-load state, the load program is determined to have a load effect, and a load test combination program in which the test program and the load program are combined is determined;

a connection characteristics sorting process in which, with respect to the load test combination program, execution time of the test program is measured while changing the processors which execute the load program, and the processors of which execution time is in particular ranges are grouped and sorted into a plurality of processor groups;

a tuning step in which, with respect to the load test combination program, one of the processors is caused to execute the test program for each processor group, the remaining processors are caused to execute the load program while changing the number of the processors, the minimum number of the processors at which the execution time of the test program is saturated and not changed even when the number of the load program execution processors is increased is obtained, and the minimum number of the processors is added to the load test combination program so as to perform tuning; and

a load test allocating step in which, in accordance with the tuned load test combination program, the test program and load program having a high load effect are prioritized in allocation to the plurality of processors, so as to execute a long-time load test.

The present invention provides a test program which is executed by a computer which controls a data processing system in which a plurality of processors are mutually connected by one or a plurality of connection mechanisms.

Such test program of the present invention is characterized by causing the computer which controls the data processing system to execute

a connection characteristics determination step in which whether the connection mechanisms have a difference in connection characteristics in terms of hardware implementation or not is determined;

a first load test execution step in which, if the connection characteristics of the connection mechanisms have no difference therebetween, a load test combination program in which a test program and a load program having a load effect are combined is determined for all the processors, so as to execute a long-time load test; and

a second load test execution step in which, if the connection characteristics of the connection mechanisms have a difference therebetween, a load test combination program in which a test program and a load program having a load effect are combined is determined for each of a plurality of processor groups which are sorted in accordance with the difference of the connection characteristics, so as to execute a long-time load test.

Herein, the first load test execution step includes

a load test combination determination step in which execution time of a no-load state in which merely the test program is executed by all the processors is compared with execution time of a loaded state of the test program when the test program is executed by one of the processors and the load program is executed by all the remaining plural processors at the same time, wherein, if the execution time of the loaded state is longer than the execution time of the no-load state, the load program is determined to have a load effect, and a load test combination program in which the test program and the load program are combined is determined;

a tuning step in which, with respect to the load test combination program, one of the processors is caused to execute the test program, the remaining processors are caused to execute the load program while changing the number of the processors, the minimum number of the processors at which the execution time of the test program is saturated and not changed even when the number of the load program execution processors is increased is obtained, and the minimum number of the processors is added to the load test combination program so as to perform tuning; and

a load test allocating step in which, in accordance with the tuned load test combination program, the test program and load program having a high load effect are prioritized in allocation to the plurality of processors, so as to execute a long-time load test.

The second load test execution step includes

a load test combination determination step in which execution time of a no-load state in which merely the test program is executed by all the processors is compared with execution time of a loaded-state of the test program when the test program is executed by one of the processors and, at the same time, the load program is executed by the remaining plurality of processors while sequentially changing the processors which execute the load program, wherein, if the execution time of the loaded state is longer than the execution time of the no-load state, the load program is determined to have a load effect, and the load test combination program in which the test program and the load program are combined is determined;

a connection characteristics sorting step in which, with respect to the load test combination program, execution time of the test program is measured while changing the processor which executes the load program, and the processors of which execution time is in particular ranges are grouped and sorted into a plurality of processor groups;

a tuning step in which, with respect to the load test combination program, for each of the processor groups, one of the processors is caused to execute the test program, the remaining processors are caused to execute the load program while changing the number of the processors, the minimum number of the processors at which the execution time of the test program is saturated and not changed even when the number of the load program execution processors is increased is obtained, and the minimum number of the processors is added to the load test combination program so as to perform tuning; and

a load test allocating step in which, in accordance with the tuned load test combination program, the test program and load program having a high load effect are prioritized in allocation to the plurality of processors, so as to execute a long-time load test.

The present invention provides a test device of a data processing system in which a plurality of processors are mutually connected by one or a plurality of connection mechanisms. For the test device, the present invention has

a connection characteristics determination unit in which whether the connection mechanisms have a difference in connection characteristics in terms of hardware implementation or not is determined;

a first load test execution unit in which, if the connection characteristics of the connection mechanisms have no difference therebetween, a load test combination program in which a test program and a load program having a load effect are combined is determined for all the processors, so as to execute a long-time load test; and

a second load test execution unit in which, if the connection characteristics of the connection mechanisms have a difference therebetween, a load test combination program in which a test program and a load program having a load effect are combined is determined for each of a plurality of processor groups which are sorted in accordance with the difference of the connection characteristics, so as to execute a long-time load test.

According to the present invention, with respect to a plurality of test programs and load programs prepared in advance, the execution time of a no-load state in which merely the test program is executed by all the processors is compared with the execution time of the test program which is executed by the processors when the test programs and the load programs are combined, and, if it is longer, the combination is determined to have a load effect and determined as a load test combination program; therefore, the combinations of the test programs and the load programs having no or low load effects can be eliminated, and an optimal combination for the load test can be determined.

The functions of the connection mechanisms are designed in a hardware specification level which is different from the logical specification serving as the design level of the load programs. Therefore, the load test combination program of which load effect is determined is executed while changing the number of the processors which execute the load program, and the minimum number of the processors which execute the load program at which the execution time of the test program is saturated is obtained and added to the load test combination program so as to perform tuning. Consequently, the processor allocation of the test program and the load program can be optimized such that high load can be achieved when a long-time load test is to be executed.

When it is unknown that the connection mechanisms do not have differences in the connection characteristics in terms of hardware implementation, with respect to the load test combination program of which load effect is determined, the execution time of the test program is obtained while changing the processors which execute the load program, the processors having close connection characteristics according to execution time are grouped and sorted into processor groups, and tuning of the load test combination program and allocation of the test program and the load program for a long-time load test is performed for each of the processor groups. Consequently, a high-load long-time load test can be efficiently executed for the data processing system having a difference in the connection characteristics of the connection mechanisms in terms of hardware implementation, reliability of the operation examination of the connection mechanisms is improved, and human-related burden can be reduced. The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description with reference to the drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1A and 1Bare block diagrams of a functional configuration showing an embodiment of a data processing system to which a load test of the present invention is applied. InFIGS. 1A and 1B, a control device12of the present embodiment which executes the load test for the data processing system10which serves as an object of the load test is provided, and the load test of the data processing system10is performed by processing functions of the control device12. The data processing system10is provided with, when viewed from the control device12which performs control management of the load test, for example, 16 processors14-1to14-16, cache devices15-1to15-16loaded on the processors14-1to14-16, memories18-1to18-4which function as shared devices, and connection mechanisms16-1to16-4mutually connecting the processors14-1to14-16and the memories18-1to18-4. In the control device12, a connection characteristics determination unit20, a first load test execution unit22, and a second load test execution unit24are provided. In addition, a test program file26and a load program file28are provided for the control device12. For example, test programs26-1,26-2, and26-3are stored in the test program file26in advance, and, for example, load programs28-1,28-2, and28-3are stored in the load program file28. The number of the test programs and the load programs which are prepared in advance is arbitrary. Each of the test programs26-1to26-3is a program which confirms validity in referencing and writing of data from a processor to a memory and referencing and writing to a cache device in another processor. Each of the load programs28-1to28-3is a program which is executed by a processor in the state in which a test program is executed by another processor and causes it to operate in order to output operation requests, which are more than the simultaneous processing capability, to connection mechanisms. More specifically, in the load test of the data processing system10, in the state in which the test program is executed by a certain processor, the load program is executed by another processor, and operation requests from the processor which are more than the simultaneous processing capability that the connection mechanisms have are output, thereby temporarily generating an execution waiting state in the processor which is executing the test program and generating a loaded state in which they are sequentially processed. When the load test in which a certain processor is caused to execute the test program and another processor is caused to execute the load program in the above described manner in the data processing system10under the instructions of the control device12, the operation of the connection mechanisms provided in the data processing system10can be examined. The test programs and the load programs executed by the processors14-1to14-16in the load test are downloaded from the control device12to all the processors prior to the load test, and, in the load test, the control device12gives an instruction to each of the processors that which test program or load program is to be executed. The data processing system10herein serving as a test object of the control device12forms a symmetric multiprocessor system which is connected so as to perform equivalent access, in terms of logical specification, to the memories18-1to18-4shared among the processors14-1to14-16and the respective cache devices15-1to15-16. However, in terms of hardware implementation, the connection mechanisms16-1to16-4of the data processing system10are equivalently connected to all the processors in some cases and are not equivalently connected thereto in some cases. More specifically, the connection mechanisms16-1to16-4can be classified into two cases, the case in which there is no difference in connection characteristics with respect to the processors14-1to14-16and the case in which there is difference in the connection characteristics. In the load test by means of the control device12of the present embodiment, they are classified into the case in which there is no difference in the connection characteristics of the connection mechanisms and the case in which there is difference in the connection characteristics to execute a test process. Therefore, a connection characteristics determination unit20is provided in the control device12and determines whether it is apparent that the connection mechanisms16-1to16-4of the data processing system10serving as a test object has no difference in the connection characteristics in terms of hardware implementation or has difference (including the cases in which presence of difference is unknown) When it is apparent that the connection characteristics of the connection mechanisms have no difference, the first load test execution unit22determines a load test combination program in which the test programs and the load programs having load effects are combined for all the processors14-1to14-16, allocates the test programs to part of the processors14-1to14-16, allocates the load programs to the rest, and executes a long-time load test. On the other hand, when the connection characteristics of the connection mechanisms have difference (including the cases in which presence of the difference is unknown), the second load test execution unit24sorts them into a plurality of processor groups in accordance with the difference in the connection characteristics obtained through measurement of the load effects which depend on the combinations of the test programs and the load programs, determines a load test combination program in which the test programs and the load programs having load effects are combined for each of the processor groups, allocates the determined test program and the load program to each of the processor groups, and executes a long-time load test. In the first load test execution unit22which executes the load test in the case in which the connection characteristics have no difference therebetween as described above, as processing functions thereof, a load test combination determination unit30-1, a tuning unit34-1, and a load test allocating unit36-1are provided; and, furthermore, the load test allocating unit36-1is composed of a first load test allocating unit38-1and a second load test allocating unit40-1. In the second load test execution unit24which performs the load test in the case in which the connection characteristics of the connection mechanisms have difference therebetween, a load test combination determination unit30-2, a connection characteristics sorting unit32, a tuning unit34-2, and a load test allocating unit36-2are provided; and, furthermore, the load test allocating unit36-2is composed of a first load test allocating unit38-2and a second load test allocating unit40-2. Specific examples of the case in which the connection characteristics of the connection functions in the data processing system10have no difference therebetween and the case in which the connection characteristics of the connection functions have difference will be described below.

FIG. 2shows, together with the control device12, a data processing system10-1of the case in which the connection mechanisms have no difference therebetween in the connection characteristics in terms of hardware implementation. The data processing system10-1has eight processors14-1to14-8, which respectively have dedicated cache devices15-1to15-8and connection mechanisms62-1to62-8, and they are connected to memories18-1and18-2serving as shared devices via the connection mechanisms62-1to62-8. Such data processing system10-1forms a symmetric multiprocessor system which equivalently accesses, in terms of logical specifications, the memories18-1and18-2shared by the processors14-1to14-8and the cache devices15-1to15-8. At the same time, all the processors are equivalently connected also in terms of hardware implementation since the processors14-1to14-8respectively have the individual connection mechanisms62-1to62-8. Therefore, it is apparent that the connection characteristics of the connection mechanisms do not have difference therebetween.

FIG. 3shows, together with the control device12, a data processing system10-2as another embodiment in which it is apparent that the connection characteristics in terms of hardware implementation have no difference. In the data processing system10-2, eight processors14-1to14-8are respectively provided with cache devices15-1to15-8and connected to a shared connection mechanism16. Therefore, a symmetric multiprocessor system which equivalently accesses, in terms of logical specifications, the memories18-1and18-2shared among the processors14-1to14-8and the cache devices15-1to15-8is formed. At the same time, also in terms of hardware implementation, all the processors14-1to14-8are equivalently connected by the connection by means of the single connection mechanism16, and it is apparent that the connection characteristic of the connection mechanism16has no difference.

FIGS. 4A and 4Bshow, together with the control device12, a data processing system10-3serving as an embodiment in which the connection characteristics have difference therebetween. The data processing system10-3has sixteen processors14-1to14-16, also sixteen cache devices15-1to15-16respectively provided therein, and four memories18-1to18-4as shared devices. Connection between the processors14-1to14-16and the memories18-1to18-4is established via four connection mechanisms16-1to16-4. The connection by means of the connection mechanisms16-1to16-4connects the processors14-1to14-4to the connection mechanism16-1, connects the processors14-5to14-8to the connection mechanisms16-2, connects the processors14-9to14-12to the connection mechanism16-3, and, furthermore, connects the processors14-13to14-16to the connection mechanism16-4; and, in this state, the connection individually connects the memories18-1to18-4to the four connection mechanisms16-1to16-4, respectively, and, furthermore, mutually connects the four connection mechanisms16-1to16-4. The data processing system10-3forms a symmetric multiprocessor system, which performs equivalent access in terms of logical specifications, for the memories18-1to18-4shared among the processors14-1to14-16and the respective cache devices15-1to15-16; however, not all the processors are equivalently connected in terms of hardware implementation, and the processors14-1to14-16respectively have differences in the connection characteristics by means of the connection mechanisms16-1to16-4. For example, when the processor14-1accesses the memory18-1, the access is made merely via the connection mechanism16-1; however, when access is made to the memory18-4, the access has to be made, for example, via the connection mechanisms16-1and16-4, and it is apparent that the connection characteristics have differences in terms of hardware implementation.

FIG. 5is a block diagram of a hardware environment of a computer which executes test programs which realize the functions of the connection characteristics determination unit20, the first load test execution unit22, and the second load test execution unit24of the control device12ofFIGS. 1A and 1B. InFIG. 5, to a bus44of a CPU40, a RAM46, a ROM48, a hard disk drive50, a device interface52connecting a keyboard54, a mouse56,a display58, and a network adapter60which connects a network path25to the data processing system10. The test programs of the present embodiment are stored in the hard disk drive50. When the computer is activated, the test programs are read from the hard disk drive50to the RAM46after activating an OS by the boot-up and executed by the CPU40.

FIG. 6is a flow chart showing a processing procedure of the test programs which realizes the load test of the present embodiment. The process ofFIG. 6will be described below in accordance with the functional configuration of the control device12shown inFIGS. 1A and 1B. In the control device12, when the load test for the data processing system10is activated, first of all, in step S1, the connection characteristics determination unit20determines whether it is apparent or not that the data processing system10serving as the test object has no difference in the connection characteristics of the connection mechanisms. In this case, when the data processing system serving as the test object is like the data processing system10-1ofFIG. 2or the data processing system10-2ofFIG. 3, it is apparent that the connection characteristics of the connection mechanisms have no difference therebetween; therefore, the processes of steps S2to S4are performed. The process of step S2is executed by the load test combination determination unit30-1of the first load test execution unit22, the process of step S3is executed by the tuning unit34-1, and the process of step S4is executed by the load test allocating unit36-1. Meanwhile, if it is unknown that whether the connection characteristics of the connection mechanisms have difference therebetween or not, that is, for example a case like the data processing system10-3ofFIGS. 4A and 4B, the processes of steps S5to S8are executed. The processes of steps S5to S8correspond to the second load test execution unit24of the control device12shown inFIGS. 1A and 1B. The process of step S5is executed by the load test combination determination unit30-2, the process of step S6is executed by the connection characteristics sorting unit32, the process of step S7is executed by the tuning unit34-2, and the process of step S8is executed by the load test allocating unit36-2. Therefore, the load test process by means of the control device12according to the present embodiment will be according to detail separately in the process by the first load test execution unit22in the case in which the connection characteristics of the connection mechanisms have no difference and the case by the second load test execution unit24in which the connection characteristics of the connection mechanisms have difference. The load test combination determination unit30-1of the first load test execution unit22executes a combination determination process for, for example, the data processing system10-1ofFIG. 2in which it is apparent that the connection characteristics of the connection mechanisms have no difference through measurement of load effects of the test programs and load programs. More specifically, when the combination of the test program26-1and the load program28-1is taken as an example, first of all, the load test combination determination unit30-1executes the test programs26-1in the state in which the test programs are attached to all the processors14-1to14-8, and measures execution time T1in a no-load state. The execution time T1is obtained as a difference between the start time and the end time of the test programs.

FIG. 7Ais an explanatory diagram of a measurement process of the execution time in execution of the test programs performed by the processors14-1to14-8, wherein the same test programs26-1are allocated to and executed by all the processors14-1to14-8so as to obtain the execution time T1of the test program. Herein, eight periods of the test time can be measured for the eight processors14-1to14-8; however, any one of the processors, for example, the processor14-1may be used as a representative to obtain the measurement time T1, or the execution time T1may be obtained from the mean value of all of the measurement time periods. Then, as shown inFIG. 7B, the same test programs26-1are allocated to the processors14-1to14-7, at the same time the load program28-1is allocated to the processor14-8, and they are executed at the same time, thereby measuring execution time T11of the test programs in the loaded state in which the test programs26-1and the load program28-1are combined. Then, when the execution time T11of the loaded state is longer than the execution time T1of the no-load state, it is determined that the load program28-1has a load effect, and a load test combination program in which the test program26-1and the load program28-1are combined is determined.

FIG. 8shows a list of measurement results obtained by performing measurement tests of load effects by the load test combination determination unit30-1for all the combinations of the three test programs26-1to26-3and the load programs28-1to28-3provided in the test program file26and the load program file28ofFIGS. 1A and 1B. In the list of the measurement results, T1, T2, and T3are obtained for the test programs26-1to26-3as independent execution time, i.e., execution time of the no-load state. Also, T11to T33are obtained as combination execution time of the loaded states in which each of the load programs28-1to28-3is combined with the test programs26-1to26-3. When such list of measurement results is obtained, the independent execution time of the test programs and the execution time of the combinations with the load programs are compared with each other. If the combination execution time is longer, the combination is determined to have a load effect and is determined as an effective combination. In the list of the measurement results, although the combination of the test program26-1and the load program28-2is excluded since the combination execution time T12is shorter than the independent execution time T1, except for that, all of them are determined as effective combinations having load effects. In addition, priorities 1 to 8 are set for the combinations of the test programs and the load programs in the descending order of the combination execution time. As a result of setting the priorities indicating the degrees of load effects in the above described manner for the combinations of the test programs and load programs having load effects, when the long-time load test is to be performed by actually allocating the test programs and load programs to the processors, the load test of high load can be performed by selecting the combinations of the test programs and the load programs in the descending order of load effects, i.e., the descending order of priorities. Next, the tuning process in step S3ofFIG. 6by the tuning unit34-1ofFIGS. 1A and 1Bwill be according to the tuning process, when, for example, the combination of the test program26-1and the load program28-1is taken as an example for the load test combination program determined in step S2and for the eight processors14-1to14-8in the data processing system10-1ofFIG. 2serving as a test object, one of the processors is caused to execute the test program26-1, the other seven processors are caused to execute the load program while changing the number of the processors that execute the load program28-1, the minimum number of the processors with which the execution time of the test program26-1is not changed but saturated even when the number of the processors that execute the load program is increased is obtained, and the minimum number of the processors is added to the already-determined load test combination program so as to perform tuning. In this tuning of the load test combination program, optimal numbers of the test programs and the load programs allocated to the processors are determined while testing the load effects, since, merely by determining the combination of the test program and the load program having a load effect, it is unknown that how the test programs and the load programs should be allocated in order to realize a high-load test in the plurality of processors which are to be subjected to the load test.

FIGS. 9A to 9Dare explanatory diagrams of the tuning process of combinations of the load program28-1and the test program. In this process, instead of sequentially increasing the number of the processors which execute the load program, the load program is allocated to all the processors at the beginning, and the number of the processors which execute the test program is sequentially increased from this state, thereby achieving efficiency of the process. More specifically, as shown inFIG. 9A, in the tuning process, first of all, the load program28-1is allocated to all the eight processors14-1to14-8; and then, as shown inFIG. 9B, in the state in which the test program26-1is allocated to one processor, for example, the processor14-1, the test program and the load program are executed by the processors14-1to14-8, and the execution time of the test program26-1is measured. Hereinafter, as shown inFIGS. 9C and 9D, the number of the processors which execute the test program26-1is sequentially increased, and the execution time of the test program is respectively obtained.

FIGS. 10A and 10Bshow measurement results according to the tuning process ofFIGS. 9A to 9D. InFIG. 10A, the horizontal axis represents the number of processors which execute the load program, and the vertical axis represents the test program execution time. When the number of processors serving as test objects is n, the maximum number of the processors which execute the load programs is (n−1) which is smaller than the number by one. In the case ofFIGS. 9A to 9D, since n=8, it is (n−1)=7. When, for example as shown inFIGS. 9A to 9D, the load program is allocated to all the processors which execute the load program, and subsequently, the execution time is obtained while sequentially increasing the processors which execute the test program and decreasing the processors which execute the load program; inFIG. 10A, in the state in which the number of the load program execution processors is large, the execution time is constant and in a saturated state in the manner of a straight line68, however, from the point when the number of the load allocated processors decreases to k, the execution time begins to decrease as shown by a straight line66. Above described k which is the number of the processors at this point provides a saturation point70from which the execution time of the test program does not changes even if the number of the processors which execute the load program is further increased. Therefore, in the tuning process of this case, the load program execution processor number k which provides the saturation point70is added to the combination of the test program26-1and the load program28-1as a tuning parameter. Such tuning is executed for the combinations of the test programs and load programs which are shown in the list ofFIG. 8and have load effects, and load test combination program information having the format of tuned test combination program

=(test program, load program, minimum number of processors of load saturation) is generated.FIG. 10Bis the case in which the number of the processors which execute the load program is sequentially decreased and the case in which no saturation point is generated in the middle as shown by a straight line72. More specifically, the case ofFIG. 10Bis the case in which the load saturation, from which the execution time of the test program does not further increases, cannot be obtained even when all the (n−1) processors which execute the load program are fully used. As the minimum number of the processors of load saturation added as the tuning parameter in this case, the number of all the processors that execute the load program (n−1) is added. In the case likeFIG. 10Ain which the processors for load allocation are not fully used in execution of the load program and in the case likeFIG. 10Bin which they are fully used, allocation of the test program and the load program to the processors which achieves the maximum load is performed for the test program and the load program specified by the tuned load test combination program and program allocation in the long-time load test based on the minimum number of processors under respective conditions. Next, the processes of the load test allocating unit36-1ofFIGS. 1A and 1Bwhich executes a high-load test for a long time for all the processors based on the tuned load test combination program of step S3ofFIG. 6will be according to the processes of the load test allocating unit36-1, in accordance with the tuned load test combination program, a test program and a load program having high load effects are prioritized in allocation to the plurality of processors, thereby executing the long-time load test. The processes of the load test allocating unit36-1are separated into a process by the first load test allocating unit38-1and a process by the second load test allocating unit40-1.

FIGS. 11A and 11Bshow the process by the first load test allocating unit38-1, in which, if either one of the conditions of(1) the case in which the minimum number of the processors of the tuned load test combination program fully uses all the (n−1) processors which can execute the load program and(2) the case in which all the processors are not fully used and there is merely one test program is satisfied, as shown inFIG. 11A, the test program26-1is allocated to one processor14-1, the load program28-1is allocated to all the remaining processors14-2to14-8, and the long-time load test is executed.FIG. 11Bis under the same conditions asFIG. 11A; however, it is the case in which the two load programs28-1and28-2are executed at the same time as the load program so as to enhance the load effects. Also in this case, the test program26-1is allocated to one processor14-1, and the load programs28-1and28-2are allocated to all the remaining processors14-2to14-8, and they are caused to execute the long-time load test. On the other hand, when two conditions that(1) the minimum number of the processors of the tuned load test combination program does not fully use all the (n−1) processors which can execute the load program, and(2) a plurality of test programs which belong to the load test combination program of the same configuration are present
are satisfied, as shown inFIG. 12A, the first load test allocating unit38-1, for example, allocates the two test programs26-1and26-2to the processors14-1and14-2and allocates the load program28-1to all the remaining processors14-3to14-8, and causes them to execute the long-time load test.

FIG. 12Bis the case in which two load programs28-1and28-2are used as load programs in order to further enhance load effects; wherein, as well as the conditions ofFIG. 12A, the test programs26-1and26-2are allocated to the processors14-1and14-2, the load program28-1and28-2are allocated to each of all the remaining processors14-3to14-8, and the long-time load test is executed. When allocation ofFIGS. 11A and 11Bare possible, the load test allocating unit36-1of the present embodiment gives priority to selection of the allocation ofFIG. 11Bwhich has a high load effect and causes the long-time load test to be executed, since the test program and load programs having high load effects are prioritized and allocated to the plurality of processors to execute the long-time load test.FIGS. 12A and 12Bemployed, as examples, the cases in which two test programs which belong to the load test combination program of the same configuration are present; however, when there are more than that, processors corresponding to the number of the test programs are allocated to execution of the respective programs. Next, the data processing system10-3ofFIGS. 4A and 4Bhaving differences in the connection characteristics of the connection mechanisms is taken as an example to describe the processing function of the second load test execution unit24which executes the processes of steps S5to S8ofFIG. 6and is provided in the control device12ofFIGS. 1A and 1B. The load test combination determination unit30-2of the second load test execution unit24executes a process of determining combinations having load effects among the test programs26-1to26-3of the test program file26and the load programs28-1to28-3of the load program file28. In the combination determination process, first of all, as shown inFIG. 13, the test programs26-1are executed at the same time in the state in which, for example, the test programs are allocated to all the sixteen processors14-1to14-16in the data processing system10-3ofFIGS. 4A and 4B, and the execution time of the test programs26-1in a loaded state is measured.

FIG. 14shows a list of the measurement results of the independent execution time obtained by executing merely the test program ofFIG. 13. In the list of the measurement results, independent execution time T1to T16measured by executing the test program26-1by each of the processors14-1to14-16is stored. Next, the process in which the processor which executes the load program is sequentially changed one by one while all the remaining processors execute the test program is repeated for all the sixteen processors14-1to14-16, and the execution time of the test program of each of them is measured. More specifically, the load program and the test program are allocated thereto and executed in the manner shown inFIGS. 15A to 15E.

InFIG. 15A, the load program28-1is allocated to and executed by the processor14-1at the top, the test program26-1is allocated to and executed by all the remaining processors14-2to14-16, and the execution time T2to T16of the test program26-1of the processors14-2to14-16is measured.FIG. 15Bis the case in which the load program28-1is executed by the processor14-2, andFIG. 15Cis the case in which the load program28-1is executed by the processor14-3. After that, the load program is sequentially executed by the sixteen processors in a similar manner; and, finally, the load program28-1is executed by the processor14-16as shown inFIG. 15E, and the execution time of the test program is measured for each of them.

FIG. 16is a list of the measurement results of the execution time of the test programs measured in the process ofFIGS. 15A to 15Eof load effects in which the test programs and the load program are combined. In the list of the measurement results ofFIG. 16, the test program execution processors14-1to14-16are disposed in the rows in the vertical direction, and the load program execution processors14-1to14-16are disposed in the lateral direction serving as the column direction. For example, in the confirmation process of load effects ofFIG. 15A, the load program execution processor is14-1, meanwhile, the test program execution processors are the processors14-2to14-16. The execution time T1-2to T1-16of the test programs executed by the processors14-2to14-16is stored at the positions where both of them intersect with each other. When the test results ofFIG. 14are obtained by executing the test programs ofFIG. 13, and the measurement results of the execution time ofFIG. 16are obtained by executing the combination programs ofFIGS. 15A to 15E, a load effect is determined to be present if the combination execution time of each combination of the test program and the load program is longer than the independent execution time which is according to execution of merely the test program, and the combination of the test program and the load program at that point is determined as an effective combination. For example, the independent execution time T1to T16ofFIG. 14of merely the test programs and the combination execution time T1-2to T1-16of the case in which other processors execute the test programs are compared with each other respectively for the same processors. If all the combination execution time T1-2to T1-16is longer than the independent execution time T1to T16, the combination is determined to have a load effect. Comparison with the independent execution time T1is not performed for the processor14-1executing the load program at this time, since combination execution time is not obtained therefor. Other than the comparison between the independent execution time and the combination execution time in processor units, combinations having load effects may be determined by comparing the mean time of the independent execution time with the mean time of the combination execution time. When, corresponding to step S5ofFIG. 6, a load test combination program having any of the combinations of the test programs and the load programs having load effects is determined by the load test combination determination unit30-2of the second load test execution unit24in the control device12, subsequently, the connection characteristics sorting unit32executes a connection characteristics sorting process in which the processors having close connection characteristics among the processors14-1to14-16serving as test objects are grouped and sorted into a plurality of processor groups.

FIG. 17shows an arrangement of a two-dimensional space in which the horizontal axis represents test program time and the vertical axis represents the number of processors when the test program execution time is obtained for each of the sixteen processors14-1to14-16based on the list of the measurement results of the test programs and load program shown inFIG. 16. The test program execution time of each of the processors14-1to14-16obtained from the measurement result list ofFIG. 16is plotted in the manner ofFIG. 17by obtaining the mean time of the test program execution time ofFIG. 16for each of the processors. Regarding the connection characteristics of the processors14-1to14-16in terms of hardware8with respect to the connection mechanisms16-1to16-4of the data processing system10-3ofFIGS. 4A and 4Bserving as a test object of the second load test execution unit24, the connection characteristics are close to one another in the processor units which are respectively connected to the connection mechanisms16-1to16-4; therefore, the test program execution time in the load tests are expected to be grouped in terms of time in the connection units of the connection mechanisms16-1to16-4. In the example ofFIG. 17, the processors14-1to14-16disposed in accordance with the test program execution time and the processor numbers can be separated into processor groups64-1to64-4when they are grouped in particular time ranges. The processors included in the processor groups64-1to64-4correspond to the groups of the processors which are respectively connected to, in this case, the connection mechanisms16-1to16-4ofFIGS. 4A and 4B. According to such connection characteristics of the processors in terms of hardware arrangement, even if whether the connection characteristics of the connection mechanisms in terms of hardware arrangement of the data processing system10serving as a test object have differences therebetween or not is unknown in the control device12ofFIGS. 1A and 1B, whether the connection characteristics of the connection mechanisms have differences or not can be estimated from the distribution of the test program execution time like that ofFIG. 17which is obtained in load effect processes in which the test programs and the load program are combined. Since the distribution ofFIG. 17is separated into the plurality of processor groups64-1to64-4, it is determined that the connection characteristics of the connection mechanisms have differences therebetween. On the other hand, for example, if the execution time of all the processors is included in a particular time range, they are sorted into merely one processor group. In such a case, it is determined that the connection characteristics of the connection mechanisms have no difference therebetween like the data processing system10-1or10-2ofFIG. 2orFIG. 3.

FIG. 18is an explanatory diagram in which the processor groups64-1to64-4obtained from the distribution of the test program execution time with respect to the processor numbers shown inFIG. 17are virtually disposed with respect to the connection mechanism16. The hardware configuration of the connection mechanism16is unknown when viewed from the control device12; however, the connection relation of the processor groups64-1to64-4which are collections of those having equivalent or close connection characteristics with respect to the connection mechanism16and the processors included therein can be specified. When the processor16-1to16-16are sorted into the processor groups64-1to64-4by the connection characteristics sorting process in the above described manner, the tuning process by the tuning unit34-2and the load test allocating process by the load test allocating unit36-2thereafter are executed in the units of the processor groups.

FIGS. 19A and 19Bare explanatory diagrams of a correction process in which the number of the processors included in the processor groups obtained in the connection characteristics sorting process of the present embodiment is corrected. In the sorting process for specifying the processor groups ofFIG. 17based on a measurement result list like that ofFIG. 16which is obtained in the tests in which the test programs and load program are combined and load effects are determined, sometimes, for example, not four of the sixteen processor are sorted into each of the processor groups64-1to64-4, for example five processors are sorted into the processor group64-1likeFIG. 19A, and three processors are sorted into the processor group64-3. Herein, the number of the mounted processors in terms of hardware arrangement with respect to the connection mechanisms16-1to16-4in the data processing system10-3as shown inFIGS. 4A and 4Bis normally determined in the unit of the number of processors which is an integral multiple of 2n. Therefore, a minimum integral multiple E of 2nis derived from the processor groups64-1to64-4which are sorted in accordance with particular ranges of the execution time of the test programs as shown inFIG. 19A, and the numbers of the processors of the processor groups64-1to64-4is corrected such that they are integral multiples of the integral multiple E. In the case ofFIG. 19A, the number of the processors in each of the processors64-2and64-4is four, and the minimum integral multiple E of 2nis
E=2n=4;
therefore, the processor groups are corrected such that they are integral multiples of the integral multiple E=4. For example, the number of the processors of the processor group64-1is five, and a remainder of 1 is left with respect to an integral multiple, that is, one time of the integral multiple E. Therefore, correction of moving the remainder 1 to the processor group64-3which is not in a multiple of the integral multiple E=4 as well is performed, and correction is performed such that all the numbers of the processors of the processor groups64-1to64-4after the correction are integral multiples, that is, one time of the integral multiple E=4 as shown inFIG. 19B. In the case ofFIGS. 19A and 19B, correction is performed such that they are one time of the initial integral multiple E=4; however, for example, if the number of processors of a certain processor group is 7, and the number of processors of another processor group is 9, the numbers of processors are corrected such that they are two times the initial integral multiple E=4. In the performed method, as the processor moved from the processor group64-1to the processor group64-3in the manner ofFIG. 19B, the processor14-xhaving the smallest difference with the execution time of the processors14-9,14-10, and14-12included in the processor group64-3of the movement destination is selected, and, for example, it is moved as the processor14-11. The sorting of the processor groups inFIG. 17employs a method in which certain time ranges are set for the test program execution time so as to sort it; however, they may be sorted into processor groups by sorting the test program execution time of the processors, and, when the minimum integral multiple E of 2nis found, sequentially extracting the sorted processors such that the integral multiple thereof is achieved. When the sorting process of sorting all the processors into processor groups having equivalent or close connection characteristics according to the test program execution time is finished in the above described manner, the tuning process corresponding to step S7ofFIG. 6is executed by the tuning unit34-2provided in the second load test execution unit24. The tuning process is basically same as the process of the tuning process34-1which is provided in the first load test execution unit22; however, the different point is that the tuning process is performed for each of the processor groups. In the tuning unit34-2of the second load test execution unit24, one processor among a processor group is caused to execute a test program, the remaining processors are caused to execute load program while changing the number of the processors, the minimum number of the processors at which the execution time of the test program is not changed and saturated even when the number of the processors which execute the load programs is increased is obtained, and that is added to the load test combination program of the load test program in terms of processors as a tuning parameter. In practice, instead of sequentially increasing the number of the processors serving as load objects of the processor group which execute the load programs, the load programs are allocated to all the processors, and the minimum number of the processors at which the execution time of the test programs is saturated is obtained while reducing, from this state, the processors which execute the load programs one by one.

For example, as shown inFIG. 20A, the load programs28-1are attached to all the processors14-1to14-4of the processor group64-1, next, the load programs are reduced by one by allocating the test program26-1to the processor14-1and executed as shown inFIG. 20B, and the programs are executed while sequentially increasing the processors which execute the test programs as shown inFIGS. 20C and 20D. The execution time of the test programs accompanying the execution of the test programs and the load programs in this state is obtained. When such process of confirming the load effects while changing the number of the processors which execute the load programs is performed in the processor group unit, for example, as shown inFIG. 10A, the saturation point70from which the test program execution time is not changed even when the processors are further increased is obtained at k which is in the middle of reduction from the maximum number n−1 of the number of the load program execution processors to one, and the tuning process of adding the number of the processors at the saturation point70to the load test program as the minimum number of the processors is executed. Meanwhile, in a certain processor group, when the saturation point from which the test program execution time is not changed even when the number of the processors which execute the load programs is changed is not obtained as shown inFIG. 10B, all the processors which can execute the load programs are fully used, the maximum number of the load allocatable processors in the processor group, that is, three for example in the processor group64-1ofFIGS. 20A to 20Dis added to the load test combination program as the minimum number of the processors. Then, the tuning process as shown inFIGS. 20A to 20Dis similarly repeated for the remaining processor groups64-1to64-4, and the minimum numbers of the processors are added to respective load test programs so as to perform tuning.

FIGS. 21A to 21Dare explanatory diagrams of another tuning process performed for the processor group. In this embodiment, a process of tuning a load test combination program, which is a combination with a test program, by using two load programs28-1and28-2as load programs having load effects is shown. Also in this case, for example in the state in which the load programs28-1and28-2are allocated to all the processors14-1to14-4of the processor group64-1as shown inFIG. 21A, at the beginning, one processor14-1is caused to execute the test program26-1and all the remaining processors are caused to execute the load programs28-1and28-2as shown inFIG. 21B, the execution time of the test programs is measured thereafter while increasing the processors which execute the test programs as shown inFIGS. 21C and 21D, in other words, while reducing the processors which execute the load programs28-1and28-2, and the load test combination program is tuned by obtaining the minimum number of the processors and adding the number thereto. Then, when the tuning of the load test combination program is finished, a long-time load test is executed by the load test allocating unit36-2corresponding to step S8ofFIG. 6by prioritizing the test program and load programs having high load effects in allocation to the plurality of processors in accordance with the tuned load test combination programs. The process by the load test allocation processing unit36-2can be separated into a process of the first load test allocating unit38-2and a process of the second load test allocating unit40-2. First of all, the first load test allocating unit38-2is for the case in which either condition of(1) the case in which the minimum number of the processors of load saturation according to the combination program which is tuned for the processor group in which the test program is present fully uses all the processors which can execute the load programs in the processor group or(2) the case in which not all the processors are fully used, and there is merely one test program is satisfied. In this case, as shown inFIG. 22, when the test program is disposed in the processor group64-1, the test program26-1is allocated to one processor14-1of the processor group64-1, the load programs are allocated to the remaining processors14-2to14-4, and they are caused to execute a long-time load test. At the same time, regarding the processor groups64-2to64-4in which no test program is disposed, the load programs28-2,28-3, and28-4of the load test combination programs which are tuned for the respective processor groups are allocated to all the processors in the respective processor groups, and they are caused to execute a long-time load test.

Herein,FIG. 22employs, as an example, a long-time load test which is based on the load test combination program obtained in the tuning ofFIGS. 20A to 20D. On the other hand, in the case of the load test combination program obtained by the tuning using the two load programs28-1and28-2shown inFIGS. 21A to 21D, it is as shown inFIGS. 23A and 23B.

In the first load test process ofFIGS. 23A and 23B, if the processor in which the test program is disposed is in the first processor group64-1, the test program26-1is allocated to the processor14-1from the processor group64-1, and the load programs28-1are allocated to all the remaining processors14-2to14-4. At the same time, regarding the processor groups64-2to64-4in which no test program is disposed, two load programs28-1and28-22, load programs28-31and28-32, or load programs28-41and28-42obtained in the tuning process ofFIGS. 21A to 21Dfor each of the processor groups are allocated to respective processor groups, and a long-time load test is executed in the state in which the test program and the load programs are allocated. In the test load allocation process of the present embodiment, allocation of the test program and load programs having a high load effect is prioritized to execute a long-time load test; therefore, when the load tests ofFIGS. 22,23A and23B are possible, execution of the load test ofFIGS. 23A and 23Bhaving a high load effect is prioritized. Next, the process by the second load test allocating unit40-2ofFIGS. 1A and 1Bis for the case in which two conditions that(1) the minimum number of the processors according to the combination program tuned for the processor group in which the test program is present does not fully use all the processors which can execute the load programs and(2) a plurality of test programs which belong to the load test combination program of the same configuration are present
are satisfied. In this case, as shown inFIG. 24, in the processor group64-1which is the processor group in which the test programs are present, if the test programs obtained by the load test combination program of the same configuration are four test programs26-1to26-4, the test programs26-1to26-4are respectively allocated to the processors14-1to14-4. Meanwhile, regarding the other processor groups64-2to64-4in which no test program is present, the respectively-tuned load programs28-1to28-4are allocated to all the processors in the respective processor groups, and a long-time load test is executed in the state in which the test programs and the load programs are allocated.

FIGS. 25A and 25Bexplain another process by the second load test allocating unit40-2. In this process, the test program26-1is allocated to the processor14-1of the processor group64-1in which the test programs are disposed, and, at the same time, two test programs26-21and26-22, test programs26-31and26-32, or test programs26-41and26-42are allocated to and executed by each of the processors14-2to14-4. At the same time, two load programs28-21and28-22, load programs28-31and28-32, or load programs28-41and28-42are allocated to and executed by each of the processor groups64-2to64-4in which no test program is disposed. When the load tests ofFIGS. 24,25A and25B are compared with each other herein, since that ofFIGS. 25A and 25Bhas a larger load effect, it is prioritized to execute a long-time load test. The long-time load tests ofFIGS. 22 to 25Bperformed by allocating the test program and load programs for each of the processor groups are examples, and an executable tuned load test program is selected such that the maximum load effect is achieved to perform a long-time load test.

FIG. 26AtoFIG. 26Eare flow charts showing details of processing procedures according to the test program of the present embodiment, and they will be described below with reference toFIGS. 1A and 1B.

InFIG. 26A, whether it is apparent or not that the connection mechanisms of the data processing system10serving as a test object have differences in connection characteristics in terms of hardware implementation is determined. This process is same as the process of step S1ofFIG. 6. When it is apparent that the connection characteristics in terms of hardware implementation have no differences therebetween, the processes by the first load test execution unit22shown in step S2to step S14ofFIG. 26Bare executed. The processes of steps S2to S14are those showing details of the processes of steps S2to S4ofFIG. 6. In the processes by the first load test execution unit22, in step S2, for example as shown inFIG. 7A, the test programs26-1are executed by all the processors14-1to14-8, and the execution time is measured. Next, in step S3, for example as shown inFIG. 7B, the load program is executed by one processor14-8, the test programs26-1are executed by all the remaining processors14-1to14-7, and the execution time is measured. Subsequently, in step S5, whether the execution time of the test program combined with the load program is longer than the execution time of merely the test program or not is compared and determined. If it is longer, in step S6, it is determined to have a load effect, and a load test combination program of the test program and the load program is determined. If the load effect is not obtained in step S5, another load program is selected in step S4, and the processes from step S3are repeated. The processes of steps S2to S5are the processes by the load test combination determination unit30-1ofFIGS. 1A and 1B. Next, in step S7, the number of the processors which execute the load programs is sequentially increased by the tuning unit34-1in all the processors14-1to14-8for example as shown inFIGS. 9A to 9D, and the execution time is measured. When the execution time is saturated in step S8, in step S9, the minimum number of the processors at the point of saturation is added to the load test combination program which is composed of a combination of the test program and the load program determined in step S6so as to perform tuning. Meanwhile, if the execution time is not saturated in step S8, the number of all the processors which are for load allocation is added to the load test combination program in which the test program and the load program are combined so as to perform tuning in step S10.

Subsequently, the process proceeds to step S11ofFIG. 26B, in which whether the minimum number of the processors of the load test combination program fully uses all the processors for load allocation or not is determined. If they are fully used, the process proceeds to step S13, in which, for example as shown inFIG. 11A, program allocation is performed such that the test program26-1is executed by one processor14-1and the load programs28-1are executed by all the remaining processors14-2to14-8, so as to execute a high-load test for a long time. Meanwhile, if the minimum number of the processors of the load test combination program does not fully use all the processors for load allocation in step S11, whether a plurality of test programs which can be executed by the load test combination program of the same configuration are present or not is checked in step S12. If they are plural, the process proceeds to step S14, in which, for example as shown inFIG. 12A, the test programs26-1and26-2are allocated to the plurality of processors14-1and14-2, the load programs28-1are allocated to all the remaining processors14-3to14-8, and a high-load test is executed for a long time. On the other hand, if not plural but merely one test program which is executable by the load test combination program of the same configuration is present in step S12, the process proceeds to step S13, in which, as shown inFIG. 11A, a high-load test in which the test program is executed by one processor and the load programs are executed by all the remaining processors is executed for a long time.

Referring again toFIG. 26A, in step S1, if it is unknown that the connection mechanisms of the data processing system serving as a test object have differences in the connection characteristics in terms of hardware implementation, the processes of step S15ofFIGS. 26C and 26Dto step S29ofFIG. 26Eare executed. The processes of steps S15to S29are the processes of the second load test execution unit24provided in the control device12ofFIGS. 1A and 1B, and details of the processing procedures of steps S5to S8ofFIG. 6will be shown.

In step S15ofFIGS. 26C and 26D, as shown inFIG. 13, the test programs26-1are executed by all the processors14-1to14-16, and the execution time is measured. Then, in step S16, the load program is executed by one processor while changing the processor as shown inFIGS. 15Ato15E, the test programs are executed by all the remaining processors, and the execution time is measured. Subsequently, in step S17, whether the execution time of the test program combined with the load program is longer than the execution time of merely the test program or not is determined. If it is longer, it is assumed to have a load effect, and, in step S19, the combination of the test program and the load program is assumed to be effective to determine a load test combination program. If the load effect is not exerted in step S17, another load program is selected in step S18, and the processes from step S16are repeated. The processes of steps S15to S18are the processes by the load test combination determination unit30-2provided in the second load test execution unit24ofFIGS. 1A and 1B. Next, in step S20, the processors in particular ranges of the execution time according to combination execution of the test program and the load program are collected, and processor groups are formed by performing connection characteristics sorting processes of grouping them into the processor groups64-1to64-4for example likeFIG. 17. Subsequently, in step S21, as shown inFIGS. 19A and 19B, the numbers of the processors in the formed processor groups are corrected to be integral multiples of a minimum integral multiple E of 2n. The processes of steps20and21are the processes by the connection characteristics sorting unit32ofFIGS. 1A and 1B. Next, in step S22, the number of the processors which execute the load programs is sequentially increased for the sorted processor groups, and the execution time of the test programs is measured. In this process, in practice, for example as shown inFIGS. 20A to 20DorFIGS. 21A to 21D, the execution time of the test programs is measured while sequentially reducing the number of the processors which execute the load programs in the state in which the load programs are allocated to all the processors of the processor group. Subsequently, in step S23, whether the execution time is saturated or not is determined, and if it is saturated, the minimum number of the processors at the point of saturation is added to the load test combination program to perform tuning in step S24. On the other hand, if the execution time is not saturated, the number of all the processors which are for load allocation is added to the load test combination program as a minimum number of the processors to perform tuning in step S25. The processes of steps S22to S25are the processes of the tuning unit34-2ofFIGS. 1A and 1B.

Next the process proceeds to step S26ofFIG. 26E, in which whether the minimum number of the processors of the load test combination program tuned for the processor group in which the test program is present fully uses all the processors for load allocation or not is determined. If it they are fully used, the process proceeds to step S28, in which, for example as shown inFIG. 22, the test program26-1is allocated to one processor14-1in the processor group64-1in which the test program is present, and the load programs28-1are allocated to all the remaining processors14-2to14-4. Furthermore, in the other processor groups64-2to64-4, the load programs28-2,28-3, and28-4obtained from the respective load test combination programs are allocated, and a high-load test is executed for a long time in this state. Meanwhile, in step S26, if the minimum number of the processors of the load test combination program does not fully use all the processors for load allocation in the processor group in which the test program is present, the process proceeds to step S27, in which whether a plurality of test programs executable by the load test combination program of the same configuration are present or not is determined. If they are plural, the process proceeds to step S29. In step S29, for example regarding the processor group64-1in which the test programs are present as shown inFIG. 24, for example if there are four test programs26-1to26-4, the test programs26-1to26-4are allocated to the plurality of processors14-1to14-4, respectively; and, in this case, if the number of the test programs is less than all the processors of the processor group64-1, load programs are allocated to all the remaining processors. Regarding the other processor groups64-2to64-4, the respective load test combination programs are allocated to all the processors, and a high-load test is executed for a long time in this allocation state. The processes of steps S26to S29are performed by the first load test allocation unit38-2and the second load test allocation unit40-2ofFIGS. 1A and 1B. In the above described embodiments, when the load test is to be started, for example as shown in step S1ofFIG. 6, whether it is apparent or unknown that the connection characteristics in terms of hardware arrangement of the connection mechanisms of the data processing system serving as a test object have differences therebetween is determined, and the processes are separately performed for the apparent case and the unknown case; however, the connection characteristics in all the connection mechanisms may be left unknown without performing such determination process of the presence of the differences in the connection characteristics of the connection mechanisms, the processes of steps S4to S8, i.e., the processes merely by the second load test execution unit24ofFIGS. 1A and 1Bmay be performed. In the processes merely by the second load test execution unit24, the process of grouping into processor groups can be performed by separation into certain ranges of execution time according to the distribution of the test program execution time obtained in the test of confirming load effects by the connection characteristics sorting unit32. If merely one processor group is generated when the process of grouping into the processor groups is performed, the process will be that for the connection mechanisms of the data processing system10-1ofFIG. 2or the data processing system10-2ofFIG. 3having no difference in the connection characteristics, and the process which is substantially same as the first load test execution unit22can be performed by executing the process in which all the processors are in one processor group. As a matter of course, when it is apparent in advance that the connection mechanisms have no difference in the connection characteristics likeFIG. 2orFIG. 3, for example it may be retrieved and determined as an answer to a question request to an operator as a process of the connection characteristics determination unit20, thereby achieving a merit that the process is simplified in the amount corresponding to the unrequired process by the connection characteristics sorting unit32in the second load test execution unit24. The present invention includes arbitrary modifications that do not impair the object and advantages thereof and is not limited by the numerical values shown in the above described embodiments.