Complementary bipolar inverter

An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.

BACKGROUND

The present invention is directed toward semiconductor circuits, and more particularly to complementary bipolar inverter circuits and methods for fabrication such circuits.

Digital logic has been dominated by silicon CMOS circuits. It's desirable to reduce the operating voltage for CMOS circuits due to increased power consumption and heating in scaled CMOS technologies. However, CMOS performance is reaching a limit due to its poor signal-to-noise margins at low operating voltages (i.e., less than 0.5 volts).

In a bipolar inverter circuit, the output current is exponentially dependent on the input voltage, giving much higher transconductance and potentially faster switching speed than CMOS. However, conventional vertical bipolar transistors are generally not suitable for high density digital logic because of their large footprint due to isolation structure, their large parasitic capacitance due to the relatively large base-collector junction area, and associated minority carrier charge storage when biased in the saturation mode, that is when the collector-base diode is forward biased.

SUMMARY

In one aspect, the present invention provides a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector.

In another aspect, the present invention provides a method for fabricating a complementary transistor inverter circuit. The method includes fabricating a lateral PNP transistor on a silicon-on-insulator substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. Another fabricating step forms a lateral NPN transistor on the silicon-on-insulator substrate. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. Next, the lateral PNP transistor and the lateral NPN transistor are electrically coupled to form an inverter. The base of the PNP and the base of the NPN are electrically connected to form the input of the inverter, and the collector of the PNP and the collector of the NPN are electrically connected to form the output of the inverter.

DETAILED DESCRIPTION

The present invention is described with reference to embodiments of the invention. Throughout the description of the invention reference is made toFIGS. 1-5. When referring to the figures, like structures and elements shown throughout are indicated with like reference numerals.

FIG. 1shows an example embodiment of a complementary transistor inverter circuit102contemplated by the present invention. The inverter circuit102includes a semiconductor-on-insulator (SOI) substrate. In a particular embodiment, the SOI wafer used has a silicon thickness between 10 nm to 100 nm, and a buried insulator thickness between 20 nm to 200 nm. The inverter circuit102further includes a lateral PNP bipolar transistor106and a lateral NPN bipolar transistor108fabricated on the silicon layer located on the buried oxide layer104. The buried oxide layer104is located on a substrate which is not shown. The lateral PNP bipolar transistor106and the NPN bipolar transistor108may be separated by a shallow insulation trench122made from dielectric material.

The lateral PNP bipolar transistor106includes a PNP base110between a PNP emitter112and a PNP collector114. The PNP base110is an n-type semiconductor region and the PNP emitter112and the PNP collector114are heavily-doped p-type semiconductor regions separated by the PNP base110. As used herein, heavy doping means introducing more than one dopant atom per one-hundred thousand atoms of silicon. The lateral PNP bipolar transistor106also includes a PNP extrinsic base region124abutting the PNP base110. The PNP extrinsic base region124is a heavily-doped n-type semiconductor region. Furthermore, the PNP base, the PNP emitter, and the PNP collector abut the SOI buried oxide104.

The lateral NPN bipolar transistor108includes a NPN base116between a NPN emitter118and a NPN collector120. The NPN base116is a p-type semiconductor region and the NPN emitter118and the NPN collector120are heavily-doped n-type semiconductor regions separated by the NPN base116. The lateral NPN bipolar transistor108also includes a NPN extrinsic base region126abutting the NPN base116. The NPN extrinsic base region126is a heavily-doped p-type semiconductor region. Furthermore, the NPN base116, the NPN emitter118, and the NPN collector120abut the SOI buried oxide104.

The inverter circuit102includes an input terminal128electrically coupled to the NPN extrinsic base region126and the PNP extrinsic base region124. Additionally, an output terminal130is electrically coupled to the NPN collector120and the PNP collector114. The inverter circuit102is powered with a power voltage line VDDelectrically coupled to the PNP emitter112and a ground voltage line electrically coupled to the NPN emitter118. The PNP base110and the NPN base116may be fabricated from silicon or silicon-germanium alloy.

With reference toFIG. 2, the PNP base110and the NPN base116may include a middle region202between a top region204and a bottom region206. The base is configured so that the middle region202has a smaller band gap than the top region204and the bottom region206. For example, the middle region is made of silicon-germanium alloy and the top and the bottom regions are made of silicon. For a detailed discussion of a transistor base with a middle region202between a top region204and a bottom region206, the reader is referred to U.S. patent application Ser. No. 12/958,647 filed Dec. 2, 2010, titled “SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR” and incorporated herein in its entirety by reference.

Referring toFIGS. 3A-3F, embodiments of the present invention include a method for fabricating a complementary transistor inverter circuit. The method includes fabricating a lateral PNP transistor on a silicon-on-insulator substrate, fabricating a lateral NPN transistor on the silicon-on-insulator substrate, and electrically coupling the lateral PNP transistor and the lateral NPN transistor to form an inverter.

AtFIG. 3A, the method includes providing a silicon-on-insulator (SOI) wafer as a starting substrate. The silicon layer304is located on the buried oxide302on a substrate which is not shown. The silicon thickness may be, for example, between 10 nm to 100 nm, and buried insulator thickness between 20 nm to 200 nm. Shallow trench isolation may be used to define active silicon device areas. This step may include removing a silicon layer between active silicon device areas, filling the trench with oxide and polishing the wafer to form a planar surface. At least one NPN transistor and PNP transistor device areas are defined during the trench isolation step.

Next, a masked implant step is used to dope the silicon p-type304to about 1×1018parts/cm3to 1×1019/cm3in the NPN device areas. Another implanting step dopes the silicon n-type to about similar concentration in the PNP device areas.

Next, atFIG. 3B, a dummy gate stack306is formed (to be removed later). The dummy gate stack306includes a dielectric layer308and a polysilicon layer310. The total gate stack height can be between 50 nm to 200 nm. The dummy gate stack can be taller than the silicon thickness to facilitate the self-aligned implant.

After creating the dummy gate stack306, the polysilicon layer and the dielectric layer are etched selective to the underlying silicon layer304. In addition, sidewall spacers312are formed by depositing a dielectric layer (e.g., nitride) followed by an etch back.

AtFIG. 3C, a self-aligned implant is performed to form heavily doped emitter314and collector316regions using the gate stack306as an implant mask. The NPN transistor is doped n-type and the PNP transistor doped p-type. The doping concentration may be in the range of 5×1019parts/cm3to 5×1020parts/cm3.

Next, atFIG. 3D, a dielectric layer318(e.g., oxide) is deposited. This is followed by polish back to form a planar surface with the polysilicon layer310of the gate stack.

AtFIG. 3E, the dummy gate is removed. This process includes etching away the exposed polysilicon layer and then the underlying dielectric layer in both the NPN and PNP transistor device areas.

AtFIG. 3F, the gate trench is refilled with polysilicon320. This step is followed by polish back to form a planar surface with the dielectric layer318. The polysilicon layer320is doped by masked implant; p-type doping for the NPN transistor and n-type doping for the PNP transistor. The doped polysilicon layer320acts as the extrinsic base for contacting the intrinsic base layer322underneath.

The inverter fabrication undergoes further processing, such as removing the dielectric layer outside the gate material while keeping the spacer intact. The process may additionally add a spacer layer before a self-aligned silicidation process. Next, a self-aligned silicidation, metalization and contact process is performed to wire the NPN and PNP transistors to form the complementary lateral SOI bipolar inverter.

One advantage of the replacement gate process flow described above is that the sacrificial dielectric layer under the polysilicon gate is used as an etch stopper for the gate stack etch process to prevent any recess in the emitter and collector areas. Furthermore, the replacement gate process is generally compatible with the conventional CMOS fabrication process.

Alternatively, a “gate first” process flow can be used in which the polysilicon layer is deposited directly on the silicon layer without the gate dielectric layer in between. In this flow, no dummy gate removal and polysilicon gate refill is needed. However, the gate stack etch will also remove the top part of the silicon layer in the emitter and collector regions in absence of an etch stopper such as a dielectric layer.

As mentioned above, the transistor bases may be fabricated from a silicon-germanium alloy.FIGS. 4A-4Gshow an example method for fabricating a complementary transistor inverter circuit using a silicon-germanium alloy for the transistor bases.

AtFIG. 4A, a silicon-germanium-on-insulator (SGOI) wafer is provided as a starting substrate. The silicon-germanium alloy layer404is located on the buried oxide402on a substrate, which is not shown. In one embodiment, the SiGe layer thickness is between 10 to 100 nm, and buried insulator thickness between 20 nm to 200 nm. The SGOI wafer can be formed by depositing a germanium layer on a SOI wafer followed by a thermal mixing process. The atomic germanium concentration can be approximately 10% to 50%.

The fabrication method may include performing a shallow trench isolation to define active device areas. This includes removing the silicon-germanium layer between active device areas, filling the trench with oxide and polishing back to form a planar surface. At least a NPN SiGe-base transistor and a PNP SiGe-base transistor device areas are defined during this step.

Next, a masked implant is used to dope the SiGe layer p-type404. The doping may be about 1×1018parts/cm3to 1×1019/cm3in the NPN device areas. Another implanting step dopes the SiGe layer n-type to about similar concentration in the PNP device areas

Next, atFIG. 4B, a dummy gate stack406is formed (to be removed later). The dummy gate stack406includes a dielectric layer408(e.g., oxide), a polysilicon layer410, and another dielectric layer412(e.g., nitride). The total gate stack height can be between 50 nm to 200 nm. The dummy gate stack can be taller than the SiGe layer thickness to facilitate the self-aligned implant.

After creating the dummy gate stack406, the polysilicon layer and the dielectric layer are etched selective to the underlying silicon-germanium alloy layer404. In addition, sidewall spacers414are formed by depositing a dielectric layer (e.g., nitride) followed by an etch back.

As shown inFIG. 4C, the SiGe layer is recessed in the emitter and collector areas. This leaves a 10 nm to 20 nm seed layer for subsequent epitaxial silicon growth.

Next, atFIG. 4D, an epitaxy silicon layer416is selectively grown in the emitter and collector areas. The silicon layer416can be in-situ doped to n-type in the NPN transistor and p-type in the PNP transistor. Alternatively, the silicon layer416can be doped by self-aligned implant similarly to those in a Si-based bipolar inverter. With the in-situ doped process, a dielectric layer is needed to protect the PNP device region when the n-doped silicon is grown over the NPN transistor area, and vise versa. The doping concentration is in the range of 5×1019parts/cm3to 5×1020parts/cm3.

Next, atFIG. 4E, a dielectric layer418(e.g., oxide) is deposited. This is followed by polish back to form a planar surface with the polysilicon layer410of the gate stack.

AtFIG. 4F, the dummy gate is removed. This process includes etching away the exposed polysilicon layer and then the underlying dielectric layer in both the NPN and PNP transistor device areas.

AtFIG. 4G, the gate trench is refilled with polysilicon420. This step is followed by polish back to form a planar surface with the dielectric layer418. The polysilicon layer420is doped by masked implant; p-type doping for the NPN transistor and n-type doping for the PNP transistor. The doped polysilicon layer420acts as the extrinsic base for contacting the intrinsic base layer422underneath.

The inverter fabrication undergoes further processing, such as removing the dielectric layer outside the gate material while keeping the spacer intact. The process may additionally add a spacer layer before a self-aligned silicidation process. Next, a self-aligned silicidation process followed by metalization and contact processes are performed to wire the NPN and PNP transistors to form the complementary SiGe-base lateral SOI bipolar inverter.

FIG. 5shows a flowchart representing an example method502for fabricating a complementary transistor inverter circuit contemplated by the present invention.

The method includes fabricating operation504, where a lateral PNP transistor is formed on a semiconductor-on-insulator (SOI) substrate. The method also includes fabricating operation506, where a lateral NPN transistor is formed on the semiconductor-on-insulator substrate. Next, coupling operation508electrically couples the lateral PNP transistor and the lateral NPN transistor to form an inverter.

As discussed above, the lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The PNP base, PNP emitter, and PNP collector abut the buried insulator of the SOI substrate. Furthermore, the lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The NPN base, NPN emitter, and NPN collector also abut the buried insulator of the SOI substrate. Additionally, coupling operation508may include electrically coupling the PNP base to the NPN base and electrically coupling the PNP collector to the NPN collector. The NPN base and the PNP base may be fabricated from silicon or silicon-germanium alloy. The buried insulator may be oxide.

Fabricating operation504may include doping a PNP region of the semiconductor-on-insulator substrate with n-type dopant to form a n-type region. A dummy stack is then formed over the PNP base and p-type dopant is implanted using the dummy stack as a mask to form a heavily-doped p-type emitter region and a heavily-doped p-type collector region. Next, the dummy stack is removed and replaced with a PNP extrinsic base region abutting the PNP base. As detailed above, the dummy stack can include a dielectric oxide layer and a semiconductor layer over the dielectric oxide layer. The PNP extrinsic base region can be a heavily-doped n-type semiconductor region. Fabrication operation504may also include forming dielectric side wall spacers along two sides of the PNP dummy stack.

Fabricating operation506may include doping a NPN region of the semiconductor-on-insulator substrate with p-type dopant to form a p-type region. A dummy stack is then formed over the NPN base and n-type dopant is implanted using the dummy stack as a mask to form heavily-doped n-type emitter and collector regions. Next, the dummy stack is removed and replaced with a NPN extrinsic base region abutting the NPN base. In this case, the dummy stack includes a dielectric oxide layer and a semiconductor layer over the dielectric oxide layer. The NPN extrinsic base region can be a heavily-doped p-type semiconductor region. Fabrication operation506may also include forming dielectric side wall spacers along two sides of the NPN dummy stack.

The method502may include forming an isolation trench between a PNP region containing the lateral PNP transistor and a NPN region containing the lateral NPN transistor. The isolation trench is then filled with a dielectric material.