Interposer with a lateral recess in a slot to facilitate connection of intermediate conductive elements to bond pads of a semiconductor die with which the interposer is assembled

An interposer including a substantially planar substrate element with a slot formed therethrough. The slot, through which bond pads of a semiconductor die are exposed upon assembly of the interposer with the semiconductor die, includes a laterally recessed area formed in only a portion of a periphery thereof. The laterally recessed area is positioned so as to expose at least a portion of an active surface of the semiconductor die located between a bond pad located adjacent an outer periphery of the semiconductor die and the outer periphery. The laterally recessed area facilitates access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. Semiconductor device assemblies and packages that include the interposer are also disclosed, as are methods for assembling semiconductor device components with the interposer and methods for packaging such assemblies.

TECHNICAL FIELD

The present invention relates generally to interposers for use in semiconductor device packages and, more specifically, to interposers that are to be assembled with semiconductor dice having bond pads arranged substantially linearly across central regions of the active surfaces thereof. In particular, the present invention relates to interposers including slots formed therethrough that are configured to facilitate the connection of bond wires to bond pads that are located proximate the edges of semiconductor dice to be assembled with the interposers. The present invention also relates to ball grid array packages including the interposers, as well as to methods for assembling the interposers with semiconductor devices and methods for forming ball grid array packages that include the interposers.

BACKGROUND ART

The dimensions of many different types of state of the art electronic devices are ever decreasing. To reduce the dimensions of electronic devices, the structures by which the microprocessors, memory devices, other semiconductor devices, and other electronic componentry of these devices are packaged and assembled with circuit boards must become more compact.

One approach to reducing the sizes of assemblies of semiconductor devices and circuit boards has been to minimize the profiles of the semiconductor devices or other electronic components upon carrier substrates (e.g., circuit boards) to which the semiconductor devices are electrically connected so as to reduce the distances the semiconductor devices protrude from the carrier substrates. Various types of packaging technologies have been developed to facilitate orientation of semiconductor devices upon carrier substrates in this manner.

One example of such a technology is the so-called “flip-chip,” or controlled collapse chip connection (C-4), technology. In flip-chip technology, the bond pads or contact pads of a semiconductor device are arranged in an array over a major surface of the semiconductor device. Flip-chip techniques are applicable to both bare and packaged semiconductor devices. A packaged flip-chip type semiconductor device, which typically has a “ball grid array” (BGA) connection pattern, typically includes a semiconductor die and a substrate element, which is typically termed an “interposer.” The interposer may be disposed over either the backside of the semiconductor die or the front (active) surface thereof.

When the interposer is positioned adjacent the backside of the semiconductor die, the bond pads of the semiconductor die are typically electrically connected by way of wire bonds or other intermediate conductive elements to corresponding contact areas on a top surface of the interposer. These contact areas communicate with corresponding bumped contact pads on the backside of the interposer. This type of flip-chip assembly is positioned adjacent to a carrier substrate with the backside of the interposer facing the carrier substrate.

If the interposer is positioned adjacent the active surface of the semiconductor die, the bond pads of the semiconductor die may be electrically connected to corresponding contact areas on an opposite, top surface of the interposer by way of intermediate conductive elements that extend through one or more holes formed in the interposer. Again, the contact areas communicate with corresponding bumped contact pads on the interposer. In this type of flip-chip semiconductor device assembly, however, the contact pads are also typically located on the top surface of the interposer. Accordingly, this type of flip-chip assembly is positioned adjacent a carrier substrate by orienting the interposer with the top surface thereof facing the carrier substrate.

In each of the foregoing types of flip-chip semiconductor devices, the contact pads of the interposer are disposed in an array that has a footprint that mirrors an arrangement of corresponding terminals formed on a carrier substrate. Each of the bond pads (on bare flip-chip semiconductor dice) or contact pads (on flip-chip packages) and its corresponding terminal may be electrically connected to one another by way of a conductive structure, such as a solder ball, that also spaces the interposer some distance away from the carrier substrate.

The space between the interposer and the carrier substrate may be left open or filled with a so-called “underfill” dielectric material that provides additional electrical insulation between the semiconductor device and the carrier substrate.

In addition, each of the foregoing types of flip-chip type semiconductor devices may include an encapsulant material covering portions or substantially all of the interposer and/or the semiconductor die.

Another approach to reducing the sizes of assemblies of semiconductor devices and carrier substrates has been to reduce the amount of “real estate,” or surface area, upon a carrier substrate that is consumed by individual semiconductor device packages. This is typically done by reducing the dimensions of the semiconductor device packages along a plane that is parallel to a plane of the substrate upon which the semiconductor device packages are to be carried. As a result of ever-decreasing package dimensions, the so-called “chip-scale package” (CSP) has been developed. The dimensions of the outer peripheries of chip-scale packages are typically substantially the same as or only slightly larger than the corresponding dimensions of the outer peripheries of the semiconductor dice that are used in chip-scale packages.

As indicated previously herein, some chip-scale packages have ball grid array connection patterns. Some ball grid array chip-scale packages include interposers that are configured to be secured over the active surfaces of semiconductor dice, with bond pads of the dice being exposed through an opening formed through the interposer. Due to the limited dimensions of chip-scale packages, the dimensions of the interposers for use therein are also constrained, as are the sizes of openings formed through the interposers. In addition, state of the art semiconductor dice typically include bond pads that are positioned very near the outer peripheries of the dice. Consequently, in order to maintain the structural integrity of chip-scale package interposers, the interposer openings may not extend a sufficient lateral distance beyond bond pads of their corresponding semiconductor devices to provide adequate clearance for the tip of a wire bonding capillary or other intermediate conductive element-forming, -positioning, or -securing apparatus to properly access the bond pads.

Accordingly, there is a need for a chip-scale package interposer that includes an opening which is configured to facilitate access to bond pads located at or near the edges of semiconductor dice by apparatus for forming, positioning, or securing intermediate conductive elements. There is also a need for a method for fabricating such interposers.

DISCLOSURE OF INVENTION

The present invention includes an interposer with a slot formed therethrough which is configured to facilitate the connection of an intermediate conductive element, such as a bond wire, to a bond pad positioned at or very near an edge of a semiconductor die to be assembled with the interposer. Semiconductor device packages that include the interposer are also within the scope of the present invention, as are methods for assembling the interposer with a semiconductor die and for forming a package that includes the interposer.

The interposer of the present invention includes a substantially planar substrate element that may be formed from any suitable material, such as resin (e.g., FR-4 resin), plastic, insulator-coated semiconductor material (e.g., silicon oxide-coated silicon), glass, ceramic, or any other suitable electrically insulative material or insulative-coated material. The interposer also includes an opening, or slot, formed therethrough. The slot is positioned to be aligned over the bond pads of a semiconductor die upon mutual positioning of the interposer and the semiconductor die. Thus, when the interposer and semiconductor die are properly oriented, the bond pads of the semiconductor die are exposed through the slot of the interposer.

A first end of the slot is configured to extend laterally beyond an outer periphery of the semiconductor die when the interposer and semiconductor die are properly oriented with respect to one another. The opposite, second end of the slot includes a laterally recessed area along only a portion thereof. The laterally recessed area of the slot is configured to receive at least a portion of a wire bonding capillary. When the interposer is properly aligned with respect to a semiconductor die, the laterally recessed area of the slot is preferably positioned adjacent a bond pad located at or very near the edge of the semiconductor die. As a result, a wire bonding capillary or other intermediate conductive element-positioning or -forming apparatus may access the bond pad located adjacent to the laterally recessed area of the slot to form an electrical connection between that bond pad and a corresponding contact area on a surface of the interposer.

A semiconductor device package incorporating teachings of the present invention includes a semiconductor die, an interposer positioned over an active surface of the semiconductor die, wire bonds connecting bond pads of the semiconductor die to corresponding contact areas of the interposer, and a quantity of encapsulant material at least partially filling the slot formed through the interposer and at least partially covering the active surface of the semiconductor die. The encapsulant material may also extend at least partially onto the surface of the interposer and above the surface of the interposer to substantially encapsulate the bond wires that connect bond pads of the semiconductor die to corresponding contact areas of the interposer.

A method for fabricating the interposer includes providing a substantially planar substrate and forming a slot therethrough at an appropriate location. In forming the slot, a laterally recessed area is formed at an end of the slot. One example of the manner in which a slot with a laterally recessed area at an end thereof may be formed includes using a first drill bit to form a first, small hole through the substantially planar substrate element at a location where the laterally recessed area of the slot is to be positioned. The remainder of the slot is formed by using a second, larger diameter drill bit (e.g., a router bit) to form a second, larger hole proximate the location of the first, small hole and by moving the second drill bit longitudinally to elongate the second hole. Alternatively, a first drill bit may be used to form a narrow slot, then a second, larger diameter drill bit may be used to widen the slot along the length thereof except in the location where the laterally recessed area is to be located. In this case, the laterally recessed area is the remaining, narrow portion of the slot formed by the first drill bit. Thus, the first, narrower slot serves as a reference by which the second, larger drill bit that is used to form the majority of the slot is positioned.

While the foregoing exemplary methods may be used to form a slot with a laterally recessed area at a portion of an end thereof on any type of substrate element, including, without limitation, a resin, a plastic, dielectric-coated silicon (e.g., silicon oxide-coated silicon), glass, ceramic and other suitable insulative or insulator-coated substrate elements, slots having a laterally recessed area formed in only a portion of a periphery (e.g., at an end) thereof may be formed by other suitable techniques. For example, if the substrate element of the interposer is formed from silicon or another etchable material, such as glass or ceramic, known patterning processes, such as the use of known masks and etchants, which are typically used in semiconductor device fabrication processes may be employed to define a slot in the substrate element, as well as a laterally recessed area in a peripheral edge of the slot.

Other features of the interposer, such as contact areas, conductive traces, conductive vias, and terminals, may be fabricated by known circuit board or semiconductor device fabrication processes.

Other features and advantages of the present invention will become apparent to those of ordinary skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.

BEST MODE(S) FOR CARRYING OUT THE INVENTION

Although it has many applications in semiconductor die packaging, an interposer or another substrate element of the present invention may best be described in relation to a board-on-chip assembly. A semiconductor device assembly10incorporating teachings of the present invention, as shown inFIGs. 1 and 2, has conductive structures46(shown inFIG. 5) (e.g, balls, bumps, or pillars of solder, another metal or metal alloy, or z-axis conductive elastomer) protruding therefrom in a ball grid array connection pattern and includes a semiconductor die20and a substrate element, which is also referred to herein as an interposer30.

The interposer30includes a substantially planar substrate element31that may be formed from any suitable material, such as resin (e.g., FR-4 resin), plastic, insulator-coated semiconductor material (e.g., silicon oxide-coated silicon), glass, ceramic, or any other suitable, electrically insulative or at least partially dielectric-coated material, and may be positioned over the active surface22of the semiconductor die20.

As shown, the interposer30includes an aperture, or slot14, formed therethrough for exposing the bond pads12of a semiconductor device20over which the interposer30is to be positioned. The slot14has a first end15that is configured to extend laterally beyond an outer periphery21of the semiconductor die20when the interposer30and semiconductor die20are properly oriented with respect to one another. As the first end15of the slot14is configured to extend beyond the outer periphery21of a semiconductor die20to which the interposer30is attached, the first end15does not restrict the flow of encapsulant material being introduced into the slot14and is, therefore, also referred to herein as a “nonmold flow restriction end.”

Another end16of the slot14, which may be located opposite the first end15, includes a laterally recessed area17in a peripheral edge18of the slot14. The laterally recessed area17provides additional lateral access to a bond pad12located at or near the outer periphery21of the semiconductor die20. Specifically, the laterally recessed area17provides additional access to bond pad12E (seeFIG. 4) that is located adjacent an outer periphery21of the semiconductor die20, which is also referred to herein as an end bond pad, at a location between the bond pad12E and the adjacent portion of the outer periphery21of the semiconductor die20, than would otherwise be available with a chip-scale package interposer. As shown, the laterally recessed area17of slot14may extend beyond the outer periphery21of the semiconductor die20when the interposer30and the semiconductor die20are properly oriented with respect to one another. By providing an additional lateral opening around a portion of the end bond pad12E, the laterally recessed area17may facilitate access to the end bond pad12E by equipment that forms or positions intermediate conductive elements43on bond pads12(e.g., a portion of a wire bonding capillary).

Although the drawings illustrate an interposer30with only a single slot14formed therethrough, interposers having more than one slot formed therethrough are also within the scope of the present invention.

Contact areas34are carried upon a top surface32of the interposer30. Preferably, the contact areas34are located proximate the slot14so as to facilitate the positioning of relatively short intermediate conductive elements43through the slot14, between the bond pads12of a semiconductor die20and the contact areas34. As illustrated inFIGS. 1 and 2, a circuit trace36extends laterally from each contact area34to a corresponding terminal38, which may also be carried upon the top surface32of the interposer30, electrically connecting each contact area34to its corresponding terminal38.

To arrive at a board-on-chip configuration, such as that illustrated inFIGS. 1 and 2, a semiconductor die20is placed below each slot14in a die attach or die-receiving area of the interposer30so as to be positioned underneath the interposer30with bond pads12of the semiconductor die20being exposed through the slot14. An active surface22of the semiconductor die20faces a backside33of the interposer30and may be secured thereto via a quantity of adhesive material40.

When a semiconductor die20has been positioned adjacent the backside33of the interposer30, the bond pads12of the semiconductor die20maybe electrically connected, by way of intermediate conductive elements43(e.g., bond wires, gold or aluminum conductors, tape automated bonding type conductors, etc.) to corresponding contact areas34on the top surface32of the interposer30. Each of the intermediate conductive elements43extends through the slot14, between a bond pad12of the semiconductor die20and its corresponding contact area34on the interposer30.

Referring now toFIG. 5, a quantity of encapsulant material45may partially or substantially fill the slot14formed through the interposer30. The encapsulant material45covers at least a portion of the active surface22of the semiconductor die20and may also cover a portion of the top surface32of the interposer30. Preferably, the encapsulant material45substantially encapsulates the intermediate conductive elements43that extend through the slot14.

The slot14and the laterally recessed area17in the peripheral edge18of the slot14at an end16of the slot14may be formed through the substantially planar substrate element31of the interposer30by any known process that is suitable for forming an opening through the material of the substantially planar substrate element31. For example, if the substantially planar substrate element31comprises silicon, glass, or ceramic, patterning techniques that are typically used in semiconductor device fabrication processes (e.g., mask and etch techniques) may be used to form the slot14and the laterally recessed area17. When a photoimageable material is used to form the interposer30, the slot14and the laterally recessed area17thereof may be formed through the substantially planar substrate element31by use of known photoimaging processes.

As another example, when the substantially planar substrate element31of the interposer30comprises a resin (e.g., FR-4 resin) or another material that has conventionally been used to form carrier substrates, the slot14may be formed by suitable machining processes (e.g., drilling or cutting). The laterally recessed area17may then be formed in a peripheral edge18of the slot14.

Turning now toFIGS. 6-6B, the slot14and the laterally recessed area17thereof may be formed through the substantially planar substrate element31by drilling.

As shown inFIG. 6, a first, small hole70may be formed through the substantially planar substrate element31at a location thereof where the formation of a laterally recessed area17is desired. By way of example, the first, small hole70may be formed by use of a drill80and a first drill bit81.

FIGS. 6A and 6Billustrate the formation of a second, wider, elongated hole72through the substantially planar substrate element31at a location where the formation of a slot14is desired, which location is adjacent and continuous with the first, small hole70. The second hole72may be formed by use of the drill80and a second drill bit82, which has a larger diameter than that of the first drill bit81. As depicted inFIG. 6A, the second drill bit82may be used to form a hole72a at a location adjacent and continuous with the location of the first, small hole70. The length of the hole72a may then be extended to form the remainder of the second hole72by moving the second drill bit82in a direction parallel to the plane of the substantially planar substrate element31while the second drill bit82is being rotated and intersects the plane of the substantially planar substrate element31, as shown in FIG.6B.

Alternatively, with reference toFIGs. 7 and 7A, the slot14and the laterally recessed area17thereof may be formed by using a drill80and a first drill bit81to form a first, small hole74through the substantially planar substrate element31at areas thereof where the slot14and the laterally recessed area17are to be located. As shown inFIG. 7, the first, small hole74may be formed by allowing the first drill bit81to penetrate the substantially planar substrate element31and, while the first drill bit81is being rotated and continues to intersect the plane of the substantially planar substrate element31, by moving the first drill bit81in a direction parallel to the plane of the substantially planar substrate element31.

FIG. 7Adepicts the introduction of a second drill bit82into the first, small hole74. The second drill bit82has a larger diameter than that of the first drill bit81(FIG.7). The first, small hole74serves as a guide to the second drill bit82as the second drill bit82is moved along the first, small hole74in a direction parallel to the plane of the substantially planar substrate element31to increase the thickness of the first small hole74and to form a second, wider hole76at locations where the slot14is to be located. Stated another way, the second drill bit82is used to form the second hole by increasing the width of the first, small hole74at all locations along the length thereof except for that at which the laterally recessed area17is to be located. The laterally recessed area17is formed by the remaining, original width portion of the first, small hole74.

Turning now toFIGS. 3-5, methods for assembling the interposer30with a semiconductor device20and for packaging a semiconductor device20are depicted.

As shown inFIG. 3, a plurality of interposers30may be provided in the form of a strip50that includes a plurality of interposers30that are physically connected in an end-to-end fashion. The strip50or each interposer30thereon may also be configured with guide holes52for handling and positioning each interposer30during automated assembly and packaging processes.

In forming semiconductor device assemblies10, a quantity of a suitable adhesive material40is applied to at least portions of one or both of the backside33of each interposer30and the active surface22of each semiconductor die20. Known processes, including, without limitation, spray coating, curtain coating, use of a doctor blade, or positioning of a film or tape bearing adhesive material40on both major surfaces thereof, may be used to apply the adhesive material40to the backside33of the interposer30, to the active surface22of the semiconductor die20, or to both backside33and active surface22. The adhesive material40is preferably positioned such that it will not cover the bond pads12of a semiconductor die20once the interposer30and semiconductor die20are assembled.

With reference toFIG. 4, a semiconductor die20may then be positioned relative to and secured to each interposer30on the strip50to form semiconductor device assemblies10that are physically connected to one another by way of the material that physically connects adjacent interposers30along the strip50. When each semiconductor die20is properly positioned relative to an interposer30on the strip50, the bond pads12of the semiconductor die20will be exposed through both the adhesive material40(FIG. 3) and the slot14formed through the interposer30. The laterally recessed area17of the slot14of each interposer30is positioned laterally adjacent to a bond pad12E that is located adjacent an outer periphery21of the semiconductor die20.

Once a semiconductor die20has been properly positioned relative to and secured to each of the interposers30on the strip50, each bond pad12of each semiconductor die20may be electrically connected to its corresponding contact area34on the interposer30by forming or placing an intermediate conductive element43between the bond pad12and the contact area34. Known processes and equipment, such as wire bonding processes and apparatus, may be used to form or place intermediate conductive elements43between each bond pad12and its corresponding contact area34. The laterally recessed area17of the slot14formed through each interposer30facilitates access by such equipment to the end bond pad12E so that an intermediate conductive element43may be more easily positioned between that bond pad12E and its corresponding contact area34on the interposer30.

Turning now toFIG. 5, at least a portion of the active surface22of each semiconductor die20may also be encapsulated, as known in the art, by introducing a quantity of a suitable encapsulant material45(e.g., a filled polymer transfer molding compound or a silicone or epoxy glob-top type encapsulant material) into the slot14. The encapsulant material45preferably covers at least portions of the active surface22of the semiconductor die20, including the bond pads12thereon. The encapsulant material45may also substantially cover the intermediate conductive elements43that extend between the bond pads12of each semiconductor die20and the corresponding contact areas34of the interposer30. Accordingly, the encapsulant material45may substantially fill the slot14and cover the regions of the top surface32of the interposer30at which the contact areas34are located.

Once the encapsulant material45has been introduced into the slot14, it is permitted to harden, set, or cure. For example, if a thermoplastic resin is used as the encapsulant material45, the encapsulant material will harden upon cooling of the same. If a transfer molding compound or other thermosetting resin is used as the encapsulant material45, the encapsulant material45may be cured by applying heat and/or pressure to the same. If the encapsulant material45is a photoimageable polymer, the encapsulant material45may be set or cured by exposing the same to an appropriate wavelength of radiation.

Conductive structures46, such as balls, bumps, or pillars formed from a conductive material, such as solder, another metal or metal alloy, or z-axis conductive elastomer, may be secured to terminals38(FIGS. 1-2) of the interposer30to facilitate the connection of semiconductor device assembly10to a carrier substrate or to another assembly, such as in a multi-chip module (MCM) configuration, as known in the art.

Adjacent semiconductor device assemblies10may be separated from one another by use of known processes, such as by saw-cutting or use of an energy beam (e.g., a laser or ion beam) to cut the strip50at locations between adjacent interposers30.

Of course, semiconductor device assemblies10may also be formed separately from one another by securing an individual interposer30and semiconductor die20to one another, as described previously herein with respect toFIG. 3, and electrically connecting the bond pads12of the semiconductor die20to corresponding contact areas34of the interposer30.

As another alternative, semiconductor device assemblies10may be formed on a larger scale, such as a wafer scale, wherein an array of physically connected interposers30is provided (e.g., on a wafer or other large-scale substrate) and semiconductor dice20, which may be separate from one another or also physically connected to one another on a large-scale substrate, are aligned with and secured to the interposers30.

Although the interposer30has been described herein in terms of a circuit board-type interposer and the method of the present invention is described in terms of assembling one or more semiconductor dice with a circuit board-type interposer, other types of substrates (e.g., other carrier substrates) that incorporate teachings of the present invention, as well as assemblies and packages including such substrate elements and assemblies, methods relating to the fabrication of such substrate elements, and assembly and packaging methods that include use of such substrate elements are also within the scope of the present invention.

Although the foregoing description contains many specifics, these should not be construed as limiting the scope of the present invention, but merely as providing illustrations of some exemplary embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention. Features from different embodiments may be employed in combination. The scope of the invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions, and modifications to the invention, as disclosed herein, which fall within the meaning and scope of the claims are to be embraced thereby.