Elongated source/drain region structure in finFET device

A semiconductor device includes a semiconductor substrate, an n-type fin field effect transistor. The n-type fin field effect transistor includes a fin structure, a gate stack, and a source/drain region. The gate stack includes a gate dielectric and a gate electrode. The gate dielectric is disposed in between the fin structure and the gate electrode. The source/drain region includes an epitaxial structure and an epitaxy coat covering the epitaxial structure. The epitaxial structure is made of a material having a lattice constant larger than a channel region. The epitaxy coat is made of a material having a lattice constant lower than the channel region.

BACKGROUND

The source/drain regions of a fin-field effect transistor (finFET) are commonly formed by epitaxy growing. Different materials are used for n-type metal-oxide-semiconductor (MOS) and p-type MOS. For example, the nMOS transistor source/drain regions are formed with silicon phosphate (SiP), and the pMOS transistor source/drain regions are formed with silicon germanium (SiGe).

Source/drain regions grown with silicon phosphate, however, suffer from drawbacks. Silicon phosphate grows in an isotropic manner. It means the silicon phosphate very often expands in lateral direction. If the silicon phosphate cannot be contained in its predetermined region, the lateral expansion can lead to serious problems. For example, when the silicon phosphate source/drain regions are formed first and followed by the formation of the silicon germanium source/drain regions. The recessing of the pMOS fin structure may cause damage to the laterally expanding nMOS source/drain regions (i.e., the silicon phosphate structure).

DETAILED DESCRIPTION

Referring toFIG. 1, a flow chart of a method100of fabricating a semiconductor device in accordance with some embodiments of the instant disclosure. The method begins with operation S110in which a first fin structure and a second fin structure are formed on a semiconductor substrate. The method continues with operation S120in which a gate stack is formed across the first fin structure and the second fin structure. Subsequently, operation S130is performed. A portion of the first fin structure is removed to form a first recess. The method continues with operation S140in which a first epitaxy structure is formed in the first recess. The first epitaxy structure includes a p-type stressor. The method continues with operation S150in which an epitaxy coat is formed on the first epitaxy structure. The epitaxy coat includes an n-type stressor. The method continues with operation S160in which a portion of the second fin structure is removed to form a second recess. The method continues with operation S170in which a second epitaxy structure is formed in the second recess. The second epitaxy structure includes the p-type stressor.

A fin field-effect transistor (FinFET) embodiment and the method of forming the same are presented. The intermediate stages of manufacturing the embodiment are illustrated. The variations of the embodiment are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIGS. 2 to 12are perspective and cross-sectional views of a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure. Referring toFIG. 2, a fin structure is formed. The FinFET includes a semiconductor substrate20, which may be a silicon semiconductor substrate, a germanium semiconductor substrate, or a semiconductor substrate formed of other semiconductor materials. The semiconductor substrate20may be doped with a p-type or an n-type impurity. Isolation regions such as shallow trench isolation (STI) regions22may be formed in or over the semiconductor substrate20. The fin structures124and324are formed above top surfaces of the STI regions22. In some embodiments, the fin structures124and324are formed by recessing top portions of semiconductor substrate20between neighbouring the STI regions22to form recesses, and re-growing fin in the recesses. Top portions of the STI regions22may then be removed, while bottom portions of the STI regions22are not, so that the top portion of the re-grown fin between neighbouring the STI regions22becomes the fin structures124and324. In some embodiments, the fin structures124and324are formed by patterning and etching the semiconductor substrate20to form recesses. Dielectric material then fills between the recesses to form the STI regions22.

The fin structures124and324may have channel dopings. The fin structures124may be doped with an n-type impurity such as phosphorous, while the fin structure324may be doped with a p-type impurity such as boron. The semiconductor substrate20includes a portion in PMOS device region10and a portion in NMOS device region30. The fin structures124and324are in the PMOS device region10and the NMOS device region30respectively.

Referring toFIG. 3, gate dielectric layer42and gate electrode layer44are deposited in both PMOS device region10and NMOS device region30and over the fin structures124and324. In some embodiments, the gate dielectric layer42is formed of a high-k dielectric material. The exemplary high-k materials may have k values larger than about 4.0, or even larger than about 7.0, and my include aluminium-containing dielectrics such as Al2O3, HfAlO, HfAlON, AlZrO, Hf-containing materials such as HfO2, HfSiOx, HfAlOx, HfZrSiOx, HfSiON, and/or other materials such as LaAlO3and ZrO2. The gate electrode layer44is formed on the gate dielectric layer42and may include metal.

Referring toFIG. 4, the gate electrode layer44and gate dielectric layer42are patterned to form gate stacks. The gate stack in the PMOS device region10includes the gate electrode144and the gate dielectrics142. The gate stack in the NMOS device region30includes the gate electrode344and the gate dielectric342. Each of the fin structures124and324thus has portions that are uncovered by the gate stacks. In some embodiments, a gate-last process is employed. In this case, a dummy gate layer is used to replace the gate electrode layer. Dummy gate layer is later removed after gate spacers are formed, and gate electrode the fills in the space left by the dummy gate layer.

Referring toFIG. 5, gate spacers146and346are formed. PMOS device region10and NMOS device region30are shown separately for the sake of clarity. Spacer layer is deposited on the gate electrodes144and344, uncovered fin structures124and324, and over the STI regions22. Spacer layer is then pattern to form gate spacers146and346around the gate stacks and leaving portions of fin structures124and324exposed again as shown inFIG. 5.

Referring toFIG. 6, first recesses350are formed. The exposed portions of the fin structure324are not covered by the gate dielectric342, gate electrode344and gate spacers346in NMOS device region30. The exposed portions of the fin structure324may be removed by, for example, a dry etch. The covered portions of the fin structure324are not removed. Slight consumption of covered portions of the fin structure324may occur during etching process as illustrated inFIG. 6. The spaces left by the removed portions of the fin structure324are referred to as first recesses350. First recesses350may have bottoms level with top surfaces25of the STI regions22. Alternatively, the bottoms of first recesses350may be lower than top surfaces25of the STI regions22as shown inFIG. 6. PMOS device region10is covered by a mask layer52, for example, photo resist. The exposed portions of fin structure124are not removed and remain in PMOS device region10due to the protection of the mask layer52.

FIG. 7illustrates a cross-sectional view of the structure shown inFIG. 6. The cross-sectional view of PMOS device region10is obtained in a vertical plane crossing line X-X inFIG. 6, while the cross-sectional view of NMOS device region30is obtained in a vertical plane crossing X′-X′ inFIG. 6. SubsequentFIGS. 8 and 9that illustrate the cross-sectional views of PMOS device region10and NMOS device region30are in a same plane.

Referring toFIG. 7, the first recesses350have bottoms lower than top surfaces25of the STI regions22. The covered portions of the fin structure324is slightly consumed, while gate dielectric352, gate electrode354, and gate spacers356remain on the remaining the fin structure324.

Next, as shown inFIG. 8, the PMOS device region10is covered, and first epitaxy structures362are epitaxially grown in the first recesses350. The term “epitaxy”, “epitaxial”, and “epitaxially grown” hereinafter referred to the growth on a crystalline substrate of a crystalline substance that mimics the orientation of the substrate, but the final product may not be crystalline. The first epitaxy structures362have a lattice constant greater than the lattice constant of the fin structure324. During the epitaxial process of forming the first epitaxy structures362, p-type dopants (impurities) such as germanium and boron may be doped with the proceeding epitaxial processes. The dopant concentration in terms of surface distribution may be between about 5%/cm3and 10%/cm3. In some embodiments, low temperature condition is applied during first epitaxy structures362formation. The temperature is lower than about 600° C. to allow the first epitaxy structures362to grow faster along <111> plane. Due to the selection of dopant, low temperature condition, and fine regulation of dopant concentration during epitaxy process, the first epitaxy structures362grow slower along <100> plane, and therefore elongated bar like first epitaxy structures362are formed. The first epitaxy structures362fill in the first recesses350and grow high in a direction that is away from the semiconductor substrate20. In some embodiments, the first epitaxy structure362may have slanting sidewalls that taper gradually toward top surface. The first epitaxy structures362have a width measured between two the STI regions22and a height measured from bottoms of first recesses350. The width is much smaller than the height to create slim bar like structures protruding over surfaces25of the STI regions22.

Referring toFIG. 9, epitaxy coats372are formed. Epitaxy coats372are epitaxially grown over the first epitaxy structures362. Epitaxy coats372have a lattice constant smaller than the lattice constant of the fin structure124. During the epitaxial process of forming the epitaxy coats372, n-type dopants (impurities) such as phosphorous and/or arsenic may be in-situ doped when epitaxial growth proceeds. Sidewalls and top surfaces of the first epitaxy structures362are blanked by epitaxy coats372. Epitaxy coats372conform to outline of first epitaxy structures362, resembling horseshoes crossing over first epitaxy structures362. Source and drain (referred to as source/drain hereinafter) regions380of NMOS device region30are then formed. Source/drain regions380are also alternatively referred to as source/drain stressors380and may have a lattice constant smaller than the lattice constant of the fin structure124. With the lattice constant of the source/drain regions380being smaller than that of the fin structure324, the source/drain regions380apply a tensile stress to the fin structure324, which forms the channel region of the resulting n-type FinFET device.

Referring toFIG. 15A, an enlarged view of portion A inFIG. 9is illustrated. The source/drain region380includes the first epitaxy structure362and the epitaxy coat372. The first epitaxy structure362has top portion364in which the epitaxy coat372permeates through to form a fringe portion376of the epitaxy coat372. The epitaxy coat372piles up on a top portion364of the first epitaxy structure362and adds a thickness to the first epitaxy structure362. This portion is referred to as a ridge portion374. Thickness TNrepresents entire thickness of the source/drain region380measured from the bottom of the first recess350. Thickness TNranges between about 45 and 55 nm. N1and N2represent lower portion and upper portion of source/drain region380respectively. Lower portion N1is majorly constituted of the first epitaxy structure362, and upper portion N2includes top portion364of the first epitaxy structure362, fringe portion376and ridge portion374of the epitaxy coat372. Lower portion N1has a thickness ranging between about 30-45 nm, and upper portion N2has a thickness greater than about 12 nm. In other words, the epitaxy coat372accounts for approximately one third (⅓) of thickness TNof source/drain region380.

Still referring toFIG. 15A, lower portion N1has a first dopant concentration, in which the first dopant has lattice constant greater than the fin structure324, between about 5%/cm3and 10%/cm3. Lower portion N1also has a second dopant concentration, in which the second dopant has lattice constant smaller than the fin structure324, of about 2×1020/cm3. Upper portion N2has the second dopant concentration between about 3×1021/cm3and 4×1021/cm3. The source/drain region380exhibits second dopant concentration gradient that gradually reduces from the ridge portion374to fringe portion376and further down to lower portion N1of the first epitaxy structure. The ridge portion374has the highest second dopant concentration, while lower portion N1is milder because first dopant dilutes second dopant concentration. First dopant and second dopant concentration at lower portion N1is finely controlled at a predetermined level, or electrical leakage may occur.

Referring back toFIG. 9, the source/drain regions380are constituted of different types of dopants. In some embodiments, one of the dopant may be p-type stressor and the other n-type stressor. P-type stressor allows the first epitaxy structures362to grow in a specific orientation, resulting in slim, narrow, bar-like first epitaxy structures362. Next, n-type stressor is used to form the epitaxy coat372and applies tensile stress to the fin structure324. N-type stressor follows the bar-like first epitaxy structures362and is less likely to overstretch toward the STI regions22. Source/drain regions380are not in a diamond shape and confined in the spaces left by the first recesses350.

Referring toFIG. 10, second recesses150are formed. After the epitaxial growth of source/drain regions380, the mask layer52is removed. The exposed portions of the fin structure124are not covered by gate dielectrics142, gate electrode144and gate spacers146in the PMOS device region10. The exposed portions of fin structure124may be removed by, for example, a dry etch. The covered portions of fin structure124are not removed. Slight consumption of covered portions of fin structure124may occur during etching process as illustrated inFIG. 10. The spaces left by the removed portions of fin structure124are referred to as second recesses150. Second recesses150may have bottoms level with top surfaces25of the STI regions22. Alternatively, the bottoms of second recesses150may be lower than top surfaces25of the STI regions22as shown inFIG. 10. NMOS device region30is covered by mask layer (not shown), for example, photo resist. The source/drain regions380are not removed and remain in PMOS device region10due to the protection of mask layer.

Due to shrinkage of cell dimension in ever compacting integrated circuit, densely arranged components imply limited spaces between each device. The slim, narrow, bar-like first epitaxy structures362ensures n-type stressor on NMOS device region30does not expand laterally to PMOS device region10. The first epitaxy structures362are scaffoldings for the subsequently formed the epitaxy coat372. The configuration of first epitaxy structures362prevents the epitaxy coat372from lateral development. When forming the second recesses150on PMOS device region10, the source/drain regions380on NMOS device region30are less likely to be damaged, for example, by etching consumption.

FIG. 11illustrates a cross-sectional view of the structure shown inFIG. 10. The cross-sectional view of PMOS device region10is obtained in a vertical plane crossing line X-X inFIG. 10, while the cross-sectional view of NMOS device region30is obtained in a vertical plane crossing X′-X′ inFIG. 6. SubsequentFIG. 12that illustrates the cross-sectional views of PMOS device region10and NMOS device region30are in a same plane.

Referring toFIG. 11, the first recesses350have bottoms lower than top surfaces25of The STI regions22. The covered portions of fin structure124is slightly consumed, while gate dielectric152, gate electrode154, and gate spacers156remain on the remaining fin structure124.

Next, as shown inFIG. 12, second epitaxy structures162are epitaxially grown in the second recesses150. The second epitaxy structures162have a lattice constant greater than the lattice constant of fin structure124. During the epitaxial process of forming the second epitaxy structures162, p-type dopants (impurities) such as germanium and boron may be doped with the proceeding epitaxial processes. The dopant concentration in terms of surface distribution may be between about 5%/cm3 and 10%/cm3. In some embodiments, low temperature condition is applied during the second epitaxy structures162formation. The temperature is lower than about 600° C. to allow the second epitaxy structures162to grow faster along <111> plane. Due to the selection of dopant, low temperature condition, and fine regulation of dopant concentration during epitaxy process, the second epitaxy structures162grow slower along <100> plane, and therefore elongated bar like second epitaxy structures162are formed. The second epitaxy structures162fill in the second recesses150and grow high in a direction that is away from the semiconductor substrate20. In some embodiments, the second epitaxy structure162may have slanting sidewalls that taper gradually toward top surface. The second epitaxy structures162have a width measured between two the STI regions22and a height measured from bottoms of second recesses150. The width is much smaller than the height to create slim bar like structures protruding over surfaces25of the STI regions22. Source/drain regions180of PMOS device region10are then formed. Source/drain regions180are also alternatively referred to as source/drain stressors regions180and may have a lattice constant greater than the lattice constant of fin structure124. With the lattice constant of source/drain regions180being greater than that of fin structure124, source/drain regions180apply a compressive stress to fin structure124, which forms the channel region of the resulting p-type FinFET device.

Referring toFIG. 13, the first epitaxy structures362and second epitaxy structures162may be made of same material that has lattice constant greater than fin structures124and324. The first epitaxy structures362and second epitaxy structures162have the characteristics of fast growing along <111> crystal orientation. Under low temperature condition (e.g., lower than 600° C.), the phenomenon is even more pronounced. Aspect ratio of the first epitaxy structures362and the second epitaxy structures162may be controlled in the proceeding of epitaxy growth by tuning dopant concentration and ratio of different dopants. For example, when germanium and boron are used as p-type stressor, the ratio between germanium and boron (Ge:B) may be adjusted so as to obtain desirable configuration of the first epitaxy structures362and second epitaxy structures162. As a result, the first epitaxy structure362and second epitaxy structure162are amorphous and have elongated bar-like shape when the first recesses350and second recesses150are filled in.

FIG. 14illustrates a cross-sectional view of the structure shown inFIG. 13. The cross-sectional view of PMOS device region10is obtained in a vertical plane crossing line Y-Y inFIG. 13, while the cross-sectional view of NMOS device region30is obtained in a vertical plane crossing Y′-Y′ inFIG. 13.

Referring toFIGS. 14A and 14B, cross-sectional views of the first epitaxy structures326and the second epitaxy structures126are close to rectangle with narrow width and stretching height. The first epitaxy structures362and second epitaxy structures protrude over top surfaces25of the STI regions22. Even with densely packed layout design, the patterning processes of PMOS device region10and NMOS device region30do not damage its neighbouring components. The second epitaxy structures162is on the PMOS device region10and not covered by the epitaxy coat372, while the first epitaxy structure362is on the NMOS device region30and covered by the epitaxy coat372.

FIG. 15Billustrates an enlarged view of region B inFIG. 14B. Referring toFIG. 15B, the source/drain region380includes the first epitaxy structure362contains p-type stressor that allows the first epitaxy structure362to grow into elongated bar-like shape. The first epitaxy structure362is used as the skeleton for the epitaxy coat372. The epitaxy coat372contains n-type stressor that has lattice constant smaller than channel region325. The epitaxy coat372grows conformally along contour of the first epitaxy structure362and therefore resembles a horseshoe clutching across the first epitaxy structure362. The epitaxy coat372has a ridge portion374sitting on top of the first epitaxy structure362. Due to epitaxial growing process, the epitaxy coat372permeates through into the top portion364of the first epitaxy structure362. The fringe portion376refers to a buffer area where concentrations of p-type and n-type stressor vary gradually. More specifically, source/drain region380exhibits a concentration gradient. In terms of n-type stressor, the concentration gradient gradually reduces from the ridge portion374to the first epitaxy structure362. The fringe portion364has an n-type stressor concentration lower than that of the ridge portion374while slightly higher than that of the first epitaxy structure362.

Source/drain region380is on NMOS device region30, and a material having lattice constant larger than the channel region325is used for scaffolding, and then the epitaxy coat372that contains a material having lattice constant smaller than the channel region325is used. The epitaxy coat372applies tensile stress to the channel region325. It is not uncommon of an n-type source/drain region having excess dimension especially in terms of lateral development. When n-type stressor is epitaxially grown on an existing structure (i.e., first epitaxy structure), excess lateral development is minimized because epitaxy coat follows contour of first epitaxy structure. As shown inFIG. 15B, the epitaxy coat372wraps around the first epitaxy structure362in a thin layer and permeates slightly into the first epitaxy structure362. Source/drain region380functions as n-type source/drain stressor and has p-type skeleton.

In an NMOS device region, using a first epitaxy structure having lattice constant larger than the channel region as scaffolding for the source/drain regions, and epitaxy coat blankets the first epitaxy structure to apply tensile stress to the channel region. Configuration of the source/drain regions is well controlled as elongated bar like structure to prevent excess lateral source/drain region development.

In some embodiments, a semiconductor device includes a semiconductor substrate, an n-type fin field effect transistor. The n-type fin field effect transistor includes a fin structure, a gate stack, and a source/drain region. The gate stack includes a gate dielectric and a gate electrode. The gate dielectric is disposed in between the fin structure and the gate electrode. The source/drain region includes an epitaxial structure and an epitaxy coat covering the epitaxial structure. The epitaxial structure is made of a material having a lattice constant larger than a channel region. The epitaxy coat is made of a material having a lattice constant lower than the channel region.

In some embodiments, a semiconductor device includes a semiconductor substrate, an n-type fin field effect transistor. The n-type fin field effect transistor includes a first fin structure, a gate stack, and a first source/drain region. The first gate stack includes a first gate dielectric and a first gate electrode. The first gate dielectric is disposed in between the first fin structure and the first gate electrode. The first source/drain region includes a first epitaxial structure and an epitaxy coat covering the first epitaxial structure. The first epitaxial structure includes a p-type stressor. The epitaxy coat includes an n-type stressor.

In some embodiments, a method of fabricating a semiconductor device includes forming a first fin structure and a second fin structure on a semiconductor substrate. A gate stack across the first fin structure and the second fin structure are formed. A portion of the first fin structure is removed to form a first recess. A first epitaxy structure is formed in the first recess. The first epitaxy structure includes a p-type stressor. An epitaxy coat is formed on the first epitaxy structure. The epitaxy coat includes an n-type stressor. A portion of the second fin structure is removed to form a second recess. A second epitaxy structure is formed in the second recess. The second epitaxy structure includes the p-type stressor.