METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device includes: forming a first type well in a substrate; and after forming the first type well in the substrate, forming a second type well in the substrate, where the second type well has a conductivity type different from that of the first type well. One of the first and second type wells is formed by sequentially performing multiple ion implantations that use different energies, and one of the ion implantations that uses a lowest energy among the ion implantations is performed first among the ion implantations.

BACKGROUND

The semiconductor integrated circuit (IC) industry has over the past decades experienced tremendous advancements and is still experiencing vigorous development. With the dramatic advances in IC design, it is a big challenge to reduce sub-fin leakage in a transistor.

DETAILED DESCRIPTION

FIG.1is a flow chart illustrating a method600for manufacturing a semiconductor device in accordance with some embodiments.FIGS.2to34are schematic sectional views of semiconductor structures700during various stages of the method600. The method600and the semiconductor structures700are collectively described below. However, additional steps can be provided before, after or during the method600, and some of the steps described herein may be replaced by other steps or be eliminated. Similarly, further additional features may be present in the semiconductor structures700, and/or features present may be replaced or eliminated in additional embodiments.

Referring toFIGS.1and2, a substrate900is provided with a pad oxide901formed thereon. In some embodiments, the substrate900may be a silicon substrate, and the pad oxide901may include silicon oxide. The method600begins at block601, where at least one p-type well702is formed in the substrate900.FIG.2only depicts one of the at least one p-type well702for simplicity. Block601may be implemented as described below. Firstly, a masking layer701is coated on the pad oxide901, and is patterned to form at least one opening. Secondly, multiple p-type ion implantations that use different energies are sequentially performed to implant p-type dopants into the substrate900through the at least one opening, so as to form the at least one p-type well702in the substrate900. The patterned masking layer701may be removed after the at least one p-type well702is formed. In some embodiments, the masking layer701may be a photoresist or a hard mask, and may have a multi-layer structure (e.g., a bi-layer structure or a tri-layer structure). In some embodiments, the p-type dopants may include boron, BF2, other suitable materials, or combinations thereof. One of the p-type ion implantations that uses a lowest energy among the p-type ion implantations would form a punch through stop layer in a sub-fin region of each of the at least one p-type well702, so as to suppress sub-fin leakage. The sub-fin region of the p-type well702is an uppermost region of the p-type well702with a thickness of about 50 nm.

Referring toFIGS.1and3, the method600then proceeds to block602, where at least one n-type well704is formed in the substrate900.FIG.3only depicts one of the at least one n-type well704for simplicity. Block602may be implemented as described below. Firstly, a masking layer703is coated on the pad oxide901, and is patterned to form at least one opening. Secondly, multiple n-type ion implantations that use different energies are sequentially performed to implant n-type dopants into the substrate900through the at least one opening, so as to form the at least one n-type well704in the substrate900. The patterned masking layer703may be removed after the at least one n-type well704is formed. In some embodiments, the masking layer703may be a photoresist or a hard mask, and may have a multi-layer structure (e.g., a bi-layer structure or a tri-layer structure). In some embodiments, the n-type dopants may include phosphorus, arsenic, indium, other suitable materials, or combinations thereof. One of the n-type ion implantations that uses a lowest energy among the n-type ion implantations would form a punch through stop layer in a sub-fin region of each of the at least one n-type well704, so as to suppress sub-fin leakage. The sub-fin region of the n-type well704is an uppermost region of the n-type well704with a thickness of about 50 nm.

In some embodiments, the n-type ion implantation that uses the lowest energy may be performed last in block602. In an example where a total number of the n-type ion implantations is three, the n-type ion implantations may be sequentially performed from the highest to the lowest energy as shown inFIGS.4,5and6. It should be noted that each n-type ion implantation may cause shrinkage of the patterned masking layer703, so the n-type ion implantation that uses the lowest energy may introduce more n-type dopants (or n-type impurities) within the sub-fin region of each p-type well702when it is performed last among the n-type ion implantations, as compared to when it is performed first among the n-type ion implantations. Similarly, in some embodiments, the p-type ion implantation that uses the lowest energy may be performed last in block601, and may introduce more p-type dopants (or p-type impurities) within the sub-fin region of each n-type well704when it is performed last among the p-type ion implantations, as compared to when it is performed first among the p-type ion implantations.

In some embodiments, the n-type ion implantation that uses the lowest energy may be performed first in block602. In the example where the total number of the n-type ion implantations is three, the n-type ion implantations may be sequentially performed from the lowest to the highest energy as shown inFIGS.7,8and9; alternatively, the n-type ion implantations may be sequentially performed in an order of the lowest, highest and medium energies as shown inFIGS.10,11and12. It should be noted that each n-type ion implantation may cause shrinkage of the patterned masking layer703, so the n-type ion implantation that uses the lowest energy may introduce less n-type dopants (or n-type impurities) within the sub-fin region of each p-type well702when it is performed first among the n-type ion implantations, as compared to when it is performed last among the n-type ion implantations. Similarly, in some embodiments, the p-type ion implantation that uses the lowest energy may be performed first in block601, and may introduce less p-type dopants (or p-type impurities) within the sub-fin region of each n-type well704when it is performed first among the p-type ion implantations, as compared to when it is performed last among the p-type ion implantations.

It should be noted that the n-type ion implantations may be sequentially performed in an order the same as or different from that of the p-type ion implantations. In addition, when the p-type ion implantation that uses the lowest energy is performed first among the p-type ion implantations and the n-type ion implantation that uses the lowest energy is performed first among the n-type ion implantations, in the sub-fin regions of any two adjacent p-type and n-type wells702,704and around a boundary between the two adjacent p-type and n-type wells702,704, a portion that is subjected to both p-type ion implantation and n-type ion implantation would be smaller.

In some embodiments, with respect to each of the p-type and n-type ion implantations, depending on a target dopant concentration profile of the corresponding p-type or n-type well702/704, the ion implantation may be performed along an axis normal to a top surface of the substrate900, or it may be a tilt implantation. The tilt implantation is performed at an angle with respect to the axis that is greater than 0 degrees, and that is smaller than or equal to 15 degrees.

In some embodiments, with respect to each of the p-type and n-type ion implantations, depending on the target dopant concentration profile of the corresponding p-type or n-type well702/704, the ion implantation may be performed without rotating the substrate900, or it may be a rotational implantation. The rotational implantation is performed as the substrate900is being rotated by angles that fall between 0 and 360 degrees.

In some embodiments, with respect to each of the p-type and n-type ion implantations, depending on the target dopant concentration profile of the corresponding p-type or n-type well702/704, the ion implantation may be performed at a temperature that falls within a range of from −60° C. to 450° C. (i.e., the substrate900is adjusted to the temperature).

In an example where both of a total number of the p-type ion implantations and the total number of the n-type ion implantations are three, the p-type ion implantation that uses the lowest energy may be performed such that a concentration of the p-type dopants introduced into the substrate900by such ion implantation falls within a range of from 1×1019cm−3to 5×1019cm−3, the p-type ion implantation that uses the medium energy may be performed such that a concentration of the p-type dopants introduced into the substrate900by such ion implantation falls within a range of from 5×1018cm−3to 1×1019cm−3, the p-type ion implantation that uses the highest energy may be performed such that a concentration of the p-type dopants introduced into the substrate900by such ion implantation falls within a range of from 1×1018cm−3to 5×1018cm−3, the n-type ion implantation that uses the lowest energy may be performed such that a concentration of the n-type dopants introduced into the substrate900by such ion implantation falls within a range of from 1×1019cm−3to 5×1019cm−3, the n-type ion implantation that uses the medium energy may be performed such that a concentration of the n-type dopants introduced into the substrate900by such ion implantation falls within a range of from 5×1018cm−3to 1×1019cm−3, and the n-type ion implantation that uses the highest energy may be performed such that a concentration of the n-type dopants introduced into the substrate900by such ion implantation falls within a range of from 1×1018cm−3to 5×1018cm−3.

In the example where both of the total number of the p-type ion implantations and the total number of the n-type ion implantations are three, the p-type ion implantations may be performed to implant boron into the substrate900, with the lowest energy falling within a range of from 3 keV to 7 keV, the medium energy falling within a range of from 10 keV to 20 keV, and the highest energy falling within a range of from 20 keV to 50 keV; and the n-type ion implantations may be performed to implant phosphorus into the substrate900, with the lowest energy falling within a range of from 7 keV to 13 keV, the medium energy falling within a range of from 25 keV to 55 keV, and the highest energy falling within a range of from 55 keV to 120 keV. Alternatively, the p-type ion implantation that uses the lowest energy may be performed to implant BF2into the substrate900, with the lowest energy falling within a range of from 10 keV to 20 keV. Alternatively, the n-type ion implantation that uses the lowest energy may be performed to implant arsenic into the substrate900, with the lowest energy falling within a range of from 10 keV to 20 keV.

The method600then proceeds to block603, where the p-type and n-type wells702,704are annealed so as to repair damages caused by ion implantation and to activate the p-type and n-type dopants that were implanted.

In some embodiments, the substrate900may be heated at least when the p-type ion implantation that uses the lowest energy and the n-type ion implantation that uses the lowest energy are being performed, so less point defects would be created in the p-type and n-type wells702,704, and less lateral diffusion of the p-type and n-type dopants from the sub-fin regions of the p-type and n-type wells702,704into the sub-fin regions of the n-type and p-type wells704,702would occur when the p-type and n-type wells702,704are annealed.

The method600then proceeds to block604, where the pad oxide901is removed, and a plurality of transistors (not shown) are formed on the p-type and n-type wells702,704.

FIGS.13to22are schematic sectional views of semiconductor structures700during various stages of a method for forming an n-type fin field-effect transistor (FinFET) on a p-type well702in accordance with some embodiments. The exemplary scenario depicted in these figures is that one p-type well702is formed between two n-type wells704.FIG.14is a schematic section view taken along line A-A ofFIG.13;FIGS.15,17,19and21are views similar toFIG.13; andFIGS.16,18,20and22are views similar toFIG.14.

At first, as shown inFIGS.13and14, a semiconductor layer705is formed on the p-type well702and the n-type wells704. In some embodiments, the semiconductor layer705may be epitaxially formed using, for example, low pressure chemical vapor deposition (LPCVD), other suitable techniques, or combinations thereof. In some embodiments, the semiconductor layer705may include group IV semiconductor, group III-V semiconductor, group II-VI semiconductor, other suitable materials, or combinations thereof. For example, the semiconductor layer705may be a silicon layer, but the disclosure is not limited in this respect.

Then, as shown inFIGS.13,14,15and16, the semiconductor layer705is patterned to form a fin structure705′ on the p-type well702, a shallow trench isolation (STI) layer706is formed on the p-type well702and the n-type wells704to cover a lower portion of the fin structure705′, and a dummy gate layer707is formed on the fin structure705′ and the STI layer706. In some embodiments, the semiconductor layer705may be patterned using a photolithography process and an etching process. The photolithography process may include, for example, but not limited to, coating the semiconductor layer705with a photoresist, soft-baking, exposing the photoresist through a photomask, post-exposure baking, developing the photoresist, and hard-baking, so as to form a patterned photoresist. The etching process may be implemented by etching the semiconductor layer705through the patterned photoresist using, for example, dry etching, wet etching, reactive ion etching (RIE), atomic layer etching (ALE), other suitable techniques, or combinations thereof. The patterned photoresist may be removed after the etching process. In some embodiments, each of the STI layer706and the dummy gate layer707may be formed using, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), other suitable techniques, or combinations thereof. In some embodiments, the STI layer706may include, for example, oxide (e.g., silicon oxide), nitride, other suitable materials, or combinations thereof. In some embodiments, the dummy gate layer707may include, for example, polysilicon, other suitable materials, or combinations thereof.

Next, as shown inFIGS.15,16,17and18, the dummy gate layer707is patterned to form a dummy gate707′, first spacers708are respectively formed on sidewalls of the dummy gate707′, and second spacers709are respectively formed on the first spacers708. In some embodiments, the dummy gate layer707may be patterned using a photolithography process and an etching process similar to those used to pattern the semiconductor layer705(seeFIGS.13and14). In some embodiments, the first and second spacers708,709may be formed by conformally and sequentially depositing two dielectric layers for forming the first and second spacers708,709using, for example, CVD, ALD, other suitable techniques, or combinations thereof, followed by one or more etching processes to selectively leave the first and second spacers708,709remaining on the sidewalls of the dummy gate707′. In some embodiments, the first and second spacers708,709may include, for example, B(C)N-based materials, SiOxCyNz-based materials, silicon nitride, other suitable materials, or combinations thereof.

Then, as shown inFIGS.19and20, source/drain electrodes710are formed in the fin structure705′ at opposite sides of the dummy gate707′. In some embodiments, the fin structure705′ may be etched using, for example, dry etching, wet etching, RIE, ALE, other suitable techniques, or combinations thereof, so as to form recesses in the fin structure705′ at the opposite sides of the dummy gate707′; and the source/drain electrodes710may be epitaxially formed in the recesses using, for example, LPCVD, other suitable techniques, or combinations thereof. In some embodiments, the source/drain electrodes710may include, for example, silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, other suitable materials, or combinations thereof.

A process for forming the structure shown inFIGS.21and22may include (i) conformally depositing a dielectric layer for forming an interlayer dielectric (ILD) layer713over the structure shown inFIG.20, (ii) performing a planarization process to remove an excess of the dielectric layer to expose the dummy gate707′ to thereby form the ILD layer713, (iii) removing the dummy gate707′ using, for example, dry etching, wet etching, RIE, ALE, other suitable techniques, or combinations thereof to form a trench between the first spacers708, (iv) conformally depositing materials for forming a gate dielectric711and a gate electrode712over the ILD layer and inner surfaces of the trench using, for example, PVD, CVD, ALD, other suitable techniques, or combinations thereof, and (v) performing planarization to remove an excess of the materials to obtain the gate dielectric711and the gate electrode712. In some embodiments, the gate dielectric711may include, for example, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3(BST), Al2O3, Si3N4, silicon oxynitrides (SiON), other suitable materials, or combinations thereof. In some embodiments, the gate electrode712may include, for example, Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, other suitable materials, or combinations thereof.

A method for forming a p-type FinFET on an n-type well704in accordance with some embodiments is similar to the method for forming an n-type FinFET on a p-type well702, but differs from the method for forming an n-type FinFET on a p-type well702in that the source/drain electrodes710may include, for example, silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, other suitable materials, or combinations thereof.

FIGS.23to34are schematic sectional views of semiconductor structures700during various stages of a method for forming an n-type nanosheet FET on a p-type well702in accordance with some embodiments. The exemplary scenario depicted in these figures is that the p-type well702is formed between two n-type wells704.FIG.24is taken along line B-B inFIG.23;FIGS.25,27,29,31and33are views similar toFIG.23; andFIGS.26,28,30,32and34are views similar toFIG.24.

At first, as shown inFIGS.23and24, a semiconductor layer stack721and a dummy gate layer724are sequentially formed on the p-type well702and the n-type wells704. The semiconductor layer stack721includes first semiconductor layers722and second semiconductor layers723stacked in an alternating manner. The first semiconductor layers722include a semiconductor material different from that of the second semiconductor layers723. In some embodiments, the first semiconductor layers722may include group IV semiconductor, group III-V semiconductor, group II-VI semiconductor, other suitable materials, or combinations thereof. In some embodiments, the second semiconductor layers723may include group IV semiconductor, group III-V semiconductor, group II-VI semiconductor, other suitable materials, or combinations thereof. For example, the first semiconductor layers722may be silicon layers, and the second semiconductor layers723may be SiGe layers, but the disclosure is not limited in this respect. In some embodiments, the dummy gate layer724may include, for example, polysilicon, other suitable materials, or combinations thereof. In some embodiments, each of the first and second semiconductor layers722,723and the dummy gate layer724may be epitaxially formed using, for example, LPCVD, other suitable techniques, or combinations thereof.

Then, as shown inFIGS.23,24,25and26, the dummy gate layer724and the semiconductor layer stack721are patterned to form a dummy gate strip724′ and a semiconductor strip stack721′ on the p-type well702, and an STI layer725is formed on the p-type well702and the n-type wells704to cover the semiconductor strip stack721′. The semiconductor strip stack721′ includes first semiconductor strips722′ and second semiconductor strips723′. In some embodiments, the dummy gate layer724and the semiconductor layer stack721may be patterned using a photolithography process and an etching process. The photolithography process may include, for example, but not limited to, coating the dummy gate layer724with a photoresist, soft-baking, exposing the photoresist through a photomask, post-exposure baking, developing the photoresist, and hard-baking, so as to form a patterned photoresist. The etching process may be implemented by etching the dummy gate layer724and the semiconductor layer stack721through the patterned photoresist using, for example, dry etching, wet etching, RIE, ALE, other suitable techniques, or combinations thereof. The patterned photoresist may be removed after the etching process. In some embodiments, the STI layer725may be formed using, for example, CVD, PECVD, PVD, ALD, other suitable techniques, or combinations thereof. In some embodiments, the STI layer725may include, for example, oxide (e.g., silicon oxide), nitride, other suitable materials, or combinations thereof.

Next, as shown inFIGS.25,26,27and28, the dummy gate strip724′ is patterned to form a dummy gate724″, and first spacers725are formed on sidewalls of the dummy gate724″. In some embodiments, the dummy gate strip724′ may be patterned using a photolithography process and an etching process similar to those used to pattern the dummy gate layer724and the semiconductor layer stack721(seeFIGS.22and23). In some embodiments, the first spacers725may be formed by conformally depositing a dielectric layer for forming the first spacers725using, for example, CVD, ALD, other suitable techniques, or combinations thereof, followed by one or more etching processes to selectively leave the first spacers725remaining on the sidewalls of the dummy gate724″. In some embodiments, the first spacers725may include, for example, B(C)N-based materials, SiOxCyNz-based materials, silicon nitride, other suitable materials, or combinations thereof.

Then, as shown inFIGS.27,28,29and30, the semiconductor strip stack721′ is patterned to form a semiconductor feature721″ that includes first semiconductor elements722″ and second semiconductor elements723″, the second semiconductor elements723″ are etched to form recesses at side portions thereof, and second spacers (i.e., inner spacers)726are formed to fill the recesses. In some embodiments, the semiconductor strip stack721′ may be patterned using a photolithography process and an etching process similar to those used to pattern the dummy gate layer724and the semiconductor layer stack721(seeFIGS.22and23). In some embodiments, the second semiconductor elements723″ may be etched using, for example, dry etching, wet etching, RIE, ALE, other suitable techniques, or combinations thereof. In some embodiments, the second spacers726may include B(C)N-based materials, SiOxCyNz-based materials, silicon nitride, other suitable materials, or combinations thereof.

Next, as shown inFIGS.31and32, source/drain electrodes727are formed at opposite sides of the semiconductor feature721″. In some embodiments, the source/drain electrodes727may be epitaxially formed using, for example, LPCVD, other suitable techniques, or combinations thereof. In some embodiments, the source/drain electrodes727may include, for example, silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, other suitable materials, or combinations thereof.

At last, as shown inFIGS.31,32,33and34, the second semiconductor elements723″ and the dummy gate724″ are removed, a gate dielectric728is formed on the first semiconductor elements722″ thus exposed, and a gate electrode729is formed to surround the first semiconductor elements722″ that have been covered by the gate dielectric728. In some embodiments, the second semiconductor elements723″ and the dummy gate724″ may be removed using, for example, drying etching, wet etching, RIE, ALE, other suitable techniques, or combinations thereof. In some embodiments, each of the gate dielectric728and the gate electrode729may be formed using, for example, PVD, CVD, ALD, other suitable techniques, or combinations thereof. In some embodiments, the gate dielectric728may include, for example, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3(BST), Al2O3, Si3N4, silicon oxynitrides (SiON), other suitable materials, or combinations thereof. In some embodiments, the gate electrode729may include, for example, Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, other suitable materials, or combinations thereof.

A method for forming a p-type nanosheet FET on an n-type well704in accordance with some embodiments is similar to the method for forming an n-type nanosheet FET on a p-type well702, but differs from the method for forming an n-type nanosheet FET on a p-type well702in that the source/drain electrodes727may include, for example, silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, other suitable materials, or combinations thereof.

Referring toFIGS.3,35and36, each ofFIGS.35and36is a plot illustrating n-type dopant concentration versus depth characteristic of the semiconductor structure700ofFIG.3in a first condition and a second condition. The characteristic inFIG.35is taken along a boundary between two adjacent p-type and n-type wells702,704, beginning from a top surface of the two adjacent p-type and n-type wells702,704downward. The characteristic inFIG.36is taken along a line that is parallel to the boundary between the two adjacent p-type and n-type wells702,704and that passes through the most concave part of one of side walls of the masking layer703(in practice, the side walls of the masking layer703may be concave), beginning from the top surface of the two adjacent p-type and n-type wells702,704downward, wherein said one of the side walls corresponds in position to the boundary between the two adjacent p-type and n-type wells702,704. In each of the first and second conditions, six n-type ion implantations are performed. In the first condition, at first, the n-type ion implantation that uses the energy of 120 keV and an ion dose of 4×1013cm−2is performed; then, the n-type ion implantation that uses the energy of 40 keV and the ion dose of 7×1013cm−2is performed; next, the n-type ion implantation that uses the energy of 52 keV and the ion dose of 8×1013cm−2is performed; then, the n-type ion implantation that uses the energy of 35 keV and the ion dose of 1×1013cm−2is performed; next, the n-type ion implantation that uses the energy of 25 keV and the ion dose of 1×1013cm−2is performed; and at last, the n-type ion implantation that uses the energy of 10 keV and the ion dose of 8×1013cm−2is performed. In other words, the n-type ion implantation that uses the lowest energy is performed last among the six n-type ion implantations. The total shrinkage of the masking layer703after the first to fifth n-type ion implantations are performed are 2.74 nm, 4.54 nm, 8.32 nm, 8.32 nm and 8.32 nm, respectively. In the second condition, at first, the n-type ion implantation that uses the energy of 10 keV and the ion dose of 8×1013cm−2is performed; then, the n-type ion implantation that uses the energy of 25 keV and the ion dose of 1×1013cm−2is performed; next, the n-type ion implantation that uses the energy of 35 keV and the ion dose of 1×1013cm−2is performed; then, the n-type ion implantation that uses the energy of 52 keV and the ion dose of 8×1013cm−2is performed; next, the n-type ion implantation that uses the energy of 40 keV and the ion dose of 7×1013cm−2is performed; and at last, the n-type ion implantation that uses the energy of 120 keV and the ion dose of 4×1013cm−2is performed. In other words, the n-type ion implantation that uses the lowest energy is performed first among the six n-type ion implantations. The total shrinkage of the masking layer703after the first to fifth n-type ion implantations are performed are 1.61 nm, 2.25 nm, 2.92 nm, 6.99 nm and 8.3 nm, respectively. It can be reasonably determined fromFIGS.35and36that the p-type well702is less n-type doped in the second condition than in the first condition. Therefore, the sub-fin leakage in the n-type transistors formed on the p-type well702is lower in the second condition than in the first condition. In addition, the n-type dopants are distributed in a shallower portion of the p-type well702in the second condition than in the first condition. Therefore, a resistance of the p-type well702is lower in the second condition than in the first condition. Similarly, the sub-fin leakage in the p-type transistors formed on the n-type well704is lower in a third condition where the p-type ion implantation that uses the lowest energy is performed first among all p-type ion implantations than in a fourth condition where the p-type ion implantation that uses the lowest energy is performed last among all p-type ion implantations; and a resistance of the n-type well704is lower in the third condition than in the fourth condition.

In some embodiments, by performing the p-type ion implantation that uses the lowest energy first among all p-type ion implantations, and by performing the n-type ion implantation that uses the lowest energy first among all n-type ion implantations, in the sub-fin regions of any two adjacent p-type and n-type wells702,704and around the boundary between the two adjacent p-type and n-type wells702,704, a portion that is subjected to both p-type ion implantation and n-type ion implantation would be smaller, as compared to when the lowest energy ion implantations are performed last, so sub-fin leakage in the transistors formed on the p-type and n-type wells702,704can be effectively reduced. In addition, in this manner, the n-type dopants are distributed in a shallower portion of the p-type well702, and the p-type dopants are distributed in a shallower portion of the n-type well704, as compared to when the lowest energy ion implantations are performed last, so the resistance of the p-type well702and the resistance of the n-type well704can be relatively low.

In some embodiments, by heating the substrate900while performing the p-type ion implantation that uses the lowest energy, and by heating the substrate900while performing the n-type ion implantation that uses the lowest energy, less lateral diffusion of the p-type and n-type dopants from the sub-fin regions of the p-type and n-type wells702,704into the sub-fin regions of the n-type and p-type wells704,702would occur when annealing the p-type and n-type wells702,704, so sub-fin leakage in the transistors formed on the p-type and n-type wells702,704can be further reduced.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming a first type well in a substrate; and after forming the first type well in the substrate, forming a second type well in the substrate, the second type well having a conductivity type different from that of the first type well. One of the first and second type wells is formed by sequentially performing multiple first ion implantations that use different energies, and one of the first ion implantations that uses a lowest energy among the first ion implantations is performed first among the first ion implantations.

In accordance with some embodiments of the present disclosure, the other one of the first and second type wells is formed by sequentially performing multiple second ion implantations that use different energies, and one of the second ion implantations that uses a lowest energy among the second ion implantations is performed first among the second ion implantations.

In accordance with some embodiments of the present disclosure, the first ion implantation that uses the lowest energy is performed to implant boron into the substrate, and the lowest energy falls within a range of from 3 keV to 7 keV.

In accordance with some embodiments of the present disclosure, the first ion implantation that uses the lowest energy is performed to implant BF2into the substrate, and the lowest energy falls within a range of from 10 keV to 20 keV.

In accordance with some embodiments of the present disclosure, the first ion implantation that uses the lowest energy is performed to implant phosphorus into the substrate, and the lowest energy falls within a range of from 7 keV to 13 keV.

In accordance with some embodiments of the present disclosure, the first ion implantation that uses the lowest energy is performed to implant arsenic into the substrate, and the lowest energy falls within a range of from 10 keV to 20 keV.

In accordance with some embodiments of the present disclosure, the first ion implantation that uses the lowest energy is performed to implant dopants into the substrate such that a concentration of the dopants implanted into the substrate by said first ion implantation falls within a range of from 1×1019cm−3to 5×1019cm−3.

In accordance with some embodiments of the present disclosure, each of the first ion implantations is a tilt implantation, and is performed at an angle that is greater than 0 degrees and that is smaller than or equal to 15 degrees.

In accordance with some embodiments of the present disclosure, each of the first ion implantations is a rotational implantation, and is performed as the substrate is being rotated by angles that fall between 0 and 360 degrees.

In accordance with some embodiments of the present disclosure, each of the first ion implantations is performed at a temperature that falls within a range of from −60° C. to 450° C.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming a well in a substrate by sequentially performing multiple ion implantations that use different energies, where one of the ion implantations that uses a lowest energy among the ion implantations is performed first among the ion implantations; and forming a transistor on the well.

In accordance with some embodiments of the present disclosure, the ion implantation that uses the lowest energy is performed to implant dopants into the substrate such that a concentration of the dopants implanted into the substrate by said ion implantation falls within a range of from 1×1019cm−3to 5×1019cm−3.

In accordance with some embodiments of the present disclosure, each of the ion implantations is a tilt implantation, and is performed at an angle that is greater than 0 degrees and that is smaller than or equal to 15 degrees.

In accordance with some embodiments of the present disclosure, each of the ion implantations is a rotational implantation, and is performed as the substrate is being rotated by angles that fall between 0 and 360 degrees.

In accordance with some embodiments of the present disclosure, each of the ion implantations is performed at a temperature that falls within a range of from −60° C. to 450° C.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming a well in a substrate by sequentially performing multiple ion implantations that use different energies, where one of the ion implantations that uses a lowest energy among the ion implantations is performed first among the ion implantations while the substrate is being heated; and annealing the well.

In accordance with some embodiments of the present disclosure, the ion implantation that uses the lowest energy is performed to implant boron into the substrate, and the lowest energy falls within a range of from 3 keV to 7 keV.

In accordance with some embodiments of the present disclosure, the ion implantation that uses the lowest energy is performed to implant BF2into the substrate, and the lowest energy falls within a range of from 10 keV to 20 keV.

In accordance with some embodiments of the present disclosure, the ion implantation that uses the lowest energy is performed to implant phosphorus into the substrate, and the lowest energy falls within a range of from 7 keV to 13 keV.

In accordance with some embodiments of the present disclosure, the ion implantation that uses the lowest energy is performed to implant arsenic into the substrate, and the lowest energy falls within a range of from 10 keV to 20 keV.