LATENCY REDUCTION FOR TRANSITIONS BETWEEN ACTIVE STATE AND SLEEP STATE OF AN INTEGRATED CIRCUIT

An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes an integrated circuit with a security processor. The security processor determines the integrated circuit transitions to an active state from a sleep state that is not intended to maintain configuration information to return to the active state without restarting an operating system. In the sleep state, multiple components of the integrated circuit have a power supply reference level turned off, which provides low power consumption for the integrated circuit. The security processor performs the bootup operation using information stored in persistent on-chip memory. By not using information stored in off-chip memory, the security processor reduces the latency of the transition. The persistent on-chip memory utilizes synchronous random-access memory that receives a standby power supply reference level that continually supplies a voltage magnitude by not being turned off.

BACKGROUND

Description of the Relevant Art

Generally speaking, a variety of semiconductor chips include at least one integrated circuit, such as a processing unit, coupled to a memory. The processing unit processes instructions (or commands) by fetching instructions and data, decoding instructions, executing instructions, and storing results. The processing unit sends memory access requests to the memory for fetching instructions, fetching data, and storing results of computations. Examples of the processing unit are a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a multimedia engine, and a processing unit with a highly parallel microarchitecture such as a graphics processing unit (GPU) and a digital signal processor (DSP). In some designs, the processing unit and the memory are on a same die such as a system-on-a-chip (SOC), whereas, in other designs, the processing unit and the memory are on different dies within a same package such as a multi-chip-module (MCM) or in a system in a package (SiP).

A variety of computing devices use the above examples of semiconductor chips with one or more integrated circuits. Examples of these computing devices are a desktop computer, a laptop computer, a server computer, a tablet computer, a smartphone, a gaming device, a smartwatch, and so on. As power consumption increases, more costly cooling systems such as larger fans and heat sinks are utilized to remove excess heat and prevent failure of the integrated circuit. However, cooling systems increase system costs. The power dissipation constraint of the integrated circuit is not only an issue for portable computers and mobile communication devices, but also for high-performance desktop computers and server computers. Power management circuitry assigns operating parameters to different partitions of an integrated circuit. The operating parameters include at least an operating power supply voltage and an operating clock frequency.

During a bootup operation prior to executing applications, several steps are performed such as verifying available hardware resources are functioning, loading a preferred operating system, and initializing one or more integrated circuits of the semiconductor chip. These steps follow an algorithm with instructions organized in small programs distributed across on-chip memory and within partitions of disk memory. Although a semiconductor chip can have no computational tasks to perform during a particular time period, the power management circuitry is unable to assign a sleep state, or other deep low-power state, to the semiconductor chip due to one or more components, such as particular one or more integrated circuits, consuming time to reinitialize when the sleep state ends. To avoid the duration of time for reinitializing these one or more components of the semiconductor chip, the power management circuitry limits the assigned low-power state.

In view of the above, methods and systems for efficiently managing power consumption of multiple components of an integrated circuit are desired.

While the invention is susceptible to various modifications and alternative forms,

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, one having ordinary skill in the art should recognize that the invention might be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention. Further, it will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements.

Apparatuses and methods efficiently managing power consumption of multiple components of an integrated circuit are contemplated. In various implementations, a computing system includes an integrated circuit with a security processor. The security processor determines a condition is satisfied that includes initializing at least a given client of multiple clients of the integrated circuit. Examples of the condition are a cold bootup operation, a warm bootup operation, and a resume operation. The resume operation occurs when the security processor determines the integrated circuit transitions to an active state from a sleep state or a suspend state that is typically not intended to maintain configuration information for returning to the active state without aid from the operating system. When the integrated circuit transitions to the sleep state or suspend state, in some implementations, the operating system stores its context information in one or more of system memory (typically implemented with DRAM) and main memory (typically implemented with disk memory). In an implementation, the security processor stores boot firmware and at least a subset of configuration information of at least the given client in persistent on-chip memory. Following, the multiple components of the integrated circuit have a power supply reference level turned off, which provides low power consumption for the integrated circuit while in the suspend state.

When transitioning from the suspend state to the active state, if the security processor checks the persistent on-chip memory to determine whether a valid copy of boot firmware and at least a subset of configuration information of at least the given client is stored in the persistent on-chip memory. If so, then the security processor performs initialization steps during the resume time of at least the given client using the copy of this information. The security processor performs these initialization steps independent of interacting with one or more of the operating system and one or more drivers corresponding to one or more clients. In some implementations, the persistent on-chip memory has a limited size due to a limited amount of on-die area available for the persistent on-chip memory. In such implementations, the security processor also retrieves configuration information of at least the given client from the system memory (typically implemented with DRAM). By initializing at least the given client of multiple clients independent of interacting with one or more of the operating system and one or more drivers corresponding to one or more clients, the security processor reduces the resume time, which is the latency of the transition from the suspend state (or sleep state) to the active state. The security processor also ensures the multiple clients are ready for access by the operating system as soon as possible without the operating system initializing the clients. In implementations that have the security processor access only the persistent on-chip memory when initializing at least the given client, the security processor further reduces the resume time.

In an implementation, the persistent on-chip memory utilizes one of a variety of types of on-chip synchronous random access memory (SRAM) that receives a standby power supply reference level that is not turned off. The standby power supply reference level is directly connected to a power plane that provides the standby power supply reference level from a power supply unit. There are no power switches used for connecting and disconnecting the standby power supply reference level. The standby power supply reference level continually supplies a voltage magnitude to the persistent on-chip memory. Therefore, the persistent on-chip memory continually stores at least a subset of boot firmware and a subset of configuration information even during the sleep state. In another implementation, the standby power supply reference level is turned off after a threshold amount of time has elapsed. A programmable configuration register stores a value indicating the threshold amount of time. The power controller146uses this value to determine whether to turn off the standby power supply reference level. Further details of these techniques to reduce the resume time of the integrated circuit for further power consumption reduction are provided in the following description ofFIGS.1-7.

Referring toFIG.1, a generalized block diagram is shown of a computing system100that efficiently manages power consumption of multiple components of an integrated circuit. An integrated circuit110includes at least a security processor120, persistent on-chip memory130, clients140, and a separate cache memory subsystem142. The integrated circuit110is connected to off-chip memory150. The off-chip memory150includes at least dynamic random-access memory (DRAM)160and disk memory170. The disk memory170includes one or more of hard disk drives (HDDs) and solid-state disks (SSDs). Clock sources, such as phase lock loops (PLLs), an interrupt controller, a communication fabric, power controllers, memory controllers, interfaces for input/output (I/O) devices, one or more temperature sensors and current sensors, and so forth are not shown in the computing system100for ease of illustration. It is also noted that the number of components of the computing system100and the number of subcomponents for those shown inFIG.1can vary from implementation to implementation. There can be more or fewer of each component/subcomponent than the number shown for the computing system100.

In various implementations, the components of the integrated circuit110are on a same die such as a system-on-a-chip (SOC). In other implementations, the components are individual dies in a system-in-package (SiP) or a multi-chip module (MCM). A variety of computing devices use the integrated circuit110such as a desktop computer, a laptop computer, a server computer, a tablet computer, a smartphone, a gaming device, a smartwatch, and so on. The clients140include a variety of types of circuits such as a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit

(GPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a multimedia engine, and so forth. Each of the clients140is capable of processing tasks of a variety of workloads. Additionally, each of the clients140is capable of generating and servicing one or more of a variety of requests such as memory access read and write requests and cache snoop requests.

The cache memory subsystem142includes one or more levels of a hierarchical memory subsystem using a slower type of memory than registers, but a faster type of memory than the DRAM160and the disk memory170of the off-chip memory150. In an implementation, one or more levels of the cache memory subsystem142utilizes one of a variety of types of on-chip synchronous RAM (SRAM). The cache memory subsystem142stores a copy of a subset of the data stored in the off-chip memory150, and reduces latencies of memory requests generated by the clients140, the security processor120, and any other types of circuitry within the integrated circuit110.

Compared to memory bit cells, such as 6T (six transistor) bit cells, used in the on-chip SRAM, the DRAM160that implements the system memory of computing system100reaches higher densities. Unlike HDDs and flash memory, the DRAM160is volatile memory, rather than non-volatile memory. The DRAM160loses its data relatively quickly when a power supply is removed. The disk memory170includes one or more of hard disk drives (HDDs) and solid-state disks (SSDs). The read only memory (ROM)180utilizes one of a variety of types of ROM for storing either data that remains unmodified or data that is modified during particular events rather than as part of typical processing of tasks of a workload. In an implementation, the ROM180is one of a variety of non-volatile memories. In an implementation, the ROM180cannot be electronically modified after the manufacture of the memory device used to implement the ROM180. In other implementations, the ROM180utilizes one of erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory that can be erased and re-programmed. The ROM180stores instructions of software that is rarely changed such as one of a variety of types of firmware. For example, the ROM180stores boot firmware182.

In some implementations, the security processor120includes the circuitry of a

processor core of a multi-core processor. In other implementations, the security processor120includes the circuitry of a stand-alone (not a core of multiple cores), dedicated unit or processor or other type of circuit. In an implementation, the persistent on-chip memory130utilizes one of a variety of types of on-chip synchronous RAM (SRAM). Although the persistent on-chip memory130uses SRAM, the persistent on-chip memory130is not used as part of the cache memory subsystem142. In various implementations, the persistent on-chip memory130stores a subset of information stored in one or more of the ROM180and the security processor120. For example, the persistent on-chip memory130stores the boot firmware and configuration information132that is a subset of boot firmware182and any configuration information stored in one or more of the ROM180and the security processor120.

Being non-volatile, the persistent on-chip memory130retains stored data regardless of whether the integrated circuit110is powered on or powered off such a being disconnected from the power supply reference level192. To implement the persistent on-chip memory130as non-volatile memory while also using one of a variety of types of SRAM, the persistent on-chip memory130receives the standby power supply reference level194that is not turned off by the power supply unit145or the power controller146. In an implementation, the other circuitry of the integrated circuit110, such as at least the security processor120, the clients140, and the cache memory subsystem142, receive the power supply reference level192. The power controller146generates the power supply reference level192, which is based on the power supply reference level190received from the power supply unit145. It is possible for the power controller146to turn off the power supply reference level192.

In various implementations, the persistent on-chip memory130uses a pair of voltage planes, and the pair includes the standby power supply reference level194as a first power plane and a standby ground reference level as a second power plane. Each of these power planes is separate from power planes used by other circuitry of the integrated circuit110. In other implementations, only one ground reference level is used, rather than two or more ground reference levels, by the integrated circuit110. In yet other implementations, a virtual ground reference level is used within the integrated circuit110, and this virtual ground reference level is connected to a physical ground reference level through a sleeper gate such as a field effect transistor. In such an implementation, the persistent on-chip memory130receives the physical ground reference level, whereas, the other circuitry of the integrated circuit110receives the virtual ground reference level.

In various implementations, the power supply reference level192is connected to a

power plane that provides the power supply reference level190from the power supply unit145through power switches which allows the power supply reference level192to be removed from supplying any voltage magnitude to the other circuitry of the integrated circuit110. The other circuitry includes at least the security processor120, the clients140, and the cache memory subsystem142. Conversely, the standby power supply reference level194is directly connected to a power plane that provides the standby power supply reference level194from the power supply unit145. The standby power supply reference level194continually supplies a voltage magnitude to the persistent on-chip memory130.

Although a single power supply reference level192is shown, in other implementations, any number of power supply reference levels are generated by the voltage regulator147for use by the other circuitry of the integrated circuit110such as at least the security processor120, the clients140, and the cache memory subsystem142. Similarly, although a single power supply reference level190is shown being sent by the power supply unit145, in other implementation, another number of power supply reference levels are sent from the power supply unit145. In various implementations, the circuitry148of the power controller146determines one of multiple available voltage magnitudes to use for the power supply reference level192. For example, the circuitry148selects a particular voltage magnitude based on a selected performance state (P-state). The circuitry148selects the P-state based on determining a power domain for one or more components of the integrated circuit110. Each power domain includes operating parameters such as at least an operating power supply voltage and an operating clock frequency. Each power domain also includes control signals for enabling and disabling connections to clock generating circuitry and a power supply reference level. In some implementations, the voltage magnitude provided by the standby power supply reference level194is based on reducing leakage current of devices (transistors) within the persistent on-chip memory130.

As shown, the ROM180stores boot firmware182. As used herein, “firmware” includes instructions of an algorithm to be executed by circuitry to perform low-level tasks. An example of a low-level task is performing initial steps of a bootup operation. There are multiple types of the bootup operation. A cold bootup operation occurs when the computing device has been switched off, or otherwise had its power supply removed. A warm bootup operation occurs when the computing device maintains connection to its power supply without interruption, but the user restarts the computing device through a provided command or a particular input key sequence on the keyboard. Another example of a low-level task is performing initializing steps during resume time, which is the latency of the transition from the suspend state (or sleep state) to the active state. These initialization steps occur when the circuitry124of the security processor120determines the integrated circuit110transitions to an active state from a sleep state (or suspend state). Therefore, boot firmware and configuration information need to be maintained, such as stored in the on-chip memory130, for the security processor120to perform these initialization steps independent of interacting with one or more of the operating system and one or more drivers corresponding to one or more of the clients140. This sleep state (or suspend state) provides more power consumption reduction than other idle states, but at a cost of higher latency to perform the transition to the active state from the sleep state. This latency to perform the transition to the active state from the sleep state is also referred to as the “resume time” for the integrated circuit110.

When the power controller146determines the security processor120, the clients140, and the cache memory subsystem142transition to one of multiple idle states, the power supply reference level192remains turned on although at a smaller voltage magnitude than a voltage magnitude used by the active state. In each of the multiple idle states, one or more clients of the clients140maintain configuration information. Consequently, the integrated circuit110can return to the active state without restarting the operating system to obtain the configuration information used to initialize one or more clients of the clients140. In some implementations, the idle states of the integrated circuit110are states of the Advanced Configuration and Power Interface (ACPI) standard. In other implementations, the idle states of the integrated circuit110are states of another standard.

In contrast, when the power controller146determines the integrated circuit110transitions to the sleep state (or suspend state), the power supply reference level192is turned off, or the power supply reference level192is disconnected by power switches from a physical power plane. In the sleep state, the one or more clients of the clients140do not maintain configuration information. Consequently, to return to the active state, the integrated circuit110typically relies on the operating system to obtain the configuration information used to initialize the one or more clients of the clients140. Having the operating system perform the resume operation (the initialization steps for the clients140) provides a high latency to transition from the sleep state to the active state. In other words, the resume time is appreciably large. Therefore, the power controller146typically avoids using the sleep state on a regular basis although the sleep state provides lower power consumption than the idle states.

To reduce the latency of transitioning from the sleep state to the active state (or reduce the resume time for the integrated circuit110), the circuitry124of the security processor120stores a subset of the boot firmware182in the persistent on-chip memory130as information132. Additionally, the security processor120stores, in the persistent on-chip memory130as information132, a subset of configuration information used to initialize one or more clients of the clients140. In some implementations, the configuration information is for a client such as a parallel data processing unit that includes a graphics processing unit (GPU), a parallel data accelerator, a shader engine, or other. The configuration information, which is also referred to as context information, is used by a corresponding driver, such as a video graphics card driver or other type of driver, to initialize the client.

Initialization steps include one or more of setting up a frame buffer with a particular size and address range, setting up power management parameters to emphasize high performance or power consumption reduction, setting up modes of operation such as a default to a maximum operating clock frequency for all workloads or select the operating clock frequency based on a type of workload, setting up configuration and status registers with values corresponding to a resolution supported by a connected display device, identifying a particular version of a software toolkit or platform used to support applications that run on the client and aid the client to utilize commands from another client, identifying a particular bus interface and corresponding communication protocol parameters for accessing memory and/or communication with another client, and so forth. The types of workloads for the parallel data processing unit include parallelized floating-point calculations for machine learning (implementing neural networks), fast Fourier transforms for high-performance computing, and general-purpose computing on graphics processing units (GPGPU) applications.

The types of workloads for the parallel data processing unit also include rendering video pixel data of three-dimensional (3-D or 3D) visual content, and video shading during rendering. Examples of platforms are OpenCL (Open Computing Language), OpenGL (Open Graphics Library) and OpenGL for Embedded Systems (OpenGL ES), are used for running programs on GPUs from AMD, Inc. The applications are written by designers in a chosen higher-level language (e.g., C, C++, FORTRAN, and Java), and then partially processed with the aid of graphic libraries with their own application program interfaces

(APIs) based on the identified platform. It is possible and contemplated that the configuration information for the parallel data processing unit of the clients140includes other types of information and additional types of information than the above listed examples.

To reduce the latency of transitioning the integrated circuit110from the sleep state to the active state, the circuitry124of the security processor120stores, in the persistent on-chip memory130as information132, at least a subset of the configuration information for the parallel data processing unit of the clients140. It is also possible and contemplated that the security processor120stores as information132in the persistent on-chip memory130other configuration information corresponding to other types of clients of clients140. In some implementations, the security processor120stores information in the persistent on-chip memory130after previously authenticating the information. Since the security processor120is the only component of the integrated circuit110that accesses the persistent on-chip memory130, in some implementations, the security processor120does not generate any hash values or execute any encryption algorithms when storing information in the persistent on-chip memory130. In such implementations, the keys122are used for protecting and authenticating other information, but not for information read out of the persistent on-chip memory130. The lack of decrypting information stored in the persistent on-chip memory130further reduces the resume time, which is the latency of transitioning from the sleep state to the active state (or performing the resume operation).

As shown, each of the DRAM160and the disk memory170of the off-chip memory150stores a copy of multiple partitions. For example, the disk memory170stores the partitions172, and the DRAM160stores the partitions162. Each one of the partitions172is used as if it was a separate hard disk by the operating system and corresponding file system. Partitioning the disk memory170allows multiple operating systems and file systems to have information stored on the disk memory170. Each operating system and each file system within a respective operating system uses a corresponding partition independently from other operating systems and other file systems. Without partitions, a separate disk memory can be used for each separate operating system and each separate mounted file system. The number of partitions and the content of each of the partitions in partitions172follows either the MBR standard (that uses BIOS as boot firmware) or the GPT standard (that uses UEFI as boot firmware). There are at least two standards used to define how information used during a bootup operation is stored on the computing system100. A first standard uses a master boot record (MBR) and boot firmware referred to as basic input/output system (BIOS). A second standard uses the globally unique identifiers (GUID) partition table (GPT) and boot firmware referred to as unified extensible firmware interface (UEFI).

The partitions172are shown to include at least “Part. 1” (Partition 1), “Part. 2” (Partition 2), “Kernel Part. 1” (Kernel Partition 1), and “Kernel Part. 2” (Kernel Partition 2). These partitions can represent a variety of primary partitions, partitions with a root directory and one or more boot loaders for loading and running components of a particular operating system, partitions that include files and small programs to setup one or more file systems and/or one or more subdirectories of a particular file system, and so forth. During a resume operation, the security processor120inspects a flag that indicates whether the persistent on-chip memory130stores valid information. In some implementations, the flag is a data (e.g., one or more bits) stored in a particular storage location of the persistent on-chip memory130that indicates whether other storage locations of the persistent on-chip memory130stores valid information. In other implementations, the flag is stored in a register type implementation or multiple bits with error correction code (ECC) defending against data corruption.

When the security processor120determines the flag indicates that the persistent on-chip memory130stores valid information, the security processor120retrieves instructions of boot firmware of information132and runs it. Otherwise, if the security processor120determines the flag indicates that the persistent on-chip memory130stores invalid information, then the security processor120retrieves instructions of boot firmware182stored in the ROM180and runs it after authentication using the keys122. The steps of the boot firmware include performing one or more of a hardware discovery of computing system100, determining which I/O devices are bootable, determining whether any hardware resources are malfunctioning by performing a power-on self-test (POST), checking for custom or updated settings, loading the interrupt handlers and device drivers, initializing power management, displaying system settings, and loading initial programs of a bootstrap sequence. The algorithm defined by the boot firmware loads programs from a selected one of the partitions172. During the bootup operation, copies of selected partitions (or subsets of the selected partitions) are loaded from disk memory170and stored on the DRAM160and the cache memory subsystem142.

When the security processor120determines the flag indicates that the persistent on-chip memory130stores valid information, the security processor120is also capable of performing initializing steps, during resume time, independent of interacting with one or more of the operating system and one or more drivers corresponding to one or more of the clients140. Examples of the initialization steps were provided earlier. In some implementations, the persistent on-chip memory130has a limited size due to a limited amount of on-die area available in the integrated circuit110for the persistent on-chip memory130. The limited size prohibits the security processor120from storing all of the required configuration information in the persistent on-chip memory130. In such implementations, when transitioning to the suspend state, the security processor120also stores, in the system memory (the DRAM160), a subset of one or more of the boot firmware182and the configuration information for one or more of the clients140. This subset of information is unable to be stored in the persistent on-chip memory130with its limited size. The memory locations of a particular region of the DRAM160is accessible by only the security processor120, and this region is used to store the subset of information. In such implementations, the power controller146generates the standby power supply reference level195that is not turned off by the power supply unit145or the power controller146. The DRAM160receives the standby power supply reference level195. Therefore, in the suspend state, each of the persistent on-chip memory130and the DRAM160continue to receive a power supply reference level.

During the resume time, the security processor120retrieves information from each of the persistent on-chip memory130and the DRAM160to perform initialization steps of the resume operation independent of interacting with one or more of the operating system and one or more drivers corresponding to one or more of the clients140. In some implementations, the power controller146includes programmable configuration registers that stores a first value indicating a first threshold amount of time and a second value indicating a second threshold amount of time. The power controller146uses the first threshold amount of time to determine whether to turn off the standby power supply reference level194. For example, when a measurement of the idle time since the suspend state began reaches or exceeds the first threshold amount of time, the power controller146turns off the standby power supply reference level194. Therefore, power switches are used in this implementation for the standby power supply reference level194. Turning off the standby power supply reference level194causes the persistent on-chip memory130to lose its stored information, but it also further reduces power consumption during the suspend state.

In a similar manner, the power controller146uses the second threshold amount of time to determine whether to turn off the standby power supply reference level195. For example, when a measurement of the idle time since the suspend state began reaches or exceeds the second threshold amount of time, the power controller146turns off the standby power supply reference level195. Therefore, power switches are used in this implementation for the standby power supply reference level195. Turning off the standby power supply reference level195causes the DRAM160to lose its stored information, but it also further reduces power consumption during the suspend state. In another implementation, the power controller146uses a single threshold amount of time for both the persistent on-chip memory130and the DRAM160. In yet another implementation, each of the persistent on-chip memory130and the DRAM160includes circuitry that measures the idle time since the suspend state began, stores a value indicating a threshold amount of time for comparing to the measured idle time, and turning off a respective one of the standby power supply reference levels194and195. When both of the standby power supply reference levels194and195are turned off, as described earlier, during a later resume operation, the secure processor120retrieves a copy of the boot firmware182from the ROM180to initialize the clients140.

Referring now toFIG.2, a generalized block diagram is shown of a method200for efficiently managing power consumption of multiple components of an integrated circuit. For purposes of discussion, the steps in this implementation (as well as inFIGS.3-4and6-7) are shown in sequential order. However, in other implementations some steps occur in a different order than shown, some steps are performed concurrently, some steps are combined with other steps, and some steps are absent.

A voltage regulator provides a standby power supply voltage level to persistent on-chip memory that stores a copy of boot firmware and configuration information of one or more clients of an integrated circuit (block202). In various implementations, the standby power supply voltage level is directly connected to a power plane with no power switches being used. Therefore, the standby power supply voltage level cannot be turned off for the persistent on-chip memory. Additionally, the persistent on-chip memory utilizes one of a variety of types of on-chip SRAM. A power manager determines, for clients of an integrated circuit, a transition has begun to an active state from a sleep state (block204). In the sleep state, in some implementations, the power manager had turned off power supply reference levels to the one or more clients by sending particular control signals to power switches. Turning off the power supply reference levels provides low power consumption for the integrated circuit while in the sleep state (or suspend state).

To transition to the active state, the power manager provides one or more power supply voltage levels to the one or more clients of the integrated circuit (block206). The power manager returns to providing one or more power supply reference levels to the one or more clients by sending particular control signals to power switches. A security processor performs a resume operation by initializing, independent of the operating system, one or more clients using a copy of information stored in persistent on-chip memory (block208). For example, the security processor performs these initialization steps of the resume operation independent of interacting with one or more of the operating system and one or more drivers corresponding to one or more clients. The copy of the information includes at least a subset of boot firmware and a subset of configuration information used to initialize at least one client of multiple clients of the integrated circuit. Accessing this information from the persistent on-chip memory, rather than from one of a variety of types of off-chip memory, reduces the latency for transitioning the integrated circuit from the sleep state to the active state. However, in other implementations, a subset of this information is stored in the system memory, which receives a standby power supply reference level. In yet other implementations, one or more of the persistent on-chip memory and the system memory has its standby power supply reference level turned off when a measurement of an idle time since the suspend state began reaches or exceeds a threshold amount of time.

Turning now toFIG.3, a generalized block diagram is shown of a method300for efficiently managing power consumption of multiple components of an integrated circuit.

A voltage regulator provides a standby power supply voltage level to persistent on-chip memory that stores a copy of boot firmware and configuration information of one or more clients of an integrated circuit (block302). In various implementations, the standby power supply voltage level cannot be turned off for the persistent on-chip memory, since the standby power supply voltage level is directly connected to a power plane with no power switches being used. Additionally, the persistent on-chip memory utilizes one of a variety of types of on-chip SRAM. A power manager determines, for clients of an integrated circuit, a transition has begun to a sleep state from an active state (block304).

To transition to the sleep state (or suspend state), the power manager turns off each

of one or more power supply voltage levels to the one or more clients of the integrated circuit (block306). In an implementation, the power manager sends particular control signals to power switches to turn off the power supply reference levels. Turning off the power supply reference levels provides low power consumption for the integrated circuit while in the sleep state. In addition, the operating system saves its context information in one or more of system memory (typically implemented by DRAM) and main memory (typically implemented by disk memory). The security processor stores boot firmware and configuration information of one or more clients in the persistent on-chip memory, if this information is not already stored. In some implementations, the persistent on-chip memory has a limited size due to a limited amount of on-die area available for the persistent on-chip memory. In such implementations, the security processor also stores a subset of one or more of the boot firmware and the configuration information of the clients in the system memory.

Referring toFIG.4, a generalized block diagram is shown of a method400for efficiently managing power consumption of multiple components of an integrated circuit. A security processor determines a condition to initialize at least a given client of multiple clients of an integrated circuit (block402). Examples of the condition are a cold bootup operation, a warm bootup operation, and a resume operation. If the security processor determines that the persistent on-chip memory does not include a valid copy of boot firmware and configuration information (“no” branch of the conditional block404), then the security processor performs the initialization steps using copies of boot firmware and configuration information stored in one of a variety of types of off-chip memory (block406). To do so, in this case, the security processor interacts with one or more of the operating system and one or more drivers corresponding to one or more clients to locate the configuration information. In other words, the security processor is unable to independently perform the initialization steps. However, if the security processor determines that the persistent on-chip memory includes a valid copy of at least a subset of boot firmware and a subset of configuration information (“yes” branch of the conditional block404), then the security processor performs the initialization steps independent of the operating system and the one or more drivers corresponding to one or more clients by using the copy of boot firmware stored in the persistent on-chip memory (block408).

If the security processor determines an initialization stage for a particular client has not been reached (“no” branch of the conditional block410), then the security processor continues performing the initialization steps independent of the operating system using the copy of boot firmware stored in the persistent on-chip memory (block412). If the security processor determines an initialization stage for a particular client has been reached (“yes” branch of the conditional block410), then the security processor performs the initialization of the particular client independent of the operating system using the copy of configuration information stored in the persistent on-chip memory (block414). In an implementation, the particular client is a parallel data processing unit, and the subset of configuration information includes information for performing initialization steps such as setting up a frame buffer with a particular size and address range, setting up power management parameters to emphasize high performance or power consumption reduction, setting up modes of operation such as a default to a maximum operating clock frequency for all workloads or select the operating clock frequency based on a type of workload, setting up configuration and status registers with values corresponding to a resolution supported by a connected display device, identifying a particular version of a software toolkit or platform used to support applications that run on the client and aid the client to utilize commands from another client, identifying a particular bus interface and corresponding communication protocol parameters for accessing memory and/or communication with another client, and so forth.

If the security processor determines that the last client with configuration information stored in the persistent on-chip memory has not been reached (“no” branch of the conditional block416), then control flow of method400returns to block412where the security processor continues performing the initialization steps independent of the operating system using the copy of boot firmware stored in the persistent on-chip memory. If the security processor determines that the last client with configuration information stored in the persistent on-chip memory has been reached (“yes” branch of the conditional block416), then the security processor completes the initialization steps independent of the operating system and the one or more clients begin processing tasks (block418). For example, the operating system accesses the one or more clients and assigns tasks.

Referring toFIG.5, a generalized block diagram is shown of a computing system500that supports providing access to reliable boot firmware. As shown, the computing system500includes the processing node502. Although a single processing node is shown, it is possible and contemplated that the computing system500includes another number of processing nodes based on design requirements. The processing node502includes communication fabric520between each of clients510, memory controller530, power controller540and link interfaces542. In some implementations, the components of processing node502are individual dies on an integrated circuit (IC), such as a system-on-a-chip (SOC). In other implementations, the components are individual dies in a system-in-package (SiP) or a multi-chip module (MCM). A variety of computing devices use the processing node502such as a desktop computer, a laptop computer, a server computer, a tablet computer, a smartphone, a gaming device, a smartwatch, and so on.

The power supply unit545provides the power supply reference level590and the

standby power supply reference level594to the power controller540. In another implementation, the processing node502includes a voltage regulator separate from the power controller540that receives the power supply reference level590and the standby power supply reference level594. The power supply reference level592is based on the power supply reference level590, and it is possible for the power controller540to turn off the power supply reference level592. For example, the power controller540is capable of sending particular control signals to power switches that disconnect the disconnect the power supply reference level592from a physical voltage plane corresponding to the power supply reference level590.

Although a single power supply reference level592is shown, in other implementations, any number of power supply reference levels are generated by the voltage regulator (not shown) for use by the other circuitry of the processing node502such as at least the clients510, the communication fabric520, the memory controller530, and the link interfaces542. In various implementations, the power controller540determines one of multiple available voltage magnitudes to use for the power supply reference level592based on a selected performance state (P-state). The persistent on-chip memory514receives the standby power supply reference level594that is not turned off. The standby power supply reference level594is directly connected to a power plane that provides the standby power supply reference level594from the power supply unit545. There are no power switches used for the standby power supply reference level594. The standby power supply reference level594continually supplies a voltage magnitude to the persistent on-chip memory514. In some implementations, the persistent on-chip memory514utilizes one of a variety of types of on-chip SRAM, but the persistent on-chip memory514is not used as part of any cache memory subsystem. Rather, in various implementations, only the security processor513accesses data stored within the persistent on-chip memory514.

In the illustrated implementation, clients510include central processing unit (CPU)

512, graphics processing unit (GPU)515and Hub516. Hub516is used for communicating with Multimedia Engine518. The CPU512, GPU515and Multimedia Engine518are examples of computing resources capable of processing applications. Although not shown, in other implementations, other types of computing resources are included in clients510. Each of the one or more processor cores in CPU512includes circuitry for executing instructions according to a given selected instruction set architecture (ISA). In various implementations, each of the processor cores in CPU512includes a superscalar, multi-threaded microarchitecture used for processing instructions of the given ISA. In an implementation, GPU515includes a high parallel data microarchitecture with a significant number of parallel execution lanes. In one implementation, the microarchitecture uses single-instruction-multiple-data (SIMD) pipeline for the parallel execution lanes. Multimedia Engine518includes processors for processing audio data and visual data for multimedia applications.

In an implementation, the CPU512includes a security processor513that accesses copies of boot firmware stored in the persistent on-chip memory514. However, in other implementations, the GPU515or other type of client includes dedicated circuitry to implement the security processor513. In various implementations, the security processor513performs the functionality of the security processor120(ofFIG.1), and the persistent on-chip memory514performs data storage and is used in techniques in a same manner as the persistent on-chip memory130(ofFIG.1). Therefore, the computing system500supports reducing the transitions between an active state and a sleep state of the processing node502.

In some implementations, the communication fabric520transfers traffic back and forth between clients510and memory controller530and includes interfaces for supporting respective communication protocols. The communication fabric520includes at least queues for storing requests and responses, selection circuitry for arbitrating between received requests before sending requests across an internal network, packing circuitry for building and decoding packets, and control circuitry for selecting routes for the packets.

Although a single memory controller530is shown, in other implementations, another number of memory controllers are used in the processing node502. The memory controller530receives memory requests from clients510via the communication fabric520, schedules the memory requests, and sends the scheduled memory requests to one or more of system memory and main memory. Memory controller530also receives responses from system memory (implemented by DRAM560) and main memory (implemented by disk memory570) and sends the responses to a corresponding source of the request in clients510. The memory controller530also supports one or more memory interface protocols. A protocol determines values used for information transfer, such as a number of data transfers per clock cycle, signal voltage levels, signal timings, signal and clock phases and clock frequencies. In various implementations, system memory, such as DRAM560, is filled with data from main memory through the I/O controller and bus572and the memory bus550. A corresponding cache fill line with the requested block is conveyed from main memory, such as disk memory570, to a corresponding one of the cache memory subsystems in clients510in order to complete the original memory request. The cache fill line is placed in one or more levels of caches.

The address space of processing node502is divided among at least CPU512, GPU515and Hub516and one or more other components such as input/output (I/O) peripheral devices (not shown) and other types of computing resources. Memory maps are maintained for determining which addresses are mapped to which component, and hence to which one of CPU512, GPU515and Hub516a memory request for a particular address should be routed. In some implementations, main memory, such as disk memory570, is one of a variety of types of non-volatile, random access secondary storage of data. Examples of main memory are hard disk drives (HDDs) and solid-state disks (SSDs).

Link interfaces542support communication between processing node502and other processing nodes by transferring messages on links. In various implementations, the messages sent across the links between nodes include an indication of an operating state for one or more nodes, a power down request, responses to requests, interrupts, and other information. In various implementations, each link is a point-to-point communication channel between two nodes. At the physical level, a link includes one or more lanes. In some implementations, link interfaces542, the corresponding links, and other nodes include communication protocol connections such as PCIe (Peripheral Component Interconnect Express), InfiniBand, RapidIO, HyperTransport, and so forth. In some implementations, link interfaces542include control circuitry and buffers or queues used to communicate with other nodes via the interconnect links.

In one implementation, power controller540collects data from clients510. In some implementations, power controller540also collects data from memory controller530. In some implementations, the collected data includes predetermined sampled signals. The switching of the sampled signals indicates an amount of switched capacitance. Examples of the selected signals to sample include clock gating enable signals, bus driver enable signals, mismatches in content-addressable memories (CAM), CAM word-line (WL) drivers, and so forth. In an implementation, power controller540collects data to characterize power consumption in the processing node502during given sample intervals. On-die current sensors and temperature sensors in the processing node502also send information to power controller540. Power controller540uses one or more of the sensor information, a count of issued instructions or issued threads, and a summation of weighted sampled signals to estimate power consumption for the processing node502. Power controller540decreases (or increases) power consumption if the processing node502is operating above (below) a threshold limit. In some implementations, power controller540selects a respective power-performance state (P-state) for each of the computing resources in clients510. The P-state includes at least an operating voltage and an operating clock frequency. In addition, the power controller540determines whether the processing node502is placed in an active state or in a sleep state.

Referring toFIG.6, a generalized block diagram is shown of a method600for efficiently managing power consumption of multiple components of an integrated circuit. A security processor determines a condition to initialize at least a given client of multiple clients of an integrated circuit (block602). Examples of the condition are a cold bootup operation, a warm bootup operation, and a resume operation. If the security processor determines that the persistent on-chip memory includes a valid copy of boot firmware and configuration information (“yes” branch of the conditional block604), then the security processor performs the initialization steps independent of the operating system using copies of boot firmware and configuration information stored in persistent on-chip memory (block606). If the security processor determines that the persistent on-chip memory does not include a valid copy of boot firmware and configuration information (“no” branch of the conditional block604), then the security processor retrieves a copy of boot firmware stored in one of multiple types of off-chip memory (block608). The security processor stores a copy of at least a subset of the boot firmware in persistent on-chip memory (block610). In addition, the operating system performs the initialization steps for the multiple clients. The stored information, though, allows the security processor to perform the initialization steps for a subsequent resume operation.

When storing information in the persistent on-chip memory, the security processor

retrieves copies of boot loaders and configuration information stored in one or more of multiple types of off-chip memory. The security processor selects at least a subset of information of the copies of boot loaders and configuration information. In an implementation, a particular client is a parallel data processing unit, and the subset of configuration information includes information for performing initialization steps such as setting up a frame buffer with a particular size and address range, setting up power management parameters to emphasize high performance or power consumption reduction, setting up modes of operation such as a default to a maximum operating clock frequency for all workloads or select the operating clock frequency based on a type of workload, and setting up configuration and status registers with values corresponding to a resolution supported by a connected display device.

Other examples of the subset of configuration information for the parallel data processing unit are information identifying a particular version of a software toolkit or platform used to support applications that run on the client and aid the client to utilize commands from another client, information identifying a particular bus interface and corresponding communication protocol parameters for accessing memory and/or communication with another client, and so forth. In various implementations, the security processor authenticates each of the boot firmware and the configuration information prior to using them and storing them in the persistent on-chip memory. As described earlier, in some implementations, the persistent on-chip memory has a limited size due to a limited amount of on-die area available for the persistent on-chip memory. In such implementations, the security processor also stores a subset of one or more of the boot firmware and the configuration information of the clients in the system memory. In such implementations, the system memory receives a standby power supply reference level. In yet other implementations, one or more of the power controller, the persistent on-chip memory, and the system memory includes timers used to determine when a measurement of the idle time since the suspend state began reaches or exceeds a threshold amount of time, and then one or more of the standby power supply reference levels are turned off for the persistent on-chip memory and the system memory.

Turning now toFIG.7, a generalized block diagram is shown of a method700for updating bootup and configuration information used by multiple components of an integrated circuit. A security processor detects (e.g., a condition) or otherwise determines an update procedure is indicated. For example, such a condition may indicate an update is to be performed using one or more of boot firmware and configuration information stored in one or more of multiple types of off-chip memory (block702). The off-chip memory includes one or more of a variety of types of non-volatile ROMs, a variety of type of volatile DRAM, and non-volatile hard disk drives (HDDs) and solid-state disks (SSDs). If the security processor determines that persistent on-chip memory includes a valid copy of boot firmware and configuration information (“yes” branch of the conditional block704), then the security processor invalidates the contents of the persistent on-chip memory (block706). Afterward, the security processor or other circuitry updates one or more of boot firmware and configuration information stored in the one or more of the multiple types of off-chip memory (block708). If the security processor determines that persistent on-chip memory does not include a valid copy of boot firmware and configuration information (“no” branch of the conditional block704), then control flow of method700moves to block708where the security processor or other circuitry updates one or more of boot firmware and configuration information stored in the one or more of the multiple types of off-chip memory.

It is noted that one or more of the above-described implementations include software. In such implementations, the program instructions that implement the methods and/or mechanisms are conveyed or stored on a computer readable medium. Numerous types of media which are configured to store program instructions are available and include hard disks, floppy disks, CD-ROM, DVD, flash memory, Programmable ROMs (PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage. Generally speaking, a computer accessible storage medium includes any storage media accessible by a computer during use to provide instructions and/or data to the computer. For example, a computer accessible storage medium includes storage media such as magnetic or optical media, e.g., disk (fixed or removable), tape, CD-ROM, or DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-Ray. Storage media further includes volatile or non-volatile memory media such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low-power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM, Flash memory, non-volatile memory (e.g., Flash memory) accessible via a peripheral interface such as the Universal Serial Bus (USB) interface, etc. Storage media includes microelectromechanical systems (MEMS), as well as storage media accessible via a communication medium such as a network and/or a wireless link.

Additionally, in various implementations, program instructions include behavioral-level descriptions or register-transfer level (RTL) descriptions of the hardware functionality in a high level programming language such as C, or a design language (HDL) such as Verilog, VHDL, or database format such as GDS II stream format (GDSII). In some cases, the description is read by a synthesis tool, which synthesizes the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates, which also represent the functionality of the hardware including the system. The netlist is then placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks are then used in various semiconductor fabrication steps to produce a semiconductor circuit or circuits corresponding to the system. Alternatively, the instructions on the computer accessible storage medium are the netlist (with or without the synthesis library) or the data set, as desired. Additionally, the instructions are utilized for purposes of emulation by a hardware based type emulator from such vendors as Cadence®, EVE®, and Mentor Graphics®.