Cross-coupled input voltage sampling and driver amplifier flicker noise cancellation in a switched capacitor analog-to-digital converter

A switching component comprises a plurality of switches configured to receive a differential signal at an input and is configured to provide a non-inverted version of the differential signal at an output during a first phase of operation and an inverted version of the differential signal at an output during a second phase of operation. A driver amplifier component is configured to receive the non-inverted version of the differential signal at an input during the first phase of operation and the inverted version of the differential signal at an input during the second phase of operation. A sampling capacitor component is configured to sample the output of the driver amplifier component during the first phase of operation and the second phase of operation.

FIELD

The present disclosure relates to switched capacitor systems and, in particular, to cross-coupled input voltage sampling and driver amplifier flicker noise cancellation in switched capacitor analog to digital converter (ADC).

BACKGROUND

Advancement in modern technology has led to an increased number of digital applications and thereby to an increased demand for analog-to-digital converters (ADCs). Delta sigma (ΣΔ) ADCs have the advantage of offering high resolution among the various types of ADCs. ΣΔ ADCs comprise a switched capacitor integrator as its first stage in order to sample the input signal. One of the main limitations of the performance of switched capacitor circuits is noise, such as thermal noise. In switched capacitor systems, this thermal noise (e.g., thermal KT/C noise) limits the accuracy of the sampling circuit. Further, in some applications ΣΔ ADCs include a driver amplifier, which generates flicker noise associated with it that further degrades the performance of the ΣΔ ADCs. Therefore, it is desirable for a switched capacitor system to operate with low thermal noise and low flicker noise.

SUMMARY

In one embodiment of the disclosure, a switched capacitor system comprises a switching stage comprising a plurality of switches configured to receive a differential signal at an input of the switching stage and provide a non-inverted version of the differential signal at an output of the switching stage during a first phase of operation and an inverted version of the differential signal at the output of the switching stage during a second phase of operation. The switched capacitor system further comprises a driver stage comprising an amplifier, located downstream of the switching stage, configured to receive the non-inverted version of the differential signal at an input of the driver stage during the first phase of operation and the inverted version of the differential signal at the input of the driver stage during the second phase of operation. A sampling capacitor stage is configured to sample an output of the driver stage during the first phase of operation and the second phase of operation and provide a cancellation of a flicker noise and an offset of the driver stage during the second phase of operation. In addition, the switched capacitor system comprises a switching controller configured to control a cross-coupled configuration of the plurality of switches and increase a signal-to-noise ratio of the sampling capacitor stage by approximately doubling a transferred charge and corresponding signal swing across the sampling capacitor stage.

In another embodiment of the disclosure, an analog to digital converter system, comprises a switching component configured to receive a differential signal at a first signal branch and a second signal branch, comprising a first set of switches configured to provide a non-inverted version of the differential signal at an output of the switching component during a first phase of operation, and a second set of switches configured to provide an inverted version of the differential signal at the output of the switching component during a second phase of operation. The analog to digital converter system further comprises a driver component configured to generate a drive signal to the first signal branch and the second signal branch based on the non-inverted version of the differential signal during the first phase of operation and based on the inverted version of the differential signal during the second phase of operation. A sampling component is configured to sample the drive signal of the driver component, generate a charge transfer to a first sampling capacitor and a second sampling capacitor during the first phase of operation and the second phase of operation, and generate a cancellation of a flicker noise and an offset of the driver component during the second phase of operation. In addition the analog to digital converter system comprises a switching control component configured control a cross-coupled configuration of the first set of switches and the second set of switches and increase a signal-to-noise ratio of the sampling component by approximately doubling a charge transfer and corresponding signal swing across the first sampling capacitor and the second sampling capacitor.

In another embodiment of the disclosure, a method for an analog to digital converter comprises receiving an analog differential signal, sampling a first portion of the analog differential signal at a first sampling capacitance in a first phase of operation, and generating a first charge transfer to the first sampling capacitance. The method further includes sampling a second portion of the analog differential signal, comprising an inverted version of the first portion of the differential signal at the first sampling capacitance in a second phase of operation, and generating a second charge transfer to the first sampling capacitance and providing, via a first amplifier, the first portion and the second portion of the analog differential signal prior to the first charge transfer and the second charge transfer to the first sampling capacitance. The method further comprises sampling the second portion of the analog differential signal at a second sampling capacitance in the first phase of operation, and generating a first charge transfer to the second sampling capacitance, sampling the first portion of the analog differential signal, comprising an inverted version of the second portion of the analog differential signal at the second sampling capacitance in the second phase of operation, and generating a second charge transfer to the second sampling capacitance and providing, via a second amplifier, the second portion and the first portion of the analog differential signal prior to the first charge transfer and the second charge transfer to the second sampling capacitance.

DETAILED DESCRIPTION

This disclosure is directed towards a cross-coupled input voltage sampling and driver amplifier flicker noise cancellation in switched capacitor ADCs. Delta-sigma conversion is a method that is used when high resolution is desired. ADC comprises an integrator having a switched capacitor sampling circuit as a first stage of operation. Further, ADC includes a driver amplifier in order to provide isolation of the signal source from the sampling circuit and provide a low impedance drive for the sampling circuit. However, switched capacitor systems are subject to noise, which limits the accuracy of the sampling circuit.

At least two noise effects associated with switched capacitor ADCs can include thermal noise and flicker noise of the driver amplifier. Thermal noise is the electronic noise generated by the thermal agitation of the charge carriers (usually the electrons) inside an electrical conductor at equilibrium, which happens regardless of the applied voltage. The thermal noise on a sampling capacitor is inversely proportional to the capacitor value (KT/C noise). In order to provide low noise performance, the capacitor value can be made sufficiently high. However, large capacitors can degrade the speed of the circuit and increase the area. In addition, flicker noise, a type of electronic noise dominant in the low frequency range, can be caused by charge carriers getting trapped and later released as they move in a channel of transistors.

To provide a solution for reducing the thermal noise and flicker noise associated with switched capacitor sampling circuits, one example architecture of the sampling circuit provides an implementation of cross-coupled input voltage sampling and driver amplifier flicker noise cancellation. In some embodiments, the sampling circuit enables a reduction of the flicker noise and an offset of the driver amplifiers.

Cross-coupled input voltage sampling operates to reduce the effect of thermal noise by increasing the effective sampling charge across sampling capacitors, thereby obtaining improved signal to noise performance for a given capacitor value. For example, in a switched capacitor sigma delta ADC, a sampling circuit of a first integrator can sample the input signal in both φ1and φ2phases (sampling and integration) in order to double the amount of charge transferred to an integration capacitor during an integration phase. In one embodiment, a fully differential circuit with a differential input signal performs sampling of the input signal in both φ1and φ2phases by using a cross-coupled switching circuit, which samples the differential input with opposite polarities in the two phases φ1and φ2. This cross-coupled sampling doubles the effective voltage swing across the sampling capacitors, thereby doubling the sampled charge and the sampled signal power during the integration phase, while the thermal noise remains the same. This technique improves the SNR performance of the sampling circuit.

FIG. 1depicts an example ADC100, according to the present disclosure, comprising an integrator102having a sampling circuit104. The ADC100receives a differential input signal106at the input of the sampling circuit104, which is configured to sample the differential input signal106at a particular sampling frequency. The sampling circuit104further comprises a switching stage110configured to receive the differential input signal106at its input, a driver stage112located downstream of the switching stage110, a sampling capacitor stage114located downstream of the driver stage112and a switching controller116configured to control a configuration of the switching stage110. The sampling frequency is greater than or equal to the Nyquist frequency, which is twice the frequency of the differential input signal106. During a sampling phase, the sampling circuit104samples the differential input signal106. During an integration phase, the sampled differential input signal is transferred to the integrator102, which generates an output signal108proportional to the integral of the sampled differential input signal.

The switching stage110, for example, can comprise different switching components such as a plurality of switches, transistors, or other switching devices, for example, in order to generate switching patterns or operations. The switching stage110can define a point in time or phase(s) of operation based on switching configurations. The switching stage110of the switching circuit104can operate to receive the differential input signal106at different signal branches or at different signal chains or pathways, such as a first signal branch and a second signal branch of an input of the switching stage. In one embodiment, the switching stage110of the sampling circuit104can provide a non-inverted version of the differential input signal106at an output of the switching stage110, which can be performed during a first phase of operation. In addition, the switching stage110can operate to provide an inverted version of the differential input signal106at the output of the switching stage110during a second phase of operation. For example, in the first phase of operation, the switching stage110can configure a first set of switches (not shown) to be turned on, activated, or in a configuration or state that is a first configuration among various different configurations, for example. Concurrently or at the same time, the switching stage110can configure a second set of switches to be turned off, inactivated or in a second different state or configuration than the first state of configuration.

Additionally or alternatively, the switching stage110can operate in a second phase of operation that is different from the first phase of operation. For example, a second set of switches (now shown) can be turned on, activated or in a third state, while the first set of switches are turned off or inactivated in a fourth state.

The switching stage110operates to alter the states or configuration of the sampling circuit along one or more signal branches and to provide a first set of control signals to the driver stage112in a first state or first configuration and a second set of output signals or control signals in a second state or second configuration. The control signals, for example, can be different from one another based on the different switching states generated by the switching stage110(e.g., different polarities, inversions, frequencies, or the other parameter difference). In addition or alternatively, the control signals provided to the driver stage112can be single ended signals or differential signals, for example.

In addition, the different configurations generated by the switching stage110can be configured or dynamically structured based on the differential input signal106and a control signal derived from the switching controller116. The switching stage110can operate to generate the different configurations or states among different signal pathways, branches or signal chains as the first and second configurations or stages, or generate the different configurations or states within individual signal branches or pathways independently of one another. For example, the switching stage110can generate the first configuration by cross-coupling two or more signal pathways coupled to the driver stage112or other components within the sampling circuit104, and generate the second configuration within each signal pathway without cross-coupling branches or pathways of signal communication.

The driver stage112is located downstream of the switching stage110and is configured to receive the output of the switching stage110during the first phase of operation and the second phase of operation. For example, a first output of the switching stage110can be received during the first phase of operation and comprise a first signal or a first switching signal that is derived from the first switching state of the switching stage110. A second output of the switching stage110can be received by the driver stage112during the second phase of operation and comprise a second output signal or a first switching signal of the switching stage110. In one aspect, the driver stage112can comprise one or more amplifiers (e.g., drivers, buffers etc.) that generate a driver output to drive or bias one or more components of the sampling capacitor stage114.

The driver stage112further operates to provide an isolation of the signal source (i.e. the differential input signal106) from the sampling capacitor stage114. The driver stage112can also generate a low impedance drive for the sampling circuit104, which can be derived from or operate based on the controls signals received from the switching stages as a function of the different phases of operation (the first phase and the second phase). The driver stage112can be further configured to process a differential signal or other signal as the output signals from the switching stage110during the different phases (the first phase of operation and the second phase of operation) received at its input. In addition, the driver stage112provides the different inversions of the processed signals with a driver signal or other amplifier signal. For example, the driver stage112can generate a voltage source signal while providing the non-inverted version of the differential signal106at its output during the first phase of operation and the inverted version of the differential input signal106at its output during the second phase of operation. As such, the driver stage112drives a driver signal or a bias signal to the sampling capacitor stage114with the different inversions of the switching stage output110.

In one embodiment, the driver stage112can comprise one or more drivers, buffer amplifiers, or other driver circuits, which can provide driver signals with the inverted and non-inverted versions of the outputs of the switching stage110along one or more different signal branches or pathways. For example, a first driver amplifier (not shown) on a first signal branch or pathway (not shown) can be configured to receive the differential signal at the first signal branch of the output of the switching stage110and a second driver amplifier on the second signal branch can be configured to receive the differential signal at the second signal branch of the output of the switching stage110. The first driver amplifier and the second driver amplifier can be, for example, amplifiers with a single input terminal and a single output terminal, or can comprise multiple different input terminal or output terminals respectively.

In another embodiment, for example, the driver stage112can comprise a fully differential amplifier with two inputs and two outputs. The two inputs of the driver stage112comprises a first driver input configured to receive the differential signal at the first signal branch of the output of the switching stage110and a second driver input configured to receive the differential signal at the second signal branch of the output of the switching stage110. The two outputs of the driver stage112comprises a first driver output configured to provide a drive signal to the first signal branch and a second driver output configured to provide a drive signal to the second signal branch.

The sampling capacitor stage114is located downstream of the driver stage112and is configured to receive the drive signal from the driver stage112. In one embodiment, the sampling capacitor stage114comprises a first sampling capacitor configured to sample the drive signal on the first signal branch at the output of the driver stage112during the first phase of operation and the second phase of operation. Additionally, the sampling capacitor stage114comprises a second sampling capacitor configured to sample the drive signal on the second signal branch at the output of the driver stage112during the first phase of operation and the second phase of operation.

The integrator102is located downstream of the sampling capacitor stage114and can comprise a fully differential integrator having two inputs and two outputs. The fully differential integrator, according to one embodiment, comprises a first integrating capacitor configured to integrate a sampled voltage across the first sampling capacitor during the second phase of operation. The fully differential integrator further comprises a second integrating capacitor configured to integrate a sampled voltage across the second sampling capacitor during the second phase of operation.

The switching controller116is coupled to the switching stage110and is configured to control the configuration of the plurality of switches in the switching stage110. The switching controller116provides a non-overlapping clock scheme and can be implemented with hardware/software or both. In one embodiment, the switching controller116operates to turn on or activate a first switching configuration or state in the switching stage110, such as with a first set of switches or switching components, for example. As such, the switching controller116can adjust the switching stage110to operate in the first phase of operation and generate a first charge transfer to the sampling capacitor stage114, which can comprise, for example, one or more capacitors or capacitor components, such as a first sampling capacitor and a second sampling capacitor. Further, the switching controller116can operate to turn on or activate the switching stage110to operate in the second switching configuration or state, such as with a second set of switches or switching components of the switching stage110. The switching controller116can also activate the switching stage110to operate in a second phase of operation to generate a second charge transfer to the sampling capacitor stage114. The different charge transfers, the first and the second charge transfer, for example, can be derived from input signals of different configurations or stages, which can generate different inversions of the input signals and different cross couplings depending upon the phase and configurations being generated by the switching stages and the driver stage112. The switching controller116thus can operate to alternate or sequence the different phases (e.g., the first phase and the second phase of operation), such as to generate different charges for storage and subsequent sampling in one or more capacitor components, such as with a first sampling capacitor or a second sampling capacitor.

In response, a non-inverted version of the differential input signal106can be sampled onto the first sampling capacitor and the second sampling capacitor during the first charge transfer, and the inverted version of the differential input signal106can be sampled onto the first sampling capacitor and the second sampling capacitor during the second charge transfer. Because the differential input signal106can be sampled on to the first sampling capacitor and to the second sampling capacitor with opposite polarities during the first phase of operation and the second phase of operation respectively, the sampling circuit104operates to increase, or approximately double, a sampling charge to the sampling capacitor stage114, such as to one or more sampling capacitors (e.g., a first sampling capacitor and the second sampling capacitor). The sampling circuit104is configured to increase the signal-to-noise ratio of the sampling capacitor stage114by a factor of approximately two, for example.

The driver stage112further operates to provide the differential input signal106to the sampling capacitor stage114prior to the first charge transfer and the second charge transfer respectively. A first positive flicker noise and a first offset (e.g., a driver signal mismatch or offset of the output of the amplifiers within the driver stage112) is introduced into the first charge transfer to the sampling capacitor stage114during the first phase of operation. Additionally, a second positive flicker noise and a second offset are introduced into the second charge transfer to the sampling capacitor stage114during the second phase of operation. Because the first positive flicker noise and the first offset and the second positive flicker noise and second offset are opposite in polarities, the sampling circuit104operates to generate a cancellation of the flicker noise and the offsets, and thereby provide better ADC stability and resolution with a decrease in noise.

FIG. 2illustrates a particular embodiment wherein a sampling circuit202for a fully differential switched capacitor integrator200is disclosed. The sampling circuit202comprises a cross-coupled switching stage204comprising a plurality of switches210,212,214and216configured to receive an analog differential signal205at its input and configured to provide a non-inverted version of the differential signal at its output during a first phase of operation and an inverted version of the differential signal at its output during a second phase of operation. Additionally, the sampling circuit202comprises a driver amplifier stage206located downstream of the cross-coupled switching stage204and configured to receive the non-inverted version of the differential signal at its input during the first phase of operation and the inverted version of the differential signal at its input during the second phase of operation. Furthermore, the sampling circuit202comprises a sampling capacitor stage208downstream of the driver amplifier stage206configured to sample the output of the driver amplifier stage206during the first phase of operation and the second phase of operation.

The driver amplifier stage206ofFIG. 2further comprises a first driver amplifier218downstream of a first branch of the cross-coupled switching stage204and a second driver amplifier220downstream of a second branch of the cross-coupled switching stage204. Additionally, the sampling capacitor stage208comprises a first sampling capacitor222coupled to the output of the first driver amplifier218and a second sampling capacitor224coupled to the output of the second driver amplifier220.

Furthermore, the cross-coupled switching stage204ofFIG. 2comprises a first switch210between the first input226of the analog differential signal205and an input of the first driver amplifier218, and a second switch212between the second input228of the analog differential signal205and an input of the second driver amplifier220. The cross-coupled switching stage204further comprises a third switch214between the first input226of the analog differential signal205and an input of the second driver amplifier220, and a fourth switch216between the second input228of the analog differential signal205and an input of the first driver amplifier218, wherein the third switch214and the fourth switch216operate to cross-couple the first input226of the analog differential signal205and the second input228of the analog differential signal205to the second driver amplifier220and the first driver amplifier218.

In one embodiment, the cross-coupled switching stage204is configured, in the first phase of operation, to turn on the first switch210and the second switch212, while the third switch214and the fourth switch216are turned off. Further, in the second phase of operation, the cross-coupled switching stage204is configured to turn on the third switch214and the fourth switch216, while the first switch210and the second switch212are turned off.

FIG. 3shows another embodiment wherein a sampling circuit302for a fully differential switched capacitor integrator300is disclosed. The sampling circuit302comprises a cross-coupled switching circuit304comprising a plurality of switches310,312,314and316configured to receive an analog differential signal305at its input and configured to provide a non-inverted version of the differential signal at its output during a first phase and an inverted version of the differential signal at its output during a second phase. Additionally, the sampling circuit302comprises a driver amplifier stage306located downstream of the cross-coupled switching circuit304and configured to receive the non-inverted version of the differential signal at its input during the first phase of operation and the inverted version of the differential signal at its input during the second phase of operation. Furthermore, the sampling circuit302comprises a sampling capacitor stage308downstream of the driver amplifier stage306configured to sample the output of the driver amplifier stage306during the first phase of operation and the second phase of operation.

The driver amplifier stage306ofFIG. 3comprises a fully differential driver amplifier318with its first input319coupled to the first branch of the cross-coupled switching circuit304and its second input320coupled to the second branch of the cross-coupled switching circuit304. Additionally, the sampling capacitor stage308comprises a first sampling capacitor322coupled to the first output330of the driver amplifier318and a second sampling capacitor324coupled to the second output332of the driver amplifier318.

Furthermore, the cross-coupled switching circuit304ofFIG. 3comprises a first switch310between the first input326of the analog differential signal305and the first input319of the driver amplifier318, and a second switch312between the second input328of the analog differential signal305and a second input320of the driver amplifier318. The cross-coupled switching circuit304further comprises a third switch314between the first input326of the analog differential signal305and the second input320of the driver amplifier318, and a fourth switch316between the second input328of the analog differential signal305and the first input319of the driver amplifier318, wherein the third switch314and the fourth switch316operate to cross-couple the first input326and the second input328of the analog differential signal305to the second input320and the first input319of the driver amplifier318.

FIG. 4ashows a schematic diagram of a switched capacitor sampling network400, according to the present disclosure that could be used as an input circuit for an ADC, such as a ΣΔADC. The network400comprises a cross-coupled switching circuit402comprising a first switch S1410between the first input446of the analog differential signal405and an input of the first driver amplifier418, and a second switch S2412between the second input448of the analog differential signal405and an input of the second driver amplifier420. The cross-coupled switching circuit402further comprises a third switch S3414between the first input446of the analog differential signal405and an input of the second driver amplifier420, and a fourth switch S4416between the second input448of the analog differential signal405and an input of the first driver amplifier418, wherein the third switch S3414and the fourth switch S4416operate to cross-couple the first input446and the second input448of the analog differential signal405to the second driver amplifier420and the first driver amplifier418.

Network400further comprises a driver amplifier system404of comprising a first driver amplifier418downstream of a first branch of the cross-coupled switching circuit402and a second driver amplifier420downstream of a second branch of the cross-coupled switching circuit402. Additionally, the network400comprises a sampling capacitor component406comprising a first sampling capacitance C1422coupled to the output445of the first driver amplifier418and a second sampling capacitance C2424coupled to the output447of the second driver amplifier420.

Furthermore, the network400comprises an integrator407comprising an operational amplifier408with an inverting terminal438and a non-inverting terminal440. Integrator407produces an integrated signal that comprises a positive voltage output signal “Voutp”442and a negative voltage output signal “Voutn”444. A positive voltage integrator feedback capacitor C4434is connected in parallel with operational amplifier408between438and “Voutp”442. A negative voltage integrator feedback capacitor C3436is connected in parallel with operational amplifier408between440and “Voutn”444. In addition, the network400comprises summing junction switches S4, S5, S6and S7. Switch S4428is disposed between C1422and a reference ground. Switch S6426is disposed between C1422and inverting terminal438of the operational amplifier408. Likewise, switch S5430is disposed between C2424and a reference ground. Switch S7432is disposed between C2424and non-inverting terminal440of the operational amplifier408.

FIG. 4billustrates a two-phase non-overlapping clock450defined by four clock waveforms: “φ1”452, “φ1d”454, “φ2”456and “φ2d”458. The position of each switch at any given time is determined by its corresponding clock waveform. In a representative embodiment, a switch is open when its corresponding clock waveform is “off” and a switch is closed when its corresponding clock waveform is “on”. However, in other embodiments, the switches could be configured with other relationships between the state of the switches and their corresponding clock waveforms.

Operation of network400can be explained by tracing the circuits that are established in response to the cycling of the clock waveforms of the clock450. At time t0, clock waveforms φ1452and φ1d454cycle to the on state while the clock waveforms φ2456and φ2d458remain in the off state. In response to the on state of φ1452, switches S4428and S5430close. In response to the on state of φ1d454, switches S1410and S2412close. With S1410and S4428closed, a circuit is established between the first input446i.e., Vp and ground449through driver amplifier418and C1422. This circuit allows the first input446i.e., Vp to be sampled as a charge on C1422. Further, this circuit samples a flicker noise Vfp of the driver amplifier418as a charge on C1422. Similarly, with S2412and S5430closed, a circuit is established between the second input448i.e., Vn and ground449through driver amplifier420and C2424. This circuit allows the second input448i.e., Vn to be sampled as a charge on C2424. Further, this circuit samples a flicker noise Vfn of the driver amplifier420as a charge on C2424.

At time t1, clock waveform φ1452cycles to the off state while φ1d454remains in the on state. Clock waveforms φ2456and φ2d458remain in the off state. In response to the off state of φ1452, switches S4428and S5430open. Opening switch S4428breaks the circuit between the first input446i.e., Vp and ground449. This isolates the charge stored on C1422, thus effectively sampling the first input446i.e., Vp and Vfp. The total charge sampled on capacitance C1422at the end of first phase of operation is defined by:
QC11=C1★(Vp+Vfp)  (1)
Similarly, opening switch S5430breaks the circuit between the second input448i.e., Vn and ground449. This isolates the charge stored on C2424, thus effectively sampling the second input448i.e., Vn and Vfn. The total charge sampled on capacitance C2424at the end of first phase of operation is defined by:
QC21=C2★(Vp+Vfp)  (1)

At time t2, clock waveform φ1d454cycles to the off state. Clock waveforms φ1452, φ2456and φ2d458remain in the off state. In response to the off state of φ1d454, switches S1410and S2412open. By delaying the opening of switches S1410and S2412until after switches S4428and S5430have been opened, and thus isolating the charges stored on C1422and C2424, the sampled signals are unaffected by the charge injections that occur after switches S4428and S5430have been opened.

At time t3, clock waveforms φ2456and φ2d458cycle to the on state while the clock waveforms φ1452and φ1d454remain in the off state. In response to the on state of φ2d458, switches S3414and S4416close. In response to the on state of φ2456, switches S6426and S7432close. With switches S6426and S4416closed, a circuit is established between the second input448i.e., Vn and the inverting terminal438of the operational amplifier408through driver amplifier418and C1422. This circuit allows the second input448i.e., Vn and the flicker noise Vfp of the driver amplifier418to be sampled as a charge on C1422and further enables the total charge QC1+on C1422to be transferred to C4434. The transferred charge QC1+is defined by:
QC1+=C1*((Vp+Vfp)−(Vn+Vfp))=C1*(Vp−Vn)  (3)
Similarly, with switches S7432and S3414closed, a circuit is established between the first input446i.e., Vp and the non-inverting terminal440of the operational amplifier408through driver amplifier420and C2424. This circuit allows the first input446i.e., Vp and the flicker noise Vfn of the driver amplifier420to be sampled as a charge on C2424and further enables the total charge QC2+on C2424to be transferred to C3436. The transferred charge QC2+is defined by:
QC2+=C2*((Vn+Vfn)−(Vp+Vfn))=C2*(Vn−Vp)  (4)

From the above analysis, it is clear that the cross-coupled sampling doubles the effective voltage swing (i.e., Vp−Vn and Vn−Vp) across the sampling capacitance C1422and C2424by sampling the differential signal with opposite polarities during the first phase and the second phase, thereby doubling the integrated charge across C4434and C3436, while the thermal noise remains the same. This improves the SNR performance of the sampling circuit. Further, flicker noise Vfp and Vfn of the buffer amplifiers gets sampled on to the sampling capacitance C1422and C2424with the same polarity during the first phase and the second phase, thereby enabling the cancellation of the flicker noise during the integration phase.

At time t4, clock waveform φ2456cycles to the off state, while φ2d458remains in the on state. Clock waveforms φ1452and φ1d454remain in the off state. In response to the off state of φ2456, switches S6426and S7432open. Opening switch S6426breaks the circuit between the first input446i.e., Vp and inverting terminal438of the operational amplifier408. This isolates the charge transferred to C4434. Additionally, opening switch S7432breaks the circuit between Vn the second input448i.e., Vp and non-inverting terminal440of the operational amplifier408. This isolates the charge transferred to C3436.

At time t5, clock waveform φ2d458cycles to the off state. Clock waveforms φ1452, φ1d454and φ2456remain in the off state. In response to the off state of φ2d458, switches S3414and S4416open. By delaying the opening of switches S3414and S4416until after switches S7432and S6426have been opened, and thus isolating the charges stored on C4434and C3436, the sampled signals are unaffected by the charge injections that occur after switches S6426and S7432have been opened.

At time t6, clock waveforms φ1452and φ1d454cycle to the on state while the clock waveforms φ2456and φ2d458remain in the off state. The response of the network400to the on state of φ1452and φ1d454is identical to the response to the on state at time t0as explained above. Likewise, at times subsequent to t6, network400operates in the manner explained above.

FIG. 4cillustrates the amplitude Vdiff (i.e., Vp-Vn), of the differential input signal at the first phase φ1and the second phase φ2. Since the sampling frequency is much higher than the frequency of the input signal, the amplitude of the differential input signal does not change much between φ1and φ2, as is shown inFIG. 4c.FIG. 4dillustrates the amplitudes of the differential output of the driver amplifier during φ1and φ2. Since the differential input signal is sampled with opposite polarities in the first phase of operation φ1and the second phase of operation φ2, the differential output of the driver amplifier has opposite polarities (i.e., A*Vdiff at φ1and −A*Vdiff at φ2, where A is the gain of the driver amplifier) in the first phase of operation φ1and the second phase of operation φ2. Similarly,FIG. 4eillustrates the amplitudes of the differential driver amplifier output flicker noise and offset during φ1and φ2. Since the driver amplifier flicker noise and offset are sampled with the same polarity in the first phase of operation φ1and the second phase of operation φ2, the differential driver amplifier output flicker noise and offset have the same polarity (i.e., Vbuf_noise) in the first phase of operation φ1and the second phase of operation φ2. The amplitude of the flicker noise is approximately equal in φ1and φ2, because flicker noise is a low-frequency noise. The clock frequency for the oversampling ADCs is usually much higher that the corner frequency of the flicker noise.

FIG. 5shows another embodiment of a switched capacitor sampling network500, similar to the switched capacitor sampling network400. However, the driver amplifier system504comprises a fully differential driver amplifier518having two differential inputs519and520and two differential outputs542and544. The analysis for the switched capacitor sampling network500is similar to that explained above for the switched capacitor sampling network400.

FIG. 6shows an example embodiment, wherein the switched capacitor sampling network600, similar to the switched capacitor sampling network400, is having their driver amplifiers implemented as source followers601and602. The analysis for the switched capacitor sampling network600is similar to that explained above for the switched capacitor sampling network400. The integrator implementation inFIG. 6has an advantage in comparison to the integrator inFIG. 4aandFIG. 5because it comprises a flicker noise cancellation of the internal flicker noise of the integrator. S5and S6sample the flicker noise of the integrator amplifier and differential input signal during φ1. S7and S8enable integration of the inverted differential input signal and cancellation of the integrator flicker noise during φ2. In other embodiments, the switched capacitor integrator could be implemented with other techniques for cancellation or reduction of its internal flicker noise.

FIG. 7shows a flowchart illustrating a method700for sampling a differential signal, according to one embodiment of the disclosure. The method700is described here with reference to the switched capacitor sampling network400ofFIG. 4awith a first driver amplifier Bufp418and a second driver amplifier Bufn420, however, the method can also be applied to other switched capacitor sampling networks with a fully differential driver amplifier, as illustrated inFIG. 5.

In the method700, at702, the analog differential signal405is received at the first input446and second input448of a cross-coupled switching circuit402. At704, a first portion Vp of the analog differential signal405from the first input446is sampled at a first sampling capacitance C1422in a first phase of operation and generates a first charge transfer to the first sampling capacitance C1422. At706, a second portion Vn of the analog differential signal405, comprising an inverted version of the first portion Vp of the analog differential signal405is sampled at the first sampling capacitance C1422in a second phase of operation, resulting in a second charge transfer to the first sampling capacitance C1422. At708, the first portion Vp and the second portion Vn of the analog differential signal405is provided through the driver amplifier418, prior to the first and second charge transfers to the first sampling capacitance C1422.

At710, the second portion Vn of the analog differential signal405from the second input448is sampled at the second sampling capacitance C2424in a first phase of operation and generates a first charge transfer to the second sampling capacitance C2424. At712, the first portion Vp of the analog differential signal405, comprising an inverted version of the second portion Vn of the analog differential signal405is sampled at the second sampling capacitance C2424in a second phase of operation, resulting in a second charge transfer to the second sampling capacitance C2424. At714, the second portion Vn and the first portion Vp of the analog differential signal405is provided through the driver amplifier420, prior to the first and second charge transfers to the second sampling capacitance C2424.

As highlighted above, the switched capacitor sampling network having the buffer amplifier system downstream of the cross-coupled sampling circuit has many advantages. Providing the buffer amplifier downstream of the cross-coupled sampling circuit provides reduced resistance in series with the sampling capacitance and provides an isolation of the sampling capacitors from the input signal source, reducing the load for the input source. In addition, the efficient flicker noise cancellation enables reduced design requirements for the internal flicker noise of the driver amplifier, thereby making it possible to choose relatively small input transistor dimensions in order to reduce the switched capacitive load for the input signal source. The suppression of the flicker noise enables the optimization of the driver amplifier towards low thermal noise, while maintaining small input capacitance.