Semiconductor device

A semiconductor device used in a protection circuit including a thyristor and an LCR circuit which includes a coil L, a capacitor C and a resistor R, the semiconductor device may include: a semiconductor layer in which the thyristor is provided; an insulating film provided on the semiconductor layer; and a pair of electrodes provided on the insulating film and connected to a protection target circuit, wherein at least one of the coil L, the capacitor C and the resistor R is provided in the insulating film, and the at least one of the coil L, the capacitor C and the resistor R is connected to an anode of the thyristor by a first metal wire filling a first hole provided in the insulating film.

TECHNICAL FIELD

The disclosure herein relates to a semiconductor device. The disclosure herein especially relates to a semiconductor device that is used in a protection circuit configured to prevent an overvoltage from being applied to an IC circuit and the like.

DESCRIPTION OF RELATED ART

Japanese Patent Application Publication No, 2010-50328 describes a protection circuit configured to protect a protection target circuit from an overvoltage by using a semiconductor device including a thyristor. When an overvoltage, such as a surge, is applied to a power line of the protection target circuit, the semiconductor device turns on to protect the protection target circuit from the overvoltage. Hereinbelow, Japanese Patent Application Publication No. 2010-50328 is referred to as Patent Literature 1.

SUMMARY

In Patent Literature 1, application of overvoltage to the protection target circuit is prevented by the semiconductor device (the thyristor) turning on when a high voltage is applied to the power line. However, when an overvoltage is applied to the power line at a high speed, for example in a few nanoseconds, the overvoltage may be applied to the protection target circuit before the thyristor turns on. If the protection circuit is constituted of the thyristor and an LCR circuit by arranging the LCR circuit between the thyristor and the protection target circuit, application of an overvoltage to the protection target circuit can be prevented during a period of time before the thyristor turns on. However, when the LCR circuit is prepared as a separate component from the thyristor, and the thyristor and the LCR circuit are connected by a wire, an on-operation of the thyristor may be hindered due to occurrence of parasitic capacitance and wire resistance in the wire, and the application of overvoltage to the protection target circuit may not be prevented. The disclosure herein discloses a technique of improving protection performance to protect a protection target circuit in a semiconductor device comprising a thyristor.

A semiconductor device disclosed herein may be used in a protection circuit comprising a thyristor and an LCR circuit which includes a coil L, a capacitor C and a resistor R. The semiconductor device may comprise a semiconductor layer, an insulating film, and a pair of electrodes. In the semiconductor layer, the thyristor may be provided. The insulating film may be provided on the semiconductor layer. The pair of electrodes may be provided on the insulating film and may be connected to a protection target circuit. In the protection circuit, at least one of the coil L, the capacitor C and the resistor R may be provided in the insulating film, and the at least one of the coil L, the capacitor C and the resistor R may be connected to an anode of the thyristor by a first metal wire filling a first hole provided in the insulating film.

In the above-described semiconductor device, at least one of the coil L, the capacitor C, and the resistor R is connected to the anode of the thyristor by the metal wire (the first metal wire) filling the hole provided in the insulating film. That is, the thyristor (the semiconductor layer) and the at least one of the coil L, the capacitor C, and the resistor R are laminated with the insulating film intervened therebetween, and are connected by an embedded wire (the metal wire). Conventionally, when a thyristor and an LCR circuit are connected, they are arranged on a circuit board and are connected by a bonding wire, print wiring, and the like. Therefore, there are limits to shortening a length of the wire and increasing a thickness of the wire. In the above-described semiconductor device, the wire length can be Shortened by adjusting a thickness of the insulating film. Further, the wire thickness can be thickened by enlarging the hole (the first hole) provided in the insulating film. Due to this, parasitic capacitance and wire resistance occurring between the thyristor and the LCR circuit can be reduced.

DETAILED DESCRIPTION

Some of the features characteristic to the technique disclosed herein will be listed below It should be noted that the respective technical elements are independent of one another, and are useful solely or in combinations.

A semiconductor device disclosed herein may be used as a protection circuit for a protection target circuit, or as a part of the protection circuit. The protection circuit may comprise a thyristor and an LCR circuit including a coil L, a capacitor C and a resistor R. The semiconductor device may comprise the thyristor and at least one of elements (the coil L, the capacitor C and the resistor R) constituting the LCR circuit. The semiconductor device may comprise a semiconductor layer, an insulating film, and a pair of electrodes. In the semiconductor device, the thyristor may be provided. The semiconductor layer may comprise a p-type semiconductor substrate, and an element formation layer provided on the semiconductor substrate. A material of the semiconductor substrate and the element formation layer may be silicon.

The element formation layer may comprise an n-type semiconductor region, a p-type well region provided within the n-type semiconductor region and disposed at a surface of the element formation layer, an n+-type cathode region provided at a part within the p-type well region and disposed at the surface of the element formation layer, and a p+-type anode region provided within the n-type semiconductor region at a position separated from the p-type well region and disposed at the surface of the element formation layer. The n+-type cathode region may be separated from the n-type semiconductor region by the p-type well region. The p+-type anode region may be separated from the p-type well region by the n-type semiconductor region. The thyristor may be constituted of an npn transistor which is constituted of the n+-type cathode region, the p-type well region, and the n-type semiconductor region, and a pnp transistor which is constituted of the p+-type anode region, the n-type semiconductor region, and the p-type well region. In this case, the p-type well region corresponds to a gate region of the thyristor.

The element formation layer may further comprise a p+-type contact region provided within the p-type well region at a position separated from the n+-type cathode region and disposed at the surface of the element formation layer, and an n+-type contact region provided within the n-type semiconductor region at a position separated from the p+-type anode region and disposed at the surface of the element formation layer. The n+-type cathode region and the p+-type contact region may be connected to a mutual electrode (cathode electrode). Further, the p+-type anode region and the n+-type contact region may be connected to a mutual electrode (anode electrode). An ohmic contact between the anode electrode and the n-type semiconductor region can be realized by the n+-type contact region. An ohmic contact between the cathode electrode and the p-type well region can be realized by the p+-type contact region. The anode electrode and the cathode electrode may be provided on the surface of the element formation layer so as to be separated from each other. The anode electrode may be connected to a power line extending from a power source, The cathode electrode may be connected to a grounding conductor.

For the semiconductor substrate and the element formation layer, boron (B) may be used as p-type impurities, and phosphorus (P) may be used as n-type impurities. An impurity concentration of the semiconductor substrate may be adjusted to between 1×1015to 1×1016cm−3, an impurity concentration of the n-type semiconductor region may be adjusted to between 1×1017to 1×1018cm−3, an impurity concentration of the p-type well region may be adjusted to between 1×1017to 1×1018cm−3, an impurity concentration of the n+-type cathode region may be adjusted equal to or more than 1×1019cm−3, an impurity concentration of the p+-type contact region may be adjusted equal to or more than 5×1018cm−3, an impurity concentration of the p+-type anode region may be adjusted equal. to or more than 5×1018cm−3, and an impurity concentration of the n+-type contact region may be adjusted equal to or more than 5×1018cm3.

The insulating film may be provided on the semiconductor layer (the element formation layer). As a material of the insulating film, a CVD film constituted of BPSG (Boron Phosphor Silicate Glass), TEOS-SiO2(Tetraethoxysilane-based SiO2), etc. can be used. At least one of the elements (the coil L, the capacitor C and the resistor R) constituting the LCR circuit may be provided in the insulating film. The at least one of the elements provided in the insulating film may be connected to an anode of the thyristor by a metal wire filling a hole provided in the insulating film. That is, the at least one of the elements provided in the insulating film may be connected, by a via wire, to the anode electrode which is connected to the p+-type anode region. In the insulating film, two of the elements constituting the LCR circuit may be provided, or all of the elements constituting the LCR circuit may be provided.

The pair of electrodes for connecting to the protection target circuit may be provided on the insulating film One (first electrode) of the pair of electrodes may be connected to the element(s) (the at least one of the coil L, the capacitor C and the resistor R) provided in the insulating film by a metal wire filling a hole provided in the insulating film. That is, the first electrode may be connected to the element(s) provided in the insulating film by a via wire. Further, the other one (second electrode) of the pair of electrodes may be connected to a cathode of the thyristor by a metal wire filling a hole provided in the insulating film. That is, the second electrode may be connected, by a via wire, to the cathode electrode which is connected to the n+-type cathode region. For the via wires (the metal wires), polysilicon having a high impurity concentration (e.g., impurity concentration equal to or more than 1×1019cm−3), tungsten, aluminum, and the like can be used.

The thyristor may be connected in parallel to the protection target circuit between the power line and the grounding conductor. Further, the element(s) provided in the insulating film which is provided on the semiconductor layer may be connected in parallel to the protection target circuit. The thyristor and the element(s) provided in the insulating film may be connected to the power line at upstream with respect to the protection target circuit. Due to this, when an overvoltage (such as a surge) is applied to the power line, application of the overvoltage to the protection target circuit can be prevented.

EMBODIMENTS

First Embodiment

With reference toFIGS. 1 and 2, a semiconductor device80used in a protection circuit100will be described. As shown inFIG. 1, the protection circuit100is connected in parallel to an IC circuit6between a power line10and a grounding conductor2. The IC circuit6is an example of a protection target circuit. The protection circuit100is connected to the power line10at upstream (on a power source V side) with respect to the IC circuit6. The protection circuit100comprises a capacitor C and the semiconductor device80. The semiconductor device80is connected in parallel to the capacitor C between the power line10and the grounding conductor2, and is connected to the power line10at upstream with respect to the capacitor C. The semiconductor device80comprises a thyristor (SCR), a resistor R, and a coil L.

The semiconductor device80comprises a first electrode8and a second electrode4. The first electrode8and the second electrode4are an example of a pair of electrodes. The first electrode8is connected to the IC circuit6and the capacitor C by the power line10. The second electrode4is connected to the IC circuit6and the capacitor C by the grounding conductor2. The first electrode8and the second electrode4are external electrodes of the semiconductor device80. An anode A of the thyristor is connected to the power line10, and a cathode K of the thyristor is connected to the grounding conductor2. Further, the resistor R and the coil L are connected in series to the thyristor. The power line10is connected to between the resistor R and the coil L, and the thyristor (the anode A). A current supplied from the power source V passes through the resistor R and the coil L, and is supplied to the IC circuit6.

As shown inFIG. 2, the semiconductor device80comprises a semiconductor layer50, an insulating film60provided on the semiconductor layer50, and the first electrode8and the second electrode4provided on the insulating film60. The semiconductor layer50comprises a p-type semiconductor substrate54, and an element formation layer52in which the thyristor is provided. The element formation layer52comprises an n-type semiconductor region32, a p-type well region34provided within the n-type semiconductor region32, an if n+-type cathode region36provided within the p-type well region34, a p+-type contact region38provided within the p-type well region34, a p+-type anode region48provided within the n-type semiconductor region32, and an n+-type contact region46provided within the n-type semiconductor region32.

The p-type well region34is provided at a part within the n-type semiconductor region32, and is disposed at a surface of the element formation layer52. At a portion where the p-type well region34is not provided, the n-type semiconductor region32is disposed at the surface of the element formation layer52. The n+-type cathode region36is provided at a part within the p-type well region34, and is disposed at the surface of the element formation layer52. The n+-type cathode region36is separated from the n-type semiconductor region32by the p-type well region34. The n+-type cathode region36, the p-type well region34, and the n-type semiconductor region32constitute an npn transistor.

The p+-type contact region38is provided at a part within the p-type well region34at a position separated from the n+-type cathode region36, and is disposed at the surface of the element formation layer52. A cathode electrode40is provided on the surface of the element formation layer52so as to be in contact with the n+-type cathode region36and the p+-type contact region38. The p+-type contact region38is a region for realizing ohmic contact between the cathode electrode40and the p-type well region34. The cathode electrode40is connected to the grounding conductor2(also seeFIG. 1).

The p+-type anode region48is provided at a part within the n-type semiconductor region32at a position separated from the p-type well region34, and is disposed at the surface of the element formation layer52. The p+-type anode region48is separated from the p-type well region34by the n-type semiconductor region32. The p+-type anode region48, the n-type semiconductor region32, and the p-type well region34constitute a pnp transistor. The pnp transistor (the regions48,32,34) and the npn transistor (the regions36,34,32) constitute the thyristor.

The n+-type contact region46is provided at a part within the n-type semiconductor region32at a position separated from the p+-type anode region48, and is disposed at the surface of the element formation layer52. An anode electrode44is provided on the surface of the element formation layer52so as to be in contact with the p+-type anode region48and the n+-type contact region46. The n+-type contact region46is a region for realizing ohmic contact between the anode electrode44and the n-type semiconductor region32. The anode electrode44is connected to the power line10(also seeFIG. 1).

The insulating film60is provided on the surface of the element formation layer52(the semiconductor layer50). The first electrode8and the second electrode4are provided on a surface of the insulating film60The insulating film60covers a part of the element formation layer52(a portion of the element formation layer52where the electrodes40,44are not provided) and surfaces of the electrodes40,44. A first hole65, a second hole63, and a third hole61are provided in the insulating film60. Further, a coil68is arranged in the insulating film60. The first hole65extends from a middle portion of the insulating film60to a rear surface of the insulating film60. Specifically, the first hole65extends between the coil68and the anode electrode44. The second hole63extends from the middle portion of the insulating film60to the surface of the insulating film60. The second hole63extends between the first electrode8and the coil68. The third hole61extends from the surface of the insulating film60to the rear surface thereof. The third hole61extends between the second electrode4and the cathode electrode40.

The first hole65is filled with an embedded wire70. The embedded wire70is an example of a first metal wire, The embedded wire70connects the coil68and the anode electrode44. The embedded wire70is constituted of polysilicon containing 1×1019cm−3of n-type impurities. Phosphorus is an example of the impurities contained in the embedded wire70. The coil68can be arranged in the insulating film60by using publicly known techniques. The coil68can be formed in the insulating film60by stacking a plurality of insulating sheets that have wiring patterns formed therein, and connecting the respective wiring patterns.

The second hole63is filled with an embedded wire66, The embedded wire66is an example of a second metal wire. The embedded wire66connects the first electrode8and the coil68. A material of the embedded wire66is the same as that of the embedded wire70. Further, a resistor64is provided at a middle portion of the embedded wire66. The resistor64is constituted of polysilicon that contains the impurities at a lower concentration than the embedded wire66. An impurity concentration of the resistor64is adjusted to between 1×1014cm−3to 1×1017cm−3. The embedded wire66and the resistor64are constituted of the same material (polysilicon) having different impurity concentrations. The resistor64and the coil68are connected between the first electrode8and the anode electrode44by the embedded wires66,70.

The third hole61is filled with an embedded wire62. The embedded wire62is an example of a third metal wire. The embedded wire62connects the second electrode4and the cathode electrode40. A material of the embedded wire62is the same as those of the embedded wires66,70.

Advantages of the semiconductor device80will be described. In the protection circuit100comprising the semiconductor device80, a current supplied from the power source V is supplied to the IC circuit6through the anode electrode44, the coil68, the resistor64, and the first electrode8. Due to this, when an overvoltage is applied to the power line10, application of the overvoltage to the IC circuit6before the thyristor turns on can be prevented. Further, in the semiconductor device80, the coil68and the resistor64are arranged above the thyristor, and the coil68and the resistor64are connected to the thyristor by the embedded wires66,70filling the holes63,65. Thicknesses (cross sectional areas) of the embedded wires66,70are adjustable according to sizes of the holes63,65. That is, the thicknesses of the embedded wires66,70can be easily enlarged. Further, since the thyristor, and the coil68and the resistor64are connected by the embedded wires66,70, lengths of the wires can he shortened. By using the semiconductor device80, a smaller wire resistance is achieved as compared to a conventional case in which a coil and a resistor are connected to a thyristor by a bonding wire, print wiring, and the like, and parasitic capacitance can thereby be suppressed from occurring.

Conventionally, in a plan view of a circuit board, a coil and a resistor are arranged at positions different from a position at which a thyristor on the circuit board is provided. In the semiconductor device80, in a plan view of a circuit board, the coil and the resistor arc arranged at a same position where the thyristor on the circuit board is provided. Therefore, an area of the circuit board can be made small. That is, by using the semiconductor device80, a compact circuit board can be realized. It should be noted that a size of the third hole61is also adjustable, and the cathode electrode40and the second electrode4can be connected by the wire62with a small resistance.

Further, as in a semiconductor device80ashown inFIG. 3, the resistor64may be provided at a middle portion of the embedded wire70in the first hole65. In this case, only the embedded wire66may be provided in the second hole63. The resistor64and the coil68can be arranged in this order from the anode electrode44toward the first electrode8.

In the above-described semiconductor device80, the resistor64is provided in the embedded wire66by employing a lower impurity concentration for the middle portion of the embedded wire66. However, the second hole63may be filled with an embedded wire having an even impurity concentration, in this case, the impurity concentration of the embedded wire filling the second hole63is made lower than that of the embedded wire62filling the third hole61. That is, the second hole63is tilled with a resistor. Similarly, in the semiconductor device80a, the first hole65may be filled with an embedded wire having a lower impurity concentration than the embedded wire62. Further, a commercially available coil and resistor may be arranged in the insulating film, and they may be connected by embedded wires.

Second Embodiment

With reference toFIG. 4, a semiconductor device180will be described. The semiconductor device180is a variant of the semiconductor device80a, and comprises the thyristor (SCR), the capacitor C, the resistor R, and the coil L (also seeFIG. 1). Configurations of the semiconductor device180which are identical to those of the semiconductor device80awill be denoted with the same reference signs as in the semiconductor device80a, and description thereof may be omitted.

In the semiconductor device180, a first electrode108is connected to the embedded wire66, and a second electrode104is connected to the embedded wire62. Further, an insulating film90is provided between the first electrode108and the second electrode104at an outside of the insulating film60. A thickness of the insulating film90is approximately 1 μm. A capacitor92is constituted of the first electrode108, the insulating film90, and the second electrode104. In the semiconductor device180, it can be said that the capacitor92is provided at the outside of the insulating film60. It should be noted that the technique of constituting a capacitor by providing an insulating film between a first electrode and a second electrode can be applied also in the semiconductor device80(seeFIG. 2).

While specific examples of the present invention have been described above in detail, these examples are merely illustrative and place no limitation on the scope of the patent claims. The technology described in the patent claims also encompasses various changes and modifications to the specific examples described above. The technical elements explained in the present description or drawings provide technical utility either independently or through various combinations. The present invention is not limited to the combinations described at the time the claims are filed. Further, the purpose of the examples illustrated by the present description or drawings is to satisfy multiple objectives simultaneously, and satisfying any one of those objectives gives technical utility to the present invention.