Array of cross point memory cells individually comprising a select device and a programmable device

A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. The electrode pillars and walls form spaced openings between the first lines. The openings are lined with programmable material of the memory cells being formed to less-than-fill the openings with the programmable material. Conductive upper electrode material is formed over the programmable material within remaining volume of the openings and spaced upper second lines are formed which cross the first lines elevationally over the conductive upper electrode material that is within the openings. A select device is between the lower electrode pillar and the underlying first line or is between the conductive upper electrode material and the overlying second line for the individual memory cells. Aspects of the invention include an array of cross point memory cells independent of method of manufacture.

TECHNICAL FIELD

Embodiments disclosed herein pertain to arrays of cross point memory cells and to methods of forming an array of cross point memory cells.

BACKGROUND

Memory cells may be volatile or non-volatile. Non-volatile memory cells can store data for extended periods of time including when the computer is turned off. Volatile memory dissipates and therefore requires being refreshed/rewritten, in many instances multiple times per second. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A capacitor is one type of electronic component that may be used in a memory cell. A capacitor has two electrical conductors separated by electrically insulating material. Energy as an electric field may be electrostatically stored within such material. One type of capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a memory cell. The polarization state of the ferroelectric material can be changed by application of suitable programming voltages, and remains after removal of the programming voltage (at least for a time). Each polarization state has a different charge-stored capacitance from the other, and which ideally can be used to write (i.e., store) and read a memory state without reversing the polarization state until such is desired to be reversed. Less desirable, in some memory having ferroelectric capacitors the act of reading the memory state can reverse the polarization. Accordingly, upon determining the polarization state, a re-write of the memory cell is conducted to put the memory cell into the pre-read state immediately after its determination. Regardless, a memory cell incorporating a ferroelectric capacitor ideally is non-volatile due to the bi-stable characteristics of the ferroelectric material that forms a part of the capacitor. One type of memory cell has a select device electrically coupled in series with a ferroelectric capacitor.

Another type of non-volatile memory is phase change memory. Such memory uses a reversibly programmable material that has the property of switching between two different phases, for example between an amorphous disorderly phase and a crystalline or polycrystalline orderly phase. The two phases may be associated with resistivities of significantly different values. Presently, typical phase change materials are chalcogenides, although other materials may be developed. With chalcogenides, the resistivity may vary by two or more orders of magnitude when the material passes between the amorphous (more resistive) phase and the crystalline (more conductive) phase. Phase change can be obtained by locally increasing the temperature of the chalcogenide. Below 150° C., both phases are stable. Starting from an amorphous state and rising to temperature above about 400° C., a rapid nucleation of crystallites may occur and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change to become crystalline. Reversion to the amorphous state can result by raising the temperature above the melting temperature (about 600° C.) followed by cooling.

Other reversibly programmable materials for memory cells exist and undoubtedly will be developed.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass an array of cross point memory cells and methods of forming an array of cross point memory cells.FIGS. 1 and 2show a small portion of a substrate construction8comprising an array10of individual cross point memory cells12that has been fabricated relative to a base substrate11. Substrate11may comprise any one or more of conductive (i.e., electrically herein), semiconductive, or insulative/insulator (i.e., electrically herein) materials. Various materials have been formed elevationally over base substrate11. In this document, “elevational”, “upper”, “lower”, “top”, “bottom”, and “beneath” are generally with reference to the vertical direction. “Horizontal” refers to a general direction along a primary surface relative to which the substrate is processed during fabrication, and vertical is a direction generally orthogonal thereto. Further, “vertical” and “horizontal” as used herein are generally perpendicular directions relative one another and independent of orientation of the substrate in three-dimensional space. Example outlines of immediately adjacent individual memory cells12are shown as being elevationally staggered for ease of depiction in the Figures where, for example, such memory cells in some embodiments overlap and/or share some component(s).

Materials may be aside, elevationally inward, or elevationally outward of theFIG. 1—depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within fragment11. Control and/or other peripheral circuitry for operating components within the memory array may also be fabricated, and may or may not wholly or partially be within a memory array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. As used in this document, a “sub-array” may also be considered as an array. Regardless, any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Further, unless otherwise stated, each material may be formed using any suitable or yet-to-be-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.

Array10comprises spaced lower first lines14and spaced upper second lines16which cross first lines14, with individual memory cells12being between first lines14and second lines16where such cross. Reference to “first” and “second” with respect to different components herein is only for convenience in description in referring to different components. Accordingly, “first” and “second” may be interchanged independent of relative position within the finished circuit construction and independent of sequence in fabrication. Lines14and16comprise conductive material, with examples being elemental metals, a mixture or alloy of two or more elemental metals, conductive metal compounds, and conductively-doped semiconductive materials. Lines14and16may be of the same composition or of different compositions relative one another. In one embodiment, first lines14and second lines16angle orthogonally relative one another. In one embodiment, lines14are access or word lines and lines16are sense or bit lines. Dielectric material15is between individual first lines14.

Individual memory cells12comprise a select device18and a programmable device20in series (i.e., electrical) with each other. Select device18is proximate (e.g., more so than is the programmable device) and electrically coupled to one of first lines14or one of second lines16. Programmable device20is proximate (e.g., more so than is the select device) and electrically coupled to one of the other of a first line14or a second line16. In one embodiment, select device18is directly electrically coupled to the one first or second line and in one embodiment programmable device20is directly electrically coupled to the one of the other first or second line. In this document, two electronic devices or components are “electrically coupled” to one another if in normal operation electric current is capable of continuously flowing from one to the other, and does so predominately by movement of subatomic positive and/or negative charges when such are sufficiently generated. Another electronic component may be between and electrically coupled to the two electrically coupled electronic components or devices. In contrast, when two electronic components or devices are referred to as being “directly electrically coupled”, no intervening electronic component is between the two directly electrically coupled components or devices. In theFIG. 1embodiment, select device18is proximate and directly electrically coupled to one of first lines14and programmable device20is proximate and directly electrically coupled to one of second lines16. Any existing or yet-to-be developed select devices may be used, for example a junction device or a diode. Example diodes include PN diodes, PIN diodes, Schottky diodes, Zener diodes, avalanche diodes, tunnel diodes, diodes having more than three materials, etc. As an additional example, select device18may be a junction bipolar transistor. Select device18may include an elevationally outer and/or elevationally inner conductive material as a part thereof (not specifically shown).

Individual programmable devices20comprise a first electrode22in the form of a conductive pillar elevationally over one of first lines14. In this document, a “pillar electrode” and a “conductive pillar” is a conductive structure that is of radially continuous conductive material(s) longitudinally along at least a majority of its length. First pillar electrode22comprises a top24and sidewalls26(FIG. 2). Any suitable conductive material(s) may be used for first pillar electrodes22, with TiN being one example. Programmable material28is laterally outward of opposing sidewalls26of first pillar electrode22, in one embodiment is elevationally over pillar top24, and in one embodiment comprises a continuous layer extending over opposing sidewalls26and top24of individual first pillar electrodes22. Any existing or yet-to-be-developed programmable material may be used, for example those described in the “Background” section above.

Programmable device20includes a second electrode30outward of the programmable material28that is laterally over opposing sidewalls26of first pillar electrode22, and in one embodiment is elevationally over first pillar electrode top24. Second electrode30may be of the same or different composition from that of first pillar electrode22, and may be of the same or different composition from second lines16. In the depicted example, second electrode30is shown to be of different conductive composition than second lines16. Regardless, second electrodes30may be considered as part of or an elevational extension of a conductive line16. In one embodiment and as shown, the second electrodes30of immediately adjacent memory cells12along individual second lines16are directly electrically coupled to one another. For example in one embodiment, second electrodes30are shown as comprising conductive pillars31, with immediately adjacent memory cells12sharing one of conductive pillars31. Regardless, in one embodiment programmable material28is beneath second electrode30between two immediately adjacent first lines14. Further in one embodiment, programmable material28is continuous over multiple tops24and sidewalls26of multiple first pillar electrodes22, and beneath multiple second electrodes30between immediately adjacent first lines14. In one embodiment, first pillar electrode22has a maximum conductive material width that is greater than that of conductive pillar31laterally proximate the programmable material that is laterally outward of one of opposing sidewalls26of first pillar electrode22. In one embodiment, first pillar electrode22has a maximum conductive material volume that is greater than that of conductive pillar31. Regardless, in one embodiment programmable device20is a ferroelectric capacitor with programmable material28thereby comprising ferroelectric material.

The first pillar electrode or the second electrode is electrically coupled to the select device (in one embodiment directly electrically coupled) and the other of the first pillar electrode or the second electrode is electrically coupled (in one embodiment directly electrically coupled) to one of the first or second lines. In the depicted embodiment where select device18is proximate and electrically coupled to a first line14, first pillar electrode22is elevationally over and electrically coupled to select device18. Second electrode30is electrically coupled to one of second lines16, and again may be considered as comprising a part thereof. In one embodiment and as shown, second electrode30is of an upside-down U-shape33in cross-section along its overlying second line16, for example as readily viewable inFIG. 2(only one U-shape shape33being shown for one second electrode30of one memory cell12inFIG. 2for clarity).

FIGS. 1 and 2show an example embodiment where second lines16may have been formed in a self-aligned manner within trenches that were also formed in a self-aligned manner in conductive material of second electrodes30, and for example as will be described below. Thereby, and for example where second lines16and second electrodes30are of different conductive compositions, material of second electrodes30is shown extending along sidewalls of second lines16. Additionally as an example and as shown, programmable material28also extends along sidewalls of second lines16laterally outward of the second electrode conductive material. In this document, “self-aligned” means a technique whereby at least a lateral surface of a structure is defined by deposition of material against a sidewall of a previously patterned structure. Dielectric material17is between immediately adjacent second lines16.

FIG. 3shows an example alternate embodiment construction8aof an array10athat may be produced, for example, from subtractive patterning of conductive material of second lines16a. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “a”. In theFIG. 3example, programmable material28and conductive material of second electrodes30do not extend along sidewalls of second lines16, and pillar electrodes22aare shown taller than pillar electrodes22(FIGS. 1 and 2). Any other attribute(s) or aspect(s) as described above and/or shown inFIGS. 1 and 2may be used in theFIG. 3embodiments.

FIG. 4shows another alternate embodiment construction8bto that shown inFIG. 3. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “b”. In array10b, a memory cell12bhas select device18proximate (e.g., more so than is the programmable device) and electrically coupled to one of second lines16. Programmable device20is proximate (e.g., more so than is the select device) and electrically coupled to one of first lines14. Accordingly, first pillar electrode22ais elevationally over, proximate, and electrically coupled (e.g., directly) to one first line14and second electrode30is electrically coupled (e.g., directly) to one select device18. Construction analogous to that shown inFIG. 4can also of course be used in the construction ofFIGS. 1 and 2whereby the select device is provided between a second line16aand a second electrode30(not shown). Any other attribute(s) or aspect(s) as described above and/or shown inFIGS. 1-3may be used in theFIG. 4embodiments.

Embodiments of the invention encompass methods of forming an array of cross point memory cells and example embodiments of which are next described initially with reference toFIGS. 5-14. Like numerals from the above-described embodiments for like materials of construction have been used where appropriate, with some construction differences being indicated with different numerals.FIGS. 5-14show an example embodiment for fabrication of theFIGS. 1 and 2array (bottom-formed select device) from a predecessor construction8, although a top-formed select device method may alternately be used.FIG. 5shows an example wherein select device material18has been patterned commensurate with the patterning of first lines14, and dielectric material15is between first lines14. Only some of the thickness of select device material18may be patterned depending on the type of select devices being formed. Any of the depicted patternings herein may use masking steps, for example photolithographic or other patterning and, regardless, which may use pitch multiplication.

Referring toFIG. 6, dielectric material50has been formed over the substrate ofFIG. 5, and has been patterned and used as a mask to form rails of material50that run along the second line-direction and to complete patterning of select device material18. In one embodiment, dielectric material50is of different composition (e.g., silicon dioxide) from that of dielectric material15(e.g., silicon nitride), and an etch of select device material18is conducted selectively relative to dielectric materials50and15. In this document, a selective etch or removal is an etch or removal where one material is removed relative to another stated material at a rate of at least 1.5:1.

Referring toFIG. 7, dielectric material17has been deposited to fill space between the rails of material50inFIG. 6, with material17then being planarized back at least to elevationally outermost surfaces of material50. In one embodiment, materials50and17are of different compositions relative one another, for example with material50comprising silicon dioxide and material17comprising silicon nitride.

Referring toFIG. 8, mask lines53have been formed over the substrate ofFIG. 7elevationally over the spaces between first lines14, and then unmasked material50has been anisotropically etched selectively relative to mask lines53, dielectric material17, and exposed select device material18. Mask lines53are shown as having been removed inFIG. 9. Such processing results in the formation of first spaced openings55longitudinally along and elevationally over spaced lower first lines14(regardless of presence of select device material18). First openings55are between first opposing walls56(e.g., material50) that are between first lines14and are between second opposing walls58(e.g., material17) that are along and cross elevationally over first lines14.

Referring toFIG. 10, conductive lower electrode pillar material22has been formed within individual of first openings55for individual of the memory cells.

Referring toFIG. 11, and in one embodiment, conductive lower electrode pillar material22has been elevationally recessed within first openings55, for example by a timed etch of pillar material22conducted selectively relative to material(s) of walls56and58.

Referring toFIG. 12, first opposing walls56(not shown) have been removed to form second spaced openings60between first lines14, with second openings60being between second opposing walls58and pillar electrodes22. In one embodiment where, for example, walls56and58are of different compositions, such may be conducted by a selective etch of walls56(not shown) relative to walls58and conductive material of pillars22. Where pillar electrodes22are elevationally recessed, such recessing may be conducted before and/or after removing first opposing walls56.

The above processing is but one example method of forming spaced lower electrode pillars22for individual of the memory cells being formed along and elevationally over spaced lower first lines14. Walls58cross elevationally over first lines14and between pillar electrodes22that are along first lines14, with pillars22and walls58forming spaced openings60between first lines14. Other techniques may be used, and with or without any recessing of the pillar electrodes.

Referring toFIG. 13, openings60have been lined with programmable material28to less-than-fill openings60with programmable material28, and regardless of whether first openings are ever formed. In one embodiment and as shown, programmable material28is formed over pillar electrode tops24and remains in a finished construction of the array (e.g.,FIGS. 1 and 2).

Referring toFIG. 14, conductive upper electrode material30has been formed over programmable material28within remaining volume of openings60, in one embodiment to fill all of the remaining volume of openings60, and in one embodiment as shown to overfill all of the remaining volume of openings60, thereby forming conductive pillars31of second electrodes30. Accordingly and in one embodiment as shown, conductive upper electrode material30has also been formed elevationally over programmable material28that is over conductive pillar tops24, and remains in the finished circuitry construction. Upper second line material16can then be deposited and planarized back at least to elevationally outermost surfaces of walls58, for example to produce a construction as shown inFIGS. 1 and 2(e.g., in a self-aligned manner). Alternately as an example, second electrode material30and conductive lines16may be deposited as a single, continuous, homogenous conductive material composition, with material16thereby forming or constituting part of second electrodes30(not shown) (e.g., also in a self-aligned manner). Regardless, in one embodiment masking steps are used in the formation of the array of cross point memory cells.FIGS. 5-14(includingFIGS. 1 and 2) show an example method of forming all of spaced first lines14, pillar electrodes22, spaced second lines16, and select devices18(and in one embodiment first openings55) using only three masking steps, namely a masking step to produce theFIG. 5construction, a masking step to produce theFIG. 6construction, and the masking step ofFIG. 8.

An alternate example embodiment method for producing the construction ofFIG. 3is described with reference toFIGS. 15 and 16with respect to a predecessor construction8a. Like numerals from the above-described method embodiments have been used where appropriate, with some construction differences being indicated with the suffix “a”.FIG. 15shows processing conducted immediately after the processing that produced the substrate ofFIG. 10in the above-described method embodiments. Specifically, first opposing walls56(not shown) have been removed to form openings60a(e.g., without recessing of pillar electrodes22a).

Referring toFIG. 16, programmable material28has been deposited to line openings60ato less-than-fill such openings, followed by formation of upper electrode material30within remaining volume of openings60a. Conductive material16for the second lines has been deposited and patterned there-over. Such may then be used as masking during an anisotropic etch of outer electrode material30to isolate it along the second line-direction to produce a construction analogous to that shown inFIG. 3. Again as an example, the second line material16and the outer conductive electrode material30may alternately be deposited as a single composition deposition (or collectively as multiple compositions) and then collectively patterned together.

A select device is ultimately provided between the conductive lower electrode material and the underlying first line or provided between the conductive upper electrode material and the overlying second line for the individual memory cells. Any other attribute(s) or aspect(s) as described above and/or shown inFIGS. 1-4of the structure embodiments may be used in the method embodiments.

CONCLUSION

In some embodiments, a method of forming an array of cross point memory cells comprises forming spaced lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. The electrode pillars and walls form spaced openings between the first lines. The openings are lined with programmable material of the memory cells being formed to less-than-fill the openings with the programmable material. Conductive upper electrode material is formed over the programmable material within remaining volume of the openings and spaced upper second lines are formed which cross the first lines elevationally over the conductive upper electrode material that is within the openings. A select device is between the lower electrode pillar and the underlying first line or is between the conductive upper electrode material and the overlying second line for the individual memory cells.

In some embodiments, a method of forming an array of cross point memory cells comprises forming first spaced openings longitudinally along and elevationally over spaced lower first lines. The first openings are between first opposing walls that are between the first lines and are between second opposing walls that are along and elevationally over the first lines. Lower electrode pillars for individual of the memory cells are formed within individual of the first openings. The first opposing walls are removed to form second spaced openings between the first lines. The second openings are between the second opposing walls and the electrode pillars. The second openings are lined with programmable material of the memory cells being formed to less-than-fill the second openings with the programmable material. Conductive upper electrode material is formed over the programmable material within remaining volume of the second openings and spaced upper second lines are formed which cross the first lines elevationally over the conductive upper electrode material within the second openings. A select device is between the lower electrode pillars and the underlying first line or is provided between the conductive upper electrode material and the overlying second line for the individual memory cells.

In some embodiments, an array of cross point memory cells comprises spaced lower first lines, spaced upper second lines which cross the first lines, and an individual memory cell between the first lines and the second lines where such cross. The individual memory cells comprise a select device and a programmable device in series with each other. The select device is proximate and electrically coupled to one of the first or second lines. The programmable device is proximate and electrically coupled to one of the other of the first or second lines. The programmable device comprises a first pillar electrode elevationally over the one of the first lines. The first pillar electrode comprises a top and opposing sidewalls. Programmable material is laterally outward of the opposing sidewalls of the first pillar electrode. A second electrode is outward of the programmable material laterally over the opposing sidewalls of the first pillar electrode. One of the first pillar electrode or the second electrode is electrically coupled to the select device. The other of the first pillar electrode or the second electrode is electrically coupled to the one of the other of the first or second lines.

In some embodiments, an array of memory cells comprises spaced lower first lines, spaced upper second lines which cross the first lines, and an individual memory cell between the first lines and the second lines where such cross. The individual memory cells comprise a select device and a programmable device in series with each other. The select device is proximate and directly electrically coupled to one of the first lines. The programmable device is proximate and directly electrically coupled to one of the second lines. The programmable device comprises a first pillar electrode elevationally over and directly electrically coupled to the select device. The first pillar electrode comprises a top and opposing sidewalls. Programmable material is laterally outward of the opposing sidewalls and elevationally over the top of the first pillar electrode. A second electrode is outward of the programmable material laterally over the opposing sidewalls of the first pillar electrode. The second electrode is directly electrically coupled to the one second line.

In some embodiments, an array of memory cells comprises spaced lower first lines, spaced upper second lines which cross the first lines, and an individual memory cell between the first lines and the second lines where such cross. The individual memory cells comprise a select device and a programmable device in series with each other. The select device is proximate and electrically directly coupled to one of the second lines. The programmable device is proximate and directly electrically coupled to one of the first lines. The programmable device comprises a first pillar electrode elevationally over and directly electrically coupled to the one first line. The first pillar electrode comprises a top and opposing sidewalls. Programmable material is laterally outward of the opposing sidewalls and elevationally over the top of the first pillar electrode. A second electrode is outward of the programmable material laterally over the opposing sidewalls of the first pillar electrode. The second electrode is directly electrically coupled to the select device.