Operational amplifier integrator

An integrator circuit comprises an operational amplifier which has a transistor stage (1) with an input terminal (4) and an output terminal(3), a feedback capacitor (2) connected between the input terminal (4) and the output terminal (3), and a resistor (5) connected to the input terminal (4), and also has an additional circuit branch (20) comprising a second capacitor (22) and a second resistor (25) connected in series one with the other and connected between the output terminal (3) of the transistor stage (1) and voltage comprising the inverted input voltage to the integrator circuit. Preferably two additional circuit branches (320, 320′) are provided. One may be connected between the non-inverting or positive output terminal (33) of the transistor stage (1) and the inverting or negative input of the integrator. The other circuit may be connected between the negative output terminal (37) of the transistor stage (1) and the positive input of the integrator. This is particularly useful for balanced amplifier topology. The invention finds particular application in the first filter stage (integrator) in a sigma delta analog to digital conversion circuits and provide an improved operational amplifier integrator and particularly helps in compensating for a right halfplane zero.

The present invention relates to an operational amplifier (op amp) integrator.

It is known to construct integrator circuits from op amps by connecting a resistor to the input of a transistor circuit and using a capacitor as a feedback element. The ideal integrator has infinite gain and only a single pole when the frequency of the applied signal is zero. However, practical integrator circuits based on a transconductance stage have a zero in the right halfplane when the frequency of the applied signal is equal to the feedback capacitance divided by the transconductance of the transistor.

It is an object of the present invention to provide an improved operational amplifier integrator and particularly to compensate for the right halfplane zero.

According to the present invention there is provided an integrator circuit comprising:a transistors stagea feedback capacitor connected between the input and the output of the transistor stage;a resistor connected to the input of the transistor stage;characterised by an additional circuit branch comprising:a second capacitor and a second resistor connected in series one with the other and connected between the output of the transistor stage and the inverted input to the integrator circuit.

Preferably two additional circuit branches are provided: one may be connected between the positive input and output of the transistor stage and one connected between the negative input and output. This is particularly useful for balanced amplifier topology. The transistor is an invertor and thus positive input voltages provide negative output voltages and vice versa.

The invention finds particular application in the first filter stage (integrator) in a sigma delta analog to digital conversion circuit. This first filter stage is very hard to design.

InFIG. 1a prior art op amp integrator circuit (transconductance stage) is shown comprising, as is well known to a person skilled in the art, a transistor stage1having a tranconductance gmand an internal voltage V+. A feedback capacitor2of value C is connected between a inverting output terminal3of the transistor and its non-inverting input terminal4. A resistor5of value R is also connected to the non-inverting input terminal4to buffer the input voltage Vin. The inverting input terminal6is connected to ground. The voltage at the non-inverting output3of the transistor stage1is Vout.

The current to the feedback capacitor2is I2and this is given by the voltage across the capacitor2divided by the total impedence presented by the capacitor2and the resistor5, and is given by equation1inFIG. 5. The current flowing through the transistor1to ground is I1as indicated and this is given by the voltage V+through the transistor stage1multiplied by its transconductance gm, as shown by equation 2 inFIG. 5. The internal voltage V+of transistor stage1is given by equation 3.

Since the total current must be preserved in the circuit then the sum of the currents I2and I1must be zero, as indicated in equation 4. Thus, substituting equations 1 and 2 in equation 4 results in equation 5. The terms are rearranged in equation 6 showing that there is a zero in the right half plane. This is undesirable.

This zero can be compensated by the extra circuit branch which will be evident from a comparison of the known circuit ofFIG. 1with the new circuit ofFIG. 2. The extra circuit branch20has a current I3and comprises a second capacitor22and a second resistor25connected in series between an inverted input voltage −Vinand the non-inverting output node3of the transistor stage1.

The equations 7 to 13 inFIG. 6illustrate how the extra circuit branch20compensates for the zero in the right half plane.

Equation 7 is the same as Equation 1 inFIG. 5and gives the value of the current I2in the feedback branch comprising capacitor2. Equation 8 gives the current I3in the xtra circuit branch20, and equation 9 sums these two currents.

In equation 10 the formula for the internal voltage V+in the transistor stage1is set out and this leads to equation 11, giving the current I1through the transistor stage1.

Equation 12 assumes that the current in the three branches must cancel out, ie that the three currents add up to zero, and equation 13 then effectively sums the currents I1, I2and I3given by equations 11, 7 and 8 respectively.

In equation 14 the terms are simplified to give an equation for the ratio of the output voltage to the input voltage. As can be seen from a comparison of equation 14 giving this ratio for the new circuit ofFIG. 2, with the equation6giving the ratio for the known circuit ofFIG. 1, the new circuit compensates for the zero in the right halfplane, and this compensation is not dependent on the characteristic of the amplifier.

FIG. 3illustrates an op amp integrator using balanced amplifier topology, which is well known to persons skilled in the art. The bias amplifier is a transconductance so that a positive input voltage leads to a current sink at the output and hence a negative voltage at the output. The circuit is essentially the same as that inFIG. 2but the circuit elements are repeated on the other side of the transistor stage31essentially in mirror image. Thus a first input voltage Vinis connected via a first input resistor35ato a first input terminal34of transistor stage31. A first feedback capacitor32ais connected between the first input terminal34and a first output terminal33at which a first output voltage Voutappears.

An negative input voltage −Vinis connected via a second input resistor35bto a second input terminal36of transistor stage31. A second feedback capacitor32bis connected between the second input terminal36and the second output terminal37at which a negative output voltage −Voutappears.

Two extra circuit branches, each comprising a capacitor and a resistor in series, are provided. A first extra circuit branch320acomprises a capacitor322aand a resistor325a. This connects the negative input voltage −Vinto the first output terminal33at which the positive output voltage Voutappears. A second extra circuit branch320bcomprises a capacitor322band a resistor325b. This connects the positive input voltage Vinto the output terminal37at which the negative output voltage −Voutappears.

InFIG. 4a circuit diagram is presented wherein the invention is applied to the first stage of a sigma delta analog to digital convertor. This circuit comprises the circuit elements shown inFIG. 3and denoted by the same reference symbols and some additional resistors and output voltage lines. The additional resistors have a different value R2to the resistors R1shown in the previous figures. Each is connected between respective resistors R1and capacitors C and an additional output voltage line. Thus resistor41connects resistor325ato analog output voltage line45on which the positive analog voltage VDACappears. Resistor42connects input terminal34of transistor stage31to output line45(VDAC).

Likewise resistor43connects resistor325bto analog output voltage line46on which a negative analog voltage −VDACappears. Resistor44connects input terminal36of transistor stage31to the inverting analog output line46(−VDAC).