Resistance change memory and manufacturing method thereof

According to one embodiment, a resistance-change memory of embodiment includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit. The cell unit is provided at an intersection of the first interconnect line and the second interconnect line. The cell unit includes a non-ohmic element having a silicide layer on at least one of first and second ends thereof, and a memory element to store data in accordance with a reversible change in a resistance state. The silicide layer includes a 3d transition metal element which combines with an Si element to form silicide and which has a first atomic radius, and at least one kind of an additional element having a second atomic radius greater than the first atomic radius.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2009-272628, filed Nov. 30, 2009; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a resistance change memory and a manufacturing method thereof.

BACKGROUND

Recently, as next-generation nonvolatile semiconductor memories, resistance change memories have been attracting attention, such as a resistive RAM (ReRAM) in which a variable resistive element serves as a memory element, and a phase change RAM (PCRAM) in which a phase change element serves as a memory element.

These resistance change memories are characterized in that a memory cell array is a cross-point type and a higher memory capacity is enabled by three-dimensional integration, and also characterized by being capable of the same high-speed operation as that of a DRAM.

If such a resistance change memory is put to practice use, a NAND flash memory serving as a file memory and a DRAM serving as a work memory, for example, can be replaced with the resistance change memories.

There are, however, challenges to solve in putting the resistance change memory to practice use. One of these challenges concerns the material (e.g., silicide) used for the resistance change memory.

Jpn. Pat. Appln. KOKAI Publication No. 2005-019943 discloses a technique associated with nickel silicide to which other elements are added.

However, the use of silicide that takes the structure and manufacturing process of the resistance change memory is desired.

DETAILED DESCRIPTION

Hereinafter, an embodiment of embodiments will be described in detail with reference to the drawings. In the following explanation, elements having the same function and configuration are provided with the same signs and are repeatedly described when necessary.

In general, according to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction; and a cell unit. The cell unit is provided at an intersection of the first interconnect line and the second interconnect line. The cell unit includes a non-ohmic element having a silicide layer on at least one of first and second ends thereof, and a memory element to store data in accordance with a reversible change in a resistance state. The silicide layer includes a 3d transition metal element which combines with an Si element to form silicide and which has a first atomic radius, and at least one kind of an additional element having a second atomic radius greater than the first atomic radius.

The embodiment is directed to a resistance change memory in which a variable resistive element or a phase change element serves as a memory element.

EMBODIMENT

Basic Example

A resistance change memory according to an embodiment of the embodiment is described withFIG. 1toFIG. 3.

FIG. 1shows essential parts of the resistance change memory.

A resistance change memory (e.g., chip)1has a memory cell array2.

A first control circuit3is disposed at one end of the first direction of memory cell array2, and a second control circuit4is disposed at the other end of the second direction that intersects with the first direction.

The first control circuit3selects a row of the memory cell array2on the basis of, for example, a row address signal. Moreover, the second control circuit4selects a column of the memory cell array2on the basis of, for example, a column address signal.

The first and second control circuit3,4control writing, erasing and reading of data in a memory element within memory cell array2.

Here, in the resistance change memory1, for example, a write is referred to as a set, and an erasure is referred to as a reset. A resistance value in a set state has only to be different from a resistance value in a reset state, and whether the resistance value in the set state is higher or lower makes no difference.

Moreover, if one of a plurality of levels of resistance values that can be marked by the memory element can be selectively written in a set operation, a multilevel resistance change memory in which one memory element stores multilevel data can be obtained.

A controller5supplies a control signal and data to the resistance change memory1. The control signal is input to a command/interface circuit6, and data is input to a data input/output buffer7. The controller5may be disposed in the chip1or may be disposed in a chip (host device) different from the chip1.

The command/interface circuit6judges in accordance with the control signal whether data from the controller5is command data. When the data is command data, the data is transferred from the data input/output buffer7to a state machine8.

The state machine8manages the operation of the resistance change memory1on the basis of the command data. For example, the state machine8manages the set/reset operations and read operation on the basis of command data from the controller5. The controller5can receive status information managed by the state machine8, and judge the result of the operation in the resistance change memory1.

In the set/reset operations and read operation, the controller5supplies an address signal to the resistance change memory1. The address signal is input to the first and second control circuits3,4via the address buffer9.

A potential supplying circuit10outputs, at a predetermined timing, a voltage pulse or current pulse necessary for, for example, the set/reset operations and read operation in accordance with an instruction from the state machine8. The potential supplying circuit10includes a pulse generator10A.

FIG. 2is a bird's-eye view showing the structure of the memory cell array. The memory cell array shown inFIG. 2has a cross-point type structure.

The cross-point type memory cell array2is disposed on a substrate11. The substrate11is a semiconductor substrate (e.g., a silicon substrate), or an interlayer insulating film on a semiconductor substrate. In addition, when the substrate11is an interlayer insulating film, a circuit that uses, for example, a field effect transistor may be formed on the surface of a semiconductor substrate under the cross-point type memory cell array2.

The cross-point type memory cell array2is configured by, for example, a stack structure of a plurality of memory cell arrays (also referred to as memory cell layers).

FIG. 2shows, by way of example, the case where the cross-point type memory cell array2is composed of four memory cell arrays M1, M2, M3, M4that are stacked in the third direction (a direction perpendicular to the main plane of substrate11). The number of memory cell arrays stacked has only to be two or more. In addition, the cross-point type memory cell array2may be configured by one memory cell array. Alternatively, an insulating film may be provided between two memory cell arrays stacked, and the two memory cell arrays may be electrically separated by the insulating film.

Thus, when the plurality of memory cell arrays M1, M2, M3, M4are stacked, the address signal includes, for example, a memory cell array selection signal, a row address signal and a column address signal. The first and second control circuit3,4select one of the stacked memory cell arrays in accordance with, for example, the memory cell array selection signal. The first and second control circuit3,4can write/erase/read data in one of the stacked memory cell arrays, or can simultaneously write/erase/read data in two or more or all of the stacked memory cell arrays.

Memory cell array M1is composed of a plurality of cell units CU1arrayed in the first and second directions. Similarly, the memory cell array M2is composed of a plurality of arrayed cell units CU2, memory cell array M3is composed of a plurality of arrayed cell units CU3, and memory cell array M4is composed of a plurality of arrayed cell units CU4.

Each of cell units CU1, CU2, CU3, CU4is composed of a memory element and a non-ohmic element that are connected in series.

The odd interconnect lines from the side of substrate11, that is, interconnect lines L1(j−1), L1(j), L1(j+1), interconnect lines L3(j−1), L3(j), L3(j+1) and interconnect lines L5(j−1), L5(j), L5(j+1) extend in the second direction.

The even interconnect lines from the side of substrate11, that is, interconnect lines L2(i−1), L2(i), L2(i+1) and interconnect lines L4(i−1), L4(i), L4(i+1) extend in the first direction.

These interconnect lines are used as word lines or bit lines. Here, interconnect lines L1(j−1), L1(j), L1(j+1), L3(j−1), L3(j), L3(j+1), L5(j−1), L5(j), L5(j+1) that extend in the second direction intersect with interconnect lines L2(i−1), L2(i), L2(i+1), L4(i−1), L4(i), L4(i+1) that extend in the first direction.

Lowermost first memory cell array M1is disposed between first interconnect lines L1(j−1), L1(j), L1(j+1) and second interconnect lines L2(i−1), L2(i), L2(i+1). In the set/reset operations and read operation for the memory cell array M1, either interconnect lines L1(j−1), L1(j), L1(j+1) or interconnect lines L2(i−1), L2(i), L2(i+1) are used as word lines, and the other interconnect lines are used as bit lines.

The memory cell array M2is disposed between second interconnect lines L2(i−1), L2(i), L2(i+1) and third interconnect lines L3(j−1), L3(j), L3(j+1). In the set/reset operations and read operation for the memory cell array M2, either interconnect lines L2(i−1), L2(i), L2(i+1) or interconnect lines L3(j−1), L3(j), L3(j+1) are used as word lines, and the other interconnect lines are used as bit lines.

The memory cell array M3is disposed between third interconnect lines L3(j−1), L3(j), L3(j+1) and fourth interconnect lines L4(i−1), L4(i), L4(i+1). In the set/reset operations and read operation for the memory cell array M3, either interconnect lines L3(j−1), L3(j), L3(j+1) or interconnect lines L4(i−1), L4(i), L4(i+1) are used as word lines, and the other interconnect lines are used as bit lines.

The memory cell array M4is disposed between fourth interconnect lines L4(i−1), L4(i), L4(i+1) and fifth interconnect lines L5(j−1), L5(j), L5(j+1). In the set/reset operations and read operation for the memory cell array M4, either interconnect lines L4(i−1), L4(i), L4(i+1) or interconnect lines L5(j−1), L5(j), L5(j+1) are used as word lines, and the other interconnect lines are used as bit lines.

FIG. 3is a bird's-eye view schematically showing the structure of one cell unit.

In the cross-point type memory cell array2, a current is only passed through a selected memory element, a memory element20and a non-ohmic element30are connected in series between two interconnect lines (the word line and the bit line).

In the cell unit CU inFIG. 3, the memory element20is stacked on the non-ohmic element30. However, the structure of the cell unit CU shown inFIG. 3is only one example, and the non-ohmic element30may be stacked on the memory element20.

In the cross-point type memory cell array, a stack composed of the memory element20and the non-ohmic element30is disposed as one cell unit CU in a part where two interconnect lines60,65intersect with each other. In the stacking direction (third direction), the cell unit CU is interposed between two interconnect lines60,65. Here, interconnect lines60,65correspond to two successively stacked interconnect lines inFIG. 2, such as interconnect line L1(j) and interconnect line L2(i), or interconnect line L2(i) and interconnect line L3(j) or interconnect line L3(j) and interconnect line L4(i).

The memory element20is a variable resistive element or a phase change element. Here, the term variable resistive element means an element made of a material with a resistance value that changes upon application of, for example, a voltage, a current or heat. The term phase change element means an element made of a material having a physicality (impedance) such as a resistance value or capacitance that changes due to a phase change by an application of a voltage, a current or heat.

In accordance with the above definition, the variable resistive element includes the phase change element.

In the embodiment of the present invention, the variable resistive element is mainly made of, for example, a metal oxide (e.g., a binary or ternary metal oxide), a metal compound, a chalcogenide material (e.g., Ge—Sb—Te, In—Sb—Te), organic matter, carbon, or carbon nanotube.

In addition, the resistance value of a magnetoresistive effect element used for a magnetoresistive RAM (MRAM) changes when the relative directions of the magnetizations of two magnetic layers constituting this element change. In the present embodiment, a magnetoresistive effect element such as a magnetic tunnel junction (MTJ) element is also included in the variable resistive element.

As a means of changing the resistance value of the memory element20, there are an operation called a bipolar operation and an operation called a unipolar operation. In the bipolar operation, the polarity of a voltage applied to the memory element20is changed to cause a reversible change in the resistance value of the memory element20between at least a first value (first level) and a second value (second level). In the unipolar operation, one or both of the intensity and application time (pulse width) of a voltage is controlled without changing the polarity of the voltage applied to the memory element to cause a reversible change in the resistance value of the memory element between at least the first value and the second value.

The bipolar operation is used for a memory such as a spin injection type MRAM which requires bi-directional passage of a current through the memory element during writing.

The non-ohmic element30is an element which does not have linearity in its input/output characteristics, that is, an element which has non-ohmic characteristics.

A rectification element such as a PN junction diode, a PIN junction diode, a Schottky diode or a metal-insulator-semiconductor (MIS) diode is used for the non-ohmic element30. The term PN junction diode means a diode in which a P-type semiconductor layer (anode layer) and an N-type semiconductor layer (cathode layer) form a PN junction. The term PIN diode means a diode which has an intrinsic semiconductor layer between a P-type semiconductor layer (anode layer) and an N-type semiconductor layer (cathode layer). The term Schottky diode means a diode in which a semiconductor layer and a metal layer form a Schottky junction. The term MIS diode means a diode which has an insulating layer between a metal layer and a semiconductor layer.

In addition to the rectification element, a stack structure such as a semiconductor-insulator-semiconductor (SIS) structure or a metal-insulator-metal (MIM) structure is used for non-ohmic element30.

In the resistance change memory driven by the unipolar operation, a rectification element such as a diode is mainly used as the non-ohmic element30. In the resistance change memory driven by the bipolar operation, the MIM structure or SIS structure is mainly used as the non-ohmic element30.

In the present embodiment, a resistance change memory that utilizes the unipolar operation is mainly described. However, it goes without saying that the resistance change memory in the embodiment of the present invention may be a memory that utilizes the bipolar operation.

When a resistance change memory having a cross-point type memory cell array (hereinafter referred to as a cross-point type resistance change memory) is driven via unipolar operation, the following characteristics are required for rectification element30as a non-ohmic element in order to accurately perform the set/reset operations and read operation: a current (forward current) is high when a forward bias is applied, and a current (reverse current) is low and a breakdown voltage is high when a reverse bias is applied.

As shown inFIG. 3, in the resistance change memory according to the present embodiment, the non-ohmic element30that forms the cell unit CU has a silicide layer39on at least one of its ends (upper end and lower end) in its as-stacked direction.

The silicide layer (also simply referred to as silicide)39includes a silicon element50, a 3d transition metal element51having first atomic radius r1, and an element52having second atomic radius r2. Although three kinds of elements50,51,52are randomly arranged in the silicide layer39inFIG. 3for the sake of simplicity in illustration, it goes without saying that the three kinds of elements50,51,52are chemically bonded together on the basis of a stoichiometric composition ratio to form one crystal grain or one layer.

The 3d transition metal element51is chemically bonded the Si element50, and thereby the silicide layer is formed.

In the present embodiment, the 3d transition metal element51means a metal element capable of having stable unpaired electrons on the 3d orbit of an atom. 3d transition metal element includes, for example, scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu) and zinc (Zn). In the present embodiment, the group of elements listed here as 3d the transition metal elements are referred to as a 3d transition metal element group (first element group).

The element51included in the silicide layer39is at least one kind of element selected from the 3d transition metal element group.

The element52has atomic radius r2greater than atomic radius r1of a selected 3d transition metal element. The element52having atomic radius r2is an element added to silicide formed of the Si element and the 3d transition metal element, and is an element foreign to silicide. In the present embodiment, the element52is also referred to as an additional element or foreign element.

The element52includes a 4d transition metal element, a 4f transition metal element, a group13element and a group14element.

In the present embodiment, the 4d transition metal element means a metal element capable of having stable unpaired electrons on the 4d orbit of an atom.

In the present embodiment, the 4f transition metal element means a metal element capable of having a stable unpaired electron on the 4f orbit of an atom.

A group of elements52having an atomic radius greater than the atomic radius of an element selected as the 3d transition metal element51is referred to as an additional element group (second element group). At least one kind is selected from the second element group for the element52included in silicide layer39.

The element52is not limited to the elements belonging to the additional element group shown here by way of example. The element52may be any element as long as atomic radius r2of the element52is greater than atomic radius r1of one kind of the 3d transition metal element51selected from the 3d transition metal element group. Moreover, an element belonging to the 3d transition metal element group may be used for the additional element52as long as it has as atomic radius greater than atomic radius r1of the element51selected as the 3d transition metal element to form silicide.

It is to be noted that, in the present embodiment, the atomic radius of an element is regulated by one of a metallic bond radius, an ionic radius and a covalent bond radius in accordance with the selected element52and a combination state of elements. Here, the atomic radius of each element is not described in detail. In general, the radius of an element (atom) having a greater atomic number in the periodic table of elements among elements of the same group tends to be greater, and the radius of an element having a smaller atomic number among elements of the same period tends to be greater.

The element52is mainly lattice-substituted for the 3d transition metal element51in the crystal structure of silicide formed of the Si element50and the 3d transition metal element51and present in the silicide layer39. That is, the silicide layer39including the additional element52is rendered a mixed crystal by the addition of the additional element52.

However, the additional element52may be present in the silicide layer39as a crystal grain of a compound of this element52and the Si element50, as a crystal grain of a compound of this element52and the 3d transition metal element51, as a compound of this element and two elements50,51, or as a crystal grain of single additional element52.

The silicide39included in the resistance change memory according to the present embodiment is represented by a chemical formula (composition formula) “M1−xDxSiy”, wherein “M” indicates the 3d transition metal element, “D” indicates an element having a greater atomic radius than that of the 3d transition metal element, and “Si” indicates silicon. Here, “x” is 0.01 or more and 0.99 or less, and “y” is 1 or more and 2 or less.

However, silicide made of the 3d transition metal element51and the Si element52is preferably the main component (base material) of the silicide layer39, and preferably has a relation x1>x2 when indicated by “x=x2”, “x1=1−x=1−x2”, that is, when indicated by Mx1Dx2Siy.

More specifically, the amount of addition of additional element D to silicide composed of the Si element and 3d transition metal element (M) (the ratio of element D to element M) is preferably 30 atomic % or less. That is, the value of “x” in the composition formula of silicide in the present embodiment is preferably 0.3 or less.

This is based on the following theory: If element “D(52)” is excessively added, a compound containing the additional element may also be excessively generated in the silicide layer39. Due to the excessively formed compound, the crystal phase of the silicide layer39may be rough, or phase separation may be caused. Therefore, the resulting formation of no silicide layer having predetermined characteristics and considerable deterioration of the quality of the silicide layer39should be prevented.

Furthermore, the additional element52is preferably an element which is one or more periods away from the selected 3d transition metal element51. For example, when Ti or Ni is selected as the 3d transition metal element51, Pd or Pt is preferably used as the additional element52.

The reason for this is that, as described above or as represented by the composition formula, the added element “D(52)” is lattice-substituted for the 3d transition metal element in the crystal structure of silicide and the silicide layer39is rendered a mixed crystal. Therefore, the crystal structure of a compound (e.g., silicide) formed of the added element52and the Si element50and the crystal structure of a compound containing the additional element52are preferably approximate to the crystal structure of silicide formed of the Si element50and the 3d transition metal element51.

For example, in the case of an MnP crystal structure as in NiSi, an element (e.g., Pt or Pd) in which silicide formed of Si and an additional element can have a crystal structure approximate to the MnP structure is preferably selected as the element52to be added to silicide serving as the base material.

The change in the composition and crystal structure of the silicide layer caused by the addition of the foreign element52is thus taken into consideration to prevent the adverse effect of the addition of the foreign element52.

As shown inFIG. 3, in the resistance change memory according to the embodiment of the present invention, the silicide layer39which includes the Si element50, the 3d transition metal element51forming silicide, and the element52having the atomic radius r2greater than the atomic radius r1of the element51is provided on at least one end of the non-ohmic element (e.g., a rectification element) forming the resistance change memory.

When the foreign element52is added to a certain silicide, the silicide layer39has high heat resistance, and characteristic deterioration of the junction of the silicide layer39and some other parts is reduced.

Thus, according to the resistance change memory in the embodiment of the present invention, the characteristics of elements constituting the resistance change memory, for example, the forward bias/reverse bias of a diode can be improved.

(2) Characteristics of Silicide

The characteristics of silicide included in the resistance change memory according to the embodiment of the present invention are next described withFIG. 4toFIG. 8B.

FIG. 4is a graph showing the relation between the temperature of a thermal treatment for silicide and the electric resistance of silicide, in silicide included in the resistance change memory according to the present embodiment. InFIG. 4, the horizontal axis indicates heating temperature (denoted by “A” inFIG. 4, unit: ° C.), and the vertical axis indicates electric resistance (denoted by “B” inFIG. 4). InFIG. 4, the electric resistance is indicated by sheet resistance (unit: Ω/□).

InFIG. 4, the characteristics of silicide to which palladium (Pd) is added and the characteristics of silicide to which platinum (Pt) is added are shown. Silicide serving as the base material is nickel silicide (NiSiy(0<y≦2)). In this case, inFIG. 3, Ni corresponds to the 3d transition metal element51, and Pd or Pt corresponds to the additional element52. NiSiyincluding Pd or Pt is formed on B-doped SiGe. Here, silicide is thermally treated by a rapid thermal annealing (RTA) method.

InFIG. 4, the concentrations of Pd are 8 atomic %, 15 atomic % and 30 atomic %, and the concentrations of Pt are 8 atomic % and 15 atomic %.

In the present embodiment, the concentrations (atomic percentages) of Pd and Pt are regulated by the ratio of Pd (or Pt) to Ni. In the present embodiment, this ratio is indicated by atomic percent, and written as atomic % or at. %. For example, when the concentration of Pd is 8 atomic %, NiSiyincluding Pd is indicated by Ni0.92Pd0.08Siy(0<y≦2).

As shown inFIG. 4, at a thermal treatment temperature ranging from 500° C. to 700° C., the sheet resistance of NiSiyto which Pd is added and the sheet resistance of NiSiyto which Pt is added respectively show values ranging from 10Ω/□ to 30Ω/□ without any significant change in the resistance value.

If agglomeration of a metal in the silicide layer or phase separation of the silicide layer is caused, the electric resistance (sheet resistance) of the silicide layer is increased.

Therefore, the experimental result inFIG. 4shows that even if NiSiyto which Pd or Pt is added is thermally treated at 500° C. to 700° C., there is no agglomeration of metal elements (Ni, Pd and Pt) in the silicide layer, no phase separation of silicide and no deterioration of the crystallinity of the silicide layer.

In particular, the electric resistance of NiSiyto which 8 atomic % of Pd and 15 atomic % of Pd is added maintains the same level as the resistance value at a heating temperature of 500° C. to 700° C. even if such NiSiyis thermally treated at 750° C.

In addition, the sheet resistance of Pd-added NiSiythermally treated at 500° C. to 700° C. is lower than the sheet resistance of Pd-added NiSiythermally treated at 350° C. This is attributed to the fact that the crystallinity of silicide has improved owing to the thermal treatment or a chemical reaction between the metal (Ni, Pd) elements and the Si element is optimized within a temperature range of 500° C. to 700° C. such that the composition ratio of silicide made of Ni, Pd and Si is closer to an ideal stoichiometric composition ratio.

On the other hand, the resistance value of NiSiyto which Pt is added is within a range of 350° C. to 700° C., and shows no great change. It is considered from this fact that the reaction temperature for silicidation of NiSiycontaining Pt (hereinafter also referred to as a silicide reaction temperature) is lower than the silicide reaction temperature of NiSixcontaining Pd.

FIG. 5AandFIG. 5Bshow changes in the electric resistance of silicide included in the resistance change memory according to the present embodiment versus the concentration of the element (foreign element) added to silicide. InFIG. 5AandFIG. 5B, the horizontal axis indicates the concentration (denoted by “A” inFIG. 5AandFIG. 5B) of the added element, and the vertical axis indicates electric resistance (here, sheet resistance) (denoted by “B” inFIG. 5AandFIG. 5B). The unit of the concentration of the added element is at. % (atomic %).

FIG. 5AandFIG. 5Bshow the cases where Pd or Pt is added to NiSiyas in the example shown inFIG. 4. In addition, each silicide layer is formed on B-doped SiGe as inFIG. 4.

FIG. 5Ashows the case where NiSiyto which Pd or Pt is added is thermally treated at 700° C.FIG. 5Bshows the case where NiSiyto which Pd or Pt is added is thermally treated at 750° C.

As shown inFIG. 5AandFIG. 5B, the sheet resistance of Pd-added NiSiyis lower than the sheet resistance of Pt-added NiSiy.

Moreover, as inFIG. 4, the sheet resistance of Pt-added NiSiyat a heating temperature of 750° C. is higher than the sheet resistance at a heating temperature of 700° C. On the other hand, the sheet resistance of Pd-added NiSiyeven at a heating temperature reaching 750° C. is at about the same level as the sheet resistance at a heating temperature of 700° C.

Further, in Pd-added NiSiy, a sheet resistance of the same level is obtained regardless of the concentration of Pd within the range of Pd concentration of about 8 atomic % to 30 atomic %.

In accordance with the experimental result shown inFIG. 4toFIG. 5B, the silicide layer in which Pd is added to NiSiycan have low electric resistance, and can obtain a characteristic close to the maximum high-temperature resistance. This characteristic is particularly apparent when the silicide layer in which Pd is added to NiSiyis formed on SiGe.

Furthermore, regarding the high-temperature resistance of a silicide layer on a P-type silicon layer, as in a MIS diode that uses P-type silicon, Pd-added NiSiyshows more satisfactory high-temperature resistance (higher heat resistance) than Pt-added NiSiy. In addition, if the manufacturing cost is compared with the characteristics of silicide, Pd-added NiSiymakes it possible to obtain a lower-cost and higher-performance element (e.g., rectification element) and resistance change memory that uses this element than Pt-added NiSiy.

For example, when the concentration of added Pd is 15 atomic %, Pd-added NiSiy(Ni0.85Pd0.15Siy) can ensure a relatively low sheet resistance of about 20Ω/□ and have high heat resistance at a temperature of about 750° C.

As a result, the amount of the addition of the foreign element (D) to silicide (base material) composed of the Si element (Si) and 3d transition metal element (M) (the ratio of element D to element M) is particularly preferably 15 atomic % or less. In this case, the value of “x” in the composition formula of silicide in the present embodiment is 0.15 or less.

The relation between the addition of the foreign element to a certain silicide and crystal grains constituting silicide is described withFIGS. 6A and 6B.

FIG. 6Ashows the relation between the concentration [at. %] of an element added to silicide (denoted by “A” inFIG. 6A) and the crystal grain diameter [nm] of silicide (denoted by “B” inFIG. 6A), in silicide (NiSiy) included in the resistance change memory according to the present embodiment.FIG. 6Bshows microscopic images of the surface of the silicide layer.FIG. 6Bshows the surface of nickel silicide (NiSiy) to which no foreign element is added and the surface of NiSiyto which 30 atomic % of a foreign element is added.

As shown inFIG. 6A, when the concentration of the foreign element added to NiSiyis higher, the grain diameter of crystals constituting one silicide layer is smaller.

Furthermore, as shown inFIG. 6B, one silicide layer is formed of crystals having a greater grain diameter in NiSiyto which no foreign element is added, while one silicide layer is formed of crystals of 30 nm or less (hereinafter referred to as microcrystal) in NiSiyto which foreign element D is added.

As shown inFIG. 6AandFIG. 6B, the grain diameter of crystals constituting a certain silicide layer becomes smaller when an element different in size from the 3d transition metal element forming the silicide layer, in particular, element D having a greater atomic radius than the 3d transition metal element is added.

The smaller crystal leads to a smaller surface area of each crystal and more stable energy for maintaining crystal. It is considered that such stabilization of crystal energy attributed to the smaller crystal prevents decomposition of silicide crystals (interatomic bonds) and inhibits agglomeration of a metal and deterioration of the crystal phase of silicide even if high heat energy is applied to the silicide layer.

As shown inFIG. 4toFIG. 6B, silicide which includes Si, a 3d transition metal element forming silicide, and an element having a greater atomic radius than the 3d transition metal element shows high-temperature resistance (high heat resistance).

A thermal treatment at about 500° C. is used in a back-end process of a general semiconductor device (e.g., an integrated circuit). A thermal treatment at about 600° C. to 700° C. may be used for a resistance change memory.

The silicide layer included in the resistance change memory according to the present embodiment is capable of maintaining electric properties without deterioration in the quality of the crystallinity of silicide even when thermally treated at 700° C. or more.

Therefore, as shown inFIG. 4toFIG. 6B, silicide which includes a 3d transition metal element and an element having a greater atomic radius than the 3d transition metal element, such as Ni1−xPdxSiyand Ni1−xPtxSiy, has resistance to a higher temperature (hereinafter referred to as high-temperature resistance) than the temperature of a thermal treatment in a general back-end process, and also has resistance to a high-temperature thermal treatment used for the resistance change memory.

FIG. 7AandFIG. 7Bshows current-voltage characteristics (I-V characteristics) in the junction of silicon and silicide according to the present embodiment. InFIG. 7AandFIG. 7B, the horizontal axis indicates the voltage applied to a silicon-silicide junction (denoted by “A” inFIG. 7AandFIG. 7B, unit: [V]), and the vertical axis indicates the current running through the junction due to the applied voltage (denoted by “B” inFIG. 7AandFIG. 7B, unit: [A]).

FIG. 7Ashows I-V characteristics measured under temperature conditions at 255 K (absolute temperature), 270 K, 285 K and 300 K in the junction of silicide (Ni0.87Pd0.13Siy) in which the concentration of Pd versus Ni is set at 13 atomic % and P-type silicon.FIG. 7Bshows I-V characteristics measured under temperature conditions at 255 K (absolute temperature), 285 K and 300 K in the junction of silicide (Ni0.70Pd0.30Siy) in which the concentration of Pd versus Ni is set at 30 atomic % and P-type silicon. In addition, “y” is a value indicated by a range of 0<y≦2.

As shown inFIG. 7A, the junction of Ni0.87Pd0.13Siyand P-type silicon forms a Schottky junction. From the temperature dependence of each I-V characteristic shown inFIG. 7A, the height of a Schottky barrier of this junction measures about 0.28 eV.

As inFIG. 7A, Ni0.70Pd0.30Siyand P-type silicon forms a Schottky junction. From the temperature dependence of each I-V characteristic shown inFIG. 7B, the height of a Schottky barrier of Ni0.70Pd0.30Siyand P-type silicon measures about 0.31 eV.

Generally, in a Schottky junction of P-type silicon and each of NiSiyto which no Pd is added, titanium silicide (TiSiy) and tantalum silicide (TaSiy), the height of a Schottky barrier is about 0.4 eV to 0.5 eV.

The following is shown from the result of measurements inFIG. 7AandFIG. 7B.

If element D having a greater atomic radius than the atomic radius of element (3d transition metal element) M is added to silicide indicated by “MSiy”, the work function of silicide can be modulated. As shown inFIG. 7AandFIG. 7B, the modulation of the work function of silicide depends on the concentration of added element D.

Furthermore, if the work function of silicide is modulated by the addition of a foreign element, the work function of silicide versus silicon can be optimized, and the interface resistance of the silicon-silicide junction can be reduced.

For example, as described above, the Schottky barrier against P-type silicon is lower in NiSiyto which Pd is added than in NiSiyto which no Pd is added. That is, the interface resistance against P-type silicon can be lower in NiSiyto which Pd is added than in NiSiy, TiSiyand TaSiyto which no foreign element is added.

The addition of the foreign element (e.g., Pt or Pd) to silicide tends to cause the segregation of Pt or Pd or of other impurities contained in silicon at the interface between silicide and silicon. Thus, a layer in which impurities are segregated with high concentration (referred to as a high-concentration segregation layer) is formed at the silicide-silicon interface. As a result, the interface resistance of the silicon-silicide junction is reduced.

As shown inFIG. 7AandFIG. 7B, in silicide including a 3d transition metal element and a foreign element (additional element) having a greater atomic radius than the atomic radius of the 3d transition metal element, the work function of silicide can be modulated by the addition of the foreign element, so that the interface resistance of the silicon-silicide junction can be reduced.

In addition, Pd or Pt is added to NiSiyin the case mainly illustrated inFIG. 4toFIG. 7B, and the characteristics of silicide included in the resistance change memory according to the present embodiment have been described. However, substantially the same tendency as that inFIG. 4toFIG. 7Bis also shown and similar results can be obtained in the present embodiment when silicide made of an Si element and a different 3d transition metal element (e.g., Ti) and other additional elements (foreign elements) are used.

Advantages in the following case are described withFIG. 8AandFIG. 8B: the silicide layer (M1−xDxSiy) including the Si element50, the 3d transition metal element51, and at least one kind of the element52having atomic radius r2greater than atomic radius r1of the 3d transition metal element51is applied to the resistance change memory, as shown inFIG. 3.

FIG. 8Ais a diagram schematically showing the state of the non-ohmic element included in the resistance change memory when subjected to a high-temperature thermal treatment. InFIG. 8A, diodes30X,30constituting a cell unit of the cross-point type resistance change memory are shown. In addition, PIN diodes constituted of three semiconductor layers (silicon layers)31,32,33are shown as examples of diodes30X,30inFIG. 8A.

Here, the PIN diode has a stack structure composed of the intrinsic semiconductor layer32, semiconductor layer33containing a large amount of a P-type impurity (having a high concentration of acceptor impurities), and the semiconductor layer31containing a large amount of an N-type impurity (a high concentration of donor impurities). In addition, the stack positions (vertical relation) of the P-type semiconductor layer33and the N-type semiconductor layer31may be reverse to that inFIG. 8A.

InFIG. 8A, a silicide (MSiy)90to which no foreign element is added is provided on one end (semiconductor layer33side) of the diode30X. InFIG. 8A, a silicide (M1−xDxSiy)39to which foreign element D is added is provided on one end (semiconductor layer33side) of the diode30.

In the process of manufacturing the resistance change memory, a high-temperature thermal treatment at about 600° C. to 800° C. may be conducted to form the non-ohmic element and the memory element.

For example, the high-temperature resistance (heat resistance) of NiSiyto which no foreign element is added is about 600° C. When a thermal treatment at a high temperature of 600° C. or more is conducted, agglomerates59of metal element M forming silicide may be formed in the semiconductor layer33where the silicide layer90is provided and in the intrinsic semiconductor32thereunder, in the diode30X that uses silicide to which no foreign element is added (MxSiy), as shown inFIG. 8A.

Furthermore, transition metal element (transition metal atom) M can diffuse into semiconductor layers33,32due to the high-temperature thermal treatment. In particular, the intrinsic semiconductor32is provided between the N-type semiconductor layer31and the P-type semiconductor layer33in the PIN diode. Therefore, the diffusion of the metal atoms in the intrinsic semiconductor32forms an impurity level in the intrinsic semiconductor32and significantly deteriorates the electric properties of the PIN diode.

Moreover, due to an excessive silicide reaction resulting from the high-temperature thermal treatment, the silicide layer91may be formed to erode not only the end of the semiconductor layer33but also regions where formation of no silicide layer is needed, such as the inside of the semiconductor layer33and the intrinsic semiconductor32. This erosion may break down a silicon-silicon junction.

This deteriorates the electric characteristics of the diode30X, and degrades the operating characteristics of the resistance change memory. Moreover, if the thickness of semiconductor layer33is increased to reduce adverse effects of the agglomeration/diffusion of the metal element and the erosion by silicide, shrinking (decrease of the aspect ratio) of the cell unit is difficult.

Moreover, since the agglomeration/diffusion of the metal element and the erosion of the semiconductor layer by the silicide layer are nonuniform in the memory cell array, characteristic variation among the cell units in the memory cell array increases.

On the other hand, the silicide layer39including the Si element, the 3d transition metal element (M) and the element (D) having an atomic radius greater than the atomic radius of the 3d transition metal element has high-temperature resistance ranging from 700° C. to 750° C. owing to the smaller crystal grain as described withFIG. 4toFIG. 6B.

Therefore, as shown inFIG. 8A, in diode30having silicide layer39, the agglomeration/diffusion of the metal element (M or D) and the erosion by silicide are inhibited by the high heat resistance of silicide (M1−xDxSiy) even if a thermal treatment at 500° C. or more is conducted.

This reduces the deterioration of the characteristics of the cell unit including the silicide layer, for example, the forward bias characteristic and reverse bias characteristic of the diode due to the high-temperature thermal treatment included in the process of manufacturing the resistance change memory.

FIG. 8Bshows one example of the I-V characteristic of the diode. InFIG. 8B, the horizontal axis indicates a potential difference applied across both ends of the diode (denoted by “D” inFIG. 8B, unit: [V]), and the vertical axis indicates, on a logarithmic scale, the current running through the junction due to the applied potential difference (denoted by “E” inFIG. 8B, unit: [A]).

InFIG. 8B, characteristic line (full line) A indicates a simulation result obtained by a self-manufactured simulator regarding the I-V characteristic of the diode which is provided, on one end, with the silicide layer39including the Si element, the 3d transition metal element (M) and the additional element (D) as in, for example, the diode30shown inFIG. 8A. Characteristic line (chain line) B indicates a simulation result regarding the I-V characteristic of the diode which is provided, on one end, with the silicide layer including the Si element and the 3d transition metal element (M), that is, the silicide layer to which no foreign element is added. A silicon-silicide interface resistance model is applied to the simulations indicated by these characteristic lines A, B.

Characteristic line (broken line) C indicates measurements of the I-V characteristic of the diode shown by characteristic line B. Characteristic line B and characteristic line C show that the simulation and the measurements substantially correspond to each other.

In addition, the silicide layer forms an interface with the P-type silicon layer in the simulation and experiment shown inFIG. 8B. Moreover, in the diode corresponding to each of characteristic lines A, B, C, the silicide layer includes the same kind of 3d transition metal element.

The intensity (upper limit value) of an output current (referred to as a forward current) of the rectification element when a forward bias is applied is subject to the intensity of the interface resistance of the silicon-silicide junction. Specifically, the upper limit value of the forward current decreases if the interface resistance increases.

As shown inFIG. 7AandFIG. 7B, the work function of silicide can be modulated by the addition of an additional element (foreign element) of desired concentration to silicide. Thus, at the junction of silicon and silicide, resistance (interface resistance) generated in the interface can be reduced. That is, the interface resistance can be reduced, so that a current loss resulting from the interface resistance can be reduced.

Consequently, as indicated by characteristic line A inFIG. 8B, the upper limit of the forward current of the rectification element when a forward bias is applied can be improved in the resistance change memory according to the present embodiment, as compared with the rectification element that uses silicide indicated by characteristic line B to which no foreign element is added.

Therefore, at a certain voltage applied to the rectification element (non-ohmic element), the rectification element can supply a higher forward current to the memory element. This also contributes to a reduction in the power consumption of the resistance change memory.

Furthermore, since the silicide layer to which a foreign element is added has high-temperature resistance in the resistance change memory according to the present embodiment as described above, the agglomeration and diffusion of the metal element included in the silicide layer and the erosion of other parts by the silicide layer can be inhibited. This makes it possible to prevent the formation of an impurity level in the semiconductor layer and the breakdown of the junction.

Thus, in the resistance change memory according to the present embodiment, a high breakdown voltage can be ensured in the rectification element used as the non-ohmic element, and an output current (referred to as a reverse current) of the rectification element when a reverse bias is applied can be reduced.

Furthermore, in the resistance change memory according to the present embodiment, since the formation of randomly generated agglomerates and the diffusion of the metal element in the silicon layer can be inhibited, characteristic variation of the cell units in one memory cell array can be reduced.

Moreover, the forward bias/reverse bias characteristics of the rectification element can be improved, which contributes to the thickness reduction of the layers constituting the rectification element and the reduction of the area of the cell unit.

Consequently, according to the resistance change memory in the embodiment of the present invention, characteristic deterioration of the resistance change memory can be inhibited.

EXAMPLE

An example of the resistance change memory according to the embodiment of the present invention is more specifically described withFIG. 9toFIG. 19.

(a) Configurations of the Memory Cell Array and the Control Circuit

FIG. 9specifically shows one example of the configurations of the interconnect lines and the cell units in the cross-point type memory cell array.

Here, cell units CU1, CU2in two memory cell arrays M1, M2inFIG. 2are shown. In this case, the cell units in two memory cell arrays M3, M4inFIG. 2are the same in configuration as the cell units in two memory cell arrays M1, M2inFIG. 2.

Each of cell units CU1, CU2is composed of a memory element and a non-ohmic element that are connected in series. Here, a rectification element is used for the non-ohmic element.

There are various patterns of the connection between the memory element and the rectification element. However, all the cell units in one memory cell array need to be the same in the connection between the memory element and the rectification element.

FIG. 10shows the connection between the memory element and the rectification element.

In one cell unit, there are a total of four patterns of the connection between the memory element and the rectification element; two patterns of the positional relation between the memory element and the rectification element, and two patterns of the direction of the rectification element. Therefore, there are sixteen patterns (four patterns×four patterns) of the connection between the memory element and the rectification element regarding the cell units in two memory cell arrays.

a to p ofFIG. 10denote sixteen patterns of connection.

While the embodiment is applicable to all of the sixteen patterns of connection, the connection of “a” ofFIG. 10is mainly described below by way of example.

FIG. 11AandFIG. 11Bshow a first example of the layout of the first and second control circuits.

Memory cell array Ms inFIG. 11Acorresponds to one layer M1, M2, M3, M4of cross-point type memory cell array2shown inFIG. 2. As shown inFIG. 11A, memory cell array Ms is composed of a plurality of arrayed cell units CUs. The cell units CUs are connected on one end to interconnect lines Ls (j−1), Ls (j), Ls (j+1), and connected on the other end to interconnect lines Ls+1 (i−1), Ls+1 (i), Ls+1 (i+1).

As shown inFIG. 11B, memory cell array Ms+1 is composed of a plurality of arrayed cell units CUs+1. The cell units CUs+1 are connected on one end to interconnect lines Ls+1 (i−1), Ls+1 (i), Ls+1 (i+1), and connected on the other end to interconnect lines Ls+2 (j−1), Ls+2 (j), Ls+2 (j+1).

The first control circuit3is connected to interconnect lines Ls+1 (i−1), Ls+1 (i), Ls+1 (i+1) on one end in the first direction via switch elements SW1. Switch elements SW1are controlled by, for example, control signals φs+1 (i−1), φs+1 (i), φs+1 (i+1). The switch element SW1is configured by, for example, an N-channel field effect transistor (FET).

The second control circuit4is connected to interconnect lines Ls (j−1), Ls (j), Ls (j+1) on one end in the second direction via switch elements SW2. Switch elements SW2are controlled by, for example, control signals φs (j−1), φs (j), φs (j+1). The switch element SW2is configured by, for example, an N-channel FET.

Second control circuit4is connected to interconnect lines Ls+2 (j−1), Ls+2 (j), Ls+2 (j+1) on one end in the second direction via switch elements SW2′. Switch elements SW2′ are controlled by, for example, control signals φs+2 (j−1), φs+2 (j), φs+2 (j+1). Switch element SW2′ is configured by, for example, an N-channel field effect transistor.

FIG. 11Cshows a second example of the layout of the first and second control circuits. In addition, inFIG. 11C, the internal configuration of memory cell arrays Ms, Ms+1, Ms+2, Ms+3 is substantially the same as that of the memory cell array shown inFIG. 11AorFIG. 11Band is therefore not shown.

The layout in the second example is different from the layout in the first example in that first control circuits3are disposed at both ends of the first direction of memory cell array Ms, Ms+1, Ms+2, Ms+3 and in that second control circuits4are disposed at both ends of the second direction of memory cell array Ms, Ms+1, Ms+2, Ms+3.

Second control circuits4are connected to interconnect lines Ls (j−1), Ls (j), Ls (j+1) on both ends in the second direction via switch elements SW2. Switch elements SW2are controlled by, for example, control signals φs (j−1), φs (j), φs (j+1), φs+2 (j−1), φs+2 (j), φs+2 (j+1). The switch element SW2is configured by, for example, an N-channel field effect transistor.

(b) Configuration of the Cell Unit

FIG. 12AtoFIG. 12Fshow examples of the configuration of the cell unit.

One cell unit CU is disposed between two interconnect lines60,65. One cell unit CU is composed of one memory element20and one non-ohmic element30.

In one cell unit, the memory element20is stacked on the non-ohmic element30, or the non-ohmic element30is stacked on the memory element20.

Here, in the stacking direction of two elements20,30, an interconnect line65side is called an upper side (upper end or upper part), and an interconnect line60side is called a lower side (lower end or lower part).

Here, a PIN diode is illustrated as the non-ohmic element30. As described above, the PIN diode has a structure in which an intrinsic semiconductor layer is interposed between a P-type semiconductor layer and an N-type semiconductor layer. In addition, in accordance with the connection of two cell units of the memory cell array2shown inFIG. 10, the vertical relation between an anode layer and a cathode layer of the diode30in the stacking direction may be reverse.

For example, in the cell unit CU shown inFIG. 12A, in case the upper semiconductor layer33is a P-type semiconductor layer (anode layer) of the PIN diode, the lower semiconductor layer31is an N-type semiconductor layer (cathode layer) of the PIN diode. On the contrary, in case the upper semiconductor layer33is an N-type semiconductor layer (cathode layer) of the PIN diode, the lower semiconductor layer31is a P-type semiconductor layer (anode layer) of the PIN diode. In each case, the semiconductor layer32between two semiconductor layers31,33is an intrinsic semiconductor layer of the PIN diode.

In the cell unit inFIG. 12BtoFIG. 12Fas well, two semiconductor layers31,33sandwiching the intrinsic semiconductor layer32have a similar relation to that inFIG. 12Awhen a PIN diode is used for the rectification element (non-ohmic element)30.

Each of semiconductor layers31,32,33is made of a material containing silicon as the main component. For example, silicon carbide (SiC), silicon germanium (SiGe), silicon tin (SiSn), polycrystalline silicon (Poly-Si), amorphous silicon or monocrystalline silicon is used to form semiconductor layers31,32,33. In SiC, the concentration of C (carbon) against Si is about 0 to 3 atomic %. In SiGe, the concentration of Ge (germanium) versus Si is about 0 to 30 atomic %. In SiSn, the concentration of Sn (tin) versus Si is about 0 to 3 atomic %.

Furthermore, boron (B) is added to semiconductor layers31,33containing P-conductivity-type silicon as the main component. Phosphorus (P) or arsenic (As) is added to semiconductor layers31,33containing N-conductivity-type silicon as the main component. In addition, the intrinsic semiconductor layer may contain P-type/N-type impurities, but the concentration of the P-type/N-type impurities contained in the intrinsic semiconductor layer32is lower than the concentration of impurities contained in semiconductor layers31,33.

The memory element20has a structure in which the resistance change film21is interposed between two electrodes25,26. In the examples shown inFIG. 12AtoFIG. 12F, the electrode25on the lower side in the stacking direction of two elements20,30is called a lower electrode, and the electrode26on the upper side is called an upper electrode.

The resistance change film21is a layer made of a material with a resistance value that changes upon application of, for example, a voltage, a current or heat, or a material having a physicality such as a resistance value or capacitance (impedance) that changes due to a phase change. The resistance value of the resistance change film21is reversibly changed by the application of energy such as a voltage, and the condition in which the resistance value has changed is retained in a nonvolatile manner until energy that changes the resistance value is again provided.

In addition, the memory element20may be an element that shows such characteristics by the combination of electrodes25,26and the resistance change film21, or the resistance change film21may be an element that shows such characteristics.

Interconnect lines60,65are used as a bit line and a word line, as described above. Interconnect lines60,65are made of, for example, a metal such as Cu, Al or W, a metal compound such as titanium nitride (TiN) or tungsten nitride (WN), or silicide such as NiSiyor TiSiy.

In the example shown inFIG. 12A, the memory element20is stacked on the diode30. The diode30is disposed on the interconnect line60. One end (bottom) of the diode30is electrically connected to the interconnect line60. The other end (top) of the diode30is electrically connected to one end (lower electrode) of the memory element20. The other end (upper electrode) of the memory element20is electrically connected to the interconnect line65.

The diode30has the silicide layer39A on its upper end, and the silicide layer39A is provided on the top of the upper semiconductor layer33. The silicide layer39A intervenes between the semiconductor layer33and the lower electrode25of the memory element20. For example, the silicide layer39A is in direct contact with the lower electrode25.

Furthermore, in the example shown inFIG. 12B, the diode30is stacked on memory element20. In this case, the memory element20is disposed on the interconnect line60. One end (lower electrode) of memory element20is electrically connected to the interconnect line60. The other end (upper electrode) of the memory element20is electrically connected to one end (bottom) of the diode30. The other end (top) of the diode30is electrically connected to the interconnect line65. In the cell unit shown inFIG. 12B, the diode30has the silicide layer39B on its lower end, and the silicide layer39B is provided on the bottom of the lower semiconductor layer31. Silicide layer39B intervenes between the semiconductor layer31and the upper electrode26. For example, the silicide layer39B is in direct contact with the upper electrode26.

In the example shown inFIG. 12C, the memory element20is stacked on the diode30. The silicide layer39B is provided on the bottom of the semiconductor layer31of the diode30. The silicide layer39B intervenes between the semiconductor layer31and the interconnect line60. For example, the silicide layer39B is in direct contact with the interconnect line60.

In the example shown inFIG. 12D, the diode30is stacked on the memory element20. The silicide layer39A is provided on the top of the semiconductor layer33of the diode30. The silicide layer39A intervenes between the semiconductor layer33and the interconnect line65. For example, the silicide layer39A is in direct contact with the interconnect line65.

As shown inFIG. 12AtoFIG. 12D, the silicide layer39A,39B is only formed on a single end (one end) of the diode, so that the process of manufacturing the diode having the silicide layer39A,39B can be simpler.

Especially, when a silicide in which a metal element having a work function close to that of a valence band such as Pt, Pd, Os, Ir, Rh or Ru is added to a 3d transition metal element such as Ni or Ti that is used in the present embodiment is used as silicide (M1−xDxSiy) in the present embodiment, the formation of the silicide layer39A,39B in a semiconductor layer containing P-conductivity-type silicon as the main component is effective. The reason for this is as follows: The system to which, for example, the above-mentioned Pt belongs has a work function (a Fermi level) close to that of the valence band of P-type Si, and such elements can improve the segregation of impurities at the interface and the activation rate of impurities. Therefore, the formation of an electric junction of silicide that uses the above-mentioned system and a P-type semiconductor (e.g., P-type Si) is preferable as regards the electric properties of the element.

Furthermore, as shown inFIG. 12EandFIG. 12F, silicide layers39A,39B may be provided on both ends (top/bottom) of the diode30, respectively.

In the example shown inFIG. 12E, silicide layer39A provided at the top of the diode30intervenes between the lower electrode25and the semiconductor layer33. Moreover, the silicide layer39B provided at the bottom of the diode30intervenes between the semiconductor layer31and the interconnect line60. For example, the silicide layer39A on the upper side of the element is in direct contact with the lower electrode25, and the silicide layer39B on the bottom side of element is in direct contact with the interconnect line60.

In the example shown inFIG. 12F, the silicide layer39A provided at the top of the diode30intervenes between the semiconductor layer33and the interconnect line65. Moreover, the silicide layer39B provided at the bottom of the diode30intervenes between the semiconductor layer31and the upper electrode26. For example, the silicide layer39A on the upper side of the element is in direct contact with the interconnect line65, and the silicide layer39B on the bottom side of the element is in direct contact with the upper electrode26.

One of the cell units shown inFIGS. 12A and 12Fis disposed between the bit line and the word line to satisfy the connection relation shown inFIG. 10to configure a memory cell array and a cross-point type memory cell array.

As in the cell units CU shown inFIG. 12AtoFIG. 12F, the silicide layer39A,39B is provided on at least one end (top) or the other end (bottom) of the non-ohmic element (e.g., rectification element). As shown inFIG. 3, the silicide layer39A,39B includes the Si element50, the 3d transition metal element51that combines with the Si element to form silicide, and the additional element (foreign element)52having an atomic radius greater than the atomic radius of the 3d transition metal element.

The junction of the silicide layer39A,39B and the silicon layer31,32may have a segregation layer (not shown) in which impurities (donor/acceptor) contained in the silicon layer are segregated with high concentration due to the addition of the additional element52.

Further, the silicide layer39A,39B may contain one kind of additional element, or may contain two or more kinds of additional elements.

Although three semiconductor layers are stacked as in a PIN diode in the structures illustrated inFIG. 12AtoFIG. 12F, a metal-insulator-semiconductor (MIS) diode, a SIS structure or a MIM structure may be used for the non-ohmic element30, or a structure in which two layers are stacked as in a PN diode may be used for the non-ohmic element. Moreover, the non-ohmic element may be an element which allows non-ohmic characteristics to be formed by four layers (films).

For example, if the non-ohmic element30having the silicide layer39A in the present embodiment is a MIS diode, three layers are stacked in the following order: a metal layer, an insulating layer and a semiconductor layer from the lower side; or a semiconductor layer, an insulating layer and a metal layer from the lower side. In addition, a structure in which the silicide layer is only provided on the semiconductor layer is sufficient for the MIS diode. However, the semiconductor layer and the silicide layer may be provided on the surface of the metal layer opposite to the junction surface of the metal layer and the insulating layer.

Moreover, the non-ohmic element30may have a structure in which three or more P-type semiconductor layers and N-type semiconductor layers are alternately stacked, such as a three-layer bipolar transistor type structure or a four-layer thyristor type structure. Especially, in case the upper semiconductor layer33is a P-type semiconductor layer or an N-type semiconductor layer in the above-mentioned structure, the silicide layer39A,39B described in the present embodiment may be provided in the semiconductor layer33.

InFIG. 12AtoFIG. 12F, a diffusion preventing layer or an adhesive layer may be provided between the interconnect line60,65and the non-ohmic element30, between the non-ohmic element30and the memory element20or between the memory element20and the interconnect line60,65. The diffusion preventing layer prevents the diffusion of constituent atoms or constituent elements of each part between parts that are joined together. The adhesive layer secures the bonding force between joined parts and prevents the separation of the parts. In addition, electrodes25,26may have substantially the same function as the diffusion preventing layer or the adhesive layer.

FIG. 13AtoFIG. 13Cshow one example of the non-ohmic element (here, the rectification element) and the work function of silicide.

InFIG. 13AandFIG. 13B, a PIN diode is shown as the non-ohmic element. In case the non-ohmic element includes a semiconductor layer as in the PIN diode, the silicide layer39used in the present embodiment is provided in the P-type semiconductor layer35or the N-type semiconductor layer37depending on the connection of the cell units. The intrinsic semiconductor layer36is provided between the P-type semiconductor layer35and the N-type semiconductor layer37. Semiconductor layers35,36,37are semiconductor layers containing silicon as the main component, and may be a layer containing Ge or C in addition to silicon. Here, for ease of explanation, these semiconductor layers are simply referred to as P-type/N-type silicon layers.

When the silicide layer and the N-type silicon layer form an interface (junction), the relation between the conduction band of the N-type silicon layer and the work function of the silicide layer affects the electric properties of the element. When the silicide layer and the P-type silicon layer form an interface (junction), the relation between the valence band of the P-type silicon layer and the work function of the silicide layer affects the electric properties of the element. That is, the difference between the conduction band (N-type Si)/valence band (P-type Si) of silicon and the work function of silicide is one of the causes of interface resistance.

In case the energy difference between the conduction band (N-type Si)/valence band (P-type Si) of silicon and the work function of silicide is closer to 0 eV, the interface resistance is lower, and a current and a voltage output via the silicon-silicide junction are higher.

As long as the P-type/N-type silicon layer that forms an interface with the silicide layer is a P+/N+ silicon layer having a high impurity concentration of, for example, 1020/cm3or more, an energy difference that can reduce a loss caused by the interface resistance is sufficient. In this case, the energy difference between the valence band of P-type silicon and the work function of silicide and the energy difference between the conduction band of N-type silicon and the work function of silicide may be, by way of example, 0.7 eV or less.

As described withFIG. 7AandFIG. 7B, the magnitude of the work function of silicide to silicon can be adjusted by adding at least one kind of additional element having an atomic radius greater than the atomic radius of the 3d transition metal element to the silicide layer composed of the Si element and the 3d transition metal element.

Therefore, by controlling the combination of the material of silicide and an additional element and controlling the addition amount of the additional element, the work function of silicide can be adjusted to a value suitable for silicon forming the rectification element. This makes it possible to reduce the interface resistance generated at the junction of P-type/N-type semiconductor (e.g., P-type/N-type silicon) and silicide.

FIG. 13Cshows the magnitude of the work function of each kind of silicide. InFIG. 13C, the horizontal axis indicates a base material for forming silicide layer39of the present embodiment, and the vertical axis indicates the work function to silicon (denoted by “A” inFIG. 13C, unit: [eV]).

As shown inFIG. 13A, when an interface is formed between silicide layer39and the P-type semiconductor layer (e.g., the P-type silicon layer), silicide belonging to group G1enclosed by a full line inFIG. 13Cis preferably used as the base material (also referred to as a base silicide material) for forming silicide layer39in the P-type silicon layer.

Among silicides in group G1, TiSiy, VSiy, CrSiy, MnSiy, FeSiy, CoSiy, NiSiy, NdSiy, MoSiy, HfSiy, TaSiy, WSiy, PdSiy, IrSiy, PtSiy, RhSiy, ReSiyor OsSiyis used as the base silicide material for the silicide layer39. It is preferable to add a foreign element to these silicides in order to reduce the resistance of the interface between the silicide layer39and the P-type silicon layer. In addition, “y” in each composition formula is indicated by a value higher than 0 and a value equal to or lower than 2.

As shown inFIG. 13B, when an interface is formed between silicide layer39and the N-type semiconductor layer (e.g., the N-type silicon layer), silicide belonging to group G2enclosed by a broken line inFIG. 13Cis preferably used as the base silicide material for forming the silicide layer39in the N-type silicon layer.

Among silicides in group G2, TiSiy, VSiy, CrSiy, MnSiy, FeSiy, CoSiy, NiSiy, NdSiy, MoSiy, HfSiy, TaSiy, YSiy, YbSiy, ErSiy, HoSiy, DySiy, GdSiyor TbSiyis used as the base silicide material for the silicide layer39. It is preferable to add a foreign element to these silicides in order to reduce the resistance of the interface between the silicide layer39and the N-type silicon layer. In addition, “y” in each composition formula is a value indicated by 1 to 2.

Not only the amount of doping of the silicide layer39with the additional element adjusted but also the material of silicide to serve as the base silicide material for the silicide layer39is changed depending on whether the silicon layer that combines with the silicide layer to form a junction is a P-type silicon layer or an N-type silicon layer. Thereby, the high-temperature resistance of silicide layer39is improved, and the resistance of the interface between the silicon layer and silicide layer39can be reduced by using a material having more suitable physicality.

In addition, from the perspective of the high-temperature resistance, TiSiy, CoSiy, PtSiy, TaSiyor WSiyis effective as the base material for forming silicide layer39to which a foreign element is added.

Moreover, in the case illustrated inFIG. 13AandFIG. 13B, the silicide layer39forms an interface with the P-type/N-type silicon layer that configures the PIN diode. However, the example shown inFIG. 13AandFIG. 13Bis substantially the same as the case where the silicide layer39is provided in a P-type/N-type silicon layer that configures a different element structure, such as a PIN structure, a MIS structure (e.g., a MIS diode) or a PN structure (e.g., a PN diode).

The high-temperature resistance of the silicide layer can be improved and the interface resistance can be reduced by adjusting the arrangement, in the cell unit, of the silicide layer39,39A,39B which includes an additional element having a greater atomic radius than the atomic radius of the 3d transition metal element or by adjusting the material serving as the base material for the silicide layer39,39A,39B as shown inFIG. 12AtoFIG. 13Cin accordance with the configurations of the memory cell array and the cell unit.

In the resistance change memory according to the present embodiment, the high-temperature resistance of the silicide layer is improved by the addition of the foreign element, so that the agglomeration or diffusion of the metal elements (atoms) included in the silicide layer and the erosion by the silicide layer can be inhibited. As a result, the breakdown voltage of the rectification element can be higher, and the output current of the rectification element when a reverse bias is applied can be reduced.

Furthermore, in the resistance change memory according to the present embodiment, the interface resistance of the silicon-silicide junction is reduced by the addition of the foreign element, so that the output current of the rectification element when a forward bias is applied can be increased.

Moreover, these improvements in the element characteristics can contribute to the thickness reduction of the element and the reduction of a cell area. As described above, according to the resistance change memory in the embodiment, characteristic deterioration of the element used in the resistance change memory can be inhibited.

(2) Manufacturing Method

(a) First Manufacturing Method

A first method of manufacturing the resistance change memory according to the present embodiment is described withFIG. 14AtoFIG. 14G. Here,FIG. 14AtoFIG. 14Eshow sectional process views taken along the second direction of a memory cell array in one step of the present manufacturing method. Further,FIG. 14FandFIG. 14Gshow sectional process views taken along the first direction of a memory cell array in one step of the present manufacturing method.

Although a memory element is stacked on a non-ohmic element in the structure of a cell unit formed in the case of this manufacturing method, this manufacturing method is not limited to this structure.

As shown inFIG. 14A, a conductive layer60X serving as a interconnect line is deposited on the substrate (e.g., an interlayer insulating film)11by, for example, a chemical vapor deposition (CVD) method or a sputter method.

A plurality of layers for forming a rectification element (non-ohmic element) of a cell unit are sequentially deposited on the conductive layer60X by, for example, the chemical vapor deposition (CVD) method.

For example, in case the rectification element is a PIN diode, three semiconductor layers31X,32X,33X are stacked. Semiconductor layers31X,32X,33X contain silicon, and are made of, for example, at least one of an SiC layer, an SiGe layer, an SiSn layer, a polycrystalline Si layer, an amorphous silicon layer and a monocrystalline Si layer. In the SiC layer, the ratio of C to Si is, for example, 0 atomic % to 3 atomic %. In the SiSn layer, the ratio of Sn to Si is, for example, 0 atomic % to 3 atomic %. In the SiGe layer, the ratio of Ge to Si is, for example, 0 atomic % to 30 atomic %.

In case that the rectification element in the cell unit is a PIN diode, one of semiconductor layers31X,33X is a P-type semiconductor layer (e.g., B-doped Si), and the other is an N-type semiconductor layer (e.g., P-doped Si). The semiconductor layer32X between the semiconductor layer31X and the semiconductor layer33X is an intrinsic semiconductor layer.

In case a PN diode is used as the rectification element, two semiconductor layers are stacked on the conductive layer60X. In case a MIS diode is used as the rectification element, a metal layer, an insulating layer and a semiconductor layer are stacked on the conductive layer60X.

The stacking order of two or more layers such as the semiconductor layers constituting the rectification element is appropriately changed depending on which of the circuit configurations, indicated by a to p ofFIG. 10, the cell unit has. For example, when the cell unit has the configuration indicated by “a” ofFIG. 10, the N-type semiconductor layer (cathode layer)31X having a thickness of about 5 nm to 30 nm is deposited on the conductive layer60X inFIG. 14A. The intrinsic semiconductor layer (I layer)32X having a thickness of about 50 nm to 120 nm is deposited on the N-type semiconductor layer31X. Further, the P-type semiconductor layer (e.g., an anode layer)33X having a thickness of about 5 nm to 30 nm is deposited on the intrinsic semiconductor layer32X.

Here, three stacked layers (semiconductor layers)31X,32X,33X are referred to as silicon layers31X,32X,33X.

In addition, a diffusion preventing layer, an adhesive layer and a high-concentration impurity layer may be formed between the conductive layer60X and the silicon layer31X.

A metal film59is deposited on the semiconductor layer33X by, for example, the sputter method or the CVD method. In the first manufacturing method according to the present embodiment, the metal film59is an alloy film. This alloy film includes a 3d transition metal element51, and an additional element52having an atomic radius greater than the atomic radius of the 3d transition metal element51.

For example, when Ni or Ti is used as the 3d transition metal element51, Pd or Pt is used as the additional element52. In addition, the metal film59may include two or more kinds of additional elements. For example, the metal film59may include both Pd and Pt.

The substrate11is performed to a thermal treatment (silicide treatment) for forming a silicide layer. For example, the silicon layer33serves as the source of silicon (hereinafter referred to as a base layer) for forming a silicide layer. The thermal treatment is conducted at a temperature ranging from, for example, 500° C. to 800° C. A rapid thermal annealing (RTA) method or other heating method may be used as a heating method for the silicide treatment.

A silicide reaction between the silicon layer33X and the alloy film59is caused by this thermal treatment. Therefore, as shown inFIG. 14B, the silicide layer39X is formed on the top of silicon layer33X. The silicide layer39X includes the Si element50derived from the silicon layer33X, the 3d transition metal element51derived from the alloy film, and the additional element52. Crystal grains constituting silicide layer39X are rendered microcrystal by the addition of a foreign element to a certain silicide.

InFIG. 14A, the ratio of the 3d transition metal element51and the additional element52included in the alloy film59is appropriately set on the basis of the stoichiometric composition ratio of the silicide layer39X to be formed or on the basis of an amount in which a desired high-temperature resistance and a desired work function are obtained. Similarly, the thickness of the alloy film59is set by a thickness relative to the thickness of the semiconductor layer33X so that desired silicide layer39X may be formed. The composition ratio and thickness of the silicide layer39to be formed may be controlled in accordance with the heating time or temperature of the silicide treatment.

In addition, due to the formation of the silicide layer39to which the foreign element52is added, a segregation layer (not shown) in which impurities (donor/acceptor) contained in the silicon layer33are segregated may be formed at the junction (interface) of the silicide layer39and the silicon layer33.

After the silicide treatment, the alloy film59which has not caused a silicide reaction with the silicon layer is removed by, for example, wet etching.

In addition, the silicide layer39X may further include elements (e.g., B, Ge) other than the Si element contained in the silicon layer33X.

As shown inFIG. 14C, a first electrode layer25X, a resistance change film21X and a second electrode layer26X are sequentially deposited on the silicide layer39X as constituent parts of the memory element. Electrode layers25X,26X are formed by, for example, the CVD method or sputter method. The resistance change film21X is formed by, for example, the sputter method, the CVD method, an atomic layer deposition (ALD) method, or a metal-organic CVD (MOCVD) method.

The materials for electrode layers25X,26X and the resistance change film21X are selected by the combination of materials whereby the resistance value of the resistance change film21X reversibly changes and the changed resistance value of the resistance change film21X is retained in a nonvolatile manner. However, the material for electrode layers25X,26X is not limited as long as the resistance change film21X itself reversibly changes its resistance value due to externally provided energy (e.g., a voltage or heat) and retains the changed resistance value.

As described above, a metal oxide, a metal compound or organic matter is used for the resistance change film21X. Thus, a high formation temperature of about 600° C. to 800° C. may be used, depending on the material that forms the resistance change film21X.

In the present embodiment, the silicide layer39X formed on the silicon layer33X includes an additional element having an atomic radius greater than the atomic radius of the 3d transition metal element, in addition to the Si element and the 3d transition metal element. Thus, as shown inFIG. 4toFIG. 6, crystal grains constituting the silicide layer39are rendered microcrystal, so that silicide layer39X has high high-temperature resistance (heat resistance).

Therefore, in the manufacturing method according to the present embodiment, agglomeration of metal elements for forming the silicide layer39X is not easily caused by the high-temperature thermal treatment, and the formation of resultant agglomerates in the silicide layer39X and silicon layers32X,33X thereunder is inhibited. The diffusion of the metal elements included in the silicide layer39X into silicon layers32X,33X is also inhibited. Moreover, the silicon layer33X is prevented from being reduced to a thickness smaller than a predetermined thickness due to excessive formation of the silicide layer39X resulting from the high-temperature thermal treatment, and the junction (interface) of two silicon layers is prevented from being broken due to the erosion of two silicon layers32X,33X by the silicide layer39X.

This reduces the need to increase the thickness of silicon layers31X,32X,33X to alleviate the adverse effects of the diffusion of the metal elements and the erosion by the silicide layer.

As shown inFIG. 14D, a mask (not shown) having a predetermined shape is formed on an electrode layer26Y. For example, each layer under the mask is processed in accordance with the shape of the mask by etching that uses a reactive ion etching (RIE) method. As a result, electrode layer25Y,26Y, a resistance change film21Y, a silicide layer39Y and silicon layers31Y,32Y,33Y are sequentially processed, and divided into cell units in the second direction with a predetermined space. Thus, a stack100is formed on substrate11. Formed stack100extends in the first direction. Simultaneously with the formation of the stack100, conductive layer is processed, and the interconnect line60extending in the second direction is formed on the substrate11.

Then, an interlayer insulating film69is embedded between adjacent stacks100by, for example, the CVD method or a coating method.

In addition, in this step, the stack may be divided in the first direction and a interconnect line extending in the second direction may be formed to form the first memory cell array M1shown inFIG. 2. However, in a cross-point type memory cell array, the cell unit and the memory cell array are preferably formed in the manufacturing process shown inFIG. 14EandFIG. 14Fwithout dividing stack100in the first direction immediately after the step shown inFIG. 14D.

As shown inFIG. 14EandFIG. 14F, conductive layer65X serving as a second interconnect line is deposited on stack100and interlayer insulating film69extending in the first direction. Then, layers to constitute the cell unit of a second memory cell array are sequentially deposited on conductive layer65X. The stacking order of the layers on conductive layer65X varies depending on which of the connection relations indicated by “a” to “p” ofFIG. 10two cell units shared by one interconnect line (conductive layer65X) have. For ease of explanation, the two cell units have the connection relation indicated by “a” ofFIG. 10in the case described here.

In the example shown inFIG. 14E, the stacking order of layers31X′,32X′,33X′,25X′,21X′,26X′ on a conductive layer65X is the same as the stacking order of the layers constituting stack100. The layers stacked on conductive layer65X are formed in the same manufacturing process as the layers constituting the stack100, respectively.

When the silicide layer39X′ is formed above stack100, the whole substrate is subjected to a high-temperature (about 500° C. to 800° C.) thermal treatment. The silicide layer39Y in the stack100is rendered microcrystal by the addition of a foreign element, and therefore has high-temperature resistance. Thus, in the stack100including the silicide layer39Y, adverse effects of the high-temperature thermal treatment, such as the diffusion of the metal elements included in the silicide layer39Y and the erosion of the silicon layer33Y by the silicide layer39Y are inhibited.

The stack100on the interconnect line60and the layers on the stack100are processed by a photolithographic technique and the RIE method in such a manner as to ensure the etching selectivity for the interconnect line60. The stack100extending in the first direction is divided into cell units in the first direction with a predetermined space. Simultaneously with the division of the stack in the first direction, The conductive layer65X on the stack is processed into individual patterns divided in the first direction, and an interconnect line65extending in the second direction is formed on the stack disposed on the interconnect line60extending in the first direction.

As shown inFIG. 14G, cell unit CU1is formed between the interconnect line60extending in the first direction and the interconnect line65extending in the second direction.

In a cell unit CU1, a rectification element (non-ohmic element)30has a silicide layer39at the top, and the silicide layer39is provided on the top surface of a silicon layer33. Further, a memory element20is provided on the silicide layer39.

Moreover, since the layers are etched starting from the upper layer in order, a stack100′ is formed on the cell unit CU1with the interconnect line65in between. Similarly to the interconnect line65, the stack100′ is divided in the first direction with a predetermined space. In the step shown inFIG. 14G, the stack100′ extends in the second direction, in the same manner as inFIG. 14E. In the cross-point type memory cell array, the stack100′ is processed in the second direction into a cell unit CU2of a (second-layer) memory cell array to be higher than the first-layer memory cell array.

Interlayer insulating films are embedded between cell units CU1adjacent in the first direction and between stacks100′ adjacent in the first direction.

Here, in case memory cell arrays are further provided on stacks100′, the process similar to the process shown inFIG. 14EtoFIG. 14Gis repeated before a predetermined number of memory cell arrays are stacked.

As shown inFIG. 14EtoFIG. 14G, the second-layer memory cell array is processed simultaneously with the formation of the first-layer memory cell array on the substrate11.

Thus, the formation of the upper memory cell array and the processing of the lower memory cell array are carried out in a common step, so that the process of manufacturing the resistance change memory having the cross-point type memory cell array is simpler and its manufacturing costs are lower than when each memory cell array in each layer (interconnection level) is processed in the first and second directions.

In the case described withFIG. 14AtoFIG. 14E, the silicide layer is formed at the top of the rectification element. When silicide layer39is formed at the bottom of the rectification element as in12B andFIG. 12C, the alloy film formed between the conductive layer60X and the silicon layer is subjected to silicidation together with the silicon layer, so that the silicide layer39is formed on the bottom of the silicon layer. The silicon layer to form the silicide layer39may be the silicon layer31X,33X or may be a layer formed separately from the silicon layer31X,33X.

In the case described withFIG. 14B, the alloy film59which has not caused a silicide reaction with the silicon layer is removed by, for example, wet etching after the silicide treatment. However, the alloy film which has not caused a silicide reaction may remain on the silicide layer39X for use as the diffusion preventing layer, the adhesive layer, or as part of the electrode of the rectification element or the memory element.

For example, as shown inFIG. 14H, the resistance change film21X and the second electrode layer26X may be sequentially deposited as constituent parts of the memory element on the metal film (alloy film)59used as the first electrode layer. As a result, the step of separately depositing lower electrode (first electrode layer) of the memory element can be eliminated, and the process of manufacturing the resistance change memory can be simpler.

As described above, in the first method of manufacturing the resistance change memory according to the present embodiment, the silicide layer39is provided on at least one end (top) or the other end (bottom) of non-ohmic element (rectification element)30. The silicide layer39includes the Si element50and the 3d transition metal element51, and also includes the element (additional element)52having an atomic radius greater than the atomic radius of the 3d transition metal element51. In this manufacturing method, the silicide layer39is formed by the thermal treatment at 500° C. or more for the metal film (alloy film) including the 3d transition metal element51and the additional element52and for the silicon layer.

As shown inFIG. 4toFIG. 6, the silicide layer39included in the resistance change memory according to the present embodiment includes the additional element52and thus has high-temperature resistance. Therefore, even if a high-temperature thermal treatment is included in the method of manufacturing a semiconductor device such as the resistance change memory, agglomeration of the metal elements (atoms) included in the silicide layer, diffusion of the metal elements into other constituent elements (e.g., the silicon layer) and the erosion of other parts by silicide can be inhibited.

As a result, in the resistance change memory according to the present embodiment, characteristic deterioration of the non-ohmic element caused when silicide having low heat resistance, such as the increase of a reverse current of the rectification element when a reverse bias is applied is reduced.

Furthermore, there is no need to increase the thickness of the silicon layer33X in order to alleviate effects of the diffusion of the metal elements and the erosion by the silicide layer. Therefore, the thickness (height in the stacking direction) of the non-ohmic element (rectification element) is smaller, and the aspect ratio of the cell unit (stack) is lower.

Thus, the processing (etching) to form the cell unit is relatively easy, and the embedding quality of the interlayer insulating film between adjacent cell unit is improved.

As shown inFIG. 14EtoFIG. 14G, the aspect ratio increases when two stacked memory cell arrays (cell units) are simultaneously processed, so that reducing the thickness of the non-ohmic element to hold down the increase of the aspect ratio is effective.

In addition, since the height of the non-ohmic element is smaller, there is no need to have a large space between adjacent cell units to ensure a margin for processing. This enables a reduction in the area of the memory cell array of the resistance change memory.

Furthermore, as shown inFIG. 7AandFIG. 7B, the work function of silicide can be adjusted by the addition of the additional element52to a certain silicide. This enables a reduction in the resistance of the interface between the silicide layer39and the semiconductor layer33.

As a result, a current loss attributed to the interface resistance is reduced. For example, the upper limit value of the forward current when a forward bias is applied is higher in the rectification element, and the output of the forward current of the rectification element is higher than the value of a certain applied voltage. Thus, the current (voltage) that can be supplied to the memory element20is higher at a certain drive voltage applied to a selected cell unit.

As described above, according to the resistance change memory manufacturing method in the embodiment, a resistance change memory in which deterioration of element characteristics is inhibited can be provided.

(b) Second Manufacturing Method

A second method of manufacturing the resistance change memory according to the embodiment is described withFIG. 15AtoFIG. 15D.FIG. 15AtoFIG. 15Dshow sectional process views taken along the second direction of a memory cell array in one step of the present manufacturing method. It is to be noted that parts equivalent to the parts described in the first manufacturing method are denoted with the same reference numbers and are not described. It is also to be noted that steps equivalent to the steps in the first manufacturing method described withFIG. 14AtoFIG. 14Gare not described here.

The second method of manufacturing the resistance change memory according to the present embodiment is different from the first manufacturing method in that a metal film including one kind of the 3d transition metal element51is deposited separately from a metal film including at least one kind of the element52having an atomic radius greater than the atomic radius of the 3d transition metal element51.

As shown inFIG. 15A, a metal film57containing the 3d transition metal element51as the main component is formed on the silicon layer33X. Further, a metal film58containing the additional element52as the main component is formed on the metal film57.

Layers33X,57,58are thermally treated, so that elements51,52in two metal films57,58cause a silicide reaction with the Si element in the silicon layer33X, and the silicide layer39X is formed on the silicon layer33X as inFIG. 14B.

As shown inFIG. 15B, the metal film58containing the additional element52may be deposited on the silicon layer33X, and the metal film57containing the 3d transition metal element51may be deposited on the metal film58.

As shown inFIG. 15AandFIG. 15B, in the second method of manufacturing the resistance change memory according to the present embodiment, a silicide layer which has high-temperature resistance and which can reduce the resistance of the interface with the silicon layer33X can be formed as in the first manufacturing method described above.

Furthermore, metal films57,58which have not caused a silicide reaction with silicon may remain on the silicide layer38X for use as part of the electrode of the memory element.

For example, when the step of removing the metal film which has not caused a silicide reaction with the silicon layer after the step inFIG. 15Ais omitted, the metal film58can be used for the first electrode layer (the lower electrode of the memory element).

For example, as shown inFIG. 15C, the resistance change film21X and the second electrode layer26X are sequentially deposited as constituent parts of the memory element on the metal film58used as the first electrode layer. As a result, the step of separately depositing the first electrode layer can be eliminated, and the manufacturing process can be simplified.

Similarly, if the step of removing the metal film which has not caused a silicide reaction with the silicon layer after the step inFIG. 15Bis omitted, the metal film57can be used for the first electrode layer (the lower electrode of the memory element).

For example, as shown inFIG. 15D, the resistance change film21X and the second electrode layer26X are sequentially deposited as constituent parts of the memory element on the metal film57used as the first electrode layer. As a result, the step of separately depositing the first electrode layer can be eliminated, and the manufacturing process can be simplified.

Consequently, according to the second method of manufacturing the resistance change memory in the embodiment, a resistance change memory in which deterioration of element characteristics is inhibited can be provided as in the first manufacturing method.

(c) Third Manufacturing Method

A third method of manufacturing the resistance change memory according to the embodiment is described withFIG. 16AtoFIG. 16D.FIG. 16AtoFIG. 16Dshow sectional process views taken along the second direction of a memory cell array in one step of the present manufacturing method. It is to be noted that parts equivalent to the parts described in the first and second manufacturing methods are provided with the same reference numbers and are not described. It is also to be noted that steps equivalent to the steps in the first and second manufacturing methods are not described here.

The third method of manufacturing the resistance change memory according to the present embodiment is different from the first and second manufacturing methods in that a silicide layer including the Si element50and the 3d transition metal element51is formed and then the additional element52having an atomic radius greater than the atomic radius of the 3d transition metal element51is added to the formed silicide layer.

As shown inFIG. 16A, a silicide layer (hereinafter referred to as a base silicide layer)37including the Si element50and the 3d transition metal element51is formed on the silicon layer33X. The base silicide layer37is formed by, for example, a silicide reaction between the silicon layer33X and the 3d transition metal element. After the base silicide layer37is formed, the metal film58is deposited on the silicide layer37. The metal film58includes the element52having an atomic radius greater than the atomic radius of the 3d transition metal element51.

The base silicide layer37and the metal film58are thermally treated, and the element52included in the metal film58diffuses into the base silicide layer37. Diffused element52chemically reacts (is bonded) with the Si element50and the metal element51in the silicide layer37. Thus, the element52is added into the base silicide layer37including the Si element50and the 3d transition metal element51.

Thus, in the same manner as shown inFIG. 14B, the silicide layer39including the Si element50, the 3d transition metal element51, and the element52having an atomic radius greater than the atomic radius of the element51is formed on the silicon layer33X.

As shown inFIG. 16B, the metal film57containing the 3d transition metal element51as the main component may be deposited on a compound layer38including the Si element50and the additional element52. In this case, the Si element50in the compound layer38and the 3d transition metal element51in the metal film57cause a silicide reaction due to a thermal treatment, and the silicide layer39shown inFIG. 14Bis formed. In addition, the compound layer38may be a silicide layer composed of the Si element50and the additional element52, depending on the kind of selected additional element52.

As shown inFIG. 16AandFIG. 16B, in the third method of manufacturing the resistance change memory according to the present embodiment, a silicide layer which has high-temperature resistance and which can reduce the resistance of the interface with the silicon layer33X can be formed as in the first and second manufacturing methods.

Furthermore, metal films57,58, which have not diffused into the silicide layer, may remain on the silicide layer38X for use as part of the electrode of the memory element.

For example, when the step of removing the metal film which has not caused a silicide reaction with the silicon layer after the step inFIG. 16Ais omitted, the metal film58can be used for the first electrode layer (the lower electrode of the memory element).

For example, as indicated byFIG. 16C, the resistance change film21X and the second electrode layer26X are sequentially deposited as constituent parts of the memory element on the metal film58used as the first electrode layer. As a result, the step of separately depositing the first electrode layer can be eliminated, and the manufacturing process can be simplified.

Similarly, when the step of removing the metal film which has not caused a silicide reaction with the silicon layer after the step inFIG. 16Bis omitted, the metal film57can be used for the first electrode layer (the lower electrode of the memory element).

For example, as shown inFIG. 16D, the resistance change film21X and the second electrode layer26X are sequentially deposited as constituent parts of the memory element on the metal film58used as the first electrode layer. As a result, the step of separately depositing the first electrode layer can be eliminated, and the manufacturing process can be simplified.

Consequently, according to the third method of manufacturing the resistance change memory in the embodiment, a resistance change memory in which deterioration of element characteristics is inhibited can be provided as in the first and second manufacturing methods.

(d) Fourth Manufacturing Method

A fourth method of manufacturing the resistance change memory according to the embodiment is described withFIG. 17AandFIG. 17B.FIG. 17AandFIG. 17Bshow sectional process views taken along the second direction of a memory cell array in one step of the present manufacturing method. It is to be noted that parts equivalent to the parts described in the first to third manufacturing methods are provided with the same reference numbers and are not described. It is also to be noted that steps equivalent to the steps in the first to third manufacturing methods are not described here.

The fourth method of manufacturing the resistance change memory according to the present embodiment is different from the first to third manufacturing methods in that an element having an atomic radius greater than the atomic radius of a 3d transition metal element is added into a silicide layer by ion implantation.

As shown inFIG. 17A, a predetermined dose amount of ionized element52is implanted the into the base silicide layer37including the Si element50and the 3d transition metal element51by an ion implantation method. The silicide layer37into which the element52has been implanted is thermally treated. As a result of this thermal treatment, the element52implanted into the silicide layer37is activated in the silicide layer37, and added element52chemically reacts (is bonded) with the Si element50and/or the 3d transition metal element51in the silicide layer37. Thus, as shown inFIG. 14B, the silicide layer39including the Si element50, the 3d transition metal element51, and the element52having an atomic radius greater than the atomic radius of the element51is formed on the silicon layer33X.

As shown inFIG. 17B, ionized 3d transition metal element51may be implanted into the compound layer38including the Si element50and the additional element52. Then, a thermal treatment is carried out as shown inFIG. 17A, so that implanted 3d transition metal element51causes a silicide reaction with the Si element52in compound layer38, and the silicide layer39is formed on the silicon layer33X.

Moreover, both the 3d transition metal element51and the additional element52may be implanted into the silicon layer33X by the ion implantation method. In this case as well, the silicide layer39is formed by carrying out a thermal treatment.

As shown inFIG. 17AandFIG. 17B, in the fourth method of manufacturing the resistance change memory according to the present embodiment, a silicide layer which has high-temperature resistance and which can reduce the resistance of the interface with the silicon layer33X can be formed as in the first to third manufacturing methods.

Furthermore, if a silicide layer including the additional element52is formed by the ion implantation method as in the fourth manufacturing method described above, the silicide layer39including the additional element can be formed at a lower heating temperature than when the additional element52is formed in the silicide layer only by the thermal treatment. That is, in the fourth manufacturing method, the temperature of the thermal treatment for forming the silicide layer39can be lower.

Thus, when a plurality of memory cell arrays are stacked as in the case of the cross-point type memory cell arrays, heat for forming silicide layer39can be inhibited from being repeatedly provided to the lower layer memory cell arrays. This makes it possible to reduce the deterioration of element characteristics resulting from the history of a plurality of thermal treatments and reduce the difference of element characteristics between the upper layer element and the lower layer element.

Furthermore, the thermal treatment for forming the silicide layer39can inhibit impurities (e.g., carbon) in the interlayer insulating film and metal elements included in interconnect lines and the electrodes from diffusing into semiconductor layers31X,32X,33X or the resistance change film21X. This makes it possible to inhibit the deterioration of element characteristics resulting from the diffusion of impurities.

Consequently, according to the fourth method of manufacturing the resistance change memory in the embodiment, a resistance change memory in which deterioration of element characteristics is inhibited can be provided as in the first to third manufacturing methods.

(e) Fifth Manufacturing Method

A fifth method of manufacturing the resistance change memory according to the embodiment is described withFIG. 18AandFIG. 18B.FIG. 18AandFIG. 18Bshow sectional process views taken along the second direction of a memory cell array in one step of the present manufacturing method. It is to be noted that parts equivalent to the parts described in the first to fourth manufacturing methods are provided with the same reference numbers and are not described. It is also to be noted that steps equivalent to the steps in the first to fourth manufacturing methods are not described here.

In the cases described in the first to fourth manufacturing methods, the silicide layer including the Si element, the 3d transition metal element and the additional element is formed before a plurality of layers to constitute the cell unit are processed into a stack of a predetermined shape (size). However, the silicide layer may be formed after the stack is formed.

In the case described withFIG. 18A, a non-ohmic element (rectification element) forming a cell unit is stacked on a memory element.

For example, as shown inFIG. 18A, the electrode layer25Y, the resistance change film21Y and the electrode layer26Y are sequentially deposited on the conductive layer60. Further, three silicon layers31Y,32Y,33Y are sequentially deposited on the electrode layer26Y.

As shown in the step shown inFIG. 14D, the stack100is formed by the photolithographic technique and the RIE method. Then, the interlayer insulating film69is embedded between adjacent stacks100.

After the stack100is formed, the metal film59, for example, is deposited on semiconductor layer33Y and on the interlayer insulating film69. The metal film59includes the 3d transition metal element51, and the element52having an atomic radius greater than the atomic radius of the 3d transition metal element.

Furthermore, the 3d transition metal element included in the metal film59causes a silicide reaction with the Si element included in the silicon layer33Y due to the thermal treatment for the metal film59and the silicon layer33Y, and a silicide layer is formed. The additional element in the metal film59is added into the silicide layer.

Thus, the silicide layer39including an Si element, a 3d transition metal element, and an element having an atomic radius greater than the atomic radius of the 3d transition metal element is formed on the end (top) of the silicon layer33Y after stack100is formed.

The step in which the silicide layer used in the present embodiment is formed after being processed into a stack as in the fifth method of manufacturing the resistance change memory according to the present embodiment is effective in the structure in which the rectification element30is stacked on the memory element20as in cell unit CU shown inFIG. 12DorFIG. 12F.

However, even when a memory element is stacked on a rectification element, silicon layers31Y,32Y,33Y constituting the rectification element may be once processed, and a silicide layer may be formed by a method similar to that inFIG. 18A, as shown inFIG. 18B.

In the case described here, the above-described first manufacturing method is used to form the silicide layer including the 3d transition metal element51and the additional element52after the processing of the stack. However, it goes without saying that the above-described second to fourth manufacturing methods can also be used to form the silicide layer after the processing of the stack as inFIG. 18AtoFIG. 18C.

Consequently, according to the fifth method of manufacturing the resistance change memory in the embodiment, a resistance change memory in which deterioration of element characteristics is inhibited can be provided as in the first and second manufacturing methods.

The operation of the resistance change memory is described next.

Memory cell array M1corresponds to memory cell array M1shown inFIG. 2, and memory cell array M2corresponds to memory cell array M2shown inFIG. 2. The connection between the memory element and the non-ohmic element (e.g., a rectification element) in cell unit CU1, CU2corresponds to “a” ofFIG. 10.

A. Set Operation

First described is the case where a writing (set) operation is performed on selected cell unit CU1-sel in memory cell array M1.

The initial state of selected cell unit CU1-sel is an erased (reset) state.

For example, the reset state is a high-resistance state (100 kΩ to 1 MΩ), and the set state is a low-resistance state (1 kΩ to 10 kΩ).

Selected interconnect line L2(i) is connected to high-potential-side power supply potential Vdd, and selected interconnect line L1(j) is connected to low-potential-side power supply potential Vss.

Among first interconnect lines from the substrate side, unselected interconnect lines L1(j−1), L1(j+1) other than selected interconnect line L1(j) are connected to power supply potential Vdd. Among second interconnect lines from the substrate side, unselected interconnect lines L2(i+1) other than selected interconnect line L2(i) are connected to power supply potential Vss.

Furthermore, third unselected interconnect lines L3(j−1), L3(j), L3(j+1) from the substrate side are connected to power supply potential Vss.

In this case, a forward bias is applied to the rectification element (e.g., a diode) in selected cell unit CU1-sel. Thus, set current I-set from a constant current source12runs through selected cell unit CU1-sel, and the resistance value of the memory element in selected cell unit CU1-sel changes from the high-resistance state to the low-resistance state.

Here, in the set operation, a voltage of, for example, about 1 V to 2 V is applied to the memory element in selected cell unit CU1-sel, and the density of set current I-set running through the memory element (high-resistance state) is set at a value ranging, for example, from 1×105to 1×107A/cm2. In addition, when the change of the resistance value of the memory element in the set operation depends on the pulse width of the current, the pulse width of a set current is appropriately set at a predetermined pulse width.

On the other hand, a reverse bias is applied to the rectification element (diode) in the cell unit which is connected between unselected interconnect lines L1(j−1), L1(j+1) and unselected interconnect line L2(i+1), among unselected cell units CU1-unsel in memory cell array M1.

Similarly, a reverse bias is applied to the rectification element (diode) in the cell unit which is connected between selected interconnect line L2(i) and unselected interconnect lines L3(j−1), L3(j), L3(j+1), among unselected cell units CU2-unsel in memory cell array M2.

Therefore, the following characteristics are required for the rectification element in the cell unit: a sufficiently low current when a reverse bias is applied, and a sufficiently high breakdown voltage.

B. Reset Operation

Next described is the case where an erasing (reset) operation is performed on selected cell unit CU1-sel in memory cell array M1.

Selected interconnect line L2(i) is connected to high-potential-side power supply potential Vdd, and selected interconnect line L1(j) is connected to low-potential-side power supply potential Vss.

Among first interconnect lines from the substrate side, unselected interconnect lines L1(j−1), L1(j+1) other than selected interconnect line L1(j) are connected to power supply potential Vdd. Among second interconnect lines from the substrate side, unselected interconnect lines L2(i+1) other than selected interconnect line L2(i) are connected to power supply potential Vss.

Furthermore, third unselected interconnect lines L3(j−1), L3(j), L3(j+1) from the substrate side are connected to power supply potential Vss.

In this case, a forward bias is applied to the rectification element (e.g., a diode) in selected cell unit CU1-sel. Thus, reset current I-reset from a constant current source12runs through selected cell unit CU1-sel, and the resistance value of the memory element in selected cell unit CU1-sel changes from the low-resistance state to the high-resistance state.

Here, in the reset operation, a voltage of, for example, about 1 V to 3 V is applied to the memory element in selected cell unit CU1-sel, and the density of reset current I-reset running through the memory element (low-resistance state) is set at a value ranging, for example, from 1×103to 1×106A/cm2. In addition, when the change of the resistance value of the memory element in the reset operation depends on the pulse width of the current, the pulse width of a reset current is appropriately set at a predetermined pulse width.

On the other hand, a reverse bias is applied to the rectification element (diode) in the cell unit which is connected between unselected interconnect lines L1(j−1), L1(j+1) and unselected interconnect line L2(i+1), among unselected cell units CU1-unsel in memory cell array M1.

Similarly, a reverse bias is applied to the rectification element (diode) in the cell unit which is connected between selected interconnect line L2(i) and unselected interconnect lines L3(j−1), L3(j), L3(j+1), among unselected cell units CU2-unsel in memory cell array M2.

Therefore, the following characteristics are required for the rectification element in the cell unit: a sufficiently low current when a reverse bias is applied, and a sufficiently high breakdown voltage.

In addition, the value of set current I-set and the value of reset current I-reset are different from each other. Moreover, when the set/reset operation of the memory element depends on the pulse width of the current/voltage, the pulse width of the set current and the pulse width of the reset current are different from each other. Further, the value/time of the voltage applied to the memory element in selected cell unit CU1-sel for generating these currents depends on the materials constituting the memory element.

C. Read Operation

Next described is the case where a read operation is performed on selected cell unit CU1-sel in memory cell array M1.

Selected interconnect line L2(i) is connected to high-potential-side power supply potential Vdd, and selected interconnect line L1(j) is connected to low-potential-side power supply potential Vss.

Among first interconnect lines from the substrate side, unselected interconnect lines L1(j−1), L1(j+1) other than selected interconnect line L1(j) are connected to power supply potential Vdd. Among second interconnect lines from the substrate side, unselected interconnect lines L2(i+1) other than selected interconnect line L2(i) are connected to power supply potential Vss.

Furthermore, third unselected interconnect lines L3(j−1), L3(j), L3(j+1) from the substrate side are connected to power supply potential Vss.

In this case, a forward bias is applied to the rectification element (e.g., diode) in selected cell unit CU1-sel. Thus, read current I-read from a constant current source12runs through the memory element in selected cell unit CU1-sel (the high-resistance state or the low-resistance state).

Therefore, for example, by detecting a potential change in a sense node when read current I-read is running through the memory element, data (resistance value) in the memory element can be read.

Here, the value of read current I-read is much lower than the value of set current I-set and the value of reset current I-reset so that the resistance value of the memory element may not change in reading. When the change of the resistance value of the memory element depends on the pulse width of the current, the pulse width of the read current is set at a pulse width that does not change the resistance value of the memory element.

In reading, as in setting/resetting, a reverse bias is applied to the rectification element (diode) in the cell unit which is connected between unselected interconnect lines L1(j−1), L1(j+1) and unselected interconnect line L2(i+1), among unselected cell units CU1-unsel in memory cell array M1.

A reverse bias is also applied to the rectification element (diode) in the cell unit which is connected between selected interconnect line L2(i) and unselected interconnect lines L3(j−1), L3(j), L3(j+1), among unselected cell units CU2-unsel in memory cell array M2.

Thus, the following characteristics are required for the rectification element in the cell unit: a sufficiently low current when a reverse bias is applied, and a sufficiently high breakdown voltage.

The set/reset operation and read operation of the resistance change memory are performed as described above.

As described above, the resistance change memory according to the present embodiment has silicide layer39on at least one of both ends of the non-ohmic element (e.g., a rectification element) forming the cell unit as shown inFIG. 3. The silicide layer39includes the Si element50, the 3d transition metal element51that combines with the Si element50to form silicide, and the additional element (foreign element)52having an atomic radius greater than the atomic radius of the 3d transition metal element51.

Since silicide layer39included in the resistance change memory according to the present embodiment has high high-temperature resistance (high heat resistance) owing to the addition of the foreign element, the agglomeration and diffusion of the metal elements (atoms) included in the silicide layer and the erosion of silicon layer by the silicide layer are not easily caused.

In the resistance change memory according to the present embodiment, adverse effects of such a high-temperature thermal treatment on the silicide layer can be inhibited, so that, for example, a reverse current at the time of reverse bias application can be reduced, and a high breakdown voltage can be ensured.

Thus, in the resistance change memory according to the present embodiment, even if a high-temperature thermal treatment is carried out in its manufacturing process, deterioration in the reverse bias characteristics of the rectification element can be inhibited. Since the deterioration in the reverse bias characteristics of the unselected cell unit can be inhibited, wrong operation (e.g., wrong writing) of the unselected cell unit, such as the supply of an excessive current to the unselected cell unit, can be decreased.

In addition, in any of the set/reset operation and read operation, the number of unselected cell units is greater than the number of selected cell units.

Therefore, if the reverse bias characteristics of the unselected cell unit are deteriorated, the total amount of the reverse current generated in the whole memory cell array is significantly great. As a result, the power consumption of cross-point type memory cell array2inFIG. 2is increased.

On the contrary, since the deterioration in the reverse bias characteristics of the rectification element can be inhibited in the resistance change memory according to the present embodiment, the increase of the power consumption of the resistance change memory can be inhibited.

The work function of the silicide layer included in the resistance change memory according to the present embodiment can be modulated by the addition of the foreign element to silicide. That is, by properly selecting the kind and addition amount of the foreign element added to a certain silicide, the interface resistance of the silicon-silicide junction can be reduced, and a current loss resulting from the interface resistance can be reduced.

Thus, in the resistance change memory according to the present embodiment, the upper limit of the forward current when a forward bias is applied can be improved, and the forward current of the rectification element at a certain forward bias voltage can be higher.

Therefore, in the resistance change memory according to the present embodiment, a current of an intensity sufficient to accurately perform the set/reset operation can be supplied to the memory element of the selected cell unit. The improvement of the characteristics of the rectification element when a forward bias is applied can also contribute to the reduction of the power consumption of the resistance change memory.

Consequently, characteristic deterioration of constituent elements (e.g., a rectification element) including silicide can be inhibited.

As described above, the silicide layer39including the Si element50, the 3d transition metal element51that combines with the Si element50to form silicide, and the additional element52having an atomic radius greater than the atomic radius of element51is used to form the non-ohmic element (e.g., a rectification element). This inhibits the change of the quality of the silicide layer attributed to the high-temperature thermal treatment and resultant adverse effects on the elements, reduces the interface resistance of the silicide layer, and improves the electric characteristics of the elements.

Thus, according to the resistance change memory in the embodiment of the present invention, deterioration of the element characteristics of the resistance change memory can be inhibited.

A modification of the resistance change memory according to the embodiment is described withFIG. 20AtoFIG. 21.

Modification 1 of the resistance change memory according to the embodiment is described withFIG. 20AandFIG. 20B.

FIG. 20Aschematically shows a modification of the silicide layer used in the cell unit.

In the modification shown inFIG. 20A, a silicide layer39D includes two or more kinds of additional elements52,53selected from the above-mentioned additional element group.

Atomic radius r3of the second additional element53may be greater than atomic radius r2of the first additional element52, or may be equal to or less than atomic radius r2.

Here, this modification is described taking as an example the case where Pd and Pt are added to NiSiy.

In case a cross-point type memory cell array of the resistance change memory is provided above a substrate in which peripheral circuits are formed so that an interlayer insulating film intervenes therebetween, a thermal treatment for forming silicide may cause deterioration of the element formed by a front-end process as in the case of, for example, the effect of slipping into the edge of an element isolation insulating film. Moreover, in, for example, a back-end process for forming a memory cell array, the temperature used for the thermal treatment is preferably lowered to the extent possible.

As has been described withFIG. 4, the temperature of Pd-added NiSiy(Ni1−xPdxSiy) at which a silicide reaction is caused is higher than that of Pt-added NiSiy(Ni1−xPtxSiy). In other words, Ni1−xPtxSiycan be formed at a relatively low heating temperature.

Furthermore, Ni1−xPdxSiyhas lower electric resistance and higher high-temperature resistance than Ni1−xPtxSiy. When Ni1−xPdxSiyand Ni1−xPtxSiyare combined together using such a characteristic difference, silicide which maintains high high-temperature resistance and low electric resistance and which can be formed at a low temperature can be provided.

In NiSiyincluding both Pt and Pd, the addition amount of Pt has only to be greater than the addition amount of Pd to decrease the reaction temperature (heating temperature) of silicide layer39D.

Moreover, in NiSiyincluding both Pt and Pd, the addition amount of Pd has only to be greater than the addition amount of Pt to decrease electric resistance and improve high-temperature resistance.

Thus, by adding two or more kinds of additional elements to a certain silicide, the characteristics of the silicide layer39D can be adjusted to better suit the operation characteristics and manufacturing process of the resistance change memory.

As a result, the element of the resistance change memory formed in both the front-end process and back-end process can be inhibited from characteristic deterioration due to a high-temperature thermal treatment.

FIG. 20Bschematically shows a modification different from the modification inFIG. 20A.

Silicide layer39E to which a foreign element is added is formed by, for example, the heating treatment of a metal film and a Si element or by ion implantation of an element into a layer including Si, in accordance with the manufacturing method described above.

Thus, SiC, SiGe or SiSn, for example, is used for the layer as a base layer including Si. These substances are subjected to silicidation, or a foreign element is added to these substances.

Furthermore, part of the N-type silicon layer or P-type silicon layer may be silicidated depending on the structure and characteristics of the non-ohmic element, and a silicide layer39E may be thereby formed. Therefore, an element (e.g., P or As) serving as a donor for Si or an element (e.g., B) serving as an acceptor for Si may be included in the silicide layer39E.

Moreover, an oxide film or nitride film may be formed on the surface of the silicon layer in the process of manufacturing the memory.

Thus, as shown inFIG. 20B, silicide layer39E may include one or more kinds of elements54derived from a layer (base layer) including a Si element for forming the silicide layer39E, such as C, Ge, Sn, P, As, B, O and N, in addition to the Si element50, the 3d transition metal element51and the additional element52.

These elements54are mainly lattice-substituted for the Si element50.

It goes without saying that effects substantially similar to the effects obtained by the resistance change memories described in Basic example and Example can be obtained by the resistance change memory in Modification 1 shown inFIG. 20AandFIG. 20B.

Modification 2 of the resistance change memory according to the embodiment is described withFIG. 21AtoFIG. 21C.

For a interconnect line used as a word line/bit line, silicide may be used instead of a metal such as Cu or Al or a metal compound.

Therefore, a silicide layer including a Si element, a 3d transition metal element and an additional element may be used for interconnect lines60,65.

InFIG. 21A, a lower interconnect line is formed of the silicide layer39. InFIG. 21B, an upper interconnect line is formed of the silicide layer39. InFIG. 21C, both of two interconnect lines are formed of the silicide layers39.

In addition, interconnect line60,65may have a stack structure including a metal layer and silicide layer39.

It goes without saying that effects substantially similar to the effects obtained by the resistance change memories described in Basic example and Example can be obtained by the resistance change memory in Modification 2 shown inFIG. 21AtoFIG. 21C.

An application of the embodiment is described withFIG. 22toFIG. 26.

In the resistance change memory, memory cell array2shown inFIG. 2is formed by, for example, a back-end process. On the other hand, field effect transistors (FET) that configure peripheral circuits such as the control circuits3,4are formed by a front-end process. As shown inFIG. 22, field effect transistor Tr of the peripheral circuit is formed on a semiconductor substrate (silicon substrate) under the memory cell array2.

FIG. 22shows one example of the sectional structure of field effect transistor Tr used in the peripheral circuit. A section of the field effect transistor in a channel length direction is shown inFIG. 22.

As shown inFIG. 22, the same material as that of the silicide layer included in the cell unit according to the embodiment may be used for gate electrodes73,391of field effect transistor Tr and for source/drain electrodes392,393of field effect transistor Tr.

A P-well71A and an N-well71B are provided in a semiconductor substrate70. The P-well71A and N-well71B are electrically isolated from each other by an element isolation insulating film79in the semiconductor substrate70.

An N-channel field effect transistor Tr is provided in the P-well71A. A P-channel field effect transistor is provided in the N-well71B. P-channel and N-channel field effect transistors are substantially the same in configuration. Therefore, the structure of transistor Tr in the P-well71A is described here.

Two diffusion layers74,75are provided in P-well71A. Diffusion layers74,75are used as the source/drain of transistor Tr. Source/drain electrodes392,393are provided on the surfaces of diffusion layers74,75.

A gate insulating film72is provided on the surface of the well71between two diffusion layers74,75. A gate electrode73,391are provided on the gate insulating film72. The top of the gate electrode is formed of the silicide layer391, and the bottom of the gate electrode is formed of the silicon layer73.

A sidewall insulating film76is provided on the side portions of gate electrode73,391.

Contacts CP1, CP2, CP3and interconnect lines M1, M2, M3are provided in interlayer insulating films77A,77B. A metal such as W is used for contacts CP1, CP2, CP3.

An upper electrode391of the gate electrode and source/drain electrodes392,393are formed of silicide layers391,392,393in which a foreign element (additional element) is added to silicide including an Si element and a 3d transition metal element.

In silicide layers391,392,393used for the field effect transistor, the atomic radius of the added foreign element is greater than the atomic radius of the 3d transition metal element, similarly to the silicide layer used for the cell unit described withFIG. 3. In addition, one or more kinds of elements may be added to silicide layers391,392,393.

The field effect transistor shown inFIG. 22is formed by the following manufacturing method.

FIG. 23shows one example of the field effect transistor manufacturing method.

As shown inFIG. 23, wells71A,71B and the element isolation insulating film79are formed in the semiconductor substrate (silicon substrate)70.

The gate insulating film72is formed on the surfaces of wells71A,71B by, for example, a thermal oxidation method or the CVD method. A silicon layer is deposited on the gate insulating film72by, for example, the CVD method. The silicon layer is processed into a gate electrode73A of a predetermined shape by the photolithographic technique and the RIE method.

Furthermore, the gate electrode73A is used as a mask, so that diffusion layers74,75are formed in wells71A,71B by the ion implantation method. When an N-type diffusion layer is formed in the P-well71A, the surface of the well71B is covered with a mask (resist). In contrast, when a P-type diffusion layer is formed in the N-well71B, the surface of the P-well71A is covered with a mask (resist).

After diffusion layers (source/drain)74,75are formed in the P-well71A, the sidewall insulating film76is formed on the side surface of the gate electrode73A by the CVD method and the RIE (etch back) method.

Then, the gate electrode73A having a silicon single-layer structure and the surfaces of diffusion layers74,75in the silicon substrate are subjected to silicidation. When the transistor formed in the P-well is only subjected to silicidation, the surface of the N-well71B is covered with the mask (insulating film)78, as shown inFIG. 23.

As shown inFIG. 23, the metal film59including a 3d transition metal element and other elements (additional elements) is formed on the gate electrode73A and diffusion layers74,75by the sputter method or the CVD method, in the same manner as in the manufacturing method shown inFIG. 14AandFIG. 14B. Then, the substrate70is thermally treated, and the metal film59and silicon cause a silicide reaction.

However, any one of the second to fourth manufacturing methods described in Example may be used as the method of forming a silicide layer in the gate electrode of the transistor.

Thus, as shown inFIG. 22, the silicide layer391is formed on the gate electrode73of the transistor. Moreover, silicide layers392,393are formed as source/drain electrodes on the surfaces of diffusion layers74,75of the transistor.

Silicide layer391,392,393includes a Si element, a 3d transition metal element, and an additional element having an atomic radius greater than the atomic radius of the 3d transition metal element. Similarly to the treatment for the transistor in the P-well71A, the transistor formed in the N-well71B is subjected to silicidation.

In the P-well71A, diffusion layers74,75as the source/drain of N-channel transistor are made of N-conductivity-type silicon. In the N-well71B, the diffusion layers as the source/drain of P-channel transistor are made of P-conductivity-type silicon. Thus, in the P-channel transistor and the N-channel transistor, the 3d transition metal element and the additional element for forming silicide layers391,392,393may vary in consideration of the work function of silicide, depending on the P-type or N-type diffusion layers as the source/drain. Moreover, the silicide layers in the P-channel transistor and the N-channel transistor may include the same additional element. In this case, the P-well and the N-well may be subjected to silicidation at the same time.

Then, after the alloy film which has not caused a silicide reaction with Si is removed, an interlayer insulating film and a interconnect line, for example, are formed over transistor Tr by a known technique. Thus, the field effect transistor according to the application is completed.

As described above, in the Application shown inFIG. 22andFIG. 23, the silicide layer391,392,393including the Si element, the 3d transition metal element and the additional element is used for the gate electrode or the source/drain electrodes of the transistor. The atomic radius of the additional element is greater than the atomic radius of the 3d transition metal element.

In the application, a silicide layer having high high-temperature resistance is used for each of electrodes391,392,393. Thus, as described above, even if a high-temperature thermal treatment is carried out in the back-end process for forming a memory cell array, the element (e.g., the FET on the substrate) which is formed in the front-end process and which includes the silicide layer is inhibited from deteriorating in characteristic due to the high-temperature thermal treatment.

Diffusion layers74,75and the lower part73A of the gate electrode are made of silicon. The silicide layer391,392,393to which a foreign element is added can reduce the interface resistance of the silicon-silicide junction, for example, the junction of the diffusion layer and the source/drain electrode.

In the gate electrode, the resistance of the interface between the upper part of the gate electrode for which the silicide layer391is used and the lower part of the gate electrode for which silicon layer73is used is reduced. The decrease of a voltage due to the interface resistance is reduced, so that a gate voltage applied to the gate electrode73can be decreased, and a channel can be formed under the gate electrode391,73at a low gate voltage without any adverse effects of the interface resistance.

Similarly, the resistance of the interface between the diffusion layers74,75formed in the silicon substrate70and the source/drain electrodes391,392is reduced. As a result, the drain current of the field effect transistor at a certain supply potential increases.

In the example described here, the silicide layer391,392,393to which a foreign element is added is used for the field effect transistor of the peripheral circuit of the resistance change memory. However, the silicide layer may be applied to the constituent element on the substrate formed by the front-end process other than the field effect transistor.

Furthermore, silicide layer391,392,393described in the present embodiment may be used for a peripheral circuit of other semiconductor memories or a field effect transistor as a constituent element of a semiconductor integrated circuit (e.g., a logic circuit).

As described above, in the resistance change memory according to the embodiment, at least one kind of element having an atomic radius greater than the atomic radius of a 3d transition metal element is added to a silicide layer composed of Si and the 3d transition metal element. In the application, silicide layers391,392,393are not only used for the memory cell arrays but also used for peripheral circuits formed on the silicon substrate such as the gate electrodes and the source/drain electrodes of the field effect transistor.

Consequently, as shown inFIG. 22andFIG. 23, characteristic deterioration of the element used in the resistance change memory can also be inhibited in the application of the embodiment.

(2) Select Transistor

In Basic example and Example, the resistance change memory having the cross-point type memory cell array has been mainly described, and the cell unit of this memory is composed of the memory element and the non-ohmic element. However, depending on the kind of resistance change memory, a cell unit may be composed of one memory element and at least one transistor.

In the example shown inFIG. 24, one cell unit has a so-called a 1T+1R structure composed of one memory element20and one transistor STr. The transistor (hereinafter referred to as a select transistor) is used as a selective element for the memory element. The cell unit including such the select transistor STr is used in, for example, an MRAM or PCRAM. In addition, two or more select transistors may be provided for one memory element.

In the cell unit shown inFIG. 24, silicide layers391,392,393described in the present embodiment are used for the gate electrode and the source/drain electrodes of the select transistor STr. The structure of the select transistor STr is substantially the same as the structure of transistor Tr in the peripheral circuit shown inFIG. 22, and the difference therebetween is therefore only described here.

The select transistor STr is a field effect transistor formed on a semiconductor substrate (e.g., a silicon substrate).

The memory element20is provided on an upper layer of select transistor STr via interlayer insulating films77A,77B.

One end of the memory element20is electrically connected to first bit line BL via contact V1. The other end of the memory element20is electrically connected to one end (source/drain)392,75of a current path of select transistor STr via an intermediate interconnect line M0and a contact CP1.

The other end (source/drain)393,74of the current path of the select transistor STr is electrically connected to second bit line bBL via a contact CP2.

The gate electrode391,73of the select transistor STr is connected to the word line. In the example shown inFIG. 24, the gate electrode391,73is used as word line WL, and extends in the channel width direction.

The method of forming silicide layers391,392,393in the gate electrode and the source/drain electrodes of select transistor STr is similar to the manufacturing method described withFIG. 23, and is therefore not described here.

In an MRAM or PCRAM, in writing or reading data, a potential is applied to the gate electrode (word line) of the select transistor in the selected cell unit, and the select transistor STr is turned on. A write current or read current is supplied to the memory element20via the current path (channel) of select transistor STr in an on-state.

For example, when a spin-injection magnetization inversion method is used for the operation of writing into the MRAM, the running direction of current I to be supplied to the memory element (MTJ element) is changed depending on the data to be written. Moreover, in the PCRAM, the write current I is supplied to the memory element20to provide a heat quantity for changing the crystal phase of resistance change film of the memory element20.

Thus, when the memory is in operation, the write current or read current runs through the silicon-silicide junction.

As described above, in silicide layers391,392,393, the work function of silicide can be modulated by the addition of a foreign element to a certain silicide. As a result, the interface resistance is reduced at the junction of silicide and other parts.

Therefore, in the resistance change memory described in the application, the write current or read current can be supplied to the memory element20without any current attenuation attributed to the interface resistance.

Furthermore, as in the example of the field effect transistor inFIG. 22, silicide layers391,392,393used for the gate electrode and the source/drain electrodes of the select transistor STr contain an additional element, so that the agglomeration and diffusion of the metal elements included in the silicide layer caused by the high-temperature thermal treatment are inhibited. Thus, deterioration of current transferring capability of the select transistor STr resulting from the high-temperature thermal treatment is inhibited.

Therefore, a write current of an intensity sufficient to write data into memory element20can be supplied, and writing failure due to the reduction of the write current can be prevented. Moreover, the reduction of the read current due to the interface resistance can be inhibited similarly to the write current, so that deterioration of a current or potential (e.g., a bit line potential) for determining data can be inhibited, and data can be read with accuracy.

Furthermore, since the influence of the reduction of the write current due to the interface resistance is reduced, there is no need to generate a high current in advance to counter the reduction of the current due to high interface resistance. Thus, the power consumption of the resistance change memory can be reduced.

Consequently, as shown inFIG. 24, characteristic deterioration of the element used in the resistance change memory can also be inhibited in the application of the embodiment.

(3) Flash Memory

In the example described above, a silicide layer including an Si element, a 3d transition metal element and an additional element having an atomic radius greater than the atomic radius of the 3d transition metal element is used for the resistance change memory.

However, this silicide layer can also be used for other semiconductor memories. The above-mentioned silicide layer can be applied to a flash memory.

FIG. 25AandFIG. 25Bshow the sectional structure of one cell unit (NAND cell unit) in a NAND type flash memory.FIG. 25Ashows the section of the NAND cell unit along a y-direction, andFIG. 25Bshows the section of the NAND cell unit along an x-direction.

One NAND cell unit comprises a plurality of memory cells MC (e.g., n memory cells MC) having their current paths connected in series, and select transistors SG1, SG2connected to one end of the plurality of memory cells MC and the other.

As shown inFIG. 25AandFIG. 25B, the NAND cell unit is disposed in an active area AA of a semiconductor substrate80. The active areas AA adjacent in the x-direction are electrically isolated from each other by an element isolation insulating film89.

As shown inFIG. 25A, a memory cell MC is a field effect transistor having a gate structure in which an control gate electrodes39,84are stacked on a charge storage layer82A.

The gate structure of the memory cell MC may be a stack gate structure that uses a floating gate electrode for the charge storage layer82A, or a MONOS structure that uses an insulating film (e.g., a silicon nitride film) including a trap level for the charge storage layer82A. In the case shown inFIG. 25AandFIG. 25B, the floating gate electrode is used for the charge storage layer.

The floating gate electrode82A is provided on a gate insulating film81formed on the surface of semiconductor substrate80.

The control gate electrode39,84A are stacked on the floating gate electrode82A via an intergate insulating film83A. the control gate electrode84A,39have a polycide structure in which the silicide layer39is stacked on a polycrystalline Si layer84A. In addition, the control gate electrode may have a fully-silicided structure (FUSI structure) in which the entire control gate electrode from its upper end to lower end is formed of a silicide layer.

The control gate electrode39,84A extend in the x-direction, and are shared by the plurality of memory cells MC adjacent in the x-direction. The control gate electrodes39,84A are used as word lines WL.

Furthermore, the plurality of memory cells MC adjacent in the y-direction share diffusion layers85A, and are connected in series. The diffusion layer85A is used as the source/drain of the memory cells MC.

Select transistors SG1, SG2are provided on one end (drain side) of the memory cells MC connected in series and the other end thereof (source side), respectively. Select transistors SG1, SG2are connected to the adjacent memory cells MC via diffusion layers85D,85S.

Select transistors SG1, SG2are formed in a simultaneous process with the memory cells MC, and therefore become field effect transistors of the stack gate structure. A lower gate electrode82B of select transistors SG1, SG2are formed simultaneously with the floating gate electrode82A. An upper gate electrode39,84B of select transistors SG1, SG2are formed simultaneously with the control gate electrode39,84A. In select transistors SG1, SG2, The upper gate electrode84B is electrically connected to the lower gate electrode3B via opening formed in intergate insulating film.

The upper gate electrodes39,84B have a polycide structure, and include the silicide layer39. Gate electrodes39,82B,84B of select transistors SG1, SG2are shared by a plurality of select transistors adjacent in the x-direction. Gate electrodes39,82B,84B of two select transistors SG1, SG2are used as select gate lines.

Drain-side diffusion layer86D of the select transistor SG1is connected to bit line BL via contacts BC, V1and intermediate interconnect line M0. Source-side diffusion layer86S of the select transistor SG2is connected to a source line SL via a source line contact SC.

A method of manufacturing the flash memory according to the application is described next withFIG. 26.

As shown inFIG. 26, gate electrodes82A,84A,82B,84B of a memory cell and select transistors are formed on the semiconductor substrate80by the CVD method, photolithography and RIE method. As described above, in the memory cell, control gate electrode84A is formed on the floating gate electrode82A via the intergate insulating film83A. The control gate electrode84A is made of, for example, a polycrystalline Si layer.

After gate electrodes82A,84A,82B,84B are formed, the interlayer insulating film88A is formed over gate electrodes82A,84A. Then, the interlayer insulating film88A is etched back, and control gate electrode84A and the upper part of the gate electrode84B of the gate electrode are exposed.

Furthermore, as in the manufacturing method shown inFIG. 14AandFIG. 14B, an alloy film59is deposited on the interlayer insulating film88A and on exposed the control gate electrode84A. The alloy film59includes a 3d transition metal element, and an element (additional element) having an atomic radius greater than the atomic radius of the 3d transition metal element. Then, the substrate80is thermally treated, and the alloy film59and an upper part of the polycrystalline Si layer84A of the control gate electrode cause a silicide reaction.

Thus, as shown inFIG. 25AandFIG. 25B, the silicide layer39is formed on the polycrystalline Si layer84A of the control gate electrode. In addition to the Si element and the 3d transition metal element, the silicide layer39includes an element having an atomic radius greater than the atomic radius of the 3d transition metal element.

Similarly, the silicide layer39is also formed on the polycrystalline Si layer84B in the gate electrode (select gate line) of the select transistor.

In addition, any one of the second to fourth manufacturing methods described in Example may be used as the method of forming the silicide layer39in the gate electrode of the memory cell.

After the alloy film which has not caused a silicide reaction is removed, interlayer insulating films88B,88C, contacts BC, SC, V1and interconnect lines M0, BL, SL are sequentially formed on the substrate80by a known technique. Thus, the flash memory shown inFIG. 25AandFIG. 25Bis completed.

As described above, the silicide layer39including the Si element, the 3d transition metal element and the additional element (foreign element) can be applied to the gate electrodes of the memory cell and the select transistor, that is, a control line (word line/select gate line) of the flash memory. In this silicide layer39, the atomic radius of the additional element is greater than the atomic radius of the 3d transition metal element, as in the silicide layer used in the resistance change memory.

This makes it possible to reduce the interface resistance of the silicon-silicide junction in the word line WL.

In the write operation of the flash memory, a write voltage is applied to the selective word line in the selected cell unit, so that a charge is injected into the charge storage layer82A.

According to the application, since the reduction of the write voltage resulting from the interface resistance is small in the word line (control gate electrode) having the polycide structure, there is no need to generate a high voltage in advance to counter the reduction of the write voltage due to the interface resistance. Thus, the power consumption of the flash memory can be reduced.

While the flash memory has been described herein by way of example, the silicide layer39described in the embodiment can be applied to a DRAM or SRAM or to a mixed memory including the former memories. In the DRAM or SRAM, the silicide layer described in the present embodiment is used for the gate electrode (word line) or the source/drain electrodes of the transistor included in the memory cell.

OTHERS