System and method for determining line widths of free-standing structures resulting from a semiconductor manufacturing process

A apparatus and method for determining minimum line widths of free standing structures built by a semiconductor (S/C) manufacturing process. Free standing structures are created in a semiconductor device and subjected to an aerosol process which is tuned and centered with respect to a critical line width for the free standing structures. The S/C manufacturing process is tuned responsive to failure of free standing structures of sub-critical line widths.

BACKGROUND OF INVENTION

This invention relates to semi-conductor manufacturing processes, and more particularly to an aerosol process for inspecting free standing structures.

As minimum semiconductor design feature sizes decrease from 90 nm to 65 nm to 40 nm, structures such as those created by traditional lithography-etching become mechanically less and less stable. Unstable structures will cause defects that result in electrical opens or shorts, preventing circuit operation. The use of new ultra short wavelength lithography/resist systems makes across chip line width variation (ACLV) control difficult, such that lines within a chip, or portions of such lines, can easily be 10% smaller than the average. The necessity for on-mask corrections further compounds the problem, because imperfect optical proximity correction (OPC), which compensates a design for lithographic image variation due to local environment, actually can make the local line variation worse.

The industry has relied predominately on electrical and critical dimension measurements via scanning electron microscopy (SEM) to determine average line widths across a chip or wafer. Realistically, measurements are preformed on structures in nested, semi-nested and isolated local environments that mimic the product chip to obtain a fairly good understanding the line widths on the product chip.

Ideally, all local environments should be measured on a product chip or wafer to ensure an accurate understanding of line width. Since this is not feasible, line width variations and/or failures may exist and will ultimately be detected in the product through electrical characterization and subsequent failure analysis. This procedure, however, is a costly, time consuming, and resource intensive solution.

Thus there is a need in the art for an improved method for identifying specific regions on a wafer or chip where free standing structures of a specific width, such as poly-Si gates, resist trenches, or trenches in a low K material such as SiLK, fail to maintain structural integrity.

SUMMARY OF INVENTION

A system and method are provided for determining minimum line widths of free standing structures built by a semiconductor (S/C) manufacturing process, by creating free standing structures in a semiconductor device; tuning and centering an aerosol process with respect to a critical line width for the free standing structures; subjecting the device to the aerosol process; and responsive to failure of free standing structures of sub-critical line widths, selectively tuning the S/C manufacturing process.

DETAILED DESCRIPTION

In accordance with the preferred embodiment of the invention, a tunable aerosol system and method is provided for identifying specific regions on a wafer or chip where free standing structures fail to maintain structural integrity. The occurrence of some type of physical disturbance on these structures resulting from the aerosol clean process can be correlated to line width.

With this aerosol process, “at level” knowledge of problem areas on a wafer or chip may be derived with a dramatically reduced mean time to problem detection. This aerosol process may be used after key process steps in making a wafer or chip which, when combined with Process Limited Yield (PLY) inspections and/or electrical tests, will help identify such problem areas, particularly with respect to line widths of free standing structures. Such key process steps include litho develop, PC mask open, PC etch, dielectric etch, and the like. In the following example, an aerosol process is performed after free-standing poly-silicon lines are deposited on a wafer.

Referring toFIG. 1, a simple block diagram of an argon/nitrogen cryogenic aerosol tool for cleaning silicon wafers is illustrated. The aerosol process starts with argon50and nitrogen52gas. The volume of each gas is controlled individually by mass-flow controllers and mixed in blender54before entering cryogenic chiller56. Chiller56is a liquid nitrogen heat exchanger that cools the gas mixture to cryogenic temperatures. This cooled mixture flows into an injection nozzle or expansion chamber58, and then is injected into cleaning chamber60through an array of nozzle holes48. Expansion of the gas into the vacuum chamber58, which is controlled at a partial vacuum of 100–300 torr, causes further cooling. This leads to the formation of frozen crystals as the gas temperature drops below 84 K, the triple point for argon. Nitrogen in the gas mixture permits higher expansion ratios, and acts as a diluent for the argon, thus providing a means for controlling argon particle size and kinetic energy.

Wafer40passes under the nozzle and is sprayed with an aerosol comprising Ar/N2 mixture and argon ice crystals, which impinge on free standing structures42. The injector nozzle angle of incidence46can be adjusted to optimize cleaning of high-aspect features. The intensity of the aerosol, energy, and size of the ice crystals are controlled by total gas flow, the ratio of argon to nitrogen, gas temperature, and chamber60pressure. The Aerosol process, such as an Aerosol clean process, is a simple momentum transfer process. (“P” is scientific notation for momentum.) Free-standing structures can be knocked over by transferring the momentum of frozen gas particles to them. The pressure applied to the gas behind the nozzle will change the momentum of the frozen gas particles. Pressure is one “knob” which can be turned to change the momentum. Other “knobs” which can be turned that allow for the tenability of the process are gas species and distance from nozzle to wafer.

Referring toFIGS. 2A through 2G, a typical semiconductor manufacturing process is illustrated, with various free standing structures42which may be tested using the aerosol clean process of the preferred embodiments of the invention occurring at several stages of the process.

In step200, for an NMOS process, a starting material consisting of a P-type lightly doped, polished silicon wafer70is provided. In step202, a SiO2 layer74is formed by thermal oxidation. In step204, photoresist is applied, such as by dropping several drops of positive Photoresist (e.g. Shipley S1818) on the wafer, which is then spun to be uniformly spread out. After spinning, the wafer is given a pre-expose baking to remove solvent from the PR film74and improve adhesion to substrate70.

In step206the drain and source regions75are defined by photolithography. The PR layer74portion not covered by a mask undergoes a chemical change by UV light and is removed by spraying the wafer with a developing solution. The remaining PR74is a copy of the mask pattern. The wafer is rinsed and spin dried, and then baked again so that PR74can resist a strong acid used to etch the exposed oxide layer.

In step208, hydrofluoric (HF) acid is used to etch away the oxide in the openings76of the photo resist74, and stops at the surface of silicon70. In step210, the photo resist74is stripped by solvent or plasma oxidation, leaving behind an insulator pattern72that is the same as the opaque image on a mask.

In step212, a two-step diffusion process is used to form drain and source regions78in which phosphorous predeposition is first formed followed by a drive-in diffusion, and a thin layer of phosphosilicate glass on the wafer is removed. In step214, oxide layer72is further grown from thermal oxidation. Phosphorous78spreads out by diffusion during this furnace operation.

In steps216,218, and220, a second photolithography process is done to remove oxide72to define a gate region84. This is done, as before, by photoresist80drop, spinning, pre-baking, mask alignment, UV exposure, PR developing, rinsing and drying, post-baking, and oxide72etching. In step222, photoresist80is stripped.

In step222, a very thin gate oxide layer86is grown by thermal oxidation. In steps226,228and230, a third photolithography process is done to remove oxide72to define contact holes92. The same procedure is followed: PR88drop, spinning, pre-baking, mask alignment, UV exposure, PR88developing, rinsing and drying, post-baking, and oxide72etching. In step232, PR88is removed.

In step234, a metal such as Aluminum94is evaporate on the whole substrate surface to form electrical contacts later.

In steps236,238, and240, a final lithography process is done to remove the Al-layer94, defining a contact pattern. The same procedure is followed: PR drop, spinning, pre-baking, mask alignment, UV exposure, PR developing, rinsing and drying, post-baking, Al etching. In step242, PR96is stripped, and all the NMOS fabrication steps are completed.

At several stages in the NMOS fabrication process, as in other such fabrication processes, free standing structures42are created which can be subjected to the aerosol clean process of the present invention for testing structural and electrical integrity (length of line width and continuity). These include, for example, PR74at step206, oxide72at step210, PR88at steps228and230, oxide86at step232, Al94at step234, PR96at steps238and240, and AL94at step242.

Referring toFIGS. 3A and 3B, process steps for determining minimum line widths begins in step110with creating freestanding structures, as previously described with respect toFIGS. 2A through 2G.

In step112, it is determined if the aerosol process is tuned (or, has been tuned as a result of steps114–130) for critical line width. Parameters to tune to control the intensity of the aerosol, energy, and size of the aerosol crystals include injector nozzle48angle of incidence46, total gas flow into chamber58, the ratio of argon50to nitrogen52, gas temperature out of cooler56, and chamber60pressure.

In step114, free standing structures42on wafer or chip40are subjected to the aerosol process in chamber60. In step116, structures42are examined (by scanning electron microscope (SEM), or PLY) to determine in steps118and122if any free standing structures broke. If it is determined in step118that an FSS42of sub-critical line width broke, the aerosol process is not tuned and in step120parameters are tuned to increase aerosol pressure. If it is determined in step122that an FSS42of greater than critical line width broke, the aerosol process is not tuned, and in step124parameters are tuned to decrease aerosol pressure (that is, the force by which the aerosol impinges on FSS42during test). If FSS structures of less than or greater than critical line width did not break, then in step126it is determined if the aerosol process is centered for the critical line width. The aerosol process is centered for critical line width when freestanding structures start breaking just below the dimensions determined by the technology minimum line width. Whether or not the process is centered is determined by PLY inspection to determine where the lines are breaking and SEM inspection to determine at what width the lines are breaking.

If the aerosol process is centered for the critical line width, then step130indicates that the aerosol process is tuned and, if not, in step128the aerosol process is tuned by increasing or decreasing pressure as needed. The minimum line width is determined by the technology node. It is the smallest allowed freestanding structure width as determined by the design manual for the technology. Here the critical line width is the threshold value where the freestanding structures will start to break as determined by where the aerosol process is tuned.

Once it is determined in step112that the aerosol process has been tuned for the critical line width of the FSS42to be tested, in step132the test is conducted and in step134the results examined.FIG. 4is a representation of a scanning electron microscope (SEM) view of test results,FIG. 5is a schematic representation of a PLY map of results, andFIG. 6plots the results of observations of four exemplary structures42at various line widths.

Referring toFIG. 3B, in step136it is determined if any free standing structures (FSS) of sub-critical line width broke, and if not, step138indicates that there are none. Step140indicates that sub-critical line widths have been observed, and in step142root cause analysis is undertaken. A sub-critical line width is observed when a line is determined to be below minimum acceptable width because it broke when subjected to a process tuned to the center of the critical line width.

In steps144and146, a process correction action plan is designed to correct for the manufacture of sub-critical line width related to such process steps or parameters as Reactive Ion Etch (RIE) and planarity. RIE is a process where reactive gases in plasma form will chemically etch away specific materials. Planarity refers to how planar the surface is that the FSS is landing. If the surface is not planar (varying in height by a few nanometers) the lithographic process will not print the FSS pattern correctly and can result in a sub-critical feature. Once the substructure is located and imaged (with an SEM) the problematic structure can be traced back to which manufacturing process caused the problem depending on what the faulty FSS looks like. Lithographic issues have a different signature than RIE issues than OPC issues.

In steps148and150, a lithography corrective action plan is designed to correct for sub-critical line width issues related to lithography, including for example Optical Proximity Correction (OPC), resist system, optics. OPC is a method for adding or subtracting extra features in a lithographic mask to make the features print to the desired shape. Herein, optics refers to the lithographic tools itself and, if the tool is printing sub-critical line width features, a change in the process of the lithographic tool may be necessary.

In steps152and154, an action plan is designed to handle sub-critical line width results not related to process or lithography.

Referring toFIG. 4, a schematic representation is presented of a scanning electron microscope examination of free standing structures160,162,170,172which have been subjected to aerosol cleaning. These exemplary structures are free standing on PC elements164,166,174and176, which are surface structures on wafer or chip40. Structure160has been broken at168. Structure170has been broken, and portion178moved into contact with structure172.

Referring toFIG. 5, a schematic representation of a PLY map illustrates the results of testing a chip180which has been subjected to aerosol cleaning. A failure (that is, a damaged FSS42) in a component is represented by a blackened square184, with white squares182representing absence of a failure. In this example, column186contains structures with the shortest PC line widths and the largest density of structures broken by aerosol cleaning; column188contains structures with the longest PC line widths and the lowest density of structures broken (knocked over, evaporated or moved) by aerosol cleaning; and columns190,192contain structures of intermediate line widths and failure density.

Each broken line160,170inFIG. 4is represented by a defect indicator184in PLY map180.

Referring toFIG. 6, observations of four exemplary electrical structures are graphed with respect to yield and count of observations. Results are bucketized with the minimum line width of a bucket indicated in microns. The lines represent yield, the bars number of observations. These test structures42have been measured in line by observations taken at various points in the manufacture process. This chart illustrates that the longer the line width, the higher the yield, and also shows that with aerosol process tuning (such as pressure, flow rate) free standing structures of poly-Si lines below 30 nm could be knocked over.FIG. 6is based solely on electrical data. A root cause (steps144cannot be determined without doing a root cause analysis like physical failure analysis.FIG. 6represents electrical confirmation that the aerosol process (112) is being tuned.

It is an advantage of the present invention that a system and method is provided for identifying specific regions on a wafer or chip where free standing structures fail to maintain structural integrity.

It will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. In particular, it is within the scope of the invention to provide a computer program product or program element, or a program storage or memory device such as a solid or fluid transmission medium, magnetic or optical wire, tape or disc, or the like, for storing signals readable by a machine, for controlling the operation of a computer according to the method of the invention and/or to structure its components in accordance with the system of the invention.

Further, each step of the method may be executed on any general computer, such as IBM Systems designated as zSeries, iSeries, xSeries, and pSeries, or the like and pursuant to one or more, or a part of one or more, program elements, modules or objects generated from any programming language, such as C++, Java, PI/1, Fortran or the like. And still further, each said step, or a file or object or the like implementing each said step, may be executed by special purpose hardware or a circuit module designed for that purpose.

Accordingly, the scope of protection of this invention is limited only by the following claims and their equivalents.