Method of forming a Schottky diode and structure therefor

In one embodiment, a Schottky diode is formed on a doped region having a thickness less than about eighteen microns.

This application is related to an application entitled “SCHOTTKY DIODE AND METHOD OF MANUFACTURE” filed on Mar. 21, 2005 as application Ser. No. 11/084,524, having at least one common inventor, a common assignee.

BACKGROUND OF THE INVENTION

The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.

In the past, the semiconductor industry utilized various methods and structures for forming Schottky diodes. Schottky diodes were frequently used in low voltage/high frequency applications because the low forward voltage provided very fast switching characteristics. There was an increasing interest in Schottky diodes with low forward voltage. However, lowering the forward voltage drop usually resulted in decreasing the reverse breakdown voltage of the Schottky diode.

Accordingly, it is desirable to have a method of making a Schottky diode with a low forward voltage drop without reducing the reverse breakdown voltage.

For simplicity and clarity of the illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-Channel devices, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of doped regions generally may not be straight lines and the corners may not be precise angles.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1illustrates an enlarged cross-sectional portion of an embodiment of a Schottky diode20that has a low forward voltage drop and a high reverse breakdown voltage. Diode20includes an E-field spreading structure50that spreads out the E-field and facilitates reducing the forward voltage without reducing the reverse breakdown voltage. As will be seen further hereinafter, structure50includes a semi-insulating material that is formed adjacent to a dielectric material. Diode20generally is formed on a semiconductor substrate23that has a top surface25and a bottom surface24. Semiconductor substrate23usually includes a bulk semiconductor substrate21that has an epitaxial layer22formed on a surface of substrate21. Epitaxial layer22is a doped region that has also has a low resistivity.

FIG. 2illustrates an enlarged cross-sectional portion of diode20and an early stage of a method of formation. Epitaxial layer22is formed on a first surface of bulk substrate21. The thickness of layer22is less than about eighteen (18) microns and preferably is about 1.7 to 15.0 microns. Bulk substrate21and layer22typically are formed from the same conductivity type of semiconductor material, preferably N-type, with layer22having a higher resistivity than substrate21. For example, the resistivity of layer22usually is less than about four (4) ohm-centimeter and preferably is in a range of about 0.2 to 2.0 ohm-cm. Such resistivity and thickness result in a forward voltage of about two hundred fifty to three hundred milli-volts (250-300 mv) and a reverse breakdown voltage that is less than about two hundred volts (200 V) and preferably is about ten to two hundred volts (10-200 V). The semi-insulating material of structure50facilitates forming layer22with such thickness and resistivity thereby facilitates forming diode20with the low forward voltage drop without reducing the reverse breakdown voltage. In one embodiment, layer22is epitaxially formed on substrate21to have a phosphorus doping concentration that is greater than about 1E15 atoms/cm3and preferably is about 2E15 to 1E10 atoms/cm3. Those skilled in the art will appreciate that layer22is optional and may be replaced by other structures. For example, a portion of the top surface of bulk substrate21may be doped to form a doped region having a thickness and resistivity that is similar to the thickness and resistivity of epitaxial layer22. Additionally, layer22and substrate21may be doped with P-type dopants instead of N-type dopants.

A dielectric layer28may be formed on surface25of substrate23. As will be seen further hereinafter, a portion of layer28is used as a portion of structure50. Dashed lines illustrate portions of layer28that are removed during the operations explained in the description ofFIG. 2. Suitable materials for layer28include silicon dioxide, silicon nitride, silicon oxide-nitride, silicon carbide, or other well-known dielectric materials. Layer28may be formed by a variety of well-known techniques including chemical vapor deposition (CVD), thermal oxide growth, and oxide deposition. Subsequently, a mask100, such as a photolithographic mask, is formed on layer28and patterned to expose a portion of dielectric layer28where a doped region32is to be formed. Mask100is utilized to form openings27through the portions of layer28overlying the portion of substrate23where doped region32is to be formed. Openings27generally are formed by etching the exposed portions of layer28by techniques that are well known to those skilled in the art, for example, by an anisotropic reactive ion etch.

Referring toFIG. 3, mask100is removed leaving the remaining portions of layer28on surface25. The portion of layer22that is exposed within openings27is doped to form a doped region32that extends from surface25a distance into layer22that is less than the thickness of layer22. In most embodiments, region32is formed in a multiply-connected topology such as a donut or other connected shape having an opening in it. For a multiply-connected topology, the portion of the shape enclosed by the inner periphery of region32will subsequently become an active region26of diode20. Those skilled in the art will appreciate that the shape formed by doped regions32may be any of a variety of multiply-connected shapes including a circular doughnut, a triangle, a square, or other shape. The shape formed by region32may also have other shapes that are not multiply-connected as long as region32forms a boundary of active region26.

A dielectric34is formed on surface25to abut layer28and overlie a portion of region32. Dielectric34generally has a thickness that is less than the thickness of layer28and may be in the range of about fifty to ten thousand (50-10000) micro-meters. During the formation of dielectric34, the thickness of layer28may be increased. Layer34may be formed as a by-product of forming region32or may be formed by other well-known methods.

Referring toFIG. 4, a semi-insulating semiconductor material36is formed on layer28and dielectric34. In most embodiments, material36is formed from a plurality of layers of semi-insulating semiconductor material that may have different resistivity, although, material36may have only one layer of semi-insulating material in some embodiments. Preferably, material36has at least a first semi-insulating layer37that is formed on layer28and dielectric34, and a second semi-insulating layer38that is formed on layer37. Layer38generally has a higher resistivity than layer37in order to assist in spreading the E-field formed near region32. A semi-insulating semiconductor material is a semiconductor material that has a resistivity that is greater than about 2E17 ohm-cm. Suitable materials that may be used to form layers37and38include polycrystalline silicon (polysilicon) having a carrier concentration of less than about 1E10 atoms/cm3and alpha-silicon having a carrier concentration of less than about 1E10 atoms/cm3. A protective layer48is formed on material36to protect material36during subsequent processing operations. The material used for layer48may be any one of a variety of materials suitable for use on a semiconductor device, such as a dielectric material, and preferably is TEOS.

Material36, layer48, and the underlying dielectric of layer28and dielectric34will be patterned to form structure50. A mask101, such as a photolithographic mask, is formed on layer48and patterned to overlie a distal edge of region32that is distal from active region26so that a first edge102of mask101overlies region32and a second edge103overlies a portion of surface25that extends laterally away from the distal edge of region32.

Referring toFIG. 5, mask101, illustrated by dashed lines, is used to remove portions of dielectric layer48, material36, and portions of dielectric layer28and dielectric34. For example an isotropic reactive ion etch be utilized to remove the exposed portions of dielectric layer48in addition to the portions of material36and the portions of layer28and dielectric34that underlie the exposed portions of layer48. Such techniques are well known to those skilled in the art. Thereafter, mask101is removed. The remaining portion of layer28and dielectric34that underlie material36are identified as dielectrics40and41, respectively.

Referring toFIG. 6andFIG. 7, a Schottky barrier junction is formed at an interface of layer22and a Schottky barrier material, such as a silicon-metal alloy62. Silicon-metal alloy62is formed on surface25within active region26. Silicon-metal alloy62preferably extends across surface25between interior sides52of structure50(FIG. 7) and into portions of region32that do not underlie structure50. Another silicon-metal alloy61(FIG. 7) is formed outside of active region26to extend a distance across surface25from exterior sides53of structure50. Alloys61and62may be formed by depositing a metal layer58(FIG. 6) onto surface25and onto the portion of layer48that is on structure50. The material used for metal layer58is a Schottky barrier material that has a low energy barrier in order to form a Schottky barrier junction that results in a low forward voltage for diode20. The material used for layer58preferably forms a metal-silicon alloy with the material of layer22and forms the Schottky barrier junction between alloy62and layer22. Suitable materials for layer58include refractory metals such as tungsten, titanium, platinum, nickel, cobalt, or other similar materials. Layer58generally is heated in order to form metal-silicon alloys61and62. The heating may be formed by a separate annealing operation or may be the result of a subsequent processing step. The portions of layer58that do not contact silicon remain as un-reacted portions of layer58. These un-reacted portions of layer58are removed. Those skilled in the art will appreciate that alloys61and62may be omitted and that a metal layer may be formed within active region26and on surface25to form a Schottky junction between the metal layer and layer22.

Subsequently, the portion of protective layer48on structure50is removed leaving underlying E-field spreading structure50on surface25with a first side52overlying a portion of region32and extending across surface25over the distal edge of region32to have a second side53that overlies a portion of layer22near region32. In most embodiments, side52is formed to be substantially coplanar to and overlie an edge of layer22. Those killed in the art will appreciate that structure50usually is formed in a geometric pattern that is the same as the pattern of region32and extends laterally across the surface of substrate23. Structure50includes a first layer that is formed on surface25and includes a portion of dielectric layer28and a portion of dielectric34as respective dielectrics40and41, and also includes a second layer that is formed by material36which abuts dielectrics40and41.

Referring toFIG. 8, conductors64and65are formed to provide electrical contact to respective metal-silicon alloys61and62. A conductor layer63typically is formed on structure50and on alloys61and62by a blanket deposition of a conductor material such as aluminum-silicon or other conductor material. Thereafter, a mask66, such as a photolithographic mask, is applied to layer63and patterned to form an opening68through mask66and overlying dielectric40.

Referring back toFIG. 1, an opening is formed through conductor layer63using opening68through mask66(FIG. 8). The opening through layer63electrically disconnects portions of layer63to form a conductor64that is electrically contacting alloy61and a conductor65that is electrically contacting alloy62. Thereafter, mask66is removed. Opening70typically overlies dielectric40to ensure that conductor65extends onto structure50to overlie most of region32. A conductor76may be formed on surface24. Such a configuration spreads the E-field from alloy62further into region32thereby reducing the intensity of the E-filed and increasing the reverse breakdown voltage of diode20. Also, forming dielectric40to be thicker than dielectric41also assists in spreading the E-field and increases the reverse breakdown voltage.

It has been found that forming semi-insulating material36on dielectrics40and41spreads the E-field and facilitates forming layer22to be thin and have a low resistivity to reduce the forward voltage without reducing the reverse breakdown voltage of diode20. It is believed that this is an unexpected result that is counter to common design practices of the industry. Prior design practices required that the doped region, such as layer22, be made thick and to have a high resistivity, typically higher than that of the underlying substrate, such as substrate21, in order to prevent reducing the breakdown voltage. Thus, the results of forming semi-insulating material36on dielectrics40and41and reducing both the thickness and the resistivity of layer22without reducing the breakdown voltage is an unexpected result.

FIG. 9illustrates an enlarged plan view of an embodiment of a portion of some topographical features of diode20without conductor65. Region32and structure50are formed in a multiply-connected topology that encloses region26.

In view of all of the above, it is evident that a novel device and method is disclosed. Included, among other features, is forming layer22to have a thickness no greater than about eighteen microns and a resistivity that is no greater than about four ohm-cm thereby forming a low forward voltage. Also included is forming a semi-insulating layer abutting a dielectric thereby increasing the breakdown voltage.

While the subject matter of the invention is described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts.