NFC device combining components of antenna driver and shunt regulator

Embodiments of the present disclosure can be used to produce smaller, more compact antenna drivers at a reduced cost. Systems and methods for integrating components of an antenna driver with components of a shunt regulator and clamp are provided. By combining these components according to embodiments of the present disclosure, transistor count in an antenna driver can be reduced. This integrated device advantageously allows antenna driver functionality, regulator functionality, and clamp control functionality to be provided at a reduced manufacturing cost and with reduced real estate.

FIELD OF THE INVENTION

This invention relates to antennas and more specifically to NFC transceiver devices.

BACKGROUND

In many conventional communications devices, separate circuitry is often included to provide antenna driver functionality and regulator/clamp functionality. Implementations using separate circuitry for antenna driver functionality and regulator/clamp functionality can require several large transistors, which increases manufacturing cost and real estate.

For example, many conventional antenna driver circuits incorporate two large input/output transistors on each antenna port. A conventional antenna driver for a near field communication (NFC) device can include a N-type metal-oxide-semiconductor (NMOS) device for pulling current down to VSS(e.g., a negative power supply voltage) and a P-type metal-oxide-semiconductor (PMOS) device for supplying current from VDD(e.g., a positive power supply voltage). These NMOS and PMOS devices are specialized metal-oxide-semiconductor field effect transistors (MOSFETs) used to implement logic for the antenna driver circuit.

Circuitry for a regulator and clamp control for the antenna can also include NMOS devices and/or PMOS devices. Thus, adding regulator and/or clamp control circuitry to a device can further increase the manufacturing cost and the real estate (e.g., circuit board area) required for the device. These specialized transistors can be very costly and can also require large real estate on the transceiver device integrated circuit (IC).

Features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

DETAILED DESCRIPTION OF THE INVENTION

In the following description, numerous specific details are set forth to provide a thorough understanding of the disclosure. However, it will be apparent to those skilled in the art that the disclosure, including structures, systems, and methods, can be practiced without these specific details. The description and representation herein are the common means used by those experienced or skilled in the art to most effectively convey the substance of their work to others skilled in the art. In other instances, well-known methods, procedures, components, and circuitry have not been described in detail to avoid unnecessarily obscuring aspects of the disclosure.

Although the present disclosure is to be described in terms of near field communications (NFC) embodiments, those skilled in the relevant art(s) will recognize that the present disclosure may be applicable to other communications that use the near field and/or the far field without departing from the spirit and scope of the present disclosure. For example, although the present disclosure is described using NFC-capable communications devices, those skilled in the relevant art(s) will recognize that functions of these NFC-capable communication devices may be applicable to other communications devices that use the near field and/or the far field without departing from the spirit and scope of the present disclosure.

Embodiments of the present disclosure provide systems and methods for combining components of an antenna driver with components of a shunt regulator and clamp to reduce transistor count in an antenna driver circuit. Because these transistors can be very costly, as they are required to source or sink several hundred milliamps, embodiments of the present disclosure can be used to produce antenna drivers at a reduced cost. Further, because these transistors can require significant silicon area on an integrated circuit (IC), embodiments of the present disclosure can advantageously be used to produce a smaller, more compact antenna driver when compared with traditional devices requiring separate circuitry for antenna driver functionality and regulator/clamp control functionality.

Embodiments of the present disclosure provide systems and methods for combining N-type metal-oxide-semiconductor (NMOS) input/output transistors of an antenna driver with NMOS input/output transistors of the shunt regulator and clamp. For example, embodiments of the present disclosure provide an integrated antenna driver, regulator, and clamp control circuit. By reusing these NMOS transistors for both antenna driver and shunt regulator/clamp functionality, total transistor count in a device can be reduced.

FIGS. 3A,3B, and4show circuit diagrams of an integrated antenna driver, regulator, and clamp control circuit in accordance with embodiments of the present disclosure. Embodiments of the present disclosure (e.g., as shown byFIGS. 3A,3B, and 4) can be implemented on one or more ICs. For example, in an embodiment, all the elements shown inFIG. 3Acan be implemented on a single IC, all the elements shown inFIG. 3Bcan be implemented on a single IC, and all the elements ofFIG. 4can be implemented on a single IC. In an embodiment, the integrated antenna driver, regulator, and clamp control circuit ofFIGS. 3A,3B, and/or4can be incorporated into a near field communications (NFC) device. NFC devices will now be described with reference toFIGS. 6,7, and8.

FIG. 6illustrates a block diagram of a NFC environment according to an exemplary embodiment of the disclosure. A NFC environment600provides wireless communication of information, such as one or more commands and/or data, among a first NFC device602and a second NFC device604that are sufficiently proximate to each other. The first NFC device602and/or the second NFC device604may be implemented as a standalone or a discrete device or may be incorporated within or coupled to another electrical device or host device such as a mobile telephone, a portable computing device, another computing device such as a laptop, tablet computer, or a desktop computer, a computer peripheral such as a printer, a portable audio and/or video player, a payment system, a ticketing writing system such as a parking ticketing system, a bus ticketing system, a train ticketing system or an entrance ticketing system to provide some examples, or in a ticket reading system, a toy, a game, a poster, packaging, advertising material, a product inventory checking system and/or any other suitable electronic device that will be apparent to those skilled in the relevant art(s) without departing from the spirit and scope of the disclosure. Herein, when incorporated within or coupled to another electrical device or host device, this type of NFC device may be referred to as a NFC capable device.

The first NFC device602generates a magnetic field and probes the magnetic field for the second NFC device604. The first NFC device602and the second NFC device604may be implemented using a Type A standard, a Type B standard, a Type F (FeliCa) standard, and/or a vicinity standard. The Type A and Type B standards are further defined in the “NFC Forum: NFC Activity Specification: Technical Specification, NFC Forum™ Activity 1.0 NFCForum-TS-Activity-1.0,” published Nov. 18, 2010 (hereinafter the “NFC Activity Specification”) and/or ISO/IEC 14443-3, “Identification cards—Contactless integrated circuit(s) cards—Proximity cards—Part 3: Initialization and anticollision,” published on Jun. 11, 1999, which are incorporated herein by reference in their entirety. The Type F standard is further defined in the NFC Activity Specification. The Vicinity standard is further defined in ISO/IEC 15693-3:2009, “Identification cards—Contactless integrated circuit(s) cards—Vicinity cards—Part 3: Anti-collision and transmission protocol,” published on Apr. 6, 2009 (hereinafter the “Vicinity Specification”).

Upon establishing communication with the second NFC device604, the first NFC device602modulates its corresponding information onto the first carrier wave and generates the first magnetic field by applying the modulated information communication to a first antenna of the first NFC device to provide the first information communication652. The first NFC device602continues to apply the first carrier wave without its corresponding information to continue to provide the first information communication652once the information has been transferred to the second NFC device604. The first NFC device602is sufficiently proximate to the second NFC device604such that the first information communication652is inductively coupled onto a second antenna of the second NFC device604.

The second NFC device604derives or harvests power from the first information communication652to recover, to process, and/or to provide a response to the information. The second NFC device604demodulates the first information communication652to recover and/or to process the information. The second NFC device604may respond to the information by applying its corresponding information to the first carrier wave that is inductively coupled onto the second antenna to provide the second modulated information communication654.

Further operations of the first NFC device602and/or the second NFC device604may be described in International Standard ISO/IEC 18092:2004(E), “Information Technology—Telecommunications and Information Exchange Between Systems—Near Field Communication—Interface and Protocol (NFCIP-1),” published on Apr. 1, 2004 and International Standard ISO/IEC 21481:2005(E), “Information Technology—Telecommunications and Information Exchange Between Systems—Near Field Communication—Interface and Protocol-2 (NFCIP-2),” published on Jan. 15, 2005, each of which is incorporated by reference herein in its entirety.

2.2 NFC Device Integration Into Host Device

NFC devices (such as NFC device602) may be integrated into a host communications device (e.g., a host mobile phone).FIG. 7shows a block diagram illustration integration of NFC device602into electronic host communications device700with a shared memory704according to embodiments of the present disclosure. In an embodiment, the electronic communications device700includes the NFC device700, the memory704, a security component708, a WI-FI component710, a telephony component712, a Bluetooth component714, a battery716used to power the communications device, a host processor718, and a bus720. It should be understood that components712,718,710,708, and714are optional and are provided to illustrate components that may be incorporated into a host communications device. It should further be understood that, according to embodiments of the present disclosure, one, several, all, or none of components712,718,710,708, and714may be incorporated into the host communications device700.

According to embodiments of the present disclosure, host communications device700may represent a number of electronic communications devices including, but not limited to, mobile telephones, portable computing devices, other computing devices such as personal computers, laptops, desktop computers, computer peripherals such as printers, portable audio and/or video players, payment Systems, ticket writing systems such as parking ticket systems, bus ticketing systems, train ticketing systems, or entrance ticketing systems.

In an embodiment, NFC devices and/or NFC controllers are designed to include secure element(s) that use a secure external memory. In an embodiment, this secure external memory is provided by a host mobile device (e.g., memory704). In another embodiment, this secure external memory is provided by a dedicated additional non-volatile memory chip, such as flash or EE memory. Utilizing this external memory enables the NFC device and/or NFC controller to be manufactured using 40 nm process technology, Which does not necessarily support non-volatile memory.

2.3 Integrated Antenna Driver, Regulator, and Clamp Control Circuit

FIG. 8illustrates a block diagram of an NFC device with an integrated antenna driver, regulator, and clamp control circuit in accordance with an embodiment of the present disclosure. NFC device602is configurable to operate in a target, or tag, mode of operation to respond to a polling command from a second NFC capable device, such as NFC device604, in a polling mode of operation. NFC device602may represent a NFC tag or a NFC communicator. A NFC reader is a type of NFC device that is capable of operating in an initiator mode to initiate a communication with another NFC enabled device. A NFC tag is a type of NFC device that is capable of operating in the target mode to respond to the initiation of a communication by another NFC enabled device. A NFC communicator is a type of NFC device that is capable of operating in the initiator mode or in the target mode and is capable of switching between these two modes.

NFC device602may represent a standalone or a discrete device or may represent a NFC capable device. Since the second NFC capable device may be configured substantially similarly to the NFC device602, the following description focuses on describing the NFC device602. NFC device602may have a plurality of identities associated with it, such as a ticket, credit card, identification, etc. NFC device602includes an antenna module802, a demodulator module804, a controller module806, a power control module808, and a memory module810. NFC device602may represent an exemplary embodiment of NFC device604.

The antenna module802inductively receives a communications signal850from the second NFC capable device to provide a recovered communications signal854. Typically, the received communications signal850includes a polling command that has been modulated by the second NFC capable device.

The demodulator module804demodulates the recovered communications signal854using any suitable analog or digital modulation technique to provide a recovered command856. The recovered command856may be the polling command. The suitable analog or digital modulation technique may include amplitude modulation (AM), frequency modulation (FM), phase modulation (PM), phase shift keying (PSK), frequency shift keying (FSK), amplitude shift keying (ASK), quadrature amplitude modulation (QAM) and/or any other suitable modulation technique that will be apparent to those skilled in the relevant art(s).

When the demodulator module804is within a Type A tag field, it detects polling commands based on 100% ASK modulation. The voltage amplitude must drop substantially to zero, such that the demodulator module804functions as a gap detector for Type A tags. In this situation, any modulation based on another modulation scheme that does not drop below the threshold required for Type A tags may be given the digital value of 1. When the amplitude drops low enough, the demodulator module804gives it the digital value of 0 in accord with the modified Miller coding scheme.

When the demodulator module804is within a Type B tag field, it detects polling commands based on 10% ASK modulation. The demodulator module804has a voltage threshold that is at 90% of the total modulation amplitude. If the polling command's modulation decreases below that threshold, the demodulator module804gives it the digital value of 0 in accord with the NRZ-L coding scheme. In this situation, any modulation based on another protocol may drop below the threshold required for Type B tags and therefore be given the digital value of 0. Any modulation that remains above this threshold would be given the digital value of 1.

When the demodulator module804is within a Type F tag field, it detects polling commands based on a Manchester coding scheme that uses a modulation threshold between that used for Type A and that used for Type B tags. If the polling command's modulation decreases below this threshold, it will be given the digital value of 0. Any modulation that remains above this threshold would be given the digital value of 1.

As can be seen from the above, a Type A tag will not assign a digital value of 0 to any modulation based on Type B or Type F tags because the modulation amplitude would not fall below the threshold required for 100% ASK modulation. Thus, the demodulator module804in a Type A tag would not detect a polling command sent to detect a Type B or Type F tag.

When the demodulator module804is within a Vicinity standard tag field, it detects polling commands based on either 10% or 100% ASK modulation, depending on the choice of modulation by the reader, When using 100% ASK modulation, the voltage amplitude must drop substantially to zero, such that the demodulator module804functions as a gap detector for Vicinity standard tags. In this situation, any modulation based on another modulation scheme that does not drop below the threshold required for Vicinity standard tags may be given the digital value of 1.

When the amplitude drops low enough, the demodulator module804gives it the digital value of 0 in accord with pulse position modulation. When using 10% ASK modulation with the Vicinity standard, the demodulator module804has a voltage threshold that is at 90% of the total modulation amplitude. If the polling command's modulation decreases below that threshold, the demodulator module804gives it the digital value of 0 in accord with the pulse position modulation coding scheme. In this situation, any modulation based on another protocol may drop below the threshold required for Vicinity standard tags and therefore be given the digital value of 0. Any modulation that remains above this threshold would be given the digital value of 1.

Moving on to other aspects of NFC device602, the controller module806controls overall operation and/or configuration of NFC device602. The controller module806sends a list search command862to the memory module810when NFC device602supports a plurality of identities. The control module806receives list search response864with the first identity that matches the polling command characteristic(s). The controller module306then provides a response858to the recovered command856, which incorporates list search response864when responding to a polling command.

Typically, the second NFC capable device inductively couples a carrier wave on the antenna module802as the received communications signal850after it has transferred the polling command to NFC device602. The controller module806modulates this carrier wave in accordance with the response858to provide a transmitted communications signal860. For example, an impedance of the antenna module802varies based upon the response858to vary a load of the NFC device602as seen by the second NFC capable device.

The memory module810stores a list of the plurality of identities associated with the NFC device602. When the received communications signal850is a polling command which has been modulated from the second NFC capable device, the memory module810receives the list search command862in order to search the list of the plurality of identities associated with the NFC device602. Once a match to the characteristics of the polling command is found, the memory module810returns the corresponding identity as list search response864. For example, this match may represent a first identity from among the plurality of identities that matches to the characteristics of the polling command, referred to as a first match.

The power control module808may harvest power for NFC device602from the recovered communications signal854. The power couplings from the power harvesting module808that supply the power to other modules of NFC device602, such as the antenna module802, the demodulator module804, the controller module806, and/or the memory module810, are not shown inFIG. 8. Alternatively or additionally, a battery can be provided.

In an embodiment, power control module808includes an integrated antenna driver, regulator, and clamp control circuit870. Integrated antenna driver, regulator, and clamp control circuit870reuses NMOS transistors for both antenna driver and shunt regulator/clamp functionality so that total transistor count in a device can be reduced, which allows antenna driver functionality, regulator functionality, and clamp control functionality to be provided at a reduced manufacturing cost and with reduced real estate (e.g., reduced circuit board area).

Circuits for conventional antenna drivers, regulators, and clamps will now be described with references toFIGS. 1A-1C.FIGS. 1A and 1Bshow conventional antenna driver circuits, andFIG. 1Cshows a conventional circuit including a regulator and clamp for an antenna. In conventional devices, separate circuitry is often included to provide antenna driver functionality and regulator/clamp functionality. As will be discussed below, implementations using separate circuitry for antenna driver functionality and regulator/clamp functionality can require several large transistors, which increases manufacturing cost and real estate.

3.1 Conventional Antenna Driver

FIG. 1Ashows a circuit diagram of a conventional antenna driver. InFIG. 1A, antenna predriver102is used to power an antenna port. For example, antenna predriver102can be used to power antenna port104a. Antenna predriver102generates a signal that gets buffered by large transistors (PMOS108aand NMOS110a) coupled to antenna port104a. These large transistors allow antenna104to deliver a large current. For example, the area of NMOS110aand PMOS108acan be about 0.1 square millimeters, and these transistors can be capable of 2 mA peak current. Antenna port104ais coupled to the drain of PMOS108aand to the source of NMOS110a. The source of PMOS108ais coupled to positive supply voltage VDD114, and the source of NMOS110ais coupled to negative supply voltage VSS116, The gates of PMOS108aand NMOS110aare coupled and decoupled to antenna predriver102using switches106and112.

Switches106and112are cycled on and off to change the state of antenna port104a. For example, in an embodiment, switches106and112are cycled on and off to change the state of antenna port104ato a state for creating a magnetic field, on which data may be sent and received, or for receiving a magnetic field, on which data may be sent and received. When the antenna driver ofFIG. 1is being used to drive a magnetic field to antenna port104a, horizontal switches106aand106bare closed, and vertical switches112aand112bare open. When horizontal switches106are closed, antenna predriver102connects to the gates of PMOS108aand NMOS110a. While horizontal switches106are closed, vertical switches112are open so there is no connection between the gate of NMOS110aand VSS116and so that there is no connection between PMOS108aand antenna port104a.

When the antenna driver ofFIG. 1Ais off (e.g., when antenna port104ais being used to receive a magnetic field), horizontal switches106are open, and vertical switches112are closed. The opening of horizontal switches106prevents connections between antenna predriver102and PMOS108aand NMOS110a. The closing of vertical switches112aprevents PMOS108aand NMOS110afrom receiving current (i.e., closing vertical switches112turns these transistors “off”). By opening and closing horizontal switches106and vertical switches112, the antenna driver ofFIG. 1Acan cycle between states for creating and receiving a magnetic field. For example, in an embodiment, the antenna driver ofFIG. 1Acan be used as an antenna driver for a near field communications (NFC) device. When the antenna driver ofFIG. 1Ais placed into a state for creating a magnetic field, the NFC device can be used in a reader mode, and when the antenna driver ofFIG. 1Ais placed into a state for receiving a magnetic field, the NFC device can be used in a target (tag) mode.

FIG. 1Bis a circuit diagram of a conventional antenna driver having two antenna ports (antenna port104aand antenna port104b). InFIG. 1B, antenna port104bis coupled to two additional large transistors (PMOS108band NMOS110b) that allow antenna port104bto deliver a large current. Two additional horizontal switches (106cand106d) and two additional vertical switches (112cand112d) are toggled in the same fashion to place antenna port104bin a mode to create a magnetic field or to receive a magnetic field. For example, when horizontal switches106cand106dare closed and vertical switches112cand112dare open, antenna port104bcan be used to create a magnetic field. When horizontal switches106cand106dare open and vertical switches112cand112dare closed, antenna port104bcan be used to receive a magnetic field. In an embodiment, antenna predriver102can drive a signal in antiphase to PMOS108band NMOS110bsuch that the signal sent to antenna port104bis the opposite phase of the signal sent to antenna port104a.

FIG. 2shows a circuit diagram of conventional regulator/clamp circuitry for an antenna. In conventional devices, separate circuitry is often included to provide antenna driver functionality and regulator/clamp functionality. Thus, in many conventional communications devices, the regulator/clamp circuitry (e.g., as shown inFIG. 2) is separate from (e.g., not integrated with) the antenna driver circuitry ofFIGS. 1A and 1B. Because separate circuitry is used, the transistors ofFIGS. 1A and 1Bare not shared with the circuitry ofFIG. 2. InFIG. 2, new large transistors (NMOS210aand NMOS210b) are included to support regulator and clamp control functionality. NMOS210ais used to pull voltage and/or current from antenna port104ato VSS116, and NMOS210bis used to clamp (i.e., short circuit) voltages generated at antenna port104athat are below VSS116.

The circuit ofFIG. 2can either be turned “on” or turned “off” depending on the state of the circuit (i.e., whether antenna port104ais used to create or receive a magnetic field). Horizontal switches212and vertical switches214are toggled open and closed to change the state of the circuit. For example, if antenna port104ais being used to create a magnetic field, the circuit ofFIG. 2is turned “off.” When the circuit ofFIG. 2is turned off, horizontal switches212are opened and vertical switches214are closed. The connection formed by closed vertical switches214pull the gates of transistors210down, to VSS116so that the output of transistors210is turned off.

InFIG. 2, regulator202can be used to maintain a signal supplied to antenna port104aat a stable voltage. Diode208detects the voltage of the signal on antenna port104aand feeds this information back to regulator202. In an embodiment, diode208is a full wave rectifier and detects the voltage peaks of the signal on antenna port104a. Diode208converts the AC signal on antenna port104ato an approximate DC signal. Regulator202compares the output of diode208to a reference voltage206, which can represent a desired voltage. If the regulator202determines that the voltage of the signal on antenna port104ais not maintained close to (e.g., within a predetermined range of) the desired voltage, regulator202can adjust its output to maintain the voltage of the signal supplied to antenna port104aat the desired value set by reference voltage206.

When antenna port104ais receiving a magnetic field, the circuit ofFIG. 2is turned “on.” In this state, horizontal switches212are closed, and vertical switches214are opened. Thus, regulator202couples to the gate of NMOS210a, and clamp control204couples to the gate of NMOS210b. As antenna port104areceives a magnetic field, a current flows through the antenna coupled to antenna port104a, and a voltage builds on antenna port104a. Regulator202compares the voltage detected by diode208against reference voltage206, and if the detected voltage is too high, regulator202increases the voltage supplied to the gate of NMOS210a, which in turn lowers the voltage supplied to antenna (and thus the current flowing through the antenna at antenna port104a). When diode208detects a lower voltage, regulator202will stop increasing the voltage supplied to the gate of NMOS210a.

Clamp control204can be used to prevent a voltage from antenna port104afrom exceeding a predefined magnitude. This functionality can be especially important if more than one antenna is present. For clarity, a single antenna port104ais shown inFIG. 2(e.g., for a single port antenna embodiment). However, it should be understood that embodiments of the present disclosure can include multiple antenna ports (e.g., for a dual port antenna embodiment). For example, an NFC embodiment of the present disclosure can include two antenna ports (e.g., as shown inFIG. 1B). In an embodiment of the present disclosure having two antenna ports, when the voltage at one antenna port is positive (i.e., higher than VSS116), the voltage at the other port becomes negative (i.e., it is driven lower than VSS116). Clamp control204can be used to prevent voltage lower than VSSfrom impacting the circuitry ofFIG. 2.

As previously discussed, when the circuit ofFIG. 2is turned “on” and antenna port104ais receiving a magnetic field, horizontal switches212are closed, and vertical switches214are opened. In this state, clamp control204is coupled to the gate of NMOS210b. If clamp control204detects that the voltage at antenna port104ais negative, clamp control204creates a short circuit between antenna port104aand VSS116using NMOS210b. For example, in an embodiment using two antenna ports, clamp control204can detect whether the voltage at antenna port104aor antenna port104bis higher. If the voltage at antenna port104bis higher than the voltage at antenna port104a, clamp control204can determine that antenna port104ais “negative.” In response, clamp control204adjusts the voltage supplied to the gate of NMOS210bsuch that there is a short circuit between antenna port104aand VSS116. By doing so, clamp control204prevents voltages lower than VSS116at antenna port104afrom negatively impacting the circuitry ofFIG. 2.

4. Integrated Antenna Driver, Regulator, and Clamp Control Circuit

As previously discussed, the separate circuits used to provide antenna driver functionality and regulator/clamp control functionality require several large transistors (e.g., transistors108,110, and210). By integrating antenna driver functionality, regulator functionality, and clamp control functionality into a single circuit, embodiments of the present disclosure advantageously provide antenna driver functionality, regulator functionality, and clamp control functionality using a reduced number of transistors. This reduction in the number of required transistors advantageously leads to a reduction in required real estate and manufacturing cost. For example, these transistors can each require 5% or more of the real estate on an C. Thus, embodiments of the present disclosure enable cheaper, smaller ICs for providing antenna driver functionality, regulator functionality, and clamp control functionality to be produced.

FIG. 3Ashows a circuit diagram of an integrated antenna driver, regulator, and clamp control circuit in accordance with an embodiment of the present disclosure. This circuit requires fewer transistors than two separate circuits providing antenna driver functionality and regulator/clamp functionality (e.g., as shown byFIGS. 1A,1B, and2). In an embodiment, the circuit ofFIG. 3Acan be implemented in an NFC device (e.g., NFC device602). For example, the circuit ofFIG. 3Acan be implemented as integrated antenna driver, regulator, and clamp control circuit870of power control module808.

In an embodiment, the circuit ofFIG. 3Acan be placed into two modes of operation: a mode of operation for receiving a magnetic field from antenna port104a(e.g., when antenna port104ais being used to support a target (tag) mode of an NFC device) and a mode of operation for creating a magnetic field via antenna port104a(e.g., when antenna port104ais being used to support an initiator (reader) mode of an NFC device).

If antenna port104ais being used to create a magnetic field, horizontal switches302a,302b, and302dare closed to allow a signal to propagate to PMOS306and NMOS308a. At the same time, vertical switch304is open, and horizontal switches302cand302eare open so that regulator202and clamp control204are disconnected from the rest of the circuit. In this mode, antenna predriver102generates a signal that gets amplified by PMOS306and NMOS308acoupled to antenna port104a. These large transistors allow antenna port104ato deliver a large current.

If antenna port104ais being used to receive a magnetic field, vertical switch304is closed, and horizontal switches302a,302b, and302dare opened to create an open circuit between antenna port104aand antenna predriver102. Horizontal switches302cand302eare closed to connect regulator202and clamp control204to the rest of the circuit. As antenna port104areceives a magnetic field, regulator202regulates a signal detected at antenna port104a, and clamp control204prevents a negative voltage (e.g., a voltage below VSS116) at antenna port104afrom negatively impacting the rest of the circuit.

FIG. 3Bshows another circuit diagram of an integrated antenna driver, regulator, and clamp control circuit in accordance with an embodiment of the present disclosure. In an embodiment, the circuit ofFIG. 3Bcan be implemented in an NFC device (e.g., NFC device602). For example, the circuit ofFIG. 3Bcan be implemented as integrated antenna driver, regulator, and clamp control circuit870of power control module808.

InFIG. 3B, diode310and feedback path312aare shown. In an embodiment, diode310is a rectifier (e.g., a full wave rectifier). When regulator202and clamp control204are switched in to the circuit (i.e., when antenna port104ais used to receive a magnetic field), diode310resolves the peak voltage associated with the incoming signal at antenna port104aand compares it to reference voltage206. Based on this comparison, regulator202can determine whether the voltage of the signal supplied to antenna port104ais too high (or too low). As previously discussed, regulator202can increase (or decrease) the amount of voltage supplied to NMOS308a(and thus alter the current at antenna port104a) to maintain the voltage at antenna port104aat a stable value.

FIG. 4shows a circuit diagram of an integrated antenna driver, regulator, and clamp control circuit for two antenna ports in accordance with an embodiment of the present disclosure. In an embodiment, the circuit ofFIG. 4can be implemented in an NFC device (e.g., NFC device602). For example, the circuit ofFIG. 4can be implemented as integrated antenna driver, regulator, and clamp control circuit870of power control module808.

InFIG. 4, antenna predriver102, regulator202, and clamp control204can be coupled to antenna port104avia horizontal switches302and to antenna port104bvia horizontal switches402. In an embodiment, antenna predriver102can drive a signal in antiphase such that the signal sent to antenna port104bis the opposite phase of the signal sent to antenna port104a.

In an embodiment, when antenna port104aand104bare being used to create a magnetic field, for example, antenna predriver102is connected to antenna ports104aand104b(e.g. by closing horizontal switches302a,302b,302d,402a,402b, and402d). Vertical switches304and404are also opened. Regulator202and clamp control204are disconnected from antenna ports104aand104bby opening horizontal switches302c,302e,402cand402e. If antenna ports104aand104bare being used to receive a magnetic field, antenna predriver102can be disconnected from antenna ports104aand104bby opening horizontal switches302a,302b,302d,402a,402b, and402dand closing vertical switches304and404. Regulator202and clamp control204can be coupled to antenna ports104aand104bby closing horizontal switches302c,302e,402c, and402e.

As current flows through the antenna, regulator202detects the voltage building on antenna port104bvia diode (e.g., full wave rectifier)310. By comparing this voltage against reference voltage206, regulator202can determine whether the current flowing through the antenna (via NMOS408a) should be increased or decreased. Clamp control204prevents a negative voltage (e.g., a voltage below VSS116) from negatively impacting the rest of the circuit ofFIG. 4. When the voltage at one antenna port is positive (i.e., higher than VSS116), the voltage at the other port can become negative (i.e., it is driven lower than VSS116). For example, if the voltage at antenna port104bis higher than the voltage at antenna port104a, clamp control204can determine that antenna1is “negative.” In response, clamp control204adjusts the voltage supplied to the gate of NMOS308asuch that there is a short circuit between antenna port104aand VSS116. By doing so, clamp control204prevents voltages lower than VSS116at antenna port104aor antenna port104bfrom negatively impacting the circuitry ofFIG. 4.

In the integrated circuit configuration shown byFIGS. 3A,3B, and4, one transistor can be “saved” per antenna. In other words, by integrating antenna driver functionality, regulator functionality, and clamp control functionality onto a single circuit, one less transistor is required per antenna port with respect to conventional devices that use a separate circuit to provide antenna driver functionality and a separate circuit to provide regulator/clamp control functionality, Thus, embodiments of the present disclosure enable cheaper and smaller communications devices supporting this functionality to be manufactured.

FIG. 5is a flowchart of a method for providing antenna driver functionality, regulator functionality, and clamp control functionality in accordance with an embodiment of the present disclosure. In step500, a determination is made regarding whether an antenna is used to receive a magnetic field or create a magnetic field. For example, a host device (e.g., an NFC device) can use an antenna port (e.g., using antenna port104a) to create a magnetic field (e.g., if the NFC device is operating in a reader mode) or to receive a magnetic field (e.g., if the NFC device is operating in a target mode). A circuit supporting antenna driver functionality, regulator functionality, and clamp control functionality can then be reconfigured in step502based on this determination.

If the antenna port is used to create a magnetic field, the antenna predriver is connected to the antenna in step504. For example, antenna predriver102is coupled to PMOS306and NMOS308aby closing horizontal switches302a,302b, and302dopening vertical switch304. In step506, the regulator is disconnected from the antenna. For example, regulator202is disconnected from NMOS308aby opening horizontal switch302c. In step508, the clamp control is also disconnected from the antenna. For example, clamp control204is disconnected from NMOS308bby opening horizontal switch302e.

If the antenna port (e.g., antenna port104a) is not used to create a magnetic field (i.e., if the antenna port is being used to receive a magnetic field), the antenna predriver is disconnected from the antenna port in step510. For example, antenna predriver is disconnected from the circuit by opening horizontal switches302a,302b, and302dand closing vertical switch304. In step512, the regulator is connected to the antenna port. For example, regulator202is coupled to NMOS308aby closing horizontal switch302c. In step512, the clamp control is also connected to the antenna port. For example, clamp control204is connected to NMOS308bby closing horizontal switch302e.

6. Other Embodiments

An antenna driver according to embodiments of the present disclosure can also include additional functionality. For example, load modulator functions can also be combined with regulator202. In an embodiment, load modulator functionality can also be supported without requiring additional transistors. Further, the NMOS input/output transistor (e.g., NMOS308a) can be configured to be driven by antenna predriver202, regulator202, and clamp control204while retaining a mode in which its gate can be pulled to VSS116to turn it off.

Regulator202can also be redesigned to incorporate a linear shunt. In this case, the protection NMOS transistor (e.g., NMOS308b) connects between the antenna ports (e.g., between antenna port104aand antenna port104b), not to VSS116, and a clamp device (e.g., clamp control204) is no longer required. Further, in an embodiment, the NMOS transistors of the linear shunt can be combined with the NMOS transistor used to support the antenna driver (e.g., NMOS308a).

The representative signal processing functions described herein (e.g. channel and source decoders, etc.) can be implemented in hardware, software, or some combination thereof. For instance, the signal processing functions can be implemented using computer processors, computer logic, application specific circuits (ASIC), digital signal processors, etc., as will be understood by those skilled in the art based on the discussion given herein. Accordingly, any processor that performs the signal processing functions described herein is within the scope and spirit of the present disclosure.

The above systems and methods can be implemented as a computer program executing on a machine, as a computer program product, or as a tangible and/or non-transitory computer-readable medium having stored instructions. For example, the functions described herein could be embodied by computer program instructions that are executed by a computer processor or any one of the hardware devices listed above. The computer program instructions cause the processor to perform the signal processing functions described herein. The computer program instructions (e.g. software) can be stored in a tangible non-transitory computer usable medium, computer program medium, or any storage medium that can be accessed by a computer or processor. Such media include a memory device such as a RAM or ROM, or other type of computer storage medium such as a computer disk or CD ROM. Accordingly, any tangible non-transitory computer storage medium having computer program code that cause a processor to perform the signal processing functions described herein are within the scope and spirit of the present disclosure.