ESD unit

An electrostatic discharge (ESD) unit is described, including a first device, and a second device coupled to the first device in parallel. In an ESD event, the first device is turned on before the second device is turned on. The second device may be turned on by the turned-on first device to form an ESD path in the ESD event.

BACKGROUND OF THE INVENTION

Field of Invention

This invention relates to protection of an integrated circuit (IC), and particularly relates to an electrostatic discharge (ESD) unit for protecting an internal circuit from damage caused by an ESD event.

Description of Related Art

During an ESD event, a large current may flow through an IC and easily cause damage. The damage may occur within the device that conducts the current, and also in devices that is subjected to a significant voltage drop due to the large current flow. In order to avoid damage due to an ESD event, an ESD unit is usually added to the IC.

Conventionally, a gate-grounded metal-oxide-semiconductor (GGMOS) device and a gate-driven protect circuit are used as an ESD unit, but they require a large area of the IC chip. In order to reduce the area of the ESD unit, the silicon-controlled rectifier (SCR), especially LDMOS-inserted SCR, is recently used.

FIG. 1illustrates a conventional SCR for ESD. The SCR typically has a PNPN structure that includes the P+-region and the N-well at the drain side, and the P-well and the N+-region at the source side, and may be considered to include a PNP bipolar junction transistor (BJT) and a NPN BJT coupled to the PNP BJT. The ESD path of the SCR is indicated by the arrow in the figure.

However, the ESD holding current of the conventional SCR tends to be lower than the maximal latch-up current (ILU) in normal operation, so the latch-up immunity becomes worse and the leakage becomes larger. In addition, the trigger voltage needed to trigger the SCR is higher, so that the effect of preventing ESD damage is worse.

SUMMARY OF THE INVENTION

In view of the foregoing, this invention provides an ESD unit that has a larger holding current and a lower trigger voltage.

The ESD unit of this invention includes a first device, and a second device coupled to the first device in parallel. In an ESD event, the first device is turned on before the second device is turned on.

In an embodiment, the second device is turned on by the turned-on first device to form an ESD path in the ESD event.

In some embodiments, the first device comprises a GGNMOS or an NPN BJT. A GGNMOS is known to include a parasitic NPN BJT. In some embodiments, the second device comprises an SCR.

In an embodiment, the first device comprises, as a first NPN BJT, a parasitic NPN BJT in a GGNMOS, or a non-parasitic NPN BJT, the second device comprises an SCR that comprises a second NPN BJT and a PNP BJT, the base of the first NPN BJT is electrically connected to the collector of the PNP BJT, and the base of the second NPN BJT, the emitter of the first NPN BJT is grounded, the collector of the first NPN BJT is electrically connected to the emitter of the PNP BJT and an I/O pad, the emitter of the second NPN BJT is grounded, and the collector of the second NPN BJT is electrically connected to the base of the PNP BJT.

In some embodiments, the first device and the second device are planar devices.

In some other embodiments, the first device and the second device are three-dimensional (3D) devices, such as fin device.

In some embodiments, the ESD unit further comprises a trigger element coupled to the first device in series. In the ESD event, the trigger element is turned on by an electrostatic voltage, and the first device is turned on by the turned-on trigger element.

According to a first aspect of this invention, the trigger element is embedded in a region where the first device is formed.

According to a second aspect of this invention, the trigger element is coupled to the first device externally.

According to a third aspect of this invention, no trigger element is included.

When the first device and the second device are planar devices and the trigger element is an embedded element, the trigger element is also a planar device. When the first device and the second device are fin devices and the trigger element is an embedded element, the trigger element is also a fin device.

Since the first device that is coupled to the second device in parallel and turned on earlier than the second device is included in the ESD unit of this invention, the holding current can be increased, so that the latch-up immunity of the ESD unit is improved and the leakage in normal operation is decreased. Moreover, in a case where the trigger element is further included in the ESD unit of this invention, the trigger voltage required to trigger the SCR can be lowered so that the effect of preventing ESD damage is improved.

DESCRIPTION OF EMBODIMENTS

This invention will be further explained with the following embodiments and the accompanying drawings, which are not intended to restrict the scope of this invention.

FIG. 2illustrates a block diagram of an ESD unit according to the third aspect of this invention without a trigger element.

The ESD unit includes a first device20, and a second device22coupled to the first device20in parallel, both of which are electrically connected to the I/O pad10. In an ESD event, the first device20is turned on to flow a current200before the second device22is turned on. The second device22may be turned on by the turned-on first device20to form an ESD path202in the ESD event.

FIG. 3illustrates a block diagram of an ESD unit according to the first and second aspects of this invention with a trigger element.

As compared to the ESD unit as shown inFIG. 2, the ESD unit according to the first or second aspect further includes a trigger element24that is also electrically connected to the I/O pad10. The trigger element24can be turned on by an electrostatic voltage, as indicated by the arrow204. The first device20can be turned on by a signal206transmitted from the turned-on trigger element24. The signal206may be a substrate current.

The trigger element24may include a diode, an RC-invertor, a diode couple device, or a CR circuit. The diode may be one that is formed using a shallow trench isolation (STI) layer, a gate layer, or a salicide blocking (SAB) layer as a mask, namely an STI diode, a gated diode, or an SAB diode. The diode may be an embedded diode that is embedded in a region where the first device20is formed. The RC-invertor, the diode couple device, or the CR circuit can be coupled to the first device20externally.

The first device20may include a GGNMOS or an NPN BJT. The GGNMOS is known to include a parasitic NPN BJT. The second device22may include an SCR. In the following embodiments, the first device includes a parasitic or non-parasitic NPN BJT and the second device includes an SCR.

FIG. 4Aillustrates a circuit diagram of an ESD unit according to certain embodiments in the third aspect of this invention without a trigger element.

The ESD unit includes a parasitic or non-parasitic NPN BJT40as the first device, and a SCR42as the second device, wherein the SCR42includes a PNP BJT42aand an NPN BJT42b. The base of the NPN BJT40is electrically connected to the collector of the PNP BJT42a, and the base of the NPN BJT42b. The emitter of the NPN BJT40is grounded. The collector of the NPN BJT40is electrically connected to the emitter of the PNP BJT42aand the I/O pad10. The emitter of the NPN BJT42bis grounded. The collector of the NPN BJT42bis electrically connected to the base of the PNP BJT42a.

FIG. 4Billustrates a circuit diagram of an ESD unit according to certain embodiments in the first aspect of this invention where the trigger element is embedded in a region where the first device is formed.

As compared to the ESD unit as shown inFIG. 4A, the ESD unit in embodiments in the first aspect of this invention further includes a trigger element that is an embedded diode44. The positive electrode of the diode44is electrically connected with the base of the NPN BJT40, and the negative electrode of the diode44is electrically connected with the I/O pad10, the collector of the NPN BJT40, and the emitter of the PNP BJT42a. Accordingly, the terminal of the trigger element or the embedded diode44that is coupled to the base of the NPN BJT40is the positive electrode thereof.

FIG. 4Cillustrates a circuit diagram of an ESD unit according to certain embodiments in the second aspect of this invention where the trigger element is coupled to the first device externally.

As compared to the ESD unit as shown inFIG. 4A, the ESD unit in embodiments in the second aspect of this invention further includes an externally coupled trigger element46, such as an RC-invertor, a diode couple device, or CR circuit. The externally coupled trigger element46is coupled to the base of the NPN BJT40for turning on the NPN BJT40after sensing an electrostatic voltage. When the externally coupled trigger element46comprises an RC-invertor or a CR circuit, the terminal of the trigger element46that is coupled to the base of the NPN BJT40as the first device is a trigger point of the RC-invertor or the CR circuit.

<First Aspect of this Invention (with Embedded Trigger Element)>

Some embodiments of the first aspect of this invention are described below, including two cases (first and second embodiments) based on planar devices, and a case (third embodiment) based on 3D devices.

FIG. 5Aillustrates a top view of an ESD unit according to the first embodiment of the first aspect of this invention,FIG. 5Billustrates the B-B cross-sectional view of the first device (GGNOS) in the ESD unit, andFIG. 5Cillustrates the C-C′ cross-sectional view of the second device (SCR). In the first embodiment, the trigger element, the first device and the second device are all planar devices.

Referring toFIG. 5A, the ESD unit includes two GGNMOS devices52as the first devices at two sides of one SCR54as the second device, and a trigger element50embedded in the region of each GGNMOS device52. Because the GGNMOS devices52and the trigger elements50are at the two edges of the ESD unit, the ESD unit can be called an edge-trigger ESD unit.

Referring toFIGS. 5A to 5C, the ESD unit is formed based on a P-substrate500. The GGNMOS devices52and the SCR54share a P-well502in the P-substrate500, an N-well504in the P-substrate500, two gate lines506each overlapping with the neighboring P-well502and the N-well504, an N+-source region508in the P-well502, and an N+-drain region510ain the N-well504. The SCR54further includes, in the N-well504, an N+-drain region510band a P+-drain region520between the N+-drain region510aand the N+-drain region510b. Accordingly, in view of each gate line506, the P-well502and the N+-source region508are at one side of the gate line506, and the N-well504and the N+-drain regions510aand510bare at the other side of the gate line506. The N+-drain regions510aand510bare electrically connected to an I/O pad10. The gate lines506, the N+-source region508and the P-well502are grounded, wherein the P-well502is grounded via a pick-up region522.

Each GGNMOS device52as the first device further has a P+-region512in the N-well504and a P+-region516in the P-well502, wherein the P+-region512forms the embedded diode50with the N-well504and is electrically connected to the P+-region516. The P+-region512in the N-well504may be formed with a portion of a patterned SAB layer514as a mask, as illustrated in the figures, but may alternatively be formed with a portion of a patterned STI layer or gate layer as a mask. The P+-region516in the N-well504may be formed with a patterned STI layer518as a mask.

As for the SCR54as the second device, the P+-region520in the N-well504, the N-well504, the P-substrate500, the P-well502and the N+-source region508in the P-well502together constitute a PNPN-type SCR. The P+-region520may be formed in the N-well504with another portion of the patterned SAB layer514as a mask, as illustrated in the figures, but may alternatively be formed with another portion of the patterned STI layer or gate layer as a mask. Moreover, the design that the P+-region520accompanies inner and outer portions of the patterned SAB layer514as illustrated inFIGS. 5A and 5Cis suitable for a high-voltage application. For a normal-voltage application, the inner portion of the patterned SAB layer514surrounded by the P+-region520(seeFIG. 5A), which is shown at the right side of the P+-region520inFIG. 5C, can be omitted so that the P+-region520contacts the N+-drain region510b(not shown).

The operation mechanism of the above ESD unit is described below. When an electrostatic voltage being high enough is generated at the I/O pad10, the diode50as the trigger element is turned on in backward bias, and a current540from the N+-drain region510ato the P+-region512is generated and is then transmitted to the P+-region516in the P-well502, as indicated by the arrow550. The current will raise the substrate bias to turn on the GGNMOS device52as the first device. After a sufficiently clamp voltage is generated by the GGNMOS device52, an SCR ESD path560is formed with increase in the voltage drop.

FIG. 6illustrates a top view of an ESD unit according to a second embodiment of the first aspect of this invention. In the second embodiment, the trigger element, the first device and the second device are all planar devices.

The second embodiment is different from the first embodiment in that the ESD unit includes two SCRs54as the second devices at two sides of one GGNMOS device52as the first device. A trigger element50embedded in the region of the GGNMOS device52. Because the GGNMOS device52and the trigger element50are at the middle of the ESD unit, the ESD unit can be called a middle-trigger ESD unit.

FIG. 7illustrates a top view of an ESD unit according to a third embodiment of the first aspect of this invention. In the third embodiment, the trigger element, the first device and the second device are all 3D devices, such as fin devices.

Referring toFIG. 7, the ESD unit includes two fin-type SCRs74as the second devices at two sides of one fin-type GGNMOS device72as the first devices, and a fin-type diode70as the trigger element embedded in the region of the fin-type GGNMOS device72. Such ESD is a middle-trigger ESD unit, as the trigger element70and the fin-type GGNMOS device72are at the middle of the ESD unit. The middle-trigger design can be readily changed into an edge-trigger design in reference of the case of the first and second embodiments.

The ESD unit includes a plurality of fin structures700, a P-well702shared by the two fin-type SCRs74and the fin-type GGNMOS device72, two N-wells704respectively in the two fin-type SCRs74, and two gate lines706each crossing over the fin structures700.

The embedded diode70includes a P+-fin segment712and an N+-fin segment710neighboring to the P+-fin segment712, wherein the P+-fin segment712and the N+-fin segment710are disposed on a P-well702, and the N+-fin segment710forms a diode with the P-well702.

The fin-type GGNMOS device72further includes, in view of a gate line706, at least one N+-fin segment708as a source at a second side of the gate line, at least one N+-fin segment710as a drain at a first side of the gate line, and a P+-fin segment716at the second side of the gate line706, wherein the at least one N+-fin segment708and the at least one N+-fin segment710are in the same fin structure(s)700, the at least one N+-fin segment708, the at least one N+-fin segment710and the P+-fin segment716are disposed on the P-well702, and the P+-fin segment716is electrically connected to the P+-fin segment712. The at least one N+-fin segment708, the P-well702and the at least one N+-fin segment710constitute a parasitic NPN BJT in the fin-type GGNMOS device72.

Each fin-type SCR74further includes, in view of a gate line706, at least one N+-fin segment708at the second side of the gate line706and on the P-well702, and at least one P+-fin segment720at the first side of the gate line706and on the N-well704. In each fin-type SCR74, the at least one P+-fin segment720, the N-well704, the P-well702and the at least one N+-fin segment708constitute a PNPN-type SCR.

The at least one N+-fin segment708in the fin-type GGNMOS device72and the at least one N+-fin segment708in an adjacent fin-type SCR74are grounded via the same contact line730a. The N+-fin segment710of the embedded diode70, the at least one N+-fin segment710in the fin-type GGNMOS device72, and the at least one P+-fin segment720in the adjacent fin-type SCR74are electrically connected to an I/O pad via the same contact line730b. The P+-fin segment716of the fin-type GGNMOS device72is electrically connected to the P+-fin segment712of the diode70via the contact730don the P+-fin segment716, the contact730con the P+-fin segment712, and an interconnect line (not shown).

<Second Aspect of this Invention (with Externally Coupled Trigger Element)>

Some embodiments of the second aspect of this invention are described below, including two cases (fourth and fifth embodiments) based on planar devices, and a case based on 3D devices (sixth embodiment).

FIG. 8Aillustrates a top view of an ESD unit according to a fourth embodiment of the second aspect of this invention, andFIG. 8Billustrates the B-B cross-sectional view of the first device in the ESD unit. In the fourth embodiment, the first device and the second device are both planar devices.

Referring toFIGS. 8A and 8B, the fourth embodiment is different from the first embodiment as shown inFIGS. 5A to 5Cin that the embedded diode50or the P+-region512is not formed but an external trigger element80is externally coupled to the P-well502shared by the GGNMOS devices82and the SCR84. The ESD unit of this fourth embodiment is an edge-trigger ESD unit according to the aforementioned definition.

FIG. 9illustrates a top view of an ESD unit according to a fifth embodiment of the second aspect of this invention. In the fifth embodiment, the first device and the second device are both planar devices.

The fifth embodiment is different from the fourth embodiment in that the ESD unit includes two SCRs84as the second devices at two sides of one GGNMOS device82as the first device without an embedded trigger element. The ESD unit of this fifth embodiment is a middle-trigger ESD unit according to the aforementioned definition.

FIG. 10illustrates a top view of an ESD unit according to a sixth embodiment of the second aspect of this invention. In the sixth embodiment, the first device and the second device are both fin devices, and the ESD unit is different from the ESD unit in the third embodiment as shown inFIG. 7mainly in that the embedded trigger element is replaced by an external trigger element.

Referring toFIG. 10, the ESD unit includes two fin-type SCRs104as the second devices at two sides of one fin-type GGNMOS device102as the first device. The fin-type GGNMOS device102and two fin-type SCRs104include fin structures1000, a P-well1002, two N-wells1004, two gate lines1006, N+-fin segments1008, N+-fin segments1010, P+-fin segments1016, P+-fin segments1020, contact lines1030a, a contact line1030band contacts1030dthat are arranged and configured like the parts700,702,704,706,708,710,716,720,730a,730band730d, respectively, in the ESD unit as shown inFIG. 7, and are different from the latter in not including parts corresponding to the P+-fin segments712for forming the embedded trigger element or diode and the contacts730con the P+-fin segments712. Instead of an embedded diode as an embedded trigger element, the ESD unit of the sixth embodiment includes an external trigger element100that is externally electrically connected with the contacts1030don the P+-fin segments1016via interconnect lines1040. Such ESD is a middle-trigger ESD unit, as the fin-type GGNMOS device102is at the middle of the ESD unit. The middle-trigger design can be readily changed into an edge-trigger design in reference of the case of the first and second embodiments.

<Third Aspect of this Invention (without Trigger Element)>

Some embodiments of the third aspect of this invention are described below, including two cases (seventh and eighth embodiments) based on planar devices, and a case based on 3D devices (ninth embodiment).

FIG. 11Aillustrates a top view of an ESD unit according to a seventh embodiment of the third aspect of this invention, andFIG. 11Billustrates the B-B cross-sectional view of the first device in the ESD unit. In the seventh embodiment, the first device and the second device are both planar devices.

Referring toFIG. 11A/11B, the seventh embodiment is different from the fourth embodiment as shown inFIG. 8A/8B in that an N-well (504) is not formed at the opposite side of the P-well502, that the P-well502extends from the source side of the gate line506to the drain side of the same and covers the N+-drain region510a/bso that breakdown will occur between the N+-drain region510a/band the P-well502lowering the breakdown voltage, that a P+-region (516) and a patterned STI layer (518) for defining the region thereof are not formed in the P-well502shared by the GGNMOS devices112and the SCR114therebetween, and that no external trigger element (80) is coupled to the P-well502. Accordingly, the P+-region520(FIG. 5C), the N+-drain region510a, the P-substrate500, the P-well502, and the N+-source region508in the P-well502together constitute a PNPN-type SCR as the SCR114. Since the parasitic BJTs in the GGNMOS devices112as the first devices are turned on earlier than the SCR114as the second device, the same effects can be made without an external or embedded trigger element.

FIG. 12illustrates a top view of an ESD unit according to an eighth embodiment of the third aspect of this invention. In the eighth embodiment, the first device and the second device are both planar devices.

The eighth embodiment is different from the seventh embodiment in that the ESD unit includes two SCRs114as the second devices at two sides of one GGNMOS device112as the first device without an embedded trigger element.

FIG. 13illustrates a top view of an ESD unit according to a ninth embodiment of the third aspect of this invention. In the ninth embodiment, the first device and the second device are both fin devices, and the ESD unit is different from the ESD unit in the third embodiment as shown inFIG. 7, or the ESD unit in the sixth embodiment as shown inFIG. 10, mainly in that the trigger element is omitted.

Referring toFIG. 13, the ESD unit includes two fin-type SCRs134as the second devices at two sides of one fin-type GGNMOS device132as the first device. The fin-type GGNMOS device132and two fin-type SCRs134include fin structures1300, a P-well1302, two N-wells1304, two gate lines1306, N+-fin segments1308, N+-fin segments1310, P+-fin segments1320, contact lines1330aand a contact line1330bthat are arranged and configured like the parts700,702,704,706,708,710,720,730aand730b, respectively, in the ESD unit as shown inFIG. 7, and are different from the latter in not including parts corresponding to the P+-fin segments712and P+-fin segments716and the contacts730cand730dthereon. Briefly, no P+-fin segment for forming an embedded trigger element or for electrically connecting with an external trigger element is formed in the ESD unit of the ninth embodiment without a trigger element. Since the parasitic BJT in the fin-type GGNMOS device132as the first device is turned on earlier than the fin-type SCRs134as the second devices, the same effects can be made without an embedded or external trigger element.

No matter the ESD unit of this invention is of an edge-trigger type or of a middle-trigger type, or includes planar devices or 3D devices, since the first device that is coupled to the second device in parallel and is turned on earlier than the second device is included in the ESD unit of this invention, the holding current can be increased, so that the latch-up immunity of the ESD unit is improved and the leakage in normal operation is decreased.

Moreover, when the ESD unit of this invention includes a trigger element, no matter the trigger element is embedded or external, the trigger voltage required to trigger the SCR can be lowered so that the effect of preventing ESD damage is improved.

This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.