Semiconductor structure and manufacturing method thereof

A semiconductor structure including a substrate, a dielectric layer and a polysilicon layer is provided. The dielectric layer is disposed on the substrate. The polysilicon layer is disposed on the dielectric layer. A fluorine dopant concentration in the polysilicon layer presents Gaussian distributions from a top portion to a bottom portion of the polysilicon layer. Fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the priority benefits of China application serial no. 201710479670.X, filed on Jun. 22, 2017. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a semiconductor structure and a manufacturing method thereof, and particularly relates to a semiconductor structure capable effectively mitigating flicker noise and a manufacturing method thereof.

Description of Related Art

In a semiconductor device, when a dielectric layer has excessive oxide traps, flicker noise is increased to decrease a performance of the semiconductor device.

At present, the industry often uses fluorine dopant to fill the oxide traps, so as to decrease the flicker noise. However, the above solution may only fill the oxide traps located at an interface of the dielectric layer and a substrate, so that only the flicker noise of a high frequency portion is mitigated, and the flicker noise of other frequency (for example, a low frequency) portion cannot be mitigated.

SUMMARY OF THE INVENTION

The invention is directed to a semiconductor structure and a manufacturing method thereof, which are adapted to mitigate flicker noise of both of a high frequency portion and a low frequency portion.

The invention provides a semiconductor structure including a substrate, a dielectric layer and a polysilicon layer. The dielectric layer is disposed on the substrate. The polysilicon layer is disposed on the dielectric layer. A fluorine dopant concentration in the polysilicon layer presents Gaussian distributions from a top portion to a bottom portion of the polysilicon layer. Fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer.

In an embodiment of the invention, in the aforementioned semiconductor structure, the substrate is, for example, a silicon substrate.

In an embodiment of the invention, in the aforementioned semiconductor structure, a material of the dielectric layer is, for example, silicon oxide.

In an embodiment of the invention, in the aforementioned semiconductor structure, a material of the polysilicon layer is, for example, doped polysilicon or undoped polysilicon.

In an embodiment of the invention, in the aforementioned semiconductor structure, the fluorine dopant peak concentrations include a first fluorine dopant peak concentration and a second fluorine dopant peak concentration. The first fluorine dopant peak concentration is close to the bottom portion of the polysilicon layer. The second fluorine dopant peak concentration is close to the top portion of the polysilicon layer.

In an embodiment of the invention, in the aforementioned semiconductor structure, the fluorine dopant peak concentrations further include a third fluorine dopant peak concentration. Compared to the second fluorine dopant peak concentration, the third fluorine dopant peak concentration is closer to the top portion of the polysilicon layer.

The invention provides a method for manufacturing a semiconductor structure, which includes following steps. A dielectric layer is formed on a substrate. A polysilicon layer is formed on the dielectric layer. Ion implantation processes are performed to the polysilicon layer by using a fluorine dopant. Implantation depths of the ion implantation processes are different. A fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth. After the ion implantation processes, a thermal process is performed to the polysilicon layer.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, a method of forming the dielectric layer is, for example, thermal oxidation or chemical vapor deposition.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, a method of foil ling the polysilicon layer is, for example, chemical vapor deposition.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, the polysilicon layer is, for example, an unpatterned polysilicon layer or a patterned polysilicon layer.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, the step of performing ion implantation processes to the polysilicon layer is, for example, performed before a lightly doped drain (LDD), a source region or a drain region is formed.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, a fluorine dopant concentration in the polysilicon layer may present Gaussian distributions from a top portion to a bottom portion of the polysilicon layer. Fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, the fluorine dopant peak concentrations include a first fluorine dopant peak concentration and a second fluorine dopant peak concentration. The first fluorine dopant peak concentration is close to the bottom portion of the polysilicon layer. The second fluorine dopant peak concentration is close to the top portion of the polysilicon layer.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, the fluorine dopant peak concentrations further include a third fluorine dopant peak concentration. Compared to the second fluorine dopant peak concentration, the third fluorine dopant peak concentration is closer to the top portion of the polysilicon layer.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, after the thermal process, the fluorine dopant concentration in the polysilicon layer may still present the Gaussian distributions.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, implantation energy of the ion implantation process with the deeper implantation depth is, for example, greater than implantation energy of the ion implantation process with the shallower implantation depth.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, the ion implantation processes include following steps. A first ion implantation process and a second ion implantation process are performed to the polysilicon layer. A first fluorine dopant concentration of the first ion implantation process is smaller than a second fluorine dopant concentration of the second ion implantation process. First implantation energy of the first ion implantation process is greater than second implantation energy of the second ion implantation process.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, the ion implantation processes further include a following step. A third ion implantation process is performed to the polysilicon layer. The second fluorine dopant concentration of the second ion implantation process is smaller than a third fluorine dopant concentration of the third ion implantation process. The second implantation energy of the second ion implantation process is greater than third implantation energy of the third ion implantation process.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, the first ion implantation process, the second implantation process and the third ion implantation process may be sequentially performed.

According to an embodiment of the invention, in the aforementioned method for manufacturing the semiconductor structure, the first ion implantation process, the second implantation process and the third ion implantation process may not be sequentially performed.

According to the above description, in the semiconductor structure of the invention, since the fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer, a specific fluorine dopant concentration distribution is formed in the polysilicon layer. In this way, after the thermal process is performed to the polysilicon layer, the fluorine dopant in the polysilicon layer is diffused into the dielectric layer, so that the oxide traps in the whole dielectric layer may be filled by the fluorine dopant in the Gaussian distributions with different fluorine dopant peak concentrations, so as to mitigate the flicker noise of both of a high frequency portion and a low frequency portion.

Moreover, in the method for manufacturing the semiconductor structure of the invention, since the fluorine dopant concentration of the ion implantation process with the deeper implantation depth is smaller than the fluorine dopant concentration of the ion implantation process with the shallower implantation depth, a specific fluorine dopant concentration distribution is formed in the polysilicon layer. In this way, after the thermal process is performed to the polysilicon layer, since the fluorine dopant in the polysilicon layer is diffused into the dielectric layer, the oxide traps in the whole dielectric layer may be filled by using the fluorine dopant in the specific fluorine dopant concentration distribution, so as to mitigate the flicker noise of both of the high frequency portion and the low frequency portion.

DESCRIPTION OF EMBODIMENTS

FIG. 1AtoFIG. 1Care cross-sectional views of a process of manufacturing a semiconductor structure according to an embodiment of the invention. Moreover, inFIG. 1AtoFIG. 1C, relationship curve diagrams of depth positions and fluorine dopant concentrations are also illustrated.

Referring toFIG. 1A, a dielectric layer102is formed on a substrate100. The substrate100may be a semiconductor substrate, for example, a silicon substrate. A material of the dielectric layer102is, for example, oxide (for example, silicon oxide). A method for forming the dielectric layer102is, for example, thermal oxidation or chemical vapor deposition.

A polysilicon layer104is formed on the dielectric layer102. A material of the polysilicon layer104is, for example, doped polysilicon or undoped polysilicon. A method for forming the polysilicon layer104is, for example, the chemical vapor deposition.

Ion implantation processes are performed to the polysilicon layer104by using a fluorine dopant, where implantation depths of the ion implantation processes are different. A fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth. Implantation energy of the ion implantation process with the deeper implantation depth is, for example, greater than implantation energy of the ion implantation process with the shallower implantation depth. The ion implantation processes performed to the polysilicon layer is, for example, performed before a lightly doped drain (LDD), a source region or a drain region is formed.

In this way, the fluorine dopant concentration in the polysilicon layer104may present Gaussian distributions from a top portion to a bottom portion of the polysilicon layer104. Fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer104. The top portion of the polysilicon layer104is the portion of the polysilicon layer104located away from the dielectric layer102. The bottom portion of the polysilicon layer104is the portion of the polysilicon layer104located close to the dielectric layer102.

For example, the ion implantation processes performed to the polysilicon layer104by using the fluorine dopant may include a first ion implantation process110and a second ion implantation process112performed to the polysilicon layer104, and may further include a third ion implantation process114performed to the polysilicon layer104. In the present embodiment, the first ion implantation process110, the second ion implantation process112and the third ion implantation process114are sequentially performed as an example. In another embodiment, the first ion implantation process110, the second ion implantation process112and the third ion implantation process114may not be sequentially performed.

In the first ion implantation process110, the second ion implantation process112and the third ion implantation process114, the implantation depth of the first ion implantation process110is the deepest, the implantation depth of the second ion implantation process112is shallower, and the implantation depth of the third ion implantation process114is the shallowest. A first fluorine dopant concentration of the first ion implantation process110is smaller than a second fluorine dopant concentration of the second ion implantation process112. The second fluorine dopant concentration of the second ion implantation process112is smaller than a third fluorine dopant concentration of the third ion implantation process114. The first fluorine dopant concentration may be 1×1015ions/cm2to 4×1015ions/cm2, for example, 3×1015ions/cm2. The second fluorine dopant concentration may be 5×1015ions/cm2to 7×1015ions/cm2, for example, 6×1015ions/cm2. The third fluorine dopant concentration may be 8×1015ions/cm2to 1×1016ions/cm2, for example, 8×1015ions/cm2.

First implantation energy of the first ion implantation process110may be greater than second implantation energy of the second ion implantation process112. The second implantation energy of the second ion implantation process112may be greater than third implantation energy of the third ion implantation process114. The first implantation energy may be 27 KeV to 33 KeV, for example, 30 KeV. The second implantation energy may be 18 KeV to 22 KeV, for example, 20 KeV. The third implantation energy may be 9 KeV to 11 KeV, for example, 10 KeV.

Therefore, referring to a relationship curve diagram of the depth position and the fluorine dopant concentration ofFIG. 1A, the fluorine dopant concentration in the polysilicon layer104may present a third Gaussian distribution G3, a second Gaussian distribution G2and a first Gaussian distribution G1from the top portion to the bottom portion of the polysilicon layer104. The first Gaussian distribution G1, the second Gaussian distribution G2and the third Gaussian distribution G3respectively have a first fluorine dopant peak concentration P1, a second fluorine dopant peak concentration P2and a third fluorine dopant peak concentration P3. The first fluorine dopant peak concentration P1may be close to the bottom portion of the polysilicon layer104. The second fluorine dopant peak concentration P2may be close to the top portion of the polysilicon layer104. Moreover, compared to the second fluorine dopant peak concentration P2, the third fluorine dopant peak concentration P3may be closer to the top portion of the polysilicon layer104. The second fluorine dopant peak concentration P2may be greater than the first fluorine dopant peak concentration P1. The third fluorine dopant peak concentration P3may be greater than the second fluorine dopant peak concentration P2.

Referring toFIG. 1B, a patterning process may be performed to the polysilicon layer104and the dielectric layer102to form patterned polysilicon layer104aand dielectric layer102a. The polysilicon layer104amay serve as a gate. The dielectric layer102amay serve as a gate dielectric layer. The patterning process is, for example, a combination of a lithography process and an etching process.

In the present embodiment, after the ion implantation processes are first performed to the unpatterned polysilicon layer104, the polysilicon layer104is then patterned, though the invention is not limited thereto. In another embodiment, after the polysilicon layer104is first patterned, the ion implantation processes are then performed to the patterned polysilicon layer104a.

Referring to a relationship curve diagram of depth positions and fluorine dopant concentrations ofFIG. 1AandFIG. 1B, the fluorine dopant concentration distribution in the polysilicon layer104aand the fluorine dopant concentration distribution of the polysilicon layer104are substantially the same.

Referring toFIG. 1C, after the ion implantation processes are performed, a thermal process120is performed to the polysilicon layer104a. The thermal process120may be a subsequent thermal process used for forming the source region or the drain region or an additionally perform thermal process.

After the thermal process120is performed, the fluorine dopant concentration in the polysilicon layer104amay still present the Gaussian distributions. Since after the thermal process120is performed, the fluorine dopant is diffused into the dielectric layer102a, oxide traps of the whole dielectric layer102amay be filled by the fluorine dopant. Therefore, after the thermal process120is performed, the fluorine dopant concentration in the polysilicon layer104ais decreased.

For example, referring to a relationship curve diagram of depth positions and fluorine dopant concentration ofFIG. 1C, after the thermal process120is performed, the fluorine dopant concentration in the polysilicon layer104amay still present the first Gaussian distribution G1, the second Gaussian distribution G2and the third Gaussian distribution G3, where the first fluorine dopant peak concentration P1of the first Gaussian distribution G1is decreased to a first fluorine dopant peak concentration P1a, the second fluorine dopant peak concentration P2of the second Gaussian distribution G2is decreased to a second fluorine dopant peak concentration P2a, and the third fluorine dopant peak concentration P3of the third Gaussian distribution G3is decreased to a third fluorine dopant peak concentration P3a.

In the present embodiment, it is assumed that three ion implantation processes are performed, such that the fluorine dopant concentration may present three Gaussian distributions in the polysilicon layer104a, though the invention not limited thereto. It is considered to be within a protection range as long as two or more ion implantation processes are performed to make the fluorine dopant concentration to present two or more Gaussian distributions in the polysilicon layer104a.

Based on the above description, it is known that in the method for manufacturing the semiconductor structure, since the fluorine dopant concentration of the ion implantation process with the deeper implantation depth is smaller than the fluorine dopant concentration of the ion implantation process with the shallower implantation depth, a specific fluorine dopant concentration distribution is formed in the polysilicon layer104a. In this way, after the thermal process is performed to the polysilicon layer104a, since the fluorine dopant in the polysilicon layer104ais diffused into the dielectric layer102a, the oxide traps in the whole dielectric layer102acan be filled by the fluorine dopant in the specific fluorine dopant concentration distribution, so as to mitigate the flicker noise of both of the high frequency portion and the low frequency portion.

The semiconductor structure of the aforementioned embodiment is described below with reference ofFIG. 1B.

Referring toFIG. 1B, the semiconductor structure includes the substrate100, the dielectric layer102aand the polysilicon layer104a. The dielectric layer102ais disposed on the substrate100. The polysilicon layer104ais disposed on the dielectric layer102a. A fluorine dopant concentration in the polysilicon layer104apresents Gaussian distributions (for example, the third Gaussian distribution G3, the second Gaussian distribution G2and the first Gaussian distribution G1) from the top portion to the bottom portion of the polysilicon layer104a. Fluorine dopant peak concentrations (for example, the third fluorine dopant peak concentration P3, the second fluorine dopant peak concentration P2and the first fluorine dopant peak concentration P1) of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer104a. Moreover, materials, configuration methods, forming methods and effects of various components of the semiconductor structure have been describe in detail in the aforementioned embodiment, and details thereof are not repeated.

Based on the aforementioned embodiment, it is known that in the semiconductor structure, since the fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer104a, the specific fluorine dopant concentration distribution is formed in the polysilicon layer. In this way, after the thermal process is performed to the polysilicon layer104a, since the fluorine dopant in the polysilicon layer104ais diffused into the dielectric layer102a, the oxide traps in the whole dielectric layer102amay be filled by the fluorine dopant in the Gaussian distributions with different fluorine dopant peak concentrations, so as to mitigate the flicker noise of both of the high frequency portion and the low frequency portion.

In summary, in the semiconductor structure and the manufacturing method thereof of the invention, by adjusting the fluorine dopant concentration distribution in the polysilicon layer, the flicker noise of both of the high frequency portion and the low frequency portion is mitigated.