Method of manufacturing semiconductor device utilizing outdiffusion and epitaxial deposition

A method of manufacturing a semiconductor device, which comprises the steps of forming a first high impurity concentration region of a conductivity type opposite to the conductivity type of a semiconductor substrate in the substrate along the principal surface thereof, depositing a first epitaxial layer of the same conductivity type as the substrate on the entire principal surface thereof, forming a low impurity concentration region of the opposite conductivity type to the substrate in the first epitaxial layer along a surface portion thereof corresponding to the first high impurity concentration region, forming a second high impurity concentration region of the opposite conductivity type to the substrate in the first epitaxial layer along a different surface portion thereof, forming a second epitaxial layer of the opposite conductivity type to the substrate on the first epitaxial layer, thermally treating the resultant intermediate device to cause diffusion of the impurities in the first and second high impurity concentration region into the respective first and second epitaxial layers and also causing diffusion of the impurity in the low impurity concentration region into the entire portion of the first epitaxial layer corresponding to the first high impurity concentration region, and forming an element isolation region of the same conductivity type as the substrate in the second epitaxial layer such that the element isolation region reaches the first epitaxial layer.

BACKGROUND OF THE INVENTION 
This invention relates to methods of manufacturing semiconductor devices 
and, more particularly, to a method of manufacturing a semiconductor 
device in which a high breakdown voltage semiconductor element and a low 
breakdown voltage semiconductor element are formed on the same 
semiconductor substrate. 
Semiconductor devices, in which a high breakdown voltage bipolar transistor 
and a low breakdown voltage bipolar transistor are respectively formed 
within a high breakdown voltage element region and a low breakdown voltage 
element region, these regions being defined in a single semiconductor 
substrate, are in practical use. In the semiconductor device of this 
structure, an isolation region is provided between the high breakdown 
voltage and low breakdown voltage bipolar transistors. 
In the prior-art method of manufacturing this semi-conductor device, the 
isolation region is formed by diffusing an impurity from the surface of 
the eventual device in the last or practically last step of the 
manufacturing process. This means that the diffusion at this time has to 
be made considerably deep. Therefore, it is inevitable that the isolation 
region spreads laterally a considerable distance, i.e., along the surface 
of the device. Namely, this region occupies a considerable area, which is 
undesirable from the standpoint of the integration density. 
In another aspect, a high impurity concentration buried layer is provided 
within the low breakdown voltage element region. With the prior-art device 
the distance between this buried layer and the collector of the low 
breakdown voltage bipolar transistor is comparatively large. Therefore, 
the collector series resistance between that collector and the buried 
layer is considerably high. This means that the saturation characteristic, 
i.e., the collector saturation voltage, of the low breakdown voltage 
bipolar transistor is considerably high. 
SUMMARY OF THE INVENTION 
An object of the invention, accordingly, is to provide a method of 
manufacturing a semiconductor device, with which it is possible to reduce 
the collector series resistance of the low breakdown voltage element for 
improving the saturation characteristic of that element and also reduce 
the superficial area of the isolation region formed between the high 
breakdown voltage and low breakdown voltage elements for realizing a high 
integration density. 
According to the invention, there is provided a method of manufacturing a 
semiconductor device which comprises the steps of selectively forming at 
least one first high impurity concentration region of a conductivity type 
opposite to the conductivity type of a semiconductor substrate and having 
a desired depth in the substrate along the principal surface thereof, 
depositing a first epitaxial layer of the same conductivity type as the 
substrate on the entire principal surface of the substrate, selectively 
forming at least one second high impurity concentration region of the 
opposite conductivity type to the substrate in the first epitaxial layer 
along a surface portion thereof not corresponding to the first high 
impurity concentration region, selectively forming a low impurity 
concentration region of the opposite conductivity type to the substrate in 
the first epitaxial layer along a surface portion thereof corresponding to 
the first high impurity concentration region, depositing a second 
epitaxial layer and subsequently thermally treating the resultant system, 
forming an element isolation region of the same conductivity type as the 
first epitaxial layer in a portion of the second epitaxial layer between 
the first and second high impurity concentration regions such that the 
isolation region reaches the surface of the first epitaxial layer, and 
forming at least one high breakdown voltage semiconductor element in a 
portion of the second epitaxial layer corresponding to the first high 
impurity concentration region and at least one low breakdown voltage 
semiconductor element in a portion of the second epitaxial layer 
corresponding to the second high impurity concentration region.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
The invention will now be described in conjunction with an example thereof 
applied to the manufacture of a bipolar transistor device with reference 
to FIGS. 1 to 10. 
EXAMPLE 
[1] As shown in FIG. 1, a thermal oxidation film 2 is formed contiguous to 
the entire surface of a p-type silicon substrate 1 with a resistivity of 
10 .OMEGA.cm to 50 .OMEGA.cm and is selectively removed by photo-etching 
techniques to form a diffusion window 3 over a high breakdown voltage 
element forming region. Then, an impurity of the opposite conductivity 
type to the silicon substrate 1, i.e., n-type, (e.g., arsenic or antimony) 
is diffused into the substrate 1 through the diffusion window 3 to form a 
first n.sup.+ -type impurity region 4 of a high surface impurity 
concentration, namely 5.times.10.sup.19 /cm.sup.3 (as shown in FIG. 2). 
The depth of diffusion at this time is 5 .mu.m. 
[2] Subsequently, the thermal oxidation film 2 is removed, and then 
boron-added silicon is epitaxially grown as a p-type epitaxial layer 
(first expitaxial layer) 5, of the same conductivity type as the silicon 
substrate 1, to a thickness of 20 .mu.m atop the substrate 1, as shown in 
FIG. 3. 
[3] Then, as shown in FIG. 4 another thermal oxidation film 6 is formed 
contiguous to the surface of the wafer consisting of the silicon substrate 
1 and p-type epitaxial layer 5 and is selectively removed by the 
photo-etching techniques to form a diffusion window 7 over a low breakdown 
voltage element forming region other than the high breakdown voltage 
element forming region including the first n.sup.+ -type region 4. 
Subsequently, an n-type impurity, of the opposite conductivity type to the 
substrate 1, (e.g., arsenic or antimony) is injected into the p-type 
epitaxial layer 5 through the diffusion window 7 to form a second n.sup.+ 
-type impurity region 8 of a high surface impurity concentration, namely 
5.times.10.sup.19 /cm.sup.3 (as shown in FIG. 5). 
[4] Then, as shown in FIG. 6 the diffusion window 7 is closed with a 
thermal oxidation layer 6', and thereafter a portion of the thermal 
oxidation film 6 corresponding to the first n.sup.+ -type impurity region 
4 is photo-etched to form a diffusion window 9. Subsequently, a low 
impurity concentration or n.sup.- -type impurity region 10 of an impurity 
concentration of 7.times.10.sup.11 /cm.sup.2 is formed in the p-type 
epitaxial layer 5 through ion injection of an n-type impurity, for 
instance phosphorus, through the diffusion window 9 (as shown in FIG. 7). 
[5] Then, the thermal oxidation films 6 and 6' are removed, and 
arsenic-added silicon is epitaxially grown as an n.sup.- -type epitaxial 
layer (second epitaxial layer) 11 atop the substrate 1. Afterwards, the 
resultant device is thermally treated at 1,200.degree. C. In consequence, 
a structure as shown in FIG. 8 is obtained. More particularly, a buried 
layer 12 of n.sup.+ -type is formed as a result of diffusion of arsenic 
from the n.sup.+ -type impurity region 4 in the p-type silicon substrate 1 
into the epitaxial layer 5, while also a deep high breakdown voltage 
element region 13 which occupies a portion of the epitaxial layer 5 and a 
portion of the upper contiguous epitaxial layer 11 is formed as a result 
of the conversion of that portion of the p-type epitaxial layer 5 into an 
n.sup.- -type epitaxial layer 5a caused by the diffusion of phosphorus 
from the n.sup.- -type impurity region 10 into that portion of the p-type 
epitaxial layer 5. At the same time, an n.sup.+ -type buried layer 14 is 
formed as a result of the diffusion of arsenic from the second n.sup.+ 
-type impurity region 8 in the p-type epitaxial layer 5 into the epitaxial 
layer 11, while also a shallow low breakdown voltage element region 15 is 
formed in the upper n.sup.- -type epitaxial layer 11. 
[6] Then, boron is selectively injected or diffused into a boundary portion 
of the n.sup.- -type epitaxial layer 11 between the high breakdown voltage 
element regions 13 and 15 to form a p.sup.+ -type isolation region 16 (as 
shown in FIG. 9). The injection depth of the isolation region 16 need only 
cover the thickness of the second epitaxial layer, i.e., the n.sup.- -type 
epitaxial layer 11 which is 15 .mu.m in thickness for the first epitaxial 
layer 5 is of p-type. 
[7] Afterwards, as shown in FIG. 10, p-type outer and inner bases 17 and 18 
are formed in the high breakdown voltage element region 13, and then an 
emitter 19 and a collector 20, which are of n-type, are formed in the 
inner base 18 and in a separate portion of the element region 13 
respectively. In this way, a high breakdown voltage bipolar transistor is 
formed. Meanwhile, p-type outer and inner bases 21 and 22, an n-type 
emitter 23 and an n-type collector 24 are similarly formed in the low 
breakdown voltage element region 15 to obtain a low breakdown voltage 
bipolar transistor. 
It has been found that the bipolar transistors which are formed in the 
above way respectively have high breakdown voltage and low breakdown 
voltage characteristics. Also, it has been found that the collector series 
resistance which is offered by the portion between the collector region 24 
in the epitaxial layer 11 and the n.sup.+ -type buried layer 14, and hence 
the collector saturation voltage, is sufficiently low to obtain a 
satisfactory saturation characteristic. This is attributable to the fact 
that the collector region 24 of the low breakdown voltage element and the 
buried layer 14 are close to each other. Further, since the injection or 
diffusion depth of the p.sup.+ -type isolation region 16 need only cover 
the thickness of the second epitaxial layer (i.e., n.sup.- -type epitaxial 
layer 11) and is comparatively small, the isolation region 16 does not 
spread laterally too much. In other words, it is possible to form an 
isolation region occupying a narrow area of the surface of the device, so 
that a high density of integration can be obtained in the manufacture of a 
bipolar transistor device. 
The surface impurity concentration of the first and second high impurity 
concentration regions according to the invention vary with different 
impurities, but usually it is preferably 1.times.10.sup.19 /cm.sup.3 to 
5.times.10.sup.19 /cm.sup.3. The depth of these impurity regions may be 5 
.mu.m to 15 .mu.m. 
The impurity concentration of the first epitaxial layer according to the 
invention may usually be 1.times.10.sup.14 /cm.sup.3 to 5.times.10.sup.14 
/cm.sup.3. The thickness of this epitaxial layer is preferably 10 .mu.m to 
20 .mu.m. 
The amount of the dosed impurities of the low impurity concentration region 
10 according to the invention is preferably 7.times.10.sup.11 /cm.sup.2 to 
1.2.times.10.sup.12 /cm.sup.2. 
The impurity concentration of the second epitaxial layer 11 according to 
the invention, of the opposite conductivity type to the semiconductor 
substrate 1, is preferably 1.times.10.sup.14 /cm.sup.3 to 
5.times.10.sup.14 /cm.sup.3. The thickness of this epitaxial layer is 
preferably 10 .mu.m to 20 .mu.m. 
As has been described in the foregoing, according to the invention the 
saturation characteristic can be improved by reducing the collector series 
resistance of the low breakdown voltage element without increasing the 
area thereof, and also can form an element isolation region, which does 
not spread laterally too much and has a narrow area. Thus, it is possible 
to provide a method of manufacturing a semiconductor device of high 
reliability and high integration density.