Light emitting display device

A light emitting display device, includes: a plurality of pixels arranged in a matrix form, each of the plurality of pixels including: a light emitting element in which a light emitting diode is between an anode and a cathode; a light emission transistor, one of a source or a drain of the light emission transistor is connected to the anode; a driving transistor, one of a source or a drain of the driving transistor is connected to the other of the source or the drain of the light emission transistor; and an initialization transistor which is configured to connect a gate of the driving transistor, the one of the source or the drain of the driving transistor, and the anode, the anode being connected to an initialization voltage line of a fixed voltage at a same time, wherein initialization transistor has a resistance greater than the driving transistor.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application claims the priority benefit of Japanese Patent Application No. 2018-238137 filed in Japan on Dec. 20, 2018, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein.

BACKGROUND

Technical Field

The present disclosure relates to a light emitting display device.

Description of the Related Art

Various display devices capable of reducing weight and volume, which are disadvantages of a cathode ray tube, are developed. Such display devices may be implemented as a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an electroluminescence display, etc.

BRIEF SUMMARY

Pi Based on known techniques, it is difficult to make it possible to attain initialization of an anode of a light emitting element and an auxiliary capacitor and compensation for a voltage variation of a power voltage line while maintaining a low number of signals and fixed voltages.

For examples, known techniques require a large number of signals and fixed voltages without compensating for a voltage variation in a low power line, and known techniques also lack voltage compensation for a high power voltage line.

As another example, known techniques lack an initialization of an anode of a light emitting element and a sufficient initialization of an auxiliary capacitor.

The present disclosure provides a light emitting display device that can stably display high quality pictures by solving above technical problems.

Accordingly, the present disclosure is directed to a light emitting display device that can attain initialization of an anode of a light emitting element and an auxiliary capacitor and compensation for a voltage variation of a power voltage line while maintaining a low number of signals and fixed voltages.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosure. The advantages of the disclosure will be realized and attained by the structure particularly pointed out in the written description and claims as well as the appended drawings.

To achieve these and other advantages, and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a light emitting display device, includes: a plurality of pixels arranged in a matrix form, each of the plurality of pixels including: a light emitting element in which a light emitting diode including an anode and a cathode; a light emission transistor, one of a source or a drain of the light emission transistor is connected to the anode; a driving transistor, one of a source or a drain of the driving transistor is connected to the other of the source or the drain of the light emission transistor; and an initialization transistor which is configured to connect a gate of the driving transistor, the one of the source or the drain of the driving transistor, and the anode being connected to an initialization voltage line having a fixed voltage at a same time, wherein initialization transistor has a resistance greater than the driving transistor.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. The same or like reference numbers may be used throughout the drawings to refer to the same or like parts.

FIG. 1is a block diagram illustrating an overall configuration of a light emitting display device according to one or more embodiments of the present disclosure.

Referring toFIG. 1, the light emitting display device10may include a control portion11, a data line driving circuit12, a light emission control line and scan line driving circuit13, a power line and initialization voltage line control circuit14, and a plurality of pixels100arranged in a matrix form.

InFIG. 1, a part of the plurality of pixels100is extracted and illustrated in three rows by three columns by way of example. However, in fact, more pixels than those shown inFIG. 1are arranged.

The control portion11may output control signals for controlling the data line driving circuit12, the light emission control line and scan line driving circuit13, and the power line and initialization voltage line control circuit14.

The data line driving circuit12may be a driving circuit that outputs data signals to a plurality of data lines Data based on the control signal from the control portion11.

The light emission control line and scan line driving circuit13may be a driving circuit that outputs signals to, drives, a plurality of light emission control lines EM(n) and scan lines Scan(n) connected thereto based on the control signals from the control portion11.

n is a natural number.

The power line and initialization voltage line control circuit14may be a control circuit that controls voltages of a high voltage power line as a power line of a high power voltage VDD, a low voltage power line as a power line of a low power voltage VSS, and an initialization voltage line as a power line of an initialization voltage Vini.

FIG. 2Ais a view illustrating a pixel circuit of a pixel surrounded by a broken line shown inFIG. 1.

In the pixel100ofFIG. 2A, transistors101,102,105,106,107and108, which are P-type thin film transistors (TFTs), capacitors103and104, and a light emitting element109may be provided.

The transistors applicable to this disclosure are not limited to P-type TFTs, and may use N-type TFTs.

The transistor106may be an initialization TFT.

The transistor107may be a driving TFT.

The initialization TFT may preferably have a resistance greater than the driving TFT. As described later, the initialization TFT may be prevented from being destroyed by increasing a channel length L thereof and shortening a channel width W thereof.

Specifically, the channel length L of the initialization TFT may be made longer than a channel length L of the driving TFT, and the channel width W of the initialization TFT may be made shorter than a channel width W of the driving TFT.

Moreover, inFIG. 2A, it is shown that the data line Data, the initialization voltage line of the initialization voltage Vini, a nthscan line Scan(n), a (n−2)thscan line Scan(n−2), and a nthlight emission control line EM(n), a high voltage power line as a first power line of a power voltage VDD-Δdrop, and a low voltage power line as a second power line of a power voltage VSS.

Moreover, the initialization voltage Vini, the power voltage VDD of the high voltage power line as the first power line, and the power voltage VSS of the low voltage power line as the second power line may be fixed voltages, and the high voltage power line may have a higher voltage than the initialization voltage line, and the low voltage power line may have a lower voltage than the initialization voltage line.

For example, the power voltage VDD of the high voltage power line may be about 3V, the initialization voltage Vini may be about −2V, and the power voltage VSS of the low voltage power line may be about −4V.

Moreover, Δdrop may be a voltage variation value of the high voltage power line.

Moreover, inFIG. 2A, a first node N1, a second node N2, a third node N3and a fourth node N4are shown.

The first node N1may be a node that is connected to one of a source or a drain of the transistor101, one of a source or a drain of the transistor102, one electrode of the capacitor103, and one electrode of the capacitor104.

The second node N2may be a node that is connected to the other electrode of the capacitor104, one of a source or a drain of the transistor105, and a gate of the transistor107.

The third node N3may be a node that is connected to the other of the source or the drain of the transistor105, one of a source or a drain of the transistor107, and one of a source or a drain of the transistor108.

The fourth node N4may be a node that is connected to one of a source or a drain of the transistor106, the other of the source or the drain of the transistor108, and an anode of the light emitting element109.

A gate of the transistor101as a first transistor may be connected to a nthscan line Scan(n), the one of the source or the drain of the transistor101may be connected to the first node N1, and the other of the source or the drain of the transistor101may be connected to the data line Data.

A gate of the transistor102as a second transistor may be connected to a (n−2)thscan line Scan(n−2), the one of the source or the drain of the transistor102may be connected to the first node N1, and the other of the source or the drain of the transistor102may be connected to the initialization voltage line.

The one electrode of the capacitor103as a first capacitor may be connected to the first node N1, and the other electrode of the capacitor103may be connected to the high voltage power line.

The one electrode of the capacitor104as a second capacitor may be connected to the first node N1, and the other electrode of the capacitor104may be connected to the second node N2.

A gate of the transistor105as a third transistor may be connected to the (n−2)thscan line Scan(n−2), the one of the source or the drain of the transistor105may be connected to the second node N2, and the other of the source or the drain of the transistor105may be connected to the third node N3.

A gate of the transistor106as a fourth transistor may be connected to the (n−2)thscan line Scan(n−2), the one of the source or the drain of the transistor106may be connected to the fourth node N4, and the other of the source or the drain of the transistor106may be connected to the initialization voltage line.

The gate of the transistor107as a fifth transistor may be connected to the second node N2, the one of source or the drain of the transistor107may be connected to the third node N3, and the other of the source or the drain of the transistor107may be connected to the high voltage power line.

A gate of the transistor108as a sixth transistor may be connected to the nthlight emission control line EM(n), the one of source or the drain of the transistor108may be connected to the third node N3, and the other of the source or the drain of the transistor108may be connected to the fourth node N4.

The anode of the light emitting element109may be connected to the fourth node N4, and the cathode of the light emitting element109may be connected to the low voltage power line.

An operation of a pixel circuit ofFIG. 2Ais explained below,

FIG. 2Bis a timing chart illustrating an operation of a pixel circuit of a pixel100ofFIG. 2A.

A period t1is a light emission period of a previous frame, a period t2is a reset period of the capacitors and the light emitting element, a period t3is a reset and sensing period of the light emitting element, a period t4is a writing period, a period t5is a waiting period, and a period t6is a light emission period of a current frame.

As shown inFIG. 2B, a voltage of the data line Data may be varied stepwise within a range of V(L) to V(H) depending on an image, and voltages of the (n−2)thscan line Scan(n−2), the nthscan line Scan(n) and the nthlight emission control line EM(n) may each be either V(L) or V(H).

In a case of using P-type TFTs, V(L) is an ON signal and V(H) is an OFF signal.

In this case, magnitude relationship between V(L), V(M), and V(H) in each line is V(L)<V(M)<V(H).

In the period t1, for example, the voltage of the data line Data is V(M), the voltage of the (n−2)thscan line Scan(n−2) is V(H), the voltage of the nthscan line Scan(n) is V(H), and the voltage of the nthlight emission control line EM(n) is V(L).

In the period t2, the voltage of the data line Data is V(L), the voltage of the (n−2)thscan line Scan(n−2) is V(L), the voltage of the nthscan line Scan(n) is V(H), and the voltage of the nthlight emission control line EM(n) is V(L).

By such the voltages applied to the pixel, in the period t2, the transistor101is turned off, and the transistors102,105,106,107and108are turned on.

Accordingly, in the period t2, all of the first node N1, the second node N2, the third node N3, and the fourth node N4are connected to the initialization voltage line to have the initialization voltage Vini.

At this time, the voltage of the capacitor103is V(103)=VDD-Δdrop-Vini.

In the period t3, the voltage of the data line Data is V(H), the voltage of the (n−2)thscan line Scan (n−2) is switched from V(L) to V(H) in a later section of the period t3, the voltage of the nthscan line Scan(n) is V(H), and the voltage of the nthlight emission control line EM(n) is V(H).

By such the voltages applied to the pixel, in the period t3, the transistors101and108are turned off, and the transistors102,105and106are turned on.

Further, the transistor107is also turned on. Regarding the transistor107, the third node N3is charged until the transistor107becomes in a state of Vgs=Vth so that no current flows between the source and drain of the transistor107.

In this regard, Vgs is a gate-to-source voltage based on the source of the transistor107, and Vth is a threshold voltage of the transistor107.

Accordingly, in the period t3, the voltage of the capacitor103is V(103)=VDD−Δdrop-Vini, and the voltage of the capacitor104is V(104)=VDD−Δdrop+Vth−Vini, the voltages of the second node N2and the third node N3are VDD−Δdrop+Vth.

In the period t4, the voltage of the data line Data is switched from V(M) to V(L) in a middle of the period t4, and the voltage of the (n−2)thscan line Scan (n−2) is V(H). The voltage of the nthscan line Scan(n) is switched from V(L) to V(H) in a later section of the period, and the voltage of the nthlight emission control line EM(n) is V(H).

By such the voltages applied to the pixel, in the period t4, the transistors102,105,106,107and108are turned off, and the transistor101is turned on.

In the period t4, the voltage of the first node N1becomes the voltage Vdata of the data line Data, the voltage of the capacitor103becomes V(103)=Vdata−(VDD−Δdrop), and the voltage of the capacitor104is V(104)=VDD−Δdrop Vth−Vini, the voltage of the second node N2is Vdata+V(104)=Vdata+VDD−Δdrop Vth−Vini.

In the period t5, the voltage of the data line Data is switched from V(H) to V(M) in a middle of the period t5, and the voltage of the (n−2)thscan line Scan (n−2) is V(H). The voltage of the nthscan line Scan(n) is V(H), and the voltage of the nthlight emission control line EM(n) is V(H).

By such the voltages applied to the pixel, in the period t5, the transistors101,102,105,106,107and108are turned off.

In the period t6, the voltage of the data line Data is V(L), the voltage of the (n−2)thscan line Scan (n−2) is V(H), the voltage of the nthscan line Scan(n) is V(H), and the voltage of the nthlight emission control line EM(n) is V(L).

By such the voltages applied to the pixel, in the period t6, the transistors101,102,105and106are turned off, and the transistors107and108are turned on.

Accordingly, the accumulated charge flows to the anode of the light emitting element109through the third node N3and the fourth node N4, and the light emitting element109emits a light.

At this time, in the transistor107as a driving transistor, Vgs=Vdata+Vth−Vini.

As such, since the voltage variation of the voltage power line is not included in the gate-to-source voltage of the driving transistor during the light emission, the voltage variation of the power voltage line may be compensated.

Moreover, as described above, the signals used in one or more embodiments are the signal of the data line, the signal of the scan line, and the signal of the emission control line. The fixed voltages used in one or more embodiments are the initialization voltage Vini, the power voltage VDD of the high voltage power line, and the power voltage. VSS of the low voltage power line. As a result, a low number of the signals and a low number of the fixed voltages are maintained.

Therefore, compared with the related art, a light emitting display device capable of performing initialization of the anode of the light emitting element and the auxiliary capacitor and compensating for the voltage variation of the power voltage line while maintaining a low number of the signals and the fixed voltages may be obtained.

Accordingly, a light emitting display device capable of stably displaying with high quality may be obtained.

The transistors applied in one or more embodiments are explained below.

FIG. 3Ais a top view and a cross-sectional view of the transistor as the initialization transistor ofFIG. 2A.

The transistor106of FIG. A may have a coplanar top gate structure.

As shown inFIG. 3A, a semiconductor layer161may be provided on a substrate160, an insulating layer162may be provided while covering the semiconductor layer161. The first electrode layers164A and164B may be provided to be connected to the semiconductor layer161through openings164A and1646provided in the insulating layer162, and a second electrode layer165may be provided on the insulating layer162and at a position overlapping the semiconductor layer161.

Moreover, as shown inFIG. 3A, the transistor106as the initialization transistor may have a shape such that a channel length Lt-i is shorter than a channel width Wt-i.

The substrate160may be an insulating substrate.

As an insulating substrate, a glass substrate may be used by way of example.

The semiconductor layer161may be formed of polycrystalline silicon or oxide semiconductor.

As polycrystalline silicon, low temperature polysilicon (LTPS) formed by laser-crystallizing amorphous silicon may be used by way of example.

An oxide semiconductor may use, for example, but not limited to, indium gallium zinc oxide (IGZO).

In the semiconductor layer161, a channel conducting portion may be provided at a portion in contact with the source and drain, and a contact resistance may be reduced.

The insulating layer162may be a gate insulating layer and may be formed of silicon oxide or silicon nitride.

The insulating layer162may be formed by a chemical vapor deposition (CVD) method.

The openings163A and163B may be formed by, for example, selectively etching parts of the insulating layer162.

The etching may be preferably performed by dry etching.

The first electrode layers164A and164B may form source and drain electrodes.

The first electrode layers164A and164B may be formed by, for example, selectively etching parts of a metal film which is formed through a sputtering method.

The second electrode layer165may form a gate electrode.

The second electrode layer165may be formed by the same method as the first electrode layers164A and164B.

Although not shown in the drawings, an insulating layer may be provided between the first electrode layers164A and164B and the second electrode layer165to ensure insulation between the gate and the source and drain.

FIG. 3Bis a top view of the transistor as the driving transistor ofFIG. 2A.

InFIG. 3B, a number of opening163A and a number of opening163B may each be, but not limited to, plural number.

The channel length Lt-i of the transistor106as the initialization transistor may be longer than a channel length Lt-d of the transistor107as the driving transistor, and the channel width Wt-i of the transistor106as the initialization transistor may be shorter than a channel width Wt-d of the transistor107as the driving transistor.

Moreover, a ratio of the width to the length of the current direction in a channel layer of the transistor106as the initialization transistor may be smaller than that in a channel layer of the transistor107as the driving transistor, that is, Wt-i/Lt-i<Wt-d/Lt-d.

With such the structure, a resistance of the transistor106as the initialization transistor may be greater than a resistance of the transistor107as the driving transistor.

However, the transistor106may be not limited to that shown inFIGS. 3A and 3B.

FIG. 4Ais a top view and a cross-sectional view of a transistor106awhich is a modification of the transistor106ofFIG. 2A.

The transistor ofFIG. 4Amay have an inverted staggered bottom gate structure.

A first electrode layer166may correspond to the second electrode layer165ofFIG. 3Aand may form a gate electrode.

An insulating layer167may correspond to the insulating layer162ofFIG. 3Aand may form a gate insulating layer.

A semiconductor layer168may correspond to the semiconductor layer161ofFIG. 3A.

Second electrode layers169A and169B may correspond to the first electrode layers164A and164B ofFIG. 3Aand may form source and drain electrodes.

As shown inFIG. 4A, the transistor106aas the initialization transistor may have a shape such that a channel length Lb-i is shorter than a channel width Wb-i.

FIG. 4Bis a top view of a transistor107awhich is a modification of the transistor107ofFIG. 2A.

As shown inFIGS. 4A and 4B, the bottom gate structure may also have the same length relationship as the above-described top gate structure.

In other words, the channel length Lb-i of the transistor106aas the initialization transistor may be longer than the channel length Lb-d of the transistor107aas the driving transistor, and the channel width Wb-i of the transistor106aas the initialization transistor may be shorter than the channel width Wb-d of the transistor107aas the driving transistor.

Moreover, a ratio of the width to the length of the current direction in a channel layer of the transistor106aas the initialization transistor may be smaller than that in a channel layer of the transistor107aas the driving transistor, that is, Wb-i J Lb-i<Wb-d Lb-d.

With such the structure, a resistance of the transistor106aas the initialization transistor may be greater than a resistance of the transistor107aas the driving transistor.

As described above, in one or more embodiments, a light emitting display device may be capable of performing initialization of an anode of a light emitting element and an auxiliary capacitor and compensating for voltage variation of a power voltage line while maintaining a low number of signals and fixed voltages, compared with the related art.

FIG. 5is a block diagram illustrating an overall configuration of a light emitting display device according to one or more embodiments of the present disclosure.

Referring toFIG. 5, the light emitting display device20may include a control portion11, a data line driving circuit12, a light emission control line and scan line driving circuit13, a power line and initialization voltage line control circuit14, and a plurality of pixels200arranged in a matrix form.

InFIG. 5, a part of the plurality of pixels200is extracted and illustrated in three rows by three columns by way of example. However, in fact, more pixels than those shown inFIG. 5are arranged.

The control portion11may output control signals for controlling the data line driving circuit12, the light emission control line and scan line driving circuit13, and the power line and initialization voltage line control circuit14.

The data line driving circuit12may be a driving circuit that outputs data signals to a plurality of data lines Data based on the control signal from the control portion11.

The light emission control line and scan line driving circuit13may be a driving circuit that outputs signals to, drives, a plurality of light emission control lines EM(n) and scan lines Scan(n) connected thereto based on the control signals from the control portion11.

n is a natural number.

The power line and initialization voltage line control circuit14may be a control circuit that controls voltages of a high voltage power line as a power line of a high power voltage VDD, a low voltage power line as a power line of a low power voltage VSS, and an initialization voltage line as a power line of an initialization voltage Vini.

FIG. 6Ais a view illustrating a pixel circuit of a pixel surrounded by a broken line shown inFIG. 5.

In the pixel200ofFIG. 6A, transistors201,202,203,206,207,208and209, which are P-type thin film transistors (TFTs), capacitors204and205, and a light emitting element210may be provided.

The transistors applicable to this disclosure are not limited to P-type TFTs, and may use N-type TFTs.

The transistor207may be an initialization TFT.

The transistor208may be a driving TFT.

In one or more embodiments, as described above, the initialization TFT may preferably have a resistance greater than the driving TFT. Specifically, a channel length L of the initialization TFT may be made longer than a channel length L of the driving TFT, and a channel width W of the initialization TFT may be made shorter than a channel width W of the driving TFT, and thus the initialization TFT may be prevented from being destroyed.

Moreover, inFIG. 6A, it is shown that the data line Data, the initialization voltage line of the initialization voltage Vini, a nthscan line Scan(n), a (n−1)thlight emission control line EM(n−1) as a first light emission control line, a nthlight emission control line EM(n) which is a second light emission control line at one row line after the first light emission control line, a high voltage power line as a first power line of a high power voltage VDD−Δdrop, and a low voltage power line as a second power line of a low power voltage VSS.

Moreover, as described above, the initialization voltage Vini, the power voltage VDD of the high voltage power line as the first power line, and the power voltage VSS of the low voltage power line as the second power line may be fixed voltages, and the high voltage power line may have a higher voltage than the initialization voltage line, and the low voltage power line may have a lower voltage than the initialization voltage line.

For example, the power voltage VDD of the high voltage power line may be about 3V, the initialization voltage Vini may be about −2V, and the power voltage VSS of the low voltage power line may be about −4V.

Moreover, Δdrop may be a voltage variation value of the high voltage power line.

Moreover, inFIG. 6A, a first node N1, a second node N2, a third node N3, a fourth node N4and a fifth node N5are shown.

The first node N1may be a node that is connected to one of a source or a drain of the transistor201, one of a source or a drain of the transistor203and one electrode of the capacitor205.

The second node N2may be a node that is connected to the other of the source or the drain of the transistor203, one of a source or a drain of the transistor202and one electrode of the capacitor204.

The third node N3may be a node that is connected to the other electrode of the capacitor204, one of a source or a drain of the transistor206and a gate of the transistor208.

The fourth node N4may be a node that is connected to the other of the source or the drain of the transistor206, one of a source or a drain of the transistor208, and one of a source or a drain of the transistor209.

The fifth node N5may be a node that is connected to the other of the source or the drain of the transistor209, one of a source or a drain of the transistor207, and an anode of the light emitting element210.

A gate of the transistor201as a first transistor may be connected to a nthscan line Scan(n), the one of the source or the drain of the transistor201may be connected to the first node N1, and the other of the source or the drain of the transistor201may be connected to the data line Data.

A gate of the transistor202as a second transistor may be connected to a nthscan line Scan(n), the one of the source or the drain of the transistor202may be connected to the second node N2, and the other of the source or the drain of the transistor202may be connected to the initialization voltage line.

A gate of the transistor203as a third transistor may be connected to a (n−1)thlight emission control line EM(n−1), the one of the source or the drain of the transistor203may be connected to the first node N1, and the other of the source or the drain of the transistor203may be connected to the second node N2.

The one electrode of the capacitor204as a first capacitor may be connected to the second node N2, and the other electrode of the capacitor204may be connected to the third node N3.

The one electrode of the capacitor205as a second capacitor may be connected to the first node N1, and the other electrode of the capacitor205may be connected to the high voltage power line.

A gate of the transistor206as a fourth transistor may be connected to the nthscan line Scan(n), the one of the source or the drain of the transistor206may be connected to the third node N3, and the other of the source or the drain of the transistor206may be connected to the fourth node N4.

A gate of the transistor207as a fifth transistor may be connected to the nthscan line Scan(n), the one of source or the drain of the transistor207may be connected to the fifth node N5, and the other of the source or the drain of the transistor207may be connected to the initialization voltage line.

The gate of the transistor208as a sixth transistor may be connected to the third node N3, the one of the source or the drain of the transistor208may be connected to the fourth node N4, and the other of the source or the drain of the transistor208may be connected to the high voltage power line.

A gate of the transistor209as a seventh transistor may be connected to the nthlight emission control line EM(n), the one of the source or the drain of the transistor209may be connected to the fourth node N4, and the other of the source or the drain of the transistor209may be connected to the fifth node N5.

The anode of the light emitting element210may be connected to the fifth node N5, and the cathode of the light emitting element210may be connected to the low voltage power line.

An operation of a pixel circuit ofFIG. 6Ais explained below,

FIG. 6Bis a timing chart illustrating an operation of a pixel circuit of a pixel200ofFIG. 6A.

A period t1is a light emission period of a previous frame, a period t2is a reset period of the capacitors and the light emitting element, a period t3is a reset and sensing of the light emitting element and a writing period, a period t4is a waiting period, a period t5is a capacitive connection period, and a period t6is a light emission period of a current frame.

As shown inFIG. 6B, a voltage of the data line Data may be varied stepwise within a range of V(L) to V(H) depending on an image, and voltages of the nthscan line Scan(n), the (n−1)thlight emission control line EM(n−1) and the nthlight emission control line EM(n) may each be either V(L) or V(H).

In a case of using P-type TFTs, V(L) is an ON signal and V(H) is an OFF signal.

In this case, magnitude relationship between V(L), V(M), and V(H) in each line is V(L)<V(M)<V(H).

In the period t1, for example, the voltage of the data line Data is V(M), the voltage of the nthscan line Scan(n) is V(H), the voltage of the (n−1)hlight emission control line EM(n−1) is V(L), and the voltage of the nthlight emission control line EM(n) is V(L).

In the period t2, the voltage of the data line Data is V(L), the voltage of the nthscan line Scan(n) is V(L), the voltage of the (n−1)thlight emission control line EM(n−1) is V(H), and the voltage of the nthlight emission control line EM(n) is V(L).

By such the voltages applied to the pixel, in the period t2, the transistor203is turned off, and the transistors201,202,206,207,208and209are turned on.

Accordingly, in the period t2, the second node N2, the third node N3, the fourth node N4and the fifth node N5are connected to the initialization voltage line to have the initialization voltage Vini.

In the period t3, the voltage of the data line Data is switched from V(H) to V(M) in a middle of the period t3, the voltage of the nthscan line Scan (n) is V(L), the voltage of the (n−1)thlight emission control line EM(n−1) is V(H), and the voltage of the nthlight emission control line EM(n) is V(H).

By such the voltages applied to the pixel, in the period t3, the transistor209is turned off, and the transistors201,202,203,206and207are turned on.

Further, the transistor208is also turned on. Regarding the transistor208, the fourth node N4is charged until the transistor208becomes in a state of Vgs=Vth so that no current flows between the source and drain of the transistor208.

In this regard, Vgs is a gate-to-source voltage based on the source of the transistor208, and Vth is a threshold voltage of the transistor208.

Accordingly, in the period t3, the voltage of the first node N7is the voltage Vdata of the data line Data, the voltage of the fourth node N4is VDD−Δdrop+Vth, the voltage of the capacitor204is V(204)=VDD−Δdrop+Vth−Vini, and the voltage of the capacitor205is V(205) Vdata−(VDD−Δdrop).

In the period t4, the voltage of the data line Data is switched from V(L) to V(H) in a middle of the period t4, and the voltage of the nthscan line Scan (n) is V(H). The voltage of the (n−1)thlight emission control line EM(n−1) is V(H), and the voltage of the nthlight emission control line EM(n) is V(H).

By such the voltages applied to the pixel, in the period t4, the transistors201,202,203,206,207,208and209are turned off.

In the period t4, the voltage of the capacitor204is V(204)=VDD−Δdrop+Vth−Vini, and the voltage of the capacitor205is V(205)=Vdata (VDD Δdrop).

In the period t5, the voltage of the data line Data is V(M), and the voltage of the nthscan line Scan (n) is V(H). The voltage of the (n−1)thlight emission control line EM(n−1) is V(L), and the voltage of the nthlight emission control line EM(n) is V(H).

By such the voltages applied to the pixel, in the period t5, the transistors201,202,206,207,208and209are turned off, and the transistor203is turned on.

Accordingly, in the period t5, the first node N1and the second node N2are connected to each other so that one electrode of the capacitor204and one electrode of the capacitor205are connected to each other.

In the period t6, the voltage of the data line Data is V(L), the voltage of the nthscan line Scan (n) is V(H), the voltage of the (n−1)thlight emission control line EM(n−1) is V(L), and the voltage of the nthlight emission control line EM(n) is V(L).

By such the voltages applied to the pixel, in the period t6, the transistors201,202,206,207and208are turned off, and the transistors203and209are turned on.

Accordingly, the accumulated charge flows to the anode of the light emitting element210through the fourth node N4and the fifth node N5, and the light emitting element210emits a light.

At this time, in the transistor208as a driving transistor, Vgs=Vdata+Vth−Vini.

As such, since the voltage variation of the voltage power line is not included in the gate-to-source voltage of the driving transistor during the light emission, the voltage variation of the power voltage line may be compensated.

Moreover, as described above, the signals used in one or more embodiments are the signal of the data line, the signal of the scan line, and the signal of the emission control line. The fixed voltages used in one or more embodiments are the initialization voltage Vini, the power voltage VDD of the high voltage power line, and the power voltage VSS of the low voltage power line. As a result, a low number of the signals and a low number of the fixed voltages are maintained.

Therefore, compared with the related art, a light emitting display device capable of performing initialization of the anode of the light emitting element and the auxiliary capacitor and compensating for the voltage variation of the power voltage line while maintaining a low number of the signals and the fixed voltages may be obtained.

Accordingly, a light emitting display device capable of stably displaying with high quality may be obtained.

As described above, in one or more embodiments, a light emitting display device may be capable of performing initialization of an anode of a light emitting element and an auxiliary capacitor and compensating for voltage variation of a power voltage line while maintaining a low number of signals and fixed voltages, compared with the related art.

In the overall configuration of the light emitting display device according to one or more embodiments, pixels300may replace the pixels200inFIG. 5of one or more embodiments.

FIG. 7Ais a view illustrating a pixel circuit of a pixel of a light emitting display device according to one or more embodiments of the present disclosure.

In the pixel200ofFIG. 7A, transistors301,302,305,306,307,308and309, which are P-type thin film transistors (TFTs), capacitors303and304, and a light emitting element310may be provided.

The transistors applicable to this disclosure are not limited to P-type TFTs, and may use N-type TFTs.

The transistor307may be an initialization TFT.

The transistor308may be a driving TFT.

In one or more embodiments, as described above, the initialization TFT may preferably have a resistance greater than the driving TFT. Specifically, a channel length L of the initialization TFT may be made longer than a channel length L of the driving TFT, and a channel width W of the initialization TFT may be made shorter than a channel width W of the driving TFT, and thus the initialization TFT may be prevented from being destroyed.

Moreover, inFIG. 7A, it is shown that the data line Data, the initialization voltage line of the initialization voltage Vini, a nthscan line Scan(n), a (n−1)thlight emission control line EM(n−1) as a first light emission control line, a nthlight emission control line EM(n) as a second light emission control line, a high voltage power line as a first power line of a high power voltage VDD−Δdrop, and a low voltage power line as a second power line of a low power voltage VSS.

Moreover, as described above, the initialization voltage Vini, the power voltage VDD of the high voltage power line as the first power line, and the power voltage VSS of the low voltage power line as the second power line may be fixed voltages, and the high voltage power line may have a higher voltage than the initialization voltage line, and the low voltage power line may have a lower voltage than the initialization voltage line.

For example, the power voltage VDD of the high voltage power line may be about 3V, the initialization voltage Vini may be about −2V, and the power voltage VSS of the low voltage power line may be about −4V.

Moreover, Δdrop may be a voltage variation value of the high voltage power line.

Moreover, inFIG. 7A, a first node N1, a second node N2, a third node N3, a fourth node N4and a fifth node N5are shown.

The first node N1may be a node that is connected to one of a source or a drain of the transistor301, one of a source or a drain of the transistor302and one electrode of the capacitor303.

The second node N2may be a node that is connected to the other electrode of the capacitor303, one electrode of the capacitor304, and one of a source or a drain of the transistor305.

The third node N3may be a node that is connected to the other electrode of the capacitor304, one of a source or a drain of the transistor306and a gate of the transistor308.

The fourth node N4may be a node that is connected to the other of the source or the drain of the transistor306, one of a source or a drain of the transistor308, and one of a source or a drain of the transistor309.

The fifth node N5may be a node that is connected to one of a source or a drain of the transistor307, the other of the source or the drain of the transistor309, and an anode of the light emitting element310.

A gate of the transistor301as a first transistor may be connected to nthscan line Scan(n), the one of the source or the drain of the transistor301may be connected to the first node N1, and the other of the source or the drain of the transistor301may be connected to the data line Data.

A gate of the transistor302as a second transistor may be connected to a (n−1)thlight emission control line EM(n−1), the one of the source or the drain of the transistor302may be connected to the first node N1, and the other of the source or the drain of the transistor302may be connected to the initialization voltage line.

The one electrode of the capacitor303as a first capacitor may be connected to the first node N1, and the other electrode of the capacitor303may be connected to the second node N2.

The one electrode of the capacitor304as a second capacitor may be connected to the second node N2, and the other electrode of the capacitor304may be connected to the third node N3.

A gate of the transistor305as a third transistor may be connected to a nthscan line Scan(n), the one of the source or the drain of the transistor305may be connected to the second node. N2, and the other of the source or the drain of the transistor305may be connected to the high voltage power line.

A gate of the transistor306as a fourth transistor may be connected to the nthscan line Scan(n), the one of the source or the drain of the transistor306may be connected to the third node N3, and the other of the source or the drain of the transistor306may be connected to the fourth node N4.

A gate of the transistor307as a fifth transistor may be connected to the nthscan line Scan(n), the one of source or the drain of the transistor307may be connected to the fifth node N5, and the other of the source or the drain of the transistor207may be connected to the initialization voltage line.

The gate of the transistor308as a sixth transistor may be connected to the third node N3, the one of source or the drain of the transistor308may be connected to the fourth node N4, and the other of the source or the drain of the transistor308may be connected to the high voltage power line.

A gate of the transistor309as a seventh transistor may be connected to the nthlight emission control line EM(n), the one of the source or the drain of the transistor309may be connected to the fourth node N4, and the other of the source or the drain of the transistor309may be connected to the fifth node N5.

The anode of the light emitting element310may be connected to the fifth node N5, and the cathode of the light emitting element310may be connected to the low voltage power line.

An operation of a pixel circuit ofFIG. 7Ais explained below,

FIG. 7Bis a timing chart illustrating an operation of a pixel circuit of a pixel300ofFIG. 7A.

A period t1is a light emission period of a previous frame, a period t2is a reset period of the capacitors and the light emitting element, a period t3is a reset and sensing of the light emitting element and a writing period, a period t4is a waiting period, a period t5is a capacitive connection period, and a period t6is a light emission period of a current frame.

As shown inFIG. 7B, a voltage of the data line Data may be varied stepwise within a range of V(L) to V(H) depending on an image, and voltages of the nthscan line Scan(n), the (n−1)thlight emission control line EM(n−1) and the nthlight emission control line. EM(n) may each be either V(L) or V(H).

In a case of using P-type TFTs, V(L) is an ON signal and V(H) is an OFF signal.

In this case, magnitude relationship between V(L), V(M), and V(H) in each line is V(L)<V(M)<V(H).

In the period t1, for example, the voltage of the data line Data is V(M), the voltage of the nthscan line Scan(n) is V(H), the voltage of the (n−1)thlight emission control line EM(n−1) is V(L), and the voltage of the nthlight emission control line EM(n) is V(L).

In the period t2, the voltage of the data line Data is V(L), the voltage of the nthscan line Scan(n) is V(L), the voltage of the (n−1)thlight emission control line EM(n−1) is V(H), and the voltage of the nthlight emission control line EM(n) is V(L).

By such the voltages applied to the pixel, in the period t2, the transistor302is turned off, and the transistors301,305,306,307,308and309are turned on.

Accordingly, in the period t2, the third node N3, the fourth node N4and the fifth node N5are connected to the initialization voltage line to have the initialization voltage Vini.

In the period t3, the voltage of the data line Data is switched from V(H) to V(M) in a middle of the period t3, the voltage of the nthscan line Scan (n) is V(L), the voltage of the (n−1)thlight emission control line EM(n−1) is V(H), and the voltage of the nthlight emission control line EM(n) is V(H).

By such the voltages applied to the pixel, in the period t3, the transistor302and309are turned off, and the transistors301,305,306and307are turned on.

Further, the transistor308is also turned on. Regarding the transistor308, the fourth node N4is charged until the transistor308becomes in a state of Vgs=Vth so that no current flows between the source and drain of the transistor308.

In this regard, Vgs is a gate-to-source voltage based on the source of the transistor308, and Vth is a threshold voltage of the transistor308.

Accordingly, in the period t3, the voltage of the first node N1is the voltage Vdata of the data line Data, the voltage of the fourth node N4is VDD−Δdrop Vth, the voltage of the capacitor303is V(303)=(VDD−Δdrop)−Vdata, and the voltage of the capacitor304is V(304)=Vth.

In the period t4, the voltage of the data line Data is switched from V(L) to V(H) in a middle of the period t4, and the voltage of the nthscan line Scan (n) is V(H). The voltage of the (n−1)thlight emission control line EM(n−1) is V(H), and the voltage of the nthlight emission control line EM(n) is V(H).

By such the voltages applied to the pixel, in the period t4, the transistors301,302,305,306,307,308and309are turned off.

In the period t4, the voltage of the capacitor303is V(303)=(VDD−Δdrop)−Vdata, and the voltage of the capacitor304is V(304)=Vth.

In the period t5, the voltage of the data line Data is V(M), and the voltage of the nthscan line Scan (n) is V(H). The voltage of the (n−1)thlight emission control line EM(n−1) is V(L), and the voltage of the nthlight emission control line EM(n) is V(H).

By such the voltages applied to the pixel, in the period t5, the transistors301,305,306,307,308and309are turned off, and the transistor302is turned on.

In the period t6, the voltage of the data line Data is V(L), the voltage of the nthscan line Scan (n) is V(H), the voltage of the (n−1)thlight emission control line EM(n−1) is V(L), and the voltage of the nthlight emission control line EM(n) is V(L).

By such the voltages applied to the pixel, in the period t6, the transistors301,305,306,307and308are turned off, and the transistors302and309are turned on.

Accordingly, the accumulated charge flows to the anode of the light emitting element310through the fourth node N4and the fifth node N5, and the light emitting element310emits a light.

At this time, in the transistor308as a driving transistor, Vgs=Vdata+Vth−Vini.

As such, since the voltage variation of the voltage power line is not included in the gate-to-source voltage of the driving transistor during the light emission, the voltage variation of the power voltage line may be compensated.

Moreover, as described above, the signals used in one or more embodiments are the signal of the data line, the signal of the scan line, and the signal of the emission control line. The fixed voltages used in one or more embodiments are the initialization voltage Vini, the power voltage VDD of the high voltage power line, and the power voltage VSS of the low voltage power line. As a result, a low number of the signals and a low number of the fixed voltages are maintained.

Therefore, compared with the related art, a light emitting display device capable of performing initialization of the anode of the light emitting element and the auxiliary capacitor and compensating for the voltage variation of the power voltage line while maintaining a low number of the signals and the fixed voltages may be obtained.

Accordingly, a light emitting display device capable of stably displaying with high quality may be obtained.

It will be apparent to those skilled in the art that various modifications and variations can be made in a display device of the present disclosure without departing from the sprit or scope of the disclosure.