Memory device with write pulse trimming

A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

BACKGROUND

Memory devices are used to store information in semiconductor devices and systems. A nonvolatile memory device is capable of retaining data even after power is cut off. Examples of nonvolatile memory devices include flash memory, ferroelectric random access memories (FRAMs), magnetic random access memories (MRAMs), resistive random access memories (RRAMs), and phase-change memories (PCMs). MRAM, RRAM, FRAM, and PCM are sometimes referred to as emerging memory devices.

DETAILED DESCRIPTION

The fabrication processes for emerging memory devices are still not mature. Write error rates (WER) of emerging memory devices such as ferroelectric random access memories (FRAMs), magnetic random access memories (MRAMs), resistive random access memories (RRAMs), and phase-change memories (PCMs) are temperature dependent. Specifically, the difficulty of programming during write operation is affected by the temperature of the emerging memory device. When the temperature is relatively high, it is relatively easy to program data into memory cells of the emerging memory device, thus relatively fewer write pulses (i.e., lower write pulse width) are needed; when the temperature is relatively low, it is relatively hard to program data into memory cells of the emerging memory device, thus relatively more write pulses (i.e., higher write pulse width) are needed. An example normal temperature range of a memory device is between 25° C. and 85° C. However, sometimes memory devices may operate under extreme temperature conditions such as down to −25° C. or up to 125° C. In one example, the number of write pulses needed at 125° C. are about 6 times of the write pulses needed at −50° C. As such, fixed write pulses cannot fit all write operations in all conditions. In other words, when a fixed programming condition is set, it may merely be suitable or optimized for write operations at a specified temperature, and the write error rate may increase when the actual temperature deviates from the specified temperature.

In accordance with some aspects of the present disclosure, the write pulse width of the memory device is adjusted (i.e., write pulse trimming) based on the temperature of the memory cell array or the write error rate of the memory device. The adjustment makes the memory device operate under a suitable condition to decrease the write error rate. Specifically, the write pulse width of the memory device is adjusted based on the temperature of the memory as well as a temperature dependent table. Alternatively, the write pulse width is adjusted based on the write error rate of the memory device.

FIG.1is a block diagram illustrating an example memory device100incorporating write pulse trimming in accordance with some embodiments. In the example shown, the example memory device100includes, among other things, a memory cell array102, a controller106, a voltage generating circuit116, a row decoder118, a word line control circuit120, a column decoder122, a bit line control circuit124, a read circuit126, a write circuit130, an input/output (I/O) circuit132, optionally a temperature sensor134, and optionally an error monitor136. In one example, the memory device100includes the temperature sensor134. In another example, the memory device100includes the error monitor136. In yet another example, the memory device100includes both the temperature sensor134and the error monitor136.

The memory cell array102includes multiple memory cells104arranged in rows and columns. The memory cells104are emerging memory cells such as MRAM cells, RRAM cells, FRAM cells, and PCM cells, though other types of memory cells may also be employed.

The controller106includes, among other things, a control circuit108, a command-address latch circuit110, a pulse generator circuit112, and a storage114. The command-address latch circuit110temporarily holds commands and addresses received by the memory device100as inputs. The command-address latch circuit110transmits the commands to the control circuit108. The command-address latch circuit110transmits the addresses to the row decoder118and the column decoder122.

The row decoder118decodes a row address included in the address and sends the row address to the word line control circuit120. The word line control circuit120selects a word line (corresponding to a specific row) of the memory cell array102based on the decoded row address. Specifically, the memory cells104in that specific row are accessed.

On the other hand, the column decoder120decodes a column address included in the address and sends the column address to the bit line control circuit124. The bit line control circuit124selects a bit line (corresponding to a specific column) of the memory cell array102based on the decoded column address. Specifically, the memory cell104in that specific column, among all the memory cells104in that specific row, is accessed and data can be written to or read from the memory cell104in that specific row and specific column.

During a write operation, the write circuit130supplies various voltages and currents for data writing to the memory cell104selected based on the decoded row address and the decoded column address. The write pulses needed (i.e., the write pulse width) for the write operation is generated by the pulse generator circuit112. In the illustrated example ofFIG.1, the pulse generator circuit112is located in the controller106, though the pulse generator circuit112may be a separate component outside the controller106. The write circuit130includes, among other things, a write driver not shown.

During a read operation, the read circuit126supplies various voltages and currents for data reading from the memory cell104selected based on the decoded row address and the decoded column address. The read circuit126includes, among other things, a read driver not shown and a sense amplifier128. The sense amplifier128senses a relatively small difference between the voltages of two complementary bit lines (i.e., BL and BLB) and amplifies the difference at the output of the sense amplifier128.

The I/O circuit132is coupled to both the write circuit130and the read circuit126. During the write operation, the I/O circuit132temporarily holds data to be written and transmits the data to be written to the write circuit130. On the other hand, during the read operation, the I/O temporarily holds data read by the read circuit126.

The voltage generation circuit116generates various voltages used for the operation of the memory device100by using power supply voltages outside the memory device100. The various voltages generated by the voltage generation circuit116may be applied to components of the memory device100such as the controller110, the row decoder118, the word line control circuit120, the column decoder122, the bit line control circuit124, the read circuit126, the write circuit130, the I/O circuit132, and optionally the temperature sensor134and/or the error monitor136.

The control circuit108receives the commands from the command-address latch circuit110. In response to the commands, the control circuit108controls operations of components of the memory device100such as the controller110, the row decoder118, the word line control circuit120, the column decoder122, the bit line control circuit124, the read circuit126, the write circuit130, the I/O circuit132, the pulse generator circuit112, the storage114, the command-address latch circuit110, the storage, the voltage generating circuit116, and optionally the temperature sensor134and/or the error monitor136.

The temperature sensor134measures the temperature of the memory cell array102. In one example, the temperature sensor134is an analog temperature transducer that produces an output current proportional to absolute temperature of the temperature sensor134with a wide temperature range from −55° C. to 150° C. In another example, the temperature sensor134is a digital temperature that compares a voltage generated by an on-board temperature sensor to an internal voltage reference and digitized by an analog-to-digital converter (ADC). It should be noted that other types of temperature sensors may also be employed. The temperature sensor134may be a separate component as shown inFIG.1. The temperature sensor134may also be embedded in the controller106.

The error monitor136monitors the write error rate (WER) of the memory device100. Write error rate is the number of write bit errors per unit time. Within a certain interval, the more write bit errors there are, the higher the write error rate is. During the write operation, some bits are not written as intended after the first write operation, and those bits are called unfinished bits. Due to unfinished bits, the second write operation is needed. If there is still any bit unfinished after the second write operation, the third write operation is needed. This process keeps going until there are no unfinished bits. The error monitor136is coupled to the I/O circuit132to monitor the write error rate of the memory device100.

The error monitor136may employ various methods of write error rate detection such as error correction code (ECC), though other methods may also be employed. ECC schemes are used to detect and correct bit errors stored in a memory. ECC encodes data by generating ECC check bits, e.g., redundancy bits or parity bits, which are stored along with the data in a memory device. Data bits and check (e.g., parity) bits together form a codeword. For example, an ECC that generates 8 parity bits for 64 bits of data can usually detect two bit errors and correct one bit error in the 64 bits of data, known as a DED/SEC code, meaning double-error detecting (DED) and single-error correcting (SEC). In another example, a DED/DEC scheme, meaning double-error detecting (DED) and double-error correcting (DEC), may be employed. In yet another example, a SED/SEC scheme, meaning single-error detecting (SED) and single-error correcting (SEC), may be employed. In one embodiment, the error monitor136may be an ECC circuit utilizing an ECC scheme. The ECC circuit can detect errors and correct them during the operation of the memory device. Specifically, the ECC circuit may include, among other things, an ECC encoder and an ECC decoder. The ECC encoder is configured to generate parity bits and form a codeword, while the ECC decoder is configured to decode the codeword and provide corrected data. The ECC circuit may therefore determine the write error rate by taking advantage of the error detection function of the ECC circuit.

The storage114stores among other things, temperature dependent table(s) and/or a threshold write error rate which are described below in detail with reference toFIG.2andFIG.4, respectively. In one example, the storage114is a read-only memory (ROM). In another example, the storage114is a random-access memory (RAM). It should be noted that other types of storage may also be employed.

FIG.2is a flowchart illustrating a method of write pulse trimming in accordance with some embodiments.FIG.3Ais a diagram illustrating an example temperature dependent table used in the method ofFIG.2in accordance with some embodiments.FIG.3Bis a diagram illustrating another example temperature dependent table used in the method ofFIG.2in accordance with some embodiments.FIG.3Cis a flow chart illustrating a method of generating a temperature dependent table in accordance with some embodiments. In general, the write pulse width of the memory device100is adjusted based on the temperature of the memory cell array102so that the write operation is performed under a suitable condition to decrease the write error rate.

As shown inFIG.2, the method begins at step202, where a temperature of the memory cell array102is detected by the temperature sensor134. Since the temperature sensor134is coupled to the controller106, the controller can make decisions based on the temperature of the memory cell array102. At step204, a target write pulse width is determined based on the detected temperature of the memory device, as explained below with reference toFIGS.3A-3C. In general, the target write pulse width is determined by referring to a temperature dependent table as shown inFIG.3AorFIG.3Bbelow which serves as a look-up table. Various temperatures of the memory device correspond to various target write pulse widths.

In the illustrated example inFIG.3A, an example temperature dependent table302aserves as a look-up table. The temperature dependent table302aprovides the target write pulse width306according to the temperature304of the memory cell array102. Specifically, when the temperature is 125° C., the target write pulse width is 1× (one unit); when the temperature is 105° C., the target write pulse width is 1.2×; when the temperature is 85° C., the target write pulse width is 1.5×; when the temperature is 60° C., the target write pulse width is 2×; when the temperature is 45° C., the target write pulse width is 2.2×; when the temperature is 25° C., the target write pulse width is 2.7×; when the temperature is 0° C., the target write pulse width is 3.5×; and when the temperature is −25° C., the target write pulse width is 5×. In other words, the lower the temperature304is, the larger the target write pulse width306becomes.

In the illustrated example inFIG.3B, another example temperature dependent table302bserves as another look-up table. The temperature dependent table302balso provides the target write pulse width306according to the temperature304of the memory cell array102. Specifically, when the temperature is 125° C., the target write pulse width is 1× (one unit); when the temperature is 105° C., the target write pulse width is 1×; when the temperature is 85° C., the target write pulse width is 2×; when the temperature is 60° C., the target write pulse width is 2×; when the temperature is 45° C., the target write pulse width is 3×; when the temperature is 25° C., the target write pulse width is 3×; when the temperature is 0° C., the target write pulse width is 5×; and when the temperature is −25° C., the target write pulse width is 5×. In other words, the lower the temperature304is, the larger the target write pulse width306becomes. Different from the temperature dependent table302a, the temperature dependent table302bhas a lower resolution. For example, for both 25° C. and 45° C., the target write pulse width is 3× based on the temperature dependent table302b. It should be noted that temperature dependent tables with higher resolutions or lower resolutions than those of the temperature dependent tables302aand203bmay be employed as needed.

FIG.3Cis a flow chart illustrating a method300of generating a temperature dependent table in accordance with some embodiments. In general, a temperature dependent table (e.g., the temperature dependent table302aor302bshown inFIG.3AorFIG.3B, respectively) is generated during initial testing procedures before the shipment of the memory device. The method300starts at step332where a memory device (e.g., the memory device100shown inFIG.1) and a testing system are provided. In one embodiment, the testing system is a memory tester which is used to test a memory device during initial testing procedures before the shipment. The memory tester may test whether the memory device operates normally. To test the memory device, the memory tester may transmit various signals to the memory device and may control an operation of the memory device. Various signals may include for example address signals, data, command signals, and clock signals. In some examples, the memory tester may transmit command signals, address signals, and data for the purpose of storing data in the memory device or reading data stored in the memory device. In some examples, the memory tester may store write data at a particular address of the memory device and may read data from the address at which the write data are stored. The memory tester may then compare the write data and the read data to determine whether the write operation is failed. Based on the results, the memory tester may calculate the write error rate of the memory device.

The method300then proceeds to step334. At step334, the memory tester sweeps the temperature, the write pulse width, and the voltage of the memory device. As such, various combinations of conditions (e.g., at temperature T1, at voltage V1, and with write pulse width WPW1) are provided. The method300then proceeds to step336. At step336, write error rates under different conditions are calculated. The write error rates may be calculated by counting write bit errors and dividing the write bit errors by a unit time. The method300then proceeds to step338. At step338, the temperate dependent table is generated based on the write error rates calculated under different conditions. Specifically, at a specific temperature Ti, the minimum write pulse width WPWi that can achieve an acceptable write error rate (e.g., below a threshold write error rate) is determined. In other words, at the specific temperature Ti, if the write pulse width is lower than the minimum write pulse width WPWi, the write error rate will be higher than the threshold write error rate. As such, the minimum write pulse width WPWi is the target write pulse width306corresponding to the specific temperature Ti. Since the memory tester sweeps the temperature of the memory device, the temperature dependent table that covers a temperature range (e.g., from −25° C. to 125° C.) is generated. The method300then proceeds to step340. At step340, the temperature dependent table is stored in the storage (e.g., the storage114shown inFIG.1) of the memory device. As such, the temperature dependent table may be referred to after the shipment of the memory device.

The temperature dependent table302aand/or the temperature dependent table302bare stored in the storage114of the controller106. It should be noted that the temperature dependent table302aand/or the temperature dependent table302bare examples, and other temperature dependent tables may be employed. Different temperature dependent tables may be employed for different applications such as mobile phones, smart watches, tablets, and digital cameras. As explained above, different applications may have different acceptable write error rates. As such, different temperature dependent tables may be employed due to different acceptable write error rates. In one example, temperature dependent tables may be configurable after shipment of the memory device. The manufacturer of the memory device provides different temperature dependent tables, corresponding to different applications, generated during the initial testing procedures. The user may configure/choose one suitable temperature dependent table for a specific application after the shipment as needed.

Referring back toFIG.2, data are written to the memory device using the target write pulse width at step206. The pulse generator circuit112of the controller106generates a write pulse with the target write pulse width306, which is in turn used by the write circuit130in the write operation. Then the method loops back to step202again, in one example after a certain interval, to detect the temperature304. In one example, the interval is configurable. In some applications (e.g., when used in industrial applications), the interval is relatively short such that the write pulse width may be adjusted relatively more frequently. On the other hand (e.g., when used in consumer electronics such as mobile phones, smart watches), the interval is relatively long such that the write pulse width may be adjusted relatively less frequently. The user may have the flexibility to configure the interval after shipment of the memory device. As such, the write pulse width is adjusted based on the temperature304of the memory cell array102as well as the temperature dependent table302aor302b. The adjustment makes the memory device100operate under a suitable condition to decrease the write error rate.

FIG.4is a flowchart illustrating another method of write pulse trimming in accordance with some embodiments. In general, the write pulse width of the memory device100is adjusted dynamically based on the write error rate of the memory device100so that the write operation is performed under a suitable condition to decrease the write error rate.

As shown inFIG.4, the method begins at step402, where a write error rate of the memory device100is detected by the error monitor136. Since the error monitor136is coupled to the controller106, the controller can make decisions based on the write error rate of the memory device100. At step404, the controller106compares the detected write error rate to a threshold write error rate. The threshold write error rate is stored in the storage114of the controller106. In one example, the threshold write error rate is associated with the number of data bits written in the second write operation. During the write operation, some bits are not written as intended after the first write operation, and those bits are called unfinished bits. Due to unfinished bits, the second write operation is needed. If there is still any bit unfinished after the second write operation, the third write operation is needed. This process keeps going until there are no unfinished bits. Thus, the number of data bits written in the second write operation can be used as a benchmark of write error rate. In other words, if the write error number is higher than the number of data bits written in the second write operation, the write error number is typically regarded as relatively high. Other threshold write error rates may be employed for different applications such as mobile phones, smart watches, tablets, and digital cameras. In one example, the threshold write error rate may be configurable. Depending on the result of step404, the method proceeds to either step406or step408.

When the controller106determines that the write error rate is higher than the threshold write error rate, the write pulse width is increased at step406. When the controller106determines that the write error rate is not higher than the threshold write error rate, the write pulse width is decreased at step408. The write pulse width is increased or decreased by the pulse generator circuit112of the controller106. In one example, the write pulse width is increased or decreased by an amount proportionate to the difference between the write error rate and the threshold write error rate. In other words, the more the write error rate deviates from the threshold write error rate, the larger the increase amount or decrease amount is. Specifically, the controller106determines the difference between the write error rate and the threshold write error rate. Then the pulse generator circuit112increases or decreases the write pulse width based on the difference determined by the controller106. The larger the determined difference is, the larger the increase step or decrease step is. As such, when the deviation of the write error rate from the threshold write error rate is large, the step of increase or decrease in the write pulse width is relatively large (i.e., like a coarse adjustment). As the deviation of the write error rate becomes smaller, the increase step or decrease step of the write pulse width becomes relatively small (i.e., like a fine adjustment). As such, the write pulse width adjustment is relatively quick while avoiding over-adjusting in the meantime due to large increase step or decrease step. In another example, the write pulse width is increased or decreased by a fixed amount. In other words, the fixed amount is predetermined. The fixed amount may be configured based on different applications such as mobile phones, smart watches, tablets, and digital cameras. Specifically, the pulse generator circuit112increases or decreases the write pulse width, regardless of the difference between the write error rate and the threshold write error rate. A predetermined increase step or decrease step may achieve simplicity of the relevant circuits.

After either step406or step408, the method loops back to step402again, in one example after a certain interval, to detect the write error rate of the memory device100again. In one example, the interval is configurable. In some applications (e.g., when used in industrial applications), the interval is relatively short such that the write pulse width may be adjusted relatively more frequently. On the other hand (e.g., when used in consumer electronics such as mobile phones, smart watches), the interval is relatively long such that the write pulse width may be adjusted relatively less frequently. The user may have the flexibility to configure the interval after shipment of the memory device. As such, the write pulse width is adjusted based on the write error rate of the memory device100. The adjustment makes the memory device100operate under a suitable condition to decrease the write error rate.

It should be noted that the method ofFIG.2and the method ofFIG.4may be combined. In other words, a memory device100may employ both the method ofFIG.2and the method ofFIG.4. In that case, the memory device100includes both a temperature sensor134and an error monitor136.

In accordance with some disclosed embodiments, a method is provided. The method includes: detecting a temperature of a memory device; determining a target write pulse width based on the detected temperature of the memory device; and writing data to the memory device using the target write pulse width.

In accordance with further disclosed embodiments, a method includes: detecting a write error rate of a memory device; comparing the detected write error rate to a threshold write error rate; if the detected write error rate is higher than the threshold write error rate, then increasing a write pulse width; and if the detected write error rate is not higher than the threshold write error rate, then decreasing the write pulse width.

In accordance with further disclosed embodiments, a memory device is provided. The memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.