Processing apparatus and integrated circuit to prevent illicit access and reverse engineering

A processing apparatus including an internal circuit having a CPU and internal devices and an external circuit including external devices provided externally of the internal circuit, and the like, and is aimed to prevent illicit access and reverse engineering. The internal circuit including a CPU, internal devices and a bus line connecting the CPU to the internal devices and extending externally, and the external circuit including external devices provided externally of an externally extending portion of the bus line. The internal circuit further including a ciphering section 120 provided at an entrance to an external side and ciphering addresses and data on the bus line by ciphering patterns according to a plurality of regions divided from an address space allotted to the entire external devices.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a processing apparatus comprising an internal circuit having a CPU and internal devices, and an external circuit including external devices provided externally of the internal circuit, and to an integrated circuit having a CPU and an internal device mounted thereon and capable of providing an external devices externally of the integrated circuit.

2. Description of the Related Art

With the recent development of LSI, a CPU executing programs, a memory storing the programs executed by the CPU and various other devices have been able to be integrated on one chip, which contributes greatly to making an apparatus small in size, cost reduction and the like. To manufacture such LSI, it suffices to mount a memory storing programs on a LSI chip if a system executes the same programs irrespectively of users and does not need to change programs after completion. However, if it is necessary to execute different programs according to users or to change a program while the program is in use, it is desirable to constitute LSI so that an external memory can be further provided externally of the LSI having the above constitution and to store programs which may be possibly changed while in use or programs which differ according to users in the external memory.

Meanwhile, in case of a system capable of adding such an external memory externally of the LSI, however, there is a probability that the content of the external memory is illicitly rewritten or the external memory is replaced by a memory storing an illicit program and having the same specification as that of the external memory, with the result that important programs or data stored in the internal memory are illicitly accessed and the contents of the programs or data are illicitly interpreted. The following is one example of this case.

Recently, IC cards and magnetic cards each having a cash value or a point value corresponding to a cash as data is spreading increasingly. Following this, it is of urgent necessity to ensure data security so as to prevent the fabrication or falsification of cards. To this end, methods of preventing the reverse engineering of an apparatus were attempted in the past. Despite these attempts, it is the present situation that illicit ROMs and the like are created and apparatuses are incessantly abused against developers' will.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above circumstances. It is, therefore, an object of the present invention to provide a processing apparatus and an integrated circuit intended to prevent illicit access and reverse engineering.

The first processing apparatus of the present invention to attain the above object is characterized by comprising:

an internal circuit including a CPU executing programs, at least one internal circuit having a predetermined function and a bus line connecting the CPU to the internal device, extending externally and transferring an address and data; and

an external circuit provided externally of an externally extending portion of the bus line and including at least one external device having a predetermined function, wherein

the internal circuit includes a ciphering section interposed at an entrance to an external side and ciphering the address and the data on the bus line by ciphering patterns according to a plurality of regions divided from an address space allotted to entirety of the at least one external device.

Here, the ciphering patterns adopted by the ciphering section include one ciphering pattern in which neither the address nor data is ciphered.

As stated above, by dividing the address space into a plurality of areas and ciphering the address and the data by the patterns which differ according to the divided areas, it is made difficult to interpret ciphers.

In the first processing apparatus of the present invention stated above, it is preferable that the external circuit includes a plurality of external devices; and

the ciphering section performs ciphering using ciphering patterns according to the plurality of external devices, respectively.

By doing so, it is possible to perform ciphering according to the property of the external device as follows. If a flash ROM is provided as one of the external devices, for example, both the address and the data are ciphered for the flash ROM. As for a RAM, as one of the external devices, which can read continuous addresses at high speed, only the data is ciphered or the addresses are ciphered but the lower bit side of the addresses continuously read are not ciphered. If an I/O device is provided as one of the external devices, neither the address nor data is ciphered.

Further in the first processing apparatus of the present invention stated above, it is preferable that the ciphering section outputs a dummy address and dummy data to the externally extending portion of the bus line at timing at which the external circuit is not accessed.

This makes illicit interpretation more difficult.

Furthermore, in the first processing apparatus of the present invention stated above, it is preferable that the CPU is supplied with a clock and executes the programs synchronously with the supplied clock, and the ciphering section is supplied with a clock and performs ciphering synchronously with the supplied clock; and a clock supply section for supplying a clock at a higher speed than a speed of the clock supplied to the CPU, to the ciphering section.

This makes complicated ciphering possible.

Moreover, in the first processing apparatus of the present invention, it is preferable that the processing apparatus comprises ciphering pattern determination means for recognizing a constitution of the external circuit and determining a ciphering pattern of the ciphering section according to the constitution of the external circuit.

By providing this ciphering pattern determination means, it becomes unnecessary to carry out operations such as the operator's determination of ciphering patterns according to different constitutions of the external circuit.

Further, in the first processing apparatus of the present invention stated above, it is preferable that the ciphering section ciphers the address and the data on the bus line by ciphering patterns according to the plurality of regions divided from the address space allotted to the entirety of the no less than one external device and according to application programs executed by the CPU.

This makes ciphering patterns more complicated and illicit interpretation more difficult.

Furthermore, in the first processing apparatus of the present invention stated above, it is preferable that a deciphering section connected to the externally extending portion of the bus line, and returning the ciphered address and the data on the bus line to an address and data which are not ciphered.

If debugging is to be performed without providing this deciphering section, the debugging becomes extremely difficult since the address and data are ciphered. Considering this, this deciphering section is provided, thereby making it possible to easily carry out debugging at the time of developing the processing apparatus.

This deciphering section becomes unnecessary after the completion of debugging. Therefore, it is preferable that the deciphering section is detached from the processing apparatus, fixed to a disabled state or destroyed.

Additionally, in the first processing apparatus of the present invention stated above, it is preferable that the processing apparatus comprises ciphering pattern change means for changing a ciphering pattern whenever a predetermined initialization operation is carried out for one of the plurality of regions divided from the address space allotted to the entirety of the at least one external device.

By resetting the ciphering pattern in a predetermined initialization operation, e.g., when the processing apparatus is powered on or reset and the like, illicit interpretation is made more difficult and security thereby enhances.

Also, in the first processing apparatus of the present invention stated above, it is preferable that the ciphering section adopts a ciphering pattern in which ciphered data is changed according to the address, for one of the plurality of regions divided from the address space allotted to the entirety of the at least one external device, to thereby cipher the data.

By adopting the function of addresses as a ciphering function to cipher the data, complicated ciphering is made possible, illicit interpretation is made more difficult and data security thereby enhances.

The second processing apparatus among the processing apparatuses of the present invention is characterized by comprising:

an internal circuit including a CPU executing programs, at least one internal device having a predetermined function, and a bus line connecting the CPU to the internal device, extending externally and transferring an address and data; and

an external circuit provided externally of the externally extending portion of the bus line, and storing information, wherein

the internal circuit has information rewrite means for ciphering and rewriting at least part of the information stored in the memory in a predetermined initial operation.

Here, the predetermined initialization operation typically indicates an initialization operation when the apparatus is first powered on.

By ciphering and rewriting the content of the memory in the predetermined initialization operation such as, for example, the initialization operation when the apparatus is first powered on, data security further enhances.

In this case, it is preferable that the information rewrite means generates a random number, and performs ciphering by adopting a ciphering pattern using the generated random number.

If so, information is ciphered by a ciphering pattern which no one, including persons of a processing apparatus manufacturer, knows and data security thereby further enhances.

In the second processing apparatus of the present invention stated above, it is preferable that the at least part of the information stored in the memory has been already ciphered before the predetermined initialization operation is carried out; and

the information rewrite means temporarily returns the at least part of the information to information which is not ciphered, and rewrites the information by ciphering again the information by adopting a different ciphering pattern.

In this case, deciphering information for returning the at least part of information stated above to information before being ciphered may be stored in the memory; and

the information rewrite means may temporarily return the at least part of information to the information before being ciphered using the deciphering information.

In this way, by ciphering information by a different pattern at the time of shipment from a factory, security further enhances.

Further, as described above, in case of ciphering the information by a different ciphering pattern at the time of shipment from a factory, at least part of information stated above may be ciphered by a public key and a secret key may be embedded in this processing apparatus;

the information rewrite means may temporarily return the at least part of information to the information before being ciphered using the secret key, or an information acquisition section for acquiring ciphered deciphering information to return the at least part of information to the information before being ciphered may be provided; and

the information rewrite means may decipher the ciphered deciphering information which is acquired by the information acquisition section, fetch deciphering information in plain text, and temporarily return the at least part of information to the information before being ciphered using this deciphering information in plain text.

If the public key is employed as a ciphering pattern, information ciphered by the public key is written into a memory and the ciphered information is returned to information before being ciphered using the secret key embedded inside of the apparatus, security among, for example, a plurality of companies and the like which employ processing apparatuses having the same specification, respectively, can be ensured by passing only the public key to each company.

Further, by constituting the processing apparatus so that deciphering information can be acquired from externally, it is possible to obtain the deciphering information from a key management center and the like by, for example, communications and the like and flexible system can be, therefore, constituted.

Moreover, in the second processing apparatus of the present invention stated above, it is preferable that the internal circuit holds a ciphering pattern adopted by the ciphering section;

the processing apparatus further comprises a tamper detection section detecting tamper; and

ciphering pattern destruction means for destroying the ciphering pattern held in the internal circuit in response to tamper detection made by the tamper detection section.

When this processing apparatus is illicitly, forcibly opened or disassembled, the tamper detection is made. In response to the tamper detection, the ciphering pattern is destroyed, thereby making illicit interpretation further difficult and contributing to further enhancing security.

Moreover, the first integrated circuit among integrated circuits of the present invention to attain the above object, is characterized by constituted by mounting: a CPU executing programs; at least one internal device having a predetermined function; a bus line connecting the CPU to the internal device, externally extending, at least one external device having a predetermined function provided externally of the externally extending portion of the bus line, and transferring an address and data; and a ciphering section interposed at an entrance to an external side, and ciphering the address and the data on the bus line by ciphering patterns according to a plurality of regions divided from a space allotted to entirety of the at least one external device provided externally of the externally extending portion of the bus line.

The first integrated circuit of the present invention has the above constitution and exhibits the same function and advantage as those of the first processing apparatus of the present invention. Besides, the fist integrated circuit is an integrated circuit (LSI). Thus, it is made difficult to interpret the circuit arrangement and the like. In this respect, too, the first integrated circuit contributes to enhancing security.

Here, in the first integrated circuit stated above, as in the case of the first processing apparatus of the present invention, it is preferable that the ciphering patterns adopted by the ciphering section typically include a ciphering pattern in which neither the address nor data is ciphered; it is preferable that if a plurality of external devices are provided externally of the externally extending portion of the bus line, the ciphering section performs ciphering by the ciphering patterns according to the plurality of external devices, respectively; and

it is preferable that the ciphering section outputs a dummy address and dummy data to the externally extending portion of the bus line at the timing at which the external circuit is not accessed.

Further, it is preferable that the first integrated circuit comprises ciphering pattern change means for changing a ciphering pattern whenever a predetermined initialization operation is performed, for one of the plurality of regions divided from the address space allotted to the entirety of the at least one external device.

It is also preferable that the ciphering section ciphers the data by adopting a ciphering pattern in which ciphered data is changed according to the address, for one of the plurality of regions divided from the address space allotted to the entirety of the at least one external device.

Moreover, the second integrated circuit among the integrated circuits of the present invention is characterized by comprising: a CPU executing programs; at least one internal device having a predetermined function; and a bus line connecting the CPU to the internal device, extending externally, a memory storing information provided externally of an externally extending portion of the bus line, and transferring an address and data; wherein the integrated circuit includes information rewrite means for ciphering and rewriting at least part of the information stored in the memory in a predetermined initialization operation.

The second integrated circuit of the present invention has the above constitution and exhibits the same function and advantage as those of the second processing apparatus of the present invention as in the case of the relationship between the first processing apparatus of the present invention and the first integrated circuit of the present invention. Besides, the second integrated circuit is an integrated circuit (LSI). Thus, it is made difficult to interpret the circuit arrangement and the like. Also in this respect, the second integrated circuit contributes to enhancing security.

Here, in the second integrated circuit of the present invention, the above predetermined initialization operation, similar to the second processing apparatus of the present invention, typically indicates an initialization operation when the apparatus is first powered on,

it is preferable that the information rewrite means generates a random number, adopts a ciphering pattern using the generated random number and thereby performs ciphering;

it is preferable that at least part of the information stored in the memory is already ciphered before the predetermined initialization operation is executed; and

it is preferable that the information rewrite means rewrite the at least part of information by temporarily returning the at least part of information to the information before being ciphered, adopting a different ciphering pattern and re-ciphering the information.

In the present invention, it is possible to consider that one ciphering arithmetic system is one ciphering pattern according to the present invention, it is possible to consider that if the ciphering arithmetic systems differ, the ciphering patterns differ, and it is possible to consider that if the ciphering arithmetic system is common and variables and the like used in the ciphering arithmetic systems differ, the ciphering patterns differ.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments of the present invention will be described hereinafter.

FIG. 1is a block diagram showing the first embodiment of a processing apparatus according to the present invention.

A processing apparatus1shown inFIG. 1consists of a internal circuit100mounted inside of an LSI10, an external circuit200provided externally of the LSI10and the others including oscillators301and302and the like. This LSI10corresponds to one embodiment of an integrated circuit of the present invention.

The internal circuit100provided within the LSI10has a central processing unit (CPU)101as well as an internal memory102, a ciphering information register103, an address decoder104and a peripheral circuit105which are internal devices according to the present invention. The CPU101and the various internal devices are mutually connected through a bus line110. This bus line consists of an address bus111and a data bus112and extends externally of the LSI10. Various external devices are connected to a portion110aof the bus line110which extends externally. The external devices will be described later.

The internal circuit100constituted within the LSI10is provided with a ciphering section120interposed at an entrance to an external side. This ciphering section120consists of a ciphering circuit121, a bus interface122and a random number generation circuit123.

A clock signal from the oscillator301is inputted into the CPU101. The CPU101executes various programs synchronously with the clock signal received from the oscillator301.

A clock signal from another oscillator302which generates a clock signal higher in repetition frequency than the clock signal inputted into the CPU101, is inputted into the ciphering circuit121. The ciphering circuit121conducts a ciphering processing synchronously with the clock signal with a high repetition frequency from the oscillator302. The detail of the ciphering processing will be described later.

The above two oscillators301and302generate clock signals synchronous with each other. Therefore, the oscillators301and302may generate clock signals by dividing a high-speed clock obtained by a common oscillation source.

Further, a plurality of external devices, i.e., in case ofFIG. 1, a liquid crystal display (LCD)201, a keyboard (KB)202, a read-only memory (ROM)203, a flash ROM211and a random-access memory (RAM)212, are connected to the externally extending portion110aof the bus line110. InFIG. 1, a device213, such as another LSI, which is the same in constitution as the LSI10shown inFIG. 1and which has the same ciphering mechanism as that of the internal circuit100, and a deciphering circuit214for debugging programs operated by the CPU101are also connected to the externally extending portion110a. The device213and the deciphering circuit214are shown inFIG. 1for description purposes. The device213is connected to the LSI10if cipher communication is established between the LSI10and the device213having a similar constitution to that of the LSI10. The deciphering circuit214is connected for program debugging and detached after the completion of debugging.

The LCD201and the KB202as well as, in case of the embodiment shown inFIG. 1, the ROM203belong to external devices which cipher neither addresses nor data. The flash ROM211and the RAM, by contrast, belong to external devices which cipher and access addresses or data. Here, the flash ROM211ciphers only data and the RAM ciphers both addresses and data. Further, the device213ciphers both addresses and data and establishes cipher communication with the LSI10. When connected to the LSI10, the deciphering circuit214belongs to the devices which cipher neither addresses nor data in this embodiment.

Here, the bus line110is divided into a portion connected to the CPU101(the address and data of which portion are denoted by A1and D1, respectively), a portion put between the ciphering circuit121and the bus interface122(the address and data of which portion are denoted by A2and D2, respectively) and the externally extending portion110aof the LSI10(the address and data of which portion are denoted by A3and D3, respectively).

FIG. 2shows the memory map of the processing apparatus shown inFIG. 1.

A plurality of application programs are stored in the flash ROM which is one of the external devices. OS programs are stored in the internal memory which is one of the internal devices. Also, apparatus constitution information on this processing apparatus, e.g., types of external devices connected and memory capacities are recorded on the ROM which is one of the external devices.

FIG. 3is a flow chart of an initialization program executed when the processing apparatus shown inFIG. 1is powered on. This initialization program is stored in the internal memory102as one of the OS programs and executed by the CPU101when power is turned on.

According to the initialization program shown inFIG. 3, first, the apparatus constitution information stored in the ROM203which is one of the external devices is read (in a step a1), a memory map as shown inFIG. 2is created based on the information and a ciphering pattern is determined for each area of the memory map (in a step a2). It is noted that ciphering patterns include a pattern in which neither addresses nor data are ciphered.

In this initialization program, various other initialization processings follow (in a step a3).

Description will be continued, with reference back toFIG. 1.

The CPU101reads and writes information using the address A1and the data D1. The external devices are accessed using the address A3and the data D3irrespectively of whether it is necessary to cipher the devices or not (or it is prohibit the devices from being ciphered).

The CPU101writes area information on areas to be ciphered (ciphered areas) and a ciphering pattern for each ciphered area on the memory map shown inFIG. 2, in a ciphering information register103.

The address decoder104inputs the address A1and receives the area information indicating to-be-ciphered areas from the ciphering information register103. Then, the address decoder104outputs chip select signals CS0to CS6to an access target device and outputs a ciphering control signal Crp indicating which device is an access target and whether or not it is necessary to conduct ciphering, to the ciphering circuit121.

The ciphering circuit121receives the ciphering control signal Crp from the address decoder, conducts ciphering according to the ciphered areas when it is necessary to cipher the address A1and data D1based on the ciphering pattern information recorded on the ciphering pattern information register103, and outputs the address A2and data D2. The address A2and data D2are outputted externally of the LSI10as address A3and data D3by way of the bus interface123.

An external bus access signal indicating whether an external device is to be accessed, is transmitted from the CPU101to the bus interface122. The bus interface122outputs the address A2and data D2outputted externally from the ciphering circuit121as the external address A3and data D3when access to the external device is requested, generates a dummy address and dummy data based on the random number from the random number generation circuit123and outputs the dummy address and dummy data as the external address A3and data D3when access to the external device is not requested. This makes illicit interpretation more difficult.

The conversion of addresses and data from internally to externally has been described. As for the data D3read from the external flash memory211, RAM212, ROM203and the like is fetched into the internal side as the data D2. If the data is ciphered data, the ciphering circuit121deciphers the ciphered data and transmits the data to the CPU101and the like as data D1which is not ciphered.

In this embodiment, as the ciphering pattern, a ciphering pattern in which neither addresses nor data are ciphered is adopted. In addition, the following ciphering patterns are adopted:(1) Type 1

The higher level and lower level of the data as a result of the operation of type 2 are replaced.

In above types, reference p1denotes an appropriate constant obtained by, for example, random numbers;

A XOR B signifies performing an exclusive OR operation for bits corresponding to A and B, and A+B signifies an addition operation if A and B are assumed as numeric values.

As already described above with reference toFIG. 3, in the initialization operation when power is turned on, the CPU101reads the apparatus constitution information stored in the ROM203which is one of the external devices, creates a memory map as shown inFIG. 2and determines a ciphering pattern for each ciphered area. The flash ROM211adopts the ciphering pattern of, for example, (2) above in which the address is not ciphered and only the data is ciphered, and the RAM212adopts the ciphering pattern of, for example, (1) above in which both the address and the data are ciphered.

The RAM212adopts the ciphering pattern of type 1 in (1) above. Therefore, if it is assumed that p1=0 x 5555 (0 x means that following ‘5555’ is a hexadecimal), both the address and the data become completely different values from the original address and data as follows:

Further, the flash ROM211adopts the ciphering pattern of type 2 in (2) above. Therefore, if it is assumed that p1=0 x 5555, the address has no change and the data becomes a completely different value from the original data as follows:

D3⁡(0×5778)=A1⁡(0×0100)+D1⁡(0×0123)+p1⁡(0×5555).
Here, in ciphering the data, the data is a function of the address A1. Due to this, even if the data is the same, i.e., D1, the ciphered data D3differs from the original data according to the address A1, thereby further making illicit interpretation difficult and further enhancing security.

It is noted that the above description is a calculative example of a ciphering pattern. If an address is to be ciphered, a ciphering algorithm is taken into consideration so that a ciphered address does not overspread the address area of the ciphering target device and does not move to the address area of a device other than the ciphering target device.

In addition, even with the same RAM212, it is possible to change ciphering patterns for accessing the RAM212according to application programs executed by the CPU101. By not only selecting a ciphering pattern according to a memory area (a to-be-accessed external device) but also changing ciphering patterns according to application programs even in the same memory area (same external device), the address and data outputted to the externally extending portion110aof the bus line110are ciphered in a more complicated manner, thereby making illicit interpretation further difficult and further enhancing security.

Here, if it is assumed that the CPU101and the ciphering circuit121operate at the same clocks, the ciphering circuit121cannot perform a complex ciphering operation. For example, if the CPU101accesses an external device at one-clock intervals, the ciphering circuit121is required to complete its ciphering processing within one clock. In case of the type 3 ciphering processing in (3) above, for example, it requires one-clock time to perform the type 2 ciphering in (2) and it further requires one-clock time to exchange the higher level and lower level bits. Namely, it requires a total of two-clock time and it is necessary for the ciphering circuit121to complete the ciphering processing within one clock, then the ciphering pattern type 3 in (3) cannot be adopted.

In case of the embodiment shown inFIG. 1, the oscillator302which generates a higher-speed clock than that of the oscillator301which supplies a clock to the CPU101, is provided and the ciphering circuit121operates synchronously with the higher-speed clock supplied from the oscillator302. Thus, for example, the ciphering pattern of type 3 in (3) above or a more complicated ciphering pattern which requires a plurality of clocks can be adopted.

For example, if a clock with 10 MHzis supplied to the CPU101and a clock with 100 MHzis supplied to the ciphering circuit121, the ciphering circuit can perform a ciphering processing using 10 clocks.

Moreover, the internal circuit100of the processing apparatus shown inFIG. 1is incorporated into the LSI10and address and data ciphered through the ciphering circuit121and the bus interface122are outputted from the LSI10. With the address and data as they are, it is quite difficult for the CPU101to execute program debugging when developing a product employing this LSI10. In view of this, a deciphering circuit214is connected to the processing circuit shown inFIG. 1.

Before debugging, information on a ciphering pattern and a ciphered area having the same content as that written into the ciphered information register103from the CPU101are written into this deciphering circuit214. In the following debugging, the deciphering circuit214deciphers the ciphered address and data outputted to the externally extending portion110aof the bus line110based on the information on the ciphering pattern and the ciphered area written in advance, and deciphers the address to an address and data which are not ciphered. By doing so, it is possible to monitor the address and data deciphered by the deciphering circuit214by using, for example, a measuring instrument and to easily debug programs executed by the CPU101.

If this deciphering circuit214is left undetached, the significance of ciphering the address and data with a view to making illicit interpretation difficult is lost. For that reason, the deciphering circuit214is constituted as a device different from the processing apparatus and detached therefrom after the completion of debugging. Alternatively, the deciphering circuit214may remain attached thereto to be completely disabled.

Further, as shown inFIG. 1, the device213having the same ciphering mechanism as that of the LSI10is connected. If a plurality of LSIs10are combined as shown inFIG. 1, it is possible to establish cipher communication among the LSIs on the substrate.

FIG. 4is a block diagram of the second embodiment of a processing apparatus according to the present invention.

A processing apparatus5shown inFIG. 4consists of an internal circuit500incorporated into an LSI50and an external circuit600provided externally of the LSI50. The LSI50also corresponds to one embodiment of an integrated circuit according to the present invention.

The internal circuit500incorporated into the LSI50has a CPU501, an internal memory502, an address bus scramble arithmetic circuit503, an address bus scramble pattern memory504, a data bus scramble arithmetic circuit505, a data bus scramble pattern memory506and a decoder circuit507. All of these constituent elements are mutually connected through a bus line510. The bus line510consists of an address bus511and a data bus512. Although the internal circuit500is also provided with other internal devices, those devices are not shown and not described herein.

Among the constituent elements of the internal circuit500incorporated into the LSI10shown inFIG. 4, the composition of the constituent elements except for the CPU501and the internal memory502, i.e., the composition of the address bus scramble arithmetic circuit503, the address bus scramble pattern memory504, the data bus scramble arithmetic circuit505, the data bus scramble pattern memory506and the decoder circuit507corresponds to one example of a ciphering section according to the present invention.

Also, a RAM601and a flash ROM602constituting the external memory600are connected to an externally extending portion of the bus line of the LSI50.

OS programs are stored in the internal memory502constituting the internal circuit500. Application programs are stored in the flash ROM602constituting the external circuit600. These various programs are executed by the CPU501of the internal circuit500. Further, various data are stored in the RAM601constituting the external circuit600so as to be freely readable and writable.

The address bus scramble arithmetic circuit503and the data bus scramble arithmetic circuit505are arithmetic circuits which scramble (cipher) addresses A0to A15and data D0to D7, respectively. Scramble patterns employed in arithmetic operations performed by the address bus scramble arithmetic circuit503and the data bus scramble arithmetic circuit505are stored in the address bus scramble pattern memory504and the data bus scramble memory506, respectively. The address bus scramble pattern memory504and the data bus scramble pattern memory506, which are constituted of nonvolatile memories and the like, respectively, can hold the contents of data even if the processing apparatus is powered off. In addition, scramble patterns can be rewritten by the CPU501.

In this embodiment, an exclusive OR circuit is employed for each of the address bus scramble arithmetic circuit503and the data bus scramble arithmetic circuit505.

An input IN (address A0to A15or data D0to D7) is inputted into the exclusive OR circuit shown inFIG. 5(which is either the address bus scramble arithmetic circuit or the data bus scramble arithmetic circuit506shown inFIG. 4) by way of the bus line510, and a scramble pattern SP (SPA0to SPA15or SPD0to SPD7) is also inputted into the exclusive OR circuit from the address bus scramble pattern memory504or the data bus scramble pattern memory506. As an output OUT (SA0to SA15or SP0to SP7),
OUT=IN XOR SP  (1)
where XOR indicates an exclusive OR, is outputted from the exclusive OR circuit.

Here, by setting all bits of the scramble pattern SP at 0, scrambling can be prohibited. By setting a part of these bits at 0, scrambling for corresponding bits can be prohibited. For example, if lower level 4 bits out of 16 bits of the scramble pattern SP are set to be always 0, the lower level 4 bits are not scrambled (ciphered).

An exclusive OR circuit which performs an operation based on the formula (1) above is employed for each of the address scramble arithmetic circuit503and the data bus scramble arithmetic circuit505(which will be generally referred to as ‘scramble arithmetic circuit’ hereinafter). Now, various types of circuit constitutions which can be adopted for the scramble arithmetic circuit, will be shown by way of example.

FIGS. 6 to 9show circuit constitutions which can be adopted as the scramble arithmetic circuits, respectively.

An adder circuit is adopted for the scramble arithmetic circuit shown inFIG. 6and performs an operation of:
OUT=IN+SP  (2)

FIG. 7shows an adder circuit and an exclusive OR circuit and the following operation is performed:
OUT=(IN+SP1) XOR SP2  (3)
where SP1and SP2denote two scramble patterns either different or the same.

Further,FIG. 8shows an exclusive OR circuit and a bit switching circuit and the following operation is performed:
OUT=(IN XOR SP)m(4)
(after an exclusive OR operation is performed, higher level bits and lower level bits are switched by m bits).

Furthermore,FIG. 9shows an adder circuit and an exclusive OR circuit and the following operation is performed:
OUT=(IN (data)+IN (address))XOR SP(5)
where, IN (data) denotes data on the data bus and IN (address) denotes an address on the address bus. It is noted that the operation based on the formula (5) is performed by a circuit which can be adopted as the data bus scramble arithmetic circuit505. If an address is used to scramble data, quite complicated scrambling which makes illicit interpretation further difficult, is carried out.

FIGS. 10 and 11shows examples of the scramble arithmetic circuits to each of which a mask pattern is added so as to scramble only specified bits.

The scramble arithmetic circuit shown inFIG. 10consists of one inverting circuit, two AND circuits and one adder circuit, and performs the following operation:
OUT=(IN andM)+SP+(IN and (notM))  (6)

In the formula (6), M denotes a mask pattern. The bits of the mask pattern M which are set at 0, are not subjected to scrambling. For example, if the lower level 4 bits out of 16 bits are prohibited from being scrambled, the mask pattern M is set at 0 x FFF0.

Further, the scramble arithmetic circuit shown in FIG.11is constituted by connecting one inverting circuit, two AND circuits, two adder circuits and one exclusive OR circuit as shown inFIG. 11, and performs the following operation:

As exemplified above, various arithmetic circuits can be adopted for the scramble arithmetic circuit.

FIG. 12is the address map of the processing apparatus5in the second embodiment shown inFIG. 4.

AlthoughFIG. 4typically shows only one RAM, a work RAM and a backup RAM are actually provided. The work RAM is allotted an address region (work RAM region) of 0 x 00000 to 0 x 0FFFF. The backup RAM backs up data and holds the content of the data using a battery and the like even if the apparatus is powered off.

In addition, 0 x 20000 to 0 x 2FFFF indicate an IO region and 0 x 30000 to 0 x 3FFFF indicate a flash ROM region. Various application programs are stored in the flash ROM. The address bus scramble pattern memory504and the data bus scramble pattern memory506shown inFIG. 4are allotted to the IO region (0 x 2xxxx region).

Here, the decoder circuit shown inFIG. 4outputs a write enable signal *WEPMD of the data bus scramble pattern memory506and a write enable signal *WEPMA of the address bus scramble pattern memory504in accordance with a truth table of Table 1 based on the addresses A4to A19.

The Table 1 signifies that the data bus scramble pattern memory506turns into a writable state (*WEPMD=0) at 0 x 2000X, and that the address bus scramble pattern memory504turns into a writable state (*WEPMA=0) at 0 x 2001X.

FIG. 13shows a constitution of the data bus scramble pattern memory506. The data bus scramble pattern memory506consists of two decoders (decoder1and decoder2) and four data latches (data latches0to3). The data latches0to3are scramble pattern storage regions for scrambling the data of the work RAM, the backup RAM, the IO and the flash ROM, respectively. As shown in Table 4 shown later, the data latches0to3are allotted addresses 0 x 2000, 0 x 2001, 0 x 2002 and 0 x 2003, respectively.

The decoder1is a circuit which generates output enable signals *OE0to *OE3for selectively outputting scramble patterns stored in the data latches0to3, respectively and logically constituted as shown in a truth table of Table 2 below.

Further, the decoder2is a circuit which generates write enable signals *WE0to *WE3for writing new scramble patterns to the respective data latches0to3and logically constituted as shown in a truth table of Table 3 below.

The data latches0to3store data D0to D7outputted to the data bus512at the timing at which their corresponding write enable signals *WE0to *WE3become 0, and output the scramble patterns stored therein as data SPD0to SPD7when their corresponding output enable signals *OE0to *OE3become 0. If all of the output enable signals *OE0to *OE3are 1, all bits of the SPD0to SPD7become 0.

In this embodiment, data on the data bus512has a width of 8 bits (D0to D7), whereas data on the address bus511has a width of 16 bits (A0to A15) except for expansion bits SA16to SA19irrespective of scrambling. WhileFIG. 13shows the constitution of the data bus scramble pattern memory506, the address bus scramble pattern memory504has a wider bit width of an address than that of data. Due to this, the data latches0to3shown inFIG. 13are constituted of 2 bytes and addresses for selecting the respective data latches are constituted of A0to A3of 4 bits (in case of the data bus scramble pattern memory506shown inFIG. 13, addresses for selecting the data latches are A0to A1of 2 bits). The address bus scramble pattern memory504has the same constitution as that of the data bus scramble pattern memory except for the above architecture of data latches and address width. The illustration and further description of the address bus scramble pattern memory504will not be given herein.

In this embodiment, the data latches0to3of the data bus scramble pattern memory506and the data latches of the address bus scramble pattern memory504are allotted addresses shown in Table 4, respectively. Scramble patterns for executing scrambling with respect to the scramble target regions corresponding to the addresses are written into the respective addresses. The scramble patterns written into the respective data latches are outputted toward the scramble arithmetic circuit in accordance with address information (A0to A19) outputted from the CPU501.

Table 5 shows an example of settings for the pattern memories in this embodiment.

The RAM adopted in this embodiment is a high-speed assessible element when an address having continuous lower level 4 bits is accessed. As shown in Table 5, therefore, the lower level 4 bits of each address bus scramble pattern in the RAM are set at 0 (which means scrambling is not performed), thus ensuring high speed access in case of continuous memory access from the CPU.

Further, all bits are set at 0 in the IO region so as to prohibit scrambling.

FIG. 14shows a part of a program operating when the processing apparatus shown inFIG. 4is powered on or reset.

As shown inFIG. 14, a 16-bit random number RA and an 8-bit random number RD are generated (in steps b1and b2), the result of an AND operation between the 16-bit random number RA and 0×FFF0is written into the addresses 0 X 20008 to 0 x 20009, and the 8-bit random number RD is written into the address 0×20000 (in a step b3). As shown in Table 4, the addresses 0 x 20008 to 0 x 20009 indicate an address bus scramble pattern storage region for the work RAM and the address 0 x 20000 indicates a data bus scramble pattern storage region for the work RAM.

Namely, whenever the processing apparatus is powered on or reset, the scramble pattern of the work RAM is changed, which also contributes to making external illicit interpretation more difficult.

As for the backup RAM and the flash ROM, the consistency of the data and programs stored therein is necessary. Due to this, a preset scramble pattern is held for each memory and not changed even if the apparatus is powered on again or reset.

As for the flash ROM, it is also possible not to perform scrambling when data is written in a factory. In that case, when the apparatus is powered on for the first time since shipping, scrambling is performed according to the following procedures.

FIG. 15is a flow chart showing a flash ROM scrambling part of the program operating when the apparatus is powered on.

In this flow chart, a scramble flag indicating whether or not the content of the flash ROM was scrambled is checked first. The scramble flag is stored in a predetermined address of the backup RAM. When the backup RAM is written in a factory, the scramble flag is set at “not scrambled”.

The reason for checking the scramble flag is to determine whether or not the content of the flash ROM has been already scrambled. In stead of setting the scramble flag, a scramble pattern corresponding to the flash ROM may be read and it may be determined that the flash ROM has not been scrambled yet by confirming that all bits of the scramble pattern thus read are 0.

If it is determined that the scramble flag is set at “not scrambled” in a step c1, a step c2follows in which the content of the flash ROM is copied in the RAM. Programs for conducting the following processings are written in a part of this flash ROM.

Next, among the programs copied into the RAM, a program for conducting the following processing is controlled. Then, the flash ROM is erased (in a step c4), a 16-bit random number RA and an 8-bit random number RD are generated (in steps c5and c6), the 16-bit random number RA is written, as the address scramble pattern of the flash ROM, into the addresses 0 x 2000E to 0 x 2000F and the 8-bit random number RD is written, as the data scramble pattern of the flash ROM, into the address 0 x 20003 (see Table 4; in steps c7and c8).

Next, the programs copied in the RAM in the step c2are scrambled by the address scramble pattern and the data scramble pattern written into the addresses 0 x 2000E to 0 x 2000F and 0 x 20003, respectively and written back into the flash ROM (in a step c9), and the flash ROM scramble flag is changed to “scrambled” (in a step c10).

By doing so, the content of the flash ROM is scrambled when the processing apparatus is first powered on.

At the time of shipment from the factory, the content of the flash ROM may be scrambled in a specified scramble pattern, and scrambled again in another scramble pattern when the processing apparatus is first powered on. In that case, a descramble pattern (which is a scramble pattern itself since the scrambled content can be returned to original one by referring to the scramble pattern) for returning the content of the flash ROM which was scramble at the time of shipment from the factory to the original content, may be written into the scramble pattern memory or in the flash ROM. If written into the flash ROM, it is advantageously unnecessary to back up the scramble pattern memory by a battery and the like.

FIG. 16is a flow chart showing a flash ROM scrambling part of the program operating when the apparatus is powered on if the apparatus is shipped while a program scrambled in advance is written into the flash ROM and a scramble pattern needed for descrambling is stored in the flash ROM. This program is executed instead of the program shown inFIG. 15.

In a step d1, a scramble flag indicating whether or not the flash ROM has been already scrambled except for scrambling before shipment from the factory, is referred to. If no scrambling is conducted except for scrambling before shipment from the factory, steps d2to d12are executed.

In the steps d2and d3, the address bus scramble pattern SPA0and the data bus scramble pattern SPD0stored in the flash ROM are written into addresses 0 x 2000E to 0 x 2000F and 0 x 20003 respectively (see Table 4).

Next, in the step d4, the content of the flash ROM is returned to a state before the flash ROM is scrambled based on scramble patterns SPA0and SPD0, and the resultant content is copied in the RAM.

The following steps d5to d12are the same as the steps c3to c10shown inFIG. 15, respectively. The repetitive description thereof will not be, therefore, given herein.

By executing the program shown inFIG. 16, the content of the flash ROM is scrambled again with random numbers RA and RB newly generated when the apparatus is first powered on, and the scrambled state is held thereafter.

The above example shows that the scramble pattern is written into the flash ROM. It is also possible to scramble, for example, the content of the flash ROM in scramble patterns different according to individual products before shipment from the factory, to descramble patterns for descrambling the individual scramble patterns by a specific ciphering processing, and to write the descramble patterns into a region other than the flash ROM, such as the backup RAM. In that case, procedures for a deciphering processing to return the ciphered scramble patterns to scramble patterns which are not ciphered, are embedded in a certain region in the LSI50.

To conduct the above ciphering processing, a public key ciphering system (e.g., RAS and the like) can be utilized. That is, a descramble pattern ciphered by a public key (Kpb) is written into the flash ROM or a memory other than the flash ROM. The ciphered scramble pattern is deciphered by a secret key (Kpv) embedded in a certain region in the LSI50. In case of such a system, even if a plurality of companies employ LSIs50of the same specification, respectively, security between the companies can be ensured by passing only the public key to the respective companies and the secret key is kept secret.

FIG. 17is a flow chart showing a flash ROM scrambling part of the program operating when the apparatus is powered after a state in which the flash ROM is scrambled before shipment from the factory, a scramble pattern for descrambling the scrambled flash ROM is ciphered by a public key Kpb and stored in the backup RAM.

In steps e2and e3, the address bus scramble pattern Kpb (SPA0) which was ciphered by the public key is read from the backup RAM and deciphered by the secret key Kpv embedded in the LSI, to thereby fetch an address bus scramble pattern SPA0in a plain text.

In steps e4and e5, the data bus scramble pattern Kpb (SPD0) which was ciphered by the public key is read from the backup RAM and deciphered by the secret key Kpv embedded in the LSI, thereby fetching a data bus scramble pattern in a plain text.

In steps e6and e7, the address bus scramble pattern SPA0and the data bus scramble pattern SPD0in plain texts obtained as stated above are written into the addresses 0 x 2000E to 0 x 2000F and the address 0 x 20003, respectively (see Table 4).

The following steps e8to e16are the same as the steps d4to d12shown inFIG. 16, respectively. The repetitive description thereof will not be, therefore, given herein.

FIG. 18is a block diagram of the third embodiment of a processing apparatus according to the present invention.

Description will be given to the differences of the third embodiment from the second embodiment shown inFIG. 4.

In this third embodiment, an external circuit600is provided with an RAM601and a flash ROM602similar to those in the second embodiment shown inFIG. 4, and further provided with a communication control circuit603.

The communication control circuit603is connected to a key management center700through a communication network800. Programs scrambled before shipment from a factory are stored in the flash ROM602. The flash ROM602is constituted such that when the apparatus is first powered on, the flash ROM602receives deciphered scramble patterns through the communication network800.

FIG. 19is a flow chart showing a flash ROM scrambling part of the program executed when the processing apparatus shown inFIG. 18is powered on.

A step F1shown inFIG. 19is the same as the step e1shown inFIG. 17.

In a step f2, the communication control circuit is connected to the key management center. In a step f3, an address bus scramble pattern Kpb (SPA0) and a data bus scramble pattern Kpb (SPD0) ciphered by a public key Kpb are downloaded from the key management center.

In steps f4and f5, the ciphered address bus scramble pattern Kpb (SPA0) and the ciphered data bus scramble pattern Kpb (SPD0) are deciphered by a secret key Kpv embedded in an LSI, and an address bus scramble pattern SPA0and a data bus scramble pattern SPD0in plain text are fetched.

The following steps f6to f16are the same as the steps e6to e16shown inFIG. 17. The repetitive description thereof will not be, therefore, given herein.

As can be understood from the above, by allowing scramble patterns to be acquired from an external section such as the key management center through communications, system flexibility can be ensured.

FIG. 20is a block diagram of the fourth embodiment of a processing apparatus according to the present invention.

Description will be given to the differences of the fourth embodiment from the second embodiment shown inFIG. 4.

In the fourth embodiment shown inFIG. 20, an external circuit600is provided with an RAM601and a flash ROM602similar to those in the second embodiment shown inFIG. 4and also provided with a tamper detection switch604. Besides, a backup battery605is explicitly shown.

An address bus scramble pattern memory504and a data bus scramble pattern memory506are backed up by power supplied from the backup battery605so that the contents of these memories are not erased even if the processing apparatus is powered off.

Here, if this processing apparatus5is illicitly opened, the tamper detection switch604is actuated. Then, a power supply path from the backup battery605is shut off, an address bus scramble pattern and a data bus scramble pattern stored in the address scramble pattern memory504and the data bus scramble pattern memory506, respectively, are erased and the processing apparatus is thereby disabled. By doing so, it is possible to further ensure preventing illicit interpretation.

In the above-stated embodiments, the circuit incorporated into one LSI is referred to as an internal circuit and a group of devices provided externally of the LSI is referred to as an external circuit. The internal circuit is not necessarily mounted on one LSI. It is also possible, for example, that if a circuit is dispersed and mounted on a plurality of LSIs and the plurality of LSIs are packaged in one integrated circuit package or integrally molded, then the entire circuit dispersed and mounted on these plural LSIs may be referred to as an internal circuit.