HEMT power device operating in enhancement mode and manufacturing process thereof

The power device is formed by a D-mode HEMT and by a MOSFET in cascade to each other and integrated in a chip having a base body and a heterostructure layer on the base body. The D-mode HEMT includes a channel area formed in the heterostructure layer; the MOSFET includes a first and a second conduction region formed in the base body, and an insulated-gate region formed in the heterostructure layer, laterally and electrically insulated from the D-mode HEMT. A first metal region extends through the heterostructure layer, laterally to the channel area and in electrical contact with the channel area and the first conduction region.

BACKGROUND

Technical Field

The present disclosure relates to a HEMT power device, operating in enhancement mode, and to the manufacturing process thereof.

Description of the Related Art

As is known, HEMTs (High-Electron-Mobility Transistors), also known as HFETs (Heterostructure Field-Effect Transistors) or as MODFETs (Modulation-doped Field-Effect Transistors), are encountering wide diffusion due to their capacity to operate at high frequencies, as well as to withstand high breakdown voltages. In particular, HEMT devices based upon Si—GaN (or GaN-On-Si “Gallium-Nitride-On-Silicon”) technology are increasingly widespread due to their low cost and high scalability.

In particular, HEMTs based upon Si—GaN technology have extensive application in power-converter devices. These, as known, basically comprise a control stage and at least one power element, generally integrated in separate chips.

In particular, there are two main N-types of HEMTs based upon GaN-On-Si technology:transistors operating in enhancement mode (E-mode), normally off; i.e., they are off when the gate-to-source voltage Vgs is zero and require a positive Vgs voltage (Vgs>0 V) to switch on; andtransistors operating in depletion mode (D-mode), normally on; i.e., they are on when the voltage Vgs is zero and require a negative Vgs voltage (Vgs<0 V) to switch off.
D-mode transistors are more mature, are intrinsically more robust and reliable than transistors that operate in E-mode. However, D-mode transistors are not compatible with the drivers of power converters, normally designed to work with E-mode transistors. For this reason, generally D-mode transistors are operatively converted into E-mode transistors, off at zero Vgs, using a cascade, mode-conversion circuit. To this end, the mode-conversion circuit is formed separately from the D-mode transistor and is connected thereto via wired connections during assembly at package or board level. However, the presence of interconnection wires limits the maximum switching frequency usable in high-frequency applications, such as in power converters, and requires a large board area. In addition, it also causes a reduction in power-conversion efficiency.

BRIEF SUMMARY

The present disclosure provides a HEMT power device that overcomes the drawbacks of the prior art.

According to embodiments of the present disclosure, a HEMT power device and the manufacturing process thereof are provided, as defined in the claims.

In practice, a power device is provided, that integrates, in a same chip, a D-mode HEMT and a conversion transistor; the latter causes the power device to operate in enhancement mode (E-mode) and enables the D-mode HEMT to be driven using the same driver as that for an E-mode transistor. No connection wires are therefore necessary between the conversion transistor and the D-mode HEMT. Specifically, the conversion transistor of, e.g., a MOSFET type, is formed in the substrate of a semiconductor material (for example, silicon) underneath the heterostructure layer of the D-mode HEMT; the substrate also assumes an electrically active function. Note that conventionally, a substrate in a HEMT device does not normally have an own electrical function, but functions purely as a mechanical support.

According to an aspect of the disclosure, in the present power device, the chip of semiconductor material that integrates both the D-mode HEMT and the MOSFET conversion transistor has a first, a second and a third external connection terminal, wherein the first external connection terminal is coupled to a first conduction terminal of the D-mode HEMT, a second conduction terminal of the D-mode HEMT is coupled to a first conduction terminal of the MOSFET, a second conduction terminal of the MOSFET is coupled to the second external connection terminal and a gate terminal of the MOSFET is coupled to the third external connection terminal.

For instance, if the MOSFET is an N-channel MOSFET (P-type substrate), the drain terminal of the D-mode HEMT is connected to the first external connection terminal, the source terminal of the D-mode HEMT is connected to the drain terminal of the MOSFET, and the source terminal of the MOSFET is connected to the second external connection terminal. If the MOSFET is a P-channel MOSFET (N-type substrate), the drain terminal of the D-mode HEMT is connected to the first external connection terminal, the source terminal of the D-mode HEMT is connected to the source terminal of the MOSFET, and the drain terminal of the MOSFET is connected to the second external connection terminal.

The gate terminal of the D-mode HEMT may be coupled to a fourth external connection terminal of the chip, if present, or may be coupled to the second external connection terminal.

Moreover, the chip of semiconductor material may include a fifth external connection terminal coupled to the intermediate point between the second conduction terminal of the D-mode HEMT (source) and the first conduction terminal of the MOSFET (source or drain, according to the channel type of the MOSFET).

DETAILED DESCRIPTION

FIGS.1and1Ashow a power device1integrating a D-mode HEMT2in Si—GaN technology and a MOSFET3, cascaded to each other. It will be noted that, as explained below in greater detail, the structure ofFIG.1(showing the cross-section in a plane XZ of a Cartesian reference system XYZ) may have different implementations as regards the geometry in a third direction Y perpendicular to the drawing plane. In particular, the regions and structures ofFIG.1may extend along lines parallel to axis Z, or have a circular and/or annular development with a different shape and symmetry, as discussed hereinafter. Specifically,FIG.1Arelates to an embodiment with circular symmetry with respect to a central axis O, and the following description refers to this topology.

In detail, the power device1ofFIGS.1and1Acomprises a body5formed by a stack of layers superimposed on each other and in direct mutual contact, including a substrate10, of silicon, here of a P-type with a crystallographic orientation <111>; an epitaxial layer11, also of P-type silicon, less doped than the substrate10; a dielectric layer12, for example, of aluminum nitride (AlN); a channel layer13, here of gallium nitride (GaN); and a barrier layer14, here of aluminum gallium nitride (AlGaN). An insulation/passivation layer18extends over the surface of the barrier layer14. A first gate region19, with annular shape, hereinafter also referred to as “HEMT gate region”, is formed inside the insulation/passivation layer18.

The substrate10and the epitaxial layer11as a whole form a base layer16and have a first interface12A with the dielectric layer12. The channel layer13, the barrier layer14, and the dielectric layer12, as a whole, form a heterostructure layer17. The channel layer13and the barrier layer14form a second interface13A between them, where free electrons are present, as represented schematically inFIG.1. The body5also has a bottom surface5A, formed by the substrate10, and a top surface5B, formed by the insulation/passivation layer18.

In the embodiment shown inFIG.1, the silicon layer16accommodates a drain region20and a source region21, both of N-type and with a same doping level, extending inside the epitaxial layer11from the first interface12A. Furthermore, in the embodiment shown, the drain region20surrounds the source region21.

An enhanced region23, of P-type and a higher doping level than the epitaxial layer11, extends from the first interface12A between and partially underneath the source region21as far as approximately the substrate10. In the embodiment shown, the drain region20and the source region21have a circular ring shape, and the enhanced region23has a circular shape.

The power device1comprises a first, a second and a third metal region25,26,27.

The first metal region25, which is circular ring-shaped in the top plan view ofFIG.1A, comprises a tubular portion25A and a surface portion25B. The tubular portion25A of the first metal region25extends vertically through the insulation/passivation layer18and the heterostructure layer17as far as and in electrical contact with the drain region20; the surface portion25B extends over the surface5B of the body5above the HEMT gate region19. In practice, the surface portion25B of the first metal region25has a larger external diameter than the external diameter of the HEMT gate region19and a smaller internal diameter than the internal diameter of the HEMT gate region19. Furthermore, the tubular portion25A of the first metal region25has a smaller external diameter than the internal diameter of the HEMT gate region19and approximately equal to the external diameter of the drain region20, and has a larger internal diameter (coinciding with the internal diameter of the surface portion25B) than the internal diameter of the drain region20.

The second metal region26has, in the top plan view ofFIG.1A, a circular shape, and extends through the insulation/passivation layer18and the heterostructure layer17as far as, and in electrical contact with, the source region21and the enhanced region23. In particular, the second metal region26has a larger diameter than the smaller diameter of the source region21. In practice, the second metal region26is surrounded at a distance by the first metal region25, is crossed by the central axis O, and short-circuits the enhanced region23and therefore the substrate10with the source region21.

The third metal region27extends on the channel layer13, through the barrier layer14and the insulation/passivation layer18, is in direct electrical contact with and surrounds at a distance the first metal region25.

A first and a second electrical-insulation regions30,31, for example of silicon oxide or silicon nitride and having the shape of cylindrical walls, extend vertically and concentrically through the insulation/passivation layer18and the heterostructure layer17as far as the first interface12A, between the tubular portion25A of the first metal region25and the second metal region26, at a distance therefrom and mutually spaced from each other. The first electrical-insulation region30extends vertically over the drain region20and is in direct contact therewith. The second electrical-insulation region31extends vertically over the source region21and is in direct contact therewith.

In practice, the first electrical-insulation region30is arranged externally with respect to the second electrical-insulation region31, the second electrical-insulation region31surrounds a first portion32of the heterostructure layer17accommodating the second metal region26, and the first and the second electrical-insulation regions30,31delimit between them a second portion33of the heterostructure layer17.

Therefore, the second portion33of the heterostructure layer17has a hollow cylindrical shape (tubular shape) and comprises a first part33A, formed by the channel layer13, and a second part33B, formed by the dielectric layer12. The first part33A of the second portion33of the heterostructure layer17forms a gate region of the MOSFET3, and the second part33B of the second portion33of the heterostructure layer17forms a gate-dielectric region of the MOSFET3. Consequently, the parts33A and33B are hereinafter also referred to as “MOSFET gate region33A” and “MOSFET gate-dielectric region33B”. Therefore, the MOSFET3has here a circular symmetry (even though this is not mandatory, as mentioned above).

A fourth metal region35extends inside the second portion33of the heterostructure layer17, through the insulation/passivation layer18and the barrier layer14, and is in direct electrical contact with the channel layer13. In this way, the fourth metal region35forms a gate metallization in contact with the MOSFET gate region33A of the MOSFET3.

A rear metal region40extends on the bottom surface5A of the body5.

In practice, in the power device1, the MOSFET3is an N-channel MOSFET, since the base layer16is of a P-type.

In the power device1ofFIG.1, the base body16is formed by a monocrystal having a crystallographic orientation <111>.

Use of such an orientation requires adoption of some technological measures in the design step. In fact, active transistors used in integrated circuits are generally formed in substrates with crystallographic orientation <100>, having repeatability, reliability, and electronic mobility characteristics suited to MOS transistors. However, substrates with crystallographic orientation <100> are not adapted for growing GaN layers thereon. To enable integration of the MOSFET3in the substrate of the D-mode HEMT device2, a substrate with a crystallographic orientation <111> is thus used, which has a high crystal quality. In addition, to obtain electrical characteristics comparable with the ones obtainable using a <100> substrate, the MOSFET3is appropriately sized. In particular, the MOSFET3is manufactured with greater dimensions than a corresponding MOSFET having equal electrical performances, formed in a <100> substrate, and the sizing is made, in a known way for the person skilled in the art, so as to compensate for the lower mobility of the electrons in the <111> substrate.

In the power device1ofFIG.1, the substrate10is highly conductive, and has dopant atoms, for example, with a doping concentration of >1019atoms/cm3. The drain and the source regions20,21have a doping concentration, for example >1019atoms/cm3. As such, the drain and source regions20,21are also highly conductive, even if they have a conductivity of an opposite type from that of the substrate10. The epitaxial layer11has a lower conductivity than the substrate10, and has dopant atoms with a lower concentration, typically from 1016to 1017atoms/cm3, or even lower or higher (but still lower than the substrate10) according to the breakdown voltage desired for the power device1, as appreciable by a person skilled in the art. Also the thickness of the epitaxial layer11depends upon the desired breakdown voltage; for example, it may be 2-3 μm in the case of lower operating voltages (<10 V) and 5-10 μm in the case of higher voltages.

The enhanced region23enables reduction of the contact resistance of the second metal region26.

With reference also toFIG.2, representing the electrical equivalent of the power device1(integrated in a first chip51) and of a possible driver50, the third metal region27of the power device1ofFIG.1forms a drain electrode D for the D-mode HEMT2, which may be coupled to a drain pin52of the power device1. The first metal region25forms a floating electrode for the source of the D-mode HEMT2and of the drain for the MOSFET3, indicated as electrode INT(S/D) and may be coupled to a floating pin53of the power device1; the second metal region26and the rear metal region40form source electrodes S for the MOSFET3and may be coupled together and to a source pin54of the power device1; and the fourth metal region35forms, as said, a gate electrode G1for the MOSFET3(which may be coupled to a first gate pin55of the power device1). Furthermore, in a not shown way, the HEMT gate region19is coupled, through an own metallization forming a gate electrode G2for the D-mode HEMT2, to a second gate pin56of the power device1.

Furthermore, as shown inFIG.2, the driver50comprises a resistor60, coupled between the first gate pin55and the source pin54of the power device1; a driving stage61, coupled between a first and a second supply lines65,66; and a power-up device62, coupled between the first gate pin55and the first supply line65, receiving a control signal Vin, and having an output coupled to the second gate pin56of the power device1. The source pin54of the power device1is grounded.

The driver50is generally integrated in a second chip68separated from the first chip51; in this case, the resistor61may be integrated in the second chip68or in the first chip51using any known technique.

The driving stage61may be of a standard type designed for working with E-mode HEMTs since the power device1is electrically equivalent to a known E-mode HEMT.

Thereby, the power device1has high efficiency, in particular in power-conversion applications, high switching frequency (it can work at frequencies beyond 1 MHz), requires a reduced area, and therefore has lower costs than a non-integrated solution.

FIGS.2and3show a different embodiment, where the power device, now designated by101, is formed in a base layer116of an N-type and therefore comprises, in addition to a HEMT102, a P-channel MOSFET103.

The power device101has a structure similar to the power device1ofFIG.1and, in top plan view, may have the same structure shown inFIG.1A. Consequently, the structures (layers and regions) similar to the homologous structures ofFIG.1are designated by reference numbers increased by 100 and will not be described in detail, andFIG.1Amay be useful for also understanding the type of the device101, increasing the reference numbers ofFIG.1Aby 100.

In detail, in the power device101, the epitaxial layer111houses a source region120and a drain region121, of a P-type; namely, the source region120is electrically coupled to the first metal region125and surrounds at a distance the drain region121of the MOSFET103. The enhanced region123is here of an N-type.

Furthermore, the first metal region125is connected to the outside via a terminal INT.

The power device101has the electrical equivalent shown inFIG.4, which moreover represents a possible driver150. Also inFIG.4, the elements similar to those ofFIG.2are designated by reference numbers increased by 100 and will not be described any further.

In the circuit ofFIG.4, the resistor160is coupled between the first gate pin155and the intermediate pin153of the power device101. Furthermore, the power-up device162is coupled between the first gate pin155and the second supply line166.

Also in this case, the resistor161may be integrated in the second chip168or in the first chip151, using any known technique.

FIG.5shows an embodiment where the power device, here designated by201, is obtained in a P-type base layer216and has a structure similar to that of the power device1ofFIG.1, except that it has no the enhanced region23. Consequently, the structures (layers and regions) similar to the homologous structures ofFIG.1are designated by reference numbers increased by 200 and will not be described in detail, andFIG.1Amay be useful for also understanding the type of the device101, considering the reference numbers ofFIG.1Aincreased by 200.

Furthermore, in the power device201ofFIG.5, the rear metal region40ofFIG.1is not present, and the source terminal S of the power device201is formed by the second metal region226. Furthermore, in the power device201, the HEMT gate region219is not connected separately with the outside, but, as shown in the electrical equivalent ofFIG.6, is electrically coupled to the second metal region226and to the source pin254of the power device201. The power device201therefore has only three pins252(drain),254(source) and255(gate), and the driver (not shown) is connected to the latter.

FIG.7shows an embodiment where the power device, here designated by301, is formed in an N-type base layer316and has a structure similar to the power device101ofFIG.3, except that there is no enhanced region123. Consequently, the structures (layers and regions) similar to the homologous structures ofFIG.3are designated by reference numbers increased by 200 and will not be described in detail. Also in this case,FIG.1Amay be useful for understanding the type of the device301, increasing the reference numbers ofFIG.1Aby300.

In the power device301ofFIG.7, the rear metal region140ofFIG.2is not present, and the source terminal S of the power device301is connected to the drain region321of the MOSFET303through the second metal region326. Furthermore, in the power device301, the HEMT gate region319is not connected separately to the outside, as shown in the electrical equivalent ofFIG.8, but is electrically coupled to the second metal region326and to the source pin354of the power device301. The power device301therefore has only three pins352(drain),354(source) and355(gate).

Hereinafter, the steps for manufacturing the power device1ofFIG.1will be described with reference toFIGS.9to19. The description below applies likewise (with the possible modifications of the used dopant and possibly the absence of the step for forming the enhanced regions23,123) for manufacturing the power devices101,201, and301.

FIG.9shows a wafer400of semiconductor material designed to form the base layer16, at the end of the manufacturing steps, after sawing of the wafer. Consequently (as for the other layers), the same reference numbers ofFIG.1will be used.

InFIG.9, the base layer16(comprising the substrate10and the epitaxial layer11grown in a known way thereon) has already been subjected to usual photolithographic steps for selective implantation of the enhanced region23.

InFIG.10, the wafer400is subjected to further photolithographic steps for implanting the drain and the source region20,21with P-type dopant, for example boron, and for their diffusion.

InFIG.12, the dielectric layer12is deposited on the surface of the epitaxial layer11and,FIG.13, the channel layer13, of GaN, and the barrier layer14, of AlGaN are grown thereon, in a known way, forming heterostructure layer17.

Then,FIG.13, the wafer400is deep etched to form first and second trenches401,402extending though the heterostructure layer17; the etch stops on the epitaxial layer11. The first and the second trenches401,402are then filled with dielectric material, such as silicon oxide or silicon nitride to form the electrical-insulation regions30,31, and therefore have the aforementioned shape thereof, in particular a tubular shape. In this way, inside the heterostructure layer17, the first portion32and the second portion33of the heterostructure layer17are electrically insulated from each other and from the rest of the wafer400. Then, a first insulating layer403, of dielectric material such as silicon oxide, is deposited on the heterostructure layer17.

Next,FIG.14, the HEMT gate region19is formed on the first insulating layer403by depositing and defining a conductive material, for example polycrystalline silicon or a metal, such as tungsten, titanium, aluminum; then a second insulating layer404, of dielectric material, for example silicon oxide, is deposited. In practice, the first and the second insulating layers403,404envelop and electrically insulate the HEMT gate region19, thus forming the insulation/passivation layer18.

InFIG.15, contacts are opened towards the MOSFET gate region33A, the channel layer13, and the drain region20. To this end, the wafer400is masked, and the insulation/passivation layer18and the barrier layer14are etched, forming third trenches405. Moreover,FIG.16, before or after forming the third trenches405, by deep etching the insulation/passivation layer18, the barrier layer14, the channel layer13, and the dielectric layer12, fourth trenches406are formed where it is desired to form the tubular portion25A of the first metal region25and the second metal region26.

Then,FIG.17, a metal layer410, for example of aluminum, copper, tungsten or any alloy thereof, is deposited and fills the trenches405,406, and,FIG.18, the metal layer410is photolithographically defined, to form the metal regions25-27and35. InFIG.19, the rear metal region40is formed on the bottom surface5A of the wafer400.

Finally, the wafer400is diced to form the single power devices1.

As explained above, by virtue of the integration of the MOSFET3,103,203,303in the same chip51,151,251,351as the D-mode HEMT2,102,202,302, the power device1,101,201,301can work at higher switching frequencies and in a more efficient way as compared to the discrete solutions. Integration is obtained, in a simple way using well-known process steps that can therefore be controlled individually in an effective and reliable way, partially underneath the D-mode HEMT and therefore without requiring any further area. The shown solution is thus very efficient from the standpoint of the integration area and therefore of the costs of the finished power device.

Finally, it is clear that modifications and variations may be made to the power device and to the manufacturing process described and shown herein, without thereby departing from the scope of the present disclosure, as defined in the attached claims. For instance, the various embodiments described may be combined to provide further solutions.

Furthermore, the three-dimensional structure may vary with respect to the above description. For instance, the source and drain regions, the metal regions, and the electrical-insulation regions may extend transverse to the drawing plane, i.e., in the direction Y. The structure may comprise only half of the shown structures (for example, it may comprise only the portions to the left or to the right of the central axis O ofFIG.1). Alternatively, the structure may have, in top plan view, a rectangular, square or oval shape, instead of being circular, or may be formed with a circular symmetry about one of the edges (the left-hand edge or the right-hand edge) ofFIG.1(i.e., about the third metal region—drain metal27). The variants referred to may obviously apply also to the embodiments ofFIGS.3,5, and7.

The materials, dimensions, and conductivity levels referred to may be modified according to the electrical characteristics that it is desired to achieve as known to the person skilled in the art.

The various embodiments described above can be combined to provide further embodiments.