Image sensor, endoscope, and endoscope system

An image sensor includes: pixels; first transfer lines configured to transfer imaging signals of shared pixels that are present in a plurality of different rows and share a single column transfer line for each predetermined number of pixels adjacent in a row direction and; a constant current source configured to transfer the imaging signals; output units configured to externally output the imaging signals; and a control unit configured to simultaneously and externally outputs, by simultaneously driving the plurality of shared pixels present in a same single column transfer line in the plurality of different rows, each of the plurality of imaging signals, which are output from the shared pixels and are present in the same column in the plurality of different rows, and externally output all of the imaging signals of the shared pixels present in the plurality of different rows same number of times as the predetermined number.

BACKGROUND

The present disclosure relates to an image sensor, an endoscope, and an endoscope system.

In recent years, regarding complementary metal oxide semiconductor (CMOS) image sensors, there is a known technology for allowing a plurality of adjacent pixels to share a single vertical signal line and transferring image signals (see International Publication Pamphlet No. WO 2007/108129). With this technology, by allowing a plurality of adjacent pixels to share a single vertical signal line, a small sized image sensor with high pixel is implemented.

SUMMARY

An image sensor according to one aspect of the present disclosure includes: a plurality of pixels arranged in a two-dimensional matrix and configured to receive light from outside and generate imaging signals in accordance with an amount of received light; a plurality of first transfer lines configured to transfer the imaging signals of shared pixels that are present in a plurality of different rows and share a single column transfer line for each predetermined number of pixels adjacent in a row direction and; a constant current source provided in each of the plurality of first transfer lines and configured to transfer the imaging signals output from the pixels to the first transfer lines; a plurality of output units configured to externally output the imaging signals transferred from the plurality of first transfer lines; and a control unit configured to simultaneously and externally outputs, from the plurality of output units, by simultaneously driving the plurality of shared pixels present in a same single column transfer line in the plurality of different rows, each of the plurality of imaging signals, which are output from the shared pixels and are present in the same column in the plurality of different rows, and externally output all of the imaging signals of the shared pixels present in the plurality of different rows same number of times as the predetermined number.

DETAILED DESCRIPTION

In the following, as modes for carrying out the present disclosure (hereinafter, referred to as “embodiments”), an endoscope system provided with an endoscope having image sensor that is disposed at a distal end of an insertion portion that is inserted into a subject will be described. The present disclosure is not limited to the embodiments. In the drawings, components that are identical to those in embodiments are assigned the same reference numerals. The drawings used for the descriptions below are only schematic illustrations. The relationship between the thickness and the width of each member, the proportions of each member, and so on are different from those used in practice. The size or reduction in scale of elements may sometimes differ between the drawings.

First Embodiment

Configuration of Endoscope System

FIG. 1is a schematic diagram illustrating the overall configuration of an endoscope system according to a first embodiment. An endoscope system1illustrated inFIG. 1includes an endoscope2, a transmission cable3, a connector portion5, a processor6(processing device), a display device7, and a light source device8.

The endoscope2captures an image of the interior of a subject by inserting an insertion portion100that is a part of the transmission cable3into a body cavity of the subject and then outputs an imaging signal (image data) to the processor6. Furthermore, in the endoscope2, an imaging unit20(imaging device) that captures an in-vivo image is provided at a distal end101side, which is one end of the transmission cable3, of the insertion portion100that is inserted into the body cavity of the subject and an operating unit4that receives various operations performed with respect to the endoscope2is provided on a proximal end102side of the insertion portion100. The imaging signal of the image captured by the imaging unit20passes through the transmission cable3having a length of, for example, several meters and is output to the connector portion5.

The transmission cable3connects the endoscope2and the connector portion5and connects the endoscope2and the light source device8. Furthermore, the transmission cable3propagates the imaging signal generated by the imaging unit20to the connector portion5. The transmission cable3is formed by using a cable, an optical fiber, or the like.

The connector portion5is connected to the endoscope2, the processor6, and the light source device8; performs predetermined signal processing on the imaging signal that is output by the connected endoscope2; converts an analog imaging signal to a digital imaging signal (A/D conversion); and outputs the converted imaging signal to the processor6.

The processor6performs predetermined image processing on the imaging signal that is input from the connector portion5and then outputs the processed imaging signal to the display device7. Furthermore, the processor6performs overall control of the endoscope system1. For example, the processor6performs control for changing the illumination light emitted by the light source device8and switching an imaging mode of the endoscope2.

The display device7displays an image associated with the imaging signal that has been subjected to image processing by the processor6. Furthermore, the display device7displays various kinds of information related to the endoscope system1. The display device7is formed by using a display panel, such as a liquid crystal or organic electro luminescence (EL) display panel.

The light source device8irradiates an object with illumination light from the distal end101side of the insertion portion100of the endoscope2via the connector portion5and the transmission cable3. The light source device8is formed by using a white light emitting diode (LED) that emits white light, an LED that emits special light of narrow-band light having a wavelength band narrower than the wavelength band of the white light. The light source device8irradiates, under the control of the processor6, the object with the white light or the narrow-band light via the endoscope2.

FIG. 2is a block diagram illustrating a function of a relevant part of the endoscope system1illustrated inFIG. 1. Each of the components in the endoscope system1in detail and the path of the electrical signal in the endoscope system1will be described with reference toFIG. 2.

Configuration of Endoscope

First, the configuration of the endoscope2will be described. The endoscope2illustrated inFIG. 2includes the imaging unit20, the transmission cable3, and the connector portion5.

The imaging unit20includes a first chip21(image sensor) and a second chip22. Furthermore, the imaging unit20receives, together with ground GND, a power supply voltage VDD generated by a power supply voltage generating unit55, which will be described later, in the connector portion5via the transmission cable3. A condenser C1used to stabilize a power supply is provided between the power supply voltage VDD supplied to the imaging unit20and the ground GND.

The first chip21includes a light-receiving unit23having a plurality of arrayed unit pixels230that are arranged in a two-dimensional matrix, that receive light from outside, that generate image signals in accordance with an amount of light received, and that output the generated image signals; a reading unit24that reads an imaging signal subjected to photoelectric conversion in each of the unit pixels230in the light-receiving unit23; and a timing generating unit25that generates a timing signal based on the reference clock signal and a synchronization signal input from the connector portion5and that outputs the generated signals to the reading unit24. A more detailed description of the configuration of the first chip21will be described later.

The second chip22includes a buffer27that amplifies the imaging signal output from each of the unit pixels230in the first chip21and that outputs the amplified imaging signals to the transmission cable3. Furthermore, a combination of the circuits disposed on the first chip21and the second chip22may appropriately be changed. For example, the timing generating unit25disposed on the first chip21may also be disposed on the second chip22.

The connector portion5includes an analog front-end unit51(hereinafter, referred to as an “AFE unit51”), an A/D converter52, an imaging signal processing unit53, a driving pulse generating unit54, and the power supply voltage generating unit55.

The AFE unit51receives the imaging signals propagated from the imaging unit20; extracts an alternating-current component by using the condenser after having performed impedance matching by using a passive element, such as a resistance; and determines an operating point based on partial pressure resistance. Then, the AFE unit51corrects the imaging signals (analog signals) and outputs the corrected imaging signals to the A/D converter52.

The A/D converter52converts the analog imaging signals input from the AFE unit51to digital imaging signals and outputs the converted signals to the imaging signal processing unit53.

The imaging signal processing unit53is formed by, for example, a field programmable gate array (FPGA), performs a process, such as noise removal and format conversion processes, on the digital imaging signals that are input from the A/D converter52, and then outputs the processed signal to the processor6.

The driving pulse generating unit54generates, based on a reference clock signal (for example, a clock signal with 27 MHz) that is supplied from the processor6and that is the criteria for the operation of each of the components in the endoscope2, a synchronization signal indicating a start position of each frame and outputs the generated synchronization signal, together with the reference clock signal, to the timing generating unit25in the imaging unit20via the transmission cable3. Here, the synchronization signal generated by the driving pulse generating unit54includes horizontal synchronization signals and vertical synchronization signals.

The power supply voltage generating unit55generates a power supply voltage needed to drive the first chip21and the second chip22from the power supply supplied from the processor6and then outputs the generated power supply voltage to the first chip21and the second chip22. The power supply voltage generating unit55generates the power supply voltage needed to drive the first chip21and the second chip22by using a regulator or the like.

Configuration of Processor

In the following, the configuration of the processor6will be described. The processor6is a control device that performs overall control of the endoscope system1. The processor6includes a power supply unit61, an image signal processing unit62, a clock generating unit63, a recording unit64, an input unit65, and a processor control unit66.

The power supply unit61generates a power supply voltage VDD and supplies the generated power supply voltage VDD to, together with the ground (GND), the power supply voltage generating unit55in the connector portion5.

The image signal processing unit62converts a digital imaging signal subjected to signal processing by the imaging signal processing unit53to an image signal by performing image processing, such as a synchronization process, a white balance (WB) adjustment process, a gain adjustment process, a gamma correction process, a digital analog (D/A) conversion process, a format conversion process, and then outputs the processed image signal to the display device7.

The clock generating unit63generates a reference clock signal that is the criteria for the operation of each of the components in the endoscope system1and outputs the reference clock signal to the driving pulse generating unit54.

The recording unit64records various kinds of information related to the endoscope system1and data that is being processed. The recording unit64is formed by using a recording medium, such as a flash memory or a random access memory (RAM).

The input unit65receives various operations related to the endoscope system1. For example, the input unit65receives an input of an instruction signal that switches the type of the illumination light emitted by the light source device8. The input unit65is formed by using, for example, a cross switch or a push button.

The processor control unit66performs overall control of the units that form the endoscope system1. The processor control unit66is formed by using a central processing unit (CPU). The processor control unit66switches, in accordance with the instruction signal input from the input unit65, the illumination light emitted by the light source device8.

Configuration of the First Chip

In the following, a detailed configuration of the above described first chip21will be described.FIG. 3is a circuit diagram illustrating the configuration of the first chip21illustrated inFIG. 2. As illustrated inFIG. 3, the first chip21includes the timing generating unit25, an output unit31, constant current sources240, a vertical scanning unit241(row selection circuit), first sample hold units242, second sample hold units243, a horizontal scanning unit244(column selection circuit), and a horizontal reset unit245.

The timing generating unit25generates, based on the reference clock signal and the synchronization signal, various driving pulses (V control signal, ϕhclr, ϕSS, ϕNS, and ϕH) and outputs the driving pulses to each of the vertical scanning unit241, the first sample hold units242, the horizontal scanning unit244, and the horizontal reset unit245, which will be described later. The timing generating unit25simultaneously and externally outputs, by simultaneously driving the unit pixels230present in a plurality of rows adjacent in the vertical direction (column direction), each of the plurality of imaging signals that are output from the unit pixels230in the plurality of rows. In the first embodiment, the timing generating unit25functions as a control unit.

One end of the constant current source240is connected to the ground GND and the other end thereof is connected to a vertical transfer line239and a signal line to which a reference voltage Vbias is input is connected to the gate.

The vertical scanning unit241applies, based on the driving pulses (ϕX, ϕR, ϕT1, ϕT2, and the like) input from the timing generating unit25, each of a row selection pulse ϕX<M>, a driving pulse ϕR<M>, a driving pulse ϕT1<M>, and a driving pulse ϕT2<M> to the selected rows <M> (M=1, 2, . . . , and m) in the light-receiving unit23and drives each of the unit pixels230in the light-receiving unit23by the constant current sources240that are connected to the vertical transfer lines239, whereby the vertical scanning unit241transfers, by using the vertical transfer lines239(first transfer lines), the imaging signals and noise signals at the time of pixel reset and then outputs each of the noise signals and the imaging signals to the first sample hold units242. In the first embodiment, the imaging signals are read from two unit pixels230in a shared manner.

Each of the first sample hold units242(sample hold circuit) samples the noise signals at the time of pixel reset in each of the unit pixels230in the odd numbered rows and outputs the sampled noise signals to the output unit31. Furthermore, each of the first sample hold units242samples the imaging signals subjected to photoelectric conversion in each of the unit pixels230in the odd numbered rows and outputs the sampled imaging signals to the output unit31. Each of the first sample hold units242includes a first sampling switch251, a first sampling unit252(capacitor), a first output switch253, a second sampling switch254, a second sampling unit255, and a second output switch256.

One end of the first sampling switch251is connected to the vertical transfer line239(239a), the other end thereof is connected to one end of the first output switch253, and a signal line to which the driving pulse ϕNS is input from the timing generating unit25is connected to the gate.

One end of the first sampling unit252is connected between the first sampling switch251and the first output switch253and the other end thereof is connected to the ground GND. Each of the first sampling units252samples (holds) the noise signals received from the unit pixels230, in the case where the row selection pulse ϕX<M> and the driving pulse ϕR<M> are applied to the unit pixels230, when the driving pulse ϕNS is applied to the gate of each of the first sampling switches251.

One end of the first output switch253is connected to the first sampling switch251, the other end thereof is connected to a second horizontal transfer line260, and a column selection pulse ϕH<M> is input to the gate from the horizontal scanning unit244. When the column selection pulse ϕH<M> is applied to the gate, the first output switch253transfers the noise signals sampled by the first sampling unit252to the second horizontal transfer line260.

One end of the second sampling switch254is connected to the vertical transfer line239(239a), the other end thereof is connected to one end of the second output switch256, and a signal line to which the driving pulse ϕSS is input from the timing generating unit25is connected to the gate.

One end of the second sampling unit255is connected between the second sampling switch254and the second output switch256and the other end thereof is connected to the ground GND. The second sampling unit255samples (holds) the imaging signals received from the unit pixels230, in the case where the row selection pulse ϕX<M> and the driving pulse ϕT1<M> or the driving pulse ϕT2<M> are applied to the unit pixels230, when the driving pulse ϕSS is applied to the gate of the second sampling switch254.

One end of the second output switch256is connected to the second sampling switch254, the other end thereof is connected to a first horizontal transfer line259, and the column selection pulse ϕH<M> is input to the gate from the horizontal scanning unit244. When the column selection pulse ϕH<M> is applied to the gate, the second output switch256transfers the imaging signals sampled by the second sampling unit255to the first horizontal transfer line259.

The second sample hold units243(sample hold circuit) have the same configuration as those of the first sample hold units242, sample the noise signals at the time of pixel reset in each of the unit pixels230in the even numbered rows, and output the sampled noise signals to the output unit31. Furthermore, the second sample hold units243sample the imaging signals subjected to photoelectric conversion in each of the unit pixels230in the even numbered rows and output the sampled imaging signals to the output unit31. Each of the second sample hold units243includes a first sampling switch251a, a first sampling unit252a(capacitor), a first output switch253a, a second sampling switch254a, a second sampling unit255a, and a second output switch256a.

One end of the first sampling switch251ais connected to the vertical transfer line239(239b), the other end thereof is connected to one end of the first output switch253a, a signal line to which the driving pulse ϕNS is input from the timing generating unit25is connected to the gate.

One end of the first sampling unit252ais connected between the first sampling switch251aand the first output switch253aand the other end thereof is connected to the ground GND. The first sampling unit252asamples (holds) the noise signals received from the unit pixels230, in the case where the row selection pulse ϕX<M> and the driving pulse ϕR<M> are applied to the unit pixels230, when the driving pulse ϕNS is applied to the gate of the first sampling switch251a.

One end of the first output switch253ais connected to the first sampling switch251a, the other end thereof is connected to a fourth horizontal transfer line262, and the column selection pulse ϕH<M> is input to the gate from the horizontal scanning unit244. If the column selection pulse ϕH<M> is applied to the gate, the first output switch253atransfers the noise signals sampled by the first sampling unit252ato the fourth horizontal transfer line262.

One end of the second sampling switch254ais connected to the vertical transfer line239(239b), the other end thereof is connected to one end of the second output switch256a, a signal line to which the driving pulse ϕSS is input from the timing generating unit25is connected to the gate.

One end of the second sampling unit255ais connected between the second sampling switch254aand the second output switch256aand the other end thereof is connected to the ground GND. The second sampling unit255asamples (holds) the imaging signals received from the unit pixels230, in the case where the row selection pulse ϕX<M> and the driving pulse ϕT1<M> or the driving pulse ϕT2<M> are applied to the unit pixels230, when the driving pulse ϕSS is applied to the gate of the second sampling switch254a.

One end of the second output switch256ais connected to the second sampling switch254a, the other end thereof is connected to a third horizontal transfer line261, and the column selection pulse ϕH<M> is input to the gate from the horizontal scanning unit244. When the column selection pulse ϕH<M> is applied to the gate, the second output switch256atransfers the imaging signals sampled by the second sampling unit255ato the third horizontal transfer line261.

The horizontal scanning unit244applies, based on the driving pulse (ϕH) supplied from the timing generating unit25, the column selection pulse ϕH<M> to the selected columns <M> (M=1, 2, 3, . . . , and m) in the light-receiving unit23; transfers and outputs the noise signals received from each of the unit pixels230at the time of pixel reset in each of the unit pixels230to the first horizontal transfer line259via the first sample hold units242; and transfers and outputs the noise signals to the third horizontal transfer line261via the second sample hold units243. Furthermore, the horizontal scanning unit244applies, based on the driving pulse (ϕH) supplied from the timing generating unit25, the column selection pulse ϕH<M> in the selected column <M> in the light-receiving unit23; transfers and outputs the imaging signals subjected to photoelectric conversion by each of the unit pixels230to the second horizontal transfer line260via the first sample hold units242; and transfers and outputs the imaging signals to the fourth horizontal transfer line262via the second sample hold units243. Furthermore, in the first embodiment, the vertical scanning unit241and the horizontal scanning unit244function as the reading unit24.

A large number of the unit pixels230are arrayed in a two-dimensional matrix in the light-receiving unit23in the first chip21. Each of the unit pixels230includes a photoelectric conversion element231(photodiode) and a photoelectric conversion element232, a charge voltage converter233, a transfer transistor234(first transferring unit) and a transfer transistor235, a charge voltage converter reset unit236(transistor), a pixel source follower transistor237, and a pixel output switch238(signal output unit). Furthermore, in this application, one or a plurality of photoelectric conversion elements and transfer transistors for transferring the signal charge from each of the photoelectric conversion elements to the charge voltage converters233are referred to as a unit cell. Namely, a set of one or a plurality of photoelectric conversion elements and transfer transistors is included in the unit cell and a single unit cell is included in each of the unit pixels230. Furthermore, in the first embodiment, two pixels (the photoelectric conversion element231and the photoelectric conversion element232) are provided in each of the unit pixels230and are allowed to share the single vertical transfer line239(first transfer line); however, the embodiment is not limited to this. For example, four or eight pixels may also be allowed to share the single vertical transfer line239.

The photoelectric conversion element231and the photoelectric conversion element232perform photoelectric conversion on incident light to the signal charge level that is in accordance with the light level of the incident light and accumulate the signal charge. Regarding the photoelectric conversion element231and the photoelectric conversion element232, each of the cathode sides thereof is connected to one end of the transfer transistor234and the transfer transistor235and each of the anode side is connected to the ground GND. The charge voltage converter233is formed by floating diffusion capacitor (FD) and converts the charge accumulated by the photoelectric conversion element231and the photoelectric conversion element232to a voltage.

The transfer transistor234and the transfer transistor235transfer a charge from the photoelectric conversion element231and the photoelectric conversion element232, respectively, to the charge voltage converter233. A signal line through which the driving pulses ϕT1<M> and ϕT2<M> are supplied is connected to each of the gates of the transfer transistor234and the transfer transistor235and the charge voltage converter233is connected to the other end thereof. If the driving pulses ϕT1 and ϕT2 are supplied from the vertical scanning unit241via the signal lines, the transfer transistor234and the transfer transistor235enter the on state and transfer the signal charge from the photoelectric conversion element231and the photoelectric conversion element232, respectively, to the charge voltage converter233.

The charge voltage converter reset unit236resets the charge voltage converter233to a predetermined electric potential. One end of the charge voltage converter reset unit236is connected to the power supply voltage VDD, the other end thereof is connected to the charge voltage converter233, a signal line through which the driving pulse ϕR<M> is supplied is connected to the gate. If the driving pulse ϕR<M> is supplied from the vertical scanning unit241via the signal line, the charge voltage converter reset unit236enters the on state, emits the signal charge accumulated in the charge voltage converter233, and resets the charge voltage converter233to the predetermined electric potential.

One end of the pixel source follower transistor237is connected to the power supply voltage VDD, the other end thereof is connected to one end of the pixel output switch238, and a signal (image signal or signal at the time of reset) subjected to charge voltage conversion by the charge voltage converter233is input to the gate.

The pixel output switch238outputs the signal subjected to charge voltage conversion by the charge voltage converter233to the vertical transfer line239. The other end of the pixel output switch238is connected to the vertical transfer line239and a signal line through which the row selection pulse ϕX<M> is supplied is connected to the gate. If the row selection pulse ϕX<M> is supplied to the gate of the pixel output switch238from the vertical scanning unit241via the signal line, the pixel output switch238enters the on state and transfers an image signal or the signal (noise signal) at the time of reset to the vertical transfer line239.

The horizontal reset unit245resets, based on a driving pulse ϕhclr that is input from the timing generating unit25, each of the first horizontal transfer line259, the second horizontal transfer line260, the third horizontal transfer line261, and the fourth horizontal transfer line262. The horizontal reset unit245includes a first horizontal reset transistor271, a second horizontal reset transistor272, a third horizontal reset transistor273, and a fourth horizontal reset transistor274.

One end of the first horizontal reset transistor271is connected to the reference voltage VREF, the other end thereof is connected to the first horizontal transfer line259, a signal line to which the driving pulse ϕhclr is input from the timing generating unit25is connected to the gate. If the driving pulse ϕhclr is input from the timing generating unit25to the gate of the first horizontal reset transistor271, the first horizontal reset transistor271enters the on state and resets the first horizontal transfer line259.

One end of the second horizontal reset transistor272is connected to the reference voltage VREF, the other end thereof is connected to the second horizontal transfer line260, and a signal line to which the driving pulse ϕhclr is input from the timing generating unit25is connected to the gate. If the driving pulse ϕhclr is input from the timing generating unit25to the gate of the second horizontal reset transistor272, the second horizontal reset transistor272enters the on state and resets the second horizontal transfer line260.

One end of the third horizontal reset transistor273is connected to the reference voltage VREF, the other end thereof is connected to the third horizontal transfer line261, and the signal line to which the driving pulse ϕhclr is input from the timing generating unit25is connected to the gate. If the driving pulse ϕhclr is input from the timing generating unit25to the gate of the third horizontal reset transistor273, the third horizontal reset transistor273enters the on state and resets the third horizontal transfer line261.

One end of the fourth horizontal reset transistor274is connected to the reference voltage VREF, the other end thereof is connected to the fourth horizontal transfer line262, and the signal line to which the driving pulse ϕhclr is input from the timing generating unit25is connected to the gate. When the driving pulse ϕhclr is input from the timing generating unit25to the gate of the fourth horizontal reset transistor274, the fourth horizontal reset transistor274enters the on state and resets the fourth horizontal transfer line262.

By obtaining a difference between the noise signal and the imaging signal transferred from each of the first horizontal transfer line259to the fourth horizontal transfer line262, the output unit31externally outputs the imaging signal from which noise has been removed. The output unit31includes a first output amplification unit311and a second output amplification unit312.

The first output amplification unit311is formed by using a differential amplifier and externally outputs, by obtaining a difference between the imaging signals in the odd numbered columns transferred from the first horizontal transfer line259and the noise signals in the odd numbered columns transferred from the second horizontal transfer line260, the imaging signals that are in the odd numbered columns and from which noise has been removed (Vout1).

The second output amplification unit312is formed by using a differential amplifier and externally outputs, by obtaining a difference between the imaging signals in the even numbered columns transferred from the third horizontal transfer line261and the noise signals in the even numbered columns transferred from the fourth horizontal transfer line262, the imaging signals that are in the even numbered columns and from which noise has been removed (Vout2).

Operation of the Imaging Unit

In the following, a driving timing of the imaging unit20will be described.FIG. 4is a timing chart illustrating a driving timing of the imaging unit20according to the first embodiment.FIG. 4illustrates the timing of, in the order from the top, a row selection pulse ϕX<1>, a driving pulse ϕR<1>, a driving pulse ϕT1<1>, a driving pulse ϕT2<1>, a row selection pulse ϕX<2>, a driving pulse ϕR<2>, a driving pulse ϕT1<2>, a driving pulse ϕT2<2>, a driving pulse ϕNS, a driving pulse ϕSS, a column selection pulse ϕH, and a driving pulse ϕhclr.

As illustrated inFIG. 4, first, the timing generating unit25sets the row selection pulse ϕX<1> and the driving pulse ϕR<1> to the on state (High). Consequently, each of the charge voltage converter reset units236in the first row and the second row enters the on state, emits the signal charge accumulated in each of the charge voltage converters233in the first row and the second row, and resets each of the charge voltage converters233in the first row and the second row to a predetermined electric potential.

Subsequently, the timing generating unit25sets the driving pulse ϕR<1> to the off state (Low), sets the driving pulse ϕNS to the on state (High), allows the first sampling units252to sample the noise signals input from the charge voltage converters233in the first row via the vertical transfer lines239(239a), and allow the first sampling units252ato sample the noise signals input from the charge voltage converters233in the second row via the vertical transfer lines239(239b).

Then, the timing generating unit25sets the driving pulse ϕNS to the off state (Low). Consequently, the first sampling units252complete the sampling of the noise signals in the first row. Furthermore, the first sampling units252acomplete the sampling of the noise signals in the second row.

Subsequently, the timing generating unit25sets the driving pulse ϕT1<1> to the on state (High) and sets the driving pulse ϕSS to the on state (High). In this case, each of the transfer transistors234in the first row and the second row enters the on state due to the driving pulse ϕT1<1> being input to the gate from the timing generating unit25and then transfers the signal charge from each of the photoelectric conversion elements231to the charge voltage converters233in the odd numbered columns in the first row and the second row. At this time, each of the pixel output switches238in the first row outputs the imaging signals subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237to the vertical transfer lines239(239a), whereas each of the pixel output switches238in the second row outputs the imaging signals subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237to the vertical transfer lines239(239b). Furthermore, the second sampling units255sample the imaging signals in the odd numbered columns in the first row output from the vertical transfer lines239(239a), whereas the second sampling units255asample the imaging signals in the odd numbered columns in the second row output from the vertical transfer lines239(239b).

Then, after having set the driving pulse ϕSS to the off state (Low), the timing generating unit25sets the row selection pulse ϕX<1> to the off state (Low) and sequentially repeats, for each column, the on/off operation of the column selection pulse ϕH<M> and the driving pulse ϕhclr. In this case, each of the second sampling units255transfers the sampled imaging signals in the odd numbered columns in the first row to the first horizontal transfer line259and outputs the transferred imaging signals to the first output amplification unit311, whereas each of the first sampling units252transfers the sampled noise signals in the odd numbered columns in the first row to the second horizontal transfer line260and outputs the transferred noise signals to the first output amplification unit311. The first output amplification unit311outputs a difference between the imaging signals and the noise signals in the odd numbered columns in the first row, whereby the imaging signals, from which noise has been removed, in the odd numbered columns in the first row are output (Vout1).

Furthermore, each of the second sampling units255atransfers the sampled imaging signals in the odd numbered columns in the second row to the third horizontal transfer line261and outputs the transferred imaging signals to the second output amplification unit312, whereas each of the first sampling units252atransfers the sampled noise signals in the odd numbered columns in the second row to the fourth horizontal transfer line262and outputs the transferred noise signals to the second output amplification unit312. The second output amplification unit312outputs a difference between the imaging signals and the noise signals in the odd numbered columns in the second row, whereby the imaging signals, from which noise has been removed, in the odd numbered columns in the second row are output (Vout2).

Then, the timing generating unit25sets the row selection pulse ϕX<1> and the driving pulse ϕR<1> to the on state (High). Consequently, each of the charge voltage converter reset units236in the first row and the second row enters the on state, emits the signal charge accumulated in each of the charge voltage converters233in the first row and the second row, and resets each of the charge voltage converters233to a predetermined electric potential.

Subsequently, the timing generating unit25sets the driving pulse ϕR<1> to the off state (Low), sets the driving pulse ϕNS to the on state (High), allows the first sampling units252to sample the noise signals input from the charge voltage converters233in the first row via the vertical transfer lines239(239a), and allow the first sampling units252ato sample the noise signals input from the charge voltage converters233in the second row via the vertical transfer lines239(239b).

Then, the timing generating unit25sets the driving pulse ϕNS to the off state (Low). Consequently, the first sampling units252complete the sampling of the noise signals in the first row. Furthermore, the first sampling units252acomplete the sampling of the noise signals in the second row.

Subsequently, the timing generating unit25sets the driving pulse ϕT2<1> to the on state (High) and sets the driving pulse ϕSS to the on state (High). In this case, each of the transfer transistors235in the first row and the second row enters the on state due to the driving pulse ϕT2<1> being input to the gate from the timing generating unit25and then transfers the signal charge from each of the photoelectric conversion elements232in the even numbered columns in the first row and the second row to the charge voltage converters233. At this time, the pixel output switches238in the first row output the imaging signals that have been subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237in the first row to the vertical transfer lines239(239a), whereas the pixel output switches238in the second row outputs the imaging signals that have been subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237in the second row to the vertical transfer lines239(239b). Furthermore, each of the second sampling units255samples the imaging signals output from the vertical transfer lines239(239a), whereas each of the second sampling unit255asamples the imaging signals output from the vertical transfer lines239(239b).

Then, after having set the driving pulse ϕSS to the off state (Low), the timing generating unit25sets the row selection pulse ϕX<1> to the off state (Low) and sequentially repeats, for each column, the on/off operation of the column selection pulse ϕH<M> and the driving pulse ϕhclr. In this case, each of the second sampling units255transfers the sampled imaging signals in the even numbered columns in the first row to the first horizontal transfer line259and outputs the transferred imaging signals to the first output amplification unit311, whereas each of the first sampling units252transfers the sampled noise signals in the even numbered columns in the first row to the second horizontal transfer line260and outputs the transferred noise signals to the first output amplification unit311. The first output amplification unit311outputs a difference between the imaging signals and the noise signals in the even numbered columns in the first row, whereby the imaging signals, from which noise has been removed, in the even numbered columns in the first row are output (Vout1).

Furthermore, each of the second sampling units255atransfers the sampled imaging signals in the even numbered columns in the second row to the third horizontal transfer line261and outputs the transferred imaging signals to the second output amplification unit312, whereas each of the first sampling units252atransfers the sampled noise signals in the even numbered columns in the second row to the fourth horizontal transfer line262and outputs the transferred noise signals to the second output amplification unit312. The second output amplification unit312outputs the difference between the imaging signals and the noise signals in the even numbered columns in the second row, whereby the imaging signals, from which noise has been removed, in the even numbered columns in the second row are output (Vout2).

Subsequently, the timing generating unit25sets the row selection pulse ϕX<2> and the driving pulse ϕR<2> to the on state (High). Consequently, each of the charge voltage converter reset units236in the third row and the fourth row enters the on state, emits the signal charge accumulated in each of the charge voltage converters233in the third row and the fourth row, and resets each of the charge voltage converters233in the third row and the fourth row to a predetermined electric potential.

Subsequently, the timing generating unit25sets the driving pulse ϕR<2> to the off state (Low), sets the driving pulse ϕNS to the on state (High), allows the first sampling units252to sample the noise signals input from the charge voltage converters233in the third row via the vertical transfer lines239(239a), and allows the first sampling units252ato sample the noise signals input from the charge voltage converters233in the fourth row via the vertical transfer lines239(239b).

Then, the timing generating unit25sets the driving pulse ϕNS to the off state (Low). Consequently, the first sampling units252complete the sampling of the noise signals in the third row. Furthermore, the first sampling units252acomplete the sampling of the noise signals in the fourth row.

Subsequently, the timing generating unit25sets the driving pulse ϕT1<2> to the on state (High) and sets the driving pulse ϕSS to the on state (High). In this case, each of the transfer transistors234in the third row and the fourth row enters the on state due to the driving pulse ϕT1<2> being input to the gate from the timing generating unit25and then transfers the signal charge from the photoelectric conversion elements231in each of the odd numbered columns in the third row and the fourth row to the charge voltage converters233. At this time, the pixel output switches238in the third row output the imaging signals subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237to the vertical transfer lines239(239a), whereas the pixel output switches238in the fourth row outputs the imaging signals subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237to the vertical transfer lines239(239b). Furthermore, the second sampling units255sample the imaging signals output from the vertical transfer lines239(239a), whereas the second sampling units255asample the imaging signals output from the vertical transfer lines239(239b).

Then, after having set the driving pulse ϕSS to the off state (Low), the timing generating unit25sets the row selection pulse ϕX<2> to the off state (Low) and sequentially repeats, for each column, the on/off operation of the column selection pulse ϕH<M> and the driving pulse ϕhclr. In this case, each of the second sampling units255transfers the sampled imaging signals in the odd numbered columns in the third row to the first horizontal transfer line259and outputs the transferred imaging signals to the first output amplification unit311, whereas each of the first sampling units252transfers the sampled noise signals in the third row to the second horizontal transfer line260and outputs the transferred noise signals to the first output amplification unit311. The first output amplification unit311outputs a difference between the imaging signals and the noise signals in the odd numbered columns in the third row, whereby the imaging signals, from which noise has been removed, in the odd numbered columns in the third row are output (Vout1).

Furthermore, each of the second sampling units255atransfers the sampled imaging signals in the odd numbered columns in the fourth row to the third horizontal transfer line261and outputs the transferred imaging signals to the second output amplification unit312, whereas each of the first sampling units252atransfers the sampled noise signals in the fourth row to the fourth horizontal transfer line262and outputs the transferred noise signals to the second output amplification unit312. The second output amplification unit312outputs the difference between the imaging signals and the noise signals in the odd numbered columns in the fourth row, whereby the imaging signals, from which noise has been removed, in the odd numbered columns in the fourth row are output (Vout2).

Then, the timing generating unit25sets the row selection pulse ϕX<2> and the driving pulse ϕR<2> to the on state (High). Consequently, each of the charge voltage converter reset units236in the third row and the fourth row enters the on state, emits the signal charge accumulated in each of the charge voltage converters233in the third row and the fourth row, and resets the charge voltage converters233to the predetermined electric potential.

Subsequently, the timing generating unit25sets the driving pulse ϕR<2> to the off state (Low), sets the driving pulse ϕNS to the on state (High), allows the first sampling units252to sample the noise signals input from the charge voltage converters233in the third row via the vertical transfer lines239(239a), and allows the first sampling units252ato sample the noise signals input from the charge voltage converters233in the fourth row via the vertical transfer lines239(239b).

Then, the timing generating unit25sets the driving pulse ϕNS to the off state (Low). Consequently, the first sampling units252complete the sampling of the noise signals in the third row. Furthermore, the first sampling units252acomplete the sampling of the noise signals in the fourth row.

Subsequently, the timing generating unit25sets the driving pulse ϕT2<2> to the on state (High) and sets the driving pulse ϕSS to the on state (High). In this case, each of the transfer transistors235in the third row and the fourth row enters the on state due to the driving pulse ϕT2<2> being input to the gate from the timing generating unit25and then transfers the signal charge from the photoelectric conversion elements232in each of the even numbered columns in the third row and the fourth row to the charge voltage converters233. At this time, the pixel output switches238in the third row output the imaging signals subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237in the third row to the vertical transfer lines239(239a), whereas the pixel output switches238in the fourth row output the imaging signals subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237in the fourth row to the vertical transfer lines239(239b). Furthermore, the second sampling units255sample the imaging signals output from the vertical transfer lines239(239a), whereas the second sampling units255asample the imaging signals output from the vertical transfer lines239(239b).

Then, after having set the driving pulse ϕSS to the off state (Low), the timing generating unit25sets the row selection pulse ϕX<2> to the off state (Low) and sequentially repeats, for each column, the on/off operation of the column selection pulse ϕH<M> and the driving pulse ϕhclr. In this case, each of the second sampling units255transfers the sampled imaging signals in the even numbered columns in the third row to the first horizontal transfer line259and outputs the transferred imaging signals to the first output amplification unit311, whereas each of the first sampling units252transfers the sampled noise signals in the even numbered columns in the third row to the second horizontal transfer line260and outputs the transferred noise signals to the first output amplification unit311. The first output amplification unit311outputs a difference between the imaging signals and the noise signals in the even numbered columns in the third row, whereby the imaging signals, from which noise has been removed, in the even numbered columns in the third row are output (Vout1).

Furthermore, each of the second sampling units255atransfers the sampled imaging signals in the even numbered columns in the fourth row to the third horizontal transfer line261and outputs the transferred imaging signals to the second output amplification unit312, whereas each of the first sampling units252atransfers the sampled noise signals in the even numbered columns in the fourth row to the fourth horizontal transfer line262and outputs the transferred noise signals to the second output amplification unit312. The second output amplification unit312outputs the difference between the imaging signals and the noise signals in the even numbered columns in the fourth row, whereby the imaging signals, from which noise has been removed, in the even numbered columns in the fourth row are output (Vout2).

In this way, by controlling each of the vertical scanning unit241, the first sample hold units242, the second sample hold units243, the horizontal scanning unit244, and the horizontal reset unit245, the timing generating unit25simultaneously (in parallel) and alternately, between the odd numbered columns and the even numbered columns, outputs the imaging signals from each of the plurality of the unit pixels230that are located in two different rows.

According to the first embodiment described above, the timing generating unit25simultaneously drives the pixels in the plurality of rows adjacent in the row direction (vertical direction) and simultaneously (in parallel) outputs, to the first output amplification unit311and the second output amplification unit312, the plurality of imaging signals output from the pixels in these plurality of rows; therefore, the time needed to read the imaging signal from each of the unit pixels230may be reduced to half, and it is thus possible to implement a reduction in size and readout at high speed.

Furthermore, according to the first embodiment, by controlling each of the vertical scanning unit241, the first sample hold units242, the second sample hold units243, the horizontal scanning unit244, and the horizontal reset unit245, the timing generating unit25simultaneously (in parallel) and alternately outputs the imaging signals in the odd numbered columns and the even numbered columns from each of the plurality of the unit pixels230that are located in two different rows, which makes it possible to output the imaging signals at a low speed and thus implementing low electrical power consumption and saving transmission bands. Furthermore, because the imaging unit20may be driven with low electrical power consumption, it is possible to prevent the distal end101of the endoscope2from becoming high temperature.

Furthermore, in the first embodiment, the timing generating unit25, the first sample hold units242, the second sample hold units243, the horizontal reset unit245, and the output unit31are provided on the first chip21; however, these units may also be provided on the second chip22. Consequently, the size of the first chip21may be further reduced and the size of the imaging unit20(image sensor) may also be reduced.

Second Embodiment

In the following, a second embodiment according to the present disclosure will be described. In an endoscope system according to the second embodiment, the configuration of the first chip is different. Specifically, regarding the first chip21according to the first embodiment described above, the sample hold unit is provided in each of the vertical transfer lines239; however, in the second embodiment, a clamp hold unit is provided in each of the vertical transfer lines239. Furthermore, in the second embodiment, instead of the horizontal reset unit, each of amplifiers and sample hold units is provided in each of the horizontal transfer lines. In a description below, the configuration of the first chip according to the second embodiment will be described and then the operation of the imaging unit according to the second embodiment will be described. Furthermore, components that are identical to those in the endoscope system1according to the first embodiment are assigned the same reference numerals and descriptions thereof will be omitted.

Configuration of the First Chip

FIG. 5is a circuit diagram illustrating the configuration of a first chip according to a second embodiment. Instead of the first sample hold units242, the second sample hold units243, and the horizontal reset unit245in the first chip21according to the first embodiment described above, a first chip21aillustrated inFIG. 5includes first clamp hold units280, second clamp hold units280a, an amplifier290, and a sample hold unit300.

The first clamp hold units280are provided in the vertical transfer line239(239a) in the odd numbered columns. After having clamped the noise signal at the time of pixel reset in each of the unit pixels230, each of the first clamp hold units280removes noise by reading the imaging signal that has been subjected to photoelectric conversion by each of the unit pixels230and then outputs the imaging signal from which noise has been removed to the amplifier290. Each of the first clamp hold units280includes a third sampling unit281, a clamp switch282, a third sampling switch283, a fourth sampling unit284, and a third output switch285.

One end of the third sampling unit281is connected to the vertical transfer line239(239a) and the other end thereof is connected to the third sampling switch283. When the row selection pulse ϕX<M> and the driving pulse ϕR<M> are applied to the unit pixels230, by changing the driving pulse ϕCLP from the on state to the off state, the third sampling unit281clamps the noise signals received from the unit pixels230and then removes, by applying the row selection pulse ϕX<M> and the driving pulse ϕT1<M> or the driving pulse ϕT2<M> to the unit pixels230, the noise component of the imaging signals received from the unit pixels230.

The signal line through which the reference voltage VREF is supplied is connected to one end of the clamp switch282, the other end thereof is connected between the third sampling unit281and the third sampling switch283, and the signal line through which the driving pulse ϕCLP is supplied from the timing generating unit25is connected to the gate.

One end of the third sampling switch283is connected to the third sampling unit281, the other end thereof is connected to one end of the third output switch285, and the signal line through which the driving pulse ϕSH1is supplied from the timing generating unit25is connected to the gate.

One end of the fourth sampling unit284is connected to the ground GND and the other end thereof is connected between the third sampling switch283and the third output switch285. When the clamp switch282enters the on state, the fourth sampling unit284is reset to a predetermined electric potential by the reference voltage VREF.

One end of the third output switch285is connected to the third sampling switch283, the other end thereof is connected to a first horizontal transfer line259a, and the signal line through which the column selection pulse ϕH<M> is supplied from the horizontal scanning unit244is connected to the gate. When the column selection pulse ϕH<M> is applied to the gate, the third output switch285transfers, to the first horizontal transfer line259a, the imaging signals that are present in the odd numbered columns, that are sampled by the fourth sampling unit284, and from which noise has been removed.

The second clamp hold unit280ais provided in the vertical transfer line239(239b) in the even numbered columns. After having clamped the noise signal at the time of pixel reset performed in each of the unit pixels230, each of the second clamp hold units280aremoves noise by reading the imaging signal that has been subjected to photoelectric conversion by each of the unit pixels230and then outputs the imaging signal from which noise has been removed to the amplifier290. The second clamp hold unit280aincludes a third sampling unit281a, a clamp switch282a, a third sampling switch283a, a fourth sampling unit284a, and a third output switch285a.

One end of the third sampling unit281ais connected to the vertical transfer line239(239b) and the other end thereof is connected to the third sampling switch283a. When the row selection pulse ϕX<M> and the driving pulse ϕR<M> are applied to the unit pixels230, by changing the state of the driving pulse ϕCLP from the on state to the off state, the third sampling unit281aclamps the noise signals received from the unit pixels230and then removes, by applying the row selection pulse ϕX<M> and the driving pulse ϕT1<M> or the driving pulse ϕT2<M> to the unit pixels230, the noise component of the imaging signals received from the unit pixels230.

The signal line through which the reference voltage VREF is supplied is connected to one end of the clamp switch282a, the other end thereof is connected between the third sampling unit281aand the third sampling switch283a, and the signal line through which the driving pulse ϕCLP is supplied from the timing generating unit25is connected to the gate.

One end of the third sampling switch283ais connected to the third sampling unit281a, the other end thereof is connected to one end of the third output switch285a, and the signal line through which the driving pulse ϕSH1is supplied from the timing generating unit25is connected to the gate.

One end of the fourth sampling unit284ais connected to the ground GND and the other end thereof is connected between the third sampling switch283aand the third output switch285a. When the clamp switch282aenters the on state, the fourth sampling unit284ais reset to a predetermined electric potential by the reference voltage VREF.

One end of the third output switch285ais connected to the third sampling switch283a, the other end thereof is connected to a second horizontal transfer line260a, and the signal line through which the column selection pulse ϕH<M> is supplied from the horizontal scanning unit244is connected to the gate. When the column selection pulse ϕH<M> is applied to the gate, the third output switch285atransfers, to the second horizontal transfer line260a, the imaging signals that are present in the even numbered columns, that are sampled by the fourth sampling unit284a, and from which noise has been removed.

The amplifier290holds the imaging signals from which noise has been removed and that are input from the first horizontal transfer line259aor the second horizontal transfer line260aand then outputs the imaging signals from which noise has been removed to the sample hold unit300, while sequentially changing the on/off operation based on the driving pulse ϕAMP that is input from the timing generating unit25. The amplifier290includes a first amplifier switch291, a first amp capacitor292, a first operational amplifier293, a second amplifier switch294, a second amp capacitor295, and a second operational amplifier296.

One end of the first amplifier switch291is connected to the first horizontal transfer line259a, the other end thereof is connected to the sample hold unit300, and the signal line through which the driving pulse ϕAMP is supplied from the timing generating unit25is connected to the gate.

One end of the first amp capacitor292is connected between the first horizontal transfer line259aand the first amplifier switch291and the other end thereof is connected between the first amplifier switch291and the sample hold unit300.

The first horizontal transfer line259ais connected to the plus terminal section of the input side of the first operational amplifier293, the signal line through which the reference voltage VREF is supplied is connected to the minus terminal section on the input side, and the sample hold unit300is connected to the output side of the first operational amplifier293. Furthermore, an output of the first operational amplifier293is input, via the first amp capacitor292, to the plus terminal section of the input side of the first operational amplifier293.

One end of the second amplifier switch294is connected to the second horizontal transfer line260a, the other end thereof is connected to the sample hold unit300, and the signal line through which the driving pulse ϕAMP is supplied from the timing generating unit25is connected to the gate.

One end of the second amp capacitor295is connected between the second horizontal transfer line260aand the second amplifier switch294and the other end thereof is connected between the second amplifier switch294and the sample hold unit300.

the second horizontal transfer line260ais connected to the plus terminal section of the input side of the second operational amplifier296, the signal line through which the reference voltage VREF is supplied is connected to the minus terminal section on the input side, and the sample hold unit300is connected to the output side of the second operational amplifier296. Furthermore, an output of the second operational amplifier296is input, via the second amp capacitor295, to the plus terminal section of the input side of the second operational amplifier296.

The amplifier290configured in this way multiplies imaging signals held in the fourth sampling unit284and the fourth sampling unit284aby the gain that is determined by the ratio of the capacity values of the first amp capacitor292and the second amp capacitor295, the capacity values of the fourth sampling unit284and the fourth sampling unit284a, and the capacity values of the third sampling unit281and the third sampling unit281aand then outputs the results to the sample hold unit300.

The sample hold unit300holds the imaging signals input from the amplifier290and outputs the imaging signals to an output unit31abased on the driving pulse ϕSH2that is input from the timing generating unit25.

The sample hold unit300includes a fourth sampling switch301, a fifth sampling unit302, a fifth sampling switch303, and a sixth sampling unit304.

One end of the fourth sampling switch301is connected to the first operational amplifier293, the other end thereof is connected to a first output amplification unit311a, and the signal line through which the driving pulse ϕSH2is supplied from the timing generating unit25is connected to the gate.

One end of the fifth sampling unit302is connected to the ground GND and the other end thereof is connected between the fourth sampling switch301and the first output amplification unit311a.

One end of the fifth sampling switch303is connected to the second operational amplifier296, the other end thereof is connected to a second output amplification unit312a, and the signal line through which the driving pulse ϕSH2is supplied from the timing generating unit25is connected to the gate.

One end of the sixth sampling unit304is connected to the ground GND and the other end thereof is connected between the fifth sampling switch303and the second output amplification unit312a.

The output unit31aincludes the first output amplification unit311a, and the second output amplification unit312a. The first output amplification unit311aamplifies the imaging signals output from the fifth sampling unit302and externally outputs the amplified imaging signals (Vout1). The second output amplification unit312aamplifies the imaging signals externally output from the sixth sampling unit304and outputs the amplified imaging signals (Vout2).

Operation of the Imaging Unit

In the following, a driving timing of the imaging unit20will be described.FIG. 6is a timing chart illustrating a driving timing of the imaging unit20according to the second embodiment.FIG. 6illustrates the timing of, in the order from the top, the row selection pulse ϕX<1>, the driving pulse ϕR<1>, the driving pulse ϕT1<1>, the driving pulse ϕT2<1>, the row selection pulse ϕX<2>, the driving pulse ϕR<2>, the driving pulse ϕT1<2>, the driving pulse ϕT2<2>, a driving pulse ϕCLP, a driving pulse ϕSH1, a driving pulse ϕAMP, a column selection pulse ϕH<m>, and a driving pulse ϕSH2.

As illustrated inFIG. 6, first, while maintaining the driving pulse ϕCLP in the on state, the timing generating unit25sets the row selection pulse ϕX<1>, the driving pulse ϕR<1>, and the driving pulse ϕSH1to the on state (High). Consequently, each of the charge voltage converter reset units236in the first row and the second row enters the on state, emits the signal charge accumulated in each of the charge voltage converters233in the first row and the second row, and resets each of the charge voltage converters233in the first row and the second row to the predetermined electric potential.

subsequently, the timing generating unit25sets the driving pulse ϕR<1> to the off state (Low), allows the fourth sampling unit284to clamp the noise signals input from the charge voltage converters233in the first row via the vertical transfer lines239(239a) and the third sampling unit281, and allows the fourth sampling units284ato clamp the noise signals input from the charge voltage converters233in the second row via the vertical transfer lines239(239b) and the third sampling units281a.

Then, the timing generating unit25sets the driving pulse ϕCLP to the off state (Low). Consequently, the fourth sampling units284complete the clamping of the noise signals in the first row. Furthermore, the fourth sampling units284acomplete the clamping of the noise signals in the second row.

Subsequently, the timing generating unit25sets the driving pulse ϕT1<1> to the on state (High). In this case, each of the transfer transistors234in the first row and the second row enters the on state due to the driving pulse ϕT1<1> being input to the gate from the timing generating unit25and transfers the signal charge from each of the photoelectric conversion elements231to the charge voltage converters233in the odd numbered columns in the first row and the second row. At this time, each of the pixel output switches238in the first row outputs the imaging signals subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237to the vertical transfer lines239(239a), whereas each of the pixel output switches238in the second row outputs the imaging signals subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237to the vertical transfer lines239(239b). Furthermore, the third sampling units281complete noise removal of the imaging signals in the odd numbered columns in the first row output from the vertical transfer lines239(239a), whereas the third sampling units281acomplete noise removal of the imaging signals in the odd numbered columns in the second row output from the vertical transfer lines239(239b).

Then, after having set the driving pulse ϕSH1to the off state (Low), the timing generating unit25sets the row selection pulse ϕX<1> to the off state (Low), sets the driving pulse ϕCLP to the on state (High), and sequentially repeats, for each column, the on/off operation of the driving pulse ϕAMP, the column selection pulse ϕH<M>, and the driving pulse ϕSH2. In this case, each of the fourth sampling units284transfers, when the column selection pulse ϕH<M> is in the on state, the sampled imaging signals in the odd numbered columns in the first row to the first horizontal transfer line259aand outputs the transferred imaging signals to the first operational amplifier293. The fifth sampling unit302outputs the sampled imaging signals to the first output amplification unit311ain accordance with the on/off operation of the fourth sampling switch301. The first output amplification unit311aexternally outputs the imaging signals in the odd numbered columns in the first row input from the fifth sampling unit302(Vout1).

Furthermore, each of the fourth sampling units284atransfers, when the column selection pulse ϕH<M> is in the on state, the sampled imaging signals in the odd numbered columns in the second row to the second horizontal transfer line260aand outputs the transferred imaging signals to the second operational amplifier296. The sixth sampling unit304outputs the sampled imaging signals to the second output amplification unit312ain accordance with the on/off operation of the fifth sampling switch303. The second output amplification unit312aexternally outputs the imaging signals in the odd numbered columns in the second row input from the sixth sampling unit304(Vout2).

Subsequently, the timing generating unit25sets the row selection pulse ϕX<1>, the driving pulse ϕR<1>, and the driving pulse ϕSH1to the on state (High). Consequently, each of the charge voltage converter reset units236in the first row and the second row enters the on state, allows each of the charge voltage converters233in the first row and the second row to emit the signal charge, and resets each of the charge voltage converters233in the first row and the second row to a predetermined electric potential.

Then, the timing generating unit25sets the driving pulse ϕR<1> to the off state (Low), allows the fourth sampling units284to clamp the noise signals input from the charge voltage converters233in the first row via the vertical transfer lines239(239a) and the third sampling units281, and allows the fourth sampling units284ato clamp the noise signals input from the charge voltage converters233in the second row via the vertical transfer lines239(239b) and the third sampling units281a.

Then, the timing generating unit25sets the driving pulse ϕCLP to the off state (Low). Consequently, the fourth sampling units284complete the clamping of the noise signals in the first row. Furthermore, the fourth sampling units284acomplete the clamping of the noise signals in the second row.

Subsequently, the timing generating unit25sets the driving pulse ϕT2<1> to the on state (High). In this case, each of the transfer transistors235in the first row and the second row enters the on state due to the driving pulse ϕT2<1> being input to the gate from the timing generating unit25and transfers the signal charge from the photoelectric conversion elements232to the charge voltage converters233in each of the even numbered columns in the first row and the second row. At this time, the pixel output switches238in the first row output the imaging signal subjected to charge voltage conversion by the charge voltage converter233from the pixel source follower transistors237to the vertical transfer lines239(239a), whereas the pixel output switches238in the second row output the imaging signals subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237to the vertical transfer lines239(239b). Furthermore, the third sampling units281complete noise removal of the imaging signals in the even numbered columns in the first row output from the vertical transfer lines239(239a), whereas the third sampling units281acomplete noise removal of the imaging signals in the even numbered columns in the second row output from the vertical transfer lines239(239b).

Then, after having set the driving pulse ϕSH1to the off state (Low), the timing generating unit25sets the row selection pulse ϕX<1> to the off state (Low), sets the driving pulse ϕCLP to the on state (High), and sequentially repeats, for each column, the on/off operation of the driving pulse ϕAMP, the column selection pulse ϕH<M>, and the driving pulse ϕSH2. In this case, each of the fourth sampling units284transfers, when the column selection pulse ϕH<M> is in the on state, the sampled imaging signals in the even numbered columns in the first row to the first horizontal transfer line259aand outputs the transferred imaging signals to the first operational amplifier293. The fifth sampling unit302outputs the sampled imaging signals to the first output amplification unit311ain accordance with the on/off operation of the fourth sampling switch301. The first output amplification unit311aoutputs the imaging signals in the even numbered columns in the first row input from the fifth sampling unit302to an external unit (Vout1).

Furthermore, each of the fourth sampling units284aoutputs, when the column selection pulse ϕH<M> is in the on state, the sampled imaging signals in the even numbered columns in the second row to the second horizontal transfer line260aand outputs the transferred imaging signals to the second operational amplifier296. The sixth sampling unit304outputs the sampled imaging signals to the second output amplification unit312ain accordance with the on/off operation of the fifth sampling switch303. The second output amplification unit312aexternally outputs the imaging signals in the even numbered columns in the second row input from the sixth sampling unit304(Vout2).

Subsequently, the timing generating unit25performs the on/off operation of the row selection pulse ϕX<2>, the driving pulse ϕR<2>, the driving pulse ϕT1<2>, the driving pulse ϕT2<2>, the driving pulse ϕCLP, the driving pulse ϕSH1, the driving pulse ϕAMP, the column selection pulse ϕH, and the driving pulse ϕSH2. Consequently, after having output the imaging signals in the odd numbered columns in the third row and the fourth row to an external unit, the timing generating unit25allows the imaging signals in the even numbered columns to output outside.

In this way, by controlling each of the vertical scanning unit241, the first clamp hold units280, the second clamp hold units280a, the amplifier290, and the sample hold unit300, the timing generating unit25simultaneously and alternately outputs the imaging signals in the odd numbered columns and the even numbered columns from each of the plurality of the unit pixels230located in two different rows to an external unit.

According to the second embodiment described above, the timing generating unit25simultaneously drives the pixels in the plurality of rows adjacent in the row direction (vertical direction) and simultaneously (in parallel) outputs, to the first output amplification unit311aand the second output amplification unit312a, the plurality of imaging signals output from the pixels in these plurality of rows; therefore, the time needed to read the imaging signal from each of the unit pixels230may be reduced to half, and it is thus possible to implement a reduction in size and readout at high speed.

Third Embodiment

In the following, a third embodiment will be described. In an endoscope system according to the third embodiment, the configuration of the first chip is different from that described in the second embodiment. Specifically, in the first chip according to the third embodiment, the sample hold circuit is eliminated from a clamp hold circuit. In a description below, the configuration of the first chip according to the third embodiment will be described and then the operation of the imaging unit according to the third embodiment will be described. Furthermore, components that are identical to those in the endoscope system1according to the second embodiment are assigned the same reference numerals and descriptions thereof will be omitted.

Configuration of the First Chip

FIG. 7is a circuit diagram illustrating the configuration of a first chip according to a third embodiment. Instead of the first clamp hold units280and the second clamp hold units280ain the first chip21according to the second embodiment described above, a first chip21billustrated inFIG. 7includes first clamp hold units280cand second clamp hold units280d.

The first clamp hold units280care provided in the vertical transfer lines239(239a) in the odd numbered columns. The first clamp hold units280csample the imaging signals subjected to photoelectric conversion in each of the unit pixels230and then output the sampled imaging signals to the amplifier290. Each of the first clamp hold units280cincludes the third sampling unit281, the clamp switch282, and the third output switch285.

The second clamp hold units280dare provided on the vertical transfer lines239(239b) in the even numbered columns. The second clamp hold units280dsample the imaging signals subjected to photoelectric conversion in each of the unit pixels230and then output the sampled imaging signals to the amplifier290. The second clamp hold unit280aincludes the third sampling unit281a, the clamp switch282a, and the third output switch285a.

Operation of the Imaging Unit

In the following, a driving timing of the imaging unit20will be described.FIG. 8is a timing chart illustrating a driving timing of the imaging unit20according to the third embodiment.FIG. 8illustrates the timing of, in the order from the top, the row selection pulse ϕX<1>, the driving pulse ϕR<1>, the driving pulse ϕT1<1>, the driving pulse ϕT2<1>, the row selection pulse ϕX<2>, the driving pulse ϕR<2>, the driving pulse ϕT1<2>, the driving pulse ϕT2<2>, a driving pulse ϕCLP, the driving pulse ϕAMP, the column selection pulse ϕH, and the driving pulse ϕSH2.

As illustrated inFIG. 8, first, while maintaining the driving pulse ϕCLP in the on state, the timing generating unit25sets the row selection pulse ϕX<1> and the driving pulse ϕR<1> to the on state (High). Consequently, each of the charge voltage converter reset units236in the first row and the second row enters the on state, emits the signal charge accumulated in each of the charge voltage converters233in the first row and the second row, and resets each of the charge voltage converters233in the first row and the second row to the predetermined electric potential.

Subsequently, the timing generating unit25sets the driving pulse ϕR<1> to the off state (Low), allows internal nodes287in the first clamp hold units280cto clamp the noise signals input from the charge voltage converters233in the first row via the vertical transfer lines239(239a) and the third sampling unit281, and allows an internal node287ain the second clamp hold units280dto clamp the noise signals input from the charge voltage converters233in the second row via the vertical transfer lines239(239b) and the third sampling units281a. At this time, the timing generating unit25sets the driving pulse ϕAMP to the on state (High) and resets the input/output of the first operational amplifier293to the same electric potential.

Then, the timing generating unit25sets the driving pulse ϕCLP to the off state (Low) and sets the driving pulse ϕT1<1> to the on state (High). In this case, each of the transfer transistors234in the first row and the second row enters the on state due to the driving pulse ϕT1<1> being input to the gate from the timing generating unit25and transfers the signal charge from the photoelectric conversion elements231to the charge voltage converters233in each of the odd numbered columns in the first row and the second row. At this time, the pixel output switches238in the first row output the imaging signals subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237to the vertical transfer lines239(239a), whereas the pixel output switches238in the second row outputs the imaging signals subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237to the vertical transfer lines239(239b). Furthermore, each of the third sampling unit281performs noise removal of the imaging signals in the odd numbered columns in the first row output from the vertical transfer lines239(239a) and samples to the internal nodes287in the first clamp hold units280c, whereas each of the third sampling units281aperforms noise removal of the imaging signals in the odd numbered columns in the second row output from the vertical transfer lines239(239b) and samples to the internal nodes287ain the second clamp hold units280d.

Then, the timing generating unit25sets the row selection pulse ϕX<1> to the off state (Low), sets the driving pulse ϕCLP to the on state (High), and sequentially repeats, for each column, the on/off operation of the driving pulse ϕAMP, the column selection pulse ϕH<M>, and the driving pulse ϕSH2. In this case, each of the third sampling units281transfers, when the column selection pulse ϕH<M> is in the on state, the sampled imaging signals in the odd numbered columns in the first row to the first horizontal transfer lines259aand outputs the transferred imaging signals to the first operational amplifier293. The fifth sampling unit302outputs the sampled imaging signals to the first output amplification unit311ain accordance with the on/off operation of the fourth sampling switch301. The first output amplification unit311aexternally outputs the imaging signals in the odd numbered columns in the first row input from the fifth sampling unit302(Vout1).

Furthermore, each of the third sampling units281atransfers, when the column selection pulse ϕH<M> is the on state, the sampled imaging signals in the odd numbered columns in the second row to the second horizontal transfer line260aand outputs the transferred imaging signals to the second operational amplifier296. The sixth sampling unit304outputs the sampled imaging signals to the second output amplification unit312ain accordance with the on/off operation of the fifth sampling switch303. The second output amplification unit312aexternally outputs the imaging signals in the odd numbered columns in the second row input to the sixth sampling unit304(Vout2).

Subsequently, the timing generating unit25sets the row selection pulse ϕX<1> and the driving pulse ϕR<1> to the on state (High). Consequently, each of the charge voltage converter reset units236in the first row and the second row enters the on state, emits the signal charge accumulated in each of the charge voltage converters233in the first row and the second row, and resets each of the charge voltage converters233in the first row and the second row to the predetermined electric potential.

Then, the timing generating unit25sets the driving pulse ϕR<1> to the off state (Low), allows the internal nodes287in the first clamp hold units280cto clamp the noise signals input from the charge voltage converters233in the first row via the vertical transfer lines239(239a) and the third sampling units281, and allows the internal nodes287ain the second clamp hold units280dto clamp the noise signals input from the charge voltage converters233in the second row via the vertical transfer lines239(239b) and the third sampling units281a. At this time, the timing generating unit25sets the driving pulse ϕAMP to the on state (High) and resets the input/output of the first operational amplifier293to the same electric potential.

Then, the timing generating unit25sets the driving pulse ϕCLP to the off state (Low) and completes the clamping of the noise signals input from the charge voltage converters233in the first row via the vertical transfer lines239(239a). The clamping of the noise signals input from the charge voltage converters233in the second row via the vertical transfer lines239(239b) has been completed.

Subsequently, the timing generating unit25sets the driving pulse T2<1> to the on state (High). In this case, each of the transfer transistors235in the first row and the second row enters the on state due to the driving pulse ϕT2<1> being input to the gate from the timing generating unit25and transfers the signal charge from the photoelectric conversion elements232in each of the even numbered columns in the first row and the second row to the charge voltage converters233. At this time, the pixel output switches238in the first row output the imaging signals subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237to the vertical transfer lines239(239a), whereas the pixel output switches238in the second row outputs the imaging signal subjected to charge voltage conversion by the charge voltage converters233from the pixel source follower transistors237to the vertical transfer lines239(239b). Furthermore, each of the third sampling units281performs noise removal of the imaging signals in the even numbered columns in the first row output from the vertical transfer lines239(239a) and samples to the internal nodes287in the first clamp hold units280c, whereas each of the third sampling units281aperforms noise removal of the imaging signals in the even numbered columns in the second row output from the vertical transfer lines239(239b) and samples to the internal nodes287ain the second clamp hold units280d.

Subsequently, the timing generating unit25sets the row selection pulse ϕX<1> to the off state (Low), sets the driving pulse ϕCLP to the on state (High), and sequentially repeats, for each columns, the on/off operation of the driving pulse ϕAMP, the column selection pulse ϕH<M>, and the driving pulse ϕSH2. In this case, when the column selection pulse ϕH<M> is in the on state, each of the third sampling units281transfers the sampled imaging signals in the even numbered columns in the first row to the first horizontal transfer lines259aand outputs the transferred imaging signals to the first operational amplifier293. The fifth sampling unit302outputs, in accordance with the on/off operation of the fourth sampling switch301, the sampled imaging signal to the first output amplification unit311a. The first output amplification unit311aoutputs the imaging signal in the even numbered columns in the first row input from the fifth sampling unit302to an external unit (Vout1).

Furthermore, when the column selection pulse ϕH<M> is in the on state, each of the third sampling units281atransfers the sampled imaging signal in the even numbered columns in the second row to the second horizontal transfer line260aand outputs the transferred imaging signals to the second operational amplifier296. The sixth sampling unit304outputs, in accordance with the on/off operation of the fifth sampling switch303, the sampled imaging signals to the second output amplification unit312a. The second output amplification unit312aoutputs the imaging signals in the even numbered columns in the second row input from the sixth sampling unit304to an external unit (Vout2).

Subsequently, the timing generating unit25performs on/off operation of the row selection pulse ϕX<2>, the driving pulse ϕR<2>, the driving pulse ϕT1<2>, the driving pulse ϕT2<2>, the driving pulse ϕCLP, the driving pulse ϕAMP, the column selection pulse ϕH, and the driving pulse ϕSH2. Consequently, after having output the imaging signals in the odd numbered columns in the third row and the fourth row to an external unit, the timing generating unit25allows the imaging signals in the even numbered columns to output outside.

In this way, by controlling each of the vertical scanning unit241, the first clamp hold units280c, the second clamp hold units280d, the amplifier290, and the sample hold unit300, the timing generating unit25simultaneously and alternately outputs the imaging signals in the odd numbered columns and the even numbered columns from each of the plurality of the unit pixels230located in two different rows to an external unit.

According to the third embodiment described above, the timing generating unit25simultaneously drives the pixels in the plurality of rows adjacent in the row direction (vertical direction) and simultaneously (in parallel) outputs, to the first output amplification unit311aand the second output amplification unit312a, the plurality of imaging signals output from the pixels in these plurality of rows; therefore, the time needed to read the imaging signal from each of the unit pixels230may be reduced to half, and it is thus possible to implement a reduction in size and readout at high speed.

Fourth Embodiment

In the following, a fourth embodiment will be described. In an endoscope system according to the fourth embodiment, the configuration of the first chip is different from that described in the third embodiment. Specifically, the first chip according to the third embodiment includes a column amplifier in a clamp hold circuit. In a description below, the configuration of the first chip according to the fourth embodiment will be described and then the operation of the imaging unit according to the fourth embodiment will be described. Furthermore, components that are identical to those in the endoscope system1according to the third embodiment are assigned the same reference numerals and descriptions thereof will be omitted.

Configuration of the First Chip

FIG. 9is a circuit diagram illustrating the configuration of a first chip according to a fourth embodiment. Instead of the first clamp hold units280cand the second clamp hold units280din the first chip21baccording to the third embodiment described above, a first chip21cillustrated inFIG. 9includes third clamp hold units400and fourth clamp hold units410.

The third clamp hold units400are provided in the vertical transfer lines239(239a) in the odd numbered columns. Each of the third clamp hold units400samples the imaging signal subjected to photoelectric conversion by each of the unit pixels230, amplifies the sampled imaging signal, and outputs the amplified imaging signal to the amplifier290. Each of the third clamp hold unit400includes the third sampling unit281, the clamp switch282, the third output switch285, and a column amplifier286.

Each of the column amplifier286amplifies the imaging signals transferred from the vertical transfers line239(239a) in the odd numbered columns and outputs the amplified imaging signals to the amplifier290.

The fourth clamp hold units410are provided in the vertical transfer lines239(239b) in the even numbered columns. Each of the fourth clamp hold units410samples the imaging signals subjected to photoelectric conversion by each of the unit pixels230, amplifies the sampled imaging signals, and outputs the amplified imaging signals to the amplifier290. Each of the fourth clamp hold unit410includes the third sampling unit281a, the clamp switch282a, the third output switch285a, and a column amplifier286a.

Each of the column amplifiers286aamplifies the imaging signals transferred from the vertical transfer lines239(239b) in the even numbered columns and outputs the amplified imaging signals to the amplifier290.

Operation of the Imaging Unit

In the following, a driving timing of the imaging unit20will be described.FIG. 10is a timing chart illustrating a driving timing of the imaging unit20according to the fourth embodiment.FIG. 10illustrates the timing of, in the order from the top, the row selection pulse ϕX<1>, the driving pulse ϕR<1>, the driving pulse ϕT1<1>, the driving pulse ϕT2<1>, the row selection pulse ϕX<2>, the driving pulse ϕR<2>, the driving pulse ϕT1<2>, the driving pulse ϕT2<2>, the driving pulse ϕCLP, the driving pulse ϕAMP, the column selection pulse ϕH, and the driving pulse ϕSH2.

As illustrated inFIG. 10, the timing generating unit25performs the same operation as that described the third embodiment above (seeFIG. 8). Specifically, the timing generating unit25simultaneously and alternately outputs the imaging signals in the odd numbered columns and the even numbered columns from each of the plurality of the unit pixels230located in two different rows to an external unit while changing the on/off operation of the row selection pulse ϕX<1>, the driving pulse ϕR<1>, the driving pulse ϕT1<1>, the driving pulse ϕT2<1>, the row selection pulse ϕX<2>, the driving pulse ϕR<2>, the driving pulse ϕT1<2>, the driving pulse ϕT2<2>, the driving pulse ϕCLP, the driving pulse ϕAMP, the column selection pulse ϕH, and the driving pulse ϕSH2.

According to the fourth embodiment described above, the timing generating unit25simultaneously drives the pixels in the plurality of rows that are adjacent in the row direction (vertical direction) and simultaneously (in parallel) outputs the plurality of imaging signals output from the pixels in these plurality of rows to the first output amplification unit311aand the second output amplification unit312a; therefore, the time needed to read the imaging signal from each of the unit pixels230may be reduced to half, and it is thus possible to implement a reduction in size and readout at high speed.

Other Embodiments

Furthermore, in the embodiments, the endoscope inserted into a subject is used; however, for example, a capsule-type endoscope or an imaging device that captures a subject may also be used.

Furthermore, in the embodiments, the number of unit pixels that are allowed to share the vertical transfer line (the first transfer line) is two; however, the number of unit pixels is not limited to this. For example, shared pixels of 4 pixels or 8 pixels may also be used. In this case, the number of output amplifiers may also appropriately be provided in accordance with the number of shared pixels. Specifically, when four pixels are allowed to share a single vertical transfer line, the number of output amplifies to be provided is four (arrange four output channels).

In a description of the timing charts in the application, the relationship between before and after the processes performed at each Step is stated by using “first”, “then”, “subsequently”, and the like; however, the order of the processes needed to implement the present disclosure is not uniquely determined by the descriptions above. Specifically, the order of the processes in the timing charts described in the application may also be changed as long as processes do not conflict with each other.

According to the present disclosure, an advantage is provided in that it is possible to implement both a reduction in size and readout at high speed.