Single-ended output driver buffer

Circuits and related methods are provided for buffering reference voltages from noise associated with output driver transistors. In one example, an output driver buffer circuit includes an output driver transistor adapted to adjust an output voltage of an output pad. The circuit also includes a pre-driver circuit connected to a gate of the output driver transistor. The pre-driver circuit is adapted to receive a reference voltage to control the output driver transistor. The pre-driver circuit includes a precharged capacitor, a first switch adapted to connect the capacitor to the gate, and a second switch adapted to connect the reference voltage to the gate. The second switch is adapted to operate following a time period after the capacitor is connected to the gate. The capacitor is adapted to buffer noise associated with the output driver transistor during the time period.

TECHNICAL FIELD

Generally relates to driver circuitry and more specifically to providing reference voltages to output driver circuits.

BACKGROUND

Single-ended output driver circuits are often used to provide output signals at output pads of electronic devices. In this regard, output driver circuits typically includes drive transistors connected to output pads. Analog reference voltages applied to the gates of the drive transistors can facilitate precise control of the current delivered by the drive transistors and can be used to maintain drive strength (e.g., a constant 8 mA current drive) or adjust slew rates (e.g., faster or slower) of the drive transistors. These reference voltages are typically generated for distribution to a large group of output driver circuits.

Unfortunately, as the drive transistors switch to provide different voltages at the output pads, large amounts of noise can couple onto the gates of the drive transistors. This noise can disturb the global reference voltages to the point where they provide no control benefit to the drive transistors, or can even cause the driver transistors to malfunction.

One approach to reducing the effects of this noise involves the use of buffers such as source-follower amplifier stages or unity-gain buffers connected between the reference voltages and the driver transistors. These buffers typically consume a constant DC current (e.g., between approximately 200 μA and 2 mA per output driver), regardless of whether or not the driver transistors are switching. However, for implementations with large numbers of output drivers, the output buffers can significantly increase the current consumption of the output driver circuitry.

In a second approach, switches and delay elements may be used with the buffers to reduce the power consumed by the output buffers. In this second approach, delay elements may be used to power down the buffers after a time period during which most of the noise associated with a switching driver transistor has settled. For example, such switching may occur approximately 4 ns after a driver transistor has switched on. Switches may be used to directly connect the reference voltage to the driver transistors following this time period.

Although this second approach may reduce DC current consumption by the buffers to a period of approximately 4 ns (e.g., consuming approximately 1 mA to 3 mA depending on drive strength), additional layout area is required to implement the additional switches and delay elements. This can significantly increase the size of the output driver circuitry. For example, in one implementation, the output buffers may comprise approximately 232 square microns, and the switches and delay elements may comprise an additional approximately 950 square microns.

Accordingly, there is a need for an improved output driver circuit to buffer reference voltages provided to driver transistors that does not consume excessive current. In addition, there is also a need for an output driver circuit that performs such buffering without requiring a large chip area for implementation.

SUMMARY

In accordance with one embodiment of the present invention, an output driver buffer circuit includes a first output driver transistor adapted to adjust an output voltage of an output pad; and a first pre-driver circuit connected to a gate of the first output driver transistor and adapted to receive a first reference voltage to control the first output driver transistor, wherein the first pre-driver circuit comprises: a first capacitor adapted to be precharged to a first voltage, a first switch adapted to connect the first capacitor to the gate of the first output driver transistor, and a second switch adapted to connect the first reference voltage to the gate of the first output driver transistor following a first time period after the first capacitor is connected to the gate of the first output driver transistor, wherein the first capacitor is adapted to buffer noise associated with the first output driver transistor during the first time period.

In accordance with another embodiment of the present invention, a method of adjusting an output voltage of an output pad includes receiving a data signal; precharging a first capacitor to a first voltage; in response to the data signal transitioning from a first value to a second value, connecting the first capacitor to a gate of a first output driver transistor connected to the output pad; and connecting a first reference voltage to the gate of the first output driver transistor following a first time period after the first capacitor is connected to the gate of the first output driver transistor, wherein the first capacitor is adapted to buffer noise associated with the first output driver transistor during the first time period.

In accordance with another embodiment of the present invention, an output driver buffer circuit includes a first means for adjusting an output voltage of an output pad; a first means for buffering noise associated with the first adjusting means; a first means for connecting the first buffering means to the first adjusting means; and a first means for connecting a first reference voltage to the first adjusting means following a first time period after the first buffering means is connected to the first adjusting means.

DETAILED DESCRIPTION

FIG. 1illustrates a block diagram of a buffer system100in accordance with an embodiment of the invention. Buffer system100may be implemented as part of any appropriate device having single-ended output drivers. For example, in various embodiments, buffer system100may be included as part of the input/output (I/O) circuitry of an integrated circuit such as a programmable logic device (PLD) (e.g., such as a field programmable gate array (FPGA)), an application-specific integrated circuit (ASIC) or generic circuit, a peripheral component interconnect (PCI) compatible device, a low voltage CMOS (LVCMOS) device, or other types of devices.

As shown inFIG. 1, buffer system100includes a reference block110and an output driver block140. Reference block110includes a reference generation block115that provides bias signals pbias and nbias to amplifiers120and130. Using the bias signals, amplifiers120and130provide reference voltages pref and nref to output driver block140.

Capacitors160and170may be precharged (for example, to voltages approximately equal to a logic high voltage and ground, respectively) and selectively connected to gates184and188by switches162and172, respectively. In addition, reference voltages pref and nref, may be selectively connected to gates184and188of transistors182and186by switches164and174, respectively.

Transistor182may be used to pull output pad190up to a logic high voltage, and transistor186may be used to pull output pad190down to a logic low voltage. In this regard, reference voltage pref may be provided to gate184of transistor182to turn on transistor182in order to pull up output pad190to a logic high voltage, or reference voltage nref may be provided to gate188of transistor186to turn on transistor186in order to pull down output pad190to a logic low voltage, depending on the desired output voltage of output pad190.

Through the operation of switches162,164,172, and174, capacitors160and170can be used to buffer reference voltages pref and nref from noise disturbances caused by transistors182and186as output pad190transitions between low and high values corresponding, for example, to logic low and logic high voltages, respectively. For example, if output pad190is to be transitioned from a logic low voltage to a logic high voltage, transistor184may be turned on and capacitor160may be connected to gate184through switch162while switch164remains open for a brief time period. During this time period while switch162is closed and switch164is open, noise caused by the turning on of transistor182may be filtered by capacitor160. Following the time period, switch164may be closed to connect reference voltage pref to gate184with little or no noise disturbance to reference voltage pref.

Similarly, if output pad190is to be transitioned from a logic high voltage to a logic low voltage, transistor186may be turned on and capacitor170may be connected to gate188through switch172while switch174remains open for a brief time period. During this time period while switch172is closed and switch174is open, noise caused by the turning on of transistor186may be filtered by capacitor170. Following the time period, switch174may be closed to connect reference voltage nref to gate188with little or no noise disturbance to reference voltage nref.

Advantageously, each of capacitors160and170may consume very little current (for example, approximately 200-300 μA for a period of approximately 500-600 ps for each time output pad190toggles) and do not require large chip area to implement. As a result, noise associated with transistors180and188can be buffered with little impact on the power and chip area consumed by buffer system100.

FIG. 2illustrates a circuit diagram of a buffer system200in accordance with an embodiment of the invention. Buffer system200may be used, for example, to implement buffer system100ofFIG. 1previously described herein. As shown inFIG. 2, buffer system200includes a reference generator210, a data timer220, a pull-up pre-driver230, a pull-down pre-driver240, an output driver250, and an output pad260.

Reference generator210provides reference voltages pref and nref to pull-up pre-driver230and pull-down pre-driver240, respectively. In this regard, reference generator210may be used, for example, to implement reference block110ofFIG. 1previously described herein.

Data timer220receives a data signal (labeled “data”) to be provided to output pad260. The data signal may be received from any appropriate source. For example, in one embodiment where buffer system200is implemented as part of I/O circuitry of a PLD, the data signal may be provided by other portions of the PLD. In response to the data signal transitioning between low and high values (for example, corresponding to logic low and logic high voltages), data timer220provides a plurality of control signals (labeled “pg_charge,” “pg_pass1,” “upg_pass2,” and “pg_pullup”) to pull-up pre-driver230, and also provides a plurality of control signals (labeled “ng_charge,” “ng_ass1,” “ng_pass2,” and “ng_pulldown”) to pull-down pre-driver240.

Pull-up pre-driver230provides a plurality of control signals (labeled “pg1,” “pg2,” and “pg3”) to output driver250which may be used to switch pull-up transistors (for example, PMOS transistors) of output driver250. Similarly, pull-down pre-driver240provides a plurality of control signals (labeled “ng1,” “ng2,” and “ng3”) to output driver250which may be used to switch pull-down transistors (for example, NMOS transistors) of output driver250.

FIG. 3illustrates a reference voltage generator circuit300in accordance with an embodiment of the invention. Voltage generator circuit300may be used, for example, to implement reference generator210of buffer system200. As shown inFIG. 3, voltage generator circuit300provides various components that may be used to generate reference voltages pref and nref. In this regard, reference voltages pref and nref may be implemented as global reference voltages that are provided to one or more output driver circuits of a device including buffer system100.

FIG. 4illustrates a data timer circuit400in accordance with an embodiment of the invention. Data timer circuit400may be used, for example, to implement data timer220of buffer system200. As shown inFIG. 4, data timer circuit400provides various components that may be used to generate control signals pg_charge, pg_pass1, pg_pass2, and pg_pullup to be provided to pull-up pre-driver230, and also generate control signals ng_charge, ng_pass1, ng_pass2, and ng_pulldown to be provided to pull-down pre-driver240.

In this regard, data timer circuit400includes logic410to receive the data signal previously described inFIG. 2. Logic410provides the data signal to a voltage level shifter420which in turn provides a voltage-shifted version of the data signal to a non-overlapping clock generator430. Various signals generated by clock generator430in response to the data signal are provided to decoders440and460, and logic450and470to generate control signals to be provided to pull-up pre-driver230and pull-down pre-driver240.

Subcircuit570includes a capacitor510which has been implemented in the illustrated embodiment by a transistor with its source, drain, and substrate connected together to a reference voltage VCCO. However, different implementations of capacitor510may be used in other embodiments. Capacitor510is connected to transistors520and540at a node515. Node515may be precharged to a reference voltage, such as ground, through the operation of control signal pg_charge. In this regard, control signal pg_charge is provided to logic525which inverts the signal twice before providing it to a gate of transistor520. When control signal pg_charge is set to a logic high voltage, transistor520will turn on. Because a drain of transistor520is connected to ground (labeled inFIG. 5as “gndo”), node515will be pulled approximately to ground while transistor520is on.

Control signal pg1may be set to a logic high voltage in response to control signal pg_pullup. As shown inFIG. 5, control signal pg_pullup is received by logic535which inverts the signal three times before providing it to a gate of a transistor530as signal pg_pu1. When control signal pg_pullup is set to a logic high voltage, signal pg_pu1will be set to a logic low voltage causing transistor530to turn on. A source of transistor530is connected to reference voltage VCCO. Therefore, transistor530will operate to pull a node560up approximately to reference voltage VCCO while transistor530is on, causing control signal pg1to provide a logic high voltage. When control signal pg_pullup is set to a logic low voltage, signal pg_pu1will be set to a logic high voltage causing transistor530to turn off. While transistor530is off, it will no longer operate to pull up node560.

Capacitor510and node515may be selectively connected to node560through the operation of control signal pg_pass1. As shown inFIG. 5, control signal pg_pass1is received by logic545which inverts the signal twice before providing it to a gate of transistor540. When control signal pg_pass1is set to a logic low voltage, transistor540will remain turned off. As a result, capacitor510and node515will remain disconnected from node560. When control signal pg_pass1is set to a logic high voltage, transistor540will turn on to connect capacitor510and node515to node560.

Reference voltage pref may be selectively connected to node560through the operation of control signal pg_pass2. As shown inFIG. 5, control signal pg_pass2is received by logic555which inverts the signal twice before providing it to a gate of a transistor550. When control signal pg_pass2is set to a logic low voltage, transistor550will remain turned off. As a result, reference voltage pref will remain disconnected from node560. When control signal pg_pass2is set to a logic high voltage, transistor550will turn on to connect reference voltage pref to node560.

It will be appreciated that the various components of subcircuits580and590illustrated inFIG. 5may be operated in a similar manner to the above-described components of subcircuit570to provide control signals pg2and pg3, respectively, in response to control signals pg_charge, pg_pass1, pg_pass2, and pg_pullup.

Subcircuit670includes a capacitor610which has been implemented in the illustrated embodiment by a transistor with its source, drain, and substrate connected together to ground (labeled inFIG. 6as “gndo”). However, different implementations of capacitor610may be used in other embodiments. Capacitor610is connected to transistors620and640at a node615. Node615may be precharged to a reference voltage, such as a logic high voltage, through the operation of control signal ng_charge. In this regard, control signal ng_charge is provided to logic625which inverts the signal three times before providing it to a gate of transistor620as control signal ng_chrg1. When control signal ng_charge is set to a logic high voltage, control signal ng_chrg1will be set to a logic low voltage causing transistor620to turn on. Because a source of transistor620is connected to reference voltage VCCO, node615will be pulled approximately to reference voltage VCCO while transistor620is on.

Control signal ng1may be set to a logic low voltage in response to control signal ng_pulldown. As shown inFIG. 6, control signal ng_pulldown is received by logic635which inverts the signal twice before providing it to a gate of a transistor630. When control signal ng_pulldown is set to a logic high voltage, transistor630will turn on. A drain of transistor630is connected to ground. Therefore, transistor630will operate to pull a node660down approximately to ground while transistor630is on, causing control signal ng1to provide a logic low voltage. When control signal ng_pulldown is set to a logic low voltage, transistor630will turn off. While transistor630is off, it will no longer operate to pull down node660.

Capacitor610and node615may be selectively connected to node660through the operation of control signal ng_pass1. As shown inFIG. 6, control signal ng_pass1is received by logic645which inverts the signal twice before providing it to a gate of transistor640. When control signal ng_pass1is set to a logic low voltage, transistor640will remain turned off. As a result, capacitor610and node615will remain disconnected from node660. When control signal ng_pass1is set to a logic high voltage, transistor640will turn on to connect capacitor610and node615to node660.

Reference voltage nref may be selectively connected to node660through the operation of control signal ng_pass2. As shown inFIG. 6, control signal ng_pass2is received by logic655which inverts the signal twice before providing it to a gate of a transistor650. When control signal ng_pass2is set to a logic low voltage, transistor650will remain turned off. As a result, reference voltage nref will remain disconnected from node660. When control signal ng_pass2is set to a logic high voltage, transistor650will turn on to connect reference voltage nref to node660.

It will be appreciated that the various components of subcircuits680and690illustrated inFIG. 6may be operated in a similar manner to the above-described components of subcircuit670to provide control signals ng2and ng3, respectively, in response to control signals ng_charge, ng_pass1, ng_pass2, and ng_pulldown.

FIG. 7illustrates an output pad driver circuit700in accordance with an embodiment of the invention. Output pad driver circuit700may be used, for example, to implement output driver250of buffer system200.

As shown inFIG. 7, output pad driver circuit700includes pull-up transistors710,720, and730that receive control signals pg1, pg2, and pg3, respectively. Output pad driver circuit700also includes pull-down transistors740,750, and760that receive control signals ng1, ng2, and ng3, respectively. In addition, output pad driver circuit700includes an output pad780that may be used to implement, for example, output pad260of buffer system200.

Each of pull-up transistors710,720, and730have a source connected to reference voltage VCCO and a drain connected to a node770. Each of pull-down transistors740,750, and760have a source connected to ground gndo and a drain connected to node770. As shown, output pad780is also connected to node770.

The voltage of output pad780may be switched between a logic high voltage and a logic low voltage by pull-up transistors710,720, and730and pull-down transistors740,750, and760in response to control signals pg1, pg2, pg3, ng1, ng2, and ng3. In this regard, when control signals pg1, pg2, pg3are set to logic low voltages and control signals ng1, ng2, ng3are set to logic low voltages, pull-up transistors710,720, and730will turn on and pull-down transistors740,750, and760will turn off. As a result, pull-up transistors710,720, and730will operate to pull the voltage of output pad780up approximately to reference voltage VCCO.

When control signals pg1, pg2, pg3are set to logic high voltages and control signals ng1, ng2, ng3are set to logic high voltages, pull-up transistors710,720, and730will turn off and pull-down transistors740,750, and760will turn on. As a result, pull-down transistors740,750, and760will operate to pull the voltage of output pad780down approximately to ground.

The operation of various circuits described herein can be further understood with regard to the waveform plots shown inFIGS. 8-14. In this regard,FIGS. 8-10illustrate waveform plots800,900, and1000showing various signals and voltages associated with a low-to-high voltage transition at output pad280in accordance with an embodiment of the invention. For example,FIG. 8illustrates a waveform plot800showing control signals pg_charge, pg_pu1, pg_pass1, and pg_pass2used to implement a low-to-high voltage transition at output pad280. As previously discussed, data timer circuit400provides control signals pg_charge, pg_pullup, pg_pass1, and pg_pass2to pull-up pre-driver circuit500which may be used to implement pull-up pre-driver230. As also previously discussed, logic535of pull-up pre-driver circuit500inverts control signal pg_pullup to provide control signal pg_pu1.

FIG. 9illustrates a waveform plot900showing the data signal provided to data timer circuit400and a low-to-high voltage transition of output pad280.FIG. 10illustrates a waveform plot1000showing voltages of control signal pg1, reference voltage pref, and node515(labeled as “pcap1”) also during the low-to-high voltage transition of output pad280.

Each of control signals pg_charge, pg_pu1, pg_pass1, and pg_pass2are shown inFIG. 8transitioning between a logic low voltage of approximately 0V and a logic high voltage of approximately 3.25V. These transitions may be performed by data timer circuit400(and also by logic535in the case of control signal pg_pu1) in response to the data signal provided to data timer circuit400transitioning from a logic low voltage to a logic high voltage.

For example, as shown inFIG. 9, the data signal may transition from a logic low voltage to a logic high voltage approximately at time 5 ns. Prior to the low-to-high transition of the data signal, control signal pg_charge is initially set to a logic high voltage as shown inFIG. 8. During this time (e.g., prior to the low-to-high transition of the data signal), transistor520ofFIG. 5will be turned on by control signal pg_charge. As a result, node515(e.g., pcap1) will be pulled approximately to ground as shown inFIG. 10to precharge capacitor510.

Also during this time, control signal pg_pu1is set to a logic low voltage which causes transistor530ofFIG. 5to turn on. As a result, control signal pg1provided by node560is pulled up to a logic high voltage of approximately 3.25V as shown inFIG. 10. Control signals pg_pass1and pg_pass2are also set to logic low voltages during this time which cause transistors540and550, respectively of pull-up pre-driver circuit500to turn off. As a result, node515, capacitor510, and reference voltage pref will be disconnected from node560of pull-up pre-driver circuit500. Also during this time, reference voltage pref exhibits a voltage of approximately 1.5V as shown inFIG. 10.

Following the transition of the data signal from a logic low voltage to a logic high voltage as shown inFIG. 9, control signals pg_charge, pg_pu1, pg_pass1, and pg_pass2are switched by data timer circuit400and logic535. Initially, control signal pg_charge transitions from a logic high voltage to a logic low voltage, and control signal pg_pu1transitions from a logic low voltage to a logic high voltage. As a result, transistor520will turn off and no longer operate to precharge node515and capacitor510approximately to ground. In addition, transistor530will turn off and no longer operate to pull up node560and control signal pg1to a logic high voltage.

Following the switching of control signals pg_charge and pg_pu1, data timer circuit400switches control signal pg_pass1from a logic low voltage to a logic high voltage. As a result, transistor540will turn on and connect node515and capacitor510to node560.

Following a time period (for example, approximately 200 ps) after the switching of control signal pg_pass1, data timer circuit400switches control signal pg_pass2from a logic low voltage to a logic high voltage. As a result, transistor550will turn on and connect reference voltage pref to node560.

The effects of the above-described switching of control signals pg_charge, pg_pu1, pg_pass1, and pg_pass2are shown in waveform plots900and1000. For example, after the precharging of capacitor510and node515is interrupted (e.g., in response to control signal pg_charge turning off transistor520), and node560is no longer pulled to a logic high voltage (e.g., in response to control signal pg_pu1turning off transistor530), charge will transfer from capacitor510to node560until the voltage of node560equalizes. This causes the voltage at node515(e.g., pcap1) to rise and also causes the voltage at node560(e.g., control signal pg1) to fall as shown inFIG. 10. Capacitor510may be sized so that nodes515and560settle to a voltage approximately equal to reference voltage pref as shown inFIG. 10. In response to the change in voltage of control signal pg1, transistor710of output pad driver circuit700will turn on, causing the voltage of output pad280to rise as shown inFIG. 9.

It will be appreciated that prior to the switching of control signal pg_pass2from a logic low voltage to a logic high voltage, reference voltage pref remains disconnected from node560. In this regard, noise associated with the switching on of transistor710can be largely buffered by capacitor510. As a result, when reference voltage pref is later connected to the gate of transistor710(e.g., through node560and control signal pg1), reference voltage pref is disturbed very little as shown inFIG. 10.

It will be appreciated that subcircuits580and590of pull-up pre-driver circuit500may be operated in a similar manner as described above in order to buffer reference voltage pref from noise disturbances associated with transistors720and730, respectively.

FIGS. 11-13illustrate waveform plots1100,1200, and1300showing various signals and voltages associated with a high-to-low voltage transition at output pad280in accordance with an embodiment of the invention. For example,FIG. 11illustrates a waveform plot1100showing control signals ng_chrg1, ng_pulldown, ng_pass1, and ng_pass2used to implement a high-to-low voltage transition at output pad280. As previously discussed, data timer circuit400provides control signals ng_charge, ng_pulldown, ng_pass1, and ng_pass2to pull-down pre-driver circuit600which may be used to implement pull-down pre-driver240. As also previously discussed, logic625of pull-down pre-driver circuit600inverts control signal ng_charge to provide control signal ng_chrg1.

FIG. 12illustrates a waveform plot1200showing the data signal provided to data timer circuit400and a high-to-low voltage transition of output pad280.FIG. 13illustrates a waveform plot1300showing voltages of control signal ng1, reference voltage nref, and node615(labeled as “ncap1”) also during the high-to-low voltage transition of output pad280.

Each of control signals ng_chrg1, ng_pulldown, pg_pass1, and pg_pass2are shown inFIG. 11transitioning between a logic high voltage of approximately 3.25V and a logic low voltage of approximately 0V. These transitions may be performed by data timer circuit400in response to the data signal provided to data timer circuit400transitioning from a logic high voltage to a logic low voltage.

For example, as shown inFIG. 12, the data signal may transition from a logic high voltage to a logic low voltage approximately at time 10 ns. Prior to the high-to-low transition of the data signal, control signal ng_chrg1is initially set to a logic low voltage as shown inFIG. 11. During this time (e.g., prior to the high-to-low transition of the data signal), transistor620ofFIG. 6will be turned on by control signal ng_chrg1. As a result, node615(e.g., ncap1) will be pulled approximately to reference voltage VCCO (implemented in this embodiment as approximately 3.25V) as shown inFIG. 13to precharge capacitor610.

Also during this time, control signal ng_pulldown is set to a logic high voltage which causes transistor630ofFIG. 6to turn on. As a result, control signal ng1provided by node660is pulled down to a logic low voltage of approximately 0V as shown inFIG. 13. Control signals ng_pass1and ng_pass2are also set to logic low voltages during this time which cause transistors640and650, respectively of pull-down pre-driver circuit600to turn off. As a result, node615, capacitor610, and reference voltage nref will be disconnected from node660of pull-down pre-driver circuit600. Also during this time, reference voltage nref exhibits a voltage of approximately 1.0V as shown inFIG. 13.

Following the transition of the data signal from a logic high voltage to a logic low voltage as shown inFIG. 12, control signals ng_chrg1, ng_pulldown, ng_pass1, and ng_pass2are switched by data timer circuit400and logic625. Initially, control signal ng_chrg1transitions from a logic low voltage to a logic high voltage, and control signal ng_pulldown transitions from a logic high voltage to a logic low voltage. As a result, transistor620will turn off and no longer operate to precharge node615and capacitor610approximately to reference voltage VCCO. In addition, transistor630will turn off and no longer operate to pull down node660and control signal ng1to a logic low voltage.

Following the switching of control signals ng_chrg1and ng_pulldown, data timer circuit400switches control signal ng_pass1from a logic low voltage to a logic high voltage. As a result, transistor640will turn on and connect node615and capacitor610to node660.

Following a time period (for example, approximately 200 ps) after the switching of control signal ng_pass1, data timer circuit400switches control signal ng_pass2from a logic low voltage to a logic high voltage. As a result, transistor650will turn on and connect reference voltage nref to node660.

The effects of the above-described switching of control signals ng_chrg1, ng_pulldown, ng_pass1, and ng_pass2are shown in waveform plots1200and1300. For example, after the precharging of capacitor610and node615is interrupted (e.g., in response to control signal ng_chrg1turning off transistor620), and node660is no longer pulled to a logic low voltage (e.g., in response to control signal ng_pulldown turning off transistor630), charge will transfer from capacitor610to node660until the voltage of node660equalizes. This causes the voltage at node615(e.g., ncap1) to fall and also causes the voltage at node660(e.g., control signal ng1) to rise as shown inFIG. 13. Capacitor610may be sized so that nodes615and660settle to a voltage approximately equal to reference voltage nref as shown inFIG. 13. In response to the change in voltage of control signal ng1, transistor740of output pad driver circuit700will turn on, causing the voltage of output pad280to fall as shown inFIG. 12.

It will be appreciated that prior to the switching of control signal ng_pass2from a logic low voltage to a logic high voltage, reference voltage nref remains disconnected from node660. In this regard, noise associated with the switching on of transistor740can be largely buffered by capacitor610. As a result, when reference voltage nref is later connected to the gate of transistor740(e.g., through node660and control signal ng1), reference voltage nref is disturbed very little as shown inFIG. 13.

It will be appreciated that subcircuits680and690of pull-down pre-driver circuit600may be operated in a similar manner as described above in order to buffer reference voltage nref from noise disturbances associated with transistors750and760, respectively.

FIG. 14illustrates a waveform plot1400showing current flowing into capacitor610as it is precharged in accordance with an embodiment of the invention. In this example, capacitor610is sized to connect to the gate of a driver transistor that has been implemented to satisfy the LVCMOS 33-20 mA specification. As shown inFIG. 14, current flows into capacitor610over a period of approximately 600 ps and reaches a maximum current of approximately 220 μA. It will be appreciated that this corresponds approximately to the current previously described herein with regard to capacitors160and170of buffer system100. Capacitor510may be implemented in a similar manner and exhibit a current flow of similar magnitude when precharged.

Advantageously, the current shown inFIG. 14is significantly smaller than the current required by prior buffering techniques. For example, by way of comparison, prior source-follower buffers implemented with power save circuits may draw approximately 2 mA over a period of approximately 4 ns each time an output pad toggles.

Although particular embodiments of the invention have been described herein, additional embodiments are also contemplated. For example, in one embodiment, the slew rate of output pad280may be adjusted higher by implementing a low resistance connection between capacitor510and the gate of transistor710to create a fast slew rate where charge quickly transfers from capacitor510to the driver gate. Conversely, a high resistance connection between capacitor510and the gate of transistor710may be used to create a slow slew rate condition where the charge transfer occurs more slowly. The speed of the charge transfer affects how quickly the gate voltage of transistor710changes and therefore affects how quickly transistor710turns on which controls the slew rate of output pad280. Similar changes can be made to one or more of subcircuits580and590ofFIG. 5and subcircuits670,680, and690FIG. 6if desired in particular embodiments. Advantageously, such slew rate adjustments may be made without increasing the bias current traditionally used to perform such control for circuits employing source-follower or unity gain buffers.

As another example, although only a single capacitor510is connected to node515in the embodiment illustrated inFIG. 5, additional capacitors may selectively connected to node515(for example, through appropriate switches) in other embodiments to further tune the operation of buffer system200. In this regard, such additional capacitors may be switched in or out to fine tune the voltage at which the driver transistor gates settle (for example, gates of transistors710-760). Advantageously, such capacitors may be used to compensate for reference variations due to process, temperature, voltage supply levels, or other factors. Such capacitors may also be used to provide pre-emphasis or additional drive current prior to connecting reference voltages to gates of driver transistors. Similar changes can be made to one or more of subcircuits580and590ofFIG. 5and subcircuits670,680, and690FIG. 6if desired in particular embodiments.

In one embodiment, the various circuits described herein may be implemented using 65 nm CMOS technology. Alternatively, other implementations and/or other CMOS sizes may be used.

In view of the present disclosure, it will be appreciated that a buffer system implemented in accordance with various embodiments described herein may consume less current than prior buffering techniques. In addition, because of the short control signal switching times described herein, propagation delays between a data signal received by the buffer signal and voltage changes at an output pad can also be reduced. A buffer system as described in the embodiments set forth herein may also require less layout area than prior buffer systems. For example, in one embodiment, a buffer system as described herein may occupy an area of approximately 450 to 570 square microns.