Method of making MEMS wafers

A wafer level package for a MEMS device is made by bonding a MEMS wafer and a lid wafer together to form a hermetically sealed cavity. One or more vias filled with conductive or semiconductive material is etched one of the wafers to form one or more rods extending through the wafer. The rods provide electrical connection to components within the hermetically sealed cavity.

FIELD OF THE INVENTION

This invention relates to a method of making MEMS wafers, and in particular to a method of obtaining a hermetic seal while providing an electrical connection to components within the sealed wafer.

BACKGROUND OF THE INVENTION

The manufacture of Micro-Electro-Mechanical-Systems (MEMS), such as micro-gyroscopes, micro-accelerometers, resonant accelerometers, RF devices, RF resonators, micro-mirrors, micro-motors, micro-actuators and other such micro-devices integrating at least one moving and/or particular component operating under sub-atmospheric conditions creates a very serious challenge for packaging. The vast majority of MEMS-based devices require the encapsulation to be done before wafer dicing so as to protect against micro-contamination from particles and dicing slurry while the wafers are processed like a standard semiconductor chip, and avoid the need for dedicated equipment or processes for dicing, mounting and molding. Most MEMS-based gyroscopes, MEMS-based accelerometers, MEMS-based inertial sensors, MEMS-based RF switching devices, MEMS-based resonators and other such MEMS devices, which are susceptible to a reduction of performance due to gas-induced damping (reduction of Q-factor) or gas-induced degradation, are influenced by the hermeticity of the packaging.

A sealed package to encapsulate the moving and/or particular components in vacuum or in a controlled atmosphere in a sealed protection micro-cavity is necessary to ensure reliable operation.

This micro-cavity is typically fabricated using microelectronics fabrication technologies to produce, on the wafer itself, a hermetic wafer-level package over each one of the various MEMS devices present on the wafer. Various approaches have been proposed to generate such a sealed wafer-level package, of which only a few permit the fabrication of a truly hermetically sealed hermetic package.

SUMMARY OF THE INVENTION

The present invention provides a novel technique for producing hermetically sealed micro-cavities between a so called “LID wafer” and a so called “MEMS wafer” to control the micro-environment around the MEMS devices.

In accordance with the invention there is provide a method of making a MEMS device from two parts (normally a lid and MEMS body) which are subsequently hermetically sealed together comprising forming a least one via, and preferably an array of vias through one of the parts, made of a material such as silicon, depositing conductive material or semiconductive material, such as phosphorus doped amorphous silicon, in said vias to form rods, and subsequently joining said parts together, preferably using direct contact (such as silicon-silicon) bonding, to provide a sealed cavity with said one or more rods providing a conductive path to the cavity.

The conductive material can suitably be deposited by LPCVD (Low Pressure Chemical Vapor Deposition). Electrical contact can be made to components within the cavity through the one or more rods formed extending through the MEMS body. By forming the rods into arrays, the overall electrical resistance of the path to the cavity can be reduced.

Thus in one aspect the invention provides a method of making a wafer level package for a MEMS device including a MEMS wafer and a lid wafer bonded together to form a hermetically sealed cavity, comprising forming one or more vias filled with conductive or semiconductive material in one of said wafers to form one or more rods extending through said one wafer; and bonding said two wafers together to form a hermetically sealed cavity with said one or more rods providing electrical connection between one or more components within said cavity and a contact pad on an exposed face of said one wafer.

In another aspect the invention provides a method of making a wafer level package for a MEMS device, comprising etching deep vias into a first wafer from a front side thereof; filling said deep vias with conductive or semiconductive material to form rods; providing contact pads on exposed portions of said rods; providing seal rings on said first wafer; providing a second wafer with corresponding contact pads and seal rings; bonding said first and second wafers together to define a hermetically sealed cavity; exposing said rods from the backside of said wafer; and providing contact pads on said rods on the backside of said wafer; wherein said rods provide electrical connection through said first wafer to one or more components within said heremetically sealed cavity.

In yet another aspect the invention provides a MEMS device comprising a MEMS body containing MEMS components; a lid portion bonded to said MEMS body by seal rings to form a hermetically sealed cavity; and one or more conductive or semiconductive rods filling vias extending through the lid portion into the sealed cavity to provide electrical connection to one or more components within the sealed cavity.

In the semiconductive material phosphorus-doped amorphous silicon. Other suitable materials may be used.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The device accordance to the invention is made using a series of mask steps involving a photoresist masks.FIG. 1shows a cross section through a silicon substrate1that will form the lid wafer of a MEMS device. The lid wafer starts off as a 600 μm DSP (double sided polished)wafer.

In a first step, a first mask (not shown) is applied to the backside2of the substrate1to form notches10that will serve as alignment marks. The notches10are formed under locations where vias are to be formed on the front side of the wafer. They are subsequently used for alignment purposes when the two wafers are brought together, as shown inFIG. 10, to ensure proper alignment.

In a second step (FIG. 2) a photoresist mask3is applied to the front side4of the substrate1to pattern 4.0 μm via openings5. In a third step (FIG. 3), a deep reaction ion etch is performed to form the vias50extending 100 μm into the substrate1.

In a next step (FIG. 4), after stripping the mask3, a 1.0 μm thermal oxide layer6is applied over the front side4of the substrate such that it extends into the silicon substrate1to line the walls of the vias50. Next, as shown inFIG. 5, an LPCVD deposition is carried out to form an in-situ phosphorus doped amorphous silicon (ISPD) layer7, which extends into the deep vias50to form conductive rods51. This layer7is then reduced to a thickness of 1.0 μm by chemical mechanical polishing (CMP) as shown inFIG. 6. The CMP process removes the notches7aformed over the vias5.

Next, as shown inFIG. 7, a third mask is applied and patterned to create via pad mask regions9and seal pad mask regions11. A dry etch is then performed to remove the ISPD layer7except under the mask regions9and11(FIG. 8). The mask is then stripped away to expose via pads13and seal rings14(FIG. 9). The pads13and seal rings are aligned relative to the backside notches10.

The next step, shown inFIG. 10is to flip over the substrate1and align it to preformed MEMS silicon wafer15. This contains the MEMS components and has been preformed with seal rings16and pads17with cantilevered extensions17aextending into the MEMS cavity19. The pads and seal rings are formed on a thermal oxide layer18. The structure of the wafer15is formed in a similar manner to the structure of the body1.

Next, as shown inFIG. 11, the two parts, substrate1and MEMS wafer15are brought together so that the respective pads13,17, and seal rings14,16come together and form a pressure bond55formed by direct contact between the amorphous silicon contact pads and seal rings respectively.

Next, as shown inFIG. 12, the backside, which is now on top, of the flipped substrate1is ground away to expose the ends20of the rods51remote from the cavity19.

As shown inFIG. 13, the backgrinding is followed by the PECVD deposition of a SiO2layer21, to which a fourth mask22is applied (FIG. 14). The fourth mask22is patterned to expose contact regions23over the rods51. As shown inFIG. 15, the oxide layer21is etched away in the contact regions23to expose the ISDP material forming the rods51and the mask subsequently stripped away.

The next step, shown inFIG. 16, is to deposit a conductive layer24over the oxide layer21. In this embodiment, the conductive layer is a double layer consisting of a 0.1 μm TiW sublayer followed by a 0.5 μm AlCu sublayer. The separate sublayers are not shown in the Figure.

Next, as shown inFIG. 17, a fifth mask is applied and patterned to form contact regions25over the vias5. This is followed by a wet etch of the conductive layer24and subsequent stripping of the mask pad regions to expose the oxide layer31except in at the formed contacts26over the vias5.

In a next step, shown inFIG. 19, a 1.0 μm layer27of Ni(P) is deposited by electroless plating over the contacts26. Next, as shown inFIG. 20, a 0.1 μm layer28of Pd(P) is deposited by electroless plating over the layer27. In a final step, shown inFIG. 21, the structure is diced and prepared for flip-chip bonding onto an FGBA (Fine-Ball-Grid-Array). As noted inFIG. 21, while the seal rings provide a hermetic seal, it is not critical that the bond to contact pads connected to the rods be hermetic because the material fills the vias extending to the surface and thus effectively prevents leakage into the cavity.

It will be noted that while the bond between the pads and the seal rings is hermetic, the via itself does not have to be hermetically sealed because it is filled with the ISPD material which provides a conductive path to the contact17awithin the cavity30of the MEMS device.

EXAMPLE

In a particular embodiment, if we assume that the resistivity of the aSi(P) rods within the vias is 800 μohm-cm, each via is 4 μm diameter and 100 μm tall, the resistance of the rods from bottom to top is then 800 μohm-cm×100 μm)/(3.14×4 μm2)=63.7 ohm. Thus, a single via connecting the TiW/AlCu pad has a series resistance of about 65 ohm. An array of four vias (occupying an array of about 16 μm×16 μm) would have a resistance of 16 ohms, and an array of 64 vias (occupying an array of about 64 μm×64 μm) would have a resistance of 1 ohm.

A single via may be capped by a single 24 μm×24 μm sealing pad of aSi(P) (phosphorus doped amorphous silicon) underneath of the LID wafer and a single 10 μm×10 μm sealing and connecting pad of TiW/AlCu. An array of 4 vias would be capped by a single 20 μm×20 μm sealing pad of aSi(P) underneath of the LID wafer and a single 20 μm×20 μm sealing and connecting pad of TiW/AlCu. Thus, improved hermetic sealing, improved mechanical robustness and lower connection resistance are achieved.

An array of 64 vias would typically be capped by a single 72 μm×72 μm sealing PAD of aSi(P) underneath of the lid wafer and a single 72 μm×72 μm sealing and connecting pad of TiW/AlCu. Such an arrangement results in an excellent hermetic seal, excellent mechanical robustness, and less then about 1 ohm connection resistance.

It will thus be appreciated that increasing the number of rods forming an array reduces the resistance of the connection. For example, with an array of 64 rods, the resistance of the connection to the sealed cavity can be reduced to one ohm.

Many variations of the invention are possible in accordance with the spirit of the invention. It will be appreciated that different materials from those illustrated in the drawings, which are purely exemplary, can be employed. For example, the metallic contacts27shown inFIG. 19need to provide good electrical contact with the conductive material in the vias, but the actual composition is not critical. Any suitable metallic arrangement can be employed. Also, other methods of depositing the various materials can be employed.

Other features of the invention are lining the vias with an insulating material, such as SiO2, since the material forming the parts, such as silicon, may have some degree of conductivity, forming the rods in the lid wafer, flipping the lid wafer prior to bonding with the MEMS wafer, and etching back the flipped wafer after bonding to expose the rods prior to forming the contacts. One skilled in the art on looking at the exemplary Figures will appreciate that the underlying principles can be implemented in many different equivalent ways.

It should be noted that the resist, thermal oxide, and aSi(P) shown inFIGS. 3,4,6, and7, though not shown, will also be deposited on the back side of the wafer as well.

InFIG. 21, the beam17aof the MEMs device is electrically connected to the rod32through the bonded sealing rings, which are also made of phosphorus-doped amorphous silicon. Since the via is filled with amorphous silicon, the cavity30of the MEMS device is effectively sealed.