Solid-state image sensor

According to embodiments of the present invention, a solid-state image sensor has a semiconductor element substrate having a plurality of photo electric conversion elements, an interlaminar insulating film having wires, formed at a first surface of the semiconductor element substrate, a color filter having a plurality of dye films of a plurality of colors, formed at a second surface of the semiconductor element substrate, a micro lens array having a plurality of micro lenses, formed above the color filter, a plurality of inner lenses formed between the photoelectric conversion elements and the dye films, and a shroud that surrounds each of the inner lenses, formed above the second surface of the semiconductor element substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2012-146871, filed Jun. 29, 2012; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to solid-state image sensors.

BACKGROUND

Solid-state image sensors such as CCD image sensors and CMOS image sensors are used for various applications such as digital still cameras, video cameras, and surveillance cameras. Single plate type image sensors which obtain multiple color information with a single pixel array are entering mainstream use.

In recent years, development of backside-illumination image sensors, which capture light corresponding to a photographed or imaged object at the backside of the semiconductor substrate comprising the sensor substrate are being promoted.

DETAILED DESCRIPTION

The present disclosure is directed to improve the image quality of an image formed by image sensors.

In general, embodiments of the present disclosure will be explained below with reference to the figures. In the explanations below, elements containing the same functions and/or structures will be marked with identical symbols; duplicate explanations will be given if necessary.

A solid-state image sensor in the embodiments has a semiconductor element substrate having a plurality of photo electric conversion elements, an interlaminar insulating film having wires, formed at a first surface of the semiconductor element substrate, a color filter having a plurality of dye films of a plurality of colors, formed at a second surface of the semiconductor element substrate, a micro lens array having a plurality of micro lenses, formed above the color filter, a plurality of inner lenses formed between the photoelectric conversion elements and the dye films, and a visor or shroud that surrounds each of the inner lenses, formed above the second surface of the semiconductor element substrate.

First Embodiment

A solid-state image sensor and its manufacturing method according to a first embodiment will be explained with reference toFIG. 1throughFIG. 8.

A solid-state image sensor according to the first embodiment will be explained applyingFIG. 1throughFIG. 5.

FIG. 1is a schematic diagram of a layout of a chip of the solid-state image sensor (image sensor hereafter) according to the present embodiment.FIG. 2is a cross-sectional view of a schematic structure of the image sensor.

As shown inFIG. 1andFIG. 2, in an image sensor100of the present embodiment, pixel array120and peripheral circuit region125, in which the analog circuit and logic circuit that control the pixel array are formed, are arranged within a single semiconductor substrate (chip)150.

The pixel array120includes a plurality of unit cells UCs. The unit cells (unit cell regions) UCs are arranged within the pixel array120in a matrix form.

The unit cell UC includes a photoelectric convertor which converts light corresponding to photographic objects (exterior light) into electric signals. One single unit cell UC includes at least one photoelectric convertor. Pixels are formed using the photoelectric convertor.

An element isolation area (element isolating layer)9separates adjacent unit cells UCs as well as adjacent photoelectric convertors. Thus, a formation region of the single unit cell UC and the single photoelectric convertor is surrounded by the element isolation area9.

The photoelectric convertor is formed from, for example, a photodiode1. As shown inFIG. 2, the photodiode1is formed from at least one dopant layer within a semiconductor substrate150. The photodiode1photoelectrically converts light corresponding to an imaged object into electric signals (electrical charges, voltage), which corresponds to the intensity of the light received from the imaged object. The photodiode1may store electrical charges generated in the dopant layer in accordance with the light received.

A floating diffusion layer or node6, which is a dopant layer, is arranged within the semiconductor substrate150. The floating diffusion layer6functions to temporarily store charge output from the photodiode1through an electric field effect transistor2.

The electric field effect transistor2is arranged on the semiconductor substrate150and in a space between the photodiode1and the floating diffusion layer6. A Gate electrode21of the electric field effect transistor2is disposed above a channel region within the semiconductor substrate150, and a gate insulating film22is placed between the gate electrode21and the semiconductor substrate150.

The image sensor is comprised of the unit cell UC. The unit cell UC may include the other components in addition to the photodiode1, the floating diffusion layer6, and the transfer gate2, depending on the circuit structure of the image sensor. For instance, the unit cell UC may include electric field effect transistors, such as an amplifier transistor and a reset transistor, as a component.

FIG. 3shows an example of a circuit structure of the pixel array120and its neighboring circuit.

The unit cells UCs, positioned in a matrix form within the pixel array120, are arranged at intersections of a readout control line TRF and a vertical signal line VSL.

The unit cells UCs arranged in a row direction of the pixel array120are connected to the common readout control line TRF. The unit cells UCs arranged in a column direction of the pixel array120are connected to the common vertical signal line VSL.

For instance, a single unit cell UC includes four electric field effect transistors2,3,4,5to control a behavior of the unit cell UC and photodiode1. In the example shown inFIG. 3, the four electric field effect transistors2,3,4,5included in the unit cell UC comprise a transfer gate (read transistor)2, an amplifier transistor3, a reset transistor4, and an address transistor5. The electric field transistors2,3,4,5may be, for instance, N-channel MOS transistors.

The elements1,2,3,4,5within a single unit cell UC are connected as follows.

An anode of the photodiode1is for instance grounded. A cathode of the photodiode1is connected to the floating diffusion layer6through a current path of the transfer gate2.

The transfer gate2controls storing and transferring of signal charges that are photoelectrically converted by the photodiode1. A gate of the transfer gate2is connected to the readout control line TRF. One end of the current path of the transfer gate2is connected to the cathode of a photodiode1, and the other end of the current path of the transfer gate2is connected to the floating diffusion layer6.

The amplifier transistor3detects and amplifies the signal (electric potential) of the floating diffusion node6. A gate of the amplifier transistor3is connected to the floating diffusion node6. One end of the current path of the amplifier transistor3is connected to the vertical signal line VSL, and the other end of the current path of the amplifier transistor3is connected to one end of a current path of the address transistor5. The signal amplified by the amplifier transistor3is output to the vertical signal line VSL. The amplifier transistor3functions as a source follower.

The reset transistor4resets an electric potential of the floating diffusion node6, i.e., resets an amount of the signal charge stored in the floating diffusion node6. A gate of the reset transistor4is connected to a reset control line RST. One end of the current path of the reset transistor4is connected to the floating diffusion6, and the other end of the current path of the reset transistor4is connected to a power terminal135.

The address transistor5controls an activation of the unit cell UC. A gate of the address transistor5is connected to an address control line ADR. One end of the current path of the address transistor5is connected to the other end of the current path of the amplifier transistor3, and the other end of the current path of the address transistor5is connected to the power terminal135.

The power terminal135is connected to a drain power source, ground, or a unit cell formed in an optical black region, which has a standard electric potential.

In the present embodiment, a structure in which one pixel has a single unit cell UC that contains a single photodiode1will be defined as a 1 Pixel-1 Cell structure.

A vertical shift register133is connected to the readout control line TRF, the address control line ADR, and the reset control line RST. The vertical shift register133controls the electric potentials of the readout control line TRF, address control line ADR, and reset control line RST and controls and selects the unit cells UC within the pixel array120by row. The vertical shift register133outputs control signals (voltage pulses) to the control lines TRF, ADR, and RST in order to control on and off of the transistors2,4, and5.

An AD (analog-to-digital) conversion circuit131is connected to the vertical signal line VSL. The AD conversion circuit131includes processing unit (PUs)132to convert analog signals from the unit cell UC into digital signals, or to conduct a CDS (Corrected Double Sampling) processing of the signals from the unit cell UC.

A load transistor134is used to control a current supplied to the vertical signal line VSL. A gate of the load transistor134is connected to a selecting line SF. One end of the current path of the load transistor134is connected to one end of the current path of the amplifier transistor3through the vertical signal line. The other end of the current path of the load transistor134is connected to a control line DC.

Now, a single unit cell UC does not necessarily have the address transistor5. If the address transistor5is not provided within the unit cell UC, the other end of the current path of the reset transistor4is connected to the other end of the current path of the amplifier transistor3. If the unit cell UC does not have the address transistor5, the address signal line ADR is not provided.

The unit cell UC may have a circuit structure in which two or more pixels (photodiodes) are provided, such as a 2 Pixel-1 Cell structure, a 4 Pixel-1 Cell structure, and an 8 Pixel-1 Cell structure. In the unit cell (multiple pixel-1 cell structure) containing multiple photodiodes, more than two photodiodes shares a single floating diffusion6, a single reset transistor3, a single amplifier transistor4, and a single address transistor5. In the unit cell containing multiple photodiodes, each photodiode has one transfer gate. In addition, the unit cell formed from a single pixel contains a single pixel region, the unit cell formed from a plurality of pixels contain a plurality of pixel regions. In a Multipixel-1 Cell structure unit cell, the pixel regions in a single cell are isolated by the element isolation area9with each other. The pixel regions are arranged within the pixel array120.

As shown inFIG. 1andFIG. 2, the peripheral circuit region125is juxtaposed to the pixel array120within the semiconductor substrate150with an element isolation area (not designated by a reference number inFIG. 1) in between.

Within the peripheral circuit region125, circuits like the above-mentioned shift register133which controls the pixel array120and circuits like the AD conversion circuit131that process the signals provided from the pixel array120are disposed.

The peripheral circuit region125is electrically isolated from the pixel array120by the element isolation area. In order to dispose the peripheral circuit region125within the element isolation area, an element isolation insulating film91having, for example, an STI structure is embedded in the element isolation area.

The circuits within the peripheral circuit region125are formed from electric elements, such as an electric field effect transistor7, resistance element, and capacitance element. InFIG. 2, to simplify the illustration, only electric field effect transistor7is shown. InFIG. 2, although only a single field effect transistor is illustrated, a plurality of transistors are provided on the semiconductor substrate150to form the peripheral circuit.

For instance, within the peripheral circuit region125, the electric field effect transistor (e.g., MOS transistor)7is arranged at a well region159of the semiconductor substrate150. Within the well region159, two diffusion layers (dopant layers)73are provided. These two diffusion layers73function as a source and a drain of the transistor7. A gate electrode71is provided above the surface of the well region159(channel region) and above a space between the two diffusion layers73. Agate insulating film72is provided between the gate electrode71and the well region159. Thus, the electric field effect transistor7is formed at the well region159.

In addition, whether the electric field effect transistor7is of P-channel-type or N-channel-type will depend on the conductivity types of the well region159, where the transistor7is disposed and of the diffusion layer73, which acts as the source/drain.

A single-crystal silicon substrate (bulk substrate) or an epitaxial silicon layer of SOI substrate is used for the semiconductor substrate150.

A plurality of interlaminar insulating films92are laminated on the semiconductor substrate150covering the gate electrodes21of the transistors2, the gate electrodes71of the transistors7, and the upper surfaces of the photodiodes1. Silicon oxide is used for the interlaminar insulating films92.

Multilayer wiring technology is used for the image sensor100of the present embodiment. That is, within the laminated interlaminar insulating films92, a plurality of wirings80are disposed on a plurality of wiring levels (i.e., heights from the substrate surface, which is set as the standard). A single wiring80is electrically connected to other wiring disposed on different wiring levels by via plugs81, which are embedded within the interlaminar insulating films92. Also, the wirings80contain a dummy layer that is not connected to the components and circuits (e.g., a shading film).

The gate electrodes21and71, the source/drain73, and terminals of electric elements formed on the semiconductor substrate150are connected to the wirings80within the interlaminar insulating films92through contact plugs CP1and CP2. Thus, the wirings80disposed on a lower layer and on an upper layer and the via plugs81embedded within the interlaminar insulating films92connect the electric elements placed on the semiconductor substrate150. Multilayer wiring technology is used in this manner to form the circuits.

In the present embodiment, a face on which the electric elements are formed, to be more specific, a face of the semiconductor substrate150on which the gate electrodes21and71are disposed, is called a front surface (a first surface) of the semiconductor substrate150. The interlaminar insulating films92and the wirings80formed by the multilayer wiring technology are disposed on the front surface of the semiconductor substrate150. A face opposing the front surface (opposite face to the front surface) of the semiconductor substrate150in the perpendicular direction to the surface of semiconductor substrate150is called a back surface (a second surface). If the front and the back surfaces of the semiconductor substrate150are not distinguished, the front and the back surfaces of the semiconductor substrate150will be called a principal surface of the semiconductor substrate150.

A via88A is formed within the semiconductor substrate150penetrating through from the front surface to the back surface of the semiconductor substrate150by methods such as TSV (Through Substrate Via) technology. The via88A is embedded in a through hole (opening) formed within the semiconductor substrate150. An insulating layer98A is formed on an interior surface of the through hole, and thus the via88A is electrically isolated from the semiconductor substrate150by the insulating layer98A.

The via88A is connected to the wiring80within the interlaminar insulating films92through the contact plug CP2. The via88A is also connected to a pad (electrode)99formed at the back surface of the semiconductor substrate150through a via plug88B. The pad99is disposed on an insulating layer95(a flattening layer or a protective film) that is formed on the back surface of the semiconductor substrate150. Thus the pad99is isolated from the semiconductor substrate150by an insulating layer95.

In the present embodiment, as shown inFIG. 2, a color filter is disposed at the back surface side of the semiconductor substrate150, overlying a protective layer (not shown) or adhesion layer (not shown) disposed therebetween. The color filter118is placed below, and in registration with, the pixel array120at the back surface of the semiconductor substrate150. For instance, the image sensor100in the present embodiment is a single-plate-type image sensor. The single plate type image sensor obtains image information concerning multiple colors (wavelengths of light) from a pixel array120. The color filter118contains a plurality of dye films that correspond with the colors (wavelengths).

A micro lens array117is disposed below the color filter118, between which a protective layer (not shown) or an adhesion layer (not shown) is disposed. The micro lens array117is placed below and in registration with the pixel array120in the perpendicular direction to the principal surface of the semiconductor substrate150. Specifically, the micro lens array117has a plurality of micro lenses that are arranged in two dimensions such that each micro lens corresponds to a single pixel (a single photodiode1). Each micro lens concentrates the light from the photographic object onto a photodiode1.

In the image sensor100of the present embodiment, the micro lens array117and the color filter118are disposed at the side of the semiconductor substrate150(i.e., the back surface) opposite to the side where the gate electrodes21,71of transistors2,7and the interlaminar insulating film are formed (i.e., the front surface). Thus, the semiconductor substrate150, on which the electric elements are formed, is disposed between the interlaminar insulating films92and the micro lens array117.

Light from imaged objects are illuminated onto the pixel array120from the back surface side of the semiconductor substrate150through the micro lens array117and the color filter118and the light entering the microlens array is then captured by the photodiodes1.

A supporting substrate119is placed above the interlaminar insulating film92. The supporting substrate119is disposed above the uppermost interlaminar insulating film92, between which a protective layer (not shown) and an adhesion layer (not shown) are disposed. A silicon substrate or insulating substrate may be used for the supporting substrate119.

In the present embodiment, a surface receiving the light from the photographic objects (an illuminated surface) is the back surface of the semiconductor substrate150, where the micro lens array117is disposed. Like the image sensor100in the present invention, image sensors that are structured so that light from the back surface side of semiconductor substrate150is illuminated to the pixel1are called backside-illumination image sensors.

As shown inFIG. 2, the backside-illumination image sensor100of the present embodiment contains a plurality of inner lenses31, which are placed between the micro lens array117and the photodiodes1in the perpendicular direction to the principal surface of the semiconductor substrate150. A plurality of visors32are placed adjacent to the inner lenses31at the back surface of the semiconductor substrate150.

UsingFIG. 4andFIG. 5, the structure of the inner lenses31and the visors32of the backside-illumination image sensor100of the present embodiment will be explained in detail.FIG. 4shows a planar layout of the pixel array120of the backside-illumination image sensor100of the present embodiment.FIG. 5shows a cross-sectional structure of a 3 by 3 pixel array120of the backside-illumination image sensor100of the present embodiment, it being understood that in an actual device greater or fewer pixels may also be present.

InFIG. 5, in order to clarify the illustration, only the photodiode1, transfer gate2, and floating diffusion6are illustrated for the electric elements included in a unit cell UC. Additionally, the interlaminar insulating film, wirings, and supporting substrate at the front surface side of the semiconductor substrate150schematically shown as wirings80, it being understood that the structure shown inFIG. 5for the wirings80and film layers underlying (opposed to the lenses) have the structure thereof shown inFIG. 2. Also, inFIG. 5the position of the substrate and devices are inverted in comparison toFIG. 2.

As shown inFIG. 4andFIG. 5, the photodiode1, the transfer gate2, and the floating diffusion6are formed within an element formation region (active region), which is partitioned by an element isolation layer90that includes a dopant.

The photodiodes1are arranged in registration with the plurality of micro lenses in the perpendicular direction to the principal surface of the semiconductor substrate150.

If the dopant layer10in which the photodiode1is formed is within a P-type semiconductor substrate (semiconductor layer)150, dopant of the dopant layer10is n-type.

InFIG. 5, in order to simplify the illustration, only a single N-type dopant layer10is illustrated as a component of the photodiode1. However, to improve the characteristic of the photodiode1(e.g., sensitivity and photoelectric conversion efficiency), a plurality of N-type and P-type dopant layers that differ in the concentration of the dopant may be laminated in the depth direction of the semiconductor substrate150within the formation region of the photodiode1(i.e., a photodiode formation region).

The floating diffusion node6is formed in the semiconductor substrate150and separated from the photodiode1. The transfer gate2is formed below a space between the floating diffusion6and the transfer gate2. The photodiode1and floating diffusion6node are arranged in a channel longitudinal direction of the transfer gate2, i.e., extending inwardly and outwardly of the view of the device inFIG. 5.

The floating diffusion6node is an N-type dopant layer formed within the semiconductor substrate150. For instance, the concentration of the N-type dopant in the N-type dopant layer60is greater than the concentration of the N-type dopant in the N-type dopant layer10.

The transfer gate2is located on the semiconductor substrate150intermediate of the location of the photodiode1and the floating diffusion6node in the substrate150. The gate electrode21of the transfer gate2is formed below the semiconductor substrate150, between which the gate insulating film22is formed. The N-type dopant layer10and the N-type dopant layer60forming the floating diffusion node6function as a source and a drain of the transfer gate2. The semiconductor substrate region located between the two N-type dopant layers10and60within the semiconductor substrate150constitutes a channel region of the transfer gate2.

At the front surface of the semiconductor substrate150, a front surface shield layer19is formed within the N-type dopant layer10. The front surface shield layer19is, for example, a P-type dopant layer. The front surface shield layer19is formed so as to be isolated from the channel region of the transfer gate132. The upper surface (the lower side inFIG. 5) of the front surface shield layer19is in contact with the interlaminar insulating film92.

A back surface shield layer18is formed within the semiconductor substrate150, at the back surface of the semiconductor substrate150. The Back surface shield layer18may be in contact with the N-type dopant layer10. The Back surface shield layer18is, for example, a P-type dopant layer.

A dark current generated on the photodiode1may be controlled by the back surface and the front surface shield layers18,19.

As shown inFIG. 4andFIG. 5, inner lenses31are disposed between the micro lens array117and the photodiodes1at the back surface of the semiconductor substrate150. The inner lenses31are formed from transparent materials. For instance, the inner lenses31are formed from silicon oxides (SiO2), silicon nitrides (Si3N4), silicon oxynitrides, or organic materials. The inner lenses31are arranged at the back surface of the semiconductor substrate150in a matrix form, and each inner lens31corresponds to a single photodiode1. The inner lens31provides an optical waveguide from the micro lens ML to the photodiode1. InFIG. 5the surface of the inner lens31on the side of the micro lens ML is flat. However, the surface of the inner lens31on the side of the micro lens ML may be a curved surface (spherical surface) as well.

For instance, with respect to the dimension in the parallel direction to the principal surface of the semiconductor substrate150, a maximum size L1of the inner lens31is smaller than a maximum size L2of the micro lens ML.

The visors or shrouds32are formed so as to surround the inner lenses31in the parallel direction to the principal surface of the semiconductor substrate150. Thus the shrouds are formed between the adjacent inner lenses31arranged in the parallel direction to the principal surface of the semiconductor substrate150. Thus, the shrouds32are adjacent to the inner lenses31. In the perpendicular direction to the principal surface of the semiconductor substrate150, the height or thickness of the shrouds32at the side of the micro lens shroud is same as the height or thickness of the inner lenses31extending from the adjacent surface of the semiconductor substrate150at the side of the micro lens.

The shrouds32in the present embodiment are formed from materials that have a property of absorbing or reflecting light (e.g., visible light). However, the shrouds32and inner lenses31are arranged, with respect to the photodiodes1, such that the light receiving surface of the photodiodes1at the back surface of the semiconductor substrate150are not covered by the shrouds32and are thus exposed to light passing through the micro lens array117through the inner lenses31.

The shrouds32are positioned to overlie and thus block, from light entering the microlens array117, the element isolation layer90, transfer gate2, and floating diffusion node6in the perpendicular direction to the principal surface of the semiconductor substrate150. Thus, the shroud32covers the element isolation layer90, transfer gate2, and floating diffusion6at the back surface of the semiconductor substrate150. In addition, the shrouds32may cover the edge of the photodiodes1in the parallel direction to the principal surface of the semiconductor substrate150. In terms of the planar shape of each shroud32, the corners may be rounded or chamfered.

The color filter118having discrete and different wavelength absorbing and transmitting properties among individual filter elements F1, F2and F3thereof, is disposed to overlie the insulating film95which overlies the inner lenses31and the shrouds32at the back surface side of the semiconductor substrate150.

In a single-plate-type image sensor, the color filter118includes a plurality of adjacent film layers F1, F2, and F3with different color admitting and transmitting properties. The color filter118may include, for example, red, blue, and green dye films, wherein each of the dye films F1, F2and F3are configured to allow only light of a specific wavelength or range of wavelengths, corresponding to a color, therethrough, so that each pixel in the pixel array receives a specific wavelength range of light and thus the color rendering properties of the imaging device may be precise. The dye films F1, F2, and F3are arranged within the color filter118so that a single color dye film corresponds to a single unit cell UC and a single photodiode1. These dye films F1, F2, F3are arranged within the color filter118so that they form a layout of Bayer pattern. Now, in addition to red, green, and blue; the color filter118may contain yellow or white filters.

In two adjacent photodiodes (pixel regions), the color filtering, i.e., the wavelengths of light which may pass through each of the films F1to F3, of the dye films F1, F2, and F3disposed on the corresponding photodiodes differ from each other.

In the micro lens array117, the micro lenses ML are arranged above and in registration with the dye films F1, F2, F3.

In the image sensor100of the present embodiment, the shroud32in a unit cell UC, i.e., entering a single photodiode1, absorbs or blocks the light entering the other unit cells. Due to this, light from a unit cell (photodiode) is does not enter the inside of another unit cell (photodiode).

In the image sensor100of the present embodiment, the shroud32(or referred to as an absorbing layer below) is composed of one or more semiconductors. The shroud32is formed from materials having an absorption coefficient higher than that of Si. For instance, it is desirable that materials of the shroud32have little or no transparency, and absorbs and/or reflects incident light thereon. In addition, it is desirable that the refractive indices of the inner lens31and shrouds32differ. Due to the difference in the refractive indices of the inner lens31and shroud32, the light that enters from inner lens31to the shroud32is reflected at the interface of the inner lens31and shroud32, and then enters the photodiode1that corresponds to the inner lens31. As a result, the function of the inner lens31, as a waveguide for the light from the photographic objects to the unit cell UC (within pixel), is improved.

The shroud32, for example, is formed from SiGe (Silicon Germanium). The light absorption coefficient of a SiGe shroud is larger than the absorption coefficient of adjacent silicon with respect to a visible light. A SiGe layer employed as the shroud32, may be a pure semiconductor layer that includes little or no dopant or may be a semiconductor layer that includes N-type or P-type dopants (i.e., a conductive semiconductor layer).

Furthermore, the shroud32may be comprised of another semiconductor material than SiGe as long as the material has the property of absorbing and/or reflecting light. For example, the shroud32may be formed from Si. However, to improve the light blocking effect from the adjacent unit cells UC (between pixels), it is desirable that the material for the shroud32is chosen from materials with high absorption coefficient, for example materials that have larger absorption coefficient than Si, such as SiGe. Alternatively, a metallic compound that has the characteristic of absorbing and/or reflecting visible light may also be used for the shroud32.

In an image sensor without the shroud32, light OL1that passes through the dye film F1that corresponds to a unit cell may enter (leak into) the adjacent unit cells, depending on the incident angle of the light to the image sensor. When the unintended light from adjacent unit cells is photoelectrically converted by the photodiode of the unit cell, an optical crosstalk may occur, resulting in a mixture of colors in the formed images.

Furthermore, as the densification of pixel array and miniaturization of the unit cell (pixel) progresses, the space between unit cells and pixels becomes smaller. As a result, the impact of optical crosstalk becomes more significant.

In the image sensor100of the present embodiment, the shroud32, which is comprised of SiGe, absorbs the OL1light that enters the shroud32from adjacent unit cells.

Thus, almost all the light OL1that would otherwise cause crosstalk between the adjacent unit cells (referred to as leaked light, below) are absorbed by the shroud32. Hence, even if the light OL1in a direction s from a unit cell (one of the pixels) to the photodiode1in the adjacent unit cell (the other pixel), the photodiode1in the adjacent unit cell will barely receive the light OL1from the unit cell because of the blocking action of the shroud32.

Therefore, the light that passed the color filter and heads from a unit cell to the adjacent unit cell is rarely photoelectrically converted by the photodiode1of the adjacent unit cell.

In the present embodiment, the undesirable effect of the optical crosstalk in the image sensor is decreased and the mixture of colors in the images formed is controlled in this manner.

Accordingly the image sensor of the present embodiment can improve the accuracy of the images received.

(b) Manufacturing Method

A manufacturing method of a solid-state imaging device (for example, an image sensor) of the first embodiment will be explained usingFIG. 6throughFIG. 8.

FIGS. 6 through 8, respectively, show a cross-sectional view of the pixel array120in a process of the image sensor manufacturing method of this embodiment. Here, we will useFIG. 2andFIG. 5to explain each processes of the image sensor manufacturing method of this embodiment, in addition toFIG. 6throughFIG. 8. Furthermore, within the image sensor manufacturing method of this embodiment, the forming sequence of the components, which will be mentioned below, may be changed as long as the consistencies of the processes are secured.

As shown inFIG. 6, the element isolating layer90is formed within the substrate150, at a position so as to surround the region within which the photoelectric diode1, the floating node6and the channel region therebetween are to be formed, using standard masking (photolithographic) techniques to form a masking layer and patter the same.

For example, through ion implantation, the element isolation layer90made of doped semiconductor layer will be formed at specified regions of the semiconductor substrate150(for example, within the pixel array120), which are exposed through apertures in the mask.

As shown inFIG. 2, the device isolation groove to form a STI (Shallow Trench Isolation) structure91therein is formed within the semiconductor substrate150using a mask and reactive ion etching the groove through apertures in the mask, and filling the groove with an by a CVD (Chemical Vapor Deposition) method or a spin coating method. By this process, the STI film91forming the STI structure is formed on a specified region in the semiconductor substrate150.

As result of this process, the unit cell region UC within of pixel array120and the neighboring circuit region125are partitioned from one another in the semiconductor substrate150.

Using a different mask from the one that is used to form the element isolation layer, N-type or P-type well region is formed in a specified region in the semiconductor substrate150.

As are shown inFIG. 2andFIG. 6, the electric elements that are included in the image sensor are formed in the unit cell region UC of the pixel array120and in the neighboring well region159of the circuit region125.

The gate insulating film22of the transistor2and the gate insulating film72of the transistor7are formed on the exposed surfaces (front surface) of the semiconductor substrate150by conducting a thermal oxidation process to the semiconductor substrate150. On the formed gate insulating films22and72, a polysilicon layer is deposited by a CVD method. Then, by using photolithography to form a patterned mask and the RIE method, the polysilicon layer is patterned and the gate electrodes21and71that have specified gate lengths and gate widths are formed on the gate insulating films22, and72.

As shown inFIG. 6, in the pixel array120area, by using the gate electrode22and a patterned resist film (not shown) used as a mask, the n-type dopant layer10of photodiode1is formed at the photodiode formation region within the unit cell region UC by an ion implantation method.

In the floating diffusion formation region of the unit cell range UC, a dopant layer60to form the floating diffusion node6is also formed in the semiconductor substrate150by an ion implantation method, using an additional patterned mask. In addition, the dopant layers (not shown) are formed for the source/drain of transistors within the pixel array120, such as the amplifier transistor.

P-type dopant layer forming the surface shield layer19is formed in the N-type dopant layer10by ion implantation.

During the period when ion implantation is conducted to form the photodiode1and floating diffusion6node in the pixel array120, the peripheral circuit region125is covered by the resist film (not shown).

As shown inFIG. 2, in the region (N-type or P-type well region)159of the peripheral circuit region125where the transistor7is formed, the P-type or N-type dopant layers73as the source and the drain of the transistor7are formed in the semiconductor substrate150, by the ion implantation using the gate electrode72as the mask. Furthermore, the transistor7may be formed in the process of forming the transistors in the pixel array120.

As shown inFIG. 6, on the front surface of the semiconductor substrate150above which the gate electrodes of the transistors2are formed, a multilayer wiring structure that includes the interlaminar insulating films92and the wirings80is formed by a multilayer wiring technology. The interlaminar insulating films92cover the front surface side of the semiconductor substrate150, for example, covering the gate electrodes21of the transistors2.

In the process of forming each wiring level of the multilayer wiring structure, as shown inFIG. 2, a single interlaminar insulating film92of a silicon oxide film is laminated using CVD method. At each wiring level, after the process of flattening the exposed interlaminar insulating layer92by a CMP method, the contact plugs CP1or via plugs81are embedded in the contact holes that are formed in the interlaminar insulating film92by photolithographic and the RIE methods as are well known in the art, the resulting interconnecting wiring layer shown schematically inFIG. 2.

A conductive layer that includes, for example, aluminum or copper as the main component is formed on the interlaminar insulating film92and in the contact plugs CP1and the via plugs81by a sputtering method. The deposited conductive layer is patterned into a specified form by a photolithography method and a RIE method to be selectively connected to the plugs CP1and81. By this process, the conductive layer80as the wirings is formed. Simultaneously to the formation of the conductive layer80as the wirings, a shading film and a dummy layer that are made of the same materials are formed on the interlaminar insulating film92. The wiring80may be formed by a damascene method.

As a result of these processes, the electric elements1,2, and7of the semiconductor substrate150are connected by the multilayer wiring technology and the circuits of the image sensor are formed.

As shown inFIG. 6, after the flattening process is conducted on the uppermost layer of the interlaminar insulating films92(and the conductive layer), an adhesion layer (not shown) is formed on the flattened surface of the uppermost layer of the interlaminar insulating film92. Then, the supporting substrate119is pasted on the adhesion layer. By the adhesive layer, the supporting substrate119connects with the interlaminar insulating films92, which cover the surface of the semiconductor substrate150.

Before the supporting substrate119is adhered to the interlaminar insulating film92, additional wirings to rewire the wirings80that are already formed may be formed on the uppermost layer of the interlaminar insulating film92by a rewiring technology, so that the additional wirings connect to the wiring formed in the interlaminar insulating films92.

As shown inFIG. 7, after the supporting substrate119is adhered to the interlaminar insulating film92, the back surface of the semiconductor substrate150is thinned using methods such as a CMP method and a wet etching using an HF solution. Due to this process, the thickness of the semiconductor substrate150is thinned to the depth of the STI90features.

After the thickness of the semiconductor substrate150is reduced, a P-type dopant layer as the back surface side shield layer18is formed at the back surface of the semiconductor substrate150within the pixel array120by using the ion implantation.

Next, the shrouds32and the inner lenses31are formed on the back surface of the semiconductor substrate150. As shown inFIG. 7, a layer32Z to form the shrouds32is deposited on the back surface side of the semiconductor substrate150.

For example, SiGe is used to form the layer32Z to form the shrouds therefrom. The SiGe layer32Z is formed by a CVD method or as a selectively deposited epitaxial layer. The SiGe layer32Z may be formed by implanting germanium ions into the exposed silicon of the substrate on the back surface of the semiconductor substrate150within the STI features, i.e., within the areas of the silicon substrate isolated by the STI90structures. Furthermore, the SiGe layer32Z may be a pure semiconductor layer or an N-type/P-type semiconductor layer. Thus, the SiGe layer32Z may include dopants.

As shown inFIG. 8, the SiGe layer32Z is processed by the photolithography method and the RIE method to form openings that penetrate to the layer18on the back surface of the semiconductor substrate150. This results in openings in the layer32Z, into which the lenses31will be formed, and the remaining portions of the layer32Z, adjacent to the opening s, form the shrouds32.

A lens material (for example, SiO2) is deposited over the SiGe layer32into the openings therein. An etching process (or CMP) is performed on the lens material and inner lenses31are thus formed within the openings.

If the lens material is overetched, the exposed surface (the side where the color filter will be placed) of the inner lenses31will be set back to the side of the semiconductor substrate150from the upper surface of the SiGe layer32Z. In this case, the film thickness of inner lenses31will be thinner than the film thickness of the shrouds32formed from the SiGe layer32Z

Though the SiGe layer32Z is formed before the inner lenses are formed in the above-mentioned process, the lenses may be formed first and patterned to leave gaps therein for placement of the shrouds32, and then the SiGe layer32Z maybe formed thereover and in the apertures, and removed from the location thereover, to form the shrouds32.

As shown inFIG. 5, a protective insulating layer95is formed on the inner lens31and the shroud32.

Then, the color filter118that has a specified dye film arrangement pattern is formed on the insulating film95so that each dye film is formed above and in registration with each pixel in the perpendicular direction to the principal surface of the semiconductor substrate. In the F1, F2, F3arrangement pattern of the dye films within the color filter118, each of the films F1, F2, F3adjacent to one another are different in terms of the wavelength of light (color) that may pass therethrough.

The micro lens array117is formed on the color filter118in the position that overlaps with the pixel array120.

One dye film and one micro lens ML are formed above the back surface of the semiconductor substrate150so as to correspond to one unit cell UC (one photo diode1) in the pixel array120.

Before the color filter118is formed, wiring, for example a metallic film is deposited on the insulating film95by a sputtering method. The deposited metallic film is patterned to a predetermined shape by the photolithographic and RIE methods. The thus patterned metallic film constitutes the wires in the back surface side of the semiconductor substrate150.

Furthermore, the SiGe layer32Z for forming the shrouds32may include impurities deriving from the inner lenses31, the insulating film95or the wiring (metal).

After the color filter118and the micro lens117are formed, the substrate is etched to form a through via88A through the semiconductor substrate150, as shown inFIG. 2. The via88A may also be formed before the color filter118and the micro lens117are formed.

Through the above-mentioned processes, the backside-illumination image sensor is manufactured.

In the manufacturing method of the image sensor of this embodiment, the inner lenses31and the shrouds32are formed on the back surface of the semiconductor substrate150, which is the light receiving surface of the light. In this embodiment, a single shroud32is formed between each adjacent inner lens31, using materials that have the property of absorbing light.

For example, it is desired that SiGe is preferably used for the shroud32, because SiGe has a high affinity for Si, which is the primary material for the semiconductor substrate150and the other layers, during the manufacturing process. SiGe has a larger absorption coefficient than Si and absorbs light more efficiently than Si.

In cases where the light that transmitted through the corresponding dye film of a unit cell (pixel) is travelling in a direction toward a different unit cell, the shroud32that is placed around a single unit cell UC shroud absorbs the light OL1that is travelling in the direction from the inside of the unit cell UC to the other unit cells UCs. Due to the absorption of the light by the shrouds32, the light that otherwise would head to the other unit cells UCs is blocked at the shrouds32and therefore the light does not leak to adjacent unit cells and thus to the photoelectric convertors of the other unit cells UCs.

Due to this effect, the optical crosstalk in the image sensor is decreased and the colors of the images captured by the image sensor is more accurate.

Second Embodiment

A solid-state image sensor of the second embodiment will be explained referring toFIG. 9. Furthermore, in this embodiment, the explanations that is virtually identical to the explanation for the structure of the first embodiment will be explained, if preferable.

FIG. 9is a cross-sectional view that schematically shows a cross sectional structure of the image sensor of this embodiment. Furthermore, in theFIG. 9, similar toFIG. 5, the illustration of the interlaminar insulating layer, the wirings, and the supporting substrate at the front surface of the semiconductor substrate is simplified.

In the second embodiment, the film thickness t1of a shroud (e.g., a SiGe layer)32A is thinner than the film thickness t2of the inner lens31.

Spacer layers35are placed on the shrouds32A. For example, the spacer layers35are formed from transparent materials. The refractive indices of the inner lens31and the space layer35are preferred to be different.

For example, the upper surfaces of the inner lens31and the spacer layer35are formed co-planar, as shown inFIG. 9. However, there may be a difference in level between the upper surfaces of the inner lens31and the spacer layer35.

The largest incident angle of the light that enters a unit cell UC from another unit cell is determined by the design of the components that are formed at the back surface of the semiconductor substrate150, such as the micro lens117, the color filter118, and the insulating layer95. Thus, the thickness t1of the shroud32A can be thinned within a range of design parameters of the image sensor and a range in which the shroud32can absorb the light from the adjacent cells.

In this embodiment, the size of the photodiode1at the color filter side (light receiving surface side) may be widened and the light that enters the photodiode1from the micro lens and the dye film that correspond to the photodiode1can be increased.

As a result, due to the increase in the light that enters the photodiode1, the quality of the image captured (sensitivity of the image sensor) can improve.

Instead of adding the new spacer layer35, a transparent insulating layer95as a protective film or an adhesion layer may be placed on the shroud32A of film thickness t1, and the insulating layer95may be embedded in the space between the adjacent inner lenses31. In addition, a material with no transparency such as metals may be used for the spacer layer35in order to improve the light blocking effect between the adjacent unit cells.

Furthermore, the manufacturing method of the image sensor in the second embodiment is virtually the same as the manufacturing method in the first embodiment, except an additional process of forming the spacer layers35.

For example, as a manufacturing method, the shrouds32with a film thickness t1and the spacer layers35are formed on the semiconductor substrate150, and then the portion of the layer from which the shrouds32and the spacer layers35are formed is removed in the position corresponding to the position of the photodiodes1. Then, the inner lenses31are formed on the exposed semiconductor substrate150that corresponds to the position of the photodiodes1.

In addition, as a different method from the above-mentioned manufacturing method in the manufacturing processes shown inFIG. 8, the spacers32and overlying film layer35may be formed after the inner lenses31are formed. If so, after forming the inner lens31and the shrouds32, selective etching is performed on the layers forming the shrouds32so that the film thickness t1of the SiGe layer32A will be thinner than the film thickness t2of the inner lens31. Then, the spacer layer35is formed on the shrouds32with a film thickness t1between the adjacent inner lenses31.

As stated above, the image sensor in the second embodiment is similar to the image sensor in the first embodiment and may improve the quality of the images captured by the image sensor.

Third Embodiment

A solid-state image sensor of the third embodiment will be explained referring toFIG. 10andFIG. 11. Furthermore; in this embodiment, the explanations that is virtually identical to that of the first or the second embodiment will be explained, if preferable.

FIG. 10is a cross-sectional view that schematically shows a cross sectional structure of the image sensor of this embodiment. Furthermore, in theFIG. 10, similar toFIG. 5andFIG. 9, the illustration of the interlaminar insulating layer, the wirings, and the supporting substrate at the front surface of the semiconductor substrate is simplified.

In this embodiment, the cross-sectional shape of a shroud (for example, SiGe layer)32B has a tapered shape and a lateral surface of the shroud32B is sloped. Further, the dimension DB1at the upper side of the shroud32B is smaller than the dimension DB2at the lower side, as shown inFIG. 10.

Corresponding to the cross-sectional shape of the shroud32B, the cross-sectional shape of the inner lens31A has a tapered shape. The dimension DA1at the upper side of the inner lens31A is larger than the dimension DA2at the lower side of the inner lens31A, as shown inFIG. 10.

Because the dimension DB1is smaller than the dimension DB2, the dimension DA1of the inner lens31A may be enlarged to be larger than the underlying area of the photodiode1, thus allowing a greater amount of light to pass therethrough. Therefore, the quality of the images captured can improve.

Furthermore, as stated above in the example as shown inFIG. 9, in the configuration in which the film thickness of the shroud32is thinner than the film thickness of the inner lens31, the shroud may have the tapered shape. In addition, the film thickness of the tapered inner lens31B may be thinner than the tapered shroud32B.

Furthermore, to improve the light blocking effect, the dimension of the shroud32B on the upper side may be larger than the dimension of the shroud32B on the lower side.

If a tapered shroud32B is formed as shown inFIG. 10, a film38may be formed between inner lens31A and semiconductor substrate150, depending on the manufacturing process.

The manufacturing method of the solid-state image sensor in the third embodiment is explained usingFIG. 11. Furthermore, the explanations of common manufacturing process as the first embodiment will be explained, if preferable.

If the shroud formed from SiGe is formed by a selective epitaxial growth method, as shown inFIG. 11, the film (e.g., SiO2)38is formed entirely on the back surface of the semiconductor substrate150to control the nuclear growth of SiGe. Then, the back surface of the semiconductor substrate (Si) is exposed within the formation region of the shroud32B by removing the formed film38, and the film38remains in the inner lens formation region.

Due to the selective epitaxial growth, single crystal SiGe selectively grows on the exposed semiconductor substrate150and the grown crystal constitutes the shroud32. On the film38, the SiGe film cannot nucleate, and therefore the crystal of SiGe is not formed on the film38.

If the shroud32B formed from SiGe is formed by an epitaxial growing on the grid plane of Si (100) of the Si substrate used for the semiconductor substrate150, the crystal of SiGe grows in substantial conformity with the crystal grid of Si. A surface S1the SiGe layer32B that is parallel to the principal surface of the semiconductor substrate150constitutes an SiGe (100) surface and the lateral surface S2of SiGe layer32B constitutes an SiGe (111) surface. Crystal growth of SiGe progresses from the side of the semiconductor substrate150. Due to this, a surface sloping to the top surface of SiGe layer32B and the base surface S1is inherently formed on the lateral surface of the SiGe layer32B.

As a result, a shroud32B with a tapered shape can be formed without any additional process besides the forming process of the shroud32B. Thus, in the SiGe layer32B as a shroud, the dimension DB1(opposite side of the semiconductor substrate) is smaller than the dimension DB2.

If the inner lens is formed after SiGe layer32B is formed by the selective epitaxial growth, then the inner lens is formed to conform to the tapered shape of the shroud32B. Thus, as shown inFIG. 10, the dimension DA1at the upper side of the inner lens31B becomes larger than the dimension DB2at the lower side of the inner lens31B.

Furthermore, after the taper-shaped shroud32B is formed, the film38may be removed.

By using the selective epitaxial growth and forming the taper-shaped shroud, like the above-mentioned manufacturing method, an image sensor that improves the quality of image can be obtained without complicating making the manufacturing process.

The tapered shroud may be formed using a different manufacturing procedure from the method shown inFIG. 11. Thus, the tapered shroud may be formed by not using selective epitaxial growth and rather using an etching process such as wet etching and other isotropic etching and etching from the diagonal directions to process the SiGe layer. If the SiGe layer is formed without using the selective epitaxial growth, the film (for instance, SiO2film)38may be formed between the shroud32and the semiconductor substrate150, as the stopper for the etching process.

Accordingly, the solid-state image sensor in the third embodiment, as with the first embodiment and the second embodiment can improve the quality of the captured image by the image sensor.

(4) Modification Example

Modified application examples of the solid-state image sensor according to the above-mentioned embodiments will be explained with reference toFIG. 12throughFIG. 14. Furthermore, within these modified examples, the explanation of configurations that is virtually same as that for the first through third embodiments will be explained, if preferable. In addition, inFIG. 12andFIG. 13, the illustration of the interlaminar insulating layer formed on the surface of the semiconductor substrate, the wirings, and the supporting substrate are simplified.

FIG. 12shows a modified example of the image sensor of the embodiments. As shown inFIG. 12, on an interface of the inner lens31and the shroud (e.g., SiGe layer)32, a plurality of layers39made of a different composition from the inner lens material and SiGe (referred to as an interlayer below) may be placed.

For example, an interlayer39is a material or a compound that is composed of at least one of the constituent element of the shroud32(for here, Si and Ge). Specifically, the interlayer39is composed of a composition, such as SiGe oxide, SiGe nitride, SiGe oxynitride, Si, Si oxide, Si nitride, Si oxynitride, Ge, Ge oxide, Ge nitride, and Ge oxynitride.

The interlayer39may be a material or a compound that includes at least one of the constituent elements of the inner lens31. In addition, the interlayer39may be a compound that includes at least one constituent element of the shroud32and at least one constituent element of inner lens31. For example, a metal film or an organic membrane may be used as the interlayer39.

If the interlayer39is formed between the inner lens31and the SiGe layer32, a material that can reflect light at the interface between the inner lens31and the interlayer39or the interface between the interlayer39and the shroud32can be selected for the material of the interlayer39.

If the interlayer39is formed from transparent materials, it is preferable that the refractive indices of the inner lens31and the interlayer39differs so that light within the lens31incident on the interface reflects at the interfaces of each layer31,32,39.

The amount of light received by the photodiode1increases, because the interface of the inner lens31and the interlayer39reflects the incident light and the inner lens31constitutes a waveguide from the micro lens ML to the photodiode1. Moreover, because the interface between the interlayer39and the SiGe layer32reflects the incident light and the reflective light at the photodiode1, the leakage of light from one unit cell (pixel) UC to another unit cell adjacently positioned decreases. As a result, the optical crosstalk of the image sensor decreases. Therefore, the quality of the captured images can improve.

Although the example that the interlayer39is formed on the lateral surface of the shroud32is shown inFIG. 12, the interlayer39may be placed on the upper surface (the color filter side) of the shroud32. Additionally, in order for the shroud to be divided for each unit cell (pixel), an insulator that surrounds the shroud (and the inner lens) may be placed on the back surface of semiconductor substrate150and at the element isolation area.

FIG. 13shows another modified example of the image sensor, which is different from the example shown inFIG. 12.

In the second embodiment as shown inFIG. 10, the taper-shaped shroud32shroud makes the opening area of the photodiode1on the light receiving surface side wider.

As shown inFIG. 13, the cross-sectional shape of the shroud32X, which is composed of SiGe, shroud is processed into a step-wise form by photo lithographic and etching processes. Due to this process, a shroud32X is formed so that the dimension DZ1at the upper side is smaller than the dimension DZ2at the lower side, as shown inFIG. 13.

The shroud32X shroud contains a first section321that has the dimension DZ1and a second section322that has the dimension DZ2, which is larger than DZ1. The two sections321and322have a rectangular (square shaped) cross-sectional shape, respectively.

The second section322is formed on the back surface of the semiconductor substrate150. The first section321is formed on the second section322, and formed between the second section322that has the dimension DZ2and the insulating layer95in the perpendicular direction to the principal surface of the semiconductor substrate150.

Corresponding to the shape of the shroud32X, the dimension DX1at the upper side of the inner lens31Z becomes larger than the dimension DX2at the lower side of the inner lens31Z, as shown inFIG. 13.

In the modified example shown inFIG. 13, like the example shown inFIG. 10, the opening space of photodiode1can be expanded at the light receiving surface, and the incident light received by the photodiode1can increase.

FIG. 14shows another modified example of the image sensor, which is different fromFIG. 12andFIG. 13. The first through the third embodiments have shown examples in which the shroud32shroud partially covers the unit cell region, so that it covers the formation region of the transfer gate and the formation region of the floating diffusion. However, as shown inFIG. 14, if the shroud32shroud is placed at the boundary part between the adjacent unit cells UCs, the shroud32may be placed within the element isolation area, and the inner lens31may extend over the unit cell region UC.

The shroud32is formed parallel to the layout of element isolation layer90. Each inner lens31covers the entire unit cell region UC at the back surface of the semiconductor substrate150.

Due to this configuration, the opening space of the photodiode1at the back surface of the semiconductor substrate150can be widened and the amount of light that is received by the photodiode1from the micro lens ML can increase.

Therefore, the modified examples shown inFIG. 12throughFIG. 14can achieve virtually the same effect as the first through third embodiments can.

(5) Application Example

An application example of the solid-state image sensor of the embodiments will be explained with reference toFIG. 15.

The solid-state image sensor (image sensor) in the embodiment is modularized and applied to digital cameras and cellular phones with cameras.

FIG. 15is a block diagram that shows an application example of the image sensor of the embodiments.

A camera (or a cellular phone with a camera)900, which includes the image sensor100according to one of the embodiments, includes an optical lens unit (lens unit)101, a signal processing unit (e.g., DSP: Digital Signal Processor)102, a memory unit (memory)103, a display screen (display)104, and a control unit (controller)105in addition to the image sensor100.

The image sensor100receives (captures) the light from an object and converts it to electrical signals.

The lens unit101concentrates the light from the object to the image sensor100and forms the image that corresponds to the light from the imaged object on the image sensor100. The lens Unit101includes a plurality of lenses and is able to mechanically or electrically control optical properties (e.g., focal length).

The DSP102processes the signals that are output from the image sensor100. The DSP102forms the image data that correspond to the imaged object based on the signals output from the image sensor100.

The memory103stores the image data output from the DSP102. The memory103also may store signals and data provided from the outside. The memory103can be a memory chip, such as a DRAM and a flash memory that is installed within the camera900, or a memory card or an USB memory that may be attached or removed from the body of camera900.

The display104shows the image data output from the DSP102and the memory103. The data output from the DSP101or memory103is an image data or a video data.

The controller105controls the action of each component100-104within the camera900.

As mentioned above, the image sensor100of the embodiment can be applied to a camera or a cellular phone with a camera. The camera900including the image sensor100of one of the present embodiments improves the quality of the captured image.