Validation of an integrated circuit for electro static discharge compliance

An aspect of the present invention validates ESD compliance by examining netlist data generated from a schematic level design of an integrated circuit. Routing and placement may be performed only after confirming that whether each protected circuit (having exposure to ESD current, without the protection circuit) is protected by an appropriate protection circuit. As a result, the design cycle time may be reduced. According to another aspect of the present invention, layout guidelines for each protection circuit is also considered in performing the routing and placement. As a result, the number of iterations in a design cycle may be reduced.

BACKGROUND

The present disclosure relates software tools used in computer aided design (CAD) of integrated circuits, and more specifically to a method and apparatus for validating integrated circuits for electro static discharge (ESD) compliance.

2. Related Art

Electro static discharge (ESD) generally refers to the flow of electric charges (current) through the interface pads of an integrated circuit (IC), typically while not in use. One example of such not-in-use scenario is while packages containing the ICs are transported/moved prior to deployment in corresponding systems/devices. A common reason for the ESD is interface pads coming in contact with human beings while being deployed on systems or during transportation.

ESD is generally undesirable in that the magnitude of the current is often much higher than the magnitude for which an IC may be designed for during normal use in systems/devices. Such high current flow can damage various functional circuits within an IC, as is well known in the relevant arts. Accordingly, there has been a general need to avoid ESD current flowing through the functional circuits within an IC, as is well known in the relevant arts.

Protection circuits are accordingly often implemented associated with the portions functional circuits and/or the pads to avoid the flow of ESD current through functional circuits (Aprotected circuits@). Validation of an IC for ESD compliance generally refers to ensuring adequate protection circuit for each portion of a functional circuit that may be susceptible to ESD discharge noted above. Such portions often provide path from a interface pad to Vdd (supply terminal) or ground.

The validation generally needs to be efficiently integrated into the design approach employed to design ICs. In one approach, an IC designer may generate a schematic circuit graphically representing electronic/electrical components (e.g., transistors, diodes, capacitors) and their connectivity in a schematic phase. The netlist (textual representation of the graphic information) resulting from the schematic phase may be used by a routing and placement phase to place the components meeting various criteria. Further checks may be performed to ensure that the eventually fabricated circuit meets various criteria.

In general, the ESD compliance validation needs to be performed within the context of at least such a design approach, while meeting one or more requirements such as reduced time to complete design (prior to fabrication), simplicity, reduced effort, etc.

DETAILED DESCRIPTION

An aspect of the present invention validates ESD compliance by examining netlist data generated from a schematic level design of an integrated circuit. Routing and placement may be performed only after confirming that whether each protected circuit (having exposure to ESD current, without the protection circuit) is protected by an appropriate protection circuit. As a result, the design cycle time may be reduced.

According to another aspect of the present invention, layout guidelines for each protection circuit is also considered in performing the routing and placement. As a result, the number of iterations in a design cycle may be reduced.

According to yet another aspect of the present invention, another netlist may be extracted from layout information (generated by routing and placement), with the another netlist including parasitic information between nodes of a protection circuit. The acceptability of the parasitic may also thus be verified at the netlist level. As a result, a single verification engine operating at netlist level, can be implemented for verification before and after routing/placement.

2. Example Integrated Circuit

FIG. 1is block diagram of a portion of an integrated circuit illustrating the general need for of an ESD protection circuit. The block diagram is shown containing I/O pad110, ESD circuits130and140, input/output (I/O) cells170and160, and core logic180. Each block is described below in further detail.

Core logic180operates to provide desired utility for which the integrated circuit is primarily designed. Core logic180processes signal received on pad110and send the result of the processing on the pad110. However, different pads can be used for input and output respectively. Portions of core logic180may also be required to be protected circuits, but is not addressed the present application merely in the interest of conciseness.

Each of I/O cells170and160operates as an interface/buffer between the pad110and core logic180. Each I/O cell may operate to change the signal level in either direction to suit the interface requirements of core logic/external devices. For example, I/O cell may reduce a signal level to a suitable internal signal value (before providing to core logic180) and vice versa. The I/O cells represent example protected circuits.

I/O pad110provides an interface for making an external connection to integrated circuit100. An I/O pad is generally formed of a conductive metal portion provided on the surface of a package containing the integrated circuit. Often, pad210is soldered to a conducting path (not shown) on a printed circuit board. The signals received from the conducting path are provided to core logic180and vice versa.

Protection circuits130and140operate to protect respective I/O cells160and170, and core logic from ESD current noted above in the Background Section. As noted in that section, integrated circuits need to be validated for ESD compliance (ESD verification) within a framework of approaches used for design of integrated circuits.

Several aspects of the present invention provide for such validation. The features of the invention may be appreciated in comparison with a prior approach in which one or more aspects of the present invention are not implemented. Accordingly an example prior approach is described first below.

3. Example Prior Approach

FIGS. 2 and 3are flow diagrams illustrating the ESD verification in the context of one prior design approach. In block210, a designer may graphically design a desired integrated circuit using various design tools (e.g., Spice tool, AutoCAD tool) and generate a netlist. Netlist represents the graphic information in a pseudo-code (typically representable as text), which can be processed easily by computer instructions. The netlist indicates the electrical/electronic components and their connectivity, as specified by the designer.

In block230, routing and placement of the design represented by the netlist, is performed. Additional guidelines from libraries, etc., may also be used in performing routing and placement. Routing and placement may be performed using various tools (e.g., Virtuoso software from Cadence Corporation, Astro/Magma Blast Fusion software from Synopsys) available in the industry. If any desired criteria (e.g., propagation delays, bus width, cross talk, etc.) is not met, the IC design may need to be continued with block210described above.

Layout information representing the specific location of underlying structure (e.g., channel information for transistors, plate information for capacitors) supporting each component on the die on which the IC is to be fabricated, and path information (e.g., bus width, material, etc.), is generated due to the routing and placement. The layout information may be in the form of various masks to be used in fabrication, described below.

In block250, verification for ESD compliance is performed by examining the layout information. Other checks (power compliance, IR-drop compliance, etc.) may also be performed in block250, but are not shown/described for conciseness. Non-compliance of the circuit for ESD protection may require that the phases of210and/or230be revisited.

In block270, once the design complies with the compliance requirements, the mask information from block230is used to fabricate ICs.

The approach ofFIG. 2may be inefficient for multiple reasons. For example, since ESD verification is performed after placement230, both210and230may need to be performed when protection circuit is to be corrected or added. In addition, ESD specific requirements may not be checked by routing and placement230(e.g., parasitic requirements specific to components forming protection circuit).

Some of the inefficiencies may be further clear by understanding the details of ESD verification250and accordingly details of ESD verification250in one embodiment are described below first.

FIG. 3is a flow diagram illustrating the details of ESD verification (of block250) in one prior embodiment. Layout information310(resulting from routing and placement230) is received.

Library information330contains information representing the various circuit portion types (e.g., I/O cells) and corresponding protection circuit types, the number of external interface (pads) present in the circuit. The library information may also contain rules, with each rule being designed for a specific type of protection circuit. As may be appreciated, different circuit portions (sought to be protected) may require different type of protection circuits, and a rule may be provided associated with each type. The rule may further indicate the type of circuit portions the protection circuit would protect when deployed.

Syntax converter320reads the layout information310and library information330, and provides the combined information in a common format (readable) for further processing by layout extraction deck340.

Layout extraction deck340identifies protection circuit instances corresponding to each type defined in a rule of the library. The protected circuits corresponding to each protection circuit may also be extracted from layout information330. The output of layout extraction deck340is stored in extracted information350(in Netlist format in a file). The output contains the list of bond pads, and for each bond pad the associated protection circuits and protected circuits. The output may also contain various parasitics (capacitance, path resistance, etc.) of the paths connecting the components.

Protection confirmation380checks whether there are any bond pads that are not connected based on the extracted information350. Protection confirmation380may match each protected circuit with the corresponding protection circuit and determine whether the protection circuit effective protects the protected circuit (based on various ESD guidelines, which may be received as a part of library information), and can be implemented in a known way. Protection confirmation380may also check whether the parasitic components (due to layout stage230) affect the desired protection. A report of the checking may be provided to facilitate any necessary changes.

It may be appreciated that extraction of the protected/protection circuits is performed by defining rules in the extraction rule deck. New rules may thus be needed for each additional protection/protected circuit types. The definition of such rules is again overhead for the designers, as well as, adds to the complexity of the overall implementation/verification.

Various aspects of the present invention overcome at least one or more the disadvantages noted above.

5. Netlist Based ESD Validation

FIG. 4is a flowchart illustrating the manner in which an integrated circuit can be designed in an embodiment of the present invention. The features herein can be integrated, for example, into a CAD based design/verification tool and accordingly is described with respect to a design tool merely for illustration. The tool can be implemented as a single computer program (provided by a single vendor) or multiple programs (provided by respective vendors) operating according to pre-specified interfaces.

Further, the flowchart is described with respect to the circuit ofFIG. 6merely for illustration. However, the features can be implemented in relation to various other integrated circuits (of much higher complexity as well), as will be apparent to one skilled in the relevant arts by reading the disclosure provided herein. The flowchart starts in step401, in which control passes to step410.

In step410, a design tool enables designers to provide a schematic level design of an integrated circuit. The designers may further provide a library indicating the general structures (components and connectivity) of protection circuits and protected circuits. The library may be provided according to any convention and be updated based on the content/purpose of the integrated circuit sought to be designed.

Thus, with respect toFIG. 6, the schematic level design may substantially be similar to the display ofFIG. 6. The library may indicate that structure such as601represents a protection circuit for a structure such as602represents the corresponding protected circuit.

In step420, the design tool forms a netlist from the schematic design. Various commercially available tools can be used to enter the schematic level diagram, and the tool may be designed to generate the netlist as well. In general, designers specify various components and connectivity information using an appropriate GUI (graphics user interface).

In step430, the design tool examines the netlist based on the library to identify each circuit portion requiring protection (Aprotected circuit@) and protection circuits connected to each pad. Each structure in the library may be compared with various portions in the netlist for such identification.

Thus, with respect toFIG. 6, the design tool may determine that there is pad610, and that there is only a single protection circuit601for protected circuit602associated with pad610. From the comparisons, structures601and602may be respectively identified as the protection circuit and the protected circuit.

In step435, the design tool determines if all protected circuits are protected by appropriate protection circuits. Such determination is made based on various design rules defined by technology development team responsible for responsible for ESD guidelines. designers for the integrated circuit. Each design rule may specify an approved protection circuit structure and corresponding protected circuit topologies. Thus, a design rule may indicate a structure such as601is appropriate for a cascode buffer structure such as602.

If the result of the determination is yes, control passes to step440, else to step410. With respect toFIG. 6, as structure601is an appropriate protection circuit for protected circuit602, control passes to step440. However, if there are identified protected structures that are not protected (e.g., due to design oversight in step410), control would pass to step410(so that the designer can add the appropriate protection structures).

In step440, the design tool generates layout guidelines for the components of each protection circuit. Layout guidelines may indicate maximum parasitics permitted between two nodes (e.g. the maximum parasitic limit between the source terminal of transistor640and ground Vss, the maximum parasitic limit between the drain terminal of transistor640to pad610) in a protection circuit. The guidelines may be computed dynamically based on various parameters (e.g., junction capacitance, stray capacitance, etc.) related to the components of the protected and protection circuits.

In step450, the design tool provides layout guidelines along with the netlist to a route and placement stage. The guidelines may be provided in the form of various values suitable as inputs for placement and routing. For example, the parasitic values computed may be converted into bus thickness, distance, etc., and provided along with the netlist.

In step455, the design tool performs placement and routing to form a layout, and can be performed in a known way. Due to the use of the guidelines of step440, the placement of components may accordingly be affected. In the illustrative examples noted above, the drain terminal of transistor640may be placed close to pad610, and the source terminal may be placed close to ground to stay within the parasitic limits. Alternatively, the thickness of the paths may be increased to reduce the parasitics.

In step460, the design tool may generate a netlist containing parasitic information from the layout. Such information can be generated using various >extraction=techniques, well known in the relevant arts.

In step470, the design tool determines whether the parasitics are within acceptable limits. The acceptable limits may also be received in the form of design guidelines from designers. Control passes to step480is there is a violation or else to step490.

In step480, the design tool may require the designer to change the layout, and control passes to step455. The designers may be indicated the violated limits/parameters, such that appropriate adjustments can be performed.

In step490, the layout information in the form of masks is sent for fabrication. The flowchart ends in step499.

From the above it may be appreciated that the design cycle time may be reduced both due to detection of errors prior to layout phase, in addition to providing additional constraints (guidelines) to routing/placement stage of the design tool. The description is continued with respect to an example architecture implementing some of the features described above.

FIG. 5is a block diagram illustrating an example architecture in which at least some of the features described above can be implemented. Netlist510represents both the netlist generated from schematic design and the extracted information in step460(represented by layout extraction module520). Since both are represented in a common representation, common modules (verification tools) can be used downstream. The common modules in an example implementation are described below in further detail.

Network representation module540reads the information (components, connectivity, and optionally the parasitic information) received as net list510and maintains the information in a efficient geometric format. For example, each component may be converted into a corresponding geometric representation, with the magnitudes of the geometry potentially representing the size type attributes of the component. The geometric representative may provide higher level abstract view (e.g., structure602as a cascode buffer) also. The conversion from net list to graph format is performed using well-known approaches.

Network reduction module550reduces parasitic networks into compact RC representation on VDD and VSS/ground bus. Large RC network on VDD and VSS bus are obtained due to large RC extractions techniques used for extracting the layout. The reduction enables faster topology checking and path tracing.

Pattern matching module570locates stamps of ESD circuit (assuming the circuits in the library of step410are also converted to corresponding geometry/stamp) to identify the protection circuits. Pattern matching module570further searches netlist and locate protected circuits at the pads based on the available pattern defined in the configuration file (library).

Library may be updated with new protection circuit structure and protected circuit structure (Topology) in netlist (Spice) format as and when designer designs such circuits. As may be appreciated, such information is automatically checked while performing pattern matching (to detect matching protected and protection circuits).

ESD validation module580may first check for known bad/undesirable circuit topologies. Such circuit topologies are often specified for each integrated circuit based on the context or purpose of the integrated circuit. For example, if there are specific protected circuits, which are undesirable, such circuits may be specified in a library, and module580flags the occurrence of any of such undesirable protected circuits.

Further, module580determines whether each protection circuit is suited for the corresponding protected circuit (identified in430/570). Geometric checks on ESD components and components connected to pads are performed to generate a report. Reporting module590consolidates the output error data in a user compatible format.

As noted above, the features described above may be provided in a design tool, which is implemented on one or more digital processing systems. The description is continued with respect to the details of such a system on which the design tool may be executed.

7. Digital Processing System

FIG. 7is a block diagram of computer system700illustrating an example system for implementing the design tool(s) noted above. Computer system700may contain one or more processors such as central processing unit (CPU)710, random access memory (RAM)720, secondary memory730, graphics controller760, display unit770, network interface780, and input interface790. All the components except display unit770may communicate with each other over communication path750, which may contain several buses as is well known in the relevant arts. The components ofFIG. 7are described below in further detail.

CPU710may execute instructions stored in RAM720to provide several features of the present invention (by performing tasks corresponding to various approaches described above). CPU710may contain multiple processing units, with each processing unit potentially being designed for a specific task. Alternatively, CPU710may contain only a single processing unit. RAM720may receive instructions from secondary memory730using communication path750.

Graphics controller760generates display signals (e.g., in RGB format) to display unit770based on data/instructions received from CPU710. Display unit770contains a display screen to display the images defined by the display signals. Input interface790may correspond to a key-board and/or mouse, and generally enables a user to provide inputs. Network interface780enables some of the inputs (and outputs) to be provided on network ofFIG. 7. In general, display unit770, input interface790and network interface780enable designers to interact with the design tool according to various features described above.

Secondary memory730may contain hard drive735, flash memory736and removable storage drive737. Secondary storage730may store the software instructions (which perform the actions specified by various flow charts above) and data (e.g., topology of the modules, cell libraries, library, rules), which enable computer system700to provide several features in accordance with the present invention.

Some or all of the data and instructions may be provided on removable storage unit740, and the data and instructions may be read and provided by removable storage drive737to CPU710. Floppy drive, magnetic tape drive, CD-ROM drive, DVD Drive, Flash memory, removable memory chip (PCMCIA Card, EPROM) are examples of such removable storage drive737.

Removable storage unit740may be implemented using medium and storage format compatible with removable storage drive737such that removable storage drive737can read the data and instructions. Thus, removable storage unit740includes a computer readable storage medium having stored therein computer software and/or data. However, the computer readable storage medium can be on other types of memories (removable or not, volatile or non-volatile). An embodiment of the present invention is implemented using software running (that is, executing) in computer system700.

In this document, the term “computer program product” is used to generally refer to removable storage unit740or hard disk installed in hard drive735. These computer program products are means for providing software to computer system700. As noted above, CPU710may retrieve the software instructions, and execute the instructions to provide various features of the present invention described above.