Semiconductor switch

A semiconductor switch includes: a first terminal; a second terminal; a switch section including a through FET connected between the first terminal and the second terminal and a shunt FET connected between the second terminal and a first ground terminal; a first control terminal configured to drive the through FET; a second control terminal configured to drive the shunt FET; and a driver provided on a substrate together with the switch section and configured to provide a differential output to the first control terminal and the second control terminal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-200647, filed on Aug. 31, 2009; the entire contents of which are incorporated herein by reference.

BACKGROUND

Embodiments of the invention relate generally to a semiconductor switch.

2. Background Art

Cell phones include a radio frequency circuit section in which a transmit circuit and a receive circuit are selectively connected to a common antenna through a switch circuit for radio frequency signals. The switch element of such a switch circuit for radio frequency signals has conventionally been based on a HEMT (high electron mobility transistor) made of compound semiconductor. Recently, replacement of the HEMT by a MOSFET (metal oxide semiconductor field effect transistor) formed on a silicon substrate has been under consideration in view of requirements for cost reduction and downsizing.

However, the conventional MOSFET formed on a silicon substrate has large parasitic capacitance between the source or drain electrode and the silicon substrate. Another problem is that the radio frequency signal incurs large power loss because silicon is a semiconductor. In this context, a technique is proposed for forming a switch circuit for radio frequency signals on an SOI (silicon on insulator) substrate (see, e.g., JP-T-2005-515657).

However, further improvement is required for inter-terminal isolation and insertion loss. For instance, a switch for switching high-definition digital television signals requires an isolation of 75 dB or more at a frequency of 1 GHz.

SUMMARY

According to an aspect of the invention, there is provided a semiconductor switch including: a first terminal; a second terminal; a switch section including a through FET connected between the first terminal and the second terminal and a shunt FET connected between the second terminal and a first ground terminal; a first control terminal configured to drive the through FET; a second control terminal configured to drive the shunt FET; and a driver provided on a substrate together with the switch section and configured to provide a differential output to the first control terminal and the second control terminal.

DETAILED DESCRIPTION

Embodiments of the invention will now be described in detail with reference to the drawings.

In the present specification and drawings, elements similar to those described previously with reference to earlier figures are labeled with like reference numerals, and the detailed description thereof is omitted as appropriate.

FIG. 1is a block diagram illustrating the configuration of a semiconductor switch according to an embodiment of the invention.

As shown inFIG. 1, the semiconductor switch1includes a switch section2and a controller section3. These are formed in the same substrate18(semiconductor switch substrate) to provide a one-chip structure.

The switch section2illustratively has a configuration for switching the connection state between a first terminal RFcom and two second terminals RF1, RF2.

The controller section3switches the connection state of the switch section2. It is noted that the controller section3may be part of a circuit for controlling the switch section2.

The through FETs T11, T12, . . . , T1nare connected between the first terminal RFcom and the second terminal RF1. The through FETs T21, T22, . . . , T2nare connected between the first terminal RFcom and the second terminal RF2.

The gates of the through FETs T11, T12, . . . , T1nconnected to the second terminal RF1are connected to a first control terminal Con1arespectively through resistors RT11, RT12, . . . , RT1nfor preventing leakage of radio frequency. The first control terminal Con2ais connected to the controller section3. The resistors RT11, RT12, . . . , RT1neach have a resistance high enough to avoid leakage of radio frequency signals to the controller section3.

The gates of the shunt FETs S11, S12, . . . , S1mconnected to the second terminal RF1are connected to a second control terminal Con1brespectively through resistors RS11, RS12, . . . , RS1mfor preventing leakage of radio frequency. The second control terminal Con1bis connected to the controller section3. The resistors RS11, RS12, . . . , RS1meach have a resistance high enough to avoid leakage of radio frequency signals to the controller section3.

The gates of the through FETs T21, T22, . . . , T2nconnected to the second terminal RF2are connected to a first control terminal Con2arespectively through resistors RT21, RT22, . . . , RT2nfor preventing leakage of radio frequency. The first control terminal Con2ais connected to the controller section3. The resistors RT21, RT22, . . . , RT2neach have a resistance high enough to avoid leakage of radio frequency signals to the controller section3.

The gates of the shunt FETs S21, S22, . . . , S2mconnected to the second terminal RF2are connected to a second control terminal Con2brespectively through resistors RS21, RS22, . . . , RS2mfor preventing leakage of radio frequency. The second control terminal Con2bis connected to the controller section3. The resistors RS21, RS22, . . . , RS2meach have a resistance high enough to avoid leakage of radio frequency signals to the controller section3.

During turn-off of the through FETs connected to the second terminal to which the shunt FET is connected, the shunt FET enhances isolation between that second terminal and the first terminal. More specifically, even when the through FET is turned off, a radio frequency signal may leak to the second terminal connected to that through FET in the OFF state. At this time, the leaked radio frequency signal can be dissipated to the ground through the shunt FET in the ON state.

For instance, for conduction between the second terminal RF1and the first terminal RFcom, the n stages of series connected through FETs T11-T1nbetween the second terminal RF1and the first terminal RFcom are turned on, and the m stages of series connected shunt FETs S11-S1mbetween the second terminal RF1and the ground are turned off. Simultaneously, the through FETs between the other second terminal RF2and the first terminal RFcom are all turned off, and the shunt FETs between the other second terminal RF2and the first ground terminal GND2are all turned on.

In the above case, an ON potential Von is applied to the first control terminal Con1a, and an OFF potential Voff is applied to the second control terminal Con1b. Furthermore, the OFF potential Voff is applied to the first control terminal Con2a, and the ON potential Von is applied to the second control terminal Con2b. The ON potential Von is a gate potential bringing each FET into the conducting state in which its ON resistance has a sufficiently small value. The OFF potential Voff is a gate potential bringing each FET into the blocking state which can be sufficiently maintained even under superposition of a radio frequency signal. The threshold voltage Vth of each FET is illustratively 0.1 V.

If the ON potential Von is lower than a desired potential (such as 2.4 V), the ON resistance of the FET in the conducting state increases, degrading insertion loss, and distortion generated by the FET in the conducting state (ON distortion) increases. If the OFF potential Voff is higher than a desired potential (such as −1.5 V), the maximum allowable input power decreases, and distortion generated by the FET in the blocking state for rated input (OFF distortion) increases.

However, an extremely high ON potential Von or an extremely low OFF potential Voff will exceed the breakdown voltage of the FET. Hence, there is an optimal range for the ON potential Von and the OFF potential Voff.

The signal for controlling the gate potential of each FET of the switch section2is generated by the controller section3.

FIG. 2is a circuit diagram illustrating the configuration of the controller section of the semiconductor switch shown inFIG. 1.

As shown inFIG. 2, the controller section3includes drivers4a,4b, a negative voltage generator (voltage generator)5, an input interface circuit10, and an inverted/non-inverted signal generator11.

The power supply voltage Vdd is illustratively 2.7 V. On the other hand, the high level of the signal inputted to the external control terminal IN is lower than Vdd, illustratively 1.8 V. Hence, it is level-shifted in the input interface circuit10.

As shown inFIG. 2, the input interface circuit10is composed of three stages of CMOS inverters. In the first stage, two stages of diode-connected FETs are provided at the high-potential node of a normal CMOS inverter. In the second stage, one stage of diode-connected FET is provided at the high-potential node of a normal CMOS inverter. Furthermore, the third stage is composed of a normal CMOS inverter. By this configuration, an input signal with a high level of 1.8 V is level-shifted to a signal with a high level of Vdd (2.7 V).

The output signal of the input interface circuit10is inputted to the inverted/non-inverted signal generator11, which is composed of two stages of CMOS inverters. Its differential output is inputted to the drivers4aand4b. Here, each driver4a,4bis composed of a level shifter.

The negative potential Vn of the low-potential power supply of the drivers4a,4bis generated by the negative voltage generator (voltage generator)5.

The negative voltage generator (voltage generator)5is illustratively composed of a ring oscillator6, a charge pump7, a low-pass filter (LPF)8, and a clamp circuit9. The ring oscillator6supplies a differential clock CK, CK− to the charge pump7. The output of the charge pump7is smoothed by the low-pass filter8, which outputs a negative potential Vn. The negative potential Vn is stabilized by the clamp circuit9. Here, the value of the negative potential Vn outputted from the negative voltage generator (voltage generator)5is illustratively −1.5 V.

In the drivers4a,4b, P-channel MOSFETs (hereinafter PMOSs) are provided on the high-potential power supply (power supply voltage Vdd) side, and cross-coupled N-channel MOSFETs (hereinafter NMOSs) with the gate connected to the other's drain are provided on the low-potential power supply (negative potential Vn) side.

A control signal is differentially outputted at the drain of the NMOS and the drain of the PMOS of the driver4a. This control signal is differentially outputted to the first control terminal Con1aand the second control terminal Con1bof the switch section2. Furthermore, a control signal is differentially outputted at the drain of the NMOS and the drain of the PMOS of the driver4b. This control signal is differentially outputted to the first control terminal Con2aand the second control terminal Con2bof the switch section2.

By the drivers4a,4b, the low level is level-shifted from 0 V to Vn (−1.5 V). More specifically, a control signal with a high level of Vdd (2.7 V) and a low level equal to the negative potential Vn (−1.5 V) is outputted to the first and second control terminals Con1a, Con1b, Con2a, Con2b. By setting the low level of the control signal to the negative potential, a switch can be realized with low distortion even for high-power input signals.

Here, the logic level of the control signal is the same for the first control terminal Con1aand the second control terminal Con2b, and the same for the second control terminal Con1band the first control terminal Con2a.

Hence, it may be contemplated that two drivers are not needed, but only one is sufficient.

FIG. 3is a circuit diagram illustrating the configuration of a semiconductor switch of a comparative example.

As shown inFIG. 3, the semiconductor switch101of the comparative example has a configuration in which the controller section3of the semiconductor switch1shown inFIG. 1is replaced by an inverter103. The first control terminal Con1aand the second control terminal Con2bare connected to the input end of the inverter103. The second control terminal Con1band the first control terminal Con2aare connected to the output end of the inverter103.

However, if the through FETs T11, T12, . . . , T1nand the shunt FETs S21, S22, . . . , S2mconnected to a plurality of second terminals RF1, RF2are driven by the same driver, a radio frequency signal superposed on each control signal may interfere with other control signals. More specifically, if the first control terminal Con2aand the second control terminal Con1bare connected and driven by one inverter103, interference between signals may occur and lead to isolation degradation.

More specifically, the driver4adifferentially outputs a control signal to the first control terminal Con1aand the second control terminal Con1b, which respectively drive a pair of through FETs T11, T12, . . . , T1nand shunt FETs S11, S12, . . . , S1mconnected to the second terminal RF1.

The driver4bdifferentially outputs a control signal to the first control terminal Con2aand the second control terminal Con2b, which respectively drive a pair of through FETs T21, T22, . . . , T2nand shunt FETs S21, S22, . . . , S2mconnected to the second terminal RF2.

Thus, by providing the drivers4a,4bindependently at the respective second terminals (respective ports), interference of radio frequency signals superposed on each control signal with other control signals is avoided.

Hence, isolation can be improved in the semiconductor switch1.

The semiconductor switch1shown inFIGS. 1 and 2is illustratively based on the configuration using the negative voltage generator (voltage generator)5. However, if the through FETs and shunt FETs can satisfy desired loss/distortion characteristics without using the negative potential Vn, then the negative voltage generator (voltage generator)5, the input interface circuit10, and the inverted/non-inverted signal generator11may be omitted.

Furthermore, although the semiconductor switch1is illustratively based on the SPDT switch, a kPIT switch can be constructed likewise, where k, l are natural numbers.

FIG. 4is a block diagram illustrating the configuration of a semiconductor switch according to the embodiment of the invention.

As shown inFIG. 4, the semiconductor switch is includes a switch section2aand a controller section3. These are formed in the same substrate18(semiconductor switch substrate) to provide a one-chip structure. That is, the semiconductor switch is has a configuration in which the switch section2of the semiconductor switch1shown inFIG. 1is replaced by the switch section2a.

The switch section2aillustratively has a configuration for switching the connection state between a first terminal RFcom and two second terminals RF1, RF2.

The connection state of the switch section2ais switched by the controller section3.

The semiconductor switch is an SPDT switch.

The gates of the first FETs T11, T12, . . . , T1nconnected to the second terminal RF1are connected to a first control terminal Con1arespectively through resistors RT11, RT12, . . . , RT1nfor preventing leakage of radio frequency. The first control terminal Con1ais connected to the controller section3. The resistors RT11, RT12, . . . , RT1neach have a resistance high enough to avoid leakage of radio frequency signals to the controller section3.

The gates of the shunt FETs S11, S12, . . . , S1mconnected to the second terminal RF1are connected to a second control terminal Con1brespectively through resistors RS11, RS12, . . . , RS1mfor preventing leakage of radio frequency. The second control terminal Con1bis connected to the controller section3. The resistors RS11, RS12, . . . , RS1meach have a resistance high enough to avoid leakage of radio frequency signals to the controller section3.

The gates of the second FETs T21, T22, . . . , T2nconnected between the connection node N1and the first terminal RFcom are connected to the first control terminal Con1arespectively through resistors RT21, RT22, . . . , RT2nfor preventing leakage of radio frequency. The resistors RT21, RT22, . . . , RT2neach have a resistance high enough to avoid leakage of radio frequency signals to the controller section3.

The gates of the third FETs S21, S22, . . . , S2mconnected between the connection node N1and the second ground terminal GND3are connected to the second control terminal Con1brespectively through resistors RS21, RS22, . . . , RS2mfor preventing leakage of radio frequency. The resistors RS21, RS22, . . . , RS2meach have a resistance high enough to avoid leakage of radio frequency signals to the controller section3.

The gates of the first FETs T41, T42, . . . , T4nconnected to the second terminal RF2are connected to a first control terminal Con2arespectively through resistors RT41, RT42, . . . , RT4nfor preventing leakage of radio frequency. The first control terminal Con2ais connected to the controller section3. The resistors RT41, RT42, . . . , RT4neach have a resistance high enough to avoid leakage of radio frequency signals to the controller section3.

The gates of the shunt FETs S41, S42, . . . , S4mconnected to the second terminal RF2are connected to a second control terminal Con2brespectively through resistors RS41, RS42, . . . , RS4mfor preventing leakage of radio frequency. The second control terminal Con2bis connected to the controller section3. The resistors RS41, RS42, . . . , RS4meach have a resistance high enough to avoid leakage of radio frequency signals to the controller section3.

The gates of the second FETs T31, T32, . . . , T3nconnected between the connection node N2and the first terminal RFcom are connected to the first control terminal Con2arespectively through resistors RT31, RT32, . . . , RT3nfor preventing leakage of radio frequency. The resistors RT31, RT32, . . . , RT3neach have a resistance high enough to avoid leakage of radio frequency signals to the controller section3.

The gates of the third FETs S31, S32, . . . , S3mconnected between the connection node N2and the second ground terminal GND4are connected to the second control terminal Con2brespectively through resistors RS31, RS32, . . . , RS3mfor preventing leakage of radio frequency. The resistors RS31, RS32, . . . , RS3meach have a resistance high enough to avoid leakage of radio frequency signals to the controller section3.

During turn-off of the through FETs, or the first and second FETs, connected to the second terminal to which the shunt FET is connected, the shunt FET and the third FET enhance isolation between that second terminal and the first terminal. More specifically, even when the first and second FET are turned off, a radio frequency signal may leak to the second terminal connected to that first FET in the OFF state. At this time, the leaked radio frequency signal can be dissipated to the ground through the shunt FET and the third FET in the ON state and through the first and second ground terminal.

Furthermore, a first capacitor C1is connected between the first ground terminal GND1and the second ground terminal GND3. A first capacitor C2is connected between the first ground terminal GND2and the second ground terminal GND4. Furthermore, a second capacitor C3is connected between the second ground terminals GND3and GND4.

For instance, for conduction between the second terminal RF1and the first terminal RFcom, the through FETs between the second terminal RF1and the first terminal RFcom, that is, the n stages of series connected first FETs T11-T1nand second FETs T21-T2n, are turned on. Simultaneously, the m stages of series connected shunt FETs S11-S1mbetween the second terminal RF1and the first ground terminal GND1and the m stages of series connected third FETs S21-S2mbetween the connection node N1and the second ground terminal GND3are turned off. Simultaneously, the through FETs, or the first and second FETs, between the other second terminal RF2and the first terminal RFcom are all turned off, and the shunt FETs between the other second terminal RF2and the first ground terminal GND2and the third FETs between the connection node N2and the second ground terminal GND4are all turned on.

In the above case, an ON potential Von is applied to the first control terminal Con1a, and an OFF potential Voff is applied to the second control terminal Con1b. Furthermore, the OFF potential Voff is applied to the first control terminal Con2a, and the ON potential Von is applied to the second control terminal Con2b. The ON potential Von is a gate potential bringing each FET into the conducting state in which its ON resistance has a sufficiently small value. The OFF potential Voff is a gate potential bringing each FET into the blocking state which can be sufficiently maintained even under superposition of a radio frequency signal. The threshold voltage Vth of each FET is illustratively 0.1 V.

If the ON potential Von is lower than a desired potential (such as 2.4 V), the ON resistance of the FET in the conducting state increases, degrading insertion loss, and distortion generated by the FET in the conducting state (ON distortion) increases. If the OFF potential Voff is higher than a desired potential (such as −1.5 V), the maximum allowable input power decreases, and distortion generated by the FET in the blocking state for rated input (OFF distortion) increases.

However, an extremely high ON potential Von or an extremely low OFF potential Voff will exceed the breakdown voltage of the FET. Hence, there is an optimal range for the ON potential Von and the OFF potential Voff. Here, the ON potential Von and the OFF potential Voff are similar to those for the switch section2shown inFIG. 1.

When the conducting state is established between the second terminal RF1and the first terminal RFcom, the impedance seen from the second terminal RF2toward the switch is the sum of the ON resistance of the shunt FETs S41-S4mand the resistance of the resistor Rtem2. This value is normally set to 75 Ω. Likewise, when the conducting state is established between the second terminal RF2and the first terminal RFcom, the impedance seen from the second terminal RF1toward the switch is the sum of the ON resistance of the shunt FETs S11-S1mand the resistance of the resistor Rtem1. This value is normally set to 75 Ω. Here, if the ON resistance of the shunt FETs S11-S1mis set to 75 Ω, the resistor Rtem1is not needed. This also applies to the resistor Rtem2.

Thus, in the semiconductor switch1a, the ground terminal of the switch section2ais split into the first ground terminal GND1, GND2and the second ground terminal GND3, GND4, and the first and second capacitor C1-C3are separately provided between the first and second ground terminal GND1-GND4.

As described below, this can suppress isolation degradation due to bonding wire parasitic inductance.

FIG. 5is a graph of a simulation result for isolation of the semiconductor switch shown inFIG. 4.

FIG. 5shows the relationship between bonding wire parasitic inductance and the isolation between the second terminals RF1, RF2at a frequency of 1 GHz.

It shows the case where the capacitances of the first capacitors C1, C2and the second capacitor C3are all set to 0.4 pF, and the case where they are 0 pF, that is, the first and second capacitor C1, C2, C3are absent.

As shown inFIG. 5, in the case where the capacitances of the first and second capacitor C1, C2, C3are 0.4 pF, isolation degradation is completely suppressed even if there is a parasitic inductance of approximately 1 nH.

Furthermore, in the controller section3, the drivers4a,4bare independently provided at the respective second terminals (respective ports). Thus, interference of radio frequency signals superposed on each control signal with other control signals is avoided, and isolation can be improved. Furthermore, because the switch section2aincludes the first and second capacitor C1, C2, C3, isolation degradation due to the effect of parasitic inductance is suppressed, and isolation can be improved.

FIG. 6is a block diagram illustrating the configuration of a semiconductor switch according to the embodiment of the invention.

As shown inFIG. 6, the semiconductor switch1bhas a configuration in which the switch section2ashown inFIG. 4is replaced by a switch section2b. The switch section2bis similar to the switch section2aexcept that the first and second capacitor C1, C2, C3, of the switch section2aare replaced by ESD protection elements ESD1, ESD2, ESD3, respectively.

The ESD protection element, such as series connected pn-junction diodes, has a parasitic capacitance of approximately 0.4 pF. Hence, the semiconductor switch1bachieves an effect similar to that of the semiconductor switch1ashown inFIG. 4. Furthermore, it has the advantage over the semiconductor switch1aof enhancing ESD breakdown voltage between ground pads of the first and second ground terminal GND1-GND4.

Here, the controller section3is similar to that of the semiconductor switch1a, and illustratively configured as shown inFIG. 2.

FIG. 7is a block diagram illustrating the configuration of a semiconductor switch according to the embodiment of the invention.

As shown inFIG. 7, the semiconductor switch1chas a configuration in which the switch section2ashown inFIG. 4is replaced by a switch section2c. The switch section2chas a configuration in which the second ground terminals GND3, GND4of the switch section2aare connected to each other. That is, the semiconductor switch1cis similar to the semiconductor switch1ashown inFIG. 4except that the second capacitor C3is short-circuited.

A common, second ground terminal GND3is used as the ground of the third FETs S21-S2m, S31-S3mconnected to the connection nodes N1and N2. The first ground terminals GND1, GND2are split as in the semiconductor switch1ashown inFIG. 5. Furthermore, first capacitors C1, C2are provided, respectively, between the first ground terminal GND1and the second ground terminal GND3and between the first ground terminal GND2and the second ground terminal GND3.

This configuration can suppress isolation degradation due to bonding wire parasitic inductance.

FIG. 8is a graph of a simulation result for isolation of the semiconductor switch based on the switch section shown inFIG. 7.

FIG. 8shows the relationship between bonding wire parasitic inductance and the isolation between the second terminals RF1, RF2at a frequency of 1 GHz.

It shows the case where the capacitances of the first capacitors C1, C2are all set to 0.4 pF, and the case where they are 0 pF, that is, the first capacitors C1, C2are absent.

As shown inFIG. 8, in the case where the capacitances of the first capacitors C1, C2are 0.4 pF, isolation degradation due to parasitic inductance is suppressed.

Although the effect of suppressing isolation degradation is slightly inferior to that of the semiconductor switch is shown inFIG. 4, an advantage over the semiconductor switch1ais that the number of ground terminals of the switch section2cis reduced to three.

Thus, the semiconductor switch is can suppress isolation degradation due to the effect of parasitic inductance by bonding wires.

Here, the controller section3is similar to that of the semiconductor switch1a, and illustratively configured as shown inFIG. 2.

FIG. 9is a block diagram illustrating the configuration of a semiconductor switch according to the embodiment of the invention.

As shown inFIG. 9, the semiconductor switch1dhas a configuration in which the switch section2cshown inFIG. 7is replaced by a switch section2d. The switch section2dis similar to the switch section2cexcept that the first capacitors C1, C2of the switch section2care replaced by ESD protection elements ESD1, ESD2, respectively.

As described with reference toFIG. 6, the ESD protection element has a parasitic capacitance of approximately 0.4 pF. Hence, the semiconductor switch1dachieves an effect similar to that of the semiconductor switch1cshown inFIG. 7. Furthermore, it has the advantage over the semiconductor switch is of enhancing ESD breakdown voltage between ground pads of the first and second ground terminal GND1-GND3.

The semiconductor switch1dcan suppress isolation degradation due to the effect of parasitic inductance by bonding wires.

Here, the controller section3is similar to that of the semiconductor switch1a, and illustratively configured as shown inFIG. 2.

FIG. 10is a schematic view illustrating the configuration of the semiconductor switch according to the embodiment of the invention.

FIG. 10schematically shows the state in which the semiconductor switch substrate18is mounted on a package21. The semiconductor switch1ashown inFIG. 4is illustratively provided on the semiconductor switch substrate18.

As shown inFIG. 10, the semiconductor switch substrate18is placed on the bed22of the package21.

The semiconductor switch substrate18has a rectangular planar shape having four sides. Along one side are placed pads (a control pad, a first pad, and a supply pad) for connecting the external control terminal IN, the first terminal RFcom, and the power supply terminal (power supply voltage Vdd) to leads24a,24b,24cof the package21, respectively. The pads (the control pad, the first pad, and the supply pad) are bonded to the leads24a-24cby bonding wires23a-23c, respectively. It is noted that inFIG. 10, the pads (the control pad, the first pad, and the supply pad) are labeled with the same reference numerals as the corresponding terminals.

Ground pads of the first ground terminal GND1, the second ground terminal GND3, the second ground terminal GND4, and the first ground terminal GND2are juxtaposed along another side opposed to the side where the first pad of the first terminal RFcom is located. Furthermore, second pads of the second terminals RF1, RF2are provided on both sides next to the first and second ground terminals GND1-GND4.

Furthermore, the ground pad of the first ground terminal GND1is bonded to the bed22of the package21by a bonding wire23g. Likewise, each ground pad of the first and second ground terminal GND2-4is bonded to the bed22. Thus, no ESD breakdown occurs in the capacitor element between the first ground terminal GND1and the second ground terminal GND3, the capacitor element between the second ground terminals GND3, GND4, and the capacitor element between the second ground terminal GND4and the first ground terminal GND2.

Furthermore, the second pads of the second terminals RF1, RF2are separately bonded to leads24d,24e.

Such placement of the first pad, the ground pads, and second pads on the semiconductor switch substrate18can prevent isolation degradation due to packaging.

Although the parasitic inductance existing in the grounding lead25gof the package21tends to degrade isolation, the degradation can be suppressed by suitably setting the value of the first and second capacitor C1, C2, C3.

FIG. 11is a schematic view illustrating the configuration of the semiconductor switch according to the embodiment of the invention.

FIG. 11schematically shows the state in which the semiconductor switch substrate18is mounted on a package21. The semiconductor switch1bshown inFIG. 6is illustratively provided on the semiconductor switch substrate18.

As shown inFIG. 11, the semiconductor switch substrate18is placed on the bed22aof the package21.

In the planar configuration of the bed22a, grounding leads25a,25b,25care provided between the lead24aand the lead24b, and between the lead24band the lead24c. Furthermore, the grounding lead25gbetween the lead24eand the lead24din the bed22does not exist, but the package21separately includes leads24f-24i. Ground pads of the first and second ground terminal GND1-GND4are separately bonded to the leads24f-24i. The rest is similar to the bed22of the package21shown inFIG. 10.

Pads (a control pad, a first pad, and a supply pad) of the external control terminal IN, the first terminal RFcom, and the power supply terminal (supply voltage Vdd) are placed along one side of the semiconductor switch substrate18. A second pad of the second terminal RF1, ground pads of the first and second ground terminals GND1-GND4, and a second pad of the second terminal RF2are placed along another side opposed to the side where the first pad of the first terminal RFcom is located.

Because the ground pads of the first and second ground terminals GND1-GND4are separately connected to the different leads24f-24iof the package21, no isolation degradation occurs due to the parasitic inductance of the leads. Furthermore, ESD protection elements ESD1-ESD3are separately provided between the first ground terminal GND1and the second ground terminal GND3, between the second ground terminals GND3and GND4, and between the second ground terminal GND4and the first ground terminal GND2. Hence, no ESD breakdown occurs even if high voltage is applied between the ground terminals, that is, the leads24f-24i.

Such placement of the first pad, the ground pads, and the second pads can prevent isolation degradation due to packaging.

Although the foregoing has described the case where the semiconductor switch1bis mounted on the bed22aof the package21, the semiconductor switch1dcan be mounted likewise.

FIG. 12is a schematic view illustrating the configuration of the semiconductor switch according to the embodiment of the invention.

FIG. 12schematically shows the state in which the semiconductor switch substrate18is mounted on a package21. The semiconductor switch1cshown inFIG. 7is illustratively provided on the semiconductor switch substrate18. That is, in this configuration, the semiconductor switch1ais replaced by the semiconductor switch1c.

The semiconductor switch substrate18has a rectangular planar shape having four sides. Along one side are placed pads (a control pad, a first pad, and a supply pad) for connecting the external control terminal IN, the first terminal RFcom, and the power supply terminal (supply voltage Vdd) to leads24a,24b,24cof the package21, respectively. The pads (the control pad, the first pad, and the supply pad) are bonded to the leads24a-24cby bonding wires23a-23c, respectively.

Ground pads of the first ground terminal GND1, the second ground terminal GND3, and the first ground terminal GND2are juxtaposed along another side opposed to the side where the first pad of the first terminal RFcom is located. Furthermore, second pads of the second terminals RF1, RF2are provided on both sides next to the first and second ground terminals GND1-GND3.

Furthermore, the ground pad of the first ground terminal GND1is bonded to the bed22of the package21by a bonding wire23g. Likewise, each ground pad of the first and second ground terminal GND2-3is bonded to the bed22. Thus, no ESD breakdown occurs in the capacitor element between the first ground terminal GND1and the second ground terminal GND3, and the capacitor element between the second ground terminal GND3and the first ground terminal GND2.

Furthermore, the second pads of the second terminals RF1, RF2are separately bonded to leads24d,24e.

Such placement of the first pad, the ground pads, and the second pads on the semiconductor switch substrate18can prevent isolation degradation due to packaging.

Although the parasitic inductance existing in the grounding lead25gof the package21tends to degrade isolation, the degradation can be suppressed by suitably setting the value of the first capacitors C1, C2.

FIG. 13is a schematic view illustrating the configuration of the semiconductor switch according to the embodiment of the invention.

FIG. 13schematically shows the state in which the semiconductor switch substrate18is mounted on a package21. The semiconductor switch1dshown inFIG. 9is illustratively provided on the semiconductor switch substrate18.

As shown inFIG. 13, the semiconductor switch substrate18is placed on the bed22bof the package21.

In the planar configuration of the bed22b, grounding leads25a,25bare provided between the lead24aand the lead24b, and between the lead24band the lead24c, respectively. Furthermore, besides the grounding lead25gbetween the lead24eand the lead24din the bed22, the package21additionally includes leads24f,24g. Ground pads of the first and second ground terminal GND1-GND3are separately bonded to the lead24f, the grounding lead25g, and the lead24g. The rest is similar to the bed22of the package21shown inFIG. 10.

The ground pads of the first and second ground terminal GND1-GND3are juxtaposed along another side opposed to the side where a first pad of the first terminal RFcom of the semiconductor switch substrate18is located. Furthermore, second pads of the second terminals RF1, RF2are provided on both sides next to them. Such placement of the first pad, the ground pads, and the second pads can prevent isolation degradation due to packaging.

Because the ground pads of the first ground terminals GND1, GND2are connected to the separate leads24f,24gof the package21, respectively, no isolation degradation occurs due to the parasitic inductance of the leads. Furthermore, ESD protection elements ESD1, ESD2are provided, respectively, between the first ground terminal GND1and the second ground terminal GND3, and between the second ground terminal GND3and the first ground terminal GND2. Hence, no ESD breakdown occurs even if high voltage is applied between the ground terminals, that is, between the lead24f, the grounding lead25g, and the lead24g.

Although the foregoing has described the case where the semiconductor switch1dis mounted on the bed22bof the package21, the semiconductor switch1bcan be mounted likewise.

Returning again toFIG. 2, in the semiconductor switch1, the controller section3includes two drivers4a,4b.

Thus, by providing the drivers4a,4bindependently at the respective second terminals (respective ports), interference of radio frequency signals superposed on each control signal with other control signals is avoided. Hence, isolation is improved.

FIG. 14is a circuit diagram illustrating the configuration of a semiconductor switch according to the embodiment of the invention.

As shown inFIG. 14, the semiconductor switch1eincludes a switch section2and a controller section3a. These are formed in the same substrate18(semiconductor switch substrate) to provide a one-chip structure.

The semiconductor switch1ehas a configuration in which the controller section3of the semiconductor switch1shown inFIG. 1is replaced by the controller section3a.

The controller section3aswitches the connection state of the switch section2. It is noted that the controller section3amay be part of a circuit for controlling the switch section2.

In the controller section3a, the first control terminal Con1a, the second control terminal Con1b, the first control terminal Con2a, and the second control terminal Con2bare independently driven by inputs at external control terminals IN1-IN4.

As an illustrative configuration, four drivers, not shown, can be provided so that signals inputted to the external control terminals IN1-IN4are each level-shifted to independently drive the first and second control terminals Con1a-Con2b.

Hence, isolation can be improved.

Furthermore, the semiconductor switch1eallows a total of 16 types of switching because the first and second control terminals Con1a-Con2bcan be driven independently.

That is, a total of 16 types of switching can be implemented by providing a binary value of high level or low level independently to the external control terminals IN1-IN4.

If such states are possible, then as shown inFIG. 15, for instance, an SP4T switch can be constructed by juxtaposing two SPDT switches SW1, SW2. Here, the SPDT switches SW1, SW2can each be based on the semiconductor switch1e.

As shown inFIG. 15, the first terminal RFcom1of the SPDT switch SW1and the first terminal RFcom2of the SPDT switch SW2are connected to the common terminal RFcom of the SP4T switch. The second terminals RF1, RF2of the SPDT switch SW1and the second terminals RF3, RF4of the SPDT switch SW2each serve as a radio frequency terminal of the SP4T switch.

For instance, for conduction between the second terminal RF1and the common terminal RFcom, the conducting state is established between the second terminal RF1and the first terminal RFcom1in the SPDT switch SW1. Simultaneously, two through FETs connected to the second terminals RF3, RF4of the SPDT switch SW2are both turned off.

Here, in such a configuration for independently driving all the first and second control terminals Con1a-Con2b, the number of external control terminals IN1-IN4increases. Even an SPDT like the semiconductor switch1erequires four, and the number exponentially increases with the increase of the number of first and second terminals.

FIG. 16is a block diagram illustrating the configuration of a semiconductor switch according to the embodiment of the invention.

As shown inFIG. 16, the semiconductor switch if includes a switch section2and a controller section3b. These are formed in the same substrate18(semiconductor switch substrate) to provide a one-chip structure.

The semiconductor switch if has a configuration in which the controller section3of the semiconductor switch1shown inFIG. 1is replaced by the controller section3b.

The controller section3bswitches the connection state of the switch section2. It is noted that the controller section3bmay be part of a circuit for controlling the switch section2.

In the controller section3b, the first control terminal Con1ais driven by an input at an external control terminal IN1. Simultaneously, the second control terminal Con1bis driven by the inverted signal of the signal inputted to the external control terminal IN1. Furthermore, the first control terminal Con2ais driven by an input at an external control terminal IN2. Simultaneously, the second control terminal Con2bis driven by the inverted signal of the signal inputted to the external control terminal IN2.

That is, in the semiconductor switch if, isolation degradation is suppressed by providing drivers4c,4dat the second terminals RF1, RF2, respectively. Furthermore, the number of external control terminals required is reduced to the number of second terminals. It is noted thatFIG. 16does not show the input interface circuit for matching the signal level between the external control terminal IN1, IN2and the driver4c,4d.

The semiconductor switch if can establish the following four states in the switch section2.

The first state corresponds to IN1=high level and IN2=low level, establishing the conducting state between the second terminal RF1and the first terminal RFcom, and the blocking state between the second terminal RF2and the first terminal RFcom.

The second state corresponds to IN1=low level and IN2=high level, establishing the blocking state between the second terminal RF1and the first terminal RFcom, and the conducting state between the second terminal RF2and the first terminal RFcom.

The third state corresponds to IN1=low level and IN2=low level, establishing the blocking state both between the second terminal RF1and the first terminal RFcom, and between the second terminal RF2and the first terminal RFcom.

The fourth state corresponds to IN1=high level and IN2=high level, establishing the conducting state both between the second terminal RF1and the first terminal RFcom, and between the second terminal RF2and the first terminal RFcom.

In the foregoing, the first and second states are the two states of the SPDT switch shown inFIG. 1.

The third state is the state in which the impedance seen from the first terminal RFcom toward the switch is high. Hence, it is required in such cases where the semiconductor switch if is wire-connected to the first terminal RFcom of another switch.

The fourth state implements the conducting state among all the radio frequency terminals, including the second terminals RF1, RF2, and the first terminal RFcom.

Thus, the semiconductor switch if can suppress isolation degradation. Furthermore, a multifunctional switch can be constructed with a small number of external control terminals.

FIG. 17is a circuit diagram illustrating the configuration of the controller section of the semiconductor switch if shown inFIG. 16.

As shown inFIG. 17, the controller section3chas a configuration including two inverted/non-inverted signal generators11a,11b, which produce outputs to level shifters4a,4b, respectively. The rest is similar to the controller section3shown inFIG. 2. It is noted that the input interface circuit is not shown.

As shown inFIG. 17, the signal inputted to the external control terminal IN1is differentially inputted to the driver4athrough the inverted/non-inverted signal generator11a. The driver4adrives the first and second control terminal Con1a, Con1bof the through FETs and shunt FETs connected to the second terminal RF1.

The signal inputted to the external control terminal IN2is differentially inputted to the driver4bthrough the inverted/non-inverted signal generator11b. The driver4bdrives the first and second control terminal Con2a, Con2bof the through FETs and shunt FETs connected to the second terminal RF2.

The number of external control terminals can be further reduced by using multi-valued logic for the input signal to the external control terminal.

FIG. 18is a block diagram illustrating the configuration of a semiconductor switch according to the embodiment of the invention.

As shown inFIG. 18, the semiconductor switch1gincludes a switch section2and a controller section3d. These are formed in the same substrate18(semiconductor switch substrate) to provide a one-chip structure.

The semiconductor switch1ghas a configuration in which the controller section3of the semiconductor switch1shown inFIG. 1is replaced by the controller section3d.

In the controller section3d, a three-valued logic signal is inputted to the external control terminal IN. The first and second control terminals Con1a-Con2bare driven by the controller section3din accordance with the signal inputted to the external control terminal IN.

The controller section3dincludes, separately, a driver for driving the first control terminal Con1aand the second control terminal Con1b, and a driver for driving the first control terminal Con2aand the second control terminal Con2b.

The following three states can be implemented.

The first state establishes the conducting state between the second terminal RF1and the first terminal RFcom, and the blocking state between the second terminal RF2and the first terminal RFcom.

The second state establishes the conducting state between the second terminal RF2and the first terminal RFcom, and the blocking state between the second terminal RF1and the first terminal RFcom.

The third state is other than the above first and second state, and can be designed as needed. For instance, it is the state of conducting both between the second terminal RF1and the first terminal RFcom, and between the second terminal RF2and the first terminal RFcom, or the state of blocking both between the second terminal RF1and the first terminal RFcom, and between the second terminal RF2and the first terminal RFcom.

The semiconductor switch1gcan improve isolation.

Furthermore, a multifunctional switch can be constructed with a small number of external control terminals.

FIG. 19is a block diagram illustrating the configuration of a semiconductor switch according to the embodiment of the invention.

As shown inFIG. 19, the semiconductor switch1hincludes a switch section2and a controller section3e. These are formed in the same substrate18(semiconductor switch substrate) to provide a one-chip structure.

The semiconductor switch1hhas a configuration in which the controller section3dof the semiconductor switch1gshown inFIG. 18is replaced by the controller section3e.

The controller section3eis an example of the controller section3d.

The signal inputted to the external control terminal IN can assume three values of low level, intermediate level, and high level, where

the low level ranges from 0 to V1,

the intermediate level ranges from V1to V2, and

the high level ranges from V2to Vdd.

It is assumed that 0<V1<V2<Vdd, and Vdd is the supply voltage. Although not shown, the power supply of each logic gate is supplied with the supply voltage Vdd.

The external control terminal IN is connected to the input terminal of the inverter INV1. The output of the inverter INV1is inputted to the inverter INV2.

Signals opposite in polarity to each other are inputted to the first and second control terminal Con1a, Con1bwhich drive the through and shunt FETs on the second terminal RF1side. The outputs of the inverters INV1and INV2are inputted to the first control terminal Con1aand the second control terminal Con1b, respectively. The inverters INV1, INV2constitute one driver.

Signals opposite in polarity to each other are outputted to the first and second control terminal Con2a, Con2bwhich drive the through and shunt FETs on the second terminal RF2side. The output of the selector13and the output of the inverter INV3are inputted to the first control terminal Con2aand the second control terminal Con2b, respectively. The selector13and the inverter INV3constitute one driver. Thus, the controller section3eincludes two drivers.

The selector13is a circuit for selecting the input signal to the first control terminal Con1aor the second control terminal Con1bin accordance with a select signal SEL.

The select signal SEL is generated by an intermediate logic level detection circuit12.

The intermediate logic level detection circuit12is composed of inverters INV4, INV5, and an exclusive OR circuit EXOR.

The input signal to the external control terminal IN is inputted to each of the inverters INV4, INV5. The outputs of the inverters INV4, INV5are inputted to the exclusive OR circuit EXOR, whose output serves as the select signal SEL.

The logic threshold of the inverter INV4is V1, and the logic threshold of the inverter INV5is V2.

The intermediate logic level detection circuit12is operated as follows.

When the input to the external control terminal IN is low level, the inverters INV4, INV5both output high level. The output of the exclusive OR circuit EXOR assumes low level, and the select signal SEL assumes low level.

When the input to the external control terminal IN is high level, the inverters INV4, INV5both output low level. The output of the exclusive OR circuit EXOR assumes low level, and the select signal SEL assumes low level.

When the input to the external control terminal IN is intermediate level, the inverter INV4outputs low level, and the inverter INV5outputs high level. The output of the exclusive OR circuit EXOR assumes high level, and the select signal SEL assumes high level.

Hence, when the input to the external control terminal IN is low level or high level, the select signal SEL assumes low level. The selector13selects the signal of the second control terminal Con1bfor output. The output signal serves as an output to the first control terminal Con2a, hence achieving the function of a normal SPDT switch.

More specifically, when the input to the external control terminal IN is high level, the conducting state is established between the second terminal RF1and the first terminal RFcom, and the blocking state is established between the second terminal RF2and the first terminal RFcom. When the input to the external control terminal IN is low level, the conducting state is established between the second terminal RF2and the first terminal RFcom, and the blocking state is established between the second terminal RF1and the first terminal RFcom.

On the other hand, when the input to the external control terminal IN is intermediate level, the select signal SEL assumes high level. The selector13selects the signal of the first control terminal Con1afor output. The output signal serves as an output to the first control terminal Con2a, hence bringing the two through FETs into the same state. Here, the state of the shunt FETs is opposite to that of the through FETs.

Hence, two cases are possible. In one case, the two through FETs are both turned on, and the two shunt FETs are both turned off. In the other case, the two through FETs are both turned off, and the two shunt FETs are both turned on. These cases are determined by the logic threshold of the inverter INV1.

The logic threshold of the inverter INV1is set to V1or V2.

When the logic threshold of the inverter INV1is set to V1, the inverter INV1identifies the input signal as high level. Hence, the two through FETs are both turned on, and the two shunt FETs are turned off.

When the logic threshold of the inverter INV1is set to V2, the inverter INV1identifies the input signal as low level. Hence, the two through FETs are both turned off, and the two shunt FETs are turned on.

FIG. 20is a circuit diagram illustrating the configuration of the controller section of the semiconductor switch shown inFIG. 18.

As shown inFIG. 20, the controller section3fis an example of the controller section3dof the semiconductor switch1gshown inFIG. 18.

The controller section3fincludes drivers4a,4b, a negative voltage generator (voltage generator)5a, an inverted/non-inverted signal generator11c, and an inverter INV8. In this configuration, the negative voltage generator (voltage generator)5and the inverted/non-inverted signal generator11of the controller section3shown inFIG. 2are replaced by the negative voltage generator (voltage generator)5aand the inverted/non-inverted signal generator11c, respectively, and the inverter INV8is added. It is noted that the input interface circuit is not shown.

In the negative voltage generator (voltage generator)5a, an NMOS N1is added to the first-stage current mirror of the ring oscillator6a. The enable signal Enable to the gate of the NMOS N1allows the ring oscillator6ato be switched to the oscillating or halt state. When the enable signal Enable is low level, the NMOS N1is turned off, and the ring oscillator6astops oscillation. When the enable signal Enable is high level, the NMOS N1is turned on, and the ring oscillator6aoscillates. The enable signal Enable is generated by inverting the input signal to the external control terminal IN by the inverter INV8.

The inverted/non-inverted signal generator11cis composed of series connected inverters INV6, INV7, and allows the signal inputted to the external control terminal IN to be differentially outputted to the drivers4a,4b.

The signal inputted to the external control terminal IN can assume three values of low level, intermediate level, and high level, where

the low level ranges from 0 to V1,

the intermediate level ranges from V1to V2, and

the high level ranges from V2to Vdd.

It is assumed that 0<V1<V2<Vdd, and Vdd is the power supply voltage. Although not shown, the power supply of each logic gate, such as the inverter INV8, is supplied with the power supply voltage Vdd.

The logic threshold of the inverter INV6is V1, and the logic threshold of the inverter INV8is V2. The logic threshold of the inverter INV7is set to generally Vdd/2.

This configuration allows the controller section3fto have a normal operation mode and a sleep mode. Here, the normal operation mode is a mode in which the SPDT switch performs the normal switching operation. The sleep mode is a mode in which the ring oscillator6astops operation (oscillation) and does not perform the switch function.

In the normal operation mode, low level and intermediate level signal are supplied to the external control terminal IN. Because the logic threshold of the inverter INV8is V2, the inverter INV8identifies its input as low level in the normal operation mode. The output of the inverter INV8, or enable signal Enable, assumes high level (=Vdd). Because the enable signal Enable is high level, the NMOS N1in the ring oscillator6ais turned on. Thus, the current mirror is operated, and the ring oscillator6aperforms its function.

Furthermore, in the normal operation mode, the low level and intermediate level signal supplied to the external control terminal IN are identified by the inverter INV6as low level and high level, respectively.

For instance, when a high level signal is supplied to the external control terminal IN, a low level signal from the inverter INV6and a high level signal from the inverter INV7are outputted to the drivers4a,4b.

Here, the first control terminal Con1ais subjected to the ON potential Von (=Vdd), and the second control terminal Con2bis subjected to the ON potential Von. Furthermore, the second control terminal Con1bis subjected to the OFF potential Voff (=Vn), and the first control terminal Con2ais subjected to the OFF potential Voff.

In the sleep mode, a high level signal is supplied to the external control terminal IN. The inverter INV8identifies its input as high level. The output of the inverter INV8, or enable signal Enable, assumes low level (=0 V). Because the enable signal Enable is low level, the NMOS N1in the ring oscillator6ais turned off, and the current mirror is not operated. Hence, the ring oscillator6adoes not perform its function, and no power consumption occurs.

In the foregoing, the negative voltage generator (voltage generator)5is taken as an example to describe the sleep mode. However, the voltage generator5may include a positive voltage generator for generating a positive potential higher than the power supply voltage Vdd and supplying it to the drivers4a,4b.

In the foregoing, the SPDT switch is taken as an example to describe the embodiment of the invention. However, a kPIT switch can be constructed likewise, where k, l are natural numbers.

The embodiments of the invention have been described with reference to examples. However, the invention is not limited to these examples. For instance, various specific configurations of the components constituting the semiconductor switch are encompassed within the scope of the invention as long as those skilled in the art can similarly practice the invention and achieve similar effects by suitably selecting such configurations from conventionally known ones.

Furthermore, any two or more components of the examples can be combined with each other as long as technically feasible, and such combinations are also encompassed within the scope of the invention as long as they fall within the spirit of the invention.

Furthermore, those skilled in the art can suitably modify and implement the semiconductor switch described above in the embodiments of the invention, and all the semiconductor switches thus modified are also encompassed within the scope of the invention as long as they fall within the spirit of the invention.

Furthermore, those skilled in the art can conceive various modifications and variations within the spirit of the invention, and it is understood that such modifications and variations are also encompassed within the scope of the invention.