SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME

A semiconductor device and a data storage system including the same, the semiconductor device including: a first structure including a peripheral circuit; and a second structure, including: a pattern structure; an upper insulating layer; a stack structure between the first structure and the pattern structure and including first and second stack portions spaced apart from each other, the first and second stack portions respectively including horizontal conductive layers and interlayer insulating layers alternately stacked; separation structures penetrating through the stack structure; memory vertical structures penetrating through the first stack portion; and a contact structure penetrating through the second stack portion, the pattern structure, and the upper insulating layer, wherein the contact structure includes a lower contact plug penetrating through at least the second stack portion and an upper contact plug contacting the lower contact plug and extending upwardly to penetrate through the pattern structure and the upper insulating layer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2020-0151779 filed on Nov. 13, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference for all purposes.

BACKGROUND

The present inventive concept relates to a semiconductor device and a data storage system including the same.

2. Description of Related Art

An electronic system required to store data may require a semiconductor device capable of storing high-capacity data. Accordingly, research is being conducted on a method of increasing the data storage capacity of the semiconductor device. For example, as one of the methods of increasing the data storage capacity of the semiconductor device, a semiconductor device including memory cells arranged in three dimensions instead of memory cells arranged in two dimensions has been proposed.

SUMMARY

Example embodiments provide a semiconductor device having improved integration and reliability.

Example embodiments provide a data storage system including the semiconductor device.

According to example embodiments, a semiconductor device includes: a first structure including a peripheral circuit; and a second structure disposed on the first structure and bonded to the first structure, wherein the second structure includes: a pattern structure; an upper insulating layer disposed on the pattern structure; a stack structure disposed between the first structure and the pattern structure and including a first stack portion and a second stack portion spaced apart from each other in a horizontal direction, the first and second stack portions respectively including horizontal conductive layers and interlayer insulating layers alternately stacked in a vertical direction; separation structures penetrating through the stack structure and separating the stack structure; memory vertical structures penetrating through the first stack portion of the stack structure; and a contact structure penetrating through the second stack portion, the pattern structure, and the upper insulating layer. The contact structure includes a lower contact plug penetrating through at least the second stack portion of the stack structure and an upper contact plug in contact with the lower contact plug and extending upwardly to penetrate through the pattern structure and the upper insulating layer.

According to example embodiments, a semiconductor device includes: a first structure including a peripheral circuit; and a second structure disposed on the first structure and bonded to the first structure, wherein the second structure includes: a pattern structure; an upper insulating layer disposed on the pattern structure; word lines disposed between the pattern structure and the first structure, and stacked r in a vertical direction; dummy horizontal conductive layers disposed between the pattern structure and the first structure, and stacked in the vertical direction; memory vertical structures penetrating through the word lines in the vertical direction and in contact with the pattern structure, separation structures penetrating through the word lines in the vertical direction and in contact with the pattern structure; and a contact structure penetrating through the dummy horizontal conductive layers, the pattern structure, and the upper insulating layer in the vertical direction. The dummy horizontal conductive layers are electrically isolated.

According to example embodiments, a data storage system includes a semiconductor device including a first structure including a peripheral circuit and a second structure disposed on the first structure and including a data storage layer storing data; and a controller electrically connected to the semiconductor device, wherein the second structure includes: a pattern structure; an upper insulating layer disposed on the pattern structure; word lines disposed between the pattern structure and the first structure, and stacked in a vertical direction; dummy horizontal conductive layers disposed between the pattern structure and the first structure, and stacked in the vertical direction; memory vertical structures penetrating through the word lines in the vertical direction and in contact with the pattern structure; separation structures penetrating through the word lines in the vertical direction and in contact with the pattern structure; and a contact structure penetrating through the dummy horizontal conductive layers, the pattern structure, and the upper insulating layer in the vertical direction, and wherein the dummy horizontal conductive layers are electrically isolated.

DETAILED DESCRIPTION

Hereinafter, terms such as ‘upper’, ‘upper portion’, ‘upper surface’, ‘lower’, ‘lower portion’, ‘lower surface’ and ‘side surface’ are indicated by reference numerals and may be understood as referring to drawings, unless otherwise indicated.

FIG. 1is a schematic perspective view illustrating a semiconductor device according to an example embodiment;FIG. 2is an enlarged plan view illustrating a region indicated by “A” inFIG. 1;FIG. 3Ais a cross-sectional view illustrating a region taken along lines I-I′ and II-II′ ofFIG. 2;FIG. 3Bis a cross-sectional view illustrating a region taken along line III-III′ ofFIG. 1;FIG. 3Cis a cross-sectional view illustrating a region taken along line IV-IV′ ofFIG. 1; andFIG. 3Dis an enlarged cross-sectional view illustrating a portion indicated by “B” inFIG. 3A.

Referring toFIGS. 1, 2, and 3A to 3D, a semiconductor device1according to an example embodiment may include a first structure3and a second structure103disposed on the first structure3. In some embodiments, the first structure3may be disposed on and bonded to the second structure103.

The first structure3may be a first semiconductor chip including a peripheral circuit, and the second structure103may be a second semiconductor chip including a memory cell array region in which memory cells capable of storing data are arranged in three dimensions.

In an example embodiment, the first structure3may include: a semiconductor substrate6; an isolation region9sdisposed on the semiconductor substrate6and defining a peripheral active region9a; a peripheral circuit12formed on the semiconductor substrate6; first bonding pads18electrically connected to the peripheral circuit12; and a first insulating structure21disposed on the semiconductor substrate6, covering the peripheral circuit12and having an upper surface coplanar with upper surfaces of the first bonding pads18. Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein, encompass near identicality including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.

The peripheral circuit12may include a circuit device14such as a transistor including a peripheral gate14aand a peripheral source/drain14b, and a circuit interconnection16electrically connected to the circuit device14. The circuit device14may further include a circuit element such as a resistor and a capacitor in addition to an active element such as the transistor.

The circuit interconnection16may be electrically connected to the first bonding pads18. Therefore, the circuit interconnection16may electrically connect the first bonding pads18and the peripheral circuit12to each other.

In an example embodiment, the first bonding pads18may include a metal, for example, copper.

In an example embodiment, the second structure103may include a pattern structure109, a stack structure113, separation structures157s, memory vertical structures143c, a contact structure190, second insulating structures136,111, and177, and second bonding pads174.

The pattern structure109may include a doped silicon layer. For example, the pattern structure109may include a polysilicon layer having an N-type conductivity.

The stack structure113may be disposed between the pattern structure109and the first structure3.

In an example embodiment, the stack structure113may include a plurality of stacked groups113Ga,113Gb, and113D. For example, the plurality of stacked groups113Ga,113Gb, and113D of the stack structure113may include the first stacked group113Ga and the second stacked group113Gb and the dummy stacked group113D, which are spaced apart from one another in a horizontal direction. For example, the first stacked group113Ga and the second stacked group113Gb may be spaced apart from each other in a first horizontal direction X. The dummy stacked group113D may be spaced apart from the first stacked group113Ga and the second stacked group113Gb in a second horizontal direction Y perpendicular to the first horizontal direction X. However, the numbers and arrangement positions of the first stacked group113Ga, the second stacked group113Gb and the dummy stacked group113D are not limited to the shape illustrated inFIG. 1and may be variously modified.

In an example embodiment, each of the first and second stacked groups (e.g., first and second stacked groups113Ga and113Gb inFIG. 1) may include a first flat region114f1and a first stepped region114s1disposed on at least one side of the first flat region114f1. The first stepped region114s1may surround the first flat region114f1.

In an example embodiment, the dummy stacked group (e.g., the dummy stacked group113D inFIG. 1) may include a second flat region114f2and a second stepped region114s2disposed on at least one side of the second flat region114f2. The second stepped region114s2may surround the second flat region114f2.

In an example embodiment, each of the first stacked group113Ga and the second stacked group113Gb may include a plurality of first stack portions113a.

In an example embodiment, at least one of the first stacked group113Ga and the second stacked group113Gb may include one or more second stack portions113b. Accordingly, the stack structure113may include the first stack portions113aand the one or more the second stack portions113b.

In an example embodiment, at least one of the second stack portions113bmay be disposed between the first stack portions113a. For example, at least one of the first stacked group113Ga and the second stacked group113Gb may include the plurality of first stack portions113a, and one second stack portion113bmay be disposed between two first stack portions113aof the plurality of first stack portions113a.

In an example embodiment, the separation structures157smay be disposed in separation trenches154spenetrating through the stack structure113and separating the stack structure113in the first horizontal direction X. Accordingly, the separation structures157smay penetrate through the stack structure113. For example, the separation structures157smay penetrate through the first stacked group113Ga of the stack structure113and may penetrate through the second stacked group113Gb of the stack structure113. Each of the separation structures157smay have a shape of a line extending in the first horizontal direction X. The separation structures157smay extend into the pattern structure109and may be in contact with the pattern structure109. The term “contact,” as used herein, refers to a direct connection (i.e., touching) unless the context indicates otherwise.

Some of the separation structures157smay penetrate through the first stacked group113Ga and divide the first stacked group113Ga into the plurality of stack portions113aand113bspaced apart from each other in the second horizontal direction Y, and some of the separation structures157smay penetrate through the second stacked group113Gb and divide the second stacked group113Gb into the plurality of stack portions113aand113bspaced apart from each other in the second horizontal direction Y.

At least one of the plurality of stack portions113aand113bspaced apart from each other in the second horizontal direction Y may be the second stack portion113b, and the plurality of stack portions may be the first stack portions113a.

In an example embodiment, each of the first and second stack portions113aand113bof the stack structure113may include interlayer insulating layers118and127and horizontal gate layers122and131, which are alternately and repeatedly stacked in a vertical direction Z. Each of the horizontal gate layers122and131may include a conductive layer. The horizontal gate layers122and131may be stacked and spaced apart from each other in the vertical direction Z.

In an example embodiment, at least some of the horizontal gate layers122and131of the first stack portion113amay be word lines. Among the horizontal gate layers122and131of the first stack portion113a, one or more upper horizontal gate layers disposed at its upper portion and/or one or more lower horizontal gate layers disposed at its lower portion may be selection gate electrodes, and a plurality of horizontal gate layers disposed between the one or plurality of upper horizontal gate layers and the one or more lower horizontal gate layers may be the word lines.

In an example embodiment, the horizontal gate layers122and131of the second stack portion113bmay be dummy horizontal conductive layers which may be electrically isolated.

In an example embodiment, the dummy stacked group113D of the stack structure113may include the interlayer insulating layers118and127and horizontal insulating layers123and132which are alternately and repeatedly stacked in the vertical direction.

In an example embodiment, each of the first and second stack portions113aand113bof the stack structure113may include a first stacked region125and a second stacked region117disposed on the first stacked region125. Here, the first stacked region125may be disposed between the second stacked region117and the first structure3.

The first stacked region125may include the first interlayer insulating layers127and the first horizontal gate layers131which are alternately and repeatedly stacked in the vertical direction Z. A lowermost layer and an uppermost layer among the first interlayer insulating layers127and the first horizontal gate layers131may each be one of the first interlayer insulating layers127.

In an example embodiment, the second stacked region117may include the second interlayer insulating layers118and the second horizontal gate layers122which are alternately and repeatedly stacked in the vertical direction. A lowermost layer and an uppermost layer among the second interlayer insulating layers118and the second horizontal gate layers122may each be one of the second interlayer insulating layers118.

The first and second horizontal gate layers131and122may have pad regions GP arranged in a step shape within the first stepped region114s1. The pad regions GP of the first and second horizontal gate layers131and122may have a shape of the step down in a direction from the first structure3toward the pattern structure109. The pad regions GP may face the first structure3.

The second structure103may further include gate contact plugs162in contact with the pad regions GP and electrically connected to the first and second horizontal gate layer131and122. For example, the gate contact plugs162may be electrically connected to the first and second horizontal gate layers131and122, which may be the selection gate electrodes and the word lines, among the first and second horizontal gate layers131and122. The gate contact plugs162may extend downward from a portion of the first and second horizontal gate layer131or122in contact with the pad regions GP. For example, the gate contact plugs162may extend from the pad regions GP toward the first structure3. The gate contact plugs162may be formed of a conductive material.

The memory vertical structures143cmay penetrate through the first stack portion113aof the stack structure113. For example, the memory vertical structures143cmay penetrate through the horizontal gate layers122and131, which may be the selection gate electrodes and word lines of the first stack portion113a, in the vertical direction Z.

In an example embodiment, the memory vertical structures143cmay extend into the pattern structure109from its portion penetrating through the first stack portion113aof the stack structure113to be in contact with the pattern structure109.

The second structure103may further include dummy vertical structures143d. The dummy vertical structures143dmay penetrate through the second stack portion113bof the stack structure113and may be in contact with the pattern structure109.

In an example embodiment, the dummy vertical structures143dmay include the same material layer as the memory vertical structures143c. For example, the dummy vertical structures143dmay be formed by substantially the same process as the memory vertical structures143c, and may have a cross-sectional structure substantially the same as the memory vertical structures143c.

In another example embodiment, the dummy vertical structures143dmay be formed by a process different from the memory vertical structures143c. For example, each of the dummy vertical structures143dmay be formed of a silicon oxide column.

The second bonding pads174may be in contact with and bonded to the first bonding pads18. The first and second bonding pads18and174may include the same conductive material, for example, copper.

In an example embodiment, the second insulating structures136,111, and177may include an outer insulating layer111disposed on a side surface of the pattern structure109, and an upper insulating layer177disposed on the pattern structure109and the outer insulating layer111. The outer insulating layer111may contact the side surface of the pattern structure109, and the upper insulating layer177may contact upper surfaces of the pattern structure109and the outer insulating layer111. The second insulating structures136,111, and177may further include a capping insulating layer136disposed on the first structure3and covering the stack structure113while surrounding side surfaces of the second bonding pads174. The pattern structure109and the outer insulating layer111may contact an upper surface of the capping insulating layer136. The upper insulating layer177may be formed of a silicon oxide layer. The capping insulating layer136may include a single material layer or multiple material layers. For example, the capping insulating layer136may be formed of a silicon oxide layer or may be formed to include a silicon oxide layer and a material having etching selectivity with the silicon oxide layer, for example, a silicon nitride layer.

The capping insulating layer136may fill a space between the stack structure113and the first structure3while surrounding each of the first stacked group113Ga, the second stacked group113Gb and the dummy stacked group113D. For example, a portion of the capping insulating layer136may fill the space between the first stacked group113Ga, the second stacked group113Gb and the dummy stacked group113D, which are spaced apart from one another.

A plurality of contact structures190may be arranged. At least some of the plurality of contact structures190may penetrate through the stack structure113, the pattern structure109, and the upper insulating layer177. Each of the plurality of contact structures190may include a lower contact structure157cand an upper contact structure183cdisposed on the lower contact structure157c.

In the following, for easier understanding, the description is made focusing on one contact structure190including a portion penetrating through the stack structure113.

The lower contact structure157cof the contact structure190may be disposed in a lower contact hole154cpassing through the second stack portion113bof the stack structure113, and the upper contact structure183cthereof may be disposed in an upper contact hole180passing through the pattern structure109and the upper insulating layer177.

In an example embodiment, the upper contact structure183cadjacent to the lower contact structure157cmay have a greater width than the lower contact structure157cadjacent to the upper contact structure183c.

The lower contact structure157cmay include a conductive lower contact plug157c2and an insulating lower spacer157c1surrounding a side surface of the lower contact plug157c2.

In an example embodiment, the lower contact plug157c2of the lower contact structure157cmay include a portion penetrating through the second stack portion113bof the stack structure113and a portion extending into the pattern structure109from the portion penetrating through the second stack portion113bof the stack structure113. Accordingly, an upper surface (e.g., the upper surface157cU inFIG. 3D) of the lower contact plug157c2may be disposed at a height level between a lower surface (e.g., the lower surface109L inFIG. 3) of the pattern structure109and an upper surface (e.g., the upper surface109U inFIG. 3D) of the pattern structure109. For example, the upper surface157cU of the lower contact plug157c2may be disposed at a level higher than the lower surface109L of the pattern structure109, and may be disposed at a level lower than the upper surface109U of the pattern structure109. In an example embodiment, a height difference between the upper surface157cU of the lower contact plug157c2and the lower surface109L of the pattern structure109may be smaller than a height difference between the upper surface157cU of the lower contact plug157c2and the upper surface109U of the pattern structure109.

The lower contact plug157c2may include a first liner layer159a1and a first pillar pattern159a2.

In an example embodiment, the first liner layer159a1may cover at least a side surface of the first pillar pattern159a2. For example, the first liner layer159a1may contact at least the side surface of the first pillar pattern159a2.

In an example embodiment, the first liner layer159a1may include a portion covering the side surface of the first pillar pattern159a2and a portion covering an upper surface of the first pillar pattern159a2. For example, the first liner layer159a1may include a portion contacting the side surface of the first pillar pattern159a2and a portion contacting an upper surface of the first pillar pattern159a2. Here, the “upper surface” of the first pillar pattern159a2may be a term referred to with reference toFIG. 3A.

The upper contact structure183cmay include an upper contact plug183c2in contact with the lower contact plug157c2and an insulating upper spacer183c1surrounding at least a side surface of the upper contact plug183c2. The insulating upper spacer183c1may contact at least the side surface of the upper contact plug183c2.

The upper contact plug183c2may be in contact with the upper surface157cU of the lower contact plug157c2and may be in contact with the side surface of the lower contact plug157c2, which is adjacent to the upper surface157cU of the lower contact plug157c2.

The upper spacer183c1may be formed of an insulating material such as silicon oxide and/or silicon nitride. The upper contact plug183c2may include at least one of a conductive material, for example, a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)) or a metal (e.g., tungsten (W), copper (Cu), or aluminum (Al)).

In an example embodiment, a thickness of the upper spacer183c1in the horizontal direction may be greater than a thickness of the lower spacer157c1in the horizontal direction.

In an example embodiment, a lower surface183cL of the upper contact plug183c2may be disposed at a level higher than the lower surface109L of the pattern structure109, and at a level lower than the upper surface109U of the pattern structure109.

Each of the separation structures157smay include an insulating separation spacer157s1and a conductive separation pattern157s2. The separation pattern157s2may include a second liner layer159b1and a second pillar pattern159b2. The second liner layer159b1may cover an upper surface of the second pillar pattern159b2while covering a side surface of the second pillar pattern159b2. For example, the second liner layer159b1may contact the upper and side surfaces of the second pillar pattern159b2. Here, the upper surface of the second pillar pattern159b2may be disposed at a height level between the lower surface109L of the pattern structure109and the upper surface109U of the pattern structure109.

In an example embodiment, the separation spacer157s1of the separation structures157sand the lower spacer157c1of the lower contact structure157cmay be formed of the same material, for example, silicon oxide and/or silicon nitride, formed by the same process.

In an example embodiment, the separation pattern157s2of the separation structures157sand the lower contact plug157c2of the lower contact structure157cmay be formed of the same conductive material and formed by the same process. For example, the first liner layer159a1of the lower contact plug157c2and the second liner layer159b1of the separation pattern157s2may include the same conductive material, for example, metal nitride (e.g., TiN, TaN, or WN), and be formed by the same process, and the first pillar pattern159a2of the lower contact plug157c2and the second pillar pattern159b2of the separation pattern157s2may include the same conductive material, for example, metal (e.g., W), and be formed by the same process. For another example, the lower contact plug157c2and the separation pattern157s2may include at least one of doped silicon, a metal-semiconductor compound, a metal nitride, and a metal.

The second structure103disposed between the stack structure113and the first structure3may further include bit lines168b, gate interconnections168g, a contact interconnection168c, bit line connection vias164b, gate connection vias164g, and a contact connection via164c. The gate interconnections168gand the contact interconnection168cmay each be referred to as the gate interconnection lines168gand the contact interconnection lines168c. The bit line connection vias164bmay be disposed between the bit lines168band the memory vertical structures143c, and may electrically connect the bit lines168band the memory vertical structures143cto each other. The bit lines168bmay not be electrically connected to the dummy vertical structures143d. The gate connection vias164gmay be disposed between the gate interconnections168gand the gate contact plugs162, and may electrically connect the gate interconnections168gand the gate contact plugs162to each other. The contact connection via164cmay be disposed between the contact interconnection168cand the lower contact plug157c2, and may electrically connect the contact interconnection168cand the lower contact plug157c2to each other. The second structure103may further include an interconnection structure171electrically connecting the bit lines168b, the gate interconnections168gand the contact interconnection168cwith the second bonding pads174. The second structure103may further include a conductive pattern193disposed on the upper insulating layer177and electrically connected to the upper contact plug183c2.

In an example embodiment, the contact structure190may be an input/output contact structure for transmitting an input/output signal of the semiconductor device1.

Next, various modified examples of the contact structure190are respectively described with reference toFIGS. 4A to 4D. Each ofFIGS. 4A to 4Dis a partially enlarged cross-sectional view corresponding to the partially enlarged cross-sectional view ofFIG. 3D, and may indicate a modified example of the portion of the contact structure190, which is illustrated inFIG. 3D. Hereinafter, the description is made focusing on a portion of the contact structure190, which may be modified, with reference toFIGS. 4A to 4D, respectively.

Referring toFIG. 4A, the modified example may provide a lower contact structure157caincluding a lower contact plug157c2aand the lower spacer157c1, and the lower contact plug157c2amay include a first pillar pattern159a2aand a first liner layer159a1asurrounding a portion of a side surface of the first pillar pattern159a2a. The first pillar pattern159a2amay extend into the upper contact plug183c2and may be in contact with the upper contact plug183c2. The upper contact plug183c2may be in contact with the upper surface157cU of the first pillar pattern159a2a, and may be in contact with a side surface of a portion of the first pillar pattern159a2a, which extends into the upper contact plug183c2.

Referring toFIG. 4B, another modified example may provide the upper contact structure183caincluding an upper contact plug183c2aand an upper spacer183c1a, and the upper spacer183c1amay surround a side surface of the upper contact plug183c2a.

In an example embodiment, a lower surface183cLa of the upper contact plug183c2amay be disposed at substantially the same level as the lower surface109L of the pattern structure109or at a level lower than the lower surface109L of the pattern structure109.

Referring toFIG. 4C, another modified example may provide the lower contact structure157casubstantially the same as that illustrated inFIG. 4Aand the upper contact structure183casubstantially the same as that described with reference toFIG. 4B. For example, the upper surface and a portion of the side surface of the first pillar pattern159a2aof the lower contact structure157cadescribed with reference toFIG. 4Amay be in contact with the upper contact plug183c2a. A portion of the first liner layer159a1aof the lower contact structure157cadescribed with reference toFIG. 4Amay be interposed between the side surface of the first pillar pattern159a2aand the upper contact plug183c2a.

Referring toFIG. 4D, another modified example may provide the upper contact structure183casubstantially the same as that described with reference toFIG. 4B.

A lower contact structure157cbmay include a lower contact plug157c2band the lower spacer157c1, and the lower contact plug157c2bmay include a first pillar pattern159a2band a first liner layer159a1bsurrounding at least a portion of a side surface of the first pillar pattern159a2b.

In an example embodiment, the first pillar pattern159a2bmay extend into the upper contact plug183c2and may be in contact with the upper contact plug183c2.

In an example embodiment, an upper surface157cU′ of the lower contact plug157c2bmay be disposed at the same height level as the lower surface109L of the pattern structure109, or at a height level lower than the lower surface109L of the pattern structure109.

Next, the description describes an example embodiment of the memory vertical structures143c.FIG. 5Ais an enlarged cross-sectional view illustrating a region indicated by “C” inFIG. 3A. Hereinafter, referring toFIG. 5A, the description is made focusing on any one of the memory vertical structures143cand describes example embodiments of the horizontal gate layers122and131and the pattern structure109.

Referring toFIGS. 3A and 5A, in an example embodiment, the pattern structure109may include a plurality of layers. For example, the pattern structure109may include a first pattern layer109a, a second pattern layer109bdisposed under and contacting the first pattern layer109a, and a third pattern layer109cdisposed under and contacting the second pattern layer109b. At least one of the first pattern layer109a, the second pattern layer109b, and the third pattern layer109cmay include a polysilicon layer. For example, each of the first pattern layer109a, the second pattern layer109b, and the third pattern layer109cmay include the polysilicon layer. At least one of the first pattern layer109a, the second pattern layer109b, and the third pattern layer109cmay include the polysilicon layer having the N-type conductivity.

The memory vertical structures143cmay penetrate through the stack structure113and extend into the pattern structure109.

The memory vertical structures143cmay include a core region149, a channel layer147, a pad pattern151, and a data storage structure145.

The channel layer147may cover the side surface and bottom surface of the core region149. The channel layer147may be formed of a semiconductor material such as silicon. For example, the channel layer147may be formed of polysilicon.

The core region149may be formed of silicon oxide or silicon oxide having a void or a seam therein.

The pad pattern151may be disposed on the core region149and in contact with the core region149and the channel layer147. The pad pattern151may be formed of polysilicon having the N-type conductivity.

In an example embodiment, the data storage structure145may cover an upper surface of the channel layer147by covering an outer side surface of the channel layer147. Here, the upper surface of the channel layer147may be the upper surface of the channel layer147as viewed with reference toFIG. 5A.

In an example embodiment, the second pattern layer109bmay penetrate through the data storage structure145and be in contact with the channel layer147, and the first and third pattern layers109aand109cmay be spaced apart from the channel layer147by the data storage structure145. The data storage structure145may include a first data storage structure145U disposed at its lower portion and a second data storage structure145L disposed at its upper portion. The first data storage structure145U may be separated from the second data storage structure145L by the second pattern layer109b.

The data storage structure145may include a first dielectric layer145a, a second dielectric layer145c, and a data storage layer145bdisposed between the first dielectric layer145aand the second dielectric layer145c. At least one of the first and second dielectric layers145aand145cmay include silicon oxide and/or a high-k dielectric.

In an example embodiment, the data storage layer145bmay include a material capable of trapping an electric charge, for example, silicon nitride. The data storage layer145bmay be a charge trap layer.

In an example embodiment, the data storage layer145bmay include regions capable of storing data in a semiconductor device such as a NAND flash memory device. For example, the data storage layer145bmay include the data storage regions capable of storing data between the gate layer, which may be the word lines among the horizontal gate layers122and131, and the channel layer147. Such data storage regions may each configure memory cells capable of storing data and may be arranged in one memory vertical structures143cin a substantially vertical direction, and the plurality of memory vertical structures143cincluding such data storage regions may be arranged in the horizontal direction. Accordingly, the plurality of memory vertical structures143cincluding the plurality of data storage regions capable of configuring the memory cells may be disposed, and the semiconductor device1may thus include a memory cell array region including the memory cells arranged in the three dimensions. Here, the memory cell array region may be defined as regions of the first and second stacked groups113Ga and113Gb in which the memory vertical structures143care disposed. For another example, the memory vertical structures143cmay include a data storage region of a memory device that stores data using a change in resistance. For example, the memory vertical structures143cmay include a data storage structure of Resistive RAM (ReRAM) including any one of silicon oxide (SiOx), aluminum oxide (AlOx), magnesium oxide (MgOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), silicon nitride (SiNx), tungsten oxide (WOx), and titanium oxide (TiOx), or a composite material including at least two of those materials. Alternatively, the memory vertical structures143cmay include a data storage structure of a PRAM including a phase change memory material such as a chalcogenide material including germanium (Ge), antimony (Sb), and/or tellurium (Te).

In the example embodiments, the memory vertical structures143cmay be referred to as a vertical structure, a vertical pattern, or the like.

Each of the horizontal gate layers122and131may include a first layer133aand a second layer133b. The first layer133amay cover the upper and lower surfaces of the second layer133band extend to a space between the memory vertical structures143cand a side surface of the second layer133b.

In an example embodiment, the first layer133amay include a dielectric material, and the second layer133bmay include a conductive material. For example, the first layer133amay include a high-k dielectric such as AlO, and the second layer133bmay include a conductive material such as titanium nitride (TiN), tungsten nitride (WN), titanium (Ti), or tungsten (W).

For another example, the first layer133amay include a first conductive material (e.g., titanium nitride (TiN) or tungsten (W)), and the second layer133bmay include a second conductive material (e.g., titanium (Ti) or tungsten (W)) different from the first conductive material.

For another example, each of the horizontal gate layers122and131may be formed of doped polysilicon, a metal-semiconductor compound (e.g., titanium silicide (TiSi), tantalum silicide (TaSi), cobalt silicide (CoSi), nickel silicide (NiSi), or tungsten silicide (WSi)), a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)) or a metal (e.g., titanium (Ti) or tungsten (W)).

As described above, the stack structure113may include the first stacked region125and the second stacked region117.

Each of the memory vertical structures143cmay include a lower vertical portion145s2penetrating through the first stacked region125and an upper vertical portion145s1penetrating through the second stacked region117.

In an example embodiment, a side surface of the lower vertical portion145s2and a side surface of the upper vertical portion145s1adjacent to each other may not be aligned in the vertical direction. Accordingly, a side surface of the memory vertical structures143cmay have a bent portion in a region between the first horizontal conductive layers131of the first stacked region125and the second horizontal gate layers122of the second stacked region117. For example, a portion of the side surface of the memory vertical structures143cmay extend in a horizontal direction, and may be coplanar with a surface of one of the second interlayer insulating layers118.

In an example embodiment, the upper vertical portion145s1of the memory vertical structures143c, which is adjacent to the lower vertical portion145s2, may have a width greater than the lower vertical portion145s2thereof, which is adjacent to the upper vertical portion145s1.

Next, a modified example of the memory vertical structures143cis described with reference toFIG. 5B.FIG. 5Bis a partially enlarged view corresponding to the partially enlarged view ofFIG. 5A. Hereinafter, the description is made focusing on the modified portion of the memory vertical structures143cdescribed with reference toFIG. 5A.

Referring toFIG. 5B, a memory vertical structures143c′ penetrating through the stack structure113and extending into the pattern structure109may include: an epitaxial channel layer144including a portion disposed in the pattern structure109, disposed at a level lower than a lower surface of at least the lowermost horizontal gate layer122L and having an upper surface disposed at a level higher than an upper surface of the next-lowest horizontal gate layer, among the horizontal gate layers122and131; a core region149′ disposed under the epitaxial channel layer144; a channel layer147′ interposed between the core region149′ and the epitaxial channel layer144and covering a side surface of the core region149′; and a data storage structure145′ covering an outer side surface of the channel layer147′. The data storage structure145′ may include the first dielectric layer145a, the second dielectric layer145c, and the data storage layer145bdisposed between the first and second dielectric layers145aand145c.

In an example embodiment, a dielectric layer152may be disposed between the lowermost horizontal gate layer122L and the epitaxial channel layer144.

In the example embodiments, the contact structure190may have a circular shape when viewed as a plane as illustrated inFIG. 1. However, the planar shape of the contact structure190is not limited to the circular shape. The description describes such a modified example of the planar shape of the contact structure190with reference toFIG. 6.FIG. 6is a plan view illustrating a modified example of the planar shape of the contact structure.

Referring toFIG. 6, a contact structure190′ may have an elongated shape in one direction, for example, an oval shape, a rectangular shape, a bar shape, or a line shape. For example, the lower contact structure157cof the contact structure190′, which includes the lower contact plug157c2and the lower spacer157c1may have the elongated shape in one direction, and the upper contact structure183cthereof, which includes the upper contact plug183c2and the upper spacer183c1may have the elongated shape in one direction. In example embodiments, the lower contact structure157cand the upper contact structure183cmay both have shapes that are elongated in the one direction.

Next, a modified example of the semiconductor device1according to an example embodiment is described with reference toFIGS. 7 and 8.FIG. 7is a schematic perspective view illustrating the modified example of the semiconductor device according to an example embodiment; andFIG. 8is a schematic cross-sectional view illustrating a region taken along line IVa-IVa′ ofFIG. 7. Hereinafter, the description is made focusing on a portion modified from the semiconductor device1described with reference toFIGS. 1 through 3D.

Referring toFIGS. 7 and 8, a semiconductor device1aaccording to an example embodiment may include the first structure3and a second structure103a. The first structure3may be substantially the same as that described with reference toFIGS. 1 through 3D. The second structure103amay include first and second gate groups113Ga and113Gb including the first stack portions113awithout including the second stack portions (e.g., the second stack portions113binFIG. 1), instead of the first and second stack groups113Ga and113Gb including the first stack portions (e.g., the first stack portions113ainFIG. 1) and the second stack portions (e.g., the second stack portions113binFIG. 1) described with reference toFIG. 1.

The second structure103amay include a dummy stacked group113D′ including a second stack portion113b′, instead of the dummy stacked group113D described with reference toFIGS. 1 through 3D.

The dummy stacked group113D′ may further include a dummy stack portion113din contact with the second stack portion113b′.

The second stack portion113b′ of the dummy stacked group113D′ may be formed of layers substantially the same as the first and second stack portions113aand113bof the first and second stacked groups113Ga and113Gb described with reference toFIGS. 1 to 3D. For example, the second stack portion113b′ of the dummy stacked group113D′ may include the interlayer insulating layers118and127and horizontal gate layers122′ and131′, which are alternately and repeatedly stacked on each other. The dummy stack portion113dof the dummy stacked group113D′ may include the interlayer insulating layers118and127and horizontal insulating layers123and132, which are alternately and repeatedly stacked on each other.

The second stack portion113b′ of the dummy stacked group113D′ may include a first stacked region125′ and a second stacked region117′ disposed on the first stacked region125′. The first stacked region125′ may include the first interlayer insulating layers127and the first horizontal gate layers131′ which are alternately and repeatedly stacked on each other, and the second stacked region117′ may include the second interlayer insulating layers118and the second horizontal gate layers122′ which are alternately and repeatedly stacked on each other.

The second structure103amay include a contact structure290having the same structure as the contact structure190described with reference toFIGS. 1 to 3D. For example, the contact structure290may include the lower contact structure157cpenetrating through the second stack portion113b′ of the dummy stacked group113D′ and the upper contact structure183cpenetrating through the pattern structure109and the upper insulating layer177. Here, the lower contact structure157cand the upper contact structure183cmay be substantially the same as the structures of the lower contact structure157cand the upper contact structure183cdescribed with reference toFIGS. 1 to 3D.

In an example embodiment, the contact structure290may be modified like any one of the modified examples of the contact structure190described with reference toFIGS. 4A to 4D and 6.

Next, another modified example of the semiconductor device1according to an example embodiment is described with reference toFIG. 9.FIG. 9is a schematic perspective view illustrating the modified example of the semiconductor device according to an example embodiment. Hereinafter, the description is made focusing on a portion modified from the semiconductor devices1and1adescribed with reference toFIGS. 1 through 8.

Referring toFIG. 9, a semiconductor device1baccording to an example embodiment may include the first structure3and a second structure103b. The first structure3may be substantially the same as that described with reference toFIGS. 1 to 3D. The second structure103bmay include: the first and second stack groups113Ga and113Gb including the first stack portions (e.g., the first stack portions113ainFIG. 1) and the second stack portions (e.g., the second stack portions113binFIG. 1) described with reference toFIG. 1; the dummy stacked group113D′ including the second stack portion113b′ described with reference toFIG. 7; the contact structure190described with reference toFIGS. 1 to 3D; and the contact structure290described with reference toFIGS. 7 and 8.

In an example embodiment, the contact structures190and290may each be modified like any one of the modified examples of the contact structure190described with reference toFIGS. 4A to 4D and 6.

In the example embodiments, the contact structure190described with reference toFIGS. 1 to 3Dmay be referred to as a first contact structure, and the contact structure290described with reference toFIGS. 7 and 8may be referred to as a second contact structure.

Next, another modified example of the semiconductor device1according to an example embodiment is described with reference toFIG. 10.FIG. 10is a cross-sectional view illustrating a region taken along line III-III′ ofFIG. 1.

Referring toFIGS. 1 and 10, the modified example may provide a semiconductor device1caccording to an example embodiment, and the second structure103may further include a third contact structure390spaced apart from the stack structure113without penetrating through the stack structure113.

The third contact structure390may include the lower contact structure157capenetrating through the capping insulating layer136, and the upper contact structure183cpenetrating through the pattern structure109and the upper insulating layer177. Here, the lower contact structure157caand the upper contact structure183cmay be substantially the same as the structures of the lower contact structure157cand the upper contact structure183cdescribed with reference toFIGS. 1 to 3D.

In an example embodiment, the third contact structure390may be modified like any one of the modified examples of the contact structure190described with reference toFIGS. 4A to 4D and 6.

Next, an example of a method of manufacturing a semiconductor device according to an example embodiment is described with reference toFIGS. 11 to 14C. AmongFIGS. 11 to 14C,FIG. 11is a cross-sectional view illustrating a method of forming a cross-sectional structure of a first structure3in a region taken along lines I-I′ and II-II′ ofFIG. 2;FIGS. 12A, 13A and 14Aare cross-sectional views each illustrating a method of forming a cross-sectional structure of a second structure103in the region taken along lines I-I′ and II-II′ ofFIG. 2;FIGS. 12B, 13B and 14Bare cross-sectional views each illustrating a method of forming a cross-sectional structure of the second structure103in a region taken along line III-III′ ofFIG. 1; andFIGS. 12C, 13C and 14Care cross-sectional views each illustrating a method of forming a cross-sectional structure of a second structure103ain a region taken along line IVa-IVa′ ofFIG. 7.

Referring toFIG. 11, the first structure3may be formed. The first structure3may include: a semiconductor substrate6; an isolation region9sdisposed on the semiconductor substrate6and defining a peripheral active region9a; a peripheral circuit12formed on the semiconductor substrate6; a first bonding pads18electrically connected to the peripheral circuit12; and a first insulating structure21disposed on the semiconductor substrate6, covering the peripheral circuit12and having an upper surface coplanar with an upper surface of the first bonding pads18.

The peripheral circuit12may include a circuit device14such as a transistor including a peripheral gate14aand a peripheral source/drain14b, and a circuit interconnection16electrically connected to the circuit device14. The circuit interconnection16may be electrically connected to the first bonding pads18.

Referring toFIGS. 12A, 12B, and 12C, an insulating layer107may be formed on a substrate base105and a pattern structure109may be formed on the insulating layer107.

In an example embodiment, the pattern structure109may include a polysilicon layer. For example, the pattern structure109may include the polysilicon layer having an N-type conductivity.

For another example, the pattern structure109may include a polysilicon layer having a P-type conductivity.

For still another example, the pattern structure109may include a polysilicon layer including a region having the N-type conductivity and a region having the P-type conductivity. For yet still another example, the pattern structure109may include a doped polysilicon layer and a pattern layer disposed on the doped polysilicon layer. The pattern layer may include a first layer, a second layer and a third layer sequentially stacked on one another. Here, the first layer and the third layer may each be a silicon oxide layer, and the second layer may be a silicon layer or a silicon nitride layer.

In another example embodiment, the substrate base105and the insulating layer107may be omitted, and the pattern structure109may include a single crystal silicon layer.

In an example embodiment, an outer insulating layer111may be formed on a side surface of the pattern structure109.

A preliminary stack structure115and a preliminary capping insulating layer136amay be formed on the pattern structure109and the outer insulating layer111.

Forming the preliminary stack structure115and the preliminary capping insulating layer136amay include the followings: forming a preliminary lower stack structure116on the pattern structure109; forming a first preliminary upper insulating layer disposed on the pattern structure109and the outer insulating layer111, covering a portion of the preliminary lower stack structure116and having an upper surface coplanar with an upper surface of the preliminary lower stack structure116; forming a preliminary upper stack structure124on the preliminary lower stack structure116; and forming a second preliminary upper insulating layer disposed on the first preliminary upper insulating layer, covering a portion of the preliminary upper stack structure124and having an upper surface coplanar with an upper surface of the preliminary upper stack structure124. The first and second preliminary upper insulating layers may be formed of the same material as each other, for example, silicon oxide to form the preliminary capping insulating layer136a.

Forming the preliminary lower stack structure116may include forming second interlayer insulating layers118and second preliminary horizontal layers121which are alternately stacked in a vertical direction Z, and patterning the second interlayer insulating layers118and the second preliminary horizontal layers121to form a step shape on at least one side. A lowermost layer and an uppermost layer among the second interlayer insulating layers118and the second preliminary horizontal layers121may each be one of the second interlayer insulating layers118.

Forming the preliminary upper stack structure124may include forming first interlayer insulating layers127and first preliminary horizontal layers130to be alternately stacked in the vertical direction Z, and patterning the first interlayer insulating layers127and the first preliminary horizontal layers130to form a step shape on at least one side. A lowermost layer and an uppermost layer among the first interlayer insulating layers127and the first preliminary horizontal layers130may each be one of the first interlayer insulating layers127.

The first and second interlayer insulating layers127and118may be formed of a first insulating material layer such as a silicon oxide layer. The first and second preliminary horizontal layers130and121may be formed of a material different from the first and second interlayer insulating layers127and118, for example, a second insulating material layer such as a silicon nitride layer. For another example, the first and second preliminary horizontal layers130and121may be formed of a conductive material layer including at least one of doped polysilicon, metal nitride (e.g., titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN)), metal-semiconductor compound (e.g., titanium silicide (TiSi), tantalum silicide (TaSi) or nickel silicide (NiSi)), or metal (e.g., tungsten (W)).

The preliminary stack structure115may include first preliminary stack structures114aand a dummy preliminary stack structure114b.

A plurality of memory vertical structures143cpenetrating through the first preliminary stack structures114amay be formed. A dummy vertical structures143dpenetrating through the second preliminary stack structure114bmay be formed.

In an example embodiment, the plurality of memory vertical structures143cand the dummy vertical structures143dmay be simultaneously formed. For example, the plurality of memory vertical structures143cand the dummy vertical structures143dmay be formed at the same time and of the same materials.

For another example, the dummy vertical structures143dmay be formed after the plurality of memory vertical structures143care formed.

Referring toFIGS. 13A, 13B, and 13C, a preliminary capping insulating layer136bhaving an increased upper surface may be formed by forming an additional preliminary capping insulating layer on the preliminary stack structure115and the preliminary capping insulating layer136a.

Lower contact holes154cand separation trenches154swhich pass through the preliminary capping insulating layer136band the preliminary stack structure115may be formed. The lower contact holes154cand the separation trenches154smay expose the first and second preliminary horizontal layers130and121of the preliminary stack structure115.

An empty space may be formed by etching the first and second preliminary horizontal layers130and121exposed by the lower contact holes154cand the separation trenches154s, and first and second horizontal gate layers131and122may be formed in the respective empty spaces. For example, the second horizontal gate layers122may be formed in the empty spaces from which the second preliminary horizontal layers121are removed, and the first horizontal gate layers131may be formed in the empty spaces from which the first preliminary horizontal layers130are removed.

The preliminary lower stack structure116may be formed to be a second stacked region117including the horizontal gate layers122and the interlayer insulating layers118, and the preliminary upper stack structure124may be formed to be a first stacked region125including the horizontal gate layers131and the interlayer insulating layers127. The stack structure113may include the stacked regions117and125. Here, the horizontal gate layers122and interlayer insulating layers118of the second stacked region117may be referred to as the second horizontal gate layers122and the second interlayer insulating layers118, respectively, and the horizontal gate layers131and interlayer insulating layers127of the first stacked region125may be referred to as the first horizontal gate layers131and the first interlayer insulating layers127, respectively.

In an example embodiment, a portion of the first preliminary horizontal layers130may remain as the horizontal insulating layers132.

Lower contact structures157cand separation structures157smay each be formed in the lower contact holes154cand the separation trenches154s, respectively.

Forming the lower contact structures157cand the separation structures157smay include forming insulating spacers157c1and157s1respectively on sidewalls of the lower contact holes154cand separation trenches154s, and forming conductive patterns157c2and157s2respectively filling the lower contact holes154cand the separation trenches154s. Forming the conductive patterns157c2and157s2may include forming liner layers159a1and159b1uniformly covering inner walls of the lower contact holes154cand separation trenches154sin which the spacers157c1and157s1are formed, respectively, and forming pillar patterns159a2and159b2filling the lower contact holes154cand the separation trenches154s, respectively.

Among the liner layers159a1and159b1, the liner layer formed in the lower contact holes154cmay be referred to as the first liner layer159a1, and the liner layer formed in the separation trenches154smay be referred to as the second liner layer159b1. Among the pillar patterns159a2and159b2, the pillar pattern formed in the lower contact holes154cmay be referred to as the first pillar pattern159a2, and the pillar pattern formed in the separation trenches154smay be referred to as the second pillar pattern159b2.

Among the spacers157c1and157s1, the spacer formed on the side surface of the lower contact holes154cmay be referred to as the lower spacer157c1, and the spacer formed on the sidewall of the separation trenches154smay be referred to as the separation spacer157s1. Among the conductive patterns157c2and157s2, the pattern formed in the lower contact holes154cmay be referred to as the lower contact plugs157c2, and the conductive patterns formed in the separation trenches154smay be referred to as the separation patterns157s2.

Referring toFIGS. 14A, 14B, and 14C, a gate contact plugs162penetrating through the preliminary capping insulating layer136band electrically connected to the horizontal gate layers122and131may be formed. The gate contact plugs162may be formed in a first stepped region114s1inFIG. 1. A deposition process of depositing the additional capping insulating layer may be performed, and it is possible to form bit line connection vias164bpassing through the additional capping insulating layer and electrically connected to the memory vertical structures143c, gate connection vias164gelectrically connected to the gate contact plugs162, and a contact connection via164celectrically connected to the lower contact plug157c2. It is possible to form bit lines168belectrically connected to the bit line connection vias164b, gate interconnections168gelectrically connected to the gate connection vias164g, and a contact interconnection168celectrically connected to the contact connection via164c.

A capping insulating layer136having an increased thickness may be formed by forming an additional capping insulating layer, and it is possible to form an interconnection structure171embedded in the capping insulating layer136and a second bonding pads174on the interconnection structure171. The capping insulating layer136and the second bonding pads174may have upper surfaces coplanar with each other.

Again referring toFIG. 8along withFIGS. 1, 2, 3A, and 3B, the structure formed from the capping insulating layer136to the second bonding pads174may be bonded to the first structure3inFIG. 11by performing a wafer bonding process and using the method described with reference toFIGS. 12A to 14C. Here, the capping insulating layer136may be bonded to the first structure3while being in contact with the first insulating structure21, and the second bonding pads174may be bonded thereto while being in contact with the first bonding pads18.

For example, the pattern structure109may be exposed by sequentially removing the substrate base105and the insulating layer107, and an upper insulating layer177may be formed on the exposed pattern structure109.

For another example, the substrate base105may be removed, and the insulating layer107may remain. Here, the remaining insulating layer107may be the upper insulating layer177.

For still another example, when the substrate base105and the insulating layer107are omitted, and the pattern structure109is formed of a single crystal silicon layer, the pattern structure109may be formed to have a reduced thickness, and the upper insulating layer177may be formed on the pattern structure having the reduced thickness.

The lower contact structure157cmay be exposed while forming an upper contact hole180passing through the upper insulating layer177and the pattern structure109, an upper spacer layer covering an inner wall of the upper contact hole180may be formed, the upper spacer layer may be anisotropically etched to form an upper spacer183c1exposing the lower contact plug157c2of the lower contact structure157c, and an upper contact plug183c2filling the contact hole180may be formed. Accordingly, an upper contact structure183including the upper spacer183c1and the upper contact plug183c2may be formed. Accordingly, a contact structure190including the upper contact structure183cand the lower contact structure157cmay be formed. A conductive pattern193may be formed on the upper contact structure183c.

In the example embodiments, the contact structure190may be formed to have the same shape as any one of cross-sectional structures as illustrated inFIGS. 3D, 4A, 4B, 4C, and 4Ddepending on a depth at which the lower contact structure157cextends into the pattern structure109, a distance between a side surface of the lower contact structure157cand a side wall of the upper contact hole180, and a thickness of the upper spacer layer to form the upper spacer183c1.

Next, an electronic system including a semiconductor device according to an exemplary embodiment is described with reference toFIG. 15.FIG. 15is a schematic view illustrating the electronic system including the semiconductor device according to an exemplary embodiment.

Referring toFIG. 15, an electronic system1000according to an example embodiment may include a semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The electronic system1000may be a storage device including one or more semiconductor devices1100or an electronic device including the storage device. For example, the electronic system1000may be a solid state drive (SSD) device including one or more semiconductor devices1100, a universal serial bus (USB), a computing system, a medical device, or a communications device.

The semiconductor device1100may be a nonvolatile memory device, for example, a semiconductor device according to any one of the example embodiments described with reference toFIGS. 1 to 10. The semiconductor device1100may include a first structure1100F and a second structure1100S disposed on the first structure1100F.

In an example embodiment, the first structure1100F may be the first structure3of any one of the example embodiments described with reference toFIGS. 1 to 10, and the second structure1100S may be the second structure103,103a, or103bof any one of the example embodiments described with reference toFIGS. 1 to 10.

The first structure1100F may be a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. In an example embodiment, the peripheral circuit12of the first structure3of any one of the example embodiments described with reference toFIGS. 1 to 10may be a peripheral circuit structure including the decoder circuit1110, the page buffer1120, and the logic circuit1130.

The second structure1100S may be a memory vertical structure including bit lines BL, a common source line CSL, word lines WL, first and second gate upper lines UL1and UL2, and first and second gate lower lines LL1and LL2, and memory cell strings CSTR disposed between the bit lines BL and the common source line CSL.

In an example embodiment, the bit lines BL may be the bit lines168bof any one of the example embodiments described with reference toFIGS. 1 to 10.

In an example embodiment, the common source line CSL may be a polysilicon layer having an N-type conductivity in at least a portion of the pattern structure109.

In an example embodiment, the first and second gate lower lines LL1and LL2, the word lines WL, and the first and second gate upper lines UL1and UL2may be the horizontal gate layers122and131of the first stack portion113aof any one of the example embodiments described with reference toFIGS. 1 to 10. Therefore, the horizontal gate layers122and131of the first stack portion113amay include the first and second gate lower lines LL1and LL2, the word lines WL, and the first and second gate upper lines UL1and UL2. At least some of the first and second gate lower lines LL1and LL2and the first and second gate upper lines UL1and UL2may be selection gate electrodes.

Each of the memory cell strings CSTR of the second structure1100S may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of the lower transistors LT1and LT2and the number of the upper transistors UT1and UT2may be variously modified based on the example embodiments. The plurality of memory cell transistors MCT may each include data storage region capable of storing information (data). For example, the data storage layer145bof the data storage structure145as described with reference toFIG. 5Amay include the data storage region.

In the example embodiments, the upper transistors UT1and UT2may each include a string select transistor, and the lower transistors LT1and LT2may each include a ground select transistor. The gate lower lines LL1and LL2may be respective gate electrodes of the lower transistors LT1and LT2. The word lines WL may be respective gate electrodes of the memory cell transistors MCT, and the gate upper lines UL1and UL2may be respective gate electrodes of the upper transistors UT1and UT2.

In the example embodiments, the lower transistors LT1and LT2may include the lower erase control transistor LT1and the ground select transistor LT2connected in series with each other. The upper transistors UT1and UT2may include the string select transistor UT1and the upper erase control transistor UT2connected in series with each other. At least one of the lower erase control transistor LT1and the upper erase control transistor UT1may be used for an erase operation in which data stored in the memory cell transistors MCT is erased using a gate induce drain leakage (GIDL) phenomenon.

The common source line CSL, the first and second gate lower lines LL1and LL2, the word line WL, and the first and second gate upper lines UL1and UL2may each be electrically connected with the decoder circuit1110through first interconnections1115extending from the inside of the first structure1100F to the second structure1100S. The bit line BL may be electrically connected to the page buffer1120through second interconnections1125extending from the inside of the first structure1100F to the second structure1100S.

The decoder circuit1110and the page buffer1120of the first structure1100F may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The semiconductor device1100may communicate with the controller1200through an input/output pad1101electrically connected to the logic circuit1130. The input/output pad1101may be electrically connected to the logic circuit1130through an input/output connection wiring1135extending from the inside of the first structure1100F to the second structure1100S.

In an example embodiment, the input/output pad1101may be electrically connected to the conductive pattern193of any one of the example embodiments described with reference toFIGS. 1 to 10.

In an example embodiment, the input/output connection wirings1135may include the contact structures190,290, and390of any one of the example embodiments described with reference toFIGS. 1 to 10.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. According to an example embodiment, the electronic system1000may include a plurality of semiconductor devices1100, and in this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control an overall operation of the electronic system1000including the controller1200. The processor1210may be operated based on predetermined firmware, and may access to the semiconductor device1100by controlling the NAND controller1220. The NAND controller1220may include a NAND interface1221that processes its communications with the semiconductor device1100. Through the NAND interface1221, it is possible to transmit a control command for controlling the semiconductor device1100, data to be written to the memory cell transistor MCT of the semiconductor device1100, data to be read from the memory cell transistor MCT of the semiconductor device1100, etc. The host interface1230may provide communications between the electronic system1000and an external host. When the control command is received from the external host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

The electronic system including a semiconductor device according to another exemplary embodiment is described with reference toFIG. 16.FIG. 16is a schematic perspective view illustrating the electronic system including the semiconductor device according to another example embodiment.

Referring toFIG. 16, an electronic system2000according to an example embodiment may include a main substrate2001, a controller2002mounted on the main substrate2001, one or more semiconductor packages2003, and a dynamic random access memory (DRAM)2004. The semiconductor package2003and the DRAM2004may be connected to the controller2002by a wiring pattern2005formed on the main substrate2001.

The main substrate2001may include a connector2006including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins on the connector2006may depend on a communications interface between the electronic system2000and the external host. In the example embodiments, the electronic system2000may communicate with the external host based on any one of the interfaces such as a universal serial bus (USB), a peripheral component interconnect (PCI)-express, a serial advanced technology attachment (SATA), and an M-physostigmine (phy) for a universal flash storage (UFS). In the example embodiments, the electronic system2000may be operated by power supplied from the external host through the connector2006. The electronic system2000may further include a power management integrated circuit (PMIC) that distributes the power supplied from the external host to the controller2002and the semiconductor package2003.

The controller2002may write data to the semiconductor package2003or read data from the semiconductor package2003, and may improve an operation speed of the electronic system2000.

The DRAM2004may be a buffer memory to mitigate a difference in speed between the semiconductor package2003, which is a data storage space, and the external host. The DRAM2004included in the electronic system2000may also be operated as a type of a cache memory, and may provide a space for temporarily storing data during an operation of controlling the semiconductor package2003. When the DRAM2004is included in the electronic system2000, the controller2002may further include a DRAM controller controlling the DRAM2004in addition to the NAND controller controlling the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003bspaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay be a semiconductor package including a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include: a package substrate2100; the semiconductor chips2200disposed on the package substrate2100; an adhesive layer2300disposed on a lower surface of each of the semiconductor chips2200; a connection structure2400electrically connecting the semiconductor chips2200and the package substrate2100to each other; and a molding layer2500disposed on the package substrate2100and covering the semiconductor chips2200and the connection structure2400.

The package substrate2100may be a printed circuit board including a package upper pad2130. Each of the semiconductor chips2200may include an input/output pad2210. The input/output pad2210may correspond to the input/output pad1101ofFIG. 15. Each of the semiconductor chips2200may include stack structures3210and memory vertical structures3220. Each of the semiconductor chips2200may include the semiconductor device of any one of the example embodiments described with reference toFIGS. 1 to 10. The stack structure3210may be the stack structure113of any one of the example embodiments described with reference toFIGS. 1 to 10. The memory vertical structures3220may be the memory vertical structures143cor143c′ of any one of the example embodiments described with reference toFIGS. 1 to 10.

In the example embodiments, the connection structure2400may be a bonding wire electrically connecting the input/output pad2210and the upper pad2130of the package to each other. Accordingly, the semiconductor chips2200of each of the first and second semiconductor packages2003aand2003bmay be electrically connected to each other by a bonding wire method, and may each be electrically connected to the package upper pad2130of the package substrate2100. According to an example embodiment, the semiconductor chips2200of each of the first and second semiconductor packages2003aand2003bmay also be electrically connected to each other by a connection structure including a through electrode (e.g., through silicon via (TSV)), instead of the bonding wire type connection structure2400.

In the example embodiments, the controller2002and the semiconductor chip2200may be included in one package. In an example embodiment, the controller2002and the semiconductor chips2200may be mounted on a separate interposer substrate different from the main substrate2001, and the controller2002and the semiconductor chips2200may be connected to each other by a wiring formed on the interposer substrate.

FIG. 17is a schematic cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.FIG. 17illustrates an example embodiment of the semiconductor package2003ofFIG. 16, and conceptually illustrates a region cut along a cutting line V-V′ of the semiconductor package2003ofFIG. 16.

Referring toFIG. 17, each of the semiconductor chips2200aof the semiconductor package2003A may include a semiconductor substrate4010and a first structure4100disposed on the semiconductor substrate4010, and a second structure4200disposed on the first structure4100and bonded to the first structure4100by the wafer bonding method.

In an example embodiment, the first structure4100may be the first structure3of any one of the example embodiments described with reference toFIGS. 1 to 10and/or the first structure1100F described with reference toFIG. 15, and the second structure4200may be the second structure103,103a, or103bof any one of the example embodiments described with reference toFIGS. 1 to 10and/or the second structure1100S described with reference toFIG. 15.

The first structure4100may include a peripheral circuit region including a peripheral wiring4110and first bonded structures4150. The second structure4200may include: a common source line4205; a gate stack structure4210disposed between the common source line4205and the first structure4100; memory vertical structures4220and separation structures4230which penetrate through the gate stack structure4210; and second bonded structures4250electrically connected to each of the word lines (e.g., the word lines WL inFIG. 15) of the gate stack structure4210and the memory vertical structure4220. For example, the second bonded structures4250may be electrically connected to each of the memory vertical structures4220and the word lines (e.g., the word lines WL inFIG. 15) through bit lines4240electrically connected to the memory vertical structures4220and the gate interconnections (e.g., the gate interconnections168ginFIG. 3B) electrically connected to the word lines (e.g., the word lines WL inFIG. 15). The first bonded structures4150of the first structure4100and the second bonded structures4250of the second structure4200may be bonded to each other while being in contact with each other. A portion in which the first bonded structures4150and the second bonded structures4250are bonded to each other may be formed of, for example, copper (Cu).

In an example embodiment, the gate stack structure4210may be the stack structure113of any one of the example embodiments described with reference toFIGS. 1 to 10.

In an example embodiment, the memory vertical structures4220may be the memory vertical structures143cor143c′ of any one of the example embodiments described with reference toFIGS. 1 to 10.

In an example embodiment, the separation structures4230may be the separation structures157sof any one of the example embodiments described with reference toFIGS. 1 to 10.

In an example embodiment, the first bonded structures4150may include the first bonding pads18of any one of the example embodiments described with reference toFIGS. 1 to 10, and the second bonded structures4250may include the second bonding pads174of any one of the example embodiments described with reference toFIGS. 1 to 10.

Each of the semiconductor chips2200amay further include the input/output pad2210. The input/output pad2210may be electrically connected to the conductive pattern193of any one of the example embodiments described with reference toFIGS. 1 to 10. The semiconductor chips2200amay be electrically connected to each other by the bonding wire type connection structure2400. However, in the example embodiments, semiconductor chips in one semiconductor package, such as the semiconductor chips2200a, may be electrically connected to each other by the connection structure including the through electrode (through silicon via, TSV).

As set forth above, the example embodiments may provide the semiconductor device having improved integration and reliability and the data storage system including the same. For example, it is possible to penetrate through the horizontal conductive layers formed simultaneously as the word lines, and to provide the contact structure formed simultaneously as the separation structures. Accordingly, it is thus possible to form the contact structure more stably and minimize the space occupied by the contact structure, thereby improving a degree of integration of the semiconductor device. As a result, the semiconductor device may have the improved integration density and reliability.

The various and beneficial advantages and effects of the present inventive concept are not limited to the above description, and more easily understood in the process of explaining the specific example embodiments.

While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.