Method and apparatus to permit external access to internal configuration registers

Access to internal configuration registers on a computer system's chipset using an external micro-controller is provided. A SMB configuration read command including a register address may be received from an external micro-controller. Access to an internal bus may be requested from a bus arbiter. If internal bus access is granted, the SMB configuration read command may be forwarded to a device including the identified register address using the internal bus. In response to the SMB configuration read command, configuration register values from the device may be received. The configuration register values may be forwarded to the external micro-controller.

TECHNICAL FIELD

The present invention relates to computer systems. In particular, the present invention relates to system management with an external micro controller.

BACKGROUND OF THE INVENTION

A typical computer system consists of several basic components, including a central processor, volatile and non-volatile memory, and various peripheral devices, including graphics controller(s), mass storage devices, and input/output devices. A chipset connects these computer system components together, and manages the flow of information between them. Several different communications protocols may be used by the computer system, including, for example, Peripheral Component Interconnect (PCI), Small Computer System Interface (SCSI-2, ANSI, etc), Universal Serial Bus (USB), system management interface, etc.

Historically, computer system chipsets use a Northbridge/Southbridge architecture, in which the functionality of the chipset is apportioned between two basic chips, or components, a Northbridge chip and a Southbridge chip, connected via a hublink bus. The Northbridge chip connects the central processor to main/secondary memory, graphics controller(s), and the hublink bus, while the Southbridge chip connects all the other input/output (I/O) devices to the hublink bus. The I/O devices are indirectly connected to the central processor via various external busses and the hublink bus on the Northbridge chip.

A chipset, developed by the Intel Corporation of Santa Clara, Calif., uses an accelerated hub architecture. In this chipset, the functionality of the traditional Northbridge and Southbridge chips is divided among three basic components, the Memory Controller Hub (MCH), the I/O Controller Hub (ICH), and the Firmware Hub (FWH). These hubs are connected using a high-speed, proprietary data bus, (hub bus), rather than the PCI bus. As the name suggests, the ICH provides I/O functionality similar to that residing in the Southbridge chip, and may include modular components connected internally using a variety of internal buses. The ICH may also include various external bus interfaces, such as, for example, a PCI bus interface, or a system management bus (SMBus) interface.

PCI configuration registers in the chipset may store a variety of configuration register information for the PCI devices connected to the system. For example, PCI configuration registers may contain configuration information from each PCI card and/or device included in the system. PCI cards may include, for example, PCI LAN cards, PCI audio cards, PCI video cards, PCI SCSI cards, etc. Configuration register information contained in the configuration registers144may include, for example, manufacturing ID, device ID, software and/or hardware revision ID, and/or any other information related to the particular PCI card or device.

Using conventional techniques, PCI configuration registers can be read using suitable software programs running on the central processing unit. In the event, for example, the higher-level operating system freezes and/or the path from the processor to the chipset is otherwise blocked; it may not be possible to read the PCI configuration registers.

DETAILED DESCRIPTION

Embodiments of the present invention provide a chipset architecture that may enable an external micro-controller to access and/or control PCI configuration registers using a system management bus controller. The PCI configuration registers may contain device hardware/software configuration information, management information, availability information, etc. In embodiments of the present invention, the external micro-controller may operate on a secondary operating system (OS) independent from the higher level OS running on the computer system. The secondary OS may operate in the background, with or without the presence of a higher level OS running. Using the external micro-controller and a system management controller, configuration register information may be retrieved in the background independent of the central processing unit and/or the higher level OS running.

In one embodiment, a data path is provided from the external micro-controller to the configuration registers using a system management bus interface and the system management bus controller. In a further embodiment, a machine-readable medium is disclosed having a plurality of executable instruction stored thereon. The plurality of instructions includes instructions to enable the external micro-controller to access the PCI configuration registers using the system bus controller. Advantageously, the disclosed chipset architecture may offer additional system management capabilities while maximizing system availability.

FIG. 1is a partial block diagram of a network100in which the embodiments of the present invention find application.

In embodiments of the present invention, system100may include additional computers, modules and/or devices that are not shown for convenience. The network100may be a local-area network (LAN), a wide-area network (WAN), a campus-area network (CAN), a metropolitan-area network (MAN), a home-area network, an Intranet, Internet and/or any other type of computer network. It is recognized that embodiments of the present invention can be applicable to two computers that are coupled together in, for example, a client-server relationship or any other type of architecture such as peer-to-peer network architecture. The network100may be configured in any known topology such as a bus, star, ring, etc. It is further recognized that network100may use any known protocol such as Ethernet, fast Ethernet, etc. for communications.

As shown inFIG. 1, the system100is a partial representation of client computer101that includes an external micro-controller140coupled to chipset130via a communication path, for example, a system management bus interface (e.g., SMBUS I/F)181using an external system management bus (SMBus)150.

In accordance with embodiments of the present invention, additional clients101may be included in the network100coupled to a management console or computer (not shown). In this case, PCI configuration register information gathered by the micro-controller140for each client101may be shared with the management console via the network connection. This information may be centrally stored in the management console and may be used for management and/or maintenance purposes. For example, software and/or hardware revision IDs for PCI devices connected to each client101may be readily accessible and analyzed prior to a network and/or system upgrade to prevent any compatibility issues.

Additionally, it is recognized that the devices such as external micro-controller140and/or client101may be coupled to other clients using a wireless interface and/or a wireless communications protocol. Embodiments of the present invention may find application in a personal digital assistant (PDA), a laptop, a cell phone, and/or any other handheld and/or desktop device.

In embodiments of the present invention, client computer101may include a CPU110connected to a chipset130via a memory controller hub (MCH)120. The CPU110may be coupled to the MCH120using, for example, a host bus104and the MCH120may be coupled to the chipset130using bus105.

As indicated above, the micro-controller140may be coupled to the chipset130via the interface181using an external SMBus150and/or other external interface/bus combination.

The chipset130of computer system101may include, for example, a system management bus (SMB) controller131, hublink module132, peripheral devices133, north PCI bridge141, bus arbiter142, south PCI bridge143, south PCI bridge configuration registers (PCI registers)144, low pin count registers (LPC)145and a system management bus (SMB) host137. The system management bus (SMB) controller131, hub-link module132, peripheral devices133, north PCI bridge141and bus arbiter142may all be connected to internal bus160. The internal bus160may be, for example, an ISA bus, a SMBus, a PCI bus and/or any other type of bus.

In embodiments of the present invention, the PCI registers144, LPC145and SMB host137may be coupled to the south PCI bridge143that is coupled to the north PCI bridge141via PCI bus138. PCI Bus138couples south the PCI bridge143, PCI registers144, LPC145and SMB host137to internal bus160. The PCI bus138may also provide an external connection via an external PCI interface185.

Typically, the north PCI bridge141connects to main/secondary memory, graphics controller(s), and the peripheral component interconnect bus (PCI bus). The south PCI bridge143may connect all the other I/O devices to the PCI bus105. The plurality of I/O devices may be indirectly connected to the CPU110via the PCI bus105and the Host-PCI bus104via the MCH120. MCH120may interface with chipset130via the hub-link module132.

In embodiments of the present invention, system100includes a plurality of internal and/or external communication buses that connect the various components internal to and/or external to the client101. These busses may include, for example, host bus104, PCI or proprietary bus105, internal bus160, SMBus150, PCI bus138, PCI bus155and/or other PCI buses (not shown).

In embodiments of the present invention, the external micro-controller140may be, for example, an 8, 16 or 32 bit microprocessor. The micro-controller140may be located internal or external to the motherboard, and may operate using a secondary OS independent of the higher level OS running on the computer system. Accordingly, the micro-controller140may operate in the background of the higher level OS. In accordance with embodiments of the present invention, the micro-controller140may still be operational even if the higher level OS of computer system101is not in operation and/or is in a fault condition. Advantageously, micro-controller140may access PCI configuration registers even when the computer system101is locked up or in a fault state.

In embodiments of the present invention, micro-controller140may access information contained in PCI configuration registers144, internal registers of peripheral devices133, and/or any other type of internal registers located in computer system101using SMB controller131. For example, PCI configuration registers144may copy configuration information from each PCI card and/or device included in the system. PCI cards may include, for example, PCI LAN cards, PCI audio cards, PCI video cards, PCI SCSI cards, etc. Configuration information copied into the configuration registers144may include, for example, manufacturing ID, device ID, software and/or hardware revision ID, and/or any other information related to the particular PCI card or device.

In embodiments of the present invention, additional information copied to the configuration registers144may include device identification information, the amount of time the device has been operation, date, time and description of last fault, date, time and description of last repair, and/or any other information that may be needed to manage, repair, and/or replace the device to prevent system failures.

In embodiments of the present invention, the information stored in the configuration registers144may be used by the external micro-controller140for inventory management, to predict when a device may fail, to predict when the device may need to be repaired and/or replaced, etc. As indicated above, such information may be sent to a management console using a LAN where the information centrally located and used for system maintenance and/or system management purposes.

In embodiments of the invention, external micro-controller140may access the register configuration values using the SMB controller131via external system management bus150and SMBus interface181. The external micro-controller140can periodically access the register configuration values by sending a SMB configuration read command to the SMB controller131. The SMB configuration read command may include an address identifying the register and/or device for which internal configuration information is desired. Responsive to the SMB configuration read command, from external micro-controller140, the SMB controller131may send a read request to bus arbiter142using internal bus160.

In embodiments of the present invention, the bus arbiter142contains logic to the arbitrate between traffic or requests from, for example, the CPU110, the external micro-controller140and other devices and or modules in system100. By providing an external connection to the internal bus160, micro-controller140can access the plurality of configuration registers associated with modules located on the chipset130and/or other devices coupled to computer system101.

In embodiments of the present invention, the SMB controller131may request bus arbiter142for access to the internal bus160. As indicated above, the bus arbiter142controls access to internal bus160. If the internal bus160is being accessed by another device such as CPU110, the bus arbiter142may not grant access to the SMB controller131. When the internal bus160is available, management controller131is granted access to the bus160. The SMB controller131may post the SMB configuration read command on internal bus160. It is recognized that the SMB configuration read commands may be issued and/or processed using normal SMB protocol and may use an SMB based signal. Although SMB configuration read commands are used herein, it is recognize that these commands may be read commands, write commands and/or other type of commands.

In embodiments of the present invention, the SMB configuration read command is forwarded to the module and/or device identified by the address included in the SMB configuration read command. For example, the SMB configuration read command may be sent to PCI configuration registers144. In embodiments of the present invention, the SMB configuration read command may request the entire contents of the configuration register and/or may request only portion of the contents of the configuration registers.

In embodiments of the present invention, the module or device identified by the address may receive the SMB configuration read command and processes the read request. The module and/or device may retrieve the requested information from the internal configuration registers and forward the contents of the configuration registers to the SMB controller131.

In embodiments of the invention, the device may request the bus arbiter142for access to the internal bus160. When the internal bus160access is granted, the module may post the contents of the configuration registers on internal bus160. The requested configuration register values may be retrieved from the internal bus160by the SMB controller131. The SMB controller131may forward the configuration values to the external micro-controller140via the SMB interface181.

In embodiments of the present invention, the contents of the configuration registers may be used by the micro-controller140for system management purposes. For example, the micro-controller140may determine based on the contents of the registers, the version of software running on the device, the hardware version of the device, the amount of time the device has been operation, and/or any other information related to the device operation and/or management. Such information may be used for inventory management and/or to predict when the corresponding device and/or module may fail. In this case the device may be examined, repaired, and/or replaced prior to failure. In embodiments of the present invention, external micro-controller may be coupled to a plurality of computers101and may be able to quickly retrieve and/or request the contents of configuration registers associated with devices and/or modules related to the plurality of computers101.

As indicated above, in embodiments of the present invention, micro-controller140may use an OS that is running independent of the OS of computer system101. Accordingly, the external micro-controller140may be able to access contents of the configuration registers even when system101is in a fault and/or lock-up state. The external micro-controller140may retrieve and/or use the contents of the internal registers to diagnose, isolate and/or repair faults related to the corresponding device and/or module. Additionally, the use of the external micro-controller to access the configuration registers may free the CPU110from this responsibility.

In an embodiment of the present invention, the micro-controller140may request the contents of the configuration registers on a periodic basis, during a fault condition and/or when requested by an operator.

In embodiments of the present invention, contents of the configuration registers may be used to determine, for example, the total amount of time the associated device has been in operation. In one example, the total time of the operation time may be compared with the mean or average time before failure for the particular device. This information may be used to maintain, repair and/or replace the corresponding module and/or device. An operator may be notified if a particular device is approaching such a possible failure point.

FIG. 2is a flowchart illustrating a method in accordance with an embodiment of the present invention. In one embodiment of the present invention, a SMB configuration read command including a register address is received from the external micro-controller140, as shown in2010. The SMB controller131or another device may receive the SMB configuration read command from the external micro-controller140. As shown in2020, access to the internal bus160is requested from the bus arbiter142. Once bus access is granted, the SMB configuration read command may be sent to the peripheral device with the corresponding configuration register identified by the register address, as shown in2030–2040.

If, on the other hand, bus access is not granted, the SMB controller131may continue to request bus access until granted, as shown in2030and2020.

In embodiments of the present invention, the corresponding device may retrieve contents of the configuration registers and send the retrieved contents to the SMB controller131once access to the internal bus160is granted from arbiter142. As shown in2050–2060, the requested contents of the configuration registers may be received by the SMB controller131and forwarded to the external micro-controller140.

In embodiments of the present invention, the external micro-controller140examines the contents of the configuration registers and may log this information. As indicated above, the external micro-controller may use the contents of the configuration registers for inventory management and recordation purposes. In addition, the external micro-controller140may use the contents of the configuration registers to predict when device may fail based on the time the device has been in operation. In this manner, an operator may take action before the device fails.