Phase change memory cells with surfactant layers

An example embodiment is a phase change memory cell including a bottom electrode and phase change material carried within a via above the bottom electrode. A surfactant layer is deposited above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface.

BACKGROUND

The present invention is directed toward computer memory, and more particularly to a non-volatile phase change memory devices and methods for fabrication such devices.

There are two major groups in computer memory: non-volatile memory and volatile memory. Constant input of energy in order to retain information is not necessary in non-volatile memory but is required in the volatile memory. Examples of non-volatile memory devices are Read Only Memory, Flash Electrical Erasable Read Only Memory, Ferroelectric Random Access Memory, Magnetic Random Access Memory, and Phase Change Memory. Examples of volatile memory devices include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM).

The present invention is directed to phase change memory. In phase change memory, information is stored in materials that can be manipulated into different phases. Each of these phases exhibit different electrical properties which can be used for storing information. The amorphous and crystalline phases are typically two phases used for bit storage (1's and 0's) since they have detectable differences in electrical resistance. Specifically, the amorphous phase has a higher resistance than the crystalline phase.

Glass chalcogenides are a group of materials commonly utilized as phase change material. This group of materials contain a chalcogen (Periodic Table Group 16/VIA) and a more electropositive element. Selenium (Se) and tellurium (Te) are the two most common semiconductors in the group used to produce a glass chalcogenide when creating a phase change memory cell. An example of this would be Ge2Sb2Te5(GST), SbTe, and In2Se3. However, some phase change materials do not utilize chalcogen, such as GeSb. Thus, a variety of materials can be used in a phase change material cell as long as they can retain separate amorphous and crystalline states.

SUMMARY

One example of the invention is a method for fabricating a memory cell including phase change material. The method includes forming a bottom electrode within a substrate. A via is formed above the bottom electrode. During a depositing step, a surfactant layer is deposited above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface. A further depositing step deposits the phase change material within the via.

Another example of the invention is a phase change memory cell. The memory cell includes a bottom electrode and phase change material carried within a via above the bottom electrode. A surfactant layer is positioned above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface.

Yet another example of the invention is an array of phase change memory cells. Each phase change memory cell in the array includes a bottom electrode and phase change material carried within a via above the bottom electrode. A surfactant layer is positioned above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface.

DETAILED DESCRIPTION

The present invention is described with reference to embodiments of the invention. Throughout the description of the invention reference is made toFIGS. 1-5. When referring to the figures, like structures and elements shown throughout are indicated with like reference numerals.

Embodiments of the invention include phase change memory cells incorporating a surfactant along the surface of a via containing phase change material. When the phase change material is melted, the surfactant beneficially facilitates capillary forces within the via to bring the phase change material down to the bottom of the via.

FIG. 1shows an example phase change memory cell102contemplated by the present invention. The memory cell102is comprised of an insulating substrate104and a bottom electrode106within the insulating substrate104.

The insulating substrate104may be deposited as part of a starting front end of line (FEOL) wafer. The insulating substrate104may be composed of, for example, silicon dioxide (SiO2). The bottom electrode106may be constructed from, but is not limited to, titanium nitride (TiN), tungsten (W), silver (Ag), gold (Au), or aluminum (Al). A conductive plug108may be deposited over the bottom electrode106. In one embodiment, the conductive plug is made of tungsten.

The memory cell102further includes one or more intermediate insulating layers110and112forming a via114above the bottom electrode106. A surfactant layer116is deposited above the bottom electrode along the surface of the via114. It is contemplated that the surfactant layer may be deposited using atomic layer deposition (ALD). As discussed in more detail below, the surfactant layer116includes a surfactant configured to lower an interfacial force between the phase change material and the via surface.

In one embodiment, the memory cell102includes a step spacer118within the via114. The step spacer118narrows a portion of the via proximate the bottom electrode106. In a particular configuration, the via114, in combination with the step spacer118, has a substantially T-shaped cross section.

InFIG. 2, the memory cell102is shown with phase change material202deposited in the via114such that the phase change material202is carried within the via114and above the bottom electrode106. When the phase change material202is melted, the phase change material202flows down the via114and makes electrical contact with the bottom electrode106.

As mentioned above, the surfactant is configured to lower an interfacial force between the phase change material and the via surface. Thus, the surfactant enables a capillary force within the via114to overcome the attraction force(s) keeping the phase change material202from flowing to the bottom of the via114and making an electrical connection with the bottom electrode106.

The surfactant material should have a short diffusion path when intermixed with the phase change material202. Preferably, the phase change material202should defuse into the surfactant material rather than the surfactant material defusing into the phase change material202. In one embodiment, the phase change material202diffuses into the surfactant material less than 5 Angstroms (approximately 2 to 3 monolayers). The surfactant layer116may include materials such as aluminum nitride, boron nitride, aluminum oxide, tantalum nitride, tungsten, tungsten nitride, cobalt tungsten (CoW), nickel tungsten (NiW), and/or yttrium oxide.

Turning now toFIG. 3, another embodiment of a phase change memory cell102contemplated by the present invention is shown. In this embodiment, the surfactant layer302forms a portion of the via surface proximate the bottom electrode106. A top electrical contact304is also pictured over the phase change material202. As with the previous embodiment, the surfactant layer302enables a capillary force within the via114to overcome the attraction force(s) keeping the phase change material202from flowing to the bottom of the via114and making an electrical connection with the bottom electrode106.

FIG. 4shows a flowchart illustrating an example method for fabricating a memory cell in accordance with the present invention. The fabrication process begins at forming operation402where a bottom electrode is formed within a substrate. As discussed above, the substrate is an electrical insulator and the bottom electrode may include a plug at its top portion. After forming operation402is completed the process continues to forming operation404.

At forming operation404, a via is formed above the bottom electrode. The via is etched from one or more intermediate insulating layers above the bottom electrode. In one embodiment, a lithography mask with photo resist above the intermediate insulating layers is deposited. The photo resist is pattern so that the area above the bottom electrode is exposed to the proceeding etch. The etch can then be performed using, for example, an anisotropic reactive-ion etch (RIE) process. The photo resist is then stripped from the surface of the upper intermediate insulating layer.

In one embodiment of the invention, forming operation404may include forming a step spacer within the via that narrows a portion of the via proximate the bottom electrode. The step spacer is created by forming an undercut below an upper intermediate insulating layer. The undercut can be formed by performing a dilute HF wet etch where the HF attacks a silicon dioxide layer more rapidly than a silicon nitride or amorphous silicon layer. Next, a conformal insulating layer is deposited in the via. The conformal insulating layer creates a keyhole cavity within the via. In one embodiment of the invention, amorphous silicon is used as the conformal insulating layer. The conformal insulating layer can be deposited, for example, by chemical vapor deposition (CVD). Next, the step spacer is defined by anisotropic selective reactive-ion etch. The reactive-ion etch removes all of the conformal insulating material above and below the keyhole cavity and stops on a lower insulating layer or the bottom electrode.

After forming operation404is completed the process may include removing the remaining conformal insulating layer, based on cell design, using a suitable wet etching. Next, depositing operation406follows. At depositing operation406, a surfactant layer is deposited above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface. In one embodiment, the surfactant layer is deposited within the via between the bottom electrode and the phase change material after formation of the via. However, as discussed above, it is contemplated that the via may be formed after deposition of the surfactant layer such that the surfactant layer forms a portion of the via surface proximate the bottom electrode. In one embodiment, the surfactant layer is deposited using atomic layer deposition (ALD).

After depositing operation406is completed, the process continues to depositing operation408. During depositing operation408, phase change material is deposited within the via. The phase change material can be comprised of a chalcogenide. Chalcogenides are comprised of a chalcogen (Periodic Table Group 16/Group VIA) and a more electropositive element. An example of phase change materials are Ge2Sb2Te5(GST), In2Se3, GeSb and SbTe. After depositing operation408is completed the process continues to melting operation410.

At melting operation410, the phase change material is heated to its melting point. As discussed above, at least part of the phase change material interacts with the surfactant, causing it to flow to the bottom of the via. The surfactant lowers the interfacial energy between the phase change material and the via surface so that the phase change material flows down the via due to capillary action.

The fabrication process may continue with a planarizing Chemical Mechanical Polishing (CMP) step followed by deposition of a Top Electrical Contact (TEC) above the phase change material. The TEC may be comprised of, but not limited to, TiN, TaN, tungsten (W), or other suitable material that do not inter diffuse with the phase change material. Furthermore, for a full cell integration, a top electrode may be formed with any suitable Back End of the Line (BEOL) metal such as copper (Cu) or aluminum (Al).

FIG. 5shows an array of phase change memory cells502. As discussed above, each phase change memory cell102in the array includes a bottom electrode, phase change material carried within a via above the bottom electrode, and a surfactant layer above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface.