Interposers, electronic modules, and methods for forming the same

In accordance with a method for forming an interposer, a fill hole is formed in a first side of a substrate and a cavity is formed in a second side. The cavity is in fluidic communication with the fill hole. A plurality of posts is formed in the cavity, and an encapsulant is injected through the fill hole into the cavity to encapsulate the plurality of posts. In accordance with a method of thermal management, an electronic component and a heat sink are disposed on opposing sides of an interposer that includes a plurality of encapsulated posts.

FIELD OF THE INVENTION

The present invention relates, in various embodiments, to the construction and fabrication of high-density heterogeneous electronic modules and electrical and/or thermal interposers.

BACKGROUND

High-density electronic modules have been designed and fabricated to satisfy the increasing demand for high levels of functionality in small packages. Products that may be made from the modules include memory, digital logic, processing devices, and analog and RF circuits. Typically, the integration density of electronic modules is many times greater than surface mount technology (“SMT”) is capable of achieving, but less than an application specific integrated circuit (“ASIC”). However, for low volume production, these modules offer an alternative to ASIC devices, as they require less set-up cost and development time. Moreover, modules may be optimized for particular applications that demand multiple functions—for example, a pre-fabricated microelectronic die optimum for each desired function is selected, and the multiple dies are then interconnected and packaged together to form the module. Often, the pre-fabricated dies will have different form factors and thicknesses, making attempts to package them together in a single module problematic. Additional difficulties may arise when attempting to vertically interconnect different layers of dies together in a single module, as the requisite processing may damage the dies in each layer.

The fabrication of electronic modules typically features pre-thinned microelectronic dies simply positioned on an adhesive-coated substrate. A custom-machined spacer is then placed over and between the dies in order to provide a planar surface for further processing, including metal deposition, patterning, and interconnection. A thin dielectric layer is often laminated (via application of high pressure) over the dies and spacer to provide the requisite isolation between the dies and the metal interconnects. Vias to the die pads (i.e., the conductive contact pads connecting to the inner circuitry of the die) are then laser drilled and filled with a conductive material. Although high integration density may be achieved using this method, there are certain limitations. For example, dies thinned to less than 100 μm, e.g., approximately 35 μm or less, might not survive the high pressure used for lamination. Furthermore, the dies that are used typically cannot be thinned after they are placed on the module substrate, limiting the module thicknesses that may be achieved. Another limitation of this method is the use of laser-drilled vias, which are typically limited in diameter to approximately 40 μm. This puts constraints on die pad sizes, which restricts design choices to certain devices. In addition, spacing between dies must typically be greater than the via diameter to allow deep via formation. Finally, deep, high-aspect-ratio vias are often difficult to reliably and repeatably fill with the conductive material (as is required to interconnect multiple layers in a module).

Moreover, it is frequently difficult to make efficient electrical contact between high-density electronic modules or other electronic components and additional modules or circuit boards. For example, a module may have electrical contacts that do not line up, or have a different pitch than, contacts on a circuit board. Time-consuming and expensive custom fabrication processes may be required in order to fabricate connectable parts. Further, it may be impossible to directly connect conventional thermal management solutions, such as heat sinks, to high-density electronic modules or other electronic components.

Thus, in order to service the demand for increasingly small microelectronic systems, improved systems and methods for constructing high-density electronic modules and thermal and/or electrical interposers are needed.

SUMMARY

In accordance with certain embodiments, a technique is provided for forming high-density electronic modules that include encapsulated dies and reliable interlayer and/or intradie interconnections. The dies are preferably encapsulated with a bipartite structure that includes a dielectric layer protecting the active device surface and an encapsulant surrounding the rest of the device. Moreover, posts are preferably simultaneously formed with cavities that contain the die. These posts form at least a portion of electrical connections between dies or across a single die. In accordance with additional embodiments of the invention, modules including only the encapsulated posts (i.e., without the electronic dies) are fabricated. Such modules may be bonded to other electronic components and utilized as thermal and/or electrical interposer layers, the posts conducting electricity and/or heat through the module.

In one aspect, embodiments of the invention feature a method for constructing an electronic module. The method includes forming at least one fill hole in a first side of a substrate and a cavity in a second side of the substrate. The cavity is in fluidic communication with the fill hole, and a die is positioned within the cavity. An encapsulant is injected through the fill hole into the cavity to encapsulate the die. The die may be disposed on a dielectric layer that is disposed over the second side of the substrate such that the die is within the cavity.

Embodiments of the invention may include one or more of the following. At least one post may be formed within the cavity, and the post may be formed during cavity formation. Forming the post may include positioning a via chip within the cavity, and the via chip may include a matrix disposed around the post. The matrix may include silicon and the post may include a metal, e.g., copper. Forming the via chip may include defining a hole through the thickness of the matrix and forming a metal within the hole to form the post.

A conductive material may be formed over the post and the interior surface of the cavity. The encapsulated die may be electrically connected to a second die, and at least a portion of the electrical connection may include the post. At least one layer of conductive interconnections may be formed over the second side of the substrate. At least a portion of the first side of the substrate may be removed to expose at least a portion of the die, and at least one layer of conductive interconnects may be formed over the exposed portion of the die. A handle wafer may be disposed over the second side of the substrate prior to removing at least a portion of the first side of the substrate. A temporary bonding material may be formed over the handle wafer prior to disposing it over the second side of the substrate. The encapsulated die may be individuated.

In another aspect, embodiments of the invention feature an electronic module that includes a die encapsulated within each of a plurality of cavities in a substrate. At least one post defines at least a portion of an electrical connection through the substrate. The post and the substrate may include the same material, which may be a semiconductor material. The die may be encapsulated by an encapsulant and a dielectric layer, which may include different materials. The encapsulant may include a filled polymer and the dielectric layer may include an unfilled polymer. Each die may have a surface that is substantially coplanar with a surface of each other die. A conductive material may be disposed over at least the lateral surfaces of the post.

In yet another aspect, embodiments of the invention feature a structure that includes a substrate defining at least one fill hole and a cavity in fluidic communication with the fill hole. The fill hole is in a first side of the substrate and the cavity is in a second side of the substrate. A die is at least partially encapsulated within the cavity by an encapsulant. A dielectric layer may be disposed over the cavity and in contact with the die. A plurality of fill holes may be in fluidic communication with the cavity.

In a further aspect, embodiments of the invention feature a method for forming an interposer. A fill hole is formed in a first side of a substrate, and a cavity is formed in a second side; the cavity is in fluidic communication with the fill hole. A plurality of posts is formed in the cavity, and an encapsulant is injected through the fill hole into the cavity to encapsulate the plurality of posts. In various embodiments, a conductive material is formed over the plurality of posts. At least one layer of conductive interconnects may be formed over the second side of the substrate. At least a first portion of the first side of the substrate may be removed to expose the plurality of posts, and at least one layer of conductive interconnects may be formed over the exposed plurality of posts. Circuitry and heat-sink components may be associated with the resulting structure: for example, a passive component may be provided in the cavity; a heat sink and an electronic component may be disposed on opposing sides of the substrate; or an electronic component and a circuit board may be disposed on opposing sides of the substrate.

In another aspect, embodiments of the invention feature a method of thermal management including disposing an electronic component and a heat sink on opposing sides of an interposer that includes (or consists essentially of) a plurality of encapsulated posts. Each post may, for example, include or consist essentially of a semiconductor material, or a layer of a conductive material disposed on a semiconductor material. In various embodiments, each post is substantially cylindrical and consists essentially of an annular copper layer on silicon. The heat-transfer effectiveness of the interposer may be greater than 2, or even greater that approximately 1000.

In yet another aspect, embodiments of the invention feature an interposer including a substrate and a plurality of posts, each extending substantially through the thickness of the substrate. The plurality of posts may be encapsulated. The interposer may further include a layer of conductive interconnects over the front surface and/or the back surface of the substrate, and may have a heat-transfer effectiveness greater than 2, or even greater than approximately 1000. A passive component may be disposed within the substrate. The substrate and the plurality of posts may include or consist essentially of the same material, e.g., a semiconductor material. A conductive material may be disposed over at least the lateral surfaces of each post. A heat sink may be disposed under the substrate.

In a further aspect, embodiments of the invention feature an electronic system including or consisting essentially of an interposer that itself includes or consists essentially of a plurality of encapsulated posts, as well as an electronic component disposed over the interposer. A heat sink and/or a circuit board may be disposed under the interposer. A passive component may be disposed within the interposer, and a second electronic component may be disposed under the interposer. Each post may include or consist essentially of a semiconductor material surrounded (on at least its lateral surfaces) by a layer of a metal. Each post may include or consist essentially of silicon surrounded (on at least its lateral surfaces) by a layer of copper. The interposer may have a heat-transfer effectiveness greater than 2, or even greater than approximately 1000.

These and other objects, along with advantages and features of the invention, will become more apparent through reference to the following description, the accompanying drawings, and the claims. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.

DETAILED DESCRIPTION

Referring toFIG. 1A, a substrate100is provided with one or more fill holes110formed in its back surface120. Substrate100preferably includes or consists essentially of a rigid and/or non-conductive material, e.g., glass or a semiconductor such as silicon. In an embodiment, substrate100includes or consists essentially of at least one unmoldable and uncurable material. At least a portion of substrate100forms the support structure for a high-density electronic module containing multiple microelectronic dies, as further described below. In an embodiment, substrate100is a silicon wafer with a dielectric layer disposed on at least back surface120and a front surface130. The dielectric layer may be an oxide, e.g., silicon dioxide, and may have a thickness of approximately 1 μm. Fill holes110are preferably formed in substrate100by forming a protective layer (not shown), e.g., photoresist, over front surface130and back surface120, e.g., by a spin-on process. The protective layer on back surface120is then patterned, e.g., by conventional masked photolithography, such that areas of back surface120where fill holes110are to be fabricated are substantially free of the protective layer. Fill holes110are subsequently formed by, e.g., plasma or wet etching. In a preferred embodiment, fill holes110do not completely penetrate to unetched front surface130of substrate100, and have a depth in the range of approximately 200 μm to approximately 400 μm. The remaining thickness t1between the bottoms of fill holes110and front surface130may be approximately 150 μm. In an embodiment, each fill hole110has a diameter of approximately 1 mm.

Referring toFIGS. 1B and 1C, at least one cavity140is formed in front surface130of substrate100. The depth of each cavity140may be approximately 100 μm to approximately 250 μm, and is preferably sufficient to 1) fluidically connect cavity140with fill holes110and 2) substantially contain a microelectronic die200(as further described below). Each cavity140is preferably in fluidic communication with multiple fill holes110(e.g., between approximately 25 and 36, or even up to approximately 100), but may also be in fluidic communication with as few as ten, five, or even one fill hole110. Cavity140may be formed by, e.g., conventional masked photolithography and etching. Within each cavity140, at least one post150may be formed, the height of which is substantially equal to the depth of cavity140. Each post150may be formed during formation of cavity140, e.g., simultaneously via the same etch process. Each post150may be roughly cylindrical in shape and have a diameter of approximately 10 μm to approximately 35 μm. In other embodiments, each post is non-pyramidal, i.e., has approximately the same diameter throughout its thickness, and/or is in the shape of a prism with a roughly square or rectangular cross-section. In embodiments incorporating multiple posts, the posts may have a pitch ranging from approximately 20 μm to approximately 100 μm, e.g., approximately 50 μm. In a preferred embodiment, each post150remains rigidly connected (at one end) and includes or consists essentially of the same material as substrate100and/or a non-metallic material. In a preferred embodiment, each post150includes or consists essentially of a semiconductor material such as silicon. In another embodiment, each post150includes or consists essentially of a metal such as copper. As illustrated inFIG. 1C, a layer of conductive material160may be formed over front side130of substrate100, preferably coating at least all lateral sides of each post150and the internal surfaces of each cavity140. Conductive material160may include or consist essentially of a metal such as copper, and may have a thickness between approximately 0.5 μm and approximately 7 μm, or even greater than approximately 7 μm. In an embodiment, the thickness of conductive material160is approximately 3 μm. In an embodiment, a portion of conductive material160(which may be a “seed portion” for electroplating) is formed by physical deposition, e.g., sputtering or evaporation, and a remaining portion is formed by electroplating. The physically deposited portion of conductive material160may include or consist essentially of approximately 200 nm of copper over approximately 100 nm of titanium, and the electroplated portion may include or consist essentially of approximately 3 μm of copper. In another embodiment, substantially all of conductive material160is formed by physical deposition. If desired, conductive material160may be sintered, thus reacting it with the material of post150to convert at least a portion of post150into a conductive alloy (e.g., a metal silicide). In a preferred embodiment, even after formation of conductive material160to metalize posts150, posts150are not entirely formed of a metal. In various embodiments, conductive material160formed within cavities140is not removed, at least not until a suitable thinning process is performed (as described below). In an embodiment, one or more posts150are formed within cavities140substantially below where a microelectronic die will be positioned (as described below). Such posts150may be utilized to conduct heat away from the microelectronic die to the ambient or to, e.g., a heat sink or other thermal management structure such as a heat pipe or a microfluidic layer (in a similar manner to thermal interposer1300described below). The posts may be formed in a regular pattern below the microelectronic die, in which case the amount of heat conducted will depend on the diameter of each post, the density of the pattern, and the material of the posts. Alternatively, the posts may be located opportunistically where “real estate” is available.

Referring toFIGS. 1D and 1E, in various embodiments, one or more posts150are not formed by etching of substrate100. In such embodiments, one or more posts150may be pre-formed in a via chip170. Via chip170may include or consist essentially of a matrix180within which one or more posts150are formed. Matrix180may include or consist essentially of a dielectric material or a semiconductor material, e.g., silicon. Posts150preferably extend through the entire thickness of via chip170. Via chip170may be fabricated by forming one or more holes through matrix180, e.g., by etching. The one or more holes may be at least substantially filled (or have their interior surfaces coated) by a conductive material (e.g., a metal) to form post(s)150. The conductive material may be formed by, e.g., electroplating and/or physical vapor deposition. In this manner, one or more posts150may be formed in via chip170by a process resembling a through-silicon via (TSV) process. Via chip170may be introduced into cavity140and encapsulated as described below with reference to microelectronic die200. In another embodiment (further described below), the functionality of via chip170is replicated by encapsulating one or more posts150without a microelectronic die200being present.

FIG. 2depicts an exemplary apparatus for the mounting and aligning of microelectronic dies to the substrate100, e.g., within the cavities140of the substrate100. As illustrated inFIG. 2, a plurality of microelectronic dies200are disposed over a film210, although, more generally, as few as a single microelectronic die200may be disposed over the film210. In an embodiment, one microelectronic die200is disposed over film210for each cavity140prepared in substrate100as described above. Each microelectronic die200may include or consist essentially of at least one semiconductor material such as Si, GaAs, or InP, and may be a bare die or a packaged die. In an embodiment, at least one microelectronic die200is a packaged assembly of multiple devices, e.g., a hermetically packaged sensor and/or microelectromechanical systems (MEMS) device. In various embodiments, each microelectronic die200is a microcontroller, a central processing unit, or other type of chip utilized in various electronic components such as sensors or computers. Microelectronic dies200may have non-uniform thicknesses, and may differ in size and shape—because the microelectronic dies200may be encapsulated in cavities140as described below, individually tailored recesses or plinths may not be required for cavities140to be suitable to contain a wide range of different microelectronic dies200. In a preferred embodiment, a dielectric layer220is disposed between and in contact with each microelectronic die200and film210. Dielectric layer220may have a thickness of approximately 10 μm, and may be formed on film210by a spin-on process. In various embodiments of the invention, dielectric layer220includes or consists essentially of an unfilled polymer, e.g., a negative-toned spin-on material such as one of the various Intervia Photodielectrics (available from Rohm and Haas Company of Philadelphia, Pa.) or the SINR 3100 series (available from Shin-Etsu MicroSi, Inc. of Phoenix, Ariz.). A first surface of each microelectronic die200, which typically contains circuitry fabricated thereon, is in contact with film210or dielectric layer220.

In a preferred embodiment, dielectric layer220is a good electrical insulator, forms uniform coatings over uneven surfaces, and is relatively transparent. Dielectric layer220may be initially formed on film210as a liquid. In one embodiment, dielectric layer220is capable of being used to produce coatings or films with uniform thickness using equipment typically employed in fabrication of semiconductor devices. Initial heat treatments of dielectric layer220may allow it to become “tacky,” or at least mildly adhesive. Further heat treatments may ultimately cure/crosslink dielectric layer220such that it becomes a rigid structural material.

In one embodiment, dielectric layer220is selected for its sensitivity to light (i.e., it is photosensitive or photoimageable). Thus, areas of dielectric layer220may be removed by standard photolithographic methods, e.g., prior to being fully cured. In another embodiment, dielectric layer220is not sensitive to light. In such a case, dielectric layer220may be patterned using mechanical methods such as masking, machining, deep reactive ion etching (DRIE), or ablation with a laser, before or after it is fully cured.

In order to facilitate accurate placement of microelectronic dies200, film210may be placed over die placement mask230containing features corresponding to the pattern of cavities140and posts150defined on substrate100. Film210and dielectric layer220are preferably at least partially transparent, and, as such, the microelectronic dies200may be placed on dielectric layer220in locations defined on the die placement mask230thereunder. Film210may include or consist essentially of a substantially transparent material (e.g., Mylar or Kapton), and it (and dielectric film220thereover) may be supported around its perimeter by an alignment ring240. In an embodiment, alignment ring240includes or consists essentially of a rigid material such as a metal. Die placement mask230, film210, and dielectric layer220are preferably heated by a heated platen250disposed below die placement mask240to a temperature of approximately 60° C. to approximately 100° C. The elevated temperature softens dielectric layer220such that, as each microelectronic die200is placed in a desired location (dictated by the pattern on die placement mask230), it adheres to dielectric layer220. Once in contact with dielectric layer220, the front, active surfaces of microelectronic dies200may be approximately coplanar, within ±2 μm. The front surfaces of microelectronic dies may be substantially coated, i.e., “sealed,” by dielectric layer220.

Referring toFIG. 3, microelectronic dies200adhered to dielectric layer220may be placed over and aligned to cavities140in substrate100. Posts150may be utilized as alignment marks, thus facilitating accurate alignment of microelectronic dies200to cavities140. Substrate100is disposed over a hotplate300and within a diaphragm310. Once microelectronic dies200are aligned to cavities140, alignment ring240is lowered such that dielectric layer220contacts a surface of substrate100and microelectronic dies200are substantially disposed within cavities140. A substantial vacuum may be drawn in the space between film210and substrate100(now “sealed” due to the contact between diaphragms310,320) such that dielectric film220preferably (and substantially uniformly) contacts a top surface of substrate100and posts150. Thus, dielectric film220“seals” microelectronic dies200within cavities140, as shown inFIG. 4. In an embodiment, microelectronic dies200adhere to dielectric film220within cavities140, but not to an internal surface of cavities140.

Referring toFIG. 4, an encapsulation chamber400may be utilized to encapsulate the microelectronic dies200within cavities140. Substrate100, now adhered to dielectric film220(which itself is disposed on film210and alignment ring240) is placed within encapsulation chamber400. Additionally disposed within encapsulation chamber400, on opposing sides of substrate100, are platen410and pressure plate420. At least one o-ring430is disposed over platen410, and film440is disposed over platen410and o-rings430, thus forming pockets445. Each pocket445may contain encapsulant450. Platen410preferably includes or consists essentially of a rigid material, e.g., a metal, and is heatable. O-rings430may include or consist essentially of an elastomeric material such as silicone, and film440may include or consist essentially of Teflon. Platen410also includes holes460suitable for the conduction of compressed gas (e.g., compressed air), as described further below. The introduction of compressed gas through holes460applies pressure to the back surface of film440in pockets445, and film440may deflect in response to the applied pressure. Encapsulation chamber400also includes vacuum port470connected to a vacuum pump (not shown) that enables the evacuation of encapsulation chamber400.

In an exemplary embodiment, microelectronic dies200are encapsulated according to the following steps. First, platen410is heated to approximately 30° C. and encapsulation chamber400is evacuated for approximately 5 minutes in order to out-gas encapsulant450. The vacuum in encapsulation chamber400also substantially prevents the formation of trapped air bubbles in cavities140during encapsulation of microelectronic dies200(as described below). Fill holes110are aligned above pockets445, and force is applied to pressure plate420in order to seal the back surface of substrate100to o-rings430covered with film440. A pressure of approximately 15 pounds per square inch (psi) is applied to the back surface of film440via the introduction of compressed gas through holes460, thus forcing encapsulant450through fill holes110into cavities140. Dielectric film220, supported by pressure plate420, at least substantially prevents the flow of encapsulant450between microelectronic dies200and dielectric film220, maintaining the substantial coplanarity of the top surfaces of microelectronic dies200. The pressure is applied for approximately 5 minutes, whereupon the pressure is reduced to, e.g., approximately 1 psi. Platen410is heated to approximately 60° C. for a time period sufficient to at least substantially cure encapsulant450, e.g., approximately 4 hours. As encapsulant450cures, its volume may be reduced, and the pressure applied to film440is sufficient to inject additional encapsulant450into cavities140. Thus, cavities140are continuously filled with encapsulant450during curing, ensuring that cavities140are substantially or completely filled with encapsulant450after curing. Substrate100is then removed from encapsulation chamber400, and excess encapsulant450present on the back surface of substrate100may be removed by, e.g., scraping with a razor blade and/or application of a suitable solvent. Curing may be continued at a temperature of approximately 60° C. for a period of approximately 3 hours to approximately 5 hours. Film210is then removed from substrate100, leaving dielectric layer220substantially or completely intact. After removal of film210, the exposed surface of dielectric layer220is preferably planar to within ±2 μm. The presence of dielectric layer220over microelectronic dies200preferably maintains this planarity even after introduction of encapsulant450, obviating the need to separately planarize encapsulant450and/or microelectronic dies200after encapsulation. In other embodiments, other techniques are utilized to introduce encapsulant450into cavities140. For example, a syringe, an injection-molding screw, or a piston pump may be utilized to introduce encapsulant450into cavities140through fill holes110.

In an exemplary embodiment, encapsulant450includes or consists essentially of a filled polymer such as molding epoxy. The filler may reduce the thermal expansion of the polymer, and may include or consist essentially of minerals, e.g., quartz, in the form of particles, e.g., spheres, having characteristic dimensions, e.g., diameters, smaller than approximately 50 μm. Encapsulant450may be an insulating material having a coefficient of thermal expansion (CTE) approximately equal to the CTE of silicon. Encapsulant450may be present in pockets445in the form of a paste or thick fluid, or in the form of a powder that melts upon application of pressure thereto. Subsequent processing may cure/crosslink encapsulant450such that it becomes substantially rigid. In various embodiments, encapsulant450includes or consists essentially of a heavily filled material such as Shin-Etsu Semicoat 505 or SMC-810.

As described above, encapsulant450and dielectric layer220may cooperatively encapsulate microelectronic dies200. Encapsulation by multiple materials may be preferred, as encapsulant450(which is molded around the majority of each microelectronic die200) and dielectric layer220(which coats the surface of each microelectronic die200containing active circuitry) may advantageously have different material properties and/or methods of processing. Encapsulant450may wet to and bond directly to dielectric layer220, thereby forming a substantially seamless interface.

In certain embodiments, one or more passive components such as resistors, capacitors, and/or inductors may be encapsulated within substrate100instead of or in addition to a microelectronic die200. Modules including such passive components may be used as, e.g., high-density interconnect (HDI) substrates. The HDI substrates (and the passive components therein) may in turn be electrically connected (e.g., via contact to posts150) to platforms such as circuit boards, and may themselves function as platforms for one or more electronic component or module (e.g., as described below).

Referring toFIGS. 5A-5C, conductive connections to metalized posts150and to contact pads on the surface of microelectronic dies200, as well as a first metallization layer, may be formed according to the following exemplary steps. First, dielectric layer220, which is preferably photosensitive, is patterned by, e.g., conventional masked photolithography, to form via holes500. Prior to patterning, dielectric layer may have been soft baked at approximately 90° C. for approximately 60 seconds. Via holes500may have a diameter between approximately 5 μm and approximately 20 μm. Patterned dielectric layer220is then subjected to a hard bake of approximately 190° C. for approximately 1 hour, after which it is substantially planar to within ±2 μm. As illustrated inFIG. 5B, conductive material510is subsequently formed over dielectric layer220, coating and substantially or completely filling via holes500(thus forming conductive vias therein). Conductive material510may include or consist essentially of a metal such as copper, and may have a thickness between approximately 0.5 μm and approximately 7 μm, or even greater than approximately 7 μm. In an embodiment, a portion of conductive material510(which may be a “seed portion” for electroplating) is formed by physical deposition, e.g., sputtering or evaporation, and a remaining portion is formed by electroplating. In various embodiments, the electroplated portion may be omitted, i.e., substantially all of conductive material510is formed by physical deposition. The physically deposited portion of conductive material510may include or consist essentially of approximately 200 nm to approximately 2000 nm of copper over approximately 100 nm of titanium, and the electroplated portion may include or consist essentially of approximately 3 μm to approximately 7 μm of copper. Conductive material510may also include a capping layer of approximately 100 nm of titanium that may be formed by, e.g., a physical deposition method such as sputtering. The filling of via holes500with conductive material510is facilitated by the fact that via holes500only extend through the thickness of dielectric layer220, whereupon at least some via holes500reach metalized posts150. This arrangement obviates the need for the filling of high-aspect-ratio vias for the subsequent formation of interconnections on or near the back side of microelectronic dies200(after substrate thinning as described below), which may be difficult in many circumstances. As illustrated inFIG. 5C, conductive material510is patterned by, e.g., conventional masked photolithography and etching (e.g., wet or plasma etching) to form interconnection layer520. In a preferred embodiment, conductive material510is etched by application of a commercially available metal etchant such as ferric chloride or chromic acid. After etching, interconnection layer520preferably includes conductive lines with a minimum linewidth of less than approximately 12.5 μm, or even less than approximately 5 μm.

Referring toFIG. 6A, after formation of interconnection layer520, another dielectric film (which may be substantially identical to dielectric layer220) may be deposited thereover, and the steps described above with reference toFIGS. 5A-5Cmay be repeated once or even multiple times. The resulting pre-thinned module layer600includes a desired number and arrangement of metal interconnection layers. Referring toFIG. 6B, a solder mask610may be formed over pre-thinned module layer600and patterned by, e.g., conventional masked photolithography. Solder mask610may include or consist essentially of a photosensitive dielectric material, e.g., those described above with reference to dielectric layer220. Openings620in solder mask may be later utilized to form, e.g., solder ball connections to topmost interconnection layer630.

Referring toFIGS. 7A and 7B, in various embodiments of the invention, a handle wafer700is wafer bonded to pre-thinned module layer600according to the following steps. A temporary bonding material710is formed over pre-thinned module layer600by, e.g. a spin-on or silk-screen process. Temporary bonding material710may include or consist essentially of, e.g., WaferBOND or WaferBOND HT-250 (both available from Brewer Science, Inc. of Rolla, Mo.). In an embodiment, temporary bonding material710is applied to handle wafer700by spinning it on at a rate of approximately 1000 to approximately 3500 rpm. Temporary bonding material710may then be baked at a temperature of approximately 170° C. to approximately 220° C. for a time of approximately 7 minutes. Handle wafer700may then be brought into contact with pre-thinned module layer600utilizing, e.g., an EVG501wafer bonding tool (available from EV Group E. Thallner GmbH of Austria). The wafer bonding process may include applying a pressure of approximately 15 psi to handle wafer700and pre-thinned module layer600, as well as applying an elevated temperature (between approximately 140° C. and approximately 220° C.) thereto. Handle wafer700may include or consist essentially of glass, or may be a semiconductor (e.g., silicon) wafer having a dielectric layer (e.g., an oxide such as silicon dioxide) formed thereover.

After handle wafer700is bonded to a first surface of pre-thinned module layer600, a thinning process may be performed, as illustrated inFIG. 7B, on a second, opposing side of pre-thinned module layer600. During thinning, a thickness t2(illustrated inFIG. 7A) of pre-thinned module layer600is preferably removed, thus exposing (or even removing) at least a portion of a bottom surface of encapsulated microelectronic dies200and at least a portion of metalized posts150. Microelectronic dies200and posts150remain in their desired locations, as they are encapsulated in encapsulant450. The thinning process may include or consist essentially of mechanical grinding or lapping, e.g., on a copper lapping plate, with a polishing slurry, e.g., diamond particles suspended in a liquid such as water. In an embodiment, an exposed surface of thinned module layer720thus formed is further smoothed by, e.g., chemical-mechanical polishing. After removal of thickness t2of pre-thinned module layer600, each post150preferably forms at least a substantial portion of an electrical connection through substrate100. As further described below, this connection may be utilized as an intradie interconnect (e.g., connecting the front and back sides of microelectronic die200) and/or as an interconnect to further layers of microelectronic dies in an electronic module.

Referring toFIGS. 8A-8C, conductive backside connections to metalized posts150, as well as a first backside metallization layer, may be formed according to the following exemplary steps. First, dielectric layer800, which is preferably photosensitive (and may include or consist essentially of materials described above for dielectric layer220), is patterned by, e.g., conventional masked photolithography, to form backside via holes810. Each backside via hole810may have a diameter of approximately 20 μm. As illustrated inFIG. 8B, conductive material820is subsequently formed over dielectric layer800, substantially or completely filling backside via holes810(thus forming conductive vias therein). Conductive material820may include or consist essentially of a metal such as copper, and may have a thickness between approximately 0.5 μm and approximately 7 μm, or even greater than approximately 7 μm. In an embodiment, a portion of conductive material820(which may be a “seed portion” for electroplating) is formed by physical deposition, e.g., sputtering or evaporation, and a remaining portion is formed by electroplating. In various embodiments, the electroplated portion may be omitted, i.e., substantially all of conductive material820is formed by physical deposition. The physically deposited portion of conductive material820may include or consist essentially of approximately 200 nm to approximately 2000 nm of copper over approximately 100 nm of titanium, and the electroplated portion may include or consist essentially of approximately 3 μm to approximately 7 μm of copper. Conductive material820may also include a capping layer of approximately 100 nm of titanium that may be formed by, e.g., a physical deposition method such as sputtering. As described above with respect to via holes500, connections through backside via holes810are facilitated by the presence of metalized posts150, which obviate the need for high-aspect-ratio via filling. As illustrated inFIG. 8C, conductive material820is patterned by, e.g., conventional masked photolithography and etching (e.g., wet or plasma etching) to form backside interconnection layer830. In a preferred embodiment, conductive material820is etched by application of a commercially available metal etchant such as ferric chloride or chromic acid. After etching, backside interconnection layer830preferably includes conductive lines with a minimum linewidth of less than approximately 12.5 μm, or even less than approximately 5 μm.

Thinned module layer720with backside interconnection layer830may optionally be connected to a second, similarly processed, thinned module layer850by, e.g., bonding the backside interconnection layers of each module720,850together, as shown inFIG. 9A. The handle wafer of the second module layer850(not shown) may be removed, and another (or multiple) module layer(s) may be connected to the exposed surface of the second module layer850. In a preferred embodiment, each additional module layer includes at least one microelectronic die that is encapsulated prior to attachment to thinned module layer720. As illustrated inFIG. 9B, after a desired number (which may be none) of additional module layers is connected to thinned module layer720, modules900may be individuated from the stacked module layers by, e.g., die sawing. Posts150may interconnect front and back surfaces of microelectronic dies200or may form interdie interconnections within each module900. Handle wafer700may be removed either before or after individuation of modules900. Removal of handle wafer700may be accomplished by heating to a suitable debonding temperature (which may be approximately 130° C. to approximately 250° C., depending on the selected temporary bonding material710), and sliding away handle wafer700. Modules900may then be suitably cleaned and utilized in any of a variety of applications, including ultra-miniature sensors, space applications with mass and size restrictions, fully integrated MEMS-complementary metal-oxide-semiconductor (MEMS-CMOS) structures, and implantable biological sensors. Microelectronic dies200within modules900may include analog or digital integrated circuits, digital signal processors, wireless communication components such as radio frequency receivers and transmitters, optical signal processors, optical routing components such as waveguides, biological and chemical sensors, transducers, actuators, energy sources, MEMS devices, and/or passive components such as resistors, capacitors, and inductors.

Embodiments of the invention may also be advantageously utilized to fabricate “interposers,” i.e., the above-described modules without any active electronic dies or components encapsulated therewithin. Referring toFIGS. 10A and 10B, an interposer fabrication process in accordance with embodiments of the invention begins, as described above in reference toFIGS. 1B and 1C, with the formation of fill holes110and posts150. As illustrated inFIG. 10B, a layer of conductive material160may be formed over front side130of substrate100, preferably coating at least all lateral sides of each post150.

Referring toFIGS. 11A and 11B(and as described above with reference to FIGS.4and5A-5C), the posts150may then be encapsulated with encapsulant450. Encapsulant450preferably has a thermal expansion coefficient substantially matched to the thermal expansion coefficient of posts150. A dielectric layer220(or other suitable dielectric layer) may be formed over substrate100containing encapsulated posts150by, e.g., a spin-on process. Dielectric layer220is preferably patterned to form via holes500, and conductive material510is formed thereover, coating and substantially or completely filling via holes500. Conductive material510is then patterned and etched (as described above), forming interconnection layer520. Interconnection layer520, in turn, may make electrical contact to one or more posts150, and may be designed for subsequent connection to, e.g., an electrical component having a particular pattern or pitch of electrical contacts. In embodiments where one or more passive components are encapsulated within substrate100, interconnection layer520may also make electrical contact thereto, thus facilitating the electrical connection of the passive component(s) to, e.g., a circuit board or another electrical component or module. As described above with reference toFIGS. 6A and 6B, multiple interconnection layers520may be formed over substrate100.

Referring toFIG. 12(and with reference toFIGS. 7A-9A), an electrical interposer1200may be formed according to the following steps. First, the opposing side of substrate100is thinned, thus exposing at least a bottom portion of posts150. Posts150remain in their desired locations, as they are encapsulated in encapsulant450. After thinning, the posts150form at least substantial portions of electrical and/or thermal connections through substrate100. Dielectric layer is applied to the opposing side of substrate100, and may be patterned to form via holes. A conductive material is applied and patterned to form backside interconnection layer830. Backside interconnection layer830may make electrical contact to one or more posts150, and may be designed for subsequent connection to, e.g., an electrical component having a particular pattern or pitch of electrical contacts. The pattern and/or pitch of backside interconnection layer may be substantially identical or substantially different from the pattern and/or pitch of interconnection layer520. Thus, electrical interposer1200may be utilized to facilitate electrical contact between electrical components and, e.g., platforms such as circuit boards, that have different electrical contact pitches. In some embodiments, electrical interposer1200may also function as a thermal interposer (as described further below).

With reference toFIG. 13, a thermal interposer1300may be formed in a manner similar to that of the above-described electrical interposer1200, but thermal interposer1300may be formed without interconnection layer520and/or backside interconnection layer830. Thermal interposer1300may be utilized to conduct heat away from one or more electrical components and/or to facilitate connection of such components to an additional heat sink. For example, a backside interconnection layer830including or consisting essentially of a ball-grid array may be formed on thermal interposer1300, and a heat sink (e.g., one including or consisting essentially of a thermally conductive material such as copper or a copper-graphite alloy) may be thermally connected to backside interconnection layer830. Heat generated from an electrical component (not pictured) in thermal contact with thermal interposer1300is conducted away by posts150and interconnection layer520and/or backside interconnection layer830(if present) either to the ambient or to a heat sink. In an embodiment, a larger density of posts150is positioned within substrate100in locations where such electrical components (or “hot spots” thereof) are to be attached to thermal interposer1300. In another embodiment, one or more posts positioned to make thermal contact with an electrical component (or a “hot spot” thereof) have a larger diameter (and/or a thicker layer of conductive material160thereon) than at least one post150positioned away from the component. In various embodiments, thermal interposer1300has a heat-transfer effectiveness (as defined below) of at least 2. In preferred embodiments, the heat-transfer effectiveness is greater than approximately 100, or even greater than approximately 1000.

Example

The effectiveness of heat transfer through posts150(in, e.g., thermal interposer1300) has been modeled for the case of an electrical component having a surface area of 1 cm2and a temperature of 100° C. An exemplary post150is formed of silicon, has a uniform cylindrical cross-section with a diameter of 10 μm, and is coated with a 5 μm-thick annulus of electroplated copper. Thus, the total diameter of each post150is 20 μm, and the volume fraction of each of silicon and copper per unit length is 0.5. The posts150have a pitch of 50 μm, equivalent to approximately 62,500 posts/cm2. We assume that heat transfer to the surrounding medium is poor (equivalent to a stagnant surrounding air space), and that the thermal conductivity of posts150follows the law of mixing (i.e., is proportional to the volume percent of the silicon and copper components). The posts150are in contact with the electrical component at one end and a heat sink at 25° C. at the other end.

The heat flux through posts150is modeled as steady-state heat transfer through an extended surface (a “microfin”). Such microfins are utilized to increase the heat transfer from a surface by increasing its effective surface area. The figure of merit utilized to evaluate fin effectiveness is ∈f, the ratio of the fin heat-transfer rate to the heat-transfer rate that would exist in the absence of the fin:

ɛf=qfhAbase⁢θbase(1)
where qfis the fin heat-transfer rate, h is the heat-transfer coefficient between the fin and the surroundings, Abaseis the cross-sectional area of the electrical component without fins, and θbaseis the temperature difference between the component and the surroundings.

For a cylindrical microfin such as post150, and a heat sink at a known temperature, the heat-transfer rate qfis:

qf=hPkAc⁢θbase⁢θtipθbase⁢sinh⁡(hPkAc)1/2+sinh⁡(hPkAc)1/2⁢(L-x)sinh⁡(hPkAc)1/2⁢L(2)
where h is the heat-transfer coefficient between the microfin and stagnant air, P is the total perimeter of the microfins under the chip, k is the thermal conductivity of the microfins, Acis the total cross-sectional area of the microfins under the chip, θbaseis the temperature difference between the component and the surroundings, θtipis the temperature difference between the heat sink and the surroundings, and L is the x-coordinate at the tip of the microfin. Utilizing the assumptions listed above, the heat-transfer rate is approximately 15.4 W, and the fin effectiveness is approximately 1,026. The assumptions utilized herein are conservative; thus, fin effectiveness of thermal interposer1300(and posts150) may be even larger than this value.