Semiconductor package

A semiconductor package includes: a connection structure including a plurality of insulating layers and redistribution layers respectively disposed on the plurality of insulating layers; a semiconductor chip having connection pads connected to the redistribution layer; an encapsulant encapsulating the semiconductor chip; first and second pads arranged on at least one surface of the connection structure and each having a plurality of through-holes; a surface mount component disposed on the at least one surface of the connection structure and including first and second external electrodes positioned, respectively, in regions of the first and second pads; first and second connection vias arranged in the plurality of insulating layers and connecting the first and second pads to the redistribution layers, respectively; and first and second connection metals connecting the first and second pads and the first and second external electrodes to each other, respectively.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of priority to Korean Patent Application No. 10-2018-0135129 filed on Nov. 6, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor package.

BACKGROUND

A significant recent trend in the development of technology related to semiconductor chips has been reductions in the size of semiconductor chips. Therefore, in the field of package technology, in accordance with a rapid increase in demand for small-sized semiconductor chips, or the like, the implementation of a semiconductor package, having a compact size while including a plurality of pins, has been demanded. One type of package technology suggested to satisfy the technical demand as described above may be a fan-out semiconductor package.

A semiconductor package may include various surface mount components such as capacitors in order to improve electrical performance (for example, noise and/or impedance reduction). In these surface mount components, a crack occurs in an electrical connection metal (for example, a solder) due to thermal and mechanical impact or stress is concentrated on an outer side of a pad to cause a reliability defect (for example, cracking, peeling, or the like).

SUMMARY

An aspect of the present disclosure may provide a semiconductor package in which a problem due to mounting of a surface mount component may be solved.

According to an aspect of the present disclosure, a semiconductor package may include: a connection structure including a first surface and a second surface opposing each other and including a plurality of insulating layers and redistribution layers respectively disposed on the plurality of insulating layers; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; first and second pads arranged on at least one surface of the connection structure and each having a plurality of through-holes; a surface mount component disposed on the at least one surface of the connection structure and including first and second external electrodes positioned, respectively, in one regions of the first and second pads; first and second connection vias in the plurality of insulating layers and connecting the first and second pads to the redistribution layers, respectively; and first and second connection metals connecting the first and second pads and the first and second external electrodes to each other, respectively.

According to another aspect of the present disclosure, a semiconductor package may include: a connection structure including a first surface and a second surface opposing each other and including a plurality of insulating layers and redistribution layers respectively disposed on the plurality of insulating layers; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; first and second pads adjacent to each other and arranged on the second surface of the connection structure, each having a plurality of through-holes; and first and second connection vias arranged in the plurality of insulating layers and connecting the first and second pads to the redistribution layers, respectively, wherein the first and second pads respectively include first regions corresponding to portions adjacent to each other and second regions corresponding to remaining portions except the first regions, and the first and second connection vias are positioned to overlap with the first regions of the first and second pads, respectively, from a plan view perpendicular to a stacking direction.

According to another aspect of the present disclosure, a board assembly may include: a circuit board including a plurality of insulating layers and wiring circuits respectively disposed on the plurality of insulating layers; first and second pads arranged on an upper surface of the circuit board and each having a plurality of through-holes; a surface mount component disposed on the upper surface of the circuit board and including first and second external electrodes positioned, respectively, in one regions of the first and second pads; first and second connection vias disposed in the plurality of insulating layers, arranged in regions overlapping the first and second external electrodes, respectively, from a plan view perpendicular to a stacking direction, and respectively connecting the first and second pads to the wiring circuits; and first and second connection metals connecting the first and second pads and the first and second external electrodes to each other, respectively.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated or shortened for clarity.

Herein, a lower side, a lower portion, a lower surface, and the like, are used to refer to a downward direction in relation to cross sections of the drawings for convenience, while an upper side, an upper portion, an upper surface, and the like, are used to refer to an opposite direction to the downward direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above, and concepts of upper and lower portions may be exchanged with each other.

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with one another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context.

Electronic Device

Referring toFIG. 1, an electronic device1000may accommodate a mainboard1010therein. The mainboard1010may include chip related components1020, network related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines1090.

FIG. 2is a schematic perspective view illustrating an example of an electronic device.

Referring toFIG. 2, a semiconductor package may be used for various purposes in the various electronic devices1000as described above. For example, a motherboard1110may be accommodated in a body1101of a smartphone1100, and various electronic components1120may be physically or electrically connected to the motherboard1110. In addition, other components that may or may not be physically or electrically connected to the mainboard1010, such as a camera module1130, may be accommodated in the body1101. Some of the electronic components1120may be the chip related components, and the semiconductor package100may be, for example, an application processor among the chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone1100, but may be other electronic devices as described above.

Semiconductor Package

Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a semiconductor finished product in oneself, and may be damaged due to external physical or chemical impact. Therefore, the semiconductor chip is not used in oneself, and is packaged and is used in an electronic device, or the like, in a package state.

The reason why semiconductor packaging is required is that there is a difference in a circuit width between the semiconductor chip and a mainboard of the electronic device in terms of electrical connection. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the mainboard used in the electronic device and an interval between the component mounting pads of the mainboard are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and packaging technology for buffering a difference in a circuit width between the semiconductor and the mainboard is required.

A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof.

The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the accompanying drawings.

Fan-In Semiconductor Package

FIGS. 3A and 3Bare schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged, andFIG. 4is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package.

Referring toFIGS. 3 and 4, a semiconductor chip2220may be, for example, an integrated circuit (IC) in a bare state, including a body2221including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads2222formed on one surface of the body2221and including a conductive material such as aluminum (Al), or the like, and a passivation layer2223such as an oxide layer, a nitride layer, or the like, formed on one surface of the body2221and covering at least portions of the connection pads2222. Since the connection pads2222may be significantly small, it may be difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the mainboard of the electronic device, or the like.

Therefore, a connection structure2240may be formed depending on a size of the semiconductor chip2220on the semiconductor chip2220in order to redistribute the connection pads2222. The connection structure2240may be formed by forming an insulating layer2241on the semiconductor chip2220using an insulating material such as a photoimagable dielectric (PID) resin, forming via holes2243hopening the connection pads2222, and then forming wiring patterns2242and vias2243. Then, a passivation layer2250protecting the connection structure2240may be formed, an opening2251may be formed, and an underbump metal layer2260, or the like, may be formed. That is, a fan-in semiconductor package2200including, for example, the semiconductor chip2220, the connection structure2240, the passivation layer2250, and the underbump metal layer2260may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size.

However, since all I/O terminals need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has significant spatial limitations. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a small size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not be directly mounted and used on the mainboard of the electronic device. The reason is that even in the case in which a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the mainboard of the electronic device.

FIG. 5is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is ultimately mounted on a mainboard of an electronic device, andFIG. 6is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is ultimately mounted on a mainboard of an electronic device.

Referring toFIGS. 5 and 6, in a fan-in semiconductor package2200, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more through an interposer substrate2301, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device in a state in which it is mounted on the interposer substrate2301. In this case, low melting point metal or alloy balls2270, and the like, may be fixed by an underfill resin2280, or the like, and an outer side of the semiconductor chip2220may be covered with an encapsulant2290, or the like. Alternatively, a fan-in semiconductor package2200may be embedded in a separate interposer substrate2302, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more by the interposer substrate2302in a state in which the fan-in semiconductor package2200is embedded in the interposer substrate2302, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device.

As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the mainboard of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate and be then mounted on the mainboard of the electronic device through a packaging process or may be mounted and used on the mainboard of the electronic device in a state in which it is embedded in the interposer substrate.

Fan-Out Semiconductor Package

Referring toFIG. 7, in a fan-out semiconductor package2100, for example, an outer side of a semiconductor chip2120may be protected by an encapsulant2130, and connection pads2122of the semiconductor chip2120may be redistributed outwardly of the semiconductor chip2120by a connection structure2140. In this case, a passivation layer2150may further be formed on the connection structure2140, and an underbump metal layer2160may further be formed in openings of the passivation layer2150. Low melting point metal or alloy balls2170may further be formed on the underbump metal layer2160. The semiconductor chip2120may be an integrated circuit (IC) including a body2121, the connection pads2122, a passivation layer (not illustrated), and the like. The connection structure2140may include an insulating layer2141, redistribution layers2142formed on the insulating layer2141, and vias2143electrically connecting the connection pads2122and the redistribution layers2142to each other.

In the present manufacturing process, the connection structure2140may be formed after the encapsulant2130is formed outside the semiconductor chip2120. In this case, the connection structure2140may be formed after the semiconductor chip2120is encapsulated, and the vias2143connected to the redistribution layers may thus have a width that becomes small as they become close to the semiconductor chip (see an enlarged region).

As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection structure formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection structure formed on the semiconductor chip as described above. Therefore, even in the case in which a size of the semiconductor chip is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using a separate interposer substrate, as described below.

FIG. 8is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a mainboard of an electronic device.

Referring toFIG. 8, a fan-out semiconductor package2100may be mounted on a mainboard2500of an electronic device through low melting point metal or alloy balls2170, or the like. That is, as described above, the fan-out semiconductor package2100includes the connection structure2140formed on the semiconductor chip2120and capable of redistributing the connection pads2122to a fan-out region that is outside of a size of the semiconductor chip2120, such that the standardized ball layout may be used in the fan-out semiconductor package2100as it is. As a result, the fan-out semiconductor package2100may be mounted on the mainboard2500of the electronic device without using a separate interposer substrate, or the like.

As described above, since the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out electronic component package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem due to the occurrence of a warpage phenomenon.

Meanwhile, the fan-out semiconductor package refers to package technology for mounting the semiconductor chip on the mainboard of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is a concept different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein.

FIG. 9is a schematic cross-sectional view illustrating a semiconductor package according to an exemplary embodiment in the present disclosure, andFIG. 10is a plan view taken along line I-I′ of the semiconductor package ofFIG. 9.

Referring toFIGS. 9 and 10, a semiconductor package100according to the present exemplary embodiment may include a connection structure140having a first surface140A and a second surface140B opposing each other, a semiconductor chip120disposed on the first surface140A of the connection structure140, and an encapsulant130disposed on the first surface140A of the connection structure140and encapsulating the semiconductor chip120.

The semiconductor package100may further include a frame110, a wiring pattern layer132, wiring vias133, a passivation layer150, a surface mount component190, underbump metals160, and external connection metals170.

The connection structure140may include three redistribution layers142implemented on a plurality of (for example, fourth) insulating layers141, and connection pads122of the semiconductor chip120disposed on the first surface140A of the connection structure140may be connected to the redistribution layers142. The frame110may be disposed on the first surface140A of the connection structure140, and the semiconductor chip120may be accommodated in a cavity110H of the frame. The frame110may have a wiring structure including three wiring layers112a,112b, and112cand wiring vias113aand113bconnecting the three wiring layers112a,112b, and112cto each other. The wiring structure of the frame110may be connected to the redistribution layer142of the connection structure140.

The surface mount component190may be mounted on the second surface140A of the connection structure140. The surface mount component190may include various types of surface mount components as well as passive components such as a capacitor and an inductor. In the present exemplary embodiment, a case in which the semiconductor package100includes two surface mount components190is exemplified, but the semiconductor package100may include at least one surface mount component, and in some exemplary embodiments (seeFIG. 18), the surface mount component190may also be disposed on the first surface140A of the connection structure140.

FIG. 11is an enlarged cross-sectional view of region “A1” of the semiconductor package ofFIG. 9. Here, in the enlarged cross-sectional view ofFIG. 11, region “A1” is illustrated in a state in which the top and the bottom are reversed in order to facilitate the understanding.

Referring toFIG. 11, the surface mount component190may include first and second external electrodes195aand195bfor externally connecting an element body191. First and second pads182aand182bfor the surface mount component190may be formed on the insulating layer141of the connection structure140. First and second connection vias183aand183bmay be formed in the outermost insulating layer of the plurality of insulating layers141, and the first and second pads182aand182bmay be connected to the redistribution layer142of the connection structure140through the first and second connection vias183aand183b, respectively. The surface mount component190may be mounted on the first and second pads182aand182bso that the first and second external electrodes195aand195bare positioned on one regions of the first and second connection pads182aand182b, respectively. The first and second external electrodes195aand195bof the surface mount component190may be electrically or mechanically connected to the first and second pads182aand182bby first and second connection metals175aand175b, respectively. Each of the first and second connection metals175aand175bmay include a low melting point metal, for example, a lower melting point metal such as tin (Sn)-aluminum (Al)-cupper (Cu).

FIG. 12is a plan view of the first pad182aused in the present exemplary embodiment, andFIG. 13is an enlarged perspective view of region “AA1” of the semiconductor package ofFIG. 11. Here, it may be understood that the second pad182bhas a structure corresponding to that of the first pad182a.

Referring toFIG. 12, the first and second pads182aand182bused in the present exemplary embodiment may include a plurality of through-holes h1and h2, respectively. The through-holes h1and h2used in the present exemplary embodiment may reduce volumes of the first and second pads182aand182bto reduce stress due to a difference in a coefficient of thermal expansion between the first and second pads182aand182band the insulating layer141. In detail, the plurality of through-holes h1and h2may provide different beneficial functions depending on positions thereof.

The first and second pads182aand182bmay include first regions P1covered with the first and second external electrodes195aand195band the first and second connection metals175aand175band second regions P2corresponding to remaining portions except the first regions P1, respectively. The plurality of through-holes h1and h2may include first through-holes h1positioned in the first regions P1and second through-holes h2positioned in the second regions P2.

As illustrated inFIG. 13, the first through holes h1may have portions175aand175bF of which at least portions are filled with the first and second connection metals175aand175b, and the second through-holes h2may maintain empty internal spaces.

The first through-holes h1may be in contact with the first and second connection metals175aand175bin a reflow process, such that portions or the entirety of inner portions of the first through-holes h1may be filled with first and second connection metals175aand175b. In this case, due to such a filling process, amounts of used first and second connection metals175aand175b, that is, volumes of the first and second connection metals175aand175bmay be increased as compared with a case in which the first through-holes h1do not exist, and large contact areas between the first and second connection metals175aand175band the first and second pads182aand182bmay be secured. Even though cracks occur in the first and second connection metals175aand175b, propagation paths of the cracks may be increased, such that the cracks are isolated, resulting in reduction in the possibility of an open defect.

In addition, the second through-holes h2may maintain empty spaces connected to a surface of the insulating layer141without being in contact with the first and second connection metals175aand175b. Therefore, the second through-holes h2may also be used as degassing holes. In addition, as described above, the second through-holes h2may reduce volumes of the first and second pads182aand182bto reduce the stress (or thermal impact) due to the difference in the coefficient of thermal expansion between the first and second pads182aand182band the insulating layer141, resulting in effective suppression of peeling of the first and second pads182aand182bfrom the insulating layer141or occurrence of the cracks.

As described above, the first and second through-holes h1and h2used in the present exemplary embodiment may provide different beneficial functions depending on positions an arrangement forms thereof.

Shapes or structures of the first an second through-holes h1and h2used in the present exemplary embodiment may also be variously modified. For example, as illustrated inFIG. 12, the first and second through-holes h1and h2may include closed holes h1′ and h2′ arranged in internal regions of the first and second pads182aand182band surrounded by pad regions and opened holes h1″ and h2″ arranged along edges of the first and second pads182aand182band partially opened in side surfaces of the first and second pads182aand182b, respectively. Particularly, the opened holes h1″ of the first through-holes h1are positioned at the edge of the first and second pads182aand182b, as illustrated inFIG. 13, and may thus be more easily filled with the first and second connection metals175aand175bin a reflow process.

Meanwhile, the first regions P1of the first and second pads182aand182bmay be divided into regions Pia overlapping the first and second external electrodes195aand195bfrom a plan view perpendicular to a stacking direction, and regions P1b, which correspond to regions except the regions Pia, covered with the first and second connection metals175aand175b.

The first and second connection vias183aand183bused in the present exemplary embodiment may be positioned in the regions Pia overlapping the first and second external electrodes195aand195bfrom a plan view perpendicular to a stacking direction. At these positions of the first and second connection vias183aand183b, the first and second connection vias183aand183bmay connect the first and second external electrodes195aand195bto the redistribution layer142in the shortest path.

As illustrated inFIG. 12, before the surface mount component190is mounted, each of the first and second pads182aand182bmay be divided into adjacent regions adjacent to each other in relation to a central line L dividing each of the first and second pads182aand182bsubstantially in half and corresponding to a substantially half portion and the other regions corresponding to remaining portions except the adjacent regions. Also in this case, the first and second connection vias183aand183bmay be represented as being positioned to overlap the adjacent regions of the first and second pads182aand182b, respectively.

In addition, as illustrated inFIG. 12, in the regions Pia overlapping the first and second external electrodes195aand195bfrom a plan view perpendicular to a stacking direction, the first through-holes h1may not be formed in order to ensure stable connection between the pads182aand182band the first and second connection vias183aand183b, and the opened holes h1″ filled with the first and second connection metals175aand175bmay be positioned at the edges of the first and second pads182aand182b, as described above. In such an arrangement, thermal impact or thermal stress may be concentrated in outer side regions of the first and second pads182aand182b, and relatively small thermal impact or thermal stress may be applied to the regions overlapping the first and second external electrodes195aand195bfrom a plan view perpendicular to a stacking direction.

In the first and second pads182aand182bused in the present exemplary embodiment, a form in which the opened holes h1″ and h2″ are formed to surround the entire pads and the closed holes h1′ and h2′ are provided in only specific regions P1band P2is exemplified, but the first and second pads182aand182bare not limited thereto, and may have various other arrangements, as illustrated inFIGS. 14 and 14B.

Referring toFIG. 14A, a pad182a′ according to the present modified example may include first through-holes h1positioned in a first region P1and second through-holes h2positioned in a second region P2, similar to the pad182according to the previous exemplary embodiment. The second through-holes h2may include closed holes h2′ and opened holes h2″ arranged along edges of the pad in an internal region of the pad, but the first through-holes h1may include only opened holes h1″ unlike the pad182aaccording to the previous exemplary embodiment. That is, the closed holes h2′ may be provided to only the second region P2in which an external electrode and a connection metal are not positioned. In addition, connection vias183a′ may be arranged in a region P1bin which only the connection metal is positioned as well as a region Pia overlapping the external electrode from a plan view perpendicular to a stacking direction. As described above, the number of connection vias183a′ and positions of the connection vias183a′ may be modified in the first region P1.

Referring toFIG. 14B, a pad182a″ according to the present modified example may include first through-holes h1positioned in a first region P1and second through-holes h2positioned in a second region P2, similar to the pad182according to the previous exemplary embodiment. However, both of first second through-holes h1and h2may include only closed holes formed in an internal region of the pad. In addition, the first through-holes h1used in the present modified example may be formed in a region P1aoverlapping an external electrode from a plan view perpendicular to a stacking direction, as well as a region P1bin which only a connection metal is positioned. However, in the region P1aoverlapping the external electrode, the first through-holes h1may be appropriately arranged so as not to overlap connection vias183a″. In another exemplary embodiment, both of the first and second through-holes h1and h2may include only opened holes arranged along edges of the pad.

In the present exemplary embodiment, the second surface140B of the connection structure140on which the surface mount component190is mounted may be provided by the outermost insulating layer of the plurality of insulating layers141. The outermost insulating layer141may perform a passivation function, and have openings opening at least portions of the redistribution layer142. The underbump metals160may be disposed in the openings, respectively, and may be connected to external connection metals170, respectively. The external connection metals170may serve to physically and/or electrically connect the semiconductor package100to an external apparatus such as a mainboard of an electronic device. The external connection metal170may include a low melting point metal, for example, a solder such as tin (Sn)-aluminum (Al)-copper (Cu), or the like. The external connection metal170may be a single layer or multiple layers. For example, the multiple layers may include a copper pillar and a solder, and the single layer may include a tin-silver solder or copper.

A case in which the external connection metal170has a ball shape is exemplified, but the electrical external metal170may have another structure having a predetermined height, such as a land or a pin. Therefore, a predetermined mounting space may be secured on a lower surface of the insulating layer141by a height of the external connection metal170. In some exemplary embodiments, the outermost insulting layer may include a separate passivation layer having a material different from that of the other insulating layers.

In the present exemplary embodiment, two surface mount components190are exemplified for convenience of explanation, but one or a plurality of (three or more) surface mount components may be mounted on the first surface140A of the connection structure140as well as the first surface140B of the connection structure140, in a manner similar to the manner described above.

Main components of the semiconductor package100according to the present exemplary embodiment will hereinafter be described in more detail.

The frame110may improve rigidity of the semiconductor package100depending on certain materials, and serve to secure uniformity of a thickness of the encapsulant130. When wiring layers112a,112b,112c, and112d, wiring vias113a,113b, and113c, and the like, are formed in the frame110, the semiconductor package100may be utilized as a package-on-package (POP) type package. The frame110may have the cavity110H. The semiconductor chip120may be disposed in the cavity110H to be spaced apart from the frame110by a predetermined distance. Side surfaces of the semiconductor chip120may be surrounded by the frame110. However, such a form is only an example and may be variously modified to have other forms, and the frame110may perform another function depending on such a form.

The frame110may include a first insulating layer111ain contact with the connection structure140, a first wiring layer112ain contact with the connection structure140and embedded in the first insulating layer111a, a second wiring layer112bdisposed on the other surface of the first insulating layer111aopposing one surface of the first insulating layer111ain which the first wiring layer112ais embedded, a second insulating layer111bdisposed on the first insulating layer111aand covering the second wiring layer112b, and a third wiring layer112cdisposed on the second insulating layer111b. The first to third wiring layers112a,112b, and112cmay be electrically connected to connection pads122. The first to third wiring layers112a,112b, and112cmay be electrically connected to each other through first and second wiring vias113aand113beach penetrating through the first to second insulating layers111aand111b.

When the first wiring layer112ais embedded in the first insulating layer111aas in the present exemplary embodiment, a step generated due to a thickness of the first wiring layer112amay be significantly reduced, and an insulating distance of the connection structure140may thus become constant. The first wiring layer112amay be recessed into the first insulating layer111a, such that a lower surface of the first insulating layer111aand a lower surface of the first wiring layer112amay have a step therebetween. In this case, a phenomenon in which a material of an encapsulant130bleeds to pollute the first wiring layer112amay be prevented. The frame110may be manufactured at a sufficient thickness by a substrate process, or the like, while the connection structure140may be manufactured by a semiconductor process, or the like so as to have a small thickness. Therefore, a thickness of each of the first to third wiring layers112a,112b, and112cof the frame110may be greater than that of each of the redistribution layers142of the connection structure140.

A material of each of the first and second insulating layers111aand111bmay be, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. In some exemplary embodiments, a photoimagable dielectric (PID) resin may also be used as the material of each of the first and second insulating layers111aand111b. In terms of maintenance of rigidity, the prepreg may be used as the material of each of the first and second insulating layers111aand111b.

The first to third wiring layers112a,112b, and112cmay serve to redistribute the connection pads122of the semiconductor chip120. Each of the first to third wiring layers112a,112b, and112cmay include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first to third wiring layers112a,112b, and112cmay perform various functions depending on designs of corresponding layers. For example, the first to third wiring layers112a,112b, and112cmay include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals except for the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the first to third wiring layers112a,112b, and112cmay include via pads, wire pads, ball pads, and the like.

The first and second wiring vias113aand113bmay electrically connect the first to third wiring layers112a,112b, and112cformed on different layers to each other to form a wiring structure having an interlayer connection path within the frame110. A material of each of the first and second wiring vias113aand113bmay be the conductive material described above. Each of the first and second wiring vias113aand113bmay be a filled-type via filled with the conductive material, or be a conformal-type via in which the conductive material may be formed along a wall of each of via holes. Meanwhile, depending on a process, the first and second wiring vias113aand113bmay have tapered shapes of which directions are the same as each other, that is, tapered shapes of which widths of upper portions are greater than those of lower portions, in relation to a cross section. When the first and second wiring vias113aand113bare formed by the same plating process, the first and second wiring vias113aand113bmay be integrated with the second and third wiring layers112band112c.

The semiconductor chip120may be an integrated circuit (IC) provided in an amount of several hundred to several million or more elements integrated in a single chip. In this case, the IC may be, for example, a processor chip (more specifically, an application processor (AP)) such as a central processor (for example, a CPU), a graphic processor (for example, a GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a micro controller, or the like, but is not limited thereto. For example, the IC may be a memory chip such as a volatile memory (for example, a DRAM), a non-volatile memory (for example, a ROM), a flash memory, or the like, a logic chip such as an analog-to-digital converter, an application-specific IC (ASIC), or the like, or another kind of chip such as a power management IC (PMIC), or a combination of some thereof.

The semiconductor chip120may be formed on the basis of an active wafer. In this case, a base material of a body121may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body121. The connection pads122may electrically connect the semiconductor chip120to other components. A material of each of the connection pads122may be a conductive material such as aluminum (Al), copper (Cu), or the like. A passivation layer123opening the connection pads122may be formed on an active surface of the body121, and may be an oxide layer, a nitride layer, or the like, or a double layer of an oxide layer and a nitride layer. A lower surface of the connection pad122may have a step with respect to a lower surface of the encapsulant130through the passivation layer123. Therefore, the encapsulant130may fill at least portions of a space between the passivation layer123and the connection structure140. In this case, a phenomenon in which the encapsulant130bleeds into the lower surface of the connection pad122may be prevented to some degree. An insulating layer (not illustrated), and the like, may further be disposed in other required positions. The semiconductor chip120may be a bare die, and the connection pads122may thus be in physical contact with connection vias143of the connection structure140. However, depending on a kind of semiconductor chip120, a separate redistribution layer (not illustrated) may further be formed on an active surface of the semiconductor chip120, and bumps (not illustrated), or the like, may be connected to the connection pads122.

The encapsulant130may protect the frame110, the semiconductor chip120, and the like. An encapsulation form of the encapsulant130is not particularly limited, but may be a form in which the encapsulant130surrounds at least portions of each of the frame110and the semiconductor chip120. For example, the encapsulant130may cover the frame110and an inactive surface (a surface on which the connection pads122are not formed) of the semiconductor chip120, and fill at least portions of the cavity110H. The encapsulant130may fill the cavity110H to thus serve as an adhesive and reduce buckling of the semiconductor chip120depending on certain materials.

A material of the encapsulant130may be, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, or a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber, or the like, but is not limited thereto. In some exemplary embodiments, a material of the encapsulant130may be a thermosetting resin such as prepreg, ABF, FR-4, or BT or a photoimagable encapsulant (PIE) resin.

The wiring pattern layer132may be formed on the encapsulant130and be connected to the wiring structure (particularly, the third wiring layer112c). The wiring vias133may penetrate through at least portions of the encapsulant130, and may electrically connect the third wiring layer112c, which is the uppermost wiring layer of the frame110, and the wiring pattern layer132to each other. A material of each of the wiring pattern layer132and the wiring via133may be the conductive material described above, and be a metal such as copper (Cu) in some exemplary embodiments. In addition, each of the wiring pattern layer132and the wiring via133may be a plurality of conductor layers including a seed layer and a plating layer. The wiring pattern layer132may perform various functions depending on a design. For example, the redistribution layers142may include ground patterns, power patterns, signal patterns, and the like. The wiring via133may also have a tapered shape of which a width of an upper surface is greater than that of a lower surface, in relation to a cross section.

The connection structure140may redistribute the connection pads122of the semiconductor chip120. Several tens to several hundreds of connection pads122of the semiconductor chip120having various functions may be redistributed by the connection structure140, and may be physically and/or electrically externally connected through the external connection metals170depending on the functions. The connection structure140may include insulating layers141in contact with the frame110and the semiconductor chip120, the redistribution layers142disposed on the insulating layers141, and the connection vias143penetrating through the insulating layers141and connecting the connection pads122and the redistribution layers142to each other. A case in which the connection structures140include three insulating layers141and three redistribution layers142and connection vias143is exemplified inFIG. 9, but the connection structure140may be implemented as a single layer or two layers or as a larger number of layers than three layers in another exemplary embodiment.

A material of each of the insulating layers141may be a photosensitive insulating material such as a PID resin, in addition to the insulating material described above. When the insulating layer141has photosensitive properties, the insulating layer141may be formed to have a smaller thickness, and a fine pitch of the connection via143may be achieved more easily by a photolithography process. In some exemplary embodiments, each of the insulating layers141may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layers141are multiple layers, materials of the insulating layers141may be the same as each other, and may also be different from each other, if necessary. Even though the insulating layers141are the multiple layers, a boundary between the insulating layers141may also not be apparent.

The redistribution layers142may serve to substantially redistribute the connection pads122, and may be formed of the conductive material described above. The redistribution layers142may perform various functions depending on designs of corresponding layers. For example, the redistribution layers142may include ground patterns, power patterns, signal patterns, and the like. Here, the signal patterns may include various signals except for the ground patterns, the power patterns, and the like, such as data signals, and the like, and may include pad patterns having various shapes, if necessary.

The connection vias143may electrically connect the redistribution layers142formed on different layers, the connection pads122, and the like, to each other, and form an electrical path in a vertical direction (interlayer electrical path) within the semiconductor package100. A material of each of the connection vias143may be the conductive material described above. Each of the connection vias143may be completely filled with the conductive material or the conductive material may be formed along a wall of each of via holes. Meanwhile, each of the connection vias143of the connection structure140may have a tapered shape of which a direction is opposite to that of each of the first and second wiring vias113aand113bof the frame110. That is, each of the connection vias143of the connection structure140may have a tapered shape of which a width of an upper surface is smaller than that of a lower surface, in relation to a cross section.

The passivation layer150may protect the connection structure140from external physical or chemical damage. The passivation layer150may include the insulating material described above. In some exemplary embodiments, the passivation layer150may include prepreg, ABF, FR-4, BT, a solder resist, or a PID. The passivation layer150may have openings H opening partial regions of the wiring pattern layer132. A surface treatment layer132P may be formed in the opened regions of the wiring pattern layer132by plating such as noble metal plating. The surface treatment layer132P may be formed by, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating/substituted gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), or the like, but is not limited thereto.

The underbump metals160may be formed in openings of the outermost insulating layer or the passivation layer by any known metallization method using any known conductive material such as a metal, but are not limited thereto. The number, an interval, a disposition form, and the like, of external connection metals170are not particularly limited, but may be sufficiently modified depending on design particulars by those skilled in the art. For example, the external connection metals170may be provided in an amount of several tens to several thousands according to the number of connection pads122, or may be provided in an amount of several tens to several thousands or more or several tens to several thousands or less.

At least one of the external connection metals170may be disposed in a fan-out region. The fan-out region refers to a region except for a region overlapping the semiconductor chip120. The fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a 3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness, and may have price competitiveness.

Although not illustrated inFIG. 9, a plurality of semiconductor chips120performing functions that are the same as or different from each other may be disposed in the cavity110H. In some exemplary embodiments, a separate passive component such as an inductor, a capacitor, or the like, may be disposed in the cavity110H. In addition, in some exemplary embodiment, a plurality of cavities110H may be formed, and semiconductor chips120and/or passive components may be disposed in the cavities110H, respectively. A metal layer may be formed on walls of the cavity110H, if necessary, in order to dissipate heat and block electromagnetic waves.

FIG. 15is a schematic cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure, andFIG. 16is an enlarged cross-sectional view of region “A2” of the semiconductor package ofFIG. 15.

Referring toFIG. 15, it may be understood that a semiconductor package100A has a structure similar to that illustrated inFIGS. 9 through 11except that an additional (or second) passivation layer150B is used and pads182aand182band connection vias183aand183bform underbump metal layers160′ together with each other. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package100illustrated inFIGS. 9 through 13unless explicitly described otherwise.

The semiconductor package100A according to the present exemplary embodiment may include a first passivation layer150A disposed on a second surface140B of a connection structure140and a second passivation layer150B disposed on an upper surface of the semiconductor package. Underbump metal layers160′ each connected to a redistribution layer142may be formed on the first passivation layer150A. The underbump metal layer160′ may include an underbump metal (UBM) pad162aand a plurality of UBM vias163a.

As illustrated inFIG. 15, first and second pads182aand182bdisposed on the first passivation layer150A may be connected to the redistribution layer142by first and second connection vias183aand183bpenetrating through the first passivation layer150A, respectively. The first and second pads182aand182bmay include through-holes h, and the first and second connection vias183aand183bmay be positioned in pad regions overlapping external terminals195aand195band/or connection metals175aand175b, respectively, from a plan view perpendicular to a stacking direction.

In the present exemplary embodiment, the first and second pads182aand182bmay have integrated structures with the first and second connection vias183aand183b, respectively. In the present specification, a term “integrated structure” does not mean that two components are simply in contact with each other, and refers to a structure in which two components are formed integrally with each other using the same material by the same process. That is, the first pad182and the first connection via183a, and the second pad182band the second connection via183bmay be considered to have the “integrated structures” in which they are simultaneously formed by the same plating process (for example, a Cu plating process).

In addition, the first and second pads182aand182band the first and second connection vias183aand183bmay be formed together with the underbump metal layers160′ by a metallization process for the underbump metal layers160′ by forming the plurality of UBM vias163aof each underbump metal layer160′ and forming the UBM vias163aat a small thickness similar to a diameter of each of the first and second connection vias. As described above, the first and second pads182aand182band the first and second connection vias183aand183bmay include the same metal as that of the UBM layer160′.

Referring toFIG. 17, a plane structure of the underbump metal160′ used in the present exemplary embodiment is illustrated. Four UBM vias163aconnected to the redistribution layer142may be arranged on a UBM pad162aformed on the second passivation layer150B. In this via arrangement, even though a diameter of each of individual UBM vias163ais reduced, a sufficient connection area may be secured, and stress may be dispersed through a plurality of UBM vias163ato improve board level reliability of the semiconductor package100A.

In the exemplary embodiment described above, a form in which the surface mount component is mounted on the second surface (a surface on which the external connection metals are formed) of the connection structure is exemplified, but in another exemplary embodiment, the surface mount component may be mounted on the first surface (a mounting surface of the semiconductor chip) of the connection structure.

FIG. 18is a schematic cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure.

Referring toFIG. 18, a semiconductor package100B according to the present exemplary embodiment may include a connection structure140including insulating layers141, redistribution layers142formed on the insulating layers141, and vias143, first and second semiconductor chips121and122disposed on a first surface140A of the connection structure140and having connection pads121P and122P connected to the redistribution layer142, a surface mount component190disposed on the first surface140A of the connection structure140and having first and second external electrodes195aand195bconnected to first and second pads182aand182b, respectively, and an encapsulant130disposed on the first surface140A of the connection structure140and encapsulating the first and second semiconductor chips121and122.

The connection pads121P and122P of the first and second semiconductor chips may be connected to the redistribution layer142through bumps121B and122B formed on the first surface140A of the connection structure140. Each of the bumps121B and122B may be formed of a low melting point metal or a solder. An underfill (not illustrated) may be disposed between the first and second semiconductor chips121and122and the first surface140A of the connection structure140.

Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package100illustrated inFIGS. 9 through 13unless explicitly described otherwise.

However, it may be understood that the semiconductor package100B according to the present exemplary embodiment is formed by a process different from those of the semiconductor packages100and100A according to the previous exemplary embodiments. In detail, a process of manufacturing the semiconductor package100B according to the present exemplary embodiment may be performed by mounting the first and second semiconductor chips121and122after forming the connection structure140in advance, unlike the previous exemplary embodiments.

In addition, it may be understood that the connection structure140used in the present exemplary embodiment is formed in a direction different from that of the connection structure140used in the previous exemplary embodiment by a process different from that used in the previous exemplary embodiments from the redistribution layers142and the vias143formed in the connection structure140, particularly, a tapered direction of each of the vias143. In detail, it may be understood that the redistribution layers142and the vias143are sequentially formed from the second surface140B toward the first surface140A in the connection structure140used in the present exemplary embodiment.

In the present exemplary embodiment, the surface mount component190may be mounted on the first surface140A of the connection structure140. The first and second pads182aand182bdisposed on the insulating layer141providing the first surface140A of the connection structure140may be connected to the redistribution layer142by first and second connection vias183aand183bpenetrating through the second passivation layer150B, respectively. The first and second pads182aand182bmay include through-holes h, and the first and second connection vias183aand183bmay be positioned in pad regions overlapping first and second external terminals195aand195band/or first and second connection metals175aand175b, respectively, from a plan view perpendicular to a stacking direction.

By adopting such a structure, volumes of the pads may be reduced to reduce stress due to a difference in a coefficient of thermal expansion between the pads and the insulating layer and ensure stable electrical connection between the surface mount component190and the redistribution layer142through the shortest path (for example, noise reduction).

FIGS. 19 and 20are schematic cross-sectional views illustrating semiconductor packages according to various exemplary embodiments in the present disclosure.

Referring toFIG. 19, it may be understood that a semiconductor package100C according to the present exemplar embodiment has a structure similar to that illustrated inFIGS. 9 through 13orFIG. 15except that additional redistribution structures132and133are introduced on an encapsulant130and a surface mount component190is mounted on an upper surface of the semiconductor package100C instead of a second surface140B of a connection structure140. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor packages100and100A illustrated inFIGS. 9 through 13andFIG. 15explicitly described otherwise.

The semiconductor package according to the present exemplary embodiment may include a wiring pattern layer132and wiring vias133implemented on an insulating layer131disposed on the encapsulant. As illustrated inFIG. 19, the surface mount component190may be disposed on the upper surface of the semiconductor package100C. First and second pads182aand182bmay be disposed on the insulating layer131, and may be opened by openings of a second passivation layer150B. The first and second pads182aand182bmay be connected to the wiring pattern layer132by first and second connection vias183aand183bpenetrating through the insulating layer131, respectively. The first and second pads182aand182bmay include through-holes h, and the first and second connection vias183aand183bmay be positioned in pad regions overlapping first and second external terminals195aand195band/or first and second connection metals175aand175b, respectively, from a plan view perpendicular to a stacking direction. The semiconductor package may further include an additional surface mount component190disposed on the second surface140B of the connection structure140.

Referring toFIG. 20, it may be understood that a semiconductor package100D according to the present exemplary embodiment has a structure similar to that illustrated inFIGS. 9 through 13andFIG. 15except for a form of a wiring structure of a frame110. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor packages100and100A illustrated inFIGS. 9 through 13andFIG. 15explicitly described otherwise.

A frame110used in the present exemplary embodiment may have a structure different from that of the frame110described above, and a wiring structure of the frame110may thus be modified. In detail, the frame110may include a first insulating layer111a, a first wiring layer112adisposed on one surface of the first insulating layer111a, a second wiring layer112bdisposed on the other surface of the first insulating layer111a, a second insulating layer111bdisposed on one surface of the first insulating layer111aand covering at least portions of the first wiring layer112a, a third wiring layer112cdisposed on the other surface of the second insulating layer111bopposing one surface of the second insulating layer111bin which the first wiring layer112ais embedded, a third insulating layer111cdisposed on the outer surface of the first insulating layer111aand covering at least portions of the second wiring layer112b, a fourth wiring layer112ddisposed on the other surface of the third insulating layer111copposing one surface of the third insulating layer111cin which the second wiring layer112bis embedded, first wiring vias113apenetrating through the first insulating layer111aand electrically connecting the first and second wiring layers112aand112bto each other, second wiring vias113bpenetrating through the second insulating layer111band electrically connecting the first and third wiring layers112aand112cto each other, and third wiring vias113cpenetrating through the third insulating layer111cand electrically connecting the second and fourth wiring layers112band112dto each other. Since the frame110used in the present exemplary embodiment has a larger number of wiring layers112a,112b,112c, and112d, redistribution layers142of a connection structure140may further be simplified.

The first insulating layer111amay have a thickness greater than those of the second insulating layer111band the third insulating layer111c. The first insulating layer111amay be basically relatively thick in order to maintain rigidity, and the second insulating layer111band the third insulating layer111cmay be introduced in order to form a larger number of wiring layers112cand112d. The first insulating layer111amay include an insulating material different from those of the second insulating layer111band the third insulating layer111c. For example, the first insulating layer111amay be, for example, prepreg including a core material such as a glass fiber, an inorganic filler, and an insulating resin, and the second insulating layer111band the third insulating layer111cmay be an ABF or a PID including an inorganic filler and an insulating resin. However, the materials of the first insulating layer111aand the second and third insulating layers111band111care not limited thereto. Similarly, the first wiring vias113apenetrating through the first insulating layer111amay have a diameter greater than those of the second and third wiring vias113band113ceach penetrating through the second and third insulating layers111band111c. In addition, the first wiring via113amay have an hourglass shape or a cylindrical shape, while the second and third wiring vias113band113cmay have tapered shapes of which directions are opposite to each other. Thicknesses of the first to fourth wiring layers112a,112b,112c, and112dmay be greater than those of the redistribution layers142.

In the present disclosure, examples of the semiconductor packages in which the surface mount component is mounted are disclosed, but unique features of the present disclosure are that the semiconductor package includes the first and second pads having the through-holes and the first and second connection vias connected to the first and second pads, respectively, in a state in which the surface mount component is not mounted, and the spirit and scope of the present disclosure may thus be considered to include another board as well as a semiconductor package in which the surface mount component is not mounted.

In this case, as illustrated inFIGS. 12, 14A and 14B, before the surface mount component190is mounted, each of the first and second pads182aand182bmay be divided into adjacent regions adjacent to each other in relation to the central line L dividing substantially a half thereof and corresponding to a substantially half portion and the other regions corresponding to remaining portions except the adjacent regions, and the first and second connection vias183aand183bmay be represented as being positioned to overlap the adjacent regions of the first and second pads182aand182b, respectively, from a plan view perpendicular to a stacking direction.

As set forth above, according to an exemplary embodiment in the present disclosure, a plurality of through-holes may be formed in pads on which a surface mount (SMT) component is to be mounted, and connection vias may be positioned in regions of the pads overlapping a mounting region of the surface mount component to reduce volumes of the pads, such that stress due to a difference in a coefficient of thermal expansion between the pads and an insulating layer may be reduced and more reliable electrical connection between the surface mount component and an internal circuit (for example, a redistribution layer) may be ensured.