Boot block features in synchronous serial interface NAND

Embodiments are provided for protecting boot block space in a NAND memory device connected to a host device via an SPI interface. One such method includes programming a boot block password into the NAND memory device such that the host device is required to provide the boot block password in order to access the boot block space. A counter may be provided to track the number of times the host device provides an incorrect password, permanently locking the boot block space if the counter reaches a predetermined value. A further method includes associating each of various areas of the boot block space with at least one write lock bit, setting the write lock bit to a lock enable or lock disable value, and locking or unlocking an area of the boot block space depending on the value of its associated write lock bit. Areas of the boot block space may include a single boot block page, a single boot block, or a plurality of boot blocks.

BACKGROUND

1. Field of the Invention

Embodiments of the present invention relate generally to protecting boot block space in NAND memory devices.

2. Description of the Related Art

A serial peripheral interface (SPI) is a communication interface that provides a synchronous serial data link between a master device and a slave device. SPI provides support for a low to medium bandwidth network connection amongst processors and other devices.

The SPI bus includes four wires including of two control lines and two data lines. The control lines include a Serial Clock (SCK) line and a Chip Select (CS) line. The SCK signal is used to clock the shifting of serial data simultaneously into and out of the master and slave devices, allowing the SPI architecture to operate as a full duplex protocol. The CS line is driven with a signal that enables or disables the slave device being controlled by the master device. Furthermore, the master device may communicate with additional slave devices, although an additional CS line is required for each additional slave device.

SPI data lines include a Serial Data Out (SO) line and a Serial Data In (SI) line. The SO line is a data communication line that transfers data from an output of the slave device to an input of the master device. Similarly, the SI line is a data communication line that transfers data from the output of the master device to the input of the slave device. The SO and SI lines are active when the CS signal for a specific slave device transitions to an enabling state, typically active low.

Because SPI utilizes only four lines of communication, SPI has become increasingly advantageous for use in systems that require relatively simple IC designs. For example, devices which have been configured to communicate using SPI include several types of nonvolatile memory devices, including EEPROM and NOR flash memory. The SPI's relatively simple configuration of control and data lines allows for a relatively high board density at a low cost. For example, SPI EEPROM devices allow for ICs with as few as 8 pins, whereas conventional EEPROM devices may require 32 or more pins. Similarly, SPI NOR flash memory also allows ICs with substantially fewer pins than conventional NOR memory devices. Accordingly, SPI may be advantageous for use in applications desiring compact and simple layouts, such as computers.

Computer systems and other electrical systems generally include one or more memory devices. For example, computers often employ NOR flash memory and NAND flash memory. NOR and NAND flash each have certain advantages over the other. For example, NOR flash memory typically has slower write and erase speeds than NAND flash. Further, NAND flash memory typically has more endurance than NOR flash memory. However, NOR flash memory typically enables random access to data stored within the memory devices, whereas, NAND flash memory generally operates by accessing and writing data in larger groups. For example, NAND flash memory typically includes a plurality of blocks. Each block includes a plurality of pages that each includes a large number of bytes of data. During NAND flash memory operation, data is erased one block at a time and written one page at a time.

Memory arrays are generally divided into several blocks, each block including a plurality of pages of data. The memory array may also include one or more boot blocks. Boot blocks are typically smaller in size compared to the main data blocks and are used to store sensitive data, for example, boot code. Although some memory devices may include only a single boot block, as computing technology has advanced, boot code for computing devices has also increased in size, thus driving the need for increased boot block space. Because of the often sensitive nature of the data stored in the boot blocks, there is a need for security mechanisms to limit access to boot block data.

Embodiments of the present invention may be directed to one or more of the problems set forth above.

DETAILED DESCRIPTION

Turning now to the drawings, and referring initially toFIG. 1, a block diagram depicting a NAND memory system, in accordance with one or more embodiments of the invention, is illustrated, and designated generally by reference numeral100. The memory system100may be adapted for use in a variety of applications, such as, a computer, pager, cellular phone, digital camera, digital audio player, control circuit, etc. The system100may include a master device102and a slave device104. In one embodiment, the master device102may include programmed control circuitry, such as a microcontroller, and the slave device104may include a NAND memory device, as illustrated inFIG. 1. Further, while additional slave devices may be interfaced with and controlled by the master device102, for purposes of simplicity, only one slave device104is illustrated inFIG. 1.

The master device102typically communicates with the slave device104via one or more transmission lines. As illustrated inFIG. 1, the master device102and the slave device104communicate via a serial peripheral interface (SPI) including an SPI bus126. SPI provides a synchronous serial data link and operates in full duplex mode. During operation, devices on the SPI bus126typically operate in master/slave mode, enabling the master device102to initiate data frames to the slave device104. The master device102and the slave device104may also include various shift registers configured to exchange and store data.

The SPI bus126provides four lines of communication, including two data lines and two control lines. The data lines of the SPI bus126include a Serial Data In (SI) line and a Serial Data Out (SO) line. The SI line is a data communication line that carries data from the output of the master device102to the input of the slave device104. Similarly, the SO line is a data communication line carrying data from the output of the slave device104to the input of the master device102.

The control lines include a serial clock (SCK) line and a chip select (CS) line. The SCK line provides a clock signal from the master device102to the slave device104. The SCK signal is typically driven with a digital clock signal to regulate the flow of bits between the devices. For example, data may be latched or written on either a rising edge or falling edge of the SCK signal. The CS line is driven with a signal that enables or disables the slave device104being controlled by the master device102. Typically, the CS line is active low. For example, the master device102may drive the CS line low in order to enable and communicate with the slave device104. As discussed above, certain embodiments of the memory system100may include multiple slave devices104. By way of example, each additional slave device may be connected to the master device102by one of a plurality of CS lines, while a single SCK, SI, and SO line may be shared by the plurality of slave devices104. The master device102may drive a particular CS line in order to enable a corresponding slave device104to send and receive data via the SI and SO lines, regulated by the SCK signal.

In the illustrated embodiment, the slave device104of the memory system100includes an SPI NAND controller106, a cache memory118, and a NAND memory array108. The control lines CS and SCK and data line SI carry signals from the master device102to the SPI NAND controller106. The SPI NAND controller106is configured to receive and transmit data via the SPI bus126. For example, data transmitted by the master device102across the SPI bus126is received by the SPI NAND controller106inputs. Similarly, the SPI NAND controller106may also transmit data from the slave device to the master device via the SO data line. The SPI NAND controller106also transmits and receives data by way of the data input/output (DTIO) line and various access control lines, represented by reference numerals114and116. The DTIO line allows for communication between the cache memory118and the SPI NAND controller106while the control line116enables the SPI NAND controller106to send and receive signals to and from the cache memory118. Similarly, the control line118enables the SPI NAND controller106to send and receive signals to and from the NAND memory array108. Although not illustrated inFIG. 1, the NAND memory device104may also include error correction circuitry (ECC).

During operation of the memory system100, the SPI NAND controller106receives data transmitted via the SPI bus126and synchronizes the flow of data (DTIO) and control signals between other components of the NAND memory slave device104. For example, the SPI NAND controller106receives data and commands from the master device102in a serialized format via the SI line and parses the incoming serialized signal for the data and the commands. As will be appreciated by those of ordinary skill in the art, the SPI NAND controller106may include shift registers that provide appropriate timing of the signals transmitted and received by the SPI NAND controller106. Further, the SPI NAND controller106may include algorithms that are run onboard to interpret incoming signals that include commands, addresses, data, and the like. The algorithms may also include routines to determine the appropriate outputs of the SPI NAND controller106, including, for example, address schemes, error corrections, and movements of data within the NAND memory array108.

The SPI NAND controller106transmits signals from the SI data line to the NAND memory array108through the cache memory118. The cache memory118receives signals from the SPI NAND controller106via the data line DTIO and acts as a buffer for the data being transmitted by the SPI NAND controller106. The cache memory118may be of various sizes. For example, the cache memory20may include 2048 bytes, 4096 bytes, 8192 bytes or a multiple thereof. The cache memory118may also include smaller sizes such, as 256 bytes or 512 bytes. The cache memory118may also include one or more data registers to provide a path for the transfer of data between the cache memory118and the NAND memory array108. In alternate embodiments, the data registers may be included in the NAND memory array108, rather than the cache118.

After the data is buffered in the cache memory118, it may be transmitted to the NAND memory array108via data line112. Similarly, data may also be read from the NAND memory array108via data line112, and transmitted to the master device102. In one embodiment, the SPI NAND controller106may translate signals sent to the NAND memory108into standard NAND format signals, such as command latch enable (CLE), address latch enable (ALE), write enable (WE), and read enable (RE) signals. In one embodiment, the SPI NAND controller106translates signals sent to the NAND memory108into a modified NAND format, rather than the standard NAND format. In one or more embodiments, the modified NAND format signals may include a set of hexadecimal command codes.

The NAND memory array108includes a memory cell array divided into blocks, wherein each block includes a number of pages. By way of example, in a memory array having blocks of 128 kilobytes (KB), each block may include 64 pages of 2048 bytes per page. Other configurations may include 32 pages of 4096 bytes per page, or 16 pages of 8192 bytes per page. Additionally, a number of additional bytes may be associated with each page for purposes of error correction (ECC). Typically, 8 to 64 bytes may be associated with each page for ECC. The NAND memory array108is programmed and read in page-based operations (e.g., one page at a time) and is erased in block based operations (e.g., one block at a time). Because the NAND memory array108is accessed sequentially as a page, random data access of bytes may not be possible. In other words, a single byte cannot be read from the NAND memory array108because read and write functions are performed one page at a time.

The NAND memory array108generally includes a boot block space including one or more boot blocks110. The boot blocks110also include a number of pages, but are typically smaller than the main data blocks. For example, compared to the 128 KB data blocks described above, a boot block110may only be 16 KB in size. Boot blocks110are typically used to store sensitive data, such as boot code. In some embodiments, the NAND memory array108may include only a single boot block. However, as computing devices have advanced, the amount of data in the boot code has also increased in size and, accordingly, other embodiments may include a plurality of boot blocks110. Additionally, it is also possible that updates to boot code are programmed into new boot blocks while the outdated code remains programmed, but is not executed by the memory system100, instead of overwriting the outdated code.

In the illustrated embodiment, the NAND memory device104includes a boot block password register120for providing boot block security features. To provide secured access to the boot blocks110, the master device102may be required to “enter” a user password by writing the password to the boot block password register120via data line124(through the SPI NAND controller106). The entered password may be compared to the boot block password, which may be stored in a non-volatile block of the NAND memory array118, in order to authenticate the master device for accessing the boot block space. Until the correct password is entered, read, write, and erase operations to the boot blocks110may be disabled. As will be appreciated by those skilled in the art, in one or more embodiments, the boot block password register120may be further adapted to protect the entire NAND memory array108, so that until a correct password is entered, read, write, and erase operations are disabled as to both the boot block and the non-boot block space of the NAND memory array108.

In the illustrated embodiment, the NAND memory device104also includes a boot block access register122for providing additional boot block security features. Various portions of the boot blocks may be write locked (locked to a read-only state) using the boot block access register122. The boot block access register122may be configured to disable or enable boot block access by individual boot blocks, by individual pages within a particular boot block, or by a boot block region, which may include the entire boot block space, or a plurality of boot blocks defined by a user. These security features will be described in more detail in the subsequent paragraphs.

Turning now toFIG. 2, a process200for programming a boot block password for providing secured access to one or more boot blocks110of NAND memory array108is illustrated in accordance with one or more embodiments of the present invention. At step202, a boot block password is selected to be programmed into the NAND memory array108. In one or more embodiments, the boot block password may be an n-bit password, for example, a 64-bit password. The boot block password may be programmed to a non-volatile area of the NAND memory array108. For example, in certain embodiments, the boot block password is programmed to a specific block in the memory array108. The specific block may be reserved for storing secured data, such as passwords and read, write, and erase protection status of each individual boot block, boot block page, or boot block region. The data in the specific block may be read through status registers when the NAND memory device102is initialized and/or powered on. In other embodiments, the boot block password may be programmed into one or more pages of the NAND memory array108designated as one-time programmable (OTP) areas. OTP areas are typically reserved for programming unique data to the memory device108. While data, once written to an OTP area, may be stored permanently, some memory devices may allow for a limited number of program operations to an OTP page, for example, typically 1 to 4 operations per OTP page.

At step204, after a suitable password is selected, the master device102accesses the non-volatile block in which the password is to be stored. In embodiments using a specific block, as described above, the boot block password may be programmed by issuing a write command from the master device102addressing the specific block via the SI line. In embodiments storing the password in the OTP area of the memory device108, the master device102may need to first enable OTP access by setting an OTP access enable bit before the OTP area may be accessed for programming. At step206, the boot block password is programmed into the memory array108for use as an authentication means, typically requiring the master device102to enter the correct password before accessing data stored in the boot blocks110. In one or more embodiments, the memory device104is configured to enable boot block password protection at power up, thereby disabling read, write, and erase access until the correct password is supplied.

FIG. 3illustrates a process300for issuing a read command to read data from a boot block110. At step302, the memory device104is powered on. At step304, the master device102issues a read command via the SI data line to read data from a boot block110. At step306, if the boot blocks110are password protected, read access is denied (step308) and, at step310, invalid data (e.g., garbage data, all logical 1's) is returned via the SO data line. As described above, one or more embodiments of the memory device104may be configured to enable password protection at power up, denying read, write, and erase access to the boot blocks. However, if the boot blocks are not password protected at step306, the master device may proceed to read data from the boot blocks, as indicated at step312. The boot block data is returned to the master device102via the SO data line.

Referring now toFIG. 4, a process400for providing a password to the memory device104in order to securely access and read data from the boot block space110is illustrated. At step402, the memory device104is powered on. At step404, if the boot blocks110are not password protected, the master device102may issue read commands via the SI data line to read data from the boot blocks (step422). If however, at step404, password protection is enabled, the master device102must provide the correct password in order to read data from the boot blocks110. For example, in one or more embodiments, the boot blocks110are read, write, and erase protected via the boot block password at power up.

At step406, the master device102provides a boot block password. In one or more embodiments, providing the password may include writing the password to the boot block password register120shown inFIG. 1. The value written to the password register120is evaluated, at step408, with the programmed boot block password (process ofFIG. 2). At step410, if the entered password is incorrect, an attempt counter is incremented at step412. The attempt counter tracks the number of unsuccessful attempts in which the master device102tries to access the boot blocks110. In one or more embodiments, the attempt counter may be implemented by a shift register. Also in step412, the value of the attempt counter is compared to a pre-determined maximum number of allowed attempts. If the number of unsuccessful attempts indicated by the attempt counter is equivalent to the maximum allowed attempts (step414), as an additional security feature, the boot blocks110are permanently read, write, and erase locked, making any further attempts to access the boot block impossible. If, however, at step414, the attempt counter has not reached the maximum allowed attempts, the boot blocks110remain protected (step416), but the master device102may subsequently make additional attempts to enter a correct boot block password, returning the process400to step406. At this point, however, any read commands issued to the boot blocks110via the master device102will fail and result in invalid data being returned on the SO data line, as discussed inFIG. 3.

Returning to step410, if the password supplied by the master device102is determined to be correct, password protection for read, write, and erase operations for the boot blocks110is disabled, and the master device may issue read operations to the boot blocks (step420). For example, at step422, the master device102may issue read commands to read data from the boot blocks110. In one or more embodiments, the password protection may be re-enabled the next time the memory device104is power cycled on, or re-enabled by the master device102after completion of necessary boot block operations. It should be noted that while entering the correct boot block password in step410disables the password protection for read, write, and erase operations, the boot blocks may be further protected from write and erase access by write lock bits in the memory array108corresponding to each boot block110, each boot block page, or to one or more boot block regions.

Referring now toFIG. 5a process500for enabling access to a boot block or boot block page protected by a write lock bit is illustrated, in accordance with one or more embodiments of the present invention. While the process500will be described primarily with respect to unlocking and locking a boot block110, the process500may similarly be applied to unlocking and locking individual boot block pages.

The process500assumes that a correct boot block password has been previously entered. If the correct password has not been entered, the master device102must first enter the correct boot block password, as described by the process400ofFIG. 4, before proceeding. At step502, the master device102issues a write or erase command to a boot block110via the SI data line. In one or more embodiments, a non-volatile write lock bit is associated with each boot block110for write/erase protection. In other embodiments, additional write lock bits may also be associated with each individual boot block page in order to lock or unlock an individual page. In one or more embodiments, when a write lock bit is enabled (e.g., set high to logical 1), the boot block110associated with that particular write lock bit is locked, denying write/erase access to the boot block110by the master device102. The write lock bits function as an additional measure of security, protecting the boot blocks110even after a correct boot block password has been entered.

At step504, if the write lock bit associated with the addressed boot block in the write/erase command of step502is enabled, the write/erase command fails, and no data is written to or erased from the addressed boot block110(step506). It should be noted, that while the boot block110is write locked, the master device102may still read data from the boot block110, provided the correct boot block password has been entered. In order to write to the addressed boot block, the master device102must set the boot block access register122to disable the write lock bit. In one or more embodiments, the master device102writes a disable value (e.g., logical 0) to the boot block access register122(step508). A subsequent write/erase command will store the value in the boot block access register122into the corresponding write lock bit of the boot block110addressed in the write/erase command. Thus, if the boot block access register122stores an enable value when the write/erase command is executed, the addressed boot block will remain locked or, if the boot block access register122stores a disable value when the write/erase command is executed, the addressed boot block110is unlocked for write/erase operations. In one or more embodiments, the boot block access register122may include a plurality of registers, each of the plurality of registers configured to enable or disable write lock bits corresponding to a boot block, a boot block page, and a boot block region.

Returning to step504, if the write lock bit associated with the addressed boot block110is disabled, the master device102may perform write and erase operations on the boot block110via the SI line (step510). Following a write or erase operation in step510, it may be desirable to lock the boot block110for protection from unwanted write/erase operations. In one or more embodiments, the master device102writes an enable value (e.g., logical 1) to the boot block access register122(step512). A subsequent program execution command will store the enable value in the boot block access register122into the corresponding write lock bit of the addressed boot block110, thereby locking the boot block110(step514). As discussed above, one or more embodiments of the present invention may include write lock bits associated with each individual boot block as well as each boot block page, wherein the process500ofFIG. 5may similarly be applied for locking and unlocking boot block pages. By providing this increased resolution of boot block locking, a user has the flexibility of locking, for example, each boot code update. The boot block page lock operation is especially useful if boot code is updated often in small sizes.

In one or more embodiments of the present invention, the memory device104may also include a boot region lock feature, wherein a boot region may be defined by a user. For example, the boot region may encompass the entire boot block space. The boot block space may also be divided into two or more boot regions, each boot region encompassing an equal number of boot blocks110. This provides a faster mechanism for locking a defined range of boot blocks as opposed to locking each individual boot block one by one.

Referring now toFIG. 6A, a process600for locking and unlocking a boot region is illustrated, in accordance with one or more embodiments of the present invention. The process600is initiated at step602. Like the boot block and boot block page locking and unlocking process500described inFIG. 5, each defined boot region may have a write lock bit associated with the boot region. In one or more embodiments, the master device102may write an enable value to the boot block access register122via the SI data line and data line124. An execution command stores the enable value stored in the boot block access register122into the corresponding write lock bit of the addressed boot region, thereby locking the boot region (step604). As such, each boot block and each boot block page within the locked boot region is protected from write and erase operations. At step606, after the boot region is locked, the protection status (read/write/erase) for each boot block and boot block page in the boot region is stored in a separate non-volatile block. This may include storing, for example, the values of each write lock bit associated with each boot block and boot block page within the boot region. By saving this data, the protection status of each block and page can be restored when the device is powered up, or when the boot region is unlocked at a later time.

The boot region may be subsequently unlocked via the process650illustrated inFIG. 6B. At step652, the boot region unlock process is initiated, and may include, in one or more embodiments, writing a disable value to the boot block access register122via the SI data line and data line124. An execution command stores the disable value in the boot block access register122into the corresponding write lock bit of the addressed boot region, thereby unlocking the boot region (step654). At step656, after the boot region is unlocked, the saved protection status (from step606ofFIG. 6A) for each boot block and boot block page of the boot region is read from the non-volatile separate block. Write and erase operations may now be performed on the boot blocks110and the boot block pages within the boot region based on the restored protection status data.