Methods of manufacturing a semiconductor device having increased gaps between gates

According to embodiments of the present invention, methods of manufacturing a semiconductor device, and semiconductor devices manufactured thereby, are provided. A field region is formed that defines active regions in a semiconductor substrate. Spaced apart gates are formed on the active regions in the semiconductor substrate. The gates have sidewalls that extend away from the semiconductor substrate. First spacers are formed on the sidewalls of the gates. Second spacers are formed on the first spacers and opposite to the gates. Ion impurities are implanted into the active regions in the semiconductor substrate, adjacent to the gates, using the first and second spacers as an ion implantation mask. A portion of the second spacers is removed to widen the gaps between the gates. A dielectric layer is formed on the semiconductor substrate in the gaps between the gates.

RELATED APPLICATION

This application claims priority from Korean Application No. 2001-0064775, filed Oct. 19, 2001, the disclosure of which is herein incorporated by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to methods of manufacturing semiconductor devices, and more particularly, to methods of manufacturing semiconductor devices having spaced apart gates, and semiconductor devices manufactured thereby.

BACKGROUND OF THE INVENTION

As memory devices, such as DRAMs, are designed to operate at higher speeds and to have larger storage capacities, their integration densities have generally increased while their design rules have decreased. Horizontal gaps between individual devices in the memories, such as between gates or word lines, have generally reduced in proportion to the decreasing design rules. Moreover, the gap between devices may be further reduced when spacers are formed between the devices. As the gaps between devices become increasingly narrow, defects, such as poor contact filling or misalignment, may occur.

For example, bit lines may be insulated from gates by filling the gaps between the gates with an insulating layer. With decreased design rules, the gaps between the gates may become sufficiently narrow, such that the insulating layer does not completely fill the gaps and voids result. Filling defects may become particularly common when the design rules are reduced to about 0.14 μm or less. While the width of the gates and/or the thickness of spacers may be reduced to increase the gaps between the gates, the operational characteristics of the memory device, such as the refresh characteristics, may deteriorate.

SUMMARY OF THE INVENTION

According to embodiments of the present invention, a method of manufacturing a semiconductor device is provided. A field region is formed that defines active regions in a semiconductor substrate. Spaced apart gates are formed on the active regions in the semiconductor substrate. The gates have sidewalls that extend away from the semiconductor substrate. First spacers are formed on the sidewalls of the gates. Second spacers are formed on the first spacers and opposite to the gates. Ion impurities are implanted into the active regions in the semiconductor substrate, adjacent to the gates, using the first and second spacers as an ion implantation mask. A portion of the second spacers is removed to widen the gaps between the gates. A dielectric layer is formed on the semiconductor substrate in the gaps between the gates.

Using the spacers as a mask may reduce gate induced drain leakage or other deterioration of the characteristics of a semiconductor device, such as a transistor, that is fabricated in this manner. Reducing the thickness of the spacers can increase the gaps between the gates, and may reduce any occurrence of voids when the gaps are filled with a dielectric layer.

In some embodiments, impurity ions may be implanted to form source and drain regions in the active regions adjacent to the gates. The combined thickness of the first and second spacer may be sufficient to mask the substrate so that the gates do not overlap the source and drain regions. The second spacer may be thicker than the first spacer, and they may have different etching selectivity. In one embodiment, the first spacer may comprise silicon oxide and the second spacer may comprise silicon nitride. Accordingly, a portion of the second spacer may be removed, such as by etching, to widen the gaps, while leaving at least a portion of the first spacer on the sidewalls of the gates and on the semiconductor substrate between the gates. The remaining first spacer may be used as an etch stopper in subsequent processes.

In some embodiments of the present invention, the interlayer dielectric layer may be patterned to form contact holes that expose portions of the active regions in the semiconductor substrate and the sidewalls of the gates. Spacers may be formed that cover the sidewalls of the contact holes, including the exposed sidewalls of the gates. Ion impurities may be implanted into the active regions of the semiconductor substrate that are exposed by the contact holes. The second ion implantation process may reduce contact resistance between the conductive contact pads and the active regions in the semiconductor substrate. The spacers may be used as an ion implantation mask. The second spacers may avoid deterioration of the semiconductor device by the second ion implantation. Conductive pads may be formed in the contact holes.

In other embodiments of the present invention, a semiconductor device may be provided that includes a semiconductor substrate having active regions defined by a field region. Gates are spaced across the active regions. Source and drain regions are in the active regions adjacent to the gates. An interlayer dielectric layer is in the gaps between the gates. Spacers are between the sidewalls of the gates and the interlayer dielectric layer. The spacers have a sufficient thickness to mask the substrate so that the gates do not overlap the source and drain regions.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a plan view of a semiconductor device, such as a DRAM, according to embodiments of the present invention.FIGS. 2 through 13are cross-sectional views illustrating operations for manufacturing the semiconductor device ofFIG. 1, taken along lines X-X′ and X′-X″, according to embodiments of the present invention. With reference first toFIGS. 1 and 2, the semiconductor device includes a substrate100, active regions110, field regions150, and gates200that form a cell array. The field regions150and active regions110are formed in the substrate100using an isolation process. The field regions150may be defined by an insulating layer formed by a shallow trench isolation (STI) process in the substrate100. The insulating layer may fill a trench formed in the semiconductor substrate100, by the STI process, and may include silicon oxide.

The active regions110are defined adjacent to the field regions150on the surface of the substrate100. As shown inFIG. 1, the active regions110, along the plan view, are defined in bar shapes, although they may be defined in other shapes. A plurality of active regions110may be arranged along a plane of the semiconductor substrate100, as shown in FIG.1.

Spaced apart gate oxide layers170are formed on the semiconductor substrate100. An ion implantation process may be performed in the semiconductor substrate100, to adjust a well structure and a threshold voltage VTof a subsequently formed transistor, before the gate oxide layers170are formed.

Conductive layers for the gates200are sequentially formed on the gate oxide layers170. In one embodiment, polysilicon layers210may be deposited, and then dichlorosilane tungsten silicide (DCS-WSix) layers250may be deposited. The polysilicon layers210may be deposited to a thickness of about 800 Å, and the tungsten silicide layers250may be deposited to a thickness of about 1000 Å. Capping insulating layers300may be formed on the tungsten suicide layers250. The capping insulating layers300may be formed of silicon nitride to a thickness of about 1,500-1,800 Å.

Hard masks may be formed on the capping insulating layers300. The hard masks may comprise silicon oxide, and may be used as an etching mask when the capping insulating layers300, the tungsten suicide layers250, and the polysilicon layers210are sequentially etched to pattern the gates200. The sequentially etching may include photolithography to form the patterned gates200of stacked tungsten suicide layers250and the polysilicon layers210. As shown inFIG. 1, the bar shaped gates200extend across the active regions110and are spaced apart from each other.

Referring toFIG. 3, a spacer layer400may be formed on the gates200. The spacer layer400may include a first spacer layer410and a second spacer layer450. Preferably, the spacer layer400includes two or more layers of different materials, such as materials having different dielectric constants and/or different etching selectivity. In one embodiment, the first and second spacer layers410and450are sequentially formed to cover sidewalls of the gates200and the capping insulating layers300, where the sidewalls of the gates200extend away from the semiconductor substrate100. The first spacer layer410may comprise silicon oxide with a thickness of about 150 Å. The second spacer layer450may comprise silicon nitride with a thickness of about 400-500 Å. The first spacer layer410may be between the second spacer layer450, and the gates200and capping layers300.

Referring toFIG. 4, at least a portion of the second spacer layer450may be removed, such as by an anisotropic etching process, from over portions of the semiconductor substrate100, between the gates200, to form second spacers450′ that cover the sidewalls of the gates200and sidewalls of the capping insulating layers300. The first spacer layer410remains between the second spacers450′ and the gates200and between the second spacers450′ and the capping insulating layers300. The thickness of the first spacer layer410, that is exposed on the semiconductor substrate100between the gates200by the removal of the second spacer layer450, may be reduced by about ½ of its thickness before the etching. When the first spacer layer410is formed with a thickness of about 150 Å, the portion of the first spacer layer410that is not covered with the second spacers450′ may be reduced to a thickness of about 80 Å by the etching. In this manner, the etching selectivity of silicon oxide of the first spacer layer410relative to the silicon nitride of the second spacer layer450may be used to selectively remove portions of the second spacer layer450to form the second spacers450′ while substantially leaving the first spacer layer410to cover the surface of the semiconductor substrate100between the gates200. Moreover, the first spacer layer410may severs as an etch stopper in a subsequent process to selectively remove the second spacers450′.

Referring toFIG. 5, source/drain regions180are formed in the semiconductor substrate100adjacent to the gates200for use as transistors. A cell ion implantation process is performed in cell regions. Impurity ions, such as n−ions, are implanted into the active regions110in the semiconductor substrate100, between the second spacers450′, to form the source and drain regions180. In one embodiment, phosphorous (P) is ion implanted into the active regions110at a concentration of about 5E12 (or 5×1012) at an energy of about 20 eV to form the source and drain regions180in the active regions110between the gates200. The ion implantation process may include a halo ion implantation process for forming halos around the source and drain regions180.

The second spacers450′ may be used as an ion implantation mask during the ion implantation process for the source and drain regions180. The second spacers450′ may serve to avoid reduction in the effective channel length that may be caused by the process of implanting n−ions into the source and drain regions180. If the effective channel length were otherwise allowed to decrease, the sub-threshold current leakage may undesirably increase for the transistor formed by the gates200and source and drain regions180. The combined thickness of the first and second spacers410and450′ should be sufficient to avoid the gates200overlapping with the source and drain regions180. Otherwise, gate induced drain leakage (GIDL) current may increase and the refresh characteristics of the device may deteriorate. As previously described, in one embodiment, the second spacers450′ may have a thickness of about 400-500 Å along at least a portion of the sidewalls of the gates. Referring toFIG. 6, the second spacers450′ may be removed, such as by selective etching. In one embodiment, the silicon nitride of the second spacers450′ is removed by etching, using wet etching with phosphoric acid, while substantially leaving the silicon oxide of the first spacer layer410. The first spacer layer410may serve as an etch stopper to protect the semiconductor substrate100between the gates200, and the capping insulating layers300, during the etching process to remove the second spacers450′.

Referring toFIG. 7, an interlayer dielectric (ILD) layer500may be formed to fill the gaps between the gates. The ILD layer500insulates the gates200from bit lines (not shown) that may be formed later. The ILD layer500may be formed from one or more of many dielectric materials, such as silicon oxide, and may comprise a stack of a plurality of different dielectric material layers. The second spacers450′ between the gates200are removed before the ILD layer500is deposited to widen the gaps between the gates200. With the second spacers450′ removed, the ILD layer500may more easily fill the gaps between the gates200, and voids may be prevented from occurring.

When the second spacers450′ have a thickness of about 400-500 Å, the gaps between the gates200may be widened to a width of about 800-1,000 Å when the second spacers450′ are removed. If the ILD layer500were formed before the second spacers450′ were removed, it may be more difficult to fill the gaps between the gates200, which may be only about 600 Å, without voids. However, when the second spacers450′ are removed, the gaps between the gates200may be widened to at least 1,200 Å. The ILD layer500may then be deposited without filling defects, such as voids, due to the larger gap between the gates200.

As before, the first spacer layer410covers the surface of the semiconductor substrate100in which the source and drain regions180are formed, and may protect the source and drain regions180from being damaged.

The surface of the ILD layer500may be planarized, such as by chemical mechanical polishing (CMP) or etch back. The ILD layer500may be planarized to a thickness of about 1,000 Å on the capping insulating layers300on the gates200.

InFIG. 8, the ILD layer500is patterned to form contact holes510between the gates200. The ILD layer500may be patterned by photolithography and self-aligned contact (SAC) to form the contact holes510. Conductive contact pads600may be formed in the contact holes510, such as is shown ofFIG. 1, for connecting the transistors to subsequent interconnection lines or capacitors.

It may be preferable to form the contact holes510using a SAC etching process. In one embodiment using photolithography, an etching mask, such as a resist pattern, is formed that exposes positions on the ILD layer500where the contact holes510are to be formed. The exposed ILD layer500is then etched to selectively remove the exposed portions, and then exposed first spacer layer410is removed.

The etching process for forming the contact holes510may be performed in a manner that leaves at least a portion of the capping insulating layers300. In one embodiment, the etching process has a sufficient etch selectivity with respect to the capping insulating layers300, so that the ILD layer500is etched at a higher rate. For example, the above-described SAC etching may be performed by dry etching using C5F8and O2as an etch reaction gas. The etch reaction gas may further include argon (Ar). Dry etching using this etch reaction gas can obtain an etch selectivity of about 15:1 of silicon oxide to silicon nitride.

Portions of the first spacer layer410covering the sidewalls of the gates200may be selectively removed by the etching process for forming the contact holes510. Portions of the first spacer layer410covering the surface of the semiconductor substrate100may also be removed, and thus the surface of the semiconductor substrate100may be exposed. As a result, the contact holes510may extend along the exposed sides of the gates200and the exposed sides of the capping insulating layers300. Portions of the first spacer layer410, which are not in the contact holes510and covered with the ILD layer500, may remain on the sidewalls of the gates200, as shown in FIG.8. Also, when the contact holes510are formed by SAC, edge portions of the capping insulating layers300may be etched, as shown. The etched edge portions of the capping insulating layers300may be compensated in a subsequent process.

InFIG. 9, third and fourth spacer layers470and490may be formed, for example, to protect the sidewalls of the gates200exposed by the contact holes510. The third spacer layers470may be formed to selectively cover the exposed sidewalls of the gates200. In one embodiment, the third spacer layers470may be selectively grown to cover the exposed sidewalls of the gates200by thermally oxidizing the silicon oxide. Because the gates200are formed of polysilicon layers210and tungsten silicide layers250, silicon oxide may be selectively grown from the exposed sidewalls of the gates200by an oxidation process. The third spacer layers470may also be grown from the surface of the semiconductor substrate100exposed by the contact holes510, adjacent to the gates200, and may be extended upwardly therefrom.

The fourth spacer layers490may be formed on the third spacer layers470. The fourth spacer layers490may be used as a mask in a subsequent ion implantation process and may be formed of a dielectric material, such as silicon nitride. In one embodiment, silicon nitride may be deposited to a thickness of about 200-300 Å to form the fourth spacer layers490.

InFIG. 10, portions of the fourth spacer layers490may be removed, such as by etching, to form fourth spacers490′. In one embodiment, the fourth spacer layers490are anisotropically etched to form the fourth spacers490′ that cover the sidewalls of the capping insulating layers300and the sidewalls of the gates200. It may be preferable to perform the anisotropic etching so that portions of the fourth spacers490that cover the semiconductor substrate100are removed to expose the surface of the semiconductor substrate100in the contact holes510.

InFIG. 11, ions may be implanted in the semiconductor substrate100exposed by the contact holes510using the fourth spacers490′ as an ion implantation mask. The ion implanting process may form impurity regions190in the surface of the semiconductor substrate100. The ion implantation process may reduce contact resistance between conductive contact pads, that may be subsequently formed to fill the contact holes510and the active regions100, in the semiconductor substrate100.

InFIG. 12, a conductive layer610may be formed to fill the contact holes510and contact the semiconductor substrate100. The conductive layer610may be formed by depositing a polysilicon layer.

InFIG. 13, the conductive layer610may be planarized to form separate conductive contact pads600in the contact holes510. The conductive layer610may be planarized by CMP or etch back. It may be preferable to planarize the conductive layer610until the capping insulating layers300are exposed. The separate contact pads600may later be connected to bit lines (not shown) or storage nodes (not shown) of capacitors. Referring toFIG. 1, the conductive contact pads600may be classified as conductive contact pads610, connected to buried contacts (BC) (not shown), that may be connected to the storage nodes, and conductive contact pads650, connected to direct contacts (DC) (not shown), which may be connected to bit lines. Reference numeral700, shown inFIG. 1, represents the positions of contact holes700for the DC, according to an embodiment of the invention.

According to some aspects of these embodiments, spacers may be provided along the sidewall of the gates. The spacers may be used as an ion implant mask for the semiconductor substrate when ions are implanted into the substrate to form source and drain regions. The thickness of the spacers may be sufficient to mask the substrate so that the gates do not overlap the source and drain regions, and, may thereby, avoid GIDL and/or other deterioration of the device characteristics. The thickness of the spacers may then be reduced to facilitate filling of the gaps with an ILD layer, while substantially avoiding voids in the filled layer. Contact holes for conductive contact pads may be formed in the ILD layer. Spacers may then be formed on the sidewalls of the contact holes, and may be used as an ion implantation mask for the semiconductor substrate. Ions may be implanted in the contact holes to reduce contact resistance between conductive contact pads, which may be formed in the contact holes, and the active regions in the semiconductor substrate.