Input/output circuitry with compensation block

Circuitry including an output circuit having a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block having a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the output circuit having an output impedance determined by the resistance of the first variable resistance block; and a compensation circuit for regulating the impedance of the first variable resistance block of the output circuit, the compensation circuit having a second variable resistance block coupled between the first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein the second variable resistance block comprises a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the first node of the external resistor, and wherein the plurality of selectable resistive elements of the first and second variable resistance blocks are selected based on a voltage level at the first node of the external resistor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of French patent application number 08/57026, filed on Oct. 16, 2008, entitled “INPUT/OUTPUT CIRCUITRY WITH COMPENSATION BLOCK,” which is hereby incorporated by reference to the maximum extent allowable by law.

Field of the Invention

The present invention relates to circuitry comprising a compensation block for regulating the output impedance of an output buffer of the circuitry.

BACKGROUND OF THE INVENTION

When signals are output from one integrated circuit to another via connections on a PCB (Printed Circuit Board), it is generally necessary to amplify them in order to overcome large parasitic capacitance charges present at the two PCB-integrated circuit interfaces. These parasitic charges degrade the signal and thus limit the maximum frequency at which the signal can be transmitted. Output buffers and often pre-amplifiers are used to amplify the output signals. Furthermore, to ensure signal integrity of the transmitted signal at the destination circuit, impedance matching is often performed, such that the impedance of the output buffers matches the impedance of the PCB lines.

Signal integrity includes factors such as signal overshoots, signal slopes, propagation delays and signal to noise ratios, these factors determining when data can be correctly received at the destination circuit. However, due to varying PVT (Process, Voltage and Temperature) conditions, the output impedance of the output buffers in transmission mode may vary at different operating conditions, and can lead to a mismatch between the output impedance and the impedance of the PCB lines, leading to a degradation of the signal integrity.

As clock speeds increase, the rate of data transmission on such PCB lines is also increasing. This makes signal integrity all the more important, and thus precise impedance matching of the impedance of the output buffer with the impedance of the PCB lines for all PVT conditions is critical.

While some solutions exist for matching the output impedance of the output buffers to the impedance of the PCB lines, such solutions are generally inadequate for providing acceptable signal integrity at increased data rates.

SUMMARY OF THE INVENTION

It is an aim of embodiments of the present invention to at least partially address one or more problems in the prior art.

According to one aspect of the present invention, there is provided circuitry comprising an output circuit comprising a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block comprising a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the output circuit having an output impedance determined by the resistance of the first variable resistance block; and a compensation circuit for regulating the impedance of the first variable resistance block of the output circuit, the compensation circuit comprising a second variable resistance block coupled between said first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein the second variable resistance block comprises a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the first node of the external resistor, and wherein said plurality of selectable resistive elements of the first and second variable resistance blocks are selected based on a voltage level at said first node of the external resistor.

According to one embodiment of the present invention, the plurality of selectable resistive elements of the first and second variable resistance blocks are transistors.

According to another embodiment of the present invention, the at least one resistors of the first and second variable resistance blocks are integrated resistors.

According to another embodiment of the present invention, the circuitry further comprises a third variable resistance block coupled between said second supply voltage and said output node and comprising a plurality of selectable resistive elements coupled in series with at least one resistor; said compensation circuit further comprising a fourth variable resistance block coupled between the second supply voltage and a feedback node, the fourth variable resistance block comprising a plurality of selectable resistive elements coupled in series with at least one resistor, the selectable resistive elements of the third and fourth variable resistance blocks being selected based on a voltage level at the feedback node; and the resistive elements of the first and second variable resistance blocks being transistors of a first type, and the resistive elements of the third and fourth variable resistance blocks being transistors of a second type.

According to another embodiment of the present invention, the compensation circuit further comprises a fifth variable resistance block identical to the second variable resistance block and coupled between the first supply voltage and the feedback node, wherein the selectable resistance elements of the fifth variable resistance block are selected based on the voltage at the first node of the external resistor.

According to another embodiment of the present invention, the circuitry comprises a preamplifier comprising: first and second output nodes coupled to said first and third variable resistance blocks respectively; a sixth variable resistance block coupled to the first output node and comprising selectable resistive elements selected based on the voltage at the feedback node; and a seventh variable resistance block coupled to the second output node and comprising selectable resistive elements selected based on the voltage at the first node of the external resistor.

According to another embodiment of the present invention, the dimensions of selectable resistive elements of the first and third variable resistance blocks are different by a determined ratio to those of the selectable resistive elements of the sixth and seventh variable resistance blocks, and the dimensions of the at least one resistor of the first and third variable resistance blocks are different by said determined ratio to the at least one resistors of the sixth and seventh variable resistance blocks.

According to another embodiment of the present invention, the compensation circuitry is arranged to provide a plurality of control signals, one for each of the plurality of selectable resistive elements of the first variable resistance block, said control signals determined based on the voltage at the first node of the external resistor, the output circuitry further comprising control logic arranged to control the plurality of selectable resistive elements of the first variable resistance block based on said plurality of control signals and an input signal from an input node of said output circuit.

According to another embodiment of the present invention, the input circuit comprises a first variable resistance block coupled between the first supply voltage and an input node, the first variable resistance block comprising a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the input node, the input circuit having an input impedance determined by the resistance of the first variable resistance block of the input circuit, wherein the plurality of selectable resistive elements of the first variable resistance block of the input circuit are selected based on said voltage level at said first node of the external resistor of the compensation circuit.

According to a further aspect of the present invention, there is provided a PCB (printed circuit board) comprising first and second integrated circuits coupled together by at least one printed connection on said PCB, wherein at least one of said first and second integrated circuits comprises the above circuitry.

According to another embodiment of the present invention, at least one of the first and second integrated circuits is an external memory device.

According to one aspect of the present invention, there is provided an electronic device comprising a first integrated circuit coupled to a second integrated circuit via at least one conducting track, said first integrated circuit comprising the above circuitry coupled to said at least one conducting track, wherein one of said first and second integrated circuits is an external memory device.

According to one aspect of the present invention, there is provided a method of regulating the output impedance of an output circuit comprising a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block comprising a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the method comprising: adjusting a plurality of control signals to select a plurality of resistive elements in a second variable resistance block, the resistive elements being coupled in series with at least one resistor between said first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein said adjustment is based on the voltage at the first terminal of the external resistor; and selecting one or more of the plurality of resistive elements of the first variable resistance block based on said plurality of control signals.

According to another embodiment of the present invention, the output circuit further comprises a third variable resistance block coupled between the second supply voltage and said output node, the method further comprising: adjusting a further plurality of control signals to select a plurality of resistive elements in a fourth variable resistance block coupled between said second supply voltage and a feedback node, wherein said adjustment is based on the voltage at the feedback node; and selecting one or more of the plurality of resistive elements of the third variable resistance block based on said further plurality of control signals.

According to another embodiment of the present invention, the resistive elements of the first and second variable resistance blocks are transistors of a first type and the resistive elements of the third and fourth variable resistance blocks are transistors of a second type different to the first type.

DETAILED DESCRIPTION

FIG. 1illustrates circuitry100comprising a first circuit102and a second circuit104on a PCB. Each of the circuits102,104is for example an integrated circuit, and circuits102,104are arranged to communicate with each other. As an example, circuit102is a processor comprising a memory controller, and circuit104an external memory device.

A clock signal CLK on line106and data signals DQ0to DQn on lines108to110are transmitted from circuit102to circuit104, via communications interfaces112of circuit102. A communications interface112is provided for each clock/data line, and each comprises an output buffer. Conducting lines114and116to118couple the communications interfaces112of circuit102to circuit104. Each of the conducting lines114to118has an associated impedance. Clock line114is coupled to a DLL (delay-locked loop) or a PLL (phase-locked loop)120of circuit104, while data lines116to118are coupled to communications interfaces122of circuit104, which each comprise input buffers. Communications interfaces122are clocked by an output from the DLL/PLL122.

Each communications interface112of circuit102has a variable output impedance that can be adjusted to match an impedance of the respective conducting lines114to118, as will now be described.

FIG. 2illustrates an embodiment of one of the communications interfaces112.

An input node202receives the clock/data signal to be transmitted via an output circuit203of the communications interface112. An output node204is coupled to the conducting line (not shown inFIG. 2) on which the clock/data signal is to be transmitted.

Input node202is coupled to the output circuit203, and in particular to the control logic block206, via line207and to a control logic block208via a line209. Outputs from control logic blocks206and208control variable resistance blocks210and212respectively. Variable resistance block210is coupled between the supply voltage VDDand the output node204, while variable resistance block212is coupled between the supply voltage VSS, and the output node204. Supply voltage VDDis for example at 1.5 V, while supply voltage VSSis for example at 0 V or a different voltage.

A compensation block214provides control signals PA[0:3] to logic block206on lines216and control signals NA[0:3] to logic block208on lines218. Compensation block214is coupled to an external resistor220, which is in turn coupled to VSS. Compensation block214determines the control signals on lines216and218based on the resistance of external resistor220, and in particular based on the voltage at the terminal of resistor220coupled to the compensation block214.

Variable resistance block210comprises four selectable resistive elements coupled in parallel between an output node204and the supply voltage VDD. Each of the selectable resistive elements is in the form of a p-channel MOS (PMOS) transistor P0to P3respectively, each coupled by its source/drain nodes between the supply voltage VDDand one terminal of a respective resistor222,224,226and228, each of which is integrated on chip. Resistors222to228are for example formed in polysilicon. The other terminals of resistors222to228are coupled to the output node204. The gate nodes of transistors P0to P3are coupled to control logic block206for receiving control signals VP0to VP3respectively.

Variable resistance block212comprises four selectable resistive elements coupled in parallel between output node204and supply voltage VSS. Each of the selectable resistive elements is in the form of a n-channel MOS (NMOS) transistors N0to N3respectively, each coupled by its source/drain nodes between the supply voltage VSSand one terminal of a respective resistor230,232,234and236, each of which is integrated on chip. Resistors230to236are for example formed in polysilicon. The other terminals of resistors230to236are coupled to the output node204. The gate nodes of transistors N0to N3are coupled to control logic block208for receiving control signals VN0to VN3respectively.

In operation, the control signals NA[0:3] and PA[0:3] control which PMOS transistors P0to P3and which NMOS transistors N0to N3are activated to receive the input signal. The number of PMOS and NMOS transistors selected determines the output impedance of the output circuitry. For example, the output impedance on the PMOS side will equal the parallel resistances of each of the activated branches, each branch having a resistance equal to the on resistance of the respective PMOS transistor P0to P3in series with the resistance of the associated resistor222to228. The resistors222to228for example have a resistance representing a substantial proportion of the total impedance of each branch, for example between 50 and 90 percent, and preferable approximately 80 percent of the total resistance of each branch. The same applies to the NMOS side.

The control signals NA[0:3] and PA[0:3] are determined based on the resistance of the external resistor220, which is chosen to have a resistance equal to or a multiple of the impedance of the conducting line on which the output signal is to be transmitted from node204.

FIG. 3Aillustrates the control logic block206ofFIG. 2in more detail. The input line207from the input node202ofFIG. 2is coupled to one source/drain node of a PMOS transistor302and an NMOS transistor304, which are coupled in parallel with each other. The other source/drain nodes of transistors302and304are coupled to a node306, which provides the signal VP0for controlling the first PMOS P0of the variable resistance block ofFIG. 2. Node306is also coupled to the supply voltage VDDvia a PMOS transistor308. The gate node of PMOS302receives the first control signal PA0provided by the compensation block214ofFIG. 2, while NMOS304and PMOS308receive the inverse of PA0.

Transistors312,314, node316and transistor318are arranged in the same way as transistors302,304, node306and transistor308respectively, between the input line207and the supply voltage VDD. PMOS312receives the control signal PA1, while NMOS314and PMOS318receive the inverse of PA1, and node316provides the control voltage VP1to transistor P1inFIG. 2. Similarly, transistors322,324, node326and transistor328are arranged in the same way as transistors302,304, node306and transistor308respectively, between the input line207and the supply voltage VDD. PMOS322receives the control signal PA2, while NMOS324and PMOS328receive the inverse of PA2, and node326provides the control voltage VP2to transistor P2inFIG. 2. Similarly again, transistors332,334, node336and transistor338are arranged in the same way as transistors302,304, node306and transistor308respectively, between the input line207and the supply voltage VDD. PMOS332receives the control signal PA3, while NMOS334and PMOS338receive the inverse of PA3, and node336provides the control voltage VP3to transistor P3inFIG. 2.

Thus when the control signal PA0is high, PMOS302and304are non-conducting, and node306is coupled to VDDby PMOS308, such that transistor P0is non-conducting. On the other hand, when PA0is low, transistors302and304conduct, and transistor308is non-conducting. The input signal on line207is thus coupled to the gate node of P0. Likewise, when PA1, PA2or PA3are high, transistors P1, P2or P3respectively are non-conducting, and when PA1, PA2or PA3are low, transistors P1, P2or P3respectively receive the input signal from line207.

FIG. 3Billustrates the control logic block208ofFIG. 2in more detail. It is identical to control logic block206, except that each group of transistors is coupled between line209and the supply voltage VSS. The transistors and nodes have been labeled with the same reference numerals as corresponding elements inFIG. 3A, but with the addition of an apostrophe. As illustrated, the transistors308′,318′,328′ and338′ are NMOS rather than PMOS transistors, and the transistors all receive the NMOS versions for the control signals NA[0:3] rather than the PMOS versions, except that the PMOS transistors302′,312′,322′ and332′ receive the inverse of NA0, NA1, NA2and NA3respectively, while NMOS transistors304′,314′,324′ and334′ receive signals NA0, NA1, NA2and NA3respectively.

Operation of the control logic208is the same as that of control logic206, and will not be described again in detail.

FIG. 4Aillustrates compensation block214for determining the control voltages PA[0:3] and NA[0:3] provided to the control logic blocks206and208ofFIGS. 3A and 3Brespectively.

The compensation block214comprises a control block402that outputs the control signals PA[0:3] and NA[0:3] on lines216and218to control logic blocks206and208respectively ofFIG. 2. Control signals PA[0:3] are also provided to control variable resistance blocks404and406of the compensation block214, while control signals NA[0:3] are provided to control a variable resistance block408of the compensation block214. Variable resistance blocks404and406are the same as variable resistance block210ofFIG. 2, while variable resistance block408is the same as variable block212ofFIG. 2, and these blocks inFIG. 4Awill not be described again in detail.

The variable resistance block404is coupled between the supply voltage VDDand a node410, which provides a feedback signal to the control block402. Node410is also coupled to one terminal of the external resistor220ofFIG. 2, the other terminal of which is coupled to the supply voltage VSS.

The variable resistance block406is coupled between the supply voltage VDDand a node412, which provides a further feedback to signal to control block402. Given that variable resistance block406is controlled by the same control signals as variable resistance block404, and that it is identical, it will have the same impedance as block404. The variable resistance block408is coupled between the supply voltage VSSand node412.

In operation, during a first phase, the control signals PA[0:3] are determined. For this, the control block402systematically adjusts the control signals PA[0:3] until the voltage on node410is closest to a desired value.

FIG. 4Bis a flow diagram illustrating an example of steps in a calibration sequence for calibrating the control signals PA[0:3].

According to this example, the width, and thus the on resistance Ronof each of the transistors P0to P3of the variable resistance block404are different, with P0the lowest resistance and P3the highest resistance.

In an initial step S0, each of the control signals PA[0:3] is set to logic “1”, thereby making the PMOS transistors P0to P3non-conducting. After S0, each of the transistors P0to P3are tested in turn to determine whether they should be on or off, as will now be explained.

In S1, a first code for PA[0:3] is applied by control block402to activate the least resistive transistor, in this example transistor P0. The first code is thus PA[0:3]=0111. It is then determined whether this code results in RC<RE, in other words whether the impedance RCof the variable resistance block404is lower than the resistance REof the external resistance. This can be determined based on whether the voltage on node410ofFIG. 4Ais higher than the desired value. If so, it is determined that P0should be off, and the next step is S2. On the other hand, if RC≧RE, then P0should be on, and the next step is S3.

In steps S2and S3, transistor P1, which has the next lowest resistance, is activated.

In particular, in step S2, the code PA[0:3]=1011 is applied by the control block402, such that P0is switched off again and transistor P1is activated. It is then determined whether this code results in RC<RE, and if so, the next step is S4in which P1is switched off again, and if not the next step is S5in which P1remains on.

In S3, the code PA[0:3]=0011 is applied by the control block402, such that P0remains activated, and transistor P1is also activated. It is then determined whether this code results in RC<RE, and if so, the next step is S6in which P1is switched off again, and if not the next step is S7in which P1remains on.

In steps S4, S5, S6and S7, transistor P2, which is the next lowest resistance after P1, is activated by applying the codes PA[0:3]=1101, PA[0:3]=1001, PA[0:3]=0101 and PA[0:3]=0001 respectively. In each of these steps it is determined whether the code results in RC<RE. If so, after S4, the control signals PA[0:3] are determined as being equal to “1110”, and after each of steps S5, S6and S7, the next step is S8, S9and S10respectively. If not, the next step after each of steps S4, S5, S6and S7is S11, S12, S13and S14respectively.

After each of steps S8to S14, the control signals PA[0:3] are determined as being equal to the code applied in each of these steps, with a “1” for transistor P3if it is determined in these steps that RC<RE, and a “0” for transistor P3if it is determined that RCis not lower than RE.

Thus, the control signals PA[0:3] can be determined by performing at most four steps in sequence:

a first step corresponding to S1inFIG. 4B;

a second step corresponding to either S2or S3inFIG. 4B;

a third step corresponding to one of S4, S5, S6or S7inFIG. 4B; and, except where it is determined that transistors P0, P1and P2should be off,

a fourth step corresponding to one of S8to S14ofFIG. 4B.

Only three steps are performed in the case that it is determined that each of transistors P0, P1and P2should be off, as at least one transistor should be on, and thus PA[0:3]=1111 is not a valid control signal.

The control signals PA[0:3] that have been determined can be stored and output on lines216to control the output circuit accordingly.

With reference again toFIG. 4A, assuming that resistor220has the same resistance as the conducting line, i.e. the desired resistance of the variable resistance blocks, the desired value of the voltage on line410will be the mid-point between VDDand VSS. Alternatively, in some embodiments resistor220is selected to have a resistance equal to a multiple M of the resistance of the variable resistance blocks, where M is for example twice their resistance. In this case, a desired voltage different from the mid-point could be used. Alternatively, when a multiple M of the PCB line resistance is used for the resistor220, the control signals PA[0:3] could still be determined using VDD/2, but the output circuit could comprise M of the resistance blocks210coupled in parallel.

During a second phase of operation, the control signals NA[0:3] are determined. For this, the determined control signals PA[0:3] are applied to variable resistance block406, and control block402systematically adjusts the control signals NA[0:3] until the voltage at node412is closest to the desired value, which is the same as the desired value used for node410. The transistors N0to N3for example also have varying width and thus varying on resistances, and may be controlled in the same way as for the PMOS transistors P0to P3as explained above in relation toFIG. 4B, except that a high voltage is used to turn them on. As soon as the desired voltage is reached, the associated values of N0to N3are stored and output on lines218to control the output circuit accordingly.

A calibration to determine the control signals NA[0:3] and PA[0:3] is for example performed once during initialization of the circuitry before data transmission, and these values are valid for all subsequent transmission. Alternatively, regular recalibration can be performed, for example every minute, or after a certain number of data packets have been transmitted. Generally, during an initialization phase, the control signals NA[0:3] and PA[0:3] are determined for an ambient temperature, and these values may generally be used for a relatively wide range of temperatures. In some examples, a sensor could trigger a new calibration phase if the temperature exceeds a certain level.

FIG. 5illustrates an alternative embodiment of the communications interface112. The compensation block214and external resistor220are not shown and are for example the same as those ofFIG. 4Aand will not be described again.

The input signal is received at an input node202, and an output node204provides the signal to be transmitted on a conducting line. Between the input and output nodes202,204, a preamplifier506is provided having its inputs coupled to input node202and its outputs coupled to the inputs of an output buffer508, which in turn has its output coupled to the output node204.

The output buffer508is for example identical to the output circuit203ofFIG. 2, except that inFIG. 5the input on lines207and209are provided by different outputs of the preamplifier506.

In this embodiment, the preamplifier506also has a variable output impedance, as will now be explained.

The preamplifier506comprises a PMOS510having its gate node coupled to the input node202, and its source/drain nodes coupled between the supply voltage VDDand an output node512, which is coupled to line207. An NMOS514also has its gate node coupled to the input node202, and its source/drain nodes coupled between the supply voltage VSSand one terminal of a variable resistance block516, which has its other terminal coupled to output node512. Variable resistance block516is for example identical to the variable resistance block212ofFIG. 2, except that transistors N0to N3are coupled to a source/drain node of transistor514rather than directly to VSS.

The preamplifier506further comprises an NMOS520having its gate node coupled to the input node502, and its source/drain nodes coupled between the supply voltage VSSand an output node522, which is coupled to line209. A PMOS524also has its gate node coupled to the input node202, and its source/drain nodes coupled between the supply voltage VDDand one terminal of a variable resistance block526, which has its other terminal coupled to output node522. Variable resistance block526is for example identical to the variable resistance block210ofFIG. 2, except that transistors P0to P3are coupled to a source/drain node of transistor524rather than directly to VDD.

In operation, the NMOS transistors N0to N3of the variable resistance block516and the PMOS transistors P0to P3of the variable resistance block526are controlled directly by the control signals NA[0:3] and PA[0:3] respectively, which are determined by the compensation block214as described above. This has the effect of adjusting the output impedance seen at nodes512and524and thus improving control of the slopes of the rising edges at node209and falling edges at node209.

In the embodiment ofFIG. 5, there may be a ratio between the resistance of the variable resistance blocks516and526of the preamplifier506, and variable resistance blocks210and212of the output buffer. For example, the resistances used in the preamplifier506may be ten times greater than those of the output buffer508. To achieve this, the external resistor220of the compensation circuitry for example has a resistance of ten times the impedance of the conducting line, for example of around 500 ohms and ten of each of the variable resistance blocks210and212are provided in the output buffer508, coupled in parallel such that the combined impedance is one tenth of a single variable resistance block, for example around 50 ohms.

Alternatively, a single pair of variable resistance blocks210and212is provided in the output buffer508, but the transistors P0to P3and N0to N3are ten times as wide as those of the variable resistance blocks516and526. Furthermore, the integrated resistors222to228and230to236have a resistance equal to one tenth of those of the variable resistance blocks516to526of the preamplifier. In this way, there is a fixed ratio between the variable resistance blocks of the preamplifier506and of the output buffer508.

FIG. 6Aillustrates the variable resistance blocks210,404,406and/or526according to an alternative embodiment. Rather than each PMOS transistor P0to P3being coupled to a respective integrated resistor in series, a single integrated resistor602is provided coupled to each of the PMOS transistors.

FIG. 6Billustrates the variable resistance block212,408and/or516according to an alternative embodiment. Again, rather than each NMOS transistor N0to N3being coupled to a respective integrated resistor in series, a single integrated resistor604is provided coupled to each of the NMOS transistors.

As with the serially coupled resistors described previously, the resistors602and604are integrated devices, for example formed of polysilicon, and preferably represent a substantial proportion of the overall resistance of the variable resistance block, for example between 50 and 90 percent, and preferably around 80 percent.

FIG. 7illustrates the communications interface112ofFIG. 2according to an alternative embodiment in which it comprises both output circuit203and an input circuit702.

The output circuit203comprises the preamplifier506and amplifier508ofFIG. 5coupled to the output node204, and these elements will not be described again in detail.

The input circuit702is also coupled to node204, which in this example is coupled to a two-way transmission line. In particular, during a transmission mode, node204is an output node via which data amplified by amplifiers506and508may be transmitted on the transmission line. During a reception mode, node204is an input node via which data may be received from the transmission line.

The input circuit702comprises a node703coupled to node204. Node703is coupled to the supply voltage VDDvia a variable resistance block704, and to supply voltage VSSvia a variable resistance block706. Variable resistance block704is for example identical to the variable resistance block210ofFIG. 2and is controlled by control signals PA[0:3], determined by the compensation block214ofFIG. 2(not shown inFIG. 7). Variable resistance block706is for example identical to the variable resistance block212ofFIG. 2, and is controlled by control signals NA[0:3], determined again by the compensation block214ofFIG. 2.

Node703, is further coupled to a positive input of a differential amplifier708of the input circuit702, which compares the signal at node702with a reference voltage VREF, generally equal to VDD/2, to provide the data signal.

Rather than comprising a single PMOS variable resistance block704and a single NMOS variable resistance block706as shown inFIG. 7, the input circuit702could comprise a plurality of each block coupled in parallel. Assuming that each resistance block has a resistance of 500 Ohms, five NMOS variable resistance blocks and five PMOS variable resistance blocks are for example coupled in place of blocks704and706respectively, such that each group of five variable resistance blocks has an impedance of 100 Ohms, and the overall input impedance seen from node204is 50 Ohms.

FIG. 8illustrates a device800comprising chips802and804, which are mounted on a support (not shown), for example a PCB. Chip802comprises an output circuit806, which is connected by conducting lines on the support to the second chip804, and in particular to input circuitry810of this chip. As illustrated, chip802also comprises compensation circuitry808for calibrating the impedance of the output buffers of the output circuitry806, as described in the embodiments above.

The device800is for example any device in which signals are transmitted between one chip or part of a chip to a second chip or part of the chip, and in which the impedance of output buffers and/or the transition time at the input of the device804is to be controlled. Chip802could for example be part of a processor or DMA (Direct Memory Access) unit, arranged to transmit signals to the second chip804, which could be a separate memory. The memory could for example be a flash memory, SDRAM, DRAM or other type of memory.

Device800is for example a portable electronics device, such as a mobile telephone, MP3 player, PDA (Personal Digital Assistant), portable games console, laptop computer, digital camera or the like.

An advantage of the embodiments described herein is that by providing a variable resistance block having a resistor coupled in series with selectable resistive elements, the impedance variations of the variable resistance block due to varying PVT conditions can be reduced. In particular, resistors tend to have a relatively linear resistance variation due to PVT conditions, whereas selectable resistive elements such as transistors have a less linear resistance variation for varying PVT conditions. Thus the use of fixed integrated resistors makes the total resistance variation of the variable resistance block more linear, and in consequence the output impedance more precise as a function of PVT variations. For varying PVT conditions, the adaptation of the impedance of the output circuit with that of the impedance of the PCB lines on which the data is to be transmitted is also more precise.

A further advantage of the embodiments described herein is that the integrated resistors of the variable resistance block provide a current that is linear with respect to the voltages applied to their terminals. The selectable elements of the variable resistance blocks are formed of MOS transistors, which do not provide a linear current, but by combining the selectable element with the integrated resistors, the MOS transistors represent a reduced proportion of the overall impedance of the variable resistance block. Thus the output impedance of the output buffer using the variable resistance blocks has improved linearity with respect to the impedance of the transmission line, and is more independent of variations in PVT conditions.

There is also an advantage when the variable resistance blocks are used in the preamplifier of the output circuit, as a means of controlling the slope of the control signals to the transistors of the output buffer. In particular, the slopes are more linear for all voltage ranges, and are more independent of variations in PVT conditions.

A further advantage of embodiments described herein is that, by determining different control signals for PMOS and NMOS transistors, differences in the impedance variations between these transistor types can be taken into account. Thus the output impedance can be more accurately controlled for both rising edges and falling edges, and also the rise time and fall time of the edges can be more equal, for varying PVT conditions.

A further advantage of the embodiments described herein is that the output circuit can be used for non-terminated applications in which the conducting line has a floating end point, as well as terminated applications, with good performance in terms of signal integrity. For example, such applications include mobile telephone DDR (double data rate) RAM.

A further advantage of the embodiments described herein is that, due to improved linearity of the variable resistance blocks, impedance variations due to temperature changes are relatively low. This means that calibration of the control signals for the variable resistance blocks can be performed only occasionally, for example once at initialization.

While a number of particular embodiments of the present invention have been described, it will be apparent to those skilled in the art that various modifications and improvements can be applied.

For example, while the present has been described using the example of MOS transistors, alternative types of transistors could be used.

Furthermore, it will apparent to those skilled in the art that the present invention may be applied too a wide range of devices, and not just the examples provided herein.

Furthermore, while in the embodiments described herein the variable resistance blocks comprise four selectable resistive elements coupled in parallel, in alternative embodiments a fewer or greater number may be provided, depending on the precision required. The greater the number of resistive elements, the greater the resistance precision that is possible. Obviously, where more resistive elements are present, more control signal bits will be used to control the variable resistance blocks.

Furthermore, the integrated resistors of the variable resistance blocks may be formed in a variety of different materials, including polycrystalline silicon (poly-Si) or other materials.

Furthermore, while one example of circuitry for controlling the variable resistance blocks has been described, other solutions are possible. Other arrangements of the variable resistance blocks are possible.