Method, system and computer program product for generating simulation sample

A method includes determining a sampling region in a sample space, generating samples in the sampling region without generating samples outside the sampling region, and simulating a performance of a device using the generated samples as input data. The sample space is defined by a plurality of variables associated with the device. Values of the plurality of variables in the sampling region having lower probabilities to meet a specification of the device than values of the plurality of variables outside the sampling region. The method is performed at least partially by at least one processor.

BACKGROUND

The recent trend in miniaturizing integrated circuits (ICs) has resulted in smaller devices which consume less power yet provide more functionality at higher speeds. The miniaturization process has also resulted in stricter design and manufacturing specifications. Various electronic design automation (EDA) processes are developed to generate, optimize and verify designs for semiconductor devices while ensuring that the design and manufacturing specifications are met.

DETAILED DESCRIPTION

In some embodiments, simulation samples are generated, with constraints, to be concentrated in a sampling region of a sample space. Compared to other approaches where simulation samples are generated over the whole sample space and/or without constraints, one or more embodiments achieve one or more effects including, but not limited to, lower simulation time and/or cost, enhanced stability, and higher accuracy, without an increase in the number of simulation samples.

In the following description, one or more simulation sample generation methodologies in accordance with some embodiments are described in the context of a manufacturing process of a semiconductor device. Other arrangements are within the scope of various embodiments. In an example, one or more simulation sample generation methodologies in accordance with some embodiments are applicable to a manufacturing process of a device other than a semiconductor device. In another example, one or more simulation sample generation methodologies in accordance with some embodiments are applicable to one or more aspects other than the manufacture of a device. In a further example, one or more simulation sample generation methodologies in accordance with some embodiments are applicable to various simulation techniques where randomly generated samples are used as input data for simulations. An example simulation technique includes a Monte Carlo (MC) simulation. Other simulation techniques are within the scope of various embodiments.

FIG. 1is a functional flow chart of at least a portion of a semiconductor device design process100, in accordance with some embodiments. The design process100utilizes one or more EDA tools for generating, optimizing and verifying a design of a semiconductor device before manufacturing the semiconductor device. The EDA tools, in some embodiments, comprise one or more sets of executable instructions for execution by a processor or controller or a programmed computer to perform the indicated functionality. In some embodiments, the semiconductor device includes a plurality of interconnected circuit elements. A circuit element includes one or more active elements and/or one or more passive elements. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), FinFETs, planar MOS transistors with raised source/drains. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, and resistors. Interconnects within or among the circuit elements include, but are not limited to, vias, conductive pads, conductive patterns, conductive redistribution lines (RDLs).

At operation110, a design of a semiconductor device is provided by a circuit designer. In some embodiments, the design of the semiconductor device includes a schematic, i.e., an electrical diagram, of the semiconductor device. In some embodiments, the schematic is generated or provided in the form of a schematic netlist. In some embodiments, the circuit designer uses a process design kit (PDK) to develop the design of the semiconductor device. The PDK includes a variety of automated design tools, such as EDA tools, to assist the circuit designer in the design process. In at least one embodiment, the PDK is provided by a foundry to the circuit designer.

At operation120, a pre-layout simulation is performed on the design to determine whether the design meets a predetermined specification. When the design does not meet the predetermined specification, the semiconductor device is redesigned. For example, a modification is made, by the circuit designer using the PDK, to the design to change a configuration of the semiconductor device to meet the predetermined specification, and the process repeats the pre-layout simulation at operation120. When the design meets the predetermined specification, the process proceeds to operation130.

At operation130, a layout of the semiconductor device is generated based on the design. The layout includes the physical positions of various circuit elements of the semiconductor device as well as the physical positions of various interconnects within and among the circuit elements. In some embodiments, the layout is generated by a placement and routing tool.

At operation140, one or more verifications and/or checks are performed. For example, a layout-versus-schematic (LVS) check is performed to ensure that the generated layout corresponds to the design. For another example, a design rule check (DRC) is performed to ensure that the layout satisfies certain manufacturing design rules, i.e., to ensure that the semiconductor device can be manufactured. When one of the checks fails, correction is made to at least one of the layout or the design by returning the process to operation110and/or operation130.

At operation150, a post-layout simulation is performed to determine whether the layout meets a predetermined specification. When the simulation result indicates that the layout does not meet the predetermined specification, e.g., when there are undesirable time delays, correction is made to at least one of the layout or the design by returning the process to operation110and/or operation130. Otherwise, the layout is passed to manufacture at operation160. In some embodiments, one or more of the above-described operations are omitted. For example, the pre-layout simulation at operation120or the post-layout simulation at operation150is omitted in one or more embodiments. In some embodiments, one or more of the above-described operations are performed in an order different from the described order. For example, in at least one embodiment, one or more simulations is/are performed during the IC layout generation at operation130.

In some embodiments, one or more simulations of the semiconductor device design process100, including, but not limited to, the pre-layout simulation at operation120and/or the post-layout simulation at operation150, comprise one or more MC simulations. Other simulation techniques are within the scope of various embodiments. In an example MC simulation, samples are randomly generated. For each generated sample, a circuit simulation is performed using the generated sample as input data. When the circuit simulation indicates that the sample meets a specification of the semiconductor device, the sample is considered feasible. A yield of the semiconductor device is estimated as a percentage of feasible samples among all generated samples. When the estimated yield does not meet a predetermined yield value, a modification is made to the design or configuration of the semiconductor device and the MC simulation is repeated. In some situations, a large number (e.g., millions to billions) of samples is generated to achieve an intended accuracy. As the intended accuracy increases, the number of generated samples is also increased which, in turn, increases the simulation cost and/or time.

To reduce the number of generated samples while achieving the same or better intended accuracy and/or to achieve an increased accuracy without increasing the number of generated samples, simulation sample generation methodologies in accordance with some embodiments generate samples with sampling constraints, so that the generated samples are concentrated in a sampling region where a failure to meet the specification is most likely observed. One or more such simulation sample generation methodologies for identifying a sampling region in accordance with some embodiments are described with reference toFIGS. 2-4, 5A and 5B.

FIG. 2is a diagram for explaining a sample space, a bin division scheme and check points, in accordance with some embodiments. As illustrated inFIG. 2, a sample space200is defined by a plurality of variables. For example, two variables Var1and Var2define the sample space200inFIG. 2as a 2-dimensional sample space in an X-Y plane. However, other numbers of variables are within the scope of various embodiments. For example, n variables define the sample space200as an n-dimensional sample space, where n is a positive integer. In at least one embodiment involving the design and/or manufacture of a semiconductor device, n is from 30 to 1000.

In some embodiments, the variables defining the sample space200are associated with a device, a performance of which is to be simulated. In some embodiments, the variables are associated with a manufacturing process of a device. In some embodiments, the variables include variables of a manufacturing process of a semiconductor device. In some embodiments, the variables defining the sample space200include one or more variables which are not controllable by the circuit designer and which potentially affect a performance or yield of the semiconductor device. Examples of variables which are not controllable by the circuit designer include, but are not limited to, global process variations, local process variations, environmental variations, parasitic parameters, and aging effects. Examples of environmental variables include, but are not limited to, temperature and load variations or conditions.

Variations of the variables defining the sample space200are represented, in some embodiments, by a Gaussian distribution. A Gaussian distribution has a mean value μ and a standard deviation σ. A variable tends to cluster around the mean value μ which means the probability is highest at the mean value μ. The probability is decreased away from the cluster around the mean value μ. For example, variations of Var1inFIG. 2are represented by a probability distribution210. The probability distribution210in an example configuration illustrated inFIG. 2is a standard normal distribution with μ=0 and σ=1. Var1tends to cluster around the mean value μ=0 which has the highest probability. The probability of Var1is decreased away from the cluster around the mean value μ=0. The described values of μ and/or σ are examples. Other values of μ and/or σ are within the scope of various embodiments.

The probability distribution210is divided into a number of areas or bins. In an example configuration illustrated inFIG. 2, the probability distribution210is divided into six bins211-216. The bins211-216of the probability distribution210have corresponding boundaries217-223. For example, the bin211has the boundaries217,218. Other numbers of divided bins per probability distribution are within the scope of various embodiments. For example, the probability distribution210is divided into four bins in at least one embodiment. As the number of bins increases, the accuracy increases but the processing time and/or resource also increase. The number of bins divided from a probability distribution is determined, in at least one embodiment, with considerations of various factors including, but not limited to, accuracy, processing time and/or cost, application.

In an example configuration illustrated inFIG. 2, the bins211-216are divided such that the probabilities of the bins211-216are the same. In particular, the probability of the entire probability distribution210is 1 and the probability distribution210is divided into six bins of the same (or equal) probability. As a result, the probability of each of the bins211-216is ⅙ =16.67%. When the probability distribution210is divided into six bins211-216having the same probability, the values of Var1on the boundaries217-223are correspondingly −3σ, −0.97σ, −0.43σ, 0, 0.43σ, 0.97σ and 3σ. Values of Var1in each of the bins211-216are given the same probability of the corresponding bin. For example, values of Var1between −0.97σ and −0.43σ have the same probability of 16.67%. When the probability distribution210is divided into four bins having the same probability, the values of Var1on the corresponding boundaries are −3σ, −0.68σ, 0, 0.68σ and 3σ. The described bin division scheme of the probability distribution210to include divided bins having the same probability is an example. Other bin division schemes are within the scope of various embodiments. For example, an alternative bin division scheme, where the divided bins have the same width, is described with respect toFIG. 3.

Variations of Var2are represented by a probability distribution230. The probability distribution230in an example configuration illustrate inFIG. 2is also a standard normal distribution and is divided into six bins having the same probability as described with respect to the probability distribution210. Other arrangements are within the scope of various embodiments. For example, in at least one embodiment, the probability distribution230is divided into a number of bins different from that of the probability distribution210and/or based on a bin division scheme different from that of the probability distribution210. In some embodiments, one or more values of μ and/or σ of one variable (e.g., Van) is/are different from those of μ and/or σ of another variable (e.g., Var2).

In an example configuration illustrated inFIG. 2, the sample space200is defined as the region within a 3σ contour233. The 3σ contour233is a circle having a center at a nominal point (designated with the star symbol inFIG. 2) and a radius of 3σ. The nominal point corresponds to the zero values of Var1and Var2. The radius of the 3σ contour233corresponds to the farthest distance from the outermost boundaries (e.g., boundaries217and223of the probability distribution210) to the nominal point. Other configurations of the sample space200are within the scope of various embodiments. In general, the sample space200corresponds to a kσ contour, where k is a positive integer. For example, when k=4, the sample space200corresponds to a 4σ contour234; when k=5, the sample space200corresponds to a 5σ contour235; and when k=6, the sample space200corresponds to a 6σ contour236. As the value of k increases, the accuracy increases but the processing time and/or resource also increase. The value of k is determined, in at least one embodiment, with considerations of various factors including, but not limited to, accuracy, processing time and/or cost, application.

A plurality of check points (designated with the circle symbols inFIG. 2) are selected to be at intersections of boundaries of the divided bins of the probability distributions of the variables. For example, a check point240is identified as the intersection between the boundary221corresponding to the value 0.43σ of Var1, and a boundary241corresponding to the value −0.43σ of Var2. In an example configuration illustrated inFIG. 2, intersections located along the center boundaries (e.g., the boundary220) corresponding to the zero values of Var1and Var2are not selected as check points. Intersections (designated with the triangle symbols inFIG. 2) of the center boundaries (e.g., the boundary220) corresponding to the zero values of Var1and Var2and the outermost boundaries (e.g., the boundaries217,223) corresponding to the values −3σ and 3σ of Var1and Var2are used as perturbation analysis points as described herein. Scores of the check points are determined as described herein to identify a sampling region in accordance with some embodiments.

FIG. 3is a diagram for explaining a bin division scheme, in accordance with some embodiments. As illustrated inFIG. 3, a probability distribution310of an ithvariable Vari(i=1. . . n) is divided into a plurality of bins, three of which, i.e., bins311,312, and313, are illustrated as examples inFIG. 3. The divided bins of the probability distribution310have the same width. For example, the width of the bin311is a difference between values of Varicorresponding to boundaries314,315of the bin311. The width of the bin312is a difference between values of Varicorresponding to boundaries315,316of the bin312. The widths of the bins311and312are the same, i.e., ΔXi. While the widths of the bins311-313are the same, their probabilities are different. For example, the probability of the bin313is greater than the probability of the bin312which, in turn, is greater than the probability of the bin311. In general, a probability Pxiof a point xi(and the corresponding bin) located between values a and b of Variis determined by the following equation:

Other techniques for determining probabilities of in various bins of the probability distribution310are within the scope of various embodiments. For example, probabilities and boundaries of the corresponding bins of the probability distribution310are stored in a look-up table. The determined probabilities are used to calculate the scores of the check points as described herein.

In some embodiments, to determine the scores of the check points, weight values of the variables are determined. For example, the following equations are used in at least one embodiment to determine normalized weight value of each of the variables:

where

xiis a value of an ithvariable of the plurality of variables,

σ is a standard deviation of the probability distribution of the ithvariable,

μ is a mean value of the probability distribution of the ithvariable,

k is a positive integer,

Perf is a performance function associated with the ithvariable,

wi±is a weight value of the ithvariable before normalization, and

wi_n±is a normalized weight value of the ithvariable, wi_n−corresponds to xi<0, wi_n+corresponds to xi≥0.

In at least one embodiment, k=3. In some embodiments, the performance function Perf represents a model of at least a portion of the semiconductor device. In some embodiments, the values Perf(xi=μ±kσ)and Perf(xi=μ)are obtained by a perturbation analysis in which a simulation of at least a portion of the semiconductor device is performed at the perturbation analysis points xi=μ±kσ and xi=μ. The described calculation of the weight values and/or the normalized weight values of the variables is an example. Other arrangements for determining weight values are within the scope of various embodiments.

In some embodiments, the score of each of the check points are determined based on one or more of the weight values of the variables, values of the variables at the check point, and probabilities of the values of the variables at the check point. For example, the following equations are used in at least one embodiment to determine the score of each of the check points:

where

scorejis the score of a jthcheck point among the check points,

n is a number of the variables,

xijis a difference between a value of the ithvariable (Vari) at the jthcheck point and the mean value μ of the probability distribution of the ithvariable,

Pjis a probability of the jthcheck point with respect to the variables,

Pxijis a probability of the jthcheck point with respect to the ithvariable,

P is a probability distribution function describing the probability distribution of the ithvariable, and

a and b are values of the ithvariable at the boundaries of the divided area corresponding to xij*wi_n±.

In some embodiments, the probability distribution function P is represented by the equation (1) described with respect toFIG. 3. In some embodiments, when the probability distribution of Variis divided into bins having the same probability, the probability Pxijis the same at all values of Vari.

For example, the score of the check point240inFIG. 2for two variables (n=2) is calculated in accordance with some embodiments as follows.

For Var1, x1j=0.43σ which corresponds to the boundary221of the probability distribution210of Var1, Px1j=16.67%=0.1667 which is the same for all values of Var1, and wi_n±is w1_n+for i=1 and x1j=0.43σ>0.

For Var2, x2j=−0.43σ which corresponds to the boundary241of the probability distribution230of Var2, and Px2j=16.67%=0.1667 which is the same for all values of Var2, and wi_n±is w2_n−for i=2 and x2j=−0.43σ<0.

The score of the check point240inFIG. 2is 0.02779/(0.43σ*(w1_n+−w2_n−)).

The described determination of the scores of the check points is an example. Other arrangements for determining the scores of the check points are within the scope of various embodiments. An example alternative method is described in U.S. provisional application No. 61/881,091, filed Sep. 23, 2013, the disclosure of which is incorporated by reference herein in its entirety.

In some embodiments, the scores of the check points are used to determine sampling constraints for generation of simulation samples. The lower the score of a check point, the lower the likelihood that values of the variables at, or in a vicinity of, the check point will meet the specification of the semiconductor device. In at least one embodiment, the scores are sorted in a descending or acceding order. The check points having the corresponding scores lower than a predetermined threshold are identified as low score check points, i.e., locations with low probabilities that the specification of the semiconductor device will be met. In at least one embodiment, the predetermined threshold is a predetermined score value. In at least one embodiment, the predetermined threshold is a predetermined percentile value. For example, for 1000 check points and with a predetermined percentile value of 99, the worse 1 percent, i.e., 10 check points, with the lowest scores, are identified as low score check points, i.e., locations with low probabilities of the specification being met.

FIG. 4is a diagram similar toFIG. 2, and shows various check points identified as low score check points (designated with the square symbols) based on the corresponding scores. The low score check points define sampling constraints for simulation sample generation. For example, in an example configuration illustrated inFIG. 4, the low score check points all have values of Var1equal to or greater than 0.43σ. As a result, 0.43σ is determined as a sampling constraint C1for Var1. In a subsequent simulation sample generation, samples will be generated to satisfy this sampling constraint C1, i.e., to have values of Van equal to or greater than C1=0.43σ. Further, in an example configuration illustrated inFIG. 4, the low score check points all have values of Var2equal to or greater than −0.43σ. As a result, −0.43σ is determined as a sampling constraint C2for Var2. In a subsequent simulation sample generation, samples will be generated to satisfy this sampling constraint C2, i.e., to have values of Var2equal to or greater than C2=−0.43σ. The sampling constraints Var1≥C1and Var2≥C2defining corresponding boundaries221,241of a sampling region443in the sample space which, in an example configuration illustrated inFIG. 4, comprises the 3σ contour233. As described herein with respect toFIGS. 5A-5B, values of the variables in the sampling region443have lower probabilities to meet the specification of the semiconductor device than values of the variables outside the sampling region443, i.e., in the remaining region of the sample space (i.e., the 3σ contour)233. The sampling region443includes simulation targets for extracting statistical corners, and simulation samples are generated in the sampling region443in accordance with some embodiments

FIG. 5Ais a diagram showing simulation sample generation in a sampling region in accordance with some embodiments. For example, simulation samples550are generated in the sampling region443, without being generated outside the sampling region443, i.e., without being generated in a remaining region544of the sample space233. One or more simulation sample generation methodologies in accordance with some embodiments are not limited to a particular sampling algorithm. Example sampling algorithms for generating simulation samples550include, but are not limited to, pseudo-random sampling algorithms, variance reduction techniques, low discrepancy sequences and the like.

FIG. 5Bis a graph showing a distribution555of simulation results corresponding to generated simulation samples. In the distribution555, the horizontal axis indicates simulated performance variation, and the vertical axis indicates the number of simulation results having a particular performance variation value. Simulation results560inFIG. 5Bcorrespond to the simulation samples550in the sampling region443inFIG. 5A. The simulation results560tend to concentrate in a worst-case performance region563around the specification. In other approaches where simulation samples are also generated in the remaining region544of the sample space233inFIG. 5A, corresponding simulation results would tend to concentrate in a remaining region564of the distribution555inFIG. 5B. In other words, values of the variables in the sampling region443have lower probabilities to meet the specification of the semiconductor device than values of the variables outside the sampling region443, i.e., in the remaining region544of the sample space233.

InFIG. 5B, simulation results560corresponding to performance variation values smaller than (i.e., failing to meet) the specification indicate failed samples. A ratio of the number of failed samples to a total number of samples is used to estimate the yield of the semiconductor device in one or more embodiments. In some situations, a low number of failed samples affects the accuracy of the estimated yield and/or statistical corner extraction. To locate more failed samples, other approaches increase the number of generated samples with an associated increase in simulation time and cost.

One or more simulation sample generation methodologies in accordance with some embodiments make it possible to increase the number of failed samples without increasing the number of generated samples. An example is detailed in Table 1.

In the example in Table 1, five variables PG2_var1, PU2_var1, PG1_var1, PD1_var1 and PG2_var2 are considered for determining a sampling region. The variables' corresponding weight values, sampling constraints and numbers of selected bins are given in Table 1. In this example, the probability distribution of each of the variables is divided into six bins. In the example, the higher the absolute value of the weight value (hereinafter referred to as “absolute weight value”) of a variable, the greater impact the variable has on a probability of a sample meeting the specification. Variables having the absolute weight values greater than a predetermined threshold are considered critical. In the example, the five variables are considered critical based on the corresponding absolute weight values. The example further includes other, non-critical variables with lower absolute weight values than shown in Table 1. In at least one embodiment, non-critical variables are not considered for determining a sampling region, and simulation samples are generated across the sample space with respect to the non-critical variables.

A ratio of concentration of samples in the sampling region is determined in accordance with some embodiments with the following equation:

where Number of Total bins is the a total number of all bins for all variables, and Number of Selected bins is a total number of the bins corresponding the sampling region. In in at least one embodiment, this ratio is determined simply by using the equation (7), without determining, e.g., by integration, the actual areas of the sampling region and the sample space. This increases the processing speed in at least one embodiment.

The ratio of 162 indicates that the simulation sample generation methodologies in accordance with some embodiments in this particular example provide an increase of 162 times in coverage. For example, assuming that, in this example, ten (10) billion samples are generated. The coverage provided by this example is equivalent to that provided by other approaches with 1620 billion samples. At a predetermined yield value of 99.9999999013%, the acceptable number of failed samples for meeting the predetermined yield value is (1−99.9999999013%)*10*109=9.87, in accordance with other approaches. In other words, out of 10 billion samples, only 9 failed samples are permitted by other approaches when the predetermined yield value of 99.9999999013% is to be met. Such a low acceptable number (i.e., 9) of failed samples compared to a much larger number of generated samples (i.e., ten billion) potentially involves a risk of yield estimation inaccuracy.

Because the simulation sample generation methodologies in accordance with some embodiments in this particular example provide an increase of 162 times in coverage equivalent to 1620 billion samples, an acceptable number of failed samples in this particular example is not greater than (1-99.9999999013%)*1620*109=1598.94, i.e., 1598. Given the same number (10 billion) of generated samples and the same predetermined yield value of 99.9999999013%, this particular example provides a much higher acceptable number (1598) of failed samples, compared with 9 samples as in the other approaches. Accordingly, accuracy is increased in one or more embodiments. Given the sufficient number of failed samples in accordance with some embodiments, a statistical corner extraction and/or another analysis is unlikely to involve multiple simulation iterations which further speeds-up the processing time.

In at least one embodiment, the acceptable number of failed samples (also referred to herein as fail rate) is further increased by increasing the number of divided bins for one or more variables, without increasing the number of generated samples. In an example, when the probability distribution of each of five variables is divided into four bins, the fail rate is increased 76 times compared to other approaches. When the probability distribution of each of five variables is divided into six bins, the fail rate is increased 116 times compared to other approaches.

In one or more simulation sample generation methodologies in accordance with some embodiments, the simulation samples are concentrated at locations where the specification of the semiconductor device is likely violated, without spending simulation time and/or cost outside the sampling region where the specification of the semiconductor device is likely met. The concentration of simulation samples in a sampling region, instead of spreading simulation samples all over the sample space as in other approaches, permit one or more embodiments to improve one or more of accuracy, time, cost, stability, MC error of the simulation.

One or more simulation sample generation methodologies in accordance with some embodiments are independent of circuit structures or configurations, and/or independent of sampling algorithms. One or more simulation sample generation methodologies in accordance with some embodiments are applicable to advanced process nodes, such as N10 and beyond, and/or applicable to high sigma analyses. One or more simulation sample generation methodologies in accordance with some embodiments further speed up the design and/or manufacturing processes, especially the design-for-yield flow.

FIG. 6is a flow chart of a method600in accordance with some embodiments. In at least one embodiment, the method600is performed, at least partially, by at least one processor or computer system as described herein.

At operation605, a sampling region is determined in a sample space. In in at least one embodiment, the sample space is defined by a plurality of variables associated with a device, and values of the variables in the sampling region have lower probabilities to meet a specification of the device than values of the plurality of variables outside the sampling region. For example, a sampling region443is determined in a sample space233as described with respect toFIGS. 2-4.

At operation615, samples are generated in the sampling region. In at least one embodiment, samples are not generated outside the sampling region, by, e.g., using one or more sampling constraints. For example, simulation samples550are generated in the sampling region443as described with respect toFIG. 5A.

At operation625, a simulation is performed, using the generated samples as input data. In at least one embodiment, the performed simulation is an MC simulation. For example, simulation samples550are used as input data for a simulation as described with respect toFIG. 5B, and simulation results are analyzed for device modification and/or yield estimation as described with respect toFIG. 1.

In some embodiments, the sampling region determination at operation605includes one or more of the following operations.

At operation635, probability distributions of a plurality of variables are divided into bins (or areas). In at least one embodiment, the bins divided from the same probability distribution have the same probability or width. For example, probability distributions210,230are divided into a plurality of bins, as described with respect toFIG. 2.

At operation645, intersections of the boundaries of the divided bins are identified as a plurality of check points. For example, check points (designated with the circle symbols) are determined at the intersections of the bins' boundaries, as described with respect toFIG. 2.

At operation655, scores of the check points are determined. For example, an equation-based method is used to determine the scores of the check points, as described with respect to equations (2)-(6).

At operation665, sampling constraints (or a boundary of the sampling region) are determined based on the scores of the check points. For example, the check points are sorted by the corresponding scores and the check points with the lowest scores are identified and used for determining sampling constraints, as described with respect toFIG. 4.

The above methods include example operations, but they are not necessarily required to be performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiments of the disclosure. Embodiments that combine different features and/or different embodiments are within the scope of the disclosure and will be apparent to those of ordinary skill in the art after reviewing this disclosure.

FIG. 7is a block diagram of a computer system700in accordance with some embodiments. One or more of the tools and/or engines and/or systems and/or operations described with respect toFIGS. 1-6is realized in some embodiments by one or more computer systems700ofFIG. 7. The system700comprises at least one processor701, a memory702, a network interface (I/F)706, a storage710, an input/output (I/O) device708communicatively coupled via a bus704or other interconnection communication mechanism.

The memory702comprises, in some embodiments, a random access memory (RAM) and/or other dynamic storage device and/or read only memory (ROM) and/or other static storage device, coupled to the bus704for storing data and/or instructions to be executed by the processor701, e.g., kernel714, userspace716, portions of the kernel and/or the userspace, and components thereof. The memory702is also used, in some embodiments, for storing temporary variables or other intermediate information during execution of instructions to be executed by the processor701.

In some embodiments, a storage device710, such as a magnetic disk or optical disk, is coupled to the bus704for storing data and/or instructions, e.g., kernel714, userspace716, etc. The I/O device708comprises an input device, an output device and/or a combined input/output device for enabling user interaction with the system700. An input device comprises, for example, a keyboard, keypad, mouse, trackball, trackpad, and/or cursor direction keys for communicating information and commands to the processor701. An output device comprises, for example, a display, a printer, a voice synthesizer, etc. for communicating information to a user.

In some embodiments, one or more operations and/or functionality of the tools and/or engines and/or systems described with respect toFIGS. 1-6are realized by the processor701, which is programmed for performing such operations and/or functionality. In some embodiments, the processor701is configured as specifically configured hardware (e.g., one or more application specific integrated circuits (ASICs)). One or more of the memory702, the I/F706, the storage710, the I/O device708, the hardware components718, and the bus704is/are operable to receive instructions, data, design constraints, design rules, netlists, layouts, models and/or other parameters for processing by the processor701.

In some embodiments, simulation samples are generated, with constraints, to be concentrated in a sampling region of a sample space. Compared to other approaches where simulation samples are generated over the whole sample space and/or without constraints, at least one embodiment achieves one or more effects including, but not limited to, lower simulation time and/or cost, enhanced stability, and higher accuracy, without an increase in the number of simulation samples.

In some embodiments, a method comprises determining a sampling region in a sample space, generating samples in the sampling region without generating samples outside the sampling region, and simulating a performance of a device using the generated samples as input data. The sample space is defined by a plurality of variables associated with the device. Values of the plurality of variables in the sampling region having lower probabilities to meet a specification of the device than values of the plurality of variables outside the sampling region. The method is performed at least partially by at least one processor.

In some embodiments, a system comprises at least one processor configured to divide probability distributions of a plurality of variables into areas having boundaries, identify intersections of the boundaries as a plurality of check points, determine scores of the plurality of check points, determine sampling constraints based on the scores of the plurality of check points, and generate samples satisfying the sampling constraints as simulation input data.

In some embodiments, a computer program product comprises a non-transitory, computer-readable medium containing instructions therein which, when executed by at least one processor, cause the at least one processor to divide a first probability distribution of a first variable of a plurality of variables into first areas having first boundaries, and divide a second probability distribution of a second variable of the plurality of variables into second areas having second boundaries. The first areas have the same probability. The second areas have the same probability. The plurality of variables is associated with a manufacturing process of a semiconductor device. The instructions, when executed, further cause the at least one processor to identify intersections of the first boundaries with the second boundaries as a plurality of check points, determine scores of the plurality of check points, determine first and second sampling constraints corresponding to the first and second variables based on the scores of the plurality of check points, generate samples satisfying the first and second sampling constraints, and simulate a performance of the semiconductor device using the generated samples as input data. The first sampling constraint corresponds to one of the first boundaries, and the second sampling constraint corresponds to one of the second boundaries.