Semiconductor device and fabrication method of the same

A semiconductor device including a first conduction type semiconductor layer; a second conduction type element forming region formed above the first conduction type semiconductor layer and formed with at least one semiconductor element formed on a surface region of the second conduction type element forming region; a first conduction type element-isolation region insulating and segregating the second conduction type element forming region from the exterior; and a second conduction type buried region formed at the interface of the first conduction type semiconductor layer and the second conduction type element forming region, formed separated from the first conduction type element-isolation region. In the semiconductor device a second conduction type high concentration region is buried in the surface of the second conduction type element forming region and formed to surround the semiconductor element and separated from the first conduction type element-isolation region.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC 119 from Japanese Patent Application No. 2008-211937 filed on Aug. 20, 2008, the disclosure of which is incorporated by reference herein.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device and to a fabrication method thereof, and in particular to a semiconductor device with a high element-isolation breakdown voltage in impurity element-isolation regions, and to a fabrication method of the same.

2. Related Art

Along with developments in making electrical devices more compact and lowering their cost, there is also demand for more compactness in power transistors for installation in such electrical devices. In particular, technology for integrating a control circuit and plural power transistors (semiconductor elements) onto the same semiconductor substrate is essential in electrical devices that are subject to demands for even more compactness, such as mobile devices and household devices. When forming plural semiconductor elements on the same semiconductor substrate, methods exist for element-isolation between semiconductor elements by use of impurity element-isolation regions.

Apart from the above demands for more compactness and higher integration, there are also demands for higher breakdown voltages of semiconductor devices. Greater currents can be used for driving semiconductor devices accommodating such high breakdown voltages. Such semiconductor devices can prevent various current leaks and avoid latching up. For example, the breakdown voltage required in semiconductor devices is of the order of a few V for microcomputer, DRAM, and memory use, of the order of a few tens of V for LCD driver use, and of the order of several hundreds of V for high voltage display use.

An example of a high breakdown voltage electric field effect transistor (HVMOS: High Voltage Metal-Oxide-Semiconductor) will now be explained, with reference toFIG. 1.

As shown inFIG. 1, an HVMOS200is configured with a P-type silicon substrate201, an N-type epitaxial layer202formed above the P-type silicon substrate201, an N-type buried layer203selectively formed at the interface of the P-type silicon substrate201and the N-type epitaxial layer202, an inter-layer insulating layer204formed above the N-type epitaxial layer202, and a metal wiring layer205formed above the inter-layer insulating layer204.

A P-type drift layer206, a P-type high concentration region207(referred to below as P+region), and a field oxide film208are formed on the N-type epitaxial layer202. A gate oxidized film209, and a gate electrode210that is made from poly-crystalline silicon, are formed above the N-type epitaxial layer202. A P-type isolation region211electrically connected to the P-type silicon substrate201is formed in the N-type epitaxial layer202. An element region of the HVMOS200is element-isolated by the P-type isolation region211. The P+region207is connected to the metal wiring layer205via a contact line212that penetrates through the inter-layer insulating layer204.

The HVMOS200configured as described above can accommodate high breakdown voltages due to the N-type buried layer203formed at the interface of the P-type silicon substrate201and the N-type epitaxial layer202. A reason for this is that the resistance value of the N-type region formed by the N-type epitaxial layer202and the N-type buried layer203is lower than the resistance value of the N-type epitaxial layer202alone, and so resistance to latch-up of the HVMOS200is raised. In addition, since isolation of the P-type silicon substrate201from the N-type epitaxial layer202is ensured by the N-type buried layer203, leak current from the P-type silicon substrate201to the N-type epitaxial layer202is prevented from occurring, and robustness to noise can be raised.

In an HVMOS200such as that shown inFIG. 1, the isolation breakdown voltage between adjacent element regions is determined by the PN junction between the P-type isolation region211and the N-type epitaxial layer202. If the isolation breakdown voltage between adjacent element regions is lower than the operating voltage of the HVMOS200, then when the operating voltage is applied to a given metal line205, a leak current occurs from the N-type epitaxial layer202of a semiconductor element that includes the metal wiring layer205to which the operating voltage has been applied, through the P-type isolation region211, to the N-type epitaxial layer202of an adjacent semiconductor element. The HVMOS200can no longer be operated correctly when such a leak current occurs.

In Japanese Patent Application Laid-Open (JP-A) No. 5-299498 a semiconductor device is described that can achieve suppression of leak current and stronger latch-up resistance without the provision of a buried layer as described above. In the semiconductor device described in JP-A No. 5-299498, by provision of a channel stopper region in a silicon substrate bottom face, and by having a trench buried insulating film penetrating to the channel stopper region through the silicon substrate and through an impurity well region, suppression of leak current and stronger latch-up resistance can be achieved.

However, in the HVMOS200shown inFIG. 1, if an even higher breakdown voltage is required then there is the problem that sufficiently a high breakdown voltage cannot be achieved in practice.

The present invention is made in consideration of the above circumstances, and provides a semiconductor device with a buried layer formed at a semiconductor substrate and epitaxial layer interface, the semiconductor device enabling sufficiently higher breakdown voltage to be achieved. A fabrication method of the same is also provided.

SUMMARY

The present invention has been made in view of the above circumstance and provides a semiconductor device.

The present invention provides a semiconductor device including: a first conduction type semiconductor layer; a second conduction type element forming region formed above the first conduction type semiconductor layer and formed with at least one semiconductor element formed on a surface region of the second conduction type element forming region; a first conduction type element-isolation region that segregates the second conduction type element forming region; a second conduction type buried region formed at the interface of the first conduction type semiconductor layer and the second conduction type element forming region, separated from the first conduction type element-isolation region; and a second conduction type high concentration region buried in a surface of the second conduction type element forming region and also formed to surround the semiconductor element and separated from the first conduction type element-isolation region.

The present invention provides a semiconductor device on which a plurality of element regions for forming semiconductor elements are consolidated so as to be electrically isolated from each other by a first conduction type element-isolation region, wherein: each of the element regions includes a first conduction type semiconductor layer, a second conduction type element forming region, and a second conduction type buried layer interposed between the first conduction type semiconductor layer and the second conduction type element forming region; and in the second conduction type element forming region, by forming a second conduction type high concentration region buried in the surface of the second conduction type element forming region so as to be separated from the first conduction type element-isolation region and so as to surround the semiconductor element, adjacent element regions have a higher isolation breakdown voltage in comparison to a case where the second conduction type high concentration region is not provided.

The semiconductor device according to the present invention, as well as burying a second conduction type high concentration region in the surface of a second conduction type element forming layer formed on a first conduction type semiconductor substrate, also has the second conduction type high concentration region surrounding the semiconductor elements formed on the surface of the second conduction type element forming layer and being separated from the first conduction type element-isolation region for segregating the semiconductor elements. The isolation breakdown voltage between the adjacent element regions can thereby be increased to a high breakdown voltage.

Another aspect of the present invention provides a semiconductor device fabrication method including:

a preparation process of preparing a first conduction type semiconductor substrate;

a buried layer forming process of forming a second conduction type buried layer including a non-continuous portion on the surface of the first conduction type semiconductor substrate;

an element layer forming process of forming a second conduction type element forming layer above the first conduction type semiconductor substrate and the second conduction type buried layer;

a high concentration region forming process of forming a second conduction type high concentration region in a surface region of the second conduction type element forming layer, the second conduction type high concentration region having an impurity concentration higher than that of the second conduction type element forming layer;

an element-isolation region forming process of forming a first conduction type element-isolation region above the non-continuous portion in the second conduction type buried layer and separated from the second conduction type high concentration region; and

an element forming process of forming a semiconductor element in the surface region of the second conduction type element forming layer in a region surrounded by the second conduction type high concentration region.

In the element-isolation region forming process, the first conduction type element-isolation region may be formed such that the outside end portion of the second conduction type high concentration region faces a region between the second conduction type buried layer and the first conduction type element-isolation region.

In the element-isolation region forming process, the first conduction type element-isolation region may be formed such that the separation distance from the first conduction type element-isolation region to the second conduction type high concentration region is 20% to 60% of the separation distance from the first conduction type element-isolation region to the second conduction type buried layer.

In the element-isolation region forming process, the first conduction type element-isolation region may be formed such that the separation distance from the first conduction type element-isolation region to the second conduction type high concentration region is 30% to 40% of the separation distance from the first conduction type element-isolation region to the second conduction type buried layer.

In the high concentration region forming process, the second conduction type high concentration region may be formed such that the second conduction type buried layer and at least one portion of the second conduction type high concentration region face each other.

The high concentration region forming process may further comprise forming an element-isolation insulation film on the second conduction type high concentration region by thermal processing.

DETAILED DESCRIPTION

Explanation will now be given of details of an exemplary embodiment of the present invention, with reference to the accompanying drawings.

First, explanation will be given regarding the structure of a semiconductor device that is an exemplary embodiment of the present invention, with reference toFIG. 2andFIG. 5.

FIG. 2is a cross-section of part of a semiconductor device10(a cross-section taken on lines2-2shown (with a single dashed intermittent line) inFIG. 3andFIG. 4). As shown inFIG. 2, the semiconductor device10is segregated by a P-type element-isolation region, described later, into an LDMOS section10aformed by an LDMOS transistor (LDMOS: Lateral Diffusion Metal-Oxide-Semiconductor), and an HVMOS section10bformed from an HVMOS transistor (HVMOS: High Voltage Metal-Oxide-Semiconductor).

The semiconductor device10is configured from a P-type semiconductor substrate11, an N-type epitaxial layer12formed above the P-type semiconductor substrate11, an N-type buried layer13formed at the interface of the P-type semiconductor substrate11and the N-type epitaxial layer12, an inter-layer insulating layer14formed above the N-type epitaxial layer12, and an LDMOS source electrode15a, an HVMOS source electrode15b, an LDMOS drain electrode16aand an HVMOS drain electrode16bthat are formed from metal wiring above the inter-layer insulating layer14.

A first high concentration P-type region17a(referred to below simply as P+region17a), a second high concentration P-type region17b(referred to below simply as P+region17b), a first N-type high concentration region18(referred to below simply as N+region18), a P-type body layer19, a first field oxide film20a, a second field oxide film20b, and an LDMOS channel stopper21athat is a second N-type high concentration region, are formed on the surface of the N-type epitaxial layer12of the LDMOS section10a. Third high concentration P-type regions17c(referred to below simply as P+regions17c), a second field oxide film20b, a third field oxide film20c, an HVMOS channel stopper21bthat is a third N-type high concentration region, and a P-type drift layer22are formed on the surface of the N-type epitaxial layer12of the HVMOS section10b. The impurity regions formed on the surface of the N-type epitaxial layer12, and the gate oxidation film and the gate electrode etc., which will be described below, are referred to in general below as semiconductor elements. A P-type isolation region23is formed in the N-type epitaxial layer12for element-isolation of the LDMOS section10afrom the HVMOS section10b(namely for segregating the semiconductor element formed by the LDMOS section10afrom the semiconductor elements formed by the HVMOS section10b). The second field oxide film20bis above the P-type isolation region23, and is formed so as to straddle both sections of the LDMOS section10aand the HVMOS section10b.

An LDMOS gate oxidation film24a, an HVMOS gate oxidation film24b, and an LDMOS gate electrode25aand an HVMOS gate electrode25bformed from polycrystalline silicon, are formed above the N-type epitaxial layer12of the LDMOS section10aand the HVMOS section10b. Contact lines26ato26cfor electrically connecting each of the source electrodes, or each of the drain electrodes, to the P+regions17ato17c, or to the N+region18, are formed in the inter-layer insulating layer14of the LDMOS section10aand the HVMOS section10b. Specifically, the LDMOS source electrode15ais connected to the P+region17aand the N+region18by the contact line26a, the LDMOS drain electrode16ais connected to the P+region17bby the contact line26b, and the HVMOS source electrode15band the HVMOS drain electrode16bare connected to the P+region17cby the contact lines26c.

Explanation will now be given of the plan view structure of the semiconductor device10, with reference toFIG. 3andFIG. 4.FIG. 3is a diagram in which each of the impurity regions and the wiring layout of each of the contact lines in the semiconductor device10are represented in plan view.FIG. 4is a diagram in which each type of electrode formed on the surface of the semiconductor device10and each contact line connected to each type of electrode is represented in plan view.

As shown inFIG. 3, there are four LDMOS gate electrodes25aformed in rectangular shapes to the LDMOS section10a. An LDMOS gate line31is connected to each of the four LDMOS gate electrodes25a, so as to be electrically connectable to the portions external to the semiconductor device10. The P+regions17bare formed in rectangular shapes at both ends and at a central portion of the LDMOS section10a. Three of the contact lines26bare connected to each of the respective P+regions17b, so as to be electrically connectable to portions external to the semiconductor device10. The rectangular shaped P+region17aand two rectangular shaped N+regions18on either side of the P+region17aare formed in each of the regions interposed between two of the respective LDMOS gate electrodes25a(excluding the central portion of the LDMOS section10a). The P-type body layers19are formed so as to surround the P+region17aand the two N+regions18. Three rectangular shaped contact lines26aare connected to the P+region17aand the two N+regions18, so as to be electrically connectable to portions external to the semiconductor device10. A ring shaped LDMOS channel stopper21ais formed so as to surround the contact lines26a,26b, the LDMOS gate line31and the plural impurity regions (the P+regions17a, the P+region17b, the N+regions18, and the P-type body layers19). In other words, the semiconductor elements configuring the LDMOS section10aare surrounded by the LDMOS channel stopper21a. Charge leakage or the like is stopped in this manner by the shape of the LDMOS channel stopper21asurrounding the semiconductor elements configuring the LDMOS section10a. It should be noted that the LDMOS channel stopper21amay be configured with a portion thereof cut away, as long as there is no charge leakage or the like (i.e. a structure having a non-continuous portion). The LDMOS channel stopper21adoes not make contact with the semiconductor elements configuring the LDMOS section10a.

The rectangular shaped HVMOS gate electrode25bis formed at a central portion of the HVMOS section10b. An HVMOS gate line32is connected to the HVMOS gate line25b, so as to be electrically connectable to the portions external to the semiconductor device10. A fourth N-type high concentration region33(referred to below simply as N+region33) is formed at a position facing the HVMOS gate line25b. A contact line34is also connected to the N+region33, so as to be electrically connectable to the portions external to the semiconductor device10. Two of the P+regions17care also formed at the left and right sides of the HVMOS gate line25b, so that the HVMOS gate line25bis interposed in the middle thereof. A contact line26cis also connected to each of these two P+regions17c, so as to be electrically connectable to the portions external to the semiconductor device10. A ring shaped HVMOS channel stopper21bis formed so as to surround the contact lines26c, the HVMOS gate line32, the contact line34, and the plural impurity regions (the P+region17c, the N+region33, the P-type body layer19). In other words the semiconductor elements configuring the HVMOS section10bare surrounded by the HVMOS channel stopper21b. It should be noted that, also with respect to the HVMOS channel stopper21bconfiguring the HVMOS section10b, in a similar manner to the LDMOS channel stopper21aconfiguring the HVMOS section10a, charge leakage etc. can be prevented by configuration in a shape so as to surround the semiconductor elements configuring the HVMOS section10b. The HVMOS channel stopper21bconfiguring the HVMOS section10btoo may be configured with a portion thereof cut away, as long as there is no charge leakage or the like (i.e. a structure having a non-continuous portion). The HVMOS channel stopper21bdoes not make contact with the semiconductor elements configuring the HVMOS section10b.

As shown inFIG. 4, the LDMOS gate lines31that are connected to each of the four LDMOS gate electrodes25aof the LDMOS section10aare connected to LDMOS gate lead electrode41athat is formed on the inter-layer insulating layer14. The contact lines26bthat are connected to the rectangular shaped P+regions17bformed at the two ends and at a central portion of the LDMOS section10aare connected to LDMOS drain electrodes16aformed on the inter-layer insulating layer14. Further, the contact lines26aconnected to the P+region17aand the two N+regions18on either side of the P+region17aare connected to LDMOS source electrodes15aformed on the inter-layer insulating layer14.

The HVMOS gate line32connected to the HVMOS gate line25bof the HVMOS section10bis connected to an HVMOS gate lead electrode41bformed on the inter-layer insulating layer14. One of the contact lines26cconnected to each of the two P+regions17cformed on either side of the HVMOS gate line25bis connected to the HVMOS source electrode15b, and the other of these contact lines26cis connected to the HVMOS drain electrode16b. Further, the contact line34connected to the N+region33formed in a position facing the HVMOS gate line25bis connected to a back electrode42.

Explanation will now be given of the positional relationship between the N-type buried layer13, the LDMOS channel stopper21a, and the P-type isolation region23, with reference toFIG. 5toFIG. 9. It should be noted that explanation will be omitted of the positional relationship between the HVMOS channel stopper21band the P-type isolation region23since it is similar to that of the explanation below, but with the LDMOS channel stopper21areplaced with the HVMOS channel stopper21b.

FIG. 5is an enlarged diagram of the region5ofFIG. 2(shown by the broken line). As shown inFIG. 5, the N-type buried layer13is separated by a separation distance A from the P-type isolation region23. The LDMOS channel stopper21ais separated by a separation distance B from the P-type isolation region23. The LDMOS channel stopper21ais formed directly below the second field oxide film20bthat is formed above the P-type isolation region23, and is connected thereto, therefore a channel stopper effect is obtained. Note that preferably at least one portion of the LDMOS channel stopper21ashould face toward the N-type buried layer13. As shown inFIG. 5, an outside end portion21A of the LDMOS channel stopper21athat surrounds the impurity regions and semiconductor elements formed on the surface of the N-type epitaxial layer12shown inFIG. 2toFIG. 4, these being the LDMOS gate oxidation film24a, the HVMOS gate line25betc., is within a region that faces an isolation region51between the P-type isolation region23and the N-type buried layer13(namely faces the region of the separation portion of separation distance B from the P-type isolation region23to the N-type buried layer13, or the region not formed with the N-type buried layer13).

FIG. 6is a graph based on test results, showing the change in isolation breakdown voltage of each semiconductor device when the separation distance B (the separation distance from the P-type isolation region23to the LDMOS channel stopper21a) is changed for each of semiconductor devices having different specific resistances of the P-type semiconductor substrate11. The horizontal axis shows the separation distance B (μm: micrometers), and the vertical axis shows the isolation breakdown voltage (V: volts). There are 5 values for the specific resistance of the P-type semiconductor substrate11, 1.5 Ω·cm (Ohm-centimeters), 2.0 Ω·cm, 2.5 Ω·cm, 3.0 Ω·cm, and 15 Ω·cm. The separation distance A (the separation distance from the P-type isolation region23to the N-type buried layer13) is fixed at 5 μm. As shown inFIG. 6, with different specific resistances the isolation breakdown voltage is at the maximum value when the separation distance B is from 1.5 μm to 2.0 μm. The isolation breakdown voltage of the semiconductor device gradually decreases as the separation distance B approaches the separation distance A (namely as the outside end portion21A of the LDMOS channel stopper21agets nearer to the end portion (outside end) of the N-type buried layer13).

FIG. 7is a graph showing the change in isolation breakdown voltage of semiconductor devices when the separation distance B is changed, for two semiconductor devices having different separation distances A. The horizontal axis shows the separation distance B (μm: micrometers), and the vertical axis shows the isolation breakdown voltage (V: volts). There are two values for the separation distance B, 5 μm and 10 μm. The specific resistance of the P-type semiconductor substrate11is 15 Ω·cm. This is done since, as can be seen fromFIG. 6, the change in isolation breakdown voltage becomes more significant the higher the specific resistance.

As can be seen fromFIG. 7, when the separation distance B is zero (separation distance B=0: the LDMOS channel stopper21aand the P-type isolation region are in a state of contact) the isolation breakdown voltage of the semiconductor device is about 45V, independent of the separation distance A. When the separation distance B is greater than 0 (separation distance B>0) (namely when the LDMOS channel stopper21ais separated from the P-type isolation region) the isolation breakdown voltage of the semiconductor device gradually rises. Namely, it is clear that a higher isolation breakdown voltage of the semiconductor device is obtained by not having the LDMOS channel stopper21ain contact with the P-type isolation region23, and instead having a specific separation distance therebetween.

The isolation breakdown voltage of the semiconductor device when the separation distance A is 10 μm has a maximum value (about 100V) when the separation distance B is about 3 to 4 μm. In addition, as explained above, the isolation breakdown voltage of the semiconductor device at a separation distance A of 5 μm has a maximum value (about 70V) when the separation distance B is about 1.5 μm to 2.0 μm. Namely, the isolation breakdown voltage of the semiconductor device is at the maximum value when the separation distance B is at a value within a specific range of the separation distance A (cases where the outer peripheral end portion of the LDMOS channel stopper21ais in a position correspond to a midpoint between the N-type buried layer13and the P-type isolation region23). The separation distance B being a value within a specific range of separation distance A as described above means, for example, setting the separation distance B at a value that is from 20% to 60% of the separation distance A. Preferably the separation distance B is set at a value that is from 30% to 40% of the separation distance A.

When the value of separation distance B is greater than the separation distance A (when the LDMOS channel stopper21ais more separated from the P-type isolation region23than the N-type buried layer13is separated from the P-type isolation region23) then change in the isolation breakdown voltage of the semiconductor device substantially disappears. This means that an increase in the isolation breakdown voltage of the semiconductor device can be achieved by setting the position of the outside end portion21A of the LDMOS channel stopper21aso as to be in a range that at least corresponds to a position between the P-type isolation region23and the N-type buried layer13.

FIG. 8AtoFIG. 8Care schematic diagrams showing equivalent electrical potential lines of state of an electrical field in the semiconductor device10where the separation distance B is changed and the separation distance A is at 5 μm.FIG. 9AtoFIG. 9Care schematic diagrams showing equivalent electrical potential lines of state of an electrical field in the semiconductor device10where the separation distance B is changed and the separation distance A is at 10 μm.FIG. 8AtoFIG. 8Care schematic diagrams for state where separation distance B is 0 μm (FIG. 8A), 2 μm (FIG. 8B), and 5 μm (FIG. 8C).FIG. 9AtoFIG. 9Care schematic diagrams for state where separation distance B is 0 μm (FIG. 9A), 4 μm (FIG. 9B), and 10 μm (FIG. 9C).

As can be seen fromFIGS. 8A to 8CandFIGS. 9A to 9C, when the separation distance B=0 (namely when the LDMOS channel stopper21ais in a state of contact with the P-type isolation region23), the equivalent electrical potential lines are densely packed in the vicinity of the interface of the P-type isolation region and the LDMOS channel stopper21a, and so a concentrated electrical field is generated. When the separation distance B is equivalent to the separation distance A (namely the position of the outside end portion21A of the LDMOS channel stopper21aand the position of the end portion of the N-type buried layer13are equivalent in the thickness direction of the semiconductor device10), electrical field concentration is generated in the vicinity of the N-type buried layer13. In addition, as shown inFIG. 8BandFIG. 9B, when the separation distance B is a value that is about 40% of the separation distance A, there is no electrical field concentration generated. A high isolation breakdown voltage like that shown inFIG. 7cannot be obtained when electrical field concentration is generated as described above. In contrast, when the electrical potential distribution within the semiconductor device10is uniform, then a high isolation breakdown voltage is obtained. Therefore, it can be seen that a high isolation breakdown voltage in the semiconductor device can be obtained by adjusting the position for forming the LDMOS channel stopper21a, making the electrical potential distribution within the semiconductor device10uniform.

In order to raise the isolation breakdown voltage in the semiconductor device10the necessity arises from the above to form the LDMOS channel stopper21asuch that the outside end portion21A of the LDMOS channel stopper21ais positioned so as to be more to the outside than the outer peripheral end of the N-type buried layer13. There is also a necessity to form the LDMOS channel stopper21aso as not to make contact with the P-type isolation region23. In other words, the outside end portion21A of the LDMOS channel stopper21aneeds to be within a region facing the isolation region51between the P-type isolation region23and the N-type buried layer13(directly below the second field oxide film20b, positioned so as to be aligned with a non-continuous portion, where the N-type buried layer13of the P-type semiconductor substrate11is not formed). In order to achieve an even higher breakdown voltage of the semiconductor device10, the LDMOS channel stopper21ais preferably formed such that the outside end portion21A of the LDMOS channel stopper21ais positioned aligned with a central portion of the isolation region51between the P-type isolation region23and the N-type buried layer13. With regard to specific numerical values for the position aligned with a central portion of the isolation region51, it can be seen from the above results that the separation distance from the P-type isolation region23to the LDMOS channel stopper21ashould preferably be 20% to 60% of the separation distance from the P-type isolation region23to the N-type buried layer13. The separation distance from the P-type isolation region23to the LDMOS channel stopper21ashould more preferably be 30% to 40% of the separation distance from the P-type isolation region23to the N-type buried layer13.

Explanation will now be given of a fabrication method for the semiconductor device according to an exemplary embodiment, with reference toFIG. 10AtoFIG. 13D.

First, the P-type semiconductor substrate11is prepared (FIG. 10A). The specific resistance of the P-type semiconductor substrate11may, for example, be 3 Ω·cm. A silicon oxide film101is formed by a thermal oxidation method on the prepared P-type semiconductor substrate11(FIG. 10B). The film thickness of the silicon oxide film101may, for example, be 20 nm. After forming the silicon oxide film101, a resist is applied to the silicon oxide film101. This resist is then patterned by lithography. Arsenic ions are then implanted in the broken-line region102(FIG. 10B) of the P-type semiconductor substrate11while using the patterned resist as a mask. As shown inFIG. 10B, the regions in which the arsenic ions are implanted are formed at specific intervals (namely, include non-continuous portions). This is done in order that the P-type isolation region23can be formed afterwards in the regions that are not implanted with the arsenic ions (on the P-type semiconductor substrate11). The above specific interval needs to be set so as to be separated by a specific separation distance from the P-type isolation region23to be formed later. The implantation amount of the arsenic ions may be 1×1015cm−2. This resist is then removed, and boron ions are then implanted into the whole of the surface of the P-type semiconductor substrate11. The implantation amount of the boron ions may be 2×1012cm−2. The P-type semiconductor substrate11with boron ions implanted into the surface thereof is then subjected to thermal processing at about 950° C. The arsenic ions implanted regions in the P-type semiconductor substrate11are activated by this processing, forming the N-type buried layer13in these regions implanted with arsenic ions (FIG. 10C).

Next, the silicon oxide film101formed by the above thermal oxidation method is removed. An N-type epitaxial layer12is then formed using an epitaxial growth method on the surface of the P-type semiconductor substrate11from which the silicon oxide film101has been removed (FIG. 10D). The P-type semiconductor substrate11may, for example, be subjected to thermal processing at 1150° C. in a monosilane gas and hydrogen gas atmosphere. The thickness of the N-type epitaxial layer12may be about 3 μm.

A silicon oxide film103is then formed using a thermal oxidation method on the N-type epitaxial layer12. This is followed by forming a silicon nitride film104on the silicon oxide film103using a CVD (Chemical Vapor Deposition) method. The film thickness of the silicon oxide film103may, for example, be 25 nm and the film thickness of the silicon nitride film104may be 200 nm. Resist is then applied to the silicon nitride film104. This resist is then patterned by lithography. The silicon oxide film103and the silicon nitride film104are then subjected to etching using this patterned resist as a mask. Plural through holes105are formed penetrating through the silicon oxide film103and the silicon nitride film104by this etching, exposing portions of the N-type epitaxial layer12(FIG. 10E).

A resist111is then coated so as to fill the through holes105. The resist111is then patterned using a lithography (FIG. 11A). Phosphorous ions are then implanted into the broken-line regions112in the N-type epitaxial layer12using the resist111as a mask (FIG. 11A). The ion implanted broken-line regions112are set so as to be positioned separated from the P-type isolation region23that will be formed later. The phosphorous ion implantation amount may be 5×1012cm−2. It should be noted that the phosphorous ion implantation is ion implantation at low energy, such that ion implantation is performed with the phosphorous ion implanted region (broken-line regions112) not reaching the N-type buried layer13. It should be noted that the ion implantation of the phosphorous ions is performed so as to give rise to ring shaped ion implantation regions, like the LDMOS channel stopper21aand HVMOS channel stopper21bshown inFIG. 3. This is undertaken such that the regions for phosphorous ion implantation (broken-line regions112) become the LDMOS channel stopper21aand the HVMOS channel stopper21bby thermal processing as described later. The regions in which phosphorous ions are ion implanted (the broken-line regions112) are provided positioned such that at least a portion faces the N-type buried layer13.

The resist111is then removed, and the surface of the N-type epitaxial layer12exposed by the through holes105is subjected to thermal oxidation processing at 950° C. First to third field oxide films20ato20care formed by this thermal processing on the exposed surface of the N-type epitaxial layer12. The phosphorous ion implanted regions are activate by this thermal processing, forming the LDMOS channel stopper21aand HVMOS channel stopper21b. The silicon oxide film103and the silicon nitride film104are then removed (FIG. 11B). It should be noted that as well as using a LCOS method (Local Oxidation of Silicon) as described above, as the method for forming the first to third field oxide films20ato20c, a STI (Shallow Trench Isolation) method may also be used for forming an oxidized film for segregating.

Next, a sacrificial oxidized film (not illustrated) is formed to the N-type epitaxial layer12and the first to third field oxide films20ato20cusing a thermal oxidation method. The film thickness of the sacrificial oxidized film may, for example, be 20 nm. Resist is coated on this sacrificial oxidized film. The resist is then patterned using lithography. Boron ions are then implanted to the broken-line regions113in the N-type epitaxial layer12using this patterned resist as a mask (FIG. 11C). The regions implanted with boron ions (broken-line regions113) are made such that the interface of the second field oxide film20band the N-type epitaxial layer12reaches to the interface of the P-type semiconductor substrate11and the N-type epitaxial layer12(portion where N-type buried layer13is separated). The regions implanted with boron ions (broken-line regions113) do not make contact with the LDMOS channel stopper21aand the HVMOS channel stopper21b, and are formed at specific intervals.

Next, the above resist is removed, and a new resist is applied to the sacrificial oxidized film. Patterning is then made of this resist using lithography. Then boron ions are implanted to the broken-line regions114in the N-type epitaxial layer12using this patterned resist as a mask (FIG. 11D). It should be noted that the regions implanted with boron ions (broken-line regions114) are preferably formed so as not to make contact with the HVMOS channel stopper21b. This is because if the broken-line regions114and the HVMOS channel stopper21bmake contact the breakdown voltage of the semiconductor device10is decreased.

This resist and the sacrificial oxidized film are next removed. The LDMOS gate oxidation film24aand the HVMOS gate oxidation film24bare then formed on the N-type epitaxial layer12, the first field oxide film20aand the third field oxide film20cusing a thermal oxidation method. Poly-crystalline silicon is then deposited on the LDMOS gate oxidation film24aand the HVMOS gate oxidation film24busing a CVD method. Resist is applied onto the deposited poly-crystalline silicon. This resist is then patterned using lithography. The LDMOS gate oxidation film24a, the HVMOS gate oxidation film24band the poly-crystalline silicon are then subjected to etching using this patterned resist as a mask. The LDMOS gate oxidation film24a, HVMOS gate oxidation film24b, the LDMOS gate electrode25aand the HVMOS gate line25bare formed by this etching only in specific locations (FIG. 12A).

A resist is then applied onto the N-type epitaxial layer12, the first to third field oxide films20ato20c, the LDMOS gate electrode25a, and the HVMOS gate line25b. The resist is then patterned using lithography. Boron ions are implanted into a broken-line region121in the N-type epitaxial layer12(FIG. 12B) using this patterned resist as a mask.

The N-type epitaxial layer12, formed with the LDMOS gate electrode25a, the HVMOS gate line25band plural impurity regions as above, is then subjected to thermal processing at about 1050° C. The impurities of the above ion implanted regions (the broken-line regions113,114, and121) are diffused and activated by this thermal processing, and the P-type body layer19, the P-type drift layer22, and the P-type isolation region23are formed in the N-type epitaxial layer12(FIG. 12C).

Resist is then applied to the N-type epitaxial layer12, the first to third field oxide films20ato20c, the LDMOS gate electrode25aand the HVMOS gate line25b. This resist is then patterned using lithography. Boron ions are implanted into the broken-line regions122in the N-type epitaxial layer12, into the P-type body layer19, the P-type drift layer22(FIG. 12D) using this patterned resist as a mask. The above resist is then removed, and new resist is applied to the N-type epitaxial layer12, the first to third field oxide films20ato20c, the LDMOS gate electrode25a, and the HVMOS gate line25b. This resist is then patterned using lithography. Arsenic ions are implanted into a broken-line region123in the P-type body layer19using this patterned resist as a mask (FIG. 12D).

The N-type epitaxial layer12formed with plural impurity regions is then subjected to thermal processing at about 950° C. The impurities of the above ion implanted regions (the broken-line regions122,123) are diffused and activated by this thermal processing, forming the first to third high concentration P-type regions17ato17c(referred to below simply as P+regions17ato17c) and the first N-type high concentration region18(referred to below simply as N+region18) in the N-type epitaxial layer12, the P-type body layer19, and the P-type drift layer22(FIG. 13A).

The inter-layer insulating layer14is then formed by a CVD method on the N-type epitaxial layer12, the first to third field oxide films20ato20c, the LDMOS gate electrode25a, and the HVMOS gate line25b. The formed inter-layer insulating layer14is then subjected to polishing using a CMP (Chemical Mechanical Polishing) method. The inter-layer insulating layer14is flattened by this polishing (FIG. 13B).

Resist is then applied to the inter-layer insulating layer14. This resist is then patterned using lithography. The inter-layer insulating layer14is subjected to etching using this patterned resist as a mask. Contact holes are formed by this etching so as to reach the P+regions17ato17cand the N+region18in the inter-layer insulating layer14. Tungsten is also filled into these contact holes using a CVD method with titanium nitride as an undercoat. Contact lines22ato22care formed in the inter-layer insulating layer14by this tungsten filling (FIG. 13C).

A metal wiring layer is formed from tungsten and aluminum on the inter-layer insulating layer14and the contact lines26ato26cusing a sputtering method. Resist is coated on this metal wiring layer. This resist is then patterned using lithography. The metal wiring layer is then subjected to etching using this patterned resist as a mask. The LDMOS source electrode15a, the HVMOS source electrode15b, the LDMOS drain electrode16a, and the HVMOS drain electrode16bare formed by this etching (FIG. 13D). It should be noted that, while not shown inFIG. 13D, the LDMOS gate lead electrode41a, the HVMOS gate lead electrode41b, and the back electrode42are also formed at the same time as forming the above drain electrodes and source electrodes. By the above processes, fabrication processes are completed of the semiconductor device10that includes the LDMOS section10aand the HVMOS section10b.

As described above, the semiconductor device according to the present invention, as well as burying a channel stopper in the surface of an N-type epitaxial layer formed on a P-type semiconductor substrate, also has the channel stopper surrounding the semiconductor elements formed on the surface of the N-type epitaxial layer and being separated from the P-type element-isolation regions for segregating these semiconductor elements. The isolation breakdown voltage of the semiconductor device can thereby be increased to a high breakdown voltage.

It should be noted that the P-type and N-type of the semiconductor device10of the exemplary embodiment may be swapped over. Also, though the N-type epitaxial layer12was formed on the P-type semiconductor substrate11, an N-type region may be formed by ion implantation on the P-type semiconductor substrate11in place of the N-type epitaxial layer12.

In the above exemplary embodiment the semiconductor device10is configured with an LDMOS section10aand an HVMOS section10b, however configuration may be made with either one of these sections alone. In addition, in place of the LDMOS section10aor the HVMOS section10b, a CMOS structure may be adopted, and such a CMOS structure surrounded by a channel stopper.

—Exemplary Modification of the Present Invention—

The semiconductor device of the present invention may be a semiconductor device with bi-polar transistors instead of a MOS structure. Explanation will be given of a case with such bi-polar transistors, with reference toFIG. 14toFIG. 16.

FIG. 14is a cross-section of a portion of a semiconductor device300(a cross-section taken on line400-400inFIG. 15andFIG. 16). As shown inFIG. 14, the semiconductor device300is segregated by a P-type element-isolation region, described later, into an LDMOS section300aformed from a lateral diffusion MOS transistor (LDMOS: Lateral Diffusion Metal-Oxide-Semiconductor) and an NPN bi-polar transistor section300b. The LDMOS section300ais formed with the same composition as the LDMOS section10adescribed above, and so the same reference numerals are allocated thereto and explanation thereof is omitted.

As shown inFIG. 14, the NPN bi-polar transistor section300bof the semiconductor device300is configured with: a P-type semiconductor substrate11; an N-type epitaxial layer12formed above the P-type semiconductor substrate11; an N-type buried layer13formed at the interface of the P-type semiconductor substrate11and the N-type epitaxial layer12; a inter-layer insulating layer14formed above the N-type epitaxial layer12; and a collector electrode301, a base electrode302, and an emitter electrode303formed on the inter-layer insulating layer14.

A fourth high concentration P-type region17d(referred to below simply as P+region17d), a fourth N-type high concentration region304(referred to below simply as N+region304), a fourth field oxide film20d, a bi-polar channel stopper305which is fifth N-type high concentration regions, a P-type base region306and an N-type lifting layer307which is a sixth N-type high concentration region, are formed on the surface of the N-type epitaxial layer12of the NPN bi-polar transistor section300b.

Contact lines308are formed for electrically connecting the P+region17dand the N+region304in the inter-layer insulating layer14of the NPN bi-polar transistor section300b. Each of the contact lines308is connected to one or other of the collector electrode301, the base electrode302or the emitter electrode303.

Explanation will now be given of the structure in plan view of the semiconductor device300, with reference toFIG. 15andFIG. 16.FIG. 15is a diagram showing the layout of each of the impurity regions and each of the contact lines in the semiconductor device300, represented in plan view.FIG. 16is a diagram showing in plan view each of the types of electrode formed on the surface of the semiconductor device300and each of the contact lines contacted thereto.

As shown inFIG. 15, the rectangular shaped P+region17dis formed at a central portion of the NPN bi-polar transistor section300b. The contact lines308are connected to the P+region17d, so as to be electrically connectable to the portions external to the semiconductor device300. Two of the rectangular shaped N+regions304are formed to the NPN bi-polar transistor section300b, so that the P+region17dis interposed therebetween. Contact lines308are connected to each of these two N+regions304, so as to be electrically connectable to the portions external to the semiconductor device300. The P-type base region306is formed so as to surround the P+region17dand one of the N+regions304. The N-type lifting layer307is formed in a ring shape so as to surround the P-type base region306. The bi-polar channel stopper305is also formed in a ring shape so as to surround the N-type lifting layer307. Charge leakage and the like does not occur due to the above shape of the bi-polar channel stopper305. The bi-polar channel stopper305may be configured with a portion thereof cut away as long as there is no charge leakage or the like (i.e. a structure having a non-continuous portion).

As shown inFIG. 15andFIG. 16, the contact line308that is connected to the P+region17dof the NPN bi-polar transistor section300bis connected to the base electrode302formed above the inter-layer insulating layer14. One of the contact lines308connected to the N+regions304of the NPN bi-polar transistor section300bis connected to the collector electrode301formed above the inter-layer insulating layer14, and another is connected to the emitter electrode303.

The above semiconductor device300with the NPN bi-polar transistor section300balso is provided with the bi-polar channel stopper305separated by a specific separation distance from the P-type isolation region23. A high isolation breakdown voltage is thereby obtained.

EXPLANATION OF THE REFERENCE NUMERALS