Binary phase shift keying modulation system and/or frequency multiplier

A low cost spread spectrum modulator for BPSK, or Binary Phase Shift Keying capable of outputting the high modulation rate and suppressed carrier output needed in spread spectrum systems. The present invention provides high quality BPSK modulation without the double balance mixers as required in the prior art, thereby dispensing with the necessity of complex transistor/potonciometer or diode/transformer arrangements. The present invention provides BPSK modulation utilizing only one transformer, which can be adjusted for carrier suppression and two transistors, FET's, or digital logic gates or the like, allowing the present system to be driven from low power CMOS logic levels, yet producing eight db of gain. The present invention may also be utilized as a frequency multiplier, with the utilization of the appropriately high frequency transistor, FET, digital logic gate, or the like.

BACKGROUND OF INVENTION 
1. Field of Invention 
The present invention relates to modulators, and more particularly to an 
improved spread spectrum BPSK, or Binary Phase Shift Keying, Modulation 
system designed for providing gain, low cost and suppressed carrier 
output, as well as compatibility with CMOS low power logic modulation 
drive circuitry. The present invention also teaches a Frequency Multiplier 
circuit, which is much less costly than traditional designs currently 
known. 
The present system teaches a new, superior, and less costly BPSK modulator 
and/or frequency multiplier than that contemplated by the prior art, 
providing a less complicated system while outputting increased gain over 
prior art modulators. 
2. Prior Art & General Background 
Previous spread spectrum BPSK modulators required conventional balance 
mixers to produce carrier suppression. These conventional modulators 
utilized either 1) a complex transistor array in conjunction with a 
transformer tunable with a potonciometer or 2) two center tapped 
transformers and four diodes, which arrangement required a high level 
drive circuit to modulate it, typically +7 to +15 dBM. 
Besides the greater expense, increased complexity thereby contributing the 
probability of failure, and incompatibility with low power -10 dB CMOS 
logic drive circuitry, the prior art modulators typically produced on the 
order of six dB of signal loss, resulting in considerably less 
satisfactory overall performance when compared to the present invention. 
3. General, Summary Discussion of the Invention 
A low cost spread spectrum modulator is an essential component of a 
commercially viable spread spectrum communications system. While a low 
cost, high performance modulator has not been contemplated until now, the 
present invention describes the ideal modulator, designed specifically for 
Binary Phase Shift Keying or BPSK. 
The present invention is designed to provide a low cost, efficient, quality 
and reliable modulation system having sufficiently high BPSK modulation 
rate, coupled with the suppressed carrier output needed in spread spectrum 
communication systems and the like. 
Unlike the prior art, which required balance mixers of the sort discussed 
in the background section supra, the present invention provides a BPSK 
modulator utilizing only one transformer having the capability of 
adjusting for maximum carrier suppression, in conjunction with two bipolar 
transistors, which allows the modulator to be driven from the low power 
logic levels found in CMOS circuitry -10 dBM. The present invention in its 
preferred embodiment produces eight dB of gain, much superior in 
performance over the prior art, which performs at a six dB signal loss. 
Further, the present invention is not limited to utilizing two bipolar 
transistors as discussed supra and may utilize in an equivalent fashion 
any device which provides sufficient gain at the desired frequency or 
operation, as well as having sufficiently fast switching capabilities. 
For example, other acceptable, equivalent devices which may be utilized in 
place of the two transistors in the present invention may include high 
frequency field effect transistors (FET's), or digital logic gates, which 
are biased into a linear region utilizing common techniques. These devices 
may be incorporated into the system of the present invention, replacing in 
effect the transistors, utilizing common engineering techniques. 
The present invention, in an alternative use, may be utilized as a 
frequency multiplier. For example, if the transistor, or its equivalent, 
is adequately fast, for example, F.sub.t &gt;1 GHZ, the system may be 
utilized to create at its output a higher frequency harmonic. 
As is known in the art, it is a common radio design practice to utilize a 
non-linear device such as a diode, transistor, or the like to perform 
frequency multiplication. This is desirable because only lower frequency 
crystals are readily available, and as such, the lower frequency must then 
be translated into the higher, desired frequency. 
When the modulation transistor arrangement is additionally utilized in the 
present invention in the frequency modulation capacity, less subsequent 
stages are required. This serves to lower both the cost and complexity of 
a frequency multiplier system, when compared to the prior art systems. 
It is thus an object of the present invention to provide a low cost, high 
quality BPSK modulator compatible for use in spread spectrum-type 
communications systems. 
It is another object of the present invention to provide a BPSK modulation 
system which is compatible with low power logic input, such as that driven 
by CMOS circuitry. 
It is still another object of the present invention to provide a BPSK 
modulator which utilizes a single transformer and two transistors, adjusts 
for carrier suppression, and provides eight db+ of gain.

DESCRIPTION OF THE PREFERRED EXEMPLARY EMBODIMENT(S) 
The described modulator uses only one transformer which also adjusts for 
carrier suppression and two transistors, and as such can be driven from 
low power CMOS logic levels producing a full eight dB of gain. 
BPSK modulation seeks to alternate a carrier between a 0 degree phase shift 
and a 180 degree phase shift, the phase shift of the carrier providing the 
modulation. As illustrated in FIG. 1 of the present invention, the outputs 
of the transformer "A", when the center tap "B" is grounded, are 
inherently at opposite phases, 0 degrees and 180 degrees. 
Transistor C and D can then be alternately selected by biasing the MOD + or 
MOD - inputs to on. Thus, either the 0 degree phase shift or 180 degree 
phase shift can be selected, which provides BPSK modulation with 8 dB of 
gain. 
An alternative embodiment to the present invention obviates with the need 
for the costly center tap in the transformer, further simplifying the 
present design. This circuit is based upon the premise that an inductor at 
resonance has outputs 180 degrees out of phase, producing 0 and 180 
degrees outputs. The 0 degree and 180 degree outputs are selected using 
the same MOD -, MOD + biasing as described above. 
Through extensive experimentation, the present inventor has determined that 
either tight (&gt;0.6 coupling coefficient) or loose (&lt;0.3 coupling 
coefficient) coupling of the transformer windings can be used to produce 
suitable 0 degree and 180 degree phase shifts for BPSK modulation. 
As illustrated in FIG. 2, in the embodiment implementing the loosely 
coupled transformer, both capacitors G and F must be configured to 
resonate in conjunction with the carrier frequency to be modulated. The 
resonate point in this circuit may be fine adjusted by varying the 
transformer's inductance, by turning the tunable core or slug of 
transformer E. 
In a tightly coupled transformer, capacitor G can be eliminated and 
transformer E must be only resonate with capacitor F. Fine tuning is again 
achieved by adjusting the slug or core of transformer E. The value of 
capacitor F must be such that it resonates with transformer E at the 
frequency to be modulated. 
Both embodiments of the invention perform identically when properly 
configured and can produce excellent BPSK spread spectrum modulation with 
adjustable carrier suppression. 
As discussed above, the value of the resonate capacitors to be frequency. 
In the present invention, if a 11/2 primary turn to 2 1/2 secondary turn 
transformer is used with a carrier frequency of 300 MHz, then practical 
resonate capacitor values are 2.2 to 6.8 pf for G & E. The series coupling 
capacitors must be relatively small to minimize coupling of transistor 
base to collector capacitance. Practical values are from 2.2 to 8.2 pf. 
The transformer turns ratio is selected to match the impedance of the 
driving carrier CKT to the input impedance of the gain/phase selection 
transistors. 
Since FIG. 2 must be in resonance to function, the overall Q of the CKT and 
transformer coupling can be chosen to optimize performance as a tuned 
filter. Q is primarily effected by the transformer slug loss. Further 
loosely coupled transformers provide optimum filtering characteristics. 
This function can filter out undesirable harmonics from previous RF 
stages, eliminating otherwise required additional filter components. 
The overall 8 dB of gain realized is a product of sums of both gain and 
losses of the entire circuit. The transformer produces 2 to 4 dB of loss, 
the coupling capacitors produce 1 dB of loss, the transistors provide 12 
to 13 dB of gain. The average circuit gain is determined as the minimum 
overall gain (12-4-1)=7 dB to a maximum overall gain of (13-2-1)=10 dB of 
gain. 
As discussed infra, the present invention's design is not limited to use in 
BPSK modulation. The present invention, in an alternative use, may be 
utilized as a frequency multiplier. 
For example, if the transistor(s), or their equivalents, as utilized in the 
present invention, is adequately fast, for example, F.sub.t &gt;1 GHZ, the 
system may be utilized to create at its output a higher frequency 
harmonic. The circuit layout, and implementation of this alternative 
embodiment would remain substantively the same as set forth in the figures 
shown. 
As is known in the art, it is a common radio design practice to utilize a 
non-linear device such as a diode, transistor, or the like to perform 
frequency multiplication. This is desirable because only lower frequency 
crystals are readily available, and as such, the lower frequency must then 
be translated into the higher, desired frequency. 
When the modulation transistor arrangement is additionally utilized in the 
present invention in the frequency modulation capacity, less subsequent 
stages are required. This serves to lower both the cost and complexity of 
a frequency multiplier system, when compared to the prior art systems. 
The embodiment(s) described herein in detail for exemplary purposes are of 
course subject to many different variations in structure, design, 
application and methodology. Because many varying and different 
embodiments may be made within the scope of the inventive concept(s) 
herein taught, and because many modifications may be made in the 
embodiment(s) herein detailed in accordance with the descriptive 
requirements of the law, it is to be understood that the details herein 
are to be interpreted as illustrative and not in a limiting sense. 
As a further example, other acceptable, equivalent devices may be utilized 
in place of the two transistors in the present invention. These may 
include high frequency field effect transistors (FET's), or digital logic 
gates, which are biased into a linear region utilizing common techniques. 
These devices may be incorporated into the system of the present 
invention, replacing in effect the transistors, utilizing common 
engineering techniques. 
For example, the topological dual of the described circuits is also 
practicable, having the gain or frequency multiplication precede the phase 
shifting transformer. In an alternate embodiment of the present invention, 
as shown in FIG. 3, a frequency f.sub.IN is introduced at 501, so that the 
frequency f.sub.IN is AC coupled and present on both transistors 502 and 
503. BPSK data is generated in complement via inverter 508, thereby 
selecting, via base bias resistors, transistors 502 or 503. The collectors 
are connected via the opposite center tapped primary windings of 
transformer 506. The center tap provides DC power and AC bypass. The 
selection of transistor 502 or 503 thereby forces a 0.degree. or 
180.degree. phase relationship on f.sub.OUT 509. Capacitors 504, 505, and 
507 can be used to effect single or double pole filtering depending on the 
coupling of transformer 506. Frequency multiplication can also be achieved 
with transistors 502 and 503 by adjusting bias and drive levels for 
nonlinear output, as well as tuning transformer 506 to the target 
harmonic. 
An additional alternate embodiment of the present invention, illustrated in 
FIG. 4, has very high speed logic gates 403, 405 biased into a linear 
region and replacing transistors 502, 503 of FIG. 3. As shown in FIG. 4, a 
frequency is introduced via f.sub.IN in 401. Bias network means, embodied 
as a DC bias device 402, is used to force logic elements 403, 405 into a 
linear region of operation. Either AND gates or OR gates can be made to 
function in this circuit. The inverter 404 provides complementary BPSK 
data thereby selecting either gate 403 or gate 405. The outputs then drive 
the primary of a transformer 407 causing either a 0.degree. or a 
180.degree. phase shift on the output of the transformer 407 at f.sub.OUT 
409. In addition, the transformer 407 can be used as a one or two pole 
filter in conjunction with capacitors 406, 408, depending on the coupling 
coefficient of the transformer 407. 
Furthermore, gates 403, 405 can be used as frequency multipliers by 
adjusting the DC offset and drive levels on the inputs of gates 403, 405, 
and tuning transformer 407 to the desired harmonic output.