Signal processing system and self-calibration digital-to-analog converting method thereof

A signal processing system including a DAC, a comparing unit, and a control unit is provided. The DAC receives a digital input and generates an output voltage. The comparing unit receives the output voltage and compares the output voltage with a reference voltage to output an output value. The control unit receives the output value and accordingly generates the digital input in a manner of value mapping through firmware or software to calibrate the DAC. Furthermore, a self-calibration digital-to-analog converting method is also provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 100117787, filed May 20, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a signal processing system and a digital-to-analog converting method thereof. Particularly, the invention relates to a signal processing system having a self-calibration mechanism and a digital-to-analog converting method thereof.

2. Description of Related Art

Digital-to-analog converters (DACs) are widely used in digital circuits, for example, a video DAC and a TVDAC, etc. The conventional DAC generally has an external resistor, and a function thereof is to serve as a reference resistance when an internal reference current of the DAC is output. However, although the design of connecting the external resistor to the DAC can reduce an influence of fabrication process variation, such design still has a chance to cause yield loss due to fabrication process variation.

SUMMARY OF THE INVENTION

The invention is directed to a signal processing system, in which a digital-to-analog converter (DAC) has a self-calibration mechanism, so as to avoid an influence of a fabrication process variation to increase a production yield.

The invention is directed to a self-calibration digital-to-analog converting method adapted to a DAC inbuilt with a reference resistor, by which the DAC may have a self-calibration mechanism to avoid an influence of a fabrication process variation, so as to increase a production yield.

The invention provides a signal processing system including a DAC, a comparing unit, and a control unit. The DAC receives a digital input and generates a first output voltage. The comparing unit receives the first output voltage and compares the first output voltage with a first reference voltage to output an output value. The control unit receives the output value and accordingly generates the digital input in a manner of value mapping through firmware or software to calibrate the DAC.

In an embodiment of the invention, the DAC includes a reference resistor. The control unit selects to increase or decrease a resistance of the reference resistor according to the output value, so as to calibrate the DAC.

In an embodiment of the invention, the DAC includes a reference current source and a current source array. The control unit selects to increase or decrease a mirror ratio of the reference current source and the current source array according to the output value, so as to calibrate the DAC.

In an embodiment of the invention, the DAC receives a second reference voltage. The control unit selects to increase or decrease the second reference voltage according to the output value, so as to calibrate the DAC.

In an embodiment of the invention, the signal processing system further includes a test compensation unit. The test compensation unit outputs a testing signal to the DAC, and the DAC generates a second output voltage. The test compensation unit determines whether the second output voltage is matched to the testing signal.

In an embodiment of the invention, the DAC includes a compensation current source adapted to provide a compensation current. The test compensation unit selects to increase or decrease the compensation current according to a determination result thereof.

In an embodiment of the invention, the control unit includes a look-up table. When the digital input is generated in the manner of value mapping, the control unit looks up the digital input corresponding to the output value from the look-up table, so as to calibrate the DAC.

The invention provides a self-calibration digital-to-analog converting method adapted to a DAC. The self-calibration digital-to-analog converting method includes following steps. A digital input is received to generate a first output voltage. The first output voltage is received, and the first output voltage is compared with a first reference voltage to generate an output value. The output value is received, and the digital input is generated in a manner of value mapping through firmware or software to calibrate the DAC.

In an embodiment of the invention, the DAC includes a reference resistor. The step of calibrating the DAC comprises selecting to increase or decrease a resistance of the reference resistor according to the output value, so as to calibrate the DAC.

In an embodiment of the invention, the DAC includes a reference current source and a current source array. The step of calibrating the DAC comprises selecting to increase or decrease a mirror ratio of the reference current source and the current source array according to the output value, so as to calibrate the DAC.

In an embodiment of the invention, the DAC receives a second reference voltage. The step of calibrating the DAC comprises selecting to increase or decrease the second reference voltage according to the output value, so as to calibrate the DAC.

In an embodiment of the invention, the self-calibration digital-to-analog converting method further includes following steps. A testing signal is input to the DAC, and the DAC generates a second output voltage. It is determined whether the second output voltage is matched to the testing signal.

In an embodiment of the invention, the DAC includes a compensation current source adapted to provide a compensation current. The self-calibration digital-to-analog converting method further includes selecting to increase or decrease the compensation current according to a determination result.

In an embodiment of the invention, the step of generating the digital input in the manner of value mapping through firmware or software comprises looking up the digital input corresponding to the output value from a look-up table, so as to calibrate the DAC.

According to the above descriptions, in the embodiment of the invention, the DAC is inbuilt with a reference resistor, and applies the aforementioned digital-to-analog converting method to achieve a self-calibration mechanism, so as to avoid an influence of a fabrication process variation to increase a production yield.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

If a reference resistor externally connected to a digital-to-analog converter (DAC) according to a conventional technique is built in the DAC, the inbuilt reference resistor may have different resistances due to influence of a fabrication process variation, so that a level of an operating voltage output by the DAC is shifted, which may decrease a chip yield as an operation range is changed.

Accordingly, in an embodiment of the invention, according to a self-calibration digital-to-analog converting method, a feedback comparison is performed on the output voltage of the DAC, and by adjusting a resistance of a reference resistor, adjusting a mirror ratio of a reference current source and a current source array, adjusting a reference voltage or adjusting a compensation current, influence of the fabrication process variation is reduced so as to improve the chip yield and achieve a low cost and high performance circuit design.

FIG. 1is a functional block diagram of a signal processing system according to an embodiment of the invention. Referring toFIG. 1, in the present embodiment, the signal processing system100includes a DAC110, a comparing unit120, a control unit130and a test compensation unit140. The DAC110receives a digital input SINand generates a first output voltage VOUT1. The comparing unit120receives the first output voltage VOUT1and compares the first output voltage VOUT1with a first reference voltage VREF1to generate an output value SD. The control unit130receives the output value SDand accordingly generates the digital input SINin a manner of value mapping through firmware or software to calibrate the DAC110. Here, the signal processing system100, for example, processes a video image signal.

In detail,FIG. 2is a circuit schematic diagram of the DAC ofFIG. 1. Referring toFIG. 2, in the present embodiment, the DAC110includes an operation amplifier OP, a current source array112, a reference resistor RADJ, a reference current source IREF, an output resistor ROUTand a compensation current source ICPS.

In the present embodiment, the DAC110is coupled to the comparing unit120and outputs the first output voltage VOUT1to the comparing unit120, and the comparing unit120compares the first output voltage VOUT1with the specific first reference voltage VREF1. For example, the comparing unit120is, for example, an analog-to-digital converter (ADC) or a comparator. If the comparing unit120is implemented by a comparator, the comparator receives the first output voltage VOUT1and the first reference voltage VREF1for comparison to obtain a level of the first output voltage VOUT1, as that shown inFIG. 1. If the comparing unit120is implemented by an ADC, the ADC converts the first output voltage VOUT1into a digital signal to represent the level of the first output voltage VOUT1. In other words, now the comparing unit120is unnecessary to additionally receive the first reference voltage VREF1.

Then, the signal processing system100adjusts a resistance of the reference resistor RADJ, adjusts a second reference voltage VREF2or adjusts a mirror ratio of the reference current source IREFand the current source array112through the control unit130for calibration. Alternatively, the signal processing system100can also adjust the compensation current ICPSthrough the test compensation unit140to compensate an offset of the first output voltage VOUT1caused by differential non-linearity (DNL).

Further, after the first output voltage VOUT1is output to the ADC or the comparator, a comparison result thereof is transmitted to the control unit130. Then, the control unit130determines how to adjust the DAC110through firmware or software according to a predetermined condition. For example, the control unit130can select to adjust the reference resistor RADJ, adjust the second reference voltage VREF2or adjust the mirror ratio of the reference current source IREFand the current source array112through a voltage current source conversion loop. The voltage current source conversion loop may include the operation amplifier OP, the reference resistor RADJand the reference current source IREF.

In detail,FIG. 3is a flowchart illustrating a method that a control unit adjusts a resistance of a reference resistor according to an embodiment of the invention. Referring toFIG. 1toFIG. 3, in the present embodiment, the self-calibration digital-to-analog converting method is, for example, adapted to the signal processing system100and the DAC110shown inFIG. 1andFIG. 2, though the invention is not limited thereto.

First, in step S300, the control unit130provides the digital input SINto the DAC110. The digital input SINis, for example, a video image signal. Then, in step S302, the DAC110outputs the first output voltage VOUT1to the comparing unit120according to the digital input SIN. Then, in step S304, the control unit130reads the output value SDof the comparing unit120to determine whether a level of the first output voltage VOUT1is within an expected range. In the present embodiment, the comparing unit120is, for example, an ADC, so that the output value SDis, for example, a digital signal obtained by analog-to-digital converting the first output voltage VOUT1, which represents the level of the first output voltage VOUT1.

Then, in step S306, the control unit130determines whether the level of the first output voltage VOUT1is within the expected range. If the level of the first output voltage VOUT1is within the expected range, it represents that the reference resistor RADJis less influenced by the fabrication process variation, and now the control unit130does not adjust the resistance of the reference resistor RADJ, and the self-calibration is ended. Comparatively, if the level of the first output voltage VOUT1is not within the expected range, the control unit130adjusts the resistance of the reference resistor RADJto implement the self-calibration. Therefore, if the level of the first output voltage VOUT1is not within the expected range, a step S308of the self-calibration digital-to-analog converting method is executed.

In the step S308, the control unit130further determines whether the level of the first output voltage VOUT1is greater than a specific expected value. In step S310, if the level of the first output voltage VOUT1is greater than the expected value, the control unit130increases the resistance of the reference resistor RADJto implement the self-calibration. Comparatively, in step S312, if the level of the first output voltage VOUT1is smaller than or equal to the expected value, the control unit130decreases the resistance of the reference resistor RADJ, which may also implement the self-calibration. Therefore, after the control unit130executes the step S310or S312, the self-calibration digital-to-analog converting method is returned back to the step S302to repeat the self-calibration. In other words, according to the above self-calibration method, the control unit130determines whether or not to adjust the resistance of the reference resistor RADJto accordingly adjust the first output voltage VOUT1according to whether the level of the first output voltage VOUT1is within the expected range.

It should be noticed that in the voltage current source conversion loop, when the resistance of the reference resistor RADJis increased, the reference current provided by the reference current source IREFis decreased, so that the level of the first output voltage VOUT1can be smaller than the expected value. Comparatively, when the resistance of the reference resistor RADJis decreased, the reference current provided by the reference current source IREFis increased, so that the level of the first output voltage VOUT1can be greater than the expected value.

In other words, in the present embodiment, after the control unit130reads the output value SD, it selects to increase or decrease the resistance of the reference resistor RADJaccording to the output value SD, so as to calibrate the DAC110. Moreover, the self-calibration digital-to-analog converting method of the present embodiment can reduce the influence of the fabrication process variation by adjusting the resistance of the reference resistor RADJof the DAC110. In another embodiment, the self-calibration digital-to-analog converting method of the present embodiment can select to adjust the mirror ratio of the reference current source IREFand the current source array112of the DAC110, or adjust the second reference voltage VREF2received by the DAC110, so as to adjust the first output voltage VOUT1to reduce the influence of the fabrication process variation.

FIG. 4is a flowchart illustrating a method that the control unit adjusts a mirror ratio of a reference current source and a current source array according to an embodiment of the invention. Referring toFIG. 1, andFIG. 2toFIG. 4, in the present embodiment, the reference current source IREFand the current source array112are, for example, implemented by a plurality of current mirrors, so that by adjusting the mirror ratio there between, an output current of the current source array112is changed, so as to achieve an effect of adjusting the first output voltage VOUT1.

In the present embodiment, the so-called “mirror ratio” refers to a ratio of numbers of master/slave transistors used for consisting current mirrors in the reference current source IREFand the current source array112. Generally, if width/length ratios of the transistors used for implementing the current mirrors are the same, according to the ratio of the numbers of the master/slave transistors, a slave side current of the current mirror can be deduced according to a master side current. For example, in the present embodiment, if the reference current provided by the reference current source IREFis the master side current of the current mirror, the output current of the current source array112is the slave side current, and when the ratio of the numbers of the master/slave transistors is 1:10, it can be deduced that the output current of the current source array112is 10 times of the reference current provided by the reference current source IREF. In other words, when the reference current provided by the reference current source IREFis fixed, by adjusting the mirror ratio, the output current of the current source array112is changed.

In the present embodiment, the self-calibration digital-to-analog converting method of adjusting the mirror ratio is similar to the self-calibration digital-to-analog converting method of adjusting the resistance of the reference resistor ofFIG. 3, and a difference there between lies in steps S410and S412. In the step S410, if the level of the first output voltage VOUT1is greater than the expected value, the control unit130decreases the mirror ratio of the reference current source IREFand the current source array112. Comparatively, in the step S412, if the level of the first output voltage VOUT1is smaller than or equal to the expected value, the control unit130increases the mirror ratio there between. Therefore, by adjusting the mirror ratio, the self-calibration digital-to-analog converting method can also achieve the effect of self-calibration.

In other words, in the present embodiment, after the control unit130reads the output value SD, it selects to increase or decrease the mirror ratio of the reference current source IREFand the current source array112according to the output value SD, so as to calibrate the DAC110. In another embodiment, the self-calibration digital-to-analog converting method can also can select to adjust the second reference voltage VREF2received by the DAC110, so as to adjust the first output voltage VOUT1to reduce the influence of the fabrication process variation.

FIG. 5is a flowchart illustrating a method that the control unit adjusts a second reference voltage according to an embodiment of the invention. Referring toFIG. 1, andFIG. 2toFIG. 5, in the present embodiment, a non-inverting input terminal of the operation amplifier OP is coupled to an adjustable second reference voltage VREF2, and an inverting input terminal thereof is coupled to a node between the reference current source IREFand the reference resistor RADJ. Therefore, when the second reference voltage VREF2is changed, the current flowing through the reference resistor RADJis changed, and the output current of the current source array is accordingly changed, so as to achieve the effect of adjusting the first output voltage VOUT1.

In the present embodiment, the self-calibration digital-to-analog converting method of adjusting the second reference voltage is similar to the self-calibration digital-to-analog converting method of adjusting the resistance of the reference resistor ofFIG. 3, and a difference therebetween lies in steps S510and S512. In the step S510, if the level of the first output voltage VOUT1is greater than the expected value, the control unit130decreases the second reference voltage VREF2. Comparatively, in the step S512, if the level of the first output voltage VOUT1is smaller than or equal to the expected value, the control unit130increases the second reference voltage VREF2. Therefore, by adjusting the second reference voltage VREF2, the self-calibration digital-to-analog converting method can also achieve the effect of self-calibration.

In other words, in the present embodiment, after the control unit130reads the output value SD, it selects to increase or decrease the second reference voltage VREF2according to the output value SD, so as to calibrate the DAC110.

On the other hand,FIG. 6is a flowchart illustrating a method that the test compensation unit adjust a compensation current according to an embodiment of the invention. Referring toFIG. 1, andFIG. 2toFIG. 6, in the present embodiment, the test compensation unit140outputs a test signal STESTto the DAC110to generate a second output voltage VOUT2(step S600). The test signal STESTis, for example, a ramp signal, which is used to test linearity of the DAC110. Then, in step S602, it is determined whether the second output voltage VOUT2of the DAC110is matched to the test signal STEST. Here, if the test signal STESTis a rising ramp signal, the second output voltage VOUT2must have a variation trend of monotonic rising for matching the test signal STEST. Similarly, if the test signal STESTis a falling ramp signal, the second output voltage VOUT2must have a variation trend of monotonic falling for matching the test signal STEST. Then, the test compensation unit140determines whether or not to adjust the compensation current ICPSaccording to whether the second output voltage VOUT2is matched to the test signal STEST.

Therefore, when the second output voltage VOUT2is matched to the test signal STEST, the test compensation unit140does not adjust the compensation current ICPS, and the operation of self-calibration is ended. When the second output voltage VOUT2is not matched to the test signal STEST, in step S604, the test compensation unit140determines whether a missing code corresponding to the second output voltage VOUT2is voltage decrease. If the missing code is voltage decrease, in step S606, the test compensation unit140increases the compensation current ICPS. If the missing code is not voltage decrease, in step S608, the test compensation unit140decreases the compensation current ICPS. Therefore, after the control unit130executes the step S606or S608, the self-calibration digital-to-analog converting method is returned back to the step S600to repeat the self-calibration. In other words, the test compensation unit of the present embodiment selects to increase or decrease the compensation current according to a determination result thereof.

Therefore, the signal processing system100can adjust the compensation current ICPSthrough the test compensation unit140, so as to compensate the offset of the first output voltage VOUT1caused by differential non-linearity (DNL).

FIG. 7illustrates a look-up table according to an embodiment of the invention. Referring toFIG. 1andFIG. 7, in the present embodiment, the control unit130may include the look-up table shown inFIG. 7. When the digital input SINis generated in the manner of value mapping, the control unit130can look up the digital input SINcorresponding to the output value SDfrom the look-up table, so as to calibrate the DAC110.

In the look-up table, each row of the first column represents a variation percentage range of the reference resistor RADJrelative to a standard resistance, and division of the ranges is determined by a compensation resolution. The second column to the fourth column respectively represent the first output voltage VOUT1, the output value SDand the digital input SINcorresponding to each variation percentage range. In the look-up table ofFIG. 7, magnitude relations of the parameters in the second column and the third column are respectively as follows: VNX> . . . >VNB>VNA>VTYP>VPA>VPB> . . . >VPX; and LevelNX> . . . >LevelNB>LevelNA>LevelPA>LevelPB> . . . >LevelPX.

In the present embodiment, the output value SDand the digital input SINare, for example, respectively a 10-bit and a 2-bit digital signal, where the bit number is determined according to the compensation resolution. For example, in a row of the variation percentage of 0%, it is assumed that the first output voltage VTYP=1.40 volts, the reference resistor RADJand the standard resistance are almost the same, which is unnecessary to be adjusted. In a row of the variation percentage of RP1%˜RP2%, the reference resistor RADJhas a positive resistor variation, for example, +1%˜+10%, so that the first output voltage VOUT1can be VPA=1.27 volts. Comparatively, in a row of the variation percentage of −RN1%˜−RN2%, the reference resistor RADJhas a negative resistor variation, for example, −1%˜−10%, so that the first output voltage VOUT1can be VNA=1.55 volts. In the above three cases, the designer may select not to adjust the reference resistor RADJaccording to an actual design requirement, and set the digital input SINto one of the patterns of the 2-bit digital signal, for example, SIN[0:1]=00, where the bit number is determined by the compensation resolution.

On the other hand, in a row of the variation percentage of RN3%˜RN4%, the reference resistor RADJhas a negative resistor variation of −11%˜−17%, and now a variation range VNA-VNBof the first output voltage VOUT1is between 1.57 and 1.68 volts. Therefore, the comparing unit120compares the first output voltage VOUT1and the first reference voltage VREF1, and the generated output value SDis between LevelNAand LevelNB. When the output value SDis represented by the 10-bit digital signal, it is between 493 and 527. Now, the digital input SINcan be set to one of the patterns of the 2-bit digital signal, for example, SIN[0:1]=01.

Moreover, in a row of the variation percentage of RP(X−1)%˜RPX%, the reference resistor RADJhas a positive resistor variation of +11%˜+25%, and now the variation of first output voltage VOUT1may reach VPX=1.26 volts. Therefore, the output value SDis below LevelPX. When the output value SDis represented by the 10-bit digital signal, it is smaller than 396. Now, the digital input SINcan be set to one of the patterns of the 2-bit digital signal, for example, SIN[0:1]=11. Similarly, in a row of the variation percentage of −RN(X−1)%˜RNX%, the reference resistor RADJhas a negative resistor variation of −18%˜−25%, and VNX=1.86 volts, LevelNX=528, and SIN[0:1]=10.

In the present embodiment, the designer can divide variation percentage ranges of the reference resistor RADJrelative to the standard resistance according to the compensation resolution, so as to design a suitable look-up table. Various values shown in the above embodiment are only used for description, and are not used to limit the invention. Moreover, although only the example of the reference resistor RADJis referred in the look-up table ofFIG. 7, adjustments of the mirror ratio of the reference current source and the current source array, the second reference voltage and the compensation current source according to the look-up table can also be deduced, and details thereof are not repeated.

Therefore, in the present embodiment, based on the look-up table ofFIG. 7, the control unit receives the output value SD, and accordingly generates the digital input SINin a manner of value mapping by firmware or software to calibrate the DAC110.

In summary, in the embodiment of the invention, the DAC is inbuilt with a reference resistor, and applies the aforementioned digital-to-analog converting method to achieve a self-calibration mechanism, so as to avoid an influence of a fabrication process variation to increase a production yield. Moreover, digital-to-analog converting method of the invention can effectively mitigate a gain error and an offset error of the DAC.