A system and method include receiving an input signal; transmitting high-frequency components of the input signal to a first converter; attenuating low-frequency components of the input signal to a predetermined level such that the low-frequency components of dither can be used to correct non-linearity errors introduced by the first converter; transmitting the low-frequency components of the input signal to a second converter; attenuating the high-frequency components of the input signal to a predetermined level such that the high-frequency components of linearization correction and dither can be used to correct non-linearity errors introduced by the second converter; converting the high-frequency components to form a first converted signal; converting the low-frequency components to form a second converted signal; and combining the first and second converted signals to form the output signal.

TECHNICAL FIELD

This patent application relates to improving the performance of an analog-to-digital converter, and more particularly to improving the spurious-free dynamic range over a wide band of frequencies.

BACKGROUND

A digital-to-analog converter (DAC) converts a digital input code to an analog output signal. The output of a DAC may deviate from the ideal output due to variations in the manufacturing process and due to various sources of inaccuracy in the digital-to-analog conversion process. The transfer function of a DAC is a plot of the signal generated at the DAC output as function of the input code. Such a plot is not continuous but is a plot of 2Nsteps, where N is the resolution of the DAC in bits. For an ideal DAC, a single straight line can be drawn through the points at each code-transition boundary, beginning at the origin of the plot.

FIG. 1shows a plot10an example of an ideal transfer function12for a 3-bit DAC with reference points at code transition boundaries. The DAC in this example produces a total of eight steps that each represents a value of a digital input code. The output signal reaches a minimum at code zero (000) and a maximum at code (111). Thus, the transition to the maximum output does not occur at voltage reference, Vref. The transition occurs at one code width, which is equal to a least significant bit (LSB). An LSB is Vref/2N.

Limitations in the materials used in fabrication and inaccuracies inherent in the conversion process itself cause the actual transfer function of a DAC to deviate from the ideal transfer function.

The deviation of a DAC's transfer function from a straight line is referred to as non-linearity.FIG. 2illustrates a plot20of non-linear deviation between the ideal12transfer function and the actual transfer function22the exemplary 3-bit DAC. The differences between the ideal voltage levels at which code transitions occur and the actual voltage are referred to as non-linear errors. Non-linear errors may be expressed in LSBs (e.g., 1.3 LSB).

Nonlinearity affects performance, which is often characterized using parameters obtained via frequency-domain analysis and is typically measured by performing a fast Fourier transform (FFT) on the analog output of the DAC.FIG. 3shows a plot30of the DAC output in the frequency domain. The fundamental frequency is equal to the frequency of the digital input (i.e., the signal measured with the DAC). All other frequency components are unwanted signals that result from harmonic distortion, thermal noise, 1/f noise, and quantization noise. Some sources of noise may not originate from the DAC itself. For example, distortion and thermal noise originate from the external circuit at the input to the DAC.

Nonlinearity in the data converter results in harmonic distortion when analyzed in the frequency domain. Such distortion is observed as “spurs” in the FFT at harmonics of the measured signal as illustrated inFIG. 3. Nonlinearity also produces spurs within the Nyquist frequency of the DAC at frequencies that are not harmonics of the fundamental frequency. The ratio between the magnitude of the measured signal and its highest spur peak is referred to as “spurious-free dynamic range” (SFDR), and is often expressed in decibels (dB). The highest spur could be a harmonic of the measured signal or non-harmonic component, depending on the application. SFDR depends on the fundamental frequency of the input signal. As the fundamental frequency increases, the SFDR tends to decrease.

SUMMARY

The invention provides methods and systems, including computer program products, for converting an input signal to an output signal.

In general, in one aspect, the invention features a system that includes a first converter having a first performance specification for use with frequencies above a frequency threshold; a second converter having a second performance specification for use with frequencies below the frequency threshold; and a frequency multiplexer coupled the first and second converters. The frequency multiplexer includes a high-pass crossover filter coupled to the first converter in which the high-pass crossover filter is configured to transmit high-frequency components of the input signal to the first converter and to attenuate low-frequency components of the input signal to a predetermined level such that the low-frequency components can be used to correct non-linearity errors introduced by the first converter. The high-frequency components are above the frequency threshold and the low frequency components are below the frequency threshold. The frequency multiplexer also includes a low-pass crossover filter coupled to the second converter in which the low-pass crossover filter is configured to transmit the low-frequency components of the input signal to the second converter and to attenuate the high-frequency components of the input signal to a predetermined level such that the high-frequency components can be used to correct non-linearity errors introduced by the second converter; and a combiner coupled the first and second converters that is configured to combine first and second converted signals received from the first and second converters to form the output signal.

Embodiments may include one or more of the following. The combiner may include a high-pass crossover filter coupled to the first converter that is configured to attenuate the low-frequency components of the first converted signal to a predetermined level; and a low-pass crossover filter coupled to the second converter that is configured to attenuate the high-frequency components of the second converted input signal to a predetermined level. The first and second performance specifications may include spurious-free dynamic-range specifications. The first converter may include a first digital-to-analog converter and the second converter comprises a second digital-to-analog converter. A lookup table may be coupled to the frequency multiplexer and configured to determine that a value of the input signal corresponds to an input code of the second converter and to express a compensation value corresponding the input code such that the compensation value causes the first converted signal to at least partially cancel a linearization error that is present in the second converted signal. The lookup table may include virtual bits that are configured to extend a number of physical bits of the second converter. The frequency multiplexer may also include a summer configured to add the compensation value to the input signal. A dithering module may be coupled to the frequency multiplexer and to the first and second converters. The dithering module may include a dithering signal generator configured to generate a dithering signal comprising a sequence of random values; negating circuitry, coupled to the dithering signal generator, that generates a dithering-cancellation signal comprising a sequence of values that are equal and opposite to the random values of the dithering signal; a first summer configured to add the dithering signal to the high-frequency components of the input signal; and a second summer configured to add the dithering-cancellation signal to the low-frequency components of the input signal. The dithering module may also include a first equalizer, coupled to the dithering signal generator, having a transfer function that is an inverse of a transfer function of the high-pass filter of the combiner; and a second equalizer, coupled to the negating circuitry, having a transfer function that is an inverse of a transfer function of the low-pass filter of the combiner. The dithering signal may be configured to attenuate spurs in the output signal and the dithering-cancellation signal may at least partially cancel distortion in the output signal caused by the dithering signal.

In another aspect, the invention features a method and a computer program produce for converting an input signal to an output signal. The method includes receiving the input signal; transmitting high-frequency components of the input signal to a first converter, (the high-frequency components being above a frequency threshold); attenuating low-frequency components of the input signal to a predetermined level such that the low-frequency components of dither can be used to correct non-linearity errors introduced by the first converter; transmitting the low-frequency components of the input signal to a second converter, (the low-frequency components being below the frequency threshold); attenuating the high-frequency components of the input signal to a predetermined level such that the high-frequency components of linearization correction and dither can be used to correct non-linearity errors introduced by the second converter; converting the high-frequency components to form a first converted signal; converting the low-frequency components to form a second converted signal; and combining the first and second converted signals to form the output signal.

Embodiments may include one or more of the following. Transmitting the high-frequency components may include attenuating the low-frequency components of the input signal, and transmitting the low-frequency components may include attenuating the high-frequency components of the input signal. Converting the high-frequency and low frequency components may include converting digital signals to analog signals. Converting the high-frequency and low frequency components may include converting analog signals to digital signals. A linearization error of the second converter that corresponds to an input code may be measured and stored in a lookup table. A value of the input signal that corresponds the input code may be determined, and a compensation value corresponding to the input code may be expressed such that the compensation value causes the first converted signal to at least partially cancel a linearization error that is present in the second converted signal.

A dithering signal comprising sequence of random values may be generated; a dithering-cancellation signal comprising a sequence of values that are equal and opposite to the random values of the dithering signal may be generated; the dithering signal may be added to the high-frequency components of the input signal to attenuate spurs in the output signal; and the dithering-cancellation signal may be added to the low-frequency components of the input signal to at least partially cancels distortion in the output signal caused by the dithering signal.

DETAILED DESCRIPTION

Although SFDR depends on frequency, the SFDR over a given frequency range may be larger or smaller in other DACs. Typically a DAC will optimize SFDR in different frequency ranges. For example, a first DAC optimizes SFDR in a frequency range below a given frequency threshold, and a second DAC optimizes SFDR in a frequency range above that frequency threshold.

The DAC plays a role in an arbitrary waveform generator (AWG). The performance of the AWG depends greatly on the performance of the DAC. For testing some state-of-art devices, the best available DAC at the time the instrument is designed may not have sufficient SFDR. Furthermore, it is desirable to optimize SFDR across a large range of frequencies that may be greater than any one optimized range of a DAC.

FIG. 4shows a converter system40for converting an input digital signal Si(n) to an analog output signal So(t) using multiple DAC's (DACH44and DACL46) so the overall SFDR of the converter system40is better than the SFDR of either the DACH44or the DACL46.

The converter system40includes a first DAC (DACH44) that optimizes SFDR for frequencies above a frequency threshold (ft), a second DAC (DACL46) that optimizes SFDR for frequencies below the frequency threshold(seeFIG. 5). The converter system40also includes a frequency multiplexer42that receives a digital input signal Si(n), and a combiner48that outputs an analog output signal So(t). The frequency multiplexer42includes a digital high-pass filter50, and a digital low-pass filter52. The digital high-pass filter50attenuates the frequency components of the input signal Si(n) that are below the threshold frequency and passes the higher frequency components to the DACH44. For ease of explanation, the range of frequencies that are below the threshold frequency will be referred to as the “low frequency range” and the range of frequencies that are above the threshold frequency will be referred to as the “high frequency range.” The digital low-pass filter52attenuates the frequency components of the input signal Si(n) that are in the high frequency range and passes components in the low frequency range to the DACL46. The DACH44and the DACL46convert the respective digital outputs of the digital high-pass and low-pass filters50and52to analog signals.

The combiner48includes an analog high-pass filter54, an analog low-pass filter56, and a summer58. The analog filters54and56filter out unwanted frequency components, such as spurs, that result from conversion processes performed by the DACH44and the DACL46. The analog high-pass filter54receives the analog signal produced by the DACH44and attenuates the frequency components that lie in the low frequency range. The analog low-pass filter56receives the analog signal produced by the DACL46and attenuates the frequency components of the signal that lie in the high frequency range. The output of the analog high-pass filter54includes the high-frequency components of the input digital signal Si(n) having a SFDR specified for the DACH44(i.e., the SFDR that is optimized for the high frequency range). Similarly, the output of the analog low-pass filter56includes the low-frequency components of the input digital signal Si(n) having a SFDR specified for the DACL46(i.e., the SFDR that is optimized for the low frequency range). The summer58adds together the analog signals produced by each of the analog filters54and56to produce the analog output signal So(t).

For any waveform at the input of the system, we can divide that waveform into higher frequency components and lower frequency components. For example if the frequency components of the input signal Si(n) are of a low frequency, the signal generated by the DACL46(i.e., the converter with the better performance at low frequency) provides a larger contribution to the output signal So(t) than does the DACH44due to digital low-pass filter52. For ease of explanation, the DAC with the higher performance for a given input signal Si(n) will be referred to as the “main converter” and the other DAC will be referred to as the “auxiliary converter.” In this case DACL46is the main converter and DACH44is the auxiliary converter. Furthermore, because DACL46is optimized for the low frequency range, the contribution of the signal from DACL46degrades the integrity of the output signal So(t). That is, the output signal generated solely by DACL46, without any contribution from DACH44being added, would have a higher SFDR than the output So(t) that includes the contribution from DACH44. Short of disconnecting DACH44from the converter system40, in this scenario, the contribution from DACH44cannot be completely set to zero in practice because the digital high-pass filter42and the analog high-pass filter54are not ideal and thus do not completely attenuate signals in their respective stop bands. In the converter system40, the contribution of the signal from the auxiliary converter (referred to as the “auxiliary signal”), whether the auxiliary converter is the DACH44or the DACL46, is apparently undesirable.FIG. 6shows a block diagram of a converter system100that modifies the converter system40ofFIG. 4such that the contribution of the auxiliary signal improves the integrity of the output signal So(t). Converter system100includes a linearization look-up table (LUT)72, a digital low-pass filter74, a gain stage78, digital summers76,90and92, a dithering module94, a frequency multiplexer41, a combiner47, a DACH44serving as the main converter for a high frequency input signal or auxiliary converter for a low frequency input signal, and a DACL46serving as the main converter for a low frequency input signal or auxiliary converter for a high frequency input signal. The dithering module94includes a dithering-signal generator82, a negating circuit84, a digital low-pass equalizer86, and a digital high-pass equalizer88. The frequency multiplexer41includes a digital high-pass crossover filter51and a digital low-pass crossover filter53. The combiner47includes an analog high-pass crossover filter55, an analog low-pass crossover filter57, and a summer58that adds the outputs of each of the analog crossover filters55and57. Unlike the filters50,52,54, and56of the converter40(shown inFIG. 4) the attenuation at stop band of these crossover filters51,53,55, and57of converter100have been intentionally limited to a predetermined level so that a signal can pass through the filter even if the signal lies in the stop band. The attenuation level of the crossover filters51,53,55, and57are adjusted so that the spurs produced from the auxiliary converter in the optimized frequency range are significantly lower in magnitude than the spurs produced by the main converter for the optimized frequency range. In some embodiments, the crossover filters are adjusted so that the spurs from the auxiliary converter are at least 10 dB less than the corresponding spurs produced by the main converter. This ensures that the spurs produced by the auxiliary converter are negligible. For example, if DACH44is the main converter and has an SFDR that is approximately 10 dB higher than the auxiliary converter DACL46for a high frequency range, the low-pass crossover filters53and57are configured to attenuate a signal components in their stop bands by 20 dB to ensure that the spurs produced by DACL46in the high frequency range are less than the spurs produced by DACH46in that range by at least 10 dB.

For each input code of the main DAC (in this case, DACL46) the linearization LUT72stores a corresponding linearity correction that was previously measured and calculated for each of the DACLcodes. When the LUT72receives a code of the input digital signal Si(n), it looks up the linearization error stored for that code and applies and expresses an equal and opposite voltage value. The summer76adds this voltage value to the input of the DACH44to cancel the linearization error that results when the DACL46converts the code to an analog value. Introducing linearization error compensation values into the input signal Si(n) brings the analog output of the DACL46closer to its ideal level. The digital gain stage78compensates for the attenuation in the stop band of high-pass filter55. In some embodiments, the digital gain stage78could be physically built into the LUT72. In some embodiments, the LUT72assigns, to each code, a first linearization error that results when the DAC transitions from a higher code, and a second linearization error that results when the DAC transitions from a lower code. In other embodiments, the first and second linearization errors are substantially the same and therefore only one linearization error value is stored for each code.

In some embodiments, this linearization is not only limited to the DACL46physical number of bits. In these embodiments, the DACL46has some virtual bits that do not produce any output. In these embodiments, the output of the DACH44may be used to linearize these virtual bits to build a combined DAC having more bits than just the DACL46alone.

Compensating for linearization in this way works better at low frequencies (e.g., frequencies below approximately 1 MHz). At higher frequencies, the DAC transfer function is frequency dependent and the linearization error depends on the frequency of the signal. Linearization is inefficient at higher frequencies as the non-linearity changes with frequency. Therefore, compensating for linearization is used mainly when the DACL46is the main converter (i.e., when the main frequency component of the input signal Si(n) is in the low frequency range). High linearity is typically important for lower frequencies in the audio range (e.g., between zero and approximately 20 KHz). The digital low-pass filter74removes high frequency noise produced by linearization. In some embodiments, system100has a SFDR value greater than 120 DB in the audio frequency range.

Spurs that are generated from converting a high frequency signal are often caused by the dynamic non-linearity of converters. Therefore, the linearization technique described above for lower frequency input signals is less useful for higher frequency input signals. Furthermore, the spurs (both harmonic and non-harmonic) are strongly correlated with the input signal. To reduce the correlation between the input signal and the spurs, additive dither noise is added to the input signal Si(n). The result is that the frequencies at which the spurs appear in the output signal are more randomized over time and therefore spur will be spread through out the entire spectrum. In the case of a repetitive signal, averaging techniques could reduce random noise. For example, by averaging a number of N values of a signal, noise that is present is reduced by a factor of approximately the square root of N. In the case of spurs that are correlated with the transfer function of the converter, averaging does not help to reduce their contribution because they are not random and always show up at the same frequency for a given DAC transfer function. Dithering will make the spur random, so averaging in presence of dither will become effective.

The dithering is performed by dithering module94. The dithering module94dithers the input of each converter to attenuate unwanted spurs that result in their outputs. The dither signal generator82generates a dither signal Sd(n), which is a sequence of random numeric value of a few LSB around zero. The dither could have narrow band or broadband spectrum. The summer90and92add the dither signals at the inputs of converters44and46with samples of the input signal Si(n) after it passes through the digital crossover filters51and53. The dither signal added to the input of converters reduces the correlation of the spurs to the signal at the expense of adding a higher noise level to the output of each converter. The combined transfer function of digital low-pass equalizer86and analog high-pass crossover filter55should be equal to combined transfer function of digital high-pass equalizer88and analog low-pass crossover filter57. The digital equalizers86and88compensate the effect of the analog crossover filters55and57so that the dither signal generated by the same generator82produce two dither signals of opposite amplitude at the combiner58. The digital equalizers are designed such that the dither noise produced by the DACH46can be used to cancel out the dithering noise added to the input of the DACL44at low frequency range and the dither noise produced by the DACL44can be used to cancel out the dithering noise added to the input of the DACH46at high frequency range.

The output of the analog high-pass crossover filter55includes the output waveform with the added dithering noise. The output of the analog low-pass crossover filter57also includes the output waveform, though at an attenuated level, and added noise that is equal and opposite of the dithering noise. For ease of explanation, this added noise will be referred to as a “correction waveform.” When the outputs of the analog high-pass and low-pass crossover filters55and57are added, the correction waveform cancels the dithering noise yielding the output waveform that includes both contributions from the DACH44and the DACL46. To ensure that the dithering noise and the correction waveform have the same amplitude, the correction waveform is amplified, by the digital high-pass equalizer88, to compensate for the attenuation of the crossover filters. For example, if the analog low-pass crossover filter has a stop-band attenuation of 20 dB, the magnitude of the correction waveform would need to be boosted by 20 dB.

The correction waveform is produced by negating the dithering signal Sd(n) using the negating circuitry84to produce a digital signal having sample values that are equal and opposite to the sample values of the dithering signal Sd(n). The correction waveform is then passed through the digital high-pass equalizer88. The summer92adds the output of the digital high-pass equalizer88to that of the digital low-pass crossover filter53. Thus, the correction waveform cancels the offsets produced by the dithering signal Sd(n). If for example, the input signal Si(n) were zero and dithering signal Sd(n) were generated, ideally, the output signal So(t) would also be zero. In some embodiments, the negation circuitry84is absent from the converter100and the negation operations of the negating circuitry84are performed by the summer92.

The dithering signal Sd(n) can be added to either the output signal from the digital high-pass crossover filter51or the output of the digital low-pass crossover filter53. For example, the negating circuitry84could be coupled to the digital low-pass equalizer86rather than to the digital high-pass equalizer88.

InFIG. 6, the linearization LUT72is arranged so that the output of the DACH44compensates non-linearities introduced by the DACL46. The dithering module94, however, is arranged so that it dithers the portion of the input signal that lies in the high frequency range. Dithering the output signal to randomize spurs is particularly advantageous when the DACH44is the main converter and when the frequency components of the input signal Si(n) are too high to efficiently correct for nonlinearity using linearization LUT72. In some embodiments, the dithering module94is arranged to dither the portion of the input signal Si(n) that lies in the low frequency range. In some of these embodiments, the LUT72is also arranged so that the output of DACL46compensates non-linearities introduced by DACH44, provided that the main frequency components of the input signal are sufficiently low so that the transfer function of DACH44is nearly frequency-independent.

FIG. 7shows a plot110of SFDR versus output frequency that were measured for the DACH44, the DACL46, and the converter system100shown inFIG. 6. The DACH44is a Texas Instruments® DAC5675 operating at a sampling frequency of 400 MHz and the DACL46is a MAXIM® MAX5888 operating at a sampling frequency of 400 MHz. As evident from the plot, the performance of the converter system100is better than the performance of either the DACH44or the DACL46.

Referring toFIG. 8, a process120for converting an digital input signal Si(n) to an analog output signal So(t) using the converter system100shown inFIG. 6. The frequency multiplexer42receives (122) the digital input signal Si(n) and divides (124) the signal into its high and low frequency components. The linear compensation value produced by the linearization LUT72is added (126) to the dithering signal generated by the dithering signal generator82. The result is then passed through the digital low-pass equalizer86and added (128) to the high frequency components of the input signal by summer90. A dithering-cancellation signal, which is equal and opposite to the dithering signal, is produced at the output of the negating circuitry84. The result is then passed through the digital high-pass equalizer88and added (130) to the low frequency components of the input signal by summer92. The DACH44converts (132) the signal produced by summer90to a first analog signal and the DACL46converts (134) the signal produced by summer90to a second analog signal. The analog outputs of DACH44and DACL46are filtered by the analog high-pass and low-pass crossover filters55and57. The summer58then combines (136) the signals received from the analog high-pass and low-pass crossover filters55and57to form the output signal So(t).

Process120is not limited to use with the hardware and software described herein. Process120can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations thereof.

Digital data to be sent to each DAC could be computed in real time when an analog waveform is generated or off-line and stored in a memory device.

Method steps associated with implementing process120can be performed by one or more programmable processors executing one or more computer programs to perform the functions of the processes. All or part of process120can be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) and/or an ASIC (application-specific integrated circuit).

Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. Elements of a computer include a processor for executing instructions and one or more memory devices for storing instructions and data.

The circuitry described herein, including the frequency multiplexer41, the linearization LUT72, the dithering module94, the DACH44, the DACL46, and the combiner47, may be implemented as part of converter systems40and100or as separate circuitry for use in conjunction with converter systems40and100.

A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made. For example, converter systems40and100could be modified to convert an analog input to a digital output by replacing the DACH44with an analog-to-digital converter (ADC) having an SFDR that is optimized for the high frequency range and by replacing the DACL46with an ADC having an SFDR that is optimized for the low frequency range. Accordingly, other embodiments are within the scope of the following claims.