Adaptive power control for hysteretic regulators

A hysteretic regulator may be set to an active mode when voltage at an output falls to a first threshold level. In the active mode, charge is applied to an output node by a current having a set limit value. The regulator is set to an inactive mode when the voltage at the output node rises to a second threshold level. The current limit value is automatically adjusted as a function of average regulator current. An indication of average regulator current may be obtained by charging a sense capacitor during the active mode and discharging the sense capacitor during the inactive mode. The voltage of the sense capacitor, which is representative of the average regulator current, is used to generate an offset adjustment applied to a regulator controller.

TECHNICAL FIELD

The present disclosure relates to control of regulators, more particularly to switched regulators that can be operated in burst mode.

BACKGROUND

Switching DC/DC power converters designed to be efficient at light loads typically use a hysteretic control technique, sometimes referred to as Burst Mode or Pulse Frequency Mode, to regulate output voltage. In such operation, the converter operates at a fixed power level, usually by regulating a peak inductor current, until the output achieves the desired voltage. The converter then goes into a “sleep” (inactive) operational mode, drawing minimal quiescent current from the power source. During the inactive mode, the load current is supplied only by an output filter capacitor. When the output voltage has dropped by a small amount, typically one to two percent, the converter comes out of the sleep mode and resumes active operation to bring the output voltage back up to the desired value. The cycle of alternating periods of active and inactive operational modes repeats, maintaining the output voltage within the specified hysteretic limits. The time duration of the active, or “wake”, time and sleep time varies with the amount of output capacitance and the amount of hysteresis chosen. The percentage of time spent awake or asleep, i.e., duty cycle, varies with load. At its maximum load capability, the converter stays awake one hundred percent of the time.

Typical converter architecture may comprise step-up (boost), step-down (buck) or step-down/step-up (buck-boost) designs. A known “four-switch” buck-boost converter is described, for example, in an October 2001 datasheet for the LTC3440 “Micro-power Synchronous Buck-Boost DC/DC Converter” integrated circuit manufactured by Linear Technology Corporation. During the active mode, an inductor is switched among various circuit configurations to apply charge to the output capacitor. In active burst operation, inductor current traditionally is controlled to vary, cyclically, between fixed upper and lower limits, commonly called peak and valley levels, respectively.

An advantage of burst mode converter operation, as compared to fixed frequency pulse width modulated switching operation, is high efficiency at light loads, because the percentage of time that the converter is asleep increases as the load current diminishes. If the quiescent current of the hysteretic converter can be made very small, typically tens of micro-amps, while in the sleep mode, high efficiency can be maintained until the load current drops to as little as one hundred micro-amps or less. This operation is advantageous for battery powered applications that spend considerable time in an idle state that requires little power.

A disadvantage of the burst mode operation is that the maximum output power that can be delivered is limited by the peak inductor current, which is fixed regardless of load. If the peak inductor current is raised to increase power capability, the converter's conduction losses are increased, which lowers efficiency across the entire load range. Therefore, in a hysteretic converter, a fixed peak inductor current value is chosen as a compromise between efficiency and maximum power capability. If maximum power capability is increased, the increased peak inductor current results in lower efficiency at light loads. Difficulty in sensing load current while maintaining hysteretic operation, presents challenges in departing from fixed peak inductor current operation.

SUMMARY OF THE DISCLOSURE

The subject matter described herein fulfills the above-described needs of the prior art. A DC/DC regulator may be set to an active mode when the voltage at the output falls to a first threshold level. In the active mode, charge is applied to an output node by a current having a set limit value. The regulator is set to an inactive mode when the voltage at the output node rises to a second threshold level. The current limit value is automatically adjusted as a function of average regulator output current.

Preferably, an indication of average regulator output current is obtained by charging a sense capacitor during the active mode of the regulator and discharging the sense capacitor during the inactive mode of the regulator. The voltage of the sense capacitor, which is representative of the average regulator output current, is sensed and converted to a current. A fixed minimum current source is added to the converted current to generate an offset adjustment.

In the active mode, an inductor is switchably coupled to a voltage source to charge a regulator output capacitor, the inductor current being controlled to vary cyclically between maximum (peak) and minimum (valley) levels. Regulator current is sensed and the sensed signal is compared with the offset adjustment. When the sensed current signal attains the offset adjustment value, the current limit value is reached. The current limit value, thus, is varied in accordance with the voltage of the sense capacitor. The adjusted current limit value preferably is the peak inductor current, although a valley current limit may also be adjusted. The current converted from the sense capacitor voltage may be set not to exceed a maximum level.

A power controller, coupled to the converter input and to the inductor, is responsive to output voltage feedback to change between active and inactive modes when the hysteretic thresholds are reached. A power adjust control circuit has an input coupled to the power controller for receiving a signal indicative of the mode of the power controller. A first switch is coupled between a first terminal of a voltage source and a node of the sense capacitor. A second switch is coupled between a second terminal of the voltage source and the node of the sense capacitor. In response to an active mode signal at the power adjust control circuit input, the first switch is closed to charge the capacitor. In response to an inactive mode signal at the input, the second switch is closed to discharge the sense capacitor. The voltage at the sense capacitor node is proportional to the average regulator current.

A voltage to current converter is coupled to the sense capacitor to produce a current representing the average regulator current. Through adder circuitry, a minimum current is added to the output of the voltage to current converter to generate an offset voltage. A comparator has a first input for receiving a sensed inductor current signal, a second input for receiving the offset voltage, and an output coupled to the power controller. In response to the comparator output, the power controller sets the peak current value. A second comparator output may also be used to set the valley current value.

DETAILED DESCRIPTION

Switching regulator20, represented in the schematic block diagram ofFIG. 1, receives an input voltage from a power supply at input node VINand provides a preset output voltage at the VOUTnode. Connected in series between the input and output nodes are a switched power controller22and inductor24. Output capacitor26is connected between the output node and common connection. Power controller22is representative of any known hysteretic burst mode operable switching and control circuitry for driving inductor current cyclically between peak and valley levels during an active state. For example, known buck, boost, and buck-boost hysteretic converter architecture may be employed.

Voltage at the output node is fed back to the power controller as represented schematically by feedback line28. A voltage divider or well-known equivalent circuit may by used to scale the feedback voltage to meet appropriate design parameters. When the feedback voltage attains the hysteretic thresholds, the controller transitions between the active and inactive modes of operation. The controller22outputs a “WAKE/SLEEP” signal on line30that is indicative of the mode of operation, the signal applied to an input of power adjust control circuit32. The signal has a duty cycle that corresponds to the wake/sleep duty cycle of the power controller. Power adjust control circuit32outputs an offset signal that is applied to the negative input of comparator34. A current sensor36, represented schematically, applies a signal indicative of sensed inductor current to the positive input of comparator34. Any known current sensing technique may be used to provide the sensed current signal. The output of comparator34is applied to an input of switched power controller22.

FIG. 2is a circuit diagram of an exemplified power adjust control circuit32. Connected between a first voltage source terminal VCCand a common second voltage source terminal are current source34, controlled switch36, controlled switch38, and current source40. Connected between the junction of switches36and38and the second voltage source terminal is capacitor42. Logic circuit44, which may include a flip-flop or the like, has an input for receiving the “wake/sleep” signal from line30. A first output of logic circuit44is applied to control switch36. A second output of logic circuit44is applied to control switch38. When the signal at line30is indicative of the wake, or active, mode of controller22, the logic circuit maintains switch36closed and switch38open. At this time, capacitor42is charged from the first voltage source terminal via current source34and switch36. When the signal at line30is indicative of the sleep, or inactive, mode of controller22, the logic circuit maintains switch38closed and switch36open. At this time, capacitor42is discharged via switch38and current source40to the second voltage source terminal.

Current source46and switch48are connected in series across the voltage source terminals, as is the series connection of switch50, switch52resistor54, and switch56. The upper node of capacitor42is connected to the gate of switch52. The gates of switches48and56are connected together. Switch58is connected in series with resistor60across the voltage source terminals. Switches50and58are connected in a current mirror configuration. Current source62is connected between the first voltage source terminal and the junction, output line33, of switch58and resistor60.

By charging capacitor42with a fixed current when the controller is active, and discharging the capacitor with a fixed current when the converter is inactive, a voltage proportional to average load current is produced at the upper node of the capacitor42. This voltage is fed to a current converter that comprises switch52and resistor54. The maximum current in resistor54is limited by current sink switch56, which is set by current source46and switch48. The current154in resistor54will be:
I54=(V42−VSAT(56)−VGS(52))/R
Where V42is the voltage of capacitor42, VSAT(56)is the voltage across switch56, VGS(52)is the gate to source voltage of switch52, and R is the resistance of resistor54.

The current in resistor54is mirrored by current mirror switches50and58and added to a set minimum current from current source62to create an offset output voltage across resistor60. The maximum value of I54is limited, regardless of whether the voltage at capacitor42increases inordinately as a result of a varying VCCsupply voltage. The ratio of the discharge current of capacitor42to charge current of capacitor42will determine the converter operating duty cycle (percentage of wake time) that is required to ramp up the voltage on capacitor42and transition to a maximum inductor current.

The use of duty cycle “awake time vs. asleep time” information as an indicator of average load current avoids the complexity of actually measuring the average current directly. In a monolithic IC power converter, the information can be obtained internally, requiring no extra pins or external components. The use of voltage of capacitor42to adjust the peak inductor current enables higher peak currents to support heavy loads and lower peak currents for better efficiency at lighter loads. If inductor valley current is adjusted as well as peak current, peak-to-valley inductor current remains relatively constant with load. With such provision, the effect of load variation on switching frequency and output ripple can be minimized.

Typical waveforms, illustrating the inductor current variation with load current, are shown inFIG. 3. In this example, the load current has been ramped up from less than 20 mA to 50 mA. In response to the change in load, the peak inductor current increases from a minimum value of 100 mA to a maximum value of 190 mA. The valley current of the inductor increases from a minimum of 20 mA to a maximum of 120 mA.

In this disclosure there are shown and described only preferred embodiments of the invention and but a few examples of its versatility. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein. For example, the invention can be incorporated as part of a monolithic power converter or implemented in a converter using discrete components. The invention is applicable to any hysteretic converter architecture and not restricted to use at any particular power level.