Fast floating point result forwarding using non-architected data format

A microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands. The microprocessor includes a plurality of floating-point units, each comprising an arithmetic unit configured to receive non-ADF source operands and to perform a floating-point operation on the non-ADF source operands to generate a non-ADF result. The microprocessor also includes forwarding buses, configured to forward the non-ADF result generated by each arithmetic unit of the plurality of floating-point units to each of the plurality of floating-point units for selective use as one of the non-ADF source operands.

FIELD OF THE INVENTION

The present invention relates in general to the field of pipelined microprocessor architectures, and particularly to the forwarding of floating-point results from one instruction to another.

BACKGROUND OF THE INVENTION

The x86 architecture specifies multiple data formats for floating point operands, namely, single-precision, double-precision, and extended double-precision. This implies that the floating point units have a different multiplier, adder, etc. for each architected data format. This is an inefficient use of space and power. So, to reduce the number of multipliers, adders, etc., the floating point units include a single multiplier, adder, etc. each capable of operating on operands that are in a single non-architected data format. The floating point units convert the received source operands from their architected data format to the non-architected data format, perform the operation on the non-architected data format operands to generate a result in the non-architected data format, and then convert the result back to the architected data format. The architected data format results are then forwarded to the floating point units as source operands, as illustrated by the conventional floating point units112shown inFIG. 4.

BRIEF SUMMARY OF INVENTION

In one aspect the present invention provides a microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands. The microprocessor includes a plurality of floating-point units, each comprising an arithmetic unit configured to receive non-ADF source operands and to perform a floating-point operation on the non-ADF source operands to generate a non-ADF result. The microprocessor also includes forwarding buses, configured to forward the non-ADF result generated by each arithmetic unit of the plurality of floating-point units to each of the plurality of floating-point units for selective use as one of the non-ADF source operands. Each of the floating-point units includes a mux configured to receive the non-ADF results and to select one or more of the non-ADF results for provision as the non-ADF source operands to the floating-point unit.

In another aspect, the present invention provides a method for processing floating-point instructions in a microprocessor having first and second floating-point units each having an arithmetic unit, wherein the microprocessor has an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands. The method includes the arithmetic unit of the first floating-point unit performing a floating-point operation on first and second non-ADF source operands to generate a first non-ADF result. The method also includes the arithmetic unit of the second floating-point unit performing a floating-point operation on third and fourth non-ADF source operands to generate a second non-ADF result. The method also includes the first floating-point unit forwarding the first non-ADF result to the second floating-point unit. The method also includes the second floating-point unit forwarding the second non-ADF result to the first floating-point unit. The method also includes the arithmetic unit of the first floating-point unit performing a floating-point operation on the second non-ADF result and a fifth non-ADF operand to generate a third non-ADF result. The method also includes the arithmetic unit of the second floating-point unit performing a floating-point operation on the first non-ADF result and a sixth non-ADF operand to generate a third non-ADF result. Each of the floating-point units includes a mux configured to receive the non-ADF results and to select one or more of the non-ADF results for provision as the non-ADF source operands to the floating-point unit.

In yet another aspect, the present invention provides a computer program product encoded in at least one computer readable medium for use with a computing device, the computer program product comprising computer readable program code embodied in said medium for specifying a microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands. The computer readable program code includes first program code for specifying a plurality of floating-point units, each comprising an arithmetic unit configured to receive non-ADF source operands and to perform a floating-point operation on the non-ADF source operands to generate a non-ADF result. The computer readable program code also includes second program code for specifying forwarding buses, configured to forward the non-ADF result generated by each arithmetic unit of the plurality of floating-point units to each of the plurality of floating-point units for selective use as one of the non-ADF source operands. Each of the floating-point units includes a mux configured to receive the non-ADF results and to select one or more of the non-ADF results for provision as the non-ADF source operands to the floating-point unit.

DETAILED DESCRIPTION OF THE INVENTION

The forwarding of architected data format results described above with respect toFIG. 4, or more specifically the data format conversions performed, is time-wasteful in the sense that it adds additional latency in cases where the result-generating and result-consuming instructions are scheduled back-to-back for execution. To reduce latency, embodiments described herein include modified floating point units that forward the non-architected data format (NADF) result without converting to the architected data format (ADF) and are capable of receiving and operating directly on the NADF operands without converting them from the ADF to the NADF. This reduces the latency by removing the conversion time in and out of the floating point units from the critical path. The amount of latency reduced may be particularly significant when there is a sequence of back-to-back result-generating and result-consuming instructions such that the modified floating point units are able to forward the NADF results. In one embodiment, the NADF includes additional exponent bits beyond the number of exponent bits specified by the largest ADF. For example, in one embodiment the largest ADF is the 80-bit double-precision format, which includes a 15-bit exponent field, and the NADF includes a 17-bit exponent field to accommodate overflows and underflows.

Referring now toFIG. 1, a block diagram illustrating a microprocessor100that incorporates the latency-reducing NADF result forwarding described above is shown. The microprocessor100includes a plurality of floating point units (FPU)112. In one embodiment, the floating point units112include a first floating point unit112A that includes a floating point multiplier226(seeFIG. 2) that generates a first ADF result162, and a second floating point unit112B that includes a floating point adder236(seeFIG. 2) that generates a second ADF result164. The floating point units112receive ADF source operands152from a multiplexer116that receives ADF source operands from general purpose registers (GPRs)118, from temporary registers of a reorder buffer (ROB)114, and the ADF results162/164from the floating point units112themselves. Additionally, the floating point units112generate respective exception signals172/174to the ROB114to indicate that an instruction created an exception condition, such as an overflow or underflow, as described in more detail below.

In one embodiment, the microprocessor100is an x86 (also referred to as IA-32) architecture microprocessor100; however, other microprocessor architectures may be employed. A microprocessor is an x86 architecture processor if it can correctly execute a majority of the application programs that are designed to be executed on an x86 microprocessor. An application program is correctly executed if its expected results are obtained. In particular, the microprocessor100executes instructions of the x86 instruction set and includes the x86 user-visible register set.

Referring now toFIG. 2, a block diagram illustrating in more detail the floating point units112ofFIG. 1is shown. Floating point unit112A includes a converter222, coupled to a mux224, coupled to a NADF multiplier226, coupled to a second converter228. Floating point unit112B includes a converter232, coupled to a mux234, coupled to a NADF adder236, coupled to a second converter238.

The converter222converts the ADF operands152into NADF operands272that are provided to the mux224. The mux224also receives a NADF result252forwarded from the NADF multiplier226and a NADF result254forwarded from the NADF adder236. From its inputs, the mux224selects NADF operands266for provision to the NADF multiplier226, which multiplies the operands266to generate the NADF result252. The converter228converts the NADF result252to the ADF result162ofFIG. 1. Additionally, the converter228generates an exception indicator172ofFIG. 1if it detects that the ADF result162created an exception condition, such as an underflow or overflow. That is, the NADF may have accommodated the result252without creating an underflow or overflow; however, the smaller ADF may not sufficiently accommodate the NADF result252such that the conversion from the NADF to the ADF creates an exception condition.

The converter232converts the ADF operands152into NADF operands274that are provided to the mux234. The mux234also receives the NADF result252forwarded from the NADF multiplier226and the NADF result254forwarded from the NADF adder236. From its inputs, the mux234selects NADF operands268for provision to the NADF adder236, which adds the operands268to generate the NADF result254. The converter238converts the NADF result254to the ADF result164ofFIG. 1. Additionally, the converter238generates an exception indicator174ofFIG. 1if it detects that the ADF result164created an exception condition, such as an underflow or overflow.

As may be observed by comparingFIGS. 2 and 4, the floating point units112ofFIG. 2advantageously potentially reduce instruction execution latency by directly forwarding to one another their NADF results252/254. This is in contrast to the conventional floating point units112ofFIG. 4, which incur the latency of converting the NADF results to ADF results, forwarding the converted ADF results, and then reconverting to NADF operands.

Floating point operations may generate exception conditions, such as overflow or underflow. A side-effect of the NADF is that some results that would overflow/underflow in the ADF would not do so in the NADF, e.g., because of the larger exponent, as discussed above. Consequently, the forwarding of the NADF results252/254is speculative because the programmer may not want the instruction that receives the forwarded NADF result252/254to execute with a value that would cause an exception when converted to ADF. Therefore, in parallel with the speculative forwarding of NADF results252/254, the converters228/238also perform the conversion to ADF, and if the conversion yields an overflow/underflow, then they generate an exception172/174on the forwarding instruction and the microprocessor100kills the instruction that executed using the speculatively forwarded NADF result, as described in more detail with respect toFIG. 3.

Referring now toFIG. 3, a flowchart illustrating an example of operation of the microprocessor100ofFIG. 1is shown. Flow begins at block302.

At block302, floating point unit112A receives an instruction-B for execution. The mux224detects that one of the source operands is the NADF result254of a previous instruction-A that has been forwarded from the NADF adder236and accordingly selects the forwarded NADF result254. The mux224may also select as the other operand the forwarded NADF result252from the NADF multiplier226or the converted NADF operands272. Flow proceeds to block304.

At block306, the forwarding buses forward the NADF result252of instruction-B to the NADF adder236. Flow proceeds to block308.

At block308, floating point unit112B receives an instruction-C for execution. The mux234detects that one of the source operands is the NADF result252of instruction-B that has been forwarded at block306from the NADF multiplier226and accordingly selects the forwarded NADF result252. The mux234may also select as the other operand the forwarded NADF result254from the NADF adder236or the converted NADF operands274. Flow proceeds to block312.

At block312, the NADF adder236adds the NADF operands268to generate the NADF result254for instruction-C. Flow ends at block312, although it is understood that the forwarding of NADF results252and/or254may advantageously continue for a long sequence of instructions, thereby reducing latency and speeding up the execution of the sequence of instructions relative to the conventional floating point units112ofFIG. 4that include the ADF-to-NADF conversion and NADF-to-ADF conversion in the forwarding paths.

At block322, the converter228converts the NADF result252of instruction-B to ADF result162. Flow proceeds to decision block324.

At decision block324, the converter228determines whether the NADF result252of instruction-B creates an exception condition when converting to ADF. If so, flow proceeds to block326; otherwise, flow proceeds to block328.

At block326, the converter228asserts the exception indicator172to the ROB114. Consequently, the microprocessor100will take an exception, and the ROB114will flush instruction-C since instruction-C is newer in program sequence than instruction-B that caused the exception. This is necessary since the NADF result252of instruction-B was speculatively forwarded to the NADF adder236without knowledge of whether the NADF result252was a good operand, i.e., without knowledge of whether the NADF result252was a non-underflowed/overflowed value from an ADF perspective. That is, the programmer may not have desired instruction-C to execute with a non-good operand. However, advantageously the NADF results252/254are speculatively forwarded to potentially reduce the latency of instruction execution and in most cases both the forwarding and the receiving instructions will complete successfully. Flow ends at block326.

At block328, floating point unit112A provides the ADF result162to the ROB114for storage in a temporary register therein. Flow proceeds to block332.

At block332, the ROB114retires the ADF result162from the temporary register to the appropriate GPR118. Flow ends at block332.

While various embodiments of the present invention have been described herein, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant computer arts that various changes in form and detail can be made therein without departing from the scope of the invention. For example, software can enable, for example, the function, fabrication, modeling, simulation, description and/or testing of the apparatus and methods described herein. This can be accomplished through the use of general programming languages (e.g., C, C++), hardware description languages (HDL) including Verilog HDL, VHDL, and so on, or other available programs. Such software can be disposed in any known computer usable medium such as magnetic tape, semiconductor, magnetic disk, or optical disc (e.g., CD-ROM, DVD-ROM, etc.), a network, wire line, wireless or other communications medium. Embodiments of the apparatus and method described herein may be included in a semiconductor intellectual property core, such as a microprocessor core (e.g., embodied in HDL) and transformed to hardware in the production of integrated circuits. Additionally, the apparatus and methods described herein may be embodied as a combination of hardware and software. Thus, the present invention should not be limited by any of the exemplary embodiments described herein, but should be defined only in accordance with the following claims and their equivalents. Specifically, the present invention may be implemented within a microprocessor device which may be used in a general purpose computer. Finally, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the scope of the invention as defined by the appended claims.