High speed chip screening method using delay locked loop

A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface that reads the delay code from the register and outputs the delay code to automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum chip speed.

BACKGROUND OF THE INVENTION

The present invention relates generally to an apparatus for screening high speed chips during mass production, and more particularly, to high speed chip screening via an algorithm in an embedded delay lock loop (DLL) that is read from a register through an interface by automated testing equipment (ATE).

High speed chips, such as a serializer/deserializer (serdes), advanced memory buffer (AMB), or the like can achieve speeds reaching several Giga-samples per second (GSa/s). During mass production, it is difficult to monitor the process variation and test the chip speed for compliance. Conventionally, the chip would include a built-in self-test (BIST) loop. By sweeping a reference clock through the BIST loop, the maximum speed of the chip could be determined. However, this procedure suffers from several drawbacks, particularly in the context of speed screening during mass production. For example, screening using the BIST is time-consuming due to the frequency sweeping. Further, the BIST is always a partial test and cannot cover the entire chip, and repeatability is a concern with BIST loops.

Another conventional screening technique includes the provision of a ring oscillator on the chip. The speed of the chip could be determined by measuring the frequency of the ring oscillator at an output, but an oscilloscope is required to perform the frequency measurement. Using an oscilloscope during production testing is very difficult, and often impossible. As a further complication to speed screening, ATE cannot test a high speed signal directly from the chip due to hardware limitations.

It is therefore desirable to provide an apparatus that enables accurate speed screening of high speed chips, reduces test times during mass production, is reliable and repeatable, and does not require the use of unnecessary testing instruments.

BRIEF SUMMARY OF THE INVENTION

Briefly stated, an embodiment of the present invention comprises a voltage controlled delay line (VCDL) for use in an apparatus for measuring the maximum speed of a chip with automated testing equipment. The VCDL includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal. The phase error signal represents a phase delay between the reference clock signal and the output clock signal. A register has a delay code stored therein. The VCDL is configured to generate the output clock signal by applying the delay code stored in the register to the reference clock signal to delay the reference clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface configured to read the delay code from the register of the VCDL and output the delay code to the automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum speed of the chip.

Another embodiment of the present invention comprises an apparatus for measuring the maximum speed of a chip with automated testing equipment including a phase detector having a first input configured to receive a reference clock signal, a second input configured to receive an output clock signal, and an output. The phase detector is configured to compare the reference clock signal with the output clock signal to generate at the output of the phase detector a phase error signal representing a phase delay between the reference clock signal and the output clock signal. A voltage controlled delay line (VCDL) includes a first input configured to receive the reference clock signal, a second input coupled to the output of the phase detector and configured to receive the phase error signal, a first output configured to feed back the output clock signal to the second input of the phase detector, a second output, and a register having a delay code stored therein. The VCDL is configured to generate the output clock signal by applying the delay code stored in the register to the reference clock signal to delay the reference clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. An interface is coupled to the second output of the VCDL and is configured to read the delay code from the register of the VCDL and output the delay code to the automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum speed of the chip.

A further embodiment of the present invention comprises a method of measuring the maximum speed of a chip with automated testing equipment. The method includes receiving a reference clock signal at a voltage controlled delay line (VCDL), generating, by the VCDL, an output clock signal by delaying the reference clock signal according to a delay code stored in a register of the VCDL, and adjusting the delay code according to a phase error signal received by the VCDL. The phase error signal represents a phase delay between the reference clock signal and the output clock signal. The method further includes outputting, by the VCDL and through an interface to the automated testing equipment, the delay code when the phase delay is equal to a predetermined value. The outputted delay code corresponds to the maximum speed of the chip.

DETAILED DESCRIPTION OF THE INVENTION

Certain terminology is used in the following description for convenience only and is not limiting. The words “a” and “an”, as used in the claims and in the corresponding portions of the specification, mean “at least one.”

Referring to the drawings in detail, wherein like reference numerals indicate like elements throughout,FIG. 1shows a preferred embodiment of a system10for measuring the maximum speed of a chip. The system10, which forms an on-chip DLL, includes a phase detector12having a first input14, a second input16, and an output18. The first input14is configured to receive a reference clock signal REF CLK, which is preferably generated by the circuitry of the chip (not shown). The second input16is configured to receive an output clock signal OUT CLK, which will be described in further detail below. The phase detector12is configured to compare the reference clock signal REF CLK with the output clock signal OUT CLK to generate a phase error signal ΦE, which is sent to the output18of the phase detector12. The phase error signal ΦEis a control signal that represents a phase delay between the reference clock signal REF CLK and the output clock signal OUT CLK.

The system10also includes a voltage controlled delay line (VCDL)20, which includes first and second inputs22,24and first and second outputs26,28. Similar to the first input14of the phase detector12, the first input22of the VCDL20receives the reference clock signal REF CLK. The second input24of the VCDL20is coupled to the output18of the phase detector12and is therefore configured to receive the phase error signal ΦE. The VCDL20generates the output clock signal OUT CLK at the first output26, which is configured to feed back the output clock signal OUT CLK to the second input16of the phase detector20.

The VCDL20also includes a register30, which stores a delay code therein. The VCDL20is configured to generate the output clock signal OUT CLK by applying the delay code stored in the register30to the reference clock signal REF CLK to delay the reference clock signal REF CLK. The delay code is adjustable according to the phase error signal ΦEsupplied by the phase detector12. Once the phase delay between the reference clock signal REF CLK and the output clock signal OUT CLK is equal to a predetermined (desired) value, the delay code is locked. The predetermined value is preferably a phase delay of ninety degrees, but other values may be used.

The delay code is preferably a first multi-bit control signal and a second multi-bit control signal, which may be applied to at least two delay buffers.FIG. 2is an exemplary partial schematic of a VCDL20having three delay buffers32,34,36. The first delay buffer32includes three inverters38a,38b,38cand a variable capacitor39. The second and third delay buffers34,36are identically arranged. The reference clock signal REF CLK traverses a number of the delay buffers32,34,36based on the first multi-bit control signal delay code, and the capacitance of the variable capacitors39,41,43is determined by the second multi-bit control signal of the delay code. Table 1 below shows a potential application of the delay code within the VCDL20.

According to the example of Table 1, the first multi-bit control signal SEL is an eight bit signal and the second multi-bit control signal D is a five bit signal. In Step 1, the first control signal SEL has an exemplary value of 11111110, causing the reference clock signal REF CLK to traverse the first buffer32only (delay1path inFIG. 2traversing inverters38a,38b). The second control signal D has an exemplary value of 00000, setting the variable capacitor39to the lowest setting. Thus, the delay experienced by the reference clock signal REF CLK is equivalent to the delay caused by the traversal of two inverters38a,38b.

In step 2, the first control signal SEL remains the same, but the second control signal D is adjusted to an exemplary value of 00001, thereby increasing the delay from step 1 by an additional value rc introduced by the variable capacitor39. As further steps are required, D is adjusted by an additional amount rc until the variable capacitor39reaches its maximum. By step 7, the first control signal SEL is adjusted to an exemplary value of 11111101, causing the reference clock to now traverse the first and second delay buffers32,34(delay2path inFIG. 2traversing inverters38a,40a,40b,38c). The second control signal D supplied to the variable capacitor41of the second delay buffer34begins at the exemplary value of 00000, and the process of stepping the variable capacitance is repeated. At step 13, the first control signal SEL is 11111011, causing the reference clock signal REF CLK to traverse all three delay buffers32,34,36(delay3path traversing inverters38a,40a,42a,42b,40c,38c). As can be seen from the above description, the VCDL20adjusts between steps based on the received phase error signal ΦEin order to lock into the desired phase delay of the reference clock signal REF CLK. Adjustments may be made by stepping incrementally or decrementally (i.e. step 1 to step 2), but preferably adjustments are made by altering the delay code to the desired step, thereby shortening the time period for achieving phase lock.

Referring again toFIG. 1, the second output28of the VCDL20is coupled to an interface50. The interface50is configured to access the register30to read out the delay code when the phase delay is equal to the desired value. Preferably, the interface50is one of an inter-integrated circuit (I2C) interface, a Joint Test Action Group (JTAG) interface, and a System Packet Interface (SPI). The interface50outputs the delay code to ATE52having a similar interface (not shown).

The outputted delay code corresponds to the maximum speed of the chip. In Table 1, for example, a higher step required for lock indicates a faster chip. The correlation between the delay code and the actual chip speed can be determined through bench testing. Once the correlation between each step is made to a particular chip speed, the ATE52can be programmed to automatically present the chip speed to the user upon mass production tests. The resolution of the testing may be increased by the addition of more delay buffers. The system10thus exhibits repeatability and high precision speed grading, reduces test time, and may easily be ported to other processes.

FIG. 3is thus a flowchart100of a preferred embodiment of operation of the VCDL20. The VCDL20receives the reference clock signal REF CLK at step102and delays the reference clock signal REF CLK according to the delay code in the register30in order to generate the output clock signal OUT CLK at step104. If the phase delay is not equal to the predetermined value (for example, 90°) at step106, the delay code is adjusted in the register30according to the phase error signal ΦEat step108, wherein steps102-106are thereafter repeated. Once the phase delay is equal to 90°, the delay code may be output from the register30to the interface50.