Method to preserve ordering of read and write operations in a DMA system by delaying read access

A method, system and computer program product for handling write requests in a data processing system is disclosed. The method comprises receiving on an interconnect bus a first write request targeted to a first address and receiving on the interconnect bus a subsequent second write request targeted to a subsequent second address. The subsequent second write request is completed prior to completing the first write request, and, responsive to receiving a read request targeting the second address before the first write request has completed, data associated with the second address of the second write request is supplied only after the first write request completes.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates in general to data processing systems and in particular to managing memory access in data processing systems. Still more particularly, the present invention relates to a system, method and computer program product for preserving the ordering of read and write operations in a direct memory access system by delaying read access.

2. Description of the Related Art

A conventional symmetric multiprocessor (SMP) computer system, such as a server computer system, includes multiple processing units coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of volatile memory in the multiprocessor computer system and which generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be shared by one or more processor cores.

One aspect of design that affects cache performance and design complexity is the handling of writes initiated by the processor or by an alternate bus master. Because two copies of a particular piece of data or instruction code can exist, one in system memory and a duplicate copy in the cache, writes to either the system memory or the cache memory can result in an inconsistency between the contents of the two storage units. For example, consider the case in which the same data in both the cache memory and the system memory in association with a particular address. If the processor subsequently initiates a write cycle to store a new data item at the predetermined address, a cache write “hit” occurs and the processor proceeds to write the new data into the cache memory. Since the data is modified in the cache memory but not in the system memory, the cache memory and system memory become inconsistent. Similarly, in systems with an alternate bus master, direct memory access (DMA) write cycles to system memory by the alternate bus master modify data in system memory but not in the cache memory. Again, the data in the cache memory and system memory become inconsistent.

Inconsistency between data in the cache memory and data in system memory during processor writes can be prevented or handled by implementing one of several commonly employed techniques. In the first technique, a “write-through” cache guarantees consistency between the cache memory and system memory by writing the same data to both the cache memory and system memory. The contents of the cache memory and system memory are always identical, and so the two storage systems are always coherent. In a second technique, a “write back” cache handles processor writes by writing only to the cache memory and setting a “dirty” bit to indicate cache entries which have been altered by the processor. When “dirty” or altered cache entries are later replaced during a “cache replacement” cycle, the modified data is written back into system memory.

Inconsistency between data in the cache memory and corresponding data in system memory during a DMA write operation is handled somewhat differently. Depending upon the particular caching architecture employed, one of the variety of bus monitoring or “snooping” techniques may be used. One such technique involves the invalidation of cache entries which become “stale” or inconsistent with system memory after a DMA write to system memory occurs. Another technique involves the “write-back” to system memory of all dirty memory blocks within the cache memory prior to the actual writing of data by the alternate bus master. After the dirty memory blocks that are targeted by the DMA write is written back to the system memory, the memory blocks are invalidated in the cache, and the write by the alternate bus master may be performed.

As systems become larger and the latency required to resolve cache coherence increases, this latency can limit the bandwidth that a DMA device is able to achieve in the system. To sustain full DMA write throughput, the system must balance the amount of time to resolve cache coherence with the amount of data transferred per request. The traditional method of balancing time required to resolve cache coherence and the amount of data transferred per request is to design the system with a larger cache line size. Thus, with a larger cache line size, more data can be invalidated per cache line invalidation request. However, the major drawbacks of increasing the cache line size include trailing edge effects and the increased likelihood of false sharing of data within the larger cache lines.

Therefore, there is a need for an improved system and method of increasing the throughput capacity of DMA devices without increasing the size of the cache line within the cache memory.

SUMMARY OF THE INVENTION

A method, system and computer program product for handling write requests in a data processing system is disclosed. The method comprises receiving on an interconnect bus a first write request targeted to a first address and receiving on the interconnect bus a subsequent second write request targeted to a subsequent second address. The subsequent second write request is completed prior to completing the first write request, and, responsive to receiving a read request targeting the second address before the first write request has completed, data associated with the second address of the second write request is supplied only after the first write request completes.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In the present invention, DMA write requests are sent to interconnect logic upon receipt from the I/O controller or interconnect logic. If an older DMA write request receives retry response while a newer DMA write is in flight, the newer DMA write is allowed to complete, but the I/O controller issues a retry response to any subsequent read of the newer DMA write data until all older DMA writes have completed.

With reference now to the figures and, in particular, with reference toFIG. 1, there is illustrated a high level block diagram of an exemplary embodiment of a data processing system10containing a plurality of processing units100in accordance with the present invention. In the depicted embodiment, processing unit100is a single integrated circuit including two processor cores102a,102bfor independently processing instructions and data. Each processor core102includes at least an instruction sequencing unit (ISU)104for fetching and ordering instructions for execution and one or more execution units106for executing instructions. The instructions executed by execution units106may include, for example, fixed and floating point arithmetic instructions, logical instructions, and instructions that request read and write access to a memory block.

The operation of each processor core102a,102bis supported by a multi-level volatile memory hierarchy having at its lowest level one or more shared system memories132(only one of which is shown inFIG. 1) and, at its upper levels, one or more levels of cache memory. As depicted, processing unit100includes an integrated memory controller (IMC)124that controls read and write access to a system memory132in response to requests received from processor cores102a,102band operations snooped on an interconnect fabric.

In the illustrative embodiment, the cache memory hierarchy of processing unit100includes a store-through level one (L1) cache108within each processor core102a,102band a level two (L2) cache110shared by all processor cores102a,102bof the processing unit100. L2 cache110includes an L2 array and directory114, masters112and snoopers116. Masters112initiate transactions on the interconnect fabric and access L2 array and directory114in response to memory access (and other) requests received from the associated processor cores102a,102b. Snoopers116detect operations on the interconnect fabric, provide appropriate responses, and perform any accesses to L2 array and directory114required by the operations. Although the illustrated cache hierarchy includes only two levels of cache, those skilled in the art will appreciate that alternative embodiments may include additional levels (L3, L4, etc.) of on-chip or off-chip in-line or lookaside cache, which may be fully inclusive, partially inclusive, or non-inclusive of the contents the upper levels of cache.

As further shown inFIG. 1, processing unit100includes integrated interconnect logic120by which processing unit100may be coupled to the interconnect fabric as part of a larger data processing system. In the depicted embodiment, interconnect logic120supports an arbitrary number N of interconnect links121, which include in-bound and out-bound links. With these interconnect links121, each processing unit100may be coupled for bi-directional communication to up to N/2+1 other processing units100.

Each processing unit100further includes an instance of response logic122, which implements a portion of a distributed coherency signaling mechanism that maintains cache coherency between the cache hierarchy of processing unit100and those of other processing units100. Finally, each processing unit100includes an integrated I/O (input/output) controller128supporting the attachment of one or more I/O devices, such as I/O device130. I/O controller128may issue I/O read and I/O write operations and transmit data to and receive data from the local IMC124and interconnect links121in response to requests by I/O device130.

Turning now toFIG. 2, a high-level block diagram of a memory controller in accordance with the present invention is depicted. Integrated memory controller124contains dispatch logic200for routing incoming read and writes requests to a read queue202and a write queue204, respectively. Read queue202holds read requests before servicing by reference to them to system memory132. Read queue202contains several entries206a–206n, each of which has a Ttype208and an address210, regulated by a read queue control212.

Similarly, write queue204holds write requests before servicing by reference to them to system memory132. Write queue204contains several entries220a–220n, each of which has a reorder bit222, a Ttype224and an address226, regulated by a write queue control230. As will be explained below with respect toFIGS. 3–5, IMC124allows multiple DMA writes from a single I/O device130to remain ordered as observed by any potential consumer of data within data processing system10by reordering writes220a–220nthrough adjustment of reorder bit222and control of read queue202.

Referring now toFIG. 3, a high-level logical flowchart of a process by which IMC124assigns read and write requests to an appropriate queue in accordance with the present invention is illustrated. The process starts at step300and then moves to step302, which depicts dispatch logic200of integrated memory controller124determining whether or not a read-type request has been received. If not, then the process iterates at step302. If a request is received at step302, then the process next proceeds to step304. At step304, dispatch logic200of integrated memory controller124determines the Ttype (transaction type) of the request received in step302. If the request is a read-type request, the process next moves to step306, which depicts dispatch logic200of integrated memory controller124allocating an entry in read queue202to the read-type request received in step302and placing the read-type request in the allocated entry in read queue202. The process then ends at step308.

Returning to step304, if dispatch logic200of integrated memory controller124determines that the Ttype of the request received in step302is a write-type request, then the process next moves to step310. At step310, dispatch logic200of integrated memory controller124allocates an entry in write queue204to the request received in step302and places the write-type request in the allocated entry in write queue204. The process then ends at step308.

Turning now toFIG. 4, a high-level logical flowchart of a process by which read queue202services a read-type request in accordance with the preferred embodiment of the present invention is depicted. The process starts at step400and then moves to step404, which depicts read queue controller212determining whether a read-type request has been received from dispatch logic200. If no read-type request has been received, then the process iterates to step404.

If read queue controller212determines that a read-type request has been received in one of the entries206of read queue202, then the process next moves to step406, which depicts read queue controller212determining whether any pending re-ordered write request exists within write queue204having a matching request address. In one preferred embodiment, read controller212queue makes this determination by reference to comparing address field210of the read request with the address fields226of the pending write requests and by checking the reorder flag222of any matching entry. In a preferred embodiment, if no address match is found for a re-ordered write request, then the process proceeds to step408. At step408, read queue controller212performs the requested read-type operation and routes the requested data to the appropriate destination. Thereafter, at block410, read queue controller212de-allocates the entry in read queue202allocated to the read-type request. The process then ends at step412.

Returning to step406, if read queue controller212determines that any pending re-ordered write request exists within write queue204having a matching request address, the process will next proceed to step414. At step414, integrated memory controller124will provide a retry partial response to the sender of the read request, which can be any consumer of data on data processing system10.

In an alternative embodiment, at step406, if read queue controller212determines that any pending re-ordered write request exists within write queue204having a matching request address, then the process will proceed to step416. At step416, will allow read queue control212on integrated memory controller124will queue and hold the read-type request until any pending re-ordered write request that exists within write queue204having a matching request address completes. The process then moves to step408, which is described above. As will be apparent to those skilled in the art, source queuing is generally preferred in a memory system. However, those skilled in the art will realize that some specialized applications may require destination queuing, such as is indicated with respect to step416. Destination queuing, such as is indicated with respect to step416, lies within the scope and spirit of the present invention.

Turning now toFIG. 5, a high-level logical flowchart of a process by which write queue204services a write-type request in accordance with the preferred embodiment of the present invention is depicted. The process starts at step500and moves to step504. At step504, write queue controller230determines whether a write-type request has been received from dispatch logic200. If no write request is received at dispatch logic200, then the process iterates to step504.

If write queue controller230determines that a write-type request has been received from dispatch logic200, then the process next moves to step508, which depicts write queue controller230determining whether any pending re-ordered write-type request exists within write queue204having a matching request address. If write queue controller230determines that any pending re-ordered write-type request exists within write queue204having a matching request address, then the process next proceeds to step510.

At step510, write queue controller230on integrated memory controller124determines whether re-ordering is enabled by inspecting reorder bit222. If write queue controller230on integrated memory controller124determines that reorder bit222indicates re-ordering is enabled, then the process next moves to step512, which depicts write queue controller230on integrated memory controller124performing a second subsequent received write request before a first received write request. The process then ends at step514.

Returning to step508, if write queue controller230determines that no pending re-ordered write-type request exists within write queue204having a matching request address, then the process next proceeds to step516, which depicts write queue controller230determining whether the received write request is the next write-type request to be serviced. Those skilled in the art will realize that while a first-in first-out buffering and queuing system will be common in the art, alternative queuing mechanisms can be used to determine priority of fulfillment of write requests without departing from the spirit and scope of the present invention. If the write request received at step504is determined by write queue controller230to be the next to be serviced, then the process moves to step518, which depicts integrated memory controller124performing the write-type request. The process then ends at step514.

Returning to step516, if write queue controller230determines that the write request received at step504is not the next to be serviced, then the process next moves to step520, which depicts write queue controller230determining by inspecting reorder bit222of each entry220a–220nwhether there is a later-received write-type request that is to be re-ordered. If write queue controller230determines that there is no later write request to be re-ordered, then the process returns to step516. If write queue controller230determines that there is a later write request to be re-ordered, then the process proceeds to step522, which depicts write queue controller230on integrated memory controller124performing a second subsequent received write request before a first received write request. The process then returns to step516, which is described above.

An example is provided below. While the example below is explained with respect to an environment with two write requests and one read request, those skilled in the art will quickly anticipate that the present invention applies equally to any set of multiple writes and multiple reads, and that the present invention is substantially scalable. The following example of system behavior illustrates the performance of a preferred embodiment:1. DMA address A is broadcast by interconnect logic120.2. DMA address B is broadcast by interconnect logic120.3. DMA address A receives a response indicating that the operation must be retried.4. DMA address B receives a response indicating that the operation is successful.5. DMA address A is broadcast on interconnect logic120.6. DMA address A receives a response indicating that the operation is successful.

During the time required to complete step 5 and step 6, if any processor or other consumer of data attempts to read the data from DMA write to address B, I/O controller128issues a retry response to prevent the read from completing, thereby restricting read access. By allowing DMA writes to deliver data independently and enforcing coherency by restricting subsequent read access when required, the DMA write ordering rules are met without substantial negative impact to bandwidth and throughput.

While the present invention is explained with respect to an environment with two write requests and one read request, those skilled in the art will quickly anticipate that the invention applies equally to any set of multiple writes and multiple reads, and that the present invention is substantially scalable. Further, as used with respect to the present invention, the terms second and second subsequent refer to any subsequent write request without regard to how many intervening write requests have accumulated.

While the invention has been particularly shown as described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. It is also important to note that although the present invention has been described in the context of a fully functional computer system, those skilled in the art will appreciate that the mechanisms of the present invention are capable of being distributed as a program product in a variety of forms, and that the present invention applies equally regardless of the particular type of signal bearing media utilized to actually carry out the distribution. Examples of signal bearing media include, without limitation, recordable type media such as floppy disks or CD ROMs and transmission type media such as analog or digital communication links.