Solid-state imaging device and electronic apparatus

The present technology relates to a solid-state imaging device and an electronic apparatus that perform a stable overflow from a photodiode and prevent Qs from decreasing and color mixing from occurring. A solid-state imaging device according to an aspect of the present technology includes, at a light receiving surface side of a semiconductor substrate, a charge retention part that generates and retains a charge in response to incident light, an OFD into which the charge saturated at the charge retention part is discharged, and a potential barrier that becomes a barrier of the charge that flows from the charge retention part to the OFD, the OFD including a low concentration OFD and a high concentration OFD having different impurity concentrations of the same type, and the high concentration OFD and the potential barrier being formed at a distance. For example, the present technology is applicable to a CMOS image sensor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a national stage application under 35 U.S.C. 371 and claims the benefit of PCT Application No. PCT/JP2015/084783 having an international filing date of 11 Dec. 2015, which designated the United States, which PCT application claimed the benefit of Japanese Patent Application No. 2014-256043 filed 18 Dec. 2014, and Japanese Patent Application No. 2015-239945 filed 9 Dec. 2015, the disclosures of which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present technology relates to a solid-state imaging device and an electronic apparatus, and more particularly to a solid-state imaging device and an electronic apparatus that perform a stable overflow from a photodiode.

BACKGROUND ART

As a solid-state imaging device mounted in a digital still camera, a digital video camera, or the like, a CMOS (Complementary Metal Oxide Semiconductor) image sensor is known. In the CMOS image sensor (hereinafter referred to as CIS), a charge is generated in response to incident light through photoelectric conversion by a PD (Photodiode) formed for each pixel, the generated charge is transferred to an FD (Floating Diffusion) via a transfer transistor, and the charge is converted into electrical signals (pixel signals) in the FD, which are read.

Meanwhile, conventionally, a configuration, in which PDs are formed in the deep portion of (at a back surface side of) an Si (silicon) substrate, has been proposed in order to improve Qs (saturation charge amount) of the CIS, to form a vertical direction spectroscopy CIS where a plurality of PDs are laminated in the vertical direction, and the like. The charge generated and accumulated in the PD and read is transferred to the FD disposed at a front surface side of the Si substrate via a vertical transistor, for example, disposed in a direction perpendicular (vertical) to the Si substrate.

In a case of the above-described configuration, a distance between the PD and the FD is long, and the vertical transistor is fixed to a low voltage during charge accumulation in the PD. Therefore, it is difficult to design the overflow. For that reason, a structure, in which an overflow drain (hereinafter referred to as OFD) is provided at a back surface side of the Si substrate, has been proposed (see Patent Literature 1, for example).

FIG. 1shows a configuration example of a CMOS image sensor including a PD and an OFD at a back surface side of an Si substrate. It should be noted that A ofFIG. 1is a cross-sectional diagram, and B ofFIG. 1shows a potential of each part of the CIS.

A CIS10includes a PD12formed at a back surface side of (in the deep portion of) an Si substrate11, and an FD14formed at a front surface side of the Si substrate11. In addition, a vertical transistor13is formed in a direction perpendicular (vertical) to the Si substrate11. Further, an OFD16connected to the PD12via a potential barrier15is formed at the back surface side of (in the deep portion of) the Si substrate11. The OFD16includes a high concentration diffusion layer whose voltage is set at the power source voltage.

Potential levels of the PD12, the potential barrier15, and the OFD16are as shown in B ofFIG. 1. In a case where the charge generated and accumulated in the PD12are saturated, the saturated charge is discharged into the OFD16via the potential barrier15.

CITATION LIST

Patent Literature

DISCLOSURE OF INVENTION

Technical Problem

In the configuration shown in A ofFIG. 1, the potential levels of the PD12, the potential barrier15, and the OFD16are theoretically those shown in B ofFIG. 1. However, the OFD16is the high concentration diffusion layer, and the distance between the OFD16and the potential barrier15is small. Therefore, if the PD12, the potential barrier15, and the OFD16are misaligned or their impurity concentrations are different when forming them, the potential level of the potential barrier15is likely to be changed greatly. In that case, Qs may be decreased, and color mixing with adjacent pixels may occur.

The present technology is made in view of the above-mentioned circumstances, and it is an object of the present technology to perform a stable overflow from a PD and to be able to prevent Qs from decreasing and color mixing from occurring.

Solution to Problem

A solid-state imaging device according to a first aspect of the present technology includes, at a light receiving surface side of a semiconductor substrate, a charge retention part that generates and retains a charge in response to incident light, an OFD into which the charge saturated at the charge retention part is discharged, and a potential barrier that becomes a barrier of the charge that flows from the charge retention part to the OFD, the OFD including a low concentration OFD and a high concentration OFD having different impurity concentrations of the same type, and the high concentration OFD and the potential barrier being formed at a distance.

The charge retention part and the low concentration OFD may have an equal impurity concentration of the same type.

The solid-state imaging device according to the first aspect of the present technology may further include a first vertical transistor formed from a surface of the semiconductor substrate opposite to the light receiving surface and being in contact with the high concentration OFD.

The first vertical transistor and the potential barrier may be formed at a distance.

The solid-state imaging device according to the first aspect of the present technology may further include a drain layer extending in a horizontal direction from the first vertical transistor between a pixel transistor formed at the semiconductor substrate and the charge retention part.

The drain layer may be formed of a diffusion layer including impurities of the same type as the charge retention part.

The solid-state imaging device according to the first aspect of the present technology may further include a well isolation layer that electrically isolates a lower region of a predetermined pixel transistor from another region of well regions of the semiconductor substrate, and extends in a horizontal direction from the first vertical transistor.

A potential of the lower region of the predetermined pixel transistor that is electrically isolated by the well isolation layer may be lower than a potential of the other region.

The predetermined pixel transistor may be an AMP transistor and an SEL transistor.

An RST potential being an input voltage of the AMP transistor as the predetermined pixel transistor may be lower than a drain voltage of the AMP transistor.

The predetermined pixel transistor may be an RST transistor.

The solid-state imaging device according to the first aspect of the present technology may further include a second vertical transistor formed from a surface of the semiconductor substrate opposite to the light receiving surface that reads the charge from the charge retention part.

A voltage may be applied to the high concentration OFD, the voltage being higher than a voltage generated on the charge retention part when a charge is accumulated in the charge retention part.

A voltage may be applied to the high concentration OFD, the voltage being higher than a voltage generated on the charge retention part when a charge is accumulated in the charge retention part, and being supplied via a through electrode that penetrates through the semiconductor substrate from a surface opposite to the light receiving surface of the semiconductor substrate.

The through electrode may be formed for a plurality of pixels and may be shared by the plurality of pixels.

The solid-state imaging device according to the first aspect of the present technology may further include a control unit that controls a potential of the potential barrier.

The high concentration OFD may be shared by the plurality of pixels.

A plurality of layers of the charge retention part may be laminated in the semiconductor substrate.

The solid-state imaging device according to the first aspect of the present technology may further include a photoelectric conversion film formed outside the light receiving surface of the semiconductor substrate.

An electronic apparatus according to a second aspect of the present technology is an electronic apparatus on which a solid-state imaging device is mounted, the solid-state imaging device includes, at a light receiving surface side of a semiconductor substrate, a charge retention part that generates and retains a charge in response to incident light, an OFD into which the charge saturated at the charge retention part is discharged, and a potential barrier that becomes a barrier of the charge that flows from the charge retention part to the OFD, the OFD includes a low concentration OFD and a high concentration OFD having different impurity concentrations of the same type, and the high concentration OFD and the potential barrier are formed at a distance.

Advantageous Effects of Invention

According to the first aspect of the present technology, it is possible to perform a stable overflow from the charge retention part and prevent Qs from decreasing and color mixing from occurring.

According to the second aspect of the present technology, it is possible to prevent Qs from decreasing and color mixing from occurring in the solid-state imaging device.

MODE(S) FOR CARRYING OUT THE INVENTION

Hereinafter, best modes (hereinafter referred to as embodiments) for carrying out the present technology will be described with reference to the drawings.

<First Configuration Example of Solid-State Imaging Device According to Embodiment of the Present Technology>

FIG. 2is a cross-sectional block diagram showing a first configuration example of the solid-state imaging device as an embodiment of the present technology. It should be noted thatFIG. 2shows one pixel, the structural components in common with the CIS in the related art shown inFIG. 1are denoted by the same reference numerals, and thus detailed description thereof will be hereinafter omitted as appropriate.

The first configuration example of this solid-state imaging device30is a so-called back surface irradiation type CIS that has a PD (charge retention part)31formed close to a back surface of an Si substrate11, and outputs a pixel signal in response to light irradiated from a back surface side.

In the first configuration example of the solid-state imaging device30, a vertical transistor13is formed in a vertical direction (longitudinal direction) with respect to the Si substrate11, an FD14is formed at a front surface side of the Si substrate11, and a charge converted by and accumulated in the PD31is transferred to the FD14via the vertical transistor13.

For example, the PD31is an N+ region (N type, impurity concentration of 1E16 to 1E18/cm3) formed in a P type well of the Si substrate11, and is formed inside the Si substrate11at a predetermined distance from the back surface of the Si substrate11so as not to be in contact with the back surface.

In addition, in the solid-state imaging device30, a potential barrier32including an N-region (P type, impurity concentration of 1E16 to 1E18/cm3) formed adjacent to the PD31in the horizontal direction, and a low concentration OFD33including N+ region (N type, impurity concentration of 1E16 to 1E18/cm3) having the same concentration as the PD31formed adjacent to the potential barrier32in the horizontal direction. The potential control of the potential barrier32is described later with reference toFIG. 12.

Furthermore, in the solid-state imaging device30, a high concentration OFD34including a higher concentration N+ region (N type, impurity concentration of 1E18 to 1E20/cm3) than the low concentration OFD33is formed at a position spaced from the potential barrier32so as to overlap with the low concentration OFD33and to be in contact with the back surface side of the Si substrate11. The high concentration OFD34has a fixed voltage higher than the potential generated on the PD31when the charge is accumulated in the PD31(details are described later with reference toFIG. 9toFIG. 11).

FIG. 3shows the potential in the vicinity of the PD31in the first configuration example of the solid-state imaging device30. As shown inFIG. 3, the charge saturated during charge accumulation in the PD31flow to the low concentration OFD33via the potential barrier32, and is discharged into the high concentration OFD34.

<Manufacturing Method of First Configuration Example of Solid-State Imaging Device30>

Next, a method of manufacturing the first configuration example of the solid-state imaging device30is described.FIG. 4shows a manufacturing process of the first configuration example of the solid-state imaging device30.

First, N type ions are implanted into an Si thin-film (SOI)41to form the PD (charge retention part)31and the low concentration OFD33, as shown in A ofFIG. 4. Note that the PD31and the low concentration OFD33are made of the same material, and they are not distinguished and integrally formed at this stage. Next, P type ions are implanted to form the potential barrier32between the PD31and the low concentration OFD33, as shown in B ofFIG. 4. Since the potential barrier32is formed, the PD31is distinguished from the low concentration OFD33.

Next, N type ions are implanted to form the high concentration OFD34so as to overlap with the Si thin-film41and the low concentration OFD, as shown in C ofFIG. 4. At this time, the high concentration OFD34is formed at a position spaced from the potential barrier32so as to overlap with the low concentration OFD33and to be in contact with the back surface side of the Si thin film41. It should be noted that the high concentration OFD34may be formed before the potential barrier32is formed, and the potential barrier32may be formed after the high concentration OFD34is formed.

Finally, Si is epitaxially grown from the Si thin-film41, and an Si portion42is formed, as shown in D ofFIG. 4. In the Si portion42, the vertical transistor13, the FD14and the like are formed. It should be noted that P type ions may be implanted between the PD31and the back surface of the Si thin-film41.

In the first configuration example of the solid-state imaging device30produced as described above, in a case where the charge generated in the PD31is read-out, the charge is transferred to the FD14through the vertical transistor13. In addition, in a case where the charge generated in the PD31is saturated, the saturated charge flows to the low concentration OFD33via the potential barrier32, and is discharged into the high concentration OFD34.

Thus, since a route for reading out the charge is different from a route for discharging the saturated charge in the first configuration example of the solid-state imaging device30, the charge can be more stably discharged in comparison with the configuration that the charge is discharged from the same route where the charge is read-out from the PD31, for example.

In addition, since the high concentration OFD34is formed in no direct contact with the potential barrier32in the first configuration example of the solid-state imaging device30, the high concentration OFD34can be prevented from having an effect on a potential level of the potential barrier32. As a result, Qs can be prevented from decreasing, and color mixing with adjacent pixels can be prevented.

<Second Configuration Example of Solid-State Imaging Device According to Embodiment of the Present Technology>

FIG. 5is a cross-sectional block diagram showing a second configuration example of the solid-state imaging device as an embodiment of the present technology. It should be noted thatFIG. 5shows one pixel, the structural components in common with the configuration example shown inFIG. 2are denoted by the same reference numerals, and thus detailed description thereof will be hereinafter omitted as appropriate.

The second configuration example of the solid-state imaging device30is the back surface irradiation type CIS similar to the first configuration example, the high concentration OFD34of the first configuration example is omitted, and a vertical transistor (VG)51and an OFD52are provided instead.

The vertical transistor51is formed at a position that is in contact with the low concentration OFD33and is not in contact with the potential barrier32in the perpendicular direction (vertical direction) with respect to the Si substrate11. The vertical transistor51has a fixed voltage higher than the potential generated on the PD31when charge is accumulated in the PD31. The OFD52is formed at the front surface side of the Si substrate11.

FIG. 6shows the potential in the vicinity of the PD31of the second configuration example of the solid-state imaging device30.

As shown inFIG. 6, the charge saturated during charge accumulation in the PD31flows to the low concentration OFD33via the potential barrier32, and is further discharged into the OFD52via the vertical transistor51.

<Manufacturing Method of Second Configuration Example of Solid-State Imaging Device30>

Next, a method of manufacturing the second configuration example of the solid-state imaging device30is described.FIG. 7shows a manufacturing process of the second configuration example of the solid-state imaging device30.

First, N type ions are implanted into the Si thin-film (SOI)41to form the PD (charge retention part)31and the low concentration OFD33, as shown in A ofFIG. 7. Note that the PD31and the low concentration OFD33are made of the same material, and they are not distinguished and integrally formed at this stage. Next, P type ions are implanted to form the potential barrier32between the PD31and the low concentration OFD33, as shown in B ofFIG. 7. Since the potential barrier32is formed, the PD31is distinguished from the low concentration OFD33.

Finally, Si is epitaxially grown from the Si thin-film41, and the Si portion42is formed, as shown in C ofFIG. 7. In the Si portion42, the vertical transistor51, the OFD52, the vertical transistor13, the FD14and the like are formed. It should be noted that P type ions may be implanted between the PD31and the back surface of the Si thin-film41.

As described above, the second configuration example of the solid-state imaging device30can be manufactured with a smaller number of steps than those in the first configuration example.

In the second configuration example of the solid-state imaging device30produced, in a case where the charge generated in the PD31is read-out, the pixels are transferred to the FD14through the vertical transistor13. In addition, in a case where the charge generated in the PD31is saturated, the saturated charge flows to the low concentration OFD33via the potential barrier32, and is discharged into the high concentration OFD52via the vertical transistor51.

Thus, since a route for reading out the charge is different from a route for discharging the saturated charge in the second configuration example of the solid-state imaging device30, the charge can be more stably discharged in comparison with the configuration that the charge is discharged from the same route where the charge is read-out from the PD31, for example.

In addition, since the vertical transistor51is formed in no direct contact with the potential barrier32in the second configuration example of the solid-state imaging device30, a voltage applied to the vertical transistor51can be prevented from having an effect on a potential level of the potential barrier32. As a result, Qs can be prevented from decreasing, and color mixing with adjacent pixels can be prevented.

<Third Configuration Example of Solid-State Imaging Device According to Embodiment of the Present Technology>

FIG. 8is a cross-sectional block diagram showing a third configuration example of the solid-state imaging device as an embodiment of the present technology. It should be noted thatFIG. 8shows one pixel, the structural components in common with the first configuration example shown inFIG. 2or the second configuration example shown inFIG. 5are denoted by the same reference numerals, and thus detailed description thereof will be hereinafter omitted as appropriate.

In the third configuration example of the solid-state imaging device30, the vertical transistor51and the OFD52of the second configuration example are added to the first configuration example. The vertical transistor51is connected to the high concentration OFD34.

In the third configuration example of the solid-state imaging device30, in a case where the charge generated in the PD31is read-out, the charge is transferred to the FD14through the vertical transistor13. In addition, in a case where the charge generated in the PD31is saturated, the saturated charge flows to the low concentration OFD33via the potential barrier32, and is discharged into the high concentration OFD34or is discharged into the OFD52via the vertical transistor51.

Thus, since a route for reading out the charge is different from a route for discharging the saturated charge in the third configuration example of the solid-state imaging device30, the charge can be more stably discharged in comparison with the configuration that the charge is discharged from the same route where the charge is read-out from the PD31, for example.

In addition, since the high concentration OFD34and the vertical transistor51are formed in no direct contact with the potential barrier32in the third configuration example of the solid-state imaging device30, the high concentration OFD34and the vertical transistor51can be prevented from having an effect on a potential level of the potential barrier32. As a result, Qs can be prevented from decreasing, and color mixing with adjacent pixels can be prevented.

<Potential Fixing Method of High Concentration OFD34>

As described above, the high concentration OFD34into which the saturated charge generated in the PD31is discharged needs to have a fixed voltage higher than the potential generated on the PD31when the charge is accumulated in the PD31. In this regard, in a case where the electrode of the high concentration OFD34is present at the back surface side of the Si substrate11, a through electrode may be formed at the Si substrate11to electrically connect a power source at the front surface side of the Si substrate11to the high concentration OFD34.

FIG. 9is a configuration example where a through electrode is formed for each pixel. In this case, a high-voltage power source71and the high concentration OFD34are connected via wiring72, a through electrode73, and wiring74, and the high concentration OFD34has a fixed higher voltage.

FIG. 10andFIG. 11show a configuration example where a plurality of pixels share a through electrode,FIG. 10is a cross-sectional diagram, andFIG. 11is a top view. In this case, the area occupied by each pixel can be reduced by the size of the through electrodes73in comparison with the case that the through electrode73is formed for each pixel.

<Potential Control of Potential Barrier32>

Next,FIG. 12shows configuration examples that the potential of the potential barrier32is controlled. A ofFIG. 12shows a configuration example that a gate electrode81is formed at the back surface side of the Si substrate11and is connected to the potential barrier32. In this case, the potential of the potential barrier32can be controlled by applying a predetermined voltage from the gate electrode81. B ofFIG. 12shows a configuration example that a vertical transistor82is formed from the front surface side of the Si substrate11and is connected to the potential barrier32. In this case, the potential of the potential barrier32can be controlled by applying a predetermined voltage from the vertical transistor82.

<Modification Examples of First Configuration Example of Solid-State Imaging Device According to Embodiment of the Present Technology>

Next,FIG. 13andFIG. 14show a configuration example where a plurality of pixels share the high concentration OFD34,FIG. 13is a cross-sectional diagram, andFIG. 14is a top view, as a modification example (first modification example) of the first configuration example of the solid-state imaging device shown inFIG. 2. It should be noted that A ofFIG. 14and B ofFIG. 14show the case that two pixels share the high concentration OFD34, and C ofFIG. 14shows the case that four pixels share the high concentration OFD34.

Since the plurality of pixels adjacent to each other share the high concentration OFD34, the area occupied by the high concentration OFD34in each pixel can be reduced in comparison with the case that the high concentration OFD34is formed for each pixel.

FIG. 15is a cross-sectional diagram showing a configuration example that a PD91is additionally laminated in the Si substrate11as another modification example (second modification example) of the first configuration example of the solid-state imaging device.

As shown inFIG. 15, in a case where a plurality of PDs (charge retention part31and PD91) are formed in the Si substrate11, the PD31close to the back surface side mainly photoelectrically converts light of a short wavelength side, and the PD91distant from the back surface side mainly photoelectrically converts light of a long wavelength side. Since the plurality of PDs photoelectrically convert light beams having different wavelengths, a spectroscopic operation can be performed. Further, with the combination of outputs from the plurality of PDs, Qs can be increased. It should be noted that three or more PD layers may be formed in the Si substrate11.

FIG. 16is a cross-sectional diagram showing a configuration example that a photoelectric conversion film92such as an organic photoelectric conversion film is further added outside of and distant from the back surface of the Si substrate11of the second modification example ofFIG. 15as still another modification example (third modification example) of the first configuration example of the solid-state imaging device.

As shown inFIG. 16, in a case where the photoelectric conversion film92is formed, a component photoelectrically converted by the photoelectric conversion film92can be taken out as an output, and light transmitted through the photoelectric conversion film92can be photoelectrically converted by the respective PDs31,91. The plurality of PDs31,91and the photoelectric conversion film92photoelectrically convert light beams having different wavelengths, and thereby a spectroscopic operation can be performed.

<Modification Example of Second Configuration Example of Solid-State Imaging Device According to Embodiment of the Present Technology>

Next,FIG. 17shows a modification example (fourth modification example) of the second configuration example of the solid-state imaging device shown inFIG. 5.

In the fourth modification example, a photoelectric conversion film101such as an organic photoelectric conversion film is added outside of and distant from the front surface of the Si substrate11and an FD103that accumulates the charge generated by the photoelectric conversion film101is added inside of the front surface of the Si substrate11of the second configuration example ofFIG. 5.

In addition, a GND terminal105is connected to the FD103via an RST transistor104to prevent dark current flowing through the photoelectric conversion film101. It should be noted that the GND terminal105has a voltage of 0 V, but it is not limited thereto. The voltage lower than VDD is acceptable. The same applies to other configuration examples and modification examples.

Further, a drain layer106including an N type diffusion layer extending in the horizontal direction is formed between the FD103and the GND terminal105, and the charge retention part31, and is connected to the vertical transistor51.

In the fourth modification example, the drain layer106including the N type diffusion layer is turned on at all times by electric power supplied from the vertical transistor51connected to the power source. Thus, the drain layer106functions as a drain for collecting the charge leaking from the pixel transistor of the FD103and the GND terminal105, a P type well contact107and the like. As a result, an increase of dark current flowing through the charge retention part31can be inhibited. It can also be expected that the vertical transistor51to which electric power is supplied functions as a drain for collecting the leaked charge similar to the drain layer106. In a case where the vertical transistor51functions effectively as the drain, the drain layer106may be omitted.

It should be noted that the above-described fourth modification example may be applied to the third configuration example shown inFIG. 8.

<Another Modification Example of Second Configuration Example of Solid-State Imaging Device According to Embodiment of the Present Technology>

Next,FIG. 18shows another modification example (fifth modification example) of the second configuration example of the solid-state imaging device shown inFIG. 5.

In the fifth modification example, a photoelectric conversion film101such as an organic photoelectric conversion film is added outside of and distant from the front surface of the Si substrate11and an FD103that accumulates the charge generated by the photoelectric conversion film101is added inside of the front surface of the Si substrate11of the second configuration example ofFIG. 5.

In addition, a GND terminal105is connected to the FD103via an RST transistor104to prevent dark current flowing through the photoelectric conversion film101.

In the fifth modification example, an AMP transistor112and an SEL transistor113that are omitted in the above-described configuration examples and modification examples are illustrated.

In the fifth modification example, insulators111and114are formed in the Si substrate11, the AMP transistor112and the SEL transistor113being provided between the insulators111and114.

In addition, a well isolation layer115including the N type diffusion layer extending in the horizontal direction is formed below the AMP transistor112and the SEL transistor113. The well isolation layer115is extended in the horizontal direction from the vertical transistor51, and is in contact with the insulators111and114.

With such a configuration, a lower region below the AMP transistor112and the SEL transistor113is electrically isolated from the other well region (region where the RST transistor104for resetting the FD103or the like is formed), and the potential of the lower region is different from the potential of the other region. In the fifth modification example, the potential of the lower region below the AMP transistor112and the SEL transistor113is lower than the potential of the other well region.

In this manner, as a reset potential of the FD103can be arbitrarily set irrespective of the input voltage of the AMP transistor112, it can inhibit degradation of the imaging characteristics relating to random noises, a driving power (gm) and the like arising from the operation point of the AMP transistor112.

In addition, in a case where only from the viewpoint of the above-described effects obtained from the difference between the potential of the lower region below the AMP transistor112and the SEL transistor113and the potential of the region where the RST transistor104and the like are formed, the well isolation layer115does not have to be connected to the vertical transistor51. In this case, the configuration examples shown inFIG. 19toFIG. 22described below can be employed.

Specifically, in the configuration example shown inFIG. 19, the well isolation layer115is extended below the AMP transistor112and the SEL transistor113from an N type region121connected to a drain. Also in this case, since the potential of the lower region below the AMP transistor112and the SEL transistor113is lower than the potential of the other well region, the above-described effects can be obtained.

In the configuration example shown inFIG. 20, the well isolation layer115is extended below the RST transistor104from the N type region121connected to a drain. A lower region below the RST transistor104of the well regions is electrically isolated from the other well region (region where the AMP transistor112, the SEL transistor113, and the like are formed), and the potential of the lower region is different from the potential of the other region. In this case, the potential of the lower region below the RST transistor104is higher than the potential of the other well region, and the above-described effects can be obtained.

It should be noted that the fifth modification example shown ofFIG. 18may be modified similarly to the configuration example shown inFIG. 20, and the lower region below the RST transistor104may be electrically isolated from the other well region (region where the AMP transistor112, the SEL transistor113, and the like are formed) by the well isolation layer115extending from the vertical transistor51.

In the configuration example shown inFIG. 21, electrical conductivity of each semiconductor in the configuration example shown inFIG. 20is reversed. In this case, the potential of the lower region below the RST transistor104is lower than the potential of the other well region, and the above-described effects can be obtained.

In the configuration example shown inFIG. 22, the AMP transistor112and the SEL transistor113are formed of PMOS, and the N type well region is formed below the AMP transistor112and the SEL transistor113. Thus, without forming the well isolation layer115, a lower region below the AMP transistor112and the SEL transistor113is electrically isolated from the other well region where the RST transistor104and the like are formed, and the potential of the lower region is different from the potential of the other region. In this case, the potential of the lower region below the AMP transistor112and the SEL transistor113is higher than the potential of the other well region, the above-described effects can be obtained.

<Still Another Modification Example of Second Configuration Example of Solid-State Imaging Device According to Embodiment of the Present Technology>

Next,FIG. 23shows still another modification example (sixth modification example) of the second configuration example of the solid-state imaging device shown inFIG. 5. Specifically, the fourth modification example shown inFIG. 17is combined with the fifth modification example shown inFIG. 18.FIG. 24is a top view of the sixth modification example shown inFIG. 23.

In the sixth modification example, by turning on the drain layer106at all times with electricity from the vertical transistor51connected to the power source, the drain layer106functions as a drain for collecting the charge leaking from the FD103and the GND terminal105. As a result, an increase of dark current flowing through the charge retention part31can be inhibited.

Further, the well isolation layer115electrically isolates the lower region below the AMP transistor112and the SEL transistor113of the well regions from the other well region, and the potential of the lower region is different from the potential of the other region. In this manner, as the reset potential of the FD103can be arbitrarily set irrespective of the input voltage of the AMP transistor112, it inhibits degradation of the imaging characteristics relating to random noises and a driving power (gm) arising from the operation point of the AMP transistor112.

It should be noted that the above-described sixth modification example may be applied to the third configuration example shown inFIG. 8.

Next,FIG. 25is a top view showing a configuration example where a plurality of pixels share the vertical transistor51in the sixth modification example shown inFIG. 23. In this case, the area occupied by each pixel can be reduced in comparison with the case that the vertical transistor51is formed for each pixel.

FIG. 26is a diagram showing a usage example that uses the solid-state imaging device30according to an embodiment of the present technology.

The solid-state imaging device30can be used in various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays as follows.An apparatus for photographing images to be viewed, such as a digital camera and a camera-equipped mobile apparatusAn apparatus used for traffic purposes, such as a car-mounted sensor that photographs front/rear/periphery/inside of an automobile, a surveillance camera that monitors running vehicles and roads, and a distance measurement sensor that measures distances among vehicles, for safe driving including automatic stop, recognition of a driver's state, and the likeAn apparatus used in home electronics such as a TV, a refrigerator, and an air conditioner, for photographing gestures of users and executing apparatus operations according to the gesturesAn apparatus used for medical and healthcare purposes, such as an endoscope and an apparatus that performs blood vessel photographing by receiving infrared lightAn apparatus used for security purposes, such as a surveillance camera for crime-prevention purposes and a camera for person authentication purposesAn apparatus used for beauty care purposes, such as a skin measurement apparatus that photographs skins and a microscope that photographs scalpsAn apparatus used for sports purposes, such as an action camera and a wearable camera for sports purposesAn apparatus for agriculture purposes, such as a camera for monitoring a state of fields and crops

It should be noted that the embodiments of the present technology are not limited to the above-described examples and that various variations or modifications are possible without departing from the spirit and scope of the present technology.

The present technology may also have the following configurations.

at a light receiving surface side of a semiconductor substrate,

a charge retention part that generates and retains a charge in response to incident light;

an OFD into which the charge saturated at the charge retention part is discharged; and

a potential barrier that becomes a barrier of the charge that flows from the charge retention part to the OFD,

the OFD including a low concentration OFD and a high concentration OFD having different impurity concentrations of the same type, and

the high concentration OFD and the potential barrier being formed at a distance.

(2) The solid-state imaging device according to (1), in which

the charge retention part and the low concentration OFD have an equal impurity concentration of the same type.

(3) The solid-state imaging device according to (1) or (2), further including:

a first vertical transistor formed from a surface of the semiconductor substrate opposite to the light receiving surface and being in contact with the high concentration OFD.

(4) The solid-state imaging device according to (3), in which

the first vertical transistor and the potential barrier are formed at a distance.

(5) The solid-state imaging device according to (3), further including:

a drain layer extending in a horizontal direction from the first vertical transistor between a pixel transistor formed at the semiconductor substrate and the charge retention part.

(6) The solid-state imaging device according to (5), in which

the drain layer is formed of a diffusion layer including impurities of the same type as the charge retention part.

(7) The solid-state imaging device according to any of (3) to (6), further including:

a well isolation layer that electrically isolates a lower region of a predetermined pixel transistor from another region of well regions of the semiconductor substrate, and extends in a horizontal direction from the first vertical transistor.

(8) The solid-state imaging device according to (7), in which

a potential of the lower region of the predetermined pixel transistor that is electrically isolated by the well isolation layer is lower than a potential of the other region.

(9) The solid-state imaging device according to (7) or (8), in which

the predetermined pixel transistor is an AMP transistor and an SEL transistor.

(10) The solid-state imaging device according to (9), in which

an RST potential being an input voltage of the AMP transistor as the predetermined pixel transistor is lower than a drain voltage of the AMP transistor.

(11) The solid-state imaging device according to (7), in which

the predetermined pixel transistor is an RST transistor.

(12) The solid-state imaging device according to any of (1) to (11), further including:

a second vertical transistor formed from a surface of the semiconductor substrate opposite to the light receiving surface that reads the charge from the charge retention part.

(13) The solid-state imaging device according to any of (1) to (12), in which

a voltage is applied to the high concentration OFD, the voltage being higher than a voltage generated on the charge retention part when a charge is accumulated in the charge retention part.

(14) The solid-state imaging device according to any of (1) to (13), in which

a voltage is applied to the high concentration OFD, the voltage being higher than a voltage generated on the charge retention part when a charge is accumulated in the charge retention part, and being supplied via a through electrode that penetrates through the semiconductor substrate from a surface opposite to the light receiving surface of the semiconductor substrate.

(15) The solid-state imaging device according to (14), in which

the through electrode is formed for a plurality of pixels and is shared by the plurality of pixels.

(16) The solid-state imaging device according to any of (1) to (15), further including:

a control unit that controls a potential of the potential barrier.

(17) The solid-state imaging device according to any of (1) to (16), in which

the high concentration OFD is shared by the plurality of pixels.

(18) The solid-state imaging device according to any of (1) to (17), in which

a plurality of layers of the charge retention part are laminated in the semiconductor substrate.

(19) The solid-state imaging device according to any of (1) to (18), further including:

a photoelectric conversion film formed outside the light receiving surface of the semiconductor substrate.

(20) An electronic apparatus on which a solid-state imaging device is mounted,

the solid-state imaging device including:

at a light receiving surface side of a semiconductor substrate,a charge retention part that generates and retains a charge in response to incident light;an OFD into which the charge saturated at the charge retention part is discharged; anda potential barrier that becomes a barrier of the charge that flows from the charge retention part to the OFD,the OFD including a low concentration OFD and a high concentration OFD having different impurity concentrations of the same type, andthe high concentration OFD and the potential barrier being formed at a distance.

REFERENCE SIGNS LIST