Imaging device

An imaging device includes: a first unit pixel cell including a first electrode, a second electrode facing the first electrode, a first photoelectric conversion layer between the first electrode and the second electrode, the first photoelectric conversion layer generating first signal charge, and a first signal detection circuit connected to the first electrode, the first signal detection circuit detecting the first signal charge; and a voltage supply circuit. The voltage supply circuit supplies a first voltage to the second electrode during a first period when the first unit pixel cell accumulates the first signal charge. The voltage supply circuit supplies a second voltage to at least one of the first electrode and the second electrode during a second period other than the first period, the second period including a first moment at which a difference in potential between the first electrode and the second electrode is zero.

BACKGROUND

1. Technical Field

The present disclosure relates to an imaging device.

2. Description of the Related Art

Imaging elements that include an organic photoelectric conversion layer have been developed. Japanese Unexamined Patent Application Publication No. 2013-84789 discloses that after-image is likely to occur when high-luminance light enters an organic photoelectric conversion layer (hereinafter, this phenomenon is referred to simply as “high-luminance after-image”) because signal charge generated in the organic photoelectric conversion layer migrates inside the organic photoelectric conversion layer at a low speed. After-image is caused by the generation of residual charge. For limiting the generation of residual charge, it is desirable not to arrange wires immediately below the gaps between pixel electrodes. Not arranging wires immediately below the gaps between pixel electrodes increases the strength of the electric field oriented toward the pixel electrodes in portions of the organic photoelectric conversion layer which correspond to the gaps between the pixel electrodes. This reduces the amount of time required for the signal charge being collected by the pixel electrodes and the occurrence of high-luminance after-image.

SUMMARY

A reduction in the occurrence of high-luminance after-image in imaging elements has been anticipated.

One non-limiting and exemplary embodiment provides an imaging device comprising: one or more unit pixel cells including a first unit pixel cell, the first unit pixel cell including a first electrode, a second electrode facing the first electrode, a first photoelectric conversion layer between the first electrode and the second electrode, the first photoelectric conversion layer generating first signal charge, and a first signal detection circuit connected to the first electrode, the first signal detection circuit detecting the first signal charge; and a voltage supply circuit. The voltage supply circuit supplies a first voltage to the second electrode during a first period when the first unit pixel cell accumulates the first signal charge. The voltage supply circuit supplies a second voltage to at least one of the first electrode and the second electrode during a second period other than the first period, the second period including a first moment at which a difference in potential between the first electrode and the second electrode is zero.

It should be noted that general or specific embodiments may be implemented as an element, a device, an apparatus, a system, an integrated circuit, and a method, a computer program, or any selective combination thereof.

DETAILED DESCRIPTION

The imaging element disclosed in Japanese Unexamined Patent Application Publication No. 2013-84789 employs a structure in which wires are not disposed below the gaps between the adjacent pixel electrodes in order to increase the strength of the electric field oriented toward the pixel electrodes. However, this structure increases the electric field in only regions of the organic photoelectric conversion layer which are located in the vicinity of the gaps between the pixel electrodes, and does not always reduce the amount of time required for all the signal charge carriers generated in the organic photoelectric conversion layer being collected by the pixel electrodes. Furthermore, arranging wires in the above-described manner poses a limitation on the positions of wires and reduces the degree of flexibility in the design of an imaging element.

The inventor of the present invention focused on the fact that electron-hole pairs generated by an organic photoelectric conversion layer being irradiated with light are separated into holes and electrons upon a voltage being applied to the organic photoelectric conversion layer, and the electrons or holes are detected as signal charge. As a result, the inventor conceived that the signal charge carriers, which are holes or electrons generated in the organic photoelectric conversion layer, may be recombined with electrons or holes, that is, eliminated, when the difference in potential applied to the organic photoelectric conversion layer is set to be zero.

On the basis of the above findings, the inventor of the present invention conceived a novel imaging device that includes an organic photoelectric conversion layer. The summary of an aspect of the present disclosure is described below.[1] An imaging device including:

one or more unit pixel cells including a first unit pixel cell, the first unit pixel cell includinga first electrode,a second electrode facing the first electrode,a first photoelectric conversion layer between the first electrode and the second electrode, the first photoelectric conversion layer generating first signal charge, anda first signal detection circuit connected to the first electrode, the first signal detection circuit detecting the first signal charge; and

a voltage supply circuit, wherein

the voltage supply circuit supplies a first voltage to the second electrode during a first period when the first unit pixel cell accumulates the first signal charge, and

the voltage supply circuit supplies a second voltage to at least one of the first electrode and the second electrode during a second period other than the first period, the second period including a first moment at which a difference in potential between the first electrode and the second electrode is zero.[2] The imaging device described in [1], comprising a first controller that causes the voltage supply circuit to supply the first voltage and the second voltage.[3] The imaging device described in [1] or [2], wherein the first photoelectric conversion layer includes an organic semiconductor material.[4] The imaging device described in any one of [1]-[3], wherein the second voltage changes in the second period.[5] The imaging device described in any one of [1]-[4], wherein

the one or more unit pixel cells includes a second unit pixel cell, the second unit pixel cell includinga third electrode,a fourth electrode facing the third electrode,a second photoelectric conversion layer between the third electrode and the fourth electrode, the second photoelectric conversion layer generating second signal charge, anda second signal detection circuit connected to the third electrode, the second signal detection circuit detecting the second signal charge,

the voltage supply circuit supplies the first voltage to the fourth electrode during a third period when the second unit pixel cell accumulates the second signal charge,

the voltage supply circuit supplies the second voltage to at least one of the third electrode and the fourth electrode during the second period, the second period including a second moment at which a difference in potential between the third electrode and the fourth electrode is zero, and

timing of the first moment in a frame period is different from timing of the second moment in the frame period.[6] The imaging device described in [5], wherein the second photoelectric conversion layer includes an organic semiconductor material.[7] The imaging device described in any one of [1]-[6], wherein

the first period and the second period are included in a frame period, and

the second period divides the first period into two separate periods.[8] The imaging device described in any one of [1]-[7], wherein

the one or more unit pixel cells are arranged in a two-dimensional array having rows and columns,

the one or more unit pixel cells include a second unit pixel cell, the second unit pixel cell includinga third electrode,a fourth electrode facing the third electrode,a second photoelectric conversion layer between the third electrode and the fourth electrode, the second photoelectric conversion layer generating second signal charge, anda second signal detection circuit connected to the third electrode, the second signal detection circuit detecting the second signal charge,

a row in which the first unit pixel cell is located is different from a row in which the second unit pixel cell is located, and

the first signal detection circuit outputs a signal of the first unit pixel cell at first timing in a frame period, the second signal detection circuit outputting a signal of the second unit pixel cell at second timing different from the first timing in the frame period.[9] The imaging device described in [8], comprising a second controller that causes the first signal detection circuit to output the signal of the first unit pixel cell, and causes the second signal detection circuit to output the signal of the second unit pixel cell.[10] An imaging device including:

a plurality of unit pixels arranged in a two-dimensional array; and

a driving unit that drives the plurality of unit pixels in a rolling shutter mode during imaging,

the plurality of unit pixels each includinga photoelectric conversion layer having first and second surfaces on opposite sides thereof and including an organic semiconductor material,a first electrode disposed on the first surface,a second electrode disposed on the second surface, anda signal detection circuit connected to the first electrode, the signal detection circuit detecting signal charge generated in the photoelectric conversion layer,

the driving unit changing a voltage applied to at least one of the first electrode and the second electrode during a predetermined period at least once every N frames such that the potential of the first electrode changes from the potential applied during imaging to a ground level, the predetermined period including a timing at which the difference in potential between the first electrode and the second electrode is zero.

The imaging device described in [10] may reduce the occurrence of high-luminance after-image while maintaining the degree of flexibility in the arrangement of wires in the unit pixels.[11] The imaging device described in [10], wherein the driving unit changes a voltage applied to at least one of the first electrode and the second electrode of each of the plurality of unit pixels.

The imaging device described in [11] may enable the occurrence of high-luminance after-image to be reduced at a high speed.[12] The imaging device described in [10] or [11], wherein

the plurality of unit pixels include first and second pixels, and

the timing at which the difference in potential between the first electrode and the second electrode of the first pixel is zero during the predetermined period and the timing at which the difference in potential between the first and second electrodes of the second pixel is zero during the predetermined period are different from each other.

The imaging device described in [12] may reduce the occurrence of high-luminance after-image even during the exposure period.[13] The imaging device described in any one of [10]-[12], wherein the driving unit sets the predetermined period to be included in a period during which the plurality of unit pixels are exposed to light.

Embodiments of the present disclosure are described below in detail with reference to the attached drawings. In the following embodiments, general or specific examples are described. All the values, shapes, materials, components, the arrangement of the components, and the connection between the components, steps, and the order of the steps described in the following embodiments are merely an example and are not intended to limit the scope of the present disclosure. The various aspects described herein may be combined with one another unless a contradiction arises. Among the components described in the following embodiments, components that are not described in any one of the independent claims, which indicate the broadest concepts, are described as optional components. In the following description, components that have substantially the same function are denoted by the same reference numeral, and the description thereof may be omitted.

Circuit Structure of Imaging device

FIG. 1is an exemplary circuit structure of an imaging device according to an embodiment of the present disclosure. The imaging device100illustrated inFIG. 1includes a pixel array PA that includes a plurality of unit pixels10arranged in a two-dimensional array.FIG. 1schematically illustrates an example where the unit pixels10are arranged in a matrix having two rows and two columns. Needless to say that the number and arrangement of the unit pixels10included in the imaging device100are not limited to those in the example illustrated inFIG. 1.

The unit pixels10each include a photoelectric conversion unit13and a signal detection circuit14. As described below with reference to the drawings, the photoelectric conversion unit13includes two electrodes facing each other and a photoelectric conversion layer interposed therebetween and generates a signal upon receiving incident light. The photoelectric conversion unit13is not necessarily an element in which all the components are exclusively provided for each of the unit pixels10. For example, some of the components of the photoelectric conversion unit13may extend across the plurality of unit pixels10. The signal detection circuit14is a circuit that detects the signal generated by the photoelectric conversion unit13. In this example, the signal detection circuit14includes a signal detection transistor24and an address transistor26. The signal detection transistor24and the address transistor26are typically field-effect transistors (FETs). In the following description, the signal detection transistor24and the address transistor26are N-channel MOS transistors.

As described schematically inFIG. 1, the control terminal (i.e., the gate) of the signal detection transistor24is electrically connected to the photoelectric conversion unit13. The signal charge carriers (i.e., holes or electrons) generated by the photoelectric conversion unit13are accumulated at a charge accumulation node41(also referred to as “floating diffusion node”), which is located between the gate of the signal detection transistor24and the photoelectric conversion unit13. The detailed structure of the photoelectric conversion unit13is described below.

The imaging device100includes a driving unit in order to drive the pixel array PA in a rolling shutter mode. The driving unit includes a voltage supply circuit32, a reset voltage source34, a vertical scanning circuit36, a column-signal processing circuit37, and a horizontal-signal readout circuit38. The driving unit may include a controller that controls the voltage supply circuit32, the reset voltage source34, the vertical scanning circuit36, the column-signal processing circuit37, and the horizontal-signal readout circuit38.

The photoelectric conversion unit13included in each unit pixel10is further connected to the corresponding one of voltage control lines42. In the example structure illustrated inFIG. 1, the voltage control lines42are connected to the voltage supply circuit32. The voltage supply circuit32applies different voltages to the counter electrodes12during the exposure period and the after-image reduction period. The term “exposure period” used herein refers to a period during which positive or negative charge (i.e., signal charge) generated by photoelectric conversion is accumulated at the charge accumulation regions. This period may also be referred to as “charge accumulation period”. The term “after-image reduction period” and “high-luminance after-image resetting period” used herein refer to a predetermined period in which a voltage of the first electrode, which is applied from the voltage supply circuit32, changes so as to include timing at which the difference in potential between the first and second electrodes is zero. It is noted that the predetermined voltage is between a ground voltage and a voltage of the first electrode in operation. The voltage supply circuit32is not limited to a specific power source circuit. The voltage supply circuit32may be a circuit that generates a predetermined voltage or a circuit that converts a voltage supplied from another power source into a predetermined voltage.

The unit pixels10are each connected to a power source line40, through which a power source voltage VDD is supplied. As illustrated inFIG. 1, the power source line40is connected to the input terminal (typically, the drain) of the signal detection transistor24. The power source line40serves as a source-follower power source, which enables the signal detection transistor24to amplify the signal generated by the photoelectric conversion unit13and output the amplified signal.

The output terminal (i.e., the source) of the signal detection transistor24is connected to the input terminal (i.e., the drain) of the address transistor26. The output terminal (i.e., the source) of the address transistor26is connected to the corresponding one of a plurality of vertical signal lines47, which are provided for the respective columns of the pixel array PA. The control terminal (i.e., the gate) of the address transistor26is connected to the corresponding one of address control lines46. Controlling the potentials of the address control lines46enables the data output from the signal detection transistors24to be each selectively read out through the corresponding one of the vertical signal lines47.

In the example illustrated inFIG. 1, the address control lines46are connected to a vertical scanning circuit36(also referred to as “row scanning circuit”). The vertical scanning circuit36selects a plurality of the unit pixels10disposed in each row on a row-by-row basis by applying a predetermined voltage to the corresponding one of the address control lines46. This enables the signals to be read out from the selected unit pixels10and enables the pixel electrodes to be reset as described below.

The vertical signal lines47are main signal lines through which pixel signals output from the pixel array PA are transmitted to the peripheral circuits. The vertical signal lines47are each connected to the corresponding one of column-signal processing circuits37(also referred to as “row-signal accumulation circuits”). The column-signal processing circuits37perform noise-reduction signal processing such as correlated double sampling, analog-digital conversion (AD conversion), and the like. As illustrated inFIG. 1, the column-signal processing circuits37are provided for the respective columns of the unit pixels10in the pixel array PA. The column-signal processing circuits37are connected to a horizontal signal readout circuit38(also referred to as “column-scanning circuit”), which sequentially reads a signal from each of the column-signal processing circuits37to a horizontal common signal line49.

In the example structure illustrated inFIG. 1, the unit pixels10each include a reset transistor28. The reset transistor28may be a field-effect transistor or the like, similarly to the signal detection transistor24and the address transistor26. In the example described below, the reset transistor28is an N-channel MOS transistor unless otherwise specified. As illustrated inFIG. 1, the reset transistor28is connected to a reset voltage line44, through which a reset voltage Vr is supplied, and to the charge accumulation node41. The control terminal (i.e., the gate) of the reset transistor28is connected to the corresponding one of reset control lines48, and the potential of the charge accumulation node41is reset to the reset voltage Vr by controlling the potential of the reset control line48. In this example, the reset control lines48are connected to the vertical scanning circuit36. Thus, it is possible to reset a plurality of the unit pixels10which are disposed in each row on a row-by-row basis by the vertical scanning circuit36applying a predetermined voltage to the corresponding one of the reset control lines48.

In this example, the reset voltage line44, through which the reset voltage Vr is supplied to the reset transistors28, is connected to a reset-voltage supply circuit34(hereinafter, referred to simply as “reset voltage source”). The reset voltage source34may have any structure that allows a predetermined reset voltage Vr to be supplied through the reset voltage line44during the operation of the imaging device100and is not limited to a specific power source circuit, similarly to the voltage supply circuit32described above. The voltage supply circuit32and the reset voltage source34may be parts of a single voltage supply circuit or independent voltage supply circuits. One or both of the voltage supply circuit32and the reset voltage source34may be a part of the vertical scanning circuit36. Alternatively, a sensitivity control voltage may be supplied from the voltage supply circuit32to the unit pixels10via the vertical scanning circuit36, and/or the reset voltage Vr may be supplied from the reset voltage source34to the unit pixels10via the vertical scanning circuit36.

The power source voltage VDD supplied to the signal detection circuits14may be used as a reset voltage Vr. In such a case, the reset voltage source34may also be used as a voltage supply circuit (not illustrated inFIG. 1) that supplies a power source voltage to the unit pixels10. Furthermore, it is possible to use the power source line40as the reset voltage line44, which allows the arrangement of wires in the pixel array PA to be simplified. However, setting the reset voltage Vr to be different from the power source voltage VDD supplied to the signal detection circuits14increases the degree of flexibility in the control of the imaging device100.

Device Structure of Unit Pixel

FIG. 2schematically illustrates an exemplary device structure of the unit pixels10. In the exemplary structure illustrated inFIG. 2, the above-described signal detection transistor24, the address transistor26, and the reset transistor28are disposed on a semiconductor substrate20. The semiconductor substrate20is not limited to a substrate the entirety of which is composed of a semiconductor and may be an insulating substrate that includes a semiconductor layer on a surface thereof, the surface being on the same side as the photoelectric conversion unit13. In the example described below, a p-type silicon (Si) substrate is used as a semiconductor substrate20.

The semiconductor substrate20includes impurity regions (in this example, n-type regions)26s,24s,24d,28d, and28s. The semiconductor substrate20also includes element separation regions20tin order to electrically separate the unit pixels10from one another. In this example, an element separation region20tis also interposed between the impurity regions24dand28d. For forming the element separation regions20t, for example, the injection of acceptor ions may be performed under predetermined injection conditions.

The impurity regions26s,24s,24d,28d, and28sare typically diffusion layers formed in the semiconductor substrate20. As schematically illustrated inFIG. 2, the signal detection transistor24includes impurity regions24sand24dand a gate electrode24g(typically, a polysilicon electrode). The impurity region24sserves as, for example, the source region of the signal detection transistor24. The impurity region24dserves as, for example, the drain region of the signal detection transistor24. The channel region of the signal detection transistor24is formed between the impurity regions24sand24d.

Similarly to the signal detection transistor24, the address transistor26includes impurity regions26sand24sand a gate electrode26g(typically, a polysilicon electrode), which is connected to the corresponding one of the address control lines46(seeFIG. 1). In this example, the signal detection transistor24and the address transistor26are electrically connected to each other by sharing the impurity region24s. The impurity region26sserves as, for example, the source region of the address transistor26. The impurity region26sis connected to the corresponding one of vertical signal lines47, which is not illustrated inFIG. 2(seeFIG. 1).

The reset transistor28includes impurity regions28dand28sand a gate electrode28g(typically, a polysilicon electrode) connected to the corresponding one of reset control lines48(seeFIG. 1). The impurity region28sserves as, for example, the source region of the reset transistor28. The impurity region28sis connected to the reset voltage line44, which is not illustrated inFIG. 2(seeFIG. 1).

An interlayer insulating layer50(typically, a silicon dioxide layer) is disposed on the semiconductor substrate20so as to cover the signal detection transistor24, the address transistor26, and the reset transistor28. The interlayer insulating layer50may include a wiring layer56formed therein as illustrated inFIG. 2. The wiring layer56is typically composed of a metal such as copper and may include wires such as the vertical signal lines47described above. The number of insulating sublayers constituting the interlayer insulating layer50and the number of sublayers constituting the wiring layer56formed in the interlayer insulating layer50may be set appropriately and not limited to those in the example illustrated inFIG. 2.

The above-described photoelectric conversion unit13is disposed on the interlayer insulating layer50. In other words, in an embodiment of the present disclosure, a plurality of unit pixels10constituting a pixel array PA (seeFIG. 1) are formed on the semiconductor substrate20. The unit pixels10, which are arranged on the semiconductor substrate20in a two-dimensional array, form a photosensitive region (i.e., a pixel region). The distance (i.e., pixel pitch) between a pair of adjacent unit pixels10may be about 2 μm.

The photoelectric conversion unit13includes a pixel electrode11(i.e., a first electrode), a counter electrode12(i.e., a second electrode), and a photoelectric conversion layer15interposed therebetween. In this example, the counter electrode12and the photoelectric conversion layer15are formed so as to extend across a plurality of the unit pixels10, while each of the unit pixels10is provided with one pixel electrode11. Each of the pixel electrodes11is electrically separated from other pixel electrodes11included in the adjacent unit pixels10by being spatially separated from them.

The counter electrode12is typically a transparent electrode composed of a transparent conducting material. The counter electrode12is disposed on a side of the photoelectric conversion layer15on which light enters. That is, light that have transmitted through the counter electrode12enters the photoelectric conversion layer15. The wavelength of light that can be detected by the imaging device100is not limited to be within the wavelength range of visible light (e.g., 380 nm or more and 780 nm or less). The term “transparent” used herein refers to passing at least part of light having a wavelength that falls within the detectable wavelength range, and it is not always necessary to pass light having any wavelength that falls within the wavelength range of the visible light. Hereinafter, all electromagnetic waves including infrared radiation and ultraviolet radiation are comprehensively referred to as “light” for the sake of convenience. The counter electrode12may be composed of a transparent conducting oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminium-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), SnO2, TiO2, or ZnO2.

The photoelectric conversion layer15generates electron-hole pairs upon receiving the incident light. The photoelectric conversion layer15is typically composed of an organic semiconductor material. Specific examples of the material of the photoelectric conversion layer15are described below.

As described above with reference toFIG. 1, the counter electrode12is connected to the corresponding one of the voltage control lines42, which are connected to the voltage supply circuit32. In this example, the counter electrode12is formed so as to extend across a plurality of the unit pixels10. This enables the voltage supply circuit32to apply a desired sensitivity control voltage to a plurality of the unit pixels10at a time through the voltage control lines42. Each of the unit pixels10may be provided with one counter electrode12when a desired sensitivity control voltage can be applied from the voltage supply circuit32. Similarly, each of the unit pixels10may be provided with one photoelectric conversion layer15.

Controlling the potential of the counter electrode12with respect to the pixel electrode11enables holes or electrons of the electron-hole pairs generated in the photoelectric conversion layer15due to photoelectric conversion to be collected by the pixel electrode11. For example, in the case where holes are used as signal charge carriers, controlling the potential of the counter electrode12to be higher than that of the pixel electrode11enables the holes to be selectively collected by the pixel electrode11. In the example described below, holes are used as signal charge carriers. Needless to say that electrons may alternatively be used as signal charge carriers.

The pixel electrode11, which faces the counter electrode12, collects positive or negative charge generated in the photoelectric conversion layer15due to photoelectric conversion, by applying an appropriate bias voltage between the counter electrode12and the pixel electrode11. The pixel electrode11is composed of a metal such as aluminium or copper, a nitride of the metal, or a polysilicon or the like which has conductivity by being doped with an impurity.

The pixel electrode11may have a light-blocking property. When the pixel electrode11is, for example, a TaN electrode having a thickness of 100 nm, the pixel electrode11may have a sufficient light-blocking property. Using an electrode having a light-blocking property as a pixel electrode11may reduce the intrusion of light that transmits through the photoelectric conversion layer15into the channel regions or the impurity regions of the transistors formed on the semiconductor substrate20, which are at least one of the signal detection transistor24, the address transistor26, and the reset transistor28in this example. A light-blocking film may optionally be formed in the interlayer insulating layer50by using the wiring layer56described above. Reducing the intrusion of the light into the channel regions of the transistors formed on the semiconductor substrate20may limit a shift of the properties of the transistors (e.g., the fluctuations in threshold voltage). Reducing the intrusion of the light into the impurity regions formed on the semiconductor substrate20may limit the mixing of noises unintendedly generated by photoelectric conversion occurring in the impurity regions. Thus, reducing the intrusion of the light into the semiconductor substrate20increases the reliability of the imaging device100.

As schematically illustrated inFIG. 2, the pixel electrode11is connected to the gate electrode24gof the signal detection transistor24with a plug52, a wire53, and a contact plug54. In other words, the gate of the signal detection transistor24is electrically connected with the pixel electrode11. The plug52and the wire53may be composed of a metal such as copper. The plug52, the wire53, and the contact plug54constitute at least a part of the charge accumulation node41(seeFIG. 1), which is located between the signal detection transistor24and the photoelectric conversion unit13. The wire53may constitute a part of the wiring layer56. The pixel electrode11is also connected to the impurity region28dwith the plug52, the wire53, and a contact plug55. In the exemplary structure illustrated inFIG. 2, the gate electrode24gof the signal detection transistor24, the plug52, the wire53, the contact plugs54and55, and the impurity region28d, which serves as a source or drain region of the reset transistor28, function as a charge accumulation region where the signal charge collected by the pixel electrode11is accumulated.

Upon the signal charge being collected by the pixel electrode11, a voltage correspondent to the amount of signal charge accumulated at the charge accumulation region is applied to the gate of the signal detection transistor24. The signal detection transistor24amplifies the voltage. The voltage amplified by the signal detection transistor24is selectively read out as a signal voltage via the address transistor26.

Photoelectric Conversion Layer

An example of the photoelectric conversion layer15is described below.

The photoelectric conversion layer15typically includes a semiconductor material. In the example described below, an organic semiconductor material is used as a semiconductor material.

The photoelectric conversion layer15includes, for example, tin naphthalocyanine represented by General Formula (1) below (hereinafter, this tin naphthalocyanine is referred to simply as “tin naphthalocyanine”).

In General Formula (1), R1to R24each independently represent a hydrogen atom or a substituent group. The substituent group is not limited to a specific substituent group and may be selected from the following: a heavy hydrogen atom, a halogen atom, an alkyl group (including a cycloalkyl group, a bicycloalkyl group, and a tricycloalkyl group), an alkenyl group (including a cycloalkenyl group and a bicycloalkenyl group), an alkynyl group, an aryl group, a heterocyclic group, a cyano group, a hydroxy group, a nitro group, a carboxy group, an alkoxy group, an aryloxy group, a silyloxy group, a heterocyclic oxy group, an acyloxy group, a carbamoyloxy group, an alkoxycarbonyloxy group, an aryloxycarbonyloxy group, an amino group (including an anilino group), an ammonio group, an acylamino group, an aminocarbonylamino group, an alkoxycarbonylamino group, an aryloxycarbonylamino group, a sulfamoylamino group, an alkylsulfonylamino group, an arylsulfonylamino group, a mercapto group, an alkylthio group, an arylthio group, a heterocyclic thio group, a sulfamoyl group, a sulfo group, an alkylsulfinyl group, an arylsulfinyl group, an alkylsulfonyl group, an arylsulfonyl group, an acyl group, an aryloxycarbonyl group, an alkoxycarbonyl group, a carbamoyl group, an arylazo group, a heterocyclic azo group, an imido group, a phosphino group, a phosphinyl group, a phosphinyloxy group, a phosphinylamino group, a phosphono group, a silyl group, a hydrazino group, a ureide group, a boronic acid group (—B(OH)2), a phosphate group (—OPO(OH)2), a sulfate group (—OSO3H), and other known substituent groups.

The tin naphthalocyanine represented by General Formula (1) above may be a commercially available one. Alternatively, the tin naphthalocyanine represented by General Formula (1) above may be synthesized, for example, by using the naphthalene derivative represented by General Formula (2) below as a starting material as described in Japanese Unexamined Patent Application Publication No. 2010-232410. The substituent groups represented by R25to R30in General Formula (2) may be the same as those represented by R1to R24in General Formula (1).

In the tin naphthalocyanine represented by General Formula (1) above, it is advantageous that 8 or more of R1to R24are a hydrogen atom or a heavy hydrogen atom, it is more advantageous that 16 or more of R1to R24are a hydrogen atom or a heavy hydrogen atom, and it is further advantageous that all of R1to R24are a hydrogen atom or a heavy hydrogen atom in terms of ease of control of cohesion of the molecules. The tin naphthalocyanine represented by Formula (3) below is advantageous in terms of ease of synthesis.

The tin naphthalocyanine represented by General Formula (1) above absorbs light having a wavelength of about 200 nm or more and 1100 nm or less. For example, the tin naphthalocyanine represented by Formula (3) has an absorption peak at a wavelength of about 870 nm as illustrated inFIG. 3.FIG. 3illustrates an example of an absorption spectrum of a photoelectric conversion layer that includes the tin naphthalocyanine represented by Formula (3). The measurement of the absorption spectrum is made by using a sample prepared by stacking a photoelectric conversion layer (thickness: 30 nm) on a quartz substrate.

The absorption spectrum illustrated inFIG. 3confirms that a photoelectric conversion layer composed of a material including tin naphthalocyanine absorbs light in the near-infrared region. That is, selecting a material including tin naphthalocyanine as a material of the photoelectric conversion layer15enables, for example, a photosensor capable of detecting the near-infrared radiation to be produced.

FIG. 4schematically illustrates an exemplary structure of the photoelectric conversion layer15. In the exemplary structure illustrated inFIG. 4, the photoelectric conversion layer15includes a hole-blocking layer15h, a photoelectric conversion structure15A composed of an organic semiconductor material including the tin naphthalocyanine represented by General Formula (1) above, and an electron-blocking layer15e. The hole-blocking layer15his interposed between the photoelectric conversion structure15A and the counter electrode12. The electron-blocking layer15eis interposed between the photoelectric conversion structure15A and the pixel electrode11.

The photoelectric conversion structure15A illustrated inFIG. 4includes at least one of a p-type semiconductor and an n-type semiconductor. In the exemplary structure illustrated inFIG. 4, the photoelectric conversion structure15A includes a p-type semiconductor layer150p, an n-type semiconductor layer150n, and a mixed layer150minterposed between the p-type and n-type semiconductor layers150pand150n. The p-type semiconductor layer150pis interposed between the electron-blocking layer15eand the mixed layer150mand responsible for photoelectric conversion and/or hole transportation. The n-type semiconductor layer150nis interposed between the hole-blocking layer15hand the mixed layer150mand responsible for photoelectric conversion and/or electron transportation. As described below, the mixed layer150mmay optionally include at least one of a p-type semiconductor and an n-type semiconductor.

The p-type and n-type semiconductor layers150pand150ninclude a p-type organic semiconductor and an n-type organic semiconductor, respectively. That is, the photoelectric conversion structure15A includes at least one of a p-type organic semiconductor and an n-type organic semiconductor in addition to the organic photoelectric conversion material including the tin naphthalocyanine represented by General Formula (1) above.

The p-type organic semiconductor (compound) is a donor-type organic semiconductor (compound) which is likely to donate electrons to others, such as a hole-transporting organic compound. More specifically, in the case where two organic materials are used while they are in contact with each other, the term “p-type organic semiconductor (compound)” used herein refers to an organic compound having a lower ionization potential. Thus, the donor-type organic compound may be any organic compound having an electron-donating property. Examples of such an organic compound include triarylamines, benzidines, pyrazolines, styrylamines, hydrazones, triphenylmethanes, carbazoles, polysilanes, thiophenes, phthalocyanines, cyanines, merocyanines, oxonols, polyamines, indoles, pyrroles, pyrazoles, polyarylenes, condensed aromatic carbocyclic compounds (e.g., a naphthalene derivative, an anthracene derivative, a phenanthrene derivative, a tetracene derivative, a pyrene derivative, a perylene derivative, and a fluoranthene derivative), and metal complexes including a nitrogen-containing heterocyclic compound as a ligand. Examples of the donor-type organic semiconductor are not limited to the above compounds. As described above, any organic compound having a lower ionization potential than an organic compound used as an n-type (acceptor-type) compound may be used as a donor-type organic semiconductor. The above-described tin naphthalocyanine is an example of the p-type organic semiconductor material.

The n-type organic semiconductor (compound) is an acceptor-type organic semiconductor (compound) which is likely to accept electrons, such as an electron-transporting organic compound. More specifically, in the case where two organic compounds are used while they are in contact with each other, the n-type organic semiconductor (compound) is an organic compound having a larger electron affinity. Thus, any organic compound capable of accepting electrons may be used as an acceptor-type organic compound. Examples of such an organic compound include fullerene, fullerene derivatives, condensed aromatic carboncyclic compounds (e.g., a naphthalene derivative, an anthracene derivative, a phenanthrene derivative, a tetracene derivative, a pyrene derivative, a perylene derivative, and a fluoranetene derivative), five- or seven-membered heterocyclic compounds containing a nitrogen atom, an oxygen atom, or a sulfur atom (e.g., pyridine, pyradine, pyrimidine, pyridadine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole, pyrazole, imidazole, thiazole, oxazole, indazole, benzimidazole, benzotriazole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridadine, triazolopyrimidine, tetrazaindene, oxadiazole, imidazopyridine, pyrrolidine, pyrrolopyridine, thiadiazolopyridine, dibenzazepine, and tribenzazepine), polyarylenes, fluorenes, cyclopentadienes, silyl compounds, and metal complexes including a nitrogen-containing heterocyclic compound as a ligand. Examples of the acceptor-type organic semiconductor are not limited to the above compounds. As described above, any organic compound having a larger electron affinity than an organic compound used as a p-type (donor-type) compound may be used as an acceptor-type organic semiconductor.

The mixed layer150mmay be, for example, a layer having a bulk heterojunction structure including a p-type semiconductor and an n-type semiconductor. For forming the mixed layer150mincluding the bulk heterojunction structure, the tin naphthalocyanine represented by General Formula (1) above may be used as a p-type semiconductor material, and fullerene and/or a fullerene derivative may be used as an n-type semiconductor material. It is advantageous that the material of the p-type semiconductor layer150pbe the same as that of the p-type semiconductor material included in the mixed layer150m. Similarly, it is advantageous that the material of the n-type semiconductor layer150nbe the same as that of the n-type semiconductor material included in the mixed layer150m. The bulk heterojunction structure is described in detail in Japanese Patent No. 5553727, the entire contents of which are incorporated by reference herein.

By using materials appropriate to the wavelength region in which light is to be detected, it is possible to produce an imaging device having sensitivity in the desired wavelength region. The photoelectric conversion layer15may include an inorganic semiconductor material such as amorphous silicon. The photoelectric conversion layer15may include a sublayer composed of an organic material and a sublayer composed of an inorganic material. In the example described below, the photoelectric conversion layer15has a bulk heterojunction structure formed by codeposition of tin naphthalocyanine and C60.

Action of Imaging device

FIG. 5includes timing charts for explaining an example of the action of the imaging device according to an embodiment of the present disclosure.FIG. 5(a)illustrates the timing of the rise (or fall) of a vertical synchronizing signal Vss.FIG. 5(b)illustrates the timing of the rise (or fall) of a horizontal synchronizing signal Hss.FIG. 5(c)illustrates an example of a change, with time, in the voltage Vb applied from the voltage supply circuit32to the counter electrodes12via the voltage control lines42.FIG. 5(d)illustrates a change, with time, in the potential φ of the counter electrode12with respect to the pixel electrode11.FIG. 5(e)schematically illustrates the timings of resetting, exposure, and high-luminance after-image resetting of each row of the pixel array PA (seeFIG. 1).

An example of the action of the imaging device100is described below with reference toFIGS. 1, 2, and 5. For the sake of simplicity, an example of the action of an imaging device100that includes a pixel array PA including pixels arranged in 8 rows in total, that is, namely, the R0-th to R7-th rows, is described below.

For acquiring an image, first, the charge accumulation region of each of the unit pixels10included in the pixel array PA is reset, and a pixel signal is read out from each of the reset unit pixels10. For example, as illustrated inFIG. 5, the resetting of a plurality of pixels in the R0-th row starts in response to the vertical synchronizing signal Vss (Time t0). InFIG. 5, the rectangular portions filled with dots schematically represent a period during which a signal is read out. The readout period may include a resetting period during which the potential of the charge accumulation region of each unit pixel10is reset.

For resetting the pixels in the R0-th row, the address transistors26whose gates are connected to the specific one of the address control lines46which belongs to the R0-th row are turned on by controlling the potential of the address control line46. Furthermore, the reset transistors28whose gates are connected to the specific one of the reset control lines48which belongs to the R0-th row are turned on by controlling the potential of the reset control line48. Thus, the charge accumulation node41and the reset voltage line44are connected to each other, and a reset voltage Vr is supplied to each charge accumulation region. Specifically, the potential of the gate electrode24gof each signal detection transistor24and the potential of the pixel electrode11of each photoelectric conversion unit13are reset to be the reset voltage Vr. Subsequently, a pixel signal is read out from each of the reset unit pixels10in the R0-th row via the corresponding one of the vertical signal lines47. These pixel signals are correspondent to the reset voltage Vr. Subsequent to the readout of the pixel signals, the reset transistors28and the address transistors26are turned off.

In this example, the pixels in each of the R0-th to R7-th rows are reset sequentially on a row-by-row basis in response to a horizontal synchronizing signal Hss as schematically illustrated inFIG. 5. In other words, the pixel array PA is driven in a rolling shutter mode. Hereinafter, the intervals between the pulses of the horizontal synchronizing signal Hss, that is, the period from when a row is selected to when the next row is selected, is referred to as “1 H period”. In this example, for example, the period between Time t0and Time t1corresponds to the 1 H period.

As illustrated inFIG. 5, the voltage Ve for imaging is applied from the voltage supply circuit32to each counter electrode12during the period (Time t0to Time t9) from the start of the acquisition of the image to the end of the resetting of all the rows of the pixel array PA and the readout of pixel signals. The voltage Ve is, for example, about 10 V.

Subsequent to the resetting of all the rows of the pixel array PA and the readout of pixel signals, the high-luminance after-image resetting period is started in response to the horizontal synchronizing signal Hss (Time t9). InFIG. 5(e), the blank rectangular portions schematically represent the high-luminance after-image resetting period in each row. The high-luminance after-image resetting period starts when the voltage applied from the voltage supply circuit32to each counter electrode12is changed from the voltage Ve. In this embodiment, the voltage applied to each counter electrode12is gradually decreased from the voltage Ve to a voltage V3over the period from the start (t9) to the end (t13) of the high-luminance after-image resetting period. Subsequently, the voltage applied from the voltage supply circuit32to each counter electrode12is increased from V3to Ve at Time t13, at which the high-luminance after-image resetting period is terminated. The voltage V3is typically set to a voltage at which the potential of the counter electrode12with respect to the pixel electrode11is 0 V or less, that is, for example, about 0 V. However, the voltage V3is not limited to 0 V.

When a bias voltage of 0 V is applied to the photoelectric conversion layers15, most of the charge accumulated at the photoelectric conversion layers15, which causes high-luminance after-image, is eliminated. This is presumably because, when the bias voltage is 0 V, the electron-hole pairs generated in the photoelectric conversion layers15due to the light irradiation do not migrate toward the pixel electrodes11and counter electrodes12to separate from each other, but quickly recombine with each other and disappear. The inventors of the present invention are the first to find that setting the difference in potential between the counter electrodes12and the pixel electrodes11to 0 V, that is, setting the bias voltage applied to the photoelectric conversion layers15to 0 V, may enable the charge that may cause high-luminance after-image to be quickly eliminated. The elimination of the charge that may cause high-luminance after-image occurs in the photoelectric conversion layers15in the high-luminance after-image resetting period. Since the elimination of the charge is the cancellation of the charge which occurs inside the photoelectric conversion layers15, the elimination of the charge hardly affects the signal charge accumulated at the charge accumulation nodes41.

The high-luminance after-image resetting period is terminated when the voltage applied from the voltage supply circuit32to the counter electrodes12is increased to the voltage Ve (Time t13). As described above, in this embodiment of the present disclosure, selecting the voltage applied to the counter electrodes12between the voltage Ve and the voltage V3enables switchover between the exposure period and the high-luminance after-image resetting period. As illustrated inFIG. 5, in this example, the start (Time t9) and the end (Time t13) of the high-luminance after-image resetting period are common to all the pixels included in the pixel array PA.

Subsequently, signal charge is read out from the pixels in each row of the pixel array PA in response to the horizontal synchronizing signal Hss. In this example, signal charge is read out from the pixels in each of the R0-th to R7-th rows sequentially on a row-by-row basis from Time t15. Hereinafter, the period from a time when pixels in a row are selected to a time when the pixels in the row are selected again may be referred to as “1V period”. In this example, the period from Time t0to Time t15corresponds to the 1V period.

When signal charge is read out from the pixels in the R0-th row subsequent to the high-luminance after-image resetting period and the exposure period, the address transistors26in the R0-th row are turned on. This allows the pixel signals correspondent to the amounts of charge accumulated at the respective charge accumulation regions during the exposure period to be output through the vertical signal lines47. Subsequent to the readout of the pixel signals, the pixels may be reset by turning on the reset transistors28. Subsequent to the readout of the pixel signals, the address transistors26(and the reset transistors28) are turned off. Subsequent to the readout of the signal charge from the pixels in each row of the pixel array PA, the difference between the signals read out at Time t0and Time t9is determined in order to remove fixed noises contained in the signals.

As described above, in this embodiment of the present disclosure, the start and end of the high-luminance after-image resetting period are controlled by changing the voltage Vb applied to the counter electrodes12. That is, according to this embodiment of the present disclosure, the occurrence of high-luminance after-image may be reduced by controlling the voltage Vb, without arranging the wiring layer included in the unit pixels to be only immediately below the pixel electrodes as in Japanese Unexamined Patent Application Publication No. 2013-84789. As a result, in this embodiment of the present disclosure, it is possible to operate the imaging device at a further high speed. Furthermore, in this embodiment of the present disclosure, the degree of flexibility in the arrangement of wires in the unit pixels10is not reduced, which is advantageous in terms of a reduction in the size of the pixels.

In addition, it is possible to set the high-luminance after-image resetting period to be included in the exposure period, which is a period from the resetting of each of the rows of the pixel array PA to the readout of signals from the row. This may reduce the occurrence of high-luminance after-image without reducing the frame rate or the like.

For performing the exposure and the readout of signal charge in a rolling shutter mode, the pixel array PA is driven on a row-by-row basis. In other words, the timing of exposure and the timing of signal readout vary by the rows of the pixel array PA. On the other hand, the resetting of high-luminance after-image is performed at a time in all the pixels10included in the pixel array PA by the voltage supply circuit32simultaneously changing the voltage of the counter electrodes of the pixels10. However, as described above, the resetting of high-luminance after-image does not affect the signal charge accumulated at the charge accumulation nodes41. Thus, the amount of exposure time of the pixel array PA is the amount of the 1V period minus the amount of high-luminance after-image resetting period. The amount of time during which each row is exposed to light is equal.

The frequency of the high-luminance after-image resetting period is determined in consideration of the application or operation of the imaging device, such as the degree to which the occurrence of high-luminance after-image should be reduced. For example, a high-luminance after-image resetting period may be set every one to N frames, where N is an integer of 2 or more. The frequency of the high-luminance after-image resetting period may be changed automatically or manually by a user on the basis of incident light, the scene, and the like.

In the above-described embodiment, the voltage applied to the counter electrodes12is changed in the high-luminance after-image resetting period. Alternatively, the voltage applied to the pixel electrodes11or both the voltage applied to the pixel electrodes11and the voltage applied to the counter electrodes12may also be changed such that the voltage applied to the photoelectric conversion layers reaches 0 V at any timing within the high-luminance after-image resetting period. For example, the voltage of the charge accumulation portions, that is, the voltage of the pixel electrodes may be changed by changing the reset voltage Vr under the condition where the reset transistors28are on.

Other Examples of Action of Imaging device

FIG. 6includes diagrams used for explaining another example of the action of the imaging device according to an embodiment of the present disclosure. Similarly toFIG. 5,FIG. 6(a)illustrates the timing of the rise (or fall) of the vertical synchronizing signal Vss;FIG. 6(b)illustrates the timing of the rise (or fall) of the horizontal synchronizing signal Hss;FIG. 6(c)illustrates an example of a change, with time, in the voltage Vb applied from the voltage supply circuit32to the counter electrodes12via the voltage control lines42;FIG. 6(d)illustrates the change, with time, in the potential φ of the counter electrodes12with respect to the pixel electrodes11; andFIG. 6(e)schematically illustrates the timing at which pixels in each row of the pixel array PA are reset, the timing at which the pixels are exposed to the light, and the timing at which the pixels are subjected to the high-luminance after-image reset.

The other example of the action of the imaging device100is described below with reference toFIGS. 1, 2, and 6. As in the above description, an example of the action of an imaging device100that includes a pixel array PA including pixels arranged in 8 rows in total, that is, namely, the R0-th to R7-th rows, is described below.

For resetting all the pixels, the charge accumulation region of each of the unit pixels10of the pixel array PA is reset simultaneously in all the rows. For example, as illustrated inFIG. 6, the resetting of the plurality of pixels in the R0-th to R7-th rows is started in response to a vertical synchronizing signal Vss (Time t0to Time t2). InFIG. 6, the solid filled rectangular portions represent a resetting period during which the potentials of the charge accumulation regions of the unit pixels10are reset.

For resetting all the pixels, that is, the pixels in each of the R0-th to R7-th rows, the address transistors26whose gates are connected to the specific one of the address control lines46which belongs to each of the R0-th to R7-th rows are turned on by controlling the potential of the address control line46. Moreover, the reset transistors28whose gates are connected to the specific one of the reset control lines48which belongs to each of the R0-th to R7-th rows are turned on by controlling the potential of the reset control line48. Thus, the charge accumulation nodes41are connected to the reset voltage line44, and the reset voltage Vr is supplied to the charge accumulation regions. Specifically, the potential of the gate electrode24gof each signal detection transistor24and the potential of the pixel electrode11included in each photoelectric conversion unit13are reset to the reset voltage Vr. Subsequently, the reset transistors28and the address transistors26are turned off.

Subsequent to the resetting of the pixels of the pixel array PA in each row, the high-luminance after-image resetting period is started in response to the horizontal synchronizing signal Hss (Time t2).

InFIG. 6(e), the blank rectangular portions represent a period during which the high-luminance after-image is reset in the row. The high-luminance after-image resetting period is started upon the voltage applied from the voltage supply circuit32to the counter electrodes12being changed to a voltage V3different from the voltage Ve. In this embodiment, the voltage applied to the counter electrodes12is changed from the voltage Ve to the voltage V3at the time when the high-luminance after-image resetting period is started, that is, Time t2. The voltage applied to the counter electrodes12is maintained to be V3during the high-luminance after-image resetting period, and changed from V3to Ve at the time when the high-luminance after-image resetting period is terminated, that is, Time t6. The voltage V3is typically set to a voltage at which the difference in potential between the pixel electrodes11and the counter electrodes12is 0 V, that is, for example, about 0 V. However, the voltage V3is not limited to 0 V.

As described above, in an embodiment of the present disclosure, resetting pixels of the pixel array PA simultaneously in all the rows and immediately performing the resetting of high-luminance after-image enable the charge that may cause high-luminance after-image to be eliminated from all the pixels substantially at a time. This may enable the occurrence of high-luminance after-image to be reduced at a further high speed. In addition, it is possible to maintain the voltage applied to the photoelectric conversion layers15to be 0 V during the high-luminance after-image resetting period. This makes it possible to increase the amount of time during which the electron-hole pairs are capable of recombining in the photoelectric conversion layers15and to eliminate the charge that may cause high-luminance after-image with further certainty.

FIG. 7includes diagrams used for explaining further another example of the action of the imaging device according to an embodiment of the present disclosure. Similarly toFIG. 5,FIG. 7(a)illustrates the timing of the rise (or fall) of a vertical synchronizing signal Vss;FIG. 7(b)illustrates the timing of the rise (or fall) of a horizontal synchronizing signal Hss;FIG. 7(c)illustrates an example of a change, with time, in the voltage Vb applied from the voltage supply circuit32to the counter electrodes12via the voltage control lines42;FIG. 7(d)illustrates an example of a change, with time, in the potential φ R0of the counter electrodes12in the R0-th row with respect to the pixel electrodes11;FIG. 7(e)illustrates an example of the change, with time, in the potential φ R1of the counter electrodes12in the R1-th row with respect to the pixel electrodes11; andFIG. 7(f)schematically illustrates the timing of the resetting of pixels in each of the rows of the pixel array PA, the timing of the exposure of the pixels, and the timing of the resetting of high-luminance after-image in the pixels.

The other example of the action of the imaging device100is described below with reference toFIGS. 1, 2, and 7. As in the above description, an example of the action of an imaging device100that includes a pixel array PA including pixels arranged in 8 rows in total, that is, namely, the R0-th to R7-th rows, is described below.

For acquiring an image, first, the charge accumulation region of each of the unit pixels10included in the pixel array PA is reset and a pixel signal is read out from each of the reset unit pixels10. For example, the resetting of a plurality of pixels in the R0-th row is started in response to the vertical synchronizing signal Vss as illustrated inFIG. 7(Time t0). InFIG. 7(f), the rectangular portions filled with dots schematically represent a period during which a signal is read out. The readout period may include a resetting period, during which the potential of the charge accumulation region of each unit pixel10is reset.

For resetting the pixels in the R0-th row, the address transistors26whose gates are connected to the specific one of the address control lines46which belongs to the R0-th row are turned on by controlling the potential of the address control line46. Furthermore, the reset transistors28whose gates are connected to the specific one of the reset control lines48which belong to the R0-th row are turned on by controlling the potential of the reset control line48. Thus, the charge accumulation nodes41are connected with the reset voltage line44, and the reset voltage Vr is supplied to the charge accumulation regions. Specifically, the potential of the gate electrode24gof each signal detection transistor24and the potential of the pixel electrode11of each photoelectric conversion unit13are reset to the reset voltage Vr. Subsequently, a pixel signal is read out from each of the reset unit pixels10in the R0-th row via the corresponding one of the vertical signal lines47. These pixel signals are correspondent to the reset voltage Vr. Subsequent to the readout of the pixel signals, the reset transistors28and the address transistors26are turned off.

In this example, the pixels in each of the R0-th to R7-th rows are reset sequentially on a row-by-row basis in response to a horizontal synchronizing signal Hss as schematically illustrated inFIG. 7.

As illustrated inFIG. 7, the voltage Ve for imaging is applied from the voltage supply circuit32to each counter electrode12during the period (Time t0to Time t9) from the start of the acquisition of the image to the end of the resetting of all the rows of the pixel array PA and the readout of pixel signals. The voltage Ve is, for example, about 10 V.

Subsequent to the resetting of all the rows of the pixel array PA and the readout of pixel signals, the high-luminance after-image resetting period is started in response to the horizontal synchronizing signal Hss (Time t9). InFIG. 7(f), the blank rectangular portions schematically represent the high-luminance after-image resetting period in each row. As described above with reference toFIG. 5, the high-luminance after-image resetting period is started when the voltage applied from the voltage supply circuit32to each counter electrode12is changed from the voltage Ve. Specifically, the voltage applied to each counter electrode12is gradually reduced from the voltage Ve to a voltage V3over the period from the start (t9) to the end (t13) of the high-luminance after-image resetting period. Subsequently, the voltage applied from the voltage supply circuit32to each counter electrode12is increased from V3to Ve at Time t13, at which the high-luminance after-image resetting period is terminated. The voltage V3is typically set to a voltage at which the potential of the counter electrode12with respect to the pixel electrode11is 0 V or less, that is, for example, about 0 V. However, the voltage V3is not limited to 0 V.

The intensity of light incident on the pixel array PA may vary significantly between the R0-th and R1-th rows. In another case, the intensity of light incident on the pixel array PA may vary significantly between Time t0and Time t3. In such cases, the amount of charge accumulated at the charge accumulation regions of the pixels may vary significantly between the R0-th and R1-th rows. Since the potentials of the pixel electrodes11vary with the amount of charge accumulated at the respective charge accumulation regions, the potentials φ of the counter electrodes12with reference to the respective pixel electrodes11are different from each other at Time t9as illustrated inFIGS. 7(d) and 7(e)even when the voltage applied to the counter electrodes12is the same across all the pixels. Accordingly, the timing tR0at which the φR0is 0 V subsequent to the start of the high-luminance after-image resetting period and the timing tR1at which the φR1is 0 V subsequent to the start of the high-luminance after-image resetting period are different from each other. However, even in such cases, setting V3such that the potentials φ of the counter electrodes12with respect to the respective pixel electrodes11reach 0 V at any timing within the high-luminance after-image resetting period enables the charge that may cause high-luminance after-image to be eliminated.

The high-luminance after-image resetting period is terminated when the voltage applied from the voltage supply circuit32to the counter electrodes12is increased to the voltage Ve (Time t13). As described above, in this embodiment of the present disclosure, selecting the voltage applied to the counter electrodes12between the voltage Ve and the voltage V3enables switchover between the exposure period and the high-luminance after-image resetting period.

Subsequently, signal charge is read out from the pixels in each row of the pixel array PA in response to the horizontal synchronizing signal Hss. In this example, signal charge is read out from the pixels in each of the R0-th to R7-th rows sequentially on a row-by-row basis from Time t15.

When signal charge is read out from the pixels in the R0-th row subsequent to the high-luminance after-image resetting period and the exposure period, the address transistors26in the R0-th row are turned on. This allows the pixel signals correspondent to the amounts of charge accumulated at the respective charge accumulation regions during the exposure period to be output through the vertical signal lines47. Subsequent to the readout of the pixel signals, the pixels may be reset by turning on the reset transistors28. Subsequent to the readout of the pixel signals, the address transistors26(and the reset transistors28) are turned off. Subsequent to the readout of the signal charge from the pixels in each row of the pixel array PA, the difference between the signals read out at Time t0and Time t9is determined in order to remove fixed noises contained in the signals.

As described above, in this embodiment of the present disclosure, even when the resetting of high-luminance after-image is performed during the exposure period and the potentials of pixel electrodes vary by pixels, it is possible to create a timing at which the potential of each counter electrode with respect to the corresponding one of the pixel electrodes reaches 0 V. This enables the charge that may cause high-luminance after-image to be eliminated and reduces the occurrence of high-luminance after-image.

The imaging device according to an embodiment of the present disclosure may be used as an image sensor or the like and may be included in a camera for medical use, a camera for robot control, a security camera, a camera for automotive use, or the like. In a camera for automotive use, the imaging device according to an embodiment of the present disclosure may be used, for example, as an input device for a control device that governs control in order to achieve safe driving of a vehicle. The imaging device according to an embodiment of the present disclosure may also be used for aiding an operator to drive a vehicle safely.