SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF AND POWER CONVERTER

A semiconductor device is obtained, in which the impact of bonding of the wiring member on an underneath structure including a semiconductor element is reduced and thus the reliability is improved. The semiconductor device includes: a semiconductor element with a first main surface; a first metal member formed on the first main surface; a second metal member formed on an upper surface of the first metal member; a third metal member formed on an upper surface of the second metal member; a fourth metal member with copper as a principal component, formed on an upper surface of the third metal member; and a wiring member with copper as a principal component, bonded to an upper surface of the fourth metal member corresponding to a formation position of the third metal member.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device with an electrode structure for using copper wiring, a manufacturing method of the semiconductor device, and a power converter.

BACKGROUND TECHNOLOGY

In recent years, it has been required for a semiconductor device for power applications to have a higher current density. In order to carry high density current, a semiconductor device that can withstand being driven under a high temperature condition is required. For such a semiconductor device, it is proposed to use copper wiring as metal wiring for connecting the semiconductor device to an external terminal.

There is a generally known bonding method in which ultrasonic vibration energy is applied to a metal wire with a diameter of about 100 μm to bond the metal wire to a semiconductor device. In this technique, the ultrasonic energy for bonding a copper wire as the metal wire is required to be greater than the ultrasonic energy for bonding an aluminum wire as the metal wire.

Thus, in a conventional semiconductor device, a large energy acts on the semiconductor element with an electrode formed thereon in order to bond the copper wire thereto. With the aim of reducing the impact of this energy on an underneath structure, a method to improve wire bonding performance by using a copper for the top surface of the electrode to which a copper wire is bonded and by forming, underneath the copper, a copper (Cu) with a higher Vickers hardness than that of the top surface copper or a nickel (Ni) is described (for example, Patent Document 1).

PRIOR ART REFERENCES

Patent Documents

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

However, in the semiconductor device described in Patent Document 1, when a copper wire is bonded, if there is a material of low hardness underneath the material of high hardness, a crack caused in the material of high hardness will also develop into the aluminum of low hardness, resulting in deterioration of the reliability of the semiconductor device.

The present disclosure is made to solve the above-mentioned problem and aims to obtain a semiconductor device with improved reliability by reducing the impact on the underneath structure including a semiconductor element during bonding a metal wire.

Means for Solving the Problem

A semiconductor device according to the present disclosure includes: a semiconductor element with a first main surface; a first metal member formed on the first main surface; a second metal member formed on an upper surface of the first metal member; a third metal member formed on an upper surface of the second metal member; a fourth metal member with copper as a principal component, formed on an upper surface of the third metal member; and a wiring member with copper as a principal component, bonded to an upper surface of the fourth metal member corresponding to a formation position of the third metal member.

Effects of the Invention

According to the present disclosure, a second metal member is formed on an upper surface of a first metal member, a third metal member is formed on an upper surface of the second metal member, and a wiring member with copper as the principal component is provided on an upper surface of a fourth metal member corresponding to the formation position of the third metal member, so that the impact of bonding of the wiring member on an underneath structure including the semiconductor element can be reduced and the reliability of the semiconductor device can be improved.

EMBODIMENTS FOR CARRYING OUT THE INVENTION

First, overall configurations of the semiconductor device according to the present disclosure will be described with reference to the drawings. The figures are schematic and do not reflect the exact sizes, etc., of the components shown. The components with the same symbols are the same or equivalent, and this is common to the entire specification.

FIG.1is a schematic diagram of a planar structure showing a semiconductor device according to Embodiment 1.FIG.2is a schematic diagram of a cross-sectional structure showing the semiconductor device according to Embodiment 1.FIG.2is a schematic diagram of the cross-sectional structure along the alternate long and short dash line AA inFIG.1.

In the figure, a semiconductor device100includes a semiconductor element1, a first metal member2, a second metal member3, a third metal member4, a fourth metal member5, and a bonding wire6, which is a wiring member, with copper as the principal component. The bonding wire6is bonded to an upper surface of the fourth metal member5.

In the figure, the first metal member2is disposed (formed) on a first main surface of the semiconductor element1. The second metal member3is formed on the upper surface of the first metal member2. The third metal member4is formed on the upper surface of the second metal member3. The fourth metal member5is formed on the upper surface of the third metal member4. The bonding wire6with copper as the principal component is bonded to the upper surface of the fourth metal member5. A bonding area61on the upper surface of the fourth metal member5is a bonding portion between the bonding wire6and the upper surface of the fourth metal member5. The bonding wire6is bonded to the bonding area61on the upper surface of the fourth metal member5.

InFIG.1, the bonding area61between the bonding wire6and the fourth metal member5is shown by the dashed line. The bonding area61of the bonding wire6is disposed inside an outer edge of the fourth metal member5. The bonding wire6is extended along a pair of opposite sides in the bonding area61of the bonding wire6.

InFIG.2, the bonding wire6bends away from the upper surface of the fourth metal member as the bonding wire6extends from the pair of opposite sides in the bonding area61of the bonding wire6. In other words, the bonding wire6bends in a direction to increase the distance from the upper surface of the fourth metal member5.

The semiconductor element1is, for example, a semiconductor element for power applications such as a metal oxide semiconductor field effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT). As a material for the semiconductor element1, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN) can be used.

However, the structure, material, and shape of the semiconductor element1are arbitrary as long as the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5can be formed on it. The thickness of the semiconductor element1may be from 50 μm to 500 μm and can be selected as appropriate depending on the applicable voltage and current rating of the semiconductor element1.

The first metal member2is formed on the first main surface of the semiconductor element1. As a material for the first metal member2, for example, aluminum (Al) can be used. However, the material of the first metal member2is not limited to Al, but copper (Cu), nickel (Ni), tungsten (W), cobalt (Co), chromium (Cr), titanium (Ti) and their alloy materials can be used. The film thickness of the first metal member2ranges from 1 μm to 50 μm.

When Ni is used as the first metal member2, a thicker Ni film improves the wire bonding performance, but an excessively thick Ni film increases film stress and thus increases the possibility of cracking. Therefore, the film thickness of the first metal member2preferably should be within a range from 5 μm to 20 μm.

The second metal member3is formed on the upper surface of the first metal member2. As a material for the second metal member3, for example, Cu can be used. The material for the second metal member3is not limited to Cu, but magnesium (Mg), iron (Fe), tin (Sn), palladium (Pd), and zinc (Zn) can also be used. The film thickness of the second metal member3ranges from 1 μm to 50 μm.

The third metal member4is formed on the upper surface of the second metal member3. As a material for the third metal member4, for example, Ni can be used. The material of the third metal member4is not limited to Ni, but Co, Cr, W, titanium nitride (TiN) and their alloy materials can be used. The film thickness of the third metal member4ranges from 1 μm to 50 μm. If Co or Cr is used as the material for the third metal member4, the thickness of the third metal member4should be within the range of 1 μm to 20 μm, since these materials can be formed by plating.

The fourth metal member5is formed on the upper surface of the third metal member4. For the fourth metal member5, a material with Cu as the principal component can be used. The film thickness of the fourth metal member5ranges from 1 μm to 50 μm.

Here, the relationship among the materials of the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5will be described.

A material with Cu as the principal component is used for the bonding wire6, described below, which is to be bonded to the fourth metal member5. Therefore, considering the wire bondability of the bonding wire6to the first main surface of the semiconductor element1, the material with Cu as the principal component is selected. And, in order to reduce the downward impact (damage) when the Cu bonding wire6is wire-bonded to the first main surface of the semiconductor element1, a material with a hardness equal to or higher than that of the fourth metal member5is used for either the second metal member3or the third metal member4. Here, the “hardness” used here is a value defined by, for example, Vickers hardness, but the same relationship applies even if another index of hardness is used.

In particular, the Ni, when used as the third metal member4, serves as a damage suppression layer that prevents the impact (damage) generated during the wire bonding from propagating downward from the second metal member3.

The second metal member3serves as a damage suppression layer that suppresses the damage due to the thermal stress caused by the heat generated when the semiconductor device100operates. Therefore, for the second metal member3, a material with a hardness equal to or lower than that of the third metal member4is used.

The hardness of the material of the first metal member2is equal to or lower (softer) than the hardness of the second metal member3and the third metal member4. As described above, by using, for the second metal member3, a material with a hardness equal to or higher than that of the first metal member2, the influence of the damage due to the thermal stress can be suppressed from being propagated to the first metal member2. Regarding the hardness of the materials, using materials with the same hardness between the materials has a certain effect, but it is more effective to use materials with different hardness.

Specifically, the layer composition from the first metal member2to the fourth metal member5must include a Cu/Ni/Cu sandwich structure. In particular, it is desirable that the materials in the Cu/Ni/Cu sandwich structure be disposed contiguous to each other as in a case where Cu/Ni/Cu respectively correspond to the fourth metal member5/the third metal member4/the second metal member3. Notwithstanding the above, the materials in the Cu/Ni/Cu sandwich structure do not necessarily need to be placed contiguous to each other, but it suffices as long as Ni is eventually disposed between Cu and Cu, as in the Cu/Ni/Cu layer structure realized by the layer composition of the fourth metal member5/the second metal member3/the first metal member2or the fourth metal member5/the third metal member4/the first metal member2. Of the first metal member2, the second metal member3, and the third metal member4, if a material other than Cu and Ni is used for the first metal member2, Al can be selected for the material because Al is commonly used to form the first main surface of the semiconductor element1. In this case, the structure from the first metal member2to the fourth metal member5will be an Al/Cu/Ni/Cu structure. As for other configurations, the layers other than the layers of Cu, Ni, and Cu can be selected from the metal members mentioned above, and these layers each are expected to serve as a barrier metal or an adhesion layer.

In addition to the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5, a diffusion barrier layer or an adhesion layer may be inserted between the above metal members as appropriate. W Co, Cr, Ti, Pd, Pt and their alloys may be used as the diffusion barrier layer or the adhesion layer. Other materials may be used as well, as long as the effects of the present disclosure can be obtained.

Additionally, an antioxidant film may be additionally formed on the upper surface of the fourth metal member5to prevent oxidation from occurring, the oxidation starting from the upper surface of the fourth metal member5. As the antioxidant film, an organic material or an inorganic material such as metal can be used. As a metal material for the antioxidant film, Au, Ag, Pd and Pt can be used. The antioxidant film should preferably be made of a precious metal material. However, the material is not limited to the above as long as the effects of the present disclosure are not compromised.

Thus, by providing the diffusion barrier layer between the metal members, interdiffusion of metal atoms between the layers can be suppressed. Also, by providing the adhesion layer between the metal members, adhesion between the layers can be improved. Furthermore, by providing the antioxidant film between the metal members, defects due to oxidation (insufficient adhesion) can be controlled.

The wiring member6is formed on the upper surface of the fourth metal member5. The material for the wiring member6may be a material with Cu as the principal component. The wiring member6may contain as its component, in addition to Cu, a different material such as another metal or an organic component. Also, the surface of the wiring member6may be coated with another metal or an organic component. In terms of shape, the wiring member6may be a plate, a foil, or a wire. The best shape for the wiring member6is a wire shape. The thickness or the diameter of the wiring member6of the wire shape should preferably be from 100 μm to 500 μm. However, the structure, material and shape are not limited to the above as long as the effects of the present disclosure are not compromised.

FIG.3is a schematic diagram of a planar structure showing another semiconductor device according to Embodiment 1.FIG.4is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 1.FIG.4is a schematic diagram of a cross-sectional structure along the alternate long and short dash line BB inFIG.3.

In the figure, a semiconductor device101includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, and an insulation member8. The bonding wire6is bonded to the upper surface of the fourth metal member5.

InFIG.3, an outermost edge of the semiconductor device100is an outer edge of the semiconductor element1. Inside the outer edge of the semiconductor element1, there is an outer edge of the fourth metal member5. The insulation member8is disposed around a perimeter (outer edge) of the fourth metal member5. The bonding area61of the bonding wire6and the fourth metal member5is shown by the dashed line. The bonding area61of the bonding wire6is disposed inside the outer edge of the fourth metal member5. The bonding wire6is extended along a pair of opposite sides in the bonding area61of the bonding wire6.

InFIG.4, the bonding wire6bends away from the upper surface of the fourth metal member5as the bonding wire6extends from the pair of opposite sides in the bonding area61of the bonding wire6. In other words, outside the outer edge of the bonding area61, the bonding wire6bends in the direction that increases the distance from the upper surface of the fourth metal member5. The upper surface of the insulation member8is disposed higher than the upper surface of the fourth metal member5. In other words, the upper surface of the insulation member8protrudes upward from the upper surface of the fourth metal member5.

FIG.5is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 1.FIG.6is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 1.

InFIG.5, the semiconductor device102has the same configuration as the semiconductor device101inFIG.4, except the shape of the insulation member8. Although in the semiconductor device101inFIG.4, the upper surface of the insulation member8is disposed above the upper surface of the fourth metal member5, in the semiconductor device102, the upper surface of the insulation member8is disposed below the upper surface of the fourth metal member5.

To allow the semiconductor device to perform its function, it is conceivable that its stacked metal members, namely, the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5, be covered around their outer sides with the insulation member8, which is made of an insulating material, in order to ensure insulation with the other areas. In this case, the insulation member8is disposed on the first main surface (upper surface) of the semiconductor element1because the semiconductor element1itself has a larger outer shape than the stacked metal members.

InFIG.4, the insulation member8is in contact with the respective sides of the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5. The upper surface of the insulation member8protrudes upward from the upper surface of the fourth metal member5.

UnlikeFIG.4, inFIG.5, the insulation member8only needs to be in contact with at least part of a side of one of the stacked metal members, namely the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5.

As shown inFIG.6, a plurality of the structures shown inFIG.4may be disposed side by side, with the insulation member8serving as a termination region of the semiconductor element1. In a case where the plurality of structures shown inFIG.4are disposed side by side, regarding the configurations of the stacked metal members, if at least one of the plurality of structures disposed side by side has the structure shown inFIG.4, other areas may have a structure different from that shown inFIG.4. In a case where the insulation member8serves as the termination region of the semiconductor element1, regarding the positional relation between the semiconductor element1and the insulation member8, the insulation member8may be disposed inside the outer edge of the first main surface of the semiconductor element1, or may be disposed flush with the termination region of the semiconductor element1. Also, the insulation member8may protrude from the outer edge of the first main surface of the semiconductor element1. Additionally, the insulation member8may be disposed covering the side of the semiconductor element1and the second main face (back surface), which is the opposite side of the first main surface.

The material for the insulation member8may be polyimide or the like, but any material can be used as long as the functionalities of the present disclosure are not compromised.

Next, the manufacturing method of the semiconductor device100according to the present embodiment will be described.

FIGS.7to12are each a schematic diagram of a cross-sectional structure showing a manufacturing process of the semiconductor device according to Embodiment 1.

The main manufacturing process of Embodiment 1 is roughly divided into six steps. The first step is a step of performing a process to make the semiconductor element1function as a semiconductor element (semiconductor element preparation step). The second step is a step of forming the first metal member2on the first main surface of the semiconductor element1(first metal member formation step). The third step is a step of forming the second metal member3on the upper surface of the first metal member2(second metal member formation step). The fourth step is a step of forming the third metal member4on the upper surface of the second metal member3(third metal member formation step). The fifth step is a step of forming the fourth metal member5on the upper surface of the third metal member4(fourth metal member formation step). The sixth step is a step of forming the bonding wire6, which is the wiring member, on the upper surface of the fourth metal member5(wiring member formation step). Through these steps, the semiconductor device100can be manufactured.

In the first step, the semiconductor element1is processed to function as a semiconductor element.

Next, as shown inFIG.7, in the second step, the first metal member2is formed on the first main surface of the semiconductor element1. To form the first metal member2, chemical vapor deposition (CVD method), physical vapor deposition (PVD method), or plating may be used. The plating includes two types: electroless plating and electrolytic plating. When using a plating method, regarding the details of the plating process, any process, method, and formation condition can be applied as long as the first metal member2can be formed. Any pre-process necessary to form a plating film may be performed as needed.

For example, sputtering film deposition may be used as the PVD method. Although there are many sputtering methods for the sputtering film deposition such as magnetron sputtering, evaporation, or ion beam sputtering, any sputtering method may be used as long as a targeted first metal member2can be formed.

Although there are two types of power supply, a direct current type and an alternating current type, to be used when performing the sputtering film deposition, any sputtering method may be used as long as the targeted first metal member2can be formed. Although the sputtering film deposition conditions include many setting parameters such as heated deposition or non-heated deposition, assisted deposition or non-assisted deposition, input power, and gas flow rate, any deposition condition may be used as long as the targeted first metal layer can be formed.

In a case where the electrolytic plating method is used to form the first metal member2, it may be necessary to form a seed layer for plating film formation and an adhesion film for improving adhesion with the first main surface of the semiconductor element1. Although the CVD method and the PVD method, mentioned above, can be used to form the seed layer and the adhesion layer, either of them may be used as long as the targeted film can be formed. However, in view of the configuration of the semiconductor element1or the film thicknesses required for the seed layer and the adhesion layer, the sputtering film deposition is desirable to form the seed layer and the adhesion layer.

Next, as shown inFIG.8, in the third step, the second metal member3is formed on the upper surface of the first metal member2. To form the second metal member3, the forming method similar to that used to form the first metal member2described above may be used.

Next, as shown inFIG.9, in the fourth step, the third metal member4is formed on the upper surface of the second metal member3. To form the third metal member4, the forming method similar to that used to form the first metal member2described above may be used.

Next, as shown inFIG.10, in the fifth step, the fourth metal member5is formed on the upper surface of the third metal member4. To form the fourth metal member5, the forming method similar to that used to form the first metal member2described above may be used.

Next, as shown inFIG.11, in the sixth step, the bonding wire6is formed on the upper surface of the fourth metal member5. To form the bonding wire6, bonding by thermocompression, bonding by ultrasonic energy, and bonding by a bonding material such as solder may be used. In view of the aim of the present disclosure, the bonding by ultrasonic energy is desirable to form the bonding wire6. Although the bonding by ultrasonic energy involves various parameters such as load, amplitude, and processing time, any method or condition may be used as long as a targeted bonding result is obtained. By applying the ultrasonic energy by vibrating a tool9in the directions10parallel to the first main surface of the semiconductor element1with the tool9keeping pressing the bonding wire6in the direction11toward the upper surface of the fourth metal member5, the upper surface of the fourth metal member5and the bonding wire6are bonded together in the bonding area61.

Through these steps, the semiconductor device100shown inFIG.12can be manufactured.

In the semiconductor device configured as described above, the second metal member3is formed on the upper surface of the first metal member2, the third metal member4is formed on the upper surface of the second metal member3, and the bonding wire6with copper as the principal component is provided on an upper surface of the fourth metal member5corresponding to the formation position of the third metal member4, so that the impact of bonding of the bonding wire6on the underneath structure including the semiconductor element1can be reduced and the reliability of the semiconductor device can be improved.

Embodiment 2 differs from Embodiment 1 in that at least the outer edge of the fourth metal member5, from among the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5, used in Embodiment 1, is disposed inside the outer edges of the other metal members. Stacking the metal members inevitably increases the total thickness of the metal members. The increase in the total film thickness of the metal members is likely to cause stress at the position where the semiconductor element1and a metal member are in direct contact, which may result in damaging the semiconductor element1such as cracking. As described above, the outer edge of the fourth metal member5is disposed inside the outer edge of at least one of the first metal member2, the second metal member3, and the third metal member4, thereby reducing the total film thickness of the metal members at the contact position of the semiconductor element1and the metal member and thus reducing the stress generated in the semiconductor element1. As a result, the occurrence of damage such as cracking to the semiconductor element1can be suppressed and the reliability of the semiconductor device200can be improved. Other respects are the same as in Embodiment 1, so that the detailed descriptions will be omitted.

FIG.13is a schematic diagram of a cross-sectional structure showing the semiconductor device according to Embodiment 2. In the figure, the semiconductor device includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, and the bonding wire6, which is the wiring member, with copper as the principal component. The bonding wire6is bonded to the upper surface of the fourth metal member5.

InFIG.13, the first metal member2is formed (bonded) on the first main surface of the semiconductor element1. The second metal member3is formed on the upper surface of the first metal member2. The third metal member4is formed on the upper surface of the second metal member3. The fourth metal member5is formed on the upper surface of the third metal member4. The bonding wire6with copper as the principal component is bonded to the upper surface of the fourth metal member5. The bonding area61on the upper surface of the fourth metal member5is the bonding portion between the bonding wire6and the upper surface of the fourth metal member5. The bonding wire6is bonded to the bonding area61on the upper surface of the fourth metal member5. The outer edge of the fourth metal member5is disposed inside the outer edges of the first metal member2, the second metal member3, and the third metal member4.

FIG.14is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 2.FIG.15is a schematic diagram of a planar structure showing another semiconductor device according to Embodiment 2. InFIG.14, the insulation member8is disposed in a peripheral area of the upper surface of the third metal member4, the peripheral area being located outside the outer edge of the fourth metal member5. The insulation member8is in contact with the side of the fourth metal member5. The upper surface of the insulation member8protrudes upward from the upper surface of the fourth metal member5. InFIG.15, the insulation member8is disposed in contact with the side of the fourth metal member5and in contact, from the peripheral area of the upper surface of the third metal member4to the first main surface of the semiconductor element1, with the sides of the third metal member4, the second metal member3, and the second metal member3.

FIG.16is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 2. InFIG.16, the second metal member3and the third metal member4of the semiconductor device200shown inFIG.13have the same outer shape (outer edge) as that of the fourth metal member5. In the figure, the semiconductor device includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, and the bonding wire6, which is the wiring member, with copper as the principal component. The bonding wire6is bonded to the upper surface of the fourth metal member5.

InFIG.16, the first metal member2is formed (bonded) on the first main surface of the semiconductor element1. The second metal member3is formed on the upper surface of the first metal member2. The third metal member4is formed on the upper surface of the second metal member3. The fourth metal member5is formed on the upper surface of the third metal member4. The bonding wire6with copper as the principal component is bonded to the upper surface of the fourth metal member5. The bonding area61on the upper surface of the fourth metal member5is the bonding portion between the bonding wire6and the upper surface of the fourth metal member5. The bonding wire6is bonded to the bonding area61on the upper surface of the fourth metal member5. The outer edges of the second metal member3, the third metal member4, and the fourth metal member5are of the same size and the outer edge of the first metal member2is disposed outside the outer edge of the second metal member3.

FIG.17is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 2.FIG.18is a schematic diagram of a planar structure showing another semiconductor device according to Embodiment 2. InFIG.17, the insulation member8is disposed in the peripheral area of the upper surface of the first metal member2, the peripheral area being located outside the outer edge of the fourth metal member5. The insulation member8is in contact with the sides of the fourth metal member5, the third metal member4, and the second metal member3. The upper surface of the insulation member8protrudes upward from the upper surface of the fourth metal member5. InFIG.18, the insulation member8is disposed in contact with the sides of the fourth metal member5to the second metal member3to reach the peripheral area of the upper surface of the first metal member2and the first main surface of the semiconductor element1.

Thus, the insulation member8should be disposed around at least one of the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5. The insulation member8may be disposed around the fourth metal member5in contact with the side of the fourth metal member5on the upper surface of the third metal member4. Alternatively, the insulation member8may be disposed around the second metal member3, the third metal member4, and the fourth metal member5in contact with the sides of the second metal member3, the third metal member4, and the fourth metal member5to reach the upper surface of the first metal member2. Further alternatively, the insulation member8may be disposed around the second metal member3, the third metal member4, and the fourth metal member5in contact with the sides of the second metal member3, the third metal member4, and the fourth metal member5to reach the upper surface of the first metal member2. In this case, the insulation member8may be disposed in contact with the side of the first metal member2to reach the first main surface of the semiconductor element1.

As described above, the outer edge of the fourth metal member5is disposed inside the outer edge of at least one of the first metal member2, the second metal member3, and the third metal member4, thereby suppressing the occurrence of damage such as cracking to the semiconductor element1due to stress and thus improving the reliability of the semiconductor device200. The same effect can be obtained by disposing the outer edge of the fourth metal member5inside any plurality of the outer edges of the first metal member2, the second metal member3, and the third metal member4.

For example, the outer edges of the third metal member4and the fourth metal member5, being flush with each other, can be disposed inside the outer edges of the first metal member2and the second metal member3, being flush with each other.

Alternatively, the outer edges of the second metal member3, the third metal member4, and the fourth metal member5, being flush with each other, can be disposed inside the outer edge of the first metal member2. Alternatively, the outer edge of the fourth metal member5can be disposed inside the flush outer edges of the first metal member2, the second metal member3, and the third metal member4.

To increase the effectiveness of the present disclosure, the outer edge of the second metal member3should be inside the outer edge of the first metal member2. Even when the outer edge of the fourth metal member5is disposed outside one of or both of the outer edges of the second metal member3and the third metal member4, the outer edge of the fourth metal member5should be disposed inside at least one of the outer edges of the first metal member2, the second metal member3, and the third metal member4.

Such stacking of the metal members inevitably increases the total thickness of the metal members. The increase in the total film thickness of the metal members is likely to cause stress at the position where the semiconductor element1and a metal member are in direct contact, which may result in damaging the semiconductor element1such as cracking.

However, the total film thickness of the metal members at the contact position of the semiconductor element1and the metal member can be reduced and thus the stress generated in the semiconductor element1can be reduced, for example, by forming the outer edge of the fourth metal member5inside the outer edge of at least one of the first metal member2, the second metal member3, and the third metal member4. As a result, the occurrence of damage such as cracking to the semiconductor element1can be suppressed and the reliability of the semiconductor device200can be improved.

Next, the manufacturing method of the semiconductor device200according to the present embodiment will be described.

FIGS.19to23are each a schematic diagram of a cross-sectional structure showing a manufacturing process of the semiconductor device according to Embodiment 2.

In order to dispose the outer edge of the fourth metal member5shown inFIG.14inside the outer edge of at least one of the first metal member2, the second metal member3, and the third metal member4, a resist material or a metal mask, for example, may be used to limit the formation area of the metal member.

When the resist material is used, the outer edge of the fourth metal member5can be disposed inside the outer edge of the third metal member4by the following steps.

First, through the steps up to the fifth step shown in Embodiment 1, the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5are stacked on the first main surface of the semiconductor element1, as shown inFIG.19. Here, the following steps are performed before proceeding to the sixth step.

Next, as shown inFIG.20, a resist material7is applied to the upper surface of the fourth metal member5as the seventh step (resist material application step). A positive resist or a negative resist can be used for the resist material7. In a case where a photoresist is used as the resist material7, regarding formation steps of a resist pattern on the semiconductor element1with the metal members up to the fourth metal member5formed, first, the resist material7is applied and spin coated on the upper surface of the fourth metal member5over the semiconductor element1with the metal members up to the fourth metal member5formed, so that the resist material7is wet spread evenly on the entire top surface over the semiconductor element1with the metal members up to the fourth metal member5formed.

Next, as shown inFIG.21, in the eighth step, a photo mask with a predetermined pattern is placed over the semiconductor element1with the metal members up to the fourth metal member5formed and the resist material7evenly wet spread, and then ultraviolet rays are applied by an exposure machine (photolithography step). After the application of the ultraviolet rays, the semiconductor element1with the metal members up to the fourth metal member5formed and the applied resist material7exposed to the ultraviolet rays is immersed in a developing solution to remove the resist material7in the area not cured by exposure to the ultraviolet rays (photolithography step).

Next, as shown inFIG.22, in the ninth step, in the semiconductor element1with the un-cured resist material7removed and the upper surface of the fourth metal member5exposed, the area where the resist material7is removed is etched, using the cured resist material7as the mask (metal member processing step). Wet etching or dry etching can be used to etch the fourth metal member5. Any etching method can be used to etch the fourth metal member5as long as a targeted etching result can be obtained.

Next, as shown inFIG.23, by removing the resist material7in the tenth step, a desired pattern of the fourth metal member5can be formed (resist material removal step). To remove the resist material7, wet etching or dry etching can be used. To remove the resist material7leaving the targeted shape intact, it is better to selectively remove the resist material by wet etching. As for the etching solution to be used for the wet etching, any etching solution can be used as long as the resist material7can be removed with the targeted shape of the fourth metal member5maintained intact.

When etching the fourth metal member5using a metal mask, the metal mask is placed on the upper surface of the semiconductor element1with the fourth metal member5formed and sputter etching is performed to form the fourth metal member5into a desired shape.

Although in the above example, the fourth metal member5is formed on the upper surface of the third metal member4with the outer edge of the fourth metal member5disposed inside the outer edge of the third metal member4, also the second metal member3can be formed by using the similar method, as shown inFIG.23, on the upper surface of the first metal member2with the outer edge of the second metal member3disposed inside the outer edge of the first metal member2. The metal members and the bonding wire6can be formed in the same manner as in Embodiment.

In the semiconductor device configured as described above, the second metal member3is formed on the upper surface of the first metal member2, the third metal member4is formed on the upper surface of the second metal member3, and the bonding wire6with copper as the principal component is provided on an upper surface of the fourth metal member5corresponding to the formation position of the third metal member4, so that the impact of bonding of the bonding wire6on the underneath structure including the semiconductor element1can be reduced and the reliability of the semiconductor device can be improved.

Also, the outer edge of the fourth metal member5is disposed inside the outer edge of at least one of the first metal member2, the second metal member3, and the third metal member4, thereby reducing the total film thickness of the metal members at the contact position of the semiconductor element1and a metal member and thus reducing the stress generated in the semiconductor element1. As a result, the occurrence of damage such as cracking to the semiconductor element1can be suppressed and the reliability of the semiconductor device can be improved.

Embodiment 3 differs from Embodiment 1 and Embodiment 2 in that the insulation member8is disposed (inserted) in the peripheral area of at least one of the interfaces of the contiguous metal members from among the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5, which are used in Embodiment 1 and Embodiment 2. The disposed insulation member8in the peripheral area of the stacked contiguous metal members as described above can reduce the occurrence of stress in the peripheral area of the semiconductor element1. As a result, the insulation member8, which is softer than the metal members, can suppress the stress generation in the peripheral areas of the metal members, where stresses are likely to occur, and can suppress the occurrence of damage such as cracking in the semiconductor element1, thereby improving the reliability of the semiconductor device. Other respects are the same as in Embodiment 1 and Embodiment 2, so that the detailed descriptions will be omitted. Note that the insulation member8is in contact with and surrounds the side of at least one of the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5. The insulation member81is disposed in the peripheral area of at least one of the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5.

FIG.25is a schematic diagram of a planar structure showing a semiconductor device according to Embodiment 3.FIG.26is a schematic diagram of a cross-sectional structure showing the semiconductor device according to Embodiment 3.FIG.26is a schematic diagram of a cross-sectional structure along the alternate long and short dash line CC inFIG.25.

In the figure, a semiconductor device300includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, and the insulation member81.

InFIG.25, the bonding area61between the bonding wire6and the fourth metal member5is shown by the dashed line. The bonding area61of the bonding wire6is disposed inside the outer edge of the fourth metal member5. The bonding wire6is extended along a pair of opposite sides in the bonding area61of the bonding wire6. The insulation member81is disposed inside the outer edge of the fourth metal member5. The insulation member81has an opening82at a position corresponding to the bonding area61. The opening82of the insulation member81is shown by the chain double-dashed line. The inner edge of the insulation member81matches the outer edge of the opening82.

InFIG.26, the insulation member81is disposed in the peripheral area of the upper surface of the first metal member2. The insulation member81is absent in the area corresponding to the bonding area61where the bonding wire6is bonded to the upper surface of the fourth metal member5. In the insulation member8, the opening82is provided in the area corresponding to the bonding area61. The thickness of the second metal member3at the opening82of the insulation member81is thicker than the thickness of the second metal member3at the upper surface of the insulation member8by the thickness of the insulation member81. Thus, the shape of the second metal member3is such that the lower-surface side thereof protrudes in its center toward the upper surface of the first metal member2. The upper surface of the second metal member3is flat. Since the third metal member4is disposed on the flat upper surface of the second metal member3, the third metal member4has flat upper and lower surfaces. Similarly, since the fourth metal member5is disposed on the flat upper surface of the third metal member4, the fourth metal member5has flat upper and lower surfaces.

The insulation member8disposed between the layers of the first metal member2and the second metal member3divides (insulates from each other) the first metal member2and the second metal member3vertically in the peripheral area of the first metal member2where the insulation member81is disposed. Thus, using the insulation member81of lower hardness (softer) than the metal members, the first metal member2and the second metal member3are divided, so that the thickness of the metal members contributing to the stress generation is reduced compared to when the metal members are continuously stacked. This makes it possible to suppress the stress generation. Thus, by inserting the insulation member81, the stress applied to the semiconductor element1can be reduced, which leads to reducing damage to the semiconductor element1caused by cracking and thus improving the reliability of the semiconductor device200.

However, if the length of the insulation member81, formed in the peripheral area of the first metal member2, from the outer edge of the first metal member2toward the inside is too short, the reduction amount of the metal members is small and thus the stress relaxation effect is limited. As a result, the effect of controlling damage, such as caused by cracking, to the semiconductor element1is also limited. Conversely, if the length of the insulation member81from the outer edge of the first metal member2is too long, the area covered by the insulation member81on the upper surface of the first metal member2is too extensive. If the insulation member81with low heat dissipation extensively covers the upper surface of the first metal member2, heat dissipation from the semiconductor device200is hindered. Therefore, the length of the insulation member81from the outer edge of the first metal member2should preferably be from 10 μm to 100 μm. In other words, the length of the second metal member3existing on the upper surface of the insulation member81should be from 10 μm to 100 μm.

Polyimide, for example, may be used as a material for the insulation member81. However, the material is not limited to this as long as the similar effects can be achieved. In particular, a material of lower hardness than the metal members is desirable.

FIG.27is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 3.

In the figure, a semiconductor device301includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, and the insulation member81.

InFIG.27, the insulation member81is disposed in the peripheral area on the lower surface of the second metal member3. The insulation member81is absent in the area corresponding to the bonding area61where the bonding wire6is bonded to the upper surface of the fourth metal member5. The opening82is provided in the area of the insulation member81corresponding to the bonding area61. The thickness of the first metal member2disposed in the opening82of the insulation member81is thicker by the thickness of the insulation member8than the thickness of the first metal member2disposed in contact with the lower surface of the insulation member81. In other words, the thickness of the peripheral area of the first metal member2where the insulation member81is disposed is thinner by the thickness of the insulation member81than the thickness of the first metal member2in the opening82. In terms of shape, the first metal member2protrudes in its center toward the lower surface of the second metal member3. The upper surface of the second metal member3is flat. Since the third metal member4is disposed on the flat upper surface of the second metal member3, the third metal member4has flat upper and lower surfaces. Similarly, since the fourth metal member5is disposed on the flat upper surface of the third metal member4, the fourth metal member5has flat upper and lower surfaces.

FIG.28is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 3.

In the figure, a semiconductor device302includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, and the insulation member81.

InFIG.28, in terms of shape, the semiconductor device302has a shape of combination of the shape of the semiconductor device300and the shape of the semiconductor device301. The insulation member81is disposed across (on both sides of) the interface between the first metal member2and the second metal member3. In terms of shape, therefore, the first metal member2protrudes in its center toward the lower surface of the second metal member3. The second metal member3protrudes in its center toward the upper surface of the first metal member2. The protrusion of the first metal member2and the protrusion of the second metal member3are in contact to each other and surrounded by the insulation member81.

InFIG.28, the insulation member81is absent in the area corresponding to the bonding area61where the bonding wire6is bonded to the upper surface of the fourth metal member5. The opening82is provided in the area of the insulation member81corresponding to the bonding area61. The thickness of the first metal member2disposed in the opening82of the insulation member81is thicker by the corresponding thickness of the insulation member81than the thickness of the first metal member2disposed in contact with the lower surface of the insulation member81. The thickness of the second metal member3disposed in the opening82of the insulation member81is thicker by the corresponding thickness of the insulation member81than the thickness of the second metal member3disposed on the upper surface of the insulation member81. The thickness of the first metal member2disposed in the opening82of the insulation member81is thicker by the corresponding thickness of the insulation member81than the thickness of the first metal member2disposed in contact with the lower surface of the insulation member81. In other words, the thickness of the peripheral area of the first metal member2where the insulation member81is disposed is thinner by the corresponding thickness of the insulation member81than the thickness of the first metal member2in the opening82. The upper surface of the second metal member3is flat. Since the third metal member4is disposed on the flat upper surface of the second metal member3, the third metal member4has flat upper and lower surfaces. Similarly, since the fourth metal member5is disposed on the flat upper surface of the third metal member4, the fourth metal member5has flat upper and lower surfaces.

FIG.29is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 3.

In the figure, a semiconductor device303includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, and the insulation member81.

InFIG.29, the semiconductor device303has a shape formed by disposing the second metal member3, the third metal member4, the fourth metal member5, and the bonding wire6in accordance with (while maintaining) an upper shape formed when the insulation member81is disposed in the peripheral area of the upper surface of the first metal member2in the manufacturing process of the semiconductor device300. Thus, as for the shapes of the metal members, the second metal member3, the third metal member4, and the fourth metal member5each are convex downward (concave upward) in their respective areas corresponding to the opening82of the insulation member81. The bonding wire6also is convex downward in the bonding area61in accordance with the shape of the fourth metal member5.

InFIG.29, the insulation member81is disposed in the peripheral area of the upper surface of the first metal member2. The insulation member81is absent in the area corresponding to the bonding area61where the bonding wire6is bonded to the upper surface of the fourth metal member5. The opening82is provided in the area of the insulation member81corresponding to the bonding area61. Although the thickness of the second metal member3is uniform regardless of the formation position, in other words, whether the insulation member81is present or absent, the second metal member3is depressed (dented) by the thickness of the insulation member81at the opening82of the insulation member81. Since the third metal member4and the fourth metal member5are stacked on the upper surface of the second metal member3, their shapes are similar to that of the underlying second metal member3, accordingly. The bonding area61where the bonding wire6is bonded to the upper surface of the fourth metal member5is within the dent of the fourth metal member5, the dent corresponding to the opening82of the insulation member81. Thus, the bonding wire6protrudes in the area corresponding to the bonding area61.

FIG.30is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 3.

In the figure, a semiconductor device304includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, and the insulation member81.

InFIG.30, the semiconductor device304has a shape in which the upper surface of the fourth metal member5of the semiconductor device303shown inFIG.28is flattened. Except for the shape mentioned above, the semiconductor device304has the same shape as the semiconductor device303shown inFIG.28.

FIG.31is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 3.

In the figure, a semiconductor device305includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, the insulation member8, and the insulation member81.

InFIG.31, the outer edge of the semiconductor element1is disposed outside the outer edge of the first metal member2. Although the semiconductor device305has the same metal member configuration as the semiconductor device300shown inFIG.26, the semiconductor device305differs from the semiconductor device300in that the insulation member8is disposed such that the insulation member8is in contact with the sides of the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5in the peripheral area over the first main surface of the semiconductor element1and surrounds the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5. The side of the insulation member81disposed in the peripheral area on the upper surface of the first metal member2is in contact with the insulation member8disposed around the metal members.

FIG.32is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 3.

In the figure, a semiconductor device306includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, the insulation member8, and the insulation member81.

The semiconductor device306shown inFIG.32differs from the semiconductor device305shown inFIG.31in that the outer edge of the first metal member2of the semiconductor device is at the position of the outer edge of the insulation member8surrounding the first metal member2inFIG.31.

InFIG.31, the outer edge of the semiconductor element1is disposed outside the outer edge of the first metal member2. The outer edge of the first metal member2is disposed outside the outer edges of the second metal member3, the third metal member4, and the fourth metal member5. In the peripheral area on the upper surface of the first metal member2, the insulation member8is disposed in contact with the sides of the second metal member3, the third metal member4, and the fourth metal member5to surround these metal members. The outer edge of the insulation member8is flush with the outer edge of the first metal member2. The side of the insulation member81disposed in the peripheral area on the upper surface of the first metal member2is in contact with the insulation member8disposed around the metal members.

FIG.33is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 3.

In the figure, a semiconductor device307includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, and the insulation member81.

The semiconductor device307shown inFIG.33differs from the semiconductor device306shown inFIG.32in that the insulation member8that was disposed, as shown inFIG.32, in contact with the sides of the second metal member3, the third metal member4, and the fourth metal member5of the semiconductor device to surround these metal members is currently removed. The sides of the second metal member3, the third metal member4, and the fourth metal member5are exposed because the insulation member8that was disposed in contact with the sides of the second metal member3, the third metal member4, and the fourth metal member5to surround these metal members is removed. The outer edge of the semiconductor element1is disposed outside the outer edge of the first metal member2. The outer edge of the first metal member2is disposed outside the outer edges of the second metal member3, the third metal member4, and the fourth metal member5. In the peripheral area of the first metal member2, the insulation member81protrudes to expose its upper surface. The outer edge of the insulation member81is flush with the outer edge of the first metal member2.

FIG.34is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 3.

In the figure, a semiconductor device308includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, the insulation member8, and the insulation member81.

The semiconductor device308shown inFIG.34differs from the semiconductor device307shown inFIG.33in that the insulation member8is disposed in contact with the side of the first metal member2of the semiconductor device to surround the first metal member2. In the peripheral area on the first main surface of the semiconductor element1, the insulation member81covers the upper surface of the peripheral area of the first metal member2protruding outside the outer edge of the second metal member3, and the insulation member8is in contact with the side of the first metal member2. The outer edge of the semiconductor element1is disposed outside the outer edge of the first metal member2. The outer edge of the first metal member2is disposed outside the outer edges of the second metal member3, the third metal member4, and the fourth metal member5. The outer edge of the insulation member8is flush with the outer edge of the semiconductor element1.

FIG.35is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 3.

In the figure, a semiconductor device309includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, the insulation member8, and the insulation member81.

The semiconductor device309shown inFIG.35differs from the semiconductor device308shown inFIG.34in that the outer edge of the first metal member2is flush with the outer edges of the second metal member3, the third metal member4, and the fourth metal member5. The insulation member8is disposed in the peripheral area on the first main surface of the semiconductor element1. The outer edge of the semiconductor element1is disposed outside the outer edge of the first metal member2. The outer edge of the first metal member2is flush with the outer edges of the second metal member3, the third metal member4, and the fourth metal member5. The insulation member81is disposed in the peripheral area of the first metal member2. The outer edge of the insulation member81is flush with the outer edge of the first metal member2. The outer edge of the insulation member8is flush with the outer edge of the semiconductor element1.

FIG.36is a schematic diagram of a cross-sectional structure showing another semiconductor device according to Embodiment 3.

In the figure, a semiconductor device310includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, the insulation member8, and the insulation member81.

The semiconductor device310shown inFIG.36differs from the semiconductor device309shown inFIG.34in that the upper surface of the insulation member8is disposed above the upper surface of the fourth metal member5. In the peripheral area on the first main surface of the semiconductor element1, the insulation member8is disposed in contact with the sides of the first metal member2, the second metal member3, the third metal member4, and the fourth metal member5. The outer edge of the semiconductor element1is disposed outside the outer edge of the first metal member2. The outer edge of the insulation member8is flush with the outer edge of the semiconductor element1.

Next, the forming method of the insulation member81will be described.

One of the forming methods of the insulation member81, for example, is to form the insulation member81by patterning itself. When using the resist material described in Embodiment 2 to form the insulation member81, the same method as used when the fourth metal member5is patterned in Embodiment 2 can be used, in which the resist material, etc. is separately applied to the upper surface of the insulation member81.

When directly patterning the insulation member81as done to the resist material, the insulation member81can be formed by referring to the process of Embodiment 2 in which the resist material is replaced with the material of the insulation member81.

In the semiconductor device configured as described above, the second metal member3is formed on the upper surface of the first metal member2, the third metal member4is formed on the upper surface of the second metal member3, and the bonding wire6with copper as the principal component is provided on an upper surface of the fourth metal member5corresponding to the formation position of the third metal member4, so that the impact of bonding of the bonding wire6on the underneath structure including the semiconductor element1can be reduced and the reliability of the semiconductor device can be improved.

Also, the insulation member81is disposed between the layers of the peripheral areas of the first metal member2and the second metal member3, so that the stress generation can be suppressed compared to when the metal members are continuously stacked. Thus, by inserting the insulation member8, the stress applied to the semiconductor element1can be reduced, which leads to reducing damage to the semiconductor element1caused by cracking and thus improving the reliability of the semiconductor device.

Embodiment 4 differs from Embodiment 1, Embodiment 2, and Embodiment 3 in that the third metal member4is disposed only in the area corresponding to the bonding area61where the bonding wire6is bonded. Thus, the third metal member4is disposed only in the area corresponding to the bonding area61where the bonding wire6is bonded, so that the occurrence of cracking in the first metal member2due to the bonding wire6can be suppressed. Other respects are the same as in Embodiment 1, Embodiment 2, and Embodiment 3, so that the detailed descriptions will be omitted.

FIG.37is a schematic diagram of a cross-sectional structure showing a semiconductor device according to Embodiment 4.

In the figure, a semiconductor device400includes the semiconductor element1, the first metal member2, the second metal member3, the third metal member4, the fourth metal member5, the bonding wire6, which is the wiring member, with copper as the principal component, and the insulation member8.

In the figure, the third metal member4is in contact with the upper surface of the third metal member4in its lower surface and is covered by the fourth metal member5in its side and upper surfaces. The bonding wire6is disposed on the upper surface of the fourth metal member5right over the third metal member4in accordance with the location where the third metal member4is disposed.

The third metal member4is disposed (inserted) as described above in order to prevent a crack from occurring in the metal members starting from the disposed position of the bonding wire6on the upper surface of the fourth metal member5where the bonding wire6is bonded and thus to prevent the semiconductor element1from being damaged by the crack that occurs. Therefore, the third metal member4should be provided at least directly under the area where the bonding wire6is disposed. For example, if Ni is used for the third metal member4and Cu is used for the second metal member3and the fourth metal member5in this configuration, Ni, which is formed on part of the second metal member3, is surrounded by Cu and the proportion of Cu increases, accordingly. As a result, with a high thermal conductivity of Cu, which is higher than that of Ni, the heat dissipation from the semiconductor device400increases and thus the reliability of the semiconductor device400improves.

FIGS.38to43are each a schematic diagram of a planar structure showing the semiconductor device according to Embodiment 4.FIGS.37to42are each a plan view from above the upper surface of the fourth metal member5, where the third metal member4is shown by the dashed line.

InFIG.38, the shape of the third metal member4is rectangular (square). InFIG.39, the shape of the third metal member4is triangular. InFIG.40, the shape of the third metal member4is pentagonal. InFIG.41, the shape of the third metal member4is circular. InFIG.42, the shape of the third metal member4is cruciform. InFIG.43, the shape of the third metal member4is trapezoidal. Thus, the planar shape of the third metal member4may be, for example, polygonal or donut-shaped such as circular, oval, square, rectangular, pentagonal, hexagonal, triangular, trapezoidal, cross-shaped, and star-shaped. The third metal member4with such a shape should be disposed directly under the area where the bonding wire6is disposed. The third metal member4should preferably be larger than the bonding area61where the bonding wire6is bonded. As shown inFIGS.38to43, a plurality of third metal members4may be disposed in accordance with the number of the bonding wires6bonded to the upper surface of the fourth metal member5and their bonding areas61.

In the semiconductor device configured as described above, the second metal member3is formed on the upper surface of the first metal member2, the third metal member4is formed on the upper surface of the second metal member3, and the bonding wire6with copper as the principal component is provided on an upper surface of the fourth metal member5corresponding to the formation position of the third metal member4, so that the impact of bonding of the bonding wire6on the underneath structure including the semiconductor element1can be reduced and the reliability of the semiconductor device can be improved.

Because the third metal member4is disposed only in the area corresponding to the bonding area61where the bonding wire6is bonded, the occurrence of cracking in the first metal member2due to the bonding wire6can be suppressed.

Here, a power converter to which the semiconductor device described in Embodiments 1 to 4 above is applied will be described. Application of this disclosure is not limited to a specific type of power converter. In Embodiment 5, however, an example in which this disclosure is applied to a three-phase inverter will be described.

FIG.44is a block diagram showing a configuration of a power conversion system to which the power converter according to the present embodiment is applied.

The power conversion system, shown inFIG.44, includes a power supply1000, a power converter2000, and a load3000. The power supply1000, which is a DC power supply, supplies DC power to the power converter2000. For the power supply1000, various devices and systems, such as a DC system, a solar cell, and a storage battery can be used. Also, a rectifier circuit and an AC/DC converter, connected to an AC system, can be used for the power supply. Furthermore, a DC/DC converter that converts DC power outputted from the DC system to a predetermined power may be used for the power supply1000.

The power converter2000, which is a three-phase inverter connected between the power supply1000and the load3000, converts the DC power supplied from the power supply1000to AC power, and supplies the AC power to the load3000. As shown inFIG.44, the power converter2000includes a main conversion circuit2001, which converts DC power to AC power and outputs it, and a control circuit2003, which outputs a control signal for controlling the main conversion circuit2001to the main conversion circuit2001.

The load3000is a three-phase electric motor driven by the AC power supplied from the power converter2000. Note that the load3000is an electric motor installed in various electrical equipment, not being limited to any specific application. For example, it is an electric motor used in a hybrid car, an electric car, a railroad car, an elevator, and air conditioning equipment.

The following is a detailed description of the power converter2000. The main conversion circuit2001includes a switching device and a freewheeling diode (both not shown). The main conversion circuit2001converts the DC power supplied from the power supply1000to AC power by the switching operation of the switching device and supplies the AC power to the load3000. The specific circuit configurations of the main conversion circuit2001are various. The main conversion circuit2001according to the present embodiment is a three-phase full-bridge circuit with two levels and includes six switching devices and six freewheeling diodes each connected in reverse parallel to one of the switching devices.

At least one of the switching devices and the freewheeling diodes included in the main conversion circuit2001is the switching device or the freewheeling diode included in the semiconductor device2002corresponding to the semiconductor device according to at least one of Embodiments 1 to 4 described above. The six switching devices are combined into pairs. In each pair, the switching devices are connected in series to form a pair of upper and lower arms. Each pair of the upper and lower arms constitutes a phase (U-phase, V-phase, or W-phase) of the full bridge circuit. The output terminals of the pairs of the upper and lower arms, in other words, the three output terminals of the main conversion circuit2001, are connected to the load3000.

The main conversion circuit2001includes a drive circuit (not shown) to drive the switching devices. The drive circuit may be built in the semiconductor device2002or may be separately provided. The drive circuit generates a drive signal to drive the switching devices of the main conversion circuit2001and supplies it to the control electrodes of the switching devices of the main conversion circuit2001. Specifically, the drive circuit outputs a drive signal to turn on a switching device and a drive signal to turn off a switching device to their control electrodes in accordance with the control signal from the control circuit2003to be described later. The drive signal to keep a switching device in an ON state is a voltage signal (ON signal) above the threshold voltage of the switching device. The drive signal to keep the switching device in an OFF state is a voltage signal (OFF signal) below the threshold voltage of the switching device.

The control circuit2003controls the switching devices of the main conversion circuit2001so that the load3000is supplied with the power it needs. Specifically, the control circuit2003calculates the time (ON time) during which each of the switching devices of the main conversion circuit2001should be in an ON state on the basis of the power to be supplied to the load3000. For example, PWM control, in which ON time of each switching device is modulated in accordance with the voltage to be outputted, can be applied to the control of the main conversion circuit2001. A control command (control signal) is outputted to the drive circuit of the main conversion circuit2001in a timely manner so that an ON signal is outputted to the switching device that should be in an ON state and an OFF signal is outputted to the switching device that should be in an OFF state. The drive circuit outputs the ON signal or the OFF signal to the control electrode of each of the switching devices as a drive signal in accordance with this control signal.

The power converter2000according to the present embodiment uses the semiconductor device according to Embodiments 1 to 4 as the semiconductor device2002constituting the main conversion circuit2001. This makes it possible to bond, as the bonding wire6, a copper wire or the like on the bonding area61more firmly and in a better condition. This improves the reliability of the power converter2000.

In the present embodiment, an example is described, in which this disclosure is applied to a three-phase inverter with two levels. However, this disclosure is not limited as such and can be applied to various power converters. In the present embodiment, a power converter with two levels is used for description. However, this disclosure can also be applied to a multi-level power converter with three or more levels and even to a single-phase inverter if the load is single-phased. This disclosure can also be applied to a DC/DC converter, an AC/DC converter, and the like when supplying power to a DC load or the like.

Not limited to application to an electric motor as the load as described above, the power converter according to this disclosure can be used, for example, as a power supply system of an electric discharge machine, a laser processing machine, an induction heating cooker, and a non-contact power supply, and also as a power conditioner of a photovoltaic power generation system and a power storage system.

The configurations of the semiconductor device described in each embodiment may be combined in various ways as necessary.

The embodiments disclosed herein are illustrative, not restrictive. The scope of this disclosure is indicated by the scope of the claims, not by the scope of the descriptions provided above, and includes all modifications made within the meaning and scope equivalent to those of the claims.

DESCRIPTION OF SYMBOLS