Memory cell heights

Embodiments of the present disclosure provide methods, arrays, devices, modules, and systems for memory cell heights. One array of memory cells includes a number of semiconductor pillars having a number of charge storage nodes, each of the charge storage nodes being associated with a respective number of pillars and separated from the respective pillars by a dielectric. The array also includes a number of conductively coupled gates, each of the number of gates being associated with a respective one of the number of storage nodes. At least two pillars in the array have different heights.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor devices and, more particularly, to an array of memory cells having different heights.

BACKGROUND

Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications, including personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones, among others. Program code and system data, such as a basic input/output system (BIOS) which can be used in personal computing systems, are typically stored in flash memory devices.

Flash memories, comprised of a number of strings formed of one or more memory cells, are typically arranged into array architectures, e.g., a matrix. Two common types of flash memory array architectures are the “NAND” and the “NOR” architectures.

In the NOR array architecture, the floating gate memory cells of the memory array are typically arranged in a matrix. The NOR architecture floating gate memory array is accessed using a row decoder to activate a row of floating gate memory cells by selecting a word select line coupled to their gates. The data values of the row of selected memory cells are then placed on the column sense lines, a data value being indicated by the flow of current corresponding to a particular cell being in a programmed state or an erased state.

A NAND architecture also has its array of floating gate memory cells arranged in a matrix such that the control gates of each floating gate memory cell transistor of the array are typically coupled in rows by word select lines. However, each memory cell is not directly coupled to a column sense line. Instead, the memory cells are electrically coupled together in series, source to drain, between a source line and a column sense line, i.e., bit line, with the drain terminal for each transistor in a string being oriented towards the column sense line.

The NAND architecture memory array is also accessed using a row decoder activating a row of memory cells by selecting a word select line, e.g., row select line, coupled to their gates. A high bias voltage is applied to a selected gate's drain line SG(D). The word select lines coupled to the gates of unselected memory cells of each string are driven to operate the unselected memory cells of each group as pass transistors so that they pass current, e.g., at Vpass, in a manner that is unrestricted by their stored data values. In this manner, a selected transistor is tested for its ability to conduct current, which flows through each group of series-coupled transistors, restricted only by the selected memory cells of each string, thereby placing the current encoded data values of the row of selected memory cells on the column sense lines.

Memory cells in a NAND array architecture can be configured, e.g., programmed, to a desired state. That is, electric charge can be placed on, or removed from, the floating gate of a memory cell to put the cell into any of a number of stored states. For example, a single level cell (SLC) can represent two states, e.g., a 1 or 0. Flash memory multi state memory cells, multibit cells, or multilevel cells, which are referred to hereinafter using the term multilevel cells (MLCs), can be programmed into more than two possible states. MLCs allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one bit. MLCs can have more than one programmed state, e.g., a cell capable of representing four bits can have fifteen programmed states and an erased state, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 1110, 1000, 1010, 0010, 0110, and 0000.

MLC memory stores multiple bits on each cell by using different threshold voltage (Vt) levels for each state that is stored. The difference between adjacent Vt distributions may be very small for a MLC memory device as compared to a SLC memory device. The reduced margins between adjacent Vt distributions, e.g., program states, can increase the difficulty associated with distinguishing between adjacent program states, which can lead to problems such as reduced data read and/or data retrieval reliability.

Memory device fabricators are continuously seeking to increase performance. However, the scaling of memory cells is limited by the need to increase and/or maintain coupling between a control gate and a floating gate while minimizing the interference between adjacent floating gates. One method of increasing performance of a floating gate memory cell involves placing more memory cells in the same or a smaller area on a memory device. Unfortunately, this can lead to increased parasitic coupling of the gate stacks.

As NAND array architectures are scaled to smaller physical dimensions, the effects of charge located proximate any particular memory cell structure increases. Thus, charge stored on a floating gate of one memory cell can have an increasingly greater influence on the operation of adjacent memory cells as the distance between the semiconductor substrate pillars of adjacent memory cells decreases. Capacitive coupling increases between the structures forming the memory cells as transistors are formed closer together in more dense arrays. Quantitatively, capacitance is the ratio of charge and voltage (C=Q/V), with voltage being proportional to the product of electric field strength and distance. Therefore, as distance decreases in the denominator of the ratio, capacitance increases for a particular amount of charge.

DETAILED DESCRIPTION

Embodiments of the present disclosure provide methods, arrays, devices, modules, and systems for memory cell heights. One array of memory cells includes a number of charge storage nodes, each of the charge storage nodes being associated with a respective one of the number of pillars and separated from the respective pillars by a dielectric. The array also includes a number of conductively coupled gates, each of the number of gates being associated with a respective one of the number of storage nodes. At least two of the pillars in the array have different heights.

In one or more embodiments the memory cells are non-volatile floating gate memory cells arranged in rows, with the gates conductively coupled by a select line and columns coupled to sense lines. The cells along a given select line are formed on pillars fabricated to at least two different heights. In one or more embodiments a first group of pillars associated with the select line are fabricated to a first height and a second group of pillars associated with the select line are fabricated to a second height, the second height being greater than the first height by a distance at least as great as a thickness of the first dielectric.

In one or more embodiments, the cells along a given select line alternate between cells having a pillar fabricated to a first height and cells having a pillar fabricated to a second height. In other embodiments, adjacent pairs along the given select line are formed on pillars fabricated to either the first height or the second height.

Hereinafter, the terms “wafer” and “substrate” are used interchangeably and are to be understood as including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. As used herein, the term “substrate” or “substrate assembly” used in the following description may include a number of semiconductor-based structures that have an exposed semiconductor surface. The semiconductor need not be silicon-based. For example, the semiconductor can be silicon-germanium, germanium, or gallium-arsenide. When reference is made to “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in or on the semiconductor structure and/or foundation.

As used herein, “layer” can refer to a layer formed on a substrate using a deposition process. The term “layer” is meant to include layers specific to the semiconductor industry, such as “barrier layer,” “dielectric layer,” and “conductive layer.” The term “layer” is also meant to include layers found in technology outside of semiconductor technology, such as coatings on glass.

In the figures, the first digit of a reference number refers to the Figure in which it is used, while the remaining two digits of the reference number refer to the same or equivalent parts of embodiment(s) of the present disclosure used throughout the several figures. The scaling of the figures does not represent precise dimensions and/or dimensional ratios of the various elements illustrated herein.

As memory cells are scaled to smaller dimensions, distances between gate structures decrease. For a given amount of charge stored on a particular charge storage structure, e.g., a floating gate, capacitance increases as distances relative to the charge-storage structure decrease. Thus, associated capacitive coupling effects also increase. This increase in capacitive coupling results in greater interference between the floating gate of one cell, e.g., where charge is stored, and the floating gates of adjacent cells. Floating gate to channel capacitive coupling intensifies the problem of floating gate to floating gate coupling, and the interference caused thereby. The interference associated with this increased capacitive coupling becomes particularly problematic for 50 nanometer (nm) generation design rule and below for cell structures, e.g., cells separated by 50 nm or less. According to one or more embodiments of the present invention, memory cell structures are disclosed which should offset the effects of horizontal distance reductions, by increasing a vertical distance dimension between one cells storage node, e.g., floating gate, and storage nodes and/or channels in adjacent cells in order to mitigate capacitive coupling therebetween.

FIG. 1is a schematic of a portion of a non-volatile memory array100that can be used with embodiments of the present disclosure. The embodiment ofFIG. 1illustrates a NAND architecture non-volatile memory. However, embodiments described herein are not limited to this example. In various embodiments, the array100includes a number of multilevel memory cells (MLCs).

As shown inFIG. 1, the memory array100includes row-select lines103-1, . . . ,103-N and intersecting sense lines105-1,105-2,105-3, . . . ,105-M. The indicators “M” and “N” are used to indicate that the array100can include a number of row-select lines and a number of sense lines. For ease of addressing in the digital environment, the number of row-select lines103-1, . . . ,103-N and the number of sense lines105-1,105-2,105-3, . . . ,105-M are usually each some power of two, e.g., 256 row-select lines by 4,096 sense lines.

Memory array100includes NAND strings107-1,107-2,107-3, . . . ,107-M. Each NAND string includes non-volatile memory cells109-1, . . . ,109-N, each located at an intersection of a row-select line103-1, . . . ,103-N and a local sense line105-1,105-2,105-3, . . . ,105-M. The non-volatile memory cells109-1, . . . ,109-N of each NAND string107-1,107-2,107-3, . . . ,107-M are connected in series, source to drain between a select gate source (SGS) transistor, e.g., a field-effect transistor (FET)111, and a select gate drain (SGD) transistor, e.g., FET113. Source select gate111is located at the intersection of a local sense line105-1and a source select line115, while drain select gate113is located at the intersection of a local sense line105-1and a drain select line117.

As shown in the embodiment illustrated inFIG. 1, a source of source select gate111is connected to a common source line119. The drain of source select gate111is connected to the source of the memory cell109-1of the corresponding NAND string107-1. The drain of drain select gate113is connected to the local sense line105-1for the corresponding NAND string107-1at drain contact121-1. The source of drain select gate113is connected to the drain of the last memory cell109-N, e.g., floating-gate transistor, of the corresponding NAND string107-1.

In various embodiments, construction of non-volatile memory cells109-1, . . . ,109-N includes a source, a drain, a floating gate or other charge storage layer, and a control gate. Non-volatile memory cells,109-1, . . . ,109-N, have their control gates coupled to an associated row-select line,103-1, . . . ,103-N, respectively. Thus, a row of the non-volatile memory cells are commonly coupled to a given row-select line, e.g.,103-1, . . . ,103-N. A column of the non-volatile memory cells109-1, . . . ,109-N make up the NAND strings, e.g.,107-1,107-2,107-3, . . . ,107-M, coupled to a given local sense line, e.g.,105-1,105-2,105-3, . . . ,105-M, respectively. A NOR array architecture would be similarly laid out with the exception that the string of memory cells would be coupled in parallel between the select gates.

As will be described further below in connection with subsequent figures, various aspects of memory cell operational performance change as a NAND array architectures is scaled to smaller physical dimensions. These effects are due to quantities of charge being located in closer proximity to other memory cell structures, e.g., the charge stored on a floating gate of one memory cell is nearby the floating gate and channel of adjacent memory cells which tends to increase floating gate to floating gate, and floating gate to channel, interference due to capacitive coupling.

FIG. 2illustrates a side view of a memory cell200, taken along cut line2-2inFIG. 1, that can be included in an array of memory cells according to one or more embodiments of the present invention.FIG. 2illustrates a source region201and a drain region203formed in a substrate202with a channel region205therebetween. In the example illustration ofFIG. 2, the source region201and drain region203are n-type doped, formed in a p-type substrate202, to form an n-channel device. One of ordinary skill in the art will appreciate, however, that the doping types can be switched to form a p-channel device. A first gate206is shown separated from the substrate202by a first dielectric204. In one or more embodiments, described herein, the first gate can be a floating gate (FG). A second gate212is separated from the first gate206by a second dielectric208. In one or more embodiments, the second gate can be a control gate (CG), as the same is known in association with non-volatile floating gate memory cells. While non-volatile floating gate memory cells are described in connection with one or more embodiments, the embodiments discussed herein are not limited to non-volatile floating gate memory cells.

FIG. 3Aillustrates an end on cross-sectional view of a portion of an array of memory cells, taken along cut line3A-6B inFIG. 1, at a particular point in a semiconductor fabrication sequence according to a previous approach for fabricating memory cell structures.FIG. 3Aillustrates a dielectric layer304is formed over a surface303of a semiconductor substrate302. As the reader will appreciate, the dielectric layer304can eventually serve as a tunnel dielectric and be formed from such materials as silicon dioxide (SiO2), silicon nitrides (SiN/Si2N/Si3N4), silicon oxynitrides (SiOxNy), high K dielectrics, etc. A conductive layer, e.g., a doped polysilicon gate layer,306is formed over the dielectric layer304.

FIG. 3Billustrates a cross-sectional view of the portion of an array of memory cells fromFIG. 3A, taken along cut line3A-6B inFIG. 1, at another particular point in a semiconductor fabrication sequence according to a previous approach for fabricating memory cell structures. As shown inFIG. 3Bisolation regions309have been formed between adjacent columns of cells running into and out of the drawing sheet, e.g., columns107-1,107-2, etc., inFIG. 1, to reduce parasitic capacitance and/or cross talk between adjacent cells. As the reader will appreciate, the source and drain regions for these cell structures, e.g.,201and203inFIG. 2, would be located into and out of the drawing sheet respectively, hence not shown. One of ordinary skill in the art will appreciate the manner in which the isolation regions309can be formed by photolithographic etching, for example, to form trenches through the conductive306and dielectric304layers, and into the substrate (SUB)302, e.g., using a shallow trench isolation (STI) process, etc. As shown inFIG. 3B, the isolation regions309can be filled with a dielectric material308.

InFIG. 3Bthe isolation regions309have separated the conductive layer306to form gate structures306above semiconductor substrate pillars302. As the reader will appreciate, the gate structures306can be a floating gate structure306for a floating gate non-volatile memory cell. InFIG. 3B, each respective floating gate structure306is separated from a respective semiconductor substrate pillars302by a dielectric304. The dielectrics304separating the floating gate structures306from the semiconductor substrate pillars302have a particular thickness (D). Adjacent floating gates306are illustrated as separated by a particular horizontal distance, i.e., length (L1).

As one of ordinary skill in the art will appreciate source and drain regions, e.g.,201and203inFIG. 2, can be formed in the semiconductor substrate pillars302on opposing sides of the floating gate structures306, e.g., into and out of the page (not shown), forming a channel region therebetween underneath the dielectrics304in the semiconductor substrate pillars302where conduction can be made to occur. As the reader will appreciate, such source and drain regions,201and203inFIG. 2, are differentially doped from the channel formed between in the semiconductor substrate pillars302to create appropriate conduction characteristics.

As shown inFIG. 3B, in addition to a separation distance L1between adjacent floating gate structures306and a dielectric thickness D separating the floating gate structures306from the semiconductor substrate pillars302, a distance, i.e., length (L2), exists between the floating gate structure306of one cell and the channel in the semiconductor substrate pillar302of an adjacent cell. As mentioned above, a suitable dielectric material308, e.g. oxide-nitride-oxide (ONO), provides isolation between the floating gate structure306of one cell and the channel in the semiconductor substrate pillar302of an adjacent cell.

FIG. 3Cillustrates a cross-sectional view of the portion of the array of memory cells fromFIG. 3B, taken along cut line3A-6B inFIG. 1, at another particular point in a semiconductor fabrication sequence according to a previous approach for fabricating memory cell structures. As shown inFIG. 3Ca conductive layer, e.g., polysilicon layer,312has been deposited across the number of floating gate structures306. As shown inFIG. 3C, the conductive layer312is separated from the floating gate structures306by the dielectric material308. A portion of the dielectric material308may have been removed in regions310, e.g., using known etch techniques, to allow the conductive layer312to fill partially between the floating gate structures306.

As the reader will appreciate, the conductive layer312can serve as a control gate connected to a row select line for a row of cells in an array, e.g., row select lines103-1, . . . ,103-N shown inFIG. 1. In this arrangement, each semiconductor substrate pillar302shown would be part of a column of cells, e.g.,107-1,107-2, etc. shown inFIG. 1, running into and out of the drawing sheet. These columns of cells in the array would further be coupled to sense lines, e.g., sense lines105-1,105-2, etc., as shown inFIG. 1.

FIG. 3Cillustrates a first capacitive coupling (C1) (corresponding to distance L1) which occurs between floating gates306for adjacent columns of cells, e.g., columns of cells running into and out of the drawing sheet.FIG. 3Calso illustrates a second capacitive coupling (C2) (corresponding to distance L2) which occurs between the floating gates306for adjacent columns of cells, e.g., columns running into and out of the drawing sheet, and channel regions located in the semiconductor substrate pillars302for adjacent cells. The capacitor symbols are not intended to indicate that a capacitor structure is intentionally formed, but rather that adjacent gate structures and semiconductor substrate channel regions, e.g.,306and302, are inherently capacitively coupled by their proximity to one another. Such capacitive coupling occurs between each of the adjacent columns of cells running into and out of the drawing sheet.

FIGS. 4A-Dillustrates a cross-sectional views of a portion of an array of memory cells, taken along cut line3A-6B inFIG. 1, at various particular points in a semiconductor fabrication sequence according to one or more embodiments of the present invention. AlthoughFIG. 1, is referenced herein, and illustrates a NAND architecture for an array of memory cells, embodiments are not limited to either a NAND architecture or to floating gate non-volatile memory cells. Features of one or more embodiments described herein can be used in NOR type architectures as well as for an array of memory cells in other types of memory devices. The description ofFIGS. 4A-4Dis intended to illustrate one possible technique for forming semiconductor substrate pillars to different heights according to one or more embodiments of the present invention. The technique shown inFIGS. 4A-4Dis not to the exclusion of other suitable techniques as will be recognized by those of skill in the art upon reading this disclosure.

Although, for ease of illustration, the embodiments of theFIGS. 4A-D,5and6A-6B, will be discussed in relation to a non-volatile floating gate memory cell, one of ordinary skill in the art will appreciate that embodiments of the present disclosure are not so limited. In one or more embodiments, a memory cell, whose fabrication is illustrated in the figures that follow, includes a first dielectric, e.g., SiO2, separating a charge storage node, e.g., a floating gate, from the surface of a semiconductor substrate channel region, the channel region separating source and drain regions. In one or more embodiments, electron charge is stored in the floating gate, which can be associated for example with direct tunneling of the charge by methods such as direct Fowler-Nordheim tunneling or channel hot electron injection, from the substrate to the floating gate through the first dielectric layer, which causes a shift in the threshold voltage for the memory cell. The charge storage node, e.g., a floating gate, is further separated from a gate, e.g., control gate, by a second dielectric layer. In operation, current flow in the memory cell can be between the source and drain regions. The control gate is provided to turn the device on and provide a channel in the device such that a potential can be established between the source/drain regions. The floating gate is charged and stores the charge to control the threshold turn-on voltage of the device.

FIG. 4Aillustrates a cross-sectional view of a portion of an array of memory cells, taken along cut line3A-6B inFIG. 1, at a particular point in a semiconductor fabrication sequence according to one or more embodiments of the present invention. The portion of the array shown inFIG. 4Ais analogous to the portion of the array shown inFIG. 3B. That is, the portion of the array shows a number semiconductor substrate pillars402each having a floating gate406formed above and separated from the semiconductor substrate pillars by a dielectric404. Isolation regions409are illustrated, also filled with a suitable dielectric material408, separating columns of memory cells running into and out of the drawing sheet. In the embodiment ofFIG. 4A, alternating pillars are masked, e.g., represented by photolithographic masks415.

FIG. 4Billustrates a cross-sectional view of the portion of the array of memory cells fromFIG. 4A, taken along cut line3A-6B inFIG. 1, at another particular point in a semiconductor fabrication sequence according to one or more embodiments of the present invention. InFIG. 4B, through openings411in the mask415, the exposed floating gate material406, the dielectric material404, and a portion of the semiconductor substrate material402have been removed. One of ordinary skill in the art will appreciate the manner in which exposed floating gate material406, the dielectric material404, and a portion of the semiconductor substrate material402can be removed using directional and selective etching techniques as the same are known. The structure is now as shown inFIG. 4Bwith a first group of semiconductor substrate pillars having a surface fabricated to a first elevation in the plane of the substrate, e.g., first height (H1), and a second group of semiconductor substrate pillars having a surface fabricated to a second elevation in the plane of the substrate, e.g., second height (H2).

While the term “height” is used in reference to the elevation of a pillar surface with respect to a reference in the plane of the substrate material402, height does not necessarily connote a vertical direction. Height, as used herein, is taken to be in the direction by which a pillar projects from the plane of the substrate material402, e.g., perpendicular to the plane of the substrate material402from which the pillar is fabricated. As shown inFIG. 4B, the second height (H2) is greater than the first height (H1) by a distance represented by reference numeral418.

In the embodiment ofFIG. 4B, the floating gates406and dielectrics404remain above the semiconductor substrate pillars which were masked, e.g., have a height (H2). In one or more embodiments, the difference in height418between the first height (H1) and the second height (H2) is at least the equivalent of a thickness (D) of the dielectric404.

FIG. 4Cillustrates a cross-sectional view of the portion of the array of memory cells fromFIG. 4B, taken along cut line3A-6B inFIG. 1, at another particular point in a semiconductor fabrication sequence according to one or more embodiments of the present invention. In the embodiment ofFIG. 4C, the mask415, shown inFIG. 4B, is once again used to deposit dielectric404and floating gate406material in the openings411. The dielectric404material deposited in the openings411can be deposited to a thickness equivalent to a thickness (D) as the dielectric material above the semiconductor substrate pillars which were masked. In the embodiment ofFIG. 4Cthe floating gate406material deposited in the openings can be deposited to a level equivalent to that of the floating gates406which were masked to fill the openings411. The floating gate406material could also be deposited in the openings411to a level greater than even to the floating gates which were masked and the portion of the array then could be planarized.

One of ordinary skill in the art will appreciate the manner in which the dielectric404and floating gate material406can be deposited in the opening using chemical vapor deposition (CVD), physical vapor deposition (PVD) or other suitable technique. One of ordinary skill in the art will further appreciate the manner in which the materials can be planarized using a chemical mechanical planarization (CMP) process, or other suitable technique. Embodiments, however, are not so limited.

In the embodiment shown inFIG. 4Ceach of the floating gates406have a surface opposite dielectric404fabricated to a substantially equivalent elevation in the plane of the substrate, e.g., height H3. This structure can then be covered with a dielectric material413such as dielectric material408separating the columns of cells running into and out of the drawing sheet. The structure is now as appears inFIG. 4C.

FIG. 4Dillustrates a cross-sectional view of the portion of an array of memory cells, taken along cut line3A-6B inFIG. 1, at another particular point in a semiconductor fabrication sequence according to one or more embodiments of the present invention. InFIG. 4D, a sequence of processing steps can be performed similar to that described above in connection withFIG. 3C.

That is, as shown inFIG. 4D, a conductive layer, e.g., polysilicon layer,412has been deposited across the number of floating gate structures406. As shown inFIG. 4D, the conductive layer412is separated from the floating gate structures406by the dielectric material408. A portion of the dielectric material408may have been removed in regions410, e.g., using known etch techniques, to allow the conductive layer412to fill partially between the floating gate structures406.

As described in connection withFIG. 3C, the conductive layer412ofFIG. 4Dcan serve as a control gate connected to a row select line, parallel to the plane of the drawing sheet, for a row of cells in an array, e.g., row select lines103-1, . . . ,103-N shown inFIG. 1. In this arrangement, each semiconductor substrate pillar402shown would also be part of a column of cells, e.g.,107-1,107-2, etc. shown inFIG. 1, running into and out of the drawing sheet. These columns of cells in the array would further be coupled to sense lines, e.g., sense lines105-1,105-2, etc., as shown inFIG. 1.

FIG. 4Dillustrates a first capacitive coupling (C1) (corresponding to distance L1) which occurs between floating gates406for adjacent columns of cells, e.g., columns of cells running into and out of the drawing sheet. However, according to the one or more embodiments of the present disclosure there is now a distance (L3), which is greater than distance L2separating a floating gate406in one column of cells and a channel in the semiconductor substrate pillar402in an adjacent column of cells. This distance (L3) has associated with it a third capacitive coupling (C3) which will be weaker than the aforementioned C2on account of the distance L3being greater than that of L2for equivalent semiconductor substrate pillar spacing, e.g., in a 50 nm operation design rule, due to the difference in height418between the group of semiconductor substrate pillars having first heights (H1) and the group of semiconductor substrate pillars having second heights (H2).

In the embodiment ofFIG. 4D, a first group of semiconductor substrate pillars having a first height (H1) are labeled402A and included along a row of memory cells, running parallel to the plane of the drawing sheet, coupled to a particular select line412, e.g., select lines103-1,103-2, etc., shown inFIG. 1. A second group of semiconductor substrate pillars having a second height (H2) are labeled402B and are also included along the row of memory cells coupled to the particular select line. In the embodiment shown inFIG. 4D, the first group of semiconductor substrate pillars having the first height (H1) and the second group of semiconductor substrate pillars having the second height (H2) alternate between adjacent columns of cells running into and out of the drawing sheet. In one or more embodiments, within a given column of cells running into and out of the drawing sheet, e.g.,107-1,107-2, etc., as shown inFIG. 1, all cells will be associated with semiconductor substrate pillars having a first height (H1), or all cells will be associated with semiconductor substrate pillars having a second height (H2). As described below, however, embodiments are not so limited.

The embodiment ofFIG. 4Dthus illustrates floating gates406A being associated with semiconductor pillars fabricated to the first height (H1)402A and illustrates floating gates406B being associated with semiconductor pillars fabricated to the second height (H2)402B. In the embodiment ofFIG. 4Dthe thickness of floating gates406A is greater than the thickness of floating gates406B. As described in more detail in connection withFIG. 5, embodiments are not so limited. Floating gates406A and406B are one possible embodiment of a charge storage node, e.g., a structure for storing charge. However, embodiments of the present invention are not so limited, and the present disclosure is intended to encompass other structures and arrangements for storing charge as a means for implement information storage and retrieval. Thus, a gate associated with a charge storage node may be embodied as a control gate (as shown inFIG. 4D) for example, or some other structure configured to control operation of the associated charge storage node.

Indicated below the cross-sectional view of the array of memory cells is a tabulation of “PAGE” and “PROGRAM ORDER” nomenclature corresponding to columns of cells running into and out of the drawing sheet as associated with semiconductor substrate pillars having either a first (H1) or a second height (H2). In one or more embodiments, alternate columns of cells associated with semiconductor substrate pillars having either a first (H1) or a second height (H2) can be associated with different data pages. That is, in the embodiment shown inFIG. 4D, columns of cells associated with semiconductor substrate pillars having a first height (H1) are associated with EVEN data pages and columns of cells associated with semiconductor substrate pillars having a second height (H2) are associated with ODD data pages. Hence, in the embodiment ofFIG. 4D, along the particular row select line412, the first group of cells associated with semiconductor substrate pillars having the first height (H1)402A are shown alternating with the second group of cells associated with semiconductor pillars having the second height (H2)402B.

In one or more embodiments, as reflected inFIG. 4D, the EVEN data pages may be programmed together first, as indicated by the PROGRAM ORDER numeral “1”, and ODD data pages may be programmed together second, as indicated by the PROGRAM ORDER numeral “2”. Embodiments of the present invention, however, are not limited to the specific order set forth above in this example. That is, cells associated with semiconductor substrate pillars having the first height (H1)402A could be associated with ODD data pages and be programmed first and cells associated with semiconductor substrate pillars having the second height (H2) could be associated with EVEN data pages and be programmed second, etc.

As one of ordinary skill in the art will appreciate upon reading this disclosure, grouping alternate columns of cells running into and out of the drawing sheet together into particular groups of data cells, e.g., a page, and programming a particular group together can reduce interference by avoiding adjacent floating gates along a particular select line being simultaneously operated, hence attenuating capacitive coupling therebetween. For example, since floating gates along a particular select line are not being simultaneously being operated, e.g., programmed or erased, the impact of operating voltages applied to any given cell on that of its neighboring cells may be mitigated.

FIG. 5illustrates a cross-sectional view of a portion of an array of memory cells, taken along cut line3A-6B inFIG. 1, at a particular point in a semiconductor fabrication sequence according to one or more embodiments of the present invention. The embodiment ofFIG. 5illustrates an embodiment similar to that ofFIG. 4Din that adjacent columns of cells running into and out of the drawing sheet alternate between columns of cells associated with semiconductor pillars having a first height (H1)502A and cells associated with semiconductor pillars having a second height (H2)502B. However, in the embodiment ofFIG. 5, the deposition process described in connection withFIG. 4Cis different.

In the embodiment ofFIG. 5, the dielectric504deposited in the openings, e.g.,411shown inFIG. 4B, may be deposited to a uniform thickness, for example a thickness equivalent to thickness (D) inFIG. 4B, for those semiconductor pillars that were masked. However, by appropriate use of masking, the floating gate506A material for semiconductor substrate pillars fabricated to the first height (H1) is only deposited in the openings, e.g.,411shown inFIG. 4B, to reach a height (H4), which is reduced from the elevation, e.g., height H3, to which floating gate506B material for semiconductor substrate pillars fabricated to the second height (H2) is deposited. In one or more embodiments, the floating gate506A material for semiconductor pillars fabricated to the first height (H1) is deposited such that the thickness of the floating gate material506A is equivalent to the thickness of the floating gate506B material for semiconductor substrate pillars fabricated to the second height (H2), which were masked.

FIG. 6Aillustrates a cross-sectional view of a portion of an array of memory cells, taken along cut line3A-6B inFIG. 1, at a particular point in a semiconductor fabrication sequence according to one or more embodiments of the present invention. The embodiment ofFIG. 6Aillustrates a cross-sectional view along a particular select line612in which the first group of cells602A associated with semiconductor substrate pillars having a first height (H1) includes at least two adjacent cells along the given select line612and the second group of cells602B associated with semiconductor substrate pillars having a second height (H2) includes at least two adjacent cells along the given select line.

As the one of ordinary skill in the art will appreciate upon reading this disclosure, the embodiment ofFIG. 6Acan be formed by adjusting a mask, e.g., mask415as described in connection withFIG. 4A, to expose two or more adjacent cells along the particular select line612and hence forming two or more adjacent cells along the particular select line612to the same of one or more different heights, e.g., height (H1) or height (H2). Although forming semiconductor substrate pillars to two different heights (H1) and (H2) has been discussed herein. One of ordinary skill in the art will appreciate that more than two different semiconductor pillar heights can be achieved according to one or more embodiments of the present invention.

In one or more embodiments, adjusting a mask, e.g., mask415as described in connection withFIG. 4A, to expose two or more adjacent cells along the particular select line612and hence forming two or more adjacent cells along the particular select line612to the same of one or more different heights, e.g., height (H1) or height (H2), may provide an easier processing sequence in certain fabrication environments.

In the embodiment ofFIG. 6A, adjacent floating gates along a particular select line612, e.g.,606A/606A and606B/606B, as associated with semiconductor substrate pillars having a first height (H1) and second height (H2) respectively, are capacitively coupled across a distance L1, as indicated, for example, by capacitance C1inFIG. 6A. In this embodiment, floating gates606A are capacitively coupled to semiconductor substrate pillars602A across a distance L2, as has been associated with a capacitance C2(described above). However, floating gates606B are capacitively coupled to semiconductor substrate pillars602A across a greater distance, e.g., L3, which as described above results in a weaker capacitive C3.

The embodiment ofFIG. 6Aillustrates the floating gates,606A and606B associated with semiconductor substrate pillars having the first and the second heights, H1and H2, having the same vertical height, e.g., H3similar to that shown in the embodiment ofFIG. 4D. Embodiments ofFIG. 6A, however, are not so limited and embodiments may include forming the floating gates606A associated with semiconductor substrate pillars having the first height (H1) to a height (H4) and forming floating gates606B associated with semiconductor substrate pillars having the second height (H2) to a height (H3) such that floating gates606A and606B have a substantially equivalent height as the same has been described in connection withFIG. 5.

FIG. 6Billustrates a cross-sectional view of the portion of the array of memory cells fromFIG. 6Aillustrating a particular sense line mapping sequence according to one or more embodiments of the present invention. LikeFIG. 4D,FIG. 6Bindicates below the cross-sectional view of the array of memory cells a tabulation of “PAGE” and “PROGRAM ORDER” nomenclature corresponding columns of cells running into and out of the drawing sheet as associated with semiconductor substrate pillars having either a first (H1) or a second height (H2). However, the embodiment ofFIG. 6Bprovides an alternative mapping to the sense lines, e.g., bit lines BL0, BL1, BL2, etc., associated in numerical order with the columns of cells running into and out of the drawing sheet.

The sense lines, e.g., bit lines BL0, BL1, BL2, etc., may be physically formed in a fabrication sequence to be sequentially ordered with each adjacent column of cells running into and out of the drawing sheet. However, as indicated above, it may be desirable to associate a first group of cells associated with semiconductor pillars having a first height, e.g., height (H1), with a first programming order and a second group of cells associated with semiconductor substrate pillars having a second height, e.g., height (H2), with a second programming order. According to the embodiment described in connection withFIG. 6B, adjacent along a particular select line612a first group of cells602A associated with semiconductor substrate pillars having a first height (H1) may include at least two adjacent cells along the given select line612and the second group of cells602B associated with semiconductor substrate pillars having a second height (H2) may include at least two adjacent cells along the given select line612. Thus, physically adjacent sense lines, e.g., bit lines BL0and BL1, may both be physically connected to columns of cells associated with semiconductor pillars having a the same height, e.g., height (H1).

If the programming is designed to use a programming order which alternates between even and odd numbered sense lines, e.g., bit lines BL0and BL1, the order would be programming similar height semiconductor substrate pillars in both PROGRAM ORDER “1” and PROGRAM ORDER “2” according to physical topographical layout and methodology ofFIG. 4Dwhere columns alternate assignment between EVEN and ODD data pages. If as described above in connection withFIG. 4Dit is desirable to program a first group of cells associated with semiconductor substrate pillars having a first height (H1) as like pages, e.g., as EVEN or ODD pages, and to program a second group of cells associated with semiconductor substrate pillars having a second height (H2) as like pages, e.g., as EVEN or ODD pages, then mapping using control circuitry is employed according to one or more embodiments.

For example, in one embodiment control circuitry, e.g.,770inFIG. 7, is used for an array of cells arranged in rows coupled to select lines and columns coupled to sense lines, and for cells coupled to a given select line612to associate a first group of columns with cells associated with semiconductor substrate pillars602A having the first height H1with a first group of sense lines, e.g., EVEN bit lines BL0, BL2, BL4, etc. And, control circuitry, e.g.,770inFIG. 7, is used for cells coupled to the given select line612to associate a second group of columns with cells associated with semiconductor substrate pillars602B having the second height H2with a second group of sense lines, e.g., ODD bits lines BL1, BL3, etc. As shown in the embodiment ofFIG. 6B, the control circuitry, e.g.,770inFIG. 7, associating the first and the second group of columns, e.g., columns associated with semiconductor substrate pillars602A and602B, operates to associate non-adjacent sense lines, e.g., bit lines BL0and BL2with adjacent cells602A along select line612as EVEN pages having a PROGRAM ORDER “1”. Likewise, the control circuitry, e.g.,770inFIG. 7, associating the first and the second group of columns, e.g., columns associated with semiconductor substrate pillars602A and602B, operates to associate non-adjacent sense lines, e.g., bit lines BL1and BL3with adjacent cells602B along select line612as ODD pages having a PROGRAM ORDER “2”.

Hence, according to one or more embodiments, the control circuitry operates to map the first group of non-adjacent sense lines, e.g., BL0/BL2, to adjacent columns having the first group of cells associated with semiconductor substrate pillars having a first height (H1), and operates to map the second group of non-adjacent sense lines, e.g., and BL1/BL3, to adjacent columns having the second group of cells associated with semiconductor substrate pillars having a second height (H2).

In this manner, as reflected inFIG. 6B, the EVEN data pages associated with semiconductor substrate pillars having a first height (H1) may be programmed together first, as indicated by the PROGRAM ORDER numeral “1” and ODD data pages associated with semiconductor substrate pillars having a second height (H2) may be programmed together second, as indicated by the PROGRAM ORDER numeral “2”. Again, embodiments of the present invention, however, are not limited to the specific order set forth above in this example. That is, cells associated with semiconductor substrate pillars having the first height (H1)402A could be associated with ODD data pages and be programmed second and cells associated with semiconductor substrate pillars having the second height (H2) could be associated with EVEN data pages and be programmed first, etc.

As one of ordinary skill in the art will appreciate upon reading this disclosure, grouping particular columns of cells running into and out of the drawing sheet together into particular groups of data cells, e.g., a page, and programming a particular group together can reduce interference by avoiding adjacent floating gates along a particular select line from being simultaneously operated, hence attenuating capacitive coupling therebetween. That is, floating gate602A associated with BL2will be programmed at a different time from floating gate602A associated with BL0, as associated physically with the next adjacent sense line in the programming order, but still be mapped by control circuitry to the PROGRAM ORDER “1”.

FIG. 7illustrates a memory system730, which includes a processor732and is coupled to a memory device734that includes an array of memory cells701, e.g., a memory array such as array100shown inFIG. 1, which includes one or more embodiments of the present invention. The memory system730can include separate integrated circuits or both the processor732and the memory device734can be on the same integrated circuit. The processor732can be a microprocessor or some other type of controlling circuitry such as an application-specific integrated circuit (ASIC).

For clarity, the electronic memory system730has been simplified to focus on features with particular relevance to the present disclosure. The memory device734includes an array of non-volatile memory cells701, which can be floating gate flash memory cells with a NAND architecture. The control gates of each row of memory cells are coupled with a row-select line, while the drain regions of the memory cells are coupled to sense lines. The source regions of the memory cells are coupled to source lines, as the same has been illustrated inFIG. 1. As will be appreciated by those of ordinary skill in the art, the manner of connection of the memory cells to the sense lines and source lines depends on whether the array is a NAND architecture, a NOR architecture, and AND architecture, or some other memory array architecture.

The embodiment ofFIG. 7includes address circuitry740to latch address signals provided over I/O connections762through I/O circuitry760. Address signals are received and decoded by a row decoder744and a column decoder746to access the memory array701. In light of the present disclosure, it will be appreciated by those skilled in the art that the number of address input connections depends on the density and architecture of the memory array701and that the number of addresses increases with both increased numbers of memory cells and increased numbers of memory blocks and arrays.

The array of memory cells701includes cells that can utilize operating voltages associated with programming. The memory device734reads data in the memory array701by sensing voltage and/or current changes in the memory array columns using sense/buffer circuitry that in this embodiment can be read/latch circuitry750. The read/latch circuitry750can be coupled to read and latch a row of data from the memory array701. I/O circuitry760is included for bi-directional data communication over the I/O connections762with the processor732. Write circuitry755is included to write data to the memory array701.

Control circuitry770decodes signals provided by control connections772from the processor732. These signals can include chip signals, write enable signals, and address latch signals that are used to control the operations on the memory array701, including read, write, heal, and erase operations. In various embodiments, the control circuitry770is responsible for executing instructions from the processor732to perform the operating and programming embodiments of the present disclosure. The control circuitry770can be a state machine, a sequencer, or some other type of controller. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device detail ofFIG. 7has been reduced to facilitate ease of illustration.

FIG. 8illustrates memory module880as a memory card, although the concepts discussed with reference to memory module880are applicable to other types of removable or portable memory, e.g., USB flash drives, and are intended to be within the scope of “memory module” as used herein. In addition, although one example form factor is depicted inFIG. 8, these concepts are applicable to other form factors as well.

In some embodiments, memory module880will include a housing882(as depicted) to enclose one or more memory devices884, though such a housing is not essential to all devices or device applications. At least one memory device884includes an array of memory cells including at least two adjacent memory cells associated with semiconductor substrate pillars having different heights according to one or more embodiments of the present invention. Where present, the housing882includes one or more contacts888for communication with a host device. Examples of host devices include digital cameras, digital recording and playback devices, PDAs, personal computers, memory card readers, interface hubs and the like. For some embodiments, the contacts888are in the form of a standardized interface. For example, with a USB flash drive, the contacts888might be in the form of a USB Type-A male connector. For some embodiments, the contacts888are in the form of a semi-proprietary interface, such as might be found on CompactFlash™ memory cards licensed by SanDisk Corporation, Memory Stick™ memory cards licensed by Sony Corporation, SD Secure Digital™ memory cards licensed by Toshiba Corporation and the like. In general, however, contacts888provide an interface for passing control, address and/or data signals between the memory module880and a host having compatible receptors for the contacts888.

The memory module880may optionally include additional circuitry886, which may be one or more integrated circuits and/or discrete components. For some embodiments, the additional circuitry886may include a memory controller for controlling access across multiple memory devices884and/or for providing a translation layer between an external host and a memory device884. For example, there may not be a one-to-one correspondence between the number of contacts888and a number of connections to the one or more memory devices884. Thus, a memory controller could selectively couple an I/O connection (not shown inFIG. 8) of a memory device884to receive the appropriate signal at the appropriate I/O connection at the appropriate time or to provide the appropriate signal at the appropriate contact888at the appropriate time. Similarly, the communication protocol between a host and the memory module880may be different than what is required for access of a memory device884. A memory controller could then translate the command sequences received from a host into the appropriate command sequences to achieve the desired access to the memory device884. Such translation may further include changes in signal voltage levels in addition to command sequences.

The additional circuitry886may further include functionality unrelated to control of a memory device884such as logic functions as might be performed by an ASIC. Also, the additional circuitry886may include circuitry to restrict read or write access to the memory module880, such as password protection, biometrics or the like. The additional circuitry886may include circuitry to indicate a status of the memory module880. For example, the additional circuitry886may include functionality to determine whether power is being supplied to the memory module880and whether the memory module880is currently being accessed, and to display an indication of its status, such as a solid light while powered and a flashing light while being accessed. The additional circuitry886may further include passive devices, such as decoupling capacitors to help regulate power requirements within the memory module880.

CONCLUSION

Methods, arrays, devices, modules, and systems for memory cell heights have been shown. One array of memory cells includes a number of semiconductor substrate pillars having a first gate separated from the pillars by a first dielectric. A second gate is separated from the first gate by a second dielectric. At least two adjacent semiconductor substrate pillars in the array have different heights.