MICROELECTRONIC DEVICES INCLUDING A SELECTIVELY REMOVABLE CAP DIELECTRIC MATERIAL, METHODS OF FORMING THE MICROELECTRONIC DEVICES, AND RELATED SYSTEMS

A microelectronic device includes tiers of alternating dielectric and conductive materials, a cap oxide material vertically adjacent to the tiers, and pillars extending vertically through the tiers. The cap oxide material is formulated to exhibit a different etch rate relative to an etch rate of the oxide material of the tiers. Additional microelectronic devices, microelectronic systems, and methods of forming a microelectronic device are also disclosed.

TECHNICAL FIELD

Embodiments disclosed herein relate to microelectronic devices and microelectronic device fabrication. More particularly, embodiments of the disclosure relate to microelectronic devices including a cap dielectric material having a different property than a dielectric material of the underlying tiers, and to related systems and methods.

BACKGROUND

Memory devices provide data storage for electronic systems. A Flash memory device is one of various memory device types and has numerous uses in modern computers and other electrical devices. A conventional Flash memory device includes a memory array that has a large number of charge storage devices (e.g., memory cells, such as non-volatile memory cells) arranged in rows and columns. In a NAND architecture type of Flash memory, memory cells arranged in a column are coupled in series, and a first memory cell of the column is coupled to a data line (e.g., a bit line). In a three-dimensional NAND (3D NAND) memory device, a type of vertical memory device, not only are the memory cells arranged in row and column fashion in a horizontal array, but tiers of the horizontal arrays are stacked (e.g., vertically stacked) over one another to provide a three-dimensional array of the memory cells. The tiers include alternating conductive materials with insulating (e.g., dielectric) materials. The conductive materials function as control gates for, e.g., access lines (e.g., word lines) of the memory cells. Vertical structures (e.g., pillars including channel materials) extend along the vertical string of the memory cells. A drain end of a string is adjacent to one of the top and bottom of the vertical structure (e.g., pillar), while a source end of the string is adjacent to the other of the top and bottom of the pillar. The drain end is operably connected to a bit line, while the source end is operably connected to a source line. 3D NAND memory devices also include electrical connections between the access lines and other conductive structures of the device so that the memory cells of the vertical strings can be selected for writing, reading, and erasing operations. String drivers drive the access line voltages to write to or read from the memory cells of the vertical string.

As memory density increases in the 3D NAND memory devices, increased aspect ratios of pillars (e.g., the length of the pillar versus the width of the pillar opening) occurs. However, as the aspect ratios of pillars increases, possibilities for pillar misalignment, cell film voids, and reduced conductive connectivity also increases.

DETAILED DESCRIPTION

A microelectronic device (e.g., an apparatus, an electronic device, a semiconductor device, a memory device) is disclosed that includes a cap dielectric material that is formulated to be selectively removable (e.g., selectively etchable) relative to a dielectric material present in tiers of alternating dielectric materials and nitride materials used in the formation of the microelectronic device. The cap dielectric material is adjacent to an uppermost tier of the tiers of the electronic device and includes a step change at an interface between the cap dielectric material and the uppermost tier. The cap dielectric material exhibits a different quality (e.g., property) than the dielectric materials of the tiers, with the resulting quality enabling the selective removal of the cap dielectric material and corresponding formation of the step change. The cap dielectric material may, for example, exhibit a greater (e.g., faster) effective etch rate than an etch rate of the dielectric materials of the tiers when exposed to the same removal process conditions. Portions of the cap dielectric material are removed at different times (e.g., by different processes) to form pillar openings having a greater critical dimension (CD) at the top of the pillar openings and a smaller CD at the bottom of the pillar openings. The portions of the cap dielectric material are selectively removed without substantially removing the dielectric materials of the tiers. Cell films and conductive materials are subsequently formed in the pillar openings to form pillars and conductive elements. The different CDs at different locations of the pillar openings enable the cell films and conductive materials to be formed without forming voids in the resulting pillars. The different CDs also reduce misalignment between decks of the microelectronic device.

The following description provides specific details, such as material types, material thicknesses, and process conditions in order to provide a thorough description of embodiments described herein. However, a person of ordinary skill in the art will understand that the embodiments disclosed herein may be practiced without employing these specific details. Indeed, the embodiments may be practiced in conjunction with conventional fabrication techniques employed in the semiconductor industry. In addition, the description provided herein does not form a complete description of an electronic device or a complete process flow for manufacturing the electronic device and the structures described below do not form a complete electronic device. Only those process acts and structures necessary to understand the embodiments described herein are described in detail below. Additional acts to form a complete electronic device may be performed by conventional techniques.

As used herein, the singular forms of the terms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, the term “array region” means and includes a region of an electronic device including memory cells of a memory array. The array region of the electronic device includes active circuitry.

As used herein, the phrase “coupled to” refers to structures operatively connected with each other, such as electrically connected through a direct ohmic connection or through an indirect connection (e.g., by way of another structure).

As used herein, the term “deck” means and includes multiple (e.g., two or more) tiers of alternating nitride materials and dielectric materials (e.g., relative to a microelectronic device structure) or alternating conductive materials and dielectric materials (e.g., relative to a microelectronic device).

As used herein, the term “microelectronic device” includes, without limitation, an electronic device, such as a memory device, as well as a semiconductor device which may or may not incorporate memory, such as a logic device, a processor device, or a radiofrequency (RF) device. Further, a microelectronic device may incorporate memory in addition to other functions such as, for example, a so-called “system on a chip” (SoC) including a processor and memory, or a microelectronic device including logic and memory. The microelectronic device includes of tiers of alternating conductive materials and dielectric materials.

As used herein, the term “microelectronic device structure” means and includes a precursor structure to the microelectronic device, with tiers of alternating conductive materials and dielectric materials.

As used herein, the terms “horizontal” or “lateral” mean and include a direction that is parallel to a primary surface of the substrate on which the referenced material or structure is located. The width and length of a respective material or structure may be defined as dimensions in a horizontal plane. With reference to the figures, the “horizontal” or “lateral” direction may be perpendicular to an indicated “Z” axis and may be parallel to an indicated “X” axis, and the term “lateral” may be perpendicular to an indicated “Z” axis and may be parallel to an indicated “Y” axis.

As used herein, reference to an element as being “on” or “over” another element means and includes the element being directly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to), underneath, or in direct contact with the other element. It also includes the element being indirectly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to), underneath, or near the other element, with other elements present therebetween. In contrast, when an element is referred to as being “directly on” or “directly adjacent to” another element, no intervening elements are present.

As used herein, the term “non-array region” means and includes a region of the microelectronic device proximal to the array region.

As used herein, the term “selectively removable” means and includes a material that exhibits a greater removal rate responsive to exposure to a removal chemistry and/or removal conditions, collectively referred to herein as process conditions, relative to another material exposed to the same removal chemistry and/or removal conditions. A material that is selectively removable relative to another material is substantially completely removable without removing substantially any of the another material.

As used herein, the term “selectively etchable” means and includes a material that exhibits a greater etch rate responsive to exposure to a given etch chemistry and/or etch conditions relative to another material exposed to the same etch chemistry and/or etch conditions. For example, the material may exhibit an etch rate that is at least about five times greater than the etch rate of another material, such as an etch rate of about ten times greater, about twenty times greater, or about forty times greater than the etch rate of the another material. Etch chemistries and etch conditions for selectively etching a desired material may be selected by a person of ordinary skill in the art.

As used herein, the term “step change” means and includes an offset between sidewalls of vertically adjacent materials. For instance, the sidewalls of one of the materials of the vertically adjacent materials are recessed (e.g., laterally recessed) relative to the sidewalls of the other material.

As used herein, the term “substrate” means and includes a material (e.g., a base material) or construction upon which additional materials are formed. The substrate may be a microelectronic substrate, a semiconductor substrate, a base semiconductor layer on a supporting structure, an electrode, an electronic substrate having one or more materials, layers, structures, or regions formed thereon, or a semiconductor substrate having one or more materials, layers, structures, or regions formed thereon. The materials on the microelectronic substrate or semiconductor substrate may include, but are not limited to, semiconductive materials, insulating materials, conductive materials, etc. The substrate may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates and silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by Earth’s gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure (e.g., parallel to the Z-axis). The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. The height of a respective material or feature (e.g., structure) may be defined as a dimension in a vertical plane.

The following description provides specific details, such as material types and processing conditions, in order to provide a thorough description of embodiments of the disclosed apparatus (e.g., devices, systems) and methods. However, a person of ordinary skill in the art will understand that the embodiments of the apparatus and methods may be practiced without employing these specific details. Indeed, the embodiments of the apparatus and methods may be practiced in conjunction with conventional semiconductor fabrication techniques employed in the industry.

The fabrication processes described herein do not form a complete process flow for processing an apparatus (e.g., a microelectronic device, a semiconductor device, a memory device,), the structures thereof, or the systems. The remainder of the process flow is known to those of ordinary skill in the art. Accordingly, only the methods and structures necessary to understand embodiments of the present apparatus and methods are described herein.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. Unless the context indicates otherwise, the removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization, or other known methods.

FIGS.1through4Dare simplified cross-sectional views illustrating embodiments of a method of forming a microelectronic device structure (e.g., a memory device structure, such as a NAND structure) for a microelectronic device (e.g., a memory device, such as a NAND device). With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods described herein may be used to form various microelectronic devices, such as to form other microelectronic devices where 3D scaling is advantageous.

Referring toFIG.1, a microelectronic device structure100may be formed to include a deck102having tiers104of alternating nitride and dielectric materials106,108adjacent to (e.g., vertically adjacent to, over) a conductive material of a source (not shown) adjacent to (e.g., on) a substrate (not shown). The source is formed vertically adjacent to the substrate by conventional techniques. The alternating nitride materials106and dielectric materials108of the tiers104are formed adjacent to (e.g., vertically adjacent to, on) the source by conventional techniques. The nitride materials106may be, for example, at least one dielectric nitride material (e.g., a silicon nitride (SiNy)). In some embodiments, the nitride materials106may be silicon nitride. The dielectric materials108may be an electrically insulative material. By way of non-limiting example, the dielectric materials108may be formed of and include one or more of at least one dielectric oxide material, and are therefore sometimes referred to as alternating oxide materials, (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, and a MgOx), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric oxycarbide material (e.g., SiOxCy), at least one hydrogenated dielectric oxycarbide material (e.g., SiCxOyHz), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). In some embodiments, the dielectric materials108may be formed of and may include a dielectric oxide material (e.g., SiOx, such as SiO2). In other embodiments, the dielectric materials108include silicon dioxide, and may be configured to electrically isolate conductive materials. Each of the alternating materials (e.g., nitride materials106and dielectric materials108) may be substantially homogeneous in material composition, each of the alternating materials106,108may be heterogeneous in material composition, or one of the alternating materials106,108may be substantially homogenous in material composition, while the other is substantially heterogeneous in material composition.

The microelectronic device structure100may include one or more plugs110that are formed of a conductive material, such as tungsten or tungsten silicide. The plugs110may be formed by conventional techniques. An etch stop material112may be adjacent to (e.g., over, surrounds, or partially surrounding) the plugs110and adjacent to a lower portion of the pillars (FIG.4A, below).

The etch stop material112may be formed of and include at least one material this is selectively removable (e.g., selectively etchable) relative to the nitride materials106and the dielectric materials108of the tiers104. The etch stop material112may be formed by conventional techniques. The materials of the tiers104may be selectively etchable relative to the etch stop material112during common (e.g., collective, mutual) exposure to first removal conditions; and the etch stop material112may be selectively etchable relative to the alternating materials106,108during common exposure to second removal conditions. In some embodiments, the etch stop material112is formed of and includes a carbon nitride material (CNx). The etch stop material112may be substantially homogeneous in material composition, or the etch stop material112may be substantially heterogeneous in material composition.

After forming the desired number of tiers104, a cap dielectric material114is formed adjacent to an uppermost tier104of the deck102. The deck102may, for example, include, greater than or equal to 10 tiers, greater than or equal to 20 tiers, greater than or equal to 40 tiers, greater than or equal to 80 tiers, greater than or equal to 160 tiers, etc. A material of the cap dielectric material114is selected to be selectively removable relative to the nitride materials106and the dielectric materials108of the tiers104. The cap dielectric material114is also selectively removable relative to the etch stop material112. In some embodiments, the selective removal of the cap dielectric material114is achieved without including dopants or other impurities in the cap dielectric material114or in the dielectric materials108. Instead, the selective removal of the cap dielectric material114is achieved by appropriately selecting the materials of the cap dielectric material114and the dielectric materials108and/or the deposition techniques for forming the cap dielectric material114and the dielectric materials108. In other embodiments, the selective removal of the cap dielectric material114is achieved by including dopants in one or more of the cap dielectric material114or the dielectric materials108. For instance, the cap dielectric material114and the dielectric materials108may be formed of different materials (e.g., different material compositions) having sufficiently different etch rates. Alternatively, the cap dielectric material114and the dielectric materials108may be formed of similar materials (e.g., similar material compositions) by different techniques that result in the materials having sufficiently different etch rates to provide the etch selectivity.

By way of non-limiting example, the cap dielectric material114may be formed of and include at least one of a silicon oxide, a silicon oxycarbide, and a silicon oxynitride. For convenience, the cap dielectric material114may also be referred to herein as cap oxide material114. The cap dielectric material114may be doped or undoped to achieve the desired etch selectivity relative to the dielectric materials108. In some embodiments, the cap dielectric material114is formed of and includes silicon dioxide. The cap dielectric material114may be homogeneous in material composition or may be heterogeneous in material composition. The cap dielectric material114may be selectively removable relative to the dielectric materials108of the tiers104using the same removal conditions, such as the same etch chemistry and/or process conditions. For instance, the etch rate of the cap dielectric material114may be faster than the etch rate of the dielectric materials108when the cap dielectric material114and the dielectric materials108are exposed to a wet etch process.

The selective removal may be achieved even if the cap dielectric material114and the dielectric materials108exhibit substantially similar material compositions. For instance, by forming the cap dielectric material114and the dielectric materials108using different processes, such as different deposition processes, the cap dielectric material114may be selectively removable relative to the dielectric materials108. The cap dielectric material114may, for example, be a silicon oxide material that is deposited by one or more of CVD, PVD, ALD, or spin-coating over upper surfaces of the tiers104while the dielectric materials108are formed by a different one of CVD, PVD, ALD, or spin-coating. Alternatively, the same deposition process may be used to form the cap dielectric material114and the dielectric materials108, except one or more process parameter (e.g., temperature, precursor, other reaction conditions) is different to achieve the desired etch selectivity. By way of example only, the dielectric materials108may be formed by a CVD process and the cap dielectric material114may be formed by an ALD process, or the dielectric materials108may be formed by an ALD process conducted at a first temperature and/or a first pressure and the cap dielectric material114may be formed by an ALD process conducted at a different, second temperature and/or a second pressure. Alternatively, the dielectric materials108may be formed by an ALD process using a first ALD precursor and the cap dielectric material114may be formed by an ALD process using a second, different ALD precursor. In other words, the first ALD process differs from the second ALD process by at least one precursor.

The desired etch selectivity between the cap dielectric material114and the dielectric materials108may also be achieved by using a different deposition tool to form the cap dielectric material114than is used to form the dielectric materials108. For example, a first tool may be used to conduct a first insitu ALD process to form the cap dielectric material114or the dielectric materials108, and a second tool may be used to conduct a second exsitu ALD process to form the other of the cap dielectric material114or the dielectric materials108, where the second ALD process differs from the first by one or more parameters (e.g., temperature, precursor, other reaction conditions). However, the first and second tools are not limited to ALD tools. Rather, the first tool may include a CVD tool capable of depositing the dielectric materials108of the tiers104, while the second tool may be the same tool and is capable of forming the cap dielectric material114by a process having one or more different parameter (e.g., temperature, precursor, other reaction conditions) than the first tool. For example, a parameter (e.g., pressure) of the CVD tool may be altered after forming the alternating tiers104of nitride and dielectric materials106,108to form the cap dielectric material114. In some embodiments, a physical vapor deposition (PVD) process is used in forming the tiers104of alternating materials106,108, and a growth mechanism (e.g., ion bombardment, temperature, etc.) of the PVD process is altered before forming, and in order to form, the cap dielectric material114. Without being bound by any theory, it is believed that the different processes or the process conditions used to form the cap dielectric material114and the dielectric materials108alter the bonding characteristics (e.g., increase bond angle) of the resulting materials. For instance, different bonding characteristics may occur between silicon atoms and oxygen atoms of the materials, or between silicon atoms and hydroxide groups of the materials. The different bonding characteristics may cause the cap dielectric material114to exhibit a lower density than the dielectric materials108, enabling the cap dielectric material114to be selectively etchable. Deposition temperatures for forming the dielectric materials108, may range from about 20° C. to 1000° C., while deposition temperatures for forming the cap dielectric material114may be lower (e.g., ranging from about 20° C. to about 700° C.). In some embodiments, deposition temperatures for forming the dielectric materials108, may range from about 500° C. to 800° C., while deposition temperatures for forming the cap dielectric material114may range from about 250° C. to 650° C. In other embodiments, the deposition temperature for the cap dielectric material114is less than 100° C.

Pressures for forming the dielectric material108may range from about 0.1 torr to about 5 torr. In some embodiments, pressures for forming the dielectric material108may range from about 0.1 torr to about 3 torr. In other embodiments, pressures for forming the dielectric material108may range from about 0.5 torr to about 2 torr. Pressures for forming the cap dielectric material114may range from about 0.01 torr to about 5 torr. In some embodiments, pressures for forming the cap dielectric material114may range from about 0.01 torr to about 2 torr. In other embodiments, pressures for forming the cap dielectric material114may range from about 0.01 torr to about 0.5 torr.

The density of the cap dielectric material114may be less than a density of the dielectric material108. For example, an oxide density of the cap dielectric material114may range from about 2.0 g/cm3to about 2.5 g/cm3. In some embodiments, the oxide density of the cap dielectric material114may range from about 2.05 g/cm3to about 2.2 g/cm3. The density of the dielectric materials108may range from about 2.2 g/cm3to about 2.7 g/cm3.

A hard mask material116may be formed adjacent the cap dielectric material114by conventional techniques. The hard mask material116may be a doped hard mask material (e.g., a boron-doped hard mask material), a carbon hard mask material, or other hard mask material. In some embodiments, the hard mask material116is formed of and includes one or more of amorphous carbon and doped amorphous carbon (e.g., boron-doped amorphous carbon, such as boron-doped amorphous carbon comprising at least 1 weight percent (wt%) boron and at least 20 wt% carbon, such as between about 1 wt% boron and about 40 wt% boron, and between about 99 wt% carbon and about 60 wt% carbon). In other embodiments, the hard mask material116is a boron-doped hard mask material. In additional embodiments, the hard mask material116is a carbon hard mask material.

Referring toFIG.3, the hard mask material116may be patterned by conventional photolithography and etching techniques and the pattern transferred to the cap dielectric material114to expose the tiers104. The pattern may include linear and/or non-linear features and linear and/or non-linear openings. In some embodiments, an anisotropic etch process is performed to pattern the cap dielectric material114using the patterned hard mask material116as a mask. In other embodiments, an isotropic etch process is used to pattern the cap dielectric material114using the patterned hard mask material116as a mask. In some embodiments, first an anisotropic etch is used, followed by a subsequent isotropic etch. The removal conditions may be selected based on the materials used as the hard mask material116and the cap dielectric material114.

First portions118of the cap dielectric material114are removed to form openings adjacent to (e.g., vertically adjacent to, over) the plugs110and etch stop material112and to expose the tiers104. A width (e.g., W1) of the openings in the patterned hard mask material and the patterned cap dielectric material114corresponds to a critical dimension (CD) (e.g., W5) of pillars (seeFIG.4A) subsequently formed. The first portions118of the cap dielectric material114may be removed by a dry etch process or a wet etch process. The removal conditions used to remove the first portions118may be selected based on the materials used as the hard mask material116and the cap dielectric material114. In some embodiments, a thickness of the first portions118removed is less than a thickness of the cap dielectric material114. In other embodiments, a thickness of the first portions118removed is substantially equal to the thickness of the cap dielectric material114.

After patterning the cap dielectric material114, the hard mask material116is removed. Sidewalls of the patterned cap dielectric material114and an uppermost tier104of the alternating materials106,108define the openings over the plugs110and etch stop material112.

After exposing the uppermost tier104, underlying portions of the alternating nitride materials106and dielectric materials108of the deck102may be removed to form pillar openings120, into which channel material and cell film materials of the pillars (e.g., memory pillars) (FIGS.4A-4D) are subsequently formed. The pillar openings120extend through the tiers104and expose the etch stop material112. The pillar openings120may be formed by removing materials of the tiers104by conventional etch techniques, such as by a wet etch process or a dry etch process. The removal conditions may be selected based on the materials used as the tiers104. The pillar openings120proximal to the plugs110and distal to the plugs110exhibit substantially the same CD as the openings in the patterned hard mask material116and the patterned cap dielectric material114. Substantially no removal of the underlying materials of the plugs110, source, and substrate occurs during the formation of the pillar openings120.

In some embodiments, a wet etch process is used to form the pillar openings120. The etchant may comprise one or more of hydrofluoric acid (HF), a buffered oxide etchant (BOE), and nitric acid (HNO3). In some embodiments, the etchant comprises a solution including water and HF at a ratio within a range of from about500: 1 to about100:1.

The removal of the cap dielectric material114and the tiers104may be conducted by separate process acts, as described above, and performed with different tools, or at least at different times and using different parameters (e.g., pressure and/or temperature). Alternatively, the removal of the tiers104to form the pillar openings120and the removal of the portions of the cap dielectric material114may be conducted substantially simultaneously (e.g., occur within a single process act).

As shown inFIG.3, the pillar openings120may be high aspect ratio (HAR) openings defined by sidewalls124of the tiers104and sidewalls125of the cap dielectric material114. The pillar openings120are further defined by upper surfaces of the etch stop material112.

In some embodiments, the sidewalls125of the cap dielectric material114are substantially tapered (e.g., sloped) relative to the substantially vertical sidewalls124of the pillar openings120, similar to plug sidewalls ofFIG.4B, below. In other embodiments, the sidewalls125of the cap dielectric material114are bowed (e.g., concave) relative to the sidewalls124of the pillar openings120, similar to plug sidewalls ofFIG.4C. In additional embodiments, sidewalls125of the cap dielectric material114are curved (i.e., non-linear) relative to the sidewalls124of the pillar openings120, similar to plug sidewalls ofFIG.4D.

The width W3of an upper surface of a portion131of the cap dielectric material114is from about 20 to about 40 nanometers between horizontal boundaries. In some embodiments, the upper surface of the portion131may range from about 20 nanometers to about 30 nanometers in width (e.g., W3). In other embodiments the upper surface of portion131is from about 20.0 to about 21.5 nanometers in width. In some embodiments, the upper surface of portion131is substantially equal in dimension to the lower surface of the portion131of the cap dielectric material114. In other embodiments (FIGS.4B to4D), the width of the upper surface is not equal in dimension to a lower surface of the portion131.

After removing the first portions118of the cap dielectric material114, the sidewalls125of the cap dielectric material114and the tiers104may be substantially vertical, as indicated inFIG.3by dashed lines and inFIG.4A. Alternatively, the sidewalls of the cap dielectric material114and the tiers104may be sloped (seeFIGS.4B,4C). The width W1of the pillar openings120may be substantially the same proximal to the plugs110and distal to the plugs110. In other words, the width W1of the pillar openings120laterally adjacent to the cap dielectric material114and the width W1of the pillar openings120laterally adjacent to the tiers104may be substantially the same as one another.

The width W1of the pillar openings120laterally adjacent to the cap dielectric material114may be adjusted (e.g., increased) by conducting an additional removal act. The width of the pillar openings120may be increased to width W2by selectively removing second portions119of the cap dielectric material114without substantially removing the dielectric materials of the tiers104. The additional removal act may more precisely remove portions of the cap dielectric material114than were removed in the initial removal act. Removing the second portions119results in the formation of a step change122between the sidewalls124of the tiers and the sidewalls125of the cap dielectric material114. Following the additional removal act, the width (e.g., W2) of the pillar openings120laterally adjacent to the cap dielectric material114may be greater than the initial width (e.g., W1) of the pillar openings120. The removal conditions for increasing the width of the pillar openings120may be selected based on the materials used as the nitride materials106, the dielectric materials108, and the cap dielectric material114, and/or the deposition process to form the dielectric materials108and the cap dielectric material114. In some embodiments, the first portions118of the cap dielectric material114are removed by a dry etch process and the second portions119are selectively removed by a wet etch process.

The second portions119of the cap dielectric material114may be removed in a lateral direction. Removing the second portions119results in an increase in width of the pillar openings120laterally adjacent to the cap dielectric material114of from about 30% to about 40% compared to the width of the pillar openings120proximal to the plugs110. After removal of the second portions119, the sidewalls124of the tiers and the sidewalls125of the cap dielectric material114are no longer aligned relative to the step change122. The step change122may form a transitional interface between the lesser width of the pillars129and a greater width of the plugs130. A size of the step change122(e.g., amount of offset between sidewalls124and sidewalls125) may vary depending on a number of formation parameters, including but not limited to, a width, W3, of the cap dielectric material114between pillar openings120, a material composition of the cap dielectric material114, the sidewalls125being sloped or vertical, and/or a pitch of pillars formed in the pillar openings120. The step change122may form a substantially right angle (seeFIG.4A) if the sidewalls125are vertically offset from the sidewalls124, one or more angles less than about 90° if the sidewalls125are sloped (seeFIG.4B,FIG.4C), or curved surfaces if the sidewalls125are curved (i.e., non-linear) (seeFIG.4D).

In some embodiments, after a second etch process, sidewalls125of the cap dielectric material114are offset (e.g., laterally offset, laterally recessed) from the sidewalls of the tiers104by an amount of offset (e.g., recess) that is dependent on an amount of time a wet etch process is conducted. Depending on the time and the process conditions used, the sidewalls of the cap dielectric material114may be curved (seeFIG.4D), sloped (seeFIG.4B,FIG.4C), or may be substantially vertical (seeFIG.4A).

By removing the first portions118and the second portions119of the cap dielectric material114in separate process acts, the CD of the pillar openings120proximal to the plugs110(seeFIG.4A) may be maintained while widening the pillar openings120proximal to the plugs130. Therefore, after the second removal act, the widths of the pillar openings120proximal to the plugs110and distal to the plugs110may be different. By forming the pillar openings120having two or more different widths along a height thereof, the pillar openings120have a greater width at the top of the pillar openings120and a smaller width at the bottom of the pillar openings120, with the greater width laterally adjacent to the cap dielectric material114and the smaller width laterally adjacent to the tiers104. The width of the pillar openings120laterally adjacent to the tiers104corresponds to the CD of the pillar openings120, while the width of the pillar openings120laterally adjacent to the cap dielectric material114is greater. The different widths at different locations within the pillar openings120enable the cell films and conductive materials to be formed without forming voids in the resulting pillars.

In other words, the increased width of the pillar openings120laterally adjacent to the cap dielectric material114increases the process margin for subsequently conducted process acts. In conventional processes where a cap dielectric material is formed of the same dielectric material as the dielectric materials of the tiers, no step change would be present at the interface because the materials would be etched at substantially the same rates.

Referring toFIG.4A, nitride materials106of the tiers104are removed to form openings (not shown) between the dielectric materials108of the tiers104. Conductive materials126are formed in the openings between the dielectric materials108of the tiers104. The nitride materials106are, therefore, removed and replaced with the conductive materials126through a slit (not shown) as part of a so-called “replacement gate” or “gate last” process. The nitride materials106of the tiers may be removed by exposing the nitride materials to a wet etchant comprising one or more of phosphoric acid, sulfuric acid, hydrochloric acid, nitric acid, or another etch chemistry, such as a so-called “wet nitride strip” comprising a wet etchant comprising phosphoric acid.

After removal of the nitride materials106, conductive materials126may be formed between the neighboring dielectric materials108at locations corresponding to the previous locations of the nitride materials106to form a microelectronic device structure101comprising tiers of alternating levels of dielectric materials108and conductive materials126(e.g.,FIGS.4A to4D). The conductive materials126may function as access lines (e.g., word lines). One or more lower conductive materials126of the microelectronic device structure101may function as one or more lower select gate (e.g., at least one source side select gate (SGS)) and one or more upper conductive materials126may function as at least one upper select gate (e.g., at least one drain side select gate (SGD)) of the microelectronic device structure101.

The conductive materials126may include a conductive liner material (not shown) around the conductive materials126, such as between the conductive materials126and the dielectric materials108. The conductive liner material may comprise, for example, a seed material from which the conductive materials are formed. The conductive liner material may be formed of and include, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another material. In some embodiments, the conductive liner material comprises titanium nitride.

Channel and cell materials127are conformally formed on the sidewalls124of the tiers104and partially fill the pillar openings120. Although multiple materials are present, the channel material and cell materials127are shown as a single material inFIGS.4A-4Dfor convenience. The channel material may be polysilicon or other channel material as known in the art. The cell materials may be one or more of a dielectric material, a conductive material, etc. The cell material(s) may include one or more of an oxide material, a storage material, or a tunnel dielectric material as known in the art. By way of example only, the cell materials may include an oxide-nitride-oxide (ONO) structure having a dielectric material (e.g., a tunnel dielectric material), a charge trapping material, and a charge blocking material between the channel material and the dielectric materials or the conductive materials (described in greater detail below). The charge trapping material may be located directly between the dielectric material and the charge blocking material. In some embodiments, the dielectric material directly contacts the channel material and the charge trapping material. The charge blocking material may directly contact and may be located directly adjacent to the charge trapping material and the dielectric materials or the conductive materials.

Fill material128is formed in remaining portions of the pillar openings120to form pillars129(e.g., memory pillars) of the microelectronic device structure101. The fill material128may be a dielectric material, such as a silicon oxide material (e.g., silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, or a combination thereof), a metal oxide material (e.g., titanium dioxide, hafnium oxide, zirconium dioxide, tantalum oxide, magnesium oxide, hafnium magnesium oxide, aluminum oxide, or a combination thereof), or a combination thereof. In some embodiments, the fill material128may substantially and/or completely fill the pillar openings120in which the pillars are formed. In some embodiments, a portion of the fill material128is removed, such as by an etch process, forming recesses into which adjacent plugs130are formed. In other embodiments, the fill material128only partially fills the pillar openings120, and the conductive material for the plugs130is formed vertically adjacent to the fill material128in the remaining portions of the pillar openings120to form the pillars129.

The plugs130have one or more widths depending on how the sidewalls125of the cap dielectric material114are formed. For example, an upper width, W4, of the plugs130may be greater than a lower width, W5.

The lower width, W5, of the plugs130may be dependent on the pattern of the hard mask material116used to form the pillar openings120. The lower width, W5, of the plugs130may correspond to a width, or a critical dimension, of the pillar openings120. At least the upper width, W4, is increased by about 20% to 40% relative to the lower width, W5, of the plugs130. In some embodiments, at least the upper width, W4, is increased by about 20% to 30% relative to the lower width, W5, of the plugs130.

In some embodiments, the plugs130represent multiple additional conductive plugs that are not shown, and at least one of the total number of conductive plugs of the plugs130exhibits an increased horizontal dimension (e.g., width) relative to a horizontal dimension (e.g., width) of at least one pillar129. In other embodiments, the plugs130represent multiple conductive plugs that are not shown, and all of the conductive plugs of the plugs130exhibit an increased horizontal dimension (e.g., width) relative to respective horizontal dimensions (e.g., width) of each of the pillars129.

In some embodiments, the plugs130are formed of multiple, different conductive materials (e.g., metal alloys), and are substantially homogeneous in material composition (e.g., metal used to form alloys are uniformly distributed throughout the plug structure). In other embodiments, the plugs130are formed of multiple, different conductive materials, and are substantially heterogeneous in material composition (e.g., layered, doped, etc.). In additional embodiments, the plugs130are formed substantially of a single conductive material, and substantially homogenous in material composition.

Formation of the conductive materials126and pillars129may form strings of memory cells132. The memory cells132of the strings may be located at intersections of the channel and cell materials127and the conductive materials126, and may individually include a portion of one of the pillars129and a portion of one of the conductive material126. Vertically neighboring memory cells132of the strings may be separated from each other by one of the levels of the dielectric materials108.

In some embodiments, the cap dielectric material114electrically isolates conductive materials from one another (e.g., plugs130from other plugs and/or other conductive structures overlying the deck102). The cap dielectric material114may also electrically isolate another microelectronic device structure (e.g., CMOS control circuitry) from the conductive materials of the microelectronic device structure101. In some embodiments, the cap dielectric material114may be formed over each of an array region, a non-array region, and a periphery region. In other embodiments, the cap dielectric may114may be confined to one or two or more of the regions of the microelectronic device structure101.

In some embodiments, the selective removal of the cap dielectric material114is achieved without including dopants in the cap dielectric material114, such as by forming the cap dielectric material114and the dielectric materials108of the tiers104by different processes. Therefore, the microelectronic device structure is formed without affecting electrical performance of the resulting microelectronic device or downstream process acts.

Referring toFIG.4B, a microelectronic device structure101is depicted having plugs130with tapered sidewalls. The tapered sidewalls of the plugs130correspond to tapered sidewalls of the cap dielectric material114formed according to a selective removal of second portions119in the formation of another embodiment of microelectronic device structure101. The tapered sidewalls result in an upper width W6of the plugs130that is greater than a middle width W7, where the middle width W7is greater than a lower width W8.

An upper surface of the portion131of the cap dielectric material114may range from about 15 to about 30 nanometers between horizontal boundaries; whereas, a lower surface of the portion131may range from about 20 to about 40 nanometers. In some embodiments, a horizontal dimension of the upper surface of the portion131is about 20.0, 20.5, 21.0, 21.5, 22.0, 22.5 and 23.0 nanometers; while a horizontal dimension of the lower surface of the portion131is about 32.0, 32.5, 33.0, 33.5, 34.0, and 34.5 nanometers. In some embodiments, a horizontal dimension of the upper surface of portion131is less than a horizontal dimension of the lower surface of the portion131of the cap dielectric material114.

Referring toFIG.4C, a microelectronic device structure101is depicted having plugs130with linearly bowed sidewalls. The linear, bowed sidewalls of the plugs130correspond to linear, bowed sidewalls of the cap dielectric material114formed according to a selective removal of second portions119in the formation of another embodiment of microelectronic device structure101. The linearly bowed sidewalls result in an upper width W9of the plugs130that is less than a middle width W10, where the middle width W10is greater than a lower width W11.

An upper surface of the portion131of the cap dielectric material114may range from about 15 to about 30 nanometers between horizontal boundaries; whereas, a mid-section of the portion131may range from about 10 to about 20 nanometers in horizontal width, while a lower surface of the portion131may range from about 20 to about 40 nanometers. In other words, a horizontal dimension of the upper surface of portion131is greater than a horizontal dimension of the mid-section of the portion131; whereas, a horizontal dimension of the mid-section of the portion131is less than a horizontal dimension of the lower surface of the portion131of the cap dielectric material114.

Referring toFIG.4D, a microelectronic device structure101is depicted having plugs130with non-linear, bowed sidewalls. The non-linear, bowed sidewalls of the plugs130correspond to non-linear, bowed sidewalls of the cap dielectric material114formed according to a selective removal of second portions119in the formation of another embodiment of microelectronic device structure101. The non-linear, bowed sidewalls result in an upper width W12that is less than a middle width W13, where the middle width W13is greater than a lower width W14, where each of the respective dimensions continuously transition (e.g., curves) to another of the respective dimensions.

An upper surface of the portion131of the cap dielectric material114may range from about 20 to about 40 nanometers between horizontal boundaries; whereas, a mid-section of the portion131may range from about 15 to about 30 nanometers in horizontal width, while a lower surface of the portion131may range from about 20 to about 40 nanometers. In other words, a horizontal dimension of the upper surface of portion131is greater than a horizontal dimension of the mid-section of the portion131. Similarly, a horizontal dimension of the lower surface of the portion131of the cap dielectric material114is greater than a horizontal dimension of the mid-section of the portion131.

Accordingly, disclosed is a microelectronic device comprising tiers of alternating dielectric materials and conductive materials. Pillars extend vertically through the tiers, and a cap oxide material is vertically adjacent to the tiers. The cap oxide material is formulated to exhibit a different etch rate relative to an etch rate of the dielectric materials of the tiers.

Accordingly, disclosed is a microelectronic device comprising tiers of alternating dielectric materials and conductive materials, with pillars extending vertically through the tiers. A cap oxide material is over the tiers. Sidewalls of the cap oxide material are offset from the sidewalls of the tiers.

By forming the pillar openings120having different widths in upper portions and lower portions, the materials of the pillars and the plugs130subsequently formed in the pillar openings120may have different widths in the upper portions relative to the lower portions. The width of the plugs130in the upper portions (e.g., laterally adjacent to the cap dielectric material114) may be greater than the width of the pillars in the lower portions (e.g., laterally adjacent to the tiers104). The plugs130may also exhibit multiple widths. A width of an upper portion of the plugs130may be greater than a width of a lower portion of the plugs130. Therefore, the materials of the pillars and the plugs130may be formed in the pillar openings120without forming voids in (e.g., pinching off of) the pillars or the plugs130. Additionally, the conductive material of the plugs130exhibits a larger surface area than in electronic devices formed by conventional process, increasing the process margin for coupling (e.g., electrically coupling) additional conductive components (e.g., conductive elements) of the second deck to the plugs130. The increased surface area also facilitates improved landing between conductive structures of the first deck and conductive structures of the second decks. Therefore, the electronic device is formed without affecting electrical performance or downstream process acts

In addition, substantial vertical alignment between the pillars of a first deck and pillars of a second deck is increased. Channel materials, cell materials, and conductive elements of the second deck that are subsequently formed over the first deck may have an increased process margin for coupling with the channel material and the cell materials of the first deck. The channel materials of the second deck may extend substantially continuously between the first and second decks. Therefore, misalignment between the decks is substantially reduced compared to conventional electronic devices. In such conventional electronic devices, misalignment occurs between conductive components of the decks, leading to electrical shorts. Therefore, microelectronic devices including the microelectronic device structures101ofFIGS.4A-4Dmay be formed without affecting electrical performance or downstream process acts.

Referring toFIG.5, a portion of a microelectronic system includes microelectronic device structure500, having multiple decks502, each with respective tiers504of alternating dielectric and conductive materials similar to microelectronic device structure101. The multiple decks502may include an upper deck505, a lower deck507, and an interdeck dielectric509between the lower deck507and the upper deck505. Each deck of the multiple decks502may be formed according to the previously described methods. The pillars of the upper deck505are aligned and electrically connected, according to the previously described methods, with the landing surfaces (e.g., plugs) of the lower deck507. In some embodiments, the upper deck505comprises an uppermost deck of a microelectronic device structure.

Referring toFIG.6, a method600of forming the microelectronic device structure101includes an act602of forming a deck of a microelectronic device structure (e.g., microelectronic device structure100), having tiers of alternating nitride and dielectric materials.

The act604includes forming a patterned cap dielectric material adjacent to, or vertically above, an uppermost tier of the deck. The patterned cap dielectric material is used to form the underlying structures, such as pillar openings, in the cap dielectric material.

The act606includes selectively removing first portions of the cap dielectric material, without removing the materials of the tiers. In some embodiments, the selective removal of first portions of the cap dielectric material may occur as a result of forming the underlying structures (e.g., pillar openings) in the cap dielectric material due to differences in etch selectivity between the cap dielectric material and the alternating materials of the tiers. Only the first portions of cap dielectric material are removed when forming the underlying structures.

Upon removal of the first portions of cap dielectric material, in some embodiments, the act608includes removing portions of the tiers exposed through the patterned cap dielectric material to form pillar openings in the one or more decks of alternating materials. This removal act608occurs prior to metallization. In other embodiments, the material removal of act608occurs during act606.

The act610includes the selective removal of second portions of the cap dielectric material, without substantially removing the materials of the tiers. In some embodiments, the first portions of the cap dielectric are removed simultaneous with the removal of the materials of the tiers, and the second portions of the cap dielectric material are removed without affecting the material of the tiers. In other embodiments, the first portions of the cap dielectric are removed without removing the materials of the tiers, such that a removal of the materials of the tiers precedes the selective removal of the second portions of the cap dielectric material. In additional embodiments, both first and second portions of the cap dielectric material are removed when forming the underlying structures due to the etch selectivity of the cap dielectric material relative to the dielectric material of the tiers, such that a final CD of the pillar openings may be obtained using a single material removal process (e.g., with etch chemistries varied insitu relative to the different materials to be removed). In these embodiments, the act608is optional.

The selective removal of the second portions of the cap dielectric material may depend on one or more formation parameters612previously obtained, adjusted, or controlled during the formation of either the cap dielectric material or the dielectric material of the tiers of alternating materials. For example, the formation parameters612may include, but is not limited to, an etch selectivity (e.g., of the cap dielectric vs. the dielectric of the tiers), an oxide density, an etch type (e.g., wet, dry, vapor, CMP, etc.) used to form the structures underlying the patterned hard mask material, etch chemistry, material formation precursors, chemical bond formation (e.g., resulting different material densities), and combinations thereof.

Act614occurs after formation of a slit structure through the tiers, and includes removing (e.g., exhuming) the nitride materials of the tiers of alternating materials. The voids created by their removal may be filled with conductive materials, forming alternating conductive and dielectric materials within the tiers of the deck of the microelectronic device structure (e.g., microelectronic device structure101).

The act616of forming cell, channel, fill and/or plug materials in the pillar openings facilitates the formation of pillars and plugs of the microelectronic device structure. The pillars and plugs facilitate the electrical connection of a first deck (e.g., lower deck) with another deck (e.g., upper deck), or the electrical connection of a deck with another microelectronic device structure (e.g., CMOS).

Accordingly, disclosed is a method of forming a microelectronic device that includes forming tiers of alternating nitride materials and dielectric materials, and forming a cap dielectric material adjacent to the tiers. A first portion of the cap dielectric material is removed to form a patterned cap dielectric material. Portions of the tiers exposed through the patterned cap dielectric material are removed to form pillar openings in the tiers, and a second portion of the cap dielectric material is removed without substantially removing the nitride materials and the dielectric materials of the tiers. A channel material and cell film materials is formed in the pillar openings, and the nitride materials of the tiers are removed to form spaces between the dielectric materials of the tiers. A, conductive material is formed in the spaces.

Referring toFIG.7, microelectronic device structures101of the disclosure may be included in microelectronic devices (e.g., memory devices) of the disclosure. For example,FIG.7illustrates a partial cutaway perspective view of a portion of a microelectronic device700(e.g., a memory device, such as a 3D NAND Flash memory device) including a microelectronic device structure substantially similar to the microelectronic device structure101at or following the processing stage previously described with reference toFIGS.4A to4D. For clarity and ease of understanding the drawings and associated description, some features (e.g., structures, materials) of the microelectronic device structure101previously described herein are not shown inFIG.7. However, it will be understood that any features of the microelectronic device structure101at or preceding a processing stage previously described with reference toFIGS.4A to4D, and that have been described herein with reference to one or more ofFIGS.1through4D, may be included in a microelectronic device structure of the microelectronic device700described herein with reference toFIG.7.

As shown inFIG.7, the microelectronic device700may include a deck structure702including a vertically alternating (e.g., in the Z-direction) sequence of conductive structures726and insulative structures708arranged in tiers704each including at least one of the conductive structures726vertically adjacent at least one of the insulative structures708. The deck structure702, the conductive structures726, the insulative structures708, and the tiers704may respectively correspond to the deck102, the conductive structures (e.g., conductive materials126), the insulative structures (e.g., dielectric materials108), and the tiers104previously described with reference toFIGS.4A to4D. In addition, the microelectronic device includes cell pillar structures732corresponding to the structures of the cell pillars129previously described with reference toFIGS.4A to4D, vertically extending through the deck structure702. Intersections of the cell pillar structures732and the conductive structures726of the deck structure702form strings of memory cells728vertically extending through the deck structure702. The conductive structures726may serve as local access line structures (e.g., local word line structures) for the strings of memory cells728. Furthermore, the microelectronic device700may also include one or more staircase structures715having steps717defined by edges (e.g., horizontal ends in the X direction) of the tiers704of the deck structure702. The steps717of the staircase structures715may serve as contact regions for the conductive structures726of the deck structure702.

The microelectronic device700may further include at least one source structure719, access line routing structures721, first select gates723(e.g., upper select gates, drain select gates (SGDs)), select line routing structures725, one or more second select gates727(e.g., lower select gates, source select gate (SGSs)), digit line structures729, access line contact structures731, and select line contact structures733. The digit line structures729may be coupled to the cell pillar structures732by way of additional contact structures, plug structures, and pillar contact structures. For example, the digit line structures729may vertically overlie and physically contact the additional contact structures; the additional contact structures may vertically overlie and physically contact the plug structures; the plug structures may vertically overlie and physically contact the pillar contact structures; and the pillar contact structures may physically contact the cell pillar structures732(e.g., corresponding to the cell pillars129(FIGS.4A to4D)). In addition, the access line contact structures731and the select line contact structures733may couple additional features of the microelectronic device700to one another as shown (e.g., the select line routing structures725to the first select gates723, the access line routing structures721to the conductive structures726of the tiers704of the deck structure702).

The microelectronic device700may also include a base structure735positioned vertically below the cell pillar structures732(and, hence, the strings of memory cells728). The base structure735may include at least one control logic region including control logic devices configured to control various operations of other features (e.g., the strings of memory cells728) of the microelectronic device700. As a non-limiting example, the control logic region of the base structure735may further include one or more (e.g., each) of charge pumps (e.g., VCCP charge pumps, VNEGWL charge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuitry (e.g., ring oscillators), Vddregulators, drivers (e.g., string drivers), page buffers, decoders (e.g., local deck decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs), PMOS sense amplifiers (PSAs)), repair circuitry (e.g., column repair circuitry, row repair circuitry), I/O devices (e.g., local I/O devices), memory test devices, MUX, error checking and correction (ECC) devices, self-refresh/wear leveling devices, and other chip/deck control circuitry. The control logic region of the base structure735may be coupled to the source structure719, the access line routing structures721, the select line routing structures725, and the digit line structures729. In some embodiments, the control logic region of the base structure735includes CMOS (complementary metal-oxide-semiconductor) circuitry. In such embodiments, the control logic region of the base structure735may be characterized as having a “CMOS under Array” (“CuA”) configuration. Although a CuA configuration is depicted, in other embodiments, the base structure735may be located above the digit line structures729and configured as a “CMOS over Array” (“CoA”) device.

Microelectronic device structures (e.g., the microelectronic device structure101at or following the processing stage previously described with reference toFIGS.4A to4D) and microelectronic devices (e.g., the microelectronic device700(FIG.7)) in accordance with embodiments of the disclosure may be used in embodiments of electronic systems of the disclosure.

The microelectronic device700according to embodiments of the disclosure may include, but is not limited to, a 3D electronic device, such as a 3D NAND Flash memory device, such as a multideck 3D NAND Flash memory device. The microelectronic device700formed according to embodiments of the disclosure may be used in any 3D microelectronic device where reduced or eliminated pillar misalignment is desired.

For example,FIG.8is a block diagram of a microelectronic system800implemented according to one or more embodiments described herein. The microelectronic system800may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPad® or SURFACE@ tablet, an electronic book, a navigation device, etc. The microelectronic system800includes at least one memory device802, which includes one or more microelectronic device structures101as previously described. The microelectronic system800may further include at least one processor804, such as a microprocessor, to control the processing of system functions and requests in the microelectronic system800. The processor804and other subcomponents of the microelectronic system800may include the memory cells. The processor804may, optionally, include one or more microelectronic device structures101as previously described relative toFIGS.4A to4D.

Various other devices may be coupled to the processor804depending on the functions that the microelectronic system800performs. For example, an input device806may be coupled to the processor804for inputting information into the microelectronic system800by a user, such as, for example, a mouse or other pointing device, a button, a switch, a keyboard, a touchpad, a light pen, a digitizer and stylus, a touch screen, a voice recognition system, a microphone, a control panel, or a combination thereof. An output device808for outputting information (e.g., visual or audio output) to a user may also be coupled to the processor804. The output device808may include an LCD display, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or a combination thereof. The output device808may also include a printer, an audio output jack, a speaker, etc. In some embodiments, the input device806and the output device808may comprise a single touchscreen device that can be used both to input information to the microelectronic system800and to output visual information to a user. The one or more input devices806and output devices808may communicate electrically with at least one of the memory devices802and the processor804. The at least one memory device802and processor804may also be used in a system on chip (SoC).

Accordingly, disclosed is a microelectronic system comprising an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device may be made up of one or more decks including tiers of alternating oxide materials and conductive materials. The memory device may further include pillars extending vertically through the one or more decks and a cap material over the one or more decks. The cap material may include a different oxide material than the oxide materials of the tiers. The memory device may further include a plug laterally adjacent to the cap material and overlying the pillars, where the plug exhibits two or more different widths along a height thereof.