CELL SITE DEVICE AND ASSOCIATED CLOCK SYNCHRONIZATION METHOD

A cell site device and an associated clock synchronization method are provided. The cell site device includes a clock synchronizer, a first processing circuit, and a second processing circuit. The clock synchronizer generates a first operation clock and a second operation clock. The first operation clock and the second operation clock have a specific synchronous relationship, and the clock synchronizer is adjusted by a synchronizer setting signal. The first processing circuit generates the synchronizer setting signal according to one of an external clock synchronization source and an internal clock signal. The clock synchronizer respectively transmits the first operation clock and the second operation clock to the first processing circuit and the second processing circuit. The first processing circuit generates a cross-unit periodic synchronization signal and transmits the cross-unit periodic synchronization signal to the second processing circuit.

TECHNICAL FIELD

The disclosure relates in general to a cell site device and an associated clock synchronization method, and more particularly to a cell site device and an associated clock synchronization method capable of freely switching clock synchronization sources so that synchronization relationship between processing circuits can be maintained.

BACKGROUND

Small cells can be considered as base stations developed with distributed radio technology. Mobile operators utilize small cells to extend service coverage in-building and/or outdoors. Small cells are electronic devices that play a significant role in 4G and 5G technologies, and the clock synchronization issue of the small cells is a concern in the present disclosure. In the specification, the clock synchronization may represent frequency, phase, and/or time synchronization.

A radio access network (RAN) decomposition classifies RAN's functions into a radio unit (hereinafter, RU) component, a distributed unit (hereinafter, DU) component, and a central unit (hereinafter, CU) component. The distribution of the RAN functions across the RU component, DU component, and CU component is dependent on the RAN functional split option, and the RAN functional split operation may vary in practical applications.

Clock synchronization (for example, frequency synchronization, time synchronization, and phase synchronization) is an essential requirement for cell site devices. In the specification, the clock synchronization sources of the RU component, DU component, and CU component in a cell site device having an all-in-one structure are concerned.

FIG.1(prior art) is a schematic diagram illustrating the clock synchronization approach adopted in a conventional cell site device. The cell site device10includes a global positioning system (hereinafter, GPS) receiver102, a GPS antenna102a, processing circuits101,103, and a network interface circuit104. The network interface circuit104includes a media access control (hereinafter, MAC) and port physical layer (hereinafter, PHY) integrating a timestamp unit (hereinafter, TSU).

The cell site device10is in communication with a GPS satellite11, and the cell site device10is in communication with or electrically connected to a mobile network15. The GPS receiver102is electrically connected to the GPS antenna102aand the processing circuit101. The processing circuit103is electrically connected to the processing circuit101and the network interface circuit104.

The GPS antenna102areceives GPS signal GPS_SIG from a GPS satellite11. Then, the GPS receiver102generates a processing-circuit clock CLK1according to the synchronization-related information embedded in the GPS signal GPS_SIG. Based on the processing-circuit clock CLK1, the processing circuit101performs operations related to the CU component and DU component.

After receiving network signal netSIG from the mobile network15, the network interface circuit104generates another processing-circuit clock CLK2, according to the synchronization-related information acquired from the network signal netSIG. Based on the processing-circuit clock CLK2, the processing circuit103performs the RU component-related operations and transmits radio frequency (RF) signals to user equipment (hereinafter, UE)17. The cell site device10is in communication with one or more user equipment17.

As illustrated above, the processing circuits101,103respectively receive synchronization-related information from the GPS satellite11and the mobile network15. After the processing circuits101,103respectively operate based on the processing-circuit clocks CLK1, CLK2, the processing circuits101,103need to exchange synchronization-related information to ensure the CU/DU/RU components can communicate with each other smoothly.

In the case that the cell site device10is placed indoors or outdoors but the GPS signal GPS_SIG is blocked by tall buildings, the GPS signal GPS_SIG is weak, and the GPS antenna102cannot receive the GPS signal GPS_SIG correctly. This implies that the processing circuit101is incapable of receiving the processing-circuit clock CLK1, and the processing circuits101,103cannot exchange the synchronization-related information.

To be more specific, synchronization accuracy is crucial for communications between the cell site device10and the UEs. However, the conventional cell site device10cannot provide a stable synchronization relationship between the processing-circuit clocks CLK1, CLK2. Once the processing-circuit clocks CLK1, CLK2cannot be synchronized, the synchronization issues between the cell site device10and the UEs occur.

SUMMARY

The disclosure is directed to a cell site device and an associated clock synchronization method.

According to one embodiment, a cell site device in a radio access network is provided. The cell site device includes a clock synchronizer, a first processing circuit, and a second processing circuit. The clock synchronizer generates a first operation clock and a second operation clock. The first processing circuit is electrically connected to the clock synchronizer. The first processing circuit receives the first operation clock, generates a synchronizer setting signal, transmits the synchronizer setting signal to the clock synchronizer, and generates a cross-unit periodic synchronization signal. The second processing circuit is electrically connected to the clock synchronizer and the first processing circuit. The second processing circuit receives the second operation clock from the clock synchronizer, and receives the cross-unit periodic synchronization signal from the first processing circuit.

According to another embodiment, a clock synchronization method applied to a cell site device in a radio access network is provided. The cell site device includes a clock synchronizer, a first processing circuit, and a second processing circuit. The clock synchronization method includes the following steps. The clock synchronizer generates a first operation clock and a second operation clock. The clock synchronizer transmits the first operation clock to the first processing circuit and transmits the second operation clock to the second processing circuit. The first processing circuit generates a synchronizer setting signal according to one of an external clock synchronization source and the first operation clock. The first processing circuit generates a cross-unit periodic synchronization signal. The first processing circuit transmits the cross-unit periodic synchronization signal to the second processing circuit.

DETAILED DESCRIPTION

To avoid the situation that CU/DU/RU components cannot communicate with each other when any of the external synchronization sources malfunctions, the present disclosure provides an alternate approach to clock synchronization. The clock synchronization approach is implemented based on the combination of various external/internal clock synchronization sources.

The external clock synchronization source can be, for example, a global navigation satellite system (hereinafter, GNSS) and/or network. The network clock source can be, for example, a precision time protocol (hereinafter, PTP) clock source, synchronous Ethernet (hereinafter, syncE) clock source, and so forth. The internal clock synchronization source can be, for example, an oscillator.

FIG.2is a block diagram schematically illustrating the cell site device according to an embodiment of the present disclosure. The internal components of the cell site device30and their connections are first introduced.

The cell site device30includes a first processing circuit301, a second processing circuit303, an oscillator305, and a clock synchronizer307. The first processing circuit301and the second processing circuit303can be implemented with software, hardware, or a combination of software and hardware.

The first processing circuit301further includes a central processing unit (hereinafter, CPU)3011, a global positioning system (hereinafter, GPS) receiver3013, a GPS antenna3017, and a network interface circuit3015. The CPU3011executes software programs, including a PTP driver3011e, a synchronization source selector3011c, CU and DU components3011a, and so forth. In practical applications, the PTP driver3011e, the synchronization source selector3011c, CU and DU components3011acan be implemented with software, hardware, or a combination of software and hardware.

The clock synchronizer307is electrically connected to the oscillator305, the first processing circuit301, and the second processing circuit303. The GPS receiver3013is electrically connected to the GPS antenna3017and the CPU3011. The network interface circuit3015is electrically connected to the CPU3011.

According to an embodiment of the present disclosure, the synchronization source selector3011ccan freely change the clock synchronization source of the cell site device30. The clock synchronization source can be the GNSS system, PTP, syncE, and/or the oscillator305.

The GNSS system can be, for example, a global positioning system (hereinafter, GPS), a Galileo system, or a BeiDou Navigation Satellite System. For illustration purposes, the GPS is selected as an exemplary GNSS system.

Basically, the clock synchronization source having better precision accuracy is preferable. As the precision accuracy of the GPS-based clock synchronization is better than the precision accuracy of the PTP-based clock synchronization, the precision accuracy of the PTP-based clock synchronization is better than the precision accuracy of the syncE-based clock synchronization, and the precision accuracy of the syncE-based clock synchronization is better than the precision accuracy of the oscillator-based clock synchronization, the synchronization source selector3011cwill choose the GPS-based clock synchronization first, then the PTP-based clock synchronization, then the syncE-based clock synchronization, and finally the oscillator-based clock synchronization.

FIG.3is a state diagram schematically illustrating how the cell site device, according to an embodiment of the present disclosure, operates. InFIG.3, the ellipses represent various initialization states (STG1, STG2-1, STG3-1) and clock synchronization states (STG2-2, STG3-2, STG4) of the cell site device30, and the dotted arrows (dotAR1a, dotAR1b, dotAR2-1, dotAR2-2a, dotAR2-2b, dotAR2-2c, dotAR3-1, dotAR3-2a, dotAR3-2b, dotAR3-2c, dotAR4a, dotAR4b, dotAR4c) represent transition directions between the states. Table 1 summarizes the initialization/clock synchronization states and steps shown inFIG.3.

In practical applications, even though the quality of the GPS signal GPS_SIG and the network condition in the environment may change, the synchronization source selector3011ccan always maintain the specific synchronous relationship between the first processing circuit301and the second processing circuit303based on the state diagram inFIG.3.

In the following, how the cell site device30creates and maintains the specific synchronous relationship is explained inFIGS.4-9. InFIGS.4-9, bold arrows are labeled with symbols and numbers to represent the signal creation sequence. Table 2 compares the specific synchronous relationship described inFIGS.4-9.

FIG.4is a schematic diagram illustrating that an oscillator is utilized as the clock synchronization source during the system initialization state. Firstly, the oscillator305generates and provides an internal clock signal intCLK to the clock synchronizer307(bold arrow A1). Then, according to the internal clock signal intCLK, the clock synchronizer307generates the first operation clock opCLK1(for example, 125 MHZ) and the second operation clock opCLK2(for example, 122.88 MHz). The frequency of the first operation clock opCLK1is higher than the frequency of the second operation clock opCLK2, and the frequency of the second operation clock opCLK2is higher than the frequency of the internal clock signal intCLK.

The clock synchronizer307transmits the first operation clock opCLK1to the synchronization source selector3011c(bold arrow A2-1) and transmits the second operation clock opCLK2to the second processing circuit303(bold arrow A2-2). As both the first operation clock opCLK1and the second operation clock opCLK2are generated by the clock synchronizer307, the first operation clock opCLK1and the second operation clock opCLK2belong to the same clock domain.

For the sake of illustration, the clocks being derived from an identical clock source are defined as having a specific synchronous relationship in the specification, regardless of their actual frequencies. For example, the first operation clock opCLK1and the second operation clock opCLK2are considered as having a specific synchronous relationship because they are derived from the same clock source, that is, the internal clock signal intCLK.

After receiving the first operation clock opCLK1, the synchronization source selector3011cselects the first operation clock opCLK1to be the processing-circuit clock CLK1and transmits the processing-circuit clock CLK1to the CU and DU components3011a(bold arrow A3). Then, the first processing circuit301transmits a synchronizer setting signal clkSync_SetSIG to the clock synchronizer307via a serial peripheral interface (hereinafter, SPI).

Via the synchronizer setting signal clkSync_SetSIG, the CPU3011can calibrate the clock-related settings of the clock synchronizer307. Meanwhile, the clock synchronizer307can also use the synchronizer setting signal clkSync_SetSIG to report its clock-related settings and/or clock status information to the first processing circuit301(bold arrow A4).

After the CPU3011and the clock synchronizer307exchange the clock-related settings via the synchronizer setting signal clkSync_SetSIG, the clock synchronizer307respectively transmits the first operation clock opCLK1and the second operation clock opCLK2, as having the specific synchronous relationship, to the synchronization source selector3011cand the second processing circuit303(bold arrows A5-1, A5-2).

To ensure traffic between the DU component and the RU component is always synchronized, the synchronization source selector3011ctransmits the cross-unit periodic synchronization signal CPU1_1ppsto the RU component (bold arrow A6). The cross-unit periodic synchronization signal CPU1_1ppsis a hardware-based (physical) signal generated once per second, and the cross-unit periodic synchronization signal CPU1_1ppsis synchronized with the first operation clock opCLK1and the second operation clock opCLK2.

According to an embodiment of the present disclosure, the CU and DU components3011aare performed by the first processing circuit301, and the first processing circuit301operates based on the processing-circuit clock CLK1. On the other hand, the RU component is performed by the second processing circuit303, and the second processing circuit303operates based on the operation clock opCLK2.

As the processing-circuit clock CLK1and the operation clock opCLK2both originate from the clock synchronizer307, the specific synchronous relationship between the processing-circuit clock CLK1and the operation clock opCLK2is ensured. Accordingly, the CU and DU components3011acan freely exchange synchronization-related information syncINFO with the RU component (bold arrow A7).

FIG.4represents the initialization procedure of the cell site device30. After the initialization procedure, the specific synchronous relationship between the first processing circuit301and the second processing circuit303is built based on oscillator305. According to an embodiment of the present disclosure, the oscillator305is always ON as long as the cell site device30is in operation. In other words, the oscillator305continuously generates the internal clock signal intCLK, regardless of whether the oscillator305is selected as the clock synchronization source or not.

FIG.5is a schematic diagram illustrating that the device positioning information posGPS can be acquired from the GPS signal GPS_SIG so that the synchronization source selector knows that the GPS-based periodic synchronization signal GPS_1ppscan be utilized for clock synchronization. The cell site device30utilizes the GPS antenna3017to receive the GPS signal GPS_SIG from a GPS satellite. After receiving the GPS signal GPS_SIG, the GPS antenna3017generates and conducts a GPS interface signal to the GPS receiver3013. Through the GPS signal GPS_SIG, the GPS satellite provides a GPS master clock and device positioning information posGPS to the cell site device30.

If the GPS receiver3013can successfully receive device positioning information posGPS, the GPS receiver3013transmits the device positioning information posGPS to the first processing circuit301via a universal asynchronous receiver/transmitter (UART) interface. Details about using the device positioning information posGPS are omitted.

Once the CPU3011receives the device positioning information posGPS from the GPS receiver3013, the CPU3011knows that the GPS-based periodic synchronization signal GPS_1ppsis available. The GPS-based periodic synchronization signal GPS_1ppsis a hardware-based (physical) signal generated once per second. Then, the GPS receiver3013periodically generates the GPS-based periodic synchronization signal GPS_1ppsaccording to the GPS signal GPS_SIG (bold arrow B1).

According to the GPS-based periodic synchronization signal GPS_1pps, the synchronization source selector3011cperiodically issues a coarse cross-unit periodic synchronization signal crs_CPU1_1ppsto the second processing circuit303(bold arrow B2). The coarse cross-unit periodic synchronization signal crs_CPU1_1ppsis a hardware-based signal generated once per second, and the coarse cross-unit periodic synchronization signal crs_CPU1_1ppsis synchronized with the GPS-based periodic synchronization signal GPS_1pps. Based on the GPS-based periodic synchronization signal GPS_1pps, the synchronization source selector3011cgenerates and provides the processing-circuit clock CLK1to the CU and DU components3011a(bold arrow B3).

Then, via the synchronizer setting signal clkSync_SetSIG, the CPU3011can fine-tune the clock-related settings of the clock synchronizer307. Meanwhile, the clock synchronizer307can report its clock-related settings and/or clock status information to the first processing circuit301(bold arrow B4). By communicating with the clock synchronizer307via the synchronizer setting signal clkSync_SetSIG, the first processing circuit301calibrates the cross-unit periodic synchronization signal cal_CPU1_1ppsto synchronize the cross-unit periodic synchronization signal cal_CPU1_1ppsand the first operation clock opCLK1.

After the CPU3011and the clock synchronizer307exchange the clock-related settings via the synchronizer setting signal clkSync_SetSIG, the clock synchronizer307respectively transmits the first operation clock opCLK1and the second operation clock opCLK2to the synchronization source selector3011cand the second processing circuit303(bold arrows B5-1, B5-2).

To ensure traffic between the DU component and the RU component is always synchronized, the synchronization source selector3011ctransmits a calibrated cross-unit periodic synchronization signal cal_CPU1_1ppsto the RU component303a(bold arrow B6). The calibrated cross-unit periodic synchronization signal cal_CPU1_1ppsis a hardware-based signal generated once per second, and the calibrated cross-unit periodic synchronization signal cal_CPU1_1ppsis synchronized with the first operation clock opCLK1and the second operation clock opCLK2.

According to an embodiment of the present disclosure, the CU and DU components3011aare performed by the first processing circuit301, and the first processing circuit301operates based on the processing-circuit clock CLK1. On the other hand, the RU component is performed by the second processing circuit303, and the second processing circuit303operates based on the second operation clock opCLK2.

As the processing-circuit clock CLK1and the second operation clock opCLK2both originate from the clock synchronizer307, and the cross-unit periodic synchronization signal cal_CPU1_1ppshas been calibrated, the specific synchronous relationship between the processing-circuit clock CLK1and the second operation clock opCLK2is ensured. Accordingly, the CU and DU components3011acan freely exchange synchronization-related information syncINFO with the RU component (bold arrow B7).

Please refer to step2-1inFIG.3andFIG.5together. After the initialization procedure of the GPS-based clock synchronization inFIG.5is complete, the cell site device30continues to perform the GPS-based clock synchronization inFIG.7.

Please note that the oscillator305continues to provide the internal clock signal intCLK to the clock synchronizer307inFIG.5, even though the clock synchronizer307does not further utilize the internal clock signal intCLK for generating the first operation clock opCLK1and the second operation clock opCLK2. Alternatively, the continuous generation of the internal clock signal intCLK can be considered as an operation performed in the background.

The cell site device30may be placed in an indoor or outdoor environment. In either environment, the GPS signal GPS_SIG may be weak, so the GPS receiver3013is incapable of generating the device positioning information posGPS. Then, an alternate choice is adopted by using the network signal netSIG (for example, Ethernet signal) as another media that carries synchronization-related information. The synchronization-related information carried by the network signal netSIG can be packet-based (for example, PTP) or physical-layer-based (for example, syncE).

The network interface circuit3015is utilized to assist the synchronization source selector3011cin acquiring the synchronization-related information carried by the network signal netSIG. Details regarding how the network interface circuit3015assists the synchronization source selector3011cto acquire the synchronization-related information are omitted in the present disclosure.

FIG.6Ais a schematic diagram illustrating that the PTP timestamps PTP_tstmp can be acquired from the network signal netSIG, and the synchronization source selector determines to use the PTP-based clock synchronization. The cell site device30utilizes the network interface circuit3015to receive the network signal netSIG (bold arrow C1). Then, the network interface circuit3015acquires PTP packets PTP_PKT from the network signal netSIG (bold arrow C2).

According to the PTP packets PTP_PKT, the PTP driver3011egenerates PTP timestamps PTP_tstmp. The PTP driver3011etransmits the PTP timestamps PTP_tstmp to the synchronization source selector3011c(bold arrow C3). According to the PTP timestamps PTP_tstmp, the synchronization source selector3011cissues the processing-circuit clock CLK1to the CU and DU components3011a(bold arrow B3(blocked arrow C4-1) and issues a coarse cross-unit periodic synchronization signal crs_CPU1_1ppsto the second processing circuit303(bold arrow C4-2).

Then, via the synchronizer setting signal clkSync_SetSIG, the CPU3011can fine-tune the timing/frequency/phase of the first operation clock opCLK1and the second operation clock opCLK2, by adjusting the clock-related settings of the clock synchronizer307. Meanwhile, the clock synchronizer307can report its clock-related settings and/or clock status information to the first processing circuit301(bold arrow C5).

After the CPU3011and the clock synchronizer307exchange the clock-related settings via the synchronizer setting signal clkSync_SetSIG, the clock synchronizer307respectively transmits the first operation clock opCLK1and the second operation clock opCLK2to the synchronization source selector3011cand the second processing circuit303(bold arrows C6-1, C6-2).

To ensure traffic between the DU component and the RU component is always synchronized, the synchronization source selector3011ctransmits a calibrated cross-unit periodic synchronization signal cal_CPU1_1ppsto the RU component303a(bold arrow C7). The calibrated cross-unit periodic synchronization signal cal_CPU1_1ppsis a hardware-based signal generated once per second, and the calibrated cross-unit periodic synchronization signal cal_CPU1_1ppsis synchronized with the first operation clock opCLK1and the second operation clock opCLK2.

According to an embodiment of the present disclosure, the CU and DU components3011aare performed by the first processing circuit301, and the first processing circuit301operates based on the processing-circuit clock CLK1. On the other hand, the RU component is performed by the second processing circuit303, and the second processing circuit303operates based on the second operation clock opCLK2.

As the processing-circuit clock CLK1and the second operation clock opCLK2both originate from the clock synchronizer307, the specific synchronous relationship between the processing-circuit clock CLK1and the second operation clock opCLK2is ensured. Accordingly, the CU and DU components3011acan freely exchange synchronization-related information syncINFO with the RU component (bold arrow C8).

Please refer to step3-1inFIG.3andFIG.6Atogether. After the initialization procedure of the PTP-based clock synchronization inFIG.6Ais complete, the cell site device30continues to perform the PTP-based clock synchronization inFIG.8A.

Please note that the oscillator305continues to provide the internal clock signal intCLK to the clock synchronizer307inFIG.6A, even though the clock synchronizer307does not further utilize the internal clock signal intCLK for generating the first operation clock opCLK1and the second operation clock opCLK2. Alternatively, the existence and continuous generation of the internal clock signal intCLK can be considered as an operation performed in the background.

FIG.6Bis a schematic diagram illustrating that the syncE clock signal syncE_CLK can be acquired from the network signal netSIG and the synchronization source selector determines to use the syncE-based clock synchronization. The cell site device30utilizes the network interface circuit3015to receive the network signal netSIG (bold arrow C1′). Then, the network interface circuit3015acquires the syncE clock signal syncE_CLK from the network signal netSIG (bold arrow C2′).

According to the syncE clock signal syncE_CLK, the synchronization source selector3011cissues the processing-circuit clock CLK1to the CU and DU components3011a(bold arrow B3(blocked arrow C4-1′) and issues a coarse cross-unit periodic synchronization signal crs_CPU1_1ppsto the second processing circuit303(bold arrow C4-2′).

Then, via the synchronizer setting signal clkSync_SetSIG, the CPU3011can fine-tune the clock-related settings of the clock synchronizer307. Meanwhile, the clock synchronizer307can report its clock-related settings and/or clock status information to the first processing circuit301(bold arrow C5′).

After the CPU3011and the clock synchronizer307exchange the clock-related settings via the synchronizer setting signal clkSync_SetSIG, the clock synchronizer307respectively transmits the first operation clock opCLK1and the second operation clock opCLK2to the synchronization source selector3011cand the second processing circuit303(bold arrows C6-1, C6-2).

To ensure traffic between the DU component and the RU component is always synchronized, the synchronization source selector3011ctransmits a calibrated cross-unit periodic synchronization signal cal_CPU1_1ppsto the RU component303a(bold arrow C7′). The calibrated cross-unit periodic synchronization signal cal_CPU1_1ppsis a hardware-based signal generated once per second, and the calibrated cross-unit periodic synchronization signal cal_CPU1_1ppsis synchronized with the first operation clock opCLK1and the second operation clock opCLK2.

According to an embodiment of the present disclosure, the CU and DU components3011aare performed by the first processing circuit301, and the first processing circuit301operates based on the processing-circuit clock CLK1. On the other hand, the RU component is performed by the second processing circuit303, and the second processing circuit303operates based on the second operation clock opCLK2.

As the processing-circuit clock CLK1and the second operation clock opCLK2both originate from the clock synchronizer307, the specific synchronous relationship between the processing-circuit clock CLK1and the second operation clock opCLK2is ensured. Accordingly, the CU and DU components3011acan freely exchange synchronization-related information syncINFO with the RU component (bold arrow C8′).

Please refer to step3-1inFIG.3andFIG.6Btogether. After the initialization procedure of the syncE-based clock synchronization inFIG.6Bis complete, and the cell site device30continues to perform the syncE-based clock synchronization inFIG.8B.

Please note that the oscillator305continues to provide the internal clock signal intCLK to the clock synchronizer307inFIG.6B, even though the clock synchronizer307does not further utilize the internal clock signal intCLK for generating the first operation clock opCLK1and the second operation clock opCLK2. Alternatively, the generation of the internal clock signal intCLK can be considered as an operation performed in the background.

According to an embodiment of the present disclosure, the cell site device30supports internal and external clock synchronization sources. The initialization procedures corresponding to these clock synchronization sources have been described inFIGS.4,5,6A, and6B. These various clock synchronization sources and their related signals are summarized in Table 3.

In the following, the stable synchronization states corresponding to these clock synchronization sources will be illustrated inFIGS.7,8A,8B, and8C.

FIG.7is a schematic diagram illustrating that the cell site device is in the stable clock synchronization state using GPS-based clock synchronization. Please refer toFIGS.5and7together. The signals related to the GPS-based clock synchronization, including the device positioning information posGPS, the GPS-based periodic synchronization signal GPS_1pps, the processing-circuit clock CLK1, the cross-unit periodic synchronization signal CPU1_1pps, the first operation clock opCLK1, the second operation clock opCLK2, the synchronizer setting signal clkSync_SetSIG, and the synchronization-related information syncINFO, as explained inFIG.5, are redrawn inFIG.7. In short, the signals related to the GPS-based clock synchronization jointly become a stable circulation as long as the cell site device30continuously uses the GPS signal GPS_SIG as the clock synchronization source.

FIG.8Ais a schematic diagram illustrating that the cell site device is in the stable clock synchronization state using the PTP-based clock synchronization. Please refer toFIGS.6A and8Atogether. The signals related to the PTP-based clock synchronization, including the network signal netSIG, the PTP packets PTP_PKT, the PTP timestamps PTP_tstmp, the processing-circuit clock CLK1, the cross-unit periodic synchronization signal CPU1_1pps, the first operation clock opCLK1, the second operation clock opCLK2, the synchronizer setting signal clkSync_SetSIG, and the synchronization-related information syncINFO, as explained inFIG.6A, are redrawn inFIG.8A. In short, the signals related to the PTP-based clock synchronization jointly become a stable circulation as long as the cell site device30continuously uses the PTP as the clock synchronization source.

FIG.8Bis a schematic diagram illustrating that the cell site device is in the stable clock synchronization state using the syncE-based clock synchronization. Please refer toFIGS.6B and8Btogether. The signals related to the syncE-based clock synchronization, including the network signal netSIG, the syncE clock signal syncE_CLK, the processing-circuit clock CLK1, the cross-unit periodic synchronization signal CPU1_1pps, the first operation clock opCLK1, the second operation clock opCLK2, the synchronizer setting signal clkSync_SetSIG, and the synchronization-related information syncINFO, as explained inFIG.6B, are redrawn inFIG.8B. In short, the signals related to the syncE-based clock synchronization jointly become a stable circulation as long as the cell site device30continuously uses the syncE as the clock synchronization source.

As mentioned above, generation of the internal clock signal intCLK is still performed in the background inFIGS.7,8A, and8B. According to an embodiment of the present disclosure, even if the cell site device30suddenly encounters situations where GPS/network signals are unavailable/invalid, the synchronization relationship between the CU and DU components3011aand the RU component can be maintained because of the internal clock signal intCLK generated in the background.

With the internal clock signal intCLK generated in the background, the synchronization relationship between the CU and DU components3011aand the RU component is not interrupted when the cell site device30encounters unexpected changes, such as suddenly losing the GPS signal GPS_SIG and/or the network signal netSIG.

While waiting for qualities of the GPS signal GPS_SIG/network signal netSIG to recover, clocks of the CU and DU components3011aand the RU component can remain having the specific synchronous relationship as the oscillator305is always available as a backup clock synchronization source.

FIG.9is a schematic diagram illustrating that the cell site device is in the stable clock synchronization state using oscillator-based clock synchronization. InFIG.9, it is assumed that none of the GPS signal GPS_SIG and the network signal netSIG is available, so the synchronization source selector3011cchooses the oscillator305as the clock synchronization source.

Please refer toFIGS.4and9together. The signals related to the oscillator-based clock synchronization, as explained inFIG.4, are redrawn inFIG.9. In short, the signals related to the oscillator-based clock synchronization, including the processing-circuit clock CLK1, the cross-unit periodic synchronization signal CPU1_1pps, the first operation clock opCLK1, the second operation clock opCLK2, the synchronizer setting signal clkSync_SetSIG, the synchronization-related information syncINFO, and the internal clock signal intCLK, jointly become a stable circulation. This stable circulation is always ready to be utilized when none of the external clock synchronization sources is available/valid.

As the oscillator305is an internal component of the cell site device30, the oscillator305can consistently provide the internal clock signal intCLK to the clock synchronizer307. Accordingly, the specific synchronous relationship between the first operation clock opCLK1and second operation clock opCLK2can be assured even when the synchronization source selector3011cchanges the clock synchronization source of the cell site device30or when the signal quality of the external clock synchronization source becomes worse.

As multiple clock synchronization sources are adopted, the synchronization relationship between the first processing circuit301and the second processing circuit303is maintained. The clock synchronization source being selected by the synchronization source selector is dynamically determined, depending on the availability of the clock synchronization sources. For example, the clock synchronization source can be GNSS-based, a packet-based clock synchronization such as PTP protocol, a physical-layer-based clock synchronization, an oscillator305, and so forth.

In Table 4, the duration required for being synchronized with the external clock synchronization source and the accuracy of precision in comparison with the external clock synchronization source are compared.

As summarized in Table 4, the precision of using GPS-based clock synchronization is the highest. Thus, the synchronization source selector3011cwould select the GPS-based clock synchronization whenever the GPS signal GPS_SIG is available. However, the duration required for GPS-based clock synchronization is also the slowest, so the synchronization source selector3011cneeds to be able to change to other clock sources if the GPS signal GPS_SIG becomes weak or interrupted. Based on a similar selection strategy, the synchronization source selector3011ccan dynamically select and change the clock synchronization source of the cell site device30based onFIGS.10A and10B.

FIGS.10A and10Bare flow diagrams schematically illustrating how the cell site device, according to an embodiment of the present disclosure, switches the clock synchronization source. Please refer toFIGS.4-10together.

Firstly, the system initialization of the cell site device30is performed (step S901). Details about step S901can be referred toFIG.4. After step S901is complete, the internal clock signal intCLK is continuously generated in the background. Then, the synchronization source selector3011cchecks if the device positioning information posGPS is available (step S903).

If the determination result of step S903is positive, the initialization procedure of GPS-based clock synchronization is performed (step S905). Details about step S905can be referred toFIG.5.

After step S905, the synchronization source selector3011cagain checks if the device positioning information posGPS is still available (step S907). If the determination result of step S907is positive, the cell site device30continues to utilize the GPS-based periodic synchronization signal GPS_1ppsto perform the GPS-based clock synchronization (step S909). Details about step S909can be referred toFIG.7. Steps S907and S909are repetitively performed until the determination result of step S907is negative.

In a poor GPS environment, the GPS receiver3013cannot receive the GPS signal GPS_SIG through the GPS antenna, and the GPS-based periodic synchronization signal GPS_1ppsis unavailable/invalid. This is the situation when the determination result of step S903is negative or when the determination result of step S907is negative.

Under such circumstances, the synchronization source selector3011cneeds to check if the PTP timestamps PTP_tstmp are available (step S911). If the determination result of step S911is positive, the initialization procedure of PTP-based clock synchronization is performed (step S913). Details about step S913can be referred toFIG.6A.

After step S913, the synchronization source selector3011cagain checks if the PTP timestamps PTP_tstmp remain available (step S915). If the determination result of step S915is positive, the cell site device30continues to perform the PTP-based clock synchronization (step S917). Details about step S917can be referred toFIG.8A.

After step S917, the synchronization source selector3011cchecks if the device positioning information posGPS becomes available (step S919). If the determination result of step S919is negative, the device positioning information posGPS is still not available, and step S915is repetitively performed to check if the PTP timestamps PTP_tstmp can still be acquired from the network signal netSIG.

On the other hand, if the determination result of step S919is positive, the synchronization source selector3011cuses the GPS-based clock synchronization to replace the PTP-based clock synchronization, as the precision accuracy of the GPS-based clock synchronization is better. Thus, step S905is performed. As the initialization procedure of GPS-based clock synchronization takes time (a few minutes to a few hours), the synchronization source selector3011ccan continue utilizing a PTP-based clock synchronization during the initialization procedure of GPS-based clock synchronization.

When both GPS-based periodic synchronization signal GPS_1ppsand PTP timestamps PTP_tstmp are unavailable, the synchronization source selector3011cchecks if the syncE clock signal syncE_CLK is available in the network signal netSIG (step S921). If the determination result of step S921is positive, the initialization procedure of syncE-based clock synchronization is performed (step S923). Details about step S923can be referred toFIG.6B.

After step S923, the synchronization source selector3011cagain checks if the syncE clock signal syncE_CLK is still available (step S925). If the determination result of step S925is positive, the cell site device30continues to perform the syncE-based clock synchronization (step S927). Details about step S927can be referred toFIG.8B.

After step S927, the synchronization source selector3011cchecks if the device positioning information posGPS becomes available (step S929). If the determination result of step S929is positive, the synchronization source selector3011cuses the GPS-based clock synchronization to replace the syncE-based clock synchronization and step S905is performed. As the initialization procedure of GPS-based clock synchronization (step S905) takes a while, the synchronization source selector3011ccan continue to utilize a PTP-based clock synchronization during the clock source transition procedure.

If the determination result of step S929is negative, the synchronization source selector3011cfurther checks if the PTP timestamps PTP_tstmp become available (step S931). If the determination result of step S931is positive, the synchronization source selector3011cuses the PTP-based clock synchronization to replace the syncE-based clock synchronization and step S913is performed.

As the initialization procedure of PTP-based clock synchronization (step S913) takes a while, the synchronization source selector3011ccan continue to utilize a syncE-based clock synchronization during the transition procedure of the clock synchronization source. If the determination result of step S931is negative, step S925is repetitively performed.

When none of the GPS-based periodic synchronization signal GPS_1pps, the PTP timestamps PTP_tstmp, and the syncE clock signal syncE_CLK is available, the synchronization source selector3011cperforms the oscillator-based clock synchronization (step S933). Details about step S933can be referred toFIG.9.

After step S933, the synchronization source selector3011cchecks if the cell site device30is still in operation (step S935). If the determination result of S935is positive, step S903is repetitively executed. Otherwise, the flow ends.

FIG.11is a flow diagram schematically illustrating the clock synchronization method applied to the cell site device according to an embodiment of the present disclosure. Firstly, the clock synchronizer307generates a first operation clock opCLK1and a second operation clock opCLK2(step S111). Then, the clock synchronizer307transmits the first operation clock opCLK1to the first processing circuit301and transmits the second operation clock opCLK2to the second processing circuit303(step S112).

The first processing circuit301generates the synchronizer setting signal clkSync_SetSIG according to one of the external clock synchronization sources (GPS, PTP, or syncE) and the first operation clock opCLK1(step S113). Furthermore, the first processing circuit301generates a cross-unit periodic synchronization signal CPU1_1pps(step S114) and transmits the cross-unit periodic synchronization signal CPU1_1ppsto the second processing circuit303(step S115).

As illustrated above, a multiple clock synchronization approach is provided. The multiple clock synchronization approach provides multiple clock synchronization sources. Among these clock synchronization sources, the GPS-based periodic synchronization signal GPS_1ppsis the primary choice, the PTP timestamps PTP_tstmp are the secondary choice, the syncE clock signal syncE_CLK is an alternate choice, and the oscillator305is a backup choice. As the backup choice, the oscillator305is always available for maintaining synchronization between the CU and DU components3011aand the RU component. Thus, the connections and transmissions between the cell site device30and user equipment (UE) are not affected by the clock synchronization source switching.