Wafer level package, chip size package device and method of manufacturing wafer level package

A wafer level package has a first wafer having a plurality of chips mounted or formed thereon in a plane, and a second wafer that is opposed to the first wafer. The first wafer and the second wafer are joined while a seal frame that seals a periphery of each chip is interposed therebetween. A gap is formed between the seal frames of the chips adjacent to each other. A partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other.

BACKGROUND

1. Technical Field

The present invention relates to a wafer level package, a chip size package device, and a wafer level package manufacturing method, in which plural chips are mounted on or formed in a plane of a first wafer and a second wafer is joined to the first wafer to seal each chip using a seal frame. Particularly, the present invention relates to a wafer level package that can avoid generation of a crack in the seal frame during dicing and reduce generation of separation in the wafer even if the wafer is subjected to a high-temperature process after a wet process or liquid cleaning.

2. Related Art

Nowadays, downsizing, weight reduction, and high functionality make dramatic progress in electronic products typified by a mobile phone, a mobile computer, a personal digital assistance (PDA), and a digital still camera (DSC) and the like. With a market trend of the electronic products, there is also a strong demand for the downsizing, a low profile, the weight reduction, and high-density packaging into a mounting board for a semiconductor package mounted on the electronic product.

A new semiconductor package technology called a wafer level package in which processes are performed up to packaging in a wafer state receives attention against this background. In the wafer level package, re-wiring, electrode formation, resin sealing, and dicing are thoroughly performed in the wafer process, a size of the semiconductor chip into which the wafer is finally cut directly becomes a size of the package. Therefore, the wafer level package is ideal technology from the viewpoints of the downsizing and the weight reduction, and is already used in the mobile phone and the like.

Specifically, Patent Documents 1 to 3 disclose conventional technologies for the wafer level package.

In a wafer level package100disclosed in Patent Document 1, as illustrated inFIG. 9, a cover wafer102including an external electric terminal101is disposed on a substrate wafer104on which plural semiconductor chips103are mounted, each semiconductor chip103is sealed with a seal ring105that is of a seal frame by joining the cover wafer102to the substrate wafer104, and an electric contact between the external electric terminal101of the cover wafer102and the semiconductor chips103mounted on the substrate wafer104is established by a conductive route106.

In the wafer level package100, all peripheries of the semiconductor chips103, . . . are formed by the seal ring105as illustrated inFIGS. 10(a) and10(b), and the seal ring105is diced on dicing lines107to segmentalize the wafer level package100into individual packages as illustrated inFIGS. 11(a) and11(b).

In a wafer level package200disclosed in Patent Document 2, a cap wafer201made of silicon (Si) and a base wafer203which a device202is mounted on or formed in are joined as illustrated inFIGS. 12(a) and12(b). In the joined portion, a gasket204that is of the seal ring formed by partially removing the cap wafer201and the base wafer203are bonded by a joining material205, and a spatial portion in the gasket204is sealed by a resin206.

In the wafer level package200, a gap207exists between the gaskets204and204in the peripheries of the devices202adjacent to each other as illustrated inFIGS. 13(a) and13(b), and the wafer level package200is diced in the gap207and segmentalized into the individual packages as illustrated inFIGS. 14(a) and14(b).

The wafer level package disclosed in Patent Document 3 has the configuration similar to that of the wafer level package200disclosed in Patent Document 2.Patent Document 1: Japanese Unexamined Patent Publication No. 6-318625 (Published on Nov. 15, 1994)Patent Document 2: Japanese Unexamined Patent Publication No. 2003-204005 (Published on Jul. 18, 2003)Patent Document 3: U.S. Patent Application No. 2009/0194861 (Published on Aug. 6, 2009)

SUMMARY

However, in the conventional wafer level package100described in Patent Document 1, because the dicing line107exists in the seal ring105, unfortunately a crack generated during the dicing remains in the seal ring105, and becomes a degradation factor in a reliability test.

In the conventional wafer level package200described in Patent Document 2, the gap207exists between the gaskets204and204adjacent to each other. Because the liquid invades in the gap207in a wet process or dipping cleaning in a liquid, unfortunately the liquid such as water is vaporized at once to separate the cap wafer201from the base wafer203which the device202is mounted on or formed in when the wafer level package200is subjected to a high-temperature process after the wet process or the liquid cleaning. Accordingly, it may be necessary to bake the wafer level package200for a long time at 100° C., which results in lengthened working hours. The same holds true for the wafer level package described in Patent Document 3.

One or more embodiments of the present invention provides a wafer level package, a chip size package device, and a wafer level package manufacturing method, for being able to avoid the generation of the crack in the seal frame during the dicing and reduce the generation of the separation even if the wafer level package is subjected to the high-temperature process after the wet process or the liquid cleaning.

In accordance with one or more embodiments of the present invention, a wafer level package includes: a first wafer of which plural chips are mounted or formed in a plane; and a second wafer that is opposed to the first wafer, wherein the first wafer and the second wafer are joined while a frame-like seal frame that seals a periphery of each chip is interposed therebetween, a gap is formed between the seal frames of the chips adjacent to each other, and a partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other.

In accordance with one or more embodiments of the present invention, a chip size package device into which a wafer level package is individualized, a first wafer of which plural chips are mounted or formed in a plane and a second wafer opposed to the first wafer being joined while a frame-like seal frame that seals a periphery of each chip is interposed between the first wafer and the second wafer, wherein a gap is formed between the seal frames of the chips adjacent to each other, a partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other, and the chip is individualized by dicing the gap and the partial connect part, after the first wafer and second wafer are joined while the frame-like seal frame that seals a periphery of each chip is interposed therebetween.

In accordance with one or more embodiments of the present invention, a wafer level package manufacturing method for individualizing the wafer level package in which a first wafer of which plural chips are mounted or formed in a plane and a second wafer opposed to the first wafer being joined while a frame-like seal frame that seals a periphery of each chip is interposed between the first wafer and the second wafer, the wafer level package manufacturing method includes: a seal frame forming step of forming a gap between the seal frames of the chips adjacent to each other, and of forming the seal frame such that a partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other, and a dicing step of individualizing the chips by dicing the gap and the partial connect part, after the first wafer and second wafer are joined while the frame-like seal frame that seals a periphery of each chip is interposed therebetween.

According to one or more embodiments of the present invention, the gap is formed between the seal frames of the chips adjacent to each other. Therefore, the gap formed between the seal frames of the chips adjacent to each other can be diced when the wafer level package is individualized through the dicing process. As a result, the crack is not left in the seal frame because the seal frame is not directly diced.

The gap formed between the seal frames of the chips adjacent to each other is closed by the partial connect part. Therefore, the liquid such as water does not invade from the outside even in the state in which the first wafer and the second wafer are joined with the seal frame interposed therebetween. As a result, in the state in which the first wafer and the second wafer are joined with the seal frame interposed therebetween, the joined wafer separation caused by the vaporization of the liquid at once is not generated even if the wafer level package is subjected to the high-temperature process after the wet process or the liquid cleaning is performed.

Accordingly, one or more embodiments of the present invention can provide the wafer level package, the chip size package device, and the wafer level package manufacturing method, for being able to avoid the generation of the crack in the seal frame during the dicing and reduce the generation of the separation even if the wafer level package is subjected to the high-temperature process after the wet process or the liquid cleaning.

In the wafer level package according to one or more embodiments of the present invention, as described above, the gap is formed between the seal frames of the chips adjacent to each other, and the partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other.

In the chip size package device according to one or more embodiments of the present invention, as described above, the gap is formed between the seal frames of the chips adjacent to each other, the partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other, and the wafer level package is individualized by dicing the gap and the partial connect part, after the first wafer and the second wafer are joined while the frame-like seal frame that seals a periphery of each chip is interposed therebetween.

As described above, the wafer level package manufacturing method according to one or more embodiments of the present invention includes the seal frame forming step of forming the gap between the seal frames of the chips adjacent to each other, and of forming the seal frame such that the partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other, and the dicing step of individualizing the chip by dicing the gap and the partial connect part, after the first wafer and second wafer are joined while the frame-like seal frame that seals a periphery of each chip is interposed therebetween.

Therefore, one or more embodiments of the present invention can advantageously provide the wafer level package, the chip size package device, and the wafer level package manufacturing method, for being able to avoid the generation of the crack in the seal frame during the dicing and reduce the generation of the separation even if the wafer level package is subjected to the high-temperature process after the wet process or the liquid cleaning.

DETAILED DESCRIPTION

Structures of an individual chip size package device10and a wafer level package20A, which are manufactured in one or more embodiments of the present invention, will be described with reference toFIGS. 1(a) to1(e).FIG. 1(a) is a plan view illustrating a configuration of a main part of the wafer level package20A,FIG. 1(b) is a perspective view illustrating the configuration of a main part of the wafer level package20A,FIG. 1(c) is a plan view illustrating the wafer level package20A immediately after dicing with a cover wafer omitted,FIG. 1(d) is a front view illustrating the wafer level package20A immediately after the dicing, andFIG. 1(e) is a perspective view illustrating a configuration of individualized chip size package device10. In the description, a joined wafer packaged at a wafer level in a pre-dicing state is referred to as a wafer level package. The wafer level package individualized by the dicing is referred to as a chip size package device.

As illustrated inFIGS. 1(c) to1(e), in each chip size package device10manufactured by a wafer level package manufacturing method of one or more embodiments of the present invention, a base2which a semiconductor chip1that is of the chip is mounted on or formed in and a cover3that covers the base2are joined by an bonding agent5while a frame-like seal frame4that seals a periphery of each semiconductor chip1is interposed therebetween.

In one or more embodiments of the present invention, the chip is not limited to the semiconductor chip1as long as the chip1is a device having a Micro Electro Mechanical System (MEMS) structure or a chip such as an electronic circuit.

As long as the semiconductor chip1is sealed, a gap between the semiconductor chip1and the seal frame4may completely be evacuated or filled with an inert gas or a material such as resin.

Any bonding agent may be used as long as the bonding agent5does no damage to the semiconductor chip1from the viewpoints of an allowable adhesion property, a sealing power, sealing performance, and an external environment. Accordingly, the bonding agent5may be either conductive or non-conductive. In one or more embodiments of the present invention, the bonding agent5is disposed or formed between the seal frame4and a cover wafer23. Alternatively, the seal frame4may be formed on the side of the cover wafer23while the bonding agent5is disposed or formed between the seal frame4and a base wafer22to join the seal frame4and the base wafer22. Alternatively, the bonding agents5may be disposed or formed both between the seal frame4and the base wafer22and between the seal frame4and the cover wafer23. The bonding agent5can be applied to not only the case that the seal frame4is provided as individual component but also the case that the seal frame4is formed by machining from the base wafer22or the cover wafer23. As to the method for disposing or forming the bonding agent5, the bonding agent5can be formed by applying a liquid such as resin, or by evaporating metal.

As illustrated inFIGS. 1(a) and1(b), the chip size package device10is manufactured in the form of the wafer level package20A. In the wafer level package20A, the base wafer22that is of the first wafer which the plural semiconductor chips1, . . . are mounted on or formed in plane and the cover wafer23that is of the second wafer opposed to the base wafer22are joined to each other while the seal frame4that seals the periphery of each semiconductor chip1is interposed between the base wafer22and the cover wafer23.

The plural semiconductor chips1are arrayed while mounted on or formed in the plane of the base wafer22. Specifically, the plural semiconductor chips1are provided into a square lattice shape.

At this point, the base wafer22and the cover wafer23are made of silicon. However, in one or more embodiments of the present invention, the base wafer22and the cover wafer23are not limited to the silicon. The base wafer22and the cover wafer23may be made of glass, ceramic, or other semiconductor materials.

For example, the seal frame4is formed by metal plating using a mold. However, the seal frame4is not limited to the metal plating. The seal frame4may be made of other materials such as resin. Alternatively, for example, as illustrated inFIG. 2, after a recess portion is formed by machining the surface of the base wafer22, the seal frame4may be formed by depositing metal deposition (such as mold plating) and the bonding agent5.

In one or more embodiments of the present invention, the seal frame4is a square frame. However, any shape may be used as the seal frame4as long as the shape can seal the periphery of the semiconductor chip1. For example, polygonal frames such as a triangle and a pentagon or frames such as a circle and an ellipse may be used.

In one or more embodiments of the present invention, as illustrated inFIG. 1(a), a gap24is formed between the seal frames4and4adjacent to each other. As a result, as illustrated inFIG. 1(c), generation of a crack can be prevented in the seal frame4during the dicing by performing the dicing with the substantial center of the gap24as a dicing line25.

In one or more embodiments of the present invention, a partial connect part26that partially connects the seal frames4and4is provided in the gap24formed between the seal frames4and4of the semiconductor chips1adjacent to each other. As a result, the gap24constitutes a closed space surrounded by the seal frames4and4and the partial connect part26.

Therefore, a liquid such as water does not invade from the outside even in the state in which the base wafer22and the cover wafer23are joined with the seal frame4interposed therebetween. As a result, in the state in which the base wafer22and the cover wafer23are joined with the seal frame4interposed therebetween, the separation of the joined base wafer22and cover wafer23, which is caused by the vaporization of the liquid at once, is not generated even if the wafer level package is subjected to the high-temperature process at 100° C. or more after the wet process or the liquid cleaning is performed.

Accordingly, the wafer level package20A, in which the generation of the crack in the seal frame4is avoided during the dicing and the generation of the separation is reduced even if the wafer level package is subjected to the high-temperature process after the wet process or the liquid cleaning, can be provided.

At this point, in the wafer level package20A according to one or more embodiments of the invention, as illustrated inFIG. 1(a), in the case that the plural semiconductor chips1are arrayed while mounted on or formed in the plane of the base wafer22, the partial connect part26is provided in a center portion on opposed sides of the seal frames4opposed to each other.

Generally, in the device in which different materials are stacked, a stress is generated by a difference in thermal expansion coefficient during a temperature change. The stress increases with distance from the center of the device. Therefore, in the case that the partial connect part26is located closest to the center of the device, namely, in the case that the plural semiconductor chips1is arrayed while mounted on or formed in the plane of the base wafer22, the partial connect part26is disposed in the center portion in each of an x-direction and a y-direction of the seal frame4, thereby obtaining the best environment resistance.

On this point, in one or more embodiments of the present invention, the partial connect part26is provided at the position where the thermal stress is minimized during the thermal expansion because the partial connect part26is provided in the center portion on the opposed sides of the seal frames4opposed to each other. Accordingly, a possibility that the partial connect part26is destroyed becomes the minimum during the thermal expansion.

In the case that the seal frames4are formed by the mold plating like one or more embodiments of the present invention, the partial connect part26is provided in the center portion on the opposed sides of the seal frames4opposed to each other, thereby equalizing an area ratio of each partial connect part26. This is because the formation of the partial connect part26in the center portion on the opposed sides of the seal frames4equalizes the plating deposition rate in the plane in the case that the seal frames4are formed by the mold plating. As a result, a variation in plating thickness decreases to be able to stabilize run-around of the sealing material between the joined surfaces.

At this point, in the wafer level package20A of one or more embodiments of the present invention, as illustrated inFIG. 3, a pattern width C that is of a width of the partial connect part26is equalized to a pattern width S that is of a width of the seal frame4.

That is, the joined surfaces of the base wafer22and the cover wafer23, particularly the joined surfaces of the seal frame4and the cover wafer23are bonded using the bonding agent5, the bonding agent5moves to the wider pattern width by an influence of a surface tension when spreading onto the joined surface while the pattern width C of the partial connect part26differs from the pattern width S of the seal frame4.

Specifically, as illustrated inFIG. 4(a), in the case that the pattern width C of the partial connect part26is less than the pattern width S of the seal frame4, the bonding agent5applied to the partial connect part26moves onto the side of the seal frame4to reduce a wet area of the bonding agent5in the partial connect part26. Therefore, there is a risk of easily destroying the sealing performance of the partial connect part26.

On the other hand, as illustrated inFIG. 4(b), in the case that the pattern width C of the partial connect part26is greater than the pattern width S of the seal frame4, the bonding agent5applied to the seal frame4moves onto the side of the partial connect part26to reduce the wet area of the bonding agent5in the seal frame4. As a result, there is a risk that the sealing performance of the seal frame4becomes insufficient.

When the pattern width C of the partial connect part26is equalized to the pattern width S of the seal frame4, base wafer22and the cover wafer23are joined while the bonding agent5spreads stably to both the partial connect part26and the seal frame4.

In the case that the seal frame4is formed by the mold plating, the pattern width C of the partial connect part26is equalized to the pattern width S of the seal frame4to equalize the plating deposition rate in the plane. As a result, the variation in plating thickness decreases to be able to stabilize the run-around of the sealing material between the joined surfaces, namely, the bonding agent5that performs the sealing by spreading between the seal frame4and the cover side bonded to the seal frame4.

In the wafer level package20A of one or more embodiments of the present invention, as illustrated inFIG. 5, the pattern width C of the partial connect part26is greater than or equal to 1 μm.

The one partial connect part26is provided in the side surface of each seal frame4, and the pattern width C of the partial connect part26is narrowed as much as possible within the range where the partial connect part26can stably be joined. Therefore, a length of the joined portion to be diced can be shortened. Therefore, the crack, which is generated in the joined portion during the dicing, can be reduced to the minimum to ensure high reliability.

From this viewpoint, according to one or more embodiments of the present invention, the minimum value of the pattern width C of the partial connect part26is greater than or equal to 1 μm in consideration of the partial connect part26that can be formed by etching and a restriction to alignment accuracy during the joining.

A method for manufacturing the wafer level package20A of one or more embodiments of the present invention will be described below.

As illustrated inFIGS. 1(a) and1(b), the plural semiconductor chips1are arrayed while mounted on or formed in the plane of the base wafer22. Then, in a seal frame forming process that is of the seal frame forming step, the frame-like seal frame4that seals the periphery of each semiconductor chip1is formed by the mold plating. At this point, the gap24is formed between the seal frames4of the semiconductor chips1. The seal frame4including the partial connect part26that partially connects the seal frames4and4is formed in the gap24. Then, as illustrated inFIGS. 1(b) and1(d), the bonding agent5is disposed or formed in the seal frame4, and the cover wafer23covers the seal frame4after the alignment. Then, as illustrated inFIGS. 1(c) and1(d), through the dicing process, the gap24between the seal frames4and4is diced on the dicing line25to individualize the wafer level package20A. Therefore, the chip size package device10individualized into each package is completed as illustrated inFIG. 1(e).

The wafer level package20A of one or more embodiments of the present invention includes the base wafer22of which the plural semiconductor chips1are mounted on or the formed in the plane and the cover wafer23opposed to the base wafer22, and the base wafer22and the cover wafer23are joined while the frame-like seal frame4that seals the periphery of each semiconductor chip1is interposed therebetween. The gap24is formed between the seal frames4of the semiconductor chips1adjacent to each other, and the partial connect part26that partially connects the seal frames4to each other is provided in the gap24formed between the seal frames4of the semiconductor chips1adjacent to each other.

Therefore, the gap24formed between the seal frames4and4of the semiconductor chips1adjacent to each other can be diced when the wafer level package is individualized through the dicing process. As a result, the crack is not left in the seal frame4because the seal frame4is not directly diced.

The gap24formed between the seal frames4of the semiconductor chips1adjacent to each other is closed by the partial connect part26. As a result, in the state in which the base wafer22and the cover wafer23are joined with the seal frame4interposed therebetween, the joined wafer separation caused by the vaporization of the liquid at once is not generated even if the wafer level package is subjected to the high-temperature process after the wet process or the liquid cleaning is performed.

Accordingly, the wafer level package20A, in which the generation of the crack in the seal frame4is avoided during the dicing and the generation of the separation is reduced even if the wafer level package is subjected to the high-temperature process after the wet process or the liquid cleaning, can be provided.

As to a spillover effect, the number of chip size package devices10per wafer increases compared with the case that the protect ring is formed in the outer circumference of the wafer. The wet process, the cleaning, and the high-temperature process can be performed even if the outer circumferential gap is not closed in the state in which the base wafer22and the cover wafer23are joined.

In the wafer level package20A of one or more embodiments of the present invention, the plural semiconductor chips1are arrayed while mounted on or formed in the plane of the base wafer22, and the partial connect part26is provided in the center portion on the opposed sides of the seal frames4opposed to each other.

Because the partial connect part26is provided in the place where the thermal stress is minimized during the thermal expansion, the risk of destroying the partial connect part26is minimized during the thermal expansion.

In one or more embodiments of the present invention, the partial connect part26is provided in the center portion on the opposed sides of the seal frames4opposed to each other, thereby locally equalizing the area ratio of the seal frame4in the plane of the wafer. Accordingly, as illustrated inFIGS. 6(a) and6(b), in the case that the seal frame4is patterned using a resist mold R and formed by electrolytic plating, the electric flux density is equalized during the electrolytic plating when the partial connect part26is formed in the center portion on the opposed sides of the seal frames4by the electrolytic plating. As a result, the deposition rate of the electrolytic plating is equalized in the plane of the wafer, and the variation in plating thickness decreases to be able to stabilize the run-around of the sealing material between the joined surfaces. Particularly, as illustrated inFIGS. 6(a) and6(b), in the electrolytic plating, a metallic ion in a plating solution is attracted to the surface of the base wafer22by an electric field, and deposited on the surface. An electric line of force E flows intensively in a place through which a current is passed (a place in which a seed metal SM is exposed while the resist mold R does not exist). As illustrated inFIGS. 6(c) and6(d), the electric flux density becomes dense in the portion in which the pattern is sparse and the electric flux density becomes sparse in the portion in which the pattern is dense. Therefore, amount of metal deposited per unit area or unit time (the plating deposition rate) varies when the sparse and dense difference exists in the patterns. As described above, in one or more embodiments of the present invention, the partial connect part26is provided in the center portion on the opposed sides of the seal frames4opposed to each other. Therefore, the area ratio of the seal frame4is locally equalized in the plane of the wafer, the deposition rate of the electrolytic plating is equalized in the plane of the wafer, the variation in plating thickness decreases, and the run-around of the sealing material between the joined surfaces can be stabilized.

In the wafer level package20A of one or more embodiments of the present invention, the pattern width C of the partial connect part26can be equalized to the pattern width S of the seal frame4. Therefore, the base wafer22and the cover wafer23can be joined while the bonding agent5spreads stably onto both the seal frame4and the partial connect part26.

In the case that the seal frame4is formed by the mold plating, the variation in plating thickness decreases to be able to stabilize the run-around of the sealing material between the joined surfaces.

In the wafer level package20A of one or more embodiments of the present invention, the pattern width C of the partial connect part26is greater than or equal to 1 μm. Therefore, the crack, which is generated in the joined portion during the dicing, can be reduced to the minimum to ensure the high reliability.

The chip size package device10of one or more embodiments of the present invention is formed by individualizing the wafer level package20A, in which the base wafer22of which the plural semiconductor chips1are mounted on or formed in the plane and the cover wafer23opposed to the base wafer22are joined while the frame-like seal frame4that seals the periphery of each semiconductor chip1is interposed therebetween. The gap24is formed between the seal frames4and4of the semiconductor chips1adjacent to each other, the partial connect part26that partially connects the seal frames4and4to each other is formed in the gap24formed between the seal frames4of the semiconductor chips1adjacent to each other, and the wafer level package20A is individualized by dicing the gap24and the partial connect part26after the base wafer22and the cover wafer23are joined while the frame-like seal frame4that seals the periphery of each semiconductor chip1is interposed therebetween.

The wafer level package20A, in which the base wafer22of which the plural semiconductor chips1are mounted on or formed in the plane and the cover wafer23opposed to the base wafer22are joined while the frame-like seal frame4that seals the periphery of each semiconductor chip1is interposed therebetween, is individualized in the method for manufacturing the wafer level package20A of one or more embodiments of the present invention. At this point, the method includes: the seal frame forming process of forming the gap24between the seal frames4of the semiconductor chips1adjacent to each other and of forming the seal frame4such that the partial connect part26that partially connects the seal frames4and4to each other is provided in the gap24formed between the seal frames4of the semiconductor chips1adjacent to each other; and the dicing process of individualizing the semiconductor chips1by dicing the gap and the partial connect part26after the base wafer22and the cover wafer23are joined while the frame-like seal frame4that seals the periphery of each semiconductor chip1is interposed therebetween.

Therefore, one or more embodiments of the present invention can provide the wafer level package20A, the chip size package device10, and the method for manufacturing the wafer level package20A, for being able to avoid the generation of the crack in the seal frame4during the dicing and reduce the generation of the separation even if the wafer level package is subjected to the high-temperature process after the wet process or the liquid cleaning.

One or more embodiments of the present invention will be described below with reference toFIGS. 7 and 8.

In the wafer level package20A of one or more embodiments of the present invention, as illustrated inFIG. 1(b), the partial connect part26is formed in the seal frame4in the periphery of each of all the semiconductor chips1. On the other hand, in a wafer level package20B of one or more embodiments of the present invention, as illustrated inFIGS. 7(a),7(b), and7(c), the partial connect part26is formed only in the seal frame4in an outer circumferential portion of the base wafer22.

This is, in the wafer level package20B of one or more embodiments of the present invention, as illustrated inFIGS. 7(a) and7(b), the partial connect part26is formed in the center of the seal frame4of the semiconductor chip1that is mounted on or formed in an outer circumferential portion OUTER of the base wafer22. On the other hand, as illustrated inFIGS. 7(a) and7(c), the partial connect part26is not formed in the seal frame4of the semiconductor chip1that is mounted on or formed in a central portion INNER of the base wafer22.

Specifically, according to one or more embodiments of the present invention the seal frame4of the semiconductor chip1in the outer circumferential portion OUTER of the base wafer22includes the seal frames4formed in the peripheries of at least the top third semiconductor chips1from the outermost circumferential semiconductor chip1of the base wafer22in both the x-direction and the y-direction.

When the partial connect parts26are formed only in the seal frames4in the outer circumferential portions OUTER of the base wafer22and the cover wafer23, the partial connect part26that traverses the dicing line does not exist in the seal frames4in the central portions INNER of the base wafer22and the cover wafer23. Accordingly, the generation of the crack can be reduced in the seal frame4.

In the above description, the partial connect part26formed in the gap24of the seal frame4exists only in the outer circumferential portion OUTER of the base wafer22.

Alternatively, for example, as illustrated inFIGS. 8(a) and8(b), the partial connect part26may be provided in the gap24only of the seal frame4of the semiconductor chip1that is mounted on or formed in the outermost circumference of the base wafer22in the semiconductor chips1, which are mounted on or formed in the plane of the base wafer22that is of the first wafer.

Therefore, the number of semiconductor chips1in which the dicing line25passes through the seal frame4can be minimized by minimizing the number of partial connect parts26, and the generation of the crack can further be reduced in the seal frame4.

It is conceivable that there is no meaning to form the partial connect part26of the seal frame4only in the outer circumferential portions OUTER of the base wafer22and the cover wafer23. However, in the case that the partial connect part26is provided only in the gap24in the seal frame4of the semiconductor chip1that is mounted on or formed in the outermost circumference of the base wafer22, there is the risk of destroying the sealing property due to the crack generated in the seal frame4during the dicing.

On the other hand, when the partial connect part26of the seal frame4is formed only in the outer circumferential portions OUTER of the base wafer22and the cover wafer23, the sealing property in the central portion INNER of the wafer is not destroyed even if the crack is generated in the seal frame4during the dicing.

As described above, in the wafer level package according to one or more embodiments of the present invention, the plural chips are arrayed while mounted on or formed in the plane of the first wafer and the partial connect part is provided in the center portion on the opposed side of the seal frames opposed to each other.

Generally, in the device in which different materials are stacked, the stress is generated by the difference in thermal expansion coefficient during the temperature change. The stress increases with distance from the center of the device. Therefore, in the case that the partial connect part is located closest to the center of the device, namely, in the case that the plural chips are arrayed while mounted on or formed in the plane of the first wafer, the partial connect part is disposed in the center portion in each of the x-direction and the y-direction of the seal frame, thereby obtaining the best environment resistance.

On this point, in one or more embodiments of the present invention, the partial connect part is provided at the position where the thermal stress is minimized during the thermal expansion because the partial connect part is provided in the center portion on the opposed sides of the seal frames opposed to each other. Accordingly, the possibility that the partial connect part is destroyed becomes the minimum during the thermal expansion.

In one or more embodiments of the present invention, the partial connect part is provided in the center portion on the opposed sides of the seal frames opposed to each other, thereby locally equalizing the area ratio of the seal frame in the plane of the wafer. Accordingly, in the case that the seal frame is patterned using the resist mold and formed by the electrolytic plating, the electric flux density is equalized during the electrolytic plating when the partial connect part is formed in the center portion on the opposed sides of the seal frames by the electrolytic plating. As a result, the plating deposition rate is equalized in the plane of the wafer, and the variation in plating thickness decreases to be able to stabilize the run-around of the sealing material between the joined surfaces.

In the wafer level package of one or more embodiments of the present invention, the width of the partial connect part is equalized to the width of the seal frame.

In the case that the joined surfaces of the first wafer and the second wafer, particularly the joined surfaces of the seal frame and the first wafer and/or the second wafer are bonded using the bonding agent, the bonding agent moves to the wider pattern width by the influence of the surface tension when the bonding agent spreads onto the joined surface while the partial connect part differs from the seal frame in the pattern width.

On this point, in one or more embodiments of the present invention, the width of the partial connect part is equal to the width of the seal frame, so that the first wafer and the second wafer can be joined while the bonding agent spreads stably to both the partial connect part and the seal frame.

In the case that the seal frame is formed by the mold plating, the width of the partial connect part is equalized to the width of the seal frame to equalize the plating deposition rate in the plane. As a result, the variation in plating thickness decreases to be able to stabilize the run-around of the sealing material between the joined surfaces.

In the wafer level package of one or more embodiments of the present invention, the width of the partial connect part is greater than or equal to 1 μm.

The one partial connect part is provided in the side surface of each seal frame, and the width of the partial connect part is narrowed as much as possible within the range where the partial connect part can stably be joined. Therefore, the length of the joined portion to be diced can further be shortened. Therefore, the crack, which is generated in the joined portion during the dicing, can be reduced to the minimum to ensure the high reliability. From this viewpoint, according to one or more embodiments of the present invention, the minimum value of the width of the partial connect part is greater than or equal to 1 μm in consideration of the partial connect part that can be formed by the etching and the restriction to the alignment accuracy during the joining.

In the wafer level package of one or more embodiments of the present invention, the partial connect part can be provided in the gap only of the seal frame of the chip that is mounted on or formed in the outer circumferential portion of the first wafer in the chips that are mounted on or formed in the plane of the first wafer. As used herein, the outer circumferential portion of the first wafer specifically means the seal frames that are formed in the peripheries of at least the top third chips from the outermost circumference of the first wafer in both the x-direction and the y-direction.

Therefore, when the partial connect part of the seal frame is formed only in the outer circumferential portions of the first wafer and the second wafer, the partial connect part that traverses the dicing line does not exist in the seal frame in the central portions of the first wafer and the second wafer. Accordingly, the generation of the crack can be reduced in the seal frame.

In the wafer level package of one or more embodiments of the present invention, the partial connect part can be provided in the gap only of the seal frame of the chip that is mounted on or formed in the outermost circumference of the first wafer in the chips that are mounted on or formed in the plane of the first wafer.

Therefore, the number of chips in which the dicing line passes through the seal frame can be minimized by minimizing the number of partial connect parts, and the generation of the crack can further be reduced in the seal frame.

The present invention is not limited to the above embodiments, but various changes can be made without departing from the scope of the present invention. It is noted that an embodiment obtained by properly combining technical means disclosed in different embodiments is also included in the technical scope of the present invention.

One or more embodiments of the present invention can be applied to the wafer level package that is applied to the semiconductor package mounted on the electronic products typified by the mobile phone, the mobile computer, the personal digital assistance (PDA), and the digital still camera (DSC), the chip size package device such as the MEMS (Micro Electro Mechanical Systems) device, and the wafer level package manufacturing method.

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