Source/Drain Contacts and Methods for Forming the Same

Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a source/drain feature over a substrate; a metal gate structure extending lengthwise along a first direction and adjacent to the source/drain feature; a gate isolation structure extending lengthwise along a second direction substantially perpendicular to the first direction, and a source/drain contact electrically coupled to the source/drain feature and including a first portion directly above the source/drain feature and a second portion extending from the first portion along the first direction. In embodiments, the gate isolation structure divides the metal gate structure into two isolated portions. In embodiments, the first portion has a first width along the second direction and the second portion has a second width along the second direction, the first width being greater than the second width.

BACKGROUND

As integrated circuit (IC) technologies progress towards smaller technology nodes, electrical short may exist between adjacent metal gates and source/drain contacts disposed over source/drain features. This may impact the overall performance of an IC device. While existing source/drain contacts are generally adequate for their intended purposes, they are not satisfactory in all aspects.

DETAILED DESCRIPTION

As integrated circuit (IC) technologies progress towards smaller technology nodes, multi-gate devices are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a metal gate structure, or portion thereof, disposed over more than one side of a channel region. Fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. A FinFET has an elevated channel wrapped by a gate on more than one side (for example, the gate wraps a top and sidewalls of a “fin” of semiconductor material extending from a substrate). An MBC transistor has a metal gate structure that can extend, partially or fully, around a channel region to provide access to the channel region on two or more sides. Because its metal gate structure surrounds the channel region, an MBC transistor may also be referred to as a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor. The channel region of an MBC transistor may be formed from nanowires, nanosheets, other nanostructures, and/or other suitable structures. The shapes of the channel region have also given an MBC transistor alternative names such as a nanosheet transistor or a nanowire transistor. Variants of MBC transistors, such as those referred to as fish-bone structures or forksheet structures, have been proposed to reduce cell dimensions. In a forksheet structure, adjacent stacks of channel members may be divided by a dielectric wall (also referred to as a dielectric fin). The dielectric wall usually has a height substantially equal to or greater than that of the topmost channel members or that of the source/drain features. Complementary metal-oxide-semiconductor field effect transistors (CMOSFETs or CFETs) have dominated the semiconductor industry due to their high noise immunity and low static power consumption. A CFET includes an n-type FET (NFET) and a p-type FET (PFET) disposed side-by-side on the same substrate and the NFET and PFET share the same structure. In some embodiments, NFET and the PFET are both planar devices, both FinFETs, or both MBC transistors.

A semiconductor structure may have isolation features between segments of a metal gate structure, which are referred to as gate isolation structures or gate-cut structures. In one example, the metal gate structure may be cut into two or more portions and subsequently separated by gate isolation structure(s) in a process referred to as cut metal gate (CMG). The gate isolation structures are oriented lengthwise in a direction generally perpendicular to the direction of the metal gate structure. The gate isolation structures are formed by patterning process to form trenches and deposition to fill in the trenches with one or more dielectric materials. The patterning process includes lithography process and etching process and may use hard mask to define the regions for forming the gate isolation structures.

The semiconductor structure may have source/drain contacts formed over and electrically coupled to one or more source/drain features. An example process for forming a source/drain contact may include forming a source/drain contact opening exposing the source/drain features, and then forming a conductive layer in the source/drain contact opening. However, during the formation of the source/drain contact opening, due to, for example, etch variation, mask overlay of photolithography process, and/or critical dimension uniformity (CDU) limitations, the source/drain contact opening may be enlarged and/or shifted, leading to electrical short between the segments of the metal gate structure and the source/drain contact formed in the source/drain contact opening.

The present disclosure provides semiconductor structures and methods of forming the same. In an embodiment, a semiconductor structure includes a source/drain contact having a first portion disposed directly above the source/drain feature and a second portion disposed directly over an isolation feature and adjacent to a gate isolation structure. In an exemplary embodiment, to reduce or avoid electrical short between segments of the metal gate structure (e.g., a metal gate structure cut by the gate isolation structure) and the source/drain contact, the second portion of the source/drain contact has a reduced width compared to its first portion. In some embodiments, the second portion of the source/drain contact also has a reduced depth compared to the first portion of the source/drain contact.

The various aspects of the present disclosure will now be described in more detail with reference to the figures. In that regard,FIG.1is a flowchart illustrating method100of forming a semiconductor structure according to embodiments of the present disclosure. Method100is described below in conjunction withFIGS.2A-6D, which are fragmentary top or cross-sectional views of a workpiece200at different stages of fabrication according to embodiments of method100. Method100is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated therein. Additional steps may be provided before, during and after the method100, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method. Not all steps are described herein in detail for reasons of simplicity. Because the workpiece200will be fabricated into a semiconductor structure upon conclusion of the fabrication processes, the workpiece200may be referred to as the semiconductor structure200as the context requires.FIGS.7A-13Bare fragmentary top or cross-sectional views of workpieces300,400,500,600,700,800, and900, respectively, according to various alternative aspects of the present disclosure. The workpieces300,400,500,600,700,800, and900may be referred to as semiconductor structures300,400,500,600,700,800, and900, respectively. For avoidance of doubts, the X, Y and Z directions inFIGS.2A-13Bare perpendicular to one another and are used consistently throughout the present disclosure. Throughout the present disclosure, like reference numerals denote like features unless otherwise excepted.

Referring toFIGS.1and2A-2C, method100includes a block102where the workpiece200is received.FIG.2Adepicts a fragmentary top view of the workpiece200to undergo various stages of operations in the method ofFIG.1, according to various aspects of the present disclosure.FIGS.2B and2Cillustrate fragmentary cross-sectional views of the workpiece200taken along line B-B′ and line C-C′ as shown inFIG.2A, respectively.

As illustrated inFIGS.2A-2C, the workpiece200includes a substrate202. In one embodiment, the substrate202may be a silicon (Si) substrate. In some other embodiments, the substrate202may include other semiconductor materials such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate202may include multiple n-type well regions and multiple p-type well regions. A p-type well region may be doped with a p-type dopant (i.e., boron (B)). An n-type well region may be doped with an n-type dopant (i.e., phosphorus (P) or arsenic (As)).

In embodiments, the workpiece200includes a number of active regions204(e.g., fin-shaped active regions). As depicted inFIG.2A, each of the active regions204extends lengthwise along the X direction and is divided into channel regions204coverlapped by metal gate structures210aand210b(to be described below) and source/drain regions204sdnot overlapped by the metal gate structures210aand210b. Source/drain region(s)204sdmay refer to a source region or a drain region, individually or collectively dependent upon the context. The number of active regions204and the number of metal gate structures210aand210bshown inFIG.2Aare for illustration purpose only and should not be construed as limiting the scope of the present disclosure. In the depicted embodiments, the active regions204are disposed over the substrate202. In embodiments where the workpiece200includes FinFETs, the active regions204may be formed of a single semiconductor element (e.g., Si). In embodiments where the workpiece200includes MBC transistors, the active regions204include one or more nanostructures (e.g., a number of channel layers wrapped around by the metal gate structure210a/210b). Each of the nanostructures may be formed of silicon (Si).

In the present embodiments, the workpiece200also includes an isolation feature208(shown inFIG.2C) formed around each active region204to isolate two adjacent active regions204. The isolation feature208may also be referred to as a shallow trench isolation (STI) feature and may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. In some embodiments, the workpiece200includes a dielectric structure228(to be described below) disposed over the isolation feature208and source/drain features214a-214f(to be described below).

In embodiments, the workpiece200includes the metal gate structures210aand210bdisposed over the channel regions204cof the active regions204and extend lengthwise along the Y direction, such that the metal gate structure210ahas a first portion interposing the source/drain features214aand214cand a second portion interposing the source/drain features214band214d, and the metal gate structure210bhas a first portion interposing the source/drain features214cand214eand a second portion interposing the source/drain features214dand214f. The metal gate structures210aand210beach includes a high-k dielectric layer (i.e., having a dielectric constant greater than that of silicon oxide, which is about 3.9; not depicted) disposed over the active regions204and a metal gate electrode (not depicted) disposed over the high-k dielectric layer. The metal gate electrode may further include at least one work function metal layer disposed over the high-k dielectric layer and a bulk conductive layer disposed thereover. The work function metal layer may be a p-type or an n-type work function metal layer. Example work function materials include TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable work function materials, or combinations thereof. The bulk conductive layer may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or combinations thereof. The metal gate structures210aand210bmay further include numerous other layers (not depicted), such as an interfacial layer disposed between the active regions204and the high-k dielectric layer, hard mask layers, capping layers, barrier layers, other suitable layers, or combinations thereof. Various layers of the metal gate structures210aand210bmay be deposited by any suitable method, such as chemical oxidation, thermal oxidation, atomic layer deposition (ALD), CVD, physical vapor deposition (PVD), plating, other suitable methods, or combinations thereof. A polishing process, such as a chemical mechanical planarization/polishing (CMP) process, may be performed to remove excess materials from a top surface of the metal gate structures210aand210bto planarize a top surface of the workpiece200.

In some embodiments, the metal gate structures210aand210bare formed after other components of the workpiece200(e.g., the source/drain features214a-214f) are fabricated. Such process is generally referred to as a gate replacement process, which includes forming dummy gate structures (not depicted) as a placeholder for the metal gate structures210aand210b, forming the source/drain features214a-214f, forming the dielectric structure228over the dummy gate structures and the source/drain features214a-214f, planarizing the dielectric structure228by, for example, CMP, to expose top surfaces of the dummy gate structures, removing the dummy gate structures in the dielectric structure228to form trenches that expose the channel regions204cof the active regions204, and forming the metal gate structures210aand210bin the trenches to complete the gate replacement process.

In some embodiments, the dielectric structure228may include a contact etch-stop layer (CESL) and an interlayer dielectric (ILD) layer formed over the CESL. The ILD layer includes a dielectric material, such as tetraethylorthosilicate (TEOS), silicon oxide, a low-k dielectric material, doped silicon oxide such as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), FSG, boron doped silicate glass (BSG), other suitable dielectric materials, or combinations thereof. The ILD layer may include a multi-layer structure having multiple dielectric materials and may be formed by a deposition process such as, for example, CVD, FCVD, SOG, other suitable methods, or combinations thereof. The CESL may comprise silicon nitride, silicon oxynitride, silicon nitride with oxygen or carbon elements, other suitable materials, or combinations thereof, and may be formed by CVD, PVD, ALD, other suitable methods, or combinations thereof. The ILD layer may be deposited after the deposition of the CESL.

In some embodiments, the workpiece200includes the source/drain features214a-214fformed in and/or over the source/drain regions204sdof the active regions204, each being disposed adjacent to the metal gate structures210aand210b. The source/drain features214a-214ecan be separately or collectively referred to as source/drain feature(s)214. The source/drain features214a-214fmay be formed by any suitable techniques, such as etching processes followed by one or more epitaxial growth processes. In one example, one or more etching processes are performed to remove portions of the active regions204to form recesses (not shown) in the source/drain regions204sd. A cleaning process may be performed to clean the recesses with a hydrofluoric acid (HF) solution or other suitable solution. Subsequently, one or more epitaxial growth processes are performed to grow epitaxial source/drain features in the recesses. Each of the source/drain features214a-214fmay be suitable for forming a p-type FinFET device or alternatively, an n-type FinFET device. The p-type source/drain features may include one or more epitaxial layers of silicon germanium (epi SiGe) doped with a p-type dopant such as boron, germanium, indium, and/or other p-type dopants. The n-type source/drain features may include one or more epitaxial layers of silicon (epi Si) or silicon carbon (epi SiC) doped with an n-type dopant such as arsenic, phosphorus, and/or other n-type dopant.

In embodiments, the workpiece200further includes gate spacers212disposed on sidewalls of the metal gate structures210aand210b. The gate spacers212may include a dielectric material, such as an oxygen-containing material (e.g., silicon oxide, silicon oxycarbide, aluminum oxide, aluminum oxynitride, hafnium oxide, titanium oxide, zirconium aluminum oxide, zinc oxide, tantalum oxide, lanthanum oxide, yttrium oxide, silicon oxycarbonitride, etc.), a nitrogen-containing material (e.g., tantalum carbonitride, silicon nitride (SiN), zirconium nitride, silicon carbonitride, etc.), a silicon-containing material (e.g., hafnium silicide, silicon, zirconium silicide, etc.), other suitable materials, or combinations thereof. The gate spacers212may be a single layered structure or a multi-layered structure. Notably, the composition of the gate spacers212is distinct from that of the surrounding dielectric components, such that an etching selectivity may exist between the gate spacers212and the surrounding dielectric components during subsequent etching processes. In an embodiment, the gate spacers212include SiN. The gate spacers212may be formed by first depositing a blanket of spacer material over the workpiece200, and then performing an anisotropic etching process to remove portions of the spacer material to form the gate spacers212.

Referring toFIGS.1and3A-3C, method100includes a block104where a gate isolation trench256is formed to divide the metal gate structure210into two portions.FIG.3Adepicts a fragmentary top view of the workpiece200,FIGS.3B and3Cillustrate fragmentary cross-sectional views of the workpiece200taken along line B-B′ and line C-C′ as shown inFIG.3A, respectively. In some embodiments, the gate isolation trench256extends lengthwise along the X direction from a top view.

The forming of the gate isolation trench256may use any suitable methods. In an embodiment, photolithography process(es) and etching process(es) are performed to the workpiece200to form the gate isolation trench256. Portions of the metal gate structure210a, the gate spacers212, the dielectric structure228, and/or the isolation feature208are removed to form the gate isolation trench256. The etching process(es) may include wet etch, dry etch, or a combination thereof and etch through the conductive materials of the metal gate structure210a. The etching process(es) may use one or more etchant. In some implementations, the gate isolation trench256includes tapered sidewalls. In the present embodiments, the gate isolation trench256extends through the metal gate structure210aand extends downward into the isolation feature208as shown inFIG.3C. In some other implementations, the etching may stop at a top surface of the isolation feature208. The formation of the gate isolation trench256cuts the metal gate structure210ainto a first portion210a-1and a second portion210a-2(also referred to as a first metal gate structure210a-1and a second metal gate structure210a-2, respectively). The first portion210a-1and the second portion210a-2may also be collectively referred to as the metal gate structure210a. Dashed rectangle shown inFIG.3Cis the metal gate structure210aprojected on the cross-sectional view across line C-C′.

Referring toFIGS.1and4A-4C, method100includes a block106where a gate isolation structure222is formed in the gate isolation trench256.FIG.4Adepicts a fragmentary top view of the workpiece200,FIGS.4B and4Cillustrate fragmentary cross-sectional views of the workpiece200taken along line B-B′ and line C-C′ as shown inFIG.4A, respectively. The gate isolation structure222cuts/divides the metal gate structure210aelectrically and physically into two isolated portions (e.g., the first portion210a-1and the second portion210a-2).

The gate isolation structure222may cut and thus be in direct contact with the metal gate electrode of the metal gate structures210a-1and210a-2. In an embodiment, the gate isolation structure222extends into the isolation feature208. In some embodiments, the gate isolation structure222includes multiple layers, such as a first dielectric layer222aand a second dielectric layer222bembedded in the first dielectric layer222a. The formation of the gate isolation structure222may include conformally depositing the first dielectric layer222aover the workpiece200, depositing the second dielectric layer222bover the first dielectric layer222ato fill a remaining portion of the gate isolation trench256, and performing a planarization process to the workpiece200to remove excess portions of the first and the second dielectric layers222aand222bover the metal gate structures210aand210band define a final structure of the gate isolation structure222. The term “conformally” may be used herein for ease of description of a layer having substantially uniform thickness over various regions of the workpiece200. In embodiments, the first dielectric layer222aincludes silicon nitride (SiN) and may be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition process. In an embodiment, the first dielectric layer222aincludes silicon nitride. In some embodiments, the second dielectric layer222bincludes a high-k dielectric material, a low-k dielectric material, other suitable materials, or combinations thereof. Example materials of the second dielectric layer222binclude silicon oxide (SiO and SiO2), silicon nitride, silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiCON), aluminum oxide, zirconium silicate (ZrSiO4), and hafnium silicate (HfSiO4). In some embodiments, the second dielectric layer222bincludes silicon oxide. The second dielectric layer222bmay be deposited by CVD, PECVD, flowable CVD, PVD, ALD, other suitable methods, or combinations thereof. In an embodiment, the second dielectric layer222bincludes silicon oxide. In some embodiments, the gate isolation structure222may be a single-layer structure. In some embodiments, the gate isolation structure222and the gate spacers212include different dielectric materials. In embodiments, the gate spacers212include a dielectric material having a dielectric constant greater than a dielectric material of the gate isolation structure222. In an embodiment, the gate spacers212include silicon nitride and the gate isolation structure222includes silicon oxide.

Referring toFIGS.1and5A-5D, method100includes a block108where a trench (e.g., trench260a,260b, and/or260c) is formed to expose the source/drain features214.FIG.5Adepicts a fragmentary top view of the workpiece200,FIGS.5B and5Cillustrate fragmentary cross-sectional views of the workpiece200taken along line B-B′ and line C-C′ as shown inFIG.5A, respectively,FIG.5Dillustrates enlarged top views of the trenches260aand260b.

In this step, to form the trench260aor260b, portions of the dielectric structure228and portions of the gate isolation structure222are removed to expose the source/drain features214using a combination of photolithography process(es) and etch process(es), such as dry etching, wet etching, and/or reactive ion etching (RIE)). In an example process, a hard mask layer and a photoresist are deposited over the workpiece200. The photoresist layer is then exposed to a patterned radiation transmitting through or reflected from a photo mask, baked in a post-exposure bake process, developed in a developer solution, and then rinsed, thereby forming a patterned photoresist layer. The patterned photoresist layer is then applied as an etch mask to etch the hard mask layer to form a patterned hard mask layer. The patterned hard mask layer is then applied as an etch mask to etch the dielectric structure228and the gate isolation structure222. The etch process may be a dry etch process that includes use of argon (Ar), a fluorine-containing etchant (for example, SF6, NF3, CH2F2, CHF3, C4F8, and/or C2F6), an oxygen-containing etchant, a chlorine-containing etchant (for example, Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing etchant (for example, HBr and/or CHBr3), an iodine-containing etchant, oxygen, hydrogen, other suitable gases, or combinations thereof.

In the present embodiments, a cross-sectional view of the workpiece200taken along line A-A′ shown inFIG.5Ais substantially identical to the cross-sectional view of the workpiece200taken along line B-B′. Accordingly, the cross-sectional view of the workpiece200taken along line A-A′ is omitted in the description of subsequent processing stages. A person skilled in the art understands that cross-sectional view of the workpiece200taken along line A-A′ at those processing stages substantially mirrors those depicted for the cross-sectional view of the workpiece200taken along line B-B′. Although three trenches260a-260care depicted, it is understood that the workpiece200may include any combination and number of the trenches260a-260cin various relative positions. For example, depending on the position of the gate isolation structure222, a workpiece may include a trench260aexposing the source/drain features214cand214dand a trench260cexposing the source/drain features214cand214f. In the present embodiments, the trenches260a,260b, and260cinclude tapered sidewalls. In some other implementations, the trenches260a,260b, and260cmay include substantially vertical sidewalls.

In some embodiments, each of the trenches260a-260care formed to penetrate into the dielectric structure228and/or into the gate isolation structure222. More specifically, in some embodiments, the gate isolation structure222and the trench260across over each other from a top view as shown inFIG.5A. The trench260aincludes two first portions260a-1and a second portion260a-2spanning between the two first portions260a-1. The two first portions260a-1and the second portion260a-2are divided by dashed lines inFIG.5D. The two first portions260a-1expose the source/drain features214aand214b, respectively. In embodiments, the second portion260a-2does not have an overlap with the metal gate structure210aprojected on the cross-sectional view across line C-C′. The trench260ahas a shape having a non-uniform width along its length from a top view. In an embodiment, the two first portions260a-1span a width W1 along the X direction and a depth D1 along the Z direction. The width W1 may be substantially the same as or smaller than a distance between adjacent gate spacers212on two sides of each of the trenches260a,260b, and260c. In some embodiments, the second portion260a-2spans a width W3 along the X direction and a depth D3 along the Z direction. The width W1 is greater than the width W3. In an embodiment, a ratio of the width W3 to the width W1 (i.e., W3/W1) is in a range of about 0.5 to about 0.95. If W3/W1 is too small, contact resistance between the source/drain contact (e.g., the source/drain contact218a, to be described below) to be formed in the trench260aand the source/drain features (e.g., source/drain features214aand214b) thereunder may be too large. If W3/W1 is too large, the second portion260a-2may be too close to the adjacent metal gate structures210a-1and210a-2, electrical short issue between the metal gate structures210a-1and210a-2and the source/drain contact218amay persist. In some embodiments, the depth D1 is greater than the depth D3. In an embodiment, a ratio of the depth D3 to the depth D1 is in a range of about 0.3 to about 0.95.

In embodiments, an end222eof the gate isolation structure222and the trench260bhave an overlap from a top view as shown inFIG.5A. Similar to the trench260a, the trench260bincludes two first portions260b-1and a second portion260b-2spanning between the two first portions260b-1. The two first portions260b-1expose the source/drain features214cand214d, respectively. In some embodiments, referring toFIG.5C, a portion of the sidewall of the gate spacers212is exposed to the second portion260b-2. In embodiments, the second portion260b-2does not have an overlap with the metal gate structure210aprojected on the cross-sectional view across line C-C′. The trench260bhas a shape having a non-uniform width along its length from a top view. In an embodiment, the two first portions260b-1span the width W1 along the X direction and the depth D1 along the Z direction. In some embodiments, as depicted inFIG.5C, the second portion260b-2spans a width W4 along the X direction and a depth D4 along the Z direction. The width W1 is greater than the width W4. In an embodiment, a ratio of the width W4 to the width W1 (i.e., W4/W1) is in a range of about 0.7 to about 0.95. If W4/W1 is too small, contact resistance between the source/drain contact (e.g., the source/drain contact218b, to be described below) to be formed in the trench260band the source/drain features (e.g., source/drain features214cand214d) thereunder may be too large. If W4/W1 is too large, the second portion260b-2may be too close to the adjacent metal gate structures210a-1and210a-2, electrical short between the metal gate structures210a-1and210a-2and the source/drain contact218bmay persist. In some embodiments, the depth D1 is greater than the depth D4. In an embodiment, a ratio of the depth D4 to the depth D1 is in a range of about 0.5 to about 0.95.

In some embodiments, the width W4 is equal to or greater than the width W3. In an embodiment, a ratio of the width W3 to the width W4 (i.e., W3/W4) is in a range of about 0.7 to about 1. If W3/W4 is too small, contact resistance between the source/drain contact218aand the source/drain features (e.g., source/drain features214aand214b) thereunder may be too large, affecting an overall performance of the semiconductor structure or the second portion260b-2of the trench260bmay be too close to the adjacent metal gate structures210a-1and210a-2, electrical short between the metal gate structures210a-1and210a-2and the source/drain contact218bmay persist. If the ratio of W3/W4 is too large, contact resistance between the source/drain contact218band the source/drain features (e.g., source/drain features214cand214d) thereunder may be too large, affecting an overall performance of the semiconductor structure or the second portion260a-2of the trench260amay be too close to the adjacent metal gate structures210a-1and210a-2, electrical short between the metal gate structures210a-1and210a-2and the source/drain contact218amay persist. In some embodiments, the depth D4 is equal to or greater than the depth D3. In an embodiment, a ratio of the depth D3 to the depth D4 is in a range of about 0.5 to about 1.

In embodiments, the trench260cis spaced apart from the gate isolation structure222. The trench260cexposes the source/drain features214eand214f. The trench260chas a shape having a substantially uniform width W2 along its length from a top view and a depth D2 along the Z direction. The width W2 is substantially equal to the width W1. The depth D2 is substantially equal to the depth D1.

Referring toFIGS.1and6A-6D, method100includes a block110where source/drain contacts218a,218b, and218care formed in the trenches260a,260b, and260c, respectively.FIG.6Adepicts a fragmentary top view of the workpiece200,FIGS.6B and6Cillustrate fragmentary cross-sectional views of the workpiece200taken along line B-B′ and line C-C′ as shown inFIG.6A, respectively,FIG.6Dillustrates enlarged top views of the source/drain contacts218aand218b.

Before forming the source/drain contacts218a-218c, a silicide layer (not depicted) may be formed over each of the source/drain features214a-214f. In some embodiments, the silicide layer includes a metal silicide, such as nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, other suitable silicides, or combinations thereof. The silicide layer may be formed by a deposition process such as CVD, ALD, PVD, other suitable processes, or combinations thereof. For example, a metal layer (e.g., nickel) may be deposited over the source/drain features214a-214f. Then, the workpiece200is annealed to allow the metal layer and the semiconductor materials of the source/drain features214a-214fto react. Thereafter, the un-reacted metal layer is removed, leaving the silicide layer over the source/drain features214a-214f. Alternatively, the silicide layer may be directly formed over the source/drain features214a-214fby any suitable deposition method, such as CVD, ALD, PVD, other suitable methods, or combinations thereof.

Forming the source/drain contacts218a,218b, and218cmay include depositing a conductive layer (not depicted) in the trenches260a,260b, and260cand over portions of the metal gate structures210aand210b, the gate spacers212, and the dielectric structure228. The conductive layer may include any suitable material, such as W, Co, Ru, Cu, Ta, Ti, Al, Mo, other suitable conductive materials, or combinations thereof. The conductive layer may be deposited by any suitable method, such as CVD, PVD, ALD, plating, other suitable methods, or combinations thereof. Thereafter, the method100planarizes the top surface of the workpiece200using a suitable method such as CMP to form the source/drain contacts218a,218b, and218cover the source/drain features214and in the trenches260a,260b, and260c, respectively, such that a top surface of the conductive layer (i.e., the formed source/drain contacts218a,218b, and218c) is substantially coplanar with top surfaces of the metal gate structures210aand210b. In some embodiments, before the deposition of the conductive layer, a glue layer (not depicted) may be formed over the workpiece200to partially fill the trenches260a-260c. The glue layer may include TiN, TaN, etc.

The source/drain contacts218a-218ctrack the shapes of the trenches260a-260c, respectively. That is, dimensions (e.g., widths, depths) of the source/drain contacts218a,218b, and218care substantially the same as the trenches260a,260b, and260c, respectively. For example, the first portions218a-land218b-1of the source/drain contacts218aand218bhave the depth D1, the second portion218a-2of the source/drain contact218ahas the depth D3, and the second portion218b-2of the source/drain contact218bhas the depth D4. In embodiments, the first portions218a-land218b-1of the source/drain contacts218aand218bhave the width W1, the second portion218a-2of the source/drain contact218ahas the depth W3, and the second portion218b-2of the source/drain contact218bhas the width W4. The source/drain contact218chas substantially the same width (i.e., the depth W2) and substantially the same depth (i.e., the depth D2).

In addition, the source/drain contact218aincludes two first portions218a-1directly above and electrically coupled to the source/drain features214aand214b, respectively, and a second portion218a-2extending between the two first portions218a-1. In embodiments, from a top view, the second portion218a-2of the source/drain contact218aincludes two edges220a(shown inFIG.6D) curved inward. Referring toFIG.6C, the second portion218a-2doesn't overlap with the metal gate structure210aprojected on the cross-sectional view across line C-C′. In embodiments, the second portion218a-2is embedded in the gate isolation structure222.

The source/drain contact218bincludes two first portions218b-1directly above and electrically coupled to the source/drain features214cand214d, respectively, and a second portion218b-2extending between the two first portions218b-1. In the depicted embodiment as inFIG.6D, the second portion218b-2of the source/drain contact218bincludes a first edge220b-1curved inward. A second edge220b-2opposite to the first edge220b-1of the second portion218b-2of the source/drain contact218bis aligned with an edge220b-3of the first portions218b-1of the source/drain contact218balong the Y direction. In other words, from a top view, the first portions218b-1and the second portion218b-2of the source/drain contact218bshare a continuous edge extending along the Y direction, and the continuous edge is substantially straight. Put differently, there is no significant offset between the second edge220b-2and the edge220b-3along the Y direction. A distance between the first edge220b-1of the second portion218b-2of the source/drain contact218band the metal gate structure210ais less than a distance between the second edge220b-2of the second portion218b-2of the source/drain contact218band the metal gate structure210a.

In some embodiments, referring toFIG.6C, a boundary223of the gate isolation structure222is directly under the second portion218b-2of the source/drain contact218b. A bottom surface of the second portion218b-2is in direct contact with both the gate isolation structure222and the dielectric structure228. In an embodiment, a portion of the dielectric structure228is interposed between the second portion218b-2and the gate spacers212. In embodiments, the second portion218b-2is in direct contact with a sidewall of the gate isolation structure222. In embodiments, the source/drain contact218bdoesn't overlap with the metal gate structure210aprojected on the cross-sectional view across line C-C′. A region219circled by dotted lines around the second portion218b-2indicates a region where the source/drain contact218bmay be formed within even if there is, for example, an etch variation, overlay shift, during the formation of the trench260b. In embodiments, the gate spacers212are etched at a slower etching rate than that of the gate isolation structure222. Thus, during the formation of the trench260b, the gate isolation structure222is etched more than the gate spacers212. Because the second portion218b-2has a width (e.g., width W4) less than that of the two first portions218b-1, a distance from the second portion218b-2to the projected metal gate structure210ais increased. Thus, even if there are fabrication variations during the formation of the trench260b, because of the increased distance, the possibility of the second portion218b-2being in direct contact with an end of the metal gate structures210a-1/210a-2is reduced. Therefore, electrical short between the metal gate structure210aand the second portion218b-2may be avoided. For similar reasons, a distance from the second portion218a-2of the source/drain contact218ato the projected metal gate structure210ais increased, electrical short between the metal gate structure210aand the second portion218a-2is also eliminated.

Referring back toFIG.1, method100includes a block110where further processes are performed to finish the fabrication of the workpiece200. Such further processes may include forming a multi-layer interconnect (MLI) structure (not depicted) over the workpiece200. In some embodiments, the MLI structure may include multiple intermetal dielectric (IMD) layers and multiple metal lines or contact vias in each of the IMD layers. In some instances, the IMD layers and the dielectric structure228may share similar composition. The metal lines and contact vias in each IMD layer may be formed of metal, such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be lined by a barrier layer to insulate the metal lines and contact vias from the IMD layers.

In the present embodiments, the gate isolation structure222is formed after the forming of the metal gate structures210aand210b. In some other implementations, the gate isolation structure222may be formed before or after forming dummy gate structures. For example, the gate isolation structure222may be formed to cut a dummy gate structure into two portions, and the two portions of the dummy gate structure may be then replaced by two metal gate structures (e.g., metal gate structures210a-1and210a-2), respectively.

FIG.7Adepicts a fragmentary top view of a first alternative workpiece300,FIGS.7B and7Cillustrate fragmentary cross-sectional views of the workpiece300taken along line B-B′ and line C-C′ as shown inFIG.7A, respectively. The workpiece300represented inFIGS.7A-7Cis similar to the workpiece200described with reference toFIGS.6A-6D. One of the differences between the workpiece300and the workpiece200includes that, in this alternative embodiment, the workpiece300includes a dielectric barrier layer232. More specifically, to prevent diffusion of the conductive layer, after the formation of the trenches260a-260c, a dielectric barrier layer232is formed over the workpiece300and then etched back to only cover sidewalls of the trenches260a-260cand expose the source/drain features214. The source/drain contacts218a,218b, and218cmay then be formed in the trenches260a-260c. That is, sidewall surfaces of each of the source/drain contacts218a,218b, and218care lined by the dielectric barrier layer232continuously. In some embodiments, the dielectric barrier layer232may include silicon nitride or other suitable materials.

FIG.8Adepicts a fragmentary top view of a second alternative workpiece400,FIGS.8B and8Cillustrate fragmentary cross-sectional views of the workpiece400taken along line B-B′ and line C-C′ as shown inFIG.8A, respectively. The workpiece400represented inFIGS.8A-8Cis similar to the workpiece200described with reference toFIGS.6A-6D. One of the differences between the workpiece400and the workpiece200includes that, in this alternative embodiment, the workpiece400includes a self-aligned cap (SAC) layer252formed over the metal gate structures210aand210b. In an example process, a SAC recess may be formed by removing (e.g., etching) top portions of the metal gate structures210aand210b. Then a dielectric material (not depicted) may be deposited over the workpiece400including the SAC recess by CVD, PECVD, or a suitable deposition process. The dielectric material may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, or a suitable dielectric material. After the deposition of the dielectric material, a planarization process, such as a CMP process, may be performed to remove excess dielectric material over the dielectric structure228, thereby forming the SAC layer252directly over the metal gate structures210aand210b. After the forming of the SAC layer252, photolithography processes and etch processes are then performed to form the gate isolation trench256. In the present embodiments, due to the recess of the metal gate structures210aand210b, a top surface of the source/drain contact218a/218b/218cis above top surfaces of the recessed metal gate structures210aand210b. In embodiments, top surfaces of the source/drain contacts218a.218b, and218care coplanar with a top surface of the SAC layer252.

In the depicted embodiment, sidewalls of the SAC layer252are in direct contact with the at least one gate spacer212and a bottom surface of the SAC layer252is in direct contact with top surfaces of the high-k dielectric layer and the metal gate electrode of the metal gate structures210aand210b. In some other implementations, the SAC layer252may have other configurations. For example, the SAC recess may be formed by recessing top portions of the metal gate structures210aand210band recessing top portions of the gate spacers212, and the resulted SAC layer252may be formed directly on the recessed gate spacers212and the metal gate structures210aand210b. Top surfaces of the recessed gate spacers212may be above top surfaces of the metal gate structures210aand210b.

FIG.9Adepicts a fragmentary top view of a third alternative workpiece500,FIG.9Billustrates a fragmentary cross-sectional view of the workpiece500taken along line B-B′ as shown inFIG.9A. The workpiece500represented inFIGS.9A-9Bis similar to the workpiece200described with reference toFIGS.6A-6D. One of the differences between the workpiece500and the workpiece200includes that, in this alternative embodiment, the configuration of the source/drain contacts of workpiece500are different from that of workpiece200.

In embodiments, the workpiece500includes one or more dielectric structures236and240formed over the metal gate structures210aand210b, and the source/drain contacts218a,218b, and218cextend upward above top surfaces of the metal gate structures210aand210band extend through the dielectric structure236. The workpiece500may further include one or more contact vias250embedded in the dielectric structure240and over and electrically coupled to the source/drain contacts218a,218b, and/or218c, and a gate contact via244over and electrically coupled to the metal gate structure210b. In embodiments, a cross-sectional view of the workpiece500along line C-C′ may be similar to the workpiece200represented inFIG.6C, except that the one or more dielectric structures236and240are disposed over the gate isolation structure222, the dielectric structure228, and the metal gate structures210aand210b, and the source/drain contacts218a,218b, and218cextend upward into/through the dielectric structure236.

In an example process, the dielectric structure236is formed over the dielectric structure228. Lithography process(es) and etch process(es) are performed to the workpiece500to form the trenches260a-260bthrough the dielectric structure236, the dielectric structure228, and the gate isolation structure222, such that the upper surfaces of their respective source/drain features214below are exposed. In a subsequent process, the source/drain contacts218a,218b, and218care formed in the trenches260a-260b, similar to the process described inFIGS.6A-6D. Further processes may include forming dielectric structure240over the dielectric structure236, forming contact vias250in the dielectric structure240, and forming the gate contact via244.

FIG.10illustrates a fragmentary cross-sectional view of a fourth alternative workpiece600. A fragmentary top view of the fourth alternative workpiece600is similar toFIG.6A, a fragmentary cross-sectional view of the workpiece600taken along line B-B′ as shown inFIG.6Ais similar toFIG.6B.FIG.10illustrates a fragmentary cross-sectional view of the workpiece600taken along line C-C′ as shown inFIG.6A. In the above embodiments described with reference toFIGS.6A-6D, to form the gate isolation trench256, portions of the gate spacers212and the metal gate structure210aexposed by the gate isolation trench256are substantially removed. In the fourth alternative embodiment represented inFIG.10, when forming the gate isolation trench256, a selective etching process is performed to selectively remove the portion of the metal gate structure210aexposed by the gate isolation trench256while the exposed portions of the gate spacers212are slightly etched, such that a portion of the gate spacers212(also referred to as remaining gate spacers212a) and a portion of the dielectric structure228(also referred to as a remaining dielectric structure228a) are exposed by the gate isolation trench256after the selective etching process. In embodiments, sidewalls of the remaining gate spacers212aare substantially not etched. Any suitable methods may be used in the selective etching process, such as wet etch, dry etch or a combination thereof using suitable etchants to etch various materials.

In the present embodiments, the gate isolation structure222formed in the gate isolation trench256includes a first part222-1directly above the remaining gate spacers212aand a second part222-2between two adjacent remaining gate spacers212a. In embodiments, the first part222-1of the gate isolation structure222is also directly above the remaining dielectric structure228a. In some embodiments, the second part222-2of the gate isolation structure222extends into the isolation feature208and has a depth D7. The first part222-1of the gate isolation structure222has a depth D8. The depth D7 may be greater than a depth D9 of the metal gate structures210aand210b. In embodiments, a ratio of the depth D7 to the depth D9 is in a range of about 1.05 to about 3. If the ratio is too small, the gate isolation structure222may not completely divide the metal gate structure210ainto two isolated portions. If the ratio is too large, the gate isolation structure222may extend through the isolation feature208and extend into the substrate202, leading to an increased leakage current. The depth D7 may be greater than the depth D8. In some embodiments, a ratio of the depth D7 to the depth D8 is in a range of about 1.05 to about 5.

Still referring toFIG.10, an upper part of the second portion218b-2of the source/drain contact218bis separated from the second part222-2of the gate isolation structure222by the first part222-1of the gate isolation structure222, a lower part of the second portion218b-2of the source/drain contact218bis separated from the second part222-2of the gate isolation structure222by the remaining dielectric structure228aand the remaining gate spacer212a. In the depicted embodiment, a bottom surface of the second portion218b-2of the source/drain contact218bis below a top surface of the adjacent remaining gate spacer212a. In some other embodiments, the bottom surface of the second portion218b-2of the source/drain contact218bis coplanar with or above the top surface of the adjacent remaining gate spacer212a. In some embodiments, the second portion218a-2of the source/drain contact218ais directly above the remaining dielectric structure228a. A bottom surface of the second portion218a-2of the source/drain contact218amay be above, below, or at a same level with a top surface of the adjacent remaining gate spacer212a.

Similar to the embodiments described with reference toFIG.6C, the region219around the second portion218b-2of the source/drain contact218bindicates a region where the source/drain contact218bmay be formed within even if there is, for example, an etch variation, overlay shift, during the formation of the trench260b. For similar reasons as described above, possibility of the second portion218b-2being in direct contact with an end of the metal gate structure210ais reduced. In addition, in some embodiments, because the gate spacer212aare etched at a slower etching rate than the rate at which the gate isolation structure222is etched when forming the trench260b, the adjacent remaining gate spacer212aprovides more burdens to avoid the second portion218b-2being in direct contact with an end of the metal gate structure210a. Therefore, electrical short between the metal gate structure210aand the second portion218b-2of the source/drain contact218bmay be avoided. For similar reasons, electrical short between the metal gate structure210aand the second portion218a-2of the source/drain contact218ais also eliminated.

FIG.11Adepicts a fragmentary top view of a fifth alternative workpiece700,FIG.11Billustrates a fragmentary cross-sectional view of the workpiece700taken along line C-C′ as shown inFIG.11A,FIG.11Cillustrates enlarged top views of source/drain contacts218dand218c. A fragmentary cross-sectional view of the workpiece700taken along line B-B′ as shown inFIG.11Ais similar toFIG.6Band is thus omitted for reason of simplicity. The workpiece700is similar to the workpiece200described with reference toFIGS.6A-6C, and one of the differences between the workpiece700and the workpiece200includes that, the gate isolation structures of the workpiece700have different configurations than that of the workpiece200. More specifically, the workpiece700includes a first gate isolation structure222L configured to cut the metal gate structure210ainto two portions210a-1and210a-2(also referred to as metal gate structures210a-1and210a-2, and collectively referred to as metal gate structure210a) and a second gate isolation structure222R configured to cut the metal gate structure210binto two portions210b-1and210b-2(also referred to as metal gate structures210b-1and210b-2, and collectively referred to as metal gate structure210b). The formation of the second gate isolation structures222L and222R are similar to the formation of the gate isolation structure222except that each of the two gate isolation trenches (not depicted) spans a width less than that of the trench256, and each of the two gate isolation trenches doesn't divide the gate spacers into physically isolated segments. That is, edges of each of the two gate isolation trenches are also confined by two partially etched gate spacers212. As a result, as represented inFIGS.11A-11C, the portion (also referred to as remaining gate spacer212b) of the gate spacer212that is disposed directly over the isolation feature208and in direct contact with the gate isolation structure222L/222R has a width along the X direction less than that of the portion of the gate spacer212that is disposed directly on the sidewall surface of the metal gate structures210aand210b, and the remaining gate spacer212bis in direct contact with the gate isolation structure222L or222R. The remaining gate spacers212bhave the same height as the portion of the gate spacers212that is disposed directly on the sidewall surface of the metal gate structures210aand210b.

Similar to the source/drain contact218ainFIGS.6A-6D, referring toFIGS.11A-11C, the source/drain contact218dhas two first portions218d-1directly above the source/drain features214aand214band a second portion218d-2extending between the two first portions218d-1. The second portion218d-2is between and adjacent to the two gate isolation structures222L and222R. In embodiments represented inFIG.11B, the second portion218d-2is embedded in the dielectric structure228, which is between two adjacent remaining gate spacers212b. More specifically, the second portion218d-2is spaced apart from the gate isolation structures222L and222R by the remaining gate spacers212band the dielectric structure228.

Similar to the source/drain contact218binFIGS.6A-6D, the source/drain contact218ehas two first portions218e-1directly above the source/drain features214cand214dand a second portion218e-2extending between the two first portions218e-1. The second portion218e-2is adjacent to the gate isolation structure222R on one side. In embodiments, the second portion218e-2is embedded in the dielectric structure228, which is between an adjacent remaining gate spacer212band an adjacent gate spacer212. In embodiments, the second portion218e-2is spaced apart from the gate isolation structure222R by the remaining gate spacer212band the dielectric structure228. In some embodiments, the source/drain contact218eis in direct contact with an adjacent gate spacer212.

Similar to the embodiments described with reference toFIG.6C, the region219(shown inFIG.11B) indicates a region where the source/drain contact218emay be formed within even if there is, for example, an etch variation, overlay shift, during the formation of the trench260e(the trench for the source/drain contact218e, not depicted). In embodiments, the gate spacers212are etched at a slower etching rate than that of the dielectric structure228. Thus, during the formation of the trench260e, the dielectric structure228is etched more than the gate spacers212. For similar reasons as described above, possibility of the second portion218e-2being in direct contact with an end of the metal gate structure210bis reduced. In addition, in some embodiments, because the remaining gate spacer212bis etched at a slower etching rate than the isolation gate structure222R when forming the trench260e, the adjacent remaining gate spacer212bprovides more burdens to avoid the second portion218e-2being in direct contact with an end of the metal gate structure210b. Therefore, electrical short between the metal gate structure210band the second portion218e-2of the source/drain contact218eis avoided. For similar reasons, electrical short between the metal gate structures210aand210band the second portion218d-2of the source/drain contact218dis also eliminated.

The source/drain contacts218dand218ehave similar shapes as the source/drain contacts218aand218b, respectively. In embodiments, the second portion218d-2of the source/drain contact218dhas a width W5 along the X direction and a depth D5 along the Z direction. In embodiments, the width W5 is smaller than the width W1. In some embodiments, a ratio of the width W5 to the width W1 (i.e., W5/W1) is in a range of about 0.5 to about 0.95. If W5/W1 is too small, contact resistance between the source/drain contact218dand the source/drain features (e.g., source/drain features214aand214b) thereunder may be too large. If W5/W1 is too large, the second portion260d-2may be too close to the adjacent metal gate structures210aand210b, electrical short between the metal gate structures210aand210band the source/drain contact218dmay persist. In embodiments, the depth D5 is smaller than the depth D1. In an embodiment, a ratio of the depth D5 to the depth D1 is in a range of about 0.3 to about 0.95.

In embodiments, the second portion218e-2of the source/drain contact218ehas a width W6 along the X direction and a depth D6 along the Z direction. In some embodiments, the width W6 is smaller than the width W1. In embodiments, a ratio of the width W6 to the width W1 (i.e., W6/W1) is in a range of about 0.5 to about 0.95, alternatively in a range of about 0.7 to about 0.95. If W6/W1 is too small, contact resistance between the source/drain contact218eand the source/drain features (e.g., source/drain features214cand214d) thereunder may be too large. If W6/W1 is too large, the second portion260e-2may be too close to the adjacent metal gate structure210b, electrical short between the metal gate structure210band the source/drain contact218emay persist. In some embodiments, the depth D6 is smaller than the depth D1. In an embodiment, a ratio of the depth D6 to the depth D1 is in a range of about 0.5 to about 0.95.

In some embodiments, the width W6 is equal to or greater than the width W5. In some embodiments, a ratio of the width W5 to the width W6 (i.e., W5/W6) is in a range of about 0.7 to about 1. If W5/W6 is too small, contact resistance between the source/drain contact218dand the source/drain features (e.g., source/drain features214aand214b) thereunder may be too large, affecting an overall performance of the semiconductor structure or the second portion218e-2may be too close to the adjacent metal gate structure210b, electrical short between the metal gate structure210band the source/drain contact218emay persist. If W5/W6 is too large, contact resistance between the source/drain contact218eand the source/drain features (e.g., source/drain features214cand214d) thereunder may be too large, affecting an overall performance of the semiconductor structure or the second portion218d-2may be too close to the adjacent metal gate structures210aand210b, electrical short between the metal gate structures210aand210band the source/drain contact218dmay persist. In some embodiments, the depth D6 is equal to or greater than the depth D5. In an embodiment, a ratio of the depth D5 to the depth D6 is in a range of about 0.5 to about 1.

FIG.12Adepicts a fragmentary top view of a sixth alternative workpiece800,FIG.12Billustrates a fragmentary cross-sectional view of the workpiece800taken along line C-C′ as shown inFIG.12A. A fragmentary cross-sectional view of the workpiece800taken along line B-B′ as shown inFIG.12Ais similar toFIG.8B. One of the differences between the workpiece800and the workpiece700includes that, in this alternative embodiment, the workpiece800includes a SAC layer252′ formed over the metal gate structures210aand210b. The SAC layer252′ may have the same material as and is formed similarly to the SAC layer252described inFIGS.8A-8C. In some embodiments, top surfaces of the source/drain contacts218d,218c, and218care above top surfaces of the metal gate structures210.

In the above embodiments described with reference toFIGS.6A-12A, the source/drain contact is configured to have a non-uniform width along its length direction, and example top views of the source/drain contact are shown. In some alternative embodiments, from a top view, the source/drain contacts (e.g.,218aand218b) have different shapes.FIG.13Adepicts a fragmentary top view of a seventh alternative workpiece900.FIG.13Billustrates enlarged top views of the source/drain contacts218aand218b. One of the differences between the workpiece900and the workpiece200includes that, in this alternative embodiment, from a top view, the two edges220a-1of the second portion218a-2of the source/drain contact218aand a first edge220b-1of the second portion218b-2of the source/drain contact218bare substantially straight and recessed from the edges220a-3and220b-4of the first portions218a-1and218b-1, respectively. In other words, from a top view, a profile of the source/drain contact218aresembles a dumbbell shape. The dimensions (e.g., widths, depths) of the source/drain contacts218aand218bmay be the same as described before.

Various combinations of the embodiments of the semiconductor structure and the method of making the same are within the scope of the present disclosure. For example, a workpiece may include the SAC layer252and the dielectric barrier layer232. In another example, the source/drain contacts218a,218b,218c,218d, and/or218eextend above a top surface of the metal gate structures210aand210band have a shape shown inFIGS.13A-13B. The source/drain contacts218a,218b,218c,218d, and/or218emay be arranged in any number and any position relative to each other.

Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor structure and the formation thereof. For example, one advantage is that the present disclosure reduces/avoids the electrical short between source/drain contacts and the adjacent metal gate structure(s) without sacrificing a relative low contact resistance between the source/drain contacts and the source/drain features thereunder. The present disclosure is compatible to various semiconductor fabrication processes, and compatible to various semiconductor structures (e.g., semiconductor structures having a SAC layer and/or a dielectric barrier layer). The semiconductor structure may include a planar transistor or a multi-gate device, such as FinFET, GAA, nanosheet, forksheet, or CFET.

The present disclosure provides for many different embodiments. Semiconductor structures and methods of fabrication thereof are disclosed herein. In one exemplary aspect, the present disclosure is directed to a semiconductor structure including a source/drain feature over a substrate, a metal gate structure extending lengthwise along a first direction and adjacent to the source/drain feature, and a gate isolation structure extending lengthwise along a second direction substantially perpendicular to the first direction. The gate isolation structure divides the metal gate structure into two isolated portions. The semiconductor structure further includes a source/drain contact electrically coupled to the source/drain feature and having a first portion directly above the source/drain feature and a second portion extending from the first portion along the first direction. The first portion has a first width along the second direction and the second portion has a second width along the second direction. The first width is greater than the second width.

In some embodiments, the second portion of the source/drain contact includes two edges curved inward from a top view. In some embodiments, from a cross-sectional view, a boundary of the gate isolation structure is directly under the second portion of the source/drain contact. In some embodiments, the first portion of the source/drain contact has a first depth and the second portion of the source/drain contact has a second depth less than the first depth. In some embodiments, the semiconductor structure further includes an isolation feature over the substrate and under the gate isolation structure, and gate spacers extending lengthwise along the first direction and including a first part on sidewalls of the metal gate structure and a second part disposed directly over the isolation feature. The second part of the gate spacers is directly under a first part of the gate isolation structure. In some embodiments, the gate isolation structure further includes a second part adjacent to the second part of the gate spacers. The second part of the gate isolation structure extends into the isolation feature and has a bottom surface lower than a bottom surface of the first part of the gate isolation structure. In some embodiments, a top surface of the source/drain contact is above a top surface of the metal gate structure. In some embodiments, the source/drain feature is a first source/drain feature and the source/drain contact is a first source/drain contact. The semiconductor structure further includes a second source/drain feature, such that the metal gate structure is disposed between the first and the second source/drain features. In some embodiments, the semiconductor structure further includes a second source/drain contact electrically coupled to the second source/drain feature and having a third portion directly above the second source/drain feature and a fourth portion extending from the third portion along the first direction. The third portion has a third width and the fourth portion has a fourth width less than the third width. In some embodiments, the fourth portion of the second source/drain contact includes a first edge curved inward and a second edge opposite to the first edge and aligned with an edge of the third portion from a top view. In some embodiments, the fourth portion of the second source/drain contact has a depth less than a depth of the third portion of the second source/drain contact and greater than a depth of the second portion of the first source/drain contact.

In another exemplary aspect, the present disclosure is directed to a semiconductor structure including a first and a second source/drain features over a substrate, a first and a second metal gate structures extending lengthwise along a first direction over the substrate and adjacent to the first and the second source/drain features, respectively, and a gate isolation structure extending lengthwise along a second direction substantially perpendicular to the first direction. The first and the second metal gate structures are isolated by the gate isolation structure. The semiconductor structure further includes a source/drain contact including two first portions directly over the first and second source/drain features and a second portion connecting the two first portions. The second portion is adjacent to the gate isolation structure, and the two first portions and the second portion have different widths.

In some embodiments, the second portion of the source/drain contact is embedded in the gate isolation structure. In some embodiments, the second portion of the source/drain contact is directly above a part of the gate isolation structure and in direct contact with a sidewall of the gate isolation structure. In some embodiments, the semiconductor structure further includes an isolation feature disposed between the first and second source/drain features and gate spacers having a first portion on sidewalls of the first and the second metal gate structures and a second portion disposed directly over the isolation feature. The second portion of the source/drain contact is spaced apart from the gate isolation structure by the second portion of the gate spacers. In some embodiments, the semiconductor structure further includes a dielectric layer adjacent to the gate spacers, wherein the source/drain contact is embedded in the dielectric layer. In some embodiments, from a top view, a profile of the source/drain contact resembles a dumbbell shape.

In yet another exemplary aspect, the present disclosure is directed to a semiconductor structure including a substrate and a first and a second active regions over the substrate and in parallel to each other. The first active region includes a first source/drain feature, and the second active region includes a second source/drain feature. The semiconductor structure further includes a metal gate structure extending lengthwise along a first direction, over the first and the second active regions, and adjacent to the first and the second source/drain features. The semiconductor structure further includes a source/drain contact including two first portions directly over the first and the second source/drain features, respectively, and a second portion extending between the two first portions. The two first portions have a first width along a second direction substantially perpendicular to the first direction and the second portion has a second width along the second direction. The first width is greater than the second width.

In some embodiments, the semiconductor structure further includes gate spacers on sidewalls of the metal gate structure and a gate isolation structure extending lengthwise along the second direction and between the first and the second active regions. The gate isolation structure divides the metal gate structure into two isolated portions and includes a dielectric material different from the gate spacers. In some embodiments, the gate isolation structure includes an outer layer and an inner layer embedded in the outer layer. In some embodiments, the semiconductor structure further includes a first and a second gate isolation structures extending lengthwise along the second direction and between the first and the second active regions. The first gate isolation structure divides the metal gate structure into two isolated portions, and the second portion of the source/drain contact is between the first and the second gate isolation structures.