Accelerating Method of Executing Comparison Functions and Accelerating System of Executing Comparison Functions

An accelerating method includes inputting first data and second data, buffering the first data and the second data to at least one memory, acquiring a first address of the first data, acquiring a second address of the second data, generating a code corresponding to the comparison functions, combining the code, the first address, and the second address to form a command signal, transmitting the command signal from an advanced extensible interface to a bus circuit, reading out the first data and the second data from the at least one memory according to the first address and the second address, comparing the first data with the second data by using an accelerator, generating a comparison result of the first data and the second data, and transmitting the comparison result to the advanced extensible interface.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure illustrates an accelerating method and an accelerating system, and more particularly, an accelerating method and an accelerating system of executing comparison functions by introducing additional hardware components.

2. Description of the Prior Art

With the rapid development of science and technology, programming languages and automated processing technologies are adopted in our daily life. The programming languages include library functions. Different library functions can execute different commands. For example, the C language has many functions for comparing strings, such as a strcmp function, a strchr function, a strlen function, and a strstr function.

In order to execute functions (i.e., such as “strchr”, “strlen”, and “strstr”), a compiler can be used for linking these functions with C language library. Then, in the C language library, a processor can read a string of a source address and a string of a destination address. Further, the processor can compare contents of the two strings according to lengths of bytes and words of the two strings.

In aforementioned methods of executing the functions of strcmp, strchr, strlen, and strstr, the long processing time and large transmission bandwidth are required. Therefore, for the processor, the long processing time and large transmission bandwidth occupy a lot of resources of the processor.

SUMMARY OF THE INVENTION

In an embodiment of the present disclosure, an accelerating method of executing comparison functions is disclosed. The accelerating method comprises inputting first data and second data, buffering the first data and the second data to at least one memory, acquiring a first address of the first data, acquiring a second address of the second data, generating a code corresponding to the comparison functions, combining the code, the first address, and the second address to form a command signal, transmitting the command signal from an advanced extensible interface to a bus circuit, reading out the first data and the second data from the at least one memory according to the first address and the second address, comparing the first data with the second data by using an accelerator, generating a comparison result of the first data and the second data, and transmitting the comparison result to the advanced extensible interface.

In another embodiment of the present disclosure, an accelerating system of executing comparison functions is disclosed. The accelerating system comprises a processor, a bus circuit, and at least one memory. The processor comprises an advanced extensible interface and is configured to receive data and generate a command signal. The bus circuit is coupled to the advanced extensible interface and configured to receive the command signal. The at least one memory is coupled to the bus circuit and configured to buffer data. After first data and second data are inputted to the advanced extensible interface, the first data and the second data are buffered to the at least one memory. The processor acquires a first address of the first data and a second address of the second data. The processor generates a code corresponding to the comparison functions, and combines the code, the first address, and the second address to form a command signal. The processor transmits the command signal from the advanced extensible interface to the bus circuit. After the first data and the second data from the at least one memory are read out according to the first address and the second address, an accelerator compares the first data with the second data for generating a comparison result of the first data and the second data. The comparison result is transmitted to the advanced extensible interface.

DETAILED DESCRIPTION

FIG. 1is a block diagram of an accelerating system100of executing comparison functions according to a first embodiment of the present disclosure. Various embodiments are introduced in the accelerating system for accelerating processing speed of comparison functions of the programming language. These embodiments can also simplify commands and mitigate resources occupied in a queue of a processor. Details are illustrated later. The accelerating system100can include a processor10, a bus circuit11, and at least one memory (i.e., such a first memory13and a second memory14). The processor10can include an advanced extensible interface10afor receiving data and generating a command signal. The advanced extensible interface10aincludes a main writing interface10bfor communicating with the bus circuit11. The bus circuit11is coupled to the advanced extensible interface10afor receiving the command signal. The at least one memory is linked to the bus circuit11through a memory controller12for buffering data. For example, the first memory13and the second memory14can be two memory segments partitioned from one memory circuit. Alternatively, the first memory13and the second memory14can be two different circuits. The memory controller12can include an accelerator12a. The first memory13and the second memory14are coupled to the memory controller12. The first data buffered in the first memory13is compared with the second data buffered in the second memory14by using the accelerator12a. Here, the first data and the second data can be any character string data or any digital data. The comparison functions of a program can be string comparison function of C program, such as a strcmp function, a strchr function, a strlen function, and a strstr function.

In the accelerating system100, as previously mentioned, the first data and the second data can be buffered in the first memory13and the second memory14respectively. After the first data and the second data are inputted to the advanced extensible interface10aby the processor10, the processor10can acquire a first address of the first data and a second address of the second data. The processor10can generate a code corresponding to the comparison functions. Then, the processor10can combine the code, the first address, and the second address to form a command signal (i.e., a function command instruction). The processor10transmits the command signal from the advanced extensible interface10ato the bus circuit11. After the first data and the second data from the at least one memory are read out according to the first address and the second address, the accelerator12acan compare the first data with the second data for generating a comparison result of the first data and the second data. Finally, the comparison result of the first data and the second data can be transmitted to the advanced extensible interface10a.

In the accelerating system100, some properties are introduced as follows. Extended instructions of the processor10, logical operations of the extended instructions, extended part of the bus circuit11or the memory controller12, and protocols of the processor10, the bus circuit11, and the memory controller12can be used for collaboratively executing the strcmp function, the strchr function, the strlen function, and the strstr function. Further, for the processor10, commands of the strcmp function, the strchr function, the strlen function, and the strstr function can be extended as specific instructions. When the processor10executes the specific instructions, the processor10can generate command signals to the bus circuit11according to default register configurations. For example, for the advanced extensible interface10a, the processor10can generate the specific instructions for requesting the bus circuit11to executing the strcmp function, the strchr function, the strlen function, and the strstr function. Further, after the bus circuit11or the memory controller12receives a special protocol request, it can cooperatively execute the strcmp function, the strchr function, the strlen function, and the strstr function. Finally, a result value or an interruption notification signal can be returned to the processor10. Therefore, the accelerating system100has the following advantages. First, since additional hardware components (i.e., such as the bus circuit11, the memory controller12, and the accelerator12a) are introduced for assisting the processor10to execute various functions such as the strcmp function, the strchr function, the strlen function, and the strstr function, resource requirements of the processor10can be reduced. Therefore, since more resources of the processor10can be released, the processor10can execute other programs without sacrificing a lot of processing time. Second, since the comparison function corresponds to specific instruction, its command can be simplified. Third, a data accessing path is generated between the memory controller12and at least one memory. Transmissions of returning the result value of the comparison result to the processor10(i.e., the memory controller12to the processor10through the bus circuit11) only require a small bandwidth capacity. Any reasonable technology modification or hardware replacement should be covered by the scope of the present disclosure.

FIG. 2is a block diagram of an accelerating system200of executing comparison functions according to a second embodiment of the present disclosure. In the accelerating system200, the first data is buffered in a third memory15. The second data is buffered in a peripheral device16. Further, the accelerator11ais disposed inside the bus circuit11. The third memory15and the peripheral device16are coupled to the bus circuit11. The accelerator11acan be used for comparing the first data buffered in the third memory15and the second data buffered in the peripheral device16. In the accelerating system200, the bus circuit11can access the second data buffered in the peripheral device16. The bus circuit11can also access the first data buffered in the third memory15through the memory controller12. Therefore, the accelerator11acan be disposed in the bus circuit11for executing various functions such as the strcmp function, the strchr function, the strlen function, and the strstr function. Finally, the result value of the comparison result can be transmitted to the processor10by the bus circuit11. Therefore, the accelerating system200can be regarded as one embodiment with the processor10supported an extended bus protocol. Similarly, the accelerating system200has the following advantages. First, since additional hardware components (i.e., such as the bus circuit11, the memory controller12, and the accelerator11a) are introduced for assisting the processor10to execute various functions such as the strcmp function, the strchr function, the strlen function, and the strstr function, resource requirements of the processor10can be reduced. Therefore, since more resources of the processor10can be released, the processor10can execute other programs without sacrificing a lot of processing time. Second, since the comparison function corresponds to specific instruction, its command can be simplified. Third, a data accessing path is generated between the memory controller12and at least one memory. Transmissions of returning the result value of the comparison result to the processor10(i.e., the bus circuit11to the processor10) only require a small bandwidth capacity. Any reasonable technology modification or hardware replacement should be covered by the scope of the present disclosure.

FIG. 3is a block diagram of an accelerating system300of executing comparison functions according to a third embodiment of the present disclosure. In the accelerating system300, the advanced extensible interface10afurther includes a main reading interface10c. The main reading interface10cin the advanced expandable interface10ais also connected to the bus circuit11. Therefore, the main reading interface10cin the advanced expandable interface10acan also perform bi-directional communications with the bus circuit11. For example, the main reading interface10cin the advanced expandable interface10acan transmit a command signal to the bus circuit11. Further, the bus circuit11may also transmit a comparison result to the processor10. In other words, in the accelerating system300, a write user (awuser) channel can be used for communicating a main writing interface10bin the advanced extensible interface10awith the bus circuit11. A read user (aruser) channel can also be used for communicating a main reading interface10cwith the bus circuit11. Therefore, operating modes of the awuser and the aruser are similar. The advanced extensible interface10acan support both awuser command sets and aruser command sets.

FIG. 4is a block diagram of an accelerating system400of executing comparison functions according to a fourth embodiment of the present disclosure. The accelerating system400can also introduce an internal accelerator10d, a memory mapping unit10e, and a query port P. The processor10can use the internal accelerator10dfor driving the memory mapping unit10efor converting formats of the first address and the second address from two virtual address formats to two physical address formats. The first address and the second address having physical address formats are partitioned into a plurality of pages having fixed bit lengths. For example, the processor10may set 4K bytes as a page length. Pair-wised pages are adjacent. Therefore, if a length of the physical address is not an integer multiple of 4K bytes, the length of the physical address may exceed a certain page boundary. Therefore, memory coordinates of the physical address may be shifted. Therefore, in order to control the bus circuit11or the memory controller12to precisely acquire correct memory coordinates of the two physical addresses, the query port P can be introduced between the bus circuit11and the memory mapping unit10e. Therefore, in the accelerating system400, the processor10can use the query port P for synchronously accessing the first address and the second address having physical address formats generated by the memory mapping unit10eto the bus circuit11. Therefore, the accelerator (not shown) disposed inside the bus circuit11or the accelerator (not shown) disposed inside the memory controller12can acquire the first data and the second data according to the first address and the second address. Subsequent processes are similar to the modes of aforementioned embodiments. Therefore, they are omitted here.

FIG. 5is a block diagram of an accelerating system500of executing comparison functions according to a fifth embodiment of the present disclosure. The accelerating system500is similar to the accelerating system400. A difference is that the memory controller12of the accelerating system500can include a query table12a′. As previously mentioned, The processor10can use the internal accelerator10dfor driving the memory mapping unit10efor converting formats of the first address and the second address from two virtual address formats to two physical address formats. Therefore, in order to control the memory controller12to precisely acquire the correct memory coordinates of the two physical addresses, the query table12a′ can be introduced to the memory controller12. Therefore, the processor10can read the first data and the second data by using the query table12a′ of the memory controller12coupled to or disposed inside the bus circuit11according to the physical address formats of the first address and the second address. Finally, the bus circuit11can transmit the comparison results to the processor10.

In the aforementioned embodiments of the accelerating systems, the bus circuit11or the memory controller12can be used for assisting the processor10to execute functions such as the strcmp function, the strchr function, the strlen function, and the strstr function. In practice, first, the processor10can receive the command and determine if it is a comparison function (i.e., for example, the strcmp function). If the command is not the comparison function, the processor10continuously receives a signal. If the command is the comparison function, the processor10waits for the corresponding write data (i.e., such as string data), or collects all required messages. Then, the processor10can read values of the two strings and compare the two strings (i.e., this step can be completed by an external circuit, such as the accelerator in the bus circuit11or the accelerator in the memory controller12). Finally, after all characters are completely compared, the comparison result can be generated and transmitted to the processor10through the bus circuit11. In other words, since the accelerating system of the present disclosure introduces additional hardware components such as the bus circuit11and/or the memory controller12, the bus circuit11and/or the memory controller12can be used for assisting the processor10for comparing data of two strings. Therefore, the resources occupied in the queue of the processor can be mitigated. The processor10has more resources to execute other programs.

In practical programming operation, for avoiding ambiguity, an embodiment is introduced for executing the strcmp function, as illustrated below. Variables are defined as follows:

rs1: denoted as the address of the first string.
rs2: denoted as the address of the second string.
rs3: denoted as the length of the first string.

When the processor10executes instructions such as the Advanced Reduced Instruction Set Computer-Fifth (RISC-V) architecture, the information of the instructions can be converted into instructions supported by the bus circuit11. For the Advanced Extensible Interface bus, some methods can be used for realizing the architecture. In a first method, when the processor10executes a special instruction, the processor10can generate a write command comprising “awaddr=source address” (i.e., data of rs1, which denotes the address of the first string), “awlen=burst length” (i.e., the length of the first string), and “awsize=1” (byte). At the same time, a command of “awvalid=1” is transmitted to the bus circuit11. A message of data writing channel is also transmitted to the bus circuit11. The message of the data writing channel includes wdata (i.e., data of rs2, which is the address of the second string), wstrb (i.e., masked bits of the byte), and identification code. As in previously embodiments, the write command can also be the read command. The write command can be extended by other signals for transmitting other information, such as the address of the second string. The processor10can control timing of transmitting the write command. For example, when the processor10is used for transmitting the command and the bus circuit11is operated in an idle state, the command can be transmitted from the bus circuit11immediately. Otherwise, the command may be queued until the processor10is available. Further, the processor10can execute other advanced extensible interface instructions without waiting for a return signal of the strcmp command. Moreover, when the writing mode of the advanced and expandable interface is executed, the bus circuit11can return a message of the comparison result to the processor10. After the bus circuit11receives the write command and the write data, two addresses and lengths of the write command and the write data can be stored. The bus circuit11can generate two read commands to a slave device (i.e., for example, the memory controller12). If two character strings do not correspond to the same slave device, the bus circuit11can also sequentially transmit two read commands for generating a comparison result of two data strings.

During a period of executing the strcmp function by the bus circuit11, if the length of the string is greater than a maximum acceptable length, the string can be partitioned into several sub-strings for multiple transmissions. The processor10can record data of the source and destination addresses of each transmission until transmission of all sub-strings is done. In a second method, an extension part of the processor10and an extension part of the advanced extensible interface10aare the same. The slave device (i.e., for example, the memory controller12) can be used for executing the strcmp/strchr/strlen/strstr functions. A limitation of this method is that the data of strcmp/strchr/strlen/strstr functions is located (saved) under one device (i.e., the first memory13and/or the second memory14under the memory controller12). It is assumed that the slave device is the memory controller12. The memory controller12can store two addresses and two lengths after the memory controller12receives special commands and the string data. Then, the memory controller12can issue a read command to at least one memory and compare the two data strings when receiving the two data strings. In a third mode, the processor10is not modified. The bus circuit11or the memory controller12can directly execute the comparison functions. The processor10can set start timing and addresses of comparison operation, and acquire a flag of end timing of the comparison operation. For example, assume that the bus circuit11has a plurality of registers (not shown) for storing data and controlling data. The processor10can set a first register in the bus circuit11pointing to the first address of the first string. The processor10can set a second register in the bus circuit11pointing to the second address of the second string. The processor10can set a length of a third register in the bus circuit11for indicating the lengths of the two strings. However, if the end of the string is determined by the bus circuit11, the third register can be omitted. The processor10can set a fourth register in the bus circuit11as an activation control unit. After the activation control unit of the fourth register is enabled, the processor10can read status information of a fifth register. It is assumed that after the operation of the bus circuit11is completed, a value “1” can be returned to the processor10. After the processor10reads the value “1”, it can determine that the function operation has been completed. In the present disclosure, the comparison functions are string comparison functions executed by C programming language. The command signal can correspond to a processor extension command of the comparison functions. Any reasonable operation or hardware modification should be covered by the scope of the present disclosure.

FIG. 6is a flow chart of performing an accelerating method of executing comparison functions by using the accelerating systems100-500. The accelerating method can include steps S601-S608. Any reasonable technology modification falls into the scope of the present disclosure. Steps S601-S608are illustrated below.Step S601: inputting the first data and the second data;Step S602: buffering the first data and the second data to at least one memory;Step S603: acquiring the first address of the first data;Step S604: acquiring the second address of the second data;Step S605: generating a code corresponding to the comparison functions and combining the code, the first address, and the second address to form the command signal;Step S606: transmitting the command signal from the advanced extensible interface10ato the bus circuit11;Step S607: reading out the first data and the second data from the at least one memory according to the first address and the second address and comparing the first data with the second data by using the accelerator11aor12a;Step S608: generating the comparison result of the first data and the second data and transmitting the comparison result to the advanced extensible interface10a.

Details of steps S601-S608are previously illustrated. Thus, they are omitted here. In the accelerating system of the present disclosure, particular extended instructions of the processor10(i.e., corresponding to the bus circuit11and/or memory controller12) and additional hardware components are introduced. Therefore, when the processor10prepares to perform comparison functions such as the strcmp/strchr/strlen/strstr function, the processor10can use extended instructions to control the bus circuit11and/or the memory controller12for assisting the processor10to process the comparison functions. Therefore, for the processor10, the processing time and resource requirement can be reduced. No additional cache memory of the processor10is required. Therefore, the processor10has more resources to execute other programs.

To sum up, the present disclosure illustrates a method and a system for accelerating the execution of the comparison functions. The system can perform fast and high-efficiency operations of strcmp/strchr/strlen/strstr functions in specific programming languages (i.e., such as C language). Since the system of the present disclosure introduces additional hardware components such as a bus circuit or a memory controller, the hardware components such as the bus circuit or the memory controller can assist the processor for comparing data of two strings. Therefore, the resources occupied in the queue of the processor can be mitigated. The processor has more resources to execute other programs. Further, the system requires only a small amount of bandwidth for performing comparison functions. Therefore, the system of the present disclosure can accelerate execution speed of the comparison functions in conjunction with simplifying instructions and mitigating occupied resources of the processor.