Caterpillar trenches for efficient wafer dicing

A method for fabricating caterpillar trenches for wafer dicing includes forming at least one opening from a top surface of a mask formed on a substrate to a bottom surface of the mask opposite the top surface of the mask. The mask is formed on the substrate to protect an electronics device disposed on the substrate during isotropic etching. The method further includes isotropically etching through the at least one opening to form at least one wafer dicing channel, including isotropically etching a collection of nested trenches from a top surface of the substrate to a bottom surface of the substrate opposite the top surface of the substrate.

BACKGROUND

Technical Field

The present invention generally relates to semiconductor devices, and more particularly to caterpillar trenches for efficient wafer dicing and methods of fabricating the same.

Description of the Related Art

During integrated circuit manufacturing, wafer dicing is a process by which dies are separated from a wafer following wafer processing. A variety of techniques can be used to perform wafer dicing, including but not limited to sawing (e.g., using a dicing saw machine) and laser cutting. Wafer dicing processes are generally automated processes to maintain accuracy and precision. Following the wafer dicing process, individual chips can be used to build devices, such as, e.g., computers.

SUMMARY

In accordance an embodiment of the present invention, a method for fabricating caterpillar trenches for wafer dicing is provided. The method includes forming at least one opening from a top surface of a mask formed on a substrate to a bottom surface of the mask opposite the top surface of the mask. The mask is formed on the substrate to protect an electronics device disposed on the substrate during isotropic etching. The method further includes isotropically etching through the at least one opening to form at least one wafer dicing channel, including isotropically etching a collection of nested trenches from a top surface of the substrate to a bottom surface of the substrate opposite the top surface of the substrate.

In accordance another embodiment of the present invention, a method for fabricating caterpillar trenches for wafer dicing is provided. The method includes forming a mask on a substrate to protect an electronics device disposed on the substrate during isotropic etching, forming at least one opening from a top surface of the mask to a bottom surface of the mask opposite the top surface of the mask, isotropically etching through the at least one opening to form at least one wafer dicing channel, including isotropically etching a collection of nested trenches from a top surface of the substrate to a bottom surface of the substrate opposite the top surface of the substrate.

In accordance with yet another embodiment of the present invention, a semiconductor device including caterpillar trenches for wafer dicing is provided. The device includes a substrate, an electronics device disposed on the substrate, and at least one wafer dicing channel including a collection of nested trenches from a top surface of the substrate to a bottom surface of the substrate opposite the top surface of the substrate.

DETAILED DESCRIPTION

To form optimized and low-cost wafer dicing channels, the embodiments described herein provide for the fabrication of caterpillar trenches for efficient wafer dicing. The embodiments described herein can reduce the amount of space that the wafer dicing channels consume on the wafer. For example, the embodiments described herein can use an isotropic etch process and multiple sidewalls formed from a spacer material, as opposed to an anisotropic etch process such as, e.g., reactive ion-etching (RIE), to form optimized and lower cost dicing channels. The dicing channels formed in accordance with the embodiments described herein can have sub-1 micron (μm) widths, as opposed to conventional dicing channels which can have widths ranging from about 10 μm to 100 μm. Thus, the embodiments described herein can be used to make smaller electronic devices (e.g., computers) with die sizes of, e.g., about 100 μm×100 μm.

Referring now to the drawings in which like numerals represent the same or similar elements and initially toFIG. 1, a cross-sectional view of a semiconductor device100including a substrate102is provided. The substrate102can include any suitable substrate structure, e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc. In one example, the substrate102can include a silicon-containing material. Illustrative examples of Si-containing materials suitable for the substrate102can include, but are not limited to, Si, SiGe, SiGeC, SiC and multi-layers thereof. Although silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, etc.

As further shown inFIG. 1, an electronics device110is disposed on the substrate. In one embodiment, the electronics device110includes a circuit. For example, the electronics device110can include, e.g., an integrated circuit.

Referring toFIG. 2, a mask120is formed on the substrate102and the electronics device110. In one embodiment, the mask120has a thickness of, e.g., about 1 μm. However, in other embodiments, the mask120can be thinner or thicker. The mask120can be patterned using any suitable process in accordance with the embodiment described herein (e.g., lithography). The mask120can include any suitable dielectric material in accordance with the embodiments described herein, such as, e.g., silicon dioxide (SiO2) or a silicon nitride material (e.g., SiN).

As further shown, etching is performed to create openings130-1and130-2through the mask120and up to the substrate102. As shown, the openings130-1and130-2can have a width “X”. In one embodiment, the width “X” is below, e.g., about 1 μm. More specifically, the width “X” can be, e.g., about 0.5 μm.

In one embodiment, the openings130-1and130-2are created using isotropic or non-directional etching. In contrast to anisotropic or directional etch processes, which include etch processes that etch material in a single direction, isotropic etch processes etch material in multiple directions. For example, isotropic etch processes can have the same or similar etch rates for all spatial directions (e.g., lateral and downward etching can take place at the same or similar rate). Isotropic etch processes can include wet isotropic etch processes and dry isotropic etch processes.

In one embodiment, a wet isotropic etch process is used to create the openings130-1and130-2. A wet isotropic etch process is an isotropic etch processes that removes material by using a solvent including one or more liquid chemicals or etchants that react with material subject to removal. For example, the etchants can oxidize the material via a chemical reaction (e.g., a reduction-oxidation (redox) reaction), and the oxidized material can be removed (e.g., dissolved). The etch rate for a wet isotropic etch process can be determined at least in part based on the concentrations of the one or more etchants in the solvent.

Referring toFIG. 3, a trench140-1is formed within the substrate102corresponding to the opening130-1using isotropic etching (e.g., wet isotropic etching). The lateral etching of the isotropic etch process removes material of the substrate102underneath the mask120due to the solvent reacting underneath the mask120, which is referred to as undercutting.

The removal of the material underneath the mask120can create a concave shaped void. It is to be understood and appreciated that due to the location of the trenches140-1and140-2relative to the electronics device110, the amount of undercutting needs to be controlled to prevent damage to the electronics device110. The lateral etch can be, e.g., about 30% for a well-tuned process. The trench140-1can have a depth of, e.g., about 1 μm.

Referring toFIG. 4, a spacer142-1is formed within the trench140-1. The spacer142-1can be formed within the trench140-1by depositing dielectric material along the substrate102within the trench140-1, and etching the lateral surface of the dielectric material corresponding to the opening130-1. For example, an anisotropic etch process can be used to etch the lateral surface of the dielectric material corresponding to the opening130-1. The spacer142-1can have a thickness of, e.g., about 1 nm. The spacer142-1can be formed using any suitable material and process in accordance with the embodiments described herein. For example, the spacer142-1can include, e.g., a hafnium oxide material (e.g., HfO2).

Referring toFIG. 5, a trench150-1is formed within the substrate102underneath the trench140-1using isotropic etching (e.g., wet isotropic etching). Undercutting results from the lateral etching of the isotropic etch process removing material of the substrate102underneath the trench140-1. It is to be understood and appreciated that less care is needed to control the undercutting with respect to the electronics device110, since the trench150-1is located below the electronics device110. The trench150-1can have a depth of, e.g., about 2 μm.

As further shown inFIG. 5, a spacer152-1is formed within the trench150-1. The spacer152-1can be formed within the trench150-1by depositing dielectric material along the substrate102within the trench150-1, and etching the lateral surface of the dielectric material corresponding to the opening130-1. For example, an anisotropic etch process can be used to etch the lateral surface of the dielectric material corresponding to the opening130-1. The spacer152-1can have a thickness of, e.g., about 1 nm. The spacer152-1can be formed using any suitable material in accordance with the embodiments described herein. For example, the spacer152-1can include, e.g., a hafnium oxide material (e.g., HfO2).

Referring toFIG. 6, a trench160-1is formed within the substrate102underneath the trench150-1using isotropic etching (e.g., wet isotropic etching). Undercutting results from the lateral etching of the isotropic etch process removing material of the substrate102underneath the trench150-1. It is to be understood and appreciated that even less care is needed to control the undercutting with respect to the electronics device110, since the trench160-1located even further underneath the electronics device110. The trench160-1can have a depth of, e.g., about 20 μm.

As further shown inFIG. 6, a spacer162-1is formed within the trench160-1. The spacer162-1can be formed within the trench160-1by depositing dielectric material along the substrate102within the trench160-1, and etching the lateral surface of the dielectric material corresponding to the opening130-1. For example, an anisotropic etch process can be used to etch the lateral surface of the dielectric material corresponding to the opening130-1. The spacer162-1can have a thickness of, e.g., about 1 nm. The spacer162-1can be formed using any suitable material in accordance with the embodiments described herein. For example, the spacer162-1can include, e.g., a hafnium oxide material (e.g., HfO2)

Referring toFIG. 7, a trench170-1is formed within the substrate102underneath the trench160-1using isotropic etching (e.g., wet isotropic etching). Undercutting results from the lateral etching of the isotropic etch process removing material of the substrate102underneath the trench160-1. It is to be understood and appreciated that even less care is needed to control the undercutting with respect to the electronics device110, since the trench170-1is located even further underneath the electronics device110. The trench170-1can have a width of, e.g., about 20 μm.

The trench170-1in this illustrative embodiment is the trench of the collection of nested trenches corresponding to the bottom surface of the substrate102. As further shown inFIG. 7, in contrast to the trenches140-1through160-1, the trench170-1lacks a spacer. That is, the final trench in the collection of nested trenches can lack a spacer.

As further shown inFIG. 7, another collection of nested trenches140-2through170-2can be formed through the opening130-2. The trenches140-2through170-2can be formed in a manner similar to that described above with respect to trenches140-1through170-1formed through the opening130-1. Moreover, the trenches140-2through170-2can include properties (e.g., thicknesses) similar to those of trenches140-1through170-2, respectively.

Although the opening130-2is shown in this illustrative embodiment being formed prior to forming the trench140-1through the opening130-1, the opening130-2can be formed at any suitable point within the fabrication process in accordance with the embodiments described herein (e.g., after the formation of the trench170-1). Additionally, although the trenches140-2through170-2are shown in this illustrative embodiment being formed after the formation of the trenches140-1through170-1, the trenches140-2through170-2can be formed at any suitable point within the fabrication process in accordance with the embodiments described herein (e.g., trenches140-2through170-2can be formed concurrently with respective ones of the trenches140-1through170-1).

The formation of the trenches140-1through170-1and140-2through170-2results in the creation of respective dicing channels formed to the bottom surface of the substrate102. That is, as shown inFIGS. 1-7, each of the wafer dicing channels can include respective collections of nested or stacked trenches.

As shown inFIG. 7each of the trenches140-1through170-1and140-2through170-2can have a trapezoidal shaped cross-section. The trapezoidal shaped cross-section can result from the use of isotropic etching to form each of the trenches140-1through170-1and140-2through170-2. Although only four trench formation steps were described in this illustrative embodiment to create the respective dicing channels, the trench formation process can include any number of steps to form any number of trenches suitable for creating dicing channels that are formed to the bottom surface of the substrate102.

As shown inFIG. 7, each of the trenches140-1through170-1and140-2through170-2can be arranged in order of ascending widths. For example, as shown inFIG. 7, trench140-1, which has a top surface corresponding to the top surface of the substrate102has a smaller width than the trench150-1underneath the trench140-1, the trench150-1has a smaller width than the trench160-1located underneath the trench150-1, and the trench160-1has a smaller width than the trench170-1having a bottom surface corresponding to the bottom surface of the substrate102.

Referring toFIG. 8, the mask120is removed (e.g., stripped). Any suitable process can be used to remove (e.g., strip) the mask120in accordance with the embodiments described herein.

Referring toFIG. 9, a device200is shown including a die210formed on a substrate202after dicing is performed in accordance with the embodiments described herein. As shown, the die210has a pyramidal-type shape that can be viewed as a stack of rectangles formed on top of each other in descending size order (e.g., a rectangular pyramidal shape).

Referring toFIG. 10, a device300is shown. The device300can function as a lid for the die, such as the die210shown inFIG. 9. The device300includes an inner portion having the pyramidal-type shape corresponding to the die to improve contact between the chip and the lid for thermal cooling, if needed.

Referring toFIG. 11, a block/flow diagram is shown illustrating a system/method400for fabricating caterpillar trenches for efficient wafer dicing.

At block410, a mask is formed on a substrate to protect an electronics device disposed on the substrate during isotropic etching. The electronics device can include, e.g., a circuit. For example, the electronics device can include, e.g., an integrated circuit.

In one embodiment, the mask has a thickness of, e.g., about 10 μm. However, in other embodiments, the mask can be thinner or thicker. The mask can be patterned using any suitable process(es) in accordance with the embodiment described herein (e.g., lithography). The mask can include any suitable material in accordance with the embodiments described herein. Examples of mask materials include, but are not limited to, SiO2, a silicon nitride material (e.g., SiN), photosensitive organic film dielectric materials, etc.

At block420, at least one opening is formed from a top surface of the mask to a bottom surface of the mask opposite the top surface of the mask. The at least one opening can have a width below, e.g., about 1 μm. More specifically, the width of the at least one opening can be, e.g., about 0.5 μm.

In one embodiment, the at least one opening is created using isotropic or non-directional etching. In contrast to anisotropic or directional etching, which can include etch processes that etch material in a single direction, isotropic etch processes can etch material in multiple directions. For example, isotropic etch processes can have the same or similar etch rates for all spatial directions (e.g., lateral and downward etching can take place at the same or similar rate). Isotropic etch processes can include wet isotropic etch processes and dry isotropic etch processes.

A wet isotropic etch process is an isotropic etch processes that removes material by using a solvent including one or more liquid chemicals or etchants that react with material subject to removal. For example, the etchants can oxidize the material, and the oxidized material can be removed (e.g., dissolved). The etch rate for a wet isotropic etch process can be determined based on the concentrations of the etchants in the solvent.

At block430, at least one wafer dicing channel including a collection of nested trenches is formed from a top surface of the substrate to a bottom surface of the substrate opposite the top surface of the substrate.

Forming the at least one wafer dicing channel includes isotropically etching through the at least one opening. Isotropically etching through the at least one opening to form the at least one wafer dicing channel includes isotropically etching a collection of nested trenches from a top surface of the substrate to a bottom surface of the substrate opposite the top surface of the substrate. The collection of nested trenches can include any suitable number of trenches so that the at least one wafer dicing channel is formed to the bottom surface of the substrate.

The lateral etching of the isotropic etch process removes material of the substrate underneath the mask due to the solvent reacting underneath the mask, resulting in undercutting that creates a concave shaped void. It is to be appreciated that the amount of undercutting needs to be controlled to prevent damage to the electronics device.

Isotropically etching through the at least one opening to form the at least one wafer dicing channel can include isotropically etching each trench of the collection of nested trenches such that each trench has a respective width. In one embodiment, the trenches of the collection of nested trenches can be arranged in order of ascending widths. For example, in an illustrative example in which the collection of nested trenches includes four trenches, a first trench having a top surface corresponding to the top surface of the substrate can have a smaller width than a second trench located underneath the first trench, the second trench can have a smaller width than a third trench located underneath the second trench, and the third trench can have a smaller width than a fourth trench having a bottom surface corresponding to the bottom surface of the substrate.

It is to be understood and appreciated that the etch rate and/or etch chemistry used to form the collection of nested trenches can be controlled to achieve a suitable or desired wafer dicing channel shape or geometry. As described above with reference toFIGS. 1-8, isotropically etching the collection of nested trenches can include isotropically etching each trench of the collection of nested trenches to have a trapezoidal shaped cross-section. Such a shape or geometry of the corresponding wafer dicing channel can correspond to a device having a pyramidal-type shape (e.g., rectangular pyramidal shape), as described above with reference toFIG. 9.

In one embodiment, forming the at least one wafer dicing channel can further include forming a spacer along sidewalls of at least one of the trenches in the collection of nested trenches. For example, forming the spacer can include depositing dielectric material along the substrate within the at least one trench, and etching a lateral surface of the dielectric material corresponding to the at least one opening (e.g., using anisotropic etching). The spacer can be formed using any suitable material and process in accordance with the embodiments described herein. For example, the spacer can include a hafnium oxide material (e.g., HfO2). The trench in the collection of nested trenches corresponding to the bottom surface of the substrate (e.g., the final trench of the collection of nested trenches) can lack a spacer.

At block440, the mask is removed after creating the at least one wafer dicing channel. In one embodiment, removing the mask after creating the at least one wafer dicing channel includes stripping the mask. Any suitable technique can be used to remove the mask in accordance with the embodiments described herein.

The illustrative embodiments described above with reference toFIGS. 1-11allow for the fabrication of caterpillar trenches that form optimized and low-cost dicing channels, thereby increasing efficiency of wafer dicing. The embodiments described herein can reduce the amount of space that the dicing channels consume on the wafer. For example, the embodiments described herein can use an isotropic etch process and multiple sidewalls, as opposed to an anisotropic etch process such as, e.g., RIE, to form optimized and lower cost dicing channels. The dicing channels formed in accordance with the embodiments described herein can have sub-1 μm widths, as opposed to conventional dicing channels which can have widths ranging from about 10 μm to 100 μm. Thus, the embodiments described herein can be used to make smaller electronic devices (e.g., computers) with die sizes of, e.g., about 100 μm×100 μm.