Multi-gate VDMOS transistor and method for forming the same

Various embodiments provide multi-gate VDMOS transistors. The transistor can include a substrate having a first surface and a second surface opposite to the first surface, a drift layer on the first surface of the substrate, and an epitaxial layer on the drift layer. The transistor can further include a plurality of trenches. Each trench can pass through the epitaxial layer and a thickness portion of the drift layer. The transistor can further include a plurality of gate structures. Each gate structure can fill the each trench. The transistor can further include a plurality of doped regions in the epitaxial layer. Each doped region can surround a sidewall of the each gate structure. The transistor can further include a source metal layer on the epitaxial layer to electrically connecting the plurality of doped regions, and a drain metal layer on the second surface of the substrate.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. CN201310342027.4, filed on Aug. 7, 2013, the entire contents of which are incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure relates to the field of semiconductor fabrication and, more particularly, relates to multi-gate VDMOS transistors and methods for forming the same.

BACKGROUND

With growing demand for consumer electronics products, there is an increasingly great demand for power metal-oxide-semiconductor field effect transistors (MOSFETs). Power MOSFETs include two main types, i.e., vertical double-diffused MOSFET (VDMOS) and lateral double-diffused MOSFET (LDMOS). Among the two types, the trench VDMOS transistor (or Trench Vertical MOS) has advantages such as high degree of device integration, low on-resistance, lower gate-drain charge density, and high current capacity. Thus, the trench VDMOS transistor has lower switching loss and fast switching speed, and is widely used in the field of power devices.

However, using current fabrication processes, the drive current of the existing VDMOS transistor is still relatively small. The disclosed methods and devices are directed to solve one or more problems set forth above and other problems.

BRIEF SUMMARY OF THE DISCLOSURE

One aspect of the present disclosure includes a multi-gate vertical double-diffused metal-oxide-semiconductor (VDMOS) transistor. The transistor can include a substrate having a first surface and a second surface opposite to the first surface, a drift layer on the first surface of the substrate, and an epitaxial layer on the drift layer. The transistor can further include a plurality of trenches, each trench of the plurality of trenches can pass through the epitaxial layer and a thickness portion of the drift layer. The transistor can further include a plurality of gate structures. Each gate structure of the plurality of gate structures can fill the each trench. The transistor can further include a plurality of doped regions in the epitaxial layer. Each doped region of the plurality of doped regions can surround a sidewall of the each gate structure. The transistor can further include a source metal layer on the epitaxial layer, the source metal layer electrically connecting the plurality of doped regions, and the transistor can further include a drain metal layer on the second surface of the substrate.

Another aspect of the present disclosure includes a method for forming a multi-gate VDMOS transistor. In an exemplary method, a substrate can be provided, the substrate having a first surface and a second surface opposite to the first surface. A drift layer can be formed on the first surface of the substrate. An epitaxial layer can be formed on the drift layer. The epitaxial layer and a thickness portion of the drift layer can be etched to form a plurality of trenches. A plurality of gate structures can be formed, each gate structure of the plurality of gate structures filling each trench of the plurality of trenches. A plurality of doped regions can be formed in the epitaxial layer, each doped region of the plurality of doped regions surrounding a sidewall of the each gate structure. A source metal layer can be formed on the epitaxial layer, the source metal layer electrically connecting the plurality of doped regions. A drain metal layer can be formed on the second surface of the substrate.

DETAILED DESCRIPTION

During operation of a VDMOS transistor, operating voltages can be respectively applied to a gate and a drain of the VDMOS transistor and a source can be grounded. A conduction channel can be formed in an epitaxial layer near a sidewall of the gate. A source-drain current (drive current) can flow from the drain to the source via the conduction channel. Therefore, when certain operating voltages are respectively applied to the gate and the drain, the number and width of the conduction channel(s) are fixed. The drive current passing through the conduction channel is thus limited. As a result, the source-drain current (drive current) of the VDMOS transistor is relatively small.

Various embodiments provide a multi-gate VDMOS transistor. The multi-gate VDMOS transistor can have a plurality of gates. Each gate can correspondingly generate a conduction channel in the epitaxial layer. The number of the conduction channels can be equal to the number of the gates. Thus, the number of the conduction channels can be greater. During operation of the VDMOS transistor, the number of paths that a drive current flows through can be increased. Therefore, when certain operating voltages are respectively applied to the gate and the drain, the drive current can be increased.

FIG. 1depicts a cross-sectional view of an exemplary VDMOS transistor in accordance with various disclosed embodiments. For example, the VDMOS transistor can include an N-type substrate201. The N-type substrate201can have a first surface and a second surface opposite to the first surface. The VDMOS transistor can include an N-type drift layer202on the first surface of the N-type substrate201, a P-type epitaxial layer203on the N-type drift layer202, and a plurality of trenches passing through the P-type epitaxial layer203and a thickness portion of the N-type drift layer202. A plurality of gate structures207can fill the plurality of trenches, respectively (i.e., a gate structure207can fill a trench). A thickness portion of a layer, as used herein, e.g., in ‘a thickness portion of the N-type drift layer’, can refer to a portion of the layer that has a thickness less than the total thickness of the layer.

The VDMOS transistor can further include an N-type doped region208that is located in the P-type epitaxial layer203and surrounds sidewall(s) of each gate structure207. The VDMOS transistor can further include a source metal layer210on the P-type epitaxial layer203, the source metal layer210electrically connecting the plurality of N-type doped regions208together. The VDMOS transistor can further include a drain metal layer211disposed on the second surface of the N-type substrate201.

For example, the N-type substrate201can be a portion of a drain of the VDMOS transistor. The N-type substrate201can be made of a material including silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), and/or any other suitable semiconductor materials. In one embodiment, the N-type substrate201can be made of a material including silicon.

The N-type substrate201can be doped with N-type impurity ions. For example, the N-type impurity ions can include one or more of phosphorus ions, arsenic ions, antimony ions, and any other suitable ions.

The N-type substrate201can have the N-type drift layer202thereon. The N-type drift layer202can be formed by an epitaxial process. The N-type substrate201and the N-type drift layer202can be made of the same material or different materials. In one embodiment, the N-type drift layer202can be made of a material including silicon.

In other embodiments, the N-type drift layer202can be made of a semiconductor material having a stress. For example, the N-type drift layer202can be made of a material including silicon carbide. When the P-type epitaxial layer203is formed on the N-type drift layer202, a tensile stress can be generated at an interface between the N-type drift layer202and the P-type epitaxial layer203, and mobility of carriers (or charge carriers) in a channel region formed in the P-type epitaxial layer203can thus be increased. In addition, a tensile stress can be generated at an interface between the N-type drift layer202and the N-type substrate201, and mobility of carriers (or charge carriers) transported from the N-type drift layer202to the N-type substrate201can be increased. As a result, performance of the VDMOS device can be improved.

The N-type drift layer202can be doped with N-type impurity ions. A concentration of impurity ions doped in the N-type drift layer202can be smaller than a concentration of impurity ions doped in the N-type substrate201. For example, the concentration of the impurity ions doped in the N-type drift layer202can range from about 1E16 atom/cm3to about 1E19 atom/cm3. The concentration of the impurity ions doped in the N-type substrate201can range from about 1E18 atom/cm3to about 1E21 atom/cm3. The concentration of the impurity ions doped in the N-type substrate201and the concentration of the impurity ions doped the N-type drift layer202can be adjusted according to actual needs, without limitation.

The N-type drift layer202can have the P-type epitaxial layer203thereon. The P-type epitaxial layer203can be used for forming a conduction channel. The P-type epitaxial layer can be doped with P-type impurity ions. The P-type impurity ions can include one or more of boron ions, gallium ions, indium ions, and any other suitable ions. The P-type epitaxial layer203can be formed by an epitaxial process. The P-type epitaxial layer203and the N-type substrate201can be made of the same material or different materials. In one embodiment, the P-type epitaxial layer203can be made of a material including silicon.

A plurality of trenches can be formed in the P-type epitaxial layer203and a thickness portion of the N-type drift layer202. The plurality of trenches can pass through the thickness of the P-type epitaxial layer203and a thickness portion of the N-type drift layer202(i.e., a depth portion of each trench of the plurality of trenches can be located in the N-type drift layer202).

Each trench can be used for forming therein a gate structure207of the VDMOS transistor. The gate structure207can include a gate dielectric layer206on sidewall(s) and bottom of the trench and a gate electrode205that is located on the gate dielectric layer206and fills the trench.

In one embodiment, the gate dielectric layer206can be made of a material including silicon oxide. The gate electrode205can be made of a material including polysilicon. In other embodiments, the gate dielectric layer206can be made of a high dielectric constant material including, e.g., one or more of HfO2, Al2O3, ZrO2, HfSiO, HfSiON, HfTaO, HfZrO, and any other suitable materials. The gate electrode205can be made of a metal (or a metallic material) including, e.g., one or more of W, Al, Cu, Ti, Ta, Co, TaN, NiSi, CoSi, TiN, TiAl, TaSiN, and any other suitable materials.

The number of trenches can be greater than or equal to two. Correspondingly, the number of gate structures207can also be greater than or equal to two. For illustrative purposes, in one embodiment, the plurality of gate structures207can include two gate structures207.

Thus, during the operation of the multi-gate VDMOS transistor in accordance with various disclosed embodiments, because of the plurality of gate structures207, a plurality of conduction channels can be formed in the P-type epitaxial layer203, such that the number of paths that the source-drain current (i.e., the drive current) pass through can be increased. In various embodiments, a path can be formed by (i.e., formed in) the N-type doped region208, the conduction channel in the P-type epitaxial layer203, the N-type drift layer202, and the N-type substrate201. As a result, when certain operating voltages are respectively applied to the gate and the drain, the source-drain current (i.e., the drive current) can be increased.

In order to improve degree of integration of the VDMOS transistor and distribution uniformity of the source-drain current, a distance between adjacent gates207(i.e., gate structures207) can be substantially the same. In addition, the distance between adjacent gate structures207, and a width of each gate structure207can be small. For example, in some embodiments, a distance between adjacent gate structures207can range from about 0.1 micron to about 10 microns. The width of the each gate structure207can range from about 0.1 micron to about 10 microns. In other embodiments, the distance between adjacent gate structures207, and the width of the each gate structure207can be adjusted according to needs of actual applications, without limitation.

When the number of the gate structures207is greater than or equal to three, the gate structure207can have various arrangements to improve uniformity and magnitude of the source-drain current. The various arrangements are depicted in subsequent sections in the present disclosure.

Still referring toFIG. 1, the P-type epitaxial layer203can have a plurality of N-type doped regions208therein. Each N-type doped region208can surround sidewall(s) of a respective (i.e., corresponding) gate structure207. The plurality of N-type doped regions208can be electrically connected together via the source metal layer210to form the source of the VDMOS transistor.

In some embodiments, an N-type doped region208can surround (i.e., enclose) a gate structure207, respectively. In this case, a cross section (e.g. a cross section parallel to the surface of the N-type substrate201) of the N-type doped region208can have a ring shape (e.g., as shown inFIGS. 3-4).

In other embodiments, e.g., as shown inFIG. 2, each N-type doped region208can surround a half of a gate structure207(i.e., a half of sidewall(s) of a gate structure207). The half of the sidewall(s) of the gate structures207surrounded by the N-type doped region208can be adjacent sidewall(s) of two gate structures207. That is, the half of the sidewall(s) of each gate structure207closest to (i.e., adjacent to) another gate structure207can be surrounded by the N-type doped region208. Such an arrangement can reduce area occupied by a multi-gate VDMOS transistor, and improve the degree of integration of the device.

Still referring toFIG. 1, the N-type doped regions208corresponding to adjacent gate structures207(i.e., adjacent N-type doped regions208) are not in contact with each other in the P-type epitaxial layer203. That is, a region between adjacent N-type doped regions208can still be a portion of the P-type epitaxial layer203. Thus, the source metal layer210can be in contact (or in direct contact) with the P-type epitaxial layer203, i.e., the P-type epitaxial layer203between the adjacent N-type doped regions208.

During the operation the VDMOS transistor, an operating voltage can be applied to the gate structure207(or the gate electrode205). The source metal layer210can be grounded (or connected to a negative voltage), and the P-type epitaxial layer203is accordingly directly grounded. Thus, there can be a great electrical potential difference between the gate electrode205and the source metal layer210. As a result, holes in the P-type epitaxial layer203can be more easily repelled toward an interface between the P-type epitaxial layer203and the source metal layer210. Electrons in the P-type epitaxial layer203can be more easily attracted toward near the gate dielectric layer206. Therefore, the conduction channel formed in the P-type epitaxial layer203can be substantially wide. When the conduction channel have a greater width, the source-drain current passing through the conduction channel can be greater.

Further, during the operation the VDMOS transistor, operating voltage(s) can simultaneously be applied to the plurality of gate structures207. An equivalent electrical potential difference within the P-type epitaxial layer203between adjacent gate structures207can be increased. Thus, the width of the conduction channel(s) formed in the P-type epitaxial layer203between the adjacent gate structures207can be increased.

The P-type epitaxial layer203can have the source metal layer210thereon. The source metal layer210can electrically connect together the plurality of N-type doped regions208, such that the plurality of N-type doped regions208can have the same electrical potential. The plurality of N-type doped regions208can be electrically connected together to form the source (or the source region) of the VDMOS (or DMOS) device.

Optionally, an isolation dielectric layer209can be formed between the source metal layer and the gate structure207. The isolation dielectric layer209can be used for isolating the gate structure207and the source metal layer210. The isolation dielectric layer209can cover a surface of the gate dielectric layer206and the gate electrode205. Optionally, the isolation dielectric layer209can further cover a portion of a surface of the N-type doped region208.

In order to ensure effective isolation performance, the isolation dielectric layer209can have a dielectric constant greater than about 2.5, and a thickness greater than about 500 angstroms. The Isolation dielectric layer209can be made of a material including one or more of SiO2, SiN, SiON, SiCN, SiC, and any other suitable materials. The isolation dielectric layer209can include a single-layer, or a multi-layer stacking structure.

FIG. 12depicts cross-sectional views of another exemplary VDMOS transistor in accordance with various disclosed embodiments. As shown inFIG. 12, a multi-gate VDMOS transistor can further include opening(s) in the source metal layer210to expose the surface of the isolation dielectric layer209. In addition, an interlayer dielectric layer220can be disposed on the source metal layer210. The interlayer dielectric layer220can fill the opening(s). A plurality of through holes can be formed in the interlayer dielectric layer220and the isolation dielectric layer209to respectively expose the surface of the plurality of gate electrodes205. The plurality of through holes can be filled with a conductive material to form a plurality of conductive plugs224. A gate metal layer222can be disposed on the interlayer dielectric layer220. The gate metal layer222can electrically connect together the plurality of conductive plugs224, to thus electrically connect together the plurality of gate electrodes205. The plurality of gate electrodes205that are electrically connected together can form a gate electrode (or gate) of the VDMOS transistor.

When the number of the gate structures207is greater than or equal to three, the gate structure207can have various different arrangements. For example, an arrangement of the gate structures207in the P-type epitaxial layer203and the thickness portion of the N-type drift layer202can have a linear (i.e. straight line) shape, a polygonal shape, a honeycomb (i.e., honeycomb-type) shape, a concentric circular shape, an array shape, and/or an irregular shape.

When the arrangement of the gate structures207has a shape other than the straight line shape, i.e., including, e.g., a polygonal shape, a honeycomb shape, a concentric circular shape, an array shape, and/or an irregular shape, a gate structure207can be adjacent to at least two gate structures207(i.e. two other gate structures207) according to the spatial arrangement. And there can be a common region (of the P-type epitaxial layer203) between the multiple adjacent gate structures207. When operating voltage(s) are applied to the gate structures207, an electrical potential difference within the common region (i.e., of the P-type epitaxial layer203) between the multiple adjacent gate structures207can be increased (e.g., because multiple operating voltages can be superposed on and interact with each other in the common region). Therefore, a width of the conduction channel formed in the common region can be increased, and the source-drain current (i.e., the drive current) passing through the conduction channel can be increased accordingly.

FIGS. 3-4depict arrangements of multi-gate structures in accordance with various disclosed embodiments. For example,FIG. 3depicts arrangements of three gate structures207in accordance with various disclosed embodiments.FIG. 4depicts arrangements of four gate structures207in accordance with various disclosed embodiments.

Referring toFIG. 3, in some embodiments, an arrangement of the three gate structures207in the P-type epitaxial layer203and the thickness portion of the N-type drift layer202can have a linear shape. That is, line(s) connecting centers of the gate structures207can form a straight line. A distance between every two adjacent gate structures207can be substantially equal (i.e., the gate structures207can be equally spaced along the straight line). Thus, effect of adjacent gate structures207on forming the conduction channel can be the same, and uniformity of the source-drain current passing through each conduction channel can be improved. In other embodiments, the distance between every two adjacent gate structures207can be unequal.

In some embodiments, the arrangement of three gate structures207can have an equilateral triangular shape. That is, lines connecting centers of the gate structures207can form an equilateral triangle. In comparison with the arrangement having a linear shape, in the arrangement having an equilateral triangular shape, each gate structure207can be adjacent to other two gate structures207. When the operating voltage(s) are applied to the gate structures207, the electrical potential difference in the common region (i.e., the P-type epitaxial layer203) between the three adjacent gate structures207can be increased (e.g., because multiple operating voltages can be superposed on and interact with each other in the common region), such that the width of the conduction channel(s) formed in the common region can be increased, and thus the source-drain current (i.e., the drive current) passing through the conduction channel can be increased accordingly. In other embodiments, an arrangement of three gate structures207can have a non-equilateral triangular shape.

Referring toFIG. 4, an arrangement of four gate structures207in the P-type epitaxial layer203and the thickness portion of the N-type drift layer202can have a parallelogram shape or a square shape. In other embodiments, the arrangement of the four gate structures207can have other quadrilateral shapes including, e.g., a rectangular shape, a trapezoidal shape, a kite shape, and/or an unequal quadrilateral shape (or a trapezium shape, or an irregular quadrilateral shape, or a quadrilateral shape having no equal sides).

Further, in other embodiments, the arrangement of the four gate structures207can have a linear shape, a triangular shape. For example, when the arrangement of the four gate structures207has a triangular shape, three gate structures207can be three vertices of a triangle, and the other gate structure207can be located in the triangle, e.g., at the center of the triangle.

In addition, although an N-type substrate is used in the above description, a P-type or any appropriate type of substrate can be used. Although an N-type drift layer is used in the above description, a P-type or any appropriate type of drift layer can be used. Although a P-type epitaxial layer is used in the above description, an N-type or any appropriate type of epitaxial layer can be used. Although an N-type doped region is used in the above description, a P-type or any appropriate type of doped region can be used.

Various embodiments also provide methods for forming a multi-gate VDMOS transistor as disclosed above.FIG. 11depicts a flow diagram of an exemplary method for forming a VDMOS transistor in accordance with various disclosed embodiments.FIGS. 5-10depict cross-sectional views of the VDMOS transistor at various stages during its formation in accordance with various disclosed embodiments. Note that althoughFIGS. 5-10depict structures corresponding to the method depicted inFIG. 11, the structures and the method are not limited to one another in any manner.

In Step S101ofFIG. 11and referring toFIG. 5, an N-type substrate201is provided for illustrative purposes (other type substrate may also be used). The N-type substrate201has a first surface and a second surface opposite to the first surface. An N-type drift layer202can be formed on the first surface of the N-type substrate201. A P-type epitaxial layer203can be formed on the N-type drift layer202.

The N-type drift layer202can be formed by an epitaxial process. In some embodiments, during the epitaxial process, the N-type drift layer202can be in-situ doped with N-type impurity ions. In other embodiments, the N-type drift layer202can be doped with N-type impurity ions by an ion implantation process. The N-type impurity ions doped in the N-type drift layer202can have a concentration less than the concentration of impurity ions doped in the N-type substrate201.

The P-type epitaxial layer203can be formed by an epitaxial process. In some embodiments, during the epitaxial process, the P-type epitaxial layer203can be in-situ doped with P-type impurity ions. In other embodiments, the P-type epitaxial layer203can be doped with P-type impurity ions by an ion implantation process.

The P-type epitaxial layer203can have a thickness ranging from about 0.1 micron to about 10 microns. In one embodiment, the N-type substrate201, the N-type drift layer202and the P-type epitaxial layer203can be made of a material including silicon.

In Step S102ofFIG. 11and referring toFIG. 6, the P-type epitaxial layer203and a thickness portion of the N-type drift layer202are etched to form a plurality of trenches204. The trenches204can pass through the thickness of the P-type epitaxial layer203and can be located inside the N-type drift layer202.

Before etching the P-type epitaxial layer203and the thickness portion of the N-type drift layer202, a mask layer can be formed on the P-type epitaxial layer203. The mask layer can have openings to expose a surface of the P-type epitaxial layer203. The positions of the openings can correspond to the positions of the formed trenches204.

A process of etching the P-type epitaxial layer203and the thickness portion of the N-type drift layer202can include a plasma etching process. The plasma etching process can use a chlorine-containing gas, a bromine-containing gas, or a mixture gas thereof.

In Step S103ofFIG. 11and referring toFIG. 7, a plurality of gate structures207are formed in the plurality of trenches204(as shown inFIG. 6). Each gate structure207can include a gate dielectric layer206on sidewall(s) and bottom of the trench204and a gate electrode205located on the gate dielectric layer206and filling the trench204.

For example, a process of forming the gate structure207can include the following steps. A gate dielectric material layer can be formed on the sidewall(s) and the bottom of the trench204and on the P-type epitaxial layer203. A gate electrode material layer can be formed on the surface of the gate dielectric material layer. The gate dielectric material layer and the gate electrode material layer can be chemical mechanical polished using the P-type epitaxial layer203as a polishing stop layer, to form the gate dielectric layer203and the gate electrode205.

The number of the gate structures207can be greater than or equal to two. The number of the trenches204can be equal to the number of the gate structures207. When the number of the gate structures207is greater than or equal to three, an arrangement of the gate structures207in the P-type epitaxial layer203and the thickness portion of the N-type drift layer202can have a linear (i.e. straight line) shape, a polygonal shape, a honeycomb shape, a concentric circular shape, an array shape, and/or an irregular shape. Optionally, a distance between every two adjacent gate structures207can be substantially equal.

In Step S104ofFIG. 11and referring toFIG. 8, an N-type doped region208is formed in the P-type epitaxial layer203to surround sidewall(s) of each gate structure207. For example, a process of forming the N-type doped regions208can include an ion implantation process. In various embodiments, adjacent N-type doped regions208do not contact each other, i.e., are not in contact with each other.

Before the ion implantation process, a protective mask can be formed on the P-type epitaxial layer203and the gate structures207. The protective mask can have opening(s) to expose region(s) of the P-type epitaxial layer203to be implanted.

In Step S105ofFIG. 11and referring toFIG. 9, an isolation dielectric layer209is formed on the gate structures207. The isolation dielectric layer209can be used for electrically isolating a subsequently-formed source metal layer and the gate structures207. The isolation dielectric layer209can be made of a material including one or more of SiO2, SiN, SiON, SiCN, SiC, and any other suitable materials.

In Step S106ofFIG. 11and referring toFIG. 10, a source metal layer210is formed on the P-type epitaxial layer203and the isolation dielectric layer209. The source metal layer210can electrically connect together the plurality of N-type doped regions208. The plurality of N-type doped regions208that are electrically connected together can form the source (or the source region) of the VDMOS (or DMOS) transistor. A drain metal layer211can be formed on the second surface of the N-type substrate201.

The source metal layer210and the drain metal layer211can be made of a material including Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and/or Wsi. A process of forming the source metal layer210and the drain metal layer211can include a physical vapor deposition process and/or an electroplating process.

Referring toFIG. 12, optionally and/or additionally, a method for forming a multi-gate VDMOS transistor can further include the following steps. The source metal layer210can be etched to form opening(s) to expose the surface of the isolation dielectric layer209. An interlayer dielectric layer220can be formed on the source metal layer210to fill the openings. A plurality of through holes can be formed in the interlayer dielectric layer220and the isolation dielectric layer209to respectively expose the surface of the plurality of gate electrodes205. The plurality of through holes can be filled with a conductive material to form a plurality of conductive plugs224. A gate metal layer222can be disposed on the interlayer dielectric layer220. The gate metal layer222can electrically connect together the plurality of conductive plugs224, to thus electrically connect together the plurality of gate electrodes205. The plurality of gate electrodes205that are electrically connected together can form a gate electrode (or gate) of the VDMOS transistor.

Therefore, a VDMOS transistor can be formed accordingly. The VDMOS transistor can have multiple gates (i.e., multiple gate structures). The multiple gate structures can enhance carrier mobility in an conduction channel by changing original surface channel to body channel to avoid surface roughness scattering. Total size of the gate can remain constant. The multiple gate structure can be equivalent to decreasing the gate pitch, which can improve breakdown voltage. In addition, the improved carrier mobility implies that a lightly doped p-region can be applied to increase voltage blocking capability.

Optionally, the disclosed VDMOS transistor can have two gate structures. In one embodiment, the disclosed VDMOS transistor can have a structure as shown inFIG. 2. An N-type doped region208can surround a half of a gate structure207(i.e., a half of sidewall(s) of a gate structure207). In another embodiment, the disclosed VDMOS transistor can have a structure as shown inFIG. 1. An N-type doped region208can surround a gate structure207(e.g., surround the entire gate structure207).

Optionally, the disclosed VDMOS transistor can have three or more gate structures. In one embodiment, the VDMOS transistor as shown inFIG. 2can have a third gate structure between the two gate structures.

Optionally, the gate structures can be arranged or placed at edges, center, or anywhere of the VDMOS transistor along the surface of the VDMOS transistor (e.g., along the surface of the P-type epitaxial layer203as shown inFIG. 1or2).