Built-in self-test circuit for voltage controlled oscillators

A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

BACKGROUND

In radio frequency circuits, such as a receiver or transceiver, a voltage controlled oscillator (VCO) is used as a frequency synthesizer to down-convert or up-convert a radio frequency signal. A VCO may comprise an oscillator designed to be controlled in frequency by a received voltage generated by a VCO control system formed by a frequency divider, a frequency and phase detector, a charge pump and a low pass filter. In the VCO control system, the output of the frequency divider is compared with a reference signal at the frequency and phase detector. The output of the frequency and phase detector is coupled to the low pass filter and further coupled to the oscillator. As a result, the oscillator generates a desired signal in response to the voltage from the low pass filter.

During the process of fabricating semiconductor chips, a plurality of VCO circuits may be built on a wafer. In order to detect defective voltage controlled oscillators of a wafer, various testing circuits are employed to test voltage controlled oscillators during different phases of fabricating semiconductor devices. There are two major types: semiconductor testing performed at wafer level and semiconductor testing performed at packaging level. An advantageous feature of wafer level testing is that wafer level product testing helps to reduce the cost of package and improve the yield.

Wafer level testing can be done by either using a probe card or built-in self-test circuits. A probe card may comprise a variety of probes. Each of the variety of probes may be coupled to a testing pad on a wafer to be tested. The probe card generates a testing signal and reads the testing results from the probes coupled to the testing pads on the wafer. If one circuit block on the wafer does not work or its result is out of the limit to which the circuit block is specified, the probe card can find the failure through the result from the probe coupled to the defective circuit block. By employing the probe card, defective circuit blocks can be found so that they are screened out before the wafer is sent to the next stage of a semiconductor fabrication process. As a result, the cost for packaging defective chips will be saved.

Built-in self-test circuits may be placed at regions wherein scribe lines are drawn. While conventional built-in self-test circuits may only test open-circuit, short-circuit and dc characteristics of an active device, conventional built-in self-test circuits may be not sufficient for evaluating a VCO because the ac characteristics of a VCO is a key factor to decide whether the radio frequency performance of the VCO is within the limit to which the VCO is specified. As a result, despite passing wafer level testing of open-circuit, short-circuit and dc characteristics, some VCO circuits may still fail to pass the final packaged chip test.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to preferred embodiments in a specific context, a single transistor based peak detector converting the amplitude of an ac signal from a cross-coupled voltage controlled oscillator into a dc value. The invention may also be applied, however, to converting an ac signal's amplitude into a dc value by means of various peak detector topologies.

Referring initially toFIG. 1, a block diagram of a built-in self-test circuit for testing a voltage controlled oscillator (VCO) is illustrated in accordance with an embodiment. In a wafer, there may be a plurality of VCO circuits such as VCO102illustrated inFIG. 1. In order to test the ac characteristics of the VCO102, a radio frequency (RF) peak detector106is built, preferably in the same wafer, and coupled to the output of the VCO102via a buffer104. The RF peak detector106is configured such that: when the VCO102generates an ac signal, the RF peak detector106detects the amplitude of the ac signal and generates a dc output proportional to the amplitude of the ac signal. The detailed operation of the RF peak detector106will be described below with respect toFIG. 2. On the other hand, when the VCO102fails to generate an ac signal, the output of the RF peak detector106is at zero volts. An advantageous feature of having an on-chip self-test RF peak detector is that the failed VCO can be identified before packaging so as to reduce unnecessary time and cost in the subsequent steps of a semiconductor fabrication process.

FIG. 2illustrates in detail a schematic diagram of the built-in self test circuit shown inFIG. 1. In accordance with an embodiment, a cross-coupled VCO is used to illustrate the inventive aspects of the various embodiments. The cross-coupled VCO102comprises a first inductor LP1, a second inductor LP2, a capacitor CP, a pair of n-channel metal oxide semiconductor (NMOS) transistors M1and M2and a bias current source Ibias. Both the first inductor LP1and the second inductor LP2are coupled to a voltage potential VDD at one terminal and coupled to the capacitor CPat the other terminal. The L-C tank formed by the first inductor LP1, the second inductor LP2and the capacitor CPare further coupled to the pair of NMOS transistors M1and M2. It should be noted that the inductors LP1, LP2and the capacitor CPmay be derived from inductive effects of a square area from a wafer such as a square spiral inductor and capacitive effects of a NMOS transistor respectively.

The NMOS transistor M1and the NMOS transistor M2are cross-coupled to opposite terminals. More particularly, the gate of the NMOS transistor M1is coupled to the drain of the NMOS transistor M2and the gate of the NMOS transistor M2is coupled to the drain of the NMOS transistor M1. As shown inFIG. 2, the drains of both NMOS transistors M1and M2are further coupled to the L-C tank formed by inductors LP1, LP2and capacitor CP. The sources of both NMOS transistor M1and M2are connected together and coupled to ground via the bias current source Ibias. As known in the art, the cross-coupled VCO102is capable of having a wider tuning range by fine-tuning the value of the capacitor CP. The operation principle of a cross-coupled VCO is well-known in the art, and thus is not discussed herein.

The buffer104comprises a p-channel metal oxide semiconductor (PMOS) transistor MPand an NMOS transistor MNconnected in series. More particularly, the source of the PMOS transistor MPis connected to the voltage potential VDD and the drain of the PMOS transistor MPis coupled to the drain of the NMOS transistor MN. The gates of the PMOS transistor MPand the NMOS transistor MNare connected together and further coupled to the output of the cross-coupled VCO102via a first blocking capacitor CB1. The buffer further comprises two bias resistors RB1and RB2. The first bias resistor RB1is connected from a bias voltage potential VB1to the gates of MPand MN. The second bias resistor RB2is connected between the gates and drains of both transistors MPand MN. The buffer104is used to isolate the cross-coupled VCO102and the RF peak detector106so as to prevent the RF peak detector106from interfering with the operation of the cross-coupled VCO102. The operation principle of the buffer shown inFIG. 2is well-known in the art, and thus is not discussed herein. However, it should be noted that the buffer shows inFIG. 2can be replaced by any circuits capable of isolating the VCO102from the RF peak detector106. For example, the isolation between the VCO102and the RF peak detector106can be implemented by adding a differential pair between the VCO102and the RF peak detector106.

The RF peak detector106comprises an NMOS transistor M3operating at a weak inversion region, a second block capacitor CB2, a first filter and a second filter. It should be noted whileFIG. 2illustrates a RF peak detector employing an NMOS transistor operating at a weak inversion region, the RF peak detector shown inFIG. 2is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the NMOS transistor may be replaced by a PMOS transistor operating at a weak inversion region. Furthermore, the RF peak detector106can be replaced by any circuits capable of converting an amplitude of an ac signal into a dc value. It should further be noted that whileFIG. 2illustrates two filters connected in cascade, a single filter may fulfill the function of eliminating high frequency unwanted signals and generating a dc value at the output of the RF peak detector106.

While there may be many ways of implementing a RF peak detector, when the RF peak detector is implemented on a wafer, there is a need for simplification as well as performance. As a result, a simple peak detector topology is preferred. The RF peak detector106is formed by a single NMOS transistor, and thus is a preferred embodiment for implementing the built-in self-test circuit for a VCO. The NMOS transistor M3has a gate coupled to a fixed voltage VG, which is small enough so that the NMOS transistor M3is biased to operate in a weak inversion region. As known in the art, the drain current of a NMOS transistor operating in a weak inversion region can be expressed by an exponential function as follows:

ID=WL⁢ID⁢⁢0·ⅇqVGS/nkT·(1-ⅇ-qVDS/kT)
Where W, L, ID0, q, nkT are constants for an NMOS transistor. Because the gate-to-source voltage of the NMOS transistor is fixed, the equation above can be further simplified into the following equation:
ID=K1·(1−eK2·VDS)
Where K1and K2are constants. In accordance with the Taylor series approximation, the drain current can be simplified by replacing the exponential function with the first three terms of the Taylor series. As a consequence, the drain current can be expressed as:

ID=K1·(K2·VDS+12·K22·VDS2)
Where VDSis generated from the output of the VCO102. Use a cosine function to replace VDS. The equation above can be expressed as:

ID=K1·K2·cos⁡(ω⁢⁢X)+14·K1·K22·(1+cos⁡(2⁢ω⁢⁢X))
From the equation above, the drain current comprises a dc component as well as an ac component proportional to the amplitude of the input signal generated from the VCO102. As a result, the NMOS transistor104operating at a weak inversion region can convert an ac input signal into a dc component and an ac component proportional to the signal generated by the VCO102. It should be noted whileFIG. 1illustrates an NMOS transistor operating at a weak inversion region, the RF peak detector can also be implemented by a PMOS transistor operating at a weak inversion region. As known in the art, the operation of a PMOS transistor operating at a weak inversion region will not be discussed herein to avoid repetition.

FIG. 2further illustrates a first filter formed by R1and C1and a second filter formed by R2and C2. Both filters have a cut-off frequency much lower than the frequency of the ac signal generated from the VCO102. As a result, the high frequency ac components at the output of the NMOS transistor M3are eliminated and the dc component can pass through both filters and reach the output of the RF peak detector106. An advantageous feature of having an NMOS transistor operating at a weak inversion region is that a dc component proportional to the amplitude of the output of the VCO can be forwarded to the output of the RF peak detector106and unwanted ac components are eliminated by the low pass filters shown inFIG. 2.

FIG. 3Ashows a built-in self-test circuit for testing a VCO generating a 5.2 GHz signal. When the VCO102functions correctly and generates a 5.2 GHz signal, as shown inFIG. 3B, the spectrum at VAof the RF peak detector106includes a dc component and an ac component at 5.2 GHz. Furthermore, the first filter and second filter eliminate the high frequency ac component. As shown inFIG. 3C, the spectrum at VBincludes only a dc component proportional to the amplitude of the 5.2 GHz signal generated by the VCO102.

FIGS. 4A-4Cillustrate in detail a simulation result of the built-in self-test circuit shown inFIG. 3A. In accordance with an embodiment, when the VCO102is in a normal operation mode generating a 5.2 GHz ac signal, the simulation result shows at VAthe dc component has a voltage potential of 0.37V and the ac component at 5.2 GHz has a amplitude of 0.60V. In contrast, when the VCO102fails to generate an ac signal at 5.2 GHz,FIG. 4Bshows both the dc component and the ac component at 5.2 GHz are at zero volts.FIG. 4Cfurther gives a relationship curve between the amplitude of the ac signal generated by the VCO102and the dc component's value at the output of the RF peak detector106. For example, when the VCO102generates an ac signal having an amplitude of 0.6V, the corresponding dc value at the output of the RF peak detector106is 0.4V. The curve inFIG. 4Cshows another advantageous feature of the RF peak detector is that the amplitude of an ac signal generated by the VCO102can be back-calculated based upon the dc value at the output of the RF peak detector106.