ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME

An electronic device is provided. The electronic device includes a substrate, a first gate line disposed on the substrate, a first insulating layer disposed on the first gate line, a second insulating layer disposed on the first insulating layer, an oxide semiconductor layer disposed between the first insulating layer and the second insulating layer, a second gate line disposed on the second insulating layer, a third insulating layer disposed on the second gate line, and a first conductive element disposed on the third insulating layer, wherein the first conductive element is electrically connected to the first gate line by passing through the first insulating layer, the second insulating layer and the third insulating layer and is electrically connected to the second gate line by passing through the third insulating layer. The method for manufacturing the electronic device is also provided.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of China Patent Application No. 202210456046.9, filed on Apr. 24, 2022, the entirety of which is incorporated by reference herein.

BACKGROUND

Technical Field

The present disclosure relates to an electronic device, and in particular it relates to an electronic device in which a conductive element is connected to the gate lines of a double-gate transistor.

Description of the Related Art

Low-temperature polycrystalline oxide (LTPO) circuits include a low-temperature polycrystalline silicon (LTPS) transistor and an indium gallium zinc oxide (IGZO) transistor. Since the IGZO transistor in the LTPO circuit has the characteristics of low leakage current, if the IGZO transistor is used to replace the transistor that needs to be turned on for a long time in the circuit, the energy-saving effect of the LTPO circuit can be improved.

However, since the electron mobility of IGZO transistors is lower than that of LTPS transistors, how to increase the driving speed of IGZO transistors plays an important role in terms of the overall performance of LTPO circuits.

SUMMARY

In accordance with one embodiment of the present disclosure, an electronic device is provided. The electronic device includes a substrate, a first gate line disposed on the substrate, a first insulating layer disposed on the first gate line, a second insulating layer disposed on the first insulating layer, an oxide semiconductor layer disposed between the first insulating layer and the second insulating layer, a second gate line disposed on the second insulating layer, a third insulating layer disposed on the second gate line, and a first conductive element disposed on the third insulating layer. The first conductive element is electrically connected to the first gate line by passing through the first insulating layer, the second insulating layer and the third insulating layer, and is electrically connected to the second gate line by passing through the third insulating layer.

In accordance with one embodiment of the present disclosure, a method for manufacturing an electronic device is provided. The manufacturing method includes the following steps. A substrate is provided. A first gate line is formed on the substrate. A first insulating layer is formed on the first gate line. An oxide semiconductor layer is formed on the first insulating layer. A second insulating layer is formed on the oxide semiconductor layer. A second gate line is formed on the second insulating layer. A third insulating layer is formed on the second gate line. The third insulating layer is penetrated to expose a portion of the second gate line. The first insulating layer, the second insulating layer and the third insulating layer are penetrated to expose a portion of the first gate line. A first conductive element is formed on the third insulating layer, the portion of the first gate line and the portion of the second gate line, so that the first conductive element is electrically connected to the first gate line and the second gate line.

DETAILED DESCRIPTION

Various embodiments or examples are provided in the following description to implement different features of the present disclosure. The elements and arrangement described in the following specific examples are merely provided for introducing the present disclosure and serve as examples without limiting the scope of the present disclosure. For example, when a first component is referred to as “on a second component”, it may directly contact the second component, or there may be other components in between, and the first component and the second component do not come in direct contact with one another.

It should be understood that additional operations may be provided before, during, and/or after the described method. In accordance with some embodiments, some of the stages (or steps) described below may be replaced or omitted.

In this specification, spatial terms may be used, such as “below”, “lower”, “above”, “higher” and similar terms, for briefly describing the relationship between an element relative to another element in the figures. Besides the directions illustrated in the figures, the devices may be used or operated in different directions. When the device is turned to different directions (such as rotated 45 degrees or other directions), the spatially related adjectives used in it will also be interpreted according to the turned position. In some embodiments of the present disclosure, terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.

Herein, the terms “about”, “around” and “substantially” typically mean a value is in a range of +/−15% of a stated value, typically a range of +/−10% of the stated value, typically a range of +/−5% of the stated value, typically a range of +/−3% of the stated value, typically a range of +/−2% of the stated value, typically a range of +/−1% of the stated value, or typically a range of +/−0.5% of the stated value.

Referring toFIGS.1-3, in accordance with one embodiment of the present disclosure, an electronic device10is provided.FIG.1is the top view of the electronic device10.FIG.2is the rear view of the electronic device10.FIG.3is the cross-sectional view of the electronic device10.

As shown inFIG.3, the electronic device10includes a substrate12, a first insulating layer14, a first semiconductor layer16, a second insulating layer18, a gate electrode20, a third insulating layer22, a first metal layer24, a fourth insulating layer26, an oxide semiconductor layer28, a fifth insulating layer30, a second metal layer32, a sixth insulating layer34, a third metal layer36, a seventh insulating layer38, and a fourth metal layer40. The substrate12includes an active region12aand a peripheral region12badjacent to the active region12a. The first insulating layer14is disposed on the substrate12. The first semiconductor layer16is disposed on the first insulating layer14and located in the peripheral region12bof the substrate12. The second insulating layer18is disposed on the first insulating layer14and covers the first semiconductor layer16. InFIG.3, the transistor42is located in the peripheral region12bof the substrate12. The transistor42may include the first semiconductor layer16(an active layer) and the gate electrode20. The gate electrode20is disposed on the second insulating layer18, corresponding to the position of the first semiconductor layer16. The third insulating layer22is disposed on the second insulating layer18and covers the gate electrode20. The first metal layer24is disposed on the third insulating layer22. The first metal layer24includes a first portion24a, a second portion24band a third portion24c. The first portion24ais located in the active region12aof the substrate12. The second portion24bis located in the peripheral region12bof the substrate12and connected to the first portion24a. The third portion24cis located in the peripheral region12bof the substrate12and separated from the second portion24b. The fourth insulating layer26is disposed on the third insulating layer22and covers the first metal layer24. The fourth insulating layer26has an opening46. InFIG.3, the number of the opening46is two. In some embodiments, the number of the opening46may include other numbers, such as one or more than two. The oxide semiconductor layer28is located in the active region12aof the substrate12and disposed on the fourth insulating layer26. The fifth insulating layer30is disposed on the fourth insulating layer26and covers the oxide semiconductor layer28. The fifth insulating layer30has an opening48. InFIG.3, the number of the opening48is two. In some embodiments, the number of the opening48may include other numbers, such as one or more than two. The second metal layer32is disposed on the fifth insulating layer30. The second metal layer32includes a first portion32aand a second portion32b. The first portion32ais located in the active region12aof the substrate12. The second portion32bis located in the peripheral region12bof the substrate12and connected to the first portion32a. InFIG.3, the transistor44is disposed on the active region12aof the substrate12. In some embodiments, the transistor44may be a double-gate transistor. The transistor44may include the oxide semiconductor layer28. The oxide semiconductor layer28may include indium gallium zinc oxide (IGZO). A first gate line GL1may include the first portion24aand the second portion24bof the first metal layer24. A second gate line GL2may include the first portion32aand the second portion32bof the second metal layer32. The first gate line GL1and the second gate line GL2can be used to provide a gate signal to the transistor44. In addition, the first gate line GL1may be used as a bottom gate of the transistor44. The second gate line GL2may be used as a top gate of the transistor44, but not limited thereto. The sixth insulating layer34is disposed on the fifth insulating layer30and covers the second metal layer32. The sixth insulating layer34has an opening50. InFIG.3, the number of the opening50is two. In some embodiments, the number of the opening50may include other numbers, such as one or more than two. InFIG.3, the opening50overlaps the opening46and the opening48. The sixth insulating layer34further includes an opening52adjacent to the opening50. InFIG.3, the number of the opening52is two. In some embodiments, the number of the opening52may include other numbers, such as one or more than two. The third metal layer36is disposed on the sixth insulating layer34. The third metal layer36includes a first portion36a, a second portion36band a third portion36c. In some embodiments, the conductive element CE may be the first portion36aof the third metal layer36. The conductive element CE may be electrically connected to the second portion24bof the first metal layer24through the fourth insulating layer26, the fifth insulating layer30and the sixth insulating layer34. The conductive element CE may be electrically connected to the second portion32bof the second metal layer32through the sixth insulating layer34. In more detail, inFIG.3, the conductive element CE is electrically connected to the first gate line GL1through the opening46, the opening48and the opening50. The conductive element CE is electrically connected to the second gate line GL2through the opening52. The connection line CL is electrically connected to the first portion36aof the third metal layer36, and electrically connected to the third portion24cof the first metal layer24. In the embodiment, the connection line CL may be the second portion36bof the third metal layer36, but is not limited thereto. The third portion36cof the third metal layer36serves as a drain/source of the transistor42electrically connecting the first semiconductor layer16and the third portion24cof the first metal layer24. The seventh insulating layer38is disposed on the sixth insulating layer34and covers the third metal layer36. The fourth metal layer40is disposed on the seventh insulating layer38, located in the peripheral region12bof the substrate12, corresponding to the position of the third portion24cof the first metal layer24. A driving circuit54is disposed on the peripheral region12bof the substrate12. The driving circuit54may be, for example, the gate on panel (GOP). InFIG.3, the driving circuit54may include the transistor42. The connection line CL may be electrically connected to the driving circuit54and the conductive element CE.

It should be noted that the third metal layer36here refers to the layer-to-layer positional relationship or formation sequence, and is not limited to the formation of the same process or the same material. That is, the third metal layer36is located on the first metal layer24and the second metal layer32, or the third metal layer36is formed behind the first metal layer24and the second metal layer32. The different portions of the third metal layer36may be formed by different processes or different materials. For example, the material of the first portion36aof the third metal layer36may be different from the material of the second portion36bof the third metal layer36, or the first portion36aof the third metal layer36and the second portion36bof the third metal layer36are formed by different processes.

In some embodiments, the substrate12may include a rigid substrate, such as a glass substrate, but the present disclosure is not limited thereto, and other suitable rigid substrate materials are also applicable to the present disclosure. The substrate12may include a flexible substrate, such as a polyimide (PI) substrate, but the present disclosure is not limited thereto, and other suitable flexible substrate materials are also applicable to the present disclosure.

In some embodiments, the first insulating layer14, the second insulating layer18, the third insulating layer22, the fourth insulating layer26, the fifth insulating layer30, the sixth insulating layer34, and the seventh insulating layer38may include organic insulating materials or inorganic insulating materials, for example, silicon oxide, silicon nitride, silicon oxynitride or a combination thereof, but the present disclosure is not limited thereto, and other suitable organic or inorganic insulating materials are also applicable to the present disclosure.

In some embodiments, the first semiconductor layer16may include low-temperature polycrystalline silicon (LTPS), but the present disclosure is not limited thereto, and other suitable semiconductor materials are also applicable to the present disclosure. In some embodiments, when the material selected for the first semiconductor layer16is LTPS, the transistor42is a LTPS transistor. In some embodiments, the gate electrode20, the first metal layer24, the second metal layer32, and the fourth metal layer40may include molybdenum, aluminum, copper or titanium, but the present disclosure is not limited thereto, and other suitable conductive materials are also applicable to the present disclosure. In some embodiments, the oxide semiconductor layer28may include indium gallium zinc oxide (IGZO), but the present disclosure is not limited thereto, and other suitable semiconductor or oxide semiconductor materials are also applicable to the present disclosure. In some embodiments, when the material selected for the oxide semiconductor layer28is IGZO, the transistor44is an IGZO double-gate transistor. In some embodiments, the third metal layer36may include molybdenum, aluminum, copper, titanium or a combination thereof, such as molybdenum/aluminum/molybdenum, titanium/aluminum/titanium or titanium/aluminum/molybdenum, but the present disclosure is not limited thereto, and other suitable conductive materials are also applicable to the present disclosure.

In some embodiments, the conductivity of the material of the connection line CL may be greater than the conductivity of the material of the first gate line GL1and/or the conductivity of the material of the second gate line GL2. For example, in terms of material selection, molybdenum (Mo) may be used for the first metal layer24and the second metal layer32, and aluminum (Al) with better conductivity may be used for the third metal layer36, so the material of the connection line CL may be adjusted to improve signal conduction effect.

Referring toFIGS.1,2and4, the configuration of another transistor44ain the electronic device10and the electrical connection relationship with each element are illustrated. InFIG.4, the portions similar to those disclosed inFIG.3will not be described again. The first metal layer24includes a first portion24a′ and a second portion24b′. The first portion24a′ is located in the active region12aof the substrate12. The second portion24b′ is located in the peripheral region12bof the substrate12and is connected to the first portion24a′. An oxide semiconductor layer29is located in the active region12aof the substrate12. The second metal layer32includes a first portion32a′, a second portion32b′ and a third portion32c′. The first portion32a′ is located in the active region12aof the substrate12. The second portion32b′ is located in the peripheral region12bof the substrate12and is connected to the first portion32a′. The third portion32c′ is located in the peripheral region12bof the substrate12and is separated from the second portion32b′. InFIG.4, the transistor44amay be disposed on the active region12aof the substrate12. In some embodiments, the transistor44amay be a double-gate transistor. The transistor44amay include the oxide semiconductor layer29. The oxide semiconductor layer29may include indium gallium zinc oxide (IGZO). The first gate line GL1may include the first portion24a′ and the second portion24b′ of the first metal layer24. The second gate line GL2may include the first portion32a′ and the second portion32b′ of the second metal layer32. The number of the opening46may include other numbers, such as two or more. The fifth insulating layer30has the opening48, the number of which is one. In some embodiments, the number of the opening48may include other numbers, such as two or more. The sixth insulating layer34has the opening50, the number of which is one. In some embodiments, the number of the opening50may include other numbers, such as two or more. InFIG.4, the opening50overlaps the opening46and the opening48. The sixth insulating layer34further includes the opening52adjacent to the opening50, the number of which is one. In some embodiments, the number of the opening52may include other numbers, such as two or more. The third metal layer36is located in the peripheral region12bof the substrate12. The third metal layer36includes a first portion36a′ and a second portion36b′. In some embodiments, the conductive element CE may be the first portion36a′ of the third metal layer36. The conductive element CE may pass through the fourth insulating layer26, the fifth insulating layer30and the sixth insulating layer34to electrically connect to the second portion24b′ of the first metal layer24, and pass through the sixth insulating layer34to electrically connect to the second portion32b′ of the second metal layer32. In more detail, inFIG.4, the conductive element CE is electrically connected to the first gate line GL1through the opening46, the opening48and the opening50. The conductive element CE is electrically connected to the second gate line GL2through the opening52. The connection line CL is connected to the third portion32c′ of the second metal layer32. The connection line CL is electrically connected to the conductive element CE.

Referring toFIGS.5and6, in accordance with one embodiment of the present disclosure, an electronic device10is provided.FIG.5is the top view of the electronic device10.FIG.6is the cross-sectional view of the electronic device10.

InFIG.6, the portions similar to those disclosed inFIG.3will not be described again. The fourth insulating layer26has the opening46, the number of which is one. In some embodiments, the number of the opening46may include other numbers, such as two or more. The fifth insulating layer30has the opening48, the number of which is one. In some embodiments, the number of the opening48may include other numbers, such as two or more. The sixth insulating layer34has the opening50, the number of which is one. In some embodiments, the number of the opening50may include other numbers, such as two or more. InFIG.6, the opening50overlaps the opening46and the opening48. The sixth insulating layer34further includes the opening52adjacent to the opening50, the number of which is one. In some embodiments, the number of the opening52may include other numbers, such as two or more. The third metal layer36is located in the peripheral region12bof the substrate12. The third metal layer36includes a first portion36a, a second portion36band a third portion36c. In some embodiments, the conductive element CE may be the first portion36aof the third metal layer36. The conductive element CE may pass through the fourth insulating layer26, the fifth insulating layer30and the sixth insulating layer34to electrically connect to the second portion24bof the first metal layer24, and pass through the sixth insulating layer34to electrically connect to the second portion32bof the second metal layer32. In more detail, inFIG.6, the conductive element CE is electrically connected to the first gate line GL1through the opening46, the opening48and the opening50. The conductive element CE is electrically connected to the second gate line GL2through the opening52. The second portion36bis separated from the first portion36aof the third metal layer36. The third portion36cof the third metal layer36serves as the source/drain of the transistor42, electrically connecting the first semiconductor layer16and the third portion24cof the first metal layer24. It should be noted that the connection line CL is electrically connected to the third portion24cof the first metal layer24and the second portion24bof the first metal layer24. In some embodiments, the thickness T3of the connection line CL is greater than the thickness T1of the first gate line GL1or the thickness T2of the second gate line GL2. In some embodiments, as shown inFIG.5, the width We of the connection line CL is greater than the width Wa of the first gate line GL1or the width Wb of the second gate line GL2. In the present disclosure, the signal conduction effect can be improved by adjusting the thickness or width of the connection line CL. InFIG.6, the driving circuit54is disposed on the peripheral region12bof the substrate12. The driving circuit54may be, for example, the gate on panel (GOP). The driving circuit54may include the transistor42. The connection line CL may be electrically connected to the driving circuit54and the conductive element CE.

According to the top view (FIG.5) of the electronic device10, the electrical connection relationship between the transistor44and each element in the electronic device is described. The conductive element CE (i.e. the first portion36aof the third metal layer36) is electrically connected to the first gate line GL1and the second gate line GL2. The connection line CL is electrically connected to the third portion24cof the first metal layer24and the second portion24bof the first metal layer24. The third portion36cof the third metal layer36is electrically connected to the first semiconductor layer16of the transistor42and the third portion24cof the first metal layer24.

Referring toFIG.7, in accordance with one embodiment of the present disclosure, an electronic device10is provided.FIG.7is the cross-sectional view of the electronic device10.

InFIG.7, the portions similar to those disclosed inFIG.6will not be described again. The main difference fromFIG.6is that the electronic device10disclosed inFIG.7further includes a second conductive element disposed on the other end of the transistor44, electrically connected to the gate line of the transistor44. The details are as follows. The first gate line GL1has two ends (GL1band GL1d). The second gate line GL2has two ends (GL2band GL2d). The first conductive element CE is disposed on the peripheral region12bof the substrate12. In some embodiments, the first conductive element CE may be the first portion36aof the third metal layer36, electrically connected to one (for example, the end GL1b) of the two ends (GL1band GL1d) of the first gate line GL1, and electrically connected to one (for example, the end GL2b) of the two ends (GL2band GL2d) of the second gate line GL2. The second conductive element CE′ may be disposed on the peripheral region12bof the substrate12. In some embodiments, the second conductive element CE′ may be electrically connected to the other (for example, the end GL1d) of the two ends (GL1band GL1d) of the first gate line GL1, and electrically connected to the other (for example, the end GL2d) of the two ends (GL2band GL2d) of the second gate line GL2. One of the two ends (GL1band GL1d) of the first gate line GL1is adjacent to one of the two ends (GL2band GL2d) of the second gate line GL2. For example, the end GL1bof the first gate line GL1is adjacent to the end GL2bof the second gate line GL2. The end GL1dof the first gate line GL1is adjacent to the end GL2dof the second gate line GL2.

Referring toFIGS.8and9, in accordance with one embodiment of the present disclosure, an electronic device10is provided.FIG.8is the top view of the electronic device10.FIG.9is the cross-sectional view of the electronic device10.

InFIG.9, the portions similar to those disclosed inFIG.3will not be described again. The first metal layer24includes a first portion24aand a second portion24b. The first portion24ais located in the active area12aof the substrate12. The second portion24bis connected to the first portion24aand located in the peripheral area12bof the substrate12. The second metal layer32includes a first portion32a, a second portion32band a third portion32c. The first portion32ais located in the active region12aof the substrate12. The second portion32bis connected to the first portion32aand located in the peripheral region12bof the substrate12. The third portion32cis separated from the second portion32band located in the peripheral region12bof the substrate12. The third metal layer36includes a first portion36aand a second portion36blocated in the peripheral area12bof the substrate12. It should be noted that the connection line CL may be the second portion36bof the third metal layer36and connected to the conductive element CE, and electrically connected to the third portion32cof the second metal layer32. The third portion36cof the third metal layer36serves as the source/drain of the transistor42, and is electrically connected to the first semiconductor layer16and the third portion32cof the second metal layer32.

According to the top view (FIG.8) of the electronic device10, the electrical connection relationship with each element in the electronic device10is described. The conductive element CE is electrically connected to the first gate line GL1and the second gate line GL2. The connection line CL is connected to an external circuit (not shown).

Referring toFIGS.10and11, the electronic device10shown inFIG.7is taken as an example to illustrate that, when the switching impedance in the device is too large, whether to add a second conductive element in the other end of the transistor44and make the second conductive element electrically connected to the gate line of the transistor44will affect signal transmission.

The reasons for the excessive switching impedance in the device include that the opening made by etching is too small, resulting in insufficient contact area of the metal layer for electrical connection, or the etching gas damages the surface of the metal layer during the process of etching the opening, etc.FIG.10is the circuit diagram of the electronic device. In the circuit design, no conductive element is provided in the other end of the double-gate transistor, that is, one end of the gate lines of the double-gate transistor is not electrically connected to each other.FIG.11is the circuit diagram of the electronic device. In the circuit design, a conductive element is added to the other end of the double-gate transistor, that is, both ends of the gate lines of the double-gate transistor are electrically connected to each other. InFIG.10, when the signal60provided by the external circuit produces a switching impedance62during the transmission process, since one end of the gate lines of the double-gate transistor is not electrically connected to each other (for example, the end GL1dof the first gate line GL1is not electrically connected to the end GL2dof the second gate line GL2), the signal of one of the gate lines is abnormal. In contrast, inFIG.11, when the signal60provided by the external circuit produces a switching impedance62during the transmission process, since both ends of the gate lines of the double-gate transistor are electrically connected to each other (for example, the end GL1dof the first gate line GL1is electrically connected to the end GL2dof the second gate line GL2through the conductive element CE′), the two gate lines of the double-gate transistor obtain the same potential to achieve the effect of stable signal transmission.

Referring toFIGS.12to14, in accordance with one embodiment of the present disclosure, a method for manufacturing an electronic device is provided.FIGS.12to14are the cross-sectional views of the manufacturing method of the electronic device. Some elements in the electronic device are omitted in the figures for convenience of description.

First, as shown inFIG.12, a substrate12is provided, on which a first insulating layer14, a second insulating layer18, a third insulating layer22, a first metal layer24, a fourth insulating layer26, an oxide semiconductor layer28, a fifth insulating layer30, a second metal layer32, a sixth insulating layer34and a photoresist layer64are sequentially formed.

Next, as shown inFIG.13, the photoresist layer64is patterned to form a patterned photoresist layer66. The patterned photoresist layer66includes a first opening68and a second opening70. InFIG.13, the number of the first opening68is two. The number of the second opening70is two. In some embodiments, the number of the first opening68and the second opening70may include other numbers, such as one or more than two. Next, using the patterned photoresist layer66as an etching mask, the insulating layers under the patterned photoresist layer66are etched to form a third opening72and a fourth opening74, respectively exposing a portion of the first metal layer24and a portion of the second metal layer32. The number of the third opening72is two, which pass through the fourth insulating layer26, the fifth insulating layer30and the sixth insulating layer34, exposing a portion of the first metal layer24. The number of the fourth opening74is two, which pass through the sixth insulating layer34and expose a portion of the second metal layer32.

Next, as shown inFIG.14, a third metal layer36is formed on the sixth insulating layer34, and fills the third opening72and the fourth opening74to form on the exposed first metal layer24and the second metal layer32, so that the third metal layer36is electrically connected to the first metal layer24and the second metal layer32. So far, the fabrication of the conductive elements in the electronic device is completed. It should be noted that, in some embodiments, the step of etching through the sixth insulating layer34and the step of etching through the fourth insulating layer26, the fifth insulating layer30and the sixth insulating layer34are implemented in the same process.

Referring toFIG.13, the size relationship of each opening in the structure of the electronic device is further described.

As shown inFIG.13, the width of the first opening68is W1. The width of the second opening70is W2. The width of the third opening72is W3. The width of the fourth opening74is W4. The spacing between the third openings72is S1. The spacing between the fourth openings74is S2. The spacing between the third opening72and the fourth opening74is S3. InFIG.13, the width W1of the first opening68is greater than the width W2of the second opening70. The width W3of the third opening72is greater than the width W4of the fourth opening74. The width W1of the first opening68is greater than the width W3of the third opening72. The width W2of the second opening70is greater than the width W4of the fourth opening74. The spacing S1between the third openings72is smaller than the spacing S3between the third openings72and the fourth openings74. The spacing S2between the fourth openings74is smaller than the spacing S3between the third openings72and the fourth openings74. In some embodiments, the width W3of the third opening72and the width W4of the fourth opening74are approximately between 2 μm and 4 μm. In some embodiments, the spacing S1of the first openings68and the spacing S2of the second openings70are approximately between 0.5 μm and 2 μm. In some embodiments, the spacing S3between the first opening68and the second opening70is approximately between 3 μm and 5 μm. It should be noted that the width W3(i.e. the width of the bottom of the opening) of the third opening72and the width W4(i.e. the width of the bottom of the opening) of the fourth opening74should not be too small to reduce poor electrical contact. However, an excessively large size also occupies more space. The spacing S1between the first openings68and the spacing S2between the second openings70should not be too small to reduce the possibility of collapse of the opening structure, but also should not be too large to reduce the occupied area. In addition, the spacing S3between the first opening68and the second opening70can be appropriately large to reduce the connection between the third opening72and the fourth opening74, resulting in excessive impedance and failure of the upper and lower gate lines at the same time.

In the present disclosure, a metal conductive element is used to simultaneously connect to the top gate and the bottom gate of the double-gate transistor. The circuit design enables channels to be formed on the upper and lower surfaces of the conductor layer, which can effectively increase the driving speed (ION) of the transistor. In the present disclosure, the electrical signal provided by the external circuit (for example, flexible printed circuit board (FPC) or chip-on-film (COF)) can be transmitted to the metal conductive element through the connection line on the upper layer, and then drive the top gate and bottom gate of the double-gate transistor, or it is firstly transmitted to the bottom gate of the double-gate transistor through the connection line on the lower layer, and then transmitted to the top gate of the double-gate transistor through the metal conductive element. If the top gate and the bottom gate are directly connected to each other, more photolithography process steps are required, and the line impedance of the bottom gate is also increased, causing the RC load of the bottom gate to be greater than that of the top gate, resulting in a potential difference between the top and bottom gates. The disclosed method of fabricating the metal conductive element connecting the top gate and the bottom gate at the same time (that is, forming openings with different depths simultaneously in the same process) has fewer photolithography process steps. In the present disclosure, increasing the number of switching openings can reduce the risk of overall signal switching failure due to excessive switching impedance of a single opening. In the present disclosure, the effect of signal transmission can be improved by adjusting the material (chosen to have better conductivity), thickness or width of the connection line. In addition, the metal conductive element of the present disclosure is electrically connected to the top gate and the bottom gate through the openings corresponding to the top gate and the bottom gate respectively, so as to increase the contact area of the top gate and the bottom gate for the electrical connection, which can reduce the switching impedance.