Dual write wordline memory cell

A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

The present disclosure is generally related to a dual write wordline memory cell.

II. DESCRIPTION OF RELATED ART

A computing device may include a memory (e.g., random access memory (RAM)) to store data. The memory may include memory cells as storage elements. Data errors may occur at the memory, causing data read from the memory to differ from data written to the memory. A data error at a particular memory cell may occur when a value is written to another memory cell that shares a common wordline or a common bitline with the particular memory cell. When the common wordline or the common bitline is used to send signals to the other memory cell, transistors at the particular memory cell may trigger and may modify data stored at the particular memory cell. This type of error is referred to as a half-select error.

A seven transistor (7T) static random-access memory (SRAM) memory cell that utilizes a single write bitline and two independently controlled write wordlines is disclosed. The 7T memory cell may use a two-phase write operation during memory write operations. For example, during a memory write operation, a first write wordline (WWL1) may be used to select a row of 7T memory cells (and their associated gating transistors) and a second write wordline (WWL2), and a write bitline (WBL) may be used to write a value to the memory cells of the selected row. In a particular embodiment, a first phase of the two-phase write operation may write a logical “1” value (e.g., a “high” value) to the memory cells of the selected row. In a second phase of the two-phase write operation, a logical “0” value (e.g., a “low” value) may be selectively written to memory cells that are to store a logical “0” value.

In a particular embodiment, an SRAM memory cell includes a pair of cross-coupled inverters. The SRAM memory cell also includes a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. The gating transistor has a gate that is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

In another particular embodiment, a method includes, during a first phase of a write operation of a memory cell that includes a pair of cross-coupled inverters, applying a first signal to a first wordline to selectively couple a bitline to a first node of a first inverter of the pair of cross-coupled inverters. The method also includes, during the first phase of the write operation, applying a second signal to a second wordline that is coupled to a second node of the first inverter. The first signal is independently generated from the second signal. The method also includes, during the first phase of the write operation, applying a third signal to the bitline.

In another particular embodiment, an apparatus includes a first means for inverting. The apparatus also includes a second means for inverting. The first means for inverting and the second means for inverting are cross-coupled. The apparatus also includes a means for switching coupled to a first node of the first means for inverting. A control input of the means for switching is coupled to a first wordline. The means for switching selectively couples a bitline to the first node of the first means for inverting responsive to a first wordline signal. The first means for inverting has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

In a particular embodiment, a non-transitory computer readable medium storing instructions. The instructions are executable by the processor to cause the processor to, during a first phase of a write operation of a memory cell that includes a pair of cross-coupled inverters, initiate application of a first signal to a first wordline to selectively couple a bitline to a first node of a first inverter of the pair of cross-coupled inverters. The processor may also, during the first phase of the write operation, initiate application of a second signal to a second wordline that is coupled to a second node of the first inverter, where the first signal is independently generated from the second signal. The processor may also, during the first phase of the write operation, initiate application of a third signal to the bitline.

One particular advantage provided by at least one of the disclosed embodiments is reduced dynamic power consumption without degrading the data hold stability of a memory cell (e.g., column half selected cells). For example, an eight transistor (8T) memory cell may be susceptible to half select error for half-selected memory cells of a selected memory row during write operations. To compensate for the half select error, a write-back scheme (also referred to as a “read-modify-write” scheme) may be used. However, the write-back scheme applied to an 8T memory cell may result in a significant increase in total write power, which includes the bitline power used during the read operation, the bitline power used to write back to unselected cells, and the bitline power used to write to the selected cell. To address the power consumption associated with an 8T write-back scheme, a single write bitline structure for the memory cell may be used. However, the single write bitline structure may be unable to write a “strong” logical “1” for write operations. By contrast, a dual write wordline memory cell that uses a two-phase write operation may provide proper write operations in the single write bitline structure without degrading data read/hold stability of a memory cell and may provide reduced power consumption for write operation of a memory cell.

V. DETAILED DESCRIPTION

Referring toFIG. 1, a particular illustrative embodiment of a dual write wordline memory cell100is shown. The dual write wordline memory cell100includes a first inverter102, a second inverter104, a first write wordline106, a write bitline108, a second write wordline110, a read wordline112, a read bitline114, a gating transistor116, and a read buffer118. The first inverter102may include a first p-type metal-oxide-semiconductor (PMOS) transistor120coupled in series with a first n-type metal-oxide-semiconductor (NMOS) transistor122. The second inverter104may include a second PMOS transistor124coupled in series with a second NMOS transistor126. The first inverter102may be cross-coupled with the second inverter104to form a pair of cross-coupled inverters. For example, an input of the first inverter102may be coupled to an output of the second inverter104and an input of the second inverter104may be coupled to an output of the first inverter102. The first inverter102and the second inverter104may together store a data value (e.g., a data value of the dual write wordline memory cell100). The pair of cross-coupled inverters, the first transistor, and the read buffer may correspond to a single write bitline memory cell architecture. The dual write wordline memory cell100may be part of a row of a memory array, as described below with reference toFIG. 2.

The gating transistor116may include a NMOS transistor or a PMOS transistor. The gating transistor116may have a gate terminal coupled to the first write wordline106. Thus, the gating transistor116may be responsive to the first write wordline106. Based on a signal from the first write wordline106, the gating transistor116may selectively couple the write bitline108to a first node128that corresponds to the input of the second inverter104(and to the output of the first inverter102). When the write bitline108is coupled to the input of the second inverter104, the write bitline108may cause the first inverter102and the second inverter104to store a value (e.g., a memory cell data value).

The second write wordline110may be coupled to a source terminal of a transistor of the first inverter102(e.g., to a source terminal of the first PMOS transistor120or to a source terminal of the first NMOS transistor122). The second write wordline110may be used to selectively apply a signal to the source terminal of the transistor of the first inverter102. The second write wordline110and the first write wordline106may be independently controllable. In a first embodiment, as illustrated inFIG. 1, the gating transistor116includes a NMOS transistor with a gate terminal coupled to the first write wordline106, the second write wordline110is coupled to a second node130that corresponds to a source terminal of the first NMOS transistor122, and the drain terminal of the first NMOS transistor122is coupled to the gating transistor116that is coupled to the first node128. In a second embodiment, the gating transistor116includes a PMOS transistor and the second write wordline110is coupled to a source terminal of the first PMOS transistor120.

During operation, a two-phase write operation may be performed at the dual write wordline memory cell100. In a first embodiment, a first phase of the two-phase write operation may include writing a logical “1” value to the dual write wordline memory cell100(e.g., regardless of data to be stored at the dual write wordline memory cell100). In the first embodiment, a second phase of the two-phase write operation may include selectively writing a logical “0” to the dual write wordline memory cell100based on a corresponding data value (e.g., a data value received from an execution unit). The corresponding data value may be received from a processing device and may correspond to a value (e.g., a memory cell data value) to be stored at the dual write wordline memory cell100. Thus, the second phase of the write operation may be different from memory cell to memory cell at the dual write wordline memory cell100based on the corresponding data value. In the second embodiment, the first phase of the two-phase write operation may include writing a logical “0” value to the dual write wordline memory cell100. In the second embodiment, the second phase of the two-phase write operation may include selectively writing a logical “1” to the dual write wordline memory cell100based on the corresponding data value.

To illustrate, in the first embodiment, during a first phase of the write operation, a logical “1” value is written to the dual write wordline memory cell100. The logical “1” value may be written by providing a select signal to the first write wordline106(e.g., a first signal), and providing signals (e.g., voltages) corresponding to a logical “1” value to the second write wordline110(e.g., a second signal), and to the write bitline108(e.g., a third signal). Thus, the gating transistor116may be enabled and the write bitline108may send the logical “1” to the first node128. When, prior to the first phase of the write operation, the input of the second inverter104is a logical “0” value, the first NMOS transistor122may be enabled. When the first NMOS transistor122is enabled, the first NMOS transistor122may send a value of the second write wordline110(e.g., a logical “1” value) from the second node130to the first node128. Thus, when the data value of the input of the second inverter104is changed from a logical “0” value to a logical “1” value, both the gating transistor116and the first NMOS transistor122may send a logical “1” value to the first node128. Sending the logical “1” value to the first node128using both the gating transistor116and the first NMOS transistor122may change a value at the input of the second inverter104more quickly and with less average leakage current, as compared to sending the logical “1” value to the first node128using only the gating transistor116. In the second embodiment, during the first phase of the write operation, a logical “0” value is written to the dual write wordline memory cell100(e.g., to the first node128) instead of a logical “1” value.

In the first embodiment, during a second phase of the write operation, after the logical “1” value has been written to the dual write wordline memory cell100, a logical “0” value may be selectively written to the dual write wordline memory cell100based on the corresponding data value. The logical “0” may be written by providing signals (e.g., voltages) corresponding to a logical “0” value to the second write wordline110(e.g., a fourth signal) and to the write bitline108(e.g., a fifth signal). For example, when the corresponding data value is a logical “0,” signals corresponding to a logical “0” value may be sent from the write bitline108to the first node128. In this example, when the corresponding data value is a logical “1,” a logical “0” value is not sent from the write bitline108to the input of the second inverter104. In the second embodiment, during the second phase of the write operation, after the logical “0” value has been written to the dual write wordline memory cell100, a logical “1” value is selectively written to the input of the second inverter104instead of a logical “0” value.

The read buffer118, the read wordline112, and the read bitline114may be used to perform a read operation at the dual write wordline memory cell100. The read buffer118may be coupled to a third node132of the first inverter102(e.g., corresponding to an input of the first inverter102). During operation, a value at the read wordline112may indicate a read request corresponding to the dual write wordline memory cell100. Based on the value at the read wordline112and a value at the third node132, the read buffer118may cause a value at the read bitline114to correspond to a value at the first node128. In a particular embodiment, the read buffer118includes two transistors (e.g., NMOS transistors) coupled to a source voltage (e.g., a ground voltage). In the particular embodiment, the dual write wordline memory cell100corresponds to a seven-transistor memory cell architecture.

By utilizing the two-phase write operation with the dual write wordline memory cell100, a reduction in write power consumption may be achieved and the data hold stability of the memory cell may be maintained. Additionally, by applying the two-phase write operation to the dual write wordline memory cell100, a reduction in bitline current leakage may be achieved during write operations.

Referring toFIG. 2, details of a particular embodiment of a portion of a memory device200that includes a dual write wordline memory cell is shown and generally designated200. The memory device200may be a static random-access memory (SRAM). The memory device200may include one or more dual write wordline memory cells (e.g., dual write wordline memory cells202,204,206, or208ofFIG. 2) that may form part of an array of dual write wordline memory cells (i.e., the “memory array”). The dual write wordline memory cells202,204,206, and208may each correspond to the dual write wordline memory cell100ofFIG. 1.

A first row201of the portion of the memory array of the memory device200may include a dual write wordline memory cell204(e.g., the dual write wordline memory cell100ofFIG. 1). The dual write wordline memory cell204may share a first write wordline210(e.g., the first write wordline106ofFIG. 1), a second write wordline212(e.g., the second write wordline110ofFIG. 1), and a first read wordline214(e.g., the read wordline112ofFIG. 1) with other dual write wordline memory cells (e.g., a dual write wordline memory cell202) of the first row201of the memory array. The dual write wordline memory cell204may also share a first write bitline226(e.g., the write bitline108ofFIG. 1) and a first read bitline228(e.g., the read bitline114ofFIG. 1) with other dual write wordline memory cells (e.g., a dual write wordline memory cell208) of a column of memory cells of the memory array.

A second row203of the portion of the memory array may include a dual write wordline memory cell208(e.g., the dual write wordline memory cell100ofFIG. 1). The dual write wordline memory cell208may share a third write wordline216(e.g., the write wordline106ofFIG. 1), a fourth write wordline218(e.g., the write wordline110ofFIG. 1), and a second read wordline220(e.g., the read wordline112ofFIG. 1) with other dual write wordline memory cells (e.g., a dual write wordline memory cell206) of the second row203of memory cells of the memory array. The dual write wordline memory cell208may also share the first write bitline226and the first read bitline228with other dual write wordline memory cells (e.g., a dual write wordline memory cell204) of a column of memory cells of the memory array.

During operation, a two-phase write operation may be performed at a selected row of the memory array, the selected row including one or more of a dual write wordline memory cell. The two-phase write operation may be performed at dual write wordline memory cells of more than one selected row. For example, when the first row201is selected (e.g., when a select signal is applied to write wordline210), the two-phase write operation may be performed at the dual write wordline memory cells204and202of the first row201. In a first embodiment, a first phase of the two-phase write operation may include writing a logical “1” value to every cell of the first row (e.g., regardless of data to be stored at each cell).

For example, the first phase may include providing a select signal to the first write wordline210(e.g., a first signal at106ofFIG. 1), and providing signals (e.g., voltages) corresponding to a logical “1” value to the second write wordline212(e.g., a second signal at110ofFIG. 1), and to the write bitlines226and222(e.g., a third signal at write bitline108ofFIG. 1). Thus, gating transistors of each of the dual write wordline memory cells202and204of the first row201may send a logical “1” value to a first node of a first inverter.

To illustrate, prior to the first phase write operation, if the dual write wordline memory cells204and202both store a logical “0” value, application of the first phase write operation may write a logical “1” value to the dual write wordline memory cells204and202, regardless of the data to be stored at each cell.

In the first embodiment, a second phase of the two-phase write operation may include selectively writing a logical “0” to memory cells of the first row201based on a corresponding data value of multiple data values. The multiple data values may be received from a processing device and may include a value (e.g., a memory cell data value) to be stored at each memory cell in the first row201. Thus, the second phase of the write operation may be different for different cells of the row of memory cells.

To illustrate, for the first row201, the second phase may include maintaining a select signal to the first write wordline210(e.g., a first signal at106ofFIG. 1), selectively providing a signal corresponding to a logical “0” value to the second write wordline212(e.g., a fourth signal at110ofFIG. 1), selectively providing a signal corresponding to a logical “0” value to the write bitline222(e.g., a sixth signal at write bitline108ofFIG. 1), and selectively providing a signal corresponding to a logical “1” value to the write bitline226(e.g., a sixth signal at write bitline108ofFIG. 1) based on corresponding data values associated with the dual write wordline memory cells202and204. For example, the corresponding data value may be received from a processing device and may correspond to a value (e.g., a memory cell data value) to be stored at a particular dual write wordline memory cell (e.g., the dual write wordline memory cells204or202). When the corresponding data value is a logical “0,” signals corresponding to a logical “0” value may be sent to a particular dual write wordline memory cell. When the corresponding data value is a logical “1,” signals corresponding to a logical “1” value may be sent to the particular dual write wordline memory cell.

To illustrate, prior to a first phase write operation, the dual write wordline memory cells204and202may both store a logical “0” value. For a particular write operation, where a logical “1” value is to be written to dual write wordline memory cell204and a logical “0” value is to be maintained at other memory cells (e.g., the dual write wordline memory cell202) in the first row201, application of the first phase write operation may write a logical “1” value to both dual write wordline memory cells204and202. Thus, when the corresponding data value for the dual write wordline memory cell204, received from a processing device, is a data value that corresponds to a logical “1” to be stored at the dual write wordline memory cell204, application of the first phase write operation writes the corresponding data value to the dual write wordline memory cell204. During the second phase write operation, to write a logical “0” value (e.g., based on the corresponding data value) to the dual write wordline memory cell202, a logical “0” value may be selectively written to the dual write wordline memory cell202via a signal (e.g., voltage) corresponding to a logical “0” value applied to the write bitline222. During the second phase write operation, a logical “1” value may be selectively written to the dual write wordline memory cell204via a signal (e.g., voltage) corresponding to a logical “1” value applied to the write bitline226.

Thus, in a first embodiment, the first phase write operation may write a logical “1” to all cells of the selected row, regardless of data to be stored at each cell. The second phase write operation may selectively write a logical “0” to one or more selected memory cells of the selected row based on data to be stored at the one or more memory cells. In a second embodiment, the first phase of the two-phase write operation may include writing a logical “0” value to every cell of the row. In the second embodiment, the second phase of the two-phase write operation may include selectively writing a logical “1” to one or more memory cells of the selected row based data to be stored at the one or more memory cells. Although two dual write wordline memory cells are illustrated inFIG. 2, the first row201may include more than two dual write wordline memory cells. When more than two dual write wordline memory cells are part of the first row201, in the first embodiment, the first phase writes logical “1” to all memory cells and the second phase writes “0” to some memory cells.

In a particular embodiment, a read operation may be performed at the dual write wordline memory cells of a selected row of memory cells prior to the execution of a two-phase write operation. Additionally, a read operation may be performed at dual write wordline memory cells of more than one selected row. For example, prior to a two-phase write operation, a signal (e.g., voltage) may be provided at the read wordline214that may indicate a read request corresponding to the dual write wordline memory cells of the first row201. Data values stored by the dual write wordline memory cells (e.g., dual write wordline memory cells202and204) of the first row201may be read causing corresponding values to be sensed at read bitlines of the memory array (e.g., read bitline (RBL)224and RBL228). In a particular embodiment, the read data values at the read bitlines (e.g., RBL224and RBL228) may be latched or otherwise captured and may be used by a processing device for sending a corresponding data value for use in the second phase of the two-phase write operation of the dual write wordline memory cell.

Using the two-phase write operation as part of a write operation of a memory array may enable the maintenance of data hold stability for both selected and half-selected memory cells of a selected row. Additionally, by using the two-phase write operation with the dual write wordline memory cell, a capacitance to be toggled during a write operation may be reduced and may enable a reduction in switching power during write operations.

Referring toFIG. 3, additional detail of the operation of a memory cell, such as the dual write wordline memory cell100, during a first embodiment of a two-phase write operation is shown in the graph300.FIG. 3illustrates a graph300of signals at a first write wordline (WWL1), at a second write wordline (WWL2), and at a write bitline (WBL). The WWL1may correspond to the first write wordline106ofFIG. 1or the first write wordline210ofFIG. 2. The WWL2may correspond to the second write wordline110ofFIG. 1or the second write wordline212ofFIG. 2. The WBL may correspond to the write bitline108ofFIG. 1or the write bitlines222or226ofFIG. 2.

As illustrated by the graph300, during a first phase of the write operation, signals corresponding to a logical “1” value are applied at the WWL1(e.g., a first signal), at the WWL2(e.g., a second signal), and at the WBL (e.g., a third signal). For example, referring toFIG. 1, application of a logical “1” at the WWL1may enable the gating transistor116to couple a signal applied to the WBL108to the first node128of the first inverter102. Thus, the WBL108provides a logical “1” value to the first node128of the first inverter102. Prior to the first phase of the write operation, if the input of the second inverter104is a logical “0” value, the first NMOS transistor122may be enabled. Thus, the first NMOS transistor122provides the logical “1” value applied at the WWL2110from the second node130to the first node128. Accordingly, when the WWL1, the WWL2, the WBL and the data value of the output of the second inverter104have a logical “1” value, both the gating transistor116and the first NMOS transistor122may send a logical “1” value to the first node128.

As illustrated by the graph300, during a second phase of the two-phase write operation, a signal corresponding to a logical “1” value may be applied to the WWL1(e.g., the first signal) and a signal corresponding to a logical “0” value may be applied to the WWL2(e.g., a fourth signal). A value applied to the WBL depends on a corresponding data value to be stored at the particular memory cell. When the corresponding data value (e.g., a value received from a processing device) is a logical “0”, a signal corresponding to a logical “0” may be selectively applied to the WBL (e.g., a fifth signal). For example, referring toFIG. 1, a logical “0” may be applied to the WWL2110. Application of a logical “1” at the WWL1may enable the gating transistor116to couple a signal applied to the WBL108to the first node128of the first inverter102. A logical “0” may be selectively applied to the WBL based on a data value that corresponds to writing a logical “0” value (e.g., Write “0”) to the dual write wordline memory cell (e.g., the dual write wordline memory cell100ofFIG. 1, or the dual write wordline memory cells202,204,206,208ofFIG. 2). When the corresponding data value is a logical “1”, a logical “1” may be selectively applied to the WBL to write a logical “1” value (e.g., Write “1”) to the dual write wordline memory cell (e.g., the dual write wordline memory cell100ofFIG. 1, or the dual write wordline memory cells202,204,206,208ofFIG. 2). Thus, when WWL1has a logical “1” value and WWL2has a logical “0” value, WBL may selectively send either a logical “0” value or a logical “1” value to the first node128based on a data value that corresponds to either a Write “0” or a Write “1” to the dual write wordline memory cell, respectively.

In a particular embodiment, one or both of wordlines WWL1and WWL2may be voltage “boosted” to improve performance of write operations. For example, the first signal, the second signal, or both the first and the second signal may be voltage-boosted signals (i.e., >Vdd) that may be applied at wordlines WWL1and WWL2. In a particular embodiment, a voltage-boosted signal that is greater than Vdd may be applied to both WWL1and WWL2. In another embodiment, the voltage-boosted signal applied to the WWL1may be a voltage greater than Vdd, and the voltage-boosted signal applied to the WWL2may be a voltage less than Vss. Control of wordlines WWL1and WWL2in the row direction may enable voltage boosting while avoiding the column-select issue that may occur at memory cells of a selected row.

Referring toFIG. 4, a particular embodiment of a method400of operating a dual write wordline memory cell is shown. The method400may be applied to an SRAM dual write wordline memory cell. The method400may, for example, be applied to the dual write wordline memory cell100ofFIG. 1. In another example, the method400may be applied to the dual write wordline memory cells (e.g., the dual write wordline memory cells202,204,206,208) that form part of the memory array of the memory device200ofFIG. 2. The method400may be executed by the memory device200ofFIG. 2and/or the communication device500ofFIG. 5.

The method400may include a first phase of a write operation of a memory cell that includes a pair of crossed-coupled inverters, at402. During the first phase402, the method400may include applying a first signal to a first wordline to selectively couple a bitline to a first node of a first inverter of the pair of cross-coupled inverters, at403. For example, in a first embodiment, a signal (e.g., a voltage) corresponding to a logical “1” value may be provided to the first write wordline106ofFIG. 1to enable the gating transistor116. When enabled, the gating transistor116couples the write bitline108to the first node128of the first inverter102of the pair of crossed-coupled inverters102,104.

During the first phase402, the method400also includes applying a second signal to a second wordline that is coupled to a second node of the first inverter, where the first signal is independently generated from the second signal, at404. For example, in a first embodiment, a second signal (e.g., a voltage) corresponding to a logical “1” value may be provided to the second write wordline110ofFIG. 1, which is coupled to the second node130of the first inverter102. The second signal may have a voltage value that corresponds to a source voltage (e.g., Vdd) of the first inverter102. The first signal may be generated independently from the second signal to enable the first signal to remain at a logical value (e.g., logical “1”) in more than one phase (e.g., during the first phase and the second phase) while the second signal is changed for different phases based on a value to be stored at the dual write wordline memory cell100(e.g., a logical “1” during the first phase and a logical “0” during the second phase).

During the first phase402, the method400also includes applying a third signal to the bitline, at405. For example, in the first embodiment, a signal (e.g., a voltage) corresponding to a logical “1” value may be provided to a write bitline108. Thus, during the first phase, a logical “1” value may be written to the dual write wordline memory cell100by providing signals (e.g., voltages) corresponding to a logical “1” value to the first write wordline106(e.g., the first signal), to the second write wordline110(e.g., the second signal), and to the write bitline108(e.g., the third signal).

The method400may include a second phase of a write operation of the memory cell, at406. During the second phase406, the method400may include applying a fourth signal to the second wordline, at407. For example in a first embodiment, a signal (e.g., voltage) corresponding to a logical “0” value may be provided to the second write wordline110.

During the second phase406the method400also includes applying, based on a corresponding data value, a fifth signal to the bitline, at408. For example, after the logical “1” value has been written to the dual write wordline memory cell100during the first phase, a logical “0” value may be selectively provided to the write bitline108to selectively write a logical “0” value to the dual write wordline memory cell100based on a corresponding data value. In a particular embodiment, a logical “1” value may be selectively provided to the write bitline108to selectively write a logical “1” value to the dual write wordline memory cell100based on the corresponding data value.

Although the method400ofFIG. 4has been described above with regard toFIG. 1, the method400may also be performed by the memory device200ofFIG. 2. The method400ofFIG. 4may be implemented by a field-programmable gate array (FPGA) device, an application-specific integrated circuit (ASIC), a processing unit such as a central processing unit (CPU), a digital signal processor (DSP), a controller, another hardware device, firmware device, or any combination thereof. As an example, the method ofFIG. 4can be performed by a processor or memory controller that executes instructions, as described with respect toFIG. 5

Referring toFIG. 5, a particular embodiment of a wireless communication device500including a dual write wordline memory cell502is shown. The communication device500includes a processor512(e.g., a DSP), coupled to a memory532. The memory532includes one or more of a dual write wordline memory cell502as part of a memory array of the memory532. In an illustrative embodiment, the dual write wordline memory cell502may correspond to the dual write wordline memory cell100ofFIG. 1. In another illustrative embodiment, the memory532may include an array of dual write wordline memory cells, such as the dual write wordline memory cells202,204,206and208ofFIG. 2.

The memory532may be a non-transient computer readable medium storing computer-executable instructions504that are executable by the processor512to cause the processor512, during a first phase of a write operation of a memory cell that includes a pair of cross-coupled inverters, to initiate application of a first signal to a first write wordline (e.g., the write wordline106ofFIG. 1) to selectively couple a write bitline (e.g., the write bitline108ofFIG. 1) to a first node (e.g., the first node128ofFIG. 1) of a first inverter (e.g., the first inverter102ofFIG. 1) of the pair of cross-coupled inverters. The processor512may further initiate application of a second signal to a second write wordline (e.g., the write wordline110ofFIG. 1) that is coupled to a second node (e.g., the second node130ofFIG. 1) of the first inverter, where the first signal is independently generated from the second signal. The processor512may still further initiate application of a third signal to the write bitline (e.g., the write bitline108ofFIG. 1).

FIG. 5also shows a display controller526that is coupled to the processor512and to a display528. A coder/decoder (CODEC)534can also be coupled to the processor512. A speaker536and a microphone538can be coupled to the CODEC534.

FIG. 5also indicates that a wireless controller540can be coupled to the processor512and to an antenna542. In a particular embodiment, the processor512, the display controller526, the memory532, the CODEC534, and the wireless controller540are included in a system-in-package or system-on-chip device522. In a particular embodiment, an input device530and a power supply544are coupled to the system-on-chip device522. Moreover, in a particular embodiment, as illustrated inFIG. 5, the display528, the input device530, the speaker536, the microphone538, the antenna542, and the power supply544are external to the system-on-chip device522. However, each of the display528, the input device530, the speaker536, the microphone538, the antenna542, and the power supply544can be coupled to a component of the system-on-chip device522, such as an interface or a controller.

In conjunction with the described embodiments, a system is disclosed that may include a pair of cross-coupled means for inverting, such as the pair of crossed-coupled inverters102,104ofFIG. 1, one or more other devices or circuits configured to cause inverting, or any combination thereof. The system may also include a first means for inverting, such as the first inverter102ofFIG. 1, one or more other devices or circuits configured to cause switching, or any combination thereof. The system may also include means for switching, that is coupled to a first wordline, where the switching means selectively couples a bitline to the first node of the first means for inverting responsive to a first wordline signal, where the first means for inverting has a second node coupled to a second wordline, and where the first wordline and the second wordline are each independently controllable, such as the gating transistor116and the first inverter102ofFIG. 1, one or more other devices or circuits configured to cause switching, or any combination thereof. The system may be integrated in at least one die and may be integrated into at least one electronic device.

The foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g. RTL, GDSII, GERBER, etc.) stored on computer readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into semiconductor die and packaged into a semiconductor chip. The chips are then employed in devices described above.FIG. 6depicts a particular illustrative embodiment of an electronic device manufacturing process600.

Referring toFIG. 6, a particular embodiment of a manufacturing process600to manufacture electronic devices that include a dual write wordline memory cell is shown. Physical device information602is received at the manufacturing process600, such as at a research computer606. The physical device information602may include design information representing at least one physical property of a semiconductor device, such as the dual write wordline memory cell100ofFIG. 1, the array of dual write wordline memory cells of memory device200ofFIG. 2, or the dual write wordline memory cell502ofFIG. 5, or any combination thereof. For example, the physical device information602may include physical parameters, material characteristics, and structure information that is entered via a user interface604coupled to the research computer606. The research computer606includes a processor608, such as one or more processing cores, coupled to a computer readable medium such as a memory610. The memory610may store computer readable instructions that are executable to cause the processor608to transform the physical device information602to comply with a file format and to generate a library file612.

In a particular embodiment, the library file612includes at least one data file including the transformed design information. For example, the library file612may include a library of semiconductor devices including a device that includes the dual write wordline memory cell100ofFIG. 1, the array of dual write wordline memory cells of memory device200ofFIG. 2, or the dual write wordline memory cell502ofFIG. 5, or any combination thereof, that is provided for use with an electronic design automation (EDA) tool620.

The library file612may be used in conjunction with the EDA tool620at a design computer614including a processor616, such as one or more processing cores, coupled to a memory618. The EDA tool620may be stored as processor executable instructions at the memory618to enable a user of the design computer614to design a circuit including the dual write wordline memory cell100ofFIG. 1, the array of dual write wordline memory cells of memory device200ofFIG. 2, or the dual write wordline memory cell502ofFIG. 5, or any combination thereof, of the library file612. For example, a user of the design computer614may enter circuit design information622via a user interface624coupled to the design computer614. The circuit design information622may include design information representing at least one physical property of a semiconductor device, such as the dual write wordline memory cell100ofFIG. 1, the array of dual write wordline memory cells of memory device200ofFIG. 2, or the dual write wordline memory cell502ofFIG. 5, or any combination thereof. To illustrate, the circuit design property may include identification of particular circuits and relationships to other elements in a circuit design, positioning information, feature size information, interconnection information, or other information representing a physical property of a semiconductor device.

The design computer614may be configured to transform the design information, including the circuit design information622, to comply with a file format. To illustrate, the file formation may include a database binary file format representing planar geometric shapes, text labels, and other information about a circuit layout in a hierarchical format, such as a Graphic Data System (GDSII) file format. The design computer614may be configured to generate a data file including the transformed design information, such as a GDSII file626that includes information describing the dual write wordline memory cell100ofFIG. 1, the array of dual write wordline memory cells of memory device200ofFIG. 2, or the dual write wordline memory cell502ofFIG. 5, or any combination thereof, in addition to other circuits or information. To illustrate, the data file may include information corresponding to a system-on-chip (SOC) that includes the dual write wordline memory cell100ofFIG. 1, the array of dual write wordline memory cells of memory device200ofFIG. 2, or the dual write wordline memory cell502ofFIG. 5and that also includes additional electronic circuits and components within the SOC.

The GDSII file626may be received at a fabrication process628to manufacture the dual write wordline memory cell100ofFIG. 1, the array of dual write wordline memory cells of memory device200ofFIG. 2, or the dual write wordline memory cell502ofFIG. 5, or any combination thereof, according to transformed information in the GDSII file626. For example, a device manufacture process may include providing the GDSII file626to a mask manufacturer630to create one or more masks, such as masks to be used with photolithography processing, illustrated as a representative mask632. The fabrication process628may include a processor634coupled to a memory635. The mask632may be used during the fabrication process628to generate one or more wafers633that may be tested and separated into dies, such as a representative die636. The die636includes a circuit including a device that includes the dual write wordline memory cell100ofFIG. 1, the array of dual write wordline memory cells of memory device200ofFIG. 2, or the dual write wordline memory cell502ofFIG. 5, or any combination thereof.

The die636may be provided to a packaging process638where the die636is incorporated into a representative package640. For example, the package640may include the single die636or multiple dies, such as a system-in-package (SiP) arrangement. The package640may be configured to conform to one or more standards or specifications, such as Joint Electron Device Engineering Council (JEDEC) standards.

Information regarding the package640may be distributed to various product designers, such as via a component library stored at a computer646. The computer646may include a processor648, such as one or more processing cores, coupled to a memory650. A printed circuit board (PCB) tool may be stored as processor executable instructions at the memory650to process PCB design information642received from a user of the computer646via a user interface644. The PCB design information642may include physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device corresponding to the package640including the dual write wordline memory cell100ofFIG. 1, the array of dual write wordline memory cells of memory device200ofFIG. 2, or the dual write wordline memory cell502ofFIG. 5, or any combination thereof.

The computer646may be configured to transform the PCB design information642to generate a data file, such as a GERBER file652with data that includes physical positioning information of a packaged semiconductor device on a circuit board, as well as layout of electrical connections such as traces and vias, where the packaged semiconductor device corresponds to the package640including the dual write wordline memory cell100ofFIG. 1, the array of dual write wordline memory cells of memory device200ofFIG. 2, or the dual write wordline memory cell502ofFIG. 5, or any combination thereof. In other embodiments, the data file generated by the transformed PCB design information may have a format other than a GERBER format.

The GERBER file652may be received at a board assembly process654and used to create PCBs, such as a representative PCB656, manufactured in accordance with the design information stored within the GERBER file652. For example, the GERBER file652may be uploaded to one or more machines to perform various steps of a PCB production process. The PCB656may be populated with electronic components including the package640to form a representative printed circuit assembly (PCA)658.

The PCA658may be received at a product manufacture process660and integrated into one or more electronic devices, such as a first representative electronic device662and a second representative electronic device664. As an illustrative, non-limiting example, one or more of the electronic devices662and664may be remote units such as mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. As another illustrative, non-limiting example, the first representative electronic device662, the second representative electronic device664, or both, may be selected from the group of a tablet, a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the dual write wordline memory cell100ofFIG. 1, the array of dual write wordline memory cells of memory device200ofFIG. 2, or the dual write wordline memory cell502ofFIG. 5, or a system having a dual write wordline memory cell, is integrated. AlthoughFIG. 6illustrates remote units according to teachings of the disclosure, the disclosure is not limited to these illustrated units. Embodiments of the disclosure may be suitably employed in any device that includes active integrated circuitry including memory and on-chip circuitry.

A device that includes the dual write wordline memory cell100ofFIG. 1, the array of dual write wordline memory cells of memory device200ofFIG. 2, or the dual write wordline memory cell502ofFIG. 5, or any combination thereof, may be fabricated, processed, and incorporated into an electronic device, as described in the manufacturing process600. One or more aspects of the embodiments disclosed with respect toFIGS. 1-6may be included at various processing stages, such as within the library file612, the GDSII file626, and the GERBER file652, as well as stored at the memory610of the research computer606, the memory618of the design computer614, the memory650of the computer646, the memory of one or more other computers or processors (not shown) used at the various stages, such as at the board assembly process654, and also incorporated into one or more other physical embodiments such as the mask632, the die636, the package640, the PCA658, other products such as prototype circuits or devices (not shown), or any combination thereof. Although various representative stages of production from a physical device design to a final product are depicted, in other embodiments fewer stages may be used or additional stages may be included. Similarly, the manufacturing process600may be performed by a single entity or by one or more entities performing various stages of the manufacturing process600.