Mounting table and plasma processing apparatus

A mounting table for use in a plasma processing apparatus, on which a substrate is mounted, includes: a conductive member connected to a high frequency power supply and a high frequency power supply; a dielectric layer embedded in a central portion on an upper surface of the conductive member; and an electrostatic chuck mounted on the dielectric layer. Further, the electrostatic chuck is connected to a high voltage DC power supply and includes an electrode film satisfying following conditions: δ/z≧85 (where δ=(ρv/(μπf))1/2) and, a surface resistivity of the substrate>a surface resistivity of a central portion of the electrode film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Japanese Patent Application No. 2008-245722, filed on Sep. 25, 2008, the entire contents of which are hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to a mounting table for mounting thereon a substrate which is subjected to a plasma processing, and a plasma processing apparatus having the mounting table, and more particularly, to a mounting table in which a dielectric layer is embedded.

BACKGROUND OF THE INVENTION

In a process of manufacturing a semiconductor device, a plasma process, such as dry etching or ashing, is performed on a semiconductor wafer by using a plasma generated from a process gas. In a plasma processing apparatus performing the plasma process, for example, a pair of parallel electrodes, each having a plate shape, are positioned in parallel one above the other. High frequency power is applied between the pair of parallel plates to generate a plasma from a process gas. When the plasma process is carried out, the wafer is mounted on a lower electrode serving as a mounting table.

With an increasing demand for a plasma which has low ion energy and high electron density, high frequency power applied between the electrodes tends to have a very high frequency, e.g., 100 MHz, compared to conventional frequencies of, e.g., less than 20 MHz. However, it has been observed that if the frequency of the applied high frequency power rises, an electric field is strengthened at a space above the center of the surface of the electrode, i.e. the center of the wafer, but is weakened at a space above a peripheral portion of the surface of the electrode. Such non-uniform distribution in electric field may cause a non-uniform electron density in the plasma, so that, e.g., etching rate may vary depending on a position within the wafer in dry etching using ions. Thus, a problem may occur in that satisfactory in-plane uniformity can not be obtained in dry etching.

In order to cope with this problem, there is disclosed a plasma processing apparatus, which can make the electric field strength distributed uniformly and improve in-plane uniformity in a plasma process by embedding a dielectric layer made of, e.g. a ceramic, at the central of a top surface region of the lower electrode, i.e., mounting table (see, e.g., Japanese Patent Laid-open Application No. 2004-363552 and corresponding U.S. Patent Application Publication No. 2005/0276928 A1)

As shown inFIG. 10A, when high frequency power is applied from a high frequency power supply82to a lower electrode81in a plasma processing apparatus80, a high frequency current flows along a surface of the lower electrode81to an upper part thereof by the skin effect, and then flows through a wafer W toward the central portion thereof. At this time, a part of the current leaks from the central portion of the wafer to the lower electrode81and then flows outward inside the lower electrode81. Here, the high frequency current may more deeply penetrate into the portion of the lower electrode81at which a dielectric layer83is embedded than the other portions of the lower electrode81; and accordingly, a hollow cylindrical resonance of TM mode is generated at the central portion of the lower electrode81. Consequently, the electric field strength can be lowered at a space above the central portion of the wafer W, to thereby make the electric field strength uniformly distributed at the space above the wafer W.

Since a plasma process is normally conducted under a depressurized atmosphere, an electrostatic chuck84is used to firmly mount the wafer W in the plasma processing apparatus80as shown inFIG. 10B. A conductive electrode film85is interposed between a lower member and an upper member, which are made of a dielectric material, e.g., alumina, in the electrostatic chuck84. During a plasma processing, high voltage DC power is supplied from a high voltage DC power supply86to the electrode film85to generate a coulomb force on a surface of the upper member of the electrostatic chuck84, whereby the wafer W is electrostatically adsorbed and fixed.

Each component of the plasma processing apparatus80can be treated as a component of an electric circuit for a high frequency current. Further, the wafer W is formed of a semiconductor such as silicon, and thus, the wafer W is also considered as a component of the electric circuit. Since the wafer W is mounted in parallel with the electrode film85when the wafer W is electrostatically attracted to the electrostatic chuck84, the wafer W and the electrode film85are considered to serve as resistors arranged in parallel in the electric circuit.

As a consequence, the value of a high frequency current flowing through the wafer W is dependent on a resistance of the wafer W and a resistance of the electrode film85. For instance, when the resistance of the electrode film85is larger than that of the wafer W, high frequency current mainly flows from a peripheral portion to the central portion of the wafer W (seeFIG. 11A). In such a case, a large potential difference occurs between the peripheral portion of the wafer W and the central portion of the wafer W as shown inFIG. 11B, so that a gate oxide film87is charged up and deteriorated.

Further, when the resistance of the electrode film85is very small, the high frequency current leaking from the central portion of the wafer W to the lower electrode81side can readily flow through the electrode film85, and thus the high frequency current can not penetrate deep into the central portion. As a consequence, a hollow cylindrical resonance of TM mode is not produced and the electric field strength is non-uniformly distributed, which causes electron density of a plasma to be increased in a space above the central portion of the wafer W. Accordingly, a DC-like current flows between the central portion and the peripheral portion of the wafer W. This case also has the same problem as that described above in that the gate oxide film87of semiconductor devices disposed on the wafer W is charged up and deteriorated.

SUMMARY OF THE INVENTION

In view of the above, the present invention provides a mounting table and a plasma processing apparatus capable of preventing deterioration of an insulation film of semiconductor devices disposed on a substrate.

In accordance with a first aspect of the invention, there is provided a mounting table for use in a plasma processing apparatus, on which a substrate is mounted, including: a conductive member connected to a high frequency power supply for generating a plasma and a high frequency power supply for attracting ions; a dielectric layer embedded in a central portion on an upper surface of the conductive member; and an electrostatic chuck mounted on the dielectric layer, wherein the electrostatic chuck is connected to a high voltage DC power supply and includes an electrode film satisfying the following conditions: δ/z≧85 (where δ=(ρv/(μπf))1/2) and, a surface resistivity of the substrate>a surface resistivity of a central portion of the electrode film, where z refers to a thickness of the electrode film; δ, to a skin depth of the electrode film with respect to high frequency power supplied from the high frequency power supply for generating a plasma; f, to a frequency of high frequency power supplied from the high frequency power supply for generating a plasma; π, to the circular constant; μ, to a permeability of the electrode film; and ρv, to a resistivity of the electrode film.

In accordance with a second aspect of the present invention, there is provided a mounting table for use in a plasma processing apparatus, on which a substrate is mounted, including: a conductive member connected to a high frequency power supply for generating a plasma and a high frequency power supply for attracting ions; a dielectric layer embedded in a central portion on an upper surface of the conductive member; and an electrostatic chuck mounted on the dielectric layer, wherein the electrostatic chuck is connected to a high voltage DC power supply and includes an electrode film satisfying following conditions: 115Ω/□≦ρsand, a surface resistivity of the substrate>a surface resistivity of a central portion of the electrode film, where ρs: a surface resistivity of the electrode film.

In accordance with a third aspect of the present invention, there is provided a plasma processing apparatus having a mounting table on which a substrate is mounted, the mounting table including: a conductive member connected to a high frequency power supply for generating a plasma and a high frequency power supply for attracting ions; a dielectric layer embedded in a central portion on an upper surface of the conductive member; and an electrostatic chuck mounted on the dielectric layer, wherein the electrostatic chuck is connected to a high voltage DC power supply and includes an electrode film satisfying the following conditions: δ/z≧85 (where δ=(ρv/(μπf))1/2) and, a surface resistivity of the substrate>a surface resistivity of a central portion of the electrode film, where z refers to a thickness of the electrode film; δ, to a skin depth of the electrode film with respect to high frequency power supplied from the high frequency power supply for generating a plasma; f, to a frequency of high frequency power supplied from the high frequency power supply for generating a plasma; π, to the circular constant; μ, to a permeability of the electrode film; and ρv, to a resistivity of the electrode film.

In accordance with a fourth aspect of the present invention, there is provided a plasma processing apparatus having a mounting table on which a substrate is mounted, the mounting table including: a conductive member connected to a high frequency power supply for generating a plasma and a high frequency power supply for attracting ions; a dielectric layer embedded in a central portion on an upper surface of the conductive member; and an electrostatic chuck mounted on the dielectric layer, wherein the electrostatic chuck is connected to a high voltage DC power supply and includes an electrode film satisfying the following conditions: 115Ω/□≦ρsand, a surface resistivity of the substrate>a surface resistivity of a central portion of the electrode film, where ρs: a surface resistivity of the electrode film.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings which form a part hereof.

FIG. 1is a cross sectional view schematically illustrating a configuration of a plasma processing apparatus having a mounting table in accordance with an embodiment of the present invention. The plasma processing apparatus is configured to perform plasma etching, for example, RIE (Reactive Ion Etching), or ashing on a semiconductor wafer (substrate) having a diameter of, e.g., 300 mm.

Referring toFIG. 1, the plasma processing apparatus10includes a processing vessel11formed of, e.g., a vacuum chamber, a mounting table12supported by a supporting case disposed on a central part of the bottom wall of the processing vessel11, and an upper electrode13disposed above and in parallel with the mounting table12.

The processing vessel11has a cylindrical upper chamber11ahaving a smaller diameter and a cylindrical lower chamber11bhaving a larger diameter chamber. The upper chamber11aand the lower chamber11bcommunicate with each other, and the overall processing vessel11is configured to be airtightly sealed. The mounting table12and the upper electrode13are accommodated in the upper chamber11a, and the supporting case14that supports the mounting table12and has pipes for a coolant and a backside gas therein is disposed in the lower chamber11b.

An exhaust port15is prepared at the bottom of the lower chamber11band an exhaust system17is connected to the exhaust port15via an exhaust pipe16. The exhaust system17includes, e.g., an APC (Adaptive Pressure Control) valve, a DP (Dry Pump) and TMP (Turbo Molecular Pump) (all not shown), which are controlled by a signal from a controller (not shown) so that the whole inner space of the processing vessel11is vacuum exhausted to maintain a desired vacuum level. Further, a transfer port18for transferring a wafer W is provided at a side wall of the upper chamber11ato be opened and closed by a gate valve19. The upper chamber11aand the lower chamber11bare formed of a conductive member such as aluminum and grounded.

The mounting table12includes a lower electrode20(conductive member), a dielectric layer21, and an electrostatic chuck22. The lower electrode20has a table shape formed of a conductive member, such as aluminum, to generate a plasma. The dielectric layer21is formed of a dielectric material, such as a ceramic, and is embedded in a central upper part of the lower electrode20to make the electric field strength uniformly distributed in a processing space as described later. The electrostatic chuck22electrostatically adsorbs and fixes the wafer W on a mounting surface. The lower electrode20, the dielectric layer21, and the electrostatic chuck22are disposed in the mounting table12in that order. Further, the lower electrode20is secured on a supporting table23disposed on the supporting case14via an insulation member24and is fully electrically isolated from the processing vessel11.

The lower electrode20has a coolant flow path25through which a coolant flows. When a coolant flows through the coolant flow path25, the lower electrode20is cooled so that the wafer W mounted on a mounting surface of the electrostatic chuck22is cooled to a desired temperature.

The electrostatic chuck22is formed of a dielectric material and contains a conductive electrode film37therein. The electrode film37is formed of, for example, an electrode material produced by mixing molybdenum carbide (MoC) with Alumina (Al2O3). The electrostatic chuck22has a circular plate shape similar to the wafer W to electrostatically adsorb the wafer W securely, and accordingly, the electrode film37contained in the electrostatic chuck22also has the shape of a circular plate. Further, the electrode film37is configured such that the surface resistivity of the central portion37ais smaller than that of a peripheral portion37b, as will be described later. A high voltage DC power supply42is connected to the electrode film37, and high voltage DC power supplied to the electrode film37generates a coulomb force between the mounting surface of the electrostatic chuck22and the wafer W to electrostatically adsorb and fix the wafer W.

Further, the electrostatic chuck22has a through hole26for discharging a backside gas to raise a heat transfer rate between the mounting surface and a rear surface of the wafer W. The through hole26communicates with a gas flow path27provided in the lower electrode20. A backside gas, such as helium (He), which has been supplied from a gas supplier (not shown) via the gas flow path27, is discharged through the through hole26.

In the lower electrode20, a first high-frequency power supply28(high frequency power supply for generating a plasma) for supplying high frequency power whose frequency is, for example, 40 MHz or more, and a second high-frequency power supply29(high frequency power supply for attracting ions) for supplying high frequency power whose frequency is, for example, 13.56 MHz or less, which is lower than that of the first high-frequency power supply28, are connected to each other via matching units (MUs)30and31. High frequency power supplied from the first high-frequency power supply28generates a plasma from a processing gas as described later and high frequency power supplied from the second high-frequency power supply29supplies bias power to the wafer W to draw ions from the plasma to the wafer W.

Further, a focus ring32is arranged at an outer peripheral portion on the top surface of the lower electrode20to surround the electrostatic chuck22. The focus ring32expands a plasma in a processing space to wider than a space directly above the wafer W, to enhance the uniformity of etching rate in the surface of the wafer W.

A baffle plate33is disposed outside of a lower part of the supporting table23to surround same. By the baffle plate33, a processing gas flows from the upper chamber11ato the lower chamber11bthrough a gap provided between the baffle plate33and a wall portion of the upper chamber11a. Namely, the baffle plate33serves as a rectifying plate for rectifying flow of the process gas and prevents a plasma from leaking to the lower chamber11bfrom the processing space to be described later.

In addition, the upper electrode13further includes a ceiling electrode plate34formed of a conductive material contacted with an inner surface of the upper chamber11a, an electrode plate support35that supports the ceiling electrode plate34, and a buffer chamber36disposed below the electrode plate support35. One end of a gas inlet pipe38is connected to the buffer chamber36and the other end thereof is connected to a processing gas supply source39. The processing gas supply source39includes a control unit (not shown) for controlling the amount of supplying the processing gas. Further, a plurality of gas supply holes40is provided through the ceiling electrode plate34to allow the buffer chamber36to communicate with the upper chamber11a.

Since the processing gas supplied from the processing gas supply source39to the buffer chamber36is dispersedly supplied through the gas supply holes40in the upper electrode13, the upper electrode13serves as a shower head for the processing gas. In addition, since the upper electrode13is fixed onto an inner wall of the upper chamber11a, a conductive path is formed between the upper electrode13and the processing vessel11.

Two multi-pole ring magnets41aand41bare respectively arranged above and beneath the gate valve19around the upper chamber11aof the plasma processing apparatus10. In the multi-pole ring magnets41aand41b, a plurality of anisotropic segment columnar magnets (not shown) are accommodated in a casing (not shown) of a ring-shaped magnetic material and are arranged in the casing, such that a magnetic pole of one of two neighboring anisotropic segment columnar magnets is opposite to that of the other. Accordingly, magnetic force lines are created between two neighboring segment columnar magnets, and a magnetic field is generated around the processing space located between the upper electrode13and the lower electrode20, so that a plasma is trapped in the processing space by the magnetic field. Further, the plasma processing apparatus10may be configured not to have the multi-pole ring magnets41aand41b.

When RIE or ashing is performed on the wafer W in the plasma processing apparatus10, the pressure in the processing vessel11is adjusted to have a desired vacuum level and a processing gas is introduced into the upper chamber11a. And then the high frequency powers are supplied from the first high-frequency power supply28and the second high-frequency power supply29to generate a plasma from the processing gas. Accordingly, ions contained in the plasma are drawn to the wafer W. To generate a plasma that has low ion energy and high electron density, the high frequency power of 40 MHz or more may be supplied from the first high-frequency power supply28. Further, the high frequency power of 13.56 MHz or less may be supplied from the second high-frequency power supply29so that the ions contained in the plasma can be securely drawn toward the wafer W. The high frequency electric powers supplied from the first high-frequency power supply28and the second high-frequency power supply29flow through a path passing from the lower electrode20to the ground through the plasma, the upper electrode13, a wall portion of the processing vessel11in that order.

In the plasma processing apparatus10, the high frequency power supplied from the first high-frequency power supply28has a high frequency (40 MHz or more) which tends to cause the electric field strength to be greater at a portion directly above the central portion of the wafer W in the processing space. To make the electric field strength uniformly distributed in the processing space by removing such tendency, the plasma processing apparatus10further includes the dielectric layer21on the lower electrode20. The existence of the dielectric layer21allows a high frequency current from the first high-frequency power supply to penetrate from the central portion of the wafer W deeply to the dielectric layer21on the lower electrode20via the electrostatic chuck22. As a consequence, a hollow cylindrical resonance of TM mode occurs at the central portion of the lower electrode20, so that the electric field strength can be uniformly distributed in the processing space.

In the plasma processing apparatus10, the first high-frequency power supply28, the lower electrode20, the dielectric layer21, the electrostatic chuck22, the electrode film37(central portion37aand peripheral portion37b), the wafer W, and the plasma PZ (seeFIG. 2A) generated in the processing space constitute an equivalent circuit43as shown inFIG. 2B. Further, the second high-frequency power supply29and the other components shown inFIG. 3Aconstitute an equivalent circuit44as shown inFIG. 3B.

Referring toFIGS. 2B and 3B, a capacitance CIis a equivalent capacitance of the dielectric layer21; a capacitance Cc1is a capacitance between the lower electrode20and the electrostatic chuck22; a capacitor Cc2is a capacitance between the electrostatic chuck22and the wafer W; a capacitor CTis a capacitance of a gate oxide film; a capacitor Cpis a capacitance of the plasma PZ; a resistance Rcis a resistance of the plasma PZ, a resistor Rwis a resistance of the wafer W; a resistor REIis a resistance of the central portion37aof the electrode film37; and a resistor REOis a resistance of the peripheral portion37bof the electrode film37.

Since the dielectric layer21is present only around the central portion of the lower electrode20in the equivalent circuits43and44shown inFIGS. 2B and 3B, it is considered that there exist a circuit43a(44a) corresponding to the central portion of the lower electrode20and a circuit43b(44b) corresponding to the peripheral portion of the lower electrode20, wherein the two circuits43aand43b(44aand44b) are bridged by the resistance Rw of the wafer W, and the resistances REIand REOof the electrode film37. Further, since the wafer W and the electrode film37are disposed in parallel with each other when the wafer W is mounted on the mounting surface of the electrostatic chuck22, the resistance Rw is arranged in electrically parallel with the resistances REIand REO.

When the resistance RE(particularly, REO) of the electrode film37is small when a high-power, high frequency power is supplied from the first high-frequency power supply28, a high frequency current, which propagate from the central portion of the wafer W to the electrostatic chuck22in a thickness direction, flows from the central portion37aof the electrode film37to the peripheral portion37binstead of penetrating into the dielectric layer21, so that the high frequency current hardly reaches the dielectric layer21. Resultantly, it is difficult to generate an electric field which originates from the high frequency current penetrating into the dielectric layer21and penetrates through the electrode film37. This phenomenon will be described below.

In this embodiment, a skin depth δ of the electrode film37is employed as an index that indicates a degree of reduction of an electric field penetrating into the electrode film37. The skin depth δ means a depth by which an electric field penetrating into the electrode film37is reduced as much as 1/e. As the skin depth δ increases, the electric field is difficult to be reduced and can easily penetrate into the electrode film37, whereas as the skin depth δ decreases, the electric field is easily reduced and it is difficult for the electric field to penetrate into the electrode film37. The skin depth δ can be defined by Eq. 1 as follows:
δ=(2ρv/(μω))1/2=(ρv/(μπf))1/2Eq. 1
where μ refers to a permeability (H/m) of the electrode film37; ω, to 2πf (n being the circular constant, and f being the frequency (Hz) of the high frequency power supplied from the first high-frequency power supply28); and ρv, to a resistivity (Ω·m) of an electrode material constituting the electrode film37.

Further, an electric field E generated at the electrode film37can be expressed by Eq. 2 based on Maxwell's equations:
E=E0·exp(−iωt)·exp(iz/δ)·exp(−z/δ)  Eq. 2,
where z refers to the thickness of the electrode film37; and E0refers to a strength of an electric field incident onto the electrode film37.

That is, a penetration ratio “E/E0” by which an electric field of high frequency power supplied from the first high-frequency power supply28penetrates through the electrode film37is proportional to “exp (−z/δ)” as represented in Eq. 3:
E/E0∝exp(−z/δ)  Eq. 3

As the value “z/δ” is close to “0” in Eq. 3, the penetration ratio of the electric field approaches 1.0 (100%), and as “δ” is smaller, the penetration ratio of the electric field is reduced. Here, the resistance REof the electrode film37being small means the resistivity ρvof the electrode film37is small. Therefore, as the resistance REis smaller, the skin depth δ represented as “(ρv/(μπf))1/2” is reduced, so that it becomes difficult to generate an electric field that penetrates through the electrode film37.

If an electric field penetrating through the electrode film37is less generated, a weaker hollow cylindrical resonance of TM mode occurs in the central portion of the lower electrode20, and the electric field strength in a space directly above the central portion of the wafer W (hereinafter, referred to as “central space”) in the processing space becomes larger than the electric field strength in a space directly above the peripheral portion of the wafer W in the processing space, resulting in the increased electron density at the central space. As a result, the etching rate distribution becomes non-uniform in the surface of the wafer W.

Moreover, the non-uniformity in distribution of electron density of a plasma causes a DC-like current (indicated by a dashed-line arrow inFIG. 2B) to be created along a circuit consisting of the resistance Rc, the capacitance Cp, the capacitance CT, and the resistance Rwin the equivalent circuit43.

When the DC-like current flows through the wafer W, the gate oxide film (insulation film) of the semiconductor device (hereinafter, simply referred to as “device”) placed on the wafer W may be charged up and thus can be damaged and deteriorated.

To make the etching rate uniformly distributed an the surface of the wafer W and prevent the gate oxide film of the device from being deteriorated in case that high-power, high frequency power is supplied from the first high-frequency power supply28, it is needed to generate an electric field penetrating through the electrode film37by suppressing a high frequency current from the first high-frequency power supply28to flow through the electrode film37and allowing the high frequency current to penetrate into the dielectric layer21. For this purpose, it may be appropriate to increase δ/z in the Eq. 3. To increase δ/z, it may be appropriate to increase the skin depth δ. Since the skin depth δ is represented as “(ρv/(μπf))1/2” as described above, it may be appropriate to increase the resistance REof the electrode film37by using a conductive material with high resistivity ρvto increase the skin depth δ if the frequency is constant. Further, as the frequency of the high frequency power is higher, the skin depth δ is smaller (δ∝(1/ω)=(½ πf)). Therefore, it may be appropriate to use an electrode material with a larger resistivity ρvas the material constituting the electrode film37when the frequency of the high frequency power is adapted to be higher.

A plurality of electrode films37, each having a different value of δ/z (and resistance RE) from that of the others, were prepared by the inventors to find δ/z (and resistance RE) that may prevent the gate oxide film of the device from being deteriorated due to a charge-up damage and make the etching rate uniformly distributed on the surface of the wafer W by preventing the non-uniformity in electron density distribution of the plasma in the processing space. And, ashing was performed on a photoresist of each of various wafers W in the plasma processing apparatus10by using the electrode film37thus prepared, the etching rate distribution of the photoresist on the surface of each wafer W was observed, and the results were depicted as a graph shown inFIG. 4. Hereinafter, the resistance of the electrode film37is represented by the surface resistivity ρsto remove effects by the thickness of the electrode film37from the resistance RE. The surface resistivity ρsrefers to a resistance per unit area represented in Eq. 4, and is determined based on a property value (resistivity ρv) of the electrode material constituting the electrode film37and the thickness of the electrode film37.
ρs=ρv/z(Ω/□)  Eq. 4,
where (δ/z and ρs) of each electrode film37used herein was (7518, 8.9×105Ω/□), (6711, 2.67×105Ω/□), (297, 1740Ω/□), (195, 750Ω/□), (124, 304Ω/□), (103, 208Ω/□), (92, 166Ω/□), (85, 115Ω/□), and (47, 35Ω/□).

In the ashing process, a single gas of O2was introduced as the processing gas into the upper chamber11aby a flow rate of 100 sccm, and the high frequency power supplied from the first high-frequency power supply28and frequency thereof were set 2000 W, and 100 MHz, no high frequency power was supplied from the second high-frequency power supply29.

In the graph depicted inFIG. 4, the horizontal axis refers to a distance from the center of the wafer W and the vertical axis refers to an etching rate (nm/minute). In addition, the dashed-line refer to the case where (δ/z, surface resistivity)=(47, 35Ω/□) and solid lines refer to the cases where δ/z≧85 and surface resistivity≧115Ω/□.

It was found in the graph depicted inFIG. 4that the etching rate distribution can be nearly uniform on the surface of the wafer W in case that δ/z is set to be equal to or more than 85 or ρsis 115Ω/□ or more. Further, it is considered that the distribution of electron density of the plasma is almost uniform in the processing space from a fact that the etching rate is nearly uniformly distributed. From this view, it was found that if δ/z is adapted to be equal to or more than 85 or ρsis 115Ω/□ or more, deterioration of the gate oxide film due to a charge-up damage may be substantially prevented in the device. In this embodiment, δ/z is set to be equal to or more than 85 or ρsis set to be 115Ω/□ or more based on observations of the above-described etching rate distribution.

Further, the capacitance CIof the dielectric layer21is present in the electric circuit44acorresponding to the central portion of the lower electrode20. Therefore, when high-power, high frequency power is supplied from the second high-frequency power supply29in the equivalent circuit44, a high frequency current from the second high-frequency power supply29primarily flows not through the electric circuit44abut through the electric circuit44bcorresponding to the peripheral portion of the lower electrode20and then flows back to the electric circuit44a, as indicated by a thick solid line arrow inFIG. 3B.

Here, the resistance REof the electrode film37is set to be large to prevent the non-uniformity in distribution of electron density of the plasma in the processing space in case that high-power, high frequency power is supplied from the first high-frequency power supply28as described above. Therefore, the resistance REof the electrode film37can be larger than the resistance Rwof the wafer W. If the resistance RE(REI, REO) of the electrode film37is set to be larger than the resistance Rwof the wafer W, the high frequency current can flow back to the electric circuit44aprimarily not through the electrode film37but through the wafer W from the peripheral portion to the central portion. At this time, a large voltage difference is generated from the peripheral portion of the wafer W toward the central portion of the wafer W, and thus the charge balance of the gate oxide film (insulation film) collapses on the surface of the wafer W. As a consequence, the gate oxide film may be charged up in the device placed on the wafer W, thus to be damaged and deteriorated.

To prevent the deterioration of the gate oxide film of the device caused by charge-up damage when a high-power, high frequency power is supplied from the second high-frequency power supply29, it is needed to prevent the high frequency current from the second high-frequency power supply29from flowing from the peripheral portion of the wafer W to the central portion thereof. For this purpose, it may be appropriate to make the high frequency current flow not through the central portion of the wafer W but through the central portion of the electrode film37.

To allow the high frequency current to flow not through the central portion of the wafer W but through the central portion of the electrode film37, it may be appropriate to make the resistance REIof the central portion37aof the electrode film37smaller than the resistance Rwof the central portion of the wafer W, so that it becomes difficult for the high frequency current flowing through the peripheral portion of the wafer W to flow through the central portion of the wafer W. In view of this, the surface resistivity of the central portion37aof the electrode film37is set smaller than that of the wafer W in this embodiment.

Accordingly, as shown inFIG. 5A, the high frequency current flowing through the peripheral portion of the wafer W flows not through the central portion of the wafer W but through the central portion37aof the electrode film37. In such a case, the electric potential at the wafer W is changed in the peripheral portion but not in the central portion as shown inFIG. 5B. As a result, any large voltage difference is not generated from the peripheral portion of the wafer W toward the central portion of the wafer W, so that it can be possible to prevent deterioration of the gate oxide film of the device caused by a charge-up damage.

Further, since the resistance REof the electrode film needs be set large to prevent the non-uniformity in distribution of electron density of the plasma in the processing space when the high frequency power is supplied from the first high-frequency power supply28as described above, at least the resistance REOof the peripheral portion37bof the electrode film37is set to be larger than the resistance Rwof the peripheral portion of the wafer W. Accordingly, the surface resistivity of the central portion37abecomes smaller than that of the peripheral portion37bin the electrode film37.

A potential distribution was simulated by the inventors with respect to the surface resistivity (2×103Ω/□, 2×102Ω/□, 2×10Ω/□, 2Ω/□) in a plurality of central portions37ato find the surface resistivity in the central portion37aof the electrode film37which enables a high frequency current may flow not through the central portion of the wafer W but through the central portion of the electrode film37. In this case, the surface resistivity of the wafer W was 26Ω/□, the surface resistivity of the peripheral portion37bof the electrode film37was 2×105Ω/□, and the frequency of the high frequency power supplied from the second high-frequency power supply29was 2 MHz. In comparison, another potential distribution was simulated with respect to a case where the surface resistivity of the entire surface of the electrode film37is 2×103Ω/□.

Further, to find the optimal location of a boundary between the peripheral portion37band the central portion37ain the electrode film37, the potential distribution was also simulated with respect to for the cases of differing locations of a plurality of boundaries, i.e., a case where a boundary is positioned about 10 mm to a periphery of the lower electrode20from a peripheral end of the dielectric layer21; a case where a boundary is positioned at the same location as that of the peripheral end of the dielectric layer21; and a case where a boundary is positioned about −10 mm to the periphery of the lower electrode20from the peripheral end of the dielectric layer21.

FIGS. 6A to 6Cdepict results of the potential distribution simulated on the wafer W when the high frequency power supplied from the second high-frequency power supply29has a frequency of 2 MHz.FIG. 6Adepicts a result of the potential distribution simulated in a case where the boundary is positioned about −10 mm closer to the periphery of the lower electrode20from the peripheral end of the dielectric layer21,FIG. 6Bdepicts a result of the potential distribution simulated in a case where the boundary is positioned at the same location as that of the peripheral end of the dielectric layer21, andFIG. 6Cdepicts a result of the potential distribution simulated in a case where the boundary is positioned about +10 mm closer to the periphery of the lower electrode20from the peripheral end of the dielectric layer21.

In each graph, when the surface resistivity of the central portion37aof the electrode film37is 2×103Ω/□, the result is marked as “♦”, when the surface resistivity of the central portion37aof the electrode film37is 2×102Ω/□, the result is marked as “▪”, when the surface resistivity of the central portion37aof the electrode film is 2×10Ω/□, the result is marked as “▴”, when the surface resistivity of the central portion37aof the electrode film37is 2Ω/□, the result is marked as “●”, and when the surface resistivity of the entire surface of the electrode film37is 2×103Ω/□, the result is marked as “×”.

In comparison with the graphs depicted inFIGS. 6A to 6C, it was found that in the case where the boundary is positioned about −10 mm to the periphery of the lower electrode20from the peripheral end of the dielectric layer21(FIG. 6A) or in the case where the boundary is positioned at the same location as that of the peripheral end of the dielectric layer21(FIG. 6B), a voltage difference from the peripheral portion of the wafer W toward the central portion thereof is still large.

However, in the case where the boundary is positioned about 10 mm to the periphery of the lower electrode20from the peripheral end of the dielectric layer21(FIG. 6C), if the surface resistivity of the central portion37ais 2×102Ω/□ or less, particularly 2×10Ω/□ or less, the high frequency current flows not through the central portion of the wafer W but through the central portion of the electrode film37, so that the voltage difference from the peripheral portion of the wafer W toward the central portion becomes small.

Further, a potential distribution was simulated by the inventors when the high frequency power supplied from the second high-frequency power supply29has a frequency of 13 MHz in a manner similar to the case the high frequency power supplied from the second high-frequency power supply29has a frequency of 2 MHz.

FIG. 7depicts a result of a potential distribution simulated in the wafer W when high frequency power supplied from the second high-frequency power supply29has a frequency of 13 MHz, wherein when the surface resistivity of the central portion37aof the electrode film37is 2×103Ω/□, the result is marked as “♦”, when the surface resistivity of the central portion37ais 2×102Ω/□, the result is marked as “▪”, when the surface resistivity of the central portion37ais 1×102Ω/□, the result is marked as “□”, when the surface resistivity of the central portion37ais 2×10Ω/□, the result is marked as “▴”, and when the surface resistivity of the central portion37ais 2Ω/□, the result is marked as “●”. In the result simulated inFIG. 7, the boundary is positioned about +10 mm closer to the peripheral portion of the lower electrode20than the peripheral end of the dielectric layer21.

It was also found inFIG. 7that when the surface resistivity of the central portion37ais 1×102Ω/□ or less, particularly 2×10Ω/□ or less, the high frequency current flows not through the central portion of the wafer W but through the central portion of the electrode film37, so that the voltage difference from the peripheral portion of the wafer W toward the central portion of the wafer W becomes small.

To prevent the deterioration of the gate oxide film caused by a charge-up damage to the device based on the results of simulation of the potential distribution, the surface resistivity of the peripheral portion37bof the electrode film37is set 2×105Ω/□ or more and the surface resistivity of the central portion37ais set 2×102Ω/□ or less, for example, 2×10Ω/□ or less, while positioning the boundary 10 mm or more closer to the peripheral portion of the lower electrode20than the peripheral end of the dielectric layer21.

Reducing the surface resistivity of the central portion37aof the electrode film37may raise concerns that the electron density of a plasma may be non-uniformly distributed in the processing space in case that high-power, high frequency power is supplied from the first high-frequency power supply28. Therefore, a simulation was performed by the inventors with respect to a strength distribution of a sheath field when high-power, high frequency power is supplied from the first high-frequency power supply28.

Even in this case, a distribution of a sheath field strength was simulated for the surface resistivity (2×103Ω/□, 2×102Ω/□, 2×10 Ω/□, 2Ω/□) of a plurality of central portions37aand a distribution of a sheath field strength was also simulated for a case where the surface resistivity of the entire surface of the electrode film37is 2×103Ω/□ for comparison.

FIG. 8depicts a graph showing a result of simulation of sheath field strength distribution when the high frequency power supplied from the first high-frequency power supply28has a frequency of 100 MHz.

In the graph depicted inFIG. 8, also, when the surface resistivity of the central portion37aof the electrode film37is 2×103Ω/□, the result is marked as “♦”, when the surface resistivity of the central portion37ais 2×102Ω/□, the result is marked as “▪”, when the surface resistivity of the central portion37ais 2×10Ω/□, the result is marked as “▴”, when the surface resistivity of the central portion37ais 2Ω/□, the result is marked as “●”, and when the surface resistivity of the entire surface of the electrode film37is 2×103Ω/□, the result is marked as “×”.

As can be seen in the graph shown inFIG. 8, although the surface resistivity of the central portion37awas changed between 2×103Ω/□ to 2Ω/□, the distribution of sheath field strength was changed only by about 4%.

FIG. 9is a graph illustrating a result of simulation of a sheath field strength distribution when high frequency power supplied from the first high-frequency power supply28has a frequency of 40 MHHz.

In the graph depicted inFIG. 9, when the surface resistivity of the central portion37aof the electrode film is 2×103Ω/□, the result is marked as “♦”, when the surface resistivity of the central portion37ais 2×102Ω/□, the result is marked as “▪”, when the surface resistivity of the central portion37ais 1×102Ω/□, the result is marked as “□”, when the surface resistivity of the central portion37ais 2×10Ω/□, the result is marked as “▴”, and when the surface resistivity of the central portion37ais 2Ω/□, the result is marked as “●”.

As can be seen in the graph shown inFIG. 9, although the surface resistivity of the central portion37awas changed between 2×103Ω/□ to 2Ω/□, the distribution of sheath field strength was changed only by about 1%.

As described above, it was identified that the electron density of a plasma was not non-uniformly distributed in the processing space in case that high-power, high frequency power is supplied from the first high-frequency power supply28within a setup range for the surface resistivity of the central portion37ain this embodiment.

In the mounting table12in accordance with the embodiment, there is provided the electrostatic chuck22having the electrode film37that satisfies a condition “δ/z 85” and a condition “surface resistivity of the wafer W>surface resistivity of the central portion37aof the electrode film37”.

As the skin depth δ increases, an electric field easily penetrates into the electrode film37, so that a high frequency current is prone to pass through the electrode film37in a thickness direction thus to penetrate into the dielectric layer21.

Accordingly, if δ/z≧85, most of a high frequency current from the first high-frequency power supply28may penetrate through the electrode film37in a thickness direction without flowing through the electrode film37thus to penetrate into the dielectric layer21.

As a consequence, a hollow cylindrical resonance of TM mode may be generated so that an electron density of a plasma may be nearly uniformly distributed in the processing space. Further, since the surface resistivity of the wafer W is larger than that of the central portion37aof the electrode film37, a high frequency current from the second high-frequency power supply29flows through a peripheral portion of the wafer W and then not through a central portion of the wafer W but through the central portion37aof the electrode film37.

Accordingly, a potential at the central portion of the wafer W is not changed, so that a large voltage difference may be prevented from occurring from the peripheral portion of the wafer W toward the central portion of the wafer W. Consequently, it may be possible to prevent deterioration of the gate oxide film due to a charge-up damage to the device.

Further, in the mounting table12in accordance with the embodiment, the electrode film37satisfies a condition “115Ω/□≦ρs”.

As the surface resistivity of the electrode film37increases, it is difficult for a high frequency current to flow through the electrode film37, so that it is easy for the high frequency current to penetrate into the electrode film37in a thickness direction thus to plunge. Accordingly, if 115Ω/□≦ρs, a high frequency current from the first high-frequency power supply28mostly may pass through the electrode film37in a thickness direction to penetrate into the dielectric layer21without flowing through the electrode film37. As a consequence, a hollow cylindrical resonance of TM mode may be generated so that an electron density of a plasma may be nearly uniformly distributed in the processing space.

In the above-described mounting table12, the electrode film37satisfies a condition “surface resistivity of a peripheral portion of the electrode film37>surface resistivity of the central portion37aof the electrode film37”, so that more current flows to the central portion37aof the electrode film37rather than the peripheral portion37bof the electrode film37. That is, since energy originating from the high frequency current focuses on an upper part of the dielectric layer21, it is easy for the hollow cylindrical resonance of TM mode to occur, thus making it possible to certainly reduce the electric field strength in a space vertically facing the central portion37a(that is, central portion of the wafer W) of the electrode film37.

In the above-described mounting table12, further, a boundary between the central portion37aand the peripheral portion37bof the electrode film37is positioned 10 mm or more closer to a peripheral portion of the lower electrode20than a peripheral end of the dielectric layer21, so that a portion of the electrode film37whose surface resistivity is lower than the wafer W, is expanded and a high frequency current more actively flows through the electrode film37than through the wafer W. Accordingly, it may be possible to reduce the amount of high frequency current flowing through the wafer W, thus making it possible to prevent a large voltage difference from being generated in the wafer W. Further, more high frequency current flows to a central portion of the electrode film37located over the dielectric layer21, so that energy originating from the high frequency current focuses more on the central portion, thus making it possible to more certainly create the hollow cylindrical resonance of TM mode.

In this embodiment, the surface resistivity of the wafer W is set more than 26Ω/□. Since the surface resistivity of wafers W generally available is equal to or more than 26Ω/□, it may be possible to allow a high frequency current from the second high-frequency power supply29to certainly flow not through a central portion of the wafer W but through the central portion37aof the electrode film37with respect to wafers W generally available in the electrode film37that satisfies a condition “surface resistivity of the wafer W>surface resistivity of the central portion37aof the electrode film37”.

Although the semiconductor wafer W has been used as a substrate on which RIE or ashing is performed in the above-described embodiment, the substrate on which RIE or ashing is performed is not limited thereto. For example, an LCD (Liquid Crystal Display) or FPD (Flat Panel Display) may be used as the substrate.

In accordance with the mounting table and the plasma processing apparatus described above, there is provided an electrostatic chuck having an electrode film that satisfies a condition “δ/z≧85” and a condition “surface resistivity of substrate>surface resistivity at central portion of electrode film”. Here, δ (skin depth) refers to a thickness by which the electric field strength is reduced only by 1/e in the electrode film, wherein as δ increases, the electric field easily penetrate into the electrode film, so that a high frequency current passes through the electrode film in a thickness direction to penetrate. Accordingly, when δ/z≧85, most of a high frequency current from a high frequency power supply for generating a plasma propagates the electrode film in a thickness direction without flowing through the electrode film, and can penetrate into the dielectric layer. Consequently, a hollow cylindrical resonance of TM mode may be generated to allow the electric field strength to be uniformly distributed in a space opposite to the substrate and a DC-like current may be prevented from being generated in the substrate. Further, since the surface resistivity of substrate is larger than the surface resistivity at the central portion of the electrode film, a high frequency current from a high frequency power supply for attracting ions first flows through a peripheral portion of the substrate and then through the central portion of the electrode film but not through the central portion of the substrate. Accordingly, potential is not changed in the central portion of the substrate, and this may prevent a large potential from being generated from the peripheral portion of the substrate toward the central portion of the substrate. As a result, an insulation film may be prevented from being deteriorated in the semiconductor device placed on the substrate.

Further, it may be possible to generate a plasma that has low ion energy and high electron density.

Further, it may be possible to certainly draw ions from the plasma into the substrate placed on the mounting table.

Furthermore, the surface resistivity of the substrate is equal to or more than 26Ω/□. Since substrates commercially available generally have the surface resistivity of 26Ω/□ or more, the electrode film satisfying a condition “surface resistivity of the substrate>surface resistivity at the central portion of the electrode film” allows a high frequency current to certainly flow not through the central portion of the substrate but through the central portion of the electrode film with respect to the substrates commercially available.