Diode for adjusting pin resistance of a semiconductor device

A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.

BACKGROUND

1. Technical Field

The embodiments described herein relate to a semiconductor device, and more particularly, to a diode that can be used for adjusting a pin resistance of a semiconductor product.

2. Related Art

In a semiconductor device, an input/output circuit will often comprise a plurality of components such as an electrostatic protection circuit, an input buffer and an output buffer. Each of these components will include their respective resistance components and capacitance components. The pin resistance is then is obtained by adding the resistance component of the input/output circuit and the resistance component of the associated package. The pin capacitance is obtained by adding the capacitance component of the input/output circuit and the capacitance component of the package.

With respect to the pin resistance, the resistance of a package is as small and can often be neglected.

In order to maintain signal integrity during operation of a semiconductor circuit, a predetermined level of pin resistance is required. As a result, the minimum value and the maximum value of pin resistance are often regulated in a specification associated with the semiconductor circuit.

FIG. 1illustrates a typical example of an input circuit used in a conventional semiconductor integrated circuit. Referring toFIG. 1, it can be seen that the input circuit includes an input pad100, a first electrostatic discharge section110and a second electrostatic discharge section120for protecting an internal circuit170from static electricity generated from the input pad100, a power clamp circuit130for providing an electrostatic discharge path between a power voltage supply line Vcc and a ground voltage supply line Vss when static electricity is generated, an input buffer160for transmitting a signal, input through the input pad100to the internal circuit170, and a resistor140and a MOS transistor150for protecting the input buffer160.

During normal operation, the electrostatic discharge sections110and120and the power clamp circuit130are turned off to exert no influence on normal circuit operation. In the event that static electricity is generated between the input pad100and power pads, then discharge sections110and120will enter an operation mode and provide the electrostatic discharge path so that the input buffer160and the internal circuit170can be protected from transient electrostatic current.

Currently, a MOS transistor and a diode are widely used as the first electrostatic discharge section110and the second electrostatic discharge section120. Since a diode is significantly better in terms of electrostatic protection as function of parasitic capacitance than a MOS transistor, the diode is more appropriate for a circuit operating at a high speed, and therefore, the number of products using a diode is increasing. However, because a diode has smaller resistance and capacitance than those of a MOS transistor, the pin resistance is markedly decreases and therefore may not satisfy the specified pin resistance.

FIGS. 2aand2billustrate the structure of the first electrostatic discharge section110in a conventional semiconductor circuit.FIG. 2ais a plan view andFIG. 2bis a sectional view taken along the line A-B ofFIG. 1.

The first electrostatic discharge section110includes a P-type well111formed in the surface of a P-type semiconductor substrate, one or a plurality of N+ impurity areas112formed in the surface of the substrate within the P-type well111, one or a plurality of insulation areas113formed in the surface of the substrate to surround the respective N+ impurity areas112, and a P+ impurity area114formed in the surface of the substrate to surround the insulation areas113.

The N+ impurity areas112and the P-type well111constitute a PN diode. In the case that this diode is used as the first electrostatic discharge section110ofFIG. 1, the N+ impurity areas112are connected to the input pad100through contacts115, and the P+ impurity area114is connected to the ground voltage supply line (Vss) through contacts115.

Referring toFIG. 2b, it can be observed that the P-type well111is formed in the substrate, the plurality of N+ impurity areas112and the P+ impurity area114are formed in the P-type well111, and the insulation areas113are formed between the N+ impurity areas112and the P+ impurity area114. Further, in order to connect the input pad100and the ground voltage supply line (Vss), the contacts115are formed on the N+ impurity areas112and the P+ impurity area114.

In a conventional diode structure as described above, the contacts115are arranged in the N+ impurity areas (cathodes)112and the P+ impurity area (anode)114to have minimum pitches D1and D2permitted by an associated design rule in order to minimize the operation resistance of the diode. Also, the distance D3between the N+ impurity area112and the P+ impurity area114is set as a minimum distance permitted by the design rule.

Accordingly, when a conventional diode is laid out according to the minimum design rule, the pin resistance of a semiconductor product, which uses the diode as an electrostatic protection element, is likely to be less than regulated minimum pin resistance, since the diode parasitic resistance is small and therefore the degree to which the diode contributes to pin resistance is also small.

In particular, in order to reduce parasitic capacitance to allow high speed operation of a semiconductor product, the decrease in pin resistance will raise a serious problem, because the electrostatic discharge section cannot but be minimized.

SUMMARY

Apparatus and methods for increasing the resistance of a diode used in an input/output pad are described herein.

In one aspect, a diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.

The distance between the N-type impurity doping area and the P-type impurity doping area can be determined to be at least two times greater than a distance that is defined according to a design rule for a minimum distance between an N-type impurity doping area and a P-type impurity doping area in a corresponding product.

The contact pitch between the first contacts can be determined to be at least two times greater than a contact pitch that is defined according to a minimum contact pitch design rule in the corresponding product.

The contact pitch between the second contacts can be determined to be at least two times greater than a contact pitch that is defined according to a minimum contact pitch design rule in the corresponding product.

One N-type impurity doping area is formed to be elongate or at least two N-type impurity doping areas are formed to be parallel to one another.

In another aspect, a diode comprises an N-type well formed in a semiconductor substrate, at least one P-type impurity doping area formed in the N-type well, an isolation area formed to surround the P-type impurity doping area, an N-type impurity doping area formed to surround the isolation area, first contacts formed in the P-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the N-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the P-type impurity doping area and the N-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.

The distance between the P-type impurity doping area and the N-type impurity doping area can be determined to be at least two times greater than a distance that is defined according to a design rule for a minimum distance between a P-type impurity doping area and an N-type impurity doping area in a corresponding product.

The contact pitch between the first contacts can be determined to be at least two times greater than a contact pitch that is defined according to a minimum contact pitch design rule in the corresponding product.

The contact pitch between the second contacts can be determined to be at least two times greater than a contact pitch that is defined according to a minimum contact pitch design rule in the corresponding product.

One P-type impurity doping area can be formed to be elongate or at least two P-type impurity doping areas are formed to be parallel to one another.

In still another aspect, a diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, at least one P-type impurity doping area formed in the P-type well to be parallel to the N-type impurity doping area, at least one isolation area formed between the N-type impurity doping area and the P-type impurity doping area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.

The distance between the N-type impurity doping area and the P-type impurity doping area can be determined to be at least two times greater than a distance that is defined according to a design rule for a minimum distance between an N-type impurity doping area and a P-type impurity doping area in a corresponding product.

The contact pitch between the first contacts can be determined to be at least two times greater than a contact pitch that is defined according to a minimum contact pitch design rule in the corresponding product.

The contact pitch between the second contacts can be determined to be at least two times greater than a contact pitch that is defined according to a minimum contact pitch design rule in the corresponding product.

Some of the first contacts or some of the second contacts can have the contact pitch at least two times greater than a contact pitch that is defined according to a minimum contact pitch design rule in the corresponding product.

In still another aspect, a diode comprises an N-type well formed in a semiconductor substrate, at least one P-type impurity doping area formed in the N-type well, at least one N-type impurity doping area formed in the N-type well to be parallel to the P-type impurity doping area, at least one isolation area formed between the P-type impurity doping area and the N-type impurity doping area, first contacts formed in the P-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the N-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the P-type impurity doping area and the N-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.

The distance between the P-type impurity doping area and the N-type impurity doping area can be determined to be at least two times greater than a distance that is defined according to a design rule for a minimum distance between a P-type impurity doing area and an N-type impurity doping area in a corresponding product.

The contact pitch between the first contacts can be determined to be at least two times greater than a contact pitch that is defined according to a minimum contact pitch design rule in the corresponding product.

The contact pitch between the second contacts can be determined to be at least two times greater than a contact pitch that is defined according to a minimum contact pitch design rule in the corresponding product.

Some of the first contacts or some of the second contacts have the contact pitch at least two times greater than a contact pitch that can be defined according to a minimum contact pitch design rule in the corresponding product.

In a still further aspect, a diode can be provided wherein pin resistance can be adjusted through changing at least one of a distance between an anode and a cathode, a contact pitch of the anode, and a contact pitch of the cathode.

The distance between the anode and the cathode can be determined to be at least two times greater than a distance that is defined according to a minimum design rule in a corresponding product.

The contact pitch of the anode can be determined to be at least two times greater than a contact pitch that is defined according to a minimum contact pitch design rule in the corresponding product.

The contact pitch of the cathode can be determined to be at least two times greater than a contact pitch that is defined according to a minimum contact pitch design rule in the corresponding product.

DETAILED DESCRIPTION

FIG. 3is a layout diagram of a diode110constructed in accordance with one embodiment. The reference number110is used inFIG. 3to indicate that the diode depicted therein can be used in a similar fashion to the diode illustrated inFIG. 1and described above.

The diode110can be divided into a first region110a, which can be laid out according to a minimum design rule and a second region110b, which can be laid out to have the pitches between contacts greater than those regulated by the minimum design rule.

Still referring toFIG. 3, the diode110can include a P-type well111, which can be formed in a P-type semiconductor substrate, a first N+ impurity area (an N-type impurity doping area)112aand a second N+ impurity area112b, a first isolation area113aand a second isolation area113b, which can be formed to surround the first N+ impurity area112aand the second N+ impurity area112b, a first P+ impurity area (a P+ impurity doping area)114aand a second P+ impurity area114b, which can be formed to surround the first isolation area113aand the second isolation area113b, and contacts115, which can be formed in each of the first and second N+ impurity areas112aand112band the first and second P+ impurity areas114aand114bin a single row or a plurality of rows.

While the first region110aand the second region110bare illustrated separately and are designated by different reference numerals, it is to be readily understood that they operate together as the diode110, are formed through the same processes, and are referenced separately only for the sake of convenience in explanation.

In the P-type well111, only one N+ impurity area can be formed to be elongate, or two or more N+ impurity areas can be formed as described below. In the present embodiment, two N+ impurity areas are exemplarily formed in the P-type well111.

The pitch D1of the contacts115formed in the first N+ impurity area112aof the first region110a, the pitch D2of the contacts115formed in the first P+ impurity area114aof the first region110a, and the distance D3between the first N+ impurity area112aand the first P+ impurity area114acan all be determined according to the minimum design rule of a corresponding product in which the diode110is used.

The pitch D4of the contacts115formed in the second N+ impurity area112bof the second region110b, the pitch D5of the contacts115formed in the second P+ impurity area114bof the second region110b, and the distance D6between the second N+ impurity area112band the second P+ impurity area114bcan be determined to be greater than those according to the minimum design rule so that pin resistance is increased. For example, D4, D5and D6can each be determined to be at least two times greater than D1, D2and D3.

In this way, D4, D5and D6can be determined to be at least two times greater than D1, D2and D3regulated according to the minimum design rule, and as the case may be, only one or two of D4, D5and D6can be applied.

By adjusting the pitches of the contacts and the distance between the impurity areas, it is possible to form a diode having pin resistance that falls within the range regulated in a specification, i.e., the pin resistance required by a specific implementation.

The following is an explanation of how the pin resistance of the diode can be increased using the above-described structure.

First, it will be understood that the resistance of a diode is composed of contact resistance and well resistance between an anode and a cathode. Since the contact resistance has a value that is obtained through dividing the resistance of one contact by the total number of contacts, the contact resistance increases in proportion to a contact pitch. In other words, if the contact pitch is increased, contact resistance increases, because the number of contacts decreases.

The well resistance between an anode and a cathode has a value that is obtained through multiplying the sheet resistance of a well by the distance L between the anode and the cathode and then dividing the resultant product by the width W of a diode finger. Therefore, if the distance L between the anode and the cathode increases, the well resistance increases in proportion to the distance L. Accordingly, the resistance of a diode can be designed using the above-described three parameters so that a desired value can be obtained.

When the diode110is connected to the input/output pad of the semiconductor circuit as shown inFIG. 1, the first region110ahaving the same structure as a conventional diode can perform a function of discharging static electricity and protecting a circuit, and the second region110bcan perform a function of increasing pin resistance.

FIG. 4illustrates the layout of the second electrostatic discharge section120constructed in accordance with another embodiment. Again, reference number120is used to indicate that a diode constructed as illustrated inFIG. 4can perform the functions described in relation to diode120inFIG. 1.

Generally, the diode such as the first electrostatic discharge section110described with reference toFIG. 3is called an N-type diode and the diode shown inFIG. 4is called a P-type diode. Further, since the diode120has the same structure as the diode110described with reference toFIG. 3except that it has opposite polarity, the detailed description thereof will be omitted herein.

Referring toFIG. 4, it can be observed that the pitches D4and D5of contacts and the distance D6between impurity areas in a second region120bcan be set to be greater than the pitches D1and D2of contacts and the distance D3between impurity areas in a first region120a.

When the diode120is connected to the input/output pad of a semiconductor circuit, the first region120acan perform a function of discharging static electricity and protecting a circuit, and the second region120bperforms a function of increasing pin resistance.

The influence due to the increase of resistance in the diode as described above can be modeled using a simple equivalent circuit shown inFIG. 5. In this model, R1and C1respectively represent the pin resistance and the pin capacitance of a conventional semiconductor device, and R2and C2respectively represent the parasitic resistance and the parasitic capacitance of a diode configured in accordance with the embodiments described herein and which can be connected to a pad in order to increase the pin resistance of the conventional semiconductor device.

For example, suppose a semiconductor product has the following parameters: R1=3.5Ω and C1=1 pF. If the minimum pin resistance of a semiconductor product regulated in the associated specification is 4Ω, then it is necessary to increase pin resistance by about 1Ω to meet the requirements of that specific implementation. Calculating pin resistance using the equivalent circuit ofFIG. 5, in the case of using the diode for the purpose of increasing resistance, pin resistance Rpin is obtained by multiplying the respective resistance by the square of the respective capacitance, adding the resultant products, and then dividing the resultant sum by the square of total capacitance.

When expressing the pin resistance in a numerical formula, the following Mathematical Expression 1 is obtained.

Generally, a diode having the width of 20 μm and the anode area width of 1 μm is used for electrostatic protection. The junction capacitance of this diode has the level of 0.03 pF. In the case of the semiconductor product manufactured using a process below 0.1 μm, the sheet resistance of a P-type well is 1,500Ω/square, the contact resistance of a metal-P+ area is 1,500Ω/contact, the contact resistance of a metal-N+ area is 500Ω/contact, and the contact pitch and the distance between the anode and the cathode according to the minimum design rule are about 0.4 μm.

Therefore, when using the minimum design rule, since 50 contacts are located in the anode and 50 contacts are located in the cathode, contact resistance is calculated as 1,500/50+500/50=40Ω and well resistance is calculated as 1,500*0.5/20=37.5Ω, whereby total diode resistance becomes about 80Ω. When the number of such diode, which is laid out according to the minimum design rule, is increased by one pin resistance rather decreases from 3.5Ω to (80*0.03*0.03+3.5*1*1)/(1.03*1.03)=3.4Ω.

If the contact pitch of the anode is considerably increased by using only one contact at the center portion of the anode, as described herein, the total diode resistance is calculated as 1,500/1+500/50+37.5=1,547.5Ω and becomes about 1,550Ω. By increasing the number of such a diode by one, pin resistance significantly increases to (1550*0.03*0.03+3.5*1*1)/(1.03*1.03)=4.6Ω and can satisfy the specification. That is to say, since pin resistance can be increased by 1Ω or more, the embodiments described herein can be advantageously adapted for adjusting pin resistance.

FIG. 6is a layout diagram of a diode constructed in accordance with another embodiment.

In the aforementioned embodiments, one region is laid out according to the minimum design rule as in a conventional device, and the other region is laid out according to the principles described above. In the example embodiment ofFIG. 6, an entire region is laid out according to the principles described above.

Thus, a diode constructed according to the embodiment ofFIG. 6can include a P-type well111formed in a P-type semiconductor substrate, N+ impurity areas112formed in the P-type well111, an isolation area113formed to surround the N+ impurity areas112, a P+ impurity area114formed to surround the isolation area113, and contacts115formed in each of the N+ impurity areas112and the P+ impurity area114in a single row or a plurality of rows.

In the case that the diode is used as the first electrostatic discharge section110ofFIG. 1, the N+ impurity areas112can be connected to the input pad through the contacts115, and the P+ impurity area114can be connected to the ground voltage supply line (Vss) through the contacts115.

As mentioned above, in a conventional diode, as can be readily seen fromFIG. 2, problems are caused in that the pitches of the contacts115, which are formed in the N+ impurity areas and the P+ impurity area, and the distance between the N+ impurity area and the P+ impurity area are set according to the minimum design rule, and thus, the resulting pin resistance may not be able to satisfy the requirements of the associated specification.

In the embodiments described herein, however, the pitches of the contacts formed in the N+ impurity areas and the P+ impurity area can be increased so that pin resistance can be increased.

Referring again toFIG. 6, the pitches D4and D5between the contacts115formed in the N+ impurity areas112and the P+ impurity area114and the distance D6between the impurity areas can, e.g., each be determined to be at least two times greater than the values defined according to the minimum design rule. In this way, the contact pitches D4and D5and the distance D6between the impurity areas can be determined to be at least two times greater than the values defined according to the minimum design rule, and as the case may be, only one or two of D4, D5and D6can be applied.

Further, only one N+ impurity area can be formed to be elongate, or two or more N+ impurity areas can be formed in parallel.

FIG. 7is a layout diagram of a diode constructed in accordance with still another embodiment. As can be seen, the diodeFIG. 7can include a P-type well111formed in the surface of a P-type semiconductor substrate, one or more N+ impurity areas112formed in the surface of the substrate within the P-type well111to be elongate or parallel to one another, P+ impurity areas114formed to be separated from the N+ impurity areas112by a predetermined distance, and isolation areas113formed between the N+ impurity areas112and the P+ impurity areas114.

In the structure ofFIG. 7, at least one of the contact pitches D4and D5of the cathodes and the anodes and the distance D6between the cathode and the anode can be determined to be at least two times greater than the value defined according to the minimum design rule so that the resistance of the diode can be increased. Further, The cathodes112can be connected to the input/output pad of a semiconductor integrated circuit, and the anodes114can be connected to the ground voltage supply line (Vss), so that the pin resistance of a semiconductor device can be increased.

A diode, having the structure as shown inFIG. 7and in which the polarities of impurity areas are changed, can also be envisaged. Such a diode can include one or more P+ anode areas formed in an N-type well formed in the surface of a P-type semiconductor substrate to be elongate or parallel to one another, N+ cathode areas formed to be separated from the P+ anode areas by a predetermined distance, and isolation areas formed between the P+ anode areas and the N+ cathode areas. In the structure of this diode, at least one of the contact pitches of the anodes and the cathodes and the distance between the anode and the cathode can be determined, e.g., to be at least two times greater than the value defined according to the minimum design rule so that the resistance of the diode can be increased.

As is apparent from the above description, implementation of the methods described herein can allow the pin resistance to be significantly increased while minimally increasing capacitance. As a consequence, the pin resistance of a semiconductor product can be easily increased, and therefore, it is possible to satisfy the pin resistance regulated in any given specification.

While certain embodiments have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the apparatus and methods described herein should not be limited based on the described embodiments. Rather, the apparatus and methods described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.