Semiconductor device

According to this invention, there is provided a semiconductor device having conversion units which change the reference potential of an input signal to a first or second reference potential and outputs the input signal to a first drive unit or second drive unit, change the reference potential of a first control signal output from the first drive unit to the second reference potential and outputs the first control signal to the second drive unit, and changes the reference potential of a second control signal output from the second drive unit to the first reference potential and outputs the second control signal to the first drive unit, wherein the conversion units increase currents flowing through the conversion units on the basis of a time when the input signal changes.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims benefit of priority under 35 USC 119 from the Japanese Patent Application No. 2005-258180, filed on Sep. 6, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

There are DC-DC converters which generate a desired level of DC voltage by converting an externally input DC voltage into a high-frequency AC voltage and smoothing the AC voltage and output the DC voltage to a subsequent circuit. A plurality of DC-DC converters of this type are mounted in, e.g., an electronic device such as a cellular phone handset which uses a battery as its power source and generate a plurality of voltages for respective functional blocks.

In recent years, the operating frequencies of DC-DC converters have been increasing to cope with the lower voltage and higher current of a power source. For this reason, high-speed operation and high efficiency are required of a control circuit of a DC-DC converter. However, implementation of high-speed operation involves problems such as an increase in current consumption and an increase in circuit scale.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided a semiconductor device including first and second switching elements connected in series between first and second terminals with a predetermined potential difference between the terminals, and a control unit which controls connection states of the first and second switching elements on the basis of an input signal such that when one of the first and second switching elements enters an off state, the other switching element enters an on state, wherein the control unit has a first drive unit to which a first reference potential is applied as a reference potential and which generates and outputs a first control signal for controlling the connection state of the first switching element on the basis of the input signal and a second control signal, a second drive unit to which a second reference potential different from the first reference potential is applied as a reference potential and which generates and outputs the second control signal for controlling the connection state of the second switching element on the basis of the input signal and the first control signal, and a conversion unit which changes a reference potential of the input signal to one of the first and second reference potentials and outputs the input signal to one of the first and second drive units, changes a reference potential of the first control signal output from the first drive unit to the second reference potential and outputs the first control signal to the second drive unit, and changes a reference potential of the second control signal output from the second drive unit to the first reference potential and outputs the second control signal to the first drive unit, and the conversion unit increases a current flowing through the conversion unit on the basis of a time when the input signal changes.

DETAILED DESCRIPTION OF THE INVENTION

(1) First Embodiment

FIG. 1shows the configuration of a DC-DC converter10according to a first embodiment of the present invention. The DC-DC converter10generates a desired level of DC voltage by converting a DC voltage input from a voltage input terminal VIN into a high-frequency AC voltage and smoothing the AC voltage and outputs the DC voltage from a voltage output terminal VOUT.

The DC-DC converter10has NMOS transistors Tr10and Tr20as switching elements. A source of the NMOS transistor Tr10and a drain of the NMOS transistor Tr20are connected, a drain of the NMOS transistor Tr10is connected to the voltage input terminal VIN, and a source of the NMOS transistor Tr20is connected to a ground terminal GND.

The DC-DC converter10alternates the operation of turning on or off the NMOS transistors Tr10and Tr20with the reverse operation such that if an NMOS transistor Tr, one of the NMOS transistors Tr10and Tr20is brought into an off state, the other NMOS transistor Tr is brought into an on state. With this operation, an AC voltage is generated at a node LX which is the junction of the NMOS transistors Tr10and Tr20.

More specifically, if the NMOS transistor Tr10is brought into the on state, and the NMOS transistor Tr20is brought into the off state, the node LX is connected to the voltage input terminal VIN. This changes the potential of the node LX to the same potential as that of the DC voltage applied from the voltage input terminal VIN.

On the other hand, if the NMOS transistor Tr10is brought into the off state, and the NMOS transistor Tr20is brought into the on state, the node LX is connected to the ground terminal GND. This changes the potential of the node LX to 0 V.

An AC voltage obtained in the above-described manner is smoothed by a low-pass filter composed of a coil L10connected between the node LX and the voltage output terminal VOUT and a capacitor C10connected between the voltage output terminal VOUT and the ground terminal GND. The AC voltage is outputted as a desired level of DC voltage from the voltage output terminal VOUT.

The voltage level of the DC voltage is determined on the basis of the ratio (i.e., an on/off time ratio) between a period of time (i.e., an on time) during which the NMOS transistor Tr10is in the on state, and the DC voltage applied from the voltage input terminal VIN is selected as a potential to be generated at the node LX and a period of time (i.e., an off time) during which the NMOS transistor Tr20is in the on state, and 0 V is selected as the potential to be generated at the node LX.

For this reason, the DC-DC converter10has a control circuit20which controls on/off operation for the NMOS transistors Tr10and Tr20in accordance with an on/off control signal for controlling the on/off time ratio supplied from a control signal input terminal ON/OFF.

To prevent the NMOS transistors Tr10and Tr20from simultaneously entering the on state, the control circuit20first brings one of the NMOS transistors, the NMOS transistor Tr10or Tr20into the off state in accordance with the on/off control signal. The control circuit20notifies a drive circuit70or60for driving the other NMOS transistor Tr20or Tr10that the one NMOS transistor Tr10or Tr20has changed to the off state, thereby bringing the other NMOS transistor Tr20or Tr10into the on state. The control circuit20notifies the drive circuit60or70for driving the NMOS transistor Tr10or Tr20that the other NMOS transistor Tr20or Tr10has changed to the on state.

As described above, the control circuit20notifies one of the NMOS transistors Tr10and Tr20of the connection state of the other and notifies the other of the connection state of the one. With this operation, the control circuit20controls the on/off operation for the NMOS transistors Tr10and Tr20such that if one of the NMOS transistors, the NMOS transistor Tr10or Tr20is brought into the off state, the other NMOS transistor Tr20or Tr10is brought into the on state.

Of the NMOS transistors Tr10and Tr20, the NMOS transistor Tr20uses, as its reference potential, a potential applied from the ground terminal GND, i.e., 0 V while the NMOS transistor Tr10uses, as its reference potential, a potential generated at the node LX.

The control circuit20has a PMOS transistor Tr50and an NMOS transistor Tr60as circuits for driving the NMOS transistor Tr20. A drain of the PMOS transistor Tr50and a drain of the NMOS transistor Tr60are connected, and the junction of the transistors is connected to a gate of the NMOS transistor Tr20. A source of the PMOS transistor Tr50is connected to a power supply terminal VDD, and a source of the NMOS transistor Tr60is connected to the ground terminal GND. For this reason, the PMOS transistor Tr50and NMOS transistor Tr60use 0 V as their reference potentials.

The control circuit20also has a PMOS transistor Tr30and an NMOS transistor Tr40as circuits for driving the NMOS transistor Tr10. A drain of the PMOS transistor Tr30and a drain of the NMOS transistor Tr40are connected, and the junction of the transistors is connected to a gate of the NMOS transistor Tr10. A source of the PMOS transistor Tr30is connected to a terminal BST, and a source of the NMOS transistor Tr40is connected to the node LX. For this reason, the PMOS transistor Tr30and NMOS transistor Tr40use the potential generated at the node LX as their reference potentials.

Note that a zener diode ZD is connected between the terminal BST and the power supply terminal VDD. A cathode of the zener diode ZD is connected to the terminal BST while an anode thereof is connected to the power supply terminal VDD. A capacitor C20is connected between the terminal BST and the node LX.

The zener diode ZD and capacitor C20form a constant voltage circuit. For this reason, the potential of the terminal BST changes in response to a change in the potential of the node LX such that the potential difference between the terminal BST and the node LX is kept constant.

As described above, in the control circuit20, the circuits for driving the NMOS transistor Tr20use, as their reference potentials, 0 V, i.e., a low reference potential while the circuits for driving the NMOS transistor Tr10use, as their reference potentials, the potential generated at the node LX, i.e., a high reference potential.

Accordingly, when transferring a signal with the low reference potential to the drive circuit60on the high reference potential side, the control circuit20needs to convert the signal with the low reference potential into one with the high reference potential (change the reference potential from the low reference potential to the high reference potential) and transfer the resulting signal to the drive circuit60on the high reference potential side.

When transferring a signal with the high reference potential to the drive circuit70on the low reference potential side, the control circuit20needs to convert the signal with the high reference potential into one with the low reference potential (change the reference potential from the high reference potential to the low reference potential) and transfer the resulting signal to the drive circuit70on the low reference potential side.

For this reason, the control circuit20has level shift circuits30and40for converting a signal with the low reference potential into one with the high reference potential used to transfer a signal with the low reference potential to the drive circuit60on the high reference potential side and a level shift circuit50for converting a signal with the high reference potential into one with the low reference potential used to transfer a signal with the high reference potential to the drive circuit70on the low reference potential side.

When a signal of “L” level is input from the control signal input terminal ON/OFF as the on/off control signal with the low reference potential, the control circuit20inverts the level of the signal with an inverter INV10and outputs the obtained signal of “H” level to the level shift circuit30on the high reference potential side. At the same time, the control circuit20further inverts the level of the signal from “H” level to “L” level with an inverter INV20and outputs the obtained signal of “L” level to the drive circuit70on the low reference potential side.

The level shift circuit30converts the signal of “H” level with the low reference potential into one of “H” level with the high reference potential and outputs the resulting signal to the drive circuit60. If at least one of two input signals is at “H” level, the drive circuit60outputs a signal of “H” level to both the PMOS transistor Tr30and NMOS transistor Tr40. On the other hand, if both the input signals are at “L” level, the drive circuit60outputs a signal of “L” level to both the PMOS transistor Tr30and NMOS transistor Tr40.

In this example, the drive circuit60outputs a signal of “H” level to both the PMOS transistor Tr30and NMOS transistor Tr40to bring the PMOS transistor Tr30into the off state and the NMOS transistor Tr40into the on state.

This causes the gate of the NMOS transistor Tr10to be connected to the node LX via the NMOS transistor Tr40, and as a result, the NMOS transistor Tr10is brought into the off state.

An on/off detection circuit80is a circuit for detecting whether the NMOS transistor Tr10is in the on state or off state. When the on/off detection circuit80detects that the NMOS transistor Tr10has changed to the off state, it outputs a signal of “L” level with the high reference potential to the level shift circuit50.

The level shift circuit50converts the signal of “L” level with the high reference potential into one of “L” level with the low reference potential and outputs the resulting signal to the drive circuit70. When the signal of “L” level is supplied from the inverter INV20, and the signal of “L” level is supplied from the level shift circuit50, the drive circuit70outputs a signal of “L” level to both the PMOS transistor Tr50and NMOS transistor Tr60to bring the PMOS transistor Tr50into the on state and the NMOS transistor Tr60into the off state.

This causes the gate of the NMOS transistor Tr20to be connected to the power supply terminal VDD via the PMOS transistor Tr50, and as a result, the NMOS transistor Tr20is brought into the on state.

When an on/off detection circuit90detects that the NMOS transistor Tr20has changed to the on state, it outputs a signal of “H” level with the low reference potential to the level shift circuit40. After the level shift circuit40converts the signal into one of “H” level with the high reference potential, it outputs the resulting signal to the drive circuit60.

In this case, since the drive circuit60continues to output the signal of “H” level to both the PMOS transistor Tr30and NMOS transistor Tr40, the NMOS transistor Tr10remains in the off state.

After that, when the on/off control signal changes from “L” level to “H” level, the control circuit20inverts the level of the signal with the inverter INV10, converts the obtained signal of “L” level into one of “L” level with the high reference potential in the level shift circuit30, and outputs the resulting signal to the drive circuit60. At the same time, the control circuit20further inverts the level of the signal with the inverter INV20and outputs the obtained signal of “H” level to the drive circuit70.

In this case, the drive circuit70outputs a signal of “H” level to both the PMOS transistor Tr50and NMOS transistor Tr60to bring the PMOS transistor Tr50into the off state and the NMOS transistor Tr60into the on state.

This causes the gate of the NMOS transistor Tr20to be connected to the ground terminal GND via the NMOS transistor Tr60, and as a result, the NMOS transistor Tr20is brought into the off state.

When the on/off detection circuit90detects that the NMOS transistor Tr20has changed to the off state, it outputs a signal of “L” level with the low reference potential to the level shift circuit40. After the level shift circuit40converts the signal into one of “L” level with the high reference potential, it outputs the resulting signal to the drive circuit60.

When the signal of “L” level is supplied from the level shift circuit30, and the signal of “L” level is supplied from the level shift circuit40, the drive circuit60outputs a signal of “L” level to both the PMOS transistor Tr30and NMOS transistor Tr40to bring the PMOS transistor Tr30into the on state and the NMOS transistor Tr40into the off state.

This causes the gate of the NMOS transistor Tr10to be connected to the terminal BST via the PMOS transistor Tr30, and as a result, the NMOS transistor Tr10is brought into the on state.

When the on/off detection circuit80detects that the NMOS transistor Tr10has changed to the on state, it outputs a signal of “H” level with the high reference potential to the level shift circuit50. After the level shift circuit50converts the signal into one of “H” level with the low reference potential, it outputs the resulting signal to the drive circuit70.

In this case, since the drive circuit70continues to output the signal of “H” level to both the PMOS transistor Tr50and NMOS transistor Tr60, the NMOS transistor Tr20remains in the off state.

In this embodiment, the control circuit20inputs the on/off control signal with the low reference potential, having been supplied from the control signal input terminal ON/OFF, to the level shift circuits30and40. Since the control circuit20needs to input the on/off control signal to the level shift circuit50after converting the signal into one with the high reference potential, it inputs, to the level shift circuit50, a signal output from the level shift circuit30. The control circuit20also has an LX state determination circuit100. The LX state determination circuit100determines the state, i.e., potential of the node LX and outputs the determination result as a LX state determination signal to the level shift circuits30to50.

To implement high-speed operation and high efficiency, the control circuit20needs to shorten time (i.e., dead time) from when one of the NMOS transistors Tr10and Tr20is brought into the off state to when the other NMOS transistor Tr20or Tr10is brought into the on state.

For this reason, the level shift circuits30to50are required to transfer signals at high speed. The signal transfer speeds of the level shift circuits30to50depend on respective driving currents in the level shift circuits30to50.

Accordingly, each of the level shift circuits30to50is configured to increase the signal transfer speed by increasing a driving current therein on the basis of a time when the on/off control signal changes.

In this case, each of the level shift circuits30to50needs to set a driving current increase time such that the driving current increases at least until the potential of the node LX changes. The level shift circuit30to50decreases the increased driving current after the potential of the node LX changes, on the basis of the LX state determination signal supplied from the LX state determination circuit100.

FIG. 2shows the configuration of the level shift circuit30, which converts a signal with the low reference potential into one with the high reference potential.FIG. 3shows an example of a timing chart in the level shift circuit30. An input terminal IN is connected to a gate of an NMOS transistor Tr90and also connected to a gate of an NMOS transistor Tr70via an inverter INV30.

A source of the NMOS transistor Tr90is connected to the ground terminal GND via a constant current source130. A drain of an NMOS transistor Tr100is connected to the junction of the source of the NMOS transistor Tr90and the constant current source130, and the ground terminal GND is connected to a source of the NMOS transistor Tr100.

An edge pulse circuit110is connected to a gate of the NMOS transistor Tr100. The on/off control signal input from the control signal input terminal ON/OFF via an inverter INV50and the LX state determination signal input from the LX state determination circuit100via a determination input terminal LXDT are input to the edge pulse circuit110.

A source of the NMOS transistor Tr70is connected to the ground terminal GND via a constant current source140. A drain of the NMOS transistor Tr80is connected to the junction of the source of the NMOS transistor Tr70and the constant current source140, and the ground terminal GND is connected to a source of the NMOS transistor Tr80.

An edge pulse circuit120is connected to a gate of the NMOS transistor Tr80. The on/off control signal input from the control signal input terminal ON/OFF and the LX state determination signal input from the LX state determination circuit100via the determination input terminal LXDT are input to the edge pulse circuit120.

A drain of a PMOS transistor Tr130is connected to a drain of the NMOS transistor Tr90. The terminal BST is connected to sources of the PMOS transistor Tr130and a PMOS transistor Tr140. Gates of the PMOS transistors Tr130and Tr140are connected to each other, and the drain of the PMOS transistor Tr130is connected to the junction of the gates. For this reason, the PMOS transistors Tr130and Tr140form a current mirror circuit.

A drain of a PMOS transistor Tr110is connected to a drain of the NMOS transistor Tr70. The terminal BST is connected to sources of the PMOS transistor Tr110and a PMOS transistor Tr120. Gates of the PMOS transistors Tr110and Tr120are connected to each other, and the drain of the PMOS transistor Tr110is connected to the junction of the gates. For this reason, the PMOS transistors Tr110and Tr120form a current mirror circuit.

A drain of an NMOS transistor Tr150is connected to a drain of the PMOS transistor Tr140, and a drain of an NMOS transistor Tr160is connected to a drain of the PMOS transistor Tr120. Sources of the NMOS transistors Tr150and Tr160are connected to the node LX via a terminal LX. An output terminal OUT is connected to the junction of the PMOS transistor Tr120and the NMOS transistor Tr160via an inverter INV40.

Gates of the NMOS transistors Tr150and Tr160are connected to each other, and the drain of the NMOS transistor Tr150is connected to the junction of the gates. For this reason, the NMOS transistors Tr150and Tr160form a current mirror circuit.

When an input signal (FIG. 3(b)) with the low reference potential input from the input terminal IN changes from “L” level to “H” level (time t20), the NMOS transistor Tr70enters the off state (FIG. 3(e)), and the NMOS transistor Tr90enters the on state (FIG. 3(c)).

In this case, since the NMOS transistor Tr70enters the off state, no current flows through the PMOS transistor Tr110. Due to the characteristics of the current mirror circuit, no current flows through the PMOS transistor Tr120as well.

In the meantime, since the NMOS transistor Tr90enters the on state, a current equal to one which flows through the NMOS transistor Tr90flows through the PMOS transistor Tr130. Due to the characteristics of the current mirror circuit, a current equal to that which flows through the NMOS transistor Tr90flows through the PMOS transistor Tr140as well. Additionally, a current equal to that which flows through the NMOS transistor Tr90flows through the NMOS transistor Tr150.

Due to the characteristics of the current mirror circuit, there arises a force trying to feed, to the NMOS transistor Tr160, a current equal to that for the NMOS transistor Tr90. However, since the PMOS transistor Tr120is in the off state, no current flows through the NMOS transistor Tr160.

For this reason, the potential difference between the drain and source of the NMOS transistor Tr160becomes almost 0 V, and as a result, the potential of a node ND changes to the same potential as that of the node LX applied from the terminal LX, i.e., a signal of “L” level with the high reference potential. The inverter INV40inverts the level of a signal of “L” level with the high reference potential and outputs the obtained signal of “H” level with the high reference potential from the output terminal OUT.

In this embodiment, at a time when the on/off control signal (FIG. 3(a)) changes from “H” level to “L” level (time t10), the edge pulse circuit110outputs a signal of “H” level to the gate of the NMOS transistor Tr100(FIG. 3(d)) to bring the NMOS transistor Tr100into the on state.

As a result, a current which is the sum of a current which flows through the constant current source130and one which flows through the NMOS transistor Tr100flows through the NMOS transistor Tr90. The large increase in the current, which flows through the NMOS transistor Tr90, i.e., a driving current makes it possible to increase the signal transfer speed. The increase in the driving current before the input signal input from the input terminal IN changes from “L” level to “H” level makes it possible to improve the stability of the operation of the level shift circuit30.

After that, if the potential of the node LX changes from the same potential as that of the DC voltage input from the voltage input terminal VIN to 0 V, and the LX state determination signal (FIG. 3(g)) changes from “H” level to “L” level (time t30), the edge pulse circuit110outputs a signal of “L” level to the gate of the NMOS transistor Tr100(FIG. 3(d)) to bring the NMOS transistor Tr100into the off state (time t40).

As a result, a current equal to that which flows through the constant current source130flows through the NMOS transistor Tr90. The current, which flows through the NMOS transistor Tr90, decreases to a level just enough to maintain the output state of the output terminal OUT.

The decrease in the increased driving current on the basis of the time when the potential of the node LX changes makes it possible to suppress the driving current increase time to the minimum necessary and thus implement a decrease in current consumption. The decrease also has the effect of eliminating the need to provide, in the edge pulse circuit110, a CR circuit for setting the driving current increase time. This makes it possible to implement a decrease in circuit scale.

When the input signal (FIG. 3(b)) with the low reference potential input from the input terminal IN changes from “H” level to “L” level (time t60), the NMOS transistor Tr70enters the on state (FIG. 3(e)), and the NMOS transistor Tr90enters the off state (FIG. 3(c)).

In this case, since the NMOS transistor Tr90enters the off state, no current flows through the PMOS transistor Tr130. Due to the characteristics of the current mirror circuit, no current flows through the PMOS transistor Tr140as well. For this reason, no current flows through the NMOS transistor Tr150. Due to the characteristics of the current mirror circuit, no current flows through the NMOS transistor Tr160as well.

In the meantime, since the NMOS transistor Tr70enters the on state, a current equal to one which flows through the NMOS transistor Tr70flows through the PMOS transistor Tr110. Due to the characteristics of the current mirror circuit, there arises a force trying to feed, to the PMOS transistor Tr120, a current equal to that for the NMOS transistor Tr70. However, since the NMOS transistor Tr160is in the off state, no current flows through the PMOS transistor Tr120.

For this reason, the potential difference between the drain and source of the PMOS transistor Tr120becomes almost 0 V, and as a result, the potential of the node ND changes to the same potential as that applied from the terminal BST, i.e., the high reference potential (“H” level). The inverter INV40inverts the level of a signal of “H” level with the high reference potential and outputs the obtained signal of “L” level with the high reference potential from the output terminal OUT.

As in the above-described case, at a time when the on/off control signal (FIG. 3(a)) changes from “L” level to “H” level (time t50), the edge pulse circuit120outputs a signal of “H” level to the gate of the NMOS transistor Tr80(FIG. 3(f)) to bring the NMOS transistor Tr80into the on state.

As a result, a current which is the sum of a current which flows through the constant current source140and one which flows through the NMOS transistor Tr80flows through the NMOS transistor Tr80. This largely increases the current, which flows through the NMOS transistor Tr70, i.e., the driving current.

After that, if the potential of the node LX changes from 0 V to the same potential as that of the DC voltage input from the voltage input terminal VIN, and the LX state determination signal (FIG. 3(g)) changes from “L” level to “H” level (time t70), the edge pulse circuit120outputs a signal of “L” level to the gate of the NMOS transistor Tr80(FIG. 3(f)) to bring the NMOS transistor Tr80into the off state.

As a result, a current equal to that which flows through the constant current source140flows through the NMOS transistor Tr70. The current, which flows through the NMOS transistor Tr70, decreases to a level just enough to maintain the output state of the output terminal OUT.

FIG. 4shows, as a comparative example, an example of a timing chart in the case (FIGS. 4(d) and4(f)) of increasing the driving current from a time (time t20or t60) when a signal input to the level shift circuit (FIG. 4(b)) changes to a time (time t100or t110) set by a time constant CR for a CR circuit of the edge pulse circuit.

In this comparative example, the driving current increase time needs to be set to be longer such that it includes time to spare, in consideration of variations in switching time among the NMOS transistors Tr10and Tr20and the like and variations in CR elements. Such prolongation of the driving current increase time causes an increase in current consumption and thus creates the need to provide a CR circuit with a large time constant CR. This causes a problem of an increase in circuit scale.

Note that the level shift circuit40has the same configuration as the level shift circuit30. However, when the level shift circuit40notifies the drive circuit60that the NMOS transistor Tr20has changed to the on state, the NMOS transistor Tr10remains in the off state, and the potential of the node LX does not change. Accordingly, in this case, a time when an increased driving current is decreased is set by a time constant CR for a CR circuit of an edge pulse circuit having increased the driving current.

FIG. 5shows the configuration of the level shift circuit50, which converts a signal with the high reference potential into one with the low reference potential. The level shift circuit50is formed by reversing the plus and minus signs of circuit elements included in the level shift circuit30(FIG. 2) except for an inverter INV150provided at the preceding stage of an edge pulse circuit210.

More specifically, the level shift circuit50has an inverter INV130and the inverter INV150, the edge pulse circuit210and an edge pulse circuit220, constant current sources230and240, PMOS transistors Tr170to TR200, NMOS transistors Tr210and Tr220, NMOS transistors Tr230and Tr240, and PMOS transistors Tr250and Tr260. Each of the pair of NMOS transistors, Tr210and Tr220, the pair of NMOS transistors, Tr230and Tr240, and the pair of PMOS transistors, Tr250and Tr260form a current mirror circuit.

Note that similarly to the level shift circuit40, when the level shift circuit50notifies the drive circuit70that the NMOS transistor Tr10has changed to the on state, the NMOS transistor Tr20remains in the off state, and the potential of the node LX does not change. Accordingly, in this case, a time when an increased driving current is decreased is set by a time constant CR for a CR circuit of an edge pulse circuit having increased the driving current.

As described above, according to this embodiment, it is possible to implement high-speed operation and at the same time implement a decrease in current consumption and circuit scale.

(2) Second Embodiment

FIG. 6shows the configuration of a DC-DC converter300according to a second embodiment of the present invention. Note that the same components as those shown inFIG. 1are denoted by the same reference numerals and that an explanation thereof will be omitted. Level shift circuits320to340have the same configurations as the corresponding level shift circuits30to50(FIGS. 2 and 5) except for edge pulse circuits.

The potential of a node LX changes in response to a change in signals indicating the connection states of NMOS transistors Tr10and Tr20output from on/off detection circuits80and90. Accordingly, in this embodiment, each of the level shift circuits320to340determines a time when an increased driving current is decreased using a signal notifying, of the connection state of one of the NMOS transistors Tr10and Tr20, a drive circuit70or60for driving the other NMOS transistor Tr20or Tr10, i.e., a signal output from the on/off detection circuit80or90.

The level shift circuit320inputs a signal output from the on/off detection circuit90to an edge pulse circuit (one corresponding to the edge pulse circuit110of the level shift circuit30inFIG. 2) used to transfer an on/off control signal of “L” level (one for bringing the NMOS transistor Tr10into an off state).

The edge pulse circuit increases a driving current at a time when the on/off control signal changes from “H” level to “L” level. After that, when the NMOS transistor Tr20changes to an on state, and the potential of the node LX changes to 0V, the signal output from the on/off detection circuit90changes from “L” level to “H” level. The edge pulse circuit decreases the driving current on the basis of the time when the signal changes to “H” level.

The level shift circuit320inputs a signal output from the on/off detection circuit80after converting the signal into one with a low reference potential in the level shift circuit340to an edge pulse circuit (one corresponding to the edge pulse circuit120of the level shift circuit30inFIG. 2) used to transfer the on/off control signal of “H” level (one for bringing the NMOS transistor Tr10into the on state).

The edge pulse circuit increases a driving current at a time when the on/off control signal changes from “L” level to “H” level. After that, when the NMOS transistor Tr10changes to the on state, and the potential of the node LX changes to the same potential as that of a DC voltage applied from a voltage input terminal VIN, the signal output from the on/off detection circuit80via the level shift circuit340changes from “L” level to “H” level. The edge pulse circuit decreases the driving current on the basis of the time when the signal changes to “H” level.

The level shift circuit330inputs the signal output from the on/off detection circuit80after converting the signal into one with the low reference potential in the level shift circuit340to an edge pulse circuit (one corresponding to the edge pulse circuit120of the level shift circuit20inFIG. 2) used to make a notification that the NMOS transistor Tr20has changed to the off state.

The edge pulse circuit increases a driving current at a time when the on/off control signal changes from “L” level to “H” level. After that, when the NMOS transistor Tr10changes to the on state, and the potential of the node LX changes to the same potential as that of the DC voltage input from the voltage input terminal VIN, the signal output from the on/off detection circuit80via the level shift circuit340changes from “L” level to “H” level. The edge pulse circuit decreases the driving current on the basis of the time when the signal changes to “H” level.

Note that when the level shift circuit330notifies the drive circuit60that the NMOS transistor Tr20has changed to the on state, the NMOS transistor Tr10remains in the off state, and the potential of the node LX does not change. Accordingly, in this case, a time when the increased driving current is decreased is set by a time constant CR for a CR circuit of an edge pulse circuit (one corresponding to the edge pulse circuit110of the level shift circuit20inFIG. 2) used to make a notification that the NMOS transistor Tr20has changed to the on state.

The level shift circuit340inputs the signal output from the on/off detection circuit90after converting the signal into one with a high reference potential in the level shift circuit330to an edge pulse circuit (one corresponding to the edge pulse circuit210of the level shift circuit50inFIG. 5) used to make a notification that the NMOS transistor Tr10has changed to the off state.

The edge pulse circuit increases a driving current at a time when the on/off control signal changes from “H” level to “L” level. After that, when the NMOS transistor Tr20changes to the on state, and the potential of the node LX changes to 0 V, the signal output from the on/off detection circuit90via the level shift circuit330changes from “L” level to “H” level. The edge pulse circuit decreases the driving current on the basis of the time when the signal changes to “H” level.

Note that when the level shift circuit340notifies the drive circuit70that the NMOS transistor Tr10has changed to the on state, the NMOS transistor Tr20remains in the off state, and the potential of the node LX does not change. Accordingly, in this case, a time when the increased driving current is decreased is set by a time constant CR for a CR circuit of an edge pulse circuit (one corresponding to the edge pulse circuit220of the level shift circuit50inFIG. 5) used to make a notification that the NMOS transistor Tr10has changed to the on state.

As described above, according to this embodiment, it is possible to increase signal transfer speed and at the same time implement a decrease in current consumption and circuit scale. Also, this embodiment eliminates the need to provide the LX state determination circuit100(FIG. 1) and makes it possible to decrease CR circuits in the edge pulse circuits of the level shift circuits320to340.

FIG. 7shows the configuration of a DC-DC converter400according to a third embodiment of the present invention. Note that the same components as those shown inFIG. 1are denoted by the same reference numerals and that an explanation thereof will be omitted.

In this embodiment, a control circuit410has a drive circuit480for driving a PMOS transistor Tr50and a drive circuit490for driving an NMOS transistor Tr60.

The drive circuits480and490are powered by different power sources. The drive circuit490uses, as a reference potential, 0 V, i.e., a low reference potential while the drive circuit480uses, as a reference potential, a potential between one applied from a power supply terminal VDD and 0 V (to be referred to as an intermediate reference potential hereinafter).

This makes it possible to increase the gate threshold voltage of an NMOS transistor Tr20while maintaining the withstand voltages of the drive circuits480and490. Accordingly, it is possible to decrease the on-resistance of the NMOS transistor Tr20(a resistance generated between the source and drain when the NMOS transistor Tr20is brought into an on state).

The control circuit410has a level shift circuit450for converting a signal with the low reference potential into one with the intermediate reference potential used to transfer a signal with the low reference potential to the drive circuit480on the intermediate reference potential side, and a level shift circuit460for converting a signal with the intermediate reference potential into one with the low reference potential used to transfer a signal with the intermediate reference potential to the drive circuit490on the low reference potential side.

Note that the level shift circuit450is formed by connecting the inverter INV50connected at the preceding stage of the edge pulse circuit110in the level shift circuit30(FIG. 2) to the preceding stage of the edge pulse circuit120and that the level shift circuit460has the same configuration as the level shift circuit50(FIG. 5).

When a signal of “L” level is input from a control signal input terminal ON/OFF as an on/off control signal with the low reference potential, the control circuit410sequentially inverts the level of the signal with inverters INV10and INV20. The control circuit410inputs the obtained signal of “L” level to the drive circuit490on the low reference potential side and the level shift circuit450. The level shift circuit450converts the signal of “L” level with the low reference potential into one of “L” level with the intermediate reference potential and outputs the resulting signal to the drive circuit480.

When an NMOS transistor Tr10changes to an off state, and a signal of “L” level with a high reference potential is supplied from an on/off detection circuit80, a level shift circuit440converts the signal of “L” level with the high reference potential into one of “L” level with the intermediate reference potential and outputs the resulting signal to the drive circuit480.

In this case, the drive circuit480outputs the signal of “L” level to the PMOS transistor Tr50to bring the PMOS transistor Tr50into the on state and outputs the signal of “L” level to the level shift circuit460to notify the level shift circuit460that the PMOS transistor Tr50has changed to the on state.

The level shift circuit460converts the signal of “L” level with the intermediate reference potential into one of “L” level with the low reference potential and outputs the resulting signal to the drive circuit490. In this case, since the drive circuit490is supplied with the signals of “L” level from the level shift circuit460and inverter INV20, it outputs a signal of “L” level to the NMOS transistor Tr60to bring the NMOS transistor Tr60into the off state. At the same time, the drive circuit490outputs the signal of “L” level to the level shift circuit450to keep the PMOS transistor Tr50in the on state.

This causes a gate of the NMOS transistor Tr20to be connected to the power supply terminal VDD via the PMOS transistor Tr50, and as a result, the NMOS transistor Tr20is brought into the on state.

After that, when the on/off control signal changes from “L” level to “H” level, the control circuit410sequentially inverts the level of the signal with the inverters INV10and INV20. The control circuit410inputs the obtained signal of “H” level to the drive circuit490on the low reference potential side and the level shift circuit450on the intermediate reference potential side.

The level shift circuit450converts the signal of “H” level with the low reference potential into one of “H” level with the intermediate reference potential and outputs the resulting signal to the drive circuit480. In this case, the drive circuit480outputs the signal of “H” level to the PMOS transistor Tr50to bring the PMOS transistor Tr50into the off state and outputs the signal of “H” level to the level shift circuit460to make a notification that the PMOS transistor Tr50has changed to the off state.

The level shift circuit460converts the signal of “H” level with the intermediate reference potential into one of “H” level with the low reference potential and outputs the resulting signal to the drive circuit490. In this case, the drive circuit490outputs the signal of “H” level to the NMOS transistor Tr60to bring the NMOS transistor Tr60into the on state and outputs the signal of “H” level to the level shift circuit450to keep the PMOS transistor Tr50in the off state.

This causes the gate of the NMOS transistor Tr20to be connected to a ground terminal GND via the NMOS transistor Tr60, and as a result, the NMOS transistor Tr20is brought into the off state.

As in the first embodiment, the control circuit410inputs the on/off control signal supplied from the control signal input terminal ON/OFF to the level shift circuit450. Since the control circuit410needs to input the on/off control signal to the level shift circuit460after converting the signal into one with the intermediate reference potential, it inputs, to the level shift circuit460, a signal output from the level shift circuit450. An LX state determination circuit100outputs an LX state determination signal obtained by determining the state, i.e., potential of a node LX to the level shift circuits450and460.

For this reason, similarly to the level shift circuits30to50(FIG. 1) according to the first embodiment, each of the level shift circuits450and460increases a driving current therein on the basis of a time when the on/off control signal changes. After that, the level shift circuit decreases the increased driving current on the basis of a time when the potential of the node LX changes.

Note that when the PMOS transistor Tr50changes to the on state, and a drive circuit60is notified that the NMOS transistor Tr20has changed to the on state, the NMOS transistor Tr10remains in the off state, and the potential of the node LX does not change. Accordingly, in this case, a time when an increased driving current is decreased in the level shift circuit460, which notifies the drive circuit490that the PMOS transistor Tr50has changed to the on state, is set by a time constant CR for a CR circuit of an edge pulse circuit (one corresponding to the edge pulse circuit210of the level shift circuit50inFIG. 5) used to make a notification that the PMOS transistor Tr50has changed to the on state.

As described above, according to this embodiment, it is possible to increase signal transfer speed and at the same time implement a decrease in current consumption and circuit scale. Also, this embodiment makes it possible to increase the gate threshold voltage of the NMOS transistor Tr20and thus decrease the on-resistance of the NMOS transistor Tr20.

FIG. 8shows the configuration of a DC-DC converter500according to a fourth embodiment of the present invention. Note that the same components as those shown inFIGS. 1,6, and7are denoted by the same reference numerals and that an explanation thereof will be omitted.

In this embodiment, a control circuit510has drive circuits480and490for separately driving a PMOS transistor Tr50and an NMOS transistor Tr60. Also, the control circuit510determines a time when an increased driving current is decreased in each of level shift circuits320,330, and540to560, using signals output from on/off detection circuits80and90.

Note that as in the third embodiment, the level shift circuit550is formed by connecting the inverter INV50connected at the preceding stage of the edge pulse circuit110in the level shift circuit30(FIG. 2) to the preceding stage of the edge pulse circuit120and that the level shift circuit560has the same configuration as the level shift circuit50(FIG. 5).

The level shift circuit550inputs a signal output from the on/off detection circuit90to an edge pulse circuit (one corresponding to the edge pulse circuit120of the level shift circuit30inFIG. 2) used to transfer an on/off control signal of “L” level (one for bringing an NMOS transistor Tr20into an on state).

The edge pulse circuit increases a driving current at a time when the on/off control signal changes from “H” level to “L” level. After that, when the NMOS transistor Tr20changes to the on state, and the potential of a node LX changes to 0 V, the signal output from the on/off detection circuit90changes from “L” level to “H” level. The edge pulse circuit decreases the increased driving current on the basis of the time when the signal changes to “H” level.

The level shift circuit550inputs a signal output from the on/off detection circuit80after converting the signal into one with an intermediate reference potential in the level shift circuit540to an edge pulse circuit (one corresponding to the edge pulse circuit110of the level shift circuit30inFIG. 2) used to transfer the on/off control signal of “H” level (one for bringing the NMOS transistor Tr20into an off state).

The edge pulse circuit increases the driving current at a time when the on/off control signal changes from “L” level to “H” level. After that, when an NMOS transistor Tr10changes to the on state, and the potential of the node LX changes to the same potential as that of a DC voltage applied from a voltage input terminal VIN, the signal output from the on/off detection circuit80via the level shift circuit540changes from “L” level to “H” level. The edge pulse circuit decreases the driving current on the basis of the time when the signal changes to “H” level.

The level shift circuit560inputs the signal output from the on/off detection circuit80after converting the signal into one with the intermediate reference potential in the level shift circuit540to an edge pulse circuit (one corresponding to the edge pulse circuit220of the level shift circuit50inFIG. 5) used to make a notification that the PMOS transistor Tr50has changed to the off state (the NMOS transistor Tr20has changed to the off state).

The edge pulse circuit increases a driving current at a time when the on/off control signal changes from “L” level to “H” level. After that, when the NMOS transistor Tr10changes to the on state, and the potential of the node LX changes to the same potential as that of the DC voltage input from the voltage input terminal VIN, the signal output from the on/off detection circuit80via the level shift circuit540changes from “L” level to “H” level. The edge pulse circuit decreases the driving current on the basis of the time when the signal changes to “H” level.

Note that when a notification is made that the PMOS transistor Tr50has changed to the on state (the NMOS transistor Tr20has changed to the on state), the NMOS transistor Tr10remains in the off state, and the potential of the node LX does not change. Accordingly, in this case, a time when the increased driving current is decreased is set by a time constant CR for a CR circuit of an edge pulse circuit (one corresponding to the edge pulse circuit210of the level shift circuit50inFIG. 5) used to make a notification that the PMOS transistor Tr50has changed to the on state.

As described above, according to this embodiment, it is possible to increase signal transfer speed and at the same time implement a decrease in current consumption and circuit scale. Also, this embodiment makes it possible to increase the gate threshold voltage of the NMOS transistor Tr20and thus decrease the on-resistance of the NMOS transistor Tr20. Additionally, this embodiment eliminates the need to provide the LX state determination circuit100(FIG. 7) and makes it possible to decrease CR circuits in the edge pulse circuits of the level shift circuits320,330, and540to560.

Note that the above-described embodiments are merely examples and not intended to limit the present invention. For example, although the embodiments use the NMOS transistors Tr10and Tr20as switching elements, other various switching elements may be used instead.