Semiconductor device

According to one embodiment, a semiconductor device includes a stacked body; a columnar portion; a plate portion; and a blocking insulating film. The stacked body includes a plurality of electrode layers. The columnar portion includes a semiconductor body and a charge storage film. The plate portion includes a conductor and a sidewall insulating film. The sidewall insulating film is provided between the conductor and the insulator and between the conductor and the electrode layers. The conductor contacts the major surface of the substrate. The blocking insulating film is provided between the sidewall insulating film and the insulator, between the insulator and the electrode layers, and between the charge storage film and the electrode layers. The blocking insulating film includes a first blocking insulating layer and a second blocking insulating layer, the second blocking insulating layer being different from the first blocking insulating layer.

FIELD

BACKGROUND

A memory device having a three-dimensional structure has been proposed in which a memory hole is made in a stacked body in which multiple electrode layers are stacked, and a charge storage film and a semiconductor film are provided to extend in the stacking direction of the stacked body in the memory hole. The electrode layers of the stacked body are gate electrodes of a drain-side selection transistor, a source-side selection transistor, and memory cells. The memory device includes the multiple memory cells connected in series between the drain-side selection transistor and the source-side selection transistor. The structure in which the drain-side selection transistor, the multiple memory cells, and the source-side selection transistor are connected in series is called a memory string. A slit that reaches the substrate from the upper surface of the stacked body is made in the stacked body. A conductor is filled into the slit. For example, the conductor is used to form a source line of the memory string. It is desirable to cause the cell current to flow quickly from the memory string toward the source line.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a stacked body; a columnar portion; a plate portion; and a blocking insulating film. The stacked body includes a plurality of electrode layers stacked from the major surface of the substrate with an insulator interposed. The columnar portion extends along a stacking direction of the stacked body. The columnar portion includes a semiconductor body and a charge storage film. The charge storage film is provided between the semiconductor body and the electrode layers. The plate portion includes a conductor and a sidewall insulating film. The sidewall insulating film is provided between the conductor and the insulator and between the conductor and the electrode layers. The sidewall insulating film contacts the major surface of the substrate. The conductor contacts the major surface of the substrate. The blocking insulating film is provided between the sidewall insulating film and the insulator, between the insulator and the electrode layers, and between the charge storage film and the electrode layers. The blocking insulating film includes a first blocking insulating layer and a second blocking insulating layer, the second blocking insulating layer being different from the first blocking insulating layer.

Embodiments will now be described with reference to the drawings. In the respective drawings, like members are labeled with like reference numerals. Semiconductor devices of the embodiments are semiconductor memory devices having memory cell arrays.

FIG. 1is a schematic perspective view of a memory cell array1of a semiconductor device of a first embodiment. InFIG. 1, two mutually-orthogonal directions parallel to a major surface10aof a substrate10are taken as an X-direction and a Y-direction. The XY plane is a planar direction of a stacked body100. A direction orthogonal to both the X-direction and the Y-direction is taken as a Z-direction (the stacking direction of the stacked body100). In the specification, “down” refers to the direction toward the substrate10; and “up” refers to the direction away from the substrate10.

As shown inFIG. 1, the memory cell array1includes a stacked body100, multiple columnar portions CL, and multiple slits ST. The stacked body100is provided on the major surface10aof the substrate10. InFIG. 1, arrow TOP indicates the upper end portion of the stacked body100. Arrow BTM indicates the lower end portion of the stacked body100. The stacked body100includes the multiple electrode layers (SGS, WL, and SGD) stacked from the major surface10awith an insulator40interposed. A drain-side selection gate line SGD, multiple word lines WL, and a source-side selection gate line SGS are provided in the columnar portion CL.

The electrode layers (SGD, WL, and SGS) are stacked to be separated from each other. The electrode layer SGS is a source-side selection gate line. The electrode layer SGD is a drain-side selection gate line. The electrode layer WL is a word line. The number of stacks of the electrode layers (SGD, WL, and SGS) is arbitrary. The electrode layers (SGD, WL, and SGS) include a conductor. The conductor includes, for example, tungsten. The insulator40is disposed in each region between the electrode layers (SGD, WL, and SGS). The insulator40may be an insulator such as a silicon oxide film, etc., or may be an air gap.

The source-side selection gate line SGS is provided on the major surface10aof the substrate10with the insulator40interposed. The substrate10is, for example, a semiconductor substrate. The semiconductor substrate includes, for example, silicon. The multiple word lines WL are provided, with the insulator40interposed, on the source-side selection gate line SGS. The drain-side selection gate line SGD is provided, with the insulator40interposed, on the word line WL of the uppermost layer.

At least one selection gate line SGD is used as a gate electrode of a drain-side selection transistor STD. At least one selection gate line SGS is used as a gate electrode of a source-side selection transistor STS. Multiple memory cells MC are connected in series between the drain-side selection transistor STD and the source-side selection transistor STS. One of the word lines WL is used as a gate electrode of the memory cell MC. A memory string MS has a structure in which the drain-side selection transistor STD, the multiple memory cells MC, and the source-side selection transistor STS are connected in series.

The slit ST is provided in the stacked body100. The slit ST extends along the stacking direction of the stacked body100(the Z-direction) and the major surface direction of the substrate10(the X-direction) through the stacked body100. The slit ST divides the stacked body100into a plurality in the Y-direction orthogonal to the X-direction. The region that is divided by the slit ST is called a “block.”

A plate portion PT is provided in the slit ST. The plate portion PT includes, for example, a source line SL that has a plate configuration, and a sidewall insulating film (not shown inFIG. 1) of the source line SL for insulating the source line SL having the plate configuration from the periphery. The source line SL is a conductor. The source line SL is insulated from the stacked body100by the sidewall insulating film. For example, the plate portion PT extends along the stacking direction of the stacked body100(the Z-direction) and the major surface direction of the substrate10(the X-direction). An upper layer interconnect80is disposed above the source line SL. The upper layer interconnect80extends in the Y-direction. The upper layer interconnect80is electrically connected to the multiple source lines SL arranged along the Y-direction.

The columnar portion CL is provided in the stacked body100divided by the slit ST. The columnar portion CL extends in the stacking direction of the stacked body100(the Z-direction). For example, the columnar portion CL is formed in a circular columnar or elliptical columnar configuration. For example, the columnar portion CL is disposed in a staggered lattice configuration or a square lattice configuration in the memory cell array1. The memory string MS is disposed in the columnar portion CL.

Multiple bit lines BL are disposed above the upper end portion of the columnar portion CL. The multiple bit lines BL extend in the Y-direction. The upper end portion of the columnar portion CL is electrically connected via a contact portion Cb to one of the bit lines BL. One bit line BL is electrically connected to one columnar portion CL selected from each block.

FIG. 2is a schematic cross-sectional view of the memory cell array1of the semiconductor device of the first embodiment.FIG. 2corresponds to a cross section parallel to the Y-Z plane ofFIG. 1.FIG. 2shows the extracted lower end portion BTM side of the stacked body100.

As shown inFIG. 2, the columnar portion CL is provided in a memory hole MH. The memory hole MH has a hole pattern. The memory hole MH is provided in the stacked body100. The memory hole MH extends along the stacking direction of the stacked body100(the Z-direction) through the stacked body100. The columnar portion CL includes a memory film30, a semiconductor body20, and a core layer50.

The memory film30is provided on the inner wall of the memory hole MH. The configuration of the memory film30is, for example, a tubular configuration. The memory film30includes a cover insulating film31, a charge storage film32, and a tunneling insulating film33.

The cover insulating film31is provided on the inner wall of the memory hole MH. The cover insulating film31includes, for example, silicon oxide. For example, the cover insulating film31protects the charge storage film32from the etching when forming the word lines WL.

The charge storage film32is provided on the cover insulating film31. The charge storage film32includes, for example, silicon nitride. Other than silicon nitride, the charge storage film32may include hafnium oxide. The charge storage film32has trap sites that trap charge in a film. The threshold of the memory cell MC changes due to the existence/absence of the charge trapped in the trap sites and the amount of the trapped charge. Thereby, the memory cell MC retains information.

The tunneling insulating film33is provided on the charge storage film32. For example, the tunneling insulating film33includes silicon oxide, or includes silicon oxide and silicon nitride. The tunneling insulating film33is a potential barrier between the charge storage film32and the semiconductor body20. Tunneling of the charge occurs in the tunneling insulating film33when the charge is injected from the semiconductor body20into the charge storage film32(a programming operation) and when the charge is discharged from the charge storage film32into the semiconductor body20(an erasing operation).

The semiconductor body20is provided on the memory film30. The semiconductor body20of the first embodiment includes a cover layer20aand a channel layer20b. The configuration of the cover layer20ais, for example, a tubular configuration. The configuration of the channel layer20bis, for example, a tubular configuration having a bottom. The cover layer20aand the channel layer20binclude, for example, silicon. The silicon is, for example, polysilicon made of amorphous silicon that is crystallized. The conductivity type of the silicon is, for example, a P-type. For example, the semiconductor body20is electrically connected to the substrate10.

The core layer50is provided on the semiconductor body20. The core layer50is insulative. The core layer50includes, for example, silicon oxide. The configuration of the core layer50is, for example, a columnar configuration.

The memory hole MH is filled with the memory film30, the semiconductor body20, and the core layer50.

The plate portion PT is provided in the slit ST. The slit ST extends along the stacking direction of the stacked body100(the Z-direction) and the major surface direction of the substrate10(the X-direction). The slit ST refers to the region of the space pattern prior to the plate portion PT being provided. As described above, the plate portion PT includes a conductor60and a stacked body sidewall insulating film used to form the source line SL.

The sidewall insulating film70is provided between the conductor60and the insulator40and between the conductor60and the electrode layers (SGD, WL, and SGS: inFIG. 2, referring to SGS and WL). For example, the sidewall insulating film70contacts the major surface10aat the lower end portion of the plate portion PT. The sidewall insulating film70includes, for example, silicon oxide. For example, the conductor60contacts the major surface10aat the lower end portion of the plate portion PT. In the first embodiment, for example, the conductor60is provided, with a barrier film61interposed, on the major surface10aand the sidewall insulating film70. The conductor60includes, for example, tungsten. The barrier film61includes, for example, titanium. The barrier film61may include titanium and titanium nitride. For example, the conductor60is used to form the source line SL.

A blocking insulating film34is provided in the stacked body100. The blocking insulating film34is provided between the sidewall insulating film70and the insulators40, between the insulators40and the electrode layers (SGD, WL, and SGS), and between the memory film30(in the first embodiment, the charge storage film32) and the electrode layers (SGD, WL, and SGS). The blocking insulating film34is provided along the stacking direction of the stacked body100(the Z-direction) between the sidewall insulating film70and the insulators40. The blocking insulating film34is provided along the planar direction of the stacked body100(the XY plane) between the insulators40and the electrode layers (SGD, WL, and SGS). The blocking insulating film34is provided along the stacking direction of the stacked body100(the Z-direction) between the memory film30and the electrode layers (SGD, WL, and SGS). The blocking insulating film34extends along the stacking direction of the stacked body100(the Z-direction) via the regions between the insulators40and the electrode layers (SGD, WL, and SGS) and the regions between the memory film30and the electrode layers (SGD, WL, and SGS). The blocking insulating film34includes a first blocking insulating layer34aand a second blocking insulating layer34b.

The first blocking insulating layer34ais provided on the memory film30side in the blocking insulating film34. The first blocking insulating layer34ais provided to be continuous from a lower end portion34cof the blocking insulating film34toward the upper end portion of the blocking insulating film34. In the first embodiment, the first blocking insulating layer34acontacts the charge storage film32, the cover insulating film31, and the insulator40.

The second blocking insulating layer34bis provided on the electrode layers (SGD, WL, and SGS) side in the blocking insulating film34. The second blocking insulating layer34bis provided to be continuous along the first blocking insulating layer34a. In the first embodiment, the second blocking insulating layer34bcontacts the electrode layers (SGD, WL, and SGS) via the first blocking insulating layer34a, the sidewall insulating film70, and a barrier film62. The barrier film62includes, for example, titanium nitride. The barrier film62may include titanium and titanium nitride.

The first blocking insulating layer34ais different from the second blocking insulating layer34b. For example, the first blocking insulating layer34ais an insulator having silicon oxide as a major component. The first blocking insulating layer34ais, for example, SiO2. The second blocking insulating layer34bis an insulator having a metal oxide as a major component. The metal is, for example, aluminum. The second blocking insulating layer34bis, for example, Al2O3. The first blocking insulating layer34ahas a first relative dielectric constant. The second blocking insulating layer34bhas a second relative dielectric constant that is higher than the first relative dielectric constant.

The substrate10includes a carrier in the portion where the memory cell array1is provided. The carrier is, for example, an acceptor. The acceptor is, for example, boron. Thereby, the conductivity type of the substrate10is the P-type in the portion where the memory cell array1is provided.

In the first embodiment, the substrate10includes a first recess portion71in the major surface10a. The first recess portion71is provided in the substrate10to correspond to the slit ST. The plate portion PT is provided to correspond to the first recess portion71. A semiconductor region72is provided in the substrate10to correspond to the first recess portion71. The semiconductor region72includes, for example, an acceptor and a donor. The semiconductor region72is, for example, a region to which the donor is additionally introduced to the substrate10. When the conductivity type of the substrate10is the P-type, the conductivity type of the semiconductor region72is the N-type or the P-type. When both the substrate10and the semiconductor region72are of the P-type, the carrier concentration (the effective acceptor concentration) of the semiconductor region72is, for example, lower than the substrate10of the P-type. This is because the donor that is the opposite conductivity type of the substrate10including the acceptor is additionally introduced to the semiconductor region72. The acceptor is, for example, boron (B). The donor is, for example, arsenic (As) or phosphorus (P).

In the first embodiment, a second recess portion73is further included in the first recess portion71. In the first embodiment, the blocking insulating film34contacts the first recess portion71; and the sidewall insulating film70and the conductor60contact the second recess portion73.

A method for manufacturing the semiconductor device of the first embodiment will now be described.

FIG. 3toFIG. 14are schematic cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment. The cross sections shown inFIG. 3toFIG. 14correspond to the cross section shown inFIG. 2.

As shown inFIG. 3, the stacked body100is formed on the major surface10aof the substrate10by alternately stacking the insulators40as first layers and replacement members41as second layers on the substrate10. The replacement members41are layers that are replaced with the electrode layers (SGD, WL, and SGS) subsequently. The material of the replacement members41is selected from materials that are different from the insulators40and can provide etching selectivity with respect to the insulators40. For example, when silicon oxide is selected as the insulators40, silicon nitride is selected as the replacement members41. The substrate10is a semiconductor. The conductivity type of the substrate10is, for example, the P-type. The semiconductor is, for example, silicon.

Then, the memory hole MH is made in the stacked body100; and the memory film30is formed on the inner wall of the memory hole MH. The memory film30is formed by forming the cover insulating film31, the charge storage film32, and the tunneling insulating film33in this order from the inner wall side of the memory hole MH. For example, the cover insulating film31is formed by depositing silicon oxide, or silicon oxide and aluminum oxide, on the stacked body100and the inner wall of the memory hole MH. For example, the charge storage film32is formed by depositing silicon nitride on the cover insulating film31. The tunneling insulating film33is formed by depositing silicon oxide, or silicon oxide and silicon nitride, on the charge storage film32.

Then, the semiconductor body20is formed on the memory film30. The semiconductor body20is formed by forming the cover layer20aand the channel layer20bin this order on the memory film30. For example, the cover layer20ais formed by depositing silicon doped with boron on the tunneling insulating film33. After forming the cover layer20a, the cover layer20aand the memory film30that are on the bottom portion of the memory hole MH are removed. Thereby, the substrate10is exposed from the bottom portion of the memory hole MH. Then, the channel layer20bis formed on the cover layer20aand the substrate10. For example, the channel layer20bis formed by depositing silicon doped with boron on the cover layer20aand the substrate10. Subsequently, crystallization annealing of the cover layer20aand the channel layer20bis performed. Thereby, the cover layer20aand the channel layer20bare crystallized; and the semiconductor body20of the P-type is formed. It is sufficient for the crystallization annealing to be performed after the cover layer20aand the channel layer20bare formed. The timing of the crystallization annealing is not limited to the timing of the first embodiment.

Then, an insulator, e.g., silicon oxide, is deposited on the semiconductor body20; and the memory hole MH is filled with silicon oxide. Thereby, the core layer50is formed.

Then, as shown inFIG. 4, the slit ST is made in the stacked body100. The slit ST is made also in the interior of the substrate10via the major surface10aof the substrate10. Thereby, the first recess portion71is formed in the substrate10.

Then, as shown inFIG. 5, the semiconductor region72is formed in the substrate10. The semiconductor region72is formed to correspond to the first recess portion71. For example, the semiconductor region72is formed by using a not-shown resist mask layer as a mask and by introducing a carrier of the opposite conductivity type of the substrate10in the substrate10via the selected slit ST. For example, when the conductivity type of the substrate10is the P-type, an N-type carrier (a donor) is introduced to the substrate10. The N-type carrier (the donor) is, for example, arsenic (As) or phosphorus (P). For example, it is sufficient for ion implantation, etc., to be used to introduce the carrier.

Then, as shown inFIG. 6, the replacement members41are removed via the slit ST from the stacked body100. Thereby, a space42is made between the insulator40and the insulator40. The surfaces of the insulators40and the columnar portion CL are exposed. In the first embodiment, in the spaces42, the surface of the cover insulating film31of the columnar portion CL is exposed in the stacking direction of the stacked body100(the Z-direction); and the surfaces of the insulators40are exposed along the planar direction of the stacked body (the XY plane).

Then, as shown inFIG. 7, the cover insulating film31is removed from the columnar portion CL via the slit ST and the spaces42. Thereby, for example, the charge storage film32is exposed from the columnar portion CL. For example, in the first embodiment, the cover insulating film31includes silicon oxide. The insulators40also include silicon oxide. Therefore, when removing the cover insulating film31, for example, an amount of the surfaces of the insulators40corresponding to the thickness of the cover insulating film31is caused to recede.

Then, as shown inFIG. 8, the blocking insulating film34is formed on the insulators40, the cover insulating film41, and the charge storage film32. The blocking insulating film34is formed by forming the first blocking insulating layer34aand the second blocking insulating layer34bin this order on the insulators40, the cover insulating film41, and the charge storage film32. For example, the first blocking insulating layer34ais formed by depositing silicon oxide on the insulators40, the cover insulating film31, and the charge storage film32via the slit ST and the spaces42. For example, the second blocking insulating layer34bis formed by depositing aluminum oxide, e.g., alumina (Al2O3), on the first blocking insulating layer34avia the slit ST and the spaces42.

Then, as shown inFIG. 9, the barrier film62is formed on the second blocking insulating layer34bvia the slit ST and the spaces42. For example, the barrier film62includes titanium nitride, or includes titanium nitride and titanium. Then, a conductor43is formed on the barrier film62. Thereby, the spaces42are filled with the conductor43. The conductor43is a layer used to form the electrode layers (SGD, WL, and SGS) subsequently and includes, for example, tungsten.

Then, as shown inFIG. 10, the conductor43is etched; the portion of the conductor43above the blocking insulating films (34aand34b) of the slit ST is etched; and the conductor43is caused to remain in the spaces42. Thereby, the blocking insulating film34, the barrier film62, and the electrode layers (SGD, WL, and SGS: inFIG. 10, referring to SGS and WL) are formed between the insulator40and the insulator40above the stacked body100. The word line WL and the source-side selection gate line SGS are shown as the electrode layers inFIG. 10. The removal of the conductor43is performed using, for example, anisotropic dry etching and wet etching. The anisotropic dry etching is, for example, reactive ion etching (RIE). The reactant gas that is used in the RIE is a gas including a fluorine-based gas. An example of the fluorine-based gas is NF3. The barrier film62that is on the slit ST also is removed when removing the conductor43.

As shown inFIG. 11, the blocking insulating film34is removed from the bottom portion of the slit ST. The reactant gas of the removal of the blocking insulating film34is a chlorine-based gas. An example of the chlorine-based gas is Cl2gas. Thereby, the blocking insulating film34is removed from the bottom portion of the slit ST. When removing the blocking insulating film34, the anisotropic dry etching progresses in the substrate10. Thereby, the second recess portion73is formed in the first recess portion71. For example, the surface of the substrate10is exposed from the bottom portion of the second recess portion73. The semiconductor region72is exposed in the first embodiment.

Then, as shown inFIG. 12, an insulating film70ais formed in the slit ST. Inside the slit ST, the insulating film70ais formed on the insulator40and the electrode layers (SGD, WL, and SGS). For example, the insulating film70ais formed by depositing silicon oxide on the structure body shown inFIG. 11. The insulating film70acontacts the substrate10at the bottom portion of the second recess portion73. The insulating film70acontacts the semiconductor region72in the first embodiment.

Then, as shown inFIG. 13, the surface of the substrate is exposed by performing, for example, anisotropic dry etching of the insulating film70a. Thereby, the sidewall insulating film70is formed on the inner wall of the slit ST.

Then, as shown inFIG. 14, the barrier film61is formed on the sidewall insulating film70. For example, the barrier film61includes titanium, or titanium nitride and titanium. Then, the conductor60is formed on the barrier film61. Thereby, the slit ST is filled with the conductor60. The conductor60is used to form the source line SL.

For example, the semiconductor device of the first embodiment can be manufactured by such a manufacturing method.

FIG. 15is a schematic cross-sectional view of the bottom portion of the slit ST of the semiconductor device of the first embodiment.FIG. 16is a schematic view showing the trend of the aluminum concentration at the bottom portion of the slit ST of the semiconductor device of the first embodiment.

As shown inFIG. 15, in the semiconductor device of the first embodiment, the sidewall insulating film70contacts the major surface10aof the substrate10at the bottom portion of the slit ST (the bottom portion of the second recess portion73). Thereby, at the bottom portion of the slit ST, the blocking insulating film34is separated from the conductor60by the sidewall insulating film70. In the first embodiment, the first blocking insulating layer34a, the second blocking insulating layer34b, and the sidewall insulating film70exist in the first recess portion71. The sidewall insulating film70exists in the second recess portion73. The blocking insulating film34is separated from the conductor60with the sidewall insulating film70interposed in the second recess portion73.

The blocking insulating film34includes a metal oxide (the second blocking insulating layer34b). The metal is, for example, aluminum. Therefore, as shown inFIG. 16, the concentration of aluminum in the structure body on the major surface10adecreases from portion A toward portion B. Portion A is, for example, the portion where the stepped portion due to the first recess portion71starts. Portion B is, for example, the boundary between the conductor60and the substrate10(in the first embodiment, the barrier film61also is considered to be a portion of the conductor60). Portion C is the portion where the second blocking insulating layer34bis shielded by the sidewall insulating film70. Portion D is the portion where the stepped portion of the second recess portion73between portion A and portion B starts.

In the first embodiment, because the second blocking insulating layer34bis shielded by the sidewall insulating film70, the concentration of aluminum can be reduced from portion C to portion B. For example, as shown inFIG. 16, the aluminum can be “substantially zero” between portion C and portion B. Substantially zero refers to the amount of aluminum decreasing to a level at which the existence of aluminum cannot be detected. That is, in the first embodiment, the amount of aluminum between portion C and portion B can be reduced to be not more than the detection limit of the analysis device. The analysis device is, for example, a secondary ion mass spectrometer.

FIG. 17is a schematic cross-sectional view of the bottom portion of the slit ST of a semiconductor device of a reference example.FIG. 18is a schematic view showing the trend of the aluminum concentration at the bottom portion of the slit ST of the semiconductor device of the reference example.

As shown inFIG. 17, the reference example is the case where the blocking insulating film34is not separated from the conductor60at the bottom portion of the slit ST. In such a case, as shown inFIG. 18, the concentration of aluminum in the structure body on the major surface10ais maintained at a high concentration from portion A toward portion B. An oxide that includes a metal, e.g., an oxide that includes aluminum, becomes trap sites that trap electrons. The “x” in the drawing on the right ofFIG. 17schematically shows electrons e trapped in the second blocking insulating layer34b.

The electrons e are somewhat trapped in the second blocking insulating layer34bfrom the initial part of the film formation process. For example, this is because there are processes that use charged particles in the manufacturing processes. Then, the amount of the electrons e trapped in the second blocking insulating layer34bfurther increases as the usage time (the operation time) as a semiconductor device increases. This is because the electrons e flow between the source line SL and the memory string MS. As a result, the second blocking insulating layer34bbecomes strongly charged to be “negative” as the usage time increases. As illustrated by reference numeral72a, the second blocking insulating layer34bbeing charged to be “negative” obstructs the semiconductor region72from inverting to the N-type or from being of a strong N-type. Therefore, the resistance value between the memory string MS and the source line SL increases; and the cell current does not flow easily. In the case where the cell current does not flow easily, the threshold of the memory cell MC appears to be undesirably high. Accordingly, for example, the determination undesirably may erroneously be “the threshold is high” in the read-out operation. This is “misreading.”

Compared to such a reference example, in the semiconductor device of the first embodiment, the concentration of aluminum in the structure body on the major surface10adecreases from portion A toward portion B. Therefore, compared to the reference example, the likelihood that the electrons e may be trapped in the structure body on the major surface10acan be reduced. Accordingly, even if the memory device is used for a long period of time, compared to the reference example, the cell current can be caused to flow quickly from the memory string MS to the source line SL.

According to the first embodiment, the cell current can be caused to flow quickly from the memory string MS to the source line SL. Accordingly, for example, even when used for a long period of time, a memory device in which the occurrence of misreading is low and the reliability is high can be obtained.

FIG. 19is a schematic cross-sectional view of the bottom portion of the slit ST of a semiconductor device of a second embodiment.FIG. 20is a schematic view showing the trend of the aluminum concentration at the bottom portion of the slit ST of the semiconductor device of the second embodiment.

As shown inFIG. 19, the semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the second blocking insulating layer34bdoes not exist in the first recess portion71(referring to circle E inFIG. 19). In the second embodiment, the first blocking insulating layer34aand the sidewall insulating film70exist in the first recess portion71. The sidewall insulating film70exists in the second recess portion73.

Even for a structure such as that of the second embodiment, similarly to the first embodiment, the likelihood that the electrons e may be trapped in the structure body on the major surface10acan be reduced. In the second embodiment, as shown inFIG. 20, for example, it is possible to set the concentration of aluminum in the structure body on the major surface10abetween portion A and portion B to be substantially zero.

FIG. 21is a schematic cross-sectional view of the bottom portion of the slit ST of a semiconductor device of a third embodiment.FIG. 22is a schematic view showing the trend of the aluminum concentration at the bottom portion of the slit ST of the semiconductor device of the third embodiment.

As shown inFIG. 21, the semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that there is no second recess portion73. In the third embodiment, the first blocking insulating layer34a, the second blocking insulating layer34b, and the sidewall insulating film70exist in the first recess portion71. The thickness of the second blocking insulating layer34bdecreases from portion A toward portion B. The second blocking insulating layer34bvanishes in the first recess portion71before reaching the conductor60. The sidewall insulating film70contacts the major surface10aof the substrate10at the bottom portion of the slit ST (the bottom portion of the first recess portion71). Thereby, the first blocking insulating layer34ais separated from the conductor60by the sidewall insulating film70in the first recess portion71at the bottom portion of the slit ST.

Even for a structure such as that of the third embodiment, similarly to the first embodiment, the likelihood that the electrons e may be trapped in the structure body on the major surface10acan be reduced. This is because the concentration of aluminum can be reduced from portion A to portion B as shown inFIG. 22. In the third embodiment as well, for example, the concentration of aluminum in the structure body on the major surface10abetween portion C and portion B can be set to be substantially zero.

FIG. 23is a schematic cross-sectional view of the bottom portion of the slit ST of a semiconductor device of a fourth embodiment.FIG. 24is a schematic view showing the trend of the aluminum concentration at the bottom portion of the slit ST of the semiconductor device of the fourth embodiment.

As shown inFIG. 23, the semiconductor device of the fourth embodiment differs from the semiconductor device of the third embodiment in that the sidewall insulating film70contacts the first blocking insulating layer34aat the bottom portion of the slit ST (the bottom portion of the first recess portion71).

Even for a structure such as that of the fourth embodiment, similarly to the third embodiment, the likelihood that the electrons e may be trapped in the structure body on the major surface10acan be reduced. This is because the second blocking insulating layer34bis shielded by the sidewall insulating film70in portion C.

Accordingly, as shown inFIG. 24, for example, the concentration of aluminum in the structure body on the major surface10abetween portion C and portion B can be set to be substantially zero. For example, the first blocking insulating layer34asubstantially does not include aluminum. Therefore, even if the first blocking insulating layer34aremains in the first recess portion71, the concentration of aluminum in the structure body on the major surface10asubstantially does not increase.

Thus, according to the embodiments, a semiconductor device in which the cell current can be caused to flow quickly from the memory string MS toward the source line SL can be obtained.