Liquid crystal device and method of driving the same

A driving circuit for driving a liquid crystal display device having a plurality of gate lines, data lines and switch elements connected to the gate and data lines includes a data driver for applying a plurality of data signals to the date lines, a gate driver for applying a plurality of gate signals to the gate lines, a timing controller for providing a plurality of control signals to the data and gate drivers, a power supply for generating a power voltage, and a discharging circuit for applying a first signal and a second signal to the gate driver in accordance with the power voltage.

The invention claims the benefit of Korean Patent Applications No. 10-2006-0138514 filed in Korea on Dec. 29, 2006 and No. 10-2007-0045036 filed in Korea on May 9, 2007, which are hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of driving the same. Although embodiments of the invention are suitable for a wide scope of applications, they are particularly suitable for obtaining a liquid crystal display device including a discharging circuit and the method of driving the same.

2. Discussion of the Related Art

Liquid crystal display (LCD) devices use the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. The liquid crystal molecules have long and thin shapes, and have the optical anisotropy property, such that the liquid crystal molecules can be aligned along an alignment direction. The liquid crystal molecules also have the polarization property, such that the alignment direction can be changed according to an intensity of an applied electric field. In particular, the arrangement of the liquid crystal molecules can be changed by varying the intensity of the electric field. Consequently, light transmittance of the liquid crystal molecules is controlled by the electric field, and the LCD device displays images due to the changes in light transmittance.

In general, an LCD device includes a liquid crystal panel and a driving circuit. The liquid crystal panel includes first and second substrates spaced apart from each other and a liquid crystal layer between the first and second substrates. The first substrate, which is commonly referred to as an array substrate, has a thin film transistor and a pixel electrode, and the second substrate, which is commonly referred to as a color filter substrate, has a color filter layer and a common electrode. The driving circuit electrically drives the liquid crystal panel. Since the LCD device is a non-emissive type device, the LCD device includes a light source, such as a backlight unit, under the liquid crystal panel.

FIG. 1is a schematic diagram illustrating an LCD device according to the related art. InFIG. 1, an LCD device includes a liquid crystal panel10and a driving circuit60. The liquid crystal panel10includes a plurality of gate lines GL1to GLn and a plurality of data lines DL1to DLm. The plurality of gate lines GL1to GLn cross the plurality of data lines DL1to DLm to define a plurality of pixel regions, and each pixel region includes a thin film transistor (TFT) T, a liquid crystal capacitor Clc and a storage capacitor Cst to display images.

The driving circuit60includes a timing controller20, a gate driver30, a data driver40and a power supply50. The timing controller20generates data control signals for the data driver40including a plurality of data integrated circuits (ICs) and gate control signals for the gate driver30including a plurality of gate ICs using a plurality of external signals from an external system. Moreover, the timing controller20outputs data signals to the data driver40.

The gate driver30controls ON/OFF operation of the thin film transistors (TFTs) in the liquid crystal panel10according to the gate control signals from the timing controller20. On-level gate voltages are sequentially applied to the gate lines GL1to GLn by a single horizontal synchronization time (1H) to enable the gate lines GL1to GLn and the TFTs connected to the gate lines GL1to GLn. When the TFTs corresponding to a single gate line are turned on, the data signals are applied to pixels in the pixel regions of the liquid crystal panel10through the data lines DL1to DLm.

The data driver40selects reference voltages of the data signals according to the data control signals from the timing controller20, and supplies the selected reference voltages to the liquid crystal panel10to adjust a rotation angle of liquid crystal molecules. The power supply50generates and supplies source voltages to the timing controller20, the gate driver30and the data driver40. In addition, the power supply50generates and supplies a common voltage to the liquid crystal panel10.

When a power of the LCD device is off, the TFTs are also turned off. As a result, the data signals stored in the liquid crystal capacitor Clc and the storage capacitor Cst remain and are not discharged. Since the remaining data signals abnormally drives the liquid crystal panel for a short time, the liquid crystal panel displays undesired residual images or abnormal images.

SUMMARY OF THE INVENTION

Accordingly, embodiments of the invention is directed to a liquid crystal display device and a method of driving the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.

An object of the embodiments of the invention is to provide a liquid crystal display device and a method of driving the same that includes a discharging circuit for remaining data signals.

Another object of embodiments of the invention is to provide a liquid crystal display device and a method of driving the same that includes a voltage detecting integrated circuit (IC).

To achieve these and other advantages and in accordance with the purpose of embodiments of the invention, as embodied and broadly described, a driving circuit for driving a liquid crystal display device having a plurality of gate lines, data lines and switch elements connected to the gate and data lines includes a data driver for applying a plurality of data signals to the date lines, a gate driver for applying a plurality of gate signals to the gate lines, a timing controller for providing a plurality of control signals to the data and gate drivers, a power supply for generating a power voltage, and a discharging circuit for applying a first signal and a second signal to the gate driver in accordance with the power voltage.

In another aspect, a method for driving a liquid crystal display device having a plurality of gate lines, a plurality of data lines, a plurality of switch elements connected to the gate and data lines, and a gate driver for driving the gate lines includes generating a power voltage, detecting the power voltage, and when the power voltage is detected to be lower than a reference voltage, applying a first signal to the gate driver, the first signal corresponding to turning on all of the switching elements.

In another aspect, a method for driving a liquid crystal display device having a plurality of gate lines, a plurality of data lines, a plurality of switch elements connected to the gate and data lines, and a gate driver for driving the gate lines includes during an operation mode, generating a power voltage and enabling sequentially the switching elements in a row-by-row manner based on the power voltage, and after the operation mode when the power voltage is below a reference voltage, enabling all the switching elements synchronously for a discharging period.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings.

A liquid crystal display (LCD) device according to an embodiment of the invention includes a discharging circuit to solve the problems of the residual images or the abnormal images.FIG. 2is a circuit diagram schematically illustrating a discharging loop of remaining data signals in an LCD device according to an embodiment of the invention. InFIG. 2, after a power of the LCD device is off, a discharging circuit (not shown) applies an on-level gate voltage to a gate line GL during a predetermined time period and a thin film transistor (TFT) T is turned on. As a result, data signals remaining in a liquid crystal capacitor Clc and a storage capacitor Cst are discharged.

FIG. 3is a schematic diagram illustrating an LCD device according to an embodiment of the invention. InFIG. 3, an LCD device includes a liquid crystal panel100displaying images and a driving circuit160for the liquid crystal panel100. The liquid crystal panel100includes a plurality of gate lines GL1to GLn and a plurality of data lines DL1to DLm. The plurality of gate lines GL1to GLn cross the plurality of data lines DL1to DLm to define a plurality of pixel regions, and each pixel region includes a thin film transistor (TFT) T, a liquid crystal capacitor Clc and a storage capacitor Cst to display images.

The driving circuit160includes a timing controller120, a gate driver130, a data driver140, a power supply150and a discharging circuit190. The timing controller120generates gate control signals for the gate driver130including a plurality of gate integrated circuits (ICs) and data control signals for the data driver140including a plurality of data ICs using a plurality of external signal from an external system. The gate control signals may include a gate output enable signal GOE, a gate shift clock signal GSC and gate start pulse signal GSP, and the data control signals may include a source output enable signal SOE, a source sampling clock signal SSC, a polarity reverse signal POL and a source start pulse signal SSP. Moreover, the timing controller120outputs data signals Vdata to the data driver140. In addition, the timing controller120generates a flicker signal FLK and a DPM maintenance signal DPM_VCC for the discharging circuit190and supplies the flicker signal FLK, the DPM maintenance signal DPM_VCC and the gate shift clock signal GSC to the discharging circuit190.

The gate driver130controls ON/OFF operation of the thin film transistors (TFTs) in the liquid crystal panel100according to the gate control signals from the timing controller120. On-level gate voltages are sequentially applied to the gate lines GL1to GLn by a single horizontal synchronization time (1H) to enable the gate lines GL1to GLn and the TFTs connected to the gate lines GL1to GLn. When the TFTs corresponding to a single gate line are turned on, the data signals are applied to pixels in the pixel regions of the liquid crystal panel100through the data lines DL1to DLm.

The data driver140selects reference voltages of the data signals according to the data control signals from the timing controller120, and supplies the selected reference voltages to the liquid crystal panel100to adjust a rotation angle of liquid crystal molecules. The power supply150generates and supplies first, second and third source voltages VCC, VDD and GND to the timing controller120, the data driver140and the discharging circuit190. Further, the power supply150generates and supplies a gate high voltage VGH and a gate low voltage VGL to the gate driver130to turn on and off the TFTs and a common voltage Vcom to the liquid crystal panel100.

The discharging circuit190includes four partial circuits generating and maintaining a discharging signal ALL_H during a predetermined time period. For example, when the first source voltage VCC is lower than an off-reference voltage, the discharging circuit190generates and supplies the discharging signal ALL_H to the gate driver130. The off-reference voltage may be of 2.5 V. The gate driver130applies the gate high voltage VGH to all the gate lines GL1to GLn according to the discharging signal ALL_H to turn on all the TFTs. Moreover, the discharging circuit190generates a discharging maintenance signal VGH_M to maintain the discharging signal ALL_H during the predetermined time period and supplies the discharging maintenance signal VGH_M to the gate driver130. For example, the predetermined time period may be over than 3 msec.

FIG. 4is a block diagram schematically illustrating a discharging circuit for an LCD device according to an embodiment of the invention, andFIGS. 5A to 5Care circuit diagrams schematically illustrating first to third partial circuits, respectively, of a discharging circuit for an LCD device according to an embodiment of the invention. InFIG. 4, the discharging circuit190includes first, second, third and fourth partial circuits192,194,196and198and receives first, second and third source voltages VCC, VDD and GND. When the first source voltage VCC becomes lower than the off-reference voltage, the first partial circuit192outputs the discharging signal ALL_H to the gate driver120(ofFIG. 3). The off-reference voltage may be about 2.5 V.

As shown inFIG. 5A, for example, the first partial circuit192may include a first voltage detecting integrated circuit (IC)192a. The first voltage detecting IC192amay have a power source input terminal Vps, an output terminal Vout and a ground terminal Vgd. The first partial circuit192may further include a first capacitor C1and a first resistor R1connected to the first voltage detecting IC192a.

Referring again toFIG. 4, when the first source voltage VCC becomes lower than the off-reference voltage, the second partial circuit194generates and supplies a power modulating signal (DPM) maintenance signal DPM_VCC as a first varied flicker signal V_FLK1to the fourth partial circuit198. The DPM maintenance signal DPM_VCC maintains a power modulating signal DPM during the predetermined time period, where the power modulating signal DPM is used to control the source voltages. The power modulating signal that determines a starting timing of the data signals DPM may be about 1.6 V. For example, the source voltages may be applied when the power modulating signal DPM has a high level voltage and the source voltages may be not applied when the power modulating signal DPM has a low level voltage.

As shown inFIG. 5B, the second partial circuit194may include a second voltage detecting IC194a, a second capacitor C2, a second resistor R2, a third resistor R3and a first transistor T1. The second voltage detecting IC194amay have an output terminal Vout, a power source input terminal Vps and a ground terminal Vgd, and the first transistor T1may have a positive-negative-positive (PNP) bipolar type. Since the output terminal Vout of the second voltage detecting IC194ais connected to a base of the first transistor T1, the second voltage detecting IC194acontrols the first transistor T1and determines the DPM maintenance signal DPM_VCC as the first varied flicker signal V_FLK1through the first transistor T1. For example, when the first source voltage VCC is lower than the off-reference voltage, the DPM maintenance signal DPM_VCC is outputted from the second partial circuit194as the first varied flicker signal V_FLK1.

Referring back toFIG. 4, when the first source voltage VCC is higher than the off-reference voltage, the third partial circuit196generates and supplies a flicker signal FLK as a second varied flicker signal V_FLK2to the fourth partial circuit198. Accordingly, the third partial circuit196receives the flicker signal FLK and a gate shift clock signal GSC and controls the supply of the flicker signal FLK as the second varied flicker signal V_FLK2. The flicker signal FLK is used to prevent a flicker phenomenon in the liquid crystal panel. For example, a rear portion of a gate pulse may be reduced according to the flicker signal FLK, such that the gate pulse has a high level voltage in a long front section of a single period corresponding to the gate shift clock signal GSC and has a low level voltage in a short rear section of the single period. As a result, the third partial circuit196supplies the flicker signal FLK from the timing controller120(ofFIG. 3) as the second varied flicker signal V_FLK2to the fourth partial circuit198when the source voltage VCC is higher than the off-reference voltage, and does not supply the flicker signal FLK to the fourth partial198when the source voltage VCC is lower than the off-reference voltage. Alternatively, the gate shift clock signal GSC instead of the flicker signal FLK may be supplied as the second varied flicker signal V_FLK2.

As shown inFIG. 5C, the third partial circuit196may include a third voltage detecting IC196a, a third capacitor C3, fourth to eighth resistors R4to R8and a second transistor T2. The third voltage detecting IC196amay have an output terminal Vout, a power source input terminal Vps and a ground terminal Vgd, and the second transistor T2may have a negative-positive-negative (NPN) bipolar type. Since the output terminal Vout of the third voltage detecting IC196ais connected to a base of the second transistor T2, the third voltage detecting IC196acontrols the second transistor T2and determines the flicker signal FLK as the second varied flicker signal V_FLK2. For example, when the first source voltage VCC is higher than the off-reference voltage, the flicker signal FLK is outputted from the third partial circuit196as the second varied flicker signal V_FLK2. In addition, when the first source voltage VCC is lower than the off-reference voltage, the flicker signal FLK is not outputted from the third partial circuit196as the second varied flicker signal V_FLK2. Instead, the second partial circuit194outputs the DPM maintenance signal DPM_VCC as the first varied flicker signal V_FLK1.

Referring back toFIG. 4, the fourth partial circuit198that is a power block generates and supplies the discharging maintenance signal VGH_M according to the first and second varied flicker signals V_FLK1and V_FLK2to the gate driver130(ofFIG. 3). Accordingly, when the first source voltage VCC is higher than the off-reference voltage and the LCD device is powered on, the fourth partial circuit198modulates the gate signal with the flicker signal FLK to generate the discharging maintenance signal VGH_M and the discharging maintenance signal VGH_M is supplied to the gate driver130(ofFIG. 3) to operate the LCD device without flicker. When the first source voltage VCC is lower than the off-reference voltage and the LCD device is powered off, the fourth partial circuit198modulates the gate signal with the DPM maintenance signal DPM_VCC to generate the discharging maintenance signal VGH_M and the discharging maintenance signal VGH_M is supplied to the gate driver130(ofFIG. 3) to determine the predetermined time period for the discharging signal ALL_H. Although not shown, at least two of the first to third voltage detecting ICs192a,194aand196amay be formed as a single IC.

FIG. 6is a block diagram schematically illustrating a discharging circuit for an LCD device according to another embodiment of the invention, andFIGS. 7A and 7Bare circuit diagrams schematically illustrating first and second partial circuits, respectively, of a discharging circuit for an LCD device according to another embodiment of the invention. InFIG. 6, the discharging circuit290includes first, second and third partial circuits292,294and298and receives first, second and third source voltages VCC, VDD and GND. When the first source voltage VCC becomes lower than the off-reference voltage, the first partial circuit292outputs the discharging signal ALL_H to the gate driver (not shown). The off-reference voltage may be about 2.5 V. In addition, the second partial circuit294supplies the third partial circuit298with a flicker signal FLK from a timing controller (not shown) as a varied flicker signal V_FLK when the source voltage VCC is higher than the off-reference voltage and with a DPM maintenance signal DPM_VCC as the varied flicker signal V_FLK when the source voltage VCC is lower than the off-reference voltage. Similarly to the fourth partial circuit198(ofFIG. 4), the third partial circuit298that is a power block generates and supplies a discharging maintenance signal VGH_M according to the varied flicker signals V_FLK to the gate driver130(ofFIG. 3).

As shown inFIG. 7A, for example, the first partial circuit292may include a first voltage detecting integrated circuit (IC)292a. The first voltage detecting IC292amay have a power source input terminal Vps, an output terminal Vout and a ground terminal Vgd. The first partial circuit292may further include a first capacitor C11and a first resistor R11connected to the first voltage detecting IC292a.

As shown inFIG. 7B, for example, the second partial circuit294includes a voltage detecting integrated circuit (IC)292a, a second capacitor C12, second to fourth resistors R12to R14and first and second transistors T11and T12. The voltage detecting IC292ahas an output terminal Vout, a power source input terminal Vps and a ground terminal Vgd. In addition, the first transistor T11may have negative-positive-negative (NPN) bipolar type and the second transistor T12may have positive-negative-positive (PNP) bipolar type. A base of the first transistor T11is connected to the output terminal Vout of the voltage detecting IC292athrough the third resistor R13and the flicker signal FLK is inputted to a collector of the first transistor T11through the second resistor R12. Further, a base of the second transistor T12is connected to the output terminal of the voltage detecting IC292athrough the third resistor R13and the DPM maintenance signal DPM_VCC is inputted to an emitter of the second transistor T12. An emitter of the first transistor T11and a collector of the second transistor T12alternately output the flicker signal FLK and the DPM maintenance signal DPM_VCC as the varied flicker signals V_FLK. Accordingly, the collector of the first transistor T11and the emitter of the second transistor T12may be connected to the timing controller120(ofFIG. 3), and the emitter of the first transistor T11and the collector of the second transistor T12may be connected to the second partial circuit298(ofFIG. 6).

One of a high level voltage and a low level voltage may be outputted from the output terminal Vout of the voltage detecting IC292aaccording to the first source voltage VCC. A value of the varied flicker signal V_FLK of the first partial circuit292and states of the first and second transistors T11and T12according to the first source voltage VCC are shown is shown in TABLE 1.

In TABLE 1, the first source voltage VCC is higher than the off-reference voltage when the ON state and is lower than the off-reference voltage when the OFF state. In the ON state of the first source voltage VCC, the first transistor T11is turned on and the second transistor T12is turned off. In the OFF state of the first source voltage VCC, the first transistor T11is turned off and the second transistor T12is turned on. As a result, the first partial circuit292outputs the flicker signal FLK in the ON state of the first source voltage VCC and outputs the DPM maintenance signal DPM_VCC in the OFF state of the source voltage VCC as the varied flicker signal V_FLK. Accordingly, the first partial circuit292ofFIG. 6having a single voltage detecting IC292ahas the same function as the first, second and third partial circuits192,194and196ofFIG. 4having the first, second and third voltage detecting ICs192a,194aand196a.

FIG. 8is a block diagram schematically illustrating a discharging circuit for an LCD device according to another embodiment of the invention. Although not shown inFIG. 8, the LCD device includes a liquid crystal panel and driving circuit elements such as a timing controller, a gate driver, a data driver and a power supply. InFIG. 8, a discharging circuit390includes first and second partial circuits392and398and receives first, second and third source voltages VCC, VDD and GND. The first partial circuit392outputs a discharging signal ALL_H to the gate driver (not shown) when the first source voltage VCC is lower than an off-reference voltage. The off-reference voltage may be about 2.5 V. In addition, the first partial circuit392supplies the second partial circuit398with a flicker signal FLK from a timing controller (not shown) as a varied flicker signal V_FLK when the source voltage VCC is higher than the off-reference voltage and with a DPM maintenance signal DPM_VCC as the varied flicker signal V_FLK when the source voltage VCC is lower than the off-reference voltage. Similarly to the fourth partial circuit198(ofFIG. 4), the second partial circuit398that is a power block generates and supplies a discharging maintenance signal VGH_M according to the varied flicker signals V_FLK to the gate driver130(ofFIG. 3).

FIG. 9is a circuit diagram schematically illustrating a first partial circuit of a discharging circuit for an LCD device according to another embodiment of the invention. As shown inFIG. 9, the first partial circuit392includes a voltage detecting integrated circuit (IC)392a, a first capacitor C21, first to third resistors R21to R23and first and second transistors T21and T22. The voltage detecting IC292ahas an output terminal Vout, a power source input terminal Vps and a ground terminal Vgd. In addition, the first transistor T21may have negative-positive-negative (NPN) bipolar type and the second transistor T22may have positive-negative-positive (PNP) bipolar type. A base of the first transistor T21is connected to the output terminal Vout of the voltage detecting IC392athrough the second resistor R22and the flicker signal FLK is inputted to a collector of the first transistor T21through the first resistor R21. Further, a base of the second transistor T22is connected to the output terminal of the voltage detecting IC392athrough the second resistor R22and the DPM maintenance signal DPM_VCC is inputted to an emitter of the second transistor T22. An emitter of the first transistor T21and a collector of the second transistor T22alternately output the flicker signal FLK and the DPM maintenance signal DPM_VCC as the varied flicker signals V_FLK. Accordingly, the collector of the first transistor T21and the emitter of the second transistor T22may be connected to the timing controller120(ofFIG. 3), and the emitter of the first transistor T21and the collector of the second transistor T22may be connected to the second partial circuit398(ofFIG. 8).

One of a high level voltage and a low level voltage may be outputted from the output terminal Vout of the voltage detecting IC392aaccording to the first source voltage VCC. A value of the varied flicker signal V_FLK of the first partial circuit392and states of the first and second transistors T21and T22according to the first source voltage VCC are shown is shown in TABLE 2.

In TABLE 2, the first source voltage VCC is higher than the off-reference voltage when the ON state and is lower than the off-reference voltage when the OFF state. In the ON state of the first source voltage VCC, the first transistor T21is turned on and the second transistor T22is turned off. In the OFF state of the first source voltage VCC, the first transistor T21is turned off and the second transistor T22is turned on. As a result, the first partial circuit392outputs the flicker signal FLK in the ON state of the first source voltage VCC and outputs the DPM maintenance signal DPM_VCC in the OFF state of the source voltage VCC as the varied flicker signal V_FLK. Accordingly, the first partial circuit392ofFIG. 8having a single voltage detecting IC392ahas the same function as the first, second and third partial circuits192,194and196ofFIG. 4having the first, second and third voltage detecting ICs192a,194aand196a.

FIG. 10is a circuit diagram schematically illustrating a partial circuit of a discharging circuit for an LCD device according to another embodiment of the invention. As shown inFIG. 10, the first partial circuit492has elements similar to those of the first partial circuit392ofFIG. 9. Accordingly, the first partial circuit492includes a voltage detecting integrated circuit (IC)492a, a first capacitor C31, first to fourth resistors R31to R34and first and second transistors T31and T32. The voltage detecting IC492ahas an output terminal Vout, a power source input terminal Vps and a ground terminal Vgd. In addition, the first transistor T31may have negative-positive-negative (NPN) bipolar type and the second transistor T32may have positive-negative-positive (PNP) bipolar type.

In the first partial circuit492, at least one of the flicker signal FLK and the gate shirt clock signal GSC of the timing controller120(ofFIG. 3) is inputted to a collector of the first transistor T31through the first resistor R31and the fourth resistor R34, respectively. Accordingly, when the first source voltage VCC is higher than the off-reference voltage, the first transistor T31outputs at least one of the flicker signal FLK and the gate shift clock signal GSC as a varied flicker signal V_FLK. As a result, the first transistor T31and the second transistor T32alternately output the flicker signal FLK and the DPM maintenance signal DPM_VCC as the varied flicker signals V_FLK to a second partial circuit (not shown).

FIG. 11is a timing chart schematically illustrating a plurality of signals for driving an LCD device according to another embodiment of the invention. InFIG. 11, after a gate shift clock signal GSC followed by a predetermined delay time is enabled, a plurality of gate lines GL1to GLn are sequentially enabled synchronized with the gate shift clock signal GSC when a gate signal has a gate high voltage VGH. A gate output enable signal GOE divides the gate signals for the plurality of gate lines GL1to GLn. When the LCD device is off, a first source voltage VCC (ofFIG. 8) becomes lower than an off-reference voltage and a discharging circuit390(ofFIG. 8) outputs a discharging signal ALL_H having a low level voltage for a predetermined time period over about 3 msec. The off-reference voltage may be about 2.5V. As a result, all the plurality of gate lines GL1to GLn is enabled synchronously with the low level voltage of the discharging signal ALL_H. Accordingly, all the TFTs in the liquid crystal panel are turned on to discharge the pixels sufficiently.

At least one of the flicker signal FLK and the gate shift clock signal GSC synchronous with each other is used to generate a discharging maintenance signal VGH_M when the first source voltage VCC is higher than the off-reference voltage (ON state). In addition, a DPM maintenance signal DPM_VCC determining the predetermined time period for discharging is used to generate the discharging maintenance signal VGH_M when the first source voltage VCC is lower than the off-reference voltage (OFF state). Consequently, in the LCD device according to an embodiment of the invention, display of abnormal images is prevented due to a discharging circuit discharging the pixels after the LCD device is off. In addition, since the discharging circuit includes a single voltage detecting IC, the driving circuit of the LCD device is simplified and production cost of the LCD device is reduced.