SEMICONDUCTOR STRUCTURE WITH DIELECTRIC WALL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first well region and longitudinally oriented along a first direction and a second well region adjoining the first well region in a second direction. The semiconductor structure also includes a dielectric wall structure formed over a boundary between the first well region and the second well region and first channel structures vertically suspended over a first region of the first well region and laterally attached to a first sidewall surface of the dielectric wall structure. The semiconductor structure includes a first gate structure wrapping around the first channel structures and second channel structures vertically suspended over a second region of the first well region and a second gate structure wrapping around the second channel structures. In addition, the first channel structures is smaller than the second channel structures.

BACKGROUND

The electronics industry is experiencing ever-increasing demand for smaller and faster electronic devices that are able to perform a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). So far, these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such miniaturization has introduced greater complexity into the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.

Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). However, integration of fabrication of the multi-gate devices can be challenging.

DETAILED DESCRIPTION

The nanostructure transistors (e.g. nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nano-ribbon FET, forksheet structures, and gate all around (GAA) transistors) described below may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, smaller pitches than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the nanostructures.

Embodiments of semiconductor structures and methods for forming the same are provided. The semiconductor structures may include different types of channel structures (e.g. nanostructures) formed over a substrate. For example, a first type of channel structures (e.g. forksheet structures) may be attached to dielectric wall structures and may be narrower than a second type of channel structures (e.g. nanosheet structures). Since the first type of channel structures may be attached to the dielectric wall structure, the distance between the first type of channel structures may be relatively small, and the numbers of the transistors formed in a certain area may be increased. Meanwhile, the widths of the first type of channel structures cannot the too wide, or the formation of the first type of channel structures may be challenging (details will be described later).

On the other hand, the second type of channel structures may not have dielectric wall structures sandwiched therebetween, and therefore the formation of the second type of channel structures may be easier and the second type of channel structures may have greater widths, resulting in a higher performance. Accordingly, by forming both the first type and the second type of channel structures in the same substrate, the number of the transistors may be increased due to the formation of the first type of channel structures and the performance of some of the transistors may be improved by forming the second type of channel structures.

FIGS.1A-1to1D-1illustrate diagrammatic top views of intermediate stages of manufacturing a semiconductor structure100in accordance with some embodiments.FIGS.1A-2to1D-2illustrate the diagrammatic perspective views of the intermediate stages of manufacturing the semiconductor structure100shown in blocks B10and B20ofFIG.1A-1in accordance with some embodiments.FIGS.2A-1,2A-2, and2A-3illustrate the cross-sectional views of the intermediate stage of the semiconductor structure100shown inFIGS.1D-1and1D-2, andFIGS.2B-1to2M-1,2B-2to2M-2,2B-3to2M-3illustrate the cross-sectional views of the intermediate stages of manufacturing the semiconductor structure100afterwards in accordance with some embodiments. More specifically,FIGS.2A-1to2M-1illustrate the cross-sectional views of the intermediate stages of manufacturing the semiconductor structure100shown along lines Y1SD-Y1SD′ (i.e. in the Y direction) and Y2SD-Y2SD′ (i.e. in the Y direction) inFIG.1D-1in accordance with some embodiments.FIGS.2A-2to2M-2illustrate the cross-sectional views of the intermediate stages of manufacturing the semiconductor structure100shown along lines Y1MG-Y1MG′ (i.e. in the Y direction) and Y2MG-Y2MG′ (i.e. in the Y direction) inFIG.1D-1in accordance with some embodiments.FIGS.2A-3to2M-3illustrate the cross-sectional views of the intermediate stages of manufacturing the semiconductor structure100shown along lines X1—X1′ (i.e. in the X direction) inFIG.1D-1in accordance with some embodiments.

The semiconductor structure100may include multi-gate devices and may be included in a microprocessor, a memory, or other IC devices. For example, the semiconductor structure100may be a portion of an IC chip that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other applicable components, or combinations thereof.

First, a substrate102including a first region10and a second region20is formed in accordance with some embodiments. For a better understanding of the semiconductor structure100, the X-Y-Z coordinate reference is provided in the figures. The X-axis and the Y-axis are generally orientated along the lateral (or horizontal) directions that are parallel to the main surface of the substrate102. The Y-axis is transverse (e.g., substantially perpendicular/orthogonal) to the X-axis. The Z-axis is generally oriented along the vertical direction that is perpendicular to the main surface of the substrate102(or the X-Y plane).

The substrate102may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, the substrate102may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP.

A first well region W1and a second well region W2are formed in the substrate102, as shown inFIGS.1A-1and1A-2in accordance with some embodiments. In some embodiments, the first well region W1and the second well region W2include different types of dopants. In some embodiments, the first well region W1is an N-type well region doped with N-type dopants, and the second well region W2is a P-type well region doped with P-type dopants. In some embodiments, the first well region W1is a P-type well region doped P-type dopants, and the second well region W2is an N-type well region doped N-type dopants. In some embodiments, the N-type dopants include phosphorus, arsenic, other n-type dopants, or a combination thereof. In some embodiments, the P-type dopants include boron, indium, other p-type dopants, or a combination thereof. The P-type well region may be configured to have N-type transistors formed on it, and the N-type well region may be configured to have P-type transistors formed on it. In some embodiments, the first well region W1and the second well region W2are formed by performing ion implantation processes, diffusion processes, and/or other suitable doping processes.

As shown inFIG.1A-1, the first well region W1and the second well region W2are formed adjacent to each other in the Y direction and are both longitudinally oriented in the X direction in accordance with some embodiments. In some embodiments, the width WW1of the first well region W1is substantially equal to the width WW2of the second well region W2. The first well region W1may be divided into regions W1-1and W1-2, and the second well region W2may be divided into regions W2-1and W2-2, although they are shown for further explanation for the structure and no real interfaces are formed between the regions. In some embodiments, the widths WW1-1and WW1-2of the regions W1-1and W1-2are substantially half of the width WW1of the first well region W1. In some embodiments, the widths WW2-1and WW2-2of the regions W2-1and W2-2are substantially half of the width WW2of the second well region W2.

After the first well region W1and the second well region W2are formed, a semiconductor stack including first semiconductor material layers106and second semiconductor material layers108is formed over both the first region10and the second region20of the substrate102, as shown inFIGS.1B-1and1B-2in accordance with some embodiments.

In some embodiments, the first semiconductor material layers106and the second semiconductor material layers108are alternately stacked over the substrate102. In some embodiment, the first semiconductor material layers106and the second semiconductor material layers108are made of different semiconductor materials. In some embodiments, the first semiconductor material layers106are made of SiGe, and the second semiconductor material layers108are made of silicon. It should be noted that although four first semiconductor material layers106and three second semiconductor material layers108are shown inFIG.1B-2, the semiconductor stack may include less or more of the first semiconductor material layers106and the second semiconductor material layers108alternately stacked. For example, the semiconductor stack may include two to five of the first semiconductor material layers106and two to five of the second semiconductor material layers108.

The first semiconductor material layers106and the second semiconductor material layers108may be formed by using low-pressure chemical vapor deposition (LPCVD), epitaxial growth process, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

After the first semiconductor material layers106and the second semiconductor material layers108are formed as the semiconductor stack over the substrate102, the semiconductor stack and the substrate102are patterned to form fin structures104-1,104-2,104-3,104-4,104-5, and104-6, as shown inFIGS.1C-1and1C-2in accordance with some embodiments. The formation of the fin structures104-5and104-6and the elements around the fin structures104-5and104-6may be similar to, or the same as, those for forming the fin structures104-1and104-2and therefore are not repeated herein.

The fin structures104-1,104-2,104-3, and104-4may extend lengthwise along the X direction. More specifically, the fin structures104-1and104-2are formed in the first region10, and the fin structures104-3and104-4are formed in the second region20in accordance with some embodiments. In addition, the fin structures104-1and104-3are formed in the first well region W1, and the fin structures104-2and104-4are formed in the second well region W2in accordance with some embodiments. In some embodiments, the fin structure104-1is formed within the region W1-2of the first well region W1, and the fin structure104-2is formed within the region W2-1of the second well region W2. On the other hand, the fin structure104-3partially overlaps both the regions W1-1and W1-2of the first well region W1, and the fin structure104-4partially overlaps both the regions W2-1and W2-2of the second well region W2in accordance with some embodiments.

In some embodiments, the width W104-1of the fin structure104-1in the Y direction is substantially equal to the width W104-2of the fin structure104-2in the Y direction, and the width W104-3of the fin structure104-3in the Y direction is substantially equal to the width W104-4of the fin structure104-4in the Y direction. In some embodiments, the width W104-1of the fin structure104-1is smaller than the width W104-3of the fin structure104-3. In some embodiments, the width W104-3of the fin structure104-3is greater than two times of the width W104-1of the fin structure104-1. In some embodiments, the width W104-1of the fin structure104-1is in a range from about 1 nm to about 50 nm. In some embodiments, the distance DFSbetween the fin structures104-1and104-2in the Y direction is smaller than the distance DNSbetween the fin structures104-3and104-4in the Y direction.

In some embodiments, the patterning process for forming the fin structures104-1,104-2,104-3, and104-4includes forming a mask structure110over the semiconductor material stack, and etching the semiconductor material stack and the underlying substrate102through the mask structure110. In some embodiments, the mask structure110is a multilayer structure including a pad oxide layer and a nitride layer formed over the pad oxide layer. The pad oxide layer may be made of silicon oxide, which is formed by thermal oxidation or CVD, and the nitride layer may be made of silicon nitride, which is formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD). In some embodiments, the fin structures104-1,104-2,104-3, and104-4include base fin structures104B and the semiconductor stacks, including the first semiconductor material layers106and the second semiconductor material layers108formed over the base fin structures104B.

After the fin structures104-1,104-2,104-3, and104-4are formed, an isolation structure116is formed around the fin structures104-1,104-2,104-3, and104-4, as shown inFIGS.1D-1,1D-2,2A-1,2A-2, and2A-3in accordance with some embodiments. The isolation structure116is configured to electrically isolate active regions (e.g. the fin structures104-1,104-2,104-3, and104-4) of the semiconductor structure and is also referred to as shallow trench isolation (STI) feature in accordance with some embodiments. In some embodiments, the top surface of the portion of the isolation structure116between the fin structures104-1and104-2(i.e. DFS) is narrower than the top surface of the portion of the isolation structure116between the fin structures104-3and104-4(i.e. DNS) in the Y direction.

More specifically, an insulating layer may be formed around and covering the fin structures104-1,104-2,104-3, and104-4, and the insulating layer may be recessed to form the isolation structure116with the fin structures104-1,104-2,104-3, and104-4protruding from the top surface of the isolation structure116. In some embodiments, the insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In addition, liner layers (not shown) may be formed before forming the insulating layer, and the liner layers may also be recessed with the insulating layer to form the isolation structure116. In some embodiments, the liner layers include multiple dielectric material layers.

After the isolation structure116is formed, dielectric wall structures may be formed. More specifically, a dielectric shell layer118is conformally formed to cover the fin structures104-1,104-2,104-3, and104-4and the isolation structure116, and a core portion120is formed over the dielectric shell layer118, as shown inFIGS.2B-1,2B-2, and2B-3in accordance with some embodiments.

The dielectric shell layer118is configured to protect the dielectric wall structure in subsequent etching process. In some embodiments, the dielectric shell layer118covers the sidewalls and the top surfaces of the fin structures104-1,104-2,104-3, and104-4and the top surface of the isolation structure116. In some embodiments, the dielectric shell layer118is made of a nitride base dielectric materials such as SiN. In some embodiments, the dielectric shell layer118has a thickness in a range from about 3 nm to about 5 nm.

In some embodiments, the core portion120is made of a low k dielectric material, so that the capacitance of the resulting semiconductor device may be reduced. In some embodiments, the core portion120is made of an oxide base dielectric material, an oxynitride base dielectric material, or a flowable base dielectric material, such as SiO2. In some embodiments, the core portion120and the isolation structure116are made of the same material. The dielectric shell layer118and the core portion120may be deposited using CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other applicable methods, or combinations thereof.

In some embodiments, since the distance DFSis smaller than the distance DNS, the space between the fin structures104-1and104-2is substantially filled with the dielectric shell layer118and the core portion120, while the space between the fin structures104-3and104-4is not completely filled with the dielectric shell layer118and the core portion120in accordance with some embodiments.

Next, an etching process122is performed, as shown inFIGS.2C-1,2C-2, and2C-3in accordance with some embodiments. In some embodiments, the etching process122is performed without using a mask structure. During the etching process122, the removal of the core portion120and the dielectric shell layer118in the space between the fin structures104-1and104-2may be much slower than that in other places, since the space between the fin structures104-1and104-2is completely filled by the core portion120and the dielectric shell layer118while the top and sidewall surfaces of the core portion120in other regions are largely exposed. In other words, the removal of the core portion120and the dielectric shell layer118in other regions (e.g. in the spaces between the fin structures104-3and104-4) is faster than the removal of the core portion120and the dielectric shell layer118in the space between the fin structures104-1and104-2. Therefore, the core portion120and the dielectric shell layer118formed in the wider space are completely removed, and the core portion120and the dielectric shell layer118formed in the space between the fin structures104-1and104-2are only partially removed during the etching process in accordance with some embodiments. The remaining core portion120and the dielectric shell layer118form the bottom portion of the dielectric wall structure in accordance with some embodiments. In some other embodiments, the core portion120and the dielectric shell layer118are also partially etched during the etching process122. In some embodiments, the mask structures110formed over the fin structures104-1,104-2,104-3, and104-4are also partially etched during the etching process122. Accordingly, the heights of the mask structures110are reduced after the etching process122is performed in accordance with some embodiments.

Next, the dielectric shell layer118and the core portion120are recessed to form a recess, and a cap layer124is formed in the recess, as shown inFIGS.2D-1,2D-2, and2D-3in accordance with some embodiments. In some embodiments, the dielectric shell layer118and the core portion120are recessed by performing an etching process. In some embodiments, the etching process is an isotropic etching such as dry chemical etching, remote plasma etching, wet chemical etching, other applicable technique, and/or a combination thereof. In some embodiments, the cap layer124is made of a high k dielectric material, such as HfO2, ZrO2, HfAlOx, HfSiOx, Al2O3, or the like.

In some embodiments, the bottom surface of the cap layer124is lower than the topmost surface of the second semiconductor material layers108and is higher than the bottom surface of the topmost layer of the second semiconductor material layers108. In some other embodiments, the bottom surface of the cap layer124is substantially level with the topmost surface of the second semiconductor material layers108. In some other embodiments, the bottom surface of the cap layer124is higher than the topmost surface of the second semiconductor material layers108and is lower than the topmost surface of the first semiconductor material layers106.

A dielectric wall structure126, including the dielectric shell layer118, the core portion120, and the cap layer124, is formed between the fin structures104-1and104-2, as shown inFIGS.2D-1and2D-2in accordance with some embodiments. More specifically, the dielectric wall structure126is sandwiched between the fin structures104-1and104-2over the isolation structure116and is longitudinally oriented along the X direction in accordance with some embodiments.

FIG.2D-4illustrates a top view of the intermediate stage of manufacturing the semiconductor structure100in the step shown inFIGS.2D-1,2D-2, and2D-3in accordance with some embodiments. As shown inFIGS.2D-4, the fin structures104-1and104-2are attached to the opposite sides of the dielectric wall structure126in accordance with some embodiments. That is, the fin structures104-1and104-2are separated by the dielectric wall structure126, and therefore the distance DFSbetween the fin structures104-1and104-2may be relatively small. In some embodiments, the dielectric wall structure126is formed on the boundary between the first well region W1and the second well region W2and partially overlaps both the first well region W1and the second well region W2. In some embodiments, a numbers of dielectric wall structures126are formed at opposite sides of the boundaries of the first well region W1and the second well region W2, as shown inFIG.2D-4in accordance with some embodiments.

Afterwards, the remaining mask structures110are removed, and dummy gate structures130-1,130-2, and130-3are formed, as shown inFIGS.2E-1,2E-2, and2E-3in accordance with some embodiments.FIG.2E-4illustrates a top view of the intermediate stage of manufacturing the semiconductor structure100in the step shown inFIGS.2E-1,2E-2, and2E-3in accordance with some embodiments. More specifically, the dummy gate structure130-1is formed across the fin structures104-1and104-2and the dielectric wall structure126, the dummy gate structure130-2is formed across the fin structures104-3and104-4, and the dummy gate structure130-3is formed across the fin structures104-1,104-2,104-3, and104-4and the dielectric wall structure126, as shown inFIG.2E-4in accordance with some embodiments. The dummy gate structures130-1,130-2, and130-3may be used to define the channel regions of the transistors in the resulting semiconductor structure100.

In some embodiments, each of the dummy gate structures130-1,130-2, and130-3includes a dummy gate dielectric layer132and a dummy gate electrode layer134. In some embodiments, the dummy gate dielectric layer132is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or a combination thereof. In some embodiments, the dummy gate dielectric layer132is formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof.

In some embodiments, the dummy gate electrode layer134is made of conductive material includes polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), or a combination thereof. In some embodiments, the dummy gate electrode layer134is formed using CVD, PVD, or a combination thereof.

In some embodiments, a hard mask layer136is formed over the dummy gate electrode layer134. In some embodiments, the hard mask layer136includes multiple layers, such as an oxide layer and a nitride layer. In some embodiments, the oxide layer is silicon oxide, and the nitride layer is silicon nitride.

The formation of the dummy gate structures130-1,130-2, and130-3may include conformally forming a dielectric material as the dummy gate dielectric layers132. Afterwards, a conductive material may be formed over the dielectric material as the dummy gate electrode layers134, and the hard mask layer136may be formed over the conductive material. Next, the dielectric material and the conductive material may be patterned through the hard mask layer136to form the dummy gate structures130-1,130-2, and130-3.

After the dummy gate structures130-1,130-2, and130-3are formed, a spacer layer is formed to cover the top surfaces and the sidewalls of the dummy gate structures130-1,130-2, and130-3and the fin structures104-1,104-2,104-3, and104-4in accordance with some embodiments. Next, an etching process is performed to form gate spacers140and fin spacers142with the spacer layer and to form source/drain recesses144in the fin structures104-1,104-2,104-3, and104-4, as shown inFIGS.2F-1,2F-2, and2F-3in accordance with some embodiments. The gate spacers140may be configured to separate source/drain structures (formed afterwards) from the dummy gate structures130-1,130-2, and130-3, and the fin spacers142may be configured to confine the growth of the source/drain structures formed therein.

In some embodiments, the spacer layer is made one or more dielectric materials. The dielectric materials may include silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), and/or a combination thereof. After the spacer layer is formed, the spacer layer is etched to form the gate spacers140on opposite sidewall surfaces of the dummy gate structures130-1,130-2, and130-3, and fin spacers142are formed on the opposite sidewall surfaces of the fin structures104-1,104-2,104-3, and104-4by performing an etching process in accordance with some embodiments. In addition, the fin structures104-1,104-2,104-3, and104-4not covered by the dummy gate structures130-1,130-2, and130-3and the gate spacers140are further etched to form the source/drain recesses144, as shown inFIGS.2F-1and2F-3in accordance with some embodiments. The etching process may be an anisotropic etching process, such as dry plasma etching, and the dummy gate structures130-1,130-2, and130-3and the gate spacers140may be used as etching masks during the etching process. In some embodiments, the isolation structure116is also slightly etched during the etching process.

After the source/drain recesses144are formed, the first semiconductor material layers106exposed by the source/drain recesses144are laterally recessed to form notches146, as shown inFIGS.2G-1,2G-2, and2G-3in accordance with some embodiments. In some embodiments, an etching process is performed to laterally recess the first semiconductor material layers106of the fin structure104-1,104-2,104-3, and104-4from the source/drain recesses144. In some embodiments, during the etching process, the first semiconductor material layers106have a greater etching rate (e.g. etching amount) than the second semiconductor material layers108, thereby forming notches146between the adjacent second semiconductor material layers108. In some embodiments, the second semiconductor material layers108are also slightly etched during the etching process, so that the portions of the second semiconductor material layers108exposed by the notches146become thinner than other portions, as shown inFIG.2G-3in accordance with some embodiments. In some embodiments, the etching process is an isotropic etching such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, and/or a combination thereof.

Next, inner spacers148are formed in the notches146between the second semiconductor material layers108, as shown inFIGS.211-1,211-2, and211-3in accordance with some embodiments. The inner spacers148may be configured to separate the source/drain structures and the gate structures formed in subsequent manufacturing processes. As described previously, since the second semiconductor material layers108are also partially etched when forming the notches146, the inner spacers148formed in the notches146are thicker than the thicknesses of the first semiconductor material layers106in accordance with some embodiments. In addition, the inner spacers148have curve sidewalls in accordance with some embodiments. In some embodiments, the inner spacers148are made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or a combination thereof.

After the inner spacers148are formed, source/drain structures150-1,150-2,150-3, and150-4are formed in the source/drain recesses144of the fin structures104-1,104-2,104-3, and104-4respectively, as shown inFIGS.2I-1,2I-2, and2I-3in accordance with some embodiments. The source/drain structures described below may refer to a source or a drain, individually or collectively dependent upon the context.

In some embodiments, the source/drain structures150-1and150-2and the source/drain structures150-3and150-4have different shapes. More specifically, the source/drain structures150-1and150-2are formed over the fin structures104-1and104-2and are sandwiched between one fin spacer142and the dielectric wall structure126with the dielectric wall structure126being higher than the fin spacer142in accordance with some embodiments. Therefore, the source/drain structures150-1and150-2have asymmetry shapes in the cross-sectional view in the Y direction in accordance with some embodiments. Each of the source/drain structures150-1and150-2may have a first side and a second side opposite the first side and has a substantially straight sidewall at the second side and a curved sidewall at the first side in accordance with some embodiments. The substantially straight sidewall at the second side may be in direct contact with the dielectric wall structure126, and the curved sidewall at the first side extends laterally outside the outer sidewalls of the fin spacer142in accordance with some embodiments.

On the other hand, the source/drain structures150-3and150-4are formed over the fin structures104-3and104-4and are sandwiched between the fin spacers142in accordance with some embodiments. Since both sides of the source/drain structures150-3and150-4are confined by the fin spacers142, the source/drain structures150-3and150-4have substantially symmetry shapes in the cross-sectional view along the Y direction in accordance with some embodiments.

In some embodiments, the top surface of the dielectric wall structure126is higher than the topmost portions of the source/drain structures150-1,150-2,150-3, and150-4. In some embodiments, the topmost portions of the source/drain structures150-3and150-4are higher than the topmost portions of the source/drain structures150-1and150-2. In some embodiments, the source/drain structures150-1,150-2,150-3, and150-4are all substantially the same height. In addition, since the fin structures104-1and104-2are narrower than the fin structures104-3and104-4, the source/drain structures150-1and150-2are also narrower than the source/drain structures150-3and150-4in accordance with some embodiments.

In some embodiments, the source/drain structures150-1,150-2,150-3, and150-4are formed using an epitaxial growth process, such as MBE, MOCVD, VPE, other applicable epitaxial growth process, or a combination thereof. In some embodiments, the source/drain structures150-1,150-2,150-3, and150-4are made of any applicable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof. In some embodiments, the source/drain structures150-1,150-2,150-3, and150-4are in-situ doped during the epitaxial growth process. For example, the source/drain structures150-1,150-2,150-3, and150-4may be the epitaxially grown SiGe doped with boron (B). For example, the source/drain structures150-1,150-2,150-3, and150-4may be the epitaxially grown Si doped with carbon to form silicon:carbon (Si:C) source/drain features, phosphorous to form silicon:phosphor (Si:P) source/drain features, or both carbon and phosphorous to form silicon carbon phosphor (SiCP) source/drain features. In some embodiments, the source/drain structures150-1,150-2,150-3, and150-4are doped in one or more implantation processes after the epitaxial growth process.

After the source/drain structures150-1,150-2,150-3, and150-4are formed, a contact etch stop layer (CESL)160is conformally formed to cover the source/drain structures150-1,150-2,150-3, and150-4, and an interlayer dielectric (ILD) layer162is formed over the contact etch stop layers160, as shown inFIGS.2J-1,2J-2, and2J-3in accordance with some embodiments. In some embodiments, the contact etch stop layer160is in direct contact with the sidewalls of the dielectric shell layers118and the top surface of the cap layer124of the dielectric wall structures126.

In some embodiments, the contact etch stop layer160is made of a dielectric materials, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the contact etch stop layers160may be conformally deposited over the semiconductor structure by performing CVD, ALD, other application methods, or a combination thereof.

The interlayer dielectric layer162may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or other applicable low-k dielectric materials. The interlayer dielectric layer162may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or other applicable processes.

After the contact etch stop layer160and the interlayer dielectric layer162are deposited, a planarization process such as CMP or an etch-back process is performed until the dummy gate electrode layer134is exposed, as shown inFIGS.2J-2and2J-3in accordance with some embodiments.

Next, the dummy gate structures130-1,130-2, and130-3and the first semiconductor material layers106of the fin structures104-1,104-2,104-3, and104-4are removed to form gate trenches166-1,166-2, and166-3, as shown inFIGS.2K-1,2K-2, and2K-3in accordance with some embodiments.FIG.2K-4illustrates a top view of the intermediate stage of manufacturing the semiconductor structure100in the step shown inFIGS.2K-1,2K-2, and2K-3in accordance with some embodiments. More specifically, the dummy gate structures130-1,130-2, and130-3and the first semiconductor material layers106are removed to form channel structures (e.g. nanostructures)108′-1,108′-2,108′-3, and108′-4with the second semiconductor material layers108of the fin structures104-1,104-2,104-3, and104-4respectively in accordance with some embodiments. Although not shown in the figures, the channel structures108′-1,108′-2,108′-3, and108′-4and the base fin structures104B may have rounded corners.

The removal process may include one or more etching processes. For example, when the dummy gate electrode layer134is made of polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layer134. Afterwards, the dummy gate dielectric layer132may be removed using a plasma dry etching, a dry chemical etching, and/or a wet etching. The first semiconductor material layers106may then be removed by performing a selective wet etching process, such as APM (e.g., ammonia hydroxide-hydrogen peroxide-water mixture) etching process. For example, the wet etching process uses etchants such as ammonium hydroxide (NH4OH), TMAH, ethylenediamine pyrocatechol (EDP), and/or potassium hydroxide (KOH) solutions.

During the removal of the first semiconductor material layers106, the first semiconductor material layers106of the fin structures104-3and104-4may be removed from both sidewalls of the fin structures104-3and104-4. However, the first semiconductor material layers106of the fin structures104-1and104-2can only be removed from one side of the fin structures104-1and104-2, since another side of the fin structures104-1and104-2are attached to the dielectric wall structure126. Therefore, the removal of the first semiconductor material layers106for the fin structures104-1and104-2may be more difficult than that for the fin structures104-3and104-4. Accordingly, the fin structures104-1and104-2may be relatively narrow, compared to the fin structures104-3and104-4, so that the first semiconductor material layers106of the fin structures104-1and104-2may be fully removed. On the other hand, since the first semiconductor material layers106of the fin structures104-3and104-4may be removed from both sides of the fin structures104-3and104-4, the widths of the fin structures104-3and104-4may be relatively wide.

As shown inFIG.2K-2, the channel structures108′-1,108′-2,108′-3, and108′-4are vertically suspended and spaced apart from each other in the Z direction in accordance with some embodiments. In addition, the top surface, the bottom surface, and the two sidewalls of each of the channel structures108′-3and108′-4in the channel region are fully exposed by the gate trench166-2in accordance with some embodiments. On the other hand, although the top surface and the bottom surface of each of the channel structures108′-1and108′-2are also exposed by the gate trench166-1, only one sidewall of each of the channel structures108′-1and108′-2is exposed by the gate trench166-1in the cross-sectional view along the Y direction in accordance with some embodiments. More specifically, one sidewall of each of the channel structures108′-1and108′-2is laterally attached to a sidewall surface of the dielectric wall structure126and is not exposed by the gate trench166-1in accordance with some embodiments. Meanwhile, the portions of the sidewall of the dielectric wall structure126not attached to the channel structures108′-1and108′-2are exposed by the gate trench166-1in accordance with some embodiments. The first semiconductor material layers106of the fin structures104-5and104-6may also be removed to form nanostructures108′-5and108′-6, which may have the same structures with the nanostructures108′-1and108′-2.

Next, gate structures168-1,168-2, and168-3are formed in the gate trenches166-1,166-2, and166-3, as shown inFIGS.2L-1,2L-2, and2L-3in accordance with some embodiments.FIG.2L-4illustrates a top view of the intermediate stage of manufacturing the semiconductor structure100in the step shown inFIGS.2L-1,2L-2, and2L-3in accordance with some embodiments. The gate structures168-1,168-2, and168-3are longitudinally oriented along the Y direction.

In some embodiments, each of the gate structures168-1,168-2, and168-3includes a gate dielectric layer170and a gate stack172. Interfacial layers (not shown) may also be formed around the channel structures108′-1,108′-2,108′-3, and108′-4and on the exposed portions of the base fin structure104B. In some embodiments, the interfacial layers are oxide layers formed by performing a thermal process.

In some embodiments, the gate dielectric layers170are conformally formed in the gate trenches166-1,166-2, and166-3. In some embodiments, the gate dielectric layers170wrap around the channel structures108′-1,108′-2,108′-3, and108′-4and cover the sidewalls of the dielectric shell layer118and the top surface of the cap layer124of the dielectric wall structure126in accordance with some embodiments.

In some embodiments, the gate dielectric layers170are made of one or more layers of dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other applicable high-k dielectric materials, or a combination thereof. In some embodiments, the gate dielectric layers170are formed using CVD, ALD, other applicable methods, or a combination thereof.

In some embodiments, the gate stacks172are formed over the gate dielectric layers170. In some embodiments, the gate stacks172are made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof. In some embodiments, the gate stacks172are formed using CVD, ALD, electroplating, another applicable method, or a combination thereof.

In some embodiments, the gate structures168-1,168-2, and168-3include different conductive layers in different portions. For example, portions168-1-1,168-2-1, and168-3-1of the gate structures168-1,168-2, and168-3over the first well region W1may include a first type of work function metal layers, and portions168-1-2,168-2-2, and168-3-2of the gate structures168-1,168-2, and168-3over the second well region W2may include a second type of work function metal layers. In some embodiments, the first well region W1is an N-type well region, the second well region W2is a P-type well region, the portions168-1-1,168-2-1, and168-3-1include P-type metal layers, and the portions168-1-2,168-2-2, and168-3-2include N-type metal layers. In some other embodiments, the first well region W1is a P-type well region, the second well region W2is an N-type well region, the portions168-1-1,168-2-1, and168-3-1include N-type metal layers, and the portions168-1-2,168-2-2, and168-3-2include P-type metal layers.

For example, a first type of work function metal layers may first be formed in the gate trenches166-1,166-2, and166-3, and then the portions of the first type of work function metal layers formed over the second well region W2may be removed. Next, a second type of work function metal layers may be formed in the gate trenches166-1,166-2, and166-3, and a gate electrode layers may be formed over the second type of work function metal layers. Afterwards, a planarization process, such as CMP, may be performed until the interlayer dielectric layer162is exposed, thereby forming the gate structures168-1,168-2, and168-3. In some other embodiments, the portions of the second type of metal layers over the first well region W1are removed before forming the gate electrode layer.

After the gate structures168-1,168-2, and168-3are formed, silicide layers180and source/drain contacts182are formed over the source/drain structures150-1,150-2,150-3, and150-4, as shown inFIGS.2M-1,2M-2, and2M-3in accordance with some embodiments.FIG.2M-4illustrates the top view of the semiconductor structure100in accordance with some embodiments.FIG.2M-5illustrates the cross-sectional view of the semiconductor structure100shown along lines X2—X2′ (i.e. in the X direction) inFIG.2M-4in accordance with some embodiments.FIG.2M-6illustrates the cross-sectional view of the semiconductor structure100shown along lines X3—X3′ (i.e. in the X direction) inFIG.2M-4in accordance with some embodiments.

More specifically, contact trenches may be formed through the contact etch stop layer160and the interlayer dielectric layer162to expose the source/drain structures150-1,150-2,150-3, and150-4. Afterwards, the silicide layers180are formed over the exposed portions of the source/drain structures150-1,150-2,150-3, and150-4, and the source/drain contacts182are formed in the contact trenches over the silicide layers180, as shown inFIGS.2M-1,2M-3,2M-4,2M-5, and2M-6in accordance with some embodiments.

The silicide layers180may be formed by forming a metal layer over the top surface of the source/drain structures150-1,150-2,150-3, and150-4and annealing the metal layer so the metal layer reacts with the source/drain structures150-1,150-2,150-3, and150-4to form the silicide layers180. The unreacted metal layer may be removed after the silicide layers180are formed.

The source/drain contacts182may further include a liner and/or a barrier layer. For example, a liner (not shown) may be formed on the sidewalls and bottom of the contact trench. The liner may be made of silicon nitride, although any other applicable dielectric may be used as an alternative. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other applicable processes, such as physical vapor deposition or a thermal process, may be used as an alternative. The barrier layer (not shown) may be formed over the liner (if present) and may cover the sidewalls and bottom of the opening. The barrier layer may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition processes. The barrier layer may be made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used.

As described previously, the semiconductor structure100includes the first well region W1and the second well region W2, and the first well region W1and the second well region W2are longitudinally oriented along the X direction and are adjoined with each other in the Y direction.

In the first region10, the channel structures108′-1and108′-5are formed in the first well region W1and the channel structures108′-2and108′-6are formed in the second well region W2in accordance with some embodiments. In the second region, the channel structures108′-3is formed in the first well region W1and the channel structures108′-4is formed in the second well region W2in accordance with some embodiments. In some embodiments, the channel structures108′-1,108′-2,108′-3, and108′-4are spaced apart from the boundary between the first well region W1and the second well region W2.

In addition, the dielectric wall structures126are formed over the boundary of the first well region W1and the second well region W2in the first region10and partially cover both the first well region W1and the second well region W3, as shown inFIGS.2M-1,2M-2, and2M-4in accordance with some embodiments. The dielectric wall structures126may be configured to separate neighboring channel structures108′-1and108′-2, and the structures may be referred as forksheet structures. Since the channel structures108′-1and108′-2are separated by the dielectric wall structure126, the distance between the channel structures108′-1and108′-2may be relatively small. On the other hand, the channel structures108′-3and108′-4without the dielectric wall structures126formed between them may be referred as nanosheet structures for clarity.

In some embodiments, the distance DNSbetween the channel structures108′-3and108′-4is greater than the distance DFSbetween the channel structures108′-1and108′-2(i.e. the width W126of the dielectric wall structure126) in the Y direction. In some embodiments, the channel structure108′-3and/or channel structure108′-4is spaced a distance DBNSapart from the boundary of the first well region W1and the second well region W2, the channel structure108′-1and/or108′-2is spaced a distance DBFSapart from the boundary of the first well region W1and the second well region W2, and the distance DBNSis greater than the distance DBFS, as shown inFIG.2M-2.

The gate structure168-1abuts channel structures108′-1,108′-2,108′-5, and108′-6to form transistors T1, T2, T5, and T6, respectively, and the gate structures168-2abut the channel structures108′-3and108′-4to form transistors T3and T4, respectively, in accordance with some embodiments. Meanwhile, the gate structure168-3may be a dummy gate structure without an actual electrical function. In some embodiments, a portion168-3-1of the gate structure168-3surrounds and makes direct contact with the end portions of the channel structures108′-3, as shown inFIG.2M-5. Similarly, a portion168-3-2of the gate structure168-3surrounds and makes direct contact with the end portions of the channel structures108′-1, as shown inFIG.2M-6in accordance with some embodiments. In addition, since the sidewalls of the channel structures108′-1and108′3are not aligned in the X direction, some portion of the gate structure168-1is located over isolation structure116in the cross-sectional view shown inFIG.2M-5and the portion of the gate structure168-2is located over isolation structure116in the cross-sectional view shown inFIG.2M-6in accordance with some embodiments.

In some embodiments, the first region10of the first well region W1and the second well region W2may be seem as a first unit, the second region20of the first well region W1and the second well region W2may be seem as a second unit, and the first unit and the second unit substantially have the same size. In some embodiments, the amount of the transistors formed in the first unit is greater than the amount of the transistors formed in the second unit. In some embodiments, four transistors T1, T2, T5, and T6can be formed in the first region10, while two transistors T3and T4are formed in the second unit.

In some embodiments, the width Ww1of the first well region W1is substantially equal to the width WW2of the second well region W2. In some embodiments, the width W108′-1of the channel structures108′-1is substantially equal to the width W108′-2of the channel structures108′-2. In some embodiments, the width W108′-3of the channel structures108′-3is substantially equal to the width W108′-4of the channel structures108′-4.

In some embodiments, the width Ww1of the first well region W1is greater than the width W108′-3of the channel structures108′-3, the width W108′-3of the channel structures108′-3is greater than half of the width Ww1of the first well region W1, and half of the width Ww1of the first well region W1is greater than the width W108′-1of the channel structures108′-1. Similarly, the width Ww2of the second well region W2is greater than the width W108′-4of the channel structures108′-4, the width W108′-4of the channel structures108′-4is greater than half of the width Ww2of the second well region W2, and half of the width Ww2of the second well region W2is greater than the width W108′-2of the channel structures108′-2in accordance with some embodiments.

In some embodiments, the width Ww1of the first well region W1is greater than the sum of the width W108′-1of the channel structures108′-1, the width W108′-2of the channel structures108′-2, and the width W126of the dielectric wall structure126. In some embodiments, the width W108′-3of the channel structures108′-3is greater than two times of the width W108′-1of the channel structures108′-1. In some embodiments, half of the width Ww1of the first well region W1is greater than the width W108′-1of the channel structures108′-1.

Since the dielectric wall structures126are formed, the channel structures in the forksheet structures may have a greater density, and the size of the device may be decreased. However, during the formation of the forksheet structures (e.g. channel structures108′-1,108′-2,108′-5, and108′-6), one sides of the fin structures (e.g. the fin structures104-1,104-2,104-5, and104-6) are attached to the dielectric wall structures126. Therefore, the first semiconductor material layers106of the fin structures need to be removed through the side not attached to the dielectric wall structures126(i.e. the processes shown inFIGS.2K-1,2K-2,2K-3, and2K-4). Accordingly, the channel structures in the forksheet structures may not be too wide, or the removal of the first semiconductor material layers106of the fin structures may be challenging.

On the other hand, since the first semiconductor material layers106of the fin structures104-3and104-3may be removed from two sides of the structure, the channel structures108′-3and108′-4may have a greater width without considering the removal of the first semiconductor material layers106. Therefore, the resulting transistors T3and T4may have improved performance.

FIGS.3A-1to3C-1,3A-2to3C-2, and3A-3to3C-3illustrate cross-sectional views of intermediate stages of manufacturing a semiconductor structure100ain accordance with some embodiments.FIGS.3A-4to3C-4illustrates the top views of the intermediate stages of manufacturing the semiconductor structure100ain accordance with some embodiments. More specifically,FIGS.3A-1to3C-1illustrate the cross-sectional views of the intermediate stages of manufacturing the semiconductor structure100ashown along lines Y1SDa-Y1SDa′ (i.e. in the Y direction) and Y2SDa-Y2SDa′ (i.e. in the Y direction) inFIGS.3A-4to3C-4in accordance with some embodiments.FIGS.3A-2to3C-2illustrate the cross-sectional views of the intermediate stages of manufacturing the semiconductor structure100ashown along lines Y1MGa-Y1MGa′ (i.e. in the Y direction) and Y2MGa-Y2MGa′ (i.e. in the Y direction) inFIGS.3A-4to3C-4in accordance with some embodiments.FIGS.3A-3to3C-3illustrate the cross-sectional views of the intermediate stages of manufacturing the semiconductor structure100ashown along lines X1a—X1a′ (i.e. in the X direction) inFIGS.3A-4to3C-4in accordance with some embodiments.

The semiconductor structure100amay be similar to the semiconductor structure100described previously, except one of the dummy gate structure (i.e. the dummy gate structure130-3shown inFIGS.2E-1,2E-2,2E-3, and2E-4) is replaced with a dielectric structure in accordance with some embodiments. Some processes and materials for forming the semiconductor structure100amay be similar to, or the same as, those for forming the semiconductor structure100described previously and are not repeated herein.

More specifically, the processes shown inFIGS.2A-1to2J-1,2A-2to2J-2, and2A-3to2J-3are performed, and the dummy gate structure130-3(as shown inFIGS.2J-3) is removed to form a gate trench166a-3, as shown inFIGS.3A-1,3A-2,3A-3, and3A-4in accordance with some embodiments. In addition, the first semiconductor material layers106and the second semiconductor material layers108and some portions of the first well region W1and the second well region W2under the dummy gate structure130-3are also removed in accordance with some embodiments. As shown inFIG.3C-3, the inner spacers148and portions of the second semiconductor material layers108are exposed by the gate trench166a-3in accordance with some embodiments. The gate trench166a-3may be formed by performing multiple etching processes.

After the gate trench166a-3is formed, a dielectric structure169is formed in the gate trench166a-3, as shown inFIGS.3B-1,3B-2,3B-3, and3B-4in accordance with some embodiments. The dielectric structure169may be formed by depositing a dielectric material in the gate trench166a-3, and polishing the dielectric material until exposing the dummy gate structures130-1and130-2. The dielectric material may be a low k material, such as SiO2, SiN, SiCN, SiOC, SiOCN, or the like.

Afterwards, the processes shown inFIGS.2K-1to2M-1,2K-2to2M-2, and2K-3to2M-3are performed to form the semiconductor structure100a, as shown inFIGS.3C-1,3C-2,3C-3, and3C-4in accordance with some embodiments.FIG.3C-5illustrates the cross-sectional view of the semiconductor structure100ashown along lines X2—X2′ (i.e. in the X direction) inFIG.3C-4in accordance with some embodiments.FIG.3C-6illustrates the cross-sectional view of the semiconductor structure100ashown along lines X3—X3′ (i.e. in the X direction) inFIG.3C-4in accordance with some embodiments.

In some embodiments, the bottommost portion of the dielectric structure169is lower than the top surfaces of the first well region W1and the second well region W2. In some embodiments, the bottommost portion of the dielectric structure169is higher than the bottom surface of the first well region W1and the second well region W2but is lower than the bottom surface of the isolation structure116, as shown inFIGS.3C-5and3C-6in accordance with some embodiments. In some other embodiments, the dielectric structure169is higher than the bottom surface of the isolation structure116. In some embodiments, the dielectric structure169and the isolation structure116are made of different materials.

Since the dielectric structure169is formed by replacing the dummy gate structure130-3, the width W169of the dielectric structure169in the X direction is substantially equal to the widths W168-1and W168-2of the gate structures168-1and168-2in the X direction in accordance with some embodiments. In addition, the top surfaces of the dielectric structure169and the gate structures168-1and168-2are substantially level with each other, while the bottom surface of the dielectric structure169is lower than the bottom surfaces of the gate structures168-1and168-2.

FIG.4Aillustrates a top view of a semiconductor structure100bin accordance with some embodiments.FIG.4Billustrate the cross-sectional view of the semiconductor structure100bshown along lines Y1SDb-Y1SDb′ (i.e. in the Y direction) and Y2SDb-Y2SDb′ (i.e. in the Y direction) inFIG.4Ain accordance with some embodiments.FIG.4Cillustrates the cross-sectional view of the semiconductor structure100bshown along lines Y1MGb-Y1MGb′ (i.e. in the Y direction) and Y2MGb-Y2MGb′ (i.e. in the Y direction) inFIG.4Ain accordance with some embodiments.FIG.4Dillustrate the cross-sectional view of the semiconductor structure100bshown along lines X1b—X1b′ (i.e. in the X direction) inFIG.4Ain accordance with some embodiments.FIG.4Eillustrate the cross-sectional view of the semiconductor structure100bshown along lines X2b—X2b′ (i.e. in the X direction) inFIG.4Ain accordance with some embodiments.FIG.4Fillustrate the cross-sectional view of the semiconductor structure100bshown along lines X3b—X3b′ (i.e. in the X direction) inFIG.4Ain accordance with some embodiments.

The semiconductor structure100bmay be similar to the semiconductor structure100described previously, except the channel structures attached to dielectric wall structures (e.g. the forksheet structures) are separated from the channel structures without the dielectric wall structures (e.g. the nanosheet structures) in accordance with some embodiments. Some processes and materials for forming the semiconductor structure100bmay be similar to, or the same as, those for forming the semiconductor structure100described previously and are not repeated herein.

More specifically, channel structures108′-3band108′—of fin structures104-3band104-4bare formed in the first well region W1and the second well region W2respectively in accordance with some embodiments. The processes and materials for forming the channel structures108′-3band108′-4b(and the fin structures104-3band104-4b) may be similar to, or the same as, those for forming the channel structures108′-3and108′-4(and the fin structures104-3and104-4) described previously, except the channel structures108′-3bare spaced apart from the channel structures108′-1and the channel structures108′-4bare spaced a distance PSPapart from the channel structures108′-2in the X direction, as shown inFIGS.4A and4Din accordance with some embodiments.

In some embodiments, a gate structure168-2bsurrounds the end portions of the channel structures108′-3band108′-4b, and a gate structure168-3bsurrounds the end portions of the channel structures108′-1and108′-2, as shown inFIGS.4A,4D,4E, and4Fin accordance with some embodiments. That is, the channel structures108′-3band108′-4blaterally extends into the gate structure168-2bbut do not pass through the gate structure168-2bin the top view in accordance with some embodiments. Similarly, the channel structures108′-1and108′-2laterally extends into the gate structure168-3bbut do not pass through the gate structure168-3bin the top view in accordance with some embodiments. In some embodiments, the distance PSPbetween the channel structures108′-3band the channel structures108′-1is about one to five times of the distance PMGbetween the central of the gate structure168-1and the central of the gate structure168-3bin the X direction, as shown inFIG.4A. By keeping the distance PSP, the resulting transistors may have improved isolation. The processes and materials for forming the gate structures168-2band168-3bmay be similar to, or the same as, those for forming the gate structures168-2and168-3and are not repeated herein.

In addition, dummy contacts183are formed between the gate structures168-3band168-2b, although there are not electrically connected to the channel structures108′-1,108′-2,108′-3b, and108′-4bin accordance with some embodiments. In some embodiments, the dummy contacts183are located between the source/drain contacts182in the first region10and in the second region20. The dummy contacts183may be formed using the same processes and materials for forming the source/drain contacts182. In some other embodiments, dummy contacts183are not formed.

FIG.5illustrates a top view of an arrangement of the first well regions W1and the second well regions W2of a substrate102W in accordance with some embodiments. More specifically, the first well regions W1and the second well region W2are the first well regions and the second well regions are arranged in an alternating manner in the Y direction in the substrate102W in accordance with some embodiments. In some embodiments, the width WW1of the first well regions W1is substantially equal to the width WW2of the second well regions W2. Each of the first well regions W1may include portions W1-1and W1-2having the same width, and each of the second well regions W2may include portions W2-1and W2-2having the same width. The substrate102W may be the same as the substrate102described previously. The forksheet structures and the nanosheet structures may be arranged over the substrate102W in different ways. For examples, the forksheet structures and the nanosheet structures are arranged over the substrate102W in both the X direction and the Y direction.

FIG.6Aillustrates a top view of a semiconductor structure100cformed over the substrate102W shown inFIG.5in accordance with some embodiments.FIG.6Billustrate the cross-sectional view of the semiconductor structure100cshown along lines YSDc-YSDc′ (i.e. in the Y direction) inFIG.6Ain accordance with some embodiments.FIG.6Cillustrates the cross-sectional view of the semiconductor structure100cshown along lines YMGc-YMGc′ (i.e. in the Y direction) inFIG.6Ain accordance with some embodiments.FIG.6Ahas been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features may be included in the semiconductor structure100c, and some of the features described below may be replaced, modified, or eliminated. The semiconductor structure100cmay be similar to the semiconductor structure100described previously, except the channel structures attached to dielectric wall structures (e.g. the forksheet structures) are further formed in the second region20in accordance with some embodiments.

More specifically, channel structures108′-1cand108′-2c(i.e. fin structures104-1cand104-2c) are formed in the region W1-2of the first well region W1and the region W2-1of the second well region W2respectively in accordance with some embodiments. As shown inFIGS.6A and6C, in a cross-sectional view in the second region20, the semiconductor structure100cincludes both the channel structures108′-1cand108′-2c(e.g. the forksheet structures) and the channel structures108′-3and108′-4(e.g. the nanosheet structures) in accordance with some embodiments. In some embodiments, the width W108′-3of the channel structure108′-3and the width W108′-4of the channel structure108′-4are greater than the width W108′-1cof the channel structure108′-1cand the width W108′-2cof the channel structure108′-2c.

In some embodiments, the edges in the Y direction of the channel structures108′-1c,108′-2c,108′-3, and108′-4are substantially aligned with each other. In some embodiments, the edges in the X direction of the channel structures108′-1c,108′-2c,108′-3, and108′-4are substantially parallel with each other.

In some embodiments, gate structures168, including gate structures168-1,168-2, and168-3, are formed abutting the channel structures. In some embodiments, the gate structure168-2abuts (e.g. wraps around) the channel structures108′-1c,108′-2c,108′-3, and108′-4. In some embodiments, the gate structure168-3abuts (e.g. wraps around) the channel structures108′-1,108′-2,108′-1c,108′-2c,108′-3, and108′-4.

Processes and materials for forming the semiconductor structure100cmay be similar to, or the same as, those for forming the semiconductor structure100described previously and are not repeated herein. For example, the processes and materials for forming the channel structures108′-1cand108′-2c, the fin structures104-1cand104-2c, and gate structures168may be similar to, or the same as, those for forming the channel structures108′-1and108′-2, the fin structures104-1and104-2, and the gate structures168-1described previously.

FIG.7illustrates a top view of a semiconductor structure100c′ formed over the substrate102W shown inFIG.5in accordance with some embodiments. The semiconductor structure100c′ may be similar to the semiconductor structure100cdescribed previously, except the dielectric structure169shown inFIGS.3C-1,3C-2,3C-3,3C-4,3C-5, and3C-6is formed. Processes and materials for forming the semiconductor structure100c′ may be similar to, or the same as, those for forming the semiconductor structures100aand100cdescribed previously and are not repeated herein.

FIG.8illustrates a top view of a semiconductor structure100c″ formed over the substrate102W shown inFIG.5in accordance with some embodiments. The semiconductor structure100c″ may be similar to the semiconductor structure100cdescribed previously, except the channel structures108′-3band108′-4band the dummy contacts183shown inFIGS.4A to4Fare formed. Processes and materials for forming the semiconductor structure100c″ may be similar to, or the same as, those for forming the semiconductor structures100band100cdescribed previously and are not repeated herein.

FIG.9Aillustrates a top view of a semiconductor structure100dformed over the substrate102W shown inFIG.5in accordance with some embodiments.FIG.9Billustrate the cross-sectional view of the semiconductor structure100dshown along lines Y1SDd-Y1SDd′ (i.e. in the Y direction) and Y2SDd-Y2SDd′ (i.e. in the Y direction) inFIG.9Ain accordance with some embodiments.FIG.9Cillustrates the cross-sectional view of the semiconductor structure100dshown along lines Y1MGd-Y1MGd′ (i.e. in the Y direction) and Y2MGd-Y2MGd′ (i.e. in the Y direction) inFIG.9Ain accordance with some embodiments.FIG.9Dillustrate the cross-sectional view of the semiconductor structure100dshown along lines X1d—X1d′ (i.e. in the X direction) inFIG.9Ain accordance with some embodiments.FIG.9Eillustrate the cross-sectional view of the semiconductor structure100dshown along lines X2d—X2d′ (i.e. in the X direction) inFIG.9Ain accordance with some embodiments.FIG.9Fillustrate the cross-sectional view of the semiconductor structure100dshown along lines X3d—X3d′ (i.e. in the X direction) inFIG.9Ain accordance with some embodiments.

The semiconductor structure100dmay be similar to the semiconductor structure100described previously, except the channel structures have different widths in Y direction in accordance with some embodiments. More specifically, channel structures108′-1dare formed over the first well region W1and the channel structures108′-2dare formed over the second well region W2, and the channel structures108′-1dand108′-2dare attached to opposite sides of the dielectric wall structure126to form forksheets structures in accordance with some embodiments. In addition, the channel structures108′-1dand108′-2dhave different widths in Y direction, as shown inFIGS.9A and9Cin accordance with some embodiments. In some embodiments, the width W108′-2dof the channel structures108′-2dis greater than the width W108′-1dof the channel structures108′-1d. Furthermore, source/drain structures150-2dattached to the channel structures108′-2dare also wider than source/drain structures150-1dattached to the channel structures108′-1d. In some embodiments, the width W108′-1dof the channel structures108′-1dis greater than a quarter of the width W108′-2dof the channel structures108′-2d.

Similarly, channel structures108′-3dare formed over the first well region W1and channel structures108′-4dare formed over the second well region W2, and the channel structures108′-3dand108′-4dhave different widths in Y direction, as shown inFIGS.9A and9Cin accordance with some embodiments. In some embodiments, the width W108′-4dof the channel structures108′-4dis greater than the width W108′-3dof the channel structures108′-3d. In addition, source/drain structures150-4dattached to the channel structures108′-4dare also wider than source/drain structures150-3dattached to the channel structures108′-3d. Furthermore, although the channel structures108′-3dare narrower than the channel structures108′-4d, the channel structures108′-3dmay still be wider than the channel structures108′-2d, since the size of the forksheet structures may be limited so the first semiconductor material layers may be fully removed. In some embodiments, the width W108′-3dof the channel structures108′-3dis greater than the width W108′-2dof the channel structures108′-2d.

Processes and materials for forming the semiconductor structure100dmay be similar to, or the same as, those for forming the semiconductor structure100cdescribed previously and are not repeated herein. For example, processes and materials for forming the fin structures104-1d,104-2d,104-3d, and104-4d, the channel structures108′-1d,108′-2d,108′-3d, and108′-4d, and the source/drain structures150-1d,150-2d,150-3d, and150-4dare similar to, or the same as, those for forming the fin structures104-1,104-2,104-3, and104-4, the channel structures108′-1,108′-2,108′-3, and108′-4, and the source/drain structures150-1,150-2,150-3, and150-4described previously and are not repeated herein.

FIG.10illustrates a top view of a semiconductor structure100d′ formed over the substrate102W in accordance with some embodiments. The semiconductor structure100d′ may be similar to the semiconductor structure100ddescribed previously, except the dielectric structure169shown inFIGS.3C-1,3C-2,3C-3,3C-4,3C-5, and3C-6is formed. Processes and materials for forming the semiconductor structure100d′ may be similar to, or the same as, those for forming the semiconductor structures100aand100ddescribed previously and are not repeated herein.

FIG.11illustrates a top view of a semiconductor structure100d″ formed over the substrate102W in accordance with some embodiments. The semiconductor structure100d″ may be similar to the semiconductor structure100ddescribed previously, except channel structures108′-3d″ and108′-4d″, similar to the channel structures108′-3band108′-4bshown inFIGS.4A to4F, are laterally spaced apart from the channel structures108′-1dand108′-2. Processes and materials for forming the semiconductor structure100d″ may be similar to, or the same as, those for forming the semiconductor structures100band100ddescribed previously and are not repeated herein. For example, processes and materials for forming the channel structures108′-3d″ and108′-4d″ may be similar to, or the same as, those for forming the channel structures108′-3dand108′-4ddescribed previously.

FIG.12Aillustrates a top view of a semiconductor structure100eformed over the substrate102W shown inFIG.5in accordance with some embodiments.FIG.12Billustrate the cross-sectional view of the semiconductor structure100eshown along lines Y2SDe-Y2SDe′ (i.e. in the Y direction) inFIG.12Ain accordance with some embodiments.FIG.12Cillustrates the cross-sectional view of the semiconductor structure100eshown along lines Y2MGe-Y2MGe′ (i.e. in the Y direction) inFIG.12Ain accordance with some embodiments.

The semiconductor structure100emay be similar to the semiconductor structure100cdescribed previously, except the channel structures of the nanosheet structures are arranged in different ways in accordance with some embodiments.

More specifically, channel structures108′-4e1and108′-4e2are formed at opposite sides of the channel structures108′-3in the Y direction, as shown inFIG.12Ain accordance with some embodiments. In addition, the width W108′-4e1of the channel structures108′-4e1and the width W108′-4e2of the channel structures108′-4e2are smaller than half of the width WW2of the second well region W2in accordance with some embodiments. On the other hand, the width W108′-3of the channel structures108′-3is greater than half of the width WW1of the first well region W1and is smaller than the width WW1of the first well region W1in accordance with some embodiments. In some embodiments, source/drain structures150-4e-1attached to the channel structures108′-4e-1and source/drain structures150-4e-2attached to the channel structures108′-4e-2are narrower than the source/drain structures150-3, as shown inFIG.12Bin accordance with some embodiments.

The semiconductor structure100emay include a region R as shown inFIG.12A. The region R may include two regions W2-2of the second well regions W2and the first well region W1is sandwiched between the two regions W2-2in the Y direction. The width of the region R may be substantially the same as the sum of the width WW1of one first well region W1and the width WW2of one second well region W2. In some embodiments, in the first region10of the region R1, four channel structures, including channel structures108′-1e1,108′-2e1,108′-1e2, and108′-2e2, are formed. On the other hand, in the second region20of the region T1, three channel structures, including the channel structures108′-4e1,108′-3, and108′-4e2, are formed. In some embodiments, a sidewall surface of the channel structures108′-1e1is substantially aligned with a sidewall surface of the channel structures108′-4e1. In some embodiments, a sidewall surface of the channel structures108′-2e2is substantially aligned with a sidewall surface of the channel structures108′-4e2.

Processes and materials for forming the semiconductor structure100emay be similar to, or the same as, those for forming the semiconductor structures100cand/or100ddescribed previously and are not repeated herein. For examples, the processes and materials for forming the channel structures108′-1e1and108′-1e2, the channel structures108′-2e1and108′-2e2, the channel structures108′-4e1and108′-4e2, the fin structures104-1e1and104-1e2, the fin structures104-2e1and104-2e2, the fin structures104-4e1and104-4e2, and the source/drain structures105-4e1and104-4e2may be similar to, or the same as, those for forming the channel structures108′-1, the channel structures108′-2, the channel structures108′-4, the fin structures104-1, the fin structures104-2, the fin structures104-4, and the source/drain structures105-4described previously.

FIG.13illustrates a top view of a semiconductor structure100e′ formed over the substrate102W in accordance with some embodiments. The semiconductor structure100e′ may be similar to the semiconductor structure100edescribed previously, except the dielectric structure169shown inFIGS.3C-1,3C-2,3C-3,3C-4,3C-5, and3C-6is formed. Processes and materials for forming the semiconductor structure100e′ may be similar to, or the same as, those for forming the semiconductor structures100aand100edescribed previously and are not repeated herein.

FIG.14illustrates a top view of a semiconductor structure100e″ formed over the substrate102W in accordance with some embodiments. The semiconductor structure100e″ may be similar to the semiconductor structure100edescribed previously, except channel structures108′-4e1″,108′-3d, and108′-4e2″, similar to the channel structures108′-3band108′-4bshown inFIGS.4A to4F, are laterally spaced apart from the channel structures108′-1e1,108′-2e1,108′-1e2, and108′-2e2. Processes and materials for forming the semiconductor structure100e″ may be similar to, or the same as, those for forming the semiconductor structures100band100edescribed previously and are not repeated herein. For example, processes and materials for forming the channel structures108′-4e1″,108′-3″, and108′-4e2″ may be similar to, or the same as, those for forming the channel structures108′-4e1,108′-3, and108′-4e2described previously.

FIG.15Aillustrates a top view of a semiconductor structure100fformed over the substrate102W in accordance with some embodiments.FIG.15Billustrates the cross-sectional view of the semiconductor structure100fshown along lines Y2SDf-Y2SDf′ (i.e. in the Y direction) inFIG.15Ain accordance with some embodiments.FIG.15Cillustrates the cross-sectional view of the semiconductor structure100fshown along lines Y2MGf-Y2MGf′ (i.e. in the Y direction) inFIG.15Ain accordance with some embodiments.

The semiconductor structure100fmay be similar to the semiconductor structure100cdescribed previously, except the channel structures of the nanosheet structures have different widths in accordance with some embodiments. More specifically, channel structures108′-3f1and108′-3f2are formed at opposite sides of the channel structures108′-4in the Y direction, as shown inFIG.15Ain accordance with some embodiments. In addition, the width W108′-3f1of the channel structures108′-3f1, the width W108′-3f2of the channel structures108′-3f2, and the width W108′-4of the channel structures108′-4are different from each other in accordance with some embodiments. In some embodiments, the width W108′-4of the channel structures108′-4is greater than the width W108′-3f1of the channel structures108′-3f1, and the width W108′-3f1of the channel structures108′-3f1is greater than the width W108′-3f2of the channel structures108′-3f2in the Y direction. In some embodiments, the width W108′-3f2of the channel structures108′-3f2is greater than both half of the width WW1of the first well region W1and half of the width WW2of the second well region W2.

In some embodiments, the distance between the channel structures108′-3f1and the channel structures108′-4is smaller than the distance between the channel structures108′-3f2and the channel structures108′-4. In some embodiments, the source/drain structures150-4attached to the channel structures108′-4is wider than source/drain structures150-3f1attached to the channel structures108′-3f1, and the source/drain structures150-3f1attached to the channel structures108′-3f1is wider than source/drain structures150-3f2attached to the channel structures108′-3f2.

Processes and materials for forming the semiconductor structure100fmay be similar to, or the same as, those for forming the semiconductor structure100cdescribed previously and are not repeated herein. For example, processes and materials for forming the channel structures108′-3f1and108′-3f2, fin structures104-3f1and104-3f2, the source/drain structures105-3f1and105-3f2may be similar to, or the same as, those for forming the channel structures108′-3, the fin structures104-3, the source/drain structures105-3described previously.

FIG.16illustrates a top view of a semiconductor structure100f′ formed over the substrate102W in accordance with some embodiments. The semiconductor structure100f′ may be similar to the semiconductor structure100fdescribed previously, except the dielectric structure169shown inFIGS.3C-1,3C-2,3C-3,3C-4,3C-5, and3C-6is formed. Processes and materials for forming the semiconductor structure100f′ may be similar to, or the same as, those for forming the semiconductor structures100aand100fdescribed previously and are not repeated herein.

FIG.17illustrates a top view of a semiconductor structure100f′ formed over the substrate102W in accordance with some embodiments. The semiconductor structure100f′ may be similar to the semiconductor structure100fdescribed previously, except channel structures108′-3f1″,108′-4″, and108′-3f2″, similar to the channel structures108′-3band108′-4bshown inFIGS.4A to4F, are laterally spaced apart from the channel structures108′-1and108′-2. Processes and materials for forming the semiconductor structure100f′ may be similar to, or the same as, those for forming the semiconductor structures100band100fdescribed previously and are not repeated herein. For example, processes and materials for forming the channel structures108′-3f1″,108′-4″, and108′-3f2″ may be similar to, or the same as, those for forming the channel structures108′-3f1,108′-4, and108′-3f2described previously.

As described above, a semiconductor structure may include various transistors with different types of the channel structures. More specifically, the semiconductor structure may include both forksheet structures (e.g. channel structures108′-1and108′-2) and nanosheet structures (e.g. channel structures108′-3and108′-4).

In some embodiments, dielectric wall structures (e.g. the dielectric wall structures126) may be formed between two active devices (e.g. the transistors T1, T2, T5, and T6) to form forksheet structures, so that the device area may be reduced. However, during the formation of the forksheet structures, the removal of the first semiconductor material layers (e.g. the first semiconductor material layers106) may become more challenging since one side of the fin structure is attached to the dielectric wall structures (e.g. the processes shown inFIGS.2K-1to2K-4). Therefore, the width of the channel structures may be limited.

On the other hand, nanosheet structures are also formed in the semiconductor structure. Although the distance between the nanosheet structure may need to be greater than the forksheet structures due to device isolation, the channel structures (e.g. the channel structures108′-3and108′-4) of the nanosheet structures may have a greater widths. Therefore, the performance of the device (e.g. the transistors T3and T4) may be improved.

Since the semiconductor structures (e.g. the semiconductor structures100,100ato100f,100c′ to100f′,100c″ to100f″) described above include both the forksheet structures and the nanosheet structures, the device size and the power consumption may be reduced due to the formation of the forksheet structures and the performance may be improved by having nanosheet structures with greater widths.

In addition, it should be noted that same elements inFIGS.1A to17may be designated by the same numerals and may include materials that are the same or similar and may be formed by processes that are the same or similar; therefore such redundant details are omitted in the interests of brevity. In addition, althoughFIGS.1A to17are described in relation to the method, it will be appreciated that the structures disclosed inFIGS.1A to17are not limited to the method but may stand alone as structures independent of the method. Similarly, the methods shown inFIGS.1A to17are not limited to the disclosed structures but may stand alone independent of the structures. Furthermore, the channel structures (e.g. the nanostructures) described above may include nanowires, nanosheets, or other applicable nanostructures in accordance with some embodiments.

Also, while the disclosed methods are illustrated and described below as a series of acts or events, it should be appreciated that the illustrated ordering of such acts or events may be altered in some other embodiments. For example, some acts may occur in a different order and/or concurrently with other acts or events apart from those illustrated and/or described above. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description above. Furthermore, one or more of the acts depicted above may be carried out as one or more separate acts and/or phases.

Furthermore, the terms “approximately,” “substantially,” “substantial” and “about” used above account for small variations and may be varied in different technologies and be within the deviation range understood by the skilled in the art. For example, when used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs in a close approximation.

Embodiments for forming semiconductor structures may be provided. The semiconductor structures may include first channel structures, second channel structures, and a dielectric wall structure attached to the first channel structures. The first channel structure may be narrower than the second channel structures and may have a smaller device size. On the other hand, the second channel structures may have a greater device size but an improved performance.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first well region formed in a substrate and longitudinally oriented along a first direction and a second well region formed in the substrate and adjoining the first well region in a second direction being substantially orthogonal to the first direction. The semiconductor structure also includes a dielectric wall structure formed over the boundary between the first well region and the second well region and longitudinally oriented along the first direction and first channel structures vertically suspended over a first region of the first well region and laterally attached to a first sidewall surface of the dielectric wall structure. The semiconductor structure also includes a first gate structure wrapping around the first channel structures over the first region of the first well region and longitudinally oriented along the second direction. In addition, the first gate structure partially covers the first sidewall surface of the dielectric wall structure. The semiconductor structure also includes second channel structures vertically suspended over a second region of the first well region and a second gate structure wrapping around the second channel structures over the second region of the first well region and longitudinally oriented along the second direction. In addition, a dimension of the first channel structures in the second direction is smaller than a dimension of the second channel structures in the second direction.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes first well regions and second well regions formed over a substrate. In addition, the first well regions and the second well regions are alternatively arranged in a Y direction. The semiconductor structure also includes a first dielectric wall structure longitudinally oriented along an X direction and partially overlapping the first well region and the second well region. The semiconductor structure also includes first channel structures, second channel structures, third channel structures, and fourth channel structures sequentially arranged in the Y direction. In addition, the first channel structures and the second channel structures are attached to opposite sides of the first dielectric wall structure. The semiconductor structure also includes a first gate structure abutting the first channel structures, the second channel structures, the third channel structures, the fourth channel structures, and the first dielectric wall structure. In addition, the first channel structures and the third channel structures are formed over the first well regions, the second channel structures and the fourth channel structures are formed over the second well regions, and the third channel structures are wider than the second channel structures in a cross-sectional view along the Y direction.

In some embodiments, a method for manufacturing a semiconductor structure is provided. The method for manufacturing the semiconductor structure includes forming a first well region and a second well region in a substrate and stacking first semiconductor material layers and second semiconductor material layers to form a semiconductor stack over the first well region and the second well region. The method for manufacturing the semiconductor structure also includes patterning the semiconductor stack to form a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure in a first region of the first well region, a first region of the second well region, a second region of the first well region, and a second region of the second well region respectively. In addition, the first fin structure, the second fin structure, the third fin structure, and the fourth fin structure are substantially parallel to each other and are longitudinally oriented along a first direction, and the third fin structure is wider than the first fin structure in a second direction. The second direction is different from the first direction. The method for manufacturing the semiconductor structure also includes forming a dielectric wall structure sandwiched between the first fin structure and the second fin structure and over the boundary between the first well region and the second well region and removing the first semiconductor material layers of the first fin structure and the second fin structure to form first channel structures and second channel structures exposed by a first gate trench. In addition, sidewalls of the dielectric wall structure partially exposed by the first gate trench. The method for manufacturing the semiconductor structure also includes removing the first semiconductor material layers of the third fin structure and the fourth fin structure to form third channel structures and fourth channel structures exposed by a second gate trench and forming a first gate structure in the first gate trench and a second gate structure in a second gate trench. In addition, a distance between the third channel structures and the fourth channel structures is greater than the width of the dielectric wall structure in the second direction.