Embedded universal serial bus 2 repeater

Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.

SUMMARY

Other aspects of the disclosure provide for a circuit. In at least some examples, the circuit includes a first amplifier, a second amplifier, a third amplifier, a first resistor, a second resistor, a first comparator, a bus holder circuit, and a logic circuit. The first amplifier has a first input coupled to a first node, a second input coupled to a second node, a first output, and a second output. The second amplifier has a first input coupled to the first output of the first amplifier, a second input coupled to the second output of the first amplifier, a first output coupled to a third node, and a second output coupled to a fourth node. The third amplifier has a first input coupled to the third node, a second input coupled to the fourth node, a first output coupled to a fifth node, a second output coupled to a sixth node, and a control input. The first resistor is coupled between the first node and a seventh node. The second resistor is coupled between the seventh node and the second node. The first comparator has a first input coupled to the seventh node, a second input coupled to an eighth node, and an output. The bus holder circuit has an input, a first output coupled to the third node, and a second output coupled to the fourth node. The logic circuit has a first input coupled to the output of the first comparator, a first output coupled to the input of the bus holder circuit, and a second output coupled to the control input of the third amplifier.

Other aspects of the disclosure provide for a system. In at least some examples, the system includes a processing element and an embedded Universal Serial Bus (USB) (eUSB2) repeater. The processing element is configured to communicate according to an eUSB2 protocol. The eUSB2 repeater is coupled to the processing element, and includes a first amplifier, a second amplifier, a third amplifier, a first resistor, a second resistor, a first comparator, a bus holder circuit, and a logic circuit. The first amplifier has a first input coupled to a first node, a second input coupled to a second node, a first output, and a second output. The second amplifier has a first input coupled to the first output of the first amplifier, a second input coupled to the second output of the first amplifier, a first output coupled to a third node, and a second output coupled to a fourth node. The third amplifier has a first input coupled to the third node, a second input coupled to the fourth node, a first output coupled to a fifth node, a second output coupled to a sixth node, and a control input. The first resistor is coupled between the first node and a seventh node. The second resistor is coupled between the seventh node and the second node. The first comparator has a first input coupled to the seventh node, a second input coupled to an eighth node, and an output. The bus holder circuit has an input, a first output coupled to the third node, and a second output coupled to the fourth node. The logic circuit has a first input coupled to the output of the first comparator, a first output coupled to the input of the bus holder circuit, and a second output coupled to the control input of the third amplifier.

Other aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.

DETAILED DESCRIPTION

Universal Serial Bus (USB) is a standard establishing specifications for interconnect cabling, connectors, and communication protocols. As referred to herein, USB refers to any version of the USB specification, including any amendments or supplements, certified by the USB Implementers Forum (USB IF) or any suitable body who replaces and/or aids the USB IF in its role overseeing the USB specification, whether now existing or later developed. In at least one example, USB, as referred to herein, encompasses any one or more of the USB 1.0 specification, USB 2.0 specification, USB 3.0 specification, USB 4.0 specification, or any derivatives thereof, such as amended or “.x” variations of the above specifications. Also, as referred to herein, legacy USB refers to USB 2.x and/or USB 1.x. Embedded USB (eUSB), in at least some examples, refers to eUSB2. While reference is made herein to eUSB2, in various examples the teachings of the present disclosure are further applicable to other versions of eUSB that are extensions of, alternatives to, derivatives of, or otherwise share at least some commonalities with, or similarities to, eUSB2. Accordingly, while eUSB2 is referred to herein in an exemplary manner, the present disclosure is, in some examples, not limited to implementation in an eUSB2 environment, in an eUSB environment, or in a USB environment.

At its inception, USB was primarily intended for implementation in specifying standards for connection and communication between personal computers and peripheral devices. However, as adoption of the USB standard has expanded and implementation in computing devices of support for the USB standard has gained in popularity, efforts have been made to extend and expand the applicability of USB. For example, while initially establishing specifications for communications between personal computers and peripheral devices, USB has expanded to communication between peripheral devices, between personal computers, and other use cases. As a result of such widespread implementation and use of USB, efforts are being further made to utilize USB as a communication protocol among individual subsystems or circuits (e.g., such as a system-on-a-chip (SoC)). Such implementations are sometimes referred to as eUSB2. New challenges arise in implementing eUSB2. For example, at a circuit level, computing devices often operate at voltage levels that vary from those of conventional USB, creating an impediment between direct communication between eUSB2 and legacy USB systems. To mitigate this impediment, an eUSB2 repeater operates as a bridge or non-linear redriver between eUSB2 and legacy USB systems, or vice versa, to translate between legacy USB signaling voltage levels that are customarily about 3.3 volts (V) and eUSB2 signaling voltages levels that are circuit-level (e.g., silicon appropriate voltages) such as about 1.0 V, 1.2 V, 1.4 V, or any other suitable value less than 3.3 V.

In some examples, a last bit of data of a USB packet (e.g., including control information, data to be transferred, and error detection and/or correction information), such as a last bit of an end of packet (EOP) indicator of the USB packet, becomes stretched, creating additional data bits following the end of the EOP indicator. The stretching is caused, in some examples, by hub switching skews in the USB communication. Following the end of the EOP indicator, eUSB2 input lines of the eUSB2 repeater go idle. If a transmitter of the eUSB2 repeater is not rapidly turned off following a transition of the end of the EOP indicator, the idle signal received on the eUSB2 differential input signal lines is passed through to USB differential output signal lines of the eUSB2 repeater and results in noise being sent to a device coupled to the USB differential output signal lines of the eUSB2 repeater, which in at least some implementations is undesirable and/or unacceptable. However, USB specification also prohibits truncating the EOP indicator, thereby limiting how quickly the transmitter of the eUSB2 repeater is turned off. This noise or bits following the transition of the end of the EOP indicator is, in some examples, referred to as dribble bits.

In some eUSB2 repeater implementations, a clock data recovery (CDR) circuit or a phase locked loop (PLL) determines clock timing information of a signal received by the eUSB2 repeater and, based on that clock timing information, the eUSB2 repeater counts a number of bits received and/or transmitted. For example, by using the CDR and/or PLL information, the eUSB2 repeater turns off the transmitter of the eUSB2 repeater once a particular number of bits of the EOP indicator have been received and/or transmitted, turning off the transmitter of the eUSB2 repeater prior to transmitting noise resulting from the idle eUSB2 input lines. However, both a CDR circuit and a PLL are comparatively large components of an eUSB2 repeater in terms of footprint (e.g., physical surface area of a component die) with respect to a remainder of the eUSB2 repeater, increasing both cost to manufacture the eUSB2 repeater and power consumed by the eUSB2 repeater. In at least some aspects, goals of implementation of eUSB2 include providing communication according to the USB specifications in smaller, lower-power environments than legacy USB, which runs contrary to the size and power requirements of both the CDR circuit and the PLL. Accordingly, in at least some eUSB2 repeater implementations it is desirable to perform EOP detection, with support for dribble bits, without using a CDR circuit or a PLL in either ingress or egress directions.

At least some aspects of the present disclosure provide for a circuit. The circuit is, in some examples, suitable for use in interfacing between eUSB2 and USB interfaces. Particularly, in at least some examples the circuit is an eUSB2 to USB repeater. In other examples, the circuit is a USB to eUSB2 repeater. For example, the circuit provides level-shifting from eUSB2 voltage levels to USB voltage levels and/or from USB voltage levels to eUSB2 voltage levels. As such, in at least some examples the circuit is viewed as a buffer and/or a level-shifter. In some examples, the circuit further provides support for one or more elements of USB communication, such as dribble bits and EOP information of varying widths (e.g., an about 8-bit EOP indicator, such as in low-speed communication, and/or an about 40-bit EOP indicator, such as in high-speed communication). For example, at an end of the EOP indicator, eUSB2 differential input signal lines of the circuit go idle (e.g., a differential voltage between the eUSB2 differential input signal lines falls below a threshold). When the end of the EOP indicator is not accurately identified by the circuit, noise resulting from the idle eUSB2 differential input signal lines is output by the circuit on the USB differential output signal lines, which in at least some implementations is undesirable and/or unacceptable for a particular application environment of the circuit. In at least some examples, the circuit includes one or more components configured to rapidly detect eUSB2 differential input signal lines of the circuit becoming idle. The detection, in at least some examples, is made based on a differential voltage of the eUSB2 differential input signal lines of the circuit falling below a threshold. In at least some examples, based on the detection, a logic component of the circuit controls one or more other components of the circuit to maintain a value of the last bit of the EOP indicator for up to four additional bits, corresponding to the four dribble bits permitted according to USB specification. In at least some examples, the present disclosure is extensible to accommodate a larger or smaller number of dribble bits permitted according to USB specification if the allowance of dribble bits provided for in the USB specification changes.

Maintaining the last bit of data of the EOP indicator causes a control signal for turning off transmission by the circuit to arrive prior to an end of transmission of the actual data of the last bit of the EOP indicator, even if transmission of an appropriate number of bits of the EOP indicator has already occurred. For example, if the EOP indicator is a series of logical high value bits, the circuit maintains a logical high value for up to four additional bits after the end of the EOP indicator and the eUSB2 differential input signal lines of the circuit going idle to prevent noise from being sent by the circuit on the USB differential output signal lines. Similarly, if the EOP indicator is a series of logical low value bits, the circuit maintains a logical low value for up to four additional bits after the end of the EOP indicator and the eUSB2 differential input signal lines of the circuit going idle to prevent noise from being sent by the circuit on the USB differential output signal lines. In at least some examples, a comparator is implemented in the circuit to determine when the eUSB2 differential input signal lines of the circuit go idle, providing a control signal to a logic component of the circuit for causing the last bit of the EOP indicator to be held for up to four additional bits following the end of the EOP indicator, preventing noise from being transmitted by the circuit following the transition at the end of the EOP indicator at a lower space and power cost than if the circuit implemented a CDR circuit and/or a PLL.

Turning now toFIG. 1, a block diagram of an illustrative system100is shown. In at least some examples, the system100is illustrative of a computing device, or elements of a computing device. For example, the system100includes a processor105, an eUSB2 device110, an eUSB2 repeater115, and a USB device120. The USB device120is a legacy USB device, as described elsewhere herein. In some examples, one or both of the eUSB2 device110or the USB device120is implemented external to the system100and configured to couple to the system100through an appropriate interface (e.g., such as a port and receptacle suitable for performing communication according to eUSB2 or USB protocol, respectively). The processor105is, in some examples, a SoC. The eUSB2 device110is any device operating in both ingress and egress communication directions according to signal voltage level specifications for eUSB2. The USB device120is any device operating in both ingress and egress communication directions according to signal voltage level specifications for legacy USB. For example, in at least some implementations the USB device120is a peripheral such as a user input device, (e.g., a sensor, a scanner, an imaging device, a microphone, etc.), an output device (e.g., a printer, speakers, etc.), a storage device, or any other peripheral, component, or device suitable for communicating with the processor105.

The eUSB2 repeater115communicatively couples the processor105to the USB device120and vice versa, converting signals appropriate for the processor105to signals appropriate for the USB device120and vice versa. For example, in some implementations signaling in the processor105is performed in a range of about 0.8 V to about 1.4 V. Similarly, in some implementations signaling in the USB device120is performed at about 3.3 V or about 5 V. In at least some examples, the eUSB2 repeater115operates as a bit-level repeater, receiving signals from one of the processor105or USB device120and converting the signals for use by the other of the processor105or USB device120(e.g., by shifting a voltage level of the signals upward or downward based on a direction of the communications). In some examples, a data signal in the system100ends with an EOP indicator. The EOP indicator is, in some examples, about 8 bits in length, in other examples is about 40 bits in length, and in yet other examples has any length defined according to USB or eUSB2 specifications. The EOP indicator is a static value. For example, a consistent series of logical high value bits or a consistent series of logical low value bits for a specified duration of the EOP indicator.

In at least some examples, after the eUSB2 repeater115receives the EOP indicator, eUSB2 differential input signal lines of the eUSB2 repeater115go to an idle state in which a differential voltage between the eUSB2 differential input signal lines is less than a predefined threshold, but is also, in at least some examples, non-zero. If the eUSB2 repeater115continues to amplify and transmit the signal received on the eUSB2 differential input signal lines out via the USB differential output signal lines, noise will be present on the USB differential output signal lines which is undesirable and/or unacceptable (e.g., such that the noise can degrade performance of a device receiving the noise). To prevent transmission of the noise, a transmitter125of the eUSB2 repeater115is turned off prior to a rising or falling transition at an end of the EOP indicator. USB specification, in at least some versions, prohibits truncation of the EOP indicator (e.g., ceasing transmission prior to transmitting a full bit width of the EOP indicator). Accordingly, in at least some examples the eUSB2 repeater115includes a comparator130that compares values present on each of the eUSB2 differential input signal lines to each other to determine when the rising or falling transition at the end of the EOP indicator occurs and, based on the result of that comparison, extends a last bit of the EOP indicator for up to four additional bits. During the period of time in which the EOP indicator is extended, the eUSB2 repeater115turns off the transmitter125to prevent noise from being transmitted out via the USB differential output signal lines following transmission of the EOP indicator, while also assuring an entire bit width of the EOP indicator is transmitted without truncation in compliance with USB specifications prior to the turning off of the transmitter125. In at least some examples, these bits added to the end of the EOP indicator repeating the value of the last bit of the EOP indicator are referred to as EOP dribble or EOP dribble bits.

Turning now toFIG. 2, a schematic diagram of an illustrative circuit200is shown. In at least some examples, the circuit200is suitable for implementation as the eUSB2 repeater115of the system100ofFIG. 1. The circuit200, in some examples, is representative of an eUSB2 repeater having functionality to receive data from an eUSB2 system and provide data to a legacy USB system. The circuit200, in at least some examples, includes an amplifier205, an amplifier210, an amplifier215, a comparator220, a comparator225, a comparator230, a squelch detector235, a logic circuit240, a bus holder245, a resistor250, a resistor255, a resistor260, a resistor265, and a capacitor270. In at least some examples, the amplifier205is considered a receiver (RX) of the circuit200, the amplifier210is considered a pre-amplifier (Pre-Amp) of the circuit200, and the amplifier215is considered a transmitter (TX) of the circuit200, for example, such that the amplifier215is representative of the transmitter125of the eUSB2 repeater115. In at least some examples, the amplifier210is omitted from the circuit200. In at least some examples, the comparator230is representative of the comparator130of the eUSB2 repeater115. In at least some examples, the circuit200expressly does not include a CDR circuit or a PLL.

In an example architecture of the circuit200, the amplifier205has a positive differential input coupled to a node272and a negative differential input coupled to a node274. The amplifier210has a positive differential input coupled to a positive differential output of the amplifier205and a negative differential input coupled to negative differential output of the amplifier205. The amplifier210also has a positive differential output coupled to a node276and a negative differential output coupled to a node278. The amplifier215has a positive differential input coupled to the node276, a negative differential input coupled to the node278, a positive differential output coupled to a node280, and a negative differential output coupled to a node282. The comparator220has a first input coupled to the node272and a second input coupled to a node284. The comparator225has a first input coupled to the node274and a second input coupled to a node286. The comparator230has a first input coupled to a node286and a second input coupled to a node288. The squelch detector235has a first input coupled to the node272and a second input coupled to the node274. An output of the comparator220, an output of the comparator225, an output of the comparator230, and an output of the squelch detector235are each coupled to respective inputs of the logic circuit240. A first output of the logic circuit240is coupled to an offset control terminal of the amplifier205, a second output of the logic circuit240is coupled to the bus holder245, and a third output of the logic circuit240is coupled to a control terminal of the amplifier215. The bus holder has a first output coupled to the node276and a second output coupled to the node278. The resistor250is coupled between the node272and the node286and the resistor255is coupled between the node286and the node274. The resistor260is coupled between the node272and the node288and the resistor265is coupled between the node288and the node274. The capacitor270is coupled between the node288and a ground terminal290.

In an example of operation of the circuit200, a differential input signal is received at the node272and the node274. For example, a positive component of the differential input signal (eD+) is received at the node272and a negative component of the differential input signal (eD−) is received at the node274. In this regard, in at least some examples the node272and the node274collectively comprise eUSB2 differential input ports and/or eUSB2 differential input signal lines of the circuit200. The amplifier205amplifies the differential input signal and the amplifier210amplifies a result of that amplification to provide signals at the node276and the node278. In some examples, the amplifier205introduces an offset to the differential input signal based on control performed by the logic circuit240and according to a control signal received at the offset control terminal of the amplifier205. For example, the logic circuit240controls the amplifier205to introduce an offset to the differential input signal such that the output of amplifier205will be a static logic high value or static logic low value based on a polarity of the offset. This, in some examples, at least partially facilitates the EOP extension taught herein and/or prevents the amplification of random noise in the output of the amplifier205. The amplifier215amplifies the signals present at the node276and the node278to provide a differential output signal at the node280and the node282, respectively. A positive component of the differential output signal (D+) is output at the node280and a negative component of the differential output signal (D−) is output at the node282. In this regard, in at least some examples the node280and the node282collectively comprise USB differential output ports and/or USB differential output signal lines of the circuit200. In at least some examples, the amplifier215is powered by a different power source and/or receives a different supply voltage than the amplifier205, for example, such that the circuit200uses a dual-supply to provide level-shifting functionality between the eUSB2 differential input ports and the USB differential output ports. Additionally, in at least some examples the amplifier215is subject to control of the logic circuit240. For example, the logic circuit240controls when the amplifier215is active, amplifying signals present at the node276and the node278to provide the differential output signal at the node280and the node282, respectively, or when the amplifier215is turned off and is not amplifying signals present at the node276and the node278to provide the differential output signal at the node280and the node282, respectively.

The comparator220is configured to compare eD+ to a first reference voltage (Vref1) received at the node284and output a result of the comparison to the logic circuit240. The comparator225is configured to compare eD− to a second reference voltage (Vref2) received at the node286and output a result of the comparison to the logic circuit240. In at least some examples, Vref1and Vref2are the same signal (e.g., such that the node284and the node286are coupled to a same, common point. In other examples, Vref1and Vref2are different signals but have substantially a same value. In yet other examples, Vref1and Vref2have different values. In at least some examples, one or both of the comparator220and/or the comparator225are replaced by a respective loss of signal detector (not shown) configured to determine whether loss of signal has occurred with respect to eD+ and/or eD−.

Each of the resistor250, resistor255, resistor260, and resistor265have approximately a same resistance value such that they are balanced and a voltage present at the node286is approximately equal to common mode voltage (Vcm) of eD+ and eD−. Additionally, a center tap of eUSB2 differential signaling lines is floating, meaning the enter tap is not referenced to a ground potential. Accordingly, a voltage present at the node288is approximately equal to Vcm_ref based on Vcm and a voltage (Vc) of the capacitor270. In at least some examples, the capacitor270has a capacitance of about 50 picofarads (pF) to create the floating center tap between eD+ and eD−. The comparator230is configured to compare Vcm to Vcm_ref to determine an edge transition of eD+. When the eUSB2 differential input signal lines are active, Vcm_ref charges to a value approximately equal to Vcm. When Vcm is greater than or approximately equal to Vcm_ref, the comparator230outputs a signal having a logical low value. When Vcm falls below Vcm_Vref, the comparator230outputs a signal having a logical high value. When the output of the comparator230transitions from a logical low level to a logical high level, the comparator230has detected an end of data receipt (e.g., such as an end of the EOP indicator and/or an eUSB2 input signal failure) and therefore the eUSB2 differential input signal lines going idle. The squelch detector235, in at least some examples, outputs a logic high value signal when a differential between eD+ and eD− exceeds a threshold and outputs a logical low value signal when the differential between eD+ and eD− is less than the threshold. In at least some examples, the squelch detector235includes one or more noise and/or other filtering components that cause the squelch detector235to react slowly to changes in eD+ and eD−. For example, in at least some implementations a response time of the squelch detector235is insufficient (e.g., too slow) for the output of the squelch detector235to be used to identify an end of the EOP indicator and/or as a basis for control of the amplifier215, as discussed herein, despite the output of the squelch detector235subsequently indicating the eUSB2 differential input signal lines going idle at a time subsequent to the end of the EOP indicator.

Based on the output of the comparator230, the logic circuit240controls the bus holder245and/or the amplifier215to maintain a value of a last bit of the EOP indicator at the node276and the node278until after the amplifier215is turned off. In at least some examples, such control by the logic circuit240prevents noise resulting from idle eUSB2 differential input signal lines from being amplified and output by the amplifier215to the node280and/or the node282. For example, when the comparator230indicates to the logic circuit240that data receipt via the eUSB2 differential input signal lines has ended, the logic circuit240determines, via the comparator220and the comparator225, a state of each of the node272and the node274. Based on the state of each of the node272and the node274, the logic circuit240controls the bus holder245to maintain values of the node276and the node278, respectively. For example, when the comparator220indicates that the node272is at a differential high level (e.g., Vcm plus one-half of a voltage swing of the differential input signal), the comparator225indicates that the node274is at a differential low level (e.g., Vcm minus one-half of the voltage swing of the differential input signal), and the comparator230outputs a logical high signal, the logic circuit240controls the bus holder245to hold the node276at the differential high level and hold the node278at the differential low level. Similarly, when the comparator220indicates that the node272is at the differential low level, the comparator225indicates that the node274is at the differential high, and the comparator230outputs a logical high signal, the logic circuit240controls the bus holder245to hold the node276at the differential low level and hold the node278at the differential high level. In at least some examples, the logic circuit240controls the bus holder245to hold the node276and the node278at the prescribed levels until the logic circuit240has controlled the amplifier215to turn off, after which the logic circuit240controls the bus holder245to release the node276and the node278to return to values determined according to a value of a signal received at the node272and the node274, respectively.

In at least some examples, the bus holder245includes any one or more components suitable for, and configured to, selectively hold values of the node276and/or the node278at desired levels when controlled by the logic circuit240and release the nodes276and/or278when controlled by the logic circuit240. In some example implementations, the bus holder245holds the node276and/or the node278at the desired levels when controlled by the logic circuit240by shorting a source voltage or a ground terminal to the node276and/or the node278, and accordingly to respective inputs of the amplifier215. In some examples, the bus holder245inverts a polarity of a signal present at the node276and/or the node278and in other examples the bus holder245maintains or holds a polarity of the signal present at the node276and/or the node278.

Turning now toFIG. 3, a schematic diagram of an illustrative circuit300is shown. In at least some examples, the circuit300is suitable for implementation as the eUSB2 repeater115of the system100ofFIG. 1. The circuit300, in at least some examples, includes the amplifier205, the amplifier210, the amplifier215, the comparator220, the comparator225, a comparator305, the squelch detector235, the logic circuit240, the bus holder245, the resistor250, and the resistor255. The circuit300, in some examples, is representative of an eUSB2 repeater having functionality to receive data from a legacy USB system and provide data to an eUSB2 system. In at least some examples, the comparator305is representative of the comparator130of the eUSB2 repeater115. In at least some examples, the circuit300expressly does not include a CDR circuit or a PLL.

In an example architecture of the circuit300, the components are coupled as described above with respect to the circuit200ofFIG. 2and the description of which is not repeated herein. In at least one example, the comparator305has a first input coupled to the node286, a second input coupled to the ground terminal290, and an output coupled to the logic circuit240.

In at least one example of operation, components of the circuit300having like reference numerals to those of the circuit200operate in substantially the same manner as discussed above with respect to the circuit200. Additionally, in understanding the operation of the circuit300, where reference was made to eD+ and eD− in describing the circuit200, reference is instead made to D+ and D− in describing the circuit300. Where reference was made to D+ and D− in describing the circuit200, reference is instead made to eD+ and eD− in describing the circuit300. For example, whereas the circuit200received eD+ and eD− at the node272and the node274, respectively, and output D+ and D− at the node280and the node282, respectively, the circuit300receives D+ at the node272, receives D− at the node274, outputs eD+ at the node280, and outputs eD− at the node282.

The comparator305is configured to compare Vcm to a signal present at the ground terminal (e.g., such as a ground potential) and output a logical high signal when Vcm is greater the signal present at the ground terminal to determine an edge transition of D+. As discussed above with respect to the circuit200, the center tap of eUSB2 differential signaling lines is floating such that the second input of the comparator230is coupled to the node288instead of the ground terminal. In contrast, a center tap of legacy USB differential signaling lines is grounded (e.g., coupled to the ground terminal290). Accordingly, the second input of the comparator305is also coupled to the ground terminal290. When the output of the comparator305transitions from a logical low level to a logical high level, the comparator305has detected an end of data receipt (e.g., such as an end of the EOP indicator and/or an USB input signal failure) and therefore the USB differential input signal lines going idle. The logic circuit240controls the amplifier215and the bus holder245based on the output of the comparator305in substantially the same manner as described above with respect to the output of the comparator230.

Turning now toFIG. 4, a diagram400of illustrative waveforms is shown. The diagram400illustrates a waveform405, a waveform410, a waveform415, a waveform420, a waveform425, a waveform430, a waveform435, and a waveform440. In some examples, such as when the diagram400is representative of waveforms present in the circuit200, the waveform405corresponds to eD+, the waveform410corresponds to eD−, the waveform415corresponds to D+, the waveform420corresponds to D−, the waveform425corresponds to Vcm_Vref, the waveform430corresponds to Vcm, the waveform435corresponds to the output of the comparator230, and the waveform440corresponds to the output of the squelch detector235. In other examples, such as when the diagram400is representative of waveforms present in the circuit300, the waveform405corresponds to D+, the waveform410corresponds to D−, the waveform415corresponds to eD+, the waveform420corresponds to eD−, the waveform425is omitted (e.g., such that Vcm_ref is not present in the circuit300), the waveform430corresponds to Vcm, the waveform435corresponds to the output of the comparator305, and the waveform440corresponds to the output of the squelch detector235.

As illustrated inFIG. 4and described throughout the present disclosure, when a falling edge occurs in the waveform405at time t1such that a differential voltage between the waveform405and the waveform410is less than a threshold amount, an end of receipt of differential data is determined and the waveform430begins decreasing in value. When the waveform430decreases in value, a rising edge occurs in the waveform435. Based on the rising edge occurring in the waveform435, the waveform415is controlled to maintain a value present at the time t1until a time t2, at which transmission is turned off and the waveform415and the waveform420are pulled to a ground potential. Additionally, as shown by the waveform435and the waveform440, the falling edge of the waveform440trails time t1, occuringly slightly before time t2, and is therefore insufficient as detection result for use in controlling the extension of the value of the waveform415at the time t1until the time t2.

Turning now toFIG. 5, a flowchart of an illustrative method500is shown. In at least some examples, the method500corresponds to actions performed by one or more components of the system100, circuit200and/or the circuit300. The method500is, in some examples, a method for controlling a transmitter of a circuit, such as a transmitter of an eUSB2 repeater. Implementation of the method500by a circuit, in at least some examples, is advantageous in preventing transmission of noise by the circuit when differential input lines of the circuit go idle (e.g., have a floating and, at least sometimes, non-zero value) without the use of a CDR circuit or PLL.

At operation505, data is received via a differential input signal. In some examples, such as when the differential signal is received according to eUSB2 signaling protocols, a center tap of the differential input signal is floating. In other examples, such as when the differential signal is received according to legacy USB protocols, the center tap of the differential input signal is grounded. When data is being received via the differential input signal (e.g., when a magnitude of the differential input signal is much higher than 0), differential signaling lines carrying the differential input signal are considered to be active. Conversely, when data is not being received (e.g., when the magnitude of the differential input signal is about 0, or both positive and negative components of the differential input signal have approximately the same value), the differential signaling lines carrying the differential input signal are considered to be inactive or idle. Furthermore, when both positive and negative components of the differential input signal are pulled low to a ground potential, the differential signaling lines carrying the differential input signal are considered to be in a high-speed idle state.

At operation510, the data ceases to be received via the differential input signal. When data is not received via the differential signal, the differential signaling lines are considered to be idle, where particular values of the differential input signal are undefined. In at least some examples, the differential signaling lines being idle is defined as a differential between positive and negative components of the differential input signal being less than a predefined threshold.

At operation515, a falling edge in the data is detected. The falling edge, in some examples, occurs at an end to receipt of data via the differential input signal and/or the differential signaling lines transitioning to an idle state. In such examples, the falling edge causes a differential voltage between a positive component of the differential input signal and a negative component of the differential input signal to be less than a threshold amount, indicating the end to receipt of data via the differential input signal and/or the differential signaling lines transitioning to an idle state. The falling edge is, in some examples, present in a positive component of the differential input signal. In other examples, the falling edge is present in a negative component of the differential input signal. When a falling edge occurs in one, or both, of the positive component of the differential input signal and/or the negative component of the differential input signal, but the differential voltage between the positive component of the differential input signal and the negative component of the differential input signal is not less than the threshold amount, the differential signaling lines are not considered to be idle. In at least some examples, the falling edge is detected by comparing a common mode voltage of the differential input signal to a reference voltage. In some examples, such as when the data is received from an eUSB2 system, the reference voltage is Vcm_ref. In other examples, such as when the data is received from a legacy USB system, the reference voltage is a ground potential. The comparison is performed, in at least some examples, by a comparator.

At operation520, an output of the circuit is held at a final logical value of the data. The final logical value of the data is, for example, the logical value represented by the data immediately prior to the falling edge in the data. The final logical value of the data is determined according to any suitable means, the scope of which is not limited by the method500. The output of the circuit is held at the final logical value for a predefined period of time. In various examples, the predefined period of time ranges from 0 bits to 4 bits. For example, when the final value of the data was representative of a logical 1 and the falling edge in the data is detected, customarily an output of the transmitter would also include a falling edge reflective of, and corresponding to, the falling edge in the data, such that a logical 1 is no longer output by the transmitter. Conversely, at operation520the transmitter continues to output the logical 1 to hold the output of the circuit for the predefined period of time. Similarly, when the final value of the data was representative of a logical 0 and the falling edge in the data is detected, customarily an output of the transmitter would also include a falling edge reflective of, and corresponding to, the falling edge in the data, such that a logical 0 is no longer output by the transmitter. Conversely, at operation520the transmitter continues to output the logical 0 to hold the output of the circuit for the predefined period of time.

The output of the circuit is held at the final logical value, in at least some examples, by controlling input nodes of the transmitter to have values representative of a logical 1 or a logical 0 irrespective of a value of the differential input signal received at that point in time. For example, when the individual components of the differential input signal prior to the falling edge in the data values representative of a logical 1, the input nodes of the transmitter are held at the values representative of the logical 1 even after the differential input signal goes idle. When the individual components of the differential input signal prior to the falling edge in the data values representative of a logical 0, the input nodes of the transmitter are held at the values representative of the logical 0 even after the differential input signal goes idle. The input nodes of the transmitter are held at the final logical value, in some example, by controlling one or more switches (such as components of a bus holder circuit) to couple, or decouple, the input nodes of the transmitter to, or from, one or more voltage sources having values configured to represent the logical 1 and/or the logical 0. The control of the switches is performed, in at least some examples, based on a result of the detection of the falling edge. In at least some examples in which the falling edge of the data was a falling edge (e.g., a final transition) of an EOP indicator of a USB packet, holding the final logical value of the data introduces EOP dribble to the circuit and a width of the EOP dribble (e.g., the predetermined period of time and/or a number of bits of the EOP dribble) is subject to eUSB2 and/or USB specifications.

At operation525, the transmitter is turned off or disabled during the predefined period of time. The transmitter is turned off during the predefined period of time, in at least some examples, to prevent transmission of values received via the differential input signal after the differential input signal has gone idle. Accordingly, in at least some examples, turning off the transmitter during the predefined period of time prevents the transmission of noise by the transmitter between the falling edge of the data and turning off of the transmitter. In at least some examples, the operation525is performed consecutively with the operation520(e.g., such that while the final logical value of the data is being held according to operation520, operation525is performed to turn off the transmitter). In at least some examples, after turning off the transmitter, the input nodes of the transmitter are released (e.g., the final logical value of the data is no longer held) such that the input nodes of the transmitter track, either linearly or non-linearly, the differential input signal.

While the operations of the method500have been discussed and labeled with numerical reference, in various examples the method500includes additional operations that are not recited herein (e.g., such as intermediary comparisons, logical operations, output selections such as via a multiplexer, etc.), in some examples any one or more of the operations recited herein include one or more sub-operations (e.g., such as intermediary comparisons, logical operations, output selections such as via a multiplexer, etc.), in some examples any one or more of the operations recited herein is omitted, and/or in some examples any one or more of the operations recited herein is performed in an order other than that presented herein (e.g., in a reverse order, substantially simultaneously, overlapping, etc.), all of which is intended to fall within the scope of the present disclosure.

In the foregoing discussion, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean either an indirect or direct wired or wireless connection. Thus, if a first device, element, or component couples to a second device, element, or component, that coupling may be through a direct coupling or through an indirect coupling via other devices, elements, or components and connections. Similarly, a device, element, or component that is coupled between a first component or location and a second component or location may be through a direct connection or through an indirect connection via other devices, elements, or components and/or couplings. A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. Furthermore, a circuit or device that is said to include certain components may instead be configured to couple to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be configured to couple to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.

While certain components are described herein as being of a particular process technology (e.g., field effect transistor (FET), metal oxide semiconductor FET (MOSFET), n-type, p-type, drain-extended, natural, etc.), these components may be exchanged for components of other process technologies (e.g., replace FET and/or MOSFET with bi-polar junction transistor (BJT), replace n-type with p-type or vice versa, etc.) and reconfiguring circuits including the replaced components to provide desired functionality at least partially similar to functionality available prior to the component replacement. Components illustrated as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the illustrated resistor. Additionally, uses of the phrase “ground voltage potential” in the foregoing discussion are intended to include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of the present disclosure. Unless otherwise stated, “about”, “approximately”, or “substantially” preceding a value means+/−10 percent of the stated value.

The above discussion is meant to be illustrative of the principles and various examples of the present disclosure. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the present disclosure be interpreted to embrace all such variations and modifications.