System and method for providing live insertion

System and method for providing live insertion. According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a first port configured to be electrically coupled to a pad. The first port includes a first connection, a second connection, and a third connection. The integrated circuit also includes a first resistor having a first terminal and a second terminal. Additionally, the integrated circuit includes a second resistor having a third terminal and a forth terminal. The integrated circuit additionally includes a voltage source configured to provided a first voltage. The integrated circuit further includes a first PMOS transistor having a first gate terminal, a first drain terminal and a first source terminal. In addition, the integrated circuit includes a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. 200710039874.8, filed Apr. 24, 2007, commonly assigned, incorporated by reference herein for all purposes.

BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuits. More particularly, the invention provides a system and method for providing live insertion. Merely by way of example, the invention has been applied to system buses. But it would be recognized that the invention has a much broader range of applicability.

A system for providing live insertion has many application. The ability to provide live insertion allows insertion and/or removal of a component in a machine without stopping or turning down the machine. For example, many modem personal computers provides live insertion capabilities. Through universal serial bus port, a computer user is able to “live insert” various peripherals (e.g., mouse, keyboard, flash memory, etc.) to a computer that has already been turned on. For most users, the ability to use the live insertion is high convenient, as they are saved from the trouble of turning machines off and on and wait for booting time.

For applications requiring machines to constantly stay on, such as telecommunication switching and data server, it is even more desirable to be able to provide the live insert capability. For example, it is costly for a telecommunication switch in a network to turn off in order to insert and/or remove hardware components, as turning off a switch could me putting thousands of users offline. Similarly, it is highly preferred that data servers remain on all the time, regardless whether new hardware components are being inserted and/or removed.

Desirable as the live insert capability is, the actual implementation of live insert has been difficult. To be able to provide this capability requires a higher level of complexity. For example, it is usually desirable for the live insertion not to interrupt or interfere with the performance of the machine.

In the past, various conventional techniques have been used to provide live insertion capability. For example, localized component shut down was a common technique. As another example, pre-charge circuits have been used to provide live insertion mechanism. There are many other conventional techniques as well. Unfortunately, these conventional techniques are often inadequate.

Therefore, it is desirable to have an improved system and method for providing live insertion techniques.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to integrated circuits. More particularly, the invention provides a system and method for providing live insertion. Merely by way of example, the invention has been applied to system buses. But it would be recognized that the invention has a much broader range of applicability.

According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a first port configured to be electrically coupled to a pad. The first port includes a first connection, a second connection, and a third connection. The integrated circuit also includes a first resistor having a first terminal and a second terminal. Additionally, the integrated circuit includes a second resistor having a third terminal and a forth terminal. The integrated circuit additionally includes a voltage source configured to provided a first voltage. The integrated circuit further includes a first PMOS transistor having a first gate terminal, a first drain terminal and a first source terminal. In addition, the integrated circuit includes a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal. Furthermore, the integrated circuit includes a third PMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal. The integrated circuit also includes a first NMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal. The integrated circuit also includes an I/O pad comprising a plurality of connectors. The plurality of connectors includes a ground connector, a voltage connector, and an I/O connector. The integrated circuit additionally includes a first control circuit providing a first control signal. The first control signal is associated with the I/O pad. In addition, the integrated circuit includes a second control circuit providing a second control signal and a third control signal.

The first source terminal and the third source terminal are electrically coupled to the voltage source. The first gate terminal and the second gate terminal are configured to receive the first control signal. The first drain terminal is electrically coupled to the first terminal. The second terminal is electrically coupled to the I/O pad and the third terminal. The fourth terminal is electrically coupled to the second source terminal. The second drain terminal and the fourth source terminal are biased at ground. The third drain terminal and the fourth source terminal are electrically coupled to the I/O pad. The third gate terminal is configured to receive the second control signal. The fourth gate terminal is configured to receive the third control signal. During a precharge state, the first control signal indicates an “on” signal, and the second control and third control signals indicate an “off” signal.

According to another embodiment, the present invention provides a method for providing live insertion between a component and a system. The method includes a step for providing a voltage source configured to a first voltage. Addition, the method includes a step for providing an I/O pad, the I/O pad including a ground connector, a voltage connector, and an I/O connector. The method also includes a step for providing first control circuit, the first control circuit being configured to provide a first control signal. The method additionally includes a step for providing a second control circuit. The second control circuit is configured to provide a second and a third control signal. The method includes a step for providing a first switching circuit configured to receive the first control signal. The first switching circuit is electrically coupled to the I/O pad. Addition, the method includes a step for providing a second switching circuit configured to receive the second and the third control signal. The second switching circuit is electrically coupled to the I/O pad. Furthermore, the method includes a step for electrically coupling the ground connector to the system while the voltage connector and the I/O connector are open. In addition, the method includes a step for electrically coupling the voltage connector to the system while the voltage connector remains electrically coupled to the system and the I/O connector remains open. Furthermore, the method includes a step for providing the first control signal indicating an “on” state. In addition, the method includes a step for providing the second control signal and the third control signal indicating a first “off” state. Moreover, the method includes a step for charging the I/O pad to a threshold voltage by the first switching circuit in response to the first control signal indicating the “on” state. Additionally, the method includes a step for causing the I/O pad to be in a high-impedance state by the second switching circuit in response the second control signal and the third control signal indicating the first “off” state. In addition, the method includes a step for electrically coupling the I/O connector to the system. Also, the method includes a step for providing the first control signal indicating a second “off” state. Moreover, the method includes a step for turning off the first switching circuit in response to the first control signal indicating the second “off” state.

According to yet another embodiment, the present invention provides an integrated circuit. The integrate circuit includes a first port configured to be electrically coupled to a pad. The first port including a first connection, a second connection, and a third connection. In addition, the integrate circuit includes a first resistor having a first terminal and a second terminal. Furthermore, the integrate circuit includes a second resistor having a third terminal and a forth terminal. Additionally, the integrate circuit includes a voltage source configured to provided a first voltage. Also, the integrate circuit includes a first transistor having a first gate terminal, a first transistor terminal and a second transistor terminal. Moreover, the integrate circuit includes a second transistor having a second gate terminal, a third transistor terminal, and a fourth transistor terminal. In addition, the integrate circuit includes a third transistor having a third gate terminal, a fifth transistor terminal, and a sixth source terminal. Furthermore, the integrate circuit includes a first transistor having a fourth gate terminal, a seventh transistor terminal, and an eighth transistor terminal. Further, the integrate circuit includes an I/O pad comprising a plurality of connectors. The plurality of connectors includes a ground connector, a voltage connector, and an I/O connector. The integrate circuit also includes a first control circuit providing a first control signal. Additionally, the integrate circuit includes a second control circuit providing a second control signal and a third control signal.

The sixth and seventh transistor terminals are electrically coupled to the I/O pad. The first gate terminal and the second gate terminal are configured to receive the first control signal. The third gate terminal is configured to receive the second control signal. The fourth gate terminal is configured to receive the third control signal. The I/O pad is in a high impedance state when the ground connector is biased at ground and the voltage connector and the I/O connector are open. The first gate terminal and the second gate terminal are configured to receive the first control signal. The first control signal turns the first transistor and the second transistor off when the ground connector is biased at ground and the voltage connector and the I/O connector are open. The second control signal turns the third transistor off when the ground connector is biased at ground and the voltage connector and the I/O connector are open. The third control signal turns the fourth transistor off when the ground connector is biased at ground and the voltage connector and the I/O connector are open. The I/O pad is charged to a predetermine voltage level when the ground connector is biased at ground, the voltage connector is connected to the voltage source, and the I/O connector is open. The first control signal turns the first transistor and the second transistor on when the ground connector is biased at ground, the voltage connector is connected to the voltage source, and the I/O connector is open.

It is to be appreciated that, according to various embodiments, the present invention provides various advantages over conventional techniques. For example, the present invention ensures system stability during a live insertion process. According to an embodiment, an I/O pad is charged to a threshold voltage before I/O connections are connected. For example, the precharged I/O pad does not cause the system being connected to flip into an invalid state. There are other benefits as well.

The benefits and various additional objects, features and advantages of the present invention can be fully appreciated with reference to the detailed description and accompanying drawings that follow.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to integrated circuits. More particularly, the invention provides a system and method for providing live insertion. Merely by way of example, the invention has been applied to system buses. But it would be recognized that the invention has a much broader range of applicability.

As discussed above, various conventional techniques for providing live insertion capability have been inadequate. For example, various convention techniques are often inadequate to ensure that the system for live insertion remains stable throughout the process.

FIG. 1is a simplified diagram illustrating a live insertion process. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. During a live insertion process, an insertion pad110is connected to a bus106of a system100. As shown inFIG. 1, the insertion pad110usually has an impedance. Usually, the impedance of the insertion pad110is high. During the insertion process, the high impedance of the insertion pad110often forces the signal carried by the bus106to a difference voltage. For example, the insertion pad110forces the bus signal to a ground state. As another example, the insertion pad110forces the bus signal to a VCC state. Usually, the change in voltage on the bus signal is asymptotically related to the impedance of the insertion pad. Such change of voltage on the bus signal usually causes problems for the system100, as the system100could be forced into an invalid state as a result. When the bus106is being used for transmitting as the live insertion process occurs, the system100is even more likely to fall into an invalid state.

FIG. 2is a simplified diagram illustrating a conventional system that provides live insertion. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 2, a conventional system200is used to provide live insertion capability. A live insertion is to be established between the socket210and the card connector211. It is to be noted that pins on card connector211have different length. For example, a pin212for connection to the ground has the longest protrusion so that the ground connection is established first during the live insertion process. A pin213for connecting to the bias voltage has the second longest protrusion so that the bias voltage connection is established right after the ground pin212is connected. This particular order of connection provides some protection to the system during the live insertion process. For example, the connection of ground and bias voltage allows the connecting circuit to be pre-charged before the input and output (I/O) port230are connected. Typically, the I/O port230has a voltage that equals to half of the bias voltage at the time when I/O port230is connected. While conventional techniques as used for system200provides some measures of hardware protection, such techniques are often inadequate.

FIG. 3is a simplified diagram illustrating effects of live insertion on a conventional system. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, graphs310and320illustrate the insertion process on the system200fromFIG. 2. The graph310illustrates an effect of live insertion when the bus signal is at voltage level VCC. As seen in graph310, the insertion of a high impedance pad causes an abrupt voltage drop of the bus signal to a voltage level below a threshold voltage. For example, the threshold voltage is used to determine when the bus signal is at high or low. The temporary voltage drop to below the threshold voltage can causes an error reading or a “logic flip” (i.e., an incorrect logic low reading). Often, live insertion techniques practice in conventional systems also causes bus contention.

The graph320illustrates an effect of live insertion when the bus signal is biased at ground. As seen in graph320, the insertion of a high impedance pad causes an abrupt voltage rise of the bus signal to a voltage level above a threshold voltage. For example, the threshold voltage is used to determine when the bus signal is at high or low. The temporary voltage rise to above the threshold voltage can causes an error reading or a “logic flip” (i.e., an incorrect logic high reading). Often, live insertion techniques practice in conventional systems also causes bus contention. Therefore, it is to be appreciated that according to various embodiments, the present invention provides a superior solution for live insertion.

FIG. 4is a simplified diagram illustrating a live insertion system according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The live insertion system400includes the following components:1. insertion pad410;2. a PMOS405;3. a PMOS406;4. a resistor411;5. a resistor412;6. a PMOS420;7. an NMOS421;8. a PMOS430; and9. a PMOS431.

As shown inFIG. 4, the insertion pad410is being connected.FIG. 5is a simplified diagram illustrating an insertion pad according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the PMOS405and406may be implemented with NMOS transistors.

As shown, insertion pins have difference lengths. A pin501for connection to the ground has the greatest length, a pin502for connection to VCC has the second greatest length, and a pin503for connection to the I/O has the shortest length. During the insertion process, the ground connection is established first, then the VCC connection is established, and the I/O connection is established last.

Now referring back to theFIG. 4. During the insertion process, the ground connection is established first. Next, the bias voltage VCC is connected and the insertion device is charged to a predetermined voltage. For example, the predetermined voltage is a threshold voltage at VCC/2 at the node401. According to the embodiment, the resistors411and412have substantially the same resistance so that the voltage drop between VCC and ground is equally divided between the two resistors. For example, when the VCC is 3.3 volts, the node401has a voltage of 1.65 volts.

When the bias voltage VCC is connected, the PMOS420and NMOS421are both turned off, which causes the insertion pad410to stay at a high impedance state. For example, the respective “on” and “off” states of the PMOS420and the NMOS421are controlled by an external circuit. When PMOS420turns on, the insertion pad410is charge to the VCC voltage. Depending upon applications, the PUDC can be used to turn the PMOS420and NMOS421on or off.

The time to charge the insertion pad410depends from various factors, such as the load on the insertion pad, etc. During the time when the insertion pad410is being charged, the PMOS405and406are at an “on” state, where electrical current is conducted through the PMOS405and406. The “on” state of the PMOS405and406is based on the input from a power on detection circuit (PUDC).

FIG. 6is a simplified diagram illustrating a power on detection circuit (PUDC) according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. In addition, it is to be appreciated that depending upon applications, the present invention may be implemented with other types of PUDC circuits. A PUDC circuit600inFIG. 6includes a voltage supply601, a level shift circuit620, and a path630. The PUDC600receives a voltage input from the voltage supply601by the level shift circuit620. For example, the voltage supply601has a core power voltage of 1.2 volt. The level shift circuit620is configured to provide a predetermined voltage to the path630. For example, the predetermined voltage is 3.3 volt. For example, the path630includes one or more inverters to provide further adjustment at the output640. It is to be appreciated that depending upon application, the PUDC600is configured to provide any voltage levels that are required to turn on or off the PMOS inFIG. 4. Since PMOS transistors are used, a zero voltage from the PUDC600turns on the PMOS, and an operating voltage (e.g., 3.3 volts) turns off the PMOS. According to another embodiment wherein PMOS transistors are replaced with NMOS transistors, the PUDC600provides a high voltage level for turning the transistors on and a low voltage level for turning the transistors off.

FIG. 7is a simplified diagram illustrating voltages level of various terminals. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 7, the output of the PUDC is based on two input voltages. When the first input voltage710is at 3.3 volts, the PUDC has a zero output voltage. For example, the first input voltage710is the VCC voltage inFIG. 4. When both the first input voltage710is at 3.3 volts and the second input voltage720is at 1.2 volt, the PUDC carries a voltage of 3.3 volts. For example, the second input voltage720comes from a separate voltage source that is connected to the PUDC.

Now referring back toFIG. 4. The PMOS405and406are at an “on”state before the I/O pin of the insertion pad is connected. For example, a zero voltage at the gates of the PMOS405and406by the PUDC turns the transistors on. Once the I/O pin of the insertion pad410is connected, the PMOS405and406are turned off by the PUDC600. According to an embodiment, the PMOS405and406are turned on when PUDC is at zero volt, and PMOS405and406are turned off when PUDC is at 3.3 volts.

It is to be appreciated that by the time the I/O pin of the insertion pad is connected, the insertion pad has been pre-charged to a proper voltage. According to the embodiment, the present invention ensures that insertion pad is proper charged before I/O's are connected. As a benefit of the present invention, the system400does not fall into an invalid state during the live insertion process.

FIG. 8is a simplified diagram illustrating effects of live insertion on a conventional system. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, graphs810and820illustrate the insertion process on the system400fromFIG. 4. The graph810illustrates an effect of live insertion when the bus signal is at voltage level VCC. As seen in graph810, the insertion of a high impedance pad causes an abrupt voltage drop of the bus signal. However, the voltage drop does not cause the voltage level to drop below the threshold voltage. For example, the threshold voltage is used to determine when the bus signal is at high or low. The temporary voltage drop in the graph810does not causes an error reading or a “logic flip” (i.e., an incorrect logic low reading).

FIG. 9is a simplified diagram illustrating a live insertion system900according to an embodiment of the present invention. System900includes a first resistor R1having a first terminal and a second terminal, a second resistor R2having a third terminal and a forth terminal, a voltage source Vcc configured to provided a first voltage, a first PMOS transistor having a first gate terminal, a first drain terminal and a first source terminal, a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal, a third PMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal, and a first NMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal. System900also includes a first control circuit providing a first control signal1, the first control signal1is associated with an I/O pad. System900further includes a second control circuit2providing a second control signal2and a third control signal3. In an embodiment, the first source terminal and the third source terminal are electrically coupled to the voltage source, and the first gate terminal and the second gate terminal are configured to directly receive the first control signal1, the first drain terminal is electrically coupled to the first terminal, the second terminal is electrically coupled to the I/O pad and the third terminal, the fourth terminal is electrically coupled to the second source terminal, the second drain terminal and the fourth source terminal are biased at a ground potential, the third drain terminal and the fourth source terminal are electrically coupled to the I/O pad, the third gate terminal is configured to receive the second control signal2, the fourth gate terminal is configured to receive the third control signal. In an embodiment, during a precharge state, the first control signal1indicates an “on” signal, and the second and third control signals indicate an “off” signal.

The graph820illustrates an effect of live insertion when the bus signal is biased at ground. As seen in graph820, the insertion of a high impedance pad causes an abrupt voltage rise of the bus signal. However, the voltage drop does not cause the voltage level to rise above the threshold voltage. For example, the threshold voltage is used to determine when the bus signal is at high or low. The small temporary voltage rise as shown in the graph820does not cause an error reading or a “logic flip” (i.e., an incorrect logic high reading). Therefore, it is to be appreciated that the present invention provides a safer system and method for live insertion, as compared to convention techniques.

According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a first port configured to be electrically coupled to a pad. The first port includes a first connection, a second connection, and a third connection. The integrated circuit also includes a first resistor having a first terminal and a second terminal. Additionally, the integrated circuit includes a second resistor having a third terminal and a forth terminal. The integrated circuit additionally includes a voltage source configured to provided a first voltage. The integrated circuit further includes a first PMOS transistor having a first gate terminal, a first drain terminal and a first source terminal. In addition, the integrated circuit includes a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal. Furthermore, the integrated circuit includes a third PMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal. The integrated circuit also includes a first NMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal. The integrated circuit also includes an I/O pad comprising a plurality of connectors. The plurality of connectors includes a ground connector, a voltage connector, and an I/O connector. The integrated circuit additionally includes a first control circuit providing a first control signal. The first control signal is associated with the I/O pad. In addition, the integrated circuit includes a second control circuit providing a second control signal and a third control signal.

The first source terminal and the third source terminal are electrically coupled to the voltage source. The first gate terminal and the second gate terminal are configured to receive the first control signal. The first drain terminal is electrically coupled to the first terminal. The second terminal is electrically coupled to the I/O pad and the third terminal. The fourth terminal is electrically coupled to the second source terminal. The second drain terminal and the fourth source terminal are biased at ground. The third drain terminal and the fourth drain terminal are electrically coupled to the I/O pad. The third gate terminal is configured to receive the second control signal. The fourth gate terminal is configured to receive the third control signal. During a precharge state, the first control signal indicates an “on” signal, and the second control and third control signals indicate an “off” signal. For example, the embodiment is illustrated inFIGS. 4-6.

According to another embodiment, the present invention provides a method for providing live insertion between a component and a system. The method includes a step for providing a voltage source configured to produce a first voltage. Additionally, the method includes a step for providing an I/O pad, the I/O pad including a ground connector, a voltage connector, and an I/O connector. The method also includes a step for providing a first control circuit, the first control circuit being configured to provide a first control signal. The method additionally includes a step for providing a second control circuit. The second control circuit is configured to provide a second control signal and a third control signal. The method includes a step for providing a first switching circuit configured to receive the first control signal. The first switching circuit is electrically coupled to the I/O pad. Additionally, the method includes a step for providing a second switching circuit configured to receive the second control signal and the third control signal. The second switching circuit is electrically coupled to the I/O pad. Furthermore, the method includes a step for electrically coupling the ground connector to the system while the voltage connector and the I/O connector are open. In addition, the method includes a step for electrically coupling the voltage connector to the system while the ground connector remains electrically coupled to the system and the I/O connector remains open. Furthermore, the method includes a step for providing the first control signal indicating an “on” state. In addition, the method includes a step for providing the second control signal and the third control signal indicating a first “off” state. Moreover, the method includes a step for charging the I/O pad to a threshold voltage by the first switching circuit in response to the first control signal indicating the “on” state. Additionally, the method includes a step for causing the I/O pad to be in a high-impedance state by the second switching circuit in response to the second control signal and the third control signal indicating the first “off” state. In addition, the method includes a step for electrically coupling the I/O connector to the system. Also, the method includes a step for providing the first control signal indicating a second “off” state. Moreover, the method includes a step for turning off the first switching circuit in response to the first control signal indicating the second “off” state. For example, the embodiment is illustrated inFIGS. 4-6.

According to yet another embodiment, the present invention provides an integrated circuit. The integrate circuit includes a first port configured to be electrically coupled to a pad. The first port including a first connection, a second connection, and a third connection. In addition, the integrate circuit includes a first resistor having a first terminal and a second terminal. Furthermore, the integrate circuit includes a second resistor having a third terminal and a forth terminal. Additionally, the integrate circuit includes a voltage source configured to provide a first voltage. Also, the integrate circuit includes a first transistor having a first gate terminal, a first transistor terminal and a second transistor terminal. Moreover, the integrate circuit includes a second transistor having a second gate terminal, a third transistor terminal, and a fourth transistor terminal. In addition, the integrate circuit includes a third transistor having a third gate terminal, a fifth transistor terminal, and a sixth source terminal. Furthermore, the integrate circuit includes a fourth transistor having a fourth gate terminal, a seventh transistor terminal, and an eighth transistor terminal. Further, the integrate circuit includes an I/O pad comprising a plurality of connectors. The plurality of connectors includes a ground connector, a voltage connector, and an I/O connector. The integrate circuit also includes a first control circuit providing a first control signal. Additionally, the integrate circuit includes a second control circuit providing a second control signal and a third control signal. For example, the embodiment is illustrated inFIGS. 4-6.

The sixth and seventh transistor terminals are electrically coupled to the I/O pad. The first gate terminal and the second gate terminal are configured to receive the first control signal. The third gate terminal is configured to receive the second control signal. The fourth gate terminal is configured to receive the third control signal. The I/O pad is in a high impedance state when the ground connector is biased at ground and the voltage connector and the I/O connector are open. The first gate terminal and the second gate terminal are configured to receive the first control signal. The first control signal turns the first transistor and the second transistor off when the ground connector is biased at ground and the voltage connector and the I/O connector are open. The second control signal turns the third transistor off when the ground connector is biased at ground and the voltage connector and the I/O connector are open. The third control signal turns the fourth transistor off when the ground connector is biased at ground and the voltage connector and the I/O connector are open. The I/O pad is charged to a predetermine voltage level when the ground connector is biased at ground, the voltage connector is connected to the voltage source, and the I/O connector is open. The first control signal turns the first transistor and the second transistor on when the ground connector is biased at ground, the voltage connector is connected to the voltage source, and the I/O connector is open.

It is to be appreciated that, according to various embodiments, the present invention provides various advantages over conventional techniques. For example, the present invention ensures system stability during a live insertion process. According to an embodiment, an I/O pad is charged to a threshold voltage before I/O connections are connected. For example, the precharged I/O pad does not cause the system being connected to flip into an invalid state. There are other benefits as well.