Power module and power converter

An object of the present invention is to increase the reliability of a power module and a power converter and to extend their life. In order to achieve this, a power module includes: two switching devices each including a diode and a transistor, the two switching devices being electrically connected in parallel; and an insulating substrate on which the two switching devices are mounted. Further, a gate electrode of MOFET that each of the two switching device has is electrically connected to a gate resistance. Further, of the two switching devices, the gate resistance that is electrically connected to the switching device, whose current value is smaller when a predetermined voltage is applied in the forward direction of the body diode, is greater than the gate resistance that is electrically connected to the switching device whose current value is larger.

BACKGROUND

The present invention relates to a power module and power converter having a plurality of semiconductor chips including a built-in diode.

For example, power semiconductor chips are widely used for power converters such as inverter and convertor, or for power modules such as power control devices. Then, with increasing power capacity or other causes leading to an increase in the heat generated by semiconductor chips, the power module is required to have high reliability even in a high temperature environment.

In the power converter and the power control device, when a plurality of semiconductor chips are connected in parallel, the current balance of the semiconductor chips is an important factor in achieving high reliability.

Note that with respect to a voltage-driven power semiconductor device, for example, Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-235015 (Patent Literature 1) discloses a method for storing in advance a gate current value that achieves the most balanced distribution of current so as to improve the current balance in each element, and controlling each gate current control circuit based on the stored data.

SUMMARY

In recent years, the development of semiconductor such as SiC capable of high temperature operation has been promoted. In SiC, a stacking fault may grow by the energy generated when current is applied to a PN junction. In such a case, the electric resistance of the drift layer increases and the device characteristics are degraded. Then, in the power module or other device in which a plurality of semiconductor chips are electrically connected in parallel, when the characteristics of any one of the semiconductor chips are degraded, the current is concentrated in the other semiconductor chips and heat generation increases, and thus there is a possibility that the semiconductor chips will be destroyed.

An object of the present invention is to provide a technique that can increase the reliability of a power module and a power converter, and can extend their life.

The above and other objects and novel features of the present invention will become apparent from the description and drawings of the following specification.

The typical ones of the inventions disclosed in the present application will be briefly described as follows.

A power module according to an embodiment, includes: a plurality of semiconductor chips each including a built-in diode and a transistor that are electrically connected to each other, the semiconductor chips being electrically connected in parallel; and a substrate on which the semiconductor chips are mounted. A gate electrode of the transistor that each of the semiconductor chips has is electrically connected to a gate resistance. Further, in any two of the semiconductor chips, the gate resistance that is electrically connected to a semiconductor chip whose current value is smaller when a predetermined voltage is applied in the forward direction of the diode, is greater than the gate resistance that is electrically connected to a semiconductor chip whose current value is larger when the predetermined voltage is applied in the forward direction of the diode.

Further, a power module according to an embodiment, includes: first and second semiconductor chips each including a built-in diode and a transistor that are electrically connected to each other, the first and second semiconductor chips being electrically connected in parallel; and a substrate on which the first and second semiconductor chips are mounted. A gate electrode of the transistor that each of the first and second semiconductor chips has is electrically connected to a gate resistance. Further, of the first and second semiconductor chips, the gate resistance electrically connected to a semiconductor chip whose current value is smaller when a predetermined voltage is applied in the forward direction of the diode, is greater than the gate resistance that is electrically connected to a semiconductor chip whose current value is larger when the predetermined voltage is applied in the forward direction of the diode.

Further, a power converter according to an embodiment includes a first wiring, and a second wiring with an electrical potential lower than the first wiring. Further, the power converter also includes: a high-side transistor unit located between the first wiring and the second wiring, the high-side transistor unit being electrically connected to the first and second wirings; and a low-side transistor unit located between the first wiring and the second wiring, the low-side transistor unit being electrically connected to the first and second wirings and being electrically connected in series to the high-side transistor unit. Further, a plurality of transistors are electrically connected in parallel to each of the high-side transistor unit and the low-side transistor unit. Each of the transistors is electrically connected to the diode, and the gate electrode of each of the transistors is electrically connected to the gate resistance. Further, in each of the high-side transistor unit and the low-side transistor unit, the gate resistance that is electrically connected to a transistor whose current value is smaller when a predetermined voltage is applied in the forward direction of the diode, is greater than the gate resistance that is electrically connected to a transistor whose current value is larger when the predetermined voltage is applied in the forward direction of the diode.

The effect obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

It is possible to increase the reliability of a power module and a power converter and to extend their life.

DETAILED DESCRIPTION

First Embodiment

FIG. 1is a plan view showing an example of the structure of a power module according to a first embodiment of the present invention, andFIG. 2is a circuit diagram of the power module shown inFIG. 1.

First, the structure of a power module100according to the first embodiment is described with reference toFIGS. 1 and 2.

The power module100of the first embodiment shown inFIG. 1is configured with a plurality of semiconductor chips (hereinafter, also simply referred to as chips) mounted on a substrate. The following description will be given assuming that each of the semiconductor chips is a switching device. Here, the case of mounting two semiconductor chips on a substrate is described as an example. Then, in the power module100, the two semiconductor chips are electrically connected in parallel.

Further, the power module100has a metallic heat radiation base101and an insulating substrate (substrate)102is provided on the heat radiation base101. Then, the insulating substrate is provided with various wiring patterns (hatched part inFIG. 1) over the surface through an insulating layer103. In other words, various wiring patterns are provided on the insulating layer103formed on the surface of the insulating substrate102, in such a way that the wiring patterns are isolated (separated) from each other.

In the case of the power module100shown inFIG. 1, for example, conductive patterns such as a gate wiring pattern104, a source sense wiring pattern105, a drain wiring pattern106, and a source wiring pattern107are formed separately from each other on the insulating layer103.

Then, a first switching device (first semiconductor chip)108aand a second switching device (second semiconductor chip)108bare provided on the drain wiring pattern106, respectively, through a conductive bonding material (for example, such as solder). In order to maintain the current capacity, the first switching device108aand the second switching device108bare electrically connected in parallel as shown inFIG. 2, and are mounted on the drain wiring pattern106.

Further, in the first embodiment, the description assumes that the first switching device108aand the second switching device108bare each comprised of silicon carbide (SiC).

Note that the first switching device108ahas a source pad108eand a gate pad108gon the surface side. Also, the second switching device108bhas a source pad108fand a gate pad108hon the surface side.

Then, the source pad108eof the first switching device108aand the source wiring pattern107of the insulating substrate102are electrically connected by a plurality of source wires112which are conductive wires. Further, the source pad108eof the first switching device108aand the source sense wiring pattern105of the insulating substrate102are electrically connected by a source sense wire111which is a conductive wire.

Further, the gate pad108gof the first switching device108aand the gate wiring pattern104of the insulating substrate102are electrically connected by a gate wire110which is a conductive wire. At this time, in the power module100according to the first embodiment, a first gate resistance109a, which is a chip resistance, is mounted on the gate wiring pattern104. Then, the gate wire110and the gate wiring pattern104are electrically connected through the first gate resistance109a. In other words, the gate wire110is electrically connected to the gate resistance pad109ethat the first gate resistance109ahas.

On the other hand, the source pad108fof the second switching device108band the source wiring pattern107of the insulating substrate102are electrically connected by a plurality of source wires112. Further, the source pad108fof the second switching device108band the source sense wiring pattern105of the insulating substrate102are electrically connected by the source sense wire111.

Further, the gate pad108hof the second switching device108band the gate wiring pattern104of the insulating substrate102are electrically connected by the gate wire110. At this time, in the power module100, similar to the first switching device108a, a second gate resistance109b, which is a chip resistance, is mounted on the gate pattern104. Then, the gate wire110and the gate wiring pattern104are electrically connected through the second gate resistance109b. In other words, the gate wire110on the side of the second switching device108bis electrically connected to the gate resistance pad109fthat the second gate resistance109bhas.

In the power module100according to the first embodiment, as shown inFIG. 2, each semiconductor chip is a power system MOSFET (Metal Oxide Semiconductor Field Effect Transistor, hereinafter also referred to as a power MOS)302. A body diode, which is a diode, is built in each switching device. In other words, each switching device is configured with a power MOS and a body diode. Note that body diode is also referred to as built-in diode.

More specifically, the first semiconductor chip is a first MOSFET (power MOS)302aand is applied as the first switching device108a. Then, a body diode301ais built in the first switching device108a. Further, the first switching device108ais electrically connected to the first gate resistance109aon the outside of the first switching device108a. Note that in the first embodiment, the first gate resistance109ais the chip resistance mounted on the gate wiring pattern104.

On the other hand, as shown inFIG. 2, the second semiconductor chip is a second MOSFET (power MOS)302band is applied as the second switching device108b. Then, a second built-in body diode301bis built in the second switching device108b. Further, the second switching device108bis electrically connected to the second gate resistance109bon the outside of the second switching device108b. Note that, similar to the first gate resistance109a, the second gate resistance109bis the chip resistance mounted on the gate wiring pattern104of the insulating substrate102shown inFIG. 1.

Here, as shown inFIG. 2, in each of the first switching device108aand the second switching device108b, each of the first body diode301aand the second body diode301bis electrically connected in the direction opposite to the forward direction L of the circuit.

Further, the drain electrode of each of the first switching device108aand the second switching device108bis electrically connected to a drain terminal201of the power module100.

Further, the source electrode of each of the first switching device108aand the second switching device108bis electrically connected to a source terminal202of the power module100.

Further, a gate electrode108kof the first switching device108ais electrically connected to a gate terminal203of the power module100through the first gate resistance109a. Similarly, a gate electrode108kof the second switching device108bis also electrically connected to the gate terminal203of the power module100through the second gate resistance109b.

Here, in order to reduce current variation in each chip during the use of the body diode (built-in diode), the power module100according to the first embodiment is designed to select semiconductor chips with similar voltage characteristics in the forward direction L in the stage of chip screening in the manufacturing of the power module100.

However, it is difficult to select chips with exactly the same characteristics. Thus, in the power module100according to the first embodiment, the gate resistance that is electrically connected to a switching device whose current value is smaller when a predetermined voltage is applied in the forward direction L of the body diode, is set to be greater than the gate resistance that is electrically connected to a switching device whose current value is greater when the predetermined voltage is applied in the forward direction L of the diode. More specifically, the gate resistance connected to a switching device whose current value is smaller when a predetermined voltage in the forward direction L of the body diode, is set to be greater than the gate resistance connected to a switching device whose current value is greater when the predetermined voltage is applied in the forward direction L of the diode. In other words, in the stage of chip screening, semiconductor chips with similar voltage characteristics in the forward direction L are selected and mounted. Then, in the assembly of the power module100, chip resistances which become gate resistances, each of which has a different resistance value, are mounted on the insulating substrate102. In this way, the gate resistance that is electrically connected to a switching device whose current value is smaller when a predetermine voltage is applied in the forward direction L of the body diode, is set to be greater than the gate resistance that is electrically connected to a switching device whose current value is larger when the predetermined voltage is applied in the forward direction L of the diode.

For example, when the current value when a predetermined voltage is applied in the forward direction L of the body diode301is larger in the first switching device108athan in the second switching device108b, the current distribution of the second switching device108bincreases during back flow.

Then, the temperature is higher in the second switching device108bin which the current distribution increases. The body diode301has a characteristic that the higher the temperature the more the current is likely to flow, so that the balance of current flowing through each element is degraded.

Thus, in the power module100according to the first embodiment, when the current value when a predetermined voltage is applied in the forward direction L of the body diode301is smaller in the first switching device108athan in the second switching device108b, the gate resistance (chip resistance) greater than the gate resistance of the second switching device108bis connected to the first switching device108ato increase the switching loss. In this way, it is possible to increase the current distribution of the first switching device108aand to reduce the difference in the heat generation and temperature between the semiconductor chips.

Note that the magnitude of the current value when a predetermined voltage is applied in the forward direction L of the body diode (built-in diode) is based on the comparison of the specific characteristics of each of the body diodes.

As an example, under the same temperature and humidity conditions, when the current value when a predetermined voltage is applied in the forward direction L of the body diode is smaller in the first switching device108athan in the second switching device108b, a resistance (for example, a chip resistance) whose resistance value is greater than that of the second gate resistance109bis used for the first gate resistance109a.

As described above, in the power module100according to the first embodiment, of the parallel-connected switching devices (semiconductor chips), by increasing the gate resistance connected to a switching device whose current value is greater when a predetermine voltage is applied in the forward direction L of the body diode, it is possible to increase the switching loss of the switching device whose current value is smaller. In this way, the temperature of the switching device with the smaller current value increases, so that the voltage in the forward direction L can be reduced.

As a result, it is possible to prevent current concentration in other switching devices (semiconductor chips), and to improve the current balance (current distribution) in each element.

Thus, it is possible to prevent destruction of semiconductor chips caused by heat generation or other factors and to increase the reliability of the power module100. At the same time, it is possible to extend the life of the power module100.

Note that by using the chip resistance as the gate resistance, the assembly of the power module100can be facilitated by using a plurality of chip resistances with different resistance values, even after chip screening and chip mounting in the assembly of the power module100.

Next, MOSFET (power MOS) shown inFIGS. 3 and 4is described as an example of applying the power MOS to the switching device.FIG. 3is a cross-sectional view showing an example of the structure of the main part of a semiconductor chip mounted in the power module shown inFIG. 1.FIG. 4is a cross-sectional view showing a variation of the structure of the main part of the semiconductor chip mounted in the power module shown inFIG. 1.

The MOSFET shown inFIG. 3is DMOSFET (Double-diffusion Metal Oxide Semiconductor Field Effect Transistor). DMOSFET has an N+substrate406in the bottom part, and an N−layer405is formed in the upper layer. Further, a P body layer404is formed in the upper layer of the N−layer405. Further, a P+layer403and an N+layer402are formed above the P body layer404so that the P+layer403and the N+layer402are embedded in the P body layer404.

Further, on the main surface including the N+layer402and the P+layer403, a source electrode401is formed so as to be electrically connected to the N+layer402and the P+layer403. Further, a gate electrode408is formed on the main surface through a gate insulating film409. The gate electrode408is arranged so as to at least overlap the P body layer404in a plan view. On the other hand, a drain electrode407is formed on the back surface.

Further, the MOSFET shown inFIG. 4is a trench MOSFET. Similar to DMOSFET, the trench MOSFET includes an N+substrate406in the bottom part, and the N−layer405is formed in the upper layer of the N+substrate406. Further, the P body layer404is formed above the N−layer405. Further, the P+layer403and the N+layer402are formed above the P body layer404. Then, on the main surface including the N+layer402and the P+layer403, the source electrode401is formed so as to be electrically connected to the N+layer402and the P+layer403.

Further, a groove410is formed so as to reach the N−layer405from the main surface including the N+layer402and the P+layer403, passing through the N+layer402and the P body layer404. The gate electrode408is formed in the groove410through the gate insulating film409. On the other hand, similar to DMOSFET, the drain electrode407is formed on the back surface.

Then, each of DMOSFET shown inFIG. 3and trench MOSFET shown inFIG. 4includes a diode in which the source electrode401serves as anode and the drain electrode407serves as cathode. Note that the N−layer405is also an epitaxial layer411. In other words, each of DMOSFET and trench MOSFET is also power MOS including the epitaxial layer411.

Thus, when the power module is DMOSFET shown inFIG. 3and trench MOSFET shown inFIG. 4, and when the power module includes the semiconductor chip of SiC with the built-in power MOS including the epitaxial layer411, a stacking fault may grow in the epitaxial layer411by the energy generated when applying current to the PN junction.

The next describes the manufacturing method of the power module according to the first embodiment.FIG. 5is a process flow diagram showing an example of the manufacturing procedure of the power module according to the first embodiment of the present invention.FIG. 6is a schematic diagram showing an example of PL analysis results (whole wafer) in the manufacturing procedure shown inFIG. 5.FIG. 7is a schematic diagram showing an example of PL analysis results (chip region) in the manufacturing procedure shown inFIG. 5.

The manufacturing method of the power module100is described by using the flow shown inFIG. 5. First, PL (Photo Luminescence) analysis of Step S1shown inFIG. 5is performed. The PL analysis is a technique to determine crystal defects by irradiating an object with light. The PL analysis first generates a PL mapping of the whole wafer in a semiconductor wafer500shown inFIG. 6. Note that inFIG. 6, dashed lines are scribe lines501as the mark for dicing, and the area surrounded by dashed lines is one chip region502. The PL analysis counts the number of basal plane dislocations (BPD)503shown in FIG.7that are present in each chip region502. As a result, when a predetermined number or more of basal plane dislocations503are found in a semiconductor chip, it is determined that the semiconductor chip is defective.

After that, the semiconductor wafer500is cut along the scribe lines501, and then only non-defective chips proceed to the next process. Note that because the plane coordinates of the basal plane dislocation503can be located on the semiconductor wafer500, it is possible to determine the presence or absence of the basal plane dislocation503in each chip region by combining the coordinates of the scribe lines501.

Note thatFIG. 7shows the results of the PL analysis of one chip region502as an example, in which the basal plane dislocation503(BPD) is observed as a linear form.

Further, the PL analysis observes the basal plane dislocations503within the N−-type epitaxial layer. In the case in which the basal plane dislocation503is present within the N−-type epitaxial layer, the basal plane dislocation503grows to form a stacking fault by the recombination energy when applying current to the PN junction when the current returns to the built-in diode. The stacking fault functions as an electrical resistance and the drift resistance of the N−layer405(epitaxial layer411) shown inFIGS. 3 and 4increases. Thus, when a switching device including the basal plane dislocation503is used, characteristic deterioration occurs in the switching device and in the built-in diode. The degree of the characteristic deterioration depends on the number and positions of the basal plane dislocations503within the semiconductor chip. For this reason, the characteristic deterioration is different in each chip.

Thus, the characteristic deterioration by the stacking fault growth causes current variation among chips. The basal plane dislocations503, which are the cause of the stacking fault growth, are observed by the PL analysis, and for example, only semiconductor chips not including the basal plane dislocations503are used in the power module100. In this way, it is possible to prevent the characteristic deterioration during the operation of the power module100, and to prevent the current variation associated with the characteristic deterioration.

In the flow shown inFIG. 5, Step S2shows MOSFET manufacturing, which is device manufacturing, after the PL analysis. However, the PL analysis can also be performed during the manufacturing process of MOSFET as long as the PL analysis is performed before electrode formation.

After the PL analysis, device manufacturing shown in Step S2is performed. In the device manufacturing, the MOSFET shown inFIGS. 3 and 4is manufactured.

After the device manufacturing, non-detective product inspection shown in Step S3is performed. This non-defective product inspection is a fully automatic inspection that is performed on all the semiconductor chips (chip regions502) in the state of the semiconductor wafer500, regardless of the results of the PL analysis. The non-defective product inspection includes the contents such as subthreshold characteristics of MOSFET, transfer characteristics, output characteristics, leakage current, dielectric strength, forward direction voltage of the body diode, and gate insulating film reliability.

After the non-defective product inspection, dicing shown in Step S4is performed. In the dicing, the semiconductor wafer500is cut along the scribe lines501shown inFIG. 6to divide the semiconductor wafer500into individual semiconductor chips.

After the dicing, PL and electrical characteristic non-defective product screening shown in Step S5is performed. In the PL and electrical characteristic non-defective product screening, semiconductor chips in which leakage currents or other defects are found, as well as semiconductor chips with a large number of basal plane dislocations are not transmitted to current stress test, which is the next step, but are screened out in this step.

After the PL and electrical characteristic non-defective product screening, the current stress test shown in Step S6is performed. The current stress test applies current stress to the semiconductor chip determined to be non-defective in the PL and electrical characteristic non-defective product screening.

After the current stress test, current stress test non-defective product screening shown in Step S7is performed. In the current stress test non-defective product screening, the semiconductor chips are screened out when determined that the deterioration level exceeds a predetermined threshold in the current stress test. In other words, the current stress test compares the characteristics between before and after current stress. For example, the percentage of the ratio between before deterioration and after deterioration is set in advance as a threshold to determine NG. Then, in the case of semiconductor chips determined as NG based on the ratio between before deterioration and after deterioration, these semiconductor chips are screened out.

After the current stress test non-defective product screening, electrical characteristic inspection (chip) shown in Step S8is performed. In the electrical characteristic inspection, the electrical characteristic inspection of semiconductor chip is performed again. In other words, the electrical characteristics are measured again because a characteristic change within a tolerance may occur even if the semiconductor chip passed the current stress test.

After the electrical characteristic inspection (chip) is performed, chip screening shown in Step S9is performed. The chip screening performs screening in such away that the semiconductor chip with the smaller current value when a predetermined voltage is applied in the forward direction L shown inFIG. 2accordingly has a large gate resistance after assembly. For example, the screening first refers to the results of the electrical characteristic inspection (chip) of Step S8, and selects semiconductor chips with similar characteristics such as body diodes. In other words, the chip screening determines one pair of semiconductor chips to be mounted on the power module100(or determines a combination of mounted semiconductor chips).

After the chip screening, module assembly shown in Step S10is performed. In other words, the assembly of the power module100shown inFIG. 1is performed. In this assembly process, for example, the power module100according to the first embodiment implements the first gate resistance109aand the second gate resistance109b, which are chip resistances, on the gate wiring pattern104of the insulating substrate102, and adjusts the magnitude of the gate resistance that is electrically connected to each semiconductor chip.

In this way, in the power module100, of the first switching device108a(first semiconductor chip) and the second switching device108b(second semiconductor chip) which are connected in parallel, it is designed to increase the gate resistance connected to the switching device (semiconductor chip) with the smaller current value when a predetermined voltage is applied in the forward direction L of the body diode.

In the assembly of the power module100, the first switching device108aand the second switching device108bare mounted on the drain wiring pattern106of the insulating substrate102. At the same time, the first gate resistance109aand the second gate resistance109b, which are chip resistances, are mounted on the gate wiring pattern104.

After each chip is mounted, each of the first switching device108aand the second switching device108bis electrically connected to a given wiring pattern of the insulating substrate102by a given wire. Further, the first switching device108aand the first gate resistance109aare electrically connected by a given wire. At the same time, the second switching device108band the second gate resistance109bare electrically connected by a given wire.

After the wire bonding, a desired process such as resin sealing is performed to complete the assembly of the power module100.

The next describes a power converter which is an example of the power module of the first embodiment.FIG. 8is a circuit diagram of a power converter which is the power module of the first embodiment.

A power converter1101shown inFIG. 8is an inverter and has a plurality of switching device groups S1to S6. Each of the switching device groups S1to S6is a MOSFET group configured with a plurality of switching devices (transistors)108and a plurality of gate resistances109. Each switching device108is built in the semiconductor chip of SiC. Note that one switching device is shown as a representative of the switching device groups S3to S6to make the figure easy to understand.

Further, series-connected two switching device groups (for example, S1and S2) are not tuned on at the same time. In other words, when the switching device group S1is turned off, the switching device group S2is turned on after a fixed time, called dead time, has elapsed. Then, during the dead time, the current flows through the body diode (built-in diode)301of the switching device group S1or the switching device group S2depending on the direction of the load current. This also applies to the switching device groups S3and S4and to the switching device groups S5and S6.

The configuration of the power converter1101is described here in detail. The power converter1101includes a high-side (high-potential side) line (first line)1102, as well as a low-side (low-potential side) line1103in which the potential is lower than the line1102. Further, the power converter1101includes switching device groups S1, S3, and S5which are high-side transistor units provided between the line1102and the line1103. The switching device groups S1, S3, and S5are electrically connected to the line1102and the line1103. Further, the power converter1101includes switching device groups S2, S4, and S6which are low-side transistor units provided between the line1102an the line1103. The switching device groups S2, S4, and S6are electrically connected to the line1102and the line1103, and at the same time, are electrically connected in series to the switching device groups S1, S3, and S5, respectively.

More specifically, the switching device group S1, which is electrically connected to the line1102, and the switching device group S2, which is electrically connected to the line1103, are electrically connected in series between the line1102and the line1103. Further, the switching device group S3, which is electrically connected to the line1102, and the switching device group S4, which is electrically connected to the line1103, are electrically connected in series between the line1102and the line1103. Further, the switching device group S5, which is electrically connected to the line1102, and the switching device group S6, which is electrically connected to the line1103, are electrically connected in series between the line1102and the line1103.

Note that each of the power supply voltage VCC and the capacitor C is electrically connected between the line1102and the line1103. Further, each of the switching device groups S1, S2, S3, S4, S5, and S6is electrically connected to a load (LOAD)1104. The load1104is, for example, a three-phase AC motor.

Further, each of the gate resistances109of the switching device group S1is electrically connected to a gate drive circuit GD1. Similarly, each of the gate resistances109of the switching device group S2is electrically connected to a gate drive circuit GD2, and each of the gate resistances109of the switching device group S3is electrically connected to a gate drive circuit GD3. Further, each of the gate resistances109of the switching device group S4is electrically connected to a gate drive circuit GD4, and each of the gate resistances109of the switching device group S5is electrically connected to a gate drive circuit GD5. Then, each of the gate resistances109of the switching device group S6is electrically connected to a gate drive circuit GD6.

Note that the switching devices (transistors)108are electrically connected in parallel in the switching device groups S1, S3, S5, which are high-side transistor units, and in the switching device groups S2, S4, S6, which are low-side transistor units. Further, each of the switching devices108is electrically connected to the body diode (built-in diode)301. Further, the gate electrode108kof each of the switching devices108is electrically connected to the gate resistance109.

Then, the power converter1101is configured such that, in each of the switching device groups S1, S2, S3, S4, S5, and S6, the resistance value is greater in the gate resistance109electrically connected to the switching device108with the smaller current value when a predetermined voltage is applied in the forward direction L of the body diode301, than in the gate resistance109electrically connected to the switching device108with the larger current value when the predetermined voltage is applied in the forward direction L of the body diode301.

With this configuration, also in the power converter1101according to the first embodiment, it is possible to increase the switching loss of the switching device108with the smaller current value in each switching device group. In this way, the temperature of the switching device108with the smaller current value increases, so that the current distribution can be increased. As a result, it is possible to prevent current concentration in other switching devices108, and to improve the current balance in each element. In this way, it is possible to increase the reliability of the power converter1101, and to extend the life of the power converter1101.

Second Embodiment

FIG. 9is a plan view showing an example of the structure of a power module according to a second embodiment of the present invention.FIG. 10is a circuit diagram of the power module shown inFIG. 9.

A power module600according to the second embodiment shown inFIG. 9is configured in such away that three or more switching devices are electrically connected in parallel. The second embodiment describes a case in which three switching devices are mounted on the power module600. As shown inFIG. 10, three switching devices are a first switching device (first semiconductor chip)108a, a second switching device (second semiconductor chip)108b, and a third switching device (third semiconductor chip)108c. The three switching devices108are electrically connected in parallel in order to maintain the current capacity.

In other words, also in the power module600, the third semiconductor chip is a third MOSFET (power MOS)302c, which is applied as the third switching device108c. Then, a third body diode (diode)301cis built in the third switching device108c.

Further, also in the power module600, each of the first switching device108a, the second switching device108b, and the third switching device108cis comprised of silicon carbide (SiC).

Note that the power module600is the same as the power module100of the first embodiment with respect to the structure of the insulating substrate102, the implementation structure of the first switching device108aand the second switching device108b, and the structure of the wire connection among the wiring patterns (hatched part inFIG. 9) of the insulating substrate102of each switching device. Thus, their descriptions will be omitted.

Here, the third switching device108chas a source pad108iand a gate pad108jon the surface side. Then, the source pad108iof the third switching device108cand the source wiring pattern107of the insulating substrate102are electrically connected by a plurality of source wires112which are conductive wires. Further, the source pad108iof the third switching device108cand the source sense wiring pattern105of the insulating substrate102are electrically connected by the source sense wire111which is a conductive wire.

Further, the gate pad108jof the third switching device108cand the gate wiring pattern104of the insulating substrate102are electrically connected by the gate wire110which is a conductive wire. At this time, also in the power module600, a third gate resistance109c, which is a chip resistance, is mounted on the gate wiring pattern104. The gate wire110and the gate wiring pattern104are electrically connected through the third gate resistance109c. In other words, the gate wire110is electrically connected to a gate resistance pad109gthat the third gate resistance109chas.

Further, as shown inFIG. 10, the third body diode (diode)301cis built in the third switching device108c. Further, the third switching device108cis electrically connected to the third gate resistance109con the outside of the third switching device108c. Also in the second embodiment, the third gate resistance109cis a chip resistance mounted on the gate wiring pattern104of the insulating substrate102shown inFIG. 11.

Further, as shown inFIG. 10, the third body diode301cbuilt in the third switching device108cis electrically connected in the direction opposite to the forward direction L of the circuit.

Note that, also in the power module600, the drain electrode of each of the first switching device108a, the second switching device108b, and the third switching device108cis electrically connected to the drain terminal201of the power module600.

Further, the source electrode of each of the first switching device108a, the second switching device108b, and the third switching device108ccis electrically connected to the source terminal202of the power module600.

Further, the gate electrode108kof the third switching device108cis electrically connected to the gate terminal203of the power module600through the third gate resistance109c, similar to the gate electrode108kof the first switching device108aas well as the gate electrode108kof the second switching device108b.

Also in the second embodiment, when comparing two of the parallel-connected three switching devices, the resistance value is greater in the gate resistance connected to the semiconductor chip with the smaller current value when a predetermined voltage is applied to the forward direction L of the body diode301, than in the gate resistance connected to the semiconductor chip with the larger current value when the predetermined voltage is applied in the forward direction L.

For example, in the power module600, it is assumed that the current value when the predetermined voltage is applied in the forward direction L of the first body diode301abuilt in the first switching device108ais smaller than the current value when the predetermined voltage is applied in the forward direction L of the second body diode301bbuilt in the second switching device108b. In this case, the chip resistance with the resistance value greater than the second gate resistance109bis used for the first gate resistance109a.

Further, it is assumed that the current value when a predetermined voltage is applied in the forward direction L of the second body diode301bbuilt in the second switching device108bis smaller than the current value when the predetermined voltage is applied in the forward direction L of the third body diode301cbuilt in the third switching device108c. In this case, the chip resistance with the resistance value greater than the third gate resistance109cis used for the second gate resistance109b.

In this way, also in the power module600according to the second embodiment, in any two of the three semiconductor chips, it is possible to increase the switching loss of the semiconductor chip whose current value is smaller. In this way, the temperature of the semiconductor chip with the smaller current value increases and so the current distribution can be increased. As a result, it is possible to prevent current concentration in other semiconductor chips, and to improve the current balance (current distribution) in each chip. In this way, it is possible to increase the reliability of the power module600, and to extend the life of the power module600.

Third Embodiment

FIG. 11is a plan view showing an example of the structure of a power module according to a third embodiment of the present invention.FIG. 12is a circuit diagram of the power module shown inFIG. 11.

The third embodiment describes a case in which a gate resistance is built in a semiconductor chip which is a switching device mounted on a power module700shown inFIG. 11. Further, the description focuses on the case in which two semiconductor chips (switching devices) are mounted on the power module700.

Thus, the chip resistance, which is provided as a gate resistance on the gate wiring pattern104of the insulating substrate102in the power module100according to the first embodiment, is not provided in the power module700of the third embodiment.

In other words, as shown inFIG. 12, the first body diode301aand the first gate resistance109aare built in the first switching device108a, respectively. Further, the second body diode301band the second gate resistance109bare built in the second switching device108b, respectively.

Also in the power module700, similar to the first embodiment, the resistance value is made greater in the gate resistance connected to the semiconductor chip with the smaller current value when a predetermined voltage is applied in the forward direction L of the body diode301, than in the gate resistance connected to the semiconductor chip with the greater current value when the predetermined voltage is applied in the forward direction L of the body diode301.

For example, when the current value is smaller in the first switching device108awhen the predetermined voltage is applied in the forward direction L of the body diode301, the first switching device108aselects a semiconductor chip in such a way that the resistance of the built-in gate resistance is greater than in the second switching device108b. In other words, the semiconductor chips are selected in such a way that the resistance value of the built-in gate resistance109is greater in the first switching device108athan in the second switching device108b.

More specifically, in the chip screening process of Step S9shown inFIG. 5, a combination of two semiconductor chips is selected in such a way that the resistance value of the built-in gate resistance109is greater in the semiconductor chip of the first switching device108athan in the semiconductor chip of the second switching device108b. Then, the two selected semiconductor chips are mounted on the insulating substrate102in the assembly of the power module700.

In other words, in the first semiconductor chip and the second semiconductor chip that are selected as described above, the current value when a predetermined voltage is applied in the forward direction L of the built-in first body diode301ais smaller in the first switching device108awhich is the first semiconductor chip, than in the second switching device108b. At the same time, the resistance value of the built-in first gate resistance109ais greater in the first switching device108athan in the second switching device108b.

By mounting the first semiconductor chip and the second semiconductor chip that are selected as described above, it is possible to increase the switching loss of the semiconductor chip with the smaller current value also in the power module700. In this way, the temperature of the semiconductor chip with the smaller current value increases, so that the voltage in the forward direction L can be reduced. As a result, it is possible to prevent current concentration in other semiconductor chips, and to improve the current balance (current distribution) in each chip. In this way, it is possible to increase the reliability of the power module700, and to extend the life of the power module700.

Further, of the first and second semiconductor chips, the resistance of the MOSFET (switching device) of the semiconductor chip including the built-in gate resistance109with the greater resistance value can be made greater than the resistance of the MOSFET (switching device) of the semiconductor chip including the built-in gate resistance109with the smaller resistance value.

As described above, by adjusting the magnitude of the resistance of the MOSFETs in the first semiconductor chip and the second semiconductor chip, the temperature of the semiconductor chip with the smaller current value when the predetermined voltage is applied in the forward direction L increases. Thus, it is possible to reduce the voltage in the forward direction L.

In this way, it is possible to prevent current concentration in other semiconductor chips and to improve the current balance (current distribution) in each chip. As a result, it is possible to further increase the reliability of the power module700and to further extend the life of the power module700.

The invention made by the present inventors has been concretely described based on exemplary embodiments. However, the present invention is not limited to the above exemplary embodiments but includes various modifications and variations. For example, the above exemplary embodiments have been described in detail to better illustrate the present invention, and are not necessarily limited to those having all configurations described in the exemplary embodiments.

Further, part of the configuration of an embodiment can be replaced by the configuration of other embodiments, and the configuration of an embodiment can be added to the configuration of other embodiments. Further, addition, deletion, and replacement of other configurations can be made with respect to part of the configuration of each embodiment. Note that the members and relative sizes shown in figures are simplified and idealized to make the present invention easy to understand, which have however a more complicated shape in the implementation.

For example, the first and second embodiments have described a case in which chip resistances with different resistance values are used as a means of adjusting the resistance value in such a way that the gate resistance, which is connected to the semiconductor chip with the smaller current value when a predetermined voltage is applied in the forward direction L of the body diode, is made greater than the gate resistance connected to the semiconductor chip with the larger current value. However, it is also possible to establish a magnitude relationship of the gate resistance by means other than the chip resistance.

For example, in a plurality of semiconductor chips, it is also possible to establish a magnitude relationship of the gate resistance by changing the thickness (diameter), shape, material, or number of conductive wires that electrically connect between the gate pad of the semiconductor chip and the gate wiring pattern of the insulating substrate.

Further, each semiconductor chip is not limited to that of SiC, but may be comprised of Si (silicon).

Further, the above embodiments have focused on semiconductor chips with MOSFETs as an example. However, it is also possible that semiconductor chips have transistors other than MOSFETs.