Self-aligned top via

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. Mandrels are patterned on a liner, where the liner is located on a semiconductor substrate. Spacers are formed on sidewalls of the mandrels. Dielectric material lines are formed on exposed surfaces of the liner and within a plurality of gaps between the spacers. The mandrels are removed. The at least one of the dielectric material lines are removed from within at least one of the plurality of gaps between the spacers. Conductive metal is formed within each gap. The conductive metal is patterned to form metal interconnect lines and vias. The plurality of spacers and the remaining dielectric material lines are removed.

BACKGROUND

The present invention relates generally to the field of semiconductor structures and fabrication, and more particularly to the fabrication of a top via and metal interconnect line structure.

Back end of line (BEOL) is the portion of integrated circuit fabrication where the individual devices (transistors, capacitors, resisters, etc.) get interconnected with wiring on the wafer, the metallization layer. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.

A via is an electrical connection between layers in a physical electronic circuit that goes through the plane of one or more adjacent layers. In integrated circuit design, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers.

Damascene processing is an additive process where a dielectric is deposited, the dielectric is etched according to a defined pattern, metal is filled according to the pattern, and excess metal is removed by chemical-mechanical polishing/planarization (CMP).

SUMMARY

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. The method can include patterning mandrels on a liner, where the liner is located on a semiconductor substrate. The method can also include forming spacers on sidewalls of the mandrels. The method can also include forming dielectric material lines on exposed surfaces of the liner and within a plurality of gaps between the spacers. The method can also include removing the mandrels. The method can also include removing at least one of the dielectric material lines within at least one of the plurality of gaps between the spacers. The method can also include forming conductive metal within each gap. The method can also include patterning the conductive metal to form metal interconnect lines and vias. The method can also include removing the plurality of spacers and the remaining dielectric material lines.

Embodiments of the invention may additional include alternate methods for fabricating a semiconductor device and the resulting structure. The method can include providing a dielectric layer located on a surface of a liner, wherein the liner is located on a surface of a semiconductor substrate. The method can also include forming a plurality of trenches of a depth that exposes a surface of the liner and creates dielectric material lines from the remaining dielectric layer. The method can also include forming spacers on sidewalls of the dielectric material lines. The method can also include removing at least one of the dielectric material lines that is between two of the spacers. The method can also include forming conductive metal within each present gap. The method can also include patterning the conductive metal to form metal interconnect lines and vias. The method can also include removing the plurality of spacers and the remaining dielectric material lines.

DETAILED DESCRIPTION

Embodiments of the present invention describe a method to form a self-aligned back end of line (BEOL) metal line and top via structure and the resulting structure. Embodiments of the present invention recognize that conductive metal is optically opaque and can cause alignment and overlay challenges. Thick conductive metals can cause high stress resulting in wafer warpage. Further, embodiments of the present invention recognize that subtractive etching of thick metal can cause bad line edge roughness, mouse biting, or other issues. Embodiments of the present invention recognize that damascene techniques may improve line edge roughness when compared to subtractive patterning, but can cause line wiggling issues. Accordingly, embodiments of the present invention describe an approach that forms metal interconnect lines via damascene and vias by subtractive etching processes, resulting in structures where both metal interconnect lines and vias are self-aligned. Further, embodiments of the present invention recognize that such an approach does not require scaffolds, as the utilized spacers act as a scaffold and is removed after the top via formation.

FIG. 1depicts an isometric view of a device at an early stage in the method of forming the device. The semiconductor structure ofFIG. 1incudes a semiconductor material stack comprising hardmask130, on a surface of dielectric layer120, on a surface of liner110, on a surface of semiconductor substrate100.

Semiconductor substrate100may be composed of a silicon containing material. Silicon containing materials include, but are not limited to, silicon, single crystal silicon, polycrystalline silicon, SiGe, single crystal SiGe, polycrystalline SiGe, or silicon doped with carbon (Si:C), amorphous silicon, and combinations and multi-layers thereof. Semiconductor substrate100can also be composed of other semiconductor materials, such as germanium (Ge), and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., gallium arsenide (GaAs). Semiconductor substrate100may be, in some embodiments, wafers with front-end-of-line (FEOL), middle-of-the-line (MOL), and/or BEOL metals. In general, semiconductor substrate100is a smooth surface substrate.

Liner110is formed by sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD) and is a conductor such as titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, liner110may be comprised of other conductive materials such as aluminum (AL), copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), or combinations thereof.

Dielectric layer120is deposited on top of liner110. Dielectric layer120is generally a layer of insulating material. Dielectric layer120can be composed of, for example, silicon nitride (SiN), silicon carbonitride (SiCN), (SiOCN), (SiBCN), or other insulating materials known in the art. Dielectric layer120is deposited such that dielectric layer120has a thickness corresponding to the combined desired height of the via and metal line of the eventual resulting device.

Hardmask130is deposited on top of dielectric layer120. A hardmask is a material used in semiconductor processing as an etch mask. Hardmask130is composed of metal or a dielectric material such as, for example, SiN, silicon oxide, or a combination of silicon nitride and silicon oxide which may be deposited using, for example, a process such as low pressure chemical vapor deposition (LPCVD). In various embodiments, standard photolithographic processes are used to define a pattern of hardmask130in a layer of photoresist (not shown) deposited on hardmask130. The desired hardmask pattern may then be formed in hardmask130by removing hardmask130from the areas not protected by the pattern in the photoresist layer. Hardmask130is removed using, for example, reactive ion etching (ME). ME uses chemically reactive plasma, generated by an electromagnetic field, to remove various materials. A person of ordinary skill in the art will recognize that the type of plasma used will depend on the material of which hardmask130is composed, or that other etch processes such as wet chemical etching or laser ablation may be used. While not depicted, hardmask130maybe patterned such that hardmask130covers the area of dielectric layer120that becomes mandrels210(seeFIG. 2).

FIG. 2depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 2shows the formation of mandrels210from dielectric layer120and the removal of hardmask130. Mandrels are used in spacer patterning. Spacer patterning is a technique employed for patterning features with linewidths smaller than can be achieved by conventional lithography. In general, a spacer (e.g., spacers310, seeFIG. 3) is deposited over the mandrel (e.g., mandrels210), and the mandrel is a pre-patterned feature. The spacer is subsequently etched back so that the spacer portion covering the mandrel is etched away while the spacer portion on the sidewall remains. The mandrel may then be removed, leaving two spacers (one for each edge) for each mandrel.

Mandrels210may be formed by an etching process, such as ME, laser ablation, or any etch process which can be used to selectively remove a portion of material such as dielectric layer120. As described above with reference toFIG. 1, hardmask130may be patterned to cover mandrels210and utilized during the etching process in the creation of mandrels210. The etching process only removes the portions of dielectric layer120not protected by hardmask130and the etching process stops at liner110. Each of the mandrels have a height equal to the combined height of the desired metal line and via heights.

In some embodiments, subsequent to the formation of mandrels210, hardmask130is removed. In general, the process of removing hardmask130involves the use of an etching process such as RIE, laser ablation, or any etch process which can be used to selectively remove a portion of material, such as hardmask130. In alternate embodiments, hardmask130may not be removed at this time and remains on the device until a later metal chemical mechanical polishing/planarization (CMP) step (seeFIG. 7) is performed.

FIG. 3depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 3shows the formation of spacers310on the exposed sides of mandrels210. Spacers310are composed of metal (e.g., TiN, TaN) or any dielectric spacer material including, for example, a dielectric oxide, dielectric nitride, and/or dielectric oxynitride. In some embodiments, spacers310are composed of a non-conductive low-capacitance dielectric material such as silicon dioxide (SiO2). In general, spacers310are composed of a material different from liner110. The process of forming spacers310may include depositing a conformal layer (not shown) of insulating material, such as silicon nitride, over exposed surfaces of liner110and mandrels210. Spacers310can be deposited using, for example CVD, plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or other deposition processes. An anisotropic etch process, where the etch rate in the forward direction is greater than the etch rate in the lateral directions, may be used to remove portions of the insulating layer, thereby forming spacers310located on the sidewalls of mandrels210, as depicted inFIG. 3.

FIG. 4depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 4shows the formation of dielectric layer410on liner110and within the exposed gaps between spacers310. Portions of dielectric layer410within each of the exposed gaps may create a plurality of dielectric material lines. As described above with reference to dielectric layer120, dielectric layer410is generally a layer of insulating material and may be composed of, for example, SiN, SiCN, SiOCN, SiBCN, or other insulating materials known in the art. In some embodiments, dielectric layer410is a layer of low-κ dielectric material. Low-κ is a material with a small relative dielectric constant (κ) relative to SiO2. Low-κ materials include, for example, fluorine-doped SiO2, organosilicate glass (OSG), porous SiO2, porous organosilicate glass, spin-on organic polymeric dielectrics, and spin-on silicon based polymeric dielectrics. In some embodiments, dielectric layer410is spin-on-glass. Spin-on-glass is an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric surface. In some embodiments, dielectric layer410is deposited using flowable chemical vapor deposition (fCVD) or spin-on dielectric methods. Dielectric layer410may be created by depositing dielectric layer410above the desired height and then utilizing a planarization process, such as CMP, to reduce the height of dielectric layer410such that the top surface of mandrels210are exposed.

FIG. 5depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 5shows the removal of mandrels210to create a first trench within the gaps depicted ofFIG. 5. Mandrels210may be removed using an etching process that is selective in removing physically exposed portions of mandrels210relative to spacers310and dielectric layer410to create the gaps that comprise the first trench. The etching process utilized may be a dry etching or wet etching process.

FIG. 6depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 6shows the removal of portions of dielectric layer410to create a second trench. One or more dielectric material lines may be removed. In the depicted embodiment, the middle and end portions of dielectric layer410are not removed. The portion of dielectric layer410that are removed may be removed by the use of a standard photolithographic process to define the desired shape of the second trench in a layer of photoresist (not shown) deposited on the top surface of spacers310, dielectric layer410, and/or liner110. In various embodiments, standard photolithographic processes are used to remove a portion of the photoresist layer corresponding to the areas of dielectric layer which are to be removed in the formation of the second trench. The portion or dielectric layer410may be removed using, for example, a dry etch process such as RIE to remove the desired portion(s) of dielectric layer410. As a result of etching the portions of dielectric layer410, liner110is exposed in the area defined as the second trench.

FIG. 7depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 7shows the formation of conductive metal710within the gaps that comprise the first and second trenches. Conductive metal710may be any type of conductive metal. For example, conductive metal710may be composed of Ru, Co, molybdenum (Mo), tungsten (W), Al, or rhodium (Rh). Conductive metal710may be deposited using, for example, CVD, PECVD, PVD, or other deposition processes. Conductive metal710may be created by depositing conductive metal710above the desired height and subsequently utilizing a planarization process, such as CMP, to reduce the height of conductive metal710such that the top surfaces of spacers310and dielectric layer410are exposed.

In some embodiments, where spacers310are comprised of TiN, line wiggle may be reduced compared to other material usage. Embodiments of the present invention recognize that templates with higher modulus can mitigate post metal fill line wiggling. A TiN template, where spacers310are composed of TiN has a modulus of about 500 gigapascals (GPa), which is higher than many other materials.

FIG. 8depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 8shows the formation of a top via and metal interconnect line by subtractive patterning processes, during which non-via portions of conductive metal710are recessed to target depths for the desired via structure. The formation of the top via may be performed using photolithographic subtractive patterning processes. A masking step is utilized to form vias in conductive metal710. Such masking may entail depositing a photoresist layer and patterning the layer using ultra-violet light, enabling removal of only selected portions of the photoresist, and then etching conductive metal710in accordance with the photoresist pattern. It shall be noted that the depicted arrangement of the vias inFIG. 8(and subsequent similar figures) may vary based on implementation details of the final desired via structure. In some embodiments, a selective etching process may be utilized. In some embodiments, such as the embodiment depicted inFIG. 8, dielectric layer410may be damaged as a result of the etching process, which is represented inFIG. 8by the reduced height of dielectric layer410.

FIG. 9depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 9shows the selective removal of spacers310and dielectric layer410and a resulting via structure that includes one or more vias formed in conductive metal710and liner110on semiconductor substrate100. Spacers310and dielectric layer410may be removed using an etching process that is selective in removing physically exposed portions of spacers310and/or dielectric layer410relative to conductive metal710to remove all of spacers310and dielectric layer410and expose portions of liner110. The etching process utilized may be dry etching or wet etching process.

In some embodiments, exposed portions of liner110remain on semiconductor substrate100. In other embodiments, exposed portions of liner110are etched away, such that liner110is only present under conductive metal710(seeFIG. 16, where conductive metal1310is similar to conductive metal710).

The resulting structure is a BEOL metal line and top via structure. The structure may be, for example, a metal-insulator-metal capacitor that includes metal lines formed by damascene and top vias formed by subtractive processes where spacers310act as scaffold during the top via etching process.

FIGS. 10-16depict embodiments of the present invention that are formed according to a different fabrication process that begins with a trench etch.

The fabrication process depicted byFIG. 10is performed on the same device originally depicted inFIG. 1, which, as previously described, depicts an isometric view of a device that includes a semiconductor material stack comprising hardmask130, on dielectric layer120, on liner110, on semiconductor substrate100.

FIG. 10depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 10shows the removal of portions of hardmask130and dielectric layer120to create trenches. The trenches may be formed by an etching process, such as RIE, laser ablation, or any etch process which can be used to selectively remove a portion of material, such as dielectric layer120. Hardmask130may be patterned as depicted inFIG. 10, prior to performing the etching process, to aid in the creation of the trenches by preventing the remaining portions of dielectric layer120to be removed during the etching process. The etching process only removes the portions of dielectric layer120not protected by hardmask130and the etching process stops at liner110. The trench width is selected based on a sum of the final desired metal line width and spacer thickness. In some embodiments, the trench width is equal to three times the final desired metal line width. The remaining portions of dielectric layer120may form dielectric material lines.

FIG. 11depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 11shows the formation of spacers1110on the exposed sides of dielectric layer120. Spacers1110are composed of metal (e.g., TiN, TaN) or any dielectric spacer material including, for example, a dielectric oxide, dielectric nitride, and/or dielectric oxynitride. In some embodiments, spacers1110are composed of a non-conductive low-capacitance dielectric material such as silicon dioxide (SiO2). In general, spacers1110are composed of a material different from liner110. The process of forming spacers1110may include depositing a conformal layer (not shown) of insulating material, such as silicon nitride, over exposed surfaces of liner110and mandrels dielectric layer120. Spacers310can be deposited using, for example CVD, plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or other deposition processes. An anisotropic etch process, where the etch rate in the forward direction is greater than the etch rate in the lateral directions, may be used to remove portions of the insulating layer, thereby forming spacers1110located on the sidewalls of dielectric layer120, as depicted inFIG. 11.

FIG. 11also depicts the removal of hardmask130. In general, the process of removing hardmask130involves the use of an etching process such as RIE, laser ablation, or any etch process which can be used to selectively remove a portion of material, such as hardmask130.

FIG. 12depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 12shows the removal of portions of dielectric layer120to create a second trench. In the depicted embodiment, the middle and end portions of dielectric layer120are not removed. The portion of dielectric layer120that are removed may be removed by the use of a standard photolithographic process to define the desired shape of the second trench in a layer of photoresist (not shown) deposited on the top surface of spacers1110, dielectric layer120, and/or liner110. In various embodiments, standard photolithographic processes are used to remove a portion of the photoresist layer corresponding to the areas of dielectric layer which are to be removed in the formation of the second trench. The portion or dielectric layer120may be removed using, for example, a dry etch process such as RIE to remove the desired portion(s) of dielectric layer120. As a result of etching the portions of dielectric layer120, liner110is exposed in the area defined as the second trench.

FIG. 13depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 7shows the formation of conductive metal1310within the gaps that comprise the trenches. Conductive metal1310may be any type of conductive metal. For example, conductive metal710may be composed of Ru, Co, Mo, W, Al, or Rh. Conductive metal1310may be deposited using, for example, CVD, PECVD, PVD, or other deposition processes. Conductive metal1310may be created by depositing conductive metal1310above the desired height and subsequently utilizing a planarization process, such as CMP, to reduce the height of conductive metal1310such that the top surfaces of spacers1110and dielectric layer120are exposed.

In some embodiments, where spacers1110are comprised of TiN, line wiggle may be reduced compared to other material usage. Embodiments of the present invention recognize that templates with higher modulus can mitigate post metal fill line wiggling. A TiN template, where spacers1110are composed of TiN has a modulus of about 500 GPa, which is higher than many other materials.

FIG. 14depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 14shows the formation of a top via and metal interconnect line by subtractive patterning processes, during which non-via portions of conductive metal1310are recessed to target depths for the desired via structure. The formation of the top via may be performed using photolithographic subtractive patterning processes. A masking step is utilized to form vias in conductive metal1310. Such masking may entail depositing a photoresist layer and patterning the layer using ultra-violet light, enabling removal of only selected portions of the photoresist, and then etching conductive metal1310in accordance with the photoresist pattern. It shall be noted that the depicted arrangement of the vias inFIG. 14(and subsequent similar figures) may vary based on implementation details of the final desired via structure. In some embodiments, a selective etching process may be utilized. In some embodiments, such as the embodiment depicted inFIG. 14, dielectric layer120may be damaged as a result of the etching process, which is represented inFIG. 14by the reduced height of dielectric layer120.

FIG. 15depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 15shows the selective removal of spacers1110and dielectric layer120and a resulting via structure that includes one or more vias formed in conductive metal1310and liner110on semiconductor substrate100. Spacers1110and dielectric layer120may be removed using an etching process that is selective in removing physically exposed portions of spacers1110and/or dielectric layer120relative to conductive metal1310to remove all of spacers1110and dielectric layer120and expose portions of liner110. The etching process utilized may be dry etching or wet etching process.

In some embodiments, exposed portions of liner110remain on semiconductor substrate100. In other embodiments, exposed portions of liner110are etched away, such that liner110is only present under conductive metal1310(seeFIG. 16).

FIG. 16depicts an isometric view of fabrication steps, in accordance with an embodiment of the present invention.FIG. 15shows the selective removal of exposed portions of liner110. Liner110is removed using etching techniques such as, RIE. RIE uses chemically reactive plasma, generated by an electromagnetic field, to remove various materials. A person of ordinary skill in the art will recognize that the type of plasma used will depend on the material of which liner110is composed, or that other etch processes such as wet chemical etching or laser ablation may be used. In one embodiment, chemical etching is used to remove exposed portions of liner110and expose the surface of semiconductor substrate100. In some embodiments, TiN and TaN wet removal processes may be utilized to remove exposed portions of liner110, such as, for example, when liner110is composed of TiN or TaN.

The resulting structure is a BEOL metal line and top via structure. The structure may be, for example, a metal-insulator-metal capacitor that includes metal lines formed by damascene and top vias formed by subtractive processes where spacers310act as scaffold during the top via etching process.