Gate structure and method

A device includes a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure includes a first dielectric layer over the semiconductor channel, a first work function metal layer over the first dielectric layer, a first protection layer over the first work function metal layer, a second protection layer over the first protection layer, and a metal fill layer over the second protection layer.

BACKGROUND

DETAILED DESCRIPTION

Different threshold voltages (“Vt”) of the semiconductor devices are desirable to optimize performance of circuit elements having widely different functional requirements. Threshold voltage in conventional devices may be tuned by increasing the thicknesses of different work function metals of a gate electrode. However, as the device scaling down process continues, increasing the thicknesses of different work function metals may become unfeasible and/or may lead to various manufacturing difficulties. In advanced technology nodes, gate fill window for multiple Vt tuning by varying thickness of work function metal film with photolithographic patterning becomes difficult due to gate length dimension shrinkage. Such gate fill window challenges can lead to high gate resistance, which is undesirable.

Further to the above, thinner N-type work function (“nWF”) metal deposition, e.g., 10-25 Angstrom TiAlC, with thinner metal gate (5-15 Angstroms or less) multiple patterning is introduced. Thinner nWF metal, such as TiAlC, is very easily oxidized, however. N-type ultra-low threshold voltage (“ulVT”) and P-type standard threshold voltage (“SVT”) devices are more sensitive to nWF metal oxidation, which causes undesirable large Vt shift due to the nWF metal being deposited directly on a high-K (“HK”) dielectric layer close to the Si channel. As such, additional protection layers are introduced in the embodiments to prevent metal oxidation.

Embodiments include at least four techniques for enhancing Vt tuning. First, multiple thinner metal gate layers (e.g., first and second metal gate layers) are patterned. Second, the multiple thinner metal gate layers are selectively removed with etch stop on the HK dielectric layer by an AI-controlled atomic layer etch (“ALE”) process. Third, a thinner third work function (“WF”) metal (e.g., TiAlC, TiN) deposition is performed with multiple protection layers. Fourth, a metal nitride glue layer deposition is added to enhance tungsten gate fill by chemical vapor deposition (“CVD”).

Gate stack structures disclosed herein improve gate fill window, achieve lower gate resistance, and improve reliability for multiple Vt tuning with photolithographic patterning. As such, device performance gain is also improved. Multiple Vt tuning is achieved by selectively depositing additional protection layers between the HK dielectric layer(s) and the glue and metal fill layers. Further reliability improvement is accomplished by reducing loss of the HK dielectric layer(s).

FIG.1Aillustrates a diagrammatic cross-sectional side view of a portion of an IC device10fabricated according to embodiments of the present disclosure, where the IC device10includes gate-all-around (GAA) devices20N,20P. The GAA devices20N,20P may include at least an NFET or a PFET in some embodiments. For example, the GAA device20N is an NFET, and the GAA device20P is a PFET, in accordance with some embodiments. Integrated circuit devices such as the IC device10frequently include transistors having different threshold voltages based on their function in the IC device. For example, input/output (TO) transistors typically have the highest threshold voltages due to the high current handling required of the IO transistors. Core logic transistors typically have the lowest threshold voltages to achieve higher switching speeds at lower operating power. A third threshold voltage between that of the IO transistors and that of the core logic transistors may also be employed for certain other functional transistors, such as static random access memory (SRAM) transistors. Some circuit blocks within the IC device10may include two or more NFETs and/or PFETs of two or more different threshold voltages.

The cross-sectional view of the IC device10inFIG.1Ais taken along an X-Z plane, where the X-direction is the horizontal direction, and the Z-direction is the vertical direction. The GAA devices20N,20P each include channels22A-22C (alternately referred to as “nanostructures”) over a fin structure32. The channels22A-22C are laterally abutted by source/drain features82, and covered and surrounded by gate structures200A/B/C,200D/E/F. In the following description, the gate structure200A and the gate structure200F are described for simplicity. The gate structures200A,200F control flow of electrical current through the channels22A-22C based on voltages applied at the gate structures200A,200F and at the source/drain features82. The threshold voltage is a minimum voltage (e.g., gate-source voltage or source-gate voltage) needed to establish a conducting path in the channels22A-22C. Threshold voltage tuning during fabrication of the various transistors, e.g., IO transistors, core logic transistors, and SRAM transistors, preferably with low modification of the fabrication process, is accomplished by at least one of the techniques applied during fabrication of the gate structures200A,200F, described in greater detail below.

In some embodiments, the fin structure32includes silicon, silicon germanium, or another suitable semiconductor material. In some embodiments, the GAA device20N is an NFET, and the source/drain features82thereof include silicon phosphorous (SiP). In some embodiments, the GAA device20P is a PFET, and the source/drain features82thereof include silicon germanium (SiGe).

The channels22A-22C each include a semiconductive material, for example silicon or a silicon compound, such as silicon germanium, or the like. The channels22A-22C are nanostructures (e.g., having sizes that are in a range of a few nanometers) and may also each have an elongated shape and extend in the X-direction. In some embodiments, the channels22A-22C each have a nano-wire/nanowire (NW) shape, a nano-sheet/nanosheet (NS) shape, a nano-tube/nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of the channels22A-22C may be rectangular, round, square, circular, elliptical, hexagonal, or combinations thereof.

In some embodiments, the lengths (e.g., measured in the X-direction) of the channels22A-22C may be different from each other, for example due to tapering during a fin etching process. In some embodiments, length of the channel22A may be less than a length of the channel22B, which may be less than a length of the channel22C. The channels22A-22C each may not have uniform thickness, for example due to a channel trimming process used to expand spacing (e.g., measured in the Z-direction) between the channels22A-22C to increase gate structure fabrication process window. For example, a middle portion of each of the channels22A-22C may be thinner than the two ends of each of the channels22A-22C. Such shape may be collectively referred to as a “dog-bone” shape.

In some embodiments, the spacing between the channels22A-22C (e.g., between the channel22B and the channel22A or the channel22C) is in a range between about 8 nanometers (nm) and about 12 nm. In some embodiments, a thickness (e.g., measured in the Z-direction) of each of the channels22A-22C is in a range between about 5 nm and about 8 nm. In some embodiments, a width (e.g., measured in the Y-direction, not shown inFIG.1A, orthogonal to the X-Z plane) of each of the channels22A-22C is at least about 8 nm.

The gate structures200A,200F, are disposed over and between the channels22A-22C, respectively. In some embodiments, the gate structure200A is disposed over and between the channels22A-22C, which are silicon channels for N-type devices, and the gate structure200F is disposed over and between, for example, silicon germanium channels for P-type devices.

A first interfacial layer (“IL”)210, which may be an oxide of the material of the channels22A-22C, is formed on exposed areas of the channels22A-22C and the top surface of the fin32. The first IL210promotes adhesion of the gate dielectric layer220to the channels22A-22C. In some embodiments, the first IL210has thickness of about 5 Angstroms (A) to about 50 Angstroms (A). In some embodiments, the first IL210has thickness of about 10 A. The first IL210having thickness that is too thin may exhibit voids or insufficient adhesion properties. The first IL210being too thick consumes gate fill window, which is related to threshold voltage tuning, resistance and reliability as described above.

The gate dielectric layer220includes a high-k gate dielectric material, which may refer to dielectric materials having a high dielectric constant that is greater than a dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In some embodiments, the gate dielectric layer220has thickness of about 5 A to about 100 A. In some embodiments, the gate dielectric layer220comprises at least two HK layers, such as a first high-k dielectric layer including, for example, HfO2with dipole doping (e.g., La, Mg), and a second high-k dielectric layer including, for example, ZrO with crystallization, which is a higher-k material than HfO2. Other suitable combinations of high-k dielectric layers including other suitable materials may also be substituted.

The gate structures200A,200F further include one or more work function metal layers300, a protection layer structure270, and a glue layer280, which may be referred to collectively as the work function metal layer structure900. In the GAA device20N, which is an NFET in most embodiments, the work function metal layer structure900may include at least an N-type work function metal layer, an in-situ capping layer, and an oxygen blocking layer. In some embodiments, the work function metal layer structure900includes more or fewer layers than those described.

The gate structures200A,200F also include metal fill layers290N,290P. The metal fill layers290N,290P may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. Between the channels22A-22C, the metal fill layers290N,290P are circumferentially surrounded (in the cross-sectional view) by the work function metal layer structure900, which are then circumferentially surrounded by the gate dielectric layer220. In the portion of the gate structures200A,200F formed over the channel22A most distal from the fin32, the metal fill layers290N,290P are formed over the work function metal layer structure900. The work function metal layer structure900wraps around the metal fill layers290N,290P. The gate dielectric layer220also wraps around the work function metal layer structure900.

The GAA devices20N,20P also include gate spacers41and inner spacers74that are disposed on sidewalls of the gate dielectric layer220. The inner spacers74are also disposed between the channels22A-22C. The gate spacers41and the inner spacers74may include a dielectric material, for example a low-k material such as SiOCN, SiON, SiN, or SiOC.

The GAA devices20N,20P further include source/drain contacts120that are formed over the source/drain features82. The source/drain contacts120may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. The source/drain contacts120may be surrounded by barrier layers (not shown), such as SiN or TiN, which help prevent or reduce diffusion of materials from and into the source/drain contacts120. A silicide layer118may also be formed between the source/drain features82and the source/drain contacts120, so as to reduce the source/drain contact resistance. The silicide layer118may contain a metal silicide material, such as cobalt silicide in some embodiments, or TiSi in some other embodiments.

The GAA devices20N,20P further include an interlayer dielectric (ILD)130. The ILD130provides electrical isolation between the various components of the GAA devices20N,20P discussed above, for example between the gate structures200A,200F and the source/drain contacts120.

Regions800,810highlighted inFIG.1Aare shown in expanded view inFIG.1BandFIG.1C, respectively.FIG.1Billustrates the gate structure200A in greater detail, andFIG.1Cillustrates the gate structure200F in greater detail. In some embodiments, the gate structure200A corresponds to an ultra-low-Vt, N-type GAA FET. In some embodiments, the gate structure200F corresponds to an ultra-low-Vt, P-type GAA FET.

As shown inFIG.1B, the gate structure200A includes the first IL210on the channel22A, the gate dielectric layer220, a first WF metal layer250, and a capping layer260. In some embodiments, the channel22A is a Si channel for the GAA device20N, which is an N-type device. In the gate structure200A, the protection layer structure270includes a first protection layer271, a second protection layer272, and a third protection layer273, which may be referred to collectively as the protection layers. The protection layer structure270isolates the first WF metal layer250from the glue layer280and the metal fill layer290N. Including three protection layers271,272,273prevents oxidation of the first WF metal layer250, and avoids undesirable shift (increase) in the threshold voltage of the GAA device20N. In some embodiments, each of the protection layers271,272,273is or comprises a metal or a conductive metal oxide. In some embodiments, the first protection layer271may be Si, Ge, SiGe, Al, Ti, Hf, or other suitable material, which can block oxygen diffusion into the WF metal layers300to prevent oxidation of, for example, the first WF metal layer250. In some embodiments, the second and/or third protection layers272,273may be or include metal or a conductive metal oxide, such as Ti, Al, Hf, RuO2, IrO2 or the like. In some embodiments, the first protection layer271and the second and/or third protection layers272,273are or include the same material(s). In some embodiments, materials of the first protection layer271and the second and/or third protection layers272,273are different. Thickness of the first protection layer271may be less than or equal to thickness of the second and/or third protection layers272,273.

In some embodiments, the first IL210comprises at least one element of substrate material, e.g., silicon. In some embodiments, the first WF layer250comprises TiAlC, TiAl, TaAlC, TaAl, or the like. In some embodiments, the capping layer260includes TiN, TiSiN, TaN, WN, MoN, WCN, or the like. In some embodiments, the glue layer280comprises a metal nitride, such as TiN, TaN, MoN, WN, or the like, for better W adhesion. In some embodiments, the metal fill layer290N comprises W, Co, Ru, Ir, Mo, Cu, another low resistivity metal, or the like, as a gate fill material.

As shown inFIG.1C, the gate structure200F includes the first IL210on the channel22A, the gate dielectric layer220, a first WF metal layer250, and a capping layer260. In some embodiments, the channel22A is a SiGe channel for the GAA device20P, which is a P-type device. In the gate structure200F, the protection layer structure270includes the first protection layer271, and is free of the second protection layer272and the third protection layer273. The protection layer structure270including only the single first protection layer271isolates the first WF metal layer250from the glue layer280and the metal fill layer290P less than the tri-layer protection layer structure270included in the gate structure200A. Including the single first protection layer271prevents less oxidation of the first WF metal layer250, allowing a moderate Vt shift (decrease) in the GAA device20P, which is desirable for the uLVT, P-type GAA device20P including the gate structure200F. Similar to described above, the first protection layer271is or comprises a metal or a conductive metal oxide. In some embodiments, the first protection layer271may be Si, Ge, SiGe, Al, Ti, Hf, or other suitable material.

An additional second work function layer700generally includes one or more barrier layers. Each barrier layer may include Ti, Ta, W, Mo, O, C, N, Si, or the like. In some embodiments, each barrier layer includes a metal compound, such as TiN, TaN, WN, MoN, WCN, TiSiN, or the like. In some embodiments, the second work function layer700includes at least a first barrier layer and a second barrier layer (not separately illustrated for simplicity). In some embodiments, the first barrier layer and the second barrier layer are or include the same material. In some embodiments, the first barrier layer and the second barrier layer are or include different materials. In some embodiments, thickness of the first barrier layer is substantially equal to thickness of the second barrier layer (e.g., <1% difference). In some embodiments, the thickness of the first barrier layer is different from the thickness of the second barrier layer. Each of the one or more barrier layers may have thickness ranging from about 5 A to about 20 A. Inclusion of the one or more barrier layers provides additional threshold voltage tuning flexibility. In general, each additional barrier layer increases the threshold voltage. As such, for an NFET, a higher threshold voltage device (e.g., an IO transistor device) may have at least one or more than two additional barrier layers, whereas a lower threshold voltage device (e.g., a core logic transistor device) may have few or no additional barrier layers. For a PFET, a higher threshold voltage device (e.g., an IO transistor device) may have few or no additional barrier layers, whereas a lower threshold voltage device (e.g., a core logic transistor device) may have at least one or more than two additional barrier layers. In the immediately preceding discussion, threshold voltage is described in terms of magnitude. As an example, an NFET IO transistor and a PFET IO transistor may have similar threshold voltage in terms of magnitude, but opposite polarity, such as +1 Volt for the NFET IO transistor and −1 Volt for the PFET IO transistor. As such, because each additional barrier layer increases threshold voltage in absolute terms (e.g., +0.1 Volts/layer), such an increase confers an increase to NFET transistor threshold voltage (magnitude) and a decrease to PFET transistor threshold voltage (magnitude). Based on the above discussion, as an uLVT, N-type GAA device, the GAA device20N comprising the gate structure200A is free of additional barrier layers, so as not to cause an undesirable increase in the threshold voltage.

As described above with respect to the gate structure200A ofFIG.1B, in some embodiments, the first IL210of the gate structure200F ofFIG.1Ccomprises at least one element of substrate material, e.g., silicon. In some embodiments, the first WF layer250comprises TiAlC, TiAl, TaAlC, TaAl, or the like. In some embodiments, the capping layer260includes TiN, TiSiN, TaN, WN, MoN, WCN, or the like. In some embodiments, the glue layer280comprises a metal nitride, such as TiN, TaN, MoN, WN, or the like, for better W adhesion. In some embodiments, the metal fill layer290N comprises W, Co, Ru, Ir, Mo, Cu, another low resistivity metal, or the like, as a gate fill material.

Additional details pertaining to the fabrication of GAA devices are disclosed in U.S. Pat. No. 10,164,012, titled “Semiconductor Device and Manufacturing Method Thereof” and issued on Dec. 25, 2018, as well as in U.S. Pat. No. 10,361,278, titled “Method of Manufacturing a Semiconductor Device and a Semiconductor Device” and issued on Jul. 23, 2019, the disclosures of each which are hereby incorporated by reference in their respective entireties.

FIG.11illustrates a flowchart illustrating a method1000for forming an IC device or a portion thereof from a workpiece, according to one or more aspects of the present disclosure. Method1000is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated in method1000. Additional acts can be provided before, during and after the method1000, and some acts described can be replaced, eliminated, or moved around for additional embodiments of the methods. Not all acts are described herein in detail for reasons of simplicity. Method1000is described below in conjunction with fragmentary cross-sectional views of a workpiece (shown inFIGS.2A-2B,3A-3B,4A-4C,5A-5C,6A-6C,7A-7C,8A-8C,9A-9C, and10A-10C) at different stages of fabrication according to embodiments of method1000. For avoidance of doubt, throughout the figures, the X direction is perpendicular to the Y direction and the Z direction is perpendicular to both the X direction and the Y direction. It is noted that, because the workpiece may be fabricated into a semiconductor device, the workpiece may be referred to as the semiconductor device as the context requires.

InFIG.2AandFIG.2B, a substrate110is provided. The substrate110may be a semiconductor substrate, such as a bulk semiconductor, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The semiconductor material of the substrate110may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as single-layer, multi-layered, or gradient substrates may be used.

Further inFIG.2AandFIG.2B, a multi-layer stack25or “lattice” is formed over the substrate110of alternating layers of first semiconductor layers21A-21C (collectively referred to as first semiconductor layers21) and second semiconductor layers23A-23C (collectively referred to as second semiconductor layers23). In some embodiments, the first semiconductor layers21may be formed of a first semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbide, or the like, and the second semiconductor layers23may be formed of a second semiconductor material suitable for p-type nano-FETs, such as silicon germanium or the like. Each of the layers of the multi-layer stack25may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like.

Three layers of each of the first semiconductor layers21and the second semiconductor layers23are illustrated. In some embodiments, the multi-layer stack25may include one or two each or four or more each of the first semiconductor layers21and the second semiconductor layers23. Although the multi-layer stack25is illustrated as including a second semiconductor layer23C as the bottommost layer, in some embodiments, the bottommost layer of the multi-layer stack25may be a first semiconductor layer21.

Due to high etch selectivity between the first semiconductor materials and the second semiconductor materials, the second semiconductor layers23of the second semiconductor material may be removed without significantly removing the first semiconductor layers21of the first semiconductor material, thereby allowing the first semiconductor layers21to be patterned to form channel regions of nano-FETs. In some embodiments, the first semiconductor layers21are removed and the second semiconductor layers23are patterned to form channel regions. The high etch selectivity allows the first semiconductor layers21of the first semiconductor material to be removed without significantly removing the second semiconductor layers23of the second semiconductor material, thereby allowing the second semiconductor layers23to be patterned to form channel regions of nano-FETs.

InFIG.3AandFIG.3B, fins32are formed in the substrate110and nanostructures22,24are formed in the multi-layer stack25corresponding to act1100ofFIG.11. In some embodiments, the nanostructures22,24and the fins32may be formed by etching trenches in the multi-layer stack25and the substrate110. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. First nanostructures22A-22C (also referred to as “channels” below) are formed from the first semiconductor layers21, and second nanostructures24A-24C are formed from the second semiconductor layers23. Distance CD1between adjacent fins32and nanostructures22,24may be from about 18 nm to about 100 nm.

The fins32and the nanostructures22,24may be patterned by any suitable method. For example, one or more photolithography processes, including double-patterning or multi-patterning processes, may be used to form the fins32and the nanostructures22,24. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing for pitches smaller than what is otherwise obtainable using a single, direct photolithography process. As an example of one multi-patterning process, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins32.

FIGS.3A and3Billustrate the fins32having tapered sidewalls, such that a width of each of the fins32and/or the nanostructures22,24continuously increases in a direction towards the substrate110. In such embodiments, each of the nanostructures22,24may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered), such that width of the fins32and the nanostructures22,24is substantially similar, and each of the nanostructures22,24is rectangular in shape.

InFIGS.3A and3B, isolation regions36, which may be shallow trench isolation (STI) regions, are formed adjacent the fins32. The isolation regions36may be formed by depositing an insulation material over the substrate110, the fins32, and nanostructures22,24, and between adjacent fins32and nanostructures22,24. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. In some embodiments, a liner (not separately illustrated) may first be formed along surfaces of the substrate110, the fins32, and the nanostructures22,24. Thereafter, a fill material, such as those discussed above may be formed over the liner.

The insulation material undergoes a removal process, such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like, to remove excess insulation material over the nanostructures22,24. Top surfaces of the nanostructures22,24may be exposed and level with the insulation material after the removal process is complete.

The insulation material is then recessed to form the isolation regions36. After recessing, the nanostructures22,24and upper portions of the fins32may protrude from between neighboring isolation regions36. The isolation regions36may have top surfaces that are flat as illustrated, convex, concave, or a combination thereof. In some embodiments, the isolation regions36are recessed by an acceptable etching process, such as an oxide removal using, for example, dilute hydrofluoric acid (dHF), which is selective to the insulation material and leaves the fins32and the nanostructures22,24substantially unaltered.

FIGS.2A through3Billustrate one embodiment (e.g., etch last) of forming the fins66and the nanostructures55. In some embodiments, the fins32and/or the nanostructures22,24are epitaxially grown in trenches in a dielectric layer (e.g., etch first). The epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials.

Further inFIG.3AandFIG.3B, appropriate wells (not separately illustrated) may be formed in the fins32, the nanostructures22,24, and/or the isolation regions36. Using masks, an n-type impurity implant may be performed in p-type regions of the substrate110, and a p-type impurity implant may be performed in n-type regions of the substrate110. Example n-type impurities may include phosphorus, arsenic, antimony, or the like. Example p-type impurities may include boron, boron fluoride, indium, or the like. An anneal may be performed after the implants to repair implant damage and to activate the p-type and/or n-type impurities. In some embodiments, in situ doping during epitaxial growth of the fins32and the nanostructures22,24may obviate separate implantations, although in situ and implantation doping may be used together.

InFIGS.4A-4C, dummy gate structures40are formed over the fins32and/or the nanostructures22,24, corresponding to act1200ofFIG.11. A dummy gate layer45is formed over the fins32and/or the nanostructures22,24. The dummy gate layer45may be made of materials that have a high etching selectivity versus the isolation regions36. The dummy gate layer45may be a conductive, semiconductive, or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer45may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. A mask layer47is formed over the dummy gate layer45, and may include, for example, silicon nitride, silicon oxynitride, or the like. In some embodiments, a gate dielectric layer (not illustrated for simplicity) is formed before the dummy gate layer45between the dummy gate layer45and the fins32and/or the nanostructures22,24.

A spacer layer41is formed over sidewalls of the mask layer47and the dummy gate layer45. The spacer layer41is made of an insulating material, such as silicon nitride, silicon oxide, silicon carbo-nitride, silicon oxynitride, silicon oxy carbo-nitride, or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers, in accordance with some embodiments. The spacer layer41may be formed by depositing a spacer material layer (not shown) over the mask layer47and the dummy gate layer45. Portions of the spacer material layer between dummy gate structures40are removed using an anisotropic etching process, in accordance with some embodiments.

FIGS.4A-4Cillustrate one process for forming the spacer layer41. In some embodiments, the spacer layer41is formed alternately or additionally after removal of the dummy gate layer45. In such embodiments, the dummy gate layer45is removed, leaving an opening, and the spacer layer41may be formed by conformally coating material of the spacer layer41along sidewalls of the opening. The conformally coated material may then be removed from the bottom of the opening corresponding to the top surface of the uppermost channel, e.g., the channel22A, prior to forming an active gate, such as any of the gate structures200A-200F.

InFIGS.5A-5C, an etching process is performed to etch the portions of protruding fins32and/or nanostructures22,24that are not covered by dummy gate structures40, resulting in the structure shown. The recessing may be anisotropic, such that the portions of fins32directly underlying dummy gate structures40and the spacer layer41are protected, and are not etched. The top surfaces of the recessed fins32may be substantially coplanar with the top surfaces of the isolation regions36as shown, in accordance with some embodiments. The top surfaces of the recessed fins32may be lower than the top surfaces of the isolation regions36, in accordance with some other embodiments.

FIGS.6A-6C and7A-7Cillustrate formation of inner spacers74corresponding to act1300ofFIG.11. A selective etching process is performed to recess end portions of the nanostructures24exposed by openings in the spacer layer41without substantially attacking the nanostructures22. After the selective etching process, recesses64are formed in the nanostructures24at locations where the removed end portions used to be. The resulting structure is shown inFIGS.6A-6C.

Next, an inner spacer layer is formed to fill the recesses64in the nanostructures22formed by the previous selective etching process. The inner spacer layer may be a suitable dielectric material, such as silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), or the like, formed by a suitable deposition method such as PVD, CVD, ALD, or the like. An etching process, such as an anisotropic etching process, is performed to remove portions of the inner spacer layers disposed outside the recesses in the nanostructures24. The remaining portions of the inner spacer layers (e.g., portions disposed inside the recesses64in the nanostructures24) form the inner spacers74. The resulting structure is shown inFIGS.7A-7C.

FIGS.8A-8Cillustrate formation of source/drain regions82corresponding to act1400ofFIG.11. In the illustrated embodiment, the source/drain regions82are epitaxially grown from epitaxial material(s). In some embodiments, the source/drain regions82exert stress in the respective channels22A-22C, thereby improving performance. The source/drain regions82are formed such that each dummy gate structure40is disposed between respective neighboring pairs of the source/drain regions82. In some embodiments, the spacer layer41separates the source/drain regions82from the dummy gate layer45by an appropriate lateral distance to prevent electrical bridging to subsequently formed gates of the resulting device.

The source/drain regions82may include any acceptable material, such as appropriate for n-type or p-type devices. For n-type devices, the source/drain regions82include materials exerting a tensile strain in the channel regions, such as silicon, SiC, SiCP, SiP, or the like, in some embodiments. When p-type devices are formed, the source/drain regions82include materials exerting a compressive strain in the channel regions, such as SiGe, SiGeB, Ge, GeSn, or the like, in accordance with certain embodiments. The source/drain regions82may have surfaces raised from respective surfaces of the fins and may have facets. Neighboring source/drain regions82may merge in some embodiments to form a singular source/drain region82adjacent two neighboring fins32.

The source/drain regions82may be implanted with dopants followed by an anneal. The source/drain regions may have an impurity concentration of between about 1019cm−3and about 1021cm−3. N-type and/or p-type impurities for source/drain regions82may be any of the impurities previously discussed. In some embodiments, the source/drain regions82are in situ doped during growth. A contact etch stop layer (CESL) and interlayer dielectric (ILD), not illustrated for simplicity, may then be formed covering the dummy gate structures40and the source/drain regions82.

FIG.9A,FIG.9B, andFIG.9Cillustrate release of fin channels22A-22C by removal of the nanostructures24A-24C, the mask layer47, and the dummy gate layer45, which corresponds to act1500ofFIG.11. A planarization process, such as a CMP, is performed to level the top surfaces of the dummy gate layer45and gate spacer layer41. The planarization process may also remove the mask layer47(seeFIG.8A) on the dummy gate layer45, and portions of the gate spacer layer41along sidewalls of the mask layer47. Accordingly, the top surfaces of the dummy gate layer45are exposed.

Next, the dummy gate layer45is removed in an etching process, so that recesses92are formed. In some embodiments, the dummy gate layer45is removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gate layer45without etching the spacer layer41. The dummy gate dielectric, when present, may be used as an etch stop layer when the dummy gate layer45is etched. The dummy gate dielectric may then be removed after the removal of the dummy gate layer45.

The nanostructures24are removed to release the nanostructures22. After the nanostructures24are removed, the nanostructures22form a plurality of nanosheets that extend horizontally (e.g., parallel to a major upper surface of the substrate110). The nanosheets may be collectively referred to as the channels22of the GAA devices20N,20P formed.

In some embodiments, the nanostructures24are removed by a selective etching process using an etchant that is selective to the material of the nanostructures24, such that the nanostructures24are removed without substantially attacking the nanostructures22. In some embodiments, the etching process is an isotropic etching process using an etching gas, and optionally, a carrier gas, where the etching gas comprises F2and HF, and the carrier gas may be an inert gas such as Ar, He, N2, combinations thereof, or the like.

In some embodiments, the nanostructures24are removed and the nanostructures22are patterned to form channel regions of both PFETs and NFETs, such as the GAA device20P and the GAA device20N, respectively. However, in some embodiments the nanostructures24may be removed and the nanostructures22may be patterned to form channel regions of the GAA device20N, and nanostructures22may be removed and the nanostructures24may be patterned to form channel regions of the GAA device20P. In some embodiments, the nanostructures22may be removed and the nanostructures24may be patterned to form channel regions of the GAA device20N, and the nanostructures24may be removed and the nanostructures22may be patterned to form channel regions of the GAA device20P. In some embodiments, the nanostructures22may be removed and the nanostructures24may be patterned to form channel regions of both PFETs and NFETs.

In some embodiments, the nanosheets22of the GAA devices20N,20P are reshaped (e.g. thinned) by a further etching process to improve gate fill window. The reshaping may be performed by an isotropic etching process selective to the nanosheets22. After reshaping, the nanosheets22may exhibit the dog bone shape in which middle portions of the nanosheets22are thinner than peripheral portions of the nanosheets22along the X direction.

Next, inFIGS.10A-10C, replacement gates200, such as the gate structures200A,200F, are formed, corresponding to act1600ofFIG.11. Each replacement gate200generally includes the first IL210, the gate dielectric layer220, the work function metal layers300, the protection layer structure270, and the gate fill layer290N or290P. In some embodiments, the replacement gate200further includes the second work function layer700. Cross-sections of formation of the gate structures200A,200F, as well as further gate structures200B,200C,200D, and200E are provided with respect toFIG.12AthroughFIG.19F. Flowcharts of methods of formation of the gate structures200A-200F are illustrated inFIG.20andFIG.21.

Additional processing may be performed to finish fabrication of the GAA device20N and/or the GAA device20P. For example, gate contacts (not illustrated for simplicity) and the source/drain contacts120may be formed to electrically couple to the gate structures200A-200F and the source/drain regions82, respectively, corresponding to act1700ofFIG.11. An interconnect structure may then be formed over the source/drain contacts120and the gate contacts corresponding to act1800ofFIG.11. The interconnect structure may include a plurality of dielectric layers surrounding metallic features, including conductive traces and conductive vias, which form electrical connection between devices on the substrate110, such as the GAA devices20N,20P, as well as to IC devices external to the IC device10.

FIG.12AthroughFIG.19Fillustrate formation of the gate structures200A-200F in accordance with various embodiments.FIGS.12A,13A,14A,15A,16A,17A,18A,19Aillustrate formation of an N-type ultra low threshold voltage (N-uLVT) gate structure, such as the gate structure200A.FIGS.12B,13B,14B,15B,16B,17B,18B,19Billustrate formation of an N-type low threshold voltage (N-LVT) gate structure, such as the gate structure200B.FIGS.12C,13C,14C,15C,16C,17C,18C,19Cillustrate formation of an N-type standard threshold voltage (N-SVT) gate structure, such as the gate structure200C.FIGS.12D,13D,14D,15D,16D,17D,18D,19Dillustrate formation of a P-type standard threshold voltage (P-SVT) gate structure, such as the gate structure200D.FIGS.12E,13E,14E,15E,16E,17E,18E,19Eillustrate formation of a P-type low threshold voltage (P-LVT) gate structure, such as the gate structure200E.FIGS.12F,13F,14F,15F,16F,17F,18F,19Fillustrate formation of a P-type ultra low threshold voltage (P-uLVT) gate structure, such as the gate structure200F.FIG.20illustrates a flowchart of a process2000for forming the gate structures200A-200F.

The gate structures200A-200F may be formed on the same wafer and/or may be parts of the same IC device in some embodiments. As such, at least some of the fabrication processes discussed below may be performed to all the gate structure200A-200F simultaneously. In FinFET embodiments, the gate structures200A-200F may also be each formed over fin structures, such that the gate structures200A-200F each wrap around a portion of the fin structures. In GAA FET embodiments, the gate structures200A-200F may wrap around channel regions of the fin structures. In some embodiments, the gate structures200A,200B,200C correspond to N-type ultra-low threshold voltage (N-uLVT), low threshold voltage (N-LVT), and standard threshold voltage (N-SVT) GAA devices20N, respectively. In some embodiments, the GAA device20N including the gate structure200A has lower threshold voltage than the GAA device20N including the gate structure200B, which has lower threshold voltage than the GAA device20N including the gate structure200C. In some embodiments, the gate structures200D,200E,200F correspond to P-type standard threshold voltage (P-SVT), low threshold voltage (P-LVT), and ultra-low threshold voltage (P-uLVT) GAA devices20P, respectively. In some embodiments, the GAA device20P including the gate structure200D has higher threshold voltage (magnitude) than the GAA device20P including the gate structure200E, which has higher threshold voltage than the GAA device20P including the gate structure200F.

FIGS.12A-12Fillustrate the gate structures200A-200F at an intermediate stage of fabrication, in which each gate structure200A-200F includes the first IL210formed over the channels22A-22C ofFIG.1A, corresponding to act2100ofFIG.20. In some embodiments, the channels22A-22C corresponding to the gate structures200A-200C are silicon, and the channels22A-22C corresponding to the gate structures200D-200F are silicon germanium. Only a fragmentary portion of the channel22A is illustrated as an example inFIGS.2A-19Ffor simplicity. In some embodiments, the first IL210includes an oxide of the semiconductor material of the substrate110, e.g. silicon oxide. In other embodiments, the first IL210may include another suitable type of dielectric material. The first IL210has a thickness215(measured in the Z-direction ofFIG.12A). In some embodiments, the thickness215is in a range between about 5 angstroms and about 50 angstroms. In some embodiments, the thickness215is about 10 angstroms.

Still referring toFIGS.12A-12F, the gate dielectric layer220is formed over the first IL210, corresponding to act2200ofFIG.20. In some embodiments, an atomic layer deposition (ALD) process is used to form the gate dielectric layer220to control thickness of the deposited gate dielectric layer220with precision. In some embodiments, the ALD process is performed using between about 20 and 40 deposition cycles, at a temperature range between about 200 degrees Celsius and about 300 degrees Celsius. In some embodiments, the ALD process uses HfCl4 and/or H2O as precursors. Such an ALD process may form the gate dielectric layer220to have a thickness225, which may be in a range between about 5 angstroms and about 100 angstroms. In some embodiments, the thickness225is about 15 angstroms.

In some embodiments, and as described above with respect toFIG.1A, the gate dielectric layer220includes a high-k dielectric material, which may refer to dielectric materials having a high dielectric constant that is greater than a dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In other embodiments, the gate dielectric layer220may include a non-high-k dielectric material such as silicon oxide. In some embodiments, the gate dielectric layer220includes a first high-k dielectric material layer, such as HfO2with dipole doping (La, Mg), and a second higher-k dielectric material layer, such as ZrO with crystallization.

Referring now toFIGS.13A-13F, the barrier layers700are formed on the gate structures200A-200F, in accordance with some embodiments, which corresponds to act2300ofFIG.20. In some embodiments, the gate structures200A,200D are free from the barrier layers700, as shown inFIG.13AandFIG.13D. In some embodiments, the barrier layers700include a composition of at least two of the elements including Ti, Ta, W, Mo, O, C, N, Si. In some embodiments, the barrier layers700are or comprise a metal compound, such as TiN, TaN, WN, MoN, WCN, TiSiN, or the like. In a specific embodiment, the barrier layers700are TiN. The barrier layers700may have thickness715,725ranging from about 5 A to about 20 A. Inclusion of the barrier layers700provides additional threshold voltage tuning flexibility. In general, the barrier layers700increase the threshold voltage for NFET transistor devices, and decrease the threshold voltage (magnitude) for PFET transistor devices.

As shown inFIGS.13A-13F, the barrier layers700may include at least a first barrier layer701and a second barrier layer702. In some embodiments, a first deposition process is performed to form the first barrier layer701over the gate dielectric layer220. Following the first deposition process, the first barrier layer701may be removed from the gate structures200A,200B,200D,200E by etching the first barrier layer701in the presence of a first mask covering the gate structures200C,200F. Etching of the first barrier layer701may be an atomic layer etch (ALE) with artificial intelligence (AI) control. The ALE is performed in cycles to remove the first barrier layer701while substantially not removing the gate dielectric layer220. Each cycle may include a first pulse of WCl5(or TaCl5), followed by an Ar purge, followed by a second pulse of O2, followed by another Ar purge. The AI control is discussed in greater detail with respect toFIG.21. Use of AI-controlled ALE prevents damage to the high-k material of the gate dielectric layer220.

After formation of the first barrier layer701, a second deposition may be performed to form the second barrier layer702over the first barrier layer701and/or the gate electrode220. Following the second deposition process, the second barrier layer702may be removed from the gate structures200A,200D by etching the second barrier layer702in the presence of a second mask covering the gate structures200B,200C,200E,200F. The etching of the second barrier layer702may also be an AI-controlled ALE similar to that described for removing the first barrier layer701. In some embodiments, the first barrier layer701has the thickness715, and the second barrier layer702has the thickness725. In some embodiments, the thickness715is substantially equal to the thickness725. In some embodiments, the thickness715is different from the thickness725. In some embodiments, material of the first barrier layer701is different from material of the second barrier layer702. In some embodiments, the material of the first barrier layer701is the same as the material of the second barrier layer702.

FIGS.14A-14Fillustrate formation of the first work function metal layer250and the capping layer260(corresponding to act2400), which may be collectively referred to as the work function metal layers300. In some embodiments, the first work function metal layer250is or comprises an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, or the like. The first work function metal layer250may be formed by one or more deposition methods, such as CVD, PVD, ALD, plating, and/or other suitable methods, and has a thickness255of between about 10 A and 20 A. The first work function metal layer250may be formed directly on the gate dielectric layer220(gate structures200A,200D), or directly on the second barrier layer702(gate structures200B,200C,200E,200F). The capping layer260is formed on the first work function metal layer250. In some embodiments, the capping layer260is or comprises TiN, TiSiN, TaN, WN, MoN, WCN, or another suitable material, and has a thickness265between about 10 A and 20 A.

FIGS.15A-15Fillustrate formation of the first protection layer271on the capping layer260, corresponding to act2500. The first protection layer271is an oxygen blocking layer formed on the capping layer260to prevent oxygen diffusion into the first work function metal layer250, which would cause an undesirable shift in the threshold voltage. The first protection layer271is formed of a dielectric material that can stop oxygen from penetrating to the first work function metal layer250, and may protect the first work function metal layer250from further oxidation. The first protection layer271may include an oxide of silicon, germanium, SiGe, Al, Ti, Hf, or another suitable material. In some embodiments, the first protection layer271is formed using ALD and has a thickness (in the Z-direction) between about 10 A and about 20 A. In some embodiments, the first protection layer271is formed as an in-situ silane passivation on the capping layer260.

FIGS.16A-16Fillustrate formation of the second protection layer272on the first protection layer271, corresponding to act2600. The second protection layer272is a further oxygen blocking layer formed on the first protection layer271to prevent oxygen diffusion into the first work function metal layer250, which would cause an undesirable shift in the threshold voltage. The second protection layer272is formed of a dielectric material that can stop oxygen from penetrating to the first work function metal layer250, and may protect the first work function metal layer250from further oxidation. The second protection layer272may include a metal or a conductive metal oxide, such as Al, Ti, Hf, RuO2, IrO2, or another suitable material. In some embodiments, the second protection layer272is formed using ALD and has a thickness (in the Z-direction) between about 10 A and about 20 A. In some embodiments, the second protection layer272is removed from the gate structures200C,200F having both the first and second barrier layers701,702. In the gate structures200C,200F, the first work function metal layer250is separated from the channel22A by the first and second barrier layers701,702, which reduces the effect of oxidation of the first work function metal layer250on the threshold voltage shift. As such, the gate structures200C,200F may be formed free of the second protection layer272to increase gate fill window.

FIGS.17A-17Fillustrate optional formation of the third protection layer273on the second protection layer272, corresponding to act2700.FIGS.17A-17Ffurther illustrate formation of the glue layer270and the metal fill layers290N,290P, corresponding to act2800and act2900. The third protection layer273is a further oxygen blocking layer formed on the second protection layer272to prevent oxygen diffusion into the first work function metal layer250, which would cause an undesirable shift in the threshold voltage. The third protection layer273is formed of a dielectric material that can stop oxygen from penetrating to the first work function metal layer250, and may protect the first work function metal layer250from further oxidation. The third protection layer273may include a metal or a conductive metal oxide, such as Al, Ti, Hf, RuO2, IrO2, or another suitable material. In some embodiments, the third protection layer273is formed using ALD and has a thickness (in the Z-direction) between about 10 A and about 20 A. In some embodiments, the third protection layer272is removed from the gate structures200C,200F having both the first and second barrier layers701,702, and is further removed from the gate structures200B,200E having the second barrier layer702. In the gate structures200C,200F, the first work function metal layer250is separated from the channel22A by the first and second barrier layers701,702, which reduces the effect of oxidation of the first work function metal layer250on the threshold voltage shift. As such, the gate structures200C,200F may be formed free of the third protection layer273to increase gate fill window. Similarly, while the first work function metal layer250is closer to the channel22A in the gate structures200D,200E than in the gate structures200C,200F, in some embodiments, presence of the two protection layers271,272may be sufficient to mitigate oxidation of the first work function metal layer250. As such, the gate structures200D,200E may also be formed free of the third protection layer273to increase gate fill window.

The metal fill layers290N,290P are formed on the glue layer280, and may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. In some embodiments, the metal fill layers290N,290P may be deposited using methods such as CVD, PVD, plating, and/or other suitable processes. As shown inFIGS.17A-17F, the metal fill layers290N,290P may have thickness295. The thickness295may vary across the gate structures200A-200F, due to presence or absence of either the barrier layers700or the protection layers270. In embodiments in which each protection layer271,272,273is thinner than each barrier layer701,702, the gate structures200C,200F may have the smallest fill window, corresponding to the lowest thickness295of the metal fill layers290N,290P, whereas the gate structures200A,200D may have the largest fill window, corresponding to the greatest thickness295.

FIGS.18A-18Fillustrate the gate structures200A-200F in a configuration including only the first and second protection layers271,272. As shown, the gate structures200A,200D may include the first and second protection layers271,272, and the gate structures200B,200C,200E,200F may include the first protection layer271while being substantially free of the second protection layer272. The configuration ofFIGS.18A-18Fimproves gate fill window by including the additional second protection layer272only in the gate structures200A,200D corresponding to the N-uLVT GAA devices20N and the P-SVT GAA devices20P.

FIGS.19A-19Fillustrate the gate structures200A-200F in a configuration including the first, second and third protection layers271,272,273in the gate structures200A,200D, but not including the second or third protection layers272,273in the gate structures200B,200C,200E,200F. As such, the N-uLVT GAA devices20N and the P-SVT GAA devices20P benefit from an enhanced oxidation prevention effect due to the three protection layers271,272,273, while the other GAA devices20N,20P employing the gate structures200B,200C,200E,200F enjoy improved gate fill window due to absence of the second and third protection layers272,273.

FIG.21is an illustration of a semiconductor process system3200, according to one embodiment. The semiconductor process system3200can be utilized to perform the controlled ALE processes used to form the GAA devices20N,20C,20D as described in relation toFIGS.1A-20. The semiconductor process system3200includes a process chamber3202including an interior volume3203. A support3206is positioned within the interior volume3203and is configured to support a substrate3204during a thin-film etching process. The semiconductor process system3200is configured to etch a thin film on the substrate3204, such as the high-k capping layer used to form the second IL240or the work function barrier layer700. The semiconductor process system3200includes a control system3224that dynamically adjusts thin-film etching parameters. Details of the control system3224are provided after description of the operation of the semiconductor process system3200.

In one embodiment, the semiconductor process system3200includes a first fluid source3208and a second fluid source3210. The first fluid source3208supplies a first fluid into the interior volume3203. The second fluid source3210supplies a second fluid into the interior volume3203. The first and second fluids both contribute in etching a thin film on the substrate3204. WhileFIG.21illustrates fluid sources3208and3210, in practice, the fluid sources3208and3210may include or supply materials other than fluids. For example, the fluid sources3208and3210may include material sources that provide all materials for the etching process.

In one embodiment, the semiconductor process system3200is an atomic layer etching (ALE) system that performs ALE processes. The ALE system performs etching processes in cycles. Each cycle includes flowing a first etching fluid from the fluid source3208, followed by purging the first etching fluid from the etching chamber by flowing the purge gas from one or both of the purge sources3212and3224, followed by flowing a second etching fluid from the fluid source3210, followed by purging the second etching fluid from the etching chamber by flowing the purge gas from one or both of the purge sources3212and3224. This corresponds to a single ALE cycle. Each cycle etches an atomic or molecular layer from the thin-film that is being etched. A specific example of the ALE cycle is illustrated inFIG.22.

The parameters of a thin film generated by the semiconductor process system3200can be affected by a large number of process conditions. The process conditions can include, but are not limited to, an amount of fluid or material remaining in the fluid sources3208,3210, a flow rate of fluid or material from the fluid sources3208,3210, the pressure of fluids provided by the fluid sources3208and3210, the length of tubes or conduits that carry fluid or material into the process chamber3202, the age of an ampoule defining or included in the process chamber3202, the temperature within the process chamber3202, the humidity within the process chamber3202, the pressure within the process chamber3202, light absorption and reflection within the process chamber3202, surface features of the semiconductor wafer3204, the composition of materials provided by the fluid sources3208and3210, the phase of materials provided by the fluid sources3208and3210, the duration of the etching process, the duration of individual phases of the etching process, and various other factors.

The combination of the various process conditions during the etching process determines the remaining thickness of a thin film etched by the ALE process. It is possible that process conditions may result in thin films that do not have remaining thicknesses that fall within target parameters. If this happens, then integrated circuits formed from the semiconductor wafer3204may not function properly. The quality of batches of semiconductor wafers may suffer. In some cases, some semiconductor wafers may need to be scrapped.

The semiconductor process system3200utilizes the control system3224to dynamically adjust process conditions to ensure that etching processes result in thin films having parameters or characteristics that fall within target parameters or characteristics. The control system3224is connected to processing equipment associated with the semiconductor process system3200. The processing equipment can include components shown inFIG.2A. The control system3224can control the flow rate of material from the fluid sources3208and3210, the temperature of materials supplied by the fluid sources3208and3210, the pressure of fluids provided by the fluid sources3208and3210, the flow rate of material from purge sources3212and3214, the duration of flow of materials from the fluid sources3208and3210and the purge sources3212of3214, the temperature within the process chamber3202, the pressure within the process chamber3202, the humidity within the process chamber3202, and other aspects of the thin-film etching process. The control system3224controls these process parameters so that the thin-film etching process results in a thin-film having target parameters such as a target remaining thickness, a target composition, a target crystal orientation, etc. Further details regarding the control system are provided in relation toFIGS.23-24.

In one embodiment, the control system224is communicatively coupled to the first and second fluid sources3208,3210via one or more communication channels3225. The control system3224can send signals to the first fluid source3208and the second fluid source3210via the communication channels3225. The control system3224can control functionality of the first and second fluid sources3208,3210responsive, in part, to the sensor signals from a byproduct sensor3222.

In one embodiment, the semiconductor process system3200can include one or more valves, pumps, or other flow control mechanisms for controlling the flow rate of the first fluid from the first fluid source3208. These flow control mechanisms may be part of the fluid source3208or may be separate from the fluid source3208. The control system3224can be communicatively coupled to these flow control mechanisms or to systems that control these flow control mechanisms. The control system3224can control the flowrate of the first fluid by controlling these mechanisms. The control system3200may include valves, pumps, or other flow control mechanisms that control the flow of the second fluid from the second fluid source3210in the same manner as described above in reference to the first fluid and the first fluid source3208.

In one embodiment, the semiconductor process system3200includes a manifold mixer3216and a fluid distributor3218. The manifold mixer3216receives the first and second fluids, either together or separately, from the first fluid source3208and the second fluid source3210. The manifold mixer3216provides either the first fluid, the second fluid, or a mixture of the first and second fluids to the fluid distributor3218. The fluid distributor3218receives one or more fluids from the manifold mixer3216and distributes the one or more fluids into the interior volume3203of the process chamber3202.

In one embodiment, the first fluid source3208is coupled to the manifold mixer3216by a first fluid channel3230. The first fluid channel3230carries the first fluid from the fluid source3208to the manifold mixer3216. The first fluid channel3230can be a tube, pipe, or other suitable channel for passing the first fluid from the first fluid source3208to the manifold mixer3216. The second fluid source3210is coupled to the manifold mixer3216by second fluid channel3232. The second fluid channel3232carries the second fluid from the second fluid source3210to the manifold mixer3216.

In one embodiment, the manifold mixer3216is coupled to the fluid distributor3218by a third fluid line3234. The third fluid line3234carries fluid from the manifold mixer3216to the fluid distributor3218. The third fluid line3234may carry the first fluid, the second fluid, a mixture of the first and second fluids, or other fluids, as will be described in more detail below.

The first and second fluid sources3208,3210can include fluid tanks. The fluid tanks can store the first and second fluids. The fluid tanks can selectively output the first and second fluids.

In one embodiment, the semiconductor process system3200includes a first purge source3212and the second purge source3214. The first purge source is coupled to the first fluid line3230by first purge line3236. The second purge source is coupled to the fluid line3232by second purge line3238. In practice, the first and second purge sources may be a single purge source.

In one embodiment, the first and second purge sources3212,3214supply a purging gas into the interior volume3203of the process chamber3202. The purge fluid is a fluid selected to purge or carry the first fluid, the second fluid, byproducts of the first or second fluid, or other fluids from the interior volume3203of the process chamber3202. The purge fluid is selected to not react with the substrate3204, the gate metal layer on the substrate3204, the first and second fluids, and byproducts of this first or second fluid. Accordingly, the purge fluid may be an inert gas including, but not limited to, Ar or N2.

WhileFIG.21illustrates a first fluid source3208and a second fluid source3210, in practice the semiconductor process system3200can include other numbers of fluid sources. For example, the semiconductor process system3200may include only a single fluid source or more than two fluid sources. Accordingly, the semiconductor process system3200can include a different number than two fluid sources without departing from the scope of the present disclosure.

FIG.22is a graph illustrating a cycle of an ALE process performed by the semiconductor process system3200, according to one embodiment. At time T1the first etching fluid begins to flow. In the example ofFIG.22, the first etching fluid is WCI5. The first etching fluid flows from the fluid source3208into the interior volume3203. In the interior volume3203, the first etching fluid reacts with the top exposed layer of the high-k capping layer (e.g., TiSiN) or the work function barrier layer700(e.g., TiN). At time T2, the first etching fluid WCI5stops flowing. In one example, the time elapsed between T1and T2is between 1 s and 10 s.

At time T3, the purge gas begins to flow. The purge gas flows from one or both of the purge sources3212and3224. In one example, the purge gas is one of argon, N2, or another inert gas that can purge the first etching fluid WCI5without reacting with the high-k capping layer (e.g., TiSiN) or the work function barrier layer700(e.g., TiN). At time T4, the purge gas stops flowing. In one example, the time elapsed between T3and T4is between 2 s and 15 s.

At time T5, the second etching fluid flows into the interior volume3203. The second etching fluid flows from the fluid source3210into the interior volume3203. In one example, the second etching fluid is O2. The O2 reacts with the top atomic or molecular layer of the titanium nitride layer124and completes the etching of the top atomic or molecular layer of the titanium nitride layer124. At time T6, the second etching fluid stops flowing. In one example, the elapsed time between T5and T6is between 1 s and 10 s.

At time T7, the purge gas flows again and purges the interior volume3203of the second etching fluid. At time T8the purge gas stops flowing. The time between T1and T8corresponds to a single ALE cycle.

In practice, an ALE process may include between 5 and 50 cycles, depending on the initial thickness of the high-k capping layer (e.g., TiSiN) or the work function barrier layer700(e.g., TiN) and the desired final thickness of the high-k capping layer (e.g., TiSiN) or the work function barrier layer700(e.g., TiN). Each cycle removes an atomic or molecular layer of the high-k capping layer (e.g., TiSiN) or the work function barrier layer700(e.g., TiN). Other materials, processes, and elapsed times can be utilized without departing from the scope of the present disclosure.

FIG.23is a block diagram of the control system3224ofFIG.21, according to one embodiment. The control system3224ofFIG.23is configured to control operation of the semiconductor process system3200in performing ALE processes to form the GAA devices20N,20C,20D ofFIGS.1A-1C, according to one embodiment. The control system3224utilizes machine learning to adjust parameters of the semiconductor process system3200. The control system3224can adjust parameters of the semiconductor process system3200between ALE runs or even between ALE cycles in order to ensure that a thin-film layer formed by the ALE process falls within selected specifications.

In one embodiment, the control system3224includes an analysis model3302and a training module3304. The training module3304trains the analysis model3302with a machine learning process. The machine learning process trains the analysis model3302to select parameters for an ALE process that will result in a thin film having selected characteristics. Although the training module3304is shown as being separate from the analysis model3302, in practice, the training module3304may be part of the analysis model3302.

The control system3224includes, or stores, training set data3306. The training set data3306includes historical thin-film data3308and historical process conditions data3310. The historical thin-film data3308includes data related to thin films resulting from ALE processes. The historical process conditions data3310includes data related to process conditions during the ALE processes that generated the thin films. As will be set forth in more detail below, the training module3304utilizes the historical thin-film data3308and the historical process conditions data3310to train the analysis model3302with a machine learning process.

In one embodiment, the historical thin-film data3308includes data related to the remaining thickness of previously etched thin films. For example, during operation of a semiconductor fabrication facility, thousands or millions of semiconductor wafers may be processed over the course of several months or years. Each of the semiconductor wafers may include thin films etched by ALE processes. After each ALE process, the thicknesses of the thin-films are measured as part of a quality control process. The historical thin-film data3308includes the remaining thicknesses of each of the thin films etched by ALE processes. Accordingly, the historical thin-film data3308can include thickness data for a large number of thin-films etched by ALE processes.

In one embodiment, the historical thin-film data3308may also include data related to the thickness of thin films at intermediate stages of the thin-film etching processes. For example, an ALE process may include a large number of etching cycles during which individual layers of the thin film are etched. The historical thin-film data3308can include thickness data for thin films after individual etching cycles or groups of etching cycles. Thus, the historical thin-film data3308not only includes data related to the total thickness of a thin film after completion of an ALE process, but may also include data related to the thickness of the thin film at various stages of the ALE process.

In one embodiment, the historical thin-film data3308includes data related to the composition of the remaining thin films etched by ALE processes. After a thin film is etched, measurements can be made to determine the elemental or molecular composition of the thin films. Successful etching of the thin films results in a thin film that includes particular remaining thicknesses. Unsuccessful etching processes may result in a thin film that does not include the specified proportions of elements or compounds. The historical thin-film data3308can include data from measurements indicating the elements or compounds that make up the various thin films.

In one embodiment, the historical process conditions3310include various process conditions or parameters during ALE processes that etch the thin films associated with the historical thin-film data3308. Accordingly, for each thin film having data in the historical thin-film data3308, the historical process conditions data3310can include the process conditions or parameters that were present during etching of the thin film. For example, the historical process conditions data3310can include data related to the pressure, temperature, and fluid flow rates within the process chamber during ALE processes.

The historical process conditions data3310can include data related to remaining amounts of precursor material in the fluid sources during ALE processes. The historical process conditions data3310can include data related to the age of the process chamber3202, the number of etching processes that have been performed in the process chamber3202, a number of etching processes that have been performed in the process chamber3202since the most recent cleaning cycle of the process chamber3202, or other data related to the process chamber3202. The historical process conditions data3310can include data related to compounds or fluids introduced into the process chamber3202during the etching process. The data related to the compounds can include types of compounds, phases of compounds (solid, gas, or liquid), mixtures of compounds, or other aspects related to compounds or fluids introduced into the process chamber3202. The historical process conditions data3310can include data related to the humidity within the process chamber3202during ALE processes. The historical process conditions data3310can include data related to light absorption, light adsorption, and light reflection related to the process chamber3202. The historical process conditions data3326can include data related to the length of pipes, tubes, or conduits that carry compounds or fluids into the process chamber3202during ALE processes. The historical process conditions data3310can include data related to the condition of carrier gases that carry compounds or fluids into the process chamber3202during ALE processes.

In one embodiment, historical process conditions data3310can include process conditions for each of a plurality of individual cycles of a single ALE process. Accordingly, the historical process conditions data3310can include process conditions data for a very large number of ALE cycles.

In one embodiment, the training set data3306links the historical thin-film data3308with the historical process conditions data3310. In other words, the thin-film thickness, material composition, or crystal structure associated with a thin film in the historical thin-film data3308is linked (e.g., by labeling) to the process conditions data associated with that etching process. As will be set forth in more detail below, the labeled training set data can be utilized in a machine learning process to train the analysis model3302to predict semiconductor process conditions that will result in properly formed thin films.

In one embodiment, the control system3324includes processing resources3312, memory resources3314, and communication resources3316. The processing resources3312can include one or more controllers or processors. The processing resources3312are configured to execute software instructions, process data, make thin-film etching control decisions, perform signal processing, read data from memory, write data to memory, and to perform other processing operations. The processing resources3312can include physical processing resources3312located at a site or facility of the semiconductor process system3200. The processing resources can include virtual processing resources3312remote from the site semiconductor process system3200or a facility at which the semiconductor process system3200is located. The processing resources3312can include cloud-based processing resources including processors and servers accessed via one or more cloud computing platforms.

In one embodiment, the memory resources3314can include one or more computer readable memories. The memory resources3314are configured to store software instructions associated with the function of the control system and its components, including, but not limited to, the analysis model3302. The memory resources3314can store data associated with the function of the control system3224and its components. The data can include the training set data3306, current process conditions data, and any other data associated with the operation of the control system3224or any of its components. The memory resources3314can include physical memory resources located at the site or facility of the semiconductor process system3200. The memory resources can include virtual memory resources located remotely from site or facility of the semiconductor process system3200. The memory resources3314can include cloud-based memory resources accessed via one or more cloud computing platforms.

In one embodiment, the communication resources can include resources that enable the control system3224to communicate with equipment associated with the semiconductor process system3200. For example, the communication resources3316can include wired and wireless communication resources that enable the control system3224to receive the sensor data associated with the semiconductor process system3200and to control equipment of the semiconductor process system3200. The communication resources3316can enable the control system3224to control the flow of fluids or other material from the fluid sources3308and3310and from the purge sources3312and3314. The communication resources3316can enable the control system3224to control heaters, voltage sources, valves, exhaust channels, wafer transfer equipment, and any other equipment associated with the semiconductor process system3200. The communication resources3316can enable the control system3224to communicate with remote systems. The communication resources3316can include, or can facilitate communication via, one or more networks such as wire networks, wireless networks, the Internet, or an intranet. The communication resources3316can enable components of the control system3224to communicate with each other.

In one embodiment, the analysis model3302is implemented via the processing resources3312, the memory resources3314, and the communication resources3316. The control system3224can be a dispersed control system with components and resources and locations remote from each other and from the semiconductor process system3200.

FIG.24is a block diagram illustrating operational aspects and training aspects of the analysis model3302ofFIG.23, according to one embodiment. The analysis model3302can be used to select parameters for ALE processes performed by the semiconductor process system3200ofFIG.21to form the GAA devices20N,20C,20D ofFIGS.1A-1C. As described previously, the training set data3306includes data related to a plurality of previously performed thin-film etching processes. Each previously performed thin-film etching process took place with particular process conditions and resulted in a thin-film having a particular characteristics. The process conditions for each previously performed thin-film etching process are formatted into a respective process conditions vector3352. The process conditions vector includes a plurality of data fields3354. Each data field3354corresponds to a particular process condition.

The example ofFIG.24illustrates a single process conditions vector3352that will be passed to the analysis model3302during the training process. In the example ofFIG.24, the process conditions vector3352includes nine data fields3354. A first data field3354corresponds to the temperature during the previously performed thin-film etching process. A second data field3356corresponds to the pressure during the previously performed thin-film etching process. A third data field3354corresponds to the humidity during the previously performed thin-film etching process. The fourth data field3354corresponds to the flow rate of etching materials during the previously performed thin-film etching process. The fifth data field3354corresponds to the phase (liquid, solid, or gas) of etching materials during the previously performed thin-film etching process. The sixth data field3354corresponds to the age of the ampoule used in the previously performed thin-film etching process. The seventh data field3354corresponds to a size of an etching area on a wafer during the previously performed thin-film etching process. The eighth data field3354corresponds to the density of surface features of the wafer utilized during the previously performed thin-film etching process. The ninth data field corresponds to the angle of sidewalls of surface features during the previously performed thin-film etching process. In practice, each process conditions vector3352can include more or fewer data fields than are shown inFIG.24without departing from the scope of the present disclosure. Each process conditions vector3352can include different types of process conditions without departing from the scope of the present disclosure. The particular process conditions illustrated inFIG.24are given only by way of example. Each process condition is represented by a numerical value in the corresponding data field3354. For condition types that are not naturally represented in numbers, such as material phase, a number can be assigned to each possible phase.

The analysis model3302includes a plurality of neural layers3356a-e. Each neural layer includes a plurality of nodes3358. Each node3358can also be called a neuron. Each node3358from the first neural layer3356areceives the data values for each data field from the process conditions vector3352. Accordingly, in the example ofFIG.24, each node3358from the first neural layer3356areceives nine data values because the process conditions vector3352has nine data fields. Each neuron3358includes a respective internal mathematical function labeled F(x) inFIG.24. Each node3358of the first neural layer3356agenerates a scalar value by applying the internal mathematical function F(x) to the data values from the data fields3354of the process conditions vector3352. Further details regarding the internal mathematical functions F(x) are provided below.

Each node3358of the second neural layer3356breceives the scalar values generated by each node3358of the first neural layer3356a. Accordingly, in the example ofFIG.24each node of the second neural layer3356breceives four scalar values because there are four nodes3358in the first neural layer3356a. Each node3358of the second neural layer3356bgenerates a scalar value by applying the respective internal mathematical function F(x) to the scalar values from the first neural layer3356a.

Each node3358of the third neural layer3356creceives the scalar values generated by each node3358of the second neural layer3356b. Accordingly, in the example ofFIG.24each node of the third neural layer3356creceives five scalar values because there are five nodes3358in the second neural layer3356b. Each node3358of the third neural layer3356cgenerates a scalar value by applying the respective internal mathematical function F(x) to the scalar values from the nodes3358of the second neural layer3356b.

Each node3358of the neural layer3356dreceives the scalar values generated by each node3358of the previous neural layer (not shown). Each node3358of the neural layer3356dgenerates a scalar value by applying the respective internal mathematical function F(x) to the scalar values from the nodes3358of the second neural layer3356b.

The final neural layer includes only a single node3358. The final neural layer receives the scalar values generated by each node3358of the previous neural layer3356d. The node3358of the final neural layer3356egenerates a data value3368by applying a mathematical function F(x) to the scalar values received from the nodes3358of the neural layer3356d.

In the example ofFIG.24, the data value3368corresponds to the predicted remaining thickness of a thin film generated by process conditions data corresponding to values included in the process conditions vector3352. In other embodiments, the final neural layer3356emay generate multiple data values each corresponding to a particular thin-film characteristic such as thin-film crystal orientation, thin-film uniformity, or other characteristics of a thin film. The final neural layer3356ewill include a respective node3358for each output data value to be generated. In the case of a predicted thin film thickness, engineers can provide constraints that specify that the predicted thin film thickness3368must fall within a selected range, such as between 0 nm and 50 nm, in one example. The analysis model3302will adjust internal functions F(x) to ensure that the data value3368corresponding to the predicted thin film thickness will fall within the specified range.

During the machine learning process, the analysis model compares the predicted remaining thickness in the data value3368to the actual remaining thickness of the thin-film as indicated by the data value3370. As set forth previously, the training set data3306includes, for each set of historical process conditions data, thin-film characteristics data indicating the characteristics of the thin-film that resulted from the historical thin-film etching process. Accordingly, the data field3370includes the actual remaining thickness of the thin-film that resulted from the etching process reflected in the process conditions vector3352. The analysis model3302compares the predicted remaining thickness from the data value3368to the actual remaining thickness from the data value3370. The analysis model3302generates an error value3372indicating the error or difference between the predicted remaining thickness from the data value3368and the actual remaining thickness from the data value3370. The error value3372is utilized to train the analysis model3302.

The training of the analysis model3302can be more fully understood by discussing the internal mathematical functions F(x). While all of the nodes3358are labeled with an internal mathematical function F(x), the mathematical function F(x) of each node is unique. In one example, each internal mathematical function has the following form:
F(x)=x1*w1+x2*w2+ . . .xn*w1+b.

In the equation above, each value x1-xn corresponds to a data value received from a node3358in the previous neural layer, or, in the case of the first neural layer3356a, each value x1-xn corresponds to a respective data value from the data fields3354of the process conditions vector3352. Accordingly, n for a given node is equal to the number of nodes in the previous neural layer. The values w1-wn are scalar weighting values associated with a corresponding node from the previous layer. The analysis model3302selects the values of the weighting values w1-wn. The constant b is a scalar biasing value and may also be multiplied by a weighting value. The value generated by a node3358is based on the weighting values w1-wn. Accordingly, each node3358has n weighting values w1-wn. Though not shown above, each function F(x) may also include an activation function. The sum set forth in the equation above is multiplied by the activation function. Examples of activation functions can include rectified linear unit (ReLU) functions, sigmoid functions, hyperbolic tension functions, or other types of activation functions.

After the error value3372has been calculated, the analysis model3302adjusts the weighting values w1-wn for the various nodes3358of the various neural layers3356a-3356e. After the analysis model3302adjusts the weighting values w1-wn, the analysis model3302again provides the process conditions vector3352to the input neural layer3356a. Because the weighting values are different for the various nodes3358of the analysis model3302, the predicted remaining thickness3368will be different than in the previous iteration. The analysis model3302again generates an error value3372by comparing the actual remaining thickness3370to the predicted remaining thickness3368.

The analysis model3302again adjusts the weighting values w1-wn associated with the various nodes3358. The analysis model3302again processes the process conditions vector3352and generates a predicted remaining thickness3368and associated error value3372. The training process includes adjusting the weighting values w1-wn in iterations until the error value3372is minimized.

FIG.24illustrates a single process conditions vector3352being passed to the analysis model3302. In practice, the training process includes passing a large number of process conditions vectors3352through the analysis model3302, generating a predicted remaining thickness3368for each process conditions vector3352, and generating associated error value3372for each predicted remaining thickness. The training process can also include generating an aggregated error value indicating the average error for all the predicted remaining thicknesses for a batch of process conditions vectors3352. The analysis model3302adjusts the weighting values w1-wn after processing each batch of process conditions vectors3352. The training process continues until the average error across all process conditions vectors3352is less than a selected threshold tolerance. When the average error is less than the selected threshold tolerance, the analysis model3302training is complete and the analysis model is trained to accurately predict the thickness of thin films based on the process conditions. The analysis model3302can then be used to predict thin-film thicknesses and to select process conditions that will result in a desired thin-film thickness. During use of the trained model3302, a process conditions vector, representing current process condition for a current thin film etching process to be performed, and having the same format at the process conditions vector3352, is provided to the trained analysis model3302. The trained analysis model3302can then predict the thickness of a thin film that will result from those process conditions.

A particular example of a neural network based analysis model3302has been described in relation toFIG.24. However, other types of neural network based analysis models, or analysis models of types other than neural networks can be utilized without departing from the scope of the present disclosure. Furthermore, the neural network can have different numbers of neural layers having different numbers of nodes without departing from the scope of the present disclosure.

FIG.25is a flow diagram of a process3400for training an analysis model to identify process conditions that will result in proper etching of a thin film, according to one embodiment. One example of an analysis model is the analysis model3302ofFIG.23. The various steps of the process3400can utilize components, processes, and techniques described in relation toFIGS.21-24. Accordingly,FIG.25is described with reference toFIGS.21-24.

At3402, the process3400gathers training set data including historical thin-film data and historical process conditions data. This can be accomplished by using a data mining system or process. The data mining system or process can gather training set data by accessing one or more databases associated with the semiconductor process system3200and collecting and organizing various types of data contained in the one or more databases. The data mining system or process, or another system or process, can process and format the collected data in order to generate a training set data. The training set data3306can include historical thin-film data3308and historical process conditions data3310as described in relation toFIG.23.

At3404, the process3400inputs historical process conditions data to the analysis model. In one example, this can include inputting historical process conditions data3310into the analysis model3302with the training module3304as described in relation toFIG.23. The historical process conditions data can be provided in consecutive discrete sets to the analysis model3302. Each district set can correspond to a single thin-film etching process or a portion of a single thin-film etching process. The historical process conditions data can be provided as vectors to the analysis model3302. Each set can include one or more vectors formatted for reception processing by the analysis model3302. The historical process conditions data can be provided to the analysis model3302in other formats without departing from the scope of the present disclosure.

At3406, the process3400generates predicted thin-film data based on historical process conditions data. In particular, the analysis model3302generates, for each set of historical thin-film conditions data3310, predicted thin-film data. The predicted thin-film data corresponds to a prediction of characteristics, such as the remaining thickness, of a thin film that would result from that particular set of process conditions. The predicted thin-film data can include thickness, uniformity, composition, crystal structure, or other aspects of a remaining thin film.

At3408, the predicted thin-film data is compared to the historical thin-film data3308. In particular, the predicted thin-film data for each set of historical process conditions data is compared to the historical thin-film data3308associated with that set of historical process conditions data. The comparison can result in an error function indicating how closely the predicted thin-film data matches the historical thin-film data3308. This comparison is performed for each set of predicted thin-film data. In one embodiment, this process can include generating an aggregated error function or indication indicating how the totality of the predicted thin-film data compares to the historical thin-film data3308. These comparisons can be performed by the training module3304or by the analysis model3302. The comparisons can include other types of functions or data than those described above without departing from the scope of the present disclosure.

At3410, the process3400determines whether the predicted thin-film data matches the historical thin-film data based on the comparisons generated at step3408. For example, the process determines whether the predicted remaining thickness matches the actual remaining thickness after a historical etching process. In one example, if the aggregate error function is less than an error tolerance, then the process3400determines that the thin-film data matches the historical thin-film data. In one example, if the aggregate error function is greater than an error tolerance, then the process3400determines that the thin-film data does not match the historical thin-film data. In one example, the error tolerance can include a tolerance between 0.1 and 0. In other words, if the aggregate percentage error is less than 0.1, or 10%, then the process3400considers that the predicted thin-film data matches the historical thin-film data. If the aggregate percentage error is greater than 0.1 or 10%, then the process3400considers that the predicted thin-film data does not match the historical thin-film data. Other tolerance ranges can be utilized without departing from the scope of the present disclosure. Error scores can be calculated in a variety of ways without departing from the scope of the present disclosure. The training module3304or the analysis model3302can make the determinations associated with process step3410.

In one embodiment, if the predicted thin-film data does not match the historical thin-film data3308at step3410, then the process proceeds to step3412. At step3412, the process3400adjusts the internal functions associated with the analysis model3302. In one example, the training module3304adjusts the internal functions associated with the analysis model3302. From step3412, the process returns to step3404. At step3404, the historical process conditions data is again provided to the analysis model3302. Because the internal functions of the analysis model3302have been adjusted, the analysis model3302will generate different predicted thin-film data that in the previous cycle. The process proceeds to steps3406,3408and3410and the aggregate error is calculated. If the predicted thin-film data does not match the historical thin-film data, then the process returns to step3412and the internal functions of the analysis model3302are adjusted again. This process proceeds in iterations until the analysis model3302generates predicted thin-film data that matches the historical thin-film data3308.

In one embodiment, if the predicted thin-film data matches the historical thin-film data then process step3410, in the process3400, proceeds to3414. At step3414training is complete. The analysis model3302is now ready to be utilized to identify process conditions and can be utilized in thin-film etching processes performed by the semiconductor process system3200. The process3400can include other steps or arrangements of steps than shown and described herein without departing from the scope of the present disclosure.

FIG.26is a flow diagram of a process3500for dynamically selecting process conditions for thin-film etching process and for performing a thin-film etching process, according to one embodiment. The various steps of the process3500can utilize components, processes, and techniques described in relation toFIGS.20-24. Accordingly,FIG.26is described with reference toFIGS.21-25.

At3502, the process3500provides target thin-film conditions data to the analysis model3302. The target thin-film conditions data identifies selected characteristics of a thin film to be formed by thin-film etching process. The target thin-film conditions data can include a target remaining thickness, a target composition, target crystal structure, or other characteristics of the thin film. The target thin-film conditions data can include a range of thicknesses. The target condition or characteristics that can be selected are based on thin film characteristic(s) utilized in the training process. In the example ofFIG.26, the training process focused on thin film thickness.

At3504, the process3500provides static process conditions to the analysis model3302. The static process conditions include process conditions that will not be adjusted for a next thin-film etching process. The static process conditions can include the target device pattern density indicating the density of patterns on the wafer on which the thin-film etching process will be performed. The static process conditions can include an effective plan area crystal orientation, an effective plan area roughness index, an effective sidewall area of the features on the surface of the semiconductor wafer, an exposed effective sidewall tilt angle, an exposed surface film function group, an exposed sidewall film function group, a rotation or tilt of the semiconductor wafer, process gas parameters (materials, phase of materials, and temperature of materials), a remaining amount of material fluid in the fluid sources3208and3210, a remaining amount of fluid in the purge sources3212and3214, a humidity within a process chamber, an age of an ampoule utilized in the etching process, light absorption or reflection within the process chamber, the length of pipes or conduits that will provide fluids to the process chamber, or other conditions. The static process conditions can include conditions other than those described above without departing from the scope of the present disclosure. Furthermore, in some cases, some of the static process conditions listed above may be dynamic process conditions subject to adjustment as will be described in more detail below. In the example ofFIG.26, dynamic process conditions include temperature, pressure, humidity, and flow rate. Static process conditions include phase, ampoule age, etching area, etching density, and sidewall angle.

At3506, the process3500selects dynamic process conditions for the analysis model, according to one embodiment. The dynamic process conditions can include any process conditions not designated as static process conditions. For example, the training set data may include a large number of various types of process conditions data in the historical process conditions data3310. Some of these types of process conditions will be defined as the static process conditions and some of these types of process conditions will be defined as dynamic process conditions. Accordingly, when the static process conditions are supplied at operation3504, the remaining types of process conditions can be defined as dynamic process conditions. The analysis model3302can initially select initial values for the dynamic process conditions. After the initial values have been selected for the dynamic process conditions, the analysis model has a full set of process conditions to analyze. In one embodiment, the initial values for the dynamic process conditions may be selected based on previously determined starter values, or in accordance with other schemes.

The dynamic process conditions can include the flow rate of fluids or materials from the fluid sources3208and3210during the etching process. The dynamic process conditions can include the flow rate of fluids or materials from the purge sources3212and3214. The dynamic process conditions can include a pressure within the process chamber, a temperature within the process chamber, a humidity within the process chamber, durations of various steps of the etching process, or voltages or electric field generated within the process chamber. The dynamic process conditions can include other types of conditions without departing from the scope of the present disclosure.

At3508, the analysis model3302generates predicted thin-film data based on the static and dynamic process conditions. The predicted thin-film data includes the same types of thin-film characteristics established in the target thin-film conditions data. In particular, the predicted thin-film data includes the types of predicted thin-film data from the training process described in relation toFIGS.21-25. For example, the predicted thin-film data can include thin-film thickness, film composition, or other parameters of thin films.

At3510, the process compares the predicted thin-film data to the target thin-film data. In particular, the analysis model3302compares the predicted thin-film data to the target thin-film data. The comparison indicates how closely the predicted thin-film data matches the target thin-film data. The comparison can indicate whether or not predicted thin-film data falls within tolerances or ranges established by the target thin-film data. For example, if the target thin-film thickness is between 1 nm and 9 nm, then the comparison will indicate whether the predicted thin-film data falls within this range.

At3512, if the predicted thin-film data does not match the target thin-film data, then the process proceeds to3514. At3514, the analysis model3302adjusts the dynamic process conditions data. From3514the process returns to3508. At3508, the analysis model3302again generates predicted thin-film data based on the static process conditions and the adjusted dynamic process conditions. The analysis model then compares the predicted thin-film data to the target thin-film data at3510. At3512, if the predicted thin-film data does not match the target thin-film data, then the process proceeds to3514and the analysis model3302again adjusts the dynamic process conditions. This process proceeds until predicted thin-film data is generated that matches the target thin-film data. If the predicted thin-film data matches the target thin-film data3512, then the process proceeds to3516.

At3516, the process3500adjusts the thin-film process conditions of the semiconductor process system3200based on the dynamic process conditions that resulted in predicted thin-film data within the target thin-film data. For example, the control system3224can adjust fluid flow rates, etching step durations, pressure, temperature, humidity, or other factors in accordance with the dynamic process conditions data.

At3518, the semiconductor process system3200performs a thin-film etching process in accordance with the adjusted dynamic process conditions identified by the analysis model. In one embodiment, the thin-film etching process is an ALE process. However, other thin-film etching processes can be utilized without departing from the scope of the present disclosure. In one embodiment, the semiconductor process system3200adjusts the process parameters based on the analysis model between individual etching stages in a thin-film etching process. For example, in an ALE process, the thin-film is etched one layer at a time. The analysis model3302can identify parameters to be utilized for etching of the next layer. Accordingly, the semiconductor process system can adjust etching conditions between the various etching stages.

Embodiments may provide advantages. The gate structures200A-200F improve gate fill window, and achieve lower gate resistance and higher reliability, while providing multiple Vt tuning with photolithographic patterning. Oxidation of the first work function metal layer250may be reduced by depositing the first, second and/or third protection layers271,272,273over the capping layer260. AI-controlled ALE promotes high-precision removal of the barrier layers700for further tuning of the threshold voltages. These techniques improve the flexibility in tuning the threshold voltage.

In accordance with at least one embodiment, a device includes a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure includes a first dielectric layer over the semiconductor channel, a first work function metal layer over the first dielectric layer, a first protection layer over the first work function metal layer, a second protection layer over the first protection layer, and a metal fill layer over the second protection layer.

In accordance with at least one embodiment, a device includes a first gate structure and a second gate structure. The first gate structure includes a first dielectric layer over a first semiconductor channel, a first work function metal layer over the first dielectric layer, a first protection layer over the first work function metal layer, a second protection layer over the first protection layer and a first metal fill layer over the second protection layer. The second gate structure includes a second dielectric layer over a second semiconductor channel, a first barrier layer over the second dielectric layer, a second work function metal layer over the first barrier layer, a third protection layer over the second work function metal layer, and a second metal fill layer over the third protection layer.

In accordance with at least one embodiment, a method comprises forming a first dielectric layer over a first channel, forming a first work function metal layer over the first dielectric layer, forming a first protection layer over the first work function metal layer, forming a second protection layer over the first protection layer, and forming a first metal fill layer over the second protection layer.