Calibration scheme for a non-linear ADC

In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

CROSS REFERENCES TO RELATED APPLICATIONS

This application claims priority from India provisional patent application No. 202141001383 filed on Jan. 12, 2021 which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

This description relates generally to analog to digital converters (ADCs), and more particularly to using a lookup-table in ADCs.

BACKGROUND

In many electronic devices, an analog input signal is converted to a digital output signal using an analog to digital converter (ADC). The ADC used for digitizing a signal in a radio-frequency (RF) sampling receiver may be required to operate at high speed. Such speeds may be in the order of giga samples per second (GSPS). However, there is a need to correct the non-linearity of the high-speed ADCs.

SUMMARY

In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

The present disclosure also relates to a method of operating an analog to digital converter (ADC). The method includes generating a delay signal responsive to a calibration signal, providing the delay signal to a backend ADC, the backend ADC having a first stage of a plurality of stages, measuring an error count of the first stage by a calibration engine, the error count is an absolute difference in a number of ones and zeroes generated by the first stage, and storing a delay value of the first stage in the calibration engine for which the error count is minimum.

The present disclosure also relates to a device that includes a processor, a memory coupled to the processor, and an analog to digital converter (ADC). The ADC is coupled to the processor and the memory. The ADC, having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

The same reference numbers or other reference designators are used in the drawings to designate the same or similar (structurally and/or functionally) features.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG.1is a block diagram of a circuit100, according to an example embodiment. The circuit100includes a calibration engine102, a digital to analog converter (DAC)104, a multiplexer M112, a voltage to delay (VD) block106, a backend analog to digital converter (ADC)124and a storage circuit108. The DAC104is coupled between the calibration engine102and the multiplexer M112. The multiplexer M112is also coupled to the calibration engine102. In one version, the multiplexer M112is controlled by the calibration engine102. The multiplexer M112receives an input voltage Vin110. The VD block106is coupled to the multiplexer M112and the calibration engine102. The backend ADC124is coupled to the VD block106and the calibration engine102. The storage circuit108is coupled to the backend ADC124and the calibration engine102. The storage circuit108may be constructed of digital memory circuits, register, flip-flops, RAM, ROM, transitory memory, part of a conventional memory circuit and/or part of a digital processor system.

The VD block106includes a preamplifier array116and a delay multiplexer DM120. The preamplifier array116is coupled to the multiplexer M112and includes one or more preamplifiers. The delay multiplexer DM120is coupled to the preamplifier array116. The backend ADC124is coupled to the delay multiplexer DM120. The backend ADC124may include multiple stages, such as a first stage and a second stage as illustrated inFIG.3. Each stage includes a delay block, an AND gate and a delay comparator. The calibration engine102is coupled to the multiple stages in the backend ADC124. The calibration engine102, in one example, includes an accumulator. The accumulator is coupled to the multiple stages in the backend ADC124. The calibration engine102, in one example, is or is a part of, a processing unit, a digital signal processor (DSP), a processor and/or a programmable logic device. The calibration engine102may include memory, logic and/or software.

In some example embodiments, each of the components of the VD block106are capable of communicating with the calibration engine102independently, and with other components of the circuit100. Each block or component of the circuit100may also be coupled to other blocks inFIG.1. Those connections are not described herein. The circuit100may include one or more conventional components that are not described herein for simplicity of the description.

The circuit100, in one example, is an analog to digital converter where the VD block106performs a voltage-to-delay function and the backend ADC124perform a delay-to-digital function. The circuit100operates in a delay-calibration mode, a memory-calibration mode and a mission mode. The mission mode is also referred as normal operation mode. The delay-calibration mode and the memory-calibration mode are now explained, in that order.

The calibration engine102generates multiple input codes which, in some example embodiments, correspond to a range of a known analog signal. In one example, the multiple input codes range from a minimum input code to a maximum input code. The multiple input codes, in one example, are uniformly distributed both in terms of frequency and step size. Step size, in one version, is a difference between two consecutive input codes. The DAC104generates calibration signal in response to each of the multiple input codes. For example, the DAC104generates a first calibration signal (e.g. a first analog calibration signal) in response to a first input code of the multiple input codes. The first calibration signal is received by the VD block106.

The multiplexer M112, in both delay-calibration mode and memory-calibration mode, provides the first calibration signal to the preamplifier array116. The multiplexer M112, in one example, is controlled by the calibration engine102. Each pre-amplifier in the VD block106has a different threshold voltage. As illustrated inFIG.2, each pre-amplifier in the preamplifier array116includes a first input connected to the output of the multiplexer M112(to receive the input signal, Vin110or the calibration signal from the DAC104) and a second input coupled to a threshold voltage. Each pre-amplifier in the preamplifier array116, in both delay-calibration mode and memory-calibration mode, compares the first calibration signal to a threshold voltage (e.g. the threshold voltage associated with each preamplifier in the preamplifier array116). The delay multiplexer DM120generates a delay signal based on an output of one of the preamplifiers.

The first stage in the backend ADC124generates a digital bit in response to the delay signal from the delay multiplexer DM120. Thus, the calibration engine102generates multiple input codes; the DAC104generates multiple calibration signals in response to the multiple input codes; and the VD block106generates multiple delay signals in response to the multiple calibration signals; and the first stage in the backend ADC124generates multiple digital bits in response to the multiple delay signals. These multiple digital bits generated by the first stage represents a digital code generated by the first stage in response to the multiple input codes generated by the calibration engine102.

The delay-calibration mode, in one example, includes multiple cycles. In one cycle, the calibration engine102modifies a delay value of a first delay block in the first stage. The calibration engine102generates multiple input codes. The first stage in the backend ADC124generates a digital code in response to the multiple input codes. The accumulator in the calibration engine102measures an error count of the first stage. The error count is an absolute difference in a number of ones and zeroes in the digital code. Based on the error count, the calibration engine102modifies the delay value of the first delay block in the subsequent cycle. The calibration engine102measure the error counts generated by the first stage in multiple such cycles. The calibration engine102stores a delay value of the first stage for which the error count of the first stage is minimum. This delay value is the delay value (or calibrated delay value) of the first delay block in the first stage. In one example, the circuit100uses a binary search or other known technique to find the delay value for which error count is minimum. A non-linearity at an output of a stage of backend ADC124is caused by a non-linear transfer function of that stage. The delay-calibration mode calibrates the stage to define an optimal gain for that stage across a range defined by multiple input codes.

The calibration engine102subsequently calibrates the delay value of a second delay block in the second stage. This includes multiple cycles as well. In one cycle, the calibration engine102modifies a delay value of the second delay block in the second stage. The calibration engine102generates multiple input codes. The second stage generates a digital code in response to the multiple input codes. The accumulator in the calibration engine102measures an error count of the second stage. The error count is an absolute difference in a number of ones and zeroes in the digital code. Based on the error count, the calibration engine102, in the subsequent cycle, modifies the delay value of the second delay block. The calibration engine102measures the error counts generated by the second stage in multiple such cycles. The calibration engine102stores the delay value of the second stage for which the error count of the second stage is minimum. This delay value is the delay value (or calibrated delay value) of the second delay block in the second stage.

In the same way, the calibration engine102measures an error count of each stage of the multiple stages in the backend ADC124across multiple cycles, and also stores a delay value of each stage of the backend ADC124. The delay value (or calibrated delay value) for each stage of the multiple stages in the backend ADC124are used subsequently during other modes of operation of the circuit100. In one example, the delay values are used to correct any non-linearities introduced in the backend ADC124. The delay-calibration mode is explained in detail in connection with circuit300illustrated inFIG.3.

In the memory-calibration mode, the calibration engine102generates multiple input codes. The multiple input codes, in some example embodiments, correspond to a range of a known analog signal. The DAC104generates a calibration signal in response to an input code of the multiple input codes. The VD block106generates a delay signal in response to the calibration signal. The backend ADC124generates an output code in response to the delay signal. The storage circuit108stores the input code at an address associated with the corresponding output code. For example, the storage circuit108stores a first input code at an address corresponding to the first output code, and the storage circuit108stores a second input code at an address corresponding to a second output code. In one example embodiment, the storage circuit108maintains, for all input codes, a look-up table to store an input code at an address corresponding to an associated output code. For example, in one version, when an output code100is generated corresponding to the input code010, the input code010is stored at the address100in the look-up table. Thus, the look-up table in the storage circuit108is populated in the memory-calibration mode with the input codes at respective addresses of output codes.

In the mission mode, the multiplexer M112provides the input voltage Vin110to the VD block106. The multiplexer M112, in one example embodiment, is controlled by the calibration engine102. The VD block106generates a delay signal in response to the input voltage Vin110. The backend ADC124generates a raw code in response to the delay signal. An input code stored at an address corresponding to the raw code is generated as a final output130by the circuit100. For each value of the input voltage Vin110, the raw code is matched to an address of the output code, and the input code stored at the address is provided as the final output130. Thus, the mission mode represents, in one version, normal operation of the circuit100in which an analog signal (such as a radio frequency analog signal) is received as Vin110and converted to a digital (e.g. binary) representation via the VD block106, the backend ADC124and the storage circuit108. The final output130is thus a digital representation of the analog signal Vin110.

The multiplexer M112, the VD block106, the backend ADC124and the storage circuit108form one channel in the circuit100. The circuit100can be implemented with two or more channels. In one example embodiment, each channel may be implemented in parallel with other channels. A second channel would include a second multiplexer, a second VD block, a second backend ADC and a second storage circuit. The second backend ADC in the second channel may be similar to the backend ADC124but both are calibrated separately as both may have different transfer functions because of manufacturing variations. Multiple channels allow the flexibility to have one channel in calibration mode (delay-calibration mode or memory-calibration mode) and the other channels operate in mission mode. Multiple channels also allow flexibility to have one or more channels in delay-calibration mode, one or more channels in memory-calibration mode and other channels in mission mode. Thus, when one or more channels are being calibrated, remaining channels are used in mission mode for analog to digital conversion. In one example, all the channels are calibrated using the DAC104, and all channels are controlled by the calibration engine102. In some example embodiments, there is no need to perform any matching between the channels as the backend ADC in each channel is calibrated independently. This also reduces the requirement of background estimation and calibration algorithms.

The combination of the preamplifier array116, the delay multiplexer DM120and the backend ADC124, in one example, acts as a non-linear ADC or delay-based ADC. Though this combination is highly non-linear, the circuit100is highly linear and operates at high speed with relaxed area and power requirements. The circuit100scales well with technology nodes. The circuit100pushes the high linearity requirement on the DAC104. This is advantageous because it is relatively less difficult to design and implement analog circuits for operation at lower speed with linearity and accuracy. According to the present disclosure, the backend ADC124may be designed to run at high speed by compromising linearity. However, with the backend ADC124operating in conjugation with the look-up table in the storage circuit108, the circuit100behaves like a linear analog to digital converter (ADC). Likewise, the storage circuit108may be implemented in digital circuits, and be configured for high speed.

Interfacing external analog signals to fast digital processing cores generally requires an ADC. With higher speeds in transmission of data, the ADC may be required to operate at very high speeds and with a good signal-to-noise ratio. Without the benefits of some example embodiments, such constraints could result in large power dissipation and large area requirements for the supporting integrated circuit. These issues may be especially prominent at fast sampling rates (for example, sampling rates in the order of giga-samples per second (GSPS)) because of analog non-idealities which may limit performance. The example embodiments of circuit100provides a backend ADC124with the lookup-table approach that can open up wide architectures using one or more non-linear ADCs but can be calibrated to provide the superior performance of a highly linear ADC.

In delay-calibration mode, a delay value of each delay block in the backend ADC124is calibrated and fixed. This ensures that the circuit100has a minimum gain throughout multiple input codes (which corresponds to a range of a known analog signal) generated by the calibration engine102. The gain of circuit100is affected by delay value of each stage in the backend ADC124, and the delay-calibration mode ensures that the delay value of each stage is calibrated optimally for the circuit100to operate as a linear high-speed ADC. The delay-calibration mode allows circuit100to act as a linear ADC as delays of each stage in the backend ADC124is calibrated to achieve optimal gain across a range defined by multiple input codes.

Hence, the circuit100does not require any complex algorithms or hardware for digital conversion of the input voltage Vin110. This reduces the area and power requirements of the circuit100. Thus, the circuit100is capable of being used in RF sampling receivers which operate at speeds of GSPS. The circuit100scales well with technology nodes and is capable of supporting high GSPS transfer rates in future technology nodes.

FIG.2is a block diagram of a portion of the circuit100illustrated inFIG.1, according to an example embodiment. The preamplifier array116includes multiple preamplifiers from1to n, where n is an integer, for example, pre-amp216a, pre-amp216bto pre-amp216n. In one example embodiment, one or more preamplifiers is a threshold integrated preamplifier (a preamplifier with a fixed threshold). The delay multiplexer DM120is coupled to the multiple preamplifiers in the preamplifier array116. The backend ADC124is coupled to an output of the delay multiplexer DM120. The calibration engine102is coupled to each preamplifier in the preamplifier array116via input line240, the delay multiplexer DM120and the backend ADC124. The calibration engine102, in one example, reset the preamplifiers through input line240.

In operation, the preamplifier array116receives the input voltage Vin110, in mission mode, from the multiplexer M112. Similar to amplifiers 54-60 of U.S. Pat. No. 10,673,456 (which is hereby incorporated by reference in its entirety), each preamplifier receives a different threshold voltage. For example, the pre-amp216areceives a threshold voltage Vt1, the pre-amp216breceives a threshold voltage Vt2and the pre-amp216nreceives a threshold voltage Vtn. In one example, Vt1<Vt2<Vtn. The threshold voltages Vt1, Vt2to Vtn are generated using, in one example embodiment, a voltage divider230. In one version, the pre-amp216nis coupled to a voltage supply directly or through a resistor. Each preamplifier generates a first and a second output signals (differential output signals) based on the difference between the input voltage Vin110and the threshold voltage. For example, the pre-amp216agenerates differential signals—a first output signal OUT_M1and a second output signal OUT P1. Similarly, the pre-amp216ngenerates differential signals—a first output signal OUT_Mn and a second output signal OUT_Pn.

Similar to the operation of multiplexer 211 in U.S. Pat. No. 10,673,452 (which is hereby incorporated by reference in its entirety), the delay multiplexer DM120receives the first and the second output signal (differential output signals) from each preamplifier of the multiple preamplifiers. The delay multiplexer DM120generates a delay signal202based on an output of one of the preamplifiers. The delay signal202includes a first delay signal OUT_M and a second delay signal OUT_P, and corresponds to the output signals of a preamplifier whose threshold voltage is closest to the input voltage Vin110. For example, if the magnitude of the input voltage Vin110is closest to the threshold voltage Vt1of the pre-amp216a, the first delay signal OUT_M and the second delay signal OUT_P corresponds to the first and second output signals OUT_M1and OUT_P1of the pre-amp216a. On the other hand, if the magnitude of the input voltage Vin110is closest to the threshold voltage Vt2of the pre-amp216b, the first delay signal OUT_M and the second delay signal OUT_P corresponds to the first and second output signals OUT_M2and OUT_P2of the pre-amp216b. In one example, the calibration engine102controls the delay multiplexer DM120to select the output signals of a preamplifier whose threshold voltage is closest to the input voltage Vin110. In another example, the calibration engine102controls the delay multiplexer DM120in calibration mode (both delay-calibration mode and memory-calibration mode), and a high-speed logic controls the delay multiplexer DM120in the mission mode. In some example embodiments, the high-speed logic includes a processor, memory, digital logic and/or a state machine.

In some example embodiments, the VD block106(combination of the preamplifier array116and the delay multiplexer DM120) converts the input voltage Vin110into delay signal202(OUT_P and OUT_M), such that the timings of the delay signal202(OUT_P and OUT_M) are representative of the input voltage Vin110. The VD block106, which may be used to generate the delay signal202(OUT_P and OUT_M) based on the input voltage Vin110, may be constructed and operated, for example, as described in U.S. Pat. No. 10,673,456 (based on U.S. patent application Ser. No. 16/410,698). The VD block106may include, for example, a conversion and folding circuit described in U.S. Pat. No. 10,673,456, which includes multiple preamplifiers for converting a voltage signal into delay signal, and also includes a folding block that contains multiple logic gates for selecting earlier-arriving and later-arriving ones of the first delay signal OUT_M and a second delay signal OUT_P.

Examples of voltage-to-delay devices which may be incorporated within the VD block106, and used to generate the delay signal202(OUT_P and OUT_M) based on the input voltage Vin110, are illustrated in U.S. patent application Ser. No. 17/131,981, filed Dec. 23, 2020. A voltage-to-delay device constructed in accordance with U.S. patent application Ser. No. 17/131,981 may have, for example, first and second comparators connected to first and second lines carrying complementary voltages representative of the input voltage Vin110, for generating first and second output signals during an active phase when the complementary voltages reach a suitable threshold voltage, such that delay between the output signals is representative of the input voltage Vin110. The present disclosure is not limited, however, to the devices and processes described in detail herein. Other suitable devices may perform a suitable voltage-to-delay function within the VD block106. As noted above, the entire disclosures of U.S. Pat. No. 10,673,456 and U.S. patent application Ser. No. 17/131,981 are incorporated herein by reference.

The preamplifiers (pre-amp216a, pre-amp216bto pre-amp216n) within the preamplifier array116have varying gains (e.g. “gain” as used herein may mean voltage gain, current gain or a delay—as discussed in more detail below, amplifiers/comparators have different delays based on the input signals) as a result of various factors, which may include design, process, input voltage Vin110, and/or temperature. In one example, the gains and ranges of the preamplifier pre-amp216a, pre-amp216bto pre-amp216nmay be adjusted, and preferably matched across the preamplifier array116. The preamplifier array116and the backend ADC124enables the circuit100to operate as a high-speed and high-performance analog to digital converter (ADC).

FIG.3is a block diagram of a portion of the circuit100illustrated inFIG.1, according to an example embodiment. The backend ADC124includes multiple stages illustrated as: a first stage310a, a second stage310bto an nthstage310n, where n is an integer greater than or equal to one and is not necessary equivalent to the value of n used inFIG.2. Each stage includes a delay block, an AND gate and a delay comparator. For example, the first stage310aincludes a delay block304a, an AND gate306aand a delay comparator308a. Similarly, the second stage310bincludes a delay block304b, an AND gate306band a delay comparator308b. The illustrated AND gates are merely examples, however, of logic gates that may be employed according to this disclosure. If desired, this disclosure may be implemented with or without AND gates and/or with or without gates other than AND gates. Further, in the illustrated configuration, the AND gates306a,306bto306nmay be essentially identical to each other, and the delay comparators308a,308bto308nmay be essentially identical to each other.

The calibration engine102is coupled to the multiple stages in the backend ADC124. The calibration engine102includes a first multiplexer MUX1314and an accumulator316. The accumulator316includes a second multiplexer MUX2322, an adder324and a register326. The delay block in each stage of the backend ADC124is coupled to the calibration engine102. For example, the delay block304a, the delay block304bto the delay block304nare coupled to the calibration engine102. The delay comparator in each stage of the backend ADC124is coupled to the first multiplexer MUX1314in the calibration engine102. For example, the delay comparator308a, the delay comparator308bto the delay comparator308nare coupled to the first multiplexer MUX1314in the calibration engine102.

The accumulator316is coupled to the first multiplexer MUX1314. The second multiplexer MUX2322is coupled to the first multiplexer MUX1314. The adder324is coupled to the second multiplexer MUX2322and the register326. It is understood that the calibration engine102can include multiple other parts which are not illustrated here for simplicity. The calibration engine102may include one or more conventional components that are not described herein for simplicity of the description. Multiple components of backend ADC124may be coupled to and communicate with the calibration engine102. However, these connections are not shown inFIG.3for simplicity.

In operation, signals AN and BN (where N=1, 2 . . . n, for first stage310a, second stage310btonthstage310nrespectively) are received by respective ones of the AND gates306a,306bto306n. The AND gates306a,306bto306(n−1) generate corresponding signals AN′. For example, AND gate306areceives signal A1and B1and generates A1′. For each one of the AND gates, the timing of the leading edge of signal AN′ tracks the timing of the leading edge of the later-arriving of signals AN and BN.

The circuit100operates in a delay-calibration mode, a memory-calibration mode and a mission mode. The delay-calibration mode and the memory-calibration mode are now explained, in that order. The calibration engine102generates multiple input codes. The multiple input codes, in some example embodiments, correspond to a range of a known analog signal. In one example, the multiple input codes range from a minimum input code to a maximum input code. The multiple input codes, in one example, are uniformly distributed both in terms of frequency and step size. Step size, in one version, is a difference between two consecutive input codes. The DAC104generates calibration signal in response to each of the multiple input codes. For example, the DAC104generates a first calibration signal (e.g. a first analog calibration signal) in response to a first input code of the multiple input codes. The first calibration signal is received by the VD block106.

The multiplexer M112, in both delay-calibration mode and memory-calibration mode, provides the first calibration signal to the preamplifier array116. The multiplexer M112, in one example, is controlled by the calibration engine102. Each pre-amplifier in the VD block106has a different threshold voltage. As discussed in connection withFIG.2, the delay multiplexer DM120outputs a delay signal302based on an output of one of the preamplifiers. The delay signal302includes differential signals (a first delay signal OUT_M and a second delay signal OUT_P), and corresponds to the output signals of a preamplifier whose threshold voltage is closest to the calibration signal. In one example, the calibration engine102enables the delay multiplexer DM120in calibration mode (both delay-calibration mode and memory-calibration mode), and a high-speed logic enables the delay multiplexer DM120in the mission mode. In some example embodiments, the high-speed logic includes a processor, memory, digital logic and/or a state machine.

The backend ADC124receives the delay signal302(OUT_P and OUT_M) from VD block106. The timings of the first delay signal OUT_M and a second delay signal OUT_P have a delay which is representative of the input voltage Vin110. The first stage310ain the backend ADC124generates a digital bit in response to the delay signal302from the delay multiplexer DM120. Thus, the calibration engine102generates multiple input codes, the VD block106generates multiple delay signals in response to multiple input codes and the first stage310ain the backend ADC124generates multiple digital bits in response to the multiple delay signals. These multiple digital bits generated by the first stage310arepresents a digital code generated by the first stage in response to the multiple input codes generated by the calibration engine102. Thus, the digital code includes multiple digital bits, and a digital bit corresponds to an input code.

The delay-calibration mode may be implemented over multiple cycles. For example, with reference to a delay calibration of the first stage310a, in one cycle, the calibration engine102modifies a delay value D1312aof the delay block304ain the first stage310a. The calibration engine102generates multiple input codes. The first stage310ain the backend ADC124generates a digital code in response to the multiple input codes. The digital code from the first stage310ais provided to the accumulator316in the calibration engine102through the first multiplexer MUX1314. The accumulator316in the calibration engine102measures an error count of the first stage310a. The error count is an absolute difference in a number of ones and zeroes in the digital code.

In operation, the accumulator316processes the digital bits in the digital code serially, in one version. The accumulator316includes the second multiplexer MUX2322which receives the digital bit from the first multiplexer MUX1314. Based on the digital bit, the second multiplexer MUX2322generates one of the inputs, +1 or −1. The adder324adds a previous value of the error count which is stored in the register326to the input received from the second multiplexer MUX2322, and generates a new value of the error count. This new value of the error count is stored in the register326.

Based on the error count stored in the register326, the calibration engine102modifies the delay value D1312aof the delay block304ain a subsequent cycle (e.g. a next cycle). The calibration engine102measures the error count generated by the first stage310ain multiple such cycles. The calibration engine102stores a delay value of the first stage310afor which the error count of the first stage310ais minimum. This delay value is the delay value D1312aof the delay block304ain the first stage310a. The delay value D1312aof the first stage310ais stored in a memory location (not shown inFIG.3) specific to the first stage310a. Thus, the calibration engine102provides multiple input codes over multiple cycles, and a delay value of a stage (for example the first stage310a) is iteratively modified until the delay-calibration mode for that stage is complete. A non-linearity at an output of a stage of backend ADC124is caused by a non-linear transfer function of that stage. The delay-calibration mode calibrates the stage to define an optimal gain for that stage across a range defined by multiple input codes. For example, the stored delay value D1312aof the first stage310ais used to compensate any non-linearity caused by the non-linear transfer function of the first stage310a. Hence, the delay calibration mode calibrates the first stage310ato achieve an optimal gain for the first stage310aacross a range defined by multiple input codes.

Once the first stage310ais calibrated, the calibration engine102calibrates a delay value D2312bof the delay block304bin the second stage310b. This includes multiple cycles as well. In one cycle, the calibration engine102modifies the delay value D2312bof the delay block304bin the second stage310b. The calibration engine102generates multiple input codes. The second stage310bgenerates a digital code in response to the multiple input codes. The accumulator316in the calibration engine102measures an error count of the second stage310b. The error count is an absolute difference in a number of ones and zeroes in the digital code. Based on the error count stored in the register326, the calibration engine102modifies the delay value D2312bof the delay block304bin the subsequent cycle. The calibration engine102measures the error count generated by the second stage310bin multiple such cycles. The calibration engine102stores a delay value of the second stage310bfor which the error count of the second stage310bis minimum. This delay value is the delay value D2312bof the delay block304bin the second stage310b. The delay value D2312bmay be stored in a memory location (not shown inFIG.3) specific to the second stage310bor in the same memory as the stored delay value D1312aor in a separate memory.

In the same way, the calibration engine102measures an error count of each stage of the multiple stages in the backend ADC124across multiple cycles, and also stores a delay value of each stage of the backend ADC124. Based on the error count of each stage, the delay value, for each stage is modified by the calibration engine102to get optimal uniform gain till that stage. Thus, the delay calibration mode may be performed iteratively whereby a delay value of a stage is calibrated over one or more cycles followed by calibrating a delay value of a next stage. During the calibration-mode, each stage (310a,310b. . .310n) is iteratively calibrated and a corresponding delay value (D1, D2. . . Dn) is generated and stored, as described above. The delay value (or calibrated delay value) for each stage of the multiple stages in the backend ADC124are used subsequently during other modes of operation of the circuit100. Thus, the circuit100uses a single accumulator316for calibrating all the stages in the backend ADC124.

In the memory-calibration mode, the calibration engine102generates multiple input codes. The multiple input codes, in some example embodiments, correspond to a range of a known analog signal. The DAC104generates a calibration signal in response to an input code of the multiple input codes. The VD block106generates a delay signal in response to the calibration signal. The backend ADC124generates an output code in response to the delay signal. The delay values of multiple stages in the backend ADC124stored during the delay-calibration mode are used in the memory calibration mode to generate the output code. The storage circuit108stores the input code at an address associated with the corresponding output code. For example, the storage circuit108stores a first input code at an address corresponding to the first output code, and the storage circuit108stores a second input code at an address corresponding to a second output code. In one example embodiment, the storage circuit108maintains, for all input codes, a look-up table to store an input code at an address corresponding to an associated output code. For example, in one version, when an output code100is generated corresponding to the input code010, the input code010is stored at the address100in the look-up table. Thus, the look-up table in the storage circuit108is populated in the memory-calibration mode with the input codes at respective addresses of output codes.

In the mission mode, the multiplexer M112provides the input voltage Vin110to the VD block106. The multiplexer M112, in one example embodiment, is controlled by the calibration engine102. The VD block106generates a delay signal in response to the input voltage Vin110. The backend ADC124generates a raw code in response to the delay signal. An input code stored at an address corresponding to the raw code is generated as a final output130by the circuit100. For each value of the input voltage Vin110, the raw code is matched to an address of the output code, and the input code stored at the address is provided as the final output130. Thus, when the input voltage Vin110is received by the circuit100, a digital code corresponding to the input voltage Vin110is generated by the circuit100and the look-up table in the storage circuit108is used by the circuit100in conversion of the input voltage Vin110to the digital code.

In delay-calibration mode, a delay value of each delay block in the backend ADC124is calibrated and fixed. This ensures that the circuit100has a minimum gain throughout multiple codes (which corresponds to a range of a known analog signal) generated by the calibration engine102. The gain of circuit100is affected by delay value of each stage in the backend ADC124, and the delay-calibration mode ensures that the delay value of each stage is calibrated optimally for the circuit100to operate as a linear high-speed ADC. The delay-calibration mode allows circuit100to act as a linear ADC as delays of each stage in the backend ADC124is calibrated to achieve optimal gain across a range defined by multiple input codes.

Hence, the circuit100does not require any complex algorithms or hardware for digital conversion of the input voltage Vin110. This reduces the area and power requirements of the circuit100. Thus, the circuit100is capable of being used in RF sampling receivers which operate at speeds of GSPS. The circuit100scales well with technology nodes and is capable of supporting high GSPS transfer rates in future technology nodes.

FIG.4is a flowchart400of a method of operation of a circuit, according to an example embodiment. The flowchart400is described in connection with the circuit100ofFIG.1and/or its components illustrated inFIG.2andFIG.3. The flowchart400illustrates a methodology for operating a circuit in delay calibration mode. At step402, a delay signal is generated in response to a calibration signal. In circuit100, the calibration engine102generates multiple input codes. The multiple input codes, in some example embodiments, correspond to a range of a known analog signal. In one example, the multiple input codes range from a minimum input code to a maximum input code. The multiple input codes, in one example, are uniformly distributed both in terms of frequency and step size. Step size, in one version, is a difference between two consecutive input codes. The DAC104generates calibration signal in response to each of the multiple input codes. For example, the DAC104generates a first calibration signal (e.g. a first analog calibration signal) in response to a first input code of the multiple input codes. The VD block106receives the calibration signal and generates the delay signal. The VD block106includes the preamplifier array116and the delay multiplexer DM120. The multiplexer M112provides the first calibration signal to the preamplifier array116. The multiplexer M112, in one example, is controlled by the calibration engine102. Each pre-amplifier in the VD block106has a different threshold voltage. Each pre-amplifier in the preamplifier array116, in both delay-calibration mode and memory-calibration mode, compares the first calibration signal to a threshold voltage (e.g. the threshold voltage associated with each preamplifier in the preamplifier array116). The delay multiplexer DM120generates the delay signal based on an output of one of the preamplifiers. As explained in connection withFIG.3, the delay signal302includes a first delay signal OUT_M and a second delay signal OUT_P, and corresponds to the output signals of a preamplifier whose threshold voltage is closest to the calibration signal.

At step404, the delay signal is provided to a backend ADC. The backend ADC includes a first stage of multiple stages. The error count of the first stage is measured by the calibration engine, at step406. The error count is an absolute difference in a number of ones and zeroes generated by the first stage. The backend ADC124includes multiple stages illustrated inFIG.3as first stage310a, a second stage310bto an nth stage310n. Each stage includes a delay block, an AND gate and a delay comparator.

The first stage310ain the backend ADC124generates a digital bit in response to the delay signal302from the delay multiplexer DM120. The calibration engine102generates multiple input codes; the VD block106generates multiple delay signals in response to the multiple input codes; and the first stage310ain the backend ADC124generates multiple digital bits in response to the multiple delay signals. These multiple digital bits generated by the first stage310arepresents a digital code generated by the first stage in response to the multiple input codes generated by the calibration engine102.

The first stage310ain the backend ADC124generates a digital code in response to the multiple input codes. The digital code from the first stage310ais provided to the accumulator316in the calibration engine102through the first multiplexer MUX1314. The accumulator316in the calibration engine102measures an error count of the first stage310a. The error count is the absolute difference in a number of ones and zeroes in the digital code.

At step408, a delay value of the first stage is stored in the calibration engine for which the error count is minimum. In circuit100, the calibration engine102stores a delay value of the first stage310afor which the error count of the first stage310ais minimum. This delay value is the delay value D1312aof the delay block304ain the first stage310a.

The circuit100operates in a delay-calibration mode which may be implemented over multiple cycles. For example, with reference to a delay calibration of the first stage310a, in one cycle, the calibration engine102modifies a delay value D1312aof the delay block304ain the first stage310a. The calibration engine102generates multiple input codes. The first stage310ain the backend ADC124generates a digital code in response to the multiple input codes. The digital code from the first stage310ais provided to the accumulator316in the calibration engine102through the first multiplexer MUX1314. The accumulator316in the calibration engine102measures an error count of the first stage310a. The error count is the absolute difference in a number of ones and zeroes in the digital code.

Based on the error count, the calibration engine102modifies the delay value D1312aof the delay block304ain a subsequent cycle (e.g. a next cycle). The calibration engine102measures the error count generated by the first stage310ain multiple such cycles. The calibration engine102stores a delay value of the first stage310afor which the error count of the first stage310ais minimum. This delay value is the delay value D1312a(or calibrated delay value) of the delay block304ain the first stage310a. The delay value D1312aof the first stage310ais stored in a memory location (not shown inFIG.3) specific to the first stage310a. Thus, the calibration engine102provides multiple input codes over multiple cycles, and a delay value of a stage (for example the first stage310a) is iteratively modified until the delay-calibration mode for that stage is complete. A non-linearity at an output of a stage of backend ADC124is caused by a non-linear transfer function of that stage. The delay-calibration calibration mode calibrates the stage to define an optimal gain for that stage across a range defined by multiple input codes. For example, the stored delay value D1312aof the first stage310ais used to compensate any non-linearity caused by the non-linear transfer function of the first stage310a. Hence, the delay calibration mode calibrates the first stage310ato achieve an optimal gain for the first stage310aacross a range defined by multiple input codes.

Once the first stage310ais calibrated, the calibration engine102calibrates a delay value D2312bof the delay block304bin the second stage310b. This includes multiple cycles as well. In one cycle, the calibration engine102modifies the delay value D2312bof the delay block304bin the second stage310b. The calibration engine102generates multiple input codes. The second stage310bgenerates a digital code in response to the multiple input codes. The accumulator316in the calibration engine102measures an error count of the second stage310b. The error count is an absolute difference in a number of ones and zeroes in the digital code. Based on the error count, the calibration engine102, in the subsequent cycle, modifies the delay value D2312bof the delay block304b. The calibration engine102measures the error count generated by the second stage310bin multiple such cycles. The calibration engine102stores a delay value of the second stage310bfor which the error count of the second stage310bis minimum. This delay value is the delay value D2312b(or calibrated delay value) of the delay block304bin the second stage310b. The delay value D2312bmay be stored in a memory location (not shown inFIG.3) specific to the second stage310bor in the same memory as the stored delay value D1312aor in a separate memory.

In the same way, the calibration engine102measures an error count of each stage of the multiple stages in the backend ADC124across multiple cycles, and also stores a delay value (or calibrated delay value) of each stage of the backend ADC124. Based on the error count of each stage, the delay value, for each stage is modified by the calibration engine102to compensate for non-linearities in the delay of each stage. Thus, the delay calibration mode may be performed iteratively whereby a delay value of a stage is calibrated over one or more cycles followed by calibrating a delay value of a next stage. The delay value for each stage of the multiple stages in the backend ADC124are used subsequently during other modes of operation of the circuit100.

The method enables the circuit100, in delay-calibration mode, to calibrate and fix a delay value of each delay block in the backend ADC124. This ensures that the circuit100has a minimum gain throughout multiple codes generated by the calibration engine102. The gain of circuit100is affected by delay value (which, for example, is subject to irregularities and non-linearities based on semiconductor manufacturing variations and temperature-dependent factors) of each stage in the backend ADC124, and the method through the delay-calibration mode ensures that the delay value of each stage is calibrated optimally for the circuit100to operate as a high-speed ADC. The delay-calibration mode allows circuit100to act as a linear ADC as delays of each stage in the backend ADC124is calibrated to achieve optimal gain across a range defined by multiple input codes.

Hence, the method provides that the circuit100does not require any complex algorithms or hardware for digital conversion of the input voltage Vin110. Thus, the method of some example embodiments ensures that the circuit100is capable of being used in RF sampling receivers which operate at speeds of GSPS. The circuit100scales well with technology nodes and is capable of supporting high GSPS transfer rates in future technology nodes.

FIG.5is a flowchart500of a method of operation of a circuit, according to an example embodiment. The flowchart500is described in connection with the circuit100ofFIG.1and/or its components illustrated inFIG.2andFIG.3. The flowchart500illustrates calibrating multiple stages310a,310bto310nusing the delay calibration mode which, for example, includes multiple cycles. At step502, a delay value of stage k is set. In circuit100, for example, the backend ADC124includes multiple stages illustrated inFIG.3as first stage310a, a second stage310bto an nth stage310n. Each stage includes a delay block, an AND gate and a delay comparator. The calibration engine102sets a delay value D1312aof the delay block304ain the first stage310a.

At step504, a calibration engine generates multiple input codes. For example, in circuit100, the calibration engine102generates multiple input codes. The first stage310a(or stage k) in the backend ADC124generates a digital code in response to the multiple input codes. The digital code from the first stage310a(or stage k) is provided to the accumulator316in the calibration engine102. At step506, a number of ones (c1) and zeroes (c0) at output of stage k is counted. An absolute error count (E) is measured from a difference in the number of ones (c1) and zeroes (c0).
E=|c1−c0|  (1)
The accumulator316in the calibration engine102measures an error count of the first stage310a(or stage k). The error count is an absolute difference in a number of ones and zeroes in the digital code generated by the first stage310a(or stage k). At step508, it is determined if search (calibration of stage k) is complete. The search (or calibration of stage k) is considered complete when the error count at the output of stage k has been obtained for all the input codes. In one version, search is considered complete when there is a change in sign of the error count (E) for stage k. In another example embodiment, search is considered complete when a minimum absolute value of error count (E) is achieved. If the search (calibration of stage k) is complete, the method proceeds to step512else the method proceeds to step520.

At step512, the delay value for stage k is modified. The delay value is modified based on the error count (E) (or relative counts of ones and zeroes) for that stage. If the error count (E) is greater than zero, the delay value of the stage k is incremented and if the error count (E) is less than zero, the delay value of the stage k is decremented. In circuit100, for example, based on the error count (or counts of ones and zeroes), the calibration engine102, modifies the delay value D1312aof the delay block304ain the first stage310a. In one version, if the error count is greater than a threshold, the delay value of the delay block304ais incremented, and if the error count is lesser than a threshold, the delay value of the delay block304ais decremented.

Steps504to512are repeated until the search (or delay calibration) is complete for stage k. In one version, steps504to512are repeated until there is a change in sign of the error count (E) for stage k. In another example embodiment, steps504to512are repeated until a minimum absolute value of error count (E) is achieved. In circuit100as well, the delay calibration mode may include multiple cycles. In one example, the delay calibration starts from the first stage310a(k=1), at step502. In each cycle of step504to512, the calibration engine102iteratively modifies the delay value D1312aof the delay block304a. The calibration engine102measures the error count generated by the first stage310ain multiple such cycles.

At step520, the delay of stage k is fixed for which minimum absolute value of the error count (E) is achieved. In circuit100, the calibration engine102stores a delay value of the first stage310afor which the absolute value of error count of the first stage310ais minimum. This delay value is the delay value D1312aof the delay block304ain the first stage310a. At step524, in a system having n stages where n is the last stage, the method compares if k is equal to n. At step526, if the method has not reached the last stage, k is incremented by one, in one example. In another example, k is incremented by an integer greater than 1. Thereafter, all the steps illustrated in flowchart500are repeated for stage k+1.

At step528, if the method has reached the last stage (n), the system resets and the steps illustrated in flowchart500are repeated from first stage to nth stage. Similarly, in circuit100, the calibration engine102measures an error count of each stage of the multiple stages in the backend ADC124across multiple cycles, and also stores a delay value of each stage of the backend ADC124. The delay value for each stage of the multiple stages in the backend ADC124are used subsequently during other modes of operation of the circuit100. In some example embodiments, step528is optional.

The method illustrated by flowchart500enables the circuit100, in delay-calibration mode, to calibrate and compensate for a delay value of each delay block in the backend ADC124. This ensures that the circuit100has a minimum gain throughout multiple codes generated by the calibration engine102. The gain of circuit100is affected by delay value of each stage in the backend ADC124, and the method through the delay-calibration mode ensures that the delay value of each stage is calibrated optimally for the circuit100to operate as a high-speed ADC. The method allows circuit100to act as a linear ADC as delays of each stage in the backend ADC124is calibrated to achieve optimal gain across a range defined by multiple input codes.

Hence, the method provides that the circuit100does not require any complex algorithms or hardware for digital conversion of the input voltage Vin110. This reduces the area and power requirements of the circuit100. Thus, the method ensures that the circuit100is capable of being used in RF sampling receivers which operate at speeds of GSPS. The circuit100scales well with technology nodes and is capable of supporting high GSPS transfer rates in future technology nodes.

FIG.6is a graph which illustrates AND-gate delay and comparator delay generated by an AND gate and a delay comparator, respectively, in a stage of a backend ADC, according to an example embodiment. The graph is explained in connection with the backend ADC124illustrated inFIG.3. The graph includes an X-axis (T_IN) and a Y-axis (Output Delay). The AND-gate (for example the AND gates306a,306bto306n) delay and the comparator (for example the delay comparators308a,308bto308n) delay are functions of input-signal delay, according to an example embodiment. The input-signal delay is delay between the signals received by the AND gate or by the delay comparator. As illustrated, the AND-gate delay602contributed by a respective AND gate is linearly related to the absolute value of an input-signal delay T_IN, where the input-signal delay T_IN is the difference in timing between signals AN and BN input into the respective AND gate, where N is an integer and N is equal to 1 for the first stage310aand N is equal to 2 for second stage310b. In the illustrated configuration, the relationship of the AND gate delay602to the input-signal delay T_IN is linear regardless of whether AN or BN leads or follows.

Signals AN and BN are also applied to the inputs of the delay comparators, causing the delay comparators to generate corresponding signal BN′. For each one of the delay comparators (for example308aand308b), the timing of the leading edge of signal BN′ tracks the timing of the leading edge of the earlier-arriving of signals AN and BN. In particular, for each one of the delay comparators, the timing of the leading edge of signal BN′ is equal to (1) the timing of the leading edge of the earlier-arriving of signals AN and BN plus (2) a comparator delay604that is logarithmically inversely related to the absolute value of the input-signal delay T_IN (in other words, comparator delay is greater for input values that are more similar, and if the difference between the two inputs to the comparator is greater, the comparator delay is less).

FIG.7is a graph which illustrates output-signal delay of a stage as a function of the input-signal delay of the stage of a backend ADC, according to an example embodiment. Subtracting the AND gate-delay602from the comparator delay604yields the output-signal delay T_OUT for any given single-bit stage for example, the first stage310a. When the absolute value of the input-signal delay T_IN is less than a threshold delay T_THRES, then the output-signal delay T_OUT is a positive value (meaning that the leading edge of signal BN′ generated by the respective delay comparator lags the leading edge of signal AN′ generated by the respective AND gate. On the other hand, when the absolute value of the input-signal delay T_IN is greater than the threshold delay T_THRES, then the output-signal delay T_OUT is a negative value (meaning that the leading edge of signal AN′ leads the leading edge of corresponding signal BN′). The positive or negative character of the output-signal delay T_OUT is reported to the calibration engine102.

In operation, the delay comparator308aissues a first sign signal (“1” or “0”) to the calibration engine102. The first sign signal (an example of a digital signal in accordance with this disclosure) is based on which one of the leading edges of signals A1and B1is first received by the delay comparator308a, such that the first sign signal reflects the order of the leading edges of signals A1and B1applied to the delay comparator308a. The AND gate306aand the delay comparator308agenerate signals A1′ and B1′ which are applied to the second stage310b. The delay comparator308boutputs a second sign signal (“1” or “0”) to the calibration engine102. The second sign signal is based on which one of the leading edges of the signals A2and B2is first received by the delay comparator308b, such that the second sign signal reflects the order of the leading edges of the signals A2and B2applied to the delay comparator308b.

Since the delay between signals A1and B1can be predicted as a function of the input voltage Vin110, and vice versa, and since the delay between the signals AN′ and BN′ output by a successive stage can be predicted as a function of the signals AN and BN received from the preceding stage, and vice versa, the sign signals output by the delay comparators of the cascade of stages can be predicted as a function of the input voltage Vin110, and vice versa. Therefore, a code made up of the sign signals may be reliably compared to a predetermined correlation to determine an approximation of the input voltage Vin110. In operation, the timings of the signals A1and B1are functionally (that is, predictably) related to the timings of the signals OUT_P and OUT_M whose timing is correlated to the input voltage Vin110, as discussed above. The timings of the signals A1′ and B1′ are functionally (that is, predictably) related to the timings of the signals A1and B1, and so on. Thus, since the timings of the signals OUT_P and OUT_M are functionally (that is, predictably) related to the input voltage Vin110, the timings of the signals on lines A1, B1, A1′, B1′, and so on, which determine the sign signals used to make up the output code, are also functionally related to the input voltage Vin110.

FIGS.8A and8Bare graphs which illustrates output-signal delay of different stages as a function of the input-signal delay of a backend ADC, according to an example embodiment. As discussed in connection withFIG.7, subtracting the AND gate-delay602from the comparator delay604yields the output-signal delay T_OUT for any given single-bit stage for example, the first stage310a. When the absolute value of the input-signal delay T_IN is less than a threshold delay T_THRES, then the output-signal delay T_OUT is a positive value (meaning that the leading edge of signal BN′ generated by the respective delay comparator lags the leading edge of signal AN′ generated by the respective AND gate. On the other hand, when the absolute value of the input-signal delay T_IN is greater than the threshold delay T_THRES, then the output-signal delay T_OUT is a negative value (meaning that the leading edge of signal AN′ leads the leading edge of corresponding signal BN′).

Graph802arepresents an output signal delay for a first and a second stage in a traditional circuit. Graph802brepresents an output signal delay for the first stage310aand the second stage310bof circuit100. Graph804arepresents an output signal delay for a third and a fourth stage in a traditional circuit. Graph804brepresents an output signal delay for the third stage310cand a fourth stage310dof circuit100. Thus, from graph802a, gain profile of second stage is asymmetric, higher gain at toggling point and lower gain at extreme points. In addition, if correction is performed to correct the asymmetric nature of second stage, it results in error during calibration of subsequent stages. Also, calibration of second stage at toggling points of third stage results in error during calibration of subsequent stages. However, circuit100is able to address all these challenges. As represented by graph802b, the circuit100provides a symmetric gain profile for second stage310b. The circuit100uses a delay calibration mode which ensures delay value of each stage in the backend ADC124is calibrated. Similarly, graph804billustrates that the circuit100provides a symmetric gain profile for the third stage310cand the fourth stage310d.

The calibration engine102measures an error count of each stage of the multiple stages in the backend ADC124across multiple cycles, and also stores a delay value of each stage of the backend ADC124. The error count is an absolute difference in a number of ones and zeroes in the digital code generated by a stage. The delay value (or calibrated delay value) for each stage of the multiple stages in the backend ADC124are used subsequently during other modes of operation of the circuit100. These delay values (or calibrated delay values) of each stage distribute asymmetricity across the range of input codes making gain uniform. Thus, as illustrated by graphs802band804b, the delay-calibration mode ensures that the delay value of each stage is calibrated optimally for the circuit100to operate as a high-speed ADC. The calibration mode ensures better standard deviation resulting in more uniform gain across regions. Also, circuit100provides for averaging in each stage during delay calibration which makes it more robust to noise.

FIG.9is a block diagram of an example device900in which several aspects of example embodiments can be implemented. The device900is, or in incorporated into or is part of, a server farm, a vehicle, a communication device, a transceiver, a personal computer, a gaming platform, a computing device, or any other type of electronic system. The device900may include one or more conventional components that are not described herein for simplicity of the description.

In one example, the device900includes a processor902and a memory906. The processor902can be a CISC-type (complex instruction set computer) CPU, RISC-type CPU (reduced instruction set computer), a digital signal processor (DSP), a processor, a CPLD (complex programmable logic device) or an FPGA (field programmable gate array).

The memory906(which can be memory such as RAM, flash memory, or disk storage) stores one or more software applications (e.g., embedded applications) that, when executed by the processor902, performs any suitable function associated with the device900.

The processor902may include memory and logic, which store information frequently accessed from the memory906. The device900includes a circuit910. In one example, the processor902may be placed on the same printed circuit board (PCB) or card as the circuit910. In another example, the processor902is external to the device900. The circuit910can function as an analog to digital converter.

The circuit910is similar, in connection and operation, to the circuit100ofFIG.1. The circuit910includes a calibration engine (for example, calibration engine102), a digital to analog converter (DAC)(e.g. DAC104), a multiplexer (e.g. multiplexer M112), a voltage to delay (VD) block (e.g. VD block106), a backend analog to digital converter (ADC) (e.g. backend ADC124) and a storage circuit (e.g. storage circuit108). The VD block includes a preamplifier array (e.g. preamplifier array116) and a delay multiplexer DM (e.g. delay multiplexer DM120). The multiplexer receives an input voltage Vin. The preamplifier array includes multiple preamplifiers (e.g. as illustrated inFIG.2).

The VD block perform a voltage-to-delay function. The backend ADC perform a delay-to-digital function. Similar to the description above, the circuit910operates in a delay-calibration mode, a memory-calibration mode and a mission mode.

While the use of particular transistors are described herein, other transistors (or equivalent devices) may be used instead. For example, a p-type metal-oxide-silicon FET (“MOSFET”) may be used in place of an n-type MOSFET with little or no changes to the circuit. Furthermore, other types of transistors may be used (such as bipolar junction transistors (BJTs)).