CIRCUIT FOR DETECTING DEFECTS

A circuit for detecting defects includes a defect detection conductor provided in a peripheral region of a semiconductor die, an input pad connected to a first end of the defect detection conductor, an output pad connected to a second end of the defect detection conductor, a defect detection assembly connected to the defect detection conductor and configured to detect a defect of the defect detection conductor, and a controller configured to control operations of the defect detection assembly, where the defect detection assembly includes a reference voltage supply, a reference capacitor, a switching assembly, and a plurality of detection capacitors, and the switching assembly is configured to connect the reference capacitor to one of the reference voltage supply, a position adjacent to the input pad of the defect detection conductor, and a position adjacent to the output pad of the defect detection conductor.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority to Korean Patent Application No. 10-2023-0121920, filed on Sep. 13, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Example embodiments of the present disclosure relate to a circuit for detecting defects.

Once a semiconductor chip is manufactured on the wafer level, a packaging process is completed, and a semiconductor package is manufactured, a test process may be performed to test the product by intentionally exposing the semiconductor package to a target temperature or humidity. As a wafer goes through scribing, sawing, assembly, and testing processes, defects such as cracks may occur on the periphery of a semiconductor die or on a bonding pad. In this case, detecting defects in advance may be an important factor in maintaining reliability of the semiconductor package.

Information disclosed in this Background section has already been known to or derived by the inventors before or during the process of achieving the embodiments of the present application, or is technical information acquired in the process of achieving the embodiments. Therefore, it may contain information that does not form the prior art that is already known to the public.

SUMMARY

One or more example embodiments provide a circuit for detecting defects that detects the presence and position of defects which may occur during a semiconductor process in which a semiconductor package is manufactured at a wafer level, thereby maintaining reliability of the semiconductor package.

According to an aspect of an example embodiment, a circuit for detecting defects may include a defect detection conductor provided in a peripheral region of a semiconductor die, an input pad connected to a first end of the defect detection conductor, an output pad connected to a second end of the defect detection conductor, a defect detection assembly connected to the defect detection conductor and configured to detect a defect of the defect detection conductor, and a controller configured to control operations of the defect detection assembly, where the defect detection assembly includes a reference voltage supply, a reference capacitor, a switching assembly, and a plurality of detection capacitors, the switching assembly is configured to connect the reference capacitor to one of the reference voltage supply, a position adjacent to the input pad of the defect detection conductor, and a position adjacent to the output pad of the defect detection conductor, and the plurality of detection capacitors are connected between the input pad and the output pad in parallel.

According to an aspect of an example embodiment, a circuit for detecting defects may include a semiconductor die including a first region and a second region, a first defect detection conductor provided in a peripheral region of the first region, a second defect detection conductor provided in a peripheral region of the second region, an input pad connected to a first end of the first defect detection conductor and a first end of the second defect detection conductor, an output pad connected to a second end of the first defect detection conductor and a second end of the second defect detection conductor, a first defect detection assembly connected to the first defect detection conductor and configured to detect a defect of the first defect detection conductor, a second defect detection assembly connected to the second defect detection conductor and configured to detect a defect of the second defect detection conductor, and a controller configured to control the first defect detection assembly and the second defect detection assembly, where the first defect detection assembly includes a first reference voltage supply, a first reference capacitor, a first switching assembly, and a plurality of first detection capacitors, the first switching assembly is configured to connect the first reference capacitor to one of the first reference voltage supply, a position adjacent to the input pad of the first defect detection conductor, and a position adjacent to the output pad of the first defect detection conductor, the second defect detection assembly includes a second reference voltage supply, a second reference capacitor, a second switching assembly, and a plurality of second detection capacitors, and the second switching assembly is configured to connect the second reference capacitor to one of the second reference voltage supply, a position adjacent to the output pad of the second defect detection conductor, and a position adjacent to the output pad of the second defect detection conductor.

According to an aspect of an example embodiment, a circuit for detecting defects may include a defect detection conductor provided on a peripheral region of a semiconductor die, an input pad connected to a first end of the defect detection conductor, an output pad connected to a second end of the defect detection conductor, a defect detection assembly connected to the defect detection conductor and configured to detect a defect of the defect detection conductor, and a controller configured to control operations of the defect detection assembly, where the defect detection assembly includes a reference voltage supply, a reference capacitor, a switching assembly, a plurality of detection capacitors are connected to the defect detection conductor in parallel, the switching assembly includes a first switch configured to connect the reference capacitor to the reference voltage supply and a second switch configured to connect the reference capacitor to a position adjacent to the input pad of the defect detection conductor, based on the first switch being turned on and the second switch being turned off, the controller is configured to control the reference voltage supply to charge the reference capacitor, and based on the first switch being turned off and the second switch being turned on, the controller is configured to measure a voltage between the reference capacitor and at least one of the plurality of detection capacitors.

DETAILED DESCRIPTION

Hereinafter, example embodiments of the disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof will be omitted. The embodiments described herein are example embodiments, and thus, the disclosure is not limited thereto and may be realized in various other forms.

FIG.1is a diagram illustrating a process of manufacturing a semiconductor device according to one or more example embodiments of the present disclosure.

Referring toFIG.1, a process of manufacturing a semiconductor device1according to one or more example embodiments may start with manufacturing a plurality of semiconductor chips on a wafer W. For example, the plurality of semiconductor chips manufactured by a wafer W may provide a semiconductor device such as a system-on-chip (SOC), an application processor (AP), a graphics processing unit (GPU), and a memory device.

When the wafer W is fab-out, a test process2may be performed on the wafer W at a wafer level. Once the test process2is completed on the wafer level, a scribing process3may be performed on the wafer W to obtain a plurality of semiconductor chips.

Thereafter, by performing a package process4on the semiconductor chips, a plurality of semiconductor packages may be obtained. The plurality of semiconductor packages may be manufactured by a process of mounting at least one semiconductor chip on a package substrate, and a process of connecting the package substrate and the semiconductor chip using a wire.

When the package process4is completed and the plurality of semiconductor packages are manufactured, a test process5may be performed on the plurality of semiconductor packages. In the test process5on the package level, in addition to a process of identifying whether a normal operation is performed by applying an electrical signal, a test process of applying stress to the semiconductor package by applying a high voltage to the semiconductor package or exposing the semiconductor package to a test environment of target temperature or target humidity to initially eliminate potential defects in the semiconductor package may be performed.

External stimuli such as high temperature, high pressure, and high humidity may be applied to the semiconductor chip while going through a series of processes, and accordingly, defects may occur in the semiconductor chip. For example, cracks may occur in the periphery of the semiconductor chip, or cracks may occur in the coupling portion between the cell region and the peripheral circuit region of the semiconductor chip. Accordingly, an operation of maintaining reliability of the semiconductor chip by detecting defects in the semiconductor chip in advance may be performed.

FIGS.2and3are diagrams illustrating a semiconductor device including a circuit for detecting defects according to one or more example embodiments of the present disclosure.

First, referring toFIG.2, a semiconductor device100according to one or more example embodiments may include a semiconductor die110and a circuit for detecting defects. The circuit for detecting defects may include a defect detection conductor120, an input pad130, an output pad140, and a defect detection assembly150.

According to one or more example embodiments, the defect detection conductor120may be disposed on the peripheral region of the semiconductor die110. The input pad130and the output pad140may be disposed on the same surface of the semiconductor die110, and the input pad130and the output pad140may be disposed in the first direction (the X-axis direction inFIG.2) at a distance. The input pad130may be connected to one end of the defect detection conductor120, and the output pad140may be connected to the other end of the defect detection conductor120. The input pad130and the output pad140may be connected to a logic circuit of the semiconductor device, but the input pad130and the output pad140may be separated from the logic circuit while the circuit for detecting defects is driven.

The defect detection assembly150may include a reference voltage supply151, a reference capacitor152, a switching assembly153, and a plurality of detection capacitors154. The defect detection assembly150may be connected to the defect detection conductor120and may detect defects of the defect detection conductor120. Operations of the defect detection assembly150may be controlled by a controller.

The switching assembly153may be disposed between the input pad130and the output pad140, and the switching assembly153may connect the reference capacitor152to one or more of the reference voltage supply151and a position adjacent to the input pad130of defect detection conductor120. According to one or more example embodiments, the switching assembly153may include a first switch SW1connecting the reference capacitor152to the reference voltage supply151, and a second switch SW2connecting the reference capacitor152to a position adjacent to the input pad130of the defect detection conductor120. For example, the switching assembly153may have one of a first state in which the first switch SW1is turned on and the second switch SW2is turned off, a second state in which the second switch SW2is turned on and the first switch SW1is turned off, and a third state in which the first switch SW1and the second switch SW2are turned off.

According to one or more example embodiments, a plurality of detection capacitors154may be connected in parallel between the input pad130and the output pad140. For example, the plurality of detection capacitors154may include the first to fourth detection capacitors C1-C4. As illustrated inFIG.2, each of the plurality of detection capacitors154may be disposed at vertices of the semiconductor die110. The plurality of detection capacitors154may have different capacitance values. Also, as an example, a sum of capacitance values of the plurality of detection capacitors154may be equal to or approximate to a capacitance value of the reference capacitor152.

When cracks occur in the periphery of the semiconductor die110, the defect detection conductor120may be disconnected due to the cracks. Depending on disconnected positions, capacitor composite values of the plurality of detection capacitors154may be different. For example, when the defect detection conductor120is disconnected between the first detection capacitor C1and the second detection capacitor C2, the capacitor composite values of the plurality of detection capacitors154may be equal to or approximate to a capacitance value of the first detection capacitor C1. For example, when the defect detection conductor120is disconnected between the third detection capacitor C3and the fourth detection capacitor C4, the capacitor composite values of the plurality of detection capacitors may be equal to or approximate to a sum of capacitance values of the first to third detection capacitors C1-C3.

In the first state of the switching assembly153, the reference capacitor152may be charged by the reference voltage supply151. Thereafter, in the second state in which the switching assembly153has passed through the third state, the controller may control the defect detection assembly150to measure a measurement voltage VMat a node190at which the switching assembly153is connected to the defect detection conductor120.

According to one or more example embodiments, the capacitor composite values of the plurality of detection capacitors154may be determined depending on a position at which the defect detection conductor120is disconnected, and accordingly, the measurement voltage VMmay be determined. The controller may supply a reference voltage through the reference voltage supply151. In other words, by comparing the measurement voltage VMand the reference voltage, whether the defect detection conductor120is disconnected and the disconnection position may be detected.

Referring toFIG.3, a semiconductor device200according to one or more example embodiments may include a semiconductor die210and a circuit for detecting defects. The circuit for detecting defects may include a defect detection conductor220, an input pad230, an output pad240, and a defect detection assembly250. The defect detection assembly250may include a reference voltage supply251, a reference capacitor252, a switching assembly253, and a plurality of detection capacitors254.

As compared to the semiconductor device100inFIG.2, in the semiconductor device200inFIG.3, the plurality of detection capacitors and the switching assembly may be configured differently, and specific example embodiments may be similar to the examples described with reference toFIG.2.

For example, according to one or more example embodiments, the plurality of detection capacitors254may include first to fourth detection capacitors C1-C4, and the plurality of detection capacitors254may be disposed at the same distance from each other.

The switching assembly253may connect the reference capacitor252to one or more of the reference voltage supply251, a position adjacent to the input pad230of the defect detection conductor220, and a position adjacent to the output pad240of the defect detection conductor220. According to one or more example embodiments, the switching assembly253may include a first switch SW1connecting the reference capacitor252to the reference voltage supply251, a second switch SW2connecting the reference capacitor252to the position adjacent to the input pad230of the defect detection conductor220, and a third switch SW3connecting the reference capacitor252to a position adjacent to the output pad240of the defect detection conductor220. As compared to the switching assembly153inFIG.2, the switching assembly253inFIG.3may further include the third switch SW3.

For example, the switching assembly253may have one of a first state in which the first switch SW1is turned on and the second switch SW2and the third switch SW3are turned off, a second state in which the second switch SW2is turned on and the first switch SW1and the third switch SW3are turned off, a third state in which the third switch SW3is turned on and the first switch SW1and the second switch SW2are turned off, and a fourth state in which the first to third switches SW1-SW3are turned off.

In the first state of the switching assembly253, the reference capacitor252may be charged by the reference voltage supply251. Thereafter, in the second and third states after the switching assembly253goes through the fourth state, the controller may control the defect detection assembly250to measure a measurement voltage VMat a node at which the switching assembly253is connected to the defect detection conductor220. Specifically, in the second state of the switching assembly253, the controller may control the defect detection assembly250to measure the first measured voltage VM1at a node290at which the second switch SW2is connected to the defect detection conductor220. In the third state of the switching assembly253, the controller may control the defect detection assembly250to measure the second measured voltage VM2at a node291at which the third switch SW3is connected to the defect detection conductor220.

As illustrated inFIG.3, the defect detection assembly250may determine whether the defect detection conductor220is disconnected and the disconnection position from the input pad230in the second state, and may determine whether the defect detection conductor220is disconnected and the disconnection position from the output pad240in the third state. In other words, when the defect detection conductor220is disconnected in two positions, the defect detection assembly250may detect both disconnection positions, and accordingly, detecting accuracy may be improved as compared to the defect detection assembly150illustrated inFIG.2.

FIGS.4and5are diagrams illustrating a semiconductor device including a circuit for detecting defects according to one or more example embodiments of the present disclosure.

Referring toFIG.4, a semiconductor device300according to one or more example embodiments may include a semiconductor die310and a circuit for detecting defects. The circuit for detecting defects may include a first defect detection conductor320, a second defect detection conductor330, an input pad340, an output pad350, a first defect detection assembly360, and a second defect detection assembly370.

According to one or more example embodiments, the semiconductor die310may be divided into a first region311and a second region312. For example, the first region311and the second region312may extend in the first direction (the X-axis direction inFIG.4) parallel to an upper surface of the semiconductor die310, and may contact each other in a second direction parallel to an upper surface of the semiconductor die310and perpendicular to the first direction (the Y-axis direction inFIG.4). However, the partition and differences between the first region311and the second region312are not limited to the above example. The first defect detection conductor320may be disposed in a peripheral region of the first region311, and the second defect detection conductor330may be disposed on a peripheral region of the second region312. The input pad340and the output pad350may be disposed on the same surface of the semiconductor die310, and the input pad340and the output pad350may be disposed in the first direction (the X-axis direction inFIG.4) at a distance. The input pad340may be connected to one end of the first defect detection conductor320and one end of the second defect detection conductor330, and the output pad350may be connected to the other end of first defect detection conductor320and the other end of second defect detection conductor330.

The first defect detection assembly360may include a first reference voltage supply361, a first reference capacitor362, a first switching assembly363, and a plurality of first detection capacitors364. The first defect detection assembly360may be connected to the first defect detection conductor320and may detect defects of the first defect detection conductor320. Operations of the first defect detection assembly360may be controlled by a controller.

The first switching assembly363may connect the first reference capacitor362to one or more of the first reference voltage supply361and a position adjacent to the input pad340of the first defect detection conductor320. According to one or more example embodiments illustrated inFIG.4, the first switching assembly363may include a first switch SW1connecting the first reference capacitor362to the first reference voltage supply361, and a second switch SW2connecting the first reference capacitor362to a position adjacent to the input pad340of the first defect detection conductor320. For example, the first switching assembly363may have one of a first state in which the first switch SW1is turned on and the second switch SW2is turned off, a second state in which the second switch SW2is turned on and the first switch SW1is turned off, and a third state in which the first switch SW1and the second switch SW2are turned off.

According to one or more example embodiments, the plurality of first detection capacitors364may be connected in parallel between the input pad340and the output pad350. For example, the plurality of first detection capacitors364may include the first to fourth detection capacitors C1-C4. As illustrated inFIG.4, the plurality of first detection capacitors364may be disposed on vertices of the first region311of the semiconductor die310. The plurality of first detection capacitors364may have different capacitance values. Also, as an example, a sum of capacitance values of the plurality of first detection capacitors364may be equal to or approximate to a capacitance value of the first reference capacitor362.

When cracks occur in the periphery of the first region311of the semiconductor die310, the first defect detection conductor320may be disconnected due to the cracks. Depending on disconnected positions, capacitor composite values of the first detection capacitors364may be different. For example, when the first defect detection conductor320is disconnected between the first detection capacitor C1and the second detection capacitor C2, capacitor composite values of the plurality of first detection capacitors364may be equal to or approximate to a capacitance value of the first detection capacitor C1. For example, when the first defect detection conductor320is disconnected between the third detection capacitor C3and the fourth detection capacitor C4, capacitor composite values of the plurality of first detection capacitors364may be equal to or close to a sum of capacitance values of the first to third detection capacitors C1-C3.

As illustrated inFIG.4, in the first state of the first switching assembly363, the first reference capacitor362may be charged by the first reference voltage supply361. Thereafter, in the second state after the first switching assembly363goes through the third state, the controller may control the first defect detection assembly360to measure a first measured voltage VM1at a node390at which the first switching assembly363is connected to the first defect detection conductor320.

The second defect detection assembly370may include a second reference voltage supply371, a second reference capacitor372, a second switching assembly373, and a plurality of second detection capacitors374. The second defect detection assembly370may be connected to the second defect detection conductor330and may detect defects of the second defect detection conductor330. Operations of the second defect detection assembly370may be controlled by a controller.

The second switching assembly373may connect the second reference capacitor372to one or more of the second reference voltage supply371and a position adjacent to the input pad340of the second defect detection conductor330. According to one or more example embodiments, the second switching assembly373may include a third switch SW3connecting the second reference capacitor372to the second reference voltage supply371, and a fourth switch SW4connecting the second reference capacitor372to a position adjacent to the input pad340of the second defect detection conductor330. For example, the second switching assembly373may have a fourth state in which the third switch SW3is turned on and the fourth switch SW4is turned off, a fifth state in which the fourth switch SW4is turned on and the third switch SW3is turned off, and a sixth state in which the third switch SW3and the fourth switch SW4are turned off.

According to one or more example embodiments, the plurality of second detection capacitors374may be connected in parallel between the input pad340and the output pad350. As an example, the plurality of second detection capacitors374may include fifth to eighth detection capacitors C5-C8. As illustrated inFIG.4, the plurality of second detection capacitors374may be disposed at vertices of a second region312of the semiconductor die310. The plurality of second detection capacitors374may have different capacitance values. Also, as an example, a sum of capacitance values of the plurality of second detection capacitors374may be equal to or approximate to a capacitance value of the second reference capacitor372.

When cracks occur in the periphery of the second region312of the semiconductor die310, the second defect detection conductor330may be disconnected due to the cracks. Depending on the disconnected position, capacitor composite values of the second detection capacitors374may be different. For example, when the second defect detection conductor330is disconnected between the fifth detection capacitor C5and the sixth detection capacitor C6, capacitor composite values of the plurality of second detection capacitors374may be equal to or approximate to a capacitance value of the fifth detection capacitor C5. For example, when the second defect detection conductor330is disconnected between the seventh detection capacitor C7and the eighth detection capacitor C8, capacitor composite values of the plurality of second detection capacitors374may be equal to or close to a sum of capacitance values of the fifth to seventh detection capacitors C5-C7.

As illustrated inFIG.4, in the fourth state of the second switching assembly373, the second reference capacitor372may be charged by the second reference voltage supply371. Thereafter, in the fifth state after the second switching assembly373has passed through the sixth state, the controller may control the second defect detection assembly370to measure a second measured voltage VM2at a node391at which the second switching assembly373is connected to the second defect detection conductor330.

A magnitude of voltage supplied by the first reference voltage supply361may be equal to or different from a magnitude of voltage supplied by the second reference voltage supply371. A capacitance value of the first reference capacitor362may be equal to or different from a capacitance value of second reference capacitor372. Also, capacitance values of the plurality of first detection capacitors364may be equal to or different from capacitance values of the plurality of second detection capacitors374, respectively. The first and second defect detection assemblies360and370may operate simultaneously, and only one of the first and second defect detection assemblies360and370may operate.

According to one or more example embodiments, capacitor composite values of the plurality of first and second detection capacitors364and374may be determined depending on a position in which each of the first and second defect detection conductors320and330is disconnected, and accordingly, first and second measured voltages VM1and VM2may be determined. The controller may supply a first reference voltage through the first reference voltage supply361and a second reference voltage through the second reference voltage supply371. In other words, by comparing the first measured voltage VM1and the first reference voltage, whether the first defect detection conductor320is disconnected and a disconnection position may be detected. By comparing the second measured voltage VM2and the second reference voltage, whether the second defect detection conductor330is disconnected and a disconnection position may be detected.

As compared to the semiconductor device100inFIG.2, in the semiconductor device300inFIG.4, the second defect detection conductor330and the second defect detection assembly370may be configured differently. The circuit for detecting defects of the semiconductor device100according to one or more example embodiments inFIG.2may detect defects in the periphery of the semiconductor die110, and the circuit for detecting defects may detect defects in the periphery of the semiconductor die310and in the region in which the first region311and the second region312contact each other. Differently from the example embodiment illustrated inFIG.4, the semiconductor device300may not include at least one of the fourth detection capacitor C4and the fifth detection capacitor C5.

As illustrated inFIG.4, the first defect detection assembly360may determine whether the defect detection conductor320is disconnected and a disconnection position from the input pad340in the second state, and the second defect detection assembly370may determine whether the defect detection conductor330is disconnected and a disconnection position from the input pad340in the fifth state. In other words, when each of the first and second defect detection conductors320and330is disconnected in one position, the first defect detection assembly360may detect a disconnection position of the first defect detection conductor320, and the second defect detection assembly370may detect a disconnection position of the second defect detection conductor330. Accordingly, accuracy of detecting defects of the semiconductor device300inFIG.4may be improved as compared to that of the semiconductor device100inFIG.2.

Referring toFIG.5, a semiconductor device400according to one or more example embodiments may include a semiconductor die410and a circuit for detecting defects. The circuit for detecting defects may include a first defect detection conductor420, a second defect detection conductor430, an input pad440, an output pad450, a first defect detection assembly460, and a second defect detection assembly470. The first defect detection assembly460may include a first reference voltage supply461, a first reference capacitor462, a first switching assembly463, and a plurality of first detection capacitors464. The second defect detection assembly470may include a second reference voltage supply471, a second reference capacitor472, a second switching assembly473, and a plurality of second detection capacitors474.

As compared to the semiconductor device300inFIG.4, in the semiconductor device400inFIG.5, the arrangement of the plurality of first and second detection capacitors464and474and the configuration of the first and second switching assemblies463and473may be different, and specific example embodiments may be similar to the examples described with reference toFIG.4.

According to one or more example embodiments, the plurality of first detection capacitors464may include first to fourth detection capacitors C11-C14, and the plurality of second detection capacitors474may include fifth to eighth detection capacitors C21-C24. For example, the plurality of first and second detection capacitors464and474may be disposed at the same distance from each other.

The first switching assembly463may connect the first reference capacitor462to one or more of the first reference voltage supply461, a position adjacent to the input pad440of the first defect detection conductor420, and a position adjacent to the output pad450of the first defect detection conductor420. According to one or more example embodiments, the first switching assembly463may include a first switch SW1connecting the first reference capacitor462to the first reference voltage supply461, a second switch SW2connecting the first reference capacitor462to a position adjacent to the input pad440of the first defect detection conductor420, and a third switch SW3connecting the first reference capacitor462to a position adjacent to the output pad450of the first defect detection conductor420.

The second switching assembly473may connect the second reference capacitor472to one or more of the second reference voltage supply421, a position adjacent to the input pad440of the second defect detection conductor430, and a position adjacent to the output pad450of the second defect detection conductor430. According to one or more example embodiments, the second switching assembly473may include a fourth switch SW4connecting the second reference capacitor472to the second reference voltage supply471, a fifth switch SW5connecting the second reference capacitor472to a position adjacent to the input pad440of the second defect detection conductor430, and a sixth switch SW6connecting the second reference capacitor472to a position adjacent to the output pad450of the second defect detection conductor430.

For example, the first switching assembly463may have a first state in which the first switch SW1is turned on and the second switch SW2and the third switch SW3are turned off, a second state in which the second switch SW2is turned on and the first switch SW1and the third switch SW3are turned off, a third state in which the third switch SW3is turned on and the first switch SW1and the second switch SW2are turned off, and a fourth state in which the first to third switches SW1-SW3are turned off. The second switching assembly473may have a fifth state in which the fourth switch SW4is turned on and the fifth switch SW5and the sixth switch SW6are turned off, a sixth state in which the fifth switch SW5is turned on and the fourth switch SW4and the sixth switch SW6are turned off, a seventh state in which the sixth switch SW6is turned on and the fourth switch SW4and the fifth switch SW5are turned off, and an eighth state in which the fourth sixth switches SW4-SW6are turned off.

Specifically, in the second state of the first switching assembly463, the controller may control the first defect detection assembly460to measure a first measured voltage VM1at a node490at which the second switch SW2is connected to the first defect detection conductor420. In the third state of the first switching assembly463, the controller may control the first defect detection assembly460to measure a second measured voltage VM2at a node491at which the third switch SW3is connected to the first defect detection conductor420. Also, in the sixth state of the second switching assembly473, the controller may control the second defect detection assembly470to measure a third measured voltage VM3at a node492at which the fifth switch SW5is connected to the second defect detection conductor430. In the seventh state of the second switching assembly473, the controller may control the second defect detection assembly470to measure a fourth measured voltage VM4at a node493at which the sixth switch SW6is connected to the second defect detection conductor430.

As compared with the first and second switching assemblies363and373inFIG.4, the first and second switching assemblies463and473inFIG.5may further include third and sixth switches SW3and SW6. As illustrated inFIG.5, the first and second defect detection assemblies460and470may determine whether the first and second defect detection conductors420and430are disconnected and disconnection positions from the input pad440in the second and sixth states, and whether the first and second defect detection conductors420and430are disconnected and the disconnection positions may be determined from the output pad450in the third and seventh states. In other words, when the first and second defect detection conductors420and430are disconnected in two positions, respectively, the first and second defect detection assemblies460and470may detect both the disconnection positions, such that detecting accuracy may be improved as compared to the first and second defect detection assemblies360and370illustrated inFIG.4.

FIGS.6A to6Care diagrams illustrating cross-sections of a semiconductor device illustrated inFIG.5taken along line I-I′ according to one or more example embodiments of the present disclosure.

Referring toFIGS.6A to6C, the semiconductor device400may be divided into an uppermost wiring region WIRING AREA, a cell region CELL, and a peripheral circuit region PERI, and the uppermost wiring region WIRING AREA, the cell region CELL, and the peripheral circuit region PERI may be stacked in the first direction (the Z-axis direction). The arrangement of the uppermost wiring region WIRING AREA, the cell region CELL, and the peripheral circuit region PERI is not limited thereto.

First, referring toFIG.6A, the cell region CELL of the semiconductor device400may include a cell array region CELL ARRAY and a cell contact region CELL CONTACT. In example embodiments, the cell contact region CELL CONTACT may be stacked below the cell array region CELL ARRAY in the Z-axis direction. For example, in the cell array region CELL ARRAY, cell channel structures, wiring patterns432and cell contacts435may be disposed. For example, in the cell contact region CELL CONTACT, via patterns431, the wiring patterns432and bonding pads434may be disposed. The peripheral circuit region PERI of the semiconductor device400may include a plurality of guard-band devices GB formed on the substrate433, the via patterns431connected to the plurality of guard-band devices GB, and the wiring patterns432.

In example embodiments, the uppermost wiring region WIRING AREA may be stacked on the cell array region CELL ARRAY in the Z-axis direction. In the uppermost wiring region WIRING AREA, at least one wiring pattern and the via patterns431may be disposed. Referring toFIG.6A, the cell region CELL and the peripheral circuit region PERI may be bonded to each other through the bonding pads434. As in example embodiments illustrated inFIG.6A, each of the cell region CELL and the peripheral circuit region PERI may include a plurality of bonding pad pairs, each of which has two bonding pads434adjacent to each other and disposed at a distance from each other. However, the number of bonding pads included in each of the plurality of bonding pad pairs may not be limited thereto, and for example, the bonding pads may have one or three or more bonding pads.

For example, bonding pads434may be connected through the via patterns431and the wiring patterns432. Also, according to one or more example embodiments, each of the plurality of bonding pad pairs included in the cell region CELL and the peripheral circuit region PERI may connect the wiring patterns432of the cell region CELL to the wiring patterns432of the peripheral circuit region PERI. The plurality of bonding pad pairs, the via patterns431and the wiring patterns432of the cell region CELL and the via patterns431and the wiring patterns432of the peripheral circuit region PERI may be provided as a second defect detection conductor430.

When cracks occur in the semiconductor device400, at least one of the via patterns431, the wiring patterns432and the bonding pads434may be disconnected. In other words, referring toFIG.5as an example, the second defect detection conductor430may be disconnected. The controller may detect disconnection and a disconnection position of the second defect detection conductor430through the third or fourth measured voltage VM3and VM4. Accordingly, reliability of the semiconductor device400may be improved by detecting defects in the via patterns431, the wiring patterns432, and/or the bonding pads434of the semiconductor device400.

Thereafter, referring toFIG.6B, the cell region CELL and the peripheral circuit region PERI of the semiconductor device400may be bonded to each other through the bonding pads434. Each of the cell region CELL and the peripheral circuit region PERI may include a plurality of bonding pads434disposed at a distance from each other. However, the number of bonding pads included in each of the plurality of bonding pad pairs may not be limited thereto, and for example, the bonding pads may have one or three or more bonding pads.

Also, the bonding pads434may be connected through the via patterns431and the wiring patterns432. For example, the wiring patterns432of the cell region CELL may be disposed to be shifted from the wiring patterns432of the peripheral circuit region PERI, and specifically, the wiring patterns432of the cell region CELL may be disposed to be shifted from the wiring patterns432of the peripheral circuit region PERI with respect to two adjacent bonding pads434. The plurality of bonding pads434, the via patterns431and the wiring patterns432of the cell region CELL and the via patterns431and the wiring patterns432of the peripheral circuit region PERI may be provided as a second defect detection conductor430. Other specific example embodiments inFIG.6Bmay be similar toFIG.6A.

As illustrated inFIG.6B, when cracks occur in the semiconductor device400, at least one of the via patterns431, the wiring patterns432and the bonding pads434may be disconnected. In other words, the second defect detection conductor430in example embodiments illustrated inFIG.5may be disconnected. The controller may detect disconnection and disconnection position of the second defect detection conductor430through the third or fourth measured voltage VM3and VM4. Accordingly, reliability of the semiconductor device400may be improved by detecting defects and positions of defects in the via patterns431, the wiring patterns432, and/or the bonding pads434of the semiconductor device400.

Thereafter, referring toFIG.6C, the semiconductor device400may include a cell region CELL and a peripheral circuit region PERI. As compared toFIG.6A, the semiconductor device400may be different in that the uppermost wiring region include one wiring pattern432. For example, a wiring pattern432may be configured in the cell region CELL or the peripheral circuit region PERI. Other specific example embodiments inFIG.6Cmay be similar toFIG.6A.

As illustrated inFIG.6C, when cracks occur in the semiconductor device400, connection of the wiring pattern432may be disconnected. In other words, the second defect detection conductor430in example embodiments illustrated inFIG.5may be disconnected. The controller may detect disconnection and disconnection position of the second defect detection conductor430through the third or fourth measured voltage VM3and VM4. Accordingly, as compared to the semiconductor device400illustrated inFIG.6A, the semiconductor device400illustrated inFIG.6Cmay detect defects and positions of defects in the entire period in which the wiring pattern432in the cell region CELL is disposed. In other words, accuracy of detecting defects inFIG.6Cmay be relatively high.

FIG.7is a diagram illustrating a circuit for detecting defects according to one or more example embodiments of the present disclosure.FIG.8is a diagram illustrating a ratio of measured voltage to reference voltage depending on a position of defects according to one or more example embodiments of the present disclosure.

Referring toFIG.7, the circuit500for detecting defects may include a defect detection conductor510, an input pad520, an output pad530, and a defect detection assembly. The defect detection assembly may include a reference voltage supply540, a reference capacitor550, a switching assembly560, and a plurality of detection capacitors570.

The switching assembly560according to one or more example embodiments may be connected to a 0th position X0of the defect detection conductor510. The reference capacitor550may be connected to one or more of the reference voltage supply540and a position adjacent to the input pad520of the defect detection conductor510. Specifically, the switching assembly560may include a first switch SW1connecting the reference capacitor550to the reference voltage supply540, and a second switch SW2connecting the reference capacitor550to a position adjacent to the input pad520of the defect detection conductor510.

The plurality of detection capacitors570according to one or more example embodiments may include first to fourth detection capacitors C1-C4. The first to fourth detection capacitors C1-C4may be connected in parallel between the input pad520and the output pad530.

The first detection capacitor C1may be connected to the first position X1of the defect detection conductor510, the second detection capacitor C2may be connected to the second position X2, the third detection capacitor C3may be connected to the third position X3of the defect detection conductor510, and the fourth detection capacitor C4may be connected to the fourth position X4of the defect detection conductor510. For example, as illustrated inFIG.7, the first to fourth detection capacitors C1-C4may be disposed and spaced apart at the same distance from each other. In other words, the first position X1to the fourth position X4may be disposed and spaced apart on the defect detection conductor510at the same distance from each other.

FIG.8is a diagram illustrating a ratio of measured voltage to reference voltage according to positions of defects according to one or more example embodiments illustrated inFIG.7. Positions X of defects may correspond to the 0th position X0to the fourth position X4of the defect detection conductor510. The measurement voltage VMmay be measured at a node in the 0th position X0. The reference voltage may be supplied by the reference voltage supply540to the reference capacitor550.

The reference capacitor550may be charged by turning on the first switch SW1and connecting the reference capacitor550to the reference voltage supply540. Thereafter, by turning off the first switch SW1and turning on the second switch SW2, the reference capacitor550may be connected to the plurality of detection capacitors570. In this case, capacitor composite values of the plurality of detection capacitors570may be different depending on the positions X of defects, and the measurement voltages VMmay be different depending on the positions of defects.

For example, the first to fourth detection capacitors C1-C4may have different capacitance values. Specifically, a sum of capacitance values of the first to fourth detection capacitors C1-C4may be equal to a capacitance value of the reference capacitor550. When the capacitance value of the reference capacitor550is CSTD, a capacitance value of the first detection capacitor C1may be

a capacitance value of the second detection capacitor C2may be

a capacitance value of the third detection capacitor C3may be

and a capacitance value of the fourth detection capacitor C4may be

FIG.8may correspond to the example in which a capacitance value of each of the first to fourth detection capacitors C1-C4may be sufficiently larger than a capacitance value of defect detection conductor510. Also,FIG.8may also illustrate a ratio S of the measurement voltage VMto the reference voltage according to the positions X of defects.

For example, the ratio S of the measurement voltage VMto the reference voltage in each of the first to fourth positions X1-X4may decrease by 0.1, but example embodiments thereof is not limited thereto. When the ratio S of the measurement voltage VMto the reference voltage is 0.7 or more and 0.8 or less, the controller may recognize that defects may be present in the defect detection conductor510, and that the positions X of defects may be between the first position X1and the second position X2. For example, when the ratio S of the measurement voltage VMto the reference voltage is 0.5 or more and 0.6 or less, the controller may recognize that defects may be present in the defect detection conductor510, and the positions X of defects may be between the third position X3and the fourth position X4. For example, when the ratio S of the measurement voltage VMto the reference voltage is less than 0.5, the controller may recognize that no defects are present in the defect detection conductor510.

By designing the number of detection capacitors included in the plurality of detection capacitors570and a capacitance value of each detection capacitor, the number of defect testing positions of the defect detection conductor510and the amount by which the ratio S of the measurement voltage VMto the reference voltage decreases in each defect testing position may be adjusted. Accordingly, accuracy in detecting positions of defects may be improved through the measurement voltage VM.

FIG.9is a diagram illustrating a circuit for detecting defects according to one or more example embodiments of the present disclosure.FIG.10is a diagram illustrating a ratio of measured voltage and reference voltage depending on a position of defects according to one or more example embodiments of the present disclosure.

Referring toFIG.9, the circuit600for detecting defects may include a defect detection conductor610, an input pad620, an output pad630, and a defect detection assembly. The input pad620may be connected to one end of the defect detection conductor610, and the output pad630may be connected to the other end of the defect detection conductor610. The defect detection assembly may include a reference voltage supply640, a reference capacitor650, a switching assembly660, and a plurality of detection capacitors670. As compared to the circuit500for detecting defects inFIG.7, the plurality of detection capacitors670may be configured differently, and specific example embodiments may be similar to the examples described with reference toFIG.7.

The plurality of detection capacitors670according to one or more example embodiments may include first to Nth detection capacitors C1-CN. The first to Nth detection capacitors C1-CN may be connected in parallel between the input pad620and the output pad630.

The first detection capacitor C1may be connected to the first position X1of the defect detection conductor610, the second detection capacitor C2is connected to the second position X2of the defect detection conductor610, the Nth−1 detection capacitor CN−1 may be connected to the Nth−1 position XN−1 of the defect detection conductor610, and the Nth detection capacitor CN may be connected to the Nth position XN of the defect detection conductor610. As illustrated inFIG.9, for example, the first to Nth detection capacitors C1-CN may be disposed and spaced apart at the same distance from each other. In other words, the first position X1to the Nth position XN may be disposed and spaced apart on the defect detection conductor610at the same distance from each other.

FIG.10is a diagram illustrating a ratio of measured voltage to reference voltage according to positions of defects according to one or more example embodiments illustrated inFIG.9. The positions X of defects may correspond to a position between the 0th position X0and the Nth position XN of the defect detection conductor610. The measurement voltage VMmay be measured at a node at the 0th position X0. The reference voltage may be supplied by the reference voltage supply640to the reference capacitor650.

For example, each of the first to Nth detection capacitors C1-CN may have different capacitance values. A sum of capacitance values of the first to Nth detection capacitors C1-CN may be equal to a capacitance value of the reference capacitor650. In this case, each of the first to Nth detection capacitors C1-CN may satisfy a capacitance value CSTDof the reference capacitor650and Equation (1).

For example, a1of the first detection capacitor C1may satisfy Equation (2), and ak of the second to Nth detection capacitors C2-CN may satisfy Equation (3).

R may correspond to a ratio S value of the measurement voltage VMto the reference voltage at first position X1. For example, R may correspond to a value divided by a sum of the capacitance value CSTDof the reference capacitor650and a capacitance value of the first detection capacitor C1. In an example, R may correspond to 0.9, 0.8, or 0.7, but example embodiments thereof are not limited thereto. a may correspond to the amount by which the ratio S of the measurement voltage VMto the reference voltage decreases when a disconnection occurs between adjacent positions among the first position to the Nth position X1-XN. For example, α may be 0.1 or 0.2, but example embodiments thereof are not limited thereto.

By designing the number of detection capacitors included in the plurality of detection capacitors670and a capacitance value of each detection capacitor, the number of defect testing positions of the defect detection conductor610and the amount by which the ratio S of the measurement voltage VMto the reference voltage decreases at each defect testing position. Accordingly, accuracy in detecting positions of defects may be improved through the measurement voltage VM.

FIG.11is a diagram illustrating a circuit for detecting defects according to one or more example embodiments of the present disclosure.

Referring toFIG.11, the circuit700for detecting defects may include a defect detection conductor710, an input pad720, an output pad730, a defect detection assembly, a controller780, a comparator785, and a storage790. The input pad720may be connected to one end of the defect detection conductor710, and the output pad730may be connected to the other end of the defect detection conductor710. The defect detection assembly may include a reference voltage supply740, a reference capacitor750, a switching assembly760, and a plurality of detection capacitors770.

In example embodiments, the controller780may control the defect detection assembly to measure the measurement voltage VMat a node799at which the switching assembly760is connected to the defect detection conductor710. Specifically, the controller780may control the switching assembly760such that the reference capacitor750may be connected to the reference voltage supply740and may be charged with the reference voltage. Thereafter, the switching assembly760may be controlled such that the reference capacitor750charged with the reference voltage may be connected to the plurality of detection capacitors770. In example embodiments, the capacitor composite value of the plurality of detection capacitors770may be determined according to the positions of defects of the defect detection conductor710. Accordingly, the presence of defects and positions of defects may be detected using the measurement voltage VM.

The comparator785may compare the measurement voltage VMand a comparison reference voltage VREFthrough the controller780and may output the comparison result. A minimum value of the comparison reference voltage VREFmay correspond to the measurement voltage VMwhen the reference capacitor750is connected to the plurality of detection capacitors770when there are no defects in the defect detection conductor710. A maximum value of the comparison reference voltage VREFmay correspond to the reference voltage supplied by the reference voltage supply740. The storage790may convert the comparison result of the comparator785into digital information through the controller780, may store the information, and may output the information.

FIG.12is a diagram illustrating a circuit for detecting defects according to one or more example embodiments of the present disclosure.FIG.13is a diagram illustrating digital output signals for signals input to a circuit for detecting defects and measurement results according to one or more example embodiments of the present disclosure.

Referring toFIG.12, a circuit800for detecting defects may include a defect detection conductor810, an input control circuit820, an output control circuit830, a defect detection assembly, a controller, a comparator885, and a storage890.

The input control circuit820may be connected to one end of the defect detection conductor810, and the output control circuit830may be connected to the other end of the defect detection conductor810. The input signal IN may be output from an input pad through a logic circuit and may input into the input control circuit820. The input control circuit820may transmit the input signal IN to the defect detection conductor810, or may electrically separate the input pad from the defect detection conductor810. The output signal OUT may be output from the output pad through a logic circuit and may input into the output control circuit830. The output control circuit830may transmit the output signal OUT to the defect detection conductor810, or the output pad may be electrically separated from the defect detection conductor810.

The defect detection assembly may include a reference voltage supply840, a reference capacitor850, a switching assembly860, and a plurality of detection capacitors870. In example embodiments, the controller may control the circuit for detecting defects through the signals inFIG.13. The controller may supply a control signal to the circuit800for detecting defects, and an output signal of the circuit800for detecting defects may be input to the controller.

The switching assembly860may be connected to a position adjacent to the input control circuit820of the defect detection conductor810, and in this case, a low level voltage may be applied to the G2node. For example, the low level voltage may be 0V. At a first time point t1, a signal of the output control circuit830may change from a high level to a low level, and both ends of the defect detection conductor810may be separated. A separation state of the defect detection conductor810may be maintained until a twelfth time point t12. At a second time point t2, a D signal of the switching assembly860may change from a low level to a high level, and a voltage of G and G1nodes may be increased from 0V to a constant voltage. In this case, a constant voltage of the G and G1nodes may be a voltage amplified through each of lever shifters (L/S) connected to G and G1. For example, a constant voltage may be 3V to 3.5V. In this case, the reference capacitor850may be connected to ground 0V such that the amount of residual charge in the reference capacitor850may be dissipated. At a third time point t3, the D signal of the switching assembly860may change from a high level to a low level, and a voltage of the G and G1nodes may be reduced to 0V. In this case, the measurement voltage VMmay be 0V.

At a fourth time point t4, a Pn signal of the switching assembly860and a A2nsignal of the comparator885may change from a high level to a low level. For example, a high level value of an A2nsignal may be a reference voltage supplied by the reference voltage supply840, and a low level value of an A2nsignal may be 0V. In this case, the reference capacitor850may be connected to the reference voltage supply840by the Pn signal. Also, the comparator885may be activated by the A2nsignal, and an activation state may be maintained until a tenth time point t10. At a fifth time point t5, the Pn signal may change from a low level to a high level, and connection between the reference capacitor850and the reference voltage supply840may be disconnected.

At a sixth time point t6, a voltage of the G and G1nodes may be increased from 0V to a constant voltage. For example, the constant voltage may be 3V to 3.5V. In this case, the reference capacitor850may be connected to the plurality of detection capacitors870. In other words, the measurement voltage VMmay be applied to an input node MON of the comparator885, and the measurement voltage VMmay be input to the comparator885, such that the comparator885may output a comparison result.

At a seventh time point t7, an Sn signal of the storage890may change from a high level to a low level, and the low level may be maintained until an eighth time point t8. A C signal of the storage890may have a high level period between the seventh time point t7and the eighth time point t8, and during the high level period of the C signal, during the high level period of the C signal, the0th delay flip-flop (DFF)89A may receive a comparison result of the comparator885and may be converted to a digital signal.

Between the eighth time point t8and the ninth time point t9, the C signal of the storage890may have a high level period. The high level period of the C signal may be included in a period in which one of the X1signals of the first DFF891to the Xn signal of the Nth DFF89N may have a low level.

In example embodiments, the Sn signal of the storage890may change from a low level to a high level at the eighth time point t8. During the eighth time point t8to the ninth time point t9, a digital signal may be stored in one of the first DFF891to the Nth DFF89N. For example, at the eighth time point t8, among the first DFF891to the Nth DFF89N, the X1signal of first DFF891may change from a high level to a low level, and the low level of X1of the first DFF891may change from a low level to a high level before the ninth time point t9. In this case, the X2to Xn signals of the remaining DFFs may maintain a high level other than the X1signal of the first DFF891.

In a portion of periods of the time in which the X1signal of the first DFF891is maintained at a low level, the C signal of the storage890may have a high level period. At the time point at which the C signal changes to high level, the digital signal stored in the0th DFF89A may be transferred to the first DFF891and may be stored, and thereafter, the X1signal may be changed to a high level to maintain storage of the digital signal. Also, from the time point at which the C signal changes to a high level, the first DFF891may output the first output signal Out_1for the stored digital signal.

After the X1signal of the first DFF891changes from a low level to a high level, the above operation may be repeated by changing the comparison reference voltage VREF. Specifically, the X2to Xn signals of the second to Nth DFFs may sequentially have a low level period. When the C signal of the storage890changes from a low level to a high level in each low level period of the X2, digital signals may be stored in the second to Nth DFF, and the second to the Nth DFF may output output signals Out_2-Out_N for the stored digital signals.

In example embodiments, the measurement voltage VMmay be the first measured voltage VM1, which is higher than the comparison reference voltage VREF, or the second measured voltage VM2, which is lower than the comparison reference voltage VREF. When the measurement voltage VMis the first measured voltage VM1, the first DFF891may output a first output signal Out_1(1), which has a value of 1. For example, when the measurement voltage VMis the second measured voltage VM2, the second DFF may output the first output signal Out_1(2), which has a value of 0. In other words, when the measurement voltage VMis higher than the comparison reference voltage VREF, the first DFF891may output1, and when the measurement voltage VMis lower than the comparison reference voltage VREF, the first DFF891may output 0.

Thereafter, the comparison reference voltage VREFmay be changed in sequence, and the second to Nth DFFs may output the second to Nth output signals Out_2-Out_N. For example, the Nth DFF89N may output an Nth output signal Out_N on the basis of the changed comparison reference voltage VREF′. The measurement voltage VMmay be the first measured voltage VM1, which is higher than the changed comparison reference voltage VREF′, or the second measured voltage VM2, which is lower than the comparison reference voltage VREF. When the measurement voltage VMis the first measured voltage VM1, the Nth DFF89N may output the Nth output signal Out_n(1), which has a value of 1. For example, when the measurement voltage VMis the second measured voltage VM2, the Nth DFF89N may output the Nth output signal Out_n(2), which has a value of 0. In other words, when the measurement voltage VMis higher than the comparison reference voltage VREF, the Nth DFF89N may output1, and when the measurement voltage VMis lower than the comparison reference voltage VREF, the Nth DFF89N may output 0.

At the tenth time point t10, the A2nsignal may change to a high level such that the comparator885may be deactivated, and the D signal of the switching assembly860may change to a high level such that the M node may be connected to ground. At eleventh time point t11, the D signal may change from a high level to a low level, and the G and G1node voltages may be reduced to 0V. In this case, the M node may be maintained at 0V. At the twelfth time point t12, an An signal may change to a high level, and the defect detection conductor810may be reconnected to the input control circuit820and the output control circuit830.

In example embodiments, disconnection of the defect detection conductor810and a disconnection position may be detected using the first to Nth output signals Out_1-Out_N of the storage890. The comparison reference voltage VREFinput to the comparator885may be changed and operation from the first time point t1to the twelfth time point t12may be repeated. For example, a minimum value of the comparison reference voltage VREFmay be input into the comparator885and the operation described above may be performed, and the operations may be repeatedly performed while constantly increasing the comparison reference voltage VREF. When the output signal Out_1-Out_N of the storage890changes from 1 to 0, it may be detected that the defect detection conductor810is disconnected. Also, the disconnection position may be detected using a voltage value of the comparison reference voltage VREFat which the first to Nth output signals Out_1-Out_N of the storage890changes from 1 to 0. Accordingly, whether defects are present and positions of defects caused by cracks in the periphery of the semiconductor device or cracks in the bonding pad may be detected, thereby improving reliability of the semiconductor device.

The switching assembly860inFIG.12may be connected to a position adjacent to the input control circuit820of the defect detection conductor810, and defects may be detected using the voltage of the G and G1nodes. In another example embodiment, the switching assembly860inFIG.12may be connected to a position adjacent to the output control circuit830of the defect detection conductor810, and defects may be detected using the voltage of the G and G2nodes.

FIG.14is a flowchart illustrating a method for detecting defects according to one or more example embodiments of the present disclosure.

The circuit for detecting defects may include a defect detection conductor, an input pad, an output pad, a defect detection assembly, a controller, a comparator, and a storage. A defect detection conductor may be disposed in a peripheral region of the semiconductor die. The input pad may be connected to one end of the defect detection conductor, and the output pad may be connected to the other end of the defect detection conductor.

The defect detection assembly may be connected to the defect detection conductor and may detect defects of the defect detection conductor. The defect detection assembly may include a reference voltage supply, a reference capacitor, a switching assembly, and a plurality of detection capacitors. The switching assembly may include a first switch connecting the reference capacitor to the reference voltage supply, and a second switch connecting the reference capacitor to a position adjacent to the input pad of the defect detection conductor. A plurality of detection capacitors may be connected between the input pad and the output pad in parallel.

The controller may separate both ends of the circuit for detecting defects using the input pad and the output pad in operation S100. The controller may turn on the first switch in operation S110. In this case, the reference capacitor may be connected to the reference voltage supply, and the reference capacitor may be charged through the reference voltage supply in operation S120.

Thereafter, the controller may turn off the first switch and may turn on the second switch in operation S130. In this case, the reference capacitor may be connected to a position adjacent to the input pad of the defect detection conductor. The reference capacitor may be connected in parallel with a plurality of detection capacitors, and the controller may measure the measurement voltage at a node at which the switching assembly is connected to the defect detection conductor in operation S140. The measurement voltage may be determined according to a capacitor composite value of the plurality of detection capacitors.

The comparator may compare the measurement voltage with the comparison reference voltage in operation S150. For example, the comparator may repeatedly perform an operation of comparing the measurement voltage with the minimum voltage among the plurality of comparison reference voltages until the measurement voltage falls lower than the comparison reference voltage. A minimum voltage among comparison reference voltages may correspond to the measurement voltage when the reference capacitor is connected to the plurality of detection capacitors when no defects are present in the defect detection conductor. A maximum voltage of the comparison reference voltage may correspond to the reference voltage supplied by the reference voltage supply.

The comparator may output the comparison result, and the storage may store an output signal output by the comparator in the 0th DFF and may store the signal in one of the first to Nth output signals Out_1-Out_N in operation S160. This process may correspond to the process from the first time point t1to the twelfth time point t12as illustrated inFIG.13.

In operation S170, it may be determined whether the measured voltage is lower than a comparison reference voltage. When the measurement voltage is higher than the comparison reference voltage (NO in S170), the output signal output by the storage may correspond to 1. Also, the controller may separate both ends of the circuit for detecting defects again (operation S100) and may repeat the subsequent process (operations S110-S160). Specifically, the controller may change the comparison reference voltage input to the comparator. For example, the controller may increase the comparison reference voltage by a determined width, and the comparator may compare the measurement voltage with the comparison reference voltage again.

When the measurement voltage is lower than the comparison reference voltage (YES in S170), an output signal output by the storage may correspond to 0. In this case, whether defects are present in the semiconductor device and a position thereof may be detected through the applied comparison reference voltage in operation S180. In other words, to determine the disconnection position according to the comparison reference voltage applied when 1 to 0 are applied to the output signal Out_1-Out_N, to determine the disconnection position according to the applied comparison reference voltage, the process illustrated in the first time point t1to the twelfth time point t12illustrated inFIG.13may be repeatedly performed.

In operation S190, it may be determined whether to increase a waiting time. When a waiting time is increased (YES in S190), the controller may measure the measurement voltage again (operation S100) and may repeat the subsequent processes (operations S110-S180). In example embodiments, the waiting time may correspond to the time between the time point at which the first switch is turned off and the second switch is turned on (operation S130) and the time point at which the measurement voltage is measured at a node at which the switching assembly is connected to the defect detection conductor (operation S140). When the waiting time is not increased (NO in S190), the output signal Out_1-Out_N in operation S180may be arranged according to the comparison reference voltage when measuring the waiting time and the output signals Out_1-Out_N in operation S200. Accordingly, current leakage of the semiconductor device may be detected in operation S210, and specifically, current leakage of the defect detection conductor over time may be detected.

FIGS.15A to15Eare diagrams illustrating results of a system for detecting defects according to one or more example embodiments of the present disclosure. The results of the system for detecting defects may appear as in the example embodiments illustrated inFIGS.15A-15E. Specifically, an output signal may be arranged according to the waiting time WT corresponding to the time point at which the second switch turns on (operation S130ofFIG.14) and the time point at which the measurement voltage is measured at a node at which the switching assembly is connected to the defect detection conductor (operation S140ofFIG.14), and the comparison reference voltage VREF(operation S180ofFIG.14).

FIGS.15A to15Emay represent the results of arranging the output signal according to the waiting time and the reference voltage in the circuit for detecting defects configured the same. Specifically, the horizontal axis of eachFIGS.15A to15Emay correspond to the waiting time WT corresponding to the time point at which the second switch turns on (operation S130ofFIG.14) and the time point at which the measurement voltage is measured at a node at which the switching assembly is connected to the defect detection conductor (operation S140ofFIG.14), and the vertical axis may correspond to the comparison reference voltage VREF. For example, when the measurement voltage is 0.65 and the plurality of comparison reference voltages are 0.5 VREF, MIN, 0.6, 0.7, 0.8 VREF, MAX, respectively, when the comparator compares the measurement voltage from the lower voltage among the comparison reference voltages, the output signal may be output in the order of “1,” “1,” “0,” and “0” in the waiting time WT.

ThroughFIGS.15A to15E, whether defects are present and positions of defects in the semiconductor device may be detected (operation S180ofFIG.14). With respect to a single waiting time WT, when the output signal is divided as 1 and 0 according to the comparison reference voltage VREF, it may be determined that defects are present in the semiconductor device. According to each ofFIGS.15A to15E, the output signal may be divided into 1 and 0 on the basis of the single waiting time WT (WT1-WT4) according to the comparison reference voltage VREF, such that it may be determined that defects are present in the semiconductor device. ComparingFIGS.15A to15E, the comparison reference voltage VREF, at which the output signal is divided into 1 and 0 in the first waiting time WT1,FIGS.15C to15Emay be higher thanFIGS.15A and15B. In other words, the position in which defects occur inFIGS.15C to15Emay be closer to the input pad than the position in which defects occur inFIGS.15A and15B. For example, when the output signal is 0 at the entirety of the reference voltages VREFwith respect to the waiting time WT, it may be determined that no defects are present in the semiconductor device.

Also, throughFIGS.15A to15E, current leakage of the semiconductor device may be detected (operation S200ofFIG.14). For example, current leakage of a defect detection conductor included in the semiconductor device may be detected. Depending on the waiting time WT, when the comparison reference voltage VREF, at which the output signal is divided into 1 and 0, decreases, it may be determined that current leakage may occur in the semiconductor device.

InFIGS.15A and15C, the comparison reference voltage VREF, at which the output signal is divided into 1 and 0, may be constant depending on the waiting time WT. The notion that the comparison reference voltage, at which the output signal is divided into 1 and 0, is constant may indicate that the measurement voltage may fall within the same voltage range even when the waiting time WT has elapsed. Accordingly, when the comparison reference voltage at which the output signal is divided into 1 and 0 is constant, it may be determined that no current leakage occurs.

InFIGS.15B,15D, and15E, the comparison reference voltage VREF, at which the output signal is divided into 1 and 0, is reduced depending on the waiting time WT, such that, inFIGS.15B,15D, and15E, it may be determined that current leakage has occurred.

Specifically, inFIGS.15D and15E, the comparison reference voltage VREF, at which the output signal at the first waiting time WT1is divided into 1 and 0, may be the same. Depending on the waiting time WT, the comparison reference voltage VREF, which divides the output signal into 1 and 0, may decrease, such that it may be determined that current leakage has occurred. Also, when slopes of the graphs are different, it may be determined that the degrees of current leakage may be different. Specifically, the slope at which the comparison reference voltage VREF, at which the output signal inFIG.15Dis divided into 1 and 0, is reduced may be greater than the slope inFIG.15E. In this case, it may be determined that the degree of current leakage appearing inFIG.15Dmay be greater than the degree of current leakage appearing inFIG.15E.

According to the aforementioned example embodiments, by disposing the circuit for detecting defects which may detect defects occurring in a semiconductor die, and disposing the defect detection conductor in the periphery of the semiconductor die or the periphery of each semiconductor die region, defects may be detected. The circuit for detecting defects may include a reference voltage supply, a reference capacitor, and a plurality of detection capacitors connected in parallel to the defect detection conductor, and by measuring a voltage of a node at which the reference capacitor and the plurality of detection capacitors are connected to each other and comparing the voltage with the comparison reference voltage, defects may be detected, such that reliability of semiconductor devices may be maintained.

At least one of the devices, units, components, modules, units, or the like represented by a block or an equivalent indication in the above embodiments including, but not limited to,FIG.11may be physically implemented by analog and/or digital circuits including one or more of a logic gate, an integrated circuit, a microprocessor, a microcontroller, a memory circuit, a passive electronic component, an active electronic component, an optical component, and the like, and may also be implemented by or driven by software and/or firmware (configured to perform the functions or operations described herein).

At least one of the devices, units, components, modules, units, or the like (collectively “devices”) represented by a block or an equivalent indication in the above embodiments including, but not limited to, the “controller780”, may be physically implemented by analog and/or digital circuits including one or more of a logic gate, an integrated circuit, a microprocessor, a microcontroller such as a central processing unit (CPU), a memory circuit, a passive electronic component, an active electronic component, an optical component, and the like, and the functions or operations of the devices may be implemented by or driven by software and/or firmware executed by the devices.

Each of the embodiments provided in the above description is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the disclosure.