Apparatus for converting facsimile coded data to video data

An apparatus for converting facsimile coded data to video data utilizing a programmed digital computer for receiving the facsimile coded data buffering the facsimile coded data and converting the facsimile coded data to a fixed length intermediate code. The fixed length intermediate code is then hardware converted to the video data.

BACKGROUND OF THE INVENTION 
The present invention relates generally to data convertors and more 
particularly to apparatus for converting facsimile coded data to video 
data. 
Facsimile machines are used for transmitting a document or picture from a 
first location to a second location over communication lines, such as 
telephone lines, without the necessity of physically transporting the 
document or picture. Such facsimile machines scan the information bearing 
document on a line by line basis. The facsimile machines then produce a 
particular code indicative of the information content of the document or 
picture. The code is then sent over communication lines to a similar 
facsimile machine. The second facsimile machine then interprets the code 
received and uses a printer to reproduce the original document or picture. 
The scanning of the information bearing document, the definition of the 
transmitted codes, the transmission of the codes, and the printing of the 
copy of the document are all standard, known elements in facsimile 
machines. An example of the transmitted codes are defined by International 
Telegraph and Telephone Consultative Committee (CCITT) specifications. All 
facsimile machines adhering to this specification can then decode the 
information and reconstruct the original information bearing document. 
CCITT codes are transmitted between one of several varieties of facsimile 
machines. The apparatus and method of the present invention can be used in 
decoding facsimile coded data which results from CCITT group 3 codes or 
rather those codes required of a CCITT group 3 facsimile machine. Group 3 
codes are defined in two varities; namely, one dimensional (1D) codes and 
two dimensional (2D) codes. 1D codes interpret the information content of 
one line, namely the current line being scanned and the code produced is 
indicative of the serial run lengths of the information contained therein 
and result in Huffman codes being produced. Similarly the receiving 
facsimile machine receives the Huffman codes and reproduces the 
information bearing document by converting the serial run lengths of the 
Huffman codes by printing the document on a line by line basis. 2D codes 
interpret not only the current line but are also dependent on the 
information content of a previous line, usually the previous line scanned. 
2D codes compress the information content of an information bearing 
document into a fewer number of bits than 1D codes resulting in decreased 
transmission times, but require a more complicated decoder. While encoding 
or decoding a document containing printing or graphical information, on 
many occasions a vertical or other vertically correlated edge (or line) 
will be present in the document. In order to accurately reflect these 
vertical correlations it is advantageous to compare the vertical 
correlation of a change in the binary information content of a current 
line with a change in the binary information content of a previous line 
(usually the prior line). 
The scanning during encoding of a document and printing after decoding is 
usually accomplished on a line by line basis. Each line is divided into a 
predetermined number of elements called picture elements. The information 
bearing document or picture is scanned and encoded in a binary (i.e. black 
and white) basis. All discrete picture elements (PELs) are represented as 
either black or white (with a representation in binary language of either 
a 1 or a 0). A change in the binary information content of the information 
bearing document is a change (black to white, e.g. 1 to 0; or white to 
black, e.g. 0 to 1) in the representation of the color (black or white) of 
the picture element currently being scanned or decoded (the current 
picture element) from the color (black or white) of the picture element of 
the last scanned or decoded picture element (prior picture element). Hence 
a color change refers to a change in color (black and white) of the 
picture elements. 
2D codes represent the encoding of the vertical correlation between a color 
change between picture elements and the current line with a color change 
between picture elements in a prior line, usually the previous line as 
well as incorporating the run length capabilities of 1D codes. Such 
vertical correlation may be exactly vertical or the correlation may be 
within a certain predetermined range of vertical. In a typical facsimile 
machine in coding situation, a "window" is defined by examining vertical 
correlation within three horizontal (if the document is being scanned 
horizontally) picture elements. Thus, the "vertical correlations" 
considered are a "vertical 0 (V0)", with a color change in a previous line 
exactly vertical with the color change in the current line, "vertical left 
3 (VL3)", with a color change in a prior line occurring three elements to 
the left of a color change in the current line, and correspondingly a 
"vertical left 2 (VL2)", a "vertical left 1 (VL1)", a "vertical right 1 
(VR 1)", a "vertical right 2 (VR2)" and a "vertical right 3 (VR3)". 
Further a decoding apparatus and method of the scope of the present 
invention is required to perform in a number of other different modes. 
These modes are supplied by an external command along a command interface 
supplied to the decoder. Examples of other modes of operation include an 
ASCII mode which converts binary data to a 7.times.11 dot matrix pattern 
for printing and a self diagnostic mode which produces standard test 
patterns to adequately query the decoder to ensure its proper operation. 
Thus a decoder of the scope of the present invention must be versatile 
while still being fast enough to transmit an entire information bearing 
document within a reasonable length of time. 
Pure hardware implementations for decoding facsimile coded data have been 
accomplished in the prior art. These implementations suffer the 
disadvantage of not being versatile. Pure hardware implementations must 
have specific hardware in order to perform each individual task. This 
hardware and its resultant function is not easily upgraded if, for 
example, the CCITT specification changes or a new specification is 
produced. If this occurs, then a new hardware design is required. 
It is anticipated that a pure software solution for converting facsimile 
coded data to video data could also be achieved. Such a solution would be 
extremely flexible in order to change the decoding alogorithm it would 
only be necessary to load a new program or to replace a program contained 
in read only memory. However, such a pure software solution would result 
in very slow decoding. The number of codes required to adequately describe 
a given document would make the decoder very slow and the resultant 
transmission time of the document long. 
SUMMARY OF THE INVENTION 
Present invention provides an apparatus for converting facsimile coded data 
to video data. The apparatus uses a programmed digital computer for 
receiving the facsimile coded data, buffering the facsimile coded data, 
and converting the facsimile coded data to a fixed length intermediate 
code. A video convertor is then responsive to the programmed digital 
computer and converts the fixed length intermediate code to the desired 
video data. 
In a preferred embodiment the programmed digital computer includes a 
microprocessor capable of executing a series of instructions along with a 
read only memory containing the series of instructions and being capable 
of supplying the instructions to the microprocessor. Further an interface 
module is provided for receiving the facsimile coded data along with a 
randomly accessible memory coupled to the interface module and to the 
microprocessor for holding and buffering the facsimile coded data and for 
holding a table lookup for converting the facsimile coded data to the 
intermediate code. A direct memory access controller is coupled to the 
microprocessor, is coupled to the randomly accessible memory, and is 
coupled to the interface module and to the video convertor. The direct 
memory access controller transfers the facsimile coded data from the 
interface module to the randomly accessible memory and transfers the 
intermediate code from the randomly accessible memory to the video 
convertor under control of the microprocessor. 
In a preferred embodiment the video convertor includes an instruction 
register for receiving the intermediate code from the randomly accessible 
memory. A line counter is coupled to the instruction register for counting 
the number of picture elements in a current line of the facsimile coded 
data decoding. A history memory is coupled to the line counter for holding 
data of the picture elements in a line prior to the current line. A shift 
register is coupled to the history memory for holding data of picture 
elements in a line prior to the current line which is within a 
predetermined number of picture elements to the current one of the picture 
elements in the current line. A vertical logic array is coupled to the 
instruction register and to the shift register for determining the 
vertical correlations between the picture elements within the window with 
the current one of the picture elements in the current line. A horizontal 
logic array is coupled to the instruction register to the history memory, 
and to the vertical logic array for determining the video output data 
based upon the intermediate code in the instruction register. Further, a 
video interface logic array is coupled to the horizontal logic array and 
to the vertical logic array for outputting the video output data. 
The present invention solves the problem by dividing the facsimile coded 
data to video data conversion task into two separate and distinct parts. 
First, the front end work of determining the mode of operation, i.e. 1D, 
2D, ASCII, etc., receiving the facsimile coded data code words, 
identifying the code words in the incoming data stream, buffering the code 
words until they can be processed, and supplying the code words to the 
video convertor is all done by control of a programmed digital computer 
providing all the versatility advantages of such a computer. Further, in 
order to ease the task of the remaining system the variable length 
facsimile coded data is converted to a fixed length intermediate code. 
Subsequent hardware is made much simpler with a fixed length code word (or 
instruction, not to be confused with an instruction for a programmed 
digital computer) than the variable length CCITT codes. Second, a hardware 
video convertor then converts the specific intermediate code word (or 
instruction) into video data for printing and the reproduction of the 
original document. Specific hardware modules can be added to the video 
convertor to perform 1D or 2D decoding or other specific modes such as 
ASCII conversion. The hardware video convertor takes the fixed length 
intermediate codes (instructions) and rapidly processes them to produce 
video data at a high rate of speed. The hardware implementation can 
perform the data conversions very quickly. Note that the instruction word 
provided to the video convertor provides a fixed length instruction or 
code which has already been extracted from the incoming data bit stream 
and which has been buffered by the software to be ready for immediate use. 
The unique aspects of the present invention involve the use of a programmed 
digital computer for versatile set up, data preparation, buffering 
functions, and uses hardware for the repetitive standard data conversion 
operation. It is estimated that the present invention operates faster and 
more efficiently than with either a pure software solution or a pure 
hardware solution. The use of the best of both worlds of software and 
hardware result in the achievement of the unique synergistic operation of 
the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
As previously mentioned, the function of an apparatus and method for 
converting facsimile coded data to video data is to convert standard, 
predetermined codes such as CCITT codes transmitted over common 
communication lines to a format which may be utilized by line printer to 
reconstruct the original document encoded at the origin by an encoding 
facsimile machine. 
The encoding process is the subject of a U.S. patent application, Ser. No. 
416,138, filed Sept. 9, 1982, by John A. Harrington, entitled Apparatus 
for Producing a Code Word, now U.S. Pat. No. 4,509,194, and assigned to 
Minnesota Mining and Manufacturing Company, the assignee of the present 
invention, which application is hereby incorporated by reference. 
The apparatus of the present invention decodes the standard facsimile coded 
data by utilizing a multistep process. Under software control the variable 
length facsimile coded data is received and buffered in a randomly 
accessible memory. The CCITT fax codes can vary in length from one bit to 
thirteen bits. The software further uses a table lookup process to convert 
the variable length facsimile coded data to a fixed length, bytewide 
(eight bit) code words. The software then transfers these individual fixed 
length intermedite code instructions to a hardware video convertor which 
converts the intermediate code instruction to actual black/white video 
data suitable for use by a printer in reconstructing the original document 
on a line by line basis. 
Operation of the apparatus of the present invention may be more readily 
understood by reference to FIG. 1 which is a block diagram of the 
apparatus. The major control element of the apparatus of the present 
invention is a microprocessor 10. In a preferred embodiment the 
microprocessor 10 is a microprocessor Model 6809 manufactured by Motorola. 
The microprocessor 10 communicates via a data bus 12. A read only memory 
(ROM) 14 also communicates via data bus 12. The read only memory 14 
contains the software instructions which control the operation of the 
microprocessor 10. In a preferred embodiment the read only memory 14 is an 
8K by 8 bit read only memory device such as a Model 2564 manufactured by 
Texas Instruments. A randomly accessible memory 16 also communicates via 
data bus 12. Randomly accessible memory 16 provides working storage for 
the microprocessor 10 which includes temporary storage of the received 
facsimile coded data, buffer space for the produced intermediate codes as 
well as program work storage for the microprocessor 10. In a preferred 
embodiment, the randomly accessible memory 16 is a 2K by eight bit RAM 
such as a Model 4802 manufactured by Mostek. An asynchronous 
communications interface adapter 18 communicates via data bus 12 and 
receives external commands from command bus 20 providing a control 
interface for initiating and terminating the various modes of operation of 
the apparatus. In a preferred embodiment, during ASCII mode, ASCII 
characters are transmitted through this interface. In a preferred 
embodiment, the asynchronous communications interface adapter is a Model 
6850 manufactured by Motorola. Data interface module 22 receives the 
incoming facsimile coded data via data bus 24 and transmits the facsimile 
coded data to the randomly accessible memory 16 via data bus 12. In a 
preferred embodiment the interface module 22 is a Model 74LS374 
manufactured by Texas Instruments. Digital memory access controller 26 
also communicates via data bus 12. The digital memory access controller 26 
operating under control of the microprocessor 10 provides the handshake 
interface for interface module 22 and further provides initialization and 
control information to video convertor 28. The direct memory access 
controller also controls all memory data transfers between the randomly 
accessible memory 16 and the video convertor 28. In a preferred embodiment 
the digital memory access controller 26 is a Model 6844, manufactured by 
Motorola. Video convertor 28 receives intermediate code word instructions 
from randomly accessible memory 16 via the data bus 12 under control of 
the direct memory access controller 26. The video convertor 28 is the 
hardware portion of the apparatus for converting the intermediate code 
word instructions to video data and supplying video data along video data 
bus 30 for use in a standard state of the art printer for the reproduction 
of the original facsimile coded document. 
The facsimile coded data is received over data bus 24 by the interface 
module 22. Under control of the direct memory access controller 26 the 
facsimile coded data is transferred via the data bus 12 to the randomly 
accessible memory 16. Once in the randomly accessible memory 16 the 
microprocessor 10, under control of the instructions in the read only 
memory 14, searches the facsimile coded data for a particular facsimile 
code (e.g. 1D or 2D) in that facsimile coded data. When a particular 
facsimile code is found it is converted by a table lookup process into a 
fixed length (preferably eight bit) intermediate code which is also placed 
into randomly accessible memory 16. Under control of the direct memory 
access controller 26 the intermediate code word is transferred from the 
randomly accessible memory 16 via the data bus to the hardware video 
convertor 28 where the intermediate code operates as an instruction for 
the hardware video convertor 28. In addition to converting the facsimile 
coded data to intermediate codes, the microprocessor 10 also controls the 
direct memory access controller 26 by specifying into which blocks of 
randomly accessible memory 16 the direct memory access controller 26 
should place and retrieve data as well as initializing the direct memory 
access controller 26. 
A list of the intermediate code words utilized in a preferred embodiment of 
the apparatus of the present invention is described in Table I. 
TABLE I 
______________________________________ 
INTERMEDIATE CODE WORDS 
Bit 
7 6 5 4 3 2 1 0 Description 
______________________________________ 
1 O X X X X X X Make-Up Count 
O O X X X X X X Terminate Count 
O 1 O O O O O O VL3 
O 1 O O O O O 1 VL2 
O 1 O O O O 1 O VL1 
O 1 O O O O 1 1 VO 
O 1 O O O 1 O O VR1 
O 1 O O O 1 O 1 VR2 
O 1 O O O 1 1 O VR3 
O 1 O O O 1 1 1 Pass 
O 1 O 1 1 O O O Start New Line 
______________________________________ 
A preferred embodiment of the software contained in the read only memory 14 
suitable for operating the microprocessor 10 in the manner described can 
be found by reference to the software source code listing enclosed with 
this application and made part of the specification hereof. This computer 
program listing is submitted under the provisions of 37 CFR 1.96 and is 
located at the end of the description but before the claims. The computer 
program listing also contains guiding comments describing the flow of data 
and operation of the computer program listing. 
A more detailed description of the hardware implementation of the video 
convertor 28 may be had by reference to FIG. 2. The intermediate code word 
instructions are supplied via data bus 12 to the video convertor and 
placed in instruction register 32. Makeup and terminate intermediate codes 
are processed via run length counter 34 which counts the codes to zero and 
supplies the resulting termination to interface programmed logic array 36. 
In ASCII mode, the intermediate code word instruction contained in 
instruction register 32 is supplied to dot shift matrix 38 for immediate 
conversion to an ASCII character dot sequence and supplied to horizontal 
mode programmed logic array 40 for transmission on the video data bus 30. 
A line counter 42 is reset by the horizontal mode programmed logic array 
40 at the initialization, or start, of every given line. The line counter 
42 along with address adjust module 44 keeps track of the current picture 
element being printed or current picture element whose data is being 
converted on the line by line scan basis in the document. In this 
preferred embodiment, line counter 42 actually is counting four picture 
elements ahead of the current picture element in the line due to the 
necessity for looking at the data contained within the "window" of the 
prior line printed or decoded. Randomly accessible memory 46 obtains input 
from the horizontal mode programmed logic array 40 and contains the data 
of the picture elements printed or decoded in the prior line. In 
conjunction with the address information contained in line counter 42 and 
address adjust module 44, the randomly accessible memory 46 by way of a 
line location programmed logic array 48, transmits the data contained 
within the "window" of picture elements on the prior line to shift 
register 50 to be supplied to the vertical mode programmed logic array 52 
for use in determining vertical correlations. Address adjust module 44, 
since it is actually designed to be four picture elements ahead, subtracts 
four picture elements from the value contained in the line counter 42 as 
it is supplied to the line location program logic array 48. Horizontal 
mode programmed logic array 40 controls the color information supplied on 
the video data bus 30 and determines the proper horizontal run length 
operation and ASCII print timing. The vertical mode program logic array 52 
determines the point in the current line being printed or decoded where a 
color change is necessary due to the color data of the picture elements 
contained in the "window" supplied by shift register 50 in conjunction 
with the 2D vertical correlated code supplied by the instruction register 
32. The line location programmed logic array 48 keeps track of the 
particular location in which the decoder is operating on the current line 
and controls special beginning of line and end of line conditions and in 
particular, at an end of a line condition supplies the proper information 
to the interface programmed logic array 36 to supply proper video data to 
the video data bus 30. The interface programmed logic array 36 provides 
the timing of data transfers to the video data bus 30 for the data 
supplied by the horizontal mode programmed logic array 40. 
In a preferred embodiment, instruction register 32 is constructed of 
standard register components such as Model 74LS373 manufactured by Texas 
Instruments. Similarly, run length counter 32 is constructed from three 
standard commercially available counters such as Model 74LS193 
manufactured by Texas Instruments. Interface programmed logic array 36 is 
constructed from a commercial programmed logic array Model 16R4 
manufactured by Monolithic Memories. The particular structure contained 
within the programmed logic array may be had by reference to Table II 
which contains the equations used for the programmed logic array. 
TABLE II 
__________________________________________________________________________ 
16R4D2 
PAT0001 
DECODER INTERFACE 
CLK CTOL STL SC LRC LASTPEL CA1 CTFLG RESET GND ENABLE 
LINEREADY GOODDATA GFHDLY ERRFFL LPFFL 3FF ACTIVE ENCLK VCC 
/3FF := /SC*RESET + /SC*/3FF*/CA1 + SC*STL + /LPFFL*ACTIVE 
/3FFDLY := RESET + /3FF + /LPFFL + LASTPEL*CA1*ACTIVE + SC 
/LPFFL := /RESET*LASTPEL*CA1*ACTIVE + /RESET*/LPFFL 
/ERRFFL := /SC*/LPFFL*ACTIVE*3FF + /SC*RESET*LPFFL*/LRC = 
/ERRFFL*/SC*/LRC 
/LINEREADY = /SC*/RESET + /LRC*SC 
/ENCLK = /ACTIVE + /3FFDLY*/SC 
/ACTIVE = /ERRFFL*/LPFFL + /STL + /CTFLG*3FFDLY*/CTOL*/SC + 
/SC*RESET + /SC*/LPFFL*/CTOL*/CTFLG + /SC*/LPFFL*/3FF 
/GOODDATA = /SC*/LINEREADY + /SC*/ERRFFL + /SC*LPFFL + 
SC*/LRC + /SC*/3FF 
__________________________________________________________________________ 
Dot Shift matrix 38 is a standard commercially available part such as Model 
74LS165 manufactured by Texas Instruments. Horizontal programmed logic 
array 40 is also a commercially available programmed logic array and in a 
preferred embodiment a Model 16R6 manufactured by Monolithic Memories. 
The structure of the horizontal mode programmed logic array 40 can be had 
by reference to Table III which contains logic equations used for 
constructing that programmed logic array. 
TABLE III 
__________________________________________________________________________ 
PAT16R6 
PAT0001 
HORIZONTAL MOD . 
CLK LDL 3FF D7 D6 D5 D4 STL SC GND ENABLE ACTIVE SDODLY 
COUNTFLG HOLDFLG SHCLK STOPA COLOR DATA VCC 
/COLOR := /SC*/LDL*COLOR*HOLDFLG*/D4 + 
/SC*/LDL*/HOLDFLG*/COLOR*/D4 + /SC*LDL*/COLOR + SC*/DATA + 
/SC*/LDL*COLOR*HOLDFLG*/D6 + SC*/LDL*/HOLDFLG*/COLOR*/D6 
/STOPA := /SC*SDODLY*/SHCLK + /SC*ACTIVE*/STOPA + SC*/LDL + 
SC*/STOPA*SDODLY + SC*/STOPA*HOLDFLG + SC*/STOPA*COUNTFLG + 
/SHCLK*SC*/STOPA 
/SHCLK := /SC*/D4 + /SC*LDL + SC*STOPA + SC*SHCLK +/SC*/D6 
/HOLDFLG := /SC/LDL*D7*/D6 + /SC*/LDL*/D7*D6*D5 + 
/SC*LDL*/HOLDFLG + SC*/STOPA*/3FF*/SHCLK*/HOLDFLG + 
SC*/STOPA*/3FF*/HOLDFLG*SDODLY 
+ SC*/STOPA*/3FF*HOLDFLG*SHCLK*/SDODLY 
/COUNTFLG := /SC*LDL*/D6 + /SC*LDL*/COUNTFLG + 
SC*/STOPA*/COUNTFLG + SC*/STOPA*SHCLK*/SDODLY*/HOLDFLG 
/SDODLY := /SC*DLD + SC*/STOPA*/3FF*/SHCLK*/SDODLY + 
SC*/STOPA*/3FF*SHCLK*SDODLY 
__________________________________________________________________________ 
Line counter 42 can be constructed of commerically available counter 
components such as Model 74LS193 manufactured by Texas Instruments. 
Address adjust module 44 is a standard commerically available PROM 
configured to subtract four from the data contained in the line counter 
42. The PROM preferred for address adjust module 44 is Model 27SL9 
manufactured by Advanced Micro Devices. Randomly accessible memory 46 is a 
commercially available 4K by 1 bit RAM such as a Model 2147 manufactured 
by Intel. Line location programmed logic array is a commercially available 
logic array such as Model 14H4 manufactured by Monolithic Memories. The 
particular structure of the line location programmed logic array 40 may be 
by reference to the equations contained in Table IV. 
TABLE IV 
__________________________________________________________________________ 
14H4D 
PAT0001 
LOGIC SIGNAL GENERATOR. 
CA10 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 GND EXPANDI CAO ENOT 
EXPANDO LASTPEL D A10 DN HP VCC 
A10 = /CA10*/ENOT + 
/CA9*/CA8*/CA7*/CA6*/CA5*/CA4*/CA3*/CA2*/ENOT + ENOT*/CA10 
D = DN*EXPANDI + /HP*/EXPANDI 
LASTPEL = CA6*CA7*CA9*CA10*CA0 
EXPANDO = /CA6 + /CA7 + /CA9 + /CA10 
__________________________________________________________________________ 
Shift register 50 is a standard four bit commerically available shift 
register such as Model 74LS174 manufactured by Texas Instruments. Vertical 
mode programmed logic array 52 is a commercially available programmed 
logic array such as a 16R4 manufactured by Monolithic Memories. The 
particular structure of the vertical model program logic array can be had 
by reference to the equations contained in Table V. 
TABLE V 
__________________________________________________________________________ 
16R4D1 
PAT0001 
VERTICAL MODE . 
CLK HP0 HP1 HP2 HP3 3FFDL D2 D1 D0 GND ENABLE COLOR STOPB2L 
TRANSL F-3L F-2L F-1L STOPB1L STOPA VCC 
/STOPB1L = 3FFDL*/D0*/D1*/D2*/STOPA*COLOR*HP2*/HP3 
+ 3FFDL*/D0*/D1*/D2*/STOPA*/COLOR*/HP2*HP3 
+ 3FFDL*D0*/D1*/D2*/STOPA*COLOR*HP1*/HP2 
+ 3FFDL*D0*/D1*/D2*/STOPA*/COLOR*/HP1*HP2 
+ 3FFDL*D1*/D0*/D2*/STOPA*COLOR*HPO*/HP1 
+ 3FFDL*D1*/D0*/D2*/STOPA*/COLOR*/HPO*HP1 
+ /3FFDL*D1*D0*/D2*/STOPA*/F-2L 
/STOPB2L = 3FFDL*D0*D1*/D2*/STOPA*COLOR*/HPO*/TRANSL 
+ 3FFDL*D0*D1*/D2*/STOPA*/COLOR*HP0*/TRANSL 
+ D2*/D0*/D1*/STOPA*/TRANSL*/F-1L 
+ D2*D0*D1*/STOPA*/TRANSL*/F-2L 
+ D2*D1*/D0*/STOPA*/TRANSL*/F-3L 
+ 3FFDL*D0*D1*D2*/STOPA*/TRANSL*/COLOR*HPO 
+ 3FFDL*D0*D1*D2*/STOPA*/TRANSL*COLOR*HP0 
/TRANSL := D2*/STOPA*COLOR*HPO/HP1 + 
D2*/STOPA*/COLOR*/HPO*HF1 + D0*D1*/D2*/STOPA*COLOR*HPO + 
D0*D1*/D2*/STOPA*/COLOR*/HPO + /STOPA*/TRANSL 
/F-1L := /STOPA*/TRANSL*/HPO*COLOR*3FFDL + 
/STOPA*/TRANSL*HPO*/COLOR* 
3FFDL + /STOPA*/TRANSL*/F-1L*3FFDL 
F-2L := /STOPA*/F-1L*3FFDL + /STOPA*/F-2L + 
/STOPA*3FFDL*D0*D1*/D2 
/F-3L := /STOPA*/F-2L + /STOPA*/F-3L 
__________________________________________________________________________ 
Thus, the apparatus of the present invention provides a unique multistep 
apparatus and process for converting facsimile coded data to video data. A 
programmed digital computer first converts the variable length facsimile 
coded data into a fixed length intermediate code and buffers the data so 
produced. A hardware module then converts the intermediate codes to video 
data for use in a printer to reconstruct the original document. The use of 
the programmed digital computer to find and convert the variable length 
facsimile coded data is an inexpensive use of standard microprocessor and 
related components to accomplish a task which would otherwise require a 
great deal of hardware. The programed digital computer also provides a 
great deal of flexibility to implement ASCII, self diagnostic or other 
modes with little or no increase in hardware cost. Further, the very 
repetitive and time critical conversion of intermediate code to video data 
format is accomplished by hardware. This unique construction gives the 
apparatus of the present invention the capability of being over twenty 
times faster than a pure software approach and gives a large size 
advantage over a pure hardware approach. 
Thus, it can be seen that there has been shown and described a novel 
apparatus and method for converting facsimile coded data to video data in 
a process therefore. It is to be understood, however, that various 
changes, modifications, and substitutions in the form of the details of 
the described apparatus can be made by those skilled in the art without 
departing from the scope of the invention as defined by the following 
claims. 
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