Semiconductor device and oscillation suppressing device

A semiconductor device of the present invention suppresses high frequency noise caused in a semiconductor device incorporating SiC elements. The semiconductor device includes semiconductor elements connected in series, a SiC diode element connected in parallel to the semiconductor element, and an oscillation suppressing circuit being connected in parallel to the semiconductor element and the SiC diode element and suppressing voltage fluctuation caused in the SiC diode element in response to turn-ons of the semiconductor element. The oscillation suppressing circuit suppresses voltage fluctuation caused in the SiC diode element in response to turn-ons of the semiconductor element thereby improving reliability of the semiconductor device.

The contents of the following Japanese patent applications are incorporated herein by reference:2016-136827 filed in JP on Jul. 11, 2016PCT/JP2017/019365 filed on May 24, 2017

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device and an oscillation suppressing device.

2. Related Art

As an example of semiconductor devices, a switch device which is configured by connecting a rectifier element such as schottky barrier diodes (SBDs) and the like in anti-parallel to a switch element such as insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs) and the like or a device which is configured by serially connecting two of the switch devices is incorporated in a power conversion system such as power conditioning systems (PCSs), inverters, and smart grids. In these systems, during turn-ons or turn-offs of the switch elements in the semiconductor device or during reverse recovery of the rectifier elements, sudden current changes (di/dt) may cause surge voltage (Ldi/dt) in a wiring inductance (L) in the device resulting in leakage of high frequency noise such as, for example, 10 kHz or less into the other devices in the system.

As such, Patent Document 1, for example, discloses a semiconductor device in which a snubber circuit is connected between two terminals electrically connected to the main circuit in the semiconductor device and exposed to the exterior. For the snubber circuit, an RC snubber which is configured by serially connecting a resistor element and a capacitor element is adopted. The RC snubber can absorb high frequency noise due to surge voltage thus preventing the leakage to the outside of the device.

In recent years, power semiconductor devices (hereinafter referred to as semiconductor devices for short) incorporating next-generation semiconductor elements such as compound semiconductor elements including silicon carbide (SiC) compound semiconductor elements and the like have been developed. Compared to the conventional silicon (Si) semiconductor elements, the SiC element is more highly pressure-resistant due to its high dielectric breakdown field, and also achieves a higher impurity concentration and a thinner active layer, thus enabling a small semiconductor device capable of operating highly efficiently and fast. However, the ability of such a semiconductor element to operate fast may cause high frequency noise that cannot be solved (or suppressed) by conventional RC snubbers or C snubbers.

SUMMARY

A semiconductor device may comprise a first semiconductor element and a second semiconductor element connected in series. The semiconductor device may comprise a first SiC diode element connected in parallel to the first semiconductor element. The semiconductor device may comprise a first oscillation suppressing circuit connected in parallel to the first semiconductor element and the first SiC diode element, the first oscillation suppressing circuit suppressing voltage fluctuation caused in the first SiC diode element in response to turn-ons of the second semiconductor element.

The semiconductor device may further comprise a second SiC diode element connected in parallel to the second semiconductor element.

The first oscillation suppressing circuit may include a resistor and a capacitor connected in series.

The first oscillation suppressing circuit may suppress a voltage fluctuation of 10 MHz or more.

The first oscillation suppressing circuit may suppress a voltage fluctuation in a range of 1 MHz to 100 MHz.

The capacitor may have a capacitance of 100 nF or less.

The capacitor may have a capacitance in a range of 1 nF to 20 nF.

At least one of the resistor and the capacitor of the first oscillation suppressing circuit may be resilient.

The semiconductor device may further comprise a housing for housing the first semiconductor element, the second semiconductor element, the first SiC diode element, and the second SiC diode element. The housing may comprise a first terminal housing section housing a first terminal to be connected to a first external terminal, the first terminal being connected to the first semiconductor element at opposite side from the second semiconductor element, the first terminal housing section protruding from a main body part of the housing, and a second terminal housing section housing a second terminal to be connected to a second external terminal, the second terminal being connected between the first semiconductor element and the second semiconductor element or the second terminal being connected to the second semiconductor element at opposite side from the first semiconductor element, the second terminal housing section protruding from the main body part of the housing.

The first oscillation suppressing circuit may be mounted on surfaces in the first terminal housing section and the second terminal housing section, the surfaces where the first external terminal and the second external terminal are connected.

The first oscillation suppressing circuit may be screwed together with the first external terminal with respect to the first terminal in the first terminal housing section and may be screwed together with the second external terminal with respect to the second terminal in the second terminal housing section.

The first oscillation suppressing circuit may be mounted on a side surface laterally positioned with respect to surfaces in the first terminal housing section and the second terminal housing section, the surfaces where the first external terminal and the second external terminal are connected.

The first oscillation suppressing circuit may include an additional substrate to be attached to the housing from the outside of the housing. The additional substrate may be fixed to the first terminal housing section and the second terminal housing section.

The additional substrate may include a first portion substrate and a second portion substrate separated from each other. The first oscillation suppressing circuit may include a resistor and a capacitor connected in series, at least one of the resistor and the capacitor being resilient and being provided to straddle between the first portion substrate and the second portion substrate.

The first oscillation suppressing circuit may be connected between the first terminal connected to the first semiconductor element at opposite side from the second semiconductor element and the second terminal connected between the first semiconductor element and the second semiconductor element.

The semiconductor device may further comprise a second oscillation suppressing circuit provided between a third terminal connected to the second semiconductor element at opposite side from the second terminal and the second terminal, the second oscillation suppressing circuit suppressing voltage fluctuation caused in the second SiC diode element in response to turn-ons of the first semiconductor element.

The first oscillation suppressing circuit may be provided between a first terminal connected to the first semiconductor element at opposite side from the second semiconductor element and a second terminal connected to the second semiconductor element at opposite side from the first semiconductor element.

The semiconductor device may further comprise an RC snubber circuit connected in parallel to the first semiconductor element, the first SiC diode element and the first oscillation suppressing circuit.

The RC snubber circuit may include a capacitor having a capacitance in a range of 400 nF to 10 μF.

An oscillation suppressing device to be attached to a semiconductor device comprising a first and second semiconductor elements connected in series and a first SiC diode element connected in parallel to the first semiconductor element may be attached to the housing of the semiconductor device and connected in parallel to the first semiconductor element and the first SiC diode element thereby suppressing voltage fluctuation caused in the first SiC diode element in response to turn-ons of the second semiconductor element.

The oscillation suppressing circuit may include a resistor and a capacitor connected in series, the resistor and the capacitor being connected in parallel to the first semiconductor element and the first SiC diode element.

The housing may comprise a first terminal housing section housing a first terminal to be connected to a first external terminal, the first terminal being provided to the first semiconductor element at opposite side from the second semiconductor element, the first terminal housing section protruding from a main body part of the housing, and a second terminal housing section housing a second terminal to be connected to a second external terminal, the second terminal being provided between the first semiconductor element and the second semiconductor element or the second terminal being provided to the second semiconductor element at opposite side from the first semiconductor element, the second terminal housing section protruding from the main body part of the housing. The oscillation suppressing device may be mounted on surfaces in the first terminal housing section and the second terminal housing section, the surfaces where the first external terminal and the second external terminal are connected or a side surface laterally positioned with respect to surfaces in the first terminal housing section and the second terminal housing section, the surfaces where the first external terminal and the second external terminal are connected.

The above-mentioned summary of the invention does not list all the features of the present invention. The invention may also reside in a sub-combination of the features.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Herebelow, the present invention shall be explained by means of embodiments of the invention, but the following embodiments should not be considered to limit the invention of the claims Moreover, all the features of the combinations described in the embodiments are not necessarily essential as means for solving the problems of the invention.

FIGS. 1A, 1B and 2show a configuration of the semiconductor device100in a view from the top, a configuration of the semiconductor device in a view from the side, and an internal configuration of the semiconductor device, respectively, according to this embodiment. Herein, the upward and downward direction ofFIG. 1Aand the depth direction extending forward in the direction orthogonal to the planes ofFIGS. 1B and 2are referred to the vertical direction. The rightward and leftward direction ofFIGS. 1A, 1B and 2are referred to the horizontal direction. The depth direction extending forward in the direction orthogonal to the plane ofFIG. 1Aand the upward and downward direction ofFIGS. 1B and 2are referred to the height direction. The object of the semiconductor device100is to suppress high frequency noise which may happen during turn-ons of switch elements by incorporating an oscillation suppressing circuit, and preferably, to further configure a highly reliable oscillation suppressing circuit in terms of stress resistance such as heat stress.

The semiconductor device100includes a housing10, a substrate13, semiconductor elements14aand15a, SiC diode elements14band15b, external terminals16to18, conductive parts16ato18a, an external terminal19, and an oscillation suppressing circuit20.

Unless otherwise specifically stated, references in this specification to “connection” shall include the meaning of electrically energizable connection.

The housing10is a member for sealing each constituent element of the semiconductor device100therein with the top end of the external terminal19protruding and the lower surface of the substrate13being exposed flush with the bottom surface of the housing10, and for fixing the external terminals16to18with their respective upper surfaces being exposed to the top surface of the housing10. The housing10includes a main body11and a terminal housing chamber12, which are formed by molding a thermosetting resin such as, for example, an epoxy resin.

Instead of molding, the housing10may seal each constituent element of the semiconductor device100by filling a gel filler such as silicone gel in the interior space. Also, in addition to sealing the constituent elements inside the housing10while exposing the lower surface of the substrate13from the bottom surface of the housing10, by bonding the substrate13onto a plate-like base member of metal material such as, for example, copper using a bonding material such as solder and then fixing a frame onto the periphery of the base member using an adhesive and the like so as to have the housing10with the base member on its bottom surface, the housing10as such may seal each constituent element therein. Accordingly, heat caused by semiconductor elements mentioned below is exhausted to a member, i.e., a heat sink to which the semiconductor device100is mounted via the substrate13and the base member.

The main body11has a substantially rectangular parallelepiped where one axial direction (i.e., horizontal direction) is the longitudinal direction and a substantially rectangular parallelepiped-shaped protrusion11cthat protrudes upwardly from the middle of the upper surface of the substantially rectangular parallelepiped. In the upper surface of the main body11, a recess11bextending in the middle of the protrusion11cin the leftward direction of the figure in a view from the top is formed. In the recess11b, the terminal housing chamber12mentioned below may be inserted. Moreover, the main body11has substantially square-shaped stepped sections11aat the four corners in a view from the top, and each stepped section11ahas a through-hole11a0formed thereon which extends through in the height direction. The semiconductor device100can be fixed to external devices by inserting fittings such as a bolt into the through-holes11a0from above.

Together with the terminal housing chamber12inserted in the recess11b, the protrusion11cconstitutes a plurality of terminal housing sections11c1to11c3successively connected in one axial direction via grooves. The protrusion11chouses the respective external terminals16to18described below in the positions corresponding to the three terminal housing sections11c1to11c3within the recess11b. However, the external terminals16to18are U-shaped in a view from the side and have openings160to180formed in the middles of the upper surfaces, and the external terminals16to18are placed in the recess11bwith the upper surfaces of the external terminals16to18directed upward and the open ends of U-shape directed toward one side in the vertical direction such that the terminal housing chamber12can be inserted in the horizontal direction inside the external terminals16to18.

The terminal housing chamber12is a member for housing terminals16bto18band fixing the external terminals16to18. The terminal housing chamber12has three bumps successively connected in one axial direction via grooves, corresponding to the three terminal housing sections11c1to11c3, on the flat plate of the same shape as the recess11bof the main body11, i.e., where one axial direction is the longitudinal direction. In the respective middles of the upper surfaces of the three bumps, openings121to123of hexagonal-shape, for example, in a view from the top are formed, and as an example of the terminals16bto18b, respective nuts of the same shape are housed therein, with their female threads being directed toward the height direction.

A plurality of terminal housing sections11c1to11c3(three terminal housing sections, as an example in this embodiment) is configured by inserting the above-described terminal housing chamber12into the recess l1bof the main body11in the right direction of the figure internally through each of the external terminals16to18housed in the recess11b. At this time, the female threads of the terminals16bto18b(i.e., the nuts) housed in the terminal housing chamber12are positioned in the vertical and horizontal directions so that they communicate with the openings160to180of the external terminals16to18in the height direction. Accordingly, bolts17cand18c, as an example of fittings, may be threaded into the female threads of the terminals16bto18bthrough the openings160to180of the external terminals16to18via an additional substrate21of the oscillation suppressing circuit20below described and a conductive plate (not shown) for connecting to other semiconductor devices and the like to thereby detachably connect the additional substrate21and the conductive plate to the external terminals16to18and also removably fix them to the housing10.

The substrate13is a flat plate-like member on which semiconductor elements and the like are mounted, and, for example, Direct Copper Bonding (DCB) substrates, Active Metal Brazing (AMB) substrates and the like can be adopted. The substrate13includes an insulating plate13aand circuit layers13band13c. The insulating plate13ais a plate-like member comprising an insulating ceramic such as, for example, an aluminum nitride, silicon nitride, and aluminum oxide. For the circuit layers13band13c, a conductive metal such as, for example, copper, aluminum and the like is used, and the circuit layers13band13care provided on the lower and upper surfaces of the insulating plate13a, respectively. Also, the circuit layer13bincludes wiring patterns13b1to13b4connecting to the semiconductor elements and/or the conductive parts.

The semiconductor elements14aand15aare an example of a first and a second semiconductor elements (may also be an example of a second and a first semiconductor elements), respectively, and are switch elements made of a compound semiconductor such as, for example, SiC, etc. For this, vertical metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistor (IGBTs) and the like having electrodes on both the front and rear surfaces can be adopted. Moreover, instead of vertical elements, the semiconductor elements14aand15amay be horizontal elements having the electrodes provided only on the front surface. The semiconductor elements14aand15aare mounted on the wiring patterns13b1and13b3on the substrate13, respectively.

In the case of IGBTs (or MOSFETs), the semiconductor elements14aand15ahave emitter electrodes (a source electrode) and gate electrodes on the front surfaces, respectively and collector electrodes (a drain electrode) on the rear surfaces. The semiconductor elements14aand15aare fixed on the substrate13by bonding the rear surfaces to the wiring patterns13b1and13b3, respectively using a bonding material such as solder, etc.

The SiC diode elements14band15bare an example of a first and a second SiC diode elements (can also be an example of a second and a first SiC diode elements), respectively and are rectifier elements made of SiC. For this, as an example, vertical schottky barrier diodes (SBDs) having electrodes on both the front and rear surfaces can be adopted. Instead of vertical elements, the SiC diode elements14band15bmay be horizontal elements having the electrodes provided only on the front surface. The SiC diode elements14band15bare mounted on the wiring patterns13b1and13b3on the substrate13, respectively.

The SiC diode elements14band15bhave anode electrodes on the front surfaces and cathode electrodes on the rear surfaces. The SiC diode elements14band15bare fixed on the substrate13by bonding the rear surfaces to the wiring patterns13b1and13b3, respectively using a bonding material such as solder, etc. Accordingly, the cathode electrodes of the SiC diode elements14band15bare connected to the collector electrodes of the semiconductor elements14aand15a, respectively.

Also, the anode electrodes of the SiC diode elements14band15bare connected to the emitter electrodes of the semiconductor elements14aand15a, respectively using wires (not shown) of conductive metal such as, for example, copper, aluminum and the like or conductive alloy such as iron aluminum alloy, etc. Accordingly, the SiC diode elements14band15bare connected in anti-parallel to the semiconductor elements14aand15a, respectively thereby configuring a switching device. Moreover, the emitter electrode of the semiconductor element15ais connected to the wiring pattern13b1on the substrate13using wires (not shown). Accordingly, the semiconductor element15aand the SiC diode element15bwhich are connected in anti-parallel are connected in series to the semiconductor element14aand the SiC diode element14bwhich are connected in anti-parallel. Furthermore, the anode electrode of the SiC diode element14bis further connected to the wiring pattern13b2on the substrate13using wires (not shown), and the gate electrodes of the semiconductor elements14aand15aare connected to the wiring pattern13b4on the substrate13using wires (not shown).

The external terminals16to18are a terminal for conducting and outputting current output by the semiconductor elements14aand15ato outside the semiconductor device100, and they are formed by deforming a plate-like member of conductive metal such as, for example, copper, aluminum and the like into a U-shape in a view from the side. As described earlier, the external terminals16to18have the respective openings160to180formed on the middles of the upper surfaces, and are placed in the positions corresponding to the three terminal housing sections11c1to11c3in the recess11bof the housing10.

The conductive parts16ato18aare a conductive member, which are provided between the wiring patterns13b1to13b3on the substrate13and the external terminals16to18, respectively for carrying current output by the semiconductor elements14aand15atherebetween. As an example, a conductive metal such as copper, aluminum and the like is formed in a tabular or cylindrical shape.

The conductive parts16ato18aare erected on the substrate13by bonding the respective lower ends to the wiring patterns13b1to13b3using a bonding material such as solder, etc. or by ultrasonic bonding. And the respective upper ends of the conductive parts16ato18aare connected to the lower surfaces of the external terminals16to18by soldering, brazing, or caulking. The conductive part16aenables the collector electrode of the semiconductor element14a, the cathode electrode of the SiC diode element14b, the emitter electrode of the semiconductor element15aand the anode electrode of the SiC diode element15bto be connected to the external terminal16via the wiring pattern13b1, wires (not shown), and the terminal16b. The conductive part17aenables the emitter electrode of the semiconductor element14aand the anode electrode of the SiC diode element14bto be connected to the external terminal17via the wiring pattern13b2, wires (not shown) and the terminal17b. The conductive part18aenables the collector electrode of the semiconductor element15aand the cathode electrode of the SiC diode element15bto be connected to the external terminal18via the wiring pattern13b3and the terminal18b.

The external terminal19is a terminal for inputting control signals to the semiconductor elements14aand15afrom outside the semiconductor device100and also for outputting output signals of the semiconductor elements14aand15ato outside the semiconductor device100. For the external terminal19, a conductive metal such as, for example, copper, aluminum, and the like is formed in a tabular shape where the height direction is the longitudinal direction. The external terminal19includes four terminals and is erected on the wiring pattern13b4of the substrate13, protruding from the top surface of the housing10. Moreover, the wiring pattern13b4is connected to the gate electrodes and the emitter electrodes of the semiconductor elements14aand15avia wires (not shown). Two terminals of the external terminal19are connected to the gate electrodes of the semiconductor elements14aand15avia the wiring pattern13b4and wires (not shown) to function as gate terminals. Also, the remaining two terminals of the external terminal19are connected to the emitter electrodes of the semiconductor elements14aand15avia the wiring pattern13b4and wires (not shown) to function as emitter terminals.

FIG. 3Ashows a configuration of the oscillation suppressing circuit20in a view from the top. In the semiconductor device100incorporating SiC elements like SiC-SBD and the like, due to its high-speed operation, high frequency noise may happen, especially during turn-ons. Due to junction capacitance of the SiC-SBD, the noise is higher frequency, for example, in the range of 10 MHz to 20 MHz, so the noise may pass through and leak outside the device while very little of parasitic capacitance in the device is being attenuated. The oscillation suppressing circuit20suppresses such high frequency noise, i.e., voltage fluctuation in the SiC diode element14bcaused in response to turn-ons of the semiconductor element15aand/or voltage fluctuation (for example, high frequency noise) in the SiC diode element15bcaused in response to turn-ons of the semiconductor element14a. The oscillation suppressing circuit20has the additional substrate21, a resistor23, and a capacitor24.

The additional substrate21is a flat plate-like member incorporating the resistor23and the capacitor24for attaching the oscillation suppressing circuit20to the housing10from the outside of the housing10, and, for example, Direct Copper Bonding (DCB) substrates, Active Metal Brazing (AMB) substrates and the like as well as print substrates can be adopted for this. The additional substrate21is configured such that insulating ceramic such as, for example, an aluminum nitride, silicon nitride, and aluminum oxide is formed in a plate-like shape, and then three mutually separated wiring patterns22ato22cof conductive metal such as, for example, copper, aluminum and the like are provided on the surface. The additional substrate21has through-holes (not shown) formed on both the left side and right side of the figure for inserting the bolts17cand18cas an example of fittings.

The resistor23is a resistor element for consuming electric power of high frequency noise output by the semiconductor device100. In this embodiment, the resistor23is configured by connecting two resistor elements23aand23bin parallel and the both ends of the resistor elements23aand23bare connected to the wiring patterns22aand22bof the additional substrate21, respectively. For the resistor23here, i.e., the resistor elements23aand23b, a resilient resistance material may be formed in at least an infinitesimally deformable shape, for example, a U-shape in a view from the side, and then the both ends may be connected to different wiring patterns, respectively. Occurrences of heat stress due to transient flows of large current in the semiconductor device100or occurrences of magnetic field due to transient flows of large current in the conductive part in the semiconductor device100or in the conductive part connected to the semiconductor device100may apply stress to the external terminals16to18to which the oscillation suppressing circuit20is connected. The resilient resistor23can deform flexibly in response to mechanical vibrations of the additional substrate21and absorb the vibrations thereby maintaining good bonding of the resistor elements23aand23bto the additional substrate21, for example, thus improving reliability of the oscillation suppressing circuit20against mechanical vibrations.

The capacitor24is a capacitance element for absorbing high frequency noise electric power output by the semiconductor device100. The capacitor24is connected between the wiring patterns22band22cof the additional substrate21and serially connected to the resistor23. The capacitor24here is formed using resilient dielectric such as film, paper and the like to be at least infinitesimally deformable. Accordingly, the capacitor24can deform flexibly in response to mechanical vibrations of the additional substrate21and absorb the vibrations thereby maintaining good bonding of the capacitor24to the additional substrate21, for example, thus improving reliability of the oscillation suppressing circuit20against mechanical vibrations.

The capacitor24here has a capacitance of, for example, 100 nF, and more preferably, in the range of 1 nF to 20 nF. The resistor23has a resistance, for example, in the range of 1Ω to 10Ω. Accordingly, the oscillation suppressing circuit20suppresses voltage fluctuation in the range of 1 MHz to 100 MHz, and preferably, 10 MHz or more, and more preferably, in the range of 10 MHz to 20 MHz.

The oscillation suppressing circuit20is mounted onto the housing10where the upper surfaces of the external terminals17and18are exposed, i.e., the upper surfaces of the terminal housing sections11c2and11c3. As described earlier, the oscillation suppressing circuit20is connected together with the conductive plate between the external terminals17and18by threading the bolts17cand18c, as an example of fittings, into the female threads of the terminals17band18bhoused in the terminal housing chamber12constituting the terminal housing sections11c2and11c3, via rectangular-shaped washers27and28, respectively and further through the through-holes (not shown) provided in the additional substrate21, the conductive plate (not shown) for connecting the external terminals17and18to other semiconductor devices and the like, and the openings170and180of the external terminals17and18, and then by screwing them. Accordingly, the wiring patterns22aand22con the additional substrate21are connected to the external terminals17and18by the bolts17cand18c, respectively so that the resistor23and the capacitor24are serially connected between the external terminals17and18.

Moreover, the oscillation suppressing circuit20may be mounted on one of the side surfaces in the vertical direction of the protrusion11cof the housing10or the terminal housing chamber12constituting the terminal housing sections11c1to11c3. In such a case, the oscillation suppressing circuit20may also be configured such that, for example, a horizontally extending recess is provided on a side surface of the protrusion11cor the terminal housing chamber12, and three wires that are connected to the external terminals16to18housed correspondingly to the terminal housing sections11c1to11c3in the recess11band the resistor element and the capacitance element that are connected serially between any two of the three wires are fitted into the horizontally extending recess.

The oscillation suppressing circuit20configured as described above and a fixing means such as bolts17cand18c, etc. for fixing the oscillation suppressing circuit20to the housing10enable the oscillation suppressing circuit20having appropriate resistance and capacitance respectively for the internal circuit of the semiconductor device100to be selected, and enable it to be detachably fixed on the terminal housing sections11c1to11c3of the housing10or a side surface of the terminal housing sections11c1to11c3or the protrusion11c.

FIG. 3Bshows a variation of the configuration of the oscillation suppressing circuit20′ in a view from the top. The oscillation suppressing circuit20′ has the additional substrate21(21aand21b), resistor23, and capacitor24. For the same or corresponding parts of the constituent elements of the above-described oscillation suppressing circuit20, the same reference symbols are given and the description thereof is not repeated here.

The additional substrate21includes a first portion substrate21aand a second portion substrate21bwhich are separated from each other. The first portion substrate21amay be configured in the same manner with the additional substrate21of the oscillation suppressing circuit20, but one wiring pattern22ais provided on the front surface. Moreover, a through-hole (not shown) for inserting a bolt17cas an example of fittings is formed thereon. The second portion substrate21bmay be configured in the same manner with the additional substrate21of the oscillation suppressing circuit20, but two wiring patterns22band22cwhich are separated from each other are provided on the front surface. Moreover, a through-hole (not shown) for inserting a bolt18cas an example of fittings is formed thereon.

In this embodiment, the resistor23is configured by combining the two resistor elements23aand23bin parallel and the both ends of the resistor elements23aand23bare connected to the wiring pattern22aof the first portion substrate21aand the wiring pattern22bof the second portion substrate21b, respectively. For the resistor23here, i.e., the resistor elements23aand23b, a resilient resistance material is formed in at least an infinitesimally deformable shape, for example, U-shape in a view from the side, and then the resistor elements23aand23bare provided to straddle between the first portion substrate21aand the second portion substrate21b. Accordingly, the resistor23can deform flexibly in response to mechanical vibrations of the additional substrate21, i.e., the first portion substrate21aand the second portion substrate21b, and absorb the vibrations thereby maintaining good bonding of the resistor elements23aand23bto the additional substrate21, for example, thus improving reliability of the oscillation suppressing circuit20′ against mechanical vibrations.

The capacitor24is connected between the wiring patterns22band22cof the second portion substrate21band serially connected to the resistor23. The capacitor24here is formed using resilient dielectric such as film, paper and the like to be at least infinitesimally deformable. Accordingly the capacitor24can deform flexibly in response to mechanical vibrations of the additional substrate21and absorb the vibrations thereby maintaining good bonding of the capacitor24to the additional substrate21, for example, thus improving reliability of the oscillation suppressing circuit20′ against mechanical vibrations.

Instead of providing the resistor23to straddle between the first portion substrate21aand the second portion substrate21b, the capacitor24may be provided to straddle between them. The oscillation suppressing circuit20′ may be used alternative to or with the oscillation suppressing circuit20.

In the additional substrate21, other than separating the first portion substrate21aand the second portion substrate21bfrom each other, a slit, for example, may be provided therebetween so as to partially separate them, and the resistor23and/or capacitor24may be provided to straddle between the partially separated first portion substrate21aand the second portion substrate21b.

FIG. 4Ashows a circuit configuration of the semiconductor device100. The semiconductor elements14aand15aare serially connected between the external terminals17and18via the wiring patterns13b1to13b3, the wires (not shown), and the conductive parts17aand18a. The SiC diode element14bis connected in parallel to the semiconductor element14avia the wiring pattern13b1and wires (not shown), and the SiC diode element15bis connected in parallel to the semiconductor element15avia the wiring pattern13b3and wires (not shown). Moreover, the oscillation suppressing circuit20is connected in parallel to the semiconductor elements14aand15a(as well as the SiC diode elements14band15b) between the external terminals17and18.

In the semiconductor device100, the semiconductor elements14aand15aare turned on or off by being input control signals (switching signals contained inside) into the respective gate electrodes via the external terminal19, the wiring pattern13b4, and the wires (not shown) to supply or stop current from the external terminal18to the external terminal16or from the external terminal16to the external terminal17. Moreover, the oscillation suppressing circuit20suppresses voltage fluctuation caused in the SiC diode element14bin response to turn-ons of the semiconductor element15aand/or voltage fluctuation (for example, high frequency noise) caused in the SiC diode element15bin response to turn-ons of the semiconductor element14a.

Not only one common oscillation suppressing circuit20may be provided for the semiconductor elements14aand15b(and the SiC diode elements14band15b), but also separate oscillation suppressing circuits20may be provided to the respective semiconductor elements14a(and the SiC diode element14b) and15a(and the SiC diode element15b).

FIG. 4Bshows the first variation of the circuit configuration of the semiconductor device110. Similar to the semiconductor device100, the semiconductor elements14aand15aand the SiC diode elements14band15bare connected between the external terminals17and18. In contrast, one of the two oscillation suppressing circuits20is connected in parallel to the semiconductor element14a(and the SiC diode element14b) between the external terminals16and17, and the other is connected in parallel to the semiconductor element15a(and the SiC diode element15b) between the external terminals16and18.

In the semiconductor device110, the oscillation suppressing circuit20connected between the external terminal16and the external terminal17suppresses voltage fluctuation caused in the SiC diode element14bin response to turn-ons of the semiconductor element15a, and the oscillation suppressing circuit20connected between the external terminal16and the external terminal18suppresses voltage fluctuation caused in the SiC diode element15bin response to turn-ons of the semiconductor element14a.

In the semiconductor device110according to the variation, the oscillation suppressing circuits20may be provided to each of the semiconductor element14a(and the SiC diode element14b) and the semiconductor element15a(and the SiC diode element15b), or the oscillation suppressing circuit20may be provided to only one of them.

TheFIG. 5shows the results of transient response test on current and voltage during turn-ons of the semiconductor device in the semiconductor devices100and110. Here, in the oscillation suppressing circuit20of the semiconductor device100, 2.5Ω of resistance for the resistor23and 11 nF of capacitance for the capacitor24were adopted. This shall be an Example 1. Moreover, in the oscillation suppressing circuit20of the semiconductor device110, 6.8Ω of resistance for the resistor23and 5.2 nF of capacitance for the capacitor24were adopted. This shall be an Example 2. Furthermore, the semiconductor device100which does not include the oscillation suppressing circuit20shall be a Comparative example. In the transient response test, a wiring inductance was connected between the external terminals16and18, and a voltage source was connected between the external terminals17and18in the semiconductor device100without the oscillation suppressing circuit20(Comparative example), the semiconductor device100(Example 1) and the semiconductor device110(Example 2), respectively. And transient response characteristics of the current ICbeing supplied to the semiconductor element14aand being output from the external terminal17and the voltage VCEapplied to between the external terminals16and18when turning on the semiconductor element14a.

In Comparative example, when the semiconductor element14awas turned on, the current ICincreased progressively, showed the peak at approximately 280 ns and then turned to decrease, showed the clip at approximately 330 ns and then turned to increase again, showed the peak again at approximately 370 ns and then turned to decrease, and thereafter the current ICincreased or decreased (i.e., oscillations) repeatedly at a cycle in the range of 80 ns to 100 ns and saturated. On the other hand, the voltage VCEsurged from approximately 280 ns, showed the peak at approximately 320 ns and then turned to decrease, showed the clip at approximately 370 ns and turned to increase again, and showed the peak again at 430 ns and then turned to decrease, and thereafter the voltage VCEincreased or decreased (i.e., oscillations in the range of 10 MHz to 12.5 MHz) repeatedly at a cycle of between 80 ns and 100 ns and saturated. Here, oscillations of the current ICand voltage VCEattenuated at approximately 1200 ns.

In Example 1, when the semiconductor element14awas turned on, the current ICincreased progressively, showed the peak at approximately 280 ns and then turned to decrease, showed the clip at approximately 330 ns and then turned to increase again, and became substantially constant at approximately 350 ns. On the other hand, the voltage VCEsurged from approximately 280 ns, showed the peak at approximately 320 ns and then turned to decrease, showed the clip at approximately 380 ns and turned to increase again, and thereafter the voltage VCEincreased progressively and saturated. Oscillations of the current ICand voltage VCEhere was smaller than those of Comparative example 1 and attenuated at approximately 100 ns.

In Example 2, when the semiconductor element14awas turned on, the current ICincreased progressively, showed the peak at approximately 260 ns and then turned to decrease, showed the clip at approximately 315 ns and then turned to increase again, and showed the peak again at approximately 350 ns and then turned to decrease, and thereafter the current ICminutely increased or decreased (i.e., small oscillations) repeatedly at a short cycle of about 50 ns and saturated. On the other hand, the voltage VCEsurged from approximately 280 ns, showed the peak at approximately 310 ns and then turned to decrease, showed the clip at approximately 370 ns and turned to increase again, and thereafter the voltage VCEminutely increased or decreased (i.e., small oscillations) repeatedly at a short cycle of about 50 ns and saturated. Oscillations of the current ICand voltage VCEhere were smaller than those of Comparative example 1, but larger than those of Example 1, and attenuated at approximately 300 ns.

In the Example 1 and Example 2, very little loss of electric power by the oscillation suppressing circuit20could be confirmed.

From the above-described result of transient response test on current and voltage in response to turn-ons of the semiconductor device according to the semiconductor device100and the semiconductor device110, it could be confirmed that the oscillation suppressing circuit20in both the semiconductor devices100and110could suppress high frequency current and voltage fluctuations during turn-ons of the semiconductor elements. In other words, the oscillation suppressing circuit20can suppress higher frequency (for example, between 10 MHz and 20 MHz) noise compared to the traditional RC snubber.

In the semiconductor device100according to this embodiment and the semiconductor device110according to the first variation, a RC snubber circuit may be connected in parallel to the oscillation suppressing circuit20.

FIG. 6Ashows the second variation of the circuit configuration of the semiconductor device120. Similar to the semiconductor device100, the semiconductor elements14aand15aand the SiC diode elements14band15bare connected between the external terminals17and18, and the oscillation suppressing circuit20is connected in parallel to them between the external terminals17and18. In contrast, an RC snubber circuit30is further connected in parallel to the oscillation suppressing circuit20.

The RC snubber circuit30has a resistor33and capacitor34connected in series thereon. The capacitor34has a capacitance in the range of, for example, 400 nF to 10 μF. The resistor33has a resistance of, for example, 100Ω or more. Accordingly, the RC snubber circuit30absorbs surge voltage (Ldi/dt) caused in the wiring inductance (L) within the device due to sudden current change (di/dt) during turn-offs of the semiconductor element14aor15a. Compared to the RC snubber circuit30, the ability of the above-described oscillation suppressing circuit20to absorb this surge voltage is lower.

Instead of the RC snubber circuit30having the resistor33and the capacitor34connected serially, a C bulk snubber circuit having only a capacitor may be used.

FIG. 6Bshows the third variation of the circuit configuration of the semiconductor device130. Similar to the semiconductor device100, the semiconductor elements14aand15aand the SiC diode elements14band15bare connected between the external terminals17and18, and the oscillation suppressing circuit20is connected in parallel to them between the external terminals17and18. In contrast, a C bulk snubber circuit40is further connected in parallel to the oscillation suppressing circuit20.

The C bulk snubber circuit40has a capacitor44. The capacitor44has a capacitance in the range of, for example, 400 nF to 10 μF. Accordingly, similar to the RC snubber circuit30, the C bulk snubber circuit40can absorb surge voltage applied to them during turn-offs of the semiconductor element14aor15a.

FIG. 6Cshows the fourth variation of the circuit configuration of the semiconductor device140. Similar to the semiconductor device110, the semiconductor elements14aand15aand the SiC diode elements14band15bare connected between the external terminals17and18, and one of the two oscillation suppressing circuits20is connected in parallel to the semiconductor element14a(and the SiC diode element14b) between the external terminals16and17, and the other is connected in parallel to the semiconductor15a(and the SiC diode element15b) between the external terminals16and18. In contrast, one of the two RC snubber circuits30is further connected in parallel to one of the oscillation suppressing circuits20between the external terminals16and17, and the other of the two RC snubber circuits30is connected in parallel to the other oscillation suppressing circuit20between the external terminals16and18.

The two RC snubber circuits30are configured similar to the RC snubber circuit30in the semiconductor device120. In the semiconductor device140, the RC snubber circuit30connected between the external terminals16and17absorbs surge voltage applied to the semiconductor element14aduring turn-offs of the semiconductor element14a. The RC snubber circuit30connected between the external terminals16and18absorbs surge voltage applied to the semiconductor element15aduring turn-offs of the semiconductor element15a.

In the semiconductor device140according to the fourth variation, instead of at least one of the two RC snubber circuits30, the C bulk snubber circuit40may be used.

Although in the semiconductor device100according to this embodiment, the oscillation suppressing circuit20is fixed on the housing10(i.e., the terminal housing sections11c1to11c3), instead of this, the oscillation suppressing circuit20may be incorporated in the substrate13in which the semiconductor elements14aand15aare mounted.

Although in the semiconductor device100according to this embodiment and in the semiconductor devices110to140according to the respective variations, the two semiconductor elements14aand15bare included, a plurality of the semiconductor elements14amay be connected in series and/or in parallel between the external terminals16and17and a plurality of the semiconductor elements15amay be connected in series and/or in parallel between the external terminals16and18, for example. Similarly, a plurality of the SiC diode elements14bmay be connected in series and/or in parallel between the external terminals16and17, and a plurality of the SiC diode elements15bmay be connected in series and/or in parallel between the external terminals16and18.

Although the present invention has been explained by means of embodiments above, the technical scope of the present invention should not be restricted to the scope of the embodiments described above. It will be apparent to those skilled in the art that various modifications or improvements may be made to the embodiments. It will be apparent that such modifications and improvements shall fall into the technical scope of the present invention from the claims

As apparent from the description above, the semiconductor device and the oscillation suppressing device can be achieved according to an embodiment of the present invention.