Method of forming via hole

The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned photoresist layer is formed on the blocking layer. The patterned photoresist layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned photoresist layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of forming a via hole, and more particularly, to a method of forming a via hole by using a blocking layer.

2. Description of the Prior Art

Lithography processing, which is an essential technology when manufacturing integrated circuits, is used for defining geometries, features, lines, or shapes onto a die or wafer. In the integrated circuit making processes, lithography plays an important role in limiting feature size. By using lithography, a circuit pattern can be precisely and accurately transferred onto a die or wafer. However, with the increasing complexity and integration of the integrated circuits, conventional lithography process has met a lot of difficulties.

For example, in the process of manufacturing via holes, the pore size of the via hole and the distance between each via hole will be limited by the resolution of the photo mask. In prior art methods for producing via holes, the photo resist layer serves as an etching mask for etching the underlying dielectric layer. For the 22 nm process, the pitch (the distance of centers of two neighboring via holes) for via holes must be lower than 90 nm and the “after development inspect critical dimension” (ADICD) must be around 35-50 nm. For the current lithographic tools, it is impossible to create contact holes with pitch lower than 90 nm in one exposure. The current solution is that the desired via holes are patterned by two exposures with two photo masks on a photo resist layer, and then followed by one etching step. Thus, a via hole array with less pitch can be obtained.

By the aforementioned two exposing processes, a regular arrangement of the via hole array can be obtained. However, the method is suitable for forming the memory array, but may not be suitable for forming an integrated circuit layout which has irregular via hole arrangement.

SUMMARY OF THE INVENTION

The present invention therefore provides a method of forming a via hole, which is suitable for forming an integrated circuit layout and is able to produce via holes with smaller pore size.

First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a Mocking layer are formed on the substrate. A patterned photoresist layer is formed on the Mocking layer. The patterned photoresist layer includes a hole array wherein the area of the hole array is greater than those of the first areas. The Mocking layer in the first areas is removed by using the patterned photoresist layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first areas.

As a patterned blocking layer is employed in the present invention before the etching step for forming via holes, the via holes can be formed only in the desired region (that is, the first region) rather than other regions. Accordingly, the method provided in the present invention can produce via holes with smaller pore size by using the dual exposing processes, and on the other hand, the method in the present invention can be used in forming an integrated circuit layout with irregular via hole arrangement.

DETAILED DESCRIPTION

To provide a better understanding of the presented invention, preferred embodiments will be made in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.

Please refer toFIG. 1toFIG. 12, illustrating schematic diagrams of the method of forming via hole in the preset invention. Please refer toFIG. 1andFIG. 2, whereinFIG. 2is a cross-sectional view according toFIG. 1along line AA′. As shown inFIG. 1andFIG. 2, a substrate300is first provided. The substrate300may be a silicon substrate. In another embodiment, the substrate300may include a silicon substrate with a plurality of dielectric layers or protective layers disposed thereabove (not shown). As shown inFIG. 1, at least a first region400is defined on the substrate300. The first region400indicates the areas where the via holes will be formed within in the subsequent steps.

Subsequently, a dielectric layer302is formed on the substrate300. The forming method may include a plasma enhanced chemical vapor deposition (PECVD), a high density plasma CVD or a spin coating process, but should not be limited thereto. The dielectric layer302may include a single-layer structure or a multi-layer structure made of dielectric materials, such as silicon dioxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), undoped silicate glass (USG)borophosphosilicate glass (BPSG)FSG (fluorine-doped silicate glass), HSQ (hydrogen silsesquioxane) (SiO: H), MSQ (methyl silsesquioxane) (SiO: CH3), HOSP, H-PSSQ (hydrio polysilsesquioxane), M-PSSQ (methyl polysilsesquioxane), P-PSSQ (phenyl polysilsesquioxane), porous sol-gel or their combination, but should not be limited thereto.

Next, a blocking layer304is formed on the dielectric layer302. The forming method may include a PECVD, a high-density plasma CVD or a spin coating process. The blocking layer304may include an organic layer such as a Si-content bottom anti-reflective coating (Si-content BARC) layer.

As shown inFIG. 3, the blocking layer304is patterned to remove the portion of the blocking layer304in the first region400, thereby forming a patterned blocking layer306. For example, a photoresist layer (not shown) is formed on the blocking layer304, followed by a lithography process to remove the photoresist layer in the first region400. An etching step is carried out by using the patterned photoresist layer as a mask to remove the blocking layer304within the first region of400. The photoresist layer is then removed. By using appropriate etchant or etching recipe, the etching rate of the Mocking layer304is greater than that of the dielectric layer302. Accordingly, the patterning process toward the Mocking layer304can be performed without etching away the dielectric layer302.

As shown inFIG. 4, a first photoresist layer308is formed on the patterned blocking layer306. In one embodiment of the present invention, the first photoresist layer308includes positive photoresist material. Then, a first exposing process is performed by using a first mask (not shown) to expose the first photoresist layer308. The first mask may include a plurality of first stripe patterns402. Please refer toFIG. 5which shows the relative position of the first stripe patterns and the below first photoresist layer308when using the first mask to perform the first exposing process. As shown inFIG. 5, each first stripe pattern402is parallel to each other. It is understood that the first photoresist layer308in the region covered by the first stripe pattern will not be subjected to the first exposing process. Then, a first development process is performed to remove the first photoresist layer308not covered by the first stripe pattern402.

Then, as shown inFIG. 6, a second photoresist layer309is formed on the patterned first photoresist layer308. Then, a planarization process is carried out such that the first photoresist layer308and the second photoresist layer309form a zebra-crossing arrangement as shown inFIG. 6. It is noted that the second photoresist layer309includes positive photoresist material, and the second photoresist layer309and the first photoresist layer308are not dissolvable to each other.

As shown inFIG. 7, a second exposing process is performed by using a second mask (not shown) to expose the second photoresist layer309. The second mask includes a plurality of second stripe patterns404which are parallel to each other. In one embodiment of the present invention, the first stripe patterns402interlace with the second stripe pattern404in a 45-degree or 60-degree intersection. In one preferred embodiment, the first stripe patterns402are substantially perpendicular to the second stripe patterns404. The areas not covered by the first stripe pattern402and the second stripe pattern404are called areas D. Because the light source in the second exposing process only functions on the second photoresist layer309instead of the first photoresist layer308, only the second photoresist layer309in areas D is exposed during the second exposing process.

Please refer toFIG. 8andFIG. 9, whereinFIG. 9is a cross-sectional view according toFIG. 8along line AA′. As shown inFIG. 8andFIG. 9, a second development process is performed to remove the second photoresist layer309in areas D, thereby forming a patterned photoresist layer310. It is understood that the patterned photoresist layer310is consisted of the first photoresist layer308and the second photoresist layer309. The patterned photoresist layer310includes a plurality of holes arranged in a regular array (hole array). It is noted that, only the holes312in the first region400would expose the under-lied dielectric layer302. The holes312in the regions other than the first region400would be blocked by the patterned blocking layer306and cannot expose the dielectric layer302.

Besides the aforementioned method which uses the first photoresist layer308and the second photoresist layer309in conjugation of two exposing processes and two development processes, in another embodiment, the patterned photoresist layer310can also be formed by using one photoresist layer in conjugation of two exposing processes and one development process, or, by directly using a mask having the first stripe patterns402plus the second stripe patterns404. It is understood that the patterned photoresist layer310can be formed by other methods. Any methods that can form the patterned photoresist layer310with holes in a regular array may be built falls within the spirit and the scope of the present invention.

As shown inFIG. 10, an etching process is performed by using the patterned photoresist layer310as a mask to form a plurality of via holes314in the dielectric layer302only within the first region400. Next, please refer toFIGS. 11 and 12whereinFIG. 12is a cross-sectional view according toFIG. 11along line AA′. The blocking layer306is then removed, and a dielectric layer302with a plurality of via holes314only in the first regions400can be obtained.

In light of above, as a patterned blocking layer is employed in the present invention before the etching step for forming via holes, the via holes can be formed only in the desired region (that is, the first region) rather than other regions. Accordingly, the method provided in the present invention can produce via holes with smaller pore size by using the dual exposing processes and on the other hand, the method in the present invention can be used in forming an integrated circuit layout with irregular via hole arrangement.