POWER CABLE WITH DIFFERENT TYPES OF CONNECTORS

Disclosed herein are a power cable and a power supply system including the power cable. The power cable includes a 12VHPWR connector disposed at a first end of the power cable; a plurality of PCIE 2×4 connectors disposed at a second end of the power cable; and a converting circuit coupled with the 12VHPWR connector via a first cable and coupled with the plurality of the PCIE 2×4 connectors via a plurality of second cables. The converting circuit includes at least one AND gate configured to couple sensing pins of the plurality of PCIE 2×4 connectors with a sensing pin of the 12VHPWR connector.

TECHNICAL FIELD

Embodiments of the present invention generally relate to a power cable including two different types of connectors and, more particularly, relate to a power cable comprising a Peripheral Component Interconnect Express (PCIE) 12VHPWR connector at one end and a plurality of PCIE 2×4 connectors at another end.

BACKGROUND

Recently developed graphic cards may briefly surge its power consumption up to 3 times of a regular operation. To meet this demand of power surge, an Advanced Technology Extended (ATX) 3.0 power supply specification was developed and introduced in 2022 to support next-generation hardware. The ATX 3.0 specification includes a PCIE 12VHPWR auxiliary power connector (“12VHPWR Connector”) to supply 12 Volt power to graphics cards. A PCIE 5.0 The 12VHPWR Connector can provide up to 600 watts to a PCIE 5.0 add-in/graphics card.FIGS.1aand1billustrate pinouts and functions of a 12VHPWR Connector.

Now turning toFIGS.1aand1b, the 12VHPWR Connector100includes a sideband section102containing four sensing pins and a main section104containing six COM pins and six power pins arranged in two rows, respectively. The COM pins are configured for data communication, and the power pins are configured for power transmission. The 6 power pins are labeled1-6, respectively, and the six COM pins are labeled7-12, respectively. As shown inFIG.1b, the four sensing pins are labeled S1, S2, S3, and S4, respectively, where S1and S2transmit signals from a graphic card to a power supply unit. The sensing pins S3and S4provide sensing signals Sense0and Sense1, respectively, from a power supply unit to a graphic card. A logical combination of Sense0and Sense1signals, shown in the table below, tells the graphic card the amount of power that can be drawn.

Hardware configurations complied with earlier power management standards, such as ATX 2.0, have been widely adopted and are not fully compatible with the ATX 3.0 specification. For example, many existing power supply units include PCIE 2×4 auxiliary power connector (“PCIE 2×4 Connector”). A PCIE 2×4 Connector can supply up to 150 Watts per 2×4 auxiliary power connector.

Shown inFIGS.2aand2b, a PCIE 2×4 Connector includes eight pins arranged in two rows202and204. The eight pins include three power pins, O-1, O-2, and O-3; and three COM pins O-5, O-7, and O-8. The eight pins also include two sensing pins: O-4and O-6for generate Sense1and Sense0signals, respectively. When the PCIE 2×4 Connector is connected to a power supply unit, both O-4and O-6pins provide GROUND signals. When the PCIE 2×4 Connector is not connected to a power supply unit, both O-4and O-6pins provide OPEN signals. As the pinouts and functions of the PCIE 2×4 Connector200are different from the 12VHPWR Connector100, the existing power supply units with PCIE 2×4 Connectors cannot be used to directly supply powers to the next-generation graphics card.

Therefore, a need exists for an improved power cable that can connect the existing power supply with next-generation graphics cards.

SUMMARY

Disclosed herein are a power cable and a power supply system including the power cable. The power cable includes a 12VHPWR connector disposed at a first end of the power cable; a plurality of PCIE 2×4 connectors disposed at a second end of the power cable; and a converting circuit coupled with the 12VHPWR connector via a first cable and the plurality of the PCIE 2×4 connectors via a plurality of second cables. The converting circuit includes at least one AND gate configured to couple sensing pins of the plurality of PCIE 2×4 connectors with a sensing pin of the 12VHPWR connector.

Disclosed herein is a method of coupling a plurality of PCIE 2×4 connectors with a 12VHPWR connector. The method includes cascading one or more AND gates, coupling the power pins of the plurality of PCIE 2×4 connectors with the power pins of the 12VHPWR connector, and selectively coupling No. 4 and/or 6 sensing pins of the plurality of PCIE 2×4 connector with sensing pins S3and/or S4of the 12VHPWR connector via the one or more cascaded AND gates. For example, when two PCIE 2×4 connectors are coupled with the 12VHPWR connector, the one or more cascaded AND gates only couple the No. 6 sensing pins of the two PCIE 2×4 connectors with the sensing pin S3of the 12VHPWR connector. When three PCIE 2×4 connectors are coupled with the 12VHPWR connector, the one or more cascaded AND gates only couple the No. 4 sensing pins of the three PCIE 2×4 connectors with the sensing pin S4of the 12VHPWR connector. When four PCIE 2×4 connectors are coupled with the 12VHPWR connector, the one or more cascaded AND gates couple both the No. 6 sensing pins of the four PCIE 2×4 connectors with the sensing pin S3of the 12VHPWR connector and the No. 4 sensing pins of the four PCIE 2×4 connectors with the sensing pin S4of the 12VHPWR connector.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments.

DETAILED DESCRIPTION

Disclosed herein is a power cable including a 12VHPWR connector disposed at a first end and a plurality of PCIE 2×4 connectors disposed at a second end. The power cable further includes a converting circuit coupled with the 12VHPWR connector and the plurality of the PCIE 2×4 connectors. The converting circuit is configured to covert sensing signals provided by the PCIE 2×4 connectors to sensing signals for the 12VHPWR connector. In this way, the power cable allows an existing supply to provide power to recently introduced graphics cards that utilize a 12VHPWR connector to supply power.

The converting circuit processes the sensing signals according to the number of PCIE 2×4 connectors that are used to supply power. When four PCIE 2×4 connectors are used to supply power, the converting circuit generates two GROUND sensing signals for the 12VHPWR connector, which indicates a maximum power of 600 Watts may be drawn. When three PCIE 2×4 connectors are used to supply power, the converting circuit generates an OPEN signal for the S3sensing pin and a GROUND signal for the S4sensing pin of the 12VHPWR connector, indicating a maximum power of 450 Watts may be drawn. When two PCIE 2×4 connectors are used to supply power, the converting circuit generates a GROUND signal for the S3sensing pin and an OPEN signal for the S4sensing pin of the 12VHPWR connector, indicating a maximum power of 300 Watts may be drawn. According to an embodiment, AND gates are included in the converting circuit to process sensing signals from the PCIE 2×4 connectors.

Turning now toFIG.3a, a power cable301is provided that includes a 12VHPWR Connector100at a first end308and four PCIE 2×4 Connectors200-1,200-2,200-3,200-4at a second end310. The power cable300may include a greater or less number of PCIE Connectors at the second end310, such as three or two connectors (FIGS.3band3c). The power cable301further includes a converting circuit302coupled with the 12VHPWR Connector100via a first cable304at one end and coupled with the PCIE 2×4 Connectors200via a plurality of second cables306at another end. The first cable304is compatible with the 12VHPWR Connector100and includes 16 wires: six for power pins, six for COM pins, and four for sensing pins. Each of the second cables306is compatible with the PCIE 2×4 Connector and includes eight wires: three for power pins, three for COM pins, and two for sensing pins. According to an embodiment, the first cable304has a higher power rating than each of the second cable306.

The converting circuit302couples the power pins of the PCIE 2×4 Connectors with the power pins of the 12VHPWR Connector. The converting circuit302also couples the COM pins of the PCIE 2×4 Connectors with the COM pins of the 12VHPWR Connector. The converting circuit302also couples the sensing pins of the PCIE 2×4 Connectors with the sensing pins of the 12VHPWR Connector. According to an embodiment, the converting circuit302is configured to process sensing signals provided by the PCIE 2×4 Connectors and generate sensing signals that indicate a first level of maximum power, such as 600 Watts, can be drawn.

FIG.3billustrates a power cable303including a 12VHPWR Connector100at a first end308and three PCIE 2×4 Connectors200-1,200-2,200-3at a second end310. The power cable303further includes a converting circuit312coupled with the 12VHPWR Connector100and the PCIE 2×4 Connectors200. The converting circuit312couples the power pins and COM pins of the PCIE 2×4 Connectors with those of the 12VHPWR Connector. The converting circuit312also couples the sensing pins of the PCIE 2×4 Connectors with the sensing pins of the 12VHPWR Connector. According to an embodiment, the converting circuit312is configured to process sensing signals provided by the PCIE 2×4 Connectors and generate sensing signals that indicate a second level of maximum power, such as 450 Watts, can be drawn.

FIG.3cillustrates a power cable305including a 12VHPWR Connector100at a first end308and two PCIE 2×4 Connectors200-1,200-2at a second end310. The power cable305further includes a converting circuit314coupled with the 12VHPWR Connector100and the PCIE 2×4 Connectors200. The converting circuit314couples the power pins of the PCIE 2×4 Connectors with the power pins of the 12VHPWR Connector. The converting circuit312also couples the sensing pins of the PCIE 2×4 Connectors with the sensing pins of the 12VHPWR Connector. According to an embodiment, the converting circuit314is configured to process sensing signals provided by the PCIE 2×4 Connectors and generate sensing signals that indicate a third level of maximum power, such as 300 Watts, can be drawn.

FIG.4aillustrates a schematic circuit diagram401of the power cable301, according to an embodiment. The circuit diagram401shows the electrical connection between a 12VHPWR Connector100and four PCIE 2×4 Connectors200-1,200-2,200-3, and200-4. The power pins Nos. 1-3 of the four PCIE 2×4 Connectors200-1,200-2,200-3, and200-4are coupled with the power pins Nos. 1-6 of the 12VHPWR Connector100. The COM pins Nos. 5, 7, and 8 of the four PCIE 2×4 Connectors200-1,200-2,200-3, and200-4are coupled with the COM pins Nos. 7-12 of the 12VHPWR Connector100.

According to an embodiment, the sensing pin S3of the 12VHPWR Connector100is coupled with No. 6 sensing pins of the PCIE 2×4 Connectors200-1,200-2,200-3, and200-4. Both the sensing pin S3and No. 6 sensing pin provide the sensing signal Sense0. A plurality of AND gates arranged in a cascade manner are configured to process the sensing signals Sense0generated by the PCIE 2×4 Connectors. For example, an AND gate404receives sensing signals from No. 6 sensing pins of the PCIE 2×4 Connectors200-1and200-2and outputs a sensing signal to an AND gate424. An AND gate414receives sensing signals from No. 6 sensing pins of the PCIE 2×4 Connectors200-3and200-4and outputs a sensing signal to the AND gate424. The AND gate424receives the sensing signals from the AND gates404and414and outputs another sensing signal to the sensing pin S3of the 12VHPWR Connector100.

The sensing pin S4of the 12VHPWR Connector100is coupled with sensing pins No. 4 of the PCIE 2×4 Connectors200-1,200-2,200-3, and200-4. Both the sensing pin S4and No. 4 sensing pin provide the sensing signal Sense1. A plurality of AND gates arranged in a cascade manner are configured to process the sensing signals Sense1generated by the PCIE 2×4 Connectors. For example, an AND gate402receives sensing signals from No. 4 sensing pins No. 4 of the PCIE 2×4 Connectors200-1and200-2and outputs a sensing signal to an AND gate422. An AND gate412receives sensing signals from No. 4 sensing pins of the PCIE 2×4 Connectors200-3and200-4and outputs a sensing signal to the AND gate422. The AND gate422receives the sensing signals from the AND gates402and412and outputs another sensing signal to the sensing pin S4of the 12VHPWR Connector100.

In operation, when the four PCIE 2×4 Connectors200-1,200-2,200-3, and200-4are plugged into a power supply unit, all Nos. 4 and 6 sensing pins transmit GROUND signals. As a result, the sensing signals of both the sensing pins S3and S4are GROUND signals, which indicate a maximum power of 600 Watts according to the ATX3.0 standard.

FIG.4billustrates a schematic circuit diagram403of the power cable303, according to an embodiment. The circuit diagram403shows the electrical connection between a 12VHPWR Connector100and three PCIE 2×4 Connectors200-1,200-2, and200-3. The power pins Nos. 1-3 of the three PCIE 2×4 Connectors are coupled with the power pins Nos. 1-6 of the 12VHPWR Connector100. The COM pins Nos. 5, 7, and 8 of the three PCIE 2×4 Connectors200-1,200-2, and200-3are coupled with the COM pins Nos. 7-12 of the 12VHPWR Connector100.

According to an embodiment, the sensing pin S4of the 12VHPWR Connector100is coupled with No. 4 sensing pins of the PCIE 2×4 Connectors. Both the sensing pin S4and the No. 4 sensing pin provide the sensing signal Sense1. A plurality of AND gates arranged in a cascade manner are configured to process the sensing signals Sense1generated by the PCIE 2×4 Connectors. For example, an AND gate426receives sensing signals from No. 4 sensing pins of the PCIE 2×4 Connectors200-1and200-2and outputs a sensing signal to an AND gate428. The AND gate423receives sensing signals from No. 4 sensing pin of the PCIE 2×4 Connectors200-3and the output signal of the AND gate426. The AND gate428outputs a sensing signal to the sensing pin S4of the 12VHPWR Connector100.

The sensing pin S3of the 12VHPWR Connector100is decoupled from sensing pins No. 6 of the PCIE 2×4 Connectors. As a result, the sensing pin S3has an OPEN sensing signal.

In operation, when the three PCIE 2×4 Connectors200-1,200-2, and200-3are plugged into a power supply unit, all No. 6 sensing pins produce GROUND signals. As a result, the sensing signal of the sensing pin S4is a GROUND signal. At the meantime, the sensing signal of the sensing pin S3is an OPEN signal. Thus, the sensing signals of S3and S4indicate a maximum power of 450 Watts according to the ATX3.0 standard.

FIG.4cillustrates a schematic circuit diagram405of the power cable305, according to an embodiment. The circuit diagram405shows the electrical connection between a 12VHPWR Connector100and two PCIE 2×4 Connectors200-1, and200-2. The power pins Nos. 1-3 of the two PCIE 2×4 Connectors are coupled with the power pins Nos. 1-6 of the 12VHPWR Connector100. The COM pins Nos. 5, 7, and 8 of the two PCIE 2×4 Connectors200-1,200-2are coupled with the COM pins Nos. 7-12 of the 12VHPWR connector100.

According to an embodiment, the sensing pin S3of the 12VHPWR Connector100is coupled with No. 6 sensing pins of the PCIE 2×4 Connectors. Both the sensing pin S3and the No. 6 sensing pin provide the sensing signal Sense0. A single AND gate is configured to process the sensing signals Sense0transmitted by the PCIE 2×4 Connectors. For example, an AND gate430receives sensing signals from No. 6 sensing pins of the PCIE 2×4 Connectors200-1and200-2and outputs a sensing signal to the sensing pin S4of the 12VHPWR Connector100.

The sensing pin S4of the 12VHPWR Connector100is decoupled from sensing pins No. 4 of the PCIE 2×4 Connectors. As a result, the sensing pin S4has an OPEN sensing signal.

In operation, when the two PCIE 2×4 Connectors200-1and200-2are plugged into a power supply unit, both No. 4 sensing pins transmit GROUND signals. As a result, the sensing signal of the sensing pin S3is a GROUND signal. In the meantime, the sensing signal of the sensing pin S4is an OPEN signal. Thus, the sensing signals of S3and S4indicate a maximum power of 300 Watts according to the ATX3.0 standard.

Turning now toFIG.5, a power supply system500includes a power supply unit502, a power cable508, and an electronic device504. The power supply unit502may be an ATX 2.0 power supply unit or other suitable power supply unit. The electronic device504may be a graphics card or other processing unit, such as a PCIE 5.0 desktop graphics cards. The 12VHPWR Connector100of the power cable508couples with a mating port506disposed at the electronic device504. The PCIE 2×4 Connectors couple with the power supply unit502and transmits power from the power supply unit502to the power cable300. The power supply unit502includes mating ports510that are compatible with the PCIE 2×4 Connectors. The power cable508may be anyone of the power cables301,303, and305. The power cable508enables an ATX2.0 power supply unit to supply up to 600 Watts of power to the electronic device504.

FIG.6illustrates a method of coupling a plurality of PCIE 2×4 connectors with a 12VHPWR connector, according to an embodiment of the present application. The method600includes an operation602that cascades one or more AND gates. The one or more AND gates may include one, two, three, or more AND gates. The one or more AND gates are cascaded such that each AND gate receives two inputs from the PCIE 2×4 connectors and provides one output to another AND gate or the 12VHPWR connector.

In operation604, the power pins of the plurality of PCIE 2×4 connectors are coupled with the power pins of the 12VHPWR connector. For example, the Nos. 1-3 pins of the PCIE 2×4 connectors are directly connected with the Nos. 1-6 pins of the 12VHPWR connector.

In operation606, No. 4 and/or 6 sensing pins of the plurality of PCIE 2×4 connector are selectively coupled with sensing pins S3and/or S4of the 12VHPWR connector via the one or more cascaded AND gates. For example, when two PCIE 2×4 connectors are coupled with the 12VHPWR connector, the one or more cascaded AND gates only couple the No. 6 sensing pins of the two PCIE 2×4 connectors with the sensing pin S3of the 12VHPWR connector. The No. 4 sensing pins of the two PCIE 2×4 connectors are not coupled with the sensing pin S4of the 12VHPWR connector. When three PCIE 2×4 connectors are coupled with the 12VHPWR connector, the one or more cascaded AND gates only couple the No. 4 sensing pins of the three PCIE 2×4 connectors with the sensing pin S4of the 12VHPWR connector. The No. 6 sensing pins of the three PCIE 2×4 connectors are not coupled with the sensing pin S3of the 12VHPWR connector. When four PCIE 2×4 connectors are coupled with the 12VHPWR connector, the one or more cascaded AND gates couple both the No. 6 sensing pins of the four PCIE 2×4 connectors with the sensing pin S3of the 12VHPWR connector and the No. 4 sensing pins of the four PCIE 2×4 connectors with the sensing pin S4of the 12VHPWR connector.