Array substrate, method of making array substrate and display device having sub-pixels with transparent etching layer

Embodiments of the present disclosure provide an array substrate, a method for manufacturing an array substrate, a display panel, and a display device. The array substrate includes a plurality of pixels, each of the pixels includes a plurality of sub-pixels, wherein each of the plurality of sub-pixels includes a base substrate, an insulating layer, a color filter layer, a planarization layer, and an organic light emitting unit, and wherein the insulating layer covers the base substrate, the insulating layer is provided with a first opening, at least a portion of the color filter layer is filled in the first opening, the planarization layer covers over the insulating layer and a surface of the color filter layer, and the organic light emitting unit is disposed on the planarization layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority of Chinese Patent Application No. 201811115483.4 filed on Sep. 25, 2018 in China National Intellectual Property Administration, the disclosure of which is incorporated herein by reference in entirety.

TECHNICAL FIELD

Embodiments of the present disclosure relate to the field of display technology, and in particular, to an array substrate, a method for manufacturing an array substrate, a display panel, and a display device.

BACKGROUND

Organic Light Emitting Diode (OLED) display devices have various advantages such as white light emission, low driving voltage, high luminous efficiency, short response time, high definition and contrast ratio, nearly 180° viewing angle, wide working temperature range, flexible display and large-area full-color display, and so on, and therefore they are recognized as the most promising display devices by the industry.

Among them, the contrast ratio is an important parameter of OLED, and a higher contrast ratio can give users a good visual experience. The contrast ratio of the display device refers to a value obtained by dividing a brightness of a white picture (in a brightest state) by a brightness of a black picture (in a darkest state). It can be seen that increasing the maximum display brightness is of great significance for improving the contrast ratio.

SUMMARY

In a first aspect, some embodiments of the present disclosure provide an array substrate comprising a plurality of pixels, each of the pixels comprising a plurality of sub-pixels,

wherein each of the plurality of sub-pixels comprises a base substrate, an insulating layer, a color filter layer, a planarization layer, and an organic light emitting unit, and

wherein the insulating layer covers the base substrate, the insulating layer is provided with a first opening, at least a portion of the color filter layer is filled in the first opening, the planarization layer covers over the insulating layer and a surface of the color filter layer, and the organic light emitting unit is disposed on the planarization layer.

According to some embodiments of the present disclosure, the first opening extends through the insulating layer.

According to some embodiments of the present disclosure, the first opening extends into the insulating layer but does not extend through the insulating layer.

According to some embodiments of the present disclosure, each of the plurality of sub-pixels further comprises a transparent etching barrier layer between the color filter layer and the base substrate.

According to some embodiments of the present disclosure, each of the plurality of sub-pixels further comprises a light shielding layer covering the base substrate, and a top gate thin film transistor, the top gate thin film transistor comprising a gate electrode, a source electrode, a drain electrode, an active layer and a gate insulating layer.

According to some embodiments of the present disclosure, each of the plurality of sub-pixels further comprises a pixel capacitor, the pixel capacitor comprising a first electrically conductive layer and a second electrically conductive layer;

wherein the first electrically conductive layer covers the base substrate, the first electrically conductive layer is electrically connected to the drain electrode, and first electrically conductive layers of two adjacent ones of the plurality of sub-pixels are insulated from each other; and

wherein the second electrically conductive layer and the drain electrode cover a same layer, and the second electrically conductive layer is electrically connected to the gate electrode.

According to some embodiments of the present disclosure, the light shielding layer covers the first electrically conductive layer and is electrically connected to the first electrically conductive layer, and the light shielding layer is electrically connected to the drain electrode.

According to some embodiments of the present disclosure, each of the plurality of sub-pixels further comprises a passivation layer covering surfaces of the source electrode, the drain electrode and the second electrically conductive layer; and

the insulating layer comprises a buffer layer and the passivation layer, the buffer layer covering a surface of the light shielding layer, the planarization covering the passivation layer.

According to some embodiments of the present disclosure, the organic light emitting unit comprises a transparent electrode, at least a portion of the transparent electrode covering the planarization layer, the transparent electrode being electrically connected to the first electrically conductive layer, the transparent electrode comprising a first region, and

wherein an orthographic projection of the first region on the base substrate at least partially overlaps with an orthographic projection of the second electrically conductive layer on the base substrate.

According to some embodiments of the present disclosure, the planarization layer is provided with a second opening extending through the planarization layer, and the first region covers the passivation layer and is located in the second opening.

According to some embodiments of the present disclosure, the organic light emitting unit further comprises an organic light emitting layer disposed on the transparent electrode and an electrode disposed on the organic light emitting layer.

According to some embodiments of the present disclosure, the insulating layer comprises a buffer layer, an interlayer dielectric layer covering the buffer layer, and a passivation layer covering the interlayer dielectric layer, and

wherein a first sub-opening is provided in the buffer layer, a second sub-opening is provided in the interlayer dielectric layer, and a third sub-opening is provided in the passivation layer.

In a second aspect, some embodiments of the present disclosure provide a display panel, comprising the array substrate according to the first aspect.

In a third aspect, some embodiments of the present disclosure provide a display device, comprising the display panel according to the second aspect.

In a fourth aspect, some embodiments of the present disclosure provide a method for manufacturing an array substrate, comprising:

providing a base substrate;

forming an insulating layer on the base substrate;

forming a first opening in the insulating layer;

forming a color filter layer such that at least a portion of the color filter layer is filled in the first opening;

forming a planarization layer on the insulating layer to cover a surface of the color filter layer; and

forming an organic light emitting unit on the planarization layer.

According to some embodiments of the present disclosure, before forming the insulating layer on the base substrate, the method further comprises:

applying a conductive film on the base substrate and patterning the conductive film to form first electrically conductive layers, wherein the first electrically conductive layers located in two adjacent sub-pixel regions are spaced apart from each other; and

applying a light shielding film on the base substrate and patterning the light shielding film to form a light shielding layer.

According to some embodiments of the present disclosure, the forming an insulating layer on the base substrate comprises:

forming a buffer layer on the base substrate to cover surfaces of the first electrically conductive layer and the light shielding layer;

forming a top gate thin film transistor on the buffer layer, wherein the top gate thin film transistor comprises a gate electrode, a source electrode, a drain electrode, an active layer and a gate insulating layer, the drain electrode being electrically connected to the first electrically conductive layer through a first via hole;

forming a second electrically conductive layer over the interlayer dielectric layer covered by the source electrode and the drain electrode, so that the second electrically conductive layer and the first electrically conductive layer form a pixel capacitor therebetween; and

forming a passivation layer on the interlayer dielectric layer to cover surfaces of the source electrode, the drain electrode, and the second electrically conductive layer,

wherein the insulating layer comprises the buffer layer, the interlayer dielectric layer, and the passivation layer.

According to some embodiments of the present disclosure, the forming an organic light emitting unit on the planarization layer comprises:

forming a second via hole, which extends through the planarization layer, the passivation layer and the interlayer dielectric layer, and is in communication with the first electrically conductive layer;

forming a transparent electrode, at least a portion of which is located on the planarization layer, such that the transparent electrode is electrically connected to the first electrically conductive layer through the second via hole, and an orthographic projection of a first region of the transparent electrode on the base substrate at least partially overlaps with an orthographic projection of the second electrically conductive layer on the base substrate.

According to some embodiments of the present disclosure, the forming the transparent electrode comprises:

forming a second opening, which extends through the planarization layer, in the planarization layer; and

forming the transparent electrode such that the first region covers the passivation layer and is located within the second opening.

According to some embodiments of the present disclosure, before forming the insulating layer on the base substrate, the method further comprises:

forming a transparent etching barrier layer on the base substrate.

DETAILED DESCRIPTION OF EMBODIMENTS

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It is obvious that the described embodiments represent a part of the present disclosure, but not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without any creative efforts fall within the scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms “center”, “upper”, “lower”, “front”, “rear”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer” and the like, which indicate orientation or positional relationships, are understood based on the orientation or positional relationships shown in the drawings, they are merely used for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or component referred to must have a particular orientation, and be constructed and operated in a particular orientation, and therefore they should not be construed as limiting the present disclosure.

In the description of the present disclosure, it should be noted that the terms “install”, “couple”, and “connect” should be understood broadly, and may for example refer to a fixed connection, or a detachable connection, or an integral connection, unless otherwise explicitly specified and defined. The specific meanings of the above terms in the present disclosure should be understood by those skilled in the art according to the specific conditions.

The terms “first” and “second” are only used for the purpose of description and should not be construed as indicating or implying a relative importance or implicitly indicating the number of technical features referred to. Thus, the feature defined by “first” or “second” may include one or more said features either explicitly or implicitly. In the description of the present disclosure, the expression “a plurality of” means two or more unless otherwise stated.

An array substrate of an OLED according to the related art is shown inFIG. 1, it includes a plurality of pixels, and each of the pixels includes a plurality of sub-pixels. For each sub-pixel, it includes a base substrate01, an insulating layer02, a color filter layer03, a planarization layer04, and an organic light emitting unit05arranged in a thickness direction of the array substrate perpendicular to the array substrate.

For the array substrate in the related art, in operation, the light emitted by an organic light emitting unit05needs to pass through the planarization layer04, the color filter layer03, the insulating layer02(for example, a passivation layer023, a interlayer dielectric layer022and a buffer layer021shown inFIG. 1) and other film layers. The brightness of the light emitted by the organic light emitting unit05is attenuated due to the absorption of the light emitted by the organic light emitting unit05by the various film layers, thus it is unfavorable for improving the display brightness of the OLED.

The embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, a display panel, and a display device for solving the problem that the brightness of the light emitted by the organic light emitting unit in the array substrate in the related art is greatly attenuated.

In a first aspect, an embodiment of the present disclosure provides an array substrate including a plurality of pixels, and each of the pixels includes a plurality of sub-pixels. For each sub-pixel, as shown inFIG. 2, it includes a base substrate1, an insulating layer2, a color filter layer3, a planarization layer4, and an organic light emitting unit5. The insulating layer2covers the base substrate1, the insulating layer2is provided with a first opening20, at least a portion of the color filter layer3(CF layer) is filled in the first opening20, the planarization layer4covers the insulating layer2and a surface of the color filter layer3, and the organic light emitting unit5is disposed on the planarization layer4.

The color filter layer3may be partially located in the first opening20(for example as shown inFIG. 2), or may be completely located in the first opening20. It will not be specifically limited herein.

In the array substrate provided by the embodiments of the present disclosure as shown inFIG. 2andFIG. 3, since the insulating layer2is provided with a first opening20, and at least a portion of the color filter layer3is filled in the first opening20, a height difference between the color filter layer3and the base substrate1is reduced in case where the thickness of the color filter layer3is constant, and at least a portion of the color filter layer3is overlapped with the insulating layer2, thereby greatly reducing the height of the color filter layer3protruding from the insulating layer2. In this case, it is unnecessary to make the planarization layer4too thick, to cover the surface of the color filter layer3protruding from the surface of the insulating layer2, thus the thickness of the planarization layer4can be greatly reduced. The reduction of the thickness of the planarization layer4can effectively shorten the light exit path of the light emitted from the organic light emitting unit5, and reduce the absorption of the light emitted by the organic light emitting unit5by respective film layers, thereby facilitating the improvement of the highest brightness of the light emitted by the organic light emitting unit5, and further facilitating the improvement of the contrast ratio of the display device and allowing the user to obtain a better visual experience.

In the above embodiments, the forms of the first opening20are various. For example, the first opening20may extend through the insulating layer2, as shown inFIG. 2, the insulating layer2includes a buffer layer21covering the base substrate1, an interlayer dielectric layer22(ILD) covering the buffer layer21, and a passivation layer23(PVX) covering the interlayer dielectric layer22, and the first opening20extends through the buffer layer21, the interlayer dielectric layer22and the passivation layer23. Alternatively, the first opening20may not extend through the whole insulating layer2, for example, the first opening20may extend through the interlayer dielectric layer22and the passivation layer23. Compared with the arrangement that the first opening does not extend through the insulating layer2, the arrangement that the first opening20extends through the insulating layer2has the following advantages: (1) in case where the thickness of the color filter layer3is constant, the arrangement that the first opening extends through the insulating layer2can further reduce the height difference between the color filter layer3and the base substrates1, further reduce the height of the color filter layer3protruding from the insulating layer2, and thus further reduce the thickness of the planarization layer4, shorten the light exit path of the light emitted from the organic light emitting unit5, thereby facilitating the further improvement of the highest brightness of the light emitted from the organic light emitting unit5; (2) it reduces the number of insulating sub-layers through which the light emitted by an organic light emitting layer53passes, for example the light emitted by the organic light emitting layer53shown inFIG. 2just needs to pass through the planarization layer4and the color filter layer3, thus it avoids the light emitted from the organic light emitting layer53from being absorbed, refracted when the light passes through different insulating sub-layers (for example, the interlayer dielectric layer22, the buffer layer21, the passivation layer23), thereby the brightness of the light emitted from the organic light emitting unit5can be increased.

In order to avoid the base substrate1from being etched when the first opening20is formed, as shown inFIG. 2, the sub-pixel further includes a transparent etching barrier layer6located between the color filter layer3and the base substrate1. In this way, when the first opening20is formed by etching (for example, a dry etching process) the insulating layer2, the transparent etching barrier layer6can protect the base substrate1covered thereby to avoid the base substrate1from being etched.

The transparent etching barrier layer6may be an ITO layer. The first opening20is generally formed by dry etching. Since the ITO layer is not affected by the dry etching, the ITO layer can serve as blocking the base substrate1from being etched. In order to reduce the absorption of the light emitted from the organic light emitting layer53, the thickness of the ITO layer could be made as small as possible while satisfying the etching barrier function.

As shown inFIG. 2, the sub-pixel further includes a light shielding layer7(SH layer) covering the base substrate1, a buffer layer21covering the base substrate1and a surface of the light shielding layer7, and a top gate thin film transistor9disposed on the buffer layer21. The top gate thin film transistor9includes a gate electrode91, a source electrode92and a drain electrode93.

The sub-pixel further includes a pixel capacitor8including a first electrically conductive layer81and a second electrically conductive layer82. The first electrically conductive layer81and the second electrically conductive layer82may be arranged in various forms, for example, they may be arranged in the following manner: as shown inFIG. 2, the first electrically conductive layer81covers the base substrate1and is located in the buffer layer21, the first electrically conductive layer81is electrically connected to the drain electrode93through a first via hole83, and first electrically conductive layers81of two adjacent sub-pixels are insulated from each other; the second electrically conductive layer82and the drain electrode93cover the same insulating layer (for example, the interlayer dielectric layer22shown inFIG. 2), and the second electrically conductive layer82is electrically connected to the gate electrode91of the top gate thin film transistor9. Alternatively, they may be arranged in the following manner: an electrically conducted region of an active layer94is used as the first electrically conductive layer81, the second electrically conductive layer82and the drain electrode93covers the same insulating layer2, and the second electrically conductive layer82is electrically connected to the gate electrode91of the top gate thin film transistor9. Compared to the embodiment in which the electrically conducted region of the active layer94is used as the first electrically conductive layer81, the embodiment shown inFIG. 2has the following advantages: (1) It is not necessary to use the electrically conducted region of the active layer94as an electrode plate (Vs) of the pixel capacitor8and signal wires, thereby reducing the difficulty of electrically conducting the active layer94; (2) It prevents the problem that a parasitic resistance of the first electrically conductive layer81is large due to incomplete electrical conducting of the active layer94, thereby the performance of storing charges of the pixel capacitor8may be improved; (3) The area of the electrically conducted region of the active layer94is reduced, so that it is not necessary to make a large-area light shielding layer7on the base substrate1to shield the active layer94from light, the light shielding can be realized by using the light shielding layer7of a smaller area, so that the light shielding layer7of a smaller area can reduce the affection of the temperature rise of the light shielding layer7on the active layer94in subsequent high temperature processes (e.g., an annealing process of the active layer94), that is, avoiding the thin film transistor from being unable to be turned off due to over-annealing of the active layer94; at the same time, the light shielding layer7of a smaller area may also reduce the reflection of the light emitted from the organic light emitting layer53to the active layer94, thereby reducing any adverse affection on the characteristics of thin film transistors.

The positional relationship between the light shielding layer7and the first electrically conductive layer81may vary. For example, as shown inFIG. 2, the light shielding layer7may cover the first electrically conductive layer81from above and be electrically connected to the first electrically conductive layer81, and the light shielding layer7is electrically connected to the drain electrode93through the first via hole83. Alternatively, the first electrically conductive layer81may also cover the light shielding layer7from above and be electrically connected to the light shielding layer7, and the first electrically conductive layer81is directly electrically connected to the drain electrode93through the first via hole83. Compared with the embodiment in which the first electrically conductive layer81covers the light shielding layer7from above, the embodiment in which the light shielding layer7covers the first electrically conductive layer81from above can prevent the light shielding layer7from contacting the base substrate1, and solve the problem that the light shielding layer7and the base substrate1have poor adhesion and optional materials thereof are limited (this is because the light shielding layer7is generally made of metal, the base substrate1is generally made of glass, and the adhesion between the metal layer and the glass substrate is relatively poor), thereby the range of optional materials of the light shielding layer7can be greatly extended, and the tolerance of the process can be broadened.

In the pixel capacitor8, the first electrically conductive layer81may be an ITO layer. Thus, in the case where the transparent etching barrier layer6is an ITO layer, the first electrically conductive layer81and the transparent etch barrier layer6may be integrally formed by one process. This can simplify the production process and reduce the production cost.

As shown inFIG. 2, the top gate thin film transistor9includes an active layer94covering the buffer layer21, a gate insulating layer95covering the active layer94, a gate electrode91covering the gate insulating layer95, an interlayer dielectric layer22covering the surfaces of the active layer94, the gate insulating layer95and the gate electrode91, and a source electrode92and a drain electrode93both covering the interlayer dielectric layer22.

As shown inFIG. 2, the sub-pixel further includes a passivation layer23covering the surfaces of the source electrode92, the drain electrode93, and the second electrically conductive layer82. The insulating layer2includes the buffer layer21and the passivation layer23, and the planarization layer4covers the passivation layer23.

As shown inFIG. 2, the organic light emitting unit5includes a transparent electrode51, at least a portion of which covers the planarization layer4, and the transparent electrode51is electrically connected to the first electrically conductive layer81through a second via hole84. The transparent electrode51includes a first region511, and an orthographic projection of the first region511on the base substrate1and an orthographic projection of the second electrically conductive layer82on the base substrate1at least partially overlap with each other. Since the transparent electrode51is electrically connected to the first electrically conductive layer81through the second via hole84, an electrical signal outputted from the drain electrode93of the thin film transistor can be transmitted to the transparent electrode51through the first via hole83, the first electrically conductive layer81and the second via hole84, so as to drive the organic light emitting layer53to emit light. Since the orthographic projection of the first region511on the base substrate1and the orthographic projection of the second electrically conductive layer82on the base substrate1at least partially overlap with each other, a capacitor is formed between the first region511of the transparent electrode51and the second electrically conductive layer82, thereby increasing a charge storage capability of the pixel capacitor8, ensuring that the voltage on the transparent electrode51is more stable during the operation of the array substrate, and ensuring the display quality of the display device.

Of course, in addition to the transparent electrode51being electrically connected to the first electrically conductive layer81through the second via hole84to achieve the electrical connection of the transparent electrode51with the drain electrode93, the transparent electrode51may also be directly electrically connected to the drain electrode93through the second via hole84.

The arrangement mode of the first region511of the transparent electrode51may vary. For example, the following arrangement mode may be adopted: as shown inFIG. 2, the planarization layer4is provided with a second opening41extending through the planarization layer4, the first region511covers the passivation layer23and is located within the second opening41. Alternatively, the following arrangement mode may be adopted: there is no second opening41formed in the planarization layer4, and the first region511covers the planarization layer4from above. Compared with the embodiment in which the first region511covers the planarization layer4from above, the embodiment in which the first region511covers the passivation layer23from above and is located within the second opening41allows the distance between the first region511and the second electrically conductive layer82to be reduced, so that the capacitance between the first region511and the second electrically conductive layer82may be increased, to further increase the capacitance of the pixel capacitor8, thereby further increasing the charge storage capability of the pixel capacitor8, and ensuring that the voltage on the transparent electrode51is more stable during the operation of the array substrate.

For the array substrate provided by the embodiments of the present disclosure, the thin film transistor may be a bottom gate structure in addition to the top gate structure, which is not specifically limited herein. The thin film transistor may be an amorphous silicon thin film transistor, an oxide thin film transistor, a low temperature polysilicon thin film transistor or the like, which is not specifically limited herein. Herein, the thin film transistor of a bottom gate structure may be of a back channel type, an etching barrier type, a coplanar type or the like.

In the array substrate provided by the embodiments of the present disclosure, the material of the active layer94of the thin film transistor includes any one of a-IGZO, ZnON, IZTO, a-Si, p-Si, sexithiophene, or polythiophene; the materials of the electrodes and the lines may be commonly used metal materials, such as Ag, Cu, Al, Mo, etc., or multilayer of metals, such as MoNb/Cu/MoNb, etc., or alloy materials of the above metals, such as AlNd, MoNb, etc., a stacked structure of metal and transparent conductive oxide (such as ITO, AZO, etc.), for example, Mo/AlNd/ITO, ITO/Ag/ITO, etc.

In the array substrate provided by the embodiments of the present disclosure, the insulating layer, such as the gate insulating layer95, the interlayer dielectric layer22, the passivation layer23, the buffer layer21, and the planar layer4, may be made of the conventional dielectric material, such as SiOx, SiNx, SiON, etc., or various new organic insulating materials, or a high dielectric constant (High k) material, such as AlOx, HfOx, TaOx, etc. The organic insulating dielectric material of the planarization layer4may be polysiloxane, acrylic, polyimide or the like.

In a second aspect, an embodiment of the present disclosure provides a display panel including the array substrate described in the first aspect.

The display panel may be applied to a bottom-emitting OLED display panel manufactured based on an oxide technology, a silicon technology, or an organic technology.

The display panel provided by the embodiments of the present disclosure solves the same technical problem and achieves the same technical effect as the array substrate described in the first aspect, because the array substrate included in the display panel is the same as the array substrate described in the first aspect.

Other structures in the display panel are well known to those skilled in the art and will not be described herein.

In a third aspect, an embodiment of the present disclosure provides a display device including the display panel described in the second aspect.

The display device provided by the embodiments of the present disclosure solves the same technical problem and achieves the same technical effect as the array substrate described in the first aspect.

Other structures in the display device are well known to those skilled in the art and will not be described herein.

In a fourth aspect, an embodiment of the present disclosure provides a method for manufacturing an array substrate, including the following steps:

Step S1: providing a base substrate1, as shown inFIG. 4(a).

The base substrate1may be cleaned before the insulating layer2is formed on the base substrate1, to remove solid particles on the base substrate1, so as to avoid adverse effects on the subsequent processes; the base substrate1may be a glass substrate, a sapphire substrate, a silicon substrate, or the like.

Step S2: forming an insulating layer2on the base substrate1.

As shown inFIG. 2, the insulating layer2includes a buffer layer21, an interlayer dielectric layer22, and a passivation layer23. As shown inFIGS. 4(c) and 4(d), the formation process of the insulating layer2may refer to: forming the buffer layer21on the base substrate1; forming the interlayer dielectric layer22on the buffer layer21; forming the passivation layer23on the interlayer dielectric layer22.

The insulating layer2may be directly formed on the base substrate1, as shown inFIG. 4(d), or a transparent etching barrier layer6(for example, an ITO layer) may be first formed on the base substrate1, and then the insulating layer2is formed on the transparent etching barrier layer6, so that the base substrate1is avoided from being etched when the first opening20is formed.

Step S3: forming a first opening20in the insulating layer2.

When the insulating layer2includes a plurality of insulating sub-layers, for example, the insulating layer2includes a buffer layer21, an interlayer dielectric layer22and a passivation layer23, the first opening20may be formed by one-time etching after the plurality of insulating sub-layers are formed, or the first opening20may be formed by forming sub-openings in respective insulating sub-layers, i.e., a sub-opening is formed in each insulating sub-layer once this sub-insulating layer is formed, and then the sub-openings of the plurality of sub-insulating layers are combined to form the first opening20; for example, as shown inFIGS. 4(c) and 4(d), the first opening20may be formed by: forming a buffer layer21on the base substrate1and forming a first sub-opening201in the buffer layer21; forming an interlayer dielectric layer22on the buffer layer21and forming a second sub-opening202in the interlayer dielectric layer22; forming a passivation layer23on the interlayer dielectric layer22and forming a third sub-opening203in the passivation layer23; combining the sub-opening201, the second sub-opening202, and the third sub-opening203to form the first opening20.

Step S4: forming a color filter layer3such that at least a portion of the color filter layer3is filled in the first opening20.

The color filter layer3includes color filter sub-layers of different colors, including three colors of R, G and B, and at least a portion of the color filter sub-layer portion of each color is disposed in the first opening20of a corresponding one of the three sub-pixels.

Step S5: forming a planarization layer4on the insulating layer2to cover a surface of the color filter layer3.

Step S6: forming an organic light emitting unit5on the planarization layer4, as shown inFIG. 4(e).

As shown inFIG. 4(e), the organic light emitting unit5includes a transparent electrode51(anode), a cathode52, and an organic light emitting layer53located therebetween. In each of the sub-pixels, an orthographic projection of the organic light emitting layer53of the organic light emitting unit5on the base substrate1overlaps with an orthographic projection of the first opening20on the base substrate1.

The method for manufacturing the array substrate provided by the embodiments of the present disclosure can solve the same technical problem and achieve the same technical effect as the array substrate described in the first aspect, which will not be repeatedly described herein.

In the above method for manufacturing the array substrate, the manufacturing process of the thin film transistor is an important component of the method. Hereinafter, the oxide thin film transistor is taken as an example to illustrate the manufacturing process of the thin film transistor and the insulating layer2:

Step S21: applying a conductive film on the base substrate1and patterning the conductive film to form first electrically conductive layers81.

The first electrically conductive layers81located in two adjacent sub-pixel regions are spaced apart from each other, so that the first electrically conductive layer can transmit the electrical signal outputted by the drain electrode93of the thin film transistor in each sub-pixel to the transparent electrode51of the organic light emitting unit5.

The conductive film may be applied on the base substrate1by a sputtering process, and the material of the conductive film may be a transparent conductive oxide, such as an ITO film, an AZO film or the like.

The patterning of the conductive film is completed by a photolithography process;

Step S22: applying a light shielding film on the base substrate1and patterning the light shielding film to form a light shielding layer7, as shown inFIGS. 4(a) and 4(b).

The light shielding layer7is mainly used for shielding the active layer94to prevent the external light from being irradiated onto the active layer94, otherwise the irradiation of the external light to the active layer would cause the active layer94to generate photo-generated carriers, thereby affecting the performance of the thin film transistor. The light shielding layer7may be made of a light-transmissive metal or a metal alloy;

The first electrically conductive layer81may be first formed on the base substrate1, and then the light shielding layer7is formed, wherein the light shielding layer7covers the first electrically conductive layer81from above (as shown inFIG. 4(b)); or alternatively, the light shielding layer7may be first formed on the base substrate1, and then the first electrically conductive layer81is formed, wherein the first electrically conductive layer81covers the light shielding layer7from above.

Step S23: forming a buffer layer21on the base substrate1to cover surfaces of the first electrically conductive layer81and the light shielding layer7, as shown inFIG. 4(c).

The buffer layer21may be of a SiO2single layer structure or a SiNx/SiO2double-layer structure, which is not specifically limited herein.

The buffer layer21serves as blocking impurities in the base substrate1from diffusing into the active layer94to avoid affecting the electrical performance of the thin film transistor; the buffer layer21may be formed on the base substrate1by PECVD (Plasma Enhanced Chemical Vapor Deposition).

Step S24: forming a top gate thin film transistor9on the buffer layer21, as shown inFIGS. 4(c) and 4(d), wherein the top gate thin film transistor9includes a source electrode92and a drain electrode93, and the drain electrode93is electrically connected to the first electrically conductive layer81through the first via hole83.

In the step S24, the top gate thin film transistor9may be specifically formed by the following steps, as shown inFIG. 4(d):

Step S241: forming an active layer94on the buffer layer21;

Step S242: forming a gate insulating layer95on the active layer94, and forming a gate electrode91on the gate insulating layer95;

In an example, the gate insulating layer95and the gate electrode91may be formed by a self-aligned process;

Step S243: removing portions of the gate insulating layer95and the gate electrode91covering regions of the active layer94located at two sides of the channel region, wherein the gate insulating layer95may be removed by a dry etching process;

Step S244: processing the regions of the active layer94located at two sides of the channel region by an electrical conducting process to form a first electrically conducted region941and a second electrically conducted region942, wherein the electrical conducting process may be performed by dry-etching plasma to process the regions located at two sides of the channel region;

Step S245: forming an interlayer dielectric layer22to cover the active layer94, the gate insulating layer95and the gate electrode91;

Step S246: forming a first via hole83, a third via96and a fourth via97in the interlayer dielectric layer22; forming a source electrode92and a drain electrode93on the interlayer dielectric layer22, such that the source electrode92is electrically connected to the first electrically conducted region941through the third via hole96, the drain electrode93is electrically connected to the second electrically conducted region942through the fourth via hole97, and the drain electrode93is electrically connected to the first electrically conductive layer81through the first via hole83.

Step S25: forming a second electrically conductive layer82on the interlayer dielectric layer22covered by the source electrode92and the drain electrode93, so that the second electrically conductive layer82and the first electrically conductive layer81form a pixel capacitor8therebetween, as shown inFIG. 4(d).

The second electrically conductive layer82may be formed simultaneously with the source electrode92and the drain electrode93, that is, the interlayer dielectric layer22is covered by a source/drain metal layer, and then the source electrode92, the drain electrode93, and the second electrically conductive layer82are formed by a patterning process.

Step S26: forming a passivation layer23on the interlayer dielectric layer22to cover surfaces of the source electrode92, the drain electrode93and the second electrically conductive layer82, as shown inFIG. 4(d).

In the method for manufacturing the array substrate provided by the embodiments of the present disclosure, the forming the organic light emitting unit5on the planarization layer4specifically includes the following steps:

Step S61: forming a second via hole84which extends through the planarization layer4, the passivation layer23and the interlayer dielectric layer22, and is in communication with the first electrically conductive layer81, as shown inFIGS. 4(c) and 4(d).

The second via hole84may be formed by one-time etching after the buffer layer21, the planarization layer4, the passivation layer23, and the interlayer dielectric layer22are formed; as shown inFIGS. 4(c) and 4(d), it may also be formed by the following processes: forming the buffer layer21on the base substrate1and forming a first sub-via hole841in the buffer layer21, the first sub-via hole841being communicated with the first electrically conductive layer81; forming the interlayer dielectric layer22on the buffer layer21and forming a second sub-via hole842in the interlayer dielectric layer22; forming the passivation layer23on the interlayer dielectric layer22and forming a third sub-via hole843in the passivation layer23; forming a planarization layer4on the passivation layer23and forming a fourth sub-via hole844in the planarization layer4; combining the first sub-via hole841, the second sub-via hole842, the third sub-via hole843and the fourth sub-via hole844to form the second via hole84.

Step S62: forming a transparent electrode51, at least a portion of which is located on the planarization layer4, such that the transparent electrode51is electrically connected to the first electrically conductive layer81through the second via hole84, and an orthographic projection of the first region511of the transparent electrode51on the base substrate1at least partially overlaps with an orthographic projection of the second electrically conductive layer82on the base substrate1, as shown inFIG. 4(e).

The transparent electrode51may be made of a transparent conductive oxide such as ITO, AZO or the like.

The forming the transparent electrode51in the step S62specifically includes the following steps:

Step S621: forming a second opening41, which extends through the planarization layer4, in the planarization layer4, as shown inFIG. 4(d);

The second opening41may be spaced apart from the second via hole84; as shown inFIG. 4(e), it may partially overlap with the second via hole84.

Step S622: forming the transparent electrode51such that the first region511covers the passivation layer23and is located within the second opening41, as shown inFIG. 4(e).

The forming the organic light emitting unit5on the planarization layer4further includes the following steps, as shown inFIG. 4(e):

forming a pixel defining layer54on the transparent electrode51to form an opening defining a light emitting region; and

forming the organic light emitting layer53in the opening of the pixel defining layer54.

The organic light emitting layer53may be formed by an evaporation process or may be formed by an inkjet printing process, which is not specifically limited herein.

For the features in the embodiments of the method for manufacturing the array substrate, which are the same as or similar to those of the above-mentioned embodiments of the array substrate, references may be made to the description of the above-mentioned embodiments of the array substrate, and therefore they will not be described herein again.

In the array substrate, the method for manufacturing the same, the display panel and the display device provided by the embodiments of the present disclosure, since the insulating layer is provided with a first opening, and at least a portion of the color filter layer is filled in the first opening, a height difference between the color filter layer and the base substrate is reduced in case where the thickness of the color filter layer is constant, and at least a portion of the color filter layer is overlapped with the insulating layer, thereby greatly reducing the height the portion of the color filter layer protruding from the insulating layer. In this case, it is unnecessary to make the planarization layer too thick, to cover the surface of the color filter layer protruding from the surface of the insulating layer, thus the thickness of the planarization layer can be greatly reduced. The reduction of the thickness of the planarization layer can effectively shorten the light exit path of the light emitted by the organic light emitting unit, and reduce the absorption of the light emitted from the organic light emitting unit by respective film layers, thereby facilitating the improvement of the highest brightness of the light emitted by the organic light emitting unit, and further facilitating the improvement of the contrast ratio of the display device and allowing the user to obtain a better visual experience.

The above description only refers to the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto. Any changes or substitutions that are easily obtained by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the scope of the present disclosure should be defined by the appending claims.