Trench interconnect structure and formation method

Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in reduced interconnect resistance, I2R losses, and defects or variations due to cusping. Embodiments of the methods involve forming an opening in an insulating layer, where the opening forms a trench that exposes an underlying portion of a metal layer. Additional embodiments involve depositing multiple layers of conductive material within the opening and above the insulating layer, where one of the conductive layers includes aluminum and is deposited using a “cold aluminum” process, and a second one of the conductive layers also includes aluminum, but is deposited using a “hot aluminum” process. The interconnect structures are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

TECHNICAL FIELD

The present invention relates generally to formation of conductive interconnects on an integrated circuit, and more specifically to forming submicron VLSI trench vias that electrically interconnect metal layers of an integrated circuit.

BACKGROUND

The integrated circuit industry continues to progress in electronic circuit densification and miniaturization. This progress has resulted in increasingly compact and efficient semiconductor devices, which in turn enable the systems into which these devices are incorporated to be made smaller and less power consumptive.

Among the semiconductor device features that are being reduced in size are the vias, which electrically connect a device's various metal layers. A device's metal layers often include conductive planes that conduct power or provide grounding, and also include patterned conductive layers that serve as input/output and control lines for components on the device (e.g., transistors, resistors, capacitors, etc.). Conductive vias with a circular cross-sectional area are most often used to electrically connect these metal layers. These vias are typically drawn square on the design database.

Two important characteristics of a via are its resistance and the I2R losses associated with the structure. Ideally, the via's resistance should be as close to zero as possible, so that the via has high conductivity. In addition, the I2R loss should be as low as possible, which lowers the device temperature and, in turn, lowers resistance even further. A via's resistance and I2R losses depend on the via's physical attributes (e.g., shape, height, width), the materials used to form the via, and the methods used to deposit the conductive materials into the via openings. Basically, vias are formed by etching openings in dielectric layers of a device, and filling those openings with conductive material.

Via openings are currently designed with diameters within the half micron range, and the aspect ratio of the via openings (i.e., the ratio of the opening's height to its diameter) is becoming very high. For example, aspect ratios for via openings currently can be greater than 3. Because of this, it is difficult to deposit, with good coverage, the necessary conducting material in these tiny, narrow, high-sided via openings. As will be described in more detail below, this makes it difficult to form increasingly miniaturized vias that retain a high conductivity.

With regard to the materials used for the vias, aluminum is commonly used because of its good conductivity and ease of deposition. However, pure aluminum is subject to electromigration failures, which occur when the flow of electrons through the material dislodges aluminum atoms and causes an open circuit condition. This results in poor electrical conduction or total failure.

Another problem that occurs during via formation is that, as a result of exposure to the ambient, a native oxide layer can grow in the bottom of a via opening. These layers are highly insulative and can cause a high resistance, which at times can result in via failure. Typically, a diffusion barrier and/or electrical shunt of a material such as titanium nitride, also referred to as Ti N, is used to remove the native oxide layer. Therefore, methods used for filling via openings should be compatible with the currently known methods for depositing diffusion barriers.

With regard to the processes used to fill via openings with conductive material, one of two processes are commonly used: chemical vapor deposition (CVD); and physical vapor deposition (PVD), also known as sputtering. Limitations of the materials that can be deposited with CVD make it impractical for many applications, so PVD is more commonly used.

One problem associated with PVD is that “cusping” may occur during sputtering or reflowing aluminum into high aspect ratio via openings. Cusping occurs as aluminum aggregates at the top of the via opening and overhangs into the center of the via opening. Cusping can block the via opening before a proper thickness of aluminum can be,formed at the bottom of the via opening. This results in a partially filled via opening with poor electrical connection characteristics, and can cause total via failure.

One method for forming a via, which addresses some of the problems described above, is described by Honeycutt et al. in U.S. Pat. No. 6,331,482 B1, issued on Dec. 18, 2001. Using the Honeycutt et al. method, a via is formed by first depositing a standard diffusion barrier in a via opening. A layer of germanium is then formed over the diffusion barrier, and aluminum or aluminum alloy is reflow sputtered into the via opening. Although the technique addresses some of the process and material concerns with vias described above, it does not fully address the inherent resistance and I2R loss issues relating to the via's physical configuration (e.g., the via's shape, aspect ratio, and size).

Accordingly, what is needed is a submicron VLSI via with very low resistance and I2R loss. Particularly needed is a via which has higher reliability than prior art vias. Also needed is a method of forming these vias, which reduces the occurrence of cusping, and improves the electrical characteristics and reliability of the vias.

SUMMARY

Embodiments of the present invention provide a trench via structure, which can be reliably formed in submicron dimensions with very low resistance and I2R loss. The trench vias electrically interconnect metal layers of a semiconductor device. Embodiments of the invention form the trench vias simultaneously with forming one of the metal layers, by sequentially depositing layers of conductive material in the via openings and on the top surface of the dielectric layer in which the vias are formed. The particular materials used in the sequentially-deposited layers, and the thicknesses of these layers, enable trench and other vias to be formed with a lower incidence of cusping and electromigration failures.

For one embodiment, the invention provides a method of forming a vertical interconnect structure. The method includes forming an opening extending vertically downward through an insulating layer to an underlying portion of a first metal layer, where a length of the opening in a horizontal plane is sufficiently greater than a width of the opening in the horizontal plane so that the opening has a trench shape. The method further includes filling the opening with conductive material to form a conductive trench via, while simultaneously forming a second metal layer above the insulating layer.

For another embodiment, the method includes forming an opening extending vertically downward through an insulating layer to an underlying portion of a first metal layer, and depositing at least three layers within the opening. A coating layer of a conductive material is deposited in contact with a bottom and sidewalls of the opening. A first conductive layer containing aluminum is deposited into the opening and in contact with the coating layer at a first temperature. A second conductive layer containing aluminum is deposited into the opening and in contact with the first conductive layer at a second temperature that is higher than the first temperature. The coating layer, the first conductive layer, and the second conductive layer substantially fill the opening while simultaneously forming a second metal layer above the insulating layer.

For yet another embodiment, the method includes forming an opening extending vertically downward through an insulating layer to an underlying portion of a first metal layer, and depositing at least three layers within the opening. A coating layer of a conductive material is deposited in contact with a bottom and sidewalls of the opening. A first conductive layer containing aluminum is deposited into the opening and in contact with the coating layer, wherein the first conductive layer partially fills the opening. A second conductive layer containing aluminum is deposited into the opening and in contact with the first conductive layer, where the second conductive layer substantially fills a remainder of the opening.

For a further embodiment, a portion of a semiconductor device is formed, which includes a conductive contact to an active region. A first metal layer is formed directly above and in contact with the portion of the semiconductor device, so that the first metal layer physically and electrically connects with the contact. An insulating layer is formed above the first metal layer. An opening is formed extending vertically downward through the insulating layer to an underlying portion of the first metal layer. A length of the opening in a horizontal plane is sufficiently greater than a width of the opening in the horizontal plane so that the opening has a trench shape. The opening is filled with conductive material to form a conductive trench via, while simultaneously forming a second metal layer above the insulating layer.

Further embodiments of the invention include semiconductor structures produced using one or more methods of the invention, as well as apparatus, devices, modules and systems making use of such semiconductor structures.

It will be recognized that the methods of the various embodiments can be combined in practice, either concurrently or in succession. Various permutations and combinations will be readily apparent to those skilled in the art.

DESCRIPTION OF THE EMBODIMENTS

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that process or mechanical changes may be made without departing from the scope of the present invention.

Terminology

The terms “wafer” and “substrate” used in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor, as well as other semiconductor support structures that are new or are well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.

The terms “horizontal” and “vertical” are used to explain the relative orientations of particular views. For the purposes of this description, assuming a semiconductor wafer or device is laid flat along a horizontal plane, a “top-down” or “horizontal” view of the device indicates a view of the device from above. Conversely, a “side” or “vertical” view of the device indicates a view of the device from the side. In the figures, any cut-away view is referred to as a “cross-sectional” view. An “elevational” view is a view of an exterior surface, and a “perspective” view is a three-dimensional view.

To distinguish conductive structures (e.g., vias) that connect distinct layers of a semiconductor device from conductive structures within a single layer, the terms “interconnect structure” and “inter-layer interconnect structure” are used and defined herein as a conductive structure that electrically connects portions of at least two distinct metal layers of a semiconductor device. An interconnect structure can include a circular via or a “trench via,” described below.

A “trench via” or “trench interconnect structure” is defined herein as an interlayer interconnect structure having a cross-sectional area, along a horizontal plane, that is roughly rectangular, as illustrated inFIG. 2, which will be referred to more extensively later. The “length” of a trench via, is defined as the dimension from one end210of the via to the other end212of the via. The length of a trench via is limited or bounded by the areas of the metal portions that the trench via is designed to interconnect.

In one embodiment of the present invention, trench vias are used as inter-layer interconnect structures between metal layers of a semiconductor device. The trench vias can exist within a dielectric layer in conjunction with conventional circular vias, which provide other interconnections between metal layers.

Using trench via formation methods described later, the trench vias of the various embodiments can be formed in submicron dimensions, while still having very low resistance and I2R losses. In addition, the trench vias of the various embodiments have higher reliability than vias formed using prior art methods, because the methods of forming the trench vias, in accordance with the various embodiments, reduce the occurrence of cusping and increase the electrical characteristics and reliability of the trench vias, even at high aspect ratios.

Although structures also referred to as “trenches” are sometimes used for other purposes within semiconductor devices, trenches have not been reliably used to interconnect distinct metal layers within a semiconductor device. For example, trenches are sometimes formed as a part of a particular metal layer, where these trenches act as “wires” that enable power, ground, input/output paths or control signals to be provided to components on a semiconductor device (e.g., transistors, resistors, capacitors, etc.). These prior art trenches represent the wiring itself, while the trenches referred to in the context of the present invention refer to the inter-layer connections. For metals, the inter-layer connections are referred to as vias. Here, trench lengths are limited by the overlapping areas of the portions of the metal layers that the trench vias are used to interconnect. The trench lengths can range from short to very long.

According to the prior art, the metal layers that include trenches are sometimes formed using a damascene process, where openings for conductive trenches and other layer features are formed in a dielectric layer, and then conductive material is deposited within the openings to form the layer's trenches and other features. For example, a metal layer having conductive trenches, formed using a damascene process, is described by Chan et al. in U.S. Pat. No. 6,156,643, issued on Dec. 5, 2000. Similar structures are also described by Okada in U.S. Pat. No. 6,268,279 B1, issued on Jul. 31, 2001. Rather than interconnecting two or more metal layers, which is the function provided by the trench vias of the various embodiments of the invention, the prior art trenches represent the metal layer itself. The trenches within such a layer are interconnected to devices or other layers using conventional circular vias.

In one embodiment, trench vias are used to interconnect metal layers within a memory device, such as a DRAM (Dynamic Random Access Memory).FIG. 1illustrates a side, cross-sectional view of a portion of a semiconductor device, which includes a DRAM memory cell and two or more metal layers102,104, in accordance with an embodiment of the invention. The metal layers102,104are interconnected, at least in part, using one or more trench vias106, in accordance with one embodiment of the present invention.

A typical DRAM includes an array of memory cells. A DRAM cell generally consists of a capacitor coupled through a transistor to a digit line, also commonly referred to as a bitline. The wafer fragment illustrated inFIG. 1includes a semiconductive material112, field oxide region114, and wordlines116,118. Nitride spacers120are adjacent wordlines116,118. Node locations122,124are adjacent to wordlines116,118, and are diffusion regions within semiconductive material112. Conductive structures126,128extend upward from node locations122,124into or through an insulative layer130. The upper surface of conductive structure126contacts a capacitor construction132, which serves to store a bit of information. Conductive structure128serves as a contact to metal layer102, which includes the digit line to the memory cell. During operation, the capacitor construction132is electrically connectable to contact128through a transistor gate comprised by wordline118.

Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines, and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected or addressed. The address for the selected cell is represented by input signals to a word line decoder and to a digit line decoder. The word line decoder activates a word line in response to the word line address. The selected word line activates the access gates for each of the memory cells in communication with the selected word line. The digit line decoder selects a digit line pair in response to the digit line address. For a read operation, the selected word line activates the access gates for a given word line address, and data is latched to the digit line pairs.

In one embodiment, some or all digit lines are provided within first metal layer102. The first metal layer102, in turn, is electrically connected to second metal layer104through trench vias106, which function as vertical interconnect structures through a dielectric layer108. The second metal layer104serves to carry voltage signals that are transmitted to and received from the first metal layer102through trench vias106.

In one embodiment, at least one and potentially all of the vertical interconnect structures through dielectric layer108are trench vias106. Other vias having conventional circular cross-sectional areas also can exist in conjunction with the trench vias106, either within the same dielectric layers or within other layers of the device.

FIG. 2illustrates a perspective, cross-sectional view of the portion of the semiconductor device illustrated inFIG. 1with the second metal layer104removed to show both top and side cross-sectional views of trench vias106. In one embodiment, the length of a trench via (i.e., the dimension from one end210of the via to the other end212of the via) is at least twice as long as the width214of the via. Depending on the device design, the length of any particular trench via could be more than two, five, ten, twenty, fifty, one hundred or more times the width214of the via. This distinguishes the trench vias of the various embodiments from conventional circular vias. The term “length” is not applicable to a circular via, as such a via has a uniform, cross-sectional diameter. Circular vias216can be formed through the same layers as trench vias106.

AlthoughFIG. 2illustrates straight trench vias106, trench vias could be bent or have other shapes, in other embodiments. For example,FIG. 3illustrates a top-down, cross-sectional view of a trench via302that is bent, andFIG. 4illustrates a top-down, cross-sectional view of a trench via402having an irregular shape, in accordance with other embodiments of the invention. Virtually any length or shape of via could be formed using the methods of the embodiments of the present invention.

It will be understood that the above description of a DRAM cell is intended to provide a general understanding of the memory and is not a complete description of all the elements and features of a DRAM. Although the description shows how embodiments of the present invention are implemented in a DRAM, trench vias (e.g., vias106) could be used to interconnect metal layers within other types of devices, as well. For example, the embodiments of the present invention could be implemented in other types of memory devices, microprocessors, Application Specific Integrated Circuits (ASICs) or virtually any other semiconductor device having two or more metal layers. In particular, the invention is equally applicable to any size and type of memory circuit and is not intended to be limited to the DRAM described above. Other alternative types of devices include SRAM (Static Random Access Memory) or Flash memories. Additionally, the DRAM could be a synchronous DRAM commonly referred to as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well as Synchlink or Rambus DRAMs.

Method of Forming Trench Vias

FIGS. 5–9are side, cross-sectional views of a portion of a semiconductor device during various processing stages in accordance with an embodiment of the invention. For illustration purposes, these figures depict the formation of a portion of a DRAM memory device, and a single memory cell is illustrated.

To begin the process, a portion of a semiconductor device is formed, as illustrated inFIG. 5. In the example embodiment, the portion of the semiconductor device is a DRAM memory cell, which includes a transistor502and a capacitive structure508formed on a substrate504. Transistor502is activated through a conductive contact512. When activated, transistor502allows data to be stored into or retrieved from capacitive structure508.

A top surface of conductive contact512is exposed so that the contact512can be electrically connected to one or more conductive layers above the memory cell. Accordingly, contact512either extends to the top of or above dielectric510, or an opening is formed in dielectric510, thus exposing a portion of contact512. Methods used for forming the portion of the semiconductor device are well understood in the art, and are outside the scope of the present invention. Accordingly, for purposes of brevity, those methods are not described herein.

After the portion of the semiconductor device is formed, a patterned conductive layer602is formed on the top surface of the dielectric layer510, as illustrated inFIG. 6. This conductive layer is referred to herein as the first metal layer, or the “M1” layer. The patterned conductive layer602comes into electrical contact with conductive contact512.

In one embodiment, the M1layer602includes three layers of conductive material, which are sequentially deposited using standard deposition techniques (e.g., CVD and/or PVD). The lowest layer604includes titanium, and has a thickness in a range of about 80–120 angstroms, with a thickness of about 100 angstroms being present in one embodiment. The middle layer606includes an aluminum/copper alloy, and has a thickness in a range of about 2500–3500 angstroms, with a thickness of about 3000 angstroms being present in one embodiment. The top layer608includes TiN, and has a thickness in a range of about 200–300 angstroms, with a thickness of about 250 angstroms being present in one embodiment.

In other embodiments, layers604,606, and608could be thicker or thinner than the ranges specified above. In still other embodiments, the M1layer602could include more or fewer conductive layers (e.g., from 1 to 10), or those layers could be formed from different materials (e.g., copper), or those layers could be arranged in a different configuration (e.g., a TiN layer could exist as the bottom layer).

After forming the M1layer602, an antireflection coating702is formed on the top surface of the M1layer602, in one embodiment, as illustrated inFIG. 7. The M1layer602is then patterned using a standard, subtractive process.

Antireflection coating702is a DARC (Dielectric Anti-Reflective Coating) layer, in one embodiment, which helps in the imaging and patterning of M1layer602. This coating also can slow later etching processes down, in some cases, and thus act as a hard mask. In one embodiment, antireflection coating702is formed from siliconoxynitride. Coating702has a thickness in a range of about 300–400 angstroms, with a thickness of about 360 angstroms being present in one embodiment. In other embodiments, antireflection coating702is non-existent, is thicker or thinner than the range specified above, or is formed from other suitable materials.

Next, an interlayer dielectric material802(“ILD”) is deposited on the top surface of the antireflection coating702, as illustrated inFIG. 8. In one embodiment, ILD802is formed from tetraethyloxysilicate (TEOS). ILD802has a thickness in a range of about 4500–5500 angstroms, with a thickness of about 5000 angstroms being present in one embodiment. In other embodiments, ILD802could be formed from other suitable dielectric materials, and could be thicker or thinner than the range specified above. For example, ILD802could include other insulative materials, such as oxides or nitrides.

In one embodiment, ILD802is planarized using a chemical-mechanical polishing (CMP) process to smooth the top surface. Smoothing the top surface of ILD802has been shown to improve the overall performance of the device. Other mechanical or non-mechanical smoothing techniques may also be used, such as alternative etch processes (e.g., reactive ion etching) or chemical dissolution. In another embodiment, the top surface is not planarized.

Next, as illustrated inFIG. 9, trench via openings902are formed through ILD802using a photoresist process. The trench via openings902extend vertically downward through ILD802to an underlying portion of M1layer602. In one embodiment, a length of each opening in a horizontal plane is sufficiently greater than a width of the opening in the horizontal plane, so that the opening has a trench shape (SeeFIG. 2, illustrating the width214and length, from210to212, of a trench via).

The process of forming the openings902involves first forming a photoresist layer904over ILD802. The resist layer904contains a resist material that is light or energy sensitive, such that resist material receiving exposure will have physical characteristics different from resist material not receiving exposure.

Such resist materials are typically reactive to a specific set or range of energy types (e.g., a specific set or range of wavelengths of light). The resist layer is preferably OIR-897-10I photoresist produced by Olin Corporation or PFI 66A7 photoresist produced Sumitomo Chemical Co. LTD as used herein, although numerous other photoresist compositions and technologies could be used.

A reticle or mask is placed over the resist layer904in order to selectively block waves directed toward the surface of the resist layer. The resist layer904is then exposed to electromagnetic radiation or light waves, typically UV light, of a type capable of exposing the resist material in the resist layer. In one embodiment, the resist layer contains photoresist material of a positive type (i.e., that which is more easily removed, or more vulnerable to solvents, when exposed to light or energy). Exposed resist portions are then removed using conventional washing techniques (e.g., washing with a solution of aqueous TMAH), leaving portions of the ILD layer802uncovered. In an alternate embodiment, a negative type photoresist could be used (i.e., that which is more resistant to removal, when exposed to light or energy, than unexposed areas of the resist). In the latter embodiment, the mask or reticle would be appropriately and obviously modified.

After the photoresist is selectively removed, a patterned layer of resist904remains on the top surface of ILD802. Uncovered portions of ILD802are then modified and removed, resulting in the formation of trench via openings902. To complete the opening formation process, underexposed resist portions are then removed. Removal of underexposed resist portions can include traditional methods such as using a hydrogen peroxide and sulfuric acid solution (“piranha etch” or “Carro's acid”).

In one embodiment, conventional circular via openings (not illustrated) also can be formed simultaneously with the trench via openings, where desired. Forming the trench and conventional via openings simultaneously is advantageous because both can be formed using only one mask and photoresist process.

In one embodiment, the width906of the trench via openings902is in a range of about 0.2–0.35 microns, although the width906could be larger or smaller in other embodiments. Also, the length (not illustrated) of the trench via openings902are greater than twice the width906, in one embodiment. In some cases, the lengths of the trench via openings902can be five or more times the width906of the openings.

After forming the trench via openings902, these openings are filled with conductive material, while simultaneously forming the next metal layer, referred to herein as the “M2” layer. In one embodiment, the openings are filled using a four-step process, which is illustrated inFIGS. 10–13. Specifically,FIGS. 10–13are side, cross-sectional views of an enlarged, single via910(FIG. 9) of the semiconductor device illustrated inFIG. 9(with photoresist904removed), after various subsequent processes in accordance with an embodiment of the invention.

First, as illustrated inFIG. 10, a conductive coating layer1002is deposited in contact with the bottom and sidewalls1006of the via opening902, and also above the top surface1004of ILD802. In one embodiment, coating layer1002includes titanium or a titanium alloy, which is deposited using a PVD process. This layer has a thickness in a range of about 100–200 angstroms, with the thickness being about 150 angstroms in one embodiment. In other embodiments, coating layer1002could be thicker or thinner than the range specified above, and could be formed from different suitable materials. Titanium is a particularly well suited to the embodiment described, because it has been shown to cause subsequent aluminum layers to adhere well, and also enables via widths of 0.3 microns or less to be reliably achieved.

Next, as illustrated inFIG. 11, a first layer1102of aluminum or aluminum alloy (e.g., an aluminum/copper alloy) is deposited in contact with the coating layer1002using a “cold aluminum” process. This process involves depositing the material using a PVD process. In one embodiment, the deposition temperature is between about 0–250 degrees Celsius (C.) and at a pressure between about 1×10−7to 1×10−2torr, although temperatures and pressures higher or lower than these ranges could be used in other embodiments. After initially depositing the material, the material is then reflowed, in one embodiment, at a temperature between about 300–400 degrees C. and at a pressure between about 1×10−7to 1×10−2torr. In an alternate embodiment, the material is not reflowed. In another alternate embodiment, the material is initially deposited at a temperature in a range of about 250–350 degrees C., and is not reflowed. Either way, the first layer1102is deposited at a temperature below about 400 degrees C.

The first layer1102has a thickness in a range of about 2500–3500 angstroms, with the thickness being about 3000 angstroms in one embodiment. In other embodiments, the first layer1102could be thicker or thinner than the range specified above, and could be formed from a different suitable material. The first layer1102serves to further coat the interior of the via opening902and the top surface of the device.

A “hot aluminum” process is then used to deposit a second layer1202of aluminum or aluminum alloy (e.g., an aluminum/copper alloy) in contact with the first layer1102, as illustrated inFIG. 12. This process involves depositing the material using a PVD process at a temperature of about 465 degrees C. or higher, with the deposition temperature being in a range of about 450–480 degrees C., in one embodiment. The deposition pressure is in a range of about 1×10−7to 1×10−2torr, in one embodiment. Temperatures and pressures higher or lower than these ranges could be used in other embodiments. One advantage to using a hot aluminum process is that the aluminum flows into and fills the trench and other vias much more completely than it does using prior art methods.

The second layer1202has a thickness in a range of about 2500–3500 angstroms, with the thickness being about 3000 angstroms in one embodiment. In other embodiments, the second aluminum layer1202could be thicker or thinner than the range specified above, and could be formed from a different suitable material. In one embodiment, the second layer1202fills the remainder of the via openings, and increases the thickness of the conductive material on the top surface of the device.

Next, a top conductive layer1302is deposited over the second layer1202, as illustrated inFIG. 13. In one embodiment, top conductive layer1302includes TiN, which is deposited using a PVD process. This layer has a thickness in a range of about 200–300 angstroms, with the thickness being about 250 angstroms in one embodiment. In other embodiments, top layer1302could be thicker or thinner than the range specified above, and could be formed from different suitable materials.

The result of the four-step, conductive material deposition process is an M2layer1304and one or more filled trench vias1306. Although the embodiments described above for forming the M2layer1304use a four-step process, more or fewer layers could be deposited in order to form the M2layer1304. In addition, in various embodiments, some or all of layers1002,1102,1202, and1302(FIGS. 10–13) could be deposited using a CVD or other process, rather than a PVD process. Also, conductive materials other than those described could be used to form the M2layer1304. Suitable, alternative, conductive materials for forming metal layers are well known in the art, such as tungsten, copper, aluminum, or other materials or alloys.

The M2layer1304is then patterned, in one embodiment, by selectively removing portions of the conductive material from the top surface of ILD802using subtractive technologies that are new or are well understood in the art. After patterning the M2layer1304, one or more additional layers of dielectric and conductive material (e.g., layers M3, M4, etc.) can be built on top of the M2layer1304using the techniques and materials described above and/or other device build-up techniques that are new or are well understood in the art. In addition, interconnects between the M1, M2, and/or the new conductive layers can be formed. These additional interconnects between the conductive layers can include trench vias, as described in conjunction with the embodiments above. Alternatively, a passivation layer can be formed on top of the M2layer1304, after which the device build-up process can be considered to be essentially complete. Trench vias can interconnect adjacent layers (i.e., layers separated by a single dielectric layer) and/or layers that are non-adjacent (i.e., layers that are separated by one or more intervening conductive layers, as well as dielectric layers).

The memory cells described above can form a portion of a memory device, in accordance with various embodiments. This memory device can be, for example, a DRAM, SRAM, Flash memory or other type of memory device. Alternatively, the trench vias and their formation methods, described in conjunction with the various embodiments above, can be integrated into another type of device (e.g., a microprocessor or ASIC).

Memory Devices

FIG. 14is a simplified block diagram of an integrated circuit memory device according to one embodiment of the invention. In one embodiment, memory cells, such as those described in conjunction withFIG. 1, are suitable for use in memory devices. Other types of memory cells having structures well understood in the art are also suitable for use in memory devices.

The memory device1400includes an array of memory cells1402, address decoder1404, row access circuitry1406, column access circuitry1408, control circuitry1410, and Input/Output circuit1412. The memory can be coupled to an external microprocessor1414, or memory controller for memory accessing. The memory receives control signals from the processor1414, such as WE*, RAS* and CAS* signals. The memory is used to store data which is accessed via I/O lines. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device ofFIG. 14has been simplified to help focus on the invention. The memory device includes at least one trench via, in accordance with the various embodiments of the invention.

As recognized by those skilled in the art, memory devices of the type described herein are generally fabricated as an integrated circuit containing a variety of semiconductor devices. The integrated circuit is supported by a substrate. Integrated circuits are typically repeated multiple times on each substrate. The substrate is further processed to separate the integrated circuits into dies as is well known in the art.

Semiconductor Dies

FIG. 15is a top-down, elevational view of a wafer1500containing semiconductor dies1510in accordance with an embodiment of the invention. A die is an individual pattern, typically rectangular, on a substrate that contains circuitry, or integrated circuit devices, to perform a specific function. At least one of the integrated circuit devices includes a trench via, embodiments of which are disclosed herein. A semiconductor wafer will typically contain a repeated pattern of such dies containing the same functionality. Die1510may contain circuitry for the inventive memory device, as discussed above. Die1510may further contain additional circuitry to extend to such complex devices as a monolithic processor with multiple functionality. Die1510is typically packaged in a protective casing (not shown) with leads extending therefrom (not shown) providing access to the circuitry of the die for unilateral or bilateral communication and control.

Circuit Modules

FIG. 16is a simplified block diagram of an exemplary circuit module1600in accordance with an embodiment of the invention. As shown inFIG. 16, two or more dies1510may be combined, with or without protective casing, into circuit module1600to enhance or extend the functionality of an individual die1510. Circuit module1600may be a combination of dies1510representing a variety of functions, or a combination of dies1510containing the same functionality. Some examples of a circuit module include memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules and may include multilayer, multichip modules. Circuit module1600may be a subcomponent of a variety of electronic systems, such as a clock, a television, a cellular or radio communication device (e.g., cell phone, pager, etc.), a desktop, handheld or portable computer, an automobile, an industrial control system, an aircraft, an automated teller machine, and others. Circuit module1600will have a variety of leads1610extending therefrom and coupled to the dies1510providing unilateral or bilateral communication and control.

FIG. 17is a simplified block diagram of an exemplary memory module1700, which is one embodiment of a circuit module. Memory module1700generally depicts a Single Inline Memory Module (SIMM) or Dual Inline Memory Module (DIMM). A SIMM or DIMM is generally a printed circuit board (PCB) or other support containing a series of memory devices. While a SIMM will have a single in-line set of contacts or leads, a DIMM will have a set of leads on each side of the support with each set representing separate I/O signals. Memory module1700contains multiple memory devices1710contained on support1715, the number depending upon the desired bus width and the desire for parity. Memory module1700may contain memory devices1710on both sides of support1715. Memory module1700accepts a command signal from an external controller (not shown) on a command link1720and provides for data input and data output on data links1730. The command link1720and data links1730are connected to leads1740extending from the support1715. Leads1740are shown for conceptual purposes and are not limited to the positions shown inFIG. 17.

Electronic Systems

FIG. 18is a simplified block diagram of an exemplary electronic system1800containing one or more circuit modules1600in accordance with an embodiment of the invention. Electronic system1800generally contains a user interface1810. User interface1810provides a user of the electronic system1800with some form of control or observation of the results of the electronic system1800. Some examples of user interface1810include a keyboard, pointing device, monitor, and printer of a computer; a keypad, speaker, microphone, and display of a communication device; a tuning dial, display, and speakers of a radio; an ignition switch and gas pedal of an automobile; and a card reader, keypad, display, and currency dispenser of an automated teller machine. User interface1810may further describe access ports provided to electronic system1800. Access ports are used to connect an electronic system to the more tangible user interface components previously exemplified.

One or more of the circuit modules1600may be a processor providing some form of manipulation, control or direction of inputs from or outputs to user interface1810, or of other information either preprogrammed into, or otherwise provided to, electronic system1800. As will be apparent from the lists of examples previously given, electronic system1800will often contain certain mechanical components (not shown) in addition to circuit modules1600and user interface1810. It will be appreciated that the one or more circuit modules1600in electronic system1800can be replaced by a single integrated circuit. Furthermore, electronic system1800may be a subcomponent of a larger electronic system.

FIG. 19is a simplified block diagram of an exemplary memory system1900, which is one embodiment of an electronic system. Memory system1900contains one or more memory modules1700and a memory controller1910. Memory controller1910provides and controls a bidirectional interface between memory system1900and an external system bus1920. Memory system1900accepts a command signal from the external bus1920and relays it to the one or more memory modules1700on a command link1930. Memory system1900provides for data input and data output between the one or more memory modules1700and external system bus1920on data links1940.

FIG. 20is a simplified block diagram of an exemplary computer system2000, which is a further embodiment of an electronic system. Computer system2000contains a processor2010and a memory system1900housed in a computer unit2005. Computer system2000is but one example of an electronic system containing another electronic system (e.g., memory system1900) as a subcomponent. Computer system2000optionally contains user interface components. Depicted inFIG. 20are a keyboard2020, a pointing device2030, a monitor2040, a printer2050, and a bulk storage device2060. It will be appreciated that other components are often associated with computer system2000such as modems, device driver cards, additional storage devices, etc. It will further be appreciated that the processor2010and memory system1900of computer system2000can be incorporated on a single integrated circuit. Such single package processing units reduce the communication time between the processor and the memory circuit.

CONCLUSION

Prior art vias, which are used to interconnect metal layers of a semiconductor device, suffer performance and reliability degradations when implemented in submicron dimensions. This is primarily due to the vias' physical configurations, and due to the materials and methods currently used for forming the vias. These methods often produce vias with unacceptably high resistance and I2R losses, and result in significant cusping, electromigration, and other via failures.

Embodiments of the present invention provide a trench via structure, which can be reliably formed in submicron dimensions with very low resistance and I2R losses. The trench vias are formed simultaneously with forming a metal layer, by sequentially depositing layers of conductive material in the via openings and on the top surface of the dielectric layer in which the via openings exist. The particular materials used in these sequentially-deposited layers, and the thicknesses of these layers, enable trench and other vias to be formed with a lower incidence of cusping and electromigration failures.

While the invention has been described and illustrated with respect to forming trench vias between metal layers above a memory cell, it should be apparent that the same processing techniques can be used to form trench vias for other applications, and also to form conventional circular vias or plugs. In addition, the interconnect structures formed using the methods of the various embodiments could electrically connect a metal layer and a plug, rather than two metal layers. Furthermore, the methods described herein may be used in the development of contacts. The process used for forming a contact is very similar. The difference is well known in the art and consists of the fact that the contact, rather than interconnecting two metal layers, typically contacts an underlying portion of a semiconductor device.