Memory controller and non-volatile storage device

A non-volatile storage device comprises non-volatile memories for storing data; and a memory controller for carrying out control of the non-volatile memory. The memory controller stores second error correcting code as well as first error correcting code stored in the same page of the data. The memory controller, when writing data smaller than a predefined size, does not add the second error correcting code, and stores duplexed data of the data and the first correcting code in a different page. The memory controller, when reading, corrects data using the first and/or second correcting code. The valid data management table manages which logical block stores valid data with respect to an identical logical address.

BACKGROUND

1. Technical Field

The present invention relates to a memory controller for controlling a non-volatile memory, and a non-volatile storage device such as a semiconductor memory card including the non-volatile memory and the memory controller.

2. Related Art

In recent years, a demand for a non-volatile storage device including a rewritable non-volatile memory is increasing, centering on a semiconductor memory card.

The semiconductor memory card has various features such as being small and light weight, having large capacity and resistance to quake, and being easy and convenient to handle, and hence the demand for such a semiconductor memory card is increasing as a recording medium of a portable device such as a digital still camera or a portable telephone. Recently, a slot for the semiconductor memory card is provided as a standard not only in the portable device but also in a stationary device such as a digital television and a DVD recorder, and thus the demand for the semiconductor memory card is further increasing.

The semiconductor memory card described above includes a flash memory (mainly NAND flash memory) serving as a non-volatile main storage memory, and a memory controller for controlling the same. The memory controller carries out read/write control of data with respect to the flash memory in accordance with a read/write command of data from an access device represented by a digital still camera main body, or the like.

The writing of data from the memory controller to the flash memory is carried out in units called a page. The main stream in a recent flash memory is a page size of about 4 kB (kilobyte) or 8 kB.

The flash memory includes a number of memory elements called cells, and stores information by accumulating charges in each cell or discharging charges from each cell. However, the information stored in the cell may get lost due to degradation of the cell or the like. The memory controller thus generally generates an error correcting code with respect to write data from the access device, and stores the same in the flash memory with the write data. Thus, even if an error occurs during the reading of the data, correction can be made if the number of error bits is within a correction capability of the error correcting code to be applied, so that correct data can be read. For example, Japanese Patent Publication No. 2005-292925 proposes a method of alternately storing the write data (user data) and the error correcting code (additional data) in a page of the flash memory.

In the method described above, however, correct data cannot be read if an error beyond the correction capability of the error correcting code occurs during the reading of the data.

SUMMARY

The present invention has been made in view of the above problems, and an object of the present invention is to provide a non-volatile storage device capable of reading data correctly even if an error beyond the correction capability of the error correcting code occurs during the reading of the data.

To solve the above problems, the present inventors have devised a method of further giving a second error correcting code with respect to a set of data to which an error correcting code (hereinafter referred to as first error correcting code) is given. For example, the present inventors have devised a method of giving a parity of one page with respect to the data for four pages as the second error correcting code. In this manner, even if an error beyond the correction capability of the first error correcting code occurs, correct data can be read by using the second error correcting code (parity).

However, in the method described above, the data unit managed by the memory controller becomes large if the second error correcting code is given, and hence the overhead becomes large if the data size of the data write from the access device is small and the speed of the data write lowers.

Since the parity for one page is given to the data for four pages in the previous example, the memory controller carries out management of input/output data in units of five pages. For example, even if the size of the data write from the access device is one page, the memory controller writes a total of five pages, the data for four pages and the parity for one page with respect thereto, in the flash memory. In this case, one page of the data for four pages is configured by data received from the access device, but the remaining three pages are configured by existing data read from the non-volatile memory. Therefore, the overhead in this case inevitably becomes large compared to the case in which the size of the data write from the access device is four pages.

Further, the present invention has been made in view of the above problems, and provides a non-volatile storage device and a memory controller capable of efficiently carrying out writing of data of a small data size even if the first and second error correcting codes are given in the writing of data to the non-volatile memory.

A non-volatile storage device according to the present invention relates to a non-volatile storage device, which communicates with an access device and carries out reading and/or writing of data in accordance with a command from the access device, the device including one or more non-volatile memories for storing data; and a memory controller for carrying out control of the non-volatile memory; wherein the non-volatile memory includes a plurality of blocks, which are erase units, each of the blocks including a plurality of pages, which are write units of data; and the memory controller arranges a first logical block in one region by combining the plurality of blocks, and arranges a second logical block in a different region by combining the plurality of blocks, assigns a plurality of error correcting groups each configured by the plurality of pages to the first logical block, assigns data and first and second error correcting codes with respect to the data to the error correcting group, assigns a plurality of multiplexed groups each configured by the plurality of pages to the second logical block, multiplexes and assigns the data and the first error correcting code with respect to the data to the multiplexed group, writes data to the second logical block when a data size is smaller than a predetermined size and writes data to the first logical block when the data size is greater than or equal to a predetermined size when writing data, and includes a valid data management table for managing which one of the logical blocks, the first logical block and the second logical block, stores the valid data with respect to an identical logical address.

A memory controller according to the present invention relates to a memory controller for carrying out control of one or more non-volatile memories for storing data, wherein the non-volatile memory includes a plurality of blocks, which are erase units, each of the blocks including a plurality of pages, which are write units of data; and the memory controller arranges a first logical block in one region by combining the plurality of blocks, and arranges a second logical block in a different region by combining the plurality of blocks, assigns a plurality of error correcting groups each configured by the plurality of pages to the first logical block, assigns data and first and second error correcting codes with respect to the data to the error correcting group, assigns a plurality of multiplexed groups each configured by the plurality of pages to the second logical block, multiplexes and assigns the data and the first error correcting code with respect to the data to the multiplexed group, writes data to the second logical block when a data size is smaller than a predetermined size and writes data to the first logical block when the data size is greater than or equal to a predetermined size when writing data, and includes a valid data management table for managing which one of the logical blocks, the first logical block and the second logical block, stores the valid data with respect to an identical logical address.

According to the present invention, there are provided a non-volatile storage device and a memory controller capable of correctly reading data even if an error beyond a correction capability of a first error correcting code occurs when reading data by giving a second error correcting code to a set of data to which a first error correcting code is given and then storing the same in a non-volatile memory. Furthermore, according to the present invention, there are provided a non-volatile storage device and a memory controller capable of efficiently carrying out writing of data of a small size even if first and second error correcting codes are given in the writing of data to a non-volatile memory by arranging a multiplexed group in a second logical block to write data smaller than a predetermined size.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

First Embodiment

1.1 Configuration of Non-Volatile Storage System

A configuration of a non-volatile storage system1000according to a first embodiment of the present invention will be described with reference toFIGS. 1 to 6.

FIG. 1is a schematic configuration diagram of the non-volatile storage system1000according to the first embodiment of the present invention. As shown inFIG. 1, the non-volatile storage system1000includes a non-volatile storage device1and an access device2, to which the non-volatile storage device1is attached. The non-volatile storage device1and the access device2are connected by a bus B1, so that communication can be carried out bi-directionally. The non-volatile storage device1carries out reading and/or writing of data in accordance with a command from the access device2. In this case, the non-volatile storage device1is, for example, a semiconductor memory card. The access device2is, for example, a digital still camera for recording a still image content in a semiconductor memory card.

As shown inFIG. 1, the non-volatile storage device1includes a memory controller11, and one or more non-volatile memories12for storing data. The memory controller11and the non-volatile memory12are connected by a bus B2. The memory controller11transmits and receives data, that is, carries out reading/writing of data as well as transmission of a command and reception of a response with the non-volatile memory12via the bus B2to control the non-volatile memory12. If a plurality of non-volatile memory12are provided, a plurality of bus B2may be provided.

The memory controller11is a module that carries out the entire control of the non-volatile storage device1, and is configured, for example, as an LSI (Large Scale Integration) including a CPU and the like. The non-volatile memory12is, for example, a NAND flash memory.

As shown inFIG. 1, the memory controller11includes a CPU101, RAM102, a ROM103, an access device IF (interface) section104, a buffer105, and a non-volatile memory IF (interface) section106. As shown inFIG. 1, each function section of the memory controller11is connected via a bus BC1. The memory controller11may have a configuration in which all or part of the function sections of the memory controller11are directly connected.

The access device IF section104is a connecting section of the non-volatile storage device1and the access device2. The transmission and reception of control signals and data of the access device2and the non-volatile storage device1are carried out through the access device IF section104.

The non-volatile memory IF section106is a connecting section of the memory controller11and the non-volatile memory12. The transmission and reception of control signals and data of the memory controller11and the non-volatile memory12are carried out through the non-volatile memory IF section106.

The buffer105is a memory for temporarily storing data received from the access device2via the access device IF section104, data transmitted (output) to the access device2via the access device IF section104, data read from the non-volatile memory12via the non-volatile memory IF section106, date to write to the non-volatile memory12via the non-volatile memory IF section106, and the like.

The ROM103stores a program for controlling the non-volatile storage device1. This program is loaded to the RAM102and then executed by the CPU101.

Specifically, as shown inFIG. 1, the ROM103includes a command processing unit111, an address management unit112, a code processing unit113, and a non-volatile memory control unit114. In the present embodiment, the command processing unit111, the address management unit112, the code processing unit113, and the non-volatile memory control unit114are assumed to be implemented by software on the ROM103, but the present invention is not limited thereto, and all or part of the command processing unit111, the address management unit112, the code processing unit113, and the non-volatile memory control unit114may be implemented by hardware.

The command processing unit111is a function unit for interpreting the command and the parameter related to the command received from the access device2via the access device IF section104, and executing the process of the command.

The address management unit112carries out the overall address management of the non-volatile memory12, but valid data is not stored in the address management unit112itself. First, the address management unit112manages a physical address of a logical-physical conversion table (to be described later) in which a logical address in a logical address space provided by the non-volatile storage device1as an address space accessible from the access device2, and a physical address in the non-volatile memory12are associated. The address management unit112manages the physical address of the valid data management table, to be described later. Furthermore, the address management unit112manages a physical address of a free block, which is a block reusable for data write, a physical address of a defective block not usable for data write, and the like.

The code processing unit113carries out processing of the first and second error correcting codes with respect to the data read or written with respect the non-volatile memory12. The error correcting code herein is, for example, a Reed Solomon code or parity.

The code processing unit113generates the first error correcting code with respect to the data at the time of writing data to the non-volatile memory12. Furthermore, the code processing unit113generates the second error correcting code with respect to the data and the first correcting code of the relevant data. The data, the first error correcting code, and the second error correcting code are then written to the non-volatile memory12.

Further, the code processing unit113reads the first error correcting code with the data when reading data from the non-volatile memory12, and carries out detection and correction of error of the read data. If an error in which correction cannot be made by the first error correcting code is detected, the second error correcting code is further read from the non-volatile memory12, and the detection and correction of the error are carried out.

The non-volatile memory control unit114is a device driver for processing a control signal transmitted and received via the non-volatile memory IF section106.

FIG. 2is a diagram showing a configuration example of the non-volatile memory12according to the present embodiment. The non-volatile memory12includes a plurality of blocks (physical blocks)121, which are erase units of data. The size of each block121is about 1 MB (megabyte).

FIG. 3is a diagram showing a configuration example of the block121shown inFIG. 2. The block121includes a plurality of pages122, which are write units of data. The size of each page122is about 8 kB, for example. The number of pages per one block121is, for example, 128 pages.

FIG. 4is a diagram showing a region set in the non-volatile memory12according to the present embodiment. The region in the non-volatile memory12herein is divided based on the type of information stored in the non-volatile memory12. The region set in the non-volatile memory12includes a first data recording region125, a second data recording region126, an address management table region127, a work region128, a system information region129, and the like.

The first data recording region125is a region for storing the write data from the access device2. The first and second error correcting codes with respect to the data are also stored in addition to the data from the access device2.

The first data recording region125is assigned with a physical capacity greater than or equal to a physical capacity capable of storing the entire data of the readable/writable logical address space provided from the non-volatile storage device1to the access device2.

The second data recording region126is a region for storing the write data from the access device2. The first error correcting code with respect to the data is also stored in addition to the data from the access device2. In the second data recording region126, the data and the first error correcting code with respect to the data from the access device2are duplicated (mirrored) and stored.

The second data recording region126is assigned with a physical capacity capable of storing the data of part of the readable/writable logical address space provided from the non-volatile storage device1to the access device2. For example, a capacity of about a few percent of the readable/writable logical address space is assigned.

Therefore, the first data recording region125and the second data recording region126are both regions for storing the write data from the access device2, but are selectively used according to the size of the write data, as will be described later.

When the non-volatile storage device1according to the present embodiment is manufactured and shipped, a state is obtained in which all initialized data are written only to the first data recording region125. As will be described later, if the size(s) of the write data is(are) all greater than or equal to the page size at the time of the actual data write from the access device2, the write data is(are) stored only in the first data recording region125.

On the other hand, as will be described in detail later, if the size of the write data is smaller than the page size at the time of the actual data write from the access device2, the write data is stored in the second data recording region126. Therefore, the data may be stored in both the first data recording region125and the second data recording region126with respect to a certain (logical) address in the logical address space of the non-volatile storage device1.

In such a case, the data of each region with respect to the same logical address may not be the same. In the writing process to be described later, the write data from the access device2is selectively written to either the first data recording region125or the second data recording region126according to the size of the data, and hence the data of either region, that is, the data written last with respect to a predetermined logical address by the access device2becomes valid. Which data is the valid one is managed by the address management unit112and the valid data management table.

The address management table region127is a region for storing various types of table information necessary for the address management unit112to carry out address management. The various types of table information includes a conversion table of a logical address and a physical address (hereinafter referred to as “logical-physical conversion table”), a table for managing the valid data stored in the second data recording region126(hereinafter referred to as “valid data management table”), an address table of a free block, and the like.

The work region128is a region configured by free blocks and not stored with valid data.

The system information region129is a region for storing system information interiorly used by the memory controller11. Furthermore, the first and second error correcting codes with respect to the system information are also stored. Part or all of the system information may be duplicated (mirrored) and stored.

FIG. 5is a diagram showing an example of the logical-physical conversion table according to the present embodiment. The logical-physical conversion table stored in the address management table region127of the non-volatile memory12stores corresponding information of the address of the logical block and the address of the physical block in each region of the non-volatile memory12.

InFIG. 5, “0x” indicates that the value is a hexadecimal number. As shown inFIG. 5, the logical address space of the first data recording region125is assumed to coincide with the readable/writable logical address space provided by the non-volatile storage device1with respect to the access device2, and the logical address space of other regions (e.g., second data recording region126) is assumed to represent a virtual space different from the above. The high four bits of the physical block address are identification numbers of the non-volatile memory12, and the other bits are identification numbers of the block in the non-volatile memory12. In the example shown inFIG. 5, the blocks (identification number in each non-volatile memory12is 0x0010, 0x0010, 0x0010, 0x0010, 0x0010) in the five different non-volatile memories12(identification number is 0, 1, 2, 3, 4) are assigned with respect to the logical block having the logical block address of 0x0000.

As will be described later, the data arrangement method differs in the first data recording region125and the second data recording region126, respectively, but in either case, one logical block is made up of five physical blocks. Accordingly, the address management by the address management unit112is simplified.

FIG. 6is a diagram showing an example of the valid data management table according to the present embodiment. The valid data management table stored in the address management table region127of the non-volatile memory12is a table for managing valid data stored in the second data recording region126(i.e., data written last to predetermined logical address by access device2). In the examples shown inFIGS. 5 and 6, the data worth one page (e.g., 8 kB) in the logical address space of the access device2is assumed to be stored with respect to one of the virtual logical blocks assigned to the second data recording region126to clarify and simplify the description.

In the valid data management table shown inFIG. 6, the following addresses are managed as a set: the address of the virtual logical block (logical block address inFIG. 5), the logical address (logical block address, logical page address) for one page of the access device2stored in the relevant logical block, the physical address (physical block address, physical page address) where the relevant data is stored, and the physical address (physical block address, physical page address) where copy data (other duplicated data) of the relevant data is stored.

Here, if valid data is not stored in a certain logical block, the address management unit112sets an invalid value to the logical address of data, so that determination can be made that valid data is not stored in the logical block. When setting an invalid value in the logical address of data in the valid data management table, the address management unit112sets, for example, the value of the logical block to “0xFFFF”, and sets the value of the logical page to “0xFFF”.

Therefore, by referencing the valid data management table, the address management unit112can determine whether or not valid data with respect to a predetermined logical address is stored in the second data recording region126. Furthermore, if valid data is stored in the second data recording region126, a physical position (address) in the second data recording region126can be specified.

1.2 Arrangement of Error Correcting Code

Next, the arrangement of the first and second error correcting codes when the memory controller11stores data in the non-volatile memory12will be described with reference toFIGS. 7 to 10.

FIG. 7is a diagram showing one example of a configuration of a page storing the data (hereinafter referred to as data page) according to the present embodiment. In the data page, the data and the first error correcting code with respect to the relevant data are arranged in the page. InFIG. 7, the first error correcting code is described as “ECC”.

As shown inFIG. 7, when giving the first error correcting code in a divided manner with respect to the data stored in the page, the data and the first error correcting code are alternately arranged with the divided data and the first error correcting code with respect to the divided data as a set.

When reading the data from the non-volatile memory12, the first error correcting code with respect to the data is always read with the data, and thus the overhead of a control signal at the time of reading (e.g., address specification or the like) can be reduced by continuously arranging them in the same page.

FIG. 8is a diagram showing an example in which the second error correcting code is given to one or more data pages, according to the present embodiment. In the present embodiment, parity is used for the second error correcting code, and a page storing the second error correcting code is referred to as a parity page. Hereinafter, a combination of one or more data pages and the parity page with respect to such data pages is referred to as “parity group”.

The error correcting code other than the parity (e.g., Reed Solomon code) may be used as the second error correcting code. In this case, the parity group may be more generally referred to as an error correcting group.

In the example shown inFIG. 8, one parity page is given with respect to four data pages to configure one parity group. In the parity page, for example, the value of XOR (exclusive OR) of the data stored in each data page is stored. Furthermore, the first error correcting code with respect to the value of the XOR is stored.

In the example shown inFIG. 8, the ratio of the data page and the parity page is 4 to 1, but other arbitrary ratios may be applied. The capacity of data that can be stored in the non-volatile memory12increases as the ratio of the data page becomes greater. The error correction capability with respect to the data page increases as the ratio of the parity page becomes greater.

FIG. 9is a diagram showing one example of an arrangement of a parity group according to the present embodiment. The arrangement shown inFIG. 9is applied to the first data recording region125, which are regions for storing the parity (second error correcting code), and the system information region129.

InFIG. 9, D0, D1, . . . , D15represent the data page, P0-3represents the parity page with respect to the data pages D0to D3, P4-7represents the parity page with respect to the data pages D4to D7, P8-11represents the parity page with respect to the data pages D8to D11, P12-15represents the parity page with respect to the data pages D12to D15.

Each parity group is arranged over five physical blocks121a,121b,121c,121d,121e. Thus, the reading and writing of data to each parity group become parallel access to different physical blocks and can be carried out at high speed. Similarly, the reading and writing of successive parity groups can be carried out at high speed.

The address management process in the address management unit112can be simplified by configuring and arranging the parity group such that the parity group is not arranged over a plurality of logical blocks. In the example ofFIG. 9showing the arrangement of the parity group, the management in the address management unit112can be simplified by managing the five physical blocks121a,121b,121c,121d,121eas one logical block.

FIG. 10is a diagram showing one example of an arrangement of a duplexed group according to the present embodiment. The duplexed group is a group configured by the duplicated (mirrored) data pages and is configured by two pages, the data page and the copy thereof. The arrangement shown inFIG. 10is applied to the second data recording region126and the system information region129, which are regions to apply duplexing.

Each duplexed group is arranged across two of the five blocks121f,121g,121h,121i,121j. Thus, the reading and writing of each duplexed group become parallel accesses to the different physical blocks, and can be carried out at high speed. Similarly, the reading and writing of the successive duplexed groups can be carried out at high speed.

The duplexed group may be configured such that the duplexed group is not arranged across a plurality of logical blocks. Accordingly, the address management process in the address management unit112can be simplified.

As described above, the first data recording region125is assigned with a physical capacity greater than or equal to a physical capacity capable of storing the entire data of the readable/writable logical address space provided from the non-volatile storage device1to the access device2. On the other hand, the second data recording region126is assigned with the physical capacity capable of storing the data of part of the readable/writable logical address space provided from the non-volatile storage device1to the access device2. For example, a capacity of about a few percent of the readable/writable logical address space is assigned. Therefore, the size of the logical address space configured by the logical blocks arranged in the second data recording region126is smaller than the size of the logical address configured by the logical blocks arranged in the first data recording region125.

Furthermore, the size of the logical block (number of logical blocks) of the duplexed group inFIG. 10may be the size of the logical block (number of logical blocks) same as the logical block arranging the parity group shown inFIG. 9, so that the address management process in the address management unit112can be further simplified. In the example ofFIG. 10showing the arrangement of the duplexed group, the management in the address management unit112is simplified by managing the five blocks121f,121g,121h,121i,121jas one logical block.

1.3 Operation of Non-Volatile Storage System

Next, the operation of the non-volatile storage system1000will be described with reference toFIGS. 11 to 13.

The non-volatile storage device1is attached to the access device2, and performs the process corresponding to the command issued by the access device2. The access device2issues a command (e.g., write command or read command) necessary for recording and reproduction of still image data, moving image data, and the like to the non-volatile storage device1, and carries out transmission and reception of the data.

1.3.1 Writing Process

The access device2issues the write command to the non-volatile storage device1and transfers the write data so that the writing process is carried out in the non-volatile storage device1.FIG. 11is a flowchart showing a procedure of the writing process of the non-volatile storage device1according to the first embodiment of the present invention.

First, the process in step S101will be described. In the non-volatile storage device1, upon receiving the write command from the access device2through the access device IF section104, the command processing unit111acquires parameters such as write address and size associated with the write command. From these parameters, the command processing unit111determines whether to write the received data in the first data recording region125as a parity group or to write in the second data recording region126as duplexed group. In the present embodiment, determination is made to carry out the writing of the former case when the size of the write data is greater than or equal to the page size, and the writing of the latter case when the size of the write data is smaller than the page size. The logical address of the parity group or the duplexed group for carrying out the writing is specified, and such information is notified to the address management unit112.

The address management unit112determines a physical write destination in the non-volatile memory12by referencing the information acquired from the command processing unit111, the information of the conversion table of the logical address and the physical address, the address information of the free block, and the information of a table managing the write state to the block (i.e., state related to data of what logical address is written up to which page in which block).

Next, the process in step S102will be described. If the command processing unit111selects the writing for the parity group in the process of step S101, the process proceeds to the process in step S103. Herein, a case in which the command processing unit111selects the writing for the parity group is when the size of the write data is greater than or equal to the page size. On the other hand, when the command processing unit111selects the writing for the duplexed group, the process proceeds to step S109. Herein, a case in which the command processing unit111selects the writing for the duplexed group is when the size of the write data is smaller than the page size.

Next, the process in step S103will be described. The command processing unit111instructs the code processing unit113to prepare for the writing of the parity group. The code processing unit113ensures a region for calculation of the second error correcting code in the buffer105, and sets a value of this region as an initial value.

Next, the process in step S104will be described. The command processing unit111stores the write data from the access device2to the buffer105through the access device IF section104. The code processing unit113generates the first error correcting code with respect to the write data. The information of the data page including the write data and the first error correcting code thereof is generated in the buffer105. In generating the information of the data page, if the write data received from the access device2is not sufficient for it (e.g., when the access device2instructs writing from the address in the middle of the parity group or data page), the address management unit112is referenced to read the existing data of the non-volatile storage device1and generate the first error correcting code with respect thereto. The insufficiency in information of the data page is compensated by the existing data and the first error correcting code with respect thereto.

Next, the process in step S105will be described. The code processing unit113references the value set in the region for calculation of the second error correcting code ensured in step S103and the information of the data page generated in step S104to carry out the calculation of the second error correcting code (e.g., XOR (exclusive OR) calculation), and rewrites the result to the region for calculation of the second error correcting code ensured in step S103.

Next, the process in step S106will be described. The non-volatile memory control unit114writes the information of the data page generated in step S105to the physical write destination determined in step S101through the non-volatile memory IF section106.

Next, the process in step S107will be described. If the data page written in immediately previous step S106is the termination of the parity group, the process proceeds to the process of step S108. If not, the process returns to the process of step S104, and the processing of the next data page in the parity group is carried out.

Next, the process in step S108will be described. The code processing unit113generates the first error correcting code with respect to the parity, with the calculation result of the second error correcting code generated in step S105as the parity. The non-volatile memory control unit114writes the parity and the first error correcting code thereof as the parity page in the physical write destination determined in step S101through the non-volatile memory IF section106. Thereafter, the process proceeds to the process of step S112.

Next, the process in step S109will be described. The process of step S109is the same as that of step S104, and the information of the data page is generated on the buffer105.

Next, the process in step S110will be described. The non-volatile memory control unit114writes the information of the data page generated in step S109in the physical write destination determined in step S101through the non-volatile memory IF section106.

Next, the process in step S111will be described. The non-volatile memory control unit114writes the information of the data page generated in step S109to the physical write destination determined in step S101through the non-volatile memory IF section106. Therefore, the same data page are duplicated and written in step S110and step S111. Thereafter, the process proceeds to the process of step S112.

Next, the process in step S112will be described. The address management unit112reflects the result of the writing of the parity group from step S103to step S108or the result of the writing of the duplexed group from step S109to step S111on the various types of table information such as the logical-physical conversion table and the valid data management table. That is, when the writing of the duplexed group is carried out, the information of the valid data management table is updated. When the writing of the parity group is carried out, the update to make the registration of the logical address in the valid data management table invalid is carried out if the writing is carried out on the logical address registered in the valid data management table. If a predetermined condition matches (e.g., writing is carried out to boundary of logical blocks), the non-volatile memory control unit114writes the table information, updated by taking in the matched condition, in the address management table region127through the non-volatile memory IF section106.

Next, the process in step S113will be described. If all the write data from the access device2is written, the writing process is terminated. If not, the process returns to the process of step S101, and as for the data from the access device2, the writing of data for which writing is not yet carried out is continued.

As described above, in the non-volatile memory device1according to the present embodiment, the writing of a total of two pages, data page for one page and a copy (data page) for one page, is carried out in the writing process for smaller than the page size in the access device2. The number of pages (two pages) in such writing is less than the number of write pages (five pages) required for updating the entire parity group, and thus the writing is efficiently carried out.

If the access device2manages the logical space in the non-volatile storage device1by the file system such as the FAT, the information of the file entry and the FAT may be frequently updated at a very small size of about one sector (e.g., 512 B). The writing process in the non-volatile storage device1according to the present invention is particularly effective in such a case.

Since the physical capacity of the second data recording region126is limited, only the data of the logical address of one part of the logical address space specified by the access device2can be stored. Therefore, if the second data recording region126is insufficient in the writing process, a process of moving the data stored in the second data recording region126to the first data recording region125to increase the availability of the second data recording region126becomes necessary. In order not to cause such a movement process as much as possible, the physical capacity of the second data recording region126is desirably determined according to the write pattern (combination of address, size) of the access device2.

1.3.2 Reading Process

The reading process is carried out in the non-volatile storage device1when the access device2issues a read command to the non-volatile storage device1. The read data is sequentially transferred from the non-volatile storage device1to the access device2.FIG. 12is a flowchart showing a procedure of the reading process of the non-volatile storage device1according to the first embodiment of the present invention.

First, the process in step S201will be described. In the non-volatile storage device1, when receiving the read command from the access device2through the access device IF section104, the command processing unit111acquires parameters such as read address and size associated with the read command. From these parameters, the command processing unit111specifies the logical address of the parity group or the duplexed group to be read, and notifies the information to the address management unit112. The address management unit112determines the physical read destination in the non-volatile memory12by referencing the information acquired from the command processing unit111, the information of the conversion table of the logical address and the physical address, the address information of the free block, and the information of a table managing the write state to the block (i.e., state related to data of what logical address is written up to which page in which block).

In particular, the address management unit112references the valid data management table to determine whether the read destination is the parity group of the first data recording region125or the duplexed group of the second data recording region126. If registration of the logical address to be read has been made in the valid data management table, the read destination becomes the duplexed group of the second data recording region126.

Next, the process in step S202will be described. The non-volatile memory control unit114carries out the reading of the information of the data page from the physical read destination determined in step S201through the non-volatile memory IF section106. The information of the read data page (i.e., data and first error correcting code with respect to data) is stored in the buffer105.

Next, the process in step S203will be described. The code processing unit113carries out error detection and correction of the data using the first error correcting code stored in the buffer105in step S202. If an error that cannot be corrected with the correction capability based on the first error correcting code is detected, the process proceeds to the process of step S204. In other cases, the error correction is carried out using the first error correcting code, the information after the error correction is overwritten on the data in the buffer105, and the process proceeds to the process of step S208.

If the information of the data page read in step S202includes information other than the read address specified by the access device2(e.g., when access device instructs reading from address in the middle of data page), the calculation of the first error correcting code with respect to the portion other than the read address may be omitted.

Next, the process in step S204will be described. In the process of step S201, whether the data page on which the read error occurred in step S203belongs to the parity group or belongs to the duplexed group is determined based on the information of the read destination determined by the address management unit112. The process proceeds to the process of step S205if the data page belongs to the parity group. The process proceeds to the process of step S207if the data page belongs to the duplexed group.

Next, the process in step S205will be described. The non-volatile memory control unit114carries out the reading of the information of the parity group, to which the data page subjected, to the reading in step S202belongs, from the physical read destination determined in step S201through the non-volatile memory IF section106. Since the first error correcting code is given to the information of the read parity group (i.e., data page other than data page for which reading is carried out in step S202, and parity page), the code processing unit113stores the data and the parity in the buffer105after carrying out the error correction of the data using the first error correcting code.

Next, the process in step S206will be described. The code processing unit113carries out the error detection and correction of the data using the information of the data page and the parity page (second error correcting code) stored in the buffer in step S205. If an error that cannot be corrected with the correction capability based on the second error correcting code is detected, the error process (not shown) is carried out, and the reading process is terminated. In other cases, the error correction is carried out using the second error correcting code, the information after the error correction is overwritten on the data in the buffer105, and the process proceeds to the process of step S208.

For example, if the XOR (exclusive OR) calculation is applied for the calculation of the second error correcting code, the XOR calculation of the data of the data page other than the data page for which the reading is carried out in step S202and the parity of the parity page is carried out. Accordingly, the data of the data page for which the reading is carried out in step S202is restored.

Next, the process in step S207will be described. The non-volatile memory control unit114carries out the reading of the information (i.e., information of other data page) of the duplexed group, to which the data page subjected to the reading in step S202belongs, from the physical read destination determined in step S201through the non-volatile memory IF section106. The information (i.e., data and first error correcting code with respect to data) of the read data page is stored in the buffer105. The code processing unit113carries out the error detection and correction of the data using the first error correcting code stored in the buffer105. If an error that cannot be corrected with the correction capability based on the first error correcting code is detected, the error process (not shown) is carried out, and the reading process is terminated. Otherwise, the error correction is carried out using the first error correcting code, the information after the error correction is overwritten on the data in the buffer105, and the process proceeds to the process of step S208.

Next, the process in step S208will be described. The command processing unit111transmits the data (after error correction process) stored in the buffer105to the access device2as read data.

Next, the process in step S209will be described. If all the read data specified by the access device2is transmitted, the reading process is terminated. If not, the process returns to the process of step S201, and as for the data to the access device2, the reading of non-transmitted read data is continued.

The reading from the non-volatile memory12in step S202and step S205is desirably carried out at high speed by the parallel process for a plurality of blocks if the read destination is the parity group. In this case, the process may proceed to the process of the next step immediately after the reading of the data page and the parity page is started.

1.3.3 Initialization Process

After the non-volatile storage device1is attached to the access device2, and the power supply from the access device2to the non-volatile storage device1is started, the access device2issues an initialization command to the non-volatile storage device1to enable the reading and writing of data between the access device2and the non-volatile storage device1.FIG. 13is a flowchart showing a procedure of an initialization process of the non-volatile storage device1according to the first embodiment of the present invention.

First, the process in step S301will be described. In the non-volatile storage device1, upon receiving an initialization command from the access device2through the access device IF section104, the command processing unit111carries out an initialization setting of the hardware of the memory controller11. The connection check of the non-volatile memory12connected to the non-volatile memory IF section106and the like is also carried out.

Next, the process in step S302will be described. The non-volatile memory control unit114reads first system information from a predetermined read destination of the non-volatile memory12through the non-volatile memory IF section106. The first system information is information previously written in the non-volatile memory12at the time of the manufacturing of the non-volatile storage device1, and includes various types of control information in the non-volatile storage device1. The first system information may be the type and number of the non-volatile memory12connected to the memory controller11, the configuring information of the parity group, the configuration information of the duplexed group, the type and correction capability of the first and second error correcting codes, the information related to a physical storage position of the second system information (to be described later), and the information related to the address of the initial defective block. When an error occurs in the reading of the first system information, the error correction by the first and/or second error correcting code is carried out.

The address management unit112, the code processing unit113, and the non-volatile memory control unit114carry out an internal initialization process according to the content of the read first system information.

Next, the process in step S303will be described. The non-volatile memory control unit114reads the second system information from a predetermined read destination of the non-volatile memory12(e.g., specified in first system information) through the non-volatile memory IF section106. The second system information is information previously written to the non-volatile memory12at the time of the manufacturing of the non-volatile memory device1and then updated when the non-volatile storage device1is used, and includes various types of control information in the non-volatile storage device1. For example, the second system information includes the information related to the conversion table of the logical address and the physical address, the information related to the valid data management table, the information related to the address of the latecoming defective block, the information related to the number of write times and the number of erase times of the block, the information related to the address of the free block, and the information related to the parity table. When an error occurs in the reading of the second system information, the error correction by the first and/or second error correcting code is carried out.

Next, the process in step S304will be described. The address management unit112generates in the RAM102the table information required for address management, according to the content of the read second system information.

Next, the process in step S305will be described. When an error exceeding a predetermined amount (correctable with first or second error correcting code) occurs in the reading from the non-volatile memory12in step S302and step S303, the process proceeds to the process of step S306. If not, the process proceeds to the process of step S307.

Next, the process in step S306will be described. The code processing unit113generates the first and second error correcting codes with respect to the data of an area where the error exceeding a predetermined amount occurred in the reading from the non-volatile memory12in step S302and step S303. The non-volatile memory control unit114then rewrites the data and the generated first and second error correcting codes to the non-volatile memory12as new first or second system information.

Next, the process in step S307will be described. The command processing unit111notifies the access device2through the access device IF section104that the initialization process of the non-volatile storage device1is completed, and terminates the initialization process.

The non-volatile storage device1of the present embodiment1is a non-volatile storage device that can communicate with the access device2, and that carries out reading and/or writing of data according to a command from the access device2. The non-volatile storage device1includes one or more non-volatile memories for storing data, and a memory controller11for carrying out the control of the non-volatile memory12. The non-volatile memory12includes the plurality of blocks121, which are erase units, and the block121includes the plurality of pages122, which are write units of data.

The memory controller11arranges the first logical block in the first data recording region125by combining a plurality of blocks121. Furthermore, the memory controller11arranges the second logical block in the second data recording region126by combining the plurality of blocks. The memory controller11assigns a plurality of parity groups each configured by a plurality of pages122to the first logical block, and the data and the first and second error correcting code with respect to the data are respectively assigned to the relevant parity group. The memory controller11assigns a plurality of multiplexed groups each configured by a plurality of pages122to the second logical block, and the data and the first error correcting code with respect to the data are respectively multiplexed and assigned to the multiplexed group. Further, in writing the data, the memory controller11writes the data in the second logical block if the data size is smaller than a predetermined size, and writes the data in the first logical block when the data size is greater than or equal to a predetermined size, and includes a valid data management table for managing which one of the logical blocks, the first logical block and the second logical block, stores the valid data with respect to an identical logical address.

As described above, in the non-volatile storage device1, the second error correcting code is also stored in addition to the first error correcting code stored in the same page as the data. When writing the data, the first and second error correcting codes are given to the data and then written. When reading the data, the error correction is carried out using the first and/or second error correcting code given to the data.

As a result, in the present embodiment, even if an error beyond the correction capability of the first error correcting code given to the data page occurs in the reading of the data page, the other data page and parity page configuring the parity group can be read and the information of the data page can be restored using the parity page (second error correcting code).

Furthermore, when the access device2carries out the writing to the non-volatile storage device1at a size smaller than a predetermined size, the duplexed group is configured, and the page data and the copy of the page data are written to the second data recording region126of the non-volatile memory12. The size of the logical address space corresponding to the second data recording region126is set to be smaller than the size of the logical address space corresponding to the first data recording region125(of the non-volatile memory12) to which the data of a size greater than a predetermined size is written. As a result, the number of write pages to the non-volatile memory12at the time of the data write of a size smaller than a predetermined size can be reduced, and efficient writing can be realized.

The values described in the above embodiment is merely an example, and other values may be used. For example, the values of the respective number of pages in the data page and the parity page configuring the parity group are all merely an example, and the present invention is not limited to the values described in the above embodiment.

Moreover, arbitrary multiplexing such as tripling and quadrupling, other than the duplexing, may be applied to the duplexed group. In this case, the duplexed group may be more generally referred to as a multiplexed group.

Other Embodiments

The present invention has been described based on the above embodiments, but the present invention is, of course, not limited to the above embodiments, and the embodiment can be changed within a scope not deviating from the technical concept of the invention. Changes can be made as below.

(1) In the access device2, the non-volatile storage device1, the memory controller11, and the non-volatile storage system1000of the embodiment described above, each function block may be individually formed to one chip by a semiconductor device such as an LSI, or may be formed to one chip so as to include part of or all of the function blocks.

In the above description, the LSI has been provided by way of example, but the function block may be formed to a chip by a semiconductor device such as IC (Integrated Circuit), system LSI, super LSI, ultra LSI, or the like due to the difference in degree of integration.

Moreover, the method of forming an integrated circuit is not limited to the LSI, and an integrated circuit may be realized with a dedicated circuit or a general-purpose processor. Furthermore, an FPGA (Field Programmable Gate Array) capable of being programmed after the LSI manufacturing, or a reconfigurable processor capable of reconfiguring the connection and the setting of the circuit cells in the LSI may be used.

Further, if a technique of forming an integrated circuit that replaces the LSI appears according to a different technique advanced or derived from the semiconductor technique, the integration of the function blocks may, of course, be carried out using such a technique. For example, biotechnology or the like may be applied.

(2) Each process in the embodiment described above may be implemented by hardware, or may be implemented by software (including cases of being realized with OS (operating system), middleware, or predetermined library). Furthermore, each process may be realized by a mixed process of software and hardware. It should be recognized that the timing adjustment for carrying out each process needs to be carried out when implementing the access device2, the non-volatile storage device1, and the non-volatile storage system1000according to the above-described embodiment by hardware. In the above-described embodiment, the details of the timing adjustment of various types of signals generated in the actual hardware design is omitted for the sake of convenience of explanation.

Moreover, the executing order of the processing method in the embodiment described above is not necessarily limited to the described content of the embodiment described above, and the executing order can be interchanged within a scope not deviating from the technical scope of the present invention.

(3) The non-volatile storage device1according to the embodiment has been described as a detachable storage device like a semiconductor memory card, but may be realized as an information storage module of a type that can be incorporated in a substrate of the access device2.

(4) In order to improve the write speed in a specific region of the first data recording region125(e.g., region where access device2stores management information of file system such as FAT) and the second data recording region126(mainly region where information of file entry is stored), the non-volatile storage device1according to the embodiment described above may have the arrangement of the data and the first and second error correcting codes with respect to such regions as below.

In a configuration using a flash memory of multi-level cell (e.g., cell storing quadrature information per cell) for the non-volatile memory, the arrangement may be such that the information per cell is less than other regions (e.g., storing binary information per cell) in the specific region of the first data recording region125and the second data recording region126. Accordingly, the specific region of the first data recording region125and the second data recording region126can be physically accessed at high speed, and the management information of the file system that is accessed frequently can be efficiently read and written.

The non-volatile storage device and the memory controller according to the present invention can efficiently carry out the writing of data of a small size while improving reliability of stored data by carrying out first and second error corrections. This is obviously useful in the semiconductor memory card, but also in a movie, digital still camera, portable telephone terminal and the like, which are information processing terminals incorporating the non-volatile memory, and can be used in the field related to semiconductor memories.