DRAM cell structure with buried surrounding capacitor and process for manufacturing the same

A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

DESCRIPTION OF THE INVENTION

1. Field of the Invention

This invention pertains in general to semiconductor devices, and, more particularly, to memory cells for a dynamic random access memory (DRAM) and processes for manufacturing the same.

2. Background of the Invention

In the semiconductor industry, DRAMs are among the most important integrated circuits and the source of continuing research and development. There is a continuing effort to increase their storage capacity, improve writing and reading speed, and decrease device dimensions. A DRAM cell generally includes a transistor and a capacitor operated by the transistor. Conventionally, DRAM cell designs can be divided into three types, namely planar, stacked-capacitor and trench. In the planar design, the transistor and capacitor of a cell are produced as planar components. In the stacked-capacitor design, the capacitor of a cell is disposed above the transistor. In the trench design, the transistor is disposed on the surface of a substrate, and the capacitor is disposed in a trench formed in the substrate.

The process of forming a trench, however, requires an accurate alignment of mask work. For deep sub-micron semiconductor devices, a deep trench may have a length-to-diameter aspect ratio of 40:1. Typically, capacitors are formed in the deep and narrow trenches by depositing a dielectric layer on the trench walls and filling the trench with a doped polysilicon layer. As the aspect ratio becomes higher, for example, exceeds 20:1, the trench becomes more difficult to fill.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to DRAM cells that obviate one or more of the problems due to limitations and disadvantages of the related art. The present invention also provides processes for manufacturing the cells.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the cell structures particularly pointed out in the written description and claims thereof, as well as the appended drawings. To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided a memory cell that includes a semiconductor substrate, a capacitor and a transistor, in which the substrate includes an island formed from the substrate, the island having a top portion and at least one sidewall portion, the capacitor is formed contiguous with the sidewall portion, and the transistor is formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

In one aspect of the present invention, the capacitor includes a doped region formed in the sidewall portion, a dielectric layer formed contiguous with the sidewall portion, and a polysilicon layer formed contiguous with the dielectric layer.

In another aspect of the present invention, the memory cell includes a buried strap that couples the first diffused region of the transistor to the second plate of the capacitor.

Also in accordance with the present invention, there is provided a memory device that includes a semiconductor substrate and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, a capacitor and a transistor, in which the island has a top portion and at least one sidewall portion, and is spaced apart from other islands by a bottom surface on the substrate, the capacitor is formed contiguous with the sidewall portion and the transistor is formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

Still in accordance with the present invention, there is provided a process for manufacturing a memory device, the process including defining a semiconductor substrate, etching the substrate to form an array of islands spaced apart from one another by a bottom surface on the substrate, each island having a top portion and at least one sidewall portions, doping the sidewall portion and the bottom surface, forming a dielectric layer contiguous with the sidewall portion, forming a polysilicon layer contiguous with the dielectric layer, electrically isolating the array of islands with an insulating material, forming an oxide layer on a surface of the top portion, forming a gate on the oxide layer, and forming a first diffused region and a second diffused region spaced apart from the first diffused region in the top portion.

In one aspect of the present invention, the process further includes etching the insulating material disposed on the bottom surface in a direction of a bit line to expose the polysilicon layer, depositing a conductor layer on the etched insulating material, and etching the conductor layer to form a first conductor portion and a second conductor portion spaced apart from the first conductor portion, in which the first conductor portion couples the first diffused region to the polysilicon layer.

In another aspect of the present invention, the process further includes etching the insulating material disposed on the bottom surface in the direction of the bit line to expose the second diffused region, and depositing a contact layer on the etched insulating material to couple the second diffused region to the bit line.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1Ashows a top view of a layout of a memory cell array10in accordance with the invention. Referring toFIG. 1, the cell array10includes a substrate12and a plurality of memory cells14formed on the substrate12. A representative cell14A includes a three-dimensional island20, a capacitor30surrounding the island20and a transistor (not shown) formed on the island20. The island20is a part of the substrate12and, in the embodiment, has a substantially rectangular cross section. Other embodiments may include islands in the form of a cylinder. In the cell array10, a trench space18is defined as the space between the areas defined by opposing sidewalls of two adjacent memory cells.

FIG. 1Bshows a perspective view of the cell array10prior to the formation of transistors. Referring toFIG. 1B, each island20includes four sidewall portions22wherein a capacitor30is formed and a top portion24where a transistor (not shown) will be formed. Each island20is spaced apart from adjacent islands by a bottom surface16on the substrate12. The trench space18is thus defined between two adjacent islands by their opposing sidewall portions22and the bottom surface16therebetween.

The capacitor30includes a first plate32formed within the sidewall portion22, a dielectric layer34formed contiguous with the sidewall portion22, and a second plate36formed contiguous with the dielectric layer34. In one embodiment of the invention, the first plate32is a doped silicon region, the dielectric layer34is a nitride oxide layer and the second plate36is a polysilicon layer.

FIG. 1Cshows a top view of the layout of the representative cell14A shown inFIG. 1A and, in particular, the first plate32, the dielectric layer34and the second plate36of the capacitor30. In addition,FIG. 1Cshows an insulating material38filling the trench spaces18and remaining spaces among the islands20to electrically isolate the cells. In one embodiment, the insulating material38is oxide.

FIG. 2shows a perspective view of the representative cell14A shown in FIG.1A. Referring toFIG. 2, a transistor40is formed on the top portion24of the island20and includes a gate oxide layer42disposed on a top surface240of the top portion24, a gate44formed on the gate oxide layer42, and a pair of spaced-apart diffused regions46formed in the top portion24. The gate44is coupled to a word line (not shown). The diffused regions46serve as a source/drain pair for the transistor40, and one of the diffused regions46is coupled to a bit line (not shown).

A collar oxide layer48may be disposed on the upper part of the sidewall portion22and contiguous with the dielectric layer34and the second plate36to reduce parasitic leakage at the sidewall portion22. A buried strap50couples one of the diffused regions46of the transistor40to the second plate36of the capacitor30. The buried strap50provides a path for the transistor40to read from or write into the second plate36of the capacitor30. A bit line contact layer60is disposed between two adjacent cells and adjoins the opposing diffused regions46and46′ of the adjacent cells. The bit line contact layer60couples the opposing diffused regions46and46′ to a bit line.

FIG. 3shows a top view of the layout of buried straps50and bit line contacts60in the cell array10. Referring toFIG. 3, as an example of the cell14C, in a bit line (BL) direction, one of the diffused regions (not shown) of the cell14C is coupled to a buried strap50C, and the other diffused region is coupled to a bit line contact60C. The buried strap50C of the cell14C is spaced laterally from the buried strap50D of an adjacent cell14D, and the bit line contact60C is shared by a cell14B and the cell14C. The gate (not shown) of the cell14C is coupled to a word line (WL).

FIG. 4shows a schematic view of a single cell14. The gate44of the transistor40on the top portion24is coupled to a word line (WL). One diffused region46of the transistor40is coupled to a contact layer (CB) and in turn to a bit line (BL). The other diffused region46of the transistor40is coupled to the second plate36(not shown inFIG. 4) of the capacitor30by a buried strap (BS). The first plate32of the capacitor30is coupled to the substrate12, or a reference voltage Vsub.

FIGS. 5Ato5E show the process for manufacturing a memory cell array10in accordance with the invention. Referring toFIG. 5A, the process begins with preparing a substrate12, which may be a silicon substrate, an silicon on insulator (SOI) substrate, or a gallium arsenide substrate. The substrate12can be undoped, lightly doped or heavily doped with dopants. In the embodiment, the substrate12includes a bulk portion that is advantageously a p-type monocrystalline silicon. The substrate12is cleaned to remove contaminants and then etched to form an array of three-dimensional islands20. Each island20, which is a part of the substrate12, includes a top portion24and sidewall portions22, and is spaced apart from adjacent islands20by a bottom surface16on the etched substrate12. The opposing sidewall portions22of two adjacent islands20and the bottom surface therebetween together define a trench space18. Since the process of the invention does not require any accurate mask work in defining a trench, the invention is generally immune to the mask misalignment and high aspect ratio limitations found in conventional techniques.

Next, the sidewall portions22and the bottom surface16are doped with N+ type dopants such as As by, for example, a drive-in process. The N+ doped region32corresponds to the first plate of the capacitor30. The first plate32is coupled to the substrate reference voltage (not shown). Subsequent to the formation of the first plate32, a dielectric layer34such as nitride oxide (NO) is deposited on the sidewall portions22. A polysilicon layer36is then deposited on the dielectric layer34. The polysilicon layer36corresponds to the second plate, or storage node, of the capacitor30.

Referring toFIG. 5B, an insulating material38such as oxide is deposited on the bottom surface16to fill the spaces, including the defined trench spaces18, among the islands20. A chemical mechanical polarization (CMP) process is then performed to polish the layer of insulating material38down to the top surface of the islands20. The insulating material38electrically isolates the cells.

Referring now toFIG. 5C, gate oxide layers42and gates44are formed on a top surface240of the top portion24by conventional processes. The diffused regions46corresponding to the source/drain pair of the transistors40are then formed by ion implantation.

FIG. 5Dshows the formation of a buried strap50to couple the polysilicon layer36of the capacitor30to one of the diffused region46of the transistor40. The insulating material38disposed on every other bottom surface in the direction of a bit line is etched to expose the polysilicon layers36of two adjacent cells. A conductor layer is deposited on the etched insulating material38′. The conductor layer is etched to form a first conductor portion502and a second conductor portion504spaced apart from the first conductor portion502. The first conductor portion502couples the diffused region46of a cell to the polysilicon layer36of the cell, and the second conductor portion504couples the diffused region46′ of the adjacent cell to a polysilicon layer36′ of the adjacent cell.

FIG. 5Eshows the formation of a bit line contact layer60to couple the diffused regions to a bit line. The remaining insulating material38disposed on every other bottom surface in the direction of the bit line is etched to expose the remaining diffused regions46. A contact layer60is then deposited on the etched remaining insulating material38″ to couple the diffused regions46. A passivation layer70such as BPSG (borophosphosilicate glass) is then deposited to provide insulation and protection for the cells.