Advanced interconnection for integrated circuits

An interconnection scheme employing a dual damascene configuration for coupling multi-layer interconnects is presented. The interconnection structure includes an underlying conductive region, generally comprised of a copper or copper-based alloy having a via hole formed thereupon, with a subsequent trench region formed yet thereupon. The via hole and trench regions are coated both on the horizontal and vertical facet with a barrier material which is thereafter anisotropically etched to remove the horizontal segments of the barrier layer. The horizontal segment attached to the conductive region of the underlying conductor is also removed such that the conductive layer formed within the trench and via hole regions directly contact the underlying conductive region. Such a direct interface forgoes the problems present in material dissimilarities and also provides an improved resistivity match.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 depicts an integrated circuit substrate 200 having a first conductive region 202 fabricated thereupon. Conductive region 202 may comprise a metal layer defining an interconnect pattern. Substrate 200 further includes a first dielectric 204 which is formed, for example, of a silicon oxide layer formed through chemical vapor deposition (CVD) or through other processes known by those of skill in the art. Conductive region 202 and dielectric 204 may be configured atop other optional underlying structures 206 . Conductive region 202 is preferably comprised of a copper (Cu) or other copper-based alloys which provide enhanced conductivity. It is however known that copper-based interconnections also suffer from out-diffusion and electromigration problems that require isolation of conductive regions using barrier techniques. Therefore, FIG. 3 depicts a barrier layer 208 for providing isolation between conductive region 202 and dielectric 204 . Conductive region 202 and dielectric 204 may be further planarized in order to provide a more conducive surface for the application of additional layers. A first barrier layer 210 is overlaid upon conductive region 202 and dielectric 204 to provide a horizontal barrier for mitigating Cu out-diffusion and electromigration of the material comprising conductive region 202 . A second dielectric 212 is overlaid upon barrier layer 210 to provide an inter-metal dielectric. Dielectric 212 is typically deposited using a chemical vapor deposition process and is most generally comprised of silicon oxide. If necessary, dielectric 212 may also undergo planarization processes prior to the application of additional and successive layers and processes. Such planarization techniques are appreciated by those of skill in the art and the details of such processes are not contained herein. A second barrier layer 214 overlays dielectric 212 and is also a non-conductive barrier layer for providing Cu out-diffusion and electromigration mitigation of subsequent conductive regions. FIG. 4 depicts a patterning structure for implementing the patterning of a via for connecting a subsequently applied conductive layer to conductive region 202 . In FIG. 4, a photoresist layer 216 is applied and processed using techniques known by those of skill in the art to form an opening in the photoresist which allows for exposure of barrier layer 214 to undergo a process wherein an aperture or portion of barrier layer 214 is removed thereby exposing dielectric 212 for a subsequent etching process. It should be noted that opening 218 in barrier layer 214 is aligned so as to facilitate the formation of a via through second dielectric 212 and in vertical alignment with a portion of conductive region 202 . Following the processing to form an opening or aperture 218 in second barrier layer 214 , photoresist 216 is removed to accommodate subsequent processing steps. FIG. 5 depicts formation of a trench for facilitating interconnection, in accordance with the present invention. A third dielectric layer 220 is overlaid upon second barrier layer 214 using conventional integrated circuit processing techniques known by those of skill in the art such as chemical vapor deposition or other suitable processes. Third dielectric 220 is comprised of silicon oxide and provides both isolative separation between hereafter developed conductive interconnection regions as well as providing a mold into which interconnection trenches may be formed for receiving the conductive interconnection material. A third barrier layer 222 overlays third dielectric 220 and is applied using, preferably, a deposition process. In the preferred embodiment, barrier layer 222 is comprised of a nonconductive material. Barrier layer 222 undergoes an etching process through the application of a photoresist 224 and processing of the photoresist 224 in accordance with processes known by those of skill in the art. The processing of photoresist 224 results in a mask wherein barrier layer 222 may be etched to form opening or aperture 226 within barrier layer 222 . Photoresist 224 is thereafter removed leaving the desired patterning and exposure of dielectric 220 . FIG. 6 depicts a cross-sectional view of an anisotropic etched dual damascene structure, in accordance with a preferred embodiment of the present invention. An anisotropic etching process with barrier layer 222 forming the aperture through which third dielectric 220 is anisotropically etched to form a trench 228 defined horizontally by barrier layer 222 and defined vertically by the presence of barrier layer 214 forming an etch stop. The anisotropic etching process further continues, preferably in the same etching process, to etch a via hole 230 through second dielectric 212 and first barrier layer 210 . Via hole 230 is defined horizontally by the aperture previously etched within barrier layer 214 and further defined vertically by the existence of conductive region 202 . Trench 228 and via hole 230 together combine to form an opening 232 into which a monolithic conductive interconnect will be formed with conductive region 202 . FIG. 7 is a cross-sectional view of an integrated circuit depicting a barrier layer lining the dual damascene opening of the interconnection structure, in accordance with the preferred embodiments of the present invention. As described above, conductive interconnects such as those comprised of copper or copper-based alloys, are susceptible to migration and electromigration of the copper into adjacent dielectric layers which greatly impacts the integrity of the integrated circuit. In order to mitigate such deleterious effects, a fourth barrier layer 234 is conformally applied to the surface areas of opening 232 . Fourth barrier layer 234 may be comprised of, for example, titanium (Ti), titanium nitride (TiN) or tantalum (Ta) or tantalum nitride (TaN), or titanium silicon nitride (TiSiN), or other barrier compositions that minimize out-diffusion of Cu into dielectrics. It should be appreciated that fourth barrier layer 234 is applied to both the vertical and horizontal sidewalls of opening 232 . FIG. 8 is a cross-sectional diagram of the integrated circuit of the present invention after having undergone an etch-back process of the barrier layer. Fourth barrier layer 234 undergo an anisotropic etch-back process wherein the horizontal segments of barrier layer 234 undergoes an anisotropic etched-back wherein the horizontal segments of barrier layer 234 are removed with the vertical segments 234 ′- 234 ″″ remaining. It should be noted that the remaining vertical segments of barrier layer 234 result in a capping of exposed dielectric layers which are susceptible to Cu out-diffusion. It should be further apparent that second barrier layer 214 provides a barrier in the horizontal direction for the conductive material that will hereinafter be placed in opening 232 . It should be further apparent that the horizontal segment of barrier layer 234 located over conductive region 202 has further been removed hereby providing a direct contact between the conductive material to be placed in opening 232 with conductive region 202 . A direct physical interface of the material of conductive region 202 with the conductive layer material to be placed within opening 232 prevents failures associated with material discontinuity resulting from adjacent placement of dissimilar materials. In traditional dual damascene interconnections, the majority of interconnection failures occur at the interface located at the bottom portion of via hole 230 when the horizontal segment of barrier layer 234 remains as an obstacle between the direct connection of the material filling opening 232 with the material comprising conductive region 202 . Additionally, via resistance, a critical integrated circuit device parameter, is increased when there is an intermediary material isolating conductive region 202 . Therefore, the present invention provides an improvement which enables such similar conductive materials to engage in a direct physical interface. FIG. 9 is a cross-sectional diagram of a dual damascene interconnection incorporating a direct interface between the conductive layer filling the dual damascene opening with the conductive region of the underlying structure, in accordance with the preferred embodiment of the present invention. As shown, a conductive layer 236 fills both via hole 230 ( FIG. 6 ) and trench 228 ( FIG. 6 ) in a single monolithic process that provides a direct coupling of conductive layer 236 with conductive region 202 . Conductive layer 236 is comprised of a similar, if not identical, chemical composition as conductive region 202 . Preferably, conductive layer 236 and conductive region 202 are comprised of copper of copper-based metals. FIG. 9 also depicts third barrier layer 222 being comprised of a dielectric compound such that when excessive portions of conductive layer 232 extend beyond opening 232 , subsequent processing or etching of conductive layer 236 does not affect barrier layer 222 . Barrier layer 222 , being dielectric in nature in the preferred embodiment, facilitates the electromigration barrier that is desirable to mitigate electromigration of any conductive layer overlaid upon third barrier layer 222 . FIG. 10 is a cross-sectional diagram illustrating a dual damascene interconnection for providing direct contact between a conductive layer and a conductive region without an intervening thin film or barrier, in accordance with another embodiment of the present invention. FIG. 10 depicts conductive layer 236 having the direct coupling to conductive region 202 as described in the previous figure, however, in the present embodiment, third barrier layer 222 ( FIG. 8 ) is illustrated as being removed since it was comprised of a conductive material. During the processing of the horizontal segments of barrier layer 234 and during any etching or polishing associated with any excessive profile of conductive layer 236 beyond opening 232 , third barrier layer 222 is removed resulting in the cross-sectional profile as depicted. The absence of a third barrier layer in the present embodiment enables the placement of a single barrier layer over both a portion of third dielectric 220 and conductive layer 236 without the adjacent placement of barrier layers. An integrated circuit having a dual damascene interconnection comprised of the various dielectric and barrier layers which facilitates the direct physical coupling of the conductive layer located within the trench and via hole openings with the conductive region of a lower layer has been presented. The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.