Low power circuits for active matrix emissive displays and methods of operating the same

The embodiments of the present invention provide a flat panel display having a plurality of pixels, each comprising a light-emitting device configured to emit light in accordance with a current flowing through the light-emitting device, a transistor coupled to the light-emitting device and configured to provide the current through the light-emitting device, the current increasing with a ramp voltage applied to a control terminal of the transistor, and a switching device configured to switch off in response to the luminance of the light-emitting device having reached a specified level, thereby disconnecting the ramp voltage from the transistor and locking the brightness at the specified level. The switching device is further configured to stay off thereby allowing the luminance of the light-emitting device to be kept at the specified level until the pixel is rewritten in a different frame.

FIELD OF THE INVENTION

The present invention relates to active matrix emissive displays and particularly to low power circuits for active matrix emissive displays and methods of operating the same.

BACKGROUND OF THE INVENTION

The active matrix display employs a thin film circuit at each pixel that allows each pixel in the display to be directly addressed. In a typical active matrix liquid crystal display (AMLCD), each pixel circuit includes a data thin film transistor (TFT) T1connected between a data line Vdataand a liquid crystal display cell LCD and storage capacitor C pair, as shown inFIG. 1. The thin film transistor has a control gate G1connected to an enable voltage Venable. During operation, a data voltage Vdatais placed on drain D of transistor T1and, when gate G1is activated, data voltage Vdatais transferred to storage capacitor C and liquid crystal cell LCD though TFT T1. The power dissipated during the charging of capacitor C and liquid crystal display cell LCD is usually negligible. The power problem in the AMLCD is typically in a backlight circuit that supplies the light, which the LCD modulates. In the case of active matrix emissive displays, particularly the active matrix organic light emitting displays (AMOLED), significant amount of power is consumed to produce light emissions from the pixels, and additional power is required to operate driving circuits in the active matrix, which control the light emissions.

With reference toFIG. 2, a typical driving circuit of an organic light-emitting diode (OLED) active matrix emissive display includes an OLED D1and a power TFT T2serially coupled with each other between a voltage supply VDDand ground. TFT T2has a source S connected to OLED D1, a drain D connected to voltage supply VDD, and a gate G2connected to TFT T1. Capacitor C is coupled between the source S and gate G2of TFT T2. OLED D1has parasitic resistor RDand parasitic capacitor CD. TFT T2supplies current IDto OLED D1. The level of emissions from OLED D1, or, in a more scientific term, the luminance of OLED D1, is proportional to the current ID. Since the voltage across TFT T2and OLED D1is equal to VDD, the power P dissipated by TFT T2and OLED D1is equal to VDDtimes the current IDWhile the voltage supply VDDis divided between TFT T2and OLED D1, the same current IDflows through both. Therefore, the power P is divided between TFT T2and OLED D1in proportion to the voltage VDDbeing divided between them.

Before any current is supplied to OLED D1by TFT T2, the source S of TFT T2is at ground state causing the voltage VDDto fall almost entirely across TFT T2. As current IDincreases in OLED D1, the voltage VDacross TFT T2decreases, while the sum of the voltage across OLED D1and voltage VDequals VDD. A problem arises because OLED D1is a load on TFT T2, which load is changing during operation, as every level of luminance from OLED D1requires a specific current ID, and thus, represents a different load to TFT T2. In order to faithfully convert data voltage Vdatato a specified current IDand a specified luminance of OLED D1corresponding to Vdata, changes in the load of TFT T2due to changes in the luminance of OLED D1should not cause changes in current IDoutput from TFT T2. That is, TFT T2should act as a current source and not change current output as the load changes. In order for TFT T2to act as a current source, voltage VDacross TFT T2must bias TFT T2in the saturation mode. As shown inFIG. 3, the saturation mode corresponds to the flat part of each IDversus VDcurve, while the steep slope leading up to the flat part corresponds to the unsaturated mode.

In the saturation mode, IDdepends almost entirely on VG, which is the voltage on gate G of TFT T2, as expressed in Eq. 1:

ID=μ·ε0·εr·w2·d·1⁢(VG-Vth)2(1)
where μ,ε0, εr, W, l, d, and Vthare parameters associated with TFT T2. with μ being the effective electron mobility, ε0being the permittivity of free space, εrbeing the dielectric constant of the gate dielectric, w being the TFT channel width, l being the TFT channel length, d being the gate dielectric thickness, and Vthbeing the threshold voltage.

For a TFT to be in the saturation mode, VDmust be greater than VG−Vth. Thus, for a specified current ID

Typically, 1 μA of current is sufficient to give bright emissions from an OLED pixel. Following are examples of TFT parameters:Vth≈1 Vμ≈0.75 cm2/V·secεr≈4w≈25 μm1≈5 μmd≈0.18 μm
from which it is estimated that:
VD<VG−Vth≈5.206V, for ID=1 μA.

This means that the minimum VDrequired to put TFT T2in saturation is about 5.2V for a drain current of 1 μA, or that at ID=1 μA, the power dissipated by TFT T2is about 5.2 microwatts. This estimate is for an ideal situation. In practice, a larger voltage across the OLED is needed to pass 1 μA of current through the OLED as the OLED ages. For example, when an OLED is new, only about 4 V across the OLED is required to pass 1 μA of current, but as it ages this voltage may increase to as high as 6 volts. This means that 2 extra volts should typically be added to VDDto ensure that TFT T2stays in saturation over the lifetime of the display. In addition, if higher OLED luminance is desired, higher VDwill be required to ensure saturation. Furthermore, even higher VDmay be required to keep TFT T2in saturation due to threshold voltage drift, which often happens with amorphous silicon TFTs. Thus, the total required voltage VDis about 5.2 V for an ideal case when 1 μA of drain current is generated in the saturation mode, plus about 2 volts for threshold voltage drift and about an additional 2 volts for OLED aging and maximum OLED brightness. This means that VDDneeds to be as high as about 13.2 volts. This also means that when the display is new, for 1 microampere of current through the OLED D1, there will be about 4 volts across the OLED and about 4 microwattts of power dissipation by the OLED, while about 9.2 volts of voltage is across TFT T2and power dissipation by the TFT is about 9.2 microwatts, which is more than twice the power dissipation of the OLED itself.

Thus, there is a need for a display that provides good control of pixel luminance without excessive power dissipation by the power TFTs.

SUMMARY OF THE INVENTION

The embodiments of the present invention provide a display having a plurality of pixels. Each pixel comprises a light-emitting device configured to emit light or photons in response to a current flowing through the light-emitting device. The luminance of the light-emitting device depends on the current through the light-emitting device. Each pixel further comprises a transistor coupled to the light-emitting device and configured to provide the current through the light-emitting device, the current increasing with a ramp voltage applied to a control terminal of the transistor, and a switching device configured to switch off in response to the luminance of the light-emitting device having reached a specified level, thereby disconnecting the ramp voltage from the transistor and locking the brightness at the specified level. The switching device is further configured to stay off thereby allowing the luminance of the light-emitting device to be kept at the specified level until the pixel is rewritten in the next frame.

In some embodiments, the transistor and the light-emitting device are serially coupled with each other between a variable voltage source and ground. The variable voltage source is configured to output a voltage that changes as the display ages. The voltage output from the variable voltage source changes based on a statistical evaluation of the changes in ramp voltages required to cause the light from the light-emitting devices to reach specified levels in brightness in some or all of the pixels in the display.

The embodiments of the present invention also provide a method for controlling the brightness of a pixel in a display. The method comprises switching on a switching device by applying a first control voltage to a first control terminal and a second control voltage to a second control terminal of the switching device, and applying a ramp voltage through the switching device to a gate of a transistor serially coupled with the light-emitting device thereby causing light emitted from the light-emitting device to increase in brightness with the ramp voltage. The light from the light-emitting device illuminates an optical sensor thereby causing an electrical parameter associated with the optical sensor to change as the light changes in brightness, and the second control voltage is dependent on the electrical parameter and changes to a different value in response to the luminance of the light-emitting device having reached a specified brightness for the pixel, thereby switching off the switching device.

In some embodiments, the transistor and the light-emitting device are serially coupled with each other between a variable voltage source and ground, and the method further comprises varying a voltage output from the variable voltage source as the display ages. The voltage output is varied by recording a value of ramp voltage required to cause the light-emitting device in each pixel in the display to reach the specified level of brightness for the pixel, and computing a statistical measure from the changes in the recorded values for some or all of the pixels in the display to determine when and how much to change the voltage output.

The embodiments described herein provide significant power savings by allowing a power TFT, that supplies currents to a light-emitting device such as an OLED in a pixel of a display, to operation in the unsaturated regions associated with its current-voltage characteristics, because the brightness of the light-emitting device according to embodiments of the present invention does not depend on a current-voltage relationship of the power TFT, but on the pixel brightness itself. Further power savings are achieved in embodiments using variable power supplies.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention provide low-power circuits for emissive displays and methods of operating the same. The embodiments described herein save power consumed by power TFTs that supply currents to light-emitting devices in a display by allowing the power TFTs to operate in the unsaturated region.

FIG. 4Ais a block diagram of a portion of an exemplary circuit100for a display, such as a flat panel display, according to one embodiment of the present invention. As shown inFIG. 4A, display circuit100comprises a light emission source110, an emission driver120configured to vary the luminance of the emission source110, an optical sensor130positioned to receive a portion of the light emitted from emission source110and having an associated electrical parameter dependent on the received light, a control unit140configured to control the driver120based on the changes in the electrical parameter of the sensor130, and a data input unit150configured to provide a signal corresponding to a desired brightness level for the emission source110to the control unit140. Optionally, display circuit100may further comprise a power adjustment unit160configured to adjust the amount of power produced by a variable power supply170, which is the source of power for the emission source110, to account for variations in the emission source and other circuit elements in display circuit100.

Sensor130may comprise any sensor material having a measurable property, such as a resistance, capacitance, inductance, etc., dependent on received emissions. In one example, sensor130comprises a photosensitive resistor whose resistance varies with an incident photon flux. As another example, the sensor130comprises a calibrated photon flux integrator, such as the one disclosed in commonly assigned U.S. patent application Ser. No. 11/016,372 entitled “Active-Matrix Display and Pixel Structure for Feedback Stabilized Flat Panel Display,” filed on Dec. 17, 2004, which is incorporated herein by reference in its entirety. Sensor130may also or alternatively comprise one or more of other radiation-sensitive sensors including, but not limited to, optical diodes and/or optical transistors. Thus, sensor130may comprise at least one type of material that has one or more electrical properties changing according to the intensity of radiation falling or impinging on a surface of the material. Such materials include but are not limited to amorphous silicon (a-Si), cadmium selenide (CdSe), silicon (Si), and Selenium (Se). Sensor130may also comprise other circuit elements such as an isolation transistor for preventing cross talk among a plurality of sensors130in an active matrix display, as discussed in more detail below.

The control unit140may be implemented in hardware, software, or a combination thereof. In one embodiment, the control unit140is implemented using a voltage comparator. Other comparison circuitry or software may also or alternatively be used. The driver120may include any hardware, software, firmware, or combinations thereof suitable for providing a drive signal to emission source110. Driver120may be integrated with a display substrate on which the emission source110is formed, or it may be separate from the display substrate. In some embodiments, portions of driver120are formed on the display substrate.

During operation of display circuit100, data input150receives image voltage data corresponding to a desired brightness of the light from emission source110and converts the image voltage data to a reference voltage for use by the control unit140. The pixel driver120is configured to vary the light emission from the emission source110until the electrical parameter in sensor130reaches a certain value corresponding to the reference voltage, at which point, control unit140couples a control signal to driver120to stop the variation of the light emission. Driver120also comprises mechanisms for maintaining the light emission from emission source110at the desired brightness after the variation of the light emission is stopped. Optionally, while the light emission from the emission source110is varied, an electrical measure in the power adjustment unit is also varied accordingly, and the control signal from the control unit140is also coupled to the power adjustment unit160to stop the variation of the electrical measure. Based on the value at which the electrical measure is stopped, the power adjustment unit160determines whether to adjust the variable power supply170and how much adjustment needs to be done using, for example, a statistical technique, as explained in more detail below.

FIG. 5illustrates one implementation of the display circuit100in the embodiments ofFIG. 4A. As shown inFIG. 5, display circuit100comprises a transistor512and a light-emitting device514as the light emission source110. Display circuit100further comprises a switching device522and a capacitor524as part of the driver120, an optical sensor (OS)530and an optional isolation device532as sensor130, and a voltage divider resistor542and a comparator544as part of the control unit140. The OS530is coupled to a line selector output voltage VOS1and the voltage divider resistor542is coupled with OS530between VOS1and ground. The comparator544has a first input P1coupled to the data input unit, a second input P2coupled to a circuit node546between the OS530and the voltage divider resistor542, and an output P3. The switching device522has a first control terminal G1acoupled to VOS1, a second control terminal G1bcoupled to the output P3of comparator544, an input DR1coupled to a ramp voltage output VR, and an output S2coupled to a control terminal G2of transistor512. The capacitor524is coupled between the control terminal G2and a circuit node S2between transistor512and light-emitting device514. The capacitor524may alternatively be coupled between control terminal G2of transistor512and ground.

Each OS530can be any suitable sensor having a measurable property, such as a resistance, capacitance, inductance, or the like parameter, property, or characteristic, dependent on received emissions. An example of OS230is a photosensitive resistor whose resistance varies with an incident photon flux. As another example, each OS230is a calibrated photon flux integrator, such as the one disclosed in commonly assigned U.S. patent application Ser. No. 11/016,372 entitled “Active-Matrix Display and Pixel Structure for Feedback Stabilized Flat Panel Display,” filed on Dec. 17, 2004, which application is incorporated herein by reference in its entirety. Thus, each OS230may include at least one type of material that has one or more electrical properties changing according to the intensity of radiation falling or impinging on a surface of the material. Such materials include but are not limited to amorphous silicon (a-Si), cadmium selenide (CdSe), silicon (Si), and Selenium (Se). Other radiation-sensitive sensors may also or alternatively be used including, but not limited to, optical diodes, and/or optical transistors.

Isolation device532such as an isolation transistor may be provided to isolate the optical sensors530. Isolation transistor532can be any type of transistor having first and second terminals and a control terminal, with conductivity between the first and second terminals controllable by a control voltage applied to the control terminal. In one embodiment, isolation transistor532is a TFT with the first terminal being a drain DR3, the second terminal being a source S3, and the control terminal being a gate G3. The isolation transistor532is serially coupled with OS530between VOS1, and ground, with the control terminal of G3connected to VOS1, while the first and second terminals are connected to resistor542and OS530, respectively, or to OS530and VOS1, respectively. In the following discussion, OS530and isolation transistor532may together be referred to as sensor130.

Light-emitting device514may generally be any light-emitting device known in the art that produces radiation such as light emissions in response to an electrical measure such as an electrical current through the device or an electrical voltage across the device. Examples of light-emitting device514include but are not limited to light emitting diodes (LED) and organic light emitting diodes (OLED) that emit light at any wavelength or a plurality of wavelengths. Other light-emitting devices may be used including electroluminescent cells, inorganic light emitting diodes, and those used in vacuum florescent displays, field emission displays and plasma displays. In one embodiment, an OLED is used as the light-emitting device514.

Light-emitting device514is sometimes referred to as an OLED514hereafter. But it will be appreciated that the invention is not limited to using an OLED as the light-emitting device514. Furthermore, although the invention is sometimes described relative to a flat panel display, it will be appreciated that many aspects of the embodiments described herein are applicable to a display that is not flat or built as a panel.

Transistor512can be any type of transistor having a first terminal, a second terminal, and a control terminal, with the current between the first and second terminals dependent on a control voltage applied to the control terminal. In one embodiment, transistor512is a TFT with the first terminal being a drain D2, the second terminal being a source S2, and the control terminal being a gate G2. Transistor512and light-emitting device514are serially coupled between a power supply VDDand ground, with the first terminal of transistor512connected to VDD, the second terminal of transistor512connected to the light-emitting device514, and the control terminal connected to ramp voltage output VR through switching device522.

In one embodiment, switching device522is a double-gated TFT, that is, a TFT with a single channel but two gates G1aand G1b. The double gates act like an AND function in logic, because for the TFT522to conduct, logic highs need to be simultaneously applied to both gates. Although a double-gated TFT is preferred, any switching device implementing the AND function in logic is suitable for use as the switching device522. For example, two serially coupled TFTs or other types of transistors may be used as the switching device522. Use of a double-gated TFT or other device implementing the AND function in logic as the switching device522helps to reduce cross talk between pixels, as explained in more detail below. If cross talk is not a concern or other means are used to reduce or eliminate the cross talk, gate G1aand its connection to VOS1is not required, and a TFT with a single control gate connected to the output P3of comparator544may be used as the switching device522, as shown inFIG. 7.

In one embodiment of the present invention, display100comprises a plurality of pixels115each having a driver120and a emission source120, and a plurality of sensors130each corresponding to a pixel, as shown inFIG. 4B. Display100further comprises a column control circuit44and a row control circuit46. Each pixel115is coupled to the column control circuit44via a column line55and to the row control circuit46via a row line56. Each sensor130is coupled to the row control circuit46via a sensor row line70and to the column control circuit44via a sensor column line71. In one embodiment, at least parts of the control unit140, the data input unit150and the power adjustment unit160are comprised in the column control circuit44.

In one embodiment, each sensor130is associated with a respective pixel115and is positioned to receive a portion of the light emitted from the pixel. Pixels are generally square, as shown inFIG. 4B, but can be any shape such as rectangular, round, oval, hexagonal, polygonal, or any other shape. If display11is a color display, pixel33can also be subpixels organized in groups, each group corresponding to a pixel. The subpixels in a group should include a number (e.g., 3) of subpixels each occupying a portion of the area designated for the corresponding pixel. For example, if each pixel is in the shape of a square, the subpixels are generally as high as the pixel, but only a fraction (e.g., ⅓) of the width of the square. Subpixels may be identically sized or shaped, or they may have different sizes and shapes. Each subpixel may include the same circuit elements as pixel115and the sub-pixels in a display can be interconnected with each other and to the column and row control circuits44and46just as the pixels115shown inFIG. 4B. In a color display, a sensor130is associated with each subpixel. In the following discussions, the reference of a pixel can mean both a pixel or subpixel.

The row control circuit46is configured to activate a selected row of sensors60by, for example, raising a voltage on a selected sensor row line70, which couples the selected row of sensors to the row control circuit46. The column control circuit44is configured to detect changes in the electrical parameters associated with the selected row of sensors and to control the luminance of the corresponding row of pixels115based on the changes in the electrical parameters. This way, the luminance of each pixel can be controlled at a specified level based on feedbacks from the sensors130. In other embodiments, the sensors130may be used for purposes other than or in addition to feedback control of the pixel luminance, and there may be more or less sensors130than the pixels or subpixels115in a display.

The sensors and the pixels can be formed on a same substrate, or, they can be formed on different substrates. In one embodiment, display100comprises a sensor component100and a display component110, as illustrated inFIG. 4C. The display component110comprises pixels115, the column control circuit44, the row control circuit46, the column lines55, and the row lines56formed on a first substrate112, while the sensor component100comprises the sensors130, the sensor row lines70, and the sensor column lines71formed on a second substrate102. The sensor component100may also comprise color filter elements20,30, and40when the sensors130are integrated with a color filter for the display, as described in related patent application Ser. No. 10/872,344.

When the two components are put together to form display11, electrical contact pads or pins114on display component110are mated with electrical contact pads104on filter/sensor plate100, as indicated by the dotted line aa, in order to connect the sensor row lines70to the row control circuit46. Likewise, electrical contact pads or pins116on display component110are mated with electrical contact pads106on filter/sensor plate100, as indicated by the dotted line bb, in order to connect the sensor column lines71to the column control circuit44. It is understood that display component110can be one of any type of displays including but not limited to LCDs, electroluminescent displays, plasma displays, LEDs, OLED based displays, micro electrical mechanical systems (MEMS) based displays, such as the Digital Light projectors, and the like. For ease of illustration, only one set of column lines55and one set of row lines56for the display component100are shown inFIG. 1B. In practice, there may be more than one set of column lines and/or more than one set of row lines associated with the display component110. For example, in an OLED-based active matrix emissive display, as discussed below, display component110may comprise another set of row lines connecting each pixel33to a respective one of the contact pads114.

FIG. 6illustrates one implementation of one embodiment of display100. As shown inFIG. 6, display100comprises a plurality of pixels500arranged in rows and columns, with pixels PIX1,1, PIX1,2, etc., in row1, pixels PIX2,1, PIX2,2, etc., in row2, and so on for the other rows in the display. Each pixel500comprises a transistor512, a light-emitting device514, a switching device522, and a capacitor524.FIG. 6also shows a sensor array comprising a plurality of sensors arranged in rows and columns, each corresponding to a pixel and each comprising an optical sensor OS530and an isolation transistor532.

Still referring toFIG. 6, display100further comprises ramp selector (RS)610configured to receive a ramp voltage VR and to select one of row lines, VR1, VR2, etc., to output the ramp voltage VR. Each of lines VR1, VR2, etc., is connected to drain D1of switching device522in each of a corresponding row of pixels500. Circuit100further comprises a line selector (VOSS) configured to receive a line select voltage Vos and to select one of sensor row lines, VOS1, VOS2, etc., to output the line select voltage VOS. Each of lines VOS1, VOS2, etc., is connected to the optical sensors530and to gate G1aof switching device522in each of a corresponding row of pixels500. RS610and VosS620are part of the row control circuit46and can be implemented using shift registers.

Each sensor comprising the OS530and the TFT532may be part of a pixel in the display and formed on a same substrate the pixels are formed. Alternatively, the sensors are fabricated on a different substrate from the substrate on which the pixels are formed, as shown inFIG. 4C. In this case, another set or row lines (not shown) are provided to allow gate G1ato be connected to contact pads114and thus to the sensor row lines Vos1, Vos2, etc., when the two substrates are mated together.

FIG. 6also shows that display comprises a plurality of comparators544and resistors522each being associated with a column of pixels500.FIG. 6further shows a block diagram of data input unit150, which comprises an analog to digital converter (A/D)630configured to convert a received image voltage data to a corresponding digital value, an optional grayscale level calculator (GL)631coupled to the A/D630and configured to generate a grayscale level corresponding to the digital value, a row and column tracker unit (RCNT)632configured to generate a line number and column number for the image voltage data, a calibration look-up table addresser (LA)633coupled to the RCNT632and configured to output an address in the display circuit100corresponding to the line number and column number, and a first look-up table (LUT1)635coupled to the GL631and the LA633. Data input unit150further comprises a digital to analog converter (DAC)636coupled to the LUT1635and a first line buffer (LB1)637coupled to the DAC636. In one embodiment, comparators544, resistors522, and at least part of data input unit150are included in the column control circuit44.

In one embodiment, LUT1635stores calibration data obtained during a calibration process for calibrating against a light source having a known luminance each optical sensor in the display circuit100. Related patent applications Ser. No. 10/872,344 and U.S. patent application Ser. No. 10/841,198, supra, describes an exemplary calibration process, which description is incorporated herein by reference. The calibration process results in a voltage divider voltage level at circuit node546in each pixel for each grayscale level. As a non-limiting example, an 8-bit grayscale has 0–256 levels of luminance with the 255thlevel being at a chosen level, such as 300 nits for a Television screen. The luminance level for each of the remaining 255 levels is assigned according to the logarithmic response of the human eye. The zero level corresponds to no emission. Each value of brightness will produce a specific voltage on the circuit node546between optical sensor OS530and voltage divider resistor542. These voltage values are stored in lookup table LUT1as the calibration data. Thus, based on the address provided by LA633and the gray scale level provided by GL631, the LUT1635generates a calibrated voltage from the stored calibration data and provides the calibrated voltage to DAC636, which converts the calibrated voltage into an analog voltage value and downloads the analog voltage value to LB1637. LB1637provides the analog voltage value as a reference voltage to input P1of comparator544associated with the column corresponding to the address.

Initially, all of lines VOS1, VOS2, etc., are at zero or even a negative voltage depending on specific application. So the switching device522in each pixel500is off no matter what the output P3of the comparator544is. Also, isolation transistor532in each pixel is off so that no sensor is connected to P2of the comparator544. Also note that the voltage on P2of voltage comparator544is zero (or at ground) because there is no current flowing through the resistor542, which is connected to ground. In one embodiment, comparator544is a voltage comparator that compares the voltage levels at its two inputs P1and P2and generates at its output P3a positive supply rail (e.g., +10 volts) when P1is larger than P2and a negative supply rail (e.g., 0 volts) when P1is equal of less than P2. The positive supply rail corresponds to a logic high for the switching device522while negative supply rail corresponds to a logic low for the switching device522. Initially, before OLED514emits light, OS530has a maximum resistance to current flow; and voltage on input pin P2of VC544is minimum because the resistance R of voltage divider resistor542is small compared to the resistance of OS530. So, as the reference voltages for the first row (row1), which includes pixels PIX1,1, PIX1,2, etc., are written to line buffer657, all of the gates G1bin the pixels are opened because input P1in each comparator544is supplied with a reference voltage while input P2in each comparator544is grounded, causing comparator544to generate the positive supply rail at output P3.

Image data voltages for row1of the display100are sent to the A/D converter630serially and each is converted to a reference voltage and stored in LB1637until LB1stores the reference voltages for every pixel in the row. At about the same time, shift register VOS620sends the VOSvoltage (e.g., +10 volts) to line Vos1, turning on gate G1bof each switching device524in row1, and thus, the switching devices522themselves (since gate G1ais already on). The voltage VOSon line Vos1is also applied to OS530and to the gate G3of transistor532in each of the first row of pixels, causing transistor532to conduct and current to flow through OS530. Also at about the same time, shift register RS610sends the ramp voltage VR (e.g., from 0 to 10 volts) to line VR1, which ramp voltage is applied to storage capacitor524and to the gate G2of transistor512in each pixel in row1because switching device522is conducting. As the voltage on line VR1is ramped up, the capacitor524is increasingly charged, the current through transistor512and OLED514in each of the first row of pixels increases, and the light emission from the OLED also increases. The increasing light emission from the OLED514in each pixel in row1falls on OS530associated with the pixel and causes the resistance associated with the OS530to decrease, and thus, the voltage across resistor542or the voltage at input P2of comparator544to increase.

This continues in each pixel in row1as the OLED514in the pixel ramps up in luminance with the increase of ramp voltage VR until the OLED514reaches the desired luminance for the pixel and the voltage at input P2is equal to the reference voltage at input P1of comparator544. In response, output P3of comparator544changes from the positive supply rail to the negative supply rail, turning off gate G1bof switching device522in the pixel, and thus, the switching device itself. With the switching device522turned off, further increase in VR is not applied to gate G of transistor512in the pixel, and the voltage between gate G2and the second terminal S2of transistor512is held constant by capacitor524in the pixel. Therefore, the emission level from OLED514in the pixel is frozen or fixed at the desired level as determined by the calibrated reference voltage placed on pin, P1of the voltage comparator544associated with the pixel.

The duration of time that the ramp voltage VR1takes to increase to its full value is called the line address time. In a display having 500 lines and running at 60 frames per second, the line address time is approximately 33 micro seconds or shorter. Therefore, all the pixels in the first row are at their respective desired emission levels by the end of the line address time. And this completes the writing of row1in the display100. After row1is written, both horizontal shift registers, VOSS620and RS610turn off lines VR1and Vos1, respectively, causing switching device522and isolation transistor532to be turned off, thereby, locking the voltage on the storage capacitor524and isolating the optical sensors530in row1from the voltage comparators544associated with each column. When this happens, the voltage on pin P2of each comparator544goes to ground as no current flows in resistor R, causing the output P3of the voltage comparator544to go back to the positive supply rail, turning gate G1bof switching device522in each related pixel back on, ready for the writing of the second row of pixels in display100.

During the writing of the second row, image data associated with the second row is supplied to A/D630, ramp selector RS610selects line VR2to output ramp voltage VR, line selector VOSS620selects line VOS2to output line select voltage Vos, and the previous operation is repeated for the second row of pixels until they are turned on. Ramp selector RS610and VOSS620move to row three and so on until all rows in the display have been turned on, and then the frame repeats. In the embodiments depicted byFIG. 6, each switching device522has double gates, Gate G1aand Gate G1b, and gate G1aof each switching device522in row1is held by line VOS1. So, during the writing of subsequent rows, while gate G1bmay conduct, the switching devices522in row1are kept off because VOS1is not selected. Thus, capacitor524in each pixel in row1is kept disconnected from the capacitors524in the other pixels in row1. This eliminates cross talk between capacitors524in different pixels in the row that has just be written, so that each pixel in the row continues to output the desired emission level during the writing of subsequent rows.

Because the luminance of each pixel500in the display100does not depend on a voltage-current relationship associated with transistor512, but is controlled by a specified image grayscale level and a feedback of the pixel luminance itself, the embodiments described above allow transistor512to operate in the unsaturated region, and thus, save power for the operation of display100. Using the exemplary OLED and TFT parameters discussed in the background section, a VDDas low as 9 volts may be sufficient to operate display100because transistor TFT512does not need to operate in saturation mode. Out of the 9 volts, about 6 volts are used to produce 1 μA of current in OLED514at maximum aging of the OLED514, about 2 additional volts are required for the threshold voltage drift over the life of the display, and a minimum of about 1 volt is used as the source/drain voltage across transistor512. Thus, the power dissipation of power TFT512is now about about 5 microwatts instead of about 9.2 microwatts as required by conventional power TFTs operation in saturation mode. This is a significant power savings of about 46% for the power TFTs.

Using the following parameters associated with a typical power TFT:Vth≈1 Vμ≈0.75 cm2/V·secεr≈4w≈25 μm1≈5 μmd≈0.18 μm
where μ is the effective electron mobility, ε0being the permittivity of free space, εris the dielectric constant of the gate dielectric, w is the TFT channel width, 1 is the TFT channel length, d is the gate dielectric thickness, and Vthis the threshold voltage, it can be estimated that, the maximum gate voltage VG2for a typical power TFT512to operate in the unsaturated region at 1 μA current should be about 15 volts. Thus, the maximum value in ramp voltage VR should be set above 15 V. The required gate voltage for power TFT512is higher when TFT512is operating in the unsaturated region, but this does not create a significant power dissipation issue.

As described above, additional voltages or voltage range capacity may advantageously be included in the power supply VDDto allow for degradation in the efficiency of the OLED D1and for threshold voltage drift in power TFT512. These additional voltages may amount to as much as three to four volts, which results in significant power dissipation. Further savings in power can be attained by using a variable power supply, which allows the voltage VDDto be set low initially and be increased as pixels age, or threshold voltage drifts, or both.

FIG. 7illustrates the power adjustment unit160in display100according to one embodiment of the present invention. As shown inFIG. 7, power adjustment unit160comprises a plurality of transistors710each associated with a column of pixels and a plurality of capacitors712each coupled to a respective one of the transistors710. Each transistor710can be any transistor having first and second terminals and a control terminal, with the conductivity between first and second terminals controllable by a voltage applied to the control terminal. In one embodiment, each transistor710is a TFT with the first terminal being the drain D4, the second terminal being the source D4, and the control terminal being the gate G4of the TFT. Each capacitor712is coupled between a source S4of a respective one of the TFTs710and ground. The gate G4of each TFT710is connected to output P3of a respective one of the voltage comparators544, and the drain D4of the TFT is connected to the ramp voltage output VR.

Power adjustment unit160further comprises a line buffer (LB2)720, a ramp logic block (RL)730, a storage medium740storing therein a look-up table (LUT2), and a storage medium750storing therein a differential ramp voltage table (DRV). During operation, every time a ramp voltage value is locked on the storage capacitors524in a pixel in a row being addressed, the same voltage is locked on the storage capacitors712at the head of the column including the pixel. These locked ramp voltages is up loaded to LB2720.

The first time the display is used, the set of ramp voltages loaded in LB2720represent the initial and new state of the display before any pixel degradation or TFT threshold voltage drifts have occurred. This initial set of ramp voltages is stored in look up table LU2740. The initial ramp voltage set is guided to look up table LUT2740by Ramp logic RL730. During subsequent use of the display, the ramp voltages loaded in LB2are compared to the initial set of ramp voltages stored in lookup table LUT2and the difference is stored in DRV750. As the display ages, higher gate voltage at the power TFT512would be required to produce the same current through OLED514or the same brightness of OLED514. Therefore, the set of values in DRV750represents the aging of the display and these values should increase with the continued usage of display100.

As the differential ramp voltages increase, voltage VDDoutput from the variable power supply170is also increased using a known technique to compensate for the pixel aging and power TFT threshold voltage drifts. There are many ways to determine when to increase VDDand how much increase should be made. As a non-limiting example, VDDcan be increased by a certain increment (e.g., 0.25 volts) when a certain percentage (e.g., 20%) of the differential ramp voltages stored in DRV750have each changed by more than a certain amount (e.g., 0.25 volts). As another example, VDDcan be increased by a certain increment (e.g., 0.25 volts) when an average of the differential ramp voltages stored in DRV750has increased by a certain amount (e.g., 0.25 volts).