Stereoscopic image display and driving method thereof

A stereoscopic image display and a method of driving the same are disclosed. The stereoscopic image display includes shutter glasses including a left eye shutter and a right eye shutter that are alternately turned on and off in synchronization with a display device, a backlight unit that irradiates light to the display device and is periodically turned on and off, a controller that divides a first frame period into a first address period and a first vertical blanking period, divides a second frame period into a second address period and a second vertical blanking period, and controls so that durations of the first vertical blanking period and the second vertical blanking period are different from each other, and a driving circuit that supplies data to the display device during the first and second address periods under the control of the controller.

This application claims the benefit of Korean Patent Application No. 10-2009-0107047 filed on Nov. 6, 2009, the entire contents of which is incorporated herein by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate to a stereoscopic image display and a method of driving the same.

2. Discussion of the Related Art

A stereoscopic image display is divided into a display using a stereoscopic technique and a display using an autostereoscopic technique.

The stereoscopic technique, which uses a parallax image of left and right eyes of a user with a high stereoscopic effect, includes a glass method and a non-glass method which have been put to practical use. In the glass method, a left and right parallax image is displayed on a direct-view display or a projector through a change in a polarization direction of the left and right parallax image or in a time-division manner, and a stereoscopic image is implemented using polarization glasses or liquid crystal shutter glasses. In the non-glass method, generally, an optical plate such as a parallax barrier and a lenticular lens separates an optical axis of the left and right parallax image, and a stereoscopic image is implemented.

U.S. Pat. No. 5,821,989 and US Publication No. 20070229395A1 are known to disclose an example of the glass type stereoscopic image display.

FIGS. 1 and 2schematically illustrate a glass type stereoscopic image display. InFIGS. 1 and 2, a black region of a liquid crystal shutter glasses ST represents a shutter that blocks light traveling toward an observer (i.e., viewer), and a white region of the liquid crystal shutter glasses ST represents a shutter allowing transmission of light toward the observer.

FIG. 1illustrates a time-division operation of left and right images when an impulse type display device DIS1is selected in the glass type stereoscopic image display. In the impulse type display device DIS1such as a cathode ray tube (CRT), immediately after data is completely written in a scanning direction, data of each pixel is erased.

In the stereoscopic image display illustrated inFIG. 1, during odd-numbered frame periods, a left eye shutter of the liquid crystal shutter glasses ST is open, and left eye image data RGBLis sequentially scanned on the impulse type display device DIS1. During even-numbered frame periods, a right eye shutter of the liquid crystal shutter glasses ST is open and right eye image data RGBLis sequentially scanned on the impulse type display device DIS1. Accordingly, the observer can view only a left eye image during the odd-numbered frame periods and a right eye image during the even-numbered periods, thereby feeling stereoscopy.

FIG. 2illustrates a time-division operation of left and right images when a hold type display device DIS2is selected in the glass type stereoscopic image display. In the hold type display device DIS2such as a liquid crystal display (LCD), data written in pixels is hold until such time as data is written on a first line during a next frame period following a response completion time point after the data is written on the entire pixels because of to response time delay characteristics.

In the stereoscopic image display illustrated inFIG. 2, during an nth frame period, where n is a positive integer, the left eye shutter of the liquid crystal shutter glasses ST is open and left eye image data RGBL(Fn) is sequentially scanned on the hold type display device DIS2. While the left eye shutter of the liquid crystal shutter glasses ST is open, some pixels, to which the left eye image data RGBL(Fn) of the nth frame have not been written yet in the hold type display device DIS2, hold right eye image data RGBR(Fn−1) which had been already charged in an (n−1)th frame period. Accordingly, the observer can view an image of the right eye image data RGBR(Fn−1) of the (n−1)th frame as well as an image of the left eye image data RGBL(Fn) of the nth frame with his left eye during the nth frame.

In the stereoscopic image display illustrated inFIG. 2, during (n+1)th frame period, the right eye shutter of the liquid crystal shutter glasses ST is open and right eye image data RGBR(Fn+1) are sequentially scanned on the hold type display device DIS2. While the right eye shutter of the liquid crystal shutter glasses ST is open, some pixels, to which the right eye image data RGBR(Fn+1) have not been written yet on the hold type display device DIS2, hold left eye image data RGBL(Fn) which had been already charged in nth frame. Accordingly, the observer can view the image of the left eye image data RGBL(Fn) of the nth frame as well as an image of the right eye image data RGBR(Fn+1) of the (n+1)th frame with his right eye during the (n+1)th frame.

As can be seen fromFIG. 2, the observer can feel a pseudo-stereoscopic vision at a time when the left eye image is changed to the right eye image or at a time when the right eye image is changed to the left eye image because of crosstalk between the left and right eye images generated in the hold type display device DISP2.

Thus, in order to improve the degradation of picture quality due to the response time delay of the stereoscopic image display as shown inFIG. 2, US Publication NO. 20070229395A1 disclosed a technique of addressing data more quickly than the related art on a liquid crystal display panel and extending a vertical blanking period. Also, this publication proposed a method of opening liquid crystal shutter glasses ST during a time period obtained by subtracting a liquid crystal response time from the extended vertical blanking period. In proposed method, the vertical blanking period without data is lengthened and an opening duration of the liquid crystal shutter glasses is reduced, thereby making an observer feel flickering. In addition, constructive interference occurs between light that transmits through the liquid crystal shutter and ambient light according to a correlation between an ON/OFF period of the liquid crystal shutter and that of the ambient light such as a fluorescent lamp, making the observer feel flicking more severely.

SUMMARY OF THE INVENTION

Exemplary embodiments of the invention provide a stereoscopic image display and a method of driving the same capable of preventing crosstalk between left and right eye images generated when a hold type display device is used.

In one aspect, there is a stereoscopic image display comprising a display device that displays a stereoscopic image, shutter glasses including a left eye shutter and a right eye shutter that are alternately turned on and off in synchronization with the display device, a backlight unit that irradiates light to the display device and is periodically turned on and off, a controller that divides a first frame period into a first address period and a first vertical blanking period, divides a second frame period into a second address period and a second vertical blanking period, and controls so that a duration of the first vertical blanking period and a duration of the second vertical blanking period are different from each other, and a driving circuit that supplies data to the display device during the first and second address periods under the control of the controller.

The duration of the second vertical blanking period may be longer than the duration of the first vertical blanking period.

The duration of the first vertical blanking period may be longer than the duration of the second vertical blanking period.

In another aspect, there is a method of driving a stereoscopic image display comprising dividing a first frame period into a first address period and a first vertical blanking period, dividing a second frame period into a second address period and a second vertical blanking period, and controlling so that a duration of the first vertical blanking period and a duration of the second vertical blanking period are different from each other, supplying data to a display device during the first and second address periods, alternately turning on and off a left eye shutter and a right eye shutter of shutter glasses in synchronization with the display device, and periodically turning on and off a backlight unit for irradiating light to the display device.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The invention will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the inventions are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals designate like elements throughout the specification. In the following description, if it is decided that the detailed description of known function or configuration related to the invention makes the subject matter of the invention unclear, the detailed description is omitted.

Names of elements used in the following description are selected in consideration of facility of specification preparation. Thus, the names of the elements may be different from names of elements used in a real product.

Reference will now be made in detail embodiments of the invention examples of which are illustrated in the accompanying drawings.

As shown inFIG. 3, a stereoscopic image display according to an exemplary embodiment of the invention includes a display panel15, a backlight unit16, liquid crystal shutter glasses18, a controller11, a display panel driving circuit12, a backlight driving circuit13, a liquid crystal shutter control signal transmission unit14, and a liquid crystal shutter control signal reception unit17.

The display panel15alternately displays left eye image data RGBLand right eye image data RGBRunder the control of the controller11. The display panel15may display black data between the left eye image data RGBLand the right eye image data RGBRunder the control of the controller11. The display panel15may be selected as a hold type display device requiring a backlight unit. The hold type display device may be selected as a backlit liquid crystal display panel modulating light from the backlight unit16.

The backlit liquid crystal display panel includes a thin film transistor (TFT) substrate and a color filter substrate. A liquid crystal layer is formed between the TFT substrate and the color filter substrate. On the TFT substrate, data lines and gate lines (or scan lines) are formed to cross each other on a lower glass substrate, and liquid crystal cells are disposed in a matrix form in cell areas defined by the data lines and the gate lines. TFTs formed at crossings of the data lines and the gate lines transfer a data voltage supplied via the data lines to pixel electrodes of the liquid crystal cells in response to scan pulses from the gate lines. To this end, a gate electrode of each TFT is connected to the gate line, and a source electrode of each TFT is connected to the data line. A drain electrode of each TFT is connected to the pixel electrode of the liquid crystal cell. A common voltage is applied to a common electrode facing the pixel electrode. The color filter substrate includes black matrixes and color filters formed on an upper glass substrate. In a vertical field driving mode such as a twisted nematic (TN) mode and a vertical alignment (VA) mode, the common electrode is formed on the upper glass substrate. In a horizontal field driving mode such as an in-plane switching (IPS) mode and a fringe field switching (FFS) mode, the common electrode is formed along with the pixel electrodes on the lower glass substrate. Polarizing plates are respectively attached to the upper and lower glass substrates of the backlit liquid crystal display panel, and alignment layers for setting a pre-tilt angle of liquid crystals are respectively formed on the upper and lower glass substrates. A spacer is formed between the upper and lower glass substrates of the backlit liquid crystal display panel to maintain a cell gap of the liquid crystal layer. The backlit liquid crystal display panel may be implemented in any liquid crystal mode as well as the TN, VA, IPS, and FFS modes.

The display panel driving circuit12includes a data driving circuit and a gate driving circuit. The data driving circuit converts left eye image data and right eye image data input from the controller11into positive and negative gamma compensation voltages to generate positive and negative analog data voltages. The positive and negative analog data voltages output from the data driving circuit are supplied to the data lines of the display panel15. The gate driving circuit sequentially supplies a gate pulse (or a scan pulse) synchronized with the data voltage to the gate lines of the display panel15.

The backlight unit16is turned on for a predetermined period of time to irradiate light to the display panel15and is turned off for other period of time. The backlight unit16is repeatedly turned on and off periodically. The backlight unit16includes a light source turned on in accordance with driving power supplied from the backlight driving circuit13, a light guide plate (or diffusion plate), a plurality of optical sheets, and the like. The backlight unit16may be implemented as one of a direct type backlight unit and an edge type backlight unit. The light source of the backlight unit16may include one or two or more of a hot cathode fluorescent lamp (HCFL), a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), and a light emitting diode (LED).

The backlight driving circuit13generates driving power for turning on the light source. The backlight driving circuit13periodically turns on and off the driving power supplied to the light source under the control of the controller11.

The liquid crystal shutter glasses18include a left eye shutter STLand a right eye shutter STRwhich are separately controlled electrically. Each of the left eye shutter STLand the right eye shutter STRincludes a first transparent substrate, a first transparent electrode formed on the first transparent substrate, a second transparent substrate, a second transparent electrode formed on the second transparent substrate, and a liquid crystal layer interposed between the first and second transparent substrates. A reference voltage is supplied to the first transparent electrode, and ON and OFF voltages are supplied to the second transparent electrode. When the ON voltage is supplied to the second transparent electrode of each of the left and right eye shutters STLand STR, each of the left and right eye shutters STLand STRtransmits light from the display panel15. On the other hand, when the OFF voltage is supplied to the second transparent electrode of each of the left and right eye shutters STLand STR, each of the left and right eye shutters STLand STRexcludes light from the display panel15.

The liquid crystal shutter control signal transmission unit14is connected to the controller11and transmits a liquid crystal shutter control signal CSTinput from the controller11to the liquid crystal shutter control signal reception unit17through a wireline/wireless interface. The liquid crystal shutter control signal reception unit17is installed in the liquid crystal shutter glasses18and receives the liquid crystal shutter control signal CSTthrough the wireline/wireless interface. The liquid crystal shutter control signal reception unit17alternately opens and closes the left and right eye shutters STLand STRof the liquid crystal shutter glasses18in response to the liquid crystal shutter control signal CST. When the liquid crystal shutter control signal CSTof a first logic value is input to the liquid crystal shutter control signal reception unit17, the ON voltage is supplied to the second transparent electrode of the left eye shutter STLwhile the OFF voltage is supplied to the second transparent electrode of the right eye shutter STR. When the liquid crystal shutter control signal CSTof a second logic value is input to the liquid crystal shutter control signal reception unit17, the OFF voltage is supplied to the second transparent electrode of the left eye shutter STLwhile the ON voltage is supplied to the second transparent electrode of the right eye shutter STR. Accordingly, the left eye shutter STLof the liquid crystal shutter glasses18is open when the liquid crystal shutter control signal CSTof the first logic value is generated, and the right eye shutter STRof the liquid crystal shutter glasses18is open when the liquid crystal shutter control signal CSTof the second logic value is generated. In the embodiment of the invention, the first logic value may be set to a high logic voltage and the second logic value may be set to may be set to a low logic voltage.

The controller11receives timing signals and digital video data RGB from a video source (not shown). The timing signals include a vertical synchronous signal Vsync, a horizontal synchronous signal Hsync, a data enable signal DE, a dot clock CLK, and the like.

In a first exemplary embodiment of the invention, the controller11may insert a frame period, during which black data is addressed, behind each of the left and right eye image data RGBLand RGBRin accordance with a data sequence illustrated inFIGS. 5 and 6. When a falling time Tf is longer than a rising time Tr in response characteristic of the liquid crystals as shown inFIG. 7, the controller11controls so that a duration of a vertical blanking period of a frame period during which the black data is displayed is longer than a duration of a vertical blanking period of a frame period, during which the left and right eye image data RGBLand RGBRare displayed, as shown inFIG. 8.

In a second exemplary embodiment of the invention, as shown inFIGS. 9 to 11C, the controller11may continuously output left eye image data RGBL(HG) and RGBL(LG), each of which is modulated based on a different gamma characteristic, during N frame periods (where, N is an integer equal to or greater than 2), and then may continuously output right eye image data RGBR(HG) and RGBR(LG), each of which is modulated based on a different gamma characteristic, during N frame periods following the N frame periods. When the falling time Tf is longer than the rising time Tr in the response characteristic of the liquid crystals as shown inFIG. 7, the controller11controls so that a vertical blanking period of a frame period during which the left and right eye image data RGBL(LG) and RGBR(LG) of a low gamma characteristic are addressed is longer than a vertical blanking period of a frame period, during which the left and right eye image data RGBL(HG) and RGBR(HG) of a high gamma characteristic are addressed, as shown inFIG. 12.

In a third exemplary embodiment of the invention, when the rising time Tr is longer than the falling time Tf in the response characteristic of the liquid crystals as shown inFIG. 13, the controller11controls so that a vertical blanking period of a frame period, during which the left and right eye image data RGBLand RGBRare displayed is longer than a vertical blanking period of a frame period during which the black data is displayed, as shown inFIG. 14.

In a fourth exemplary embodiment of the invention, when the rising time Tr is longer than the falling time Tf in the response characteristic of the liquid crystals as shown inFIG. 13, the controller11controls so that a vertical blanking period of a frame period during which the left and right eye image data RGBL(HG) and RGBR(HG) of the high gamma characteristic are addressed is longer than a vertical blanking period of a frame period, during which the left and right eye image data RGBL(LG) and RGBR(LG) of the low gamma characteristic are addressed, as shown inFIG. 15.

In a fifth exemplary embodiment of the invention, as shown inFIGS. 16 and 17, the controller11may continuously output the same left eye image data RGBLduring N frame periods, and then may continuously output the same right eye image data RGBRduring N frame periods following the N frame periods. As shown inFIG. 18, the controller11controls so that a vertical blanking period of a frame period during which first left and right eye image data RGBL(1) and RGBR(1) are displayed is longer than a vertical blanking period of a frame period during which second left and right eye image data RGBL(2) and RGBR(2) are displayed.

The controller11multiplies a frame frequency by N times, preferably, by four or more times, the input frame frequency, and generates a display panel control signal CDIS, a backlight control signal CBL, and the liquid crystal shutter control signal CSTbased on the multiplied frame frequency. The input frame frequency is 50 Hz in a phase alternate line (PAL) scheme and 60 Hz in a national television standards committee (NTSC) scheme. Accordingly, when multiplying the input frame frequency by four times, the controller11multiplies the frequency of the display panel control signal CDIS, the frequency of the backlight control signal CBL, and the frequency of the liquid crystal shutter control signal CSTbased on the frame frequency of 200 Hz or higher. When the frame frequency is 200 Hz, one frame period is about 5 msec, and when the frame frequency is 240 Hz, one frame period is about 4.16 msec.

The display panel control signal CDISincludes a data control signal for controlling an operation timing of the data driving circuit and a gate control signal for controlling an operation timing of the gate driving circuit. The data control signal includes a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, a polarity control signal POL, and the like. The source start pulse SSP controls a data sampling start time point of the data driving circuit. The source sampling clock SSC is a clock signal for controlling a sampling operation of the data driving circuit based on a rising edge or a falling edge. If digital video data to be input to the data driving circuit is transmitted based on a mini low voltage differential signaling (LVDS) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted. The polarity control signal POL inverts the polarity of the data voltage output from the data driving circuit every n horizontal periods, where n is a positive integer. The source output enable signal SOE controls an output timing of the data driving circuit. The gate control signal includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like. The gate start pulse GSP controls a timing of a first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls an output timing of the gate driving circuit.

The backlight control signal CBLcontrols the backlight driving circuit13to periodically turn on and off the light source of the backlight unit16as shown inFIGS. 5 to 18. The liquid crystal shutter control signal CSTis transmitted to the liquid crystal shutter control signal transmission unit14to alternately open and close the left eye shutter STLand the right eye shutter STRof the liquid crystal shutter glasses18.

FIG. 4is a detailed view of the controller11. As shown inFIG. 4, the controller11includes a first control signal generating unit21, a frame counter22, a line counter23, a second control signal generating unit25, a memory24, and a data separating unit26.

As shown inFIGS. 5 to 18, the first control signal generating unit21generates the display panel control signal CDISand the liquid crystal shutter control signal CSTusing the timing signals input from the video source. The first control signal generating unit21outputs the display panel control signal CDIS, so that data is written on the display panel15during an address period ADDR shown inFIGS. 8,12,14,15, and18. On the other hand, the first control signal generating unit21does not output the display panel control signal CDISduring a vertical blanking period VB in which there is no data.

The frame counter22counts a signal, for example, the vertical synchronous signal Vsync or the gate start pulse GSP having a pulse generated once during 1 vertical period (or 1 frame period) to generate a frame count signal Cnt_FR. The line counter23counts a signal, for example, the horizontal synchronous signal Hsync or the data enable signal DE having a pulse generated once during 1 horizontal period to generate a line count signal Cnt_LN.

The second control signal generating unit25receives the frame count signal Cnt_FR and the line count signal Cnt_LN to generate the backlight control signal CBLas shown inFIGS. 5 to 10.

The data separating unit26rearranges the digital video data RGB input from the memory24and separates the left eye image data RGBLand the right eye image data RGBR. The data separating unit26transmits the left eye image data RGBLand the right eye image data RGBRin accordance with the data sequence illustrated inFIGS. 5 to 18. The data separating unit26may insert the black data behind each of the left and right eye image data RGBLand RGBR. In addition, the data separating unit26may differently convert gamma characteristics of the left eye image data RGBLevery 1 frame period, and may differently convert gamma characteristics of the right eye image data RGBRsequential to the left eye image data RGBLevery 1 frame period. The data separating unit26outputs data during the address period ADDR shown inFIGS. 8,12,14,15, and18, but does not output data during the vertical blanking period VB.

Various methods of driving the stereoscopic image display according to the exemplary embodiments of the invention are described below with reference toFIGS. 5 to 18. InFIGS. 5,7, and9, ‘Br’ denotes the backlight unit16, and ‘STL’ and ‘STR’ denote the left eye shutter and the right eye shutter of the liquid crystal shutter glasses18, respectively.

FIG. 5is a flow chart illustrating a method of driving the stereoscopic image display according to the first exemplary embodiment of the invention.FIG. 6is a waveform diagram illustrating a driving waveform of the stereoscopic image display according to the first exemplary embodiment of the invention. The first exemplary embodiment will be described in detail in association with the stereoscopic image display illustrated inFIGS. 3 and 4.

As shown inFIGS. 5 and 6, the controller11separates the left eye image data RGBLand the right eye image data RGBRfrom the input digital video data RGB using the memory24in step S51.

One frame period is divided into the address period ADDR during which data is addressed by the display device and the vertical blanking period VB during which there is no data. The controller11may determine the address period ADDR and the vertical blanking period VB in each frame period based on the frame count and the line count, and also may determine turn-on time and turn-off time of the backlight unit16in step S52.

The controller11generates the display panel control signal CDISduring an address period ADDR of an nth frame period Fn. During the address period ADDR of the nth frame period Fn, the controller11supplies the left eye image data RGBLto the data driving circuit and generates the liquid crystal shutter control signal CSTof a high logic level. During the address period ADDR of the nth frame period Fn, the data driving circuit supplies the data voltage of the left eye image data RGBLto the data lines of the display panel15and addresses the left eye image data RGBLto the pixels of the display panel15. The liquid crystal shutter control signal reception unit17opens the left eye shutter STLand shuts the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the high logic level during the nth frame period Fn in steps S53and S54.

The controller11keeps the backlight control signal CBLat a low logic level during a predetermined time period T ranging from a start time point of the nth frame period Fn to a predetermined time point. The controller11then converts the backlight control signal CBLfrom the low logic level to a high low logic level. The predetermined time period T may be determined depending on a line count value within a time period larger than 0 and shorter than one frame period and may be determined to be a certain time following a response time of the liquid crystals. The backlight driving circuit13turns on the light source of the backlight unit16at a time point when the predetermined time period T has elapsed from the start time point of the nth frame period Fn in response to the backlight control signal CBLof the high logic level in steps S55and S56.

The controller11generates the display panel control signal CDISduring an address period ADDR of an (n+1)th frame period Fn+1, repeatedly supplies black data (for example, digital data “0000 0000”) stored in a register to the data driving circuit, and keeps the liquid crystal shutter control signal CSTat the high logic level in steps S57and S58. During the address period ADDR of the (n+1)th frame period Fn+1, the data driving circuit supplies the data voltage of the black data to the data lines of the display panel15and addresses the black data to the pixels of the display panel15. The backlight driving circuit13turns on the light source of the backlight unit16in response to the backlight control signal CBLof the high logic level during the (n+1)th frame period Fn+1. The liquid crystal shutter control signal reception unit17opens the left eye shutter STLand shuts the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the high logic level during the (n+1)th frame period Fn+1.

During a vertical blanking period VB of the (n+1)th frame period Fn+1, the controller11converts the backlight control signal CBLfrom the high logic level to a low logic level and then converts the liquid crystal shutter control signal CSTfrom the high logic level to a low logic level.

The backlight driving circuit13turns off the light source of the backlight unit16in response to the backlight control signal CBLof the low logic level during the vertical blanking period VB of the (n+1)th frame period Fn+1. The liquid crystal shutter control signal reception unit17shuts the left eye shutter STLand opens the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the low logic level during the vertical blanking period VB of the (n+1)th frame period Fn+1 in steps S59and S60.

The controller11generates the display panel control signal CDISduring an address period ADDR of an (n+2)th frame period Fn+2. During the address period ADDR of the (n+2)th frame period Fn+2, the controller11supplies the right eye image data RGBRto the data driving circuit and generates the liquid crystal shutter control signal CSTof a low logic level. During the address period ADDR of the (n+2)th frame period Fn+2, the data driving circuit supplies the data voltage of the right eye image data RGBRto the data lines of the display panel15and addresses the right eye image data RGBRto the pixels of the display panel15. The liquid crystal shutter control signal reception unit17shuts the left eye shutter STLand opens the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the low logic level during the (n+2)th frame period Fn+2 in steps S61and S62.

The controller11generates the backlight control signal CBLof the low logic level at a start time point of the (n+2)th frame period Fn+2 and then converts the backlight control signal CBLfrom the low logic level to the high logic level at a time point when the predetermined time period T has elapsed from the start time point of the (n+2)th frame period Fn+2. The backlight driving circuit13turns on the light source of the backlight unit16at a time point when the predetermined time period T has elapsed from the start time point of the (n+2)th frame period Fn+2 in response to the backlight control signal CBLof the high logic level in steps S63and S64.

The controller11generates the display panel control signal CDISduring an address period ADDR of an (n+3)th frame period Fn+3, repeatedly supplies the black data stored in a register to the data driving circuit, and keeps the liquid crystal shutter control signal CSTat the low logic level in steps S65and S66. During the address period ADDR of the (n+3)th frame period Fn+3, the data driving circuit supplies the data voltage of the black data to the data lines of the display panel15and addresses the black data to the pixels of the display panel15. The backlight driving circuit13turns on the light source of the backlight unit16in response to the backlight control signal CBLof the high logic level during the (n+3)th frame period Fn+3. The liquid crystal shutter control signal reception unit17shuts the left eye shutter STLand opens the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the low logic level during the (n+3)th frame period Fn+3.

During a vertical blanking period VB of the (n+3)th frame period Fn+3, the controller11converts the backlight control signal CBLto the low logic level and then converts the liquid crystal shutter control signal CSTto the high logic level in steps S67and S68. The backlight driving circuit13turns off the light source of the backlight unit16in response to the backlight control signal CBLof the low logic level during the vertical blanking period VB of the (n+3)th frame period Fn+3. The liquid crystal shutter control signal reception unit17opens the left eye shutter STLand shuts the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the high logic level during the vertical blanking period VB of the (n+3)th frame period Fn+3.

The response characteristic of the liquid crystals may be determined by a rising time τrand a falling time τfdefined by the following Equations 1 and 2.

In Equation 1, “VF” indicates a Freederick transition voltage when liquid crystal molecules start a slope movement, “d” indicates a cell gap between the liquid crystal cells, “Γ (gamma)” indicates a rotational viscosity of the liquid crystal molecule.

In Equation 2, “K” indicates modulus of elasticity of the liquid crystal.

In the response characteristic of the liquid crystals, the rising time τrof the liquid crystals may be greater than the falling time τfof the liquid crystals. In this case, if a duration of a frame period during which the black data is addressed is short, the liquid crystal cells may be insufficiently charged to the black data during the short frame period. Hence, image sticking may appear. In particular, when the frame frequency is equal to or greater than 200 Hz, a black data charge time of the liquid crystal cells because of a short duration of a frame period is insufficient.

In the first exemplary embodiment of the invention, as shown inFIG. 8, the controller11controls so that the durations of the vertical blanking periods VB of the frame periods Fn+1 and Fn+3 during which the black data is addressed are longer than the durations of the vertical blanking periods VB of the frame periods Fn and Fn+2 during which the left and right eye image data RGBLand RGBRare addressed. One frame period is about 4.16 msec at the frame frequency of 240 Hz. In this case, the address period ADDR of each of the frame periods Fn and Fn+2 during which the left and right eye image data RGBLand RGBRare addressed may be controlled to be equal to or less than about 4 msec, and the vertical blanking period VB of each of the frame periods Fn and Fn+2 may be controlled to be equal to or less than about 0.167 msec. On the contrary, the address period ADDR of each of the frame periods Fn+1 and Fn+3 during which the black data is addressed may be controlled to be equal to or less than about 4 msec, and the vertical blanking period VB of each of the frame periods Fn+1 and Fn+3 may be long controlled to be equal to or greater than about 1.833 msec.

FIG. 9is a flow chart illustrating a method of driving the stereoscopic image display according to the second exemplary embodiment of the invention.FIG. 10is a waveform diagram illustrating a driving waveform of the stereoscopic image display according to the second exemplary embodiment of the invention. The second exemplary embodiment will be described in detail in association with the stereoscopic image display illustrated inFIGS. 3 and 4.

As shown inFIGS. 9 and 10, the controller11separates the left eye image data RGBLand the right eye image data RGBRfrom the input digital video data RGB and counts frame periods and lines in steps S101and S102.

The controller11generates the display panel control signal CDISduring an address period ADDR of an nth frame period Fn. During the address period ADDR of the nth frame period Fn, the controller11supplies left eye image data RGBL(HG), which is modulated based on a high gamma characteristic illustrated inFIG. 11B, to the data driving circuit and generates the liquid crystal shutter control signal CSTof a high logic level.

The left eye image data RGBL(HG) of the high gamma characteristic illustrated inFIG. 11Bincreases a display luminance at a low gray level and a middle gray level, compared with a normal gamma characteristic illustrated inFIG. 11A. During the address period ADDR of the nth frame period Fn, the data driving circuit supplies the data voltage of the left eye image data RGBL(HG) of the high gamma characteristic to the data lines of the display panel15and addresses the left eye image data RGBL(HG) to the pixels of the display panel15.

The liquid crystal shutter control signal reception unit17opens the left eye shutter STLand shuts the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the high logic level during the nth frame period Fn. The controller11generates the backlight control signal CBLof the low logic level at a start time point of the nth frame period Fn and then converts the backlight control signal CBLfrom the low logic level to the high logic level at a time point when the predetermined time period T has elapsed from the start time point of the nth frame period Fn. The backlight driving circuit13turns on the light source of the backlight unit16at a time point when the predetermined time period T has elapsed from the start time point of the nth frame period Fn in response to the backlight control signal CBLof the high logic level in steps S103to S106.

The controller11generates the display panel control signal CDISduring an address period ADDR of an (n+1)th frame period Fn+1. During the address period ADDR of the (n+1)th frame period Fn+1, the controller11supplies left eye image data RGBL(LG), which is modulated based on a low gamma characteristic illustrated inFIG. 11C, to the data driving circuit and keeps the liquid crystal shutter control signal CSTat the high logic level. During the address period ADDR of the (n+1)th frame period Fn+1, the data driving circuit supplies the data voltage of the left eye image data RGBL(LG) of the low gamma characteristic to the data lines of the display panel15and addresses the left eye image data RGBL(LG) to the pixels of the display panel15.

The left eye image data RGBL(LG) of the low gamma characteristic illustrated inFIG. 11Cfurther lowers a display luminance at a low gray level and a middle gray level, compared with the normal gamma characteristic illustrated inFIG. 11A. The backlight driving circuit13turns on the light source of the backlight unit16in response to the backlight control signal CBLof the high logic level during the (n+1)th frame period Fn+1. The liquid crystal shutter control signal reception unit17opens the left eye shutter STLand shuts the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the high logic level during the (n+1)th frame period Fn+1 in steps S107and108.

During a vertical blanking period VB of the (n+1)th frame period Fn+1, the controller11converts the backlight control signal CBLfrom the high logic level to the low logic level and converts the liquid crystal shutter control signal CSTfrom the high logic level to the low logic level in steps S109and110. The backlight driving circuit13turns off the light source of the backlight unit16in response to the backlight control signal CBLof the low logic level during the vertical blanking period VB of the (n+1)th frame period Fn+1. The liquid crystal shutter control signal reception unit17shuts the left eye shutter STLand opens the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the low logic level during the vertical blanking period VB of the (n+1)th frame period Fn+1 in steps S109and110.

The controller11generates the display panel control signal CDISduring an address period ADDR of an (n+2)th frame period Fn+2. During the address period ADDR of the (n+2)th frame period Fn+2, the controller11supplies right eye image data RGBR(HG), which is modulated based on the high gamma characteristic illustrated inFIG. 11B, to the data driving circuit and generates the liquid crystal shutter control signal CSTof a low logic level. During the address period ADDR of the (n+2)th frame period Fn+2, the data driving circuit supplies the data voltage of the right eye image data RGBR(HG) of the high gamma characteristic to the data lines of the display panel15and addresses the right eye image data RGBR(HG) to the pixels of the display panel15. The liquid crystal shutter control signal reception unit17shuts the left eye shutter STLand opens the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the low logic level during the address period ADDR of the (n+2)th frame period Fn+2. The controller11generates the backlight control signal CBLof the low logic level at a start time point of the (n+2)th frame period Fn+2 and then converts the backlight control signal CBLfrom the low logic level to the high logic level at a time point when the predetermined time period T has elapsed from the start time point of the (n+2)th frame period Fn+2. The backlight driving circuit13turns on the light source of the backlight unit16at a time point when the predetermined time period T has elapsed from the start time point of the (n+2)th frame period Fn+2 in response to the backlight control signal CBLof the high logic level in steps S111to S114.

The controller11generates the display panel control signal CDISduring an address period ADDR of an (n+3)th frame period Fn+3. During the address period ADDR of the (n+3)th frame period Fn+3, the controller11supplies right eye image data RGBR(LG), which is modulated based on the low gamma characteristic illustrated inFIG. 11C, to the data driving circuit and keeps the liquid crystal shutter control signal CSTat the low logic level. During the address period ADDR of the (n+3)th frame period Fn+3, the data driving circuit supplies the data voltage of the right eye image data RGBR(LG) of the low gamma characteristic to the data lines of the display panel15and addresses the right eye image data RGBR(LG) to the pixels of the display panel15. The backlight driving circuit13turns on the light source of the backlight unit16in response to the backlight control signal CBLof the high logic level during the (n+3)th frame period Fn+3. The liquid crystal shutter control signal reception unit17shuts the left eye shutter STLand opens the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the low logic level during the (n+3)th frame period Fn+3 in steps S115and116.

During a vertical blanking period VB of the (n+3)th frame period Fn+3, the controller11converts the backlight control signal CBLfrom the high logic level to the low logic level and converts the liquid crystal shutter control signal CSTfrom the low logic level to the high logic level in steps S117and118. The backlight driving circuit13turns off the light source of the backlight unit16in response to the backlight control signal CBLof the low logic level during the vertical blanking period VB of the (n+3)th frame period Fn+3. The liquid crystal shutter control signal reception unit17opens the left eye shutter STLand shuts the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the high logic level during the vertical blanking period VB of the (n+3)th frame period Fn+3.

A method for modulating the gamma characteristic of data may use methods disclosed in Korean Patent Application No. 10-2006-0108849 (Nov. 6, 2006), Korean Patent Application No. 10-2006-0078873 (Aug. 21, 2006), Korean Patent Application No. 10-2007-0038438 (Apr. 19, 2007), Korean Patent Application No. 10-2006-0139203 (Dec. 30, 2006), etc. corresponding to the present applicant, and which are hereby incorporated by reference in their entirety.

In the response characteristic of the liquid crystals, the falling time τfof the liquid crystals may be greater than the rising time τrof the liquid crystals as shown inFIG. 7. In this case, if a duration of a frame period during which the left and right image data RGBL(LG) and RGBR(LG) of the low gamma characteristic are addressed is short as shown inFIGS. 9 and 10, it is difficult to sufficiently charge the liquid crystal cells to the data during the short frame period. In particular, when the frame frequency is equal to or greater than 200 Hz, the duration of the frame period is shortened. Therefore, charging time of the liquid crystal cells to data, which is modulated based on the low gamma characteristic, is insufficient. To solve such a problem, in the second exemplary embodiment of the invention, as shown inFIG. 12, the controller11controls so that the vertical blanking periods VB of the frame periods Fn+1 and Fn+3 during which the left and right image data RGBL(LG) and RGBR(LG) of the low gamma characteristic are addressed are longer than the vertical blanking periods VB of the frame periods Fn and Fn+2 during which the left and right image data RGBL(HG) and RGBR(HG) of the high gamma characteristic are addressed.

In the response characteristic of the liquid crystals, as shown inFIG. 13, the rising time τrof the liquid crystals may be greater than the falling time τfof the liquid crystals. In this case, it is preferable that a duration of a frame period during which the left and right image data RGBLand RGBRare addressed sufficiently increases. In the third exemplary embodiment of the invention, as shown inFIG. 14, the controller11controls so that the durations of the vertical blanking periods VB of the frame periods Fn and Fn+2 during which the left and right eye image data RGBLand RGBRare addressed are longer than the durations of the vertical blanking periods VB of the frame periods Fn+1 and Fn+3 during which the black data is addressed.

In the response characteristic of the liquid crystals, as shown inFIG. 13, the rising time τrof the liquid crystals may be greater than the falling time τfof the liquid crystals. In this case, it is preferable that a duration of a frame period during which the left and right image data RGBL(HG) and RGBR(HG) of the high gamma characteristic are addressed sufficiently increases. In the fourth exemplary embodiment of the invention, as shown inFIG. 15, the controller11controls so that the vertical blanking periods VB of the frame periods Fn and Fn+2 during which the left and right image data RGBL(HG) and RGBR(HG) of the high gamma characteristic are addressed are longer than the vertical blanking periods VB of the frame periods Fn+1 and Fn+3 during which the left and right image data RGBL(LG) and RGBR(LG) of the low gamma characteristic are addressed.

FIG. 16is a flow chart illustrating a method of driving the stereoscopic image display according to the third exemplary embodiment of the invention.FIG. 17is a waveform diagram illustrating a driving waveform of the stereoscopic image display according to the third exemplary embodiment of the invention. The third exemplary embodiment will be described in detail in association with the stereoscopic image display illustrated inFIGS. 3 and 4.

As shown inFIGS. 16 and 17, the controller11separates the left eye image data RGBLand the right eye image data RGBRfrom the input digital video data RGB and counts frame periods and lines in steps S151and S152.

The controller11generates the display panel control signal CDISand supplies first left eye image data RGBL(1) to the data driving circuit during an address period ADDR of an nth frame period Fn. During the address period ADDR of the nth frame period Fn, the controller11generates the backlight control signal CBLof a low logic level and the liquid crystal shutter control signal CSTof a high logic level. During the address period ADDR of the nth frame period Fn, the data driving circuit supplies the data voltage of the first left eye image data RGBL(1) to the data lines of the display panel15and addresses the first left eye image data RGBL(1) to the pixels of the display panel15. The backlight driving circuit13turns off the light source of the backlight unit16in response to the backlight control signal CBLof the low logic level during the nth frame period Fn. The liquid crystal shutter control signal reception unit17opens the left eye shutter STLand shuts the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the high logic level during the nth frame period Fn in steps S153and S154.

During an address period ADDR of an (n+1)th frame period Fn+1, the controller11generates the display panel control signal CDIS, supplies second left eye image data RGBL(2) to the data driving circuit, and keeps the liquid crystal shutter control signal CSTat the high logic level in steps S155and S156. Subsequently, the controller11converts the backlight control signal CBLfrom the low logic level to the high logic level at a time point when the predetermined time period T has elapsed from a start time point of the (n+1)th frame period Fn+1. During the address period ADDR of the (n+1)th frame period Fn+1, the data driving circuit supplies the data voltage of the second left eye image data RGBL(2) to the data lines of the display panel15and addresses the second left eye image data RGBL(2) to the pixels of the display panel15. The backlight driving circuit13turns on the light source of the backlight unit16at a time point when the predetermined time period T has elapsed from the start time point of the (n+1)th frame period Fn+1 in response to the backlight control signal CBLof the high logic level in steps S157and S158. The liquid crystal shutter control signal reception unit17opens the left eye shutter STLand shuts the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the high logic level during the (n+1)th frame period Fn+1.

During a vertical blanking period VB of the (n+1)th frame period Fn+1, the controller11converts the backlight control signal CBLfrom the high logic level to the low logic level and then converts the liquid crystal shutter control signal CSTfrom the high logic level to the low logic level. The backlight driving circuit13turns off the light source of the backlight unit16in response to the backlight control signal CBLof the low logic level during the vertical blanking period VB of the (n+1)th frame period Fn+1. The liquid crystal shutter control signal reception unit17shuts the left eye shutter STLand opens the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the low logic level during the vertical blanking period VB of the (n+1)th frame period Fn+1 in steps S159and160.

The controller11generates the display panel control signal CDISand supplies first right eye image data RGBR(1) to the data driving circuit during an address period ADDR of an (n+2)th frame period Fn+2. During the address period ADDR of the (n+2)th frame period Fn+2, the controller11generates the backlight control signal CBLof a low logic level and the liquid crystal shutter control signal CSTof a low logic level. During the address period ADDR of the (n+2)th frame period Fn+2, the data driving circuit supplies the data voltage of the first right eye image data RGBR(1) to the data lines of the display panel15and addresses the first right eye image data RGBR(1) to the pixels of the display panel15. The backlight driving circuit13turns off the light source of the backlight unit16in response to the backlight control signal CBLof the low logic level during the (n+2)th frame period Fn+2. The liquid crystal shutter control signal reception unit17shuts the left eye shutter STLand opens the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the low logic level during the (n+2)th frame period Fn+2 in steps S161and S162.

During an address period ADDR of an (n+3)th frame period Fn+3, the controller11generates the display panel control signal CDIS, supplies second right eye image data RGBR(2) to the data driving circuit, and keeps the liquid crystal shutter control signal CSTat the low logic level. Subsequently, the controller11converts the backlight control signal CBLfrom the low logic level to the high logic level at a time point when the predetermined time period T has elapsed from a start time point of the (n+3)th frame period Fn+3. During the address period ADDR of the (n+3)th frame period Fn+3, the data driving circuit supplies the data voltage of the second right eye image data RGBR(2) to the data lines of the display panel15and addresses the second right eye image data RGBR(2) to the pixels of the display panel15. The backlight driving circuit13turns on the light source of the backlight unit16at a time point when the predetermined time period T has elapsed from the start time point of the (n+3)th frame period Fn+3 in response to the backlight control signal CBLof the high logic level. The liquid crystal shutter control signal reception unit17shuts the left eye shutter STLand opens the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the low logic level during the (n+3)th frame period Fn+3 in steps S163to S166.

During a vertical blanking period VB of the (n+3)th frame period Fn+3, the controller11converts the backlight control signal CBLfrom the high logic level to the low logic level and then converts the liquid crystal shutter control signal CSTfrom the low logic level to the high logic level. The backlight driving circuit13turns off the light source of the backlight unit16in response to the backlight control signal CBLof the low logic level during the vertical blanking period VB of the (n+3)th frame period Fn+3. The liquid crystal shutter control signal reception unit17opens the left eye shutter STLand shuts the right eye shutter STRin response to the liquid crystal shutter control signal CSTof the high logic level during the vertical blanking period VB of the (n+3)th frame period Fn+3 in steps S167and168.

The second left eye image data RGBL(2) is the same as the first left eye image data RGBL(1), and the second right eye image data RGBR(2) is the same as the first right eye image data RGBR(1).

In the fifth exemplary embodiment of the invention, as shown inFIG. 18, the controller11controls so that the vertical blanking period VB of the frame period Fn during which the first left eye image data RGBL(1) is addressed is longer than the vertical blanking period VB of the frame period Fn+1 during which the second left eye image data RGBL(2) is addressed. Further, the controller11controls so that the vertical blanking period VB of the frame period Fn+2 during which the first right eye image data RGBR(1) is addressed is longer than the vertical blanking period VB of the frame period Fn+2 during which the second right eye image data RGBR(2) is addressed. The control method described in the fifth exemplary embodiment may obtain an effect similar to an overdriving compensation effect. An overdriving compensation method increases a value of |Va2−VF2| in the above Equation 1 based on change or non-change of data, thereby advancing response time of the liquid crystals. If the vertical blanking period VB of the frame period Fn during which the first left eye image data RGBL(1) is addressed is extended, a current frame may be maintained until a luminance of the liquid crystal cells reaches a target luminance. Therefore, the effect similar to the overdriving compensation effect may be obtained even if the data voltage is not modulated.

In the exemplary embodiments of the invention, the liquid crystal display is mainly described as the display device, but without being limited thereto, the display device according to the exemplary embodiments of the invention may be implemented as a flat panel display device, such as a field emission display, a plasma display panel, and an electroluminescence device (EL) including an inorganic field emission display and an organic light emitting diode (OLED), as well as the liquid crystal display.

As described above, in the exemplary embodiments of the invention, when the left eye image data and the right eye image data are time-division displayed on the display device and the stereoscopic image is implemented by time-dividing the liquid crystal shutter glasses, the crosstalk between the left eye image and the right eye image can be solved by controlling the turn-on and turn-off operations of the backlight unit. In addition, the flicker appearing in the stereoscopic image display method in which the vertical blanking period is extended and a shutter opening period of the liquid crystal shutter glasses is shortened can be solved. Further, power consumption can be reduced.

Furthermore, in the exemplary embodiments of the invention, the display device is driven in the optimum response characteristic of the display device by asymmetrically controlling the vertical blanking period of the frame period during which the continued black data is addressed and the vertical blanking period of the frame period during which the image data is addressed. As a result, the display quality of the stereoscopic image display according to the exemplary embodiments of the invention can increase.