System and method for adaptive in-network time alignment for envelope tracking power amplifier

A subscriber station is configured to extend a battery life using a method for envelope tracking power amplification. The subscriber station includes a main processor configured to perform a plurality of functions to operate the subscriber station. The subscriber station also includes a power source configured to provide power to one or more components in the subscriber station and an envelope tracking power amplifier (ET PA) configured to amplify a signal. The ETPA also is configured to estimate and adaptively maintain the envelope and RF signal time alignment during operation of the ET PA.

TECHNICAL FIELD

The present application relates generally to power management in mobile devices and, more specifically, to Adaptive Time Alignment process for Envelope Tracking RF Power Amplifier in mobile devices.

BACKGROUND

The wireless communication industry is experiencing tremendous growth in the mobile internet device with 4G LTE wireless network deployed. It allows data center to provide cloud computing service through the smartphone and tablet PC to make their business more efficient. Therefore extending battery life of the mobile internet device becomes very critical and puts pressure on the transmitter designer to focus on more sophisticated high efficiency RF power amplifier, e.g. Envelope Tracking (ET).

SUMMARY

A subscriber station is provided. The subscriber station includes a main processor configured to perform a plurality of functions to operate the subscriber station. The subscriber station also includes a power source configured to provide power to one or more components in the subscriber station and an envelope tracking power amplifier (ET PA) configured to amplify a signal. The ETPA also is configured to estimate and adaptively maintain the envelope and RF signal time alignment during operation of the ET PA.

An Envelope Tracking Power Amplifier (ET PA) is provided. The ET PA includes an envelope path, an RF path, a signal processing unit configured to receive a signal, a plurality of delays coupled to the signal processing unit and configured to delay a signal transmitted via one of the envelope path and the RF path, and a power amplifier (ET PA) configured to amplify a signal. The ET PA also includes a digital signal processor—central processing unit (DSP-CPU) coupled to an output of the power amplifier and to the plurality of delays. The DSP-CPU configured to estimate and adaptively maintain the envelope and RF signal time alignment during operation of the ET PA.

A method for envelope tracking power amplification is provided. The method includes estimating and adaptively maintaining an envelope and RF signal time alignment during the operation of an envelope tracking power amplifier.

DETAILED DESCRIPTION

In mobile communication system, a mobile phone includes an amplifier that essentially amplifies an input signal. A portion of the mobile phone's battery power is consumed by the amplifier. An Adaptive Time Alignment process is critical to the Envelope Tracking Power Amplifier (ET PA) to meet 3GPP mask requirements. Certain cross-correlation/auto-correlation processes are proposed to estimate the time mismatch. But these approaches are limited to estimate a short range time mismatch and require high computation time to achieve optimal ET performance.

The tolerance of the time alignment has narrow range in the linearity performance when an Envelope Tracking Power Amplifier (ET PA) operates at very high efficiency condition. In this case the Adjacent Channel Power Ratio (ACPR) performance can easily degrade a couple of dB and fail comply the mask requirement with small time mismatch in the range of from 500 ps to 1 ns. Cross-correlation/auto-correlation processes have limitation to estimate such a short range time mismatch since these processes estimate the time mismatch based on the distance between the highest and second peaks location. When the time misalignment is small, the highest peak and the second peak can merge together and the time mismatch cannot be identified. Furthermore the time mismatch often occurred with a small amount of time delay when the temperature and output power changed. Hence a cost effective solution, adaptive in-network time alignment process, can adaptively fine tuning time alignment between the envelope and RF path to optimize the ET PA linearity performance is required.

The Envelope Tracking (ET) system can provide a better power efficiency performance. However, its linearity performances, ACPR and Error Vector Magnitude (EVM), are sensitive to the delay mismatch between envelope and RF path to the PA. The auto-correlation time alignment process can be employed to estimate the time mismatch in the ET system. But it cannot compensate a short time mismatch. Moreover the estimate errors are introduced with the limited signal length, operating output power and shaping functions. Increasing the computation resource (Digital Signal Processor-Central Processing Unit (DSP-CPU) or Field Programmable Gate Array (FPGA) silicon area) to improve the accuracy of the process is impractical. To minimize the time mismatch estimate error and extend the time alignment range the adaptive in-network time alignment process is developed as a complementary function to the auto-correlation time alignment process. This approach can be used to maintain the time alignment adaptively during ET PA operation without disturbing the communication.

FIG. 1illustrates a subscriber station according to embodiments of the present disclosure. The embodiment of the subscribe station100illustrated inFIG. 1is for illustration only. Other embodiments of the wireless subscriber station could be used without departing from the scope of this disclosure.

UE100comprises antenna105, radio frequency (RF) transceiver110, transmit (TX) processing circuitry115, microphone120, and receive (RX) processing circuitry125. Although shown as a single antenna, antenna105can include multiple antennas. SS100also comprises speaker130, main processor140, input/output (I/O) interface (IF)145, keypad150, display155, and memory160. Memory160further comprises basic operating system (OS) program161and a plurality of applications162. The plurality of applications can include one or more of resource mapping tables (Tables 1-10 described in further detail herein below). SS100further includes a power source175coupled to the main processor140. In certain embodiments, power source175is a battery. Power source175is configured to provide power to the components of SS100. For example, power source175is configured to provide power for one or more of main processor140, antenna105, RF transceiver110, RX processing circuitry125, TX processing circuitry115, speaker130, microphone120, I/O interface (IF)145, keypad150, display155, and memory160. In certain embodiments, power source175represents multiple components configured to provide power to SS100. For example, power source175can be multiple batteries configured to provide power to different components within SS100.

Radio frequency (RF) transceiver110receives from antenna105an incoming RF signal transmitted by a base station of wireless network. Radio frequency (RF) transceiver110down-converts the incoming RF signal to produce an intermediate frequency (IF) or a baseband signal. The IF or baseband signal is sent to receiver (RX) processing circuitry125that produces a processed baseband signal by filtering, decoding, and/or digitizing the baseband or IF signal. Receiver (RX) processing circuitry125transmits the processed baseband signal to speaker130(i.e., voice data) or to main processor140for further processing (e.g., web browsing).

Transmitter (TX) processing circuitry115receives analog or digital voice data from microphone120or other outgoing baseband data (e.g., web data, e-mail, interactive video game data) from main processor140. Transmitter (TX) processing circuitry115encodes, multiplexes, and/or digitizes the outgoing baseband data to produce a processed baseband or IF signal. Radio frequency (RF) transceiver110receives the outgoing processed baseband or IF signal from transmitter (TX) processing circuitry115. Radio frequency (RF) transceiver310up-converts the baseband or IF signal to a radio frequency (RF) signal that is transmitted via antenna105.

In certain embodiments, main processor140is a microprocessor or microcontroller. Memory160is coupled to main processor140. According to some embodiments of the present disclosure, part of memory160comprises a random access memory (RAM) and another part of memory160comprises a Flash memory, which acts as a read-only memory (ROM).

Main processor140executes basic operating system (OS) program161stored in memory160in order to control the overall operation of wireless subscriber station100. In one such operation, main processor140controls the reception of forward channel signals and the transmission of reverse channel signals by radio frequency (RF) transceiver110, receiver (RX) processing circuitry125, and transmitter (TX) processing circuitry115, in accordance with well-known principles.

Main processor140is capable of executing other processes and programs resident in memory160, such as operations for performing adaptive time alignment for envelope tracking power amplification as described in embodiments of the present disclosure. Main processor140can move data into or out of memory160, as required by an executing process. In some embodiments, the main processor140is configured to execute a plurality of applications162, such as applications for Coordinated Multipoint (CoMP) communications and Multi-User-Multiple Input Multiple Output (MU-MIMO) communications. The main processor140can operate the plurality of applications162based on OS program161or in response to a signal received from a base station (BS). Main processor140is also coupled to I/O interface145. I/O interface145provides subscriber station100with the ability to connect to other devices such as laptop computers and handheld computers. I/O interface145is the communication path between these accessories and main controller140.

Main processor140is also coupled to keypad150and display unit155. The operator of subscriber station100uses keypad150to enter data into subscriber station100. Display155may be a liquid crystal display capable of rendering text and/or at least limited graphics from web sites. Alternate embodiments may use other types of displays.

The subscriber station100also includes an envelope tracking power amplifier (ET PA)170. The ET PA170is configured to amplify a signal that is received by the RX processing circuitry125or a signal that is generated by another component within SS100. The amplified signal can be output via speaker130, such as under control of the main processor140, an application162, RF transceiver110, ET PA170, RX processing circuitry125or TX processing circuitry115. The amplified signal also can be transmitted to the main processor140for further processing.

In certain embodiments, the envelope tracking power amplifier170is disposed within transceiver110. However, in other embodiments, the envelope tracking power amplifier170is located in another portion of the subscriber station100. For example, the envelope tracking power amplifier170can be disposed within the main processor140, RX processing circuitry125, TX processing circuitry115, or as a stand-alone circuitry coupled to one or more of the main processor140, RX processing circuitry125, TX processing circuitry115, the RF transceiver110and antenna105. In certain embodiments, the envelope tracking power amplifier170functions are included in a combination of the main processor140, RX processing circuitry125, TX processing circuitry115, the RF transceiver110and antenna105.

Embodiments of the present disclosure provide a robust envelope tracking (ET) time alignment method including an auto-correlation process and an adaptive time alignment process with a variable correction to update the time delay per iteration. Embodiments of the present disclosure take the advantage of the auto-correlation time alignment process to estimate long distance time mismatch in conjunction with the iterative process to compensate the short distance time mismatch, to minimize the time mismatch estimate error and maintain the ET system envelope/RF signal aligned during operation.

FIG. 2illustrates an envelope tracking power amplifier according to embodiments of the present disclosure. The embodiment of the ET PA170shown inFIG. 2is for illustration only. Other embodiments could be used without departing from the scope of the present disclosure.

In the example shown inFIG. 2, the ET PA170is a general block diagram of high efficient ET system. The ET PA170includes a digital signal processing block205(e.g., a FPGA). The digital signal processing block205includes circuitry for Fractional Delay210, Envelope Detector214, envelope path Coarse Delay216, Crest Factor Reduction (CFR)216, Digital Pre-Distortion (DPD)218, and RF Coarse Delay220. The FPGA205also includes a DSP-CPU225. The DSP-CPU225is responsible for the time alignment process and power amplifier modeling for the digital pre-distortion function. The time alignment units processed by the DSP-CPU225contain: Fractional delay in the envelope path235; and Coarse delay in the envelope and RF path245. The ET PA170also includes a Digital to Analog Converter (DAC)230for the envelope path235and a DAC240for the RF path245. The ET PA170further includes a modulator250coupled to a power amplifier255and a down converter260coupled between the power amplifier255and an analog to digital converter265, which is further coupled to the DSP CPU225.

The modulator250in the envelope path235delivers modulation power through the bias of the power amplifier (PA)255, which can be a Class AB power amplifier. During the amplification process, a complex signal is sent through the RF path245while its envelope waveform is sent simultaneously through the envelope path235to drive the PA255bias. The digital signal processing block205(e.g., FPGA) includes DSP-CPU225to perform the adaptive in-network time alignment and digital pre-distortion processes and three delay blocks (Fractional Delay210, envelope path Coarse Delay216, and RF Coarse Delay220) to compensate the time mismatch between the envelope path235and the RF path240. The digital signal processing block205contains the crest factor reduction and up-sampling process.

The ET PA170can provide a better power efficiency performance. However, its linearity performances, Adjacent Channel Leakage Ratio (ACPR) and EVM, are sensitive to the delay mismatch between envelope path235and RF path245to the PA255. The auto-correlation time alignment process can be employed to estimate the time mismatch in the ET PA170. However, the auto-correlation time alignment process cannot compensate a short time mismatch. Moreover the estimate errors are introduced with the limited signal length, operating output power and shaping functions. Increasing the computation resource (DSP-CPU or FPGA silicon area) to improve the accuracy of the process is impractical. To minimize the time mismatch estimate error and extend the time alignment range, the adaptive in-network time alignment process is developed as a complementary function to the auto-correlation time alignment process. This approach can be used to maintain the time alignment adaptively during ET PA170operation without disturbing the communication.

The ET PA170is configured to perform an adaptive time-alignment algorithm. The time alignment criterion is based on the mask performances (Evolved Universal Terrestrial Radio Access (EUTRA), UMTS Terrestrial Radio Access-1 (UTRA1), UMTS Terrestrial Radio Access-2 (UTRA2), and EVM). The ET PA170adaptive time-alignment process includes non-iterative and iterative parts. The Non-iterative part is an auto-correlation process used to determine a large time mismatch case to maximize the converging speed. The iterative part is used to determine smaller time mismatch case to achieve high resolution results.

The DSP-CPU225performs the time alignment process and power amplifier modeling for the digital pre-distortion function. The DSP-CPU225receives a feedback captured signal output from the PA255. The adaptive in-network time alignment process employs the auto-correlation results of the feedback captured signal to determine an initial time mismatch and, based on the ACPR or EVM of the feedback captured signal, performs adaptive updating the time delay (TD) blocks in the envelope path, the sum of the fractional delay and the coarse delay.

The DSP-CPU225is configured to use updating parameters to perform the adaptive time alignment process. The updating parameters per iteration include the correction of the time delay (ΔTD) and the updating direction. The DSP-CPU225changes the correction of the time delay with the deviation between the current and the targeting mask performances. Correction is big when the deviation is big. Correction is small when the deviation is small. The mask performances include UTRA, EUTRA and EVM. The DSP-CPU225determines the updating direction by the nearby (mask performance)+τwith a minimum time alignment resolution, +τ. If (mask performance)+τ>(mask performance)current
TD=TD+ΔTD(1)
Otherwise
TD=TD−ΔTD(2)

The DSP-CPU225computes a correction delta time delay (ΔTD) per iteration. The DSP-CPU225selects and dynamically changes the correction of the time delay per iteration based on the current ACPR. When the ACPR is deviated from mask requirements, for example greater than 4˜5 dBc, the DSP-CPU225selects a correction with a bigger time delay to increase the algorithm converging speed. However, when the ACPR is closer to the targeting mask performance, the DSP-CPU225reduces the correction to a smaller time delay to reduce the algorithm tracking noise while the ET PA170operating smoothly toward the optimal performance. During the ET PA170operation, the ET PA170invokes the auto-correlation process to determine the time delay when a perturbation causes a large time mismatch, which is quantified by the ACPR changed, for example 4˜5 dBc degradation. In certain embodiments, the DSP-CPU225invokes the auto-correlation process. In certain embodiments, the main processor140, or other processing circuitry (such as the RX processing circuitry125, TX processing circuitry115or RF transceiver110) invoke the auto-correlation process.

Time alignment is required to eliminate the distortion caused by the delay mismatch. Certain cross-correlation/auto-correlation based algorithms that estimate the time mismatch have one or more of the following limitations:

Estimate error: The performance of cross-correlation/auto-correlation algorithms is influenced by the dynamic supply voltage condition and the mask requirements. This requires high computation time to achieve acceptable ET performance.

Algorithm blind spot: These algorithms performances have limited resolution to estimate a small delay mismatch.

Time alignment requires iterative algorithm to achieve high precision time alignment. The correction size selection is critical to the performance of this algorithm. Iterative algorithm with fixed time delay correction has to tradeoff the performance of the converging speed and time alignment stability.
Time Delay(Current state)=Time Delay(Previous state)±Correction  (3)

The In-Network Adaptive Time Alignment Procedure

In-Network delay mismatch problems can occur in an ET system. As noted herein above, ET linearity performance in terms of ACPR and EVM at the output of the PA is highly sensitive to the delay mismatch between envelope path and RF path. Clipping of the amplified signal can result due to a misalignment between the envelope path and the RF path occurs. Conventional digital pre-distortion algorithms cannot compensate for linearity degradation caused by the delay mismatch. In embodiments of the present disclosure, the ET PA170incorporates an adaptive time alignment algorithm operating in the stealth mode to compensate the delay mismatch without failing the mask performance.

FIG. 3illustrates an adaptive envelope tracking power amplifier alignment process300according to embodiments of the present disclosure. While the flow chart depicts a series of sequential steps, unless explicitly stated, no inference should be drawn from that sequence regarding specific order of performance, performance of steps or portions thereof serially rather than concurrently or in an overlapping manner, or performance of the steps depicted exclusively without the occurrence of intervening or intermediate steps. The process depicted in the example depicted is implemented by a transmitter chain in, for example, a mobile station.

The DSP-CPU225is responsible for the time alignment algorithm and RF power amplifier characterization to generate the digital pre-distortion function. Therefore, the DSP-CPU225executes the procedures of the in-network time alignment process. The DSP-CPU225estimates an initial time delay (TD) of the ET PA170in block305. In block310, the DSP-CPU225measures and checks the ACPR of the ET PA170output signal. For example, the DSP-CPU225receives a feedback signal output from the PA255. The DSP-CPU225uses the feedback signal to measure and check the ACPR. Then, in block310, the DSP-CPU225determines whether or not to invoke the auto-correlation time alignment algorithm based on the ACPR. If the DSP-CPU225determines that the ACPR is greater than a threshold level in block315, the DSP-CPU225determines that a large time mismatch occurred and that the auto-correlation time alignment process is required in block320. In block320, the DSP-CPU225executes the auto-correlation time alignment process to update the time delay. If the DSP-CPU225determines that the ACPR is less than or equal to a threshold level in block315, the DSP-CPU225proceeds to block325. The DSP-CPU225determines the correction (ΔTD) of the time delay based on ACPR in block325. Thereafter, in block330, the DSP-CPU225determines the time delay update direction based on the ET PA170output (ACPR)τmeasurement. In the example shown inFIG. 3, the DSP-CPU225determines the time delay update direction by measuring the ET PA170output (ACPR)τwith a minimum resolution time delay, τ. In block335, the DSP-CPU225determines whether the ACPR is greater than the (ACPR)τ(i.e., ACPR>(ACPR)τ). Based on whether or not ACPR>(ACPR)τ, the DSP-CPU225updates the time delay with the time delay correction. When the ACPR>(ACPR)τ, the DSP-CPU225increases the current time delay with ΔTD in block340. When the ACPR≦(ACPR)τ, DSP-CPU225decreases the current time delay with ΔTD in block345.

FIG. 3illustrates an example in which the (ACPR)τmeasurement at the miss alignment delay is +τ, to determine the time mismatch update direction. When the (ACPR)τmeasurement at the miss alignment delay is −τ, the process can be modified as shown inFIG. 4.

FIG. 4illustrates another adaptive envelope tracking power amplifier alignment process400according to embodiments of the present disclosure. While the flow chart depicts a series of sequential steps, unless explicitly stated, no inference should be drawn from that sequence regarding specific order of performance, performance of steps or portions thereof serially rather than concurrently or in an overlapping manner, or performance of the steps depicted exclusively without the occurrence of intervening or intermediate steps. The process depicted in the example depicted is implemented by a transmitter chain in, for example, a mobile station.

The DSP-CPU225is responsible for the time alignment algorithm and RF power amplifier characterization to generate the digital pre-distortion function. Therefore, the DSP-CPU225executes the procedures of the in-network time alignment process. The DSP-CPU225estimates an initial time delay (TD) of the ET PA170in block405. In block410, the DSP-CPU225measures and checks the ACPR of the ET PA170output signal. For example, the DSP-CPU225receives a feedback signal output from the PA255. The DSP-CPU225uses the feedback signal to measure and check the ACPR. Then, in block410, the DSP-CPU225determines whether or not to invoke the auto-correlation time alignment algorithm based on the ACPR. If the DSP-CPU225determines that the ACPR is greater than a threshold level in block415, the DSP-CPU225determines that a large time mismatch occurred and that the auto-correlation time alignment process is required in block420. In block420, the DSP-CPU225executes the auto-correlation time alignment process to update the time delay. The DSP-CPU225determines the correction (ΔTD) of the time delay based on ACPR in block425. Thereafter, in block430, the DSP-CPU225determines the time delay update direction based on the ET PA170output (ACPR)τmeasurement. In the example shown inFIG. 4, the DSP-CPU225determines the time delay update direction based on the ET PA170output (ACPR)τmeasurement with a minimum resolution time delay, −τ. In block435, the DSP-CPU225determines whether the ACPR is greater than the (ACPR)τ(i.e., ACPR>(ACPR)τ). Based on whether or not ACPR>(ACPR)τ, the DSP-CPU225updates the time delay with the time delay correction. When the ACPR>(ACPR)τ, the DSP-CPU225decreases the current time delay with ATD in block440. When the ACPR≦(ACPR)τ, DSP-CPU225increases the current time delay with ΔTD in block445.

FIGS. 3 and 4illustrate an example in which (ACPR), measurement is used to determine the time mismatch update direction. When the (EVM), measurement is used, the process can be modified as shown inFIGS. 5 and 6.

FIG. 5illustrates another adaptive envelope tracking power amplifier alignment process500according to embodiments of the present disclosure. While the flow chart depicts a series of sequential steps, unless explicitly stated, no inference should be drawn from that sequence regarding specific order of performance, performance of steps or portions thereof serially rather than concurrently or in an overlapping manner, or performance of the steps depicted exclusively without the occurrence of intervening or intermediate steps. The process depicted in the example depicted is implemented by a transmitter chain in, for example, a mobile station.

The DSP-CPU225is responsible for the time alignment algorithm and RF power amplifier characterization to generate the digital pre-distortion function. Therefore, the DSP-CPU225executes the procedures of the in-network time alignment process. The DSP-CPU225estimates an initial time delay (TD) of the ET PA170in block505. In block510, the DSP-CPU225measures and checks the EVM of the ET PA170output signal. For example, the DSP-CPU225receives a feedback signal output from the PA255. The DSP-CPU225uses the feedback signal to measure and check the EVM. Then, in block510, the DSP-CPU225determines whether or not to invoke the auto-correlation time alignment algorithm based on the EVM. If the DSP-CPU225determines that the EVM is greater than a threshold level in block515, the DSP-CPU225determines that a large time mismatch occurred and that the auto-correlation time alignment process is required in block520. In block520, the DSP-CPU225executes the auto-correlation time alignment process to update the time delay. The DSP-CPU225determines the correction (ΔTD) of the time delay based on the EVM in block525. Thereafter, in block530, the DSP-CPU225determines the time delay update direction based on the ET PA170output (EVM)τmeasurement. In the example shown inFIG. 5, the DSP-CPU225determines the time delay update direction based on the ET PA170output (EVM)τmeasurement with a minimum resolution time delay, −τ. In block535, the DSP-CPU225determines whether the EVM is greater than the (EVM), (i.e., EVM>(EVM)τ). Based on whether or not EVM>(EVM)τ, the DSP-CPU225updates the time delay with the time delay correction. When the EVM>(EVM)τ, the DSP-CPU225decreases the current time delay with ΔTD in block540. When the EVM≦(EVM)τ, DSP-CPU225increases the current time delay with ΔTD in block545.

FIG. 5illustrates an example in which the (EVM)τmeasurement at the miss alignment delay is +τ, to determine the time mismatch update direction. When the (EVM)τmeasurement at the miss alignment delay is −τ, the process can be modified as shown inFIG. 6.

FIG. 6illustrates another adaptive envelope tracking power amplifier alignment process600according to embodiments of the present disclosure. While the flow chart depicts a series of sequential steps, unless explicitly stated, no inference should be drawn from that sequence regarding specific order of performance, performance of steps or portions thereof serially rather than concurrently or in an overlapping manner, or performance of the steps depicted exclusively without the occurrence of intervening or intermediate steps. The process depicted in the example depicted is implemented by a transmitter chain in, for example, a mobile station.

The DSP-CPU225is responsible for the time alignment algorithm and RF power amplifier characterization to generate the digital pre-distortion function. Therefore, the DSP-CPU225executes the procedures of the in-network time alignment process. The DSP-CPU225estimates an initial time delay (TD) of the ET PA170in block605. In block610, the DSP-CPU225measures and checks the EVM of the ET PA170output signal. For example, the DSP-CPU225receives a feedback signal output from the PA255. The DSP-CPU225uses the feedback signal to measure and check the EVM. Then, in block610, the DSP-CPU225determines whether or not to invoke the auto-correlation time alignment algorithm based on the EVM. If the DSP-CPU225determines that the EVM is greater than a threshold level in block615, the DSP-CPU225determines that a large time mismatch occurred and that the auto-correlation time alignment process is required in block620. In block620, the DSP-CPU225executes the auto-correlation time alignment process to update the time delay. The DSP-CPU225determines the correction (ΔTD) of the time delay based on the EVM in block625. Thereafter, in block630, the DSP-CPU225determines the time delay update direction based on the ET PA170output (EVM)τmeasurement. In the example shown inFIG. 6, the DSP-CPU225determines the time delay update direction based on the ET PA170output (EVM)τmeasurement with a minimum resolution time delay, −τ. In block635, the DSP-CPU225determines whether the EVM is greater than the (EVM)τ(i.e., EVM>(EVM)τ). Based on whether or not EVM>(EVM)τ, the DSP-CPU225updates the time delay with the time delay correction. When the EVM>(EVM)τ, the DSP-CPU225decreases the current time delay with ΔTD in block640. When the EVM≦(EVM)τ, DSP-CPU225increases the current time delay with ΔTD in block645.

The Auto-Correlation Time Alignment Algorithm

The DSP-CPU225invokes the auto-correlation time alignment process can invoke in the ET PA170initialization stage to estimate the delay mismatch. DSP-CPU225also can invoke the auto-correlation time alignment process when a large time mismatch occurs due to the environments changed during the ET PA170operation. The large time mismatch can be identified when ACPR dramatically increases, such as by 4˜5 dB.

Determine the Correction of the Time Delay

In certain embodiments, the ET PA170is configured to implement time delay updating size dynamically changed per iteration to achieve high tracking capability and low tracking noise performance from the developed adaptive time alignment process. A bigger correction by the DSP-CPU225can provide better tracking capability and fast converging speed. Normally a larger correction is required when the ACPR deviates from the targeting mask performance, such as by more than 2 to 3 dB. However, the high tracking capability can cause a tracking noise that even inhibits the ET system from reaching the perfect time alignment. Therefore, a smaller correction of the time delay is required when ACPR is closer to the targeting mask performance, for example less than 2 dB.

Determine the Time Delay Update Direction

The DSP-CPU225determines the time delay update direction by comparing the (ACPR)τobtained at current time delay, TD, with additional delay, +τ, to the ACPR measurement at the current time mismatch. When the (ACPR)τis smaller than the current ACPR, DSP-CPU225determines that the current time delays need to be increased to optimize the ET PA170system linearity, such as by using Equation 4:
TD=TD+ΔTD(4)

Similarly, when the (ACPR)τis bigger than the current ACPR, DSP-CPU225determines that the current time delays needs to be decreased, such as by using Equation 5:
TD=TD−ΔTD(5)

Performance Measurement

FIG. 7illustrates an example time alignment process converging speed performance with fixed correction according to embodiments of the present disclosure. The embodiment of the example shown inFIG. 7is for illustration only. The chart700shown inFIG. 7is illustrative of performance of embodiments of certain systems and is not limited to embodiments of the present disclosure.

Time alignment requires iterative algorithm to achieve high precision time alignment. The correction size selection is critical to the performance of existing time alignment algorithms. An iterative algorithm with fixed time delay correction has to tradeoff the performance of the converging speed and time alignment stability. The chart700inFIG. 7illustrates convergence speeds for Auto-correlation with a step size of 1 nano-second (ns)705; fixed step size of 4 ns710; fixed step size of 2 ns715; and fixed step size of 1 ns720. That is, the smaller the step size, the longer the convergence speed. For example, a step size of 1 ns720has a convergence speed of approximately 78 iterations while a step size of 4 ns710has a convergence speed of 20 iterations. However, as shown in chart800ofFIG. 8, the step size of 4 ns experiences severe “ringing” at convergence. For example, the ACLR can range from approximately −38.8 dB to −37.8 dB at convergence for a step size of 4 ns710as opposed to a range of less than 0.1 dB (approximately steady at −38.8 dB) for a step size of 1 ns720.

FIG. 9an example mask performance for an adaptive In-Network time alignment process according to embodiments of the present disclosure. The embodiment of the example shown inFIG. 9is for illustration only. The chart900shown inFIG. 9is illustrative of an example of performance of certain embodiments of the present disclosure in certain conditions and systems and should not be construed as limiting.

During the time alignment testing, the perturbations with different time mismatch lengths are deliberating generated. The initial stage and misalignments with 80 ns and 320 ns have a large ACPR 1stoffset and the auto-correlation process is invoked to estimate the time mismatch and achieve fast time alignment results. When the misalignments with a small amount of time mismatch including 16 ns, 8 ns and 32 ns, the adaptive in-network time alignment process employs a variable correction approach to achieve fast time alignment results. The measurement shows the EVM performance is synchronized with the ACPR 1stoffset results.

Embodiments of the present disclosure eliminate the correlation based algorithm blind spot and provide high precision time alignment with high speed and stable tracking results. Embodiments of the present disclosure also allow the adaptive time alignment process to estimate the delay mismatch in-network without interrupting communication. Embodiments of the present disclosure optimize the DSP computation time without modifying the legacy terminal ET/CFR/DPD core. Embodiments of the present disclosure can be processed with the narrow bandwidth observation to deliver low cost, high performance closed-loop ET/DPD solution. Embodiments of the present disclosure provide an envelope tracking power amplification system that is configured to extend battery life. Certain embodiments can improve battery performance by 45%-46% efficiency.

It can be also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the appended claims. For example, in some embodiments, the features, configurations, or other details disclosed or incorporated by reference herein with respect to some of the embodiments are combinable with other features, configurations, or details disclosed herein with respect to other embodiments to form new embodiments not explicitly disclosed herein. All of such embodiments having combinations of features and configurations are contemplated as being part of the present disclosure. Additionally, unless otherwise stated, no features or details of any of the embodiments disclosed herein are meant to be required or essential to any of the embodiments disclosed herein, unless explicitly described herein as being required or essential.

Although various features have been shown in the figures and described above, various changes may be made to the figures. For example, the size, shape, arrangement, and layout of components shown inFIGS. 1 and 2are for illustration only. Each component could have any suitable size, shape, and dimensions, and multiple components could have any suitable arrangement and layout. Also, various components inFIGS. 1 and 2could be combined, further subdivided, or omitted and additional components could be added according to particular needs. Further, each component in a device or system could be implemented using any suitable structure(s) for performing the described function(s). In addition, whileFIGS. 3 through 6illustrate various series of steps, various steps inFIGS. 3 through 6could overlap, occur in parallel, occur multiple times, or occur in a different order.