Printed wiring board

A printed wiring board includes a lowermost resin insulating layer, a first conductor layer formed on a first surface of the lowermost resin insulating layer, a conductor post formed in the lowermost resin insulating layer such that the conductor post has an upper surface facing the first surface and a lower surface on the opposite side with respect to the upper surface, a semiconductor element embedded in the lowermost resin insulating layer such that the semiconductor element has an electrode facing the first surface and is positioned on a second surface side of the lowermost resin insulating layer, and via conductors formed in the lowermost resin insulating layer and including a first via conductor and a second via conductor such that the first via conductor is connecting the first conductor layer and the conductor post and that the second via conductor is connecting the first conductor layer and the electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2015-233454, filed Nov. 30, 2015, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a printed wiring board with a built-in semiconductor element.

Description of Background Art

Japanese Patent Laid-Open Publication No. 2010-87085 describes a method in which an electronic component is embedded in a resin layer. According to Japanese Patent Laid-Open Publication No. 2010-87085, a through hole that penetrates two resin layers and reaches a conductor layer is formed. As illustrated in Japanese Patent Laid-Open Publication No. 2010-87085, a plating conductor is formed inside the through hole. The entire contents of this publication are incorporated herein by reference.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a printed wiring board includes a lowermost resin insulating layer, a first conductor layer formed on a first surface of the lowermost resin insulating layer, a conductor post formed in the lowermost resin insulating layer such that the conductor post has an upper surface facing the first surface and a lower surface on the opposite side with respect to the upper surface, a semiconductor element embedded in the lowermost resin insulating layer such that the semiconductor element has an electrode facing the first surface and is positioned on a second surface side of the lowermost resin insulating layer, and via conductors formed in the lowermost resin insulating layer and including a first via conductor and a second via conductor such that the first via conductor is connecting the first conductor layer and the conductor post and that the second via conductor is connecting the first conductor layer and the electrode.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1Aillustrates a cross-sectional view of a printed wiring board10of a first embodiment.

As illustrated inFIG. 1A, the printed wiring board10includes: a lowermost resin insulating layer50that has a first surface (F) and a second surface (S) that is on an opposite side of the first surface; a semiconductor element90that is embedded on the second surface (S) side of the lowermost resin insulating layer50and has electrodes92facing the first surface (F); conductor posts36that are formed in the lowermost resin insulating layer50; a first conductor layer58that is formed on the first surface (F) of the lowermost resin insulating layer50; first via conductors60(60f) that are formed in the lowermost resin insulating layer50and connect the first conductor layer58and the conductor posts36; and second via conductors60(60s) that connect the first conductor layer58and the electrodes92of the semiconductor element90.

As illustrated inFIG. 1A, the printed wiring board10may further include a second conductor layer34on the second surface. The second conductor layer34has a third surface (T) that opposes the first surface (F) and a fourth surface (B) that is on an opposite side of the third surface (T). A lower surface (36B) of each of the conductor posts36is in contact with the third surface (T). InFIG. 1A, the second conductor layer34is embedded in the lowermost resin insulating layer50and the fourth surface (B) is exposed from the second surface (S). The second conductor layer34has a conductor (mounting conductor) (34D) for mounting the semiconductor element90. In the second conductor layer34, conductors that are respectively formed below the lower surface (36B) of the conductor posts36are pads (conductor post pads) (34P) for the conductor posts36. The conductor post pads (34P) each have a shape of a circular cylinder.FIG. 8Aillustrates a conductor post pad (34P) and the lower surface (36B) of a conductor post36that is directly connected to the conductor post pad (34P).FIG. 8Ais a plan view. A solid line indicates an outer periphery of the conductor post pad (34P), and a dotted line indicates an outer periphery of the lower surface (36B) of the conductor post36. The outer periphery of the conductor post pad is positioned on an outer side of the outer periphery of the lower surface (36B) of the conductor post36. The entire outer periphery of the conductor post pad (34P) is exposed from the conductor post36. It is preferable that the fourth surface (B) have a rough surface.

As illustrated inFIG. 1A, the printed wiring board10may further include: an uppermost resin insulating layer150that is formed on the lowermost resin insulating layer50and the first conductor layer58; an uppermost conductor layer158that is formed on the uppermost resin insulating layer150; and uppermost via conductors160that penetrate the uppermost resin insulating layer150and connect the first conductor layer58and the uppermost conductor layer158. The printed wiring board10may further include a solder resist layer70on the uppermost resin insulating layer150and the uppermost conductor layer158. The solder resist layer70has openings72for exposing the uppermost conductor layer158. Portions of the uppermost conductor layer158that are exposed by the openings72function as pads74.

The electronic component90such as a semiconductor element is mounted on the mounting conductor circuit (34D) via a conductive paste80. The semiconductor element90has a thickness (90T). The thickness (90T) is a distance between a back surface (90B) of the semiconductor element and an upper surface of each of the electrodes92. The thickness (90T) is 50 μm or more and 150 μm or less. The semiconductor element90has a height (HS). The height (HS) is measured relative to the second surface (S). The height (HS) is a distance from the second surface to the upper surface of each of the electrodes92. The height (HS) is 50 μm or more and 150 μm or less. Examples of the conductive paste80include a solder paste and a silver paste. A metal paste having a high thermal conductivity is used for the conductive paste80. Heat from the semiconductor element is released to outside via the metal paste. When the fourth surface (B) of the second conductor layer34has a rough surface, a surface area of the fourth surface (B) is increased. Heat is transmitted from the semiconductor element to the second conductor layer34and is efficiently released to the outside via the rough surface of the second conductor layer34. Fins for heat dissipation can be attached on the fourth surface (B) of the second conductor layer34. Malfunction of the semiconductor element can be prevented.

The conductor posts36each extend from the second surface (S) toward the first surface (F), and each have an upper surface (36T) that faces the first surface (F) and the lower surface (36B) that is on an opposite side of the upper surface. The lower surface (36B) faces the second surface (S). The conductor posts36each have a length (b). The length (b) is a distance between the upper surface (36T) and the lower surface (36B). The length (b) is 50 μm or more and 200 μm or less. There is a distance (K3) between the lower surface (36B) and the second surface (S). There is a distance (K1) between the upper surface (36T) and the first surface (F). The distance (K1) is larger than the distance (K3). The distance (K1) is larger than 0. The distance (K3) is 0 or more. There is a distance (K2) between the upper surface of each of the electrodes92of the semiconductor element90and the first surface (F). An example of a shape of each of the conductor posts36is a circular cylinder. The conductor posts36each have a diameter (a) of 50 μm or more and 200 μm or less. The conductor posts36each have a height (HP). The height (HP) is measured relative to the second surface (S). The height (HP) is a distance from the second surface (S) to the upper surface (36T). The height (HP) is 50 μm or more and 150 μm or less. The conductor posts36surround the semiconductor element90. It is preferable that the printed wiring board10include at least two rows of conductor posts36. It is preferable that the number of conductor posts for grounding among conductor posts36belonging to a row closest to the semiconductor element90be larger than the number of conductor posts for grounding among conductor posts36belonging to a row farthest from the semiconductor element90. The conductor posts for grounding are electrically connected to the ground. All of the conductor posts36belonging to the row closest to the semiconductor element90may be conductor posts for grounding. The semiconductor element90is shielded.

The lowermost resin insulating layer50has openings (51f) for the first via conductors60(60f) respectively extending from the first surface (F) of the lowermost resin insulating layer50to the upper surfaces (36T) of the conductor posts36. The openings (51f) each have a depth (f1). The depth (f1) is equal to the distance (K1). The depth (f1) is 5 μm or more and 50 μm or less.

The lowermost resin insulating layer50has openings (51s) for the second via conductors60(60s) respectively extending from the first surface (F) of the lowermost resin insulating layer50to the upper surfaces of the electrodes of the semiconductor element. The openings (51s) each have a depth (f2). The depth (f2) is equal to the distance (K2). The depth (f2) is 5 μm or more and 50 μm or less.

As illustrated inFIG. 3D, the first via conductors60(60f) are formed in the openings (51f). Therefore, the first via conductors (60f) each have a length (f1). The length (f1) and the depth (f1) are equal to each other. The first via conductors (60f) are respectively connected to the upper surfaces (36T) of the conductor posts36.

As illustrated inFIG. 3D, the second via conductors (60s) are formed in the openings (51s). Therefore, each of the second via conductors (60s) has a length (f2). The length (f2) and the depth (12) are equal to each other. The second via conductors (60s) are respectively connected to the upper surfaces of the electrodes of the semiconductor element90.

It is preferable that the height (HP) of the conductor posts36and the height (HS) of the semiconductor element90are equal to each other. The length (f1) of the first via conductors (60f) and the length (f2) of the second via conductors (60s) become equal to each other. Therefore, even when the printed wiring board10is subjected to heat cycles, a stress is unlikely to concentrate on the first via conductors (60f) or on the second via conductors (60s). Reliability of connection via the first via conductors (60f) or the second via conductors (60s) is unlikely to be reduced. Further, the openings (51f) and the openings (51s) can be formed under the same conditions. A process is simplified.

Strength of the semiconductor element90that is formed in a central region of the printed wiring board10is higher than strength of the conductor posts36that are formed in an outer periphery region of the printed wiring board10. Therefore, strength of the outer periphery region of the printed wiring board is likely to be lower than strength of the central region of the printed wiring board. When the difference in strength is large, a crack is likely to occur in the lowermost resin insulating layer50between the semiconductor element90and the conductor posts36. In order to prevent occurrence of a crack, it is desirable that the difference in strength be small. For example, the difference in strength can be reduced by increasing a volume of each of the conductor posts36. When the length (b) of the conductor posts36and the diameter (a) of the conductor posts are large, the difference in strength can be reduced. Among the length (b) and the diameter (a), when the diameter (a) is increased, a size of the printed wiring board10is increased. When the size of the printed wiring board10is large, warpage or undulation of the printed wiring board10is likely to increase. Therefore, it is difficult to prevent occurrence of a crack by increasing the diameter (a). In contrast, even when the length (b) is increased, the size of the printed wiring board10is not significantly changed. Therefore, it is preferable to prevent occurrence of a crack by adjusting the length (b). By making the length (b) larger than the thickness (90T), a crack becomes unlikely to occur.

The semiconductor element90is embedded on the second surface (S) of the lowermost resin insulating layer50. Therefore, strength of the second surface (S) side of the lowermost resin insulating layer50is higher than strength of the first surface (F) side of the lowermost resin insulating layer50. A position of the semiconductor element90in the lowermost resin insulating layer50is a cause of a crack. A diameter of each of the conductor posts36is larger than a diameter of each of the first via conductors (60f). Therefore, by increasing the height (HP), the strength of the first surface (F) side of the lowermost resin insulating layer50is increased. Therefore, it is expected that, by increasing the height (HP), occurrence of a crack due to the position of the semiconductor element90is suppressed. Therefore, when the height (HP) and the height (HS) are different from each other, it is preferable that the height (HP) be higher than the height (HS). It is preferable that the length (f1) of the first via conductors (60f) be shorter than the length (f2) of the second via conductors (60s). In the present embodiment, the first surface (F) and the second surface (S) side are connected to each other via the conductor posts36and the first via conductors (60f). Therefore, the height of the conductor posts36can be easily adjusted. When the height (HP) is higher than the height (HS), a difference (d1) between the height (HP) and the height (HS) is 20 μm or less. When the difference (d1) exceeds 20 μm, a difference between the length of the first via conductors (60f) and the length of the second via conductors (60s) is too large. A stress is likely to concentrate on the first via conductors (60f) or the second via conductors (60s). Reliability of connection via the via conductors (60f,60s) is likely to deteriorate.

It is desirable that a ratio (K1/K2) of the distance (K1) to the distance (K2) be 0.6 or more and 0.9 or less. When the ratio (K1/K2) is less than 0.6, the difference between the length of the first via conductors (60f) and the length of the second via conductors (60s) is too large. The connection reliability deteriorates. When the ratio (K1/K2) exceeds 0.9, the effect achieved by increasing the volume of the conductor posts36is decreased.

When the height (HS) is higher than the height (HP), a difference (d2) (FIG. 1C) between the height (HP) and the height (HS) is 10 μm or less. When the difference (d2) exceeds 10 μm, the difference in strength is too large. Reliability of the connection via the via conductors (60f,60s) deteriorates.

The printed wiring board10of the first embodiment accommodates the semiconductor element90in the lowermost resin insulating layer50. Therefore, a thickness of the lowermost resin insulating layer50is likely to increase. When conductors on the first surface (F) side of the lowermost resin insulating layer50and conductors on the second surface (S) side are connected only via the via conductors, the length of the via conductors is increased. The openings for the via conductors are deep and thus it becomes technologically difficult to form the via conductors. Large voids are likely to occur in the via conductors. Films that form the via conductors become thin. As a result, reliability of the connection via the via conductors is decreased. In contrast, in the present embodiment, the conductors on the first surface (F) side of the lowermost resin insulating layer50and the conductors on the second surface (S) side are connected via the conductor posts36and the first via conductors (60f). An example of the conductor son the first surface (F) side is the first conductor layer. Examples of the conductors on the second surface (S) side are the lower surfaces (36B) of the conductor posts36and the second conductor layer34. Due to the presence of the conductor posts36, the depth of the openings (51f) for the first via conductors (60f) is reduced. The openings (51f) can be easily filled with plating. The first via conductors (60f) do not contain voids. Or, the first via conductors (60f) do not contain voids related to the connection reliability. Further, the second conductor layer34is embedded in the lowermost resin insulating layer50. The conductor posts36are formed on the second conductor layer34. Therefore, the height (HP) of the conductor posts36can be easily increased. Therefore, when the printed wiring board10has the second conductor layer34that is embedded in the lowermost resin insulating layer50, the connection reliability of the printed wiring board10is likely to be high.

FIG. 5Aillustrates a cross section of a printed wiring board according to a first modified embodiment of the first embodiment.

In the first modified embodiment of the first embodiment, the second conductor layer34is not formed below the lower surfaces (36B) of the conductor posts36. The lower surfaces (36B) of the conductor posts36are exposed from the second surface (S) of the lowermost resin insulating layer50. As illustrated inFIG. 5A, the lower surfaces (36B) of the conductor posts36are recessed from the second surface (S) of the lowermost resin insulating layer50.

InFIG. 5A, the second conductor layer34is formed by the mounting conductor circuit (34D) only. In the first modified embodiment of the first embodiment, the lower surfaces (36B) of the conductor posts36are exposed to the outside. Therefore, when the printed wiring board10of the first modified embodiment of the first embodiment is connected to a motherboard or an electronic component, data is transmitted to the conductor posts36without passing through the second conductor layer. The data is unlikely to deteriorate. Further, the lower surfaces (36B) of the conductor posts36function as terminals for connecting to a motherboard or an electronic component. Since the second conductor layer34is not formed below the lower surfaces (36B) of the conductor posts36, distances between adjacent conductor posts36are shortened. The size of the printed wiring board can be reduced. A high density printed wiring board can be provided. Warpage of the printed wiring board is reduced. A sophisticated electronic component or motherboard can be mounted on the printed wiring board10. The mounting conductor circuit (34D) can be removed from the printed wiring board10ofFIG. 5A. In this case, the printed wiring board10does not have the second conductor layer34. The lower surfaces (36B) of the conductor posts36and the conductive paste80are exposed. The lower surfaces (36B) of the conductor posts36and the conductive paste80may be recessed from the second surface (S) of the lowermost resin insulating layer50.

FIG. 5Billustrates a cross section of a printed wiring board according to a second modified embodiment of the first embodiment. InFIG. 1A, the second conductor layer34is embedded in the lowermost resin insulating layer50. In contrast, inFIG. 5B, the second conductor layer34protrudes from the second surface (S) of the lowermost resin insulating layer50. Other than that, the printed wiring board10ofFIG. 1Aand the printed wiring board10ofFIG. 5Bare the same.

FIG. 5Cillustrates a cross section of a printed wiring board according to a third modified embodiment of the first embodiment. InFIG. 5C, a lowermost conductor layer35is added to the printed wiring board10ofFIG. 1A. The lowermost conductor layer35is formed on the fourth surface (B) of the second conductor layer34and on the second surface (S) of the lowermost resin insulating layer50. The lowermost conductor layer35has lowermost pads (35P) that respectively connect to the conductor post pads (34P). The conductor post pads (34P) and the lowermost pads (35P) are respectively directly connected to each other. The lowermost pads (35P) each have a shape of a circular cylinder.FIG. 8Billustrates plan views of a conductor post pad (34P) and a lowermost pad (35P).FIG. 8Billustrates a size of the conductor post pad (34P) and a size of the lowermost pad (35P). An outer periphery of the lowermost pad (35P) is indicated using a solid line, and an outer periphery of the conductor post pad (34P) is indicated using a dotted line. The lowermost pad (35P) is larger than the conductor post pad (34P). It is preferable that the lowermost conductor layer35be formed by the lowermost pads (35P) only. When the lowermost conductor layer35does not have a conductor circuit below the mounting conductor circuit (34D), the difference in strength between the central region and the outer periphery region is reduced. Further, distanced between the semiconductor element90and the conductor post pads (34P) can be reduced. The size of the printed wiring board10can be reduced. When the lowermost conductor layer35has a conductor circuit below the mounting conductor circuit (34D), heat from the semiconductor element can be efficiently released.

Second Embodiment

FIG. 6Ais a cross-sectional view of a printed wiring board according to a second embodiment of the present invention.FIG. 6Bis a plan view of the printed wiring board of the second embodiment.FIG. 6Bis obtained by cutting the printed board10ofFIG. 6Awith a plane that is parallel to the first surface (F) and passes through a position (Y1) illustrated inFIG. 6A.FIG. 6Ais a cross-sectional view of the printed circuit board10between points (X1, X1) inFIG. 6B.

In the printed circuit board of the second embodiment, a shield structure (shield structure of a first example)37is added to the printed wiring board10ofFIG. 1A. As illustrated inFIG. 6B, the shield structure37is formed between the semiconductor element90and the conductor posts36. The shield structure37completely surrounds the semiconductor element. The semiconductor element90is surrounded by the shield structure37that is formed by four walls (W1, W2, W3, W4). As illustrated inFIGS. 6A and 6B, the shield structure37ofFIG. 6Ais formed by four walls (W1, W2, W3, W4). It is preferable that a height of the shield structure and the height of the conductor posts be substantially equal to each other. It is preferable that the shield structure37be formed of a conductor and be connected to the ground. The semiconductor element90is shielded by the shield structure. Therefore, data transmitted through the conductor posts36is unlikely to be deteriorated by electromagnetic waves from the semiconductor element90.

FIG. 6Cillustrates a cross section of a printed wiring board according to a first modified embodiment of the second embodiment.

In the first modified embodiment of the second embodiment, a size of the mounting conductor (mounting conductor circuit) (34D) is larger than a size of the semiconductor element90. Further, the shield structure (shield structure of a second example)37is electrically connected to the mounting conductor circuit (34D) and penetrates the lowermost resin insulating layer50. The shield structure37is formed on the mounting conductor circuit (34D). The shield structure37is formed in an outer peripheral region of the mounting conductor circuit (34D). Since the shield structure37and the mounting conductor circuit (34D) are connected to each other, the mounting conductor circuit (34D) functions as a shield layer (second shield layer) (34E). The first conductor layer58has a first shield layer (58E) that is electrically connected to the shield structure37. The first shield layer (58E) is formed on the first surface (F) of the lowermost resin insulating layer50such that the semiconductor element90is covered by the first shield layer (58E). Further, the first shield layer (58E) opposes the second shield layer (34E). The semiconductor element90is sandwiched between the first shield layer (58E) and the second shield layer (34E). The semiconductor element90is surrounded by the shield structure37. The semiconductor element90is sterically shielded by the shield structure37and the shield layers (58E,34E). Therefore, data transmitted through the conductor posts36is unlikely to be deteriorated by electromagnetic waves from the semiconductor element90. The first shield layer (58E), the second shield layer (34E) and the shield structure37are electrically connected to the ground.FIG. 6Dillustrates an example of the first shield layer (58E). The shield layer (58E) has openings370. Lands (60sL) of the second via conductors (60s) are respectively formed in the openings370.

In the shield structure37ofFIG. 6B, the shield structure is continuous. In contrast, in a third example of the shield structure37illustrated inFIGS. 7A and 7B, the shield structure37is formed by multiple shield conductor posts39. Similar toFIG. 6B, the plan view ofFIG. 7Bis obtained by cutting the printed wiring board ofFIG. 7Awith a plane passing through a position (Y1).

The shield conductor posts39of the third example do not penetrate the lowermost resin insulating layer50. A diameter of each of the shield conductor posts39is smaller than the diameter of each of the conductor posts36. Even when the printed board10has the shield structure37, the size of the printed board is unlikely to increase. Except for the shape of the shield structure37, the printed wiring board ofFIG. 6Aand the printed wiring board ofFIG. 7Aare the same. A height of the shield conductor posts39and the height of the conductor posts36are substantially equal to each other.

In the shield structure37ofFIG. 6C, the shield structure is continuous. In contrast, in a fourth example of the shield structure37illustrated inFIG. 7C, the shield structure37is formed by multiple shield conductor posts39. The shield conductor posts39of the fourth example penetrate the lowermost resin insulating layer50. A diameter of each of the shield conductor posts39is smaller than the diameter of each of the conductor posts36. Even when the printed board10has the shield structure37, the size of the printed board is unlikely to increase. Except for the shape of the shield structure, the printed wiring board ofFIG. 6Cand the printed wiring board ofFIG. 7Care the same. Therefore, the printed wiring board ofFIG. 7Chas the first shield layer (58E) and the second shield layer (34E) that are connected to the shield structure37of the fourth example.

A fifth example of the shield structure37is illustrated inFIG. 8D. In the fifth example, the shield structure37is formed by a first shield structure371and a second shield structure372that is formed on the first shield structure371. The first shield structure371and the conductor posts36are formed at the same time. A process is simplified. A height of the first shield structure371and the height of the conductor posts36are substantially equal to each other. The second shield structure372and the first via conductors (60f) are formed at the same time. A process is simplified. A length of the second shield structure372and the length of the first via conductors (60f) are substantially equal to each other. The first shield structure371is formed by a wall. Alternatively, the first shield structure371is formed by the shield conductor posts39. The second shield structure372is formed by a wall. Alternatively, the second shield structure372is formed by via conductors that are respectively formed on the shield conductor posts.

The printed wiring board of the second embodiment can adopt the printed wiring board of the first embodiment or the printed wiring board of each of the modified embodiments of the first embodiment. The printed wiring board of each of the modified embodiments of the second embodiment can adopt the printed wiring board of the first embodiment or the printed wiring board of each of the modified embodiments of the first embodiment. The shield structure37increases the strength of the lowermost resin insulating layer50that is formed between the conductor posts36and the semiconductor element90. A crack is unlikely to occur in the lowermost resin insulating layer50that is formed between the conductor posts36and the semiconductor element90. As illustrated inFIG. 8E, the shield structure37that is formed by a wall may have opening373. The lowermost resin insulating layer50that is formed between the shield structure37and the semiconductor element90and the lowermost resin insulating layer50that is formed outside the shield structure37are connected in the openings373of the shield structure37. Even when the printed board has the shield structure37, a defect such as a crack is unlikely to occur in the lowermost resin insulating layer50.

Method for Manufacturing Printed Wiring Board

FIG. 2A-4Dillustrate a method for manufacturing the printed wiring board of the first embodiment.

A support plate30is prepared. An example of the support plate30is a double-sided copper-clad laminated plate. A copper foil28is laminated on the support plate30(FIG. 2A). A plating resist is formed on the copper foil28. An electrolytic copper plating film is formed by electrolytic copper plating on the copper foil28that is exposed from the plating resist. The plating resist is removed. The second conductor layer34is formed from the electrolytic copper plating film (FIG. 2B). The second conductor layer34includes the mounting conductor circuit (34D) and the conductor post pads (34P). A plating resist24having openings (24A) is formed on the copper foil28and the second conductor layer34(FIG. 2C). The openings (24A) partially expose the conductor post pads (34P). The openings (24A) are each filled with plating22. The conductor posts36are respectively formed on the conductor post pads (34P) (FIG. 2D).

The plating resist24is removed. The conductor posts36are exposed (FIG. 3A). The semiconductor element90is mounted in the mounting conductor circuit (34D) via the conductive paste80(FIG. 3B). The semiconductor element90is mounted on the conductive paste80such that the electrodes92face upward. The lowermost resin insulating layer50is formed on the copper foil28, the second conductor layer34and the semiconductor element90. The lowermost resin insulating layer50has the second surface (S) and the first surface (F) that is on an opposite side of the second surface. The second surface (S) opposes the copper foil28. The second conductor layer34and the semiconductor element90are embedded on the second surface (S) of the lowermost resin insulating layer50. The openings (51f) for the first via conductors reaching the conductor posts36and the openings (51s) for the second via conductors reaching the electrodes92of the semiconductor element90are formed in the lowermost resin insulating layer50using laser (FIG. 3C). An electroless plating film is formed on the first surface of the lowermost resin insulating layer50and in the openings (51f,51s) for the via conductors. Thereafter, a plating resist is formed on the electroless plating film. An electrolytic plating film is formed on the electroless plating film that is exposed from the plating resist. The openings (51f,51s) are filled with the electrolytic plating, and the first via conductors (60f) and the second via conductors (60s) are formed. The plating resist is removed. The electroless plating film that is exposed from the electrolytic plating film is removed and the first conductor layer58is formed (FIG. 3D). Since the semiconductor element90is accommodated, the lowermost resin insulating layer50is likely to become thick. However, the present embodiment has conductor posts36. Therefore, the openings (51f) for the first via conductors become shallow. The openings (51f) for the first via conductors are easily filled with the plating. The openings (51s) for the second via conductors reach the electrodes92of the semiconductor element90. The openings (51s) for the second via conductors are easily filled with the plating. Reliability of the connection via the via conductors (60f,60s) is increased.

The uppermost resin insulating layer150is formed on the lowermost resin insulating layer50and the first conductor layer58. Openings151for via conductors reaching the first conductor layer58are formed in the uppermost resin insulating layer150using laser (FIG. 4A). The uppermost conductor layer158and the uppermost via conductors160are formed by a process same as that ofFIG. 3D(FIG. 4B). The solder resist layer70having the openings72that expose the pads74is formed on the uppermost resin insulating layer150(FIG. 4C). An intermediate substrate110illustrated inFIG. 4Cis formed on the support plate30. The intermediate substrate110ofFIG. 4Cis formed by the printed wiring board10ofFIG. 1Aand the copper foil28.

The intermediate substrate110is separated from the support plate30(FIG. 4D). The copper foil28is removed from the intermediate substrate110. The printed wiring board10illustrated inFIG. 1Ais completed. When solder bumps (76F,76S) are formed on the pads74and the conductor post pads (34P), a printed wiring board having the solder bumps illustrated inFIG. 1Bis completed.

A protective film is affixed on the solder resist layer70and the pads74of the printed wiring board illustrated inFIG. 1A. A protective film is affixed on the mounting conductor circuit (34D) in the second conductor layer34. Thereafter, the conductor post pads (34P) are removed. The protective film is removed. The printed wiring board10illustrated inFIG. 5Ais completed. When the second conductor layer34is removed without forming the protective film on the second surface (S), the mounting conductor circuit (34D) is removed from the printed wiring board10illustrated inFIG. 5A.

Method for Manufacturing Printed Wiring Board According to Second Modified Embodiment of First Embodiment

The support plate30and the copper foil28that are illustrated inFIG. 2Aare prepared. A plating resist for forming the conductor posts36on the copper foil28is formed. The conductor posts36are formed on the copper foil28that is exposed from the plating resist. The plating resist is removed. The conductive paste80is formed in the central region of the copper foil28. The semiconductor element90is mounted on the conductive paste. Thereafter, the lowermost resin insulating layer50is formed on the copper foil28such that the semiconductor element90and the conductor posts36are embedded. Thereafter, the processes illustrated inFIGS. 3C, 3D, 4A, 4B and 4Care performed. An intermediate substrate110illustrated inFIG. 8Cis formed. The intermediate substrate110ofFIG. 8Cis formed by the copper foil28and the printed wiring board of the second modified embodiment without the second conductor layer. The intermediate substrate110is separated from the support plate30. The second conductor layer34is formed from the copper foil28of the intermediate substrate110. The printed wiring board10illustrated inFIG. 1Bis completed.

Method for Manufacturing Printed Wiring Board According to Third Modified Embodiment of First Embodiment

The intermediate substrate110illustrated inFIG. 4Dis formed. The lowermost conductor layer35is formed from the copper foil28. The printed wiring board10illustrated inFIG. 5Cis completed. The printed wiring board10ofFIG. 5Cdoes not have the lowermost conductor layer35below the mounting conductor circuit (34D). However, the lowermost conductor layer35can be formed below the mounting conductor circuit (34D) from the copper foil28.

Method for Manufacturing Printed Wiring Board of Second Embodiment

As illustrated inFIG. 2B, the mounting conductor circuit (34D) and the conductor post pads (34P) are formed on the copper foil28. Thereafter, a plating resist is formed on the copper foil28, the mounting conductor circuit (34D) and the conductor post pads (34P) (FIG. 9A). The plating resist ofFIG. 2Cdoes not have an opening for forming the shield structure37. In contrast, the plating resist ofFIG. 9Ahas an opening (24S) for forming the shield structure37. The opening (24S) exposes the copper foil28between the mounting conductor circuit (34D) and the conductor post pads (34P). Then, similar toFIG. 2D, the conductor posts36and the shield structure37are simultaneously formed in the openings (24A,24S) of the plating resist. Thereafter, the processes afterFIG. 3Aare performed. The printed wiring board illustrated inFIG. 6Ais formed. By changing the shape of opening (24S), the shield structure37ofFIG. 6BorFIG. 7Bis obtained.

InFIG. 6AorFIG. 7A, an opening reaching the shield structure37is not formed in theFIG. 3C. In contrast, inFIG. 8D, an opening reaching the first shield structure371is formed inFIG. 3C. Then, inFIG. 3D, the second shield structure372is formed in the opening reaching the shield structure37.

The intermediate substrate illustrated inFIG. 3Ais prepared. The intermediate substrate has the first shield layer. Thereafter, a plating resist is formed such that the conductor posts are embedded. The opening (24S) is formed for forming the shield structure37in the plating resist (FIG. 9C). The opening (24S) ofFIG. 9Creaches the mounting conductor circuit (34D) that forms the first shield layer. The shield structure37is formed in the opening (24S) ofFIG. 9C. The height of the shield structure37is higher than the height of the conductor posts36. The plating resist ofFIG. 9Cis removed. Then, the semiconductor element90is mounted on the mounting conductor circuit (34D) via the conductive paste. The lowermost resin insulating layer50is formed on the copper foil28such that the shield structure37, the conductor posts36and the semiconductor element90are embedded. By polishing the lowermost resin insulating layer50, only the shield structure37is exposed. Thereafter, as illustrated inFIG. 3C, the openings (51f,51s) are formed. As illustrated inFIG. 3D, the via conductors (60f,60s) are formed. At that time, the first conductor layer58is formed. The first conductor layer has the first shield layer (58E) that is electrically connected to the shield structure37. Thereafter, the processes afterFIG. 4Aare performed. The printed wiring board illustrated inFIG. 6CorFIG. 7Cis completed.

In FIG. 2B of Japanese Patent Laid-Open Publication No. 2010-87085, the plating conductor is formed only on an inner wall of the through hole, and the through hole is not filled with the plating conductor. The plating conductor that is formed only on the inner wall of the through hole of Japanese Patent Laid-Open Publication No. 2010-87085 is referred to as a through hole conductor of Japanese Patent Laid-Open Publication No. 2010-87085. The through hole conductor of Japanese Patent Laid-Open Publication No. 2010-87085 penetrates two resin layers and is formed only on the inner wall of the through hole. It is likely that a thermal expansion coefficient of an electronic component and a thermal expansion coefficient of the through hole conductor of Japanese Patent Laid-Open Publication No. 2010-87085 are significantly different. Therefore, when the substrate of Japanese Patent Laid-Open Publication No. 2010-87085 with the built-in electronic component is subjected to heat cycles, reliability of connection via the through hole conductor of Japanese Patent Laid-Open Publication No. 2010-87085 is likely to be low.

A printed wiring board according to an embodiment of the present invention includes: a lowermost resin insulating layer that has a first surface and a second surface that is on an opposite side of the first surface; a semiconductor element that is embedded on the second surface side of the lowermost resin insulating layer and has an electrode that faces the first surface; a conductor post that has an upper surface and a lower surface that is on an opposite side of the upper surface, and is formed in the lowermost resin insulating layer such that the upper surface faces the first surface; a first conductor layer that is formed on the first surface; a first via conductor that is formed in the lowermost resin insulating layer and connects the first conductor layer and the conductor post; and a second via conductor that is formed in the lowermost resin insulating layer and connects the first conductor layer and the electrode.

According to an embodiment of the present invention, the first surface side and the second surface side of the lowermost resin insulating layer, in which the semiconductor element is accommodated, are connected via the conductor post and the first via conductor. A length of the first via conductor is shortened. Therefore, reliability of connection between a conductor on the first surface side and a conductor on the second surface side of the lowermost resin insulating layer, in which the semiconductor element is accommodated, is increased.