Bipolar transistor and method for manufacturing the same

A method for manufacturing a bipolar transistor includes forming a first epitaxial layer on a semiconductor substrate, forming a second epitaxial layer on the first epitaxial layer, forming an oxide layer on the second epitaxial layer, etching the oxide layer to form an opening in which the second epitaxial layer is exposed, and forming a third epitaxial layer in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity.

TECHNOLOGY FIELD

The present disclosure relates to a semiconductor device and, more particularly, to a bipolar transistor and a method for manufacturing a bipolar transistor.

BACKGROUND

A bipolar transistor is one type of device constituting a modern large-scale integrated circuit. Due to their high operating speed, large output current density, and small variation of turn-on voltage, bipolar transistors are suitable for analog circuits.

Performance requirements for semiconductor devices have increased with the steady development of semiconductor processes. Generally, in a traditional process for manufacturing a bipolar transistor (e.g., a vertical NPN transistor), an effective width of a base may be controlled by a two-step base/emitter thermal process. First, boron ions are implanted and diffused in a substrate to form a base region. Then phosphor ions are implanted and diffused in the base region to form an emitter region. The depth difference between a bottom of the base region and a bottom of the emitter region defines a width of the base.

FIGS. 1-3illustrate a conventional process for manufacturing a vertical NPN transistor. As shown inFIG. 1, a semiconductor substrate100is provided. Suitable material for semiconductor substrate100may be, for example, silicon or silicon germanium. Antimony ions are then implanted and diffused in the semiconductor substrate100to form an N-type buried layer101. Then, an N-type epitaxial layer102is formed on the N-type buried layer101using an epitaxial method.

A first photoresist layer (not shown) is then formed on the N-type epitaxial layer102and patterned by a photolithography process to define an opening in the first photoresist layer. Using the patterned first photoresist layer as an implantation mask, P-type ions are implanted and diffused in the N-type epitaxial layer102to form a base region104below the opening in the first photoresist layer. The P-type ions may be, for example, boron ions. After forming the base region104, the first photoresist layer is removed, as shown inFIG. 2.

Referring toFIG. 3, a second photoresist layer (not shown) is formed on the N-type epitaxial layer102. The second photoresist layer is patterned by a photolithography process to define an opening in the second photoresist layer. Using the patterned second photoresist layer as an implantation mask, N-type ions are implanted and diffused in the base region104, so as to form an emitter106. The remaining portion of the base region104not converted into P-type serves as the base of the transistor. The depth of the base region104is larger than that of the emitter106.

Since the emitter in an NPN transistor formed by the conventional process is surrounded by the base, an edge-crowding effect of emitter current may occur. This effect may increase a current density at an edge of the emitter, resulting in a conductive modulation effect in the base. Moreover, the edge-crowding effect in the emitter may also cause a reduction of current density in a center region of the emitter, so that the area of the emitter may not be effectively utilized.

SUMMARY OF THE DISCLOSURE

In accordance with the present disclosure, there is provided a method for manufacturing a bipolar transistor. The method comprises forming a first epitaxial layer on a semiconductor substrate, forming a second epitaxial layer on the first epitaxial layer, forming an oxide layer on the second epitaxial layer, etching the oxide layer to form an opening in which the second epitaxial layer is exposed, and forming a third epitaxial layer in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity.

In accordance with the present disclosure, there is also provided a bipolar transistor. The bipolar transistor comprises a semiconductor substrate, a first epitaxial layer formed on the semiconductor substrate, a second epitaxial layer formed on the first epitaxial layer, an oxide layer formed on the second epitaxial layer and having an opening exposing a portion of the second epitaxial layer, and a third epitaxial layer formed in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity, the first-type conductivity being different from the second-type conductivity.

Features and advantages consistent with the present disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present disclosure. Such features and advantages will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

DESCRIPTION OF THE EMBODIMENTS

FIG. 4is a flow chart illustrating a method for manufacturing a vertical NPN transistor according to one embodiment consistent with the present disclosure. The method includes the following steps:

Step S1: preparing a semiconductor substrate.

Step S2: implanting and diffusing ions in the semiconductor substrate to form an N-type buried layer.

Step S3: forming a first N-type epitaxial layer as a collector on the N-type buried layer.

Step S4: forming a P-type epitaxial layer as a base on the first N-type epitaxial layer.

Step S5: forming an oxide layer on the P-type epitaxial layer.

Step S6: forming a photoresist layer on the oxide layer.

Step S7: Patterning the photoresist layer by a photolithographic process to form a first opening in the photoresist layer.

Step S8: etching the oxide layer using the patterned photoresist layer as a mask, until the P-type epitaxial layer is exposed, so as to form a second opening in the oxide layer.

Step S9: removing the photoresist layer.

Step S10: forming a second N-type epitaxial layer as an emitter in the second opening.

FIGS. 5-7are schematic cross-sectional views illustrating different stages of the manufacturing method consistent with the present disclosure. As illustrated inFIG. 5, a semiconductor substrate200is prepared. The semiconductor substrate200may be, for example, a silicon substrate or a silicon germanium substrate. N-type ions are implanted into the semiconductor substrate200. In some embodiments, the N-type ions may be antimony ions, and the implantation may be performed at a dose in the range from about 5×1014/cm2to about 8×1014/cm2and an energy in the range from about 40 Kev to about 80 Kev. In some embodiments, an annealing process may be performed to enhance diffusion of the implanted N-type ions in the semiconductor substrate200. An N-type buried layer201is formed by the N-type ion implantation and diffusion.

After the N-type buried layer201is formed, a first N-type epitaxial layer202to act as a collector is formed on the N-type buried layer201. In some embodiments, the N-type epitaxial layer202may be formed of for example, a single crystal silicon with a thickness in the range from about 4 μm to about 5 μm. Suitable epitaxial growth methods for forming, the N-type epitaxial layer202may include, for example, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD).

After forming the N-type epitaxial layer202, a P-type epitaxial layer204to act as a base is formed on the N-type epitaxial layer202. In some embodiments, the P-type epitaxial layer204may be formed of, for example, a single crystal silicon with a thickness in the range from about 1 μm to about 3 μm. The P-type epitaxial layer204may be formed by, for example, ALD, CVD, or PECVD.

Referring toFIG. 6, an oxide layer206is then formed on the P-type epitaxial layer204. In some embodiments, the oxide layer206may be formed of a silicon-containing oxide (e.g., silicon dioxide) with a thickness in the range from about 2500 Å to 3500 Å. In some embodiments, the thickness of the oxide layer206may be about 3000 Å. In some embodiments, the oxide layer206may be formed by a CVD method or a thermal oxidation method. The oxide layer206may prevent single crystal silicon from growing outside an emitter area during subsequent selective epitaxial growth.

A photoresist layer (not shown) is then formed on the oxide layer206by, for example, a spin coating method. A photolithographic process, including an exposure process and a development process, is performed to pattern the photoresist layer to define a first opening in the photoresist layer. The oxide layer206is then etched using the patterned photoresist layer as an etching mask until the P-type epitaxial layer204is exposed, so as to form a second opening208in the oxide layer206. In some embodiments, the oxide layer206may be etched by a dry etching method or a wet etching method.

Referring toFIG. 7, a second N-type epitaxial layer210is selectively deposited in the second opening208to form an emitter. The second N-type epitaxial layer210may have a thickness substantially the same as that of the oxide layer206. In some embodiments, a selective epitaxial method may he used to form the N-type epitaxial layer210. In some embodiment, after depositing the material for the N-type epitaxial layer210, a planarization process, such as a chemical-mechanical polishing (CMP) process, may be performed to remove any residual material left on the oxide layer206.

In some embodiments, a layer containing the material for the N-type epitaxial layer210may be deposited both in the second opening208and on the oxide layer206. A planarization process, such as a CMP process, may be performed to remove the material formed on the oxide layer206until the oxide layer206is exposed.

In some embodiments, after the N-type epitaxial layer210is formed, an annealing process may be performed to diffuse the implanted ions uniformly.

A vertical NPN transistor consistent with embodiments of the present disclosure is also illustrated byFIG. 7. The transistor includes: the semiconductor substrate200; the N-type buried layer201formed in the semiconductor substrate200; the first N-type epitaxial layer202as the collector of the vertical NPN transistor formed on the N-type buried layer201; the P-type epitaxial layer204as the base of the vertical NPN transistor formed on the N-type epitaxial layer202; the oxide layer206with an opening formed therein and through the entire thickness of the oxide layer206, formed on the P-type epitaxial layer204; and the N-type epitaxial layer210formed in the opening in the oxide layer206and to act as the emitter of the NPN transistor.

Methods consistent with the present disclosure may also be used to form, for example, a vertical PNP transistor. In accordance with such a method, a semiconductor substrate is prepared first, N-type ions are implanted and diffused in the semiconductor substrate to form an N-type buried layer. A first P-type epitaxial layer is formed as a collector on the N-type buried layer. An N-type epitaxial layer is formed as a base on the first P-type epitaxial layer. An oxide layer is formed on the N-type epitaxial layer. The oxide layer is then patterned and etched until the N-type epitaxial layer is exposed to form an opening in the oxide layer. After that, a second P-type epitaxial layer as an emitter is formed in the opening.