Synchronous digital signal to asynchronous digital signal desynchronizer

Improved jitter performance is realized in a desynchronizer for obtaining an asynchronous signal, e.g., a CEPT-4 signal, from a received synchronous signal, e.g., a SDH STM-1 signal. The improved jitter performance results from employing a unique gap generator which causes gaps in a received data signal to be spread regularly in time, and allows for almost continuous control by numerical techniques of the phase of a smooth output clock being generated. Phase control is obtained by employing a filtered version of the difference between the actual number of data bits in the received digital signal and the expected nominal number.

TECHNICAL FIELD 
This invention relates to digital transmission systems and, more 
particularly, to converting synchronous digital signals to asynchronous 
digital signals. 
BACKGROUND OF THE INVENTION 
Prior desynchronizer techniques and arrangements for converting synchronous 
digital transmission signals to asynchronous digital transmission signals 
are known. In recent digital transmission systems it has become important 
to smooth large gaps in a supplied data signal resulting from overhead bit 
and stuff bit removal. This is particularly important, for example, in 
converting a Synchronous Digital Hierarchy (SDH) STM-1 155.520 Mb/s 
synchronous digital signal to a CEPT-4 139.264 Mb/s asynchronous digital 
signal. 
As is known, overhead bit removal from the SDH STM-1 signal results in 
relatively high jitter components. Additionally, it is also known that 
so-called pointer adjustments are used to reconcile phase and frequency 
differences between a clock signal derived from an incoming STM-1 signal 
and a local clock signal. These pointer adjustments are made on a 
byte-wise basis and can be either positive or negative. For example, for 
the CEPT-4 application, three bytes are used for the pointer adjustments, 
i.e., for stuffing, while for the DS3 application one byte is employed. 
During normal system operation, the pointer adjustments occur relatively 
infrequently. This causes a low frequency, relatively large peak-to-peak 
jitter component in the derived clock. When the system operation is 
degraded, pointer adjustments may occur more often. Thus, a wide range of 
pointer adjustment rates is possible. 
A so-called bit leaking technique in conjunction with a phase locked loop 
and a desynchronizing elastic store has been proposed in an attempt at 
smoothing gaps in a derived clock caused by the pointer adjustments in a 
SDH signal format. A bit leak is defined as one (1) bit of phase error 
being supplied to a phase locked loop. One of these techniques employs a 
bit-by-bit leaking adjustment so that a phase locked loop having a "wider" 
bandwidth may be employed in the desynchronizer. This bit-by-bit 
technique, however, does not adequately compensate for the full range of 
pointer adjustment rates which may occur. Attempts at compensating for the 
pointer adjustments employing adaptive bit leaking arrangements have also 
been proposed. However, to the best of my knowledge the proposed adaptive 
bit leaking arrangements still cause excessive low frequency jitter to 
occur in the asynchronous digital signal, e.g., the CEPT-4 signal, or just 
simply do not operate satisfactorily. 
SUMMARY OF THE INVENTION 
The problems associated with prior known desynchronizer arrangements are 
overcome, in accordance with the invention, by employing a unique gap 
generator arrangement which causes gaps in a received data signal to be 
spread regularly in time and, in conjunction with an arrangement for 
numerically controlling phase, allows for an almost continuous control of 
the phase of a smooth output clock being generated. 
More specifically, the gap generator yields a "smooth" gapped output clock 
having a mean frequency related to the ratio of the asynchronous digital 
signal clock frequency to the synchronous digital signal clock frequency. 
The distribution of the gaps in the gapped output clock is regular in 
time, and is independent of the distribution of the gaps resulting from 
overhead bit removal. The jitter resulting from the overhead bit removal, 
known as "mapping jitter", is thereby eliminated. 
In an embodiment of the invention, the exact instantaneous phase error of a 
received synchronous digital signal is continuously monitored and used to 
automatically generate a smooth output clock. The instantaneous phase 
error is representative of the difference between the actual number and 
nominal number of payload data bits of the received digital signal and is 
available in numerical form. Numerical techniques are advantageously 
employed to control phase of the output clock. This numerical control 
provides a well defined and readily predictable response of the 
desynchronizer to the irregularities in the received signal bit rate 
caused by the justification bits or by the pointer adjustments.

DETAILED DESCRIPTION 
Shown in the FIG. 1 is incoming signal and clock source 101 which supplies 
as outputs an incoming synchronous digital signal and its associated 
clock. In one example, the incoming digital signal is the STM-1 
Synchronous Digital Hierarchy (SDH) signal and the incoming clock is the 
STM-1 clock of 155.520 MHz. Details of the STM-1 SDH signal format are 
described in CCITT Recommendation G.707, G.708 and G.709 entitled 
"Synchronous Digital Hierarchy Bit Rates", "Network Node Interface For The 
Synchronous Digital Hierarchy" and Synchronous Multiplexing Structure", 
respectively. The mapping of the 139.264 Mb/s CEPT-4 digital signal into 
an SDH signal format is specified in the above noted CCITT Recommendation 
G.709, section 5.1.1. 
The incoming STM-1 data signal and its associated STM-1 clock are supplied 
to receiver and decoder 102. The STM-1 clock is also supplied to gap 
generator 103. Receiver and decoder 102 is employed, in this example, to 
convert the STM-1 data signal into a gapped CEPT-4 digital data signal and 
to convert the STM-1 clock into a gapped incoming clock. The gapped data 
signal denoted "incoming payload data" is written into elastic store 104 
at the gapped incoming clock rate. As is known, the gapped incoming clock 
only has clock pulses at the positions in the signal format corresponding 
to data bits since the overhead bits and stuffing bits have been removed. 
As indicated in CCITT Recommendation G.709 "payload data" is the data 
carried in the payload envelope portion of the incoming STM-1 signal. As 
explained below, the output payload data is read from elastic store 104 at 
the smooth output clock rate. In this example, the nominal smooth output 
clock rate is 139.264 MHz. 
Gap generator 103 is supplied with the incoming signal clock and is 
responsive to GAPCTRL from digital filter 105 to generate a "smooth" 
gapped output clock. The smooth gapped output clock is supplied to phase 
locked loop (PLL) 106 which, in turn, yields the desired smooth output 
clock. In the CEPT-4 application, phase locked loop 106 is an analog PLL 
which is needed to filter the residual high frequency jitter of the smooth 
output gapped clock and to filter the jitter of the incoming STM-1 clock. 
In other applications, for example, for a DS1 digital signal, use of an 
analog phase locked loop may not be necessary. The smooth output clock 
from phase locked loop 106 is supplied to a read clock input of elastic 
store 104 and as an output from the desynchronizer unit. 
Gap generator 103 operates by keeping track of the instantaneous phase 
difference between the output clock actually being generated and an ideal, 
smooth target output clock. 
Let the ratio of the nominal smooth output clock to the incoming clock be 
##EQU1## 
where N and K are relative prime numbers. Then, under nominal conditions 
the phase of the desired smooth output clock should increase by 
##EQU2## 
cycles for every cycle of the incoming clock. An incoming clock pulse is 
either passed through or blocked by gap generator 103. If an incoming 
clock pulse is passed through, the output phase increases by one (1) cycle 
and, thus, introduces a phase error of 
##EQU3## 
cycles, while a blocked pulse (=gap) creates a phase error of 
##EQU4## 
cycles. 
In the STM-1/CEPT-4 example, the incoming STM-1 clock is 155.520 MHz and 
the desired smooth output CEPT-4 clock is 139.264 MHz. Thus, the ratio is 
##EQU5## 
and, therefore, N=1215, K=127. Accordingly, under "normal" conditions the 
desired smooth gapped output clock generated by gap generator 103 should 
have 1088 cycles for 1215 cycles of the incoming clock. Consequently, 
K=127 gaps must be generated for each N=1215 cycles of the incoming clock. 
In order to spread the gaps regularly in time gap generator 103 keeps track 
of the instantaneous phase difference, called PH.sub.-- ERR hereafter, 
between the generated output clock and the ideal target output clock, and 
produces pulses or gaps in the generated output clock according to the 
value of the phase error. PH.sub.-- ERR is computed in units of 1/N cycle, 
ensuring that the accumulated phase error is tracked without roundoff 
error. 
FIG. 3 shows, in simplied form, details of gap generator 103. Specifically 
shown are select 301, adder 302, adder 303 and clock enable 304. Select 
201 is responsive to PH.sub.-- ERR to supplied either -N+K or K to adder 
302. If PH.sup.-- ERR is positive or zero, -N+K is selected via 301 and 
added via 302 to PH.sub.-- ERR, thereby decrementing it by N-K. If 
PH.sub.-- ERR is negative, K is selected via 301 and added via 302 to 
PH.sub.-- ERR, thereby incrementing it. GAPCTRL from digital filter 105 is 
added via 303 to the output of adder 302 yielding PH.sub.-- ERR which, in 
turn, is supplied to clock enable 304, select 301 and adder 302. When 
PH.sub.-- ERR is positive or zero, clock enable is disabled from supplying 
the incoming clock as an output to yield the smooth gapped output clock. 
Otherwise, clock enable 304 is enabled to supply the incoming clock as an 
output to yield the smooth gapped output clock. 
The operation of gap generator 103 can be described as follows: 
______________________________________ 
reset PH.sub.-- ERR to zero; 
for each input clock cycle do: 
if PH.sub.-- ERR is positive or zero then 
{disable output clock pulse; (.fwdarw. generate gap) 
decrement PH.sub.-- ERR by N-K} 
else 
{enable output clock pulse; (.fwdarw. generate pulse) 
increment PH.sub.-- ERR by K} 
______________________________________ 
The process described above provides a gapped output clock having a phase 
value that tracks as closely as possible the phase of the ideal continuous 
target clock. The process also provides a means to control the phase of 
the generated clock with a very high resolution. Changing the value of 
PH.sub.-- ERR changes the phase of the target clock, and thereby the phase 
of the generated output clock. PH.sub.-- ERR accumulates the phase error 
in units of 1/N cycle. Adding the value of GAPCTRL produced by digital 
filter 105 to PH.sub.-- ERR changes the phase of the ideal target clock by 
GAPCTRL/N cycles. It is noted that the value of GAPCTRL can be either 
positive or negative and, therefore, will provide either a delay or 
advance, respectively, of the generated clock. 
The basic gap generating procedure described above can be modified to 
obtain a lower repetition rate of the required arithmetic operations. In 
the CEPT-4 example the ratio of present clock pulses to gaps is 
1088/127=8.567. The phase error can therefore be computed every 8 incoming 
clock cycles instead of each clock cycle, and a one cycle gap created when 
necessary, namely: 
______________________________________ 
if PH.sub.-- ERR is positive or zero then 
{disable output clock pulse; (.fwdarw. generate gap) 
decrement PH.sub.-- ERR by N-8K (199)} 
else 
{enable output clock pulse; (.fwdarw. generate pulse) 
increment PH-ERR by 8K (1016)} 
______________________________________ 
The phase of the generated output clock can again be adjusted by adding the 
value of GAPCTRL from digital filter 105 to PH.sub.-- ERR. 
The above gap generating procedure is readily realized in gap generator 103 
of FIG. 3 by supplying -N+8K and 8K as the inputs to select 302. 
Although the above embodiment of the invention can be employed in many 
applications, it may be advantageous to employ a slightly different 
arrangement for applications in which the data rate is much lower than the 
incoming signal clock rate. One example, is a desynchronizer for 
recovering a DS1 digital signal from a STS-1 SONET signal. As is known, 
the STS-1 clock is 51.840 MHz and the DS1 rate is 1.544 Mb/sec. Thus, in 
this example, 
##EQU6## 
The embodiment of the invention described above generates a clock pulse 
after either 32 or 33 gaps. A group of 32 gaps and one clock pulse yields 
a phase error of +111, while a group of 33 gaps and one clock pulse yields 
a phase error of -82. The phase error is again computed in units of 1/N or 
in this example, 1/6480 cycle. The desired sequence can be generated by a 
counter which is controllably programmed to divide the incoming clock by 
either a divisor value of 33 or a divisor value of 34 using the following: 
______________________________________ 
INITIALIZE: PH.sub.-- ERR = 0 
BEGIN: wait for divide to complete 
if PH-ERR &gt; 0 then 
divide = 34 
PH.sub.-- ERR = PH.sub.-- ERR-82 
else 
divide = 33 
PH.sub.-- ERR = PH.sub.-- ERR + 111 
goto BEGIN 
______________________________________ 
This procedure constrains the length of the output clock period to be 
either 33 or 34 cycles of the incoming clock, and phase locked loop 106 
will not be needed in most such applications. 
The phase of the generated output clock can again be adjusted by adding the 
value of GAPCTRL from digital filter 105 to PH.sub.-- ERR. 
The primary purpose of digital filter 105 is to provide smoothing of the 
phase variations of the incoming clock caused by pointer adjustments or 
justification bits. A secondary function of digital filter 105 is to 
provide control of the filling and "centering" of elastic store 104. 
Accordingly, FIG. 2 shows, in simplified form, a functional diagram of 
digital filter 105. 
Receiver and decoder 102 generates at regular time intervals T a number 
denoted MAPDIFF. MAPDIFF is representative of the difference between the 
actual number of data bits received in interval T and the expected nominal 
number of bits. Interval T can be, for example, the STM-1 frame interval 
(125 .mu.s), i.e., a fixed portion of the received digital signal. MAPDIFF 
is readily obtained by counting the actual incoming data bits and 
comparing the result to the expected nominal number of data bits per 
frame. Under nominal conditions, each STM-1 frame includes a fixed 
predetermined number of data bits. For a CEPT-4 application, each STM-1 
frame nominally includes 17,408 CEPT-4 data bits. Because of bit 
justifications and pointer adjustments, the actual number of data bits 
differs from the nominal number, the difference being the computed 
MAPDIFF. 
As shown in FIG. 2, the MAPDIFF value from receiver and decoder 102 FIG. 1 
is multiplied via 201 by the constant factor N, in this example N=1215, 
and the result is added in accumulator 202 to ERRSUM. ERRSUM is multipled 
by constant k.sub.1 via 203 to obtain TEMP which is supplied to one input 
of adder 206. TEMP is also supplied to accumulator 204 and added to ACC2. 
In turn, ACC2 is multiplied by constant k.sub.2 via 205 and the result is 
supplied to another input of adder 206. The output of adder 206 is 
inverted via 207 to yield GAPCTRL. In turn, GAPCTRL is supplied to 
accumulator 202 and added to ERRSUM. It is noted that because of the sign 
reversal in digital filter 105, ERRSUM equals the difference between the 
phase of the write and read clocks supplied to elastic store 104, i.e., 
the filling of elastic store 104, in units of 1/N bits. Both N*MAPDIFF and 
GAPCTRL are integer numbers and their sum ERRSUM is computed without 
roundoff error. 
The sequence of operations performed by digital filter 105 can be described 
as follows: 
ERRSUM=ERRSUM+N*MAPDIFF 
TEMP=k.sub.1 *ERRSUM 
ACC2=ACC2+TEMP 
GAPCTRL=-(TEMP+k.sub.2 *ACC2) 
ERRSUM=ERRSUM+GAPCTRL 
The system function of digital filter 105, in this example, is a low pass 
function and is as follows, 
##EQU7## 
The corresponding Laplace transform for the low frequency response is 
##EQU8## 
which is the response of a standard high gain second order phase locked 
loop. The dynamic response of the digital filter is thereby completely 
defined. It is basically a low-pass filter with a 3 dB cut-off frequency 
##EQU9## 
The bandwidth of the filter is chosen to meet the output jitter 
requirements. 
As is known from phase locked loop theory, the second order phase locked 
loop provides zero phase error for a constant frequency error input. In 
the present application this property provides centering of the elastic 
store for regularly recurring pointer adjustments, i.e., degraded mode. 
In order to simplify the arithmetic operations, interger powers of 2 can 
generally be chosen for filter coefficients k.sub.1 and k.sub.2. For 
example, employing k.sub.1 =2.sup.-10 and k.sub.2 =2.sup.-16 with a 
sampling period T of 125 .mu.s yields a filter 3dB bandwidth of 1.26 Hz 
and a damping factor of 4, which are suitable for the STM-1/CEPT-4 
application.