Integration of MOSFETs in a source-down configuration

An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.

FIELD OF THE INVENTION

The present invention relates to an output stage for a switched mode power supply and, in particular, to an n-channel device which is particularly advantageous for such a stage.

BACKGROUND OF THE INVENTION

A switched mode power supply output stage is known from IR Design Tips, “High Current Buffer For Control IC's,” DT-92-2A, which shows a CMOS buffer circuit which can be used as an output power stage of a control integrated circuit or a power stage in a gate driver circuit. The output stage consists of one p-channel and one n-channel transistor (Q3and Q4) in a CMOS inverter connection. The turn-off of the output p-channel transistor (Q3) is assisted by another p-channel transistor (Q1) in a common source connection which speeds-up the discharging of the gate of the power switch (Q3). In a similar manner, a n-channel transistor (Q2) speeds-up the discharging of the gate of the output n-channel switch (Q4).

When the gate input signal is low, the speed-up transistor (Q1) is turned-on, securing a fast discharging of the gate of the p-channel MOS transistor switch (Q3) and a slower charging of the n-channel MOS transistor (Q4). The delay in turning-on the n-channel transistor switch (Q4) is determined by the RC constant formed by the resistor R1and the input capacitance of the transistor (Q4). This delay is utilized to minimize the time period when both switches are on to minimize the cross-current flowing through the output inverter (Q3and Q4).

In a similar way, when the input signal is going high, the speed-up transistor (Q2) secures a fast turn-off of the n-channel transistor switch (Q4) and a delayed turn-on of the p-channel transistor switch (Q3). This circuit enables the use of a CMOS inverter topology to provide several watts of output power, a power range where a cross-current associated with a simultaneous switching of the inverter transistors would lead to a prohibitively high power dissipation.

Utilization of speed-up transistors for allowing a hard turn-off of the power MOSFET and so minimizing the power losses related to switching events, would advantageously utilize monolithic integration of the speed-up transistors and the power switch transistors. Monolithic integration is the most effective way to minimize the parasitic inductance in the connections between the speed-up transistor and the main power switch, making the hard turn-off more effective. Vertical power MOSFET devices are usually designed with the drain electrode placed at the back-side of the die. Thus, the utilization of a technology for vertical MOSFETs, the back-side of the die acting as the source terminal would enable such monolithic integration. These devices would provide a minimum internal capacitance, and especially a minimum gate-to-drain capacitance (Cgd) which dictates the speed of the voltage transient across the transistor during switching events. The steeper the wave forms, the lower the power loss during switching.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide an improved output stage for a switched mode power supply and to provide an NMOS semiconductor device with the “source-down”.

This and other objects and features are provided, in accordance with one aspect of the invention by an output stage for a switched mode power supply having a high-side switch comprising a first power FET and a first speed-up FET, wherein the first power FET and the first speed-up FET are monolithically integrated in a first single die. A low-side switch comprises a second power FET and a second speed-up FET, wherein the second power FET and the second speed-up FET are monolithically integrated in a second single die.

Another aspect of the invention includes a semiconductor device comprising a semiconductor substrate. A first n-channel laterally diffused metal oxide semiconductor (LDMOS) transistor is formed over the semiconductor substrate. At least one second n-channel LDMOS transistor is formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate electrically coupled to said first LDMOS transistor. Second drain and gate electrodes are formed over the substrate and electrically coupled to the second LDMOS transistor. A source of the first and second LDMOS transistors is electrically connected to the substrate via an electrical conductor, wherein current in channels of the LDMOS transistors flow downwardly into the substrate. A common source electrode is electrically coupled to the substrate.

A further aspect of the invention includes a method of operating an output stage of a switched mode power supply. A high-side MOSFET switch and a low-side MOSFET switch are alternately turned on and off. At least one of the high-side MOSFET switch or the low-side MOSFET switch is driven with a speed-up FET monolithically integrated with the high-side or low-side MOSFET switch.

DETAILED DESCRIPTION

FIG. 1shows an output stage for a switched mode power supply, generally as100. The output stage is formed as a module102which has two sub-modules, a first sub-module104for the low-side driver and a second sub-module106for the high-side driver. The low-side driver has a NMOS power switch108and a NMOS speed-up transistor110. The drain112of NMOS power transistor108is connected to the output Vout and the source116is connected to ground Vgnd. The body diode118is connected as shown and the gate114is connected to the drain120of NMOS speed-up transistor110. The source124of transistor110is also connected to Vgnd. The gate122of transistor110is connected to a source of pulse width modulation signals, as is well-known in the art, Vpwm. The transistors108,110are connected in a common source configuration.

Sub-module106contains PMOS power switch150and PMOS speed-up transistor152. The source154of PMOS transistor150is connected to the source of input voltage Vin. The drain158of PMOS power transistor150is connected to the terminal Vout. The body diode160is connected as shown and the gate156is connected to the drain166of PMOS speed-up transistor152. The source162of PMOS speed-up transistor152is connected to the source of input voltage Vin. The body diode168is connected as shown and the gate164is connected to the source of pulse width modulation signals Vpwm, as well-known in the art, and connected to the gate122of NMOS speed-up transistor110. A resistor R has one end connected to the drain166of PMOS speed-up transistor152and the gate156of PMOS power transistor150. The other end of the resistor R is connected to the gate114of NMOS power switch108and the drain120of NMOS speed-up transistor110.

FIG. 2shows the sub-module104separated from the circuit shown inFIG. 1. InFIG. 2, the NMOS power transistor208and the NMOS speed-up transistor210, which correspond generally to the transistors108and110ofFIG. 1, are integrated onto a single die. The transistors208and210are integrated on die104in order to minimize the inductance between the connection of the gate214of NMOS power switch208to the drain220of the NMOS speed-up transistor210. The die comprises NMOS power transistor208, having a body diode218connected as shown, a drain which is connected outside the die and a gate connected to the drain220of NMOS speed-up transistor210. The body diode226of transistor210is connected as shown. The gate222and drain220of transistor210are connected outside the die. The source224of NMOS speed-up transistor210and the source216of NMOS power transistor208are connected in a common source configuration, with the common source being connected outside the die. These transistors are advantageously formed in a “source-down” configuration as shown and described in connection withFIG. 4herein.

FIG. 3shows the sub-module106separate from the circuit100. InFIG. 3, the PMOS power transistor350and the PMOS speed-up transistor364correspond, respectively, to the PMOS main transistor150and the PMOS speed-up transistor152ofFIG. 1, monolithically integrated onto a single die. PMOS power transistor350has its source354connected to the source362of PMOS speed-up transistor352and connected outside the die. The body diode360of transistor350is connected as shown and the gate356is connected to the drain366of PMOS speed-up transistor352. The drains358and366of transistors350and352, respectively, are connected off of the die as is the gate364of speed-up transistor352. These transistors are also connected in a common source configuration. Advantageously, the transistors are integrated on a common die in the “source-down” configuration. These transistors can advantageously be produced in accordance with the teachings of co-pending application Ser. No. 11/676,618, entitled “MOS Transistor Device and Common Source Configuration,” filed Nov. 20, 2007, which is incorporated herein by reference in its entirety. This configuration is shown and described herein with connectionFIG. 5.

FIG. 4shows a cross-section of a semiconductor implementation of the die104shown inFIG. 2. The NMOS devices built in accordance with the teachings of the present invention, are shown for voltages below 12 volts, and therefore, do not need distinguished lightly built extensions of the drain region (LDD). However, those skilled in the art recognize that such changes can be incorporated into the structure shown herein without departing from the present invention, in those cases where higher voltages are needed.

FIG. 4shows the NMOS power FET404and the NMOS speed-up FET450integrated onto the same die. The P++ substrate406contains a P+ source contact408. The substrate406will provide the source electrode for both the NMOS power switch404and the NMOS speed-up FET450. Contact408is connected via an electrically conducted material410having metallic properties such as silicide. The silicide connects to N drain extension412and to N+ source414. The drain extension412is shown as symmetrical as this reduces the cost of manufacturing, but is not required to practice the present invention. This material also provides a shielded gate structure, as shown inFIG. 4, by providing a conductive film interposed between the gate and drain terminals. The gate418is formed underneath insulator416. The P region420forms the channel to the N drain extension422and the N+ drain424. The drain is connected to the drain electrode via metallization426.

NMOS speed-up FET450has an N source extension region452and source454connected by means of a film having metal properties such as Ti, Al, W or silicide such as TiSi2or WSi2, connecting it via P+ source contact470to the P++ substrate406, forming the source contact. The film456lines a trench472, formed between the NMOS power transistor404and the NMOS speed-up transistor450. Thus, the source region is electrically shorted to the body and substrate by the contact470and trench472. A gate458is formed underneath insulator468and a P region460forms the channel underneath the gate. An N drain extension462is formed on region460, a N+ drain464is formed thereon. The drain is connected via metallization466to the drain contact for the die. It should be understood that the symmetry shown for NMOS speed-up transistor450with regard to the source extension regions and drain extension regions are not required to practice the present invention, but reduces manufacturing costs by making the doping asymmetrical. It should also be noted that the NMOS speed-up transistor has a much smaller active area than the active area of the NMOS power transistor, as will be shown more clearly in connection withFIG. 6herein.

FIG. 5shows a cross-sectional view of a semiconductor implementation of the die106shown inFIG. 3. The sub-module106comprises a PMOS R transistor504and a PMOS speed-up transistor550integrated to the same die. The transistors are formed on a N++ substrate506, having a N+ source contact508connected via an electrically conductive material510having metallic properties, such as silicide, to the P source extension region512and the P+ source514. A gate518is formed underneath insulator516over N body region520forming the channel underneath the gate. The film510, which provides the connection between the source and body regions, is also used to form a shielded gate structure as a conductive film interposed between the gate and drain terminals. P drain extension region522is formed on the N body region520and has a P+ drain region formed thereon. The drain is connected to the exterior of the die via metallization526.

The PMOS speed-up transistor550has a P source extension region552formed on a N body region560, and having a P+ source formed thereon. The source extension region552and source554are connected by a film556having metallic properties such as Ti, Al, W or silicide such as TiSi2or WSi2. The conductive film556lines trench572, separating transistors504and550. The film contacts N+ body contact region570, which makes the connection for the common source configuration. A gate558is formed underneath insulator568and a drain extension562and drain region564are formed on the body region560. A metallization566connects the drain564to the exterior of the die.

It should be noted that the shielded gate structure shown, inFIGS. 4 and 5, provides a Faraday shield between the gated drain terminals effectively reducing the Cgd capacitance. This feature is important in securing good switching performance of the power switch, as explained in more detail in U.S. Pat. No. 7,420,247, which is incorporated herein by reference in its entirety, but is not required to practice the present invention.

The fact that the substrate provides a common source electrode is a basic feature enabling monolithic integration of the vertical power MOSFETs in a common source configuration. In addition, in the structure shown inFIGS. 4 and 5, the substrate provides a source structure for both the speed-up and power transistors and the gate and drain electrodes of the speed-up transistor are connected to the application circuit. The drain electrode of the speed-up transistor is connected to the gate of the power transistor and the power transistor acts as a power switch to the current flowing between its drain and source terminals.

One feature that may be used to make the speed-up transistor more effective is to use the layout shown inFIG. 6, generally as600. This figure corresponds to FIG. 2 of the co-pending application Ser. No. 12/964,484 referred to above, except that the resistor206is not shown as it is not utilized here.FIG. 6shows the drain terminal of the power transistor602, the gate terminals of the speed-up transistor604, the gate terminal for the power transistor606, the power transistor segments608and the speed-up transistor segments610. It should be noted that the speed-up transistor segments610have the uniform distribution over the die with the segment structure of the power transistor, as illustrated inFIG. 6, which has an important advantage in providing a simultaneous, uniform hard drive to all segments of the power transistor during turn-off. It should also be noted that the speed-up transistor has a much smaller active area than the power switch transistor.

FIG. 7shows another embodiment of the present invention, generally as700. In this embodiment, a signal FET is inserted between the connection of the drain of the speed-up transistor and the gate of the power transistor. The purpose of the signal FET is to enable a stage of a switched mode power supply to be turned-off, in systems where multiple stages are utilized. It should be noted, that although a signal FET is shown in both the high-side and low-side switches, in some circuit designs, a signal FET will only be required at either the high-side or the low-side switch.

InFIG. 7, a power module702has sub-modules704and706. Sub-module704is the low-side switch having a NMOS power transistor708and NMOS speed-up transistor710. Drain712of NMOS power transistor708is connected to the output Vout. The body diode718is connected as shown and the gate714is connected to the source of NMOS signal FET728. The drain732of NMOS signal FET728is connected to the drain720of NMOS speed-up transistor710. The body diode726of transistor710is connected as shown. The drain724of NMOS speed-up transistor710and the drain716of NMOS power transistor708are connected together and connected to ground Vgnd. The drain720of NMOS speed-up transistor710is connected to one end of the resistor R. The gate722of NMOS speed-up transistor710is connected to a source of pulse width modulation signals Vpwm, as is well-known in the art. The gate730of signal NMOS FET728is connected to an enable signal Venl which turns NMOS signal FET728on or off to enable or disable the circuit of sub-module704. It should be noted that the body of NMOS signal transistor728is connected to ground instead of the usual connection to its source.

High-side switch sub-module706has PMOS power transistor750and PMOS speed-up transistor752. The source754of PMOS power transistor750is connected to the input voltage Vin. The drain758of PMOS power transistor750is connected to the output Vout. The body diode760is connected as shown and the gate756is connected to the source776of PMOS signal FET770. The drain772of PMOS signal transistor770is connected to the drain766of PMOS speed-up transistor752. The body of PMOS signal transistor770is connected to Vin at778. The body diode768of PMOS speed-up transistor752is connected as shown and the gate764is connected to a source of pulse width modulation signals Vpwm and the gate722of speed-up transistor710. The source762of PMOS speed-up transistor752is connected to Vin. The gate774of PMOS signal transistor770is connected to an enable signal Venl which will turn the transistor770off or on in order to enable or disable the sub-module706. The drain766of PMOS speed-up transistor752and the drain772of PMOS signal transistor770are connected to the other end of the resistor R.

FIG. 8shows a cross-sectional view of a semiconductor implementation of sub-module704as shown inFIG. 7, in which the NMOS power transistor and NMOS signal transistor are integrated onto the same die. The integrated device is formed on a P++ substrate806having a P+ source contact808. A film810having metallic properties such as silicide is used to make contact between source contact808, a N source extension region812and a N+ source814. A gate818is formed underneath insulator816and a P body region820is formed underneath gate818. A N drain extension region822is formed over the body region820and a drain824is formed over the drain extension region822. A metallization826is utilized to connect the drain to the exterior of the die.

A trench872is formed between the NMOS power transistor804and the NMOS signal transistor850. A film having metallic properties like Ti, Al, W, or a silicide like TiSi2or WSi2lines the trench872to make contact to the source854and source extension region852. A gate858is formed over insulator868and a drain extension region862and drain864are formed over the body820. A metallization866is used to connect the drain outside the die.

It should be noted that the source for NMOS signal FET850can be accessed in a third dimension to the output of the die. It should also be noted that the symmetry shown inFIG. 8is not necessary to practice the present invention, but is used to reduce manufacturing costs. Furthermore, the film at870could be utilized to make a connection to the NMOS speed-up FET, such as the NMOS speed-up450shown inFIG. 4, so that all three transistors could be integrated onto the same die.

FIG. 9shows a cross-section of a semiconductor implementation of sub-module706ofFIG. 7having a PMOS power FET904and a PMOS signal FET950integrated on the same die. The integrated structures is formed on a N++ substrate906having a N+ source contact908connected via a film910having metallic properties such as silicide to a P source extension region912and a P+ source914. A gate918is formed under insulator916. A N body920is formed under the gate and has a P drain extension region922and a P+ drain924formed thereon. A metallization926connects the drain to the exterior of the die.

A trench972separates the PMOS power transistor904and the PMOS signal transistor950. The trench is lined with a film having metallic properties like Ti, Al, W, or silicide like TiSi2or WSi2. The film makes a contact to a P+ source954and a P source extension region952. A gate958is formed under insulator968and a drain extension region962and drain964are formed on the N body920. A Metallization966connects the drain to the exterior of the chip.

As with the n-channel version of this circuit, described above in connection withFIG. 8, the film970can be utilized to connect to the PMOS speed-up transistor as shown inFIG. 5so that all three transistors could be integrated onto the same die. In addition, in the third dimension, the source of the PMOS signal FET can be accessed at the output. It should be noted that the film provides for a shielded gate structure interposing a conductive film between the gate and drain terminals. Also, a reverse bias can be applied to the source and drain electrodes of the signal transistor, enabling a flow-down operation of the signal transistor with respect to the source potential of the power transistor. It should also be noted that separate trench contacts are provided to pin the potential of the body region to the potential of the source region of the power transistor at selected locations of the circuit.

Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made thereto without departing from the spirit and scope of the invention as defined by the appended claims. For example, the present invention can be advantageously manufactured in accordance with the teachings of U.S. Pat. No. 7,282,765 to reduce the gate drive requirement, which is incorporated herein in its entirety by reference.