Clock and data recovery using LC voltage controlled oscillator and delay locked loop

A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application is related to U.S. application Ser. No. 12/835,130, entitled “PHASE-LOCK ASSISTANT CIRCUITRY” filed on Jul. 13, 2010, which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates generally to an integrated circuit, and more particularly to a clock and data recovery (CDR) circuit.

BACKGROUND

A Clock Data Recovery (CDR) circuit needs to track data rate variations. A conventional Phase Locked Loop (PLL)-based CDR circuit intrinsically has a limit in tracking large data rate variations. The PLL-based CDR circuit utilizes a ring Voltage Controlled Oscillator (VCO), which is not suitable for super-high data rate (e.g., higher than 25 Gbps) application, because a jitter as a large portion of a Unit Interval (UI) present in the CDR circuit adversely impacts Bit Error Rate (BER). For example, the CDR may fail to lock to data when a real data rate differs beyond a certain limit (e.g. >5000 ppm) from the expected data rate, and produce incorrect (late/early) detection of clock edge versus data edge. In addition, a chip area required for the CDR circuit and skew variations among multiple phases in the CDR circuit are important factors.

DETAILED DESCRIPTION

FIG. 1is a schematic diagram showing an exemplary clock and data recovery (CDR) circuit according to some embodiments. The CDR circuit100includes an inductor-capacitor voltage controlled oscillator (LCVCO)102including one inductor128. The CDR circuit100is configured to generate a clock signal with a clock frequency. A delay locked loop (DLL)104receives the clock signal from the LCVCO102and generates multiple clock phases, e.g., Clk0, Clk180, Clk45, Clk225, Clk90, Clk270, Clk135, and Clk315for an 8 clock phase circuit. The Clk signal numbers represents the 360° phase divided by 8, e.g., 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°. Even though 8 clock phases are provided in this example, a different number of clock phases can be provided in other embodiments.

A first timing skew averaging (TSA) circuit106receives the multiple clock phases from DLL104to supply averaged multiple clock phases, e.g., Clk0a, Clk180a, Clk45a, Clk225a, Clk90a, Clk270a, Clk135a, and Clk315a, to reduce phase errors among the multiple clock phases. A second TSA circuit108receives the averaged multiple clock phases from the first TSA circuit106to supply further averaged multiple clock phases, e.g., Clk0b, Clk180b, Clk45b, Clk225b, Clk90b, Clk270b, Clk135b, and Clk315b, to reduce phase errors among the multiple clock phases. The averaged multiple clock phases are received by the phase detector (PD)112by way of a phase lock assistant (PLA) circuit110. Even though two layers of TSA, e.g.,106and108, are used in this example, more layers can be used in other embodiments, e.g., three layers of TSA.

Data input is supplied to the PLA110, PD112, and a retime circuit126. A reference clock frequency Frefclk is supplied to a phase frequency detector (PFD)114. The PLA110, PD112, and PFD114control charge pumps116,118, and120, respectively. In one embodiment, one of the charge pumps116,118, and120supplies charges to a low pass filter122coupled to the LCVCO102at a given time, thus adjusts and controls the clock frequency of the LCVCO102. In another embodiment, the PLA110, PD112, and PFD114may share one charge pump through a multiplexer, for example.

A feedback divider (FBD)124receives the clock frequency from LCVCO102, and divides the clock frequency to supply a divided frequency Ffbd to the PFD114. A lock detector130detects if Ffbd is locked to Frefclk and generates a lock detect signal LD. With adjustment of the clock frequency of LCVCO102based on the multiple clock phases aligned with data edges of the data input, the clock signal Clk_rec from the LCVCO102is supplied to the retime circuit126as a recovered clock signal. The retime circuit126supplies a recovered data Data_rec by sampling the data input using the recovered clock signal. The operation of the CDR circuit100is further described below.

Initially, the PFD114detects and compares Frefclk and Ffbd to control the charge pump120in order to bring the Ffbd (that is obtained by dividing the clock frequency from LCVCO102by using FBD124) close to the Frefclk. (The lock detector130generates the lock detect signal LD.) After accomplishing this, the PLA110receives multiple clock phases generated from DLL. The multiple clock phases are averaged through TSA106and108that supply the averaged multiple clock phases, e.g., Clk0b, Clk180b, Clk45b, Clk225b, Clk90b, Clk270b, Clk135b, and Clk315b, to PLA110.

The PLA fine tunes the clock frequency of LCVCO102to align data edges of the received data input (e.g., falling/rising edges of the data input and the multiple clock phases) and controls the charge pump116to adjust the clock frequency of LCVCO102. After accomplishing the fine tuning, the PD112keeps tuning the clock frequency of the LCVCO102to align data edges of the received data (e.g., falling/rising edges of the data and the multiple clock phases) and controls the charge pump118to adjust the clock frequency of LCVCO102.

The PLA110and PD112correct early/late detection of the data edge triggered by the clock edge. The PLA110is needed for some applications to enable robust clock and data recovery when the data rate varies quite far from the expected data rate (e.g., greater than 5,000 ppm). The PLA110is optional, and another embodiment of the CDR circuit100does not have the PLA100. However, in some situations, using only phase detector PD112without the PLA110to phase lock the received input data and a clock phase, e.g., Clk90b, enables a data edge DE to be close to but not completely aligned with the rising (or falling) edge of clock Clk90b.

The PLA110improves the phase lock, e.g., enables the data edge DE to be (substantially) aligned with the rising (or falling) edge of the Clk90b. For example, if the Clk90bis earlier than input data, the PLA generates a “down” signal for the charge pump116to drive the LPF122to decrease the clock frequency of the LCVCO102to slow down the Clk90b, and thus improves the phase lock. But if the clock phase Clk90bis later than input data, the PLA110generates an “up” signal for the charge pump116to drive the LPF122to increase the clock frequency of the LCVCO102to speed up the Clk90, and thus improves the phase lock.

In some embodiments, if Ffbd is locked to Frefclk, the LD signal turns off the PFD114and turns on the PLA110and the PD112. But if Ffbd is not locked to Frefclk, the LD signal turns on the PFD114and turns off the PLA110and the PD112.

The CDR circuit100can be used for a high-speed (e.g., higher than 25 Gbps, up to 50 Gbps or beyond, etc.) clock data recovery (CDR) circuit application that requires a low phase noise/jitter and a low timing skew between each clock phase. By using only one inductor128(i.e., one LC-Tank) in the clock generating LCVCO102, substantial chip area is saved compared to other CDR circuits using multiple LCVCOs and inductors. Even though 8 clock phases are generated by the DLL104in this example, different number of clock phases can be generated by the DLL104in other embodiments. Also, even though two TSA circuits106and108are used in this example, more TSA circuits, e.g., three TSA circuits, can be used to reduce phase errors even more. The single clock signal output from the LCVCO minimizes the clock trace.

FIG. 2is a schematic diagram showing an exemplary timing skew averaging (TSA) circuit for the CDR circuit inFIG. 1, e.g., TSA106or108, according to some embodiments. The loads202and204are coupled to a power supply voltage VDD and controlled by a voltage Pbias. Clock phase signals clk1and clk2are supplied to the gates of NMOS transistors N1and N2, respectively. The NMOS transistor N2is connected in series with an NMOS transistor N4that is controlled by the TSA enable (TSA_en) signal. The NMOS transistor N1is connected in series with an NMOS transistor N3to balance the signal travel paths between the two paths through NMOS transistors N1and N2.

Likewise, clock phase signals clk1_b and clk2_b are supplied to the gates of NMOS transistors N5and N6, respectively. The clk1_b and clk2_b are out of phase with clk1and clk2by 180°, respectively. The NMOS transistor N6is connected in series with an NMOS transistor N8that is controlled by the TSA enable (TSA_en) signal. The NMOS transistor N5is connected in series with an NMOS transistor N7to balance the signal travel paths between the two paths through NMOS transistors N5and N6.

The clk1and clk2can be, for example, Clk0and Clk45inFIG. 1. In such an instance, clk1_b and clk2_b are Clk180and Clk225. The output signal clkout1is provided as an average of the clock phase signals of Clk0and Clk45and the output signal clkout2is provided as an average of the clock phase signals of Clk180and Clk225. A voltage Nbias controls the current through an NMOS transistor N9. The load202controls the voltage range of clkout1. Assuming the current through the load202is I1and its resistance R1, the clkout1voltage ranges from (VDD—R1×I1) to VDD. The load204controls the voltage range of clkout2. Assuming the current through the load204is12and its resistance R2, the clkout2voltage ranges from (VDD—R2×I2) to VDD.

FIG. 3is a schematic diagram showing another exemplary timing skew averaging (TSA) circuit for the CDR circuit inFIG. 1, e.g., TSA106or108, according to some embodiments. VSS is a low power supply voltage, e.g., a ground. Clock phase signal clk1is supplied to the gates of NMOS transistor N10and PMOS transistor P1. Clock phase signal clk2is supplied to the gates of NMOS transistor N12and PMOS transistor P2. The NMOS transistor N12is connected in series with an NMOS transistor N13that is controlled by the TSA enable (TSA_en) signal. The NMOS transistor N10is connected in series with an NMOS transistor N11to balance the signal travel paths between the two paths through NMOS transistors N10and N12. The PMOS transistor P2is connected in series with a PMOS transistor P4that is controlled by the TSA enable complementary (TSA_enb) signal. The PMOS transistor P1is connected in series with a PMOS transistor P3to balance the signal travel paths between the two paths through PMOS transistors P1and P2. The clk1and clk2can be, for example, Clk0and Clk45inFIG. 1. The output signal clkout is provided as an average of the clock phase signals of Clk0and Clk45.

Likewise, clock phase signals clk1_b and clk2_b are supplied to the gates of NMOS transistor N14and PMOS transistor P5and to NMOS transistor N16and PMOS transistor P6, respectively. The clk1_b and clk2_b are out of phase with clk1and clk2by 180° (i.e., complementary signals), respectively. The NMOS transistor N14is connected in series with an NMOS transistor N15that is controlled by the TSA enable (TSA_en) signal. The NMOS transistor N16is connected in series with an NMOS transistor N17to balance the signal travel paths between the two paths through NMOS transistors N14and N16. The PMOS transistor P5is connected in series with a PMOS transistor P7that is controlled by the TSA enable complementary (TSA_enb) signal. The PMOS transistor P6is connected in series with a PMOS transistor P8to balance the signal travel paths between the two paths through PMOS transistors P5and P6. The clk1and clk2can be, for example, Clk0and Clk45inFIG. 1. In such an example, the clk1_b and clk2_b are Clk180and Clk225. The output signal clkout is provided as an average of the clock phase signals of Clk0and Clk45and the output signal clkout_b is provided as an average of the clock phase signals of Clk180and Clk225.

FIG. 4is a flowchart of a method for the exemplary CDR circuit inFIG. 1according to some embodiments. At step402, a clock signal is generated with a clock frequency utilizing an inductor-capacitor voltage controlled oscillator (LCVCO). At step404, the clock signal is received from the LCVCO by a delay locked loop (DLL). At step406, the DLL generates multiple clock phases. At step408, a phase detector (PD) receives a data input and the multiple clock phases. At step410, the PD controls a first charge pump (i.e., supplies a signal to the first charge pump). At step412, the first charge pump controls the LCVCO (i.e., supplies a signal to the LCVCO). At step414, a data edge of the data input and the multiple clock phases are aligned. At step416, the clock signal from the LCVCO is supplied as a recovered clock signal.

In various embodiments, the multiple clock phases are averaged utilizing a first timing skew averaging (TSA) circuit coupled between the DLL and the PD. The multiple averaged clock phases from the first TSA circuit can be further averaged utilizing a second TSA circuit coupled between the first TSA circuit and the phase detector.

In various embodiments, a feedback divider (FBD) divides an LCVCO frequency to supply the divided frequency clock Ffbd to the PFD. A low pass filter (LPF) is coupled between the first charge pump and the LCVCO. A retime circuit coupled to the LCVCO receives the data input. The retime circuit supplies a recovered data output.

In various embodiments, a phase locked assistant (PLA) circuit receives the data input and the multiple clock phases. The PLA controls a second charge pump. The second charge pump controls the LCVCO prior to the first charge pump controlling the LCVCO.

In various embodiments, a phase frequency detector (PFD) receives a reference frequency clock Frefclk and the divided frequency clock Ffbd. The PFD controls a third charge pump. The third charge pump controls the LCVCO prior to the second charge pump controlling the LCVCO.

According to some embodiments, a clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.

According to some embodiments, a method of recovering clock and data for a clock and data recovery (CDR) circuit includes generating a clock signal with a clock frequency utilizing an inductor-capacitor voltage controlled oscillator (LCVCO). The clock signal is received from the LCVCO by a delay locked loop (DLL). The DLL generates multiple (e.g., eight) clock phases. A phase detector receives a data input and the multiple clock phases. The phase detector controls a first charge pump. The first charge pump controls the LCVCO. A data edge of the data input and the multiple clock phases are aligned. The clock signal from the LCVCO is supplied as a recovered clock signal.

The above method embodiment shows exemplary steps, but they are not necessarily required to be performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiment of the disclosure. Embodiments that combine different claims and/or different embodiments are within scope of the disclosure and will be apparent to those skilled in the art after reviewing this disclosure.