Semiconductor device having improved gate leakage current

The present invention relates to a semiconductor device having an improved gate leakage current. The semiconductor device includes: a substrate; a first nitride semiconductor layer, positioned above the substrate; a second nitride semiconductor layer, positioned above the first nitride semiconductor layer and having an energy band gap greater than that of the first nitride semiconductor layer; a source contact and a drain contact, positioned above the second nitride semiconductor layer; a doped third nitride semiconductor layer, positioned above the second nitride semiconductor layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped third nitride semiconductor layer, where the doped third nitride semiconductor layer has at least one protrusion extending along a direction substantially parallel to an interface between the first nitride semiconductor layer and the second nitride semiconductor layer, thereby improving the gate leakage current phenomenon.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a semiconductor device with a group III-V layer, two-dimensional electron gas, conductor structures, and metal layers.

2. Description of the Related Art

GaN switching power transistors can realize a new generation of small-size high-efficiency power converters. Through high switching speeds of the devices, the switching frequency can be improved to realize maintenance or even increase of the total efficiency while reducing the volume and the weight. Due to the physical properties of GaN/AlGaN materials, a high breakdown voltage and a high current level can be achieved at the same time over the small semiconductor area, and the material properties are converted into the high switching frequency at a high power level. However, many different physical effects limit the voltage tolerance performance of GaN devices. In many cases, the maximum allowable operating voltage is limited by an excessive gate leakage current. The gate leakage current refers to a current leaked to a source and/or drain from gate metal along a sidewall of a doped nitride semiconductor layer and an interface between a first nitride semiconductor layer and a passivation layer. The excessive gate leakage current may inhibit the operating voltage of a component.

Therefore, there is a need of improving gate leakage current characteristics in the field of GaN switching power transistors.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the basic features of the present invention in order to provide a basic understanding of some aspects of the present invention.

First generation semiconductor materials are elemental semiconductors with indirect energy gaps, such as silicon or germanium. Second generation semiconductor materials are represented by Group III arsenide (for example, gallium arsenide (GaAs)) compound semiconductor materials, and they have direct energy gaps, are luminous but have certain wavelength limitation, and have high pollution. Third generation semiconductors refer to wide bandgap semiconductor materials represented by Group III nitrides (for example, gallium nitride (GaN)), silicon carbide (SiC), diamond, and zinc oxide (ZnO).

With the development of wireless communication markets, such as military radar systems, personal mobile phones, and base stations, in recent years, millimeter wave transistors are becoming increasingly important. High electron mobility transistors, such as AlGaN/GaN high electron mobility transistors, made of Group III nitride materials, are always a hot research topic. Gallium nitride has a wide bandgap, a high breakdown voltage, a high peak electron velocity, a high electron saturation velocity, strong bonding force and excellent thermal stability, so the gallium nitride has the opportunity to become a main material of the next generation of power devices.

Compared with the first generation semiconductor materials of silicon (Si) and the second generation semiconductor materials of gallium arsenide (GaAs), the third generation semiconductors have the unique performance of large bandgap width, high breakdown electric field, high thermal conductivity, high electron saturation drift speed, small dielectric constant and the like, so that they show great potentials in aspects of photoelectric devices, power electronics, radio frequency (RF) and microwave power amplifiers, lasers, detection devices and the like.

Components based on the third generation semiconductors may include high electron mobility transistors (HEMTs), also known as heterojunction field effect transistors (HFETs) or modulation doped field effect transistors (MODFETs). Generally, junctions formed by using two kinds of materials with different bandgap widths, such as heterojunctions, are used instead of doped regions as channels. High electron mobility transistors get benefits from heterostructures, and use high mobility electrons generated by the heterojunctions. The heterojunctions may be formed, for example, by unintentionally doped wide bandgap layers (for example, AlGaN layers) and unintentionally doped narrow bandgap layers (for example, GaN layers).

In the AlGaN/GaN material system, due to extremely strong spontaneous polarization and piezoelectric polarization effects, unintentional doping may also form a high-concentration electron channel. Under this condition, since there is no scattering caused by donor impurities in the channel, electrons may move at a high speed, and very high electron mobility is obtained. A final result is that an electron thin layer with high concentration and high mobility is generated in the heterostructure, thereby resulting in very low channel resistivity. This is generally known as two-dimensional electron gas (2DEG). In the field effect transistors (FETs), the operation of the transistor is accomplished by changing the conductivity of this layer by applying a bias voltage to a gate electrode, and this is an advantage not found in the second generation semiconductor materials (such as gallium arsenide).

Therefore, gallium nitride may be used as the HEMT. The HEMT is better than the MESFET in the carrier concentration and electron mobility due to lower impurity scattering and lattice scattering. Therefore, the gallium nitride material is very suitable for being applied to the HEMTs and applied to high-frequency, high-power or microwave purposes.

High-frequency and high-power components need to have the characteristics of high breakdown voltage and high electron speed. In view of power amplifiers, the third generation semiconductor HEMTs have better power density than the second generation semiconductor HEMTs, so that the third generation semiconductor HEMTs conform to requirements by smaller sizes.

An AlGaN/GaN HEMT is a most general heterojunction HEMT. MOCVD or MBE is used for epitaxial growth of GaN, AlGaN and relevant structures thereof on a substrate material (such as sapphire, silicon (111) and silicon carbide) to provide materials required for preparation of the AlGaN/GaN HEMT.

The energy gap of GaN is as high as 3.39 eV, and the breakdown voltage also reaches 3.3 MV/cm. From the two points, the possibility of GaN for preventing the electronic pulse attack can be improved, and GaN can also work normally in a high-temperature environment.

The technology of growing gallium nitride on a silicon carbide or sapphire substrate is very mature, and the grown gallium nitride has good crystallization quality and low surface defect density. However, the silicon carbide or sapphire substrate is expensive and difficult to process, so that a semiconductor device based on the silicon carbide or sapphire substrate is difficult to realize mass production or manufacturing cost reduction. Based on the above disadvantages, GaN-on-Si is a process development trend in recent years. The silicon substrate has the cost advantages, and GaN-on-Si is also compatible with a modern silicon semiconductor manufacturing process. However, the difference in thermal expansion coefficients of gallium nitride and silicon is as high as 34%, so that epitaxial film breaking or silicon substrate bending deformation is caused during growth of a crystal film or at the room temperature. The surface defect density of the epitaxial film is high due to poor crystallization quality of the epitaxial film, so that a leakage current of about 10−12A/mm to about 10−8A/mm may be generated when the operating voltage of a GaN-on-Si HEMT at a gate is 5 V to 6 V. However, it is found that, when the GaN-on-Si HEMT is used for a circuit such as a comparator or an oscillator, the gate leakage current of about 10−12A/mm to about 10−8A/mm still causes earlier breakdown at the operating voltage of 6 V to 8 V and system power consumption of about 10 Watt, thereby reducing the system efficiency by about 5%. Such reduction in the system efficiency does not conform to the industry standard, and in the switch application, severe problems such as abnormal operation and poor efficiency are caused. Therefore, an urgent requirement of reducing the gate leakage current exists in the related technical field.

Moreover, it is known that the magnitude of the leakage current is mainly related to the quality of the epitaxial film growing on a substrate, and different dies on the same substrate or different switching elements of the same integrated circuit generally have substantially identical gate leakage current. Additionally, the gate leakage current may be subdivided into gate-to-source leakage current (Jgs) and gate-to-drain leakage current (Jgd). In conventional devices with symmetrical gate structures, Jgsand Jgdhave similar magnitudes. It has been found that when the HEMTs are applied to an upper tube of a buck circuit in an on-board charger (OBC), it is generally desirable to minimize Jgdto reduce the power consumption of Cgdin a charging process. On the other hand, when the HEMTs are applied to LLC resonant converters in adapters, it is generally desirable to minimize Jgsto optimize the charging time for Cgs, thereby further reducing the delay of the circuit. Based on this, there are the following requirements in the art: 1) the requirement of modulating the magnitude of leakage current of different dies on the same wafer; 2) the requirement of modulating the magnitude of leakage current of different switching elements in the same integrated circuit; or 3) the requirement of independently modulating the magnitudes of Jgsand Jgdin the HEMT devices.

In various embodiments, the present invention provides precisely designed HEMT gate structures. The gate structures effectively improve the gate leakage current characteristics of the HEMT devices, thereby achieving the requirement of reducing the gate leakage current, the requirement of independently modulating the magnitude of the leakage current of each die or switching elements, or the requirement of independently modulating the magnitudes of Jgsand Jgd.

Some embodiments of the present invention provide a semiconductor device, including a substrate; a first nitride semiconductor layer, positioned above the substrate; a second nitride semiconductor layer, positioned above the first nitride semiconductor layer and having an energy band gap greater than that of the first nitride semiconductor layer; a source contact and a drain contact, positioned above the second nitride semiconductor layer; a doped third nitride semiconductor layer, positioned above the second nitride semiconductor layer and between the drain contact and the source contact, where the doped third nitride semiconductor layer has a first sidewall adjacent to the source contact, a second sidewall adjacent to the drain contact, and a third sidewall positioned between the first sidewall and the second sidewall in a direction substantially parallel to an interface between the first nitride semiconductor layer and the second nitride semiconductor layer; and a gate electrode, positioned above the doped third nitride semiconductor layer.

Some other embodiments of the present invention provide a semiconductor device, including a substrate; a first nitride semiconductor layer, positioned above the substrate; a second nitride semiconductor layer, positioned above the first nitride semiconductor layer and having an energy band gap greater than that of the first nitride semiconductor layer; a source contact and a drain contact, positioned above the second nitride semiconductor layer; a doped third nitride semiconductor layer, positioned above the second nitride semiconductor layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped third nitride semiconductor layer, where the doped third nitride semiconductor layer has a first surface in contact with the gate electrode, a second surface in contact with the second nitride semiconductor layer, and a third surface positioned between the first surface and the second surface in a direction substantially perpendicular to an interface between the first nitride semiconductor layer and the second nitride semiconductor layer, and the third surface extends in a direction substantially parallel to the interface between the first nitride semiconductor layer and the second nitride semiconductor layer.

Some other embodiments of the present invention provide a semiconductor device, including a substrate; a first nitride semiconductor layer, positioned above the substrate; a second nitride semiconductor layer, positioned above the first nitride semiconductor layer and having an energy band gap greater than that of the first nitride semiconductor layer; a source contact and a drain contact, positioned above the second nitride semiconductor layer; a doped third nitride semiconductor layer, positioned above the second nitride semiconductor layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped third nitride semiconductor layer, where the doped third nitride semiconductor layer has at least one protrusion extending along a direction substantially parallel to an interface between the first nitride semiconductor layer and the second nitride semiconductor layer.

Unexpectedly, the present invention may effectively improve the gate leakage current phenomenon of the HEMT device through the precisely designed gate structure, and the magnitudes of the gate-to-source leakage current (Jgs) and the gate-to-drain leakage current (Jgd) may even be separately adjusted as required.

PREFERRED EMBODIMENT OF THE PRESENT INVENTION

To make the figures clear and concise, unless otherwise specified, the same reference numerals in different figures indicate the same components. In addition, to simplify the description, descriptions and details of well-known steps and components may be omitted. Although devices may be described herein as some n-channel or p-channel devices or some n-type or p-type doping devices, it is found through effortful research that, the present invention may also be applied to complementary devices. The word “substantially” or “basically” used herein means that a value of a component has a parameter that is expected to be close to a stated value or position. However, as is well known in the art, there are always small differences that prevent a value or position from being exactly the stated value or position. It is acknowledged in the art that a deviation of up to at least ten percent (10%) (and even to twenty percent (20%) for some components including semiconductor doping concentrations) is a reasonable deviation from an ideal target exactly as described. The terms “first”, “second”, “third”, and the like (as used in part of a component name) in the claims and/or specific embodiments are used to distinguish similar components, and do not necessarily describe an order in time, space, rank, or any other way. It should be understood that, such terms may be interchanged under appropriate circumstances, and the embodiments described herein may be operated in other orders than that described or exemplified herein. The phrase “some embodiments” means that specific features, structures, or characteristics described in combination with the embodiments are included in at least one embodiment of the present invention. Therefore, the phrase “in some embodiments” appearing at different positions throughout this specification does not necessarily refer to the same embodiment, but in some cases, may refer to the same embodiment. In addition, it is apparent to a person of ordinary skill in the art that, in one or more embodiments, specific features, structures, or characteristics may be combined in any appropriate manner.

In this specification, the so-called “normal direction” refers to a normal direction of an interface between a first nitride semiconductor layer and a second nitride semiconductor layer of an HEMT device; in some cases, the “normal direction” may alternatively be a normal direction of a flowing direction of two-dimensional electron gas of an HEMT device; and in some cases, the “normal direction” may alternatively be a stacking direction of epitaxial layers. The so-called “tangential direction” refers to a tangential direction of an interface between a first nitride semiconductor layer and a second nitride semiconductor layer of an HEMT device; in some cases, the “tangential direction” may alternatively be a tangential direction of a flowing direction of two-dimensional electron gas of an HEMT device; and in some cases, the “tangential direction” alternatively refers to a direction along a connecting line between a source contact and a drain contact of an HEMT device.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Certainly, the descriptions are merely examples and are not intended to be limiting. In this application, in the following descriptions, the description of the first feature being formed on or above the second feature may include an embodiment formed by direct contact between the first feature and the second feature, and may further include an embodiment in which an additional feature may be formed between the first feature and the second feature to enable the first feature and the second feature to be not in direct contact. In addition, in this application, reference numerals and/or letters may be repeated in examples. This repetition is for the purpose of simplification and clarity, and does not indicate a relationship between the described various embodiments and/or configurations.

The embodiments of the present invention are described in detail below. However, it should be understood that many applicable concepts provided by the present invention may be implemented in a plurality of specific environments. The described specific embodiments are only illustrative and do not limit the scope of the present invention.

FIG.1(a)shows an HEMT device1aaccording to some embodiments of the present invention. The structure is drawn on a tangent plane substantially along a connecting line between a source contact6and a drain contact7, where the x direction is a tangential direction in this specification; and they direction is a normal direction in this specification.

Generally, the HEMT device is constructed on a substrate2. A nitride semiconductor layer4and a nitride semiconductor layer5are arranged on the substrate2. The nitride semiconductor layer5and the nitride semiconductor layer4are configured to form two-dimensional electron gas (2DEG)41in the nitride semiconductor layer4along an interface between the nitride semiconductor layer4and the nitride semiconductor layer5. Therefore, the nitride semiconductor layer4may be considered as a channel layer of the HEMT device, and the nitride semiconductor layer5may be considered as a barrier layer of the HEMT device. The source contact6, a gate structure80, and the drain contact7are additionally arranged on the nitride semiconductor layer5. The gate structure80is positioned between the source contact6and the drain contact7substantially along the tangential direction, and includes a doped nitride semiconductor layer8and a gate electrode9.

The substrate2may include, but is not limited to, silicon (Si), doped silicon (doped Si), gallium nitride, zinc oxide, silicon carbide (SiC), silicon germanium (SiGe), gallium arsenide (GaAs), sapphire, silicon on an insulator (SOI), or other suitable materials, preferably silicon. The substrate2may also include a doped region (not shown in the figure), for example, p-well and/or n-well. The substrate2has an active layer and a back layer opposite to the active layer. An integrated circuit may be formed above the active layer.

As mentioned above, the gate leakage current in the state of the art still cannot meet requirements such as high gate breakdown voltage and low system power consumption on a circuit such as a comparator or an oscillator. The inventors have found that, the gate leakage current phenomenon may be improved through a technical measure of improving the geometric contour of a sidewall adjacent to a source or drain of a doped nitride semiconductor layer of the present invention, thereby achieving the goals of reducing the gate leakage current, and reducing the system power consumption; and improving the gate breakdown voltage, and improving the device reliability.

Moreover, a leakage current Jgdbetween a source and a drain determines the power consumption of Cgd. The inventors of this application have unexpectedly found that the magnitude of Jgdmay be modulated by precisely designing the geometric contour of the gate structure80. The inventors have found that under the condition that the total gate leakage current cannot be further reduced due to the limitation by a manufacturing process technology, a proportion between Jgdand Jsdmay be regulated by a technical measure of changing the symmetry of the gate structure of the present invention, thereby achieving the effects of increasing Jgs, reducing Jgdand decreasing Cgd, and further achieving the goal of reducing the power consumption of Cgd.

On the other hand, a leakage current Jgsbetween the gate and the source determines the charging time of Cgs. Therefore, under the condition that the total gate leakage current cannot be further reduced due to the limitation by the manufacturing process technology, a proportion between Jgdand Jsdmay be regulated by a technical measure of changing the symmetry of the gate structure of the present invention, thereby achieving the effects of increasing Jgd, reducing Jgsand decreasing the charging time of Cgs, and further achieving the goal of reducing the circuit delay.

Therefore, on the tangent plane substantially along the connecting line between the source contact6and the drain contact7, relative to the geometric center83of the doped nitride semiconductor layer, the doped nitride semiconductor layer may substantially have a non-mirror-symmetric shape.

Having generated a practical channel (electron channel region) under the gate electrode9, the nitride semiconductor layer4is preset to be in an ON state when the gate electrode9is in a zero-bias state. Such a device may also be known as a depletion mode device.

An enhancement mode device is contrary to the depletion mode device. The enhancement mode device is preset to be in an OFF state when the gate electrode9is in the zero-bias state. To form the enhancement mode device, the doped nitride semiconductor layer8is necessarily disposed between the gate electrode9and the nitride semiconductor layer5so as to deplete or remove part of the two-dimensional electron gas41.

The doped nitride semiconductor layer8and the nitride semiconductor layer4may form a pn junction used to deplete the two-dimensional electron gas41. Since the pn junction depletes the two-dimensional electron gas41, when the gate electrode9is in the zero-bias state, no current passes through the HEMT device1a, i.e., a threshold voltage of the HEMT device1ais a positive value. The doped nitride semiconductor layer8is favorable for reducing the leakage current, and increasing the threshold voltage.

The gate electrode9may be used as a stop layer or a protective layer to protect the whole top surface of the doped nitride semiconductor layer8, so that the surface of the doped nitride semiconductor layer8cannot generate bulges or recesses (or relatively uneven surfaces) due to the removal operation (such as etching).

FIG.1(b)toFIG.1(l)show one or more embodiments of a gate structure80in a dotted box inFIG.1(a):

As shown inFIG.1(b), the gate structure80of the present invention may include a doped nitride semiconductor layer8and a gate electrode9, and the doped nitride semiconductor layer8may have a surface84and a surface85. The surface84may include a part84aelectrically connected to the gate electrode, and a part84band a part84cadjacent to the part84a. The part84aof the doped nitride semiconductor layer8may be in contact with the gate electrode9. The part84band the part84cmay be in direct contact with a passivation layer (not shown inFIG.1(a)toFIG.1(l)) of the HEMT device. The surface85may be in contact with the nitride semiconductor layer5. Substantially along the tangential direction, the geometric center93of the gate electrode9may be aligned with the geometric center84dof the surface84. Substantially along the tangential direction, the geometric center93of the gate electrode9may be aligned with the geometric center84dof the part84aof the surface84.

The doped nitride semiconductor layer8has a protrusion adjacent to the source contact6, and this protrusion extends toward the source contact6along the tangential direction. Therefore, a sidewall81of the doped nitride semiconductor layer8forms a one-step shaped contour line, which sequentially includes interfaces such as a sidewall81a, a surface86, and a sidewall81b. In this aspect, the doped nitride semiconductor layer8has the sidewall81aadjacent to the source contact6and a sidewall82adjacent to the drain contact7, and the sidewall81bpositioned between the sidewall81aand the sidewall82substantially along the tangential direction, and the sidewall81bis positioned between the sidewall81aand the gate electrode9substantially along the tangential direction. The doped nitride semiconductor layer8may have the surface86positioned between the surface84and the surface85substantially along the normal direction, and the surface86may be positioned between the gate electrode9and the source contact6in a direction substantially parallel to the tangential direction, and extend toward the source contact6.

The doped nitride semiconductor layer8only has the protrusion adjacent to the source contact6. Therefore, on the tangent plane substantially along the connecting line between the source contact6and the drain contact7, the doped nitride semiconductor layer8is a non-mirror-symmetric structure relative to the geometric center83thereof. In this aspect, the leakage current Jgsbetween the gate and the source is less than the leakage current Jgdbetween the gate and the drain.

Substantially along the normal direction, a ratio of the height of the sidewall81bto that of the sidewall81amay be 0.5 to 2, for example, but not limited to: 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2.

Substantially along the tangential direction, a ratio of a shortest distance between the gate electrode9and the sidewall81ato a shortest distance between the gate electrode9and the sidewall82may be greater than 1, for example, but not limited to: 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4 or 2.5; and the ratio of the shortest distance between the gate electrode9and the sidewall81ato the shortest distance between the gate electrode9and the sidewall82may not exceed 4, for example, but not limited to: 4, 3.9, 3.8, 3.7, 3.6, 3.5, 3.4, 3.3, 3.2, 3.1, 3, 2.9, 2.8, 2.7, 2.6, or 2.5. For example, the shortest distance between the gate electrode9and the sidewall81amay be d1, the shortest distance between the gate electrode9and the sidewall82may be d2, where d1/d2may be greater than 1. In some embodiments, the shortest distance between the gate electrode9and the sidewall81amay be a shortest distance between a center line of the gate electrode9substantially parallel to the normal direction and the sidewall81ain the tangential direction, and the shortest distance between the gate electrode9and the sidewall82may be a shortest distance between the center line of the gate electrode9substantially parallel to the normal direction and the sidewall82in the tangent direction.

In the tangential direction, a ratio of the width of the surface86to the width of the surface84may be 0.05 to 0.2, for example, but not limited to: 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19 or 0.2. For example, the width of the surface86may be w1, and the width of the surface84may be w2, where w1/w2may be 0.05 to 0.2.

In the tangential direction, a ratio of the width of the surface86to the width of the surface85may be 0.02 to 0.15, for example, but not limited to: 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, or 0.15. For example, the width of the surface86may be w1, and the width of the surface85may be w3, where w1/w3may be 0.02 to 0.15.

The sidewall81aof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall82of the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall81bof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The surface86of the doped nitride semiconductor layer8may be in direct contact with the passivation layer.

If the part84bof the surface84of the doped nitride semiconductor layer8exists, the part84bmay be in direct contact with the passivation layer. If the part84cof the surface84of the doped nitride semiconductor layer8exists, the part84cmay be in direct contact with the passivation layer.

The gate structure80shown inFIG.1(c)is substantially the same as that inFIG.1(b). A difference lies in that, the protrusion of the doped nitride semiconductor layer8is positioned adjacent to the drain contact7rather than adjacent to the source contact6, and this protrusion extends toward the drain contact7along the tangential direction. Therefore, the sidewall82of the doped nitride semiconductor layer8forms a one-step shaped contour line, which sequentially includes interfaces such as a sidewall82a, a surface87and a sidewall82b. In this aspect, the doped nitride semiconductor layer8has the sidewall81adjacent to the drain contact7and the sidewall82aadjacent to the drain contact, and the sidewall82bpositioned between the sidewall81and the sidewall82asubstantially along the tangential direction, and the sidewall82bis positioned between the gate electrode9and the sidewall82asubstantially along the tangential direction. The doped nitride semiconductor layer8has the surface87positioned between the surface84and the surface85substantially along the normal direction, and the surface87is positioned between the gate electrode9and the drain contact7in a direction substantially parallel to the tangential direction, and extends toward the drain contact7.

The doped nitride semiconductor layer8only has the protrusion adjacent to the drain contact7. Therefore, on the tangent plane substantially along the connecting line between the source contact6and the drain contact7, the doped nitride semiconductor layer8is a non-mirror-symmetric structure relative to the geometric center83thereof. In this aspect, the leakage current Jgdbetween the gate and the drain is less than the leakage current Jgsbetween the gate and the source.

Substantially along the normal direction, a ratio of the height of the sidewall82bto that of the sidewall82amay be 0.5 to 2, for example, but not limited to: 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2.

Substantially along the tangential direction, a ratio of a shortest distance between the gate electrode9and the sidewall82ato a shortest distance between the gate electrode9and the sidewall81may be greater than 1, for example, but not limited to: 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4 or 2.5; and the ratio of the shortest distance between the gate electrode9and the sidewall82ato the shortest distance between the gate electrode9and the sidewall81may not exceed 4, for example, but not limited to: 4, 3.9, 3.8, 3.7, 3.6, 3.5, 3.4, 3.3, 3.2, 3.1, 3, 2.9, 2.8, 2.7, 2.6, or 2.5. For example, the shortest distance between the gate electrode9and the sidewall82amay be d3, the shortest distance between the gate electrode9and the sidewall81may be d4, where d3/d4may be greater than 1. In some embodiments, the shortest distance between the gate electrode9and the sidewall82amay be a shortest distance between a center line of the gate electrode9substantially parallel to the normal direction and the sidewall82ain the tangential direction, and the shortest distance between the gate electrode9and the sidewall81may be a shortest distance between the center line of the gate electrode9substantially parallel to the normal direction and the sidewall81in the tangent direction.

In the tangential direction, a ratio of the width of the surface87to the width of the surface84may be 0.05 to 0.2, for example, but not limited to: 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19 or 0.2.

In the tangential direction, a ratio of the width of the surface87to the width of the surface85may be 0.02 to 0.15, for example, but not limited to: 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, or 0.15.

The sidewall81of the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall81aof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall82bof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The surface87of the doped nitride semiconductor layer8may be in direct contact with the passivation layer.

If the part84bof the surface84of the doped nitride semiconductor layer8exists, the part84bmay be in direct contact with the passivation layer. If the part84cof the surface84of the doped nitride semiconductor layer8exists, the part84cmay be in direct contact with the passivation layer.

The gate structure80shown inFIG.1(d)is substantially the same as that inFIG.1(b)orFIG.1(c). A difference lies in that, the doped nitride semiconductor layer8has a protrusion that is adjacent to the source contact6and extends toward the source contact6along the tangential direction, and at the same time has another protrusion that is adjacent to the drain contact7and extends toward the drain contact7along the tangential direction. Therefore, the sidewall81of the doped nitride semiconductor layer8forms a one-step shaped contour line, which sequentially includes interfaces such as a sidewall81a, a surface86and a sidewall81b; and the sidewall82of the doped nitride semiconductor layer8forms a one-step shaped contour line, which sequentially includes interfaces such as a sidewall82a, a surface87and a sidewall82b. In this aspect, the doped nitride semiconductor layer8has the sidewall81aadjacent to the source contact6and a sidewall82aadjacent to the drain contact, and the sidewall81band the sidewall82bpositioned between the sidewall81aand the sidewall82asubstantially along the tangential direction; and substantially along the tangential direction, the sidewall81bis positioned between the sidewall81aand the gate electrode9and the sidewall82bis positioned between the gate electrode9and the sidewall82a. The doped nitride semiconductor layer8may have the surface86and the surface87positioned between the surface84and the surface85substantially along the normal direction; and in a direction substantially parallel to the tangential direction, the surface86is positioned between the gate electrode9and the source contact6and extends toward the source contact6, and the surface87is positioned between the gate electrode9and the drain contact7and extends toward the drain contact7.

The doped nitride semiconductor layer8may be a non-mirror-symmetric structure or mirror-symmetric structure relative to the geometric center83thereof.

Substantially along the normal direction, a ratio of the height of the sidewall81bto that of the sidewall81amay be 0.5 to 2, for example, but not limited to: 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2; and a ratio of the height of the sidewall82bto that of the sidewall81amay be 0.5 to 2, for example, but not limited to: 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2. The sidewall81aand the sidewall82amay have the same height. The sidewall81aand the sidewall82amay have different heights. The sidewall81band the sidewall82bmay have the same height. The sidewall81band the sidewall82bmay have different heights.

Substantially along the tangential direction, a ratio of a shortest distance between the gate electrode9and the sidewall81ato a shortest distance between the gate electrode9and the sidewall82amay be greater than or equal to 1, for example, but not limited to: 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4 or 2.5; and the ratio of the shortest distance between the gate electrode9and the sidewall81ato the shortest distance between the gate electrode9and the sidewall82amay not exceed 4, for example, but not limited to: 4, 3.9, 3.8, 3.7, 3.6, 3.5, 3.4, 3.3, 3.2, 3.1, 3, 2.9, 2.8, 2.7, 2.6, or 2.5. In this aspect, the leakage current Jgsbetween the gate and the source is less than the leakage current Jgdbetween the gate and the drain.

In some embodiments, substantially along the tangential direction, a ratio of a shortest distance between the gate electrode9and the sidewall82ato a shortest distance between the gate electrode9and the sidewall81ais greater than or equal to 1, for example, but not limited to: 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4 or 2.5; and in some cases, the ratio of the shortest distance between the gate electrode9and the sidewall81ato the shortest distance between the gate electrode9and the sidewall82does not exceed 4, for example, but not limited to: 4, 3.9, 3.8, 3.7, 3.6, 3.5, 3.4, 3.3, 3.2, 3.1, 3, 2.9, 2.8, 2.7, 2.6, or 2.5. In this aspect, the leakage current Jgdbetween the gate and the drain is less than the leakage current Jgsbetween the gate and the source.

Substantially along the tangential direction, a ratio of a shortest distance between the gate electrode9and the sidewall81bto a shortest distance between the gate electrode9and the sidewall82bmay be greater than or equal to 1, for example, but not limited to: 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2; and the ratio of the shortest distance between the gate electrode9and the sidewall81bto the shortest distance between the gate electrode9and the sidewall82bmay not exceed 3, for example, but not limited to: 3, 2.9, 2.8, 2.7, 2.6, 2.5, 2.4, 2.3, 2.2, 2.1 or 2. In this aspect, the leakage current Jgsbetween the gate and the source is less than the leakage current Jgdbetween the gate and the drain.

Substantially along the tangential direction, a ratio of a shortest distance between the gate electrode9and the sidewall82bto a shortest distance between the gate electrode9and the sidewall81bmay be greater than or equal to 1, for example, but not limited to: 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2; and the ratio of the shortest distance between the gate electrode9and the sidewall81bto the shortest distance between the gate electrode9and the sidewall82bmay not exceed 3, for example, but not limited to: 3, 2.9, 2.8, 2.7, 2.6, 2.5, 2.4, 2.3, 2.2, 2.1 or 2. In this aspect, the leakage current Jgdbetween the gate and the drain is less than the leakage current Jgsbetween the gate and the source.

In the tangential direction, a ratio of the width of the surface86to the width of the surface84may be 0.05 to 0.2, for example, but not limited to: 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19 or 0.2.

In the tangential direction, a ratio of the width of the surface86to the width of the surface85may be 0.02 to 0.15, for example, but not limited to: 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, or 0.15.

In the tangential direction, a ratio of the width of the surface87to the width of the surface84may be 0.05 to 0.2, for example, but not limited to: 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19 or 0.2.

In the tangential direction, a ratio of the width of the surface87to the width of the surface85may be 0.02 to 0.15, for example, but not limited to: 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, or 0.15.

The sidewall81aof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall82aof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall81bof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall82bof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The surface86of the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The surface87of the doped nitride semiconductor layer8may be in direct contact with the passivation layer.

If the part84bof the surface84of the doped nitride semiconductor layer8exists, the part84bmay be in direct contact with the passivation layer. If the part84cof the surface84of the doped nitride semiconductor layer8exists, the part84cmay be in direct contact with the passivation layer.

According to some aspects of the present invention, on the tangent plane substantially along the connecting line between the source contact6and the drain contact7, an angle between any tangent plane of the sidewall81of the doped nitride semiconductor layer8and the tangential direction may be 30° to 150°; and an angle between the tangential direction and a connecting line between an intersection of the sidewall81and the surface84and an intersection of the sidewall81and the surface85may be 30° to 150°, for example, but not limited to: 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°, 90°, 95°, 100°, 105°, 110°, 115°, 120°, 125°, 130°, 135°, 140°, 145° or 150°.

An angle between any tangent plane of the sidewall82and the tangential direction may be 30° to 150°; and an angle between the tangential direction and a connecting line between an intersection of the sidewall82and the surface84and an intersection of the sidewall82and the surface85may be 30° to 150°, for example, but not limited to: 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°, 90°, 95°, 100°, 105°, 110°, 115°, 120°, 125°, 130°, 135°, 140°, 145° or 150°.

An angle between any tangent plane of the sidewall81aand the tangential direction may be 30° to 150°; and an angle between the tangential direction and a connecting line between an intersection of the sidewall81aand the surface86and an intersection of the sidewall81aand the surface85may be 30° to 150°, for example, but not limited to: 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°, 90°, 95°, 100°, 105°, 110°, 115°, 120°, 125°, 130°, 135°, 140°, 145° or 150°.

An angle between any tangent plane of the sidewall82aand the tangential direction may be 30° to 150°; and an angle between the tangential direction and a connecting line between an intersection of the sidewall82aand the surface87and an intersection of the sidewall81aand the surface85may be 30° to 150°, for example, but not limited to: 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°, 90°, 95°, 100°, 105°, 110°, 115°, 120°, 125°, 130°, 135°, 140°, 145° or 150°.

An angle between any tangent plane of the sidewall81band the tangential direction may be 30° to 150°; and an angle between the tangential direction and a connecting line between an intersection of the sidewall81band the surface84and an intersection of the sidewall81band the surface86may be 30° to 150°, for example, but not limited to: 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°, 90°, 95°, 100°, 105°, 110°, 115°, 120°, 125°, 130°, 135°, 140°, 145° or 150°.

An angle between any tangent plane of the sidewall82band the tangential direction may be 30° to 150°; and an angle between the tangential direction and a connecting line between an intersection of the sidewall82band the surface84and an intersection of the sidewall82band the surface87may be 30° to 150°, for example, but not limited to: 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°, 90°, 95°, 100°, 105°, 110°, 115°, 120°, 125°, 130°, 135°, 140°, 145° or 150°.

In the tangential direction, the orthographic projection range of the sidewall81, the sidewall82, the sidewall81a, the sidewall82a, the sidewall81bor the sidewall82bof the doped nitride semiconductor layer8may not overlap the surface84; or the orthographic projection range of the sidewall81, the sidewall82, the sidewall81a, the sidewall82a, the sidewall81bor the sidewall82bmay overlap the surface84.

In the tangential direction, the orthographic projection range of the sidewall81, the sidewall82, the sidewall81a, the sidewall82a, the sidewall81bor the sidewall82bmay not overlap the surface85; or the orthographic projection range of the sidewall81, the sidewall82, the sidewall81a, the sidewall82a, the sidewall81bor the sidewall82bmay overlap the surface85.

In the tangential direction, the orthographic projection range of the surface86of the doped nitride semiconductor layer8may not overlap the surface84; or the orthographic projection range of the surface86may overlap the surface84.

In the tangential direction, the orthographic projection range of the surface86may not overlap the surface85; or the orthographic projection range of the surface86may overlap the surface85.

In the tangential direction, the orthographic projection range of the surface87may not overlap the surface84; or the orthographic projection range of the surface87may overlap the surface84.

In the tangential direction, the orthographic projection range of the surface87may not overlap the surface85; or the orthographic projection range of the surface87may overlap the surface85.

In the tangential direction, the orthographic projection range of the sidewall81aof the doped nitride semiconductor layer8may overlap the surface86. The orthographic projection range of the sidewall81bmay overlap the surface86. The orthographic projection range of the sidewall81amay not overlap the surface86. The orthographic projection range of the sidewall81bmay not overlap the surface86.

In the tangential direction, the orthographic projection range of the sidewall82amay overlap the surface87. The orthographic projection range of the sidewall82bmay overlap the surface87. The orthographic projection range of the sidewall82amay not overlap the surface87. The orthographic projection range of the sidewall82bmay not overlap the surface87.

The inventors have unexpectedly found that, when a sidewall of the doped nitride semiconductor layer8deviates from the normal direction, the gate leakage current phenomenon of the HEMT device may be effectively improved. For example, as shown inFIG.1(e), the gate structure80in the figure is substantially the same as that inFIG.1(b). A difference lies in that, an angle between the tangential direction and a connecting line between an intersection of the sidewall81band the surface84and an intersection of the sidewall81band the surface86is less than 80°.

FIG.1(f)shows an enlarged view in a dotted box inFIG.1(e), where an angle between the tangential direction and a connecting line between an intersection of the sidewall81band the surface84of the doped nitride semiconductor layer8and an intersection of the sidewall81band the surface86is α, and α<80°; an angle between the tangential direction and a connecting line between an intersection of the sidewall81aand the surface86and an intersection of the sidewall81aand the surface85is β, and β>80′; and an angle between the tangential direction and a connecting line between an intersection of the sidewall82and the surface84and an intersection of the sidewall82and the surface85is θ, and θ>80°.

The inventors have unexpectedly found that, compared with the structure inFIG.1(b), the structure inFIG.1(e)may further suppress the leakage current Jgsbetween the gate and the source, thereby further improving the gate leakage current phenomenon of the HEMT device. Likewise, if the sidewall82binFIG.1(c)is modified to deviate from the normal direction, the leakage current Jgdbetween the gate and the drain may be further suppressed, thereby further improving the gate leakage current phenomenon of the HEMT device.

In the tangential direction, the orthographic projection ranges of the sidewall82, the sidewall81a, and the sidewall81bof the doped nitride semiconductor layer8may not overlap the surface84; and the orthographic projection ranges of the sidewall82, the sidewall81a, and the sidewall81bmay overlap the range of the surface85.

In the tangential direction, the orthographic projection range of the surface86of the doped nitride semiconductor layer8may not overlap the range of the surface84; and the orthographic projection range of the surface86may overlap the range of the surface85.

In the tangential direction, the orthographic projection range of the sidewall81aof the doped nitride semiconductor layer8may not overlap the range of the surface86; and the orthographic projection range of the sidewall81bfalls beyond the range of the surface86.

A skilled person in the art can use any known method to form a doped nitride semiconductor layer8having a sidewall not parallel to the normal direction, appropriate methods are, for example, but not limited to, a method published in a thesis by D. Zhuang et al., in Materials Science and Engineering R 48 (2005) 1-46, and the thesis is incorporated in this specification by reference in its entirety.

The gate structure80shown inFIG.1(g)is substantially the same as that inFIG.1(e). A difference lies in that, an angle between the tangential direction and a connecting line between an intersection of the sidewall81band the surface84of the doped nitride semiconductor layer8and an intersection of the sidewall81band the surface86is greater than 100°. In this aspect, in the tangential direction, the orthographic projection range of the sidewall81bof the doped nitride semiconductor layer8may overlap the range of the surface84, and the orthographic projection range of the sidewall81amay overlap the range of the surface84, or may not overlap the range of the surface84; and the orthographic projection ranges of the sidewall81aand the sidewall81bmay overlap the range of the surface85.

The inventors have unexpectedly found that, compared with the structure inFIG.1(b), the structure inFIG.1(g)may further suppress the leakage current Jgsbetween the gate and the source, thereby further improving the gate leakage current phenomenon of the HEMT device. Likewise, if the sidewall82binFIG.1(c)is modified to make an angle between the sidewall82band the tangential direction be greater than 100°, the leakage current Jgdbetween the gate and the drain may be further suppressed, thereby further improving the gate leakage current phenomenon of the HEMT device.

In the tangential direction, the orthographic projection range of the surface86of the doped nitride semiconductor layer8may overlap the range of the surface84; and the orthographic projection range of the surface86may overlap the range of the surface85.

In the tangential direction, the orthographic projection range of the sidewall81aof the doped nitride semiconductor layer8may not overlap the range of the surface86; and the orthographic projection range of the sidewall81bmay overlap the range of the surface86.

The gate structure80shown inFIG.1(h)is substantially the same as that inFIG.1(e). A difference lies in that, an angle between the tangential direction and a connecting line between an intersection of the sidewall81aand the surface86of the doped nitride semiconductor layer8and an intersection of the sidewall81aand the surface85is greater than 100°. In this aspect, in the tangential direction, the orthographic projection range of the sidewall81bof the doped nitride semiconductor layer8may not overlap the range of the surface84, and the orthographic projection range of the sidewall81amay overlap the range of the surface84, or may not overlap the range of the surface84; the orthographic projection range of the sidewall81amay not overlap the range of the surface85; and the orthographic projection range of the sidewall81bmay overlap the range of the surface85, or may not overlap the range of the surface85.

The inventors have unexpectedly found that, compared with the structure inFIG.1(b), the structure inFIG.1(h)may further suppress the leakage current Jgsbetween the gate and the source, thereby further improving the gate leakage current phenomenon of the HEMT device. Likewise, if the sidewall82ainFIG.1(c)is modified to make an angle between the sidewall82aand the tangential direction be greater than 100°, the leakage current Jgdbetween the gate and the drain may be further suppressed, thereby further improving the gate leakage current phenomenon of the HEMT device.

In the tangential direction, the orthographic projection of the surface86of the doped nitride semiconductor layer8may not overlap the range of the surface84; and the orthographic projection range of the surface86may overlap the range of the surface85, or may not overlap the range of the surface85.

In the tangential direction, the orthographic projection range of the sidewall81aof the doped nitride semiconductor layer8may overlap the range of the surface86; and the orthographic projection range of the sidewall81bmay not overlap the range of the surface86.

The gate structure80shown inFIG.1(i)is substantially the same as that inFIG.1(e). A difference lies in that, an angle between the tangential direction and a connecting line between an intersection of the sidewall81aand the surface86of the doped nitride semiconductor layer8and an intersection of the sidewall81aand the surface85is less than 80°. In this aspect, in the tangential direction, the orthographic projection range of the sidewall81bof the doped nitride semiconductor layer8may not overlap the range of the surface84, and the orthographic projection range of the sidewall81amay not overlap the range of the surface84; the orthographic projection range of the sidewall81amay overlap the range of the surface85; and the orthographic projection range of the sidewall81bmay overlap the range of the surface85.

The inventors have unexpectedly found that, compared with the structure inFIG.1(b), the structure inFIG.1(i)may further suppress the leakage current Jgsbetween the gate and the source, thereby further improving the gate leakage current phenomenon of the HEMT device. Likewise, if the sidewall82ainFIG.1(c)is modified to make an angle between the sidewall82aand the tangential direction be less than 80°, the leakage current Jgdbetween the gate and the drain may be further suppressed, thereby further improving the gate leakage current phenomenon of the HEMT device.

In the tangential direction, the orthographic projection of the surface86of the doped nitride semiconductor layer8may not overlap the range of the surface84; and the orthographic projection range of the surface86may overlap the range of the surface85.

In the tangential direction, the orthographic projection range of the sidewall81aof the doped nitride semiconductor layer8may not overlap the range of the surface86; and the orthographic projection range of the sidewall81bmay not overlap the range of the surface86.

The gate structure80shown inFIG.1(j)is substantially the same as that inFIG.1(i). A difference lies in that, an angle between the tangential direction and a connecting line between an intersection of the sidewall82and the surface84of the doped nitride semiconductor layer8and an intersection of the sidewall82and the surface85is less than 80°. In this aspect, in the tangential direction, the orthographic projection range of the sidewall82of the doped nitride semiconductor layer8may not overlap the range of the surface84, and the orthographic projection range of the sidewall82may overlap the range of the surface85.

The inventors have unexpectedly found that, compared with the structure inFIG.1(i), the structure inFIG.1(j)may further suppress the leakage current Jgdbetween the gate and the drain, thereby further improving the gate leakage current phenomenon of the HEMT device.

The doped nitride semiconductor layer8may have at least two protrusions adjacent to the source contact6, and the protrusions extend toward the source contact6along the tangential direction. For example, the gate structure80shown inFIG.1(k)is substantially the same as that shown inFIG.1(b). A difference lies in that the doped nitride semiconductor layer8has two protrusions adjacent to the source contact6, and the protrusions extend toward the source contact6along the tangential direction. Therefore, the sidewall81of the doped nitride semiconductor layer8forms a two-step shaped contour line, which sequentially includes interfaces such as a sidewall81a, a surface86, a sidewall81b, a surface88and a sidewall81c. In this aspect, the doped nitride semiconductor layer8has the sidewall81aadjacent to the source contact6and a sidewall82adjacent to the drain contact7, and the sidewall81band the sidewall81cpositioned between the sidewall81aand the sidewall82substantially along the tangential direction; and substantially along the tangential direction, the sidewall81bis positioned between the sidewall81aand the gate electrode9and the sidewall81cis positioned between the sidewall81band the gate electrode9. The doped nitride semiconductor layer8has the surface86and the surface88positioned between the surface84and the surface85substantially along the normal direction, the surface86is positioned between the gate electrode9and the source contact6in a direction substantially parallel to the tangential direction and extends toward the source contact6, and the surface88is positioned between the gate electrode9and the surface86in a direction substantially parallel to the tangential direction and extends toward the source contact6.

Substantially along the normal direction, a ratio of the height of the sidewall81bto that of the sidewall81amay be 0.5 to 2, for example, but not limited to: 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2; and a ratio of the height of the sidewall81cto that of the sidewall81amay be 0.5 to 2, for example, but not limited to: 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2.

In the tangential direction, a ratio of the width of the surface86to the width of the surface84may be 0.05 to 0.2, for example, but not limited to: 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19 or 0.2.

In the tangential direction, a ratio of the width of the surface86to the width of the surface85may be 0.02 to 0.15, for example, but not limited to: 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, or 0.15.

In the tangential direction, a ratio of the width of the surface88to the width of the surface84may be 0.05 to 0.2, for example, but not limited to: 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19 or 0.2.

In the tangential direction, a ratio of the width of the surface88to the width of the surface85may be 0.02 to 0.15, for example, but not limited to: 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, or 0.15.

The sidewall81aof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall82of the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall81bof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall81cof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The surface86of the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The surface88of the doped nitride semiconductor layer8may be in direct contact with the passivation layer.

If the part84bof the surface84of the doped nitride semiconductor layer8exists, the part84bmay be in direct contact with the passivation layer. If the part84cof the surface84of the doped nitride semiconductor layer8exists, the part84cmay be in direct contact with the passivation layer.

The doped nitride semiconductor layer8may alternatively have at least two protrusions adjacent to the drain contact7, and the protrusions extend toward the drain contact7along the tangential direction. The protrusions may be configured in the aforementioned manner.

The inventors have unexpectedly found that, the number of sidewall protrusions (or steps) of the doped nitride semiconductor layer8is related to the magnitude of the gate leakage current; have found that when the number of protrusions or steps is increased, the gate leakage current phenomenon can be more effectively improved; and have found through further research that, the gate leakage current phenomenon is also related to the sidewall roughness. When the sidewall roughness is greater than 50 nm, uneven electric field distribution of the gate would be present, and then earlier breakdown of the device is caused. Compared with the structure inFIG.1(b), the structure inFIG.1(k)further suppresses the leakage current Jgsbetween the gate and the source, thereby further improving the gate leakage current phenomenon of the HEMT device. Likewise, if the number of protrusions of the doped nitride semiconductor layer8inFIG.1(c)that are adjacent to the drain contact7is increased, the leakage current Jgdbetween the gate and the drain may be further suppressed, thereby further improving the gate leakage current phenomenon of the HEMT device. However, if the sidewall roughness is increased due to the limitation to the etching technology or material characteristics in a process of manufacturing a sidewall protrusion or step, an adverse effect may be generated for the effect of the gate leakage current phenomenon. If a general etching process is used for preparing a sidewall protrusion or step for the doped nitride semiconductor layer8whose thickness is 50 to 100 nm, it is found through repetitive research that when the number of sidewall protrusions or steps is 1 or 2, the gate leakage current is improved relatively notably.

The gate structure80shown inFIG.1(l)is substantially the same as that inFIG.1(k). A difference lies in that, the doped nitride semiconductor layer8has a protrusion adjacent to the drain contact7, and this protrusion extends toward the drain contact7along the tangential direction. Therefore, the sidewall82of the doped nitride semiconductor layer8forms a one-step shaped contour line, which sequentially includes interfaces such as a sidewall82a, a surface87and a sidewall82b. In this aspect, the doped nitride semiconductor layer8has the sidewall81aadjacent to the source contact6and a sidewall82aadjacent to the drain contact, and the sidewall81b, the sidewall82b, and the sidewall81cpositioned between the sidewall81aand the sidewall82asubstantially along the tangential direction; and substantially along the tangential direction, the sidewall81bis positioned between the sidewall81aand the gate electrode9, the sidewall81cis positioned between the sidewall81band the gate electrode9, and the sidewall82bis positioned between and the gate electrode9and the sidewall81a. The doped nitride semiconductor layer8has the surface86, the surface87, and the surface88that are positioned between the surface84and the surface85substantially along the normal direction, the surface86and the surface88extends toward the source contact6in a direction substantially parallel to the tangential direction, and the surface87extends toward the drain contact7in a direction substantially parallel to the tangential direction.

The inventors have unexpectedly found that, compared with the structure inFIG.1(k), the structure inFIG.1(l)may further suppress the leakage current Jgdbetween the gate and the drain, thereby further improving the gate leakage current phenomenon of the HEMT device.

The sidewall81aof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall82aof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall81bof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall82bof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The sidewall81cof the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The surface86of the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The surface86of the doped nitride semiconductor layer8may be in direct contact with the passivation layer. The surface88of the doped nitride semiconductor layer8may be in direct contact with the passivation layer.

If the part84bof the surface84of the doped nitride semiconductor layer8exists, the part84bmay be in direct contact with the passivation layer. If the part84cof the surface84of the doped nitride semiconductor layer8exists, the part84cmay be in direct contact with the passivation layer.

Relative positions of the doped nitride semiconductor layer8and the gate electrode9are described above, and the doped nitride semiconductor layer8and the gate electrode9extend substantially along a direction perpendicular to a connecting line between the source contact6and the drain contact7and along the tangential direction.

The doped nitride semiconductor layer8may include, but is not limited to, doped gallium nitride (doped GaN), doped aluminum gallium nitride (doped AlGaN), doped indium gallium nitride (doped InGaN), and other doped group III-V compounds. The doped nitride semiconductor layer8may include, but is not limited to, a p-type dopant, an n-type dopant, or other dopants. An exemplary dopant may include, but is not limited to, magnesium (Mg), zinc (Zn), cadmium (Cd), silicon (Si), and germanium (Ge).

In low-voltage application (for example, the component applicable to 10 V to 200 V), the doped nitride semiconductor layer8has the width greater than about 0.5 micrometers (μm) in the tangential direction. The width of the doped nitride semiconductor layer8may be about 0.5 μm to about 2.0 μm. The width of the doped nitride semiconductor layer8may be about 0.8 μm to about 1.5 μm. The width of the doped nitride semiconductor layer8may be about 1.0 μm.

When the gate structure80of the present invention is applied to the low-voltage device, if the gate structure80includes the part84band the sidewall81a, the following design specifications may be followed:in the tangential direction, the width range W85of the surface85: 0.5 μm≤W85≤2 μm;in the tangential direction, the width range W84of the surface84: W85−0.25 μm≤W84≤W85−0.05 μm;in the tangential direction, the lower limit of the width of the part84bis: 30 nm;in the normal direction, the lower limit of the height of the sidewall81ais: 10 nm;other undefined parameters may be adjusted as required according to the descriptions of this specification.

When the gate structure80of the present invention is applied to the low-voltage device, if the gate structure80includes the part84cand the sidewall82a, the following design specifications may be followed:in the tangential direction, the width range W85of the surface85: 0.5 μm≤W85≤2 μm;in the tangential direction, the width range W84of the surface84: W85−0.25 μm≤W84≤W85−0.05 μm;in the tangential direction, the lower limit of the width of the part84cis: 30 nm;in the normal direction, the lower limit of the height of the sidewall82ais: 10 nm;other undefined parameters may be adjusted as required according to the descriptions of this specification.

In high-voltage application (for example, the component applicable to 200 V or above), the doped nitride semiconductor layer8has the width greater than about 1.8 micrometers (μm) substantially in the tangential direction.

When the gate structure80of the present invention is applied to the high-voltage device, if the gate structure80includes the part84band the sidewall81a, the following design specifications may be followed:in the tangential direction, the width range W85of the surface85: 1.5 μm≤W85≤3.5 μm;in the tangential direction, the width range W84of the surface84: W85−0.25 μm≤W84≤W85−0.05 μm;in the tangential direction, the lower limit of the width of the part84bis: 30 nm;in the normal direction, the lower limit of the height of the sidewall81ais: 10 nm;other undefined parameters may be adjusted as required according to the descriptions of this specification.

When the gate structure80of the present invention is applied to the high-voltage device, if the gate structure80includes the part84cand the sidewall82a, the following design specifications may be followed:in the tangential direction, the width range W85of the surface85: 1.5 μm≤W85≤3.5 μm;in the tangential direction, the width range W84of the surface84: W85−0.25 μm≤W84≤W85−0.05 μm;in the tangential direction, the lower limit of the width of the part84cis: 30 nm;in the normal direction, the lower limit of the height of the sidewall82ais: 10 nm;other undefined parameters may be adjusted as required according to the descriptions of this specification.

The nitride semiconductor layer4may include a group III-V material, for example, but not limited to, group III nitrides, such as a compound InxAlyGa1-x-yN, where x+y≤1, for example, x=0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8 or 0.9. The group III nitrides may also include, for example, but are not limited to, a compound AlyGa(1-y), where y≤1, for example, y=0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8 or 0.9.

The HEMT device1aalso includes a nitride semiconductor layer5disposed on the nitride semiconductor layer4. The nitride semiconductor layer5may include, for example, but not limited to, group III nitrides, such as a compound InxAlyGa1-x-yN, where x+y≤1. The group III nitrides may also include, for example, but are not limited to, a compound AlyGa(1-y)N, where y≤1, for example, y=0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8 or 0.9. The nitride semiconductor layer5has a greater bandgap than the nitride semiconductor layer4. For example, the nitride semiconductor layer4may include a GaN layer. GaN may have a bandgap of about 3.4 eV. The nitride semiconductor layer5may include AlGaN. The AlGaN may have a bandgap of about 4 eV. The 2DEG region41is generally formed in a layer with a smaller bandgap (for example GaN). A heterojunction is formed between the nitride semiconductor layer5and the first nitride semiconductor layer4. The 2DEG region41is formed in the first nitride semiconductor layer4through polarization of the heterojunction of different nitrides. The first nitride semiconductor layer4can provide or remove electrons in the 2DEG region, and conduction of the HEMT device1acan be further controlled.

The higher the aluminum content is, the higher the concentration of the two-dimensional electron gas in a gallium nitride buffer layer, and the higher the carrier concentration of the channel for high-current operation, which is a very important index for high-power components. If AlGaN is used as a material of the nitride semiconductor layer5, the Al content may be 20 to 40%. If the Al content is too high, crystalline blocks can be easily produced, and a problem of stress release of the epitaxial layer may also be generated.

The first nitride semiconductor layer4may have an electron channel region shown by dotted lines (a region of a two-dimensional electron gas41), and the region of the two-dimensional electron gas41is generally easy to obtain in the heterostructure. In this region, the electron gas may freely move in a two-dimensional direction, and is limited in a three-dimensional direction (for example, substantially in the normal direction of the two-dimensional electron gas). It should be understood by those skilled in the art that as shown by disconnection in dotted lines, part of the two-dimensional electron gas41under the doped nitride semiconductor layer8has been depleted. It should also be understood by those skilled in the art that as shown by the dotted line41, the two-dimensional electron gas41, including its depleted region, in the first nitride semiconductor layer4forms a channel region of the first nitride semiconductor layer4, and flowing of electrons through the channel region is controlled through a gate voltage applied onto the gate structure80during operation. The nitride semiconductor layer4may be of a single-layer structure or a multi-layer structure. The nitride semiconductor layer4may also include a heterostructure.

The gate electrode9may be formed on the doped nitride semiconductor layer8, for example, formed on the surface of the doped nitride semiconductor layer8so as to provide electric connection for the gate structure80of the HEMT device1a. The gate electrode9may include, for example, but is not limited to, titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), plumbum (Pb), molybdenum (Mo) and compounds thereof (for example, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides, or conductive oxides), metal alloy (such as Al—Cu alloy), or other suitable materials. The gate electrode9may be formed by a single metal or a metal stack (such as tungsten and/or titanium or other well-known electrode materials).

The gate electrode9may be in direct contact with the doped nitride semiconductor layer8. The gate electrode9may also be electrically connected to the doped nitride semiconductor layer8. Substantially in the normal direction, the doped nitride semiconductor layer5may be disposed under the gate electrode9, and the gate electrode9may be positioned above the doped nitride semiconductor layer8. The gate electrode is configured to form a Schottky junction with the doped nitride semiconductor layer to further reduce the gate leakage current.

In low-voltage application (for example, the component applicable to 10 V to 200 V), the gate electrode9may have a width greater than about 0.4 μm substantially in the tangential direction. The width of the gate electrode9may be about 0.4 μm to about 1.2 μm. Substantially in the tangential direction, the width of the gate electrode9is smaller than the width of the doped nitride semiconductor layer8.

In high-voltage application (for example, the component applicable to 200 V or higher), the gate electrode9may have a width greater than about 1.6 μm substantially in the tangential direction.

The HEMT device1amay also include the source contact6and the drain contact7, and the source contact and the drain contact may be formed into a metal region disposed on the portion of the nitride semiconductor layer5. The metal of the source contact6and the drain contact7forms ohmic contact with the nitride semiconductor layer5so as to collect electrons or provide electrons to the channel region. Metal for forming the source contact or the drain contact may include refractory metals or compounds thereof, for example, but not limited to, metals such as aluminum (Al), titanium (Ti), niobium (Nb), molybdenum (Mo), tantalum (Ta), tungsten (W), rhenium (Re), titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr), hafnium (Hf), ruthenium (Ru), osmium (Os) and iridium (Ir) or compounds of the metals, such as tantalum nitride (TaN), titanium nitride (TiN), and tungsten carbide (WC). The source contact6and the drain contact7may be formed by a single metal or a metal stack (such as tungsten and/or titanium or other well-known electrode materials).

The nitride semiconductor layer4and the substrate2may be of homogeneous materials, for example, but not limited to GaN. No lattice constant or thermal expansion coefficient mismatch problem exists between the nitride semiconductor layer4and the substrate2during epitaxial growth. Therefore, the nitride semiconductor layer4may directly grow on the substrate2and is in direct contact with the substrate2without the need of using a buffer layer.

The nitride semiconductor layer4and the substrate2are of heterogeneous materials. The nitride semiconductor layer4and the substrate2have different lattice constants and thermal expansion coefficients. During epitaxial growth, a great quantity of dislocation and cracks may be generally generated, thereby further reducing the efficiency of the HEMT device1aor even causing dysfunction of the HEMT device. In order to avoid the above conditions, the buffer layer (not shown in the figure) disposed between the substrate2and the nitride semiconductor layer4may be optionally used. The buffer layer may be used to promote lattice match between the substrate2and the nitride semiconductor layer4so as to reduce the interface stress and/or thermal stress of the heterogeneous materials, thereby reducing the defects and crack density in the nitride semiconductor layer4. Materials suitable to be used as the buffer layer include, for example, but are not limited to, oxides (such as zinc oxide) or nitrides (such as aluminum nitride (AlN) and aluminum gallium nitride (AlGaN)).

The HEMT device1amay also include a superlattice layer (not shown inFIG.1toFIG.3) disposed between the substrate2and the nitride semiconductor layer4. The superlattice layer may be positioned between the nitride semiconductor layer4and the substrate2. The superlattice layer may be a plurality of layers or a multi-layer stack, for example an AlGaN/GaN pair or a multi-layer stack of AlN/GaN. The superlattice layer may reduce the tensile stress of the HEMT device1a. The superlattice layer may also prevent defects (such as dislocation) from propagating into the nitride semiconductor layer4from a layer (such as the buffer layer) under the superlattice layer, so as to enhance the crystallization quality to the nitride semiconductor layer4and avoid the dysfunction of the HEMT device1a. The superlattice layer may trap electrons diffused from the substrate2to the nitride semiconductor layer4, thereby further improving the efficiency and reliability of the device. The superlattice layer may reduce electron trap.

In high-voltage application, in order to avoid direct breakdown of the voltage to the substrate2, the superlattice layer may increase the integral size of the HEMT device or structure to increase the breakdown voltage. The thickness of the superlattice layer is generally about 1 μm to 4 μm, and is greater than that of the buffer layer. When the superlattice layer is disposed, defects, such as delamination or peeling off, caused by the lattice number and/or thermal expansion coefficient difference of the superlattice layer from adjacent materials still need to be considered. Additionally, the manufacturing cost will be greatly increased due to use of the superlattice layer.

In high-voltage application, in order to avoid direct breakdown of the voltage to the substrate2, the buffer layer or the superlattice layer may be doped with other heterogeneous elements, for example, but not limited to, carbon, oxygen, or nitrogen, and they may be intentionally doped or unintentionally doped.

Application of Low-Voltage HEMT Devices

The gate structure of the present invention may be applied to low-voltage HEMT devices.FIG.2(a)toFIG.2(h)show several operations for manufacturing a low-voltage HEMT device1baccording to some embodiments of the present invention. AlthoughFIG.2(a)toFIG.2(h)show several operations for manufacturing the low-voltage HEMT device1b, similar operations are also applicable.

With reference toFIG.2(a), a substrate2is provided. A buffer layer3is disposed on the substrate2. A nitride semiconductor layer4, a nitride semiconductor layer5, and a doped nitride semiconductor layer8are disposed on the substrate2through epitaxial growth. A gate electrode9is additionally disposed on the doped nitride semiconductor layer8. The gate electrode9is optionally configured to form a Schottky junction with the doped nitride semiconductor layer8. Additionally, a photoresist94is applied to a hard mask93so as to determine the position of the gate electrode9after the photolithography and etching processes. The patterned hard mask93is formed above the gate electrode9.

The doped nitride semiconductor layer8and the gate electrode9are disposed on the substrate2. The doped nitride semiconductor layer8may be formed through metal organic chemical vapor deposition (MOCVD) or in any known epitaxial growth mode, and is doped with a dopant. Then, the gate electrode9is deposited onto the doped nitride semiconductor layer8. The gate electrode9may be formed through physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plating, and/or other proper deposition steps. The gate electrode9is formed by a gate first process, i.e., the gate electrode9is formed before a source contact6and a drain contact7are formed.

The hard mask93may include (but is not limited to) silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbide (SiC). The etching step may be performed through dry etching, wet etching, or a combination of the dry etching and the wet etching.

An etching agent for etching the gate electrode9may be ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), hydrofluoric acid (HF), ammonium fluoride (NH4F), or a mixture of the above compounds. The doped nitride semiconductor layer8may be subjected to anisotropic etching in a dry etching mode.

With reference toFIG.2(b), the required portions of the gate electrode9and the doped nitride semiconductor layer8are retained in photolithography and etching modes. The etching of the exposed doped group III-V layer8and the gate electrode9may be performed by any known manufacturing process such as plasma etching. The gate electrode9may be optionally overetched so as to define, on the surface84, a part84aelectrically connected to the gate electrode9, and a part84cadjacent to the part84a, and then, the photoresist94and the hard mask93are peeled off.

With reference toFIG.2(c), the patterned hard mask95is formed above the gate electrode9, the doped nitride semiconductor layer8and the nitride semiconductor layer5to define the width of the surface86, and subsequently the exposed gate electrode9and the doped nitride semiconductor layer8are etched, so as to form a protrusion/step structure having the sidewall81a, the surface86and the sidewall81bon a sidewall of the doped nitride semiconductor layer8.

With reference toFIG.2(d), the gate electrode9may be optionally overetched, so as to define the part84badjacent to the part84aon the surface84, and subsequently the hard mask95is peeled off.

With reference toFIG.2(e), the HEMT device1bmay also include a passivation layer10disposed on the gate electrode9. The passivation layer10is in direct contact with the part84band the part84cof the surface84. The passivation layer10may surround the doped nitride semiconductor layer8, and is in direct contact with the sidewall82, the sidewall81aand the sidewall81b. The passivation layer10may cover the doped nitride semiconductor layer8, and is in direct contact with the surface86. The passivation layer10may surround the gate electrode9. The passivation layer10may cover the gate electrode9. The passivation layer10may cover part of the gate electrode9.

The passivation layer10may include, for example, but is not limited to, oxides or nitrides, such as silicon nitride (SiN) and silicon oxide (SiO2). The passivation layer10may include, for example, but is not limited to, a compound layer of oxides and nitrides, such as Al2O3/SiN, Al2O3/SiO2, AlN/SiN, and AlN/SiO2.

With reference toFIG.2(f), the passivation layer10uses the photolithography and etching processes to define the position of the drain.

With reference toFIG.2(g), a conductor material is deposited onto the passivation layer10. The conductor material is patterned by using the photolithography and etching processes to form a source6, a drain7, and a gate field plate11. Rapid thermal annealing (RTA) is performed so as to form the deposited material and the nitride semiconductor layer4into an intermetallic compound and to further form an ohmic contact from the source6to the two-dimensional electron gas41and the drain7to the two-dimensional electron gas41.

The objective of providing the field plate11on the gate electrode9is to reduce an electric field nearest to the drain7and at a corner position of the doped nitride semiconductor layer8, thereby improving the stability of the HEMT device1band increasing the breakdown voltage between the gate and the drain. The field plate11may be disposed above the passivation layer10, the doped nitride semiconductor layer8, and the gate electrode9. The field plate11may have a common potential with the source contact6or have a common potential with the gate electrode9. The field plate11may be directly connected to the source contact6. The field plate11may be electrically connected to the source contact6. By using the field plate, the electric field intensity distribution of the channel may be reconstructed, and an electric field peak value of the gate (at the side near the drain) is reduced, thereby increasing the breakdown voltage of the HEMT device1band reducing the electron trap effect caused by the high electric field, and improving the power density.

The length range of the field plate in the low-voltage device may be 0.4 to 1.2 μm. A too long field plate may improve the capacitance effect between the gate and the drain, thereby causing negative Miller feedback, and reducing the cut-off frequency of the current gain and the power gain. Additionally, if the field plate approaches to the drain, the electric field intensity of the field plate at the end point of the side near the drain may be improved, and the breakdown voltage is further reduced.

The source contact6and the drain contact7may include, for example, but are not limited to, a conductor material. The conductor material may include, for example, but is not limited to, a metal, an alloy, a doped semiconductor material (for example, doped crystalline silicon), or other suitable conductor materials.

Part of the source contact6may be positioned in the nitride semiconductor layer4. Part of the drain contact7may be positioned in the nitride semiconductor layer4. Part of the source contact6may be in direct contact with the two-dimensional electron gas41. Part of the drain contact7may be in direct contact with the two-dimensional electron gas41. The source contact6may be disposed on the nitride semiconductor layer4. The drain contact7may be disposed on the nitride semiconductor layer4. The source contact6may pass through the passivation layer10to be in contact with the nitride semiconductor layer5. The drain contact7may pass through the passivation layer10to be in contact with the nitride semiconductor layer5. With reference toFIG.2(h), the HEMT device1bmay also include an interconnect structure or conductive vias12and121. The HEMT device1bmay also include metal layers13and131.

The interconnect structure or the conductive via12is formed through a plurality of steps, including the steps of a photolithography process, etching, and deposition. The photolithography process and etching include forming a patterned mask on a passivation layer101, and etching the passivation layer101to form the source contact via12and a drain contact via (not shown in the figure). Part of the nitride semiconductor layer4is exposed from the bottom of the source contact via and the drain contact via. Then, the vias are filled with the material through the deposition steps of CVD, PVD, plating and the like.

The HEMT device1cshown inFIG.3is substantially the same as the HEMT device1bshown inFIG.2(h)in structure. A difference lies in that the gate structure of the HEMT device1chas a symmetrical geometric shape by using the normal direction as a symmetrical axis. Moreover, the doped nitride semiconductor layer8of the HEMT device1chas no protrusion. The material selection, configurations and forming modes of the layers of the HEMT device1care described in the section of “Application of low-voltage HEMT devices”.

FIG.4shows curves of Ig on (gate leakage current) versus Vgs of the HEMT device1band the HEMT device1c, where when Vgs=5 V, Ig on of the HEMT device1bis 7.2×10−11, and Ig on of the HEMT device1cis 2.2×10−9.

Application of High-Voltage HEMT Devices

With reference toFIG.5(a), the improved gate structure of the present invention is also applicable to high-voltage components. Reference may be made to the processes shown below of the passivation layer101inFIG.2(a)toFIG.2(e)for the preparation modes of the following structure of a passivation layer101of a high-voltage HEMT device1d, and those will not be described in detail herein. However, in high-voltage application, in order to avoid direct breakdown of the voltage to a substrate2, a doped superlattice layer31is optionally disposed between the substrate2and a nitride semiconductor layer4to increase the overall size of the HEMT device or structure and increase the breakdown voltage. After a passivation layer10is disposed, the passivation layer101is disposed on the passivation layer.

With reference toFIG.5(b), although a source contact6and a drain contact7are respectively disposed on two sides of a gate electrode9inFIG.5(b), the source contact6, the drain contact7, and the gate electrode9may have different configurations in other embodiments of the present invention according to design requirements.

With reference toFIG.5(c), a dielectric layer102is positioned between a field plate111and the source contact6substantially in the normal direction. A high-voltage component device may include a plurality of field plates, and the field plates are not in contact with each other and are separated from each other. One or more of the field plates may be at zero potential. Although the HEMT device1dfinally made through the method inFIG.5has four field plates, the present invention is not limited thereto. The HEMT device1dmay include more or fewer than four field plates.

The field plate111(including the field plates112,113, and114mentioned below) may be formed in the manner of firstly depositing a conductive material and then defining a pattern. For example, metal may be deposited through sputtering, and the pattern may be defined by dry etching. It should be noted that the position of the field plate111cannot be the position of a T-shaped electrode14formed in subsequent steps. Additionally, the applicable voltage of the relatively-low-voltage component is smaller, and the influence of the electric field between conductor structures on the efficiency of the component is smaller, so that the field plate of the relatively-low-voltage component may be omitted.

The field plate111may reduce the electric field of a gate contact structure, enable the electric field among the conductor structures (for example, the T-shaped electrode14, the source contact6, and the drain contact7) to be averagely distributed, and improve the voltage tolerance so as to smoothly release the voltage, thereby further improving the reliability of the device.

With reference toFIG.5(d), a dielectric layer103is positioned between a field plate111and the source contact6substantially in the normal direction. An opening1031is formed in the dielectric layers102and103. The opening1031exposes a partial surface of the gate electrode9. The opening1031may be formed in a dry etching or wet etching mode.

For example, wet etching includes exposure to a hydroxide-containing solution, deionized water, and/or other etching agents. Dry etching includes use of inductively coupled plasma. The gate electrode9may be used as a stop layer for the doped nitride semiconductor layer8in this step.

With reference toFIG.5(e), in high-voltage application, the T-shaped electrode14may be additionally disposed on the gate electrode9. The T-shaped electrode14may be in direct contact with the gate electrode9. The T-shaped electrode14may alternatively be electrically connected to the gate electrode9. Substantially in the normal direction, the T-shaped electrode14is positioned above the gate electrode9, the gate electrode9is positioned under the T-shaped electrode14, and the gate electrode9is positioned between the T-shaped electrode14and the doped nitride semiconductor layer8.

The T-shaped electrode14may include a structure formed by a single material. The T-shaped electrode14may include a structure formed by heterogeneous materials. As shown in dotted boxes inFIG.5(e), the T-shaped electrode14may include a plurality of layers of heterojunctions. The T-shaped electrode14may include a plurality of layers, for example, a layer141, a layer142, a layer143, and a layer144. Although the T-shaped electrode14depicted the dotted boxes inFIG.5(e)includes the four layers, the present invention is not limited thereto. In other embodiments, the T-shaped electrode14may include structures of more or fewer than four layers.

The layer141may include, for example, but is not limited to, a refractory metal or a compound thereof. The layer141may include a material identical or similar to that of the gate electrode9. The layer141may include a material different from that of the gate electrode9. The layer142may include, for example, but is not limited to, a metal or a metal compound, for example, titanium, chromium, and tungsten titanate. The layer142may be used as a wetting layer to help subsequent metal filling. The layer143may include, for example, but is not limited to, a gate metal. The layer143may include a material identical or similar to that of the T-shaped electrode14. The layer143may include a material different from that of the T-shaped electrode14. The layer144may include, for example, but is not limited to, a refractory metal or a compound thereof. The layer144may include a material identical or similar to that of the gate electrode9. The layer144may include a material different from that of the gate electrode9.

The field plate112may enable the electric field among the conductor structures (for example, the T-shaped electrode14, the source contact6, and the drain contact7) to be averagely distributed, and improve the voltage tolerance so as to smoothly release the voltage, thereby further improving the reliability of the device. The field plate112may reduce the electric field of the gate contact structure, and increase the threshold voltage. The field plate112partially overlaps the field plate111substantially in the normal direction.

The T-shaped electrode14has an overhang14′ so that the top width of the T-shaped electrode is greater than the width of the gate electrode9substantially in the tangential direction. In this case, the width of the gate electrode9is smaller than that of the T-shaped electrode14. In other embodiments, the T-shaped electrode14may have no overhang14′.

The distance between the border of the overhang14′ and the border of the field plate111may be about 0.5 μm to 2.5 μm. The distance between the border of the overhang14′ and the border of the field plate112may be about 2 μm to 4 μm.

The T-shaped electrode14may reduce the overall resistance value of the gate contact structure, is used to provide a low-resistance conductor wire, and may further be used to be electrically connected to other conductors.

The gate electrode9is favorable for improving bias control of the T-shaped electrode14. The gate electrode9is favorable for increasing the switching speed of the gate. The gate electrode9is favorable for reducing the leakage current and increasing the threshold voltage.

In the high-voltage component, the voltage tolerance may be influenced by the distance between the drain contact7and the T-shaped electrode14, so that the distance between the drain contact7and the T-shaped electrode14may be greater than about 15 μm. The smaller the width of the doped nitride semiconductor layer8, the greater the distance between the drain contact7and the T-shaped electrode14, and the higher the high-voltage tolerance capability. Additionally, the smaller the width of the doped nitride semiconductor layer8, the smaller the resistance value of the high-voltage component.

The T-shaped electrode14may have the width greater than about 0.3 μm substantially in the tangential direction. The width of the T-shaped electrode14may be about 0.3 μm to about 0.8 μm. The width of the T-shaped electrode14may be smaller than the width of the gate electrode9. The width of the T-shaped electrode14may be smaller than the width of the doped nitride semiconductor layer8.

Each layer of the T-shaped electrode14may be formed through PVD, CVD, ALD, plating, and/or other suitable steps. After each layer of the T-shaped electrode14is filled, the surface of the T-shaped electrode14is not treated by CMP, so that the overhang14′ remains on the dielectric layer103.

The field plate111is adjacent to the T-shaped electrode14substantially in the tangential direction. The field plate112is adjacent to the T-shaped electrode14substantially in the tangential direction. The field plate111is positioned between the T-shaped electrode14and the drain contact7substantially in the tangential direction. The field plate112is positioned between the T-shaped electrode14and the drain contact7substantially in the tangential direction.

The field plate112may be formed together with the T-shaped electrode14. The field plate112may have the same material as that of the T-shaped electrode14.

The passivation layer10may surround the T-shaped electrode14. The passivation layer10may surround part of the T-shaped electrode14.

The passivation layer101disposed on the passivation layer10may surround the T-shaped electrode14. The passivation layer101may surround part of the T-shaped electrode14.

With reference toFIG.5(f), a dielectric layer102is positioned between a field plate113and the source contact6substantially in the normal direction. The field plate113partially overlaps the field plate111substantially in the normal direction.

A dielectric layer103is positioned between a field plate113and the source contact6substantially in the normal direction. A dielectric layer104is positioned between a field plate113and the source contact6substantially in the normal direction.

The field plate113may reduce the electric field of the gate contact structure, and increase the threshold voltage. The field plate113may enable the electric field among the conductor structures (for example, the T-shaped electrode14, the source contact6, and the drain contact7) to be averagely distributed, and improve the voltage tolerance so as to smoothly release the voltage, thereby further improving the reliability of the device. The field plate113overlaps with the T-shaped electrode14substantially along the normal direction. The field plate113has a portion positioned between the border of the overhang14′ and the geometric center of the T-shaped electrode14substantially in the tangential direction. The border of the overhang14′ passes through the field plate113substantially in the normal direction.

The field plate113may not overlap the T-shaped electrode14substantially along the normal direction. In other embodiments, the field plate113may not overlap the centerline143of the T-shaped electrode14substantially in the normal direction. The field plate113is positioned between the T-shaped electrode14and the drain contact7substantially in the tangential direction.

The shortest distance between the border of the overhang14′ and the border of the field plate113may be about 3 μm to 5 μm.

With reference toFIG.5(g), the HEMT device1dmay also include a dielectric layer102, a dielectric layer103, a dielectric layer104, a dielectric layer105, a dielectric layer106, and a dielectric layer27.

The dielectric layer102is positioned between a field plate114and the source contact6substantially in the normal direction. The dielectric layer103is positioned between a field plate114and the source contact6substantially in the normal direction. The dielectric layer104is positioned between a field plate114and the source contact6substantially in the normal direction. The dielectric layer105is positioned between a field plate114and the source contact6substantially in the normal direction.

The field plate114may reduce the electric field of the gate contact structure, and increase the threshold voltage. The field plate114may enable the electric field among the conductor structures (for example, the T-shaped electrode14, the source contact6, and the drain contact7) to be averagely distributed, and improve the voltage tolerance so as to smoothly release the voltage, thereby further improving the reliability of the device. The field plate114partially overlaps the field plate111substantially in the normal direction. The field plate114is positioned between the T-shaped electrode14and the drain contact7substantially in the tangential direction.

The distance between the border of the overhang14′ and the closest border of the field plate114may be about 6 μm to 8 μm.

The width of the field plate (for example, the field plate111, the field plate112, the field plate113, and/or the field plate114) substantially in the tangential direction may be about 50 to 150 nm. The width of the field plate substantially in the tangential direction may be about 80 to 120 nm. The width of the field plate substantially in the tangential direction may be about 90 to 110 nm.

The field plate111may be connected to the source contact6and/or the drain contact7through other conductor structures. The field plate112may be connected to the source contact6and/or the drain contact7through other conductor structures. The field plate113may be connected to the source contact6and/or the drain contact7through other conductor structures. The field plate114may be connected to the source contact6and/or the drain contact7through other conductor structures. The field plate111is not in direct contact with the source contact6. The field plate111is not in direct contact with the drain contact7. The field plate112is not in direct contact with the source contact6. The field plate112is not in direct contact with the drain contact7. The field plate113is not in direct contact with the source contact6. The field plate113is not in direct contact with the drain contact7. The field plate114is not in direct contact with the source contact6. The field plate114is not in direct contact with the drain contact7.

At least one dielectric layer (for example, the dielectric layer102, the dielectric layer103, the dielectric layer104, and the dielectric layer105) may exist between the field plate111, the field plate112, the field plate113, and/or the field plate114and the conductor structure. Through such configuration, the distance between the conductor structures may be small, and the resistance value increase is avoided.

Application of Hybrid HEMT Devices

In some embodiments, the improved gate structure of the present invention may be applied to an HEMT device as shown inFIG.6.

The HEMT device includes: a substrate; a buffer layer, positioned above the substrate, the buffer layer including a superlattice structure; a first nitride semiconductor layer, positioned above the buffer layer; a second nitride semiconductor layer, positioned above the first nitride semiconductor layer and having an energy band gap greater than that of the first nitride semiconductor layer; and a high-voltage component portion and a low-voltage component portion, positioned above the second nitride semiconductor layer, the operating voltage of the high-voltage component portion being greater than the operating voltage of the low-voltage component portion.

The high-voltage component portion includes: a first source contact and a first drain contact, positioned above the second nitride semiconductor layer; a first doped third nitride semiconductor layer, positioned above the second nitride semiconductor layer and between the first drain contact and the first source contact; and a first gate electrode, positioned above the first doped third nitride semiconductor layer.

The low-voltage component portion includes: a second source contact and a second drain contact, positioned above the second nitride semiconductor layer; a second doped third nitride semiconductor layer, positioned above the second nitride semiconductor layer and between the second drain contact and the second source contact; and a second gate electrode, positioned above the second doped third nitride semiconductor layer.

The first gate electrode and the first doped third nitride semiconductor layer of the high-voltage component portion may be disposed in the mode described above.

The second gate electrode and the second doped third nitride semiconductor layer of the low-voltage component portion may be disposed in the mode described above.

The first gate electrode of the high-voltage component portion is configured to form a Schottky junction with the first doped third nitride semiconductor layer. The second gate electrode of the low-voltage component portion is configured to form a Schottky junction with the second doped third nitride semiconductor layer.

The structure of the low-voltage component portion may be similar to that of the HEMT device1bmentioned above. The structure of the high-voltage component portion may be identical or similar to that of the HEMT device1dmentioned above.

FIG.6(a)toFIG.6(l)show several operations for manufacturing an HEMT device1eaccording to some embodiments of the present invention. AlthoughFIG.6(a)toFIG.6(l)show several operations for manufacturing the hybrid HEMT device1e, similar operations are also applicable.

With reference toFIG.6(a), a substrate2is provided. In some embodiments, a doped superlattice layer32optionally epitaxially grows on the substrate2. In some embodiments, a nitride semiconductor layer4, a nitride semiconductor layer5, and a doped nitride semiconductor layer8are disposed on the substrate2through epitaxial growth. In some embodiments, a gate electrode is formed before a source contact and a drain contact are formed. The gate electrode9is configured to form a Schottky junction with the doped nitride semiconductor layer8.

Additionally, photoresists94and94′ are applied to a hard mask93so as to determine the position of the gate electrode9after the photolithography and etching processes.

With reference toFIG.6(b), patterned hard masks93and93′ are formed above the gate electrode9. Then, the required portions of the gate electrodes9and9′ and the doped nitride semiconductor layer8may be retained in photolithography and etching modes. The gate electrodes9and9′ may be optionally overetched, so as to define, on the surface84, a part84aelectrically connected to the gate electrode9, and a part84cadjacent to the part84a, and define, on the surface84′, a part84a′ electrically connected to the gate electrode9′, and a part84c′ adjacent to the part84a′. The configurations and forming modes of the above components are described above, and then, the photoresists94and94′ and the hard masks93and93′ are peeled off.

With reference toFIG.6(c), the patterned hard mask95is formed above the gate electrodes9and9′, the doped nitride semiconductor layer8and the nitride semiconductor layer5to define the widths of the surfaces86and86′, and subsequently the exposed gate electrodes9and9′ and the doped nitride semiconductor layers8and8′ are etched, so as to form a protrusion/step structure having the sidewall81a, the surface86and the sidewall81bon a sidewall of the doped nitride semiconductor layer8, and form a protrusion/step structure having the sidewall81a′, the surface86′ and the sidewall81b′ on a sidewall of the doped nitride semiconductor layer8′. The content relevant to the photolithography and etching of the gate electrodes9and9′ and the doped nitride semiconductor layers8and8′ has been described above, and will not be described in detail herein.

With reference toFIG.6(d), the gate electrodes9and9′ may be optionally overetched, so as to define the part84badjacent to the part84aon the surface84and define the part84b′ adjacent to the part84a′ on the surface84′, and subsequently the hard mask93is peeled off. The content relevant to the overetching of the gate electrodes has been described above, and will not be described in detail herein.

With reference toFIG.6(e), after the asymmetrical gate structures are formed, a passivation layer10and a passivation layer101are formed on the gate electrodes9and9′. The configurations and forming modes of the above components are described above.

With reference toFIG.6(f), source contact vias and drain contact vias are formed, and are filled with materials to form source contacts6and6′ and drain contacts7and7′. The forming modes of the source contact vias and the drain contact vias have been described above, and will not be described in detail herein.

With reference toFIG.6(g), a dielectric layer102is deposited onto the passivation layer101. The dielectric layer102(and the dielectric layers103,104,105,106, and107) may be deposited in the following modes: chemical vapor deposition (CVD), high density plasma CVD, spin-on, sputtering, and the like. Then, the surface of the dielectric layer102is treated through chemical-mechanical planarization (CMP).

Isolation regions15,151, and152are formed to isolate the source contacts6and6′ from the drain contacts7and7′ of a high-voltage component1e(i) and a low-voltage component1e(ii). An implant isolation process may be used. A patterned photoresist1021is used. Nitrogen, oxygen, fluorine or the like is implanted in the area not covered by the patterned photoresist1021. The elements will remain in the nitride semiconductor layer4to block channels of the two-dimensional electron gas41on the two sides.

The isolation regions15,151, and152may include dielectric materials. The isolation regions15,151, and152may include dielectric materials with a low dielectric constant (low k value). The isolation regions15,151, and152may include nitrides, oxides, or fluorides. The isolation regions15,151, and152may include silicon oxide, silicon nitride, silicon oxynitride, or fluorine-doped silicate glass (FSG). If the isolation regions15,151, and152need to be filled with the dielectric materials, the operation may be performed in photolithography, etching and deposition modes before the passivation layer101is disposed.

With reference toFIG.6(h), a field plate111is formed on the dielectric layer102. The dielectric layer102separates the field plate111from the source contact6substantially in the tangential direction. The configurations and forming modes of the above components are described in the section of “Application of high-voltage HEMT devices”.

With reference toFIG.6(i), an opening1031is formed in the high-voltage component portion1e(i). The opening1031exposes a partial surface of the gate electrode9. The opening1031may be formed in a dry etching or wet etching mode. The configuration and forming mode of the opening1031are described by parts relevant to the opening1031in the section of “Application of high-voltage HEMT devices”.

A semiconductor component1eincludes the high-voltage component portion1e(i) and the low-voltage component portion1e(ii). Before the manufacturing process proceeds to the formation of the isolation regions15,151, and152(including the step of forming the isolation regions15,151, and152), the high-voltage component portion1e(i) and the low-voltage component portion1e(ii) have the same structure and process, and the same component may be formed in the same step.

The high-voltage component portion1e(i) belongs to a relatively-high-voltage component, and the low-voltage component portion1e(ii) belongs to a relatively-low-voltage component. In the semiconductor component1e, the low-voltage component portion1e(ii) belongs to the gate first manufacturing process. After the isolation regions15,151, and152are formed, the low-voltage component portion1e(ii) will not form the opening or the T-shaped electrode.

The high-voltage component portion1e(i) may belong to a hybrid manufacturing process of the gate first process and the gate last process. After the isolation regions15,151, and152are formed, the high-voltage component portion1e(i) continues to form the field plate111, form the opening1031, and form the T-shaped electrode14.

With reference toFIG.6(j), each layer of the T-shaped electrode14is deposited and fills the opening1031to form the T-shaped electrode14. The material selection, configurations and forming modes of the layers of the T-shaped electrode14are described in the section of “Application of high-voltage HEMT devices”.

The field plate112may be formed together with the T-shaped electrode14. The field plate112may have the same material as that of the T-shaped electrode14.

With reference toFIG.6(k), the operations for manufacturing the HEMT device1emay additionally include forming the dielectric layer104and the field plate113.

With reference toFIG.6(l), the operations for manufacturing the HEMT device1emay additionally include forming the dielectric layer105and forming the interconnect structure12passing through the dielectric layers105to102to be connected to the source contacts6and6′ and the drain contacts7and7′.

The operations for manufacturing the HEMT device1emay additionally include forming the metal layer13and the field plate114on the dielectric layer105.

The operations for manufacturing the HEMT device1emay additionally include forming a dielectric layer106to cover the metal layer13and the field plate114. The operations for manufacturing the HEMT device1emay additionally include forming a conductive via121passing through the dielectric layer106to be connected to the metal layer13or the interconnect structure12. The operations for manufacturing the HEMT device1emay additionally include forming a metal layer131connected to the conductive via121, and forming a dielectric layer107to cover the metal layer131.

One or more field plates may be disposed in the high-voltage component portion1e(i). One or more field plates may be disposed in the low-voltage component portion1e(ii). One or more field plates may be disposed in both the high-voltage component portion1e(i) and the low-voltage component portion1e(ii). No field plate may be disposed in the low-voltage component portion1e(ii).

The high-voltage component portion1e(i) may be applied to the voltage higher than 500 V. The high-voltage component portion1e(i) may be applied to the voltage higher than 550 V. The high-voltage component portion1e(i) may be applied to the voltage higher than 600 V. The low-voltage component portion1e(ii) may be applied to the voltage of 10 V to 40 V. The low-voltage component portion1e(ii) may be applied to the voltage lower than the voltage of the high-voltage component portion1e(i).

The high-voltage component portion1e(i) may be formed on the superlattice layer32. The low-voltage component portion1e(ii) may be formed on the superlattice layer32.

As used herein, for ease of description, space-related terms such as “under”, “below”, “lower portion”, “above”, “upper portion”, “lower portion”, “left side”, “right side”, and the like may be used herein to describe a relationship between one component or feature and another component or feature as shown in the figures. In addition to orientations shown in the figures, space-related terms are intended to encompass different orientations of the device in use or operation. An apparatus may be oriented in other ways (rotated by 90 degrees or at other orientations), and the space-related descriptors used herein may also be used for explanation accordingly.

It should be noted that, values of widths and distances described in the present invention are merely exemplary, and the present invention is not limited thereto. In some embodiments, such values may be adjusted according to an actual application situation of the present invention without departing from the inventive spirit of the present invention.

As used herein, terms “approximately”, “basically”, “substantially”, and “about” are used for describing and explaining a small variation. When being used in combination with an event or circumstance, the term may refer to a case in which the event or circumstance occurs precisely, and a case in which the event or circumstance occurs approximately. As used herein with respect to a given value or range, the term “about” or “similar” generally means being in the range of ±10%, ±5%, ±1%, or ±0.5% of the given value or range. The range may be indicated herein as from one endpoint to another endpoint or between two endpoints. Unless otherwise specified, all the ranges disclosed herein include endpoints. The term “substantially coplanar” may refer to two surfaces within a few micrometers (μm) positioned along the same plane, for example, within 10 μm, within 5 μm within 1 μm or within 0.5 μm positioned along the same plane. When reference is made to “substantially” the same numerical value or characteristic, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of the values.

Several embodiments of the present invention and features of details are briefly described above. The embodiments described in the present invention may be easily used as a basis for designing or modifying other processes and structures for realizing the same or similar objectives and/or obtaining the same or similar advantages introduced in the embodiments of the present invention. Such equivalent construction does not depart from the spirit and scope of the present invention, and various variations, replacements, and modifications can be made without departing from the spirit and scope of the present invention.

Although the subject of this specification is described by using specific preferred embodiments and exemplary embodiments, the foregoing accompanying drawings and descriptions of this specification describe merely typical non-limiting examples of embodiments of the subject. Therefore, the foregoing accompanying drawings and descriptions are not intended to limit the scope of this specification, and many alternatives and modifications will be apparent to a person skilled in the art.

As reflected in the claims below, aspects of the present invention may have fewer features than all features of an individual embodiment disclosed above. Therefore, the claims described below are hereby explicitly incorporated into the specific embodiments, and each claim itself represents an independent embodiment of the present invention. In addition, although some embodiments described herein include some features included in other embodiments, but do not include other features included in the other embodiments, a person skilled in the art should understand that, a combination of features of different embodiments shall fall within the scope of the present invention, and is intended to form different embodiments.