Semiconductor device and method of forming IPD in fan-out level chip scale package

A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming an integrated passive device (IPD) in a fan-out wafer level chip scale package (FO-WLCSP).

BACKGROUND OF THE INVENTION

Semiconductor devices perform a wide range of functions such as high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

Another goal of semiconductor manufacturing is to produce higher performance semiconductor devices. Increases in device performance can be accomplished by forming active components that are capable of operating at higher speeds. In high frequency applications, such as radio frequency (RF) wireless communications, integrated passive devices (IPDs) are often contained within the semiconductor device. Examples of IPDs include resistors, capacitors, and inductors. A typical RF system requires multiple IPDs in one or more semiconductor packages to perform the necessary electrical functions.

The IPDs are commonly formed external to the die within an interconnect structure of the package over a temporary carrier for structural support. The fully fabricated external IPD and die has a high cost. Adhesion problems have been found in the IPD passivation over the temporary carrier. In addition, the IPDs require more vertical space than the baseband semiconductor die and therefore impose a high aspect ratio gap between side-by-side IPD die and baseband die.

SUMMARY OF THE INVENTION

A need exists to simplify the manufacturing process and reduce cost in forming IPDs. Accordingly, in one embodiment, the present invention is a method of manufacturing a semiconductor device comprising the steps of providing a semiconductor wafer containing a plurality of semiconductor die, forming a first conductive layer over the semiconductor die, forming a resistive layer over the semiconductor die and the first conductive layer, forming a first insulating layer over the semiconductor die and resistive layer, singulating the semiconductor wafer to separate the semiconductor die, mounting the semiconductor die to a temporary carrier, depositing an encapsulant over the semiconductor die and temporary carrier, removing the temporary carrier and a portion of the encapsulant and first insulating layer, forming a second insulating layer over the encapsulant and first insulating layer, forming a second conductive layer over the first insulating layer and second insulating layer, forming a third insulating layer over the second insulating layer and second conductive layer, forming a third conductive layer over the third insulating layer and second conductive layer, and forming a fourth insulating layer over the third insulating layer and third conductive layer.

In another embodiment, the present invention is a method of manufacturing a semiconductor device comprising the steps of providing a semiconductor wafer containing a plurality of semiconductor die, forming a capacitor over the semiconductor die, singulating the semiconductor wafer to separate the semiconductor die, mounting the semiconductor die to a carrier, depositing an encapsulant over the semiconductor die and carrier, removing the carrier, forming a first insulating layer over the encapsulant and semiconductor die, forming a first conductive layer over the first insulating layer and capacitor, forming a second insulating layer over the first insulating layer and first conductive layer, forming a second conductive layer over the second insulating layer and first conductive layer, and forming a third insulating layer over the second insulating layer and second conductive layer.

In another embodiment, the present invention is a method of manufacturing a semiconductor device comprising the steps of providing a semiconductor die, forming a capacitor over the semiconductor die, depositing an encapsulant over the semiconductor die, and forming an interconnect structure over the encapsulant and semiconductor die. The interconnect structure includes an inductor formed a predetermined distance away from a footprint of the semiconductor die.

In another embodiment, the present invention is a semiconductor device comprising a semiconductor die and capacitor formed over the semiconductor die. An encapsulant is deposited over the semiconductor die. An interconnect structure is formed over the encapsulant and semiconductor die. The interconnect structure includes an inductor formed a predetermined distance away from a footprint of the semiconductor die.

DETAILED DESCRIPTION OF THE DRAWINGS

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

FIG. 1illustrates electronic device50having a chip carrier substrate or printed circuit board (PCB)52with a plurality of semiconductor packages mounted on its surface. Electronic device50may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1for purposes of illustration.

Electronic device50may be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device50may be a subcomponent of a larger system. For example, electronic device50may be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components.

For the purpose of illustration, several types of first level packaging, including wire bond package56and flip chip58, are shown on PCB52. Additionally, several types of second level packaging, including ball grid array (BGA)60, bump chip carrier (BCC)62, dual in-line package (DIP)64, land grid array (LGA)66, multi-chip module (MCM)68, quad flat non-leaded package (QFN)70, and quad flat package72, are shown mounted on PCB52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB52. In some embodiments, electronic device50includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIGS. 2a-2cshow exemplary semiconductor packages.FIG. 2aillustrates further detail of DIP64mounted on PCB52. Semiconductor die74includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die74. Contact pads76are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die74. During assembly of DIP64, semiconductor die74is mounted to an intermediate carrier78using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads80and wire bonds82provide electrical interconnect between semiconductor die74and PCB52. Encapsulant84is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die74or wire bonds82.

FIG. 2billustrates further detail of BCC62mounted on PCB52. Semiconductor die88is mounted over carrier90using an underfill or epoxy-resin adhesive material92. Wire bonds94provide first level packaging interconnect between contact pads96and98. Molding compound or encapsulant100is deposited over semiconductor die88and wire bonds94to provide physical support and electrical isolation for the device. Contact pads102are formed over a surface of PCB52using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads102are electrically connected to one or more conductive signal traces54in PCB52. Bumps104are formed between contact pads98of BCC62and contact pads102of PCB52.

InFIG. 2c, semiconductor die58is mounted face down to intermediate carrier106with a flip chip style first level packaging. Active region108of semiconductor die58contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region108. Semiconductor die58is electrically and mechanically connected to carrier106through bumps110.

BGA60is electrically and mechanically connected to PCB52with a BGA style second level packaging using bumps112. Semiconductor die58is electrically connected to conductive signal traces54in PCB52through bumps110, signal lines114, and bumps112. A molding compound or encapsulant116is deposited over semiconductor die58and carrier106to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die58to conduction tracks on PCB52in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die58can be mechanically and electrically connected directly to PCB52using flip chip style first level packaging without intermediate carrier106.

FIGS. 3a-3nillustrate, in relation toFIGS. 1 and 2a-2c, a process of forming an IPD structure over a semiconductor die.FIG. 3ashows a semiconductor wafer120with a base substrate material, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of semiconductor die or components124is formed on wafer120separated by saw streets126as described above.

FIG. 3bshows a cross-sectional view of a portion of semiconductor wafer120. Each semiconductor die124has an active surface128containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface128to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die124may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

An insulating or dielectric layer130is formed over active surface128of semiconductor die124using PVD, CVD, printing, spin coating, spray coating, or thermal oxidation. The insulating layer130can be one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta205), aluminum oxide (Al203), polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), or other suitable dielectric material. In one embodiment, insulating layer130is a thermal oxide. The insulating layer130serves to planarize the surface of semiconductor wafer120to improve step coverage of subsequent deposition and lithography processing steps. An optional conductive via 135 can be formed through insulating layer130.

An electrically conductive layer132is formed over insulating layer130using patterning and PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer132can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.

An optional resistive layer134is formed over insulating layer130and conductive layer132using PVD, CVD, or other suitable deposition process. Resistive layer134ais formed over insulating layer130, and resistive layer134bis formed over conductive layer132. In one embodiment, resistive layer134can be tantalum silicide (TaxSiy) or other metal silicides, TaN, nickel chromium (NiCr), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), or doped poly-silicon having a resistivity between 5 and 100 ohm/sq. Conductive layer132and resistive layer134aare electrically connected through conductive vias135to the circuits on active surface128of semiconductor die124.

InFIG. 3c, an insulating or dielectric layer136is formed over the entire active surface128, including insulating layer130and resistive layer134, using patterning and PVD, CVD, printing, spin coating, spray coating, or thermal oxidation. The insulating layer136can be one or more layers of SiO2, Si3N4, SiON, Ta205, Al203, polyimide, BCB, PBO, or other suitable dielectric material.

InFIG. 3d, semiconductor wafer120is singulated with saw blade or laser cutting tool138into individual semiconductor die144.

InFIG. 3e, a substrate or carrier140contains temporary or sacrificial base material such as silicon, polymer, polymer composite, metal, ceramic, glass, glass epoxy, beryllium oxide, or other suitable low-cost, rigid material for structural support. An optional interface layer142can be formed over carrier140as a temporary double-sided adhesive tape or bonding film. Using a pick and place operation, and leading with insulating layer136, the assembly144described inFIGS. 3a-3dis mounted to carrier140, as shown inFIGS. 3e-3f.

FIG. 3gshows an encapsulant or molding compound146deposited over semiconductor die124and carrier140using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable applicator. Encapsulant146can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant146is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

FIG. 3hshows an optional step with grinder147removing a portion of encapsulant146and bulk material from back surface148of semiconductor die124, opposite active surface128. The back surface148of semiconductor die124is co-planar with a top surface of encapsulant146following the optional grinding process.

Continuing fromFIG. 3g, carrier140and interface layer142are removed by chemical etching, mechanical peel-off, CMP, mechanical grinding, thermal bake, laser scanning, or wet stripping. The removal process further takes away a portion of insulating layer130and encapsulant146, as shown inFIG. 3i.

In a first photolithographic process, an insulating or passivation layer150is formed over insulating layer136and encapsulant146by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation, as shown inFIG. 3j. The insulating layer150can be one or more layers of SiO2, Si3N4, SiON, Ta205, Al203, or other material having suitable insulating properties. In one embodiment, insulating layer150is a polymer dielectric. The insulating layer150is patterned with a portion of the insulating layer being removed by an etching process to expose insulating layer136and resistive layer134aand134b. The insulating layer150can be used as a mask for subsequent processing steps.

InFIG. 3k, an electrically conductive layer152is formed over insulating layer136and insulating layer150using patterning and PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process to form individual portions or sections152a-152c. Conductive layer152can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. The individual portions of conductive layer152a-152ccan be electrically common or electrically isolated depending on the connectivity of the individual semiconductor die.

In a second photolithographic process, an insulating or passivation layer154is formed over insulating layer150and conductive layer152using patterning and PVD, CVD, printing, spin coating, spray coating, or thermal oxidation. The insulating layer154can be one or more layers of SiO2, Si3N4, SiON, Ta205, Al203, or other material having suitable insulating properties. In one embodiment, insulating layer154is a polymer dielectric. The insulating layer154is patterned with a portion of the insulating layer being removed by an etching process to expose conductive layer152, and optionally form vias to expose resistive layer134aand134b.

InFIG. 31, an electrically conductive layer156is formed over conductive layer152, insulating layer154, and resistive layer134using patterning and PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process to form individual portions or sections156a-156i. Conductive layer156can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. The individual portions of conductive layer156a-156ican be electrically common or electrically isolated depending on the connectivity of the individual semiconductor die.

In a third photolithographic process, an insulating or passivation layer158is formed over insulating layer154and conductive layer156using spin coating, PVD, CVD, printing, sintering, or thermal oxidation. The insulating layer158can be one or more layers of SiO2, Si3N4, SiON, Ta205, Al203, or other material having suitable insulating properties. In one embodiment, insulating layer158is a polymer dielectric. The insulating layer158is patterned with a portion of the insulating layer being removed by an etching process to expose conductive layer156a,156h, and156i.

An optional electrically conductive layer160is formed over conductive layer156a,156h, and156iusing PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer160can be one or more layers of Ti, TiW, NiV, Cr, CrCu, Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layer160is an under bump metallization (UBM) containing a multi-layer metal stack with an adhesion layer, barrier layer, and seed or wetting layer. The adhesion layer is formed over conductive layer156a,156h, and156iand can be Ti, TiN, TiW, Al, or chromium (Cr). The barrier layer is formed over the adhesion layer and can be made of Ni, nickel vanadium (NiV), platinum (Pt), palladium (Pd), TiW, or chromium copper (CrCu). The barrier layer inhibits the diffusion of Cu into the active area of the die. The seed layer can be Cu, Ni, NiV, Au, or Al. The seed layer is formed over the barrier layer and acts as an intermediate conductive layer between conductive layer156a,156h, and156iand subsequent solder bumps or other interconnect structure. UBM160provides a low resistive interconnect to conductive layer156a,156h, and156i, as well as a barrier to solder diffusion and seed layer for solder wettability.

InFIG. 3m, an electrically conductive bump material is deposited over UBM160using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to UBM160using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps162. In some applications, bumps162are reflowed a second time to improve electrical contact to UBM160. The bumps can also be compression bonded to UBM160. Bumps162represent one type of interconnect structure that can be formed over UBM160. The interconnect structure can also use bond wires, stud bump, micro bump, or other electrical interconnect. Conductive layers152and156, bumps162, and insulating layers150,154, and158constitute a build-up interconnect structure164of FO-WLCSP166.

The structures described inFIGS. 3i-3nconstitute a plurality of passive circuit elements or IPDs. In one embodiment, conductive layer156gand152b, insulating layer136, resistive layer134b, and conductive layer132constitute a metal insulator metal (MIM) capacitor168. Resistive layer134abetween conductive layer156gand156his a resistor element in the passive circuit. The individual sections of conductive layer156b-156ecan be wound or coiled in plan-view to produce or exhibit the desired properties of an inductor170. Conductive layer156b-156eis formed at least 50 micrometers away from the footprint of semiconductor die124to reduce inter-device interference with MIM capacitor168.FIG. 3nshows a bottom view of FO-WLCSP166.

The IPD structures168-170provide electrical characteristics needed for high frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetric Hi-Q resonant transformers, matching networks, and tuning capacitors. The IPDs can be used as front-end wireless RF components, which can be positioned between the antenna and transceiver. The inductor can be a hi-Q balun, transformer, or coil, operating up to 100 Gigahertz. In some applications, multiple baluns are formed over a same substrate, allowing multi-band operation. For example, two or more baluns are used in a quad-band for mobile phones or other global system for mobile (GSM) communications, each balun dedicated for a frequency band of operation of the quad-band device. A typical RF system requires multiple IPDs and other high frequency circuits in one or more semiconductor packages to perform the necessary electrical functions.

The IPD structure168formed over semiconductor die124simplifies the manufacturing process and reduces cost. The MIM capacitor168and resistor134bare formed on semiconductor die124prior to depositing encapsulant146. Other IPDs, such as inductor170are formed after encapsulation, which saves manufacturing cost by reducing the required number of lithography layers: one layer to etch back insulating layer150and form conductive layer152, one layer to etch back insulating layer154and form conductive layer156, and one layer to etch back insulating layer158and form bumps162. In addition, by only forming MIM capacitor and resistor134bon semiconductor die124, and forming the aspect ratio of the gap between side-by-side IPD die and baseband die can be reduced, seeFIG. 7.

FIG. 4shows an alternate embodiment continuing fromFIG. 3j, an electrically conductive layer172is formed over insulating layer136and insulating layer150using patterning and PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process to form individual portions or sections172a-172f. Conductive layer172can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. The individual portions of conductive layer172a-172fcan be electrically common or electrically isolated depending on the connectivity of the individual semiconductor die. For example, conductive layer172bis electrically connected to resistive layer134band conductive layer172d-172eis electrically connected to resistive layer134a.

An insulating or passivation layer174is formed over insulating layer150and conductive layer172using patterning and PVD, CVD, printing, spin coating, spray coating, or thermal oxidation. The insulating layer174can be one or more layers of SiO2, Si3N4, SiON, Ta205, Al203, or other material having suitable insulating properties. In one embodiment, insulating layer174is a polymer dielectric. The insulating layer174is patterned with a portion of the insulating layer being removed by an etching process to expose conductive layer172.

An electrically conductive layer176is formed over conductive layer172and insulating layer174using patterning and PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process to form individual portions or sections176a-176i. Conductive layer176can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. The individual portions of conductive layer176a-176ican be electrically common or electrically isolated depending on the connectivity of the individual semiconductor die. For example, conductive layer176aand176dare electrically connected to conductive layer172a, conductive layer176fis electrically connected to conductive layer172b, conductive layer176gis electrically connected to conductive layer172c-172d, conductive layer176his electrically connected to conductive layer172e-172f, and conductive layer176iis electrically connected to conductive layer172f.

An insulating or passivation layer178is formed over insulating layer174and conductive layer176using spin coating, PVD, CVD, printing, sintering, or thermal oxidation. The insulating layer178can be one or more layers of SiO2, Si3N4, SiON, Ta205, Al203, or other material having suitable insulating properties. In one embodiment, insulating layer178is a polymer dielectric. The insulating layer178is patterned with a portion of the insulating layer being removed by an etching process to expose conductive layer176a,176h, and176i.

An optional electrically conductive layer180is formed over conductive layer176a,176h, and176iusing PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer180can be one or more layers of Ti, TiW, NiV, Cr, CrCu, Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layer180is an UBM containing a multi-layer metal stack with an adhesion layer, barrier layer, and seed or wetting layer, similar to conductive layer160.

An electrically conductive bump material is deposited over UBM180using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to UBM180using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps182. In some applications, bumps182are reflowed a second time to improve electrical contact to UBM180. The bumps can also be compression bonded to UBM180. Bumps182represent one type of interconnect structure that can be formed over UBM180. The interconnect structure can also use bond wires, stud bump, micro bump, or other electrical interconnect. Conductive layers172and176, bumps182, and insulating layers150,174, and178constitute a build-up interconnect structure184of FO-WLCSP186.

The structures described inFIG. 4constitute a plurality of passive circuit elements or IPDs. In one embodiment, conductive layer172cand176g, insulating layer136, resistive layer134b, and conductive layer132constitute a MIM capacitor187. Resistive layer134abetween conductive layer172dand172eis a resistor element in the passive circuit. The individual sections of conductive layer176b-176ecan be wound or coiled in plan-view to produce or exhibit the desired properties of an inductor188.FIG. 5shows a bottom view of FO-WLCSP186.

FIG. 6shows an alternate embodiment similar toFIG. 4with etching of insulating layer136prior to singulation. An electrically conductive layer190is formed in the removed portion of insulating layer136using patterning and PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process to form individual portions or sections190a-190f. Conductive layer190can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. The individual portions of conductive layer190a-190fcan be electrically common or electrically isolated depending on the connectivity of the individual semiconductor die. For example, conductive layer190ais electrically connected to resistive layer134band conductive layer190c-190dis electrically connected to resistive layer134a.

FIG. 7shows semiconductor die194containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within its active surface to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die124, MIM capacitor168, and inductor170implemented as conductive layer156are electrically connected to semiconductor die194with traces196. Semiconductor die194and WLCSP166are mounted side-by-side within package200with traces196routed to external pins202. The IPD structure168formed over semiconductor die124simplifies the manufacturing process and reduces cost. The MIM capacitor168and resistor134bare formed on semiconductor die124prior to depositing encapsulant146. Other IPDs, such as inductor170are formed after encapsulation, which saves manufacturing cost by reducing the required number of lithography layers: one layer to etch back insulating layer150and form conductive layer152, one layer to etch back insulating layer154and form conductive layer156, and one layer to etch back insulating layer158and form bumps162. In addition, by only forming MIM capacitor and resistor134bon semiconductor die124, and forming the aspect ratio of the gap between side-by-side IPD die and baseband die can be reduced.