Semiconductor device and method of fabricating the same

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a selection element, a lower electrode pattern provided on the selection element to include a horizontal portion and a vertical portion; and a phase-changeable pattern on the lower electrode pattern. The vertical portion may extend from the horizontal portion toward the phase-changeable pattern and have a top surface, whose area is smaller than that of a bottom surface of the phase-changeable pattern.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-0109081, filed on Aug. 21, 2014, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

FIELD OF THE INVENTION

Example embodiments of the inventive concepts relate to a semiconductor device and a method of fabricating the same, and in particular, to a semiconductor device including a phase-changeable pattern and a method of fabricating the same.

BACKGROUND

Next-generation semiconductor memory devices (e.g., a ferroelectrie random access memory (FRAM), a magnetic random access memory (MRAM), a phase-change random access memory (PRAM), and so forth) are being developed to meet increasing demands for high performance and low power consumption of semiconductor memory devices. In the next-generation semiconductor memory devices, a memory element may be formed of a non-volatile and variable resistance material. In other words, the memory element may exhibit an electric resistance that can be selectively changed depending on a current or voltage applied thereto and can be preserved even when a current or voltage is not supplied.

PRAMs are of particular interest because they have the potential for high operation speed and high integration density. Accordingly, intensive research is being performed in the area of PRAM device.

SUMMARY

Example embodiments of the inventive concepts provide a semiconductor device with an improved operation current property and a method of fabricating the same.

Other example embodiments of the inventive concepts provide a semiconductor device with higher reliability and a method of fabricating the same.

According to example embodiments of the inventive concepts, a semiconductor device may include a substrate, on which a plurality of memory cells are provided, and an insulating pattern provided on the substrate to define a feature of the memory cells. Each of the memory cells may include a selection element on the substrate, a lower electrode pattern provided on the selection element to have a horizontal portion and a vertical portion, a phase-changeable pattern on the lower electrode pattern, and a protection pattern interposed between the lower electrode pattern and the insulating pattern and extended to cover a side surface of the phase-changeable pattern. The vertical portion may be extended from the horizontal portion toward the phase-changeable pattern and may have a top surface having an area smaller than that of a bottom surface of the phase-changeable pattern.

In example embodiments, the horizontal portion may have a thickness that is substantially the same as a width of the vertical portion.

In example embodiments, the device may further include a spacer pattern provided on a side surface of the phase-changeable pattern.

In example embodiments, the vertical portion may have a width ranging from about 1 nm to about 10 nm.

In example embodiments, the insulating pattern may be provided in first and second trenches crossing each other on the substrate, and the memory cells may be separated from each other by the first and second trenches.

In example embodiments, the device may further include word lines extending parallel to a direction, on the substrate, and bit lines extending parallel to another direction substantially orthogonal to the direction, the bit lines crossing the word lines. The memory cells may be provided at respective intersections of the word lines and the bit lines.

In example embodiments, the memory cells disposed on two adjacent ones of the word lines may be provided to have bilateral symmetry with respect to a line therebetween.

In example embodiments, the vertical portions disposed on each of the word lines may be spaced apart from each other by a substantially same distance.

In example embodiments, when viewed in a plan view, the vertical portion may be provided to have a longitudinal axis parallel to the word lines.

According to example embodiments of the inventive concepts, a method of fabricating a semiconductor device may include forming a selection device layer, a first sacrificial pattern, and a second sacrificial pattern on a substrate, forming a first trench to penetrate the first and second sacrificial patterns, laterally etching a side surface of the first sacrificial pattern to form a recess region exposing a bottom surface of the second sacrificial pattern, the recess region being connected to the first trench, conformally forming a lower electrode pattern in the recess region to cover a top surface of the selection device layer, the side surface of the first sacrificial pattern, and the bottom surface of the second sacrificial pattern, forming a first protection pattern in the first trench and the recess region to cover the lower electrode pattern and the second sacrificial pattern, and forming an insulating pattern in the first trench to cover the first protection pattern.

In example embodiments, the method may further include forming a second trench to penetrate the first sacrificial pattern and the second sacrificial pattern, removing the first sacrificial pattern exposed by the second trench to expose the lower electrode pattern, forming a second protection pattern in the second trench to cover the lower electrode pattern, and forming a second insulating pattern in the second trench to cover the second protection pattern.

In example embodiments, the method may further include forming second mask layers spaced apart from each other on the second sacrificial pattern and a first mask layer interposed between the second mask layers. The forming of the first trench may include etching the second sacrificial pattern exposed by the first and second mask layers.

In example embodiments, the forming of the second trench may include removing the first mask layer to expose the second sacrificial pattern, and removing the second sacrificial pattern exposed by the second mask layer.

In example embodiments, the method may further include removing the second sacrificial pattern to form a contact hole exposing the first protection pattern, and forming a phase-changeable pattern in the contact hole.

In example embodiments, the forming of the contact hole may include removing the lower electrode pattern from a top surface of the first protection pattern to expose the first protection pattern.

In example embodiments, a portion of the phase-changeable pattern may be in contact with the lower electrode pattern, and other portion of the phase-changeable pattern may be contact with the first and second protection patterns.

In example embodiments, the method may further include forming a spacer pattern on a side surface of the contact hole.

In example embodiments, the forming of the lower electrode pattern may include depositing a lower electrode layer in the first trench and the recess region to have a thickness ranging from 1 nm to 10 nm, and etching the lower electrode layer to remove the lower electrode layer from a side surface of the second sacrificial pattern.

According to example embodiments of the inventive concepts, a semiconductor device may include a substrate, a selection device layer on the substrate, an ohmic pattern on the selection device layer, a phase-changeable pattern on the ohmic pattern, a lower electrode pattern provided between the ohmic pattern and the phase-changeable pattern, the lower electrode pattern including a horizontal portion covering a portion of a top surface of the ohmic pattern and a vertical portion extending from the horizontal portion and being in contact with the phase-changeable pattern, the vertical portion exposing a bottom surface of the phase-changeable pattern at both sides thereof, a first protection pattern extending from a side surface of the lower electrode pattern to a side surface and the bottom surface of the phase-changeable pattern, and a second protection pattern extending from other side surface of the lower electrode pattern to other side surface and the bottom surface of the phase-changeable pattern. The bottom surface of the phase-changeable pattern on the first protection pattern may be positioned at a level that is the same as or higher than that of a top surface of the vertical portion, and the bottom surface of the phase-changeable pattern on the second protection pattern may be positioned at a level that is higher than the bottom surface of the phase-changeable pattern on the first protection pattern.

In example embodiments, the vertical portion may have a width that may be substantially equal to a thickness of the horizontal portion.

According to example embodiments of the inventive concepts, a semiconductor device comprises a variable resistance device having a first surface, a second surface opposing the first surface and a third surface interposed therebetween. An electrode has a horizontal portion substantially parallel to the third surface, a vertical portion connected to the horizontal portion and substantially orthogonal to the horizontal portion, and the vertical portion is connected to the third surface. A first trench is proximal to the first surface of the variable resistance device and has a first recessed portion proximal to a first surface of the vertical portion of the electrode. A second trench is proximal to the second surface of the variable resistance device and has a second recessed portion proximal to the second surface of the vertical portion of the electrode. The second surface opposed the first surface.

In example embodiments, the variable resistance device includes a phase-changeable material.

In example embodiments, the first recessed portion has a first length substantially equal to a length of the vertical portion of the electrode, and the second recessed portion has a second length greater than the length of the vertical portion of the electrode.

In example embodiments, the first recessed portion and the second recessed portion are bilaterally symmetrical.

In example embodiments, the vertical portion of the electrode is connected to the third surface of the variable resistance device at a location offset from a midpoint of the third surface.

DETAILED DESCRIPTION

Accordingly, the cross-sectional view(s) illustrated herein provide support for a plurality of devices according to various embodiments described herein that extend along two different directions in a plan view and/or in three different directions in a perspective view. For example, when a single active region is illustrated in a cross-sectional view of a device/structure, the device/structure may include a plurality of active regions and transistor structures (or memory cell structures, gate structures, etc., as appropriate to the case) thereon, as would be illustrated by a plan view of the device/structure.

Hereinafter, a phase changeable random access memory (PRAM) device will be described as an example of semiconductor devices according to example embodiments of the inventive concepts, but example embodiments of the inventive concepts may not be limited thereto. For example, the inventive concepts may be used to realize other variable resistance memory devices, such as a resistive memory device (RRAM), a magnetic RAM (MRAM), and a ferroelectric RAM (FRAM). Furthermore, the inventive concepts may be used to realize a dynamic RAM (DRAM), a static RAM (SRAM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a FLASH memory device.

In an embodiment of the present inventive concepts, a three-dimensional (3D) memory array is provided. The 3D memory array is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate and circuitry associated with the operation of those memory cells, whether such associated circuitry is above or within such substrate. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array.

The following patent documents, which are hereby incorporated by reference, describe suitable configurations for three-dimensional memory arrays, in which the three-dimensional memory array is configured as a plurality of levels, with word lines and/or bit lines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Pat. Pub. No. 2011/0233648.

FIG. 1is a schematic circuit diagram illustrating a memory cell array of a semiconductor device according to example embodiments of the inventive concepts.

Referring toFIG. 1, a memory cell array may include a plurality of word lines WL1-WLm, a plurality of bit lines BL1-BLn, and a plurality of memory cells MC. The memory cells MC may be located at respective intersections of the word lines WL1-WLm and the bit lines BL1-BLn.

In example embodiments, each of the memory cells MC may include a memory device Rp and a selection device D. The memory device Rp may be connected between a corresponding one the bit lines BL1-BLn and the selection device D, and the selection device D may be located between the memory device Rp and a corresponding one the word lines WL1-WLm.

The memory device Rp may be, or may include, a variable resistance device, whose resistance state can be switched by an electric pulse applied thereto. For example, the memory device Rp may include a phase-changeable material, whose crystal structure can be changed depending on an amount of current passing therethrough. For example, the phase-changeable material may be one of GeSbTe, GeTeAs, SnTeSn, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and/or InSbTe, but example embodiments of the inventive concepts may not be limited thereto.

Depending on a heating temperature and/or a quenching speed, the phase-changeable material may have an amorphous structure having a relatively high resistance or a crystalline structure having a relatively low resistance. The crystal structure of the phase-changeable material may be switched to one of the two structures by adjusting Joule's heat. By adjusting an amount of current passing through the phase-changeable material, it is possible to control a Joule heating process and thereby to change a temperature of the phase-changeable material and the crystal structure of the phase-changeable material. The change in crystal structure, or phase, of the phase-changeable material can be used to selectively change data stored in the memory device Rp.

As another example, the memory device Rp may be configured to include one of perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials, instead of the phase-changeable material.

In example embodiments, the selection device D may be used to control an amount of current flowing through the memory device Rp and the corresponding one of the word lines WL1-WLm, and such a switching operation of the selection device D may be controlled by a voltage applied to the corresponding one of the word lines WL1-WLm.

As an example, the selection device D may be a PN or PIN junction diode, whose anode and cathode are respectively connected to the memory device Rp and the corresponding one of the word lines WL1-WLm. In this case, if a difference in voltage between the anode and the cathode becomes greater than a threshold voltage of the diode or the diode is turned on, there may be an electric current passing through the memory device Rp.

As other example, the selection device D may be a metal-oxide-semiconductor (MOS) transistor. For example, the selection device D may be an NMOS transistor, whose gate electrode is connected to the corresponding one of the word lines WL1-WLm. In this case, the voltages of the word lines WL1-WLm may be controlled to selectively form a current flow passing through the memory device Rp. In another example, the selection device D may be a PMOS transistor, where the voltages of the word lines WL1-WLm would have a reversed polarity relative to the embodiments using an NMOS transistor for the selection device D. As still other example, the selection device D may be provided in the form of a PNP or NPN-type bipolar transistor.

Hereinafter, a semiconductor device according to example embodiments of the inventive concepts will be described.

FIG. 2Ais a plan view illustrating a semiconductor device according to example embodiments of the inventive concepts.FIG. 2Bis a sectional view taken along lines I-I′ and II-IF ofFIG. 2A.FIG. 2Cis an enlarged view of a region III ofFIG. 2B. For the sake of brevity, the elements and features of this example that are similar to those previously shown and described will not be described in much further detail.

Referring toFIG. 2AandFIG. 2B, a semiconductor device1may include a substrate100and word lines WL, bit lines BL, and memory cells MC provided on the substrate100. The substrate100may include a single crystalline semiconductor material. For example, the substrate100may be a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, and/or a silicon-germanium substrate, but the substrate100may not be limited thereto.

The word lines WL may extend parallel to a second direction D2, on the substrate100. The second direction D2may be parallel to a top surface of the substrate100. The word lines WL may be configured to have the same features as those of the word lines WL1-WLm described with reference toFIG. 1.

The memory cells MC may be located at respective intersections of the word lines WL and the bit lines BL. When viewed in a plan view, the memory cells MC may be overlapped with the word lines WL. For example, all the memory cells MC located on each of the word lines WL may have substantially the same width as the corresponding one of the word lines WL.

The memory cells MC may be defined or delimited by insulating patterns111,112,113, and114. The insulating patterns111,112,113, and114may be interposed on the substrate100and between the word lines WL to enclose the memory cells MC. The insulating patterns111,112,113, and114may be formed of, or include at least one of, Tonen SilaZene (TOSZ), tetraethyl orthosilicate (TEOS), and/or Undoped Silcate Glass (USG). The insulating patterns111,112,113, and114may be extended into recess regions R1and R2. The insulating patterns111,112,113, and114may be provided in trenches T1, T2, T3, and T4. The first and second trenches, T1and T2, may extend parallel to the second direction D2, and the third and fourth trenches, T3and T4, may extend parallel to a first direction D1. Here, the second direction D2may be parallel to the top surface of the substrate100and cross the first direction D1. In one embodiment, the direction D2crosses the direction D1at a substantially orthogonal angle.

Each of the memory cells MC may include a selection element200, an ohmic pattern250, a lower electrode pattern300, a phase-changeable pattern500, a spacer pattern550, protection patterns410,420,430, and440, and an upper electrode pattern600. The selection elements200may be provided on the word lines WL to serve as the selection device D ofFIG. 1. The selection element200may be formed of, or include, a poly silicon layer. For example, the selection element200may include first and second semiconductor patterns (not shown), which are doped to have different conductivity types from each other. The selection element200may have a thickness ranging from about 60 nm to about 100 nm.

The ohmic pattern250may be interposed between the selection element200and the lower electrode pattern300. The ohmic pattern250may include a metal silicide layer (e.g., titanium silicide, cobalt silicide, tantalum silicide, nickel silicide, or tungsten silicide). The ohmic pattern250may contribute to reduce electric resistance between the selection element200and the lower electrode pattern300. In certain embodiments, the ohmic pattern250may be omitted.

The lower electrode pattern300may be provided on the ohmic pattern250to be in contact with the phase-changeable pattern500. As shown inFIG. 2C, the lower electrode pattern300may have an “L”-shaped section. The lower electrode pattern300may include a horizontal portion310and a vertical portion320vertically extending from the horizontal portion310. The horizontal portion310may cover a top surface of the ohmic pattern250. The horizontal portion310may have a thickness ranging from about 1 nm to about 10 nm. The vertical portion320may extend from the horizontal portion310toward the phase-changeable pattern500, for example, in a third direction D3and may be in contact with a bottom surface500bof the phase-changeable pattern500. Here, the third direction D3may be normal to the top surface of the substrate100. The vertical portion320may have a thickness ranging from about 1 nm to about 10 nm. A width A1of the vertical portion320may be substantially equal to a thickness A2of the horizontal portion310. In the present specification, the expression “substantially equal in thickness or width” means that a variation in thickness between two elements under consideration is smaller than a variation in deposition thickness of a layer, which is formed by a single deposition process and may be used for one or both of the two elements. The vertical portion320may have an occupying area smaller than that of the horizontal portion310. The lower electrode pattern300may be formed of, or include, a conductive material. As an example, the lower electrode pattern300may include at least one of high-melting point metals, such as TiN, TaN, TiON, WSi, WN, and/or TiW. As another example, the lower electrode pattern300may include at least one of metal nitrides, such as TiAIN, TiSiN, TaSiN, and/or TaAlN.

The protection patterns410,420,430, and440may be provided on the substrate100to cover side surface of the lower electrode patterns300. The protection patterns410,420,430, and440may be interposed between the lower electrode patterns300and the insulating patterns111,112,113, and114. The lower electrode pattern300may be spaced apart from the insulating patterns111,112,113, and114. The protection patterns410,420,430, and440may prevent the lower electrode pattern300from being oxidized in the fabrication process of the semiconductor device1. The protection patterns410,420,430, and440may include a material (e.g., silicon nitride and/or silicon oxynitride) having an etch selectivity with respect to the lower electrode patterns300. The protection patterns410,420,430, and440may be extended to cover side surfaces of the phase-changeable patterns500.

The phase-changeable patterns500may be provided on the lower electrode patterns300, respectively. The bottom surface500bof the phase-changeable pattern500may be formed to have a staircase profile. The phase-changeable pattern500may serve as the memory device Rp ofFIG. 1. The phase-changeable pattern500may include at least one of the phase-changeable materials enumerated in the previous description ofFIG. 1. As another example, the phase-changeable pattern500may include at least one of perovskite compounds or transition metal oxide materials. In addition, the phase-changeable pattern500may further contain dopants, such as C, N, Si, O, N, and/or B.

In the first direction D1, a width B1of the phase-changeable pattern500may be greater than the width A1of the vertical portion320of the lower electrode pattern300. A top surface300aof the vertical portion320of the lower electrode pattern300may have an area smaller than that of the bottom surface500bof the phase-changeable pattern500. For example, the area of the top surface300aof the vertical portion320may be about 54 nm2, and the area of the bottom surface500bof the phase-changeable pattern500may be about 143 nm2. The areas may be mean values of areas of the memory cells MC. For example, the width A1of the vertical portion320may be about 4 nm, and a length thereof may be about 13.5 nm. The bottom surface500bof the phase-changeable pattern500may have a diameter of about 6.75 nm. A portion of the bottom surface500bof the phase-changeable pattern500may be in contact with the lower electrode pattern300, and another portion of the bottom surface500bmay be in contact with the first and second protection patterns410and420. If a contact area between the phase-changeable pattern500and the lower electrode pattern300increases, a higher current may be needed to perform a program operation of the semiconductor device1. In example embodiments, a contact area between the phase-changeable pattern500and the lower electrode pattern300can be reduced, compared with the case that the top surface300aof the lower electrode pattern300has substantially the same area as the bottom surface5006of the phase-changeable pattern500. Thus, it is possible to reduce an amount of current required for a program operation of the semiconductor device1and thereby improve operational characteristics of the semiconductor device1.

As shown inFIG. 2B, the spacer patterns550may be disposed between the phase-changeable patterns500and the insulating patterns111,112,113, and114. The spacer patterns550may cover the side surfaces of the phase-changeable patterns500. When viewed in a plan view, each of the spacer patterns550may be provided to enclose a corresponding one of the phase-changeable patterns500. The spacer patterns550may include an insulating material, (e.g., silicon oxide, silicon nitride, and/or silicon oxynitride). As another example, the spacer patterns550may include a high-k dielectric material (e.g., titanium oxide, zirconium oxide, magnesium oxide, and/or hafnium oxide). The spacer pattern550makes it possible to further reduce the contact area between the lower electrode pattern300and the upper electrode pattern600. Accordingly, it is possible to further reduce an amount of current required for the program operation of the semiconductor device1.

The upper electrode pattern600may be disposed on the phase-changeable pattern500. The spacer pattern550may extend in between the upper electrode pattern600and the protection patterns410,420,430, and440. The upper electrode pattern600may include at least one of conductive materials or metal nitride materials (e.g., titanium nitride).

The bit lines BL may be provided on the substrate100to extend parallel to the first direction D1or cross the word lines WL. In one embodiment, the bit lines BL cross the word lines WL at a substantially orthogonal angle. The bit lines BL may be configured to have substantially the same features as those of the bit lines BL1-BLn described with reference toFIG. 1. The bit lines BL may include at least one of conductive metallic materials (e.g., copper). The bit lines BL may be provided on the insulating patterns111,112,113, and114, and each of them may be connected in common to or be in contact with the memory cells MC arranged in a row. In the case where the phase-changeable pattern500is in direct contact with the bit line BL, a material contained in the phase-changeable pattern500may be reacted with a material contained in the bit line BL. However, according to example embodiments of the inventive concepts, such an unintended reaction between the phase-changeable pattern500and the bit lines BL can be prevented by the upper electrode pattern600.

Hereinafter, the memory cells MC will be described in more detail. As shown inFIG. 2A, the memory cells MC may be two-dimensionally arranged along both the first and second directions D1and D2. When viewed in a plan view, the vertical portions320of the memory cells MC may be disposed to form an arrangement as shown inFIG. 2A. As an example, the vertical portions320of the memory cells MC may be arranged to form a plurality of columns, each of which is parallel to the second direction D2or the word lines WL. In each column, the vertical portions320of the memory cells MC may be spaced apart from each other in the second direction D2by substantially the same distance. When viewed in a plan view, each of the vertical portions320may be formed in such a way that a longitudinal axis thereof is parallel to the second direction D2. In each pair of adjacent columns, the memory cells MC may be formed in such a way that the vertical portions320thereof are bilaterally symmetric with respect to a line that is both equidistant therefrom and parallel to the pair of adjacent columns. Further, as shown inFIG. 2B, in each pair of adjacent columns, the memory cells MC may be formed in such a way that vertical sections thereof are bilaterally symmetric with respect to the line equidistant therefrom. For example, in each pair of adjacent columns, the lower electrode patterns300may also be formed to have the bilateral symmetry with respect to the equidistant line thereof.

Referring toFIG. 2AandFIG. 2B, the memory cells MC may have substantially the same occupying area and shape. When viewed in a plan view, each of the memory cells MC may have a square shape. Further, the memory cells MC may be disposed to have the same pitch. In certain embodiments, a width of each of the memory cells MC may be substantially equal to a distance between adjacent ones of the memory cells MC.

The vertical portions320of the memory cells MC may have substantially the same size or area. For example, the widths A1of the vertical portions320may be substantially the same in the first direction D1. Further, the top surfaces300aof the vertical portions320may have substantially the same occupying area. The memory cells MC may be provided in such a way that there is substantially no difference in contact area between the lower electrode pattern300and the phase-changeable pattern500. This allows substantially the same amount of current to flow through each of the memory cells MC in the program operation of the semiconductor device1. Accordingly, the semiconductor device1can be operated with improved reliability. because the current density of the memory cell with the largest contact area will not be too low to cause ineffective programming, and the current density of the memory cell with the smallest contact area will not be too high, which may result in damage.

A method of fabricating a semiconductor device according to example embodiments of the inventive concepts will be described below.

FIG. 3AthroughFIG. 3F,FIG. 3HthroughFIG. 3N,FIG. 3P, andFIG. 3Qare sectional views illustrating a method of fabricating a semiconductor device, according to example embodiments of the inventive concepts.FIG. 3GandFIG. 3Oare enlarged views of regions III ofFIG. 3FandFIG. 3N, respectively. For the sake of brevity, the elements and features of this example that are similar to those previously shown and described will not be described in much further detail.

Referring toFIG. 3A, a word line layer WLa, a selection device layer201, an ohmic layer251, a first sacrificial pattern710, an etch stop layer715, a second sacrificial pattern720, and mask layers810,820,830, and840may be sequentially formed on the substrate100. The substrate100may be formed to have substantially the same features as that ofFIG. 2AthroughFIG. 2C. The word line layer WLa may be formed of, or include, at least one conductive material (e.g., titanium nitride).

The selection device layer201may be formed on the word line layer WLa and may include a diode, which was described as an example of the selection device D ofFIG. 1. The selection device layer201may be formed of, or include, a polysilicon layer. For example, the selection device layer201may include first and second semiconductor layers (not shown), which are doped to have different conductivity types from each other. The selection device layer201may have a thickness ranging from about 60 nm to 100 nm. The ohmic layer251may be formed on the selection device layer201. The ohmic layer251may be formed of, or include, at least one metal silicide (e.g., tungsten silicide) and/or metal nitride (e.g., titanium nitride).

The first sacrificial pattern710may be formed on the ohmic layer251. The first sacrificial pattern710may be formed of, or include, a material that is different from those of the ohmic layer251, the etch stop layer715, the second sacrificial pattern720, and the first and second mask layers830and840. For example, the first sacrificial pattern710may include a material having an etch selectivity with respect to the ohmic layer251, the etch stop layer715, the second sacrificial pattern720, and the mask layers810,820,830, and840. As an example, the first sacrificial pattern710may be formed of, or include, a silicon oxide layer. The first sacrificial pattern710may have a thickness ranging from about 20 nm to 50 nm.

The etch stop layer715may be formed on the first sacrificial pattern710. The etch stop layer715may be formed of, or include, a material (e.g., silicon nitride and/or silicon oxynitride) having an etch selectivity with respect to the first sacrificial pattern710. In certain embodiments, the formation of the etch stop layer715may be omitted. The second sacrificial pattern720may be formed on the etch stop layer715. As an example, the second sacrificial pattern720may be a polysilicon layer, which is formed by a deposition process and has a thickness ranging from about 70 nm to 100 nm.

A lower mask layer810, a buffer mask layer820, a first mask layer830, and a second mask layer840may be sequentially formed on the substrate100. The lower mask layer810may include silicon nitride and may have a thickness of about 50 nm. The buffer mask layer820may include an amorphous carbon layer (ACL). The first mask layer830may be formed on a top surface of the buffer mask layer820and may include a material having an etch selectivity with respect to the buffer mask layer820. For example, the first mask layer830may include a metal oxide layer (e.g., aluminum oxide). The second mask layer840may be formed on a top surface of the lower mask layer810to cover a side surface of the buffer mask layer820and the first mask layer830. The second mask layer840may be conformally formed by, for example, an atomic layer deposition (ALD) process and may include a silicon oxide layer.

Referring toFIG. 3B, an opening800may be formed in the second mask layer840to expose the second sacrificial pattern720. For example, the opening800may be formed by pattering the second mask layer840using an etching process. In certain embodiments, the etching of the second mask layer840may be performed to expose a top surface of the first mask layer830. After the etching of the second mask layer840, the lower mask layer810exposed by the opening800may be further etched, and thus, the opening800may be expanded into the lower mask layer810to expose the second sacrificial pattern720.

Referring toFIG. 3C, a first trench T1may be formed to penetrate the second sacrificial pattern720, the etch stop layer715, and the first sacrificial pattern710. For example, the second sacrificial pattern720, the etch stop layer715, and the first sacrificial pattern710may be etched using the first and second mask layers830and840as an etch mask. As an example, the second sacrificial pattern720exposed by the opening800may be etched to expose portions of the etch stop layer715. The exposed portions of the etch stop layer715may be etched using the first and second mask layers830and840as an etch mask, and thus, the first trench T1may be expanded into the etch stop layer715. The first sacrificial pattern710exposed by the etch stop layer715may be etched, and thus, the first trench T1may be expanded into the first sacrificial pattern710to expose a top surface of the ohmic layer251. In example embodiments, the first trench T1may be formed in such a way that the first sacrificial pattern710has a width W1ranging from about 60 nm to 80 nm in the first direction D1. The widths of the etch stop layer715and the second sacrificial pattern720may be substantially the same as the width W1of the first sacrificial pattern710.

Referring toFIG. 3Din conjunction withFIG. 3C, a recess sacrificial pattern711may be formed by laterally etching side surfaces of the first sacrificial pattern710. The etching process may be performed to selectively etch the first sacrificial pattern710. As an example, in the case where the first sacrificial pattern710is formed of silicon oxide, the etching of the first sacrificial pattern710may be performed using a fluorine-containing gas. A width W2of the recess sacrificial pattern711may be smaller than the width W1of the first sacrificial pattern710ofFIG. 3C. The width W2of the recess sacrificial pattern711can be controlled by changing process conditions in the etching of the first sacrificial pattern710. The etching of the first sacrificial pattern710may be performed to substantially prevent the second sacrificial pattern720and the etch stop layer715from being etched, and thus, the recess sacrificial pattern711may be formed to expose a bottom surface715bof the etch stop layer715. A first recess region R1may be formed along a side surface711cof the recess sacrificial pattern711and between the ohmic layer251and the etch stop layer715. The first recess region R1may be an edge region of the first sacrificial patterns710removed by the etching process. The first trench T1may be expanded to include the first recess region R1.

Referring toFIG. 3E, a lower electrode layer301may be formed in the first recess region R1to conformally cover the side surface711cof the recess sacrificial pattern711, an exposed portion of the bottom surface715bof the etch stop layer715, and a top surface251aof the ohmic layer251. For example, the lower electrode layer301may be formed of a material (e.g., titanium nitride), which can be formed by a deposition technique with a good step coverage property, conformally (i.e., of a substantially uniform thickness). In the present specification, the expression “substantially uniform thickness” means that a variation in thickness between two elements under consideration is smaller than a variation in thickness of a layer, which is formed by a single deposition process and may be used for one or both of the two elements. For example, the lower electrode layer301may be formed to have a thickness ranging from about 1 nm to 10 nm (in particular, of about 4 nm). The lower electrode layer301may be formed to have a thickness variation of about 1% or lower. The lower electrode layer301may be formed to conformally cover the first trench T1and the opening800. For example, the lower electrode layer301may include portions covering the top surface251aof the ohmic layer251, the side surfaces of the second sacrificial pattern720, the etch stop layer715, and the second mask layer840, and the top surface of the first mask layer830.

Referring toFIG. 3FandFIG. 3Gin conjunction withFIG. 3E, the lower electrode layer301may be etched to form the lower electrode pattern300. For example, an etching process may be performed to remove the lower electrode layer301from the side surface of the etch stop layer715, the side surface of the second sacrificial pattern720, and the side and top surfaces of the mask layers810,820,830, and840. In certain embodiments, the ohmic layer251exposed by the first and second mask layers830and840may also be etched in the process of etching the lower electrode layer301. Since a portion of the lower electrode layer301in the first recess region R1is not exposed in the etching process, the lower electrode pattern300may be locally formed in the first recess region R1. The lower electrode pattern300may include the horizontal portion310, the vertical portion320, and an upper horizontal portion330. The horizontal portion310may be formed on an edge portion of the ohmic layer251to partially cover the top surface251aof the ohmic layer251. The vertical portion320may be formed on the side surface711cof the recess sacrificial pattern711and may extend in the third direction D3. The upper horizontal portion330may be formed on the exposed bottom surface715bof the etch stop layer715. A plurality of lower electrode patterns300may be formed on the recess sacrificial pattern711. For example, a plurality of the lower electrode patterns300may be formed on each of both side surfaces of the recess sacrificial pattern711to have bilateral symmetry with respect to a line equidistant therefrom. By contrast, if the lower electrode patterns300are patterned using a photolithography process and an etching process, sizes of the lower electrode patterns300and its uniformity may be limited by resolution in the photolithography process. However, in the case where, as described with respect toFIG. 3C, the lower electrode layer301is formed to have a uniform thickness, the width A1of the vertical portion320may be substantially equal to the thickness A2of the horizontal portion310and the thickness of the upper horizontal portion330.

For example, in the case where the lower electrode patterns300are formed using a photolithography process, the vertical portions320of the lower electrode patterns300may have a width of about 13.5 nm. However, in the case where a deposition process is used, the vertical portions320of the lower electrode patterns300may have a width A1that is about one-third of that of the case when the photolithography process is used. For example, the widths A1of the vertical portions320may range from about 1 nm to 10 nm (in particular, about 4 nm). In example embodiments, each of the thicknesses A2of the horizontal portions310and the widths A1of the vertical portions320may range from about 1 nm to 10 nm (in particular, about 4 nm).

According to example embodiments of the inventive concepts, the lower electrode patterns300may be formed using an atomic layer deposition process, and in this case, uniformity in size of the lower electrode patterns300may be determined depending on a deposition thickness of the lower electrode layer301. Accordingly, the lower electrode patterns300may have higher size uniformity than that in the photolithography process. Further, the top surfaces300aof the lower electrode patterns300may have substantially the same area. For example, the top surfaces300aof the lower electrode patterns300can be formed in such a way that a ratio of the maximum occupying area to the minimum occupying area is about 1.36. By contrast, in the case where the lower electrode patterns300are formed using the photolithography process, the ratio may be about 1.86. That is, according to example embodiments of the inventive concepts, it is possible to improve uniformity in occupying area or size of the lower electrode patterns300.

The first protection pattern410may be formed on the lower electrode patterns300. The first protection pattern410may be deposited to conformally cover the first trench T1. The first protection pattern410may include a portion positioned in the first recess region R1. As shown inFIG. 3G, the first protection pattern410may be formed proximal to the bottom surface715bof the etch stop layer715, the side surface711cof the recess sacrificial pattern711, and the top surface251aof the ohmic layer251to cover the lower electrode patterns300. Referring toFIG. 3F, the first protection pattern410may extend to cover the top surface of the selection device layer201, the side surface of the ohmic pattern250, the side surface of the etch stop layer715, the side surface of the second sacrificial pattern720, and the side and top surfaces of the mask layers810and820. The first protection pattern410may be formed using an atomic layer deposition and/or chemical vapor deposition process to have a thickness ranging from about 1 nm to about 5 nm. The first protection pattern410may include a material (e.g., silicon nitride) having an etch selectivity with respect to the lower electrode patterns300.

Referring toFIG. 3H, the selection device layer201and the word line layer WLa may be etched to extend the first trench T1into the selection device layer201and the word line layer WLa. For example, the first protection pattern410may be removed from top surfaces of the first and second mask layers830and840and the selection device layer201. The etching process of the selection device layer201and the word line layer WLa may be performed using the first and second mask layers830and840as an etch mask. The first trench T1may be formed to expose the top surface of the substrate100. Alternatively, the first trench T1may be formed to extend into the substrate100. The first protection pattern410in the first recess region R1may not be exposed to the etching process and thus it may remain in the first recess region R1.

The first insulating pattern111may be formed on the substrate100to fill the first trench T1. The first insulating pattern111may be formed of, or include, an insulating material having a good step coverage property (e.g., Tonen SilaZene (TOSZ), tetraethyl orthosilicate (TES), and/or Undoped Silcate Glass (USG)). Accordingly, the first insulating pattern111may be formed to cover the first protection pattern410into the first recess region R1. The lower electrode patterns300may not be in contact with the first insulating pattern111by the first protection pattern410interposed therebetween. In the case where the first protection pattern410is omitted, the lower electrode patterns300may be exposed to the process for etching the selection device layer201and the word line layer WLa and/or the process for deposition of the first insulating pattern111. According to example embodiments of the inventive concepts, due to the presence of the first protection pattern410, it is possible to prevent the lower electrode patterns300from being oxidized.

Referring toFIG. 3I, a planarization process may be performed on the first insulating pattern111to remove the first mask layer830. The first mask layer830and upper portions of the first insulating pattern111and the first protection pattern410may be removed during the planarization process. For example, the planarization process may be performed to expose the buffer mask layer820. Thereafter, the buffer mask layer820may be removed to expose the second sacrificial pattern720. For example, the buffer mask layer820may be removed by an asking process.

Referring toFIG. 3J, an etching process using the lower mask layer810as an etch mask layer may be performed to form the second trench T2. The second trench T2may be formed to penetrate the second sacrificial pattern720, the etch stop layer715, the recess sacrificial pattern711, the ohmic layer251, the selection device layer201, and the word line layer WLa and thereby expose the top surface of the substrate100. In other example embodiments, the top surface of the substrate100may be partially recessed by the second trench T2. The word line layer WLa may be divided into the word lines WL by forming the second trench T2. The word lines WL may be configured to have substantially the same features as that of the previous embodiment described with reference toFIG. 2AthroughFIG. 2C. For example, the word lines WL may extend parallel to the second direction D2. The second trench T2may be formed to expose the recess sacrificial pattern711.

Referring toFIG. 3Kin conjunction withFIG. 3J, the recess sacrificial pattern711exposed by the second trench T2may be removed to form the second recess region R2. The removal of the recess sacrificial pattern711may be performed using a selective etching process. For example, in the case where the recess sacrificial pattern711includes a silicon oxide layer, the recess sacrificial pattern711may be removed by an etching process using a fluorine-containing gas. The second recess region R2may be formed between the ohmic layer251and the etch stop layer715and may expose the side surfaces300cof the lower electrode patterns300, the bottom surface715bof the etch stop layer715, and the top surface251aof the ohmic layer251. The second trench T2may be extended or connected to the second recess region R2. A width of the recess sacrificial pattern711removed during the formation of the second recess region R2may be greater than that of the sacrificial pattern710removed by an etching process ofFIG. 3D. For example, a central axis of the vertical portion320shown inFIG. 2Amay be positioned at an offset from that of a corresponding one of the memory cells MC. Further, the central axis of the vertical portion320provided on one of adjacent ones of the word lines WL may be shifted from that of the memory cell MC in the first direction D1, and the central axis of the vertical portion320provided on the other of adjacent ones of the word lines WL may be shifted from that of the memory cell MC in a direction antiparallel to the first direction D1.

Referring toFIG. 3L, the second protection pattern420may be conformally formed in the second trench T2. The second protection pattern420may be extended into the second recess region R2to cover the top surface251aof the ohmic layer251, the side surfaces300cof the lower electrode patterns300, and the bottom surface715bof the etch stop layer715. The second protection pattern420may be formed to cover the side surface of the selection device layer201, the side surface of the ohmic layer251, the side surface of the etch stop layer715, the side surface of the second sacrificial pattern720, the lower and second mask layers810and840. The second protection pattern420may be formed using an atomic layer deposition to have a thickness ranging from about 1 nm to about 5 nm. The second protection pattern420may be formed of, or include, substantially the same material as the first protection pattern410(e.g., silicon nitride).

A second insulating pattern112may be deposited on the substrate100to fill the second trench T2. The second insulating pattern112may be formed to cover the second protection pattern420in the second recess region R2. The second insulating pattern112may be formed of, or include, substantially the same material as the first insulating pattern111.

Referring toFIG. 3M, the third and fourth trenches T3and T4and third and fourth insulating patterns113and114respectively may be formed parallel to the first direction D1to separate the selection elements200and the ohmic patterns250from each other. The formation of the third trench T3and the third insulating pattern113may be performed using the same or similar patterning process as that for forming the first and second trenches T1and T2and the first and second insulating patterns111and112respectively. For example, mask patterns (not shown) may be formed on the insulating patterns111and112and the lower mask layer810, and then, the mask patterns may be used to etch the lower mask layer810, the second sacrificial pattern720, the etch stop layer715, the lower electrode pattern300, the ohmic layer251, the selection device layer201. The third trench T1may be formed in the second sacrificial pattern720, the etch stop layer715, the lower electrode pattern300, the ohmic pattern250, and the selection element200to expose the word lines WL. A third protection pattern430may be formed in the third trench T3to cover the side surfaces of the second sacrificial pattern720, the etch stop layer715, the lower electrode pattern300, the ohmic patterns250, and the selection elements200. The third insulating pattern113may be formed in the third trench T3to cover the third protection pattern430. Thereafter, the fourth trench T4, the fourth protection pattern440, and the fourth insulating pattern114may be formed adjacent to and between the third trenches T3. The fourth trench T4, the fourth protection pattern440, and the fourth insulating pattern114may be formed by substantially the same or similar method as that for the formation of the third trench T3, the third protection pattern430, and the third insulating pattern113. For example, the fourth trench T4may be formed to penetrate the second sacrificial pattern720, the etch stop layer715, the lower electrode pattern300, the ohmic pattern250, and the selection element200to expose the top surfaces of the word lines WL. The fourth protection pattern440and the fourth insulating pattern114may be sequentially formed in the fourth trench T4. The word lines WL may not be etched during the formation of the third and fourth trenches T3and T4. The lower mask layer810may be removed by a planarization process to expose the second sacrificial pattern720. Here, the third and fourth protection patterns430and440and the insulating patterns111,112,113, and114may have tops surfaces coplanar with each other.

Referring toFIG. 3NandFIG. 3O, the second sacrificial pattern720may be removed using, for example, a wet etching process to form a contact hole501. The contact hole501may be formed to have a bottom surface exposing the etch stop layer715and a side surface exposing the protection patterns410,420,430, and440. Thereafter, the etch stop layer715may be removed by an etching process, and thus, the top surfaces of the upper horizontal portions330of the lower electrode patterns300and the first and second protection patterns410and420respectively may be exposed. The etching of the etch stop layer715may be performed to etch the upper horizontal portions330of the lower electrode patterns300positioned on the first and second protection patterns410and420respectively. However, the vertical portions320of the lower electrode patterns300may not be removed by the etching of the etch stop layer715.

Referring toFIG. 3P, the spacer pattern550may be formed on a side surface of the contact hole501. For example, the formation of the spacer pattern550may include conformally forming a spacer layer (not shown) in the contact hole501and etching the spacer layer. The spacer pattern550may include a silicon-containing material (e.g., silicon oxide). The spacer pattern550may include at least one of insulating materials or high-k dielectric materials, which were described with reference toFIG. 2AthroughFIG. 2C. The spacer pattern550may be formed to have a width ranging from about 2 nm to 5 nm.

The phase-changeable pattern500may be formed in the contact hole501. The phase-changeable pattern500may be formed to have substantially the same or similar features as that described with reference toFIG. 2AthroughFIG. 2C. The phase-changeable pattern500may include at least one of the phase-changeable materials previously enumerated inFIG. 1. The phase-changeable pattern500may be formed in such a way that a portion of the bottom surface500bis in contact with the top surfaces300aof the lower electrode patterns300. Another portion of the bottom surface500bmay be in contact with the first and second protection patterns410and420respectively. In example embodiments, each of the lower electrode patterns300may be formed to have an “L”-shaped section. Since the vertical portions320of the lower electrode patterns300are formed using a deposition process, the width A1of the vertical portions320may be about one-third of that of the case that the photolithography process. Accordingly, the contact area of the phase-changeable pattern500and the lower electrode pattern300can be reduced. This makes it possible to reduce an amount of current required for the program operation of the semiconductor device.

The phase-changeable pattern500may be formed using one of sputtering, chemical vapor deposition, or physical vapor deposition methods. In example embodiments, the formation of the phase-changeable pattern500may include forming a phase-changeable material layer (not shown) to cover the contact hole501and the insulating patterns111,112,113, and114and then planarizing the phase-changeable material layer to expose the insulating patterns111,112,113, and114.

Referring toFIG. 3Q, an etching process may be performed to remove an upper portion of the phase-changeable pattern500, and then, the upper electrode pattern600may be formed on the phase-changeable pattern500. The upper electrode pattern600may include at least one metal nitride (e.g., titanium nitride). The bit lines BL may be formed on the insulating patterns111,112,113, and114. The bit lines BL may be in contact with the upper electrode patterns600and extend parallel to the second direction D2. A material contained in the bit lines BL may be unintentionally reacted with a material contained in the phase-changeable pattern500, but according to example embodiments of the inventive concepts, the upper electrode pattern600may be interposed between the phase-changeable patterns500and the bit lines BL to prevent such an unintended reaction between the phase-changeable pattern500and the bit lines BL. Accordingly, it is possible to prevent the semiconductor device1from being deteriorated.

Hereinafter, a semiconductor device according to other example embodiments of the inventive concepts will be described. For the sake of brevity, the elements and features of this example that are similar to those previously shown and described will not be described in much further detail.

FIG. 4Ais a plan view illustrating a semiconductor device according to other example embodiments of the inventive concepts.FIG. 4Bis a sectional view taken along lines I-I′ and II-II′ ofFIG. 4A, andFIG. 4Cis an enlarged view of a region III ofFIG. 4B.

Referring toFIG. 4AandFIG. 4B, a semiconductor device2may include the word lines WL, the bit lines BL, and the memory cells MC on the substrate100. The memory cells MC may be located at respective intersections of the word lines WL and the bit lines BL. The memory cells MC may be defined or delimited by insulating patterns111,112,113, and114, The insulating patterns111,112,113, and114may be interposed on the substrate100and between the word lines WL to enclose the memory cells MC. In each pair of two adjacent word lines WL, the memory cells MC may also be formed to have the bilateral symmetry with respect to a line equidistant therefrom. Each of the memory cells MC may include the selection element200, the ohmic pattern250, the lower electrode pattern300, the protection patterns410,420,430, and440, the phase-changeable pattern500, the spacer pattern550, and the upper electrode pattern600. The semiconductor device2may be fabricated by substantially the same or similar method as that described with reference toFIG. 3AthroughFIG. 3Q.

The lower electrode pattern300may be provided on the ohmic pattern250to be in contact with the phase-changeable pattern500. As shown inFIG. 4B, the lower electrode pattern300may have an “L”-shaped section. As shown inFIG. 4C, the lower electrode pattern300may include the horizontal portion310and the vertical portion320vertically extending from the horizontal portion310. A width A1of the vertical portion320may be substantially equal to a thickness A2of the horizontal portion310. The vertical portion320may have an occupying area smaller than that of the lower electrode pattern300. The vertical portion320may have substantially the same central axis as that of the memory cell MC therewith. For example, when the first recess region R1is formed using the method described with reference toFIG. 3D, a width of the first sacrificial pattern710to be removed by the etching process of FIG.3D may be adjusted to control positions of the vertical portion320. As an example, a width of the first sacrificial pattern710to be removed by the etching process ofFIG. 3Dmay be substantially equal to a width of the recess sacrificial pattern711to be removed by the etching process ofFIG. 3J.

Hereinafter, the memory cells MC and the lower electrode patterns300will be described in more detail.

As shown inFIG. 4A, the memory cells MC may be two-dimensionally arranged along both the first and second directions D1and D2respectively. When viewed in a plan view, the vertical portions320of the memory cells MC may be disposed to form rectangular shapes as shown inFIG. 4A. The vertical portions320of the memory cells MC may be spaced apart from each other by substantially the same distance in the second direction D2. The vertical portions320may be formed to be centered within the memory cells MC, and thus, the vertical portions320of the memory cells MC may be spaced apart from each other by substantially the same distance in the first direction D1. Each of the memory cells MC may have substantially the same occupying area and shape. The top surfaces of the vertical portion320of the lower electrode patterns300may have substantially the same occupying area. This makes it possible to improve uniformity in size of the vertical portion320and reduce an amount of current required for a program operation of the semiconductor device2.

Referring toFIGS. 4B and 4Cin conjunction withFIG. 4A, the memory cells MC on each pair of two adjacent word lines WL may have the bilateral symmetry with respect to a line equidistant therefrom. The protection patterns410,420,430, and440may be interposed between the lower electrode patterns300and the insulating patterns111,112,113, and114. The phase-changeable patterns500may be provided on the lower electrode patterns300, respectively. The top surfaces300aof the vertical portions320of the lower electrode patterns300may have an area smaller than the bottom surfaces500bof the phase-changeable patterns500. The bottom surfaces500bof the phase-changeable patterns500may be in contact with the top surfaces300aof the vertical portions320of the lower electrode patterns300, and thus, contact areas between the phase-changeable patterns500and the lower electrode patterns300can be reduced. Accordingly, it is possible to further reduce an amount of current required for a program operation of the semiconductor device2.

Hereinafter, a semiconductor device according to still other example embodiments of the inventive concepts will be described. For the sake of brevity, the elements and features of this example that are similar to those previously shown and described will not be described in much further detail.

FIG. 5Ais a plan view illustrating a semiconductor device according to another example embodiments of the inventive concepts.FIG. 5Bis a sectional view taken along lines I-I′ and II-IF ofFIG. 5A, andFIG. 5Cis an enlarged view of a region III ofFIG. 5B.

Referring toFIG. 5AandFIG. 5B, a semiconductor device3may include the word lines WL, the bit lines BL, and the memory cells MC on the substrate100. The memory cells MC may be defined or delimited by insulating patterns111,112,113, and114. Each of the memory cells MC may include the selection element200, the ohmic pattern250, the lower electrode pattern300, the phase-changeable pattern500, the spacer pattern550, the protection patterns410,420,430, and440, and the upper electrode pattern600. The semiconductor device3may be fabricated by substantially the same or similar method as that described with reference toFIG. 3AthroughFIG. 3Q.

Hereinafter, the memory cells MC will be described.

The lower electrode patterns300may be disposed on the ohmic patterns250to be in contact with the phase-changeable patterns500. The lower electrode patterns300may have an “L”-shaped section. In each pair of two adjacent columns, the lower electrode patterns300may be provided to have the bilateral symmetry with respect to a line equidistant therefrom. The lower electrode patterns300may include the horizontal portions310and the vertical portions320vertically extending from the horizontal portions310. The widths A1of the vertical portions320may be substantially equal to the thicknesses A2of the horizontal portions310. The vertical portions320may be an occupying area smaller than that of the memory cells MC. A central axis of the vertical portion320of the lower electrode pattern300may be laterally positioned at a position shifted from that of the memory cell MC. When the first recess region R1is formed using the method described with reference toFIG. 3D, positions of the vertical portions320can be positioned by adjusting the process of etching the first sacrificial pattern710. As an example, a width of the first sacrificial pattern710to be removed by the etching process ofFIG. 3Dmay be larger than a width of the recess sacrificial pattern711to be removed by the etching process ofFIG. 3J.

As shown inFIG. 5A, the memory cells MC may be two-dimensionally arranged along both the first and second directions D1and D2. When viewed in a plan view, the vertical portions320of the memory cells MC may be disposed to form a rectangular arrangement. The vertical portions320of the memory cells MC may be spaced apart from each other by substantially the same distance in the second direction D2.

Hereinafter, a method of fabricating a semiconductor device according to other example embodiments of the inventive concepts will be described. For the sake of brevity, the elements and features of this example that are similar to those previously shown and described will not be described in much further detail.

FIG. 6AthroughFIG. 6CandFIG. 6EthroughFIG. 6Fare sectional views illustrating a method of fabricating a semiconductor device, according to other example embodiments of the inventive concepts.FIG. 6DandFIG. 6Gare enlarged views of regions III ofFIG. 6CandFIG. 6F, respectively.

Referring toFIG. 6A, the second trench T2and the second insulating pattern112may be formed. For example, as previously described with reference toFIG. 3AthroughFIG. 3K, the word lines WL, the selection device layer201, the ohmic layer251, the lower electrode patterns300, the etch stop layer715, the second recess region R2, and the lower mask layer810may be formed on the substrate100. The second trench T2may be formed using substantially the same method as that described with reference toFIG. 3K. For example, the second trench T2may be extended or connected to the second recess region R2. In the present embodiment, the second protection pattern420ofFIG. 3Lmay be omitted. The second insulating pattern112may be formed to fill the second trench T2and the second recess region R2.

Referring toFIG. 6B, the third and fourth trenches T3and T4and the third and fourth insulating patterns113and114may be formed parallel to the first direction D1, and thus, the separate the selection elements200and the ohmic patterns250may be separated from each other. The third trench T3and the third insulating pattern113may be formed by substantially the same or similar method as that of the previous embodiments described with reference toFIG. 3M. The third and fourth protection patterns430and440may be formed in the third and fourth trenches T3and T4, respectively. The third and fourth insulating patterns113and114may be formed on the third and fourth protection patterns430and440, respectively. In certain embodiments, the third and fourth protection patterns430and440may be omitted.

Referring toFIG. 6CandFIG. 6D, the second sacrificial pattern720and the etch stop layer715may be removed by, for example, a wet etching process, and thus, the contact hole501may be formed on the lower electrode patterns300. A process of etching the second sacrificial pattern720and the etch stop layer715may be performed in substantially the same manner as the etching process described with reference toFIG. 3N. However, in the present embodiment, the process of etching the etch stop layer715may be performed to etch a portion of the second insulating pattern112, and thus, the contact hole501may be formed to have a flat bottom surface. The bottom surface of the contact hole501may expose the upper horizontal portion330of the lower electrode pattern300, the first protection pattern410, and the second insulating pattern112. The contact hole501may be formed to have a side surface exposing the protection patterns410,430, and440and the second insulating pattern112. The etching process may be performed to prevent the vertical portions320of the lower electrode patterns300from being etched.

Referring toFIG. 6E, the spacer pattern550may be formed on a side surface of the contact hole501. The phase-changeable pattern500may be formed in the contact hole501. The formation of the spacer pattern550and the phase-changeable pattern500may be performed using the same or similar method as that described with reference toFIG. 3P. A portion of the bottom surface500bof the phase-changeable pattern500may be formed to be in contact with the top surfaces300aof the lower electrode patterns300. Other portion of the bottom surface500bmay be in contact with the first protection pattern410and the second insulating pattern112. In example embodiments, each of the lower electrode patterns300may have an “L”-shaped section, allowing for a reduction in contact area between the phase-changeable pattern500and the lower electrode patterns300.

Referring toFIG. 6FandFIG. 6G, the upper electrode pattern600and the bit lines BL may be formed on the phase-changeable pattern500. The upper electrode pattern600and the bit lines BL may be formed using the same or similar method as that described with reference toFIG. 3Q. Accordingly, the semiconductor device4may be fabricated to have the structure ofFIG. 6F.

FIG. 7is a block diagram of an electronic device including a semiconductor device according to example embodiments of the inventive concepts.

The electronic device1000according to example embodiments of the inventive concepts may be used in one or more of an application chipset, a camera image sensor, a camera image signal processor (ISP), a personal digital assistant (PDA), a laptop computer, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a wire or wireless electronic device, or a complex electronic device including at least two of the aforementioned components.

Referring toFIG. 7, the electronic device1000may include a semiconductor memory device1300, a central processing unit (CPU)1500, a user interface1600, and a power supply device1700, which are connected to a system bus1450. The semiconductor memory device1300may include a memory device1100, which may be one of the semiconductor devices described previously, and a memory controller1200.

Data processed by the CPU1500and/or input from the user interface1600may be stored in the memory device1100, and the memory controller1200may be configured to control such data exchange among the CPU1500, the user interface1600, and the memory device1100. The memory device1100may constitute a solid state drive (SSD), and in this case, an operating speed of the electronic device1000may be greatly increased.

According to example embodiments of the inventive concepts, a lower electrode pattern may be provided to have a top surface that is an area smaller than that of a bottom surface of a phase-changeable pattern. Accordingly, it is possible to reduce a contact area between the lower electrode pattern and the phase-changeable pattern and an amount of current required for a program operation of a semiconductor device.

The lower electrode pattern may be conformally formed by a deposition process. This makes it possible to improve uniformity in size of the lower electrode patterns. For example, top surfaces of the lower electrode patterns can have substantially the same area. Thus, it is possible to improve uniformity in contact area between the lower electrode patterns and the phase-changeable patterns. This makes it possible to improve uniformity in the amount of current required for the program operation of the semiconductor device. Memory cells may be formed in a self-aligned manner, and this allows memory cells to be programmed using a uniform program current, when the program operation is performed. As a result, it is possible to improve reliability of the semiconductor device.