SEMICONDUCTOR PACKAGE

A first package structure including a first redistribution structure, at least one first semiconductor chip disposed on the first redistribution structure, a first encapsulant covering the at least one first semiconductor chip, and a first through-via passing through the first encapsulant; a second package structure including a second redistribution structure, at least one second semiconductor chip disposed on the second redistribution structure, a second encapsulant covering the at least one second semiconductor chip, and a second through-via passing through the second encapsulant. The second package structure is disposed on the first package structure. At least one of a first upper end of the first through-via or a second upper end of the second through-via is between a first non-active surface and a second non-active surface.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0136666 filed on Oct. 21, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present inventive concept relates to a semiconductor package.

DISCUSSION OF THE RELATED ART

In accordance with a reduced weight and a high performance of electronic devices, the development of miniaturized and highly efficient semiconductor packages is desired in the field of semiconductor packages. Generally, semiconductor packages including a plurality of semiconductor chips may have an increased volume of an encapsulant, deteriorated heat dissipation characteristics, or increased process difficulty due to an increase in interfaces between the encapsulant and the semiconductor chips.

SUMMARY

According to an embodiment of the present inventive concept, a semiconductor package includes: a first package structure including a first redistribution structure, at least one first semiconductor chip, a first encapsulant, and a first through-via, wherein the first redistribution structure has a first front surface and a first rear surface, which oppose each other, and includes a first redistribution layer, wherein the at least one first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, wherein a first connection pad is disposed on the first active surface and is electrically connected to the first redistribution layer, wherein the at least one first semiconductor chip is disposed on the first redistribution structure such that the first active surface faces the first front surface, wherein the first encapsulant covers at least a portion of the at least one first semiconductor chip, and wherein the first through-via is electrically connected to the first redistribution layer and passes through the first encapsulant; a second package structure including a second redistribution structure, at least one second semiconductor chip, a second encapsulant, and a second through-via, wherein the second redistribution structure has a second front surface and a second rear surface, which oppose each other, and includes a second redistribution layer, wherein the at least one second semiconductor chip has a second active surface and a second non-active surface opposite to the second active surface, wherein a second connection pad is disposed on the second active surface and is electrically connected to the second redistribution layer, wherein the at least one second semiconductor chip is disposed on the second redistribution structure such that the second active surface faces the second front surface, wherein the second encapsulant covers at least a portion of the at least one second semiconductor chip, and wherein the second through-via is electrically connected to the second redistribution layer and the first through-via and passes through the second encapsulant, wherein the second package structure is disposed on the first package structure such that the second front surface faces the first front surface, wherein at least one of a first upper end of the first through-via or a second upper end of the second through-via, which face each other, is located on a level that is between the first non-active surface and the second non-active surface.

According to an embodiment of the present inventive concept, a semiconductor package includes: a first package structure including a first redistribution structure, a first semiconductor chip, a first encapsulant, and a first through-via, wherein the first redistribution structure includes a first redistribution layer, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, wherein a first connection pad is electrically connected to the first redistribution layer and is disposed on the first active surface, wherein the first semiconductor chip is disposed such that the first active surface faces the first redistribution structure, wherein the first encapsulant covers at least a portion of the first semiconductor chip, and wherein the first through-via is electrically connected to the first redistribution layer and passes through the first encapsulant; a second package structure including a second redistribution structure, a second semiconductor chip, a second encapsulant, and a second through-via, wherein the second redistribution structure includes a second redistribution layer, wherein the second semiconductor chip has a second active surface and a second non-active surface opposite to the second active surface, wherein a second connection pad is electrically connected to the second redistribution layer and is disposed on the second active surface, wherein the second semiconductor chip is disposed such that the second active surface faces the second redistribution structure, wherein the second encapsulant covers at least a portion of the second semiconductor chip, and wherein the second through-via is electrically connected to the second redistribution layer and passes through the second encapsulant, wherein the second redistribution structure is disposed on the first package structure such that the second non-active surface faces the first non-active surface; and a film structure including an insulating resin and conductive particles, wherein the insulating resin fills a gap between the first package structure and the second package structure, wherein the conductive particles are dispersed in the insulating resin to electrically connect the first through-via to the second through-via.

According to an embodiment of the present inventive concept, a semiconductor package includes: a first package structure including a first redistribution structure, a first semiconductor chip, a first encapsulant, and a first through-via, wherein the first redistribution structure includes a first insulating layer, which provides a first front surface and a first rear surface, and a first redistribution layer that is disposed within the first insulating layer, wherein the first semiconductor chip is disposed on the first front surface, wherein the first encapsulant covers at least a portion of the first semiconductor chip, and wherein the first through-via is electrically connected to the first redistribution layer and passes through the first encapsulant; a second package structure including a second redistribution structure, a second semiconductor chip, a second encapsulant, and a second through-via, wherein the second redistribution structure includes a second insulating layer, which provides a second front surface and a second rear surface, and a second redistribution layer disposed within the second insulating layer, wherein the second semiconductor chip is disposed on the second front surface, wherein the second encapsulant covers at least a portion of the second semiconductor chip, and wherein the second through-via electrically connects the second redistribution layer to the first through-via and passes through the second encapsulant, wherein the second package structure is disposed on the first package structure such that the second front surface and the first front surface face each other; and a bump structure disposed on the first rear surface of the first package structure and electrically connected to at least a portion of the first redistribution layer that is exposed from the first insulating layer, wherein the second insulating layer covers a surface of the second redistribution layer that is adjacent to the second rear surface.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the present inventive concept will be described with reference to the accompanying drawings.

FIG.1Ais a cross-sectional view of a semiconductor package1000A according to an embodiment of the present inventive concept.FIG.1Bis a partially enlarged view of region ‘A’ ofFIG.1A, andFIG.1Ca cross-sectional view taken along line I-I′ ofFIG.1A.

Referring toFIGS.1A to1C, the semiconductor package1000A according to an embodiment of the present inventive concept may include a first package structure100, a second package structure200, and a film structure300.

In an embodiment of the present inventive concept, the first package structure100and the second package structure200may be stacked on each other such that a first non-active surface120S2of a first semiconductor chip120and a second non-active surface220S2of the second semiconductor chip220face each other. For example, the second package structure200may be disposed on the first package structure100such that a second front surface FS2of the second redistribution structure210faces a first front surface FS1of the first redistribution structure110.

In an embodiment of the present inventive concept, the first package structure100and the second package structure200may be electrically connected through a first through-via130and a second through-via230. For example, the first through-via130may have a first lower end, which is electrically connected to the first redistribution layer112, and a first upper end130T, which is electrically connected to the second through-via230. The second through-via230may have a second lower end, which is electrically connected to the second redistribution layer212, and a second upper end230T electrically connected to the first through-via130.

In an embodiment of the present inventive concept, the first through-via130and the second through-via230may be electrically connected to each other by the film structure300. At least one of the first through-via130and the second through-via230may extend into an insulating resin311of the film structure300. For example, the first upper end130T of the first through-via130may protrude beyond a surface140S of a first encapsulant140that is opposite to the first front surface FS1, and the second upper end230T of the second through-via230may protrude beyond a surface240S of a second encapsulant240. According to some embodiments of the present inventive concept, one of the first through-via130and the second through-via230may extend into the insulating resin311.

In an embodiment of the present inventive concept, at least one of the first upper end130T of the first through-via130and/or the second upper end230T of the second through-via230facing each other may be located on a level between the first non-active surface120S2and the second non-active surface220S2.

In an embodiment of the present inventive concept, the semiconductor package1000A may include a bump structure160disposed on one side. For example, the semiconductor package1000A may include the bump structure160disposed on a rear surface BS1of the first package structure100. The bump structure160may be electrically connected to at least a portion of the first redistribution layer112that is exposed from the first insulating layer111. The semiconductor package1000A may be connected to an external device, such as a module substrate or a system board through the bump structure160. For example, the bump structures160may have a shape of a combination of a pillar (or under bump metal) and a ball. The pillar may include, for example, copper (Cu) or an alloy of copper (Cu), and the ball may include a low melting point metal, for example, tin (Sn) or an alloy (Sn—Ag—Cu) including tin (Sn). According to some embodiments of the present inventive concept, the bump structures160may include only pillars or balls. According to some embodiments of the present inventive concept, a resist layer may be formed on the first rear surface BS1to protect the bump structures160from external physical and chemical damage.

In an embodiment of the present inventive concept, an element for external connection might not be disposed on the other side of the semiconductor package1000A. For example, at least a portion of the first redistribution layer112that is adjacent to the first rear surface BS1may be exposed from the first insulating layer111, and the second redistribution layer212that is adjacent to the second rear surface BS2might not be exposed from the second insulating layer211. For example, the second insulation layer211of the second redistribution structure210may cover the entire surface of the second redistribution layer212adjacent to the second rear surface BS2.

In an embodiment of the present inventive concept, the first non-active surface120S2of the first semiconductor chip120may be exposed from a first encapsulant140, and the second non-active surface220S2of the second semiconductor chip220may be exposed from the second encapsulant240. In addition, the first encapsulant140might not be inserted between the first non-active surface120S2and the film structure300, and the second encapsulant240might not be inserted between the second non-active surface220S2and the film structure300. For example, the first encapsulant140might not cover the first non-active surface120S2, and the second encapsulant240might not cover the second non-active surface220S2.

As described above, according to an embodiment of the present inventive concept, by minimizing an interface formed between the encapsulant (e.g., ‘140’ or ‘240’) and the semiconductor chip (e.g., ‘120’ or ‘220’), process risks, such as voids and interface delamination, may be reduced, and heat dissipation characteristics of the semiconductor package may be improved. In addition, since the first package structure100and the second package structure200, which are discontinuously and independently manufactured, are physically and electrically coupled by the film structure300, process risks may be reduced compared to a case in which the first package structure100and the second package structures200are continuously and sequentially formed. According to some embodiments of the present inventive concept, the film structure300may be omitted (refer toFIG.3A), but even in this case, the first package structure100and the second package structure200may be separately manufactured.

Hereinafter, each component of the first package structure100, the second package structure200, and the film structure300will be described.

The first package structure100may include the first redistribution structure110, at least one first semiconductor chip120, the first through-via130, and the first encapsulant140.

The first redistribution structure110may be a support substrate, on which the semiconductor chip120is mounted, and may have a first front surface FS1and a first rear surface BS1facing each other and may include a first insulating layer111, a first redistribution layer112, and a first redistribution via113.

The first insulating layer111may include an insulating resin. The insulating resin is a thermosetting resin, such as an epoxy resin, a thermoplastic resin, such as polyimide, or a resin impregnated with an inorganic filler in these resins, for example, prepreg, Ajinomoto build-up film (ABF), FR-4, and BT. For example, the first insulating layer111may include a photosensitive resin, such as photo-imageable dielectric (PID). The first insulating layer111may include a plurality of first insulating layers111stacked in a vertical direction (e.g., a Z-axis direction). Depending on the process, the boundary between the plurality of first insulating layers111might not be apparent. The first insulating layer111may provide the first front surface FS1and the first rear surface BS1of the first redistribution structure110.

The first redistribution layer112may be disposed on or within the first insulating layer111and may redistribute the connection pad120P of the first semiconductor chip120. The first redistribution layer112may include a metal material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first redistribution layer112may perform various functions. For example, the first redistribution layer112may include a ground (GND) pattern, a power (PoWeR: PWR) pattern, and a signal (S) pattern. Here, the signal (S) pattern may provide a transmission path for various signals, e.g., data signals, excluding the ground (GND) pattern and the power (PWR) pattern. The first redistribution layer112may include more or fewer redistribution layers than shown in the drawings. The first redistribution layer112may include first front surface pads disposed on the first front surface FS1of the first redistribution structure110. The first front surface pads may be connected to the connection pad120P of the first semiconductor chip120and the first through-via130.

The first redistribution via113may pass through the first insulating layer111and be electrically connected to the first redistribution layer112. For example, the first redistribution vias113may interconnect first redistribution layers112, which are on different levels, to each other. The first redistribution via113may include, for example, a signal via, a ground via, and a power via. The first redistribution via113may include a metal material including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first redistribution via113may be a filled via, which may be formed by filling an inside of a via hole with a metal material, or a conformal via, in which a metal material extends along an inner wall of the via hole.

The first semiconductor chip120may include a first active surface120S1, on which a first connection pad120P electrically that is connected to the first redistribution layer112is disposed, and a first non-active surface120S2that is opposite to the first active surface120S1. The first semiconductor chip120may be disposed on the first front surface FS1of the first redistribution structure110. For example, the first semiconductor chip120may be disposed on the first redistribution structure110such that the first active surface120S1faces the first front surface FS1. According to some example embodiments of the present inventive concept, the first semiconductor chip120may be provided as a plurality of semiconductor chips. The first semiconductor chip120may be connected to the first redistribution layer112through the first connection bump123. The first connection bump123may be disposed between the first connection pad120P and the first redistribution layer112. For example, the first connection bump123may include a pillar portion121, which is in contact with the first connection pad120P, and a solder portion122, which is in contact with the first redistribution layer112. According to some embodiments of the present inventive concept, an underfill layer125may be disposed between the first semiconductor chip120and the first redistribution structure110. The underfill layer125may include an insulating resin, such as an epoxy resin, and may physically and electrically protect the first connection bumps123. For example, the underfill layer125may have a capillary underfill (CUF) structure, but the present inventive concept is not limited thereto. According to some embodiments of the present inventive concept, the underfill layer125may have a molded underfill (MUF) structure integrated with the encapsulant140.

The first semiconductor chip120may be an integrated circuit (IC) in a bare state, in which no bumps or wiring layers are formed, but the present inventive concept is not limited thereto, and the first semiconductor chip120may be a packaged type IC. The IC may be a processor chip, such as a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, but the present inventive concept is not limited thereto and may be logic chips, such as an analog-to-digital converter (ADC) and an application-specific IC (ASIC) or may be memory chips including volatile memories, such as dynamic RAM (DRAM) and static RAM (SRAM) and non-volatile memories, such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and a flash memory. For example, the first semiconductor chip120may include a graphics double data rate (GDDR) RAM.

The first through-via130may be electrically connected to the first redistribution layer112by passing through the first encapsulant140. The first through-via130may be electrically connected to the second package structure200. The first through-via130may extend in a direction (the Z-direction), substantially perpendicular to the first front surface FS1of the first redistribution structure110. For example, the first through-via130may have a post shape passing through the encapsulant140. However, a shape of the first through-via130is not limited thereto. In an embodiment of the present inventive concept, the first through-via130may have a first lower end, which is electrically connected to the first redistribution layer112, and a first upper end130T, which is electrically connected to the second through-via230. The first through-via130may include a metal material, such as copper (Cu). According to some embodiments of the present inventive concept, a metal seed layer including, for example, titanium (Ti), copper (Cu), or the like may be formed on a lower surface of the first through-via130.

The first encapsulant140may be disposed on the first redistribution structure110and may encapsulate at least a portion of each of the first semiconductor chip120and the first through-via130. For example, the first encapsulant140may cover at least a portion of each of the first semiconductor chip120and the first through-via130. The first encapsulant140may be formed to at least partially surround side surfaces of the first semiconductor chip120and side surfaces of the first through-via130. The first encapsulant140may be, for example, a thermosetting resin, such as epoxy resin, a thermoplastic resin, such as polyimide, or a prepreg formed by impregnating an inorganic filler in these resins, ABF, FR-4, BT, and EMC.

The second package structure200may include components having characteristics the same as or similar to those of the first package structure100described above. Hereinafter, the components of the second package structure200are referred to as the same terms as those of the corresponding components of the first package structure100, and redundant descriptions may be omitted or briefly discussed. In addition, components of the first package structure100and the second package structure200are distinguished from each other using ordinal numbers (e.g., ‘first’ and ‘second’) and reference numbers.

The second package structure200may include a second redistribution structure210, at least one second semiconductor chip220, a second through-via230, and a second encapsulant240. The second redistribution structure210, at least one second semiconductor chip220, the second through-via230, and the second encapsulant240may have characteristics the same as or similar to those of the first redistribution structure110, at least one first semiconductor chip120, the first through-via130, and the first encapsulant140of the first package structure100, respectively.

The second redistribution structure210may be a support substrate on which the second semiconductor chip220is mounted, and may have the second front surface FS2and the second rear surface BS2facing each other. The second redistribution structure210may include a second insulating layer211, a second redistribution layer212and a second redistribution via213.

The second semiconductor chip220may include a second active surface220S1, on which a second connection pad220P that is electrically connected to the second redistribution layer212is disposed, and a second non-active surface220S2that is opposite to the second active surface220S1, and the second semiconductor chip220may be disposed on the second front surface FS2of the second redistribution structure210. For example, the second semiconductor chip220may be disposed on the second redistribution structure210such that the second active surface220S1faces the second front surface FS2of the second redistribution structure210. According to some embodiments of the present inventive concept, the second semiconductor chip220may be provided as a plurality of semiconductor chips. The second semiconductor chip220may be connected to the second redistribution layer212through a second connection bumps223. For example, the second connection bump223may include a pillar portion221, which is in contact with the second connection pad220P, and a solder portion222, which is in contact with the second redistribution layer212. According to some embodiments of the present inventive concept, an underfill layer225may be disposed between the second semiconductor chip220and the second redistribution structure210. The second semiconductor chip220may include the same type of semiconductor chip as that of the first semiconductor chip120, for example, a GDDR RAM, but the present inventive concept is not limited thereto.

The second through-via230may be electrically connected to the second redistribution layer212by passing through the second encapsulant240. The second through-via230may be electrically connected to the first package structure100. In an embodiment of the present inventive concept, the second through-via230may have a second lower end, which is electrically connected to the second redistribution layer212, and a first upper end230T, which is electrically connected to the first through-via130.

The second encapsulant240may be disposed on the second redistribution structure210and may encapsulate at least a portion of each of the second semiconductor chip220and the second through-via230. For example, the second encapsulant240may cover at least a portion of each of the second semiconductor chip120and the second through-via230. The second encapsulant240may be formed to at least partially surround side surfaces of the second semiconductor chip220and side surfaces of the second through-via230.

The film structure300may be disposed between the first package structure100and the second package structure200and may electrically connect the first through-via130and the second through-via230to each other. The film structure300may include an anisotropic conductive film (ACF) including an insulating resin311and conductive particles312.

The insulating resin311may fill a gap between the first package structure100and the second package structure200. The insulating resin311may include, for example, a thermosetting resin, a thermoplastic resin, or a mixture thereof. For example, the insulating resin311may include epoxy resin, polyurethane, acrylic resin, polyethylene, silicone polymer, styrene butadiene block copolymer, and/or styrene-ethylene-propylene-styrene block copolymer. The insulating resin311may have a thickness ranging from about 5 μm to about 50 μm, about 5 μm to about 40 μm, or about 10 μm to about 30 μm. For example, a distance between the first and second non-active surfaces120S2and220S2may range from about 5 μm to about 50 μm, from about 5 μm to about 40 μm, or from about 10 μm to about 30 μm.

The conductive particles312may be dispersed in the insulating resin311. The conductive particles312may have a form in which a core particle is coated with a conductive material. The core particle may be, for example, a plastic ball having a diameter ranging from about 1 μm to about 50 μm, about 2 μm to about 40 μm, or about 3 μm to about 30 μm. However, the present inventive concept is not limited thereto, and the core particles may be carbon fibers or conductive particles, such as metal balls. The conductive material applied to the surface of the core particle may include a metal material, for example, gold (Au), silver (Ag), nickel (Ni), or lead (Pd). According to some embodiments of the present inventive concept, a surface of a conductive material, that is, an outer portion of the conductive particles312, may be coated with an insulating skin layer. Accordingly, electrical conductivity may be exhibited in a compression direction by at least some of the conductive particles312having a skin layer destroyed by high-temperature compression.

FIG.2Ais a cross-sectional view of a semiconductor package1000B according to an embodiment of the present inventive concept, andFIG.2Bis a partially enlarged view of region ‘B’ ofFIG.2A.

Referring toFIGS.2A and2B, the semiconductor package1000B according to an embodiment of the present inventive concept may have characteristics the same as or similar to those described above with reference toFIGS.1A to1C, except that the first package structure100and the second package structure200are stacked such that the first non-active surface120S2of the first semiconductor chip120and the second active surface220S1of the second semiconductor chip220face each other. For example, the second package structure200may be disposed on the first semiconductor package structure100such that the second rear surface BS2of the second redistribution structure210faces the first front surface FS1of the first redistribution structure110.

In an embodiment of the present inventive concept, the first package structure100and the second package structure200may be electrically connected to each other through the first through-via130and the second bump structure260. For example, the first through-via130may have a first lower end electrically connected to the first redistribution layer112and a first upper end130T electrically connected to the second bump structure260, and the second bump structure260may have a lower end, which is electrically connected to the second redistribution layer212, and an upper end260T, which is electrically connected to the first through-via130. The upper end260T of the second bump structure260may be on substantially the same level as that of a surface211S of the second insulating layer211providing the second rear surface BS2. For example, the upper end260T may be substantially coplanar with the surface211S of the second insulating layer211. According to some embodiments of the present inventive concept, the upper end260T of the second bump structure260may protrude, relative to the surface211S of the second insulating layer211.

In an embodiment of the present inventive concept, the first through-via130and the second bump structure260may be electrically connected to each other by the film structure300. At least one of the first through-via130and the second bump structure260may extend into the insulating resin311of the film structure300.

In an embodiment of the present inventive concept, a thickness T2of the second semiconductor chip220may be greater than a thickness T1of the first semiconductor chip120. However, the present inventive concept is not limited thereto, and the thickness T2of the second semiconductor chip220may be less than or equal to the thickness T1of the first semiconductor chip120.

FIG.3Ais a cross-sectional view of a semiconductor package1000C according to an embodiment of the present inventive concept, andFIG.3Bis a partially enlarged view of region ‘C’ ofFIG.3A.

Referring toFIGS.3A and3B, the semiconductor package1000C according to an embodiment of the present inventive concept may have characteristics the same as or similar to those described above with reference toFIGS.1A to2B, except that at least partial regions of the first package structure100and the second package structure200are directly bonded to each other.

In an embodiment of the present inventive concept, the first semiconductor chip120may further include a first bonding layer BD1that is disposed on the first non-active surface120S2, and the second semiconductor chip220may include a second bonding layer BD2that is disposed on the second non-active surface220S2. The first bonding layer BD1and the second bonding layer BD2may each include materials so that the first bonding layer BD1and the second bonding layer BD2may be bonded and combined to each other. For example, the first bonding layer BD1and the second bonding layer BD2may each include at least one of silicon oxide (SiO), silicon nitride (SiN), and/or silicon carbonitride (SiCN). The first bonding layer BD1and the second bonding layer BD2may be bonded and combined to each other by performing a thermal compression process. For example, the thermal compression process may be performed in a thermal atmosphere of about 300° C., but the present inventive concept is not limited thereto.

In an embodiment of the present inventive concept, the first upper end130T of the first through-via130and the second upper end230T of the second through-via230may directly contact each other. The first upper end130T and the second upper end230T may be located on a level that is between the first and second non-active surfaces120S2and220S2. This structure may be referred to as metal bonding based on the mutually bonded through-vias130and230, hybrid bonding configured as dielectric bonding based on bonding layers BD1and BD2bonded to each other, or direct bonding.

In an embodiment of the present inventive concept, the surface140S of the first encapsulant140and the surface240S of the second encapsulant240may be bonded and combined to each other. Depending on the process, a boundary between the surface140S of the first encapsulant140and the surface240S of the second encapsulant240might not be apparent. According to some embodiments of the present inventive concept, an anisotropic conductive film may be disposed between the first encapsulant140and the second encapsulant240and between the first through-via130and the second through-via230.

FIG.4Ais a cross-sectional view illustrating a semiconductor package1000D according to an embodiment of the present inventive concept, andFIG.4Bis a partially enlarged view illustrating region ‘D’ ofFIG.4A.

Referring toFIGS.4A and4B, the semiconductor package1000D according to an embodiment of the present inventive concept may have characteristics the same as or similar to those described above with reference toFIGS.1A to3B, except that the semiconductor package1000D further includes barrier layers BL disposed on the first redistribution layer112and the second redistribution layer212. The barrier layers BL may be disposed on first front surface pads that are disposed on the first front surface FS1and second front surface pads that are disposed on the second front surface FS2. For example, the first front surface pads of the first redistribution layer112may include a first pad P1and a second pad P2. The first pad P1may be connected to the first semiconductor chip120, and the second pad P2may be connected to the first through-via130. The barrier layers BL may be disposed between the first pad P1and the first connection bump123and between the second pad P2and the first through-via130. For example, the barrier layers BL may be disposed between a second front surface pad of the second front surface pads and the second connection bump223and between another second front surface pad of the second front surface pads and the second through-via230. The barrier layers BL may include a material resistant to oxidation, such as nickel (Ni), gold (Au), or alloys thereof. For example, the barrier layers BL may include a lower layer La, which may include nickel (Ni), and an upper layer Lb, which may include gold Au.

In an embodiment of the present inventive concept, the first connection bump123may connect the first connection pad120P of the first semiconductor chip120and at least some of the first front surface pads, that are disposed on the barrier layers BL, to each other. The second connection bump223may connect the second connection pad220P of the second semiconductor chip220and at least some of the second front surface pads, which are disposed on the barrier layers BL, to each other.

In an embodiment of the present inventive concept, the first through-via130may have a lower end, which is opposite to the first upper end (‘130T’ inFIG.1B), contacting the barrier layers BL, and the second through-via230may have a lower end, which is opposite to the second upper end (‘230T’ inFIG.1B), contacting at least some of the barrier layers BL disposed on the second front surface pads.

FIG.5is a cross-sectional view illustrating a semiconductor package1000E according to an embodiment of the present inventive concept.

Referring toFIG.5, the semiconductor package1000E of an embodiment of the present inventive concept may have characteristics the same as or similar to those described above with reference toFIGS.1A to4B, except that the semiconductor package1000E includes a plurality of first semiconductor chips120aand120band a plurality of second semiconductor chips220aand220b. In an embodiment of the present inventive concept, the plurality of first semiconductor chips120aand120bmay be arranged in a horizontal direction (e.g., an X-direction) on the first redistribution structure110, and the plurality of second semiconductor chips220aand220bmay be arranged in a horizontal direction (e.g., the X-direction) on the second redistribution structure210. According to some embodiments of the present inventive concept, the plurality of first semiconductor chips120aand120band the plurality of second semiconductor chips220aand220bmay be stacked on one another in a vertical direction (e.g., the Z-direction). The plurality of first semiconductor chips120aand120band the plurality of second semiconductor chips220aand220bmay include the same type of semiconductor chip, e.g., GDDR RAM, but the present inventive concept is not limited thereto.

FIGS.6A to6Gare cross-sectional views illustrating a sequential process of a manufacturing process of the semiconductor package1000A ofFIG.1A.

Referring toFIG.6A, the first redistribution structure110may be formed on a carrier. The carrier may include a lower layer13, a middle layer12, and an upper layer11. The lower layer13, the middle layer12, and the upper layer11may include different materials from each other. For example, the lower layer13may be a copper clad laminate (CCL), and the middle layer12may be a polymer layer including a curable resin. Further, the upper layer11may be a metal layer including nickel (Ni), titanium (Ti), and the like.

The first redistribution structure110may include a first insulating layer111, a first redistribution layer112, and a first redistribution via113. The first insulating layer111may be formed by sequentially applying and curing a photosensitive material, for example, PID. The first redistribution layer112and the first redistribution via113may be formed by forming a via hole, that passes through the first insulating layer111by performing an exposure process, and by a development process and patterning of a metal material on the first insulating layer111using a plating process. By repeating the process described above, the first redistribution structure110including a plurality of first redistribution layers112may be formed. A barrier layer including nickel (Ni), gold (Au), or alloys thereof may be formed on the uppermost first redistribution layer112that is disposed on the first front surface FS1of the first redistribution structure110. The bump structure160(pillar portion) may be formed below the lowermost first redistribution layer112, but the present inventive concept is not limited thereto. According to some embodiments of the present inventive concept, the bump structure160(pillar portion) may be formed after the carrier is removed.

Referring toFIG.6B, a first through-via130may be formed on the uppermost first redistribution layer112. The first through-via130may be formed by performing a plating process. According to some embodiments of the present inventive concept, a metal seed layer including titanium (Ti), copper (Cu), or the like may be formed on a lower surface of the first through-via130.

Referring toFIG.6C, the first semiconductor chip120may be disposed on the first front surface FS1of the first redistribution structure110. The first semiconductor chip120may be mounted in a flip-chip manner. For example, the first semiconductor chip120may be connected to the first redistribution layer112through the first connection bumps123that are formed on the connection pads120P.

The underfill layer125may be formed between the first semiconductor chip120and the first redistribution structure110. The underfill layer125may be formed using a capillary underfill (CUF) process, but the present inventive concept is not limited thereto.

Referring toFIG.6D, the first encapsulant140may be formed to encapsulate the first semiconductor chip120and the first through-via130. The first encapsulant140may be formed to cover upper surfaces of the first semiconductor chip120and the first through-via130. For example, the first encapsulant140may be formed to completely cover upper surfaces of the first semiconductor chip120and the first through-via130. The first encapsulant140may be formed by applying and curing an insulating resin. The insulating resin may include, for example, EMC.

Referring toFIG.6E, upper portions140u1and140u2of the first encapsulant140may be removed to expose the first semiconductor chip120and the first through-via130. For example, the first portion140u1of the first encapsulant140may be removed by applying a planarization process, and then the second portion140u2of the first encapsulant140may be removed by applying an etch-back process. The first non-active surface120S2of the first semiconductor chip120and the upper end130T of the first through-via130may be exposed by the surface140S of the first encapsulant140. The upper end130T of the first through-via130may protrude, relative to the first non-active surface120S2of the first semiconductor chip120and the surface140S of the first encapsulant140.

Referring toFIG.6F, the first package structure100and the second package structure200may be bonded and combined to each other using the film structure300. The second package structure200may be formed by performing a process similar to that ofFIGS.6A to6E. The first package structure100and the second package structure200may be compressed to both sides of the film structure300, respectively, so that the first through-vias130and the second through-vias230overlap each other. For example, first, the film structure300may be attached to the surface140S of the first encapsulant140, and then second package structure may be compressed to the film structure300so that the first through-via130and the second through-via230may be electrically connected to each other.

Referring toFIG.6G, the film structure300may be disposed between the first package structure100and the second package structure200to electrically connect the first through-vias130to the second through-vias230. The first through-via130and the second through-via230may be electrically connected to each other by conductive particles in the film structure300. Thereafter, the lower layer13may be separated, and the middle layer12and the upper layer11may be removed to expose the first rear surface BS2of the first redistribution structure110. Next, solder balls may be attached to the bump structure160and a sawing process may be performed thereon to complete the semiconductor package illustrated inFIG.1A.

As described above, according to an embodiment of the present inventive concept, by minimizing the interface formed between the encapsulant (e.g., ‘140’ or ‘240’) and the semiconductor chip (e.g., ‘120’ or ‘220’), process risks, such as voids and interface delamination, may be reduced and heat dissipation characteristics of a semiconductor package may be improved. In addition, since the first package structure100and the second package structure200, which are discontinuously and independently manufactured, are physically and electrically combined by the film structure300, process risk may be reduced.

According to embodiments of the present inventive concept, the semiconductor package having improved heat dissipation, and yield may be provided by combining independently formed package structures to each other.