Interim power source system and method

A method for power control includes determining a load power of a load coupled to an output of an isolated AC/DC power supply. The method also includes, when the determined load power is less than a first threshold load power, providing the load power to the load from an interim power source.

TECHNICAL FIELD

The present invention relates generally to a system and method for supplying power, and in particular embodiments, to an interim power source system and method.

BACKGROUND

Power supply systems convert input power to output load power by, for example, converting between Alternating Current (AC) and Direct Current (DC) or by changing a voltage level. For some of these power supply systems, a nominal voltage level that is expected of the input power may correspond to a standardized voltage level provided by an input power source connected to the power supply system. Examples of input power sources include AC and High Voltage DC (HVDC) transmission systems, batteries, fuel cells, generators, alternators, solar power converters, other power supply systems, etc.

Components of various power supply systems may include isolating components having outputs with low electrical dependence on their inputs, voltage-regulated components having an acceptable range of voltages at their outputs despite varying output currents or input voltages, and embedded components.

Electrical loads drawing load power from the power supply system may include, for example, domestic appliances, office equipment, industrial machinery, or a server computer that hosts software applications to support tasks in a network data center.

SUMMARY OF THE INVENTION

In accordance with a first example embodiment of the present invention, a method for power control is provided. The method includes determining a load power of a load coupled to an output of an isolated AC/DC power supply, and when the determined load power is less than a first threshold load power, providing the load power to the load from an interim power source.

In accordance with a second example embodiment of the present invention, a method for controlling a power supply is provided. The method includes determining an input voltage of the power supply. The method also includes, when the determined input voltage of the power supply is less than a first threshold voltage and is not less than a second threshold voltage, providing load power to a load at the same time from both the power supply and an interim power source.

In accordance with a third example embodiment of the present invention, a device is provided. The device includes an isolated AC/DC power supply including an output coupled to an external load. The device also includes a control circuit configured for determining a load power of the external load, and when the determined load power is less than a first threshold load power, providing the load power to the external load from an interim power source.

In accordance with a fourth example embodiment of the present invention, a system for power control is provided. The system includes a primary-side circuit, including an input coupled to an input voltage, a secondary-side circuit including an output coupled to an external load. The secondary-side circuit further includes a battery and a first microcontroller. The system also includes an AC/DC power supply disposed in the same mechanical housing as the battery. The AC/DC power supply includes a first transformer that couples power from the primary-side circuit to the secondary-side circuit. The first microcontroller includes a sensing input coupled to an output of the battery and to the output of the secondary-side circuit.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to preferred embodiments in a specific context, systems and methods for power systems using a supplemental, interruption-resistant, interim power source. Embodiments of the present invention may also be applied to other circuits including, but not limited to switched-mode power supplies and other types of power supply systems.

In various embodiments, a power system has a main power stage that includes a Switched-Mode Power Supply (SMPS) used to convert power from an AC power line to a DC load power suitable, for example, to provide power to a computer server system including processors and disk drives. In order to ensure that the server system remains functional during short interruptions in the AC power line, including a so-called brownout where the line voltage is momentarily reduced, as well as the complete loss of power, a supplemental, interruption-resistant power source of an interim power stage may be provided to supplement a main power conversion system. Such interim sources may include, for example, batteries that may be switchably coupled to the DC output of the main power system. During operation, when a loss of AC line voltage is detected, the batteries of the interim power stage are coupled to the DC server load. In some embodiments, the main power conversion system may include multiple power supplies redundantly connected between the AC power line and the server system. In some embodiments, the interim power stage may be housed in a separate chassis from the one or more power supplies of the main power stage.

In embodiments of the present invention, batteries are integrated within the design of the overall power system to not only provide backup load power but also to provide load power when conditions arise that would otherwise cause components of the main power stage to operate inefficiently, or at high temperatures. As an example, upon a detection of a brownout condition, power to the load is provided by the battery, and one or more components of the main power stage are shut down. The integration of the batteries prevents the main power stage from increasing the amount of current used by the SMPS to compensate after a PLD. In embodiments where the main power stage includes a Power Factor Correction (PFC) stage, the integration of the batteries prevents the PFC stage from increasing the amount of current to compensate during and/or after a PLD. Preventing such increased current also prevents a corresponding increase in operating temperatures and decrease in efficiencies. In server computer embodiments, the integrated batteries may be included on a server board or within the mechanical housing of a server Power Supply Unit (PSU).

In some embodiments, batteries may also be used to provide power to the load under lightly loaded conditions to prevent stress and inefficient operation of components such as switches and diodes of a PFC or SMPS of the main power stage. In one specific example, the batteries of the interim power stage may be used to supply power to a load when the load power is less than 40% of a specified full load power, which may be specified as an average load power with some moderate safety margin. By using the batteries in such conditions, SMPS topologies such as phase-shift Zero Voltage Switching (ZVS) may be used that provide high efficiency of the main power stage at high load power conditions, but which at lightly loaded conditions provide lower efficiencies, increased EMI radiation, and increased transistor thermal stress.

In some embodiments, batteries may also be used to provide at least a portion of power to the load under highly loaded conditions to reduce the hardware requirements of the main power stage. For example, an embodiment power system may have a battery dimensioned to support all expected levels of load power above a specified “full load power” level. Full load power may be specified as, e.g., the average value of the expected load power combined with a moderate safety margin. In such embodiments where the batteries are capable of providing load power support during the entire expected interval of peak load power, hardware costs may be reduced since the main power stage may be dimensioned to full load power rather than peak load power conditions.

FIG. 1Ashows an embodiment power configuration100that includes a power system121that has an Interim Source140and that is connected to a main input power source103. The main input power source103, which may be either a DC power source such as an HVDC power source or an AC power source such as a Power Distribution Unit (PDU), provides main input power with main input voltage Vmainto the power system121. The power system121includes an SMPS stage110that provides isolation and performs regulated DC-to-DC conversion and that may be, for example, a Pulse-Width Modulation (PWM) converter, an LLC Converter, etc. The SMPS stage110has a link capacitor bank111connected across its inputs that has a DC link voltage Vlink. The output of the SMPS stage110is connected to a DC power output of the power system121that provides power to a load138.

The Interim Source140, which may include one or more batteries, is also coupled to the DC output of the power system121to support the provision of DC power to the load138. In some embodiments, the Interim Source140provides at least a portion of the DC power to the load even under normal voltage conditions of the main input power source103, for example, when light or heavy load power is drawn from the load138.

A power system output capacitor bank190that has a voltage Voutis connected across the DC power output of the power system121. This power system output capacitor bank190may be pre-charged during a start-up phase to the nominal voltage of Vout. In embodiments that use, for example, an LLC converter in the SMPS stage110, this pre-charging may prevent a discharged output capacitor bank190from causing the SMPS stage110to switch at over-resonant frequencies during start-up. The pre-charging may thus allow synchronous rectification elements of the SMPS stage110to be more suitably selected for voltages that correspond more closely with normal operating conditions. In some embodiments, the Interim Source140provides the energy for pre-charging the power system output. For example, the power system output capacitor bank190may be charged directly from the Interim Source190during a start-up sequence.

A Micro-Controller (μC)150is coupled to the input and output of the SMPS stage110for communication and control such as, for example, controlling a switching rate, gain, etc. of the SMPS stage110. In some embodiments, the Interim Source140has a power connection to the microcontroller150so that it can provide power to control the power system121during at least a start-up phase of the power system121. Microcontroller150is also connected for sensing power and/or voltage conditions at the input of the SMPS stage110and at the power system output capacitor bank190. The microcontroller150controls the use of the Interim Source140by the power system121to achieve desired system objectives, such as, for example, reducing a minimum hold-up time that is required during an AC/HVDC line voltage dropout or brownout condition, reducing DC link voltage variation, or reducing power system efficiency losses during light or heavy load conditions. The microcontroller150is also coupled to the Interim Source140to sense the status of the Interim Source140, which may be, for example, a battery voltage level.

In some embodiments, a bidirectional DC-to-DC converter is coupled between the Interim Source140and the output of the power system121. For example, such embodiments may couple, between the battery output and a regulated power system output having a nominal voltage of 12V, a buck/boost converter, a buck converter working as a buck from the battery output and as a boost from the power system output, an inverting buck-boost converter, etc. In other embodiments, the battery may be coupled directly to the output of the power system121. For example, the voltage provided by a battery coupled directly at the power system output may be a fluctuating battery voltage from 9V to 14.5V instead of a stable, regulated DC rail, and the output of the power supply may act as a constant voltage source or constant current source to charge the battery. In some of these directly coupled embodiments, no-load and lightly loaded conditions may be avoided by charging the batteries.

FIG. 1Bshows a power configuration100A, which is an embodiment of the power configuration100ofFIG. 1A, and which includes a server120. The server120includes a Power Supervisor180coupled to microcontroller150via a bidirectional power management communication link to communicate battery status and to provide information about power flow to and from server120. The load138includes Voltage Regulators (VRs)114, fans116, and server loads118that may be, for example, server computer blades. The main input power source103is implemented in embodiment100A as a PDU102receiving three-phase AC power from a distribution transformer, and this PDU102may include a step-down transformer182and distribution panels184.

FIG. 1Cshows a power configuration100B that is an embodiment of the power configuration100in which both the microcontroller150and the Interim Source140are included in a PSU106A that has its own mechanical housing. The PSU106A is coupled between main power input and DC power output of power system121A. The Interim Source140has a power connection to the microcontroller150so that it can provide power to control the PSU106A during at least a start-up phase of the PSU106A.

FIG. 1Dshows a power configuration100C that is an alternative embodiment of the power configuration100ofFIG. 1Ain which both the microcontroller150and the Interim Source140are external to the mechanical housing of a PSU106B. The microcontroller150controls the operation of the PSU106B, and the Interim Source140provides power to the microcontroller150during at least a start-up phase of power system121B. The Interim Source140has a power connection to provide power to the DC output of the power system121B, and the Interim Source140may also power one or more internal components of the PSU106. In other embodiments, Interim Source140is an internal component of the PSU while microcontroller150is external to the PSU. In still other embodiments, Interim Source140is external to the PSU while microcontroller150in an internal component of the PSU.

FIGS. 2A-2Ehelp illustrate the effect of the Interim Source140on required hold-up time, thermal dissipation, and link capacitance by showing the effect of a main input power dropout on an example single-source power system202that does not include an Interim Source140. Referring toFIG. 2A, single-source power system202, which achieves a hold-up time of, e.g., 20 milliseconds, receives main input power having a voltage Vmain. The power system202has a DC output voltage Vout. A DC link voltage Vlinkis the voltage across a link capacitor bank211connected across the inputs of a SMPS stage210of the single-source power system202, and this DC link voltage has a nominal voltage of Vlink_nomand a minimum specified voltage of Vlink_min.

Referring now toFIG. 2B, the ratios of Vlinkand Voutrelative to Vlink_nomfor single-source power system202are plotted against time during an exemplary dropout of the main input voltage Vmain. At first, a normal operating condition occurs from 0 to 20 milliseconds, during which Vlinkof single-source power system202is maintained near its nominal value, and Voutof single-source power system202is maintained at a constant fraction of Vlink_nom. In this example, a dropout of the main input voltage Vmainoccurs at 20 milliseconds and continues thereafter. Accordingly, Vlinkbegins to decay at about 20 milliseconds. From about 20 milliseconds to about 40 milliseconds, Vlinkhas not yet decayed below Vlink_min, and thus Voutis regulated by SMPS stage210to be maintained at the constant fraction of Vlink_nom. Since power system202only achieves a holdup time of about 20 milliseconds, however, in the example ofFIG. 2Bafter a time of about 40 milliseconds has expired, Vlinkhas decayed below Vlink_min. Thus Voutis no longer regulated by SMPS stage210and is allowed to drop below the constant fraction of Vlink_nom.

Referring now toFIG. 2C, a comparison plot is made of the Vlinkof power system121compared to that of the single-source power system202in response to a dropout of the main input voltage Vmain. The Vlinkof single-source power system202starts to decay when the dropout occurs and continues to decay until the dropout condition is over, and then it requires a period of high-current flow to charge link capacitor bank611to bring its Vlinkback to nominal. Relative to the Vlinkof the single-source power system202, however, the Vlinkof power system121decays for only a very short period. The Interim Source140prevents further decay of Vlinkby supplementing load power, which is reflected back through SMPS stage110to bring the Vlinkof power system121near to its nominal value. Thus, in some embodiments, the Interim Power Source140may reduce the minimum required hold-up time of power system121relative to power system202. Furthermore,FIG. 2Dplots exemplary minimum link capacitances against exemplary values of Vlink_minfor the single-source power system202, but supplementing load power by the Interim Source140may reduce these minimum link capacitances for embodiments of power system121.

Furthermore, in some embodiments of power system121that use an LLC converter or similar topology in the SMPS stage110, reducing hold-up time may allow use of a transformer with a reduced airgap or without an airgap, which decreases energy losses and reduces the difficulty and expense of manufacturing the transformer. In some embodiments the required hold-up time of power system121is reduced by half relative to power system202. In an example, given the same link capacitance and the same range of Vlink_nomfrom 380 to 420V at full load power, if the time in which link capacitance211of power system202decays from Vlink_nomto Vlink_minwere 20 milliseconds, then under the same conditions the minimum hold-up time for power system121would be not greater than 10 milliseconds.

Furthermore,FIG. 2Cshows that the Vlinkof power system121stays nearly constant. In some embodiments, power system121maintains Vlinkrelative to its nominal value within a range of 80% to 120%, inclusive. The reduced variation of Vlinkof power system121in turn reduces the voltage regulation requirements of SMPS Stage110.

In some embodiments having reduced variation of the link voltage Vlinkof the SMPS stage110, a PWM-controlled topology may be used in the SMPS stage110without sacrificing duty cycle for rarely occurring operation points. Such PWM-regulated topologies reserve a maximum duty cycle for operation at their lowest required input voltage and may include, for example, Single-Transistor Forward (STF), Two-Transistor Forward (TTF), Interleaved TTF (ITTF), phase shift ZVS, push-pull, active-clamp, hard switching half-bridge, and hard switching full bridge topologies.

Additionally, for embodiments of power system121that receive an AC main input power (e.g., from the PDU102ofFIG. 1B) and that include a PFC stage, reducing the amount of stored energy of the link capacitor bank111that is discharged during a dropout condition may prevent large restart currents from being switched by the PFC stage to recover the nominal Vlink. Some embodiments may also reduce stress on the PFC stage by preventing increased current during and/or after a brown-out condition which is depicted inFIG. 2E, and which may last much longer than a dropout condition. In such embodiments, the Interim Source140may take over at least a portion of the load power during at least a portion of the brown-out time interval, where the duration of load power supported by the Interim Source140is dependent on the battery size, the severity of the brown-out, and the load power level.

Furthermore, reducing PFC currents in some embodiments of the power system121during and/or after a dropout or brownout may reduce power losses and thermal stresses of the PFC stage relative to power system202and may allow the use of technologies, products, or packages that have higher RDSonvalues or that are less capable of thermal dissipation. For example, power system202may uses various exemplary switching Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) in a PFC stage, and these various PFC MOSFETs experience increased temperatures as the main input voltage drops, as depicted inFIG. 2F. These increased temperatures in power system202require increased thermal dissipation. In an embodiment, power system121relaxes this thermal dissipation constraint relative to power system202and uses Surface Mount Device (SMD) packages instead of, e.g., TO247 packages. Use of such SMD packages may allow automated board mounting, decreased parasitic inductance, and the use of fast switching components in the PFC stage such as advanced super-junction devices and Gallium Nitride High Electron Mobility Transistors (GaN HEMTs).

FIG. 3helps illustrate the benefit of reducing the required voltage regulation range of embodiments of the SMPS stage110that are implemented as resonant LLC DC/DC converters.FIG. 3plots the gain versus normalized switching frequency (Fx) curves of six different LLC converters at three different m values, where m is the ratio of total primary inductance (magnetizing inductance plus resonant inductance) versus resonant inductance. For a given LLC converter curve and m-ratio, such as, for example the curve Q5 on the m=3 plot ofFIG. 3, a gain boost region has a minimum and a maximum switching frequency bound. The minimum bound is a switching frequency below which hard commutation events may occur, and the maximum bound occurs at the normalized switching frequency of Fxequal to 1, i.e., at the resonant frequency. The gain provided by the LLC converter decreases with increasing Fxin the boost region up to the resonant frequency. Since a voltage regulation range required for SMPS stage110of power system121is reduced relative to that of single-source power system202, peak gain is less likely to be needed from the SMPS stage110. Thus, in some LLC converter embodiments of SMPS stage210, the LLC converter may be driven at near resonant frequency throughout a wider range of main input power and load power conditions, thereby achieving improved efficiency and reducing the likelihood of hard commutation events.

Furthermore, for a given LLC converter curve (e.g., curve Q5), the peak gain provided by the boost region decreases with increasing m-ratio. The reduced requirement for peak gain of LLC converter embodiments of SMPS stage110allows them to be implemented with an increased m-ratio. For example, an m-ratio equal to 10 or greater may be used in some LLC converter embodiments of SMPS stage110. In high-m embodiments, the converter's magnetizing inductance may be increased, resulting in lower magnetizing current, as well as lower conduction losses in the transformer core and in the printed circuit board and switches of the power system121. To reduce any increase in delay time due to decreased magnetizing current, in some embodiments of SMPS110an LLC converter may use transistors with a small figure of merit RDSon×Qoss, where Qossis the transistor's output capacitance charge. For example, GaN HEMTs may be used which have a RDSon×Qossfigure of merit up to ten times lower than silicon-based super-junction devices with the same RDSonand voltage rating.

FIG. 4plots the main input voltage Vmainof power system121as a fraction of its nominal value against time periods during which various operating conditions of the main input power source103may occur. Such operating conditions include a normal operating condition, a brown-out operating condition, and a dropout operating condition. The main input power source103has a normal operating condition when Vmainis between 80% and 120% of its nominal value, inclusive. For example, when the nominal voltage of Vmainis 225V, a normal operating condition is present when Vmainis between 180V to 270V, inclusive. The main input power source103has a brown-out operating condition when Vmainis not less than 40% but less than 80% of its nominal value. For example, when the nominal voltage of Vmainis 225V, a brown-out operating condition is present when Vmainis not less than 90V but less than 180V. The main input power source103has a dropout operating condition when Vmainis less than 40% of its nominal value. For example, when the nominal voltage of Vmainis 225V, a dropout operating condition is present when Vmainis less than 90V.

Referring again toFIG. 4, during period402, main input power source103has a normal operating condition and a mode of operation is activated for power system121such that power to the load138is taken from main input power source103. During period404, a dropout of the main input voltage occurs and hold-up power is provided to the load138by DC link capacitor bank111via the SMPS stage110. As the dropout condition continues during the next period406, load power is taken from the Interim Source140. During period408, a brown-out condition of the main input voltage occurs, and load power is partly taken from main input power source103and partly taken from Interim Source140. During period410, normal operation of the main input power source103resumes, power to the load138is taken from main input power source103, and the Interim Source140slowly recovers its stored energy. In embodiments that charge the battery from the output of the SMPS stage110, because the time interval for recharging the Interim Source140is longer than the time interval for recharging the DC link capacitor bank111, burst mode frequencies that are outside the audible range may be used in the SMPS stage110.

FIG. 5is a graph showing the source of load power for an embodiment of the power configuration100ofFIG. 1A.FIG. 5plots a combined power of the main input power that is converted through the power system121and the interim source power, against the fraction of a specified full load power that is demanded by the load. The plot ofFIG. 5is for an embodiment that has a linear relationship between these variables that are plotted against each other. In other embodiments, these variables may be related by a non-linear relationship.

The amount of power provided by the main input power source103is capped at 100% of full load power, which may be specified, for example, as an expected average load power, combined with some moderate safety margin. Thus, when the load power fraction is greater than 100% of full load power, only the portion of load power equal to full load power is provided by the main input power source103, and the remainder of load power is provided by the Interim Source140. In an embodiment, the Interim Source140is capable of providing load power support during the entire expected interval of peak load power, which allows hardware costs to be reduced since the SMPS110is only required to be dimensioned to full load power rather than peak load power conditions. For example, for a peak load power level of 800 Watts (W) for the overall power system, using the Interim Source140to cap a maximum output requirement of the SMPS110to a full load power of 400 W may allow the power system121to include two redundantly connected PSUs that are each implemented as, e.g., PSU106B ofFIG. 1D, each with only 400 W maximum power output. Such redundantly connected 400 W PSUs may decrease hardware costs while maintaining the same load power uptime relative to providing two 800 W power supplies.

At no load power or very light load power conditions, main input power is not converted to the DC output of power system121, so that power is taken from Interim Source140alone. For example, in the embodiment ofFIG. 5, when the load power fraction is less than 40% of full load power, the power system121does not use any main input power but instead the load power is provided only by the Interim Source140. The conversion of main input power to the output of Power System121may be interrupted by, for example, turning off the SMPS stage110, or in embodiments of power system121that feed the SMPS stage110from a PFC stage, by turning off the PFC stage.

Referring again toFIG. 5, when the load power fraction is in the range of 40% to 100% of full load power, the power to the load is provided only by the main input power source103. At the low end of this range (e.g., 40% of full load power), the SMPS stage110may be operated efficiently in burst mode for relatively long time intervals of, e.g., hundreds of milliseconds to even seconds. In some embodiments, limiting the range of load power provided by the main input power source to between 40% and 100% of full load power reduces dynamic load stress on secondary-side synchronous rectification elements of the SMPS stage110, so that these synchronous rectification elements may be designed for voltages in accordance with commonly occurring operating conditions.

In some embodiments that include LLC converters or similar topologies for the SMPS stage110, providing power only from the Interim Source140for load power levels that are less than 40% of full load power may prevent various low-load inefficiencies of SMPS components that would otherwise occur. In such embodiments, providing low load power levels only from Interim Source140may be done, for example, instead of implementing a capacitor in parallel with the converter's primary-side switches, such an implementation avoids decreased reliability due to high voltage across the capacitor, limited maximum switching frequency, increased device costs, and increased space requirements. As another example, providing low load power levels only from Interim Source140may also prevent the parasitic capacitance of the converter's synchronous rectification switches from reducing efficiency. As a further example, providing low load power levels only from Interim Source140may prevent hard commutation of the converter's body diodes such as might otherwise occur, e.g., during burst mode operation when the converter is not fully charged or its half-bridge is turned on at a conflicting point in time.

In some embodiments where the SMPS stage110includes an LLC converter or similar topology, providing low load power levels only from Interim Source140may also allow reducing the use of burst mode and may thereby reduce load power ripple current, acoustic noise, control complexity, and reliability risk (especially of the converter's primary-side switches). In some embodiments where the LLC converter or similar topology has a primary-side switching node that includes fast, efficient switches with high dV/dt such as, e.g., super-junction switches and other switches with low RDSon×A values, providing low load power levels only from Interim Source140may also prevent reduced efficiency caused by transformer coupling capacitance.

FIG. 6Aprovides an embodiment power system621of the power system121ofFIG. 1Athat includes a single microcontroller650. The power system621implements the SMPS stage110as a PWM stage610, and the power system621includes an Auxiliary (AUX) DC-to-DC converter626and Isolation Circuit615. The Isolation Circuit615may include multiple sub-circuits such as, for example, multiple optocouplers, to provide isolation between multiple inputs and outputs of the Isolation Circuit215. The power system also includes a Bridge Rectifier (BR)690and a PFC stage608. The PFC stage608includes a switching circuit that may be implemented, for example, as a MOSFET. The Interim Source140is implemented as one or more batteries652connected by a bidirectional DC/DC converter624, such as, for example, a buck-boost converter.

PWM stage610ofFIG. 6Aprovides at least a portion of a DC output power of power system621during an AC input power dropout or brownout. During such abnormal power conditions, DC power is also output from the batteries652via the DC/DC converter624to provide at least a portion of the DC output power to the load638from the power system621. A sensing input of the microcontroller650is also connected to sense the DC output of the power system621to detect, for example, a low Voutcondition.

A control output of microcontroller650is provided to the primary side of PWM stage610via the Isolation Circuit615to control primary-side switching of the PWM stage610, including controlling a primary-side switching rate. Another control output of the microcontroller650is provided directly to the secondary side of the PWM Stage610and is used to control secondary-side PWM switching such as, for example, synchronous rectification switching. Bidirectional control is provided between inputs and outputs of microcontroller650and those of DC/DC converter624to close a switching feedback control loop of the DC/DC converter624. A sensing output from the batteries652is also provided to microcontroller650to indicate a battery voltage level.

Communication, control, and sensing may also occur between microcontroller650and other components of the power system621by way of Isolation Circuit615. Switching signals of AUX converter626are provided by a control output of Isolation Circuit615. A control output of Isolation Circuit615is also provided to PFC stage608so that, for example, the microcontroller650may coordinate switching of the PWM stage610and the PFC stage608, and may turn off PFC stage608under certain operating conditions. A sensing output from the DC input to the PWM stage610is provided to Isolation Circuit615.

Single-phase AC power that is input to the power system621is provided to BR690. DC power is output from BR690to PFC stage608. DC power is output from PFC stage608to PWM Stage610across a DC link that includes a link capacitor bank611coupled in parallel with the PWM Stage610.

DC power is also output, under at least some operating conditions, from BR690to AUX converter626and from AUX converter626to power the power supplies of various components such as microcontroller650in order to charge batteries652, and to pre-charge the power system DC output capacitor bank290via DC/DC converter624. In some embodiments, AUX converter626has a wide range of voltage regulation relative to DC/DC converter624and PWM Stage610.

FIG. 6Bshows an embodiment power system621A, which includes minor modifications of the power system621. In power system621A, the functions of the microcontroller650have been divided into two microcontrollers, a Primary-side Micro-Controller (μCprim)650A and a Secondary-side Micro-Controller (μCsec)650B. These two microcontrollers provide coordinated control of the power system621to achieve desired system objectives such as, for example, minimizing required hold-up time or reducing switching losses. The primary-side microcontroller650A and secondary-side microcontroller650B coordinate by bi-directional communication and control signaling through the Isolation Circuit615. The use of primary-side microcontroller650A allows, in some embodiments, to relax microcontroller performance requirements of secondary-side microcontroller650B relative to that of microcontroller650ofFIG. 6A. The primary-side microcontroller650A provides many of the control signals that were provided, via the Isolation Circuit615, by the microcontroller650ofFIG. 6A. The secondary-side microcontroller650B sends and receives the remaining control, communication, and sensing signals that were sent and received by microcontroller650in the embodiment ofFIG. 6A.

Referring again to the embodiment ofFIG. 6B, power to primary-side microcontroller650A is provided by AUX converter626. AUX converter626and primary-side microcontroller650A are coupled to auxiliary input capacitor bank692, which may be charged from the primary windings of AUX converter626.

AUX converter626receives switching control signals and sends power condition information by way of a bi-directional communication and control signal path between AUX converter626and primary-side microcontroller650A. The primary-side microcontroller650A uses a bi-directional communication and control path with PFC stage608to receive current readings and rectified voltage readings and to send switching control signals so that, for example, switching of the PFC stage608may be coordinated with switching of the PWM Stage620, and so that PFC stage608may be turned off under certain operating conditions. The sensing output from the DC output of PFC stage608is also provided to primary-side microcontroller650A.

FIG. 6Cshows an embodiment power system621B, which includes minor modifications of the power system621A ofFIG. 6B. Relative to batteries652of power system621A, batteries652A of power system621B have a higher voltage so that they may be connected to the DC power output of the power system621B without requiring any voltage conversion. Therefore DC/DC converter624is no longer needed in power system621B. Under some conditions, the batteries652A directly supplement the DC output power provided to the load638. The batteries652A may thus be included in some embodiments as an internal component of a PSU of the power system621B. Since the batteries652A are connected directly to the output of the PWM Stage620, they are charged directly from the output of the PWM Stage620instead of from the AUX converter626that was used to charge the batteries652in power system621A ofFIG. 6B.

FIG. 6Dshows an embodiment power system621C, which includes minor modifications of the power system621A ofFIG. 6B. In power system621C, the power needed by the secondary-side microcontroller650B and collateral logic circuitry is not provided by AUX converter626, but instead is provided from the batteries652through a DC/DC Point-of-Load (PoL) converter629.

AUX converter626ofFIG. 6Bhas been replaced by a Pulse Transformer (XFMR)628and an Auxiliary Winding627of a transformer of the PWM stage610. The batteries652are charged from the DC/DC Converter624. The Pulse Transformer628and Auxiliary Winding627are both coupled to the primary-side microcontroller650A and to the auxiliary input capacitor bank692. During a start-up sequence, power can be transferred from the batteries652to the primary-side microcontroller650A through Pulse Transformer628. Once the start-up sequence has completed, power needed at the primary-side microcontroller650A can be derived from Auxiliary Winding627, and the Pulse Transformer628becomes inactive.

In some embodiments, the replacement of AUX converter626ofFIG. 6Bby Winding627and Pulse Transformer628ofFIG. 6Dincreases efficiency and decreases cost but also decreases power available for power system primary-side components. The total cost of Winding627and Pulse Transformer628may be less than that of AUX converter626(which is controlled by microcontroller650A and which includes dedicated driver, switch and transformer circuits). Furthermore, in some embodiments the total efficiency of Winding627and Pulse Transformer628may be greater than that of a flyback-topology implementation of AUX converter626, which may show limited efficiency in the range of 70% to 80%. Additionally, if control is more centralized in the secondary-side microcontroller650B than in the primary-side microcontroller650A, then less power may be needed by the primary-side microcontroller650A and by any associated logic circuitry.

FIG. 6Eshows an alternative embodiment power system621D. power system621D is identical to the embodiment power system621C ofFIG. 6D, except that the DC/DC PoL converter629has been replaced by Linear Regulator630.

Illustrative embodiments of the present invention have the advantage of providing control of decentralized batteries in a server system to improve server uptime and availability while at the same time, relative to the inclusion of a centralized Uninterruptible Power Supply (UPS) and any associated infrastructure, improving server architecture scalability and power flow efficiency to reduce cost of electricity and total cost of ownership. In some embodiments, such decentralized batteries may yield an increased power flow efficiency of 3 to 5%. Further advantages of decentralized battery embodiments include supporting survival functions of individual servers in enterprise server architectures where only one server may be capable of doing each specific task (e.g., running Systems-Applications-Products (SAP) data).

Further advantages of embodiments of the present invention include supporting load power from an interruption-resistant power source during a main input PLD to allow, for example, reduced hold-up time requirements, reduced current flow during system restoration, and reduced voltage regulation requirements of an SMPS stage. Reducing hold-up time requirements may allow, in some embodiments, reducing the capacitance and associated space and dollar expense of a DC link capacitance bank, and reducing or removing an LLC converter airgap to reduce energy losses and manufacturing expense. Reducing current during system restoration provides advantages such as, for example, reducing power losses and thermal stresses of a PFC stage and allowing the use of a wider variety of PFC technologies, such as less thermally dissipative SMD technologies.

Reducing the link voltage variation of the SMPS stage may allow, in some embodiments, the use of efficient PWM-based SMPS topologies without sacrificing duty cycle for rarely occurring operation points. In some embodiments that use an LLC converter or similar SMPS topology, advantages of reduced voltage regulation requirements may include allowing magnetizing inductance to be significantly increased, and allowing the SMPS stage to be switched at a near-resonant frequency throughout a wide range of power conditions to increase efficiency and reduce the likelihood of hard commutation events. Increasing magnetizing inductance of an LLC converter provides advantages of, for example, reducing magnetizing current and reducing conduction losses associated with the energy stored in the LLC resonant tank. In some LLC embodiments, less stringent timing requirements for system restoration may allow the use of burst mode frequencies outside the audible range. Additional advantages of embodiments of the present invention include pre-charging a power system output from an interim source to prevent over-resonant startup switching of an LLC converter and to allow its components to be chosen in accordance with frequently occurring operating conditions.

Further advantages of illustrative embodiments of the present invention include using an interim source to limit the range of load power required from a main power stage, including supplementing peak load power to reduce hardware costs of the main power stage, and supporting light load or no-load power operation to provide increased efficiency of an SMPS stage. In some embodiments, limiting the range of load power provided by the main power stage may also reduce dynamic load stress on switching elements of the SMPS.

The following additional example embodiments of the present invention are also provided. In accordance with a first example embodiment of the present invention, a method for power control is provided. The method includes determining a load power of a load coupled to an output of an isolated AC/DC power supply, and when the determined load power is less than a first threshold load power, providing the load power to the load from an interim power source.

Also the foregoing first example embodiment may be implemented to include one or more of the following additional features. The method may also be implemented such that the isolated AC/DC power supply is a uni-directional power supply configured to transfer power from an input of the isolated AC/DC power supply to the load.

The method may also be implemented to further include, when the determined load power is greater than a second threshold load power, providing the load power to the load at the same time from both the power supply and the interim power source. The method may also be implemented such that the first threshold load power is 40% of the second threshold load power.

The method may also be implemented to further include determining an input voltage of the power supply. In such an implementation, when the determined input voltage of the power supply is less than a first threshold voltage and is not less than a second threshold voltage, the method may also include providing the load power to the load at the same time from both the power supply and the interim power source.

The method may also be implemented to further include, when the determined input voltage is less than a second threshold voltage, turning off the power supply. In such an implementation, when the determined input voltage is not less than the first threshold voltage and is not greater than a third threshold voltage and the determined load power is not less than the second threshold load power and is not greater than the first threshold load power, the method may also include providing the load power to the load from the power supply. The method may also be implemented such that the first threshold voltage is 80% of a predetermined nominal input voltage, the second threshold voltage is 40% of the predetermined nominal input voltage, and the third threshold voltage is 120% of the predetermined nominal input voltage.

The method may also be implemented to further include, when the determined input voltage is less than the first threshold voltage, providing sufficient load power from the interim power source such that a link voltage of a link capacitor is maintained for at least 10 milliseconds at not less than 80% of a predetermined nominal link voltage and at not greater than 120% of the predetermined nominal link voltage. In such an implementation, the link capacitor may be coupled to a first stage of the power supply coupled to the input voltage, and the link capacitor may also be coupled to a switched-mode stage of the power supply coupled to the load.

The method may also be implemented such that turning off the power supply includes turning off a power factor correction stage of the power supply. The method may also be implemented to further include charging an output capacitor bank coupled across the load to a predetermined nominal DC output voltage during a start-up sequence. In such an implementation, providing the load power to the load from the interim power source may include providing the load power from a battery to a computer server including a processor. The method may also be implemented such that the power supply and the battery are disposed in the same mechanical housing.

In accordance with a second example embodiment of the present invention, a method for controlling a power supply is provided. The method includes determining an input voltage of the power supply. The method also includes, when the determined input voltage of the power supply is less than a first threshold voltage and is not less than a second threshold voltage, providing load power to a load at the same time from both the power supply and an interim power source.

Also the foregoing second example embodiment may be implemented to include one or more of the following additional features. The method may also be implemented to further include determining a load power of the power supply. In such an implementation, the method may also include, when the determined load power is greater than a first threshold load power, providing the load power to the load at the same time from both the power supply and the interim power source, and when the determined load power is less than a second threshold load power, providing the load power to the load from the interim power source.

The method may also be implemented to further include, when the determined input voltage is less than a second threshold voltage, turning off the power supply. In such an implementation, the method may also include, when the determined input voltage is not less than the first threshold voltage and is not greater than a third threshold voltage and the determined load power is not less than the first threshold load power and is not greater than the second threshold load power, providing the load power to the load from the power supply. The method may also be implemented such that the second threshold load power is 40% of the first threshold load power, the first threshold voltage is 80% of a predetermined nominal input voltage, the second threshold voltage is 40% of the predetermined nominal input voltage, and the third threshold voltage is 120% of the predetermined nominal input voltage.

In accordance with a third example embodiment of the present invention, a device is provided. The device includes an isolated AC/DC power supply including an output coupled to an external load. The device also includes a control circuit configured for determining a load power of the external load, and when the determined load power is less than a first threshold load power, providing the load power to the external load from an interim power source.

Also the foregoing third example embodiment may be implemented to include one or more of the following additional features. The device may also be implemented such that the isolated AC/DC power supply is a uni-directional power supply configured to transfer power from an input of the isolated AC/DC power supply to the external load. The device may also be implemented such that the control circuit is further configured for, when the determined load power is greater than a second threshold load power, providing the load power to the external load at the same time from both the power supply and the interim power source.

The device may also be implemented such that the control circuit is further configured for determining an input voltage of the power supply. In such an implementation, the control circuit may also be configured for, when the determined input voltage is less than a first threshold voltage and is not less than a second threshold voltage, providing the load power to the external load at the same time from both the power supply and the interim power source. The device may also be implemented such that the first threshold load power is 40% of the second threshold load power.

The device may also be implemented such that the control circuit is further configured for, when the determined input voltage is less than the second threshold voltage, turning off the power supply. In such an implementation, the control circuit may also be configured for, when the determined input voltage is not less than the first threshold voltage and is not greater than a third threshold voltage and the determined load power is not less than the first threshold load power and is not greater than the second threshold load power, providing the load power to the external load from the power supply. The device may also be implemented such that the first threshold voltage is 80% of a predetermined nominal input voltage, the second threshold voltage is 40% of the predetermined nominal input voltage, and the third threshold voltage is 120% of the predetermined nominal input voltage.

The device may also be implemented such that the power supply further includes a first stage coupled to the input voltage, a switched-mode stage coupled to the external load, and a link capacitor coupled between the first stage and the switched-mode stage. In such an implementation, the control circuit may be further configured for, when the determined input voltage is less than the first threshold voltage, providing sufficient load power from the interim power source such that a link voltage of the link capacitor is maintained for at least 10 milliseconds at not less than 80% of a predetermined nominal link voltage and at not greater than 120% of the predetermined nominal link voltage.

The device may also be implemented such that the power supply further includes a power factor correction stage. In such an implementation, the control circuit may be further configured for, when the determined input voltage is less than a second threshold voltage, turning off the power supply by turning off a power factor correction stage of the power supply.

The device may also be implemented such that the control circuit is further configured for charging an output capacitor bank coupled across the external load to a predetermined nominal DC output voltage during a start-up sequence. In such an implementation, the control circuit may include a microprocessor, the external load may include a computer server that includes a second processor, and the interim power source may include a battery disposed in the same mechanical housing as the power supply.

In accordance with a fourth example embodiment of the present invention, a system for power control is provided. The system includes a primary-side circuit, including an input coupled to an input voltage, a secondary-side circuit including an output coupled to an external load. The secondary-side circuit further includes a battery and a first microcontroller. The system also includes an AC/DC power supply disposed in the same mechanical housing as the battery. The AC/DC power supply includes a first transformer that couples power from the primary-side circuit to the secondary-side circuit. The first microcontroller includes a sensing input coupled to an output of the battery and to the output of the secondary-side circuit.

Also the foregoing fourth example embodiment may be implemented to include one or more of the following additional features. The system may also be implemented to further include an isolation circuit coupling control signals between the primary-side circuit and the secondary-side circuit. In such an implementation, the AC/DC power supply may be an isolated AC/DC power supply, the primary-side circuit may further include a link capacitor, and the first microcontroller may further include a first control output coupled through the isolation circuit to a primary-side switch circuit of the power supply. In such an implementation, the first microcontroller may further include a second control output coupled to an input of a secondary-side switch circuit of the power supply.

The system may also be implemented to further include an auxiliary power source coupled between the primary-side circuit and the secondary-side circuit, the auxiliary power source including a second transformer including an output coupled to a power input of the first microcontroller. The system may also be implemented such that the primary-side circuit further includes a second microcontroller coupled to the first microcontroller through the isolation circuit, the second microcontroller including a power input coupled to an output of the auxiliary power source and a sensing input coupled to an output of the link capacitor.

The system may also be implemented such that the second microcontroller is configured for determining an input voltage of the power supply. In such an implementation, the power supply may be configured for, when the determined input voltage of the power supply is less than a first threshold voltage and is not less than a second threshold voltage, providing load power to the external load at the same time from both the power supply and the battery.

The system may also be implemented such that the first microcontroller further includes a second sensing input coupled to an output of the link capacitor. The system may also be implemented such that the second transformer includes a pulse transformer, the auxiliary power source further includes an auxiliary winding of the first transformer, and the first microcontroller further includes a power input coupled to the output of the battery for receiving power during a start-up sequence. The system may also be implemented such that the secondary-side circuit further includes a DC-to-DC converter that includes a power input coupled to the output of the battery, a control input coupled to a third control output of the first microcontroller, and an output coupled to the external load.

The system may also be implemented such that the primary-side circuit further includes a bridge rectifier including an input coupled to the power supply, and a power factor correction stage coupled between an output of the bridge rectifier and an input of the link capacitor. In such an implementation, the power factor correction stage may include a transistor, and the secondary-side circuit may further include an output capacitor coupled across the external load.

The system may also be implemented such that the external load includes a computer server that includes a processor, the isolation circuit includes an optocoupler, and the primary-side switch circuit includes pulse width modulation controlled switches. The system may also be implemented such that the first microcontroller is configured for determining a load power of the external load, and the power supply is configured for, when the determined load power is less than a first threshold load power, providing the load power to the external load from the battery.