DC-DC converter load current estimation circuit

A method for estimating load current in a DC-DC converter, in some embodiments, comprises: identifying a converter capacitor in parallel with a converter load in a DC-DC converter; providing an estimation capacitor based on a capacitance of the converter capacitor; providing said estimation capacitor with an estimation capacitor current based on an inductor current flowing through an inductor in the DC-DC converter; driving an estimation voltage across the estimation capacitor toward a voltage present across the converter capacitor; and using the estimation voltage to generate an estimation current that estimates a load current passing through said converter load.

BACKGROUND

A direct current (DC)-DC converter is typically used to step down a power supply voltage to meet the needs of a particular circuit. In many instances, such circuits have variable loads—for example, in DC motors, which are found in innumerable types of electronic products, from medical equipment to automobiles. To conserve power while maintaining the proper voltage supply to the variable load, DC-DC converters often employ pulse width modulation (PWM), in which an input voltage that is rapidly switched on and off is applied to an output filter to regulate the voltage and current supplied to the load in an efficient manner. A PWM controller is used to control this switching operation. Many such controllers (e.g., current mode controllers) monitor the current flowing through a converter output inductor and use the inductor current signal as part of a feedback loop to improve the stability of the PWM control system.

Current mode controllers have improved stability relative to other types of controllers. However, they respond slowly to changes in the load current. This slow response results in deviations in the voltage supplied to the load. It is therefore desirable to maintain the superior stability of current mode control systems while improving the response time to changes in the load. This can be accomplished with the load current feed forward control method. Available load current feed forward control methods entail the sensing of load current using a series impedance between the output filter capacitor and the load. This approach is disadvantageous, however, because the impedance can produce added power loss and interfere with the voltage regulation to the load. A simple, lossless, non-interfering method of estimating the output current is therefore desired.

SUMMARY

At least some of the embodiments disclosed herein are directed to a method for estimating load current in a DC-DC converter, comprising: identifying a converter capacitor in parallel with a converter load in a DC-DC converter; providing an estimation capacitor based on a capacitance of the converter capacitor; providing said estimation capacitor with an estimation capacitor current based on an inductor current flowing through an inductor in the DC-DC converter; driving an estimation voltage across the estimation capacitor toward a voltage present across the converter capacitor; and using the estimation voltage to generate an estimation current that estimates a load current passing through said converter load. At least some of these embodiments may be modified in one or more ways, such as to include any or all of the following concepts, in any order and in any combination: wherein a first ratio of the capacitance of the converter capacitor to a capacitance of the estimation capacitor is equal to a second ratio of the estimation current to the load current; wherein a first ratio of the estimation capacitor current flowing to the estimation capacitor to a current flowing to the converter capacitor is equal to a second ratio of the estimation current to the load current; wherein the estimation capacitor current flowing to the estimation capacitor as a function of time is equal to a capacitance of the estimation capacitor multiplied by a rate of change of the estimation voltage; wherein driving said estimation voltage comprises providing the estimation voltage and a load voltage across said converter load to an operational transconductance amplifier that produces said estimation current; further comprising using the estimation current to drive a pulse width modulation (PWM) controller that controls the DC-DC converter; wherein using the estimation current to drive the PWM controller results in a faster response of the PWM controller to a change in said converter load than a response produced by a PWM controller voltage feedback loop.

At least some embodiments are directed to a system, comprising: an estimation capacitor associated with a converter capacitor in a DC-DC converter, said estimation capacitor receives an estimation capacitor current based on an inductor current passing through an inductor in the DC-DC converter; and an amplifier, coupled to the estimation capacitor, that receives a load voltage present across a converter load in the DC-DC converter and that receives an estimation voltage present across the estimation capacitor, wherein the amplifier generates an estimation current that estimates a load current passing through said load. At least some of these embodiments may be modified in one or more ways, such as to include any or all of the following concepts, in any order and in any combination: further comprising another amplifier that is used to provide said estimation capacitor current based on the inductor current passing through said inductor in the DC-DC converter; wherein an output of said another amplifier couples to a node, wherein an input to said amplifier couples to the node, and wherein said estimation capacitor couples to the node; wherein an output of said amplifier couples to said node via a feedback loop; wherein another input to said amplifier couples to said converter load; wherein the DC-DC converter is a buck converter.

At least some embodiments are directed to a system, comprising: a DC-DC converter that includes an inductor coupled to a converter capacitor and a converter load, said converter capacitor and said converter load coupled in parallel; a first differential amplifier, coupled to the inductor, that senses an inductor current passing through the inductor; an estimation capacitor, coupled to the first differential amplifier, that has a capacitance based on a capacitance of said converter capacitor, an estimation capacitor current passing to the estimation capacitor based on an output current of the first differential amplifier; and a second differential amplifier, coupled to the first differential amplifier and the estimation capacitor, that drives an estimation voltage across the estimation capacitor toward a load voltage present across said converter load, wherein the second differential amplifier generates an estimation current based on the load voltage and the estimation voltage to estimate a load current passing through said converter load. At least some of these embodiments may be modified in one or more ways, such as to include any or all of the following concepts, in any order and in any combination: wherein an output of the first differential amplifier, an input to the second differential amplifier, and said estimation capacitor all connect at a common node; wherein each of the first and second differential amplifiers is selected from the group consisting of operational amplifiers and operational transconductance amplifiers; wherein the system uses the estimation current to drive a pulse width modulation (PWM) controller that controls the DC-DC converter; wherein a first ratio of the estimation current to the load current is equal to a second ratio of the estimation capacitor current to a current flowing to said converter capacitor; wherein the estimation capacitor current as a function of time is equal to the capacitance of the estimation capacitor multiplied by a rate of change of the estimation voltage; wherein the DC-DC converter is a buck converter.

DETAILED DESCRIPTION

Disclosed herein is an estimation circuit that may be used to estimate the load current in a DC-DC converter. The estimation circuit estimates the load current using signals that are typically already available to the pulse width modulation (PWM) controller that controls the switching operation of the DC-DC converter. Specifically, the estimation circuit includes an estimation capacitor that is a scaled-down version of a converter capacitor in the DC-DC converter. The estimation circuit uses amplifiers (e.g., operational transconductance amplifiers (OTAs)) to provide a scaled-down version of the DC-DC converter's inductor filter current to the estimation capacitor in the estimation circuit. The ratio of the estimation capacitor capacitance and the DC-DC converter capacitor capacitance is the same or substantially similar to the ratio of the estimation capacitor current and the inductor filter current. The estimation voltage across the estimation capacitor and the load voltage across the DC-DC converter load are provided to an amplifier (e.g., OTA), which produces the estimation current. The estimation current forces the estimation voltage to match or be a predetermined ratio of the load voltage in the DC-DC converter, where the estimation current estimates the load current in the DC-DC converter. The PWM controller subsequently uses the estimation current to control the converter switching operation. The estimation circuit and the PWM controller's use of the estimation current produces a faster transient response to changes in the converter load than typically achieved by current mode PWM controllers.

FIG. 1is a schematic diagram of a system100including a DC-DC buck converter102, an illustrative estimation circuit104and a pulse width modulation (PWM) controller106, all of which couple to each other. The structure of the system100is described first, followed by a description of the operation of the system100. The DC-DC converter102includes a gate driver108; transistor-based switches110,112; a VINrail voltage supply114coupling to switch110and ground116coupling to switch112; a node117at which switches110,112couple to each other; an inductor118coupled to node117; a sense resistor120coupled to the inductor118; a converter capacitor122coupled to the sense resistor120; and a variable converter load124coupled to the converter capacitor122and the sense resistor120. An inductor current IOUT126flows through the inductor118and the sense resistor120; a current ICOUT128flows to the converter capacitor122; a load current ILOAD130flows through the converter load124; a load voltage VOUT132is present across the converter load124; ground131couples to the converter capacitor122; and ground133couples to the converter load124. The scope of this disclosure is not limited to the specific arrangement of circuit logic shown in the illustrative DC-DC buck converter102, nor are the techniques disclosed herein limited to use with a buck converter. To the contrary, the disclosed estimation circuit may be used in conjunction with any suitable type of current-mode-controlled DC-DC converter.

The illustrative estimation circuit104includes an amplifier (e.g., an operational transconductance amplifier (OTA))134having a non-inverting input138and an inverting input136; a node140that couples to an output of the amplifier134; an estimation capacitor142that couples to the node140; and another amplifier (e.g., an OTA)148that has an inverting input152that couples to node140. The amplifier148further includes a non-inverting input150that couples to load124in the DC-DC converter102. The amplifier148produces two identical or nearly identical outputs, one of which couples to the node140as a feedback loop, and the other of which couples to the PWM controller106as described below. The output of the amplifier134produces a current158; an estimation capacitor current ICEST160flows to the estimation capacitor142; an estimation current IEST156flows through the feedback loop that connects the amplifier148to node140; an estimation current IEST2154(identical to IEST156) flows between the amplifier148and the PWM controller106; and an estimation voltage V2146is present across the estimation capacitor142. The estimation capacitor142couples to ground144.

Parameters for the amplifiers134,148and the estimation capacitor142are chosen based on parameters for various components in the DC-DC converter102. Specifically, the capacitance ratio of the estimation capacitor142to the converter capacitor122is referred to herein as AI, and the current ratio of the estimation current IEST2154(or, equivalently, estimation current156) to the load current ILOAD130is also AI. Similarly, the current ratio of the estimation capacitor current160to the current128flowing to the converter capacitor122is AI, and the current158is equivalent to the product of the inductor current IOUT126and AI. The value of AImay be chosen as desired and as may be suitable. In at least some embodiments, however, the value of AIis chosen to be in the range of 0.00001 to 0.001, although the scope of disclosure is not limited to this or any other particular value or range of values. Achieving AIas the capacitance ratio of the estimation capacitor142to the converter capacitor122is done by selecting capacitors122,142with the appropriate capacitance parameters. Achieving AIfor the aforementioned current ratios is accomplished by selecting the amplifiers134,148with the appropriate gain values. Not all ratios described above need be precisely equal to AI. A suitable degree of error among ratios may be permitted by a circuit designer as appropriate. In at least some embodiments, this degree of error may be plus or minus 5 percent. The scope of this disclosure is not limited to the specific arrangement of circuit logic shown in the estimation circuit104ofFIG. 1.

The PWM controller106includes an amplifier (e.g., an OTA)162having inverting input164and non-inverting input166. The amplifier162outputs a current ILSENSE170to node168, which, in turn, couples to an output of the amplifier148on which IEST2154flows. The PWM controller106further includes a resistor172coupled to the node168and to a bias voltage source174. The bias voltage source174, in turn, couples to ground176. The node168further couples to a summation block178, which, in turn, couples to a ramp voltage source180and ground182. The output of the summation block178couples to the inverting input186of a comparator184. The non-inverting input of the comparator184couples to the output of a voltage feedback loop. The voltage feedback loop includes a resistor190that receives the load voltage VOUT132; a node192that couples to the resistor190, to an inverting input204of an amplifier (e.g., operational amplifier)202, and to a feedback loop that includes a resistor194coupled to a capacitor196; a node208coupled to the output of the amplifier202and to the feedback loop including the resistor194and capacitor196; and a reference voltage source198that provides a reference voltage VREFto the non-inverting input206of the amplifier202and couples to ground200. The node208provides an error signal VERRORto the non-inverting input188of the comparator184. The output of the comparator184is a PWM control signal210that is provided to the gate driver108and that controls the operation of the gate driver108, thus controlling the voltage provided to the converter load124. The scope of disclosure is not limited to the specific arrangement of circuit logic shown in the PWM controller106ofFIG. 1.

The general operation of the system100is now described. The gate driver108, which is controlled using the PWM signal210, opens and closes the switches110,112to regulate the voltage provided to the load124. Inductor current IOUT126passes through the node117, the inductor118and the resistor120. The inductor current IOUT126then splits into two separate currents: the current ICOUT128that flows to the converter capacitor122, and the load current ILOAD130that flows to the load124. A load voltage VOUT132is generated across the load124, and the same voltage is generated across the converter capacitor122since the load124and the converter capacitor122are coupled in parallel.

The voltage present across the resistor120is converted to a current158by the amplifier134. The current158, which is produced at node140, has a gain of AI. In at least some embodiments, AIis less than one, meaning that the current158is a scaled-down version of the current IOUT126. From node140, the estimation capacitor current ICEST160flows toward the estimation capacitor142. The estimation voltage V2146present across the estimation capacitor142is provided to the inverting input152of the amplifier148, and the load voltage VOUT132is provided to the non-inverting input150of the amplifier148. The amplifier has two outputs, each of which carries an estimation current IEST156or IEST2154. The output carrying IEST156couples to the node140in a feedback loop.

One aim of the estimation circuit104is to use readily available signals from the DC-DC converter102to mimic conditions at the converter capacitor122and converter load124. The estimation circuit104thus produces an estimation current IEST2154that is a substantially accurate estimation of the actual load current ILOAD130, and the estimation current IEST2154is used by the PWM controller106to control switching operations in the DC-DC converter102. To this end, the estimation capacitor142is a scaled-down version of the converter capacitor122. The amplifiers134,148are used to regulate the voltage and current that are applied to this estimation capacitor142. Specifically, the current ICEST160flowing to the estimation capacitor142is a scaled-down version of the current ICOUT128flowing to the converter capacitor122, and the amplifier148uses the feedback loop on which IEST156is carried to drive the estimation voltage V2146toward the load voltage VOUT132. The net effect of these activities is that the estimation voltage V2146matches or nearly matches the load voltage VOUT132, thus providing the same voltage across the estimation capacitor142as that present across the converter capacitor122; and that the estimation capacitor current ICEST160passing to the estimation capacitor142is a scaled-down version of the current ICOUT128passing to the converter capacitor122. (The estimation capacitor current ICEST160, expressed as a function of time, is equal to the estimation capacitor capacitance multiplied by the rate of change of the estimation voltage V2146, assuming that the estimation voltage V2146is equal to or closely approximates load voltage VOUT132.) Based on these conditions, the amplifier148produces the substantially identical estimation currents IEST156and IEST2154, both of which may be scaled-down estimates of the current ILOAD130.

Referring now to the PWM controller106, the amplifier162—like the amplifier134—amplifies the voltage across the resistor120and produces the current ILSENSE170to node168. The difference between ILSENSE170and the estimation current IEST2154flows to the resistor172. The voltage across the resistor172is thus the product of the resistance of resistor172and the difference between ILSENSE170and IEST2154. A suitable bias voltage may be introduced by bias voltage source174. The summation block178combines the potential across the resistor172and the ramp signal produced by voltage source180to produce an output signal that is provided to the inverting input186of the comparator184. The non-inverting input188of the comparator184is provided a signal VERRORfrom node208, which is produced as follows. The load voltage VOUT132is provided to resistor190. The voltage at node192is provided to inverting input204of the amplifier202, the non-inverting input206being coupled to a reference voltage source198. The node192couples to the output of the amplifier202via the feedback loop containing resistor194and capacitor196. The comparator184compares the signal received from node208to the signal received from the summation block178. The output210of the comparator184is provided to the gate driver108, which operates as described above. One advantage to using the estimation circuit104is that a change in the load124results in a change in the voltage across resistor172, which rapidly alters the PWM on time faster and more substantially than the signal VERRORcan. Thus, the estimation circuit104provides superior transient responses to changes in the load124. Although the parameters of the components in the estimation circuit104and DC-DC converter102are described in detail herein, the parameters of the components in the PWM controller106are not, as they may be appropriately selected as desired by one of ordinary skill in the art.

FIG. 2is a flow diagram of an illustrative method250to estimate the load current in a DC-DC converter in accordance with embodiments. The method250begins by identifying the converter capacitor (step252) and providing an estimation capacitor based on the converter capacitor (step254). As explained above, these capacitors may be selected as desired, with the ratio AIof the estimation capacitor capacitance to the converter capacitor capacitance also being the ratio of the currents to these capacitors and the ratio of the estimation current produced by the estimation circuit to the load current in the DC-DC converter circuit. The method250then includes driving the estimation voltage across the estimation capacitor to the converter capacitor voltage (i.e., the load voltage) and inducing an estimation capacitor current to the estimation capacitor in proportion (i.e., the value AI) to the current to the converter capacitor (step256). In this way, the voltage and current conditions associated with the converter capacitor122are mimicked for the estimation capacitor142. The method250next includes using the estimation voltage that is present across the estimation capacitor and the converter load voltage to produce an estimation current (step258). As explained, the estimation current is an estimation (e.g., a scaled-down version) of the load current ILOAD130. The estimation current is then used to drive the PWM controller (step260).

Numerous other variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations, modifications and equivalents. In addition, the term “or” should be interpreted in an inclusive sense.