An electronic circuit includes a bandgap circuit, a capacitor, a switch and a control circuit. The bandgap circuit is configured to generate a predefined reference voltage. The capacitor is coupled to an output port of the electronic circuit on which an output voltage is to be provided. The switch is connected between the bandgap circuit and the capacitor. The control circuit is configured to control the bandgap circuit and the switch so as to alternate between: first time intervals, during which the bandgap circuit is enabled and connected to the capacitor, the capacitor is charged using the reference voltage generated by the bandgap circuit, and the reference voltage is provided as the output voltage on the output port; and second time intervals, during which the bandgap circuit is disabled and disconnected from the capacitor, and the output voltage on the output port is supplied from the capacitor.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to voltage supplies, and particularly to methods and systems for supplying reference voltages.

BACKGROUND

Bandgap voltage reference circuits are commonly used for providing accurate reference voltages in electronic circuits. In some circuits and applications, low power consumption is a prime design consideration that has impact on power supply design. Stringent requirements on power consumption exist, for example, in battery-powered equipment having sleep modes, in network devices, and in many other types of electronic devices.

SUMMARY

An embodiment that is described herein provides an electronic circuit including a bandgap circuit, a capacitor, a switch and a control circuit. The bandgap circuit is configured to generate a predefined reference voltage. The capacitor is coupled to an output port of the electronic circuit on which an output voltage is to be provided. The switch is connected between the bandgap circuit and the capacitor. The control circuit is configured to control the bandgap circuit and the switch so as to alternate between: first time intervals, during which the bandgap circuit is enabled and connected to the capacitor, the capacitor is charged using the reference voltage generated by the bandgap circuit, and the reference voltage is provided as the output voltage on the output port; and second time intervals, during which the bandgap circuit is disabled and disconnected from the capacitor, and the output voltage on the output port is supplied from the capacitor.

In some embodiments, the control circuit is configured to transition between the first time intervals and the second time intervals by setting interim time intervals in which the bandgap circuit is enabled but disconnected from the capacitor. In an embodiment, the switch includes three transistors connected in a T-network configuration.

In an embodiment, an average current consumption of the electronic circuit is lower than an instantaneous current consumption of the bandgap circuit. In an example embodiment, the instantaneous current consumption of the bandgap circuit, when enabled, is higher than 13 μA, and the average current consumption of the electronic circuit is lower than 1 μA. In a disclosed embodiment, the bandgap circuit, the capacitor, the switch and the control circuit are sub-micron Complementary Metal Oxide Semiconductor (CMOS) components implemented in a single Integrated Circuit (IC).

There is additionally provided, in accordance with an embodiment that is described herein, a method for supplying electrical power. The method includes operating a bandgap circuit that is configured to generate a predefined reference voltage, a capacitor coupled to an output port on which an output voltage is to be provided, and a switch connected between the bandgap circuit and the capacitor. The bandgap circuit and the switch are controlled so as to alternate between: first time intervals, during which the bandgap circuit is enabled and connected to the capacitor, the capacitor is charged using the reference voltage generated by the bandgap circuit, and the reference voltage is provided as the output voltage on the output port; and second time intervals, during which the bandgap circuit is disabled and disconnected from the capacitor, and the output voltage on the output port is supplied from the capacitor.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments that are described herein provide improved electronic circuits and associated methods for supplying accurate reference voltages. The disclosed techniques utilize a bandgap reference circuit that generates a highly accurate reference voltage. In order to reduce average power consumption of the electronic circuit, in an embodiment, the bandgap reference circuit is disabled most of the time, and enabled only intermittently for short time intervals.

In some embodiments, the electronic circuit comprises a bandgap reference circuit, a capacitor, a switch and a control circuit. The capacitor is coupled to an output port of the electronic circuit, on which an output voltage is provided. The switch is connected between the output of the bandgap reference circuit and the output port. The control circuit is configured to enable and disable the bandgap reference circuit, and to close and open the switch.

During the short time intervals in which the bandgap reference circuit is enabled, the control circuit closes the switch, and thus connects the bandgap reference circuit to the capacitor and the output port. During these intervals the reference voltage supplied by the bandgap reference circuit is provided as the output voltage, and also used for charging the capacitor. During the remaining time, while the bandgap reference circuit is disabled, the control circuit opens the switch, and the output voltage is supplied by the capacitor.

In practice, the length of time for which the bandgap reference circuit can be kept disabled depends, to a large extent, on the leakage current of the switch. In some embodiments, the switch is designed for very low leakage current, e.g., using three transistors connected in a T-network configuration. When using this sort of switch, the bandgap reference circuit can be disabled for relatively long periods of time, while still maintaining the output voltage within specified limits. As a result, power consumption is further reduced.

The circuits and associated methods described herein facilitate, for example, the use of a medium-power bandgap reference circuit, while achieving power consumption similar to that of ultra-low-power bandgap reference circuits. When implemented in a sub-micron (e.g., 0.028μ, i.e., 28 nm) Complementary Metal Oxide Semiconductor (CMOS) process, for example, this solution eliminates the inherent drawbacks of ultra-low-power bandgap reference circuits, without compromising output-voltage accuracy.

For example, unlike ultra-low-power bandgap reference circuits, the disclosed circuits are characterized by very low leakage current, close correlation between design simulation and actual performance, very small unit-to-unit process-related variations, and fast start-up and response time. Moreover, the disclosed techniques achieve noise and precision performance typical of medium-power bandgap reference circuit.

In an example implementation, the instantaneous current consumption of the medium-power bandgap circuit, when enabled, is higher than 13 μA. When pulsed in accordance with the disclosed techniques, the average current consumption decreases to below 1 μA, with negligible degradation in output voltage precision.

The disclosed techniques are useful, for example, in Integrated Circuits (ICs) having low-power sleep modes, such as ICs used in battery-powered equipment.

FIG. 1is a block diagram that schematically illustrates a power supply circuit20in an Integrated Circuit (IC), in accordance with an embodiment that is described herein. Circuit20can be used in any suitable type of IC. Typically, although not necessarily, circuit20supplies operating voltages for an IC in a mobile communication or computing device that supports one or more power-saving sleep modes. One non-limiting example of such a device is a Near-Field Communication (NFC) device. Other example applications comprise ICs in other types of mobile devices such as Wi-Fi or Bluetooth devices, wearable equipment, power-management ICs, and automotive equipment, to name only a few.

In the present example, circuit20is powered by a battery whose voltage (denoted VBAT) is in the range 2.4-5.5V. For clarity,FIG. 1focuses on the operation of circuit 20 during a “deep-sleep” power-saving mode, in which the requirement for low power consumption is most stringent.

In the embodiment ofFIG. 1, circuit20comprises Always-On (AON) logic28, which is powered from VBAT by a low-power regulator32. Regulator32generates two regulated voltages denoted VDD1(0.9V) and VDD2(1.6V), typically on separate lines. AON logic28is active continuously as long as battery power is present, regardless of the mode of operation of circuit20. In an embodiment, regulator32consumes approximately 1.2 μA. Circuit20further comprises a switched bandgap (BG) reference circuit24, which is configured to produce a highly accurate reference voltage denoted VBG. The structure and operation of circuit24is addressed in detail below.

In the present example, circuit20produces two accurate regulated voltages—1.8V and 1.05V. Voltage VBG is supplied as input to a Low Drop-Out regulator (LDO)36that outputs the 1.8V output voltage (denoted AVDD18). An additional LDO44generates the 1.05V voltage (denoted AVDD105) from the 1.8V voltage AVDD18. Voltage AVDD18is also used for powering a Low-Power Oscillator (LPO)40that clocks AON logic28. In an example embodiment, LPO40generates a 256 KHz clock signal and consumes approximately 300 nA.

An inset at the bottom of the figure illustrates the internal structure of switched bandgap reference circuit24, in an embodiment. Circuit24comprises a bandgap (BG) reference circuit48, a capacitor52, a switch56and a control circuit60. (In some embodiments control circuit60is part of AON logic28. Nevertheless, circuit60is depicted separately from logic28in the figure for the sake of clarity.) In an embodiment, BG reference circuit48is a medium-power BG reference circuit that consumes approximately 13.3 μA when active, and capacitor52is a 1 pF capacitor. Circuit24provides VBG as output. VBG is also referred to herein as a reference voltage (VREF) and as the output voltage of circuit24.

Capacitor52is coupled to an output port of circuit24, on which the output voltage VBG is provided. Switch56is connected between the output of bandgap reference circuit48and the output port. Control circuit60is configured to enable and disable bandgap reference circuit48, and to close and open switch56. In some embodiments, control circuit60controls bandgap reference circuit48and switch56in a periodic pattern of time intervals, also referred to as “phases.”

Reference is now made toFIGS. 2 and 3.FIG. 2is a diagram that schematically illustrates a periodic pattern of phases in which control circuit60operates switched bandgap reference circuit24, andFIG. 3is a timing diagram showing corresponding signal levels, in accordance with an embodiment that is described herein. In the present example, each period of the pattern comprises four time intervals denoted “PHASE1” through “PHASE4”. Generally speaking, PHASE1is a phase in which BG reference circuit48is active, PHASE3is a phase in which BG reference circuit48is disabled, and PHASE2and PHASE4are transition phases intended to prevent undesired transient responses.

In PHASE1, control circuit60enables BG reference circuit48by setting an enable signal (denoted EN) to EN=“1”, and closes switch56by setting a switch-control signal (denoted SW) to SW=“1”. During PHASE1, the output of BG reference circuit48is connected to capacitor52and to the output port. The reference voltage supplied by BG reference circuit48(denoted BG_VOLTAGE inFIG. 3) is provided as the output voltage of circuit24(denoted VREF inFIG. 3). The reference voltage supplied by BG reference circuit48is also used for charging capacitor52.

In PHASE2, control circuit60retains BG reference circuit48in an active state (retains EN=“1”), but opens switch56by setting SW=“0”. PHASE2is a preparatory or transition phase, prior to disabling BG reference circuit48, and is intended to prevent undesired transient voltages that might be formed on the output port during disabling of BG reference circuit48.

In PHASE3, control circuit60retains switch56in an open state (retains SW=“0”), and disables BG reference circuit48by setting EN=“0”. During PHASE3, BG reference circuit48is disconnected from capacitor52and the output port. The output voltage of circuit24(denoted VREF inFIG. 3) is supplied by capacitor52. As seen inFIG. 3, capacitor52gradually discharges along PHASE3, and therefore VREF gradually drops from VREF to VREF−ΔVREF. Techniques for reducing the rate of decrease of VREF (which in turn enable extending the length of PHASE3) are addressed further below.

PHASE4is another preparatory or transition phase, prior to enabling BG reference circuit48, intended to prevent undesired transient voltages on the output port. In PHASE4, control circuit60retains switch56open (retains SW=“0”), and enables BG reference circuit48by setting EN=“1”.

FIGS. 2 and 3depict a single period of the four-phase pattern. Typically, control circuit60repeats this pattern periodically. Alternatively, in some embodiments the pattern may comprise only PHASE1and PHASE3(i.e., without transition phases PHASE2and PHASE4), or the pattern may comprise only one of the transition phases (PHASE2or PHASE4).

At the end of PHASE1, the voltage across capacitor52is equal to the reference voltage supplied by BG reference circuit48(BG_VOLTAGE). The capacitor can be viewed as “memorizing” BG_VOLTAGE, and supplying this voltage during PHASE3in which BG reference circuit48is disabled.

The performance gain achieved by circuit24can be best understood with reference toFIG. 3. As seen in the timing diagram, BG reference circuit48is enabled with a very small duty cycle. In particular, BG reference circuit48is inactive throughout PHASE3, which is by far the longest phase in the periodic pattern. Therefore, even though the instantaneous current consumption of BG reference circuit48is approximately 13.3 μA, the average current consumption of circuit24as a whole is only approximately 1.2 μA. At the same time, the output voltage of circuit24(VREF) is highly stable and accurate.

The durations of PHASE1, PHASE2, PHASE3and PHASE4are denoted T1, T2, T3and T4, respectively. In some embodiments, control circuit60(typically part of AON logic28) comprises logic (e.g., one or more Flip-Flops and auxiliary logic) that derives signals EN and SW from the clock signal supplied by LPO40. This clock signal has no stringent precision requirements, thereby enabling the LPO to consume only ˜300 nA. The period of the clock signal supplied by LPO40(in the present example 1/(256 KHz)) is thus equal to the period of the pattern of EN and SW (T1+T2+T3+T4).

In an embodiment, T1is chosen to be sufficiently long so as to (i) allow BG reference circuit48to stabilize, and (ii) allow capacitor52to re-charge from VREF−ΔVREF back to VREF. T1is thus dependent on the stabilization time constant of BG reference circuit48. T2is chosen sufficiently long to ensure that switch56is off before BG reference circuit48is disabled. T4is chosen sufficiently long to allow BG reference circuit48to stabilize before connecting switch56. Like T1, T4is also dependent on the stabilization time constant of BG reference circuit48.

T3is chosen to be as long as possible, as long as the voltage drop ΔREF is within specified precision limits. In some embodiments, T2is considerably smaller than T1, T3and T4(e.g., 1 nS), and is generated by a small delay element rather than derived independently from the clock signal of LPO40. An example implementation having actual numerical values for T1, T2, T3and T4is described further below. Alternatively, however, any other suitable time durations can be used.

As noted above, the achievable reduction in power consumption is directly related to the fraction of time during which bandgap circuit48is disabled, in the present example the ratio between the length of PHASE3(T3) and the combined length of the other phases. The maximal length that can be chosen for T3depends on ΔVREF, the amount of decrease of VREF during PHASE3. The decrease in VREF, in turn, is determined by the leakage of switch56. Therefore, any reduction in the leakage of switch56enables an increase in T3, and translates directly into lower average power consumption.

FIG. 4is a circuit diagram showing current leakage in a switched bandgap reference circuit, in accordance with an embodiment that is described herein. In this example, switch56is modeled by a transistor that is biased with a drain-source voltage (Vds) of 1V. The leakage current of this transistor (for large Vds) is denoted I_leak. Charge injection current (denoted I_inj) from LDO36is assumed negligible in “deep-sleep” mode. The “block” element at the bottom-right of the figure represents LPO40and LDO44(seen inFIG. 1).

In various embodiments, the tolerable maximum value of ΔREF may be, for example, on the order of 100 μV, 1 mV, or 10 mV, and is given by:

wherein C denotes the capacitance of capacitor52. Therefore, T3is given by:

When designing circuit24, it is important to reduce any kickback effects on VREF (charge injection originating from elements such as LDO36), e.g., using buffers or filtering. Circuit layout and shielding have a strong impact on this performance.

In an example implementation, switch56is implemented using a single N-channel MOSFET having a length of 1μ and a width of 0.27μ. At a temperature of 125° C. and Vds=1V, the leakage current I_leak is on the order of 175 pA (pico-Ampere) or less. In some practical implementations, a leakage current of 175 pA may be too high, because it limits T3to 5.7 us (for ΔVREF=1 mV and C=1 pF). The description that follows suggests an alternative implementation for switch56, which reduces the leakage current to approximately 2 pA. Such a low leakage current enables extending T3up to approximately 500 us (for ΔVREF=1 mV and C=1 pF), thereby reducing current consumption considerably.

FIG. 5is a circuit diagram that schematically illustrates a low-leakage switch64used in a switched bandgap reference circuit, in accordance with an embodiment that is described herein. The switch depicted inFIG. 5is suitable for implementing switch56ofFIG. 1above. In this embodiment, switch64comprises three transistors connected in a T-network configuration.

In the example ofFIG. 5the transistors comprise three N-channel MOSFETS denoted SW1, SW2and SW3. The source of SW1, the drain of SW2and the drain of SW3are connected to one another, to form the junction of the T-network. The source of SW2serves as the switch input (connected to the output of BG reference circuit48). The drain of SW1serves as the switch output (connected to capacitor52and to the output port of circuit24). The gates of SW1and SW2are connected to ground. The gate and source of SW3are biased with positive voltages VDD2(1.6V) and VDD1(0.9V), respectively. As seen inFIG. 1, these voltages are produced by regulator32for other purposes, and therefore their generation does not require additional hardware. Moreover, there is no stringent precision requirement on these voltages. In an embodiment, the gates of the three transistors SW1, SW2and SW3are connected to suitable control logic, which selectably connects each gate to ground or to some supply voltage depending on the phase.FIG. 5presents a simplified view of this scheme, referring to the biasing of the transistors when the switch is off (SW=“0”), i.e., during PHASE2, PHASE3and PHASE4.

The biasing scheme described above creates a potential of 0.9V at the junction of the T-network, and thus at the source of SW1. VREF in this embodiment is 1.0V, and therefore the Vds across SW1is only 0.1V. Due to the small Vds, the leakage current through SW1(and thus through switch64as a whole) is approximately 2 pA. As noted above, such a low leakage allows extending T3up to 500 us (for ΔVREF=1 mV and C=1 pF).

In various embodiments, various design procedures can be used for setting the various parameters of circuit24. In one example embodiment, the following procedure is used:1. Simulate the maximal leakage current I_leak (Fast-Fast (FF)/125° C.), and the injection current I_inj, over variations in Process, Voltage and Temperature (PVT). This simulation provides the value of I_leak+I_inj.2. Calculate the maximal tolerable ΔVREF, for the required precision.3. Choose the capacitance C of capacitor52, taking into consideration that C affects T1.4. Calculate T3from the previously-calculated parameters in accordance with Equation 2 above.5. Choose the values of T1and T4for the required precision using simulation over PVT. If the resulting T1is too high, go back to step 3 and modify the capacitance C. Repeat until T1is acceptable.6. Calculate the minimal clock rate of LPO40, which satisfies Fclk>1/min(T1,T4). Tclk is given by 1/Fclk.

In the above design procedure, the choice of capacitance C is a trade-off between chip area and power consumption. Larger C means larger T3but also larger T1. Smaller C means smaller T1but also smaller T3.

In an example execution of the above design procedure, the following numerical values are derived:1. Simulation yields I_leak=20 pA at FF/125° C., including variation of VDD1and VDD2over PVT. Simulation also yields I_inj=0, no dynamic current on the output of LDO36.2. Specified VREF=975 mV, and specified precision of 1% (9.75 mV).3. Desired capacitance set to 1 pF, for implementation using a MOS capacitor (MOSCAP).4. Resulting T3=500 μS, including simulation of required refreshing time to reach ΔVREF<9.75 mV over PVT.5. T1and T4are on the order of 30 μS, assuming the power consumption of bandgap reference circuit48is Ibg=13.3 μA. This calculation also considers settling time of bandgap circuit48with 1% precision. In order to support T1and T4values on the order of 30 μS, the LPO clock rate over PVT should be larger than 34 KHz (˜1/30 μS).6. T2can be set as low as 1 nS.7. The resulting calculated average power consumption of bandgap circuit48is Iavg<Ibg·(Tclk−T3)/Tclk=13 μA·60 μS/560 μS=1.4 μA. In simulation, the average power consumption was lower, only 0.6 μA. The difference is due to the fact that bandgap circuit48starts-up during T4. This effect is accounted for in the simulation but not in the calculation.

In an example simulation of circuit20over PVT, including real blocks for AON logic28, LPO40, bandgap circuit24and LDO36, the following performance was predicted:1. VREF start-up time is less than 20 μS, and VREF variation in “deep-sleep” mode is less than 1 mV.2. Average current consumed by bandgap circuit24is approximately 0.6 μA.3. Bandgap is 2.2% @3σ (22 mV @3σ), therefore VREF is 23 mV @3σ. (In this example, the variation of the bandgap voltage VBG is 22 mV over PVT. The additional error due to leakage is 1 mV, yielding the total variation of 23 mV.)4. An ultra-low-power bandgap circuit having similar continuous-time power consumption would achieve much lower precision.

The circuit configurations described herein, e.g., the configurations of power supply circuit20, switched bandgap reference circuit24, and switch56, shown inFIGS. 1, 2, 4, and 5, are example configurations that are depicted solely for the sake of clarity. In alternative embodiments, any other suitable circuit configuration can also be used. Circuit elements that are not mandatory for understanding of the disclosed techniques have been omitted from the figure for the sake of clarity. The different circuit elements are typically implemented using dedicated hardware or firmware, such as in one or more Application-Specific Integrated Circuits (ASICs) or Field-Programmable Gate Arrays (FPGAs).

In some embodiments, the circuits described herein, e.g., power supply circuit20, switched bandgap reference circuit24, and switch56, shown inFIGS. 1, 2, 4, and 5, are implemented in a sub-micron (e.g., 0.028μ, i.e., 28 nm) Complementary Metal Oxide Semiconductor (CMOS) process. Alternatively, any other suitable implementation or fabrication process can be used.

Although the embodiments described herein mainly address ultra-low power communication devices such as NFC devices, the methods and systems described herein can also be used in other applications, such as in any electronic device that uses reference voltages and is to have very low power consumption.