Differential hardmasks for modulation of electrobucket sensitivity

Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application No. PCT/US2016/068581, filed Dec. 23, 2016, entitled “DIFFERENTIAL HARDMASKS FOR MODULATION OF ELECTROBUCKET SENSITIVITY,” which designates the United States of America, the entire disclosure of which is hereby incorporated by reference in its entirety and for all purposes.

TECHNICAL FIELD

Embodiments of the invention are in the field of semiconductor structures and processing and, in particular, approaches based on underlying differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures.

BACKGROUND

Integrated circuits commonly include electrically conductive microelectronic structures, which are known in the arts as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are typically formed by a lithographic process. Representatively, a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed in order to form an opening in the photoresist layer. Next, an opening for the via may be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via.

In the past, the sizes and the spacing of vias has progressively decreased, and it is expected that in the future the sizes and the spacing of the vias will continue to progressively decrease, for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.). One measure of the size of the vias is the critical dimension of the via opening. One measure of the spacing of the vias is the via pitch. Via pitch represents the center-to-center distance between the closest adjacent vias.

When patterning extremely small vias with extremely small pitches by such lithographic processes, several challenges present themselves, especially when the pitches are around 70 nanometers (nm) or less and/or when the critical dimensions of the via openings are around 35 nm or less. One such challenge is that the overlay between the vias and the overlying interconnects, and the overlay between the vias and the underlying landing interconnects, generally need to be controlled to high tolerances on the order of a quarter of the via pitch. As via pitches scale ever smaller over time, the overlay tolerances tend to scale with them at an even greater rate than lithographic equipment is able to keep up.

Another such challenge is that the critical dimensions of the via openings generally tend to scale faster than the resolution capabilities of the lithographic scanners. Shrink technologies exist to shrink the critical dimensions of the via openings. However, the shrink amount tends to be limited by the minimum via pitch, as well as by the ability of the shrink process to be sufficiently optical proximity correction (OPC) neutral, and to not significantly compromise line width roughness (LWR) and/or critical dimension uniformity (CDU).

Yet another such challenge is that the LWR and/or CDU characteristics of photoresists generally need to improve as the critical dimensions of the via openings decrease in order to maintain the same overall fraction of the critical dimension budget. However, currently the LWR and/or CDU characteristics of most photoresists are not improving as rapidly as the critical dimensions of the via openings are decreasing.

A further such challenge is that the extremely small via pitches generally tend to be below the resolution capabilities of even extreme ultraviolet (EUV) lithographic scanners. As a result, commonly two, three, or more different lithographic masks may be used, which tend to increase the costs. At some point, if pitches continue to decrease, it may not be possible, even with multiple masks, to print via openings for these extremely small pitches using EUV scanners.

Thus, improvements are needed in the area of via manufacturing technologies.

DESCRIPTION OF THE EMBODIMENTS

Approaches based on underlying differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

One or more embodiments described herein is directed to electrobucket underlying hardmask “colors” that differentiate electrobucket performance. Applications may be directed toward one or more of electron beam (e-beam) lithography, extreme ultra-violet (EUV) lithography, general lithography applications, solutions for overlay issues (such as edge placement error, EPE), and general photoresist technologies. In an embodiment, materials are described that are suitable for improving performance of so-called “ElectroBucket” based approaches. In such an approach, a resist material is confined to a pre-patterned hardmask. Select ones of the electrobuckets are then removed using a high-resolution lithography tool, e.g., an e-beam or EUV lithography tool. Specific embodiments include use of materials and process flows to solve issues associated with unwanted via openings caused by lithographic critical dimension (CD) and/or overlay errors. Approaches described herein may be described as involving alternating and differentiated underlying hardmask technology.

To provide context, current fabrication techniques for vias involve a “blind” process in which a via opening is patterned in a stack far above an ILD trench. The via opening pattern is then etched deep down into the trench. Overlay errors accumulate and can cause various problems, e.g., shorts to neighboring metal lines. In an example, patterning and aligning of features at less than approximately 50 nanometer pitch requires many reticles and critical alignment strategies that are otherwise extremely expensive for a semiconductor manufacturing process. In an embodiment, by contrast, approaches described herein enable fabrication of self-aligned conductive vias, greatly simplifying the web of overlay errors, and leaving only one critical overlay step (Mx+1 grating). In an embodiment, then, offset due to conventional lithograph/dual damascene patterning that must otherwise be tolerated, is not a factor or is less of a factor for the resulting structures described herein.

To provide further context, a conventional resist electrobucket structure following electrobucket development may only partially clear after a mis-aligned exposure. Using a broader exposure window can ensure complete clearance of the selected electrobucket, but increases the risk of exposing non-selected neighboring electrobuckets. Thus, using conventional approaches, constraints regarding exposure size and misalignment tolerance are tight to avoid, if possible, either only partially cleared selected electrobuckets with some residual photoresist remaining or opening of non-selected electrobucket potentially leading to subsequent formation of conductive structures in unwanted locations.

More particularly, electrobuckets can be formed by fabricating “buckets” from a 2-dimensional grating to confine photoresist. The confined buckets of photoresist are then selectively exposed depending on where it is preferred to either keep or dissolve the photoresist. One challenge is the edge placement error control of such a patterning scheme. For example, if the electron beam is mis-aligned with respect to the bucket, then there is a risk of opening an unwanted bucket adjacent to the desired bucket.

By way of a first example,FIG. 1Aillustrates a cross-sectional view of a conventional aligned electrobucket process. A plurality of electrobuckets102of photoresist is confined among “bucket” features104over a hardmask layer106. An aligned e-beam or EUV exposure108of a select electrobucket location110is performed. Subsequently, the selected electrobucket110is opened upon development and removal of the selected and exposed photoresist in the location110. The result of such an aligned process is the opening of a selected electrobucket at the selected location110.

By way of a second example,FIG. 1Billustrates a cross-sectional view of a conventional mis-aligned electrobucket process. A plurality of electrobuckets122of photoresist is confined among bucket features124over a hardmask layer126. A mis-aligned e-beam or EUV exposure128of a select electrobucket location130is performed. Subsequently, the selected electrobucket130is opened upon development and removal of the selected and exposed photoresist in the location130. However, inadvertently, a neighboring electrobucket at location132is also opened because of the mis-alignment and resulting exposure by mis-aligned e-beam or EUV exposure128. Accordingly, in addition to a desired electrobucket location130, an unselected or undesired electrobucket is also opened at location132.

Addressing one or more of the issues raised in the description ofFIG. 1B, in accordance with one or more embodiments of the present invention, electrobucket approaches described herein involve the “coloring” hardmasks of adjacent buckets to change the sensitivity of the electrobucket. For example, some materials have more backscatter and generate more secondary electrons than other materials. By increasing the sensitivity of the desired bucket relative to the undesired bucket, reduce the risk of the undesired bucket opening due to mis-alignment of the electron beam with respect to the buckets can be reduced.

By way of example of a differentiated approach.FIG. 1Cillustrates a cross-sectional view of a mis-aligned electrobucket process, in accordance with an embodiment of the present invention. A plurality of electrobuckets142of photoresist is confined among bucket features144over a hardmask layer146. The hardmask146is differentiated in that it includes first hardmask portions146A and second hardmask portions146B. The materials of first hardmask portions146A and second hardmask portions146B, respectively, may differ in the extent of reaction to an exposure which effectively alters the performance of respective electrobuckets formed thereon.

Referring again toFIG. 1C, a mis-aligned e-beam or EUV exposure148of a select electrobucket location150is performed. Subsequently, the selected electrobucket150is opened upon development and removal of the selected and exposed photoresist in the location150. However, although a neighboring electrobucket at location152is also exposed to mis-aligned e-beam or EUV exposure128, the electrobucket at location152is not removed upon development of the electrobuckets. In an embodiment, the electrobuckets142on second hardmask portions146B are more sensitive to an e-beam or EUV exposure by the underlying second hardmask portions146B versus the neighboring or alternating electrobuckets142on first hardmask portions146B. Accordingly, in the end, only the desired electrobucket location150is opened, while the unselected or undesired electrobucket (albeit exposed electrobucket) at location152is not opened. Thus, increased edge placement error tolerance and reduced risk of undesired bucket opening may be achieved.

Referring again toFIG. 1C, in an embodiment, the second hardmask portions146B are rendered or modified to provide electrobuckets thereon with greater sensitivity to e-beam or EUV exposure as compared to electrobuckets formed on the first hardmask portions146A. In another embodiment, the first hardmask portions146A are rendered or modified to provide electrobuckets thereon with less or reduced sensitivity to e-beam or EUV exposure as compared to electrobuckets formed on the second hardmask portions146B. In either case, in an embodiment, the second hardmask portions146B provide for increased backscatter and the generation of more secondary electrons into electrobuckets thereon versus the backscatter and the generation of more secondary electrons provided by first hardmask portions146A.

In accordance with an embodiment of the present invention, approaches described herein involve differentiated hardmask fabrication underlying electrobuckets to increase reactivity of areas of wanted vias and/or to slow down areas of unwanted vias in contrast to existing state-of-the-art approaches, fabrication schemes described herein involve the fundamentally different approach of using a selective bottom-up electrobucket differentiation methodology. By employing such a selective bottom-up electrobucket differentiation methodology, the need for self-enclosed via structures which otherwise take up metal CD margins may be mitigated. In specific embodiments, processes described herein are more tolerant to edge-placement errors, in which an aerial image does not perfectly align to an electrobucket grid. As a result, the selected locations are ultimately cleared to provide open electrobucket locations following development. The non-selected locations which may also receive some exposure remain as closed electrobucket locations following development.

As an exemplary process scheme,FIGS. 2A-2Oillustrate cross-sectional views of various operations in a method of patterning using electrobuckets with differentiated hardmasks, in accordance with an embodiment of the present invention.

Referring toFIG. 2A, a starting structure200for a method of patterning using electrobuckets includes a second hardmask layer208formed on a first hardmask layer206formed on or above an inter-layer dielectric (ILD) layer204formed above a substrate202.

Referring toFIG. 2B, the second hardmask layer208is patterned to provide a plurality of backbone features210.

Referring toFIG. 2C, a plurality of hardmask spacers212is formed along the sidewalls of the backbone features210. The plurality of hardmask spacers212may be fabricated using a conformal deposition and subsequent anisotropic etching process. The structure ofFIG. 2Cmay be viewed as including a grating structure of the plurality of hardmask spacers212. In an embodiment, the grating structure includes the plurality of hardmask spacers212patterned using a pitch division patterning scheme, such as a pitch halving or a pitch quartering process scheme, using the plurality of backbone features210as a template of mandrel.

Referring toFIG. 2D, the first hardmask layer206is patterned to form first hardmask portions214. In an embodiment, the first hardmask layer206is patterned using an etch process as masked by the plurality of hardmask spacers212and the backbone features210.

Referring toFIG. 2E, second hardmask portions216are formed between and laterally adjacent to the first hardmask portions214. The first hardmask portions214and the second hardmask portions216together form a differentiated hardmask218. In one embodiment, the first hardmask portions214and the second hardmask portions216have substantially the same thickness, as is depicted inFIG. 2E. In other embodiments, the first hardmask portions214differ in thickness from the second hardmask portions216.

In an embodiment, the second hardmask portions216are formed using a deposition and etch back process to leave second hardmask portions216remaining. In another embodiment, the second hardmask portions216are formed using a selective deposition or growth process. In one such embodiment, selective deposition or growth is achieved by first spinning-on material over the entire structure ofFIG. 2Dand then “washing away” material that does not adhere to the exposed portions of ILD layer204. In another embodiment, selective deposition or growth is performed only on the exposed portions of ILD layer204using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. Whether a blanket deposition and etch process or a selective deposition or growth process is used, in an embodiment, the second hardmask portions216are ultimately only formed between alternating pairs of neighboring spacer features212and not between each pair of spacer features212(i.e., at locations110).

Referring toFIG. 2F, the plurality of backbone features210is removed from the structure ofFIG. 2E. In an embodiment, the plurality of backbone features210is removed using a wet etch selective to the materials of the hardmask spacers212, the first hardmask portions214and the second hardmask portions216. In another embodiment, the plurality of backbone features210is removed using a dry or plasma etch selective to the materials of the hardmask spacers212, the first hardmask portions214and the second hardmask portions216.

Referring toFIG. 2G, a photoresist layer220is formed over the structure ofFIG. 2Fto form a plurality of electrobuckets. In an embodiment, the photoresist layer220is formed within and is confined by the hardmask spacers212. In one such embodiment, the uppermost surface of the photoresist layer220is below an uppermost surface of the hardmask spacers212, as is depicted. Alternating ones of the electrobuckets formed by deposition of the photoresist layer220are formed above the first hardmask portions214of differentiated hardmask218, while remaining ones of the electrobuckets formed by deposition of the photoresist layer220are formed above the second hardmask portions216of differentiated hardmask218.

In an embodiment the photoresist layer220is formed over the structure ofFIG. 2Fusing a spin-on process. In an embodiment, the photoresist layer220has a photolyzable composition. In one such embodiment, the photolyzable composition includes an acid-deprotectable photoresist material. In an embodiment, a photo-acid generator (PAG) component is included and, in a specific embodiment, includes a material selected from the group consisting of triethyl, trimethyl and other trialkylsulfonates, where the sulfonate group is selected from the group consisting of trifluoromethylsulfonate, nonanfluorobutanesulfonate, and p-tolylsulfonate, or other examples containing —SO3 sulfonate anion bound to organic group. In an embodiment, the acid-deprotectable photoresist material is an acid-deprotectable material selected from the group consisting of a polymer, a molecular glass, a carbosilane and a metal oxide. In an embodiment, the acid-deprotectable photoresist material includes a material selected from the group consisting of a polyhydroxystyrene, a polymethacrylate, small molecular weight molecular glass versions of a polyhydroxystyrene or a polymethacrylate which contain ester functionality sensitive to acid-catalyzed deprotection to carboxylic acid, a carbosilane, and a metal oxide possessing functionality sensitive to acid catalyzed deprotection or cross-linking. In another embodiment, the photolyzable material is not a photo-acid generator (PAG)-based photolyzable material. In an embodiment, the photolyzable material is a positive tone material. In another embodiment, the photolyzable material is a negative tone material.

Referring toFIG. 2H, an electrobucket selection process involves exposing a portion of the structure ofFIG. 2Gto a lithography exposure222. In an embodiment, the lithography exposure222is performed using a relatively large exposure window. For example, in one embodiment, a location224is selected as a via location for ultimate electrobucket clearance. Neighboring electrobucket locations226represent locations that may be otherwise be exposed and cleared by a large exposure window and/or by a mis-aligned exposure window. However, even though the electrobucket locations226may be exposed by lithography exposure222, they are not opened upon eventual development because they are formed on the first hardmask portions214and not on the second hardmask portions216.

In an embodiment, the lithography exposure222involves exposing the structure to e-beam radiation or extreme ultraviolet (EUV) radiation. In an embodiment, the radiation has a wavelength approximately 13.5 nanometers. In another embodiment, the radiation has an energy in the range of 5-150 keV. In an embodiment, radiation has an energy having a wavelength of approximately 365 nanometers.

In an embodiment, the second hardmask portions216are rendered or modified to provide electrobuckets thereon with greater sensitivity to e-beam or EUV exposure as compared to electrobuckets formed on the first hardmask portions214. In another embodiment, the first hardmask portions214are rendered or modified to provide electrobuckets thereon with less or reduced sensitivity to e-beam or EUV exposure as compared to electrobuckets formed on the second hardmask portions216. In either case, in an embodiment, the second hardmask portions216provide for increased backscatter and the generation of more secondary electrons into electrobuckets thereon versus the backscatter and the generation of more secondary electrons provided by first hardmask portions214.

In an embodiment, subsequent to the lithography exposure222, a bake operation is performed. In one such embodiment, the bake is performed at a temperature approximately in the range of 50-120 degrees Celsius for a duration of approximately in the range of 0.5-5 minutes. The structure may then be subjected to a development process. The development process clears the exposed electrobucket222at location224(but not at locations226). In an embodiment, the neighboring electrobuckets at locations226do not clear upon development even though at least portions of the photoresist layer220in those locations may have been exposed to the lithography exposure222.

In an embodiment, developing the structure ofFIG. 2Hincludes, in the case of positive tone development, immersion or coating with standard aqueous TMAH developer (e.g., in a concentration range from 0.1M-1M) or other aqueous or alcoholic developer based on tetraalkylammonium hydroxides for 30-120 seconds followed by rinse with deionized (DI) water. In another embodiment, in the case of negative tone development, developing the structure includes immersion or coating with organic solvents such as cyclohexanone, 2-heptanone, propylene glycol methylethyl acetate or others followed by rinse with another organic solvent such as hexane, heptane, cyclohexane or the like.

Referring toFIG. 2I, using the remaining electrobuckets of photoresist layer220as a mask, the region of the second hardmask portion216of the differentiated hardmask218is removed from location224to provide a selected via location227in a once-patterned differentiated hardmask218′ above the now partially exposed ILD layer204. The remaining electrobuckets of photoresist layer220are then removed. In an embodiment, the region of the second hardmask portion216of the differentiated hardmask218is removed from location224using a selective wet etch or dry or plasma etch process. The remaining electrobuckets of photoresist layer220are then removed using an ash process.

At this stage, with a selected via location227formed in the once-patterned differentiated hardmask218′, the once-patterned differentiated hardmask218′ can be used as a via patterning mask for forming line and/or via trenches in the ILD layer204, akin to the patterning described below in association withFIG. 2N. However, it may be the case than a second via selection process is performed prior to patterning the ILD layer204, as is described below in association withFIGS. 2J-2M.

Referring toFIG. 2J, the remaining second hardmask portions216of the once-patterned differentiated hardmask218′ are modified to provide modified second hardmask portions228. In an embodiment, the modified second hardmask portions228provide for less reactive electrobuckets than provided for by the second hardmask portions216. In one such embodiment, the remaining second hardmask portions216of the once-patterned differentiated hardmask218′ are modified by an approach described below in association withFIGS. 4A-4Eor withFIGS. 5A-5D.

Referring toFIG. 2K, a photoresist layer230is formed over the structure of

FIG. 2Jto form a plurality of electrobuckets. In an embodiment, the photoresist layer230is formed within and is confined by the hardmask spacers212. In one such embodiment, the uppermost surface of the photoresist layer230is below an uppermost surface of the hardmask spacers212, as is depicted. Alternating ones of the electrobuckets formed by deposition of the photoresist layer230are formed above the first hardmask portions214, while remaining ones of the electrobuckets formed by deposition of the photoresist layer220are formed above the modified second hardmask portions228, with the exception of one electrobucket232formed at selected via location227. In an embodiment, the photoresist layer230is the same as or similar to the photoresist layer220described above.

Referring toFIG. 2L, a second electrobucket selection process involves exposing a portion of the structure ofFIG. 2Kto a lithography exposure234, which may be similar to the lithography exposure222described above. In an embodiment, the lithography exposure234is performed using a relatively large exposure window. For example, in one embodiment, a location236is selected as a via location for ultimate electrobucket clearance. Neighboring electrobucket location238represents a location that may be otherwise be exposed and cleared by a large exposure window and/or by a mis-aligned exposure window. However, even though the electrobucket location238may be exposed by lithography exposure234, it is not opened upon eventual development because it is formed on a modified second hardmask portion228and not on a first hardmask portion214.

In an embodiment, the modified second hardmask portions228are rendered or modified to provide electrobuckets thereon with less or reduced sensitivity to e-beam or EUV exposure as compared to electrobuckets formed on the first hardmask portions214. In another embodiment, however, the first hardmask portions214are rendered or modified to provide electrobuckets thereon with greater sensitivity to e-beam or EUV exposure as compared to electrobuckets formed on the modified second hardmask portions228. In either case, in an embodiment, the first hardmask portions214provide for increased backscatter and the generation of more secondary electrons into electrobuckets thereon versus the backscatter and the generation of more secondary electrons provided by modified second hardmask portions228. In an embodiment, the electrobucket at location236is developed as described above for electrobucket development at location224.

Referring toFIG. 2M, using the remaining electrobuckets of photoresist layer230as a mask, the region of the first hardmask portion214is removed from location236to provide a selected via location237in a twice-patterned differentiated hardmask218″ above the twice partially exposed ILD layer204. The remaining electrobuckets of photoresist layer230are then removed. In an embodiment, the region of the first hardmask portion214is removed from location236using a selective wet etch or dry or plasma etch process. The remaining electrobuckets of photoresist layer230are then removed using an ash process. At this stage, in an embodiment, via selection is complete.

Referring toFIG. 2N, the structure ofFIG. 2Mis exposed to an etch process used to form trenches238in a patterned dielectric layer204′. In one embodiment, the trenches238represent eventual interconnect line locations each having an associated underlying via. Accordingly, the etch process used to form trenches238is, in one embodiment, a via opening process based on selection and removal of one or more electrobuckets.

Referring toFIG. 2O, conductive lines and vias are fabricated. In an embodiment, conductive lines and vias are fabricated by removing remaining portions of the twice-patterned differentiated hardmask218″ not covered by the hardmask spacers212. Conductive line trenches240are then formed in the patterned dielectric layer204′ to form twice-patterned dielectric layer204″. The hardmask spacers212and any remaining portions of the twice-patterned differentiated hardmask218″ are then removed. Subsequently, metal lines242and conductive vias244are formed in the twice-patterned dielectric layer204″, e.g., by a metal deposition and planarization process.

In either case, whether one or two via selection operations are performed, the structure ofFIG. 2O, or like structures, may then be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 2O, or like structures, may represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed.

It is to be appreciated that the process scheme described in association withFIGS. 2A-2Omay represent a one-dimensional (1D) or a two-dimensional (2D) electrobucket approach. For example, in a 1D electrobucket approach, lines of the grating structure of hardmask spacers212extend without interruption over a long region. By contrast, in a 2D electrobucket approach, lines of such a grating structure may be interrupted at intervals at approximately the same pitch as the pitch of the lines of the grating structure of hardmask spacers212.

As an example of a 2D electrobucket approach.FIG. 3illustrates a plan view and corresponding cross-sectional views of a 2-dimensional structure for patterning using electrobuckets with differentiated hardmasks, in accordance with an embodiment of the present invention.

Referring toFIG. 3, the cross-sectional view taken along the a-a′ axis represents a similar cross-section view ofFIG. 2F. However, as seen in the plan view and the corresponding cross-sectional view taken along the b-h′ axis ofFIG. 3, a cross-grating structure300is formed at intervals along the grating structure of hardmask spacers212. In one embodiment, the cross-grating structure300is a hardmask layer that effectively confines electrobucket locations at intervals along the grating structure of hardmask spacers212. In an embodiment, the structure ofFIG. 3is subjected to operations described in association withFIG. 2Dand on to form vias that have locations confined in two dimensions.

In an embodiment, whether a 1D or 2D approach is used, approaches described herein involve the fabrication of regular structures covering all possible feature locations, such as all possible via locations, followed by selective patterning of only the desired or select features. In an embodiment, first or second hardmask material portions remain in the final structure at the corners of metal lines underneath any mis-landed vias.

As described briefly above, a hardmask portion can be changed from a more sensitive material to a less sensitive material. In a particular embodiment, a hardmask material is initially “stuffed” (e.g., a porous carbon doped oxide stuffed with titanium nitride, TiN), and then subsequently “de-stuffed.” In an exemplary processing scheme.FIGS. 4A-4Eillustrate cross-sectional views corresponding to various operations in a method of fabricating and using a differentiated hardmask in an electrobucket process, in accordance with an embodiment of the present invention.

Referring toFIG. 4A, a starting structure such as the structure ofFIG. 2Fcan include an initially porous hardmask portion216. The porous hardmask portion216has a plurality of pores formed therein.

In an embodiment, the porous hardmask portion216is a low-k porous dielectric material layer. In an embodiment, the porous hardmask portion216is formed using a spin-on deposition process. In an embodiment, the porous dielectric material is a highly porous, e.g., 50%, spin-on material that has been optimized to fill high aspect ratio features. In an embodiment, the porous dielectric material has 30% or more pore density. In one such embodiment, the porous dielectric material has a porosity approximately in the range of 40-60%, and preferably around 50%. In an embodiment, the pores are open cells pores in that they are interconnected and are not closed cell pores.

In an embodiment, the porous dielectric material is selected from a class of materials based on hydrosilane precursor molecules, where catalyst mediates reaction of Si—H bonds with cross-linkers such as water, tetraethoxyorthosilicate (TEOS), hexaethoxytrisilacyclohexane or similar multifunctional cross-linkers. In one such embodiment, the porous dielectric material is based on trisilacyclohexanes linked together by O groups. In other embodiments, alkoxy-silane based dielectric precursors or silsesquioxane (SSQ) are used to form the porous dielectric material. Although not limited to such material, in an embodiment, the porous dielectric material is a spin-on dielectric material based on a 1,3,5-trisilacyclohexane building block. Cross-linking with loss of solubility of such a material (or other silicon based dielectrics) can be initiated either thermally, or at lower temperatures, by use of acid, base or Lewis acid catalyst processes. In one embodiment, such low temperature catalysis is critical for the implementation of approaches described herein.

Referring toFIG. 4B, a loading process400is used to fill the pores of the porous hardmask portion216to form a pore-filled hardmask portion216′. In an embodiment, the pore-filled hardmask portion216′ has increased response to e-beam or EUV lithography to enhance electrobucket sensitivity.

In an embodiment, the pores of the porous dielectric material are filled using an atomic layer deposition (ALD) process. In one such embodiment, a slow and penetrating ALD process is used to fill the pores of the porous dielectric material. By using the above described two-operation process of spin-on deposition followed by ALD pore filling, chemical stability of the resulting pore-filled material may be achieved. In other embodiments, the pores of the porous dielectric material are filled using a second spin-on process.

In an embodiment, the pores of the porous dielectric material are filled with a metal-containing material. In one such embodiment, the metal-containing material is a metal nitride such as, but not limited to, titanium nitride (TiN) or tantalum nitride (TaN). In another such embodiment, the metal-containing material is a metal oxide such as, but not limited to, tantalum oxide (Ta2O5), titanium oxide (TiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO2).

Referring toFIG. 4C, a photoresist layer402of electrobuckets is used to pattern a via location404by a process such as described above in association withFIGS. 2G-2I.

Referring toFIG. 4D, the material used to fill or “stuff” the pores to form pore-filled hardmask portion216′ are removed by a process406, such as an evaporation or sublimation process.

Referring toFIG. 4E, a second photoresist layer408of electrobuckets is used to pattern a second via location410over a differentiated hardmask portion214. In an embodiment, the second via location410is formed by a process such as described above in association withFIGS. 2K and 2L.

In another particular embodiment, a hardmask portion is intentionally oxidized or reduced to change its electron backscatter/secondary electron generator properties. As an example,FIGS. 5A-5Dillustrate cross-sectional views corresponding to various operations in another method of fabricating and using a differentiated hardmask in an electrobucket process, in accordance with another embodiment of the present invention.

Referring toFIG. 5A, a starting structure such as the structure ofFIG. 2Fcan include an initially metallic hardmask portion216.

Referring toFIG. 5B, a photoresist layer500of electrobuckets is used to pattern a via location502by a process such as described above in association withFIGS. 2G-2I.

Referring toFIG. 5D, a second photoresist layer506of electrobuckets is used to pattern a second via location508over a differentiated hardmask portion214. In an embodiment, the second via location508is formed by a process such as described above in association withFIGS. 2K and 2L.

In an exemplary embodiment, approaches described above build on approaches using so-called “electrobuckets,” in which every possible feature, e.g. via, is pre-patterned into a substrate. Then, a photoresist is filled into patterned features and the lithography operation is merely used to choose select vias for via opening formation. In a particular embodiment described below, a lithography operation is used to define a relatively large hole above a plurality of electrobuckets that include photoresist and differentiated hardmask portions in alternating photoresist locations, as described above. Such a colored underlying hardmask photoresist electrobucket approach may be implemented to allow for larger critical dimensions (CD)s and/or errors in overlay while retaining the ability to choose the via of interest.

In general, one or more embodiments are directed to an approach that employs a subtractive technique to ultimately form conductive vias and, possibly, non-conductive spaces or interruptions between metals (referred to as “plugs”). Vias, by definition, are used to land on a previous layer metal pattern. In this vein, embodiments described herein enable a more robust interconnect fabrication scheme since alignment by lithography equipment is no longer relied on. Such an interconnect fabrication scheme can be used to save numerous alignment/exposures, can be used to improve electrical contact (e.g., by reducing via resistance), and can be used to reduce total process operations and processing time otherwise required for patterning such features using conventional approaches.

Applications of approaches described herein may be implemented to create regular structures covering all possible via (or plug) locations, followed by selective patterning of only the desired features. More specifically, one or more embodiments described herein involves the use of a subtractive method to pre-form every via or via opening using the trenches already etched. An additional operation is then used to select which of the vias and plugs to retain. As described above, such operations can be illustrated using “electrobuckets,” although the selection process may also be performed using a more conventional resist expose and ILD backfill approach.

In another aspect, a differentiated hardmask process is performed using two distinct photoresist deposition process, even though the same photoresist material may be deposited in both distinct operations. Such a two-operation photoresist approach may be used to direct or confine the effects of a differentiated hardmask material at alternating locations in that a break is provided between the photoresist material at neighboring locations. As an example,FIGS. 6A-6Gillustrate cross-sectional views of various operations in a method of patterning using electrobuckets with differentiated hardmasks, in accordance with an embodiment of the present invention.

FIG. 6Aillustrates a cross-sectional view of a starting structure600following deposition, but prior to patterning, of a first hardmask material layer604formed on an interlayer dielectric (ILD) layer602, in accordance with an embodiment of the present invention. Referring toFIG. 6A, a patterned mask606has spacers608formed along sidewalls thereof, on or above the first hardmask material layer604.

FIG. 6Billustrates the structure ofFIG. 6Afollowing first time patterning of the first hardmask layer and subsequent first electrobucket till, in accordance with an embodiment of the present invention. Referring toFIG. 6B, the patterned mask606and corresponding spacers608are used together as a mask during an etch to form trenches610through the first hardmask material layer604and partially into the ILD layer602. The trenches610are then filled with first hardmask portions697and first electrobuckets612which include a photoresist material.

FIG. 6Cillustrates the structure ofFIG. 6Bfollowing second time patterning of the first hardmask layer and subsequent second electrobucket fill, in accordance with an embodiment of the present invention. Referring toFIG. 6C, the patterned mask606is removed and a second plurality of trenches614is etched through the first hardmask material layer604and partially into the ILD layer602, between spacers608. Subsequently, the trenches614are filled with second hardmask portions699and second electrobuckets618which include a photoresist material. In one such embodiment, the second electrobuckets618and the first electrobuckets612are filled with the same photoresist material.

In an embodiment, the first hardmask portions697are rendered or modified to provide electrobuckets thereon with greater sensitivity to e-beam or EUV exposure as compared to electrobuckets formed on the second hardmask portions699. In another embodiment, the second hardmask portions699are rendered or modified to provide electrobuckets thereon with less or reduced sensitivity to e-beam or EUV exposure as compared to electrobuckets formed on the first hardmask portions697. In either case, in an embodiment, the first hardmask portions697provide for increased backscatter and the generation of more secondary electrons into electrobuckets thereon versus the backscatter and the generation of more secondary electrons provided by second hardmask portions699.

Referring again toFIG. 6C, the negative pattern of the spacers608is thus transferred, e.g., by two etch processes forming trenches610and614, to the first hardmask material layer604. In one such embodiment, the spacers608and, hence, the trenches610and614are formed with a grating pattern, as is depicted inFIG. 6C. In an embodiment, the grating pattern is a tight pitch grating pattern. In a specific such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be limited to mask606, but the pitch may be halved by the use of negative spacer mask patterning, as is depicted inFIGS. 6A-6C. Even further, although not shown, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the electrobuckets612and618, collectively, is spaced at a constant pitch and has a constant width.

FIG. 6Dillustrates the structure ofFIG. 6Cfollowing planarization to isolate the first and second electrobuckets from one another, in accordance with an embodiment of the present invention. Referring toFIG. 6D, the second electrobuckets618and the top portions of the spacers608are planarized, e.g., by chemical mechanical polishing (CMP), until the top surfaces of the first electrobuckets612are exposed, forming discrete second electrobuckets618. In one embodiment, the combination of first electrobuckets612and second electrobuckets618represent all possible via locations in a subsequently formed metallization structure. One of the first electrobuckets612is labeled as612A to indicate that it is selected from removal for ultimate via fabrication.

FIG. 6Eillustrates the structure ofFIG. 6Dfollowing exposure and development of two electrobuckets to leave selected via locations, in accordance with an embodiment of the present invention. Referring toFIG. 6E, a second hardmask620is formed and patterned on the structure ofFIG. 6D. The patterned second hardmask620reveals two of the first electrobuckets612. The selected electrobuckets are exposed to light irradiation, such as an e-beam or EUV exposure621. It is to be appreciated that description herein concerning forming and patterning a hardmask layer involves, in an embodiment, mask formation above a blanket hardmask layer. The mask formation may involve use of one or more layers suitable for lithographic processing. Upon patterning the one or more lithographic layers, the pattern is transferred to the hardmask layer by an etch process to provide a patterned hardmask layer.

In accordance with one embodiment, referring again toFIG. 6E, neighboring one of the second electrobuckets618are partially exposed, e.g., due to mis-alignment in the patterning of second hardmask620. In particular, two of the second electrobuckets618are inadvertently exposed at regions650, even though they have not been selected as locations for via fabrication. Thus, the selected ones of the first electrobuckets612are exposed to the EUV or e-beam radiation to a greater extent than the neighboring partially exposed ones of the second electrobuckets618. Subsequent to exposing the structure to EUV or e-beam radiation621, a first bake of the electrobuckets is performed. Subsequent to performing the first bake, the structure is exposed to ultraviolet (UV) radiation. In one embodiment, the mask620remains during the UV radiation and is then subsequently removed. However, in another embodiment, the mask620is first removed and the electrobuckets are then all exposed to the UV radiation to approximately the same extent. In either case, subsequent to exposing the structure to UV radiation, a second bake of the electrobuckets is performed.

Referring again toFIG. 6E, the electrobuckets are subjected to a develop process. During the develop process, the select one of the first electrobuckets612targeted for via fabrication are emptied in that the photoresist is removable. However, locations not selected for via fabrication, including the ones of the second electrobuckets618that were partially exposed at regions650, are not opened during the develop process, in that the resist material is not removable in the develop process because of the second hardmask portions699, as described above. The developing provides selected via openings613A.

FIG. 6Fillustrates the structure ofFIG. 6Efollowing etching to form via locations, in accordance with an embodiment of the present invention. Referring toFIG. 6F, the pattern of the via openings613A are subjected to a selective etch process, such as a selective plasma etch process, to extend the via openings deeper into the underlying ILD layer602, forming via patterned ILD layer602′ with via locations624. The etching is selective to remaining electrobuckets612and618and to the spacers608.

FIG. 6Gillustrates the structure ofFIG. 6Fin preparation for metal fill, in accordance with an embodiment of the present invention. Referring toFIG. 6G, all remaining first and second electrobuckets612and618are removed. The remaining first and second electrobuckets612and618may be removed directly, or may first be exposed and developed to enable removal. The removal of the remaining first and second electrobuckets612and618provides metal line trenches626, some of which are coupled to via locations624in patterned ILD layer602′.

FIG. 7illustrates a cross-sectional view of the structure ofFIG. 6Gfollowing metal fill and planarization to provide a metallization layer, in accordance with an embodiment of the present invention. Referring toFIG. 7, subsequent processing can include removal of spacers608and hardmask layer604, and metal fill of metal line trenches626and via locations624to form conductive metal lines700and conductive vias702, respectively. In one such embodiment, metallization is formed by a metal fill and polish back process. The structure ofFIG. 7may subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 7may represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. Referring again toFIG. 7, self-aligned fabrication by the subtractive approach may be complete at this stage. A next layer fabricated in a like manner likely requires initiation of the entire process once again. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

Additionally, it is to be appreciated that the approaches described in association withFIGS. 6A-6G and 7are not necessarily performed as forming vias aligned to an underlying metallization layer. As such, in some contexts, these process schemes could be viewed as involving blind shooting in the top down direction with respect to any underlying metallization layers. In another aspect, a subtractive approach provides alignment with an underlying metallization layer. Furthermore, a portion or remnant of a differentiated hardmask may be retained as a portion of an inter-layer dielectric of a metallization layer. As an example of both such aspects,FIGS. 8A-8Iillustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned via patterning using electrobuckets with differentiated hardmasks, in accordance with another embodiment of the present invention. In each illustration, at each described operation, an angled three-dimensional cross-section view is provided.

FIG. 8Aillustrates a starting point structure800for a subtractive via process following deep metal line fabrication, in accordance with an embodiment of the present invention. Referring toFIG. 8A, structure800includes metal lines802with intervening interlayer dielectric (ILD) lines804. It is to be appreciated that some of the lines802may be associated with underlying vias for coupling to a previous interconnect layer. In an embodiment, the metal lines802are formed by patterning trenches into an ILD material (e.g., the ILD material of lines804). The trenches are then filled by metal and, if needed, planarized to the top of the ILD lines804. In an embodiment, the metal trench and fill process involves high aspect ratio features. For example, in one embodiment, the aspect ratio of metal line height (h) to metal line width (w) is approximately in the range of 5-10.

FIG. 8Billustrates the structure ofFIG. 8Afollowing recessing of the metal lines, in accordance with an embodiment of the present invention. Referring toFIG. 8B, the metal lines802are recessed selectively to provide first level metal lines806. The recessing is performed selectively to the ILD lines804. The recessing may be performed by etching through dry etch, wet etch, or a combination thereof. The extent of recessing may be determined by the targeted thickness of the first level metal lines806for use as suitable conductive interconnect lines within a back end of line (BEOL) interconnect structure.

FIG. 8Cillustrates the structure ofFIG. 8Bfollowing formation of an inter-layer dielectric (ILD) layer, in accordance with an embodiment of the present invention. Referring toFIG. 8C, an ILD material layer808is deposited and, if necessary, planarized, to a level above the recessed metal lines806and the ILD lines804.

FIG. 8Dillustrates the structure ofFIG. 8Cfollowing deposition and patterning of a hardmask layer, in accordance with an embodiment of the present invention. Referring toFIG. 8Da hardmask layer810is formed on the ILD layer808. In one such embodiment, the hardmask layer810is formed with a grating pattern orthogonal to the grating pattern of the first level metal lines806/ILD lines804, as is depicted inFIG. 8D. In an embodiment, the grating structure formed by the hardmask layer810is a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the second hardmask layer810ofFIG. 8Dmay have hardmask lines spaced at a constant pitch and having a constant width.

FIG. 8Eillustrates the structure ofFIG. 8Dfollowing trench formation defined using the pattern of the hardmask ofFIG. 8D, in accordance with an embodiment of the present invention. Referring toFIG. 8E, the exposed regions (i.e., unprotected by810) of the ILD layer808are etched to form trenches812and patterned ILD layer814. The etch stops on, and thus exposes, the top surfaces of the first level metal lines806and the an lines804.

FIG. 8Fillustrates the structure ofFIG. 8Efollowing electrobucket formation in all possible via locations, in accordance with an embodiment of the present invention. Referring toFIG. 8F, first and second hardmask portions897and899, respectively, are included in alternating locations of all possible via locations. A photoresist816is then formed in all possible via locations above exposed portions of the recessed metal lines806. The photoresist material816is included in a plurality of electrobucket locations, of which locations816A,816B and816C are depicted inFIG. 8F. Thus, three different possible via locations816A,816B and816C can be seen in the view provided inFIG. 8F. Additionally, as depicted, the hardmask layer810may be removed from the patterned ILD layer814.

In an embodiment, the first hardmask portions897are rendered or modified to provide electrobuckets thereon with greater sensitivity to e-beam or UN exposure as compared to electrobuckets formed on the second hardmask portions899. In another embodiment, the second hardmask portions899are rendered or modified to provide electrobuckets thereon with less or reduced sensitivity to e-beam or EUV exposure as compared to electrobuckets formed on the first hardmask portions897. In either case, in an embodiment, the first hardmask portions897provide for increased backscatter and the generation of more secondary electrons into electrobuckets thereon versus the backscatter and the generation of more secondary electrons provided by second hardmask portions899.

It is also to be appreciated that the photoresist layer816may not ultimately be completely confined and separated in the electrobucket locations. That is, in other embodiments, a photoresist layer is used as a continuous layer over a grating structure. In one embodiment, then, the photoresist816is formed above and over the top surfaces of the ILD lines804, as is depicted inFIG. 8F.

FIG. 8Gillustrates the structure ofFIG. 8Ffollowing via location selection, in accordance with an embodiment of the present invention. Referring toFIG. 8G, the electrobuckets816A and816C fromFIG. 8Fin select via locations818are removed (i.e., electrobuckets816A and816C are removed). In locations where vias are not selected to be formed, the photoresist816is retained (i.e., electrobucket816B remains after the development process). In one embodiment, the photoresist816of electrobucket816B is retained along with residual portions816′. In one embodiment, electrobucket816B is at least partially exposed during exposure of electrobuckets816A and816C. However, as described above, since the electrobucket816B is not a select via location, the differentiated hardmask approach enables retention of electrobucket516B.

FIG. 8Hillustrates the structure ofFIG. 8Gfollowing conversion of the remaining electrobucket material, e.g., electrobucket816B and, if present, residual photoresist816′, to permanent ILD material820and816″, respectively. Additionally, in an embodiment, the second hardmask portion899is retained in the final structure as well. In an embodiment, the material of the remaining photoresist material is modified, e.g., by cross-linking upon a baking operation, and may be referred to as a cross-linked photolyzable material. In one such embodiment, the final, cross-linked material has inter-dielectric properties and, thus, can be retained in a final metallization structure. In an embodiment, the retained second hardmask portion899is distinct from the retained cross-linked photolyzable material in that a seam or interface is observable in the final structure. However, in other embodiments, the electrobucket material of electrobucket816B is not converted to an ILD material and is instead ultimately removed and replaced with a permanent ILD material. In one such embodiment, the second hardmask portion899is also removed.

Referring again toFIG. 8H, in an embodiment, the resulting structure includes up to three different dielectric material regions (ILD lines804+ILD lines814+cross-linked electrobucket820, in one embodiment) in a single plane850of the metallization structure. In one such embodiment, two or all of ILD lines804, ILD lines814, and cross-linked electrobucket820are composed of a same material. In another such embodiment, ILD lines804, ILD lines814, and cross-linked electrobucket820are all composed of different ILD materials. In either case, in a specific embodiment, a distinction such as a vertical seam between the materials of ILD lines804and ILD lines814(e.g., seam897) and/or between ILD lines804and cross-linked electrobucket820(e.g., seam898) and/or between ILD) lines814and cross-linked electrobucket820(e.g., seam896) may be observed in the final structure.

FIG. 8Iillustrates the structure ofFIG. 8Hfollowing metal line and via formation, in accordance with an embodiment of the present invention. Referring toFIG. 8I, metal lines822and vias824are formed upon metal fill of the openings ofFIG. 8H. The metal lines822are coupled to the underlying metal lines806by the vias824. In an embodiment, the openings are filled in a damascene approach or a bottom-up fill approach to provide the structure shown inFIG. 8I. Thus, the metal (e.g., copper and associated barrier and seed layers) deposition to form metal lines and vias in the above approach may be that typically used for standard back end of line (BEOL) processing. In an embodiment, in subsequent fabrication operations, the ILD lines814may be removed to provide air gaps between the resulting metal lines824.

The structure ofFIG. 8Imay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 8Imay represent the final metal interconnect layer in an integrated circuit. It is to be understood that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. In any case, the resulting structures enable fabrication of vias that are directly centered on underlying metal lines. That is, the vias may be wider than, narrower than, or the same thickness as the underlying metal lines, e.g., due to non-perfect selective etch processing. Nonetheless, in an embodiment, the centers of the vias are directly aligned (match up) with the centers of the metal lines. Furthermore, the ILD used to select which plugs and vias will likely be very different from the primary ILD and will be perfectly self-aligned in both directions. As such, in an embodiment, offset due to conventional lithograph/dual damascene patterning that must otherwise be tolerated, is not a factor for the resulting structures described herein. Referring again toFIG. 5I, then, self-aligned fabrication by the subtractive approach may be complete at this stage. A next layer fabricated in a like manner likely requires initiation of the entire process once again. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

Overall, in accordance with one or more embodiments of the present invention, approaches described herein involve use of electrobucket interlayer dielectric (ILD) to select locations for conductive vias. The details above regardingFIGS. 2A-2O, 6A-6G, 7 and 8A-8Ifocus primarily on electrobuckets used for via patterning. However, it is to be appreciated that electrobuckets including a selective grating approach may also be used for dielectric plug patterning or line end patterning.

In an embodiment, the term “grating structure” or “pitch division” for metal lines, ILD lines or hardmask lines is used to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like patterns described above may have metal lines, ILD lines or hardmask lines spaced at a constant pitch and having a constant width. The pattern may be fabricated by a pitch halving or pitch quartering approach.

In an embodiment, as used throughout the present description, interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In an embodiment, as is also used throughout the present description, interconnect material (e.g., metal lines and/or vias) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including one or more of Ta, TaN, Ti or TiN), stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form interconnect lines. In an embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof. The interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect.

In an embodiment, as is also used throughout the present description, plug and/or cap and/or hardmask materials are composed of dielectric materials different from the interlayer dielectric material. In one embodiment, these materials are sacrificial, while interlayer dielectric materials are preserved at least somewhat in a final structure. In some embodiments, a plug and/or cap and/or hardmask material includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, a plug and/or cap and/or hardmask material includes a metal species. For example, a hardmask or other overlying material may include a layer of a nitride of titanium or another metal (e.g., titanium nitride). Potentially lesser amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other plug and/or cap and/or hardmask material layers known in the arts may be used depending upon the particular implementation. The plug and/or cap and/or hardmask material layers maybe formed by CVD, PVD, or by other deposition methods.

It is to be appreciated that the layers and materials described above are typically formed on or above an underlying semiconductor substrate or structure, such as underlying device layer(s) of an integrated circuit. In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the structures depicted above may be fabricated on underlying lower level back end of line (BEOL) interconnect layers.

FIG. 9illustrates a computing device900in accordance with one implementation of an embodiment of the invention. The computing device900houses a board902. The board902may include a number of components, including but not limited to a processor904and at least one communication chip906. The processor904is physically and electrically coupled to the board902. In some implementations the at least one communication chip906is also physically and electrically coupled to the board902. In further implementations, the communication chip906is part of the processor904.

The processor904of the computing device900includes an integrated circuit die packaged within the processor904. In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more structures, such as conductive vias fabricated using an approach based on electrobuckets having differentiated underlying hardmasks, built in accordance with implementations of embodiments of the invention. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip906also includes an integrated circuit die packaged within the communication chip906. In accordance with another implementation of an embodiments of the invention, the integrated circuit die of the communication chip includes one or more structures, such as conductive vias fabricated using an approach based on electrobuckets having differentiated underlying hardmasks, in accordance with embodiments of the invention.

In further implementations, another component housed within the computing device900may contain an integrated circuit die that includes one or more structures, such as conductive vias fabricated using an approach based on electrobuckets having differentiated underlying hardmasks, in accordance with embodiments of the invention.

FIG. 10illustrates an interposer1000that includes one or more embodiments of the invention. The interposer1000is an intervening substrate used to bridge a first substrate1002to a second substrate1004. The first substrate1002may be, for instance, an integrated circuit die. The second substrate1004may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer1000is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer1000may couple an integrated circuit die to a ball grid array (BGA)1006that can subsequently be coupled to the second substrate1004. In some embodiments, the first and second substrates1002/1004are attached to opposing sides of the interposer1000. In other embodiments, the first and second substrates1002/1004are attached to the same side of the interposer1000. And in further embodiments, three or more substrates are interconnected by way of the interposer1000.

The interposer may include metal interconnects1008and vias1010, including but not limited to through-silicon vias (TSVs)1012. The interposer1000may further include embedded devices1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer1000. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer1000or in one or more of the components of the interposer1000.

Thus, embodiments of the present invention include approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures.

Example embodiment 1: A method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Electrobuckets formed on the first hardmask portions have a different sensitivity to e-beam or extreme ultra-violet (EUV) radiation than electrobuckets formed on the second hardmask portions. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

Example embodiment 2: The method of example embodiment 1, wherein the electrobuckets formed on the first hardmask portions have less sensitivity to the e-beam or EUV radiation than the electrobuckets formed on the second hardmask portions.

Example embodiment 3: The method of example embodiment 1, wherein the electrobuckets formed on the first hardmask portions have greater sensitivity to the e-beam or EUV radiation than the electrobuckets formed on the second hardmask portions.

Example embodiment 4: The method of example embodiment 1, 2 or 3, wherein the electrobuckets formed on the first hardmask portions have different sensitivity to the e-beam or EUV radiation than the electrobuckets formed on the second hardmask portions based on a difference in the extent of backscatter and generation of secondary electrons between the first hardmask portions and the second hardmask portions.

Example embodiment 5: The method of example embodiment 1, 3 or 4, further including etching the set of via locations into the ILD layer. Subsequent to etching the set of via locations into the ILD layer, a plurality of metal lines is formed in the ILD layer, where select ones of the plurality of metal lines include an underlying conductive via corresponding to the set of via locations.

Example embodiment 6: The method of example embodiment 1, 2, 3, 4 or 5, wherein the second hardmask portions are formed by filling pores in a porous dielectric layer with a metal-containing material.

Example embodiment 7: The method of example embodiment 1, 2, 3, 4 or 5, wherein the second hardmask portions are formed by oxidizing a metal-containing material.

Example embodiment 8: The method of example embodiment 1, 2, 3, 4, 5, 6 or 7, wherein the exposing and removing select ones of the plurality of electrobuckets involves removing electrobuckets formed on the second hardmask portions but not removing electrobuckets formed on the first hardmask portions.

Example embodiment 9: The method of example embodiment 1, 2, 4, 5, 6, 7 or 8, wherein one or more of the electrobuckets formed on the first hardmask portions are exposed to the e-beam or EUV radiation but are not removed during the removing of the select ones of the plurality of electrobuckets.

Example embodiment 10: The method of example embodiment 1, 2, 3, 4, 5, 6, 7, 8 or 9, wherein exposing and removing the select ones of the plurality of electrobuckets to define the set of via locations includes removing corresponding second hardmask portions.

Example embodiment 11: The method of example embodiment 10, further including modifying remaining second hardmask portions, forming a second plurality of electrobuckets, exposing and removing select ones of the electrobuckets formed on the first hardmask portions but not removing electrobuckets formed on the modified second hardmask portions to define a second set of via locations.

Example embodiment 12: The method of example embodiment 11, further including etching the set of via locations and the second set of via locations into the ILD layer. Subsequent to etching the set of via locations and the second set of via locations into the ILD layer, a plurality of metal lines is formed in the ILD layer, where select ones of the plurality of metal lines include an underlying conductive via corresponding to the set of via locations and to the second set of via locations.

Example embodiment 13: The method of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein forming the plurality of dielectric spacers involves forming a grating structure using a pitch division processing scheme.

Example embodiment 14: An interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. A region of dielectric material is disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material includes a cross-linked photolyzable material disposed on a distinct underlying hardmask portion.

Example embodiment 15: The interconnect structure of example embodiment 14, wherein the cross-linked photolyzable material is a photo-acid generator (PAG)-based cross-linked photolyzable material.

Example embodiment 16: The interconnect structure of example embodiment 14 or 15, further including a conductive via disposed between and coupling a metal line of the first grating to a metal line of the second grating, the conductive via in the same plane as the region of dielectric material.

Example embodiment 17: The interconnect structure of example embodiment 16, wherein the conductive via has a center directly aligned with a center of the metal line of the first grating and with a center of the metal line of the second grating.

Example embodiment 18: The interconnect structure of example embodiment 14, 15, 16 or 17, wherein the dielectric lines of the first grating include a first dielectric material, and the dielectric lines of the second grating include a second, different dielectric material, and wherein the first and second dielectric materials are different than the cross-linked photolyzable material.

Example embodiment 19: The interconnect structure of example embodiment 14, 15, 16 or 17, wherein the dielectric lines of the first grating and the dielectric lines of the second grating include a same dielectric material different than the cross-linked photolyzable material.

Example embodiment 20: A method of fabricating an interconnect structure for an integrated circuit includes forming a mask above an ILD material layer, the mask having a plurality of spaced apart features each with a central portion and a pair of sidewall spacers. The method also includes forming, using the mask, a first plurality of trenches partially into the ILD material layer. The method also includes forming first hardmask portions and a first plurality of electrobuckets in the first plurality of trenches. The method also includes forming a second mask from the mask by removing the central portion of each feature of the mask. The method also includes forming, using the second mask, a second plurality of trenches partially into the ILD material layer. The method also includes forming second hardmask portions and a second plurality of electrobuckets in the second plurality of trenches, wherein the second plurality of electrobuckets has less sensitivity to e-beam or extreme ultra-violet (EUV) radiation than the first plurality of electrobuckets. The method also includes exposing, developing and removing fewer than all of the first plurality of electrobuckets by using a lithographic exposure. The method also includes forming via locations where the fewer than all of the first electrobuckets were remove& and forming metal vias in the via locations and metal lines above the metal vias.

Example embodiment 21: The method of example embodiment 20, wherein the first plurality of electrobuckets and the second plurality of electrobuckets are formed from a same photoresist material.

Example embodiment 22: The method of example embodiment 20 or 21, wherein the exposing involves at least partially exposing portions of the second plurality of electrobuckets, but the developing and removing does not remove the exposed portions of the second plurality of electrobuckets.

Example embodiment 23: The method of example embodiment 20, 21 or 22, wherein the first hardmask portions have a greater extent of backscatter and generation of secondary electrons than the second hardmask portions.