Single-ended to differential converter

A single-ended to differential converter is presented. The converter may be configured to convert full-swing single-ended signals to low-swing differential signals within a single-stage, thereby reducing signal distortion. The converter may include a passive network of resistive elements, for example resistors and/or metal oxide semiconductor (MOS) devices operating in a linear region. The converter may also allow for adjustable design parameters such as a common mode, differential amplitude, and an output swing. The adjustments may all be made within the single-stage of the converter.

BACKGROUND

In modern high speed mixed signal integrated circuit design, there is often a need to cross signaling domains and go from full-swing single-ended signals to low-swing differential signals. Circuits that act as intermediaries between these domains are known as level converters. Level converters typically include multiple stages as well as a variety of active circuit components.

SUMMARY

In example embodiments, a single-stage converter featuring a passive network of resistive elements is presented. The passive single-stage converter may reduce signal distortion and design complexities associated with prior art converter systems. The single-stage converter, and corresponding method, of example embodiments may include at least one input node configured to receive a full-swing single-ended signal, at least one output node configured to emit a low-swing differential signal, and a single-stage circuit that may be coupled between the at least one input and output nodes. The single-stage circuit may be configured to convert the full-swing single-ended signal to the low-swing differential signal.

The single-stage circuit may feature a fully passive network of a plurality of resistive elements. The resistive elements may include resistors and/or metal oxide semiconductor (MOS) devices operating in a linear region. At least one variable current source may be in connection with the resistive network to further define a common mode of the low-swing differential signal. The at least one variable current source may be a MOS device or a resistor. Characteristics of the low-swing differential signal, for example the common mode, output swing, and differential amplitude, may be defined and/or adjustable via a ratio with respect to at least a portion of the plurality of resistive elements. Furthermore, adjustments to the common mode may be independent of the output swing.

The resistive network may include two receiving resistive elements in connection with the at least one input node, at least one emitting resistive element in connection with the at least one output node, and at least one variable current source for defining the common mode voltage of the low-swing differential signal. The at least one variable current source may be resistor or a MOS device. Furthermore, the receiving and/or emitting resistive elements may be in the form of a bank of resistive elements.

The plurality of resistive elements may include at least one setting resistive element connected to a voltage source. The at least one setting resistive element may be configured to provide a decrease to a common mode of the low-swing differential signal to an amount less than half of a high voltage of the full-swing single-ended signal. Alternatively, the at least one setting resistive element may be configured to provide an increase to the common mode of the low-swing differential signal to at amount greater than half of the high voltage.

DETAILED DESCRIPTION

When signals are transferred from full-swing single-ended circuitry to low-swing differential circuitry, there is often a need to transition signal levels from the single-ended full-swing domain to the low-swing differential domain. This might be the case at the chip-package boundary, where full-swing on-chip signals are to be sent to a board in an LVDS (low swing, differential signaling) fashion. It might also be the case on chip where high speed signals are distributed over long distances on-chip, or in a feedback circuit where the duty cycle of the full-swing signal is to be measured, and may be converted to a differential signal to drive an on-chip differential integrator.

Differential circuits may be, by their nature, designed for input swings that are not full-swing, but some fraction of the full supply range. The low-swing differential signal amplitude and common mode (average) voltage values are key design parameters that are tailored to meet the need of the differential circuit.

FIG. 1provides an overview of mixed signal conversion. Full-swing single-ended circuitry101typically outputs a full-swing signal103and a corresponding inverted signal105. The signals103and105typically range in voltage values from a high voltage value, or Vdd (e.g., the value of the source voltage) to a low voltage value, or 0V (e.g., ground).

FIG. 1also illustrates low-swing differential circuitry107that may input a low-swing signal109and a corresponding inverted signal111. The signals107and109may range in voltage values from Vmax (e.g., a lesser value of the source voltage Vdd) to Vmin (e.g., a corresponding lesser and inverted value of the source voltage Vdd).

As shown by expanded window113, the low-swing signals109and111, as well as full-swing signals103and105, may be defined by a common mode115and a differential amplitude117. The common-mode value115may be defined as the voltage range between ground119and a mid-amplitude value121of the signal. The differential amplitude value117may be defined as the voltage range between the mid-amplitude value121of the signal and a top amplitude value (Vmax)123of the signal.

FIG. 2illustrates an overview of a conversion function that may be provided by a single-ended to differential converter (SE2DC) circuit201, namely, to translate the voltage levels at its input from full-swing single-ended values to a low-swing differential signal, with a pre-determined differential amplitude and common mode voltage. For example, a full-swing single-ended signal203, spanning the entire voltage range from a low voltage supply rail, or ground (0V)202to the high voltage rail providing a source voltage value (Vdd)204, may be input to a node205of the SE2DC201. The corresponding inverse signal207of signal203may also be input to the SE2DC201through input node209. Upon conversion, a node211of the SE2DC201may output a low-swing differential signal213, ranging from voltage values Vmax and Vmin, whose waveform corresponds to the full-swing signal203. Similarly, the SE2DC201may also output the corresponding inverted signal217via an output node215.

It should be noted that prior art converter systems typically include various stages as well as a number of active circuit components. It may be highly desirable for power and area considerations to provide this conversion function using as few stages as possible. It may also be desirable to reduce the number of active circuit elements as they are prone to cause signal distortion. Thus, reducing the number of stages, in addition to the use of passive circuit elements, may aid in the prevention of distorting the differential signal as well as the reduction of overall system complexity. Furthermore, there is also a desire to finely tune the characteristics of the output signal.

FIG. 3Aillustrates an overview of the implementation of a SE2DC circuit300according to example embodiments. The SE2DC300may include input nodes301and303that may be configured to input full-swing single-ended signals305and307, respectively. The input nodes301and303may be electrically connected to inverters302and304, respectively. The signals305and307may be in the range of a high voltage value, Vdd (the value of the voltage source), and a low voltage value, ground (0V), where the signal307is the corresponding inverse signal of signal305. The SE2DC circuit300may further include a pair of matched linear resistive elements E1309and311and a third linear resistive element E2313. Additionally, the SE2DC circuit300may further include a pair of output nodes315and317configured to provide low-swing differential signals319and321respectively. The low-swing differential signals may be in the voltage range of Vmax to Vmin. The low-swing signal321may be the corresponding inverse signal of low-swing signal319.

If ideal voltage sources (e.g., voltage sources including infinite drive strength) are assumed, which may drive full swing and complementary signals into input nodes301and303, then the associated maximum and minimum voltage values (Vmax and Vmin, respectively) that may be provided by the output nodes out315and outb317(out and outb, respectively) may be represented by:

V⁢⁢max⁡(out,outb)=E2+E1E2+2⁢E1⁢Vdd(1)V⁢⁢min⁡(out,outb)=E1E2+2⁢E1⁢Vdd.(2)
The linear resistive element E2may be a scaled version of E1described by a scaling factor defined as:
E2=αE1.  (3)
The input resistance the circuit300may be provided by:
Ein(out, outb)=(2+α)E1,  (4)
and the output resistance of the output nodes out315and outb317may be given by:

Eout⁡(out,outb)=(1+α)(2+α)⁢E1.(5)
Furthermore, by substituting the value of the resistive element E2of equation (3) and factoring the value of the resistive element E1out of equations (1) and (2), the maximum and minimum voltage values, Vmax and Vmin, of the output nodes out315and out b317may be reduced to:

V⁢⁢max⁡(out,outb)=1+α2+α⁢Vdd(6)V⁢⁢min⁡(out,outb)=12+α⁢Vdd.(7)
The common mode voltage value of the output nodes, out315and outb317may therefore be described by:

Vcm_out=(V⁢⁢max⁡(out,outb)+V⁢⁢min⁡(out,outb))/2=Vdd2,(8)
and the output differential signal amplitude may be given by:

Vdiff_out=(V⁢⁢max⁡(out,outb)-V⁢⁢min⁡(out,outb))/2=α2⁢(2+α)⁢Vdd.(9)
Note that both output common mode and differential amplitude voltage values are determined solely by passive circuit elements. The output signal (Vmax and Vmin), the common mode (Vcm_out), and the differential amplitude (Vdiff_out) of equations (6)-(9) depend on the relative matching of resistive elements E1and E2(provided by the scaling factor

Two key output design criteria for a SE2DC are typically signal output swing (Vmax and Vmin) and common mode voltage (Vcm_out). Because the differential stage receiving the output signal from the SE2DC may require specific values of a differential input swing and a common mode input level to operate properly, a desire may exist to precisely tune the characteristics of the SE2DC output signal. Furthermore, metal oxide semiconductor (MOS) differential amplifier stages, which are intended to receive the output SE2DC signal, typically require different common mode (Vcm_out) values depending on an intended operation. For example, a n-type metal oxide semiconductor (NMOS) input amplifier may often be designed to operate with inputs featuring common mode higher than

Vdd2,
while a p-type metal oxide semiconductor (PMOS) input amplifier may be designed to operate with inputs featuring a common mode lower than

In example embodiments, the maximum (Vmax) and minimum (Vmin) values of the SE2DC output signal, may be set by adjusting a resistive ratio value defined by α. Furthermore, the common mode and differential amplitude voltage values may also be finely tuned by adjusting the ratio α between the resistive elements. It should be appreciated that the common mode may be adjusted independently via use of α and Iupor Idownas will be discussed shortly.

FIG. 3Billustrates the possible modifications of Vmax306and Vmin308in terms of percentage values of Vdd (y-axis) in relation to adjustments made to the scaling factor α (x-axis). As described in Equation (6), as the resistive ratio α becomes sufficiently large, the value of Vmax is approximately equal to Vdd. Conversely, as described in Equation (7), as a becomes sufficiently large, the value of Vmin approaches zero.

FIG. 3Cillustrates the possible modifications of Vcm_out310and Vdiff_out312in terms of percentage values of Vdd (y-axis) in relation to adjustments made to the scaling factor α (x-axis). As expected from Equation (8), since the common mode voltage Vcm_out310of the output signal does not depend on the scaling factor α, the command mode Vcm_out will remain constant with respect to changes in α. However, as the scaling factor α increases the differential mode of the output signal Vdiff_out will increase to a maximum value of less than

Vdd2,
as described in Equation (9).

The SE2DC circuit300may also include two pairs of input sources. The first pair of input sources323A and323B may be connected to the high voltage supply Vdd and may provide a current Iup. Adjustments of the current Iupmay increase the common mode voltage to a value greater than

Vdd2⁢⁢(e.g.,Vcm_out=Vdd2+Iup⁢E1).
The second pair of input sources325A and325B may be connected to ground (0V) and may provide a current Idown. Adjustments of the current Idownmay decrease the common mode voltage to a value less than

FIG. 3Dillustrates an alternative SE2DC circuit design327of the SE2DC circuit300ofFIG. 3A. The SE2DC circuit design327features all of the elements of the SE2DC circuit300ofFIG. 3Awith the exception of the linear resistive elements E1309and311and E2313. The SE2DC design327instead may include linear programmable resistive elements that may be altered at anytime prior or during operation. Specifically, the matched linear resistive elements E1309and311may be replaced by a bank of programmable linear resistive elements329and331, where each bank of programmable elements may include a number of linear resistive elements numbered E1—0-E1—N. The linear resistive element E2may be replaced by a similar bank of resistive elements333numbered E2—0-E2—N.

Note that each resistive element in the programmable bank includes a switching element connected serially to a respectively resistive element. For example, the resistive element332of bank331is serially connected to switch334. If there is a desire to change the differential swing and/or common mode voltage during operation (e.g., on-the-fly adjustments), opening and closing the switches will modify the values of the overall resistance of the elements329,331, and333, thereby providing the desired adjustment. A possible modification to the circuit327is replace the switching elements with MOS switches (e.g., MOS devices operating as small resistors when “on” and open circuits when “off”).

FIG. 4Aillustrates yet another alternative SE2DC design335of the SE2DC circuit300ofFIG. 3A. The SE2DC design335ofFIG. 4Aincludes all of the elements of the SE2DC circuit300ofFIG. 3Awith the exception that the linear resistive element E2313is replaced with two linear resistive elements

E22⁢⁢337
and339in parallel. Additionally, the first pair of current sources323A and323B ofFIG. 3Ais replaced by a single current source341providing a current 2Iup, which may be used to increase the common mode voltage to a value greater than

Vdd2⁢⁢(e.g.,Vcm_out=Vdd2+Iup⁢E1).
The second pair of current sources325A and325B is also replaced by a single current source343providing a current 2Idown, which may be used to decrease the common mode voltage to a value less than

FIG. 4Billustrates an alternative SE2DC design345of the SE2DC circuit335ofFIG. 4A. The SE2DC design ofFIG. 4Bincludes all of the elements of the SE2DC circuit335ofFIG. 4Awith the exception that the matched linear resistive elements E1309and311ofFIG. 4Ais replaced with the matched programmable resistive bank329and331featuring linear resistive elements numbered E1—0-E1—N. Similarly, the parallel linear resistive elements337and339may also be replaced by two parallel banks of resistive elements347and349featuring elements numbered

E2⁢_⁢0-E2⁢_N2.
By adjusting the resistive values, the differential mode may be altered.

It should be appreciated that the linear resistive elements E1and E2may be in the form of any known circuit element capable of providing a resistance, for example a resistor or a metal oxide semiconductor field effect transistor (MOSFET). Regardless of whether the resistive elements are MOS based or resistor based, there are well known current generation techniques (e.g., replica biasing) in the art to create accurate currents Iupor Idownthat are largely process, voltage, and temperature immune. The current generation may also be able to track varying conditions in the resistive elements. Furthermore, these well know techniques may use replicas of the resistive elements and drop a stable and known voltage across the elements. Variations in the resistive elements are therefore tracked over varying environmental conditions.

It should also be appreciated that the output common mode of the SE2DC may be tailored to fit the desired value for driving the differential stage to follow by changing the magnitude and polarity of the current (Iupor Idown) used to set the common mode voltage. The flexibility afforded by this approach lends itself for use in feedback circuits that may be used to optimize the common mode output of a differential stage that drives another differential stage. This can be accomplished by using variable current sources.

It should further be appreciated that the implementations of the current sources employed in altering the common mode voltage Vcm_out may minimally change the output and input resistance of the SE2DC as described in Equations (4) and (5). However, the differential output swing may remain unaffected by the addition of the current sources.

FIG. 5Aillustrates a SE2DC circuit design500similar to the SE2DC design300ofFIG. 3Awhere the linear resistive elements E1and E2are replaced with PMOS elements M1501and503, and M2505. The resistive PMOS elements M1501and503, and M2505are configured to operate in their respective linear regions (e.g., the drain to source voltages of the PMOS elements M1and M2are less than their respective gate voltage minus a threshold voltage). A PMOS operating in the linear region is the functional equivalent of a resistor. Thus, in the linear region, a PMOS is a passive device. While operating in the linear region, the current provided by a MOS device may be expressed by:

Ids=μcox⁢WL⁢(Vgs-Vth-Vds2)⁢Vds2(10)
where Idsis the current emitted from the drain to source terminals of the MOS device, W is the channel width, L is the channel length, Vgsis the voltage applied to the gate terminal, Vdsrepresents the voltage across the drain and source terminals, and Vthis the threshold voltage associated with a particular MOS device. The MOS current Idsis also dependent on a coefficient μcoxwhich is a function of the mobility of carriers in the MOS channel, the dielectric constant of the gate oxide, and the thickness of the oxide. Assuming that

Vgs-Vth⪢Vds2,
Equation (10) may be reduced to:

Ids≈μcox⁢WL⁢(Vgs-Vth)⁢Vds2.(11)
As previously mentioned, when operating in the linear region (e.g., Vds<Vgs−Vth), the MOS device may function as a resistor. The value of the MOS resistance may be provided by:

Rds≈2μcox⁢WL⁢(Vgs-Vth).(12)
Utilizing the MOS resistor definition provided above, the maximum, minimum, common mode, and differential mode of the output signal may be found using Equations (6)-(9), respectively.

The first pair of current sources323A-323B, as illustrated inFIG. 3A, may also be replaced with PMOS elements in the converter ofFIG. 5A, while the second pair of current sources325A-325B may be replaced with NMOS elements. If it is desired to modulate the common mode voltage to a value greater than

Vdd2⁢(e.g.,Vcm_out=Vdd2+Iup⁢E1)
the first current source pair of PMOS elements511A and511B may be used. If it is desired to modulate the common mode voltage to a value less than

Vdd2⁢(e.g.,Vcm_out=Vdd2-Idown⁢E1),
the second source pair of NMOS elements513A and513B may be used. The amount of modulation in the common mode voltage introduced via the first and second current source pair may be adjusted by controlling the voltages Vbp and Vbn that are supplied to the gates of the first and second current source pair elements, respectively.

An on-the-fly implementation of the circuit shown inFIG. 5Amay be provided by using a bank of PMOS devices in the place of PMOS elements M1and M2, as described inFIG. 3B. The gate of each PMOS device in the bank may be individually controlled in order to place the respective device in an off or on state. Furthermore, by modulating the voltage supplied to the gate of each PMOS device, the value of the current provided by each individual device may be controlled. Having control of the individual devices allows for precise tuning of the bank. Thus, the bank of PMOS devices will not require the use of a switch connected in series with the device (e.g., switch334).

E22
are also replaced with PMOS elements M1501and503, and

M22
507and509are also configured to operate in their respective linear regions (e.g., Vds<Vgs−Vth). Thus, PMOS devices M1and

FIGS. 6A and 6Billustrate an example of an input signal and an output signal, respectively, that may be obtained using the SE2DC circuits ofFIG. 5Aor5B. Both the input and output signals ofFIGS. 6A and 6B, respectively, are graphically depicted in terms of voltage (y-axis) and time (x-axis). The single-ended input signals include two inverse components V(in)601and V(inb)603having a single-ended swings ranging from 0V (ground) to 1.2V (Vdd). The resulting differential output signal also includes two inverse components V(out)605and V(outb)607having a differential swing ranging from 0.4V (Vmin) to 0.8V (Vmax). The common mode voltage609is also plotted inFIG. 6B. Note that the common mode voltage609is approximately 0.6V which is equal to half of the source voltage Vdd. The differential mode voltage (DM) has a value of 0.2V. The common mode and differential mode voltage values are expected as described in Equations (8) and (9), thus adjustments to current sources or resistive ratios have not been applied to modify the output signal. Also note that the scaling factor α is equal to 1 since the resistive elements are matched.

FIG. 7illustrates a SE2DC circuit design700similar to the SE2DC design300ofFIG. 3Awhere the linear resistive elements E1and E2are replaced with resistors R1709and711, and R2713. The operation of the fully passive SE2DC circuit700may also be described by Equations (6)-(9). It should be noted that while absolute values of on-chip resistors are typically only specified to be within a +/−20% deviation of a nominal value, matching between resistors is typically better than 1%. Therefore, both the common mode voltage Vcm_out and differential voltage Vdiff_out may be precisely tuned by adjusting the scaling factor α.

FIGS. 8A and 8Billustrate an example of an input signal and an output signal, respectively, that may be obtained using the SE2DC circuit ofFIG. 7. Both the input and output signals ofFIGS. 8A and 8B, respectively, are graphically depicted in terms of voltage (y-axis) and time (x-axis). Similarly to the example provided inFIGS. 6A and 6B, the single-ended input signal includes two inverse components V(in)801and V(inb)803having a single-ended swing ranging from 0V (ground) to 1.2V (Vdd). The resulting differential output signal also includes two inverse components V(out)805and V(outb)807having a differential swing ranging from 0.4V (Vmin) to 0.8V (Vmax). The common mode voltage809is also plotted inFIG. 8Band is approximately 0.6V which is equal to half of the source voltage Vdd. The differential mode voltage (DM) has a value of 0.2V. Thus, the example ofFIG. 8Billustrates that the resistor embodiment ofFIG. 7and the MOS embodiment ofFIGS. 5A and 5Bmay provide similar results. Note that the results ofFIG. 8Bare provided with the scaling factor being set to α=1, therefore the values of R1=R2. The values of the common mode voltage Vcm_out and the differential Vdiff_out are the expected results according to equations (6)-(9).

FIGS. 9A-9Dillustrate resistor embodiments of the circuits illustrated inFIGS. 3A and 4A. In the SE2DC resistor circuit ofFIG. 9A, the current source pair of current sources323A and323B may be used to raise the common mode voltage Vcm_out to a value greater than

Vdd2
by an amount IupE1. The SE2DC resistor circuit ofFIG. 9Cmay also be used to raise the common mode voltage Vcm_out by an amount IupE1with the use of a single current source323and by replacing the single resistor R2713with two resistors

R22
737and739. The SE2DC resistor circuit illustrated inFIG. 9Bincludes a current source pair of current325A and325B that may be used to decrease the common mode voltage Vcm_out to a value less than

Vdd2
by an amount IdownE1. The SE2DC resistor circuit ofFIG. 9Dmay also be used to lower the common mode voltage Vcm_out by an amount IdownE1with the use of a single current source325and also by replacing the single resistor R2713with two resistors

FIG. 10illustrates the SE2DC circuit design ofFIG. 3Afeaturing linear resister elements R1709and711, and R2713. The circuit1000illustrated inFIG. 10also features a first and second current source pair911A-911B and913A-913B including PMOS and NMOS transistors, respectively. The first current source pair911A and911B may be used to increase the common mode voltage of the output signal Vcm_out by and amount IupE1. The second current source pair913A and913B may be used to decrease the common mode voltage of the output signal Vcm_out by an amount IdownE1.

FIGS. 11A and 11Billustrate an example of an input signal and an output signal, respectively, that may be obtained using the SE2DC circuit ofFIG. 9A,9C or10. Both the input and output signals ofFIGS. 11A and 11B, respectively, are graphically depicted in terms of voltage (y-axis) and time (x-axis). The single-ended input signal includes two inverse components V(in)1101and V(inb)1103having a single-ended swing ranging from 0V (ground) to 1.2V (Vdd). The resulting differential output signal, described by equations (6)-(9), also includes two inverse components V(out)1105and V(outb)1107having a differential swing ranging from 0.7V (Vmin) to 1.1V (Vmax). The common mode voltage1109is also plotted inFIG. 11Band is approximately 0.9V which is greater than half of the source voltage Vdd. Thus, in order to obtain the output signal illustrated inFIG. 11B, a current source may have been utilized to shift the common mode voltage without changing the differential mode voltage. The differential mode voltage (DM) has a value of 0.2V. Note that the results ofFIG. 11Bare provided with the scaling factor being set to α=1, therefore the values of R1=R2.

FIGS. 12A and 12Billustrate an example of an input signal and an output signal, respectively, that may be obtained using the SE2DC circuit ofFIG. 9B,9D or10. Both the input and output signals ofFIGS. 12A and 12B, respectively, are graphically depicted in terms of voltage (y-axis) and time (x-axis). The single-ended input signal includes two inverse components V(in)1201and V(inb)1203having a single-ended swing ranging from 0V (ground) to 1.2V (Vdd). The resulting differential output signal, described by equations (6)-(9), also includes two inverse components V(out)1205and V(outb)1207having a differential swing ranging from 0.1V (Vmin) to 0.5V (Vmax). The common mode voltage1209is also plotted inFIG. 12Band is approximately 0.3V which is less than half of the source voltage Vdd. Thus, in order to obtain the output signal illustrated inFIG. 12B, a current source was utilized to shift the common mode voltage, without changing the differential mode voltage. The differential mode voltage (DM) has a value of 0.2V. Note that the results ofFIG. 12Bare also provided with the scaling factor being set to α=1, therefore the values of R1=R2.

FIGS. 13A and 13Billustrate a fully resistive SE2DC system according to example embodiments. The fully resistive SE2DC circuit1300ofFIG. 13Ais similar in design to the SE2DC circuits ofFIGS. 9A and 9Bwith the exception that the current sources323A-323B and325A-325B have been replaced with two resistors R3723A-723B. Depending on the value of the input resistor voltage Vb, the resistors R3723A-723B may provide a current that may be used to either lower, increase, or stabilize the common mode voltage Vcm_out in a similar manner as described inFIGS. 9A and 9B.

FIG. 13Billustrates a fully resistive SE2DC circuit1301that is similar in design to the SE2DC circuits ofFIGS. 9C and 9Dwith the exception that the current sources323and325have been replaced with a single resistor R3723. Similarly to the circuit design illustrated inFIG. 13A, the value of the input resistor voltage Vb may be used to provide a current that may either lower, increase, or stabilize the common mode voltage Vcm_out in a similar manner as described inFIGS. 9C and 9D.

The presence of the additional resistor R3may alter output swing, differential mode, and common mode of the low-swing differential output signal. The maximum voltage value of the output swing Vmax may be provided by:

V⁢⁢max⁡(out,outb)=R3⁢⁡[R2+(R1⁢⁢R3)]R3⁢⁡[R2+(R1⁢⁢R3)]+R1⁢Vdd+R1⁢⁡[R2+(R1⁢⁢R3)]R1⁢⁡[R2+(R1⁢⁢R3)]+R3⁢(1+R1⁢⁢R3(R1⁢⁢R3)+R2)⁢Vb.(13)
The minimum voltage value of the output swing Vmin may be provided by:

V⁢⁢min⁡(out,outb)=(R3⁢⁡[R2+(R1⁢⁢R3)]R3⁢⁡[R2+(R1⁢⁢R3)]+R1)⁢(R1⁢⁢R3(R1⁢⁢R3)+R2)⁢Vdd+R1⁢⁡[R2+(R1⁢⁢R3)]R1⁢⁡[R2+(R1⁢⁢R3)]+R3⁢(1+R1⁢⁢R3(R1⁢⁢R3)+R2)⁢Vb(14)
The common mode voltage Vcm_out and the differential mode Vdiff_out may also be provided by:

FIGS. 14A and 14Billustrate an example of an input signal and an output signal, respectively, that may be obtained using the SE2DC circuit ofFIG. 13Aor13B. Both the input and output signals ofFIGS. 14A and 14B, respectively, are graphically depicted in terms of voltage (y-axis) and time (x-axis). The single-ended input signal includes two inverse components V(in)1401and V(inb)1403having a single-ended swing ranging from 0V (ground) to 1.2V (Vdd). The resulting differential output signal, which may be described by equations (13)-(16), also includes two inverse components V(out)1405and V(outb)1407having a differential swing ranging from 0.75V (Vmin) to 1.05V (Vmax). The common mode voltage1409is also plotted inFIG. 14Band is approximately 0.9V which is greater than half of the source voltage Vdd. The differential mode voltage (DM) has a value of 0.15V. Note that the results ofFIG. 14Bare also provided with an matched resistance therefore R1=R2=R3.

FIGS. 15A and 15Billustrate another example of an input signal and an output signal, respectively, that may be obtained using the SE2DC circuit ofFIG. 13Aor13B. Both the input and output signals ofFIGS. 15A and 15B, respectively, are graphically depicted in terms of voltage (y-axis) and time (x-axis). The single-ended input signal includes two inverse components V(in)1501and V(inb)1503having a differential swing ranging from 0V (ground) to 1.2V (Vdd). The resulting differential output signal, which may be described by equations (13)-(16), also includes two inverse components V(out)1505and V(outb)1507having a differential swing ranging from 0.15V (Vmin) to 0.45V (Vmax). The common mode voltage1509is also plotted inFIG. 15Band is approximately 0.3V which is less than half of the source voltage Vdd. The differential mode voltage (DM) has a value of 0.15V. Note that the results ofFIG. 15Bare also provided with an matched resistance therefore R1=R2=R3.

It should be appreciated that the inverters302and304ofFIGS. 3A,3D,4A,4B,7,9A-9D, and/or10may be modeled as MOS switches as illustrated inFIG. 16. Both inverters302and304may be modeled as a pair of MOS devices, including a PMOS1305and an NMOS1307transistor device. When either inverter302or304pulls down towards ground (0V), the NMOS1307output resistance may be model as a resistor Roncontrolled via a switch. Similarly, when either inverter302or304is pulling up towards Vdd, the PMOS1305linear resistance may also be modeled as a resistor Roncontrolled via a switch.FIG. 16illustrates the inverter302being modeled by a resistor Ron1301controlled via a switch1302and the inverter304being modeled by a resistor Ron1303controlled via a switch1304. The resistive values of the PMOS1305and NMOS1307may be scaled by altering the width and lengths of the MOS devices.

FIG. 17illustrates the SE2DC circuit ofFIG. 7featuring the modeled resistance Ron1301and1303in the place of inverters302and304, respectively. For simplicity, switches1302and1304have been omitted fromFIG. 17. Furthermore, it is assumed that the PMOS1305and NMOS1307devices have been dimensioned to provide the same resistance value of Ron. Recalculating the relevant voltages, the output voltage may be defined by:

V⁢⁢max⁡(out,outb)=(1+α)⁢R1+Ron(2+α)⁢R1+2⁢Ron⁢Vdd(17)V⁢⁢min⁡(out,outb)=R1+Ron(2+α)⁢R1+2⁢Ron⁢Vdd.(18)
The common mode output voltage Vcm_out and the differential mode Vdiff may be defined as:

As the resistive value of Ron1301and1302is made small relative to R1709and R2711, the error that may be introduced by a driver in regards to resistance may be correspondingly small. For example, if α≧1, and R1≧10·Ron, the error introduced by a finite Ronmay be less than 3.5%. Larger values of α and R1/Ronmay reduce the error further.

Various embodiments of a SE2DC featuring a passive network of resistive elements has been discussed. An advantage of the various SE2DC embodiments discussed is that the entire SE2DC may be included in a single stage, thereby reducing the complexity and overall cost of the device. Furthermore, the various embodiments discussed allow for precise adjustments of the common and differential mode output voltages.

Another advantage of the various embodiments is that the output swing and common mode of the described devices may not be altered in the presence of high resistance MOS differential input stages. MOS differential input stages are typically used in integrated circuit design, and may be represented as a typical load for the SE2DC. Because the SE2DC embodiments are constructed based on a resistive element network, resistive loading at the output could potentially alter the desired values of the output swing and common mode. However, because the high resistance MOS input stages are presented as loads, there minimal impact of the differential stage on the SE2DC outputs. Even in fine feature size modern nodes that exhibit MOS gate leakage, the leakage values for typical differential amplifier gates, of the MOS input stage, will be very small compared to the active current through the resistor network included in the various SE2DC embodiments. Therefore, by taking advantage of the inherent high input impedance present in differential stages of the MOS input, a single stage, low distortion, well-matched, linear resistive network may be provided as an equivalent circuit.

A further advantage of the various SE2DC embodiments that include resistors as the resistive elements is that the resistive network of the SE2DC may be unaffected by the high input impedances of typical MOS input stages. Specifically, these single-ended to differential converter circuits are capable of achieving process and temperature independent output common modes and differential amplitudes in a single stage.