Pattern generation circuit, multi-path detection circuit employing the same and multi-path detection method

A multi-path detection circuit can improve path detection accuracy in the environment where the path is located close in the extent of one chip in the multi-path detection circuit of CDMA type receiver unit. The multi-path detection circuit has generating means for generating a logic pattern of a correlated peak in the delay profile, and removing means for removing a power component of the detected correlated peak from the delay profile using the logical pattern of the correlated peak generated by the generating means.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a pattern generation circuit, a multi-path detection circuit employing the same and a multi-path detection method. More particularly, the invention relates to a detection method of a multi-path position for determining a reception timing of a finger of a RAKE receiver employed in a code division multiple access (CDMA) system (spread spectrum system).

2. Description of the Related Art

Conventionally, as a path timing detection circuit of this kind, there is a circuit to be realized by measuring a delay profile of a propagation path by correlating operation of a reception signal and a spread code using a sliding correlator or matched filter and by detecting a correlation peak amount of the delay profile.

However, when intervals of respective multi-path is narrow, a plurality of paths can overlap on the delay profile to make it difficult to detect correct path position.

For example, in an example of the delay profile shown inFIGS. 5A to 5C, when only one path is present, a shape of the path has a width as illustrated inFIG. 5A. On the other hand, when a plurality of paths are present, if paths have enough interval as shown inFIG. 5B, a plurality of paths can be identified.

However, when interval of the paths is small as shown inFIG. 5C, paths cause overlap to make it impossible to identify which sample point is the accurate path position. When the path position cannot be detected accurately, reception performance is degraded significantly.

In such case, in the prior art, it has been employed a method to set a minimum interval of respective finger position by omitting N samples (N is integer) before and after the detected path from next peak detection. Such method has been disclosed in “Path-Search Performance of DS-CDMA System in Laboratory and Field Experiments” (Aoyama et al.: Technical Report of IEICE, ROS 97–164, 1997–11) (hereinafter referred to as publication 1).

However, in the foregoing method, it is required to preliminarily determine the minimum interval of the paths to detect. Also, in the foregoing method, the detected path position may be determined depending upon the set value to cause difficulty in detecting accurate timing.

Namely, in the foregoing publication 1, when the interval between the paths is narrow to overlap the paths, the N samples before and after the detected path are masked to omit from next peak detection, pseudo peak may appear in the pattern from which the N samples before and after the detected path are omitted, to cause difficult in detection of the accurate timing.

SUMMARY OF THE INVENTION

The present invention has been worked out in view of the problems set forth above. It is therefore an object of the present invention to provide a pattern generation circuit which can enhance precision in detection of each path timing and thus can obtain more stable reception performance, a multi-path detection circuit and a multi-path detection method employing the same.

According to the first aspect of the present invention, a pattern generating circuit comprises:

generating means for generating a logical pattern of correlated peak in a delay profile of a transmission path; and

removing means for removing a power component of the detected correlated peak from the delay profile using the logical pattern of the correlated peak generated by the generating means.

According to the second aspect of the present invention, a multi-path detection circuit for detecting a timing of multi-path by measuring a delay profile of a transmission path, comprises

generating means for generating a logic pattern of a correlated peak in the delay profile; and

detection means for detecting position of the correlated peak on the basis of the logical pattern of the correlated peak generated by the generating means.

According to the third aspect of the present invention, a multi-path detection circuit comprises:

a matched filter outputting a correlated value of a spread code and a received signal;

delay profile storing means for storing a delay profile of a transmission path measured by the matched filter;

maximum value retrieving means for retrieving a maximum peak position and a peak level from the delay profile stored in the delay profile storing means;

pattern generating means for sequentially generating logical patterns of correlated peaks on the basis of the leak level and peak position obtained from the maximum value retrieving means; and

preparing means for preparing a profile removed a correlation power of the peak retrieved at preceding time by the maximum value retrieving means;

the maximum peak value and the peak level being retrieve sequentially from the profile generated by the generating means.

According the forth aspect of the invention, a multi-path detection method for detecting a timing of multi-path by measuring a delay profile of a transmission path, comprises the steps of:

generating a logical pattern of a correlated peak in a delay profile; and

detecting a position of correlated peak on the basis of the generated logical pattern of the correlated peak.

Namely, the multi-path detection circuit according to the present invention is to improve path detection accuracy in the environment where the path is located close in the extent of one chip in the multi-path detection circuit of CDMA type receiver unit.

Therefore, a multi-path detection circuit has generating means for generating a logic pattern of a correlated peak in the delay profile, and removing means for removing a power component of the detected correlated peak from the delay profile using the logical pattern of the correlated peak generated by the generating means.

More particularly, the multi-path detection circuit according to the present invention, has a matched filter outputting a correlated value of a spread code and a received signal, delay profile storing means for storing a delay profile of a transmission path measured by the matched filter, maximum value retrieving means for retrieving a maximum peak position and a peak level of the first correlated peak from the delay profile stored in the delay profile storing means, pattern generating means for generating logical patterns (logical shape) of the first correlated peak on the basis of the leak level and peak position of the first correlated peak obtained from the maximum value retrieving means, and a substractor substracts the logical pattern of the first correlated peak from the delay profile data stored in the delay profile storage portion upon detecting the second correlated peak.

With raking the construction set forth above, a profile removed the correlated power of the first correlated peak is prepared by the substractor upon detecting the second correlated peak to store in the delay profile storage portion. Subsequently, the maximum value retrieving portion outputs the maximum peak position and the peak level to obtain the peak level and the peak position of the second correlated peak. The pattern generating portion generates the logical pattern of the second correlated peak on the basis of the peak level and the peak position of the second correlated peak.

The substractor subtracts the logical pattern of the second correlated peak from the delay profile data stored in the delay profile storage portion to generate a profile removed the correlated power of the second correlated peak to store. The foregoing operation is counted by the counter to repeat for a predetermined number to retrieve a plurality of correlated peak.

Accordingly, even when the interval of the correlated peaks (path) is narrow to cause overlap on the delay profile, the multi-path can be precisely separated into each individual path to enable detection of the correlated peak position to improve reception performance.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1is a block diagram showing a construction of one embodiment of a multi-path detection circuit according to the present invention. As shown inFIG. 1, the shown embodiment of the multi-path detection circuit1is constructed with a matched filter11, a delay profile storage portion12, a maximum value retrieving portion13, a pattern generating portion14, a subtractor15and a counter16.

The multi-path detection circuit1has the matched filter11outputting a correlation value of a spread code and a received signal. A delay profile of a propagation path (not shown) measured by the matched filter11is fed to the delay profile storage portion12to be stored therein.

A first correlated peak (path) can be obtained by outputting a maximum peak position and a peak level from the delay profile by the maximum value retrieving portion13. The pattern generating portion14generates a logical pattern of the first correlated peak on the basis of the peak level and the peak position of the first peak obtained from the maximum value retrieving portion13.

Upon detecting the second correlated peak, the subtractor15subtracts the logical pattern of the first correlated peak from the delay profile data in the delay profile storage portion12to prepare a profile from which is removed a correlated power of the first correlated peak and stores the prepared profile in the delay profile storage portion12. It should be noted that the subtractor15may be replaced with other means, such as shift register or the like as long as the profile from which is removed the correlated power of the first correlated peak can be generated.

Thereafter, the maximum value retrieving portion13outputs the maximum peak position and the peak level to obtain the peak level and the peak position of the second correlated peak. The pattern generating portion14generates the logical pattern (logical shape) of the second correlated peak on the basis of the peak level and the peak position of the second correlated peak.

The subtractor15subtracts the logical pattern of the second correlated peak from the delay profile data stored in the delay profile storage portion12to prepare the profile from which is removed the correlated power of the second correlated peak. Then, the prepared profile is stored in the delay profile storage portion12.

By repeating the foregoing operation for number of times to be measured by the counter16, a plurality of correlated peak can be retrieved. Accordingly, even if the multi-path having narrow interval between adjacent correlated peaks to cause overlapping on the delay profile, the multi-paths can be separated into respective of the correlated peaks with high precision to enable detection of the correlated peak position. Thus, reception performance can be improved.

FIG. 2is a block diagram showing one embodiment of the CDMA receiver according to the present invention. InFIG. 2, one embodiment of the CDMA receiver according to the present invention is constructed with an antenna portion2, a high frequency reception circuit portion (radio portion)3, an analog-to-digital (A/D) converter4, a RAKE finger portion5, a RAKE synthesizing portion6and the multi-path detection circuit1. The multi-path detection circuit1has the construction as shown inFIG. 1. The high frequency reception circuit portion3is provided with a channel filter3ato be used for band restriction with a not shown base station.

The data transmitted as radio wave is received by the antenna portion2, then is subjected to frequency conversion (down conversion) by the high frequency reception circuit portion3and is converted from the analog signal into digital signal by the A/D converter4.

The signal from the A/D converter4is supplied to the multi-path detection circuit1for measuring the delay profile of a transmission path and timing of the multi-path is detected. The output of the multi-path detection circuit1is used as a reception timing input of the RAKE finger portion5. Data received at respective timing are synthesized by the RAKE Synthesizing portion6.

The multi-path detection circuit1has the matched filter11outputting the correlated value of the spread code and the received signal. By this, the measured delay profile of the transmission path is stored in the delay profile storage portion12.

The first correlated peak (path) can be obtained by outputting a maximum peak position and a peak level from the delay profile by the maximum value retrieving portion13. The pattern generating portion14generates a logical pattern of the correlated peak on the basis of the peak level and the peak position of the first correlated peak obtained from the maximum value retrieving portion13. At this time,the reference pattern (peak shape of one path of the peak level1) used in the logical pattern of the correlated peak can be arithmetically derived on the basis of a coefficient used in the channel filter3a. From the reference pattern, the logical pattern of the correlated peak is generated on the basis of the peak level and the peak position of the correlated peak.

Upon detecting the second correlated peak, the subtractor15subtracts the logical pattern of the first correlated peak from the delay profile data in the delay profile storage portion12to prepare a profile from which is removed a correlated power of the first correlated peak and stores the prepared profile in the delay profile storage portion12.

Thereafter, the maximum value retrieving portion13outputs the maximum peak position and the peak level to obtain the peak level and the peak position of the second correlated peak. The pattern generating portion14generates the logical pattern of the second correlated peak on the basis of the peak level and the peak position of the second correlated peak.

The subtractor15subtracts the logical pattern of the second correlated peak from the delay profile data stored in the delay profile storage portion12to prepare the profile from which is removed the correlated power of the second correlated peak. Then, the prepared profile is stored in the delay profile storage portion12. By repeating the foregoing operation for number of times, a plurality of correlated peak can be retrieved. It should be noted that the number of times is measured by the counter16.

FIG. 3is a block diagram showing a construction of the maximum value retrieving portion13ofFIG. 1. InFIG. 3, the maximum value retrieving portion13is constructed with a level comparing portion13a, a selector13b, a buffer portion(D)13cand a maximum position storage portion13d.

The level comparing portion3acompares the samples of the delay profile data with the interim maximum value in the retrieved samples. The selector13bselects the same sample of the delay profile data or the interim maximum value depending upon the result of compariseon of the level comparing portion3a.

The buffer portion13cholds an interim maximum value during maximum value retrieval. The maximum position storage portion13dholds a sample position when the level comparing portion13adetects new maximum value to output the maximum peak position. In the construction set forth above, all samples of the delay profile data are retrieved sequentially. At the end of search, the maximum value among all samples is stored in the buffer portion13c.

FIG. 4is a block diagram showing a construction of the pattern generating portion14ofFIG. 1. InFIG. 4, the pattern generating portion14is constructed with a logical pattern memory14a, a multiplier14band a peak position setting portion14c.

The logical pattern memory14aholds a preliminarily set reference pattern. The multiplier14bsets a peak level using the reference pattern stored in the logical pattern memory14a. The peak position setting portion14csets the position of the correlated peak from a peak position input and a peak shape output (logical pattern) from the multiplier14b. The multiplier14bmay be any other means, such as adder or the like as long as the peak level can be set using the reference pattern.

The logical pattern memory14amay be realized by storing the reference pattern indicative of the logical pattern of the correlated peak [the peak shape upon one path as shown inFIG. 7A] as set at peak level1in read-only-memory (ROM) or the like.

By removing the power of the detected peak obtained by the pattern generating portion14, detection of the next correlated peak becomes possible. A timing information of the multi-path thus obtained is supplied to the RAKE finger portion5.

With the construction set forth above, as shown inFIG. 5C, even in multi-path environment where the path interval is narrow to cause overlap of the delay profile, the correlated peak position can be detected with high precision to improve reception performance.

It should be noted that the matched filter11is well known to those skilled in the art as means for measuring the delay profile. Therefore, detailed description therefor will be omitted for keeping the disclosure simple enough to facilitate clear understanding of the present invention. It should be noted that a sliding correlator may also be employed in place of the matched filter11. Similarly, the RAKE finger portion5and the RAKE synthesizing portion6are well known to those skilled in the art, and are not directly related to the present invention. Therefore, detailed description therefor will be omitted for keeping the disclosure simple enough to facilitate clear understanding of the present invention.

FIGS. 5A to 5Care illustration showing examples of the delay profiles.FIG. 5Ashows the delay profile in case of one path.FIG. 5Bshows the delay profile in the case where interval between three paths is relatively wide.FIG. 5cshows the delay profile in the case where interval between three paths is narrow.

FIG. 6is a flowchart showing operation of the multi-path detection circuit1ofFIG. 1, andFIGS. 7A to 7Care illustration showing operation images of respective process for the delay profile data stored in the delay profile storage portion12. It should be noted that the operation shown inFIG. 6is realized by executing a program of a not shown control memory by the multi-path detection circuit1. As the control memory, ROM, integrated circuit (IC) memory and so forth may be used.

With reference toFIGS. 1 to 7C, operation of one embodiment of the present invention will be discussed. Here, discussion will be given for the case where the path interval is narrow and delay profiles of a plurality of correlated peaks overlap as shown inFIG. 5C.

FIG. 5Ashows an example of the correlated peak in the case where only one path is present and only one correlated peak is present. The shape of the correlated peak has a width by a reception filter characteristics.

FIG. 5Bshows an example of the delay profile in which three correlated peaks are present with interval about two chips. When the correlated peaks have sufficient interval as shown, presence of the three correlated peaks is definite.

FIG. 5Cshows an example of the case in which three correlated peaks are present with interval about one chip. Since respective paths overlap to make respective peak position indefinite. Therefore, accurate detection of the position of the correlated peak is difficult in the conventional method.

Next, discussion will be given for operation of the multi-path detection circuit1. In the multi-path detection circuit1, at first, the counter16counting number of detected peaks is reset (step S1ofFIG. 6). Subsequently, in the multi-path detection circuit1, the delay profile is measured by the matched filter11(step S2ofFIG. 6). An example of the delay profile measured by the matched filter11is shown inFIG. 7A.

Thereafter, maximum value retrieval is performed by the maximum value retrieving portion13(step S3ofFIG. 6). The maximum value retrieving portion13outputs the detected path timing (correlated peak position) to the RAKE finger portion5(step S4ofFIG. 6). The pattern generating portion14generates the logical pattern [seeFIG. 7B] of the detected peak on the basis of the maximum value and the peak position information detected by the maximum value retrieving portion13(step S5ofFIG. 6).

The subtractor15subtracts the logical pattern generated by the pattern generating portion14from the delay profile data [seeFIG. 7c] to remove the power component of the detected peak from the delay profile data (step S6ofFIG. 6).

The delay profile storage portion12stores data removed the power component of the detected peak from the delay profile data by the subtractor15(step S7ofFIG. 6). After completion of this process, the counter16is counted up (step S8ofFIG. 6). By repeating the foregoing process for the times corresponding to number of fingers (step S9ofFIG. 9), necessary number of peaks can be detected.

As set forth above, even in the multi-path environment where the correlated peaks of the delay profiles are overlapped, the multi-path detection circuit1can detect timing of respective path at high precision. Therefore, reception performance can be improved.

FIG. 8is a block diagram showing a construction of the maximum value retrieving portion of another embodiment of the multi-path detection circuit according to the present invention. InFIG. 8, another embodiment of the present invention has the same construction as the maximum value retrieving portion13in the former embodiment of the present invention shown inFIG. 3except for a coefficient multiplying portion71is provided in the maximum value retrieving portion13. Like components to those in the former embodiment will be identified by like reference numerals and detailed description therefor will be omitted for avoiding redundant discussion and whereby to keep the disclosure simple enough to facilitate clear understanding of the present invention.

It should be noted that the basic construction of another embodiment of the multi-path detection circuit according to the present invention is the same as the construction of the multi-path detection circuit in the former embodiment shown inFIG. 1. Therefore, detailed description therefor will be omitted for avoiding redundant discussion and whereby to keep the disclosure simple enough to facilitate clear understanding of the present invention.

InFIG. 8, the maximum value retrieving portion13is constructed with the level comparing portion13a, the selector13b, buffer portion13c, maximum position storage portion13dand coefficient multiplying portion71.

The level comparing portion13acompares the sample of the delay profile data with the interim maximum value in the retrieved samples. The selector13bselects the sample of the delay profile data and the interim maximum value depending upon the result of comparison of the level comparing portion13a. The buffer portion13cstores the interim maximum value during maximum value retrieval.

In the construction set forth above, all sample of the delay profile data is retrieved sequentially. At the end of search, the maximum value among all samples is stored in the buffer portion13c. The maximum position storage portion13dholds a sample position when the level comparing portion13adetects new maximum value to output the maximum peak position.

Here, the coefficient multiplying portion71multiples the maximum value among all samples stored in the buffer portion13cwith a preliminarily set given value a to output the product to the level comparing portion13aand the selector13b.

By this, upon detection of the maximum value, when a plurality of sample points having equivalent level as the maximum correlation level are present, the sample having the least delay period (left side of the delay profile) among these samples can be selected as maximum point of the samples (left side of the delay profile). It should be noted that coefficient multiplying portion71may be replaced with adder or the like as long as the sample having the least delay period can be taken as the maximum point.

FIG. 9is a flowchart showing operation of another embodiment of the multi-path detection circuit according to the present invention.FIGS. 10A to 10Cshow example of process operation by another embodiment of the present invention. Operation and effect of another embodiment of the multi-path detection circuit according to the present invention will be discussed with reference toFIGS. 8 to 10C.

It should be noted that the basic construction of another embodiment of the multi-path detection circuit according to the present invention is the same as the former embodiment of the multi-path detection circuit and the CDMA receiver shown inFIG. 1andFIG. 2according to the invention. Therefore, Like components to those in the former embodiment will be identified by like reference numerals and detailed description therefore will be omitted for avoiding redundant discussion and whereby to keep the disclosure simple enough to facilitate clear understanding of the present invention. On the other hand, the operation shown inFIG. 9is realized by executing a program in the not shown control memory by the multi-path detection circuit1. As the control memory, RON, IC memory or the like may be used.

Here, discussion will be given for the case where the path interval is narrow and delay profiles of a plurality of correlated peaks overlap as shown inFIG. 5C.FIG. 5Cshows an example of the case in which three correlated peaks are present with interval about one chip. Since respective paths overlap to make respective peak position indefinite. Therefore, accurate detection of the position of the correlated peak is difficult in the conventional method.

In the multi-path detection circuit1, at first, the counter16counting number of detected peaks is reset (step S11ofFIG. 9). Subsequently, in the multi-path detection circuit1, the delay profile is measured by the matched filter11(step S12ofFIG. 9).

Thereafter, maximum value retrieval and maximum position retrieval are performed by the maximum value retrieving portion13(steps S13and S14ofFIG. 9). The maximum value retrieving portion13outputs the path timing (correlated peak position) to the RAKE finger portion5(step S15ofFIG. 9). The pattern generating portion14generates the logical pattern of the detected peak on the basis of the maximum value and the peak position information detected by the maximum value retrieving portion13(step S16ofFIG. 9).

The subtractor15subtracts the logical pattern generated by the pattern generating portion14from the delay profile data to remove the power component of the detected peak from the delay profile data (step S17ofFIG. 9). The delay profile storage portion12stores data from which is removed the power component of the detected peak from the delay profile data by the subtractor15(step S18ofFIG. 9). After completion of this process, the counter16is counted up (step S19ofFIG. 9). By repeating the foregoing process for the times corresponding to number of fingers (step S20ofFIG. 9), necessary number of peaks can be detected.

As set forth above, even in the multi-path environment where the correlated peaks of the delay profiles are overlapped, the multi-path detection circuit1can detect timing of respective path at high precision. Therefore, reception performance can be improved.

FIG. 10Ashows an example of the delay profile in which a plurality of paths are located close proximity and levels of respective paths are substantially equal. In this case, in the maximum value retrieving portion13of the one embodiment of the present invention, difficulty is encountered in making judgment which sample is to be the first correlated peak, in contrast to this, in the maximum value retrieving portion13of the shown embodiment, as the peak of the profile, the point at the left most position (detecting position1) can be selected.

Therefore, the procedure shown inFIGS. 10B and 10C, namely by the procedure, in which the first peak component is removed from the delay profile to detect the detecting position2, and subsequently the second peak component is removed from the delay profile to detect the detecting position3, the power component of the detected peak is removed per one peak to separate all multi-path components to perform detection.

It should be noted that while the shown embodiment is designed to detect the peak located at the leftmost position, namely have the least delay period, as the profile peak sequentially, it is also possible to detect the peak located at the rightmost position, namely the peak having the most delay period as the profile peak for detecting the profile peaks sequentially by inverting the scanning direction.

FIG. 11is a block diagram showing a further embodiment of the multi-path detection circuit according to the present invention. InFIG. 11, the further embodiment of the multi-path detection circuit8according to the present invention has the same construction as one embodiment of the multi-path detection circuit1shown inFIG. 1except for presence of a path interval judgment portion82and a sample subtractiong portion83. Like components to those in the former embodiment will be identified by like reference numerals and detailed description therefor will be omitted for avoiding redundant discussion and whereby to keep the disclosure simple enough to facilitate clear understanding of the present invention. Also, operations of the common components are the same as those in one embodiment of the invention. It should be noted that, in the multi-path detection circuit8, a detection objective pattern generating portion81is formed by the pattern generating portion14and the subtractor15.

The path interval judgment portion82makes judgment of interval of the path timing on the basis of the path timing output from the maximum value retrieving portion13, to drive the detection objective pattern generating portion81when the interval of the path timing becomes smaller than a preliminarily set interval, and to drive the sample detecting portion83when the interval of the path timing becomes greater than the preliminarily set interval. It should be noted that the path interval judgment portion82outputs the path timing output from the maximum value retrieving portion13as is out of the multi-path detection circuit8.

The pattern generating portion14and the subtractor15in the detection objective pattern generating portion81perform generating operation of the delay profile data to be an object for detection. On the other hand, the sample detecting portion83performs similar operation as the prior art. In the further embodiment of the present invention, pattern generating operation by the pattern generating portion14and the subtractor15is performed only for the multi-path, in which the delay profiles overlap.

FIG. 12is an illustration showing one example of the reference pattern to be used in the pattern generating portion in the further embodiment of the present invention. In the delay profile, before and after the wave representative of the profile peak of one path, side lobe is generated to make interval between the correlated peak narrower to cause overlap of the delay profile, these side lobe may be included in the waveform.

Therefore, in the further embodiment of the present invention, upon generation of the reference pattern, the side lob portion is preliminarily prepared together with the profile peak to store as shown inFIG. 12. By this, the side lobe portion can be eliminated from the profile peak including the side lobe of adjacent profile. Thus, more accurate detection of the multi-path component becomes possible.

As set forth above, according to the present invention, in the multi-path detection circuit detecting the timing of the multi-path, the logical shape of the correlated peak in the delay profile is generated for detecting the correlated peak on the basis of the generated logical shape of the correlated peak to enhance precision in detection of the path timing in the multi-path environment where the correlated peaks overlap on the delay profile, to obtain better reception performance.

Although the present invention has been illustrated and described with respect to exemplary embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omission and additions may be made therein and thereto, without departing from the spirit and scope of the present invention. Therefore, the present invention should not be understood as limited to the specific embodiment set out above but to include all possible embodiments which can be embodied within a scope encompassed and equivalent thereof with respect to the feature set out in the appended claims.