Controlling threshold voltage in carbon based field effect transistors

A field effect transistor fabrication method includes defining a gate structure on a substrate, depositing a dielectric layer on the gate structure, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, annealing the first and second metal layers, and defining a carbon based device on the dielectric layer and the gate structure.

BACKGROUND

The present invention relates to field effect transistor fabrication, and more specifically, to threshold voltage control of carbon-based field effect transistors.

Threshold voltage, Vt, control of carbon based field effect transistor devices (FET) such as carbon nanotube (CNT) FET devices relies on gate work function. Simple metal gates on the CNT FET devices may not generate the work functions needed to adjust the threshold voltage, partially because the CNT lattice will be destroyed using the conventional ion-implantation method with dopants to control the threshold voltage. As such, there are currently CMOS process flow limitations in controlling threshold voltage during the fabrication of the devices.

SUMMARY

Exemplary embodiments include a field effect transistor fabrication method, including defining a gate structure on a substrate, depositing a dielectric layer on the gate structure, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, annealing the first and second metal layers, and defining a carbon based device on the dielectric layer and the gate structure.

Additional exemplary embodiments include a field effect transistor fabrication method, including defining a gate structure layer on a substrate, implanting dopants into the gate structure layer, depositing a gate metal layer on the gate structure layer, depositing a dielectric layer on the gate metal layer, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, and depositing a second metal layer.

Additional exemplary embodiments include a field effect transistor fabrication method, including defining a gate structure layer on a substrate, implanting dopants into the gate structure layer, depositing a gate metal layer on the gate structure layer, depositing a dielectric layer on the gate metal layer, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, removing a portion of the second metal layer, depositing a metal and silicon layer onto the first and second metal layers, annealing the metal and silicon layer, and the first and second metal layers and removing the metal and silicon layer, and the first and second metal layers.

Additional exemplary embodiments include a field effect transistor fabrication method, including defining a gate structure layer on a substrate, the gate structure layer having an n-type field effect transistor gate and a p-type field effect transistor gate, implanting an n-type dopant into the n-type field effect transistor gate, implanting a p-type dopant into the p-type field effect transistor gate, depositing a dielectric layer on the gate structure layer, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, depositing a metal and silicon layer onto the second metal layer, annealing the metal and silicon layer, and the first and second metal layers and removing the metal and silicon layer, and the first and second metal layers.

Further exemplary embodiments include a field effect transistor device, including a substrate, a gate structure layer disposed on the substrate, gates disposed in the gate structure layer, a dielectric layer disposed on the gate structure layer and a carbon-based device disposed on the gate metal layer, wherein the dielectric layer is annealed with an element for n-type field effect transistor and p-type field effect transistor voltage control of the gates.

DETAILED DESCRIPTION

Exemplary embodiments include carbon based field effect transistors (FET) and methods to fabricate the carbon based FETs. The exemplary fabrication methods described herein control the threshold voltage Vt of the fabricated FETs. For illustrative purposes, carbon nanotube (CNT) FETs are described. However, it is to be appreciated that any carbon based transistor is contemplated. The exemplary CNT FETs described herein include embedded gate structures and dipole layers that include aluminum (Al) for the p-doped FETs (PFET), and dipole layers with lanthanum (La) (or other lanthanoid elements, magnesium (Mg), strontium (Sr), barium (Ba), scandium (Sc), or yttrium (Y) dysprosium (Dy), holmium (Ho), erbium (Er)) in elemental form, as oxide, or embedded in titanium nitride (TiN), for the n-doped FETs (NFET) to control the device Vt. The same methods can be applied for top-gated CNT FETs. Several resulting devices and several fabrication options are contemplated. The examples described herein are illustrative of the exemplary systems and methods. It will be appreciated that other resulting devices and fabrication methods are contemplated.

FIG. 1illustrates an exemplary carbon based FET device100in accordance with exemplary embodiments. The device includes an NFET101and a PFET102. The device100further includes a substrate105(e.g., silicon) and a gate layer110(e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). The gate layer110is an insulating layer into which gates115,116are patterned and formed as described further herein. In the example device100ofFIG. 1, the gates115,116are initially doped with the same dopant as further described herein. The device100further includes metal gate layers120,121disposed on the gate layer110and the gates115,116. The metal gate layers120,121are shown as different metal types in the example. However, in other exemplary embodiments, the metal gate layers120,121can be the same metal type. The device100also includes dielectric layers125,126disposed respectively on the metal gate layers120,121. As described further herein, the dielectric layers125,126are annealed with an element to respectively form the NFET and PFET Vt control. Each of the NFET101and PFET102respectively includes a source130,131and a drain135,136. Each of the NFET101and PFET102also respectively includes carbon nanostructures140,141(e.g., CNTs).

FIG. 2illustrates an exemplary carbon based FET device200in accordance with exemplary embodiments. The device includes an NFET201and a PFET202. The device200further includes a substrate205(e.g., silicon) and a gate layer210(e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). The gate layer210is the layer into which gates215,216are patterned and formed as described further herein. In the example device200ofFIG. 1, the gates215,216are initially doped with the different dopants as further described herein, in contrast to the example ofFIG. 1. For example, the gate215is doped with an N-type dopant, and the gate216is doped with a P-type dopant. The device200does not include metal gate layers in contrast to the example ofFIG. 1. The device200also includes dielectric layers225,226disposed on the gate layer210and the gates215,216. As described further herein, the dielectric layers225,226are annealed with an element to respectively form the NFET and PFET Vt control. Each of the NFET201and PFET202respectively includes a source230,231and a drain235,236. Each of the NFET201and PFET202also respectively includes carbon nanostructures240,241(e.g., CNTs).

FIG. 3illustrates a flow chart of a method300for fabricating carbon-based FETs in accordance with exemplary embodiments.FIGS. 4-21illustrate intermediate structures in accordance with the method300. It will be appreciated that the method300can be modified in various manners to result in various structures such as the devices ofFIGS. 1 and 2, as described further herein. At block305, a gate layer410is deposited onto a substrate405as illustrated inFIG. 4. The gate layer410can be any suitable insulating material including, but not limited to, SiO2and Si3N4. In exemplary embodiments, the gate layer410can be deposited with any suitable deposition method including, but not limited to, chemical vapor deposition (CVD), wet oxidation and dry oxidation. At block310, trenches412into which the gates are to be formed, are defined as illustrated inFIG. 5. In exemplary embodiments, any suitable photolithography and masking methods are implemented to define the trenches412. In addition, any suitable etching techniques such as, but not limited to, wet chemical etching and reactive ion etching (RIE) are implemented to etch the gate layer410. At block315, a gate material layer414is formed within the trenches as illustrated inFIG. 6. In exemplary embodiments, any suitable material such as, but not limited to, polysilicon and any suitable deposition technique is used to form the gate material layer414. The gate material layer414is then planarized so as to be flush with the gate layer410. In exemplary embodiments, the polysilicon is polished with any suitable technique including but not limited to chemical mechanical polishing (CMP) so as to define gates415,416, as shown inFIG. 7. At block320, the gates415,416are implanted with suitable dopants406, which can be either of p-type or n-type in the method300as also shown inFIG. 7. At block325, metal gates420,421are deposited on the gate layer410and gates415,416.

In exemplary embodiments, a single metal layer420such as, but not limited, to Al can be deposited as illustrated inFIG. 8A. In other exemplary embodiments, a first NFET metal layer421such as but not limited to La, Mg, Sr, Ba, Sc, Y, dysprosium (Dy), holmium (Ho), erbium (Er) in elemental form, as oxide, or embedded in titanium nitride (TiN), can be deposited over one of the gates415,416and a second PFET metal layer422such as, but not limited to, Al followed by or embedded in TiN, can be deposited over the other of the gates415,416as illustrated inFIG. 8B. For illustrative purposes, the method is shown and described with the single metal layer420as illustrated inFIG. 8A. It is understood that the method300could also proceed with the two metal layers421,422. As further described herein, for illustrative purposes, the gate415is described as the NFET side gate and the gate416is described as the PFET side gate. It will be appreciated that either or both gates415,416can be NFET or PFET gates. At block330, a dielectric layer424is deposited onto the metal layer420as illustrated inFIG. 9. In exemplary embodiments, the dielectric layer can be any suitable dielectric material, that is, any electrical insulators or in which an electric field can be sustained with a minimal dissipation of power. For example, the dielectric layer424can be SiO2and can be deposited with any suitable deposition technique as described herein.

As described herein, the NFETs and PFETs can be defined by the types of metal layers subsequently deposited and the processing steps subsequently performed. At block335, a first metal layer460of a first metal type is deposited on the dielectric layer424as illustrated inFIG. 10. As described herein, either of a NFET or PFET metal can be deposited and processed. For illustrative purposes the gate415is the NFET side gate and the gate416is the PFET side gate. In exemplary embodiments, the first metal type is a PFET metal, which can include but is not limited to Al followed by or embedded in TiN. At block340, the first metal layer460is etched from the NFET side gate415as illustrated inFIG. 11. In exemplary embodiments, standard photolithography and etching techniques can be implemented to pattern and remove the first metal layer460. At block345, a second metal layer465of a second metal type is deposited on the first metal layer460that remained over the PFET side gate416and the dielectric layer424as illustrated inFIG. 12. The first and second metal layers460,465are deposited with any suitable metal deposition techniques. In exemplary embodiments, the second metal type is an NFET metal, which can include but is not limited to La, Mg, Sr, Ba, Sc, Y, Dy, Ho, and Er in elemental form, as oxide, or embedded in TiN. At block350, an additional layer of metal470and a silicon layer475are deposited sequentially over the second metal layer465as illustrated inFIG. 13. In exemplary embodiments, the additional layer of metal can be any suitable metal such as TiN that does not recrystallize or impart any of its properties during subsequent processing steps such as annealing. At block355, a drive-in anneal is performed in order to drive the PFET metal from the first metal layer460into the dielectric layer424and the gate416and to drive the NFET metal from the second metal layer465into the dielectric layer424and the gate415. At block360, the additional layer of metal470and silicon layer475are removed. In exemplary embodiments, any suitable etching technique can be implemented to remove the additional layer of metal470and silicon layer475. After the drive-in anneal, as illustrated inFIG. 14, the dielectric layer424becomes distinctively defined as an n-type layer425and a p-type layer426. At block365, a carbon layer439is deposited over the dielectric layers425,426as illustrated inFIG. 15. The carbon layer439can be defined and patterned for the device types contemplated for the NFET/PFET structure such as a CNT FET as described herein, resulting in the NFET and PFET side carbon based devices440,441. It will be appreciated that any type of carbon based device is contemplated in other exemplary embodiments. At block470, the remaining source430,431and drain435,436contacts are defined as described herein. It will be appreciated that any standard photolithography and etching techniques can be implemented to define and pattern the source430,431and drain435,436of the NFET and PFET devices. The resultant structure is similar to the device as illustrated inFIG. 1.

In exemplary embodiments, the method300can be modified such that the intermediate structures and final structures are modified, but still achieve the threshold voltage control in the resultant devices. For example, at block320described herein, the gates415,416are implanted with the same dopant. In other exemplary embodiments, instead of implanting both gates415,416with the same dopant, a first dopant471can be implanted on the NFET gate415with an n-type dopant, while the PFET gate416is covered with photoresist475as illustrated inFIG. 17. Similarly, a second dopant472can be implanted on the PFET gate416with a p-type dopant, while the NFET gate416is covered with photoresist480as illustrated inFIG. 18. As described herein, any suitable photolithography and masking technique can be implemented to protect the NFET gate415and the PFET gate416during the respective implants. In exemplary embodiments, the deposition of the gate metal layer420and block325can be skipped, and the dielectric layer424is deposited at block330as illustrated inFIG. 19. The subsequent fabrication blocks in method300are then performed as described with respect toFIG. 3. The resultant structure is similar to the device as illustrated inFIG. 2.

In another example, referring again toFIG. 3, at block345a second metal type is deposited. In exemplary embodiments, instead of depositing the additional metal layer470and the silicon layer475at block350, the second metal layer465is first etched from the first metal layer460, as illustrated inFIG. 20. Then, as illustrated in block350, the additional layer of metal470and a silicon layer475are deposited sequentially over the second metal layer465as illustrated inFIG. 21. The subsequent fabrication blocks in method300are then performed as described with respect toFIG. 3. The resultant structure is similar to the device as illustrated inFIG. 1.

FIG. 22illustrates a plot of carbon nanotube device transfer curves showing the threshold voltage adjustment by employing different dipole layers. The plot2200illustrates that, for PFET, Al-based gate dielectric lowers the threshold voltage and La-based dielectric increases the threshold voltage as described herein. As such, the threshold voltage can be tuned during the gate stack fabrication process without having to dope the resultant devices, which can potentially be damaged during the conventional ion-implantation process.