PASSIVATION STRUCTURES FOR SEMICONDUCTOR DEVICES

Semiconductor devices, and more particularly passivation structures for semiconductor devices are disclosed. A semiconductor device may include an active region, an edge termination region that is arranged along a perimeter of the active region, and a passivation structure that may form a die seal along the edge termination region. The passivation structure may include a number of passivation layers in an arrangement that improves mechanical strength and adhesion of the passivation structure along the edge termination region. An interface formed by at least one of the passivation layers may be provided with a pattern that serves to more evenly distribute forces related to thermal expansion and contraction during power cycling, thereby reducing cracking and delamination in the passivation structure. A patterned layer may be at least partially embedded in the passivation structure in an arrangement that forms the corresponding pattern in overlying portions of the passivation structure.

FIELD OF THE DISCLOSURE

The present disclosure is related to semiconductor devices, and in particular to passivation structures for semiconductor devices.

BACKGROUND

Semiconductor devices such as transistors and diodes are ubiquitous in modern electronic devices. Wide bandgap semiconductor material systems such as gallium nitride (GaN) and silicon carbide (SiC) are being increasingly utilized in semiconductor devices to push the boundaries of device performance in areas such as switching speed, power handling capability, and thermal conductivity. Examples include individual devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), Schottky barrier diodes, PiN diodes, high electron mobility transistors (HEMTs), and integrated circuits such as monolithic microwave integrated circuits (MMICs) that include one or more individual devices.

Semiconductor devices are typically formed in an active region of a semiconductor die. In semiconductor die manufactured to support high voltages and currents, concentration of electric fields can interfere with the proper operation thereof. Concentration of electric fields is especially problematic at edges of the semiconductor die. Accordingly, an edge termination region surrounds the active region about a perimeter of the semiconductor die to reduce electric fields at the edges of the die. Without an edge termination region, electric fields would concentrate at the edges of the die and cause the performance of the die to suffer. For example, the breakdown voltage, leakage current, and/or reliability of the die may be significantly reduced. Specifically, the die may suffer from leakage current under reverse bias when subject to thermal stress (e.g., temperatures greater than 150° C.) that may be associated with higher operating voltages. While several edge termination structures have been proposed for reducing the concentration of electric fields at the edges of a die, many of the proposed structures may not be suitable for withstanding thermal shock and power cycling associated with higher temperature and higher voltage operating conditions.

The art continues to seek improved edge termination structures for semiconductor devices capable of overcoming challenges associated with conventional semiconductor devices.

SUMMARY

The present disclosure is related to semiconductor devices, and in particular to passivation structures for semiconductor devices. A semiconductor device may include an active region, an edge termination region that is arranged along a perimeter of the active region, and a passivation structure that may form a die seal along the edge termination region. The passivation structure may include a number of passivation layers in an arrangement that improves mechanical strength and adhesion of the passivation structure along the edge termination region. An interface formed by at least one of the passivation layers may be provided with a pattern that serves to more evenly distribute forces related to thermal expansion and contraction during power cycling, thereby reducing cracking and delamination in the passivation structure. The pattern may include a number of protrusions and recesses in at least one of the passivation layers. A patterned layer may be at least partially embedded in the passivation structure to form the pattern in overlying portions of the passivation structure.

In one aspect, a semiconductor device comprises: a drift region; an active region comprising a portion of the drift region; an edge termination region in the drift region and arranged along a perimeter of the active region; a passivation structure on the edge termination region; and a patterned layer that is formed within the passivation structure. In certain embodiments, the patterned layer is embedded within the passivation structure. In certain embodiments, the patterned layer comprises polysilicon. The passivation structure may comprise a first passivation layer on the drift region and a second passivation layer that is on the first passivation layer. In certain embodiments, the patterned layer is arranged between the first passivation layer and the second passivation layer. In certain embodiments, the second passivation layer forms at least one protrusion that is registered with at least one portion of the patterned layer.

The passivation structure of the semiconductor device may further comprise a third passivation layer that is on the second passivation layer and wherein the at least one protrusion of the second passivation layer extends into the third passivation layer. In certain embodiments, the at least one protrusion comprises a plurality of protrusions and a top surface of the third passivation layer is planar in at least some portions of the passivation structure. The passivation structure may further comprise a fourth passivation layer that is on the third passivation layer, and the top surface of the third passivation structure forms an interface with the fourth passivation layer. In certain embodiments, the edge termination region further comprises a plurality of guard rings in the drift region; and the at least one portion of the patterned layer is registered with an individual guard ring of the plurality of guard rings. In certain embodiments, the at least one portion of the patterned layer is registered with at least two individual guard rings of the plurality of guard rings. The at least one guard ring of the plurality of the guard rings may be devoid of a directly overlying portion of the patterned layer. In certain embodiments, the at least one guard ring of the plurality of guard rings is arranged closer to the active region than any other guard ring of the plurality of guard rings. In certain embodiments, the at least one portion of the patterned layer forms a field plate in the passivation structure. The at least one portion of the patterned layer may be registered with the individual guard ring of the plurality of guard rings in a vertically offset position. In certain embodiments, the patterned layer is arranged on the first passivation layer and the patterned layer further extends past a sidewall of the first passivation layer in a direction towards an outside edge of the edge termination region.

In certain embodiments, the patterned layer forms at least one continuous ring around a perimeter of the active region. In certain embodiments, the patterned layer forms at least one segmented ring around a perimeter of the active region. The at least one segmented ring may comprise a first segmented ring and a second segmented ring of the patterned layer; and ring segments of the first segmented ring are arranged in laterally offset positions relative to ring segments of the second segmented ring.

In certain embodiments, the drift region comprises silicon carbide (SiC). In certain embodiments, the active region comprises a SiC metal-oxide-semiconductor field-effect-transistor (MOSFET).

In another aspect, a semiconductor device comprises: a drift region; an active region comprising a portion of the drift region; an edge termination region in the drift region and arranged along a perimeter of the active region; and a passivation structure on the edge termination region, wherein a passivation layer of the passivation structure forms at least one protrusion that partially extends into an additional passivation layer of the passivation structure. The at least one protrusion may form at least one protrusion ring around a perimeter of the active region. In certain embodiments, the at least one protrusion ring is continuous around the perimeter of the active region. In certain embodiments, the at least one protrusion ring is segmented around the perimeter of the active region.

In certain embodiments, the at least one protrusion comprises a plurality of protrusions; the passivation layer forms a plurality of recesses in between adjacent protrusions of the plurality of protrusions; and portions of the additional passivation layer extend into each recess of the plurality of recesses. In certain embodiments, at least a portion of a top surface of the additional passivation layer that is opposite the plurality of recesses is planar. In certain embodiments, the plurality of recesses comprises a first recess and a second recess; the first recess comprises a width that is larger than a width of the second recess; and the first recess is arranged closer to an outside edge of the edge termination region than the second recess.

The semiconductor device may further comprise a patterned layer in the passivation structure and the patterned layer is registered with the at least one protrusion. In certain embodiments, the patterned layer comprises polysilicon. In certain embodiments, the at least one protrusion comprises a plurality of protrusions; and a discontinuous portion of the patterned layer is registered with each protrusion of the plurality of protrusions. In certain embodiments, the edge termination region comprises a plurality of guard rings in the drift region; and a discontinuous portion of the patterned layer is registered with an individual guard ring of the plurality of guard rings.

DETAILED DESCRIPTION

The present disclosure is related to semiconductor devices, and in particular to passivation structures for semiconductor devices. A semiconductor device may include an active region, an edge termination region that is arranged along a perimeter of the active region, and a passivation structure that may form a die seal along the edge termination region. The passivation structure may include a number of passivation layers in an arrangement that improves mechanical strength and adhesion of the passivation structure along the edge termination region. An interface formed by at least one of the passivation layers may be provided with a pattern that serves to more evenly distribute forces related to thermal expansion and contraction during power cycling, thereby reducing cracking and delamination in the passivation structure. The pattern may include a number of protrusions and recesses in at least one of the passivation layers. A patterned layer may be at least partially embedded in the passivation structure to form the pattern in overlying portions of the passivation structure.

FIG. 1Ais a top view illustration of an exemplary semiconductor device10according to the present disclosure. The semiconductor device10includes an active region12and an edge termination region14surrounding the active region12about a perimeter of the semiconductor device10. Depending on the particular application, the active region12may include one or more semiconductor devices or semiconductor device cells formed therein, such as one or more metal-oxide-semiconductor field-effect transistors (MOSFETs), diodes, Schottky diodes, junction barrier Schottky (JBS) diodes, PiN diodes, and insulated gate bipolar transistors (IGBTs), among others. The semiconductor device10may embody wide bandgap semiconductor devices, for example silicon carbide (SiC)-based devices. The edge termination region14is configured to reduce a concentration of an electric field at the edges of the semiconductor device10in order to improve the performance thereof. For example, the edge termination region14may increase a breakdown voltage of the semiconductor device10and decrease a leakage current of the semiconductor device10over time, as discussed in detail below. By way of example, the edge termination region14may include one or more guard rings, a junction termination extension (JTE), and combinations thereof.

FIG. 1Billustrates a cross-sectional view of a portion of the semiconductor device10ofFIG. 1Afor embodiments where the semiconductor device10includes a MOSFET. While an exemplary MOSFET is described, the principles of the present disclosure are applicable to other semiconductor devices listed above, including diodes, Schottky diodes, JBS diodes, PiN diodes, and IGBTs, among others. The semiconductor device10includes a substrate16and a drift region18on the substrate16. The drift region18may embody one or more drift layers of a wide bandgap semiconductor material, for example SiC. An inside edge14A of the edge termination region14is indicated by a vertical dashed line to delineate the edge termination region14from the active region12. An outside edge14B of the edge termination region14may correspond with a peripheral edge of the semiconductor device10. In the edge termination region14, a number of guard rings20are provided in the drift region18. Specifically, the guard rings20are provided adjacent or even directly adjacent a top surface18A of the drift region18opposite the substrate16. The guard rings20may be formed by ion implantation and the implants used may include aluminum (Al), boron (B), or any other suitable p-type dopant when the drift region18is configured as an n-type layer. Each guard ring20forms a sub-region in the edge termination region14that has a doping type that is opposite a doping type of the drift region18. In the present example, the drift region18is an n-type layer while the guard rings20are p-type sub-regions. However, the principles of the present disclosure apply equally to devices with opposite polarity configurations where the doping types as illustrated inFIG. 1Bmay be reversed. For illustrative purposes, five guard rings20are illustrated inFIG. 1B. In various embodiments, the number of guard rings20may be five or more, or ten or more, or twenty or more, or in a range from five to twenty, or in a range from ten to twenty, depending on the application.

When a voltage is supported by the drift region18, electric field concentration at the outside edge14B of the edge termination region14tends to be substantially higher than at the inside edge14A of the edge termination region14. In certain embodiments, a surface depletion protection region22may also be provided in the drift region18at the outside edge14B of the edge termination region14. The surface depletion protection region22may have the same doping type as the drift region18but a higher doping concentration than that of the drift region18. In this manner, the surface depletion protection region22may prevent depletion at the top surface18A of the drift region18in order to further improve the performance of the semiconductor device10. In certain embodiments, the surface depletion protection region22is provided by implantation. A passivation layer24may be provided on the top surface18A of the drift region18opposite the substrate16to passivate the top surface18A of the drift region18. The passivation layer24may embody one or more layers of insulating materials of any suitable material, for example one or more layers of oxide and/or nitride-based dielectric layers. In certain embodiments, the passivation layer24may embody a multilayer structure that includes one or more of a field oxide layer, one or more intermetal dielectric layers, and a top insulating layer.

The substrate16may have a doping concentration between 1×1017cm−3and 1×1020cm−3. In various embodiments, the doping concentration of the substrate16may be provided at any subrange between 1×1017cm−3and 1×1020cm−3. For example, the doping concentration of the substrate16may be between 1×1018cm−3and 1×1020cm−3, between 1×1019cm−3and 1×1020cm−3, between 1×1017cm−3and 1×1019cm−3, between 1×1017cm−3and 1×1018cm−3, and between 1×1018cm−3and 1×1019cm−3.

The drift region18may have a doping concentration between 1×1014cm−3and 1×1018cm−3. In various embodiments, the doping concentration of the drift region18may be provided at any subrange between 1×1014cm−3and 1×1018cm−3. For example, the doping concentration of the drift region18may be between 1×1015cm−3and 1×1018cm−3, between 1×1016cm−3and 1×1018cm−3, between 1×1017cm−3and 1×1018cm−3, between 1×1014cm−3and 1×1017cm−3, between 1×1014cm−3and 1×1016cm−3, between 1×1014cm−3and 1×1015cm−3, between 1×1015cm−3and 1×1017cm−3, between 1×1015cm−3and 1×1016cm−3, and between 1×1016cm−3and 1×1017cm−3. The surface depletion protection region22may have a doping concentration that is higher than the doping concentration of the drift region18. In various embodiments, the surface depletion protection region22may have a doping concentration in a range from two times to 105times the doping concentration of the drift region18.

The guard rings20may have a doping concentration between 5×1016cm−3and 1×1021cm−3. In various embodiments, the doping concentration of the guard rings20may be provided at any subrange between 5×1016cm−3and 1×1021cm−3. For example, the doping concentration of the guard rings20may be between 5×1018cm−3and 1×1021cm−3, between 5×1019cm−3and 1×1021cm−3, between 5×1020cm−3and 1×1021cm−3, between 5×1016cm−3and 1×1020cm−3, between 5×1016cm−3and 1×1019cm−3, and between 5×1016cm−3and 1×1020cm−3.

As discussed above, the active region12may include one or more semiconductor devices. In the example ofFIG. 1B, the active region12includes at least one MOSFET cell26, for example a SiC-based MOSFET where the drift region18embodies one or more layers of SiC. The MOSFET cell26includes the substrate16and the drift region18. A number of junction implants28are provided in the drift region18, and specifically in the top surface18A of the drift region18opposite the substrate16. The junction implants28include a first well region28A having a doping type that is opposite that of the drift region18and a second well region28B having a doping type that is the same as the drift region18. The junction implants28are separated from one another by a JFET region30. The JFET region30has the same doping type as that of the drift region18and a higher doping concentration than that of the drift region18. A source contact32is provided over each one of the junction implants28on the top surface18A of the drift region18opposite the substrate16such that the source contact32contacts a portion of the first well region28A and the second well region28B. A gate oxide layer34, which may embody other insulating materials for other semiconductor devices, is provided on the top surface18A of the drift region18opposite the substrate16over the JFET region30and a portion of each one of the junction implants28such that the gate oxide layer34partially overlaps each one of the second well regions28B. A gate contact36is provided on the gate oxide layer34. A drain contact38is provided on a surface of the substrate16opposite the drift region18. The MOSFET cell26may be tiled across the active region12or tiled in a desired pattern with one or more other semiconductor devices (e.g., diodes) to provide a desired functionality.

FIG. 2Ais a partial cross-sectional view of a semiconductor device40that is similar to the semiconductor device10ofFIG. 1Band provides a more detailed view of the edge termination region14. The edge termination region14may include a surface charge compensation region42that is formed between the guard rings20and at the top surface18A of the drift region18. The surface charge compensation region42may be formed by ion implantation and may have a doping type that is opposite a doping type of the drift region18. In this manner, the surface charge compensation region42has a same doping type as the guard rings20, but with a lower doping concentration than the guard rings20. In the present example, the drift region18is an n-type layer while the surface charge compensation region42and the guard rings20have p-type doping. However, the principles of the present disclosure apply equally to devices with opposite polarity configurations. The surface charge compensation region42may have a thickness relative to the top surface18A of the drift region18that is the same or less than a corresponding thickness of the guard rings20. The surface charge compensation region42may reduce sensitivity of the guard rings20to surface charges at interfaces between a first passivation layer24-1and the drift region18.

As illustrated, the first passivation layer24-1may be formed on the top surface18A of the drift region18and the guard rings20. The first passivation layer24-1may comprise an oxide layer or other insulation layer that is formed in the same fabrication step and comprises a same material as the gate oxide layer34ofFIG. 1B. In certain embodiments, the first passivation layer24-1may have a thickness that is greater than a thickness of the gate oxide layer34ofFIG. 1B. For example, the thickness of the first passivation layer24-1may be from 2 times to 100 times the thickness of the gate oxide layer34ofFIG. 1B. For MOSFET applications, the first passivation layer24-1may comprise silicon dioxide. In other embodiments, the first passivation layer24-1comprises a different dielectric material than the gate oxide layer34ofFIG. 1B. In various applications, the first passivation layer24-1may be referred to as a field oxide for the semiconductor device40. A second passivation layer24-2may be provided on the first passivation layer24-1. In certain embodiments, the second passivation layer24-2may comprise one or more dielectric layers, which may include combinations of silicon dioxide layers and silicon nitride layers, that serve as inter-metal dielectrics to electrically insulate metal interconnect lines and may also serve as inter-level dielectrics to electrically insulate polysilicon gates and lines from metal interconnect lines. In the semiconductor device40, one or more portions of the second passivation layer24-2in the active region12serve to at least partially define and insulate a gate interconnect36′ and a source interconnect32′. In this cross-section ofFIG. 2A, the source contact (32ofFIG. 1B) is not visible as the source interconnect32′ is configured as a runner or a bus that electrically connects with the source contact (32ofFIG. 1B) in a different portion of the semiconductor device40. As illustrated, the second passivation layer24-2may overlap the first passivation layer24-1in a direction toward the outside edge14B and contact the top surface18A of the drift region18and the surface depletion protection region22. A third passivation layer24-3may be provided over the second passivation layer24-2, the gate interconnect36′ and the source interconnect32′. The third passivation layer24-3may comprise one or more dielectric layers, which may include combinations of silicon dioxide layers and silicon nitride layers, that can provide a diffusion and/or moisture barrier for the underlying portions of the semiconductor device40. The third passivation layer24-3may overlap the second passivation layer24-2in a direction toward the outside edge14B and contact the top surface18A of the drift region18and the surface depletion protection region22. Finally, a fourth passivation layer24-4may be provided on the third passivation layer24-3. In certain embodiments, the fourth passivation layer24-4may comprise a material with chemical, mechanical, and high temperature stability, for example a polyimide that may provide a scratch-resistant coating for the semiconductor device40. Additionally, the passivation layers24-1to24-4may not extend entirely to the outside edge14B of the edge termination region14in order to provide clearance for a saw or scribe street when the semiconductor device40is singulated. One or more combinations of the passivation layers24-1to24-4may be referred to as a passivation structure and/or a die seal for the semiconductor device40. In the present example, the drift region18is an n-type layer while the guard rings20are p-type sub-regions, although reverse polarity configurations are also applicable to the present disclosure.

When the semiconductor device40is electrically activated, an electric potential from the backside of the drift region18(e.g., the drain contact38ofFIG. 1B) tends to concentrate electric fields along the edge termination region14. When the semiconductor device40is in a blocking mode, voltages supported by the drift region18tend to be higher at the outside edge14B and decrease in a direction toward the inside edge14A with each of the guard rings20. In this regard, higher associated operating temperatures can introduce thermal stress in the edge termination region14and promote structural failures in one or more of the passivation layers24-1to24-4. For example, thermal shock and power cycling during operating conditions and/or qualification testing can lead to delamination and/or cracking of one or more of the passivation layers24-1to24-4, thereby causing catastrophic device failure. In particular, delamination and/or cracking may be more problematic when adjacent ones of the passivation layers24-1to24-4that have dissimilar materials and/or different materials properties are subjected to thermal expansion and contraction during power cycling. Dissimilar materials properties may include a mismatched coefficient of thermal expansion (CTE), among others. By way of example, delamination and/or cracking can occur at an interface between the second passivation layer24-2and the third passivation layer24-3in arrangements where the second passivation layer24-2comprises silicon dioxide and third passivation comprises silicon nitride. The likelihood of such structural failures may be higher when the interface between the second passivation layer24-2and the third passivation layer24-3is substantially planar throughout a majority of the edge termination region14. In this regard, forces related to thermal stress will be exerted in-plane and along continuous planar portions of the second and third passivation layers24-2,24-3. This can be especially problematic when the semiconductor device40is scaled with larger device sizes suitable for handling higher operating powers in applications such as automotive drivetrains.

FIG. 2Bis a top view illustration of the semiconductor device40ofFIG. 2A.FIG. 2Bis provided to generally illustrate the relative location of the edge termination region14relative to the active region12. The active region12may include an inner region12′ and an outer region12″. The inner region12′, which may be referred to as a device core, may include the source contacts32and gate contacts36as illustrated inFIG. 1B, and the outer region12″ may include the gate interconnect36′ and the source interconnect32′ as illustrated inFIG. 2A. The edge termination region14may include an inner region14′ and an outer region14″. The outer region14″ is defined where the passivation layers24-1to24-4ofFIG. 2Aare not present, thereby forming part of the saw or scribe street as previously described.

FIG. 3is a partial cross-sectional view of a semiconductor device44that is similar to the semiconductor device40ofFIG. 2Aand further includes an arrangement of the passivation layers24-1to24-4in the edge termination region14that provides improved structural stability. Any combination of the passivation layers24-1to24-4may be referred to as a passivation structure or a die seal for the semiconductor device44. As illustrated, a top surface of the second passivation layer24-2that is opposite the first passivation layer24-1is formed with a number of protrusions24-2′ and a number of corresponding recesses24-2″ that are formed between adjacent ones of the protrusions24-2′ to form a nonplanar or patterned interface with the third passivation layer24-3. Portions of the third passivation layer24-3are formed within the recesses24-2″ and over the protrusions24-2′ to cover the second passivation layer24-2. In this manner, the interface between the second passivation layer24-2and the third passivation layer24-3is subdivided into a series of adjacent and nonplanar segments that may serve to improve adhesion by breaking up forces related to thermal expansion and contraction during power cycling, thereby reducing cracking and delamination. The protrusions24-2′ and the recesses24-2″ may alternate in one or more lateral directions in a corrugated pattern. Since the edge termination region14may be provided around a perimeter of the active region12as illustrated inFIG. 2B, the protrusions24-2′ and the recesses24-2″ may embody protrusion rings and recessed rings that either partially or entirely surround the active region12. For illustrative purposes the protrusions24-2′ and the recesses24-2″ are represented with squared features, however the protrusions24-2′ and the recesses24-2″ can have rounded, curved, and/or angled features, and boundaries that are represented with straight lines may have some irregularities.

In certain embodiments, a patterned layer46is provided on the first passivation layer24-1to promote formation of the protrusions24-2′ and the recesses24-2″ of the second passivation layer24-2in a corresponding pattern. In particular, discontinuous portions of the patterned layer46may be registered with one or more of the guard rings20. When the second passivation layer24-2is formed on the first passivation layer and the patterned layer46, portions of the second passivation layer24-2may form in a conformal manner over the patterned layer46to form the protrusions24-2′. Additionally, other portions of the second passivation layer24-2are conformal on the first passivation layer24-1and within spaces formed between discontinuous portions of the patterned layer46to form the recesses24-2″. As illustrated, the patterned layer46may be embedded, or partially embedded, within the second passivation layer24-2, but for the portions of the patterned layer46that are in contact with the first passivation layer24-1. In this manner, the patterned layer46may be embedded within the passivation structure formed by one or more of the passivation layers24-1to24-4. The third passivation layer24-3may then be formed on the second passivation layer24-2in a manner that fills the recesses24-2″ and covers the protrusions24-2′. In certain embodiments, relative spacings between adjacent ones of the discontinuous portions of the patterned layer46may increase in a direction from the inside edge14A of the edge termination region14to the outside edge14B. In this manner, relative widths of the recesses24-2″ may also increase from the inside edge14A to the outside edge14B such that recesses24-2″ that are closer to the outside edge14B are wider and filled with more of the third passivation layer24-3than recesses24-2″ that are closer to the inside edge14A. Such configurations may provide improved structural stability near the outside edge14B where cracking and delamination may be more likely to occur. As illustrated, depending on the widths of the recesses24-2′, the third passivation layer24-3may form with a planar top surface or planar interface with the fourth passivation layer24-4as illustrated over the portions of the patterned layer46that are closest to the active region12. The third passivation layer24-3may also form with a top surface or interface with the fourth passivation layer24-4that is conformal to the underlying second passivation layer24-2as illustrated over the portions of the patterned layer46that are closest to the outside edge14B. For example, the closest recess24-2″ to the outside edge14B is wide enough that a portion of the fourth passivation layer24-4extends or protrudes downward into portions of the third passivation layer24-3that are conformal to this recess24-2″. In certain embodiments, the shape of the top surface of the third passivation layer24-3may further be controlled by adjusting an overall thickness of the third passivation layer24-3where an increased thickness would generally promote a more planar top surface and a decreased thickness would generally promote a more conformal top surface. In this manner, the pattern of the protrusions24-2′ may not extend entirely through the passivation structure (e.g., all four passivation layers24-1to24-4inFIG. 3). Rather the pattern of the protrusions24-2′ may eventually be smoothed over by overlying passivation layers (e.g., portions of24-3and24-4inFIG. 3) depending on one or more of the spacing of the patterned layer46and/or relative thicknesses of one or more of the overlying passivation layers24-3,24-4. In other embodiments, the spacing of the patterned layer46and/or the relative thicknesses of one or more of the overlying passivation layers24-3,24-4may be arranged to allow the pattern of the protrusions24-2′ to form all the way through the passivation structure (24-1to24-4). In still further embodiments, the pattern of the protrusions24-2′ may be smoothed over only in certain portions of the semiconductor device44. For example, the third passivation layer24-3smooths over portions of the pattern of protrusions24-2′ near the inside edge14A while other portions of the third passivation layer24-3are conformal near the outside edge14B inFIG. 3.

The patterned layer46may comprise any material that is non-reactive with the first passivation layer24-1and the second passivation layer24-2. In certain embodiments, the patterned layer46comprises a material that exhibits improved mechanical stability under thermal stress than the surrounding passivation layers24-1to24-3. For example, the patterned layer46may have a higher elastic modulus than any of the passivation layers24-1to24-4, in order to resist deformation under thermal cycling. In this manner, the patterned layer46may also reduce expansion and contraction of the second passivation layer24-2. In certain embodiments, the patterned layer46may comprise polysilicon that may be doped n-type or p-type and in other embodiments, the patterned layer46may comprise polysilicon that is low-doped or undoped. In certain embodiments, the patterned layer46may comprise a same material as the gate contact36(e.g., polysilicon), thereby providing the advantage of forming the patterned layer46in a same fabrication step as the gate contact36. In other embodiments, the patterned layer46may comprise other materials, such as other passivation or dielectric materials, and metal layers. In still further embodiments, the patterned layer46may embody a multiple layer structure including multiple layers of any of above-described materials and combinations thereof.

The patterned layer46may comprise electrically conductive materials or electrically non-conductive materials depending on the embodiment. When the patterned layer46comprises conductive materials, for example doped polysilicon or metal layers, each discontinuous portion of the patterned layer46may be registered with one of the guard rings20as illustrated inFIG. 3. In this manner, the discontinuous portions of the patterned layer46may be capacitively coupled to corresponding guard rings20to stabilize electric fields within the semiconductor device44. In certain embodiments, discontinuous portions of the patterned layer46may have widths as measured in a parallel direction to the drift region18that are either the same or smaller than a width of the corresponding guard ring20. In other embodiments, discontinuous portions of the patterned layer46may have widths that are larger than widths of corresponding guard rings20. In still further embodiments, widths of the discontinuous portions of the patterned layer46can be smaller, larger, or the same in different locations relative to the outside edge14B of the edge termination region14. The widths of discontinuous portions of the patterned layer46relative to widths of corresponding guard rings20may be tailored for electric fields in a particular application. As described above, the guard rings20may be formed as rings around the perimeter of the active region12. In certain embodiments, the discontinuous portions of the patterned layer46form corresponding rings of the patterned layer46that are also formed around the perimeter of the active region12.

FIG. 4is a partial cross-sectional view of a semiconductor device48that is similar to the semiconductor device44ofFIG. 3, but wherein individual portions of the patterned layer46are registered with more than one of the guard rings20. InFIG. 4, a discontinuous portion of the patterned layer46is arranged to extend over two individual and adjacent guard rings20. In further embodiments, a discontinuous portion of the patterned layer46may be arranged to extend over more than two individual guard rings20without deviating from the principles of the present disclosure. As illustrated, a spacing between adjacent guard rings20may progressively increase in a direction from the inside edge14A toward the outside edge14B of the edge termination region14.

Accordingly, widths of individual discontinuous portions of the patterned layer46and corresponding recesses24-2″ of the second passivation layer24-2may also increase in a direction toward the outside edge14B. As previously described, the patterned layer46may comprise electrically conductive or electrically nonconductive materials. For electrically conductive materials, the patterned layer46may be registered with multiple guard rings20to tailor electric fields. For electrically nonconductive materials, the patterned layer46may be provided across portions of the drift region18that are between guard rings20with minimal impact on electric fields of the semiconductor device48. In certain embodiments, portions of the patterned layer46may be provided as described forFIG. 3in combination with other portions of the patterned layer46as described forFIG. 4, depending on the electric field requirements of a particular application.

FIG. 5is a partial cross-sectional view of a semiconductor device50that is similar to the semiconductor device44ofFIG. 3, but wherein at least one guard ring20does not have a portion of the patterned layer46registered with it in an overlying arrangement. As illustrated, no portion of the patterned layer46is registered with the guard ring20that is arranged closest to the active region12. In certain arrangements, particularly when the patterned layer46comprises an electrically conductive material, having portions of the patterned layer46arranged too close to the active region12may cause dielectric weakness or dielectric breakdown near the source interconnect32′. In this regard, the patterned layer46may not be provided directly over one or more of the guard rings20that are arranged closest to the active region12. In such an arrangement, the recess24-2″ that is closest to the source interconnect32′ may have a width that is larger than others of the recesses24-2″ while widths of the other recesses24-2″ may then progressively increase in a direction toward the outside edge14B as previously described. Having a larger width recess24-2″ closer to the active region12may serve to further enhance mechanical strength of the passivation structure in combination with the other protrusions24-2′ and recesses24-2″. In other embodiments, the patterned layer46may not be arranged over other guard rings20provide different patterns of the protrusions24-2′ and recesses24-2″. For example, the patterned layer46may only be provided over every other guard ring20to provide larger widths of the recesses24-2″ between protrusions24-2′. Such alternative arrangements may also be utilized to provide different electric filed patterns for the semiconductor device50. In certain embodiments, portions of the patterned layer46in the semiconductor device50may also be provided as described above forFIG. 4, depending on the electric field requirements of a particular application.

FIG. 6is a partial cross-sectional view of a semiconductor device52that is similar to the semiconductor device44ofFIG. 3, but wherein at least one guard ring20is electrically connected to portion of the patterned layer46through the first passivation layer24-1. InFIG. 6, a portion46′ of the patterned layer46that is closest to the active region12is electrically connected to the underlying guard ring20through an opening that is formed in the first passivation layer24-1. Additionally, the portion46′ of the patterned layer46extends over the passivation layer24-1to form a field plate54that is electrically connected to the underlying guard ring20and that is otherwise surrounded by the passivation layers24-1,21-2. In other embodiments, the field plate54may not be directly electrically connected with the corresponding guard ring20such that the first passivation layer24-1extends completely between the field plate54and the guard ring20. Dimensions of the resulting field plate54may be determined to tune the electric field profile along the edge termination region14for improved efficiency. Since the field plate54is registered with the underlying guard ring20, the field plate54may form a continuous field plate ring or a segmented field plate ring around the active region12. Depending on the application, one or more of the other portions of the patterned layer46may also form field plates or filed plate rings that are registered with corresponding underlying guard rings20. In further embodiments, one or more of the field plates54may extend over adjacent ones of the guard rings20. As illustrated inFIG. 6, no portion of the patterned layer46is provided over the guard ring20closest to the active region12as described forFIG. 5. In other embodiments, portions of the patterned layer46in the semiconductor device52may also be provided as described forFIG. 3and/orFIG. 4in combination withFIG. 6, depending on the electric field requirements of a particular application.

FIG. 7is a partial cross-sectional view of a semiconductor device56that is similar to the semiconductor device44ofFIG. 3, but wherein portions of the patterned layer46are registered with underlying guard rings20in a vertically offset manner. As illustrated, each discontinuous portion of the patterned layer46is positioned over a corresponding one of the guard rings20in an offset manner so that each discontinuous portion of the patterned layer46also extends over portions of the first passivation layer24-1that are adjacent to guard rings20. Relative positions and dimensions of the patterned layer46may be determined to tune the electric field profile along the edge termination region14for improved efficiency in a similar manner as described for the field plate54ofFIG. 6. While all portions of the patterned layer46are illustrated in an offset manner relative to the guard rings20, other embodiments may include a single portion of the patterned layer46that is offset or multiple but not all portions of the patterned layer46that are offset. In this regard, portions of the patterned layer46may be provided as illustrated inFIG. 7in combination with any of the arrangements of the patterned layer46as illustrated in any ofFIG. 3,FIG. 4,FIG. 5, andFIG. 6, depending on the electric field requirements of a particular application.

The patterned layer46of any of the previously described embodiments may form one or more continuous rings or one or more segmented rings around the active region12.FIG. 8Ais a top view of a portion of a semiconductor device58where the patterned layer46forms one or more continuous rings around a perimeter of the active region12.FIG. 8Bis a top view of a portion of a semiconductor device60where the patterned layer46forms one or more segmented rings around a perimeter of the active region12. In bothFIG. 8AandFIG. 8B, portions of the source interconnect32′ are visible next to the edge termination region14. The views provided inFIGS. 8A and 8Bcould be taken anywhere along peripheral edges of the edge termination region14as illustrated inFIG. 2B. For illustrative purposes, the second, third, and fourth passivation layers24-2to24-4are omitted to show arrangements of the patterned layer46. Additionally, whileFIGS. 8A and 8Billustrate four rings to represent principles of the present disclosure, the patterned layer46may form any number of rings including one or more, or five or more, or ten or more, or twenty or more, or in a range from one to twenty, or in a range from five to twenty, or in a range from ten to twenty, depending on the application.

As illustrated inFIG. 8A, the patterned layer46forms a series of rings that are separate from one another and each ring is continuous in the edge termination region14. As previously described, each ring of the patterned layer46may form a corresponding protrusion in an overlying passivation layer and the spaces between each ring of the patterned layer46may form a corresponding recess in an overlying passivation layer for improved mechanical stability under thermal stress. In this regard, the protrusion that corresponds with each ring of the patterned layer46may also form a continuous ring protrusion around the active region12. Accordingly, the edge termination region14is provided with alternating protrusions and recesses in a direction from the inside edge14A toward the outside edge14B.

As illustrated inFIG. 8B, the patterned layer46forms a series of ring segments that extend through the edge termination region14and around the active region12. Rather than forming continuous rings as illustrated inFIG. 8A, the patterned layer46forms discontinuous or segmented rings in the edge termination region14and around the active region12. In this manner, the edge termination region14is provided with alternating protrusions and recesses in at least two directions, for example in a first direction from the inside edge14A toward the outside edge14B and in a second direction that is perpendicular to the first direction. As further illustrated inFIG. 8B, the relative positions of ring segments within each segmented ring of the patterned layer46are laterally offset with relative positions of ring segments in adjacent segmented rings in a direction toward the outside edge14B to further improve mechanical stability under thermal stress.

FIG. 9is a partial cross-sectional view of a semiconductor device62that is similar to the semiconductor device44ofFIG. 3, but wherein the patterned layer46forms a ring at a perimeter of the first passivation layer24-1. InFIG. 9, a portion of the gate contact36and the gate oxide layer34are visible in the active region12. In the edge termination region14, the patterned layer46is provided on a top surface of the first passivation layer24-1and along a sidewall of the first passivation layer24-1that is arranged closest to the outside edge14B of the edge termination region14. In this manner, the patterned layer46may extend past and overlap the first passivation layer24-1. In certain embodiments, the overlapped portion of the patterned layer46may directly contact the drift region18and/or the surface charge compensation region42of the drift region18, when present. In other embodiments, the overlapped portion of the patterned layer46may be separated from the drift region18by an insulating layer64. The insulating layer64may comprise a same material that is formed in a same fabrication step as the gate oxide layer34, or the insulating layer64may comprise a different material than the gate oxide layer34. By providing the patterned layer46in an overlapping manner relative to the first passivation layer24-1, the corresponding protrusion24-2′ of the second passivation layer24-2may be provided closer to the outside edge14B for embodiments where thermal stress may be higher in this location. In certain embodiments, the patterned layer46ofFIG. 9may be provided in combination with any of the arrangements of the patterned layer46as illustrated in any ofFIG. 3,FIG. 4,FIG. 5,FIG. 6, andFIG. 7, depending on the electric field requirements of a particular application. Additionally, the patterned layer46as illustrated inFIG. 9may form a continuous ring or a discontinuous ring as illustrated inFIGS. 8A and 8B.

While the present disclosure provides exemplary embodiments that include MOSFETs, the principles of the present disclosure are also applicable to edge termination structures in other semiconductor devices, for example diodes, Schottky diodes, JBS diodes, PiN diodes, and IGBTs, among others. Semiconductor devices of the present disclosure may embody wide bandgap semiconductor devices, for example SiC-based devices.