SEMICONDUCTOR PACKAGE

Disclosed is a semiconductor package comprising a redistribution substrate and a semiconductor chip on the redistribution substrate. The redistribution substrate includes a plurality of first conductive patterns including a pair of first signal patterns that are adjacent to each other, and a plurality of second conductive patterns on surfaces of the first conductive patterns and coupled to the first conductive patterns. The second conductive patterns include a ground pattern insulated from the pair of first signal patterns. The ground pattern has an opening that penetrates the ground pattern. When viewed in plan, the pair of first signal patterns overlap the opening.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2021-0165375, filed on Nov. 26, 2021, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The present inventive concepts relate to a semiconductor package, and more particularly, to a semiconductor package including a redistribution substrate.

A semiconductor package is provided to implement an integrated circuit chip for use in electronic products. A semiconductor package is typically configured such that a semiconductor chip is mounted on a printed circuit board and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the development of electronic industry, various researches have been conducted to improve reliability and durability of semiconductor packages.

SUMMARY

Some embodiments of the present inventive concepts provide a semiconductor package whose electrical properties are improved.

According to some embodiments of the present inventive concepts, a semiconductor package may comprise: a redistribution substrate; and a semiconductor chip on the redistribution substrate. The redistribution substrate may include: a plurality of first conductive patterns including a pair of first signal patterns that are adjacent to each other; and a plurality of second conductive patterns on first surfaces of the first conductive patterns and coupled to the first conductive patterns. The second conductive patterns may include a ground pattern insulated from the pair of first signal patterns. The ground pattern may have an opening that penetrates the ground pattern. When viewed in plan, the pair of first signal patterns may overlap the opening.

According to some embodiments of the present inventive concepts, a semiconductor package may comprise: a redistribution substrate that includes a plurality of first conductive patterns, a plurality of second conductive patterns, and a plurality of third conductive patterns; a plurality of solder balls on a bottom surface of the redistribution substrate; and a semiconductor chip on a top surface of the redistribution substrate. The second conductive patterns may be between the first conductive patterns and the third conductive patterns. The first conductive patterns may include a first signal pattern. The second conductive patterns may include a second redistribution pattern insulated from the first signal pattern. The third conductive patterns may include a third redistribution pattern that is insulated from and vertically overlaps the first signal pattern. The second redistribution pattern may not be between the first signal pattern and the third conductive pattern.

According to some embodiments of the present inventive concepts, a semiconductor package may comprise: a redistribution substrate; a plurality of solder balls on a bottom surface of the redistribution substrate; a semiconductor chip on a top surface of the redistribution substrate; and a molding layer on the top surface of the redistribution substrate, the molding layer covering the semiconductor chip. The redistribution substrate may include: a dielectric layer that includes a photo-imageable polymer; a plurality of first conductive patterns in the dielectric layer and laterally spaced apart from each other; a plurality of second conductive patterns on surfaces of the first conductive patterns and coupled to the first conductive patterns; and a plurality of third conductive patterns on surfaces of the second conductive patterns and coupled to the second conductive patterns. The first conductive patterns may include: a pair of first signal patterns that are adjacent to each other; and a plurality of first redistribution patterns laterally spaced apart from the pair of first signal pattern. The first redistribution patterns may be electrically insulated from the pair of first signal patterns. The second conductive patterns may include: a plurality of second signal patterns coupled to the pair of first signal patterns; and a plurality of second redistribution patterns insulated from the second signal patterns. The third conductive patterns may include: a plurality of third signal patterns coupled to the second signal patterns; and a plurality of third redistribution patterns insulated from the third signal patterns. The pair of first signal patterns may not vertically overlap the second redistribution patterns. The pair of first signal patterns may vertically overlap at least one of the third redistribution patterns. The first redistribution patterns may include a first signal redistribution pattern, a first ground pattern, and a first power pattern. The second redistribution patterns may include a second signal redistribution pattern, a second ground pattern, and a second power pattern. The third redistribution patterns may include a third signal redistribution pattern, a third ground pattern, and a third power pattern. Each of the second conductive patterns may include a via portion and a wire portion on the via portion.

DETAIL DESCRIPTION

In this description, like reference numerals may indicate like components. The following will now describe semiconductor packages according to the present inventive concepts.

FIG.1Aillustrates a plan view showing a second ground pattern and third signal patterns of a redistribution substrate according to example embodiments.FIG.1Billustrates a cross-sectional view taken along line I-I′ ofFIG.1A.FIG.1Cillustrates an enlarged view showing section III ofFIG.1B.FIG.1Dillustrates a cross-sectional view taken along line II-II′ ofFIG.1A.FIG.1Eillustrates a plan view showing first conductive patterns according to example embodiments.FIG.1Fillustrates a plan view showing second conductive patterns according to example embodiments.FIG.1Gillustrates a plan view showing third conductive patterns according to example embodiments.FIG.1Bcorresponds to a cross-section taken along line I-I′ ofFIGS.1E,1F, or1G.FIG.1Dcorresponds to a cross-section taken along line II-II′ ofFIGS.1E,1F, or1G.

Referring toFIGS.1A to1G, a semiconductor package10may include a redistribution substrate100, solder balls500, a semiconductor chip200, and a molding layer400. The redistribution substrate100may have a top surface and a bottom surface that are opposite to each other.

As illustrated inFIG.1B, the solder balls500may be disposed on the bottom surface of the redistribution substrate100. The solder balls500may serve as terminals of the semiconductor package10. The solder balls500may include ground solder balls and signal solder balls. The ground solder balls and signal solder balls may be laterally spaced apart and electrically separated from each other. The ground solder balls may each be a terminal to which a ground voltage is applied. The signal solder balls may each serve as a path through which a data signal is input and output. The solder balls500may include a solder material. The solder material may include tin, silver, bismuth, lead, or any alloy thereof.

The redistribution substrate100may include a dielectric layer107, first conductive patterns110R and110S, second conductive patterns120R and120S, third conductive patterns130R and130S, and conductive pads150R and150S. The dielectric layer107may include an organic material, such as a photo-imageable dielectric material. The photo-imageable dielectric material may be a polymer. The photo-imageable dielectric material may include, for example, at least one selected from photosensitive polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers. In some embodiments, the dielectric layer107may be provided in plural. There may be a variation in the number of the plurality of dielectric layers107that are stacked. For example, the plurality of dielectric layers107may include the same material. An indistinct interface may be provided between neighboring dielectric layers107. Alternatively, a lowermost dielectric layer107and an uppermost dielectric layer107may include a different material from those of other dielectric layers107. For example, the lowermost dielectric layer107and the uppermost dielectric layer107may include a solder resist material and may serve as a protection layer.

The bottom surface of the redistribution substrate100may include a bottom surface of the lowermost dielectric layer107. A first direction (see first direction D1 ofFIG.1A) may be parallel to a bottom surface of the lowermost dielectric layer107. A second direction (see second direction D2 ofFIG.1A) may be parallel to the bottom surface of the lowermost dielectric layer107and substantially orthogonal to the first direction D1. A third direction D3 may be substantially perpendicular to the first direction D1 and the second direction D2.

The first conductive patterns110R and110S may be provided in and on the lowermost dielectric layer107. Each of the first conductive patterns110R and110S may include an under-bump portion and a first wire portion. The under-bump portion may be provided in the lowermost dielectric layer107. For example, the under-bump portion of the may extend through the lowermost dielectric layer107, and a bottom surface of the under-bump portion may be coplanar with a bottom surface of the lowermost dielectric layer107. The under-bump portion may be provided on a bottom surface of the solder ball500that corresponds thereto. The first wire portion and the under-bump portion may be connected to each other without an interface therebetween. For example, the first wire portion and the under-bump portion may be in material continuity with one another. As used herein, the term “material continuity” may refer to structures, patterns, and/or layers that are formed at the same time and of the same material, without a break in the continuity of the material of which they are formed. As one example, structures, patterns, and/or layers that are in “material continuity” may be homogeneous monolithic structures. The first wire portion may be provided on a top surface of the lowermost dielectric layer107. For example, the first wire portion may be in contact with the top surface of the lowermost dielectric layer107. The first conductive patterns110R and110S may include metal, such as copper.

The first conductive patterns110R and110S may include a first signal pattern110S and first redistribution patterns110R. As shown inFIG.1E, the first signal pattern110S may include a pair of first signal patterns. The pair of first signal patterns110S may be adjacent to each other. The pair of first signal patterns110S may be a portion of a signal pair pattern SP. The signal pair pattern SP may be a differential signal pair. The first signal patterns110S may be used for transfer of differential signal pairs and/or transfer of high-speed signals.

As shown inFIG.1B, the first redistribution patterns110R may be laterally spaced apart and electrically insulated from the first signal patterns110S. In this description, the phrase “laterally spaced apart from” may mean “horizontally spaced apart.” The term “horizontally” may mean “parallel to the bottom surface of the redistribution substrate100.” For example, the term “horizontally” may mean “parallel to the first direction D1 or the second direction D2.” The first redistribution patterns110R may include a first signal redistribution pattern and a first ground pattern110G that are spaced apart from each other. The first signal redistribution pattern may transfer an electric signal different from those transmitted by the first signal patterns110S. The first ground pattern110G may be configured to receive a ground voltage. The first redistribution patterns110R may further include a first power pattern. The first power pattern may be laterally spaced apart and electrically insulated from the first signal redistribution pattern and the first ground pattern110G. The first power pattern may be configured to receive a power voltage. The power voltage may be different from the ground voltage.

The second conductive patterns120R and120S may be provided on surfaces of the first conductive patterns110R and110S, and may be electrically connected to the first conductive patterns110R and110S, respectively. The surfaces of the first conductive patterns110R and110S may be top surfaces of the first conducive patterns110R and110S. The second conductive patterns120R and120S may contact the top surfaces of the first conductive patterns110R and110S, respectively. Each of the second conductive patterns120R and120S may include a second via portion and a second wire portion. The second via portion may be provided in the dielectric layer107that corresponds thereto. The second via portion may contact a top surface of a corresponding one of the first conductive patterns110R and110S. The second wire portion may be provided on the second via portion and a top surface of the dielectric layer107. For example, the second wire portion may be in contact with the top surface of the dielectric layer107. The second wire portion and the second via portion may be connected to each other without an interface therebetween. For example, the second wire portion and the second via portion may be in material continuity with one another. The second conductive patterns120R and120S may include metal, such as copper.

The second conductive patterns120R and120S may include second signal patterns120S and second redistribution patterns120R. The second signal patterns120S may be provided on and coupled to the first signal pattern110S. As illustrated inFIG.1F, the second signal patterns120S may include a pair of neighboring second signal patterns120S. The pair of second signal patterns120S may be another portion of the signal pair pattern SP. The second signal patterns120S may be used for transfer of high-speed signals.

The second redistribution patterns120R may be provided on and coupled to the first redistribution patterns110R. The second redistribution patterns120R may be laterally spaced apart and electrically insulated from the second signal patterns120S. The second redistribution patterns120R may include a second ground pattern120G, a second signal redistribution pattern, and a second power pattern. The second signal redistribution pattern may transfer an electric signal different from those transmitted by the second signal patterns120S. The second ground pattern120G may be laterally spaced apart and electrically separated from the second signal redistribution pattern. The second ground pattern120G may be provided on and coupled to the first ground pattern110G. The second power pattern may be laterally spaced apart and insulated from the second ground pattern120G and the second signal redistribution pattern. The second power pattern may be configured to be coupled to the first power pattern and to receive the power voltage.

The third conductive patterns130R and130S may be provided on surfaces of the second conductive patterns120R and120S and may be electrically connected to the second conductive patterns120R and120S, respectively. The surfaces of the second conductive patterns120R and120S may be top surfaces of the second conducive patterns120R and120S. The third conductive patterns130R and130S may contact the top surfaces of the second conductive patterns120R and120S, respectively. Each of the third conductive patterns130R and130S may include a third via portion and a third wire portion. The third via portion may be provided in the dielectric layer107that corresponds thereto. The third via portion may contact the top surface of a corresponding one of the second conductive patterns120R and120S. The third wire portion may be provided on the third via portion and a top surface of the dielectric layer107that corresponds thereto. For example, the third wire portion may be in contact with the top surface of the dielectric layer107. The third wire portion and the third via portion may be connected to each other without an interface therebetween. For example, the third wire portion and the third via portion may be in material continuity with one another. The third conductive patterns130R and130S may include metal, such as copper.

The third conductive patterns130R and130S may include third signal patterns130S and third redistribution patterns130R. The third signal patterns130S may be provided on and coupled to the second signal patterns120S. As illustrated inFIGS.1A and1D, the third signal patterns130S may include a pair of neighboring third signal patterns130S. The pair of third signal patterns130S may be still another portion of the signal pair pattern SP. The third signal patterns130S may be used for transfer of high-speed signals.

The third redistribution patterns130R may be provided on and coupled to the second redistribution patterns120R. The third redistribution patterns130R may be laterally spaced apart and electrically insulated from the third signal patterns130S. The third redistribution patterns130R may include a third ground pattern130G, a third signal redistribution pattern, and a third power pattern. The third signal redistribution pattern may transfer an electric signal different from those transmitted by the third signal patterns130S. The third ground pattern130G may be provided on and coupled to the second ground pattern120G. The third ground pattern130G may be laterally spaced apart and electrically insulated from the third signal redistribution pattern. The third power pattern may be laterally spaced apart and insulated from the third ground pattern130G and the third signal redistribution pattern. The third power pattern may be coupled to the second power pattern. The third power pattern may be configured to receive the power voltage.

The conductive pads150R and150S may be provided on top surfaces of the third conductive patterns130R and130S, respectively. The conductive pads150R and150S may be provided in or on the uppermost dielectric layer107. The conductive pads150R and150S may include a metallic material, such as copper. The conductive pads150R and150S may include metal, such as copper, nickel, or gold.

The conductive pads150R and150S may include signal pads150S and redistribution pads150R. The signal pads150S and the redistribution pads150R may be respectively disposed on the third signal patterns130S and the third redistribution patterns130R. The redistribution pads150R may include a ground pad150G. The ground pad150G may be provided on the third ground pattern130G.

An electrical connection with the redistribution substrate100may include an electrical connection with at least one selected from the first conductive patterns110R and110S, the second conductive patterns120R and120S, the third conductive patterns130R and130S, and the conductive pads150R and150S.

The redistribution substrate100may include the signal pair pattern SP. The signal pair pattern SP may include a pair of first signal patterns110S, a pair of second signal patterns120S, a pair of third signal patterns130S, and a pair of signal pads150S. The signal pair pattern SP may be a differential signal pair discussed above. The signal pair pattern SP may have impedance greater than those of other signal patterns in the redistribution substrate100. Therefore, the signal pair pattern SP may promptly transfer a data signal of the semiconductor chip200. As illustrated inFIG.1A, the redistribution substrate100may include a plurality of signal pair patterns SP. Each of the signal pair patterns SP may have impedance of about 85 Ω to about115Q. Because the impedance of each of the signal pair patterns SP is in a range of about 85 Ω to about 115 Ω, the signal pair pattern SP may have improved electrical properties. For example, the signal pair patterns SP may improve in insertion loss and increase in signal transfer rate. For brevity of description, the following will discuss one signal pair pattern SP.

A pair of third signal patterns130S may have inner lateral surfaces and outer lateral surfaces. The inner lateral surfaces of the third signal patterns130S may face each other. The pair of third signal patterns130S may be spaced apart at a regular interval from the third redistribution patterns130R. For example, intervals between the third redistribution patterns130R and different outer lateral surfaces of the pair of third signal patterns130S may be substantially the same as or similar to each other. As shown inFIGS.1B and1C, a first horizontal interval A1between the third redistribution patterns130R and a first lateral surface S1of one of the third signal patterns130S may be about 90% to about 110% of a second horizontal interval A2between the third redistribution patterns130R and a second outer lateral surface S2of the third signal pattern130S. The second outer lateral surface S2of the third signal pattern130S may be different from the first outer lateral surface S1of the third signal pattern130S. The signal pair pattern SP may improve in impedance characteristics and electrical properties.

As illustrated inFIG.1D, a third horizontal interval A3between the third signal redistribution patterns and a third outer lateral surface S3of a pair of third signal patterns130S may be about 90% to about 110% of a fourth horizontal interval A4between the third signal redistribution patterns and a fourth outer lateral surface S4of the pair of third signal patterns130S. The third and fourth outer lateral surfaces S3and S4of the pair of third signal patterns130S may be opposite to each other. The third horizontal interval A3depicted inFIG.1Dmay be about 90% to about 110% of the first horizontal interval A1depicted inFIG.1Band about 90% to about 110% of the second horizontal interval A2depicted inFIG.1B. The fourth horizontal interval A4depicted inFIG.1Dmay be about 90% to about 110% of the first horizontal interval A1depicted inFIG.1Band of the second horizontal interval A2depicted inFIG.1BTherefore, the signal pair pattern SP may improve in impedance characteristics and electrical properties.

The third signal patterns130S may not vertically overlap the second redistribution patterns120R. The term “vertically” may mean that “parallel to the third direction D3.” For example, the second redistribution patterns120R may not be interposed between the first conductive patterns110R and110S and bottom surfaces of the third signal patterns130S. Therefore, the occurrence of parasitic capacitance may be prevented between the third signal patterns130S and the second redistribution patterns120R.

The second ground pattern120G may have an opening1290that penetrates therethrough. For example, the opening1290may penetrate top and bottom surfaces of the second ground pattern120G. For example, a portion of the second ground pattern120G may be removed to form the opening1290. A cutting process may be performed to remove the portion of the second ground pattern120G. Alternatively, any method other than the cutting process may be employed to remove the portion of the second ground pattern120G.

When viewed in plan as shown inFIG.1A, the opening1290may overlap a pair of third signal patterns130S. The opening1290may have a size greater than that of the pair of third signal patterns130S. As the second ground pattern120G has the opening1290, when viewed in plan, the third signal patterns130S may not overlap the second ground pattern120G. Therefore, the occurrence of parasitic capacitance may be prevented between the second ground pattern120G and the third signal patterns130S. The signal pair pattern SP may improve in impedance characteristics and electrical properties.

As illustrated inFIGS.1B to1D, the opening1290may expose inner sidewalls120Gcof the second ground pattern120G. The inner sidewalls120Gcof the second ground pattern120G may be vertically aligned with sidewalls of corresponding third redistribution patterns130R. The sidewalls of the third redistribution patterns130R may be directed toward and adjacent to the third signal patterns130S.

As illustrated inFIGS.1B and1C, a first spacing A1′ between the first outer lateral surface of one of the third signal patterns130S and the inner sidewalls120Gcof the second ground pattern120G may be about 90% to about 110% of the first horizontal interval A1. For example, the first spacing A1′ may be substantially the same as the first horizontal interval A1. A second spacing A2′ between the second ground pattern120G and the second outer lateral surface S2of the third signal pattern130S may be about 90% to about 110% of the second horizontal interval A2. For example, the second spacing A2′ may be substantially the same as the second horizontal interval A2.

As illustrated inFIG.1D, a third spacing A3′ between the second ground pattern120G and the third outer lateral surface S3of the pair of third signal patterns130S may be about 90% to about 110% of the third horizontal interval A3. For example, the third spacing A3′ may be substantially the same as the third horizontal interval A3. A fourth spacing A4′ between the second ground pattern120G and the fourth outer lateral surface S4of the pair of third signal patterns130S may be about 90% to about 110% of the fourth horizontal interval A4. For example, the fourth spacing A4′ may be substantially the same as the fourth horizontal interval A4. Each of the first, second, third, and fourth spacings A1′, A2′, A3′, and A4′ may be an imaginary horizontal interval.

When viewed in plan as shown inFIG.1A, the third signal patterns130S may be spaced apart at a regular interval from the inner lateral sidewalls120Gcof the second ground pattern120G. For example, intervals between the second ground pattern120G and different outer lateral surfaces of a pair of third signal patterns130S may be substantially the same as or similar to each other. For example, the first spacing A1′ may be about 90% to about 110% of the second spacing A2′, about 90% to about 110% of the third spacing A3′, and about 90% to about 110% of the fourth spacing A4′. The second spacing A2′ may be about 90% to about 110% of the third spacing A3′ and about 90% to about 110% of the fourth spacing A4′. The third spacing A3′ may be about 90% to about 110% of the fourth spacing A4′. Therefore, the signal pair pattern SP may improve in impedance characteristics and electrical properties.

The second ground pattern120G may further have holes129H. The holes129H may be spaced apart from the opening1290. When viewed in plan, the holes129H may each have a size less than that of the opening1290. For example, the holes129H may each have a width less than that of the opening1290. As illustrated inFIGS.1B and1C, neighboring dielectric layers107may in contact with each other through the holes129H. Therefore, even if the second ground pattern120G has a relatively large planar area, the dielectric layers107may be favorably bonded to each other.

Referring toFIGS.1B to1D, at least one of the third signal patterns130S may vertically overlap one of the first conductive patterns110R and110S. No conductive components (e.g., the second redistribution patterns120R) may be provided between the third signal patterns130S and the one of the first conductive patterns110R and110S. A first vertical interval C1between the third signal patterns130S and the one of the first conductive patterns110R and110S may be greater than the first horizontal interval A1, the second horizontal interval A2, the third horizontal interval A3, and the fourth horizontal interval A4. Therefore, the signal pair pattern SP may improve in impedance characteristics.

As illustrated inFIG.1C, the redistribution substrate100may further include seed patterns180. The seed patterns180may be provided on bottom surfaces of the first conductive patterns110R and110S, bottom surfaces of the second conductive patterns120R and120S, and bottom surfaces of the third conductive patterns130R and130S. Sidewalls of the seed patterns180may be vertically aligned with sidewalls of the corresponding first conductive patterns110R and110S, the second conductive patterns120R and120S, and the third conductive patterns130R and130S. The seed patterns180may be spaced apart from each other. The seed patterns180may not be interposed between the first conductive patterns110R and110S and the solder balls500. The seed patterns180may include metal different from those of the first, second, and third conductive patterns110R,110S,120R,120S,130R, and130S. For example, the seed patterns180may include one or more of copper, titanium, and any alloy thereof. For brevity of drawings, figures other thanFIG.1Comit illustration of the seed patterns180, but the present inventive concepts are not intended to exclude the seed patterns180.

The semiconductor chip200may be mounted on the top surface of the redistribution substrate100. When viewed in plan, the semiconductor chip210may be disposed on a central region of the redistribution substrate100. The semiconductor chip200may be one of a logic chip, a buffer chip, and a memory chip. The logic chip may include an applicant specific integrated circuit (ASIC) chip or an application processor (AP) chip. The ASIC chip may include an application specific integrated circuit (ASIC). Alternatively, the semiconductor chip200may include a central processing unit (CPU) or a graphic processing unit (GPU).

The semiconductor chip200may include chip pads205and first integrated circuits (not shown). The first integrated circuits may be provided in the semiconductor chip200. The chip pads205may be provided on a bottom surface of the semiconductor chip200and coupled to the first integrated circuits. For example, bottom surfaces of the chip pads205may be coplanar with the bottom surface of the semiconductor chip200. The phrase “a certain component is electrically connected to the semiconductor chip200” may mean that “a certain component is electrically connected to the first integrated circuits through the chip pads205of the semiconductor chip200.”

Conductive bumps250may be interposed between the redistribution substrate100and the semiconductor chip200. For example, the conductive bumps250may be coupled to the chip pads205and the conductive pads150R and150S. The conductive bumps250may contact the chip pads205and the conductive pads150R and150S. Therefore, the semiconductor chip200may be coupled through the conductive bumps250to the redistribution substrate100. The chip pads205may have ground chip pads coupled through the conductive bumps250to the first, second, and third ground patterns110G,120G, and130G. The chip pads205may have first signal chip pads coupled through the conductive bumps250to the first, second, and third signal patterns110S,120S, and130S. The first signal chip pads may be chip pads for transfer of differential signal pairs. The chip pads205may have other chip pads coupled through the conductive bumps250to the first, second, and third redistribution patterns110R,120R, and130R. The conductive bumps250may include a solder material. The conductive bumps250may further include pillar patterns, and the pillar patterns may include metal, such as copper. In this case, the pillar patterns may be in contact with the chip pads205.

An under-fill layer410may be provided in a gap between the redistribution substrate100and the semiconductor chip200, thereby covering sidewalls of the conductive bumps250. The under-fill layer410may include a dielectric polymer, such as an epoxy polymer.

The molding layer400may be provided on a top surface of the semiconductor chip200. The molding layer400may cover the semiconductor chip200. The molding layer400may include a dielectric polymer, such as an epoxy-based molding compound. The molding layer400may include a different material from that of the under-fill layer410, but the present inventive concepts are not limited thereto.

The semiconductor package10may be fabricated by a chip-last process, but the present inventive concepts are not limited thereto.

FIG.2Aillustrates a plan view showing first signal patterns and a second ground pattern of a redistribution substrate according to example embodiments.FIG.2Billustrates a plan view showing second signal patterns and a second ground pattern of a redistribution substrate according to example embodiments.FIG.2Cillustrates a cross-sectional view taken along line I-I′ ofFIG.2A.FIG.2Dillustrates a cross-sectional view taken along line II-II′ ofFIG.2A.FIGS.2C and2Dcorrespond to cross-sectional views respectively taken along lines I-I′ and II-II′ ofFIG.2B. A description ofFIGS.1E to1Gwill be included in the following description ofFIGS.2A to2D.

Referring toFIGS.2A to2D, a semiconductor package10A may include a redistribution substrate100A, solder balls500, semiconductor chip200, and a molding layer400. The semiconductor package10A may further include conductive bumps250and an under-fill layer410. The solder balls500, the semiconductor chip200, the conductive bumps250, the under-fill layer410, and the molding layer400may be substantially the same as those discussed in the examples ofFIGS.1A to1G.

The redistribution substrate100A may include a dielectric layer107, first conductive patterns110R and110S, second conductive patterns120R and120S, third conductive patterns130R and130S, and conductive pads150R and150S. A pair of first signal patterns110S may have inner lateral surfaces and outer lateral surfaces. The inner lateral surfaces of the first signal patterns110S may face each other. The pair of first signal patterns110S may be spaced apart at a regular interval from the first redistribution patterns110R. For example, intervals between the first redistribution patterns110R and different outer lateral surfaces of the pair of first signal patterns110S may be substantially the same as or similar to each other. For example, as shown inFIG.2C, a first horizontal interval B1between the first redistribution patterns110R and a first lateral surface S10of one of the first signal patterns110S may be about 90% to about 110% of a second horizontal interval B2between the first redistribution patterns110R and a second outer lateral surface S20of the first signal pattern110S. The first horizontal interval B1may be substantially the same as the second horizontal interval B2. The first outer lateral surface S10of the first signal pattern110S may be different from the second outer lateral surface S20of the first signal pattern110S. As the pair of first signal patterns110S are spaced apart at a regular interval from the first redistribution patterns110R, the signal pair pattern SP may improve in impedance characteristics and electrical properties.

The first signal patterns110S may not vertically overlap the second redistribution patterns120R. For example, the second redistribution patterns120R may not be interposed between the third conductive patterns130R and130S and top surfaces of the first signal patterns110S.

According to some embodiments, the second ground pattern120G may have an opening1290. When viewed in plan as shown inFIG.2A, the opening1290may overlap a pair of first signal patterns110S. The opening1290may have a size greater than that of the pair of first signal patterns110S. As the second ground pattern120G has the opening1290, when viewed in plan, the first signal patterns110S may not overlap the second ground pattern120G. Therefore, the signal pair pattern SP may improve in impedance characteristics and electrical properties.

As illustrated inFIG.2B, the opening1290may expose inner sidewalls120Gcof the second ground pattern120G. The inner sidewalls120Gcof the second ground pattern120G may be vertically aligned with sidewalls of corresponding first redistribution patterns110R. The sidewalls of the first redistribution patterns110R may be directed toward and adjacent to the first signal patterns110S.

When viewed in plan, the first signal patterns110S may be spaced apart at a regular interval from the inner sidewalls120Gcof the second ground pattern120G. For example, when viewed in plan, intervals between the second ground pattern120G and different outer lateral surfaces of the pair of first signal patterns110S may be substantially the same as or similar to each other. When viewed in plan, a fifth spacing B1′ between the second ground pattern120G and the first lateral surface S10of one of the first signal patterns110S may be about 90% to about 110% of the first horizontal interval B1. For example, the fifth spacing B1′ may be substantially the same as the first horizontal interval B1.

When viewed in plan, a sixth spacing B2′ between the second ground pattern120G and the second outer lateral surface S20of the first signal pattern110S may be about 90% to about 110% of the second horizontal interval B2. For example, the sixth spacing B2′ may be substantially the same as the second horizontal interval B2.

As illustrated inFIG.2A, a seventh spacing B3′ between the second ground pattern120G and a third outer lateral surface of a pair of first signal patterns110S may be about 90% to about 110% of the fifth spacing B1′ and about 90% to about 110% of the sixth spacing B2′. The third outer lateral surface of the pair of first signal patterns110S may be different from the first outer lateral surface S10and the second outer lateral surface S20. Therefore, the signal pair pattern SP may improve in impedance characteristics and electrical properties. The fifth spacing B1′, the sixth spacing B2′, and the seventh spacing B3′ may be imaginary horizontal intervals.

The second ground pattern120G may have holes129H. The holes129H may be substantially the same as those discussed in the examples ofFIGS.1A,1D, and1F.

As illustrated inFIG.2C, at least one of the first signal patterns110S may vertically overlap one of the third conductive patterns130R and130S. No conductive components may be provided between the first signal patterns110S and the one of the third conductive patterns130R and130S. For example, the second redistribution patterns120R may not interposed between the first signal patterns110S and the one of the third conductive patterns130R and130S. A second vertical interval C2between the first signal patterns110S and the one of the third conductive patterns130R and130S may be greater than the first horizontal interval B1and the second horizontal interval B2. Therefore, the signal pair pattern SP may improve in impedance characteristics.

FIG.3Aillustrates a plan view showing first signal patterns, a second ground pattern, and third signal patterns of a redistribution substrate according to example embodiments.FIG.3Billustrates a cross-sectional view taken along line I-I′ ofFIG.3A.FIG.3Cillustrates a cross-sectional view taken along line II-II′ ofFIG.3A. A description ofFIGS.1E and1Gwill be included in the following description ofFIGS.3A to3C.

Referring toFIGS.3A to3C, a semiconductor package 10B may include a redistribution substrate100B, solder balls500, a semiconductor chip200, and a molding layer400.

The redistribution substrate100B may include a dielectric layer107, first conductive patterns110R and110S, second conductive pattern120R and120S, third conductive patterns130R and130S, and conductive pads150R and150S. A pair of first signal patterns110S may be spaced apart at a regular interval from the first redistribution patterns110R. For example, a first horizontal interval B1may be about 90% to about 110% of a second horizontal interval B2. The first horizontal interval B1and the second horizontal interval B2may be greater than a second vertical interval C2.

A pair of third signal patterns130S may be spaced apart at a regular interval from the third redistribution patterns130R. A first horizontal interval A1, a second horizontal interval A2, a third horizontal interval A3, a fourth horizontal interval A4, and a first vertical interval C1may be the same as those discussed in the examples ofFIGS.1A to1D. For example, one of the first, second, third, and fourth horizontal intervals A1, A2, A3, and A4may be about 90% to 110% of another of the first, second, third, and fourth horizontal intervals A1, A2, A3, and A4. Each of the first, second, third, and fourth horizontal intervals A1, A2, A3, and A4may be greater than the first vertical interval C1.

According to some embodiments, the second ground pattern120G may have an opening1290that does not vertically overlap a corresponding signal pair pattern SP. An arrangement relation between the second ground pattern120G and the first conductive patterns110R and110S may be substantially the same as that discussed in the examples ofFIGS.2A to2D. An arrangement between the second ground pattern120G and the third conductive patterns130R and130S may be substantially the same as that discussed in the examples ofFIGS.1A to1G. For example, when viewed in plan, the opening1290may vertically overlap neither a pair of first signal patterns110S or a pair of third signal patterns130S. Therefore, when viewed in plan, the second ground pattern120G may be spaced apart from the pair of first signal patterns110S and the pair of third signal patterns130S. The signal pair pattern SP may improve in impedance characteristics and electrical properties.

The opening1290may expose inner sidewalls120Gcof the second ground pattern120G. Each of the inner sidewalls120Gcof the second ground pattern120G may be vertically aligned with a corresponding one of sidewalls of the first redistribution patterns110R or a corresponding one of sidewalls of the third redistribution patterns130R.

FIG.4illustrates a cross-sectional view taken along line I-I′ ofFIG.3A, showing a semiconductor package according to example embodiments.

Referring toFIG.4, a semiconductor package10C may include a redistribution substrate100C, solder balls500, a semiconductor chip200, and a molding layer400. For example, the redistribution substrate100C may include a dielectric layer107, first conductive patterns110R and110S, second conductive patterns120R and120S, third conductive patterns130R and130S, and conductive pads150R and150S. The dielectric layer107, the first conductive patterns110R and110S, the second conductive patterns120R and120S, the third conductive patterns130R and130S, and the conductive pads150R and150S may be substantially the same as those discussed in the examples ofFIGS.3A to3C. Alternatively, the first conductive patterns110R and110S, the second conductive patterns120R and120S, and the third conductive patterns130R and130S may be substantially the same as those discussed in the examples ofFIGS.1A to1GorFIGS.2A to2D. In contrast, the first conductive patterns110R and110S may be provided on a top surface of the lowermost dielectric layer107, and may not extend into the lowermost dielectric layer107. The first conductive patterns110R and110S may not be in direct contact with the solder balls500.

The redistribution substrate100C may further include under-bump patterns155R and155S. The under-bump patterns155R and155S may be provided in the lowermost dielectric layer107. The under-bump patterns155R and155S may be provided between the solder balls500and the first conductive patterns110R and110S. The under-bump patterns155R and155S may include redistribution under-bump patterns155R and a signal under-bump pattern155S. The signal under-bump pattern155S may be provided on a bottom surface of the first signal pattern110S that corresponds thereto. The redistribution under-bump patterns155R may be provided on bottom surfaces of the first redistribution patterns110R. The under-bump patterns155R and155S may include a ground under-bump pattern155G. The ground under-bump pattern155G may be provided on a bottom surface of the first ground pattern110G.

FIG.5illustrates a cross-sectional view taken along line I-I′ ofFIG.3A, showing a semiconductor package according to example embodiments.

Referring toFIG.5, a semiconductor package10D may include a redistribution substrate100D, solder balls500, a semiconductor chip200, and a molding layer400. In contrast, the semiconductor package10D may include neither the conductive bumps250nor the under-fill layer410discussed in the examples ofFIGS.1B to1D.

The redistribution substrate100D may include a dielectric layer107, first conductive patterns110R and110S, second conductive patterns120R and120S, and third conductive patterns130R and130S. The dielectric layer107, the first conductive patterns110R and110S, the second conductive patterns120R and120S, and the third conductive patterns130R and130S may be substantially the same as those discussed in the examples ofFIGS.3A to3C. Alternatively, the first conductive patterns110R and110S, the second conductive patterns120R and120S, and the third conductive patterns130R and130S may be substantially the same as those discussed in the examples ofFIGS.1A to1GorFIGS.2A to2C. However, the redistribution substrate100D may not include the conductive pads150R and150S.

The redistribution substrate100D may be in direct contact with the semiconductor chip200and the molding layer400. For example, the uppermost dielectric layer107may be directly in physical contact with a bottom surface of the semiconductor chip200and a bottom surface of the molding layer400. The third conductive patterns130R and130S may be directly coupled to the chip pads205. Each of the third conductive patterns130R and130S may include a third wire portion and a third via portion that is provided in the uppermost dielectric layer107and is on a top surface of the third wire portion. Each of the second conductive patterns120R and120S may include a second wire portion and a second via portion that is provided on a top surface of the second wire portion. Each of the first conductive patterns110R and110S may include a first wire portion and a first via portion that is provided on a top surface of the first wire portion.

The solder balls500may be provided on bottom surfaces of the first conductive patterns110R and110S. For example, the solder balls500may be in direct contact with bottom surfaces of the first conductive patterns110R and110S. Alternatively, under-bump patterns (see under-bump patterns155R and155S ofFIG.4) may further be interposed between the solder balls500and the first conductive patterns110R and110S.

The semiconductor package10D may be fabricated by a chip-first process, but the present inventive concepts are not limited thereto.

FIG.6illustrates a cross-sectional view taken along line I-I′ ofFIG.3A, showing a semiconductor package according to example embodiments.

Referring toFIG.6, a semiconductor package10E may include a redistribution substrate100E, solder balls500, a semiconductor chip200, and a molding layer400. The semiconductor package10E may further include conductive bumps250and an under-fill layer410.

The redistribution substrate100E may include a dielectric layer107, first conductive patterns110R and110S, second conductive patterns120R and120S, third conductive patterns130R and130S, and conductive pads150R and150S, and may further include fourth conductive patterns140R and140S. The first conductive patterns110R and110S, the second conductive patterns120R and120S, and the third conductive patterns130R  and130S may be substantially the same as or similar to those discussed in the examples ofFIGS.1A to1G.

The fourth conductive patterns140R and140S may be interposed between the first conductive patterns110R and110S and the second conductive patterns120R and120S, respectively. The fourth conductive patterns140R and140S may each include a fourth via portion and a fourth wire portion. The fourth via portion may be provided in a corresponding dielectric layer107. The fourth via portion may contact a top surface of a corresponding one of the first conductive patterns110R and110S. The fourth wire portion may be provided on a top surface of the corresponding dielectric layer107. For example, the fourth wire portion may be in contact with the top surface of the dielectric layer107. The fourth via portion and the fourth wire portion may be connected to each other without an interface therebetween. For example, the fourth wire portion and the fourth via portion may be in material continuity with one another. The fourth conductive patterns140R and140S may include metal, such as copper.

The fourth conductive patterns140R and140S may include fourth signal patterns140S and fourth redistribution patterns140R. The fourth signal pattern140S may be provided between and coupled to a corresponding first signal pattern110S and corresponding third signal patterns130S. Although not shown, the fourth signal pattern140S may include a pair of neighboring fourth signal patterns140S. The pair of fourth signal patterns140S may be a portion of the signal pair pattern SP. For example, the signal pair pattern SP may include first, second, third, and fourth signal patterns110S,120S,130S, and140S. A planar arrangement of the pair of fourth signal patterns140S may be substantially the same as that of the pair of second signal patterns120S depicted inFIG.1F. However, the planar arrangement of the pair of fourth signal patterns140S is variously changed without being limited thereto.

The fourth redistribution patterns140R may be provided between and coupled to the first redistribution patterns110R and the third redistribution patterns130R. The fourth redistribution patterns140R may be laterally spaced apart and electrically insulated from the fourth signal pattern140S. The fourth redistribution patterns140R may not vertically overlap the first signal pattern110S.

The fourth redistribution patterns140R may include fourth signal redistribution patterns and/or a fourth ground pattern140G. The fourth signal redistribution pattern may transfer an electric signal different from that transmitted by the fourth signal pattern140S.

The fourth ground pattern140G may be interposed between the first ground pattern110G and the third ground pattern130G. The fourth ground pattern140G may be laterally spaced apart from the fourth signal redistribution pattern. The fourth ground pattern140G may have a lower opening1490. For example, the lower opening1490may penetrate top and bottom surfaces of the fourth ground pattern140G. A planar arrangement of the fourth ground pattern140G, the lower opening1490, and the first signal pattern110S may be substantially the same as that of the second ground pattern120G, the opening1290, and the first signal pattern110S, respectively, depicted inFIG.2A. For example, when viewed in plan, the lower opening1490may overlap the fourth signal pattern140S. When viewed in plan, the lower opening1490may have a size greater than that of the fourth signal pattern140S. As the fourth ground pattern140G has the lower opening1490, the first signal patterns110S may not vertically overlap the fourth ground pattern140G. A first horizontal interval B1and a second horizontal interval B2may be greater than a second vertical interval C2. Therefore, the signal pair pattern SP may improve in impedance characteristics and electrical properties. The first horizontal interval B1, the second horizontal interval B2, and the second vertical interval C2may be substantially the same as those discussed in the examples ofFIGS.2A to2D.

The lower opening1490may expose inner sidewalls of the fourth ground pattern140G. The inner sidewalls of the fourth ground pattern140G may be vertically aligned with sidewalls of the first redistribution patterns110R. The sidewalls of the first redistribution patterns110R may be directed toward and adjacent to the first signal pattern110S.

The fourth ground pattern140G may not vertically overlap any of the first and third signal patterns110S and130S. Alternatively, the fourth ground pattern140G may vertically overlap one of the first and third signal patterns110S and130S, and may not overlap the other of the first and third signal patterns110S and130S. Dissimilarly, the fourth ground pattern140G may vertically overlap the first and third signal patterns110S and130S.

The third signal patterns130S may not vertically overlap the second redistribution patterns120R and may vertically overlap the fourth redistribution patterns140R. A third vertical interval C3between the third signal patterns130S and the fourth redistribution patterns140R may be greater than the first horizontal interval A1and the second horizontal interval A2.

According to some embodiments, the second ground pattern120G may not vertically overlap any of the third and fourth signal patterns130S and140S. Alternatively, the third ground pattern130G may vertically overlap one of the third and fourth signal patterns130S and140S, and may not vertically overlap the other of the third and fourth signal patterns130S and140S. Dissimilarly, the second ground pattern120G may vertically overlap the third and fourth signal patterns130S and140S.

FIG.7illustrates a cross-sectional view showing a semiconductor package according to example embodiments.

Referring toFIG.7, a semiconductor package10F may be a lower semiconductor package. The semiconductor package10F may include a redistribution substrate100B′, solder balls500, a semiconductor chip200, a conductive structure310, and a molding layer400. The semiconductor package10F may further include conductive bumps250and an under-fill layer410. The redistribution substrate100B′ may be substantially the same as the redistribution substrate100B ofFIGS.3A to3C. Alternatively, the redistribution substrate100B′ may be substantially the same as the redistribution substrate100ofFIGS.1A to1G, the redistribution substrate100A ofFIGS.2A to2D, the redistribution substrate100C  ofFIG.4C, the redistribution substrate100D ofFIG.5, or the redistribution substrate100E ofFIG.6.

The conductive structure310may be disposed on the redistribution substrate100B and coupled to a corresponding one of conductive pads150R and150S. When viewed in plan, the conductive structure310may be provided on an edge region of the redistribution substrate100B′. The conductive structure310may be disposed laterally spaced apart from the semiconductor chip200. A metal pillar may be provided on the redistribution substrate100B′ to form the conductive structure310. For example, the conductive structure310may be a metal pillar. The conductive structure310may be electrically connected through the redistribution substrate100B′ to the semiconductor chip200or the solder balls500. The conductive structure310may include metal, such as copper. The conductive structure310may include a plurality of conductive structures that are spaced apart from each other. For brevity of description, the following will discuss a single conductive structure310.

The molding layer400may cover sidewalls of the conductive structure310. The molding layer400may have an outer sidewall aligned with that of the redistribution substrate100B′. The molding layer400may expose a top surface of the conductive structure310. For example, the top surface of the conductive structure310may be coplanar with a top surface of the molding layer400.

The semiconductor package10F may further include an upper redistribution layer600. The upper redistribution layer600may be provided on a top surface of the molding layer400and a top surface of the conductive structure310. A lower surface of the upper redistribution layer600may contact the top surfaces of the molding layer400and the conductive structure310. The upper redistribution layer600may include upper dielectric layers610, upper redistribution patterns620, and upper bonding pads640. The upper dielectric layers610may be stacked on the molding layer400. The upper dielectric layers610may include an organic material, such as a photo-imageable polymer or a solder resist. Each of the upper redistribution patterns620may include a via portion and a wire portion. The via portion of each of the upper redistribution patterns620may be provided in a corresponding upper dielectric layer610. The wire portion of each of the upper redistribution patterns620may be provided between the upper dielectric layers610. For example, the wire portion of each of the upper redistribution patterns620may be in contact with the top surface of a corresponding one of the upper dielectric layers610. The via portion and the wire portion of each of the upper redistribution patterns620may be connected to each other without an interface therebetween. For example, the via portion and the wire portion of each of the upper redistribution patterns620may be in material continuity with one another. The upper redistribution patterns620may include metal, such as copper. At least one of the upper redistribution patterns620may be in contact with a top surface of the conductive structure310that corresponds thereto. The upper bonding pads640may be disposed on or in an uppermost one of the upper dielectric layers610and may be coupled to the upper redistribution patterns620. The upper bonding pads640may be electrically connected through the upper redistribution patterns620and the conductive structures310to the solder balls500or the semiconductor chip200. As the upper redistribution patterns620are provided, at least one of the upper bonding pads640may not be vertically aligned with the conductive structure310electrically connected thereto.

FIG.8illustrates a cross-sectional view showing a semiconductor package according to example embodiments.

Referring toFIG.8, a semiconductor package10G may be a lower semiconductor package. The semiconductor package10G may include a redistribution substrate100B′, solder balls500, a semiconductor chip200, a connection substrate300, and a molding layer400. The semiconductor package10G may further include at least one selected from conductive bumps250, an under-fill layer410, a connection bump252, and an under-fill pattern420. The redistribution substrate100B′ may be substantially the same as the redistribution substrate100B ofFIGS.3A to3C. Alternatively, the redistribution substrate100B′ may be substantially the same as the redistribution substrate100ofFIGS.1A to1G, the redistribution substrate100A ofFIGS.2A to2D, the redistribution substrate100D ofFIG.5, or the redistribution substrate100E ofFIG.6.

The connection substrate300may be disposed on the redistribution substrate100B′. The connection substrate300may have a substrate hole390that penetrates therethrough. For example, the substrate hole390may be formed to penetrate top and bottom surfaces of a printed circuit board, which may manufacture the connection substrate300. When viewed in plan, the substrate hole390may be formed on a central portion of the redistribution substrate100B′. The semiconductor chip200may be disposed in the substrate hole390of the connection substrate300. The semiconductor chip200may be disposed spaced apart from an inner sidewall of the connection substrate300.

The connection substrate300may include a base layer330and a conductive structure310. The substrate hole390may penetrate the base layer330. Differently from that shown, in some embodiments, the base layer330may include a plurality of stacked layers. The base layer330may include a dielectric material. For example, the base layer330may include a carbon-based material, a ceramic, or a polymer. The conductive structure310may be provided in the base layer330. The connection substrate300may further include a first pad311and a second pad312. The first pad311may be disposed on a bottom surface of the conductive structure310. The second pad312may be disposed on a top surface of the conductive structure310. The second pad312may be electrically connected through the conductive structure310to the first pad311. The conductive structure310, the first pad311, and the second pad312may include, for example, at least one selected from copper, aluminum, tungsten, titanium, tantalum, iron, and any alloy thereof.

The connection bump252may be disposed between the redistribution substrate100B′ and the connection substrate300. The connection bump252may be interposed between and coupled to the first pad311and a corresponding one of conductive pads150R and150S. The conductive structure310may be electrically connected through the connection bump252to the redistribution substrate100B′. The connection bump252may include at least one selected from a solder ball, a bump, and a pillar. The connection bump252may include a metallic material. The under-fill pattern420may be provided in a gap between the redistribution substrate100B′ and the connection substrate300, thereby encapsulating the connection bump252. The under-fill pattern420may include a dielectric polymer.

The molding layer400may be provided on the semiconductor chip200and the connection substrate300. The molding layer400may be interposed between the semiconductor chip200and the connection substrate300. According to some embodiments, an adhesive dielectric film may be attached to a top surface of the connection substrate300, a top surface of the semiconductor chip200, and sidewalls of the semiconductor chip200, forming the molding layer400. For example, an Ajinomoto build-up film (ABF) may be used as the adhesive dielectric film. For another example, the molding layer400may include a dielectric polymer, such as an epoxy-based polymer. The molding layer400may include a different material from that of the under-fill pattern420. Alternatively, the under-fill pattern420may be omitted, and the molding layer400may further extend into a gap between the redistribution substrate B′ and the connection substrate300.

The semiconductor package10G may further include an upper redistribution layer600. The upper redistribution layer600may be disposed on the molding layer400and the connection substrate300. The upper redistribution layer600may include upper dielectric layers610, upper redistribution patterns620, and upper bonding pads640. The upper dielectric layers610, the upper redistribution patterns620, and the upper bonding pads640may be substantially the same as those discussed above in the example ofFIG.7. However, at least one of the upper redistribution patterns620may further extend into the molding layer400, thereby being coupled to the second pad312.

Alternatively, the semiconductor package10G may include the redistribution substrate100C ofFIG.4. In this case, the conductive bumps250, the connection bump252, and the under-fill pattern420may be omitted from the semiconductor package10G.

FIG.9illustrates a cross-sectional view showing a semiconductor package according to example embodiments.

Referring toFIG.9, a semiconductor package11may include a lower semiconductor package10F′ and an upper semiconductor package20. The lower semiconductor package10F′ may be substantially the same as the semiconductor package10F discussed in the example ofFIG.7. For example, the lower semiconductor package10F′ may include a redistribution substrate100B′, solder balls500, a semiconductor chip200, a conductive structure310, a molding layer400, and an upper redistribution layer600. The lower semiconductor package10F′ may further include conductive bumps250and an under-fill layer410. Alternatively, the lower semiconductor package10F′ may be substantially the same as the semiconductor package10G ofFIG.8.

The upper semiconductor package20may be provided on the lower semiconductor package10F′. The upper semiconductor package20may include an upper substrate710, an upper semiconductor chip720, and an upper molding layer740. The upper substrate710may be disposed on and spaced apart from a top surface of the upper redistribution layer600. The upper substrate710may be a printed circuit board (PCB) or a redistribution layer. The upper substrate710may include first substrate pads701, second substrate pads702, and metal lines705. The first substrate pads701and the second substrate pad702may be respectively disposed on a bottom surface and a top surface of the upper substrate710. The metal lines705may be provided in the upper substrate710, and may be coupled to the first substrate pads701and the second substrate pads702.

The upper semiconductor chip720may be mounted on the top surface of the upper substrate710. The upper semiconductor chip720may be of a different type from the semiconductor chip200. For example, the semiconductor chip200may be a logic chip, and the upper semiconductor chip720may be a memory chip.

The upper semiconductor chip720may include upper chip pads725and second integrated circuits (not shown). The second integrated circuits may be provided in the upper semiconductor chip720. The upper chip pads725may be provided on a bottom surface of the upper semiconductor chip720and may be couple do the second integrated circuits. The upper chip pads725may include, for example, metal. The upper semiconductor package20may further include upper bumps750. The upper bumps750may be provided between the upper substrate710and the upper semiconductor chip720and may be coupled to the second substrate pads702and the upper chip pads725. The upper bumps750may include a solder material.

Connection solder balls670may be disposed between the upper redistribution layer600and the upper substrate710. For example, the connection solder balls670may be provided between and coupled to the upper bonding pads640and the first substrate pads701. Therefore, the upper semiconductor chip720may be electrically connected through the connection solder balls670to the semiconductor chip200or the solder balls500.

The upper molding layer740may be provided on the upper substrate710to cover the upper semiconductor chip720. The upper molding layer740may expose a top surface of the upper semiconductor chip720, but the present inventive concepts are not limited thereto. For example, the upper molding layer740may cover the top surface of the upper semiconductor chip720. The upper molding layer740may include a dielectric polymer, such as an epoxy-based molding compound.

The upper semiconductor package20may further include a thermal radiation structure790. The thermal radiation structure790may be disposed on the top surface of the upper semiconductor chip720and on a top surface of the upper molding layer740. The thermal radiation structure790may contact the top surface of the upper semiconductor chip720and/or the top surface of the upper molding layer740. Although not illustrated, in some embodiments, the thermal radiation structure790may further extend onto a lateral surface of the upper molding layer740. The thermal radiation structure790may include a heat sink, a heat slug, or a thermal interface material (TIM) layer. The thermal radiation structure790may include, for example, metal.

It will be understood that, although the terms “first”, “second”, “third”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one region, layer, or section from another region, layer, or section. For example, a component called “first conductive patterns” in one embodiment will be referred to as “third conductive patterns” in other embodiments or claims. In addition, a component called “third conductive patterns” in one embodiment will be referred to as “first conductive patterns” in other embodiments or claims.

According to the present inventive concepts, there may be included a signal pair pattern of a redistribution substrate. The signal pair pattern may improve in impedance characteristics and increase in electrical properties. Accordingly, a semiconductor package may enhance in electrical properties.

Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

It will be appreciated that “planarization,” “co-planar,” “planar,” etc., as used herein, refer to structures (e.g., surfaces) that need not be perfectly geometrically planar, but may include acceptable variances that may result from standard manufacturing processes. The term “contact,” as used herein, refers to a direct connection (i.e., touching) unless the context indicates otherwise.

This detailed description of the present inventive concepts should not be construed as limited to the embodiments set forth herein, and it is intended that the present inventive concepts cover the various combinations, the modifications and variations of this invention without departing from the spirit and scope of the present inventive concepts.