Semiconductor layered device with data bus inversion

Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

BACKGROUND

High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking chips (e.g., dies) vertically and interconnecting the chips using through substrate vias (TSVs). Benefits of the 3D memory devices include shorter interconnects which reduce circuit delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM), and a wide-I/O dynamic random access memory (DRAM).

For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance DRAM interface chip and vertically stacked DRAM chips. A typical HBM stack of four DRAM chips (e.g., core chips) has two 128-bit channels per chip for a total of eight input/output channels and a width of 1024 bits in total. An interface (IF) chip of the HBM provides an interface with the eight input/output channels, which function independently of each other. In the HBM, data transmission between chips (e.g., between an interface chip and core chips) via through substrate vias (TSVs) may cause high power consumption, due to current charge and discharge at the TSVs as capacitors.

3D memory devices (e.g., HBM and the like) support data bus inversion (“DBI”) during write and read operation for reducing currents in data transmission between a host controller and chips (e.g., dies) via a data bus. One of DBI algorithms, DBI-AC algorithm, is used to limit the number of simultaneously transitioning data bits (e.g., a half of bits or fewer) across the width of the interface. Under the DBI-AC algorithm, all the bits of current data to be transmitted are inverted in logic level prior to transmission of the current data, if a majority of bits of the current data are different in logic level from previous data (e.g., immediately preceding data) transmitted one data transmission cycle before the current data without inversion. If the previous data was transmitted with inversion, however, the current data is transmitted as is, even if the majority of bits of the current data are different in logic level from the previous data.

DBI calculation is performed to detect whether the majority bits of the current data are different in logic level from the previous data. Based on the majority bits' transitions based on the DBI calculation result and previous execution status of the DBI operation, a DBI bit indicating whether the DBI is executed on the current data. InFIG. 1A, the DBI bit represents “1,” if the majority bits of the current data are different in logic level from the previous data and the DBI was not executed on the previous data, and the DBI bit represents “0” if the majority of the bits of the current data are the same in logic level from the previous data. As shown inFIG. 1B, a DBI circuit1for data read path executes the DBI-AC algorithm and provides the current data with or without DBI and a DBI bit onto data bus. A data bus transmits each data from DRAM core in synchronous to a read clock signal READ. In response to each cycle of the read clock signal READ, a D-type flip-flop circuit11captures a data (DQ) and a DBI bit and provides the captured data (DQ) as previous data which with one cycle delay and the DBI bit and to a DBI calculator12that is a comparator. The DBI calculator12receives the current data from the DRAM core and the previous data that is the data one cycle before the current data from the flip-flop circuit11. The DBI calculator12compares the previous data and the current data to determine whether a majority of bits in the data are different in logic level from the previous data (e.g., the number of bits showing difference is greater than four bits, if the width of the data bus is eight bits), and provides a DBI calculation result bit to a logic AND circuit13. The logic AND circuit13receives the DBI calculation result and a DBI enable/disable bit from a mode register and provides the DBI bit to a logic XOR circuit14. The DBI bit is active (e.g., “1”) when both the DBI calculation result is indicative of the majority of bits in the current data being different from the previous data and the DBI enable/disable bit is indicative of the DBI operation enabled. The logic XOR circuit14executes inversion of the current data if the DBI bit is active (e.g., “1”), thus the DBI circuit1provides a combination of the inverted current data DQ and the DBI bit “1,” or a combination of the current data DQ and the DBI bit “0.” The DBI calculation is supposed to be executed within one cycle of the read clock signal READ; however, completion of DBI calculation takes relative long time because the DBI calculator12is composed of a large number of logic gates. Thus, a cycle of the read clock signal READ has been required to be sufficiently long to complete the DBI computation, and thus a data transfer speed with the DBI operations has been suppressed.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments of the disclosure may be practiced. The specification provides sufficient detail to enable those skilled in the art to practice embodiments of the disclosure. Other embodiments may be utilized, and structure, logical and electrical changes may be made without departing from the scope of the disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

FIG. 2Ais a schematic diagram of a DBI circuit2in accordance with an embodiment of the present disclosure.FIG. 2Bis a timing diagram of signals in the DBI circuit2during a DBI operation in accordance with an embodiment of the present disclosure. The DBI circuit2may include a plurality of DBI FIFO A circuits <7:0>21aand a plurality of DBI FIFO B circuits <7:0>21bprovided for each bit of an input data, a DBI calculator A22aand a DBI calculator B22b. For example, a DBI calculation cycle (tDBI) in the DBI calculators A and B22aand22bmay be between one clock cycle (1tCK) and two clock cycles (2tCK) of a read clock signal READ. The plurality of DBI FIFO A circuits <7:0>21aand the plurality of DBI FIFO B circuits <7:0>21bboth may receive corresponding bits of data (e.g., in order of D0, D1, D2, D3, D4, D5, D6, D7) from an input data bus, such as RW-bus [7:0] respectively at every read clock cycle (1tCK) of the read clock signal READ. The plurality of DBI FIFO A circuits <7:0>21aand the plurality of DBI FIFO B circuits <7:0>21bmay receive pointer signals PointerA and PointerB respectively. The PointerA signal and the PointerB signal are periodic signals that may have a pulse width of one clock cycle (=1tCK) of the read clock signal READ, and they are complementary to each other. Thus, PointerA signal and the PointerB signal may alternate their active states (e.g., a logic high level) and data may be latched at every other cycles (e.g., odd cycles only, or even cycles only) by the pointer signals PointerA and PointerB. The DBI calculator A22aand the DBI calculator B22bmay perform DBI calculation to detect whether the majority bits of the current data are different in logic level from the previous data. The DBI calculator B22bmay include similar components in a similar structural configuration as the DBI calculator A22a, and detailed illustration of the DBI calculator B22bis omitted inFIG. 2A.

Each DBI FIFO A circuit of the plurality of DBI FIFO A circuits <7:0>21aincludes a flip-flop circuit211a, a bit inverter (e.g., exclusive-OR (XOR) gate)212a, a flip-flop circuit213a, and a NAND circuit214a. Each DBI FIFO A circuit of the plurality of DBI FIFO A circuits <7:0>21amay also include a delay circuit DL_tDBI215aas shown inFIG. 2A. Each DBI FIFO B circuit of the plurality of DBI FIFO B circuits <7:0>21bincludes a flip-flop circuit211b, a bit inverter (e.g., XOR gate)212b, a flip-flop circuit213b, and a NAND circuit214b. Each DBI FIFO B circuit of the plurality of DBI FIFO B circuits <7:0>21bmay also include a delay circuit DL_tDBI215bas shown inFIG. 2A. The plurality of DBI FIFO A circuits <7:0>21aand the plurality of DBI FIFO B circuits <7:0>21bmay provide FIFO output signals to a plurality of output circuits23, in synchronous to DBI bit signals by holding for a number of clock cycles of the read clock signal READ corresponding to DBI calculation time (tDBI).

For example, the flip-flop circuits21bof the DBI FIFO B circuits <7:0>21bmay latch corresponding bits of the data on the corresponding RW-bus[7:0] at even cycles (e.g., D0, D2, D4, D6inFIG. 2B) responsive to the PointerB signal in the active state (e.g., at a logic high level), and provide latched data signals DBIB[7:0]. The bit inverter212bof each DBI FIFO B circuit21bmay receive a corresponding bit of the latched data signals DBIB[7:0] and a current DBI calculation result signal DBIresB from a comparator circuit25bcoupled to the DBI calculator B22b. If the current DBI calculation result signal DBIresB is active, the bit inverter212bmay provide an inverted bit of the corresponded bit of the latched data signals DBIB[7:0]. If the current DBI calculation result signal DBIresB is inactive (e.g., at a logic low level), the bit inverter212bmay provide the corresponded bit of the latched data signals DBIB[7:0]. The flip-flop circuit213bof each DBI FIFO B circuit21bmay latch an output signal of the bit inverter212band the NAND circuit214bof each DBI FIFO B circuit21bmay provide an inverted signal of the output signal of the bit inverter212bas a FIFO output signal, if the pointer signal PointerB is in the active state. If the DBI FIFO B circuit21bincludes the delay circuit DL tDBI circuit215b, the delay circuit DL_tDBI circuit215bmay provide a delayed pointer signal PointerB′ that may have a delay of the DBI calculation cycle (tDBI) with reference to the pointer signal PointerB instead of the pointer signal PointerB to the flip-flop circuit213band the NAND circuit214b.

Similarly, the flip-flop circuits211aof the DBI FIFO A circuits <7:0>21amay latch corresponding bits of the data on the corresponding RW-bus[7:0] at odd cycles (e.g., D1, D3, D5, D7inFIG. 2B), immediately following the corresponding bits of the data on RW-bus[7:0] received by the DBI FIFO B circuits <7:0>21bat even cycles (e.g., D0, D2, D4, D6inFIG. 2B), responsive to the PointerA signal in the active state (e.g., at a logic high level), and provide latched data signals DBIA[7:0]. The bit inverter212aof each DBI FIFO A circuit21amay receive a corresponding bit of the latched data signals DBIA[7:0] and a current DBI calculation result signal DBIresA from a comparator circuit25acoupled to the DBI calculator A22a. If the current DBI calculation result signal DBIresA is active, the bit inverter212amay provide an inverted bit of the corresponded bit of the latched data signals DBIA[7:0]. If the current DBI calculation result signal DBIresA is inactive (e.g., at a logic low level), the bit inverter212amay provide the corresponded bit of the latched data signals DBIA[7:0]. The flip-flop circuit213aof each DBI FIFO A circuit21amay latch an output signal of the bit inverter212a. The NAND circuit214aof each DBI FIFO A circuit21amay provide an inverted signal of the output signal of the bit inverter212aas the FIFO output signal if the pointer signal PointerA is in the active state. If the DBI FIFO A circuit21aincludes the delay circuit DL_tDBI circuit215a, the delay circuit DL_tDBI circuit215amay provide a delayed pointer signal PointerA′ that may have a delay of a DBI calculation cycle (tDBI) with reference to the pointer signal PointerA instead of the pointer signal PointerA to the flip-flop circuit213aand the NAND circuit214a. The plurality of output circuits23may receive the FIFO output signals of the corresponding NAND circuits214aand214band provide data output signals Dout [7:0].

The DBI calculator A22amay receive the latched data signals DBIA[7:0] from the flip-flop circuits211aof the DBI FIFO A circuits <7:0>21a. The DBI calculator A22amay also receive data signals b[7:0] from a plurality of flip-flop circuits24a. The plurality of flip-flop circuits24amay receive the latched data signals DBIB[7:0] from the flip-flop circuits21bof the DBI FIFO B circuits <7:0>21band the pointer signal PointerA, and latch the latched data signals DBIB[7:0] respectively to provide the data signals b[7:0]. The DBI calculator A22amay include a plurality of comparator circuits221a. For example, the plurality of comparator circuits221amay be XOR circuits. Each comparator circuit of the plurality of comparator circuits221amay receive a corresponding bit of the data signals b[7:0] and a corresponding bit of the latched data signals DBIA[7:0] and provide a result signal for each corresponding bit. For example, the result signal may be an active state (e.g., “1” or a logic high level), if the corresponding bit of the data signals b[7:0] and the corresponding bit of the latched data signals DBIA[7:0] are different, which indicates that the corresponding bits of the previous data and the current data are different. Similarly, the result signal may be an inactive state (e.g., “0” or a logic low level), if the corresponding bit of the data signals b[7:0] and the corresponding bit of the latched data signals DBIA[7:0] are the same, which indicates that the corresponding bits of the previous data and the current data are the same. The DBI calculator A22amay include an adder circuit222a. For example, the adder circuit222amay be an OR circuit. The adder circuit222amay receive calculation signals after calculations based on the result signals from the plurality of comparator circuits221aand may provide a DBI calculation signal DBI_calcA. Calculations based on the result signals will be described in detail with reference toFIG. 3. The comparator circuit25amay receive the DBI calculation signal DBI_calcA and a previous DBI calculation result signal DBIrespreB from a flip-flop circuit26bbased on DBI calculation by the DBI calculator B22b. If the DBI calculation signal DBI_calcA and the previous DBI calculation result signal DBIrespreB are different, the comparator circuit25amay provide the current DBI calculation result signal DBIresA in an active state (e.g., “l” or a logic high level). If the DBI calculation signal DBI_calcA and the previous DBI calculation result signal DBIrespreB are the same, the comparator circuit25amay provide the current DBI calculation result signal DBIresA in an inactive state (e.g., “0” or a logic low level). A flip-flop circuit26amay receive the current DBI calculation result signal DBIresA and latch the current DBI calculation result signal DBIresA with the pointer signal PointerA or the delayed pointer signal PointerA′ and may provide the latched current DBI calculation result signal DBIresA as a previous DBI calculation result signal DBIrespreA.

Similarly, the DBI calculator B22bmay receive the latched data signals DBIB[7:0] from the flip-flop circuits211bof the DBI FIFO B circuits <7:0>21b. The DBI calculator B22bmay also receive data signals a[7:0] from a plurality of flip-flop circuits24bthat may function as a plurality of pre-DBI latch circuits. The plurality of flip-flop circuits24bmay receive the latched data signals DBIA[7:0] from the flip-flop circuits211aof the DBI FIFO A circuits <7:0>21aand the pointer signal PointerB, and latch the latched data signals DBIA[7:0] respectively to provide the data signals a[7:0]. The DBI calculator B22bmay include a plurality of comparator circuits221b. For example, the plurality of comparator circuits221bmay be XOR circuits. Similarly, each comparator circuit of the plurality of comparator circuits221bmay receive a corresponding bit of the data signals a[7:0] and a corresponding bit of the latched data signals DBIB[7:0] and provide a result signal for each corresponding bit, such that the result signal may be the active state (e.g., “1” or the logic high level), if the corresponding bit of the data signals a[7:0] and the corresponding bit of the latched data signals DBIB[7:0] are different and the result signal may be the inactive state (e.g., “0” or the logic low level), if the corresponding bit of the data signals a[7:0] and the corresponding bit of the latched data signals DBIB[7:0] are the same. The DBI calculator B22bmay include an adder circuit222b. For example, the adder circuit222bmay be an OR circuit. The adder circuit222bmay receive calculation signals after calculations based on the result signals from the plurality of comparator circuits221band may provide a DBI calculation signal DBI_calcB. Calculations based on the result signals will be described in detail with reference toFIG. 3. The comparator circuit25bmay receive the DBI calculation signal DBI_calcB and a previous DBI calculation result signal DBIrespreA from the flip-flop circuit26abased on DBI calculation of the DBI calculator A22a. If the DBI calculation signal DBI_calcB and the previous DBI calculation result signal DBIrespreA are different, the comparator circuit25bmay provide the current DBI calculation result signal DBIresB in an active state (e.g., “1” or the logic high level). If the DBI calculation signal DBI_calcB and the previous DBI calculation result signal DBIrespreA are the same, the comparator circuit25bmay provide the current DBI calculation result signal DBIresB in an inactive state (e.g., “0” or a logic low level). A flip-flop circuit26bmay receive the current DBI calculation result signal DBIresB and latch the current DBI calculation result signal DBIresB with the pointer signal PointerB or the delayed pointer signal PointerB′ and may provide the latched current DBI calculation result signal DBIresB as the previous DBI calculation result signal DBIrespreB.

The DBI circuit2may also include a DBI output circuit27. The DBI output circuit27may receive the current DBI calculation result signals DBIresA and DBIresB and the pointer signals PointerA and PointerB or the delayed pointer signals PointerA′ and PointerB′. The DBI output circuit27may provide DBIresA as a DBI bit signal responsive to the pointer signal PointerA (or the delayed pointer signal PointerA′) and may provide DBIresB as the DBI bit signal responsive to the pointer signal PointerB (or the delayed pointer signal PointerB′). Because the pointer signals PointerA and PointerB, or the delayed pointer signals PointerA′ and PointerB′ are complementary periodic signals, either DBIresA or DBIresB may be provided as the DBI bit signal at odd cycles or even cycles, respectively.

FIG. 3is a DBI calculator circuit3in accordance with an embodiment of the present disclosure. For example, the DBI calculator circuit3may be used as the DBI calculator circuits22aand22binFIG. 2A. The DBI calculator circuit3may perform DBI calculation to detect whether the majority bits of the current data are different in logic level from the previous data. The DBI calculator circuit3may include an input stage31, an intermediate stage32and an output stage33. The input stage31of the DBI calculator circuit3may include a plurality of comparator circuits311ato311dfor corresponding bits (e.g., Da[3:0]) of current data and corresponding bits (e.g., Db[3:0]) of the previous data. For example, the plurality of comparator circuits311ato311dmay be logic XOR circuits. For example, a comparator circuit311amay receive Da[0] bit of the current data and Db[0] bit of the previous data and provide a change bit C[0] indicative of whether a corresponding bit D[0] is changed from the previous data to the current data. The change bit C[0] is in an active state (e.g., a logic high level) if the corresponding bit D[0] is changed, because Da[0] bit of the current data and Db[0] bit of the previous data are different. Similarly, comparator circuits311bto311dmay compare Da[1:3] bits and Db[1:3] bits and provide C[1:3] representing whether corresponding bits D[1:3] are changed. The input stage31of the DBI calculator circuit3may also include logic circuits312ato312d. For example, the logic circuit312amay be a logic NOR circuit which may receive C[0] and C[1] and may provide an intermediate signal a1that is a NOR operation of C[0] and C[1] indicating whether any of the bits D[0:1] is changed. For example, the intermediate signal a1represents “1 (=at logic high level)” if none of the bits D[0:1] is changed. The logic circuit312bmay be a logic NAND circuit which may receive C[0] and C[1] and may provide an intermediate signal b1that is a NAND operation of C[0] and C[1] indicating whether all the bits D[0:1] is changed. For example, the intermediate signal b1represents “1” if any of the bits D[0:1] is unchanged. Similarly, the logic circuit312cand the logic circuit312dmay be a logic NOR circuit and a logic NAND circuit which may receive C[2] and C[3] and may provide intermediate signals a2and b2that are a NOR operation and a NAND operation of C[2] and C[3].

The intermediate stage32of the DBI calculator circuit3may include a plurality of logic circuits321ato321d. The logic circuit321amay receive the intermediate signals a1and a2, invert the intermediate signals a1and a2, and execute an NOR operation to the inverted intermediate signals a1′ and a2′ to provide another intermediate signal A1that is indicative whether none of the bits D[0:3] is changed (e.g., A1represents “I” if none of the bits D[0:3] is changed). The logic circuit321bmay receive the intermediate signals a1, a2, b1and b2, invert the intermediate signals b1and b2, execute an NOR operation to the intermediate signals a1and a2, and may further execute an NOR operation of the inverted intermediate signals of b1and b2and the NOR value of the intermediate signals a1and a2to provide another intermediate signal B1that is indicative whether a number of bits changed in the bits D[0:3] is limited to 1 (e.g., B1represents “1” if the number of changed bits is 0 or 1). The logic circuit321cmay receive the intermediate signals a1, a2, b1and b2, execute an NOR operation to the intermediate signals a1and b2, execute another NOR operation to the intermediate signals a2and b1, and further execute an NOR operation to the NOR value the intermediate signals a1and b2and the NOR value of the intermediate signals a2and b1and provide another intermediate signal C1that is indicative whether the number of bits changed in the bits D[0:3] is limited to 2 (e.g., C1represents “1” if the number of changed bits is either 0, 1 or 2). The logic circuit321dmay receive the intermediate signals b1and b2, execute an NOR operation to the intermediate signals b1and b2, and further invert the NOR value and provide the inverted NOR value as another intermediate signal D1that is indicative whether the number of bits changed in the bits D[0:3] is limited to 3 (e.g., C1represents “0” if the number of changed bits is 4). Thus, the intermediate signals A1, B1, C1and D1may represent whether the number of bits changed in the bits D[0:3] is limited to 0, 1, 2 and 3, respectively. Similarly, from Da[7:4] and Db[7:4], the input stage31may provide the intermediate signals c1, c2, d1and d2and the intermediate stage32may provide intermediate signals A2, B2, C2and D2that may represent whether the number of bits changed in the bits D[4:7] is limited to 0, 1, 2 and 3, respectively.

The output stage33may be an evaluation circuit. For example, the evaluation circuit33may include a plurality of logic circuits331ato331d, another plurality of logic circuits332aand332b, and an output logic circuit (e.g., OR gate)333. For example, the plurality of logic circuits331ato331dmay be logic OR circuits, the plurality of logic circuits332aand332bmay be logic NAND circuits, and the output logic circuit may be a logic OR circuit. The logic circuit331amay receive the intermediate signals A1and D2and provide an OR value of the intermediate signals A1and D2to the logic circuit332a. The logic circuit331bmay receive the intermediate signals B1and C2and provide an OR value of the intermediate signals B1and C2to the logic circuit332a. Similarly, the logic circuit331cmay provide an OR value of the intermediate signals D1and A2to the logic circuit332b, and the logic circuit331dmay provide an OR value of the intermediate signals C1and B2to the logic circuit332b. The logic circuits332aand332bmay execute NAND operations and provide results to the output logic circuit333. The output logic circuit333may receive output signals from the logic circuits332aand332band provide a DBI calculation result signal DBI_calc. For example, the DBI calculation result signal DBI_calc may be in an active state (e.g., a logic high level) if the majority of the bits (e.g., five or more bits) of the current data are different in logic level from the previous data, and the DBI calculation result signal DBI_calc may be in an inactive state (e.g., a logic low level) if the majority of the bits of the current data are not different in logic level from the previous data (e.g., four bits or fewer changed). For example, each comparator of the plurality of comparators311in the input stage31of the DBI calculator circuit3ofFIG. 3may correspond to each comparator of the plurality of comparator circuits221a(or221b) of the DBI calculator A22a(or the DBI calculator B22b) ofFIG. 2A. For example, the output logic circuit333of the output stage33of the DBI calculator circuit3ofFIG. 3may correspond to the adder circuit222a(or the adder circuit222b) of the DBI calculator A22a(or the DBI calculator B22b) ofFIG. 2A.

FIG. 4Ais a schematic diagram of a DBI circuit4in accordance with an embodiment of the present disclosure.FIG. 4Bis a timing diagram of signals in the DBI circuit4during a DBI operation in accordance with an embodiment of the present disclosure. Description of components corresponding to components included inFIG. 2Awill not be repeated and changes fromFIG. 2A, including configuration of a plurality of read/write busses will be described. Unlike the RW-bus[7:0] inFIG. 2Bthat may transmit the data (e.g., in order of D0, D1, D2, D3, D4, D5, D6, D7, D8, . . . ) at every clock cycle (1tCK), there may be a plurality of input data buses, such as RW-busR[7:0] and RW-busF[7:0] inFIG. 4B, both may transmit data of every other data alternatingly every two clock cycles (2tCK) of a read clock signal READ. For example, RW-busR[7:0] may transmit data of odd cycles (e.g., in order of D1, D3, D5, D7, D9, Db, Dd and Df) and RW-busF[7:0] may transmit data of even cycles (e.g., in order of D0, D2, D4, D6, D8, Da, Dc and De). A plurality of DBI FIFO A circuits <7:0>41amay receive corresponding bits of data (e.g., in order of D1, D3, D5, D7, D9, Db, Dd and Df) from RW-busR[7:0] respectively at every other read clock cycle (2tCK) of the read clock signal READ and a plurality of DBI FIFO B circuits <7:0>41bmay receive corresponding bits of data (e.g., in order of D0, D2, D4, D6, D8, Da, Dc and De) from RW-busF[7:0] respectively at every other read clock cycle (2tCK) of the read clock signal READ. The plurality of DBI FIFO A circuits <7:0>41a may include a buffer414a, instead of the NAND circuit214a, that may provide Do_busR[7:0] signals. The plurality of DBI FIFO B circuits <7:0>41bmay include a buffer414b, instead of the NAND circuit214b, that may provide Do_busF[7:0] signals. The DBI circuit4may further include a serializer circuit48that may receive the Do_busR[7:0] signals and Do_busF[7:0] signals and may provide data output signals Dout [7:0] including data on the Do_busR[7:0] signals and data on the Do_busF[7:0] signals alternatingly in series responsive to the read clock signal READ in order of D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, Da, Db, Dc, Dd, De and Df.

FIG. 5Ais a schematic diagram of a DBI circuit5in accordance with an embodiment of the present disclosure.FIG. 5Bis a timing diagram of signals in the DBI circuit5during a DBI operation in accordance with an embodiment of the present disclosure. The DBI circuit5may include a plurality of DBI FIFO A circuits <7:0>51a, a plurality of DBI FIFO B circuits <7:0>51b, a plurality of DBI FIFO C circuits <7:0>51cand a plurality of DBI FIFO D circuits <7:0>51dprovided for each bit of an input data, a DBI calculator A52a, a DBI calculator B52b, a DBI calculator C52cand a DBI calculator D52d. For example, a DBI calculation cycle (tDBI) in the DBI calculators A, B, C and D52a,52b,52cand52dmay be longer than two clock cycles (2tCK) (e.g., between two and three clock cycles) of a read clock signal READ.

The plurality of DBI FIFO A circuits <7:0>51a, the plurality of DBI FIFO B circuits <7:0>51b, the plurality of DBI FIFO C circuits <7:0>51cand the plurality of DBI FIFO B circuits <7:0>51dmay receive corresponding bits of data (e.g., in order of D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, Da, Db, Dc, Dd, De, Df) from RW-bus [7:0] respectively at every read clock cycle (1tCK) of the read clock signal READ. Pointer signals PointerA, PointerB, PointerC and PointerD are periodic signals that may have a periodic cycle of four clock cycles (=4tCK) of a read clock signal READ. The pointer signals PointerA, PointerB, PointerC and PointerD may also have a pulse width of one clock cycle (=1tCK) of the read clock signal READ as an active state (e.g., at a logic high level) for every four clock cycles (4tCK). The pointer signals PointerA, PointerB, PointerC and PointerD may be in the active state in order. For example, a falling edge of the pointer signal PointerA and a rising edge of the pointer signal PointerB occur substantially simultaneously. Similarly, a falling edge of the pointer signal PointerB and a rising edge of the pointer signal PointerC occur substantially simultaneously, a falling edge of the pointer signal PointerC and a rising edge of the pointer signal PointerD occur substantially simultaneously, and a falling edge of the pointer signal PointerD and a rising edge of the pointer signal PointerA occur substantially simultaneously. Each of the plurality of DBI FIFO A circuits <7:0>51a, the plurality of DBI FIFO B circuits <7:0>51b, the plurality of DBI FIFO C circuits <7:0>51cand the plurality of DBI FIFO D circuits <7:0>51dmay receive a combination of pointer signals, one pointer signal that corresponds to the current data, and the other pointer having an active state immediately before the one pointer, which corresponds to the previous data processed by one of the other DBI FIFO circuits. For example, the plurality of DBI FIFO A circuits <7:0>51amay receive the pointer signals PointerD and PointerA, the plurality of DBI FIFO B circuits <7:0>51bmay receive the pointer signals PointerA and PointerB, the plurality of DBI FIFO C circuits <7:0>51cmay receive the pointer signals PointerB and PointerC, and the plurality of DBI FIFO D circuits <7:0>51dmay receive the pointer signals PointerC and PointerD, respectively. The DBI calculators A, B, C and D52a,52b,52cand52dmay perform DBI calculation to detect whether the majority bits of the current data are different in logic level from the previous data. The DBI calculators B, C and D52b,52cand52dmay include similar components in a similar structural configuration as the DBI calculator A52aand detailed illustrations of the DBI calculators B, C and D52b,52cand52dare omitted inFIG. 5A.

Each DBI FIFO A circuit51aof the plurality of DBI FIFO A circuits <7:0>51aincludes a flip-flop circuit511a, a bit inverter512aand a NAND circuit514a. Each DBI FIFO B circuit51bof the plurality of DBI FIFO B circuits <7:0>51bincludes a flip-flop circuit51b, a bit inverter512band a NAND circuit514b. Each DBI FIFO C circuit51cof the plurality of DBI FIFO C circuits <7:0>51cincludes a flip-flop circuit511c, a bit inverter512cand a NAND circuit514c. Each DBI FIFO D circuit51dof the plurality of DBI FIFO D circuits <7:0>51dincludes a flip-flop circuit511d, a bit inverter512dand a NAND circuit514d.

For example, the flip-flop circuits511aof the DBI FIFO A circuits <7:0>51amay latch corresponding bits of the data on the corresponding RW-bus[7:0] at 4×N cycles (e.g., D0, D4, D8and Dc inFIG. 5B), where N is a natural number, responsive to the pointer signal PointerA in the active state (e.g., at a logic high level), and provide latched data signals DBIA[7:0] as shown inFIG. 5B. The bit inverter512aof each DBI FIFO A circuit51amay receive a corresponding bit of the latched data signals DBIA[7:0] and a current DBI calculation result signal DBIresA from a comparator circuit55acoupled to the DBI calculator A52a. If the current DBI calculation result signal DBIresA is active, the bit inverter512amay provide an inverted bit of the corresponded bit of the latched data signals DBIA[7:0]. If the current DBI calculation result signal DBIresA is inactive (e.g., at a logic low level), the bit inverter512amay provide the corresponding bit of the latched data signals DBIA[7:0]. The NAND circuit514amay receive either the corresponding bit or its inverted bit of the latched data signals DBIA[7:0] from the bit inverter512a. The NAND circuit514amay further receive the pointer signal PointerD which has a falling edge (e.g., an end of the active state) coincides as a rising edge (a start of the active state) of the pointer signal PointerA. By using the pointer signal PointerD, a similar effect as providing a pointer signal having a delay of a DBI calculation cycle (tDBI) inFIG. 2Amay be obtained, when the DBI calculation cycle (tDBI), which is longer than the two read clock cycles (>2tCK) and shorter than three read clock cycles (<3tCK). Thus, the NAND circuit514amay provide a logic NAND value of either the corresponding bit or its inverted bit of the latched data signals DBIA[7:0] and the pointer signal PointerD. Thus, the DBI FIFO A circuits <7:0>51amay receive data on RW-bus[7:0] every four cycles (4tCK) responsive to the pointer signal PointerA and may further update output signals every four cycles (4tCK) responsive to the pointer signal PointerD. Similarly, the DBI FIFO B circuits <7:0>51bmay receive data on RW-bus[7:0] every four cycles (4tCK) responsive to the pointer signal PointerB and may further update output signals every four cycles (4tCK) responsive to the pointer signal PointerA, the DBI FIFO C circuits <7:0>51cmay receive data on RW-bus[7:0] every four cycles (4tCK) responsive to the pointer signal PointerC and may further update output signals every four cycles (4tCK) responsive to the pointer signal PointerB, and the DBI FIFO D circuits <7:0>51dmay receive data on RW-bus[7:0] every four cycles (4tCK) responsive to the pointer signal PointerD and may further update output signals every four cycles (4tCK) responsive to the pointer signal PointerC. A plurality of output circuits53may receive output signals of the corresponding DBI FIFO AtoD circuits of the plurality of the DBI FIFO A circuits <7:0>51a, the plurality of the DBI FIFO B circuits <7:0>51b, the plurality of the DBI FIFO C circuits <7:0>51c, the plurality of the DBI FIFO D circuits <7:0>51d, and provide data output signals Dout [7:0].

Description of components corresponding to components included in the DBI calculator A52a, the DBI calculator B52b, the DBI calculator C52cand the DBI calculator D52dis substantially the same as the DBI calculators A and B inFIG. 2Aand will not be repeated and changes fromFIG. 2A, including configuration of latched data signals DBIA, DBIB, DBIC, DBID and pointer signals PointerA, PointerB, PointerC and PointerD will be described. For example, the DBI calculator circuit3ofFIG. 3may be used as the DBI calculator A52a, the DBI calculator B52b, the DBI calculator C52cand the DBI calculator D52d.

The DBI calculator A52amay receive the latched data signals DBIA[7:0] and DBID[7:0] from the flip-flop circuits511aof the DBI FIFO A circuits <7:0>51aand the flip-flop circuits511dof the DBI FIFO D circuits <7:0>51d, respectively. Similarly, the DBI calculator B52bmay receive the latched data signals DBIB[7:0] and DBIA[7:0] from the flip-flop circuits511bof the DBI FIFO B circuits <7:0>51band the flip-flop circuits511aof the DBI FIFO A circuits <7:0>51a, respectively, the DBI calculator C52cmay receive the latched data signals DBIC[7:0] and DBIB[7:0] from the flip-flop circuits511cof the DBI FIFO C circuits <7:0>51cand the flip-flop circuits511bof the DBI FIFO B circuits <7:0>51b, respectively, the DBI calculator D52dmay receive the latched data signals DBID[7:0] and DBIC[7:0] from the flip-flop circuits511dof the DBI FIFO D circuits <7:0>51dand the flip-flop circuits511cof the DBI FIFO C circuits <7:0>51c, respectively.

A comparator circuit55amay receive the DBI calculation signal DBI_calc_A and a previous DBI calculation result signal DBIrespreD from a flip-flop circuit56dbased on DBI calculation of the DBI calculator D52d. If the DBI calculation signal DBI_calc_A and the previous DBI calculation result signal DBIrespreD are different, the comparator circuit55amay provide the current DBI calculation result signal DBIresA in an active state (e.g., “I” or a logic high level). If the DBI calculation signal DBI_calc_A and the previous DBI calculation result signal DBIrespreD are the same, the comparator circuit55amay provide the current DBI calculation result signal DBIresA in an inactive state (e.g., “0” or a logic low level). A flip-flop circuit56amay receive the current DBI calculation result signal DBIresA and latch the current DBI calculation result signal DBIresA with the pointer signal PointerD and may provide the latched current DBI calculation result signal DBIresA as a previous DBI calculation result signal DBIrespreA. Similarly, the comparator circuit55bmay receive the DBI calculation signal DBI_calc_B and a previous DBI calculation result signal DBIrespreA from the flip-flop circuit56abased on DBI calculation of the DBI calculator A52a, and provide the current DBI calculation result signal DBIresB either in the active state or in the inactive state, the comparator circuit55cmay receive the DBI calculation signal DBI_calc_C and a previous DBI calculation result signal DBIrespreB from a flip-flop circuit56bbased on DBI calculation of the DBI calculator B52b, and provide the current DBI calculation result signal DBIresC either in the active state or in the inactive state, and the comparator circuit55dmay receive the DBI calculation signal DBI_calc_D and a previous DBI calculation result signal DBIrespreC from a flip-flop circuit56cbased on DBI calculation of the DBI calculator C52c, and provide the current DBI calculation result signal DBIresD either in the active state or in the inactive state. The DBI circuit5may also include a DBI output circuit57. The DBI output circuit may receive the current DBI calculation result signals DBIresA, DBIresB, DBIresC and DBIresD, and the pointer signals PointerA, PointerB, PointerC and PointerD. The DBI output circuit57may provide the current DBI calculation result signal DBIresA as a DBI bit signal responsive to the pointer signal PointerA (or the pointer signal PointerD as a delayed pointer signal), may provide DBIresB as the DBI bit signal responsive to the pointer signal PointerB (or the pointer signal PointerA as a delayed pointer signal), may provide DBIresC as the DBI bit signal responsive to the pointer signal PointerC (or the pointer signal PointerB as a delayed pointer signal), and may provide DBIresD as the DBI bit signal responsive to the pointer signal PointerD (or the pointer signal PointerC as a delayed pointer signal). Because the pointer signals PointerA, PointerB, PointerC, and PointerD are periodic signal having the same cycle and activated alternatingly in order, either DBIresA, DBIresB, DBIresC or DBIresD may be provided as the DBI bit signal, respectively.

FIG. 6Ais a schematic diagram of a DBI circuit6in accordance with an embodiment of the present disclosure.FIG. 6Bis a timing diagram of signals in the DBI circuit6during a DBI operation in accordance with an embodiment of the present disclosure. The DBI circuit6may include a plurality of DBI FIFO A circuits <7:0>61a, a plurality of DBI FIFO B circuits <7:0>61band a plurality of DBI FIFO C circuits <7:0>61cprovided for each bit of an input data, a DBI calculator A52a, a DBI calculator B52band a DBI calculator C52c. For example, a DBI calculation cycle (tDBI) in the DBI calculators A, B and C62a,62band62cmay be longer than two clock cycles (2tCK) (e.g., between two and three clock cycles) of a read clock signal READ.

Description of components corresponding to components included in the plurality of DBI FIFO A circuits <7:0>61a, the plurality of DBI FIFO B circuits <7:0>61band the plurality of DBI FIFO C circuits <7:0>61cis substantially the same as the plurality of DBI FIFO A circuits <7:0>51a, the plurality of DBI FIFO B circuits <7:0>51band the plurality of DBI FIFO C circuits <7:0>51cand will not be repeated and changes fromFIG. 5A, including configuration of pointer signals PointerA, PointerB and PointerC received by the plurality of DBI FIFO A circuits <7:0>51a, the plurality of DBI FIFO B circuits <7:0>51band the plurality of DBI FIFO C circuits <7:0>51cwill be described.

Pointer signals PointerA, PointerB and PointerC are periodic signals that may have a periodic cycle of three clock cycles (=3tCK) of a read clock signal READ. The pointer signals PointerA, PointerB and PointerC may also have a pulse width of one clock cycle (=1tCK) of the read clock signal READ as an active state (e.g., at a logic high level) for every three clock cycles (3tCK). The pointer signals PointerA, PointerB, and PointerC may be in the active state in order. For example, a falling edge of the pointer signal PointerA and a rising edge of the pointer signal PointerB occur substantially simultaneously. Similarly, a falling edge of the pointer signal PointerB and a rising edge of the pointer signal PointerC occur substantially simultaneously, and a falling edge of the pointer signal PointerC and a rising edge of the pointer signal PointerA occur substantially simultaneously. Each of the plurality of DBI FIFO A circuits <7:0>61a, the plurality of DBI FIFO B circuits <7:0>61band the plurality of DBI FIFO C circuits <7:0>61cmay receive a corresponding pointer signal, PointerA, PointerB, PointerC, respectively.

For example, the flip-flop circuits611aof the DBI FIFO A circuits <7:0>61amay latch corresponding bits of the data on the corresponding RW-bus[7:0] at 3×N cycles (e.g., D0, D3, D6, D9, Dc and Df inFIG. 6B), where N is a natural number, responsive to the pointer signal PointerA in the active state (e.g., at a logic high level), and provide latched data signals DBIA[7:0] as shown inFIG. 6B. The bit inverter612aof each DBI FIFO A circuit61amay receive a corresponding bit of the latched data signals DBIA[7:0] and a current DBI calculation result signal DBIresA from a comparator circuit65acoupled to the DBI calculator A62a. If the current DBI calculation result signal DBIresA is active, the bit inverter612amay provide an inverted bit of the corresponded bit of the latched data signals DBIA[7:0]. If the current DBI calculation result signal DBIresA is inactive (e.g., at a logic low level), the bit inverter612amay provide the corresponding bit of the latched data signals DBIA[7:0]. The NAND circuit614amay receive either the corresponding bit or its inverted bit of the latched data signals DBIA[7:0] from the bit inverter612a. The NAND circuit614amay further receive the pointer signal PointerA. Thus, the NAND circuit614amay provide a logic NAND value of either the corresponding bit or its inverted bit of the latched data signals DBIA[7:0] and the pointer signal PointerA. Thus, the DBI FIFO A circuits <7:0>61amay receive data on RW-bus[7:0] every three cycles (3tCK) and may further update output signals every four cycles (3tCK) responsive to the pointer signal PointerA. Similarly, the DBI FIFO B circuits <7:0>61band the DBI FIFO C circuits61cmay receive data on RW-bus[7:0] every three cycles (3tCK) responsive to the pointer signals PointerB and PointerC respectively, and may further update output signals every three cycles (3tCK) responsive to the pointer signals PointerB and PointerC, respectively. A plurality of output circuits63may receive output signals of the corresponding DBI FIFO A to C circuits of the plurality of the DBI FIFO A circuits <7:0>61a, the plurality of the DBI FIFO B circuits <7:0>61b, the plurality of the DBI FIFO C circuits <7:0>61c, and provide data output signals Dout [7:0].

The DBI calculators A, B and C62a,62band62cmay perform DBI calculation to detect whether the majority bits of the current data are different in logic level from the previous data. The DBI calculators A, B and C62a,62band62cmay include similar components in a similar structural configuration as the DBI calculator A62ainFIG. 6A, and detailed illustrations of the DBI calculators B and C62band62care omitted inFIG. 6A. Description of components corresponding to components included in the DBI calculator A62a, the DBI calculator B62band the DBI calculator C62cis substantially the same as the DBI calculators A and B inFIG. 2Aand will not be repeated and changes fromFIG. 2A, including configuration of latched data signals DBIA, DBIB, DBIC and pointer signals PointerA, PointerB, PointerC will be described. For example, the DBI calculator circuit3ofFIG. 3may be used as the DBI calculator A62a, the DBI calculator B62band the DBI calculator C62c. The DBI calculator A62amay receive the latched data signals DBIA[7:0] from the flip-flop circuits611aof the DBI FIFO A circuits <7:0>61a. The DBI calculator A62amay also receive data signals c[7:0] from a plurality of flip-flop circuits64a. The plurality of flip-flop circuits64amay receive the latched data signals DBIC[7:0] from the flip-flop circuits611cof the DBI FIFO C circuits <7:0>61cand the pointer signal PointerA, and latch the latched data signals DBIC[7:0] respectively to provide the data signals c[7:0]. Similarly, the DBI calculator B62bmay also receive data signals a[7:0] that is the latched data signals DBIA[7:0] further latched by a plurality of flip-flop circuits64busing the pointer signal PointerB. The DBI calculator C62cmay also receive data signals b[7:0] that is the latched data signals DBIB[7:0] further latched by a plurality of flip-flop circuits64cusing the pointer signal PointerC.

FIG. 7Ais a schematic diagram of a DBI circuit7in accordance with an embodiment of the present disclosure.FIG. 7Bis a timing diagram of signals in the DBI circuit7during a DBI operation in accordance with an embodiment of the present disclosure. The DBI circuit7may include a plurality of DBI FIFO A circuits <7:0>71aand a plurality of DBI FIFO B circuits <7:0>71bprovided for each bit of an input data, a DBI calculator A72aand a DBI calculator B72b. For example, a DBI calculation cycle (tDBI) in the DBI calculators A and B72aand72bmay be longer than two clock cycles (2tCK) of a read clock signal READ. The plurality of DBI FIFO A circuits <7:0>71aand the plurality of DBI FIFO B circuits <7:0>71bboth may receive a plurality of corresponding bits of data (e.g., in order of D0, D1, D2, D3, D4, D5, D6, D7) from RW-bus [7:0] respectively at every read clock cycle (1tCK) of the read clock signal READ. The plurality of DBI FIFO A circuits <7:0>71aand the plurality of DBI FIFO B circuits <7:0>71bmay receive pointer signals PointerA and PointerB respectively. The PointerA signal and the PointerB signal are periodic signals that may have a pulse width of one clock cycle (=1tCK) of the read clock signal READ, and they are complementary to each other. Thus, PointerA signal and the PointerB signal may alternate their active states (e.g., a logic high level) and data may be latched at every other cycles (e.g., odd cycles only, or even cycles only) by the pointer signals PointerA and PointerB. The DBI calculator A72aand the DBI calculator B72bmay perform DBI calculation to detect whether the majority bits of the current data are different in logic level from the previous data. The DBI calculator B72bmay include similar components in a similar structural configuration as the DBI calculator A72a, and detailed illustration of the DBI calculator B72bis omitted inFIG. 7A.

Each DBI FIFO A circuit71aof the plurality of DBI FIFO A circuits <7:0>71amay include a series of flip-flop circuits7111a,7112a,7113a, a bit inverter712a, a flip-flop circuit713a, and a NAND circuit714a. Each DBI FIFO B circuit of the plurality of DBI FIFO B circuits <7:0>21bincludes a series of flip-flop circuits7111b,7112b,7113b, a bit inverter712b, a flip-flop circuit713b, and a NAND circuit714b. The plurality of DBI FIFO A circuits <7:0>71aand the plurality of DBI FIFO B circuits <7:0>71bmay provide FIFO output signals to a plurality of output circuits73, in synchronous to DBI bit signals by holding for a number of clock cycles of the read clock signal READ corresponding to DBI calculation time (tDBI).

For example, the flip-flop circuits7111bof the DBI FIFO B circuits <7:0>71bmay latch corresponding bits of the data on the corresponding RW-bus[7:0] at even cycles (e.g., D0, D2, D4, D6inFIG. 2B) responsive to the PointerB signal in the beginning of its active state (e.g., at a rising edge to a logic high level), and provide latched data signals DBIB1[7:0]. The flip-flop circuits7112bof the DBI FIFO B circuits <7:0>71bmay latch corresponding bits of the data on the corresponding DBIB1[7:0] at even cycles (e.g., D0, D2, D4, D6inFIG. 2B) responsive to the PointerB signal in the end of the active state (e.g., at a falling edge to a logic low level), and provide latched data signals DBIB2[7:0]. The flip-flop circuits7113bof the DBI FIFO B circuits <7:0>71bmay latch corresponding bits of the data on the corresponding DBIB2[7:0] at even cycles (e.g., D0, D2, D4, D6inFIG. 2B) responsive to the PointerB signal in the beginning of the active state, and provide latched data signals DBIB3[7:0]. The bit inverter712bof each DBI FIFO B circuit71bmay receive a corresponding bit of the latched data signals DBIB3[7:0] and a current DBI calculation result signal DBIresB from a comparator circuit75bcoupled to the DBI calculator B72b. If the current DBI calculation result signal DBIresB is active, the bit inverter712bmay provide an inverted bit of the corresponded bit of the latched data signals DBIB3[7:0]. If the current DBI calculation result signal DBIresB is inactive (e.g., at a logic low level), the bit inverter712bmay provide the corresponded bit of the latched data signals DBIB3[7:0]. The flip-flop circuit713bof each DBI FIFO B circuit71bmay latch an output signal of the bit inverter712bresponsive to the pointer signal PointerB in the end of the active state. The NAND circuit714bof each DBI FIFO B circuit71bmay provide an inverted signal of the output signal of the bit inverter712bas a FIFO output signal if the pointer signal PointerB is in the active state. Similarly, the DBI FIFO A circuits <7:0>21amay latch corresponding bits of the data on the corresponding RW-bus[7:0] at odd cycles (e.g., D1, D3, D5, D7inFIG. 2B) responsive to the PointerA signal in the beginning of the active state, and provide a FIFO output signal if the pointer signal PointerA is in the active state. A plurality of output circuits73may receive the FIFO output signals of the corresponding NAND circuits714aand714band provide data output signals Dout [7:0].

The DBI calculator A72amay receive the latched data signals DBIA1[7:0] from the flip-flop circuits7111aof the DBI FIFO A circuits <7:0>71a. The DBI calculator A22amay also receive data signals b[7:0] from a plurality of flip-flop circuits74a. The plurality of flip-flop circuits74amay receive the latched data signals DBIB1[7:0] from the flip-flop circuits7111bof the DBI FIFO B circuits <7:0>71band the pointer signal PointerA, and latch the latched data signals DBIB1[7:0] respectively to provide the data signals b[7:0]. The DBI calculator A72amay include an input stage similar to the input state31inFIG. 3, that may include a plurality of comparator circuits721aand a plurality of flip-flop circuits723a. For example, the plurality of comparator circuits721amay be XOR circuits. Each comparator circuit of the plurality of comparator circuits721amay receive a corresponding bit of the data signals b[7:0] and a corresponding bit of the latched data signals DBIA1[7:0] and provide a result signal for each corresponding bit. For example, the result signal may be an active state (e.g., “1” or a logic high level), if the corresponding bit of the data signals b[7:0] and the corresponding bit of the latched data signals DBIA1[7:0] are different, which indicates that the corresponding bits of the previous data and the current data are different. Similarly, the result signal may be an inactive state (e.g., “0” or a logic low level), if the corresponding bit of the data signals b[7:0] and the corresponding bit of the latched data signals DBIA1[7:0] are the same, which indicates that the corresponding bits of the previous data and the current data are the same. The plurality of flip-flop circuits723amay latch signals to be provided as a1, b1, c1, d1, a2, b2, c2and d2using an inverted signal of the pointer signal PointerA, thus the signals are latched responsive to the falling edge of PointerA. The DBI calculator A72amay further include an intermediate stage similar to the intermediate state32inFIG. 3, that may include a plurality of flip-flop circuits724a. The plurality of flip-flop circuits724amay latch signals to be provided as A1, B1, C1, D1, A2, B2, C2and D2using the pointer signal PointerA, thus the signals are latched responsive to the rising edge of PointerA. The DBI calculator A72amay include an adder circuit722a. For example, the adder circuit722amay be an OR circuit. The adder circuit722amay receive calculation signals after calculations based on the result signals from the plurality of comparator circuits721aand may provide a DBI calculation signal DBI_calc_A. Calculations based on the result signals was similar to the calculation with reference toFIG. 3, adding latching steps by the plurality of flip-flop circuits723aand724a. The comparator circuit75amay receive the DBI calculation signal DBI_calc_A and a previous DBI calculation result signal DBIrespreB from a flip-flop circuit76bbased on DBI calculation of the DBI calculator B72b. If the DBI calculation signal DBI_calc_A and the previous DBI calculation result signal DBIrespreB are different, the comparator circuit75amay provide the current DBI calculation result signal DBIresA in an active state (e.g., “1” or a logic high level). If the DBI calculation signal DBI_calc_A and the previous DBI calculation result signal DBIrespreB are the same, the comparator circuit75amay provide the current DBI calculation result signal DBIresA in an inactive state (e.g., “0” or a logic low level). A flip-flop circuit76amay receive the current DBI calculation result signal DBIresA and latch the current DBI calculation result signal DBIresA with the inverted signal of the pointer signal PointerA and may provide the latched current DBI calculation result signal DBIresA as a previous DBI calculation result signal DBIrespreA. Similarly, the DBI calculator B72btogether with a comparator circuit75band a flip-flop circuit76bmay provide the current DBI calculation result signal DBIresB and the previous DBI calculation result signal DBIrespreB. The DBI circuit7may also include a DBI output circuit77. The DBI output circuit77may receive the current DBI calculation result signals DBIresA and DBIresB and the pointer signals PointerA and PointerB. The DBI output circuit77may provide DBIresA as a DBI bit signal responsive to the pointer signal PointerA and may provide DBIresB as the DBI bit signal responsive to the pointer signal PointerB. Because the pointer signals PointerA and PointerB are complementary periodic signals, either DBIresA or DBIresB may be provided as the DBI bit signal at odd cycles or even cycles, respectively.

FIG. 8Ais a schematic diagram of a DBI circuit8in accordance with an embodiment of the present disclosure.FIG. 8Bis a timing diagram of signals in the DBI circuit8during a DBI operation in accordance with an embodiment of the present disclosure. Description of components corresponding to components included inFIG. 5Awill not be repeated and changes fromFIG. 5A, including configuration of RW-bus signals and pointer signals will be described. Similarly toFIGS. 4A and 4B, RW-busR[7:0] and RW-busF[7:0] inFIG. 8Bboth may transmit data of every other data alternatingly every two clock cycles (2tCK) of a read clock signal READ. For example, RW-busR[7:0] may transmit data of odd cycles (e.g., in order of D1, D3, D5, D7, D9, Db, Dd and Df) to a dataR circuit80aand RW-busF[7:0] may transmit data of even cycles (e.g., in order of D0, D2, D4, D6, D8, Da, Dc and De) to a dataF circuit80b. The dataR circuit80amay include a plurality of DBI FIFO A circuits <7:0>81a, a plurality of DBI FIFO C circuits <7:0>81cand a plurality of DBI FIFO E circuits <7:0>81ethat may receive corresponding bits of data (e.g., in order of D1, D3, D5, D7, D9, Db, Dd and Df) from RW-bus_R[7:0] respectively at every other read clock cycle (2tCK) of the read clock signal READ. The dataR circuit80amay also include a plurality of output circuits83a. The dataF circuit80bmay include a plurality of DBI FIFO B circuits <7:0>81b, a plurality of DBI FIFO D circuits <7:0>81dand a plurality of DBI FIFO E circuits <7:0>81ethat may receive corresponding bits of data (e.g., in order of D0, D2, D4, D6, D8, Da, Dc and De) from RW-bus_F[7:0] respectively at every other read clock cycle (2tCK) of the read clock signal READ. The dataF circuit80bmay also include a plurality of output circuits83b. The dataR circuit80amay provide Do_busR[7:0] signals and the dataF circuit80bmay provide Do_busF[7:0] signals. The DBI circuit8may further include a serializer circuit88that may receive the Do_busR[7:0] signals and Do_busF[7:0] signals. The serializer circuit88may combine the Do_busR[7:0] signals and Do_busF[7:0] signals and may provide data output signals Dout [7:0] in series responsive to the read clock signal READ in order of D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, Da, Db, Dc, Dd, De and Df.

For example, the flip-flop circuits811aof the DBI FIFO A circuits <7:0>81amay latch corresponding bits of the data on the corresponding RW-busR[7:0] at every six cycles (e.g., D1, D7and Dd inFIG. 8B), responsive to the pointer signal PointerA in the active state (e.g., at a logic high level), and provide latched data signals DBIA[7:0] as shown inFIG. 8B. The bit inverter812aof each DBI FIFO A circuit811amay receive a corresponding bit of the latched data signals DBIA[7:0] and a current DBI calculation result signal DBIresA from a comparator circuit85acoupled to the DBI calculator A82a. If the current DBI calculation result signal DBIresA is active, the bit inverter812amay provide an inverted bit of the corresponded bit of the latched data signals DBIA[7:0]. If the current DBI calculation result signal DBIresA is inactive (e.g., at a logic low level), the bit inverter812amay provide the corresponding bit of the latched data signals DBIA[7:0]. The NAND circuit814amay receive either the corresponding bit or its inverted bit of the latched data signals DBIA[7:0] from the bit inverter812aat one input node. The NAND circuit814amay further receive the pointer signal PointerD which is delayed by three clock cycles (3tCK) of the read clock signal READ from the pointer signal PointerA ((e.g., having a rising edge as a beginning of the active state three clock cycles (3tCK) after a rising edge of the pointer signal PointerA) and the pointer signal PointerE which is delayed by four clock signal from the pointer signal PointerA at the other input node. By using the pointer signals PointerD and PointerE, a similar effect as providing a pointer signal having a delay of a DBI calculation cycle (tDBI) inFIG. 5Amay be obtained, if the DBI calculation cycle (tDBI), which is longer than the two read clock cycles (>2tCK) and shorter than three read clock cycles (<3tCK). Thus, the NAND circuit514amay provide a logic NAND value of either the corresponding bit or its inverted bit of the latched data signals DBIA[7:0] and the pointer signal PointerD. Thus, the DBI FIFO A circuits <7:0>81amay receive data on RW-busR[7:0] every six cycles (6tCK) responsive to the pointer signal PointerA and may further update output signals every six cycles (6tCK) responsive to the pointer signals PointerD and PointerE. Similarly, the DBI FIFO B circuits <7:0>81bmay receive data on RW-busF[7:0] every six cycles (6tCK) responsive to the pointer signal PointerB and may further update output signals every six cycles (6tCK) responsive to the pointer signals PointerE and PointerF, the DBI FIFO C circuits <7:0>81cmay receive data on RW-busR[7:0] every six cycles (6tCK) responsive to the pointer signal PointerC and may further update output signals every six cycles (6tCK) responsive to the pointer signals PointerF and PointerA, and the DBI FIFO D circuits <7:0>81dmay receive data on RW-busF[7:0] every six cycles (6tCK) responsive to the pointer signal PointerD and may further update output signals every six cycles (6tCK) responsive to the pointer signals PointerA and PointerB. Similarly, the DBI FIFO E circuits <7:0>81eand the DBI FIFO F circuits <7:0> may receive data on RW-busR[7:0] and RW-busF[7:0] every six cycles (6tCK) responsive to the pointer signals PointerE and Pointer F, respectively, and may further update output signals every six cycles (6tCK) responsive to a combination of the pointers signals PointerB and PointerC, and a combination of the pointer signals PointerC and PointerD, respectively. The plurality of output circuits83amay receive output signals of the corresponding DBI FIFO A, C, E circuits of the plurality of the DBI FIFO A circuits <7:0>81a, the plurality of the DBI FIFO C circuits <7:0>81cand the plurality of the DBI FIFO E circuits <7:0>81e, and provide data output signals Do-busR[7:0] to the serializer circuit88. Similarly, the plurality of output circuits83bmay receive output signals of the corresponding DBI FIFO B, D, F circuits of the plurality of the DBI FIFO B circuits <7:0>81b, the plurality of the DBI FIFO D circuits <7:0>81dand the plurality of the DBI FIFO F circuits <7:0>81f, and provide data output signals Do-busF[7:0] to the serializer circuit88.

A comparator circuit85amay receive the DBI calculation signal DBI_calc_A and a previous DBI calculation result signal DBIrespreF from a flip-flop circuit86fbased on DBI calculation of the DBI calculator F82f. If the DBI calculation signal DBI_calc_A and the previous DBI calculation result signal DBIrespreF are different, the comparator circuit85amay provide the current DBI calculation result signal DBIresA in an active state (e.g., “1” or a logic high level). If the DBI calculation signal DBI_calc_A and the previous DBI calculation result signal DBIrespreF are the same, the comparator circuit85amay provide the current DBI calculation result signal DBIresA in an inactive state (e.g., “0” or a logic low level). A flip-flop circuit86amay receive the current DBI calculation result signal DBIresA and latch the current DBI calculation result signal DBIresA with the pointer signal PointerD and may provide the latched current DBI calculation result signal DBIresA as a previous DBI calculation result signal DBIrespreA. Similarly, the comparator circuit85bmay receive the DBI calculation signal DBI_calc_B and a previous DBI calculation result signal DBIrespreA from a flip-flop circuit86abased on DBI calculation of the DBI calculator A82a, and provide the current DBI calculation result signal DBIresB either in the active state or in the inactive state, the comparator circuit85cmay receive the DBI calculation signal DBI_calc_C and a previous DBI calculation result signal DBIrespreB from a flip-flop circuit86bbased on DBI calculation of the DBI calculator B82b, and provide the current DBI calculation result signal DBIresC either in the active state or in the inactive state, and the comparator circuit85dmay receive the DBI calculation signal DBI_calc_D and a previous DBI calculation result signal DBIrespreC from a flip-flop circuit86cbased on DBI calculation of the DBI calculator C82c, and provide the current DBI calculation result signal DBIresD either in the active state or in the inactive state. Similarly, the comparator circuits85eand85fmay provide the current DBI calculation result signals DBIresE and DBIresF, respectively. The DBI circuit8may also include a DBI output circuit87. The DBI output circuit may receive the current DBI calculation result signals DBIresA, DBIresB, DBIresC, DBIresD, DBIresE and DBIresF and the pointer signals PointerA, PointerB, PointerC, PointerD, PointerE and PointerF. The DBI output circuit87may provide the current DBI calculation result signal DBIresA as a DBI bit signal responsive to the pointer signal PointerA (or the pointer signal PointerD as a delayed pointer signal), may provide DBIresB as the DBI bit signal responsive to the pointer signal PointerB (or the pointer signal PointerE as a delayed pointer signal), may provide DBIresC as the DBI bit signal responsive to the pointer signal PointerC (or the pointer signal PointerF as a delayed pointer signal), may provide DBIresD as the DBI bit signal responsive to the pointer signal PointerD (or the pointer signal PointerA as a delayed pointer signal), may provide DBIresE as the DBI bit signal responsive to the pointer signal PointerE (or the pointer signal PointerB as a delayed pointer signal) and may provide DBIresF as the DBI bit signal responsive to the pointer signal PointerF (or the pointer signal PointerC as a delayed pointer signal). Because the pointer signals PointerA, PointerB, PointerC, PointerD, PointerE and Pointer F are periodic signal having the same cycle and activated alternatingly in order, either DBIresA, DBIresB, DBIresC, DBIresD, DBIresE, or DBIresF may be provided as the DBI bit signal, respectively.

FIG. 9Ais a schematic diagram of a DBI circuit9in accordance with an embodiment of the present disclosure. The DBI circuit9may include a plurality of DBI FIFO A circuits <7:0>91a, a plurality of DBI FIFO B circuits <7:0>91b, a plurality of DBI FIFO C circuits <7:0>91cand a plurality of DBI FIFO D circuits <7:0>91dprovided for input data from RW-bus <7:0>. The DBI circuit9may also include a DBI calculator circuit96, a pointer circuit93that may receive a read clock signal CLK and an output circuit92that may provide output data Dout <7:0>.

FIG. 9Bis a circuit diagram of a DBI calculator circuit960in accordance with an embodiment of the present disclosure. For example, the DBI calculator circuit960may be the DBI calculator circuit96inFIG. 9A. For example, the DBI calculator circuit960may include a DBI calculator A960a, a DBI calculator B960b, a DBI calculator C960cand a DBI calculator D960d. For example, a DBI calculation cycle (tDBI) in the DBI calculators A, B, C and D960a,960b,960cand960dmay be longer than two clock cycles (2tCK) (e.g., between two and three clock cycles) of the read clock signal CLK. Description of components corresponding to components included in the DBI calculator A960a, the DBI calculator B960b, the DBI calculator C960cand the DBI calculator D960dis substantially the same as the DBI calculators inFIG. 3orFIG. 5Aand thus will not be repeated.

The plurality of DBI FIFO A circuits <7:0>91a, the plurality of DBI FIFO B circuits <7:0>91b, the plurality of DBI FIFO C circuits <7:0>91cand the plurality of DBI FIFO B circuits <7:0>91dmay receive common input data from the RW-bus <7:0>. The pointer circuit93may provide InPointerA, InPointerB, InPointerC and InPointerD signals responsive to the read clock CLK. The pointer circuit93may further provide OutPointerA, OutPointerB, OutPointerC and OutPointerD signals responsive to the read clock CLK. Each of the plurality of DBI FIFO A circuits <7:0>91a, the plurality of DBI FIFO B circuits <7:0>91b, the plurality of DBI FIFO C circuits <7:0>91cand the plurality of DBI FIFO D circuits <7:0>91dmay receive a combination of those pointer signals. For example, the plurality of DBI FIFO A circuits <7:0>91amay receive the pointer signals InPointerA, InPointerD and OutPointerC, the plurality of DBI FIFO B circuits <7:0>91bmay receive the pointer signals InPointerB, InPointerA and OutPointerD, the plurality of DBI FIFO C circuits <7:0>91cmay receive the pointer signals InPointerC, InPointerB and OutPointerA, and the plurality of DBI FIFO D circuits <7:0>91dmay receive the pointer signals InPointerD, InPointerC and OutPointerB, respectively. The DBI calculators A, B, C and D960a,960b,960cand960dmay perform DBI calculation to detect whether the majority bits of the current data are different in logic level from the previous data. The DBI calculators B. C and D960b,960cand960dmay include similar components in a similar structural configuration as the DBI calculator A960aand detailed illustrations of the DBI calculators B, C and D960b,960cand92dare omitted inFIG. 9B.

FIG. 9Cis a circuit diagram of a DBI FIFO circuit910in accordance with an embodiment of the present disclosure. For example, the DBI FIFO circuit910may be each DBI FIFO circuit of the plurality of DBI FIFO A, B, C and D circuits <7:0>91a,91b,91cand91dinFIG. 9A. The DBI FIFO circuit910may include two latch circuits911and912, a bit inverter (e.g., XOR circuit)913and a NAND circuit914. For example, the latch circuits911may latch (e.g., temporarily store) a corresponding bit of the data on the corresponding RW-bus <7:0> on a node N1in response to InPointer signal on a node N2, and may further provide a signal L1to the latch circuit912. The latch circuit912may latch (e.g., temporarily store) the signal L1from the latch circuit911responsive to another InPointer signal on a node N3. The latch circuit912may provide a signal L2on a node N5and further to the bit inverter913that may receive DBIres signal at a node N7. The bit inverter913may provide an output signal to an NAND circuit914that may also receive OutPointer signal on a node N4. The NAND circuit914may provide a corresponding bit of output data Do to a node N6.

FIG. 9Dis a circuit diagram of a latch circuit920in accordance with an embodiment of the present disclosure. For example, the latch circuit920may be used as the latch circuits911and912. The latch circuit920may include two clocked inverter circuits925and926and two inverters927and928.FIG. 9Eis a circuit diagram of a pointer930in accordance with an embodiment of the present disclosure. For example, the pointer930may be the pointer93inFIG. 9A. The pointer930may include a plurality of flip-flop (FF) circuits931-934, a plurality of NAND circuits936-939and a plurality of buffers940-943, as shown inFIG. 9E. The plurality of flip-flop (FF) circuits931-934may provide output signals to the plurality of NAND circuits936-939and the plurality of buffers940-943, respectively. The plurality of NAND circuits936-939may provide the InPointerA-D signals inFIG. 9Bresponsive to the clock signal CLK. The plurality of buffers940-943may provide the OutPointerA-D signals inFIG. 9B.FIG. 9Fis a circuit diagram of an FF circuit950in accordance with an embodiment of the present disclosure. For example, the FF circuit950may be each FF circuit of the plurality of FF circuits931-935. For example, The FF circuit950may include three inverters951-953and four clocked inverters954-957.

FIG. 9Gis a timing diagram of signals in the DBI circuit9during a DBI operation in accordance with an embodiment of the present disclosure. With the above configurations, the DBI circuit9may perform a DBI operation on the current input data and the previous input data. The plurality of DBI FIFO A circuits <7:0>91a, the plurality of DBI FIFO B circuits <7:0>91b, the plurality of DBI FIFO C circuits <7:0>91cand the plurality of DBI FIFO D circuits <7:0>91dmay internally latch common input data D0-D7[7:0] from the RW-bus <7:0> (e.g., at the latch circuits911) responsive to InPointerA, InPointerB, InPointerC and InPointerD signals from the pointer circuit93and may provide a string of data D0[7:0], D1[7:0], D2[7:0], D3[7:0] as L1A-L1D signals, respectively. The plurality of DBI FIFO A circuits <7:0>91a, the plurality of DBI FIFO B circuits <7:0>91b, the plurality of DBI FIFO C circuits <7:0>91cand the plurality of DBI FIFO D circuits <7:0>91dmay internally latch the L1A-L1D signals (e.g., at the latch circuits912) responsive to InPointerD, InPointerA, InPointerB and InPointerC signals from the pointer circuit93, and may provide the string of data D0[7:0], D1[7:0], D2[7:0], D3[7:0] as L2A-L2D signals, respectively, with a delay of three clock cycles. Furthermore, the plurality of DBI FIFO A circuits <7:0>91a, the plurality of DBI FIFO B circuits <7:0>91b, the plurality of DBI FIFO C circuits <7:0>91cand the plurality of DBI FIFO D circuits <7:0>91dmay internally provide the L2A-L2D signals responsive to the DBI calculation result signals DBIres (e.g., at the bit inverters913) with a delay of the DBI calculation cycle (tDBI). Finally, the plurality of DBI FIFO A circuits <7:0>91a, the plurality of DBI FIFO B circuits <7:0>91b, the plurality of DBI FIFO C circuits <7:0>91cand the plurality of DBI FIFO D circuits <7:0>91dmay provide output data signals Dout[7:0] responsive to the OutPointerA, OutPointerB, OutPointerC and OutPointerD signals (e.g., at the NAND circuit914).

Logic levels of signals used in the embodiments described the above are merely examples. However, in other embodiments, combinations of the logic levels of signals other than those specifically described in the present disclosure may be used without departing from the scope of the present disclosure.

Although embodiments of the disclosure have been described, it will be understood by those skilled in the art that the disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of the disclosure will be readily apparent to those of skill in the art. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of other embodiments of the disclosure. Thus, it is intended that the scope of the disclosure should not be limited by the particular disclosed embodiments described above.