Methods of detecting stresses, methods of training compact models, methods of relaxing stresses, and computing systems

A method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority from Korean Patent Application No. 10-2014-0085953, filed on Jul. 9, 2014, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.

BACKGROUND

Example embodiments may relate generally to semiconductor circuit designs and verifications. Example embodiments may relate generally to methods of detecting stresses, methods of training compact models, methods of relaxing stresses, and/or computing systems.

2. Description of Related Art

In semiconductor circuits, such as integrated circuits, adjacent patterns may be formed from different materials. In cases where the materials of these adjacent patterns (e.g., an active pattern and an isolation layer pattern) have different expansion coefficients (or different coefficients of thermal expansion), each pattern may be under stress, and defects, such as standby leakage currents or cracks, may be caused by dislocation of one or more patterns.

SUMMARY

Some example embodiments may provide methods of detecting stresses of integrated circuits when verifying designs of the integrated circuits.

Some example embodiments may provide computing systems for detecting stresses of integrated circuits when verifying designs of the integrated circuits.

Some example embodiments may provide methods of training compact models for detecting stresses of integrated circuits.

Some example embodiments may provide computing systems for training compact models for detecting stresses of integrated circuits.

Some example embodiments may provide methods of relaxing stresses of integrated circuits.

Some example embodiments may provide computing systems for relaxing stresses of integrated circuits.

In some example embodiments, a method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

In some example embodiments, the first stress detection point may include at least one selected from a convex point, a concave point, and a projected point of the first pattern.

In some example embodiments, the determining of the one or more stress detection points and the detecting of the stress level may be performed throughout a whole region of the integrated circuit.

In some example embodiments, the dividing of the region including the first stress detection point into the plurality of divided regions may include: determining a rectangular shaped region having the first stress detection point as a central point; and/or dividing the rectangular shaped region into first through fourth divided regions.

In some example embodiments, the detecting of the stress level may include: calculating, as the stress level, a sum of a first coefficient, a product of a second coefficient and the area of the second pattern at the first divided region, a product of a third coefficient and the area of the second pattern at the second divided region, a product of a fourth coefficient and the area of the second pattern at the third divided region, and a product of a fifth coefficient and the area of the second pattern at the fourth divided region.

In some example embodiments, the dividing of the region including the first stress detection point into the plurality of divided regions may include: determining N rectangular shaped regions having different sizes such that each of the N rectangular shaped regions has the first stress detection point as a central point, where N is an integer greater than 0; and/or dividing each of the N rectangular shaped regions into M divided regions, where M is an integer greater than 1.

In some example embodiments, the detecting of the stress level may include: calculating the stress level by using an L-th order equation of the areas of the second pattern at the divided regions, where L is an integer greater than 0.

In some example embodiments, the dividing of the region including the first stress detection point into the plurality of divided regions may include: determining N circular shaped regions having different sizes such that each of the N circular shaped regions has the first stress detection point as a central point, where N is an integer greater than 0; and/or dividing each of the N circular shaped regions into M divided regions, where M is an integer greater than 1.

In some example embodiments, the first pattern may be an active pattern. The second pattern may be an isolation layer pattern. The stress level applied to the first stress detection point of the active pattern by the isolation layer pattern may be detected.

In some example embodiments, a computing system that is configured to detect stress of an integrated circuit including first and second patterns formed from different materials may comprise: a memory device into which layout data for the integrated circuit and a stress detection tool for detecting the stress of the integrated circuit are loaded; and/or a processor configured to execute the stress detection tool loaded into the memory device. The stress detection tool executed by the processor may be configured to determine one or more stress detection points of the first pattern based on the layout data, may be configured to divide a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions, may be configured to calculate areas of the second pattern at the divided regions, and/or may be configured to detect a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

In some example embodiments, the stress detection tool may include: a point determining module configured to determine the first stress detection point of the first pattern based on the layout data; and/or a stress detecting module configured to divide the region including the first stress detection point into the divided regions, configured to calculate the areas of the second pattern at the divided regions, and/or configured to detect the stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

In some example embodiments, the stress detection tool executed by the processor may be configured to add a layer representing the stress level to the layout data.

In some example embodiments, a method of training a compact model for detecting stress of an integrated circuit may comprise: performing compact model-based stress simulation using the compact model on the integrated circuit to extract a stress distribution of the integrated circuit; selecting sample stress detection points based on the stress distribution of the integrated circuit; performing rigorous stress simulation on the sample stress detection points; and/or calibrating the compact model based on a result of the rigorous stress simulation.

In some example embodiments, the compact model-based stress simulation may be a full-chip stress simulation for the integrated circuit. The stress distribution of the integrated circuit may be a full-chip stress distribution of the integrated circuit. The sample stress detection points may be selected based on the full-chip stress distribution of the integrated circuit.

In some example embodiments, the sample stress detection points may be selected such that a distribution of the sample stress detection points has a shape substantially the same as a shape of the stress distribution.

In some example embodiments, the performing of the compact model-based stress simulation using the compact model may include: determining, in the integrated circuit including first and second patterns formed from different materials, one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions based on the compact model; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern by using the compact model based on the areas of the second pattern at the divided regions.

In some example embodiments, the first stress detection point may include at least one selected from a convex point, a concave point, and a projected point of the first pattern.

In some example embodiments, the compact model may correspond to an L-th order equation of the areas of the second pattern at the divided regions, where L is an integer greater than 0.

In some example embodiments, the calibrating of the compact model based on the result of the rigorous stress simulation may include: calibrating at least one coefficient of the L-th order equation based on the result of the rigorous stress simulation.

In some example embodiments, a computing system that is configured to train a compact model for detecting stress of an integrated circuit may comprise: a memory device into which layout data for the integrated circuit, the compact model, a stress detection tool for detecting the stress of the integrated circuit, and a training tool for training the compact model are loaded; and/or a processor configured to execute the stress detection tool and the training tool loaded into the memory device. The stress detection tool executed by the processor may be configured to perform compact model-based stress simulation using the compact model on the integrated circuit to extract a stress distribution of the integrated circuit. The training tool executed by the processor may be configured to select sample stress detection points based on the stress distribution of the integrated circuit, may be configured to perform rigorous stress simulation on the sample stress detection points, and/or may be configured to calibrate the compact model based on a result of the rigorous stress simulation.

In some example embodiments, a method of relaxing stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions; and/or inserting a dummy pattern near the first stress detection point of the first pattern when the detected stress level is greater than a desired value.

In some example embodiments, the dummy pattern may include at least one selected from a ring type dummy pattern, a rectangle type dummy pattern, a polygon type dummy pattern, and an attached type dummy pattern.

In some example embodiments, a computing system configured to relax stress of an integrated circuit including first and second patterns formed from different materials may comprise: a memory device into which layout data for the integrated circuit, a stress detection tool for detecting the stress of the integrated circuit, and a stress relaxation tool for relaxing the detected stress are loaded; and/or a processor configured to execute the stress detection tool and the stress relaxation tool loaded into the memory device. The stress detection tool executed by the processor may be configured to determine one or more stress detection points of the first pattern based on the layout data, may be configured to divide a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions, may be configured to calculate areas of the second pattern at the divided regions, and/or may be configured to detect a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions. The stress relaxation tool executed by the processor may be configured to insert a dummy pattern near the first stress detection point of the first pattern when the detected stress level is greater than a desired value.

In some example embodiments, a method of detecting stress of an integrated circuit including patterns of different materials may comprise: determining a first stress detection point of a first pattern; dividing a first region of the integrated circuit, including the first stress detection point, into divided first regions; calculating areas of a second pattern in the divided first regions; and/or detecting the stress applied to the first stress detection point by the second pattern based on the areas of the second pattern in the divided first regions.

In some example embodiments, the first stress detection point may comprise a convex point of the first pattern, a concave point of the first pattern, or a projected point of the first pattern.

In some example embodiments, the method may further comprise: determining a second stress detection point of the first pattern; dividing a second region of the integrated circuit, including the second stress detection point, into divided second regions; calculating areas of the second pattern in the divided second regions; and/or detecting the stress applied to the second stress detection point by the second pattern based on the areas of the second pattern in the divided second regions.

In some example embodiments, the second stress detection point may comprise a convex point of the first pattern, a concave point of the first pattern, or a projected point of the first pattern.

In some example embodiments, the first region and the second region may overlap.

In some example embodiments, the first region and the second region may not overlap.

In some example embodiments, at least one of the divided first regions may overlap at least one of the divided second regions.

In some example embodiments, none of the divided first regions may overlap any of the divided second regions.

In some example embodiments, the detecting of the stress applied to the first stress detection point may comprise: calculating the stress as a sum of a first coefficient and products of second coefficients and the areas of the second pattern at the divided first regions.

In some example embodiments, the detecting of the stress applied to the first stress detection point may comprise: calculating the stress by using an L-th order equation of the areas of the second pattern at the divided first regions, where L is an integer greater than 0.

In some example embodiments, the dividing of the first region of the integrated circuit into the divided first regions may comprise: determining N regions having different sizes such that each of the N regions has the first stress detection point as a central point, where N is an integer greater than 0; and/or dividing each of the N regions into M divided first regions, where M is an integer greater than 1.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference to the accompanying drawings. Embodiments, however, may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope to those skilled in the art. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.

It will be understood that when an element is referred to as being “on,” “connected to,” “electrically connected to,” or “coupled to” to another component, it may be directly on, connected to, electrically connected to, or coupled to the other component or intervening components may be present. In contrast, when a component is referred to as being “directly on,” “directly connected to,” “directly electrically connected to,” or “directly coupled to” another component, there are no intervening components present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout. The same reference numbers indicate the same components throughout the specification.

Reference will now be made to example embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals may refer to like components throughout.

FIG. 1is a flowchart illustrating a method of detecting stress of an integrated circuit according to some example embodiments, andFIG. 2is a diagram for describing a step of determining a stress detection point in a method of detecting stress according to some example embodiments.

Referring toFIG. 1, in an integrated circuit including first and second patterns that are formed from different materials, at least one stress detection point of the first pattern may be determined (S110). In some example embodiments, the first pattern may be one of an active pattern, an isolation layer pattern, a gate pattern, a poly-silicon pattern, or an epitaxial layer pattern, and the second pattern may be another one of the patterns different from the first pattern. For example, the first pattern may be the active pattern, and the second pattern may be the isolation layer pattern.

In some example embodiments, a convex point, a concave point, or a projected point of the first pattern may be determined as the stress detection point. Here, the convex point of the first pattern may mean a convex corner of the first pattern, the concave point of the first pattern may mean a concave corner of the first pattern, and the projected point of the first pattern may mean a point on which an adjacent convex point is projected. At the projected point, a gap with respect to an adjacent region of the first pattern may be changed.

Referring toFIG. 2, in a region100of an integrated circuit, a first pattern120, and a second pattern140may be adjacent to each other, and may be formed from different materials. For example, the first pattern120may be an active pattern formed from silicon, and the second pattern140may be an isolation layer pattern formed from silicon oxide (SiO2) by a shallow trench isolation (STI) process. In this case, as illustrated inFIG. 2, convex points (indicated by “O”), concave points (indicated by “□”), and projected points (indicated by “X”) of the first pattern120may be determined as the stress detection points.

In some example embodiments, the determination of the stress detection points may be performed throughout the whole region of the integrated circuit, and stress levels at the stress detection points may be detected throughout the whole region of the integrated circuit. For example, all convex points, all concave points, and all projected points of the first pattern in the whole region of the integrated circuit may be determined as the stress detection points, and the stress levels at all convex points, all concave points, and all projected points may be detected. That is, a full-chip stress simulation for detecting stress throughout the whole region of the integrated circuit may be performed.

Referring again toFIG. 1, a region including each stress detection point may be divided into a plurality of divided regions (S130). In some example embodiments, with respect to each stress detection point, a region having the stress detection point as the central point and having any shape, such as a rectangular shape, a polygonal shape, a circular shape, etc. may be determined, and the determined region may be divided into the plurality of divided regions. Further, in some example embodiments, with respect to each stress detection point, one or more regions having the stress detection point as the central point and having different sizes may be determined, and each of the one or more regions may be divided into the plurality of divided regions. For example, N rectangular shaped regions having different sizes may be determined such that each of the N rectangular shaped regions has the stress detection point as the central point, and each of the N rectangular shaped regions may be substantially equally divided into M divided regions, where N is an integer greater than 0 and M is an integer greater than 1. In an another example, N circular shaped regions having different sizes may be determined such that each of the N circular shaped regions has the stress detection point as the central point, and each of the N circular shaped regions may be substantially equally divided into M divided regions.

Areas of the second pattern may be calculated at the divided regions, respectively (S150). For example, the areas of the second pattern at the divided regions may be calculated from layout data of the integrated circuit. A stress level applied to the stress detection point of the first pattern by the second pattern may be detected based on the areas of the second pattern at the divided regions (S170). In some example embodiments, the stress level at the stress detection point may be calculated by using an L-th order equation of the areas of the second pattern at the divided regions (e.g., M*N divided regions generated by dividing each of N regions into M divided regions), where L is an integer greater than 0. For example, in a case where N is 1 and M is 4, a rectangular shaped region having the stress detection point as the central point may be substantially equally divided into first through fourth divided regions, and the stress level at the stress detection point may be detected by calculating a sum of a first coefficient (or constant), a product of a second coefficient and the area of the second pattern at the first divided region, a product of a third coefficient and the area of the second pattern at the second divided region, a product of a fourth coefficient and the area of the second pattern at the third divided region, and a product of a fifth coefficient and the area of the second pattern at the fourth divided region. Since the L-th order equation of the areas of the second pattern at the divided regions uses the areas to calculate the stress level, the L-th order equation may require relatively few calculations, and may be rapidly processed. Accordingly, the L-th order equation may be referred to as a “compact model” or an “area-based compact model” for detecting the stress of the integrated circuit.

In a semiconductor circuit such as an integrated circuit, adjacent patterns may be formed from different materials. In a case where the materials of these adjacent patterns have different expansion coefficients (or different coefficients of thermal expansion), each pattern may be under stress, and a defect, such as a standby leakage current or a crack, may be caused by dislocation of each pattern. To prevent this standby leakage current or crack, a stress simulation may be performed to detect the stress of the integrated circuit when verifying a design of the integrated circuit. A rigorous stress simulation using a finite element method (FEM) or a finite analytic method (FAM) may require relatively many calculations and, thus, the rigorous stress simulation may require a long processing time. Accordingly, the rigorous stress simulation can be performed only on a small part of the integrated circuit. However, the method of detecting the stress using the compact model according to some example embodiments may have a short processing time since the compact model may require relatively few calculations and, thus, can detect stress levels at all stress detection points throughout the whole region of the integrated circuit. That is, by the method of detecting the stress using the compact model according to some example embodiments, the full-chip stress simulation that detects the stress throughout the whole region of the integrated circuit may be performed.

Further, a conventional stress simulation is performed to prevent degradation of a performance of an element (e.g., mobility of a transistor). However, the method of detecting the stress using the compact model according to some example embodiments may be performed to prevent an occurrence of a dislocation or a crack between adjacent patterns having different materials.

As described above, the method of detecting the stress according to some example embodiments may detect the stress level at each stress detection point by using an equation of the areas of the second pattern at the divided regions, or by using the area-based compact model. Accordingly, the method of detecting the stress according to some example embodiments may be rapidly performed, and the full-chip stress simulation that detects the stress throughout the whole region of the integrated circuit may be performed.

FIG. 3is a diagram for describing an example of a step of dividing a region including a stress detection point in a method of detecting stress according to some example embodiments,FIG. 4is a diagram illustrating an example of a compact model used in a method of detecting stress according to some example embodiments,FIGS. 5A-5Gare diagrams for describing an example of a principle of superposition that may be used in a method of detecting stress according to some example embodiments, andFIG. 6is a diagram illustrating another example of a compact model used in a method of detecting stress according to some example embodiments.

Referring toFIG. 3, in a region300of an integrated circuit, a first pattern340and a second pattern350may be adjacent to each other, and may be formed from different materials. For example, the first pattern120may be an active pattern formed from silicon, and the second pattern140may be an isolation layer pattern formed from silicon oxide by a STI process. At each stress detection point301, a stress level applied to the active pattern by the isolation layer pattern may be detected.

To detect the stress level at each stress detection point301, N rectangular shaped regions310,320, and330having different sizes may be determined such that each of the N rectangular shaped regions310,320, and330has the stress detection point301as the central point, and each of the N rectangular shaped regions310,320, and330may be substantially equally divided into M divided regions311,312,313,314,321,322,323,324,331,332,333, and334, where N is an integer greater than 0 and M is an integer greater than 1. For example, a first region310having a first size may be substantially equally divided into first through fourth divided regions311,312,313, and314; a second region320having a second size greater than the first size may be substantially equally divided into fifth through eighth divided regions321,322,323, and324; and a third region330having a third size greater than the second size may be substantially equally divided into ninth through twelfth divided regions331,332,333, and334. In an example, a length L1of each side of each of the first through fourth divided regions311,312,313, and314may range from about 30 nanometers (nm) to about 500 nm; a length L2of each side of each of the fifth through eighth divided regions321,322,323, and324may range from about 500 nm to about 1.5 microns (μm); and a length L3of each side of each of the ninth through twelfth divided regions331,332,333, and334may range from about 1.5 μm to about 3 μm.

First through twelfth areas AREA11, AREA12, AREA13, AREA14, AREA21, AREA22, AREA23, AREA24, AREA31, AREA32, AREA33, and AREA34of the second pattern350at the first through twelfth divided regions311,312,313,314,321,322,323,324,331,332,333, and334may be calculated from layout data for the integrated circuit. Further, a stress level at the stress detection point301may be calculated by using an L-th order equation of the first through twelfth areas AREA11, AREA12, AREA13, AREA14, AREA21, AREA22, AREA23, AREA24, AREA31, AREA32, AREA33, and AREA34of the second pattern350at the first through twelfth divided regions311,312,313,314,321,322,323,324,331,332,333, and334, where L is an integer greater than 0.

In some example embodiments, the stress level at the stress detection point301may be calculated by using a first-order equation400illustrated inFIG. 4. For example, as illustrated inFIG. 4, the stress level STRESS at the stress detection point301may be calculated by calculating a sum of a first coefficient CO, a product C11*AREA11of a second coefficient and the first area, a product C12*AREA12of a third coefficient and the second area, a product C13*AREA13of a fourth coefficient and the third area, a product C14*AREA14of a fifth coefficient and the fourth area, a product C21*AREA21of a sixth coefficient and the fifth area, a product C22*AREA22of a seventh coefficient and the sixth area, a product C23*AREA23of an eighth coefficient and the seventh area, a product C24*AREA24of a ninth coefficient and the eighth area, a product C31*AREA31of a tenth coefficient and the ninth area, a product C32*AREA32of an eleventh coefficient and the tenth area, a product C33*AREA33of a twelfth coefficient and the eleventh area, and a product C34*AREA34of a thirteenth coefficient and the twelfth area. This first-order equation400, or the division of the region300having the stress detection point301at the center and the first-order equation400, may be referred to as a “compact model” or an “area-based compact model” for detecting the stress of the integrated circuit.

As illustrated inFIGS. 5A-5G, in calculating a stress level at each stress detection point501a, a principle of superposition may be applied. For example, in a case where first through third regions511a,512a, and513aof a first pattern510are located near a stress detection point501aof the first pattern510, the stress detection point501amay have a stress level of about 598 megapascals (MPa), as illustrated inFIG. 5A. With respect to this example, the stress level at the stress detection point501bmay be increased by about 37 MPa in a case where the first region511aof the first pattern510is removed and a second pattern520is disposed at the removed region as illustrated inFIG. 5B, the stress level at the stress detection point501cmay be increased by about 27 MPa in a case where the second region512aof the first pattern510is removed and the second pattern520is disposed at the removed region as illustrated inFIG. 5C, and the stress level at the stress detection point501dmay be increased by about 34 MPa in a case where the third region513aof the first pattern510is removed and the second pattern520is disposed at the removed region as illustrated inFIG. 5D. Further, in a case where the first and second regions511aand512aof the first pattern510are removed and the second pattern520is disposed at the removed region as illustrated inFIG. 5E, the stress level at the stress detection point501emay be calculated by adding an increment of the stress level when the first region511ais removed, or about 37 MPa and an increment of the stress level when the second region512ais removed, or about 27 MPa according to the principle of superposition, which may be substantially the same as or similar to an actual stress level of about 661 MPa. In a case where the first and third regions511aand513aof the first pattern510are removed and the second pattern520is disposed at the removed region as illustrated inFIG. 5F, the stress level at the stress detection point501fmay be calculated by adding an increment of the stress level when the first region511ais removed, or about 37 MPa and an increment of the stress level when the third region513ais removed, or about 34 MPa according to the principle of superposition, which may be substantially the same as or similar to an actual stress level of about 670 MPa. In a case where the first through third regions511a,512a, and513aof the first pattern510are removed and the second pattern520is disposed at the removed region as illustrated inFIG. 5G, the stress level at the stress detection point501gmay be calculated by adding an increment of the stress level when the first region511ais removed, or about 37 MPa, an increment of the stress level when the second region512ais removed, or about 27 MPa, and an increment of the stress level when the third region513ais removed, or about 34 MPa according to the principle of superposition, which may be substantially the same as or similar to an actual stress level of about 694 MPa. As described above, the principle of superposition is applied in calculating the stress level, or the stress level is linearly increased or decreased according to whether the second pattern520exists or not, which may mean that the stress level at each stress detection point may be accurately detected by using the first-order equation400illustrated inFIG. 4. Further, in some example embodiments, the stress levels may be calculated at some stress detection points and, with respect to other stress detection points, the stress levels may be calculated by adding or subtracting the calculated stress levels using the principle of superposition.

In some example embodiments, the stress level at the stress detection point301may be calculated by using a second-order equation600illustrated inFIG. 6. For example, as illustrated inFIG. 6, the stress level STRESS at the stress detection point301may be calculated by calculating a sum of a coefficient CO (or a constant), first-order terms of the areas of the second pattern520(e.g., C11*AREA11, C12*AREA12, C13*AREA13, C14*AREA14, C21*AREA21, C22*AREA22, C23*AREA23, C24*AREA24, C31*AREA31, C32*AREA32, C33*AREA33and C34*AREA34), and second-order terms of the areas of the second pattern520(e.g., C111*AREA11^2, C112*AREA11*AREA12, C113*AREA11*AREA13, C114*AREA11*AREA14, C122*AREA12^2, C123*AREA12*AREA13, C124*AREA12*AREA14, C133*AREA13^2, C134*AREA13*AREA14, C144*AREA14^2, C211*AREA21^2, C212*AREA21*AREA22, C213*AREA21*AREA23, C214*AREA21*AREA24, C222*AREA22^2, C223*AREA22*AREA23, C224*AREA22*AREA24, C233*AREA23^2, C234*AREA23*AREA24, C244*AREA24^2, C311*AREA31^2, C312*AREA31*AREA32, C313*AREA31*AREA33, C314*AREA31*AREA34, C322*AREA32^2, C323*AREA32*AREA33, C324*AREA32*AREA34, C333*AREA33^2, C334*AREA33*AREA34and C344*AREA34^2). Further, in some example embodiments, the stress level at the stress detection point301may be calculated by using a third-order equation or a higher-order equation.

As described above, in the method of detecting the stress according to some example embodiments, the stress level at each stress detection point may be calculated using the compact model illustrated inFIG. 4orFIG. 6. Accordingly, the method of detecting the stress according to some example embodiments may be rapidly performed, and a full-chip stress simulation for detecting stress throughout the whole region of the integrated circuit may be performed.

FIG. 7is a diagram for describing another example of a step of dividing a region including a stress detection point in a method of detecting stress according to some example embodiments, andFIG. 8is a diagram for describing still another example of a step of dividing a region including a stress detection point in a method of detecting stress according to some example embodiments.

In some example embodiments, as illustrated inFIG. 7, to detect a stress level at each stress detection point701, N rectangular shaped regions having different sizes may be determined such that each of the N rectangular shaped regions has the stress detection point701as the central point, and each of the N rectangular shaped regions may be substantially equally divided into M divided regions. For example, a first region710having a first size may be substantially equally divided into first through eighth divided regions711,712,713,714,715,716,717, and718; a second region720having a second size greater than the first size may be substantially equally divided into ninth through sixteenth divided regions721,722,723,724,725,726,727, and728; and a third region730having a third size greater than the second size may be substantially equally divided into seventeenth through twenty-fourth divided regions731,732,733,734,735,736,737, and738.

In some example embodiments, as illustrated inFIG. 8, to detect a stress level at each stress detection point801, N circular shaped regions having different sizes may be determined such that each of the N circular shaped regions has the stress detection point801as the central point, and each of the N circular shaped regions may be substantially equally divided into M divided regions. For example, a first region810having a first size may be substantially equally divided into first through fourth divided regions811,812,813, and814; a second region820having a second size greater than the first size may be substantially equally divided into fifth through eighth divided regions821,822,823, and824; and a third region830having a third size greater than the second size may be substantially equally divided into ninth through twelfth divided regions831,832,833, and834.

AlthoughFIGS. 3, 7, and 8illustrate examples where three regions having different sizes are divided with respect to each detection point, according to some example embodiments, the number of the regions, or N, may be any integer greater than 0. Further, althoughFIGS. 3 and 8illustrate examples where each region is divided into 4 divided regions, andFIG. 7illustrates an example where each region is divided into 8 divided regions, according to some example embodiments, the number of the divided regions for each region, or M, may be any integer greater than 1. Further, althoughFIGS. 3 and 7illustrate examples where at least one rectangular shaped region including the stress detection point is divided, andFIG. 8illustrates an example where at least one circular shaped region including the stress detection point is divided, according to some example embodiments, the region including the stress detection point may have any shape.

FIG. 9is a diagram illustrating a computing system that detects stress of an integrated circuit according to some example embodiments.

Referring toFIG. 9, a computing system900may detect stress of an integrated circuit including first and second patterns formed from different materials. The computing system900may include a memory device910into which layout data920for the integrated circuit and a stress detection tool950for detecting the stress of the integrated circuit are loaded, and a processor that executes the stress detection tool950loaded into the memory device910.

The memory device910may be a main memory of the computing system900, and may store data required for operations of the computing system900. In some example embodiments, the memory device910may be implemented by a volatile memory, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a mobile dynamic random access memory (mobile DRAM), a dual data rate (DDR) synchronous DRAM (SDRAM), a low power DDR (LPDDR) SDRAM, a graphics DDR (GDDR) SDRAM, a Rambus DRAM (RDRAM), etc.

The processor may load the layout data920for the integrated circuit and the stress detection tool950from a storage device, such as a solid state drive (SSD), a hard disk drive (HDD), a memory card, a compact disc read-only memory (CD-ROM), etc., into the memory device910. In some example embodiments, the layout data920may be generated using a hardware description language (HDL). For example, the layout data920may be Verilog layout data, Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) layout data, or the like.

The processor may execute the stress detection tool950loaded into the memory device910. The stress detection tool950may determine at least one stress detection point based on the layout data920, and may detect a stress level at the stress detection point by using a compact model980. Here, the compact model980may be an equation or information about the equation of areas of the second pattern at divided regions for the stress detection point. According to some example embodiments, the compact model980may be a program code included in the stress detection tool950, or may be implemented as a separate electronic file from an electronic file of the stress detection tool950. In some example embodiments, the stress detection tool950may include a point determining module960and a stress detecting module970.

The point determining module960may determine at least one stress detection point of the first pattern based on the layout data920. By using the compact model980, the stress detecting module970may divide a region including the stress detection point into a plurality of divided regions, may calculate areas of the second pattern at the divided regions, respectively, and may detect a stress level applied to the stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

In some example embodiments, the stress detection tool950may add a layer representing the stress level to the layout data920, and may inform a designer990which position of the integrated circuit has a high stress level by using the added layer. For example, the added layer may mark the position having the high stress level with a desired color (that may or may not be predetermined) or a desired value (that may or may not be predetermined).

As described above, the computing system900for detecting the stress of the integrated circuit according to some example embodiments may detect the stress level at each stress detection point by using the equation of the areas of the second pattern at the divided regions for each stress detection point, or by using the area-based compact model. Accordingly, the computing system900may rapidly detect the stress level, and a full-chip stress simulation that detects the stress throughout the whole region of the integrated circuit may be performed.

FIG. 10is a flowchart illustrating a method of training a compact model for detecting stress of an integrated circuit according to some example embodiments,FIG. 11Ais a graph illustrating a full-chip stress distribution of an integrated circuit, andFIG. 11Bis a graph illustrating a distribution of sample stress detection points.

Referring toFIG. 10, in a method of training a compact model for detecting stress of an integrated circuit, a compact model-based stress simulation may be performed on the integrated circuit to extract a stress distribution of the integrated circuit (S1010). In some example embodiments, the compact model-based stress simulation may be a full-chip stress simulation for the integrated circuit using the compact model, such as the compact model illustrated inFIG. 4orFIG. 6. For example, stress levels at all stress detection points (e.g., all convex points, all concave points, and all projected points of a first pattern) throughout the whole region of the integrated circuit may be detected by a stress detection method illustrated inFIG. 1.

Sample stress detection points may be selected based on the stress distribution of the integrated circuit extracted by the compact model-based stress simulation (S1030). In some example embodiments, the stress distribution of the integrated circuit may be a full-chip stress distribution of the integrated circuit, and the sample stress detection points may be selected based on the full-chip stress distribution of the integrated circuit. For example, in a case where a full-chip stress distribution1110illustrated inFIG. 11Ais extracted as a result of the compact model-based stress simulation, the sample stress detection points may be selected such that a sample point distribution1130(or a distribution of the sample stress detection points) has a similar shape to that of a full-chip stress distribution1110a, as illustrated inFIG. 11B. In an example, when selecting 1,000 sample stress detection points from a total of 30 million (30 M) stress detection points of the integrated circuit, the sample stress detection points may be selected such that the sample point distribution1130of the 1,000 sample stress detection points has the substantially the same shape as that of a scaled-down full-chip stress distribution1110a. The vertical axis of the distribution is graduated at one million (1 M) points, two million (2 M) points, three million (3 M) points, and four million (4 M) points.

A rigorous stress simulation may be performed on the sample stress detection points (S1050). For example, the rigorous stress simulation may be performed using a finite element method (FEM) or a finite analytic method (FAM).

The compact model may be calibrated based on a result of the rigorous stress simulation (S1070). For example, the compact model may be an equation of areas of a pattern at divided regions for each stress detection point, and coefficients of the equation may be calibrated based on the result of the rigorous stress simulation. For example, the coefficients of the equation may be calibrated using a root-mean-square (RMS) method or the like such that stress levels at 1,000 sample stress detection points calculated using the equation may approximate the result of the rigorous stress simulation at the sample stress detection points.

As described above, in the method of training the compact model according to some example embodiments, the sample stress detection points at which the rigorous stress simulation is to be performed are selected based on the stress distribution (e.g., the full-chip stress distribution) of the integrated circuit and, thus, the accuracy of the compact model may be improved in all stress ranges of the integrated circuit. Further, unlike a typical training method that compares a value obtained by a compact model with an actual measured value, the method of training the compact model according to some example embodiments may be performed based on a comparison of the value obtained by the compact model and a value obtained by a simulation (e.g., the rigorous stress simulation).

FIG. 12is a diagram illustrating a computing system that trains a compact model for detecting stress of an integrated circuit according to some example embodiments.

Referring toFIG. 12, a computing system1200that trains a compact model1280for detecting stress of an integrated circuit may include a memory device1210into which layout data1220for the integrated circuit, the compact model1280, a stress detection tool1250for detecting the stress of the integrated circuit, and a training tool1260for training the compact model1280are loaded, and a processor that executes the stress detection tool1250and the training tool1260loaded into the memory device1210. According to some example embodiments, the stress detection tool1250and the training tool1260may be implemented as a single electronic file, or may be implemented as separate electronic files.

The stress detection tool1250executed by the processor may perform a stress simulation (e.g., a full-chip stress simulation) on the integrated circuit by using the compact model1280. For example, the stress detection tool1250may detect stress levels at all stress detection points (e.g., all convex points, all concave points, and all projected points) of the integrated circuit. A stress distribution (e.g., a full-chip stress distribution) of the integrated circuit may be extracted by the stress simulation.

The training tool1260executed by the processor may select sample stress detection points based on the stress distribution (e.g., the full-chip stress distribution) of the integrated circuit, may perform a rigorous stress simulation on the sample stress detection points, and may calibrate the compact model1280based on a result of the rigorous stress simulation.

FIG. 13is a flowchart illustrating a method of relaxing stress of an integrated circuit according to some example embodiments, andFIGS. 14A through 14Dare diagrams illustrating examples of dummy patterns inserted by a method of relaxing stress according to some example embodiments.

Referring toFIG. 13, in an integrated circuit including first and second patterns that are adjacent to each other and are formed from different materials, at least one stress detection point of the first pattern may be determined (S1310). In some example embodiments, to perform the full-chip stress simulation on the integrated circuit, stress levels may be detected at all stress detection points throughout the whole region of the integrated circuit. A region including each stress detection point may be divided into a plurality of divided regions (S1330), areas of the second pattern may be calculated at the divided regions, respectively (S1350), and a stress level applied to each stress detection point of the first pattern by the second pattern may be calculated based on the areas of the second pattern at the divided regions (S1370).

If the detected stress level at each stress detection point is less than or equal to a desired value (that may or may not be predetermined) (S1380: NO), a layout for the region including the stress detection point may not be changed. If the detected stress level at one or more stress detection points is greater than the desired value (that may or may not be predetermined) (S1380: YES), a dummy pattern may be inserted near the stress detection point of the first pattern (S1390). In some example embodiments, the dummy pattern may be formed from the same material as the first pattern. In some example embodiments, the dummy pattern may be a ring type dummy pattern, a rectangle type dummy pattern, a polygon type dummy pattern, an attached type dummy pattern, or the like.

In some example embodiments, as illustrated inFIG. 14A, a ring type dummy pattern1430amay be added to a layout data for the integrated circuit such that the ring type dummy pattern1430asurrounds a region1410aof the first pattern including the stress detection point having the stress level greater than the desired value (that may or may not be predetermined). In some example embodiments, as illustrated inFIG. 14B, a rectangle type dummy pattern1430bmay be added to the layout data for the integrated circuit such that the rectangle type dummy pattern1430bis located near or around a region1410bof the first pattern including the stress detection point having the stress level greater than the desired value (that may or may not be predetermined). In some example embodiments, as illustrated inFIG. 14C, a polygon type dummy pattern1430cmay be added to the layout data for the integrated circuit such that the polygon type dummy pattern1430cis located near or around a region1410cof the first pattern including the stress detection point having the stress level greater than the desired value (that may or may not be predetermined). In some example embodiments, as illustrated inFIG. 14D, an attached type dummy pattern1430dmay be added to the layout data for the integrated circuit such that the attached type dummy pattern1430dis attached to a wiring1450(e.g., an active guard ring pattern) surrounding a region1410dof the first pattern including the stress detection point having the stress level greater than the desired value (that may or may not be predetermined).

As described above, the dummy pattern may be inserted near the stress detection point and, thus, the area of the second pattern near the stress detection point may be reduced, which may result in a reduction of the stress level at the stress detection point. Accordingly, a dislocation or a crack of the integrated circuit may be prevented.

FIG. 15is a diagram illustrating a computing system that relaxes stress of an integrated circuit according to some example embodiments.

Referring toFIG. 15, a computing system1500that relaxes stress of an integrated circuit that are formed from different materials may include a memory device1510into which layout data1520for the integrated circuit, a stress detection tool1550for detecting the stress of the integrated circuit, and a stress relaxation tool1570for relaxing the detected stress, and a processor that executes the stress detection tool1550and the stress relaxation tool1570loaded into the memory device1510. According to some example embodiments, the stress detection tool1550and the stress relaxation tool1570may be implemented as a single electronic file, or may be implemented as separate electronic files.

The stress detection tool1550executed by the processor may detect the stress of the integrated circuit by using a compact model1580. For example, the stress detection tool1550may determine at least one stress detection point of the first pattern based on the layout data1520, may divide a region including the stress detection point into a plurality of divided regions, may calculate areas of the second pattern at the divided regions, respectively, and may detect a stress level applied to the stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

The stress relaxation tool1570executed by the processor may modify the layout data1520for the integrated circuit to insert a dummy pattern near the stress detection point of the first pattern when the detected stress level is greater than a desired value (that may or may not be predetermined). For example, as illustrated inFIGS. 14A through 14D, the stress relaxation tool1570may insert a ring type dummy pattern1430a, a rectangle type dummy pattern1430b, a polygon type dummy pattern1430c, an attached type dummy pattern1430d, or the like. Accordingly, a dislocation or a crack of the integrated circuit may be prevented.

The present inventive concept may be applied to any semiconductor circuit design and verification tool, device, system, or method. For example, the present inventive concept may be applied to an integrated circuit, or a verification tool or device for the integrated circuit.

The algorithms discussed in this application (e.g., for detecting stresses, for training compact models, and for relaxing stresses) may be used in more general purpose apparatuses and/or methods of controlling apparatuses. For example, the algorithms may be used in apparatuses for more general electrical or electronic systems and/or for controlling such apparatuses for detection, training, and/or adjusting.

The methods described above may be written as computer programs and can be implemented in general-use digital computers that execute the programs using a computer-readable recording medium. In addition, a structure of data used in the methods may be recorded in a computer-readable recording medium in various ways. Examples of the computer-readable recording medium include storage media such as magnetic storage media (e.g., ROM (Read-Only Memory), RAM (Random-Access Memory), USB (Universal Serial Bus), floppy disks, hard disks, etc.) and optical recording media (e.g., CD-ROMs (Compact Disc Read-Only Memories) or DVDs (Digital Video Discs)).

In addition, some example embodiments may also be implemented through computer-readable code/instructions in/on a medium (e.g., a computer-readable medium) to control at least one processing element to implement some example embodiments. The medium may correspond to any medium/media permitting the storage and/or transmission of the computer-readable code.

The computer-readable code may be recorded/transferred on a medium in a variety of ways, with examples of the medium including recording media, such as magnetic storage media (e.g., ROM, floppy disks, hard disks, etc.) and optical recording media (e.g., CD-ROMs or DVDs), and transmission media such as Internet transmission media. Thus, the medium may be such a defined and measurable structure including or carrying a signal or information, such as a device carrying a bitstream according to some example embodiments. The media may also be a distributed network, so that the computer-readable code is stored/transferred and executed in a distributed fashion. Furthermore, the processing element could include a processor or a computer processor, and processing elements may be distributed and/or included in a single device.

In some example embodiments, some of the elements may be implemented as a ‘module’. According to some example embodiments, ‘module’ may be interpreted as software-based components or hardware components, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), and the module may perform certain functions. However, the module is not limited to software or hardware. The module may be configured so as to be placed in a storage medium which may perform addressing, or to execute one or more processes.

For example, modules may include components such as software components, object-oriented software components, class components, and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcodes, circuits, data, databases, data structures, tables, arrays, and variables. Functions provided from the components and the modules may be combined into a smaller number of components and modules, or be separated into additional components and modules. Moreover, the components and the modules may execute one or more central processing units (CPUs) in a device.

Some example embodiments may be implemented through a medium including computer-readable codes/instructions to control at least one processing element of the above-described embodiment, for example, a computer-readable medium. Such a medium may correspond to a medium/media that may store and/or transmit the computer-readable codes.

The computer-readable codes may be recorded in a medium or be transmitted over the Internet. For example, the medium may include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disc, an optical recording medium, or a carrier wave such as data transmission over the Internet. Further, the medium may be a non-transitory computer-readable medium. Since the medium may be a distributed network, the computer-readable code may be stored, transmitted, and executed in a distributed manner. Further, for example, the processing element may include a processor or a computer processor, and be distributed and/or included in one device.