Switched mode power supply

A switching power converter includes an inductor coupled to a terminal operably supplied with an input voltage. A semiconductor switch is coupled to the inductor and configured to enable and disable an input current passing through the inductor in accordance with a drive signal. A current sense circuit is coupled to the inductor or the semiconductor switch and is configured to generate a current sense signal representing the input current passing through the inductor or the semiconductor switch. A control circuit receives the current sense signal and is configured to: close the semiconductor switch regularly in accordance with a clock frequency, to integrate the current sense signal thus providing an integrated current sense signal to compare the integrated current sense signal with a threshold that is a function of the input voltage.

TECHNICAL FIELD

The present disclosure relates to a switched mode power supply (SMPS) also referred to as switching power converters. Particular embodiments describe an over-current or over-power protection for the switching power converter is described.

BACKGROUND

Switched mode power supplies (SMPS) are becoming increasingly common as power supplies for a great variety of applications. For example, SMPS may be used as power supplies for driving LEDs, which may be used to replace incandescent lamps for illumination purposes. However, many other applications for switching power converters exist as practically any electric and electronic device which requires a DC power supply voltage (or current) can be connected to the power grid using SMPS.

Switching power converter may be operated in various modes. For example, switching converters may be operated, inter alia, with a fixed switching frequency and a variable on-time of the switch and with a fixed on-time of the switch and variable frequency. Regardless of whether a switching power converter operates with a fixed or a variable frequency, switching power converters may operate in continuous current mode (CCM) or discontinuous current mode (DCM). As different modes of operation (DCM with fixed on-time, DCM with fixed frequency, CCM with fixed frequency, etc.) usually require different concepts of controlling (regulating) the output voltage or the output current, some switching power converters are designed to operate only in a single mode (e.g., CCM, fixed frequency). However, switching power converters are often required to be able to provide a specific constant DC output voltage (or current) for a great range of AC input voltages (e.g., from 85 to 270 volts). In this case, the switching power converter is usually designed to handle both modes of operation, DCM and CCM, and a mode-switch from CCM to DCM occurs when the AC input voltage exceeds a defined threshold voltage, which is pre-set by circuit design.

To accomplish the control task mentioned above the input current (which is switched on and off by a power semiconductor switch) of the power switching converter is usually measured, e.g., using a measurement resistor that provides a voltage drop proportional to the current passing through it. The measured input current is usually compared to a reference value and a switch-off of the power semiconductor switch is triggered when the input current exceeds a threshold defined by this reference value. However, the power semiconductor does not switch-off the input current (sometimes also referred to as primary current) immediately with zero delay. Not only the power semiconductor switch exhibits an inherent switch-off delay. Furthermore, the comparator circuit (which compares the measured input current with the mentioned threshold) and other circuit components included in the control circuit (which controls the switching operation of the power converter) cause additional delays. As a result an over-shot of the input current (primary current) occurs, which may lead to excessive power dissipation in the semiconductor switch.

To avoid the mentioned excessive power dissipation, the effect of the mentioned delays should be eliminated (or at least partly compensated for). However, in known solutions this delay time compensation is either designed for DCM or for DCM. Thus, it would be useful to improve the control circuit of a SMPS such that excessive power dissipation is avoided independent form the mode of operation (DCM, CCM) of the switching power converter.

SUMMARY OF THE INVENTION

A switching power converter is disclosed. In accordance with one aspect of the invention, the switching power converter includes an inductor coupled to a terminal operably supplied with an input voltage and a semiconductor switch coupled to the inductor and configured to enable and disable an input current passing through the inductor in accordance with a drive signal. The switching power converter further includes a current sense circuit, which is coupled to the inductor or the semiconductor switch and configured to generate a current sense signal that represents the input current passing through the inductor or the semiconductor switch. A control circuit receives the current sense signal and is configured to close the semiconductor switch regularly in accordance with a clock frequency, to integrate the current sense signal thus providing an integrated current sense signal, to compare the integrated current sense signal with a threshold, and to open the semiconductor switch dependent on the result of the comparison. The threshold is a function of the input voltage.

In accordance with another aspect of the invention, the switching power converter includes an inductor coupled to a terminal operably supplied with an input voltage and a semiconductor switch coupled to the inductor and configured to enable and disable an input current passing through the inductor in accordance with a drive signal. A current sense circuit is coupled to the inductor or the semiconductor switch and configured to generate a current sense signal, which represents the input current passing through the inductor or the semiconductor switch. A control circuit receives the current sense signal as well as a signal representing the input voltage. Moreover, the control circuit includes a threshold generator that receives the signal representing the input voltage. The threshold generator is configured to generate a threshold, which is a function of the input voltage. The control circuit further includes an integrator that receives the current sense signal. The integrator is configured to generate a signal representing the integrated input current. Furthermore, the control circuit includes a comparator that receives the threshold and the signal representing the integrated input current. The comparator is configured to indicate when he the signal representing the integrated input current reaches the threshold. A driver circuit is configured to switch on the semiconductor switch periodically in accordance with a clock signal and to switch it off when the comparator indicates that the signal representing the integrated input current has reaches the threshold.

In addition to the above a method for operating a power converter is disclosed, wherein power converter may comprise an inductor coupled to a terminal operably supplied with an input voltage. In accordance with another aspect of the invention the method comprises enabling and disabling an input current, which passes through the inductor in accordance with a drive signal thereby using a semiconductor switch, which is coupled to the inductor. A current sense signal representing the input current passing through the inductor or the semiconductor switch is generated. The method further comprises closing the semiconductor switch regularly in accordance with a clock frequency, integrating the current sense signal thus providing an integrated current sense signal, and comparing the integrated current sense signal with a threshold, which is a function of the input voltage. The semiconductor switch is opened dependent on the result of the comparison.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The exemplary embodiments of the present invention include a flyback converter which is a commonly used converter topology in applications in which a galvanic isolation is needed. However, the principles discussed below with regard to a flyback converter may also be applied to other converter topologies such as, e.g., floating buck converters or the like. Excessive power dissipation may be avoided by integrating the input (primary) current sense signal and comparing this integrated signal with a threshold signal. This threshold signal may depend on the input voltage applied to the switching power converter.

FIG. 1illustrates a switching power converter circuit that includes a transformer1having a primary winding LPand a secondary winding LS. An auxiliary winding LAUXmay be used for providing a supply voltage for the control circuitry that controls the operation of the power semiconductor switch T1which is coupled in series to the primary winding LPsuch that the input current (further referred to as primary current iP) passing through the primary winding LPcan be switched on and off by the semiconductor switch T1in accordance with a drive signal VG(e.g., a gate voltage signal or a gate current signal in case of a MOSFET or an IGBT). The input voltage VINis applied to the primary winding LPduring the time interval the semiconductor switch T1is switched on (i.e., during the on-time). The input voltage VINessentially drops across the power semiconductor switch T1during the time interval the semiconductor switch T1is switched off (i.e., during the off-time). For measuring the primary current iPa current sense circuit may be coupled to the power semiconductor switch T1. In the present example ofFIG. 1a current sense resistor RCSis connected between the power semiconductor switch T1and ground terminal GND1such that the primary current passing through the transistor T1also passes through the current sense resistor RCS. The voltage drop VCSacross the resistor RCSis proportional to the primary current iP. It should be noted that, however, other current measurement techniques should be used instead of the current sense resistor RCS. Current measurement could also be accomplished using, for example, a sense transistor coupled to the load transistor.

The input voltage VINmay have a waveform corresponding to a (full-wave) rectified sine signal. This is the case when a rectifier is used to couple the switching power converter to the AC power grid. In the present example, a bridge rectifier circuit2is used to convert the AC line voltage VACto the input voltage VIN. In the present example, it is desired that the switching power converter can handle AC line voltages of 85 to 270 volts rms (rms=root means square) while maintaining the output voltage (or output current) at a specific level. This interval from 85 to 270 volts is, however, just an example, and the actual input voltage range may depend on the actual application. Nevertheless, in order to be able to work properly with the power grids in various countries all over the world the input voltage range is usually comparably broad.

The secondary winding LSof the transformer1is coupled to the output of the switching power converter. A rectifier diode D2is coupled between a first end of the secondary winding LSand an output terminal, at which the output voltage VOUTis provided. The second end of the secondary winding is coupled to ground terminal GND2. The output voltage VOUTmay be buffered using an output capacitor COUT, which is coupled between the output terminal and the corresponding ground terminal GND2. It should be noted that the circuit components coupled to the primary side of the transformer1are supplied with respect to the “primary side ground” GND1wherein the circuit components coupled to the secondary side of the transformer1are supplied with respect to the “secondary side ground” GND2. The ground terminals GND1, GND2of both sides are isolated from each other to ensure full galvanic separation between the primary side and the secondary side. However, the ground terminals GND1, GND2of both sides may be coupled via a capacitor (not shown in the Figure).

In order to regulate the output voltage VOUTor the output current (further referred to as secondary current iS) the output terminal may be coupled to a feedback circuit4which is configured to generate a feedback signal SFB(e.g., a feedback voltage) from the output voltage VOUTor the secondary current IS. Further, the feedback circuit4provides a galvanic isolation between its input and its output which may be accomplished, for example, using an opto-coupler. Circuits providing a feedback signal, which represents the output voltage or secondary current and including an opto-coupler for galvanic isolation are per se known in the field and, therefore, not discussed in detail herein.

The feedback signal SFBas well as the current sense signal VCSare supplied to a control circuit5which is configured to generate, dependent therefrom the drive signal VGfor the semiconductor switch. Thereby, the control circuit5incorporates a control law to regulate the output voltage VOUTor the secondary current iSto match a specific (pre-set or adjustable) desired value. The control circuit4may have its own power supply. In the present example, the control circuit5is supplied by the capacitor CVCwhich is charged via the rectifier diode DVCby the auxiliary winding. However, a different power supply for the control circuit may be applicable. The function of the control circuit4is discussed below in more detail with reference to the timing diagrams shown inFIGS. 2A-B.

Two different cases are illustrated in the timing diagrams ofFIGS. 2A-B. The diagrams inFIG. 2Arefer to switching operation in the discontinuous current mode (DCM) whereas the diagrams inFIG. 2Brefer to switching operation in the continuous current mode (CCM). The mode of operation may depend on the level of the input voltage VIN. In both modes of operation (DCM and CCM) the time instants t1and t5, at which the semiconductor switch is switched on, and the time instants t2and t6, at which the semiconductor switch is switched off, may be time-triggered or event-triggered. In a switching power converter that operates with a fixed frequency and variable on-time (i.e., a variable duty-cycle) these time instants are time-triggered. In a switching power converter that performs a quasi-resonant oscillation, the switch-on time as well as the switch-off time may be event-triggered. The “event,” which triggers a switch-off of the semiconductor switch, may be, for example, the primary current iPreaching a threshold value VREF/RCS, whereas the event, which triggers a switch-on of the semiconductor switch, may be the voltage across the semiconductor switch being at a (local) minimum. For further discussion, a flyback converter operated at a fixed frequency fS(fS=TS−1) and having a variable duty cycle D (D=TON/TS) is considered as an illustrative example.

The following considerations assume stationary operation in DCM as illustrated in the diagrams inFIG. 2A. A switching cycle starts at time instant t1and ends at time instant t4when the subsequent switching cycle begins. That is, the period TSof one cycle can be calculated as:
TS=(t4−t1)=fS−1.

The drive signal (e.g., the gate voltage VG), which controls the switching state of the semiconductor switch T1, is switched on at time instant t1and switched off at time instant t2. That is, the on-time TONcan be calculated as
TON=(t2−t1)=D·TS=D·(t4−t1),
wherein D denotes the duty cycle (Dε[0, 1]). The remaining time of one cycle is the off-time TOFF, which can be calculated as
TOFF=(t4−t2)=(1−D)·TS.

During the on-time TONthe primary current iPrises from zero to its peak value iPP. The gradient of the current ramp is VIN/LP(LPrepresenting the inductance of the primary winding) which is almost constant if the input voltage VINdoes not significantly change during one cycle. At time instant t2the energy EDCMstored in the inductor can be calculated as
EDCM(t2)=LP·iPP2/2.

As the semiconductor switch T1is switched off at time instant t2the energy EDCMis “transferred” from the primary side to the secondary side of the transformer1(seeFIG. 1) due to inductive coupling. The secondary current iSis zero during the on-time TON(as the rectifier diode D2is reversed biased) and falls from its initial peak value iSP, which occurs at time instant t2, down to zero, which is reached at time instant t3. The secondary current iSremains zero between time instants t3and t4. It should be noted that delay times (rise and fall times) are neglected in the present discussion in order to allow concentration on basic function of the circuit. The secondary peak current iSPfulfills the equation EDCM(t2)=LS·iSP2/2=LP·iPP2/2, wherein LSrepresents the inductance of the secondary winding. The gradient of the secondary current ramp during the off-time TOFFis (VOUT+VD2)/LSwherein the VD2is the forward voltage of the rectifier diode D2. In contrast to CCM, the DCM is characterized in that the secondary current iSdrops (beginning at iSP) to zero during a switching cycle whereas this is not the case during CCM. In the present example, the time t2.

Continuous current mode (CCM) is illustrated in the diagrams inFIG. 2B. A switching cycle starts at time instant t5and ends at time instant t7when the subsequent switching cycle begins. In stationary operation, the initial primary current iP0(iP0=iP(t5)), which would be zero in DCM, is greater than zero in CCM as the energy ECCM“stored” in the transformer windings LPand LS, respectively, never falls to zero during the off time TOFF. At time instant t5the semiconductor switch T1is closed (drive signal VGis at a high level) and the primary current ipstarts to ramp up from the initial value iP0to the peak level iPP, wherein iPP=iP0+ΔiP. When the primary current reaches its peak value iPP(defined by a threshold VREF/RCS) at time instant t6the semiconductor switch T1is switched off and the secondary current ramps down from its peak value iSPto its final value iS0, wherein iSP=iS0+ΔiS. The energy “stored” in the transformer varies from ECCMmin=LS·iS02/2=LP·iP02/2 to ECCMmax=LS·iSP2/2=LP·iPP2/2. At the time instant t7the cycle starts over again, the secondary current iSis blocked by the rectifier diode D2, and the primary current “jumps” to its initial value iP0and ramps up as in the previous cycle.

For the further considerations it is interesting to calculate the average input power PIN, which is
PIN=(½)·LP·iPP2in DCM,
whereas it is
PIN=(½)·LP·iPAVG2in CCM.

Although the theoretic calculations for the input power are quite different from the two equations above, it is important to note that the input power is related to the area under the primary current waveforms. Thus, a value representing the input power may be obtained by integrating the primary current sense signal VCSover one switching period. That is, the integrated value represents the input power.

As mentioned above, the time instant, at which the semiconductor switch T1is switched off, may be determined by comparing the primary current sense signal VCS(see FIG.1) with a threshold value VREF. That is, the semiconductor switch T1is switched off when the following inequality holds true: VCS≧VREFwhich is equivalent with iP≧VREF/RCS. Such a strategy for determining the switch-off time instant of the semiconductor switch T1may lead to the power overshot mentioned further above and the need for compensating delays. According to the exemplary embodiments described herein the switch-off time instant is determined in a different way as illustrated inFIG. 3.

Accordingly, an integrated current sense signal VCSINTis compared with a threshold signal VTH, wherein this threshold may be a function of the input voltage VIN.FIG. 4illustrates the threshold signal VTH, which is a voltage signal in the present example, as a function of the AC line voltage VAC(VIN=|VAC|). The circuit ofFIG. 3illustrates a part of the control circuit5, which is shown inFIG. 1and which is configured to signal a switch-off of the semiconductor switch T1. The circuit includes a threshold generator circuit103that receives a signal representing the level of the input voltage VIN(or the AC line voltage VAC) and that generates a corresponding threshold signal VTHtherefrom. The circuit further includes an integrator101which receives the current sense signal VCSand which integrates this current sense signal thus providing the integrated signal VCSINT(which may be a voltage signal). A comparator102receives the two signals VTHand VCSINTand evaluates the inequality VTH<VCSINT. When this inequality holds true, an SR-latch104is reset by the comparator output (which is coupled to the reset input of the SR latch104). As a result the output signal SONof the SR-latch104is reset to a low output level, which indicates the end of the on-time of the semiconductor switch and signals a switch-off of the switch T1. The SR-latch104may be re-activated by applying an appropriate set signal, which may be generated, e.g., by a clock generator. When using a fixed switching frequency, the set signal is generated periodically dependent on the switching frequency.

FIG. 4illustrates an exemplary characteristic curve which is implemented by the threshold generator circuit103depicted inFIG. 3. As mentioned above, the input power is related to the input voltage VINand hence the over-power threshold VTH(with which the integrated current sense signal VCSINTis compared) is derived from the input voltage VIN. A typical (idealized) relationship between the over-power threshold VTHand the input voltage VINis illustrated by the bent line inFIG. 4. An implementation of this characteristic curve (represented by the bent line inFIG. 4) may be difficult. However, the curve may be approximated by at least two straight lines, i.e., by dividing the curve into sections (corresponding to input voltage intervals) and linearizing the curve in each section. The resulting simplified characteristic curve is also illustrated inFIG. 4and represented by two straight lines. That is, in the present example the characteristic curve is divided into two sections (e.g., input voltages lower or equal than about 145 volts and voltages higher than about 145 volts) wherein in each section the threshold VTHis a linear function (plus an offset) of the input voltage VIN.

FIG. 5illustrates one specific example of how to implement the general circuit shown inFIG. 3for the case that the characteristic curve shown inFIG. 4is approximated by two straight lines. The present example makes use of a “reversed” characteristic curve VTH′which can be directly obtained from the curve VTHinFIG. 4using the equation VTH′=3V−VTH. The 3V offset has to be regarded as an exemplary value which has been used in the implementation described herein. Such reversion (flipping) of the characteristic curve enables the easy implementation of the circuit ofFIG. 3. Accordingly, the control circuit5(see FIG.1), which is supplied with the current sense signal VCS, includes an integrator INT which receives the current sense signal VCSand provides the integrated signal VCSINTat its output. The output signal of the integrator INT may be amplified (gain G3), wherein the gain may be negative (e.g., G3=−1) so as to also “flip” the integrated current sense signal VCSINTin the same way as the characteristic curve inFIG. 6may be obtained from the curve inFIG. 4. The output of the amplifier AMP3(gain G3) may be shifted by adding an offset value VOS3. This operation is accomplished by the level shifter circuit LS3, whose output signal is labeled VINT. Together, the amplifier AMP3and the level shifter LS3perform the following arithmetic operation:
VINT=VOS3+G3·VCSINT.

In the present example G3=−1 and VOS3=3V, the above equation yields
VINT=3V−VCSINT.

VINTrepresents the integrated current sense value VCSINT. That is, the integrated current sense signal is reverted (flipped) in the same way as the characteristic curve representing the threshold shown inFIG. 4.

The amplifiers AMP1and AMP2as well as the level shifters LS1and LS2and the current source Q are used to generate the threshold signal VTH′, e.g., as shown inFIG. 6, which is a “reversed” version of the two-part threshold curve ofFIG. 4. As the threshold VTH(seeFIG. 4) depends on the input voltage VIN, a fraction of the input voltage VINis supplied to the circuit node TH (which may be a terminal of the control circuit4) using a resistor voltage divider formed, e.g., by the two resistors R1and R2. The current source Q is also coupled to the circuit node TH such that the current iOSsourced by the current source Q passes through the voltage divider. As a result, the voltage Vxpresent at the circuit node TH can be calculated as:
Vx=VIN·R2/(R1+R2)+iOS·R1R2/(R1+R2).

One can see, that the voltage Vxis a fraction of the input voltage VINplus an offset that is proportional to the current iOS. The voltage Vxis received at the inputs of the amplifiers AMP1and AMP2having a gain G1and G2, respectively. The amplifier output signals G1·Vxand G2·Vxare supplied to the level shifters LS1and LS2, respectively, and subjected to a level shift. The level shifters LS1and LS2provide the offset voltages VOS1and VOS2, respectively. That is, the output signals VTH1and VTH2of the level shifters LS1and LS2, respectively, can be expressed as:
VTH1=G1·Vx+VOS1, and
VTH2=G2·Vx+VOS2.

In the present exemplary implementation which has been made for testing the current iOSis 1 microamperes (iOS=1 μA), the gain G1is unity (G1=1), the gain G2is 0.16 (G2=0.16), the offset voltage VOS1is zero (VOS1=0V), and the offset voltage VOS2is 2 volts (VOS2=2V).

The output signal VTH2of the level shifter LS2may be filtered to compensate for the effect of a propagation delay between the time instant, at which a gate signal is applied to the gate of the power MOS transistor T1so as to switch it off, and the corresponding time instant, at which the actual switch-off of the transistor's load current iCSoccurs. As a result of this propagation delay, a current over-shot may occur between the time instant, the comparator102signals a reset of the SR latch104(seeFIG. 3) and the actual switch-off of the power transistor T1. This over-shot increases as the input voltage VINincreases. That is, the higher, the input voltage VIN, the higher this over-shot would be. To avoid this adverse effects of the mentioned delay a so called propagation delay compensation circuit DC2may inserted between the level shifter LS2and the respective comparator CMP2. A similar circuit may be also provided in the signal path between the level shifter LS1and the respective comparator CMP2. In the present example, however, delay compensation circuit DC2is only provided in the signal path to the comparator CMP2which is effective for thresholds VTH2corresponding to higher input voltage. In essence the delay compensation circuit DC2includes a small negative offset VOScomp(about −10 mV in the present exemplary implementation) and a low pass filter having a time constant equal or similar to the propagation delay to compensate (about 1 μs in the present exemplary implementation). The mentioned offset VOScompmay be lumped together with the offset VOS2provided by the level shifter LS2and thus the delay compensation DC2circuit may be a simple RC low pass circuit LP.

The threshold signals VTH1and VTH2which represent the “reverted” (flipped) threshold curve ofFIG. 6are fed to the non-inverting inputs of the comparators CMP1and CMP2, respectively. The inverting inputs of both comparators CMP1and CMP2receive the “reverted” (flipped) integrated current sense signal VINTdiscussed above. The outputs of the comparators CMP1and CMP2are combined by an OR-gate X1which provides, at its output, a set signal SSETwhich is received by the set-input of the SR latch104(seeFIG. 3). That is, the SR latch104is set either when signal VINTfalls below the threshold VTH1or below the threshold VTH2, wherein both threshold signals depend on the input voltage VIN. In such a manner the approximated threshold curve ofFIG. 4is implemented.

FIG. 7is a circuit diagram illustrating one exemplary implementation of the integrator INT, the amplifier AMP3and the level shifter LS3. The three components INT, AMP3and LS3are implemented together in one circuit. The current sense signal VCS, which is applied to the circuit node CS, is received by the buffer amplifier B1, which provides, at its output, such a signal to the gate of the transistor M1that the load current iCSof the transistor M1is iCS=VCS/R1. This load current is amplified and “copied” to the current path to which the capacitor CINTis coupled using the current mirrors CM1and CM2. The corresponding mirror current iCS′ charges the capacitor CINTwhich is coupled between an output current node providing the “flipped,” amplified and integrated current sense signal VINTand an internal supply voltage node providing the internal supply voltage VDD. The integration is accomplished as the capacitor “integrates” the mirror current iCS′. The capacitor voltage VCINTcan be calculated as

VCINT=∫iCS′CINT⁢ⅆt,
wherein iCS′ is the current iCStimes a gain. The second buffer amplifier B2provides a constant voltage of VOS3to the output circuit node and “pre-charges” the capacitor to a voltage of VCINT=VDD−3V while the switch SW is closed during the off-time of the power transistor T1(seeFIG. 1). Thus the output voltage VINT(see alsoFIG. 5) can be calculated as

VINT⁡(t)=⁢VDD-(∫0t⁢A·iCSCINT⁢⁢ⅆx+VCINT,0)=⁢3⁢⁢V-∫0t⁢A·VCSR1⁢CINT⁢⁢ⅆx,
wherein in the equation above iCS′=A·iCSand iCS=VCS/R1. The gain G3referred to in the description ofFIG. 5is thus G3=(A·VCS)/(R1·CINT). The time t=0 in the above equation refers to that time instant at which the power transistor T1(seeFIG. 1) closes and the primary current iPbegins to pass through the primary winding LP. It is clear from the present example ofFIG. 7that not all signals occurring in the general example ofFIG. 3necessarily have to be voltage signals. Depending on the implementation (e.g., the output of amplifier AMP3) the signals may also be current signals. Further, the order of the components illustrated in the example ofFIG. 5may be changed (e.g., the integrator INT may be placed downstream of the amplifier AMP3) provided that the function of the overall circuit is maintained.

Using the inventive concept described herein enables a significant reduction of the over-power throughout the total input voltage range. It provides a safety feature by reducing the spread of the maximum input power consumption which depends on the input voltage which may vary within a relatively broad voltage range.

Some important aspects explained above with respect to the depicted examples are now summarized. It should be noted, however, that the following description is not to be regarded as an exhaustive enumeration of essential feature. Emphasis is rather put on the method of operating the power converters, particularly the power converters as illustrated in or explained with reference to theFIGS. 1 to 7. The flow chart ofFIG. 8is provided to support the following description. The method described herein can be used for operating a power converter, as depicted, for example inFIG. 1, which has an inductor LPcoupled to a terminal operably supplied with the input voltage VIN. Accordingly the method comprises generally enabling and disabling an input current iPpassing through the inductor LPin accordance with a drive signal VG, whereby the semiconductor switch T1is coupled to the inductor T1for switching the input current iPon and off. The method further includes generating a current sense signal VCSthat represents the input current iPpassing through the inductor LPor the semiconductor switch T1. The semiconductor switch T1is regularly closed in accordance with a pre-defined clock frequency, and the current sense signal VCSis integrated, thus providing an integrated current sense signal VCSINT(seeFIG. 3). The method further includes comparing the integrated current sense signal VCSINTwith a threshold VTHthat is a function of the input voltage VIN. The semiconductor switch T1is opened dependent on the result of the comparison, e.g., when the integrated current sense signal VCSINThas reached the threshold.

As explained above, the threshold may be a function of the input voltage which may be approximated by two or more linear branches (seeFIG. 4). In one exemplary implementation a threshold signal is generated dependent on the input voltage VINfor each linear branch used to approximate the function. The integrated current sense signal VCSintmay be compared with each threshold signal VTH1, VTH2(seeFIG. 5). The results of these comparisons are combined, e.g., using an OR-gate as shown in the example ofFIG. 5. In order to facilitate the implementation the function defining the threshold as dependent on the input voltage may be “flipped.” In this case the integrated current sense signal has to be flipped in the same manner. The flipped integrated current sense signal is then compared with the flipped threshold signal(s).