Converter for analog inputs

A device having a first oscillator circuit configured to generate a first signal with a first frequency based on an analog input and external characteristics, and a second oscillator circuit configured to generate a second signal with a second frequency based on a constant voltage and the external characteristics. The device also having one or more discrete logic gates configured to generate a digital composite signal based on the first signal and the second signal, such that a number of transitions in the digital composite signal over a period of time, based on the first frequency of the first signal, are indicative of the analog input.

TECHNICAL FIELD

This disclosure relates to determining values of analog inputs, and more particularly, to determining values of analog inputs from a sensor.

BACKGROUND

In various applications, it is important to sense or measure any of various types of natural or artificial phenomena, such as radiation to which a device or product has been exposed. This may be the case in electronic, medical, food safety, and space applications, for example. One application may be for assurance that medical devices or foods have received the correct dose of radiation to ensure that the medical device has been fully sterilized. Another application may be for assurance that all pathogens leading to further degradation have been exterminated from the food.

SUMMARY

In general, the disclosure is directed to techniques and devices that convert an analog input into a digital input with minimal power and minimal profile. For example, a sensor may convert a sensed input into an analog input (e.g., voltage input). The sensor may apply the analog input to a first oscillator, which sets the frequency of the signal generated by the first oscillator. In this example, a second oscillator substantially similar to the first oscillator may generate a signal that oscillates at a constant frequency and the second oscillator acts as a reference oscillator to the first oscillator.

In this example, the first and second oscillator will each produce a digital signal, such that the first signal from the first oscillator is based on the analog input and the external circumstances, and the second signal from the second oscillator is based on a constant voltage and the external circumstances. Because the first digital signal is based on the analog input and the external circumstances and the second digital signal is based on the constant voltage and the external circumstances, the frequencies of the first and second signals may be different. As both the first and second oscillators are substantially similar and will experience the same external circumstances (e.g., heat, aging, or the like), using the second oscillator as a reference for the first oscillator, it may be possible to nearly eliminate potential errors in determining the value of the analog input caused by external circumstances. For example a converter may combine the two digital signals with two different frequencies into a digital composite signal with a number of transitions indicative of the analog input. Optionally, frequency dividers may be used to increase the difference in frequencies between the first and second digital signals, providing a higher resolution for the number of transitions to be indicative of the analog input.

In one example, the disclosure is directed to a device that comprises a first oscillator circuit configured to generate a first signal with a first frequency based on an analog input and external characteristics, a second oscillator circuit configured to generate a second signal with a second frequency based on a constant voltage and the external characteristics, and one or more discrete logic gates configured to generate a digital composite signal based on the first signal and the second signal, wherein a number of transitions in the digital composite signal over a period of time are indicative of the analog input, and wherein the period of time is based on one of the first frequency of the first signal or the second frequency of the second signal.

In another example, the disclosure is directed to a method that comprises generating, by a first oscillator circuit, a first signal with a first frequency based on an analog input and external characteristics, generating, by a second oscillator circuit, a second signal with a second frequency based on a constant voltage and the external characteristics, and generating, by one or more discrete logic gates, a digital composite signal based on the first signal and the second signal, wherein a number of transitions in the digital composite signal over a period of time are indicative of the analog input, and wherein the period of time is based on one of the first frequency of the first or the second frequency of the second signal.

In another example, the disclosure is directed to a system that comprises a first oscillator circuit configured to generate a first signal with a first frequency based on an analog input and external characteristics, a second oscillator circuit configured to generate a second signal with a second frequency based on a constant voltage and the external characteristics, one or more discrete logic gates configured to generate a digital composite signal based on the first signal and the second signal, wherein a number of transitions in the digital composite signal over a period of time are indicative of the analog input, and wherein the period of time is based on one of the first frequency of the first or the second frequency of the second signal, and a processor configured to determine the analog input based on the number of transitions in the digital composite signal.

DETAILED DESCRIPTION

Some of the examples described in the disclosure may be directed to devices, methods, and systems for converting the analog output of a sensor, such as a radiation sensor, into a high resolution digital signal, where the number of transitions of the digital signal is indicative of the analog output of the sensor. In various examples, an analog signal converter as described herein may be implemented entirely in complementary metal-oxide-semiconductor (CMOS) circuitry that may be incorporated in any CMOS integrated circuit. In some examples, an analog signal converter as described herein may receive and convert one or more analog inputs, such as radiation exposure of an integrated circuit, and compensating for any affects that the external circumstances (e.g., heat, aging, or the like) have on the measurement of the input value. In some examples, the integrated circuit may incorporate an analog signal converter, such that when it is powered up or at any time thereafter, may automatically convert the analog input (e.g., a voltage varied by the amount of radiation exposure) from a sensor (e.g., a radiation sensor), and output a digital output indicative of the voltage from the analog sensor. An analog signal converter may be implemented as a portion of a larger integrated circuit, and may therefore be implemented with a small profile and low cost, in comparison to using an analog-to-digital converter.

In general, analog inputs are continuous physical quantities that cannot be used as digital inputs until the analog inputs are each converted into a digital input, which is a digital number that represents the quantity's amplitude. However, the conversion of the analog inputs requires quantization, which introduces a small amount of error. To reduce the amount of error by the quantization, the analog inputs are typically sampled over a period of time, which results in a sequence of digital value that have converted a continuous-time and continuous amplitude analog signal to a discrete-time and discrete amplitude digital signal.

One technique used to convert analog signals to digital signals is through an analog-to-digital converter (ADC). An ADC is defined by the range of frequencies the ADC can measure (e.g., “bandwidth”) and how accurately the ADC can measure a signal relative to the noise it introduces. The actual bandwidth of an ADC is limited primarily by its sampling rate, and how the ADC handles errors such as aliasing. The dynamic range of the ADC is often described in terms of effective number of bits, which is the number of bits of each measure the ADC returns that are on average not noise. For example, an ideal ADC has effective number of bits equal to the resolution of the ADC. However, real-world ADCs are often selected to match the bandwidth and required signal to noise ratio of the signal to be quantized. Matching an ADC is required as the ADC is generally limited by the number of bits at the output, while also requiring more power and a larger profile. In systems and devices with profile and power limitations, ADCs may provide only a limited resolution or may not work at all.

Techniques and devices disclosed herein provide for an analog signal converter with low power and high resolution conversion of analog inputs to a digital output, and available to systems and devices with profile and power constrains. In one example of this disclosure, a device may have a first oscillator circuit configured to generate a first signal with a first frequency that is based on an analog input and external characteristics, a second oscillator circuit configured to generate a second signal with a second frequency that is based on a constant voltage and the external characteristics, and one or more discrete logic gates configured to generate a digital composite signal based on the first signal and the second signal, wherein a number of transitions in the digital composite signal over a period of time, based on the first frequency of the first signal, are indicative of the analog input. The digital composite signal of this device should not be confused with a beat frequency, as the beat frequency is an analog signal equal to the absolute value of the difference in frequency of the two waves. Whereas the digital composite signal is a digital signal, and may represent the logical expression of a low logic state for any external low logic states, and provides a high logic state only when there are external high logic states.

One advantage of the techniques and devices as disclosed is high-resistance to external characteristics from the environment, such as heat, radiation, and the like. For example, the device could use one ring oscillator to convert the analog input into a digital output; however, one ring oscillator would also be susceptible to external circumstances. As such, two substantially similar oscillators may be used to negate the external circumstances, such as one ring oscillator based on the analog input and the external circumstances, and a second ring oscillator based on a constant voltage (e.g., reference voltage) and the external circumstances. Another advantage of the techniques and devices as disclosed is high resolution of the analog input, which may also be adjustable by the use of optional frequency dividers. For example, the lower the frequency of the first digital signal compared to the frequency the second digital signal (e.g., achieved through frequency dividers, or varying the base frequency of the two oscillators) the more transitions will be available to a processor. In this example, the number of transitions available to the processor is flexible and adjustable, based on the difference and/or ratio between the frequencies, and can result in an extremely high number of transitions in comparison to conventional ADCs. Another advantage of the techniques and devices as disclosed is the compact profile of the device and/or system, which requires a low amount of power and manufacturing cost. For example, the device may have two substantially similar matched ring oscillator circuits on the same silicon device, such that any chip-to-chip variation of one ring oscillator circuit on the silicon device will also apply to the other ring oscillator circuit on the same silicon device preventing any errors from internal circumstances (e.g., manufacturing defects) from occurring at the output. Another advantage of the techniques and devices as disclosed is the use of a zero transitions for a period, and a number of transitions for another period, which allows the need for one output pin instead of requiring more than one output pin. For example, through a single output pin a processor may count the number of transitions between the periods of zero transitions allowing to the processor to determine the digital input corresponding to the analog input. Another advantage of the techniques and devices as disclosed is the flexibility of changing the respective values of each divider. For example, for a low power application, the value of the first and second dividers may be increased to provide a lower frequency and a lower number of transitions, and conversely, for a high power application, the value of the first divider may be increased while the value of the second divider may be decreased to provide a higher frequency and a higher number of transitions at the output.

FIG. 1is a block diagram illustrating an example of analog signal converter1that implements one or more example techniques described in this disclosure. In the example ofFIG. 1, analog signal converter1includes sensor2, oscillators4A and4B, converter6, links8-12, and processor14.

Sensor2represents any analog sensor, such as a radiation sensor, which outputs an analog output to be received by oscillator4A as an analog input. Oscillators4A and4B represent a component (e.g., non-linear oscillator, or any component(s) capable of generating a signal at particular frequency that can drive a frequency divider), such as a ring oscillator that generates a signal at a particular frequency proportional to a voltage applied to oscillators4A and4B. In some examples, a gain (e.g., “sensitivity”) of oscillators4A and4B determines the particular frequency of the signal based on the applied voltage. For instance, a ring oscillator is a component composed of a chain of odd number of NOT gates (e.g., inverters), where the output of the last NOT gate feeds back to the input of the first NOT gate. Due to the odd number of NOT gates in the chain, the output of the chain of NOT gates oscillates between two voltage levels (e.g., a digital high and a digital low).

In some examples, a ring oscillator only requires power to operate above a certain threshold voltage, and oscillations begin spontaneously. In other examples, to increase the frequency associated with the signal generated by the oscillator, the applied voltage may be increased, which increases both the frequency of the signal generated by the oscillator and the current consumed. In yet other examples, to increase the frequency associated with the signal generated by the ring oscillator, a smaller number of inverters may result in a higher frequency of oscillation given a certain power consumption. In some examples, the first and second oscillators may each generate a signal oscillating at a frequency of 1 gigahertz (GHz). In some examples, the first and second oscillators may have an odd number of inverters, where the last inverter is a NOR gate. In this example, the NOR gate may allow the first and/or second oscillator circuit to be disabled by a disable input received by the last inverter (e.g., NOR gate).

Converter6represents the conversion of digital signals (e.g., oscillating digital highs and lows) produced by oscillators4A and4B to generate a digital composite signal. In some examples, oscillator4A may generate a first signal with a first frequency and oscillator4B may generate a second signal with a second frequency. In other examples, converter6may also include two optional frequency dividers, such that the output of each oscillator circuit is an input into their respective frequency divider. The two optional frequency dividers may receive the input of the first signal with the first frequency and the second signal with the second frequency from oscillators4A and4B, and generate a third signal with a third frequency and a fourth signal with a fourth frequency, respectively. Converter6may also include an AND gate, such that the output (e.g., the first and second signals, the third and fourth signals) of either oscillators4A and4B or the two frequency dividers is received by the AND gate and the output of the AND gate is a digital composite signal (e.g., a combination of either the first and second signals or the third and fourth signals to produce a single digital composite signal).

Links8-12may represent any medium capable of conducting electrical power from one location to another. Examples of links8,10A and10B, and12include, but are not limited to, physical and/or wireless electrical transmission mediums such as electrical wires, electrical traces, RF transmissions, and the like. Each of links8, and10A and10B provide electrical coupling between, respectively, sensor2and oscillators4A, oscillators4A and4B, and converter6. Link8provides electrical coupling between sensor2and oscillator4A, such that sensor2sends commands to oscillator4A in order to regulate the oscillation of oscillator4A to be delivered to converter6. Links10A and10B provide electrical coupling between oscillators4A and4B and converter6, such that oscillator4A sends a digital frequency to converter6based on the input received by oscillator4A, and oscillator4B sends a digital reference frequency to converter6in order to regulate the errors created by external circumstance, such as the environment. Link12provides electrical coupling between converter6and an integrated circuit, such as an input-output (I/O) device (not shown), such that converter6sends a composite digital signal to the integrated circuit in order to provide information regarding the analog input received from sensor2, such as the amount of radiation exposure sensed by a radiation sensor. In some examples, the information provided by the composite digital signal is the number of transitions in the composite digital signal over a period of time, and the number of transitions is indicative of the amount of radiation exposure as sensed by sensor2. In some examples, the frequency of the digital composite device to the I/O device may be dependent on the power constraints.

Processor14may represent any digital component capable of counting the length of a primary transitions and the number of secondary transitions in the primary transition, In some examples, processor14may be one of a microprocessor, an application-specific instruction-set processor, a digital signal processor, a counter, or the like.

In some examples, the base frequency of the first digital signal and the second digital signal is 1 GHz. In other examples, the base frequency of the first digital signal and the second digital signal are varied and the base frequencies are not divided by frequency dividers. In yet other examples, the base frequency of the first digital signal and the second digital signal are 1 GHz, and the base frequencies are divided by a value with frequency dividers. In this example, a higher number of transitions indicative of the analog input may be achieved through the difference and/or ratio between the values of the frequency dividers.

Input terminal22represents an input terminal (e.g., a charge input) for receiving and/or providing an analog input, such as an analog input from sensor42to oscillator44A. Disable input24represents an input terminal and may receive and/or provide a digital high to NOR gates28A and28B, such that the output of ring oscillators26A and26B will not become a digital high at the output of NOR gates28A and28B. In the alternative, disable input24may receive and/or provide a digital low to NOR gates28A and28B, such that the output of ring oscillators26A and26B may become either a digital high or a digital low at the output of NOR gates28A and28B, thereby enabling NOR gates28A and28B to provide the generated signals of ring oscillators26A and26B.

Ring oscillators26A and26B represent a chain of an odd number of inverters that oscillate continuously. In some examples, ring oscillators26A and26B may oscillate around 1 gigahertz (GHz). In some examples, only ring oscillator26B may oscillate around 1 GHz. In some examples, ring oscillators26A and26B may be an n+2 ring oscillator, such that ring oscillators26A and26B may be an odd number (e.g., n, which is an odd number) of inverters connected to two additional inverting discrete logic gates, such as inverters36A and36B, and NOR gates28A and28B. In some examples, ring oscillators26A and26B may each have a respective gain that generates a signal at a particular frequency based on the applied voltage.

Inverters36A and36B represent discrete logic gates (e.g., a NOT gate), which provide a logic negation between the external logic state and the internal logic state. NOR gates28A and28B represent a combination of two discrete logic gates, that is an OR gate and a NOT gate, which provides an internal low logic state for any external high logic states, and alternatively, provides an internal high logic only when there are external low logic states.

Dividers30A and30B are optional and represent frequency dividers, which receive an input signal with an associated frequency and divide the frequency by a specific value, before generating an output signal with the divided frequency of the input signal. In some examples, dividers30A and30B may have different values tier dividing their respective input signals. In some examples, the value of divider30A may be 2n(e.g., 216or 16 bits, or 230or 30 bits), and the value of divider30B may be 2x(e.g., 27or 7 bits, or 210or 10 bits). In some examples, the difference and/or ratio of the value of divider30A and the value of divider30B may determine the base number of secondary transitions (e.g., clock edges, T2as described inFIG. 3) inside of a half period of a primary transition (e.g., T1as described inFIG. 3) in the digital composite signal. In some examples, if the value of divider30A is ten bits greater than the value of divider30B, then the frequency of digital output signal S1is ten times (e.g., 10 bits) longer the digital output signal S2. In some examples, where the frequencies applied to both divider30A and30B are equal (e.g., where the voltage applied to both oscillators4A and4B are equal), the number of transitions (e.g., number of bits at the output) may depend on the difference between the number of bits of divider30A and the number of bits of divider SOB (e.g., n-x, 216-7or 230-10).

Output signal S1represents a digital output signal with an associated frequency from either oscillator44A or from optional divider30A. In some examples, S1may represent a signal with a frequency of 1 GHz. In other examples, S1may represent a signal with a frequency based on the analog input. In yet other examples, S1may represent a signal with a frequency based on the analog input and divided by a value (e.g., a value of 2nor 216).

Output signal S2represents a digital output signal with an associated frequency from oscillator44B or from optional divider30B. In some examples, S2may represent a signal with a frequency of 1 GHz. In other examples, S2may represent a signal with a frequency of 1 GHz and divided by a value (e.g., a value of 2xor 27).

AND gate32represents a discrete logic gate, which provides an internal low logic state for any external low logic states, and provides an internal high logic state only when there are external high logic states. Output terminal34represents an output terminal and may output a digital composite signal from AND gate32to a processor (e.g., processor14as described inFIG. 1) over link52.

In the example ofFIG. 2, an analog input (e.g., voltage) is received over link48at input terminal22. In some examples, the analog input is from sensor42. In some examples, the analog input is a voltage based on the amount of radiation detect by sensor42. In some examples, an analog-to-digital converter (ADC) may have a large profile, require more power, and may have a limited resolution at the digital output.

After receiving the analog input (e.g., voltage), the analog input causes an increase or decrease in the frequency associated with the output signal (e.g., S1) generated by ring oscillator26A with respect to the signal generated by oscillator44B. In some examples, after receiving the analog input (e.g., voltage), a resistor and one or more capacitors may condition the signal to be applied to ring oscillator26A, and the voltage across a second capacitor may be applied to ring oscillator26A. In some examples, a single ring oscillator may be exposed to external circumstances that may alter the digital output of the single ring oscillator, but two substantially similar oscillators, such as oscillator44A and oscillator44B, will affected by external circumstances in a similar manner. In some examples, oscillators44A and44B will be on the same silicon chip. In some examples, NOR gate28A may receive a digital high input from disable input24, which disables the output signal with the associated frequency indicative of the analog input (e.g., S1) from oscillator44A.

In the example ofFIG. 2, a constant voltage (e.g., a supply voltage of the circuit Vcc) is received by ring oscillator26B, which as described above causes ring oscillator26B to generate an output signal with a constant associated frequency (e.g., S2). In some examples, the difference and/or ratio in frequencies between output signal Srfrom oscillator44A and output signal S2from oscillator44B will provide information on the difference in voltage relative to Vcc with respect the analog input voltage, and the impact of the external circumstances will be canceled out as both oscillators44A and44B are similarly affected. In some examples, NOR gate28B may receive a digital high input from disable input24, which disables the output signal with the constant associated frequency (e.g., S2) from oscillator44B. In some examples, the constant associated frequency is 1 GHz.

In one example ofFIG. 2, AND gate32may receive and combine digital output signals S1and S2to generate a composite digital signal, such that the composite digital signal contains a number of transitions. In sortie examples, this combination could be a logic function (e.g., software implementing logic combinations), or a combination of one or more discrete logic gates (e.g., AND gates, OR gates, NAND gates, NOR gates, etc.), in some examples, the digital composite signal may be provided to a processor (e.g., processor14as described inFIG. 1) over link52, and the processor determines the number of transitions in the digital composite signal. In other examples, the digital composite signal may be provided to a counter over link52, and the counter determines the number of transitions in the digital composite signal.

In another example ofFIG. 2, divider30A may receive the digital output signal with an associated frequency indicative of the analog input from oscillator44A, and divides the frequency of the digital output signal by a value. In some examples, the value is 2n(e.g., 216or 230, etc.). After dividing the associated frequency indicative of the analog input by the value, divider30A may generate another digital output signal with a divided associated frequency indicative of the analog input (e.g., S1). Divider30B may also receive the digital output signal with an associated constant frequency from oscillator44B, and divides the frequency of the digital output signal by a value. In some examples, the value is 2x(e.g., 27or 210, etc.). After dividing the associated constant frequency, divider30B may generate another digital output signal with a divided associated constant frequency (e.g., S2). Alternatively in this example, dividers30A and30B may not be used, but instead the base frequencies of digital output signals S1and S2may vary in similar manner and/or ratio as the frequencies of divided digital output signals S1and S7as described above.

In some examples, AND gate32may receive and combine (e.g., the logical expression of a low logic state for any external low logic states, and provides a high logic state only when there are external high logic states) the divided digital output signals S1and S2to generate a composite digital signal, such that ratio of the values in dividers30A and30B cause the composite digital signal to contain a number of secondary transitions (e.g., clock edges, T2as described inFIG. 3) inside a single primary transition (e.g., T1as described inFIG. 3). In other words, because the divided digital output signal S2has a higher frequency than divided output signal S1in the digital composite signal, the digital composite signal has a number of transitions T2inside a primary transition T1, as described inFIG. 3. In some examples, this combination could be a logic function (e.g., software implementing logic combinations), or a combination of one or more discrete logic gates (e.g., AND gates, OR gates, NAND gates, NOR gates, etc.).

Alternatively, the value of dividers30A and30B may be reversed (e.g., divider30A may have a value of 27or 210, and divider30B may have a value of 216or 230). In this example, AND gate32may receive and combine (e.g., the logical expression of a low logic state for any external low logic states, and provides a high logic state only when there are external high logic states) the divided digital output signals S1and S2to generate a composite digital signal, such that ratio of the values in dividers30A and30B cause the composite digital signal to contain a number of secondary transitions (e.g., clock edges, T2as described inFIG. 3) inside a single primary transition (e.g., T1as described inFIG. 3). In other words, because the divided digital output signal Srhas a higher frequency than divided output signal S2the digital composite signal, the digital composite signal has a number of transitions T2inside a primary transition T1, as described inFIG. 3. In some examples, this combination could be a logic function (e.g., software implementing logic combinations), or a combination of one or more discrete logic gates (e.g., AND gates, OR gates, NAND gates, NOR gates, etc.).

In some examples, the digital composite signal may be provided to a processor (e.g., processor14as described inFIG. 1) over link52, and the processor determines the number of secondary transitions inside the primary transition. In other examples, the digital composite signal may be provided to a counter (not shown) over link and the counter determines the number of secondary transitions inside the primary transition. In some examples, the number of secondary transitions varies as the analog input varies. For example, an increase in the voltage at ring oscillator26A increases the frequency of divided output signal S1, and decreases the amount of secondary transitions T2from divided output signal S7in the digital composite signal. In another example, a decrease in the voltage at ring oscillator26A decreases the frequency of divided output signal S1, and increases the amount of transitions T2from divided output signal S2in the digital composite signal.

In some examples, the number of transitions and/or the number of secondary transitions of the composite digital signal may be indicative of the analog input. In other examples, the number of transitions and/or the number of secondary transitions of the composite digital signal may be indicative of the analog input from sensor42. In yet other examples, the number of transitions and/or the number of secondary transitions of the composite digital signal may be indicative of the amount of radiation detected by sensor42.

FIG. 3is a conceptual diagram illustrating an example of digital composite signal40.FIG. 3is described with respect toFIG. 2. In the example ofFIG. 3, T1represents one primary transition, and T2represents one secondary transition (e.g., one clock edge). In this example, in the half period of T1there are a number of T2transitions. In some examples, the number of T2transitions is indicative of the analog input. For example, if the analog input (e.g., voltage with respect to radiation) increases, then the number of T2transitions will decrease as the frequency of T1increases because of a logic function, such as AND gate32as described inFIG. 2. In another example, if the analog input (e.g., voltage with respect to radiation) decreases, then the number of T2transitions will increase as the frequency of T1decreases because of a logic function, such as AND gate32as described inFIG. 2. In some examples, the number of T2transitions may be determined by a processor (e.g., processor14as described inFIG. 1) or a counter and represents a digital conversion of the analog input. In some examples, digital composite signal40may represent a change in the number of clock edges (e.g., T2) based on the analog input (e.g., voltage from sensor42over link48) over time, such as analog input54.

In some examples, an analog-to-digital converter (ADC) may have a large profile, require more power, and may have a limited resolution at the digital output. In some examples, a single ring oscillator may be exposed to external circumstances that may alter the digital output signal of the single ring oscillator, but two substantially similar oscillators, such as oscillator44A and oscillator44B, will affected by external circumstances in a similar manner. In some examples, the difference and/or ratio in frequencies (e.g., digital composite signal40) between output signal S1from oscillator44A and output signal S2from oscillator44B, as described inFIG. 2will provide information on the difference in voltage relative to Vcc with respect the analog input voltage, and the impact of the external circumstances will be canceled out as both oscillators44A and44B are similarly affected.

FIG. 4is a conceptual diagram illustrating an example50of the frequency of divided digital output signals S1and S2based on analog input54over time.FIG. 4is described with respect toFIG. 2. In the example ofFIG. 4, S1may represent the divided digital output signal generated by divider30A with the associated frequency indicative of analog input54varying over time. In the example ofFIG. 4, divided digital output signal S2may also represent the output signal generated by divider30B with the associated constant frequency gradually varying over time. In one example ofFIG. 4, divided digital output signal S1decreases as analog input54decreases, and divided digital output signal S1increases as analog input54increases. In another example ofFIG. 4, divided digital output signal S2is substantially constant over time, as analog input54and digital output signal S1decrease and increase over time. In some examples, the gradual variance of divided digital output signal S2may be due to external circumstances (e.g., heat, aging, or the like). In some examples, the gradual variance of divided digital output signal S2compensates for the likely gradual variance (not shown) of divided digital output signal S1. In some examples, the compensation by divided digital output signal S2for external circumstances provides fir a robust digital conversion of analog input54over time.

In some examples, an analog-to-digital converter (ADC) may have a large profile, require more power, and may have a limited resolution at the digital output. In some examples, a single ring oscillator may be exposed to external circumstances that may alter the digital output signal (e.g., output signal S1may increase and/or decrease due to heat, aging, or the like) of the single ring oscillator, but two substantially similar oscillators, such as oscillator44A and oscillator44B, will affected by external circumstances in a similar manner. In some examples, the difference and/or ratio in frequencies between output signal S1from oscillator44A and output signal S2from oscillator44B will provide information on the difference in voltage relative to Vcc with respect the analog input voltage, and the impact of the external circumstances will be canceled out as both oscillators44A and44B are similarly affected.

FIG. 5is a flow chart illustrating example60of operations.FIG. 5is described with respectFIG. 2. In the example ofFIG. 5, a first oscillator (e.g., oscillator44A) generates a first signal (e.g., S1) with a first frequency based on an analog input (e.g., an analog input from sensor42over link48) and external characteristics (62). In the example ofFIG. 5, a second oscillator (e.g., oscillator44B) generates a second signal (e.g. S2) with a second frequency based on a constant voltage (e.g., Vcc) and the external characteristics (64). In the example ofFIG. 5, one or more discrete logic gates generates a digital composite signal (e.g., digital composite signal40as described inFIG. 3) based on the first signal (e.g., S1) and the second signal (e.g., S2), a number of transitions (e.g., T2as described inFIG. 3) over a period of time (e.g., a half period of T1as described inFIG. 3) are indicative of the analog input, and the period of time is based on one of the first frequency of the first signal or the second frequency of the second signal (66).

In some examples, the one or more discrete logic gates may divide the first signal with the first frequency by a first divider connected to the first oscillator circuit to generate a third signal with a third frequency, divide the second signal with the second frequency by a second divider connected to the second oscillator circuit to generate a fourth signal with a fourth frequency, the one or more discrete logic gates are configured to generate the digital composite signal based on the third signal and the fourth signal, and the number of transitions in the digital composite signal over a half period of one of the third signal or the fourth signal is indicative of the analog input. In some examples, the first divider divides the digital frequency by 216, and the second divider divides the digital reference frequency by 27. In some examples, example60of operations may further include receiving, by a sensor connected to the first oscillator circuit, the analog input. In some examples, the first oscillator is connected to a radiation measurement component, and the analog input is indicative of the amount of radiation exposure. In some examples, the first oscillator circuit and the second oscillator circuit are located on the same silicon device. In some examples, the first oscillator circuit and the second oscillator circuit are matched ring oscillator circuits. In some examples, the period of time is a half period based on one of the first signal with the first frequency or the second signal with the second frequency.

In some examples, an analog-to-digital converter (ADC) may have a large profile, require more power, and may have a limited resolution at the digital output. In some examples, a single ring oscillator may be exposed to external circumstances that may alter the digital output signal of the single ring oscillator, but two substantially similar oscillators, such as oscillator44A and oscillator44B, will affected by external circumstances in a similar manner. In some examples, the difference and/or ratio in frequencies between output signal S1from oscillator44A and output signal S2from oscillator44B will provide information on the difference in voltage relative to Vcc with respect the analog input voltage, and the impact of the external circumstances will be canceled out as both oscillators44A and44B are similarly affected.