Zero-delay serial communications circuitry for serial interconnects

Circuitry and methods for supporting serial communications over serial interconnects between circuit modules are provided. A data recovery circuit receives incoming serial data from the serial interconnect path with zero delay. The data recovery circuit includes a data sampler that samples the incoming serial data using a multiphase clock. Data samples are provided to a multiplexer that selects an optimum sampled data signal to use as a recovered data signal. The multiplexer has a control input that receives a phase pointer signal. Control circuitry in the data recovery circuit analyzes the sampled data signals and a current value of the phase pointer to compute a clock phase shift error. If the clock phase shift error exceeds a predetermined value, the phase pointer signal can be updated. The data recovery circuit may be implemented using hardwired circuitry or programmable logic.

BACKGROUND

This invention relates to communications circuitry, and more particularly, to serial communications circuitry used in conveying signals over circuit interconnects.

Integrated circuits contain various regions of circuitry. Metal lines called interconnects are used to convey signals between these different circuit regions.

It has recently become apparent that conventional circuit designs cannot simply be scaled up in size indefinitely. For example, microprocessor designers have begun to explore multi-core architectures as an alternative to constructing ever-larger microprocessor chips. Particularly in designs such as these, large numbers of signals need to be conveyed from one portion of an integrated circuit to another.

Large numbers of signals also need to be conveyed between blocks of circuitry on integrated circuits such as programmable logic device integrated circuits. In modern programmable logic device integrated circuit, circuit blocks no longer all perform identical functions. Memory blocks are used for data storage, digital signal processing blocks are used for specialized data processing functions, and programmable logic blocks are used for user logic. The broad range of functions that are implemented in the circuit blocks can place a burden on the interconnect infrastructure. Modern programmable logic device integrated circuits also tend to have circuit blocks that are larger and more complex than older devices, which further burdens the interconnects.

In a typical programmable logic device, rows and columns of interconnects are selectively coupled to each other using programmable switches at row and column intersections. Because of the custom nature of programmable logic device integrated circuits, programmable logic device integrated circuits may need to have several times as many interconnects as comparable custom logic circuits. Programmable logic device integrated circuits may therefore be particularly sensitive to interconnect inefficiencies.

One way to ensure that a given programmable logic device integrated circuit has sufficient interconnect resources to implement a desired circuit design is to over-provision the interconnect fabric. By providing many interconnects, logic designers are ensured that their designs can be implemented without exhausting available interconnect resources. However, as the number of interconnects that are included on an integrated circuit increases, the size of the integrated circuit increases. This, in turn, makes the distances between circuit blocks on the integrated circuit larger and creates new interconnect challenges.

There is therefore a need for improved integrated circuit interconnect structures.

SUMMARY

In accordance with the present invention, circuitry and methods for supporting communications over serial interconnects are provided.

Serial data may be conveyed between a first module and a second module over a serial interconnect structure. The modules may be circuit blocks within an integrated circuit such as a programmable logic device integrated circuit or may be integrated circuits on one or more circuit boards in a system. The serial interconnect structures may be formed from single-ended or differential signal paths.

In a transmitting module, programmable logic or other circuitry may generate data to be transmitted. Parallel data can be serialized using a serializer. Serial data is conveyed over the serial interconnect path and is received at a receiving circuit module.

The receiving circuit module has a data recovery circuit that receives incoming serial data and provides a corresponding recovered data stream to a deserializer. The deserializer converts the recovered data stream to parallel data for use by programmable logic or other circuitry in the receiving circuit module.

The data recovery circuit includes a data sampler that receives the incoming serial data stream. The data sampler includes a number of registers. The registers are clocked by respective clock phases in a multiphase clock signal. The data sampler provides a number of associated sampled data signals at its output.

A multiplexer receives each of the sampled data signals at its input. With one suitable arrangement, there are five clock phases in the multiphase clock, so there are five corresponding sampled versions of the serial data signal and five inputs to the multiplexer. The multiplexer has a control input that receives a phase pointer signal. The phase pointer signal controls the multiplexer. In response to the phase pointer signal, the multiplexer selects an optimum one of the sampled data signals to use as the recovered data signal.

Control circuitry in the data recovery circuit identifies which of the sampled data signals is the optimum data signal. The control circuitry may include a shift register in which the phase pointer signal is maintained.

A phase detector in the control circuitry receives the sampled data signals and a fed-back version of the phase pointer. The phase detector analyzes the sampled data signals to determine the location of the edge of the incoming serial data. Based on this information and information on the current location of the phase pointer, the phase detector generates left and right shift control signals. The left and right shift control signals are filtered using a low-pass filter implemented in a shift decision circuit. The filtered left and right shift control signals are applied to the shift register to update the pointer.

The control circuitry uses a non-linear control algorithm in determining whether or not to update the current value of the phase pointer. With one suitable approach, the control circuitry generates a clock phase shift error signal. The clock phase shift error signal indicates how much the current value of the phase pointer has become shifted (if at all) from its optimum value. If the incoming data drifts, the sampled data that is currently selected by the multiplexer will no longer be the optimum sampled data signal to use as the recovered data. The control circuit can detect this error and update the phase pointer to ensure that the appropriate sampled data stream is routed to the output of the multiplexer.

To ensure that the data recovery circuit exhibits good jitter tolerance, the control circuit preferably does not update the phase pointer unless the clock phase shift error reaches an appropriate threshold. With one suitable arrangement, the control circuit updates the current value of the phase pointer only when the clock phase shift error is at least two (i.e., when the relative phase shift is plus or minus two). Clock phase shift errors of plus or minus one and clock phase shift errors of zero will not result in an updating of the phase pointer.

The date recovery circuit may be implemented using hardwired circuitry, programmable logic that has been configured with configuration data to perform data recovery circuit functions, or a combination of programmable logic and hardwired circuitry.

DETAILED DESCRIPTION

The present invention relates to the use of serial interconnect architectures to relieve interconnect bottlenecks. Serial communications arrangements are used to transmit and receive signals over serial interconnects. The interconnects may be on-chip interconnects or may be interconnects on a circuit board or one or more other system components. For clarity, the present invention will generally be described in the context of on-chip serial interconnects.

The integrated circuits in which the serial interconnects are formed may be any suitable integrated circuits in which it is desired to convey large amounts of data from one circuit region to another. For example, the integrated circuits may be memory chips, digital signal processing circuits, microprocessors, application specific integrated circuits, programmable logic device integrated circuits and other programmable integrated circuits, or any other suitable integrated circuit. The desire to relieve interconnect bottlenecks can be particularly great in programmable logic devices, so the present invention will generally be described in the context of programmable logic device integrated circuits as an example.

An illustrative programmable logic device10in accordance with the present invention is shown inFIG. 1. Programmable logic device10may have input/output circuitry12for driving signals off of device10and for receiving signals from other devices via input/output pins14.

Interconnects16such as global and local vertical and horizontal conductive lines may be used to route signals on device10.

Programmable logic18may include combinational and sequential logic circuitry. The programmable logic18may be configured to perform a custom logic function. Programmable switches associated with the interconnection resources on device10may be considered to be a part of programmable logic18.

Programmable logic device10contains programmable elements20. Elements20can be programmed using configuration data. In general, elements20may be based on any suitable technology. With one suitable arrangement, elements20are formed form volatile memory such as random-access memory. With another suitable arrangement, elements20are formed from non-volatile structures such as programmable fuses, programmable antifuses, or programmable-read-only memory. In mask-programmed arrangements, groups of programmable via structures that are programmed using custom lithographic masks are used to form elements20.

Most commonly, programmable elements20are formed from memory elements that can be loaded with configuration data (also called programming data) using pins14and input/output circuitry12. Once loaded, the elements20each provide a corresponding static control output signal that controls the state of an associated logic component in programmable logic18. The memory element output signals are typically applied to the gates of metal-oxide-semiconductor (MOS) transistors. These transistors may include n-channel metal-oxide-semiconductor (NMOS) pass transistors in programmable components such as multiplexers. Some of the output signals may also be used to control p-channel metal-oxide-semiconductor (PMOS) transistors (e.g., power-down transistors). By loading appropriate configuration data into the programmable elements20, a logic designer can configure programmable logic device10to perform a desired custom logic function.

The circuitry of device10may be organized using any suitable architecture. As an example, the logic of programmable logic device10may be organized in a series of rows and columns of larger programmable logic regions each of which contains multiple smaller logic regions. The larger logic regions are sometimes referred to as logic array blocks. The smaller logic regions are sometimes referred to as logic elements. A typical logic element may contain a look-up table, registers, and programmable multiplexers. If desired, the logic of device10may be arranged in more levels or layers in which multiple large regions are interconnected to form still larger portions of logic. Still other device arrangements may use logic that is not arranged in rows and columns.

The logic resources of device10may be interconnected by interconnects16such as associated vertical and horizontal conductors. These conductors may include global conductive lines that span substantially all of device10, fractional lines such as half-lines or quarter lines that span part of device10, staggered lines of a particular length (e.g., sufficient to interconnect several logic areas), smaller local lines, or any other suitable interconnection resource arrangement.

Interconnects16include fixed interconnects (conductive lines) and programmable interconnects (i.e., interconnects for which programmable connections can be made using programmable switches). Interconnects16typically include at least some groups of parallel lines, which are sometimes referred to as busses. In accordance with the present invention, at least some of the interconnects16also include serial interconnects. These serial interconnects may be operated at higher data rates than the parallel interconnects on the device10, so that a relatively larger number of parallel interconnects can be replaced by a relatively smaller number of serial interconnects.

For example, in a device10in which parallel data is conveyed over parallel interconnects16at 500 Mbps (as an example), serial data can be conveyed at 40 Gbps (as an example). With this type of arrangement, 80 parallel interconnect lines can be replaced by a single serial interconnect line (or by a pair of serial lines if it is desired to use a differential signaling scheme for the serial path). This reduces the amount of real estate on the integrated circuit10that is devoted to interconnects and makes device10smaller and more efficient.

Programmable logic device integrated circuits contain blocks of programmable logic18. Programmable logic device integrated circuits may also contain other types of resources, such as blocks of memory, digital signal processors, hardwired circuits (e.g., for handling communications functions or specialized computations), and other suitable blocks of circuitry. Serial interconnects can be used to connect any of these circuit blocks to each other. If desired, serial interconnects can also be used to interconnect resources on circuit boards or other resources in a system. As an example, serial interconnects can be used to connect a programmable logic device and a custom integrated circuit on a circuit board or may be used to interconnect a microprocessor on one board in a system with a microprocessor that is located on another board in the system.

FIG. 2shows illustrative circuitry22in which modules of circuitry24communicate at least partly using serial paths26. The circuit modules24may be any suitable regions of circuitry. For example, modules24may be circuit blocks on a programmable integrated circuit10such as digital signal processing blocks, hardwired circuit blocks such as hardwired blocks of dedicated communications circuitry or circuitry for performing computationally-intensive calculations, memory blocks, or programmable logic blocks. As another example, modules24may be integrated circuits that are mounted on a single board or that are mounted on multiple boards or mounting structures in a larger system. These are merely illustrative arrangements. Modules24may be any suitable regions of circuitry in any suitable integrated circuit, circuit board, or system.

Circuit modules24may, if desired, communicate at least partly using parallel interconnects. Circuit modules24also communicate with each other over one or more serial paths26. In a typical arrangement, circuitry within a module24generates data. The data may be generated in parallel form. For example, a number of logic elements or a hardwired block of circuitry may generate data on a 16-bit bus.

Modules24contain serializers28and deserializers30to transform parallel data to serial data and to transform serial data back into parallel form. When it is desired, as an example, to transmit data from module M1to module M2, data that is generated in module M1can be serialized using serializer28in module M1. The serial data is then conveyed to module M2over serial interconnect26-1. Serial paths26such as serial interconnect path26-1may be formed from a single line (when a single-ended signaling scheme is used in which data is referenced to ground) or may be formed from a pair of lines (when a differential signaling scheme is used in which data signals on the differential lines are referenced to each other). At module M2, the signals from path26-1are received and deserialized using deserializer30in module M2. The deserialization process converts serial data from path26-1into parallel data that may be used by the circuitry of module M2. The serializer circuitry28in module M2, path26-2, and the deserializer circuitry30in module M1may be used to convey data signals from module M2to module M1.

If desired, there may be point-to-point serial data links between each module24in circuitry22. For example, in an integrated circuit (or system) that contains four modules24, there may be six bidirectional sets of serial paths26, each of which handles point-to-point serial communications between a respective pair of the modules24. In general, however, it is not necessary to interconnect each module24to every other module24in circuitry22. Serial paths such as paths26can be deployed selectively as desired.

Although the example ofFIG. 2shows circuitry22that contains four modules24, this is merely illustrative. Circuitry22can have any suitable number of modules24. In systems with more modules24, there may be more serial paths26(e.g., tens of paths26, hundreds of paths26, thousands of paths26, etc.). Systems may also have fewer modules24and fewer paths26than the circuitry22ofFIG. 2.

The number of paths26that are used on a given integrated circuit can be maintained at a reasonable level by increasing the size of modules24(i.e., by using serial paths26to connect relatively larger circuits such as complex blocks of logic rather than attempting to interconnect every logic element on an integrated circuit using a serial communications methodology).

A typical serializer28may be formed using an N:1 multiplexer. The N:1 multiplexer receives N data signals from an N-bit parallel data bus. The data signals may, as an example, have a data rate associated with a clock C1. The N:1 multiplexer is driven by a clock C2. The clock signal C2may be equal to N*C1. In operation, the N:1 multiplexer systematically connects each of its inputs to its output at a rate associated with the clock signal C2. At the output of the multiplexer, an output buffer or other circuitry may be used to route the serialized data onto an interconnect path26. The serialized data is transmitted over the path26to receiver circuitry in an appropriate receiving module24(e.g., a receiver and associated deserializer circuitry30).

The N:1 multiplexer can be operated asynchronously, without concern for the state of the receiver in the receiving module24. There are no complex serial communications protocols involved in transmitting data over interconnect paths26, so circuitry in a given module24that generates data signals for another module24need not wait for a serial communications link to be established between the two modules. There is generally no delay imposed on outgoing serial data signals. Rather, data can be transmitted immediately, in the same clock cycle that it is generated or, to ensure that the data is stable before it is transmitted, in the next clock cycle.

During normal operation of the receiving circuitry in each module24, data can be received within one clock cycle. As a result, there is essentially no delay associated with receiving incoming serial data. Incoming serial data is captured and deserialized rapidly for use by the circuitry in the receiving module.

The receiving circuitry in each module24contains a data recovery circuit that samples incoming data using a multiphase clock. Data samples corresponding to each clock phase of the multiphase clock are provided to a multiplexer. A phase pointer is used to control the multiplexer. The state of the phase pointer determines which of the sampled data signals from multiplexer's inputs is routed to the multiplexer's output.

Control circuitry in the data recovery circuit is used to continually update the phase pointer. Phase pointer updates are made based on an analysis of the current phase pointer state and the sampled data.

The control circuitry uses a non-linear control algorithm. The non-linear control algorithm responds quickly to changes in the incoming data signal while exhibiting good jitter tolerance.

Using the non-linear control algorithm, the control circuitry tracks the incoming data signal. An error signal is generated that represents the amount that the incoming data has been shifted in time. If the error signal indicates that the incoming data has drifted significantly (e.g., by plus or minus two clock phases), the phase pointer is shifted accordingly. If, however, the error signal indicates that the incoming data has changed only a relatively small amount (e.g., by plus or minus one clock phase), the phase pointer is not changed.

The control circuitry may use a count-down timer to ensure that phase pointer adjustments are not made too quickly. By restraining the speed at which the control circuitry adjusts the multiplexer control signal, the control circuitry implements a low-pass filter scheme. The low-pass filter scheme represents a form of signal averaging, which ensures that the control algorithm is stable and provides good data recovery performance.

Any suitable circuitry may be used to receive and deserialize incoming data. An illustrative data recovery circuit32that may be used to receive and deserialize incoming data for a module24is shown inFIG. 3.

Illustrative data recovery circuit32ofFIG. 3includes control circuitry68. Control circuitry68includes a phase detector50, shift decision circuit56, and shift register62. This is, however, merely one possible circuit implementation for data recovery circuit32. Any suitable receiver circuitry that receives data with zero delay may be used for receiving circuitry in modules24if desired.

As shown inFIG. 3, an incoming serial data signal DATA is received at sampler40from another module using a data path26. Sampler40receives a multiphase clock signal on path36. The multiphase clock signal may be generated locally (e.g., in the same module24in which it is used) or multiple modules may share a multiphase clock signal. The multiphase clock signal may have any suitable number of phases. In the example ofFIG. 3, the multiphase clock has five phases, so path36contains five separate clock lines. The five phases of the multiphase clock are labeled P1, P2, P3, P4, and P5, respectively. Each of the five multiphase clock signals [P1. . . P5] is shifted by 72° (one fifth of a clock period) with respect to the other, as shown in the upper five traces ofFIG. 7.

Sampler40uses the multiphase clock signal to generate a corresponding set of sampled data signals [S1. . . S5]. Clock phase P1is used to sample data signal DATA and results in sampled data signal S1. Similarly, phases P2-P5are used to produce respective sampled data signals S2-S5. There is a different phase offset between the incoming data signal DATA and each of the multiphase clock signals.

The sampler40may capture data using edge-triggered flip-flops. With this type of arrangement, the sampled data will be noisy whenever the sampling clock phases are close to the edge of the signal DATA. Optimum data sampling occurs when the edge of a clock is aligned with the center of the incoming data pulses. By analyzing the sampled data signals S1-S5, the control circuitry68can determine which of the multiple phases of the multiphase clock represents the optimum clock phase to use to sample the incoming data. When the optimum clock phase is used, the sampled data will contain a minimum number of errors.

Control circuitry68produces a control signal that indicates which of the phases of the clock signal is to be used in receiving the incoming data. This control signal is sometimes referred to as a phase pointer signal. As shown inFIG. 3, the phase pointer signal, which is represented by a vector PHASE POINTER=[a, b, c, d, e], is stored in a shift register62. The number of individual register elements in register62matches the number of phases in the multiphase clock and the number of elements in the PHASE POINTER vector. If, for example, there are five separate phases in the multiphase clock signal, register62contains five registers, each of which stores a value of one of the phase pointer elements.

With this type of arrangement, a first register in shift register62is used to store the value of a, a second register in shift register62stores the value of b, a third register stores c, and fourth and fifth registers store d and e, respectively. The values of four of the phase pointer vector elements are zero. The value of the remaining phase pointer vector element, which represents the state of the phase pointer, is equal to one. A typical state for the vector PHASE POINTER is (0, 0, 1, 0, 0).

The signal PHASE POINTER is fed back to the control circuitry68using path64. The signal PHASE POINTER is also applied to the control input of multiplexer44using path66. Multiplexer44receives the sampled data signals S1-S5from sampler40. The state of PHASE POINTER determines which of the sampled data signals S1-S5is passed from paths42to path46via multiplexer44. For example, if PHASE POINTER is (1, 0, 0, 0, 0), the first of the five sampled data lines42at the inputs to multiplexer44will be connected to the output of multiplexer44. In this situation, sampled data signal S1will be routed from path42to path46. As another example, if PHASE POINTER is (0, 1, 0, 0, 0), the second sampled data signal (S2) will be passed to the multiplexer output.

On line46, the selected sampled data (e.g., signal S1or S2) is referred to as the signal RECOVERED DATA, as shown inFIG. 3. Deserializer30receives the RECOVERED DATA signal from path46and passes this signal to deserializer30. Deserializer30converts the serial RECOVERED DATA signal to parallel data on lines38. The parallel data on lines38is used by circuitry within the module24that has received the incoming data.

When appropriate, the control circuitry68updates the value of PHASE POINTER to ensure that incoming data is received using an optimal clock phase. The shift register62can be controlled using shift right signal SR and shift left signal SL. If, for example, the signal SR is high (e.g., a logic one) and signal SR is low (a logic zero), the location of the logic one in the registers of shift register62will be shifted to the right. As a result, a PHASE POINTER vector in the shift register that has a value of (0, 0, 1, 0, 0) will be shifted to a value of (0, 0, 0, 1, 0) (as an example). If, on the other hand, the value of SR is low and the value of SL is high, the position of the PHASE POINTER will be shifted to the left. When both SR and SL are low, the current value of the PHASE POINTER vector is left unchanged.

Control circuitry68includes a phase detector50and shift decision circuit56. The phase detector50receives sampled data signals S1-S5on signal path48(e.g., a five-line parallel signal bus). Phase detector50also receives a fed-back version of the current PHASE POINTER signal from shift register62on feedback path64. By analyzing the sampled data signals S1-S5and the current state of PHASE POINTER, the phase detector50can generate right and left shift register control signals R and L on respective lines52and54to control the PHASE POINTER. The shift decision circuitry56generates the signals SR and SL for shift register62based on the R and L control signals. The shift decision circuitry56averages or otherwise filters the signals R and L, which helps ensure that circuit32will exhibit good jitter tolerance. The R and L control signals are provided to shift decision circuit56using lines52and54, respectively. The shift decision circuit56generates corresponding filtered shift register control signals SR and SL on lines60and58, respectively.

FIG. 4shows an illustrative circuit that may be used for sampler40ofFIG. 3. As shown inFIG. 4, data may be provided to sampler40on a data path26. The incoming data signal DATA may be distributed to registers70(e.g., D-Q flip-flops) using distribution path72. Each register is clocked using a separate one of the clock phases. Register R1is clocked using clock phase P1, register R2is clocked using clock phase P2, and clock phase P3is used to clock register R3. Registers R4and R5are clocked using clock signals P4and P5, respectively.

As registers70are clocked with their respective clock signals, the data signal DATA on line26is sampled. The sampled data signals S1-S5are provided on output lines42at the outputs of respective registers70. For example, when clock phase P1is used to sample DATA, the sampled data signal S1on the output42of register R1is produced. Similarly, sampled data signals S2-S5are produced at the outputs of registers R2-R5using respective clock phases P2-P5.

The relative timing between each of the clock phases and the data signal is different. Samples that are taken with a clock phase that is too near an edge of the data signal are not predictable, but at least one of the signals produces an optimum result. Optimum data sampling typically results when the data is sampled at a point that is midway between its rising and falling edges. When a clock phase that has its rising edge aligned with the midpoint of the data signal DATA is used to sample the data, an optimum predictable sampled data signal is produced. Due to drift between the clock signal phases and the data signal, the optimum clock phase will generally change as a function of time. Control circuitry68ofFIG. 3computes the optimum clock phase for data recovery and updates the optimum clock phase as a function of time, using circuitry such as phase detector40and shift decision circuit56ofFIG. 3.

Phase detector circuitry50that may be used in a data recovery circuit of the type shown inFIG. 3is shown inFIG. 5. The phase detector circuitry50ofFIG. 5is merely illustrative. In general, any suitable phase detector circuitry may be used if desired. In the example ofFIG. 5, phase detector circuitry50includes five input lines64, each of which receives a respective element of the five-element PHASE POINTER vector (i.e., the elements a, b, c, d, e) from shift register62. Sampled data signals S1-S5are provided to exclusive OR gates72via paths80.

Exclusive OR gates72analyze the sampled data signals S1-S5to identify the location of the edge of the signal DATA. Phase detector circuit50can deduce the location of the midpoint of the data signal from the location of the data signal edge and can therefore identify the optimum clock phase to use in recovering the data signal. The outputs of the exclusive OR gates72are data edge location signals Ta, Tb, Tc, Td, and Te on output lines82. Signals Ta, Tb, Tc, Td, and Te indicate the location of the data edge.

For example, if data samples S1, S2, S3, S4, and S5have the values 1, 1, 1, 0, and 0, respectively, signals Ta, Tb, Tc, Td, and Te will have the values 0, 0, 1, 0, 0, respectively. The signal Tc is high, because the transition between the data value of 1 and the data value of 0 occurs between data sample S3and S4. Because the sampled data is high for samples S1, S2, and S3and is low for samples S4and S5, the edge of the data signal lies at a time between the rising edge of clock phase P3and the rising edge of clock phase P4. This is reflected by the high value of Tc.

If, as another example, the data samples S1, S2, S3, S4, and S5were to have the values 1, 1, 0, 0, and 0, respectively, signals Ta, Tb, Tc, Td, and Te will have the values 0, 1, 0, 0, 0, respectively. In this scenario, the signal Tb is high, because the transition between the data value of 1 and the data value of 0 occurs between data sample S2and S3. The sampled data is high for samples S1and S2and is low for samples S3, S4, and S5, indicating that the edge of the data signal lies at a time between the rising edge of clock phase P2and the rising edge of clock phase P3. The value of Tb is therefore high while the remaining components of the data edge location signal (Ta, Tc, Td, and Te) are low.

Based on knowledge of the location of the data edge, the control circuitry68can determine which of the multiple clock phases should be used to sample the incoming data. The optimum clock phase is generally aligned with the midpoint of the signal DATA and is shifted two clock phases with respect to the position of the edge of signal DATA. For example, if the data edge lies between the edges of clock phases P3and P4, the middle of the signal DATA lies at about the edge of clock phase P1. As a result, optimum results will be obtained by using the clock phase P1to sample DATA. The resulting sampled data (S1) can be provided to deserializer30. Control circuitry68and multiplexer44are used to ensure that the optimum sampled data (S1in this example) is routed to deserializer30.

The AND gates72receive the edge location signal values Ta-Te and the value of the PHASE POINTER and produce corresponding outputs for OR gates76and78on lines84. The OR gate76produces the L signal on line54. The OR gate78produces the R signal on line52.

The signal PHASE POINTER provides phase detector50with information on the current clock phase that is being used to recover data. If, for example, the current clock phase is P1and sampled data S1is being used as the recovered data, the current value of PHASE POINTER will be equal to (1, 0, 0, 0, 0). If the DATA signal drifts, the values of S1-S5will change. Through the operation of exclusive OR gates72, the values of Ta-Te will be updated to reflect the new location of the edge of the data signal. The AND gates72and OR gates76and78use the most recent information on the location of the data signal edge (Ta-Te) and information on the current setting for multiplexer44(PHASE POINTER) to determine whether the value of PHASE POINTER needs to be changed. If the sampled data signal that is being used for RECOVERED DATA needs to be changed to reflect drift in the position of the edge of DATA, the AND gates72and OR gates76and78will generate suitable R and L signals on outputs54and52.

The signals R and L on lines54and52change rapidly as the position of the date edge shifts in real time. To increase jitter tolerance, it may be desirable to introduce a low-pass filter into the control algorithm.FIG. 6shows an illustrative shift decision circuit56that may be used to implement a low-pass filter in the control circuitry68. The low-pass filtering provided by circuit56helps to ensure that the response of the control circuit68to sudden shifts in the position of the data edge is dampened.

The inputs to shift decision circuit56ofFIG. 6are unfiltered left and right control signals L and R (provided on input lines54and52, respectively) and clock signal CLK (provided on clock input line86). The outputs of circuit56are the filtered control signals SR and SL on lines60and58. Unfiltered left control signal L and clock signals CLK are provided to the inputs of 8-state counter88. The 8-state counter88provides a corresponding output signal A on output line96. Unfiltered shift right control signal R and clock signal CLK are provided to the inputs of 8-state counter90. The 8-state counter90produces a corresponding output signal B on line98. The AND gate92receives the signal A and the unfiltered shift right control signal R at its inputs and produces the filtered shift right control signal SR at output60. The AND gate94receives the signal B and the unfiltered shift left signal L at its inputs and produces a corresponding filtered shift left signal SL.

The 8-state counters88and90are countdown counters. When initialized, the count value of these counters is equal to 111 (8). During counting operations, the count value is decremented by one during each clock cycle. So long as the count value is greater than 0, the outputs of outputs of the 8-state counters88and90are low (a logical zero). When the count of 8-state counter88reaches 000 (0), the output A goes high. The output B goes high when counter90reaches a count value of 0.

The shift decision circuit56implements a low-pass filter algorithm. Whenever the signal L or the signal R goes high, the count of its associated counter is set to 111. With each subsequent clock cycle, the count of the clock is decremented by one. If the counter value associated with a given counter reaches 0, the output of that counter goes high.

Whenever it is determined that the data signal DATA has shifted sufficiently to warrant a corresponding change in the setting of multiplexer44, phase detector50generates a corresponding error signal in the form of an R or L signal. If the one stored in the shift register62is to be shifted to the right, the signal R is taken high. If the one stored in the shift register62is to be shifted to the left, the signal L is taken high. Circuit56filters the unfiltered R and L signals, so that updates to the setting of multiplexer44are not made too frequently.

Consider, as an example, a situation in which the signal L goes high. When L goes high, the L input to AND gate94goes high. The B output of 8-state counter90will be high, provided that the R signal has been low for eight clock cycles. In this situation, both inputs to AND gate94will be high and the filtered shift left signal SL at output58of AND gate94will go high. Note, however, that the SL signal will only go high if the high L signal has not been contradicted by a high R signal for 8 clock cycles. Because any activity on R within these 8 clock cycles will prevent SL from going high, the circuit56acts as a low-pass filter. Rapid fluctuations on the R and L signals on the inputs of circuit56will prevent the outputs SL and SR from going high. As a result of this averaging effect, the decision circuit56serves to improve the jitter tolerance of data recovery circuit32.

The operation of data recovery circuit32can be further understood with reference to the examples ofFIG. 7. The lowermost two traces ofFIG. 7correspond to two illustrative conditions for the data signal DATA that is being received at the input to sampler40ofFIG. 3. The traces are labeled DATA1and DATA2. The trace labeled DATA1has a falling edge at time ta. The trace labeled DATA2has a falling edge at time tb.

Consider the situation in which the incoming data signal DATA has the waveform shows as DATA1inFIG. 7and the PHASE POINTER signal is (1, 0, 0, 0, 0). In this configuration, multiplexer44is passing the sampled data signal S1to its output. Sampler40uses clock phases P1-P5to sample the data. The locations of the rising edges of the clock phases P1-P5are shown in the five uppermost traces ofFIG. 7. When these clock phases are used to sample DATA1, the value of the samples S1-S5from the outputs of sampling registers R1-R5in sampler40ofFIG. 4will be (1, 1, 1, 0, 0). Phase detector circuit50ofFIG. 5receives the PHASE POINTER signal (1, 0, 0, 0, 0) and the samples (1, 1, 1, 0, 0) at inputs64and52and produces corresponding edge location signals Ta, Tb, Tc, Td, and Te (0, 0, 1, 0, 0) at outputs82. In this state, each of the AND gates74has at least one low input, so the signals on lines84and the R and L outputs of OR gates78and76are low. The R and L signals are provided as inputs to circuit56ofFIG. 3. So long as no changes occur in eight cycles of CLK, the corresponding filtered control signals SR and SL that are produced at the output of circuit56ofFIG. 6will also be low. Because SR and SL are low, the output of shift register62is not changed and the value of PHASE POINTER remains the same.

Assume, due to environmental changes in the circuitry22, that the signal DATA experiences signal drift. This drift causes the signal DATA to shift in relationship to the phase clocks P1-P5. In particular, the DATA signal in the present example moves from the position indicated by DATA1to the position indicated by DATA2. In this situation, the data signal has shifted significantly, so the clock phase P1will no longer be the optimal clock phase to use in capturing the data signal. As a result, the PHASE POINTER will need to be updated.

Because DATA2transitions from high to low at a time tbthat lies between the rising edge of clock phase P1(time t1) and the rising edge of clock phase P2(time t2), the samples S1, S2, S3, S4, and S5that are produced at the output of sampler40will be 1, 0, 0, 0, and 0, respectively. At the outputs82of exclusive OR gates72, the signals Ta, Tb, Tc, Td, and Te will be 1, 0, 0, 0, and 0, respectively (indicating that DATA2falls from high to low between t1and t2). The value of PHASE POINTER (a, b, c, d, e) is equal to (1, 0, 0, 0, 0), as described in connection with the sampling of DATA1. Because the value of PHASE POINTER element “a” is high and because Ta is high, AND gate A1ofFIG. 5has two high inputs. The output of AND gate A1is therefore high, which takes L high. This high signal is provided to the input of OR gate76via line84-1, which takes the output L of OR gate76high.

As this example demonstrates, when the signal DATA shifts by two clock phases (plus or minus), a corresponding shift register control signal (R or L) is taken high. Shifts of less than plus or minus two clock phases (i.e., shifts of only plus or minus one clock phase or shifts of no clock phases) do not result in a non-zero shift register control signal. Rather, when there is a data signal shift of less than or equal to one clock phase in magnitude, the values of R and L remain at zero. This control algorithm, which is implemented by circuit50ofFIG. 5, increases jitter tolerance, because the sampling position represented by the setting of multiplexer44is not updated unless there is a substantial (e.g., 2 or more clock phase) phase shift in the data signal.

In the present example, there are five clock phases and the shift control signals R and L are active only upon changes of two or more clock phases. This is merely illustrative. Any suitable number of clock phases may be used by sampler40and the threshold for making PHASE POINTER updates may be set at any suitable level. As one example, there may be ten clock phases in use and the threshold for shifting the contents of shift register62may be set to four clock phases by proper configuration of the phase detector circuitry. As another example, there may be 20 clock phases in use and the threshold for shifting the contents of the shift register62may be set to eight clock phases. The threshold error for shifting will typically be at least two (two, four, and eight are all greater than or equal to two in these examples).

Illustrative steps involved in using this type of control algorithm during the data recovery operations of data capture circuit32ofFIG. 3are shown inFIG. 8.

At step100, programmable logic or other circuitry within one of the modules24of circuitry22(FIG. 2) generates data to be transmitted to another module24.

At step102, the transmitting module24uses a serializer28(FIG. 2) to serialize and transmit the data over a serial communications path26.

At step104, data recovery circuitry such as data recovery circuit32in the receiver of a receiving module24recovers the incoming serial data.

At step114, the recovered data is deserialized using a deserializer30and is routed to parallel signal lines such as lines38ofFIG. 3for use by the circuitry of the receiving module.

Multiple substeps are involved in the operations of step104.

During step106, sampler40samples the incoming data using a multiphase clock. In the example ofFIG. 3, a five-phase multiphase clock having signals P1, P2, P3, P4, and P5is used to sample incoming data at various different sample points. Because five samples are taken per data clock cycle, this approach is sometimes referred to as five-times oversampling.

At step108, the data recovery circuit32uses control circuitry68to determine how far shifted the data signal DATA is shifted with respect to the clock phase and sampled data stream that are currently being used. The deviation between the optimum clock phase that is to be used to sample the incoming data and the clock phase setting that is already in use (i.e., the current value of PHASE POINTER and the current setting of multiplexer44) is sometimes referred to as a clock phase shift error signal.

At step110, the control circuitry68uses a non-linear control algorithm to update PHASE POINTER and thereby eliminate the deviation between the desired optimum sampling point and the current sampling point. The updated value of PHASE POINTER is fed back to phase detector50using path64(FIG. 3) (step112). The updated PHASE POINTER value is also applied to the control terminal of multiplexer44via path66(FIG. 3). As indicated by line113, the data recovery process may operate continuously.

During step104, the control circuitry68computes the phase error and determines which corrections need to be made to the value of PHASE POINTER using a non-linear control algorithm. The non-linear control algorithm preferably includes a time delay (averaging) component that serves as a low-pass filter, as described in connection with the discussion ofFIG. 6. With the non-linear control algorithm, corrections to the current value of PHASE POINTER are preferably not made unless the error exceeds a predetermined threshold amount. In the example described in connection withFIGS. 3 and 6, the multiphase clock included five clock phases and the error threshold was set at two clock phase deviations from the correct alignment point. With this type of arrangement, PHASE POINTER updates are not made by the control circuitry68and its non-linear control algorithm unless the computed error is at least two clock phases. Errors of one clock phase (or errors of zero when the sampling point is correctly aligned) fall below the two clock phase threshold and do not result in any change to PHASE POINTER.

Although described in connection with an example in which the multiphase clock has five separate clock phase signals and the error threshold equals two clock phases, and changes to the PHASE POINTER are low-pass filtered using counters or other such circuitry in a shift decision circuit, the data recovery circuit may use any suitable non-linear control algorithm arrangement. The use of the non-linear control algorithm described in connection with control circuitry68ofFIG. 3is merely illustrative.

The non-linear control algorithm that is implemented by the control circuitry68allows incoming data to be received with zero delay, while exhibiting good jitter tolerance. A jitter tolerance simulation has been performed for the non-linear control algorithm described in connection withFIG. 3. The results of this simulation are plotted in the graph ofFIG. 9. The jitter tolerance simulation ofFIG. 9was performed using 20,000 bits of PRBS7 data (approximately 100,000 samples). The update period was set to eight symbol periods, consistent with the use of 8-state counters88and90in circuit56ofFIG. 6. The curve ofFIG. 9exhibits a relatively high value of jitter tolerance (about 0.8 unit intervals) starting at a relatively high jitter-frequency/baud-rate value of 7×10−3, indicating that the control algorithm implemented by control circuitry68exhibits good high-frequency jitter tolerance.

The serial interconnect scheme of the present invention can exhibit a bandwidth that is comparable to parallel clocking schemes. Consider, as an example, a parallel clocking arrangement using a 500 MHz clock and a 16-bit parallel bus. In this situation, the bandwidth of the bus would be about 16*0.5 GHz=8 Gbps. In comparison, a typical serial link26may have a bandwidth of about 10 Gbps. Because data can be transmitted over serial links26in nearly the same clock cycle that it is generated, there is essentially no latency penalty imposed on serially transmitted data. At the same time, the amount of hardware resources that are consumed by interconnects on device10can be substantially reduced by replacing numerous parallel interconnects with relatively fewer serial interconnects.

The data recovery circuit32(e.g., circuitry of the type described in connection withFIG. 3) may be implemented using hardwired circuitry, programmable logic, or a combination of hardwired circuitry and programmable logic.

Programmable logic device integrated circuit10may be loaded with configuration data from a configuration data loading device116, as shown inFIG. 10. Configuration data loading device116may be any suitable equipment for loading configuration data into programmable logic device10. In a testing environment, device116may be a tester that uses a test fixture to load configuration data into device10. In a system environment, device116may be a configuration device integrated circuit that is located on the same system board as programmable logic device integrated circuit10(as an example). During system power-up operations or at other suitable times, configuration data may be loaded from the configuration device into programmable logic device10to program device10to implement a desired logic design. When it is desired to implement some or all of data recovery circuit32from programmable logic, part of the configuration data that is loaded into programmable logic device10configures programmable logic18(FIG. 1) to implement the data recovery circuit32(or part of circuit32).

Illustrative steps involved in configuring programmable logic device10to perform the functions of data recovery circuit32are shown inFIG. 11.

At step118, a logic designer uses computer-aided design (CAD) tools to generate a desired logic design for programmable logic device10. The logic design may be entered using design entry tools. Logic synthesis tools and placement and routing tools may be used to determine how to implement the logic design from the hardwired and programmable logic resources available on a given programmable logic device10.

At step120, the CAD tools generate configuration data from the logic designer's logic design specifications.

At step122, the configuration data that has been generated is provided to the configuration data loading device116. For example, the configuration data may be stored in non-volatile memory on a system board or may be stored in non-volatile memory in a configuration device integrated circuit.

At step124, the configuration data is loaded from configuration data loading device116(FIG. 10) into programmable logic device integrated circuit10. Once loaded, the configuration data implements all or part of data recovery circuit32from programmable logic18. Device10and its data recovery circuit32may then be used in a system.