Semiconductor structures and methods of forming the same

A structure and method of forming the structure is disclosed. According to an embodiment, a structure includes three devices in respective three regions of a substrate. The first device comprises a first gate stack, and the first gate stack comprises a first dielectric layer. The second device comprises a second gate stack, and the second gate stack comprises a second dielectric layer. The third device comprises a third gate stack, and the third gate stack comprises a third dielectric layer. A thickness of the third dielectric layer is less than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A gate length of the third gate stack differs in amount from a gate length of the first gate stack and a gate length of the second gate stack.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.

In the course of IC evolution, functional density (e.g., the number of interconnected devices per chip area) has generally increased while geometry size (e.g., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, by continuously scaling down devices, differences between various performance characteristics of interconnected devices may become exacerbated.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.

Embodiments will be described with respect to a specific context, namely a process for forming semiconductor devices, where at least three of the devices include a dielectric layer in a gate stack with differing thicknesses between the devices. Further, gate lengths of the devices can be biased in various ways. Other embodiments contemplate varying number of devices and/or dielectric layer thicknesses, as well as differing biasing. Although described in a particular order below, method embodiments can be performed in any logical order. Additionally, like reference numbers used in the figures refer to like components.

FIGS. 1 through 8illustrate a process flow and structures according to an embodiment.FIG. 1illustrates a substrate20. The substrate20may be a semiconductor substrate, which may further be a silicon substrate, a silicon carbon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate20may be a bulk substrate, a semiconductor-on-insulator (SOI) substrate, or other acceptable substrates. The substrate20may be lightly doped with a p-type or an n-type impurity. A first region22, a second region24, a third region26, and a fourth region28of the substrate20are identified inFIG. 1. In an embodiment, the first region22is a thin core region, such as containing devices for core circuitry where transistors have a thin gate dielectric; the second region24is a thick core region, such as containing devices for core circuitry where transistors have a relatively thicker gate dielectric; the third region26is an input/output region, such as containing devices used for inputting and/or outputting signals; and the fourth region28is a memory region, such as a SRAM region.

The substrate20further comprises isolation regions30, such as shallow trench isolation regions. The isolation regions30may be used to electrically isolate active areas of separate devices in the substrate20. Some isolation regions30can also demark boundaries between adjacent ones of the first, second, third, and fourth regions22,24,26, and28, respectively. The formation of isolation regions30may include etching the substrate20to form trenches (not shown), and filling the trenches with a dielectric material to form isolation regions30. The isolation regions30may be formed of silicon oxide deposited by a high density plasma, for example, although other dielectric materials formed according to various techniques may also be used.

A first dielectric layer32is formed over the substrate20. In an embodiment, the first dielectric layer32is an oxide layer formed by a thermal oxidation, a high density plasma deposition or the like. In other embodiments, the first dielectric layer32can be silicon oxynitride or the like formed by any acceptable technique. The first dielectric layer32can have a thickness of between about 25 Å and about 40 Å. Although specific thicknesses are provided herein as examples, different embodiments may have other thicknesses, such as for different technology sizes.

FIG. 2illustrates the formation of a thick interfacial layer36in the second region24and the fourth region28. The first dielectric layer32is removed from the second region24and the fourth region28, for example, by patterning a photoresist34over the first dielectric layer32to cover the first region22and the third region26while exposing the second region24and the fourth region28and subsequently etching the exposed portions of the first dielectric layer32, for example, by an immersion in dilute hydrofluoric acid (dHF). The thick interfacial layer36is deposited on the substrate20in the second region24and the fourth region28. The thick interfacial layer36can comprise silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof, and can be formed using thermal oxidation or chemical oxidation, for example, dipping in ozone de-ionized (DI) water, an appropriate deposition technique, or the like. In an embodiment, the thick interfacial layer36has a thickness between about 10 Å and about 20 Å. In an embodiment, the thick interfacial layer36has a thickness less than a thickness of the first dielectric layer32. The photoresist34can be subsequently removed using, for example, an appropriate ashing process.

FIG. 3illustrates the formation of a thin interfacial layer40in the first region22. The first dielectric layer32is removed from the first region22, for example, by patterning a photoresist38over the first dielectric layer32in the third region26and the thick interfacial layer36in the second and fourth regions24and28while exposing the first region22and subsequently etching the exposed portions of the first dielectric layer32, for example, by an immersion in dHF. The thin interfacial layer40is deposited on the substrate20in the first region22. The thin interfacial layer40can comprise silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof, and can be formed using thermal oxidation or chemical oxidation, for example, dipping in ozone DI water, an appropriate deposition technique, or the like. In an embodiment, the thin interfacial layer40has a thickness between about 10 Å and about 15 Å. In an embodiment, the thin interfacial layer40has a thickness less than a thickness of the thick interfacial layer36. In a further embodiment, the thickness of the thin interfacial layer40is equal to or greater than about 1 Å, such as between about 1 Å and about 5 Å, less than the thickness of the thick interfacial layer36. The photoresist38can be subsequently removed using, for example, an appropriate ashing process.

FIG. 4shows a high-k dielectric layer42formed on the thin interfacial layer40, the thick interfacial layer36, the first dielectric layer32, and the thick interfacial layer36in the first, second, third, and fourth regions22,24,26, and28, respectively. The high-k dielectric layer42can include hafnium oxide (HfO2) or other materials, such as a metal oxide, a nitrided metal oxide, or a silicate of Hf, Al, La, Zr, Ti, Ta, Ba, Sr, Pb, Zn, Y, Gd, Dy, combinations thereof, and multi-layers thereof. Specific examples include HfO2, HfZrOx, HfAlOx, HfLaOx, HfTiOx, HfTaOx, HfTiTaOx, LaO3, ZrO2, Al2O3, Ta2O5, TiO2, and combinations thereof. The high-k dielectric layer42can be formed using atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), plasma enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD), or the like. In an embodiment, the k value of the high-k dielectric layer42is greater than about 7.0. In some embodiments, the high-k dielectric layer42has a thickness of at least 10 Å, such as between about 10 Å and about 15 Å, although other embodiments contemplate any thickness.

InFIG. 5, a capping layer44is formed on the high-k dielectric layer42in the first, second, third, and fourth regions22,24,26, and28, respectively. Example materials for the capping layer44include tantalum, titanium, molybdenum, tungsten, ruthenium, platinum, cobalt, nickel, palladium, niobium, and alloys and/or nitrides thereof. Specifically, the capping layer44may comprise metal nitrides, such as TiN and TaN. The capping layer44may be formed by PVD, ALD, or other applicable chemical vapor deposition (CVD) methods. The capping layer44may have a thickness between about 1.5 nm and about 4 nm.

FIG. 6illustrates the formation of a gate electrode layer46on the capping layer44in the first, second, third, and fourth regions22,24,26, and28, respectively. The gate electrode layer46comprises a conductive material, such as polysilicon (doped or undoped), a metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), a metal nitride (e.g., titanium nitride, tantalum nitride), the like, or a combination thereof. The gate electrode layer46can be deposited using CVD, LPCVD, PVD, or other acceptable deposition techniques. If the deposition of the gate electrode layer46is conformal, a planarization technique, such as a chemical mechanical polish (CMP), may be used to planarize the gate electrode layer46.

FIG. 7illustrates the formation of gate stacks50and52in the first region22, gate stacks54and56in the second region24, gate stacks58and60in the third region26, and gate stacks62and64in the fourth region28. Gate stacks50and52comprise the thin interfacial layer40, the high-k dielectric layer42, the capping layer44, and the gate electrode layer46. Gate stacks54,56,62, and64comprise the thick interfacial layer36, the high-k dielectric layer42, the capping layer44, and the gate electrode layer46. Gate stacks58and60comprise the first dielectric layer32, the high-k dielectric layer42, the capping layer44, and the gate electrode layer46. The gate stacks50,52,54,56,58,60,62, and64can be formed by depositing a mask layer over the gate electrode layer46and depositing a photoresist over the mask layer. The photoresist can be patterned using photolithography, and a subsequent etch can transfer the pattern of the photoresist to the mask layer. Using the mask layer, the various layers of the gate stacks50,52,54,56,58,60,62, and64can be etched to form the gate stacks50,52,54,56,58,60,62, and64. The various masking and/or etching steps can be performed simultaneously for all of the gate stacks50,52,54,56,58,60,62, and64, or some masking and/or etching steps can be performed for gate stacks within only one or more region while similar masking and/or etching steps are performed separately for gate stacks within another region.

FIG. 7further depicts example gate lengths66,68,70, and72and pitches74and76. InFIG. 7, the gate lengths are distances between opposing sidewalls of a gate stack. Gate lengths66,68,70, and72are shown for gate stacks50,52,54, and56, respectively. InFIG. 7, the pitches are distances between corresponding sidewalls of adjacent gate stacks. Pitch74is shown between gate stacks50and52, and pitch76is shown between gate stacks54and56. The other gate stacks and other regions also have pitches and gate lengths that are not explicitly depicted.

Various gate lengths can be modified or biased for a particular application. For example, the gate lengths70and72of gate stacks54and56, respectively, can be a critical dimension, and the gate lengths66and68of gate stacks50and52can vary from that critical dimension, such as by about +/−5 nm. In that example, the gate lengths of gate stacks58,60,62, and64can also be the critical dimension, and hence, the gate stacks50and52in the first region22can have a gate length bias with respect to the critical dimension used in the gate stacks in the second, third, and fourth regions24,26, and28, respectively. Further, the gate stacks50and52can have differing gate lengths66and68, e.g., can be biased differently. In an embodiment, the gate lengths of gate stacks54,56,58,60,62, and64are a critical dimension, such as about 30 nm, and the gate lengths66and68of gate stacks50and52are about 2 to about 3 nm greater than the critical dimension, such as about 32 nm to about 33 nm. In other embodiments, the gate stacks54,56,58,60,62, and64have gate lengths that vary from each other, e.g., some of the gate stacks54,56,58,60,62, and64can also be biased.

In some embodiments, pitches between neighboring gate stacks within a region are equal to pitches between neighboring gate stacks within other regions. For example, pitch74between gate stacks50and52, pitch76between gate stacks54and56, pitch between gate stacks58and60, and pitch between gate stacks62and64are equal. In an embodiment, these pitches are between about 90 nm and about 150 nm, such as about 130 nm, although various other pitches can be used, such as with differing technology nodes. In other embodiments, the pitches can vary between regions and/or among various devices within a given region.

FIG. 8illustrates the formation of spacers80and source/drain regions82for various transistors comprising respective ones of the gate stacks50,52,54,56,58,60,62, and64. The spacers80and source/drain regions82are depicted for each gate stack, but not all are specifically indicated with a reference numeral so as not to obscure the depiction. The spacers80are formed on the sidewalls of the gate stacks50,52,54,56,58,60,62, and64, such as by blanket depositing a spacer layer and subsequently anisotropically etching the spacer layer to leave the spacers80. The spacers layer can comprise silicon nitride, an oxynitride, silicon carbide, silicon oxynitride, an oxide, and the like, and can be deposited by methods such as CVD, PECVD, sputter, and other suitable techniques.

Source/drain regions82are formed in the substrate20on opposing sides of the gate stacks50,52,54,56,58,60,62, and64. In an embodiment in which a transistor to be formed is a p-type transistor, such as a pFET, the source/drain regions82can be formed by implanting appropriate p-type dopants such as boron, gallium, indium, or the like. Similarly, in an embodiment in which a transistor to be formed is an n-type transistor, such as an nFET, the source/drain regions82can be formed by implanting appropriate n-type dopants such as phosphorus, arsenic, or the like. Many other processes, steps, or the like may be used to form the source/drain regions82.

Although not explicitly shown, a person having ordinary skill in the art will readily understand that further processing steps may be performed on the structure inFIG. 8. For example, an etch stop layer may be formed over and adjoining the transistors comprising the gate stacks50,52,54,56,58,60,62, and64, and an interlayer dielectric (ILD) can be formed over the etch stop layer. Contacts to respective source/drain regions82can be formed in the ILD. Another etch stop layer can be formed over the ILD, and inter-metal dielectrics (IMDs) and their corresponding metallizations may be formed over the etch stop layer.

Embodiments may have advantages. For example, various devices in some embodiments can be designed to have better performance characteristics for a given application. By allowing differing dielectric thicknesses and by allowing for various gate biasing, a device can be more specifically designed to allow an application to perform better. One example is that a product level Iddq versus Fmax performance may be optimized.

An embodiment is a structure. The structure includes three devices in respective three regions of a substrate. The first device comprises a first gate stack, and the first gate stack comprises a first dielectric layer. The second device comprises a second gate stack, and the second gate stack comprises a second dielectric layer. The third device comprises a third gate stack, and the third gate stack comprises a third dielectric layer. A thickness of the third dielectric layer is less than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A gate length of the third gate stack differs in amount from a gate length of the first gate stack and a gate length of the second gate stack.

Another embodiment is a structure. The structure comprises first, second, and third regions of a substrate. The first region comprises a first device and a second device. The second region comprises a third device and a fourth device. The third region comprises a fifth device and a sixth device. The first, second, third, fourth, fifth, and sixth devices comprise a first, second, third, fourth, fifth, and sixth gate stack, respectively. The first gate stack and the second gate stack each comprise a first dielectric layer having a first thickness. The third gate stack and the fourth gate stack each comprise a second dielectric layer having a second thickness. The fifth gate stack and the sixth gate stack each comprise a third dielectric layer having a third thickness. The third thickness is greater than the second thickness, and the second thickness is greater than the first thickness. The first, second, third, fourth, fifth, and sixth gate stacks have a respective length between opposing sidewalls of the first, second, third, fourth, fifth, and sixth gate stacks, respectively. Each of the first length and the second length is different in dimension from each of the third length, the fourth length, the fifth length, and the sixth length. A first pitch is between the first gate stack and the second gate stack. A second pitch is between the third gate stack and the fourth gate stack. A third pitch is between the fifth gate stack and the sixth gate stack.

A further embodiment is a method. The method comprises forming a first dielectric layer in a first region of a substrate, forming a second dielectric layer in a second region of the substrate, forming a third dielectric layer in a third region of the substrate, forming a first gate stack comprising the first dielectric layer, forming a second gate stack comprising the second dielectric layer, and forming a third gate stack comprising the third dielectric layer. The first dielectric layer has a first thickness; the second dielectric layer has a second thickness; and the third dielectric layer has a third thickness. The first thickness is greater than the second thickness, and the second thickness is greater than third thickness. The first gate stack has a first gate length; the second gate stack has a second gate length; and the third gate stack has a third gate length. The third gate length is greater or less than the first gate length and the second gate length.