SEMICONDUCTOR DEVICE

A semiconductor device according to the present disclosure includes a source electrode provided on a substrate, a gate electrode provided-on the substrate and surrounding a part of the source electrode, a drain electrode provided on the substrate and surrounding the gate electrode, and a gate wiring provided on the substrate, wherein a first end of the gate wiring is connected to only one portion of the gate electrode and a second end of the gate wiring is connected to a first gate bus bar.

CROSS REFERENCE TO RELATED APPLICATIONS

The application claims priority based on Japanese Patent Application No. 2023-138187 filed on Aug. 28, 2023, and the entire contents of the Japanese patent application are incorporated herein by reference.

FIELD OF THE INVENTION

A certain aspect of the embodiments is related to a semiconductor device.

BACKGROUND OF THE INVENTION

In a field effect transistor (FET) having a finger-shaped source electrode, a finger-shaped gate electrode, and a finger-shaped drain electrode, it is known that a plurality of unit FETs having a source electrode, a gate electrode, and a drain electrode are arranged in the extending direction of the electrodes (for example, Patent Document 1: Japanese Laid-Open Patent Publication No. 2002-299351).

SUMMARY OF THE INVENTION

A semiconductor device according to an embodiment of the present disclosure includes a source electrode provided on a substrate; a gate electrode provided-on the substrate and surrounding a part of the source electrode; a drain electrode provided on the substrate and surrounding the gate electrode; and a gate wiring provided on the substrate, wherein a first end of the gate wiring is connected to only one portion of the gate electrode and a second end of the gate wiring is connected to a first gate bus bar.

DETAILED DESCRIPTION

When a plurality of unit FETs are arranged, it is difficult to miniaturize the semiconductor device. When the semiconductor device is to be miniaturized, the design may become difficult.

The present disclosure has been made in view of the above problems, and an object thereof is to reduce the size of the apparatus.

Description of Embodiments of the Present Disclosure

First, the contents of the embodiments of the present disclosure will be enumerated and described.

(1) A semiconductor device according to an embodiment of the present disclosure includes a source electrode provided on a substrate; a gate electrode provided on the substrate and surrounding a part of the source electrode; a drain electrode provided on the substrate and surrounding the gate electrode; and a gate wiring provided on the substrate, wherein a first end of the gate wiring is connected to only one portion of the gate electrode and a second end of the gate wiring is connected to a first gate bus bar. This allows the semiconductor device to be easily designed and reduced in size.

(2) In the above (1), the gate electrode may be provided in a loop shape on the substrate.

This allows miniaturization.

(3) In the above (1), the drain electrode may be provided on the substrate and may surround the gate electrode in a first direction, a direction opposite to the first direction, and a second direction intersecting the first direction. This allows miniaturization.

(4) In the above (3), the drain electrode may surround the gate electrode only from the first direction, the direction opposite to the first direction, and the second direction. This allows miniaturization.

(5) In the above (3), the first end of the gate wiring may be connected to a portion of the gate electrode not surrounded by the drain electrode in a direction opposite to the second direction, within a range having a width of ½ of a width of the portion in the first direction with a center point in the first direction. This makes it possible to make the gate widths of the two FETs effectively connected in parallel close to each other, and thus the design becomes easier.

(6) In the above (3), the drain electrode may surround the gate electrode from a direction opposite to the second direction. This makes it possible to increase the effective gate width, thereby making it possible to reduce the size of the device.

(7) In the above (3), a width of the source electrode in the second direction may be not more than three times and not less than one third times the width of the source electrode in the first direction. This improves the heat dissipation.

(8) In any one of the above (1) to (7), the semiconductor device may further include a metal layer provided under the substrate and electrically connected to the source electrode via a via hole penetrating the substrate. This allows miniaturization.

(9) In the above (3), the substrate may have an active region in which a semiconductor layer in the substrate is activated, and a region of the drain electrode surrounding the gate electrode in the first direction, the direction opposite to the first direction, and the second direction is provided on the active region. This allows miniaturization.

(10) In the above (3), the semiconductor device may further include FET groups each including a plurality of unit FETs arranged in the first direction, each of the unit FETs including the source electrode, the gate electrode, and the drain electrode, and adjacent ones of the unit FETs sharing the drain electrode, and a drain bus bar to which drain electrodes of a plurality of unit FETs in a first FET group among the FET groups are connected, the first FET group being interposed between the first gate bus bar and the drain bus bar, the first gate bus bar being connected to gate wirings of the plurality of unit FETs in the first FET group. This facilitates the design of the semiconductor device having a large gate width.

(11) In the above (10), the semiconductor device may further include a second FET group included in the FET groups, the drain bus bar being interposed between the first FET group and the second FET group, and a second gate bus bar connected to a plurality of unit FETs included in the second FET group interposed between the drain bus bar and the second gate bus bar. This facilitates the design of the semiconductor device having a large gate width.

(12) In the above (11), a width of the drain bus bar in the second direction may be larger than a width of the drain electrode shared by the unit FETs adjacent to each other in the first direction. This makes it possible to make the current density of the drain bus bar close to the current density of the drain electrode, thereby making it possible to reduce the size of the device.

(13) In the above (11) or (12), the semiconductor device may further include a gate pad electrically connecting the first gate bus bar and the second gate bus bar, and a drain pad electrically connected to the drain bus bar, the first FET group and the second FET group being interposed between the drain pad and the gate pad. This allows the gate pad and the drain pad to be efficiently arranged, thereby enabling miniaturization.

(14) In any one of the above (11) to (13), the semiconductor device may further include a plurality of unit arranged in the second direction, each of the plurality of units including the first FET group, the second FET group, the drain bus bar, the first gate bus bar, and the second gate bus bar. This allows the unit FETs to be efficiently arranged, thereby enabling miniaturization.

A description will be given, with reference to the accompanying drawings, of embodiments of semiconductor devices according to the present disclosure. It is to be understood that the present disclosure is not limited to these embodiments, but is intended to be set forth by the appended claims and to include all modifications within the meaning and scope of the equivalents of the appended claims.

FIRST EMBODIMENT

FIG.1is a plan view of a semiconductor device according to a first embodiment.FIG.2is a cross-sectional view taken along the line A-A inFIG.1. The thickness direction of a substrate10is defined as a Z direction, the direction in which a source electrode12is interposed between a drain electrode16cand a gate bus bar24is defined as an X direction, and the direction in which the source electrode12is interposed between the drain electrodes16aand16bis defined as a Y direction.

As illustrated inFIGS.1and2, in a semiconductor device100of the first embodiment, the substrate10includes a substrate10aand a semiconductor layer10bprovided on the substrate10a.In the XY plane parallel to the X direction and the Y direction, a region where the semiconductor layer10bis inactivated by ion implantation or the like is an inactive region13. An active region11is a region where the semiconductor layer10bis not inactivated but activated.

The source electrode12, a gate electrode14, a drain electrode16, a gate wiring23, the gate bus bar24, and a drain bus bar26are provided on the substrate10. A unit FET35includes the source electrode12, the gate electrode14, and the drain electrode16.

The source electrode12has a substantially rectangular shape in plan view, with sides extending in the X and Y directions. The gate electrode14is provided in a loop shape so as to surround the source electrode12. The gate electrode14includes gate electrodes14ato14d. The gate electrodes14aand14bextend in the X direction, and the source electrode12is interposed therebetween in the Y direction. The gate electrodes14cand14dextend in the Y direction, and the source electrode12is interposed therebetween in the X direction.

The drain electrode16surrounds the gate electrode14in the +direction (first direction) in the Y direction, the-direction (direction opposite to the first direction) in the Y direction, and the-direction (second direction perpendicular to the first direction) in the X direction. The drain electrode16includes drain electrodes16ato16c.The gate electrodes14ato14care interposed between the drain electrodes16ato16cand the source electrode12, respectively. The source electrode12, the gate electrodes14ato14c,and the drain electrodes16ato16care provided on the active region11of the substrate10.

The unit FET35has unit FETs35ato35c.The unit FET35aincludes the source electrode12, the gate electrode14a,and the drain electrode16a.The unit FET35bincludes the source electrode12, the gate electrode14b,and the drain electrode16b.The unit FET35cincludes the source electrode12, the gate electrode14c,and the drain electrode16c.

The gate electrode14dis provided on the inactive region13of the substrate10. The gate bus bar24is provided in a region on the inactive region13of the substrate10provided in the +direction in the X direction of the gate electrode14d,and extends in the Y direction. The gate wiring23is provided on the inactive region13, and electrically connects and short-circuits the gate electrode14dand the gate bus bar24.

The drain bus bar26includes the drain electrode16cand the drain electrode16provided on the inactive region13, and extends in the Y direction. The unit FET35is interposed between the gate bus bar24and the drain bus bar26in the X direction.

The via hole20penetrates the substrate10and connects to the source electrode12. A metal layer28is provided on the lower surface of the substrate10. A metal layer28ais provided on the inner surface of the via hole20. As a result, the metal layer28is electrically connected to the source electrode12through the via hole20, and is short-circuited. A reference potential such as a ground potential is supplied to the metal layer28.

When the semiconductor device100is, for example, a nitride semiconductor device, the substrate10ais, for example, a silicon carbide (SiC) substrate, a silicon substrate, a gallium nitride (GaN) substrate, or a sapphire substrate. The semiconductor layer10bincludes a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and/or an indium gallium nitride (InGaN) layer. When the unit FET35is a GaN HEMT (Gallium Nitride High Electron Mobility Transistor), the semiconductor layer10bincludes a gallium nitride channel layer provided on the substrate10aand an aluminum gallium nitride barrier layer provided on the gallium nitride channel layer. When the semiconductor device100is, for example, a gallium arsenide (GaAs)—based semiconductor device, the substrate10ais, for example, a gallium arsenide substrate. The semiconductor layer10bincludes an arsenide semiconductor layer, such as, for example, a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer and/or an indium gallium arsenide (InGaAs) layer. The semiconductor device100may be a silicon semiconductor device such as LDMOS (Laterally Diffused Metal Oxide Semiconductor).

The source electrode12and the drain electrode16include an ohmic contact layer37and a low resistance layer38. The gate wiring23and the gate bus bar24include a gate metal layer39and the low resistance layer38. The ohmic contact layer37is a metal layer in ohmic contact with the semiconductor layer10b,and is formed of, for example, a titanium film and an aluminum film, which are arranged in the order of the substrate10. The low resistance layer38is a metal layer having a lower resistivity than that of an ohmic contact layer such as a gold layer. The gate electrode14and the gate metal layer39are metal films, and for example, are a nickel film and a gold film from the substrate10side. An insulating layer may be provided so as to cover the source electrode12, the gate electrode14, the drain electrode16, the gate wiring23, and the gate bus bar24. The insulating layer is, for example, an inorganic insulating film such as a silicon nitride layer, a polyimide layer, or an organic insulating layer such as a BCB (Benzocyclobutane) layer. InFIG.2, the width of the ohmic contact layer37and the gate metal layer39is larger than the width of the low resistance layer38, but the width of the ohmic contact layer37and the gate metal layer39may be the same as the width of the low resistance layer38. The low resistance layer38may not be provided.

First Comparative Example

FIG.3is a plan view of a semiconductor device according to a first comparative example. As illustrated inFIG.3, in a semiconductor device110according to the first comparative example, the gate electrodes14cand14dand the drain electrode16care not provided. The gate electrodes14aand14bare directly connected to the gate bus bar24. The drain electrodes16aand16bare directly connected to the drain bus bar26. The drain bus bar26is provided on the inactive region13. In the first comparative example, two unit FETs35aand35bare provided for one source electrode12. The other configuration is the same as that of the first embodiment.

Second Comparative Example

FIG.4is a plan view of a semiconductor device according to a second comparative example. As illustrated inFIG.4, in a semiconductor device112according to the second comparative example, the gate electrode14cis provided to connect the −end of the gate electrode14ain the X direction and the −end of the gate electrode14bin the X direction. The drain electrode16cis provided to connect the −end of the drain electrode16ain the X direction and the −end of the drain electrode16bin the X direction. The drain electrode16cis provided on the active region11. Thus, three unit FETs35ato35care provided for one source electrode12. Therefore, the gate width of the unit FET35can be made larger than that of the first comparative example. The output of one source electrode12can be increased, and a higher output can be achieved. When the same output power is considered, the semiconductor device can be downsized. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.

When a high-frequency signal is supplied from the-end of the gate bus bar24in the Y direction as indicated by an arrow50c,one of the branched signals passes through the gate bus bar24and then flows through the gate electrode14aas indicated by an arrow50a.The other branched signal flows through the gate electrodes14band14cas indicated by the arrow50b.The signal flowing through the arrow50aand the signal flowing through the arrow50bare merged at a portion52where the electric lengths of the arrows50aand50bare the same, that is, a point where the gate electrodes14aand14care in contact with each other. Therefore, the unit FET35can be effectively regarded as an FET in which two FETs, a first FET having the unit FET35aand a second FET having the unit FETs35band35c,are connected in parallel. The effective gate widths up to the portion52are different between the first FET and the second FET. In this case, when a plurality of unit FETs35are arranged to design a high-frequency transistor, it is necessary to consider FETs having different effective gate widths, which makes the design difficult.

Description of First Embodiment

According to the first embodiment, as illustrated inFIG.1, the first end of the gate wiring23is connected to only one location51of the gate electrode14, and the second end of the gate wiring23is connected to the gate bus bar24. Accordingly, one of the signals branched at the location51among the high-frequency signals having passed through the gate wiring23passes through a part of the gate electrode14dand the gate electrode14aand reaches the portion52in the gate electrode14cas indicated by the arrow50a.The other branched signal passes through a part of the gate electrode14dand the gate electrode14band reaches the portion52in the gate electrode14cas indicated by an arrow50b.The portion52where the electrical length of the arrow50ais equal to the electrical length of the arrow50bis substantially the center of the gate electrode14c.Thus, the unit FET35can be effectively regarded as an FET in which two FETs, i.c., the first FET having the unit FET35aand a part of the unit FET35c, and the second FET having the unit FET35band a part of the unit FET35c,are connected in parallel. Compared with the second comparative example, the effective gate widths of the first FET and the second FET can be made closer to each other. Therefore, when a plurality of unit FETs35are arranged to design a high-frequency transistor, the design is facilitated. As described above, the semiconductor device100of the first embodiment can be downsized because of its easy design.

In the first embodiment, the drain electrode16does not surround the gate electrode14from the +direction (the direction opposite to the second direction) in the X direction. That is, the drain electrode16surrounds the gate electrode14only from the +direction in the Y direction, the −direction in the Y direction, and the −direction in the X direction. As described above, the drain electrode16may not be provided between the source electrode12and the gate bus bar24. This allows miniaturization.

InFIG.1, a portion54is a portion of the gate electrode14not surrounded by the drain electrode16in the +direction in the X direction. The width of the portion54in the Y direction is W1. The center point of the portion54in the Y direction is defined as a center point53. A range55is a range having a width W2which is ½ of the width W1of the portion54in the Y direction with the center point53as the center. In this case, the first end of the gate wiring23is connected within the range55. This makes it possible to make the effective gate widths of the two FETs, which are effectively connected in parallel, of the unit FETs35closer to each other. Therefore, when a plurality of unit FETs35are arranged to design a high-frequency transistor, the design is easier. The width W2of the range55may be one third or one fourth of the width W1.

The metal layer28is provided under the substrate10and is electrically connected to the source electrode12through a via hole20penetrating the substrate10. This allows the reference potential to be supplied to the source electrode12. When one via hole20is provided in the source electrode12, the effective gate width of the unit FET35per one via hole20can be increased. Therefore, the size of the device can be reduced.

The drain electrode16has regions surrounding the gate electrode14from the +direction and the −direction in the Y direction and from the −direction in the X direction, which are formed on the active region11. This allows the drain electrode16cto function as the drain electrode of the unit FET35c.Therefore, the size of the device can be reduced.

First Modification of First Embodiment

FIG.5is a plan view of a semiconductor device according to a first modification of the first embodiment. As illustrated inFIG.5, in a semiconductor device101of the first modification of the first embodiment, FET groups36aand36bare arranged in the X direction. The FET groups36aand36binclude a plurality of unit FETs35arranged in the Y direction. The unit FETs35adjacent in the Y direction share the drain electrode16. The FET groups36aand36bshare the drain bus bar26and are provided in mirror symmetry in the X direction with respect to the drain bus bar26. The gate electrodes14of the plurality of unit FETs35of the FET group36aare electrically connected to a gate bus bar24aand short-circuited. The gate electrodes14of the plurality of unit FETs35of the FET group36bare electrically connected to a gate bus bar24band short-circuited. The FET group36ais interposed between the gate bus bar24aand the drain bus bar26in the X direction, and the FET group36bis interposed between the gate bus bar24band the drain bus bar26in the X direction.

The gate bus bars24aand24band the drain bus bar26extend in the Y direction. A gate pad25and a drain pad27are provided so that the FET groups36aand36bare interposed therebetween in the Y direction. The gate bus bars24aand24bare electrically connected to the gate pad25at the −end in the Y direction and are short-circuited. The drain bus bar26is electrically connected to the drain pad27at the +end in the Y direction and is short-circuited. The number of unit FETs35each of the FET groups36aand36bmay be two, three, or five or more. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.

As in the first modification of the first embodiment, the FET group36a(first FET group) has a plurality of unit FETs35arranged in the Y direction, and the drain electrodes16of the adjacent unit FETs35are shared. The gate electrodes14of the plurality of unit FETs35of the FET group36aare electrically connected to the gate bus bar24a(first gate bus bar). The drain bus bar26is connected to the drain electrode16of the unit FET35of the FET group36a. The FET group36ais interposed between the drain bus bar26and the gate bus bar24a.With such a structure, the unit FETs35can be arranged in the Y direction, and the gate width of the semiconductor device101can be increased. Since the unit FETs35having substantially the same characteristics are arranged, the semiconductor device101having a large gate width can be easily designed.

The drain bus bar26is interposed between the FET groups36aand36b(second FET group). The FET group36bis interposed between the drain bus bar26and the gate bus bar24b(second gate bus bar). This makes it possible to arrange the unit FETs35in the Y direction, and to increase the gate width in the semiconductor device101. Since the unit FETs35having substantially the same characteristics are arranged, the semiconductor device101having a large gate width can be easily designed.

The gate pad25to which the gate bus bars24aand24bare connected and the drain pad27to which drain bus bar26is connected are provided so that the FET groups36aand36bare interposed therebetween. This allows the gate potential to be supplied from the gate pad25to the gate electrodes14of the FET groups36aand36bvia the gate bus bars24aand24b.A drain potential can be supplied from the drain pad27to the drain electrodes16of the FET groups36aand36bvia the drain bus bar26. In this way, the gate pad25and the drain pad27can be efficiently arranged, and hence the size of the semiconductor device can be reduced.

A current larger than the current of the drain electrode16shared by the unit FETs35adjacent in the Y direction flows through the drain bus bar26. By making the current density of the drain bus bar26and the current density of the drain electrode16shared by the unit FETs35adjacent in the Y direction substantially the same, the size can be reduced. Therefore, as illustrated inFIG.5, the width W3of the drain bus bar26in the X direction is set larger than the width W4of the drain electrode16in the Y direction, which is shared by the unit FETs35adjacent to each other in the Y direction. This makes it possible to bring the current density of the drain bus bar26close to the current density of the drain electrode16shared by the unit FETs35adjacent to each other in the Y direction. Therefore, the semiconductor device101can be downsized. The width W3can be 1.5 times or more, or twice or more, the width W4. In order to prevent the current density of the drain bus bar26from being too small, the width W3can be set to be10times or less of the width W4.

The width of the source electrode12in the X direction is, for example, 0.1 μm or more and 200 μm or less, and is, for example, 50 μm. The width of the source electrode12in the Y direction is, for example, 0.1 μm or more and 200 μm or less, and is 50 μm as an example. The gate electrode14has a gate length of, for example, 0.05 μm or more and 5 μm or less. The width W3of the drain bus bar26in the X direction is, for example, 10 μm or more and 200 μm or less, and is, for example, 50 μm. The width W4in the Y direction of the drain electrode16shared by the unit FETs35adjacent in the Y direction is, for example, 10 μm or more and 100μm or less, and is, for example,25μm. The width of the drain electrode16cin the X direction is 5 μm or more and 50 μm or less, for example, 12 μm. The distance between the gate electrode14dand the gate bus bars24aand24bin the X direction is, for example, 0.1 μm or more and 100 μm or less, and is, for example, 5 μm. The widths of the gate bus bars24aand24bin the X direction are, for example, 0.05 μm or more and 500 μm or less, and for example, 30 μm. The width of the gate wiring23in the Y direction is, for example, 0.05 μm or more and 500 μm or less, and is 1.0 μm as an example.

Second Modification of First Embodiment

FIG.6is a plan view of a semiconductor device according to a second modification of the first embodiment. As illustrated inFIG.6, in a semiconductor device102of the second modification of the first embodiment, a plurality of units34each having FET groups36aand36b,gate bus bars24aand24b,and drain bus bars26are arranged in the X direction. The gate pad25is provided for each unit34, and the drain pad27is provided for each unit34. The gate pads25of the plurality of units34may be provided in a connected manner. The drain pads27of the plurality of units34may be connected to each other. The number of units34may be two, three, or five or more. The other configurations are the same as those of the first modification of the first embodiment, and the description thereof is omitted.

By arranging the units34in the X direction as in the second modification of the first embodiment, a plurality of unit FETs35can be arranged efficiently. Therefore, the size of the device can be reduced.

SECOND EMBODIMENT

FIG.7is a plan view of a semiconductor device according to a second embodiment. As illustrated inFIG.7, in a semiconductor device103of the second embodiment, the drain electrode16includes a drain electrode16din addition to the drain electrodes16ato16c.The drain electrode16dis provided between the gate electrode14dand the gate bus bar24. The drain electrode16dis provided on the active region11. A unit FET35dincludes the source electrode12, the gate electrode14d,and the drain electrode16d.The drain electrode16dis divided into two in the Y direction. A region32where the drain electrode16dis not provided is provided between the divided drain electrodes16d.The region32extends in the X direction. The gate wiring23is provided in the region32and does not overlap the drain electrode16d. The gate wiring23is provided on the inactive region13. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.

According to the second embodiment, the drain electrode16surrounds the gate electrode14from the +direction in the X direction. This makes it possible to increase the effective gate width of the unit FET35sharing one source electrode12, as compared withFIG.1of the first embodiment. Therefore, the semiconductor device103can be further downsized. For the purpose of miniaturization, the width of the region32in the Y direction can be set to be equal to or less than ½ of the width of the gate electrode14din the Y direction.

As in the first embodiment, the first end of the gate wiring23is connected to only one portion of the gate electrode14. Thus, the unit FET35can be regarded as an FET in which the first FET and the second FET having substantially the same effective gate width are connected in parallel. Therefore, when a plurality of unit FETs35are arranged to design a high-frequency transistor, the design is facilitated. In addition, since the effective gate width can be made larger than that of the second comparative example, the size can be reduced.

In the second embodiment, the effective gate width of the FET extending from the portion51to the portion52through the gate electrode14ais substantially the same as that of the FET extending from the portion51to the portion52through the gate electrode14b, regardless of the position of the portion51where the gate wiring23is connected to the gate electrode14. Therefore, the design is easier.

First Modification of Second Embodiment

FIG.8is a plan view of a semiconductor device according to a first modification of the second embodiment. As illustrated inFIG.8, in a semiconductor device104of the first modification of the second embodiment, the width Wx of the source electrode12in the X direction is substantially equal to the width Wy in the Y direction. The source electrode12has a substantially square shape in plan view. This makes it possible to maximize the effective gate width of the unit FET35when the area of the planar shape of the source electrode12is the same. In addition, heat can be isotropically diffused. This improves the heat dissipation. The other configurations are the same as those of the second embodiment, and the description thereof is omitted.

From the viewpoint of increasing the effective gate width and the heat dissipation property, the width Wx can be set to be 3 times or less and 1/3  times or more, 2 times or less and 1/2 times or more, or 1.5 times or less and 1/1.5 times or more the width Wy. In the first embodiment and the modifications thereof, the width Wx can be set to be three times or less and one third or more times the width Wy, can be set to be two times or less and one half or more times the width Wy, or can be set to be 1.5 times or less and one 1.5 times or more times the width Wy.

Second Modification of Second Embodiment

FIG.9is a plan view of a semiconductor device according to a second modification of the second embodiment. As illustrated inFIG.9, in a semiconductor device105of the second modification of the second embodiment, the unit FET35is the unit FET35of the second embodiment. The number of unit FETs35each of the FET groups36aand36bmay be two, three, or five or more. The other configurations are the same as those of the first modification of the first embodiment, and the description thereof will be omitted.

As in the second modification of the second embodiment, the unit FETs35having the drain electrodes16dmay be arranged in the Y direction. This makes it possible to increase the gate width in the semiconductor device105. The width W3of the drain bus bar26in the X direction is larger than the width W4of the drain electrode16shared by the unit FETs35adjacent to each other in the Y direction. This allows a current larger than the current flowing through the drain electrode16of the unit FET35to flow through the drain bus bar26.

Third Modification of Second Embodiment

FIG.10is a plan view of a semiconductor device according to a third modification of the second embodiment. As illustrated inFIG.10, in a semiconductor device106of the third modification of the second embodiment, the unit FET35is the unit FET35of the second embodiment. The number of units34may be two, three, or five or more. The other configuration is the same as that of the second modification of the first embodiment, and the description thereof is omitted. As in the third modification of the second embodiment, the units34may be arranged in the X direction.

THIRD EMBODIMENT

FIG.11is a plan view of a semiconductor device according to a third embodiment. As illustrated inFIG.11, in a semiconductor device107, an insulating frame61made of ceramics or the like is mounted on a base60made of metal such as copper. An input terminal62and an output terminal63are provided on the frame61. Chips40and44and a semiconductor chip48are mounted on the base60. The semiconductor chip48is, for example, the semiconductor device102ofFIG.6of the second modification of the first embodiment or the semiconductor device106ofFIG.10of the third modification of the second embodiment. The chip40includes a dielectric layer41, a conductor pattern42provided on the dielectric layer41, and a conductor pattern (not illustrated) provided under the dielectric layer41. The chip44includes a dielectric layer45, a conductor pattern46provided on the dielectric layer45, and a conductor pattern (not illustrated) provided under the dielectric layer45. The conductor patterns42and46, the input terminal62, and the output terminal63are metal layers such as gold layers. The gate pad25and the drain pad27are provided on the semiconductor chip48. InFIG.11, the unit34and the like are not illustrated.

Bonding wires65electrically connect the input terminal62to the conductor pattern42. Bonding wires66electrically connect the conductor pattern42to the gate pad25. Bonding wire67electrically connect the drain pad27to the conductor pattern46. Bonding wires68electrically connect the conductor pattern46to the output terminal63.

The conductor pattern42sandwiching the dielectric layer41and the conductor pattern under the dielectric layer41function as a capacitor connected by shunt. The bonding wires65and66and the chip40form an input matching circuit. The conductor pattern46sandwiching the dielectric layer45and the conductor pattern under the dielectric layer45function as a capacitor connected by shunt. The bonding wires67and68and the chip44form an output matching circuit.

The high frequency signal input from the input terminal62is input to the semiconductor chip48via the chip40. The high frequency signal amplified in the semiconductor chip48is output from the output terminal63through the chip44. As illustrated inFIG.6of the second modification of the first embodiment andFIG.10of the third modification of the second embodiment, the gate pad25and the drain pad27are provided on the long side of the substrate10. Therefore, the bonding wires66and67can be easily bonded to the gate pad25and the drain pad27. As in the third embodiment, the semiconductor devices of the first and second embodiments and the modifications thereof may have a configuration in which a semiconductor chip is mounted on a package.

The embodiments disclosed herein are to be considered as illustrative in all respects and not restrictive. The scope of the present disclosure is not in the sense set forth above, but is indicated by the claims, and is intended to include all modifications within the meaning and scope of the claims and equivalents.