Semiconductor protection circuit, method for fabricating the same and method for operating semiconductor protection circuit

A protection circuit protects a semiconductor device provided on a semiconductor substrate and including an interconnect from charge entering the interconnect during fabrication of the semiconductor device. The protection circuit includes a first metal interconnect connected to the interconnect; a forward diode and a backward diode connected in parallel to the interconnect; an NMIS whose drain is connected to the output port of the forward diode, whose source is connected to the semiconductor substrate and whose gate is grounded through an upper metal interconnect; a PMIS whose drain is connected to the input port of the backward diode and whose source is connected to the semiconductor substrate; a first antenna connected to the gate of the NMIS; and a second antenna connected to the gate of the PMIS.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor protection circuit of a semiconductor device, and more particularly, it relates to a circuit for protecting a device from charge entering an interconnect such as a word line provided in a nonvolatile semiconductor memory, and a method for operating the same.

In accordance with recently increased degree of integration and reduced cost of a nonvolatile semiconductor memory, a MONOS (metal-oxide-nitride-oxide-silicon) memory technique in which a virtual ground type array is used and charge is locally trapped in an insulating film disposed beneath a gate electrode has been proposed.

In a MONOS memory, when a high (positive or negative) voltage is applied to a word line owing to charge generated during the fabrication, the threshold voltage of a memory cell is varied, and therefore, it is necessary to provide a circuit for protecting a word line or a charge trapping layer from the charge generated during the fabrication.

Now, a conventional semiconductor protection circuit will be described with reference to drawings.

First, a first conventional technique will be described (see U.S. Pat. Nos. 6,337,502 and 6,117,714). A conventional MONOS memory includes a plurality of memory cells arranged in the form of a matrix; word lines provided correspondingly to the rows of the memory cells and respectively connected to gate electrodes of MONOS structures included in the corresponding memory cells; bit lines provided correspondingly to the columns of the memory cells and respectively connected to impurity diffusion layers of the corresponding memory cells; an X decoder for driving the word lines; a Y decoder connected to the bit lines; and a sense amplifier for amplifying a signal read by the Y decoder. Each memory cell includes a P-type well formed in a P-type substrate; a charge trapping layer and a word line electrode successively formed on the P-type well in this order in the upward direction; N-type diffusion layers formed in the P-type well on both sides of the charge trapping layer; a word line formed above the word line electrode and made of a first layer metal interconnect; and a contact for connecting the word line electrode and the first layer metal interconnect. The bit line is connected to the N-type diffusion layer (i.e., the source or drain) of the memory cell.

FIG. 13is a circuit diagram of a conventional semiconductor protection circuit. It is noted that this drawing shows a state attained during the fabrication, and specifically, it shows a state of the conventional semiconductor protection circuit attained after forming a first layer metal interconnect1012. As shown inFIG. 13, the first layer metal interconnect1012for connecting a word line of a memory cell and an X decoder is connected to the drain of an N-channel MOS transistor1102(hereinafter referred to as the NMOS1102) disposed in a P-type well PW. The drain of the NMOS1102also functions as an N-type diffusion layer included in a backward diode1103. The source of the NMOS1102is grounded and the gate electrode thereof is connected to an antenna formed by using the first layer metal interconnect1012or the like.

FIG. 14is a cross-sectional view of the conventional semiconductor protection circuit ofFIG. 13. It is noted that this drawing shows a state thereof attained during the fabrication, and for example, it shows a state of the conventional semiconductor protection circuit attained during formation of a first layer metal interconnect1012. As shown inFIG. 14, the conventional semiconductor protection circuit includes a P-type well1003provided in a P-type semiconductor substrate1001; an isolation insulating film1005formed on the P-type well1003; a gate insulating film1008and a gate electrode1009bprovided on the P-type well1003; N-type diffusion layers1007including an N-type impurity and provided in the P-type well1003on both sides of the gate electrode1009b; and a P-type diffusion layer1006formed on the P-type well1003to be in contact with one N-type diffusion layer1007. A word line electrode1009aof a memory cell is connected to the first layer metal interconnect1012through a contact1011aand is connected to one N-type diffusion layer1007working as the drain of the NMOS1102through a contact1011b. Since the other N-type diffusion layer1007working as the source of the NMOS1102is connected to the P-type diffusion layer1006, it has the same potential as the P-type well1003, namely, the ground potential.

FIG. 15is a diagram for showing a method for protecting a memory cell from positive charge by the conventional semiconductor protection circuit. When positive charge enters the first layer metal interconnect1012, the drain voltage of the NMOS1102is increased in the positive direction. Simultaneously, since the potential of the antenna1104connected to the gate of the NMOS1102is also increased in the positive direction, the NMOS1102is turned on, and hence, the drain and the source of the NMOS1102are connected to each other. Accordingly, the positive charge transferred to the drain of the NMOS1102can be drained to the ground. Specifically, when the threshold voltage of the NMOS1102is approximately 1 V, the potential increase of the word line electrode1009acaused by positive charge can be suppressed to approximately 1 V.

FIG. 16is a diagram for showing a method for protecting a memory cell from negative charge by the conventional semiconductor protection circuit. When negative charge enters the first layer metal interconnect1012, the negative charge can be drained to the ground through the backward diode1103.

FIG. 17is a circuit diagram of the conventional semiconductor protection circuit obtained after completing the fabrication. The conventional semiconductor protection circuit is characterized by the gate electrode and the source of the NMOS1102being grounded.

FIG. 18is a cross-sectional view of the conventional semiconductor protection circuit ofFIG. 17obtained after completing the fabrication. The word line electrode1009ais connected to the first layer metal interconnect1012through the contact1011aand is further connected to a second layer metal interconnect1014through a first via1013ato be connected to the X decoder through the second layer metal interconnect1014a. The gate electrode1009bof the NMOS1102is connected to the first layer metal interconnect1012through a contact1011c, is further connected to a second layer metal interconnect1014bthrough a first via1013band is further connected to a third layer metal interconnect1016through a second via1015, so as to be grounded through the vias and the contact.

In this manner, as a characteristic of this conventional technique, while the metal interconnect connected to a word line is being processed, the gate electrode1009bis placed in a floating state connected to the antenna, and after completing the processing of the metal interconnect connected to a word line, the potential of the gate electrode1009bis suppressed to the ground potential.

In a data write operation, a voltage of, for example, approximately +9 V is applied to a word line of the semiconductor memory. At this point, the NMOS1102is in an off state because its gate electrode is grounded, and hence, the voltage of 9 V applied to the word line is never dropped. Also, since a reverse voltage is applied to the backward diode1103, no current passes, and hence, the applied voltage is never dropped by the conduction of the backward diode. Accordingly, the voltage of approximately +9 V can be applied to the word line of the memory cell1101.

In a data delete operation, a voltage of approximately 0 V (substantially equal to the ground potential) is applied to the word line of the memory cell1101. At this point, the NMOS1102is in an off state because its gate electrode is grounded, and hence, the voltage of 0 V applied to the word line is never changed. Also, since the same potential is applied to both ends of the backward diode1103, the voltage applied to the word line is never changed by the conduction of the backward diode1103. Accordingly, the voltage of approximately +0 V can be applied to the word line.

SUMMARY OF THE INVENTION

In the aforementioned conventional technique, however, negative potential cannot be applied to a word line of a memory cell. This is because when a negative voltage is applied to a word line of a memory cell, the negative voltage is drained to the ground through the backward diode.

The present invention was devised to overcome this conventional problem, and an object of the invention is realizing a semiconductor protection circuit having a high degree of freedom in a voltage that can be applied to a word line of a memory cell during an operation.

In order to achieve the object, the semiconductor protection circuit of this invention provided on a semiconductor substrate for protecting a semiconductor device including an interconnect from charge entering the interconnect during fabrication of the semiconductor device, includes a first metal interconnect connected to the interconnect and disposed on an upper layer than the interconnect; a forward diode having an input port connected to the interconnect; a backward diode that has an output port connected to the interconnect and is connected to the forward diode in parallel; an N-channel MIS transistor whose drain is connected to an output port of the forward diode, whose source is connected to the semiconductor substrate and whose gate electrode is grounded through a second metal interconnect disposed on an upper layer than the first metal interconnect; a P-channel MIS transistor whose drain is connected to an input port of the backward diode and whose source is connected to the semiconductor substrate; a first antenna connected to the gate electrode of the N-channel MIS transistor and disposed on the same interconnect layer as at least a part of the first metal interconnect; and a second antenna connected to a gate electrode of the P-channel MIS transistor and disposed on the same interconnect layer as at least a part of the first metal interconnect.

Owing to this structure, in the case where positive charge is generated during the fabrication of the semiconductor device, the positive charge can be drained to the ground (or the semiconductor substrate) through the forward diode and the N-channel MIS transistor, and in the case where negative charge is generated, the negative charge can be drained to the ground (or the semiconductor substrate) through the backward diode and the P-channel MIS transistor. Also, the interconnect of the semiconductor device can be driven in a wide voltage range from a positive voltage to a negative voltage by controlling a voltage to be applied to each constructing member by using a control circuit or the like. Accordingly, the semiconductor protection circuit of this embodiment is useful as a protection circuit of a semiconductor memory having an interconnect on which a voltage is large varied, such as a MONOS memory.

The semiconductor protection circuit of this invention may further include a third antenna connected to a second N-type well, so as to more effectively collect charge to be drained to the ground.

Furthermore, when a plurality of forward diodes are connected to a common N-channel MIS transistor and a plurality of backward diodes are connected to a common P-channel MIS transistor, the area of the semiconductor protection circuit can be reduced.

The method of this invention for fabricating a semiconductor protection circuit provided on a P-type semiconductor substrate for protecting a semiconductor device including an interconnect from charge entering the interconnect during fabrication of the semiconductor device, includes the steps of (a) forming a deep N-type well in the semiconductor substrate and successively forming a first P-type well, a second P-type well, a first N-type well and a second N-type well in the deep N-type well; (b) forming a forward diode in the first N-type well, forming a backward diode in the first P-type well, forming an N-channel MIS transistor on the second P-type well and forming a P-channel MIS transistor on the second N-type well; (c) forming, above the semiconductor substrate, a first layer metal interconnect including a first metal interconnect for mutually connecting the interconnect, an input port of the forward diode and an output port of the backward diode, a second metal interconnect for connecting a drain of the N-channel MIS transistor and an output port of the forward diode, a third metal interconnect for connecting a source of the N-channel MIS transistor to the semiconductor substrate, a fourth metal interconnect for connecting an input port of the backward diode and a drain of the P-channel MIS transistor and a fifth metal interconnect for connecting a source of the P-channel MIS transistor to the semiconductor substrate; a first antenna connected to a gate electrode of the N-channel MIS transistor and a second antenna connected to a gate electrode of the P-channel MIS transistor; and (d) forming, above the first layer metal interconnect, an upper layer metal interconnect including a sixth metal interconnect for grounding the gate electrode of the N-channel MIS transistor, a seventh metal interconnect for connecting the drain of the N-channel MIS transistor, the gate electrode of the P-channel MIS transistor and the second N-type well to a first control circuit, and an eighth metal interconnect for connecting the drain of the P-channel MIS transistor and the input port of the backward diode to a second control circuit.

According to this method, positive charge and negative charge generated during the fabrication of the semiconductor device fabricated in parallel to the semiconductor protection circuit can be drained to the ground. In addition, when the semiconductor device is driven after completing the fabrication, it can be controlled so that any current can flow from the interconnect to neither the forward diode nor the backward diode, and hence, any voltage in a wide voltage range from a positive voltage to a negative voltage can be applied to the interconnect.

In the method for operating a semiconductor protection circuit of this invention, the semiconductor protection circuit includes a first metal interconnect that is connected to an interconnect included in a semiconductor device provided on a semiconductor substrate and is disposed on an upper layer than the interconnect; a forward diode having an input port connected to the interconnect; a backward diode that has an output port connected to the interconnect and is connected to the forward diode in parallel; an N-channel MIS transistor whose drain is connected to an output port of the forward diode, whose source is connected to the semiconductor substrate and whose gate electrode is grounded through a second metal interconnect disposed on an upper layer than the first metal interconnect; a P-channel MIS transistor whose drain is connected to an input port of the backward diode and whose source is connected to the semiconductor substrate; a first antenna connected to the gate electrode of the N-channel MIS transistor and disposed on the same interconnect layer as at least a part of the first metal interconnect; a second antenna connected to a gate electrode of the P-channel MIS transistor and disposed on the same interconnect layer as at least a part of the first metal interconnect; a first control circuit for controlling potential of the drain of the N-channel MIS transistor, the gate electrode of the P-channel MIS transistor and the second N-type well; and a second control circuit connected to the drain of the P-channel MIS transistor and the input port of the backward diode, and in the case where positive charge enters the first metal interconnect before grounding the gate electrode of the N-channel MIS transistor and before connecting the gate electrode of the P-channel MIS transistor to the first control circuit, the positive charge is transferred to ground through the forward diode and the N-channel MIS transistor.

As described above, in the semiconductor protection circuit of the present invention, positive charge generated during the fabrication of the semiconductor device is drained to the ground through the forward diode and the NMOS. Also, negative charge generated during the fabrication is drained to the ground through the backward diode and the PMOS. Furthermore, when the semiconductor device is driven after completing the fabrication, a voltage in a wide range from a positive voltage to a negative voltage can be applied to a word line by controlling voltages in wells where the forward diode and the backward diode are disposed. Specifically, the semiconductor protection circuit of this invention is applicable also to a semiconductor memory where a negative voltage is used in the operation.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a cross-sectional view of a memory cell of a MONOS semiconductor memory according to Embodiment 1 of the invention, andFIG. 2is a circuit diagram of a memory cell array of the semiconductor memory of this embodiment. Also,FIG. 3is a circuit diagram for schematically showing a semiconductor protection circuit of the semiconductor memory of this embodiment in a state attained during the fabrication.

As shown inFIG. 2the semiconductor memory of this embodiment includes a plurality of memory cells101arranged in the form of a matrix; word lines51provided correspondingly to respective rows of the memory cells101to be connected to gate electrodes of MONOS structures of the memory cells101; bit lines50provided correspondingly to respective columns to be connected to N-type diffusion layers7of the memory cells101; an X decoder54for driving the word lines51; a Y decoder56connected to the respective bit lines50; a sense amplifier58for amplifying a signal read by the Y decoder56; and a semiconductor protection circuit52provided between the X decoder54and the word lines51.

Furthermore, as shown inFIG. 1, each memory cell101includes a p-type well3formed on, for example, a P-type semiconductor substrate1; an isolation insulating film (STI)5surrounding a semiconductor forming region of the P-type well3; a charge trapping layer99and a word line electrode9asuccessively formed on the P-type well3in this order in the upward direction; N-type diffusion layers7formed in the P-type well3on both sides of the charge trapping layer99; a word line51(seeFIG. 2) formed above the word line electrode9aand made of a first layer metal interconnect (M1)12; and a contact11for connecting the word line electrode9aand the first layer metal interconnect12. Each bit line is connected to N-type diffusion layers (corresponding to sources or drains) of the memory cells101disposed in two columns.

The aforementioned structures of the memory cell array and the memory cell101are the same as those of a general MONOS memory, from which the semiconductor memory of this embodiment is different in the structure of the semiconductor protection circuit.

As shown inFIG. 3, in the state of the semiconductor memory of this embodiment attained when the first layer metal interconnect12is formed, the semiconductor protection circuit includes a deep N-type well2formed in the P-type substrate1; P-type wells PW1, PW2and PW3and N-type wells NW1, NW2and NW3formed in the P-type substrate1or in the deep N-type well2; an N-channel MIS transistor (hereinafter referred to as the NMIS)204provided on the P-type well PW2(corresponding to a second P-type well) and having the source grounded (namely, connected to the P-type substrate1); a forward diode202provided within the N-type well NW2(corresponding to a first N-type well) having an input port connected to the word line51through the first layer metal interconnect12and an output port connected to the drain of the NMIS204; a P-channel MIS transistor (hereinafter referred to as the PMIS)205provided on the N-type well NW3(corresponding to a second N-type well) and having the source grounded (namely, connected to the P-type substrate1); and a backward diode203provided within the P-type well PW3(corresponding to a first P-type well) and having an output port connected to the word line51through the first layer metal interconnect12and an input port connected to the drain of the PMIS205. The gate electrode of the NMIS204is connected to an NMIS gate antenna (corresponding to a first antenna)206made of a part of the first layer metal interconnect, and the gate electrode of the PMIS205is connected to a PMIS gate antenna (corresponding to a second antenna)207made of a part of the first layer metal interconnect. The NMIS gate antenna206and the PMIS gate antenna207are made of the same material as the metal interconnect and have substantially the same shape as a general metal interconnect.

FIG. 4is a schematic cross-sectional view of the semiconductor protection circuit according to Embodiment 1 of the invention shown inFIG. 3.FIG. 4shows a state attained during the fabrication and shows the semiconductor protection circuit in the state attained, for example, immediately after forming the first layer metal interconnect12.

As shown inFIG. 4, the deep N-type well2is formed in the P-type semiconductor substrate1, and the P-type wells PW2and PW3and the N-type wells NW1, NW2and NW3are disposed in the deep N-type well2. A P-type diffusion layer6cconstructing the forward diode202together with the N-type well NW2is disposed in a surface portion of the N-type well NW2, and an N-type diffusion layer7aof the NMIS204is disposed in a surface portion of the P-type well PW2. Also, an N-type diffusion layer7cconstructing the backward diode203together with the P-type well PW3is disposed in a surface portion of the P-type well PW3, and a P-type diffusion layer of the PMIS205is disposed in a surface portion of the N-type well NW3.

The word line electrode9aof the memory cell101is connected to the first layer metal interconnect12through a contact11and is further connected to the P-type diffusion layer6cincluded in the forward diode202through a contact11. The N-type diffusion layer7adisposed in the N-type well NW2and one of the N-type diffusion layers7aworking as the drain of the NMIS204an connected to each other through a contact11and the first layer metal interconnect12. The potential of the other N-type diffusion layer7bworking the source of the NMIS204is fixed to the ground potential through the P-type diffusion layer6adisposed in the P-type well PW1. It is noted that the P-type diffusion layer B disposed in the P-type well PW2is also connected to the P-type diffusion layer6adisposed in the P-type well PW1through a contact11and the potential of the P-type well PW2is fixed to the ground potential.

Furthermore, the word line electrode9aof the memory cell101is connected to the first layer metal interconnect12through the contact11and is further connected to the N-type diffusion layer7cincluded in the backward diode203through a contact11, and the P-type diffusion layer6bdisposed in the P-type well PW3where the backward diode203is disposed and a P-type diffusion layer6aworking the drain of the PMIS205at connected to each other through a contact11and the first layer metal interconnect12. The potential of one P-type diffusion layer6eworking as the source of the PMIS205is fixed to the ground potential through a P-type diffusion layer6fdisposed in the P-type well PW4.

In general, charge in the positive direction or the negative direction is generated through various processes such as plasma etching process employed for forming an interconnect, film formation process for growing a silicon oxide film or the like by plasma CVD and cleaning process such as scrubber cleaning.

Now, a protection method from charge performed by the semiconductor protection circuit of this embodiment will be described.

FIG. 5is a diagram for showing the flow of positive charge in the semiconductor protection circuit of this embodiment. When positive charge enters the first layer metal interconnect12, the drain voltage of the NMIS204is increased in the positive direction through the forward diode202. Simultaneously, since the potential of the NMIS gate antenna206connected to a gate electrode9b(seeFIG. 4) of the NMIS204is also increased in the positive direction, the NMIS204is turned on, and hence, the drain and the source of the NMIS204are connected to each other. Accordingly, the positive charge transferred to the drain of the NMIS204can be drained to the ground. Specifically, when the threshold voltage of the NMIS204is approximately 1 V, the potential increase of the word line electrode9acaused by the positive charge can be suppressed to approximately 1 V.

FIG. 6is a diagram for showing the flow of negative charge in the semiconductor protection circuit of this embodiment. When negative charge enters the first layer metal interconnect12, the drain voltage of the PMIS205is dropped in the negative direction through the backward diode203. Simultaneously, since the potential of the PMIS gate antenna207connected to a gate electrode9cof the PMIS205is also dropped in the negative direction, the PMIS205is turned on, and hence, the drain and the source of the PMIS205are connected to each other. Accordingly, the negative charge transferred to the drain of the PMIS205can be drained to the ground. Specifically, when the threshold voltage of the PMIS205is approximately −1 V, the potential drop of the word line electrode9acaused by the negative charge can be suppressed to approximately −1 V.

Next, a state of the semiconductor protection circuit of this embodiment attained after completing the fabrication will be described.

FIG. 7is a circuit diagram for schematically showing the state of the semiconductor protection circuit of this embodiment attained after completing the fabrication. As shown inFIG. 7, the gate electrode and the source of the NMIS204are connected to the ground potential, and the gate electrode9cof the PMIS205is electrically connected to the N-type well NW3.

FIG. 8is a cross-sectional view of the semiconductor protection circuit of this embodiment obtained after completing the fabrication as shown inFIG. 7.

As shown inFIG. 8, the word line electrode9ais connected to the first layer metal interconnect12through the contact11and is further connected to a second layer metal interconnect14through a first via13and is connected to the X decoder54through the second layer metal interconnect14.

The gate electrode9bof the NMIS204is connected to the second layer metal interconnect14successively through the contact11, the first layer metal interconnect12and the first via13, and is grounded through a second via15and a third layer metal interconnect16. In this manner, as a characteristic of this embodiment, the gate electrode9bof the NMIS204of the semiconductor protection circuit is placed in a floating state connected to the antenna while processing the metal interconnect connected to the word line of the memory cell101, and is grounded after completing the processing of the metal interconnect connected to the word line of the memory cell101. It is noted that the gate electrode9bof the NMIS204may be grounded through a metal interconnect disposed on an upper layer than the third layer.

Also, the gate electrode9cof the PMIS205is connected to the second layer metal interconnect14successively through the contact11, the first layer metal interconnect12and the first via13, and is further connected to a V-NW control circuit (corresponding to a first control circuit)112through the second via15and the third layer metal interconnect16. In this manner, as a characteristic of this embodiment, the gate electrode9cof the PMIS205of the semiconductor protection circuit is placed in a floating state connected to the antenna while processing the metal interconnect connected to the word line of the memory cell and is connected to the V-NW control circuit112after completing the processing of the metal interconnect connected to the word line of the memory cell101. It is noted that the gate electrode9cof the PMIS205may be provided with a voltage the same as that applied to the N-type well NW3by the V-NW control circuit112or may be connected to the N-type well NW3through a metal interconnect disposed on an upper layer than the third layer.

Furthermore, the potential of the P-type well PW3is controlled by a V-PW control circuit (corresponding to a second control circuit)110, and the potential of the N-type wells NW1, NW2and NW3and the deep N-type well2is controlled by the V-NW control circuit112.

FIG. 9is a circuit diagram for schematically showing an operation of the semiconductor protection circuit of this embodiment performed in a data write operation of the semiconductor memory. As shown inFIG. 9, in a data write operation, a voltage of approximately +9 V is applied to the word line of a selected memory cell101and a voltage of approximately +0 V is applied to the word lines of unselected memory cells101. At this point, the potential of the N-type wells NW1, NW2and NW3and the deep N-type well2should be set to a high voltage of +9 V or more so that no current can pass the forward diode202. Also, the potential of the P-type well PW3should be set to a low voltage of 0 V or less so that no current can pass the backward diode203.

Specifically, the potential of the N-type wells NW1, NW2and NW3and the deep N-type well2is controlled to be +9 V by the V-NW control circuit112, and the potential of the P-type well PW3is controlled to be 0 V by the V-PW control circuit110. Accordingly, neither the forward diode202nor the backward diode203is conductive, and hence, a voltage of approximately +9 V is applied to the word line of the selected memory cell101. In the case where the semiconductor protection circuit of this embodiment is used in a MONOS memory, in order to write data, the potential of the P-type well PW3should be 0 V or less and the potential of the N-type wells NW1, NW2and NW3and the deep N-type well2should be not less than a writing voltage (9 V).

FIG. 10is a circuit diagram for schematically showing an operation of the semiconductor protection circuit of this embodiment performed in a data delete operation of the semiconductor memory. In a data delete operation, a voltage of approximately −7 V is applied to the word line of a selected memory cell101, and a voltage of approximately +0 V is applied to the word lines of unselected memory cells101. At this point, the potential of the N-type wells NW1, NW2and NW3and the deep N-type well2should be set to a high voltage of +0 V or more so that no current can pass the forward diode202. Also, the potential of the P-type well PW3should be set to a low voltage of −7 V or less so that no current can pass the backward diode203.

Specifically, the potential of the N-type wells NW1, NW2and NW3and the deep N-type well2is controlled to be 0 V by the V-NW control circuit112, and the potential of the P-type well PW3is controlled to be −7 V by the V-PW control circuit110. Accordingly, neither the forward diode202nor the backward diode203is conductive, and hence, a voltage of approximately −7 V is applied to the word line of the selected memory cell101. In the case where the semiconductor protection circuit of this embodiment is used in a MONOS memory, in order to delete data, the potential of the P-type well PW3should be not more than a deleting voltage (−7 V) and the potential of the N-type wells NW1, NW2and NW3and the deep N-type well2should be 0 V or more.

FIG. 11is a plan view for schematically showing exemplified layout of the semiconductor protection circuit of this embodiment.

As shown inFIG. 11, a deep N-type well2is provided adjacent to one end of each of a plurality of word line electrodes9adisposed in parallel to one another. In this deep N-type well2, a P-type well PW3(a p-type well3) and an N-type well NW2(an N-type well4) are provided. In the P-type well PW3, N-type diffusion layers7included in backward diodes203are arranged in number equal to the number of the word line electrodes9a, and in the N-type well NW2, P-type diffusion layers6included in forward diodes202are arranged in number equal to the number of the word line electrodes9a. One word line electrode9a, one N-type diffusion layer7and one P-type diffusion layer6are mutually connected through a first layer metal interconnect12. Since an NMIS204and a PMIS205can share the backward diode203and the forward diode202, the semiconductor protection circuit of this embodiment can be very compact, and the circuit area of the semiconductor memory including the memory cell array is minimally increased by this semiconductor protection circuit.

In this manner, according to the semiconductor protection circuit of this embodiment, a high voltage can be effectively prevented from being applied to a memory cell array of a semiconductor memory by charge generated in, for example, interconnect formation process during the fabrication, and after completing the fabrication, word lines can be driven in a wide voltage range from a positive voltage to a negative voltage. Therefore, when the semiconductor protection circuit of this embodiment is employed, it is possible to realize a nonvolatile semiconductor memory, such as a MONOS memory, that can perform write and delete operations in a wide voltage range while suppressing variation of the threshold voltage of memory cells of the semiconductor memory.

It is noted that the semiconductor protection circuit of this embodiment can be fabricated by general semiconductor process through processing partially common to the semiconductor memory. Specifically, a deep N-type well2is formed by implanting an N-type impurity into a P-type semiconductor substrate1(seeFIGS. 7 and 8). Next, after forming N-type wells NW1, NW2and NW3in the deep N-type well2, P-type wells PW2and PW3are formed in the deep N-type well2. Then, an N-channel MIS transistor204is formed on the P-type well PW2, and a P-channel MIS transistor205is formed on the N-type well NW3. Simultaneously, a forward diode202is formed in the N-type well NW2and a backward diode203is formed in the P-type well PW3. Thereafter, metal interconnects are formed by known wiring technique.

Although the semiconductor protection circuit is used in the MONOS memory in this embodiment, the semiconductor protection circuit of this embodiment is suitably used in any semiconductor memory where interconnects are driven by negative and positive voltages, such as a flash memory. Also, the layout and the driving voltages of the semiconductor protection circuit are not limited to those described in this embodiment.

FIG. 12is a circuit diagram of a semiconductor protection circuit according to Embodiment 2 of the invention.FIG. 12shows a state of the semiconductor protection circuit attained, for example, during formation of a first layer metal interconnect.

The semiconductor protection circuit of this embodiment includes, in addition to the structure of the semiconductor protection circuit of Embodiment 1 shown inFIG. 4, a third antenna208connected to an N-type well. The third antenna208is made of an interconnect disposed on the same interconnect layer as an NMIS gate antenna206and a PMIS gate antenna207(for example, made of the first layer metal interconnect).

Owing to this structure, charge generated in forming interconnects enters a node between a forward diode202and the drain of an NMIS204from the third antenna208. Accordingly, in the case where positive charge enters the third antenna208during the fabrication, the positive charge is drained to the ground through an NMIS204. Thus, a larger quantity of positive charge can be drained to the ground than in the semiconductor protection circuit of Embodiment 1.

Furthermore, owing to this structure, in the case where negative charge enters a first layer metal interconnect12and similarly enters the antenna207, the negative charge entering from the first layer metal interconnect12is drained from a PMIS205. At this point, if the potential of an N-type well NW3where the PMIS205is disposed is a positive voltage, the threshold voltage of the PMIS205is shifted in the negative direction, so as to degrade the charge removing performance. In order to prevent this degradation, the potential of the N-type well NW3is fixed to the ground potential, namely, as in this embodiment, the antenna208is connected to the N-type well NW3so that the potential of the N-type well NW3can be fixed to the ground potential when negative charge enters the antenna208.

Specifically, when negative charge enters the N-type well NW3, the potential of the N-type well NW3and a deep N-type well NW is dropped in the negative direction. However, the deep N-type well NW and a P-type substrate together form a diode, and hence, when the dropped negative potential is lowered to some extent, forward bias is formed between the P-type substrate and the deep N-type well NW, resulting in ultimately attaining the ground potential.

Furthermore, in the case where negative charge enters from the third antenna208, the negative charge flows to the P-type substrate (ground potential) through the deep N-type well NW.

It is noted that the semiconductor protection circuit of this embodiment can be driven in the same manner as the semiconductor protection circuit of Embodiment 1 because the third antenna208is connected ultimately to a V-NW control circuit112(seeFIG. 7).

As described so far, the semiconductor protection circuit of the present invention is used in a semiconductor device in which interconnects are driven by voltages changed from a positive voltage to a negative voltage, and in particular, it is useful as a word line protection circuit of a nonvolatile semiconductor memory in which a non-conductive charge trapping layer is used as a memory device.