One time programmable memory cell capable of reducing leakage current and preventing slow bit response

The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a one time programmable (OTP) memory cell, and more particularly, to a one time programmable memory cell capable of reducing current leakage.

2. Description of the Prior Art

Non-volatile memory (NVM) is a type of memory that retains information it stores even when no power is supplied to memory blocks thereof. Some examples include magnetic devices, optical discs, flash memory, and other semiconductor-based memory topologies. According to the programming times limit, non-volatile memory devices are divided into multi-time programmable (MTP) memory and one-time programmable (OTP) memory. As shown inFIG. 1, a conventional OTP memory cell100comprises a transistor110and an antifuse transistor120. When programming the OTP memory cell100, the antifuse transistor120is ruptured and behaves as a MOS capacitor, such that data of logic “1” is written into the OTP memory100.

Please refer toFIG. 2andFIG. 3together.FIG. 2is a diagram showing a good rupture status of the OTP memory cell ofFIG. 1after programming.FIG. 3is a diagram showing a bad rupture status of the OTP memory cell ofFIG. 1after programming. As showing inFIG. 2, when a gate oxide layer Ox corresponding to a gate terminal G of the antifuse transistor120is ruptured near a source terminal S of the antifuse transistor120, leakage current between the gate terminal G and the source terminal S is smaller. As showing inFIG. 3, when the gate oxide layer Ox corresponding to the gate terminal G of the antifuse transistor is ruptured near a channel area of the antifuse transistor120, leakage current between the gate terminal G and the source terminal S is larger, since more current can escape through the channel area.

However, in the prior art, it is difficult to control rupture position of the gate oxide layer Ox, such that the OTP memory cell100of the prior art may work incorrectly or has slow bit response due to insufficient power caused by the leakage current.

SUMMARY OF THE INVENTION

The present invention provides a one time programmable (OTP) memory cell comprising a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.

The present invention further provides another one time programmable (OTP) memory cell, comprising a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor, having a third gate terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled to the third source terminal. Wherein a part of the third gate terminal is formed right above a shallow trench insulation, and rest of the third gate terminal is formed right above the third source/drain extension area.

DETAILED DESCRIPTION

Please refer toFIG. 4andFIG. 5together.FIG. 4is a diagram showing an equivalent circuit of a one time programmable (OTP) memory cell of the present invention.FIG. 5is a diagram showing a structure of the OTP memory cell according to a first embodiment of the present invention. As shown in the figures, the OPT memory cell200comprises a select gate transistor210, a following gate transistor220and an antifuse varactor230.

The select gate transistor210has a first gate terminal G1, a first drain terminal D1, a first source terminal S1, and two first source/drain extension areas E1respectively coupled to the first drain terminal D1and the first source terminal S1. The following gate transistor220has a second gate terminal G2, a second drain terminal D2, a second source terminal S2coupled to the first drain terminal D1, and two second source/drain extension areas E2respectively coupled to the second drain terminal D2and the second source terminal S2. The antifuse varactor230can be a MOS varactor, and has a third gate terminal G3, a third drain terminal D3, a third source terminal S3coupled to the second drain terminal D2, and a third source/drain extension area E3coupled with the third drain terminal D3and the third source terminal S3for shorting the third drain terminal D3and the third source terminal S3.

According to the above arrangement, since the third gate terminal G3is formed right above the third source/drain extension area E3, and horizontal edges of the third gate terminal G3are within horizontal edges of the third source/drain extension area E3, thus the antifuse varactor230has no channel. Therefore, when programming the OTP memory cell200, the gate oxide layer Ox3of the antifuse varactor230is ensured to be ruptured on the third source/drain extension area E3, so as to reduce possibility of current escaping through the channel. As a result, the OTP memory cell200of the present invention is capable of reducing leakage current, such that problems of slow bit response or malfunction can be prevented. Moreover, the series-connected following gate transistor220can reduce junction leakage in a program inhibition status.

In addition, each of the first source/drain extension areas E1has a first depth, and each of the second and third source/drain extension areas E2, E3has a second depth deeper than the first depth. For example, the first source/drain extension areas E1can be source/drain extension areas for core devices, and the second and third source/drain extension areas E2, E3can be source/drain extension areas for I/O devices, such that PN junction breakdown of the following gate transistor220can be prevented. Furthermore, the second source/drain extension area E2can be asymmetric thus drain side extension is deeper than source side extension. For example, the second source extension of following gate transistor can be depth of core device and second drain extension can be depth of I/O device separately. Besides, gate oxide layers Ox1-Ox3of the first to third gate terminals G1-G3are for core devices, thus the gate oxide layers Ox1-Ox3of the first to third gate terminals G1-G3are thinner than gate oxide layers for I/O devices.

Please refer toFIG. 6.FIG. 6is a diagram showing a structure of the OTP memory cell according to a second embodiment of the present invention. Most features of the OTP memory cell200A are identical to the OTP memory cell200ofFIG. 5. As shown inFIG. 6, different from the OTP memory cell200ofFIG. 5all forming on a P well, the OTP memory cell200A ofFIG. 6has the select gate transistor210and the following gate transistor220forming on a P well, and the antifuse varactor230forming on an N well. In addition, in the embodiment ofFIG. 6, the third source/drain extension area E3is not necessary, that is, the third source/drain extension area E3can either exist, or be removed and replaced by the N well.

Please refer toFIG. 7.FIG. 7is a diagram showing a structure of the OTP memory cell according to a third embodiment of the present invention. Most features of the OTP memory cell200B are identical to the OTP memory cell200A ofFIG. 6. As shown inFIG. 7, different from the OTP memory cell200A ofFIG. 6having gate oxide layers Ox1-Ox3with a same thickness, the OTP memory cell200B ofFIG. 7has the gate oxide layers Ox1, Ox2of the select gate transistor210and the following gate transistor220with a larger thickness, and the gate oxide layer Ox3of the antifuse varactor230with a smaller thickness. For example, the gate oxide layers Ox1, Ox2of the select gate transistor210and the following gate transistor220are for I/O devices, and the gate oxide layer Ox3of the antifuse varactor230is for core devices. Besides, the first source/drain extension areas E1are formed as deep as the second and third source/drain extension areas E2, E3, that is, the first source/drain extension areas E1can also be source/drain extension areas for I/O devices.

Please refer toFIG. 8.FIG. 8is a diagram showing a structure of the OTP memory cell according to a fourth embodiment of the present invention. The select gate transistor210and the following gate transistor220are identical to those ofFIG. 5. As shown inFIG. 8, different from the antifuse varactor230ofFIG. 5, the drain terminal of the antifuse varactor230′ is replaced by a shallow trench insulation area STI, such that a part of the third gate terminal G3is formed right above the shallow trench insulation area STI, and rest of the third gate terminal G3is formed right above the third source/drain extension area E3. According to the above arrangement, the antifuse varactor230′ has no channel, therefore, when programming the OTP memory cell200C, the gate oxide layer Ox3of the antifuse varactor230′ is ensured to be ruptured on the third source/drain extension area E3, which is close to the third source terminal S3, so as to reduce possibility of current escaping through the channel.

Please refer toFIG. 9.FIG. 9is a diagram showing a structure of the OTP memory cell according to a fifth embodiment of the present invention. Most features of the OTP memory cell200D are identical to the OTP memory cell200C ofFIG. 8. As shown inFIG. 9, different from the OTP memory cell200C ofFIG. 8all forming on a P well, the OTP memory cell200D ofFIG. 9has the select gate transistor210and the following gate transistor220forming on a P well, and the antifuse varactor230′ forming on an N well. In addition, in the embodiment ofFIG. 9, the third source/drain extension area E3is not necessary, that is, the third source/drain extension area E3can either exist, or be removed and replaced by the N well.

Please refer toFIG. 10.FIG. 10is a diagram showing a structure of the OTP memory cell according to a sixth embodiment of the present invention. Most features of the OTP memory cell200E are identical to the OTP memory cell200D ofFIG. 9. As shown inFIG. 10, different from the OTP memory cell200D ofFIG. 9having gate oxide layers Ox1-Ox3with a same thickness, the OTP memory cell ofFIG. 10has the gate oxide layers Ox1, OX2of the select gate transistor210and the following gate transistor220with a larger thickness, and the gate oxide layer Ox3of the antifuse varactor230′ with a smaller thickness. For example, the gate oxide layers Ox1, OX2of the select gate transistor210and the following gate transistor220are for I/O devices, and the gate oxide layer Ox3of the antifuse varactor230′ is for core devices. Besides, the first source/drain extension areas E1are formed as deep as the second and third source/drain extension areas E2, E3, that is, the first source/drain extension areas E1can also be source/drain extension areas for I/O devices.

In the above embodiments, the first drain terminal D1and the second source terminal S2are integrated as a single terminal, and the second drain terminal D2and the third source terminal S3are also integrated as a single terminal, but in other embodiments of the present invention, the first drain terminal D1, the second source terminal S2, the second drain terminal D2, and the third source terminal S3cab be separated from each other as independent terminals.

Please refer toFIG. 11.FIG. 11is a diagram showing a method for programming a memory array comprising the OTP memory cells of the present invention. As shown inFIG. 11, when programming the memory array300comprising a plurality of OTP memory cells200,200′ of the present invention, a first voltage V1(such as 1.2V) is provided to the first gate terminals of the OTP memory cells at a selected row, a second voltage V2(such as 4V) is provided to all of the second gate terminals of the memory array300, and a third voltage V3(such as 6V) is provided to the third gate terminals of the selected memory cell200′. Besides, a ground voltage Vg (such as 0V) is provided to the first source terminals of a selected column via a bit line BL.

According to the above arrangement, the antifuse varactor230of the selected memory cell200′ can be ruptured to be a resistor by the third voltage V3, such that data of logic “1” is written into the selected OTP memory cell200′ at the selected row and selected column. On the other hand, for writing data of logic “0” into the selected OTP memory cell200′ at the selected row and column, the voltage level at the third gate terminal can be set at 0V.

In addition, inFIG. 11, for the unselected OTP memory cell200at the unselected row and selected column, the ground voltage Vg is provided to the first and third gate terminals of the unselected row; for the unselected OTP memory cell200at the selected row and unselected column, the first voltage V1is provided to the first source terminal of the OTP memory cell at the unselected column; and for the unselected OTP memory cells200at the unselected row and unselected column, the ground voltage Vg is provided to the first and third gate terminals of the OTP memory cell, and the first voltage V1is provided to the first source terminals of the OTP memory cell. Therefore, the unselected OTP memory cells200at the unselected row and/or unselected column can be set in a program inhibition status.

Please refer toFIG. 12.FIG. 12is a diagram showing a method for reading a memory array300comprising the OTP memory cells of the present invention. As shown inFIG. 12, when reading data from the memory array300, a first voltage V1(such as 1.2V) is provided to the first and third gate terminals of the OTP memory cells at the selected row, and the first voltage V1is also provided to all of the second gate terminals of the memory array300. Besides, a ground voltage Vg (such as 0V) is provided to the first source terminals of the OTP memory cells at a selected column.

According to the above arrangement, data stored in a selected OTP memory cell200′ at the selected row and column can be read via a bit line BL coupled to the first source terminals of the selected column.

In addition, inFIG. 12, for the unselected OTP memory cell200at the unselected row and selected column, the ground voltage Vg is provided to the first and third gate terminals of the OTP memory cells at the unselected row; for the unselected OTP memory cell200at the selected row and unselected column, the first voltage V1is provided to the first source terminal of the OTP memory cell at the unselected column; and for the unselected OTP memory cell200at the unselected row and unselected column, the ground voltage Vg is provided to the first and third gate terminals of the OTP memory cell, and the first voltage V1is provided to the first source terminal of the OTP memory cell. Therefore, the unselected OTP memory cells200at the unselected row and/or unselected column can be set in a read inhibition status.

In the embodiment ofFIG. 12, the OTP memory cell200,200′ is illustrated by the OTP memory cell having the select gate transistor and the following gate transistor with oxide layers for core devices, however, the OTP memory cells200,200′ ofFIG. 12can also be replaced by the OTP memory cell having the select gate transistor and the following gate transistor with oxide layers for I/O devices, in that case, the first voltage V1can be set higher (such as 2.5V).

Since the antifuse varactor230the OTP memory cell200has no channel, the memory array comprising the OTP memory cells of the present invention is able to perform a reverse read operation according to an operation bias condition different from the embodiment ofFIG. 12. For example, please refer toFIG. 13.FIG. 13is a diagram showing another method for reading a memory array comprising the OTP memory cells of the present invention. As shown inFIG. 13, when reading data from the memory array300, a first voltage V1(such as 1.2V) is provided to the first gate terminals of the OTP memory cells at the selected row, the first voltage V1is also provided to all of the second gate terminals of the memory array300, and a ground voltage Vg (such as 0V) is provided to all of the third gate terminals of the memory array300. Besides, the first voltage V1is also provided to the first source terminals of the OTP memory cells at a selected column via the bit line BL. The ground voltage Vg provided to the third gate terminal of the selected memory cell200′ works as a reverse read voltage. The reverse read voltage is not necessary to be set at a ground level, the reverse read voltage can be set at other voltage level lower than the first voltage V1.

According to the above arrangement, data stored in a selected OTP memory cell200′ at the selected row and column can be read via a signal line SL coupled to the third gate terminals of the selected row. The reading direction of the selected OTP memory cell inFIG. 13is opposite to the reading direction of the selected OTP memory cell inFIG. 12. Therefore, the selected OTP memory cell200′ can perform both forward reading operation (as shown inFIG. 12) and reverse reading operation (as shown inFIG. 13) smoothly, since the rupture position of the antifuse varactor230is ensured to be on the third source/drain extension area.

In addition, inFIG. 13, for the unselected OTP memory cell200at the unselected row and selected column, the ground voltage Vg is provided to the first gate terminal of the OTP memory cell at the unselected row; for the unselected OTP memory cell200at the selected row and unselected column, the ground voltage is provided to the first source terminal of the OTP memory cell at the unselected column; and for the unselected OTP memory cell200at the unselected row and unselected column, the ground voltage Vg is provided to the first gate terminal of the OTP memory cell, and the ground voltage Vg is also provided to the first source terminal of the OTP memory cell. Therefore, the unselected OTP memory cells200at the unselected row and/or unselected column can be set in a read inhibition status.

In the embodiments ofFIG. 11toFIG. 13, the OTP memory cell is illustrated by the OTP memory cell200according to the first embodiment ofFIG. 5, however, the OTP memory cells ofFIG. 11toFIG. 13can also be replaced by the OTP memory cell200A-200E according to the second to sixth embodiments of the present invention. The voltage ranges shown inFIG. 11toFIG. 13are applicable to a memory array made in a 40 nm process, and the present invention is not limited by the above voltage ranges. In other embodiments of the present invention, the voltage ranges can be changed according to processes at different scales.

In contrast to the prior art, the OTP memory cell of the present invention can reduce current leakage of the OTP memory cell by utilizing a MOS varactor for storing data, such that problems of slow bit response and malfunction can be prevented. Furthermore, the following gate transistor provides unique advantages in this invention. During program operation, the second gate terminal is biased to higher voltage than first gate terminal. It can form a cascade series transistor to resist high voltage damage from third gate terminal when antifuse is ruptured. Also second drain extension that adopts deeper depth can improve PN junction breakdown at drain side of following gate transistor. Besides, the OTP memory cell of the present invention is capable of performing both forward reading operation and reverse reading operation, so as to improve efficiency for reading operation.