Voltage hold circuit

A voltage hold circuit includes four switches, an operational amplifier and a capacitor. By turning the switches on and off, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Thus the voltage of the capacitor is equal to the voltage of the node. In the power off mode, the positive input end of the operational amplifier is coupled d to the capacitor, and the output end of the operational amplifier is coupled to the node. Thus the voltage of the node is equal to the voltage of the capacitor. Therefore, the voltage hold circuit is able to hold the voltage of the node in the power down state.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a voltage hold circuit, and more particularly, to a voltage hold circuit of a delay-locked loop circuit.

2. Description of the Prior Art

Please refer toFIG. 1.FIG. 1is a block diagram illustrating a prior art delay-locked loop (DLL) circuit10. The DLL circuit10is configured to generate output signals having the same cycle length as the input clock signals, but delayed by a cycle. The DLL circuit10includes a phase frequency detector11, a charge pump circuit12, a capacitor13, a voltage controlled delay line (VCDL)14and a dummy delay circuit15. The phase frequency detector11is configured to receive input clock signals SI and feedback signals FB, thereby generating UP signals SU and DOWN signals SD according to phase difference and frequency difference between the two detected signals. The charge pump circuit12is configured to receive the UP signals SU and the DOWN signals SD, thereby changing the generated current signals according to the logic state of the UP signals SU and the DOWN signals SD. The capacitor13is configured to receive the current signals from the charge pump circuit12, thereby generating a DC voltage VA by low pass filtering the current signals. The voltage controlled delay line14is configured to receive the input clock signals SI and the DC voltage VA, thereby determining the required delay time of the input clock signals SI according to the DC voltage VA. Feedback signal FB is generated as the output signal SO of the VCDL14passes through the dummy delay circuit14.

For the DLL circuit with a feedback loop, a node voltage VA (such as 736 mV) raises/decreases to voltage VDD/VSS due to partial power shutdown and leakage current of components in the feedback loop. After that, it takes a lot of time for the node voltage VA to be reestablished to the original voltage (736 mV) so as to recover the feedback loop. However, a common double data rate dynamic random access memory (DDR DRAM) chip regains normal operation about 2 to 10 time clock cycles after leaving partial power saving mode. Therefore, it is important to maintain the level of the node voltage VA. Maintaining the feedback loop in the power saving mode consumes a lot of power. Maintain the node voltage VA using analog-to-digital converter (ADC) or digital-to-analog converter (DAC) occupies large chip space, while using large capacitor results in large loading effect. Besides, leakage current of switch components is an issue which needs to be taken into consideration.

SUMMARY OF THE INVENTION

It is one of the objectives of the claimed invention to provide a voltage hold circuit.

According to one embodiment, a voltage hold circuit is provided. The voltage hold circuit includes an operational amplifier, a first switch, a second switch, a third switch, a fourth switch and a capacitor. The operational amplifier includes a positive input end, a negative input end, and an output end coupled to the negative input end. The first switch includes a first end, a second end coupled to the positive input end of the operational amplifier, and a control end for receiving a first control signal. The second switch includes a first end coupled to the first end of the first switch, a second end coupled to the negative input end of the operational amplifier, and a control end for receiving a second control signal. The third switch includes a first end coupled to the output end of the operational amplifier, a second end, and a control end for receiving the first control signal. The fourth switch includes a first end coupled to the positive input end of the operational amplifier, a second end coupled to the second end of the third switch, and a control end for receiving the second control signal. The capacitor includes a first end coupled to the second end of the fourth switch, and a second end coupled to a ground end.

According to one embodiment, a voltage hold circuit is provided. The voltage hold circuit includes an operational amplifier, a capacitor and a switch module. The operational amplifier includes a positive input end, a negative input end, and an output end coupled to the negative input end. The switch module is for coupling the positive input end of the operational amplifier to a node, and the output end of the operational amplifier to the capacitor when operating in a first phase, and for coupling the positive input end of the operational amplifier to the capacitor, and the output end of the operational amplifier to the node when operating in a second phase.

DETAILED DESCRIPTION

Please refer toFIG. 2.FIG. 2is a diagram illustrating a voltage hold circuit20according to the present invention. The voltage hold circuit20includes a first switch21, a second switch22, a third switch23, a fourth switch24, an operational amplifier25, and a capacitor26. An output end of the operational amplifier25is coupled to a negative input end of the operational amplifier25. The first switch21is coupled between a node A and a positive input end of the operational amplifier25, the second switch22is coupled between the node A and the negative input end of the operational amplifier25, the third switch23is coupled between an output end of the operational amplifier25and the capacitor26, and the fourth switch24is coupled between the positive input end of the operational amplifier25and the capacitor26. In this embodiment, the first switch21and the third switch23are controlled by the first control signal S1, while the second switch22and the fourth switch24are controlled by the second control signal S2. When the first switch21and the third switch23are turned on, the second switch22and the fourth switch24are turned off; when the first switch21and the third switch23are turned off, the second switch22and the fourth switch24are turned on. The switches21to24may be implemented by NMOS transistors, PMOS transistors, CMOS transistors, or transmission gates, with different corresponding control signals. Therefore, by switching the switches21to24, the voltage hold circuit20may maintain the voltage level of the node A when the power is shut down.

Please refer toFIG. 3.FIG. 3is a wave diagram illustrating the control signals of the voltage hold circuit20according to the present invention. The first control signal S1and the second control signal S2are complementary signals. When the first control signal S1is at high level, the second control signal S2is at low level. When the first control signal S1is at low level, the second control signal S2is at high level. According to the first control signal S1and the second control signal S2, the voltage hold circuit20operates in a first phase Ph1and a second phase Ph2. During the first phase Ph1, the first switch21and the third switch23are turned on, and the second switch22and the fourth switch24are turned off. During the second phase Ph2, the first switch21and the third switch23are turned off, and the second switch22and the fourth switch24are turned on. During the first phase Ph1, the voltage hold circuit20operates in a normal operation mode, and the voltage of the node A is stored in the capacitor26. During the second phase Ph2, the voltage hold circuit20operates in the power off mode, and the voltage level of the node A is maintained by the capacitor26.

Please refer toFIG. 4.FIG. 4is a diagram illustrating an equivalent circuit of the present voltage hold circuit20when operating in the first phase Ph1. During the first phase Ph1, the first switch21and the third switch23are turned on, and the second switch22and the fourth switch24are turned off. Thus, the node A is coupled to the positive input end of the operational amplifier25, and the output end of the operational amplifier25is coupled to the capacitor26. Hence the operational amplifier25functions as a unity-gain buffer. The voltage of the node A is outputted to the capacitor26via the operational amplifier25. That is, the voltage of the node A charges the capacitor26, and the voltage of the capacitor26then becomes equal to the voltage of the node A. In the normal operation mode, the voltage hold circuit20enters the first phase Ph1. Therefore, the voltage level of the node A may be stored in the capacitor26.

Please refer toFIG. 5.FIG. 5is a diagram illustrating an equivalent circuit of the voltage hold circuit20when operating in the second phase Ph2. In the second phase Ph2, the first switch21and the third switch23are turned off, and the second switch22and the fourth switch24are turned on. Thus, the capacitor26is coupled to the positive input end of the operational amplifier25, and the output end of the operational amplifier25is coupled to the node A. The operational amplifier25functions as a unity-gain buffer. The voltage of the capacitor26is outputted to the node A via the operational amplifier25, and the voltage of the node A then becomes equal to the voltage of the capacitor26. In the power-off mode, the voltage hold circuit20enters the second phase Ph2. Therefore, the voltage level of the node A may be maintained by the capacitor26.

Please refer toFIG. 6.FIG. 6is a diagram illustrating the voltage hold circuit20coupled to the DLL circuit10. The DLL circuit10is configured generate output signals having the same cycle length as the input clock signals, but delayed by a certain phase. The DLL circuit10includes a phase frequency detector11, a charge pump circuit12, a capacitor13, a VCDL14and a dummy delay circuit15. The voltage hold circuit20is coupled to the node A. When the DLL circuit10operates in the normal operation mode, the first switch21and the third switch23of the voltage hold circuit20are turned on, and the second switch22and the fourth switch24are turned off. Thus, the voltage hold circuit20may receive the current signal from the charge pump circuit20, and generate DC voltage VA by low-pass filtering the current signal by the capacitor16. At the time, the voltage of the capacitor26is equal to the DC voltage VA. When the power of the DLL circuit10is shut down, the first switch21and the third switch23of the voltage hold circuit20are turned off, and the second switch22and the fourth switch24are turned on. Therefore, the voltage level of the node A may be maintained by the capacitor26.

In summary, the voltage hold circuit of the present invention includes four switches, an operational amplifier and a capacitor. According to the switching of the switches, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Therefore, the voltage of the capacitor is equal to the voltage of the node. In the power-off mode, the positive input end of the operational amplifier is coupled to the capacitor, and output end of the operational amplifier is coupled to the node. Therefore, the voltage of the node is equal to the voltage of the capacitor. Since the capacitor and the operational amplifier of the voltage hold circuit both have small leakage current, the voltage hold circuit may maintain the voltage of the node when powered-off.