Multi-protocol serial interface apparatus and system-on-chip apparatus including the same

A multi-protocol serial interface (MPSI) apparatus can include a controller circuit that is configured to receive information about a type of MPSI utilized for data transfer and that is configured to control a format of the data transfer and input/output timing associated with the data transfer. A data generation and processing circuit is coupled to the controller circuit and is configured to extract information from a buffer memory to generate data for the data transfer according to the format based on the information and is configured to generate the data in a packet format or a bit format based on the information.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2007-0030049, filed on Mar. 27, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

FIELD OF THE INVENTION

The present invention relates to a multi-protocol serial interface (MPSI) apparatus, and more particularly, to an MPSI apparatus capable of generating and receiving data using various types of protocols.

BACKGROUND

A multi-protocol serial interface (MPSI) apparatus is designed to transmit and receive data corresponding to a plurality of protocols between two different devices.

An interface protocol may vary according to whether (i) synchronous or asynchronous operations are performed, (ii) the bit width of bits transmitted at a time, (iii) whether error correction is to be performed, and (iv) whether a strobe signal is applied.

A widely used universal asynchronous receiver/transmitter (UART) consecutively transmits 7 or 8 bits of data. Once a specific voltage level changes from logic high to logic low, the UART senses the change and starts data transmission. By incorporating a stop bit into the last of the consecutive bits, the UART indicates the end of the data transmission.

Pulse-code modulation (PCM) and a serial peripheral interface (SPI) are used to perform data transmission and reception in synchronization with a clock signal and directly transmit and receive binary data.

An audio codec (AC) 97 is used to transmit and receive data in packet form.

A conventional MPSI apparatus is separately designed for each type of protocol. Conventionally, several MPSI apparatuses are included in a single block in order to interface data corresponding to different types of protocols.

FIG. 1Ais a block diagram of a general MPSI block101including a plurality of MPSI apparatuses.

FIG. 1Bis a block diagram illustrating an example of a structure of the MPSI block101illustrated inFIG. 1A.

Referring toFIG. 1B, an MPSI block131includes four MPSI apparatuses, and more specifically, UARTs141and142, one Inter-IC Sound (I2S)143, and one Audio Codec (AC) 97144.FIG. 1Cis a block diagram illustrating another example of a structure of the MPSI block101illustrated inFIG. 1A.

Referring toFIG. 1C, an MPSI block161includes four MPSI apparatuses, and more specifically, one PCM171, one UART172, and first and second I2Ss173and174.

In the MPSI block131ofFIG. 1B, it is not possible to use three UARTs and to perform an interface using protocols other than those included in the MPSI block131. In other words, if the MPSI block131ofFIG. 1B, includes three UARTs it may be difficult to also include PCM, Infrared Data Association (IrDA), or an SPI as an interface in the MPSI block131as well.

In the MPSI block161ofFIG. 1C, it is not possible to use at least two UARTs and to perform an interface using protocols other than those included in the MPSI block161. Moreover, for an interface using the PCM171and the first I2S173, the UART172and the second I2S174are not used, degrading the use efficiency of a chip.

As discussed above, a conventional MPSI block or a conventional system-on-chip (SOC) including a plurality of MPSI apparatuses can perform an interface using only a protocol that is initially included during a design stage. As a result, an interface using protocols other than the initially included protocol may be difficult. Moreover, in such a conventional MPSI block or conventional system-on-chip (SOC), several MPSI apparatuses are not used, degrading the use efficiency of the entire MPSI block.

SUMMARY

Embodiments according to the present invention can provide a multi-protocol serial interface (MPSI) apparatus that can be flexibly used according to a protocol desired by a user. In some embodiments according to the present invention, a system-on-chip (SOC) apparatus can be provided. In some embodiments according to the present invention, an SOC apparatus can include a plurality of MPSI apparatuses that share a single buffer memory, which may thereby reduce the size of a buffer memory.

In some embodiments according to the present invention a multi-protocol serial interface (MPSI) apparatus can include a controller circuit that is configured to receive information about a type of MPSI utilized for data transfer and that is configured to control a format of the data transfer and input/output timing associated with the data transfer. A data generation and processing circuit is coupled to the controller circuit and is configured to extract information from a buffer memory to generate data for the data transfer according to the format based on the information and is configured to generate the data in a packet format or a bit format based on the information.

DESCRIPTION OF EMBODIMENTS ACCORDING TO THE INVENTION

It will be understood that the term “unit” is used herein to refer to logical functions which can structural embodiments, such as circuits. Accordingly, although the term “unit” is used, it will be understood that each of the units may be embodied as a structural circuit.

FIG. 2is a block diagram of a system-on-chip (SOC) apparatus201for an interface, in some embodiments according to the invention. Referring toFIG. 2, the SOC apparatus201for an interface according to the current embodiment of the present invention includes a central processing unit (CPU)220, a memory controller (MC)225, a direct memory access (DMA)240, a multi-protocol serial interface (MPSI) block245, and a data bus230.

The CPU220is a central processing device for controlling the overall operation of the SOC apparatus201. Thus, all intellectual property (IP) blocks included in the SOC apparatus201are controlled by the CPU220.

The MC225controls data input to and data output from an external memory210.

The DMA240allows data to be transmitted directly between a memory (the external memory210) and the one of IP blocks without using the CPU220.

The MPSI block245includes a plurality of MPSI apparatuses.

Hereinafter, each of the plurality of MPSI apparatuses included in the MPSI block245and the SOC apparatus201including the MPSI block245will be described in detail with reference toFIGS. 3 through 6.

FIG. 3is a block diagram of an MPSI apparatus300(included in the MPSI block245) according to an embodiment of the present invention.

Referring toFIG. 3, the MPSI apparatus300according to the current embodiment of the present invention includes a controller330and a data generation and processing unit350. The MPSI apparatus300may further include a buffer memory310, a serialization/deserialization unit360, and a bit processing unit370.

The controller330receives information about a type of MPSI needed for a data transfer and controls a control order or the format of interfaced data and input/output points of time (i.e., timing) according to the received information.

The controller330includes an interface (I/F) bus unit331, a DMA/interrupt controller333, a special function register (SFRs)335, a finite state machine (FSM)339, and a timing generator337.

The I/F bus unit331is a general-purpose bus for an interface with a general-purpose on-chip bus.

The DMA/interrupt controller333controls the operation of the DMA240, and controls a data processing order in consideration of interrupt generation upon generation of an interrupt request.

The SFRs335is requested by the external CPU220to operate with a particular MPSI. The request is provided by programming a value in the SFRs335. For example, the SFRs335may recognize that it is to operate with a UART if ‘001’ is stored in the 0thaddress of the SFRs335, to operate with an Inter-IC Sound (I2S) if ‘010’ is stored in the 0thaddress of the SFRs335, and to operate with an audio codec (AC) 97 if ‘011’ is stored in the 0thaddress of the SFRs335.

According to the type of a required MPSI, the SFRs335controls generation of data used by the required MPSI or input/output points of time using software. For example, if an AC97 using data in a packet form is required, the SFRs335generates packet data used in the AC97 by controlling the FSM339and the timing generator337and determines transmission and reception points of time with respect to the generated data. If a serial peripheral interface (SPI) using binary data synchronized with a clock signal is required, the SFRs335controls a bit decoding unit373to transmit received data to the buffer memory310. In this case, a reception data processing unit353does not generate packet data because the SPI does not use data in a packet form.

The SFRs335is used for general purposes and its setting condition is set by a user separately for each protocol.

The FSM339adjusts the operation state transition of intellectual property (IP) blocks315, and361included in the MPSI apparatus in response to a control signal output from the SFRs335. The FSM339, which is simple state logic circuit of a simple level, marks the order of operations performed by the IP blocks315,350, and361in response to a control signal input from the SFRs335with a state. In other words, the FSM339determines which operation a corresponding IP block is to perform in response to an input condition A.

For example, if an AC97 using data in a packet form is required, the SFRs335instructs the FSM339to generate packet data. In response to the instruction, the FSM339activates the transmission data generation unit351to generate packet data.

The timing generator337generates a clock signal and adjusts data transmission/reception points of time or a data processing point of time.

The buffer memory310stores transmission/reception data and includes a transmission buffer memory311and a reception buffer memory313(The transmission buffer memory311and the reception buffer memory313may be both first-in, first-out (FIFO) memories). The transmission data is stored in the transmission buffer memory311, and a memory required for data reception is stored in the reception buffer memory313.

During data transmission, the data generation and processing unit350extracts information required to generate data corresponding to the required MPSI from the transmission buffer memory311or the FSM339. The data generation and processing unit350then outputs the generated data to the bit processing unit370.

During data reception, the data generation and processing unit350receives data from outside through the bit processing unit370, stores information data extracted by analyzing the received data in the reception buffer memory310, and transmits state data to the controller330. Herein, information data refers to data used as actual information (i.e. data transferred to/from the bit processing unit370) and state data refers to data for indicating the state of the information data, e.g., input/output points of time with respect to the information data or the existence of errors in the information data. The data generation and processing unit350will be described later in detail with reference toFIG. 5.

The serialization/deserialization unit360includes a serializer361and a deserializer363.

The bit processing unit370includes a bit coding unit371and the bit decoding unit373. A signal output from the bit coding unit371and a signal input to the bit decoding unit373are used in actual serial interface communication and are input from or output to outside the MPSI apparatus300.

The serializer361receives data that is generated by and output in parallel from the transmission data generation unit351and serializes the received data.

The bit coding unit371converts data stored in the buffer memory310into a form used by a required MPSI. Generally, in data signal transmission, a signal indicating ‘0’ is a logic low signal and a signal indicating ‘1’ is a logic high signal. However, there may be various data forms. For example, a peak pulse may not be generated for ‘0’ and a peak pulse may be generated for ‘1’, or a logic level may transit for ‘1’ and a logic level may be maintained for ‘0’.

For example, the buffer memory310may store a signal indicating ‘0’ as a logic low signal and a signal indicating ‘1’ as a logic high level. Herein, it is assumed that a required MPSI (or SPI) uses a data form in which a logic level transition indicates ‘1’ and a logic level that is maintained indicates ‘0’. The bit coding unit371then converts a data signal output from the buffer memory310into a data signal form used by the MPSI (or SPI).

The bit decoding unit373receives signals indicating ‘0’ and ‘1’ transmitted in different forms and converts the received signals into data suitable to be stored in the buffer memory310. As mentioned above, generally a signal indicating ‘0’ is a logic low signal and a signal indicating ‘1’ is a logic high signal. However, there may be various data forms. For example, a peak pulse may not be generated for ‘0’ and a peak pulse may be generated for ‘1’, or a logic level may transit for ‘1’ and a logic level may be maintained for ‘0’. The bit decoding unit373receives data in above-described various forms and analyzes signals, thereby converting the received data into bit data to be stored in the buffer memory310.

The deserializer363divides serially input data in units of a particular number of bits or bytes and outputs the divided data in parallel. For example, 192 bytes of data transmitted serially may be output in parallel as six chunks of 32-byte data.

FIG. 4Aillustrates the format of data used in a UART.

Referring toFIG. 4A, if a strobe signal transits from high to low, the UART senses the state transition and starts data transmission. The UART transmits 7- or 8-bit based data401and inserts a stop bit403into the last portion of the data401. When a required MPSI is the UART, the data generation and processing unit350is not activated because the UART does not use data in a packet form.

FIG. 4Billustrates the format of data used in a Serial Peripheral Interface (SPI) and pulse-coded modulation (PCM).

Referring toFIG. 4B, in a SPI and PCM, data is transmitted in synchronization with a clock signal. In other words, in a SPI and PCM, a data signal is transmitted bit-by-bit during each specific interval of the clock signal.

FIG. 4Cillustrates packet data used in an AC97 or the like.

Referring toFIG. 4C, the AC97 uses data in a packet form. Data in a packet form includes a header421and a payload423. The header421indicates what data is included in the payload423. For example, if load time information is included in the payload423, the header421includes information indicating that ‘load time information starts’. The header421also includes information about the type of the payload423or additional information of packet data. In other words, the header421may include payload length information, an error correction code (ECC), or a portion of a cyclic redundancy check (CRC).

If a required MPSI uses packet data, the data generation and processing unit350is activated in order to generate packet data or divide packet data into different portions such as the header421, the payload423, a CRC (not shown), and an ECC (not shown) for transmission to the controller330or the buffer memory310.

FIG. 4Dillustrates the format of data used in the Infrared Data Association (IrDA).

Referring toFIG. 4D, the IrDA outputs a peak signal if a logic high signal is transmitted. As mentioned above, the bit decoding unit373included in the bit processing unit370receives a signal as illustrated inFIG. 4Dand converts the received signal into data suitable to be stored in the buffer memory310.

Data forms used by MPSI types, such as an I2S and the like, other than those shown inFIGS. 4A through 4Dwould be obvious to those of ordinary skill in the art. Thus, the MPSI apparatus300according to the current embodiment of the present invention programs the SFRs335and the FSM339according to a required MPSI and generates and receives packet data through the data generation and processing unit350, thereby flexibly changing the operation of the MPSI according to a required protocol.

FIG. 5is a detailed block diagram of the data generation and processing unit350illustrated inFIG. 3, according to an embodiment of the present invention.

The data generation and processing unit350is activated when an MPSI using data in a packet form is required. The data generation and processing unit350is activated to generate a header, a CRC, and an ECC required for packet data under the control of the SFRs335and the FSM339.

First, the operation of a transmission side of the data generation and processing unit350will be described.

A packet generation unit513extracts data required to generate a header, a payload, a CRC, and an ECC from information data stored in the buffer memory310or state data stored in the SFRs335. Using the extracted data, the packet generation unit513generates a header, a payload, a CRC, and an ECC. The packet generation unit513then arranges the generated header, payload, CRC, and ECC in a particular order, thereby generating packet data. Although the header, the ECC, the payload, and the CRC of the packet data are generally arranged in this sequential order, they may also be arranged in other orders.

Data of the payload is actual information data. The CRC is used to detect an error in transmitted data and to indicate the end of the payload. The ECC having information about an error included in packet data is used to recover data having the error. The generated packet data is output to a distribution unit515. The packet generation unit513outputs a particular number of bits or bytes of data in parallel. For example, if the generated packet data totals 320 bytes and is transmitted in units of 32 bytes, the packet generation unit513outputs 10 signals in parallel. The number of signals that are output in parallel may vary with the number N of signal lines.

The distribution unit515divides signals that are transmitted in parallel through N signal lines into several groups and distributes the groups to serializers531and532. InFIG. 5, two serializers531and532are provided. Thus, the distribution unit515divides N signals into two groups and outputs N/2 parallel signals to each of the serializers531and532.

The serializer361may include a plurality of serializers531and532. The deserializer363may include a plurality of deserializers541and542. Herein, two serializers531and532and two deserializers541and542are provided in the transmission side and a reception side, respectively. Each of the serializers531and532serializes data that is output in parallel from the distribution unit515into serial data.

The serializers531and532are connected to bit encoders534and535, respectively.

Herein, an output signal line561may also be used as an input signal line.

Hereinafter, the operation of the reception side of the data generation and processing unit350will be described.

A merging unit523merges N/2 signals transmitted from each of the two deserializers541and542to output N signals.

A packet recovery unit521receives transmitted packet data and divides the packet data into a header, an ECC, a payload, and a CRC. By analyzing data of each of the header, the ECC, the payload, and the CRC, the packet recovery unit521extracts information data and state data. The packet recovery unit521then transmits the extracted information data and state data to the controller330or the buffer memory310.

The packet recovery unit521rearranges pure information data extracted from the payload into a form suitable to be stored in the buffer memory310and then transmits the rearranged data to the buffer memory310. The header, the ECC, or the CRC is transmitted to the SFRs335of the controller330for error detection, error correction, or recovery of lost information data.

The parsers510and520may also be positioned outside of the processing unit350.

In other words, the transmission side of the data generation and processing unit350includes the parser510, the packet generation unit513, and the distribution unit515. The reception side of the data generation and processing unit350includes the parser520, the packet recovery unit521, and the merging unit523.

Hereinafter, the operation and structure of the transmission side of the data generation and processing unit350will be described.

The parser510extracts data required to generate a header, a payload, a CRC, and an ECC from data stored in the buffer memory310. The parser510then transmits the extracted data to the packet generation unit513.

The packet generation unit513generates the header, the payload, the CRC, and the ECC using the extracted data. Herein, the header, the payload, the CRC, and the ECC have already been described above. The generated header, payload, CRC, and ECC are arranged in a particular order, thereby generating packet data.

The packet data is transmitted to the distribution unit515. The operation and function of the distribution unit515have already been described above.

Hereinafter, the operation of the reception side of the data generation and processing unit350will be described.

The function and structure of the merging unit523have already been described above.

The packet recovery unit521receives transmitted packet data and divides the received packet data into a header, an ECC, a payload, and a CRC. The packet recovery unit521then analyzes data of each of the header, the ECC, the payload, and the CRC, thereby extracting information data and state data. The packet recovery unit521transmits the extracted data to the controller330or the parser520. The header, the ECC, or the CRC is transmitted to the SFRs339of the controller330for error detection, error correction, or recovery of lost information data.

The parser520rearranges pure information data extracted from the payload into a form suitable to be stored in the buffer memory310and transmits the rearranged data to the buffer memory310.

FIG. 6is a block diagram of an MPSI block according to another embodiment of the present invention.

Referring toFIG. 6, the MPSI block according to the current embodiment of the present invention includes a buffer memory610that is shared by a plurality of MPSIs631through635.

In an SOC apparatus including a plurality of MPSIs, the number of MPSIs used at the same time is limited. Thus, if four MPSIs are generally used at the same time in an SOC apparatus including 5 MPSIs, a buffer memory having a capacity that is sufficient for 4 MPSIs is shared by the 4 MPSIs.

Each of the MPSIs631through635corresponds to the MPSI apparatus300illustrated inFIG. 3according to a previous embodiment of the present invention. As illustrated inFIG. 6, the buffer memory610is shared, thereby reducing the capacity of the buffer memory610and thus reducing the entire chip size.

As is apparent from the foregoing description, the MPSI apparatus according to the present invention generates and receives data corresponding to each of a plurality of protocols, thus being capable of being used according to any type of protocol.

Moreover, the SOC apparatus including a plurality of MPSIs according to the present invention removes a need for unnecessary IP blocks, thereby improving use efficiency.