MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

The present disclosure relates to memory devices and memory systems. An example memory device includes a first core die, a second core die, and a base die stacked in a first direction. The base die is configured to output data of memory cells provided by the first and second core dies through a through-via. The through-via passes through the first and second core dies in the first direction with different burst lengths based on a mode signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0080426 filed in the Korean Intellectual Property Office on Jun. 22, 2023, the entire contents of which are incorporated herein by reference.

BACKGROUND

As the amount of data to be processed by electronic devices increases, memory devices with high capacity and high bandwidth are required. To improve memory integration, three-dimensional (3D) disposing methods for stacking memory chips have been developed from the existing two-dimensional (2D) disposing method.

A high bandwidth memory (HBM) device may include vertically stacked semiconductor chips, and may electrically connect semiconductor chips through a through-via such as a through silicon via TSV.

However, as the number of data input/output pins and the number of data inputs/outputs of the high bandwidth memory device are fixed at relatively high values, there is a need to variously configure the number of data input/output pins and the rate of data transfer of the high bandwidth memory device to accommodate interconnectivity with external devices (e.g., a processor) that may have more or less number of data input/output pins and operate lower data transfer rate than that of the high bandwidth memory device.

SUMMARY

The present disclosure relates to memory devices, including a memory device for exchanging data of the number of data input/output pins with external devices as well as a memory device for reducing a cost for a process relating to a size and a pitch of a configuration of an external device, and memory systems including the same.

In some implementations, a memory device includes: a first core die and a second core die stacked in a first direction, the first core die including first memory cells and the second core die including second memory cells and a base die stacked in the first direction with the first and second core dies, the base die configured to output data of the first memory cells and the second memory cells provided by the first core die and the second core die through a through-via, the through-via passing through the first core die and the second core die in the first direction with different burst lengths based on a mode signal.

In some implementations, a memory device includes: a first core die and a second core die stacked in a first direction, the first core die including first memory cells and the second core die including second memory cells and a base die stacked with the first and second core dies in the first direction, the base die configured to output data of the first memory cells and the second memory cells provided by the first core die and the second core die through a through-via, the through-via passing through the first core die and the second core die in the first direction, the base die including a first data bump and a second data bump connected to an external pad on one side and configured to output the data, a first data register connected to the first data bump, a second data register connected to the second data bump, and a multiplexer disposed between the first data register and the second data register.

In some implementations, a memory system includes a memory device including a first core die, a second core die, and a base die stacked in a first direction, the first core die including first memory cells, the second core die including second memory cells, the base die configured to output data of the first memory cells and the second memory cells provided by the first core die and the second core die through a through-via, and the through-via passing through the first core die and the second core die in the first direction to first data bumps and a memory controller configured to exchange the data with the memory device through second data bumps, wherein the number of the second data bumps is less than the number of the first data bumps.

DETAILED DESCRIPTION

In the following detailed description, only certain implementations of the present disclosure have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described implementations may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

The size and thickness of each configuration shown in the drawings are arbitrarily shown for better understanding and ease of description, but the present disclosure is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc., are enlarged for clarity. The thicknesses of some layers and areas are exaggerated for convenience of explanation.

The phrase “in a plan view” means viewing an object portion from the top, and the phrase “in a cross-sectional view” means viewing a cross-section of which the object portion is vertically cut from the side.

FIG.1shows a configuration of an example of a memory system.

Referring toFIG.1, the memory system1includes a memory device10and a memory controller20.

The memory device10may be a high bandwidth memory (HBM) device including memory channels MCHa to MCHh (refer toFIG.3), and without being limited thereto, it may be a dynamic random access memory (DRAM) such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, or a rambus dynamic random access memory (RDRAM). The memory channels MCHa to MCHh may include a memory cell array including memory cells.

The memory controller20may provide various signals to the memory device10through a memory interface, a pin, or a bump to control memory operations such as write and read. The memory controller20may have an additional die shape, and depending on the implementation, it may be installed in a system on chip (SoC) die, a graphic processing unit (GPU) die, and a central processing unit (CPU) die.

For example, the memory controller20may provide a command CMD and an address ADDR to the memory device10to access data DQ on cells in the memory device10. According to some implementations, the memory controller20may provide a mode signal MODE_SEL together with the command CMD and the address ADDR to the memory device10and may control an operation mode of the memory device10for a memory operation, and a technical scope of the present disclosure is not limited thereto.

Further, the memory device10may exchange the data DQ with the memory controller20through first data pads dp1_1to dp1_N and second data pads dp2_1to dp2_M between the memory controller20and the memory device10. The M may be less than the N, which is not limited thereto. According to some implementations, the ratio of the number of the second data pads dp2_1to dp2_M and the number of the first data pads dp1_1to dp1_N may be 1:n, and the n may be an integer of equal to or greater than 2.

The memory controller20may access the memory device10according to a request from a host (HOST). The memory controller20may communicate with the host by use of various types of protocols, and for example, the memory controller20may communicate with the host by use of an interface protocol such as the PCI-E (Peripheral Component Interconnect-Express), the ATA (Advanced Technology Attachment), the SATA (Serial ATA), the PATA (Parallel ATA) or the SAS (serial attached SCSI). In addition, other various types of the interface protocols such as the USB (Universal Serial Bus), the MMC (Multi-Media Card), the ESDI (Enhanced Small Disk Interface), or the IDE (Integrated Drive Electronics) may be applied to the protocol between the host and the memory controller20.

FIG.2toFIG.4shows an example of a memory system.FIG.5andFIG.6show an example base die of a memory device and an example lower side of a memory controller.

Referring toFIG.1toFIG.6, the memory system1includes a memory device10, a memory controller20, an interposer30, and a printed circuit board (PCB)40.

The memory device10may include a memory die100including four core dies100_1to100_4stacked in a third direction Z and a base die200. First bumps MB may be formed between the stacked core dies100_1to100_4and the base die200, and a through silicon via TSV, a kind of through-via, passing through the core dies100_1to100_4may be formed among the stacked first bumps MB.

First direct access bumps dab, first power bumps pb1, first command and address bumps cab1, and first data bumps db1may be disposed on a lower side of the base die200with respect to the third direction Z. Although not shown, the base die200may include a data input/output buffer295(refer toFIG.7) connected to the first data bumps db1and transmitting/receiving data.

Referring toFIGS.2and3, although only four core dies are shown, one or more embodiments are not limited thereto, and the core dies may be variously configured to have more than or less than four. In addition, the base die200may be stacked not on a lower portion of the stacked core dies but on an upper portion thereof.

FIG.3shows a configuration of four stacked core dies100_1to100_4, and the respective stacked core dies100_1to100_4may include two memory channels MCHa and MCHc, MCHb and MCHd, MCHe and MCHg, and MCHf and MCHh, and the respective memory channels MCHa to MCHh may include a predetermined number of memory banks.

The memory channels MCHa, MCHb, MCHe, and MCHf may be disposed on the left side of the core dies100_1to100_4with respect to an XY-plane, and the memory channels MCHc, MCHd, MCHg, and MCHh may be disposed on the right side of the core dies100_1to100_4with respect to the XY-plane. The memory channels MCHa to MCHh may respectively divided into top and bottom in the corresponding core dies100_1to100_4and may then be disposed. Corresponding data terminals DQ1ato DQ4a, DQ1bto DQ4b, DQ1eto DQ4e, and DQ1fto DQ4fand corresponding command and address terminals CATa, CATb, CATe, and CATf may be included among the divided and disposed memory channels MCHa, MCHb, MCHe, and MCHf, and corresponding data terminals DQ1cto DQ4c, DQ1dto DQ4d, DQ1gto DQ4g, and DQ1hto DQ4hand corresponding command and address terminals CATc, CATd, CATg, and CATh may be included among the divided and disposed memory channels MCHc, MCHd, MCHg, and MCHh. A first data group DG1may be transmitted through data terminals DQ1a, DQ1b, DQ1e, and DQ1f, and a second data group DG2may be transmitted through data terminals DQ2a, DQ2b, DQ2e, and DQ2f. In this way, third to eighth data groups DG3to DG8may be transmitted through other data terminals DQ3ato DQ4h. A first command and address group CAG1may be transmitted through command and address terminals CATa, CATb, CATe, and CATf, and a second command and address group CAG2may be transmitted through command and address terminals CATc, CATd, CATg, and CATh.

Referring toFIG.3, the data terminals and the command and address terminals may be the first bumps MB shown inFIG.2, respectively. Further, lines vertically passing through the data terminals and the command and address terminals may be the TSV.

Assuming that n-bit data are input/output through the respective data terminals DQ1a-DQ4a, . . . , DQ1h-Q4h, the total of 32n-bit data may be input/output through the entire data terminals. Assuming that k-bit command and address are input/output through the respective command and address terminals CATa to ATh, the total of 8k-bit command and address may be input/output through the entire command and address terminals.

As shown inFIG.3, the second to eighth data groups DG2to DG8are configured to be identical with lines that correspond to the first data group DG1, and the second command and address group CAG2are configured to be identical with lines that correspond to the first command and address group CAG1.

The core dies100_1to100_4shown inFIG.2andFIG.3may be manufactured to be a memory device for respectively storing data that are input through data terminals to selected memory cells from among memory cells of a memory cell array in response to the command and address received through the command and address terminals or outputting the data stored in the selected memory cells through data terminals.

Second command and address bumps cab1, second data bumps db2, second power bumps pb2, and first control signal bumps cdb may be disposed on a lower side of the memory controller20. Although not shown, the memory controller20may include a buffer connected to the second data bumps db2.

The first bumps MB, the first direct access bumps dab, the first and second power bumps pb1and pb2, the first and second command and address bumps cab1and cab2, the first and second data bumps db1and db2, and the first control signal bumps cdb may be micro bumps.

Second direct access bumps DAFB, third power bumps PBFB, and second control signal bumps CDFB may be disposed on a lower side of the interposer30. The interposer30may include a direct line dal for connecting the first direct access bumps dab and the second direct access bumps DAFB; a command and address line cal for connecting the first command and address bumps cab1and the second command and address bumps cab2; and control signal lines cdl for connecting the first data bumps db1, the second data bumps db2, the data lines dl, the first control signal bumps cdb, and the second control signal bumps CDFB.

As shown inFIG.4toFIG.6, the first data bumps db1include 1 to N first data bumps db1_1to db1_N, and the second data bumps db2include 1 to M data second bumps db2_1to db2_M. According to some implementations, the number of the second data bumps db2may be less than the number of the first data bumps db1, and a ratio of the M and the N may be 1 to n, and the n is an integer of equal to or greater than 2. Depending on some implementations, the n may be 2 or 4. As shown inFIG.4,FIG.5, andFIG.6, the ratio of the number of the second data pads dp2_1to dp2_M and the number of the first data pads dp1_1to dp1_N is 1 to 2, although other ratios may be used.

The first data bumps db1may include a data pad. For example, first_x and first_y data bumps db1_xand db1_yincluded in the first data bumps db1may include first_x and first_y data pads dp1_xand dp1_y. Further, the second data bumps db2may respectively include a data pad. For example, a second_a data bump db2_aincluded in the second data bumps db2may include a second_a data pad dp2_a.

The first data bumps db1and the second data bumps db2may be electrically connected through interposer pads FP_x and FP_a and a data line dl_a disposed on an upper side of the interposer30. According to some implementations, the first_x and first_y data bumps db1_xand db1_ymay be connected to an x-th interposer pad FP_x, and the x-th interposer pad FP_x may be connected to an a-th data line dl_a and the a-th interposer pad FP_a and may transmit/receive data to/from the second_a data pad dp2_a. According to some implementations, the ratio between the number of the interposer pads connected to the data bumps db1and the number of data bumps db1may be 1 to n, and n may be an integer of equal to or greater than 2.

According to some implementations, the second data bumps db2and the data lines dl may correspond one-to-one, and the second_a data bump db2_aand the first data line dl_a may correspond to each other. According to some implementations, the number of the data lines dl may be less than the number of the first data bumps db1and the number ratio of the first data bumps db1and the data lines dl may be equal to the number ratio of the first data bumps db1and the second data bumps db2. According to some implementations, the ratio between the number of the data lines dl and the number of the first data bumps db1may be 1 to n, and n may be an integer of equal to or greater than 2, like 2 or 4. As shown inFIG.4,FIG.5and FIG.FIG.6, the ratio between the number of the data lines dl and the number of the first data bumps db1may be 1 to 2.

Through the ratio of the number of the second data pads dp2_1to dp2_M and the number of the first data pads dp1_1to dp1_N, and the ratio of the number of the data lines dl and the first data bumps db1, the memory system1may provide a memory controller and an interposer for reducing the cost of processes relating to the size and the pitch of the configuration.

Although not shown, the interposer30may additionally include power lines for connecting the first power bumps pb1and the third power bumps PBFB and connecting the second power bumps pb2and the third power bumps PBFB. The second direct access bumps DAFB, the third power bumps PBFB, and the second control signal bumps CDFB may be flip die bumps.

Direct access balls DAB, power balls PB, and control signal balls CDB may be disposed on a lower side of the PCB40.

The second direct access bumps DAFB may be connected to the direct access balls DAB, the third power bumps PBFB may be connected to the power balls PB, and the second control signal bumps CDFB may be connected to the control signal balls CDB on the PCB40.

FIG.7shows a configuration of another example of a memory device.FIG.8shows an example of a memory device.

Referring toFIG.7andFIG.8, the memory device10includes a memory cell array110, a row decoder120, a sense amplifier170, a control logic circuit210, an address register220, a bank control logic230, a refresh control circuit245, a column address latch250, a row address multiplexer260, a column address latch250, a column decoder270, an input/output gating circuit290and a data input/output buffer295.

The memory cell array110may include a predetermined number of memory banks (not shown) included in the memory channels MCHa to MCHh. Depending on some implementations, the sense amplifier170, the row decoder120, and the column decoder270may include bank sense amplifiers, bank row decoders, and bank row decoders connected to respective memory banks, which is not limited thereto.

The memory cell array110may include word lines WL, bit lines BL, and memory cells MC disposed at points on which the word lines WL cross the bit lines BL.

The control logic circuit210may control an operation of the memory device10. For example, the control logic circuit210may generate control signals so that the memory device10may perform a write operation or a read operation. The control logic circuit210may include a command decoder211for decoding a command CMD provided by the memory controller20and a mode register212for setting an operation mode of the memory device10.

For example, the command decoder211may decode a write enable signal, a row address strobe signal, a column address strobe signal, and a channel selection signal to generate a control signal CTL that corresponds to the command CMD.

The mode register212may store setting information for setting the operation mode of the memory device10. The memory controller20may perform a mode register write operation MRW to store the setting information in the mode register212. The memory controller20may perform a mode register read operation MRR to receive the setting information stored in the mode register212from the memory device10.

The address register220may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller20. The address register220may provide the received bank address BANK_ADDR to the bank control logic230, and may provide the received row address ROW_ADDR to the row address multiplexer260.

The bank control logic230may generate bank control signals in response to the bank address BANK_ADDR. The row decoder120and the column decoder270may activate the corresponding bank in response to the bank control signals.

The row address multiplexer240may receive the row address ROW_ADDR from the address register220, and may receive a refresh row address REF_ADDR from the control logic circuit210. The row address multiplexer240may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA output by the row address multiplexer240may be applied to the row decoder120.

The column address latch250may receive the column address COL_ADDR from the address register220, and may temporarily store the column address COL_ADDR. The column address latch250may gradually increase the column address COL_ADDR in a burst mode. The column address latch250may apply the temporarily stored or gradually increased column address to the column decoder270.

The column decoder270may, relating to the bank activated by the bank control logic230, activate the sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input/output gating circuit290.

The input/output gating circuit290may include input/output data gating circuits, input data mask logics, data registers291_0to291_2n−1, and multiplexers292_0to292_n−1. The input/output gating circuit290may receive a control signal CTL from the control logic circuit210, and may receive a mode signal MODE_SEL from the memory controller20. According to some implementations, as shown inFIG.5, the mode signal MODE_SEL may be input to the input/output gating circuit290through the first command and address bump cab1.

The respective data registers291_0to291_2n−1 may input/output data DQ[0] to DQ[2n−1] to/from the first data pads dp1_0to dp1_2n−1 through the data input/output buffer295. For ease of description, reference numerals of the first data pads dp1_1to dp1_N shown inFIG.5are different from the reference numerals of the first data pads dp1_0to dp1_2n−1 shown inFIG.8, but the respective configurations shown inFIG.5andFIG.8are the same according to the technical scope of the present disclosure. Depending on some implementations, N ofFIG.5may be equal to 2n ofFIG.8. The bit lines corresponding to burst length BL may be simultaneously accessed so as to support the burst mode on the burst length for indicating a maximum number of column locations for accessing the bit lines by the memory device10. The data registers291_0to290_2n−1 may temporarily store the simultaneously accessed bits in order in the burst mode, and the burst length may be set to be 8 as shown in the drawing, which is not limited thereto.

The multiplexers292_0to292_n−1 may be disposed between the even numbered data registers291_0, . . . ,291_2n−2 and the odd numbered data registers291_1, . . . ,291_2n−1. In the present disclosure, the multiplexers292_0to292_n−1 may determine a data path input/output according to the input mode signal MODE_SEL. Further, the multiplexers292_0to292_n−1 may be operable as multiplexers or demultiplexers according to the operation of the memory device10.

At the read operation of the memory device10, the multiplexers292_0to292_n−1 may output the data DQ[0], . . . , DQ[2n−2] output by the even numbered data registers291_0, . . . ,291_2n−2 to the even numbered first data pads dp1_0, . . . , dp1_2n−2 through the data input/output buffer295according to the mode signal MODE_SEL. The multiplexers292_0to292_n−1 may output the data DQ[0], . . . , DQ[2n−2] output by the even numbered data registers291_0, . . . ,291_2n−2 to the odd numbered data registers291_1, . . . ,291_2n−1 according to the mode signal MODE_SEL.

According to some implementations, the data pad connected to the data registers disposed on respective sides of one multiplexer therebetween may be connected to one interposer pad.

For example, the first_0data pad dp1_0connected to the 0-th data register291_0and the first_1data pad dp1_1connected to the first data register291_1may correspond to the first_x data pad dp1_xand the first_y data pad dp1_yofFIG.4, and the first_0data pad dp1_0and the first_1data pad dp1_1may be connected to one interposer pad disposed on the interposer30. Descriptions on the first_0data pad dp1_0and the first_1data pad dp1_1may be respectively applied to the even numbered first data pads dp1_0, . . . , dp1_2n−2 and the odd numbered first data pads dp1_1, . . . , dp1_2n−1.

The data input/output buffer295may synchronize the data DQ input/output by the memory controller20with data clocks WCK, and may distinguish the input data and the output data. According to some implementations, the data input/output buffer295may receive the mode signal MODE_SEL and may control an operation of an input or output interface.

According to some implementations, the memory cell array110, the row decoder120, and the sense amplifier170may be included in the memory die100, and the control logic circuit210, the address register220, the bank control logic230, the refresh control circuit245, the column address latch250, the row address multiplexer260, the column address latch250, the column decoder270, the input/output gating circuit290, and the data input/output buffer295may be included in the base die200.

FIG.9andFIG.10show timing diagrams on an operation of an example of a memory device.

A first operation mode of the memory device10ofFIG.1toFIG.8may be described with reference toFIG.9, and a second operation mode of the memory device10ofFIG.1toFIG.8may be described with reference toFIG.10.

Referring toFIG.7toFIG.9, before the 0-th time to, the mode signal MODE_SEL on a first level MODE1is input to the multiplexers292_0to292_n−1. The multiplexers292_0to292_n−1 of the memory device10may operate in a first operation mode based on the mode signal MODE_SEL at the first level MODE1. In the first operation mode, the multiplexers292_0to292_n−1 of the memory device10may output the data to the first burst length through the odd numbered first data pads dp1_1, . . . , dp1_2n−1 from among the first data pads.

For example, at the 0-th time to, a read command is input, and the first data DQ[1] and the 0-th data DQ[0] may be output with the burst length of 16 to the first_1data pad dp1_1from the first time t1to the third time t3.

From the first time t1to the second time t2, the first_1data register291_1may output the first data DQ[1] to the first_1data pad dp1_1through the data input/output buffer295, and the 0-th multiplexer292_0may provide the 0-th data DQ[0] provided to the first_0data register291_0to the first_1data register291_1.

From the second time t2to the third time t3, the 0-th data register291_0may not perform an output operation to the first_0data pad dp1_0. The first data register291_1may output the 0-th data DQ[0] provided by the 0-th multiplexer292_0to the first_1data pad dp1_1through the data input/output buffer295.

From the first time t1to the third time t3, descriptions on the operations of the 0-th data register291_0, the first data register291_1, and the 0-th multiplexer292_0may be applied to the even numbered first data registers291_0, . . . ,291_2n−2, the odd numbered first data registers291_1, . . . ,291_2n−1, and the multiplexers292_0to292_n−1. As described above, in the first operation mode, DQ[1] and DQ[0] may be output only through the first_1data pad dp1_1at, for example, the burst length of 16. The first operation mode may also be referred to as half-mode.

Referring toFIG.10, before the fourth time t4, the mode signal MODE_SEL on a second level MODE2may be input to the multiplexers292_0to292_n−1. The multiplexers292_0to292_n−1 of the memory device10may operate in a second operation mode based on the mode signal MODE_SEL at the second level MODE2. In the second operation mode, the multiplexers292_0to292_n−1 of the memory device10may output the data with a second burst length that is less than the first burst length through the first data pads dp1_0to dp1_2n−1. According to some implementations, ratio of the second burst length and first burst length is 1 to n, and the n is an integer of equal to or greater than 2.

For example, at the fourth time t4, a read command is input, and after latency, the 0-th data DQ[0] and the first data DQ[1] may be output at the burst length of 8 on the first_0data pad dp1_0and the first_1data pad dp1_1, respectively, for the fifth time t5to the sixth time t6.

From the fifth time t5to the sixth time t6, the 0-th data register291_0may output the 0-th data DQ[0] to the first_0data pad dp1_0through the 0-th multiplexer292_0and the data input/output buffer295, and the first data register291_1may output the first data DQ[1] to the first_1data pad dp1_1through the data input/output buffer295.

From the fifth time t5to the sixth time t6, descriptions on the operations of the 0-th data register291_0, the first data register291_1, and the 0-th multiplexer292_0may be applied to the even numbered first data registers291_0, . . . ,291_2n−2, the odd numbered first data registers291_1, . . . ,291_2n−1, and the multiplexers292_0to292_n−1. As described above, in the second operation mode, DQ[1] and DQ[0] may be output at the burst length of 8 through the first_1data pad dp1_1and the first_0data pad dp1_0, respectively. The second operation mode may also be referred to as full-mode.

Referring toFIG.9andFIG.10, a first minimum burst section tCCD_M1in the first operation mode MODE1for the burst mode is twice a second minimum burst section tCCD_M2in the second operation mode MODE2for the burst mode. That is, the first burst mode (e.g., half-mode) of the first operation mode is twice as large as the second burst mode of the second operation mode (e.g., full-mode).

The device has been described to be operated in different operation mode depending on the level of the mode signal MODE_SEL, and the mode signal MODE_SEL for changing the operation mode of the multiplexers292_0to292_n−1 is not limited thereto.

The memory device10may adjust the bump for inputting/outputting data through the mode signal MODE_SEL without any change of the configuration, thereby universally exchanging data with external devices in the viewpoint of the number of the data bumps.

FIG.11shows a configuration of another example of a memory device.

The memory device10′ ofFIG.11may be described in comparison to the memory device10ofFIG.7, and their differences will be focused for ease of description. The configuration of the memory device10′ that is not described will be replaced with the description on the corresponding configuration of the memory device10ofFIG.7.

Referring toFIG.8andFIG.11, the input/output gating circuit290receives setting information SI on the burst mode MODE from the mode register212of the control logic circuit210, and the setting information SI is latched and is input to the multiplexers292_0to292_n−1, and the operations of the multiplexers292_0to292_n−1 may be controlled.

The multiplexers292_0to292_n−1 may determine the input/output data path according to the latched setting information SI.

FIG.12andFIG.13show timing diagrams on an operation of another example of a memory device.

The first operation mode MODE1of the memory device10′ ofFIG.11may be described with reference toFIG.12, and the second operation mode MODE2of the memory device10′ ofFIG.11may be described with reference toFIG.13.

Referring toFIG.11andFIG.13, for the seventh time t7that is before the eighth time t8, the memory controller20may perform a first mode register write MRW1operation for the burst mode MODE from among the setting of the mode register212. The first mode register write MRW1may correspond to the first operation mode MODE1ofFIG.9. The setting information SI to which the first mode register write MRW1operation is performed may be input to the multiplexers292_0to292_n−1 in substitute for the mode signal MODE_SEL ofFIG.8. The multiplexers292_0to292_n−1 to which the setting information SI is input may be operable in a similar way to the multiplexers292_0to292_n−1 to which the mode signal MODE_SEL on the first level MODE1shown inFIG.8andFIG.9is input.

Descriptions on the operations of the first data registers291_0to291_2n−1 and the multiplexers292_0to292_n−1 for the eighth time t8to the eleventh time t11may be replaced with the descriptions of the operations of the first data registers291_0to291_2n−1 and the multiplexers292_0to292_n−1 for the 0-th time to to the third time t3ofFIG.9.

For the twelfth time t12that is before the thirteenth time t13, the memory controller20may perform a second mode register write MRW2operation on the burst mode MODE from among the setting of the mode register212. The second mode register write MRW2may correspond to the second operation mode MODE2ofFIG.10. The setting information SI to which the second mode register write MRW2operation is performed may be substituted with the mode signal MODE_SEL ofFIG.8and may be input to the multiplexers292_0to292_n−1. The multiplexers292_0to292_n−1 to which the setting information SI is input may be operable in a similar way to the multiplexers292_0to292_n−1 to which the mode signal MODE_SEL on the second level MODE2ofFIG.8andFIG.10is input.

Descriptions on the operations of the first data registers291_0to291_2n−1 and the multiplexers292_0to292_n−1 for the thirteenth time t13to the fifteenth time t15may be replaced with the descriptions of the operations of the first data registers291_0to291_2n−1 and the multiplexers292_0to292_n−1 for the 0-th time to to the third time t3ofFIG.10.

FIG.14toFIG.16show another example of a memory system.

The memory device10″ and the memory controller20″ ofFIG.14toFIG.16may be described in comparison to the memory device10and the memory controller20ofFIG.4,FIG.6, andFIG.8, and their differences will be focused for ease of description. The configurations of the memory device10″ and the memory controller20″ that are not described will be replaced with the description on the corresponding configurations of the memory device10and the memory controller20ofFIG.4,FIG.6, andFIG.8.

The first data bumps db1may respectively include a data pad. For example, the first_x, first_y, first_z, and first_w data bumps db1_x, db1_y, db1_z, and db1_wincluded in the first data bumps db1may include the first_x, first_y,1first_z, first_w data pads db1_x, db1_y, db1_z, and db1_w. Further, the second data bumps db2″ may respectively include a data pad. For example, the second_a data bump db2_aincluded in the second data bump db2″ may include a second_a data pad dp2_a.

The first data bumps db1and the second data bumps db2″ may be electrically connected through the interposer pads FP_x and FP_a and the data line dl_a dispose on an upper side of the interposer30. According to some implementations, the included first_x, first_y, first_z, and first_w data bumps db1_x, db1_y, db1_z, and db1_wmay be connected to an x-th interposer pad FP_x, and the x-th interposer pad FP_x may be connected to the a-th data line dl_a and the a-th interposer pad FP_a to transmit/receive data to/from the second_a data pad dp2_a.

As shown inFIG.14, the ratio of the number of the data lines dl and the number of the first data bumps db1may be 1 to 4, and the ratio of the number of the second data bumps db2″ and the number of the first data bumps db1may be 1 to 4.

The input/output gating circuit290″ may include data registers291″_0to291″_4m-1. The respective data registers291″_0to290″_4m-1may input/output the data DQ[0] to DQ[4m-1] to/from the first data pads dp1_0to dp1_4m-1through the data input/output buffer295. According to some implementations, 2n ofFIG.8may be equal to 4m ofFIG.16.

In the present disclosure, the multiplexers292″_0, . . . ,292″_4m-2may determine the data path input/output according to the input mode signal MODE_SEL. Further, the multiplexers292″_0, . . . ,292″_4m-2may be operable as multiplexers or demultiplexers according to the operation of the memory device10.

According to some implementations, the data pads connected to the four data registers disposed with the multiplexer therebetween may be connected to the interposer pad.

For example, the first_0data pad dp1_0connected to the 0-th data register291″_0, the first_1data pad dp1_1connected to the first data register291″_1, the first_2data pad dp1_2connected to the second data register291″_2, and the first_3data pad dp1_3connected to the third data register291″_3may correspond to the first_x data pad dp1_x, the first_y data pad dp1_y, the first_z data pad dp1_z, and the first_w data pad dp1_wofFIG.14, and the first_0data pad dp1_0, the first_1data pad dp1_1, the first_2data pad dp1_2, and the first_3data pad dp1_3may be connected to one interposer pad disposed on the interposer30. Descriptions on the first_0data pad dp1_0, the first_1data pad dp1_1, the first_2data pad dp1_2, and the first_3data pad dp1_3may be applied to the 4X-th first data pads dp1_0, . . . , dp1_4m-4, the (4X+1)-th first data pads dp1_1, . . . , dp1_4m-3, the (4X+2)-th first data pads dp1_2, . . . , dp1_4m-2, and the (4X+3)-th first data pads dp1_3, . . . , dp1_4m-1. The X may be an integer of equal to or greater than 0, and may be less than m.

FIG.17andFIG.18show timing diagrams on an operation of another example of a memory device.

The first operation mode of the memory device10″ ofFIG.14toFIG.16may be described with reference toFIG.17, and the second operation mode of the memory device10″ ofFIG.14toFIG.16may be described with reference toFIG.18.

Referring toFIG.14toFIG.18, before the sixteenth time t16, the mode signal MODE_SEL on the first level MODE1may be input to the multiplexers292″_0, . . . ,292″_4m-2. The multiplexers292″_0, . . . ,292″_4m-2of the memory device10″ may be operable in the first operation mode based on the mode signal MODE_SEL on the first level MODE1. In the first operation mode, the multiplexers292″_0, . . . ,292″_4m-2of the memory device10may output the data with the first burst length through the (4X+3)-th first data pads dp1_3, . . . , dp1_4m-1from among the first data pads.

For the seventeenth time t17, a read command is input, and after latency, the third data DQ[3], the second data DQ[2], the first data DQ[1], and the 0-th data DQ[0] may be output with the burst length of 32 on the first_3data pad dp1_3for the seventeenth time t17to the twenty-first time t21.

For the seventeenth time t17to the eighteenth time t18, the third data register291″_3may output the third data DQ[3] to the first_3data pad dp1_3through the data input/output buffer295, the second multiplexer292″_2may output the second data DQ[2] provided by the second data register291″_2to the third data register291″_3, the first multiplexer292″_1may output the first data DQ[1] provided by the first data register291″_1to the second data register291″_2, and the 0-th multiplexer292″_0may output the 0-th data DQ[0] provided by the 0-th data register291″_0to the first data register291″1.

For the eighteenth time t18to the nineteenth time t19, the third data register291″_3may output the second data DQ[2] to the first_3data pad dp1_3through the data input/output buffer295, the second multiplexer292″_2may output the first data DQ[1] provided by the second data register291″_2to the third data register291″_3, and the first multiplexer292″_1may output the 0-th data DQ[0] provided by the first data register291″_1to the second data register291″_2.

For the nineteenth time t19to the twentieth time t20, the third data register291″_3may output the first data DQ[1] to the first_3data pad dp1_3through the data input/output buffer295, and the second multiplexer292″_2may output the 0-th data DQ[0] provided by the second data register291″_2to the third data register291″_3.

For the twentieth time t20to the twenty-first time t21, the third data register291″_3may output the 0-th data DQ[0] to the first_3data pad dp1_3through the data input/output buffer295.

For the eighteenth time t18to the twenty-first time t21, the 0-th data register291_0may not perform an output operation to the first_0data pad dp1_0. For the nineteenth time t19to the twenty-first time t21, the first data register291_1may not perform an output operation to the first_1data pad dp1_1. For the twentieth time t20to the twenty-first time t21, the second data register291_2may not perform an output operation to the first_2data pad dp1_2.

For the seventeenth time t17to the twenty-first time t21, descriptions on the operations of the 0-th data register291″_0, the first_1data register291″_1, the second data register291″_2, the third data register291″_3, the 0-th multiplexer292″_0, the second multiplexer292_1, and the second multiplexer292″_2may be respectively applied to the 4X-th first data registers291″_0, . . . ,291″_4m-4, the (4X+1)-th first data registers291″_1, . . . ,291″_4m-3, the (4X+2)-th first data registers291″_2, . . . ,291″_4m-2, the (4X+3)-th first data registers291″_3, . . . ,291″_4m-1, the 4X-th multiplexers292″_0, . . . ,292″_4m-4, the (4X+1)-th multiplexers292″_1, . . . ,292″_4m-3, and the (4X+2)-th multiplexers292″_2, . . . ,292″_4m-2. The X may be an integer of equal to or greater than 0, and may be less than m.

Before the twenty-second time t22, the mode signal MODE_SEL on the second level MODE2may be input to the multiplexers292″_0, . . . ,292″_4m-2. The multiplexers292″_0, . . . ,292″_4m-2of the memory device10″ may be operable in the second operation mode based on the mode signal MODE_SEL on the second level MODE2. In the second operation mode, the multiplexers292″_0, . . . ,292″_4m-2of the memory device10″ may output the data with the second burst length that is less than the first burst length through the first data pads dp1_0to dp1_4m-1.

For the twenty-second time t22, a read command is input, an after latency, the 0-th data DQ[0], the first data DQ[1], the second data DQ[2], and the third data DQ[3] may be output with the burst length of 8 on the first_0data pad dp1_0, the first_1data pad dp1_1, the first_2data pad dp1_2, and the first_3data pad dp1_3for the twenty-third time t23to the twenty-fourth time t24.

For the twenty-third time t23to the twenty-fourth time t24, the 0-th data register291″_0may output the 0-th data DQ[0] to the first_0data pad dp1_0through the 0-th multiplexer292″_0and the data input/output buffer295, the first_1data register291″_1may output the first data DQ[1] to the first_1data pad dp1_1through the first multiplexer292″_1and the data input/output buffer295, the second data register291″_2may output the second data DQ[2] to the first_2data pad dp1_2through the second multiplexer292″_2and the data input/output buffer295, and the third data register291″_3may output the third data DQ[3] to the first_3data pad dp1_3through the data input/output buffer295.

For the twenty-third time t23to the twenty-fourth time t24, descriptions on the operations of the 0-th data register291″_0, the first data register291″_1, the second data register291″_2, the third data register291″_3, the 0-th multiplexer292″_0, the second multiplexer292_1, and the second multiplexer292″_2may be respectively applied to the 4X-th first data registers291″_0, . . . ,291″_4m-4, the (4X+1)-th first data registers291″_1, . . . ,291″_4m-3, the (4X+2)-th first data registers291″_2, . . . ,291″_4m-2, the (4X+3)-th first data registers291″_3, . . . ,291″_4m-1, the 4X-th multiplexers292″_0, . . . ,292″_4m-4, the (4X+1)-th multiplexers292″_1, . . . ,292″_4m-3, and the (4X+2)-th multiplexers292″_2, . . . ,292″_4m-2. The X may be an integer of equal to or greater than 0, and may be less than m.

Referring toFIG.17andFIG.18, a first minimum burst section tCCD_M1″ in the first operation mode MODE1for the burst mode is four times a second minimum burst section tCCD_M2″ in the second operation mode MODE2for the burst mode.

FIG.19shows another example of a memory system.

A base die200cofFIG.19may be described in comparison to the base die200ofFIG.5, and their differences will be focused for ease of description. The configuration of the base die200cthat is not described will be replaced with the description on the corresponding configuration of the base die200ofFIG.5.

Referring toFIG.19, the first direct access bumps dab of the base die200cincludes a mode bump MoB for receiving the mode signal MODE_SEL, and the operation mode on the burst mode of the memory device is controlled without intervention of the memory controller.

FIG.20shows another example of a memory system.

A memory system1dofFIG.20may be described in comparison to the memory system1ofFIG.1andFIG.2, and their differences will be focused for ease of description. The configuration of the memory system1dthat is not described will be replaced with the description on the corresponding configuration of the memory system1ofFIG.1andFIG.2.

Referring toFIG.20, the memory system1dis manufactured with a 3D package. The memory device10dof the memory system1dmay be disposed on the upper side of the memory controller20dwithout disposing an additional interposer with respect to the third direction Z.

That is, the first direct access bumps dab, the first power bumps pb1, the first command and address bumps cab1, and the first data bumps db1may be disposed on the upper side of the memory controller20d.

The first direct access bumps dab and the second direct access bumps DAFB may be connected to each other in the memory controller20d. The first power bumps pb1and the third power bumps PBFB may be connected to each other in the memory controller20d.

The memory controller20dmay receive control signals and data through the second control signal bumps CDFB, and may transmit channel commands, addresses, and channel data to the first command and address bumps cab1and the first data bumps db1.

The memory system according to some implementations may universally exchange data with external devices through the mode signal without any change of the configuration in the viewpoint of the number of the data input/output bumps.

The memory system according to some implementations may adjust the number of the actually operated data input/output bumps from among the data input/output bumps to ease requisites of the size and the pitch of the configuration for the external device, and may reduce the cost for the process relating to the size and the pitch of the configuration for the external device.

FIG.21shows a perspective view of a configuration of an example of a system device to which a memory system is applied.

Referring toFIG.21, the system device1000is a semiconductor package, and may be a memory module including at least one memory device1010installed on the package substrate1040such as a printed circuit board and a system-on-chip (SOC)1020.

An interposer1030may be selectively further provided on the package substrate1040. The memory device1010may be formed in a chip-on-chip (CoC) type. The memory device1010may include a memory die1100including at least one core die stacked on the base die1200. The memory die1100and the base die1200may be connected to each other by a through silicon via (TSV).

The base die1200may include an input/output gating circuit and a data input/output buffer for gating input/output data of the memory die1100, and the base die1200may control the operation of the input/output gating circuit and the data input/output buffer according to the mode signal of the externally input to thus adjust the number of the data bumps for inputting/outputting data to/from the system-on-chip1020. The input/output gating circuit and the data input/output buffer may perform the memory operation when the implementations described with reference toFIG.1toFIG.20are applied.

The memory device1010may, for example, be a high bandwidth memory (HBM) of equal to or greater than 500 GB/sec to 1 TB/sec.

FIG.22shows a perspective view of another example of a system device to which a memory system is applied.

Referring toFIG.22, the system device2000is a dual in-line memory module (DIMM) system in which semiconductor chips are installed on respective sides of the printed circuit board, and it may include a memory module2002including at least one PCB2030and a memory controller2020. The memory controller2020may be mounted on the main board2040, and the PCB2030may be electrically connected to the main board2040through connecting sockets.

The memory device2010may be formed in the chip-on-chip (CoC) type, and may be mounted on the respective sides of the PCB2030. The memory controller2020and the memory device2010may be electrically connected to each other through the PCB2030and the bus in the main board2040. According to some implementations, the memory device2010may have a stacking structure of the memory die and the base die.

The base die may include the input/output gating circuit and the data input/output buffer, and the base die may control the operations of the input/output gating circuit and the data input/output buffer according to the mode signal input to the outside, and may adjust the number of the data bumps for inputting/outputting data to/from the memory controller2020. The input/output gating circuit and the data input/output buffer may perform the memory operation when the implementations described with reference toFIG.1toFIG.20are applied. The implementations described with reference toFIG.1toFIG.20are applied to perform the memory operation.

The memory device2010may, for example, be the high bandwidth memory (HBM) of equal to or greater than 500 GB/sec to 1 TB/sec.

While this disclosure has been described in connection with what is presently considered to be practical implementations, it is to be understood that the disclosure is not limited to the disclosed implementations and/or the examples, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.