EEPROM device having selecting transistors and method of fabricating the same

An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

This application claims the priority of Korean Patent Application No. 2003-47972, filed on Jul. 14, 2003 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor memory devices, more specifically, to an EEPROM including a selection transistor, and a method of fabricating the same.

2. Description of the Related Art

Electrically erasable and programmable read only memory (EEPROM) is a memory device for electrically memorizing and erasing data and includes a flash memory device and a FLOTOX memory device representatively. The FLOTOX memory device includes a memory cell composed of two transistors (i.e., a memory transistor and a selection transistor). In contrast, the flash memory device includes a memory cell composed of one transistor. A cell array of the flash memory devices is categorized as a NAND type and a NOR type according to the arrangement of memory cells. Cell strings are disposed parallel in the NAND type cell array and are composed of a plurality of memory cells that are connected to each other in series. The cell string of a NAND type cell array includes selection transistors at both edges thereof similar to a FLOTOX memory device. However, the selection transistor of a NAND type flash memory device selects a cell string whereas the selection transistor of a FLOTOX memory device selects a memory cell.

An insulation layer is interposed between a lower conductive layer and an upper conductive layer in a stacked formation in the transistors of an EEPROM cell. The upper conductive layer and the lower conductive layer of the memory cell should be electrically insulated from each other in order to store data. However, the lower conductive layer of the selection transistor should be electrically connected to the upper conductive layer thereof. Therefore, various structures for connecting the lower conductive layer to the upper conductive layer in the selection transistor have been proposed. EEPROM memory devices including a selection transistor are disclosed in U.S. Pat. No. 4,780,431 and U.S. Pat. No. 6,221,717.

FIG. 1is a top plan view illustrating a portion of cell arrays of a conventional NAND type flash memory device.

Referring toFIG. 1, a device isolation layer2is disposed in a semiconductor substrate to dispose a plurality of active regions4. A string selection line SSL, a ground selection line GSL and a plurality of word lines WL are placed to extend across the active regions4. A memory cell unit is composed of the string selection line SSL, the ground selection line GSL and the plurality of word lines WL therebetween. The NAND type cell array comprises a plurality of memory cell units in symmetrically repeated arrangement. A common source line CSL is disposed between the neighboring ground selection lines GSL for electrically connecting the active regions4, and a bit line plug44that is disposed on each of the active region4between the neighboring string selection lines SSL.

The word line WL includes a control gate pattern49extending across the active regions4and a floating gate34formed on each of the active regions4. The ground selection line GSL and the string selection line SSL include a lower gate pattern24and a selection gate pattern30in a sequentially stacked form. Contrary to this, the selection gate pattern30should be electrically connected to the lower gate pattern24. Conventionally, the selection gate pattern30is connected to lower gate pattern24by a butting contact or by removing a portion of the inter-gate dielectric layer formed between the selection gate pattern30and the lower gate pattern24.

FIGS. 2 and 3are cross-sectional views taken along line I–I′ ofFIG. 1illustrating a method for forming a conventional EEPROM.

Referring toFIG. 2, a gate insulation layer and a first conductive layer are formed on the semiconductor substrate10. Then, the first conductive layer is patterned to form a first conductive pattern14. An inter-gate dielectric layer16and a mask conductive layer18are sequentially formed on the semiconductor substrate including the first conductive pattern14. The mask conductive layer18and the inter-gate dielectric layer16are successively patterned to form an opening20exposing the first conductive pattern14. As not illustrated in the drawings, the opening20extends across the active regions2. The opening20may be formed on the center of region S where the selection line is formed.

Referring toFIG. 3, a second conductive layer is formed on the mask conductive layer18with the opening20. The second conductive layer, the mask conductive layer18, the inter-gate dielectric layer16aand the first conductive pattern14are successively patterned to form a word line WL and the selection line SL. The word line WL includes a floating gate34, an inter-gate dielectric pattern36, a mask conductive pattern38and a control gate pattern40in a sequentially stacked form. The selection line SL includes a lower gate pattern24, a dummy dielectric pattern26, a mask conductive pattern28and a selection gate pattern30. The floating gate pattern34and the control gate pattern40are electrically insulated from each other but the lower gate pattern24and the selection gate pattern30are electrically connected through the opening20. The opening20may be formed to have a width of, for example, half a line width L of the selection line SL. In this case, a misalignment tolerance of the opening20and the selection line SL is L/4.

FIGS. 4 and 5are cross-sectional views illustrating problems of the prior art.

Referring toFIG. 4, if the opening20or the selection line SL is misaligned, a portion46of the opening20misses the selection line region S.

Referring toFIG. 5, the second conductive layer is formed, and the second conductive layer and the mask conductive layer are patterned using the inter-gate dielectric layer16as an etch stop layer to form a control gate pattern40, a selection gate pattern30and mask conductive patterns28and38. In this case, the first conductive pattern14missing the selection line region S is removed from the opening region46to expose the gate insulation layer12.

Referring toFIG. 6, the inter-gate dielectric layer16and the first conductive pattern14are patterned to form a floating gate34, a lower gate pattern24and an inter-gate dielectric pattern36and a dummy dielectric pattern26. In this case, the semiconductor substrate in the opening region20may be damaged by the etching. For example, a notch48can be formed adjacent the selection line SL.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide EEPROMs having high integration density achieved by electrically connecting an upper conductive layer and a lower conductive layer of a selection line through an opening of a dielectric layer intervening between the conductive layers and methods of fabricating the same.

Other embodiments of the present invention provide EEPROMs having high tolerance with respect to a mis-alignment between the opening and the selection line and methods of the same.

In some embodiments of the present invention, an EEPROM device includes a dummy dielectric pattern that is formed between a lower gate pattern and a selection gate pattern and is self-aligned with one sidewall of a selection gate pattern to overlap a predetermined width of the selection gate pattern.

In these embodiments, The EEPROM device includes a device isolation layer for defining a plurality of active regions, a pair of control gate patterns extending across the active regions, and a pair of selection gate patterns extending across the active regions between and parallel the control gate patterns. Floating gate patterns are formed at an intersection region where the control gate patterns extend across the active regions. Lower gate patterns are formed at an intersection region where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is parallel to the selection gate pattern and self-aligned with one sidewall of the selection gate pattern to overlap a predetermined width of the selection gate pattern. Therefore, the selection gate pattern is electrically connected to the lower gate patterns under the selection gate pattern.

Mask conductive patterns may be further interposed between the inter-gate dielectric pattern and the control gate pattern and between the dummy dielectric pattern and the selection gate pattern, respectively.

The present invention may be adapted to a flash EEPROM device with a NAND type cell array.

The flash EEPROM device includes a device isolation layer for defining a plurality of active regions, a pair of selection gate patterns extending across the active regions, and a plurality of parallel control gate patterns that are disposed to extend across the active regions between and parallel the selection gate patterns. Floating gate patterns are formed at an intersection region where the control gate patterns extend across the active regions, and lower gate patterns are formed at an intersection region where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is parallel to the selection gate pattern and self-aligned with one sidewall of the selection gate pattern to overlap a predetermined width of the selection gate pattern.

A cell array of the flash EEPROM may include a plurality of unit cell blocks. Each of the unit cell blocks include a pair of selection gate patterns and a plurality of control gate patterns therebetween. The selection gate pattern of the unit cell block faces a second selection gate pattern of a neighboring unit cell block. A portion of the selection gate pattern facing the second selection gate is connected to a lower gate pattern thereunder.

In some embodiments of the present invention, there is a method of fabricating an EEPROM device including a dummy dielectric pattern that is formed between a lower gate pattern and selection gate pattern and self-aligned with one sidewall of a selection gate pattern to overlap a predetermined width of the selection gate pattern.

The method includes forming a device isolation layer in a semiconductor substrate to define a plurality of active regions and forming a lower conductive pattern on each active region, wherein the lower conductive pattern extends to a portion of the device isolation layer parallel to the active region. A dielectric pattern is formed on the lower conductive pattern to include an opening extending across the active region and an upper conductive layer is formed on the dielectric pattern. The upper conductive layer and the dielectric pattern are successively patterned to form a control gate pattern extending across the active region and a selection gate pattern overlapping one sidewall of the opening, an inter-gate dielectric pattern self-aligned with the control gate pattern and a dummy dielectric pattern that is self-aligned with the one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern. Then, the lower conductive pattern is patterned to form a lower gate pattern aligned with the selection gate pattern and a floating gate pattern self-aligned with the control gate pattern.

A dielectric layer and a mask conductive layer are sequentially formed on the entire surface of the semiconductor substrate including the lower conductive pattern, and patterned successively to form an opening extending across the active region.

In some embodiments of the present invention, at least one pair of control gate patterns may be formed to extend across the active region, and a pair of selection gate patterns may be formed between each pair of control gate patterns to extend across the active regions. The opening overlaps a predetermine width of one of the two selection gate patterns in one direction and overlaps a predetermined width of the other selection gate pattern in the opposite direction.

In other embodiments of the present invention, a pair of selection gate patterns may be formed to extend across the active regions, and a plurality of parallel control gate patterns are formed between the pair of selection gate patterns to extend across the active regions. The opening extends toward the control gate patterns and overlaps a predetermined width of the selection gates. The device consists of a plurality of unit cell blocks including a pair of selection gate patterns and the control gate patterns between the pair of selection gate patterns. The selection gate patterns in each of the unit cell blocks may be formed to face another selection gate patterns in neighboring unit cell blocks. The opening overlaps a predetermine width of one of the selection gate patterns facing each other in one direction and overlaps a predetermined width of the other selection gate pattern in the opposite direction.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 7Bis a cross-sectional view taken along line II–II′ ofFIG. 7Aillustrating an EEPROM device according to the first embodiment of the present invention.

Referring toFIGS. 7A and 7B, the EEPROM device according to the fist embodiment of the present invention includes a device isolation layer56that is formed in a semiconductor substrate50to define a plurality of active regions52. A pair of control gate patterns68bextend across the active regions52. A pair of selection gate patterns68aare located between the control gate patterns68b. Floating gate patterns60bare disposed at the intersection region where the control gate patterns68bextend across the active regions52. The floating gate patterns60beach intervene between the active regions52and the control gate patterns68b. An inter-gate dielectric pattern62bis interposed between the floating gate pattern60band the control gate pattern68b. The inter-gate dielectric pattern62bextends across the active regions52being self-aligned with the control gate pattern68b. Lower gate patterns60aare placed at the intersection region where the selection gate patterns68aextend across the active regions52. The lower gate patterns60aeach intervene between the active regions52and the selection gate patterns68a. A dummy dielectric pattern62ais disposed between the lower gate pattern60aand the selection gate pattern68a. The dummy dielectric pattern62ahas a width narrower than that of the selection gate pattern68a. The dummy dielectric pattern62aalso has sidewalls aligned with one sidewall of the selection gate pattern68a. The dummy dielectric pattern62aruns over the active region52parallel to the selection gate pattern68aand overlaps a portion of the selection gate pattern68awhile aligned with the selection gate pattern68a. Therefore, each selection gate pattern68ais electrically connected to the lower gate patterns60athereunder. The dummy dielectric pattern62ais aligned with the sidewall of selection gate pattern68athat faces the control gate pattern68b. A mask conductive pattern64bis disposed between the inter-gate dielectric pattern62band the control gate pattern68b, and aligns itself with the inter-gate dielectric pattern62b. The mask conductive pattern64aalso is disposed between the dummy dielectric pattern62aand the selection gate pattern68a, and the mask conductive pattern64aaligns itself with the dummy dielectric pattern62a. A first gate insulation layer58bis disposed between the floating gate pattern60band the active region52, and a second gate insulation layer58ais disposed between the lower gate pattern60aand the second gate insulation layer58a. The first gate insulation layer58bincludes a thin region where charges are capable of tunneling.

As illustrated in the drawings, the pair of control gate patterns68band the pair of selection gate patterns68acomposes a unit cell block repeatedly arranged on the semiconductor substrate50. A second plurality of active regions54may be further formed between the unit cell blocks to perpendicularly cross the active regions52. The second active regions54may become common source regions. In addition, lower gate patterns connected to the same selection gate pattern are disposed apart from each other on the device isolation layer56.

FIG. 8AthroughFIG. 110Aare top plan views illustrating a method of fabricating an EEPROM device according to the first embodiment of the present invention.

FIG. 8BthroughFIG. 101Bare cross-sectional views each taken along line of II–II′ ofFIG. 8A through 10Billustrating a method of fabricating an EEPROM device according to the first embodiment of the present invention.

Referring toFIGS. 8A and 8B, a device isolation layer56is formed to define a plurality of active regions52. In this case, a second plurality of active regions54may be additionally formed, which cross the active regions52perpendicularly and become a common source region in a subsequent process. A gate insulation layer and a lower conductive layer are formed on the semiconductor substrate50. The lower conductive layer is patterned to form a plurality of lower conductive patterns60. The lower conductive pattern is disposed on the corresponding active region52. The lower conductive pattern60overlaps a portion of the device isolation layer56adjacent the active region52.

Although not shown in the drawings, the gate insulation layer may be formed to include a thin region where charges are capable of tunneling under the floating gate that will be formed.

Referring toFIGS. 9A and 9B, a dielectric pattern62is formed overlying the lower conductive pattern60and has an opening66extending across the active regions52. The dielectric pattern62is formed by stacking a dielectric layer and a mask conductive layer on the substrate and by patterning the mask conductive layer and the dielectric layer successively. Therefore, a mask conductive layer64may be formed on the dielectric pattern62.

The opening66is formed to overlap a predetermined width of one neighboring selection gate pattern68ain one direction, and to overlap a predetermined width of the other neighboring selection gate pattern68ain the opposite direction. (SeeFIG. 7)

Referring toFIGS. 10aand10b, an upper conductive layer68is formed over the resulting structure. The upper conductive layer68may be formed of the same material as the mask conductive layer64. Moreover, the upper conductive layer68may be formed to have a multi-layered structure including a high conduction layer such as a metal layer or a metal silicide layer.

The upper conductive layer68, the mask conductive layer64and the dielectric pattern62are successively patterned (not shown) to form a control gate pattern68band a selection gate pattern68athat extend across the active regions52(SeeFIG. 7). This patterning process also forms a mask conductive pattern64band an inter-gate dielectric pattern62baligned with the control gate pattern68b. In addition, a mask conductive pattern64aand a dummy dielectric pattern62aare formed. Preferably, one of the sidewall of the dummy dielectric pattern is aligned with the selection gate pattern68a.

Because the opening66is formed to overlap a portion of the selection gate pattern68a, the dielectric pattern62is not formed under the portion of selection gate pattern68a. Therefore, the dummy dielectric pattern62ahas a sidewall self-aligned with one sidewall of the selection gate pattern68aand overlaps a predetermine width of the selection gate pattern68a. Accordingly, only the sidewall of the dummy dielectric pattern62afacing the control gate pattern68bis aligned with one of the sidewalls of the selection gate pattern68a. As a result, the other sidewall of the selection gate pattern68afacing another neighboring selection gate pattern is directly aligned with (contacts) the sidewall of the lower conductive pattern60. Therefore, the sidewall of the dummy dielectric pattern62afacing the control gate pattern68bis exposed, while the other sidewall of the dummy dielectric pattern62ais not exposed. The lower conductive pattern60is patterned, as illustrated inFIGS. 7A and 7B, to form a floating gate pattern60bself-aligned with the control gate pattern68bat the intersection region where the control gate pattern68bextends across the active region52, and a lower gate pattern60aself aligned to the selection gate pattern68aat the region where the selection gate pattern68aextends across the active region52.

The present invention may be employed in flash EEPROM devices with a NAND type cell array structure.

FIG. 11Ais a top plan view illustrating an EEPROM according to a second embodiment of the present invention.

FIG. 11Bis a cross-sectional view taken along line III–III′ ofFIG. 11Aillustrating the EEPROM according to the second embodiment of the present invention.

Referring toFIGS. 11A and 11B, an EEPROM device according to the second embodiment of the present invention includes the device isolation layer56that is formed on a semiconductor substrate50to define a plurality of active regions52. A pair of selection gate patterns68aextend across the active regions52, and a plurality of control gate patterns68bare arranged in parallel between the selection gate patterns68ato extend across the active regions52. The floating gate patterns60bare disposed at the intersection region where the control gate patterns68bextend across the active regions52. The floating gate pattern60bis disposed between the active region52and the control gate pattern68b. An inter-gate dielectric pattern62bis disposed between the floating gate pattern60band the control gate pattern68b. The inter-gate dielectric pattern62bself-aligns with the control gate pattern68b. Lower gate patterns60aare disposed at the intersection region where the selection gate patterns68aextend across the active regions52. The lower gate pattern60ais disposed between the active region52and the selection gate pattern68a. A dummy dielectric pattern is disposed between the lower gate pattern60aand the selection gate pattern68a. The dummy dielectric pattern62ais narrower than the selection gate pattern68ain width and has a sidewall self aligned with one sidewall of the selection gate pattern68a. The dummy dielectric pattern62aextends across the active regions52and overlaps a portion of the selection gate pattern68a. The dummy dielectric pattern62ais self-aligned and parallel with the selection gate pattern68a. Therefore, each of the selection gate patterns68ais electrically connected to the lower gate pattern60athereunder. The dummy dielectric pattern62ais formed to self-align with a sidewall of the selection gate pattern68afacing the control gate pattern68b. A mask conductive pattern64bis disposed between the inter-gate dielectric pattern62band the control gate pattern68band self-aligns to the inter-gate dielectric pattern62b. The mask conductive pattern64aalso is disposed between the dummy conductive pattern62aand the selection gate pattern68aand aligns itself to the dummy dielectric pattern62a. A first gate insulation layer58bis disposed between the floating gate pattern60band the active region52, and a second gate insulation layer58ais disposed between the lower gate pattern60aand the active region52. The first gate insulation layer58bis a thin insulation layer where charges are capable of tunneling.

As illustrated in the drawings, the pair selection gate pattern68aand a plurality of control gate patterns68btherebetween compose a unit cell block repeated and arranged on the semiconductor substrate. A second plurality of active regions54may be further formed to neighbor and parallel one of the selection gate patterns68ain each cell block. A common source region may be formed by doping into the second active regions54with impurities. To the contrary, a common source region may be formed with a conductive pattern corresponding to the common source region and electrically connected to each active region52without the active region parallel to the gate patterns. In a NAND type cell array, the selection gate pattern68ais disposed to face a selection gate pattern68ain a neighboring cell block. The lower gate patterns connected to the same selection gate pattern are placed apart from each other on the device isolation layer.

FIG. 12AthroughFIG. 14Aare top plan views illustrating a method of fabricating an EEPROM device according to the second embodiment of the present invention.

FIG. 12BthroughFIG. 14Bare cross-sectional views each taken along line III–III′ ofFIG. 12A through 14Aillustrating a method of fabricating an EEPROM according to the second embodiment of the present.

Referring toFIG. 12AandFIG. 12b, a device isolation layer56is formed on a plurality of active regions52. In this case, a second plurality of active regions54may be further formed to cross the active regions52. The second active regions54will be the regions where common source regions are formed in a subsequent process. A gate insulation layer and a lower conductive layer are formed on the entire surface of the semiconductor substrate50and the lower conductive layer is patterned to form a plurality of lower conductive patterns60. The lower conductive patterns60each correspond with the active regions52. The lower conductive pattern60is placed on the corresponding active region. The lower conductive pattern60overlaps a portion of the device isolation layers adjacent the corresponding active region52.

While forming, the lower conductive pattern60may be formed to extend across the active regions52and to be connected in the region where selection gate patterns will be formed. In this case, the lower conductive patterns60may be formed apart from each other on the device isolation layer56because the connected portions of the lower conductive patterns60may be deformed due to a proximity effect.

Referring toFIGS. 13A and 13B, a dielectric pattern62is formed on the entire surface of the substrate including the lower conductive pattern60to have an opening66extending across the active regions52. The dielectric pattern62may be formed by stacking a dielectric layer and a mask conductive layer on the entire surface of the substrate and successively patterning the mask conductive layer and the dielectric layer. Therefore, a mask conductive layer64may be formed on the dielectric pattern62.

The opening66is formed to overlap a predetermined region of one neighboring selection gate pattern68ain one direction and to overlap a predetermined region of another neighboring selection gate pattern68ain the opposite direction.

Referring toFIGS. 14aand14b, an upper conductive layer68is formed on the entire surface of the substrate. The upper conductive layer68may be formed of the same material as the mask conductive layer64. Moreover, the upper conductive layer68may be formed of multiple layers including a high conduction layer such as a metal layer or a metal silicide layer similar to conventional high-rate, low-voltage devices.

Although not shown in the drawings, the upper conductive layer68, the mask conductive layer64and the dielectric pattern62are successively patterned to form a control gate pattern68band a selection gate pattern68athat extend across the active regions52, a mask conductive pattern64band an inter-gate dielectric pattern62bthat self-align with the control gate pattern68b, and a mask conductive pattern64aand a dummy dielectric pattern62aof which sidewalls self-align with the selection gate pattern68a. The opening66is formed to overlap a portion of the selection gate pattern68a, such that a dielectric pattern62is not formed under the portion of the selection gate pattern68a. Therefore, the dummy dielectric pattern62ahas sidewall aligned with one sidewall of the selection gate pattern68aand overlaps a predetermined width of the selection gate pattern68a. The sidewall of the dummy dielectric pattern62afacing the control gate pattern68bis aligned with the one sidewall of the selection gate pattern68a. Thus, the other sidewall of the selection gate68afacing another neighboring selection gate pattern68acontacts the lower conductive pattern60directly. Continuously, the lower conductive pattern60is patterned to form a floating gate pattern60baligning itself with the control gate pattern68bat the region where the control gate pattern68bextends across the active region52, and to form a lower gate pattern60aself-aligning with the selection gate pattern68aat the region where the selection gate pattern68aextends across the active region52.

According to the present invention, a dummy dielectric pattern intervening between a selection gate pattern and a lower gate pattern has sidewall aligned with one sidewall of the selection gate pattern, and overlaps a predetermine portion of the selection gate pattern. The dummy dielectric pattern may be formed by etching a dielectric pattern to include an opening to self-align with the selection gate pattern. The opening overlaps the selection gate pattern in one direction, thereby having a higher mis-alignment margin then the prior art. Moreover, the lower gate patterns under the selection gate pattern are disposed apart from each other on the device isolation layer. When a continuous lower gate pattern is formed to extend across the active regions parallel to the selection gate pattern, the shape of a floating gate pattern adjacent the selection gate may be deformed because of a proximity effect of a photolithographic process. The structure according to the present invention, however, appears uniform distribution of cell characteristic without deterioration due to the proximity effect.