Apparatus for calibrating a time-interleaved analog-to-digital converter

An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes an analog signal generation circuit configured to generate an analog calibration signal based on a digital calibration signal representing one or more digital data sequences for calibration. The analog calibration signal is a wideband signal. Further, the apparatus includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the analog signal generation circuit or to a node capable of providing an analog signal for digitization.

FIELD

The present disclosure relates to analog-to-digital conversion. In particular, examples relate to an apparatus for calibrating a Time-Interleaved Analog-to-Digital Converter (TI-ADC), a receiver, a base station and a mobile device.

BACKGROUND

A TI-ADC employs several lower speed sub-ADCs operating in parallel in order to achieve a desired aggregate sampling rate. Thus, each sub-ADC may operate at a lower speed compared to when a single ADC would be used. Differences amongst sub-ADCs (e.g. caused by manufacturing tolerances) result in degraded performance in terms of noise Power Spectral Density (nPSD) and/or Spurious Free Dynamic Range (SFDR). Typical mismatches amongst the sub-ADCs include: DC offset, gain, timing skew/mismatch, frequency response and other nonlinear mismatches. The combined mismatches may be understood as a single time-variant nonlinear system with memory that degrades the performance of the TI-ADC in terms of nPSD and/or SFDR. Calibration is required in order to remove these undesired performance-degrading effects.

Hence, there may be a desire for a calibration architecture.

DETAILED DESCRIPTION

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, the elements may be directly connected or coupled or via one or more intervening elements. If two elements A and B are combined using an “or”, this is to be understood to disclose all possible combinations, i.e. only A, only B as well as A and B, if not explicitly or implicitly defined otherwise. An alternative wording for the same combinations is “at least one of A and B” or “A and/or B”. The same applies, mutatis mutandis, for combinations of more than two elements.

FIG. 1illustrates an example of an apparatus100for calibrating a TI-ADC130. The TI-ADC130comprises a plurality of time-interleaved ADC circuits. The plurality of time-interleaved ADC circuits may be any number N≥2 of time-interleaved ADC circuits (e.g. related to a desired total/aggregate sample rate of the TI-ADC130). The time-interleaved ADC circuits of the TI-ADC130may be understood as ADC channels or sub-ADCs of the TI-ADC130. An ADC circuit of the TI-ADC130may, e.g., be a Successive Approximation Register (SAR) ADC, a flash ADC (also referred to as direct conversion ADC), a pipeline ADC, a sigma-delta ADC or a time-interleaved ADC itself. If an ADC circuit is a time-interleaved ADC itself, it may comprise at least two sub-ADC circuits. A sub-ADC circuit may, e.g., be a SAR ADC, a flash ADC, a pipeline ADC or a sigma-delta ADC.

The apparatus100comprises an analog signal generation circuit110configured to generate an analog calibration signal111based on a digital calibration signal151representing one or more digital data sequences for calibration. As illustrated inFIG. 1, the digital calibration signal151representing one or more digital data sequences for calibration may be supplied to the analog signal generation circuit110by a digital calibration circuit150(e.g. a Digital Signal Processor, DSP) configured to generate the digital calibration signal151. For example, the analog signal generation circuit110may comprise a one or more Digital-to-Analog Converters (DACs), one or more filters, etc. for generating the analog calibration signal111based on the digital calibration signal151. A linearity of the analog signal generation circuit110may be higher than a desired (target) linearity of the TI-ADC130after calibration.

The analog calibration signal111is a wideband signal, i.e. a signal exhibiting a wide bandwidth. For example, a bandwidth of the analog calibration signal111may be less than half of a maximum value of the sample rate of the TI-ADC130. In other words, the analog calibration signal111may be bandlimited to half of the sample rate of the TI-ADC130in accordance with the Nyquist-Shannon sampling theorem. Further, amplitude values of the analog calibration signal111may cover all input amplitude values supported by the TI-ADC130. That is, the analog calibration signal111may cover the whole input amplitude range of the TI-ADC130. The analog calibration signal111may enable to fully characterize the TI-ADC mismatches as a time-variant nonlinear system and, hence, allow to calibrate the TI-ADC130.

Additionally, the apparatus100comprises a coupling circuit120configured to operably couple an input node131of the TI-ADC130to either the analog signal generation circuit110or to a signal node140capable of providing an analog signal for digitization. For example, the coupling circuit120may be configured to controllably couple the input node131of the TI-ADC130to either the analog signal generation circuit110or to the signal node140based on a control signal12. The control signal is indicative of the presently desired one of predetermined operation modes of the TI-ADC130. A first predetermined operation mode may be a calibration mode. If the TI-ADC130is to be calibrated (i.e. the TI-ADC130operates in a calibration mode), the coupling circuit120may couple the input node131of the TI-ADC130to the analog signal generation circuit110so that the analog calibration signal111is supplied as input to the TI-ADC130. A second predetermined operation mode may be a normal operation mode of the TI-ADC130to digitize analog data. If the TI-ADC130is to digitize an analog signal such as an analog Radio Frequency (RF) signal carrying user data (i.e. the TI-ADC130operates in a regular/normal operation mode), the coupling circuit120may couple the input node131of the TI-ADC130to the signal node140so that the analog signal is supplied as input to the TI-ADC130. For example, the coupling circuit120may be implemented using one or more switches (e.g. analog switches such as Metal-Oxide-Semiconductor, MOS, transistors) or one or more (programmable) attenuators (e.g. attenuating the analog calibration signal111if the TI-ADC130is to digitize an analog signal provided by the signal node140, and vice versa).

In the normal operation mode, the analog signal of the node140is input to the TI-ADC130and digitized such that the TI-ADC130provides a digital signal132at its output. An output circuit170receives the digital signal132and generates a digital output signal171based on the digital signal132using correction parameters161for correcting impairments and mismatches of the TI-ADC130.

In the calibration mode, the analog calibration signal111is fed to the TI-ADC130. A parameter determination circuit160receives the digital signal132output by the TI-ADC130and the digital calibration signal151as a reference. The parameter determination circuit160determines (computes) the correction parameters161for correcting the impairments and mismatches of the TI-ADC130based on the digital signal132output by the TI-ADC130and the digital calibration signal151.

The apparatus100may allow selective offline calibration of the TI-ADC130by selective coupling the input of the TI-ADC130to either the analog signal generation circuit110or to the signal node140. The apparatus100may enable simple generation of a linear bandlimited and wideband analog calibration signal111for calibration of the TI-ADC130. The wideband analog calibration signal111may allow to calibrate the TI-ADC130. The generation of the analog calibration signal111will be described below in detail with reference toFIGS. 2 to 4.

FIG. 2illustrates a more detailed example of an analog signal generation circuit210. The analog signal generation circuit210comprises a DAC212configured to generate an analog signal213based on the digital calibration signal151representing the one or more digital data sequences for calibration. Further, the analog signal generation circuit210comprises an analog filter214configured to generate the analog calibration signal111by filtering the analog signal213generated by the DAC212.

The analog signal generation circuit210illustrated inFIG. 2may be understood as a basic architecture (mechanism) for generating a linear and wideband and calibration signal111for calibrating a TI-ADC.

The analog filter214may comprise one or more analog sub-circuits for filtering the analog signal213generated by the DAC212and, hence, generating the analog calibration signal111. For example, the analog filter214may filter the analog signal213such that the resulting analog calibration signal111is bandlimited to less than half of the sample rate of the TI-ADC. The analog filter214may, e.g., comprise an analog Finite Impulse Response (FIR) filter (not illustrated inFIG. 2) configured to generate an auxiliary analog signal by filtering the analog signal213together with a passive analog filter (not illustrated inFIG. 2) that is coupled to the analog FIR filter and configured to generate the analog calibration signal111by filtering the auxiliary analog signal.

Regarding the DAC212, a DAC exhibiting a high resolution and operating at a high sample rate would simplify the analog filtering requirements. However, realizing a high linearity for such a multi-level DAC is costly. Further, for very high speed DACs (e.g. at a 16 GHz sample rate), oversampling may only be possible by time-interleaving several DACs. However, the time-interleaved DACs may also suffer from mismatches.

For reasons of simplicity and efficiency, the DAC212may, at least in some examples, exhibit a resolution of 1 bit. A DAC with 1 bit resolution is inherently linear so that the analog signal generation circuit210may exhibit high linearity. Similarly, the one or more digital data sequences represented by the digital calibration signal151may be 1 bit sequences.

The thus generated wideband analog calibration signal111may allow to jointly correct for all TI-ADC impairments and mismatches listed above such that an optimum performance TI-ADC calibration may be achieved. The proposed architecture for the analog signal generation circuit210may allow to generate a highly linear and wideband analog calibration signal111in a facilitated manner.

Another more sophisticated example of an analog signal generation circuit310is illustrated inFIG. 3. The analog signal generation circuit310comprises delay circuit320configured to iteratively delay a digital data sequence snrepresented by the digital calibration signal151for generating a plurality of delayed digital data sequences322-1, . . . ,322-N (a 1 bit sequence is used). In the example ofFIG. 3, the delay circuit310comprises a chain of delay elements321-1, . . . ,321-N configured to iteratively delay the digital data sequence sn. A delay time by which each of the delay elements321-1, . . . ,321-N delays its input is based on a control signal361. A Delay-Locked Loop (DLL)360is configured to supply the control signal361to the delay elements321-1, . . . ,321-N.

A reference clock signal365exhibiting a frequency FSequal to a data rate of the digital calibration signal151is iteratively delayed by a chain of delay elements362-1, . . . ,362-N of the DLL360. The phase of the output of the last delay element362-N of the chain is compared to the phase of the reference clock signal365by means of a phase detector circuit363. Based on the phase difference between the output of the last delay element362-N and the reference clock signal365, a phase error signal is generated and filtered by means of a loop filter364of the DLL. The output of the loop filter is the control signal361for the delay elements321-1, . . . ,321-N of the delay circuit320. For example, the control signal361may be a control voltage for adjusting the delay times of the delay elements321-1, . . . ,321-N. Also the delay times of the delay elements362-1, . . . ,362-N of the DLL360are controlled by the control signal361. For example, the delay elements321-1, . . . ,321-N and362-1, . . . ,362-N may be inverter circuits.

The delay time τ of the delay elements321-1, . . . ,321-N and362-1, . . . ,362-N is defined as follows in the example ofFIG. 3:

with 1/Tsdenoting a data rate of the digital calibration signal151, and D denoting a desired oversampling ratio for the digital calibration signal151. In other words, the digital calibration signal151is oversampled D times. The number N of delay elements may, in general, be equal to or greater than the desired oversampling ratio D. In the example ofFIG. 3, the number N of delay elements is chosen greater than desired oversampling ratio D.

It is to be noted that the data rate of the digital calibration signal151may be equal to or different from a value of the (maximum) sample rate of the TI-ADC to be calibrated.

In other words, the digital calibration signal151(i.e. the digital input to the analog signal generation circuit310) is passed through a delay line with a unit delay Ts/D. The delays are generated using, e.g., a chain of inverters with controlled delay, wherein the control voltage is derived from a DLL using similar delay elements.

Further, the analog signal generation circuit310comprises a plurality of DACs330-1, . . . ,330-N each configured to generate a respective analog signal331-1, . . . ,331-N based on one of the plurality of delayed digital data sequences322-1, . . . ,322-N. In the example ofFIG. 3, the DACs330-1, . . . ,330-N exhibit a resolution of 1 bit and generate the analog signals331-1, . . . ,331-N with different gains (weights). For example, the DAC330-1generates the analog signal331-1based on the delayed digital data sequence322-1using a first gain (weight) G1, whereas the DAC330-2generates the analog signal331-2based on the delayed digital data sequence322-2using a second gain (weight) G2.

The plurality of DACs330-1, . . . ,330-N are coupled to a combiner340configured to combine the analog signals331-1, . . . ,331-N generated by the plurality of DACs330-1, . . . ,330-N to an auxiliary analog signal341. A passive analog filter350(e.g. an RLC filter) is coupled to the combiner340and configured to generate the analog calibration signal111by filtering the auxiliary analog signal341.

In other words, a set of 1 bit DACs with different weights (Gi, I=1 . . . N) are connected (coupled) to the outputs of the delay elements, added together and passed through a passive analog filter. The combination of the delay circuit320and the plurality of DACs330-1, . . . ,330-N forms an analog discrete-time FIR filter at an oversampled rate D/Ts. This configuration may be advantageous since the 1 bit DACs are inherently linear (provided that the rise and fall times of the digital input are equal). Further, the passive analog filter350(e.g. an RLC filter) is also inherently linear. Any imperfections in the implementation of the unit delay TS/D and the gains Giare linear effects. Due to the use of oversampling and FIR filtering, the analog passive filter implementation may be simplified.

In alternative examples, the delay line may be retimed after every D delays since the output of the delay line after K·D delay elements is the digital data sequence sn-K(K≥1). Applied to the example ofFIG. 3, the delay circuit320would be configured to iteratively delay the digital data sequence sr, represented by the digital calibration signal151D times in order to generate D delayed digital data sequences322-1, . . . ,322-D. The plurality of DACs331-1, . . . ,331-D would process the delayed digital data sequences as described above. In addition, the analog signal generation circuit would comprise K further sets of delay circuits and DACs for generating further analog signals based on further digital data sequences sn-1, . . . , sn-Krepresented by the digital calibration signal151. For example, the analog signal generation circuit may additionally comprise a second delay circuit configured to iteratively delay a second digital data sequence sn-1represented by the digital calibration signal151for generating a plurality of delayed second digital data sequences (similarly to what is described above for the digital data sequence sn). Further, the analog signal generation circuit may additionally comprise a second plurality of DACs each configured to generate a respective second analog signal based on one of the plurality of delayed second digital data sequences (similarly to what is described above). The combiner340may then combine the analog signals generated by the plurality of DACs331-1, . . . ,331-D and the second analog signals generated by the second plurality of DACs to the auxiliary analog signal341.

The second delay circuit and the second plurality of DACs may be implemented and configured substantially similar to what is described above for the delay circuit320and the plurality of DACs330-1, . . . ,330-N. For example, the second plurality of DACs may be configured to generate the second analog signals with different gains. The delay circuit320and the second delay circuit may, e.g., be configured to iteratively delay the digital data sequence snand the second digital data sequence sn-1by the same delay time τ. The delay times of the delay circuit320and the second delay circuit may, e.g., be controlled by the same DLL.

An alternative analog signal generation circuit410is illustrated inFIG. 4. The analog signal generation circuit410uses flip-flops as sample circuits instead of an inverter delay line. In the example ofFIG. 4, an exemplary analog signal generation circuit for an oversampling ratio of D=4 is illustrated. However, it is to be noted that the oversampling ratio of D=4 is selected for illustrative purposes only and the proposed architecture is not limited to this specific oversampling ratio.

The analog signal generation circuit410comprises a plurality of sample circuits420-1, . . . ,420-4configured to generate a plurality of sampled signals421-1, . . . ,421-4by sampling a digital data sequence snrepresented by the digital calibration signal151based on different ones of a plurality of phase shifted clock signals401-1, . . . ,401-4. The number N of sample circuits is equal to the oversampling ratio D. An exemplary signal course for the digital data sequence snis illustrated in the lower part ofFIG. 4together with four exemplary signal courses for the phase shifted clock signals401-1, . . . ,401-4. Since the oversampling ratio D=4, the clock signals401-1, . . . ,401-4are phase shifted by 360°/4=90° with respect to each other.

Further, the analog signal generation circuit410comprises a plurality of DACs430-1, . . . ,430-4each configured to generate a respective analog signal431-1, . . . ,431-4based on one of the plurality of sampled signals421-1, . . . ,421-4. In the example ofFIG. 4, the DACs430-1, . . . ,430-4exhibit a resolution of 1 bit and generate the analog signals431-1, . . . ,431-4with different gains (weights). For example, the DAC430-1generates the analog signal431-1based on the sampled signal421-1using a first gain (weight) G1, whereas the DAC430-2generates the analog signal431-2based on the sampled signal421-2using a second gain (weight) G2.

The plurality of DACs430-1, . . . ,430-4are coupled to a combiner440configured to combine the analog signals431-1, . . . ,431-4generated by the plurality of DACs430-1, . . . ,430-4to an auxiliary analog signal441. A passive analog filter450(e.g. an RLC filter) is coupled to the combiner440and configured to generate the analog calibration signal111by filtering the auxiliary analog signal441.

For the K−1 further digital data sequences sn-1, . . . , sn-Krepresented by the digital calibration signal151(K≥1), the analog signal generation circuit410comprises K−1 further sets of sample circuits and DACs for generating further analog signals. For example, the analog signal generation circuit410comprises a second plurality of sample circuits460-1, . . . ,460-4configured to generate a second plurality of sampled signals461-1, . . . ,461-4by sampling a second digital data sequence sn-1represented by the digital calibration signal151based on different ones of the plurality of phase shifted clock signals401-1, . . . ,401-4. Further, the analog signal generation circuit410additionally comprises a second plurality of DACs470-1, . . . ,470-4each configured to generate a respective second analog signal471-1, . . . ,471-4based on one of the second plurality of sampled signals461-1, . . . ,461-4.

The second plurality of sample circuits460-1, . . . ,460-4and the second plurality of DACs470-1, . . . ,470-4may be implemented and configured substantially similar to what is described above for the plurality of sample circuits420-1, . . . ,420-4and the plurality of DACs430-1, . . . ,430-4. For example, the second plurality of DACs430-1, . . . ,430-4may be configured to generate the second analog signals with different gains.

The DACs of the analog signal generation circuit410may again exhibit a resolution of 1 bit so that the DACs are inherently linear. Further, the digital data sequences sn, . . . , sn-Krepresented by the digital calibration signal151may be 1 bit sequences.

The combination of the sample circuits and the DACs forms an analog discrete-time FIR filter at an oversampled rate D/TS. The implementation of the analog passive filter implementation may, hence, again be simplified due to the use of oversampling and FIR filtering.

An example of an implementation using ADC calibration according to one or more aspects of the architecture(s) described above or one or more examples described above is illustrated inFIG. 5.FIG. 5schematically illustrates an example of a radio base station500(e.g. for a femtocell, a picocell, a microcell or a macrocell) comprising an apparatus530for calibrating a TI-ADC520as proposed.

The TI-ADC520and the apparatus530for calibrating the TI-ADC520are part of a receiver510. The receiver510additionally comprises analog circuitry540configured to receive a RF receive signal from an antenna element560of the base station500. The analog circuitry540is further configured to supply the analog signal for digitization to the signal node of the apparatus530based on the RF receive signal. For example, the analog circuitry540may comprise one or more of a filter, a down-converter (mixer) or a Low Noise Amplifier (LNA).

Further, the base station500comprises a transmitter550configured to generate a RF transmit signal. The transmitter550may use the antenna element560or another antenna element (not illustrated) of the base station500for radiating the RF transmit signal to the environment.

To this end, a base station enabling improved offline calibration of the TI-ADC may be provided. Accordingly, a performance of the TI-ADC and, hence, the base station may be improved.

The base station500may comprise further elements such as, e.g., a baseband processor, an application processor, memory, a network controller, a user interface, power management circuitry, a satellite navigation receiver, a network interface controller or power tee circuitry.

In some aspects, the application processor may include one or more Central Processing Unit (CPU) cores and one or more of cache memory, a Low-DropOut (LDO) voltage regulator, interrupt controllers, serial interfaces such as Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C) or universal programmable serial interface module, Real Time Clock (RTC), timer-counters including interval and watchdog timers, general purpose Input-Output (IO), memory card controllers such as Secure Digital (SD)/MultiMedia Card (MMC) or similar, Universal Serial Bus (USB) interfaces, Mobile Industry Processor Interface Alliance (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports.

In some aspects, the memory may include one or more of volatile memory including Dynamic Random Access Memory (DRAM) and/or Synchronous Dynamic Random Access Memory (SDRAM), and Non-Volatile Memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), Phase change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM) and/or a three-dimensional crosspoint (3D XPoint) memory. The memory may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.

In some aspects, the power management integrated circuitry may include one or more of voltage regulators, surge protectors, power alarm detection circuitry and one or more backup power sources such as a battery or capacitor. Power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions.

In some aspects, the power tee circuitry may provide for electrical power drawn from a network cable to provide both power supply and data connectivity to the base station using a single cable.

In some aspects, the network controller may provide connectivity to a network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection which is one of electrical (commonly referred to as copper interconnect), optical or wireless.

In some aspects, the satellite navigation receiver module may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the Global Positioning System (GPS), GLObalnaya NAvigatSionnaya Sputnikovaya Sistema (GLONASS), Galileo and/or BeiDou. The receiver may provide data to the application processor which may include one or more of position data or time data. The application processor may use time data to synchronize operations with other radio base stations.

In some aspects, the user interface may include one or more of physical or virtual buttons, such as a reset button, one or more indicators such as Light Emitting Diodes (LEDs) and a display screen.

Another example of an implementation using ADC calibration according to one or more aspects of the architecture(s) described above or one or more examples described above is illustrated inFIG. 6.FIG. 6schematically illustrates an example of a mobile device600(e.g. mobile phone, smartphone, tablet-computer, or laptop) comprising an apparatus630for calibrating a TI-ADC620as proposed.

The TI-ADC620and the apparatus630for calibrating the TI-ADC620are part of a receiver610. The receiver610additionally comprises analog circuitry640configured to receive a RF receive signal from an antenna element660of the mobile device600. The analog circuitry640is further configured to supply the analog signal for digitization to the signal node of the apparatus630based on the RF receive signal. For example, the analog circuitry640may comprise one or more of a filter, a down-converter (mixer) or a LNA.

Further, the mobile device600comprises a transmitter650configured to generate a RF transmit signal. The transmitter650may use the antenna element660or another antenna element (not illustrated) of the mobile device600for radiating the RF transmit signal to the environment.

To this end, a mobile device enabling improved offline calibration of the ADC may be provided. Accordingly, a performance of the ADC and, hence, the mobile device may be improved.

The mobile device600may comprise further elements such as, e.g., a baseband processor, memory, a connectivity module, a Near Field Communication (NFC) controller, an audio driver, a camera driver, a touch screen, a display driver, sensors, removable memory, a power management integrated circuit or a smart battery.

In some aspects, the application processor may include, for example, one or more CPU cores and one or more of cache memory, LDO regulators, interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface module, RTC, timer-counters including interval and watchdog timers, general purpose input-output (IO), memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces and JTAG test access ports.

In some aspects, the baseband module may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and/or a multi-chip module containing two or more integrated circuits.

The wireless communication circuits using TI-ADC calibration according to the proposed architecture or one or more of the examples described above may be configured to operate according to one of the 3GPP-standardized mobile communication networks or systems. The mobile or wireless communication system may correspond to, for example, a 5G NR, a Long-Term Evolution (LTE), an LTE-Advanced (LTE-A), High Speed Packet Access (HSPA), a Universal Mobile Telecommunication System (UMTS) or a UMTS Terrestrial Radio Access Network (UTRAN), an evolved-UTRAN (e-UTRAN), a Global System for Mobile communication (GSM), an Enhanced Data rates for GSM Evolution (EDGE) network, or a GSM/EDGE Radio Access Network (GERAN). Alternatively, the wireless communication circuits may be configured to operate according to mobile communication networks with different standards, for example, a Worldwide Inter-operability for Microwave Access (WIMAX) network IEEE 802.16 or Wireless Local Area Network (WLAN) IEEE 802.11, generally an Orthogonal Frequency Division Multiple Access (OFDMA) network, a Time Division Multiple Access (TDMA) network, a Code Division Multiple Access (CDMA) network, a Wideband-CDMA (WCDMA) network, a Frequency Division Multiple Access (FDMA) network, a Spatial Division Multiple Access (SDMA) network, etc.

The examples described herein may be summarized as follows:

Example 1 is an apparatus for calibrating a TI-ADC comprising a plurality of time-interleaved ADC circuits, the apparatus comprising: an analog signal generation circuit configured to generate an analog calibration signal based on a digital calibration signal representing one or more digital data sequences for calibration, wherein the analog calibration signal is a wideband signal; and a coupling circuit configured to controllably couple an input node of the TI-ADC to either the analog signal generation circuit or to a node capable of providing an analog signal for digitization.

Example 2 is the apparatus of example 1, wherein the coupling circuit is configured to controllably couple the input node of the TI-ADC to either the analog signal generation circuit or to the signal node based on a control signal indicative of a desired operation mode of the TI-ADC.

Example 3 is the apparatus of example 1 or example 2, wherein a bandwidth of the analog calibration signal is less than half of a maximum value of the sample rate of the TI-ADC.

Example 4 is the apparatus of any of examples 1 to 3, wherein amplitude values of the analog calibration signal cover all input amplitude values supported by the TI-ADC.

Example 5 is the apparatus of any of examples 1 to 5, wherein a linearity of the analog signal generation circuit is higher than a desired linearity of the TI-ADC.

Example 6 is the apparatus of any of examples 1 to 5, wherein the analog signal generation circuit comprises: a DAC configured to generate an analog signal based on the digital calibration signal; and an analog filter configured to generate the analog calibration signal by filtering the analog signal.

Example 7 is the apparatus of example 6, wherein the analog filter comprises: an analog finite impulse response filter configured to generate an auxiliary analog signal by filtering the analog signal; and a passive analog filter coupled to the analog finite impulse response filter and configured to generate the analog calibration signal by filtering the auxiliary analog signal.

Example 8 is the apparatus of example 6 or example 7, wherein the DAC exhibits a resolution of 1 bit.

Example 9 is the apparatus of any of examples 1 to 5, wherein the analog signal generation circuit comprises: delay circuit configured to iteratively delay a digital data sequence represented by the digital calibration signal for generating a plurality of delayed digital data sequences; a plurality of DACs each configured to generate a respective analog signal based on one of the plurality of delayed digital data sequences; a combiner configured to combine the analog signals generated by the plurality of DACs to an auxiliary analog signal; and a passive analog filter coupled to the combiner and configured to generate the analog calibration signal by filtering the auxiliary analog signal.

Example 10 is the apparatus of example 9, wherein the plurality of DACs are configured to generate the analog signals with different gains.

Example 11 is the apparatus of example 9 or example 10, wherein the delay circuit is configured to iteratively delay the digital data sequence by a delay time, and wherein the delay time τ is defined as follows:

τ=TsD,
with 1/Tsdenoting a data rate of the digital calibration signal, and D denoting a desired oversampling ratio for the digital calibration signal.

Example 12 is the apparatus of any of examples 9 to 11, wherein the delay circuit comprises a chain of delay elements configured to iteratively delay the digital data sequence, wherein a delay time by which each of the delay elements delays its input is based on a control signal, and wherein the apparatus further comprises a DLL configured to supply the control signal to the delay elements.

Example 13 is the apparatus of any of examples 9 to 12, wherein the analog signal generation circuit comprises: a second delay circuit configured to iteratively delay a second digital data sequence represented by the digital calibration signal for generating a plurality of delayed second digital data sequences; and a second plurality of DACs each configured to generate a respective second analog signal based on one of the plurality of delayed second digital data sequences, wherein the combiner is configured to combine the analog signals generated by the plurality of DACs and the second analog signals generated by the second plurality of DACs to the auxiliary analog signal.

Example 14 is the apparatus of example 13, wherein the second plurality of DACs are configured to generate the second analog signals with different gains.

Example 15 is the apparatus of example 13 or example 14, wherein the delay circuit and the second delay circuit are configured to iteratively delay the digital data sequence and the second digital data sequence by the same delay time.

Example 16 is the apparatus of any of examples 1 to 5, wherein the analog signal generation circuit comprises: a plurality of sample circuits configured to generate a plurality of sampled signals by sampling a digital data sequence represented by the digital calibration signal based on different ones of a plurality of phase shifted clock signals; a plurality of DACs each configured to generate a respective analog signal based on one of the plurality of sampled signals; a combiner configured to combine the analog signals generated by the plurality of DACs to an auxiliary analog signal; and a passive analog filter coupled to the combiner and configured to generate the analog calibration signal by filtering the auxiliary analog signal.

Example 17 is the apparatus of example 16, wherein the plurality of DACs are configured to generate the analog signals with different gains.

Example 18 is the apparatus of example 16 or example 17, wherein the number of sample circuits is equal to a desired oversampling ratio for the digital calibration signal.

Example 19 is the apparatus of any of examples 16 to 18, wherein the analog signal generation circuit further comprises: a second plurality of sample circuits configured to generate a second plurality of sampled signals by sampling a second digital data sequence represented by the digital calibration signal based on different ones of the plurality of phase shifted clock signals; a second plurality of DACs each configured to generate a respective second analog signal based on one of the second plurality of sampled signals, wherein the combiner is configured to combine the analog signals generated by the plurality of DACs and the second analog signals generated by the second plurality of DACs to the auxiliary analog signal.

Example 20 is the apparatus of example 19, wherein the second plurality of DACs are configured to generate the second analog signals with different gains.

Example 21 is the apparatus of any of examples 9 to 20, wherein the plurality of DACs exhibits a resolution of 1 bit.

Example 22 is the apparatus of any of examples 1 to 21, wherein the one or more digital data sequences represented by the digital calibration signal are 1 bit sequences.

Example 23 is a receiver, comprising: a TI-ADC; and an apparatus for calibrating the TI-ADC according to any of examples 1 to 22.

Example 24 is the receiver of example 23, further comprising: analog circuitry configured to receive a RF receive signal from an antenna element, and to supply the analog signal for digitization to the signal node based on the RF receive signal.

Example 25 is a base station, comprising: a receiver according to example 23 or example 24; and a transmitter configured to generate a RF transmit signal.

Example 26 is the base station of example 25, further comprising at least one antenna element coupled to at least one of the receiver and the transmitter.

Example 27 is a mobile device, comprising: a receiver according to example 23 or example 24; and a transmitter configured to generate a RF transmit signal.

Example 28 is the mobile device of example 27, further comprising at least one antenna element coupled to at least one of the receiver and the transmitter.

The description and drawings merely illustrate the principles of the disclosure. Furthermore, all examples recited herein are principally intended expressly to be only for illustrative purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art. All statements herein reciting principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.