Apparatus and method for reading out a differential capacity with a first and second partial capacity

An apparatus for reading out a differential capacity with a first and second partial capacity includes a first oscillator having a first frequency-determining element connectable to the first partial capacity and a second oscillator having a second frequency-determining element connectable to the second partial capacity; a switching means to switch the first frequency-determining element into a first state or to switch it into a second state, and to switch the second frequency-determining element into a third state or to switch it into a fourth state; read apparatus having a first detection means connected to the first oscillator; and an evaluation means which carries out a quotient formation to obtain a value indicating a quotient of the first and the second partial capacity.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to reading out capacities and in particular to reading out differential capacities.

2. Description of Prior Art

Today in many apparatuses differential capacities are used as sensitive elements. For example, differential capacities are used as electrical elements on various sensors. Such sensors comprise, for example, acceleration sensors, pressure sensors or path sensors. Today many circuit variations are known for reading out differential capacities, which, however, cannot be employed for specific problems or only with restrictions.

For example, in particular applications it is required to detect a relatively slow change in capacity with high resolution. At the same time, however, changes in capacity occurring for a short time must be recognized within a very short period of time during readout. Such requirements occur, for example, when a single sensor having an acceleration-dependent differential capacity is employed for traction control of a motor vehicle and is to serve as an airbag sensor at the same time. Such a sensor should be capable of recognizing a crash within a period of time that permits the release of an airbag before the passengers in the motor vehicle can be harmed on the one hand. At the same time, such a sensor should be capable of detecting the acceleration data that are significantly lower compared to the accelerations occurring in a crash with high accuracy to permit secure traction control.

Another example in which a sensor is to meet the requirements of both detecting slow changes in capacity with high accuracy and recognizing very fast changes includes the manipulation of heavy weights. Often, in particular applications such as demolition of houses, in which a crane controls the movement of an iron ball, a control of weights is carried out as a function of acceleration signals provided by a sensor fastened to the heavy weight. On the one hand, for such an application the very slow movement of the large mass should be detected by the sensor with high resolution in order to perform an exact maneuvering in a particular position. On the other hand, changes in acceleration by means of impacts which may occur when a large mass impinges on the wall of a house, for example, and which may be as strong as several 100.000 g should be recognized, the demands on such a sensor being significantly higher due to the high change in acceleration within a very short time interval than for the above-described case of a sensor intended to serve as traction control and simultaneously as an airbag sensor.

For the above-described requirements of a detection of a slow change in capacity of the differential capacity with a high resolution and the simultaneous recognition of very fast changes in capacity two or more sensors are known to be used, a first known sensor being used to perform the slow change in capacity with high accuracy and a second sensor being used to recognize the fast change in capacity. For reading out, a readout circuit which may be further adapted specifically to the requirements of the sensor is used for each sensor.

A known readout circuit is described in DE 19645028 A1, for example, in which a LC oscillator is used to detect a deflection of a middle plate of a differential capacitor. Using a switchover means, the partial capacities of the differential capacity are alternately switched as frequency-determining capacities into a LC oscillating circuit. The LC oscillating circuit comprises an oscillator transistor operated in a source circuit. The switchover means includes switching diodes, a frequency measurement being shifted by an appropriately selected time window in such a way that a frequency measurement is excluded during a transient state of the oscillator. Subsequently, the frequencies of the two circuits are determined and are provided to another interpretation for obtaining a deflection of the middle plate. The frequency measurement may be determined, for example, by measuring impulses falling into a predetermined time window, the values being averaged above a plurality of oscillation periods. However, the circuitry described above has the disadvantage that a continuous readout with high accuracy is not possible, because readout is not possible during a transient state of the oscillator. In addition to this, a secure readout of fast changes in capacity which occur for a short time during the transient states is thus not possible.

U.S. Pat. No. 4,860,232 discloses a circuit for measuring capacities, a reference capacity and a sensor capacity being connected to a voltage comparison means comparing an input voltage with a reference voltage. A feedback loop is used to generate an offset voltage which is proportional to the difference of the reference capacity and the sensor capacity. However, the use of the voltage comparison means has the disadvantage that complicated calibrations are necessary to compensate charge injections caused by a switchover.

U.S. Pat. No. 5,973,538 describes a sensor circuit in which a first arrangement of CMOS inverters connected in series, which is connected to a first capacitor, and a second arrangement of CMOS inverters connected in series, which is connected to a second capacitor, are used to generate output voltages indicating the capacity value of the first and the second capacitor.

SUMMARY OF THE INVENTION

It is the object of the present invention to provide a concept permitting enhanced readout of a differential capacity.

In accordance with a first aspect, the present invention provides an apparatus for reading out a differential capacity with a first and second partial capacity having a first oscillator having a first frequency-determining element connectable to the first partial capacity; a first oscillator having a first frequency-determining element connectable to the first partial capacity; a second oscillator having a second frequency-determining element connectable to the second partial capacity; a switching means formed to switch the first frequency-determining element into a first state, so that the first oscillator has a first oscillation with a first period duration, or to switch it into a second state, so that the first oscillator has a second oscillation with a second period duration, and wherein the switching means is further formed to switch the second frequency-determining element into a third state, so that the second oscillator has a third oscillation with a third period duration, or to switch it into a fourth state, so that the second oscillator has a fourth oscillation with a fourth period duration; a first detection means connected to the first oscillator to generate a first signal indicating the first period duration and a second signal indicating the second period duration; a second detection means connected to the second oscillator to generate a third signal indicating the third period duration and a fourth signal indicating the fourth period duration; and an evaluation means for forming a quotient, using the first, second, third and fourth signal, whose numerator depends on the first oscillator and whose denominator depends on the second oscillator to obtain a value indicating a quotient of the first and the second partial capacity.

In accordance with a second aspect, the present invention provides a method for reading out a differential capacity with a first and second partial capacity having the following steps: setting a first oscillator having a first frequency-determining element connected to the first partial capacity into a first oscillation having a first period duration by switching the first frequency-determining element into a first state; generating a first signal indicating the first period duration; setting the first oscillator into a second oscillation having a second period duration by switching the first frequency-determining element into a second state; generating a second signal indicating the second period duration; setting a second oscillator having a second frequency-determining element connected to the second partial capacity into a third oscillation having a third period duration by switching the second frequency-determining element into a third state; generating a third signal indicating the third period duration; setting the second oscillator into a fourth oscillation having a fourth period duration by switching the second frequency-determining element into a fourth state; generating a fourth signal indicating a fourth period duration; forming a quotient, using the first to fourth signal, whose numerator depends on the first oscillator and whose denominator depends on the second oscillator to obtain a value indicating a quotient of the first and the second partial capacity.

According to the present invention a first oscillator is provided for a first of the two partial capacities and a second oscillator is provided for a second partial capacity, the oscillators being connected to the associated partial capacities in operation. Each of the oscillators is operable in two states by a switchover of frequency-determining elements. In correspondence with the state in which the frequency-determining element of the oscillator is, the first oscillator generates a first or a second oscillation and the second oscillator generates a third or fourth oscillation. During a subsequent evaluation in an evaluation circuit, an input signal is formed using the detected period durations, which indicates a quotient of the first and the second partial capacity.

The present invention is based on the finding that the detection of the period durations for each of the two oscillatory states of each oscillator, which is connected to a partial capacity and permits the quotient formation using the period durations, that unknown spurious influences which otherwise prevent an accurate readout of the partial capacities can be eliminated, so that the output signal indicating a quotient of the partial capacities can be formed with high accuracy.

The forming of the quotient using the detected period durations occurs in a preferred embodiment such that the numerator of the quotient has a value indicating a difference of a first period duration of the first oscillation of the first oscillator and a second period duration of the second oscillation of the first oscillator, while the denominator has a value indicating a difference of a third period duration of the third oscillation of the second oscillator and a fourth period duration of the fourth oscillation of the second oscillator.

One advantage of the present invention is that if the frequency-determining elements are suitably selected so that the values thereof are within the same order of magnitude a continuous detection can be carried out, because for each oscillator the switchover of the states of the frequency-determining elements can be carried out at the same time as the beginning of a detection of the oscillation, i.e. without waiting for a transient state to be finished.

In a preferred embodiment the switchover of the states for the first oscillator occurs at the same time as the switchover for the second oscillator and in constant time intervals, whereby a simplification of a subsequent evaluation is achieved.

In a preferred embodiment the period durations of the oscillations are determined by detecting a number of clock periods in a first detection means connected to the first oscillator and in a second detection means connected to the second oscillator. In this embodiment, both slow changes in capacity can be detected with high accuracy and at the same time short-term high changes in capacity can be recognized by the readout means. In order to do so, within a detection time interval within which the first and second oscillator each has an oscillatory state, a first number of clock periods of the first detection means detected at the respective predetermined times is compared at predetermined times with a second number of clock periods of the second detection means detected at this time, the result of this comparison being compared with a limiting value. Comparing the number of clock periods in shorter time intervals that can be chosen at will permits that short-term great changes of the first and the second partial capacity can be recognized, while at the same time a slow change of the partial capacities can be carried out with high accuracy by determining the number of clock periods over the long-term detection time interval.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIG. 1a readout apparatus100is shown as a first embodiment of the present invention. The readout apparatus100comprises a first oscillator110and a second oscillator112, the first oscillator110being connectable to a first fixed electrode116of a differential capacity118via a line114, while the second oscillator112is connectable to a second fixed electrode122via a line120. In one embodiment the first oscillator110and the second oscillator112each comprise a square-wave oscillator formed by a CMOS circuit.

The differential capacity118comprises a moveable electrode124connectable to the first oscillator110via a line126and to the second oscillator112via a line128. The differential capacity118includes any known type, for example a semiconductor differential capacitor, which is formed by means of known etching and masking steps in a semiconductor substrate. For example, the differential capacity118includes a sensitive element of a capacitive sensor, which may be, for example, an acceleration sensor, a pressure sensor or a path sensor.

The first oscillator110comprises a first frequency-determining element130connectable to electrode116via line114. The first oscillator110is further connected to a switching means134via a line132to switch the frequency-determining element130into a first state or into a second state. In the embodiment described, the first frequency-determining element130has a first resistor R1and a second resistor R2, each connectable to line114via a switch130a. In the first state of the frequency-determining element130, the first resistor R1is connected to line114, whereas in the second state the second resistor R2is connected to line114.

The second oscillator112comprises a second frequency-determining element136, the second frequency-determining element being connectable to the fixed electrode122of the differential capacity118via line120. The second oscillator112is further connected to switching means134via a line138to carry out from switching means134a switching signal for switching the second frequency-determining element136into a third state or a fourth state. In the embodiment described, the second frequency-determining element136includes a third resistor R3connected to line120in the third state and a fourth resistor R4connected to line120in the fourth state, the resistors R3and R4being connected by means of a switch136ain response to a signal of switching means134.

Readout means100further includes a first detection means140connected to the first oscillator110via a line142. The first detection means140is formed to detect a period duration of an oscillation generated by the first oscillator. Readout means100further includes a second detection means144for detecting a period duration of an oscillation generated by the second oscillator112, the second detection means144being connected to the second oscillator112via a line146. The detection means140and144may include any known means for detecting period durations. In one embodiment, which will be explained in greater detail below, the detection means140and144have counters detecting a number of clock periods of the oscillations within a particular time interval.

An evaluation means148is further connected to the first detection means140via a line150, while it is connected to the second detection means144via a line152.

In order to carry out a readout process, switching means134applies a switching signal to the first oscillator110via line132, so that the first R1or the second R2resistor is connected to electrode116. Furthermore, switching means134applies switching signals to the second oscillator112via line138, which cause a connection of the third R3or fourth R4resistor to electrode122.

During operation of the readout means in the oscillator circuit formed by the oscillator together with the frequency-determining element and the partial capacity, depending on the switched state of the frequency-determining elements the first oscillator110and the second oscillator112generate a first or second or a third or fourth oscillation, respectively, a clock period of the oscillations depending on a charging time τ of the partial capacity C with which the oscillator is respectively connected. According to the known formula τ=R·C, charging time τ depends on both the resistance R of the resistor with which the partial capacity C is connected and on the partial capacity C itself.

In addition to the dependency on the charging time of a respective partial capacity, a period duration of the oscillators110and112is influenced by a charging time τOSCwhich does not depend on the partial capacity C and the frequency-determining elements but on further devices of the oscillators110,112, respectively. A period duration T of a respective oscillator thus results to be: T=R·C+τOSC. Charging time τOSCis typically unknown and is not constant in time due to various noise influences on the oscillators110and112. This prevents that by simply detecting a period duration of a single oscillation of an oscillator, as is carried out in prior art, partial capacities can be read out with high accuracy.

Using an operation of readout means100, it is hereinafter explained how an improved readout is achieved compared to prior art by using two oscillators110and112according to the invention.

Applying a first switching signal to the first oscillator110causes the first frequency-determining element to be switched into the first state, i.e. the first resistor R1is connected to line114in response to the first switching signal. Correspondingly, the second frequency-determining element136of the second oscillator112is switched into the third state by a switching signal of switching means134transmitted via line138, i.e. the third resistor R3is connected to partial capacity CR, which is determined by electrodes124and122, by means of switch136a. Preferably, the switchover of the switching state of the first110and the second112oscillator by the switching of the respective frequency-determining elements occurs simultaneously in order to achieve that the period durations of the first oscillator110and the period durations of the second oscillator112can be detected over the same period of time. The simultaneous detection ensures an exact result in a subsequent quotient formation, as will be explained in greater detail further below.

After the simultaneous switchover of the first oscillator110into the first state and of the second oscillator112into the third state at a first switchover time, the first oscillator110generates the first oscillation with a clock period TL1and the second oscillator112generates the third oscillation the clock period TR1. According to the above stated facts, the following applies to the clock period TL1: TL1=RL1CL+τOSC,L1. In the equation RL1is the resistance of resistor R1and τOSC,L1is the additional term describing the charging times by the further devices of the first oscillator. Accordingly, the following applies to the clock period TR1of the third oscillation of the second oscillator: TR1=RR2CR+τOSC,R1. Here, RR2is the resistance of resistor R3and τOSC,R1is the additional term describing the charging times by the further devices of the second oscillator in the third state.

Oscillators110and112generate the first or the third oscillation, respectively, continuously in the course of a first detection time interval having a predetermined length, the initial time of the first detection time interval corresponding to the first switchover time and the end time of the first detection time interval corresponding to a second switchover time at which the frequency-determining element130of the first oscillator is switched into the second state and the second frequency-determining element136of the second oscillator112is switched into the fourth state. While the first frequency-determining element is in the first state, the first detection means140detects the period duration of the oscillation generating by the first oscillator110and provides a first signal indicating a period duration of the first oscillation to evaluation means148. Accordingly, while the second frequency-determining element136is switched in the third state, the second detection means144detects the period duration of the third oscillation generated by the second oscillator112and provides a third signal indicating a period duration of the third oscillation to evaluation means148.

At the end of the first detection time interval, i.e. at the second switchover time, the first frequency-determining element130of the first oscillator is switched into the second state and the second frequency-determining element136of the second oscillator112is switched into the fourth state, so that after the switchover oscillators110and112generate the second or fourth oscillation, respectively. The period duration TL2of the second oscillation results to be TL2=RL2CL+τOSC,L2·τOSC,L2, τOSC,L2describing the charging times by the further devices of the first oscillator when the first frequency-determining element130is in the second state, and RL2being the resistance of the second resistor R2. Correspondingly, the following applies to a clock period TR2of the fourth oscillation of the second oscillator: TR2=RR2CR+τOSC,R2·τOSC,R2. Here, τOSC,R2denotes the charging times by the further devices of the second oscillator when the second frequency-determining element136is in the fourth state. Furthermore, RR2corresponds to the resistance of resistor R4.

Oscillators110and112generate the second or fourth oscillation, respectively, continuously in the course of the second detection time interval which preferably has the same length as the first detection time interval to facilitate a subsequent evaluation. The second detection time interval thus has an initial time corresponding to the second switchover time and further has an end time corresponding to the third switchover time at which the first frequency-determining element130of the first oscillator is switched from the second state back into the first state and the second frequency-determining element136of the second oscillator112is switched from the fourth state back into the third state. While the first frequency-determining element130within the second time detection interval is in the second state, the first detection means140detects the period duration of the oscillation generated by the first oscillator110and provides a second signal indicating a period duration of the second oscillation to evaluation means148. Accordingly, while the second frequency-determining element136is switched in the fourth state, the second detection means144detects the period duration of the fourth oscillation generated by the second oscillator112and provides a signal indicating a period duration of the fourth oscillation to evaluation means148.

Consequently, two oscillations, each having different period durations, are generated per oscillator and, furthermore, four signals, each indicating one of the period durations of the oscillations, are provided to the evaluation means by the detection means140and144.

In one embodiment, the first detection means140and the second detection means144each includes a counting means detecting the number of clock periods of the generated oscillations occurring in the first or second detection time interval, respectively. Referring to the detection of a number of clock periods, an evaluation for the generation of an output signal indicating a quotient of the partial capacities is explained hereinafter.

In this embodiment, by the detection during the first or second detection time interval, respectively, a time averaging of the period durations of the clock periods occurring during the detection time window is carried out. As will be explained in greater detail hereinafter, for a readout with high accuracy it is necessary to suitably choose the time length of the detection time intervals and the order of magnitude of the clock frequency of the oscillators which is determined by the partial capacities and the frequency-determining elements in order to average out statistical noise components over the period of time.

The first detection means140and the second detection means144detect at each oscillator the number of clocks N during the first and second detection time intervals each preferably having a same predetermined time length TS. The number of clocks N is a measured value which is inversely proportional to the period duration of the oscillation. As is described above, the frequency-determining elements130and136are switched at the beginning of a detection time interval. The first detection means140outputs a first and a second detection signal. The first detection signal indicates a first number NL1of clock periods of the first oscillator110in the first state occurring within the first detection time interval. Furthermore, the second detection signal indicates a second number NL2of clock periods of the first oscillator in the second state occurring within the second detection time interval, the first and second detection time interval each including time period TS. Taking the dependency of period duration T according to T=RC+τOSCinto account, the number NL1or NL2, respectively, results to be:

Correspondingly, the second detection means144outputs a third detection signal indicating a third number NR1of clocks of the second oscillator in the third state of the frequency-determining element, whereas a fourth output signal of the second detection means144indicates a fourth number NR4of clocks during the time interval within which the second frequency-determining element is switched in the fourth state. According to the following formulae, the number NR1or NR2, respectively, results to be:

The first to fourth detection signals are input into evaluation means148via lines150or152, respectively. Preferably, the first detection means140and the second detection means144are formed in such a manner that the output signals are input into evaluation means148as data words. Then evaluation means148carries out a calculation operation during which a quotient is formed, the numerator depending on the clock numbers NL1and NL2of the first oscillator, whereas the denominator of the quotient depends on the clock numbers NR1and NR2of the second oscillator. In the embodiment described, the quotient is calculated according to the following formula:

The above quotient formation permits that by transforming the quotient in the right hand quotient expression of the above equation it is achieved that the undesirable impacts on the period durations described by the terms τOSC,L1τOSC,L2and τOSC,R1τOSC,R2only occur as difference terms τOSC,L1–τOSC,L2or τOSC,R1–τOSC,R2, respectively. This means that the impacts of the undesirable period durations τOSC,L1τOSC,L2and τOSC,R1τOSC,R2which are not determined by the partial capacities and the frequency-determining elements can be significantly reduced or eliminated with regard to the quotient formation, if the condition is met that these impacts are approximately equal for both oscillation states of respectively one oscillator.

In other words, the following has to be demanded:
τOSC,v1≈τOSCv2
wherein v=L has to be set for the first oscillator110and v=R for the second oscillator112.

This optimization condition is met the better the faster the switching of the states occurs, i.e. the more short-term the detection time intervals are, because the operation conditions of the oscillators do not significantly change during two states that follow each other quickly.

On the other hand, it is desirable to determine the order of magnitude of the clock frequency of the oscillators and the length of the detection time intervals or sample phases, respectively, in such a way that the statistical noise components over this period of time are averaged out. Noise elimination is the better the greater the length of the detection time intervals is.

When optimizing these opposing behaviors it has to be taken into consideration that non-statistical noise components, such as a 1/f noise of transistors of oscillators110and112, exert an influence on the terms τOSC,L1, τOSC,L2, τOSC,R1and τOSC,R2, so that TShas to be chosen so low that these non-statistical noise components are minimized to achieve the corresponding approximate equality
ττOSC,v1≈τOSC,v2.

Under the above assumption the difference terms τOSC,L1–τOSC,L2and τOSC,R1–τOSC,R2, respectively, become approximately zero and the above quotient results to be:

The result shows that by means of the optimization described above the quotient formation carried out by evaluation means148provides a result whose value is proportional to the quotient of C1and C2. The occurring proportionality factor k is formed by the quotient whose numerator includes a difference of the first and second resistor, whereas the denominator thereof includes a difference of the third and fourth resistor. As has already been mentioned above, spurious effects by devices of the first110or the second112oscillator, respectively, are eliminated in the above quotient. Consequently, with the above optimization by the quotient formation it can be achieved that the ratio of the partial capacities CLand CRis detected with high accuracy.

For a further processing, which may be controlling of an object, for example, evaluation means148applies an output signal indicating the calculated quotient to an output to provide the signal, for example, to a control means for controlling an object whose movement is detected by differential capacity118by means of changes in the partial capacities. Advantageously, the entire logic with which most of the evaluation algorithm is realized is a digital logic, so that the output signal is advantageously provided as a digital signal, as well, which permits further processing in a digital control means without much effort.

Typical values for the resistors R1–R4are greater than 10 kΩ in one range. In one embodiment, the first resistor R1includes a value of 80 kΩ, the second resistor a value of 40 kΩ, the third resistor a value of 45 kΩ and the fourth resistor R4a resistance of 90 kΩ if the value of the first and second partial capacity is in a range below 1 pF. With regard to the choice of the resistors, it has to be noted that they advantageously include the same order of magnitude to prevent a long transient of the oscillators during a switchover. With the above resistances a value results for the proportionality factor k, which is close to 1, i.e. in a range from 0.85 to 1.15. This value of 1 is preferred, because here possible undesirable impacts of the resistors, e.g. temperature impacts, compensate each other.

In this embodiment, the clock frequencies are typically selected in such a way that they are greater than one MHz for a non-deflected state of moveable electrode124. In these clock frequencies, the length of the detection time intervals with regard to the optimization described above is advantageously selected in a range from 100 to 10,000 clock periods, and, particularly preferably, in a range from 500 to 1,500 clock periods, whereby the detection time period TSapproximately has a range from 0.1 ms to 10 ms.

Referring toFIG. 2a further embodiment will hereinafter be explained as a development of the embodiment inFIG. 1. According toFIG. 2a readout means200includes a first oscillator210and a second oscillator212. Oscillators210and212are each connected to a fixed electrode214or216, respectively, of a differential capacity218. Furthermore, a moveable electrode220of the differential capacity218is connected to both the first oscillator210and to the second oscillator212via ground. In correspondence to the embodiment ofFIG. 1, oscillator210comprises a first frequency-determining element222and the second oscillator212comprises a second frequency-determining element224. The first oscillator210and the second oscillator212are each connected to a switching means228via lines225,226, respectively. Switching means228is further connected to a control means232via a line230. The first oscillator210is connected via a line236to a first counting mechanism234for detecting period durations of the first oscillator210. The second oscillator212is also connected via a line238to a second counting mechanism240for detecting period durations of the second oscillator212.

The first counting mechanism234and the second counting mechanism240are further connected to control means232via lines242or244, respectively. Control means232is connected to an evaluation means248via a signal line246. Evaluation means248has an output250connectable to further processing and control means via signal lines252. In correspondence to the embodiment inFIG. 1, for reading out the first partial capacity CLformed between electrode214and220and the second partial capacity CRformed between electrodes216the first frequency-determining element222is switched into a first state in a first detection time interval and is switched into a second state in a second detection time interval. Correspondingly, the second frequency-determining element224is switched into a third state in the first detection time interval and is switched into a fourth state in the second detection time interval. The first detection time interval extends from a first time to a second time, whereas the second detection time interval extends from the second time to a third time.

Control means232controls counting mechanism234via a control signal applied thereto in such a way that a count value for detecting clock periods of oscillations of the first oscillator210is reset to a predetermined initial value to carry out a detection of a number of clock periods occurring in the time interval within which the first frequency-determining element has the first state. The second counting mechanism240is also reset to a predetermined value at the first time to carry out a continuous detection of a number of clock periods of an oscillation of the second oscillator212during the time interval within which the second frequency-determining element224has the third state. The continuous detection by the counting mechanisms234or240, respectively, means that their count value is set forward by a particular value, i.e. by a unit, for example, with every clock occurring. The first counting mechanism234and the second counting mechanism240are reset back to the initial value at the second time, so that the first counting mechanism234detects the clock pulses of the first oscillator210during a second detection time interval within which the first frequency-determining element222is in the first state and the second frequency-determining element224is in the third state, whereas the second counting mechanism240detects the clock periods of the second oscillator212during the second detection time interval. A switchover of the first frequency-determining element222into the second state and a switchover of the second frequency-determining element224into the fourth state are then carried out at the third time. Advantageously, the first time interval and the second time interval have the same length, which facilitates both the control of frequency-determining elements222and224and of detection means234and240and a calculation in evaluation means248. As has already been explained with reference to the embodiment inFIG. 1, for achieving a readout with high accuracy the length of the first and second detection time interval is advantageously selected such that statistical and non-statistical noise components are minimized. In contrast to the embodiment inFIG. 1, in this embodiment a detection of a temporal change of a current period duration is carried out to output a signal indicating an exceeding of a predetermined value in response to a comparison of a temporal change of a current period duration of the first, second, third or fourth oscillation with a predetermined value. The detection of the temporal change can be carried out either by detecting only a current period duration of an oscillation, i.e. either of the first, second, third or fourth oscillation, and comparing the detected value with a comparison value or by detecting the period durations of current oscillations of the first110and the second112oscillator, as will be explained hereinafter.

For this purpose, in this embodiment the number of clock periods of the first oscillator detected by the first counting mechanism234is compared with the number of clock periods of the second oscillator detected in the second counting mechanism240at predetermined comparison times. This is made possible, because the detection by the counting mechanisms234and240is continuous. The comparison of the counter values of the first counting mechanism234and of the second counting mechanism240is controlled by control means232and permits that fast changes in the first and second partial capacity occurring for a short time can be recognized quickly, as will be explained hereinafter.

A short-term high change in capacity causes the values of the partial capacities to differ greatly for a short time. Due to the great differences in capacity, the oscillators provide oscillations having period durations which differ greatly with respect to their difference compared to values before the occurrence of the short-time high change in capacity. This can be utilized, because in a continuous detection of the clock periods highly different differences of the count values of the first counting mechanism and of the second counting mechanism result for the short period of the high differences in capacity of the partial capacities. The temporal range in which such a change can be detected depends on a choice of the comparison times.

The temporal distance of the comparison times can be set by an external or internal clock signal, for example, so that after a particular number of clock cycles of the external or internal clock signal the number of detected clock periods of the first counting mechanism234and of the second counting mechanism240are compared. The temporal distances of the comparison times can be chosen at will, and it is preferable to choose them in such a way that the typical peaks of a change in capacity occurring in the intended application are securely recognized.

In one embodiment, the comparison times are alternatively determined by the clock periods of the first oscillator210or second oscillator212, respectively, detected by the first counting mechanism234and the second counting mechanism240. The comparison time results when either the first counting mechanism234or the second counting mechanism240reaches a predetermined number of clock periods which have been detected since the last comparison time. For example, the comparison time is set when five clock periods were detected in the first counting mechanism234or in the second counting mechanism240since the previous comparison time.

The comparison of the count values of the first counting mechanism234and of the second counting mechanism240carried out at the comparison times provides a difference of the two count values and allows short-term fast changes in capacity of the partial capacities to be recognized by comparing with a predetermined limit value. The predetermined limit value can, for example, be determined by a testing in which the peaks of capacity change occurring for a respective application are detected. By comparing the difference of the count value of the first counting mechanism234with the second counting mechanism240, a decision procedure can be carried out, in which a signal indicating the occurrence of a short-term high change in capacity when an amount of the difference of the count value of the first counting mechanism234and of the second counting mechanism240is greater than the predetermined limit value.

Readout means200further permits that a change in capacity can be detected continuously with high accuracy by determining four values indicating the period durations of the first oscillator210and of the second oscillator212in the respective states of the first frequency-determining element222and of the second frequency-determining element across the first and second detection time interval in correspondence with the method described with reference to the embodiment inFIG. 1. By the quotient formation described with reference to the embodiment ofFIG. 1, an output signal indicating the quotient of the first and second partial capacity is applied to output250by evaluation means248using the four values. At the same time, however, read out means200is capable of carrying out a recognition of short-term high changes in capacity by comparing the amount of difference of the count value of the first counting mechanism234and of the count value of the second counting mechanism240with a predetermined limit value at the comparison times.

Although the first and second frequency-determining element each comprises two resistors in the present embodiments, in other embodiments the first and second frequency-determining element may each comprise two inductances, the switching means being further formed to carry out a switchover of the inductances for switching the states of the frequency-determining elements.

Advantageously, readout means100or200, respectively, are provided as integrated circuits on a chip, and the chip may additionally include the differential capacity. This makes a compact sensor possible in which both the capacitive sensitive element and the read out/evaluation means are arranged on a chip. Advantageously, the first and second detection means, the switching means and the evaluation means include digital devices to permit an as much as possible digital processing on the chip without an external wiring.