Transistor with controllable compensation regions

Disclosed is a MOSFET including at least one transistor cell. The at least one transistor cell includes a source region, a drain region, a body region and a drift region. The body region is arranged between the source region and the drift region and the drift region is arranged between the body region and the drain region. The at least one transistor cell further includes a compensation region arranged in the drift region and distant to the body region, a source electrode electrically contacting the source region and the body region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a coupling arrangement including a control terminal. The coupling arrangement is configured to electrically couple the compensation region to at least one of the body region, the source region, the source electrode and the gate electrode dependent on a control signal received at the control terminal.

TECHNICAL FIELD

Embodiments of the present application relate to a transistor, in particular a MOS transistor with a compensation region.

BACKGROUND

MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), in particular power MOSFETs, are widely used as electronic switches for switching electrical loads or as electronic switches in all types of switching converters. A power MOSFET includes a drain region, a drift region adjoining the drain region, and a source region, each having a first conductivity type, and a body region arranged between the drift region and source region of a second conductivity type. A gate electrode serves to control a conducting channel in the body region between the source region and the drift region. The source electrode is electrically connected to a source electrode which is also connected to the body region, and the drain region is electrically connected to the drain electrode. The MOSFET can be switched on and off by applying a suitable drive potential to the gate terminal.

In a specific type of MOSFET, which is also referred to as compensation or superjunction MOSFET, a compensation region is arranged in the drift region. This compensation region is of the same doping type as the body region and is electrically connected to the body region. The compensation region includes doping charges that are complementary to the doping charges in the drift region and that “compensate” the doping charges in the drift region when the MOSFET is in its off-state. By virtue of the compensation regions the drift region can be more highly doped than in conventional MOSFETs, resulting in a reduced on-resistance, at a given voltage blocking capability.

MOSFETs include a voltage dependent output capacitance (usually referred to as COSS) which usually includes a drain-source capacitance CDSbetween its drain and source terminals and a gate-drain capacitance CGDbetween its gate and drain terminals. When the MOSFET transitions from the on-state to the off-state, the output capacitance is charged, i.e. energy is stored in the output capacitance; the output capacitance is discharged, when the MOSFET transitions from the off-state to the on-state. The output energy EOSS, which is the energy stored in the output capacitance, is mainly dependent on the voltage across the drain-source path when the MOSFET is in its off-state and is dependent on the capacitance value of the output capacitance. A compensation MOSFET, due to the compensation regions connected to the body regions and the source electrode, has a high drain-source capacitance and, therefore, has a high output capacitance.

Losses occur when a MOSFET is operated. These losses mainly include capacitive losses and ohmic losses.

Capacitive losses are defined by the energy stored in the output capacitance of the MOSFET, wherein these losses increase with increasing output capacitance. In many applications, the capacitive losses dominate the switching losses under typical load conditions.

Ohmic losses occur when the MOSFET is in its on-state. Ohmic losses are due to the MOSFET's on-resistance. Additionally, switching losses occur when the MOSFET switches from the on-state to the off-state, and vice versa. These switching losses result from the fact that MOSFETs do not switch on or off abruptly, but they gradually change between the on-state, in which an ohmic resistance of the MOSFET assumes its minimum value, and the off-state, in which the MOSFET blocks and prevents a current flow. The minimum value of the ohmic resistance is the on-resistance.

The ohmic losses are proportional to the square of the load current, while the capacitive losses have a smaller dependency on the load current. Therefore, dependent on the specific load conditions, the ohmic losses or the capacitive losses may prevail. For example, when a load connected to the MOSFET draws a low load current, so that a low current flows through the MOSFET in its on-state, the capacitive losses may mainly determine the overall losses. Whereas, when the load draws a high load current, the ohmic losses and switching losses during transition phases may mainly determine the overall losses. The switching losses during transition phases and the capacitive losses are directly proportional to the switching frequency of the device.

In addition, the output charge QOSS, which is the charge stored in the output capacitance, is important for some applications. E.g., the turn off delay time of the MOSFET at low load currents is dominated by the output charge. This is the charge which has to be stored in the output capacitance before the transistor is completely turned off. This output charge is provided by the load current. Therefore, the turn off delay time increases inversely proportional with decreasing load current.

There is, therefore, a need to provide a MOSFET with a compensation region in which dependent on the load conditions the losses and turn off delay time can be minimized.

SUMMARY

A first aspect relates to a MOSFET including at least one transistor cell. The transistor cell includes a source region, a drain region, a body region and a drift region. The body region is arranged between the source region and the drift region and the drift region is arranged between the body region and the drain region. The transistor cell further includes a compensation region arranged in the drift region and distant to the body region, a source electrode electrically contacting the source region and the body region, and a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric. A coupling arrangement includes a control terminal and is configured to electrically couple the compensation region to at least one of the body region, the source region, the source electrode and the gate electrode dependent on a control signal received at the control terminal.

A second aspect relates to a MOSFET including at least one transistor cell of a first type and at least one transistor cell of a second type. The at least one transistor cell of the first type includes a first source region, a first drain region, a first body region and a first drift region. The first body region is arranged between the first source region and the first drift region and the first drift region is arranged between the first body region and the first drain region. The at least one transistor cell of the first type further includes a first gate electrode arranged adjacent the first body region and dielectrically insulated from the first body region by a first gate dielectric, a first source electrode electrically contacting the first source region and the first body region, and a first compensation region arranged in the first drift region and electrically connected to at least one of the first body region, the first source region and the first gate electrode.

The at least one transistor cell of the second type includes a second drain region, a second body region and a second drift region, the second drift region arranged between the second body region and the second drain region, a second compensation region arranged in the second drift region and distant to the second body region, and a second source electrode electrically contacting the second body region. The at least one transistor cell of the second type further includes a coupling arrangement including a control terminal and being configured to electrically couple the second compensation region to at least one of the second body region and the second source electrode dependent on a control signal received at the control terminal.

DETAILED DESCRIPTION

In order to ease a better understanding of embodiments which will be explained herein further below, the use of a transistor component as an electronic switch will be explained with reference toFIG. 1.FIG. 1shows a circuit diagram with a transistor component1that acts as an electronic switch for switching a current through a load Z. The transistor component1, which in the example ofFIG. 1is implemented as a MOSFET, includes a gate terminal G which is configured to receive a drive signal S1from a drive circuit2, and a load path. The load path, which can also be referred to as internal load path, extends within the transistor1between a drain and a source terminal D, S. The load path D-S is connected in series with a load Z, with the series circuit with the transistor1and the load Z being connected between terminals for a first and a second supply potential V+, GND. The load Z can be a resistive load such as e.g. a filament bulb, an inductive load such as a coil, a transformer or an induction motor, or a capacitive load.

The transistor1can be switched on and off by the drive circuit2that generates a suitable drive signal S1at the gate terminal G of the transistor1. The drive signal is, for example, a pulsewidth-modulated (PWM) signal. This is commonly known, so that no further explanation is required in this regard.

When the MOSFET is switched on, i.e. when the MOSFET is in its on-state, a load current IDflows through the load Z and the load path of the transistor1, where the magnitude of the load current IDis mainly defined by the supply voltage present between the terminals for the first and second supply potential V+, GND and by the characteristic of the load Z. When the transistor1is in its on-state, ohmic losses occur in the transistor1. These losses result from the on-resistance of the transistor1and the load current IDflowing through the transistor1. When the MOSFET changes its operation state from the on-state to the off-state, i.e. when the MOSFET is switched off, or vice versa, losses increase for a short time interval. This is due to the simultaneous presence of high currents and high voltages at the load terminals D, S of the transistor1in transition phases between the on-state and the off-state.

Transistor components, in particular MOSFETs, include an output capacitance which is effective between the drain and the source and the drain and the gate terminals and usually includes a drain-source capacitance CDSbetween the drain and the source terminals D, S and a gate-drain CGDcapacitance between the gate and the drain terminal. InFIG. 1the drain-source capacitance CDSis schematically illustrated. It should be noted in this connection that the drain-source capacitance and the drain-gate capacitance can be regarded to be connected in parallel in a small-signal equivalent circuit diagram. A capacitance value COSSof the output capacitance is dependent on the voltage between the drain and source terminals D, S of the transistor1. The dependency of this capacitance value COSSon the voltage VDSbetween the drain and source terminals D, S is schematically illustrated inFIG. 2.

When the transistor1is switched off and the voltage VDSacross the load path of the transistor1increases, the output capacitance is charged, i.e. energy is stored in the output capacitance. Equivalently, the output capacitance is discharged when the MOSFET is switched on. Charging the output capacitance when the MOSFET is switched off, and discharging the output capacitance when the MOSFET is switched on causes losses, which will be referred to as capacitive losses in the following.

Losses that occur when the transistor component1is operated in a switched-mode, i.e. when the transistor component1is cyclically switched on and off, include ohmic losses, switching losses during transition phases, and capacitive losses. Which of these losses prevails is dependent on the load condition of the transistor component1. The load condition of the transistor component1is mainly defined by the load current IDflowing through the transistor1in its on-state, but is also defined by the switching frequency at which the transistor is switched on and off.

The capacitive losses are dependent on the energy which is stored in the output capacitance when the transistor1is switched off. This energy is dependent on the capacitance value COSSof the output capacitance and the maximum voltage across the load path of the transistor1when the transistor1is in its off-state.

There are transistor components in which the capacitance value COSSof the output capacitance is dependent on the voltage across the load path of the transistor1.FIG. 2schematically illustrates such voltage-dependency of the output capacitance value COSSon the voltage across the transistor. InFIG. 2, COSSdenotes the output capacitance value, and VDSdenotes the voltage between the drain and source terminals D, S of the transistor1. As can be seen fromFIG. 2, there is a voltage VDS0at which the output capacitance value COSSsignificantly decreases when the voltage VDSincreases.

InFIG. 2, besides the curve in which the output capacitance value COSSrapidly decreases at VDS0, two further curves are shown in which the capacitance value rapidly decreases at a voltage higher than VDS0and rapidly decreases at a voltage lower than VDS0, respectively. The VDS0voltage can be dependent on the maximum capacitance value, which occurs at low drain-source voltages VDS. According to one embodiment, the VDS0voltage decreases with decreasing maximum capacitance value COSS.

The energy EOSSstored in the output capacitance is given by:

EOSS=∫DSonVDSoff⁢COSS⁡(VDS)⁢VDS⁢⁢ⅆVDS1.⁢⁢(1⁢a)
where VDSonis the voltage across the load path when the transistor1is in its on-state, and VDSoffis the voltage across the load path when the transistor1is in its off-state. COSS(VDS) is the output capacitance value which is dependent on the voltage VDS. Since the voltage VDSonacross the transistor1in its on-state is, usually, very low and significantly lower than the voltage VDSoffin the off-state, equation (1a) can be simplified to

It can be seen fromFIG. 2and from equations (1a) or (1b), respectively, that the energy EOSSstored in the output capacitance and, therefore, the capacitive losses can be reduced by decreasing the voltage value VDS0at which the output capacitance value COSSdecreases as well as by reducing the plateau-value, i.e. the maximum capacitance value, at low VDS.

A first embodiment of a transistor component10which has a voltage-dependent output capacitance and in which the voltage-dependency of the output capacitance can be adjusted is explained next with reference toFIG. 3.

The transistor component10illustrated inFIG. 3is implemented as a MOSFET, specifically as a compensation or superjunction MOSFET. The characteristic curve of the output capacitance COSSillustrated inFIG. 2in which there is a strong dependency of the output capacitance COSSon the drain-source voltage VDSis typical for a superjunction MOSFET. The MOSFET includes a source region12connected to a source electrode51forming a source terminal S, and a drain region14connected to a drain terminal D. The drain terminal may be formed by a drain electrode52arranged on the drain region14. The MOSFET further includes a drift region11and a body region13, where the body region13is arranged between the source region12and the drift region11, and the drift region11is arranged between the body region13and the drain region14. The source region12, the body region13, the drift region11and the drain region14are integrated in a semiconductor body100. The MOSFET according toFIG. 3is implemented as a vertical MOSFET, which is a MOSFET in which the source region12and the drain region14are arranged distant to one another in a vertical direction of the semiconductor body10. In this case, a current essentially flows in a vertical direction through the semiconductor body100when the MOSFET is in its on-state. However, implementing the MOSFET as a vertical MOSFET is only an example. The basic principle explained herein below is also applicable to lateral MOSFETs in which the source and the drain regions are arranged distant to one another in a lateral direction of a semiconductor body. The basic principle is also applicable to MOSFETs (not shown) in which the drain region is implemented as a buried layer that is arranged distant to the source region in a vertical direction of the semiconductor body. The buried layer can be connected to a drain terminal that is arranged on or above the same surface of the semiconductor body as the source terminal.

The source region12and the body region13are both connected to the source electrode51that forms the source terminal S. This is common practice in MOSFETs.

The MOSFET further includes a gate electrode21connected to or forming a gate terminal G. The gate electrode21is arranged adjacent to the body region13, wherein a gate dielectric22is arranged between the gate electrode21and the body region13. In a commonly known manner the gate electrode21serves to control a first conducting channel in the body region13between the source region12and the drift region11. In the embodiment illustrated inFIG. 3, the gate electrode21is a planar electrode, i.e. the gate electrode21is arranged above one of the surfaces of the semiconductor body100. However, this is only an example. The gate electrode21could also be implemented as a trench electrode (not shown) in a trench of the semiconductor body100.

The MOSFET is in its on-state, when an electrical potential applied to the gate terminal G is suitable to generate a first conducting channel along the gate dielectric22in the body region13, and the MOSFET is in its off-state, when there is no suitable drive potential at the gate terminal G to generate a conducting channel in the body region13.

The MOSFET may be implemented as an enhancement MOSFET. In this case, the body region13is doped complementarily to the source region12, so that the first conducting channel generated in the body region13and controlled by the gate electrode21is an inversion channel. However, the MOSFET could also be implemented as a depletion MOSFET. Further, the MOSFET may be implemented as an n-type MOSFET or as a p-type MOSFET. In an n-type MOSFET the source region12and the drain region14are n-doped, while in a p-type MOSFET the source region12and the drain region14are p-doped.

The MOSFET ofFIG. 3is implemented as a compensation or superjunction MOSFET and includes a compensation region31in the drift region11. The compensation region31has a doping type that is complementary to the doping type of the drift region, so that a pn-junction is formed between the compensation region31and the drift region11.

The compensation region31, which has the same doping type as the body region13, is separated from the body region12. In the embodiment illustrated inFIG. 3, the compensation region31is arranged below the body region13and is arranged distant to the body region13in the vertical direction of the semiconductor body100, so that a section11′ of the drift region11is arranged between the body region13and the compensation region31. This allows the compensation region31to assume an electrical potential that is different from the electrical potential of the body region13.

The MOSFET further includes a coupling arrangement40that is configured to electrically couple the compensation region31to at least one of the body region13, the source region12, and the source electrode51dependent on a control signal received at a control terminal G2. The coupling arrangement40is only schematically illustrated as a switch. This switch may be implemented as an electronic switch, such as a transistor, connected between the compensation region31and the source electrode51. The compensation region31may include a contact electrode (not shown) at which the switch is connected to the compensation region31. In the embodiment illustrated inFIG. 3, the compensation region31is implemented as a buried region that is below the body region13and distant to a surface of the semiconductor body100in a vertical direction. However, the compensation region31may include a section that extends to the surface (in a vertical plane other than the one illustrated inFIG. 3) where the compensation region31can be contacted. Other embodiments for implementing the coupling arrangement are explained below.

According to a further embodiment (not shown), the coupling arrangement40may be connected between the compensation region31and the gate electrode21instead of the body region13, the source region12, or the source electrode51.

The coupling arrangement40may assume two different operating states. In a first operating state, the coupling arrangement40couples the compensation zone31to at least one of the body region13, the source region12, and the source electrode51. In a second operating state, the coupling arrangement40decouples (separates) the compensation zone31and the body region13/source electrode51, so that the compensation region31is floating. The coupling arrangement40includes a control terminal G2through which the operating state of the coupling arrangement40can be controlled. The operating state of the coupling arrangement40is independent on whether the MOSFET is in its on-state or off-state. Thus, the MOSFET may include two different switching states, namely an on-state and an off-state, and two different operating states, namely a first operating state when the coupling arrangement40is in the first operating state, and a second operating state when the coupling arrangement40is in the second operating state.

The operating principle of the MOSFET according toFIG. 3is now explained. For explanation purposes it is assumed that the MOSFET is an n-type enhancement MOSFET. However, the explanation provided herein below also applies to a p-type MOSFET and to a depletion MOSFET.

Like a conventional MOSFET, the MOSFET can be switched on and off by applying a suitable drive potential at the gate terminal G. When the MOSFET is switched on (is in its on-state) there is a conducting channel in the body region13between the source region12and the drift region11along the gate dielectric22. When the MOSFET is switched off, the conducting channel along the gate dielectric22is interrupted. When the MOSFET is in the off-state and when a voltage is applied between the drain and source terminals D, S (a positive voltage in an n-type MOSFET and a negative voltage in a p-type MOSFET), a depletion zone expands in the drift region11. This depletion zone, or the electric field associated with the depletion zone, also causes the compensation region31to be depleted of charge carriers. Thus, dopants (the doping charge) in the drift region11are “compensated” by complementary dopants in the compensation region31. This mechanism occurs independent of whether the coupling arrangement40is in the first or second operation mode, i.e. independent of whether or not the compensation region31is coupled to the body region13/source electrode51.

The compensation effect explained above allows to provide a higher doping concentration in the drift region11, resulting in a lower on-resistance, as compared with conventional (non-superjunction) components, without decreasing the voltage blocking capability. This basic operating principle of a superjunction device is commonly known so that no further explanation is required in this regard.

When the MOSFET is in its off-state, the compensation region31and the drift region11include electrical charges. These charges are positive charges (in the form of positively charged donor centers) in a n-doped drift region and negative charges (in the form of negatively charged acceptor centers) in a p-doped compensation region and cause a depletion region to extend in the drift region11and the compensation region31. When the MOSFET is driven to switch from the off-state to the on-state, two different scenarios may occur dependent on whether the coupling arrangement40is in the first operation mode or in the second operation mode.(a) When the coupling arrangement40is in the first operation mode, so that the compensation region31is electrically coupled to the source electrode51, the drift region11and the compensation region31are “discharged” so that the depletion region between the compensation region31and the drift region11is removed. This corresponds to the operation of a conventional superjunction device.(b) When the coupling arrangement40is in the second operation mode, so that the compensation region31is not electrically coupled to the source electrode51(is floating), the compensation region31cannot be discharged completely so that the depletion region between the compensation region31and the drift region11cannot totally be removed. This may cause a conducting channel in the drift region11between the drain region14and the “channel region” to be partially or completely be pinched off, even when the MOSFET is in its on-state. The channel region is that region of the body region13in which a conducting channel along the gate dielectric22can be controlled.

The MOSFET according toFIG. 3has an output capacitance with an output capacitance value COSSthat has a characteristic according toFIG. 2and which significantly decreases when the voltage reaches a threshold value VDS0. The characteristic illustrated inFIG. 2in which the output capacitance value COSShas a high value for voltages below the threshold value VDS0, and has a lower value for voltages above the threshold value VDS0is equivalent to the fact that at voltages lower than the threshold value VDS0a higher charge has to be provided to the load path of the transistor10to increase the voltage across the load path for a given voltage value □VDSthan at higher voltages, i.e. voltages higher than the threshold voltage VDS0. The capacitance value at lower voltages can be up to 10 times to 100 times higher than the capacitance value at higher voltages. Thus, at lower voltages a charge for increasing the voltage for □VDSis 10 times to 100 times higher than the charge required at higher voltages. MOSFETs of the type illustrated inFIG. 3can be designed to have a breakdown voltage of between 50V and 2000V (2 kV). The voltage VDS0at which the output capacitance decreases is, for example, between 5V and 80 V, in particular between 10V and 80V, for such MOSFETs.

The mechanism that causes the explained voltage-dependency of the output capacitance value in the MOSFET according toFIG. 3will now be for scenario (a), when the coupling arrangement40is in the first operation state. When the MOSFET is in its off-state charge carriers are accumulated in the drift region11and the compensation region31. In the on-state there is a junction capacitor with a huge capacitance between the compensation region31and the drift region11. This capacitor significantly contributes to the drain-source capacitance CDSand, thus, significantly contributes to the output capacitance COSSof the MOSFET. When the MOSFET is switched off, i.e. when the channel along the gate dielectric22is interrupted, this junction capacitance has to be charged (which is equivalent to removing dopant charges from the compensation region31and the drift region11) before the voltage across the drift region11and, thus, the voltage between the drain and source terminals D, S, can significantly increase. When the compensation region31and the drift region11have been charged, a depletion region expands in the drift region11and the compensation region31. At the time when the compensation region31has been completely charged, the junction capacitor “disappears” causing a rapid decrease of the output capacitance COSS. The slope of the decrease of the output capacitance COSSis steep and occurs at the voltage VDS0shown inFIG. 2. VDS0, which is, e.g., between 5V and 80V, is dependent on the geometry of the compensation region31and its doping concentration. VDS0represents a specific value of the drain-source voltage VDSat which the drift region11is completely depleted by a space charge region that expands in a direction perpendicular to a current flow direction of the MOSFET.

The doping concentration of the drift region11is, for example, in the range of between 1014(1E14) cm−3and 1016(1E16) cm−3. The doping concentration of the compensation region31may be in the same range.

A superjunction device with compensation region31that, as in scenario (a), is charged when the MOSFET is switched off and is discharged when the MOSFET is switched on has a higher output capacitance COSS, but a lower on-resistance, than a conventional MOSFET. The output capacitance COSSis reduced when the compensation, as in scenario (b), is not electrically coupled to the source electrode51, i.e. when the compensation region31is floating. However, there is an increased on-resistance in this case. Thus, via the controllable coupling arrangement40the output capacitance and the on-resistance of the MOSFET can be varied. There is a tradeoff in that a decrease of the output capacitance, resulting in decreased of capacitive losses, is associated with an increase of the on-resistance, resulting in higher ohmic losses. A decrease of the on-resistance, resulting in decreased ohmic losses, is associated with an increase of the output capacitance, resulting in higher capacitive losses.

The operating principle which has been explained for an n-type MOSFET hereinbefore also applies to a p-type MOSFET, wherein in a p-type MOSFET the individual semiconductor regions have a complementary doping type, and the voltages have a reversed polarity.

The compensation region31and the drift region11form a JFET (junction FET) between the body region13and the drain region14. A circuit symbol of this JFET is illustrated inFIG. 3. When the MOSFET is in the off-state there are two depletion regions that expand in the drift region11, a first depletion region expanding from the pn junction between the body region13and the drift region11, and a second depletion region expanding from the pn junction between the compensation region31and the drift region11.

The MOSFET according toFIG. 3can be implemented with a plurality of identical structures, which are commonly known as transistors cells. InFIG. 3only one transistor cell is illustrated.FIG. 4illustrates a schematic cross sectional view of a MOSFET with a plurality of transistor cells. These transistor cells are connected in parallel by having the source regions12of the individual cells connected to a common source electrode51, by having the gate electrodes21of the individual cells connected to a common gate terminal G, and by having the drain and drift regions14,11of the individual cells connected to a common drain terminal D. The drift region11and the drain region14are common to the individual transistor cells.

The coupling arrangement40is configured to couple the compensation regions31of the individual cells to at least one of the body region13, the source region12and the source electrode51dependent on a control signal received at the control terminal. For this, the coupling arrangement40includes a plurality of coupling cells, wherein each coupling cell serves to couple the compensation region31of at least one transistor cell to at least one of the body region13, the source region12and the source electrode51of the transistor cell. InFIG. 4, two coupling cells401,40nare shown where each coupling cell serves to connect one compensation region31to one body region13, source region12or source electrode51. In the embodiment illustrated inFIG. 4, one compensation region31and one body region13is common to two transistor cells. However, this is only an example. It is also possible to implement the transistor cells such that only one compensation region31, only one body region13and only one coupling cell is assigned to one transistor cell.

The coupling arrangement40can be implemented such that all the coupling cells are operated in the same operating state, which is the first operating state or the second operating state. However, it is also possible to implement the coupling arrangement40such that the individual coupling cells can be operated in the first or second operating state independently, so that some transistor cells can be operated with floating compensation regions31, while others can be operated with their compensation regions31connected to the source electrode51.

The individual transistor cells can be implemented with a conventional transistor cell geometry.FIG. 5illustrates a schematic horizontal cross sectional view of a MOSFET with longitudinal or stripe cells. In this case, the source and body regions12,13of the individual cells have a stripe geometry.

Referring toFIGS. 6 and 7it is also possible to implement the transistor cells with a rectangular or square geometry (seeFIG. 6) or with a hexagonal (seeFIG. 7) or any other polygonal geometry. In this case, the body regions13, have a rectangular or square, a hexagonal or polygonal geometry.

FIGS. 5 to 7illustrate horizontal cross sectional views of the MOSFET in a section plane A-A illustrated inFIG. 4. The compensation regions31are not illustrated inFIGS. 5 to 7. The geometry of the compensation regions31in the horizontal plane may correspond to the geometry of the body region13. Thus, in a MOSFET with stripe cells the compensation regions31may have a stripe geometry, in a MOSFET with a rectangular or square geometry, the compensation regions31may have a rectangular or square geometry, and in a MOSFET with hexagonal or polygonal cells, the compensation regions31may have a hexagonal or polygonal geometry. In each of these cases, the compensation regions31may be arranged below the body region13in a vertical direction of the semiconductor body100, as illustrated inFIG. 4.

However, it is also possible to implement the compensation regions31with a geometry that is different from the geometry of the body region13. For example it is possible to implement the compensation regions31with a stripe geometry, while the transistor cells have a rectangular, square, hexagonal or polygonal geometry. Further, it is possible to arrange the compensation regions31so that the compensation regions31are not aligned with the body regions13, i.e. the compensation regions31do not necessarily have to be arranged below the body regions13.

FIG. 8illustrates a schematic vertical cross sectional view of a MOSFET illustrating one embodiment of implementing the coupling arrangement40. In this embodiment, the compensation region31is arranged below the body region13and distant to the body region13in the vertical direction of the semiconductor body100. The coupling arrangement40, from which only one coupling cell is illustrated inFIG. 8, includes a control electrode41that is dielectrically insulated from the semiconductor body100by a control electrode dielectric42. The control electrode41extends from the body region13to or into the compensation region31. The control electrode41extends through a section11′ of the drift region11that separates the body region13from the compensation region31. In this section11′ of the drift region11achannel region43of the coupling arrangement is formed along the control electrode dielectric42between the body region13and the compensation region31.

The control electrode41is electrically connected to the control electrode G2in a manner which is not illustrated in detail inFIG. 8. The control electrode41can be implemented with a conventional electrode material, such as a metal or a highly doped polycrystalline semiconductor material, such as polysilicon. The control electrode dielectric42can be implemented with a conventional dielectric material, such as an oxide, a nitride, or a high-k-dielectric.

The control electrode41serves to control an inversion channel in the channel region43between the compensation region31and the body region13. This channel is a channel for p-type charge carriers when the compensation region31and the body region13are p-doped, and is a conducting channel for n-type charge carriers when the compensation region31and the body region13are n-doped. The coupling arrangement40is in the first operating state, when the control electrode41, by applying a suitable drive potential to the control terminal G2, is driven to generate the inversion channel in the channel region43. In an n-type MOSFET, in which the source region12is n-doped and the body region13is p-doped, an inversion channel is generated in the channel region43between the body region13and the compensation region31when an electrical potential is applied to the control terminal G2that is below the source potential, which is the electrical potential of the body region13, the source region12and the source electrode51, respectively. According to one embodiment, a voltage to be applied between the control terminal G2and the source electrode51or the source terminal S in order to generate a conducting channel is in the range of between −0.1 V and −15V. In a p-type MOSFET, in which the source region12is p-doped and the body region13is n-doped, the electrical potential to be applied to the control terminal G2is a positive potential relative to the source potential in order to generate a conducting channel in a channel region43. A voltage, to be applied between the control terminal G2and the source terminal S is, for example, in the range of between 0.1 V and 15V.

The coupling arrangement40is in the second operating state when the control electrode41is driven such that there is no conducting channel along the control electrode dielectric42between the body region13and the compensation region31. In this case, the compensation region31is floating. The coupling arrangement40is in the second operating state when the absolute value of a voltage applied between the control terminal G2and the source terminal S is below a threshold value. This threshold value is, for example, between 0.5 V and 2V.

The MOSFET according toFIGS. 3 to 8can be used like a conventional MOSFET as an electronic switch for switching an electronic load, as it has been explained with reference toFIG. 1. However, the MOSFET according toFIGS. 3 to 8, besides the gate terminal G, has at least one control terminal through which the operating state can be varied in order to adjust the output capacitance and the on-resistance, respectively. The MOSFET acts like a conventional superjunction MOSFET when the coupling arrangement40is in the first operating state. In this case, the compensation region31is electrically coupled to the body region13through the conducting channel in the channel region43along the control electrode dielectric42. Further, the MOSFET can be operated with a reduced output capacitance, but an increased on-resistance when the coupling arrangement40is operated in the second operating state, so that the conducting channel between the body region13and the compensation region31is interrupted and so that the compensation region31is floating. In this second operating state the MOSFET still acts like a conventional superjunction device, but one with another set of electrical data, in particular with another output capacitance and another on-resistance.

The geometry of the control electrode41and the control electrode dielectric42in the horizontal plane may correspond to the transistor cell geometry. This is explained next with reference toFIGS. 9 to 11in which schematically horizontal cross sectional views of MOSFETs with different cell geometries are illustrated in horizontal section planes that correspond to horizontal section plane B-B illustrated inFIG. 8.

FIG. 9illustrates a horizontal cross sectional view of a MOSFET having a stripe cell geometry, so that the body region13has a stripe geometry. Section plane B-B does not cut through the body region13. However, for a better understanding the position and the geometry of the body region13is also illustrated in dashed lines inFIGS. 9 to 11.

Referring toFIG. 9, the compensation region31, the control electrode41and the control electrode dielectric42also have a stripe geometry. In the embodiment illustrated inFIG. 9a width of the compensation region31is smaller than a width of the body region13. The “width” in this connection is the dimension of the compensation region31and the body region13in a direction perpendicular to a longitudinal direction of the compensation region31and the body region13. However, having a compensation region31with a lower width than the body region13is only an example. It is also possible to implement the compensation region31and the body region13with the same width, or to implement the compensation region31with a larger width than the body region13. This also applies to the other embodiments explained with reference toFIGS. 10 and 11below.

FIG. 10illustrates a horizontal cross sectional view of a MOSFET with a rectangular, specifically with a square cell geometry. In this example, the body region13has a rectangular, specifically a square geometry. The compensation region31also has a rectangular, specifically a square geometry. The control electrode41also has a rectangular, specifically a square geometry.

FIG. 11illustrates an embodiment, in which a transistor cell has a hexagonal geometry, the compensation region31has a hexagonal geometry, and the control electrode41has a hexagonal geometry. In this connection it should be noted that besides a hexagonal geometry any other polygonal geometry may be used as well.

Implementing the body region13, the compensation region31and the control electrode41with same geometries is not mandatory. The geometry of the compensation region31could also be different from the geometry of the body region13, and the geometry of the control electrode41could also be different from the geometry of the compensation region31. For example, each of the following geometries can be used independently for each of the body region13, the compensation region31and the control electrode41: rectangular, square, hexagonal, polygonal, circular.

FIG. 12illustrates a horizontal cross sectional view of a MOSFET in which the individual transistor cells have a rectangular geometry, i.e. the body regions13have a rectangular geometry, in which the compensation regions31also have a rectangular geometry. The control electrode41has a stripe geometry, so that one control electrode41is common to several transistor cells. Implementing the compensation region31with the same geometry as the body region13is only an example. It is also possible to implement the body region13and the compensation region31with different geometries.

FIG. 13illustrates an embodiment in which the compensation region31has a stripe geometry and in which several control electrodes41each having a rectangular geometry are coupled to one compensation region31. Instead of a rectangular geometry a circular, hexagonal or any other polygonal geometry may be used for the control electrode41as well.

The connection of the control electrode41to the control terminal G2is only schematically illustrated inFIG. 8. The control terminal G2may be implemented as an electrode that is arranged above the semiconductor body100and to which the control electrode41is connected to at a position which is not illustrated in the vertical cross sectional view illustrated inFIG. 8.

FIG. 14schematically illustrates a perspective sectional view of a MOSFET with stripe transistor cells in order to illustrate one possible way of contacting the (buried) control electrode41. InFIG. 14, only one transistor cell of the MOSFET is illustrated. This transistor cell has a stripe geometry, and the compensation region31and the control electrode41also have a stripe geometry. The control electrode41essentially extends parallel to the compensation region31and the body region13between the body region13and the compensation region31. The control electrode41, in this example, includes a connection electrode44which in the vertical direction of the semiconductor body extends through the body region13, and the source region12to a contact electrode45(shown inFIG. 15) that is connected to the control terminal G2or that forms the control terminal G2.

FIG. 15illustrates a schematic vertical cross sectional view of the MOSFET ofFIG. 14in a section plane C-C that cuts through the region of the MOSFET in which the connection electrode44and the contact electrode45are arranged. As can be seen fromFIG. 14, the control electrode41and the connection electrode44are dielectrically insulated from the body and source regions13,12by the control electrode dielectric42. The contact electrode45is arranged above the semiconductor body100and is electrically insulated from the gate electrode21. An electrical insulation between the contact electrode45and the gate electrode21can be provided by the same insulation layer and/or dielectric layer23that is arranged between the gate electrode21and the source electrode51. Optionally, the control electrode dielectric42is also arranged between the contact electrode45and the gate electrode21.

The source electrode51is arranged distant to the contact electrode45in a lateral direction and is electrically insulated from the source electrode51by an insulation layer. Referring toFIG. 15, the source region12and the gate electrode21may also be arranged below the contact electrode45. However, providing the source region12and the gate electrode21below the contact electrode45is optional. According to a further embodiment, the source region12and the gate electrode21do not extend to below the contact electrode45. The control electrode41, the connection electrode44and the contact electrode45can be formed from the same conducting material such as, e.g., a metal or a highly doped polycrystalline semiconductor material. However, it is also possible to implement these electrodes41,44,45with different electrode materials. In a manner not illustrated in detail, the contact electrode45may be connected to control electrodes41of a plurality of transistor cells each through a connection electrode44.

In the embodiment illustrated inFIG. 14, the control electrode41has an elongated (stripe) geometry and extends along the compensation region31and the body region, so that the compensation region31can be electrically connected to the body region13along its complete longitudinal length. However, this is only one possible example.

Referring toFIG. 16it is also possible to provide the control electrode41only at one position or to provide several control electrodes41at different positions along the compensation region31.FIG. 16illustrates a schematic perspective sectional view of a MOSFET in which the control electrode41does not completely extend along the compensation region31, but is only arranged below the connection electrode44.

According to one embodiment, the MOSFET includes both, transistor cells that are coupled to the body region13and the source electrode51, respectively, via a coupling arrangement40, and conventional transistor cells. A “conventional transistor cell” is a transistor cell that has its compensation region permanently connected to the body region13. For illustration purposes only, a schematic perspective sectional view of a conventional transistor cell with a stripe geometry is illustrated inFIG. 17. Of course, any other cell geometry may be implemented as well. In the transistor cell ofFIG. 18, a compensation region31′ adjoins the body region13and is, therefore, electrically connected to the source electrode51. In the conventional cell ofFIG. 17, like reference characters denote like regions as in the transistor cells explained with reference toFIGS. 3 to 16.

In the following, conventional transistor cells are referred to as transistor cells of a first type, while transistor cells with a coupling arrangement40are referred to as transistor cells of a second type. The individual transistor cells may be implemented such that they include one common drift region and one common drain region.

Transistor cells of the first and second type can be arranged in the semiconductor body100in many different ways. According to a first embodiment that is illustrated inFIG. 19, the transistor cells of the first and second type are arranged alternately.FIG. 18illustrates a horizontal cross sectional view in a section plane that corresponds to section plane B-B inFIG. 8and that cuts through the compensation regions31,31′. In the embodiment ofFIG. 19, the transistor cells and the compensation regions31,31′ have a stripe geometry. However, any other cell geometry and compensation region geometry may be used as well.

According to a further embodiment illustrated inFIG. 19, which also shows a horizontal cross sectional view of the semiconductor body, a group of several cells of the second type (having a compensation region31) is arranged next to a group of several cells of the first type (having a compensation region31′).

According to one embodiment, in a MOSFET that includes transistor cells of the first and second type, the transistor cells of the second type are implemented without a channel region, which means without a source region12and/or without a gate electrode21.

A vertical cross sectional view of a transistor cell of the second type which does not include a source region is illustrated inFIG. 20. The gate electrode21(illustrated in dashed lines) is optional in this case. In a MOSFET with transistor cells of the first and second type, the transistor cells of the second type, which are those cells that have their compensation regions coupled to the source or body region through a coupling arrangement, only serve to adjust the output capacitance and the on-resistance when they are implemented without channel region. The current flowing through the drift region11when the MOSFET is in its on-state is only provided through the channel regions of the transistor cells of the first type. The “channel regions” of the conventional cells are the regions in the body region12from the source along the gate dielectric22of the conventional cells to the drift region11(seeFIG. 17).

The operating principle of a MOSFET with transistor cells of the first and second type will now be explained with reference toFIG. 21.FIG. 22illustrates a circuit diagram representing the MOSFET10. The circuit diagram includes a plurality of n first transistors111, . . . ,11n, each representing transistor cell of the first type or a group of transistor cells of the first type, and m second transistors121, . . . ,12m, each representing a transistor cell of the second type or a group of transistor cells of the second type. The individual cells can be implemented in one of the ways explained before.

The individual transistor cells are connected in parallel. This is represented inFIG. 22in that the drain source paths of the transistors1011, . . . ,101n,1021, . . . ,102mare connected in parallel and that the transistors have their gate terminals coupled together to form the gate terminal G. The transistors that represent the transistor cells of the second type have a control terminal besides the gate terminal for adjusting the output capacitance and the on-resistance. In the embodiment illustrated inFIG. 22, the cells of the second type have their control terminals coupled together to form the control terminal G2of the MOSFET.

The MOSFET can be operated with a first on-resistance and a first output capacitance, when the cells of the second type are operated such that the coupling arrangement is in the first operating state, so that the compensation regions of the cells of the second type are electrically connected to one the body region, the source region, and the source electrode. The MOSFET can also be operated with a second on-resistance that is higher than the first on-resistance and with a second output capacitance that is lower than the first output capacitance, when the cells of the second type are operated such that the coupling arrangement is in the second operating state, so that the compensation regions of the cells of the second type are floating. A ratio between the first and the second on-resistance and between the first and the second output capacitance is dependent on a ratio between the overall size of the active areas of the transistor cells of the first type and the overall size of the active areas of the transistor cells of the second type. Assume, for example, that the individual cells have identical sizes. In this case, the overall size of the active areas of the cells of the first type and of the cells of the second type is proportional to the number of cells of the first and second type, respectively. According to one embodiment, the size ratio ACON/ACAbetween the overall size of the active areas of the cells of the first type and the overall size of the active areas of the cells of the second type is between 10:1 and 1:10, in particular between 2:1 and 1:2, or even 1.5:1 and 1:1.5.

Referring to a further embodiment, illustrated inFIG. 22, the MOSFT includes a plurality of p, with p≧2 of control terminals G21, G2p. Each of these control terminals G21, G2pserves to control the operating state of a coupling arrangement40of a group of cells of the second type, where each of these groups includes at least one cell of the second type.

In the MOSFT ofFIG. 23, the on-resistance and the output capacitance may each be adjusted to p+1 different values by varying the number of the groups of cells of the second type that are operated in the first or second operating state.

In the embodiments explained before, the coupling arrangement40acts like a switch that, dependent on a drive signal applied to the control terminal, electrically connects the compensation region31to one of the body region13, source12, and source electrode51or leaves the compensation region31floating.

According to a further embodiment illustrated inFIG. 23, the coupling arrangement also controls a current that may flow between the compensation region31and one of the body region13, source12, and source electrode51. For this, the coupling arrangement40may be implemented like a variable resistor having a resistance controlled by a drive signal applied to the control terminal G2. When the resistance of this variable resistor is controlled to be very high, the compensation region31is not discharged or is only very slowly discharged when the MOSFET switches on, while the compensation region31is rapidly discharged when the resistance is low. The variable resistor may be implemented with a control electrode41and dielectric42as shown inFIG. 8, wherein the resistance between the compensation region31and the body region13or source electrode can be adjusted by suitable selecting the drive potential applied to the control electrode41.

The output capacitance COSSof the MOSFET not only influence switching losses of the MOSFET, but also influences the dynamic behavior of the MOSFET, such as the slope of rising and falling edges of load current through the MOSFET and of the drain-source voltage, when the MOSFET is switched on and off, where a low output capacitance COSSmay result in steep slopes. Adjusting the maximum discharging current that may flow from the compensation region31to a low value may result in a low output capacitance at the of time switching, and may therefore result in steep switching slopes. The compensation region31is nevertheless discharged after a while, resulting in a low on-resistance after a delay time after the time of switching.

The coupling arrangement40could also be implemented with circuit elements that are capable of controlling or limiting the current between the compensation region31and one of the source electrode51, the body region13, the source region12, and the gate electrode21dependent on a drive signal applied to the control terminal G2. In particular, the coupling arrangement40can be configured to limit the current to or from the compensation region31to a maximum value that is dependent on the control signal at the control terminal. Conventional controllable current limiters may be used in this connection.

Referring to what has been explained before, there is a tradeoff between ohmic losses and capacitive losses, wherein this tradeoff is dependent on the load condition of the transistor. The load condition is, for example, defined by the load current flowing through the transistor in its on-state and/or by a switching frequency at which the transistor is operated. When, for example, the load current is high, it is desirable to reduce the on-resistance in order to decrease the ohmic losses, even if this results in a small increase of the total switching losses. Although the capacitive losses are independent of the current the switching losses in transition phases during turn-on and/or during turn-off increase at high load currents. The ohmic losses mainly govern the overall losses at high load currents because they increase with the square of the load current. According to one embodiment the MOSFET is, therefore operated such that with increasing load current the on resistance is reduced, while with increasing switching frequency the output capacitance is reduced.

The on-resistance can be reduced by driving the transistor cells of the second type such that the number of cells that are operated in the first operating state is increased.

The output capacitance can be reduced by driving the transistor cells of the second type such that the number of cells that are operated in the second operating state is increased.