Circuit device

A circuit device having superior mechanical strength at the interface between a circuit board and heat sink and superior efficiency for radiating heat from a circuit element to the heat sink through the circuit board. The circuit device includes the metal-based insulation board for installing the circuit element, and the heat sink, over which the insulation board is installed with a paste arranged therebetween. The insulation board has a projection arranged on the surface facing the heat sink along a peripheral portion. At least part of the projection contacts the heat sink through the paste layer.

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-278017, filed on Sep. 26, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a circuit device.

Electronic circuit devices conventionally include electronic circuits installed on a metal-based circuit board. The circuit board is bonded on a heat sink (base substrate), which is used to transfer heat.FIG. 1is a cross-sectional view briefly schematically showing a conventional circuit device. A circuit element6, which is a heat-generating body, is adhered to a circuit board3with solder5, and the circuit board3is adhered to a heat sink8via an adhesive layer7. When the circuit board3and heat sink8are adhered by means of the adhesive layer7, the adhesive layer7may harden such that the circuit board3is in an inclined state relative to the heat sink8. This causes the thickness of the adhesive layer7to become uneven and reduces the thermal transfer efficiency between the element6on the board3and the heat sink8. Moreover, the thermal expansion difference increases between the board3and the heat sink8such that cracks are generated in the adhesive layer7so as to cause concern that the board3may separate from the heat sink8. To address this problem, Japanese Laid-Open Patent Publication No. 5-121603 describes art in which a spacer is provided between the circuit board3and the heat sink8so as to make the adhesive layer7have a uniform thickness.

FIG. 2is a schematic cross-sectional diagram of a hybrid integrated circuit device introduced in the above publication. A circuit element6, which includes a heat-radiating body such as a power transistor or the like, is fixed to a board3with solder5. Spacers50are mixed into an adhesive layer7and applied to the heat sink8. The board3is adhered to the heat sink8by means of the spacers50. The spacers50are formed from a material that has satisfactory thermal conductivity and include, for example, metal grains having the same diameter or short glass fibers having the same length.

The circuit device ofFIG. 2, however, can not ensure sufficient friction force between the board3and spacers50and between the spacers50and the heat sink8when the board3is adhered to the heat sink8. Therefore, the board3is unstable with regard to external forces when the adhesive layer7is cured such that the board3may easily move. Accordingly, positioning of the board3is difficult. Furthermore, there is a possibility that the board3may be displaced from its designated position on the heat sink8and be fixed at that position.

SUMMARY OF THE INVENTION

The present invention provides a circuit device in which the circuit board is easily positioned and stably fixed on a base substrate so that the circuit board does not become inclined or displaced relative to the base substrate.

One aspect of the present invention is a circuit device including a base member. A circuit board is arranged over the base member. The circuit board has a peripheral portion and a first surface facing toward the base member. A paste is arranged between the circuit board and the base member. The circuit board includes a projection arranged on the first surface along the peripheral portion, with at least part of the projection extending through the paste and contacting the base member.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A circuit device10according to a further embodiment of the present invention will now be discussed with reference to the drawings.

FIG. 3is a schematic side view showing a cross-section of the circuit device10. The circuit device10is provided with a metal-based insulation board3a. The insulation board3aincludes a metal substrate1and a wiring layer2formed thereon. The wiring layer2is formed by laminating an insulative layer and a conductive layer. A projection4extends downward from a peripheral portion of the bottom surface of the metal substrate1, which defines a lower surface of the insulation board3a. A circuit element6is fixed to the upper surface of the insulation board3awith solder5. The insulation board3ais placed on a heat sink8with a heat radiating grease7aarranged in between. At least part of the projection4formed on the bottom surface of the metal substrate1extends through the heat radiating grease7aso that a distal portion of the projection4comes into contact with the heat sink8.

InFIG. 3, the circuit element6serves as a “circuit element” of the present invention, the metal-based insulation board3aserves as a “circuit board” of the present invention, the metal substrate1serves as a “metal substrate” of the present invention, the projection4serves as a “projection” of the present invention, the heat radiating grease7aserves as a “paste” of the present invention, and the heat sink8serves as a “base member” of the present invention.

FIG. 4is a schematic perspective view showing the lower surface of the insulation board3aofFIG. 3. As shown inFIG. 4, the projection is formed integrally with the peripheral portion of the bottom surface of the metal substrate1.

The structure of the circuit device10shown inFIG. 3will now be described referring toFIGS. 5 through 11which show the manufacturing process of the circuit device10.FIGS. 5athrough5mandFIGS. 6 through 8show the processes for manufacturing the insulation board3aofFIG. 3.

First Process (refer toFIG. 5a): A metal substrate1is formed with a multilayer structure (three-layer structure) having a thickness of approximately 100 μm to approximately 3 mm (for example, approximately 1.5 mm). The substrate1is formed by cladding material, which includes-a lower metal layer1aformed from copper, an intermediate metal layer1bformed from an Fe—Ni alloy (so-called invar alloy) on the lower metal layer1a, and an upper metal layer1cformed from copper on the intermediate metal layer1b. The copper lower metal layer1aand upper metal layer1chave a thermal expansion coefficient of approximately 12 ppm/° C. The invar alloy intermediate metal layer1bincludes Fe containing approximately 36% of Ni and has a low thermal expansion coefficient of approximately 0.2 ppm/° C. to 5 ppm/° C. That is, the thermal expansion coefficient of the intermediate metal layer1b(approximately 0.2 ppm/° C. to 5 ppm/° C.) is lower than the thermal expansion coefficient of the lower metal layer1aand upper metal layer1c(approximately 12 ppm/° C.). The thickness ratio of the lower metal layer1a, intermediate metal layer1b, and upper metal layer1cis approximately 1:1:1. This ratio is adjusted so that the thermal expansion coefficient of the substrate1is at approximately 6 ppm/° C. to 8 ppm/° C.

Second Process (refer toFIG. 5b): A copper oxide film1dhaving a thickness of approximately 0.1 μm to 0.3 μm is formed on the upper surface of the uppermost one of the three layers (1athrough1c) forming the substrate1, that is, the upper metal layer1c. The copper oxide film1dis formed by natural oxidation on the upper surface of the upper metal layer1c. In the present embodiment, the crystal grain boundary of the substrate1is selectively etched so that the substrate1has an irregular upper surface with an arithmetic mean roughness Ra of approximately 10 to 20 μm. This increases the adhesion between the substrate1(copper oxide film1d) and a resin layer formed thereon. The substrate1formed by the lower metal layer1a, the intermediate metal layer1b, the upper metal layer1c, and the copper oxide film1dserves as the “metal substrate” of the present invention.

Third Process (refer toFIG. 5c): A first resin layer12, which is mainly composed of an epoxy resin and has a thickness of approximately 60 to 160 μm, is formed on the irregular surface of the substrate1(copper oxide film1d). This resin layer12functions as an insulative layer. The resin layer12further has a thermal expansion coefficient of approximately 17 to 18 ppm/° C.

In the present embodiment, a filler having a maximum grain size of 15 μm or less is added to the resin layer12to increase the thermal conductivity of the resin layer12, the main component of which is epoxy resin. The filler may be alumina (Al2O3), silica (SiO2), aluminum nitride (AlN), silicon nitride (SiN), boron nitride (BN), and the like. The filler has a volume filling percentage of approximately 60 to 80%. The epoxy resin containing the added filler of alumina or silica has a thermal conductivity of approximately 2 W/(m·K), which is higher than the thermal conductivity of epoxy resin without the added filler (approximately 6 W/m·K). After forming the resin layer12, a copper foil13dis adhered onto the resin layer12.

Fourth Process (refer toFIG. 5d): The copper foil13dundergoes photolithography and etching to be patterned. This removes copper foil at locations that undergo laser irradiation to form via holes in the next process (fifth process). When a CO2laser is used, this process is required since the copper foil would reflect the majority of the laser light. When a UV laser is used, processing variations are reduced.

Fifth Process (refer toFIG. 5e): The patterned copper foil13dis irradiated from above by a CO2gas laser or UV laser. This removes regions from the surface of the exposed resin layer12to the surface of the substrate1. Thus, five via holes12aand two via holes12b, each having a diameter of approximately 100 μm, are formed extending through the resin layer12. Thermal via portions13aand13b(refer toFIG. 5g), which will be described later, are respectively formed using the via holes12aand12b.

Sixth Process (refer toFIG. 5f): Electroless plating is performed to plate copper to a thickness of approximately 0.5 μm on the upper surface of the copper foil13d(refer toFIG. 5e) and on the surface of the via holes12aand12b. Then, electrolytic plating is performed to plate copper on the upper surface of the copper foil13dand in the via holes12aand12b. In the present embodiment, an inhibitor and accelerant is added to the plating liquid. The inhibitor is adsorbed into the upper surface of the copper foil13d, and the accelerant is adsorbed into the surfaces of the via holes12aand12b. This increases the thickness of the copper plating in the via holes12aand12b. As a result, a conductive layer13having a thickness of approximately 15 μm is formed on the resin layer12and embedded in the via holes12aand12b, as shown inFIG. 5f.

In the present embodiment, the intermediate metal layer1b, which is formed from an invar alloy containing Fe and Ni, is interposed between the lower metal layer1aand the upper metal layer1c, which are formed from copper. Therefore, in the copper plating process described above, the components of the intermediate metal layer1b, which is formed from an invar alloy, are eluted into the plating liquid. This prevents deterioration of the plating liquid.

Seventh Process (refer toFIG. 5g): Photolithography and etching are performed to pattern the conductive layer13. This forms a thermal via portion13aat a region that would be located below an LSI chip19(refer toFIG. 9), thermal via portions13bat regions that would be located below a chip resistor20(refer toFIG. 9), and wiring portions13cat regions separated from the edges of the thermal via portion13aby a predetermined distance.

Eighth Process (refer toFIG. 5h): A prepreg formed from an epoxy resin to which a filler such as alumina or silica is added is press-fitted so as to cover the conductive layer13. This forms a resin layer14having a thickness of approximately 60 to 160 μm. Then, copper foil15ehaving a thickness of approximately 3 μm is press-fitted on the resin layer14.

Ninth Process (refer toFIG. 5i): Photolithography and etching are performed to remove the copper foil15efrom positions that would be above via hole14aand14b(refer toFIG. 5j). This exposes the surface of the resin layer14at regions in which the via holes14aand14bare formed.

Tenth Process (refer toFIG. 5j): The copper foil15eis irradiated from above by CO2gas laser or UV laser to remove regions from the exposed surface of the resin layer14to the surface of the conductive layer13. Thus, five via holes14aand two via holes14bare formed to extend through the resin layer14having a diameter of approximately 100 μm.

Eleventh Process (refer toFIG. 5k): Electroless plating is performed to plate copper to a thickness of approximately 0.5 μm on the upper surface of the copper foil15e(refer toFIG. 5j) and on the surfaces of the via holes14aand14b. Then, electrolytic plating is performed to plate copper on the upper surface of the copper foil15eand in the via holes14aand14b. An inhibitor and accelerant are added to the plating liquid. The inhibitor is adsorbed into the upper surface of the copper foil15e, and the accelerant is adsorbed into the surfaces of the via holes14aand14b. This increases the thickness of the copper plating in the via holes14aand14b. As a result, a conductive layer15having a thickness of approximately 15 μm is formed on the resin layer14, and a conductive layer15is embedded in the via holes14aand14b.

Twelfth Process (refer toFIG. 5l): Photolithography and etching are performed to pattern the conductive layer15. This forms a thermal via portion15aat a region that would be located below the LSI chip19(refer toFIG. 9), wire bonding portions15bat regions separated from the edges of the thermal via portion15aby a predetermined distance, wiring portions15cat regions that would be located below the chip resistor20(refer toFIG. 9), and a wiring portion15dat a region that would be located below a lead21(refer toFIG. 9).

Thirteenth Process (refer toFIG. 5m): A solder resist layer16ais formed so as to cover the conductive layer15. The solder resist layer16afunctions as a protective layer for the conductive layer15. The solder resist layer16ais formed from a thermosetting resin such as melamine derivative, liquid crystal polymer, polyphenylene ether (PPE) resin, polyimide resin, fluororesin, phenol resin, polyamide-bis-meleimide, and the like. Liquid crystal polymer, epoxy resin, and melamine derivative are preferred materials of the solder resist layer16adue to their superior high frequency characteristics. A filler such as SiO2or the like may be added to the solder resist layer16a. The solder resist layer16amay be applied to or laminated on the conductive layer15.

Fourteenth Process (refer toFIG. 6): A plurality of wiring layers2, each having the structure shown inFIG. 5m, are arranged on the metal substrate1without excess spacing between the wiring layers2in order to increase productivity.FIG. 6is a view showing the upper surface (chip mounting surface) of the insulation board3a. In the fourteenth process, photolithography is performed to remove the solder resist layer16afrom positions above the thermal via portion15a, the wire bonding portions15b, and the wiring portions15cand15d. Furthermore, photolithography is also performed to remove parts of the solder resist layer16athat would come into contact with the blade of a metal die (not shown) to prevent separation of the solder resist layer16a.

Fifteenth Process (refer toFIG. 7): The insulation board3a(circuit board) is formed using a metal die to punch out the wiring layer2and metal substrate1from the upper surface of the circuit board toward the lower surface. As a result, burrs are formed as the projection4on the lower surface of the insulation board3a(that is, the lower surface of the metal substrate1), and saggings11are formed on the upper surface. The projection4is integrally formed with the metal substrate1when the metal substrate1is deformed. A projection would not be formed on the lower surface when the metal substrate1is punched from the lower surface of the circuit element. In such a case, since the insulative layer is brittle, the wiring layer2may be separated or damaged. The projection4serves as the “projection” of the present invention. The projection4eliminates the process for preparing and installing spacers since the insulation board3afunctions as a spacer when the insulation board3ais installed on the heat sink8. This reduces manufacturing time and cost.

Sixteenth Process (refer toFIG. 8):FIG. 8shows the insulation board3afrom above after it has been punched out by the metal die. Reference numbers15a,15b,15c, and15ddenote the exposed wiring layer2after the solder resist layer16ahas been removed through photolithographic patterning.

Seventeenth Process (refer toFIG. 9): The LSI chip19is installed as a circuit element6(refer toFIG. 3) on the thermal via portion15aof the conductive layer15by means of the resin layer16, which is formed from an epoxy resin and has a thickness of approximately 20 μm. The LSI chip19is formed from a monocrystal silicon substrate (not shown) having a thermal expansion coefficient of approximately 4 ppm/° C. The LSI chip19is electrically connected to the wire bonding portion15bof the conductive layer15by a wire17. The chip resistor20, which serves as the a circuit element6(refer toFIG. 3), is installed on the wiring portion15cof the conductive layer15by means of a fusion layer18a, which is formed from a brazing material such as solder, and is electrically connected to the wiring portion15cthrough the fusion layer18a. Furthermore, the lead21is installed on the wiring portion15dof the conductive layer15by means of the fusion layer18b, which is formed from a brazing material such as solder, and is electrically connected to the wiring portion15dthrough the fusion layer18a.

Eighteenth Process (refer toFIG. 10): An epoxy resin layer22is formed so as to cover and protect the LSI chip and chip resistor20. Thus, the circuit element6is sealed on the insulation board3a. As shown inFIGS. 9 and 10, the lead21is arranged on one side of the insulation board3a.

During the resin molding (eighteenth process), if the projection4were formed on the upper surface of the insulation board3a(the surface facing the resin layer22) as shown inFIG. 13, the projection4may interfere with the application of the resin when the resin is applied in a lateral direction of the drawing. However, in the present embodiment, the application of the epoxy resin to the insulation board is facilitated by the saggings11(rounded corners as shown inFIG. 10), which are produced during the punching.

Nineteenth Process (refer toFIGS. 11aand11b): The insulation board3a, which has the circuit element6sealed in the molded resin (resin layer22), is installed on the heat sink8. This forms a circuit device10(refer toFIG. 3). Lead pins32of the circuit device10are inserted into and soldered to a printed circuit board31. This connects the circuit device10to the printed circuit board31.FIG. 11ais a plan view of the circuit device10, andFIG. 11bis a cross-section view taken along line A-B inFIG. 11a. The lead pins32are integrally connected (not shown) to the lead21(refer toFIG. 10) by extending the lead21. Therefore, the lead pins32and the lead21(refer toFIG. 10) are equivalent.

The insulation board3aof the circuit device10is fastened by screws33(refer toFIG. 11a) to the heat sink8with the heat radiating grease7aarranged in between. When fastening the insulation board3a, the insulation board3aand heat sink8are securely bonded with each other (refer toFIG. 11b) by the anchor effect of the projection4(that is, the effect produced by the peaks on the projection4functioning as pegs or a wedge when the peaks enter fine recesses in the surface of the heat sink8). Furthermore, the projection4includes sections free from contact with the heat sink8since the projection4, which substantially extends along the entire periphery of the insulation board3a, does not necessarily have a uniform height (refer toFIG. 4). Such non-contact sections enable the release of air mixed in the heat radiating grease7aso that heat radiation is not hindered.

The circuit device10of the embodiment of the present invention has the advantages described below.

(1) The bottom surface of the insulation board3a, which is installed on the heat sink8with the heat radiating grease7aarranged in between, has a projection4(burrs) formed on the peripheral portion through punching. The projection4functions as a spacer to maintain a constant distance between the heat sink8and the insulation board3a. Therefore, the entire insulation board3ahas uniform heat radiating characteristics.

(2) The pressure per contact area is improved between the insulation board3aand the heat sink8since the projection4supports the insulation board3arelative to the heat sink8in the manner of legs. Thus, the vertical resistance and friction force are increased. Therefore, when the insulation board3ais installed on the heat sink8, the insulation board3aremains stable even when receiving external forces. This facilitates the positioning of the insulation board3a. Moreover, the stability prevents displacement of the insulation board3a.

(3) The projection4is arranged along the peripheral portion of the insulation board3a. This minimizes the possibility of the insulation board3abeing inclined relative to the heat sink8.

(4) The projection4is formed integrally with the insulation board3a. This prevents separation of the insulation board3aat the interface between the insulation board3aand the heat radiating grease7awhen the temperature increases.

(5) As shown inFIG. 12, the molded resin (resin layer22) on the insulation board3ais generally formed using silica as a filler, and the thermal expansion coefficient is approximately 15×10−6/K. The metal substrate1in the insulation board3a, however, is mainly formed of copper, which has a thermal expansion coefficient of about 16.6×10−6/K. Thus, since the thermal expansion coefficient of the molded resin is lower than the metal substrate1, the lower surface of the metal substrate1bends upward in the insulation board3awhen the temperature rises. However, in the present embodiment, the projection4(refer toFIG. 10) is formed integrally with the metal substrate1. This improves the rigidity of the metal substrate1and prevents such bending.

(First Modification) The present invention is also applicable to hybrid integrated circuit devices that have circuit elements6other than the LSI chip19and chip resistor20and to semiconductor integrated circuit devices other than a hybrid integrated circuit device.

(Second Modification) The second process (process for forming the copper oxide film1d) may be omitted. A copper nitride film may be formed on the surface of the substrate1, in lieu of the copper oxide film1d, by nitriding the surface of the substrate1.

(Third Modification) The substrate1may also be formed by interposing the intermediate metal layer1b, which is formed from an invar alloy, between a lower metal layer1aand upper metal layer1c, which are formed from aluminum. Alternatively, the substrate1may be formed by interposing the intermediate metal layer1b, which is formed from an invar alloy, between a copper lower metal layer1a(or upper metal layer1c) and an aluminum to metal layer1c(or lower metal layer1a). When the upper metal layer1cis formed of aluminum, the surface of the upper metal layer1cmay be oxidized using an anodic oxidation method such that an aluminum oxide film can be accurately formed on the surface of the upper metal layer1cto function as an insulative layer. An intermediate metal layer1bformed of an alloy containing approximately 32% Ni and approximately 5% Co in Fe (so-called super invar alloy), and an intermediate metal layer1bformed of an alloy containing approximately 29% Ni and approximately 17% Co in Fe may be used in place of the invar alloy intermediate metal layer1b.

(Fourth Modification) The thickness ratio of the lower metal layer1a, intermediate metal layer1b, and upper metal layer1cneed not be 1:1:1, and may be set, for example, at 1:3:1.

(Fifth Modification) The circuit device10is not limited to a bi-layer structure (conductive layers13and15). The circuit device10may have a monolayer structure (for example, the conductive layer13alone). The circuit device10may have a tri-layer structure that includes a third insulative layer and conductive layer on a second conductive layer. The circuit device10may have a multi-layer structure of four or more layers.

(Sixth Modification) The maximum grain size of the filler material added to the resin layer12is not limited to 15 μm. The resin layer12may also include a filler having a grain size of approximately 15 μm and a filler having a grain size of approximately 0.7 μm.

(Seventh Modification) The metal substrate1is not limited to a tri-layer structure that includes the lower metal layer1a, intermediate metal layer1b, and upper metal layer1c. The metal substrate1may also have a multi-layer structure of four or more layers. Further, the metal substrate1may include at least one of a resin layer, a ceramic layer, and a semiconductor layer.

(Eighth Modification) The insulation board3a(circuit board) may be formed by only the metal substrate1, as shown inFIG. 16.

(Ninth Modification) In addition to the projection4that changes height in long intervals along the peripheral portion of the metal substrate1(refer toFIG. 4), the “projection” of the present invention may be a projection4having a substantially uniform height along the entire peripheral portion (refer toFIG. 14) or a projection4that changes height in short intervals along the peripheral portion (refer toFIG. 15). The “projection” may also be absent at certain parts in the peripheral portion, as indicated by arrow A inFIG. 15.

(Tenth Modification) The projection4is not limited to burrs formed when punching the insulation board3awith a metal die. A new process may be added to form a projection4that is not a burr.

(Eleventh Modification) The method for adhering the circuit element6to the insulation board3ais not limited to soldering. For example, a wire attached to the circuit element6may function as a leg to support the circuit element6on the insulation board3a.

(Twelfth Modification) The “paste” is not limited to thermally conductive grease (heat radiating grease7a) and also includes adhesives or an insulative layer and resin layer used for adhesive purposes.