Semiconductor device and inverter using same

A semiconductor device includes a gate pad, a first source pad and a second source pad insulated from each other, a drain pad, a main region, and a sense region for detecting a forward current and a reverse current. The main region and the sense region each include a plurality of unit cells which are in parallel connection, the number of unit cells in the sense region being smaller than the number of unit cells in the main region. A source electrode of any unit cell in the main region is connected to the first source pad, and a source electrode of any unit cell in the sense region is connected to the second source pad.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device having a silicon carbide semiconductor layer, and an inverter in which the same is used.

BACKGROUND ART

In recent years, vigorous development has been directed to power devices in which a silicon carbide semiconductor. Silicon carbide (SiC) is a semiconductor material with a high hardness, having a larger band gap than that of silicon (Si). Silicon carbide has dielectric breakdown field which is one order of magnitude higher than that of silicon. Therefore, use of silicon carbide makes it possible to produce a semiconductor device which has the same breakdown voltage as, but a smaller volume than, in the case of using silicon. Use of silicon carbide allows those constituent elements which serve as resistance components to be reduced as compared to using silicon, thereby making it possible to reduce the ON resistance of the semiconductor device and decrease its power loss. A silicon carbide semiconductor device also has an advantage of being able to operate at a higher temperature than is possible with silicon. A silicon carbide semiconductor device is used as a switching element composing a switching circuit, for example.

Some attempts at reducing losses in switching circuits have been made, which involve control of switching element operations (see, for example, Patent Document 1).

Patent Document 1 discloses a technique of, in a switching circuit composed of a half bridge circuit in which metal-oxide-semiconductor field effect transistors (MOSFETs) are used as switching elements, providing a transistor current detection means to detect a current flowing in a low-side MOSFET and a diode current detection means to detect a current flowing in the body diode of the low-side MOSFET functioning as a free-wheel diode, to thereby reduce recovery losses while suppressing the through-current.

Specifically, according to Patent Document 1, in a vertical MOSFET, a diode electrode is provided so as to achieve ohmic contact with the body region but without contact with the source region, the diode electrode being deployed in an electrically insulated state from the source electrode. Thus, by detecting a current flowing between the source electrode and the drain electrode, a current flowing through the MOSFET is detected, and by detecting a current flowing between the diode electrode and the drain electrode, a current flowing through the body diode can be detected. Among a plurality of unit cells, some unit cells have a means that detects a current between the source electrode and the drain electrode and a means that detects a current between the diode electrode and the drain electrode, which respectively function as the transistor current detection means and the diode current detection means. Patent Document 1 states that recovery losses can be reduced while suppressing the through-current, by setting a dead time so that the through-current which is detected by the transistor current detection means and the recovery current which is detected by the diode current detection means are both small.

On the other hand, Patent Document 2 discloses, in such an inverter as drives a motor, a construction including a transistor bridge circuit which is composed of a plurality of transistors and a diode bridge circuit which is composed of a plurality of diodes that are free-wheel diodes, where a first current detector is disposed across a plus line and a minus line between the transistor bridge circuit and the diode bridge circuit, and a second current detector is disposed between the transistor bridge circuit and diode bridge circuit and a DC power source. Patent Document 2 states that a driving current which flows during usual driving a reverse current which flows in a backflow operation, and a regenerative current which flows in a regeneration operation can be detected by using the first current detector and the second current detector, whereby an overcurrent occurring in each operation can be detected.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

However, the technique disclosed in Patent Document 1 requires, in order to detect a current flowing through the free-wheel diode, a diode current detection means to be provided in addition to the transistor current detection means, thus resulting in a complicated construction. The technique disclosed in Patent Document 2 features a construction in which the bridge circuit is two-divided into a diode bridge circuit and a transistor bridge circuit, thus resulting in long interconnects and a complicated construction. Moreover, current detectors for large current detection, which are expensive and large in size, are needed.

Therefore, the technique disclosed in the present specification provides a semiconductor device which can detect both a current flowing through a transistor and a current flowing through a free-wheel diode with a simple construction, and an inverter in which the same is used.

Solution to Problem

A semiconductor device which is disclosed in the present specification comprises: a semiconductor substrate of a first conductivity type, including a main region and a sense region; a plurality of unit cells provided in the main region and in the sense region of the semiconductor substrate of the first conductivity type, each unit cell having a metal-insulator-semiconductor field effect transistor, the number of unit cells in the sense region being smaller than the number of unit cells in the main region, the metal-insulator-semiconductor field effect transistors being connected in parallel connection in each of the main region and the sense region; a gate pad on a principal face side of the semiconductor substrate; a first source pad and second source pad insulated from each other; and a drain pad on a back side of the semiconductor substrate, each metal-insulator-semiconductor field effect transistor including a first silicon carbide semiconductor layer of the first conductivity type located on the principal face of the semiconductor substrate, a body region of a second conductivity type in contact with the first silicon carbide semiconductor layer, a source region of the first conductivity type in contact with the body region, a second silicon carbide semiconductor layer on the first silicon carbide semiconductor layer and in contact with at least a portion of the body region and at least a portion of the source region, a gate insulating film on the second silicon carbide semiconductor layer, a gate electrode on the gate insulating film, a source electrode in contact with the source region, and a drain electrode on the back side of the semiconductor substrate, wherein, given that Vds is a potential of the drain electrode relative to a potential of the source electrode, Vgs is a potential of the gate electrode relative to the potential of the source electrode, and Vth is a gate threshold voltage of the metal-insulator-semiconductor field effect transistor, when Vds is positive, the metal-insulator-semiconductor field effect transistor allows a current to flow from the drain electrode to the source electrode if Vgs is equal to or greater than Vth, when Vds is negative, the metal-insulator-semiconductor field effect transistor functions as a diode to allow a current to flow from the source electrode to the drain electrode if Vgs is less than Vth; an absolute value of an onset voltage of the diode is smaller than an absolute value of an onset voltage of a body diode which is constituted by the body region and the first silicon carbide semiconductor layer; the gate electrode of any unit cell in the main region and the gate electrode of any unit cell in the sense region are electrically connected to the gate pad; the drain electrode of any unit cell in the main region and the drain electrode of any unit cell in the sense region are electrically connected to the drain pad; the source electrode of any unit cell in the main region is electrically connected to the first source pad; and the source electrode of any unit cell in the sense region is electrically connected to the second source pad.

An inverter which is disclosed in the present specification comprises: a leg composed of an upper arm and a lower arm, at least one of the upper arm and the lower arm being the semiconductor device which is disclosed in the present specification; a current-voltage converter being connected to the second source pad of the semiconductor device, the current-voltage converter outputting a voltage of a value corresponding to the value of a current flowing between the drain pad and the second source pad; and a gate voltage controller for controlling a voltage to be applied to the gate pad of the semiconductor device based on the voltage output from the current-voltage converter.

Advantageous Effects of Invention

The semiconductor device disclosed in the present specification can detect both a current flowing through a transistor and a current flowing through a free-wheel diode, with a simple construction.

DESCRIPTION OF EMBODIMENTS

A semiconductor device of the present disclosure is generally as follows.

A semiconductor device according to an embodiment of the present disclosure comprises: a semiconductor substrate of a first conductivity type, including a main region and a sense region; a plurality of unit cells provided in the main region and in the sense region of the semiconductor substrate of the first conductivity type, each unit cell having a metal-insulator-semiconductor field effect transistor, the number of unit cells in the sense region being smaller than the number of unit cells in the main region, the metal-insulator-semiconductor field effect transistors being connected in parallel connection in each of the main region and the sense region; a gate pad on a principal face side of the semiconductor substrate; a first source pad and second source pad insulated from each other; and a drain pad on a back side of the semiconductor substrate, each metal-insulator-semiconductor field effect transistor including a first silicon carbide semiconductor layer of the first conductivity type located on the principal face of the semiconductor substrate, a body region of a second conductivity type in contact with the first silicon carbide semiconductor layer, a source region of the first conductivity type in contact with the body region, a second silicon carbide semiconductor layer on the first silicon carbide semiconductor layer and in contact with at least a portion of the body region and at least a portion of the source region, a gate insulating film on the second silicon carbide semiconductor layer, a gate electrode on the gate insulating film, a source electrode in contact with the source region, and a drain electrode on the back side of the semiconductor substrate, wherein, given that Vds is a potential of the drain electrode relative to a potential of the source electrode, Vgs is a potential of the gate electrode relative to the potential of the source electrode, and Vth is a gate threshold voltage of the metal-insulator-semiconductor field effect transistor, when Vds is positive, the metal-insulator-semiconductor field effect transistor allows a current to flow from the drain electrode to the source electrode if Vgs is equal to or greater than Vth, when Vds is negative, the metal-insulator-semiconductor field effect transistor functions as a diode to allow a current to flow from the source electrode to the drain electrode if Vgs is less than Vth; an absolute value of an onset voltage of the diode is smaller than an absolute value of an onset voltage of a body diode which is constituted by the body region and the first silicon carbide semiconductor layer; the gate electrode of any unit cell in the main region and the gate electrode of any unit cell in the sense region are electrically connected to the gate pad; the drain electrode of any unit cell in the main region and the drain electrode of any unit cell in the sense region are electrically connected to the drain pad; the source electrode of any unit cell in the main region is electrically connected to the first source pad; and the source electrode of any unit cell in the sense region is electrically connected to the second source pad.

At least a region of the body region that is in contact with the second silicon carbide semiconductor layer may have an impurity concentration of 1×1018cm−3or more; the second silicon carbide semiconductor layer may have an impurity concentration of not less than 1×1017cm−3and not more than 4×1018cm−3; and the second silicon carbide semiconductor layer may have a thickness of not less than 20 nm and not more than 70 nm.

The semiconductor device may further comprise: the first silicon carbide semiconductor layer of the first conductivity type at a boundary between the main region and the sense region, the first silicon carbide semiconductor layer being on the semiconductor substrate; and an element isolation region of the second conductivity type in the first silicon carbide semiconductor layer, wherein no second silicon carbide semiconductor layer is provided over the element isolation region.

The semiconductor device may further comprise a trench penetrating through the body region and the source region and reaching the first silicon carbide semiconductor layer.

A current to flow in the sense region may be 100 mA or less.

A current flowing between the drain pad and the second source pad may be in proportion to a current flowing between the drain pad and the first source pad.

The direction of a current flowing between the drain pad and the second source pad may be identical to the direction of a current flowing between the drain pad and the first source pad.

An inverter according to an embodiment of the present disclosure comprises: a leg composed of an upper arm and a lower arm, at least one of the upper arm and the lower arm being any of the aforementioned semiconductor devices; a current-voltage converter being connected to the second source pad of the semiconductor device, the current-voltage converter outputting a voltage of a value corresponding to the value of a current flowing between the drain pad and the second source pad; and a gate voltage controller for controlling a voltage to be applied to the gate pad of the semiconductor device based on the voltage output from the current-voltage converter.

The current-voltage converter may include: an operational amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal; and a resistor connecting the inverting input terminal and the output terminal.

The operational amplifier may be of a dual supply type.

The inverter may further comprise: a smoothing capacitor in parallel connection with the leg; a voltage detector for detecting a voltage across the smoothing capacitor; and a regenerative power consuming circuit including a resistor to consume a regenerative current flowing from a load to the inverter as heat and a switching element to control the regenerative current to be flowed to the resistor, wherein the gate voltage controller may compare the voltage across the smoothing capacitor as detected by the voltage detector against a reference voltage value, and if the voltage across the smoothing capacitor exceeds the reference voltage value, control the switching element to flow the regenerative current to the resistor.

The inverter may further comprise: a smoothing capacitor in parallel connection with the leg; and a voltage detector for detecting a voltage across the smoothing capacitor, wherein the gate voltage controller may compare the voltage across the smoothing capacitor as detected by the voltage detector against a reference voltage value, and if the voltage across the smoothing capacitor exceeds the reference voltage value, ensure that a negative voltage is applied to the gate pad.

The inverter may further comprise: a smoothing capacitor in parallel connection with the leg; and a regenerative power consuming circuit including a resistor to consume a regenerative current flowing from a load to the inverter as heat and a switching element to control the regenerative current to be flowed to the resistor, wherein the gate voltage controller may compare the value of the output voltage output from the current-voltage converter against a reverse reference voltage value, and if an absolute value of the output voltage exceeds the reverse reference voltage value, control operation of the switching element so that the regenerative current flows to the resistor.

The inverter may further comprise a smoothing capacitor in parallel connection with the leg, wherein the gate voltage controller may compare the value of the output voltage output from the current-voltage converter against a reverse reference voltage value, and if an absolute value of the output voltage exceeds the reverse reference voltage value, ensure that a negative voltage is applied to the gate pad.

A method of controlling an inverter according to an embodiment of the present disclosure is a method of controlling an inverter including a leg composed of an upper arm and a lower arm, at least one of the upper arm and the lower arm being any of the aforementioned semiconductor devices, and a smoothing capacitor in parallel connection with the leg, the method comprising: a step of detecting a voltage across the smoothing capacitor; and a step of comparing the voltage across the smoothing capacitor against a reference voltage value, and if the voltage across the smoothing capacitor exceeds the reference voltage value, ensuring that a negative voltage is applied to the gate pad.

A method of controlling an inverter according to an embodiment of the present disclosure is a method of controlling an inverter including a leg composed of an upper arm and a lower arm, at least one of the upper arm and the lower arm being any of the aforementioned semiconductor devices, a smoothing capacitor in parallel connection with the leg, a current-voltage converter being connected between the semiconductor device and the second source pad and outputting a voltage of a value corresponding to the value of a current flowing between the drain pad and the second source pad, and a regenerative power consuming circuit including a resistor to consume a regenerative current flowing from a load to the inverter as heat and a switching element to control the regenerative current to be flowed to the resistor, the method comprising: a step of detecting the value of the output voltage output from the current-voltage converter; and a step of comparing the value of the output voltage output from the current-voltage converter against a reverse reference voltage value, and if an absolute value of the output voltage exceeds the reverse reference voltage value, operating the switching element so that the regenerative current flows to the resistor.

A method of controlling an inverter according to an embodiment of the present disclosure is a method of controlling an inverter including a leg composed of an upper arm and a lower arm, at least one of the upper arm and the lower arm being any of the aforementioned semiconductor devices, a smoothing capacitor in parallel connection with the leg, and a current-voltage converter being connected to the second source pad of the semiconductor device and outputting a voltage of a value corresponding to the value of a current flowing between the drain pad and the second source pad, the method comprising: a step of detecting the value of the output voltage output from the current-voltage converter; and a step of comparing the value of the output voltage output from the current-voltage converter against a reverse reference voltage value, and if an absolute value of the output voltage exceeds the reverse reference voltage value, ensures that a negative voltage is applied to the gate pad.

Hereinafter, with reference to the drawings, embodiments of the present disclosure will be described.

First Embodiment

Structure of the Semiconductor Device

FIG. 1(a)is a plan view generally showing a semiconductor device of the present embodiment.FIG. 1(b)is a cross-sectional view generally showing portion A-A′ inFIG. 1(a).FIG. 1(c)is a cross-sectional view generally showing a unit cell111inFIG. 1(b).FIG. 1(d)is a cross-sectional view showing enlarged the neighborhood of an element isolation region110shown inFIG. 1(b). The present embodiment will illustrate an example where the unit cell111is a metal-insulator-semiconductor field effect transistor (MISFET) of a planar type.

As shown inFIG. 1(a), the semiconductor device1includes a semiconductor substrate5. Also, it includes a main region source pad2, a sense region source pad3, and a gate pad4on a principal face5aside of the semiconductor substrate5. The main region source pad2, the sense region source pad3, and the gate pad4are electrically insulated from one another. A drain electrode16and a back side electrode17are layered on a back side5bof the semiconductor device1, so as to cover the entire back side5b.

The main region source pad2, the sense region source pad3, and the back side electrode17correspond to a first source pad, a second source pad, and a drain pad of the semiconductor device which is disclosed in the present specification.

As shown inFIGS. 1(a) and (b), the semiconductor device1has a sense region21and a main region20. The sense region21and the main region20each include a plurality of unit cells111, which are in parallel connection with one another.

The main region source pad2is composed of upper interconnects15of the plurality of unit cells111in the main region20being connected with one another. Similarly, the sense region source pad3is composed of upper interconnects15of the plurality of unit cells111in the sense region21being connected with one another.

In a first silicon carbide semiconductor layer6of a first conductivity type at the boundary between the sense region21and the main region20, unlike in unit cells, edge termination base regions18and19and an element isolation region110are provided. The edge termination base regions18and19and the element isolation region110are both of a second conductivity type. The edge termination base regions18and19do not include any source region of the first conductivity type because, if any source region were provided in the edge termination base regions18and19, a large current might flow in a parasitic bipolar which is composed of the source region, the edge termination base regions18and19, and the first silicon carbide semiconductor layer6, thus possibly destroying the semiconductor device1. A source electrode10is provided on the edge termination base regions18and19, so as to be electrically connected with source electrodes10of the unit cells111via the upper interconnects15. Therefore, the edge termination base regions18and19and the source regions8of the unit cell111are at the same potential. The edge termination base regions18and19constitute a PN diode with the first silicon carbide semiconductor layer6.

The element isolation region110is located between the edge termination base region18and the edge termination base region19. No source electrode10is provided on the element isolation region110, so that the potential of the element isolation region110is a floating potential. The element isolation region110prevents a current from flowing between the sense region21and the main region20.

As shown inFIG. 1(d), no second silicon carbide semiconductor layer11is provided above the element isolation region110or at edge portions of the edge termination base regions18and19. This prevents a current from flowing between the main region20and the sense region21via the second silicon carbide semiconductor layer11, thus allowing a current flowing in the sense region21to be detected in a distinguishable manner over a current flowing in the main region20.

Gate electrodes13of adjacent unit cells111are electrically connected to each other via a gate line not shown. The gate electrodes13in the main region20and the sense region21are all electrically connected to the gate pad4.

The following relational equation (1) holds true, assuming a ratio n of the number of cells in the main region to that in the sense region, a current Iss flowing in the sense region, and a current Ism flowing in the main region.
Ism=n×Iss(1)

Thus, from the current flowing in the sense region and the cell number ratio, a current flowing in the main region can be indirectly detected. Assuming a cell number ratio of about 1000, even if a current flowing in the main region is on the order of A, a current flowing in the sense region will be on the order of mA. Therefore, with a simple circuit for detecting a small current on the mA order, it is possible to indirectly detect a large current on the order of A.

Referring toFIG. 1(c), the structure of the unit cell111will be described. On the principal face of the n type semiconductor substrate5, the n type first silicon carbide semiconductor layer6is provided. As the semiconductor substrate5, an off-cut substrate which is off from the 4H—SiC(0001) plane by 4° in the [11-20] direction is used, for example. The n type impurity in the semiconductor substrate5has a doping concentration of about 1×1019cm−3. Moreover, for example, the n type impurity in the first silicon carbide semiconductor layer6has a doping concentration of about 7×1015cm−3, and the first silicon carbide semiconductor layer6has a thickness of about 13 μm.

A p type body region (well region)7is provided on the surface layer of the first silicon carbide semiconductor layer6. For example, the body region7has a depth of about 0.8 μm, and the p type impurity in the body region7has a doping concentration of 2×1018to 2×1019cm−3. An n type source region8is provided in the body region7. For example, the source region8has a depth of about 0.2 μm, and the n type impurity in the source region8has a doping concentration of about 5×1019cm−3. In the surface layer of the body region7, a p type contact region9is provided. For example, the contact region9has a depth of about 200 nm, and the p type impurity in the contact region9has a doping concentration of about 2×1020cm−3.

A source electrode10is provided in contact with a portion of the source region8and a portion of the contact region9. The source electrode10is made of nickel silicide having been formed through a heat treatment of nickel with a thickness of about 100 nm, for example. The source electrode10has ohmic contact with the source region8and the contact region9.

On the surface of the first silicon carbide semiconductor layer6including the source region8and the body region7, the second silicon carbide semiconductor layer11is provided. The second silicon carbide semiconductor layer11is an epitaxial layer which is epitaxially grown on the first silicon carbide semiconductor layer6, for example. In the case where the second silicon carbide semiconductor layer11is composed of a single n type layer, the thickness of the second silicon carbide semiconductor layer11may be 75 nm or less, and the doping concentration of the n type impurity in the second silicon carbide semiconductor layer11may be 1×1018cm−3or more, for example.

However, in the case where the second silicon carbide semiconductor layer11is composed of a single n type layer, any fluctuations in its doping profile may result in large fluctuations in the threshold voltage in the forward direction and the onset voltage of the channel diode. In some cases, the film thickness of the second silicon carbide semiconductor layer11may become reduced during the sacrificial oxidation and gate oxidation steps. Variation in the decrease in film thickness of the second silicon carbide semiconductor layer11during the production steps causes variation in the electrical characteristics of the semiconductor device1, e.g., threshold voltage in the forward direction and onset voltage in the reverse direction. Therefore, by stacking a low-concentration doped layer on the surface of the n type impurity layer, variation in the electrical characteristics of the semiconductor device1can be reduced.

Moreover, when the second silicon carbide semiconductor layer11is epitaxially grown, the growth rate may not be stable, and the impurity concentration may also not be stable, in the initial period of growth. In this case, a dopant gas may not be flowed in the initial period of growth, and an undoped layer or a low-concentration doped layer with residual nitrogen may be grown, and a high-concentration n type impurity layer may be grown only after the growth rate becomes stable. In this manner, fluctuations in the impurity concentration due to the unstable growth rate in the initial period of growth can be reduced.

In other words, the second silicon carbide semiconductor layer11may have a multilayer structure including a bottom layer composed of an undoped or low-impurity concentration n type layer, a high concentration n type impurity layer, and a capping layer composed of an undoped or low-impurity concentration n type layer. The respective layers may have the following thicknesses: for example, the bottom layer may be about 10 to about 50 nm; the high concentration n type impurity layer may be 15 to 30 nm; and the capping layer may be 10 to 100 nm. The respective layers may have the following n type impurity concentrations, for example: less than 1×1017cm−3for the bottom layer; about 1×1019to about 1×1019cm−3for the high concentration n type impurity layer; and less than 1×1017cm−3for the capping layer. Note that the impurity concentration in each layer does not need to be constant, but may have a distribution along the film thickness direction of the respective layer.

A gate insulating film12is provided on the second silicon carbide semiconductor layer11. The gate insulating film12has a thickness of about 70 nm.

The gate electrode13is provided on the gate insulating film12. For example, the gate electrode13is an n type poly-Si doped with about 7×1020cm−3of phosphorus, and the gate electrode13has a thickness of about 500 nm.

An interlevel dielectric film14is provided on the gate electrode13. The interlevel dielectric film14is made of a silicon oxide film, for example. The interlevel dielectric film14has a thickness of about 1 μm. The upper interconnect15, which is electrically connected with the source electrode10, is provided on the interlevel dielectric film14. The upper interconnect15is made of aluminum, for example. The upper interconnect15has a thickness of about 4 μm.

On the back side of the semiconductor substrate5, the drain electrode16is provided, which has ohmic contact with the semiconductor substrate5. The drain electrode16is made of titanium silicide having been formed through a heat treatment of Ti with a thickness of about 150 nm, for example. On the drain electrode16, the back side electrode17for die bonding is provided. In the order of descending distance from the drain electrode16, the back side electrode17is composed of titanium with a thickness of about 100 nm, nickel with a thickness of about 300 nm, and silver with a thickness of about 700 nm, for example.

In the present disclosure, this unit cell has the following construction, whereby the unit cell possesses the function of a field effect transistor and the function of a diode.

Next, with reference toFIG. 28, the operations of the unit cell111in the forward direction and in the reverse direction will be described.FIG. 28(a)is a cross-sectional view of the unit cell111;FIG. 28(b)is a diagram showing a distribution of conduction band energy across A-A′ in (a) in a reverse operation; andFIG. 28(c)is a diagram showing a distribution of conduction band energy across A-A′ in (a) in a forward operation. InFIGS. 28(b) and (c), the region to the left of the left dotted line represents a conduction band energy distribution of a portion of the second silicon carbide semiconductor layer11that is located over the source region8; the region sandwiched between the right and left dotted lines represents a conduction band energy distribution of the channel; and region to the right of the right dotted line represents a conduction band energy distribution of a portion of the second silicon carbide semiconductor layer11that is located over the JFET region. The channel is the portion of the second silicon carbide semiconductor layer11that is located over the body region. the JFET region is the region of the first silicon carbide semiconductor layer6that is located between two adjacent body regions.

With reference toFIG. 28(b), an operation of the unit cell111in the reverse direction will be described.FIG. 28(b)assumes Vgs=0. When Vds=0, the conduction band energy distribution across A-A′ is represented by the lowermost curve in the graph shown inFIG. 28(b). At this time, the second silicon carbide semiconductor layer11has a potential of Vf0 with respect to the source potential. When Vds=0, the portion of the second silicon carbide semiconductor layer11that is located over the JFET region has a potential which is Vf0 lower than the potential of the channel, and thus electrons cannot flow into the channel from the portion of the second silicon carbide semiconductor layer11that is located over the JFET region. However, when Vds is made negative, as is indicated by an arrow inFIG. 28(b), the potential of the portion of the second silicon carbide semiconductor layer11that is located over the JFET region will become greater than the potential of the portion of the second silicon carbide semiconductor layer11that is located over the source region8. Once Vds<−Vf0, the potential of the portion of the second silicon carbide semiconductor layer11that is located over the JFET region is higher than the channel potential, so that electrons will flow from the portion of the second silicon carbide semiconductor layer11that is located over the JFET region, via the channel, into the portion of the second silicon carbide semiconductor layer11that is located over the source region8. That is, a reverse current will flow in the unit cell111. This operation is a diode operation, and Vf0 is an onset voltage of the channel diode.

Next, with reference toFIG. 28(c), a forward operation of the unit cell111will be described. InFIG. 28(c), the drain has a positive potential with respect to the source. When Vgs=0, the conduction band energy distribution across A-A′ is represented by the uppermost curve in the graph shown inFIG. 28(c). When Vgs=0, the channel has a higher energy than does the portion of the second silicon carbide semiconductor layer11that is located over the source region8, thus serving as a barrier; therefore, electrons will not flow into the channel from the portion of the second silicon carbide semiconductor layer11that is located over the source region8. When Vgs is increased, as indicated by an arrow inFIG. 28(c), the channel energy will decrease. Once the energy of the channel becomes lower than that of the portion of the second silicon carbide semiconductor layer11that is located over the source region8, electrons will flow from the portion of the second silicon carbide semiconductor layer11that is located over the source region8, via the channel, into the portion of the second silicon carbide semiconductor layer11that is located over the JFET region. That is, a forward current will flow in the unit cell111.

FIG. 29is a schematic diagram showing a potential distribution of the unit cell along the depth direction, according to the present disclosure. InFIG. 29, (a) is a cross-sectional view of the unit cell, and (b) is a potential distribution chart across C-C′ in (a).

Shown aboveFIG. 29(b)is a correspondence between the horizontal axis of the potential distribution chart and various regions of the unit cell.

The horizontal axis represents depth relative to the interface between the gate insulating film12and the gate electrode13. The vertical axis represents potential (−Φ) relative to the source potential.

This potential distribution can be calculated from Poisson's equation.

The curve61shows a potential distribution when Vgs=0. Since Vgs=0, the potential of the interface between the gate insulating film12and the gate electrode13is 0.

Suppose that the gate insulating film12has a film thickness t, and that the second silicon carbide semiconductor layer11, assuming a uniform impurity concentration thereof, contains a first conductivity type impurity at a concentration Nd, with a film thickness d. The body region7has an impurity concentration Nb. It is assumed that any surface of the body region7that is in contact with the second silicon carbide semiconductor layer11is depleted, so that a depletion layer700with a thickness y is formed. Similarly, on the second silicon carbide semiconductor layer11, a depletion layer extending from its plane of junction with the body region and a depletion layer extending from its interface with the gate insulating film are formed. It is assumed that the film thickness of the second silicon carbide semiconductor layer11is set so that these depletion layers overlap each other. In other words, the entire second silicon carbide semiconductor layer11is depleted. If the second silicon carbide semiconductor layer11is thus depleted when Vgs=0, then normally-OFF. In order to deplete the second silicon carbide semiconductor layer11, it is preferable to increase the impurity concentration Nb of the body region7and decrease the film thickness d of the second silicon carbide semiconductor layer11.

Note that the source region and the body region constitute a PN junction, and the potential of the body region as viewed from the source region is a built-in potential Φbi. When Vgs=0, the potential of the interface between the gate electrode13and the gate insulating film12is equal to the source potential; therefore, the potential of the body region7as viewed from the interface between the gate electrode13and the gate insulating film12is the built-in potential Φbi, too.

The potential Pch of the interface between the gate insulating film12and the second silicon carbide semiconductor layer11is expressed by eq. (2). Herein,i is the dielectric constant of the gate insulating film12, and q is the elementary charge.

[math.⁢1]Pch=φ⁢⁢bi-q2⁢ɛ⁢⁢i×(Nb×y⁡(y+2⁢d)-Nd×d2)(2)
Pch, when Vgs=0, corresponds to the onset voltage Vf0 of the diode. It can be seen from eq. (2) that |Vf0| can be made small by increasing the impurity concentration Nb of the body region.

FIG. 30illustrates the threshold voltage Vth of the transistor and the onset voltage |Vf0| of the channel diode when the impurity concentration in the body region7that is in contact with the second silicon carbide semiconductor layer11is varied. InFIG. 30, the impurity concentration in the body region7is varied between 2×1018cm−3, 5×1018cm−3, 1×1019cm−3, and 2×1019cm−3. When the impurity concentration in the body region7changes, the threshold voltage Vth also changes; herein, the impurity concentration in the second silicon carbide semiconductor layer11is appropriately altered so as to give a threshold voltage Vth of about 3 V.FIG. 30shows a tendency where the onset voltage |Vf0|decreases as the dopant concentration in the body region7increases, given a constant threshold voltage Vth. As can be seen fromFIG. 30, by increasing the impurity concentration in the body region7that is in contact with the second silicon carbide semiconductor layer11, the onset voltage |Vf0| of the channel diode can be selectively reduced, while maintaining the threshold voltage Vth of the transistor.

The above study has led to the finding that, in order to reduce the absolute value |Vf0| of the onset voltage of the channel diode, it is desirable that the impurity concentration in the body region is high. For example, the onset voltage |Vf0| of the channel diode can be reduced by ensuring that the impurity concentration in the body region is 1×1018cm−3or more. In the case of SiC, the body diode will have an onset voltage of about 2.7 V. The impurity concentration in the body region may be 2×1018cm−3or more.

FIG. 31shows a relationship between Vth and |Vf0| where the thickness d of the second silicon carbide semiconductor layer11and the concentration of the impurity concentration Nd are varied when Nb=1×1019cm−3. InFIG. 31, the horizontal axis represents the threshold voltage Vth of the forward current, and the vertical axis represents the absolute value (|Vf0|) of the onset voltage Vf0 of the reverse current. In the simulation that was conducted to result in this figure, the concentration in the p type body region (well region) was fixed at 1×1019cm−3, and the thickness of the gate insulating film at 70 nm. The thickness range of the second silicon carbide semiconductor layer11is not less than 20 nm and not more than 70 nm, and the range of impurity concentration in the second silicon carbide semiconductor layer11is not less than 1×1017cm−3and not more than 4×1018cm−3.

It can be seen fromFIG. 31that, by reducing the thickness of the channel epitaxial layer and increasing the impurity concentration in the channel epitaxial layer, for example, Vth can be made large while keeping a constant |Vf0|. Therefore, by setting a moderate impurity concentration and thickness for the channel epitaxial layer, it is possible to control Vth and |Vf0|each independently.

For example, a method of setting the thickness and impurity concentration in the channel epitaxial layer to ensure that Vth=5 V and | Vf0|=1 V will be described with reference to this figure.

First, a thickness of the channel epitaxial layer that corresponds to a correlation line which passes through an intersection between Vth=5 V and |Vf0|=1 V is found. This reads about 40 nm inFIG. 31. Therefore, the thickness of the channel epitaxial layer is set to 40 nm. Next, at the aforementioned thickness of the channel epitaxial layer, an impurity concentration that makes Vth=5 V is to be set. In this case, a midpoint between the concentrations of two points where data exists, i.e., 7×1017cm−3and 1×1018cm−3, may be adopted, thus resulting in about 8.5×1017cm−3.

It can be seen fromFIG. 31that, when the thickness d of the second silicon carbide semiconductor layer11is not less than 20 nm and not more than 70 nm and the impurity concentration Nd is not less than 1×1017cm−3and not more than 4×1018cm−3, it can be ensured that the threshold voltage Vth>0 and that the onset voltage |Vf0| of the channel diode is smaller than the onset voltage of the body diode (which is about 2.7 V for SiC).

The film thickness t of the gate oxide film may be 20 nm or more, and 100 nm or less. When the film thickness t of the gate oxide film is 100 nm or less, a quality oxide film can be formed through thermal oxidation, without requiring a long time.

Although the above description assumes for simplicity that the second silicon carbide semiconductor layer11is a single layer with a uniform impurity concentration Nd, the impurity concentration may have a distribution so long as its mean impurity concentration is Nd.

Moreover, it is not necessary that the body region has a uniform impurity concentration distribution, either; at least the region in which a depletion layer extends from its interface with the second silicon carbide semiconductor layer11may satisfy the aforementioned concentrations. For example, it suffices if a region of at least 100 nm or more from the interface with the second silicon carbide semiconductor layer11satisfies the aforementioned range of impurity concentration.

(Method of Producing the Semiconductor Device)

Next, with reference toFIG. 2toFIG. 4, a method of producing the semiconductor device of the present embodiment will be described.FIG. 2toFIG. 4are cross-sectional views showing a method of producing the semiconductor device of the present embodiment.

First, as shown inFIG. 2(a), an n type semiconductor substrate5is provided. As the semiconductor substrate5, an off-cut substrate which is off from the 4H—SiC(0001) plane by 4° in the [11-20] direction is used, for example.

Next, as shown inFIG. 2(b), an n type first silicon carbide semiconductor layer6is epitaxially grown on the semiconductor substrate5. The first silicon carbide semiconductor layer6is made of 4H—SiC, for example. The n type impurity concentration in the first silicon carbide semiconductor layer6is made lower than the n type impurity concentration in the semiconductor substrate5.

Next, as shown inFIG. 2(c), on the first silicon carbide semiconductor layer6, a mask (not shown) of e.g. SiO2is formed, and Al ions or B ions are implanted therein to form body regions7. Although not shown, a field limited ring (FLR), an edge termination base region18of the sense region, an edge termination base region19of the main region, and an element isolation region110are simultaneously formed through this ion implantation, in an edge termination region of the semiconductor device1. Therefore, the body regions7, the edge termination base region18of the sense region, the edge termination base region19of the main region, and the element isolation region110are formed with the same p-type dopant concentration and the same depth. However, this is not a limitation; these regions may be individually formed. In the case where these regions are individually formed, their p-type dopant concentrations and depths may be set individually.

Next, as shown inFIG. 2(d), nitrogen ions are implanted into each body region7by using a mask (not shown) to form a source region8, and Al ions are implanted into each body region7by using another mask (not shown) to form a contact region9. After the ion implantation, the masks are removed and an activation annealing is conducted. The activation annealing is performed in an inert ambient at a temperature of about 1700° C. for about 30 minutes, for example.

Next, as shown inFIG. 3(a), on the entire surface of the first silicon carbide semiconductor layer6including the body regions7, the source regions8, and the contact regions9, a second silicon carbide semiconductor layer11is epitaxially grown.

Next, as shown inFIG. 3(b), partial regions of the second silicon carbide semiconductor layer11are removed by dry etching so that a portion of each source region8and the surface of each contact region9are exposed, and thereafter, a gate insulating film12is formed on the surface of the second silicon carbide semiconductor layer11by thermal oxidation.

Thereafter, as shown inFIG. 3(c), a polycrystalline silicon film113which is doped with about 7×1020cm−3of phosphorus is deposited on the surface of the gate insulating film12. The polycrystalline silicon film113has a thickness of about 500 nm, for example.

Next, as shown inFIG. 3(d), by using a mask (not shown), partial regions of the polycrystalline silicon film113are removed by dry etching, thereby forming gate electrodes13.

Then, as shown inFIG. 3(e), an interlevel dielectric film14of SiO2is deposited by a chemical vapor deposition (CVD) technique, so as to cover the surface of the gate electrodes13and the surface of the first silicon carbide semiconductor layer6. The interlevel dielectric film14has a thickness of 1.5 μm, for example.

Next, as shown inFIG. 4(a), through dry etching by using a mask (not shown), the interlevel dielectric film14on the surface of each contact region9and a portion of the surface of each source region8is removed, thereby forming a via hole114.

Thereafter, as shown inFIG. 4(b), a nickel film with a thickness of e.g. about 50 nm is formed on the interlevel dielectric film14, and thereafter an etching is conducted to remove the nickel film except in the interior of each via hole114and a part of its surrounding. After the etching, in an inert ambient, a heat treatment is conducted at 950° C. for 5 minutes, for example, thereby allowing the nickel to react with the silicon carbide surface. Thus, source electrodes10of nickel silicide are formed. Nickel is also deposited on the entire back side5bof the semiconductor substrate5, and subjected to a similar heat treatment, thereby forming a drain electrode16.

Then, as shown inFIG. 4(c), aluminum to become the upper interconnect15is deposited to a thickness of about 4 μm, over the interlevel dielectric film14and the via holes114. By etching the upper interconnect15into a desired pattern, a main region source pad2and a sense region source pad3as shown inFIG. 1(a)are obtained. Although not shown, a gate line and a gate pad to be in contact with the gate electrodes are formed, so as to be electrically insulated from the main region source pad2and the sense region source pad3. Furthermore, as a back side electrode17for die bonding purposes, Ti/Ni/Ag are deposited in this order on the drain electrode16. In this manner, the semiconductor device1shown inFIG. 1is obtained.

(Threshold Voltage and Onset Voltage Assessment of the Semiconductor Device)

A semiconductor device1according to the present embodiment was prototyped, and its electrical characteristics were assessed. In the prototyped semiconductor device1, the body region7had an n type impurity concentration of 2×1018cm−3, and the gate insulating film12had a film thickness of 70 nm. The second silicon carbide semiconductor layer11was structured so that an undoped layer with a film thickness of 75 nm was layered on an n type impurity layer having an n type impurity concentration of 1.1×1018cm−3. In the prototyped semiconductor device1, a ratio of the number of unit cells of the main region to that of the sense region was 34. A threshold voltage Vth in the forward direction and an onset voltage Vf in the reverse direction of the prototyped semiconductor device1were assessed by using a prober and a semiconductor parameter analyzer.

First, in order to assess the threshold voltage of the prototyped semiconductor device1in the forward direction, Vds was set to 0.1 V, and Vgs was swept from 0 to 10 V, while the source currents (Ism, Iss) in the main region and the sense region were measured individually and simultaneously.FIG. 5is a graph showing Iss-Vgs and Ism-Vgs curves of the prototyped semiconductor device1in the forward direction. InFIG. 5, the left vertical axis represents the source current Ism in the main region, whereas the right vertical axis represents the source current Iss in the sense region. InFIG. 5, data of black circles represents the source current in the main region, whereas data of white squares represents the source current in the sense region. The threshold voltage in the forward direction was determined from a Vgs of the time when a reference current was obtained. As the value of the reference current, different values were used between the main region and the sense region, in accordance with the cell number ratio. The reference current for the main region was 1 mA, and a value obtained by dividing this with the cell number ratio of 34, i.e., 0.029 mA, was adopted as the reference current for the sense region.

From measurements at room temperature, the threshold voltage of the main region was 4.05 V, and the threshold voltage of the sense region was 3.99 V, these values being substantially equal. Although threshold voltage has negative temperature characteristics, if there is a threshold voltage of 3 V or more at room temperature, a threshold voltage of about 1 V can be maintained even at 150° C. It was found from this result that the prototyped semiconductor device1is capable of normally-OFF operation in a range from room temperature to 150° C., and provides some noise margin.

Next, in order to assess the onset voltage of the prototyped semiconductor device1in the reverse direction, Vgs was fixed at 0 V, and Vds was swept from 0 to −1 V, while the source currents in the main region and the sense region (Ism, Iss) were measured individually and simultaneously.FIG. 6is a graph showing Iss-Vds and Ism-Vds curves of the prototyped semiconductor device1in the reverse direction. InFIG. 6, the left vertical axis represents the source current −Ism in the main region, whereas the right vertical axis represents the source current −Iss in the sense region. InFIG. 6, data of black circles represents the source current in the main region, whereas data of white squares represents the source current in the sense region. The onset voltage in the reverse direction was determined from a Vds of the time when a reference current was obtained. The value of the reference current was −1 mA for the main region, and a value obtained by dividing this with the cell number ratio of 34, i.e., −0.029 mA, was adopted as the reference current for the sense region.

From measurements at room temperature, the onset voltage of the main region was −0.74 V, and the onset voltage of the sense region was −0.7 V, these values being substantially equal. The onset voltage of the body diode which is constituted by the body region7and the first silicon carbide semiconductor layer6is the value of built-in potential of a PN junction of silicon carbide, i.e., about 2.5 V; thus, it was found that the onset voltage of the prototyped semiconductor device1in the reverse direction attains a lower value than the onset voltage of the body diode. This result indicates that the reverse current is a result of a current flowing through the channel diode, i.e., from the source electrode10, via the second silicon carbide semiconductor layer11, and into the drain electrode16, rather than through the body diode.

(Forward Current Assessment of the Semiconductor Device)

Next, the prototyped semiconductor device1was mounted on a substrate72having an electrode pattern formed thereon, and was subjected to assessment under a large current.FIG. 7is a diagram showing the circuit construction of a measurement system70for assessing a forward current which simultaneously flows in the main region20and the sense region21of the semiconductor device1of the present embodiment. The substrate72having the semiconductor device1mounted thereon includes a drain terminal74, a gate terminal76, a main region source terminal78, a sense region source terminal79, and a Kelvin terminal80. Vcc power22is provided in series connection between the drain terminal74and the main region source terminal78. On the substrate, the main region source pad2of the main region20is connected to the main region source terminal78and the Kelvin terminal80.

The current Ism flowing in the main region20(hereinafter abbreviated as the main region current Ism) flows from the main region source pad2to the main region source terminal78, but not from the main region source pad2to the Kelvin terminal80. The sense region source pad3of the sense region21is connected to the sense region source terminal79. Connected to the Kelvin terminal80. The gate pad4of the main region20and the sense region21is connected to the gate terminal76.

The gate terminal76is connected to a gate driver23via a gate resistor26. The potential of the Kelvin terminal80is used as the reference potential of the gate driver23. Since only a small current from the sense region21flows to the Kelvin terminal80, the Kelvin terminal80is at a substantially equal potential to the potential of the source electrode of the main region20. Gate driver power24is connected to the gate driver23. In accordance with the output from the pulse signal generator25, a gate-source voltage which is determined by the voltage of gate driver power24is applied to both the main region20and the sense region21.

A low current probe28is provided between the sense region source pad3of the sense region21and the Kelvin terminal, and measures the current Iss flowing in the sense region21(hereinafter abbreviated as the sense region current Iss). The sense region current Iss passes through the Kelvin terminal80, and thereafter meets with the main region current Ism to together flow to the main region source terminal78. A high current probe27is provided between the main region source pad2and the main region source terminal78, and measures a sum of the sense region current Iss and the main region current Ism. A voltmeter29monitors the voltage between the drain terminal74and the source terminal78.

FIG. 8is a graph showing a result of assessing the forward current of the semiconductor device1at an ambient temperature Ta of 25° C. InFIG. 8, the horizontal axis represents the main region current Ism, the left vertical axis represents the sense region current Iss, and the right vertical axis represents a ratio Ism/Iss of the main region current Ism to the sense region current Iss. InFIG. 8, data indicated by black circles represents the sense region current Iss, whereas data indicated by white squares represents a ratio Ism/Iss of the main region current Ism to the sense region current Iss. It can be seen fromFIG. 8that the sense region current Iss is in proportion to the main region current Ism. The ratio of the main region current Ism to the sense region current Iss is about 32, which is substantially equal to the cell number ratio of 34.

FIG. 9is a graph showing a result of assessing the forward current of the semiconductor device1at ambient temperatures Ta of −40° C., 25° C., 85° C., and 150° C. InFIG. 9, the horizontal axis represents the main region current Ism, and the vertical axis represents the ratio of the main region current Ism to the sense region current Iss. As can be seen fromFIG. 9, in a range of ambient temperatures Ta from −40° C. to 150° C., the ratio of the main region current Ism to the sense region current Iss was substantially constant, regardless of the magnitude of the sense region current Iss. The ratio of the main region current Ism to the sense region current Iss had a mean value of 32.2, which is substantially equal to the cell number ratio. The ratio of the main region current Ism to the sense region current Iss had a minimum value of 30.8 and a maximum value of 33.5, with a mean absolute deviation as small as 1.7%. A mean absolute deviation is defined as in eq. (3) below.

(Reverse Current Assessment of the Semiconductor Device)

Next, the prototyped semiconductor device1was subjected to a reverse current assessment.FIG. 10is a diagram showing the circuit construction of a measurement system90for assessing a reverse current which simultaneously flows in the main region20and the sense region21of the semiconductor device1of the present embodiment.

The semiconductor device1and a switching FET30are in series connection. Note that the semiconductor device1and the switching FET30are connected in reverse directions. In other words, the main region source terminal78of the substrate72having the semiconductor device1mounted thereon is connected to the source electrode of the switching FET30. The positive terminal of Vcc power22is connected to the drain electrode of the switching FET30, and the negative terminal of Vcc power22is connected to the drain terminal74of the substrate72. Since the gate terminal76of the substrate72is connected to the Kelvin terminal80, Vgs is fixed at 0 V. The gate electrode of the switching FET30is connected to the gate driver23via the gate resistor26. Gate driver power24is connected to the gate driver23, and each reference potential terminal is connected to the Kelvin terminal80.

With an output from the pulse signal generator25, the gate driver23outputs a gate voltage which is determined by the voltage of gate driver power to the switching FET30. It is only at moments when the switching FET30conducts that a reverse voltage resulting from subtracting the potential drop of the switching FET30from the output voltage of Vcc power22is applied between the drain terminal74and the main region source terminal78of the substrate72, whereby a reverse current flows.

The current flowing through the switching FET30passes through the main region source terminal78, and thereafter at the main region source pad2, splits into a main region current −Ism in the reverse direction and a sense region current −Iss in the reverse direction. From the main region source pad2, a sense region current −Iss in the reverse direction passes through the Kelvin terminal80, and flows in the sense region21. The low current probe28is disposed between the sense region source pad3of the sense region21and the Kelvin terminal80, and measures the sense region current −Iss in the reverse direction. The high current probe27is disposed between the main region source pad2and the main region source terminal78, and measures a sum of the sense region current −Iss in the reverse direction and the main region current −Ism in the reverse direction. The voltmeter29monitors the voltage between the drain terminal74and the main region source terminal78.

With the measurement system90shown inFIG. 10, by setting Vgs of the semiconductor device1at 0 V and varying the output voltage of Vcc power22, the sense region current −Iss in the reverse direction was measured in a range where the main region current −Ism in the reverse direction was 0 to 40 A.

FIG. 11is a graph showing a result of assessing the reverse current of the semiconductor device1at an ambient temperature Ta of 25° C. InFIG. 11, the horizontal axis represents the main region current −Ism in the reverse direction, the left vertical axis represents the sense region current −Iss in the reverse direction, and the right vertical axis represents a ratio Ism/Iss of the main region current −Ism in the reverse direction to the sense region current −Iss in the reverse direction. InFIG. 11, data indicated by black circles represents the sense region current −Iss in the reverse direction, whereas data indicated by black squares represents the ratio Ism/Iss of the main region current −Ism in the reverse direction to the sense region current −Iss in the reverse direction. It can be seen fromFIG. 11that the sense region current −Iss is in proportion to the main region current −Ism, also in the reverse direction. The ratio of the main region current −Ism in the reverse direction to the sense region current −Iss in the reverse direction was about 32, which is substantially equal to the cell number ratio of 34, as was the case in the forward direction.

FIG. 12is a graph showing a result of assessing the reverse current of the semiconductor device1at ambient temperatures Ta of −40, 25° C., 85° C., and 150° C. InFIG. 12, the horizontal axis represents the main region current −Ism in the reverse direction, and the vertical axis represents the ratio Ism/Iss of the main region current −Ism in the reverse direction to the sense region current −Iss in the reverse direction. As can be seen fromFIG. 12, in a range of ambient temperatures Ta from −40° C. to 150° C., the ratio of the main region current −Ism in the reverse direction to the sense region current −Iss in the reverse direction was substantially constant, regardless of the magnitude of the sense region current −Iss in the reverse direction. The ratio of the main region current −Ism in the reverse direction to the sense region current −Iss in the reverse direction had a mean value 32.4, which is substantially equal to the ratio of the main region current Ism to the sense region current Iss in the forward direction. The ratio of the main region current −Ism in the reverse direction to the sense region current −Iss in the reverse direction had a minimum value of 31.1, and a maximum value of 33.8, with a mean absolute deviation as small as 2.3%.

As described above, the semiconductor device which is disclosed in the present specification functions as a diode which has a high threshold voltage Vth in the forward direction, and an onset voltage Vf of less than 1 V in the reverse direction. In the semiconductor device which is disclosed in the present specification, the ratio between the current flowing in the main region and the current flowing in the sense region is constant in a broad current range and a broad temperature range, and in both of the forward direction and the reverse direction, satisfying the relationship of eq. (1). Therefore, with the semiconductor device which is disclosed in the present specification, by measuring a small current flowing in the sense region, a large current flowing in the main region can be detected with a high accuracy.

Note that, without being limited to the aforementioned values, the ratio of the number of cells in the main region to that in the sense region may be greater. However, when the sense region current Iss is 100 mA or less, an advantage is obtained in that inexpensive generic operational amplifiers can be used to handle the sense region current Iss, enabling current detection with a simple current-voltage conversion circuit by using a generic operational amplifier.

FIG. 13is a diagram showing the circuit construction of a measurement system200for measuring a forward current and a reverse current of the semiconductor device of the present embodiment, incorporating a current-voltage conversion circuit which includes an operational amplifier. The measurement system200includes an operational amplifier35having a non-inverting input terminal35p, an inverting input terminal35q, and an output terminal35r.

The drain electrode in the main region33and the sense region34of the semiconductor device1is connected to one end of a load37via a drain terminal204. The other end of the load37is connected to a Vdd power line31. The source electrode of the main region33is connected to a return line32of Vdd power, via a main region source terminal208.

Moreover, a Kelvin terminal210, which branches out from the source electrode of the main region33, is connected to the non-inverting input terminal35pof the operational amplifier35. The source electrode of the sense region34is connected to the inverting input terminal35qof the operational amplifier35via a sense region source terminal209. The current flowing in the load37is split into a current Ism flowing in the main region33and a current Iss flowing in the sense region34. Since the operational amplifier35has a very large input impedance, the current Ism flowing in the main region33and the current Iss flowing in the sense region34do not flow into the non-inverting input terminal35pand the inverting input terminal35qof the operational amplifier35. Since the current Ism flowing in the main region33does not flow into the Kelvin terminal210, the Kelvin terminal210is not affected by a potential drop associated with the current Ism flowing in the main region33. Therefore, the potential of the Kelvin terminal210, i.e., the potential of the non-inverting input terminal35pof the operational amplifier35, accurately equals the potential of the main region source pad2of the main region33. A sense resistor36is connected between the output terminal35rand the inverting input terminal of the operational amplifier35. The gate electrodes in the main region20and the sense region21are connected to a gate terminal206.

The gain of the operational amplifier35is ideally infinite, and is very large in actuality. If the potentials of the inverting input terminal35qand the non-inverting input terminal35pare different, a potential which is in proportion to that difference will appear at the output terminal35r, which results in a negative feedback that decreases the potential of the inverting input terminal35qvia the sense resistor36. This consequently equalizes the potential of the inverting input terminal35qwith the potential of the non-inverting input terminal35p. As a result, the potentials of the source electrodes of the main region33and the sense region34become equal, so that equal gate-source voltages are applied to both the main region33and the sense region34. In order to further stabilize the negative feedback, the sense resistor36preferably has a resistance value on the order of kΩ.

The output Vsense of the operational amplifier35is expressed by following equation.
Vsense=−Iss×Rsense  (4)
Herein, Iss is the current flowing in the sense region34, and Rsense is the resistance value of the sense resistor36. The right-hand side of the above equation takes a negative value when the current flowing in the sense region34is a so-called forward current that flows from the drain to the source, and takes a positive value when it is a so-called reverse current that flows from the source to the drain.

Generally speaking, operational amplifiers are classified into a single supply type, which only applies power voltage of a single polarity, and a dual supply type, which applies power voltage of both positive polarity and negative polarity. In the case of a single supply type, the output can only take either positive or negative polarity. In the case of a dual supply type, the output can take both polarities of positive and negative. Therefore, in order to measure the forward current and the reverse current, it is preferable to use an operational amplifier of a dual supply type. That is, a dual supply type is preferably used for the operational amplifier35.

An operational amplifier cannot output any voltage that exceeds the power voltage. The power voltage of many a generic operational amplifier is 12 to 15 V. When the sense resistor is on the kΩ order, the current which can be allowed to flow in the operational amplifier is on the order of 100 mA or less. In the present embodiment, the negative feedback of the operational amplifier was not stable when the sense resistor was less than 100Ω.

Note that it is not necessary to use an operational amplifier for the current-voltage conversion circuit. Instead of an operational amplifier, for example, a current sensor which utilizes the Hall effect, or a current sensor such as a Rogowski coil, can be used for the current-voltage conversion circuit.

Furthermore, with the semiconductor device which is disclosed in the present specification, if a detected reverse current value is not the desired value, it is possible to control the magnitude of the reverse current by controlling the gate voltage.

FIG. 14is a graph showing gate voltage dependence of the reverse-direction Ism-Vds curve of the main region of the semiconductor device1of the present embodiment. InFIG. 14, the horizontal axis represents the drain voltage −Vds in the negative direction, and the vertical axis represents the reverse current −Ism flowing in the main region. InFIG. 14, data indicated by white squares represents data when Vgs is 0 V, whereas data indicated by black circles represents data when Vgs is −5 V. As can be seen fromFIG. 14, in the semiconductor device1, the reverse current flowing in the main region can be reduced by making the gate voltage more negative. In the graph shown inFIG. 14, at Vgs=0 V, −Vds is 1.5 V when −Is is 15 A, thus resulting in a resistance of 0.1Ω. On the other hand, at Vgs=−5 V, −Vds is 2 V when −Is is 15 A, hence increasing the resistance to 0.13Ω. Thus, in the semiconductor device of the present specification, the reverse current also flows through the channel of the transistor, so that its IV characteristics can be altered based on gate voltage. In the technique disclosed in Patent Document 1, the reverse current flows through the body diode, so that the IV characteristics in the reverse direction cannot be altered based on gate voltage.

In the technique disclosed in Patent Document 1, in order to detect a current flowing in a free-wheel diode, it is necessary to provide a diode current detection means in addition to a transistor current detection means, thus resulting in a complicated construction.

On the other hand, in the semiconductor device which is disclosed in the present specification, the sense region is utilized to detect not only the forward current, which corresponds to a transistor current, but also the reverse current, which corresponds to a diode current. Therefore, in the semiconductor device which is disclosed in the present specification, both a current flowing through the transistor and a current flowing through the free-wheel diode can be detected with a simple construction.

Moreover, Patent Document 1 discloses detection of a reverse current flowing in the body diode of the low-side MOSFET in a conventional switching circuit. However, in the switching circuit described in Patent Document 1, it is not possible to control the reverse current based on gate voltage. Moreover, in the case of a silicon carbide semiconductor, when a current is flowed in the PN junction constituting the body diode, stacking faults will grow to deteriorate the characteristics of the body diode. Moreover, since a silicon carbide semiconductor has a wide band gap, the onset voltage Vf of the body diode will be as large as about 2.5 V.

On the other hand, in the semiconductor device which is disclosed in the present specification, the reverse current is detected by using the channel diode, rather than the body diode, so that characteristics deterioration due to growing stacking faults does not occur, and the onset voltage Vf of the diode is low. Furthermore, the semiconductor device which is disclosed in the present specification provides a unique effect of being able to control the reverse current based on gate voltage.

Second Embodiment

Structure of the Semiconductor Device

Next, a semiconductor device according to a second embodiment of the present disclosure will be described with reference to the drawings.FIG. 15(a)is a plan view generally showing the semiconductor device of the present embodiment.FIG. 15(b)is a cross-sectional view generally showing portion A-A′ inFIG. 15(a).FIG. 15(c)is a cross-sectional view generally showing a unit cell inFIG. 15(b).FIG. 15(d)is a cross-sectional view showing enlarged the boundary between the main region320and the region321inFIG. 15(b).

In the semiconductor device1of the first embodiment, the unit cell111is a planar-gate type MISFET; the semiconductor device of the present embodiment301differs in that the unit cell311is a trench-gate type MISFET. Constituent elements which are common to those of the semiconductor device1of the first embodiment will be denoted by like numerals, and the descriptions thereof will be omitted.

As shown inFIG. 15(b), in a first silicon carbide semiconductor layer6of a first conductivity type at the boundary between the sense region321and the main region320, unlike in unit cells, edge termination base regions18and19and an element isolation region110are provided. The edge termination base regions18and19and the element isolation region110are both of a second conductivity type. The edge termination base regions18and19do not include any source region of the first conductivity type because, if any source region were provided in the edge termination base regions18and19, a large current might flow in a parasitic bipolar which is composed of the source region, the edge termination base regions18and19, and the first silicon carbide semiconductor layer6, thus possibly destroying the semiconductor device301. A source electrode10is provided on the edge termination base regions18and19, so as to be electrically connected with source electrodes10of the unit cells311via the upper interconnects15. Therefore, the edge termination base regions18and19and the source regions8of the unit cells311are at the same potential. The edge termination base regions18and19constitute a PN diode with the first silicon carbide semiconductor layer6.

The element isolation region110is located between the edge termination base region18and the edge termination base region19. No source electrode10is provided on the element isolation region110, so that the potential of the element isolation region110is a floating potential. The element isolation region110prevents a current from flowing between the sense region321and the main region320. As shown inFIG. 15(d), no second silicon carbide semiconductor layer11is provided on the element isolation region110or at edge portions of the edge termination base regions18and19. This prevents a current from flowing between the main region320and the sense region321via the second silicon carbide semiconductor layer11, thus allowing a current flowing in the sense region321to be detected in a distinguishable manner over a current flowing in the main region320.

With reference toFIG. 15(c), the structure of the unit cell311will be described. A trench112extends from the surface layer of the source region8to penetrate through the source region8and the body region7. The second silicon carbide semiconductor layer11is on the side face and the bottom face of the trench112and a portion of the surface of the source region8. The second silicon carbide semiconductor layer11is an epitaxial layer which is formed by epitaxial growth so as to cover the bottom face and side face of the trench112of the first silicon carbide semiconductor layer6and the periphery of the trench112, for example. In the case where the second silicon carbide semiconductor layer11is composed of a single n type layer, the thickness of the second silicon carbide semiconductor layer11may be 75 nm or less, and the doping concentration of an n type impurity in the second silicon carbide semiconductor layer11may be 1×1018cm−3or more, for example. The second silicon carbide semiconductor layer11may also be a layer obtained by stacking an undoped layer on the surface of an n type impurity layer. In some cases, the film thickness of the second silicon carbide semiconductor layer11may become reduced during the steps of sacrificial oxidation and gate oxidation. Variation in the decrease in film thickness of the second silicon carbide semiconductor layer11during production steps causes variation in the electrical characteristics of the semiconductor device301, e.g., threshold voltage in the forward direction and onset voltage in the reverse direction. By stacking an undoped layer on the surface of the n type impurity layer, variation in the electrical characteristics of the semiconductor device301can be reduced.

A gate insulating film12is provided on the second silicon carbide semiconductor layer11. The gate insulating film12has a thickness of about 70 nm.

On the gate insulating film12, a gate electrode13is provided so as to bury the trench112. For example, the gate electrode13is an n type poly-Si doped with about 1×1021cm−3of phosphorus, and the gate electrode13has a thickness of about 500 nm.

In the case of a trench-gate type MISFET, a channel is formed not in a parallel direction to the principal face of the semiconductor substrate, but in the thickness direction of the semiconductor substrate; therefore, the area density of the channel can be increased relative to a planar-gate type MISFET. Therefore, given a semiconductor device of the same size, a trench-gate type MISFET can increase the current to flow, as compared to a planar-gate type MISFET. Current measurement becomes more difficult as the current increases; therefore, when the unit cell in the semiconductor device which is disclosed in the present specification is a trench-gate type MISFET, the effect associated with current measurement becomes more pronounced, due to a current flowing in the sense region, whose number of cells is made smaller than that of the main region.

(Method of Producing the Semiconductor Device)

Next, with reference toFIG. 16toFIG. 18, a method of producing the semiconductor device of the present embodiment will be described.FIG. 16toFIG. 18are cross-sectional views showing a method of producing the semiconductor device of the present embodiment.

The step of providing the semiconductor substrate5shown inFIG. 16(a)and the step of epitaxially growing the first silicon carbide semiconductor layer6shown inFIG. 16(b)are identical to the steps shown inFIG. 2(a)andFIG. 2(b)of the first embodiment, and the descriptions thereof are omitted.

Next, as shown inFIG. 16(c), on the surface of the first silicon carbide semiconductor layer6, for example, a body region7having a thickness of about 0.5 μm to about 1 μm is epitaxially grown. Instead of epitaxial growth, aluminum ions or boron ions may be implanted into the first silicon carbide semiconductor layer6to form the body region7.

Then, as shown inFIG. 16(d), on the surface of the body region7, through nitrogen ion implantation or epitaxial growth, a source region8containing a high concentration of an n type impurity is formed. In addition, Al ions are implanted into the source region8by using a mask (not shown), thereby forming p type contact regions9that reach the body region7. Thereafter, an activation annealing is conducted. The activation annealing is performed in an inert ambient at about 1700 to about 1800° C. for about 30 minutes, for example.

Next, as shown inFIG. 16(e), partial regions of the source region8and the body region7are removed by dry etching by using a mask (not shown), thereby forming trenches112in desired regions. Each trench112is a recess that penetrates through the source region8and the body region7to reach the first silicon carbide semiconductor layer6.

Next, as shown inFIG. 17(a), on the entire surface of the first silicon carbide semiconductor layer6including the bottom face and the side face of each trench112, a second silicon carbide semiconductor layer11is epitaxially grown.

Next, as shown inFIG. 17(b), partial regions of the second silicon carbide semiconductor layer11are removed by dry etching, so as to expose a portion of each source region8and the surface of the contact region9. Thereafter, through thermal oxidation, a gate insulating film12is formed on the surface of the second silicon carbide semiconductor layer11.

Next, as shown inFIG. 17(c), on the surface of the gate insulating film12, a polycrystalline silicon film having a thickness of about 500 nm and being doped with about 7×1020cm−3of phosphorus is deposited, for example. Next, the polycrystalline silicon film is worked into a desired pattern through dry etching, thereby forming a gate electrode13within each trench112and in a partial region around the trench112.

The step of depositing the interlevel dielectric film14shown inFIG. 17(d), the step of forming the source electrode10and the drain electrode16shown inFIG. 18(a), and the step of forming the upper interconnect15and the back side electrode17shown inFIG. 18(b)are identical to the steps shown inFIG. 3(e),FIG. 4(a),FIG. 4(b), andFIG. 4(c)of the first embodiment, and the descriptions thereof are omitted.

Third Embodiment

Next, an inverter according to a third embodiment of the present disclosure will be described with reference to the drawings.FIG. 19is a block diagram showing the construction of a load driving system400including an inverter402according to the present embodiment.

The load driving system400includes an AC power source40, a rectification circuit404, an inverter402, and a load45.

The rectification circuit404includes a diode bridge circuit406, which is composed of four rectifier diodes42, and a choke coil41. An AC output voltage from the AC power source40is subjected to DC conversion through the rectifier diode42. The choke coil41is inserted between the AC power source40and the diode bridge circuit406in order to improve the power factor.

The inverter402includes a three-phase bridge circuit408, a regenerative power consuming circuit410, a current-voltage converter48, a gate voltage controller49, a smoothing capacitor43, and a voltage detector420which detects the voltage across the smoothing capacitor43.

The three-phase bridge circuit408is composed of upper arms44a,44c, and44eand lower arms44b,44d, and44f, which are semiconductor devices according to the first embodiment or the second embodiment. The upper arm44aand the lower arm44bare in series connection with each other to compose a leg440. Similarly, the upper arm44cand the lower arm44dare in series connection with each other to compose a leg442. The upper arm44eand the lower arm44fare in series connection with each other to compose a leg444. The midpoint of each leg440,442,444is connected to the load45.

A DC voltage which has been smoothed by the smoothing capacitor43is applied to both ends of each leg440,442,444of the three-phase bridge circuit408to be converted into a three-phase current voltage by the three-phase bridge circuit408. The three-phase current voltage which is output from the three-phase bridge circuit408is applied to the load45.

The gate terminals of the semiconductor devices composing the upper arms44a,44c, and44eand the lower arms44b,44d, and44fof the respective legs440,442, and444are connected to the gate voltage controller49, which provides gate voltage control.

The gate voltage controller49individually controls the gate voltages of the upper arms44a,44c, and44eand the lower arms44b,44d, and44fof the respective legs440,442, and444so that a sine-wave voltage of a desired frequency is supplied to the load45. Moreover, the source terminal of the sense region21of each semiconductor device is connected to the current-voltage converter48.

The current-voltage converter48is connected to the second source pad of each semiconductor device, and outputs voltage of a value that corresponds to the value of the current flowing between the drain pad and the second source pad.

The regenerative power consuming circuit410includes a resistor46for consuming, in the form of heat, a regenerative current which flows from the load45to the inverter402, and a switching element47for controlling the regenerative current to be flowed to the resistor. The voltage detector420is in parallel connection with the smoothing capacitor43, and is provided for detecting the regenerative current.

Based on the voltage which is output from the current-voltage converter48and the voltage which has been detected by the voltage detector420, the gate voltage controller49controls the voltages to be applied to the gate pads of the semiconductor devices.

Hereinafter, the respective constituent elements will be described in detail. The current-voltage converter48includes current-voltage converters48L and48U.FIG. 20andFIG. 21are diagrams showing the details of the current-voltage converters48L and48U.FIG. 20is a block diagram of the current-voltage converter48L, which is connected to the lower arms44b,44d, and44f. The current-voltage converter48L is composed of three operational amplifiers35b,35d, and35fthat are connected to the lower arms44b,44d, and44f, and their respective feedback resistors36b,36d, and36f. A positive power voltage Vcc and a negative power voltage −Vcc are applied to each of the operational amplifiers35b,35d, and35f. Their construction is identical to that ofFIG. 13; the positive power voltage +Vcc which is supplied to the three operational amplifiers35b,35d, and35fis an identical voltage, which may be supplied from the same positive supply.

The negative power voltage −Vcc which is supplied to the three operational amplifiers35b,35d, and35fis an identical voltage, which may be supplied from the same negative supply. For example, the circuit which is connected to the lower arm44bwill be described. A terminal481bwhich is provided at the inverting input of the operational amplifier35bis connected to the source pad of the sense region of the lower-arm semiconductor device. A terminal482bwhich is provided at the non-inverting input is connected to the Kelvin terminal which branches out from the source pad of the main region of the semiconductor device of the lower arm44b. A terminal483bwhich is provided at the output of the operational amplifier35bis connected to the gate voltage controller49. A sense resistor36is connected to the inverting input and the output of the operational amplifier35b, so that a voltage which is obtained as a result of the feedback resistor36bacting on the current flowing into481bis output from the output terminal. The source pads of the main regions of the semiconductor devices of the lower arms are all connected to one electrode of the smoothing capacitor, and therefore at the same potential; thus, the reference potential for the power voltage to be fed to each operational amplifier may be the negative-side potential of the smoothing capacitor.

FIG. 21is a block diagram of the current-voltage converter48U for upper arms. It differs from the current-voltage converter48L for lower arms in that the source potentials of the three semiconductor devices of the upper arms vary depending on the operating state, and may each take a different potential. Therefore, the power voltages to be supplied to the operational amplifiers35a,35c, and35e, which are referenced against the source potentials of the semiconductor devices of the respective upper arms which are connected thereto, are different power voltages +Vcc1, −Vcc1, +Vcc2, −Vcc2, +Vcc3, and −Vcc3. Other aspects are the same as in the current-voltage converter48L for lower arms.

FIG. 22is a functional block diagram showing the details of the gate voltage controller49. The gate voltage controller49includes a PWM signal generation circuit51, an overcurrent detection circuit52, a regenerative current determination circuit53, a transistor shutoff signal generation circuit54, a gate negative bias signal generation circuit55, a regenerative resistor switching control signal generation circuit56, and a gate signal toggling circuit57.

In a usual operating state, a signal which is generated by the PWM signal generation circuit51is output from the gate voltage controller49as a gate signal for each transistor of the legs440,442, and444. As a result, a three-phase current voltage is applied to the load45(FIG. 19).

When the load45becomes short-circuited, or gate voltage control fails so that the upper arms44a,44c, and44ebecome short-circuited with the lower arms44b,44d, and44f, an overcurrent may flow in the semiconductor device(s), possibly destroying the semiconductor device(s). In order to prevent this, upon determining that an overcurrent has flowed in a semiconductor device, the gate voltage controller49stops the usual gate voltage control for that semiconductor device, and lowers the gate voltage so that the overcurrent flowing in the semiconductor device is cut off. Specifically, the overcurrent detection circuit52receives the signal which is output from the current-voltage converter48, and compares it against a predetermined forward reference value. The signal which is output from the current-voltage converter48has a voltage value which is in proportion to the value of the current flowing between the drain pad and the second source pad. The current flowing between the drain pad and the second source pad, i.e., the current flowing in the sense region21, is in proportion to the current flowing in the main region20, which is the current flowing between the drain pad and the first source pad. Therefore, when the absolute value of the voltage which is output from the current-voltage converter48is greater than the predetermined forward reference value, it can be determined that an overcurrent is flowing to the load.

Once determining that an overcurrent is flowing to the load, the overcurrent detection circuit52outputs a signal to the transistor shutoff signal generation circuit54and the gate signal toggling circuit57. Upon receiving the signal, the gate signal toggling circuit57selects the output from the transistor shutoff signal generation circuit54, whereby the gate voltage controller49outputs a low gate voltage for shutting off the transistor, which has been generated by the transistor shutoff signal generation circuit54. As a result, the transistor of the leg in which the overcurrent has been detected is shut off, thus restraining an overcurrent from flowing to the load45.

Moreover, in the case where the load45is an inductive load, e.g., when operation of the semiconductor device is stopped after a state where a forward current was flowing, a back-induced electromotive force is generated so that a regenerative current, which is a reverse current, flows. This regenerative current flows in a path which, in this order from the load45, connects the channel diode of the upper arm44cof the leg442, the smoothing capacitor43, the channel diode of the lower arm44bof the leg440, and the load45, for example.

Once a regenerative current flows, the voltage across the smoothing capacitor43increases. If the voltage across the smoothing capacitor43exceeds the breakdown voltage of the smoothing capacitor43, the smoothing capacitor43may become destroyed. In order to prevent this, the regenerative current determination circuit53receives the detected voltage from the voltage detector420, and compares the value of the detected voltage against a predetermined reference voltage value. If the value of the detected voltage exceeds the reference voltage value, the regenerative current determination circuit53determines that the voltage across the smoothing capacitor43has exceeded the reference voltage value.

In this case, the regenerative current determination circuit53outputs a signal to the regenerative resistor switching control signal generation circuit56. Upon receiving the signal, the regenerative resistor switching control signal generation circuit56outputs a signal which causes the switching element47, provided in the regenerative power consuming circuit410, to conduct. As a result, the switching element47in the regenerative power consuming circuit410conducts, so that the regenerative current now flows through the resistor46, whereby the regenerative power is converted into heat and consumed. This prevents the voltage across the smoothing capacitor43, that is, the voltage of the primary power source, from becoming excessively high and destroying the smoothing capacitor43due to overvoltage.

Moreover, the regenerative current determination circuit53outputs a signal to the gate negative bias signal generation circuit55and the gate signal toggling circuit57. Upon receiving the signal, the gate signal toggling circuit57selects the output from the gate negative bias signal generation circuit55, whereby the gate voltage controller49outputs a negative gate voltage which has been generated by the gate negative bias signal generation circuit55. As a result, the transistors which are the semiconductor devices of the legs440,442, and444have their resistance values in the reverse direction increased, so that more regenerative current is converted into heat and consumed also at the semiconductor devices of the legs440,442, and444.

In the present embodiment, the gate voltage controller49includes both of the gate negative bias signal generation circuit55and the regenerative resistor switching control signal generation circuit56, and upon determining that the regenerative current is equal to or greater than the predetermined value, operates both of the gate negative bias signal generation circuit55and the regenerative resistor switching control signal generation circuit56. However, only one of them may be operated instead. Moreover, the gate voltage controller49does not even need to include the circuit that is not to be operated.

FIG. 23Ais a timing chart concerning a protection operation in the case where a forward overcurrent flows in a semiconductor device in the inverter of the present embodiment due to short-circuiting of the load or the like, showing gate signals and the like of a specific semiconductor device. From time0to t1, the gate is ON, and therefore the forward current that flows in the semiconductor device at issue keeps increasing during this period, whereby the output voltage value corresponding to the forward current decreases. From time t1to t2, the gate is OFF, and therefore no current flows in the semiconductor device at issue, so that the output voltage value does not change. The gate turns ON again at time t2; if an accident such as short-circuiting of the load causes a rapid increase in the current and decreases the output voltage value, until going beyond a previously-set forward reference voltage value at time t3, the output of the overcurrent detection circuit52becomes ON, so that a gate signal which will cut off the current in the semiconductor device is output. Since instantaneously turning the gate OFF will result in a back electromotive force of an inductive load, it is preferable to turn OFF the gate gradually. In this manner, the forward current of the semiconductor device is reduced to zero.

FIG. 23Bis a timing chart concerning a protection operation in the case where, due to slowing down of a motor, a regenerative current is flowing from the motor into the smoothing capacitor. At time t4, the gate signal becomes OFF, so that the current once equals zero; however, at time t5, a reverse current which is presumably a regenerative current begins to flow. The smoothing capacitor is charged with this reverse current, whereby the voltage value across its both ends increases. At time t6, the voltage across the smoothing capacitor exceeds a reference voltage value which is previously set, whereupon the output of the regenerative current determination circuit53becomes ON, thus turning the regenerative resistor switch gate signal ON at time t7. The regenerative current flows to the regenerative resistor, where it turns into heat so that the regenerative energy is consumed. As a result, the regenerative current is reduced to zero, thereby eliminating the overvoltage of the smoothing capacitor.

FIG. 23Cis a time chart showing a protection operation where regenerative energy is consumed not only in the regenerative resistor but also in the semiconductor device of the inverter. When the output of the regenerative current determination circuit53becomes ON at time t6, not only the regenerative resistor switch gate signal becomes ON, but also the gate voltage of that semiconductor device is changed from zero to negative. The negative gate voltage is −5 V, for example. As the gate voltage becomes negative, the channel diode increases in resistance. The regenerative energy is consumed by the resistances of the regenerative resistor and the channel diode. As a result, the regenerative current is reduced to zero, thereby eliminating the overvoltage of the smoothing capacitor.

As shown inFIG. 14, in the semiconductor device which is disclosed in the present specification, the resistance of the channel diode of the semiconductor device can be changed by shifting the gate voltage toward the negative side. This increases the conduction loss at the channel diode of the semiconductor device, thus allowing regenerative power to be consumed also at the channel diode. In the case of a semiconductor device in which silicon is used, the temperature of the semiconductor device will increase due to the heat when regenerative power is consumed, so that the absolute maximum rated temperature may be exceeded and operation may be disabled. In contrast, the semiconductor device which is disclosed in the present specification utilizes silicon carbide, which has excellent thermal resistance, and therefore restrains the semiconductor device from becoming unable to operate due to the heat when regenerative power is consumed.

FIG. 24is a graph showing the temperature characteristics of an IV curve of the semiconductor device which is disclosed in the present specification in the reverse direction. InFIG. 24, the horizontal axis represents the drain-source voltage Vds, and the vertical axis represents the drain current in the reverse direction. Data indicated by the broken line represents measurement results at room temperature; data indicated by the dot-dash line represents measurement results at 75° C.; and data indicated by the solid line represents measurement results at 150° C. It can be seen fromFIG. 24that the semiconductor device which is disclosed in the present specification is operating as a diode even at a high temperature of 150° C.

Thus, by shifting the gate voltage of the semiconductor device toward the negative side so as to allow regenerative power to be consumed at the channel diode, the power which is consumed by the resistor46in the regenerative power consuming circuit410decreases, thus making it possible to downsize the resistor46and the heat radiation mechanism which is provided in the resistor46.

Fourth Embodiment

Next, an inverter according to a fourth embodiment of the present disclosure will be described with reference to the drawings. The inverter of the present embodiment differs from the third embodiment in that it detects a regenerative current based not on the voltage across the smoothing capacitor but on a reverse current which flows in a semiconductor device.

FIG. 25is a functional block diagram showing a gate voltage controller49according to the present embodiment. The gate voltage controller49includes a forward overcurrent detection circuit52A and a reverse overcurrent detection circuit52B. In a usual operating state, the output of the PWM signal generation circuit is output as a gate signal for the transistors of the inverter.

the output of the current-voltage converter48, i.e., voltage of a value corresponding to the value of the current flowing between the drain pad and the second source pad, is input to the gate voltage controller49. The output voltage from the current-voltage converter48is input to both the forward overcurrent detection circuit52A and the reverse overcurrent detection circuit52B.

The forward overcurrent detection circuit52A compares a previously-set forward reference voltage value and the value of the output voltage of the current-voltage converter48, and if the absolute value of the output voltage of the current-voltage converter48is greater than the forward reference voltage value, determines an overcurrent in the forward direction. In this case, the forward overcurrent detection circuit52A outputs a signal to the transistor shutoff signal generation circuit54and the gate signal toggling circuit57. Upon receiving the signal, the gate signal toggling circuit57selects the output from the transistor shutoff signal generation circuit54, whereby the gate voltage controller49outputs a low gate voltage which has been generated by the transistor shutoff signal generation circuit54to shut off the transistors. As a result, the transistors in the leg in which an overcurrent has been detected are shut off, thus restraining an overcurrent from flowing to the load45.

The reverse overcurrent detection circuit52B compares a previously-set reverse reference voltage value and the value of the output voltage of the current-voltage converter48, and if the absolute value of the output voltage of the current-voltage converter48is greater than the reverse reference voltage value, determines that a regenerative current is occurring. In this case, as in the third embodiment, the reverse overcurrent detection circuit52B outputs a signal to the regenerative resistor switching control signal generation circuit56. Upon receiving the signal, the regenerative resistor switching control signal generation circuit56outputs a signal which causes the switching element47provided in the regenerative power consuming circuit410to conduct.

Moreover, the reverse overcurrent detection circuit52B outputs a signal to the gate negative bias signal generation circuit55and the gate signal toggling circuit57. Upon receiving the signal, the gate signal toggling circuit57selects the output from the gate negative bias signal generation circuit55, whereby the gate voltage controller49outputs a negative gate voltage which has been generated by the gate negative bias signal generation circuit55. As a result, the transistors which are the semiconductor devices of the legs440,442, and444have their resistance values in the reverse direction increased, so that more regenerative current is converted into heat and consumed also at the semiconductor devices of the legs440,442, and444.

In the present embodiment, the gate voltage controller49includes both of the gate negative bias signal generation circuit55and the regenerative resistor switching control signal generation circuit56, and upon determining that the regenerative current is equal to or greater than the predetermined value based on the value of the output voltage of the current-voltage converter48, operates both of the gate negative bias signal generation circuit55and the regenerative resistor switching control signal generation circuit56. However, only one of them may be operated instead. Moreover, the gate voltage controller49does not even need to include the circuit that is not to be operated.

FIG. 26is a time chart showing a protection operation when an overcurrent is flowing in the reverse direction in the inverter of the present embodiment. From time0to t8, the gate of the semiconductor device is ON, and therefore a forward current is flowing. At time t8, the gate signal becomes OFF, so that the current flowing in the semiconductor device once equals zero, but a reverse current begins to flow from time t9(the output voltage of the current-voltage converter48takes negative values). When the output voltage value exceeds a previously-set reverse reference voltage value at time t10, the reverse overcurrent detection circuit is turned ON, thus turning the gate of the switching element47for the regenerative resistor ON. The regenerative current flows through the resistor46, and regenerative energy is consumed in the regenerative resistor, so that the current gradually decreases and it no longer flows.

When a motor as the load45is forcibly driven in the reverse rotation direction, an overcurrent in the reverse direction may flow in the inverter402. when an overcurrent in the reverse direction flows, the voltage across the smoothing capacitor43may rapidly increase, possibly destroying the smoothing capacitor43. According to the present embodiment, when an overcurrent in the reverse direction is detected, the regenerative power is converted into heat by the resistance of the resistor46or the channel diode and consumed. As a result, the voltage of the smoothing capacitor43, that is, the voltage of the primary power source, never becomes excessively high, thereby preventing the smoothing capacitor43from being destroyed due to overvoltage.

Comparative Example

FIG. 27shows a block diagram of an inverter in which conventional semiconductor devices501ato501fwith a current detection function are used, where the semiconductor devices501ato501fdo not possess a channel diode function. Since there is no channel diode, an external free-wheel diode502needs to be employed in antiparallel connection with the semiconductor device of each arm. The conventional semiconductor device501with a current detection function is able to detect a forward current, but cannot detect a reverse current which flows in the external free-wheel diode. Therefore, direct detection of a regenerative current is not possible in the manner of the fourth embodiment of the present disclosure, and the determination that a regenerative current is flowing cannot be made unless the voltage across the smoothing capacitor is detected by the voltage detector420or a current detector for the external free-wheel diode is separately provided.

On the other hand, the semiconductor device according to the present disclosure, without the need to provide an external free-wheel diode, the reverse current flows also in the channel of the same semiconductor device, and the forward current flowing in the main region and the reverse current can both be indirectly detected from a small current which flows in the sense region.

Although the above embodiments illustrate examples where the first conductivity type is the n type and the second conductivity type is the p type, this is not a limitation. The first conductivity type may be the p type, and the second conductivity type may be the n type.

INDUSTRIAL APPLICABILITY

The technique disclosed in the present specification is useful in semiconductor device applications for use in power converters, for example. In particular, it is useful in power semiconductor device applications, for mounting on a power converter that is for onboard use or for use in industrial equipment or the like.

REFERENCE SIGNS LIST