System architecture with memory channel DRAM FPGA module

An accelerator controller comprises a detector and a loader. The detector detects runtime features of an application or a virtual machine and identifies an accelerator logic associated with the application or the virtual machine corresponding to the detected runtime features. The loader loads the identified accelerator logic into at least one dynamic random access memory (DRAM). The at least one DRAM array is selectively reconfigurable to behave like a look-up table (LUT) or to behave like a DRAM memory array based on the identified accelerator logic, and the at least one DRAM array is in a cache-coherent address space of the operating system environment. The accelerator logic may comprise a look-up table (LUT).

TECHNICAL FIELD

The present disclosure relates to computing technology. More particularly, the present disclosure relates to reconfigurable processing units and systems utilizing reconfigurable processing units.

BACKGROUND

A conventional processing accelerator may be implemented as a programmable logic device (PLD), such as a Field Programmable Gate Array (FPGA) or a Graphics Processing Unit (GPU), to provide efficient accelerator logic. Data-center and mobile-device applications are increasingly data-intensive and for such an application that utilizes a processing accelerator, a conventional memory hierarchy is unable to provide good performance and energy efficiency. The maximum efficiency of a processing accelerator in a conventional memory hierarchy is degraded by off-chip (i.e., non-CPU) memory accesses. Implementing accelerator logic close to memory to improve efficiency has thus far provided limited success because of high costs and sub-optimal performance. Further, if the accelerator logic is implemented close to memory, such as dynamic random access memory (DRAM), DRAM capacity is forfeited by integrating non-DRAM accelerator logic onto a DRAM semiconductor die.

Generally, a programmable logic device (PLD) is an electronic component that is used to form reconfigurable digital circuits. Unlike a logic gate or logic circuit, which generally has a fixed function, a PLD traditionally has an undefined function at the time of manufacture and often before the PLD can be used in a circuit, the PLD must be programmed, or reconfigured, to perform a desired function.

Traditionally, a PLD may include a combination of a logic device and a memory device. The memory is generally used to store a programming pattern that defines a desired function. Most of the techniques used for storing data in an integrated circuit have been adapted for use in a PLD, such as silicon anti-fuses, static random access memory (SRAM), erasable programmable read only memory (EPROM), electronically EPROM (EEPROM), non-volatile RAM, etc. Most PLDs generally include components that are programed by applying a special voltage (i.e., non-operational or high voltage) across a modified area of silicon inside the PLD that breaks or sets (depending on the technology) electrical connections and changes the layout of the electrical circuit of the PLD.

One of the most common types of PLDs is a field-programmable gate array (FPGA), which is an integrated circuit that is designed to be configured by a customer or a designer after manufacturing; hence the term “field-programmable.” An FPGA includes an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that allow the blocks to be “wired together”. The logic blocks of an FPGA can be configured to perform complex combinational functions, or merely simple logic gates like AND, XOR, etc.

SUMMARY

An embodiment provides an accelerator controller comprises a detector and a loader. The detector detects runtime features of an application or a virtual machine and identifies an accelerator logic associated with the application or the virtual machine corresponding to the detected runtime features. The loader loads the identified accelerator logic into at least one dynamic random access memory (DRAM). The at least one DRAM array may be selectively reconfigurable to behave like a look-up table (LUT) or to behave like a DRAM memory array based on the identified accelerator logic, and the at least one DRAM array may be in a cache-coherent address space of the operating system environment. The accelerator logic may comprise a look-up table (LUT).

Another embodiment provides an accelerator controller comprising: a detector to detect runtime features of an application or a virtual machine in which the runtime features may be based on at least one of a predefined identification of the application or the virtual machine, a function utilization, a central processing utilization, a memory utilization, a latency associated with the application or the virtual machine; and a loader to load an accelerator logic corresponding to the detected runtime features into at least one dynamic random access memory (DRAM) in which the at least one DRAM array may be selectively reconfigurable to behave like a look-up table (LUT) or to behave like a DRAM memory array based on the identified accelerator logic. The the detector may be further to identify an accelerator logic associated with the application or the virtual machine corresponding to the detected runtime features, and the at least one DRAM array may be in a cache-coherent address space of the system. In one embodiment, the accelerator logic may comprise a look-up table (LUT). In another embodiment, the DRAM array may be part of a Dual In-line Memory Module (DIMM).

Yet another embodiment provides a method, comprising detecting runtime features of an application or a virtual machine running in an operating system environment; selecting an accelerator logic corresponding to the detected runtime features; and storing the selected accelerator logic in at least one dynamic random access memory (DRAM) sub-array using load and store commands in which the at least one DRAM sub-array may be selectively reconfigurable to behave like a look-up table (LUT) or to behave like a DRAM memory array, in which the at least one DRAM sub-array may be configured to behave like an LUT, and in which the at least one DRAM sub-array may be in a cache-coherent address space of the operating system environment.

DETAILED DESCRIPTION

The subject matter disclosed herein relates to a system architecture that utilizes one or more dynamic random access memory field programmable gate arrays (DRAM-FPGAs) in a memory channel. A DRAM-FPGA uses a selectively reconfigurable DRAM cell array as lookup table (LUT); implements reconfigurable logic close to memory; and can be reconfigured into arbitrary logic designs.

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. It will be understood, however, by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail not to obscure the subject matter disclosed herein.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment disclosed herein. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” or “according to one embodiment” (or other phrases having similar import) in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. It is further noted that various figures (including component diagrams) shown and discussed herein are for illustrative purpose only, and are not drawn to scale. Similarly, various waveforms and timing diagrams are shown for illustrative purpose only.

The subject matter disclosed herein relates to a DRAM-based reconfigurable logic that uses a DRAM cell array as a lookup table (LUT); implements reconfigurable logic close to memory; and can be reconfigured into arbitrary logic designs. Moreover, such a DRAM-based reconfigurable logic is compatible with DRAM fabrication processes and is a good candidate for in-memory processing. Compared to conventional Field-Programmable Gate Arrays (FPGAs), DRAM-based reconfigurable logic provides higher density, lower cost, and more flexibility (e.g., self-modifying and fast dynamic reconfiguration that supports fast migration between different compute nodes in warehouse-scale data centers).

Conventional system architectures that utilize PLDs in the form of a Field Programmable Gate Array (FPGA) typically locate the FPGA in a PCIe slot, which is not in cache-coherent address space and provides low communication bandwith. Also, operation of accelerator logic in a FPGA in a PCIe slot is by explicit command provided by a driver.

FIG. 1depicts an embodiment of a reconfigurable memory logic device100according to the subject matter disclosed herein. The reconfigurable memory logic device100can be configured and connected to work in either a look-up table (LUT) mode or a regular dynamic random access memory (DRAM) mode. The reconfigurable memory logic device100comprises one or more sub-arrays101, an input/output (I/O) interface102, and a configuration interface103. The sub-arrays101are arranged in rows and columns. Each sub-array101may comprise a number of memory cells (not shown) that may also be arranged into an array of rows and columns. The reconfigurable memory logic device100may comprise other components and/or elements that are not depicted inFIG. 1.

In one embodiment, the sub-arrays101comprise dynamic read-only memory (DRAM). One or more of the sub-arrays101may be selectively reconfigured, or reprogrammed, using normal memory access operations to behave like a look-up table (LUT) or, alternatively, to behave like a traditional DRAM sub-array. As used herein, reconfigurable memory logic device100may generally be referred to herein as an FPGA. For embodiments of reconfigurable memory logic device100in which the sub-arrays101comprise DRAM, reconfigurable memory logic device100may be referred to herein as a “DRAM-FPGA.”

In one embodiment, the number of sub-arrays101that are configured to be LUTs or to be RAMs may be dynamically adjusted as desired. In another embodiment, one or more of the sub-arrays101may be reconfigurable to behave like an LUT or a traditional memory sub-array, while one or more of the sub-arrays101may be non-reconfigurable and are configured to behave as traditional memory sub-arrays. As used herein, a sub-array that is reconfigurable to behave like an LUT or behave like a traditional memory sub-array is referred to as a reconfigurable LUT (RLUT) sub-array.

If a sub-array101is configured to behave like an LUT, the LUT behavior may implement a logic function, such as, but not limited to, an arithmetic logic function (i.e., adder, multiplier, etc.), a logical function (AND, OR, XOR, etc.), or a combination thereof. The logic function may be altered by merely performing a memory write operation or a special write operation on the sub-array, thereby allowing logic functions to be dynamically reconfigured or altered during operation of the reconfigurable memory logic device100. A special write operation may include an indicator that the write operation involves a particular sub-array. Use of a traditional write operation (or similar) may allow for reprogramming of a selected sub-array101without the need of a special (i.e., non-operational or high) voltage, such as those used for programming EEPROMs, etc.

Co-mingling of RLUT sub-arrays and RAM sub-arrays may provide advantages. For example, the close proximity to the data stored in a RAM sub-array may speed the computation performed by an RLUT sub-array and lower the power requirements because data need not be moved across busses between individual components. Additionally, in one embodiment, one or more of the sub-arrays101may be accessed at a time, thereby reducing power and computation complexity of the reconfigurable memory logic device100. As such, the near-data computing provided by a DRAM RLUT may be faster and more efficient. By basing an RLUT sub-array upon DRAM-technology similar to that used to create a processor (not shown) and memory (not shown), an RLUT sub-array may exist within the same die or package as a processor and/or a memory. Using the same manufacturing process may lower the cost of the production of a system utilizing one or more RLUTs in a memory channel according to the subject matter disclosed herein. Further, basing the RLUT sub-arrays on DRAM subarrays, a higher density may be achieved in comparison to the density of an SRAM-based FPGA. For example, a DRAM-based RLUT may require only one transistor and one capacitor (1T1C) per memory cell or bit of information, whereas an SRAM-based FPGA may require six transistors (6T) per memory cell or bit of information. Additionally, a DRAM-based RLUT may result in a lower cost in comparison to SRAM- or Flash-based FPGAs.

The I/O interface102may be configured to read or write to a selected sub-array101. The write access may involve writing to the sub-array101to define whether the sub-array behaves as an LUT or behaves as a traditional DRAM sub-array. In some embodiments, all memory accesses or operations may pass through the I/O interface102. If the memory access is to a sub-array that stores data for revival either a RAM sub-array or an RLUT sub-array configured as a RAM sub-array, the I/O interface102may simply process the read/write request as a traditional memory access. If, however, the memory access is to an RLUT sub-array that is configured as an LUT, the I/O interface102may pass the memory access to the configuration interface103for processing.

The configuration interface103may be configured to adjust the routing of signals within the reconfigurable memory logic device100as a whole and/or within each respective RLUT sub-array101. For example, the configuration interface103may be configured to adjust the routing of signals between multiple sub-arrays configured as RLUTs and/or as RAMs. In one example embodiment, the I/O interface102may be configured to manage data access to the sub-arrays101. For example, in one embodiment, the I/O interface102may receive configuration information from a processor (not shown), that is used to configure the I/O interface102to control I/O access to the sub-arrays102so that memory locations in the sub-arrays appear as addressable registers. The configuration interface103may be configured to manage the interconnects and signal routing between the respective sub-arrays101by, for example, point-to-point routing, address-based routing, or a combination thereof. For example, in one embodiment, configuration information may be received by the I/O interface102that is used to configure the configuration interface103so that sub-arrays101may perform complex logical operation that may span multiple sub-arrays101. In one example embodiment, the I/O interface102may include the configuration interface103.

A memory access may include a write operation that stores a look-up table in a particular RLUT sub-array101. The memory access may also include a series of memory accesses depending upon the size of the LUT. In some embodiments, particular memory accesses may indicate the number of inputs to the LUT and the number of outputs from the LUT. Additionally, further memory accesses may indicate signal routing information regarding the RLUT sub-array101and/or whether two or more RLUT sub-arrays are cascaded or otherwise routed together to perform logical functions (e.g., an adder, etc.). Details of logic functions that may be provided by a sub-array101are set forth in U.S. patent application Ser. No. 14/814,503, entitled “DRAM-Based Reconfigurable Logic,” the disclosure of which is incorporated by reference herein. A memory access may alternatively include a write operation that reconfigures an RLUT sub-array101to behave as a traditional RAM sub-array.

FIG. 2depicts a block diagram of another example embodiment of the reconfigurable memory logic200in accordance with the subject matter disclosed herein. As depicted inFIG. 2, the reconfigurable memory logic200may be embodied on a separate die or a portion of a die in which the reconfigurable memory logic200may be integrated with other components (not shown) on a shared die, such as, but not limited to, a system-on-a-chip, a processor cache, etc. The reconfigurable memory logic200comprises one or more sub-arrays201, a plurality of communication buses202, input signal pads203and output signal pads204. The reconfigurable memory logic200may be implemented with a bus-based interconnection and routing scheme. The communications bus202may allow the routing scheme between the sub-arrays201to be dynamically altered to re-route signals between the sub-arrays201.

If a sub-array201is configured to behave like an LUT, the LUT behavior may implement a logic function, such as, but not limited to, an arithmetic logic function (i.e., adder, multiplier, etc.), a logical function (AND, OR, XOR, etc.), or a combination thereof. Details of logic functions that may be provided by a sub-array201are set forth in U.S. patent application Ser. No. 14/814,503, entitled “DRAM-Based Reconfigurable Logic,” the disclosure of which is incorporated by reference herein. The logic function may be altered by merely performing a memory write operation or a special write operation on the sub-array, thereby allowing logic functions to be dynamically reconfigured or altered during operation of the reconfigurable memory logic device200. A special write operation may include an indicator that the write operation involves a particular sub-array.

According to an example embodiment, one or more sub-arrays101ofFIG. 1and or one or more reconfigurable memory logic200ofFIG. 2may be used in a Dual In-line Memory Module (DIMM). That is, a DIMM may be configured to include one or more DRAM-FPGA modules, one or more RLUT modules, a combination of one or more DRAM-FPGA modules and one or more RLUT modules, or a combination of one or more DRAM-FPGA modules and/or one or more RLUT modules in combination with one or more regular DRAM modules.FIGS. 3A-3Drespectively depict example embodiments of DIMMs comprising one or more DRAM-FPGAs according to the subject matter disclosed herein.

InFIG. 3A, a DIMM300comprises a plurality of DRAM-FPGA modules301, of which only four DRAM-FPGA modules301are shown. Thus, for the particular example embodiment of DIMM300, all of the module positions are occupied by DRAM-FPGA modules301. Alternatively, all of the module positions may be occupied by RLUT modules in which each RLUT module comprises only reconfigurable look-up tables (RLUTs).

InFIG. 3B, a DIMM310comprises one or more DRAM-FPGAs modules301, of which two are shown, and one or more regular DRAM modules302, of which two are shown. For the particular example embodiment of DIMM310, the physical arrangement of the DRAM-FPGAs modules301and the regular DRAM modules302may be in any order. Alternatively, the configuration of DIMM310may one or more RLUT modules and one or more regular DRAM modules302.

InFIG. 3C, a DIMM320comprises a plurality of hybrid DRAM-FPGA modules303, of which only four hybrid DRAM-FPGAs modules303are shown. A hybrid DRAM-FPGA module303comprises one or more sub-arrays that are reconfigurable to behave like a look-up table (LUT) or to behave like a traditional DRAM sub-array, and one or more sub-arrays that are non-reconfigurable and behave like a traditional DRAM sub-array. That is, the configuration of DIMM320includes only hybrid DRAM-FPGA modules303.

InFIG. 3D, a DIMM330comprises one or more hybrid DRAM-FPGA modules303, of which two are shown, and one or more regular DRAM modules302, of which two are shown. For the particular example embodiment of DIMM330, the physical arrangement of the hybrid DRAM-FPGAs modules303and the regular DRAM modules302may be in any order.

It should be understood that other DIMM configurations are possible, such as, but not limited to a DIMM configuration comprising one or more DRAM-FPGA modules, one or more regular DRAM modules, one or more hybrid DRAM-FPGA modules and/or one or more RLUT modules.

FIG. 4depicts a functional block diagram of an example embodiment of a system architecture400that utilizes one or more DRAM-FPGAs in a memory channel according to the subject matter disclosed herein.FIG. 5depicts a flow diagram of a method500to detect runtime features of a virtual machine or an application and store acceleration logic corresponding to the virtual machine or application in a reconfigurable DRAM sub-array according to the subject matter disclosed herein. Operations501-504of method500that indicated inFIG. 4are discussed later in connection withFIG. 5.

Referring toFIG. 4, the system architecture400comprises a central processing unit (CPU)401coupled to system memory, such as random access memory (RAM) through a memory channel402and to one or more mass storage devices403. The RAM of the system memory may include static RAM (SRAM) and/or dynamic RAM (DRAM). In one example embodiment, the system memory comprises DRAM in one or more dual in-line memory modules (DIMMs)404, as depicted inFIG. 4. In one embodiment, the DIMMs404may be configured to include one or more DRAM-FPGA modules, one or more RLUT modules, a combination of one or more DRAM-FPGA modules and one or more RLUT modules, or a combination of one or more DRAM-FPGA modules and/or one or more RLUT modules in combination with one or more regular DRAM modules. DRAM-FPGAs in the memory channel are embodied in one or more DIMMs.

An operating system (OS)405runs on CPU401. The operating system405may be, but is not limited to, a Unix-based operating system, a Unix-like operating system, Linux-based operating system, a Chrome-based operating system or a windows-based operating system. One or more virtual machines (VM) may be running on the operating system405. As depicted inFIG. 4, VM1-VMnare running on operating system405. In a situation in which the system architecture400is embodied in a data-center environment, the virtual machines VM1-VMnmay represent data-center applications. In a situation in which the system architecture400is embodied in a mobile-device environment, the virtual machines VM1-VMnmay represent mobile-device applications.

The operating system405includes an accelerator controller406that detects the instantiation of a virtual machine VM by detecting runtime features407that are associated with the instantiated virtual machine VM. As used herein, the term “runtime features” of a virtual machine VM means the operating characteristics of, such as, but not limited to, an identity of the VM and/or a particular set up configuration. In one embodiment, the accelerator controller406may be software based, hardware based, or a combination thereof. In one embodiment, the accelerator controller406may comprise a software module in the operating system405. In another embodiment, the accelerator controller406may comprise a hardware module in a memory controller (not shown inFIG. 4).

In one embodiment, the accelerator controller406includes a detector407and a loader408. The detector407detects runtime features409of an application or a virtual machine and identifies an accelerator logic410associated with the application or the virtual machine corresponding to the detected runtime features409. In another embodiment, the accelerator controller406profiles a virtual machine VM or an application at run time and collects a runtime signature, such as, but not limited to, a function utilization, a central processor unit (CPU) utilization, a latency, and/or other microarchitecture statistics, and uses the runtime signature to search a repository of accelerator logic410. In one embodiment, the runtime features409that are used to detect the runtime features of a virtual machine VM or an application may be stored in the accelerator controller406or may be part of accelerator controller406. In another embodiment, the runtime features409may be stored in, for example, a storage403and loaded into the accelerator logic406at the time the accelerator controller406is initialized.

Based on the detected runtime features409of a virtual machine VM (or an application), the accelerator controller406selects and loader408retrieves the accelerator logic410that may be used by the virtual machine, which may be stored in mass storage device403, and loads the accelerator logic410for the virtual machine into a DRAM-FPGA411using memory channel store instructions. In one embodiment, the accelerator logic410that is retrieved may be requested by the virtual machine VM or may be optionally requested by the virtual machine VM. In another embodiment, the accelerator logic410may be requested or recommended by the operating system405, or by a user. In an alternatve embodiment, the accelerator controller406may identify the accelerator logic410for the virtual machine VMn, and the virtual machine VMn retrieves and stores the accelerator logic410in the DRAM-FPGA411using memory channel store instructions. As the accelerator logic410is stored in the DRAM-FPGA411, which is in the memory channel402of the system400, the accelerator logic410is thus stored in cache-coherent address space that can be accessed directly by CPU401. In that regard, the accelerator logic410is stored in a cach-coherent address space accessible by the operation system405.

As depicted inFIG. 4, the virtual machine VMn, the runtime features409, the accelerator logic410, the particular DRAM-FPGA411storing the accelerator logic410, and the DRAM-FPGA driver412for the virtual machine VMnare indicated by a crosshatching that extends from the upper left to the lower right. Other virtual machines, their respective runtime features, accelerator logic and DRAM-FPGA locations are also indicated by correspondingly similar crosshatching. In one embodiment, the accelerator controller406communicates the address of the DRAM-FPGA driver412corresponding to the virtual machine VM to the virtual machine VM. As the virtual machine VM accesses the DRAM-FPGA driver412, the DRAM-FPGA driver412accesses the accelerator logic410for the virtual machine VM, which is stored in the DRAM-FPGA411.

FIG. 5depicts a flow diagram of a method500to detect runtime features of a virtual machine or an application and store acceleration logic corresponding to the virtual machine or application in a reconfigurable DRAM sub-array according to the subject matter disclosed herein. Referring toFIG. 4, consider a situation in which a virtual machine VMnis instantiated at501ofFIG. 5. The accelerator controller406detects that the virtual machine VMnhas been instantiated based on runtime features409associated with virtual machine VMn. At502, the accelerator controller406selects and retrieves the accelerator logic410for the virtual machine VMn. At503, the loader408of the accelerator controller406stores the selected accelerator logic410in a DRAM-FPGA411using memory channel store instructions. In an alternatve embodiment, the accelerator controller406identifies the accelerator logic410for the virtual machine VMn at503, and the virtual machine VMn retrieves and stores the accelerator logic410in the DRAM-FPGA411using memory channel store instructions at502ainFIG. 4. At504, the virtual machine VMnaccesses the accelerator logic308in the DRAM-FPGA411through a DRAM-FPGA driver412. In another example embodiment, the system architecture400is applicable to a point-to-point processor interconnect environment, such as, but not limited to a QuickPath Interconnect (QPI) environment. For example,FIG. 6depicts a system architecture600that is QPI-based and that utilizes one or more DRAM-FPGAs in a memory channel according to the subject matter disclosed herein. InFIG. 6, system architecture600comprises two CPUs501that are coupled to system memory, such as random access memory (RAM), through a memory channel602, and to one or more mass storage devices603. The RAM of the system memory may include static RAM (SRAM) and/or dynamic RAM (DRAM). In one example embodiment, the system memory comprises DRAM embodied in one or more dual in-line memory modules (DIMMs)604. One or more DRAM-FPGAs605may be utilized in the memory channels602of the respective CPUs601. The CPUs601are coupled to each other through a QPI-based interconnect606.

FIG. 7depicts a functional block diagram of an example embodiment of an information-processing system700that may utilize a system architecture that comprises one or more DRAM-FPGAs in a memory channel according to the subject matter disclosed herein. The information-processing system700may include one or more of devices constructed according to the subject matter disclosed herein.

In various embodiments, the information-processing system700may be embodied as a computing device, such as, but not limited to, a laptop, desktop, workstation, server, blade server, personal digital assistant, smartphone, tablet, and other appropriate computers, etc. or a virtual machine or virtual computing device thereof. In various embodiments, the information-processing system700may be used by a user (not shown).

The information-processing system700may further comprise a central processing unit (CPU), logic, or processor710. In some embodiments, the processor710may include one or more functional unit blocks (FUBs) or combinational logic blocks (CLBs)715. In such an embodiment, a combinational logic block may include various Boolean logic operations (e.g., NAND, NOR, NOT, XOR, etc.), stabilizing logic devices (e.g., flip-flops, latches, etc.), other logic devices, or a combination thereof. The combinational logic operations may be configured in simple or complex fashion to process input signals to achieve a desired result. It is understood that while a few illustrative examples of synchronous combinational logic operations are described, the disclosed subject matter is not so limited and may include asynchronous operations, or a mixture thereof. In one embodiment, the combinational logic operations may comprise a plurality of complementary metal oxide semiconductors (CMOS) transistors. In various embodiments, these CMOS transistors may be arranged into gates that perform the logical operations; although it is understood that other technologies may be used and are within the scope of the disclosed subject matter. In some embodiments, the components comprising processor610may comprise components embodying an acceleration controller according to the subject matter disclosed herein.

The information-processing system700according to the disclosed subject matter may further include a volatile memory720(e.g., a Random Access Memory (RAM), etc.) that is accessible by processor710through a memory channel. The information-processing system700according to the disclosed subject matter may further include a non-volatile memory730(e.g., a hard drive, an optical memory, a NAND or Flash memory, etc.). In some embodiments, either the volatile memory720, the non-volatile memory730, or a combination or portions thereof may be referred to as a “storage medium.” In various embodiments, the volatile memory720and/or the non-volatile memory730may be configured to store data in a semi-permanent or substantially permanent form.

In various embodiments, one or more reconfigurable look-up tables (RLUTs) described above may be included in the volatile memory720or even the non-volatile memory730. As described above, a RLUT may be included as part of a DRAM or other memory. As described above, in some embodiments, a portion of the memory720or730may be employed to store data and a second portion may be employed as a RLUT. In some embodiments, the RLUT may also be considered part of the processor and/or logic710. As described above, the RLUT may perform one or more logic functions, and therefore may execute instructions.

In various embodiments, the information-processing system700may include one or more network interfaces740configured to allow the information-processing system700to be part of and communicate via a communications network. Examples of a Wi-Fi protocol may include, but is not limited to, Institute of Electrical and Electronics Engineers (IEEE) 802.11g, IEEE 802.11n, etc. Examples of a cellular protocol may include, but are not limited to: IEEE 802.16m (a.k.a. Wireless-MAN (Metropolitan Area Network) Advanced), Long Term Evolution (LTE) Advanced), Enhanced Data rates for GSM (Global System for Mobile Communications) Evolution (EDGE), Evolved High-Speed Packet Access (HSPA+), etc. Examples of a wired protocol may include, but are not limited to, IEEE 802.3 (a.k.a. Ethernet), Fibre Channel, Power Line communication (e.g., HomePlug, IEEE 1901, etc.), etc.

The information-processing system700according to the disclosed subject matter may further include a user interface unit750(e.g., a display adapter, a haptic interface, a human interface device, etc.). In various embodiments, the user interface unit750may be configured to either receive input from a user and/or provide output to a user. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input.

In various embodiments, the information-processing system700may include one or more other devices or hardware components760, such as, but not limited to a display or monitor, a keyboard, a mouse, a camera, a fingerprint reader, a video processor, etc.

The information-processing system700according to the disclosed subject matter may further include one or more system buses705. In such an embodiment, the system bus705may be configured to communicatively couple the processor710, the volatile memory720, the non-volatile memory730, the network interface740, the user interface unit750, and one or more hardware components760. Data processed by the processor710or data input from outside of the non-volatile memory730may be stored in either the non-volatile memory730or the volatile memory720.

In various embodiments, the information-processing system700may include or execute one or more software components770. In some embodiments, the software components770may include an operating system (OS) and/or an application. In some embodiments, the OS may be configured to provide one or more services to an application and manage or act as an intermediary between the application and the various hardware components (e.g., the processor710, a network interface740, etc.) of the information-processing system700. In such an embodiment, the information-processing system700may include one or more native applications, which may be installed locally (e.g., within the non-volatile memory730, etc.) and configured to be executed directly by the processor710and directly interact with the OS. In such an embodiment, the native applications may include pre-compiled machine-executable code. In some embodiments, the native applications may include a script interpreter (e.g., C shell (csh), AppleScript, AutoHotkey, etc.) or a virtual execution machine (VM) (e.g., the Java Virtual Machine, the Microsoft Common Language Runtime, etc.) that are configured to translate source or object code into executable code which is then executed by the processor710. In some embodiments, one or more of the software components770may comprise executable instructions embodying an acceleration controller according to the subject matter disclosed herein.