Bulk resistance control technique

The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.

FIELD OF THE INVENTION

This invention generally relates to the field of electrostatic discharge (ESD) protection circuitry, and more specifically, for providing a technique for implementing bulk connection to improve the performance of metal oxide semiconductor (MOS) devices in the silicon over insulator (SOI) protection circuitry of an integrated circuit (IC).

BACKGROUND OF THE INVENTION

Recently, advanced SOI technology nodes are being used more extensively due to a number of advantages mainly related to the reduction of the power consumption, smaller silicion area, lower gate delay and reduced parasitic junction capacitance. Moreover, due to the completely isolated transistors, latch-up is no longer an issue.

However, SOI technology comes also with a few disadvantages such as the higher cost for starting material, floating body and history effects, increased self-heating issues and higher design complexity. Another main disadvantage is the fact that traditional snap-based ESD solutions have a much reduced (It2) failure current. This It2 reduction compared to bulk is related to the thin silicon film and the complete isolation of the transistors which limits the dissipation and transfer of the generated heat.

For ESD protection, the MOS device is often used in bipolar mode. Avalanche multiplication on the drain side of the MOS triggers the intrinsic parasitic bipolar device. The amount of current needed, and thus the amount of avalanche multiplication needed, scales inversely proportional with the resistance of the Pwell of NMOS (Nwell in case of PMOS) between pwell (Nwell) connection and the gate region. Since the avalanche multiplication causes heat, reducing the avalanche multiplication can increase the failure current It2 of the MOS device. Therefore, it is important to control the bulk resistance to adjust the ESD properties of the MOS device.

In most CMOS processes the bulk connection is created by adding guard rings around the MOS device. For example, a guard ring is a heavily p-doped region surrounding the MOS. This p-doped region, the same doping as the Pwell, connects the pwell with an external node. With this node the Pwell of the NMOS is controlled. In SOI technologies three methods exist. One such method includes a schematic to view layout of a single finger MOS device100having source region102, drain region104, and a gate region106disposed between the source102and the drain regions104as shown inFIG. 1. In this process, a bulk connection108is placed at the end of the gate106. The gate106extension to the bulk connection108area is necessary to avoid isolating the bulk connection form the gate area with isolation such as a shallow trench isolation (STI) or deep trench isolation (DTI) or other isolations known to one skilled in the art. The disadvantage with this technique is that the bulk connection is only at the both sides of the gate. With large gate width only the side parts of the MOS has a good connection with the bulk connection. The middle part is connected through a large (well) resistance with the bulk connection.

A second technique is displayed inFIG. 2which includes a schematic layout view and cross section view of a single finger MOS device200having source region202, drain region204, and a gate region206disposed between the source202and the drain regions204. A bulk connection208is placed at the end of the gate206. This technique includes an isolation between the gate area206and bulk connection208is used which does not reach to a buried oxide (BOX)210. This isolation is commonly referred to as PTI (partial trench isolation)212as shown inFIG. 1. In some SOI technologies, an STI (Shallow trench isolation)214or another isolation can be used with the same effect as illustrated inFIG. 2. A very basic layout view and cross section are shown inFIG. 2. Note the difference between the PTI212, which does not reach to the BOX210, however, and STI214which does reach down to the BOX210. However, in some technologies the STI does not reach to the box either. In this case there is no need for a separate PTI layer and STI can be used instead. The disadvantage of this technique is similar to the technique discussed inFIG. 1that the bulk connection is only at the both sides of the gate. Another disadvantage is that an extra process option, for example PTI is needed. Since extra process steps are very costly, this technique is undesirable.

A third technique includes a schematic layout of a top view of a two finger MOS device300having a source regions302, drain regions304and gate regions306disposed between the source302and the drain regions304. This process includes interrupting the source302with a bulk connection area308. Silicide shorts this region with the source302. This is shown inFIG. 3, where there is bulk connection308through P+ area, interrupting the source302of the MOS device300. The silicide layer connects the bulk P+ area with the source. The disadvantage if this technique is that the bulk connection is always shorten to the source. In some cases this is acceptable, but normally it is advantageous (improved triggering) if the bulk connection can be controlled in a different way then the shortening to source.

Therefore, a need exists to provide an improved technique enabling a better control of the bulk resistance to adjust the ESD properties for an improved performance of the MOS devices. Furthermore, it is advantageous to have a good bulk connection not only to control the bulk of one finger, but also to couple the different fingers (channel regions) together to improve multifinger triggering.

SUMMARY OF THE INVENTION

In one embodiment of the present invention, there is disclosed an electrostatic discharge (ESD) MOS transistor for providing ESD protection. The MOS transistor includes at least one interleaved finger having at least one source region of a first conductivity type, at least one drain region of the first conductivity type and at least one gate region formed over a channel region disposed between the source and drain regions. The MOS transistor further includes at least one isolation gate formed in at least one of the source, the drain and the gate regions of the at least one interleaved finger.

In another embodiment of the present invention, there is disclosed a MOS transistor for providing ESD protection. The MOS transistor includes at least one interleaved finger having at least one source region of first conductivity type, at least one drain region of the first conductivity type and at least one gate region formed over a channel region disposed between the source and drain regions. The MOS transistor also includes at least one isolation gate formed in at least one of the source, the drain and the gate regions of the at least one interleaved finger. The MOS transistor further includes a bulk connection of a second conductivity type placed in one of the source, gate and drain regions of the at least one interleaved finger.

In further embodiment of the present invention, there is disclosed a MOS transistor for providing ESD protection. The MOS transistor includes a plurality of interleaved fingers. Each of the fingers include at least one source region, at least one drain region and at least one gate region formed over a channel region disposed between the source and the drain regions, such that the channel regions of the two fingers are connected together by at least one isolation gate.

DETAILED DESCRIPTION OF THE INVENTION

The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits (ICs). The present invention can be practiced in conjunction with silicon-on-insulator (SOI) integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections and layouts of portions of an IC during fabrication are not drawn to scale and form, but instead are drawn so as to illustrate the important features of the invention.

The present invention is described with reference to SOI CMOS devices. However, those of ordinary skill in the art will appreciate that selecting different dopant types and adjusting concentrations or changing the isolation types allows the invention to be applied to other processes that are susceptible to damage caused by ESD. Furthermore, it is noted that the present invention is discussed in terms of NMOS ESD devices, however, those skilled in the art recognize that the present invention is also applicable to PMOS ESD devices in a similar manner.

The invention proposes a new layout technique enabling a better control of the bulk resistance by using external impedance elements such as resistors. Key to the invention is the isolation of the bulk connection from drain and source by either adding silicide block (SB) or introducing a poly gate between drain/source and bulk connection. In previous art this isolation was created by using trench isolations such as STI, PTI or DTI. In this invention, another approach is introduced, using either a poly gate or a silicide block layer. For SOI technologies, or other technologies where an isolated Pwell is possible, this external impedance provides an excellent way of controlling the bulk resistance. The advantage of controlling the bulk in this manner is that during ESD, the NMOS is turned much faster in snapback than when the bulk is connected to ground. During normal operation the bulk can be connected to ground to limit leakage. Especially for SOI technologies, this technique is very advantageous because the well is isolated from other wells, such that each well can be controlled separately and therefore the well can be controlled much better. Whereas, generally, in bulk CMOS, the wells are connected together, making it more difficult to control one area separately. Therefore, for other technologies, the control of well is also possible, however is more limited, thereby limiting the performance of the CMOS.

Referring toFIG. 4A, there is shown a top view of a single finger NMOS device400according to one embodiment of the present invention. The NMOS400comprises a source region402, a drain region404and a gate region406. The gate region406is disposed over a channel formed by Pwell (not shown) between the source402and the drain region404in a conventional manner known by those skilled in the art. As shown inFIG. 4A, the drain404is connected via a first metal line401to a first voltage potential403connected to external circuitry (not shown) and the source404is coupled to via a second metal line405to a second voltage potential407preferably connected to ground or another circuitry (not shown).

The source region402is interrupted by P+ areas or bulk connection408called is placed as illustrated inFIG. 4A. In order to avoid shorting the P+408with the N+ source402through silicide, an isolation gate410is placed between P+408and N+402. The isolation gate410provides an isolation between the P+ bulk connection408and the source402. This isolation gate410is made in the same way as the gate406, thus named isolation poly410. Alternatively, isolation poly410or in more general isolation gate can be preferably replaced with silicide block or STI block or any other isolation layer, not only in this embodiment, but for all other implementations in this invention. For the purpose of providing a larger area efficiency, isolation poly will be used throughout this invention application.

Since this bulk connection408is now isolated from the source402by the isolation poly410, it can be connected to an external poly resistance412through contacts409via a third metal line414to increase the bulk resistance to any desirable level. The contacts409are the connection between the bulk region and the metal line414to the poly resistance412. The isolation poly410creates a high ohmic path between the source402and the bulk connection408by blocking the silicide layer. Note, that the silicide between the source402or the bulk connection408is not connected with the silicide on the isolation poly (gate)410. So the three regions, source402, isolation poly410and the bulk connection408are electrically isolated from each other. In case of using a silicide block as an isolation gate410instead of poly, the silicide is blocked at the border between source402and the bulk connection408. This also prevents the shortening of the source402and bulk connection408. Thus, the added poly resistance412can be adjusted to influence the bulk resistance408, thereby controlling the voltage of the bulk connection408and the voltage of the channel region under the gate406. Note that although in this implementation a poly resistor is proposed, the invention is not limited to any specific kind of impedance element, being active or passive such as diodes, MOS devices, well resistances, capacitors, SCRs, inductors, short, etc. Although, not shown inFIG. 4the bulk connection area408can be alternatively be placed at the drain side404or at the both drain404and the source402sides.

Also shown areFIG. 4B,FIG. 4CandFIG. 4Ddepicting cross section views along line A, line B and line C respectively of the single finger NMOS400ofFIG. 4A. As shown, the single finger NMOS device400is formed in a substrate416having an insulating layer (BOX)418buried over the substrate416. Specifically, a P-well420is formed over the BOX layer418and the single finger NMOS device400is formed in the P-well420. Preferably, two Shallow Trench Isolation (STI) regions422are formed at each end of the substrate416. In particular, the STI regions422extend down the buried oxide (BOX) layer418. It is noted that even though STI is used as one example of the isolation, it's also possible to use partial trench isolation (PTI), deep trench isolation (DTI), or other isolations known in the art. Alternatively, it is also possible to not include these isolations and place another device adjacent to this structure.

Referring toFIG. 5, there is shown a top view of a two finger NMOS400in accordance with another embodiment of the present invention. Each of the finger400is placed adjacent to each other and comprises the source402, drain404and the gate406disposed over the channel region. An isolation poly410is placed in the source region which in turn connects the gates406. of each finger. Thus, the channels of the two adjacent fingers400are connected below the isolation poly410, therefore improving bulk coupling of the fingers. The two channel regions of the two fingers are connected together, so that during triggering current from the first finger which triggers, is also injected in the second finger, thereby improving multifinger triggering. Similar toFIG. 4, a bulk connection408can be added inFIG. 5isolated from the source region through the isolation poly410. This isolation poly can be also connected to an external poly resistance412via a metal line414to increase the bulk resistance to any desirable level. The isolation poly and bulk connection can be also placed in the drain404instead of the source402. It's noted also that with a multifinger structure this technique must not be applied to all the fingers.

Referring toFIG. 6A, there is shown a top view of a multiple finger NMOS400, in accordance with further embodiment of the present invention. Each of the finger400is placed adjacent to each other and comprises the source402, drain404and the gate406disposed over the channel region. An isolation poly410is placed in the source, which in turn connects the gates406of each adjacent finger400. Thus, the two adjacent fingers400are connected below the isolation poly410, therefore improving bulk coupling of the fingers as discussed above. Similar toFIG. 4, the bulk connection408can be placed between the isolation poly410inFIG. 6Aand can be connected to an external poly resistance412via a metal line414to increase the bulk resistance to any desirable level. In this figure an additional technique is shown, i.e. the contacts409and the metal line414of the drain404are left out in the drain region404at the metal connection of the bulk region408to the impedance element, i.e. poly resistance412. This additional technique is applicable if the first metal layer401is used as connection to prevent shortening between the drain404and the bulk connection408.

Additionally, this bulk coupling can be even more exploited by extending the isolation poly410over the drain junctions404, thus connecting all the gates406of all the multiple fingers400, as illustrated inFIG. 6B. The advantage shown inFIG. 6B is that the channel region of all the fingers400are better coupled together through the isolation poly410and through the bulk connection408. It's noted that also in this figure, the technique can be applied without the bulk connection408only at the isolation gate410.

Referring toFIG. 7, there is shown an another embodiment of the multiple finger device400of the present invention. In this embodiment, both the drain404and the source406regions are interrupted with P+ bulk areas408. The advantage with this technique is that it provides a better bulk connection and easier metallization (i.e. less metal layers needed).

Referring toFIG. 8, there is shown a further embodiment of the multiple finger device400. In this implementation, the P+ bulk connection areas408are merged into one long stripe over all the fingers of the device400. Aside from previously mentioned advantages of the invention, additional advantages are associated with this embodiment. Since this P+ area408is low ohmic due to silicidation, the contacts409to this region can be placed at the end of the P+ stripe region408. This frees up the second metal line405above the bulk connection area, such that this metal can used for another purpose. InFIG. 8, this metal can be used to connect the different parts of source402together (i.e. the source402isolated through the placement of the bulk connection408) and can also be used to connect the different parts of the drain404. Since no contacts409need to be placed between the isolation poly410, these can be placed more closely together, thus saving the area to make a more compact multi-finger device400.

Furthermore, in this implementation it is easy to see that gates406in between the bulk connection areas408can be omitted without loss of performance

Referring toFIG. 9, there is shown an even further embodiment of the multiple finger device400. The bulk connection408is placed at one end of the isolation poly410. This P+ area408can be enlarged to allow for more contacts409to make a better connection to the impedance element, i.e. the poly resistor412.

It is noted that for all the embodiments as described above, the isolation poly410and thus the gate406of the MOS device400can be connected to any circuitry. For instance, an ESD circuitry could pull the gate/isolation poly of the device high (low for PMOS) during ESD thus reducing the amount of avalanche multiplication even further. This will also reduce the bulk resistance below the isolation poly410and therefore reduce the bulk resistance difference between the outer and inner fingers. Also note that if the P+ bulk area408would be omitted or placed elsewhere, the isolation poly410would still play an important role such that it would increase bulk coupling between the fingers such that the channel regions of the different fingers are connected together (through a channel region) under the isolation poly to improve multifinger triggering.

Some examples of the use of this improved NMOS described in the inventions is the use as an ESD protection clamp or as a trigger to another clamp or as an output driver, or any other known ESD devices.

Although various embodiments that incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings without departing from the spirit and the scope of the invention.