Device including a ring-shaped metal structure and method

A device includes a semiconductor chip with a ring-shaped metal structure extending along the contour of a first main surface of the semiconductor chip. An encapsulation body encapsulates the semiconductor chip and defines a second main surface. An array of external contact pads attaches to the second main surface of the encapsulation body, and at least one external contact pad of the array of external contact pads electrically couples to the ring-shaped metal structure.

BACKGROUND

One aspect relates to a device including a semiconductor chip having a ring-shaped metal structure and an external contact pad coupled to the ring-shaped metal structure. Furthermore, the invention relates to a method of manufacturing such a device.

Electronic devices including semiconductor chips concentrate heat in a very small space. In order to ensure the reliability of the devices, heat accumulation in the interior of the devices should be reduced. Therefore, ways are sought to improve the heat transfer away from the devices to maintain acceptable operating conditions.

DETAILED DESCRIPTION

As employed in this Specification, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together; intervening elements may be provided between the “coupled” or “electrically coupled” elements.

Devices containing semiconductor chips are described below. The semiconductor chips may be of different types, may be manufactured by different technologies and may include for example integrated electrical, electro-optical or electro-mechanical circuits or passives. The integrated circuits may, for example, be designed as logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, power integrated circuits, memory circuits or integrated passives. Furthermore, the semiconductor chips may include high-frequency circuits and, in one embodiment, millimeter wave integrated circuits that operate at microwave frequencies in the range from 1 to 300 GHz. The semiconductor chips need not be manufactured from specific semiconductor material, for example Si, SiC, SiGe, GaAs, and, furthermore, may contain inorganic and/or organic materials that are not semiconductors, such as for example discrete passives, antennas, insulators, plastics or metals.

The semiconductor chips may have contact pads (or electrodes), which allow electrical contact to be made with the integrated circuits included in the semiconductor chips. One or more metal layers may be applied to the contact pads of the semiconductor chips. The metal layers may be manufactured with any desired geometric shape and any desired material composition. The metal layers may, for example, be in the form of a layer covering an area. Any desired metal or metal alloy, for example aluminum, titanium, gold, silver, copper, palladium, platinum, nickel, chromium or nickel vanadium, may be used as the material. The metal layers need not be homogenous or manufactured from just one material, that is to say various compositions and concentrations of the materials contained in the metal layers are possible. The contact pads may be situated on the active main surfaces of the semiconductor chips or on other surfaces of the semiconductor chips.

Each semiconductor chip may include a ring-shaped metal structure extending along the contour of the active main surface of the semiconductor chip. The ring-shaped metal structure may be continuous and may extend along the entire contour of the active main surface. The ring-shaped metal structure may be also discontinuous and may include one or more gaps. The ring-shaped metal structure may be fabricated when the semiconductor chip is still in the wafer bond, i.e. before the wafer is diced to produce the individual semiconductor chips. The semiconductor chip contains a semiconductor substrate, for example a silicon or gallium arsenide substrate, and a number of metal layers stacked over the semiconductor substrate. In the area of the ring-shaped metal structure, vias may connect adjacent metal layers so that the top metal layer of the ring-shaped metal structure is coupled to the semiconductor substrate.

The devices described below include external contact pads (or external contact elements), which may be of any shape and size. The external contact pads may be accessible from outside the device (or solder deposits may be placed on the external contact pads) and may thus allow electrical contact to be made with the semiconductor chips from outside the device. Furthermore, the external contact pads may be thermally conductive and may serve as heat sinks for dissipating the heat generated by the semiconductor chips. The external contact pads may be composed of any desired electrically conductive material, for example of a metal, such as copper, aluminum, nickel or gold, a metal alloy or an electrically conductive organic material. Solder material, such as solder balls or solder bumps, may be deposited on the external contact pads.

Two or more metal layers may be placed over the semiconductor chip. The metal layers may, for example, be used to produce a redistribution layer. The metal layers may be employed as wiring layers to make electrical contact with the semiconductor chips from outside the device and/or to make electrical contact with other semiconductor chips and/or components contained in the device. The metal layers may couple the contact pads of the semiconductor chips to the external contact pads. The metal layers may have other functions as well, for example they may be used as ground or electrical shielding layers. The metal layers may be manufactured with any desired geometric shape and any desired material composition. For example, the metal layers may be structured and may have the shape of conductor lines (or conductor tracks), but may also be in the form of a layer covering an area. Any desired metal, for example aluminum, nickel, palladium, titanium, titanium tungsten, silver, tin, gold or copper, or metal alloys may be used as the material. The metal layers need not be homogenous or manufactured from just one material, that is to say various compositions and concentrations of the materials contained in the metal layers are possible. Furthermore, the metal layers may be arranged above or below or between electrically insulating layers.

The semiconductor chips or at least parts of the semiconductor chips may be covered with an encapsulation material. The encapsulation material may be electrically insulating and may be any appropriate duroplastic, thermoplastic or thermosetting material or laminate (prepreg) and may contain filler materials. Various techniques may be employed to cover the semiconductor chips with the electrically insulating material, for example compression molding, injection molding, powder molding, liquid molding or lamination.

The encapsulation material may be used to produce fan-out type packages. In a fan-out type package at least some of the external contact pads and/or metal layers connecting the semiconductor chip to the external contact pads are located laterally outside of the outline of the semiconductor chip or do at least intersect the outline of the semiconductor chip. Thus, in fan-out type packages, a peripherally outer part of the package of the semiconductor chip is typically (additionally) used for electrically bonding the package to external applications, such as application boards etc. This outer part of the package encompassing the semiconductor chip effectively enlarges the contact area of the package in relation to the footprint of the semiconductor chip, thus leading to relaxed constraints in view of package pad size and pitch with regard to later processing, e.g. second level assembly.

FIGS. 1A and 1Bschematically illustrate a device100in cross-sectional and plan views.FIG. 1Aillustrates the cross section through the device100along a line A-A′ that is depicted inFIG. 1B. The device100includes a semiconductor chip10, which has a ring-shaped metal structure11extending along the contour12of a first main surface13of the semiconductor chip10. An encapsulation body14encapsulates the semiconductor chip10and defines a second main surface15. An array of external contact pads16is attached to the second main surface15of the encapsulation body14. At least one external contact pad16of the array of external contact pads16is electrically coupled to the ring-shaped metal structure11of the semiconductor chip10.

FIGS. 2A to 2Eschematically illustrate a method for production of a device200. A cross section of the device200obtained by the method is illustrated inFIG. 2E. A first semiconductor chip10and a second semiconductor chip17are provided (seeFIG. 2A). Both semiconductor chips10and17include a ring-shaped metal structure11extending along the contour12of a first main surface13of the respective semiconductor chip10and17. The semiconductor chips10and17are covered with an encapsulation material14forming an encapsulation body (seeFIG. 2B). A metal layer18is deposited over the first semiconductor chip10and the encapsulation material14(seeFIG. 2C). A plurality of external contact pads16is placed over the encapsulation material14(seeFIG. 2D). The metal layer18electrically couples at least one external contact pad16of the plurality of external contact pads16to the ring-shaped metal structure11of the first semiconductor chip10. The first semiconductor chip10is separated from the second semiconductor chip17by removing the encapsulation material14partially.

FIGS. 3A to 3Pschematically illustrate a method for production of a device300, a cross-sectional view and a plan view of which are illustrated inFIGS. 30 and 3P, respectively. The device300is an implementation of the devices100and200. The details of the device300that are described below can therefore be likewise applied to the devices100and200. Furthermore, the method illustrated inFIGS. 3A to 3Pis an implementation of the method illustrated inFIGS. 2A to 2E. The details of the production method that are described below can therefore be likewise applied to the method ofFIGS. 2A to 2E.

Firstly, a plurality of semiconductor chips10is provided. One of these semiconductor chips10is exemplarily illustrated on the left side ofFIG. 3Ain cross-sectional and plan views. A portion of the cross-section of the semiconductor chip10indicated by dashed lines is illustrated enlarged on the right hand side ofFIG. 3A.

The semiconductor chip10illustrated inFIG. 3Ahas a first main surface13, on which a plurality of contact pads20may be located. The integrated circuits embedded in the semiconductor chip10can be electrically accessed via the contact pads20. The contact pads20may be made of a metal, for example gold, aluminum or copper. Furthermore, the semiconductor chip10has a ring-shaped metal structure11extending along the contour12of the main surface13of the semiconductor chip10. The contour of the main surface13may be defined by the edges between the main surface13and the side surfaces of the semiconductor chip10. In the example ofFIG. 3A, the contour12of the main surface13has a length of2a+2b. The ring-shapedmetal structure11may be continuous and may extend along the entire contour12of the main surface13. The ring-shaped metal structure11may be also discontinuous and may include one or more gaps. In the example ofFIG. 3Athe ring-shaped metal structure11has one gap19. For example, the ring-shaped metal structure11may extend along more than 50% or 60% or 70% or 80% or 90% of the contour12.

The distance d1between the ring-shaped metal structure11and the adjacent edge of the semiconductor chip10may be in the range from 1 to 200 μm and may be, in one embodiment, smaller than 150 μm. The lateral width d2of the ring-shaped metal structure11may be in the range from 10 to 300 μm and in one embodiment may be smaller than 100 μm. The distance d3of the ring-shaped metal structure11reaching into the chip body may be more than 0.5 μm and in one embodiment more than 5 μm or even more than 10 μm. It may be provided that the ring-shaped metal structure11surrounds some or all of the contact pads20.

The inner structure of the ring-shaped metal structure11is illustrated on the right hand side ofFIG. 3A. The ring-shaped metal structure11may be fabricated when the semiconductor chip10is still in the wafer bond, i.e. before the wafer is diced to produce the individual semiconductor chips. The semiconductor chip10contains a semiconductor substrate21, for example a silicon or gallium arsenide substrate, and a number of metal layers22stacked over the semiconductor substrate21. Between adjacent metal layers22dielectric layers23, for example silicon nitride or silicon oxide layers, are arranged. In the area of the ring-shaped metal structure11, vias24may connect adjacent metal layers22so that the top metal layer22of the ring-shaped metal structure11is coupled to the semiconductor substrate21. The metal layers22and the vias24may be made of a metal or a metal alloy, for example copper, aluminum or gold. The top metal layer23may not be covered with the dielectric material23thus forming an exposed surface25of the ring-shaped metal structure11. Apart form forming the ring-shaped metal structure11, the metal layers22may be used to electrically interconnect the electrical components integrated into the semiconductor substrate21.

The semiconductor chip10may further include a seal ring26, which usually encloses all components of the semiconductor chip10. Thus the seal ring26also encloses (surrounds) the ring-shaped metal structure11. The inner structure of the seal ring26may be similar to the structure of the ring-shaped metal structure11illustrated on the right hand side ofFIG. 3A, but the seal ring26may not have an exposed top surface. The seal ring26may be arranged between the ring-shaped metal structure11and the side surfaces of the semiconductor chip10. The function of the seal ring26may be to protect the integrated circuits of a semiconductor wafer when dividing the semiconductor wafer into separated semiconductor chips. Before dividing the semiconductor wafer, a scribing line is formed between any two adjacent semiconductor chips to facilitate the dicing of the semiconductor wafer. The stress generated during the scribing and dicing may cause damage to the integrated circuits. Therefore, a seal ring is normally formed between the semiconductor chips and the scribing line to prevent the integrated circuits from being damaged during the scribing and dicing process.

The semiconductor chip10may contain an integrated circuit for the transmission and/or reception of radio signals. The semiconductor chip10may, for example, be an millimeter wave integrated circuit (MMIC), which includes a signal generator producing signals having frequencies in the range from 1 to 300 GHz and thus have wavelengths in the millimeter range. A MMIC may be used for automotive radar tracking, for example adaptive cruise control (ACC) systems.

In order to manufacture the device300, a carrier30is provided as illustrated inFIG. 3B. The carrier30may be a plate made of a rigid material, for example a metal, such as nickel, steel or stainless steel, laminate, film or a material stack. The carrier30may have at least one flat surface on which components of the device300can be placed. The shape of the carrier30is not limited to any geometric shape, for example the carrier30may be round or square-shaped. The carrier30may have any appropriate size.

An adhesive tape31, for example a double sided sticky tape, may be laminated onto a surface of the carrier30as illustrated inFIG. 3C. The surface of the carrier30on which the adhesive tape31is laminated is the surface where the components of the device300are placed later on.

As illustrated inFIG. 3D, the semiconductor chips10and17as well as possibly further semiconductor chips are placed over the carrier30(only the semiconductor chips10and17are illustrated inFIG. 3D). The semiconductor chips10and17may be arranged over the carrier30with their first main surfaces13facing the carrier30. The semiconductor chips10and17can be fixed on the adhesive tape31. For attaching the semiconductor chips10and17to the carrier30, other kinds of attaching materials may in one embodiment be used. The semiconductor chips10and17and the further semiconductor chips may be arranged in an array.

The semiconductor chips10and17are relocated on the carrier30in larger spacing as they have been in the wafer bond. The semiconductor chips10and17may have been manufactured on the same semiconductor wafer, but may in one embodiment have been manufactured on different wafers. Furthermore, the semiconductor chips10and17may be physically identical, but may also contain different integrated circuits and/or represent other components. Before the semiconductor chips10and17are placed on the carrier30, they may be thinned, for example by grinding their backsides, down to a thickness in the range from 30 to 300 μm. The function and dimensions of the semiconductor chip10may be different from the function and dimensions of the semiconductor chip17, however both semiconductor chips10and17may also have the same functions and dimensions. For example, the semiconductor chips10and17may be MMICs.

After the semiconductor chips10and17have been mounted on the carrier30, they are encapsulated by an electrically insulating encapsulation material14thereby forming a layer of the electrically insulating material14as illustrated inFIG. 3E. For example, the encapsulation material14may be a duroplastic or thermosetting mold material. The gaps between the semiconductor chips10and17are also filled with the mold material14so that the mold material14covers the side surfaces of the semiconductor chips10and17. The mold material14may be based on an epoxy material and may contain a filling material consisting of small particles of glass (SiO2) or other electrically insulating mineral filler materials like Al2O3or organic filler materials.

As an alternative to the mold material, another polymer material may be used as the electrically insulating material14to encapsulate the semiconductor chips10and17. The polymer material14may have the shape of an electrically insulating foil or sheet, which is laminated on top of the semiconductor chips10and17as well as the carrier30. Heat and pressure may be applied for a time suitable to attach the polymer foil or sheet14to the underlying structure. The gaps between the semiconductor chips10and17are also filled with the polymer material14. The polymer material14may, for example, be a prepreg (short for preimpregnated fibers) that is a combination of a fiber mat, for example glass or carbon fibers, and a resin, for example a duroplastic material. Prepreg materials are usually used to manufacture PCBs (printed circuit boards). Well known prepreg materials that are used in PCB industry and that can be used here as the polymer material14are: FR-2, FR-3, FR-4, FR-5, FR-6, G-10, CEM-1, CEM-2, CEM-3, CEM-4 and CEM-5. Prepreg materials are bi-stage materials, which are flexible when applied over the semiconductor chips10and17and hardened during a heat-treatment. For the lamination of the prepreg the same or similar processes can be used as in PCB manufacturing.

The semiconductor chips10and17covered with the electrically insulating material14are released from the carrier30, and the adhesive tape31is pealed from the semiconductor chips10and17as well as from the encapsulation material14as illustrated inFIG. 3F. The adhesive tape31may feature thermo-release properties, which allow the removal of the adhesive tape31during a heat-treatment. The removal of the adhesive tape31from the carrier30is carried out at an appropriate temperature, which depends on the thermo-release properties of the adhesive tape31.

After the release of the carrier30and the adhesive tape31the first main surfaces13of the semiconductor chips10and17as well as the bottom surface of the encapsulation material14, which is the second main surface15, form a common planar surface, i.e. the first main surfaces13and the second main surface15are coplanar. In one embodiment, the surfaces13and15may be plane-parallel. As described in the following, a redistribution layer may be applied to the main surfaces13and15.

A dielectric layer32may be deposited on the main surfaces13and15as illustrated inFIG. 3G. The dielectric layer32may be fabricated in various ways. For example, the dielectric layer32may be deposited from a gas phase or from a solution, or can be laminated onto the main surfaces13and15. Furthermore, thin-film technology methods or a standard PCB industry process flow can be used for the application of the dielectric layer32. The dielectric layer32may be fabricated from a polymer, such as parylene, photoresist material, imide, epoxy, duroplast, silicone, silicon nitride or an inorganic, ceramic-like material, such as silicone-carbon compounds. The thickness of the dielectric layer32may be up to 10 μm or even higher.

In order to make electrical contacts to the integrated circuits and the ring-shaped metal structure11embedded in the semiconductor chips10and17, the dielectric layer32may be opened in areas where the contact pads20are arranged as illustrated inFIG. 3G. Furthermore, the dielectric layer32may be removed from at least portions of the top surface25of the ring-shaped metal structure11. The openings33in the dielectric layer32may, for example, be produced by using photolithographic methods and/or etching methods.

The dielectric layer32may also be omitted. In cases where electrodes, in one embodiment back side electrodes, of the semiconductor chips10and17reach to the side surfaces of the semiconductor chips10and17, the dielectric layer32may prevent short circuits with metal layers of the redistribution layer. Furthermore, conductor tracks may cross the ring-shaped metal structure11as described further below. In this case, the dielectric layer32isolates these conductor tracks from the ring-shaped metal layer11.

A metal layer18is placed over the dielectric layer32as illustrated inFIG. 3H. The metal layer18also covers the contact pads20and the portions of the ring-shaped metal structure11exposed by the openings33in the dielectric layer32. The metal layer18may have a thickness, which may be smaller than 300 nm. The metal layer18may be deposited by using, for example, sputtering, electroless deposition, evaporation or any other appropriate technique. Sputtering is a process whereby small particles, for example atoms, are ejected from a solid target material due to bombardment of the target by energetic particles, for example ions. Electroless deposition (also known as electroless or chemical or auto-catalytic or non-galvanic plating) involves the deposition of metal particles from a solution onto a surface without the use of external electrical power. That means that the solution containing the metal particles is applied to the surface to be coated with the metal, and the metal particles then adhere to the surface without the need of applying an external voltage to the solution and the surface. Evaporation involves evaporating a source material in a vacuum. The vacuum allows vapor particles to travel directly to the surface to be covered where the vapor particles condense back to a solid state.

According to one embodiment, the metal layer18may be composed of two thin metal layers stacked on each other. First a layer of titanium, titanium tungsten, chromium or any other suitable metal or metal alloy may be deposited on the top surfaces of the dielectric layer32, the exposed contact pads20and the exposed portions of the ring-shaped metal structure11. In one embodiment this layer may have a thickness smaller than 100 nm and in one embodiment about 50 nm. The function of the this layer may be to promote the adhesion of further metal layers and to prevent the diffusion of metal particles into the semiconductor chips10and17. A further metal layer, for example a copper layer, may be deposited on the adhesion promoter/diffusion barrier layer. In one embodiment this layer may have a thickness smaller than 200 nm and in one embodiment about 150 nm. The function of this layer may be to provide sufficient electrical conductivity to act as a seed layer for galvanic deposition later on. The adhesion promoter/diffusion barrier layer as well as the seed layer may be deposited by using sputtering, electroless deposition, evaporation or any other appropriate technique.

A plating resist layer35, for example a photoresist layer, may be spin-coated on top of the metal layer18. By exposure to light having a suitable wavelength through a mask and subsequent development, the plating resist layer35is selectively removed as illustrated inFIG. 3I. Instead of spin-coating, exposure to light and development, the plating resist layer35may also be deposited by using printing techniques.

Subsequently, the parts of the metal layer18, which are not covered with the plating resist layer35, may be reinforced by galvanic deposition of a further metal layer36as illustrated inFIG. 3J. During the galvanic deposition of the metal layer36, the metal layer18is employed as an electrode. Copper or other metals or metal alloys may be plated onto the metal layer18in the unmasked areas and to the desired height, which may be larger than 2 μm or 3 μm or 4 μm or 5 μm or 6 μm or 7 μm or 8 μm or 9 μm or 10 μm. Furthermore, another metal layer, for example a nickel layer, may be galvanically plated on top of the metal layer36to avoid the consumption of copper of the metal layer36by solder deposits which may be applied to the redistribution layer later on.

After the plating of the metal layer36the plating resist layer35is stripped away by using an appropriate solvent as illustrated inFIG. 3K. The now exposed parts of the metal layer18, which are not covered with the metal layer36, may be removed by one or more etching processes thereby creating a structured metal layer consisting of the metal layers18and36as illustrated inFIG. 3L.

A dielectric layer38may be deposited on top of the metal layer36and may be opened in areas where external contact pads16are arranged as illustrated inFIG. 3M. The dielectric layer38may be produced and structured by using the same or similar materials and processes as described above in connection with the dielectric layer32. The external contact pads16allow to electrically contact the contact pads20and the ring-shaped metal structure11of the semiconductor chips10and17from outside the devices300.

Solder deposits39may be placed onto the external contact pads16as illustrated inFIG. 3N. The solder deposits39may be applied to the external contact pads16by “ball placement”, in which pre-shaped balls composed of solder material are applied to the external contact pads16. As an alternative to “ball placement”, the solder deposits39may, for example, be applied by using stencil printing with a solder paste, followed by a heat-treatment process. The solder material may be formed from metal alloys which are composed, for example, from the following materials: SnPb, SnAg, SnAgCu, SnAgCuNi, SnAu, SnCu and SnBi. The solder deposits39may be used to electrically couple the devices300to other components, for example a PCB (printed circuit board).

As illustrated inFIG. 30, the devices300(and the semiconductor chips10and17) are separated from one another by removing parts of the redistribution layer and the encapsulation material14, for example by sawing, cutting, milling, etching or a laser beam.

The devices300manufactured by the method described above are fan-out type packages. The encapsulation material14allows the redistribution layer to extend beyond the contour12of the semiconductor chips10and17. The external contact pads16and the solder deposits39therefore do not need to be arranged within the contour12of the semiconductor chips10or17but can be distributed over a larger area. The increased area which is available for arrangement of the external contact pads16as a result of the encapsulation material14means that the external contact pads16cannot only be arranged at a great distance from one another, but that the maximum number of external contact pads16which can be arranged there is likewise increased compared to the situation when all the external contact pads16are arranged within the contour12of the semiconductor chip10and17. Furthermore, due to the encapsulation body14surrounding the semiconductor chips10and17the external contact pads16do not need to be placed over the semiconductor chips10and17itself. In case the semiconductor chips10and17contain integrated circuits generating high frequencies, for example MMICs generating frequencies in the range from 1 to 300 GHz, placing the external contact pads16over these circuits may lead to resonance phenomena and may impact the function of the semiconductor chips10and17.

FIG. 3Pillustrates a plan view of the device300. In this embodiment, the solder deposits39depicted on the left and right hand sides ofFIG. 3Pare electrically coupled to the ring-shaped metal layer11via conductor lines formed of the metal layers18and36. The metallic connection between the semiconductor substrate21of the semiconductor chip10and the solder deposits39(see alsoFIG. 3A) allows to transfer the heat generated by the integrated circuits in the semiconductor substrate21to the solder deposits39and the circuit board, to which the device300is mounted during operation, which dissipate the heat generated by the semiconductor chip10. The more solder deposits39are thermally coupled to the ring-shaped metal structure11, the more effective the semiconductor chip10is cooled. It may be provided that the solder deposits39which are electrically coupled to the ring-shaped metal structure11are coupled to ground or mass potential at the circuit board.

The solder deposits39depicted at the top and bottom ofFIG. 3Pare electrically coupled to the contact pads20of the semiconductor chip10via conductor lines formed of the metal layers18and36. It may be provided that the conductor lines used for low frequency signals (lower than 1 MHz) may cross the ring-shaped metal structure11and may be electrically insulated from the ring-shaped metal structure11by the dielectric layer32(see solder deposits39depicted at the top ofFIG. 3P). In the case of high frequency signals, for example in the range from 1 to 300 GHz, resonance phenomena may occur if the conductor lines transmitting these signals cross the ring-shaped metal structure11. For this reason, these conductor lines are passed through the gap19in the ring-shaped metal structure11(see solder deposits39depicted at the bottom ofFIG. 3P).

It is obvious to a person skilled in the art that the device300and the manufacturing thereof as described above are only intended to be an embodiment, and many variations are possible. For example, further semiconductor chips or passives may be included in the same device300. The semiconductor chips and passives may differ in function, size, manufacturing technology etc. Moreover, the redistribution layer of the device300may include further metal layers stacked on top of each other. These metal layers may be insulated from each other by dielectric layers.

InFIG. 4a device400is schematically illustrated in plan view. The device400is similar to the device300, but includes more solder deposits39which are electrically and thermally coupled to the ring-shaped metal structure11of the semiconductor chip10. In the present embodiment, ten solder deposits39are coupled to the ring-shaped metal structure11. The device400includes a plurality of contact pads20arranged in an array. Some of the contact pads20are electrically coupled to the solder deposits39via the metal layers18and36. The ring-shaped metal structure11of the device400has three gaps19. Conductor lines transmitting signals having frequencies higher than 1 GHz may pass through the gaps19. Conductor lines transmitting signals having smaller frequencies may cross the ring-shaped metal structure11.

FIG. 5schematically illustrates a system500in cross section. The system500includes a circuit board50, such as a PCB, and the device300mounted on the circuit board50. The solder balls of the device300are soldered to contact pads51of the circuit board50. The heat generated by the semiconductor chip10is removed by heat conduction to the circuit board50by the solder balls connected to the ring-shaped metal structure11within the semiconductor chip10. The thermal resistance of the solder balls depend strongly on their position relative to the semiconductor chip10and on their metallic connection to the ring-shaped metal layer11. For a simplified discussion,FIG. 5illustrates three different types of solder balls52,53and54. The heat transfer to the solder balls52and53located directly beneath the semiconductor chip10is fairly good. For the solder ball52, which is connected to the semiconductor chip10in the shortest possible way, the thermal resistance is smaller than 100 K/W. For the solder ball53, which is connected to the semiconductor chip10via the metal layers18and36, the thermal resistance is smaller than 250 K/W. The thermal resistance of the connection between the semiconductor chip10and the solder ball54, which is located outside the contour12of the semiconductor chip10, is smaller than 400 K/W. Solder balls lying further away from the semiconductor chip10than the solder ball54have only very little contribution to the total heat flow. Therefore, most of the solder balls54arranged in the first row outside the contour12of the semiconductor chip10are used for heat dissipation. For example, at least 50% of the solder balls54arranged in the first row outside the contour12may be electrically coupled to the ring-shaped metal structure11. These solder balls54may be connected in the shortest possible way to the semiconductor substrate21of the semiconductor chip10. In order to provide good heat transfer, the ring-shaped metal structure11may include a densely packed metal stack.

FIG. 6illustrates a model to calculate the thermal resistance RCONTACTfor the heat transfer from the semiconductor substrate21of the semiconductor chip10to the circuit board. The thermal resistance RCONTACTis composed of the thermal resistance RVIA1of the ring-shaped metal structure11, the thermal resistance RVIA2of the via in the redistribution layer, the thermal resistance RRDLof the lateral conductor line of the redistribution layer and the thermal resistance RBALLof the solder ball:
RCONTACT=RVIA1+RVIA2+RRDL+RBALL(1)

FIG. 7illustrates a model to calculate the thermal resistance RSIfor the heat transfer from the integrated circuit within the silicon substrate21generating the heat to the periphery of the silicon substrate21where the ring-shaped metal structure11is located. In the present model the silicon substrate21is cylindrical with a height d and a radius r2. The heat is generated in the middle portion of the silicon substrate21having a radius r1. The thermal resistance Rsiis calculated as follows:
RSI=ln(r2/r1)/(2πλSId)   (2)

In the case of d=450 μm, r1=100 μm, r2=1 mm and λ=148 mK/W, the thermal resistance RSIis 5.5 K/W. In the case of d=450 μm, r1=500 μm and r2=2 mm, the thermal resistance RSIis 3.3 K/W. The thermal resistance RSIusually amounts to less than 10 K/W and contributes only little to the thermal resistance RCONTACT.