STACKED PACKAGE DESIGN FOR MORE RELIABLE FIBER COUPLING TO PHOTONIC INTEGRATED CIRCUIT

In one embodiment, an integrated circuit package includes a first (top) package substrate, a photonics integrated circuit (PIC) die coupled to the first package substrate, and a second package substrate coupled to a bottom side of the first package substrate. The package further includes a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond an edge of the first package substrate at which the PIC die is located.

BACKGROUND

Photonic integrated circuits (PIC) rely on die-edge coupling to couple waveguides of the PIC to external optical fibers, e.g., those in fiber array units (FAUs). The optical fibers may be bonded to the die edge of the PIC by optical epoxy in many cases. However, the bonding area between the fiber and the die edge of the PIC is very small, and the bonding force may not be strong and/or reliable enough to support the optical fiber under stress or strain that can be experienced in real world implementations. Thus, without external hardware, optical fiber connections may be very insecure.

DETAILED DESCRIPTION

Embodiments herein provide a stacked package design for more reliable fiber coupling to photonic integrated circuit (PIC) chips of the package. In typical package designs, the package only includes a single package substrate. Current techniques for addressing the insecure nature of fiber connections to PICS include providing a support structure between the bottom of the fiber and the side of the package substrate, where the PIC edge is aligned with the edge of the package substrate. However, this may provide relatively little support to the fiber as the substrate thickness and the size of the supporting structure are both small. Further, the weight of the supporting structure can affect the bonding between the fiber and the PIC, since the additional weight can pull downward on the fiber, stressing the epoxy bond between the fiber and the PIC. In some cases, a different, mechanical epoxy may be used to bond the support structure to the edge of the package substrate than the optical epoxy used to bond the fiber and the PIC, and the proximity of the support structure (and thus, the mechanical epoxy) can cause one or both of the epoxies to spill over and contaminate the other.

Other techniques include providing a small cavity in a top area the package substrate near the PIC and using the remaining package substrate portion below the cavity to support the fiber. However, implementation of these small cavities within the top area of the package substrate can be expensive and complicated. Further, there is limited vertical area allowed by such cavities, allowing for less vertical adjustability when attaching fiber to the PIC.

In embodiments herein, a stacked package design is implemented to provide better support for attached fiber. The stacked package design includes a first (top) package substrate to which integrated circuit dies may be coupled, as in traditional integrated circuit package designs, as well as a second (bottom) package substrate below the top package substrate. The bottom package substrate includes an additional area that extends beyond the edge of the top package substrate at which the PICs are located, and the additional area of the bottom package substrate below the area at which optical fiber attaches to the PIC includes one or more mechanisms for supporting the attached fiber (e.g., fiber array units (FAUs)).

This type of design can provide better support to the attached fiber while also reducing production and implementations costs as well. For instance, the bottom package substrate can be designed with a small number of layers and/or with just vias to connect the top package substrate to the main circuit board, allowing for reduced production costs. Moreover, the two substrate design can allow for increased rigidity for supporting attached fiber, and can provide increased vertical adjustability for the fiber attachment that previous techniques have not allowed for.

FIG.1illustrates an example stacked integrated circuit package100in accordance with certain embodiments. The example package100includes a main circuit board100with stacked package substrates102,104thereon, with a top package substrate104being on top of a second (bottom) package substrate102, which is coupled to the circuit board101. The top package substrate104has integrated circuit dies coupled to it, which, in the example shown, includes a processor106and electronic integrated circuit (EIC) dies108coupled to the top of the substrate104, and photonic integrated circuit (PIC) dies110located at an outer edge of the package substrate104. In the example shown, the PIC dies110are embedded within the top surface of the substrate104(which may be referred to as an “open cavity PIC” in certain instances). The XPU106and EICs108are interconnected via bridge circuitries105, and pairs of EICs108and PICs110are directly connected to one another as shown. In certain embodiments, the PICs110may have a thickness of approximately 50-200 μm and the FAUs112may have a thickness of approximately 1-2 mm.

The bottom package substrate102includes circuitry to interconnect the top package substrate104and the circuit board101. In some embodiments, the bottom package substrate102may be implemented with a minimal number of layers or components to reduce costs. For example, the substrate102may be implemented as an interposer with vias/pillars that directly connect pads of the top substrate104to pads of the circuit board101, e.g., as shown. In other embodiments, the bottom substrate102may include more complicated interconnect circuitries than just vias/pillars, e.g., may include redistribution layers, and/or may have other integrated circuit dies (not shown) coupled thereto. For example, the substrate102may be implemented as a Package on Interposer architecture that includes multiple routing layers and/or fan-out routing of traces.

As shown, the bottom package substrate102includes an additional area103that extends beyond the edge of the top package substrate104at whierrch the PICs110are located (on the right ofFIG.1). The additional area103has support mechanisms for mechanically supporting the fiber array units (FAUs)112coupled to the PICs110(which are coupled together via optical epoxy111as shown). The example support mechanisms shown include a first pedestal120coupled to the top of the bottom substrate102that extends across both FAUs112to support each FAU as shown, with a respective epoxy122laid across the top of each FAU112to couple each to the first pedestal120. The support mechanisms also include a second pedestal124that is coupled to the substrate102via a mechanical epoxy126. In contrast to the first pedestal120, there is a second pedestal124for each respective FAU112, and the second pedestal124for each FAU112is not adhesively coupled to the FAU112(e.g., by epoxy) like the first pedestal120, which is adhesively coupled to each FAU112by the epoxy122.

The first and second pedestals may be formed using any suitable material. In some embodiments, this may include a material with a high temperature tolerance, e.g., glass, plastics, or metals that can tolerate temperatures of approximately 250° C. (which may be seen, e.g., during a solder reflow process), and thus, can better tolerate manufacturing processes such as substrate and/or die attachment processes. In some embodiments, the first and second pedestal may be formed from different materials. For example, the first pedestal120may be formed from a material with a higher force tolerance than the second pedestals124, since the forces experienced by the FAUs112at the first pedestal location (i.e., further away from the attachment point with the PICs110) may be higher than at the second pedestal location.

Although two types of pedestals are shown inFIG.1, embodiments herein may implement only one of the pedestals shown. For example, an embodiment may only include a single pedestal implemented similar to the pedestal120with overlaid epoxy122, while another embodiment may include a single pedestal implemented similar to the pedestal124with no adhesive coupling to the FAUs112. Moreover, aspects of each support mechanism shown may be combined with one another, or may be implemented in other ways than shown. For example, in some embodiments, a pedestal implemented similar to the second pedestal124may be adhesively coupled to the FAUs112using an epoxy in a similar manner as the first pedestal120is coupled to the FAUs using the epoxy122, or a pedestal implemented similar to the first pedestal120may be implemented without the epoxy overlaid across the FAUs112.

The support mechanisms shown may be attached to or formed on the bottom substrate102at any suitable time during the manufacturing process. In some embodiments, the support mechanisms may be attached to/formed on the bottom substrate102prior to the top substrate104being attached to the bottom substrate (which may be prior to both being attached to the circuit board101). In other embodiments, the support mechanisms may be attached to/formed on the bottom substrate102after the top substrate104has been attached, but prior to the FAUs112being connected to the PICs110.

The package substrates102,104may include circuitry to connect the integrated circuit dies of the package (e.g.,106,108,110) to the main circuit board101(which may be, e.g., a motherboard or main board of a computing system) and/or to interconnect the dies with one another. For example, the package substrates102,104may include connections for signaling between the main circuit board101and the integrated circuit dies of the package, as well as connections for providing power delivery from the main circuit board101(e.g., from a power supply coupled to the main circuit board) to the dies.

The bridge circuitries105may be implemented, in certain instances, as dies embedded within the package substrate104. However, other embodiments may implement the bridge circuitries105as circuitry within upper layers of the package substrate104. The bridge circuitries105may include any suitable passive and/or active circuitry to interconnect the XPU106with the EIC108. An example implementation of the bridge circuitries105is an Intel® Embedded Multi-Die Interconnect Bridge (EMIB) die.

The XPU106may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units.

The PICs110may include circuitry to receive optical signals from a source (e.g., attached fiber), convert the optical signals to electrical signals, and provide the electrical signals to other circuitry (e.g., to the EIC and/or the XPU). Likewise, the PICs may include circuitry to receive electrical signals (e.g., from the EIC and/or the XPU), generate optical signals based on the electrical signals, and provide the optical signals to the fiber. The PICs may include one or more lasers or other light sources, detectors, amplitude and/or phase modulators, filters, splitters, amplifiers, interferometers, micro ring resonators (MRR), gratings, squeezed or other quantum light sources, etc. The PIC circuitry may perform other functions beyond converting optical signals to electrical signals or vice versa, e.g., matrix multiplication, quantum logic gates, optical compute gates, etc. The EICs108may include circuitry to control and/or drive the circuitry within the PIC coupled thereto, and/or other electrical circuitry for processing the signals from the PIC. For instance, the EICs may include components such as, for example, transimpedance amplifiers (TIA), serializer/deserializer (SERDES) circuits, driver circuits, etc. The optical signals may be received from an array of fiber, e.g., FAUs112, which may be implemented as a fiber pigtail connection, that is coupled to the PIC, e.g., via optical epoxy111as shown.

FIG.2illustrates another example stacked integrated circuit package200in accordance with certain embodiments. The example package200is implemented in the same manner as the package100ofFIG.1, but with different support mechanisms. That is, the circuit board201is implemented in the same manner as the circuit board101, the substrate202is implemented in the same manner as the substrate102, the substrate204is implemented in a similar manner as the substrate104(albeit with a different form as described below), the bridge circuitries205are implemented in the same manner as the bridge circuitries105, the XPU206is implemented in the same manner as the XPU106, the EICs208are implemented in the same manner as the EICs108, the PICs210are implemented in the same manner as the PICs110, and the FAUs212are implemented in the same manner as the FAUs112.

However, in the example shown, the substrate202is implemented generally with the same dimensions as the substrate204, but the substrate204includes a cutout region203as shown, in which the fiber support mechanisms of the package200are located. The support mechanisms of the package200include a first pedestal220and second pedestals224similar to the package100. However, the first pedestal220is not adhesively coupled to the FAUs212as in the example shown inFIG.1, while the second pedestals224are adhesively coupled to the FAUs212using an epoxy226as shown. The pedestals220,224may be implemented using the same types of materials or in the same manner as described above with respect to pedestals120,124. Further, as in the example above, although two types of pedestals are shown, embodiments herein may implement only one of the pedestals shown. For example, an embodiment may only include a single pedestal implemented similar to the pedestal220with no adhesive coupling to the FAUs212, while another embodiment may include a single pedestal implemented similar to the pedestal224with adhesive coupling to the FAUs212. Moreover, aspects of each support mechanism shown may be combined with one another or may be implemented in other ways than shown.

FIG.3illustrates another example stacked integrated circuit package300in accordance with certain embodiments. The example package300is implemented in the same manner as the packages100,200described above, but does not include a pedestal for supporting the FAUs312. Rather, the FAUs312are coupled directly to the substrate302using an epoxy326as shown. The circuit board301is implemented in the same manner as the circuit boards101and201, the substrate302is implemented in the same manner as the substrates102and202, the substrate304is implemented in a similar manner as the substrate204, the bridge circuitries305are implemented in the same manner as the bridge circuitries105and205, the XPU306is implemented in the same manner as the XPUs106and206, the EICs308are implemented in the same manner as the EICs108and208, the PICs310are implemented in the same manner as the PICs110and210, and the FAUs312are implemented in the same manner as the FAUs112and212.

Although the examples described above include two PIC dies at a single (right or “east”) edge of an upper substrate (e.g.,104,204,304), embodiments of the present disclosure may include any number of PIC dies and the PIC dies may be located at any edge of the upper substrate, including one or more PIC dies at each outer edge of the upper substrate. For example, some embodiments may include three PIC dies coupled (e.g., through EIC dies) to each of four different sides of an XPU (e.g.,106,206,306), i.e., with 12 total PIC dies coupled to respective EIC dies, which are in turn coupled to a central XPU. Moreover, although the example PIC dies in the examples above are implemented “open cavity” designs, embodiments of the present disclosure may include PIC dies that are coupled to the upper substrate in another manner. Finally, the examples shown in each ofFIGS.1-3may not be drawn to scale, i.e., embodiments of the present disclosure may include components having proportions that differ from those shown or differ with respect to other components shown. For example, the proportions of the example FAUs and PIC dies with respect to one another may differ from those shown inFIGS.1-3.

FIG.4is a top view of a wafer400and dies402that may be implemented in or along with any of the embodiments disclosed herein. The wafer400may be composed of semiconductor material and may include one or more dies402having integrated circuit structures formed on a surface of the wafer400. The individual dies402may be a repeating unit of an integrated circuit product that includes any suitable integrated circuit. After the fabrication of the semiconductor product is complete, the wafer400may undergo a singulation process in which the dies402are separated from one another to provide discrete “chips” of the integrated circuit product. The die402may include one or more transistors (e.g., some of the transistors640ofFIG.6, discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and/or any other integrated circuit components. In some embodiments, the wafer400or the die402may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die402. For example, a memory array formed by multiple memory devices may be formed on a same die402as a processor unit (e.g., the processor unit702ofFIG.7) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG.5is a cross-sectional side view of an integrated circuit device assembly500that may include any of the embodiments disclosed herein. The integrated circuit device assembly500includes a number of components disposed on a circuit board502(which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly500includes components disposed on a first face540of the circuit board502and an opposing second face542of the circuit board502; generally, components may be disposed on one or both faces540and542.

In some embodiments, the circuit board502may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board502. In other embodiments, the circuit board502may be a non-PCB substrate. The integrated circuit device assembly500illustrated inFIG.5includes a package-on-interposer structure536coupled to the first face540of the circuit board502by coupling components516. The coupling components516may electrically and mechanically couple the package-on-interposer structure536to the circuit board502, and may include solder balls (as shown inFIG.5), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure536may include an integrated circuit component520coupled to an interposer504by coupling components518. The coupling components518may take any suitable form for the application, such as the forms discussed above with reference to the coupling components516. Although a single integrated circuit component520is shown inFIG.5, multiple integrated circuit components may be coupled to the interposer504; indeed, additional interposers may be coupled to the interposer504. The interposer504may provide an intervening substrate used to bridge the circuit board502and the integrated circuit component520.

The integrated circuit component520may be a packaged or unpacked integrated circuit product that includes one or more integrated circuit dies (e.g., the die402ofFIG.4, the integrated circuit device600ofFIG.6) and/or one or more other suitable components. A packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate with the integrated circuit dies and package substrate encapsulated in a casing material, such as a metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component520, a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer504. The integrated circuit component520can comprise one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I/O controller, memory, or network interface controller. In some embodiments, the integrated circuit component520can comprise one or more additional active or passive devices such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

In embodiments where the integrated circuit component520comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).

In addition to comprising one or more processor units, the integrated circuit component520can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.

Generally, the interposer504may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer504may couple the integrated circuit component520to a set of ball grid array (BGA) conductive contacts of the coupling components516for coupling to the circuit board502. In the embodiment illustrated inFIG.5, the integrated circuit component520and the circuit board502are attached to opposing sides of the interposer504; in other embodiments, the integrated circuit component520and the circuit board502may be attached to a same side of the interposer504. In some embodiments, three or more components may be interconnected by way of the interposer504.

In some embodiments, the interposer504may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer504may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer504may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer504may include metal interconnects508and vias510, including but not limited to through hole vias510-1(that extend from a first face550of the interposer504to a second face554of the interposer504), blind vias510-2(that extend from the first or second faces550or554of the interposer504to an internal metal layer), and buried vias510-3(that connect internal metal layers).

In some embodiments, the interposer504can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer504comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer504to an opposing second face of the interposer504.

The interposer504may further include embedded devices514, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer504. The package-on-interposer structure536may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board

The integrated circuit device assembly500may include an integrated circuit component524coupled to the first face540of the circuit board502by coupling components522. The coupling components522may take the form of any of the embodiments discussed above with reference to the coupling components516, and the integrated circuit component524may take the form of any of the embodiments discussed above with reference to the integrated circuit component520.

The integrated circuit device assembly500illustrated inFIG.5includes a package-on-package structure534coupled to the second face542of the circuit board502by coupling components528. The package-on-package structure534may include an integrated circuit component526and an integrated circuit component532coupled together by coupling components530such that the integrated circuit component526is disposed between the circuit board502and the integrated circuit component532. The coupling components528and530may take the form of any of the embodiments of the coupling components516discussed above, and the integrated circuit components526and532may take the form of any of the embodiments of the integrated circuit component520discussed above. The package-on-package structure534may be configured in accordance with any of the package-on-package structures known in the art.

FIG.6is a cross-sectional side view of an integrated circuit device600that may be included in any of the embodiments disclosed herein. One or more of the integrated circuit devices600may be included in one or more dies402(FIG.4). The integrated circuit device600may be formed on a die substrate602(e.g., the wafer400ofFIG.4) and may be included in a die (e.g., the die402ofFIG.4). The die substrate602may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The die substrate602may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate602may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the die substrate602. Although a few examples of materials from which the die substrate602may be formed are described here, any material that may serve as a foundation for an integrated circuit device600may be used. The die substrate602may be part of a singulated die (e.g., the dies402ofFIG.4) or a wafer (e.g., the wafer400ofFIG.4).

The integrated circuit device600may include one or more device layers604disposed on the die substrate602. The device layer604may include features of one or more transistors640(e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate602. The transistors640may include, for example, one or more source and/or drain (S/D) regions620, a gate622to control current flow between the S/D regions620, and one or more S/D contacts624to route electrical signals to/from the S/D regions620. The transistors640may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors640are not limited to the type and configuration depicted inFIG.6and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon, nanosheet, or nanowire transistors.

Returning toFIG.6, a transistor640may include a gate622formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material.

The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor640is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

The S/D regions620may be formed within the die substrate602adjacent to the gate622of individual transistors640. The S/D regions620may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate602to form the S/D regions620. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate602may follow the ion-implantation process. In the latter process, the die substrate602may first be etched to form recesses at the locations of the S/D regions620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions620. In some implementations, the S/D regions620may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions620may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions620.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors640) of the device layer604through one or more interconnect layers disposed on the device layer604(illustrated inFIG.6as interconnect layers606-610). For example, electrically conductive features of the device layer604(e.g., the gate622and the S/D contacts624) may be electrically coupled with the interconnect structures628of the interconnect layers606-610. The one or more interconnect layers606-610may form a metallization stack (also referred to as an “ILD stack”)619of the integrated circuit device600.

The interconnect structures628may be arranged within the interconnect layers606-610to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures628depicted inFIG.6. Although a particular number of interconnect layers606-610is depicted inFIG.6, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures628may include lines628aand/or vias628bfilled with an electrically conductive material such as a metal. The lines628amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate602upon which the device layer604is formed. For example, the lines628amay route electrical signals in a direction in and out of the page and/or in a direction across the page from the perspective ofFIG.6. The vias628bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate602upon which the device layer604is formed. In some embodiments, the vias628bmay electrically couple lines628aof different interconnect layers606-610together.

The interconnect layers606-610may include a dielectric material626disposed between the interconnect structures628, as shown inFIG.6. In some embodiments, dielectric material626disposed between the interconnect structures628in different ones of the interconnect layers606-610may have different compositions; in other embodiments, the composition of the dielectric material626between different interconnect layers606-610may be the same. The device layer604may include a dielectric material626disposed between the transistors640and a bottom layer of the metallization stack as well. The dielectric material626included in the device layer604may have a different composition than the dielectric material626included in the interconnect layers606-610; in other embodiments, the composition of the dielectric material626in the device layer604may be the same as a dielectric material626included in any one of the interconnect layers606-610.

A first interconnect layer606(referred to as Metal1or “M1”) may be formed directly on the device layer604. In some embodiments, the first interconnect layer606may include lines628aand/or vias628b, as shown. The lines628aof the first interconnect layer606may be coupled with contacts (e.g., the S/D contacts624) of the device layer604. The vias628bof the first interconnect layer606may be coupled with the lines628aof a second interconnect layer608.

The second interconnect layer608(referred to as Metal2or “M2”) may be formed directly on the first interconnect layer606. In some embodiments, the second interconnect layer608may include via628bto couple the interconnect structures628of the second interconnect layer608with the lines628aof a third interconnect layer610. Although the lines628aand the vias628bare structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines628aand the vias628bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

The third interconnect layer610(referred to as Metal3or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer608according to similar techniques and configurations described in connection with the second interconnect layer608or the first interconnect layer606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack619in the integrated circuit device600(i.e., farther away from the device layer604) may be thicker that the interconnect layers that are lower in the metallization stack619, with lines628aand vias628bin the higher interconnect layers being thicker than those in the lower interconnect layers.

The integrated circuit device600may include a solder resist material634(e.g., polyimide or similar material) and one or more conductive contacts636formed on the interconnect layers606-610. InFIG.6, the conductive contacts636are illustrated as taking the form of bond pads. The conductive contacts636may be electrically coupled with the interconnect structures628and configured to route the electrical signals of the transistor(s)640to external devices. For example, solder bonds may be formed on the one or more conductive contacts636to mechanically and/or electrically couple an integrated circuit die including the integrated circuit device600with another component (e.g., a printed circuit board or a package substrate, e.g.,112). The integrated circuit device600may include additional or alternate structures to route the electrical signals from the interconnect layers606-610; for example, the conductive contacts636may include other analogous features (e.g., posts) that route the electrical signals to external components.

In some embodiments in which the integrated circuit device600is a double-sided die, the integrated circuit device600may include another metallization stack (not shown) on the opposite side of the device layer(s)604. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers606-610, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s)604and additional conductive contacts (not shown) on the opposite side of the integrated circuit device600from the conductive contacts636.

In other embodiments in which the integrated circuit device600is a double-sided die, the integrated circuit device600may include one or more through silicon vias (TSVs) through the die substrate602; these TSVs may make contact with the device layer(s)604, and may provide conductive pathways between the device layer(s)604and additional conductive contacts (not shown) on the opposite side of the integrated circuit device600from the conductive contacts636. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device600from the conductive contacts636to the transistors640and any other components integrated into the integrated circuit device600, and the metallization stack619can be used to route I/O signals from the conductive contacts636to transistors640and any other components integrated into the integrated circuit device600.

Multiple integrated circuit devices600may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).

FIG.7is a block diagram of an example electrical device700that may include one or more of the embodiments disclosed herein. For example, any suitable ones of the components of the electrical device700may include one or more of integrated circuit devices600, or integrated circuit dies402disclosed herein. A number of components are illustrated inFIG.7as included in the electrical device700, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device700may be attached to one or more motherboards mainboards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the electrical device700may not include one or more of the components illustrated inFIG.7, but the electrical device700may include interface circuitry for coupling to the one or more components. For example, the electrical device700may not include a display device706, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device706may be coupled. In another set of examples, the electrical device700may not include an audio input device724or an audio output device708, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device724or audio output device708may be coupled.

The electrical device700may include a memory704, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory704may include memory that is located on the same integrated circuit die as the processor unit702. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (LA), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, the electrical device700can comprise one or more processor units702that are heterogeneous or asymmetric to another processor unit702in the electrical device700. There can be a variety of differences between the processing units702in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units702in the electrical device700.

In some embodiments, the electrical device700may include a communication component712(e.g., one or more communication components). For example, the communication component712can manage wireless communications for the transfer of data to and from the electrical device700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

In some embodiments, the communication component712may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component712may include multiple communication components. For instance, a first communication component712may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component712may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component712may be dedicated to wireless communications, and a second communication component712may be dedicated to wired communications.

The electrical device700may include battery/power circuitry714. The battery/power circuitry714may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device700to an energy source separate from the electrical device700(e.g., AC line power).

The electrical device700may include a display device706(or corresponding interface circuitry, as discussed above). The display device706may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device700may include an audio output device708(or corresponding interface circuitry, as discussed above). The audio output device708may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.

The electrical device700may include an audio input device724(or corresponding interface circuitry, as discussed above). The audio input device724may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device700may include a Global Navigation Satellite System (GNSS) device718(or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device718may be in communication with a satellite-based system and may determine a geolocation of the electrical device700based on information received from one or more GNSS satellites, as known in the art.

The electrical device700may include another output device710(or corresponding interface circuitry, as discussed above). Examples of the other output device710may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The electrical device700may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device700may be any other electronic device that processes data. In some embodiments, the electrical device700may comprise multiple discrete physical components. Given the range of devices that the electrical device700can be manifested as in various embodiments, in some embodiments, the electrical device700can be referred to as a computing device or a computing system.

Illustrative examples of the technologies described throughout this disclosure are provided below. Embodiments of these technologies may include any one or more, and any combination of, the examples described below. In some embodiments, at least one of the systems or components set forth in one or more of the preceding figures may be configured to perform one or more operations, techniques, processes, and/or methods as set forth in the following examples.

Example 1 is an integrated circuit package comprising: a first package substrate; a photonics integrated circuit (PIC) die coupled to the first package substrate at an edge of the first package substrate; a second package substrate coupled to a bottom side of the first package substrate; and a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the PIC die is located.

Example 2 includes the subject matter of Example 1, wherein the pedestal is a first pedestal, and the integrated circuit package further comprises a second pedestal coupled to the top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the PIC die is located.

Example 3 includes the subject matter of Example 2, wherein the first pedestal and second pedestal comprise different materials.

Example 4 includes the subject matter of any one of Examples 1-3, wherein the pedestal comprises glass or metal.

Example 5 includes the subject matter of any one of Examples 1-4, wherein the first package substrate comprises a cutout region and the PIC die is located at an edge defining cutout region.

Example 6 includes the subject matter of any one of Examples 1-5, wherein the PIC die is within a cavity in a top side of the first package substrate.

Example 7 includes the subject matter of any one of Examples 1-6, further comprising an electronic integrated circuit (EIC) die coupled to the first package substrate and connected to the PIC die.

Example 8 includes the subject matter of any one of Examples 1-7, further comprising a processor coupled to the first package substrate and connected to the EIC die.

Example 9 includes the subject matter of any one of Examples 1-8, wherein the second package substrate comprises vias connected between electrical connection pads on a top side of the second package substrate and electrical connection pads on a bottom side of the second package substrate.

Example 10 includes the subject matter of any one of Examples 1-9, wherein the second package substrate comprises one or more of redistribution layer traces and fan-out traces.

Example 11 is a system comprising: an integrated circuit package comprising: a first package substrate; a photonics integrated circuit (PIC) die coupled to the first package substrate at an edge of the first package substrate; a second package substrate coupled to a bottom side of the first package substrate; and a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the PIC die is located; and optical fiber coupled to the PIC and on a top surface of the pedestal.

Example 12 includes the subject matter of Example 11, wherein the optical fiber is adhesively coupled to the pedestal.

Example 13 includes the subject matter of Example 11 or 12, wherein the pedestal is a first pedestal, and the system further comprises a second pedestal coupled to the top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the PIC die is located, and wherein the optical fiber is further on a top surface of the second pedestal.

Example 14 includes the subject matter of Example 13, wherein the first pedestal and second pedestal comprise different materials.

Example 15 includes the subject matter of any one of Examples 11-14, wherein the pedestal comprises glass or metal.

Example 16 includes the subject matter of any one of Examples 11-15, wherein the first package substrate comprises a cutout region and the PIC die is located at an edge defining cutout region.

Example 17 includes the subject matter of any one of Examples 11-16, wherein the PIC die is within a cavity in a top side of the first package substrate.

Example 18 includes the subject matter of any one of Examples 11-17, further comprising an electronic integrated circuit (EIC) die coupled to the first package substrate and connected to the PIC die.

Example 19 includes the subject matter of any one of Examples 11-18, further comprising a processor coupled to the first package substrate and connected to the EIC die.

Example 20 includes the subject matter of any one of Examples 11-19, wherein the second package substrate comprises vias connected between electrical connection pads on a top side of the second package substrate and electrical connection pads on a bottom side of the second package substrate.

Example 21 includes the subject matter of any one of Examples 11-20, wherein the second package substrate comprises one or more of redistribution layer traces and fan-out traces.

Example 22 includes the subject matter of any one of Examples 11-21, further comprising a circuit board, wherein the second package is coupled to a top side of the circuit board.

Example 23 is a system comprising: a circuit board; an integrated circuit package coupled to the circuit board, the integrated circuit package comprising: a first package substrate; a first photonics integrated circuit (PIC) die coupled to the first package substrate at an edge of the first package substrate; a first electronic integrated circuit (EIC) die coupled to the first package substrate and connected to the PIC die; a second PIC die coupled to the first package substrate at the edge of the first package substrate; a second EIC die coupled to the first package substrate and connected to the PIC die; a processor coupled to the first EIC die and the second EIC die; a second package substrate coupled to a top side of the circuit board and to a bottom side of the first package substrate; and a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the first PIC die and second PIC die are located; a first fiber array unit (FAU) coupled to the first PIC and on a top surface of the pedestal; and a second FAU coupled to the second PIC and on the top surface of the pedestal.

Example 24 includes the subject matter of Example 23, wherein the pedestal is a first pedestal, the system further comprises a second pedestal coupled to the top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the first PIC die and second PIC die are located, and wherein one of the first FAU or the second FAU are on a top surface of the second pedestal.

Example 25 includes the subject matter of Example 24, wherein the first pedestal and second pedestal comprise different materials.

Example 26 includes the subject matter of Example 24, further comprising a third pedestal coupled to the top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the first PIC die and second PIC die are located, wherein the first FAU is on the top surface of the second pedestal and the second FAU is on a top surface of the third pedestal.

Example 27 includes the subject matter of any one of Examples 23-26, wherein the pedestal comprises glass or metal.

Example 28 includes the subject matter of any one of Examples 23-27, wherein the first package substrate comprises a cutout region and the first PIC die and second PIC die are located at an edge defining cutout region.

Example 29 includes the subject matter of any one of Examples 23-28, wherein the first PIC die is within a first cavity in a top side of the first package substrate and the second PIC die is within a second cavity in the top side of the first package substrate.

Example 30 includes the subject matter of any one of Examples 23-29, wherein the second package substrate comprises vias connected between electrical connection pads on a top side of the second package substrate and electrical connection pads on a bottom side of the second package substrate.

Example 31 includes the subject matter of any one of Examples 23-30, wherein the second package substrate comprises one or more of redistribution layer traces and fan-out traces.

In the above description, various aspects of the illustrative implementations have been described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations have been set forth to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without all of the specific details. In other instances, well-known features have been omitted or simplified in order not to obscure the illustrative implementations.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). Additionally, it should be appreciated that items included in a list in the form of “at least one of A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact. Further, “adjacent” may refer to layers or components that are in physical contact with each other. That is, there is no layer or component between the stated adjacent layers or components. For example, a layer X that is adjacent to a layer Y refers to a layer that is in physical contact with layer Y.

In various embodiments, the phrase “a first feature formed, deposited, or otherwise disposed on a second feature” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature. Further, “located on” in the context of a first layer or component located on a second layer or component may refer to the first layer or component being directly physically attached to the second part or component (no layers or components between the first and second layers or components) or physically attached to the second layer or component with one or more intervening layers or components.