Method of expanding 3D device architectural designs for enhanced performance

Aspects of the present disclosure provide a vertical channel 3D semiconductor device sand a method for fabricating the same. The 3D semiconductor devices may have vertical channels of the same or different epitaxially grown doped materials. Sidewall structures are formed around each vertical channel by masking and etching material between the vertical channels. A dielectric layer in each of the sidewalls is etched down to the vertical channel and a gate electrode structure is formed in the opening. The gate electrode structure may include an interfacial oxide, a high-K layer and alternating metal layers. Local interconnects connect to the metal of the gate structure.

FIELD OF THE INVENTION

This disclosure relates to microelectronic devices including vertical channel semiconductor devices, transistors, and integrated circuits, including methods of microfabrication.

BACKGROUND

In the manufacture of a semiconductor device (especially on the microscopic scale), various fabrication processes are executed such as film-forming depositions, etch mask creation, patterning, material etching and removal, and doping treatments. These processes are performed repeatedly to form desired semiconductor device elements on a substrate.

Historically, with microfabrication, transistors have been created in one plane, with wiring/metallization formed above the active device plane, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes. Semiconductor device fabricators have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of one another.

3D integration, i.e. the vertical stacking of multiple devices, aims to overcome scaling limitations experienced in planar devices by increasing transistor density in volume rather than area. Although device stacking has been successfully demonstrated and implemented by the flash memory industry with the adoption of 3D NAND, application to random logic designs is substantially more difficult. 3D integration for logic chips (CPU (central processing unit), GPU (graphics processing unit), FPGA (field programmable gate array, SoC (System on a chip)) is desired.

Accordingly, it is one object of the present disclosure to provide methods and devices for vertical transistors which can be stacked on top of one another.

SUMMARY

Techniques herein include methods of microfabrication of 3D devices that expand 3D device architectural designs for enhanced performance, and that enable higher density circuits to be produced at reduced cost. Vertical 3D epitaxial growth for vertical transistors allows current flow in a vertical dimension or perpendicular to wafer surface. Methods and designs herein include making CMOS devices with upright current flow. Vertical 3D devices herein enable another degree of freedom in the z-direction that will augment existing 3D devices for layout options. Having relatively short transistor lengths is achieved because channel length is defined by a deposited layer or epitaxially grown layer. Precise alignment with gate electrodes is achieved by selective removal of intermediate dielectric layers. Techniques herein eliminate a need for oxide isolation of a 3D nano stack.

A first embodiment describes a method of microfabrication, comprising: forming a stack of dielectric layers on a first layer of semiconductor material, the stack of dielectric layers having at least three layers in which a first dielectric material is positioned below and above a second dielectric material, the first dielectric material being different from the second dielectric material in that the second dielectric material can be removed without removing the first dielectric material; forming openings in the stack of dielectric layers such that the first layer of semiconductor material is uncovered; epitaxially growing channel material within uncovered openings to form vertical channels; removing a portion of the stack of dielectric layers such that sidewall structures remain on the vertical channels; removing the second dielectric material from the sidewall structures such that sidewall surfaces of the vertical channels are uncovered; and forming a gate structure on uncovered sidewall surfaces of the vertical channels.

A second embodiment describes a semiconductor device, comprising: a substrate layer; a first layer of a first dielectric material; a first layer of semiconductor material; a stack of dielectric layers having at least three layers in which the first dielectric material is positioned below and above a second dielectric material, the first dielectric material being different from the second dielectric material in that the second dielectric material can be removed without removing the first dielectric material; first openings in the stack of dielectric layers in which the first layer of semiconductor material is uncovered; vertical channels having epitaxially grown doped material in the first openings; sidewall structures formed by second openings in the stack of dielectric layers between the vertical channels; third openings in the sidewall structures formed by removal of the second dielectric material to the vertical channel; gate structures in the third openings; and local interconnects connected to the gate structure of each vertical channel, the vertical channels configured to conduct current perpendicular to a working surface of the substrate.

DETAILED DESCRIPTION

Techniques herein include methods of microfabrication of 3D devices that expand 3D device architectural designs for enhanced performance, and that enable higher density circuits to be produced at reduced cost. Vertical 3D epitaxial growth for vertical transistors allows current flow in a vertical dimension or perpendicular to wafer surface. Methods and designs herein include making CMOS devices with upright current flow. Vertical 3D devices herein enable another degree of freedom in the z-direction that will augment existing 3D devices for layout options. Having relatively short transistor lengths is achieved because channel length is defined by a deposited layer or epitaxially grown layer. Precise alignment with gate electrodes is achieved by selective removal of intermediate dielectric layers. Techniques herein eliminate a need for oxide isolation of a 3D nano stack. Vertical transistor can have unlimited W with GAA devices with particular substrate conditions.

Because the gate electrode and source regions have 360 degree access, a contact may be placed at any side of the source or any side of the gate. The source and drain may be interchanged because each channel can be isolated from other channels. 360 degree access is a significant benefit with the device architecture for maximum layout connections and routing. Given channel regions can be centered on the S/D epitaxial region or offset for maximum layout efficiency depending on circuit requirements. Vertical 3D structures provide accessible (360 degree contact and routing access to channel, source and drain) thereby increasing circuit density.

Example embodiments here will describe several flows referencing the drawings.FIGS.1A-1Lillustrate a single vertical single crystal (or large grain boundary) NMOS gate-all-around (GAA) device using a substrate containing silicon/oxide/silicon stack for an NFET device.FIGS.2A-2Lillustrate single vertical single crystal (or large grain boundary) PMOS gate-all-around (GAA) device using a substrate containing silicon/oxide/silicon stack for a PFET device.FIGS.3A-3Villustrate CMOS formation with dual epitaxial growth using single crystal GAA devices (NMOS and PMOS) side-by-side.

Referring now toFIG.1A, a substrate102is prepared with a layer stack. This can included alternating layers of a first dielectric104and a second dielectric108. Dielectrics are selected to be etch selective to each other. Dielectrics may be SiN, silicon oxide, silicon dioxide, silicon carbide, or the like. For example, a given isotropic or vapor phase etch can etch one dielectric without etching (substantially etching) the other dielectric. In one example embodiment, the first dielectric104is silicon dioxide while the second dielectric108is a high-K dielectric. High-K dielectrics may be Al2O3, AlN, ZrO2, HfO2, HfSiOx, ZrSiOx, HfOxNy, ZrOxNy, HfxZryOz, Ta2O5, La2O3, Y2O3, Nb2O5, TiO2, Pr2O3, Gd2O3, SiBN, BCN, hydrogenated boron carbide, or the like

In this stack, on the bulk substrate102material, oxide is deposited, then a layer of semiconductor material106is deposited on the oxide. This can be silicon or germanium or other N+ semiconductor material. It can be deposited as amorphous and then crystallized by bake or laser anneal. This layer can be formed with N+ dopants or implanted with N+ dopants. The N+ dopants can be, for example, arsenic or phosphorous, among others. Above this semiconductor layer, a dielectric layer stack is formed of alternating layers. The dielectric layer stack at least includes a first dielectric104isolating a second dielectric108. Subsequently this will enable uncovering a channel while maintaining spacing from source/drain regions.

InFIG.1B, a photoresist110is used to form an etch mask on the layer stack. A photoresist is a light-sensitive material used in photolithography to form a patterned coating on a surface. This etch mask defines openings to form in the layer stack. This opening can be circular, square/rectangular or other channel cross-sectional shape. A directional/anisotropic etch is executed using this etch mask to remove uncovered portions140of the layer stack until reaching and uncovering the layer of semiconductor material106. The masking layer(s)110can then be removed.

With the N+ material uncovered within openings, N+ channel material112can be grown by epitaxial growth as shown inFIG.1C. Because the deposited channel length is defined by physical deposition, channel lengths herein can be as short as 10 Angstroms. For channel lengths considered relatively short, these lengths can be approximately 20 A to 100 A. As can be appreciated, channel lengths in the 10s or 100s of nanometers are also contemplated. The longer lengths can provide relaxed scaling dimensions.

InFIG.1D, a second etch mask of photoresist110is formed to define sidewall structures around the epitaxially grown vertical channels112. An etch is executed leaving sidewall structures on the vertical channels. The sidewall structures have a particular thickness and keep the alternating dielectric layer stack, essentially surrounding the vertical channel. This etch defines a future gate electrode region.

InFIG.1E, the existing photoresist110fromFIG.1Dis removed and a new pattern of photoresist110is applied to etch through the N+ silicon layer to isolate each device with opening131. This isolates each device for maximum circuit applications. This step is optional. In other embodiments, the photoresist mask110for defining sidewall structures ofFIG.1Dcan also be used to isolate N+ silicon.

FIG.1F, the photoresist110has been removed and a third dielectric114is grown or selectively deposited on open substrate regions and N+ regions. The third dielectric114should be etch selective to the second dielectric108. Non-limiting examples of dielectric materials that are selective to each other are SixOy, SixNy, and SiOxNy, high-K, and (high-K) OxNy.

InFIG.1G, the second dielectric108is removed without removing the first dielectric or the third dielectric. This uncovers future gate electrode regions.

InFIG.1H, any sacrificial oxide or interface oxide growth can be removed or cleaned followed by deposition of a selective high-K layer116.

InFIG.1I, a selective high-K anneal step can be executed. Interfacial oxide growth118can be formed between the high-K layer and the vertical channel.

InFIG.1J, a metal gate electrode stack120can be formed/deposited on the substrate. This can be one layer or multiple layers to adjust the voltage threshold (Vt) of the transistor device. This can be a conformal deposition.

InFIG.1K, a directional etch is executed to remove gate stack material120from the substrate, leaving gate stack materials surrounding the vertical channel, thereby forming a GAA device. Processing can then continue such as by forming local interconnects or other connections (not shown). Additional vertical channel GAA devices can be formed on top of the layer of devices to repeat the fabrication process (not shown).

FIG.1Lis a perspective view of a device formed by the process ofFIG.1A-1K.FIG.1Lshows the first layer of semiconductor material106, a layer of dielectric104, the metal gate electrode stack120, a layer of dielectric104and the N+ epitaxial vertical channel112. Metal connections132,134and136are attached to the first layer106, the N+ epitaxial vertical channel112and the metal gate electrode stack120respectively.

FIGS.2A-2Kshow a similar flow for formation of PFET devices. Processing flow is similar except that a P-doped silicon or germanium layer122can be formed instead of an N-doped layer. Otherwise, masking, sidewall structure formation, and gate electrode formation are similar.

InFIG.2A, on the bulk substrate202material, a dielectric oxide204is deposited, then a layer of semiconductor material222is deposited on the oxide. It can be deposited as amorphous and then crystallized by bake or laser anneal. This layer can be formed with P+ dopants or implanted with P+ dopants. The P+ dopants can be boron, gallium, indium or other P+ semiconductor material. Above this semiconductor layer, a dielectric layer stack is formed of alternating layers. The dielectric layer stack at least includes top and bottom layers of dielectric oxide204isolating a second dielectric208.

InFIG.2B, photoresist210is patterned on top layer204to define openings to etch channel regions242. These openings may be rectangular or cylindrical.

InFIG.2C, with the P+ material uncovered within openings, P+ channel material224can be epitaxially grown.

FIG.2D, photoresist210is patterned over the P+ material and to define sidewall structures around the epitaxially grown vertical channels224. An etch is executed leaving sidewall structures on the vertical channels. The sidewall structures have a particular thickness and keep the alternating dielectric layer stack, essentially surrounding the vertical channel. This etch defines a future gate electrode region.

InFIG.2E, the existing photoresist210fromFIG.2Dis removed and a new pattern of photoresist210is applied to etch through the P+ silicon layer to isolate each device at opening231. This isolates each device for maximum circuit applications. This step is optional. In other embodiments, the photoresist mask210for defining the sidewall structures ofFIG.2Dcan also be used to isolate the P+ silicon.

InFIG.2F, the photoresist210ofFIG.2Ehas been removed and a third dielectric214is grown or selectively deposited on open substrate regions and P+ regions. The third dielectric214should be etch selective to the second dielectric208.

InFIG.2G, the second dielectric208is removed without removing the top and bottom layers of dielectric oxide204or the third dielectric214. This uncovers future gate electrode regions.

InFIG.2H, any sacrificial oxide or interface oxide growth can be removed or cleaned from the future electrode regions followed by deposition of a selective high-K layer216in the gate region on the vertical channel material224between the layers of the first dielectric304.

InFIG.2I, a selective high-K anneal step can be executed. Interfacial oxide growth218can be formed between the high-K layer and the vertical channel.

InFIG.2J, a metal gate electrode stack220can be formed/deposited on the substrate. This can be one layer or multiple layers to adjust the voltage threshold (Vt) of the transistor device. This can be a conformal deposition.

InFIG.2K, a directional etch is executed to remove metal gate electrode stack220from the substrate, top and sides, leaving only gate electrode stack materials within and surrounding the vertical channel, thereby forming a GAA device. Processing can then continue such as by forming local interconnects, LI (MO), Metal 1 or other connections (not shown). Additional vertical channel GAA devices can be formed on top of the layer of devices to repeat the fabrication process (not shown).

FIG.2Lis a perspective view of a device formed by the process ofFIG.2A-2K.FIG.2Lshows the first layer of semiconductor material222, a layer of dielectric204, the metal gate electrode stack220, a layer of dielectric204and the P+ epitaxial vertical channel224. Metal connections232,234and236are attached to the first layer222, the N+ epitaxial vertical channel224and the metal gate electrode stack220respectively.

FIGS.3A-3Tillustrate a process flow for formation of side-by-side vertical channel PFET and NFET devices.

InFIG.3A, the processing flow starts with a substrate of single-crystal silicon305on dielectric layer304on silicon302. A photomask of photoresist310can be formed to define areas for N+ implantation doping (phosphorous, arsenic . . . ) or plasma doping to form N+ layer306.

InFIG.3B, the photomask310ofFIG.3Ais removed and a second mask of photoresist310covers N+ layer306to define areas for P+ dopant (e.g. BF2, B, . . . ) to form P+ layer322. Although the N+ layer is shown on the left inFIG.3Aand the P+ layer is shown on the right inFIG.3B, in other aspects the dopant areas can be reversed so that P+ is on the right and N+ is on the left.

FIG.3Cshows that doped semiconductor regions can optionally be separated and isolated at this point in the process flow. In this alternative, a photoresist pattern can be formed over the structure with an opening followed by an etch down to the dielectric layer304.

InFIG.3D, annealing of implants can be followed by depositing alternating layers304,308,304, similar to previous flow. In a non-limiting example, dielectric layer304may be oxide and dielectric108may be a high-K dielectric.

InFIG.3E, photoresist310can be patterned to provide regions in the dielectric layer stack which are etched down to the doped layer (either N+ or P+) to define openings342for vertical channels. These openings can be circular, square or rectangular. In a non-limiting example, the openings can be 10 nm in diameter and have heights of 5-50 angstroms.

InFIG.3F, a third dielectric314can be grown or selectively deposited in substrate regions defined by openings342. This can prevent epi growth in selective regions in subsequent process steps. The third dielectric314should be etch selective to the second dielectric308.

InFIG.3G, the PMOS regions (right stack) are masked, and the dielectric314is removed from NMOS regions (left stack).

InFIG.3H, N+ channel regions312are epitaxially grown while PMOS regions are protected from epitaxial growth by third dielectric314.

InFIG.3I, the photoresist310is removed and a protection film326is deposited on the substrate, such as a conformal nitride to cover N+ epi regions.

InFIG.3J, the protection film326is removed in the PMOS regions.

InFIG.3K, P+ vertical channel material324is epitaxially grown. The P+ dopants can be boron, gallium, indium or other P+ semiconductor material. The remaining nitride is removed. At this point, both N+ and P+ vertical channels are completed.

InFIG.3L, a photoresist mask310is patterned over the NMOS and PMOS regions and the dielectric layer stack is etched to form sidewall structures around the vertical channels.

FIG.3Mshows growth or selective deposition of the third dielectric314on open substrate regions and N+ and P+ regions. Dielectric314should be etch selective to the second dielectric308.

InFIG.3O, a sacrificial oxide or interface oxide growth (not shown) can be removed followed by pre-clean followed by selective high-K deposition316. An anneal step can be executed. Interfacial oxide growth318can be formed between the high-K deposit316and the vertical channel.

InFIG.3P, a metal gate electrode stack can be formed/deposited on the substrate. This can be one layer or multiple layers to adjust drive current of the transistor device. This can be a conformal deposition. The metal gate stack can be layers of titanium nitride (TiN) and tantalum nitride (TaN) gate metal328followed by a layer of titanium aluminide (TiAl) gate metal330.

InFIG.3Q, a directional etch is executed to remove gate stack material from the substrate, leaving gate stack materials (316,318,328,330) surrounding the vertical channel, thereby forming a GAA device.

FIG.3Rshows that PMOS regions can be masked with photoresist310while TiAL (or other gate stack material) is removed for customization of gate stacks. For example, this can enable NMOS and PMOS to have a similar threshold voltage, Vt, in absolute value.

FIG.3Sshows the substrate cross-section with the different gate stacks after the removal of the metal gate material328. The completed NMOS stack gate electrode region is shown as340.

InFIG.3T, a photoresist mask310can be formed on the substrate to etch separations331in the doped silicon layer to isolate the lower source/drain regions.

FIG.3Ushows the device with the photoresist mask310ofFIG.3Tremoved. A dielectric326is deposited and a chemical/mechanical polish/cross sectional polish is performed. The NMOS gate stack340and the PMOS gate stack342are shown.

FIG.3Vshows a perspective view of the side-by-side NMOS (on the left) and PMOS (on the right) stacks with metal connections. The NMOS stack has a gate electrode336N connected to NMOS stack gate electrode region and electrodes332N and334N for source/drain connections. The PMOS stack has a gate electrode336P connected to gate stack material330and electrodes332P and334P for source/drain connections.

The dielectric layer may be dielectric oxide or may be a low-K dielectric that has a K value less than SiO2(K=3.9), since metal routing will be done in these layers. Some non-limiting examples of low-K dielectrics are shown in Table 1:

Processing can then continue such as by forming local interconnects or other connections (not shown).

Additional vertical channel GAA devices (not shown) can be formed on top of the layer of devices to repeat the fabrication process. Furthermore, the source, drain and gate regions can be connected with conductive connections, for example, local interconnects and interconnects to metal levels. In one example, a buried power rail (power rail positioned below the channels) can be incorporated, wherein metal hookups can be obtained from either the top surfaces of the PMOS and NMOS transistors, or by using local interconnects.

Embodiments of the present disclosure may also be as set forth in the following parentheticals.

(1) A method of microfabrication, comprising: forming a stack of dielectric layers on a first layer of semiconductor material, the stack of dielectric layers having at least three layers in which a first dielectric material is positioned below and above a second dielectric material, the first dielectric material being different from the second dielectric material in that the second dielectric material can be removed without removing the first dielectric material; forming openings in the stack of dielectric layers such that the first layer of semiconductor material is uncovered; epitaxially growing channel material within uncovered openings to form vertical channels; removing a portion of the stack of dielectric layers such that sidewall structures remain on the vertical channels; removing the second dielectric material from the sidewall structures such that sidewall surfaces of the vertical channels are uncovered; and forming a gate structure on uncovered sidewall surfaces of the vertical channels.

(2) The method of (1), wherein the first layer of semiconductor material is N-doped silicon or N-doped germanium.

(3) The method of (1), wherein the first layer of semiconductor material is P-doped silicon or P-doped germanium.

(4) The method of (1), wherein the first layer of semiconductor material includes a P-doped region adjacent to an N-doped region, wherein N-doped vertical channels are grown in first uncovered openings over the N-doped region, and wherein P-doped vertical channels are grown in second uncovered openings over the P-doped region.

(5) The method of (4), further comprising: depositing a third dielectric on the first layer of the first and second uncovered openings; masking the P-doped region of the first layer with a first photoresist mask; removing the third dielectric from the N-doped region of the first layer; epitaxially growing N+ doped material over the N-doped region; removing the first photoresist mask; depositing a protection film over the stack of dielectric layers, the N+ doped material and the third dielectric; removing the protection film from the third dielectric; and epitaxially growing P+ doped material in the second uncovered opening over the third dielectric.

(6) The method of any one of (1) to (5), further comprising forming local interconnects that connect to the gate structure of each vertical channel, the vertical channels configured to conduct current perpendicular to a working surface of the first layer of semiconductor material.

(7) The method of any one of (1) to (6), further comprising removing portions of the first layer of semiconductor material between the vertical channels.

(8) The method of any one of (1) to (7), wherein the openings formed in the stack of dielectric layers have a circular or rectangular cross section.

(9) The method of any one of (1) to (8), wherein the first layer of semiconductor material is formed on an underlying dielectric layer.

(10) The method of any one of (1) to (9), wherein removing a portion of the stack of dielectric layers comprises: masking the vertical channels and a top of a sidewall region surrounding each vertical channel; and etching through the stack of dielectric layers down to the first layer of semiconductor material.

(11) The method of any one of (1) to (10), further comprising: forming the first layer of semiconductor material on an underlying dielectric layer; masking the stack of dielectric layers; and separating the stack by etching a portion of the stack down to the underlying dielectric layer prior to forming openings in the stack such that the first layer of semiconductor material is uncovered.

(12) The method of any one of (1) to (11), further comprising forming the gate structure by: depositing a selective high-K material within the uncovered sidewall surfaces of the vertical channels, annealing; forming interfacial oxide between the selective high-K material and the vertical channels; depositing a metal gate electrode stack on the vertical channels, sidewall surfaces and the selective high-K material; and removing the metal gate electrode stack from the vertical channels and sidewall surfaces.

(13) The method of any one of (1) to (12), wherein depositing a metal gate electrode stack comprises: depositing a first metal material on the selective high-K material; depositing a second metal material on the first metal material; and depositing a third metal material on the second metal material.

(14) The method of (13), wherein the first, second and third metal materials are different metals.

(15) The method of any one of (13) to (14), wherein the first metal material is titanium nitride, the second metal material is tantalum nitride and the third metal material is titanium aluminide.

(16) The method of any one of (13) to (15), wherein depositing a metal gate electrode stack comprises: depositing a first layer of a first metal material on the high-K material; depositing a second layer of a second metal material on the first layer of metal material; depositing a third layer of the first metal material on the second layer of the second metal material; depositing a fourth layer of the second metal material on the third layer of the first metal material; and depositing a third metal material on the fourth layer of the second metal material.

(17) A semiconductor device, comprising: a substrate layer; a layer of a first dielectric material; a layer of semiconductor material; a stack of dielectric layers having at least three layers in which the first dielectric material is positioned below and above a second dielectric material, the first dielectric material being different from the second dielectric material in that the second dielectric material can be removed without removing the first dielectric material; first openings in the stack of dielectric layers in which the layer of semiconductor material is uncovered; vertical channels having epitaxially grown doped material in the first openings; sidewall structures formed by second openings in the stack of dielectric layers between the vertical channels; third openings in the sidewall structures formed by removal of the second dielectric material to the vertical channel; gate structures in the third openings; and local interconnects connected to the gate structure of each vertical channel, the vertical channels configured to conduct current perpendicular to a working surface of the substrate layer.

(18) The semiconductor device of (17), wherein the first layer of semiconductor material is N-doped silicon or N-doped germanium.

(19) The semiconductor device of (17), wherein the first layer of semiconductor material is P-doped silicon or P-doped germanium.

(20) The semiconductor device of (17), wherein the first layer of semiconductor material includes a P-doped region adjacent to an N-doped region, wherein N-doped vertical channels are disposed in first uncovered openings over the N-doped region, and wherein P-doped vertical channels are disposed in second uncovered openings over the P-doped region.

Precise alignment with gate electrode is achieved with techniques herein. Vertical 3D epitaxial growth for vertical transistors enables current flow in the vertical dimension, which enables expansion of 3D device architectural designs. Vertical 3D structures provide readily accessible contacts (360 degree contact and routing access to channel, source and drain), thereby increasing circuit density. Embodiments and transistors herein can be stacked vertically for 3D devices. Embodiments enable the source and drain to be interchanged because each channel can be isolated from other channels.