USING INTERNAL ANALOG SENSORS IN THERMAL CONTROL LOOP FOR SUPERIOR TEMPERATURE CONTROL AND FASTER RESPONSE TO POWER TRANSIENTS

Methods and systems are provided for active thermal control (ATC) of an integrated circuit (IC) during a testing procedure. The methods and systems described herein involve obtaining a plurality of measurements of a die of the IC. The plurality of temperature measurements are provided by a plurality of temperature sensors integrated with the die. Each individual sensor can, for example, be integrated with an individual compute unit of a graphics processing unit (GPU) or with an individual core of a central processing unit (CPU). The methods and systems described herein further involve controlling, based on the plurality of temperature measurements, a temperature forcing system to implement ATC. Control of the temperature forcing system involves supplying heat to the IC when a temperature falls below a desired test temperature range and/or removing heat from the IC when a temperature exceeds the desired test temperature range.

BACKGROUND

One of the more challenging tasks in modern integrated circuit (IC) manufacturing is the necessity of testing ICs at an elevated temperature to ensure complete test coverage and thereby reduce the probability of future field failures. To accomplish this, the temperature of the IC must be continuously monitored during testing and compared against the desired test temperature. If the temperature of the IC falls below the desired test temperature, the testing process may be inadequate as it may fail to simulate sufficiently harsh conditions to ensure that the IC can withstand the rigors it will experience in the field. On the other hand, if the temperature of the IC exceeds the desired test temperature, the testing process can itself damage the IC, potentially limiting its lifespan or even causing immediate failure.

SUMMARY

Embodiments of the present disclosure relate to systems and methods for active thermal control (ATC) during testing of integrated circuits (ICs) for superior temperature control and faster response to power transients. In particular, systems and methods are disclosed herein that utilize internal analog sensors, e.g. analog temperature sensors integrated with individual compute units of an IC, to provide temperature measurements to an ATC system. The ATC system provides for control of a temperature forcing system to maintain the temperature of an IC circuit within a desired temperature range during the testing thereof.

DETAILED DESCRIPTION

Systems and methods are herein disclosed that relate to the use of internal analog sensors in active thermal control (ATC) during testing of integrated circuits (ICs) for superior temperature control and faster response to power transients. Systems and method are herein disclosed that provide for (i) rapid detection of temperature increases (of an IC or a region of an IC) following an increase in power supplied during testing and (ii) highly responsive control of a temperature forcing system to more accurately maintain a desired temperature range of the IC during testing.

To control the temperature of an integrated circuit (IC) during testing thereof, a process referred to as active thermal control (ATC) is implemented. ATC involves both (i) supplying heat from an external source to increase the temperature of the IC being tested, i.e. when the temperature of the IC falls below the desired testing temperature, and (ii) removing heat from the IC being tested, i.e. when the temperature of the IC exceeds the desired testing temperature. To ensure that an IC is comprehensively tested while simultaneously preventing the testing process from causing damage to the IC, the temperature of the IC is continuously compared against the desired testing temperature/temperature range and an ATC system responds to any deviation from such desired testing temperature/temperature range by supplying heat to or removing heat from the IC.

However, different parts of an IC can see different workloads—and therefore different temperatures—during the testing process. As ICs become larger and larger, temperature gradients between different parts of the IC during testing also become larger and larger. Large temperature gradients can be problematic to the testing process because they can result in the ATC system receiving temperature measurements that are either significantly higher or significantly lower than the actual temperature of certain portions of the IC. If the ATC system receives temperature measurements that are significantly higher than the actual temperature of a particular compute unit of an IC, then the ATC system may respond by removing heat from the IC in a manner that prevents that particular compute unit from experiencing the temperatures necessary for comprehensive testing. On the other hand, if the ATC system receives temperature measurements that are significantly lower than the actual temperature of a particular compute unit, then the ATC system may fail to remove heat from the IC before that particular compute unit is damaged.

During the process of testing an IC, the temperature measurements provided to the ATC system can be obtained from a variety of different sources. One option is to provide the ATC system with temperature measurements obtained from a thermocouple that is part of a thermal head of the ATC system. In such circumstances, the thermocouple contacts a case housing the IC. The case encapsulates the IC to provide mechanical protection and includes a number of electrical connections, such as leads or pins, for connecting the IC to external circuitry. Alternatively, the case can include a temperature sensor (e.g. a thermocouple), embedded therein or disposed thereon, for obtaining temperature measurements that can be provided to an ATC system. However, because such a temperature sensor is not in direct contact with either the IC substrate or die, any temperature measurement it provides will deviate from the actual temperature of the IC die and from the actual temperature of individual compute units contained in the IC die.

Some ICs include a single temperature sensor (e.g. a PN diode) located at the periphery of the IC die. Such a PN diode can obtain measurements which could be provided to the ATC system. However, while the temperature measurements provided by a PN diode located at a periphery of the IC die are more representative (as compared to a case or substrate temperature sensor) of the actual temperature of the IC die, such measurements will still continue to deviate from that actual temperature of the IC die because the PN diode is disposed on the periphery of the IC die while the power dissipating circuitry is in the inside of the IC die.

The present disclosure provides systems and methods that provide the ATC system with temperature measurements obtained from sensors integrated with (e.g. embedded inside) or disposed on or adjacent to individual compute units and/or cores that are contained in the IC die itself. In central processing units (CPUs), a plurality of cores are or can be provided that each includes its own set of arithmetic logic units (ALUs), registers, and other functional units necessary for performing calculations and executing instructions. In graphics processing units (GPUs), a plurality of different compute units can be provided that each execute compute tasks and work together to process large volumes of data in parallel. Each respective core/compute unit can also include its own temperature sensor configured to provide a measurement of the actual temperature of the respective core/compute unit. Temperature measurements obtained from temperature sensors integrated with individual cores/compute units are—compared to temperature sensors located in or on the case or substrate—more representative of the temperature experienced by the IC die during testing. The temperature measurements obtained from temperature sensors integrated with individual cores/compute units are also capable of accounting for temperature gradients between different cores/compute units.

A variety of different types of analog temperature sensors can be integrated with individual cores/compute units of an IC. Examples of such analog sensors include semiconductor-based temperature sensors, e.g., diode temperature sensors and bandgap temperature sensors, resistance temperature detectors (RTDs), and thermocouples. Diode temperature sensors utilize a temperature-dependent voltage drop across a forward-biased diode junction to measure temperature. Diode temperature sensors are relatively simple and inexpensive to implement, rendering them suitable for integration with cores/compute units of an IC. Bandgap temperature sensors utilize a temperature dependence of a bandgap voltage in semiconductor materials to measure temperature. Bandgap temperature sensors provide high accuracy and stability over a wide temperature range and are commonly used in precision temperature sensing applications. RTDs utilize a temperature-dependent resistor, e.g. a thermistor, whose resistance changes with temperature. RTDs are often made of materials such as platinum or nickel and offer high accuracy and linearity over a wide temperature range. One drawback of RTDs is that they typically require additional circuitry for signal conditioning and amplification. Thermocouples consist of two dissimilar conductors that generate a voltage proportional to the temperature difference between their junctions. While thermocouples offer temperature detection over a wide temperature range, they are less suitable for integration with cores/compute units of an IC due to their relatively low sensitivity and accuracy compared to semiconductor-based sensors.

Upon obtaining a temperature measurement representative of the temperature of the die of the IC during testing, the ATC system can compare the representative temperature to a desired testing temperature or to a desired testing temperature range. If the representative temperature of the die of the IC falls below the desired testing temperature or the desired testing temperature range, the ATC system can increase the temperature of the IC by supplying, from a heat source, additional heat to the IC. The heat source can be provided, e.g., by a thermal forcing system configured for use in system level testing (SLT) of ICs. On the other hand, if the representative temperature of the die of the IC exceeds the desired testing temperature or the desired testing temperature range, the ATC system can remove heat from the IC via a heat sink, e.g. of the thermal forcing system.

In the case of a large IC having a high number of cores/compute units, each of which includes an analog temperature sensor, a plurality of temperature measurements are available as possible inputs to the ATC system. Due to different parts of the IC experiencing different workloads during the testing process, the plurality of temperature measurements may exhibit a relatively large range of temperature values. Specifically, temperature measurements output by temperature sensors integrated with cores/compute units currently experiencing relatively high workloads will, in the absence of differential amounts of residual heat, specify temperature values that exceed those values specified by measurements from sensors integrated with cores/compute units currently experiencing relatively low workloads. Accordingly, the ATC system should be configured to adjust the amount of heat supplied to or removed from the IC based on a plurality of temperature measurement inputs that indicate disparate temperature values for the IC die.

As one example, the ATC system can determine a maximum temperature value indicated by the plurality of temperature measurements available as inputs (e.g. the plurality of temperature measurements obtained from the plurality of temperature sensors integrated with the plurality of cores/compute units), set such maximum temperature value as being equal to a representative temperature of the IC die, and control the supply of heat to and removal of heat from the IC based on that representative temperature of the IC die. By monitoring the maximum core/compute unit temperature measurement of the IC during testing and performing ATC based on that maximum temperature measurement, damage to any individual core/compute unit of the IC can be prevented by ensuring that heat will be removed from the IC in response to any individual core/compute unit exceeding a maximum value. As an alternative, the ATC system can determine an average of the temperature values provided by the plurality of temperature sensors integrated with the plurality of cores/compute units, set the average temperature as the representative temperature of the IC die, and control the supply of heat to and removal of heat from the IC based on that representative temperature.

The systems and methods of the present disclosure provide for rapid detection of temperature increases (of an IC or a region of an IC) following an increase in power supplied during IC testing. In particular, each of the plurality of temperature sensors integrated with an individual core/compute unit can supply a current temperature measurement on the order of every 50 to 100 ms. In particular, each temperature sensor can supply a current temperature measurement at a frequency in a range of 5 to 30 Hz, preferably at a frequency in a range of 10 to 20 Hz. Similarly, the ATC system can operate a feedback control loop at identical frequencies, i.e. in a range of 5 to 30 Hz, preferably in a range of 10 to 20 Hz. It has been found that providing current temperature measurements at such frequencies is well-suited to detecting IC temperature changes resulting from power transients common during IC testing and that controlling a temperature forcing system by operating a feedback control loop at such frequencies is well-suited to maintaining the temperature of an IC—as well as the temperature of individual cores/compute units of an IC—within a desired temperature range during IC testing.

In the systems and methods of the present disclosure, the individual temperature sensors can be configured to detect current temperatures of respective regions of an IC. In particular, the individual temperature sensors can be configured to detect current temperatures of an IC die region having an area of 10-50 mm2, preferably to detect current temperatures of an IC die region having an area of 15-25 mm2. It has been found that providing individual temperature sensors for IC die regions of such areas is well-suited to accounting for temperature gradients between different parts of an IC during testing of an IC. Furthermore, it has been found that providing an ATC system with a plurality of temperature measurements for IC die regions of such areas enables the ATC system to control a temperature forcing system to maintain the temperature of an IC within a desired temperature range in the presence of power transients that are commonplace during IC testing.

In the systems and methods of the present disclosure, the ATC system is a feedback control system that uses feedback, in the form of the individual temperature measurements provided by the plurality of temperature sensors, to control a temperature forcing system to maintain the temperature of the IC within a desired testing temperature range. The feedback control systems can be closed-loop controllers, e.g., a proportional-integral-derivative (PID) controller, a proportional-integral (PI) controller, or a proportional-derivative (PD) controller. Particularly good results for maintaining the temperature of an IC within a desired testing temperature range in the presence of power transients common during IC testing were obtained by combining a closed-loop controller with a plurality of individual temperature sensors that each measure the temperature of an IC die region having an area of approximately 10-50 mm2, preferably an area of approximately 15-25 mm2, and by operating the closed-loop controller so as to receive current temperatures and to output control signals at a frequency of approximately 5 to 30 Hz, preferably a frequency of approximately 10-20 Hz.

According to a first aspect, a method is provided for active thermal control (ATC) of an integrated circuit (IC) during a testing procedure. The method includes obtaining a plurality of temperature measurements of a die of the IC. The temperature measurements are provided by a plurality of temperature sensors integrated with the die of the IC. The method further includes controlling, based on the plurality of temperature measurements, a temperature forcing system to implement ATC of the IC by: supplying, based on the plurality of temperature measurements indicating a temperature that falls below a desired test temperature range, heat to the IC from a heat source of the temperature forcing system, or removing, based on the plurality of temperature measurements indicating a temperature exceeding the desired test temperature range, heat from the IC by a heat sink of the temperature forcing system.

In embodiments of the method according to the first aspect, the testing procedure can be a system level test (SLT).

In embodiments of the method according to the first aspect, the IC can be a graphics processing unit (GPU) comprising a substrate and a die, the die comprising a plurality of compute units, each respective compute unit having integrated therewith a respective temperature sensor of the plurality of temperature sensors. In such embodiments, each respective temperature sensor of the plurality of temperatures sensors can be an analog temperature sensor. Each analog temperature sensor can be a semiconductor-based temperature sensor. Each analog temperature sensor can be, e.g., a diode temperature sensor configured to utilize a temperature-dependent voltage drop across a diode junction to measure temperature, a bandgap temperature sensor configured to utilize a temperature-dependent bandgap voltage to measure temperature, a resistance temperature detector (RTD) configured to utilize a temperature-dependent resistor to measure temperature, or a thermocouple.

In embodiments of the method according to the first aspect, the controlling, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC comprises determining, from the plurality of temperature measurements, a maximum value of the temperature of the die of the IC. In such embodiments, the plurality of temperature measurements indicate a temperature that falls below the desired test temperature range based on the maximum value of the temperature of the die of the IC falling below the desired test temperature range, and the plurality of temperature measurements indicate a temperature exceeding the desired test temperature range based on the maximum value of the temperature of the die of the IC exceeding the desired test temperature range.

In embodiments of the method according to the first aspect, obtaining the plurality of temperature measurements of the temperature of the die of the IC can be performed periodically with a frequency in a range of 5 to 30 Hz, and controlling, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC can be performed by periodically outputting a control signal with a frequency in a range of 5 to 30 Hz. In such embodiments, obtaining the plurality of temperature measurements of the temperature can be performed periodically with a frequency in a range of 10 to 20 Hz, and the controlling, based on the plurality of temperature measurements, the temperature forcing system can be performed by periodically outputting a control signal with a frequency of 10 to 20 Hz.

In embodiments of the method according to the first aspect, each respective temperature sensor can be configured to measure a temperature of a respective region of the IC having an area in a range of 10-50 mm2. In such embodiments, each respective temperature sensor can be configured to measure a temperature of a respective region of the IC having an area in a range of 15-25 mm2.

According to a second aspect, a system is provided for active thermal control (ATC) of an integrated circuit (IC) during a testing procedure. The system includes a temperature forcing system comprising a heat source and a heat sink. The system also includes a processor configured to obtain a plurality of temperature measurements of a die of the IC. The temperature measurements are provided by a plurality of temperature sensors integrated with the die of the IC. The processor is further configured to control, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC by instructing, based on the plurality of temperature measurements indicating a temperature that falls below a desired test temperature range, the temperature forcing system to supply heat to the IC, or by instructing, based on the plurality of temperature measurements indicating a temperature that exceeds the desired test temperature range, the temperature forcing system to remove heat from the IC.

In embodiments of the system according to the second aspect, the testing procedure can be a system level test (SLT).

In embodiments of the system according to the second aspect, the IC can be a graphics processing unit (GPU) comprising a substrate and a die, the die comprising a plurality of compute units, each respective compute unit having integrated therewith a respective temperature sensor of the plurality of temperature sensors. In such embodiments, each respective temperature sensor of the plurality of temperatures sensors can be an analog temperature sensor. Each analog temperature sensor can be a semiconductor-based temperature sensor. Each analog temperature sensor can be, e.g., a diode temperature sensor configured to utilize a temperature-dependent voltage drop across a diode junction to measure temperature, a bandgap temperature sensor configured to utilize a temperature-dependent bandgap voltage to measure temperature, a resistance temperature detector (RTD) configured to utilize a temperature-dependent resistor to measure temperature, or a thermocouple.

In embodiments of the system according to the second aspect, the processor can be configured to control, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC by further determining, from the plurality of temperature measurements, a maximum value of the temperature of the die of the IC. In such embodiments, the plurality of temperature measurements indicate a temperature that falls below the desired test temperature range based on the maximum value of the temperature of the die of the IC falling below the desired test temperature range, and the plurality of temperature measurements indicate a temperature exceeding the desired test temperature range based on the maximum value of the temperature of the die of the IC exceeding the desired test temperature range.

In embodiments of the system according to the second aspect, the processor can obtain the plurality of temperature measurements of the temperature of the die of the IC periodically with a frequency of at least 20 Hz, and the processor can implement control, based on the plurality of temperature measurements, of the temperature forcing system to implement ATC of the IC by periodically outputting a control signal with a frequency of 5 to 30 Hz. In such embodiments, the processor can obtain the plurality of temperature measurements periodically with a frequency in a range of 10 to 20 Hz, and the processor can control the temperature forcing system by periodically outputting a control signal with a frequency of 10 to 20 Hz.

In embodiments of the system according to the second aspect, each respective temperature sensor can be configured to measure a temperature of a respective region of the IC having an area in a range of 25 to 50 mm2. In such embodiments, each respective temperature sensor can be configured to measure a temperature of a respective region of the IC having an area in a range of 30 to 40 mm2.

According to a third aspect, non-transitory computer-readable media are provided for storing computer instructions for active thermal control (ATC) of an integrated circuit (IC) during a testing procedure that, when executed by one or more processors, cause the one or more processors to perform a method that includes obtaining a plurality of temperature measurements of a die of the IC. The temperature measurements are provided by a plurality of temperature sensors integrated with the die of the IC. The method further includes controlling, based on the plurality of temperature measurements, a temperature forcing system to implement ATC of the IC by: supplying, based on the plurality of temperature measurements indicating a temperature that falls below a desired test temperature range, heat to the IC from a heat source of the temperature forcing system, or removing, based on the plurality of temperature measurements indicating a temperature exceeding the desired test temperature range, heat from the IC by a heat sink of the temperature forcing system.

In embodiments of the third aspect, the testing procedure can be a system level test (SLT).

In embodiments of the third aspect, the IC can be a graphics processing unit (GPU) comprising a substrate and a die, the die comprising a plurality of compute units, each respective compute unit having integrated therewith a respective temperature sensor of the plurality of temperature sensors. In such embodiments, each respective temperature sensor of the plurality of temperatures sensors can be an analog temperature sensor. Each analog temperature sensor can be a semiconductor-based temperature sensor. Each analog temperature sensor can be, e.g., a diode temperature sensor configured to utilize a temperature-dependent voltage drop across a diode junction to measure temperature, a bandgap temperature sensor configured to utilize a temperature-dependent bandgap voltage to measure temperature, a resistance temperature detector (RTD) configured to utilize a temperature-dependent resistor to measure temperature, or a thermocouple.

In embodiments of the third aspect, the controlling, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC comprises determining, from the plurality of temperature measurements, a maximum value of the temperature of the die of the IC. In such embodiments, the plurality of temperature measurements indicate a temperature that falls below the desired test temperature range based on the maximum value of the temperature of the die of the IC falling below the desired test temperature range, and the plurality of temperature measurements indicate a temperature exceeding the desired test temperature range based on the maximum value of the temperature of the die of the IC exceeding the desired test temperature range.

In embodiments of the third aspect, obtaining the plurality of temperature measurements of the temperature of the die of the IC can be performed periodically with a frequency in a range of 5 to 30 Hz, and controlling, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC can also be performed by periodically outputting a control signal with a frequency in a range of 5 to 30 Hz. In such embodiments, obtaining the plurality of temperature measurements of the temperature can be performed periodically with a frequency in a range of 10 to 20 Hz, and the controlling, based on the plurality of temperature measurements, the temperature forcing system can be performed by periodically outputting a control signal with a frequency of 10 to 20 Hz.

In embodiments of the third aspect, each respective temperature sensor can be configured to measure a temperature of a respective region of the IC having an area in a range of 25 to 50 mm2. In such embodiments, each respective temperature sensor can be configured to measure a temperature of a respective region of the IC having an area in a range of 30 to 40 mm2.

The method 100 includes, at 110, obtaining a plurality of temperature measurements from a plurality of temperature sensors. Each of the plurality of temperature measurements is provided by a respective temperature sensor integrated with an individual compute unit located on the die of the IC. The method 100 further includes, at 120, controlling, based on the plurality of temperature measurements, a temperature forcing system to implement ATC of the IC. Specifically, the method includes, at 122, determining whether a die temperature of the IC falls within a desired testing temperature range. If the die temperature falls within the desired testing temperature range, the method returns to 110 where additional temperature measurements are obtained for a subsequent iteration of a feedback control loop. Alternatively, if the die temperature falls outside the desired testing temperature range, the method proceeds to 124 where it is determined whether the die temperature exceeds the desired testing temperature range or falls below the desired testing temperature range. If the die temperature falls below the desired testing temperature range, the method proceeds to 126 where an instruction to supply heat to the IC from an external heat source is provided to a temperature forcing system. Alternatively, if the die temperature exceeds the desired temperature range, the method proceeds to 128 where an instruction to remove heat from the IC via a heat sink is provided to the temperature forcing system. Thereafter, the method returns to 110 where additional temperature measurements are obtained for a subsequent iteration of a feedback control loop.

FIG. 2 illustrates a block diagram of an example active thermal control (ATC) system 200 suitable for use during a testing procedure for integrated circuits (ICs) according to some embodiments of the present disclosure. The ATC system 200 includes processor 210 and temperature forcing system 220. Temperature forcing system 220 includes heat source 222 and heat sink 224. It should be understood that this and other arrangements described herein are set forth only as examples. Other arrangements and elements (e.g., machines, interfaces, functions, orders, groupings of functions, etc.) may be used in addition to or instead of those shown, and some elements may be omitted altogether. Further, many of the elements described herein are functional entities that may be implemented as discrete or distributed components or in conjunction with other components, and in any suitable combination and location. Various functions described herein as being performed by entities may be carried out by hardware, firmware, and/or software. For instance, various functions may be carried out by a processor executing instructions stored in memory. Furthermore, persons of ordinary skill in the art will understand that any system that performs the operations of the active thermal control (ATC) system 200 is within the scope and spirit of embodiments of the present disclosure.

FIGS. 3A and 3B provide block diagrams of example integrated circuit arrangements having a plurality of temperature sensors integrated with the integrated circuit die. In FIG. 3A, the integrated circuit arrangement 30A includes an integrated circuit die 36 that is mounted on a board 37 and thermally connected to a lid/heat spreader 34 via first thermal interface material (TIM 1) 35, which is in turn thermally connected to a heat sink 31 via a second thermal interface material (TIM 2) 32. The integrated circuit die 36 includes a plurality of temperature sensors 38 integrated therewith. In FIG. 3B, the integrated circuit arrangement 30B includes the same components as the integrated circuit arrangement 30A, except the arrangement 30B does not include a lid/heat spreader. Instead, the integrated circuit die 36 is connected to the heat sink 31 via only a thermal interface material (TIM 1.5) 33. The integrated circuit die 36, in either the integrated circuit arrangement 30A or the integrated circuit arrangement 30B, can be, e.g., a CPU having a plurality of cores or a GPU having a plurality of compute units. Each of the plurality of temperature sensors 38 can be, e.g., integrated with a respective core of a CPU or with a respective compute unit of a GPU.

FIG. 3C illustrates a temperature forcing system suitable for use in implementing some embodiments of the present disclosure. The temperature forcing system includes a thermal head 331, which is the interface via which heat is either suppled from a heat source to the IC or removed, via a heat sink, from the IC. The thermal head 331 sits on top of an IC device 332.

FIG. 3D provides a block diagram of an IC testing arrangement. The IC testing arrangement includes an IC in the form of a graphics processing unit (GPU) 320, a remote temperature sensor 323, and a temperature forcing system processor 324. The GPU includes a PN diode temperature sensor 321 and an on-chip I2C port 322 that connects to I2C bus 325 to provide the temperature measurements to the temperature forcing system processor 324. In addition, a remote temperature sensor 323 receives input from the PN diode temperature sensor 321 and outputs a temperature measurement to the temperature forcing system process 324 via the I2C bus 325. The temperature forcing system processor 324 is configured to, e.g., receive temperature measurements from the PN diode temperature sensor 321 and/or a plurality of temperature sensors that are integrated with individual compute units of the GPU (e.g. temperature sensors 38 of the IC arrangement 30A and 30B of FIGS. 3A and 3B). The temperature forcing system processor is further configured to control a temperature forcing system, e.g. the temperature forcing system having thermal head 331 illustrated in FIG. 3C, so as to maintain the temperature of the GPU 320 within a desired test temperature range during testing.

FIG. 3E provides a graph of (i) temperature measurements provided by different temperature sensors during testing of an IC and (ii) power supplied to the IC during the testing process. Specifically, FIG. 3E illustrates temperature measurements 301 (provided by a temperature sensor connected the case of the IC being tested), temperature measurements 302 (provided by a PN diode disposed on a silicon substrate of the IC being tested), temperature measurements 303 (an average of temperature measurements provided by a plurality of temperature sensors integrated with individual compute units on the die of the IC being tested), and temperature measurements 304 (a peak temperature measurement i.e. a maximum value, of the plurality of temperature sensors integrated with the individual compute units). In addition, FIG. 3E further illustrates power 305 supplied to the IC during the testing procedure. Each of the temperature measurements 301 through 304 and power 305 were obtained at identical points in time at 50 ms increments. As can be seen in FIG. 3E, the temperature measurements 302 through 304 begin to increase shortly after an increase in the power 305 supplied to the IC during the testing procedure and then decrease following a reduction in the power 305 supplied to the IC. However, temperature measurements 301 remain approximately flat throughout the measurement period-thereby demonstrating the inadequacy an IC case-mounted temperature sensor for ATC. Furthermore, with respect to temperature measurements 302 through 304, it can be seen that the response of temperature measurements 303 and 304 to variations in power 305 is significantly more pronounced than the response of temperature measurements 302. Furthermore, not only do temperature measurements 303 and 304 exhibit the largest magnitude response to variations in power 305 (and thus provide the best representation of the actual temperature of the die of the IC), temperature measurements 303 and 304 also respond to variations in power 305 more quickly.

FIG. 3F provides a graph of the die temperature of an IC during a testing process employing active thermal control based on temperature measurements provided by different temperature sensors. In FIG. 3F, die temperature is measured using different temperature measurement inputs to an ATC system. Specifically, (i) temperature measurements 311 were provided for the case of ATC using temperature measurements obtained by a temperature sensor connected the case of the IC being tested, (ii) temperature measurements 312 were provided for the case of ATC using temperature measurements obtained with a 14 Hz sampling rate by a PN diode disposed on a silicon substrate of the IC being tested, (iii) temperature measurements 313 were provided for the case of ATC using temperature measurements obtained with a 50 Hz sampling rate by a PN diode disposed on a silicon substrate of the IC being tested, and (iv) temperature measurements 314 were provided for the case of ATC using a peak temperature measurement of a plurality of temperature sensors integrated with the individual compute units. As can be seen in FIG. 3F, the use of the peak temperature measurement obtained from a plurality of temperature sensors integrated with individual compute units provides the lowest die temperature during testing—thereby minimizing the risk of damage to the IC during the testing process.

Parallel Processing Architecture

In various embodiments, the individual compute units that have temperature sensors integrated therewith are components of a parallel processing unit (PPU), and the IC to be tested may include the PPU. FIG. 4 illustrates such a parallel processing unit (PPU) 400.

In an embodiment, the PPU 400 is a multi-threaded processor that is implemented on one or more integrated circuit devices. The PPU 400 is a latency hiding architecture designed to process many threads in parallel. A thread (e.g., a thread of execution) is an instantiation of a set of instructions configured to be executed by the PPU 400. In an embodiment, the PPU 400 is a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data in order to generate two-dimensional (2D) image data for display on a display device. In other embodiments, the PPU 400 may be utilized for performing general-purpose computations. While one exemplary parallel processor is provided herein for illustrative purposes, it should be strongly noted that such processor is set forth for illustrative purposes only, and that any processor may be employed to supplement and/or substitute for the same.

One or more PPUs 400 may be configured to accelerate thousands of High Performance Computing (HPC), data center, cloud computing, and machine learning applications. The PPU 400 may be configured to accelerate numerous deep learning systems and applications for autonomous vehicles, simulation, computational graphics such as ray or path tracing, deep learning, high-accuracy speech, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and the like.

As shown in FIG. 4, the PPU 400 includes an Input/Output (I/O) unit 405, a front end unit 415, a scheduler unit 420, a work distribution unit 425, a hub 430, a crossbar (Xbar) 470, one or more general processing clusters (GPCs) 450, and one or more memory partition units 480. The PPU 400 may be connected to a host processor or other PPUs 400 via one or more high-speed NVLink 410 interconnect. The PPU 400 may be connected to a host processor or other peripheral devices via an interconnect 402. The PPU 400 may also be connected to a local memory 404 comprising a number of memory devices. In an embodiment, the local memory may comprise a number of dynamic random access memory (DRAM) devices. The DRAM devices may be configured as a high-bandwidth memory (HBM) subsystem, with multiple DRAM dies stacked within each device.

The NVLink 410 interconnect enables systems to scale and include one or more PPUs 400 combined with one or more CPUs, supports cache coherence between the PPUs 400 and CPUs, and CPU mastering. Data and/or commands may be transmitted by the NVLink 410 through the hub 430 to/from other units of the PPU 400 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). The NVLink 410 is described in more detail in conjunction with FIG. 5B.

The I/O unit 405 is configured to transmit and receive communications (e.g., commands, data, etc.) from a host processor (not shown) over the interconnect 402. The I/O unit 405 may communicate with the host processor directly via the interconnect 402 or through one or more intermediate devices such as a memory bridge. In an embodiment, the I/O unit 405 may communicate with one or more other processors, such as one or more the PPUs 400 via the interconnect 402. In an embodiment, the I/O unit 405 implements a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus and the interconnect 402 is a PCIe bus. In alternative embodiments, the I/O unit 405 may implement other types of well-known interfaces for communicating with external devices.

The I/O unit 405 decodes packets received via the interconnect 402. In an embodiment, the packets represent commands configured to cause the PPU 400 to perform various operations. The I/O unit 405 transmits the decoded commands to various other units of the PPU 400 as the commands may specify. For example, some commands may be transmitted to the front end unit 415. Other commands may be transmitted to the hub 430 or other units of the PPU 400 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the I/O unit 405 is configured to route communications between and among the various logical units of the PPU 400.

In an embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the PPU 400 for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (e.g., read/write) by both the host processor and the PPU 400. For example, the I/O unit 405 may be configured to access the buffer in a system memory connected to the interconnect 402 via memory requests transmitted over the interconnect 402. In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU 400. The front end unit 415 receives pointers to one or more command streams. The front end unit 415 manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the PPU 400.

The front end unit 415 is coupled to a scheduler unit 420 that configures the various GPCs 450 to process tasks defined by the one or more streams. The scheduler unit 420 is configured to track state information related to the various tasks managed by the scheduler unit 420. The state may indicate which GPC 450 a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. The scheduler unit 420 manages the execution of a plurality of tasks on the one or more GPCs 450.

The scheduler unit 420 is coupled to a work distribution unit 425 that is configured to dispatch tasks for execution on the GPCs 450. The work distribution unit 425 may track a number of scheduled tasks received from the scheduler unit 420. In an embodiment, the work distribution unit 425 manages a pending task pool and an active task pool for each of the GPCs 450. As a GPC 450 finishes the execution of a task, that task is evicted from the active task pool for the GPC 450 and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 450. If an active task has been idle on the GPC 450, such as while waiting for a data dependency to be resolved, then the active task may be evicted from the GPC 450 and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the GPC 450.

In an embodiment, a host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 400. In an embodiment, multiple compute applications are simultaneously executed by the PPU 400 and the PPU 400 provides isolation, quality of service (QoS), and independent address spaces for the multiple compute applications. An application may generate instructions (e.g., API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 400. The driver kernel outputs tasks to one or more streams being processed by the PPU 400. Each task may comprise one or more groups of related threads, referred to herein as a warp. In an embodiment, a warp comprises 32 related threads that may be executed in parallel. Cooperating threads may refer to a plurality of threads including instructions to perform the task and that may exchange data through shared memory. The tasks may be allocated to one or more processing units within a GPC 450 and instructions are scheduled for execution by at least one warp.

The work distribution unit 425 communicates with the one or more GPCs 450 via XBar 470. The XBar 470 is an interconnect network that couples many of the units of the PPU 400 to other units of the PPU 400. For example, the XBar 470 may be configured to couple the work distribution unit 425 to a particular GPC 450. Although not shown explicitly, one or more other units of the PPU 400 may also be connected to the XBar 470 via the hub 430.

The tasks are managed by the scheduler unit 420 and dispatched to a GPC 450 by the work distribution unit 425. The GPC 450 is configured to process the task and generate results. The results may be consumed by other tasks within the GPC 450, routed to a different GPC 450 via the XBar 470, or stored in the memory 404. The results can be written to the memory 404 via the memory partition units 480, which implement a memory interface for reading and writing data to/from the memory 404. The results can be transmitted to another PPU 400 or CPU via the NVLink 410. In an embodiment, the PPU 400 includes a number U of memory partition units 480 that is equal to the number of separate and distinct memory devices of the memory 404 coupled to the PPU 400. Each GPC 450 may include a memory management unit to provide translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In an embodiment, the memory management unit provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in the memory 404.

In an embodiment, the memory partition unit 480 includes a Raster Operations (ROP) unit, a level two (L2) cache, and a memory interface that is coupled to the memory 404. The memory interface may implement 32, 64, 128, 1024-bit data buses, or the like, for high-speed data transfer. The PPU 400 may be connected to up to Y memory devices, such as high bandwidth memory stacks or graphics double-data-rate, version 5, synchronous dynamic random access memory, or other types of persistent storage. In an embodiment, the memory interface implements an HBM2 memory interface and Y equals half U. In an embodiment, the HBM2 memory stacks are located on the same physical package as the PPU 400, providing substantial power and area savings compared with conventional GDDR5 SDRAM systems. In an embodiment, each HBM2 stack includes four memory dies and Y equals 4, with each HBM2 stack including two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits.

In an embodiment, the memory 404 supports Single-Error Correcting Double-Error Detecting (SECDED) Error Correction Code (ECC) to protect data. ECC provides higher reliability for compute applications that are sensitive to data corruption. Reliability is especially important in large-scale cluster computing environments where PPUs 400 process very large datasets and/or run applications for extended periods.

In an embodiment, the PPU 400 implements a multi-level memory hierarchy. In an embodiment, the memory partition unit 480 supports a unified memory to provide a single unified virtual address space for CPU and PPU 400 memory, enabling data sharing between virtual memory systems. In an embodiment the frequency of accesses by a PPU 400 to memory located on other processors is traced to ensure that memory pages are moved to the physical memory of the PPU 400 that is accessing the pages more frequently. In an embodiment, the NVLink 410 supports address translation services allowing the PPU 400 to directly access a CPU's page tables and providing full access to CPU memory by the PPU 400.

In an embodiment, copy engines transfer data between multiple PPUs 400 or between PPUs 400 and CPUs. The copy engines can generate page faults for addresses that are not mapped into the page tables. The memory partition unit 480 can then service the page faults, mapping the addresses into the page table, after which the copy engine can perform the transfer. In a conventional system, memory is pinned (e.g., non-pageable) for multiple copy engine operations between multiple processors, substantially reducing the available memory. With hardware page faulting, addresses can be passed to the copy engines without worrying if the memory pages are resident, and the copy process is transparent.

Data from the memory 404 or other system memory may be fetched by the memory partition unit 480 and stored in the L2 cache 460, which is located on-chip and is shared between the various GPCs 450. As shown, each memory partition unit 480 includes a portion of the L2 cache associated with a corresponding memory 404. Lower level caches may then be implemented in various units within the GPCs 450. For example, each of the processing units within a GPC 450 may implement a level one (L1) cache. The L1 cache is private memory that is dedicated to a particular processing unit. The L2 cache 460 is coupled to the memory interface 470 and the XBar 470 and data from the L2 cache may be fetched and stored in each of the L1 caches for processing.

In an embodiment, the processing units within each GPC 450 implement a SIMD (Single-Instruction, Multiple-Data) architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. All threads in the group of threads execute the same instructions. In another embodiment, the processing unit implements a SIMT (Single-Instruction, Multiple Thread) architecture where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but where individual threads in the group of threads are allowed to diverge during execution. In an embodiment, a program counter, call stack, and execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. When execution state is maintained for each individual thread, threads executing the same instructions may be converged and executed in parallel for maximum efficiency.

Each processing unit includes a large number (e.g., 128, etc.) of distinct processing cores (e.g., functional units) that may be fully-pipelined, single-precision, double-precision, and/or mixed precision and include a floating point arithmetic logic unit and an integer arithmetic logic unit. In an embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. In an embodiment, the cores include 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

Tensor cores configured to perform matrix operations. In particular, the tensor cores are configured to perform deep learning matrix arithmetic, such as GEMM (matrix-matrix multiplication) for convolution operations during neural network training and inferencing. In an embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

In an embodiment, the matrix multiply inputs A and B may be integer, fixed-point, or floating point matrices, while the accumulation matrices C and D may be integer, fixed-point, or floating point matrices of equal or higher bitwidths. In an embodiment, tensor cores operate on one, four, or eight bit integer input data with 32-bit integer accumulation. The 8-bit integer matrix multiply requires 1024 operations and results in a full precision product that is then accumulated using 32-bit integer addition with the other intermediate products for a 8×8×16 matrix multiply. In an embodiment, tensor Cores operate on 16-bit floating point input data with 32-bit floating point accumulation. The 16-bit floating point multiply requires 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with the other intermediate products for a 4×4×4 matrix multiply. In practice, Tensor Cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements. An API, such as CUDA 9 C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use Tensor Cores from a CUDA-C++ program. At the CUDA level, the warp-level interface assumes 16×16 size matrices spanning all 32 threads of the warp.

Each processing unit may also comprise M special function units (SFUs) that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like). In an embodiment, the SFUs may include a tree traversal unit configured to traverse a hierarchical tree data structure. In an embodiment, the SFUs may include texture unit configured to perform texture map filtering operations. In an embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texels) from the memory 404 and sample the texture maps to produce sampled texture values for use in shader programs executed by the processing unit. In an embodiment, the texture maps are stored in shared memory that may comprise or include an L1 cache. The texture units implement texture operations such as filtering operations using mip-maps (e.g., texture maps of varying levels of detail). In an embodiment, each processing unit includes two texture units.

Each processing unit also comprises N load store units (LSUs) that implement load and store operations between the shared memory and the register file. Each processing unit includes an interconnect network that connects each of the cores to the register file and the LSU to the register file, shared memory. In an embodiment, the interconnect network is a crossbar that can be configured to connect any of the cores to any of the registers in the register file and connect the LSUs to the register file and memory locations in shared memory.

The shared memory is an array of on-chip memory that allows for data storage and communication between the processing units and between threads within a processing unit. In an embodiment, the shared memory comprises 128 KB of storage capacity and is in the path from each of the processing units to the memory partition unit 480. The shared memory can be used to cache reads and writes. One or more of the shared memory, L1 cache, L2 cache, and memory 404 are backing stores.

Combining data cache and shared memory functionality into a single memory block provides the best overall performance for both types of memory accesses. The capacity is usable as a cache by programs that do not use shared memory. For example, if shared memory is configured to use half of the capacity, texture and load/store operations can use the remaining capacity. Integration within the shared memory enables the shared memory to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data.

When configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. Specifically, fixed function graphics processing units, are bypassed, creating a much simpler programming model. In the general purpose parallel computation configuration, the work distribution unit 425 assigns and distributes blocks of threads directly to the processing units within the GPCs 450. Threads execute the same program, using a unique thread ID in the calculation to ensure each thread generates unique results, using the processing unit(s) to execute the program and perform calculations, shared memory to communicate between threads, and the LSU to read and write global memory through the shared memory and the memory partition unit 480. When configured for general purpose parallel computation, the processing units can also write commands that the scheduler unit 420 can use to launch new work on the processing units.

The PPU 400 may be included in a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and the like. In an embodiment, the PPU 400 is embodied on a single semiconductor substrate. In another embodiment, the PPU 400 is included in a system-on-a-chip (SoC) along with one or more other devices such as additional PPUs 400, the memory 404, a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like.

In an embodiment, the PPU 400 may be included on a graphics card that includes one or more memory devices. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, the PPU 400 may be an integrated graphics processing unit (iGPU) or parallel processor included in the chipset of the motherboard. In yet another embodiment, the PPU 400 may be realized in reconfigurable hardware. In yet another embodiment, parts of the PPU 400 may be realized in reconfigurable hardware.

Exemplary Computing System

FIG. 5A is a conceptual diagram of a processing system 500 implemented using the PPU 400 of FIG. 4, in accordance with an embodiment. The processing system 500 includes a CPU 530, switch 510, and multiple PPUs 400, and respective memories 404.

The NVLink 410 provides high-speed communication links between each of the PPUs 400. Although a particular number of NVLink 410 and interconnect 402 connections are illustrated in FIG. 5B, the number of connections to each PPU 400 and the CPU 530 may vary. The switch 510 interfaces between the interconnect 402 and the CPU 530. The PPUs 400, memories 404, and NVLinks 410 may be situated on a single semiconductor platform to form a parallel processing module 525. In an embodiment, the switch 510 supports two or more protocols to interface between various different connections and/or links.

In another embodiment (not shown), the NVLink 410 provides one or more high-speed communication links between each of the PPUs 400 and the CPU 530 and the switch 510 interfaces between the interconnect 402 and each of the PPUs 400. The PPUs 400, memories 404, and interconnect 402 may be situated on a single semiconductor platform to form a parallel processing module 525. In yet another embodiment (not shown), the interconnect 402 provides one or more communication links between each of the PPUs 400 and the CPU 530 and the switch 510 interfaces between each of the PPUs 400 using the NVLink 410 to provide one or more high-speed communication links between the PPUs 400. In another embodiment (not shown), the NVLink 410 provides one or more high-speed communication links between the PPUs 400 and the CPU 530 through the switch 510. In yet another embodiment (not shown), the interconnect 402 provides one or more communication links between each of the PPUs 400 directly. One or more of the NVLink 410 high-speed communication links may be implemented as a physical NVLink interconnect or either an on-chip or on-die interconnect using the same protocol as the NVLink 410.

In an embodiment, the signaling rate of each NVLink 410 is 20 to 25 Gigabits/second and each PPU 400 includes six NVLink 410 interfaces (as shown in FIG. 5A, five NVLink 410 interfaces are included for each PPU 400). Each NVLink 410 provides a data transfer rate of 25 Gigabytes/second in each direction, with six links providing 400 Gigabytes/second. The NVLinks 410 can be used exclusively for PPU-to-PPU communication as shown in FIG. 5A, or some combination of PPU-to-PPU and PPU-to-CPU, when the CPU 530 also includes one or more NVLink 410 interfaces.

In an embodiment, the NVLink 410 allows direct load/store/atomic access from the CPU 530 to each PPU's 400 memory 404. In an embodiment, the NVLink 410 supports coherency operations, allowing data read from the memories 404 to be stored in the cache hierarchy of the CPU 530, reducing cache access latency for the CPU 530. In an embodiment, the NVLink 410 includes support for Address Translation Services (ATS), allowing the PPU 400 to directly access page tables within the CPU 530. One or more of the NVLinks 410 may also be configured to operate in a low-power mode.

FIG. 5B illustrates an exemplary system 565 in which the various architecture and/or functionality of the various previous embodiments may be implemented.

As shown, a system 565 is provided including at least one central processing unit 530 that is connected to a communication bus 575. The communication bus 575 may directly or indirectly couple one or more of the following devices: main memory 540, network interface 535, CPU(s) 530, display device(s) 545, input device(s) 560, switch 510, and parallel processing system 525. The communication bus 575 may be implemented using any suitable protocol and may represent one or more links or busses, such as an address bus, a data bus, a control bus, or a combination thereof. The communication bus 575 may include one or more bus or link types, such as an industry standard architecture (ISA) bus, an extended industry standard architecture (EISA) bus, a video electronics standards association (VESA) bus, a peripheral component interconnect (PCI) bus, a peripheral component interconnect express (PCIe) bus, HyperTransport, and/or another type of bus or link. In some embodiments, there are direct connections between components. As an example, the CPU(s) 530 may be directly connected to the main memory 540. Further, the CPU(s) 530 may be directly connected to the parallel processing system 525. Where there is direct, or point-to-point connection between components, the communication bus 575 may include a PCIe link to carry out the connection. In these examples, a PCI bus need not be included in the system 565.

Although the various blocks of FIG. 5C are shown as connected via the communication bus 575 with lines, this is not intended to be limiting and is for clarity only. For example, in some embodiments, a presentation component, such as display device(s) 545, may be considered an I/O component, such as input device(s) 560 (e.g., if the display is a touch screen). As another example, the CPU(s) 530 and/or parallel processing system 525 may include memory (e.g., the main memory 540 may be representative of a storage device in addition to the parallel processing system 525, the CPUs 530, and/or other components). In other words, the computing device of FIG. 5C is merely illustrative. Distinction is not made between such categories as “workstation,” “server,” “laptop,” “desktop,” “tablet,” “client device,” “mobile device,” “hand-held device,” “game console,” “electronic control unit (ECU),” “virtual reality system,” and/or other device or system types, as all are contemplated within the scope of the computing device of FIG. 5C.

The system 565 also includes a main memory 540. Control logic (software) and data are stored in the main memory 540 which may take the form of a variety of computer-readable media. The computer-readable media may be any available media that may be accessed by the system 565. The computer-readable media may include both volatile and nonvolatile media, and removable and non-removable media. By way of example, and not limitation, the computer-readable media may comprise computer-storage media and communication media.

Computer programs, when executed, enable the system 565 to perform various functions. The CPU(s) 530 may be configured to execute at least some of the computer-readable instructions to control one or more components of the system 565 to perform one or more of the methods and/or processes described herein. The CPU(s) 530 may each include one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) that are capable of handling a multitude of software threads simultaneously. The CPU(s) 530 may include any type of processor, and may include different types of processors depending on the type of system 565 implemented (e.g., processors with fewer cores for mobile devices and processors with more cores for servers). For example, depending on the type of system 565, the processor may be an Advanced RISC Machines (ARM) processor implemented using Reduced Instruction Set Computing (RISC) or an x86 processor implemented using Complex Instruction Set Computing (CISC). The system 565 may include one or more CPUs 530 in addition to one or more microprocessors or supplementary co-processors, such as math co-processors.

In addition to or alternatively from the CPU(s) 530, the parallel processing module 525 may be configured to execute at least some of the computer-readable instructions to control one or more components of the system 565 to perform one or more of the methods and/or processes described herein. The parallel processing module 525 may be used by the system 565 to render graphics (e.g., 3D graphics) or perform general purpose computations. For example, the parallel processing module 525 may be used for General-Purpose computing on GPUs (GPGPU). In embodiments, the CPU(s) 530 and/or the parallel processing module 525 may discretely or jointly perform any combination of the methods, processes and/or portions thereof.

The system 565 also includes input device(s) 560, the parallel processing system 525, and display device(s) 545. The display device(s) 545 may include a display (e.g., a monitor, a touch screen, a television screen, a heads-up-display (HUD), other display types, or a combination thereof), speakers, and/or other presentation components. The display device(s) 545 may receive data from other components (e.g., the parallel processing system 525, the CPU(s) 530, etc.), and output the data (e.g., as an image, video, sound, etc.).

The network interface 535 may enable the system 565 to be logically coupled to other devices including the input devices 560, the display device(s) 545, and/or other components, some of which may be built in to (e.g., integrated in) the system 565. Illustrative input devices 560 include a microphone, mouse, keyboard, joystick, game pad, game controller, satellite dish, scanner, printer, wireless device, etc. The input devices 560 may provide a natural user interface (NUI) that processes air gestures, voice, or other physiological inputs generated by a user. In some instances, inputs may be transmitted to an appropriate network element for further processing. An NUI may implement any combination of speech recognition, stylus recognition, facial recognition, biometric recognition, gesture recognition both on screen and adjacent to the screen, air gestures, head and eye tracking, and touch recognition (as described in more detail below) associated with a display of the system 565. The system 565 may be include depth cameras, such as stereoscopic camera systems, infrared camera systems, RGB camera systems, touchscreen technology, and combinations of these, for gesture detection and recognition. Additionally, the system 565 may include accelerometers or gyroscopes (e.g., as part of an inertia measurement unit (IMU)) that enable detection of motion. In some examples, the output of the accelerometers or gyroscopes may be used by the system 565 to render immersive augmented reality or virtual reality.

Further, the system 565 may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) through a network interface 535 for communication purposes. The system 565 may be included within a distributed network and/or cloud computing environment.

The network interface 535 may include one or more receivers, transmitters, and/or transceivers that enable the system 565 to communicate with other computing devices via an electronic communication network, included wired and/or wireless communications. The network interface 535 may include components and functionality to enable communication over any of a number of different networks, such as wireless networks (e.g., Wi-Fi, Z-Wave, Bluetooth, Bluetooth LE, ZigBee, etc.), wired networks (e.g., communicating over Ethernet or InfiniBand), low-power wide-area networks (e.g., LoRaWAN, SigFox, etc.), and/or the Internet.

The system 565 may also include a secondary storage (not shown). The secondary storage 610 includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (DVD) drive, recording device, universal serial bus (USB) flash memory. The removable storage drive reads from and/or writes to a removable storage unit in a well-known manner. The system 565 may also include a hard-wired power supply, a battery power supply, or a combination thereof (not shown). The power supply may provide power to the system 565 to enable the components of the system 565 to operate.

Each of the foregoing modules and/or devices may even be situated on a single semiconductor platform to form the system 565. Alternately, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user. While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Example Network Environments

Network environments suitable for use in implementing embodiments of the disclosure may include one or more client devices, servers, network attached storage (NAS), other backend devices, and/or other device types. The client devices, servers, and/or other device types (e.g., each device) may be implemented on one or more instances of the processing system 500 of FIG. 5A and/or exemplary system 565 of FIG. 5B—e.g., each device may include similar components, features, and/or functionality of the processing system 500 and/or exemplary system 565.

Machine Learning

Neural networks rely heavily on matrix math operations, and complex multi-layered networks require tremendous amounts of floating-point performance and bandwidth for both efficiency and speed. With thousands of processing cores, optimized for matrix math operations, and delivering tens to hundreds of TFLOPS of performance, the PPU 400 is a computing platform capable of delivering performance required for deep neural network-based artificial intelligence and machine learning applications.

Furthermore, images generated applying one or more of the techniques disclosed herein may be used to train, test, or certify DNNs used to recognize objects and environments in the real world. Such images may include scenes of roadways, factories, buildings, urban settings, rural settings, humans, animals, and any other physical object or real-world setting. Such images may be used to train, test, or certify DNNs that are employed in machines or robots to manipulate, handle, or modify physical objects in the real world. Furthermore, such images may be used to train, test, or certify DNNs that are employed in autonomous vehicles to navigate and move the vehicles through the real world. Additionally, images generated applying one or more of the techniques disclosed herein may be used to convey information to users of such machines, robots, and vehicles.

FIG. 5C illustrates components of an exemplary system 555 that can be used to train and utilize machine learning, in accordance with at least one embodiment. As will be discussed, various components can be provided by various combinations of computing devices and resources, or a single computing system, which may be under control of a single entity or multiple entities. Further, aspects may be triggered, initiated, or requested by different entities. In at least one embodiment training of a neural network might be instructed by a provider associated with provider environment 506, while in at least one embodiment training might be requested by a customer or other user having access to a provider environment through a client device 502 or other such resource. In at least one embodiment, training data (or data to be analyzed by a trained neural network) can be provided by a provider, a user, or a third party content provider 524. In at least one embodiment, client device 502 may be a vehicle or object that is to be navigated on behalf of a user, for example, which can submit requests and/or receive instructions that assist in navigation of a device.

In at least one embodiment, requests are able to be submitted across at least one network 504 to be received by a provider environment 506. In at least one embodiment, a client device may be any appropriate electronic and/or computing devices enabling a user to generate and send such requests, such as, but not limited to, desktop computers, notebook computers, computer servers, smartphones, tablet computers, gaming consoles (portable or otherwise), computer processors, computing logic, and set-top boxes. Network(s) 504 can include any appropriate network for transmitting a request or other such data, as may include Internet, an intranet, an Ethernet, a cellular network, a local area network (LAN), a wide area network (WAN), a personal area network (PAN), an ad hoc network of direct wireless connections among peers, and so on.

In at least one embodiment, requests can be received at an interface layer 508, which can forward data to a training and inference manager 532, in this example. The training and inference manager 532 can be a system or service including hardware and software for managing requests and service corresponding data or content, in at least one embodiment, the training and inference manager 532 can receive a request to train a neural network, and can provide data for a request to a training module 512. In at least one embodiment, training module 512 can select an appropriate model or neural network to be used, if not specified by the request, and can train a model using relevant training data. In at least one embodiment, training data can be a batch of data stored in a training data repository 514, received from client device 502, or obtained from a third party provider 524. In at least one embodiment, training module 512 can be responsible for training data. A neural network can be any appropriate network, such as a recurrent neural network (RNN) or convolutional neural network (CNN). Once a neural network is trained and successfully evaluated, a trained neural network can be stored in a model repository 516, for example, that may store different models or networks for users, applications, or services, etc. In at least one embodiment, there may be multiple models for a single application or entity, as may be utilized based on a number of different factors.

In at least one embodiment, at a subsequent point in time, a request may be received from client device 502 (or another such device) for content (e.g., path determinations) or data that is at least partially determined or impacted by a trained neural network. This request can include, for example, input data to be processed using a neural network to obtain one or more inferences or other output values, classifications, or predictions, or for at least one embodiment, input data can be received by interface layer 508 and directed to inference module 518, although a different system or service can be used as well. In at least one embodiment, inference module 518 can obtain an appropriate trained network, such as a trained deep neural network (DNN) as discussed herein, from model repository 516 if not already stored locally to inference module 518. Inference module 518 can provide data as input to a trained network, which can then generate one or more inferences as output. This may include, for example, a classification of an instance of input data. In at least one embodiment, inferences can then be transmitted to client device 502 for display or other communication to a user. In at least one embodiment, context data for a user may also be stored to a user context data repository 522, which may include data about a user which may be useful as input to a network in generating inferences, or determining data to return to a user after obtaining instances. In at least one embodiment, relevant data, which may include at least some of input or inference data, may also be stored to a local database 534 for processing future requests. In at least one embodiment, a user can use account information or other information to access resources or functionality of a provider environment. In at least one embodiment, if permitted and available, user data may also be collected and used to further train models, in order to provide more accurate inferences for future requests. In at least one embodiment, requests may be received through a user interface to a machine learning application 526 executing on client device 502, and results displayed through a same interface. A client device can include resources such as a processor 528 and memory 562 for generating a request and processing results or a response, as well as at least one data storage element 552 for storing data for machine learning application 526.

In at least one embodiment a processor 528 (or a processor of training module 512 or inference module 518) will be a central processing unit (CPU). As mentioned, however, resources in such environments can utilize GPUs to process data for at least certain types of requests. With thousands of cores, GPUs, such as PPU 300 are designed to handle substantial parallel workloads and, therefore, have become popular in deep learning for training neural networks and generating predictions. While use of GPUs for offline builds has enabled faster training of larger and more complex models, generating predictions offline implies that either request-time input features cannot be used or predictions must be generated for all permutations of features and stored in a lookup table to serve real-time requests. If a deep learning framework supports a CPU-mode and a model is small and simple enough to perform a feed-forward on a CPU with a reasonable latency, then a service on a CPU instance could host a model. In this case, training can be done offline on a GPU and inference done in real-time on a CPU. If a CPU approach is not viable, then a service can run on a GPU instance. Because GPUs have different performance and cost characteristics than CPUs, however, running a service that offloads a runtime algorithm to a GPU can require it to be designed differently from a CPU based service.

In at least one embodiment, video data can be provided from client device 502 for enhancement in provider environment 506. In at least one embodiment, video data can be processed for enhancement on client device 502. In at least one embodiment, video data may be streamed from a third party content provider 524 and enhanced by third party content provider 524, provider environment 506, or client device 502. In at least one embodiment, video data can be provided from client device 502 for use as training data in provider environment 506.

In at least one embodiment, supervised and/or unsupervised training can be performed by the client device 502 and/or the provider environment 506. In at least one embodiment, a set of training data 514 (e.g., classified or labeled data) is provided as input to function as training data. In an embodiment, the set of training data may be used in a generative adversarial training configuration to train a generator neural network.

In at least one embodiment, training data can include images of at least one human subject, avatar, or character for which a neural network is to be trained. In at least one embodiment, training data can include instances of at least one type of object for which a neural network is to be trained, as well as information that identifies that type of object. In at least one embodiment, training data might include a set of images that each includes a representation of a type of object, where each image also includes, or is associated with, a label, metadata, classification, or other piece of information identifying a type of object represented in a respective image. Various other types of data may be used as training data as well, as may include text data, audio data, video data, and so on. In at least one embodiment, training data 514 is provided as training input to a training module 512. In at least one embodiment, training module 512 can be a system or service that includes hardware and software, such as one or more computing devices executing a training application, for training a neural network (or other model or algorithm, etc.). In at least one embodiment, training module 512 receives an instruction or request indicating a type of model to be used for training, in at least one embodiment, a model can be any appropriate statistical model, network, or algorithm useful for such purposes, as may include an artificial neural network, deep learning algorithm, learning classifier, Bayesian network, and so on. In at least one embodiment, training module 512 can select an initial model, or other untrained model, from an appropriate repository 516 and utilize training data 514 to train a model, thereby generating a trained model (e.g., trained deep neural network) that can be used to classify similar types of data, or generate other such inferences. In at least one embodiment where training data is not used, an appropriate initial model can still be selected for training on input data per training module 512.

In at least one embodiment, a model can be trained in a number of different ways, as may depend in part upon a type of model selected. In at least one embodiment, a machine learning algorithm can be provided with a set of training data, where a model is a model artifact created by a training process. In at least one embodiment, each instance of training data contains a correct answer (e.g., classification), which can be referred to as a target or target attribute. In at least one embodiment, a learning algorithm finds patterns in training data that map input data attributes to a target, an answer to be predicted, and a machine learning model is output that captures these patterns. In at least one embodiment, a machine learning model can then be used to obtain predictions on new data for which a target is not specified.

In at least one embodiment, training and inference manager 532 can select from a set of machine learning models including binary classification, multiclass classification, generative, and regression models. In at least one embodiment, a type of model to be used can depend at least in part upon a type of target to be predicted.

Graphics Processing Pipeline

In an embodiment, the PPU 400 comprises a graphics processing unit (GPU). The PPU 400 is configured to receive commands that specify shader programs for processing graphics data. Graphics data may be defined as a set of primitives such as points, lines, triangles, quads, triangle strips, and the like. Typically, a primitive includes data that specifies a number of vertices for the primitive (e.g., in a model-space coordinate system) as well as attributes associated with each vertex of the primitive. The PPU 400 can be configured to process the graphics primitives to generate a frame buffer (e.g., pixel data for each of the pixels of the display).

An application writes model data for a scene (e.g., a collection of vertices and attributes) to a memory such as a system memory or memory 404. The model data defines each of the objects that may be visible on a display. The application then makes an API call to the driver kernel that requests the model data to be rendered and displayed. The driver kernel reads the model data and writes commands to the one or more streams to perform operations to process the model data. The commands may reference different shader programs to be implemented on the processing units within the PPU 400 including one or more of a vertex shader, hull shader, domain shader, geometry shader, and a pixel shader. For example, one or more of the processing units may be configured to execute a vertex shader program that processes a number of vertices defined by the model data. In an embodiment, the different processing units may be configured to execute different shader programs concurrently. For example, a first subset of processing units may be configured to execute a vertex shader program while a second subset of processing units may be configured to execute a pixel shader program. The first subset of processing units processes vertex data to produce processed vertex data and writes the processed vertex data to the L2 cache 460 and/or the memory 404. After the processed vertex data is rasterized (e.g., transformed from three-dimensional data into two-dimensional data in screen space) to produce fragment data, the second subset of processing units executes a pixel shader to produce processed fragment data, which is then blended with other processed fragment data and written to the frame buffer in memory 404. The vertex shader program and pixel shader program may execute concurrently, processing different data from the same scene in a pipelined fashion until all of the model data for the scene has been rendered to the frame buffer. Then, the contents of the frame buffer are transmitted to a display controller for display on a display device.

Example Game Streaming System

FIG. 6B is an example system diagram for a game streaming system 605, in accordance with some embodiments of the present disclosure. FIG. 6B includes game server(s) 603 (which may include similar components, features, and/or functionality to the example processing system 500 of FIG. 5A and/or exemplary system 565 of FIG. 5B), client device(s) 604 (which may include similar components, features, and/or functionality to the example processing system 500 of FIG. 5A and/or exemplary system 565 of FIG. 5B), and network(s) 606 (which may be similar to the network(s) described herein). In some embodiments of the present disclosure, the system 605 may be implemented.

In the system 605, for a game session, the client device(s) 604 may only receive input data in response to inputs to the input device(s), transmit the input data to the game server(s) 603, receive encoded display data from the game server(s) 603, and display the display data on the display 624. As such, the more computationally intense computing and processing is offloaded to the game server(s) 603 (e.g., rendering—in particular ray or path tracing—for graphical output of the game session is executed by the GPU(s) of the game server(s) 603). In other words, the game session is streamed to the client device(s) 604 from the game server(s) 603, thereby reducing the requirements of the client device(s) 604 for graphics processing and rendering.

For example, with respect to an instantiation of a game session, a client device 604 may be displaying a frame of the game session on the display 624 based on receiving the display data from the game server(s) 603. The client device 604 may receive an input to one of the input device(s) and generate input data in response. The client device 604 may transmit the input data to the game server(s) 603 via the communication interface 621 and over the network(s) 606 (e.g., the Internet), and the game server(s) 603 may receive the input data via the communication interface 618. The CPU(s) may receive the input data, process the input data, and transmit data to the GPU(s) that causes the GPU(s) to generate a rendering of the game session. For example, the input data may be representative of a movement of a character of the user in a game, firing a weapon, reloading, passing a ball, turning a vehicle, etc. The rendering component 612 may render the game session (e.g., representative of the result of the input data) and the render capture component 614 may capture the rendering of the game session as display data (e.g., as image data capturing the rendered frame of the game session). The rendering of the game session may include ray or path-traced lighting and/or shadow effects, computed using one or more parallel processing units—such as GPUs, which may further employ the use of one or more dedicated hardware accelerators or processing cores to perform ray or path-tracing techniques—of the game server(s) 603. The encoder 616 may then encode the display data to generate encoded display data and the encoded display data may be transmitted to the client device 604 over the network(s) 606 via the communication interface 618. The client device 604 may receive the encoded display data via the communication interface 621 and the decoder 622 may decode the encoded display data to generate the display data. The client device 604 may then display the display data via the display 624.

It is noted that the techniques described herein may be embodied in executable instructions stored in a computer readable medium for use by or in connection with a processor-based instruction execution machine, system, apparatus, or device. It will be appreciated by those skilled in the art that, for some embodiments, various types of computer-readable media can be included for storing data. As used herein, a “computer-readable medium” includes one or more of any suitable media for storing the executable instructions of a computer program such that the instruction execution machine, system, apparatus, or device may read (or fetch) the instructions from the computer-readable medium and execute the instructions for carrying out the described embodiments. Suitable storage formats include one or more of an electronic, magnetic, optical, and electromagnetic format. A non-exhaustive list of conventional exemplary computer-readable medium includes: a portable computer diskette; a random-access memory (RAM); a read-only memory (ROM); an erasable programmable read only memory (EPROM); a flash memory device; and optical storage devices, including a portable compact disc (CD), a portable digital video disc (DVD), and the like.

It should be understood that the arrangement of components illustrated in the attached Figures are for illustrative purposes and that other arrangements are possible. For example, one or more of the elements described herein may be realized, in whole or in part, as an electronic hardware component. Other elements may be implemented in software, hardware, or a combination of software and hardware. Moreover, some or all of these other elements may be combined, some may be omitted altogether, and additional components may be added while still achieving the functionality described herein. Thus, the subject matter described herein may be embodied in many different variations, and all such variations are contemplated to be within the scope of the claims.

To facilitate an understanding of the subject matter described herein, many aspects are described in terms of sequences of actions. It will be recognized by those skilled in the art that the various actions may be performed by specialized circuits or circuitry, by program instructions being executed by one or more processors, or by a combination of both. The description herein of any sequence of actions is not intended to imply that the specific order described for performing that sequence must be followed. All methods described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context.

The use of the terms “a” and “an” and “the” and similar references in the context of describing the subject matter (particularly in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The use of the term “at least one” followed by a list of one or more items (for example, “at least one of A and B”) is to be construed to mean one item selected from the listed items (A or B) or any combination of two or more of the listed items (A and B), unless otherwise indicated herein or clearly contradicted by context. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation, as the scope of protection sought is defined by the claims as set forth hereinafter together with any equivalents thereof. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illustrate the subject matter and does not pose a limitation on the scope of the subject matter unless otherwise claimed. The use of the term “based on” and other like phrases indicating a condition for bringing about a result, both in the claims and in the written description, is not intended to foreclose any other conditions that bring about that result. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention as claimed.