Method and system for power control of a wireless communication device

According to the present disclosure, a method for tracking power levels of a wireless communications signal comprises receiving a feedback signal indicative of a power level of a wireless communication signal associated transmitted from a transmit path to an antenna of a wireless communication element. The method further comprises receiving a reference signal associated with a digital signal converted into the wireless communication signal. Additionally, the method comprises determining a gain of the feedback signal with respect to the reference signal and determining a gain error based on the determined gain and an expected gain.

TECHNICAL FIELD

The present disclosure relates generally to mobile communication networks, and more particularly, to a method and system for dynamic power control of a wireless communication device.

BACKGROUND

Traditional wireless communication terminals (e.g., cell phones) may use an external power detector to sense the output power of the terminal to control and adjust the output power of the terminal. However, using power detectors to sense output power may add to the cost of the terminal because of the need for the external discrete component. Additionally, selecting the appropriate detector and integrating the detector with the circuitry of the terminal may increase the cost, time and/or resources required to develop the terminal. Additionally, power control systems with external power detectors may require approximately thirty to forty microseconds (μsec) to perform gain control whereas various wireless communication protocols such as code division multiple access (CDMA) and evolution data optimized (EVDO) may require power control response times of less than seven microseconds. Further, power control systems with external power detectors may be susceptible to external blockers and interferers.

SUMMARY

In accordance with the present disclosure, disadvantages and problems associated with tracking power of a wireless communication device may be reduced. According to the present disclosure, a wireless communication element comprises a transmit path configured to convert a digital signal into a wireless communication signal. The wireless communication element further comprises an antenna coupled to the transmit path and configured to transmit the wireless communication signal. The wireless communication element also comprises a feedback receive path communicatively coupled between the antenna and transmit path. The feedback receive path is configured to receive a feedback signal indicative of a power level of the wireless communication signal transmitted from the transmit path to the antenna. The wireless communication element additionally comprises an error tracking path coupled to the feedback receive path. The error tracking path is configured to receive the feedback signal and receive a reference signal associated with the digital signal. The error tracking path is further configured to determine a gain of the feedback signal with respect to the reference signal and determine a gain error based on the determined gain and an expected gain.

DETAILED DESCRIPTION

FIG. 1illustrates a block diagram of an example wireless communication system100, in accordance with certain embodiments of the present disclosure. For simplicity, only two terminals110and two base stations120are shown inFIG. 1. A terminal110may also be referred to as a remote station, a mobile station, an access terminal, user equipment (UE), a wireless communication device, a cellular phone, or some other terminology. A base station120may be a fixed station and may also be referred to as an access point, a Node B, or some other terminology. A mobile switching center (MSC)140may be coupled to the base stations120and may provide coordination and control for base stations120.

System100may be a Code Division Multiple Access (CDMA) system, a Time Division Multiple Access (TDMA) system, or some other wireless communication system. A CDMA system may implement one or more CDMA standards such as IS-95 , IS-2000 (also commonly known as “1×”), IS-856 (also commonly known as “1×EV-DO”), Wideband-CDMA (W-CDMA), and so on. A TDMA system may implement one or more TDMA standards such as Global System for Mobile Communications (GSM). The W-CDMA standard is defined by a consortium known as 3GPP, and the IS-2000 and IS-856 standards are defined by a consortium known as 3GPP2.

A terminal110may or may not be capable of receiving signals from satellites130. Satellites130may belong to a satellite positioning system such as the well-known Global Positioning System (GPS). Each GPS satellite may transmit a GPS signal encoded with information that allows GPS receivers on earth to measure the time of arrival of the GPS signal. Measurements for a sufficient number of GPS satellites may be used to accurately estimate a three-dimensional position of a GPS receiver. A terminal110may also be capable of receiving signals from other types of transmitting sources such as a Bluetooth transmitter, a Wireless Fidelity (Wi-Fi) transmitter, a wireless local area network (WLAN) transmitter, an IEEE 802.11 transmitter, and any other suitable transmitter.

InFIG. 1, each terminal110is shown as receiving signals from multiple transmitting sources simultaneously, where a transmitting source may be a base station120or a satellite130. In certain embodiments, a terminal110may also be a transmitting source. In general, a terminal110may receive signals from zero, one, or multiple transmitting sources at any given moment.

A terminal110may be configured to transmit signals to a base station120at varying signal power levels depending on a variety of parameters such that the base station120may receive the transmitted signal. In some instances the terminal110may include a power amplifier (e.g., power amplifier220ofFIG. 2) that may amplify the signal and may be adjusted such the power of signals transmitted by the terminal110is at the desired level. The power amplifier may be adjusted based at least in part on detection of the transmitted signal power to ensure that the power amplifier is transmitting at the desired level. As disclosed in further detail below, the transmitted signal power may be detected using a feedback, self-receive (crx) path instead of an external discrete power detector.

As described further below, the crx path may be coupled to an error tracking path configured to receive the signal detected by the crx path (“crx signal”). The error tracking path may also be configured to receive a reference signal that is to be transmitted by terminal110. After passing through a transmit path, the reference signal may be detected by the crx path as a crx signal, such that the crx signal may be associated with the reference signal. However, a delay may occur between reception of the reference signal and reception of the crx signal. Therefore, the error tracking path may determine the time delay between the reference signal and the crx signal such that the error tracking path may time align the reference signal with the crx signal. The error tracking path may also be configured to determine the gain of the crx signal with respect to the reference signal. Further, the error tracking path may be configured to remove an expected gain from the determined gain such that the error tracking path may determine the gain error between the actual gain and the expected gain. Once the gain error is known, the terminal110may adjust the signal power such that the actual gain is more closely related to the expected gain. Therefore, terminal110may be configured to use the error tracking path to adjust the gain of transmitted signals. The error tracking path may also be configured to determine the presence of interferers or blockers that may disrupt the transmission of the wireless communication signal transmitted by a terminal110.

Such a configuration may allow for a power control system that does not require external power detectors. Additionally, using the crx and error tracking paths of the present disclosure, power tracking may be accomplished in a reduced amount of time as compared to implementations that may use an external power detector. Further, the error tracking path and crx path may be used to track interference that may not be detected using an external power detector.

FIG. 2illustrates a block diagram of selected components of an example transmitting and/or receiving element200(e.g., a terminal110, a base station120, or a satellite130), configured to detect the transmission power of element200using a crx path and error tracking path instead of a power detector to improve the power control of RF signals transmitted by element200.

Element200may include a transmit path201and a crx path221. Element200may also include a receive path not expressly shown. Depending on the functionality of element200, element200may be considered a transmitter, a receiver, or a transceiver. Element200may also include an error tracking path241configured to compare a signal detected by crx path221with a reference signal such that power control of an RF signal being transmitted by element200may be achieved, as discussed further below.

Digital circuitry202of element202may include any system, device, or apparatus configured to process digital signals and information received via receive a receive path, and/or configured to process signals and information for transmission via transmit path201. Accordingly digital circuitry202may comprise any system, device, or apparatus configured to interpret and/or execute program instructions and/or process data, and may include without limitation a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), or any other digital or analog circuitry configured to interpret and/or execute program instructions and/or process data. In some embodiments, digital circuitry202may interpret and/or execute program instructions and/or process data stored in memory communicatively coupled to and/or included in digital circuitry202.

Memory may comprise any system, device or apparatus operable to retain program instructions or data for a period of time (e.g., computer-readable media). Memory may include random access memory (RAM), electrically erasable programmable read-only memory (EEPROM), a PCMCIA card, flash memory, magnetic storage, opto-magnetic storage, or any suitable selection and/or array of volatile or non-volatile memory that retains data after power to digital circuitry202is turned off

As discussed in further detail below, digital circuitry202may be configured to control the power of RF signals transmitted via transmit path201by, for example adjusting the gain of a variable gain amplifier (VGA214) and/or a power amplifier220configured to amplify one or more wireless communication signals. Digital circuitry202may be configured to communicate in-phase (I) channel and quadrature (Q) channel components (not expressly shown) of a digital signal to transmit path201.

Transmit path201may include a digital-to-analog converter (DAC)204. DAC204may be configured to receive a digital signal from digital circuitry202and convert such digital signal into an analog signal. Such analog signal may then be passed to one or more other components of transmit path201, including upconverter208.

Upconverter208may be configured to frequency upconvert an analog signal received from DAC204to a wireless communication signal at a radio frequency based on an oscillator signal provided by oscillator210. Oscillator210may be any suitable device, system, or apparatus configured to produce an analog waveform of a particular frequency for modulation or upconversion of an analog signal to a wireless communication signal, or for demodulation or downconversion of a wireless communication signal to an analog signal. In some embodiments, oscillator210may be a digitally-controlled crystal oscillator.

Transmit path201may include a variable-gain amplifier (VGA)214to amplify an upconverted signal for transmission, and a bandpass filter216configured to receive an amplified signal VGA214and pass signal components in the band of interest and remove out-of-band noise and undesired signals. The bandpass filtered signal may be received by power amplifier220where it is amplified for transmission.

The amplified signal may be received by a radio frequency (RF) coupler225coupled between power amplifier220and antenna218. RF coupler225may be any system, device or apparatus configured to couple at least a portion of the transmission power in the transmission line between power amplifier220and antenna218and send that transmission power to crx path221, described in further detail. RF coupler225may also couple the remaining portion of the amplified signal received from power amplifier220and send it to antenna218. Antenna218may receive the amplified signal from coupler225and transmit such signal (e.g., to one or more of a terminal110, a base station120, and/or a satellite130). The signal amplified by power amplifier220and transmitted by antenna218may be referred to as an RF signal or a transmitted signal.

Crx path221may include a bandpass filter236configured to receive a portion of the wireless communication signal transmitted by transmit path201via RF coupler225. Bandpass filter236may pass the in the band of interest and remove out-of-band noise and undesired signals. In addition, crx path221may include a low-noise amplifier (LNA)224to amplify the signal received from bandpass filter236.

Crx path221may also include a downconverter228. Downconverter228may be configured to frequency downconvert a wireless communication signal received via antenna218and amplified by LNA234by an oscillator signal provided by oscillator210(e.g., downconvert to a baseband signal). During downconversion the signal may be divided into its I and Q channel components. In addition, crx path221may include an analog-to-digital converter (ADC)224configured to receive an analog signal from downconverter228and convert such analog signal into a digital signal. Such digital signal may then be passed to a filter238configured to remove any DC offset of the signal detected by crx path221(“the crx signal”). In some embodiments, filter238may comprise a moving average filter. Filter238may communicate the crx signal to error tracking path241. Although not expressly shown, the crx signal may be separated according to its I and Q channel components, and accordingly, crx path221may include an ADC224and filter221for each channel component.

Error tracking path241may include a droop compensator240configured to receive the crx signal and adjust for frequency gain droop caused by downconversion. Droop compensator may be configured to accordingly amplify the I and Q channels of the crx signal with a frequency amplified gain.

Droop compensator240may communicate the crx signal to a gain imbalance compensator242configured to adjust for any gain imbalance that may be present between the I and Q channels of the crx signal such that the gain of the I and Q channels may be substantially equal. Gain imbalance compensator242may communicate the crx signal to a phase imbalance compensator244configured to adjust for any phase difference between the I and Q channels such that the I and Q channels are substantially in quadrature phase with each other (e.g., offset by a 90° phase). Phase imbalance compensator244may communicate the crx signal to a magnitude estimator246.

Magnitude estimator246may be configured to determine the magnitude of the crx signal. In some embodiments, magnitude estimator246may determine the magnitude of the crx signal by taking the square root of the sum of the I channel magnitude squared and the Q channel magnitude squared. Magnitude estimator246may communicate the crx magnitude (crx(n), where n may represent the current sample) to an adaptive gain and delay module (“gain and delay module”)248configured to determine the gain of the crx signal with respect to the reference signal. Gain and delay module248may also be configured to determine delay differences between the crx signal and a reference signal to time align the reference and crx signals such that a more accurate gain may be determined, as disclosed further below.

The reference signal may be used by gain and delay module248, as its name denotes, as a reference to determine the gain experienced by signals being transmitted by transmit path201as measured by crx path221and indicated by the crx signal. Accordingly, gain and delay module248may compare the reference signal with the crx signal to determine the actual gain of the transmitted RF signal. Gain and delay module248may communicate the determined gain to a loop gain compensator250. As described in further detail below, loop gain compensator250may compare the actual gain of the crx signal with the expected gain of the crx signal such that the gain error (e.g., difference between the actual gain and the expected gain) may be determined. With the gain error known, loop gain compensator250may communicate such to digital circuitry202such that digital circuitry202may adjust the gain of the signals transmitted via transmit path201(e.g., adjust the gain of the digital signal communicated to transmit path201) to compensate for the gain error to more accurately control the power of the transmitted RF signal. In the same or alternative embodiments, loop gain compensator250and or digital circuitry202may also be configured to adjust the gain of VGA214to compensate for the gain error.

Gain and delay module248may also be configured to determine the delay between the crx signal and the reference signal. Gain and delay module248may accordingly communicate the delay to a delay adjustment module254such that delay module254may time align the reference signal with the crx signal to allow for a more accurate comparison of the reference signal gain with the crx signal gain.

Gain and delay module248may determine the gain of the crx signal with respect to the reference signal and may also determine the delay differences between the crx and reference signals using any suitable method, such as a least mean squares (LMS) or recursive least squares (RLS) algorithm.FIG. 3, described in more detail below, illustrates an embodiment that uses a least mean squares algorithm.

As mentioned above, error tracking path241may include a delay adjustment module254configured to receive a reference signal from digital circuitry202. Additionally, as also mentioned above, although not expressly shown, the reference signal may be divided according to its I and Q channel components. Delay adjustment module254may receive a control signal from gain and delay module248that indicates the time difference between the reference signal and the crx signal. The delay may be expressed in terms of digital samples. Accordingly, delay module254may delay the reference signal by the number of samples indicated by gain and delay module248.

Delay module254may include a plurality of delay modules configured to provide varying degrees of delay with varying degrees of delay resolution. For example, delay module254may include a course integer delay module configured to make course delay adjustments of the reference signal that may include a delay resolution of more than one sample at a particular sampling rate (e.g., a delay resolution of four samples at a 62.4 MHz sampling rate). Delay module254may also include a fine integer delay module configured to provide a delay adjustment resolution of up to one sample at the indicated sampling rate (e.g., a delay resolution of one sample at a 62.4 MHz sampling rate). Further, in the same or alternative embodiments, delay module254may include a fractional delay module configured to provide a delay resolution of a fraction of a sample at the indicated sampling rate (e.g., a delay resolution of 0.1 samples at a 62.4 MHz sampling rate). Accordingly, the finer the delay resolution of the fine delay adjustment, the more precise the delay adjustment may be.

Delay module254may communicate the time aligned reference signal to a magnitude estimator252configured to estimate the magnitude of the reference signal. Magnitude estimator252may be substantially similar to magnitude estimator246. Magnitude estimator252may communicate the time adjustment magnitude of the reference signal (e.g., ref(n), where n may represent the current sample of the reference signal) to gain and delay module248such that gain and delay module248may determine the gain between of the time aligned reference and crx signals.

Upon determining the gain between the reference and crx signals, gain and delay module248may communicate the determined gain to a loop gain compensator250. Loop gain compensator250may be configured to subtract the expected gain of the crx signal out from the determined gain to determine the gain error of the transmitted signal. The expected gain of the crx signal may be based on the expected gain of transmit path201and crx path221that may be exerted on a signal leaving digital circuitry202and received by gain and delay module248as a crx signal.

For example, a signal leaving digital circuitry202may experience amplification and/or attenuation within transmit path201such as being amplified by VGA214and power amplifier220along with experiencing attenuation at upconverter208and/or bandpass filter216. Additionally, the signal may experience a loss at coupler225and at the pad (not expressly shown) configured to receive the feedback signal from coupler225for transmission through crx path221. Additionally, the feedback signal may be amplified by LNA234and/or may be attenuated by downconverter228before entering error tracking path241as a crx signal. These gains and losses may be known to a certain degree such that the expected gain of a signal leaving digital circuitry202and received at gain and delay module248as a crx signal may be approximated. Therefore, loop gain compensator250may subtract the expected loop gain from the measured gain to obtain the gain error, which may indicate the difference between the actual gain and the expected gain.

Loop gain compensator250may communicate the gain error to digital circuitry202. As mentioned above, digital circuitry202may accordingly account for the gain error when adjusting the gain of the transmitted signal (e.g., by adjusting the gain of the digital signal communicated to transmit path201) such that the transmitted signal power may more closely correspond with its desired signal power. Further, as previously mentioned, in the same or alternative embodiments, loop gain compensator250and or digital circuitry202may also be configured to adjust the gain of VGA214to compensate for the gain error.

Gain and delay module248may also be configured to communicate an error signal (e(n)) to an interference detecting module260. The error signal may indicate the difference between the crx signal and the reference signal multiplied by the determined gain. An interferer and/or blocker may cause the detected crx signal to have a much different magnitude than if the blocker were not present. Additionally, the blocker may cause the magnitude of the crx signal to change in an unpredictable manner. In such instances, the gain determined by gain and delay module248and applied to the reference signal may not appropriately match the gain of the crx signal with respect to the reference signal. Accordingly, the error between the crx signal and the reference signal multiplied by the determined gain may increase when a blocker is present. Thus, interference detecting module260may determine whether the error is above an indicated threshold and if so, may communicate a flag to digital circuitry202indicating that a blocker may be present. Digital circuitry202may address the blocker accordingly.

Therefore, crx path221, error tracking path241and digital circuitry202may be configured to track and adjust the power of signals being transmitted by element200. Such a configuration may not include an external power detector and may have a decreased settling time as compared to an external power detection system. Accordingly, the gain error tracking may be faster than with other power detection and tracking configurations.

Modifications, additions or omissions may be made toFIG. 2without departing from the scope of the present disclosure. For example, as mentioned above, the reference and crx signals may include I and Q channel signal components such that crx path221, error tracking path241and transmit path201may include components that may be configured to perform operations with respect to the I channel and other analogous components that may be configured to perform operations with respect to the Q channel. For example, element200may include an ADC for each channel at each analog to digital conversion and may include an amplifier for each channel, even though only one is shown inFIG. 2.

FIG. 3illustrates an example embodiment of gain and delay module248ofFIG. 2. In the present example, gain and delay module248may comprise a DSP configured to perform a least mean squares (LMS) algorithm to determine the gain and delay between ref(n) and crx(n) ofFIG. 2. However, it is understood that any suitable system, apparatus or device configured to perform any suitable adaptive error detection method (e.g., an RLS algorithm) may also be used.

Gain and delay module248may include a gain adaptation path300and a delay adaptation path301configured to determine the gain and delay, respectively, between each digital sample of ref(n) and crx(n). Gain adaptation path300may be configured to perform a least mean squares algorithm that indicates the error between the gain of crx(n) with respect to ref(n) and a calculated gain g(n). Gain adaptation path300may also determine the gain of ref(n) with respect to crx(n) using the error as a metric and may accordingly adapt according to the error e(n). The LMS algorithm may be configured such that, for each sample, it adjusts based on the error and gain of the previous sample and may come to a steady state with little to no error. Once gain adaptation path300comes to the steady state with little to no error, the gain between ref(n) and crx(n) may be reasonably determined. In the present example, gain adaptation path301may be configured to execute the following equations to determine the gain between ref(n) and crx(n):
e(n)=[g(n)*ref(n)−crx(n)];
g(n)=[gainμ*e(n)*ref(n)]+g(n−1).

In the above cited equations, e(n) may represent the least mean squares error, g(n) may represent the gain of ref(n) with respect to crx(n) and gainμ may represent a scaling factor that may be used to adjust the time required for gain adaptation path300to reach steady state.

The implementation of the above equations may be seen inFIG. 3. For example, multiplier302amay receive ref(n) and may multiply ref(n) with g(n) to generate g(n)*ref(n) of the above equation, which may represent the magnitude of the reference signal multiplied by the determined gain. Following this multiplication, g(n)*ref(n) may be communicated to summer304aconfigured to determine the difference between g(n)*ref(n) and crx(n). The difference between g(n)*ref(n) and crx(n) may indicate the error e(n) between the calculated gain (g(n)) and the actual gain experienced by crx(n) with respect to ref(n). Following this difference calculation, e(n) may be communicated to multiplier302bwhere e(n) may be multiplied by ref(n) to render e(n)*ref(n) of the second equation listed above.

This product (e(n)*ref(n)) may be communicated to multiplier302cwhere it may be multiplied by gainμ. As mentioned above, gainμ may comprise a scaling factor that may adjust the time required for gain adaptation path300to reach a steady state. The larger gainμ may be, the faster gain adaptation path300may reach a steady state, however, it may also cause larger oscillations while reaching steady state. Therefore, the value of gainμ may be chosen with this trade off in mind. Following multiplier302c, (e)n*ref(n)*gainμ) may be communicated to summer304bwhere it may be summed with the previous value of the calculated gain (e.g., g(n−1)) to generate the current value of the calculated gain (e.g., g(n)). The calculated gain, g(n), may loop back to multiplier302aas a feedback to perform the above mentioned determinations and may also be output and communicated to loop gain compensator250as described with respect toFIG. 2.

As mentioned above, gain and delay module248may also include a delay adaptation path301configured to determine the delay (d(n)) between crx(n) and ref(n) such that d(n) may be communicated to delay adjustment module254(shown inFIG. 2) to accordingly adjust the delay of ref(n) to time align ref(n) with crx(n). Delay adaptation path301may be configured to execute the following equation to determine the delay between ref(n) and crx(n):
d(n)=[delμ*(ref(n−1)−ref(n))*e(n)]+d(n−1)

In the above equation, delμ may represent a scaling factor similar to gainμ, ref(n−1) may represent the magnitude of the previous sample of the reference signal, ref(n) may represent the magnitude of the current sample of the reference signal, e(n) may represent the error between crx(n) and ref(n) multiplied by g(n) as determined by gain adaptation path300. Finally, d(n−1) may represent the determined delay for the previous sample.

To implement the above delay equation, delay adaptation path301may include a summer310aconfigured to receive ref(n) and ref(n−1) and determine the difference between the two. This difference (ref(n−1)−ref(n)) may be communicated to multiplier312a. Multiplier312amay be configured to also receive error e(n) from summer304aof gain adaptation path300and may multiply e(n) by (ref(n−1)−ref(n)) as indicated by the delay adaptation equation above. Further, delay adaptation path301may include a multiplier312bconfigured to multiply [e(n)*(ref(n−1)−ref(n))] by delμ as also indicated by the delay adaptation equation. This product may then be communicated to a summer310bconfigured to receive the product and the delay of the previous sample (e.g., d(n−1)). Sumer310bmay add [(e(n)*(ref(−1)−ref(n)))*delμ] with [d(−1)] to produce the delay for the current sample (d(n)) as indicated by the delay equation above. This d(n) may be communicated to delay adjustment module254such that ref(n) may be time aligned with crx(n) according to d(n).

Therefore, in the present example, gain and delay module248may be configured to determine the gain of crx(n) with respect to ref(n) such that the gain error may be determined as described above. Additionally, gain and delay module248may be configured to determine the delay between crx(n) and ref(n) to better time align crx(n) and ref(n) such that a more accurate gain between the two may be determined. Additionally, gain and delay module248ofFIG. 3may be configured to communicate the determined e(n) to a interference detection module260ofFIG. 2(not expressly shown inFIG. 3) such that interference detection module260may determine whether a blocker is present based at least in part on e(n).

Modifications, additions or omissions may be made toFIG. 3without departing from the scope of the present disclosure. For example, in addition to gainμ and delμ, gain and delay module248may also include and error scaling factor that may be multiplied by the difference between (g(n)*ref(n)) and crx(n) to adjust the value of e(n). The scaling may be done to reduce ripples in steady state operations or to decrease the amount of time required to reach steady state operations.