Etching method, method of manufacturing semiconductor chip, and method of manufacturing article

An etching method according to an embodiment includes forming an uneven structure including a projection on a surface of a semiconductor substrate; forming a catalyst layer including a noble metal on the surface selectively at a top surface of the projection; and supplying an etchant to the catalyst layer to cause an etching of the semiconductor substrate with an assist from the noble metal as a catalyst.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2018-021849, filed Feb. 9, 2018, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to an etching method, a method of manufacturing a semiconductor chip, and a method of manufacturing an article.

BACKGROUND

Etching is known as a method of forming a hole and a groove in a semiconductor wafer.

As an etching method, for example, a method of plasma-etching a semiconductor wafer includes forming a mask layer on the semiconductor wafer, patterning the mask layer by laser scribing and using the patterned mask layer as an etching mask is known.

As another etching method, metal-assisted chemical etching (MacEtch) is known. The MacEtch is, for example, a method of etching a semiconductor substrate containing silicon using a noble metal as a catalyst.

DETAILED DESCRIPTION

An etching method according to the first embodiment comprises forming an uneven structure including a projection on a surface of a semiconductor substrate; forming a catalyst layer including a noble metal on the surface selectively at a top surface of the projection; and supplying an etchant to the catalyst layer to cause an etching of the semiconductor substrate with an assist from the noble, metal as a catalyst.

A method of manufacturing a semiconductor chip according to the second embodiment comprises etching a semiconductor wafer by the etching method according to the first embodiment to singulate the semiconductor wafer into semiconductor chips, the surface being a surface of the semiconductor wafer.

A method of manufacturing an article according to the third embodiment comprises etching the surface by the etching method according to the first embodiment.

Embodiments will be explained in detail below with reference to the accompanying drawings. Note that the same reference numerals denote constituent elements which achieve the same or similar functions throughout all the drawings, and a repetitive explanation will be omitted. In this specification, “micrograph” is scanning electron micrograph.

First, an etching method according to an embodiment will be described with reference toFIGS. 1 to 7.

In the etching method, first, a semiconductor substrate1is prepared as shown inFIG. 1.

At least a part of the surface of the semiconductor substrate1is made of a semiconductor. The semiconductor is, for example, selected from silicon (Si), germanium (Ge), semiconductor comprising compounds of group-III and group-V elements such as gallium arsenide (GaAs) and gallium nitride (GaN), silicon carbide (SiC), and the like. As one example, the semiconductor substrate1contains silicon. Note that the term “group” herein used is “a group” in the short-form periodic table.

The semiconductor substrate1is, for example, a semiconductor wafer. The semiconductor wafer can be doped with impurities, or semiconductor elements such as transistors or diodes can be formed on the semiconductor wafer. Also, the principal surface of the semiconductor wafer can be parallel to any crystal plane of the semiconductor.

Then, a first mask layer2is formed on the surface of the semiconductor substrate1, as shown inFIG. 1.

The first mask layer2is a layer for forming a projection (described later) on the surface of the semiconductor substrate1. The first mask layer2has one or more openings.

Any material can be used as the material of the first mask layer2, provided that the material can protect a region of the surface of the semiconductor substrate1which is covered with the first mask layer2from etching. Examples of the material include organic materials such as polyimide, a fluorine resin, a phenolic resin, an acrylic resin and a novolak resin.

The first mask layer2can be formed by, for example, the existing semiconductor processes. The first mask layer2made of an organic material can be formed by, for example, photolithography.

Then, the semiconductor substrate1is etched using the first mask layer2as an etching mask, as shown inFIG. 2.

When the semiconductor substrate1is etched, a projection3is formed on the surface of the semiconductor substrate1.

The etching is, for example, dry etching. The dry etching includes plasma etching using gas of SF6, CF4, C2F6, C3F8, CClF2, CCl4, PCl3, CBrF3, or the like.

The height h1of the projection3is preferably within a range of 0.001 μm to 1 μm, and more preferably within a range of 0.15 μm to 0.5 μm. If the height h1is too small, noble metal elements are diffused into the region of the semiconductor substrate1that is located right under a third mask layer4(described later) when a catalyst layer (described later) is formed. Therefore resulting in readily progress of etching in a direction crossing the thickness direction of the semiconductor substrate1. Thought the upper limit of the height h1is not particularly limited, the height h1is usually 10 μm or less.

Note that the “height h1” is a value obtained by the following method. First, an image of the section of the semiconductor substrate1including the projection3is picked up by a scanning electron microscope (SEM) under a magnification within a range of 10,000 to 100,000×. Then, the height of the projection3in the image is measured. Specifically, the height of the left sidewall of the projection3and that of the right sidewall thereof are measured. When the heights of the left and right sidewalls are the same, the height of one of the sidewalls is defined as “height h1.” When they are different, the height of a lower sidewall is defined as “height h1.”

Then, the first mask layer2is removed as shown inFIG. 3. Then, a third mask layer4is formed on the surface of the semiconductor substrate1as shown inFIG. 4.

The third mask layer4has an opening in a position corresponding to the projection3. For example, the dimensions and shape of the opening are equal to those of the top surface of the projection3. The third mask layer4has a top surface that is flush with or higher than the top surface of the projection3.

The third mask layer4is etching-resistant to an etchant for etching the semiconductor substrate1.

Any material can be used as the material of the third mask layer4. Examples of the material include organic materials such as polyimide, a fluorine resin, a phenolic resin, an acrylic resin and a novolak resin and inorganic materials such as silicon oxide and silicon nitride.

The third mask layer4can be formed by, for example, the existing semiconductor processes. The third mask layer4made of an organic material can be formed by, for example, photolithography. The third mask layer4made of an inorganic material can be formed by, for example, depositing an inorganic material layer by vapor phase deposition, forming a mask by photolithography and patterning the inorganic material layer by etching. Alternatively, the third mask layer4made of an inorganic material can be formed by oxidizing or nitriding of the surface region of the semiconductor substrate1, forming a mask by photolithography and patterning of the oxide or nitride layer by etching.

The thickness t3of the third mask layer4is preferably within a range of 0.001 μm to 10 μm, and more preferably within a range of 0.1 μm to 1 μm.

Note that the “thickness t3” is a value obtained by the following method. That is, the thickness t3of the third mask layer4is the distance from the top surface of the third mask layer4to the undersurface thereof in the image whose section is parallel to the direction of the thickness and is observed by the microscope.

The ratio t3/h1of the thickness t3of the third mask layer4to the height h1of the projection3is preferably 1 or more and more preferably 1.5 or more. When the ratio t3/h1is less than 1, a catalyst layer (described later) is formed on the sidewalls of the projection3as well as on the top surface thereof. The portion of the catalyst layer that is located on the sidewalls of the projection3is likely to inhibit the catalyst layer from moving in the thickness direction of the semiconductor substrate1during the process of etching the semiconductor substrate1. Thus make it difficult to make progress in etching. When the ratio t3/h1is 1 or more, the third mask Layer4can prevent the catalyst layer from adhering to the sidewalls of the projection3. Though the upper limit of the ratio t3/h1is not particularly limited, it is usually 5 or less.

The width of the opening of the third mask layer4(i.e., the width of the projection3) is preferably within a range of 0.3 μm to 80 μm, and more preferably within a range of 1 μm to 20 μm. If the projection3is too wide, it is likely that the number of semiconductor chips that can be produced from a single semiconductor substrate1will be reduced when the etching method is used to cut a semiconductor substrate into semiconductor chips. If the projection3is too narrow, an etchant (described later) cannot easily reach the surface of the semiconductor substrate1.

Subsequently, a catalyst layer6including a noble metal is formed on the top surface of the projection3as shown inFIG. 5. The catalyst layer6includes, for example, noble metal particles5. The noble metal is, for example, at least one metal selected from the group consisting of Au, Ag, Pt, Pd, Ru and Rh.

The thickness of the catalyst layer6is preferably within a range of 0.01 μm to 0.3 μm, and more preferably within a range of 0.05 μm to 0.2 μm. When the catalyst layer6is too thick, an etchant7(described later) cannot easily reach the semiconductor substrate1, thus making it difficult to make etching progress. When the catalyst layer6is too thin, the ratio of the total surface area of the noble metal particles5to the area to be etched is too small, thus making it difficult to make etching progress. Note that the thickness of the catalyst layer6is the distance from the top surface of the catalyst layer6to the top surface of the projection3in the image of a section that is parallel to the thickness direction of the catalyst layer6. The image is an image observed by the microscope.

The catalyst layer6covers at least a part of the top surface of the projection3. The catalyst layer6may include a discontinuous portion.

The noble metal particles5are preferably spherical. The noble metal particles5may be in any other shape such as a rod and a plate. The noble metal particles5serves as a catalyst for the oxidation reaction of the surface of a semiconductor that is in contact with the noble metal particles5.

The diameter d1of each of the noble metal particles5is preferably within a range of 0.001 μm to 1 μm, and more preferably within a range of 0.01 μm to 0.5 μm.

Note that the “diameter d1” is a value obtained by the following method. First, an image of the principal surface of the catalyst layer6is picked up by the scanning electron microscope (SEM) under a magnification within a range of 10,000 to 100,000×. Then, the area of each of the noble metal particles5is obtained from the image. Assuming that each of the noble metal particles5is spherical, the diameter of each of the noble metal particles5is obtained from the area. This diameter is defined as “diameter d1” of the noble metal particles5.

The catalyst layer6can be formed by electroplating, reduction plating, displacement plating or the like. The catalyst layer6can be formed by coating a dispersion containing the noble metal particles5, or vapor phase deposition such as evaporation and sputtering. Of these methods, the displacement plating is particularly preferable because the noble metal can be deposited directly and uniformly on the projection3. As one method of forming the catalyst layer6, the displacement plating will be described below.

For the deposition of a noble metal by the displacement plating, it is possible to use an aqueous solution of tetrachloroaurate (III) acid, a silver nitrate solution, or the like. Below is a description of an example of this process.

The displacement plating solution is, for example, a mixture of an aqueous solution of hydrogen tetrachloroaurate (III) tetrahydrate, and hydrofluoric acid. The hydrofluoric acid has a function of removing a native oxide film from the surface of the semiconductor substrate1.

When the semiconductor substrate1is immersed in the displacement plating solution, a native oxide film is removed from the surface of the semiconductor substrate1, and a noble metal, i.e. gold in this example, is deposited on the top surface of the projection3. Consequently, the catalyst layer6is obtained.

The concentration of hydrogen tetrachloroaurate (III) tetrahydrate in the displacement plating solution is preferably within a range of 0.0001 mol/L to 0.01 mol/L. Also, the concentration of hydrofluoric acid in the displacement plating solution is preferably within a range of 0.1 mol/L to 6.5 mol/L.

The displacement plating solution may further include a sulfur containing complexing agent. Alternatively, it may further include glycine and citric acid.

Then, an etchant7is supplied to the catalyst layer6as shown inFIG. 6. For example, the semiconductor substrate1on which the projection3, third mask layer4and catalyst layer6are formed is immersed in the etchant7. The etchant7includes, for example, a corrosive agent and an oxidizer. The etchant7may also include ammonium fluoride.

When the etchant7is brought into contact with the surface of the semiconductor substrate1, a portion of the surface to which the noble metal particles5are close is oxidized by the oxidizer and the oxide is dissolved away by the corrosive agent. As shown inFIG. 7, therefore, the etchant7etches the surface of the semiconductor substrate1in the vertical direction (i.e. the thickness direction described above) with an assist from the catalyst layer6as a catalyst.

The corrosive agent dissolves the oxide. The oxide is, for example, SiO2. The corrosive agent is, for example, hydrofluoric acid.

The concentration of hydrogen fluoride in the etchant7is preferably within a range of 0.4 mol/L to 20 mol/L, more preferably within a range of 0.8 mol/L to 16 mol/L, and most preferably within a range of 2 mol/L to 10 mol/L. When the concentration of hydrogen fluoride is too low, a high etching rate is difficult to achieve. When it is too high, controllability of etching in the processing direction (e.g. the thickness direction of the semiconductor substrate1) may lower.

The oxidizer in the etchant7can be selected from, for example, hydrogen peroxide, nitric acid, AgNO3, KAuCl4, HAuCl4, K2PtCl6, H2PtCl6, Fe(NO3)3, Ni(NO3)2, Mg(NO3)2, Na2S2O8, K2S2O8, KMnO4and K2Cr2O7. Hydrogen peroxide is favorable as the oxidizer because it neither forms any harmful byproduct nor contaminates a semiconductor element.

The concentration of the oxidizer such as hydrogen peroxide in the etchant7is preferably within a range of 0.2 mol/L to 8 mol/L, more preferably within a range of 0.5 mol/L to 5 mol/L, and most preferably within a range of 0.5 mol/L to 4 mol/L. When the concentration of oxidizer is too low, a high etching rate is difficult to achieve. When it is excessively high, excess side etching may occur.

Note that the foregoing etching method may generate needle-like residual portions8.

The needle-like residual portions8may be removed by, for example, at least one of the wet etching and dry etching. The etchant in the wet etching can be selected from a mixture of hydrofluoric acid, nitric acid and acetic acid, tetramethylammonium hydroxide (TMAH), KOH and the like. The dry etching includes plasma etching using gas of SF6, CF4, C2F6, C3F8, CClF2, CCl4, PCl3, CBrF3, or the like.

Note that the etchant7may be supplied to the catalyst layer6after the third mask layer4is removed.

According to the method shown inFIGS. 1 to 7, the semiconductor substrate1is etched as described above.

Incidentally, when a semiconductor substrate having no uneven structure including the foregoing projection is etched, porous residual portion tends to be generated. This will be described below.

In an etching method according to a comparative example, first, a structure including a semiconductor substrate1having a third mask layer4but no projection3is prepared as shown inFIG. 8.

Then, as shown inFIG. 9, the foregoing displacement plating is applied to the structure shown inFIG. 8to form a catalyst layer6on the surface of the semiconductor substrate1. The catalyst layer6includes noble metal particles5. The noble metal particles5include noble metal nanoparticles5aand noble metal particles5b. When the catalyst layer6is formed on the surface of the semiconductor substrate1, noble metal elements are diffused into the semiconductor substrate1. The portions of the semiconductor substrate1which include the diffused noble metal elements are defined as noble metal diffused portions9. The noble metal diffused portions9are formed in a portion located right under the third mask layer4as well as the portion of a surface region of the semiconductor substrate1which corresponds to an opening of the third mask layer4. At least a part of the noble metal particles5are also present in a portion located right under the third mask layer4.

Then, a structure shown inFIG. 9is etched as shown inFIG. 10. As the etching progresses, the noble metal particles5and the noble metal diffused portion9aof the noble metal diffused portions9which corresponds to the opening of the third mask layer4move in the thickness direction of the semiconductor substrate1. On the other hand, the noble metal diffused portion9bof the noble metal diffused portions9which is located right under the third mask layer4moves in a direction crossing the thickness direction as the etching progresses. As a result, a plurality of holes that extend in the direction crossing the thickness direction are formed in the portion of the surface region of the semiconductor substrate1which is located right under the third mask layer4.

As described above, when a semiconductor substrate having no uneven structure including a projection is etched, the porous residual portion tends to be generated.

On the other hand, according to the etching method described with reference toFIGS. 1 to 7, the porous residual portion would not be generated. The present inventors consider the reason for this as follows.

First, a structure shown inFIG. 11is obtained by the method described with reference toFIGS. 1 to 4.FIG. 11shows a semiconductor substrate1on which a projection3and a third mask layer4are formed.

Then, a structure shown inFIG. 12is obtained by the method described with reference toFIG. 5.FIG. 12shows a semiconductor substrate1on which a projection3, a third mask layer4and a catalyst layer6are formed. The catalyst layer6includes noble metal particles5. The noble metal particles5include noble metal nanoparticles5aand noble metal particles5b. Also, the semiconductor substrate1includes the noble metal diffused portion9described above.

The noble metal diffused portion9is formed in the portion of the surface region of the semiconductor substrate1which corresponds to the opening of the third mask layer4and is not easily formed in a portion located right under the third mask layer4. This is because the top surface of the projection3and the undersurface of the third mask layer4are fully separated from each other.

Then, when the structure shown inFIG. 12is etched by the method described with reference toFIGS. 6 and 7, a structure shown inFIG. 13is obtained. As the etching progresses, the catalyst layer6moves in the thickness direction of the semiconductor substrate1. Since the noble metal diffused portion9is hardly present in the portion of the semiconductor substrate1which is located right under the third mask layer4, etching does not easily progress in the portion.

Thus, a plurality of holes extending in a direction crossing the thickness direction in the semiconductor substrate1are harder to form in the etching method described with reference toFIGS. 1 to 7than in the etching method in the comparative example.

According to the etching method of the embodiment, therefore, the porous residual portion would not be generated.

Below is a description of another example of a method of forming an uneven structure including a projection3on the surface of the semiconductor substrate1.

First, as shown inFIG. 14, a semiconductor substrate1is prepared and a second mask layer10is formed on the surface of the semiconductor substrate1. The second mask layer10is a layer to form a semiconductor layer11(described later) on the surface of the semiconductor substrate1. The second mask layer10has at least one opening.

Any material can be used as the material of the second mask layer10, provided that the material is sufficiently resistant to the deposition process of the semiconductor layer11(described later).

The material of the second mask layer10is SiN, SiO2, Al or the like. The material of the second mask layer10may be the same as that of the foregoing third mask layer4.

Then, as shown inFIG. 15, a semiconductor layer11is formed on the region of the surface of the semiconductor substrate1at the opening of the second mask layer10. The semiconductor layer11is, for example, formed all over the opening of the second mask layer10. The semiconductor layer11corresponds to the foregoing projection3.

The semiconductor substrate11is made of, for example, a semiconductor. The semiconductor may be one as described with reference toFIG. 1. The material of the semiconductor11may be the same as that of the semiconductor substrate1and may be different therefrom if it can be etched under the etching conditions for etching the semiconductor substrate1.

The semiconductor substrate11can be formed by, for example, epitaxial growth. As one example, the semiconductor substrate11can be formed by epitaxial growth of silicon.

Then, as shown inFIG. 16, the second mask layer10is removed to form a third mask layer4. Note that the second mask layer10may not be removed and can be used as the third mask layer4.

Another example of a method of forming an uneven structure including a projection3on the surface of the semiconductor substrate1has been so far described.

The foregoing etching method can be used to manufacture a variety of articles. The etching method can also be used to form a recess or a through hole or to divide a structure such as a semiconductor wafer. For example, the etching method can be used to manufacture a semiconductor device.

An example of a method of manufacturing a semiconductor chip which includes singulating a semiconductor wafer into a plurality of semiconductor chips by etching the semiconductor wafer, will be described with reference toFIGS. 17 to 26.

First, a structure shown inFIGS. 17 and 18is prepared. This structure includes a semiconductor wafer12, a second mask layer10and a dicing sheet14. Semiconductor element regions13are formed on the surface of the semiconductor wafer12. The semiconductor element region13is a region in which semiconductor elements are formed. The second mask layer10covers the semiconductor regions13and serves to protect the semiconductor elements against damage. The dicing sheet11is adhered to a surface of the semiconductor wafer12, which is opposite to the surface on which the second mask layer10is formed.

Then, as shown inFIGS. 19 and 20, a semiconductor layer11is formed on the surface of the semiconductor wafer12by the method described with reference toFIG. 15.

Then, as shown inFIGS. 21 and 22, the second mask layer10is removed to form a third mask layer4by the method described with reference toFIG. 16.

Then, as shown inFIGS. 23 and 24, a catalyst layer6including noble metals is formed on the surface of the semiconductor wafer12by the method described with reference toFIG. 5.

Then, the structure shown inFIGS. 23 and 24is etched by the method described with reference toFIGS. 6 and 7to obtain the structure shown inFIGS. 25 and 26. The etching is performed until the bottom surface of a recess generated by the etching reaches the surface of the dicing sheet14.

As described above, the foregoing method makes it possible to obtain semiconductor chips15each including a semiconductor element region13as shown inFIGS. 25 and 26.

In this method, the shape of the upper surface of each semiconductor chip is not limited to a square or rectangle. For example, the upper surface shape of each semiconductor chip may also be a circle or hexagon. Furthermore, this method makes it possible to simultaneously form semiconductor chips having different upper surface shapes.

An example and a comparative example will be described below.

Example

A projection, a third mask layer and a catalyst layer were formed on a semiconductor wafer and the semiconductor wafer was etched by the following method. Then, whether the porous residual portion was generated or not was investigated.

In this method, the semiconductor wafer was singulated into semiconductor chips. This singulation was performed such that the volume of a portion to be removed from the semiconductor wafer was 5% of the entire volume of the semiconductor wafer.

Specifically, first, a first mask layer was formed on the surface of the semiconductor wafer. The first mask layer was formed by photolithography using photoresist. Openings were formed like a grid in the first mask layer, and the width of each of the openings was 1 μm.

Then, a projection was formed on the semiconductor wafer by dry etching using the first mask layer as an etching mask. The height of the projection was 0.2 μm.

Then, the first mask layer was removed, and a third mask layer was formed on the semiconductor wafer. The third mask layer had openings located at the position of the projection. The openings were formed such that its dimensions and shape were equal to those of the top surface of the projection. The third mask layer was also formed such that its top surface was flush with that of the projection.FIG. 27shows a result obtained by observing the semiconductor wafer on which the projection and the third mask layer are formed. The result was obtained by the scanning electron microscope.

FIG. 27is a micrograph showing a section of a semiconductor substrate on which a projection and a third mask layer are formed. As shown inFIG. 27, the top surface of the third mask layer and that of the projection are flush with each other.

Then, a plating solution A of 50 mL including an aqueous solution of hydrogen tetrachloroaurate (III) tetrahydrate and hydrofluoric acid was prepared.

Then, a semiconductor wafer on which projections and a third mask layer are formed was immersed in the plating solution A at room temperature for 60 seconds to form a catalyst layer on the top surface of the projections. The immersion was performed without rotating the semiconductor wafer.FIG. 28shows a result obtained by observing the semiconductor wafer on which the catalyst layer is formed. The result was obtained by the scanning electron microscope.FIG. 28is a micrograph showing a section of a structure obtained by forming a catalyst layer in the structure shown inFIG. 27.

Then, hydrofluoric acid of 27.5 mL, hydrogen peroxide of 8.6 mL and water of 63.9 mL were mixed to obtain an etchant of 100 mL. The semiconductor wafer on which the projection, third mask layer and catalyst layer were formed was immersed in the etchant at 25° C. for 30 minutes and etched.FIG. 29shows a result obtained by observing the etched semiconductor wafer by the scanning electron microscope.

FIG. 29is a micrograph showing a section of a structure obtained by etching the structure shown inFIG. 28. As shown inFIG. 29, according to the etching method of the above example, the porous residual portion was not generated.

Comparative Example

Except that the projection was not formed on a semiconductor wafer, a third mask layer and a catalyst layer were formed on a semiconductor substrate and the semiconductor substrate was etched by the same method as the etching method described in the foregoing example.

FIG. 30is a micrograph showing a section of a structure obtained by etching a semiconductor wafer having no uneven structure including a projection. As shown inFIG. 30, the porous residual portions of the semiconductor were generated.