Data storage device performing a scramble operation and operating method thereof

A data storage device includes a conversion block suitable for performing a scramble operation on write data, and generating random write data, wherein the scramble operation includes inversion/non-inversion processing and calculation processing based on a random pattern.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2014-0183329, filed on Dec. 18, 2014, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a data storage device and, more particularly, to a scramble operation of a data storage device.

2. Related Art

A semiconductor memory device may be used to store data. Semiconductor memory devices may be divided into nonvolatile and volatile memory devices.

The nonvolatile memory devices maintain data stored therein even though power is cut off. The nonvolatile memory devices include flash memory devices such as NAND flash or NOR flash, Ferroelectrics Random Access Memory (FeRAM), Phase-Change Random Access Memory (PCRAM), Magnetoresistive Random Access Memory (MRAM) or Resistive Random Access Memory (ReRAM).

Volatile memory devices fail to maintain data stored therein when power is cut off. Volatile memory devices include Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). Volatile memory devices are generally used as buffer memory devices, cache memory devices, or working memory devices in data processing systems, due to their relatively high processing speed.

SUMMARY

Various embodiments are directed to a data storage device and an operating method thereof, capable of maximizing scrambling effects by performing not only calculation processing using a random pattern but also inversion/non-inversion processing.

In an embodiment, a data storage device may include: a conversion block suitable for performing a scramble operation on write data, and generating random write data, wherein the scramble operation includes inversion/non-inversion processing and calculation processing based on a random pattern.

In an embodiment, a data storage device may include: a conversion block suitable for outputting first random write data by performing a logic operation on write data and a random pattern; and a nonvolatile memory apparatus, the nonvolatile memory apparatus including: an inversion unit suitable for outputting second random write data by inverting/non-inverting the first random write data; and a target memory block suitable for storing the second random write data.

In an embodiment, an operating method of a data storage device may include: generating random write data by performing a scramble operation on write data, the generating including: performing inversion/non-inversion processing; and performing calculation processing based on a random pattern.

In an embodiment, a data storage device may include: a conversion block suitable for performing a scramble operation on write data in response to a flag signal, and generating random write data; a memory apparatus including a plurality of memory blocks, suitable for performing a write operation to write the random write data in a target memory block; and a processor suitable for providing the flag signal to the conversion block based on flag information corresponding to the target memory block.

In an embodiment, an operating method of a data storage device may include: outputting a flag signal based on flag information corresponding to a target memory block; generating random write data by performing a scramble operation on write data in response to the flag signal; and performing a write operation to write the random write data in the target memory block.

DETAILED DESCRIPTION

Hereinafter, a data storage device and an operating method thereof according to the present invention will be described with reference to the accompanying drawings through exemplary embodiments of the present invention. The present invention may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to describe the present invention in detail to the extent that a person skilled in the art to which the invention pertains can enforce the technical concepts of the present invention.

It is to be understood that embodiments of the present invention are not limited to the particulars shown in the drawings, that the drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated to more clearly depict certain features of the invention. While particular terminology is used, it is to be appreciated that the terminology used is for describing particular embodiments only and is not intended to limit the scope of the present invention.

FIG. 1is a block diagram illustrating a data storage device10in accordance with an embodiment of the present invention.

Referring toFIG. 1, the data storage device10may be configured to store data provided from a host device (not shown), in response to a write request from the host device. Also, the data storage device10may be configured to provide stored data to the host device in response to a read request from the host device. The host device may include an electronic device capable of processing data, such as a computer, a digital camera or a mobile phone. The data storage device10may operate by being embedded in the host device, or may be fabricated separately and operate when being electrically coupled to the host device.

The data storage device10may be configured by a Personal Computer Memory Card International Association (PCMCIA) card, a compact flash (CF) card, a smart media card, a memory stick, a multimedia card (MMC), an embedded MMC (eMMC), a reduced-size multimedia card (RS-MMC) and a micro-size version of MMC (MMC-micro), a secure digital (SD) card, a mini secure digital (mini-SD) and a micro secure digital (micro-SD), a universal flash storage (UFS), or a solid state drive (SSD).

The data storage device10may include a controller100and a memory apparatus200.

The controller100may include a processor110, a memory120, and a conversion block130.

The processor110may control overall operations of the data storage device10. The processor110may control a write operation or a read operation of the memory apparatus200in response to a write request or a read request from the host device. The processor110may generate commands for controlling the operations of the memory apparatus200and provide the generated commands to the memory apparatus200. The processor110may drive a software program for controlling the operation of the data storage device10, on the memory120.

The processor110may control inversion/non-inversion processing performed in a scramble operation or a descramble operation of the conversion block130based on flag information125. The processor110may refer to a flag corresponding to a target memory block of the memory apparatus200when the scramble operation or the descramble operation of the conversion block130is performed. The target memory block may be a memory block in which scrambled data are to be written, when the scramble operation of the conversion block130is performed. The target memory block may be a memory block from which read data to be descrambled are read, when the descramble operation of the conversion block130is performed. The processor110may provide a flag signal for controlling the inversion/non-inversion processing of the conversion block130, to the conversion block130based on the flag information125.

The processor110may set the flag information125. The set flag information125may be stored in the memory120. The processor110may set flags corresponding to the memory blocks included in the memory apparatus200, as the flag information125, based on respective erase counts of the memory blocks. At each time of erasing a memory block and updating an erase count, the processor110may newly reset a flag corresponding to the corresponding memory block. The flag corresponding to the target memory block may be constantly retained until the erase count of the target memory block is updated and, accordingly, the processor110may control the conversion block130to consistently perform the scramble operation and the descramble operation on the same original data.

The memory120may serve as a working memory, a buffer memory, or a cache memory of the processor110. The memory120may serve as the working memory that stores various program data and software programs driven by the processor110. The memory120may serve as the buffer memory that buffers data transmitted between the host device and the memory apparatus200. The memory120may serve as the cache memory that temporarily stores cache data.

The conversion block130may perform the scramble operation on original data to be stored in the memory apparatus200, and provide the scrambled data to the memory apparatus200. As the memory apparatus200stores the data scrambled by the conversion block130, deformation of data due to a disturbance phenomenon among memory cells and degradation of memory cells due to repetitive storage of a specific data pattern may be suppressed. The conversion block130may recover the original data by performing the descramble operation on the scrambled data read from the memory apparatus200.

The scramble operation of the conversion block130on the original data may include inversion/non-inversion processing and calculation processing using a random pattern. The conversion block130may perform the scramble operation on the original data by the inversion/non-inversion processing and the calculation processing using the random pattern. In the embodiment, as the conversion block130performs not only the calculation processing using the random pattern but also the inversion/non-inversion processing, the scrambling effect on the original data may be maximized. The conversion block130may perform the inversion/non-inversion processing in response to the flag signal.

The descramble operation of the conversion block130on the scrambled data read from the memory apparatus200may include inversion/non-inversion processing and calculation processing using a random pattern. The conversion block130may perform the descramble operation on the scrambled data by the inversion/non-inversion processing and the calculation processing using the random pattern. The descramble operation for recovering the original data may be performed by an inverse calculation of the scramble operation performed on the corresponding original data.

The data storage device10ofFIG. 1may include the conversion block130, which is configured to perform both the scramble operation and the descramble operation, as described above. According to an embodiment, the data storage device10may be implemented with a scrambler, which performs a scramble operation, and a descrambler, which performs a descramble operation.

The memory apparatus200may include a nonvolatile memory apparatus. For example, the memory apparatus200may be a flash memory apparatus such as a NAND flash or a NOR flash, a ferroelectric random access memory (FeRAM), a phase change random access memory (PCRAM), a magnetic random access memory (MRAM) or a resistive random access memory (ReRAM). The memory apparatus200may store data under the control of the processor110. While it is illustrated inFIG. 1that the data storage device10includes one memory apparatus200, it is to be noted that the number of memory apparatuses included in the data storage device10is not specifically limited.

Referring toFIG. 2, the memory apparatus200may include a control logic210, an interface unit220, an address decoder230, a data input/output unit240, and a memory region250.

The control logic210may control the overall operations of the memory apparatus200such as a write operation, a read operation and an erase operation, in response to the commands provided from the controller100.

The interface unit220may exchange various control signals including commands and addresses and data with the controller100. The interface unit220may transmit the various control signals and the data inputted thereto, to internal units of the memory apparatus200.

The address decoder230may decode row addresses and column addresses transmitted thereto. The address decoder230may control word lines WL to be selectively driven in response to the decoded row addresses. The address decoder230may control the data input/output unit240such that bit lines BL are selectively driven in response to the decoded column addresses.

The data input/output unit240may transmit the data transmitted from the interface unit220to the memory region250through the bit lines BL. The data input/output unit240may transmit the data read through the bit lines BL from the memory region250, to the interface unit220.

The memory region250may be electrically coupled with the address decoder230through the word lines WL, and may be electrically coupled with the data input/output unit240through the bit lines BL. The memory region250may include a memory cell array of, for example, a three-dimensional structure.

The memory region250may include a plurality of memory cells which are respectively disposed at areas where the word lines WL and the bit lines BL cross each other. The memory cells may be classified according to the number of data bits stored in each memory cell. For example, the memory cells may be classified into single level cells, each of which stores 1 bit, and multi-level cells, each of which stores at least 2 bits.

The memory region250may include a plurality of memory blocks B1to Bk. Each of the memory blocks B1to Bk may include a plurality of pages, for example, P1to Pn. The pages P1to Pn may be classified according to the data stored in memory cells when the memory cells are multi-level cells. For example, when memory cells are multi-level cells, each storing 2 bits, the pages P1to Pn may be classified into least significant bit (LSB) pages and most significant bit (MSB) pages.

The memory apparatus200may perform the erase operation in units of memory blocks. The memory apparatus200may perform the write operation or the read operation in the unit of a page.

FIG. 3is a block diagram illustrating an exemplary embodiment of the conversion block130shown inFIG. 1.

Referring toFIG. 3, the conversion block130_1may receive original data as first write data WD1, perform a scramble operation on the first write data WD1, and output the scrambled first write data WD1as random write data RDWD. The random write data RDWD may be written in the memory apparatus200, and be read as random read data RDRD from the memory apparatus200. The conversion block130_1may receive the random read data RDRD read from the memory apparatus200, perform a descramble operation on the random read data RDRD, and output the descrambled random read data RDRD as second read data RD2.

The conversion block130_1may include a random pattern generation unit131, an inversion unit132, and a calculation unit133.

The random pattern generation unit131may receive seed data SEED, and output a random pattern RDP based on the seed data SEED. In the scramble operation, the seed data SEED may be selected in response to an address of a target page of a target memory block in which the random write data RDWD are to be written. In the descramble operation, the seed data SEED may be selected in response to an address of a target page of a target memory block from which the random read data RDRD are read. The random pattern generation unit131may receive the same seed data SEED in the scramble operation and the descramble operation for the same target page and, accordingly, output the same random pattern RDP. The random pattern generation unit131may be configured by, for example, a linear feedback shift register.

In the scramble operation, the inversion unit132may receive the first write data WD1, invert/non-invert the first write data WD1based on a flag signal FGS, and output second write data WD2to the calculation unit133. When the flag signal FGS is enabled, the inversion unit132may invert the first write data WD1and output the inverted first write data WD1as the second write data WD2. When the flag signal FGS is disabled, the inversion unit132may non-invert the first write data WD1and output the non-inverted first write data WD1as the second write data WD2.

In the descramble operation, the inversion unit132may receive first read data RD1from the calculation unit133, invert/non-invert the first read data RD1based on the flag signal FGS, and output the second read data RD2. When the flag signal FGS is enabled, the inversion unit132may invert the first read data RD1and output the inverted first read data RD1as the second read data RD2. The inversion unit132may non-invert the first read data RD1based on the disabled flag signal FGS, and output the non-inverted first read data RD1as the second read data RD2.

In the scramble operation, the calculation unit133may perform a logic operation on the second write data WD2and the random pattern RDP, and output the random write data RDWD. In the descramble operation, the calculation unit133may perform a logic operation on the random read data RDRD and the random pattern RDP, and output the first read data RD1. The logic operation may be, for example, an exclusive OR logic operation.

FIG. 4shows the flags F1set in correspondence to the memory blocks B1to Bk and a table T1explaining the inversion/non-inversion processing of the conversion block130_1shown inFIG. 3according to the flags F1.

Referring toFIG. 4, the processor110may set the flags F1corresponding to the memory blocks B1to Bk Included in the memory apparatus200. The processor110may set the flags F1corresponding to the memory blocks B1to Bk, based on the erase counts of the respective memory blocks B1to Bk. According to an embodiment, the processor110may set a flag of 1 bit, corresponding to each of the memory blocks B1to Bk. For example, the processor110may set a remainder when dividing the erase count of a memory block by 2, as a flag corresponding to the memory block.

At each erasing of the memory block and updating of the erase count, the processor110may reset the flag corresponding to the memory block. The flag corresponding to the target memory block may be retained until the erase count of the target memory block is updated and, accordingly, the processor110may control the conversion block130to consistently perform the scramble operation and the descramble operation on the same original data. Since a corresponding flag is reset each time a memory block is erased, even though the conversion block130_1receives the same original data before and after the erase of the target memory block, the inversion/non-inversion processing may be performed differently in response to the flag. Hence, the scrambling effect may be maximized.

In the scramble operation of the conversion block130_1, the processor110may refer to the set value of the flag corresponding to the target memory block in which the random write data RDWD are to be written. In the descramble operation of the conversion block130_1, the processor110may refer to the set value of the flag corresponding to the target memory block from which the random read data RDRD are read. The processor110may transmit the flag signal FGS to the conversion block130_1in response to the referred flag. For example, the processor110may disable the flag signal FGS when the referred flag is “0”. For example, the processor110may enable the flag signal FGS when the referred flag is “1”.

In the scramble operation and descramble operation, the inversion unit132may invert/non-invert the first write data WD1and the first read data RD1inputted thereto, based on the flag signal FGS. For example, the inversion unit132may non-invert the first write data WD1and the first read data RD1inputted thereto, when the flag signal FGS is disabled. For example, the inversion unit132may invert the first write data WD1and the first read data RD1inputted thereto, when the flag signal FGS is enabled.

In summary, when the flag corresponding to the target memory block is set to “0”, the first write data WD1and the first read data RD1inputted to the inversion unit132may be non-inverted. When the flag corresponding to the target memory block is set to “1”, the first write data WD1and the first read data RD1inputted to the inversion unit132may be inverted.

FIG. 5is a diagram explaining the scramble operation of the conversion block130_1shown inFIG. 3.FIG. 6is a diagram explaining the descramble operation of the conversion block130_1shown inFIG. 3.

Referring toFIGS. 5 and 6, it is assumed that a flag corresponding to the first memory block B1of the memory apparatus200is set to “1” and a flag corresponding to the second memory block B2of the memory apparatus200is set to “0”. InFIGS. 5 and 6, it is assumed that inversion/non-inversion processing is performed in response to a flag set to 1 bit as described above with reference toFIG. 4.

Hereinbelow, the scramble operation of the conversion block130_1will be described in detail with reference toFIGS. 3 to 5.

In the upper example11and the lower example12, the conversion block130_1may receive original data, that is, the first write data WD1, scramble the first write data WD1, and output the random write data RDWD. A target memory block of the memory apparatus200in which the random write data RDWD are to be written may be the first memory block B1in the upper example11and the second memory block B2in the lower example12.

In the upper example11, the inversion unit132may receive the first write data WD1. The inversion unit132may receive the enabled flag signal FGS based on the flag “1” corresponding to the first memory block B1. The inversion unit132may invert the first write data WD1based on the flag signal FGS, and output the inverted first write data WD1as the second write data WD2. The random pattern generation unit131may output the random pattern RDP. The calculation unit133may perform a logic operation, for example, an exclusive OR logic operation, on the second write data WD2and the random pattern RDP, and output the random write data RDWD. The outputted random write data RDWD may be transmitted to the memory apparatus200, and be written in the first memory block B1.

In the lower example12, the inversion unit132may receive the first write data WD1. The inversion unit132may receive the disabled flag signal FGS based on the flag “0” corresponding to the second memory block B2. The inversion unit132may non-invert the first write data WD1based on the flag signal FGS, and output the non-inverted first write data WD1as the second write data WD2. The random pattern generation unit131may output the random pattern RDP. The calculation unit133may perform a logic operation, for example, an exclusive OR logic operation, on the second write data WD2and the random pattern RDP, and output the random write data RDWD. The outputted random write data RDWD may be transmitted to the memory apparatus200, and be written in the second memory block B2.

Hereinbelow, the descramble operation of the conversion block130_1will be described in detail with reference toFIGS. 3, 4 and 6.

In the upper example21and the lower example22, the conversion block130_1may receive scrambled data, that is, the random read data RDRD, descramble the random read data RDRD, and output original data, that is, the second read data RD2. A target memory block of the memory apparatus200from which the random read data RDRD are read may be the first memory block B1in the upper example21and the second memory block B2in the lower example22.

In the upper example21, the calculation unit133may receive the random read data RDRD. The random pattern generation unit131may output the random pattern RDP. The calculation unit133may perform a logic operation, for example, an exclusive OR logic operation, on the random read data RDRD and the random pattern RDP, and output the first read data RD1. The inversion unit132may receive the enabled flag signal FGS based on the flag “1” corresponding to the first memory block B1. The inversion unit132may invert the first read data RD1based on the flag signal FGS, and output the inverted first read data RD1as the second read data RD2.

In the lower example22, the inversion unit132may receive the disabled flag signal FGS based on the flag “0” corresponding to the second memory block B2. The inversion unit132may non-invert the first read data RD1based on the flag signal FGS, and output the non-inverted first read data RD1as the second read data RD2.

FIG. 7shows flags F2set in correspondence to the memory blocks B1to Bk and a table T2explaining the inversion/non-inversion processing of the conversion block130_1shown inFIG. 3according to the flags F2.

ReferringFIG. 7, the processor110may set the flag F2of 2 bits corresponding to each of the memory blocks B1to Bk. For example, the processor110may set a remainder when dividing the erase count of a memory block by 4, as a flag corresponding to the memory block.

A least significant bit in the 2-bit flag F2corresponding to a certain memory block may correspond to a first page group of the memory block, and a most significant bit may correspond to a second page group of the memory block. For example, when pages are divided into LSB pages and MSB pages, the least significant bit in the 2-bit flag corresponding to the memory block may correspond to the LSB pages, and the most significant bit may correspond to the MSB pages.

In the scramble operation of the conversion block130_1, the processor110may refer to a set value of a flag corresponding to a target page of a target memory block in which the random write data RDWD are to be written. In the descramble operation of the conversion block130_1, the processor110may refer to a set value of a flag corresponding to a target memory block from which the random read data RDRD are read. For example, when the target page is an LSB page, the processor110may refer to the least significant bit of the flag corresponding to the target memory block. For example, when the target page is an MSB page, the processor110may refer to the most significant bit of the flag corresponding to the target memory block.

The processor110may transmit the flag signal FGS to the conversion block130_1in response to the referred flag. The inversion unit132may perform inversion/non-inversion processing based on the flag signal FGS.

Summarizing, when the flag corresponding to the target memory block is set to “00”, the first write data WD1and the first read data RD1inputted to the inversion unit132may be non-inverted regardless of whether they are LSB data or MSB data. When the flag corresponding to the target memory block is set to “01”, the first write data WD1and the first read data RD1inputted to the inversion unit132may be inverted only when they are LSB data. When the flag corresponding to the target memory block is set to “10”, the first write data WD1and the first read data RD1inputted to the inversion unit132may be inverted only when they are MSB data. When the flag corresponding to the target memory block is set to “11”, the first write data WD1and the first read data RD1inputted to the inversion unit132may be inverted regardless of whether they are LSB data or MSB data.

FIG. 8is a diagram explaining the scramble operation of the conversion block130_1shown inFIG. 3.

Referring toFIG. 8, it is assumed that a flag corresponding to the first memory block B1of the memory apparatus200is set to “01”. InFIG. 8, it is assumed that inversion/non-inversion processing is performed in response to a flag set to 2 bits as described above with reference toFIG. 7.

Hereinbelow, the scramble operation of the conversion block130_1will be described in detail with reference toFIGS. 3, 7 and 8.

In the upper Example31and the lower Example32, the conversion block130_1may receive original data, that is, the first write data WD1, scramble the first write data WD1, and output the random write data RDWD. In the upper Example31, a target memory block of the memory apparatus200in which the random write data RDWD are to be written may be the first memory block B1, and a target page may be an LSB page. In the lower Example32, a target memory block may be the first memory block B1, and a target page may be an MSB page.

In the upper Example31, the inversion unit132may receive the first write data WD1. The inversion unit132may receive the enabled flag signal FGS based on the least significant bit “1” of the flag corresponding to the first memory block B1. The inversion unit132may invert the first write data WD1based on the flag signal FGS, and output the inverted first write data WD1as the second write data WD2. The random pattern generation unit131may output the random pattern RDP. The calculation unit133may perform a logic operation, for example, an exclusive OR logic operation, on the second write data WD2and the random pattern RDP, and output the random write data RDWD. The outputted random write data RDWD may be transmitted to the memory apparatus200, and be written in the LSB page of the first memory block B1.

In the lower Example32, the inversion unit132may receive the disabled flag signal FGS based on the most significant bit “0” of the flag corresponding to the first memory block B1. The inversion unit132may non-invert the first write data WD1based on the flag signal FGS, and output the non-inverted first write data WD1as the second write data WD2. The random pattern generation unit131may output the random pattern RDP. The calculation unit133may perform a logic operation, for example, an exclusive OR logic operation, on the second write data WD2and the random pattern RDP, and output the random write data RDWD. The outputted random write data RDWD may be transmitted to the memory apparatus200, and be written in the MSB page of the first memory block B1.

According to an embodiment, the processor110may set a flag of i bits in correspondence to each of the memory blocks B1to Bk, where i is a natural number greater than 1. For example, the processor110may set a remainder when dividing the erase count of a memory block by 2i, as a flag corresponding to the memory block. In an i-bit flag corresponding to a certain memory block, respective bits may correspond to the different page groups of the corresponding memory block. In the scramble operation and the descramble operation of the conversion block130, the processor110may refer to a bit corresponding to a target page in the i-bit flag corresponding to the target memory block, and enable/disable the flag signal FGS.

FIG. 9is a flow chart explaining an operating method of the data storage device10shown inFIG. 1.

Hereinbelow, the operating method of the data storage device10will be described in detail with reference toFIGS. 1 and 9.

Referring toFIG. 9, at step S110, the processor110may control an erase operation on a memory block of the memory apparatus200.

At step S120, the processor110may update an erase count corresponding to the erased memory block.

At step S130, the processor110may reset a flag corresponding to the erased memory block based on the updated erase count.

FIG. 10is a flow chart explaining an operating method of the conversion block130_1shown inFIG. 3.

Hereinbelow, the scramble operation of the conversion block130_1will be described in detail with reference toFIGS. 3 and 10.

Referring toFIG. 10, at step S210, the conversion block130_1may receive the first write data WD1.

At step S220, the inversion unit132may generate the second write data WD2through inversion/non-inversion processing for the first write data WD1, based on the flag signal FGS.

At step S230, the calculation unit133may generate the random write data RDWD by performing a logic operation on the second write data WD2and the random pattern RDP.

At step S240, the conversion block130_1may output the random write data RDWD.

FIG. 11is a flow chart explaining an operating method of the conversion block130_1shown inFIG. 3.

Hereinbelow, the descramble operation of the conversion block130_1will be described in detail with reference toFIGS. 3 and 11.

Referring toFIG. 11, at step S310, the conversion block130_1may receive the random read data RDRD.

At step S320, the calculation unit133may generate the first read data RD1by performing a logic operation on the random read data RDRD and the random pattern RDP.

At step S330, the inversion unit132may generate the second read data RD2through inversion/non-inversion processing for the first read data RD1based on the flag signal FGS.

At step S340, the conversion block130_1may output the second read data RD2.

FIG. 12is a block diagram illustrating an exemplary embodiment of the conversion block130shown inFIG. 1.

Referring toFIG. 12, the conversion block130_2may receive write data WD, perform a scramble operation on the write data WD, and output the scrambled write data WD as random write data RDWD. The random write data RDWD may be written in the memory apparatus200, and be read as random read data RDRD from the memory apparatus200. The conversion block130_2may receive the random read data RDRD read from the memory apparatus200, perform a descramble operation on the random read data RDRD, and output the descrambled random read data RDRD as read data RD.

The conversion block130_2may include a random pattern generation unit231, a calculation unit233, and an inversion unit234. Unlike the conversion block130_1ofFIG. 3, in the conversion block130_2, the inversion unit234may invert a first random pattern RDP1in response to a flag signal FGS.

The random pattern generation unit231may receive a seed data SEED, and output the first random pattern RDP1based on the seed data SEED. The random pattern generation unit231may be configured and operate in substantially the same way as the random pattern generation unit131ofFIG. 3.

The inversion unit234may receive the first random pattern RDP1, invert/non-invert the first random pattern RDP1based on the flag signal FGS, and output a second random pattern RDP2. The inversion unit234may invert the first random pattern RDP1when the flag signal FGS is enabled, and output the inverted first random pattern RDP1as the second random pattern RDP2. The inversion unit234may non-invert the first random pattern RDP1when the flag signal FGS is disabled, and output the non-inverted first random pattern RDP1as the second random pattern RDP2.

In the scramble operation, the calculation unit233may perform a logic operation on the write data WD and the second random pattern RDP2, and output the random write data RDWD. In the descramble operation, the calculation unit233may perform a logic operation on the random read data RDRD and the second random pattern RDP2, and output the read data RD. The logic operation of the calculation unit233may be, for example, an exclusive OR logic operation.

FIG. 13is a diagram explaining the scramble operation of the conversion block130_2shown inFIG. 12.FIG. 14is a diagram explaining the descramble operation of the conversion block130_2shown inFIG. 12.

Referring toFIGS. 13 and 14, it is assumed that a flag corresponding to the first memory block B1of the memory apparatus200is set to “01”.

InFIGS. 13 and 14, it is assumed that inversion/non-inversion processing is performed in response to a flag set to 2 bits as described above with reference toFIG. 7. That is, when a target page is an LSB page, the processor110may output the flag signal FGS by referring to the least significant bit of the flag corresponding to a target memory block. When a target page is an MSB page, the processor110may output the flag signal FGS by referring to the most significant bit of the flag corresponding to a target memory block.

Hereinbelow, the scramble operation of the conversion block130_2will be described in detail with reference toFIGS. 12 and 13.

In the upper Example41and the lower Example42, the conversion block130_2may receive the write data WD, scramble the write data WD, and output the random write data RDWD. A target memory block of the memory apparatus200in which the random write data RDWD are to be written may be the first memory block B1. A target page may be an LSB page in the upper Example41and an MSB page in the lower Example42.

In the upper Example41, the calculation unit233may receive the write data WD. The random pattern generation unit231may output the first random pattern RDP1. The inversion unit234may receive the enabled flag signal FGS based on the least significant bit “1” of the flag corresponding to the first memory block B1. The inversion unit234may invert the first random pattern RDP1based on the flag signal FGS, and output the inverted first random pattern RDP1as the second random pattern RDP2. The calculation unit233may perform a logic operation, for example, an exclusive OR logic operation, on the write data WD and the second random pattern RDP2, and output the random write data RDWD. The outputted random write data RDWD may be transmitted to the memory apparatus200, and be written in the LSB page of the first memory block B1.

In the lower Example42, the inversion unit234may receive the disabled flag signal FGS based on the most significant bit “0” of the flag corresponding to the first memory block B1. The inversion unit234may non-invert the first random pattern RDP1based on the flag signal FGS, and output the non-inverted first random pattern RDP1as the second random pattern RDP2. The calculation unit233may perform a logic operation, for example, an exclusive OR logic operation, on the write data WD and the second random pattern RDP2, and output the random write data RDWD. The outputted random write data RDWD may be transmitted to the memory apparatus200, and be written in the MSB page of the first memory block B1.

Hereinbelow, the descramble operation of the conversion block130_2will be described in detail with reference toFIGS. 12 and 14.

In the upper Example51and the lower Example52, the conversion block130_2may receive scrambled data, that is, the random read data RDRD, descramble the random read data RDRD, and output original data, that is, the read data RD. A target memory block of the memory apparatus200from which the random read data RDRD are read may be the first memory block B1. A target page may be an LSB page in the upper Example51and an MSB page in the lower Example52.

In the upper Example51, the calculation unit233may receive the random read data RDRD. The random pattern generation unit231may output the first random pattern RDP1. The inversion unit234may receive the enabled flag signal FGS based on the least significant bit “1” of the flag corresponding to the first memory block B1. The inversion unit234may invert the first random pattern RDP1based on the flag signal FGS, and output the inverted first random pattern RDP1as the second random pattern RDP2. The calculation unit233may perform a logic operation, for example, an exclusive OR logic operation, on the random read data RDRD and the second random pattern RDP2, and output the read data RD.

In the lower Example52, the inversion unit234may receive the disabled flag signal FGS based on the most significant bit “0” of the flag corresponding to the first memory block B1. The inversion unit234may non-invert the first random pattern RDP1based on the flag signal FGS, and output the non-inverted first random pattern RDP1as the second random pattern RDP2. The calculation unit233may perform a logic operation, for example, an exclusive OR logic operation, on the random read data RDRD and the second random pattern RDP2, and output the read data RD.

FIG. 15is a flow chart explaining an operating method of the conversion block130_2shown inFIG. 12.

Hereinbelow, the scramble operation of the conversion block130_2will be described in detail with reference toFIGS. 12 and 15.

Referring toFIG. 15, at step S410, the conversion block130_2may receive the write data WD.

At step S420, the inversion unit234may generate the second random pattern RDP2through inversion/non-inversion processing for the first random pattern RDP1based on the flag signal FGS.

At step S430, the calculation unit233may generate the random write data RDWD by performing a logic operation on the write data WD and the second random pattern RDP2.

At step S440, the conversion block130_2may output the random write data RDWD.

FIG. 16is a flow chart explaining an operating method of the conversion block130_2shown inFIG. 12.

Hereinbelow, the descramble operation of the conversion block130_2will be described in detail with reference toFIGS. 12 and 16.

Referring toFIG. 16, at step S510, the conversion block130_2may receive the random read data RDRD.

At step S520, the inversion unit234may generate the second random pattern RDP2through inversion/non-inversion processing for the first random pattern RDP1based on the flag signal FGS.

At step S530, the calculation unit233may generate the read data RD by performing a logic operation on the random read data RDRD and the second random pattern RDP2.

At step S540, the conversion block130_2may output the read data RD.

FIG. 17is a block diagram illustrating an exemplary embodiment of the conversion block130shown inFIG. 1.

Referring toFIG. 17, the conversion block130_3may receive write data WD, perform a scramble operation on the write data WD, and output the scrambled write data WD as second random write data RDWD2. The second random write data RDWD2may be written in the memory apparatus200, and be read as first random read data RDRD1from the memory apparatus200. The conversion block130_3may receive the first random read data RDRD1read from the memory apparatus200, perform a descramble operation on the first random read data RDRD1, and output the descrambled first random read data RDRD1as read data RD.

The conversion block130_3may include a random pattern generation unit331, a calculation unit333, and an inversion unit335.

The random pattern generation unit331may receive a seed data SEED, and output a random pattern RDP based on the seed data SEED. The random pattern generation unit331may be configured and operate in substantially the same way as the random pattern generation unit131ofFIG. 3.

In the scramble operation, the calculation unit333may perform a logic operation on the write data WD and the random pattern RDP, and output a first random write data RDWD1. In the descramble operation, the calculation unit333may perform a logic operation on a second random read data RDRD2and the random pattern RDP, and output the read data RD. The logic operation of the calculation unit333may be, for example, an exclusive OR logic operation.

In the scramble operation, the inversion unit335may receive the first random write data RDWD1, invert/non-invert the first random write data RDWD1based on the flag signal FGS, and output the second random write data RDWD2. The inversion unit335may invert the first random write data RDWD1when the flag signal FGS is enabled, and output the inverted first random write data RDWD1as the second random write data RDWD2. The inversion unit335may non-invert the first random write data RDWD1when the flag signal FGS is disabled, and output the non-inverted first random write data RDWD1as the second random write data RDWD2.

In the descramble operation, the inversion unit335may receive the first random read data RDRD1, invert/non-invert the first random read data RDRD1based on the flag signal FGS, and output the second random read data RDRD2. The inversion unit335may invert the first random read data RDRD1when the flag signal FGS is enabled, and output the inverted first random read data RDRD1as the second random read data RDRD2. The inversion unit335may non-invert the first random read data RDRD1when the flag signal FGS is disabled, and output the non-inverted first random read data RDRD1as the second random read data RDRD2.

FIG. 18is a diagram explaining the scramble operation of the conversion block130_3shown inFIG. 17.FIG. 19is a diagram explaining the descramble operation of the conversion block130_3shown inFIG. 17.

Referring toFIGS. 18 and 19, it is assumed that a flag corresponding to the first memory block B1of the memory apparatus200is set to “01”. InFIGS. 18 and 19, it is assumed that inversion/non-inversion processing is performed in response to a flag set to 2 bits as described above with reference toFIG. 7.

Hereinbelow, the scramble operation of the conversion block130_3will be described in detail with reference toFIGS. 17 and 18.

In the upper Example61and the lower Example62, the conversion block130_3may receive the write data WD, scramble the write data WD, and output the second random write data RDWD2. A target memory block of the memory apparatus200in which the second random write data RDWD2are to be written may be the first memory block B1. A target page may be an LSB page in the upper Example61and an MSB page in the lower Example62.

In the upper Example61, the calculation unit333may receive the write data WD. The random pattern generation unit331may output the random pattern RDP. The calculation unit333may perform a logic operation, for example, an exclusive OR logic operation, on the write data WD and the random pattern RDP, and output the first random write data RDWD1. The inversion unit335may receive the enabled flag signal FGS based on the least significant bit “1” of the flag corresponding to the first memory block B1. The inversion unit335may invert the first random write data RDWD1based on the flag signal FGS, and output the inverted first random write data RDWD1as the second random write data RDWD2. The outputted second random write data RDWD2may be transmitted to the memory apparatus200, and be written in the LSB page of the first memory block B1.

In the lower Example62, the inversion unit335may receive the disabled flag signal FGS based on the most significant bit “0” of the flag corresponding to the first memory block B1. The inversion unit335may non-invert the first random write data RDWD1based on the flag signal FGS, and output the non-inverted first random write data RDWD1as the second random write data RDWD2. The outputted second random write data RDWD2may be transmitted to the memory apparatus200, and be written in the MSB page of the first memory block B1.

Hereinbelow, the descramble operation of the conversion block130_3will be described in detail with reference toFIGS. 17 and 19.

In the upper Example71and the lower Example72, the conversion block130_3may receive scrambled data, that is, the first random read data RDRD1, descramble the first random read data RDRD1, and output original data, that is, the read data RD. A target memory block of the memory apparatus200from which the first random read data RDRD1are read may be the first memory block B1. A target page may be an LSB page in the upper Example71and an MSB page in the lower Example72.

In the upper Example71, the inversion unit335may receive the first random read data RDRD1. The inversion unit335may receive the enabled flag signal FGS based on the least significant bit “1” of the flag corresponding to the first memory block B1. The inversion unit335may invert the first random read data RDRD1based on the flag signal FGS, and output the inverted first random read data RDRD1as the second random read data RDRD2. The random pattern generation unit331may output the random pattern RDP. The calculation unit333may perform a logic operation, for example, an exclusive OR logic operation, on the second random read data RDRD2and the random pattern RDP, and output the read data RD.

In the lower Example72, the inversion unit335may receive the disabled flag signal FGS based on the most significant bit “0” of the flag corresponding to the first memory block B1. The inversion unit335may non-invert the first random read data RDRD1based on the flag signal FGS, and output the non-inverted first random read data RDRD1as the second random read data RDRD2. The calculation unit333may perform a logic operation, for example, an exclusive OR logic operation, on the second random read data RDRD2and the random pattern RDP, and output the read data RD.

FIG. 20is a flow chart explaining an operating method of the conversion block130_3shown inFIG. 17.

Hereinbelow, the scramble operation of the conversion block130_3will be described in detail with reference toFIGS. 17 and 20.

Referring toFIG. 20, at step S610, the conversion block130_3may receive the write data WD.

At step S620, the calculation unit333may generate the first random write data RDWD1by performing a logic operation on the write data WD and the random pattern RDP.

At step S630, the inversion unit335may generate the second random write data RDWD2through inversion/non-inversion processing for the first random write data RDWD1based on the flag signal FGS.

At step S640, the conversion block130_3may output the second random write data RDWD2.

FIG. 21is a flow chart explaining an operating method of the conversion block130_3shown inFIG. 17.

Hereinbelow, the descramble operation of the conversion block130_3will be described in detail with reference toFIGS. 17 and 21.

Referring toFIG. 21, at step S710, the conversion block130_3may receive the first random read data RDRD1.

At step S720, the inversion unit335may generate the second random read data RDRD2through inversion/non-inversion processing for the first random read data RDRD1based on the flag signal FGS.

At step S730, the calculation unit333may generate the read data RD by performing a logic operation on the second random read data RDRD2and the random pattern RDP.

At step S740, the conversion block130_3may output the read data RD.

FIG. 22is a block diagram illustrating a data storage device in accordance with an embodiment.

Referring toFIG. 22, the data storage device20may be configured in substantially the same way as the data storage device10ofFIG. 1except that an inversion unit410is included not in a conversion block330but in a memory apparatus400.

The data storage device20may include a controller300and the memory apparatus400.

The controller300may include a processor310, a memory320, and the conversion block330. The processor310may transmit a control signal for controlling inversion/non-inversion processing of the inversion unit410, to the memory apparatus400, based on flag information325. For example, the processor310may transmit the control signal to the memory apparatus400, by including the control signal in a write or read command.

The conversion block330may include a random pattern generation unit336and a calculation unit337. The random pattern generation unit336and the calculation unit337may be configured and operate in substantially the same way as the random pattern generation unit331and the calculation unit333ofFIG. 17.

The memory apparatus400may include the inversion unit410. The inversion unit410may perform the inversion/non-inversion processing under the control of the processor310. The inversion unit410may be configured and operate in substantially the same way as the inversion unit335ofFIG. 17.

For reference, inFIG. 22, the calculation unit337of the conversion block330may perform a logic operation, for example, an exclusive OR logic operation, on write data and random pattern inputted from the random pattern generation unit336, and output first random write data to the inversion unit410of the memory apparatus400during a scramble operation. During a descramble operation, the inversion unit410of the memory apparatus400may invert/non-invert first random read data based on a flag signal, and output second random read data to the calculation unit337of the conversion block330in the controller300during a descramble operation.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments are examples only. Accordingly, the data storage device and the operating method thereof described herein should not be limited based on the described embodiments.