Distributed test control architecture

The invention includes an integrated circuit. The integrated circuit includes a test controller, at least one logic unit controller, and a test bus connected between the test controller and the logic unit controller. A design for test feature is connected to the logic unit controller. Moreover, a logic unit can be connected to the design for test feature.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention includes error detection/correction and fault detection/recovery. More particularly, the invention includes digital logic testing through a reduction in the number of global test control lines.

2. Background Information

An integrated circuit or “chip” is a microelectronic semiconductor device having many interconnected transistors and other components. Chips may be fabricated on a small rectangle cut from a silicon wafer. The small size of these circuits allows high speed, low power dissipation, and reduced manufacturing cost compared with board-level integration.

The first integrated circuits contained only a few transistors. Small Scale Integration (SSI) brought circuits containing transistors numbered in the tens. Later, Medium Scale Integration (MSI) contained hundreds of transistors and Large Scale Integration (LSI) contained thousands of transistors. At present Very Large Scale Integration (VLSI) circuit chips are composed of hundreds of thousands of logic elements or memory cells. Digital VLSI integrated circuits may contain anything from one to millions of logic gates—inverters, gates, flip-flops, and multiplexors on a few square millimeters.

Part of producing a scaleable VLSI chip includes testing and debugging the chip. Debugging is an attempt to determine the cause of any malfunction symptoms detected by testing. Circuitry may be built into an integrated circuit to assist in the test, maintenance, and support of an assembled circuit. Hardware features, known as design for test (DFT) features or resources, may be incorporated into a chip to aid in testing and debugging.

Determining the cause of a malfunction or other problem may be achieved by using a testing machine to send a simulated signal from a debug pin residing on the perimeter of the chip to a logic element within the chip so as to trigger a response bit (0 or 1) from that logic element. On a clock signal, an instruction may cause a snapshot or “scan” to be taken of this triggered response bit by a DFT feature. On the next clock signal, and as part of that same instruction, the scan information bit may be shifted one bit “out” towards a serial output the chip to a second perimeter pin so that the scan bit may be compared to an expected response. If this triggered response or “scanout” varies from the expected response, then that particular logic element may be a cause of the noted problem.

To adequately debug a chip, it may be necessary to view a sampled state of hundreds of chip-internal signals within a space of minutes. Conventionally, a first debugging technique may be used to isolate a probable bug location from a million transistors to a group of a few hundred transistors. Then, a second debugging technique may be used to rapidly find the exact transistor failure point from the grouped few hundred transistors. Chips may have redundant transistors in them such that, once a transistor failure point is located, the transistor may be turned off as part of chip production while a redundant transistor may then similarly be turned on.

To isolate a probable bug location from a million transistors to a group of a few hundred transistors, an integrated circuit chip may be designed to include internal read-only test points. These test points (or scanout “cells”) generally are scattered throughout the integrated circuit chip. When chained together to form a distributed shift register, scanout cells produce parallel data that provides observability of selected nodes during functional testing during normal operation of the chip.

U.S. Pat. No. 5,253,255 teaches a centralized control mechanism that employs two global test control lines for each design for test (DFT) feature. Here, sequentially activating the snapshot and the shift with signals requires two global speed critical signals that require close timing tolerances between the two signals.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1illustrates platform100of the invention having chip102disposed on support structure104. Platform100may be any structure having electronic components, such as chip102. For example, platform100may be a computer or computer system. Moreover, platform100may be a printed circuit board (PCB). By way of background, a computer or other electronic system might be built from several PCBs, such as processor, memory, graphics controller, and disk controller. These boards might all plug into a motherboard or backplane or be connected by a ribbon cable.

Chip102may be referred to as a processor or integrated circuit and may be thought of as a microelectronic semiconductor device having many interconnected transistors and other components. Platform100may also include memory controller106, Peripheral Component Interconnect (PCI) bridge108, and chip110, each communicatively coupled through processor bus112.

Memory controller106may be coupled to memory chips114. A controller may be thought of as that part of platform100which allows platform100to use certain kinds of devices. Thus, memory controller106may be thought of as that part of platform100which allows platform100to use memory chips114. Memory chips114may any device that can hold data in machine-readable format.

PCI is a standard to connect external or peripheral devices to a personal computer. The PCI standard entitled PCI to PCI Bridge Architecture Specification (Rev. 1.1, PCI Special Interest Group, Portland, Oreg., 1998) may be implemented as a mezzanine or a bridge, such as PCI bridge108. Here, PCI bridge108may include buffers to decouple chip102from relatively slow peripherals and to allow the peripherals to operate asynchronously. PCI bridge108may be coupled to external devices through controller122over PCI bus124. These external devices may be input devices such as keyboard116, mouse118, and modem120.

Chip110may be an integrated circuit that is similar to chip102. Chip102may include bus interface unit (BIU)126and test controller128. BIU126may operate as an input/output port to communicated signals between processor bus112and chip102. Test controller128may be any device that asserts test instructions to design for test (DFT) features, where DFT may be design and hardware features incorporated into chip102to aid in manufacturing and debugging.

Also coupled to platform100may be tester130. Tester130may be a VLSI tester that communicates test instructions to test controller128over bus132. Bus132may be thought of as a test and maintenance bus used as part of the interface design to access chip102. Institute of Electrical and Electronics Engineers (IEEE) standard 1149.1, entitled Test Access Port and Boundary-Scan Architecture, is an internationally recognized design standard specifying product design and test protocols. Particularly, IEEE 1149.1 may specify the interface design to access a chip for testing purposes. In one embodiment, bus132meets the five-pin requirement of IEEE standard 1149.1. Moreover, under IEEE 1149.1, a test access port (TAP) may be an example of test controller128.

FIG. 2illustrates chip200. Chip200may include logic units202,204,206,208,210, and212, each of which may deal with basic operations of a computer system. For example, logic unit202may be a floating point unit (FPU), logic unit204may be an arithmetic logic unit (ALU), and logic212may be a memory logic. Each logic unit may be coupled to bus interface unit214through logic unit controllers216,218,220,222,224, and226as shown. These controllers local to the logic units of chip200may be positioned very close to their respective logic unit. Moreover, bus interface unit (BIU)214may be similar to BIU126ofFIG. 1.

Clock generator227may be a core clock that is connected between each logic unit controller and BIU214. Clock or clock generator227may produce a signal which may be distributed over clock lines within chip200in a tree like structure to the logic units202,204,206,208,210, and212. Each clock signal of a given clock pulse may need to reach its destination within a timing window for events within chip200to be synchronized. Timing skew may be thought of the variation between the arrival moment of a first signal as compared to the arrival moment of one or more other signals at the same or different logic unit. Controllers may be placed within chip200to control this timing skew. These deskew (DS) controllers may include a whole host of logic elements that aid in receiving, processing, and retransmitting signals such as clock signals and instructions to the logic units so as to synchronize the arrival of all instructions to their associated logic unit. In other words, DS controllers may aid in minimizing any timing skew between the signals. Logic unit controllers216,218,220,222,224, and226may be DS controllers. As will be discussed below, the invention takes advantage of logic unit controllers216–226to receive, process, and retransmit testing signals to reduce the number of global test control lines.

Part of producing a working chip includes testing and debugging that chip. Debugging is an attempt to determine the cause of any malfunction symptoms detected by testing. Circuitry may be built into an integrated circuit to assist in the test, maintenance, and support of an assembled circuit. Hardware features, known as design for test (DFT) features, may be incorporated into a chip to aid in testing and debugging.

Each logic unit within chip200may be coupled to cells chained together to form a register. For example, logic208may be coupled to register228having cells230,232,234, and236. Logic212may be coupled to register238having cells240,242,244,246,248, and250. Cells230–236and240–250may be examples of DFT features.

Chip200may additionally include test controller252and tester254. Test controller252may be viewed as an integrated test controller when residing within chip200. Included within test controller252may be an instruction register (IR) and a test access port finite state machine (TAP FSM) as described in IEEE 1149.1. Test controller252and tester254may be similar to test controller128and tester130ofFIG. 1, respectively.

FIG. 3illustrates chip300. Chip300may be a conventional modification of chip200ofFIG. 2. Conventionally, one global test control line is required to run between test controller252and a DFT feature for each type of instruction signal. For example, to transmit a load signal and a test signal from ITC252and register238ofFIG. 3, chip300may employ global test control lines302and304, respectively. In a similar way, lines306and308may run between ITC252and register228. In other words, for a scanout process, each DFT feature conventionally may employ two global test control lines. For a different type of testing process, each design for test Feature conventionally may employ three, four, five or more global test control lines.

Chips conventionally include fifty to one hundred global test control lines to transmit information to anywhere from 5,200 DFT features to 49,000 DFT features. These global test control lines may limit chip designers in the placement and arrangement of the control lines and logical units on chip300by taking up valuable space on chip300. More restrictively, the timing of the signals distributed by each of these global test control lines is critical. As noted below, the invention may reduce the number of global test control lines to nineteen (for example, one bus having nineteen lines) to transmit that same information to the design for test Features of a chip.

FIG. 4illustrates chip400of the invention. As can be readily seen, chip400may be a modification of chip200ofFIG. 2. Included with chip400may be internal test bus402disposed between ITC252and logic unit controller226and internal test bus404disposed between ITC252and DS controller222. Chip400may also include additional internal test buses (not shown) disposed between ITC252and each logic unit controller within chip400.

Each internal test bus (ITB) of chip400may be adapted to pass test instruction signals as a test instruction packet from ITC252to a logic unit controller. Although the bits of these signals may travel over different lines, these different lines may be within a single internal test bus having a single routing path between ITC252and a logic unit controller. Moreover, these test instruction signals may travel according to a clock that is internal to tester254rather than the core clock that is internal to chip400, here clock227. For these and other reasons, timing is not critical with respect to signals routed within an internal test bus of the invention.

To transmit a test information packet in parallel, each internal test bus of chip400may include n number of lines such that
n=a+log2i(500)

where

a=number of ancillary transmission bits, and

log2i=number of instruction bits.

Ancillary transmission bits may be those supporting bits that may needed to accompany the instruction bits. For a given distributed test control architecture compliant with IEEE 1149.1, the number of ancillary transmission bits may be a constant. The number of instruction bits (log2i) may be thought of as a bit stream of zeros and ones. Moreover, the number of instruction bits (log2i) may represent the number of unique testing tasks that are desired to be performed within the collective of logic unit controllers (e.g.,222and226) of chip400. For example, where the number of instruction bits equals eight (8=log2256), the test instruction packet may include up to two hundred and fifty six (256) unique testing task signals. The instruction bits may be disposed within an IEEE 1149.1 instruction register content.

In one embodiment, the information transmitted over internal test bus402may include a shift signal and a load signal. In another embodiment, the information transmitted over internal test bus402may include a one-bit clock signal and the following five components representing eighteen bits:

(ii) partially encoded, relevant states of a test access port finite state machine (TAP FSM) (4 bits);

(v) counter value from a Wave Shaper (4 bits).

Component (i) may be thought of the number of instruction bits (log2i) and components (ii), (iii), (iv), and (v) may be thought of as ancillary transmission bits (a). Accordingly, from equation 500 above,
19=(1+4+1+1+4)+log2256  (500).
These nineteen bits of information may travel as a test information packet. Where the test instruction packet is encoded, the logic unit controller may include components that decode the test instruction packet.

Not all the states of the test access port finite state machine (TAP FSM) need be transmitted over a test bus (402,404) of chip400. This may be true where the state in question is not relevant to control DFT logic internal to chip400. In one embodiment, the relevant states of TAP FSM under IEEE 1149.1 include the following six states: test-logic-reset (tlr), run-test/idle (rti), capture-down register (capDR), shift-DR (shiftDR), update-DR (updtDR), and dead (the remaining eleven states). Accordingly, in one embodiment of the invention, a subset of all the states of a test access port finite state machine are encoded into three bits. In another embodiment, individual bits may be allocated for test-logic-reset (tlr) and run-test/idle (rti) and the residual (remainder) states (capDR, shiftDR, updtDR, and dead) are allocated among two bits.

On receiving a test instruction packet, a logic unit controller may locally generate whatever testing signals are needed for the desired testing operation. For example, on receiving a test instruction packet having a shift signal and a load signal, logic unit controller226may process the test instruction packet to locally generate a shift signal and a load signal. Logic unit controller226may then pass these two signals to register238over the relatively short distance of distributed test line406and distributed test line408, respectively.

Under the conventional method ofFIG. 3, a shift signal and a load signal each travel separately over its own global test control line between the ITC252and register238. The independent travel of these and other test signals over a relatively great distance requires tight or critical control over the timing of these signals. In contrast, the invention transmits these signals as an instruction bundle or packet between the ITC252and logic unit controller226so as to eliminate the number of global test control lines and the requirement for critical timing.

The invention may be employed as a method to control at least one DFT feature, such as register238ofFIG. 4. A test information packet may first be generated in a test controller of an integrated circuit. The test information packet may then be transmitted to at least one logic unit controller over a test bus coupled between the test controller and the at least one logic unit controller. The test information packet may then be processed within the at least one logic unit controller to generate at least one test control signal. The at least one test control signal may be transmitted to the at least one DFT feature coupled to the logic unit controller. A logic unit coupled to the at least one DFT feature may be interacted with based on the at least one test control signal.

The distributed test control scheme of the invention works towards reducing the number of global test control lines, relax routing constraints on the test control lines, and add greater flexibility in the physical placement of the test controller and test control logic. This may translate to lower silicon area and reduced design effort (cost, efficiency, quality, reliability, and timeliness). Moreover, the distributed test control scheme of the invention is scalable and flexible; that is to say, the distributed test control scheme may include the ability to add support for new test features late in the design cycle and implement fixes with relatively small impact on schedule.

The exemplary embodiments described herein are provided merely to illustrate the principles of the invention and should not be construed as limiting the scope of the subject matter of the terms of the claimed invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. Moreover, the principles of the invention may be applied to achieve the advantages described herein and to achieve other advantages or to satisfy other objectives, as well.