Symmetrical center tap inductor structure

An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation ring surrounding the coil. In some cases, the inductor structure can include a return line of conductive material positioned on the center line.

FIELD OF THE INVENTION

One or more embodiments disclosed within this specification relate to integrated circuits (ICs). More particularly, one or more embodiments relate to a center tap inductor structure implemented within an IC.

BACKGROUND

The frequency of signals associated with integrated circuits (ICs), whether generated within the IC or exchanged with devices external to the IC, has steadily increased over time. As IC signals reach radio frequency (RF) ranges exceeding a gigahertz, it becomes viable to implement inductor structures within ICs. Implementing an inductor structure within an IC, as opposed to using an external inductor device, typically reduces the manufacturing and implementation costs of the system requiring the inductor. IC inductors can be implemented within a variety of RF circuits such as, for example, low noise amplifiers (LNAs), voltage controlled oscillators (VCOs), input or output matching structures, power amplifiers, and the like. Many of these RF circuits, such as certain VCO architectures, can be implemented as differential circuits that rely on circuit and/or device symmetry to provide maximum circuit performance.

Although IC inductors are advantageous in many respects, IC inductors introduce various non-idealities not present with external or discrete inductors. For example, an IC inductor is typically surrounded by other semiconductor devices that can generate noise. As IC devices reside over a common substrate material that is conductive, signals and noise generated by an IC device can be coupled into an IC inductor built over the common substrate material. Although IC inductors are typically built within one or more metal interconnect layers that reside farthest from the substrate layer, finite parasitic capacitances exist between the substrate layer and the metal interconnect layer(s). These parasitic capacitances can couple signals between the IC inductor and the substrate layer. Further, eddy currents induced within the substrate layer by an IC inductor can generate losses that reduce the quality factor, or so called “Q,” of the IC inductor.

Other non-idealities relate to the ability of interconnect lines routed in the vicinity of the IC inductor, particularly large ground and power supply lines, to couple signals both capacitively and inductively to the inductor. In addition, inductive coupling resulting from neighboring metal lines can alter the inductive value and self resonance of an IC inductor.

Each of the non-idealities described can interfere with the implementation of an IC inductor as a consistent and reproducible element whose parameters are independent of the IC environment within which the IC inductor resides.

SUMMARY

One or more embodiments disclosed within this specification relate to integrated circuits (ICs) and, more particularly, to an inductor structure implemented within an IC.

An embodiment disclosed within this specification can include an inductor structure implemented within a semiconductor IC. The inductor structure can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil opposite the center terminal. The inductor structure can include a return line of conductive material coupled to the coil and located in a different conductive layer of the IC than the coil. The return line can be positioned on the centerline.

The inductor structure also can include an isolation ring. The isolation ring can surround the coil and can be separated from the coil by approximately a constant and predetermined distance. In one aspect, the isolation ring can have a first end and a second end separated by a predetermined distance forming an opening. For example, the first end and the second end of the isolation ring can be equidistant from the centerline.

In another aspect, the isolation ring can be coupled to the return line at a location opposite the center terminal. When in a circuit in which the inductor structure is implemented, the isolation ring can be coupled, at a midpoint of a length of the isolation ring, to a virtual AC ground of the circuit.

In another aspect, no supply voltage interconnect and no ground interconnect can be located within the isolation ring. Further, no supply voltage interconnect and no ground interconnect can be permitted to cross the centerline within a predetermined distance of the isolation ring.

In a further aspect, a length of the return line can be approximately equal to a diameter of the coil at the centerline.

Another embodiment can include an inductor structure implemented within a semiconductor IC. The inductor structure can include a coil of conductive material having a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil opposite the center terminal. The inductor structure also can include an isolation ring surrounding the coil and separated from the coil by approximately a constant and predetermined distance. The isolation ring can include a first end and a second end separated by a predetermined distance forming an opening in the isolation ring.

The inductor structure also can include a return line of conductive material located in different conductive layer of the IC than the coil. The return line can be positioned on the centerline substantially within the coil. In one aspect, a length of the return line can be approximately equal to a diameter of the coil at the centerline.

The first end and the second end of the isolation ring can be equidistant from the centerline. The first end and the second end further can be located closer to the center terminal than either of the differential terminals of the coil. In another aspect, the isolation ring can be coupled to an end of the return line that is opposite the center terminal.

The isolation ring further can be coupled, at a midpoint of a length of the isolation ring, to a virtual AC ground when in a circuit in which the inductor structure is implemented.

In another aspect, no supply voltage interconnect and no ground interconnect can be located within the isolation ring. Further, no supply voltage interconnect and no ground interconnect can be permitted to cross the centerline within a predetermined distance of the isolation ring.

Another embodiment can include an inductor structure implemented within a semiconductor IC. The inductor structure can include a plurality of coils of conductive material including a center terminal located at a midpoint of a length of the plurality of coils. Each of the plurality of coils can be symmetrical with respect to a centerline bisecting the center terminal. The plurality of coils can include a first differential terminal and a second differential terminal each located at an end of the plurality of coils. The inductor structure can include an isolation ring surrounding the plurality of coils and separated from the plurality of coils by approximately a constant and predetermined distance. The isolation ring can include a first end and a second end separated by a predetermined distance forming an opening in the isolation ring.

The first end and the second end of the isolation ring can be equidistant from the centerline. The first end and the second end also can be located external to a portion of the plurality of coils opposite the center terminal, the first differential terminal, and the second differential terminal.

The center terminal can be located on a same side of the plurality of coils as, and between, the first and second differential terminals.

When in a circuit in which the inductor structure is implemented, the isolation ring can be coupled, at a midpoint of a length of the isolation ring, to a virtual AC ground of the circuit.

In another aspect, no supply voltage interconnect and no ground interconnect are located within the isolation ring. Further, no supply voltage interconnect and no ground interconnect can be permitted to cross the centerline within a predetermined distance of the isolation ring.

DETAILED DESCRIPTION

While the specification concludes with claims defining features of one or more embodiments that are regarded as novel, it is believed that the one or more embodiments will be better understood from a consideration of the description in conjunction with the drawings. As required, one or more detailed embodiments are disclosed within this specification. It should be appreciated, however, that the one or more embodiments are merely exemplary of the inventive arrangements. Therefore, specific structural and functional details disclosed within this specification are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the one or more embodiments in virtually any appropriately detailed structure. Further, the terms and phrases used herein are not intended to be limiting, but rather to provide an understandable description of the one or more embodiments disclosed herein.

One or more embodiments disclosed within this specification relate to integrated circuits (ICs) and, more particularly, to an inductor structure for use within an IC. In accordance with one or more embodiments disclosed herein, a center tap inductor structure can be implemented that includes a return line within the inductor structure. The inductor structure can be implemented with a single turn coil constructed symmetrically about a center line that bisects the coil. When implemented within a high frequency differential circuit, the center tap of the inductor structure can receive a current used to bias the high frequency differential circuit. The return line can be routed along the centerline of the single turn coil and used as a return path for the bias current to ground. In this manner, the bias current flowing within the circuit is returned to ground along the centerline of the inductor structure.

An isolation ring can be configured to surround the single turn coil of the inductor structure. The isolation ring can be implemented with an opening located where the isolation ring intersects the centerline. The opening prevents currents induced within the isolation ring, by the single turn coil coupling to the isolation ring, from circularly flowing within the isolation ring. Routing the return line along the centerline of the inductor and breaking the current path in the isolation ring produces an inductor structure with greater differential symmetry. In addition, the parameters of the inductor structure demonstrate less variability when exposed to the effects of inductive and capacitive coupling.

FIG. 1is a circuit diagram illustrating an exemplary circuit100implemented with a center tap inductor in accordance with an embodiment disclosed within this specification. More particularly, circuit100can be a radio frequency (RF) differential circuit including a single turn center tap inductor.FIG. 1is presented to illustrate electrical properties of a physical inductor structure and the non-idealities that are typically associated with an IC center tap inductor when implemented within an RF differential circuit such as circuit100. It should be appreciated, however, thatFIG. 1, being a circuit diagram, is not intended to convey or illustrate physical location, e.g., layout, of the various components shown. As used within this specification, a “layout” or “IC layout,” can refer to a representation of an IC in terms of planar geometric shapes which correspond to the design masks that pattern the metal layers, the oxide regions, the diffusion areas, or other layers that form devices of the IC.

Circuit100represents a circuit architecture for a voltage controlled oscillator (VCO) within an IC. As shown, circuit100can include an inductor105, a capacitor110, a P-type metal oxide semiconductor (PMOS) current source115, and an N-type metal oxide semiconductor devices (NMOSs)120and125. Within circuit100, inductor105and capacitor110are coupled in parallel across nodes145and150to form an L-C tank circuit. The L-C tank circuit determines an oscillation frequency of the VCO implemented with circuit100. The oscillation frequency of circuit100is a product of the value of inductor105and the value of capacitor110of the L-C tank. Within circuit100, inductor105can be implemented as a center tap inductor. More particularly, inductor105can be implemented as a symmetrical single turn center tap inductor. As used within this specification, a “center tap” or “center terminal,” refers to a coupling point made at a midpoint in a length of windings or coils of an inductor. In addition, inductor105can be a symmetrical center tap inductor, wherein inductor105is physically symmetrical on either side of a centerline that bisects a center terminal140.

Although a continuous series of windings or coils, a center tap inductor can be modeled as two discrete inductors of equal value coupled in series. For example, inFIG. 1, inductor105is represented as two inductors coupled in series, denoted as inductors105aand105b. By implementing inductor105as a symmetrical center tap inductor coupled at the inductor midpoint, matching between inductors105aand105bcan be improved. As circuit100is a differential circuit, improving the matching between inductors105aand105bcan improve the differential symmetry and performance of circuit100.

Center terminal140is coupled to a drain of PMOS current source115. A source of PMOS current source115is coupled to a voltage source130having a voltage potential of VDD. A gate of PMOS current source115receives a bias voltage, denoted as Vbias. The voltage potential of Vbiascan determine a quantity of bias current, denoted as Ibias, sourced by PMOS current source115to center terminal140. Through center terminal140, the current Ibiascan flow into inductor105.

Nodes145and150form the differential output of circuit100. As such, the differential output voltage of circuit100is equal to the voltage difference between signals Vout+and Vout−. A drain of NMOS120and a gate of NMOS125are coupled to node145. A drain of NMOS125and a gate of NMOS120are coupled to node150. A source of each of NMOSs120and125is coupled to node135and to a negative voltage potential of source130that is typically the ground potential of circuit100. NMOSs120and125, taken together, form a cross-coupled differential pair containing a positive feedback loop. The positive feedback loop has a closed path from the gate of NMOS120to the gate of NMOS125via the drain of NMOS120and back to the gate of NMOS120via the drain of NMOS125.

In order to induce oscillation within circuit100, a current Ibiascan be injected into inductor105at center terminal140. The current Ibiasestablishes a predetermined operating point within each of NMOSs120and125. Properly designed to meet a set of oscillation conditions, for example, a gain of greater than one in the positive feedback loop of NMOSs120and125, NMOSs120and125in conjunction with inductor105and capacitor110can combine to form an oscillator. In one or more embodiments, capacitor110can be implemented with a varactor, i.e., a voltage controlled variable capacitor, in order to vary the oscillation frequency of circuit100across a predetermined frequency range.

As current Ibiasflows though inductor105, current Ibiasis divided between inductors105aand105b. For simplicity of understanding how current Ibiasflows between inductors105aand105b, current Ibiascan be divided into component currents of a common mode current, denoted as ICM, and a differential current, denoted as Idiff. The current ICMcan be considered a quantity of common DC current flowing symmetrically within each of inductors105aand105b.

In illustration, in a balanced condition of circuit100, i.e., (Vout+)−(Vout−)=zero volts, the current sourced through each of NMOSs120and125is approximately equal to one half of the current Ibias. Accordingly, the current flowing through each of inductors105aand105bis approximately equal to one half of the current Ibias. The current value of one half Ibiascan be considered the common mode current sourced through each of NMOSs120and125. As circuit100oscillates, the current flowing through NMOS120increases as current flowing through NMOS125decreases. Then, in succession, the current flowing through NMOS120decreases as the current flowing through NMOS125increases. Thus, the current flowing through inductor105aincreases as the current flowing through inductor105bdecreases. Then, in succession, the current flowing through inductor105adecreases as the current flowing through inductor105bincreases.

This directional change in the current flow through inductors105aand105bcan be considered the AC differential current, Idiff, flowing through inductor105. As inductor105is a center tap, single turn inductor and, accordingly, inductors105aand105bare physically symmetrical to each other, the current Idiffrepresents an asymmetric flow of current through inductors105aand105b. For example, PMOS current source115of circuit100can be biased to generate a current Ibiasequal to approximately 100 mA. In that case, the current ICMflowing through each of inductors105aand105bis equal to approximately 50 mA.

At a subsequent time T1, as circuit100oscillates, approximately 75 mA can be flowing out of inductor105ato node145and approximately 25 mA can be flowing out of inductor105bto node150. In that case, a current Idiffof approximately 25 mA can be considered to be flowing from node150to node145through inductor105. Although illustrated inFIG. 1with an arrow indicating a single direction for current Idiff, current Idiffcan flow in either direction through inductor105. The distinction between common mode current and differential current is significant to the performance of inductor105as the current ICMflows symmetrically on either side of center terminal140though inductor105while the current Idiffflows asymmetrically, in either direction, across inductor105.

The current flowing through each of NMOSs120and125is summed at node135and returned to source130. As circuit100is a closed path between the positive voltage potential of source130and the negative voltage potential of source130, the current received at center terminal140is equal to the current returned to the negative voltage potential of source130. Accordingly, the current returned to the negative voltage potential of source130is equal to Ibias.

Return155within circuit100ofFIG. 1represents the return pathway for current from the source of each of NMOSs120and125to the negative voltage potential of source130. When implemented as a physical circuit within an IC, return155represents one or more segments of interconnect material that couple the source of each of NMOSs120and125to a ground bus implemented within a conductive layer of the IC located some finite distance from the source of each of NMOSs120and125.

Depending upon the location and manner of routing the interconnect material that couples the source terminal of each of NMOSs120and125to source130, the interconnect material of return155can couple to inductor105. The manner of this coupling can be both capacitive and inductive. Asymmetries in routing the interconnect of return155to return current Ibiasto source130, relative to inductor105, can result in asymmetric coupling of return155to inductor105. In addition, asymmetries in the current flowing within differing segments of the interconnect material of return155can result in asymmetric inductive coupling of return155to inductor105.

The coupling of other devices and physical features, e.g., metal interconnect, within a physical implementation of circuit100in an IC can impact circuit parameters of inductor105and, accordingly, circuit100. In illustration, other IC devices and physical features coupling to inductor105can alter the inductance value of inductor105, thereby shifting the center frequency of circuit100. Asymmetric coupling of return155to inductor105can affect the inductive value of one of inductors105aand105bmore significantly than the other, thereby degrading the differential integrity of circuit100. In addition, asymmetric coupling of common mode noise to inductor105can couple more of the common mode noise to one of inductors105aand105bthan the other. The asymmetric coupling of common mode noise, noise that is inherently reduced by a differential circuit, to inductors105aand105bcan result in common mode noise being converted to differential noise.

FIG. 2is a second block diagram illustrating a topographical view of an inductor structure (inductor)105in accordance with another embodiment disclosed within this specification.FIG. 2illustrates a physical layout representation, as implemented within an IC, of the single turn, center tap inductor105discussed with reference toFIG. 1. As such, like numbers will be used to refer to the same items throughout this specification. Inductor105can include a coil205, a center terminal140, differential terminals (terminals)210and215, a return155, and an isolation ring220.

Although denoted as four distinct objects for descriptive purposes within this specification, coil205, center terminal140, and terminals210and215are coupled together and represent one continuous area of conductive material. In addition, though implemented as one continuous area or segment of conductive material, coil205, center terminal140, and terminals210and215can be implemented within one or more different conductive layers of the IC. The conductive layers can be coupled together with one or more vias to create one continuous conductive pathway.

Coil205can be implemented as a symmetrical, single turn coil of inductor105. A centerline225can be determined that symmetrically bisects coil205. Each segment of coil205residing on a particular side of centerline225can represent a physical layout of one of inductors105aand105bas described with reference toFIG. 1. Although implemented as an octagonal coil withinFIG. 2, coil205can be implemented in any of a variety of forms or shapes that can be implemented using available IC manufacturing processes so long as the symmetry of coil205about centerline225is retained. As such, the implementation of coil205as an octagonal coil within inductor105is provided for clarity and descriptive purposes only, and is not intended to be limiting.

When implemented within an RF differential circuit, e.g. circuit100ofFIG. 1, inductor105can receive bias current Ibiasat center terminal140. As noted earlier within this specification, center terminal140is located at the midpoint of the length of coil205, thereby assuring that each side of coil205is symmetric and of equal inductive value. Each of terminals210and215can be coupled to a differential output node of the RF differential circuit in which inductor105is implemented. As described earlier within this specification, when the RF differential circuit is in a balanced condition, the common mode current ICMthat is sourced from each of terminals210and215is approximately equal to one half of Ibias.

As the RF differential circuit switches state, a differential current, Idiff, can alternately flow in either direction within coil205. As Idiffalternates in direction of flow, the quantity of current associated with Idiffalso varies. With the current within coil205described in this manner, the current flowing through coil205can be represented as the sum of ICMand Idiffflowing through terminals210and215at any particular time.

For example, center terminal140can receive a current Ibiasof approximately 100 mA. As a result, the common mode current flowing through each of terminals210and215can be approximately 50 mA. At a time T1, approximately 75 mA can be flowing out of terminal210and approximately 25 mA can be flowing out of terminal215. In that case, at time T1, a differential current of approximately 25 mA flows in coil205from terminal215to terminal210. The distinction between common mode current and differential current is significant to the performance of inductor105as ICMflows symmetrically on either side of centerline225while Idiffflows alternately in either direction across centerline225.

Return155can be implemented with a segment of conductive material disposed within a conductive layer of the IC manufacturing process used to implement inductor105. In one embodiment, the length of return155can be approximately equal in length to a diameter of coil205the centerline225and further can be located substantially within coil205. The conductive layer in which return155is implemented can be a conductive layer that is different from the conductive layer used to implement coil205, center terminal140, and/or terminals210and215. Implementing return155in this manner prevents one or more of coil205, center terminal140, or differential terminals210and215from being coupled to return155. Further, through return155, the current flowing through each side of coil205, is summed and returned to source130, which can be located at the end of return155adjacent to, or near, center terminal140. Return155can be disposed on centerline225, thereby symmetrically bisecting inductor105, i.e., coil205. The implementation of return155on centerline225assures that current used within inductor105is routed symmetrically back through inductor105to the lowest potential. Additionally, the implementation of return155on centerline225assures that the conductive material used to return the current used within inductor105back to the lowest potential is routed symmetrically through inductor105.

Implementing return155in this manner assures that any coupling induced by returning bias current to the lowest potential or by the interconnect material used to return bias current to the lowest potential is symmetrically applied to either side of coil205as bisected by centerline225. Retaining this symmetry allows the retention of the matched inductive properties between each side of coil205. As each section of coil205residing on either side of centerline225implements an individual inductor, e.g., inductors105aand105bas described with reference toFIG. 1, the matching of the inductive value of each side of coil205is required to assure differential signal balance within a circuit implemented with inductor105. Any common mode noise coupled to coil205asymmetrically to one side of centerline225can be converted to a differential noise that can appear within the differential output signal of any differential circuit in which inductor105is implemented.

Isolation ring220can include one or more substrate taps coupled to a segment of conductive material residing within a conductive layer of an IC manufacturing process used to implement inductor105. In another embodiment, the lowest residing conductive layer of the IC manufacturing process, and therefore, the conductive layer vertically closest to the substrate taps, can be used to implement the segment of conductive material that is coupled to the substrate tap(s). The conductive material of isolation ring220can be coupled via one or more interconnects to a lowest voltage potential available within the IC in which inductor105is implemented, e.g., ground. In one aspect, isolation ring220can be said to electromagnetically couple to coil205.

Isolation ring220can surround coil205at a constant and predetermined distance230from an outer perimeter of coil205. For example, coil205and isolation ring220can be concentric with respect to one another. Coil205and isolation ring220further can have a same shape despite isolation ring220being sized to surround coil205and being implemented within different conductive layers of the IC.

As IC inductor structures reside over a conductive substrate material that is common to the entire IC, noise from surrounding devices can be injected into the substrate material residing directly beneath the inductor structure. The coils of an inductor structure are generally implemented within the conductive layer(s) farthest from the substrate layer and are separated from the substrate layer by one or more dielectric layers. Despite this isolation, both inductive and capacitive coupling can exist between the coils of the conventional inductor structure and the underlying substrate. For this reason, isolation rings can be located around the inductor structure and coupled to a common substrate voltage potential such as, for example, the ground potential of the IC. Coupling the substrate underlying the inductor structure to ground improves isolation of the underlying substrate from substrate noise injected by devices surrounding the inductor structure.

Typically, the isolation rings used within a conventional IC inductor structure form a continuous substrate ring surrounding the inductor coils of the conventional IC inductor. As the conventional isolation ring is continuous, it forms a coil surrounding the coils of the conventional IC inductor. As a result, a mutual inductance exists between the coils of the conventional IC inductor and the coil formed by the conventional isolation ring. Through mutual inductance, a time varying differential current within the conventional IC inductor can generate a magnetic field that induces a current flow within the conventional isolation ring. The current generated within the conventional isolation ring generates a magnetic field that opposes the current flow within the conventional IC inductor. This opposing magnetic field reduces the absolute inductive value for the conventional IC inductor when operating within a circuit.

As such, the mutual inductance between the conventional isolation ring and the conventional IC inductor decreases the inductive value of the conventional IC inductor structure. In addition, as the distance between the conventional isolation ring and the coils of the conventional inductor structure decreases, the mutual inductance between the conventional isolation ring and the coils of the conventional inductor structure increases, and the absolute inductive value of the conventional IC inductor structure decreases. The reduction in the inductive value of the conventional IC inductor structure from inductive coupling to the conventional isolation ring can approach 20 percent of the inductive value of the conventional IC inductor structure in the absence of the conventional isolation ring.

To counter the effect of the conventional isolation ring on inductance values, isolation ring220includes an opening that creates a discontinuity within isolation ring220. Unlike the conventional isolation ring, isolation ring220does not form a continuous coil surrounding coil205. Ends240and245of isolation ring220are proximate to center terminal140, e.g., at an opposing end of inductor105from differential terminals210and215, and are separated by a predetermined distance235defining the opening. In another embodiment, the opening can be centered over centerline225. In that case, each of ends240and245of isolation ring220can be equidistant from centerline225. As illustrated, the opening is aligned with center terminal140on centerline225, e.g., aligned on a same axis. A portion of isolation ring, e.g., a location opposite the opening, can be coupled to return155, as will be illustrated in greater detail within this specification.

The opening in isolation ring220can inhibit the circulation of current around isolation ring220by breaking the current pathway through isolation ring220. The decrease in current flow within isolation ring220can reduce the impact of inductive coupling between coil205and isolation ring220upon the inductive value of inductor105. For example, the inclusion of the opening defined by distance235between ends240and245within isolation ring220can reduce the effect that any variation in distance230has upon the inductive value of inductor105.

Similar to the way in which isolation ring220forms a coil that interacts with inductor105, segments of conductive material used to interconnect circuit blocks within an IC can form coils that interact with inductor105. In particular, power supply lines within an IC, e.g., VDD and ground, which are typically implemented with large areas of conductive material, are more likely to interact with inductor105. In order to form a coil that interacts with inductor105, a power supply line must bisect coil205of inductor105in a manner that crosses centerline225. When the power supply line remains on one side of centerline225, the impact of differential current flowing across differential terminal210and215on the power supply line is minimal.

By allowing a supply line to cross centerline225, differential currents flowing across coil205can induce current within the power supply line that crosses centerline225. The current induced within the power supply line can generate magnetic fields that affect the inductive value of inductor105. For this reason, when implemented within an IC layout, no power supply lines of the IC can reside within a perimeter defining inductor105, or within a predetermined spacing from the perimeter defining inductor105, that crosses centerline225. In one embodiment, isolation ring220, e.g., an outer edge of isolation ring220, can be the perimeter defining inductor105.

By implementing return155, the opening in isolation ring220, and preventing supply lines from crossing centerline225as described, a center tap inductor can be implemented that exhibits greater differential symmetry and a more stable inductive value. The use of the various structural elements described with reference toFIG. 2, a reduction in the variation of the inductive value of inductor105to approximately 2 percent of the designed inductive value can be achieved.

FIG. 3is a second block diagram providing a graphical representation of an inductor structure in accordance with another embodiment disclosed within this specification. More particularly,FIG. 3illustrates further aspects of inductor105. Accordingly,FIG. 3is intended to provide a better understanding of electrical and electromagnetic properties of inductor105and the influence of those properties upon the operation of circuit100ofFIG. 1. As such, circuit diagram representations of components such as PMOS115, NMOSs120and125, and VDD are superimposed to illustrate the operational context in which inductor105exists and operates within circuit100.

Referring toFIG. 3, a drain terminal of PMOS115is coupled to center terminal140via an interconnect305. As previously described within this specification, PMOS115functions as a current source for the current Ibiasfrom a positive voltage potential of source130to circuit100. When implemented within an IC layout, interconnect305can be routed to inductor105along centerline225, thereby retaining the structural and current symmetry within inductor105.

Differential terminal210is coupled to a drain terminal of NMOS120. A gate terminal of NMOS120is coupled to differential terminal215. Differential terminal215is coupled to a drain terminal of NMOS125. A gate terminal of NMOS125is coupled to differential terminal215. Implemented in this manner, NMOSs120and125form a cross-coupled differential pair. The source terminal of each of NMOSs120and125is coupled to interconnect310. The common mode and differential current flowing through the source terminal of each of NMOSs120and125, when summed within interconnect305, is approximately equal to Ibias. Interconnect310graphically represents the metal interconnect necessary to couple the source terminal of each of NMOSs120and125to return155. In order to retain the structural and current symmetry within inductor105, interconnect310can be symmetrically coupled to a first end of return155adjacent to differential terminals210and215.

A second end of return155, adjacent to center terminal140, can be coupled to a negative voltage potential of source130. Interconnect315is used to couple return155to the negative voltage potential of source130. Interconnect315can be routed out of inductor105along centerline225to source130. Coupled in this manner, current Ibiascan be returned via return155and interconnect315to source130. For example, interconnect315can be located in a different conductive layer to facilitate routing along central line225. In addition, routing interconnects305,310, and315in this manner assures that current Ibiasis routed to flow symmetrically into, and out of, inductor105along centerline225. This symmetric routing approach prevents the formation of loops within inductor105that can couple to coil205that can vary the total inductance value of inductor105or inject external noise into inductor105.

The coupling of substrate noise can be further minimized by the coupling of isolation ring220to return155at location250. Coupling isolation ring220to return155at location250electrically bisects isolation ring220into two symmetric segments about centerline225. Location250, also representing an electrical node, can correspond to a virtual AC ground of circuit100for differential current flowing within coil205and accordingly, induced current within isolation ring220. As used within this specification, the term “virtual AC ground,” refers to a node of a circuit that is maintained at a steady voltage potential when sourcing or sinking AC current without being directly physically coupled to a reference voltage potential. Coupling isolation ring220to the virtual AC ground at location250minimizes the ability of isolation ring220to form a loop that interacts with any segment of coil205. In addition, coupling the isolation ring220in this manner minimizes the influence of isolation ring220upon the inductive value of inductor105.

The example illustrated withinFIG. 3is not intended to limit the one or more embodiments disclosed within this specification. For example, various devices illustrated in circuit schematic form can be replaced with one or more other passive and/or active devices. In this regard, for example, differential terminal210and differential terminal215can be coupled to location250and return155through one or more active devices, passive devices, or combinations of active and passive devices other than those shown. In general, the devices through which differential terminal210couples to return155will be the same as the devices through which differential terminal215couples to return155, though this need not be the case. In similar fashion, center terminal140can couple to return155through one or more other types of circuit elements that are different from those illustrated inFIG. 3.

FIG. 4is a third block diagram providing a side view of an inductor structure in accordance with another embodiment disclosed within this specification.FIG. 4shows a side view of inductor105ofFIG. 3taken from the perspective of directional arrow300. It should be noted that withinFIG. 4being a side view, one or more objects visible withinFIG. 3may not be visible withinFIG. 4. Similarly, one or more objects that appear withinFIG. 4may not be visible withinFIG. 3.

Referring toFIG. 4, three distinct conductive layers are used to implement the elements of inductor105. Although implemented with three conductive layers, inductor105can be implemented with one or more additional conductive layers. As such, the implementation of inductor105with three conductive layers within this specification is provided for clarity and descriptive purposes only, and is not intended to be limiting. For example, inductor105can be implemented using four conductive layers. In that case, coil205can be implemented using two adjacent conductive layers coupled together by vias. In this manner, the quality factor, i.e., Q, of coil205can be improved by reducing the series resistance associated with coil205.

Continuing withFIG. 4, center terminal140, coil205, and differential terminal210are implemented with a single continuous segment of conductive material within a conductive layer farthest from a substrate layer shown as substrate420. It should be noted that withinFIG. 4, differential terminal215is obstructed from view by differential terminal210.

Return155is implemented within a conductive layer residing between the conductive layer used to implement coil205and substrate420. In the example pictured inFIG. 4, return155is implemented within a conductive layer between the conductive layer in which coil205is implemented and the conductive layer in which isolation ring220is implemented. Generally, inductors are implemented within ICs using the conductive layer(s) farthest from substrate420. Typically, these upper conductive layer(s) of an IC manufacturing process are thicker than lower residing conductive layers and, as a result, create inductors with lower series resistance and higher Q. Although implemented below coil205as shown inFIG. 4, return155also can be implemented within one or more conductive layers that reside above the conductive layer(s) used to implement coil205. As such, the implementation of return155as illustrated withinFIG. 4of this specification is provided for clarity and descriptive purposes only, and not intended to be limiting.

Interconnect305represents a region of conductive material that couples center terminal140of inductor105to a drain terminal of PMOS115. Interconnect310represents a region of conductive material that couples return155to a source terminal of each of NMOSs120and125. Interconnect315represents a region of conductive material that couples return155to a positive potential of source130. Although illustrated as a single layer of conductive material, each of interconnects305,310, and315can be implemented using one or more conductive layers and one or more vias that couple adjacent conductive layers to form each respective one of interconnects305,310, and/or315. As such, the implementation of each of interconnects305,310, and315with a single region of conductive material within this specification is provided for clarity and descriptive purposes only, and not is intended to be limiting.

Isolation ring120is implemented within a conductive layer residing closest to substrate420. Each contact415couples a segment of isolation ring120to an underlying area of substrate420. Although implemented within the conductive layer nearest to substrate420, isolation ring220can be implemented within any conductive layer(s) available within an IC manufacturing process. As such, the implementation of isolation ring220in the conductive layer closest to substrate420and the number of contacts415as illustrated withinFIG. 4is not intended to be limiting.

Interconnect410represents a region of conductive material that couples isolation ring220to interconnect310. Interconnect410is coupled to interconnect310at location250with one or more of vias425. Accordingly, though illustrated as single layer of conductive material, interconnect410can be implemented as one or more conductive layers that couple interconnect410to interconnect310.

In one or more embodiments, location250can be located at an AC virtual ground for the circuit in which inductor105is implemented. In that case, interconnect410can be physically connected to isolation ring220at location250so that isolation ring220is symmetrically bisected at a midpoint of the length of isolation ring220along the centerline of inductor105. Coupling isolation ring220to interconnect310in this manner can minimize the size any loop formed by isolation ring220that may couple to a segment of coil205. Minimizing the coupling of loops formed by isolation ring220to coil205reduces any variability in the induction value of inductor105that may be caused by the proximity of isolation ring220to coil205.

FIG. 5is a fourth block diagram illustrating a two turn center tap inductor structure (inductor)500in accordance with another embodiment disclosed within this specification. Inductor500illustrates the use of an isolation ring feature, as described with this specification as applied to a center tap inductor structure implemented with two or more turns. Inductor500can be used within differential RF circuits as described with reference to inductor105ofFIG. 1.FIG. 5illustrates further aspects and performance improvements that result from providing a symmetric opening within an isolation ring surrounding inductor500.

Inductor500can include a coil505, a center terminal510, differential terminals (terminals)515and520, and an isolation ring525. As inductor500is intended for use within a differential RF circuit, generally, a bias current is received at center terminal510. A portion of the bias current is output to the differential RF circuit at each of terminals520and515. Although referenced as four distinct objects for descriptive purposes within this specification, coil505, center terminal510, and terminals515and520are coupled together and represent one continuous area or segment of conductive material. In addition, each of coil505, center terminal510, and/or terminals515and520can be implemented within one or more different conductive layers of the IC. The conductive layers can be coupled together with one or more vias to create one continuous conductive pathway.

Coil505is implemented as a symmetrical two turn coil of inductor500. A centerline535can be determined that symmetrically bisects coil505. Although implemented as a two turn octagonal coil withinFIG. 5, coil505can include two or more turns implemented in any of a variety of forms or shapes allowable by an IC manufacturing process so long as the symmetry of coil505is retained about centerline535. As such, the implementation of coil505as a two turn octagonal coil within inductor500is provided for clarity and descriptive purposes only, and is not intended to be limiting. In another embodiment, for example, the turns of coil505can be stacked with each turn of the coil implemented within a differing conductive layer of the IC. Each turn implemented within a different conductive layer can be coupled to a turn in an adjacent conductive layer by one or more vias to form a continuous coil.

Isolation ring525can include one or more substrate taps coupled to a segment of conductive material residing within a conductive layer of an IC manufacturing process used to implement inductor500. In another embodiment, the lowest conductive layer of the IC manufacturing process, and therefore, the conductive layer vertically closest to the substrate taps, can be used to implement the segment of conductive material that is coupled to the substrate tap(s). The conductive material of isolation ring525can be coupled via interconnect material within the IC to a lowest voltage potential available within the IC in which inductor500is implemented, e.g., ground. Isolation ring525can surround coil505at a constant and predetermined distance from an outer perimeter of coil505. In another embodiment, isolation ring525can be coupled at the midpoint of the length of isolation ring525to a virtual AC ground located within the circuit in which inductor500is implemented.

FIG. 5illustrates the influence of mutual inductance between coil505and isolation ring525upon current flow within coil505and isolation ring525. Within coil505, Idiff, being a time varying differential current, flows from terminal515to terminal520. As noted within this specification, unlike common mode current that flows symmetrically in either direction away from center terminal510, Idiffflows across inductor500. As such, Idiffflows asymmetrically through inductor coil505with respect to centerline535. The flow of Idiffthough inductor500generates a magnetic field that induces a current within isolation ring525, denoted as Iring, that flows in the opposite direction of Idiff.

Current Iringgenerates a magnetic filed that opposes the flow of current Idiffthrough coil505. As previously discussed within this specification, in conventional IC inductor structures the unimpeded flow of current within an isolation ring can impact the inductive value of the conventional IC inductor structure. The opening of length530within isolation ring525serves to break the pathway for current Iringflowing within isolation ring525. WithinFIG. 5, the length of the arrows used to represent current Iringillustrates the current density of current Iringat various locations within isolation ring525. Referring toFIG. 5, the current density of current Iringis lowest within locations nearest to the opening and highest within locations farthest from the opening.

Accordingly, the magnetic field generated within isolation ring525by current Iringis weakest at locations nearest to the opening and strongest at locations farthest from the opening. As a result, the coupling between coil505and isolation ring525is weakest at locations nearest to the opening and strongest at locations farthest from the opening. Although the current density within isolation ring525decreases at locations nearest to the opening, the variation in current density is symmetric within isolation ring525on either side of the opening within isolation ring525as bisected by centerline535. Locating the center of the opening along centerline535assures the variation in the current density of current Iringand, accordingly, the level of coupling between coil505and isolation ring525, is symmetric within inductor500with respect to centerline535.

To illustrate the importance of the opening being symmetrically bisected by centerline535, assume isolation ring525is rotated clockwise 90 degrees. As coupling between coil505and isolation ring525is weakest near the opening, the coupling between coil505and isolation ring525is weaker within the side of coil505that includes terminal520than the side of coil505that includes terminal515. The asymmetry in the coupling between coil505and isolation ring525created by not centering the opening within isolation ring525over centerline535can lead to the conversion of common mode signals to differential signals.

Continuing with the previous illustration in which isolation ring525is rotated clockwise 90 degrees, a ground potential coupled to isolation ring525can contain a quantity of noise. The noise signal can be coupled by isolation ring525to coil505. As the rotation of the opening results in asymmetric levels of coupling between each side of coil505and isolation ring525, more of the noise signal is coupled to the side of coil505containing terminal515than the side containing terminal520. The difference in the power of the noise signal within one side of coil505from the other side of coil505appears as a differential noise signal within the circuit in which inductor500is implemented.

Centering the opening of isolation ring525over centerline535assures that a noise signal is symmetrically coupled to each side of coil505. In that case, the noise signal appears as a common mode signal which is inherently cancelled at some level by a typical differential circuit. The same coupling asymmetries can also influence the inductive value match of the dual inductors inherent within inductor500.

One or more embodiments disclosed within this specification provide a center tap IC inductor structure that demonstrates improved matching characteristics and improved immunity to coupling effects than conventional inductor structures. The IC inductor structure can be built symmetrically with respect to a centerline that bisects the center tap of the IC inductor structure. An isolation ring can be built that surrounds the outer perimeter of the coils of the center tap IC inductor structure. The isolation ring can be discontinuous in that the isolation ring can include an opening centered about the centerline. The discontinuity in the isolation ring impedes induced current from flowing within the isolation ring. In the case of a single turn center tap inductor structure, a return line can be added to the inductor structure. The return line can be centered symmetrically along the centerline and return current sourced from the IC inductor structure on a path that symmetrically bisects the single turn coil of the IC inductor structure.

The terms “a” and “an,” as used herein, are defined as one or more than one. The term “plurality,” as used herein, is defined as two or more than two. The term “another,” as used herein, is defined as at least a second or more. The terms “including” and/or “having,” as used herein, are defined as comprising, i.e., open language. The term “coupled,” as used herein, is defined as connected, whether directly without any intervening elements or indirectly with one or more intervening elements, e.g., circuit components such as one or more active and/or passive devices, unless otherwise indicated. Two elements also can be coupled mechanically, electrically, or communicatively linked through a communication channel, pathway, network, or system.

One or more embodiments disclosed within this specification can be embodied in other forms without departing from the spirit or essential attributes thereof. Accordingly, reference should be made to the following claims, rather than to the foregoing specification, as indicating the scope of the one or more embodiments.