Current feed-through adaptive voltage position control for a voltage regulator

In a voltage regulator including an error amplifier to generate a first signal related to an output voltage of the voltage regulator, a current sense circuit to generate a second signal related to an inductor current of the voltage regulator, and a PWM comparator to generate a PWM signal in response to the first and second signals to regulate the output voltage, a current feed-through adaptive voltage position control comprises supplying ramp signal and offset signal to modify the PWM signal to thereby eliminate the offset of the output voltage.

FIELD OF THE INVENTION

The present invention is related generally to a voltage regulator and more particularly to a control method and apparatus for a low gain current mode voltage regulator.

BACKGROUND OF THE INVENTION

Voltage regulator has been applied in various electronic products to serve as power supply for providing stable supply voltage. However, spike will be generated on the output voltage of voltage regulator in load transient resulted from instant load change, and large voltage spike may damage the load on the voltage regulator.FIG. 1shows waveform100of the output voltage of a conventional voltage regulator in load transient. At time T1, the load on the voltage regulator changes from light to heavy, and the output voltage of the voltage regulator drops down ΔV instantly, and then recovers to the original level gradually. At time T2, the load on the voltage regulator changes from heavy back to light, the output voltage of the voltage regulator jumps up ΔV instantly, and then recovers to the original level gradually. Therefore, the output voltage of a conventional voltage regulator changes with 2ΔV in load transient. To improve the ripple of output voltage generated in load transient, large output capacitor is required, and this will increase the size and cost of the voltage regulator. Alternatively, Intel proposed an adaptive voltage position (AVP) control, which uses voltage droop to reduce the output voltage spike of voltage regulator.FIG. 2shows a conventional current mode voltage regulator200having voltage droop function, in which switches SW1and SW2are coupled between input voltage PVDD and ground GND, signals UG and LG switch the switches SW1and SW2to produce inductor current IL flowing through inductor L to charge output capacitor C to thereby produce output voltage Vout, error amplifier202generates error signal COMP from the difference between the output voltage Vout and reference voltage Vref, transconductive amplifier212serves as current sense circuit whose two inputs are coupled to the two ends of sense resistor Rs coupled in series to the inductor L to sense the inductor current IL to thereby generate current sense signal VCS, pulse width modulation (PWM) comparator204compares the error signal COMP with the current sense signal VCS to generate PWM signal for the reset input R of SR latch206, fixed-frequency clock CLK is provided for the set input S of the SR latch206, and the SR latch206produces the signals UG and LG by its outputs Q and QN to switch the switches SW1and SW2with drivers208and210, respectively.

FIG. 3shows waveforms of the load current IRL and output voltage Vout of the voltage regulator200in load transient, in which waveform214represents the load current IRL, and waveform216represents the output voltage Vout. Referring toFIGS. 2 and 3, the load RL on the voltage regulator200changes from light to heavy at time T1, the load current IRL increases eventually, and the output voltage Vout drops down with the voltage drop
ΔV=IRL×Resr[EQ-1]
where Resr is the parasitic resistor of the output capacitor C. Assuming that the error amplifier202has gain M, and the transconductive amplifier212has gain K, the output voltage Vout will drop down to the level

Vout′=Vout-IRL×Resr×KM.[EQ⁢-⁢2]
After the output voltage Vout drops down, it will maintain at the lower level Vout′ until the load RL changes from heavy back to light at time T2, and then the output voltage Vout recovers back to the original level. By comparingFIG. 3withFIG. 1, it is shown that the ripple of the output voltage Vout of the voltage regulator200in load transient is less than 2ΔV. In other words, a voltage regulator having voltage droop function may reduce the ripple of the output voltage significantly. Therefore, the voltage regulator may use smaller output capacitor C.

However, this method is only applicable for high gain voltage regulator. If the voltage regulator200is a low gain voltage regulator, it will not be able to reduce the ripple effect resulted from the error signal COMP and current sense signal VCS owing to the error amplifier202having not enough gain M, resulting in offset on the output voltage Vout.FIG. 4shows waveforms of the error signal COMP and current sense signal VCS when the gain M of the error amplifier202is not large enough. When the switch SW1turns on, the current sense signal VCS increases, as shown by waveform302, and the error signal COMP decreases, as shown by waveform300. Once the current sense signal VCS equal to the error signal COMP, the switch SW1turns off, and the output voltage Vout begins to decrease, causing the error signal COMP to increase, and the current sense signal VCS to decrease. If the touch point of the error signal COMP and current sense signal VCS is not present when the load RL is zero, the output voltage Vout will have an offset apart from the reference voltage Vref in the magnitude of

Voffset=⁢Δ⁢⁢V⁢⁢1+Δ⁢⁢V⁢⁢2=⁢12⁢(Δ⁢⁢IL×Resr×M+Δ⁢⁢IL×Rs×K)=⁢12⁡[PVDD-VoutL×Ton×(Resr×M+Rs×K)]=⁢12[PVDD-VoutL×VoutPVDD×T×(Resr×M+⁢Rs×K)],[EQ⁢-⁢3]
where ΔV1is the amplitude of the error signal COMP, ΔV2is the amplitude of the current sense signal VCS, ΔIL is the variation of the inductor current IL, Ton is the on-time of the switch SW1, and T is the switch period of the switches SW1and SW2. Since L, T, Resr, Rs, M and K are all constant, from the equation EQ-3 it is obtained

The offset Voffset will result in the output voltage Vout not equal to the reference voltage Vref when the inductor current IL is zero. The equation EQ-4 shows that the variable parameters related to the offset Voffset comprise the input voltage PVDD and output voltage Vout, and it is therefore difficult to implement the equation EQ-3 by circuit to eliminate the ripple effect resulted from the error signal COMP and current sense signal VCS.

Therefore, it is desired a control method and apparatus to eliminate the ripple effect resulted from the error signal and current sense signal for a voltage regulator.

SUMMARY OF THE INVENTION

Accordingly, the present invention is to provide a control method and apparatus for voltage regulator, by which the ripple effect resulted from the error signal and current sense signal may be eliminated.

According to the present invention, a current feed-through adaptive voltage position control is provided for a voltage regulator, which uses ramp injection and offset injection to supply ramp signal and offset signal, respectively, to modify the PWM signal of the voltage regulator, thereby eliminating the offset of the output voltage of the voltage regulator resulted from low gain effect.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 5shows first embodiment according to the present invention, andFIG. 6shows waveforms of various signals in the voltage regulator400ofFIG. 5. In the current mode voltage regulator400, switches SW1and SW2are coupled in series between input voltage PVDD and ground GND, SR latch412produces signals UG and LG in response to fixed-frequency clock CLK and PWM signal to switch the switches SW1and SW2with drivers414and416, respectively, to produce inductor current IL flowing through inductor L to charge output capacitor C to thereby generate the output voltage Vout, error amplifier402of low gain M generates error signal COMP from the difference between the output voltage Vout and reference voltage Vref to provide for the non-inverting input of PWM comparator410, transconductive amplifier418of gain K serves as current sense circuit whose two inputs are coupled to the two ends of sense resistor Rs coupled in series to the inductor L to sense the inductor current IL to thereby generate current sense signal VC coupled to positive input of summing circuit408, and ramp injection circuit404supplies ramp signal Vramp to another positive input of the summing circuit408following the relationship

Vramp∝Vout×TonL,[EQ⁢-⁢5]
where Ton is the on-time of the high side switch SW1. In addition, offset injection circuit406supplies offset voltage Voffset′ to negative input of the summing circuit408, and the summing circuit408combines the current sense signal VC, ramp signal Vramp, and offset signal Voffset′ to generate signal VCS coupled to the inverting input of the PWM comparator410. InFIG. 6, waveform500represents the load current IRL, waveform502represents the current sense signal VC, waveform504represents the ramp signal Vramp, waveform506represents the offset voltage Voffset′, waveform508represents ground potential, waveform510represents the error signal COMP, waveform512represents the signal VCS, waveform514represents the signal UG, and waveform516represents the output voltage Vout. When the clock CLK transits from low to high, the high side switch SW1is turned on accordingly, and therefore, the error signal COMP begins to decrease, and the signal VCS rises. Until the error signal COMP equal to the signal VCS, the PWM signal produced by the PWM comparator410transits from high to low, thereby turning off the high side switch SW1.

In this embodiment, the ramp signal Vramp simulates the rising slope of the inductor current IL, and therefore the ramp injection circuit404behaves as a slope compensation circuit. Assuming that the ramp injection circuit404supplies the ramp signal

Vramp=VoutL×Ton×(Resr×M+Rs×K),[EQ⁢-⁢6]
it is equivalently introducing two signals having the values of Vout/L×Ton×Resr×M and Vout/L×Ton×Rs×K into the error signal COMP and current sense signal VC, respectively. As a result, the equation EQ-3 may be modified to be

In the equation EQ-7, L, T, Resr, Ra, M and K are all constant, only Vout is variable, and it is therefore easy to implement the offset injection circuit406for supplying the offset voltage Voffset′. Only by subtracting the offset voltage Voffset′ from the ramp signal Vramp, the offset Voffset of the output voltage Vout caused by the ripple effect resulted from the error signal COMP and current sense signal VC is obtained. In other words, by using the ramp signal Vramp and offset voltage Voffset′, the offset Voffset of the output voltage Vout caused by the ripple effect resulted from the error signal COMP and current sense signal VC may be eliminated such that the output voltage Vout will be equal to the reference voltage Vref when the inductor current IL is zero.

Referring toFIGS. 5 and 6, when the load RL on the voltage regulator400changes from light to heavy, the load current IRL increases, as shown by the waveform500, and the output voltage Vout drops down rapidly with the voltage drop

Δ⁢⁢V=IRL×Rs×KM,[EQ⁢-⁢8]
as shown by the waveform516. The error signal COMP increases due to the decreasing output voltage Vout. On the other hand, as the load current IRL increases, the current sense signal VC increases correspondingly, thereby the signal VCS increasing. As shown by the waveform506, the offset voltage Voffset′ maintains constant, which represents the increased values of the error signal COMP and signal VCS are equal to each other, and thereby the output voltage Vout may be maintained at the lower level518after it drops down.

In this embodiment, the current sense signal VC is generated by the transconductive amplifier418based on the voltage drop across the sense resistor Rs coupled in series to the inductor L, while in other embodiments, it may be generated by alternative scheme, such as shown inFIGS. 7 to 10. InFIG. 7, the sense resistor Rs is coupled between the input voltage PVDD and high side switch SW1, and the transconductive amplifier418generates the current sense signal VC based on the voltage drop across the sense resistor Rs. InFIG. 8, the transconductive amplifier418generates the current sense signal VC based on the voltage drop across the high side switch SW1directly. InFIG. 9, the sense resistor Rs is coupled between the low side switch SW2and ground GND, and the transconductive amplifier418generates the current sense signal VC based on the voltage drop across the sense resistor Rs. InFIG. 10, the transconductive amplifier418generates the current sense signal VC based on the voltage drop across the low side switch SW2directly.

Further, in other embodiments, the ramp signal Vramp, offset voltage Voffset′ and current sense signal VC may be combined to the non-inverting input of the PWM comparator410, or either one of the ramp signal Vramp and offset voltage Voffset′ is coupled to the input of the error amplifier402, and the other one coupled to the input of the PWM comparator410. In such cases, the phases of these signals and the corresponding gains should be modified according to the realized situations.

FIG. 11shows second embodiment according to the present invention. In voltage regulator600, PWM comparator608compares the error signal COMP produced by error amplifier606with reference voltage Vref to generate PWM signal, SR latch610produces signals UG and LG in response to fixed-frequency CLK and PWM signal to switch switches SW1and SW2with drivers612and614, respectively, to produce inductor current IL flowing through inductor L to charge output capacitor C to thereby generate output voltage Vout, transconductive amplifier616serves as current sense circuit to generate current sense signal VC based on the voltage drop across sense resistor Rs coupled in series to the inductor L to couple to positive input of summing circuit618, ramp injection circuit602supplies ramp signal Vramp to another positive input of the summing circuit618, offset injection circuit604supplies offset voltage Voffset′ to negative input of the summing circuit618, the summing circuit618combines the current sense signal VC, offset voltage Voffset′ and ramp signal Vramp to generate signal VCS for the non-inverting input of the error amplifier606, and the error amplifier606compares the output voltage Vout with the signal VCS to produce the error signal COMP for the non-inverting input of the PWM comparator608. The ramp signal Vramp in this embodiment also follows the equation EQ-5.

In this embodiment, the error signal COMP produced by the error amplifier606will cause the output voltage Vout having the offset

Voffset=⁢12⁢(Δ⁢⁢IL×Resr+Δ⁢⁢IL×Rs×K)=⁢12⁡[PVDD⁢⁢VoutL×Ton×(Resr+Rs×K)],[EQ⁢-⁢9]
where Resr is the parasitic resistor of the output capacitor C, Ton is the on-time of the high side switch SW1, and K is the gain of the transconductive amplifier616. Due to several parameters in the equation EQ-9, it is difficult to implement with circuit. To simplify the equation EQ-9, the current sense signal VC is introduced with ramp signal

Vramp=VoutL×Ton×(Resr+Rs×K),[EQ⁢-⁢10]
and then the equation EQ-9 may be modified to be

Voffset′=⁢12[PVDD⁢⁢VoutL×Ton×(Resr+Rs×K)+⁢VoutL×Ton×(Resr+Rs×K)]=⁢12⁡[VoutL×T×(Resr+Rs×K)],[EQ⁢-⁢11]
where T is the switch period of the switches SW1and SW2. It is shown by the equation EQ-11 that there is only a variable parameter Vout to determine the offset voltage Voffset′, and it is therefore easy to implement the offset injection circuit604for supplying the offset voltage Voffset′. From the equations EQ-9, EQ-10 and EQ-11, it is shown that the offset Voffset caused by the error amplifier606is equal to the difference between the offset voltage Voffset′ and ramp signal Vramp, and therefore, by using the ramp signal Vramp and offset voltage Voffset′, the offset Voffset of the output voltage Vout may be eliminated such that the output voltage Vout will be equal to the reference voltage Vref when the inductor current IL is zero.

Likewise, the schemes shown inFIGS. 7 to 10may be used in the voltage regulator600to produce the current sense signal VC alternatively. Also, in other embodiments, the ramp signal Vramp, offset voltage Voffset′ and current sense signal VC are all coupled to the non-inverting input of the error amplifier606, or either one of the ramp signal Vramp and offset voltage Voffset′ is coupled to the input of the error amplifier606, and the other one coupled to the input of the PWM comparator608. In such cases, the phases of these signals and the corresponding gains should be modified according to the realized situations.