Arithmetic processing apparatus and control method for arithmetic processing apparatus

An arithmetic processing apparatus, includes: an arithmetic operation execution circuit configured to execute an arithmetic operation; a first register configured to store data to be used for an arithmetic operation by the arithmetic operation execution circuit; a first buffer configured to store data; a first controller configured to store, when an array of data is changed and the changed data is stored into the first register as the data to be used for the arithmetic operation, a plurality of data groups, which are successively received, into the first buffer; and a second controller configured to successively output, every time each of the plurality of data groups is stored into the first buffer, data included in the data groups stored in the first buffer to the first register.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2017-025414, filed on Feb. 14, 2017, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to an arithmetic processing apparatus and a control method for an arithmetic processing apparatus.

BACKGROUND

In data processing such as image processing, transposition data are used in which rows and columns are replaced in an array of data.

A related art is disclosed in Japanese Laid-open Patent Publication No. 11-53345.

SUMMARY

According to an aspect of the embodiments, an arithmetic processing apparatus, includes: an arithmetic operation execution circuit configured to execute an arithmetic operation; a first register configured to store data to be used for an arithmetic operation by the arithmetic operation execution circuit; a first buffer configured to store data; a first controller configured to store, when an array of data is changed and the changed data is stored into the first register as the data to be used for the arithmetic operation, a plurality of data groups, which are successively received, into the first buffer; and a second controller configured to successively output, every time each of the plurality of data groups is stored into the first buffer, data included in the data groups stored in the first buffer to the first register.

The object and advantages of the invention will be realized and attained by mean of the elements and combinations particularly pointed out in the claims.

DESCRIPTION OF EMBODIMENTS

Data are transposed, for example, by writing data into memory cells arranged in the row direction of a memory cell array and reading out data from memory cells arranged in the column direction. Here, if a memory cell array including multiport memory cells having a first port and a second port is used, data may be converted into transposition data without a break. In this case, in each of a given number of cycles, after data are read out, writing of data is executed for memory cells arranged in the row direction of the memory cell array using the first port. In each of the next given number of cycles, after the reading out of data from the memory cells arranged in the column direction of the memory cell array is performed using the second port, writing of data is executed.

For example, where transposition data are generated utilizing a memory cell array including multiport memory cells, a control circuit for a row decoder, a column decoder and so forth may be complicated in comparison with a control circuit that controls a memory cell array including single-port memory cells. For example, the area of a multiport memory cell is greater than the area of a single-port memory cell. Therefore, in a memory cell array of the multiport configuration, although transposition data are generated without a break, the configuration may be complicated and complicated control may be performed.

For example, data arrayed in rows and columns are retained in a buffer unit including a plurality of flip-flop circuits, and transposition data are generated by changing the order of data to be read out from the buffer unit and the order of data written in the buffer unit. However, where transposition data are generated without a break, since two buffer units for alternately retaining data are used, the circuit scale of the circuitry may increase.

For example, the circuit scale of a buffer unit that generates transposition data without a break may be reduced.

FIG. 1depicts an example of an arithmetic processing apparatus. The arithmetic processing apparatus100depicted inFIG. 1includes an arithmetic operation execution unit1that executes an arithmetic operation, a register unit2, a transposition buffer3, a buffer input controller4and a buffer output controller5. The register unit2is an example of a first register unit, and the transposition buffer3may be an example of a first buffer unit; the buffer input controller4may be an example of a first controller; and the buffer output controller5may be an example of a second controller.

The register unit2includes a plurality of register files RF (RF0, RF1, RF2and RF3) into which data used for an arithmetic operation of the arithmetic operation execution unit1are stored. The transposition buffer3retains data to be stored into the register unit2before the data are stored into the register unit2. InFIG. 1, the transposition buffer3includes a retention region for retaining 16 data each indicated by a rectangle.

The buffer input controller4stores a plurality of data groups successively received from a memory200by the arithmetic processing apparatus100through a data line DL1in the received order into the transposition buffer3. Every time each of the plurality of data groups is stored into the transposition buffer3, the buffer output controller5successively outputs data included in the data group stored in the transposition buffer3to the register unit2through a data line DL2. The arithmetic processing apparatus100includes a bypass route BYPS for transferring data on the data line DL1directly to the register unit2without the intervention of the transposition buffer3. The bypass route BYPS is used when data read out from the memory200are stored into the register unit2without transposing the array of the data as described with reference toFIGS. 2 and 4.

Though not specifically restricted, the plurality of data groups received from the memory200are, for example, image data. The arithmetic operation execution unit1executes, for example, a program to execute discrete cosine transform (DCT) transform for image data retained in the register unit2or to execute various filtering processes for image data retained in the register unit2. For example, the arithmetic processing apparatus100is an artificial intelligence (AI) processor for deep learning. Alternatively, the arithmetic processing apparatus100is a processor such as a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU) or a general purpose computing on GPU (GPGPU). It is to be noted that the arithmetic processing apparatus100may be an accelerator that executes image processing or the like in place of a processor.

FIG. 2depicts an example of operation of the arithmetic processing apparatus100depicted inFIG. 1. For example,FIG. 2depicts an example of a control method of the arithmetic processing apparatus100. InFIG. 2, a cycle indicates, for example, a clock cycle. InFIG. 2, the memory200retains a plurality of data (#0to #31). The data are read out from the memory200for each data group including four data (for example, #0, #1, #2and #3).

The buffer input controller4stores each data group read out from the memory200into the transposition buffer3through the data line DL1. InFIG. 2, four data surrounded by a thick frame from among the data retained in the memory200and four data surrounded by a thick frame from among data transmitted to the data line DL1indicate data groups.

The buffer output controller5successively stores, for each data group, four data included in the data group stored in the transposition buffer3to one of the register files RF0to RF3over four cycles from a cycle next to the cycle in which the data group is stored into the transposition buffer3. For example, every time each of the data groups is stored into the transposition buffer3, the buffer output controller5successively outputs the data included in the data group stored in the transposition buffer3to the register unit2through the data line DL2. The arithmetic operation execution unit1executes arithmetic operation using four data stored dispersedly in the register files RF0to RF3.

For example, the data line DL2includes data lines DL2[0], DL2[1], DL2[2] and DL2[3] corresponding to the register files RF0to RF3, respectively. InFIG. 2, four data surrounded by a thick frame from among data transmitted to the data line DL2and four data surrounded by a thick frame from among data retained in the register unit2indicate a unit of data used for each arithmetic operation by the arithmetic operation execution unit1. For example, the arithmetic operation execution unit1executes arithmetic operation using the data #0, #4, #8and #12and executes arithmetic operation using the data #1, #5, #9and #13. Further, the arithmetic operation execution unit1executes arithmetic operation using the data #2, #6, #10and #14, and executes arithmetic operation using the data #3, #7, #11and #15.

The array of four data used for each arithmetic operation by the arithmetic operation execution unit1is different from the array of four data read out at once from the memory200. For example, the buffer input controller4and the buffer output controller5transpose the data read out from the memory200and retained in the transposition buffer3and store the transposed data into the register unit2.

The buffer input controller4stores the data #0to #15successively into the transposition buffer3using the cycle0to the cycle3and then successively stores the data #16to #31into the transposition buffer3using the cycle4to the cycle7. For example, the data group #16to #19is stored into a retention region of the transposition buffer3in which the data group #0to #3is stored, and the data group #20to #23is stored into a retention region of the transposition buffer3in which the data group #4to #7is stored. The data group #24to #27is stored into a retention region of the transposition buffer3in which the data group #8to #11is stored, and the data group #28to #31is stored into a retention region of the transposition buffer3in which the data group #12to #15is stored.

The data #3is read out from the transposition buffer3in the cycle4, and the data #16is stored into the transposition buffer3in the cycle4. Therefore, when the data group #16to #19is stored into the transposition buffer3in the cycle4, the data group #0to #3has been read out from the transposition buffer3into the data line DL2[0]. Accordingly, also when the data groups #16to #31are to be transferred without a break after the data groups #0to #15, the data group #0to #3is stored into the register files RF0to RF3without being lost.

Also in the cycle5to the cycle7, similarly as in the cycle4, before a new data group is stored into the transposition buffer3, a data group already retained in the transposition buffer3is read out from the transposition buffer3. Accordingly, by successively storing, every time a data group is retained into the transposition buffer3, a plurality of data included in a data group into the register unit2, data to be transposed may be successively stored into the transposition buffer3without overwriting data retained in the transposition buffer3. As a result, it is possible to transpose a plurality of data and successively store the transposed data into the register unit2utilizing the single transposition buffer3, and the arithmetic operation execution unit1may successively execute a plurality of arithmetic operations using data read out from the memory200and transposed.

In contrast, if data is transposed by transferring, after the 16 data #0to #15are stored into the transposition buffer3utilizing the cycle0to the cycle3, the data from the transposition buffer3to the register unit2using the cycle4to the cycle7, the following failure may occur. For example, in the cycle4in which the data #16to #19are stored into the transposition buffer3, the data #0, #4, #8and #12are transferred from the transposition buffer3to the register unit2. In this case, the data #1, #2and #3retained into the transposition buffer3in the cycle0may be overwritten with the data #17, #18and #19and may be lost before they are transferred to the register unit2. In order to suppress such loss of data, for example, two transposition buffers3are provided such that 16 data are alternately stored into the two transposition buffers3. During a cycle in which data are stored into one of the transposition buffers3, data are transferred from the other transposition buffer3to the register unit2.

For example, when an arithmetic operation is executed without transposing data, data read out from the memory200depicted inFIG. 1are stored into the register unit2through the bypass route BYPS. In this case, for example, the data #0, #1, #2and #3are stored into the register files RF0to RF3, respectively. For example, the data #0, #4, #8and #12are stored into the register file RF0; the data #1, #5, #9and #13are stored into the register file RF1; the data #2, #6, #10and #14are stored into the register file RF2; and the data #3, #7, #11and #15are stored into the register file RF3.

FIG. 3depicts an example of operation of the transposition buffer3in the cycle0to the cycle7depicted inFIG. 2. For example,FIG. 3depicts an example of a control method of the arithmetic processing apparatus100. Referring toFIG. 3, a bent arrow mark indicates that data is written into a retention region of the transposition buffer3. A retention region indicated by a thick frame indicates a retention region from which data is read out, and reference symbols RF0to RF3each applied to the head of a rightwardly directed arrow mark represent the register files RF0to RF3into which data read out from retention regions are stored.

For example, in the cycle4, after the data #12, #9, #6and #3are read out from the transposition buffer3, the data #16, #17, #18and #19are written into the transposition buffer3. The data #0, #1, #2and #3retained in the transposition buffer3disappear by the writing of the data #16, #17, #18and #19. However, since transfer of the data #0, #1, #2and #3to the register files RF0to RF3over the cycle1to the cycle4is completed already, a trouble does not occur.

Similarly, in the cycle5, after the data #16, #13, #10and #7are read out from the transposition buffer3, the data #20, #21, #22and #23are written into the transposition buffer3. The data #4, #5, #6and #7retained in the transposition buffer3disappear by the writing of the data #20, #21, #22and #23. However, since transfer of the data #4, #5, #6and #7to the register files RF0to RF3over the cycle2to the cycle5is completed already, a trouble does not occur.

FIG. 4depicts an example of operation of the arithmetic processing apparatus100depicted inFIG. 1. For example,FIG. 4depicts an example of a control method of the arithmetic processing apparatus100. In operation S1, the arithmetic processing apparatus100reads out data to be used for an arithmetic operation from the memory200. Reading out of data from the memory200is executed, for example, based on a load instruction from the arithmetic processing apparatus100. In operation S2, the arithmetic processing apparatus100decides whether or not data are to be transposed. Whether or not data are to be transposed is decided, for example, based on a value of a transposition flag included in the operand of the load instruction. When data are to be transposed, the operation is advanced to operation S3, but when data are not to be transposed, the operation is advanced to operation S5.

In operation S3, the arithmetic processing apparatus100successively stores data read out from the memory200into the transposition buffer3. Further, in operation S4, the arithmetic processing apparatus100successively reads out, every time data are stored into the transposition buffer3, the data stored in the transposition buffer3and stores the data into the register files RF0to RF3while the cycle is successively displaced. The data are transposed in the process by which the data are stored into the register unit2through the transposition buffer3. As depicted inFIGS. 2 and 3, the operations in operations S3and S4may be executed in parallel. After operations S3and S4, the operation is advanced to operation S6.

When the data are not to be transposed, in operation S5, the arithmetic processing apparatus100stores the data read out from the memory200so as to be used for an arithmetic operation into the register files RF0to RF3through the bypass route BYPS, and the operation is advanced to operation S6. In operation S6, the arithmetic processing apparatus100executes an arithmetic operation using the data stored in the register files RF0to RF3in accordance with an arithmetic operation instruction and ends the operation. A result of the arithmetic operation is stored into a region, for example, in the register files RF0to RF3, into which data may be written without any trouble such as a region in which data from the memory200are not stored. The result of the arithmetic operation is transferred from the register unit2to the memory200, for example, in response to execution of a store instruction from the arithmetic processing apparatus100.

In the foregoing description given with reference toFIGS. 1 to 4, every time a data group is retained into the transposition buffer3, the arithmetic processing apparatus100successively stores a plurality of data included in the data group into the register unit2. Consequently, also when data to be transposed are successively supplied to the transposition buffer3, the data are transposed without being lost, and the transposed data are stored into the register unit2. Accordingly, the arithmetic operation execution unit1successively executes a plurality of arithmetic operations using the data read from the memory200and transposed. Since transposition data are generated without a break using the single transposition buffer3, increase of the circuit scale of the transposition buffer3may be suppressed. By transferring data read out from the memory200to the register unit2through the bypass route BYPS, the data are stored into the register files RF0to RF3without being transposed.

FIG. 5depicts another example of an arithmetic processing apparatus. The arithmetic processing apparatus110depicted inFIG. 5is an AI processor for deep learning or a processor such as a CPU, a DSP, a GPU or a GPGPU. It is to be noted that the arithmetic processing apparatus110may otherwise be an accelerator.

The arithmetic processing apparatus110includes a plurality of processor cores120and a memory controller130. The arithmetic processing apparatus110may otherwise include a single processor core120. Each processor core120includes an instruction buffer10, a decoder12, a state machine14, a load/store engine16, a transposition unit18, an arithmetic operation execution unit20and a register unit22.

The instruction buffer10successively retains instructions read out from a memory210through the memory controller130and successively outputs the retained instructions to the decoder12. The decoder12decodes an instruction transferred thereto from the instruction buffer10and outputs an instruction code, a register address and so forth included in the decoded instruction to the state machine14.

The state machine14includes a plurality of entries for retaining instructions. The state machine14decides a dependency of the instructions retained in the entries and selects an executable instruction from among the instructions retained in the entries based on the decided dependency. If the selected instruction is an arithmetic operation instruction, the state machine14outputs the selected arithmetic operation instruction to the arithmetic operation execution unit20. If the selected instruction is a memory access instruction (load instruction or store instruction), the state machine14outputs the selected memory access instruction to the load/store engine16.

The load/store engine16outputs an instruction to read out data from the memory210to the memory controller130based on reception of a load instruction. The load/store engine16receives data read out from the memory210through the memory controller130and outputs the received data to the transposition unit18through a memory bus MB together with a valid signal LVALID.

The load/store engine16outputs a valid signal SVALID to the transposition unit18in response to reception of a store instruction and receives data outputted from the register unit22through the transposition unit18through the memory bus MB. The load/store engine16outputs an instruction to write the data received from the transposition unit18through the memory bus MB into the memory210to the memory controller130together with the data.

The memory controller130reads out an instruction from the memory210based on an address generated by a program counter provided in the processor core120and outputs the read out instruction to the instruction buffer10. The memory controller130reads out data from the memory210in accordance with a readout instruction from the load/store engine16and writes the data into the memory210in accordance with a write instruction from the load/store engine16.

The transposition unit18receives data (load data) outputted from the load/store engine16in accordance with a load instruction through the memory bus MB and outputs the received data to the register unit22through a register bus RB. The transposition unit18receives the data (store data) outputted from the register unit22in accordance with a store instruction through the register bus RB and outputs the received data to the load/store engine16through the memory bus MB. Examples of the transposition unit18are depicted inFIGS. 6 to 11.

The arithmetic operation execution unit20includes a plurality of product sum arithmetic units24, a plurality of adders26and a plurality of multipliers28. Each of the product sum arithmetic units24includes a multiplier and an adder and adds a result of multiplication by the multiplier using the adder. Each of the adders26executes addition. Each of the multipliers28executes multiplication or division. The numbers of product sum arithmetic units24, adders26and multipliers28are not restricted to those of the example depicted inFIG. 5and also the type of the arithmetic operation is not restricted. The product sum arithmetic units24, adders26and multipliers28each may be of the fixed point type or of the floating point type. The arithmetic operation execution unit20may include the product sum arithmetic units24, adders26and multipliers28of both the fixed point type and the floating point type.

The register unit22includes a plurality of register files RF (RF0to RF7) for retaining data transferred thereto through the register bus RB and data indicative of a result of an arithmetic operation by the arithmetic operation execution unit20. An example of the register files RF0to RF7is depicted inFIGS. 12 and 13.

FIG. 6depicts an example of the transposition unit depicted inFIG. 5. The transposition unit18includes data shift controllers32A and32B, a memory input selector unit40, a transposition buffer42, a register output selector unit44, a crossbar switch46, a register input selector unit48, a transposition buffer50and a memory output selector unit52. The data shift controller32A includes a buffer input controller34A and a buffer output controller36A that includes a plurality of counters38A. The data shift controller32B includes a buffer input controller34B including a plurality of counters38B, and a buffer output controller36B.

The memory input selector unit40may be an example of a first selector unit, and the memory output selector unit52may be an example of a fourth selector unit. The buffer input controller34A and the memory input selector unit40may be an example of a first controller, and the buffer output controller36A and the register output selector unit44may be an example of a second controller. The buffer input controller34B and the register input selector unit48may be an example of a third controller, and the buffer output controller36B and the memory output selector unit52may be an example of a fourth controller. The transposition buffer42may be an example of a first buffer unit, and the transposition buffer50may be an example of a second buffer unit.

The buffer input controller34A outputs one of enable signals EN (EN0to EN7) in synchronism with a valid signal LVALID outputted from the load/store engine16depicted inFIG. 5. Every time an enable signal EN is outputted, the buffer input controller34A outputs a transfer start signal TS1to the buffer output controller36A. The load/store engine16outputs a valid signal LVALID every time it outputs a data group including a plurality of data to the transposition unit18.

The buffer input controller34A sequentially outputs enable signals EN0to EN7in synchronism with a plurality of valid signals LVALID received in accordance with a load instruction. Although the following describes an example in which eight data groups are supplied to the transposition unit18in accordance with one load instruction in order to facilitate the description, the number of data groups to be supplied to the transposition unit18may be any one of “1” to “8” corresponding to one load instruction. For example, each data group has 256 bits. An example of the enable signals EN0to EN7generated by the buffer input controller34A is depicted inFIG. 14.

An expression (1) indicates an example of a load instruction Id. The load instruction Id includes, in the operand, a memory address maddr, a register address raddr, a transfer length length and a transposition flag trans. The memory address maddr indicates the top address of the memory210from which data is read out, and the register address raddr indicates the top address of a register file RF into which data is written. The transfer length length indicates the number of data transferred (byte number or word number). The transposition flag trans is set to “1” when data read out from the memory210are to be transposed and written into the register unit22, but is set to “0” when data read out from the memory210are to be written into the register unit22without being transposed. In the following, in order to facilitate understandings of the description, it is assumed that the register address raddr indicates to which position of each of the register files RF0to RF7depicted inFIG. 12data is to be written in the form of a number, and the transfer length length is 256 bytes.
Id maddr raddr length trans  (1)

The buffer output controller36A receives a transfer start signal TS1from the buffer input controller34A, renders the counter38A operative and outputs selection signals SEL0to SEL7in accordance with a counter value counted by the counter38A. The selection signals SEL0to SEL7may be an example of a first selection signal, and the buffer output controller36A may be an example of a first signal generator that successively generates selection signals SEL0to SEL7.

For example, the buffer output controller36A includes a counter38A for controlling data lines D0to D7. The counter38A starts counting if it receives a transfer start signal TS1, and generates each of the selection signals SEL0to SEL7. An example of the selection signals SEL0to SEL7generated by the counter38A of the buffer output controller36A is depicted inFIG. 15. The selection signals SEL0to SEL7are supplied also to the register unit22depicted inFIG. 5and are used for control to store data into the register files RF0to RF7.

The memory input selector unit40outputs data of 256 bits received through the memory bus MB to one of eight data lines (256 bits) in response to the enable signals EN0to EN7. The memory bus MB includes eight memory buses MB0to MB7, and each of the memory buses MB0to MB7is a 32-bit bus. Data outputted to one of the eight data lines from the memory input selector unit40is supplied to the transposition buffer42. An example of the memory input selector unit40is depicted inFIG. 7, and an example of operation of the memory input selector unit40is depicted inFIG. 14.

The transposition buffer42retains data of 2048 bits received through the memory input selector unit40in accordance with a load instruction Id and outputs the retained data 256 bits by 256 bits to the data lines DL (DL0to DL7). An example of the transposition buffer42is depicted inFIG. 7. The data line DL0indicates data lines DL0° to DL07; the data line DL1indicates data lines DL10to DL17; the data line DL2indicates data lines DL20to DL27; and the data line DL3indicates data lines DL30to DL37. The data line DL4indicates data lines DL40to DL47; the data line DL5indicates data lines DL50to DL57; the data line DL6indicates data lines DL60to DL67; and the data line DL7indicates data lines DL70to DL77. Each of the data lines DL00to DL77is a 32-bit line.

The register output selector unit44selects data of 2048 bits received through the data lines DL0to DL732 bits by 32 bits in response to the selection signals SEL0to SEL7and outputs the selected data to one of the data lines D (D0to D7) of 32 bits. The selection signals SEL0to SEL7are used for selection of the data lines DL0to DL7, respectively. For example, each of the selection signals SEL0to SEL7is a 4-bit signal. If the most significant one bit is valid, one of the data lines DL0° to DL77is selected in accordance with the logic of the lower 3 bits. For example, in response to the value (“0” to “7”) of the selection signal SEL0, one of the data lines DL0° to DL07is selected, and in response to the value (“0” to “7”) of the selection signal SEL1, one of the data lines DL10to DL17is selected. An example of the register output selector unit44is depicted inFIG. 8, and an example of operation of the register output selector unit44is depicted inFIG. 15.

The crossbar switch46couples each of the data lines D (D0to D7) to one of the register buses RB (RB0to RB7) or couples the bypass route BYPS to the register bus RB. The crossbar switch46may be an example of a switching unit that couples a register bus RB (for example, a register file RF) to an output of the register output selector unit44, an input of the register input selector unit48or the bypass route BYPS. It is to be noted that, in the following description, in order to facilitate understandings of the description, it is assumed that the crossbar switch46couples the data lines D0to D7to the register buses RB0to RB7, respectively, and does not change the coupling. For example, each data line D is coupled to a register bus RB having the same number at the end.

The register output selector unit44and the register input selector unit48are coupled to the crossbar switch46using ones of the data lines D0to D7which are different from each other. In this case, the crossbar switch46couples one of the data lines D0to D7coupled to the register output selector unit44to one of the register buses RB0to RB7in accordance with a load instruction Id. The crossbar switch46couples one of the register buses RB0to RB7to one of the data lines D0to D7coupled to the register input selector unit48in accordance with a store instruction st.

The bypass route BYPS is used to store data read out from the memory210in accordance with the load instruction Id into the register unit22without being transposed similarly as inFIG. 1. The bypass route BYPS is used to store data indicative of a result of an arithmetic operation or the like retained in the register unit22into the memory210without being transposed in accordance with the store instruction st. By using the bypass route BYPS, data read out from the memory210may be stored into the register unit22without being transposed, and data read out from the register unit22may be stored into the memory210without being transposed.

If the buffer input controller34B receives a valid signal SVALID outputted from the load/store engine16depicted inFIG. 5, it renders the counter38B operative and outputs enable signals EN00to EN77according to a counter value counted by the counter38B. The enable signals EN00to EN77may be an example of a second selection signal, and the buffer input controller34B may be an example of a second signal generator that generates the enable signals EN00to EN77.

For example, the buffer input controller34B includes a counter38B corresponding to the data lines D0to D7. The counter38B starts counting for timings at which data are outputted from each of the register files RF0to RF7to the data line D and generates enable signals EN00to EN77under the control of the buffer input controller34B. An example of the enable signals EN00to EN77generated by the counter38B of the buffer input controller34B is depicted inFIG. 17. It is to be noted that the enable signals EN00to EN77are supplied also to the register unit22depicted inFIG. 5and are used for control to read out data from the register files RF0to RF7.

When the load/store engine16depicted inFIG. 5executes a store instruction, it outputs a valid signal SVALID in accordance with a readout cycle of data from the register files RF0to RF7. The buffer input controller34B outputs a transfer start signal TS2to the buffer output controller36B in response to that a first data group is prepared in the transposition buffer50. In the following, in order to facilitate the description, an example in which the transposition buffer50retains eight data groups in accordance with one store instruction is described. However, the number of data groups retained by the transposition buffer50in accordance with one store instruction may be any of “1” to “8.”

An expression (2) depicts an example of the store instruction st. The store instruction st includes, in the operand, a register address raddr, a memory address maddr, a transfer length length and a transposition flag trans. The register address raddr indicates the top address of a register file RF from which data is read out, and the memory address maddr indicates the top address of the memory210into which data is written. The transfer length length indicates the number of data transferred (byte number or word number). The transposition flag trans is set to “1” when data read out from the register unit22is to be transposed and written into the memory210, but is set to “0” when data read out from the register unit22is to be written into the memory210without being transposed. In the following, in order to facilitate understandings of the description, it is assumed that the register address raddr indicates a number indicative of a position of each of the register files RF0to RF7depicted inFIG. 12into which data is to be stored, and the transfer length length has 256 bytes similarly to the load instruction Id.
st raddr maddr length trans  (2)

If the buffer output controller36B receives a transfer start signal TS2from the buffer input controller34B, it successively outputs a selection signal SEL. For example, the selection signal SEL varies from “0” to “7” for each cycle. It is to be noted that the buffer output controller36B may generate a selection signal SEL using a counter. The selection signal SEL may be an example of a third selection signal, and the buffer output controller36B may be an example of a third signal generator that generates a selection signal SEL. An example of the selection signal SEL generated by the buffer output controller36B is depicted inFIG. 18.

The register input selector unit48selects data received from the register unit22through the data lines D0to D732 bits by 32 bits in response to the enable signals EN00to EN77and outputs the selected data to the transposition buffer50through a data line DO (DO0to DO7). Each of the data lines DO0to DO7is a 256-bit (32 bits×8) line. An example of the register input selector unit48is depicted inFIG. 9, and an example of operation of the register input selector unit48is depicted inFIG. 17.

The transposition buffer50retains data of 2048 bits successively received through the register input selector unit48in accordance with the store instruction st and outputs the retained data 256 bits by 256 bits to data lines DS (DS0to DS7). An example of the transposition buffer50is depicted inFIG. 10. The data line DS0indicates data lines DS00to DS07; the data line DS1indicates data lines DS10to DS17; the data line DS2indicates data lines DS20to DS27; and the data line DS3indicates data lines DS30to DS37. The data line DS4indicates data lines DS40to DS47; the data line DS5indicates data lines DS50to DS57; the data line DS6indicates data lines DS60to DS67; and the data line DS7indicates data lines DS70to DS77. Each of the data lines DS00to DS77is a 32-bit line.

The memory output selector unit52selects one of data of 256 bits outputted from the transposition buffer50to the data lines DS0to DS7in response to the selection signal SEL and outputs the selected data to the memory bus MB (MB0to MB7). For example, the selection signal SEL is a 4-bit signal, and when the most significant one bit is valid, one of the data lines DS0to DS7is selected in response to the logic of the lower 3 bits.

FIG. 7depicts an example of the memory input selector unit and the transposition buffer depicted inFIG. 6. The transposition buffer42includes eight column units CUL (CUL0to CUL7) each retaining data of 256 bits supplied through the memory input selector unit40. Each column unit CUL may be an example of a first memory area. Each column unit CUL includes retention circuits FF divided into eight control units, and each retention circuit FF retains data of 32 bits and outputs the retained data to a data line DL. For example, each retention circuit FF of one control unit includes 32 flip-flops for retaining data and so forth. The value of an upper one of two digits applied to the end of each retention circuit FF and each data line DL represents the number of the column unit CUL and the value of the lower digit indicates the number of a memory bus MB to which data is supplied.

The memory input selector unit40includes a logic circuit that output data of 256 bits on the memory bus MB to one of the column units CUL in response to the logics of the enable signals EN0to EN7. The digit applied to the end of each enable signal EN indicates the number of the column unit CUL. InFIG. 7, every time data is transferred to the memory bus MB, one of the enable signals EN0to EN7is set to the logic1. When the enable signal EN0indicates the logic1, the data on the memory bus MB is stored into the column unit CUL0, and when the enable signal EN1indicates the logic1, the data is stored into the column unit CUL1. Each retention circuit FF in each column unit CUL latches, when the corresponding enable signal EN indicates the logic1, data in synchronism with a clock signal.

FIG. 8depicts an example of the register output selector unit depicted inFIG. 6. The register output selector unit44includes eight selectors440to447corresponding to the column units CUL0to CUL7depicted inFIG. 7. The selectors440to447are an example of a second selector unit. The digit at the end of each of the selectors440to447indicates the number of a column unit CUL coupled through a data line DL, the number of one of the selection signals SEL0to SEL7received and the number of one of the data lines D0to D7to which data is outputted. For example, the selector440selects one of data of 32 bits supplied to each of the eight data lines DL0° to DL07in response to the value of the lower 3 bits of the selection signal SEL0and outputs the selected data to the data line D0. When the logic of the most significant bit of the selection signal SEL0indicates an invalid state, the selector440stops outputting of data to the data line D0, and the data line D0outputs 0. The other selectors441to447operate similarly to the selector440.

FIG. 9depicts an example of the register input selector unit depicted inFIG. 6. The register input selector unit48includes eight selectors480to487coupled to the data lines D0to D7depicted inFIG. 6, respectively. The selectors480to487may be an example of a third selector unit. The digit at the end of each of the selectors480to487indicates the number of one of the data lines D0to D7. For example, the selector480outputs data of 32 bits received from the data line D0to one of the data lines DO00to DO07in response to the logic of the enable signals EN00to EN07. One of the enable signals EN00to EN07is set to the logic1every time data is supplied to the data line D0. The other selectors481to487operate similarly to the selector480. It is to be noted that the two digits at the end of the data line DO indicates the number of the retention circuit FF provided in the transposition buffer50depicted inFIG. 10.

FIG. 10depicts an example of another transposition buffer depicted inFIG. 6. The transposition buffer50includes eight column units CUS (CUS0to CUS7) that each retain data of 256 bits supplied through the data line DO. The column units CUS are an example of a second memory area. Each column unit CUS includes eight retention circuits FF similarly to the column unit CUL depicted inFIG. 7, and each of the eight retention circuits FF retains data of 32 bits and outputs the retained data to the data line DS. Although the number of each retention circuit FF of the transposition buffer50overlaps with the number of each retention circuit FF of the transposition buffer42depicted inFIG. 7, the retention circuits FF of the transposition buffer50and the retention circuits FF of the transposition buffer42depicted inFIG. 7may be retention circuits that are physically different from each other.

Each of the retention circuits FF00to FF77of the column units CUS0to CUS7latches data in synchronism with a clock signal when one of the enable signals EN00to EN77having a same digit at the end indicates the logic1. For example, the retention circuit FF00latches data when the enable signal EN00indicates the logic1, and the retention circuit FF10latches data when the enable signal EN10indicates the logic1. InFIG. 10, the upper one of the two digits applied to the end of the individual retention circuits FF, data lines DO and data lines DS indicates the number of the column unit CUS, and the lower one of the two digits indicates the number of the memory bus MB to which data is outputted.

FIG. 11depicts an example of the memory output selector unit depicted inFIG. 6. The memory output selector unit52selects one of data of 256 bits supplied to the data line DS in response to the value of the lower 3 bits of the selection signal SEL and outputs the selected data to the memory bus MB. For example, when the lower 3 bits of the selection signal SEL indicate “2,” the memory output selector unit52outputs data of 256 bits supplied to the data lines DS20to DS27to the memory bus MB. When the lower 3 bits of the selection signal SEL indicate “6,” the memory output selector unit52outputs data of 256 bits supplied to the data lines DS60to DS67to the memory bus MB. It is to be noted that, when the logic of the most significant bit of the selection signal SEL indicates an invalid state, the memory output selector unit52stops outputting of data to the memory bus MB, and the memory bus MB outputs the 0 level.

FIG. 12depicts an example of the register unit depicted inFIG. 5. The register unit22includes register files RF0to RF7coupled to the register buses RB0to RB7, respectively. Each of the register files RF0to RF7includes a plurality of storage regions for storing data of 32 bits. InFIG. 12, a word WL (WL0to WL7: corresponding to word WL depicted inFIG. 13) is constructed from eight storage regions of 32 bits arranged in a horizontal direction. An example of an internal structure of the register files RF0to RF7is depicted inFIG. 13.

Writing of data into the register unit22in accordance with the load instruction Id is executed, for example, for each word WL, and readout of data from the register unit22in accordance with the store instruction st is executed for each word WL. The arithmetic operation execution unit20depicted inFIG. 5executes, for example, an arithmetic operation for each data stored in one of the words WL. This is because the arithmetic operation execution unit20reads out data for each word WL through the register buses RB. At this time, it is possible to take out one data from each of the register buses RB0to RB7at the same time.

Therefore, when eight data are taken out at one time, one data is extracted from each of the register buses RB0to RB7. For example, data of a plurality of words WL is not taken out from one register bus RB. In such a case, data that may be arithmetically operated simultaneously may be arranged in the register files RF by storing data in a transposed relation into the register files RF.

FIG. 13depicts an example of the register file depicted inFIG. 12. Since the register files RF0to RF7include a same structure with each other, the register file RF0is described below.

The register file RF0includes memory cells MC of a static random access memory (SRAM) arranged in a matrix, a word decoder WDEC, a read/write controlling circuit RWC, a write amplifier WA and a read amplifier RA. The memory cells MC arrayed in a horizontal direction inFIG. 13are each coupled to one of 1024 word lines WL (WL0, WL1, WL2, . . . , and WL1023), and the memory cells MC arranged in a vertical direction inFIG. 13are each coupled to one of 32 sets of bit line pairs BL and /BL (BL0and /BL0, BL1and /BL1, . . . , and BL31and /BL31). In the register files RF0to RF7, memory cells MC coupled to word lines WL having a same number with each other belong to the same word WL. The number of word lines WL is not limited to 1024.

The word decoder WDEC drives (selects) one of the word lines WL based on a register address raddr designated by the load instruction Id, store instruction st or the like and the selection signal SEL0or an enable signal EN00to EN07. The register address raddr indicates the number of a word line WL with which access is started, and the value of the selection signal SEL0and the enable signals EN00to EN07indicate a relative position from the word line WL with which access is started.

For example, when the register address raddr indicates the word line WL0and the selection signal SEL0indicates “1,” the word decoder WDEC selects the word line WL1. When the register address raddr indicates the word line WL1and the selection signal SEL0indicates “1,” the word decoder WDEC selects the word line WL2. When the register address raddr indicates the word line WL0and the enable signal EN01is received, the word decoder WDEC selects the word line WL1. When the register address raddr indicates the word line WL1and the enable signal EN01is received, the word decoder WDEC selects the word line WL2. The word decoder WDEC of the other register files RF1to RF7operates similarly to the word decoder WDEC of the register file RF0except that the selection signals SEL0to SEL7and the enable signals EN00to EN77received are different.

By supplying the selection signals SEL0to SEL7different from each other to the register files RF0to RF7, respectively, the timings at which transposed data are written into the memory cells MC coupled to the respective word lines WL of the register files RF0to RF7may be controlled independently of each other as depicted inFIG. 15. By supplying the enable signals EN00to EN77different from each other to the register files RF0to RF7, respectively, the timings at which data are read out from the memory cells MC coupled to the respective word lines WL of the register files RF0to RF7may be controlled independently of each other as depicted inFIG. 17. Accordingly, the circuit for generating control signals for controlling operation of the register files RF0to RF7may be simplified in comparison with that in an alternative case in which the memory cells MC coupled to the word lines WL, the selection signals SEL0to SEL7and the enable signals EN00to EN77are not used.

Each memory cell MC includes a storage node MN having a pair of inverters coupled such that an output of one of the inverters is coupled to an input of the other one of the inverters and an output of the other one of the inverters is coupled to an input of the one of the inverters, and further includes transfer transistors T1and T2that couple the storage node MN to the bit lines BL and /BL. When the word line WL coupled to the memory cell MC is driven (for example, to the high level), the transfer transistors T1and T2couple one end of the storage node MN to the bit line BL and couple the other end of the storage node MN to the bit line /BL. In a writing operation for writing data into the memory cell MC, the logic0or the logic1is written into the storage node MN based on the logic of complementary data on the bit lines BL and /BL. In a reading out operation for reading out data from the memory cell MC, the logic stored in the storage node MN and the inverted logic are read out to the bit lines BL and /BL, respectively.

The read/write controlling circuit RWC outputs a write enable signal WREN in response to reception of the selection signal SEL0and outputs a read enable signal RDEN in response to reception of one of the enable signals EN00to EN07. The read/write controlling circuit RWC in each of the other register files RF1to RF7operates similarly to the read/write controlling circuit RWC of the register file RF0except that the selection signals SEL0to SEL7and the enable signals EN00to EN77received are different.

The write amplifier WA outputs data of 32 bits received from the register bus RB0as complementary data to the 32 bit line pairs BL and /BL in response to the write enable signal WREN. The read amplifier RA outputs data of 32 bits outputted from the memory cells MC to the 32 bit line pairs BL and /BL to the register bus RB0in response to the read enable signal RDEN. To each of the bit line pairs BL and /BL, a sense amplifier for amplifying the potential difference between the bit line pairs BL and /BL may be coupled.

FIG. 14depicts an example of operation of the memory input selector unit depicted inFIG. 7. For example,FIG. 14depicts an example of a control method of the arithmetic processing apparatus110. InFIG. 14, data #0to #63of 2048 bits are read out successively twice from the memory210in accordance with two load instructions Id. For example, each load instruction Id designates the transfer length length indicated in the expression (1) to 256 bytes. The load/store engine16depicted inFIG. 5repeats twice an operation for successively outputting 256 bits (data group) from among the data #0to #63of 2048 bits read out from the memory210for each cycle (cycle0to cycle7and cycle8to cycle15). Each of the data #0to #63includes 32 bits. Further, the load/store engine16outputs a valid signal LVALID not depicted together with each data group in accordance with an instruction from the state machine14. The cycle indicates a clock cycle.

Every time the buffer input controller34A receives a valid signal LVALID, it successively outputs one of enable signals EN0to EN7and outputs a transfer start signal TS1when the valid signal LVALID is received. The memory input selector unit40outputs data of 256 bits successively received through the memory buses MB (MB0to MB7) to one of the column units CUL0to CUL7in synchronism with each of the enable signals EN0to EN7. Using eight cycles, the data #0to #63of 2048 bits of eight data groups are stored into the column units CUL0to CUL7for the individual data groups.

The number of each of the retention circuits FF into which the data #0to #63are stored is indicated, inFIG. 14, at the upper side or the lower side of the data #0to #63transmitted to the memory buses MB0to MB7. For example, the first data group #0to #7is stored into the column unit CUL0; the second data group #8to #15is stored into the column unit CUL1; and the third data group #16to #23is stored into the column unit CUL2.

FIG. 15depicts an example of operation of the register output selector unit depicted inFIG. 8. For example,FIG. 15depicts an example of a control method of the arithmetic processing apparatus110. The operation depicted inFIG. 15is executed in parallel to the operation depicted inFIG. 14. For example,FIG. 15depicts operation of the register output selector unit44executed in accordance with two load instructions Id.

The buffer output controller36A depicted inFIG. 6outputs, in response to that a transfer start signal TS1is received from the buffer input controller34A, a selection signal SEL0indicating “0” to “7” to the selector440depicted inFIG. 8for each cycle. The buffer output controller36A outputs a selection signal SEL1indicating “0” to “7” to the selector441depicted inFIG. 8for each cycle in response to reception of the second transfer start signal TS1. The buffer output controller36A successively outputs each of the selection signals SEL2to SEL7indicating “0” to “7” to the selectors442to447depicted inFIG. 8based on the counter38A activated in response to the transfer start signal TS1. Thereafter, the buffer output controller36A starts operation for successively outputting selection signals SEL0to SEL7indicating “0” to “7” to the selectors440to447in response to the transfer start signals TS1successively received over the cycle9to the cycle16.

The selector440successively selects the data #0to #7outputted from the column unit CUL0in response to the value of the selection signal SEL0and outputs the selected data #0to #7to the data line D0. The selector441successively selects the data #8to #15outputted from the column unit CUL1in response to the value of the selection signal SEL1and outputs the selected data #8to #15to the data line D1. Similarly, the selectors442to447successively select data outputted from the column units CUL2to CUL7in response to the value of the corresponding selection signals SEL2to SEL7and output the selected data to one of the data lines D2to D7.

The data lines D0to D7are coupled to the register buses RB0to RB7, respectively, by the crossbar switch46depicted inFIG. 6. As described with reference toFIG. 13, each of the register files RF0to RF7generate a write enable signal WREN in response to the respective selection signals SEL0to SEL7. Therefore, the data outputted to each of the data lines D0to D7is stored into the respective register files RF0to RF7through the respective register buses RB0to RB7. In each of the register files RF0to RF7, the region into which data of 32 bits is stored is determined based on the register address raddr included in the load instruction Id and the values of the selection signals SEL0to SEL7. For example, since the register addresses raddr included in the first and second load instructions Id are different from each other, the data are stored into memory cells MC coupled to the respective word lines WL which are different form each other.

As depicted inFIG. 14, the first data #0to #7from among the data of 2048 bits supplied in accordance with the second load instruction Id are stored into the column unit CUL0in the cycle8. In each of the retention circuits FF of the column units CUL0to CUL7, writing of data is executed after reading out of data. For example, the data #0to #7from among the data of 2048 bits supplied first have been transferred to the register file RF0before the cycle8, data overwriting does not occur. Similarly, in the cycle9, since the first data #8to #15retained by the column unit CUL1are transferred to the register file RF1before the second data #8to #15are stored into the column unit CUL1, overwriting of data does not occur. Also in regard to any other column unit CUL, first data are transferred to the register file RF before second data are stored.

Therefore, also where data supplied in accordance with a plurality of load instructions Id are stored into the transposition buffer42successively without a break, it is possible to transpose data without losing data and store the transposed data into the register files RF0to RF7. For example, it is possible to transpose data, which are supplied successively in accordance with a plurality of load instructions Id, for example, using the single transposition buffer42that retains data of 2048 bits corresponding to one load instruction Id.

The operation for transposing data corresponding to a plurality of load instructions Id using the single transposition buffer42is made possible by generating values of the selection signals SEL0to SEL7respectively corresponding to the selectors440to447in a displaced relation from each other. Consequently, the selectors440to447that operate receiving the selection signals SEL0to SEL7may select data groups retained in the respective column units CUL0to CUL7in the cycles displaced from each other.

By successively outputting data included in data groups in cycles beginning with a cycle next to a cycle in which the data groups are retained into the transposition buffer42, also in a case in which the data are outputted in a displaced relation, it is possible to store the data into the register files RF0to RF7in a minimized number of cycles. For example, after each data group is retained into the transposition buffer42, transfer of the data to the register files RF may be completed in eight cycles. It is possible to make the data transfer rate when data are successively stored into the register unit22in response to a plurality of load instructions Id equal to the data transfer rate by a transposition unit18C including two transposition buffers42aand42bindicated inFIG. 22hereinafter described.

FIG. 16depicts an example of operation of the processor core120depicted inFIG. 5upon execution of a load instruction Id. For example, data #0to #63are stored in the memory210, and the data #0to #7, #8to #15, #16to #23, #24to #31, #32to #39, #40to #47, #48to #55and #56to #63are successively read out in a unit indicated by a thick frame from the memory210.

When the transposition flag trans described in the operand of the load instruction Id is “1,” data of 2048 bits read out from the memory210are stored into the register unit22through the transposition buffer42. In this case, into the register unit22, data of an array transposed from the array of the data stored in the memory210are retained as indicated in a right upper portion inFIG. 16. For example, in the register unit22, data groups of thick frames read out from the memory210are stored into the register files RF0to RF7. The register unit22into which data supplied from the transposition buffer42are stored may be an example of a first register unit, and the register files RF0to RF7including words WL into which data supplied from the transposition buffer42are stored may be an example of a first register file.

When the transposition flag trans described in the operand of the load instruction Id is “0,” data of 2048 bits read out from the memory210are stored into the register unit22without intervention of the transposition buffer42. In this case, as indicated in a right lower portion inFIG. 16, into the register unit22, data that maintain the array of the data stored in the memory210are retained. For example, into the register unit22, data groups of units of a thick frame read out from the memory210are retained in a distributed manner into the register files RF0to RF7of one word WL.

The data stored in the register unit22are used in an arithmetic operation executed, for example, in accordance with an arithmetic instruction. By the arithmetic instruction, data of 32 bits retained in the register files RF0to RF7are individually transferred to eight arithmetic units, by which an arithmetic operation of the data is executed with data of 32 bits retained in different words WL of the register files RF0to RF7. Where the data are data of 2048 bits, an arithmetic operation is executed by eight times. A result of execution of each arithmetic operation is stored into different words WL of the register files RF0to RF7.

An arithmetic operation by the eight arithmetic units is executed using data of 256 bits retained in each of the register files RF0to RF7. Therefore, where individual target data by the eight arithmetic operations are #0to #7, #8to #15, . . . , and #56to #63, data read out from the memory210are stored into the register files RF0to RF7without being transposed. On the other hand, when the target data of the arithmetic operation are #0, #8, #16, #24, #32, #40, #48, #56and so forth, data read out from the memory210are transposed by the transposition buffer42and stored into the register files RF0to RF7.

FIG. 17depicts an example of operation of the register input selector unit depicted inFIG. 9. For example,FIG. 17depicts an example of a control method of the arithmetic processing apparatus110. In the example depicted inFIG. 17, data #0to #63of 2048 bits are successively read out twice from the register unit22in response to two store instructions st. In the following, reading out of data #0to #63of 2048 bits from the register unit22in accordance with the first store instruction st is described. Also reading out of the data #0to #63of 2048 bits from the register unit22in accordance with the second store instruction st is executed similarly.

The load/store engine16depicted inFIG. 5outputs a valid signal SVALID in accordance with an instruction from the state machine14at a timing at which the transposition unit18receives first data. The buffer input controller34B successively outputs enable signals EN00to EN07in response to reception of the first valid signal SVALID and successively outputs enable signals EN10to EN17in response to reception of the valid signal SVALID.

Thereafter, every time the valid signal SVALID is received, the buffer input controller34B successively outputs enable signals EN00to EN07, EN10to EN17, EN20to EN27, EN30to EN37, EN40to EN47, EN50to EN57, EN60to EN67, and EN70to EN77. The buffer input controller34B outputs a transfer start signal TS2(FIG. 6) to the buffer output controller36B together with the enable signal EN07.

The enable signals EN00to EN77are supplied also to the register files RF0to RF7as described with reference toFIG. 13and are used also for operation for reading out data from given words WL (FIG. 12) of the register files RF0to RF7. Data read out from the given words WL of the register files RF0to RF7are supplied to the data lines D0to D7through the register buses RB0to RB7. In the register files RF0to RF7, a word WL from which data are read out in accordance with a store instruction st is an example of a second register file, and the register unit22including the second register file is an example of a second register unit.

The register input selector unit48successively stores the data #0to #7supplied to the data line D0into the retention circuits FF00to FF07of the transposition buffer50in accordance with the enable signals EN00to EN07. The register input selector unit48successively stores the data #8to #15supplied to the data line D1into the retention circuits FF10to FF17of the transposition buffer50in accordance with the enable signals EN10to EN17. Similarly, the register input selector unit48successively stores the data #16to #63supplied to the respective data lines D2to D7into the retention circuits FF30to FF77of the transposition buffer50in accordance with the enable signals EN20to EN77. The number of each of the retention circuits FF into which each of the data #0to #63is stored is indicated at the upper side or the lower side of the data #0to #63transmitted to the data lines D0to D7inFIG. 17.

FIG. 18depicts an example of operation of the memory output selector unit depicted inFIG. 11. For example,FIG. 18depicts an example of a control method of the arithmetic processing apparatus110. The operation depicted inFIG. 18is executed in parallel to the operation depicted inFIG. 17. The buffer output controller36B depicted inFIG. 6successively outputs selection signals SEL indicating “0” to “7” in response to reception of a transfer start signal TS2from the buffer input controller34B. The buffer output controller36B may include a counter for generating the selection signals SEL.

The memory output selector unit52outputs the data #0to #7retained in the retention circuits FF00to FF07of the transposition buffer50to the memory buses MB (MB0to MB7) in accordance with the selection signal SEL0. The memory output selector unit52outputs the data #8to #15retained in the retention circuits FF10to FF17of the transposition buffer50to the memory buses MB in response to the selection signal SEL1. Similarly, the memory output selector unit52successively outputs the data #16to #63retained in the retention circuits FF20to FF77of the transposition buffer50to the memory buses MB in accordance with the selection signals SEL2to SEL7. The number of each of the retention circuits FF into which each of the data #0to #63is stored is indicated at the upper side or the lower side of the data #0to #63transmitted to the memory buses MB0to MB7inFIG. 18. The data #0to #63retained in the transposition buffer50are written into the memory210by the memory controller130.

InFIG. 17, in each of the retention circuits FF of the transposition buffer50, writing of data is executed after reading out of data. Therefore, the data group #0to #7successively read out from the register unit22in accordance with the first store instruction st are outputted from the transposition buffer50before the data #0is read out from the register unit22in the cycle8in accordance with the second store instruction st. Similarly, the data group #8to #15successively read out from the register unit22in accordance with the first store instruction st are outputted from the transposition buffer50before the data #8is read out from the register unit22in the cycle9in accordance with the second store instruction st. Also the other data groups successively read out from the register unit22in accordance with the first store instruction st are outputted from the transposition buffer50before data are read out from the register unit22in accordance with the second store instruction st.

Accordingly, also when data are read out without a break from the register unit22and are transposed in accordance with a plurality of store instructions st, read out data may be written into the memory210through the transposition buffer50without being lost. For example, data successively read out from the register unit22in accordance with a plurality of store instructions st may be transposed using the single transposition buffer50that retains data of 2048 bits corresponding to one store instruction st.

The operation for transposing data corresponding to a plurality of store instructions st using the single transposition buffer50may be achieved by generating the enable signals EN00to EN77corresponding to the respective selectors480to487in a displaced relation from each other. This makes it possible for the selectors480to487, which operate in response to the enable signals EN00to EN77, to select data to be read out from the register unit22in cycles displaced from each other.

The memory output selector unit52outputs each data group to the memory buses MB in a cycle next to the cycle in which storage of data included in each of the data groups into the transposition buffer50is completed. Consequently, also when data are successively read out from the register unit22in cycles displaced from each other, the data may be written into the memory210in a minimized number of cycles. For example, each data group may be written into the memory210after eight cycles after the first data of the data group is read out from the register unit22. For example, the data transfer rate when data are successively read out from the register unit22in accordance with a plurality of store instructions st may be equal to the data transfer rate by the transposition unit18C that includes two transposition buffers50aand50bdepicted inFIG. 22hereinafter described.

The operation for transposing the array of data read out from the register files RF0to RF7and storing the data into the memory210may be explained by replacing the transposition buffer42ofFIG. 16into the transposition buffer50and reversing the direction of arrow marks between the memory210and the register unit22.

FIG. 19depicts an example of operation of the arithmetic processing apparatus depicted inFIG. 5. For example,FIG. 19depicts an example of a control method of the arithmetic processing apparatus110. A flow depicted inFIG. 19is started in response to decoding of an instruction by the decoder12depicted inFIG. 5. If the decoder12decodes a load instruction Id in operation S10, the operation is advanced to operation S12, but if the decoder12does not decode a load instruction Id, the operation is advanced to operation S14.

In operation S12, the processor core120depicted inFIG. 5executes the load instruction Id and ends its operation. An execution flow of the load instruction Id by in operation S12is depicted inFIG. 20. If the decoder12decodes an arithmetic instruction in operation S14, the operation is advanced to operation S16, but if the decoder12does not decode an arithmetic instruction, the operation is advanced to operation S18. In operation S16, the processor core120depicted inFIG. 5executes the arithmetic instruction and ends the operation.

If the decoder12decodes a store instruction st in operation S18, the operation is advanced to S20, but if the decoder12does not decode a store instruction st, the operation is ended. In operation S20, the processor core120depicted inFIG. 5executes the store instruction st and ends the operation. An execution flow of the store instruction st in operation S20is depicted inFIG. 21.

FIG. 20depicts an example of an operation flow of the load instruction Id executed in S12ofFIG. 19. First, in operation S120, the load/store engine16depicted inFIG. 5reads out data to be loaded from the memory210. After operation S120, the operation is advanced to operation S122.

If data are to be transposed in operation S122, the operation is advanced to operation S124, but if data are not to be transposed, the operation is advanced to operation S128. In operation S124, the transposition unit18depicted inFIG. 6successively stores the data read out from the memory210into the transposition buffer42. In operation S126, every time the transposition unit18stores data into the transposition buffer42, it successively reads out the data stored in the transposition buffer42in cycles displaced from each other and stores the data into the register files RF0to RF7. The data are transposed in the process in which they are stored into the register unit22through the transposition buffer42. As depicted inFIGS. 14 and 15, the operations in operations S124and S126are executed in parallel. After operations S124and S126, the operation is ended.

In operation S128, the transposition unit18stores the data read out from the memory210in order to use them for an arithmetic operation into the register files RF0to RF7through the bypass route BYPS, and ends the operation.

FIG. 21depicts an example of an operation flow of a store instruction executed in operation S20ofFIG. 19. When data are to be transposed in operation S200, the operation is advanced to operation S202, but when data are not to be transposed, the operation is advanced to operation S206. In operation S202, the transposition unit18depicted inFIG. 6successively reads out data retained by the word WL of a readout target in the register files RF0to RF7in cycles displaced from each other and stores the read out data into the transposition buffer50.

In operation S204, the transposition unit18outputs, every time a data group is prepared in the transposition buffer50, the data group to the memory210. As depicted inFIGS. 17 and 18, the operations in operations S202and S204are executed in parallel. After operations S202and S204, the operation is ended.

In operation S206, the transposition unit18reads out data retained by the word WL of a readout target in the register files RF0to RF7and writes the read out data into the memory210through the bypass route BYPS, and ends the operation.

FIG. 22depicts another example of a transposition unit. The same elements as those inFIG. 6are denoted by the same reference symbols and detailed description of the same is omitted. For example, the transposition unit18C depicted inFIG. 22is incorporated in the processor core120in place of the transposition unit18depicted inFIG. 5.

The transposition unit18C includes two transposition buffers42aand42bthat retain data of 2048 bits read out from the memory210(FIG. 5) through the memory bus MB in order to transpose the data. Further, the transposition unit18C includes two transposition buffers50aand50bthat retain data of 2048 bits read out from the register files RF0to RF7in order to transpose the data.

The transposition unit18C includes data shift controllers32D and32E, memory input selector units40Ca and40Cb, register output selector units44Ca and44Cb, a crossbar switch46, register input selector units48Ca and48Cb and memory output selector units52Ca and52Cb. The data shift controller32D includes a buffer input controller34D and a buffer output controller36D including a counter38D. The data shift controller32E includes a buffer input controller34E including a counter38E, and a buffer output controller36E.

The buffer input controller34D has functions similar to those of the buffer input controller34A depicted inFIG. 6except that it outputs one of the enable signals EN (ENa0to ENa7and ENb0to ENb7). Further, the buffer input controller34D outputs a transfer start signal TS1aafter seven cycles after outputting of the enable signal ENa0and outputs a transfer start signal TS1bafter seven cycles after outputting of the enable signal ENb0.

The buffer output controller36D has functions similar to those of the buffer output controller36A depicted inFIG. 6except that it outputs selection signals SELda and SELdb in place of the selection signals SEL0to SEL7. The buffer output controller36D controls the counter38D to generate lower 3 bits of the selection signal SELda of 4 bits in response to reception of the transfer start signal TS1a. Further, the buffer output controller36D controls the counter38D to generate lower 3 bits of the selection signal SELdb of 4 bits in response to reception of the transfer start signal TS1b. In the selection signals SELda and SELdb, when the most significant one bit is valid, the lower 3 bits are valid.

The memory input selector units40Ca and40Cb each include a configuration same as that of the memory input selector unit40depicted inFIG. 7. The memory input selector unit40Ca outputs data of 256 bits received through the memory bus MB to one of eight data lines (256 bits) in response to the enable signals ENa0to ENa7. The memory input selector unit40Cb outputs data of 256 bits received through the memory bus MB to one of the eight data lines (256 bits) in response to the enable signals ENb0to ENb7. The enable signals ENa0to ENa7are used to output data to the transposition buffer42a, and the enable signals ENb0to ENb7are used to output data to the transposition buffer42b. An example of operation of the memory input selector units40Ca and40Cb is depicted inFIG. 26.

The transposition buffer42aoutputs data of 2048 bits retained therein to data lines DLa (DLa00to DLa77), and the transposition buffer42boutputs data of 2048 bits retained therein to the data lines DLb (DLb00to DLb77). The data lines DLa00to DLa77correspond to DL0° to DL77depicted inFIG. 7, respectively, and the data lines DLb00to DLb77correspond to the data lines DL00to DL77depicted inFIG. 7, respectively. The data lines DLa00to DLa77and the data lines DLb00to DLb77are each a 32-bit line and, for example, the data lines DLa00to DLa07transmit 256 bits. For example, the data lines DLa00to DLa07are coupled to the column unit CUL0of the transposition buffer42a, and the DLb70to DLb77are coupled to the column unit CUL7of the transposition buffer42b.

The register output selector unit44Ca outputs data received through the data lines DLa (DLa00to DLa77) to the data lines D0to D7in response to the selection signal SELda. The register output selector unit44Cb outputs data received through the data lines DLb (DLb00to DLb77) to the data lines D0to D7in response to the selection signal SELdb. An example of the register output selector units44Ca and44Cb is depicted inFIG. 23.

The buffer input controller34E has functions similar to those of the buffer input controller34B depicted inFIG. 6except that it outputs enable signals ENa00to ENa77and ENb00to ENb77in place of the enable signals EN00to EN77. The buffer input controller34E controls the counter38E to operate every time it receives a valid signal SVALID outputted from the load/store engine16depicted inFIG. 5. The buffer input controller34E outputs enable signals ENa00to ENa77and ENb00to ENb77in response to a counter value counted by the counter38E.

Further, the buffer input controller34E includes a counter38E. The buffer input controller34E controls the counter38E to start counting in accordance with a timing at which data are outputted to the data lines D from each of the register files RF0to RF7. The buffer input controller34E controls the counter38E to generate enable signals ENa00to ENa77or enable signals ENb00to ENb77. An example of the enable signals ENa00to ENa77and ENb00to ENb77generated by the counter38E is depicted inFIG. 28.

The register input selector unit48Ca outputs data supplied to the data lines D0to D7through the crossbar switch46to the transposition buffer50athrough the data lines DOa0to DOa7in response to the enable signals ENa00to ENa77. The register input selector unit48Cb outputs data supplied to the data lines D0to D7through the crossbar switch46to the transposition buffer50bthrough the data lines DOb0to DOb7in response to the enable signals ENb00to ENb77. An example of the register input selector units48Ca and48Cb is depicted inFIG. 24.

Each of the transposition buffers50aand50bincludes a configuration same as that of the transposition buffer50depicted inFIG. 10. The transposition buffer50aretains data of 2048 bits supplied to the data lines DOa0to DOa7and outputs the retained data to the data lines DSa (DSa00to DSa77). The transposition buffer50bretains data of 2048 bits supplied to the data lines DOb0to DOb7and outputs the retained data to the data lines DSb (DSb00to DSb77).

The memory output selector unit52Ca selects data received through the data lines DSa in response to the selection signal SELea and outputs the selected data to the memory bus MB. The memory output selector unit52Cb selects data received through the data lines DSb in response to the selection signal SELeb and outputs the selected data to the memory bus MB. An example of the memory output selector units52Ca and52Cb is depicted inFIG. 25.

FIG. 23depicts an example of the register output selector unit depicted inFIG. 22. Each of the register output selector units44Ca and44Cb includes a configuration same as that of the register output selector unit44depicted inFIG. 8except that it receives a common selection signal SELda or a common selection signal SELdb in place of the selection signals SEL0to SEL7. The register output selector unit44Ca includes eight selectors that output data individually to the data lines D0to D7. When the value of the lower 3 bits of the selection signal SELda is one of “0” to “7,” the eight selectors select 32 bits from data of 256 bits retained by each of the column units CUL0to CUL7of the transposition buffer50ain response to the value of the selection signal SELda and outputs the 32 bits to one of the data lines D0to D7. The register output selector unit44Cb includes eight selectors that output data individually to the data lines D0to D7. When the value of the lower 3 bits of the selection signal SELdb is one of “0” to “7,” the eight selectors select 32 bits from data of 256 bits retained by each of the column units CUL0to CUL7of the transposition buffer50bin response to the value of the selection signal SELdb and outputs the 32 bits to one of the data lines D0to D7.

FIG. 24depicts an example of the register input selector unit depicted inFIG. 22. Each of the register input selector units48Ca and48Cb includes a configuration same as that of the register input selector unit48depicted inFIG. 9except that it receives an enable signal ENa or an enable signal ENb in place of the enable signal EN. The register input selector unit48Ca includes eight selectors480Ca,481Ca, . . . , and487Ca that couple the data lines D (D0to D7) to the data lines DOa (DOa0to DOa7). Each of the selectors480Ca,481Ca, . . . , and487Ca couples a data line to a data line DOa in response to the enable signal ENa. The register input selector unit48Cb includes eight selectors480Cb,481Cb, . . . , and487Cb that couple the data lines D (D0to D7) to the data lines DOb (DOb0to DOb7). Each of the selectors480Cb,481Cb, . . . , and487Cb couples a data line to a data line DOb in response to the enable signal ENb.

FIG. 25depicts an example of the memory output selector unit depicted inFIG. 22. Each of the memory output selector units52Ca and52Cb includes a configuration same as that of the memory output selector unit52C depicted inFIG. 11except that it receives selection signals SELea and SELeb in place of the selection signal SEL. When the lower 3 bits of the selection signal SELea indicate “2,” the memory output selector unit52Ca outputs data of 256 bits supplied to the data lines DSa20to DSa27to the memory buses MB. If the lower 3 bits of the selection signal SELeb indicates “6,” the memory output selector unit52Cb outputs data of 256 bits supplied to the data lines DSb60to DSb67to the memory buses MB. If the logic of the most significant bit of the selection signals SELea and SELeb indicates an invalid state, the memory output selector units52Ca and52Cb stop outputting of data to the memory buses MB.

FIG. 26depicts an example of operation of the memory input selector unit depicted inFIG. 22. In the example depicted inFIG. 26, data #0to #63of 2048 bits are read out successively twice from the memory210in accordance with two load instructions Id. The data of 2048 bits read out first are stored into the retention circuit FFa of the transposition buffer42a, and the data of 2048 bits read out for the second time are stored into the retention circuit FFb of the transposition buffer42b. The retention circuits FFa and FFb (for example, column units CUL0to CUL7) that retain data are selected in response to the enable signals ENa0to ENa7and ENb0to ENb7.

FIG. 27depicts an example of operation of the register output selector unit depicted inFIG. 22. The operation depicted inFIG. 27is executed in parallel to the operation depicted inFIG. 26. The register output selector unit44Ca selects 32 bits from each of the column units CUL0to CUL7of the transposition buffer42ain response to the value of the selection signal SELda and outputs the selected data to the data lines D0to D7. Meanwhile, the register output selector unit44Cb selects 32 bits from each of the column units CUL0to CUL7of the transposition buffer42bin response to the value of the selection signal SELdb and outputs the selected data to the data lines D0to D7. Consequently, data retained in the transposition buffers42aand42bare transposed and stored into the register files RF0to RF7. It is to be noted that the data retained in the transposition buffer42aand the data retained in the transposition buffer42bare stored into words WL different from each other in the register files RF0to RF7without overlapping with each other.

As depicted inFIGS. 26 and 27, since data of 2048 bits are retained alternately into the two transposition buffers42aand42b, it is possible to successively generate transposition data without losing any data and store the generated transposition data into the register files RF0to RF7. For example, the transposition unit18C depicted inFIG. 22may execute a transposition operation similar to that ofFIGS. 14 and 15. However, in this case, the number (128) of retention circuits FF incorporated in the transposition buffers42aand42bis twice the number (64) of retention circuits FF incorporated in the transposition buffer42depicted inFIG. 6. For example, the number (4096) of flip-flops incorporated in the transposition buffers42aand42bis twice the number (2048) of flip-flops incorporated in the transposition buffer42.

FIG. 28depicts an example of operation of the register input selector unit depicted inFIG. 22. The register input selector unit48Ca outputs data successively supplied to the data lines D0to D7to the data lines DOa0to DOa7in response to the enable signals ENa00to ENa77. Consequently, the data supplied to the data lines D0to D7are stored into the transposition buffer50a. The register input selector unit48Cb outputs data successively supplied to the data lines D0to D7to the data lines DOb0to DOb7in response to the enable signals ENb00to ENb77. Consequently, the data supplied to the data lines D0to D7are stored into the transposition buffer50b.

FIG. 29depicts an example of operation of the memory output selector unit depicted inFIG. 22. The operation depicted inFIG. 29is executed in parallel to the operation depicted inFIG. 28. The memory output selector unit52Ca selects one of data of 256 bits retained by the column units CUL0to CUL7of the transposition buffer50ain response to the value of the selection signal SELea and outputs the selected data to the memory buses MB (MB0to MB7). The memory output selector unit52Cb selects one of data of 256 bits retained by the column units CUL0to CUL7of the transposition buffer50bin response to the value of the selection signal SELeb and outputs the selected data to the memory buses MB (MB0to MB7). Then, the data read out from the register files RF0to RF7are transposed and written into the memory210.

By retaining data of 2048 bits alternately into the two transposition buffers50aand50bas depicted inFIGS. 28 and 29, the array of data read out successively from the register files RF0to RF7may be transposed without losing any data. For example, the transposition unit18C depicted inFIG. 22may execute a transposition operation similar to that ofFIGS. 17 and 18. However, in this case, the number (128) of retention circuits FF incorporated in the transposition buffers50aand50bis twice the number (64) of retention circuits FF incorporated in the transposition buffer50depicted inFIG. 6. For example, the number (4096) of flip-flops incorporated in the transposition buffers50aand50bis twice the number (2048) of flip-flops incorporated in the transposition buffer50b.

For example, in the transposition unit18depicted inFIG. 6, the number of retention circuits FF that operate in synchronism with a clock signal may be reduced to one half in comparison with the transposition unit18C depicted inFIG. 22. Accordingly, the circuit size of the transposition buffers42and50may be reduced to approximately one half the circuit size of the transposition buffers42a,42b,50aand50b. Further, the power consumption of the transposition buffers42and50may be reduced to approximately one half the power consumption of the transposition buffers42a,42b,50aand50b. As a result, the chip size of the arithmetic processing apparatus110depicted inFIG. 5may be reduced in comparison with the chip size of the arithmetic processing apparatus in which the transposition unit18C is incorporated. The power consumption of the arithmetic processing apparatus110depicted inFIG. 5may be reduced in comparison with power consumption of the arithmetic processing apparatus in which the transposition unit18C is incorporated.

As described above, inFIGS. 5 to 21, advantageous effects similar to those of the embodiment depicted inFIGS. 1 to 4may be achieved. For example, also where data to be transposed are successively supplied to the transposition buffer42, it is possible to transpose the data without losing any data and store the transposed data into the register unit22. Accordingly, the arithmetic operation execution unit20may execute a plurality of arithmetic operations successively using data read out successively from the memory210in response to a plurality of load instructions Id and transposed using the transposition buffer42.

Since data successively supplied may be transposed using the single transposition buffer42, the circuit scale may be reduced in comparison with that in an alternative case in which data are transposed using the two transposition buffers42aand42b(FIG. 22). Further, since data read out from the memory210and supplied through the bypass route BYPS are transferred to the register unit22through the crossbar switch46, the data may be stored into the register files RF0to RF7without being transposed.

In the embodiment depicted inFIGS. 5 to 21, for example, the following effects may be anticipated. Also when data are transferred from the register unit22to the transposition buffer50without a break in response to a plurality of store instructions st, it is possible to transpose data stored in the transposition buffer50by reading out the data without losing any data and write the transposed data into the memory210. Since data successively read out from the register unit22may be transposed using the single transposition buffer50, the circuit scale may be reduced in comparison with an alternative case in which data are transposed using the two transposition buffers50aand50b(FIG. 22). By transferring data read out from the register unit22to the bypass route BYPS through the crossbar switch46, the data may be written into the memory210without being transposed.

By selecting data retained in the column units CUL0to CUL7of the transposition buffer42using the selection signals SEL0to SEL7, the outputting timings of data to the data lines D0to D7may be controlled independently of each other. Consequently, even when data are successively supplied to the transposition buffer42, data retained in the column units CUL0to CUL7may be read out without being lost. Further, by supplying the selection signals SEL0to SEL7for controlling the register output selector unit44to the register files RF0to RF7, the timings at which transposed data are written into the words WL of the register files RF0to RF7may be controlled independently of each other.

By causing the selectors480to487of the register input selector unit48to select data to be successively read out from the register unit22to the data lines D0to D7using the enable signals EN00to EN77, the operation depicted inFIG. 17may be implemented. Further, by supplying the enable signals EN00to EN77for controlling the register input selector unit48to the register files RF0to RF7, data may be read out from the register unit22in accordance with operation timings of the register input selector unit48.

The number of retention circuits FF incorporated into the transposition buffers42and50may be reduced to one half the number of retention circuits FF incorporated in the transposition buffers42a,42b,50aand50bdepicted inFIG. 22. Therefore, the chip size of the arithmetic processing apparatus110depicted inFIG. 5may be reduced in comparison with the chip size of the arithmetic processing apparatus in which the transposition unit18C depicted inFIG. 22is incorporated. By reduction of the number of retention circuits FF, the power consumption of the transposition buffers42and50may be reduced to approximately one half the power consumption of the transposition buffers42a,42b,50aand50b. As a result, the power consumption of the transposition unit18of the arithmetic processing apparatus110depicted inFIG. 5may be reduced in comparison with the power consumption of the transposition unit18C depicted inFIG. 22.

Further, where the arithmetic processing apparatus18executes a plurality of load instructions Id successively, the transfer rate of data to be transferred from the memory210to the register unit22may be made equal to the transfer rate of data by the arithmetic processing apparatus18C. Further, where the arithmetic processing apparatus18executes a plurality of store instructions st successively, the transfer rate of data transferred from the register unit22to the memory210may be made equal to the transfer rate of data by the arithmetic processing apparatus18C. Accordingly, while the arithmetic processing apparatus18does not degrade the transfer efficiency of data, the chip size may be reduced and the power consumption may be reduced in comparison with the arithmetic processing apparatus18C.