Semiconductor structure with means for testing metal-insulator-metal capacitors

The present invention provides a semiconductor structure for testing MIM capacitors. The semiconductor structure comprises: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate with an insulation layer therebetween and connected with the second circuit area. The second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of China application serial no. 201310312455.2, filed Jul. 23, 2013. All disclosure of the China application is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to the field of semiconductor fabrication technology and particularly to a semiconductor structure for testing Metal-Insulator-Metal capacitors.

BACKGROUND OF THE INVENTION

Metal-Insulator-Metal (MIM) capacitors are capacitor structures formed between the interconnection layers of semiconductor devices. The Metal-Insulator-Metal capacitors are massively applied in CMOS devices such as RFICs (Radio-Frequency Integrated Circuits) and semiconductor memories due to the satisfying compatibility with the back-end-of-line (BEOL) processing during the semiconductor manufacturing.

Taken a MIM capacitor structure defined by 2 masks as an example, it comprises from top to bottom a first metal layer, a dielectric layer, a top plate, an insulation layer, a bottom plate, a dielectric layer and a second metal layer. The top plate and bottom plate can be led out to form the positive and negative poles through vertical via interconnections or BEOL line.

Considering that processing problems or defects during the MIM capacitor preparation process may cause breakdown or current leakage of the MIM capacitor, an effective measurement should be taken to determine whether an electric leakage exists in the MIM capacitor.

A semiconductor structure for testing a MIM capacitor in the prior art is provided. As shown inFIG. 1, in the semiconductor structure, a first metal layer110is configured to be an upper layer of the structure, comprising a first circuit area1100and a second circuit area1101. A second metal layer111is located right below the first metal layer110, and separated from the first metal layer110by a dielectric layer112located therebetween. A top plate120and a bottom plate121are oppositely disposed within the dielectric layer112without contacting the first metal layer110and the second metal layer111respectively. The top plate120is separated from the bottom plate121by an insulation layer122located therebetween. The first circuit area1100is connected with the top plate120through a circuit connection130, for example a vertical via interconnection or BEOL line, and the second circuit area1101is connected with the bottom plate121through a circuit connection131as well. The first metal layer110and the second metal layer111, together with the insulation layer122, form a MIM capacitor.

On one hand, since the conventional MIM capacitor is enclosed within insulating medium, the electric leakage regions existing in the insulating medium between the top plate and bottom plate is difficult to be detected through a voltage contrast mode due to the lack of a leakage path formed straight to the substrate. Therefore, it is hard to position the electric leakage regions in the MIM capacitor especially in large-size MIM capacitor.

On the other hand, by adopting a method of successively removing the layers covering the top plate of the MIM capacitor and then scanning the top plate in voltage contrast mode, unusual images representing obvious electric leakage regions can be observed. But for a slight electric leakage, it doesn't work well.

Thus, there is a need to design a semiconductor structure for detecting the electric leakage regions in a MIM capacitor completely and accurately.

SUMMARY OF THE INVENTION

Accordingly, at least one object of the present invention is to provide a semiconductor structure for testing MIM capacitor capable of completely and accurately detecting the electric leakage regions in the MIM capacitor.

In order to achieve the above object, a semiconductor structure with multi-layers for testing Metal-Insulator-Metal capacitor is provided, comprising:

a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween, and connected with the second circuit area;

a top plate located within the first dielectric layer closer to the first metal layer, and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate by an insulation layer lying therebetween, and connected with the second circuit area; wherein, the semiconductor structure is formed on a P-type substrate; the second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway which comprises the first electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.

Preferably, the semiconductor structure further comprises a third metal layer which is apart from the second metal layer with a second dielectric layer and apart from the substrate with a third dielectric layer, the third metal layer is electrically connected with the second metal layer and the substrate respectively to form the first electric pathway.

Preferably, the third metal layer is respectively connected with the second metal layer and the substrate through vertical via interconnections.

Preferably, the top plate comprises multiple plate regions arranged apart from each other, each plate region is electrically connected with the first circuit area.

Preferably, the top plate comprises 8 plate regions, with 4 plate regions evenly distributed along the length direction and 2 plate regions evenly distributed along the width direction, each plate region is uniform in size and shaped as a rectangular.

In the semiconductor structure of the present invention for testing MIM capacitor, a leakage path from the top plate straight to the substrate is formed when an electric leakage region exists in the insulation layer of the MIM capacitor, and thus the electric leakage region, however small, can be completely and accurately detected in the voltage contrast mode. The semiconductor structure is simple in preparation and low in cost. It promotes the efficiency of the failure analysis for the MIM capacitors, and it is especially suitable for quick positioning of the electric leakage regions in a large-size MIM capacitor.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The method of manufacturing dual gate oxide devices of the present invention will be described in further details hereinafter with respect to the embodiments and the accompanying drawings.

The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention.

According to one embodiment of the present invention, a semiconductor structure for testing a MIM capacitor is supplied, comprising: a first metal layer210, a second metal layer211, a top plate220and a bottom plate221. As shown inFIG. 2, the first metal layer210is configured to be the surface of the structure or an inside layer of the structure, which comprises at least a first circuit area2100and a second circuit area2101. The second metal layer211is located right below the first metal layer210, and separated from the first metal layer210by a first dielectric layer212located therebetween. Part of the second metal layer211is connected with the second circuit area2101. The top plate220is located within the first dielectric layer212closer to the first metal layer210than to the second metal layer211and is connected with the first circuit area2100. The bottom plate221, which is located oppositely to the top plate220within the first dielectric layer212closer to the second metal layer211, is separated from the top plate220by an insulation layer222disposed therebetween. The bottom plate221is also connected with the second circuit area2101. The first metal layer210, the second metal layer211together with the insulation layer222form a MIM capacitor.

The semiconductor structure is formed on a P-type substrate. The second metal layer211is connected with the substrate through a first electric pathway, so that a second electric pathway which comprises the first electric pathway is formed when electric leakage regions exist in the insulation layer222.

The material of the first dielectric layer212includes but not limited to SiO2.

In an embodiment of the invention, the semiconductor structure further comprises a third metal layer213which is electrically connected with the second metal layer211and is separated therefrom by a second dielectric layer214located therebetween. Additionally, the third metal layer213is electrically connected with the P-type substrate and is separated therefrom by a third dielectric layer216located between them. In this way, the first electric pathway, beginning from the second metal layer211and ending at the P-type substrate200, is formed.

More specifically, the first circuit area2100is electrically connected with the top plate200through at least one circuit connection230, such as the BEOL lines. The second circuit area2101is electrically connected with the bottom plate221and the second metal layer211through at least one circuit connection231and at least one circuit connection232respectively. The circuit connections230,231,232may be BEOL lines or vertical via interconnections.

Similarly, the third metal layer213is electrically connected with the second metal layer211and the P-type substrate200through circuit connections233,234respectively.

When electric leakage regions exist in the insulation layer222of the MIM capacitor, the second electric pathway beginning from the top plate220and ending at the substrate200is formed. The second electric pathway comprises the following branches: a first branch from the top plate220to the bottom plate221through the insulation layer222, a second branch from the bottom plate221to the second metal layer211through the second circuit area2101, and a third branch from the second metal layer211to the P-type substrate200which is defined as the first electric pathway mentioned above.

When the MIM capacitor is tested, any of the electric leakage regions, including tiny leakages, can be detected completely and accurately in the voltage contrast mode through the second electric pathway. Furthermore, the semiconductor structure is simple in preparation and low in cost.

It is noted that the semiconductor structure is only illustrated in a three-metal-layer form for convenience. In fact, a group of metal layers, even more than 10 metal layers, can be employed in the semiconductor structure when possible. Any one of the metal layers can be defined as the top plate or the bottom plate. Any semiconductor structure which comprises a leakage path beginning from the top plate and ending at the substrate can be used to test the MIM capacitors when electric leakage regions exist and should fall within the scope of the invention.

In the embodiment, the first electric pathway beginning from the second metal layer211and ending at the substrate200is formed by passing through the third metal layer213utilizing the vertical via interconnection, which is not limited thereto. In practice, in order to achieve the purpose of the invention, any form of electric connections, including but not limited to the BEOL lines or vertical via interconnections, can be used for connecting the top plate220with the substrate200to form the second pathway when the electric leakage regions exist in the MIM capacitor.

In another embodiment of the invention, the bottom plate221is formed in an integral plate, while the top plate220comprises multiple plate regions2201which are arranged apart from each other, as shown inFIG. 3. Each plate region2201is electrically connected with the first circuit area2100. In this way, each plate region2201is respectively led to the substrate200when electric leakage regions exist. Therefore the MIM capacitor can be considered to be composed of many small capacitors paralleled with each other. When an electric leakage region exists in the insulation layer222, the corresponding plate region2201thereof can be determined in the voltage contrast mode.

More specifically, the top plate220comprises 8 plate regions, with 4 plate regions evenly distributed along the length direction and 2 plate regions evenly distributed along the width direction, each plate region2201is uniform in size and shaped as a rectangular. The top plate and bottom plate are oppositely and parallel disposed with each other, with the area of the bottom plate221larger than that of the top plate220. The top plate220and bottom plate221can be made from TiN or TaN.

Since the top plate220comprises multiple plate regions2201, different electric leakage regions of the MIM capacitor can be simultaneously detected in the voltage contrast mode, which promotes the efficiency of the failure analysis for the MIM capacitor. The semiconductor structure of the invention is especially suitable for quick and accurate positioning of the electric leakage regions in a large-size MIM capacitor.

Although the present invention has been disclosed as above with respect to the preferred embodiments, they should not be construed as limitations to the present invention. Various modifications and variations can be made by the ordinary skilled in the art without departing the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.