Dual-memory driving of an electronic display

A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

SUMMARY

Methods and systems for reducing bandwidths, or amounts simultaneously transmitted, of image data transmitted and processed to prepare an image for presentation on an electronic display by implementing memory in pixels of the electronic display may provide immense value. Such an implementation of memory in the pixels may permit an elimination or reduction in size of a frame buffer associated with the electronic display. Having memory in the pixels may lessen the design complexity of electronic displays, as well, because the less image data that is concurrently transmitted to a pixel array of an electronic display, the simpler an electronic display may be designed. For example, the pixels may be programmed in smaller groups because memory in the pixel stores the values until a time of presentation of the image.

This disclosure describes an electronic display having one or more pixels that include memory and a driver that may help to decrease a bandwidth associated with transmitting and processing image data for presentation on an electronic display. The inclusion of the memory in the pixel may enable storage of image data prior to output to a light-emitting portion of the pixel. Thus, the memory in the pixel may reduce, or in some instances eliminate, a reliance on a frame buffer in an electronic display by acting as an individual frame buffer for the pixel. The memory in the pixel may be used in conjunction with a driver to cause a light-emitting portion of the pixel to emit light.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Electronic displays are found in numerous electronic devices, from mobile phones to computers, televisions, automobile dashboards, and many more. Electronic displays have achieved increasingly higher resolutions by reducing individual pixel size. Yet increasing resolutions may increase a difficultly associated with managing an increased amount of image data associated with the increased resolutions processed by processing circuitry prior to displaying an image, for example, by causing increased power consumption from processing increased amounts of image data. Furthermore, the increasing resolutions may increase a bandwidth used to communicate image data from the processing circuitry to a pixel array for presentation of the image because more image data is used to communicate the same image at a higher electronic display resolution.

Embodiments of the present disclosure relate to systems and methods for implementing memory-in-pixel circuitry that may be used as an individual frame buffer for each pixel. The systems and methods of this disclosure to implement memory-in-pixel circuitry may reduce transmission bandwidths of image data to pixel arrays for display because the pixel may store image data in the memory. In this way, a reliance on frame buffers to temporarily store the image data external to the pixel is reduced because the pixel has its own memory to store its own image data prior to display of the image data.

Memory may be implemented in pixel circuitry that includes a light-emitting diode (LED). An organic light-emitting diode (OLED) represents one type of LED that may be found in the pixel, but other types of LEDs or light-emitting elements may also be used. Other light-emitting or -permissive components that may be used in the pixel circuitry include components to support liquid crystal displays (LCDs), plasma display panels, and/or dot-matrix displays.

In some cases, some memory for each pixel may be included in the pixel circuitry while some memory for each pixel may be included in driving circuitry of the display. When memory implemented in the pixel is not used in combination with additional allocated external memory for the pixel, maximum bit depths for image data stored in memory may be constrained by physical footprint definitions specified for each pixel. For example, amount of memory used in each pixel, and thus the number of respective bits used to represent a target gray level for each pixel to reference when presenting an image, may be limited by an amount of space within a panel of a display dedicated for each pixel.

Separating the memory designated for each pixel in to the separate portions of the display may increase the amount of memory designated for each pixel and enable an increase in the number of respective bits used to represent the target gray level. For example, a same number of memory storage units may be included within the pixel as other memory-in-pixel panels but additional bits may be used to represent the target gray level as a result at least in part from including additional memory for the pixel in driving circuitry of the display, as will be appreciated.

Furthermore, in some cases, multiple driving cycles may be used to present one image frame. These multiple driving cycles may be thought of as “sub-frames,” where the same memory unit for a particular pixel may be loaded with data multiple times within a duration of time allocated for presentation of an image frame. When driving a display using sub-frames to present a whole frame, the sub-frame periods may be leveraged to break a target gray level up into sub-frame-based chunks. For example, a certain portion of bits representing the target gray level may be used to drive the display to emit light during a first sub-frame while a different portion of the bits representing the target gray level may be used to drive the display during a second sub-frame, where the emission of light over the two sub-frames emits light that appears as the target gray level for the overall image frame.

Displays using memory-in-pixel techniques may also implement memory allocated for the pixel disposed in a driver for the display. Sub-frames may be leveraged in combination with and/or automatically through use of the internal memory to the pixel and external memory for the pixel. For example, a pixel may be driven to emit light according to data stored in external memory allocated for the pixel for a duration of time corresponding to a first sub-frame and driven to emit light according to data stored in memory internal to the pixel (e.g., memory-in-pixel) for at least a portion of a second sub-frame. The target gray level may define for how many sub-frames the pixel is driven from the internal memory and for how many sub-frames the pixel is driven from the external memory to cause a total light emission perceivable as the target gray level. In this way, the combination of the light emitted from the pixel during the first sub-frame and the light emitted from the pixel during the second sub-frame may be perceived by an observer of the display as corresponding to the target gray level for the pixel.

Splitting the driving of a pixel at a target gray level into multiple driving operations that span multiple sub-frames may improve pixel driving methods. The division into the multiple driving operations may be controlled by processing circuitry of the electronic device (e.g., a display driver, a controller), automatically using a counter-based system of the electronic device, or the like.

When the processing circuitry controls driving operations, each target gray level may be analyzed to determine a combination of driving operations to generate the desired light emission. The operations used to drive the pixel to emit light may include selectively driving the pixel from the memory internal to the pixel (e.g., memory-in-pixel), driving the pixel from the memory external to the pixel but allocated to the pixel (e.g., allocated external memory), or a combination thereof. Furthermore, it is noted that driving the pixel from the memory external to the pixel may also involve an unmodulated and/or continuous light emission instruction (or a no-light emission instruction) for a duration of a sub-frame. For example, a pixel may be driven to emit light for a duration of the sub-frame without expectation for the light emission to stop during the sub-frame and/or driven to not emit light for a duration of the sub-frame without expectation for light emission to begin during the sub-frame. Combining the unmodulated emission instructions with the modulation emission instructions may mean that the pixel is driven for a first sub-frame to emit an unmodulated light, driven for at least a portion of a second sub-frame to emit a modulated light (e.g., to fine tune the presented gray level during the first sub-frame), and driven for a third sub-frame to not emit light (e.g., unmodulated zero emission) after the target gray level has been presented using the first sub-frame and the second sub-frame. In this way, when a target gray level is greater than a threshold gray level, a different combination of operations may be used than when the target gray level is less than the threshold gray level.

When the counter-based system controls the driving operations, the pixel may be automatically switched between the driving operations described above in response to results from comparisons between a target gray level and a current count. For example, a subset of binary data representing a present count of a counter may be compared to the same bit positions of binary representing the target gray level at each change in count. While waiting for the subset of binary data representing the target gray level to match the subset of binary data representing the count, the pixel may be driven to emit unmodulated light. When the data stored in the corresponding bit positions matches, the pixel is driven according to the remaining binary data representing the target gray level, thereby driving the pixel to emit modulated light. It should be understood that when referred to as modulated light, the light emitted from the pixel may be emitted according to image data stored in memory of the pixel as opposed to image data stored in allocated external memory for the pixel.

When driving the pixel to emit modulated or unmodulated light (or no light), data overriding and/or memory disabling operations may be used. Data stored and transmitted to the memory internal to the pixel may be overridden or disabled by a control signal from affecting output of the pixel for a duration of a sub-frame. The control signal may disable the memory internal to the pixel and may permit the allocated external memory to drive the pixel.

For example, when the target gray level is between 0 and a first threshold, the memory internal to the pixel may be decoupled from at least a light-emitting portion of the sub-pixel, and thus may be temporarily not in use or may be supplied with a “0” value to do so. Disabling or not using the memory internal to the pixel may permit the allocated external memory to drive the pixel for a first sub-frame and memory internal to the pixel may drive the pixel for a second sub-frame. In some cases, an output from the allocated external memory and an output from a counter may be compared by a comparator. The output from the comparator may be used as the control signal to control coupling or decoupling of the memory internal to the pixel to the light-emitting portion of the pixel. However, in some cases, the control signal may be generated by the controller or driver to directly control the operations.

Usage of two or more allocated memories may improve driving methods by, for example, extending possibilities of driving ranges beyond what may be permitted by the physical boundaries of the panel of pixels. For example, memory storing 6 bits of data may be included within the pixel but the pixel may be driven to emit light according to 8 bits of data (e.g., 256 gray level options) without using the footprint of 8 bits of memory internal to the pixel as opposed to being limited to the 6 bits of data (e.g., 64 gray level options). Furthermore, the memory internal to the pixel may be loaded with data for emission while or in parallel to the pixel emitting light during the first sub-frame refresh according to data stored in the allocated external memory. Driving pixels as discussed herein may leverage single pulse width modulation driving methods to improve perceivable appearances of the display relative to other memory-in-pixel driving methods. Indeed, using single pulse width modulation driving methods may improve on driving methods, such as binary pulse width modulation (BPWM) driving methods, since other driving methods may introduce visual artifacts, such as visual artifacts from slow charging of a light-emitted diode (LED) of a pixel being driven with binary pulse width modulation.

To help illustrate, an electronic device10is shown inFIG.1. As described in more detail below, the electronic device10may be any suitable electronic device, such as a computer, a mobile phone, a portable media device, a tablet, a television, a virtual-reality headset, a vehicle dashboard, and the like. Thus, it should be noted thatFIG.1is merely one example and is intended to illustrate the types of components that may be present in an electronic device10. The electronic device10may include, among other things, a processing core complex12such as a system on a chip (SoC) and/or one or more processing circuits, one or more storage devices (e.g., storage device14), one or more communication interfaces (e.g., communication interface16), one or more electronic displays (e.g., electronic display, display18), one or more input structures (e.g., input structure20), and one or more power supplies (e.g., power supply22). The various components described inFIG.1may include hardware elements (e.g., circuitry), software elements (e.g., a tangible, non-transitory computer-readable medium storing instructions), or a combination of both hardware and software elements. It should be noted that the various depicted components may be combined into fewer components or separated into additional components.

Using pixels containing light-emitting components (e.g., LEDs, OLEDs), the display18may show images generated by the processing core complex12. The processing core complex12may be operably coupled with the storage device14. The processing core complex12may execute instructions stored in the storage device14to perform operations, such as generating and/or transmitting image data. As such, the processing core complex12may include one or more general purpose microprocessors, one or more application specific integrated circuits (ASICs), one or more field programmable logic arrays (FPGAs), or any combination thereof.

In addition to instructions, the storage device14may store data to be processed by the processing core complex12. Thus, in some embodiments, the storage device14may include one or more tangible, non-transitory, computer-readable mediums. The storage device14may be volatile and/or non-volatile. For example, the storage device14may include random access memory (RAM) and/or read only memory (ROM), rewritable non-volatile memory such as flash memory, hard drives, optical discs, and/or the like, or any combination thereof.

As depicted, the processing core complex12may also be operably coupled with the communication interface16. In some embodiments, the communication interfaces16may facilitate communicating data with another electronic device and/or a network. For example, the communication interface16(e.g., a radio frequency system) may enable the electronic device10to communicatively couple to a personal area network (PAN), such as a Bluetooth network, a local area network (LAN), such as an 1622.11x Wi-Fi network, and/or a wide area network (WAN), such as a 4G, or Long-Term Evolution (LTE) cellular network, 5G, or the like.

Additionally, as depicted, the processing core complex12is also operably coupled to the power supply22. In some embodiments, the power supply22may provide electrical power to one or more components in the electronic device10, such as the processing core complex12and/or the display18. Thus, the power supply22may include any suitable source of energy, such as a rechargeable lithium polymer (Li-poly) battery and/or an alternating current (AC) power converter.

As depicted, the electronic device10is also operably coupled with the input structure20. In some embodiments, the input structure20may facilitate user interaction with the electronic device10, for example, by receiving user inputs. Thus, the input structure20may include a button, a keyboard, a mouse, a trackpad, and/or the like. Additionally, in some embodiments, the input structure20may include touch-sensing components in the display18. In such embodiments, the touch sensing components may receive user inputs by detecting occurrence and/or position of an object touching the surface of the display18.

In addition to enabling user inputs, the display18may include a display panel with one or more display pixels. As described above, the display18may control light emission from the display pixels to present visual representations of information, such as a graphical user interface (GUI) of an operating system, an application interface, a still image, or video content, by displaying frames based at least in part on corresponding image data. As depicted, the display18is operably coupled to the processing core complex12. In this manner, the display18may display frames based at least in part on image data generated by the processing core complex12. Additionally or alternatively, the display18may display frames based at least in part on image data received via the communication interface16and/or the input structure20.

As may be appreciated, the electronic device10may take a number of different forms. As shown inFIG.2, the electronic device10may take the form of a watch30. For illustrative purposes, the watch30may be any Apple Watch® model available from Apple Inc. As depicted, the watch30includes an enclosure32(e.g., housing). In some embodiments, the enclosure32may protect interior components from physical damage and/or shield them from electromagnetic interference (e.g., house components). A strap34may enable the watch30to be worn on the arm or wrist. The display18may display information related to the operation of the watch30. Input structures20may enable the user to activate or deactivate watch30, navigate a user interface to a home screen, navigate a user interface to a user-configurable application screen, activate a voice-recognition feature, provide volume control, and/or toggle between vibrate and ring modes. As depicted, the input structures20may be accessed through openings in the enclosure32. In some embodiments, the input structures20may include, for example, an audio jack to connect to external devices.

The electronic device10may also take the form of a tablet device40, as shown inFIG.3. For illustrative purposes, the tablet device40may be any iPad® model available from Apple Inc. Depending on the size of the tablet device40, the tablet device40may serve as a handheld device such as a mobile phone. The tablet device40includes an enclosure42through which input structures20may protrude. In certain examples, the input structures20may include a hardware keypad (not shown). The enclosure42also holds the display18. The input structures20may enable a user to interact with a GUI of the tablet device40. For example, the input structures20may enable a user to type a Rich Communication Service (RCS) text message, a Short Message Service (SMS) text message, or make a telephone call. A speaker44may output a received audio signal and a microphone46may capture the voice of the user. The tablet device40may also include a communication interface16to enable the tablet device40to connect via a wired connection to another electronic device.

FIG.4illustrates a computer48, which represents another form that the electronic device10may take. For illustrative purposes, the computer48may be any MacBook® or iMac® model available from Apple Inc. It should be appreciated that the electronic device10may also take the form of any other computer, including a desktop computer. The computer48shown inFIG.4includes the display18and input structures20that include a keyboard and a track pad. Communication interfaces16of the computer48may include, for example, a universal serial bus (USB) connection.

In any case, as described above, operating an electronic device10to communicate information by displaying images on its display18generally consumes electrical power. Additionally, as described above, electronic devices10often store a finite amount of electrical energy. Thus, to facilitate improving power consumption efficiency, an electronic device10, in some embodiments, may include a display18that implements memory-in-pixel as a way to reduce, or eliminate, use of an external frame buffer in displaying images, and thus reduces power consumed by use of the frame buffer in displaying images and/or reducing a bandwidth of image data being received into the display18. In some cases, an internal frame buffer (e.g., located in the display18, such as in a display driver integrated circuit of the display18) may be used additionally or alternatively to memory-in-pixel techniques. By implementing memory-in-pixel or related techniques, a display18may be programmed with smaller bandwidths of image data, further enabling power consumption savings. In addition, a display18using memory in the pixel or in an onboard frame buffer may have a less complex design than a display18without memory in the pixel or without an onboard frame buffer. These benefits may be realized because a pixel retains data transmitted to its memory until new image data is written to the memory.

Similarly, portions of image data may program a subset of pixels associated with the display18at a time, including between sub-frames. An image to be displayed is typically converted into numerical data, or image data, such that the image is interpretable by components of the display18. In this way, image data itself may be divided into small “pixel” portions, each of which may correspond to a pixel portion of the display18, or of a display panel corresponding to the display18. In some embodiments, image data is represented through combinations of red-green-blue light such that one pixel appearing to have a single color is really three sub-pixels respectively emitting a proportion of red, green, and blue light to create the single color. In this way, numerical values, or image data, that quantify the combinations of red-green-blue light may correspond to a digital luminance level, or a gray level, that associates a luminance intensity (e.g., a brightness) of a color of the image data for those particular sub-pixels. As will be appreciated, the number of gray levels in an image usually depends on a number of bits used to represent the gray levels in a particular display18, which may be expressed as 2Ngray levels where N corresponds to the number of bits used to represent the gray levels. By way of example, in an embodiment where a display18uses 8 bits to represent gray levels, the gray level ranges from 0, for black or no light emitted by the pixel, to 255, for maximum light and/or full light capable of being emitted by the pixel, for a total of 256 potential gray levels. Similarly, a display18using 6 bits may use 64 gray level increments to represent a luminance intensity for each sub-pixel (e.g., to specify a value between no light emission and maximum light emission for each sub-pixel).

Having memory internal to pixels of the display18may enable image data to transmit to sub-pixels associated with one color without image data having to transmit to additional sub-pixels associated with a second color at the same time. For the purposes of this disclosure, sub-pixels are discussed in terms of red-green-blue color channels, where a color channel is a layer of image data including gray levels for a single color where when combined with additional color channels creates an image of a true, or desired, color, and where the image data for a color channel corresponds to image data transmitted to a sub-pixel for the color channel. However, it should be understood that any combination of color channels and/or sub-pixels may be used, such as, blue-green-red, cyan-magenta-yellow, and/or cyan-magenta-yellow-black.

To help illustrate, a display system50associated with a display18that does not implement memory-in-pixel and a display system52associated with a display18that does implement memory-in-pixel, which may each respectively be implemented in an electronic device10, is shown inFIG.5. The display system50includes a timing controller54to receive image data56, a frame buffer58, a row driver60and a column driver62communicatively coupled through communicative link64to the timing controller54, and a pixel array66that receives control signals from the column driver62and the row driver60to create an image on the display18. Furthermore, the display system52includes a timing controller54to receive image data56, a row driver60and a column driver62communicatively coupled through a communicative link68to the timing controller54, and a pixel array70implementing memory-in-pixel techniques that receives control signals from the column driver62and the row driver60to create an image on the display18.

In preparing to display an image, the display system50may receive the image data56at the timing controller54. The timing controller54may receive and use the image data56to determine clock signals and/or control signals to control a provision of the image data56to the pixel array66through the column driver62and the row driver60. Additionally or alternatively, in some embodiments, the image data56is received by the frame buffer58.

In either case, the frame buffer58may serve as external storage for the timing controller54to store the image data56prior to output to the column driver62and/or the row driver60. The timing controller54may transmit the image data56from the frame buffer58to the column driver62and/or the row driver60through the communicative link64.

The communicative link64is large enough (e.g., determined through transmission bandwidth of image data) to simultaneously transmit image data56associated with all the channels to the row driver60and/or the column driver62, for example, the image data56associated with a red channel, a green channel, and a blue channel. In this way, the communicative link64communicates image data56associated with a respective pixel of the pixel array66for the red channel, the green channel, and the blue channel at the same time. The column driver62and the row driver60may transmit control signals based on the image data56to the pixel array66. In response to the control signals, the pixel array66emits light at varying luminosities, or brightness indicated through gray levels ranging from, for example, 0 to 255, to communicate an image.

However, the display system52receives the image data56at the timing controller54. The timing controller54may use the image data56to determine clock signals used to provision the image data56to the memory-in-pixel pixel array70. The timing controller54transmits the image data56to the row driver60and/or the column driver62to program the memory of the pixel array70with digital data signals associated with the image data56, where the digital data signals indicate the emission brightness/gray level for the pixels of the pixel array70.

By implementing memory-in-pixel systems and methods, the display system52may reduce a bandwidth of signals communicated over communicative link68, for example, when compared to a bandwidth of signals communicated over the communicative link64. In some instances, a single channel of image data56may transmit through the communicative link64(e.g., red channel), as opposed to all channels being simultaneously transmitted to the pixel array66(e.g., red-green-blue channels). In this way, the communicative link68communicates image data56associated with a respective pixel of the pixel array66for the red channel, the green channel, and the blue channel at different times, causing a decrease in an overall bandwidth of signals used to communicate image data56. Decreasing an overall bandwidth of the communicative link68may lead to a decrease in power consumption of the electronic device10because processing less data (e.g., a single channel of image data) at a given time may consume fewer processing resources than processing more data (e.g., three channels of image data).

To elaborate on operating the pixel array70with memory-in-pixel to display images,FIG.6is a block diagram of an example display system52, display system52A, implementing memory-in-pixel. The display system52A includes a pixel array70of L rows by M columns with one or more pixels72. Each pixel72may include sub-pixels74corresponding to color channels of the display18, for example, a red sub-pixel74R, a green sub-pixel74G, and a blue sub-pixel74B. Each of the sub-pixels74may include a memory78to store up to N bits and a driver (DRV)80to operate the sub-pixel74to emit light. It should be appreciated that the depicted display system52A is merely intended to be illustrative and not limiting. For example, in some embodiments, the pixel array70may include sub-pixels74to emit various amounts of cyan, yellow, and magenta light corresponding to cyan-yellow-magenta color channels instead of, or in addition to, the red-green-blue color channels.

Explaining operation of the display system52A, the timing controller54receives image data56corresponding to a next image to be displayed on a display18having the pixel array70. The timing controller54may receive the image data56while an image frame is presented via the display18. The timing controller54may generate control signals and/or clocking signals in response to the image data56. These generated control signals and/or clocking signal may be related to operating rows of pixels72and/or related to operating columns of pixels72, and thus may be transmitted respectively to row driver60and/or column driver62.

The row driver60is responsive to the signals associated with the image data56transmitted from the timing controller54and generates emit control signals82and write control signals84for each red-green-blue (RGB) channel. The column driver62, also being responsive to the signals associated with the image data56transmitted from the timing controller54, generates image data86to be transmitted to the memory78of each of the pixels72. The column driver62may generate image data86in response to the signals associated with the image data56and/or the image data56, in some embodiments, however, image data56transmits to each of the pixels72as image data86. The column driver62generates data of size N bits for each sub-pixel74, matching a size of the memory78which is also size N bits.

Generally, through transmission of the emit control signals82, the write control signals84, and the image data86, the pixels72are operated to emit light to create an image on a display18. Each of the pixels72receives a respective emit control signal88of the emit control signals82transmitted from the row driver60, a respective three write control signals90of the write control signals84, and respective image data92for the channels of the pixel72, for example, N bits of image data for the red channel (image data—R)92R, N bits of image data for the green channel (image data—G)92G, and N bits of image data for the blue channel (image data—B)92B. The write control signals84may enable a memory78of the pixel72to be programmed by the image data86transmitted by the column driver62. In addition, a respective emit control signal88of the emit control signals82may control whether the pixel72is able to emit light. The emit control signal88transmits to respective pixels72of a column. An enabled emit control signal88may activate a driver80causing digital image data92from a memory78to transmit to a light-emitting portion of the pixel72, for example, a light-emitting diode associated (LED) with a sub-pixel74, that uses analog data signals to cause light emitted from the pixel72. In the depicted embodiment, columns of pixels72, for example, pixels72R1C1, R2C1, R3C1, to RLC1in a first column receive a same emit control signal88. Image data92transmitted to a pixel72causes the pixel72to emit light of an overall color and/or brightness.

A perceived color emitted from the pixel72changes based on the light emitted from each of the three channels of the pixel72, that is, the light emitted from each respective sub-pixel. For example, operating each sub-pixel to output a brightness of 0, causes the pixel72to appear to be off, while operating a red sub-pixel74R to output a brightness of 100%, a green sub-pixel74G to output a brightness of 50%, and a blue sub-pixel74B to output a brightness of 0% may cause a pixel72to emit an overall color that is perceived as an orange color. Thus, data is rendered and transmitted to each sub-pixel74to correspond to individual color channels of a pixel72.

Implementing memory78in a pixel72enables image data92to be programmed into the pixel72prior to a desired presentation time of the image. In some embodiments, an enabled write control signal90causes the memory78to clear (or overwrite) stored image data92, where not enabling a write control signal90may cause the memory78to retain the programmed image data92. For example, to write new image data, a write control signal—R90R may cause a memory78of a red sub-pixel74R to clear, enabling the writing of new image data, image data—R92R to be loaded into the memory78. In this example, a write control signal—B90B was not enabled, thus the memory78of the blue sub-pixel74B does not clear and continues to retain its programmed image data, image data—B92B. Having memory78in pixels72is an improvement to display technologies and processing technologies because memory78enables portions of image data86to be written at a time instead of a whole frame of data, causing improved use of available bandwidth to communicate image data for display on a display18, as well as improvements to power consumption used for processing image data, as explained earlier with reference toFIG.5.

In the pixel array70, image data86is communicated from the column driver62to the sub-pixels74through a direct communicative coupling, for example, through a communicative coupling94. In some embodiments, a multiplexing circuit may be used to control transmission of image data86to sub-pixels74such that a multiplexing control signal is used by the column driver62to arbitrate transmission of image data to a sub-pixel74, for example, where in such arbitration a red sub-pixel74R may not receive image data at the same time as a blue sub-pixel74B and/or a green sub-pixel74G receives image data.

To elaborate,FIG.7is a block diagram of another example display system52, display system52B, associated with a display18implementing memory-in-pixel techniques. The display system52B, similar to the display system52A shown inFIG.6, includes a pixel array70of L rows by M columns with one or more pixels72each having sub-pixels74, for example, a red sub-pixel74R, a green sub-pixel74G, and a blue sub-pixel74B, where each of the sub-pixels74includes a memory78to store up to N bits and a driver (DRV)80to operate the sub-pixel74to emit light. It should be appreciated that the depicted display system52B is merely intended to be illustrative and not limiting. It is noted functions and/or descriptions of the display system52that are common to bothFIG.6andFIG.7are relied upon herein.

In the display system52B inFIG.7, the pixel array70includes a multiplexing circuit96that receives image data98of size N bits from the column driver62. The multiplexing circuit96is responsive to a respective multiplexing control signal (MUX control signal)100of multiplexing control signals101. The MUX control signal100may cause the multiplexing circuit96to output data to a sub-pixel74of a pixel72. In this way, the column driver62, through emission of the MUX control signal100, may operate to program a sub-pixel74(e.g., one color channel) of a pixel72at a time via, for example, a communicative coupling94. For the pixel array70, various embodiments of sub-pixel74circuits may be used.

An example of an embodiment of a sub-pixel74implementing memory-in-pixel techniques is shown inFIG.8.FIG.8is a block diagram of a sub-pixel74that is driven using single pulse width driving methods (e.g., single pulse width modulation emission scheme). The sub-pixel74includes a memory78, a driver80, a current source102, a light-emitting component (e.g., circuitry, light-emitting diode (LED)104), a switch106, and a counter108. The sub-pixel74may receive a variety of signals including a portion of image data56corresponding to an operation of the sub-pixel74for a present frame to be rendered (e.g., image data56A), a gray level clock110, a common voltage112, a first reference voltage114, a second reference voltage116, and a data clock118. It should be appreciated that the depicted sub-pixel74is merely intended to be illustrative and not limiting. For example, memory78may be an 8-bit register or any suitable memory circuit to store any suitable number of bits. The depicted sub-pixel74may emit according to a single pulse width modulation emission scheme. Furthermore, as described above, the image data56A may correspond to image data92transmitted in accordance with a non-multiplexing driving scheme (e.g., as described at least partially withFIG.6) and/or to image data98transmitted in accordance with a multiplexing driving scheme (e.g., as described at least partially withFIG.7).

To explain operation of the sub-pixel74, image data56A transmits to the memory78from, for example, a column driver62. Additionally or alternatively, image data92, image data56, or any suitable image data may be transmitted to the memory78for storage. After receiving the image data56A, the memory78stores the image data56A clocked in by the data clock118. The image data56A may be represented by binary data. The memory78may output the image data56A to a comparator120(e.g., comparator circuitry), such that at each increment of the counter108, the total count is checked against the image data56A stored in the memory78to identify when the total count is greater than or equal to the image data56A.

When the comparator120determines that the count is not greater than or equal to the image data56A stored in the memory78, the comparator120generates a control signal to operate the switch106, causing the LED104to emit light. The operation of the switch106occurs in response to varying emission periods (e.g., defined by how large of a number is stored as the image data56A in the memory78) as a method to modulate emission of light from the LED104, causing the perceived brightness of the sub-pixel74to change as the modulation changes. In this way, the switch106may be considered a driving transistor that activates based at least in part on digital data signal, such as the image data56A and/or an output from the comparator120. The switch106, or any switch described herein, may be any suitable switching device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). In this way, the electronic device10may include one or more p-type MOSFETs and/or n-type MOSFETs. Control signal levels may be adjusted to accommodate usage of different types of switches. For example, a p-type MOSFET may be used as a switch in the figures and described as such, but in an actual implementation be an n-type MOSFET, and thus may receive control signals of opposite polarity or adjusted amplitude when operating the pixel72.

For example, through the relationship between the output from the comparator120and the switch106, image data56A equaling “00000000” may cause the LED104to not emit light while image data56A equaling “10101100,” or any non-zero number, may cause the LED104to be perceived as brighter. The image data56A equaling “10101100” may be perceived as brighter because the sub-pixel74operates to emit light in response to each logical high value, “1,” through the value causing the switch106to activate, permitting light to emit from the LED104.

The longer a duration of time that the switch106is activated for during an emission period, the brighter a pixel is perceived because the more light is emitted over time. In some cases, image data56A may be derived from a desired gray level for the sub-pixel74without being an exact binary representation of the gray level, such as when a proportion is used to represent a target gray level for the pixel. However, it should be noted that there may be scenarios where the target gray level for the sub-pixel74does indeed equal the binary representation transmitted via image data56A.

The depicted sub-pixel74, having memory-in-pixel, may emit according to a single pulse width emission scheme. To explain operation of the sub-pixel74, image data56A transmits to the memory78, for example, from a column driver62, for storage. Additionally or alternatively, image data92, image data56, or any suitable image data may be transmitted to the memory78for storage. In some embodiments, the image data56A may be clocked into the memory78by the data clock118, for example, on a rising edge, falling edge, or both, of the data clock118. The image data56A communicated to the sub-pixel74may correspond to a desired gray level at which the sub-pixel74is to emit light. Using the image data56A stored in the memory78, the comparator120determines if a current number represented by the counter108is less than or equal to the image data56A in memory78. In other words, the counter108counts up to the number indicated by the image data56A, and in response to the number represented by the counter108meeting a condition, for example, being greater than or equal to the number indicated by the image data56A, the comparator120outputs a control signal to open the switch106when the condition is met. When the condition is not met, the comparator120continues to output a control signal to keep the switch106closed, and thus to continue light emission from the LED104. Additionally or alternatively, the comparator120may enable a deactivation control signal to cause the opening of the switch106. For instance, if the memory78stores a binary sequence of 10110101 corresponding to the number 181, the comparator120will check if the counter108has counted to the number181, and after the counter108exceeding the number181, the comparator120transmits a signal to open the switch106, thereby stopping light emission from the LED104.

When the switch106closes, an electrical connection is created between the common voltage112and the first reference voltage114. This may cause current from current source102to transmit through the LED104, causing light to emit from the sub-pixel74. Thus, emission periods of the sub-pixel74may be varied to control a perceived light emitted from the sub-pixel74through changing a number indicated by the image data56A. Additionally or alternatively, in some embodiments, the second reference voltage116is included to alter an overall current value used to control light emitted from the LED104. For instance, the second reference voltage116may increase a sensitivity of the LED104to current changes such that a lower current value may be used to cause light to emit from the LED104, or used to enable the LED104.

The counter108counts from 0 to 255 and increments based on a gray level clock110, for example, a rising edge of the gray level clock110. Periods of the gray level clock110represent the time difference between increments of the gray level for a display18, for example, a difference in emission between emitting a gray level of100and emitting a gray level of101. In this way, the counter108counts up to the number represented by the image data56A stored in memory78subsequently causing emission to occur for the time period corresponding to the desired gray level. The counter108may continue to count beyond the number represented by the image data56A stored in memory78on to a maximum value, for example, 255, and may restart counting at a minimum value, for example, 0. Thus, in some embodiments, a counting range of the counter108may be defined through design of the counter108, for example, through a number of registers and/or logical components included in the counter108. By the time the counter108restarts counting at 0, additional image data56A may be stored into memory78to begin comparison for a next emission period of a gray level associated with the additional image data56A.

Through following this emission scheme, the sub-pixel74may follow a single pulse width modulation emission scheme. A representation of an emission of light from a sub-pixel74following a single pulse width modulation emission scheme is shown in graph122. The graph122includes an actual emission period124and a total emission period126. The total emission period126corresponds to a total length of emission represented by a maximum number transmitted as image data56A, for example, 255, and may correspond to a maximum perceived brightness of light emitted from the sub-pixel74. The actual emission period124corresponds to a period of time a sub-pixel74emitted light for according to a number less than the maximum transmitted as the image data56A, for example, from the counter108. The counter108increments from 0 to 255 taking the amount of time represented by the total emission period126while the comparator120enables light to emit for the amount of time represented by the actual emission period124. In this way, a sub-pixel74may emit light of varying perceived brightness.

To elaborate on operation of the sub-pixel74depicted inFIG.8, a process130for operating the sub-pixel74having the comparator120and the memory78is described inFIG.9. Generally, the process130includes initializing memory circuitry (block132), precharging common output from comparator (block134), incrementing count of counting circuitry (block136), causing emission based on automatic comparator determination stored in memory circuitry (block138), determining if counting circuitry has reached a maximum count (block140). In response to the counting circuitry reaching the maximum count, preparing for next image (block142), and in response to the counting circuitry not reaching the maximum count, continuing to cause emission based on automatic comparator determination stored in memory circuitry (block138). In some embodiments, the process130may be performed at least in part by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as the storage device14, using processing circuitry, such as the processing core complex12. Additionally or alternatively, the process130may be implemented at least in part based on circuit connections formed in display controlling circuitry, such as a row driver60, a column driver62, and/or a timing controller54.

Thus, in some embodiments, the timing controller54may initialize memory78(block132). To initialize the memory78, the timing controller54may enable a control signal to force a node of the memory78to a low voltage value, such as through instruction to the row driver60or column driver62. TakingFIG.8for example, to initialize the memory78, the row driver60may enable a reset signal to reset a voltage value of a node of the memory78in response to receiving a control signal from the timing controller54. Initializing the memory78may enable light-emitting circuitry of the sub-pixel74(e.g., LED104) to emit until the comparator120outputs a control signal to stop light emission (e.g., in response to the gray level stored in memory being reached by the counter108). In other words, for one or more sub-pixels74implementing a comparator120, sub-pixels74may start light emission together at the same time but stop light emission at different times—where the respective duration of light emission corresponds to a target gray level for the respective sub-pixel74.

The timing controller54may precharge a common output from the comparator120after initializing the memory78(block134). The timing controller54may enable a precharge signal (e.g., via the row driver60, via the column driver62) to cause a voltage to boost circuitry of the sub-pixel74, thereby improving responsiveness of the sub-pixel74to changes in output from the comparator120. It should be appreciated that any suitable circuitry arrangement may be used to facilitate precharging the sub-pixel74.

After precharging the comparator120, the timing controller54may increment a count of the counter108(block136). The timing controller54may increment the counter108by using the gray level clock110. After incrementing the counter108, the sub-pixel74may automatically determine if the count of the counter108is greater than or equal to a value represented by the image data56A. This occurs since the individual bits of the count and the individual bits of image data56A are respectively transmitted to the comparator120. The comparator120may output a logical high value when none of the bits match or may output a logical low value when each of bits match or when a bit changes that would signify that the image data56A has been exceeded by the count.

After incrementing the count of counting circuitry, the timing controller54may cause light emission based on the output from the comparator120(block138). The value transmitted from the comparator120may activate or deactivate switching circuitry of the LED driver (e.g., switch106) and the LED104responsible for emitting light.

The timing controller54may determine if the count of the counter108is a maximum count (block140). The counter108may count from a minimum to a maximum value, for example, from 0 to 255. Thus, when a maximum value, or a maximum count, is reached by counting circuitry, the timing controller54may perform certain processing steps to restart the count. It is noted that in some embodiments the timing controller54may count down instead of counting up, and thus, the timing controller54may determine whether the minimum count has been reached.

In response to the maximum count not being reached, the timing controller54may continue to cause light emission from the sub-pixel74(block138). However, in response to the maximum count being reached, the timing controller54may prepare for presentation of a next image frame (block142). To do this, the timing controller54may prepare to receive new image data56A corresponding to the target gray level of the sub-pixel74used to communicate the next image frame.

In some cases, the timing controller54may operate the sub-pixel74to emit light according to a binary order represented by the image data56A. Sometimes the row driver60may rearrange bit order of the image data56A to improve efficiency of driving of the sub-pixel74, such as may occur when image data56A is thermally encoded. For example, if the image data56A equals 0010, the row driver60may operate according to image data equaling 1-0-0-0 such that the emission time for the “1” occurs first and is not emitted after the time period corresponding to “00.” This rearranging may improve appearances of visual artifacts on a display18while still causing the same gray level indicated by “0010” to emit from the sub-pixel74(e.g., gray level=2) as opposed to the gray level represented by the reordered image data (e.g., gray level=8). When the row driver60reorders image data56A it is noted that the relative emission periods for each bit may remain the same. For example, when data representing a gray level of20is reordered for efficient driving of the sub-pixel74, the reordering does not result in a change in gray level for the image data56A (e.g., pre-reordering gray level=20 and post-reordering gray level=20).

FIG.10is an illustration of example binary sequences150adjacent to a representation of a relative weight for each bit in each binary sequence150. Each of the binary sequences may at some point in operation of the display18correspond to image data56A. Relative weights may be assigned to each bit position (e.g., summarized in table152) of each of the binary sequences150. Bit-plane illustration154may illustrate a relative effect of each bit point on an overall gray level when using bits to drive a sub-pixel74to emit light.

For example, bit position0may correspond to 1 relative unit of influence over light emission from the sub-pixel74(e.g., 20=1) and bit position3may correspond to 8 units of influence (e.g., 23=8, 4 times the impact on overall gray level than bit position0). For example, row156may correspond to binary sequence “0001,” row158may correspond to binary sequence “0100,” and row160may correspond to binary sequence “1111.” The bit-plane illustration154visually shows a bit-plane representation of each binary combination of the binary sequences150. In some cases, the respective binary sequence of the binary sequences150corresponding to the image data56A may be used to drive the sub-pixel74, such as when the respective binary sequence is stored in memory78as image data56A ofFIG.8(e.g., when the memory78stored 4 bits).

A respective binary sequence of the binary sequences150may be thermally coded to show how the binary sequence corresponds to a natural number representation of the number. Thermal coding may change a sequence162A having a numerical value based in binary number into a sequence162B having a numerical value based on a number of consecutive values (e.g., “1” or “0” values consecutive). In this example, the value of the sequence162B may be interpreted as having a numerical value equaling “11” (e.g., eleven) since there are eleven consecutive “1”s after the thermal coding of the sequence162A. To explain differently, sequence162A corresponds to binary number “1011” which, when thermally coded, is represented by sequence162B “111111111110000.”FIG.10also shows another thermal coding example. The binary number “1101” may be thermally coded to equal “111111111111100.”

As may be apparent from the bit-plane illustration154, binary sequences150may be represented in the bit-plane representation according to a pattern. For example, a bit in the bit position3may change the gray level represented by the binary sequence from numbers 0-7 to a gray level representing the binary sequence for numbers 8-15. In this way, the bit in bit position3may be considered to have a relatively high influence on a perceived final value gray level of light emitted by the sub-pixel74.

Elaborating further on the bit-plane illustration154,FIG.11Ashows a bit-plane graph170,FIG.11Bshows an error graph172,FIG.11Cshows a bit-plane graph174,FIG.11Dshows an error graph176,FIG.11Eshows a bit-plane graph178,FIG.11Fshows an error graph180,FIG.11Gshows a bit-plane graph182, andFIG.11Hshows an error graph184, whereFIG.11as a whole illustrates the effects reordering on total error.FIG.11A-FIG.11Hrepresent simulated performance of a display18implementing the emission scheme with and without reordering for a six-bit binary number representing a target gray level for a sub-pixel and/or a pixel.

The bit-plane graph170shows an original sequence of the emission scheme without any reordering for gray levels represented by six bits, where for all the bit-plane graphs170,174,178, and182have a light portion186corresponding to light emission and a dark portion188corresponding to no light emission. In this first example, a sub-pixel74may be driven to emit light at each indicated light portion186and not driven to emit light at each indicated dark portion188. Since a human eye may integrate light emitted over time, light emitted in a modulation, non-continuous manner may be perceived as smooth. However, since no re-ordering has occurred with the first bit-plane graph170, light emission according to the indicated light portions186may be perceived as imperfect and as having visual artifacts, since sometimes the modulations are perceivable. The modulations may additionally or alternatively cause dynamic false contouring (DFC) artifacts, which may or may not worsen when an observer of the display18adjusts a viewing positioning (e.g., turns head, shifts body).

When sub-pixels74are operated to emit light following an emission scheme without reordering (e.g., according to bit-plane graph170), total error counts are high (e.g., error count =322, errors perceivable as visual artifacts, such as DFC), as shown in error graph172. It may be desired to lower the total error counts through reordering since these errors may manifest on an electronic screen of a display18as, for example, dynamic false contouring, color breakup, and/or flickering of light emitted from one or more pixels.

As reordering occurs and as the most significant bits are reordered to emit first to cause gray levels of the bit-plane graphs, as seen with bit-plane graph174and bit-plane graph178, the bit-plane pattern trends towards looking like the ideal bit-plane shown in bit-plane graph182. In addition, error decreases as reordering occurs as shown with error graph172, error graph176, error graph180, and error graph184. Perceived image quality may improve from decreasing error counts via the reordering of the bit-planes.

The ideal case (e.g., bit-plane graph182) shows how the bit-plane graph182trends to a gradual bit-plane change as gray level increases and how the total error trends to a number of total states represented by the bit-plane (e.g., 6 bits corresponds to 64 total states, following the relationship: number of states=2z, where z is the number of bits) through increasing a number of reorderings. Furthermore, it is noted that driving sub-pixels74of the display18using single pulse width modulation techniques may resemble the ideal case (e.g., bit-plane graph182) described above, and thus may reduce occurrences of perceivable visual artifacts occurring when presenting image frames. It is noted that, the systems and methods described herein are described in terms of driving sub-pixels74using these single pulse width modulation techniques. However, it should be understood that using the allocated external memory in combination with the memory internal to the pixel may provide similar benefits to each driving technique. For example, some binary pulse width modulation display systems may benefit from partially driving sub-pixels from a combination of memory allocated to the sub-pixels.

To elaborate further on memory-in-pixel architectures, memory-in-pixel panels may implement memory within an active area and/or a smart buffer of the display18. For example,FIG.12is a block diagram illustrating a memory-in-pixel architecture display210and a smart buffer architecture display212. The memory-in-pixel architecture display210includes, as depicted, memory78in each sub-pixel74located in an active area214of the display18, where the active area214includes light-emitting components of the display18and communicative couplings to support data transmission to the light-emitting components. In the memory-in-pixel architecture display210, digital data may transmit from memory216to each respective sub-pixel74for localized buffering in the memory78. In some embodiments, the digital data transmits from the memory216to a source area (SA)218before transmission into the memory78for localized buffering (e.g., buffering within the sub-pixel74). However, memory substantially similar to the memory78may be included in a smart buffer220of the smart buffer architecture display212to eliminate, or at least reduce, a reliance on a frame buffer as well as remove the memory78from the active area214. By moving the memory78into a smart buffer220, the row driver60may use an input latch222and an output latch224to arbitrate light emission from each sub-pixel74via analog out circuitry, such as the driver (DRV)80. Here, the smart buffer220may represent any suitable buffer memory disposed in an integrated circuit of the display18but outside of the active area of the display18. It is noted that although not specifically depicted, readout circuitry may be included between the memory78and interface circuitry to enable transmission of signals from the memory78and/or to the memory78.

Furthermore, in some cases, some of the memory78may be included in the sub-pixel74and some of the memory78may be included in the smart buffer220.FIG.13is a block diagram illustrating another example memory-in-pixel architecture display236. In the memory-in-pixel architecture display236, the sub-pixel74include some of the total memory78(e.g., memory78A) allocated to the sub-pixel74and the smart buffer220include the remaining memory78(e.g., memory78B) allocated to the sub-pixel74. It is noted that in these cases where the memory78is generally split into two portions (e.g., memory78A and memory78B),FIG.8may simplify what is included in the sub-pixel74. For example, the memory78A may be included in the sub-pixel74while the memory78B may be disposed external to the sub-pixel74, such as in the smart buffer220or an additional memory, as is shown inFIG.14. Referring back toFIG.8, for clarity's sake, the driver (DRV)80of the sub-pixel74may include the current source102, the comparator120, the switch106, circuitry to transmit outputs from the memory78A and/or the memory78B to the sub-pixel74for processing, or the like. In some cases, the comparator120may also be disposed external to the sub-pixel74, and thus be disposed in the smart buffer220, the row driver60, the column driver62, the timing controller54, or the like.

FIG.14is a block diagram illustrating yet another example of a memory-in-pixel architecture display238. In the memory-in-pixel architecture display238, the sub-pixel74include some of the total memory78(e.g., memory78A) allocated to the sub-pixel74and the memory216(e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)) include the remaining memory78(e.g., memory78B) allocated to the sub-pixel74. It is noted that, although not particularly depicted inFIG.13andFIG.14, the source area218may additionally be coupled between the smart buffer220and the active area214and/or between the memory216and the active area214, similar to as shown inFIG.12.

The smart buffer220and/or a controller associated with the memory216may perform thermal coding operations on received image data56A before sending a portion of image data56A to the memory78A. The thermal coding operations may help convert a target gray level into actionable operations and/or generate control signals to time activations of certain switches. In some cases, a switch controlling which one of the memory78A or the memory78B impacts light emission of the sub-pixel74may receive a control signal generated based on data of the memory78B that has been thermally coded. For example, when the memory78B stores the most significant bit of “1010,” where the most significant bit equals numeral 7 when counting from numeral 0 as the first binary state permitted by a 4 bit binary sequence, the switch may be controlled by a control signal equal to “1111 1110 0000 0000.” The control signal may toggle at a substantially similar time as when the counter is expected to reach numeral 7.

To elaborate,FIG.15is an illustration emphasizing how the electronic device10(e.g., a controller or processor of the electronic device10) may convert a target gray level into operations. For example, the electronic device10may drive the sub-pixels74based on control signals generated by the timing controller54, the row driver60, the column driver62, the smart buffer220, a controller of the memory216, the processing core complex12, or the like. As described herein, the timing controller54is described as directing the conversion of the target grey level into actionable operations but it should be understood that any suitable processing circuitry of the electronic device10may perform some or all of the conversion operations. In some cases, thermal coding operations may help convert the target gray level into control signals and/or actionable operations for the sub-pixel74, such as to identify how many sub-frames are to be used to cause the sub-pixel74to emit light at a target gray level.

The timing controller54may use an all on operation that overrides the memory78A and causes the sub-pixel74to emit light for an entire sub-frame duration regardless of the data stored in the memory78A (e.g., such as according to data stored in memory78B), an all off operation that overrides the memory78A and causes the sub-pixel74to not emit light for an entire sub-frame duration regardless of the data stored in the memory78A, and/or a modulated operation that does not override the memory78A and causes the sub-pixel74to emit light according to the data stored in the memory78A as a way to cause the sub-pixel74to emit light at a target gray level. Thus, the timing controller54may control light emission from the sub-pixel74by sometimes overriding the memory78A and by sometimes driving the sub-pixel74from the memory78A. This dual driving (e.g., dual-control) of the sub-pixel74may improve efficiencies associated with presenting and/or processing image data for an incoming image frame. The sub-pixel74may thus be driven to emit light according to (e.g., based on) a first digital data signal (e.g., data stored in memory78B) for a first duration of time and a second digital data signal (e.g., data stored in memory78A) for a second duration of time to emit light at a target gray level.

To control emission of light from the sub-pixel74, each image frame display duration (e.g., each frame duration, each frame) may thought of as divided into sub-frame display durations. A number of sub-frames used to form a complete image frame display duration may depend on particular configurations of the memory78, and thus binary arithmetic associated with the configurations of the memory78. For example, the memory78may be split into the memory78A and the memory78B. A ratio between the size of memory78A depth and total size of the memory78may define the number of sub-frames. For the depicted example, the total size of the memory78corresponds to 256 bits (28=256 total bits=0-255) and the size of the memory78A corresponds to 64 bits (e.g., 26=64 total bits=0-63). Therefore, four sub-frames may equal one frame (e.g., 256/64=4) and each sub-frame is to emit a quarter of the target gray level assigned to the sub-pixel. It is noted that the durations of each respective sub-frames may correspond to a duration of time used by the counter108to increment from count=0 to count=2M(where 2Mrepresents a number of bits represented by data stored in memory78A), as will be appreciated.

To help elaborate, the timing controller54may receive a binary sequence for a target gray level equaling 255 (e.g., arrow246), where 255/255 visualized by natural number representation248. In this way, the timing controller54may drive the sub-pixel74from the memory78B, causing a 100% light emission (e.g., all on operation) for three sub-frames, and may drive the sub-pixel from the memory78A causing a modulated light emission for one sub-frame (e.g., modulated but causes the sub-pixel74to emit light similar to the all-on operation). For the example where the target gray level equals 0 (e.g., arrow250), the timing controller54may drive the sub-pixel74from the memory78B and cause a 0% light emission (e.g., all off operation) for each sub-frame to convey the target gray level of 0.

Furthermore, for the example where the target gray level equals120(e.g., arrow252), the timing controller54may drive the sub-pixel from the memory78B for the first sub-frame for an all on operation (e.g., arrow254) to emit light at a gray level substantially similar or equal to 63/63, drive the sub-pixel from the memory78A for the second sub-frame for a modulation operation (e.g., arrow256) to emit light at a gray level substantially similar or equal to 55/63, drive the sub-pixel from the memory78B for the third sub-frame and the fourth sub-frame for an all off operation (e.g., arrow258A, arrow258B) to emit light at a gray level substantially similar or equal to 0/63 for two sub-frames. Thus, when the light emission over the four sub-frames is perceived by the operator of the display18, the sub-pixel74is perceived as emitting light according to the target gray level of 119 (e.g., 119/2556 visualized by natural number representation260).

Each sub-frame, then, may be assigned an emission operation by the timing controller54for each sub-pixel74. Sometimes, the sub-pixel74is instructed to emit light regardless of data stored in the memory78A (e.g., all on operation, all off operation), while sometimes the sub-pixel74is instructed to emit light according to data stored in the memory78A. For example, the modulation operation may permit the sub-pixel74to emit light according to data stored in the memory78A (e.g., binary data).

Data stored in the memory78B may correspond to relatively more significant bit positions than the bit positions represented by data stored in the memory78A, thus enabling the memory78B to drive contiguous light emission or unmodulated light emission (of no light or unmodulated light). In this way, while the sub-pixel74is building up to emit at the target gray level, the sub-pixel74may be driven using more significant bits that have more of an influence on a final gray level without concern for the lesser significant bits. This emission may continue until the time is reached to use the less significant bits in the emission of light to fine tune a total amount of light emitted to be perceived as the target gray level.

FIG.16is a plot illustrating a gamma relationship between gray levels (e.g., x-axis) and pulse width control operations (e.g., y-axis). Dotted lines276illustrate sub-frames and how the binary data ranges supported by the memory78may conform to dual-memory driving techniques. Each sub-frame may correspond to a 2Mrange of gray levels. In this way, the gray levels in the first sub-frame may correspond to gray levels between 0 and 2m−1, the second sub-frame may correspond to a number between 2M- and 2*2M−1, the third sub-frame may correspond to a number between 2*2Mand 3*2M−1, and the fourth sub-frame may correspond to a number between 3*2Mand 4*2M−1. When driving a sub-pixel74to emit light at a target gray level 278, the sub-pixel74may be operated to emit unmodulated light during the first sub-frame, operated to emit modulation light during the second sub-frame, and operated to emit no light during the third sub-frame and fourth sub-frame.

The most significant bit controlling modulation operations of the sub-pixel74may be updated between sub-frames, such as in response to a direct control signal from the timing controller54, row driver60, column driver62, or the like, and/or in response to a counter incrementing through a binary counting sequence until equaling the target gray level. In this way, the bit controlling whether the sub-pixel74emits unmodulated light, emits no light, or emits modulated light, may be updated between sub-frames. Updating the bit between sub-frames may enable the change of emission behavior from the sub-pixel74. It is noted that, in some cases, the display18may be a linear display, which may change the relationship between gray levels and pulse width control operations (e.g., where pulse widths used to control light emission do not necessarily exponentially increase overtime and may increase at a constant rate as gray levels increase).

FIG.17is a circuit diagram of a sub-pixel74that includes memory-in-pixel circuitry. As described at least in reference toFIG.8, using memory-in-pixel techniques and a comparator120may enable a row driver to create a single pulse width modulation emission scheme. Accordingly, an example of the sub-pixel74including the comparator120, memory78A, and memory78B is shown inFIG.17. It should be appreciated that the sub-pixel74is intended to be illustrative and not limiting. For example, while the comparator120is shown as being coupled to LED driver circuitry and to light-emitting circuitry of the sub-pixel74, the comparator120may couple to any suitable light-emitting circuitry and/or driving circuitry.

In the depicted sub-pixel74, image data56A is used to generate data284to be stored in the memory78A and data286to be stored in the memory78A. Writing data284into the memory78may involve the row driver60enabling a control signal288(e.g., write_en control signal) to cause transmission of the data284into inverter pairs290. In some embodiments, the row driver60operates in tandem with the column driver62to cause parallel transmission of all bits associated with the data284into the inverter pairs290by enabling control signals288at the same time. Additionally or alternatively, the row driver60may cause bitwise transmission of bits associated with the data284through selectively enabling control signals288, for example, loading a bit into inverter pair290A by selectively enabling control signal288A to cause transmission of the first bit of the data284.

The data286stored in inverter pair292may correspond to a control signal generated by the row driver60, column driver62, timing controller54, or the like to cause the sub-pixel74to emit light according to an all on operation. Additionally or alternatively, the data286stored in the inverter pair292may correspond to a compare result (e.g., a comparison result).

The row driver60, column driver62, timing controller54, or the like, may generate the compare result by comparing most significant bits stored in the memory78B to corresponding most significant bits of a present count of the counter108(e.g., a portion of the present count). While waiting for most significant bits stored in memory78B to match the corresponding most significant bits of a current state of the count, the sub-pixel74to emit light according to an all on operation since light emission is performed regardless of bit values stored in memory78A. When the most significant bits stored in memory78B match the corresponding most significant bits of the count, the compare result may toggle and cause the after-toggle value to be stored in the inverter pair292. In some cases, the compare result stored in the inverter pair292may equal a logical high value (e.g., a voltage value interpreted as a logic high value by circuitry of the electronic device10). The compare result may be applied to a switch294and cause the switch294to decouple the comparator120from the inverter pair296in response to the compare result having a logic high value after the matching.

Once the data284is stored in the inverter pairs290, and once the data286stored in the inverter pair292permits modulated driving of the sub-pixel74(e.g., a match has occurred and the data286resulting a comparison result indicating that the count at least matches the corresponding bits of the image data56A), light emission may continue according to a modulated operation. During a modulated output, the comparator120uses the stored bits of data284and count bits (e.g., CNT) received at switches298(e.g., transistors) from counter108indicative of the present count to perform a comparison between the two sets of bits.

As a reminder, in a single pulse width modulation emission scheme, the counter108may increments up to a maximum gray level in response to a transition of a clocking signal, like a gray level clock110, where light emission occurs from the sub-pixel74until the counter108counts up to a number equaling and/or exceeding a number represented by stored data284. The counter108may include nodes, where signals of the nodes may transmit at values able to be interpreted by circuitry as binary numbers of a count. For example, when the count is 1 from 15, the counter108may generate signals that represent “0001” since the maximum number represented by 4 bits is 15. Each of the switches298may receive either the signal representative of the count or a signal represented of an opposite count (e.g., CNTn<0:4>, inverse count). When each signal representing the count matches each signal representing the data284(e.g., when each bit matches each bit), the comparator120may output a logical high signal (e.g., MTCH=1). When the count does not match data284, the comparator120may output a logical low signal (e.g., MTCH=0) since at least one of the combinations of the signals may cause at least one of the switches298to couple to ground (e.g., a logic low reference voltage, a system low voltage, voltage equal to 0 volts, first reference voltage114) without also coupling a logical high output from a corresponding of the inverter pairs290to the switch294. In this way, the comparator120performs a compression of all of the bits of data284into a single bit indicative of if the data284is the same as the count transmitted from the counter108. Thus, the comparator120performs a bitwise exclusive not-or function (XNOR) compression to a single bit, where an output from the comparator120is a logical low (e.g., “0”) value unless every bit matches.

The output from the comparator120may be stored in inverter pair296. The inverter pair296may retain the value until the row driver60resets a voltage stored by the inverter pair296using a reset signal300. The reset signal300may activate a switch301(e.g., initialization transistor). When the switch301is “on” (e.g., activated), the inverter pair296may couple to ground.

Furthermore, a switch302may be included in a sub-pixel74to provide power-saving benefits from precharging a common output node of the comparator120(e.g., MTCH) thereby making the circuitry more responsive to changes in the output from the comparator120. Precharging the common output node may involve the timing controller54and/or the row driver60generating and transmitting a precharge signal304(PCH) to cause the switch294to couple the common output node to a system logic high reference voltage. Precharging one or more portions of the sub-pixel74prior to driving of the sub-pixel74may permit lower changes in voltages to change an operation of the sub-pixel74, such as by bringing voltage levels of the components closer to the voltage level separating logic low from logic high in the system. It is noted that the output from the depicted circuitry is output as a emission control (EM) signal306that drives emission from the LED104of the sub-pixel74until the output from the comparator120stops the emission (e.g., MTCH=1). The inverter pair296may receive a value for storage in response to a switch307being activated, thereby completing an electrical path to the inverter pair296. Thus, the timing controller54may drive the sub-pixel74to determine whether the count of the counter108matches the image data56A before activating the switch307to lock the result of the determination (e.g., comparison) in circuitry of the inverter pair296.

It should be appreciated that a variety of valid embodiments may apply described memory-in-pixel techniques, and thus, in some embodiments, counting circuitry may decrement. In this way, the comparator120may output a logical low value if every bit matches and/or the switch302may be excluded from the sub-pixel74.

To explain operation further,FIG.18is a timing diagram comparing the changing of a count308of the counter108to the state of the EM signal306. The gray level clock110may be monotonically increasing, thereby causing the increasing duration of time between changes in the count308. Durations of time corresponding to each sub-frame are delineated via lines similar to line310. In this way, the first sub-frame of this example corresponds to an all on operation (e.g., symbol312), the second sub-frame of this example corresponds to an all on operation (e.g., symbol314), the third sub-frame of this example corresponds to an all on operation (e.g., symbol316), and the fourth sub-frame of this example corresponds to an all on operation (e.g., symbol318).

Between the first sub-frame and the second sub-frame, such as during a designated write time period320between transitions in the count308(and thus also between transitions in the gray level clock110), the bits stored in memory78B (e.g., most significant bits (MSBs)) may not be updated, and thus continue to drive the sub-pixel74from the memory78B. Between the second sub-frame and the third sub-frame (e.g., during the write time duration322), the memory78B may update to store data equal to 0. This switches which memory drives the sub-pixel74from the memory78B to the memory78A. Thus, during the third sub-frame (e.g., sub-frame duration324), the memory78A drives the sub-pixel74to emit light. The sub-pixel74emits light according to a modulated operation since the light emission is anticipated to stop at some time during the third sub-frame duration324. In this case, light emission stopped at time326, where a total amount of light emitted by the sub-pixel74leading up to the time326is perceived as the target gray level or substantially similar to the target gray level.

FIG.19illustrates a process340for operating the sub-pixel74according to dual-control driving schemes. Generally, the process340includes initializing memory circuitry for a present frame (e.g., frame) (block342), precharging common output from comparator (block344), causing emission based on dual-control operations (block346), and preparing for a next frame (block350). In some embodiments, the process340may be performed at least in part by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as the storage device14, using processing circuitry, such as the processing core complex12. Additionally or alternatively, the process340may be implemented at least in part based on circuit connections formed in display controlling circuitry, such as a row driver60, a column driver62, and/or a timing controller54. As described herein, the process340is performed by the timing controller54.

Thus, in some embodiments, the timing controller54may initialize memory78to prepare to present a frame (e.g., current frame, present frame to be presented) (block342). To initialize the memory78, the timing controller54may use the row driver60and/or the column driver62to generate a control signal to force one or more nodes of the memory78to a low voltage value to reset and/or clear the memory78. The timing controller54may enable the reset signal300(e.g., via the row driver60) to reset a voltage value stored in the inverter pair296. In some cases, the memory78is initialized by the timing controller54instructing the writing of the image data56A to the memory78. Initializing the memory78may enable light-emitting circuitry of the sub-pixel74(e.g., LED104) to emit until the comparator120outputs a control signal to stop light emission (e.g., in response to the gray level stored in memory being reached by the counter108). In other words, for one or more sub-pixels74implementing a comparator120, sub-pixels74may start light emission together at the same time but stop light emission at different times, where the respective duration of light emission corresponds to a target gray level for the respective sub-pixel74.

The row driver60may precharge the sub-pixel74after initializing the memory78(block344). To precharge the sub-pixel74, the row driver60may enable a precharge signal to cause a voltage to boost a voltage of a node coupling an output from the comparator120to an input of the inverter pair296. Boosting the voltage of the node may cause the sub-pixel74to be more responsive to changes in output from the comparator120.

After precharging one or more portions of the sub-pixel74, the timing controller54cause light emission from the sub-pixel74based on dual-control operations (block346). For example, the timing controller54may cause a count of counter108to change (e.g., increment, decrement). The timing controller54may increment the counter108by using the gray level clock110, such that the count represented by outputs from the counter108change in response to a rising or falling edge of the gray level clock110. The emission of light from the LED104may stop once the count of the counter108exceeds the image data56A. After changing the count of counter108, the sub-pixel74may automatically determine if the count of the counter108is greater than or equal to a value represented by the image data56A. This occurs since a subset of bits of the count and a subset of bits of the image data56A are transmitted to the comparator120for comparison. The comparator120may output a logical high value when none of the bits match or may output a logical low value when each of bits match or when a bit changes that would signify that the image data56A has been exceeded by the count. This output from the comparator120may stop light emission from the sub-pixel74.

Once the sub-pixel74emits light at the target gray level, or emits an amount of light substantially similar to the target gray level, the timing controller54may prepare to present a next frame, or a portion of a next frame (as may be the case in partial frame presentation operations) (block350). In this way, the timing controller54may repeat operations of the process340to present a subsequent frame, where the subsequent frame may include one or more repeated gray levels from the initial frame. Data stored in the memory78may not be changed or overwritten when gray levels assigned to the sub-pixel74does not change between frames. In some cases, each sub-pixel74receives the image data56A for the subsequent frame regardless of whether a portion of the initial frame repeats in the subsequent frame, or whether a portion of the subsequent frame is to be presented using sub-pixels74emitting light at a repeated gray level relative to the initial frame.

To elaborate further on the dual-control operation discussed with reference toFIG.19(e.g., block346),FIG.20is an illustration depicting an all on operation of the sub-pixel74(e.g., represented as changing over time as within block360) and a modulated operation of the sub-pixel74(e.g., represented as changing over time as within block362) in response to a count of the counter108(e.g., represented as changing over time as within block364) andFIG.21is an illustration depicting an all off operation of the sub-pixel74(e.g., represented as changing over time as within block366) in response to a count of the counter108(e.g., represented as changing over time as within the block364). For ease of explanation,FIG.20andFIG.21are described together. The example memory system shown inFIG.20andFIG.21corresponds to the memory78being of total size 8 bits, where the memory78A stores 6 bits and the memory78B stores 2 bits. The block364shows a representation over time of a count maintained by the counter108. In this way, the counter108may include multiple serially coupled flip-flop or state-holding devices that operate in response to a clock (e.g., gray level clock110) to transition an output between binary states (e.g., an output representative of a voltage level at nodes between the serially coupled flip-flops or devices).

For this example memory configuration where the memory78has a total size of 8 bits, a total range of 256 gray levels may exist. “00000000” may represent a lowest gray level for the 256 gray levels and “11111111” may represent a highest gray level for the 256 gray levels. The sub-pixel74may be driven to emit light according to data stored in the memory78, where the data stored may indicate a target gray level out of the total range of gray levels. For example, the target gray level in this example may correspond to140from the 256 total options for gray levels (e.g., 54.7% brightness relative to maximum brightness). The gray level140may be represented by binary data “10001100.” In this example, the memory78B stores relatively more significant bits of the target gray level (e.g., binary data “10”) and the memory78A stores the remaining bits (e.g., binary data “001100”).

When controlling light emission from the sub-pixel74, the generally described comparison operation may be split into two operations (e.g., dual-control). The first operation may cause light emission until the more significant bits match, then once the more significant bits match, the second operation may cause light emission until the remaining bits (e.g., less significant bits) match (e.g., to fine tune the gray level). Light emission is caused during the first operation based on a comparison between the bits stored in the memory78B and the corresponding bits of the count (e.g., bits368). Each time the count is incremented, in this example, the corresponding bits of the count are compared to the bits stored in the memory78B. Since there is no way for the image data56A to equal the count when the first few bits do not match, the sub-pixel74may be driven to emit light without concern via the all on operation (e.g., block360) for whether the remaining bits match while waiting for the count to match the first few bits of the image data56A.

While driven according to the all on operation (e.g., block360), the sub-pixel74emits light without consideration for data stored in the memory78A. While the first two bits of the count do not match the data stored in memory78B, the data286equals a logical high value (e.g., “1”), the switch294is operated off. Output from the comparator120may be stopped from being able to drive the sub-pixel74to emit light while the switch294is off. The data286may change to equaling a logical low value (e.g., “0”) once the first two bits of the count match the data stored in memory78B. A write control signal291(write enX control signal) may be enabled during the all on operation (e.g., block360), such that the change is captured in the inverter pair292relatively soon after the change occurs.

To illustrate this change, subset370of represented count states corresponds to when the first two bits of the count do not match the data stored in memory78B (e.g., “00000000” through “01111111”) and subset372of represented count states corresponds to when the count matches the data stored in memory78B (e.g., “10000000” through “10111111”). When the data286changes to the logical low value (e.g., “0”), the switch294is activated, thereby permitting an output from the comparator120(e.g., MTCH) to drive light emission of the sub-pixel74.

When the data286changes to the logical low value (e.g., “0”), the sub-pixel74may be driven to emit light according to data stored in the memory78B via the modulated operation (e.g., block362), where any remaining bits of the image data56A are used to fine tune an amount of light emitted by the sub-pixel74during the all on operation (e.g., block360). The sub-pixel74may emit light until remaining bits of the count is greater than or equal to the image data56A. When the count is greater than the image data56A (e.g., once the last six bits of the count exceed the six bits of image data56A stored in memory78A), the output from the comparator120may be a logic high level, and thus may stop light emission from the sub-pixel74as part of an all off operation (e.g., block366). This transition between the modulation operation (e.g., block362) and the all off operation (e.g., block366) may occur in response to the count changing from count374to count376.

While driven according to the all off operation (e.g., block366), the sub-pixel74may not emit light and/or may be driven to not emit light. The transition into the all off operation (e.g., block366) may lock the logical high value generated by the comparator120into the inverter pair296and/or may disable precharge signal304, thereby disabling the output of the comparator120from adjusting the value stored in the inverter pair296. In this way, new image data56A may be loaded into the memory78A after transition into the all operation (e.g., block366) to prepare for the next frame without interrupting a presentation of the ongoing frame. The all off operation (e.g., block366) may continue while the count finishes transitioning through remaining states corresponding to subset378of count states (e.g., “10001101” through “11111111”). The sub-pixel74may not be driven to emit light again until the inverter pair296is reset and storing a logical low value (e.g., “0”). In this way, the timing controller54may transmit the reset signal300(e.g., fromFIG.17) when ready to begin presentation of a subsequent frame. It is noted that since the inverter pair292is operated to store a compare result in response to write control signal291, the value stored in the inverter pair292may not change during the all off operation (e.g., block366) since the write control signal291is not transmitted during the all off operation (e.g., block366). It is noted that although the term “all” is used to describe “all on operation” or “all off operation,” it should be understand that these operations may apply to one sub-pixel74, one pixel72, a region of pixel array70, a region of sub-pixels74, an entire display18, or any combination thereof.

Using dual-control (e.g., memory78A and memory78B) to drive the sub-pixel74may help reduce power consumed by the driving circuitry (e.g., inverter pairs290, comparator120) by reducing an amount of time that the driving circuitry is driving the sub-pixel74to emit light since the driving circuitry may be decoupled from power supplies when not driving the sub-pixel74. Dual-control driving may additionally or alternatively improve driving flexibility of the display18by increasing a number of options for loading image data and/or driving the sub-pixel74to emit light. Furthermore, dual-control driving of the sub-pixel74may enables single pulse width modulation driving techniques to be used with pixels that include memory.

FIG.22is a timing diagram of an example operation of the sub-pixel74according to various operations of process340. For example, the timing controller54may drive the sub-pixel74according to initialize operations (e.g., block342), precharge operations (e.g., block344), increment and evaluate operations (e.g., block346), write back operations, and ultimately, after performing one or more interactions of precharge operations, write operations, and/or increment and evaluate operations, prepare operations to prepare for a next frame (e.g., block350). Various combinations of control signals generated in response to instructions from the timing controller54may be illustrated inFIG.22and described herein.

For example, to initialize the sub-pixel74, the timing controller54may cause activation of the reset signal300. The initialization may cause a value stored by the inverter pair296(e.g., signal392) to reset to a logical low value (e.g., “0”). The activation of the reset signal300may correspond to a resetting of the clock used to transition the count maintained by the counter108(e.g., signal394) and received at switches298of the comparator120. The signal394may be of a logical high value sufficiently after an initialization period396and a precharge period398to cause the first instance of change in count (e.g., from 0 to 1) to occur once the sub-pixel74is ready to continue emission.

To precharge the sub-pixel74, the timing controller54may toggle the precharge signal304(e.g., signal400). The image data56A may be loaded into some or both memory78(e.g., memory78A, memory78B) during the initialization period396.

During an increment and evaluation period404, the precharge signal304may toggle to a state opposite of what it was during a portion of the precharge period398. The count may increment in response to a state of the clock (e.g., signal394), where the “4′h0” labeled portions of the signal394correspond to a duration of time between changes in count, such as a duration of time to drive the counter108to update its count. “4′hn . . . 4′h1. . . 4′hF” labeled portions of the signal394may correspond to a duration of time associated with the count of the counter108is reading the indicated number of “4′hb,” “4′h1,” or so on.

A match between the count and the image data56A stored in the memory78may be automatically evaluated. If the count matches the image data56A stored in memory78B, a value of the output from the comparator120may change (e.g., represented by toggling of a signal406). It is noted that the signal406may be briefly driven high during the precharge period398to reset the value of the output from the comparator120and thus precharge the node coupling the comparator120to the switch294, and the evaluation may be performed after the precharge period398(and any subsequent precharge periods). The output of the comparator120may be precharged one or more times for each frame to enable a relatively lower change in voltage cause the change in state of the switch294, thereby causing a temporary toggling of the signal406during the precharge period398.

Once the signal406goes high during the precharge period398, a subsequent high level of the signal406during the increment and evaluation period404may cause the output from the inverter pair296to go high during a write back period408. The switch307may be controlled in response to a logical high level of a control signal (e.g., signal410). During the write back period408, the switch307may activate in response to toggling of the signal410to the logical high level, thereby causing the output from the comparator120to be stored in the inverter pair296as the signal392. Light emission from the sub-pixel74stops in response to the signal392going high. The signal392may remain high until a subsequent initialization period396corresponding to a subsequent frame, and thus until the next frame. Furthermore, once the signal392goes high, and remains high, the signal406may stop charging up to the high level, and thus may remain at a logical low value until the subsequent initialization period396. In this way, it may be said that the signal406(e.g., output from the comparator120) and the signal392(e.g., output from the inverter pair296) may be reset at a substantially similar time during initialization periods396and/or in response to the reset signal300.

Keeping the foregoing in mind, the timing controller54may reload data for each sub-pixel74between sub-frames. This may mean that sometimes the data stored in the memory78A changes between sub-frames, such that the memory78A may be loaded independent of loading operations for the memory78B. For example, data stored in the memory78A during a first sub-frame for a first frame may correspond to a previous frame until the timing controller54updates data stored in memory78A for a present frame. This may improve driving operations by improving a capability of the display18for parallel driving and/or parallel image frame processing operations (e.g., enabling the loading of one image frame while completing presentation of a second image frame). Consider the case where a first image frame is to be presented before a second image frame. The first image frame may be displayed over a set of four sub-frame driving periods and the second image frame may be displayed over a set of four sub-frame driving periods. The timing controller54may drive the sub-pixel74to emit light from the memory78A for last sub-frame corresponding to presentation of the first image frame while loading data into the memory78B for presentation of a first sub-frame corresponding to presentation of the second image frame.

Furthermore, in some cases, data may be stored in the memory78A during a similar loading operation as the memory78B, such that the memory78A is preloaded before the emission operation according to the memory78A (e.g., modulation operation362). When driving the display18using separate loading sequences for the memory78A and the memory78B, the loading of each portion of the memory78may occur when relatively optimal for the display18, such as when a refresh is to already occur, which may improve efficiencies of the display18.

As has been discussed throughout this disclosure, it should be understood that memory-in-pixel techniques are valid for a variety of embodiments and display technologies. It should also be understood that for each reference voltage discussed, or disclosed in the figures, additional or alternative reference voltages may be used. Additionally or alternatively, it is noted that although described as reducing or eliminating a reliance on using a frame buffer, memory-in-pixel techniques may be used in tandem with a frame buffer in some embodiments. Furthermore, although memory circuitry has been described as storing 6 bits and/or 8 bits, it should be appreciated that any suitable memory structure may be used to store any suitable number of bits, such as 12 bits or 16 bits. It is also noted that any of the described systems or methods may be used in combination of with one another. For example, a memory shared between sub-pixels may benefit from driving methods that also use external allocated memory to the sub-pixels when driving the respective sub-pixels to emit light.

Accordingly, technical effects of the present disclosure include techniques for implementing memory in one or more pixels of a display to improve processing techniques of image data for presentation, for example, by using a relatively higher bit depth to represent a target gray level than what is able to be stored by individual memories storing data corresponding to the target gray level. The techniques include systems and methods for receiving image data, storing the image data in memory allocated for the pixel (e.g., in memory internal to the pixel and allocated external memory), and transmitting the image data to a driver circuit to operate a light-emitting element of a pixel to emit light. By driving a pixel according to image data stored in memory allocated to the pixel, driving operations may improve, for example, by increasing flexibility of options to be used to load or store image data for the pixel and/or by increasing a bit depth able to be used to load or store image data beyond capabilities provided by the memory-in-pixel (e.g., memory internal to the pixel). For example, storing image data in memory internal to the pixel may be loaded at a different time than image data to be loaded in external memory allocated to the pixel. Furthermore, using dual-control driving of the sub-pixel may help reduce power consumed by driving circuitry of the sub-pixel and/or the sub-pixel by reducing an amount of time that circuitry (e.g., driving circuitry) of the sub-pixel is transmitted electrical signals to drive the sub-pixel74. A duration of time electrical signals are transmitted using circuitry of the sub-pixel may reduce in time and/or reduce in a number of components consuming power since some circuitry of the sub-pixel may be decoupled from power supplies when not being used to drive the sub-pixel74. Furthermore, dual-control of the sub-pixel74enables single pulse width modulation driving techniques to be used with pixels that include memory.

The techniques described herein may be applied and integrated with a variety of display technologies and should not be limited to the specific embodiments depicted and/or described herein. For example, pixels with memory are shown as having a light-emitting diode as a light-modulating device, however, the memory-in-pixels techniques may be generally applied to different pixel circuitry to support a variety of display technologies that use a variety of light-modulating devices. In this way, suitable pixel circuitry supporting light emission via a light-emitting diode, a digital mirror display, an organic light-emitting diode, or circuitry supporting a liquid crystal display, a plasma display, or a dot-matrix display may each have memory in the pixel to achieve at least improvements to data transmission bandwidths and ease of programming the pixels.