Semiconductor device package having galvanic isolation and method therefor

A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package substrate having a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer. The first conductive layer and the second conductive layer are separated by a non-conductive material. A first semiconductor die is attached to a first major side of the package substrate. The first semiconductor die is conductively interconnected to the first inductive coil. A second semiconductor die is attached to the first major side of the package substrate. A first wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.

BACKGROUND

Field

This disclosure relates generally to semiconductor device packaging, and more specifically, to a semiconductor device package having galvanic isolation and method of forming the same.

Related Art

Today, there is an increasing trend to include sophisticated semiconductor devices in products and systems that are used every day. These sophisticated semiconductor devices may include wireless communication between integrated circuit (IC) die. In such applications, electrical (or galvanic) isolation is desired between the die. “Galvanic isolation” generally means that there is no direct current (DC) electrically conductive path between distinct circuits. For example, galvanic isolation may be desired to protect a first IC die that operates at a first supply voltage from a second IC die that operates at a second supply voltage different from the first IC die.

DETAILED DESCRIPTION

Generally, there is provided, a semiconductor device package having galvanic isolation. The packaged semiconductor device includes a first semiconductor die and a second semiconductor die attached to a package substrate. The two semiconductor die are configured to communicate and/or transfer power with one another by way of inductive coils located in the package substrate. In this manner, the two semiconductor die are isolated from one another such that if an electrical over stress (EOS) event damaged the first semiconductor die, the second semiconductor die would remain electrically isolated from the first semiconductor die.

FIG. 1AthroughFIG. 1Cillustrate, in simplified cross-sectional view and corresponding plan views, an example semiconductor device100having galvanic isolation in accordance with an embodiment. In this embodiment, the device100includes a first semiconductor die102and a second semiconductor die104attached to a package substrate106and encapsulated with an encapsulant108.FIG. 1Ashows the cross-sectional view of device100, and the corresponding top side and bottom side plan views of package100are depicted inFIG. 1BandFIG. 1Crespectively. A wireless communication link is formed between the first semiconductor die102and the second semiconductor die104by way of a first inductive coil130and a second inductive coil140configured and arranged for inductive coupling within the package substrate106.

The semiconductor die102has an active side (e.g., major side having circuitry) and a backside (e.g., major side opposite of the active side). In this embodiment, the backside of the semiconductor die102is attached to the package substrate by way of die attach material110. The semiconductor die102includes bond pads (not shown) at the active side configured for conductive connection to conductive features (e.g., conductive traces124and126) of the package substrate106by way of bond wires114and116, for example. The semiconductor die102may be formed from any suitable semiconductor material, such as silicon, germanium, gallium arsenide, gallium nitride, silicon carbide, and the like. In this embodiment, the semiconductor die102may be characterized as a low voltage die, for example. The term “low voltage” as used herein generally refers to an operating voltage in a first voltage domain, for example, sufficient for operation of CMOS digital circuitry. In this embodiment, the semiconductor die102may serve as a controller device configured to control functions of the semiconductor die104by way of the wireless communication link.

The semiconductor die104has an active side (e.g., major side having circuitry) and a backside (e.g., major side opposite of the active side). In this embodiment, the backside of the semiconductor die104is attached to the package substrate by way of die attach material112. The semiconductor die104includes bond pads (not shown) at the active side configured for conductive connection to conductive features (e.g., inductive coil130and conductive trace128) of the package substrate106by way of bond wires118and120, for example. The semiconductor die104may be formed from any suitable semiconductor material, such as silicon, germanium, gallium arsenide, gallium nitride, silicon carbide, and the like. In this embodiment, the semiconductor die104may be characterized as a high voltage die, for example. The term “high voltage” as used herein generally refers to an operating voltage in a second voltage domain sufficient for operation of circuitry such as insulated-gate bipolar transistors (IGBT), for example. In this embodiment, the second voltage domain is different from the first voltage domain, for example, having voltage values different from the first voltage domain. The second voltage domain may be electrically isolated and offset from the first voltage domain. For example, the second voltage domain may be offset from the first voltage domain by ˜400 volts, ˜800 volts, or other voltages. In this embodiment, the semiconductor die104is configured for receiving commands from and/or transferring information with the semiconductor die102by way of the wireless communication link.

The package substrate106has a first major side (e.g., top side) and a second major side (e.g., bottom side) opposite of the first major side. In this embodiment, the package substrate106is formed as a multi-layer laminate structure having a plurality of conductive layers separated by non-conductive material. For example, the package substrate106includes a first conductive layer (e.g., metal)122located at the first major side and a second conductive layer132located at the second major side. The conductive layer122and the conductive layer132are separated by a non-conductive material (e.g., fiber reinforced epoxy material)142. In this embodiment, the conductive layer122is patterned to form conductive traces124-128and the inductive coil130. The conductive layer132is patterned to form conductive traces134-138and the inductive coil140. The package substrate106may include any number of inductive coils130and140configured to form inductive coupling. Conductive vias144-148are formed to provide conductive connections between the conductive traces124-128and the conductive traces134-138, for example. The inductive coil130and the inductive coil140are substantially aligned with one another within the package substrate106to allow for communication by way of inductive coupling.

A first solder mask layer150is formed embedding the conductive traces124-128and the inductive coil130. Openings formed in the solder mask layer150expose portions of the conductive traces124-128and a conductive trace portion connected to the inductive coil130forming substrate pads. The exposed substrate pads allow for connections to the semiconductor die102and104by way of respective bond wires114-120, for example. In the embodiment depicted inFIG. 1A, the semiconductor die102is attached on the solder mask layer150and the semiconductor die104is attached on the non-conductive material142through an opening in the solder mask layer150. In other embodiments, one or both of semiconductor die102and104may be attached on the solder mask layer150or attached on the non-conductive material142. A second solder mask layer152is formed embedding the conductive traces134-138and the inductive coil140. Openings formed in the solder mask layer152expose portions of the conductive traces134and138forming connector pads to allow for connections to a printed circuit board (PCB) by way of respective ball connectors154and156, for example. The ball connectors154and156may be any suitable conductive structure such as solder balls, gold studs, copper pillars, and the like, to connect conductive features of the device100with the PCB. In this embodiment, the package substrate106serves as a mechanical carrier, isolation barrier, and external interconnect for device100.

As depicted inFIG. 1A, the encapsulant108(e.g., epoxy molding compound) encapsulates the semiconductor die102, the semiconductor die104, the bond wires114-120, and exposed portions of the top side of the package substrate106. For illustration purposes, the top side plan view (FIG. 1B) of the device100shows the active sides of the semiconductor die102and the semiconductor die104, and portions of bond wires114-120revealed through the encapsulant108. The encapsulated semiconductor die102and semiconductor die104are separated from one another by a distance sufficient to provide desired isolation (e.g., >5 kV for 60 seconds). In this embodiment, the semiconductor die102and the semiconductor die104are separated by a predetermined distance of at least 500 microns to accommodate desired isolation requirements. In other embodiments, the semiconductor die102and the semiconductor die104may be separated by other predetermined distances to accommodate desired requirements depending upon properties of the encapsulant and solder mask materials, for example. The bottom side plan view (FIG. 10) of the device100shows an example ball grid array (BGA) of the ball connectors154and156arranged at the bottom side of the package substrate106. A clearance distance is indicated by arrow labeled158. In this embodiment, the device100is configured with a predetermined clearance distance of approximately 8 millimeters to accommodate desired requirements. In other embodiments, it may be desirable to configure the device100with other clearance distance values.

In this embodiment, a wireless communication link is formed between semiconductor die102and semiconductor die104by way of the inductive coils130and140embedded in the package substrate106. The communication link includes a signal path configured to allow communication between the semiconductor die102and the semiconductor die104while being galvanically isolated from one another. For example, the signal path includes inductive coils130and140substantially aligned to form an inductive coupling within the package substrate106. The signal path further includes the conductive traces126and136, via146, and bond wire116interconnecting the semiconductor die102with the inductive coil140and bond wire118interconnecting the semiconductor die104with the inductive coil130.

FIG. 2illustrates, in a simplified cross-sectional view, an alternative example semiconductor device having galvanic isolation in accordance with an embodiment. In this embodiment, the device200includes a first semiconductor die202and a second semiconductor die204attached to a package substrate206and encapsulated with an encapsulant208. A first inductive coupling within the package substrate206is formed by way of a first inductive coil228and a second inductive coil238, and a second inductive coupling within the package substrate206is formed by way of a third inductive coil230and a fourth inductive coil240. The first and second inductive couplings are connected in series to form a wireless communication link between the first semiconductor die202and the second semiconductor die204.

The semiconductor die202has an active side and a backside. In this embodiment, the backside of the semiconductor die202is attached to the package substrate by way of die attach material210. The semiconductor die202includes bond pads (not shown) at the active side configured for conductive connection to conductive features (e.g., conductive trace224and inductive coil228) of the package substrate206by way of bond wires214and216, for example. The semiconductor die202may be formed from any suitable semiconductor material, such as silicon, germanium, gallium arsenide, gallium nitride, silicon carbide, and the like. In this embodiment, the semiconductor die202may be characterized as a low voltage die having an operating voltage in a first voltage domain sufficient for operation of CMOS digital circuitry, for example. In this embodiment, the semiconductor die202may serve as a controller device configured to control functions of the semiconductor die204by way of the wireless communication link.

The semiconductor die204has an active side and a backside. In this embodiment, the backside of the semiconductor die204is attached to the package substrate by way of die attach material212. The semiconductor die204includes bond pads (not shown) at the active side configured for conductive connection to conductive features (e.g., inductive coil230and conductive trace226) of the package substrate206by way of bond wires218and220, for example. The semiconductor die204may be formed from any suitable semiconductor material, such as silicon, germanium, gallium arsenide, gallium nitride, silicon carbide, and the like. In this embodiment, the semiconductor die204may be characterized as a high voltage die having an operating voltage in a second voltage domain different from the first voltage domain sufficient for operation of circuitry such as insulated-gate bipolar transistors (IGBT), for example. The second voltage domain may be electrically isolated and offset from the first voltage domain. In this embodiment, the semiconductor die204is configured for receiving commands from and/or transferring information with the semiconductor die202by way of the wireless communication link.

The package substrate206has a first major side and a second major side opposite of the first major side. In this embodiment, the package substrate206is formed as a multi-layer laminate structure. For example, the package substrate206includes a first conductive layer (e.g., metal)222located at the first major side and a second conductive layer232located at the second major side. The conductive layer222and the conductive layer232are separated by a non-conductive material (e.g., fiber reinforced epoxy material)242. In this embodiment, the conductive layer222is patterned to form conductive traces224-226and inductive coils228-230. The conductive layer232is patterned to form conductive traces234-236,246and inductive coils238-240. The package substrate206may include any number of inductive coils228-230and238-240configured to form inductive coupling. Conductive vias244and248are formed to provide conductive connections between the conductive traces224-226and the conductive traces234-236, for example. The inductive coil228and the inductive coil238are substantially aligned with one another within the package substrate206to allow for communication by way of inductive coupling. Likewise, the inductive coil230and the inductive coil240are substantially aligned with one another within the package substrate206to allow for communication by way of inductive coupling.

A first solder mask layer250is formed embedding the conductive traces224and226and the inductive coils228and230. Openings formed in the solder mask layer250expose portions of the conductive traces224and226and conductive trace portions connected to the inductive coils228and230forming substrate pads. The exposed substrate pads allow for connections to the semiconductor die202and204by way of respective bond wires214-220, for example. A second solder mask layer252is formed embedding the conductive traces234-236,246and the inductive coils238-240. Openings formed in the solder mask layer252expose portions of the conductive traces234and236forming connector pads to allow for connections to a printed circuit board (PCB) by way of respective ball connectors254and256, for example. The ball connectors254and256may be any suitable conductive structure such as solder balls, gold studs, copper pillars, and the like, to connect conductive features of the device200with the PCB. In this embodiment, the package substrate206serves as a mechanical carrier, isolation barrier, and external interconnect for device200.

The encapsulant208(e.g., epoxy molding compound) encapsulates the semiconductor die202, the semiconductor die204, the bond wires214-220, and exposed portions of the top side of the package substrate206. The encapsulated semiconductor die202and semiconductor die204are separated from one another by a distance sufficient to provide desired isolation. In this embodiment, the semiconductor die202and the semiconductor die204are separated by a predetermined distance to accommodate desired requirements.

In this embodiment, a wireless communication link is formed between semiconductor die202and semiconductor die204by way of the inductive coils228-230and238-240embedded in the package substrate206. The communication link includes a signal path configured to allow wireless communication between the semiconductor die202and the semiconductor die204while being galvanically isolated from one another. For example, the signal path includes a first set of inductive coils228and238substantially aligned to form the first inductive coupling within the package substrate206and a second set of inductive coils230and240substantially aligned to form the second inductive coupling within the package substrate206. Conductive trace246interconnects inductive coils238and240thus forming a series connection of the first set of inductive coils with the second set of inductive coils coupled between the semiconductor die202and the semiconductor die204. The signal path further includes the bond wire216interconnecting the semiconductor die202with the inductive coil228and bond wire218interconnecting the semiconductor die204with the inductive coil230.

FIG. 3illustrates, in a simplified cross-sectional view, an alternative example semiconductor device having galvanic isolation in accordance with an embodiment. In this embodiment, the device300includes a first semiconductor die302and a second semiconductor die304attached to a package substrate306and encapsulated with an encapsulant308. A first inductive coupling within the package substrate306is formed by way of a first inductive coil328and a second inductive coil338, and a second inductive coupling within the package substrate306is formed by way of a third inductive coil330and a fourth inductive coil340. The first and second inductive couplings are connected in series to form a wireless communication link between the first semiconductor die302and the second semiconductor die304. In this embodiment, the inductive coil328is located such that the semiconductor die302overlaps at least a portion of the inductive coil328and the inductive coil330is located such that the semiconductor die304overlaps at least a portion of the inductive coil330. By locating the inductive coils328and330under the respective semiconductor die302and304, overall package size and footprint can be minimized. In some embodiments, only one of the semiconductor die302and304may overlap one of the respective inductive coils328and330.

The semiconductor die302has an active side and a backside. In this embodiment, the backside of the semiconductor die302is attached to the package substrate by way of die attach material310. The semiconductor die302includes bond pads (not shown) at the active side configured for conductive connection to conductive features (e.g., conductive traces324and342) of the package substrate306by way of bond wires314and316, for example. The semiconductor die302may be formed from any suitable semiconductor material, such as silicon, germanium, gallium arsenide, gallium nitride, silicon carbide, and the like. In this embodiment, the semiconductor die302may be characterized as a low voltage die having an operating voltage in a first voltage domain sufficient for operation of CMOS digital circuitry, for example. In this embodiment, the semiconductor die302may serve as a controller device configured to control functions of the semiconductor die304by way of the wireless communication link.

The semiconductor die304has an active side and a backside. In this embodiment, the backside of the semiconductor die304is attached to the package substrate by way of die attach material312. The semiconductor die304includes bond pads (not shown) at the active side configured for conductive connection to conductive features (e.g., conductive traces344and326) of the package substrate306by way of bond wires318and320, for example. The semiconductor die304may be formed from any suitable semiconductor material, such as silicon, germanium, gallium arsenide, gallium nitride, silicon carbide, and the like. In this embodiment, the semiconductor die304may be characterized as a high voltage die having an operating voltage in a second voltage domain different from the first voltage domain sufficient for operation of circuitry such as insulated-gate bipolar transistors (IGBT), for example. The second voltage domain may be electrically isolated and offset from the first voltage domain. In this embodiment, the semiconductor die304is configured for receiving commands from and/or transferring information with the semiconductor die302by way of the wireless communication link.

The package substrate306has a first major side and a second major side opposite of the first major side. In this embodiment, the package substrate306is formed as a multi-layer laminate structure. For example, the package substrate306includes a first conductive layer (e.g., metal)322located at the first major side and a second conductive layer332located at the second major side. The conductive layer322and the conductive layer332are separated by a non-conductive material (e.g., fiber reinforced epoxy material)348. In this embodiment, the conductive layer322is patterned to form conductive traces324-326,342-344and inductive coils328-330. The conductive layer332is patterned to form conductive traces334-336,346and inductive coils338-340. The package substrate306may include any number of inductive coils328-330and338-340configured to form inductive coupling. Conductive vias358and360are formed to provide conductive connections between the conductive traces324-326and the conductive traces334-336, for example. The inductive coil328and the inductive coil338are substantially aligned with one another within the package substrate306to allow for communication by way of inductive coupling. Likewise, the inductive coil330and the inductive coil340are substantially aligned with one another within the package substrate306to allow for communication by way of inductive coupling.

A first solder mask layer350is formed embedding the conductive traces324-326,342-344and the inductive coils328and330. Openings formed in the solder mask layer350expose portions of the conductive traces324-326,342-344and conductive trace portions connected to the inductive coils328and330forming substrate pads. The exposed substrate pads allow for connections to the semiconductor die302and304by way of respective bond wires314-320, for example. A second solder mask layer352is formed embedding the conductive traces334-336,346and the inductive coils338-340. Openings formed in the solder mask layer352expose portions of the conductive traces334and336forming connector pads to allow for connections to a printed circuit board (PCB) by way of respective ball connectors354and356, for example. The ball connectors354and356may be any suitable conductive structure such as solder balls, gold studs, copper pillars, and the like, to connect conductive features of the device300with the PCB. In this embodiment, the package substrate306serves as a mechanical carrier, isolation barrier, and external interconnect for device300.

The encapsulant308(e.g., epoxy molding compound) encapsulates the semiconductor die302, the semiconductor die304, the bond wires314-320, and exposed portions of the top side of the package substrate306. The encapsulated semiconductor die302and semiconductor die304are separated from one another by a distance sufficient to provide desired isolation. In this embodiment, the semiconductor die302and the semiconductor die304are separated by a predetermined distance to accommodate desired requirements.

In this embodiment, a wireless communication link is formed between semiconductor die302and semiconductor die304by way of the inductive coils328-330and338-340embedded in the package substrate306. The communication link includes a signal path configured to allow wireless communication between the semiconductor die302and the semiconductor die304while being galvanically isolated from one another. For example, the signal path includes a first set of inductive coils328and338substantially aligned to form the first inductive coupling within the package substrate306and a second set of inductive coils330and340substantially aligned to form the second inductive coupling within the package substrate306. Conductive trace346interconnects inductive coils338and340thus forming a series connection of the first set of inductive coils with the second set of inductive coils coupled between the semiconductor die302and the semiconductor die304. The signal path further includes the bond wire316and conductive trace342interconnecting the semiconductor die302with the inductive coil328and bond wire318and conductive trace344interconnecting the semiconductor die304with the inductive coil330.

FIG. 4illustrates, in a simplified cross-sectional view, an alternative example semiconductor device having galvanic isolation in accordance with an embodiment. In this embodiment, the device400includes a first semiconductor die402and a second semiconductor die404attached to a package substrate406and encapsulated with an encapsulant408. A first inductive coupling within the package substrate406is formed by way of a first inductive coil428and a second inductive coil438, and a second inductive coupling within the package substrate406is formed by way of a third inductive coil430and a fourth inductive coil440. The first and second inductive couplings are connected in series to form a wireless communication link between the first semiconductor die402and the second semiconductor die404. In this embodiment, the semiconductor die402and the semiconductor die404are oriented in a flip-chip (e.g., active side down) configuration. By orienting the first semiconductor die402and the second semiconductor die404in the flip-chip configuration, overall packaging complexity and costs can be reduced while improving performance and reliability. In some embodiments, only one of the semiconductor die402and404may be oriented in the flip-chip configuration.

The semiconductor die402has an active side and a backside. In this embodiment, the active side of the semiconductor die402is attached to the package substrate in a flip-chip configuration. The semiconductor die402includes bond pads (not shown) at the active side configured for conductive connection to conductive features of the package substrate406by way of conductive connectors410(e.g., copper pillars, gold studs, solder bumps, nanotubes), for example. The semiconductor die402may be formed from any suitable semiconductor material, such as silicon, germanium, gallium arsenide, gallium nitride, silicon carbide, and the like. In this embodiment, the semiconductor die402may be characterized as a low voltage die having an operating voltage in a first voltage domain sufficient for operation of CMOS digital circuitry, for example. In this embodiment, the semiconductor die402may serve as a controller device configured to control functions of the semiconductor die404by way of the wireless communication link.

The semiconductor die404has an active side and a backside. In this embodiment, the active side of the semiconductor die404is attached to the package substrate in a flip-chip configuration. The semiconductor die404includes bond pads (not shown) at the active side configured for conductive connection to conductive features of the package substrate406by way of conductive connectors416(e.g., copper pillars, gold studs, solder bumps, nanotubes), for example. The semiconductor die404may be formed from any suitable semiconductor material, such as silicon, germanium, gallium arsenide, gallium nitride, silicon carbide, and the like. In this embodiment, the semiconductor die404may be characterized as a high voltage die having an operating voltage in a second voltage domain different from the first voltage domain sufficient for operation of circuitry such as insulated-gate bipolar transistors (IGBT), for example. The second voltage domain may be electrically isolated and offset from the first voltage domain. In this embodiment, the semiconductor die404is configured for receiving commands from and/or transferring information with the semiconductor die402by way of the wireless communication link.

The package substrate406has a first major side and a second major side opposite of the first major side. In this embodiment, the package substrate406is formed as a multi-layer laminate structure. For example, the package substrate406includes a first conductive layer (e.g., metal)422located at the first major side and a second conductive layer432located at the second major side. The conductive layer422and the conductive layer432are separated by a non-conductive material (e.g., fiber reinforced epoxy material)442. In this embodiment, the conductive layer422is patterned to form conductive traces424-426,418-420and inductive coils428-430. The conductive layer432is patterned to form conductive traces434-436,446and inductive coils438-440. The package substrate406may include any number of inductive coils428-430and438-440configured to form inductive coupling. Conductive vias444and448are formed to provide conductive connections between the conductive traces424-426and the conductive traces434-436, for example. The inductive coil428and the inductive coil438are substantially aligned with one another within the package substrate406to allow for communication by way of inductive coupling. Likewise, the inductive coil430and the inductive coil440are substantially aligned with one another within the package substrate406to allow for communication by way of inductive coupling.

A first solder mask layer450is formed embedding the conductive traces424-426,418-420and the inductive coils428-430. Openings formed in the solder mask layer450expose substrate pads for connections to the semiconductor die402and404by way of respective conductive connectors410and416, for example. A second solder mask layer452is formed embedding the conductive traces434-436,446and the inductive coils438-440. Openings formed in the solder mask layer452expose portions of the conductive traces434and436forming connector pads to allow for connections to a printed circuit board (PCB) by way of respective ball connectors454and456, for example. The ball connectors454and456may be any suitable conductive structure such as solder balls, gold studs, copper pillars, and the like, to connect conductive features of the device400with the PCB. In this embodiment, the package substrate406serves as a mechanical carrier, isolation barrier, and external interconnect for device400.

The encapsulant408(e.g., epoxy molding compound) encapsulates the semiconductor die402, the semiconductor die404, and exposed portions of the top side of the package substrate406. The encapsulated semiconductor die402and semiconductor die404are separated from one another by a distance sufficient to provide desired isolation. In this embodiment, the semiconductor die402and the semiconductor die404are separated by a predetermined distance to accommodate desired requirements.

In this embodiment, a wireless communication link is formed between semiconductor die402and semiconductor die404by way of the inductive coils428-430and438-440embedded in the package substrate406. The communication link includes a signal path configured to allow wireless communication between the semiconductor die402and the semiconductor die404while being galvanically isolated from one another. For example, the signal path includes a first set of inductive coils428and438substantially aligned to form the first inductive coupling within the package substrate406and a second set of inductive coils430and440substantially aligned to form the second inductive coupling within the package substrate406. Conductive trace446interconnects inductive coils438and440thus forming a series connection of the first set of inductive coils with the second set of inductive coils coupled between the semiconductor die402and the semiconductor die404. The signal path further includes the conductive connector410and conductive trace418interconnecting the semiconductor die402with the inductive coil428and conductive connector416and conductive trace420interconnecting the semiconductor die404with the inductive coil430. In this embodiment, each of the conductive connectors410and416is formed as a copper pillar412with a solder plated tip414.

FIG. 5AthroughFIG. 5Cillustrate, in simplified plan views, example inductive coils in accordance with an embodiment. An inductive coil502is depicted inFIG. 5Awhich corresponds to the inductive coils130,228, and230, for example. The inductive coil502includes a spiral conductive trace504connected between terminals506and508. The spiral conductive trace504may be formed having any suitable shape or pattern such as a circular spiral, square spiral, octagonal spiral, and others. In this embodiment, the spiral conductive trace504and terminals506,508are formed from a same conductive layer (e.g., metal) of a laminate package substrate. In this embodiment, the terminals506and508include trace portions characterized as substrate pads having a shape and surface suitable for bond wire attachment. For example, the bond wire118interconnecting the semiconductor die104with the inductive coil130as depicted inFIG. 1may have a first end connected at the semiconductor die104and a second end connected at the terminal506. A second bond wire (not shown) interconnecting the semiconductor die104with a second terminal of the inductive coil130may have a first end connected at the semiconductor die104and a second end connected at the terminal508.

An inductive coil510is depicted inFIG. 5Bwhich corresponds to the inductive coils140,328-330, and428-430, for example. The inductive coil510includes a spiral conductive trace512connected between terminal514and trace portion516. The spiral conductive trace512may be formed having any suitable shape or pattern such as a circular spiral, square spiral, octagonal spiral, and others. In this embodiment, the spiral conductive trace512, the terminal514and trace portion516are formed from a same conductive layer (e.g., metal) of a laminate package substrate. In this embodiment, the terminal514may be configured for connection to different conductive layer of the laminate package substrate by way of a conductive via. For example, interconnecting the semiconductor die302with the inductive coil328as depicted inFIG. 3includes the bond wire316connected to a first portion of the conductive trace342with a second portion of the conductive trace342connected at the trace portion516. A second terminal of the inductive coil328(e.g., terminal514) may be interconnected to the semiconductor die302by way of a via connection to a different conductive layer of the laminate package substrate.

An inductive coil pair520is depicted inFIG. 5Cwhich corresponds to the inductive coil pairs238-240,338-340, and438-440ofFIG. 2throughFIG. 4, for example. The inductive coil pair520includes a first inductive coil formed as a spiral conductive trace522and a second inductive coil formed as a spiral conductive trace524connected by way of a conductive trace530. Terminals526and528are configured for connection to each other by way of conductive vias interconnected to a conductive trace532(illustrated as a dashed line) formed on a different conductive layer of the laminate package substrate, for example. Each of the spiral conductive traces522and524may be formed having any suitable shape or pattern such as a circular spiral, square spiral, octagonal spiral, and others. In this embodiment, the spiral conductive traces522,524and the terminals526,528are formed from a same conductive layer (e.g., metal) of the laminate package substrate.

When the first and second inductive coils (e.g., corresponding to inductive coils238and240ofFIG. 2) of the example inductive coil pair520are inductively coupled with respective third and fourth inductive coils (e.g., inductive coils228and230ofFIG. 2), a series wireless link or communication path may be formed. For example, in the embodiment depicted inFIG. 2, a wireless communication signal path is formed between semiconductor die202and semiconductor die204by way of the series arrangement of inductive coils228-230and238-240embedded in the package substrate206. The signal path includes a first inductive coupling formed by way of inductive coils228and238and a second inductive coupling formed by way of inductive coils230and240.

Generally, there is provided, a semiconductor device including a package substrate having a first major side and a second major side; a first semiconductor die attached to the first major side of the package substrate; a second semiconductor die attached to the first major side of the package substrate; a first inductive coil formed at the first major side of the package substrate, the first inductive coil conductively interconnected to the first semiconductor die; and a second inductive coil formed at the second major side of the package substrate and substantially aligned with the first inductive coil, a first wireless communication link between the first semiconductor die and the second semiconductor die formed by way of the first and second inductive coils. The first inductive coil may be formed from a first conductive layer of the package substrate and the second inductive coil may be formed from a second conductive layer proximate to the second major side of the package substrate, the first conductive layer and the second conductive layer separated by a non-conductive material. The first semiconductor die may be configured for operation in a first voltage domain and the second semiconductor die may be configured for operation in a second voltage domain, the first voltage domain having voltage values different from the second voltage domain. The first inductive coil may be located at the first major side of the package substrate such that the first semiconductor die overlaps at least a portion of the first inductive coil. The first inductive coil may be conductively interconnected to the first semiconductor die by way of a first bond wire. Any of the first semiconductor die and the second semiconductor die may be attached to the first major side of the package substrate in a flip-chip orientation. The semiconductor device may further include a third inductive coil formed at the first major side of the package substrate, the third inductive coil conductively interconnected to the second semiconductor die; and a fourth inductive coil formed at the second major side of the package substrate and substantially aligned with the third inductive coil, a second wireless communication link formed by way of the third and fourth inductive coils, the second wireless communication link connected in series with the first wireless communication link between the first semiconductor die and the second semiconductor die. The semiconductor device may further include ball connectors attached to the second major side of the package substrate, the ball connectors configured to connect the semiconductor device package to a printed circuit board (PCB). A first subset of the ball connectors conductively interconnected to the first semiconductor die may be separated from a second subset of the ball connectors conductively interconnected to the second semiconductor die by a first distance, the first distance characterized as a clearance distance configured for high voltage isolation.

In another embodiment, there is provided, a method of manufacturing a semiconductor device including providing package substrate including a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer, the first conductive layer and the second conductive layer separated by a non-conductive material; attaching a first semiconductor die to a first major side of the package substrate, the first semiconductor die conductively interconnected to the first inductive coil; attaching a second semiconductor die attached to the first major side of the package substrate; and forming a first wireless communication link between the first semiconductor die and the second semiconductor die including the first and second inductive coils. The first conductive layer may be formed at the first major side of the package substrate and the second conductive layer may be formed at a second major side of the package substrate. The method may further include attaching a bond wire to conductively interconnect the first semiconductor die with the first inductive coil. Attaching the first semiconductor die to the first major side of the package substrate may include attaching the first semiconductor die such that the first semiconductor die overlaps at least a portion of the first inductive coil. Any of the first semiconductor die and the second semiconductor die may be attached to the first major side of the package substrate in a flip-chip orientation. The method may further include forming a second wireless communication link including a third inductive coil and a fourth inductive coil, the second wireless communication link connected in series with the first wireless communication link between the first semiconductor die and the second semiconductor die.

In yet another embodiment, there is provided, a semiconductor device including a package substrate including a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer, the first conductive layer and the second conductive layer separated by a non-conductive material; a first semiconductor die attached to a first major side of the package substrate, the first semiconductor die conductively interconnected to the first inductive coil; a second semiconductor die attached to the first major side of the package substrate; and a first wireless communication link between the first semiconductor die and the second semiconductor die formed by way of the first and second inductive coils. The first semiconductor die may be configured for operation in a first voltage domain and the second semiconductor die may be configured for operation in a second voltage domain, the first voltage domain having voltage values different from the second voltage domain. The first inductive coil may be located at the first major side of the package substrate such that the first semiconductor die overlaps at least a portion of the first inductive coil. The first inductive coil may be conductively interconnected to the first semiconductor die by way of a bond wire. The semiconductor device may further include a third inductive coil formed from the first conductive layer, the third inductive coil conductively interconnected to the second semiconductor die; and a fourth inductive coil formed from the second conductive layer and substantially aligned with the third inductive coil, a second wireless communication link formed by way of the third and fourth inductive coils, the second wireless communication link connected in series with the first wireless communication link between the first semiconductor die and the second semiconductor die.

By now, it should be appreciated that there has been provided a semiconductor device package having galvanic isolation. The packaged semiconductor device includes a first semiconductor die and a second semiconductor die attached to a package substrate. The two semiconductor die are configured to communicate and/or transfer power with one another by way of inductive coils located in the package substrate. In this manner, the two semiconductor die are isolated from one another such that if an electrical over stress (EOS) event damaged the first semiconductor die, the second semiconductor die would remain electrically isolated from the first semiconductor die.