Semiconductor structure and fabrication method thereof

A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region adjacent to the first region; forming a first dielectric layer on the substrate in the first region and the second region; and forming a plurality of first plug structures in the first dielectric layer. The top surface of each first plug structure is exposed by the first dielectric layer. The method further includes forming a first conductive layer on the first dielectric layer of the second region; forming a second dielectric layer on the first dielectric layer of the first region and on the first conductive layer of the second region; and forming a plurality of second plug structures in the second dielectric layer of the first region. The bottom surface of each second plug structure is in contact with the top surface of a first plug structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Chinese Patent Application No. CN201911302205.4, filed on Dec. 17, 2019, the entire content of which is incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure generally relates to the field of semiconductor manufacturing and, more particularly, relates to semiconductor structures and fabrication methods thereof.

BACKGROUND

With the continuous development of the very-large-scale integration (VLSI) process technology, feature size of semiconductor devices continues to shrink, and the performance of semiconductor devices becomes more advanced. The integration of integrated circuit (IC) chips has reached hundreds of millions or even billions of devices on a single chip, and multi-layer interconnection has become widely used in IC chips.

Conventional interconnect structures are usually made of aluminum. As the size of semiconductor devices continuously decreases, interconnect structure becomes smaller and smaller, and accordingly, the current density passing through the interconnect structure becomes higher and higher. In addition, the response speed of interconnect structures also needs to be shorter. The existing aluminum interconnect structures are no longer meet the requirements. Therefore, copper has replaced aluminum as the material of interconnect structures. Compared with aluminum, copper has a lower resistivity and more desirable electromigration resistance. Therefore, interconnect structure made of copper can reduce the resistance capacitance (RC) delay of the interconnect structure, and improve device reliability. As such, replacing aluminum with copper has become a development trend.

However, the production cost of an interconnection structure formed by existing method is high. There is an urgent need to provide an interconnection structure and a fabrication method to reduce the production cost while ensuring the electrical performance of the interconnection structure. The disclosed semiconductor structures and fabrication methods are directed to solve one or more problems set forth above and other problems in the art.

BRIEF SUMMARY OF THE DISCLOSURE

One aspect of the present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate, including a first region and a second region adjacent to the first region; forming a first dielectric layer on the substrate in the first region and the second region; and forming a plurality of first plug structures in the first dielectric layer. The top surface of each first plug structure of the plurality of first plug structures is exposed by the first dielectric layer. The method further includes forming a first conductive layer on the first dielectric layer of the second region; forming a second dielectric layer on the first dielectric layer of the first region and on the first conductive layer of the second region; and forming a plurality of second plug structures in the second dielectric layer of the first region. The bottom surface of each second plug structure of the plurality of second plug structures is in contact with the top surface of a first plug structure.

Optionally, the method further includes forming a gate conductive layer and a plurality of source/drain conductive layers in the first dielectric layer. The plurality of first plug structures is located on the gate conductive layer, the plurality of source/drain conductive layers, or both the gate conductive layer and the plurality of source/drain conductive layers.

Optionally, the method further includes forming a first pull-up gate structure, a first pull-down gate structure, and a first transmission gate structure in the first dielectric layer; forming a first source region and a first drain region in the substrate respectively on the two sides of the first pull-up gate structure; forming a second source region and a second drain region in the substrate respectively on two sides of the first pull-down gate structure; and forming a third source region and a third drain region in the substrate respectively on two sides of the first transmission gate structure. The gate conductive layer is located on a top surface of the first transmission gate structure, and the power conductive layer is electrically connected to the first drain region through a first plug structure and a source/drain conductive layer.

Optionally, forming the first dielectric layer and the plurality of first plug structures includes forming an initial first dielectric layer on the substrate in the first region and the second region; and forming a first mask layer on the initial first dielectric layer. A plurality of first openings is formed in the first mask layer to expose a portion of the initial first dielectric layer. Forming the first dielectric layer and the plurality of first plug structures further includes etching the initial first dielectric layer using the first mask layer as an etch mask to form the first dielectric layer, the first dielectric layer including a plurality of first dielectric openings; and forming the plurality of first plug structures in the plurality of first dielectric openings.

Optionally, when forming the plurality of second plug structures, the method further includes forming a third plug structure in the second dielectric layer of the second region. The bottom surface of the third plug structure is in contact with the top surface of the first conductive layer.

Optionally, forming the second dielectric layer, the plurality of second plug structures, and the third plug structure includes forming an initial second dielectric layer on the first dielectric layer of the first region and on the first conductive layer of the second region; forming a second mask layer, including a plurality of second openings and a third opening that expose the initial second dielectric layer; etching the initial second dielectric layer using the second mask layer as an etch mask until exposing top surfaces of the plurality of first plug structures and a top surface of the first conductive layer to form the second dielectric layer, a plurality of second dielectric openings and a third dielectric opening being formed in the second dielectric layer with positions corresponding positions of the plurality of second openings and the third opening, respectively; and forming the plurality of second plug structures in the plurality of second dielectric openings and forming the third plug structure in the third dielectric opening.

Optionally, etching the initial second dielectric layer includes a dry etching process, a wet etching process, or a combination thereof.

Optionally, the width of each second dielectric opening of the plurality of second dielectric openings is in a range of approximately 10 nm to 100 nm.

Optionally, after forming the second dielectric layer, the method further includes forming a second conductive layer on the second dielectric layer. The second conductive layer is located in the first region and the second region; and the top surface of the plurality of second plug structures and the top surface of the third plug structure are electrically connected to the bottom surface of the second conductive layer, respectively.

Optionally, the substrate is made of germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), or indium arsenic (InAs).

Optionally, the plurality of source/drain conductive layers and the gate conductive layer are made of a metal, including copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), titanium (Ti), titanium nitride (TiNx), tantalum (Ta), tantalum nitride (TaNx), ruthenium (Ru), or a combination thereof.

Optionally, the plurality of first plug structures is made of a metal, including copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), titanium (Ti), titanium nitride (TiNx), tantalum (Ta), tantalum nitride (TaNx), ruthenium (Ru), or a combination thereof.

Optionally, the first dielectric layer is made of silicon oxide (SiOx), a low-K dielectric material, or an ultra-low-K dielectric material.

Optionally, the second dielectric layer is made of silicon oxide (SiOx), a low-K dielectric material, or an ultra-low-K dielectric material.

Optionally, the plurality of second plug structures is made of a metal, including ruthenium (Ru), copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), tantalum (Ta), tantalum nitride (TaNx), titanium (Ti), titanium nitride (TiNx), silver (Ag), platinum (Pt), or a combination thereof.

Optionally, the third plug structure is made of a metal, including ruthenium (Ru), copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), tantalum (Ta), tantalum nitride (TaNx), titanium (Ti), titanium nitride (TiNx), silver (Ag), platinum (Pt), or a combination thereof.

Another aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, including a first region and a second region adjacent to the first region; a first dielectric layer, formed on the substrate in the first region and the second region; and a plurality of first plug structures, formed in the first dielectric layer. The top surface of each first plug structure of the plurality of first plug structures is exposed by the first dielectric layer. The semiconductor structure further includes a first conductive layer, formed on the first dielectric layer of the second region; a second dielectric layer, formed on the first dielectric layer of the first region and on the first conductive layer of second region; and a plurality of second plug structures, formed in the second dielectric layer of the first region. The bottom surface of each second plug structure of the plurality of second plug structures is in contact with the top surface of a first plug structure.

Optionally, the semiconductor structure further includes a third plug structure, formed in the second dielectric layer of the second region. The bottom surface of the third plug structure is in contact with the top surface of the first conductive layer.

Optionally, the semiconductor structure further includes a gate conductive layer and a plurality of source/drain conductive layers, formed in the first dielectric layer. The plurality of first plug structures is located on the gate conductive layer, the plurality of source/drain conductive layers, or both the gate conductive layer and the plurality of source/drain conductive layers.

Compared to existing semiconductor structures and fabrication methods, the disclosed semiconductor structures and fabrication methods may demonstrate the following exemplary advantages.

According to the disclosed methods, in the first region, the bottom surface of the second plug structure is directly in contact with the top surface of the first plug structure. By directly connecting the first plug structure and the second plug structure, the step of forming the word-line conductive layer WL and the power conductive layer Vss is saved. As such, while satisfying the requirements of the electrical structure, the production efficiency can be effectively improved and the production cost can also be reduced.

Further, according to the disclosed fabrication methods and semiconductor structures, the width of the second dielectric opening is in a range of approximately 10 nm to 100 nm. Because the process of forming the word-line conductive layer WL and the power conductive layer Vss is saved in the disclosed method, the second plug structure is formed directly in contact with a corresponding first plug structure. Therefore, the length of the second plug structure needs to be increased accordingly. As such, during the fabrication process, the depth of the corresponding second dielectric opening also needs to be increased. However, because the second dielectric opening formed by an etching process is generally in an inverted cone shape, in order to ensure that the bottom of the formed second dielectric opening can expose the top surface of the first plug structure, the width at the top of the second dielectric opening needs to be increased accordingly.

DETAILED DESCRIPTION

FIGS.1-2illustrate schematic cross-sectional views of structures at certain stages of a fabrication process of a semiconductor structure.

Referring toFIG.1, a substrate100is provided. The substrate100includes a first region I and a second region II that are adjacent to each other. A first dielectric layer101is formed on the substrate100. The first dielectric layer101is located on both the first region I and the second region II. A plurality of first plug structures102is formed in the first dielectric layer101, and the first dielectric layer101exposes the top surface of each first plug structure102. For illustrative purposes, only one first plug structure102is shown inFIG.1.

Referring toFIG.2, a first conductive layer103and a second conductive layer104are formed on the first dielectric layer101. The first conductive layer103is located in the first region I, and includes a word-line conductive layer WL and a power conductive layer Vss (not shown). The bottom surface of the first conductive layer103is in contact with the top surface of the first plug structure102. The second conductive layer104is located in the second region II, and includes a bit-line conductive layer BL and a power conductive layer Vcc. A second dielectric layer105is formed on the first conductive layer103and the second conductive layer104. The second dielectric layer105is located in both the first region I and the second region II. A second plug structure106and a third plug structure107are formed in the second dielectric layer105. The second plug structure106is located in the first region I and the third plug structure107is located in the second region II. The bottom surface of the second plug structure106is in contact with the top surface of the first conductive layer103, and the bottom surface of the third plug structure107is in contact with the top surface of the second conductive layer104.

According to the semiconductor structure and fabrication method described above, by sequentially connecting the first plug structure102, the first conductive layer103, and the second plug structure106, the requirements of electrical design are realized. However, as a transition layer, the word-line conductive layer WL and the power conductive layer Vss will increase the process steps. In addition, in electrical design, it is also necessary to ensure electrical separation between the word-line conductive layer WL and the power conductive layer Vss. Therefore, a metal cutting process is required to separate the two layers, and thus besides the increase in the fabrication steps, the manufacturing cost may also increase.

The present disclosure provides a semiconductor structure and a fabrication method. By directly connecting the first plug structure and the second plug structure, the step of forming the word-line conductive layer WL and the power conductive layer Vss is saved. As such, while satisfying the requirements of the electrical structure, the production efficiency can be effectively improved and the production cost can also be reduced.

To make the aforementioned objectives, features, and beneficial effects of the present disclosure more comprehensible, specific embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

The present disclosure provides a method for forming a semiconductor structure.FIG.12illustrates a flowchart of an exemplary method for forming a semiconductor structure according to some embodiments of the present disclosure, andFIGS.3-11illustrate schematic cross-sectional views of structures at certain stages of the exemplary method.

Referring toFIG.12, a substrate including a first region and a second region may be provided (S701).FIGS.3-4illustrate schematic views of a semiconductor structure consistent with various embodiments of the present disclosure. Specifically,FIG.4illustrates a schematic cross-sectional view of the semiconductor structure shown inFIG.3along an A-A1direction.

Referring toFIGS.3-4, a substrate200may be provided, and the substrate200may include a first region I and a second region II that are adjacent to each other. In one embodiment, the substrate200may be made of silicon. In other embodiments, the substrate200may be made of germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), indium arsenic (InAs), or any other appropriate semiconductor material or composite.

Further, returning toFIG.12, a first pull-up transistor including a first pull-up fin structure, a first pull-up gate structure covering a portion of the top and sidewall surfaces of the first pull-up fin structure, and a first source region and a first drain region formed in the substrate respectively on the two sides of the first pull-up gate structure; a first pull-down transistor including a first pull-down fin structure, a first pull-down gate structure covering a portion of the top and sidewall surfaces of the first pull-down fin structure, and a second source region and a second drain region formed in the substrate respectively on the two sides of the first pull-down gate structure; a first transmission transistor including a first transmission fin structure, a first transmission gate structure covering a portion of the top and sidewall surfaces of the first transmission fin structure, and a third source region and a third drain region formed in the substrate respectively on the two sides of the first transmission gate structure; and an isolation layer covering a portion of the sidewall surfaces of the first pull-up fin structure, the first pull-down fin structure, and the first transmission fin structure may be formed (S702). The exemplary semiconductor structure shown inFIGS.3-4includes a first pull-up transistor, a first pull-down transistor, and a first transmission transistor.

Referring toFIGS.3-4, a first pull-up fin structure (not labeled), a first pull-down fin structure (not labeled), and a first transmission fin structure (not labeled) may be formed on the substrate200. Also, an isolation layer220may be formed on the substrate200. The top surface of the isolation layer220may be lower than the top surfaces of the first pull-up fin structure, the first pull-down fin structure, and the first transmission fin structure. Thus, the isolation layer220may cover a portion of the sidewall surfaces of the first pull-up fin structure, the first pull-down fin structure, and the first transmission fin structure. A first pull-up gate structure201, a first pull-down gate structure202, and a first transmission gate structure203may be formed on the substrate200. The first pull-up gate structure201may cover a portion of the top and sidewall surfaces of the first pull-up fin structure, the first pull-down gate structure202may cover a portion of the top and sidewall surfaces of the first pull-down fin structure, and the first transmission gate structure203may cover a portion of the top and sidewall surfaces of the first transmission fin structure. A first source region204and a first drain region205may be formed in the substrate200on the two sides of the first pull-up gate structure201, respectively; a second source region206and a second drain region207may be formed in the substrate200on the two sides of the first pull-down gate structure202, respectively; and a third source region208and a third drain region209may be formed in the substrate200on the two sides of the first transmission gate structure203, respectively.

In one embodiment, the first pull-up gate structure201, the first pull-down gate structure202, and the first transmission gate structure203may be formed on the isolation layer220. For example, a first pull-up transistor PU1may be formed by the first pull-up gate structure201, the first pull-up fin structure, the first source region204, and the first drain region205; a first pull-down transistor PD1may be formed by the first pull-down gate structure202, the first pull-down fin structure, the second source region206, and the second drain region207; and a first transmission transistor PG1may be formed by the first transmission gate structure203, the first transmission fin structure, the third source region208, and the third drain region209.

Further, returning toFIG.12, a second pull-up transistor, a second pull-down transistor, and a second transmission transistor may be formed, and the second pull-up transistor, the second pull-down transistor, and the second transmission transistor may be in rotational symmetry with the first pull-up transistor, the first pull-down transistor, and the first transmission transistor (S703). The exemplary semiconductor structure shown inFIGS.3-4includes a second pull-up transistor, a second pull-down transistor, and a second transmission transistor.

Referring toFIGS.3-4, a second pull-up transistor PU2, a second pull-down transistor PD2, and a second transmission transistor PG2may be formed, and the second pull-up transistor PU2, the second pull-down transistor PD2, and the second transmission transistor PG2may be in rotational symmetry with the first pull-up transistor PU1the first pull-down transistor PD1, and the first transmission transistor PG1. In one embodiment, the first pull-up transistor PU1the first pull-down transistor PD1, the first transmission transistor PG1, the second pull-up transistor PU2, the second pull-down transistor PD2, and the second transmission transistor PG2may together form a smallest storage unit of a static memory.

Further, returning toFIG.12, a first dielectric layer including a first region and a second region may be formed on the substrate, a plurality of first plug structures may be formed in the first dielectric layer, and the top surface of each first plug structure may be exposed by the first dielectric layer (S704).FIGS.5-6illustrate schematic views of an exemplary semiconductor structure consistent with various embodiments of the present disclosure. Specifically,FIG.6illustrates a schematic cross-sectional view of the semiconductor structure shown inFIG.5along a B-B1direction. It should be noted that for illustrative purposes, the isolation layer and the first dielectric layer are not shown inFIG.6.

Referring toFIGS.5-6, a first dielectric layer210may be formed on the substrate200. The first dielectric layer210may be located in both the first region I and the second region II. A plurality of first plug structures211may be formed in the first dielectric layer210, and the top surface of each first plug structure211may be exposed by the first dielectric layer210. In one embodiment, the first dielectric layer210may be formed on the isolation layer220.

The process of forming the first dielectric layer210and the plurality of first plug structures211may include the following exemplary steps. An initial first dielectric layer (not shown) may be formed on the substrate200in both the first region I and the second region II. A first mask layer (not shown) may be formed on the initial first dielectric layer. A plurality of first openings (not shown) may be formed in the first mask layer to expose a portion of the first initial first dielectric layer. Further, the initial first dielectric layer may be etched using the first mask layer as an etch mask to form the first dielectric layer210. Corresponding to the position of each first opening, a first dielectric opening may be formed in the first dielectric layer210. Then, a first plug structure211may be formed in the first dielectric opening.

In one embodiment, the first dielectric layer may be made of silicon oxide. In other embodiments, the first dielectric layer may be made of a low-K dielectric material (a material having a relative dielectric constant below 3.9) or an ultra-low-K dielectric material (a material having a relative dielectric constant below 2.5).

The plurality of first plug structures211may be made of a metal, and the metal may include copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), titanium (Ti), titanium nitride (TiNx), tantalum (Ta), tantalum nitride (TaNx), ruthenium (Ru), or a combination thereof. In one embodiment, the plurality of first plug structures211may be made of tungsten (W).

In one embodiment, referring toFIGS.5-6, prior to forming the plurality of first plug structures211, the method may further include forming a gate conductive layer212and a plurality of source/drain conductive layers221in the first dielectric layer210. The gate conductive layer212may be located on the top surface of the first transmission gate structure203, and the plurality of source/drain conductive layers may respectively located on the top surfaces of the first drain region205, the second drain region207, and the third source region208.

The plurality of source/drain conductive layers221and the gate conductive layer212may be made of a metal, and the metal may include copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), titanium (Ti), titanium nitride (TiNx), tantalum (Ta), tantalum nitride (TaNx), ruthenium (Ru), or a combination thereof. In one embodiment, the gate conductive layer212may be made of titanium nitride (TiNx), and the plurality of source/drain conductive layers221may be made of (TiNx).

In one embodiment, the plurality of first plug structures211may be formed on the plurality of source/drain conductive layers221and on the gate conductive layer212. In other embodiments, the plurality of first plug structures may be formed only on the gate conductive layer212, or only on the plurality of source/drain conductive layers221.

Further, returning toFIG.12, a first conducive layer may be formed on the portion of the first dielectric layer that is located in the second region (S705).FIGS.7-8illustrate schematic views of an exemplary semiconductor structure consistent with various embodiments of the present disclosure. Specifically,FIG.8illustrates a schematic cross-sectional view of the semiconductor structure shown inFIG.7along a C-C1direction.

Referring toFIGS.7-8, a first conductive layer214may be formed in the second region II to cover the portion of the first dielectric layer210formed in the second region II.

The first conductive layer214may include a bit-line conductive layer BL and a power conductive layer Vcc. The bit-line conductive layer BL may be electrically connected to the third source region208through a first plug structure211and a source/drain conductive layer221. The power conductive layer Vcc may be electrically connected to the first drain region205through a first plug structure211and a source/drain conductive layer221.

Further, returning toFIG.12, a second dielectric layer may be formed on the first conductive layer and also on the first dielectric layer of the first region, and a second dielectric opening exposing the top surface of each first plug structure and a third dielectric layer exposing the power conductive layer may be formed in the second dielectric layer (S706).FIG.9illustrates a schematic cross-sectional view of a semiconductor structure consistent with various embodiments of the present disclosure. It should be noted that the direction of the cross-sectional view shown inFIG.9is consistent with the direction of the cross-sectional view shown inFIG.8.

Referring toFIG.9, after forming the first conductive layer214in the second region II, a second dielectric layer215may be formed on the first conductive layer214. The second dielectric layer215may also cover the portion of the first dielectric layer210formed in the first region I. Corresponding to each first plug structure211, a second dielectric opening218may be formed in the second dielectric layer215to expose the top surface of the first plug structure211, and corresponding to the power conductive layer Vcc, a third dielectric opening219may be formed in the second dielectric layer215to expose the top surface of the power conductive layer Vcc.

The process of forming the second dielectric layer215may include the following exemplary steps. An initial second dielectric layer (not shown) may be formed on the first dielectric layer210of the first region I and also on the first conductive layer214. A second mask layer (not shown) may be formed on the initial second dielectric layer. A plurality of second openings (not shown) and a third opening (not shown) may be formed in the second mask layer to expose a portion of the initial second dielectric layer. The positions of the plurality of second openings may correspond to the locations of the plurality of first plug structures211, and the position of the third opening may correspond to the location of the power conductive layer Vcc. Further, the second initial dielectric layer may be etched using the second mask layer as an etch mask to expose the top surface of each first plug structure211and the top surface of the first conductive layer214. As such, the second dielectric layer214including a plurality of second dielectric openings218and a third dielectric opening219may be formed. The plurality of second dielectric openings218may be located in the first region I, and the third dielectric opening219may be located in the second region II.

The second dielectric layer215may be made of silicon oxide. Alternatively, the second dielectric layer215may be made of a low-K dielectric material (a material having a relative dielectric constant below 3.9) or an ultra-low-K dielectric material (a material having a relative dielectric constant below 2.5).

When the second dielectric layer215is made of a low-K dielectric material or an ultra-low-K dielectric material, the material of the second dielectric layer215may be SiOH, SiCOH, fluorosilicate glass (FSG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), hydrogenated silsesquioxane (HSQ, (HSiO1.5)n), or methylsilsesquioxane (MSQ, (CH3SiO1.5)n). In one embodiment, the second dielectric layer215may be made of SiCOH.

The initial second dielectric layer may be etched by a dry etching process, a wet etching process, or a process combining dry etching and wet etching. In one embodiment, the initial second dielectric layer may be etched by a dry etching process. The processing gas used in the dry etching process may include an etching gas and a carrier gas. The etching gas may include CF4, CHF3, CH2F2, CH3F, or a combination thereof, and the carrier gas may be an inert gas. The flow rate of the etching gas may be in a range of approximately 50 sccm to 100 sccm, and the flow rate of the carrier gas may be in a range of approximately 100 sccm to 1000 sccm.

Because the process of forming the word-line conductive layer WL and the power conductive layer Vss is saved in the disclosed method, during the subsequent fabrication process, after forming a second plug structure in each second dielectric opening218, the second plug structure may be directly in contact with a corresponding first plug structure211. Therefore, the length of the second plug structure may be increased accordingly. As such, during the fabrication process, the depth of the corresponding second dielectric opening218may also need to be increased. However, because the second dielectric opening218formed by an etching process is generally in an inverted cone shape, in order to ensure that the bottom of the formed second dielectric opening218can expose the top surface of the first plug structure211, the width at the top of the second dielectric opening218may need to be increased accordingly. In one embodiment, the width of the second dielectric opening218may be in a range of approximately 10 nm to 100 nm.

Further, returning toFIG.12, a second plug structure may be formed in each second dielectric opening that is located in the first region, and the bottom surface of the second plug structure may be in contact with the top surface of the corresponding first plug structure; a third plug structure may be formed in the third dielectric opening that is located in the second region, and the bottom surface of the third plug structure may be in contact with the top surface of the first conductive layer (S707).FIG.10illustrates a schematic cross-sectional view of a semiconductor structure consistent with various embodiments of the present disclosure.

Referring toFIG.10, a second plug structure216may be formed in the second dielectric layer215to fill each second dielectric opening218(referring toFIG.9). The second plug structure216may be located in the first region I, and the bottom surface of the second plug structure216may be in contact with the top surface of the corresponding first plug structure211. When forming the second plug structure216, a third plug structure217may be simultaneously formed in the second dielectric layer215to fill the third dielectric opening219(referring toFIG.9). The third plug structure217may be located in the second region II, and the bottom surface of the third plug structure217may be in contact with the top surface of the first conductive layer214.

The process of forming the second plug structure216and the third plug structure217may include the following exemplary steps. An initial second plug structure (not shown) may be formed in the second dielectric opening218(referring toFIG.9) and an initial third plug structure (not shown) may be formed in the third dielectric opening219(referring toFIG.9). The initial second plug structure and the initial third plug structure may be planarized until the top surface of the second dielectric layer215is exposed. As such, the second plug structure216and the third plug structure217may be formed. In one embodiment, the initial second plug structure and the initial third plug structure may be planarized by a chemical mechanical polishing (CMP) process.

According to the disclosed method, by directly connecting the first plug structure211and the second plug structure216, the step for forming the word-line conductive layer WL and the power conductive layer Vss may be saved. As such, while satisfying the requirements of the electrical structure, the production efficiency can be effectively improved and the production cost can also be reduced.

The second plug structure216may be made of a metal, including ruthenium (Ru), copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), tantalum (Ta), tantalum nitride (TaNx), titanium (Ti), titanium nitride (TiNx), silver (Ag), platinum (Pt), or a combination thereof. In one embodiment, the second plug structure216may be made of tungsten (W).

The third plug structure217may be made of a metal, including ruthenium (Ru), copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), tantalum (Ta), tantalum nitride (TaNx), titanium (Ti), titanium nitride (TiNx), silver (Ag), platinum (Pt), or a combination thereof. In one embodiment, the third plug structure217may be made of tungsten (W).

Further, returning toFIG.12, after forming the second plug structure and the third plug structure, a second conductive layer may be formed on the second dielectric layer in both the first region and the second region; and the top surface of the second plug structure and the top surface of the third plug structure may be electrically connected to the bottom surface of the second conductive layer, respectively (S708).FIG.11illustrates a schematic cross-sectional view of a semiconductor structure consistent with various embodiments of the present disclosure.

Referring toFIG.11, after forming the second plug structure216and the third plug structure217, a second conductive layer213may be formed on the second dielectric layer215. The second conductive layer213may be located in both the first region I and the second region II, and the top surfaces of the second plug structure216and the third plug structure217may be electrically connected to the bottom surface of the second conductive layer213, respectively.

The second conductive layer213may be made of a metal, including ruthenium (Ru), copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), tantalum (Ta), tantalum nitride (TaNx), titanium (Ti), titanium nitride (TiNx), silver (Ag), platinum (Pt), or a combination thereof. In one embodiment, the second conductive layer213may be made of copper (Cu).

Correspondingly, the present disclosure also provides a semiconductor structure formed by a method according to various embodiments of the present disclosure.FIG.10illustrates a schematic cross-sectional view of an exemplary semiconductor structure according to various embodiments of the present disclosure.

Referring toFIG.10, the semiconductor structure may include a substrate200, including a first region I and a second region II that are adjacent to each other; a first dielectric layer210, disposed on the substrate200in both the first region I and the second region II; and a plurality of first plug structures211formed in the first dielectric layer210. The portion of the first dielectric layer210formed in the first region I may expose the top surface of each first plug structure211. The semiconductor structure also includes a first conductive layer214, formed on the portion of the first dielectric layer210that is located in the first region I; and a second dielectric layer215. In the first region I, the second dielectric layer215may be formed on the first dielectric layer210, and in the second region II, the second dielectric layer215may be formed on the first conductive layer214. The semiconductor structure may further include a plurality of second plug structures216formed in the first region I. Each second plug structure216may be formed vertically through the second dielectric layer215, and the bottom surface of the second plug structure216may be in contact with the top surface of the corresponding first plug structure211.

Compared to existing semiconductor structures and fabrication methods, the disclosed semiconductor structures and fabrication methods may demonstrate the following exemplary advantages.

According to the disclosed methods, in the first region, the bottom surface of the second plug structure is directly in contact with the top surface of the first plug structure. By directly connecting the first plug structure and the second plug structure, the step of forming the word-line conductive layer WL and the power conductive layer Vss is saved. As such, while satisfying the requirements of the electrical structure, the production efficiency can be effectively improved and the production cost can also be reduced.

Further, according to the disclosed fabrication methods and semiconductor structures, the width of the second dielectric opening is in a range of approximately 10 nm to 100 nm. Because the process of forming the word-line conductive layer WL and the power conductive layer Vss is saved in the disclosed method, the second plug structure is formed directly in contact with a corresponding first plug structure. Therefore, the length of the second plug structure needs to be increased accordingly. As such, during the fabrication process, the depth of the corresponding second dielectric opening also needs to be increased. However, because the second dielectric opening formed by an etching process is generally in an inverted cone shape, in order to ensure that the bottom of the formed second dielectric opening can expose the top surface of the first plug structure, the width at the top of the second dielectric opening needs to be increased accordingly.