A semiconductor device includes: a plurality of external terminals; a plurality of semiconductor substrates that are layered; a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the external terminals; and a plurality of electrostatic discharge protection circuits provided on any one of the semiconductor substrates. In the device, the through electrode is electrically connected with the plurality of electrostatic discharge protection circuits.

The entire disclosure of Japanese Patent Application No. 2008-306228, filed Dec. 1, 2008 is expressly incorporated by reference herein.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

2. Related Art

As an electronic apparatus is downsized, a mounting space for an electronic component such as a semiconductor device which is mounted inside the electronic apparatus is decreased. Therefore, electronic components such as a semiconductor device are required to be further limited.

As a method for downsizing a semiconductor device, a method in which a semiconductor device is structured by layering semiconductor substrates (semiconductor chips) is proposed. In this method, semiconductor chips having the same functions as each other or semiconductor chips having different functions from each other are layered and wiring-connected with each other so as to achieve high density mounting of the semiconductor chips.

As a method for wiring-connecting the semiconductor chips, a method in which a through electrode (wiring electrode penetrating through the semiconductor chips) is provided on the semiconductor chips so as to wiring-connect the semiconductor chips is proposed.

In a case where the through electrode is electrically connected with an external terminal of the semiconductor device, a circuit element on the semiconductor chips may be damaged by static electricity inputted through the external terminal. Therefore, it is common to provide an electrostatic discharge (ESD) protection circuit which serves as a discharge path for electric charge inputted by static electricity.

However, an element used in the electrostatic discharge protection circuit (for example, a transistor or a diode) is difficult to be downsized and is usually larger than other circuit elements. Therefore, the electrostatic discharge protection circuit may degrade area efficiency of the semiconductor chips and degrade latitude of layout design (arrangement and wiring design) of the semiconductor chips.

SUMMARY

The present invention is devised in view of the above technical problems. An advantage of the present invention is to provide a semiconductor device in which area efficiency and latitude of layout design are improved and to provide a method for manufacturing such a semiconductor device.

A semiconductor device according to a first aspect of the invention includes: a plurality of external terminals; a plurality of semiconductor substrates that are layered; a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the external terminals; and a plurality of electrostatic discharge protection circuits provided on any one of the semiconductor substrates. In the device, the through electrode is electrically connected with the plurality of electrostatic discharge protection circuits.

According to the first aspect, the electrostatic discharge protection circuits can be integrated on any one of the semiconductor substrates. Accordingly, the electrostatic discharge protection circuits are not required to be formed on the rest of the semiconductor substrates, so that area efficiency is improved and latitude of arrangement and wiring of the circuit element is improved.

In the semiconductor device of the first aspect, the through electrode may be formed in a plural manner, and the plurality of electrostatic discharge protection circuits may be electrically connected with any of the plurality of through electrodes.

In the semiconductor device of the first aspect, the semiconductor substrate on which the plurality of electrostatic discharge protection circuits are provided may be one of a semiconductor substrate that is a lowermost layer and a semiconductor substrate that is an uppermost layer.

In the semiconductor device of the first aspect, the semiconductor substrate on which the plurality of electrostatic discharge protection circuits are provided may be manufactured by a larger design rule than that for the rest of the semiconductor substrates.

In the semiconductor device of the first aspect, a simple electrostatic discharge protection circuit electrically connected with at least one of the through electrodes and having a lower electrostatic discharge protection function than the electrostatic discharge protection circuits may be provided on at least one of the semiconductor substrates except for the semiconductor substrate on which the plurality of electrostatic discharge protection circuits are provided.

According to a second aspect of the invention, a method for manufacturing a semiconductor device including a plurality of external terminals and a plurality of semiconductor substrates that are layered, includes: providing a plurality of electrostatic discharge protection circuits on any one of the semiconductor substrates; providing a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the plurality of external terminals and any of the plurality of electrostatic discharge protection circuits of the semiconductor device; and electrically connecting the plurality of electrostatic discharge protection circuits and the through electrode.

DESCRIPTION OF EXEMPLARY EMBODIMENT

An embodiment according to the invention will be described below with reference to the accompanying drawings. However, it should be noted that the invention is not limited to the following embodiment. The present invention includes any combination of contents of the following description.

FIG. 1is a schematic view for explaining an internal structure of a semiconductor device according to the embodiment of the invention. The semiconductor device according to the embodiment includes external terminals VDD, VSS, Pin1, and Pin2as well as elements shown inFIG. 1.

This semiconductor device1according to the embodiment includes a plurality of semiconductor substrates.FIG. 1shows a structure in which semiconductor substrates10,20, and30are layered.

The semiconductor substrate10includes a semiconductor layer11and a wiring layer12. The semiconductor layer11is a layer on which a circuit element such as a transistor is formed and is made of a semiconductor containing Si, for example. The wiring layer12is a layer on which a wiring for electrically connecting the circuit element, which is formed on the semiconductor layer11, and a through electrode (details are described later) is formed. The wiring is made of a metal such as Al and Cu.

In a similar manner, the semiconductor substrate20includes a semiconductor layer21and a wiring layer22, and the semiconductor substrate30includes a semiconductor layer31and a wiring layer32.

The semiconductor substrate10includes an internal circuit13in the semiconductor layer11thereof. The semiconductor substrate20includes an internal circuit23in the semiconductor layer21thereof.

The semiconductor substrate30includes electrostatic discharge protection circuits41,42, and43in the semiconductor layer31thereof. The electrostatic discharge protection circuits41,42, and43serve as a discharge path for an electric charge inputted from an external terminal (not shown) by static electricity, and are formed for protecting the internal circuits13and23from damage by electrostatic discharge.

The semiconductor device according to the embodiment includes through electrodes51,52,53, and54. The through electrodes51,52,53and54penetrate through at least one of the semiconductor substrates10,20, and30and are electrically connected with respective external terminals which are not shown.

The through electrode51penetrates through the semiconductor substrates20and30and is electrically connected with an external terminal VDD. The through electrode52penetrates through the semiconductor substrates20and30and is electrically connected with an external terminal VSS. The through electrode53penetrates through the semiconductor substrates20and30and is electrically connected with an external terminal Pin1. The through electrode54penetrates through the semiconductor substrate30and is electrically connected with an external terminal Pin2.

The through electrodes may be formed after the semiconductor substrates are layered. As shown inFIG. 2showing an example of a structure of a through electrode, the through electrodes may be structured such that through electrodes50a,50b, and50care individually formed on respective substrates, and are electrically connected with each other by layering the substrates.

Here, the wiring layer12of the semiconductor substrate10and the semiconductor layer21of the semiconductor substrate20may be bonded to each other with an adhesive81. Further, the wiring layer22of the semiconductor substrate20and the semiconductor layer31of the semiconductor substrate30may be bonded to each other with an adhesive82.

FIG. 3is a circuit diagram of the semiconductor device according to the embodiment. The external terminal VDD serves as a power source terminal coupled to a positive potential, and the external terminal VSS serves as a ground terminal coupled to a ground potential. The external terminal Pin1serves as an input terminal or an output terminal of the internal circuit13, and the external terminal Pin2serves as an input terminal or an output terminal of the internal circuit23.

The through electrode51electrically connected with the external terminal VDD is electrically connected with the internal circuit13through the wiring layer12, is electrically connected with the internal circuit23through the wiring layer22, and is electrically connected with the electrostatic discharge protection circuit41through the wiring layer32.

The through electrode52electrically connected with the external terminal VSS is electrically connected with the internal circuit13through the wiring layer12, is electrically connected with the internal circuit23through the wiring layer22, and is electrically connected with the electrostatic discharge protection circuits41,42, and43through the wiring layer32.

The through electrode53electrically connected with the external terminal Pin1is electrically connected with the internal circuit13through the wiring layer12and is electrically connected with the electrostatic discharge protection circuit42through the wiring layer32.

The through electrode54electrically connected with the external terminal Pin2is electrically connected with the internal circuit23through the wiring layer22and is electrically connected with the electrostatic discharge protection circuit43through the wiring layer32.

FIGS. 4A and 4Bare schematic views for explaining an example of an electrostatic discharge protection circuit of the embodiment. This electrostatic discharge protection circuit shown inFIGS. 4A and 4Bis composed of a grounded-gate negative-channel metal oxide semiconductor (ggNMOS).FIG. 4Ais a plan view of the ggNMOS, andFIG. 4Bis a sectional view showing a section of the ggNMOS taken along an a-a′ line ofFIG. 4A.

In the ggNMOS shown inFIGS. 4A and 4B, N-diffusion regions103and104to be source regions and an N-diffusion region105to be a drain region are formed in a region surrounded by a P-diffusion region102in a P-Well101.

A silicon oxide film is formed to stride between the N-diffusion region103and the N-diffusion region105, and a poly-silicon layer106is formed on the silicon oxide film. Further, a silicon oxide film is formed to stride between the N-diffusion region104and the N-diffusion region105, and a poly-silicon layer107is formed on the silicon oxide film.

According to the semiconductor device of the embodiment, the electrostatic discharge protection circuits can be integrated on any one of the semiconductor substrates. Accordingly, the electrostatic discharge protection circuits are not required to be formed on the rest of the semiconductor substrates, so that area efficiency is improved and latitude of arrangement and wiring of the circuit element is improved.

Further, the semiconductor substrate on which a plurality of electrostatic discharge protection circuits are provided may be manufactured by a larger design rule than that for the rest of the semiconductor substrates. The semiconductor substrate on which the electrostatic discharge protection circuits are integrated is manufactured in an inexpensive manufacturing process using a large design rule, being able to reduce a cost for manufacturing a semiconductor device.

FIGS. 5A and 5Bare schematic views for explaining a sectional structure of the semiconductor device of the embodiment.FIG. 5Ashows an example of a structure in which a structural body obtained by layering the semiconductor substrates10,20, and30described with reference toFIG. 1is disposed with its front surface facing an upside and the structural body is molded with a molding resin61, on a package substrate60.FIG. 5Bshows an example of a structure in which a structural body obtained by layering the semiconductor substrates10,20, and30described with reference toFIG. 1is disposed with its front surface facing a downside and the structural body is molded with the molding resin61, on the package substrate60.

In the example shown inFIG. 5A, the package substrate60is provided with the external terminals VDD, VSS, Pin1, and Pin2. The through electrodes51,52,53, and54are electrically connected with the external terminals VDD, VSS, Pin1, and Pin2respectively, through wirings and bonding wires inside the package substrate60.

In such the structure, an electrical path from the external terminals through the through electrodes to the internal circuits passes through the semiconductor substrate30which is the uppermost layer. Therefore, the electrostatic discharge protection circuits are provided on the semiconductor substrate30which is the uppermost layer. Thus, the electrostatic discharge protection circuits can be integrated on one semiconductor substrate.

In the example shown inFIG. 5B, a package substrate60is provided with the external terminals VDD, VSS, Pin1, and Pin2. The through electrodes51,52,53, and54are electrically connected with the external terminals VDD, VSS, Pin1, and Pin2respectively, through wirings inside the package substrate60.

In such the structure, an electrical path from the external terminals through the through electrodes to the internal circuits passes through the semiconductor substrate30which is the lowermost layer. Therefore, the electrostatic discharge protection circuits are provided on the semiconductor substrate30which is the lowermost layer. Thus, the electrostatic discharge protection circuits can be integrated on one semiconductor substrate.

MODIFICATION

In addition to the structure of the semiconductor device described in the above embodiment, a simple electrostatic discharge protection circuit may be provided on at least one semiconductor substrate on which the electrostatic discharge protection circuits are not provided. The simple electrostatic discharge protection circuit is electrically connected with at least one through electrode and has a lower electrostatic discharge protection function than the electrostatic discharge protection circuit.

FIG. 6is a schematic view for explaining an internal structure of a semiconductor device according to a modification.FIG. 6shows a case where a simple electrostatic discharge protection circuit is provided on the semiconductor substrate10.

FIG. 7is a circuit diagram of the semiconductor substrate10in a case where a simple electrostatic discharge protection circuit is provided on the semiconductor substrate10.

A simple electrostatic discharge protection circuit71is electrically connected with the through electrode51, which is electrically connected with the external terminal VDD, and the through electrode52, which is electrically connected with the external terminal VSS, through the wiring layer12.

A simple electrostatic discharge protection circuit72is electrically connected with the through electrode52, which is electrically connected with the external terminal VSS, and the through electrode53, which is electrically connected with the external terminal Pin1, through the wiring layer12.

A simple electrostatic discharge protection circuit73is electrically connected with the through electrode51, which is electrically connected with the external terminal VDD, and the through electrode53, which is electrically connected with the external terminal Pin1, through the wiring layer12.

FIGS. 4C and 4Dare schematic views for explaining an example of a simple electrostatic discharge protection circuit of the modification. This simple electrostatic discharge protection circuit shown inFIGS. 4C and 4Dis composed of a diode.FIG. 4Cis a plan view of the diode, andFIG. 4Dis a sectional view showing a section of the diode taken along at a b-b′ line ofFIG. 4C.

In the diode shown inFIGS. 4C and 4D, a P-diffusion region202to be an anode and an N-diffusion region203to be a cathode, which is in a region surrounded by the P-diffusion region202, are formed in a P-Well201.

In regard to the simple electrostatic discharge protection circuit71, the P-diffusion region202is electrically connected with the external terminal VSS through the through electrode52and the N-diffusion region203is electrically connected with the external terminal VDD through the through electrode51. In regard to the simple electrostatic discharge protection circuit72, the P-diffusion region202is electrically connected with the external terminal VSS through the through electrode52and the N-diffusion region203is electrically connected with the external terminal Pin1through the through electrode53.

In regard to the simple electrostatic discharge protection circuit73, the N-diffusion region203is electrically connected with the external terminal VDD through the through electrode51and the P-diffusion region202is electrically connected with the external terminal Pin1through the through electrode53.

The simple electrostatic discharge protection circuit structured as this may have a lower electrostatic discharge protection function than the electrostatic discharge protection circuit shown inFIGS. 4C and 4D. It is only necessary for the simple electrostatic discharge protection circuits71,72, and73to prevent damage by electrostatic discharge in a manufacturing step and a testing step of the semiconductor substrates10and20, because the electrostatic discharge protection circuits41,42, and43provided on the semiconductor substrate30mainly work after the semiconductor device is completed.

Accordingly, the simple electrostatic discharge protection circuits71,72, and73can be formed to have smaller areas than the electrostatic discharge protection circuits41,42, and43. Therefore, compared to a case where electrostatic discharge protection circuits are provided on all semiconductor substrates, area efficiency is improved and latitude of arrangement and wiring of circuit elements is improved.

Here, it should be noted that the present invention is not limited to the above embodiment but is applicable to various kinds of modifications within the scope and the spirit of the present invention.

The present invention may include substantially the same structures as those described in the above embodiment (for example, the same functions, manners, and results, or the same advantages and advantageous effects as those in the above embodiment). In addition, the present invention includes structures obtained by replacing a nonessential part of the structures described in the embodiment. Further, the invention includes structures offering the same advantageous effects or structures achieving the same objects as those of the structure described in the embodiment. Furthermore, the present invention includes structures obtained by adding related art to the structures described in the embodiment.

For example, the embodiment shows the example including the external terminals VDD, VSS, Pin1, and Pin2, but other external terminals such as an input terminal, an output terminal, a control terminal, and the like may be included.