Circuit arrangement for suppressing CRT beam in television receiver

For the periodic suppression of the beam of a cathode-ray tube in a television receiver during flyback, in response to a blanking pulse V.sub.2 normally accompanied by a flyback pulse V.sub.1 of shorter duration, a control transistor T.sub.11 is saturated to render conductive a master transistor T.sub.7 in series therewith, together with several slave transistors T.sub.6, T.sub.8 and T.sub.13 forming current mirrors with transistor T.sub.7. Slave transistor T.sub.13 lies in series with a Zener diode DZ across which the beam-suppressing signal V.sub.3 is generated; slave transistor T.sub.6 activates a comparator CMP having an input A connected to a biasing circuit PL1 including slave transistor T.sub.8. Another input B of the comparator receives from a voltage divider PL2 a biasing voltage of such magnitude that an output C of the comparator feeds back a holding signal to another control transistor T.sub.12, in parallel with transistor T.sub.11, to maintain the conduction of master transistor T.sub.7 until a flyback pulse V.sub.1 applied to biasing circuit PL1 reverses the comparator whereby the beam-suppressing signal V.sub.3 disappears with the blanking pulse V.sub.2. In the absence of flyback pulse V.sub.1, signal V.sub.3 persists for an indefinite period.

FIELD OF THE INVENTION 
My present invention relates to a circuit arrangement for the suppression 
of the beam of a cathode-ray tube in a televisions receiver during flyback 
as well as in the event of a malfunction. 
BACKGROUND OF THE INVENTION 
Conventional sweep circuits used for horizontal and vertical scanning in 
television receivers periodically emit a blanking pulse, derived from the 
sawtooth voltage of a respective ramp generator, in order to suppress the 
beam during its return stroke. 
If, for any reason, the vertical-sweep generator fails to operate properly 
so that the beam oscillates along a single horizontal line of the CRT 
screen, the sensitive layer of that screen may be irreparably damaged 
unless the beam is promptly extinguished. It has therefore already been 
proposed to provide protective circuitry for suppressing the beam whenever 
a flyback pulse, normally developed across the vertical-deflection yoke of 
the CRT within the blanking period, fails to materialize. Such a system 
generally comprises a storage capacitor chargeable by a guard circuit in 
response to the flyback pulse; in the discharged state of the capacitor, 
the blanking pulse is extended into a continuous d-c voltage whereby the 
beam is permanently cut off. See, for example, Technical Note 078 by N. V. 
Philips'Gloeilampenfabrieken (1978) relating to the integrated 
vertical-deflection module known as TDA2652. 
The storage capacitor used with such a prior-art guard circuit must be 
fairly large, with a capacitance of at least one microfarad. Such 
capacitors cannot be incorporated in an integrated-circuit module and are 
therefore designed as separate circuit components connected to the i-c 
chip via an external terminal. 
OBJECTS OF THE INVENTION 
The general object of my present invention, therefore, is to provide a 
circuit arrangement of the type referred to which obviates the need for a 
separate capacitor designed to store the flyback pulse. 
A related object is to provide a more compact unit of this description 
which is realizable entirely by integrated circuitry. 
SUMMARY OF THE INVENTION 
In accordance with my present invention I provide a normally deactivated 
comparator with a first signal input for receiving a switching signal from 
a first biasing circuit and a second signal input for receiving a 
reference signal from a second biasing circuit. A control circuit with an 
output connection extending to an activating input of the comparator 
receives the blanking pulse from the sweep circuit via an input connection 
and a holding signal from the comparator via a feedback connection 
whenever that comparator is activated in response to such a blanking pulse 
to assume a first operational state; the holding signal then maintains 
that operational state independently of the blanking pulse. This first 
biasing circuit is coupled to switchover means such as a shunt transistor 
connected to receive the flyback pulse and, in response to that pulse, 
modifies the switching signal emitted by it to establish a second 
operational state of the comparator with concurrent disablement of the 
feedback connection to the control circuit. Thus, the disappearance of the 
blanking pulse (whose duration exceeds that of the accompanying flyback 
pulse) restores the control circuit to normal and deactivates the 
comparator. If the flyback pulse fails to arrive, the comparator remains 
active and continues to enable an associated output circit which generates 
a beam-suppressing signal in both the first and the second operational 
state thereof. 
According to a more specific feature of my invention, the output connection 
of the control circuit includes a master transistor and several slave or 
follower transistors which are interconnected in a current-mirror 
configuration, one such slave transistor being connected to the activating 
input of the comparator for energizing same upon conduction of the 
associated master transistor. Another slave transistor so associated may 
form part of the first biasing circuit and of the output circuit which 
generates the beam-suppressing signal.

SPECIFIC DESCRIPTION 
In FIG. 1 I have shown a conventional beam suppressor, such as the 
above-mentioned guard circuit of the TDA2652 modlule, receiving a 
recurrent blanking pulse V.sub.b1 of negativve polarity from a generator 
G.sub.b1 and an accompanying flyback pulse V.sub.fb of positive polarity, 
of shorter duration, form another generator G.sub.fb. The flyback pulse 
V.sub.fb is applied to the base of a PNP transistor T.sub.1 connected in 
cascade with two similar transistors T.sub.2 and T.sub.3 ; all three 
transistors have their collector/emitter paths connected in parallel, 
through respective series resistors, across a source of d-c voltage +V. An 
R/C network in the input of transistor T.sub.1 includes a storage 
capacitor CP which is charged by recurrent flyback pulses V.sub.fb so as 
to saturate the transistor T.sub.1 whereby transistor T.sub.2 is cut off 
and transistor T.sub.3 conducts, except in the presence of a blanking 
pulse V.sub.b1 applied to its base to override the voltage +V on the 
collector of transistor T.sub.2 whereby a positive beam-suppressing pulse 
V.sub.3 appears on the collector of transistor T.sub.3. Generator G.sub.b1 
is driven by a nonillustrated sawtooth oscillator included in the 
vertical-sweep circuit associated with the cathode-ray tube of a 
television receiver whose beam is to be cut off during flyback and in the 
event of a malfunction of that sweep circuit, as discussed above. 
Generator G.sub.fb may comprise a small capacitor connected across the 
vertical-deflection yoke of that cathode-ray tube, as in the 
aforedescribed TDA2652 module. Capacitor CP, as noted above, constitutes 
an extraneous component of the guard circuit represented by transistors 
T.sub.1 -T.sub.3. 
In FIG. 2 I have shown a pair of generators G.sub.1 and G.sub.2 which are 
similar to components G.sub.b1 and G.sub.fb of FIG. 1 but produce a 
flyback pulse V.sub.1 and a blanking pulse V.sub.2 both of positive 
polarity. These two pulses have also been illustrated in the timing 
diagrams of FIGS. 4a and 4b which indicate that the blanking pulse V.sub.2 
lasts for a longer period t.sub.1 -t.sub.4 than the accompanying flyback 
pulse V.sub.1 occurring between times t.sub.2 and t.sub.3 ; the two pulse 
widths may be 1.2 msec. and 0.5 msec., respectively. The illustrated 
offset t.sub.1 -t.sub.2 between the leading edges of pulses V.sub.2 and 
V.sub.1 is not essential for the operation of the system but will 
generally occur in practice. 
The integrated circuitry shown in FIG. 2, serving to derive 
beam-suppressing signals from flyback and blanking pulses V.sub.1 and 
V.sub.2, may be conceptually subdivided into five components also 
illustrated in block form in FIG. 3, namely a comparator CMP, first and 
second biasing circuits PL1, PL2, a control circuit COM and an output 
circuit or final stage SF, all inserted between ground and a positive 
supply terminal +V. Components COM and PL1 share common circuit elements 
and have therefore not been separately indicated in FIG. 2. p Comparator 
CMP has two signal inputs A and B represented by the bases of respective 
PNP transistors T.sub.4 and T.sub.5 whose emitters are connected in 
parallel to the collector of a similar transistor T.sub.6 and whose 
collectors are grounded via respective series resistors R.sub.1 and 
R.sub.2. PNP transistor T.sub.6 is one of four such transistors with 
emitters joined to supply terminal +V and with bases interconnected by a 
lead Y in a current-mirror configuration; the remaining transistors of 
this configuration have been designated T.sub.7, T.sub.8 and T.sub.13, 
with transistor T.sub.7 acting as the master and the others serving as 
followers. The collector of master transistor T.sub.7, tied to lead Y, is 
connected by way of a voltage divider R.sub.4, R.sub.8 to the emitters of 
two NPN transistors T.sub.11, T.sub.12 inserted in parallel between that 
voltage divider and ground, these latter transistors forming part of 
control circuit COM. A shunt transistor T.sub.9, also of NPN type, has its 
collector tied to the junction of resistors R.sub.4, R.sub.8 and its 
emitter grounded. Transistor T.sub.9, whose base receives the flyback 
pulse V.sub.1 from generator G.sub.1, conducts only in the presenc of that 
pulse to switch over the comparator CMP from a first to a second 
operational state as described hereinafter. 
Slave transistor T.sub.8 has its collector connected to the base of 
transistor T.sub.4 at comparator input A from which a biasing resistor 
R.sub.3 extends to ground. The opposite input B, i.e. the base of 
transistor T.sub.5, is connected to the junction of two series resistors 
R.sub.5 and R.sub.6 forming with a further series resistor R.sub.7 a 
voltage divider inserted between terminal +V and ground. This voltage 
divider is part of biasing circuit PL2, as is an NPN transistor T.sub.10 
which constitutes an electronic bypass switch connected across resistor 
R.sub.7. The collectors of the two symmetrical comparator transistors 
T.sub.4 and T.sub.5 are respectively joined to the base of transistor 
T.sub.12 via a lead C and to the base of transistor T.sub.10 via a lead D; 
lead C constitutes a feedback connection delivering a holding signal to 
control circuit COM as will also be described hereinafter. 
Slave transistor T.sub.13 is part of output circuit SF and has its 
collector grounded through a resistor R.sub.9 in parallel with a Zener 
diode DZ. The output terminal 0 of the system, producing the 
beam-suppressing signal, lies at the junction of the collector of 
transistor T.sub.13 with impedance network R.sub.9, DZ. 
Normally, i.e. in the absence of pulses V.sub.1 and V.sub.2, transistors 
T.sub.11, T.sub.12 of control circuit COM are cut off whereby master 
transistor T.sub.7 and the associated slave transistors T.sub.6, T.sub.8 
and T.sub.13 are likewise nonconducting. The potential of comparator input 
A, shown at V.sub.A in FIG. 4a, is then at ground level and well below the 
magnitude of the reference signal V.sub.B applied to the other input B by 
biasing circuit PL2. Neither of transistors T.sub.4 and T.sub.5 conducts 
at this stage, however, in view of the cutoff of transistor T.sub.6. Shunt 
transistor T.sub.9 and bypass transistor T.sub.10 are also nonconducting; 
the voltage of output terminal 0 is likewise at ground level as seen at 
V.sub.o in FIG. 4a. 
At instant t.sub.1, the appearance of a blanking pulse V.sub.2 turns on the 
control transistor T.sub.11 whereby the base connection Y in the output of 
circuit COM is driven more negative and causes the current-mirroring 
transistors T.sub.6, T.sub.7, T.sub.8 and T.sub.13 to conduct. The 
potential of input A now rises to a level V.sub.A' which is still less 
than the reference voltage V.sub.B of terminal B. This establishes the 
first operational state of comparator CMP in which transistor T.sub.4 
conducts and supplies a holding voltage via feedback connection C to 
control transistor T.sub.12, saturating it in parallel with the already 
saturated transistor T.sub.11. Current passing through transistor T.sub.13 
generates across output resistor R.sub.9 a voltage drop exceeding the 
threshold of Zener diode DZ whereby the latter breaks down and gives rise 
to a positive beam-suppressing pulse V.sub.3 represented in FIG. 4a by a 
rise of the potential of terminal 0 to a level Vz. 
The appearance of a flyback pulse V.sub.1 at instant t.sub.2 saturates the 
shunt transistor T.sub.9 and short-circuits the resistor R.sub.8 so as to 
increase the conductivity of transistors T.sub.6, T.sub.7, T.sub.8 and 
T.sub.13. The higher biasing current now traversing the resistor R.sub.3 
raises the potential of point A to a level V.sub.A " exceeding that of 
point B. This cuts off the PNP transistor T.sub.4 and cuts in its 
companion transistor T.sub.5, thereby de-energizing the feedback 
connection C and saturating the bypass transistor T.sub.10 so as to lower 
the reference voltage at point B to a level V.sub.B ' well below the level 
V.sub.A ' which marks the first operational state of comparator CMP. In 
this second operational state of the comparator, control transistor 
T.sub.12 is cut off although transistor T.sub.11 remains saturated until 
blanking pulse V.sub.2 disappears. 
At instant t.sub.3, the termination of flyback pulse V.sub.1 effectively 
reinserts the resistor R.sub.8 in the collector lead of master transistor 
T.sub.7, thereby raising once more the potential of lead Y so that the 
switching voltage at point A is again lowered to its previous level 
V.sub.A '. Since, however, point B is still more negative than point A, 
the state of comparator CMP does not change until instant t.sub.4 when the 
trailing edge of blanking pulse V.sub.2 restores the original condition of 
the system. 
If flyback pulse V.sub.1 had not arrived in the interval t.sub.1 -t.sub.4, 
comparator CMP would have remained in its first operational state with 
voltages of points A and B at their respective levels V.sub.A ' and 
V.sub.B, as shown in FIG. 4b. The output signal on terminal 0 would 
therefore have remained at its high level V.sub.z instead of returning to 
ground potential V.sub.o as in FIG. 4a, thereby continuing the suppression 
of the beam of the associated cathode-ray tube. 
Whereas in FIG. 2 the comparator CMP is shown to have two separate output 
leads C and D respectively extending to control circuit COM and biasing 
circuit PL2, it will be apparent that these two leads could be replaced by 
a single output connection with two branches, one of them including an 
inverter INV, as illustrated in FIG. 3. 
Although my improved beam suppressor is primarily intended for the 
vertical-deflection circuit of a television receiver, it will be 
understood that an analogous arrangement can be provided for the 
horizontal sweep.