On a p− epitaxial layer, an n-type epitaxial layer and a gate region are formed in this order. A gate electrode is electrically connected to the gate region, and a source electrode and a drain electrode are spaced apart from each other with the gate electrode sandwiched therebetween. A control electrode is used for applying to the p− epitaxial layer a voltage that causes a reverse biased state of the p− epitaxial layer and the n-type epitaxial layer in an OFF operation.

TECHNICAL FIELD

The present invention relates to a lateral junction field-effect transistor, and more particularly to a structure of a lateral junction field-effect transistor in which a leakage current in an OFF operation can be reduced.

BACKGROUND ART

A junction field-effect transistor (hereinafter referred to as JFET) has a pn junction provided on either side of a channel region where carriers flow through, and a reverse bias voltage is applied from a gate electrode to expand a depletion layer from the pn junction into the channel region, thereby controlling the conductance of the channel region to perform an operation such as switching. A lateral JFET which is one type of the JFET refers to the one in which carriers move in the channel region in parallel with the surface of the device.

The carriers in the channel may be electrons (n-type) or holes (p-type). Usually, most JFETs in which SiC is used for the semiconductor substrate include the channel region that is an n-type impurity region. Therefore, for convenience of the description below, it is supposed that carriers in the channel are electrons and thus the channel region is an n-type impurity region; however, it should be understood that the channel region is a p-type impurity region in some cases.

An example of such a lateral JFET is disclosed for example in Japanese Patent Laying-Open No. 2003-68762.

FIG. 14is a schematic cross section showing a structure of a conventional lateral JFET disclosed in the above-referenced publication. Referring toFIG. 14, a p−epitaxial layer103is provided on an SiC single crystal substrate101. On this p−epitaxial layer103, an n-type epitaxial layer104having a higher impurity concentration than p−epitaxial layer103is provided. On this n-type epitaxial layer104, a p-type epitaxial layer109is provided.

On respective surfaces of p+gate region105, n+source region106and n+drain region107, a gate electrode112a, a source electrode112band a drain electrode112care provided respectively. On a lateral side of n+source region106, a p+semiconductor layer108that reaches to p−epitaxial layer103is formed, and source electrode112bis electrically connected to p+semiconductor layer108.

In this lateral JFET, p+gate region105has its impurity concentration higher than that of n-type epitaxial layer104. Thus, in the lateral JFET, a depletion layer is expanded toward the channel by applying a reverse bias voltage to the pn junction between p+gate region105and n-type epitaxial layer104. In the state where the depletion layer closes the channel, the current cannot flow through the channel to cause an OFF state. Therefore, the magnitude of the reverse bias voltage can be adjusted to control whether to allow the depletion layer to block the channel region or not. As a result, the reverse bias voltage between the gate and the source for example can be adjusted to control the ON and OFF states of the current.

DISCLOSURE OF THE INVENTION

Problems to be Solved by the Invention

The above-described lateral JFET, however, has the problem that a leakage current flowing in p−epitaxial layer103under the channel is generated.

The present invention has been made in view of the above-described problem, and an object of the invention is to provide a lateral junction field-effect transistor in which generation of a leakage current in an OFF operation can be prevented.

Means for Solving the Problems

A lateral junction field-effect transistor of the present invention includes a withstand voltage keeping region of a first conductivity type, a channel region of a second conductivity type, a gate region of the first conductivity type, a gate electrode, a source electrode and a drain electrode, and a control electrode. The channel region is formed on the withstand voltage keeping region. The gate region is formed on the channel region. The gate electrode is electrically connected to the gate region. The source electrode and the drain electrode are spaced apart from each other with the gate electrode sandwiched between the source electrode and the drain electrode, and are electrically connected to the channel region. The control electrode is used for applying to the withstand voltage keeping region a voltage causing the withstand voltage keeping region and the channel region to be in a reverse biased state in an OFF operation.

In the lateral junction field-effect transistor of the present invention, the control electrode is used to apply a voltage that causes a reverse biased state of the withstand voltage keeping region and the channel region in an OFF state. Accordingly, in the OFF operation, the potential of the withstand voltage keeping region becomes higher than the potential of the channel region so that the potential barrier between the channel region and the withstand voltage keeping region becomes higher. Therefore, it is difficult for carriers in the channel region to climb over the potential barrier and reach the withstand voltage keeping region, and thus generation of a leakage current between the channel region and the withstand voltage keeping region can be prevented. In this way, the withstand voltage can be improved.

Preferably, regarding the above-described lateral junction field-effect transistor, a potential identical to a potential applied to the gate electrode is applied to the control electrode.

In the case where the same potential as the potential applied to the gate electrode is applied to the control electrode, the potential of the withstand voltage keeping region is also higher than the potential of the channel region. Therefore, likewise, generation of a leakage current between the channel region and the withstand voltage keeping region can be prevented and the withstand voltage can be improved.

Further, the same potential as the potential applied to the gate electrode can be applied to the withstand voltage keeping region to allow the withstand voltage keeping region to operate as a gate. Therefore, the mutual conductance represented by a variation of the drain current with respect to a variation of the gate voltage can be increased.

Preferably, regarding the above-described lateral junction field-effect transistor, the control electrode is electrically insulated from the source electrode.

The control electrode is electrically insulated from the source electrode as described above so that a voltage can be applied using the control electrode to cause a reverse biased state of the withstand voltage keeping region and the channel region in an OFF state.

Preferably, the above-described lateral junction field-effect transistor further includes an electric field alleviation region of the first conductivity type formed on the channel region and at a lateral side of the gate region and having an impurity concentration lower than an impurity concentration of the gate electrode.

Accordingly, the channel region of the second conductivity type is sandwiched between the withstand voltage keeping region of the first conductivity type and the electric field alleviation region of the first conductivity type, and thus a double RESURF (Reduced Surface Field) structure can be implemented. Therefore, dielectric breakdown due to electric field concentration can be prevented and the withstand voltage characteristic of the device can be improved.

Preferably, the above-described lateral junction field-effect transistor further includes a source region of the second conductivity type formed on the channel region, electrically connected to the source electrode and having an impurity concentration higher than an impurity concentration of the channel region, and a drain region of the second conductivity type formed on the channel region, electrically connected to the drain electrode and having an impurity concentration higher than the impurity concentration of the channel region.

Since the source region and the drain region higher in impurity concentration than the channel region are provided, the connection resistance when the source electrode and the drain electrode are electrically connected to the channel region can be reduced.

Effects of the Invention

As seen from the description above, in the lateral junction field-effect transistor of the present invention, generation of a leakage current can be prevented and the withstand voltage can be improved.

DESCRIPTION OF THE REFERENCE SIGNS

BEST MODES FOR CARRYING OUT THE INVENTION

First Embodiment

FIG. 1is a cross section schematically showing a structure of a lateral junction field-effect transistor in a first embodiment of the present invention. Referring toFIG. 1, a single crystal substrate1that is of any conductivity type and made for example of 4H—SiC (silicon carbide) is used as a semiconductor substrate. On substrate1, a p-type epitaxial layer2and a p−epitaxial layer (withstand voltage keeping region)3are formed in layers stacked in this order. P-type epitaxial layer2includes Al (aluminum) as a p-type impurity with a concentration for example of 5.0×1016cm−3and has a thickness for example of 0.5 μm. P−epitaxial layer3includes Al as a p-type impurity with a concentration for example of 1.0×1016cm−3and has a thickness for example of 10 μm.

On p−epitaxial layer3, an n-type epitaxial layer (channel region)4is formed. N-type epitaxial layer4includes N (nitrogen) as an n-type impurity with a concentration for example of 2.0×1017cm−3and has a thickness for example of 0.4 μm.

On n-type epitaxial layer4, a p-type epitaxial layer (electric field alleviation region)9is formed. P-type epitaxial layer9includes Al as a p-type impurity with a concentration for example of 2.0×1017cm−3and has a thickness for example of 0.2 μm.

On n-type epitaxial layer4and in p-type epitaxial layer9, a p+gate region5is formed with its bottom surface extending into n-type epitaxial layer4(namely the depth of diffusion is deeper than p-type epitaxial layer9). P+gate region5has an impurity concentration higher than p-type epitaxial layer9and n-type epitaxial layer4. An n+source region6and an n+drain region7are formed with a predetermined distance therebetween so that p+gate region5is sandwiched between the source region and the drain region. N+source region6and n+drain region7are each formed on n-type epitaxial layer4and in p-type epitaxial layer9and have a higher impurity concentration than n-type epitaxial layer4.

At a lateral side of n+source region6, a trench (a depressed portion) that reaches to n-type epitaxial layer4is formed. A p+impurity region8is formed to reach from the bottom surface of the trench to p−epitaxial layer3. P+impurity region8has an impurity region higher than p−epitaxial layer3.

A field oxide film13is formed to cover a surface where a transistor is to be formed. In field oxide film13, openings are provided to open a part of p+gate region5, n+source region6, n+drain region7and p+impurity region8each. In respective openings, ohmic electrodes11a,11b,11c,11dmade for example of Ni (nickel) are formed in order to make an ohmic contact. A gate electrode12a, a source electrode12b, a drain electrode12c, and a control electrode12dare formed so that these electrodes are electrically connected to p+gate electrode5, n+source electrode6, n+drain electrode7and p+impurity region8respectively via these ohmic electrodes11a,11b,11c, and11d.

These gate electrode12a, source electrode12b, drain electrode12c, and control electrode12dare each made for example of Al (aluminum). Source electrode12band drain electrode12care spaced apart from each other with gate electrode12asandwiched therebetween.

Gate electrode12ais structured so that a gate voltage VGcan be applied thereto, source electrode12bis structured to be at a ground potential, and drain electrode12cis structured so that a drain voltage VDcan be applied thereto. Control electrode12dis structured to be electrically insulated from source electrode12band is structured so that a voltage VBcan be applied thereto. Namely, control electrode12dis structured so that voltage VBcan be applied to p−epitaxial layer3to cause a reverse biased state of p−epitaxial layer3and n-type epitaxial layer4in an OFF operation.

Next, a method of manufacturing the lateral junction field-effect transistor in the present embodiment will be described.

FIGS. 2 to 8are schematic cross sections showing the method of manufacturing the lateral junction field-effect transistor in the first embodiment of the present invention, the method being shown in the order of steps. Referring toFIG. 2, on single crystal substrate1made for example of 4H—SiC, p-type epitaxial layer2, p−epitaxial layer (withstand voltage keeping region)3, n-type epitaxial layer (channel region)4, and p-type epitaxial layer (electric field alleviation region)9are formed in layers stacked in this order through epitaxial growth.

Referring toFIG. 3, since it is necessary to form a plurality of transistors on a single substrate, a trench (depressed portion) for physically isolating transistors from each other is formed. The trench is formed by performing RIE (Reactive Ion Etching) using, as a mask, an anti-etching film (not shown) formed on p-type epitaxial layer9. In this way, a trench extending through p-type epitaxial layer9to reach to n-type epitaxial layer4is selectively formed.

Referring toFIG. 4, a patterned ion block film31is formed on the surface of the substrate. Ion block film31is used as a mask to selectively implant Al ions for example to the bottom surface of the trench and a predetermined region of p-type epitaxial layer9. Accordingly, ion-implanted regions5,8are formed. Ion block film31is thereafter removed.

Referring toFIG. 5, a patterned ion block film32is formed on the surface of the substrate. Ion block film32is used as a mask to selectively implant P (phosphorus) ions for example to predetermined regions of p-type epitaxial layer9between which ion-implanted region5is sandwiched. Accordingly, ion-implanted regions6,7are formed. Ion block film32is thereafter removed.

Referring toFIG. 6, in order to activate the impurities supplied by the ion implantation and to recover from any crystal damage caused by the ion implantation, heat treatment (anneal) is performed in an Ar (argon) atmosphere for example. Accordingly, p+gate region5and p+impurity region8are formed from ion-implanted regions5and8respectively, and n+source region6and n+drain region7are formed from ion-implanted regions6and7respectively.

Referring toFIG. 7, a thermal oxidation method is used to form field oxide film13on the substrate surface for protecting and electrically insulating the substrate surface.

Referring toFIG. 8, predetermined regions of field oxide film13are opened to expose a part of p+gate region5, n+source region6, n+drain region7, and p+impurity region8each. After this, Ni is vapor-deposited to form ohmic electrodes11a,11b,11c,11dmade of Ni on respective surfaces of the exposed regions.

Referring toFIG. 1, Al is vapor-deposited on the whole surface of the substrate, and thereafter the Al is patterned by etching, so that gate electrode12a, source electrode12b, drain electrode12c, and control electrode12dmade for example of Al are formed. Electrodes12ato12deach can also function as an interconnection or pad.

In this way, the lateral junction field-effect transistor in the present embodiment as shown inFIG. 1can be manufactured.

In the lateral junction field-effect transistor in the present embodiment, a leakage current in an OFF operation can be reduced as compared with the conventional example, as described in the following.

FIG. 9is a diagram showing an energy band of a portion along a line IX-IX inFIG. 1. In the case where no voltage is applied to each of the gate region and the withstand voltage keeping region, the energy band is in the state as indicated byFIG. 9(a) in both of the conventional example and the present embodiment. In this diagram of the band, electrons are represented by solid black circular marks.

In this state, gate voltage VGis applied to the gate region. Accordingly, as indicated byFIG. 9(b), the potential barrier between p+gate region5and n-type epitaxial layer (channel region)4becomes higher. In the conventional example, p−epitaxial layer (withstand voltage keeping region)103and n-type epitaxial layer (channel region)104are set at a source potential (ground potential) and thus respective potentials are identical to each other. Therefore, when a high electric field is applied, the potential of p−epitaxial layer (withstand voltage keeping region)103relative to the source side (namely n-type channel region104side) significantly decreases, so that a leakage current undesirably flows.

In contrast, in the present embodiment, p−epitaxial layer (withstand voltage keeping region)3is electrically insulated from n-type epitaxial layer (channel region)4, and voltage VBcan be applied that causes a reverse biased state of p−epitaxial layer (withstand voltage keeping region)3and n-type epitaxial layer (channel region)4. When this voltage VBis applied, as indicated byFIG. 9(c), the potential barrier between n-type epitaxial layer (channel region)4and p−epitaxial layer (withstand voltage keeping region)3becomes higher. Therefore, it is difficult for carriers (electrons) in n-type epitaxial layer (channel region)4to climb over the potential barrier and reach p−epitaxial layer (withstand voltage keeping region)3. For this reason, occurrence of the leakage current between n-type epitaxial layer (channel region)4and p−epitaxial layer (withstand voltage keeping region)3can be prevented as compared with the conventional example, and the withstand voltage can be improved.

Second Embodiment

FIG. 10is a cross section schematically showing a structure of a lateral junction field-effect transistor in a second embodiment of the present invention. Referring toFIG. 10, the lateral junction field-effect transistor in the present embodiment differs from the structure of the first embodiment shown inFIG. 1in that the former is configured to allow a gate potential VGto be applied to control electrode12d. Therefore, control electrode12dmay be electrically connected to gate electrode12a.

Components of the lateral junction field-effect transistor in the present embodiment other than the above-described one are substantially identical to those of the above-described structure of the first embodiment. Therefore, like components are denoted by like reference characters and the description thereof will not be repeated. Further, a manufacturing method in the present embodiment is also substantially identical to the manufacturing method in the first embodiment. Therefore, the description thereof will not be repeated.

In the present embodiment, like the first embodiment, the leakage current can be reduced in an OFF operation as compared with the conventional example, as described in the following.

FIG. 11is a diagram showing an energy band along a line XI-XI inFIG. 10in an OFF operation. Referring toFIG. 11, gate voltage VGis applied to control electrode12d. The application of gate voltage VGcauses p−epitaxial layer3and n-type epitaxial layer4to become a reverse biased state. Therefore, the potential barrier between n-type epitaxial layer (channel region)4and p−epitaxial layer (withstand voltage keeping region)3becomes higher. Accordingly, it is difficult for carriers (electrons) in n-type epitaxial layer (channel region)4to climb over the potential barrier and reach p−epitaxial layer (withstand voltage keeping region)3. Thus, even if a high electric field is applied, occurrence of the leakage current between n-type epitaxial layer (channel region)4and p−epitaxial layer (withstand voltage keeping region)3can be prevented as compared with the conventional example, and the withstand voltage can be improved.

Further, the same potential as gate voltage VGmay be applied to p−epitaxial layer (withstand voltage keeping region)3so that p−epitaxial layer (withstand voltage keeping region)3functions as a gate. Thus, the mutual conductance represented by a variation of the drain current relative to a variation of the gate voltage can be increased.

In the above-described first and second embodiments, n-type epitaxial layer4is sandwiched between p−epitaxial layer3and n-type epitaxial layer9. Thus, a double RESURF structure can be implemented. Accordingly, electric field concentration around gate electrode12ais alleviated. Thus, dielectric breakdown due to the field concentration can be prevented and the withstand voltage characteristic of the device is improved.

The present invention, however, is not limited to the double RESURF structure, and may be the one without p-type epitaxial layer (electric field alleviation region)9as shown inFIG. 12.

Further, the embodiments are described above regarding the substrate made of 4H—SiC. The present invention, however, is not limited to this and the material for the substrate may be Si (silicon), 6H—SiC, 3C—SiC, GaN (potassium nitride) or the like.

Further, in the case where passivation film20is formed as shown inFIG. 13, passivation film20covers the substrate surface and includes openings for exposing gate electrode12a, source electrode12b, drain electrode12cand control electrode12d, respectively.

It should be construed that embodiments disclosed above are by way of illustration in all respects, not by way of limitation. It is intended that the scope of the present invention is defined by claims, not by the embodiments and examples above, and includes all modifications and variations equivalent in meaning and scope to the claims.

INDUSTRIAL APPLICABILITY

The present invention is advantageously applicable to a lateral junction field-effect transistor in which a leakage current in an OFF operation can be reduced.