Systems and methods for enhancing BIOS performance by alleviating code-size limitations

Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

TECHNICAL FIELD

Embodiments described herein generally relate to initialization of a computer system in a boot mode. In particular, embodiments described generally relate to systems and methods for enhancing BIOS performance by alleviating code size limitation.

BACKGROUND INFORMATION

When a computer system is first powered on, system memory is not yet available. To initialize the computer system, the processor reads and begins executing a Basic Input/Output System (BIOS) program from a non-volatile memory. The processor can use a Cache-as-RAM (CAR) to enable a processor cache to serve as a memory. The BIOS can then load instructions from the non-volatile memory into the CAR, read and execute instructions from the CAR using the processor's instruction fetch, decode, and execute pipeline, read data from the CAR to use as function arguments, and store data results and intermediate values to the CAR.

Using a CAR before system memory is available is challenging because there is nowhere to store cache lines that are evicted, for example by a LRU algorithm. A no-eviction mode (NEM) can be used, but imposes a limitation on the amount of memory that can be used for code and data in order to accommodate smaller processor caches.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following description, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail to not obscure the understanding of this description.

A BIOS (Basic Input/Output System) is a program that initializes a computer system after power-on. Since system memory is not yet available immediately after power-on, a processor loads the BIOS code into its cache, and used the cache in a Cache-as-RAM (CAR) mode to execute BIOS code. But as system memory has not yet been initialized, cache line evictions requiring a writeback to memory are to be avoided.

A BIOS program includes a code region that holds instructions to be read and executed by a processor. In some embodiments, a processor reads and executes instructions from the code region during a boot mode. A BIOS program also includes a data stack that holds data to be used by the BIOS program. The data stack may hold variables that have an initial, default value, but are modified during execution of the BIOS program instructions.

To accommodate BIOS code and data to be stored in the cache without evictions, some processors place limits on the size of the code region and data stack available for BIOS programs. BIOS writers face a challenge of fitting BIOS code into a small code footprint. If the processor cache is small, or if BIOS writers assume that the cache is small, the challenge of writing BIOS code with a small footprint is greater. The task or programming BIOS code having a small footprint becomes more challenging with new generations of computers and with a growing number of initialization functions to be performed by the BIOS code.

Embodiments disclosed herein offer BIOS writers the advantage of alleviating a code size limitation. Eliminating the code size limitation allows the BIOS writer to optimize the code and make it efficient. The impact of embodiments disclosed herein is particularly beneficial because a BIOS program's data stack is usually small, while the code region is larger, and grows with new generations of processors. Having a code size limitation is detrimental because such a limitation complicates the no-eviction mode (NEM) mode implementation and significantly increases the BIOS run time for products with smaller caches. In one embodiment, a method is disclosed of reading, from a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack; during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and writing at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified; gentering a no-modified-data-eviction mode to protect modified data in the cache as RAM from eviction, and to allow eviction and replacement of readable data in the cache as RAM; and beginning reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

As used herein, boot mode is a processor initialization state that is entered after the processor is powered on. During boot mode, system memory and other system services may not yet be available. Embodiments disclosed herein operate in boot mode, and do not require system memory availability.

FIG. 1is a block diagram illustrating processing components for executing an instruction according to one embodiment. Specifically, processor100includes instruction fetch circuit102, decode circuit104, execution circuit106, registers108, CAR110, and retire or commit circuit112. When the system is powered on and operating with a functional memory hierarchy, instructions can be fetched from system memory. When the system is first powered on, however, instruction fetch circuit102fetches instructions from CAR110, according to a Cache-as-RAM scheme.

After an instruction is fetched from the CAR, decode circuit104decodes the instruction. Execution circuit106is configured to read data from and write data to registers108as well as CAR110. Registers108comprise any one or more of a data register, an instruction register, a general register, and an on-chip memory. CAR110comprises any one or more of processor100cache memories that are useable after power-on.

Processing components illustrated inFIG. 1may be included in any of various commercially available processors, including, without limitation, an AMD® Athlon®, Duron® and Opteron® processors; ARM® application, embedded and secure processors; IBM® and Motorola® DragonBall® and PowerPC® processors; IBM and Sony® Cell processors; Qualcomm® Snapdragon®; Intel® Celeron®, Core (2) Duo®, Core i3, Core i5, Core i7, Itanium®, Pentium®, Xeon®, Atom® and XScale® processors; and similar processors. Dual microprocessors, multi-core processors, and other multi-processor architectures may also include processor components ofFIG. 1. Among other capabilities, the processor components may be configured to fetch and execute computer-readable instructions or processor-accessible instructions stored in a memory or other computer-readable storage media, including a BIOS program stored on a non-volatile memory, as illustrated inFIG. 2.

FIG. 2is block diagram of a processor having cache memories for use in enhancing BIOS performance by alleviating code-size limitations according to an embodiment. Processor200includes core202and core204, and L3 Cache206, also referred to herein as last-level cache (LLC)206. Core202and core204each include an L1 data cache, an L1 instruction cache, and an L2 cache. Processor200thus includes three levels of caches, each level being illustrated inFIG. 2by a label and a dashed line. In some embodiments, L1 caches are smaller and faster than L2 caches, which are smaller and faster than L3 caches.

In some embodiments, LLC206is partitioned into multiple ways. In some embodiments discussed herein, LLC206is partitioned into T ways, of which a first number of ways are for storing read/write (RW) data, and a second number of ways are for storing readable data. Further embodiments of cache ways are illustrated and described below with respect toFIG. 3andFIG. 4.

Core202in this embodiment is the designated Boot-Strap Processor (BSP), and will perform the boot sequence to execute the BIOS program. The boot sequence as described herein is a processor state entered after power-on, and before system memory is available. As described further below, Boot-Strap Processor202uses LLC206in a Cache-as-RAM (CAR) mode while executing the BIOS code.

The remaining logical processors (RLPs), including core204, may remain in an IDLE state awaiting completion of the boot sequence by core202, or they may perform other tasks.

FIG. 2also shows chipset208and non-volatile memory210, both of which are coupled to processor200. In embodiments disclosed herein, non-volatile memory210is to store a BIOS program to be loaded and executed by processor200as part of the boot sequence. Non-volatile memory210may be selected from any one of a ROM, a PROM, an EPROM, an EEPROM, and a flash memory. Additional embodiments of non-volatile memory210may be used, without limitation.

A benefit of embodiments disclosed herein is that the BIOS code region size is not limited by the size of any of the caches at levels L1, L2, or L3. As described further below, embodiments disclosed herein load BIOS code into readable ways of a cache, and evict code and replace it with new code without limitation. The BIOS code region size in disclosed embodiments is therefore not limited by the size of any of the L1, L2, or L3 caches.

FIG. 3is a block diagram of a cache memory partitioned into a first set of read/write ways and a second set of readable ways according to an embodiment. Here, LLC302is a last-level cache (LLC) partitioned into T=16 ways304, of which306is a data stack including a first number of ways having P ways, where P=1, to store RW data, and308is a code region including a second set of readable ways having O ways, where O=15, to store readable code and data, including BIOS program instructions, such as instructions loaded from non-volatile memory210(FIG. 2).

In the embodiment ofFIG. 3, a first number of ways includes one way of the LLC that is allocated for RW Data, while the remaining 15 ways in a second number of ways are readable and are used for Code. The BIOS data stack size is limited by the size of the 1 way, while the BIOS code region size is not limited because, as described further below, cache lines containing readable code are allowed to be evicted and replaced without limit.

In some embodiments, LLC302is partitioning dynamically as part of the boot sequence. In other embodiments, LLC302is partitioned beforehand.

FIG. 4is a block diagram of a cache memory partitioned into readable ways and read/writeable ways according to an embodiment. Here, cache402is a last-level cache (LLC) partitioned into T=8 ways404, of which406is a data stack including a first number of ways includes 2 ways (P=2 ways) to store RW data, and408is a code region including a second number of ways including 6 ways (O=6 ways) to store readable code and data, including BIOS program instructions, such as instructions loaded from non-volatile memory210(FIG. 2).

In the embodiment ofFIG. 4, two ways of the LLC are allocated for RW Data, while the remaining 6 ways are used for Code. The BIOS data stack size is limited by the size of the 2 ways, while the BIOS code region size is not limited because, as described further below, cache lines containing readable code are allowed to be evicted and replaced without limit.

In some embodiments, the readable and read/write partitioning of the cache is implemented using circuitry outside the cache. For example, read/writeable cache lines can be directed to the read/writeable cache ways, while readable cache lines can be directed to the readable ways.

FIG. 5illustrates a Cache Allocation Technology (CAT) that is supported in some processors. As shown, a system502without CAT does not allocate more cache resources to high-priority applications. In system502, the same amount of cache resources504are allocated to high-priority applications as the amount506allocated to low-priority applications. Cache Allocation Technology supported by some processors enables resource allocation on a per-application basis, per-thread basis, or per-processor core basis. Some processors support CAT cache partitioning for multiple cache levels, including for example Level 2 and Level 3 caches. Some embodiments disclosed herein repurpose CAT for use in allocating a first number of ways of a cache to read/write data and a second number of ways of the cache to readable data.

FIG. 6illustrates model-specific registers (MSRs) for use in enhancing BIOS performance by alleviating code-size limitations according to some embodiments. A model-specific register (MSR) is any of various software accessible control registers in a processor's instruction set or architectural register file that can be used to control certain CPU features. Some processors allow reading and writing to these registers using RDMSR and WRMSR instructions. Documentation regarding which MSRs a certain processor supports is usually found in the processor documentation of the CPU vendor. Some processors have a predefined set of MSRs.

Embodiments disclosed herein make use of three MSRs, as illustrated inFIG. 6. Way-mask-1602and way-mask-2604each contain 1 bit per cache way. If the bit is equal to ‘0,’ the way is protected from eviction. If the bit is equal to ‘1,’ the way is not protected from eviction. Conversely, when a cache line is read into the cache from the non-volatile memory, it will be placed in a way having a mask bit equal to ‘1.’ In other words, cache ways having a mask-bit equal to ‘0’ are protected from eviction, which would be required if a new cache line were to replace an existing cache line.

As illustrated, the total number of ways is T and the total number of ways to be protected from eviction is P. Way_mask_control606indicates which way-mask should be applied for a specific request while the processor uses the Cache-as-RAM (CAR) to execute BIOS program code in no-eviction mode (NEM). Way_mask_control606has 2 bits. In some embodiments, the default value for way_mask_control606is 2′b00, indicating that no way mask should be applied, 2′b01 indicating that way-mask-1should be applied, 2′b10 indicating that way-mask-2should be applied, and 2′b11 is not to be used in NEM mode. Upon the end of the NEM mode boot sequence, the default value, 2′b00, of way_mask_control606is restored.

In operation, according to some embodiments, as an initial step in performing BIOS program code in NEM mode, the processor reads a DWORD from every cache line of the BIOS data stack in order to bring all of the data stack into the cache. In so doing, way_mask_control606will be set to 2′b10, meaning that way-mask2604should be used, meaning that incoming cache lines will be stored in one of the first number of ways, and that no incoming cache lines will be stored in any of the second number of ways.

In operation, according to some embodiments, while the processor executes BIOS program code using the Cache-as-RAM (CAR) in NEM mode, way_mask_control606is set to 2′b01, indicating that way-mask-1602should be used to protect the P cache ways that hold RW data from eviction, but to allow cache lines in the O cache ways that hold code and readable data to be freely evicted and replaced, for example to load new BIOS instructions for execution.

FIG. 7illustrates a Memory Type Range Register (MTRR) according to an embodiment. In one embodiment, memory ranges and the types of memory specified in each range are set by three groups of registers: the IA32_MTRR_DEF_TYPE MSR, the fixed-range MTRRs, and the variable range MTRRs. These registers can be read and written to using the RDMSR and WRMSR instructions, respectively. The IA32_MTRRCAP MSR indicates the availability of these registers on the processor.

In at least one embodiment of a processor, IA32_MTRR_DEF_TYPE MSR702sets the default properties of the regions of physical memory that are not encompassed by MTRRs. The functions of the flags and field in this register are as follows: Type field, bits0through7, indicates the default memory type used for those physical memory address ranges that do not have a memory type specified for them by an MTRR.

At least one processor embodiment permits software to specify the memory type for “m” variable size address ranges, using a pair of MTRRs for each range. The first entry in each pair, here, IA32_MTRR_PHYSBASEn MSR794, defines the base address and memory type for the range; the second entry in each pair, here, IA32_MTRR_PHYSMASKn MSR706) contains a mask used to determine the address range. The “n” suffix is in the range 0 through m−1 and identifies a specific register pair.

FIG. 8is an embodiment of a method of a processor executing a BIOS program in a NEM mode using the Cache-as-RAM. At802, a processor is to read from a non-volatile memory by a processor during a boot mode, at least one datum from each cache line of a data stack of a BIOS program. At804, the processor is to use a first way mask to load the data stack into a first number of ways of a cache having a first number of ways to hold read/write (RW) data and a second number of ways to hold readable data. At896, the processor is to enter a no-eviction mode (NEM) during which a second way mask is to protect data stack cache lines stored in the a first number of ways from eviction, without limiting eviction and replacement of code from the second number of ways, thereby alleviating any BIOS code size limitation. At808, the processor begins executing the BIOS program using the Cache-as-RAM (CAR).

FIG. 9is an embodiment of method enabling a processor to execute a BIOS program in a NEM mode using the Cache-as-RAM. At902, the processor is to ensure that the system is in flat 32-bit protected mode. To do so, the processor performs various software routines to check processor state and conditions. If such a check should fail, the processor can raise an exception or otherwise give notice of a failure. At904, the processor is to ensure that only one logical processor per package is the boot-strap processor (BSP). At906, the processor is to ensure all other cores and application processors are in a Wait, for example a Wait-for-SIPI state used supported by some application processors in a multi-processor environment. At908, the processor is to load a microcode update into each boot-strap processor BSP. At910, the processor is to ensure that all variable-range Memory Type Range Register (MTRRs) valid flags are clear and IA32_MTRR_DEF_TYPE MSR E flag is clear. At912, the processor initializes all fixed-range and variable-range Memory Type Range Register (MTRRs) fields to 0 (MTRRs are discussed further below). At914, the processor configures the default memory type to un-cacheable (UC) in the IA32_MTRR_DEF_TYPE MSR. At916, the processor confirms that the data stack is limited, for example by determining the size of the data stack on the non-volatile memory that stores the BIOS program.

It is to be understood that not all of the steps ofFIG. 9are necessarily to be performed in order to use embodiments disclosed herein. Some of the steps ofFIG. 9may have been performed in the past, and need not be repeated. Some of the steps inFIG. 9may be skipped, or performed if a need should arise.

FIG. 10is an embodiment of a method to execute a BIOS program in a NEM mode using the Cache-as-RAM. At1002, the processor is to configure the data stack as write-back (WB) cacheable memory type using the variable range MTRRs. Cache lines designated as WB cacheable memory are fetched from memory on a cache miss. At1004, the processor is to determine the base address of the Code Region. At1006, the processor is to configure the Code Region as write-protected (WP) cacheable memory type using the variable range MTRRs, but does not yet set the Valid bit in MTRR_PHYSMASK yet. Cache lines designated as WP cacheable memory are cacheable, but will not be modified by a cache write. By not setting the “valid” we don't enable this MTRR. This way the code that is performed after this step is still uncacheable. At1008, the processor is to enable the MTRRs (Memory Type Range Register) by setting the IA32_MTRR_DEF_TYPE MSR E flag. At1010, the processor is to enable the logical processor's (BSP) cache: execute INVD and set CPU Cache Available, for example by setting CR0.CD=0, CR0.NW=0, as described in some processors' Software Development Manuals. At1012, the processor is to enable No-Eviction Mode Setup State by setting NO_EVICT_MODE (MSR 2E0h) bit0=‘1.’ At1014, the processor is to set WAY_MASK_CONTROL=0x02 and read one DWORD from each cache line of the data stack to bring the data stack into the cache (will go to the first number of ways only). At1014, way_mask_2is used to control loading RW data is the first number of ways of the cache. At1016, the processor is to set WAY_MASK_CONTROL=0x01, so as to enable way_mask_1to cause the first number of ways (P ways) to be protected from eviction, while allowing cache lines stored in the second number of ways to be freely evicted and replaced, for example by new BIOS program instructions. At1018, the processor is to set the Valid bit in MTRR_PHYSMASK for every WP MTRR of the Code Region from step1006. At1020, one location in each 64-byte cache line of the Data stack region is written to set to the cache line to MODIFIED state. At1022, a No-Eviction Mode Run State is enabled by setting NO_EVICT_MODE (bit1of MSR 2E0h)=‘1.’ From this point on, the read/write data in the first number of ways have a MODIFIED state and are protected from eviction, while the code stored in the second number of ways becomes cacheable and is loaded in the cache in the second number of ways that are not protected from eviction. The cache is therefore in a “no-modified-data-eviction mode.” The initialization method then ends and the processor can execute the BIOS program in NEM mode using Cache-as-RAM (CAR)

FIG. 11is an embodiment of method of shutting down a No-Eviction Mode state according to an embodiment. The method can be performed, for example, by a boot-strap processor upon completion of executing the BIOS program.

In some embodiments, at1102, the processor is to copy any stack data required by the BIOS after the boot sequence is completed should be copied to the initial system memory. In some embodiments, the initial system memory is to be in the un-cacheable (UC) state. In some embodiments, at1104, the processor is to Disable the MTRRs by clearing the IA32_MTRR_DEF_TYPE MSR E flag. In some embodiments, at1106, the processor is to Invalidate the cache. In some embodiments, the processor is to execute the INVD instruction to flush the cache. After this point, in some embodiments, cache data is no longer valid and the processor ensures that no data modification occurs until No-Eviction mode exit is completed. In some embodiments, at1108, the processor disables No-Eviction Mode Run State by clearing NO_EVICT_MODE MSR 2E0h bit [1]=0. Alternatively, in some embodiments, at1110, the processor is to Disable No-Eviction Mode Setup State by clearing NO_EVICT_MODE MSR 2E0h bit [0]=0. It is to be understood that one or the other of1108or1110is to be performed by the processor, not both. In some embodiments, at1112, the processor is to Set WAY_MASK_CONTROL=0x00, the default setting. By so doing, the processor ensures that no protected ways remain in the LLC cache; all the ways are allowed to be evicted. At1114, in some embodiments, the processor is to clear any machine check errors for machine check banks6,7,8and9(according to number of cores) which may have occurred due to large NEM code and data region sizes causing a write-back for the MLC to LLC eviction. In some embodiments, at1116, the processor is to configure the system memory and cache to initialize any remaining memory and MTRRs. At1118, the processor is to continue with power-on self-test (POST).

It is to be understood that not all the steps illustrated inFIG. 11need necessarily be performed to shut down an NEM mode boot sequence. The illustrated steps may be different when executed on a different processor. In addition, some processors may allow additional shut-down steps. Some processors may all fewer shut-down steps.

Instruction Sets

Exemplary Instruction Formats

Generic Vector Friendly Instruction Format

FIGS. 12A-12Bare block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to embodiments of the invention.FIG. 12Ais a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof according to embodiments of the invention; whileFIG. 12Bis a block diagram illustrating the generic vector friendly instruction format and class B instruction templates thereof according to embodiments of the invention. Specifically, a generic vector friendly instruction format1200for which are defined class A and class B instruction templates, both of which include no memory access1205instruction templates and memory access1220instruction templates. The term generic in the context of the vector friendly instruction format refers to the instruction format not being tied to any specific instruction set.

The class A instruction templates inFIG. 12Ainclude: 1) within the no memory access1205instruction templates there is shown a no memory access, full round control type operation1210instruction template and a no memory access, data transform type operation1215instruction template; and 2) within the memory access1220instruction templates there is shown a memory access, temporal1225instruction template and a memory access, non-temporal1230instruction template. The class B instruction templates inFIG. 12Binclude: 1) within the no memory access1205instruction templates there is shown a no memory access, write mask control, partial round control type operation1212instruction template and a no memory access, write mask control, vsize type operation1217instruction template; and 2) within the memory access1220instruction templates there is shown a memory access, write mask control1227instruction template.

The generic vector friendly instruction format1200includes the following fields listed below in the order illustrated inFIGS. 12A-12B.

Base operation field1242—its content distinguishes different base operations.

Augmentation operation field1250—its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In one embodiment of the invention, this field is divided into a class field1268, an alpha field1252, and a beta field1254. The augmentation operation field1250allows common groups of operations to be performed in a single instruction rather than 2, 3, or 4 instructions.

Scale field1260—its content allows for the scaling of the index field's content for memory address generation (e.g., for address generation that uses 2scale*index+base).

Displacement Field1262A—its content is used as part of memory address generation (e.g., for address generation that uses 2scale*index+base+displacement).

Displacement Factor Field1262B (note that the juxtaposition of displacement field1262A directly over displacement factor field1262B indicates one or the other is used)—its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N)—where N is the number of bytes in the memory access (e.g., for address generation that uses 2scale*index+base+scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field's content is multiplied by the memory operands total size (N) in order to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field1274(described later herein) and the data manipulation field1254C. The displacement field1262A and the displacement factor field1262B are optional in the sense that they are not used for the no memory access1205instruction templates and/or different embodiments may implement only one or none of the two.

Data element width field1264—its content distinguishes which one of a number of data element widths is to be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that it is not needed if only one data element width is supported and/or data element widths are supported using some aspect of the opcodes.

Class field1268—its content distinguishes between different classes of instructions. With reference toFIGS. 12A-B, the contents of this field select between class A and class B instructions. InFIGS. 12A-B, rounded corner squares are used to indicate a specific value is present in a field (e.g., class A1268A and class B1268B for the class field1268respectively inFIGS. 12A-B).

Instruction Templates of Class A

In the case of the non-memory access1205instruction templates of class A, the alpha field1252is interpreted as an RS field1252A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round1252A.1and data transform1252A.2are respectively specified for the no memory access, round type operation1210and the no memory access, data transform type operation1215instruction templates), while the beta field1254distinguishes which of the operations of the specified type is to be performed. In the no memory access1205instruction templates, the scale field1260, the displacement field1262A, and the displacement scale filed1262B are not present.

In the no memory access full round control type operation1210instruction template, the beta field1254is interpreted as a round control field1254A, whose content(s) provide static rounding. While in the described embodiments of the invention the round control field1254A includes a suppress all floating point exceptions (SAE) field1256and a round operation control field1258, alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field1258).

SAE field1256—its content distinguishes whether or not to disable the exception event reporting; when the SAE field's1256content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler.

In the no memory access data transform type operation1215instruction template, the beta field1254is interpreted as a data transform field1254B, whose content distinguishes which one of a number of data transforms is to be performed (e.g., no data transform, swizzle, broadcast).

In the case of a memory access1220instruction template of class A, the alpha field1252is interpreted as an eviction hint field1252B, whose content distinguishes which one of the eviction hints is to be used (inFIG. 12A, temporal1252B.1and non-temporal1252B.2are respectively specified for the memory access, temporal1225instruction template and the memory access, non-temporal1230instruction template), while the beta field1254is interpreted as a data manipulation field1254C, whose content distinguishes which one of a number of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; up conversion of a source; and down conversion of a destination). The memory access1220instruction templates include the scale field1260, and optionally the displacement field1262A or the displacement scale field1262B.

Memory Access Instruction Templates—Temporal

Memory Access Instruction Templates—Non-Temporal

Instruction Templates of Class B

In the case of the instruction templates of class B, the alpha field1252is interpreted as a write mask control (Z) field1252C, whose content distinguishes whether the write masking controlled by the write mask field1270should be a merging or a zeroing.

In the case of the non-memory access1205instruction templates of class B, part of the beta field1254is interpreted as an RL field1257A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round1257A.1and vector length (VSIZE)1257A.2are respectively specified for the no memory access, write mask control, partial round control type operation1212instruction template and the no memory access, write mask control, VSIZE type operation1217instruction template), while the rest of the beta field1254distinguishes which of the operations of the specified type is to be performed. In the no memory access1205instruction templates, the scale field1260, the displacement field1262A, and the displacement scale filed1262B are not present.

In the no memory access, write mask control, partial round control type operation1210instruction template, the rest of the beta field1254is interpreted as a round operation field1259A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler).

In the no memory access, write mask control, VSIZE type operation1217instruction template, the rest of the beta field1254is interpreted as a vector length field1259B, whose content distinguishes which one of a number of data vector lengths is to be performed on (e.g., 128, 256, or 512 byte).

In the case of a memory access1220instruction template of class B, part of the beta field1254is interpreted as a broadcast field1257B, whose content distinguishes whether or not the broadcast type data manipulation operation is to be performed, while the rest of the beta field1254is interpreted the vector length field1259B. The memory access1220instruction templates include the scale field1260, and optionally the displacement field1262A or the displacement scale field1262B.

With regard to the generic vector friendly instruction format1200, a full opcode field1274is shown including the format field1240, the base operation field1242, and the data element width field1264. While one embodiment is shown where the full opcode field1274includes all of these fields, the full opcode field1274includes less than all of these fields in embodiments that do not support all of them. The full opcode field1274provides the operation code (opcode).

The augmentation operation field1250, the data element width field1264, and the write mask field1270allow these features to be specified on a per instruction basis in the generic vector friendly instruction format.

Exemplary Specific Vector Friendly Instruction Format

FIG. 13Ais a block diagram illustrating an exemplary specific vector friendly instruction format according to embodiments of the invention.FIG. 13Ashows a specific vector friendly instruction format1300that is specific in the sense that it specifies the location, size, interpretation, and order of the fields, as well as values for some of those fields. The specific vector friendly instruction format1300may be used to extend the x86 instruction set, and thus some of the fields are similar or the same as those used in the existing x86 instruction set and extension thereof (e.g., AVX). This format remains consistent with the prefix encoding field, real opcode byte field, MOD R/M field, SIB field, displacement field, and immediate fields of the existing x86 instruction set with extensions. The fields fromFIG. 12into which the fields fromFIG. 13Amap are illustrated.

It should be understood that, although embodiments of the invention are described with reference to the specific vector friendly instruction format1300in the context of the generic vector friendly instruction format1200for illustrative purposes, the invention is not limited to the specific vector friendly instruction format1300except where claimed. For example, the generic vector friendly instruction format1200contemplates a variety of possible sizes for the various fields, while the specific vector friendly instruction format1300is shown as having fields of specific sizes. By way of specific example, while the data element width field1264is illustrated as a one bit field in the specific vector friendly instruction format1300, the invention is not so limited (that is, the generic vector friendly instruction format1200contemplates other sizes of the data element width field1264).

The generic vector friendly instruction format1200includes the following fields listed below in the order illustrated inFIG. 13A.

Format Field1240(EVEX Byte 0, bits [7:0])—the first byte (EVEX Byte 0) is the format field1240and it contains 0x62 (the unique value used for distinguishing the vector friendly instruction format in one embodiment of the invention).

The second-fourth bytes (EVEX Bytes 1-3) include a number of bit fields providing specific capability.

Data element width field1264(EVEX byte 2, bit [7]-W)—is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the datatype (either 32-bit data elements or 64-bit data elements).

EVEX.U1268Class field (EVEX byte 2, bit [2]-U)—If EVEX.U=0, it indicates class A or EVEX.U0; if EVEX.U=1, it indicates class B or EVEX.U1.

Alpha field1252(EVEX byte 3, bit [7]-EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also illustrated with α)—as previously described, this field is context specific.

Real Opcode Field1330(Byte 4) is also known as the opcode byte. Part of the opcode is specified in this field.

MOD R/M Field1340(Byte 5) includes MOD field1342, Reg field1344, and R/M field1346. As previously described, the MOD field's1342content distinguishes between memory access and non-memory access operations. The role of Reg field1344can be summarized to two situations: encoding either the destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field1346may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand.

Scale, Index, Base (SIB) Byte (Byte 6)—As previously described, the scale field's1250content is used for memory address generation. SIB.xxx1354and SIB.bbb1356—the contents of these fields have been previously referred to with regard to the register indexes Xxxx and Bbbb.

Displacement field1262A (Bytes 7-10)—when MOD field1342contains 10, bytes 7-10 are the displacement field1262A, and it works the same as the legacy 32-bit displacement (disp32) and works at byte granularity.

Full Opcode Field

FIG. 13Bis a block diagram illustrating the fields of the specific vector friendly instruction format1300that make up the full opcode field1274according to one embodiment of the invention. Specifically, the full opcode field1274includes the format field1240, the base operation field1242, and the data element width (W) field1264. The base operation field1242includes the prefix encoding field1325, the opcode map field1315, and the real opcode field1330.

Register Index Field

FIG. 13Cis a block diagram illustrating the fields of the specific vector friendly instruction format1300that make up the register index field1244according to one embodiment of the invention. Specifically, the register index field1244includes the REX field1305, the REX′ field1310, the MODR/M.reg field1344, the MODR/M.r/m field1346, the VVVV field1320, xxx field1354, and the bbb field1356.

Augmentation Operation Field

FIG. 13Dis a block diagram illustrating the fields of the specific vector friendly instruction format1300that make up the augmentation operation field1250according to one embodiment of the invention. When the class (U) field1268contains 0, it signifies EVEX.U0 (class A1268A); when it contains 1, it signifies EVEX.U1 (class B1268B). When U=0 and the MOD field1342contains 11 (signifying a no memory access operation), the alpha field1252(EVEX byte 3, bit [7]-EH) is interpreted as the rs field1252A. When the rs field1252A contains a 1 (round1252A.1), the beta field1254(EVEX byte 3, bits [6:4]—SSS) is interpreted as the round control field1254A. The round control field1254A includes a one bit SAE field1256and a two bit round operation field1258. When the rs field1252A contains a 0 (data transform1252A.2), the beta field1254(EVEX byte 3, bits [6:4]—SSS) is interpreted as a three bit data transform field1254B. When U=0 and the MOD field1342contains 00, 01, or 10 (signifying a memory access operation), the alpha field1252(EVEX byte 3, bit [7]-EH) is interpreted as the eviction hint (EH) field1252B and the beta field1254(EVEX byte 3, bits [6:4]—SSS) is interpreted as a three bit data manipulation field1254C.

When U=1, the alpha field1252(EVEX byte 3, bit [7]-EH) is interpreted as the write mask control (Z) field1252C. When U=1 and the MOD field1342contains 11 (signifying a no memory access operation), part of the beta field1254(EVEX byte 3, bit [4]—S0) is interpreted as the RL field1257A; when it contains a 1 (round1257A.1) the rest of the beta field1254(EVEX byte 3, bit [6-5]—S2-1) is interpreted as the round operation field1259A, while when the RL field1257A contains a 0 (VSIZE1257.A2) the rest of the beta field1254(EVEX byte 3, bit [6-5]—S2-1) is interpreted as the vector length field1259B (EVEX byte 3, bit [6-5]-L1-0). When U=1 and the MOD field1342contains 00, 01, or 10 (signifying a memory access operation), the beta field1254(EVEX byte 3, bits [6:4]—SSS) is interpreted as the vector length field1259B (EVEX byte 3, bit [6-5]-L1-0) and the broadcast field1257B (EVEX byte 3, bit [4]—B).

Exemplary Register Architecture

FIG. 14is a block diagram of a register architecture1400according to one embodiment of the invention. In the embodiment illustrated, there are 32 vector registers1410that are 512 bits wide; these registers are referenced as zmm0through zmm31. The lower order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-16. The lower order 128 bits of the lower 16 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15. The specific vector friendly instruction format1300operates on these overlaid register file as illustrated in the below tables.

In other words, the vector length field1259B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length; and instructions templates without the vector length field1259B operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of the specific vector friendly instruction format1300operate on packed or scalar single/double-precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in an zmm/ymm/xmm register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment.

Write mask registers1415—in the embodiment illustrated, there are 8 write mask registers (k0through k7), each 64 bits in size. In an alternate embodiment, the write mask registers1415are 16 bits in size. As previously described, in one embodiment of the invention, the vector mask register k0cannot be used as a write mask; when the encoding that would normally indicate k0is used for a write mask, it selects a hardwired write mask of 0xFFFF, effectively disabling write masking for that instruction.

Exemplary Core Architectures

In-Order and Out-of-Order Core Block Diagram

InFIG. 15A, a processor pipeline1500includes a fetch stage1502, a length decode stage1504, a decode stage1506, an allocation stage1508, a renaming stage1510, a scheduling (also known as a dispatch or issue) stage1512, a register read/memory read stage1514, an execute stage1516, a write back/memory write stage1518, an exception handling stage1522, and a commit stage1524.

FIG. 15Bshows processor core1590including a front end unit1530coupled to an execution engine unit1550, and both are coupled to a memory unit1570. The core1590may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core1590may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit1530includes a branch prediction unit1532coupled to an instruction cache unit1534, which is coupled to an instruction translation lookaside buffer (TLB)1536, which is coupled to an instruction fetch unit1538, which is coupled to a decode unit1540. The decode unit1540(or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit1540may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core1590includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit1540or otherwise within the front end unit1530). The decode unit1540is coupled to a rename/allocator unit1552in the execution engine unit1550.

The execution engine unit1550includes the rename/allocator unit1552coupled to a retirement unit1554and a set of one or more scheduler unit(s)1556. The scheduler unit(s)1556represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)1556is coupled to the physical register file(s) unit(s)1558. Each of the physical register file(s) units1558represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit1558comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s)1558is overlapped by the retirement unit1554to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit1554and the physical register file(s) unit(s)1558are coupled to the execution cluster(s)1560. The execution cluster(s)1560includes a set of one or more execution units1562and a set of one or more memory access units1564. The execution units1562may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)1556, physical register file(s) unit(s)1558, and execution cluster(s)1560are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)1564). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units1564is coupled to the memory unit1570, which includes a data TLB unit1572coupled to a data cache unit1574coupled to a level 2 (L2) cache unit1576. In one exemplary embodiment, the memory access units1564may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit1572in the memory unit1570. The instruction cache unit1534is further coupled to a level 2 (L2) cache unit1576in the memory unit1570. The L2 cache unit1576is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline1500as follows: 1) the instruction fetch1538performs the fetch and length decoding stages1502and1504; 2) the decode unit1540performs the decode stage1506; 3) the rename/allocator unit1552performs the allocation stage1508and renaming stage1510; 4) the scheduler unit(s)1556performs the schedule stage1512; 5) the physical register file(s) unit(s)1558and the memory unit1570perform the register read/memory read stage1514; the execution cluster1560perform the execute stage1516; 6) the memory unit1570and the physical register file(s) unit(s)1558perform the write back/memory write stage1518; 7) various units may be involved in the exception handling stage1522; and 8) the retirement unit1554and the physical register file(s) unit(s)1558perform the commit stage1524.

Specific Exemplary In-Order Core Architecture

FIG. 16Ais a block diagram of a single processor core, along with its connection to the on-die interconnect network1602and with its local subset of the Level 2 (L2) cache1604, according to embodiments of the invention. In one embodiment, an instruction decoder1600supports the x86 instruction set with a packed data instruction set extension. An L1 cache1606allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit1608and a vector unit1610use separate register sets (respectively, scalar registers1612and vector registers1614) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache1606, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

FIG. 16Bis an expanded view of part of the processor core inFIG. 16Aaccording to embodiments of the invention.FIG. 16Bincludes an L1 data cache1606A part of the L1 cache1604, as well as more detail regarding the vector unit1610and the vector registers1614. Specifically, the vector unit1610is a 16-wide vector processing unit (VPU) (see the 16-wide ALU1628), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit1620, numeric conversion with numeric convert units1622A-B, and replication with replication unit1624on the memory input. Write mask registers1626allow predicating resulting vector writes.

FIG. 17is a block diagram of a processor1700that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes inFIG. 17illustrate a processor1700with a single core1702A, a system agent1710, a set of one or more bus controller units1716, while the optional addition of the dashed lined boxes illustrates an alternative processor1700with multiple cores1702A-N, a set of one or more integrated memory controller unit(s)1714in the system agent unit1710, and special purpose logic1708.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units1706, and external memory (not shown) coupled to the set of integrated memory controller units1714. The set of shared cache units1706may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit1712interconnects the integrated graphics logic1708(integrated graphics logic1708is an example of and is also referred to herein as special purpose logic), the set of shared cache units1706, and the system agent unit1710/integrated memory controller unit(s)1714, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units1706and cores1702-A-N.

In some embodiments, one or more of the cores1702A-N are capable of multithreading. The system agent1710includes those components coordinating and operating cores1702A-N. The system agent unit1710may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores1702A-N and the integrated graphics logic1708. The display unit is for driving one or more externally connected displays.

Exemplary Computer Architectures

Referring now toFIG. 18, shown is a block diagram of a system1800in accordance with one embodiment of the present invention. The system1800may include one or more processors1810,1815, which are coupled to a controller hub1820. In one embodiment the controller hub1820includes a graphics memory controller hub (GMCH)1890and an Input/Output Hub (IOH)1850(which may be on separate chips); the GMCH1890includes memory and graphics controllers to which are coupled memory1840and a coprocessor1845; the IOH1850couples input/output (I/O) devices1860to the GMCH1890. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory1840and the coprocessor1845are coupled directly to the processor1810, and the controller hub1820in a single chip with the IOH1850.

The optional nature of additional processors1815is denoted inFIG. 18with broken lines. Each processor1810,1815may include one or more of the processing cores described herein and may be some version of the processor1700.

The memory1840may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub1820communicates with the processor(s)1810,1815via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection1895.

In one embodiment, the coprocessor1845is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub1820may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources1810,1815in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor1810executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor1810recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor1845. Accordingly, the processor1810issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor1845. Coprocessor(s)1845accept and execute the received coprocessor instructions.

Referring now toFIG. 19, shown is a block diagram of a first more specific exemplary system1900in accordance with an embodiment of the present invention. As shown inFIG. 19, multiprocessor system1900is a point-to-point interconnect system, and includes a first processor1970and a second processor1980coupled via a point-to-point interconnect1950. Each of processors1970and1980may be some version of the processor1700. In one embodiment of the invention, processors1970and1980are respectively processors1810and1815, while coprocessor1938is coprocessor1845. In another embodiment, processors1970and1980are respectively processor1810coprocessor1845.

Processors1970and1980are shown including integrated memory controller (IMC) units1972and1982, respectively. Processor1970also includes as part of its bus controller units point-to-point (P-P) interfaces1976and1978; similarly, second processor1980includes P-P interfaces1986and1988. Processors1970,1980may exchange information via a point-to-point (P-P) interface1950using P-P interface circuits1978,1988. As shown inFIG. 19, IMCs1972and1982couple the processors to respective memories, namely a memory1932and a memory1934, which may be portions of main memory locally attached to the respective processors.

Processors1970,1980may each exchange information with a chipset1990via individual P-P interfaces1952,1954using point to point interface circuits1976,1994,1986,1998. Chipset1990may optionally exchange information with the coprocessor1938via a high-performance interface1992. In one embodiment, the coprocessor1938is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

Chipset1990may be coupled to a first bus1916via an interface1996. In one embodiment, first bus1916may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.

As shown inFIG. 19, various I/O devices1914may be coupled to first bus1916, along with a bus bridge1918which couples first bus1916to a second bus1920. In one embodiment, one or more additional processor(s)1915, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus1916. In one embodiment, second bus1920may be a low pin count (LPC) bus. Various devices may be coupled to a second bus1920including, for example, a keyboard and/or mouse1922, communication devices1927and a storage unit1928such as a disk drive or other mass storage device which may include instructions/code and data1930, in one embodiment. Further, an audio I/O1924may be coupled to the second bus1920. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG. 19, a system may implement a multi-drop bus or other such architecture.

Referring now toFIG. 20, shown is a block diagram of a second more specific exemplary system2000in accordance with an embodiment of the present invention. Like elements inFIGS. 19 and 20bear like reference numerals, and certain aspects ofFIG. 19have been omitted fromFIG. 20in order to avoid obscuring other aspects ofFIG. 20.

FIG. 20illustrates that the processors1970,1980may include integrated memory and I/O control logic (“CL”)1972and1982, respectively. Thus, the CL1972,1982include integrated memory controller units and include I/O control logic.FIG. 20illustrates that not only are the memories1932,1934coupled to the CL1972,1982, but also that I/O devices2014are also coupled to the control logic1972,1982. Legacy I/O devices2015are coupled to the chipset1990.

Referring now toFIG. 21, shown is a block diagram of a SoC2100in accordance with an embodiment of the present invention. Similar elements inFIG. 17bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. InFIG. 21, an interconnect unit(s)2102is coupled to: an application processor2110which includes a set of one or more cores1702A-N, which include cache units1704A-N, and shared cache unit(s)1706; a system agent unit1710; a bus controller unit(s)1716; an integrated memory controller unit(s)1714; a set or one or more coprocessors2120which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit2130; a direct memory access (DMA) unit2132; and a display unit2140for coupling to one or more external displays. In one embodiment, the coprocessor(s)2120include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

FIG. 22is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof.FIG. 22shows a program in a high level language2202may be compiled using an x86 compiler2204to generate x86 binary code2206that may be natively executed by a processor with at least one x86 instruction set core2216. The processor with at least one x86 instruction set core2216represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler2204represents a compiler that is operable to generate x86 binary code2206(e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core2216.

Similarly,FIG. 22shows the program in the high level language2202may be compiled using an alternative instruction set compiler2208to generate alternative instruction set binary code2210that may be natively executed by a processor without at least one x86 instruction set core2214(e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif. and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.). The instruction converter2212is used to convert the x86 binary code2206into code that may be natively executed by the processor without an x86 instruction set core2214. This converted code is not likely to be the same as the alternative instruction set binary code2210because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter2212represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code2206.

FURTHER EXAMPLES

Example 1 provides a system that includes: a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, and a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

Example 2 includes the substance of example 1, wherein the cache as RAM comprises at least two cache ways, and wherein the circuit to use a first way-mask during the reading the at least one datum from each cache line of the data stack to cause the cache lines of the data stack to be loaded into a first number of ways of the cache as RAM.

Example 3 includes the substance of example 2, wherein cache lines stored in the first number of ways of the cache as RAM be protected from eviction.

Example 4 includes the substance of any one of examples 2-3, wherein the circuit to use a second way-mask during the reading from the readable code region to cause the readable code data to be loaded into a second number of ways of the cache as RAM, the cache lines in the second number of ways to be allowed to be evicted and replaced.

Example 5 includes the substance of example 4, wherein a code region size is not limited by a cache as RAM size.

Example 6 includes the substance of example 5, wherein the circuit is further to continue reading from the readable code region while allowing at least one readable code region cache line to be evicted and replaced.

Example 7 includes the substance of example 6, wherein the first way mask and the second way mask comprise software-accessible model-specific registers, and wherein the circuit further to use a software-accessible way control register to specify what mask to use during read and write operations.

Example 8 includes the substance of example 1, wherein the cache as RAM is a level 3 cache and the at least two processor cores each include a level 1 cache and a level 2 cache, wherein a code region size is not limited by a level 3 cache size.

Example 9 includes the substance of any one of examples 1-8, wherein the memory is selected from the group consisting of: a read-only memory, a programmable read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory, and a flash memory.

Example 10 includes the substance of any one of examples 2-7, wherein the circuit to utilize a cache allocation technology to control which cache ways of the cache as RAM are to be protected from eviction.

Example 11 provides a system that includes: circuitry to: read, using a cache as RAM (CAR) during a boot mode, at least one datum from each cache line of a data stack of a basic input/output system (BIOS) program having a readable code region and a readable and writeable data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

Example 12 includes the substance of example 11, wherein the cache as RAM comprises at least two cache ways, and wherein the circuitry to use a first way-mask during the reading the at least one datum from each cache line of the data stack to cause the cache lines of the data stack to be loaded into a first number of ways of the cache as RAM.

Example 13 includes the substance of example 12, wherein cache lines stored in the first number of ways of the cache as RAM are to be protected from eviction.

Example 14 includes the substance of any one of examples 12-13, wherein the circuitry to use a second way-mask during the reading from the readable code region to cause the readable code data to be loaded into a second number of ways of the cache as RAM, the cache lines in the second number of ways to be allowed to be evicted and replaced.

Example 15 includes the substance of any one of examples 12-14, wherein the first way mask and the second way mask comprise software-accessible model-specific registers, and wherein the circuitry further to use a software-accessible way control register to specify what mask to use during read and write operations.

Example 16 provides a method that includes: reading, from a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and writing at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, entering a no-modified-data-eviction mode to protect modified data in the cache as RAM from eviction, and to allow eviction and replacement of readable data in the cache as RAM, and beginning reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

Example 17 includes the substance of example 16, wherein the cache as RAM comprises at least two cache ways, further comprising using a first way-mask during the reading the at least one datum from each cache line of the data stack to cause the cache lines of the data stack to be loaded into a first number of ways of the cache as RAM.

Example 18 includes the substance of example 17, wherein cache lines stored in the first number of ways of the cache as RAM are to be protected from eviction.

Example 19 includes the substance of any one of examples 17-18, further comprising using a second way-mask during the reading from the readable code region to cause the readable code data to be loaded into a second number of ways of the cache as RAM, the cache lines in the second number of ways to be allowed to be evicted and replaced.

Example 20 includes the substance of example 19, wherein a code region size is not limited by a cache as RAM size.

Example 21 includes the subject matter of any one of examples 19 to 20. In this example, a size of the code region is not limited by a size of the cache.

Example 22 includes the subject matter of example 21. This example further includes initializing the processor before reading the data stack from the non-volatile memory, wherein the initializing the processor comprises: clearing flags of the variable-range MTRR and the another variable-range MTRR, initializing the variable-range MTRR and the another variable-range MTRR to 0, and configuring a default memory type to un-cacheable (UC) in a memory type range register DEF-TYPE model specific register (MSR).

Example 23 includes the subject matter of any one of examples 19 to 22. This example further includes, after reading the at least one DWORD from each cache line of the data stack, writing at least one location in each cache line of the data stack to set each cache line of the data stack to a modified state.

Example 24 includes the subject matter of any one of examples 19 to 23. In this example, the non-volatile memory is selected from the group consisting of: a ROM, a PROM, an EPROM, an EEPROM, and a flash memory.

Example 25 includes the subject matter of any one of examples 19 to 24. This example further includes executing instructions from the BIOS program.

Example 26 includes the subject matter of any one of examples 19 to 25. In this example, the processor to utilize a Cache Allocation Technology (CAT) to control which cache ways are to be enabled for loading and protected from eviction.

Example 27 includes the subject matter of any one of examples 19 to 26. In this example, the first way mask and the second way mask comprise model-specific registers (MSRs) that are included in the processor's set of software-accessible MSRs, the first way mask and the second way mask to include one bit per each cache way to specify whether cache lines in that cache way are to be protected from eviction.

Example 28 includes the subject matter of example 28. In this example, the processor's set of software accessible MSRs further to include a cache-way-control MSR comprising a two-bit code to select whether to not apply any way mask, to apply the first way mask, or to apply the second way mask, and the fourth code value is reserved.

Example 29 provides a system including a non-volatile memory to have stored thereon a BIOS program, and a processor coupled to the non-volatile memory, the processor comprising an execution unit to perform the steps of: reading from a non-volatile memory by a processor during a boot mode, at least one datum from each cache line of a data stack of a BIOS program, and using a first way mask to load the data stack into a first number of ways of a cache having the first number of ways to hold read/write (RW) data and a second number of ways to hold readable data read from a code region of the BIOS program, beginning execution of the BIOS program by the processor using the cache in a Cache-as-RAM (CAR) mode after entering a no-eviction mode (NEM) during which a second way mask is to protect data stack cache lines stored in the first number of ways from eviction, and to allow unlimited eviction and replacement of code cache lines from the second number of ways.

Example 30 includes the substance of example 29. In this example, the execution unit is further to perform the steps of: configuring a variable-range memory type range register (MTRR) to set the memory associated with the code region as write-protected (WP) cacheable memory, configuring another variable-range MTRR to set the memory associated with the data stack as write-back (WB) cacheable memory, configuring a MTRR PHYSMASK register to reflect a size of the data stack, and set a valid bit of the MTRR PHYSMASK register, configuring another MTRR PHYSMASK register to reflect a size of the code region, and after entering the NEM mode, setting a valid bit of the another MTRR PHYSMASK register.

Example 31 includes the substance of example 30. In this example, the execution circuit further to initialize the processor before reading the data stack from the non-volatile memory, wherein the initializing the processor comprises: clearing flags of the variable-range MTRR and the another variable-range MTRR, initializing the variable-range MTRR and the another variable-range MTRR to 0, and configuring the default memory type to un-cacheable (UC) in a memory type range register DEF-TYPE model specific register (MSR).

Example 32 includes the substance of any one of examples 29 to 31. In this example, the execution circuit further to, after reading the at least one DWORD from each cache line of the data stack, write at least one location in each cache line of the data stack to set each cache line of the data stack to a modified state.

Example 33 includes the substance of any one of examples 29 to 32. In this example, the processor is to utilize a Cache Allocation Technology (CAT) to enable the second number of ways and the first number of ways to be loaded and evicted.

Example 34 includes the substance of any one of examples 29 to 33. In this example, the processor is one of at least two processors in a multiprocessor system, and wherein the processor is a sole boot-strap processor (BSP), the remaining processors to await completion of the boot mode in an IDLE state.

Example 35 includes the substance of any one of examples 29 to 35. In this example, the first way mask and the second way mask comprise model-specific registers (MSRs) that are included in the processor's set of software-accessible MSRs, the first way mask and the second way mask to include one bit per each cache way to specify whether cache lines in that cache way are to be protected from eviction.

Example 36 includes the substance of examples 35. In this example, the processor's set of software accessible MSRs further to include a cache-way-control MSR comprising a two-bit code to select whether to not apply any way mask, to apply the first way mask, or to apply the second way mask, and the fourth code value is reserved.

Example 37 includes the substance of any one of examples 29 to 36. In this example, a size of the code region is not limited by a size of the cache.

Example 38 provides a system including a non-volatile memory to have stored thereon a BIOS program, and a processor coupled to the non-volatile memory, the processor comprising: means for executing computer-executable instructions, means for reading from a non-volatile memory by a processor during a boot mode, at least one datum from each cache line of a data stack of a BIOS program, and means for using a first way mask to load the data stack into a first number of ways of a cache having a first number of ways to hold read/write (RW) data and a second number of ways to hold readable data read from a code region of the BIOS program,

wherein the means for executing computer-executable instructions to begin execution of the BIOS program by the processor using the cache in a Cache-as-RAM (CAR) mode after entering a no-eviction mode (NEM) during which a second way mask is to protect data stack cache lines stored in the first number of ways from eviction, and to allow unlimited eviction and replacement of code cache lines from the second number of ways.

Example 39 includes the substance of example 38, wherein a size of the code region is not limited by a size of the cache.

Although some embodiments disclosed herein involve data handling and distribution in the context of hardware execution circuits, other embodiments can be accomplished by way of a data or instructions stored on a non-transitory machine-readable, tangible medium, which, when performed by a machine, cause the machine to perform functions consistent with at least one embodiment. In one embodiment, functions associated with embodiments of the present disclosure are embodied in machine-executable instructions. The instructions can be used to cause a general-purpose or special-purpose processor that is programmed with the instructions to perform the steps of the at least one embodiment. Embodiments disclosed herein may be provided as a computer program product or software which may include a machine or computer-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform one or more operations according to the at least one embodiment. Alternatively, steps of embodiments may be performed by specific hardware components that contain fixed-function logic for performing the steps, or by any combination of programmed computer components and fixed-function hardware components.