THREE-DIMENSIONAL MEMORY DEVICES AND MANUFACTURING METHODS THEREOF AND THREE-DIMENSIONAL MEMORIES

The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, and a three-dimensional memory. The three-dimensional memory device includes a first memory cell and at least one second memory cell sequentially stacked on the first memory cell. Each memory cell includes a first set of contacts, and a memory array device and a CMOS device that are stacked and electrically connected with each other, and the first set of contacts is disposed on a side of the memory array device facing away from the CMOS device and electrically connected with the CMOS device. The second memory cell further comprises a second set of contacts that is disposed on a side of the CMOS device facing away from the memory array device and electrically connected with the CMOS device. The memory array device of the first memory cell is bonded with the CMOS device of the adjacent second memory cell, and the first set of contacts of the first memory cell is correspondingly electrically connected with the second set of contacts of the adjacent second memory cell.

TECHNICAL FIELD

The present disclosure relates to semiconductor devices, and particularly to a three-dimensional memory devices and a manufacturing methods thereof, and three-dimensional memories including the three-dimensional memory devices.

BACKGROUND

A 3D NAND memory is an emerging type of three-dimensional memory, and addresses the problem that a 2D or planar NAND memory has a limited storage capacity by vertically stacking multiple data memory layers in a memory chip. The memory chip includes a CMOS device and a memory array device with a step structure. The CMOS device and the memory array device are formed on a substrate separately, and the sides of the CMOS device and the memory array device far away from each substrate are electrically connected with each other.

With increasing growth of high-density design demands on the 3D NAND memory, the memory layers in the memory array device of the memory chip are increasing day by day. However, with the increase of the number of stack layers of the memory layers, both the number of step layers and the footprint of the step structure of the memory array device are increased such that the substrate area of the memory array device is increased, which therefore results in the area mismatch between the substrate of the memory array device and the substrate of the CMOS device and causes idle utilization space of the memory chip, thereby being unfavorable to development and volume miniaturization of a next generation 3D NAND memory.

Illustration of symbols of example elements found in the description:

The Detailed Description below will further illustrate the present disclosure in conjunction with the above-mentioned drawings.

DETAILED DESCRIPTION

The technical solutions in examples of the present disclosure will be described below clearly and completely in conjunction with the drawings in the examples of the present disclosure. The examples described are only part of, but not all of, the examples of the present disclosure. All other examples obtained by those of ordinary skill in the art based on the examples in the present disclosure without creative work shall fall in the scope of protection of the present disclosure.

In the description of the present disclosure, it is to be noted that the terms “upper”, “lower”, “inner side”, “outer side”, etc. indicate orientations or position relationships that are based on the orientations or position relationships as shown in the figures, which are only intended to facilitate description of the present disclosure and to simplify the description, instead of indicating or implying that the device or element indicated must have a specific orientation and be configured and operated in a specific orientation, and thus cannot be understood as limiting the present disclosure. Furthermore, the terms “first”, “second”, etc. are only for the purpose of description, and cannot be construed as indicating or implying relative importance.

Referring toFIGS.1and2, the present disclosure provides a three-dimensional memory device which comprises at least two memory cells that are stacked sequentially, where the at least two memory cells comprise a first memory cell100and at least one second memory cell200stacked on the first memory cell100. As shown inFIG.1, in one of the examples of the present disclosure, the number of the second memory cells200is one, and the first memory cell100and one second memory cell200are stacked to constitute a three-dimensional memory device1000; as shown inFIG.2, in another example of the present disclosure, the number of the second memory cells200is multiple (two or more), the multiple second memory cells200are sequentially stacked on the first memory cell100, and the first memory cell100and the multiple second memory cells200are stacked to constitute a three-dimensional memory device1000b. The three-dimensional memory device provided by the present disclosure is formed by stacking at least two memory cells, and thus has a high storage density.

As shown inFIGS.1and2, in some examples of the present disclosure, each memory cell comprises a memory array device10and a CMOS device20that are stacked and electrically connected with each other, and a first set of contacts40disposed on a side of the memory array device10facing away from the CMOS device20and electrically connected with the CMOS device20. In some examples of the present disclosure, the memory array device10and the CMOS device20of each memory cell may be connected by bonding to achieve electrical connection therebetween. Of course, in other examples, the memory array device10and the CMOS device20of each memory cell may also achieve electrical connection by other means, including, but not limited to, wire connection, conductive contact connection, plug-in connection, etc.

The memory array device10comprises an array substrate11and a memory array disposed on a side of the array substrate11close to the CMOS device20, where the memory array has a data storage function, and comprises several memory layers13and several memory strings penetrating through and connecting together the several memory layers13. The first set of contacts40of each memory cell is disposed on a side of the array substrate11facing away from the CMOS device20. The CMOS device20comprises a CMOS substrate21and a CMOS circuit disposed on a side of the CMOS substrate21close to the memory array device10, where the CMOS circuit is used to achieve logic control, read of stored data, and the like for the memory array device10.

As shown inFIGS.1and2, in some examples of the present disclosure, each memory cell further comprises an interconnection channel30that is electrically connected respectively with the first set of contacts40and the CMOS device20of the memory cell where the interconnection channel30is located, so that the first set of contacts40is electrically connected with the CMOS device20through the interconnection channel30. In some examples of the present disclosure, the interconnection channel30is disposed in the memory array device10and the CMOS device20of the memory cell where the interconnection channel30is located, and is perpendicular to the array substrate11and the CMOS substrate21. Of course, in other examples, the interconnection channel30may also be not perpendicular to the array substrate11and the CMOS substrate21, and may also be perpendicular to the array substrate11or be perpendicular to the CMOS substrate21.

In some examples of the present disclosure, each second memory cell200further comprises a second set of contacts50. In some examples, the second set of contacts50is disposed on a side of the CMOS device20of the second memory cell200facing away from the memory array device10of the second memory cell200, and is electrically connected with the CMOS device20of the second memory cell200.

As shown inFIGS.1and2, in some examples of the present disclosure, the memory array device10of the first memory cell100is bonded with the CMOS device20of the adjacent second memory cell200, and the first set of contacts40of the first memory cell100is correspondingly electrically connected with the second set of contacts50of the adjacent second memory cell200such that the first memory cell100is electrically connected with the adjacent second memory cell200through the first set of contacts40and the second set of contacts50.

As shown inFIG.1, in one of the examples of the present disclosure, when there is only one second memory cell200in the three-dimensional memory device1000, the second memory cell200is an outer second memory cell200stacked on the first memory cell100, and the first set of contacts40of the outer second memory cell200is used to connect to an external device (e.g., a control device or a drive circuit, etc.) to achieve functions such as drive, control and the like for the three-dimensional memory device1000.

As shown inFIG.2, in another example of the present disclosure, when there are multiple second memory cells200in the three-dimensional memory device1000b, the multiple second memory cells200are sequentially stacked on the first memory cell100; for two adjacent ones of the second memory cells200, the first set of contacts40of the second memory cell200close to the first memory cell100is correspondingly electrically connected with the second set of contacts50of the second memory cell200far away from the first memory cell100such that the two adjacent second memory cells200achieve electrical connection through the corresponding first set of contacts40and the second set of contacts50, and then the first memory cell100and the multiple second memory cells200sequentially stacked on the first memory cell100achieve electrical connection. The second memory cell200farthest away from the first memory cell100along a stacking direction is an outer second memory cell200stacked on the first memory cell100, and the first set of contacts40of the outer second memory cell200is used to connect to an external device (e.g., a control device or a drive circuit, etc.) to achieve functions such as drive, control and the like for the three-dimensional memory device1000b. It can be understood that the number of memory cells stacked in the three-dimensional memory device1000bis more as compared with the three-dimensional memory device1000, and thus, the storage density of the three-dimensional memory device1000bis higher.

In the examples of the present disclosure, by sequentially stacking at least two memory cells and achieving electrical connection between the at least two memory cells through the corresponding first set of contacts40and the second set of contacts50, the three-dimensional memory device with a high storage density may be constituted, without the necessity to stack too many memory layers13in the memory array device10of each memory cell, such that the area of the array substrate11of each memory cell is not too large, which is favorable to dispose the array substrate11and the CMOS substrate21of each memory cell at a proper area ratio, and the idle utilization space in each memory cell can be further reduced and the space utilization rate of the three-dimensional memory device can be increased.

Both the array substrate11and the CMOS substrate21may be made of a semiconductor material or a non-conductive material, where the semiconductor material includes, but is not limited to, silicon, germanium, silicon germanium, gallium arsenide, silicon on insulator, germanium on insulator or any suitable combination thereof, and the non-conductive material includes, but is not limited to, glass, plastic, or sapphire. In the examples of the present disclosure, both the array substrate11and the CMOS substrate21are silicon substrates. Except the CMOS substrate21of the first memory cell100, the array substrate11and the CMOS substrate21of any memory cell in the three-dimensional memory device may be thinned to be favorable to reduce the volume of the three-dimensional memory device. The means of thinning include, but are not limited to, mechanical polishing, wet/dry etching, chemical mechanical polishing, or any combination thereof.

As shown inFIGS.1and2, in each memory array device10, several memory layers13are stacked on a side of the array substrate11in a step structure, and several memory strings (e.g., NAND strings) penetrate through and connect together the several memory layers13, such that the several memory strings and the several memory layers13jointly constitute a memory array with a storage function.

In some implementations, each memory layer13extends along a lateral direction parallel to the surface of the array substrate11; along a direction being gradually far away from and perpendicular to the array substrate11, every two adjacent ones of several memory layers13offset the same distance, and shrink by the same extension distance in the lateral direction. It can be understood that every two adjacent memory layers13may be flush at one end and shrink by the same distance at the other end in the lateral direction, and may also shrink by the same distance at the two ends respectively in the lateral direction. As shown inFIGS.1and2, in some examples of the present disclosure, every two adjacent memory layers13shrink by the same distance at the two ends respectively in the lateral direction. Each memory layer13may comprise one or more pairs of conductor/dielectric layers, each of which comprises a conductor layer and a dielectric layer, where specific structures, functions and materials of the conductor layers and the dielectric layers are the same as those of conductor layers and dielectric layers that are commonly used in the prior art, which is thus not repeated herein.

Each of the memory strings comprises a channel structure that extends along a direction perpendicular to the array substrate11and penetrates through several memory layers13, where the channel structure comprises channel holes filled with a semiconductor material (as a semiconductor channel) and a dielectric material (as a memory film). The memory film may comprise a tunneling layer, a charge trap/memory layer and a barrier layer, where the semiconductor channel, the tunneling layer, the charge trap/memory layer and the barrier layer are arranged sequentially along an outward direction from the center of the memory strings. It is to be noted that the specific structure, function and material of the memory strings are the same as those of the memory strings commonly used in the prior art, which is not repeated herein either.

In the three-dimensional memory device provided by the present disclosure, the respective memory array devices10of the first memory cell100and the second memory cell200each include several memory layers13. As mentioned above, in order to avoid too large area of the array substrate11, it is not necessary to stack too many memory layers13in the memory array device10of each memory cell. In the three-dimensional memory device provided by the examples of the present disclosure, the respective memory array devices10of the first memory cell100and the second memory cell200each include a preset number of layers of memory layers13, and the value of the preset number of layers is an integer greater than 0 and less than 500, e.g., 32, 64, 96 or 128 layers. The number of layers of the memory layers13in the respective memory array devices10of the first memory cell100and the second memory cell200may be the same or not the same. In some implementations, the number of layers of the memory layers13in the respective memory array devices10of the first memory cell100and the second memory cell200may be the same to be favorable to mass production of the first memory cell100and the second memory cell200in the same process.

It can be understood that, in each memory cell, the memory array device10and the CMOS device20may also comprise some other elements respectively, for example, a stack layer covering the memory array or the CMOS circuit, a bonding structure (including, but not limited to, a conductive structure, such as a wire, a plug, a solder bump or a pad or the like) disposed on an inner side surface of the stack layer, and several interconnection conductive channels penetrating through the stack layer and electrically connected with the bonding structure and the memory array or the CMOS circuit respectively, and the like, wherein the stack layer at least includes one insulation layer covering the memory array or the CMOS circuit. The specific structures and functions of the memory array device10and the CMOS device20are substantially the same as those of the memory array device and the CMOS device in the prior art, which is not repeated herein since they are unrelated to the improvement and innovation of the present disclosure.

As shown inFIGS.1and2, in some examples of the present disclosure, the interconnection channel30comprises first interconnection sub-channels31, second interconnection sub-channels32and an interconnection structure33electrically connected between the first interconnection sub-channels31and the second interconnection sub-channels32.

In some implementations, the first interconnection sub-channels31are disposed in the memory array device10and located on a side of the memory array device10provided with the memory array, and penetrate through the stack layers of the memory array device10; the second interconnection sub-channels32are disposed in the CMOS device20and located on a side of the CMOS device20provided with the CMOS circuit, and penetrate through the stack layers of the CMOS device20, wherein the second interconnection sub-channels32correspond to the first interconnection sub-channels31in position, and the second interconnection sub-channels32are electrically connected with the CMOS circuit at one end far away from the first interconnection sub-channels31. It is to be noted that the first interconnection sub-channels31and the second interconnection sub-channels32may be formed using conventional means in the prior art. For example, in some examples of the present disclosure, deep etching may be performed on the respective stack layers of the memory array device10and the CMOS device20to form filling channels penetrating through the stack layers, and then a conductive material is filled into the filling channels to form the first interconnection sub-channels31and the second interconnection sub-channel32respectively, where the conductive material includes, but is not limited to, tungsten, cobalt, copper, polysilicon, silicide or any combination thereof. The numbers of the first interconnection sub-channels31and the second interconnection sub-channels32may be set as one or more as long as the numbers of both of them are correspondingly equal, on which no limitation is imposed.

The interconnection structure33comprises first interconnection contacts and second interconnection contacts, where the first interconnection contacts are disposed on inner side (i.e., a side close to the CMOS device) surfaces of the stack layers of the memory array device10and correspondingly electrically connected with the first interconnection sub-channels31, and the second interconnection contacts are disposed on inner side (i.e., a side close to the memory array device) surfaces of the stack layers of the CMOS device20and correspondingly electrically connected with the second interconnection sub-channels32. The first interconnection contacts and the second interconnection contacts include, but are not limited to, conductive structures such as wires, plugs, solder bumps or pads or the like, and structural forms of the first interconnection contacts and the second interconnection contacts may be the same or not the same. As shown inFIGS.1and2, in some examples of the present disclosure, the first interconnection contacts are several solder bumps which are equal to the first interconnection sub-channels31in number and electrically connected with the first interconnection sub-channels31in a one-to-one correspondence manner; the second interconnection contacts are pads that are correspondingly electrically connected with the second interconnection sub-channels32on one side surface and provided with several pins on the other side surface, which correspond to the several solder bumps of the first interconnection contacts one-to-one. It can be understood that when the memory array device10and the CMOS device20of each memory cell are bonded in a face-to-face configuration, the first interconnection contacts and the second interconnection contacts are bonded at the same time to constitute the interconnection structure33such that the first interconnection sub-channels31are correspondingly electrically connected with the second interconnection sub-channels32through the interconnection structure33to constitute the interconnection channel30of the memory cell.

Referring toFIGS.1and2again, in some examples of the present disclosure, the first set of contacts40is disposed on an outer side (i.e., a side facing away from the memory array) of the array substrate11; the array substrate11is provided with several first conductive channels41in positions corresponding to the first interconnection sub-channels31in the memory array device10where the array substrate11is located; each first conductive channel41penetrates through two opposite sides of the array substrate11and is electrically connected with a corresponding first interconnection sub-channel31such that the first set of contacts40is electrically connected to the first interconnection sub-channels31through the first conductive channels41.

The first set of contacts40includes, but is not limited to, conductive structures such as wires, plugs, solder bumps or pads or the like. In some examples of the present disclosure, the first set of contacts40is pads that are electrically connected with the first conductive channels41.

The outer side surface of the array substrate11is further covered with a first bonding layer42, and the ends of the first conductive channels41far away from the first interconnection sub-channels31and the first set of contacts40are all embedded in the first bonding layer42. The first bonding layer42may be formed through one or more thin film deposition processes including but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The first bonding layer42comprises at least one dielectric layer made of a dielectric material including but not limited to, silicon oxide or silicon nitride, on which no limitation is imposed.

In some examples of the present disclosure, the first conductive channels41may be formed using conventional means such as a through-silicon-via technology, etc. In some implementations, deep etching is performed in positions of the first bonding layer42and the array substrate11corresponding to several first interconnection sub-channels31to form several first vertical channels penetrating through the first bonding layer42and the array substrate11, wherein each of the first vertical channels exposes at least part of a corresponding first interconnection sub-channel31; then a conductive material is filled within the first vertical channels until the conductive material exceeds the outer side surface of the array substrate11, so the first conductive channels41in contact with the first interconnection sub-channels31is formed, and the ends of the first conductive channels41far away from the first interconnection sub-channels31are located within the first bonding layer42. The leakage of the conductive material within the first vertical channels may be prevented in a manufacturing process of the first conductive channels41to avoid contaminating other manufacturing processes by covering the outer side surface of the array substrate11with the first bonding layer42.

In some examples of the present disclosure, after forming the first conductive channels41, the positions of the first bonding layer42corresponding to the first conductive channels41proceed to be etched to form openings exposing end portions of several first conductive channels41far away from the first interconnection sub-channels31, and then the first set of contacts40(i.e., the pads) is disposed within the openings such that the first set of contacts40is correspondingly electrically connected with the several first conductive channels41. In some examples of the present disclosure, after the first set of contacts40is disposed within the openings of the first bonding layer42, the dielectric material of the first bonding layer42may be filled within the openings again to cover the first set of contacts40in order to avoid exposure of the first set of contacts40, thereby preventing the first set of contacts40from damage before bonding connection with the corresponding second set of contacts50, which is favorable to improve the reliability of the bonding connection of the first set of contacts40with the corresponding second set of contacts50. Of course, in other examples, the first set of contacts40may also be exposed. It can be understood that when the first set of contacts40within the openings of the first bonding layer42is covered by the dielectric material, the first bonding layer42is required to be thinned or etched before the bonding connection of the first set of contacts40with the corresponding second set of contacts50, to remove the dielectric material in order to expose the first set of contacts40within the openings.

As shown inFIGS.1and2, in some examples of the present disclosure, the second set of contacts50of the second memory cell is disposed on an outer side (i.e., a side facing away from the CMOS circuit) of the CMOS substrate21of the second memory cell200. The CMOS substrate21is provided with several second conductive channels60in positions corresponding to the second interconnection sub-channels32in the CMOS device20where the CMOS substrate21is located. Each of the second conductive channels60penetrates through two opposite sides of the CMOS substrate21and is electrically connected with the second set of contacts50and the CMOS circuit of the CMOS device20respectively, so that the second set of contacts50is electrically connected to the CMOS circuit of the CMOS device20through the second conductive channels60. Of course, in other examples, the second conductive channels60may not correspond to the second interconnection sub-channels32as long as the second conductive channels60are electrically connected to the CMOS circuit of the CMOS device20.

The second set of contacts50includes, but is not limited to, conductive structures such as wires, plugs, solder bumps or pads or the like. In some examples of the present disclosure, the second set of contacts50are several solder bumps that are electrically connected with several second conductive channels60in a one-to-one correspondence manner.

The outer side surface of the CMOS substrate21of the second memory cell200is covered with a second bonding layer52, and the ends of the second conductive channels60far away from the second interconnection sub-channels32and the second set of contacts50are all embedded in the second bonding layer52. Similar to the first bonding layer42, the second bonding layer52may also be formed through one or more thin film deposition processes that include, but are not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof; likewise, the second bonding layer52includes at least one dielectric layer made of a dielectric material including but not limited to, silicon oxide or silicon nitride, on which no limitation is imposed.

In some examples of the present disclosure, the formation processes of the second conductive channels60and the first conductive channels41are substantially the same. In some implementations, deep etching may be first performed in positions of the second bonding layer52and the CMOS substrate21corresponding to several second interconnection sub-channels32to form several second vertical channels penetrating through the second bonding layer52and the CMOS substrate21, wherein each of the second vertical channels exposes at least part of a corresponding second interconnection sub-channel32; then a conductive material is filled within the second vertical channels until the conductive material exceeds the outer side surface of the CMOS substrate21, so the second conductive channels60in contact with the second interconnection sub-channels32is formed, such that the second conductive channels60are electrically connected with the CMOS circuit, and the ends of the second conductive channels60far away from the second interconnection sub-channels32are located within the second bonding layer52. The leakage of the conductive material within the second vertical channels may be prevented in a manufacturing process of the second conductive channels60to avoid contaminating other manufacturing processes by covering the outer side surface of the CMOS substrate21with the second bonding layer52. The conductive materials filled within the second vertical channels and the aforementioned first vertical channels include, but are not limited to, tungsten, copper, aluminum, polysilicon, silicide or any combination thereof, and may be the same or different.

It is to be noted that, in some examples of the present disclosure, a manufacturing process of the second set of contacts50is different from that of the first set of contacts40in that: after forming the second conductive channels60, one solder bump is directly disposed within each of the second vertical channels of the second bonding layer52, and several solder bumps within several second vertical channels constitute the second set of contacts50. In addition, like the first set of contacts40, the second set of contacts50may be covered or exposed in some examples of the present disclosure. In some implementations, the second set of contacts50may be covered to prevent the second set of contacts50from damage before bonding connection with the corresponding first set of contacts40, which is also favorable to improve the reliability of the bonding connection of the first set of contacts40with the corresponding second set of contacts50. It can be understood that when the solder bump within each of the second vertical channels of the second bonding layer52is covered by the dielectric material of the second bonding layer52(i.e., the second set of contacts50is covered), the second bonding layer52is required to be thinned or etched before the bonding connection of the first set of contacts40with the corresponding second set of contacts50, in order to remove the dielectric material within each of the second vertical channels to expose the solder bump within each second vertical channel, i.e., to expose the second set of contacts50so as to bond with the corresponding first set of contacts40.

It can be understood that, as shown inFIGS.1and2, for any two adjacent memory cells, after the first set of contacts40of a memory cell located below is correspondingly bonded with the second set of contacts50of the other memory cell located above, the respective CMOS circuits of the two adjacent memory cells are connected together, and the first bonding layer42of the memory cell located below is integrally attached to the second bonding layer52of the other memory cell located above.

Referring toFIGS.1and2again, in some examples of the present disclosure, the three-dimensional memory device further comprises an isolation layer300and an array pad400embedded in the isolation layer300. In some implementations, the isolation layer300covers a side of the outer second memory cell200facing away from the first memory cell100and the first set of contacts40of the outer second memory cell200. The isolation layer300is provided with an accommodation cavity in a position corresponding to the first set of contacts40of the outer second memory cell200, and the accommodation cavity corresponds to at least part of the first set of contacts40. The array pad400is disposed within the accommodation cavity of the isolation layer300and electrically connected with the first set of contacts40of the outer second memory cell200, and the three-dimensional memory device is electrically connected to the aforementioned external device through the array pad400.

The accommodation cavity of the isolation layer300may be formed by conventional means such as etching and the like, which is not repeated herein. The array pad400and the aforementioned solder bumps, pads and the like may be fabricated by conventional means in the prior art, which is thus not repeated.

It is to be noted that, similar to the first bonding layer42and the second bonding layer52, the isolation layer300may also be formed through one or more thin film deposition processes that include, but are not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof; the isolation layer300may also include at least one dielectric layer made of a dielectric material including but not limited to, silicon oxide or silicon nitride, on which no limitation is imposed.

The accommodation cavity of the isolation layer300may be a cavity with one end open to the outer second memory cell200, such that the array pad400is covered by the isolation layer300before being connected to the external device, thereby being favorable to protect the array pad400; however, when the array pad400is electrically connected to the external device, a position of the isolation layer300corresponding to the accommodation cavity is required to be thinned or etched to expose the array pad400. Of course, the accommodation cavity of the isolation layer300may also be a cavity structure with openings at both ends, such that the array pad400is exposed to facilitate direct electrical connection with the external device.

As shown inFIGS.1and2, in some examples of the present disclosure, the isolation layer300covers the outer side of the first bonding layer42of the outermost second memory cell200. It can be understood that both the isolation layer300and the first bonding layer42are formed by dielectric materials, and thus, the materials of the isolation layer300and the first bonding layer42may be the same or different. That means the isolation layer300and the first bonding layer42may be formed either in different thin film deposition processes or in the same thin film deposition process. In some implementations, the isolation layer300and the first bonding layer42are formed in different thin film deposition processes, such that the first set of contacts40and the array pad400may be disposed at different times in different thin film deposition processes, which is convenient in operation; furthermore, the first bonding layer42and the isolation layer300are formed at different times, and when the first bonding layer42and the isolation layer300are etched separately, the etching depth is small, thereby being favorable to improve the etching efficiency and precision.

As shown inFIGS.1and2, in some examples of the present disclosure, the three-dimensional memory device further comprises a protective layer500stacked on an outer side face of the isolation layer300, wherein the protective layer500covers the isolation layer300and is provided with an opening in a position corresponding to the array pad400, and at least part of the array pad400is exposed through the opening to connect to the external device. Of course, in other examples, the protective layer500may also cover the array pad400to protect the array pad400; however, when electrically connecting the array pad400with the external device, a position of the protective layer500corresponding to the array pad400is required to be thinned or etched to expose the array pad400.

By covering the isolation layer300with the protective layer500, the isolation layer300can be protected against damage, thereby preventing the array pad400from loosening due to the damage of the isolation layer300and ensuring the connection reliability of the array pad400.

The protective layer500may be made of a material such as silicon nitride or silicon oxide or the like, and the opening may be formed by conventional means such as etching and the like, which is not repeated herein.

Referring toFIG.3, the present disclosure further provides a manufacturing method of the above-mentioned three-dimensional memory device, which comprises:

S1, providing a first memory cell and a second memory cell, each of which comprise a first set of contacts, and a memory array device and a CMOS device that are stacked and electrically connected with each other, wherein the first set of contacts is disposed on a side of the memory array device facing away from the CMOS device and is electrically connected with the CMOS device.

In some implementations, referring toFIGS.4to7together, the manufacturing process of the memory cell is as follows:

The memory array device10and the CMOS device20are provided. As shown inFIG.4, the memory array device10comprises an array substrate11, a memory array disposed on an inner side (i.e., a side close to the CMOS device20) of the array substrate11, first interconnection sub-channels31disposed in the memory array, and first interconnection contacts331disposed on an inner side surface of the memory array device10and electrically connected with the first interconnection sub-channels31, wherein the memory array comprises several memory layers13in a step structure and several memory strings penetrating through and connecting together the several memory layers13; as shown inFIG.4, the CMOS device20comprises a CMOS substrate21, a CMOS circuit disposed on an inner side (i.e., a side close to the memory array device10) of the CMOS substrate21, second interconnection sub-channels32disposed on one side of the CMOS circuit and electrically connected with the CMOS circuit, and second interconnection contacts332disposed on an inner side surface of the CMOS device20and electrically connected with the second interconnection sub-channels32. It is to be noted that the specific features, functions and formation processes of the array substrate11, the several memory layers13, the several memory strings, the CMOS substrate21, the first interconnection sub-channels31, the second interconnection sub-channels32, the first interconnection contacts331and the second interconnection contacts332may refer to the corresponding contents in the above-mentioned three-dimensional memory device, which is not repeated here. In addition, the memory array device10and the CMOS device20further comprise some other elements respectively, and the specific structures and functions of the memory array device10and the CMOS device20are substantially the same as those of the existing memory array device and CMOS device, which is not repeated either herein since they are unrelated to the improvement and innovation of the present disclosure.

The memory array device10and the CMOS device20are bonded face-to-face. As shown inFIG.5, after alignment bonding of the memory array device10and the CMOS device20, the aforementioned first interconnection contacts331and the second interconnection contacts332(as shown inFIG.4) are also bonded to constitute an interconnection structure33, such that the aforementioned first interconnection sub-channels31are correspondingly electrically connected with the second interconnection sub-channels32through the interconnection structure33, thereby constituting an interconnection channel30of the memory cell that is electrically connected with the first set of contacts40and the CMOS device20of the memory cell where the interconnection channel30is located, so that the first set of contacts40is electrically connected to the CMOS device20through the interconnection channel30.

As shown inFIG.6, an outer side (i.e., a side facing away from the memory array) of the array substrate11of the memory array device10is thinned. The means of thinning include, but are not limited to, mechanical polishing, wet/dry etching, chemical mechanical polishing, or any combination thereof.

The first set of contacts40are formed on the outer side of the memory array device10, so that the first set of contacts40is electrically connected to the first interconnection sub-channels31. As shown inFIG.7, in some examples of the present disclosure, the outer side surface of the array substrate11is covered with a first bonding layer42; first conductive channels41penetrating through the array substrate11and electrically connected with the first interconnection sub-channels31may be formed by conventional technical means; the ends of the first conductive channels41far away from the first interconnection sub-channels31and the first set of contacts40are all embedded in the first bonding layer42; and the first set of contacts40are electrically connected to the first interconnection sub-channels31through the first conductive channels41. Likewise, the specific features, functions or formation processes of the first bonding layer42and the first conductive channels41may refer to the corresponding contents in the above-mentioned three-dimensional memory device, which is not repeated here.

The first memory cell100and the same portions of the second memory cell200as the first memory cell100may be fabricated through the above-described operations.

S2, thinning a side of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell. That is, a side of the CMOS substrate of the second memory cell facing away from the CMOS circuit is thinned, and the means of thinning include, but are not limited to, mechanical polishing, wet/dry etching, chemical mechanical polishing, or any combination thereof.

Referring toFIGS.8and9together, in some examples of the present disclosure, before S2, the manufacturing method of the three-dimensional memory device further comprises: providing a carrier, and attaching the carrier to a side of the memory array device of the second memory cell facing away from the CMOS device of the second memory cell, so that the carrier covers the side of the memory array device of the carried second memory cell facing away from the CMOS device of the second memory cell and the first set of contacts of the second memory cell.

In some implementations, as shown inFIGS.8and9, first the second memory cell200is turned upside down, such that the memory array device10of the second memory cell200is at the bottom; then the carrier600is attached to the outer side (i.e., a side facing away from the CMOS device20of the second memory cell200) of the memory array device10of the second memory cell200, so that the carrier600covers the outer side of the memory array device10of the carried second memory cell200and the first set of contacts40; and finally, the CMOS substrate21of the second memory cell200is thinned. By attaching the carrier600to the outer side of the memory array device10of the second memory cell200, the carrier600can play a role for supporting the second memory cell200, thereby being favorable to reduce and even avoid deformation of the second memory cell200in a process of transportation or thinning of the CMOS substrate21.

The carrier600may be made of glass, sapphire or a semiconductor material, on which no limitation is imposed.

Attaching the carrier600to the outer side of the memory array device10of the second memory cell200comprises:

First, coating at least one of a side of the carrier600facing the second memory cell200and the outer side of the memory array device10of the second memory cell200with any bonding adhesive of a thermal curing adhesive, an ultraviolet irradiation curing adhesive, a thermal decomposition adhesive or a laser decomposition adhesive. In some implementations, both the side of the carrier600facing the second memory cell200and the outer side of the memory array device10of the second memory cell200are coated with the bonding adhesive to enhance the adhesion between the carrier600and the outer side of the memory array device10of the second memory cell200.

Then, the carrier600is bonded to the outer side of the memory array device10of the second memory cell200through a temporary or a permanent bonding process. The temporary bonding process refers to a process means that is used to bond the carrier600to the outer side of the memory array device10of the second memory cell200and can easily remove the carrier600from the outer side of the memory array device10as required, wherein the carrier600is easy to remove. The permanent bonding process refers to a process means that is used to bond the carrier600to the outer side of the memory array device10of the second memory cell200and may remove the carrier600from the outer side of the memory array device10by additionally applying a large external force, wherein the bonding connection between the carrier600and the memory array device10of the second memory cell200is firm.

It can be understood that, in some examples of the present disclosure, the outer side of the memory array device10of the second memory cell200is covered with the first bonding layer42, and thus, in some implementations, the carrier600may be bonded to the outer side of the first bonding layer42.

S3, forming a second set of contacts on a side of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell, wherein the second set of contacts is electrically connected with the CMOS device of the second memory cell.

Referring toFIGS.10and11together, in some examples of the present disclosure, S3of the manufacturing method of the three-dimensional memory device comprises:forming vias (i.e., the aforementioned second vertical channels) penetrating through the CMOS substrate21on the CMOS substrate21of the second memory cell200, wherein the vias expose at least a part of the interconnection channel30(i.e., at least a part of the aforementioned second interconnection sub-channels32) of the second memory cell200;filling a conductive medium within the vias to form conductive channels (i.e., the aforementioned second conductive channels60) that are electrically connected with the interconnection channel30of the second memory cell200; andforming a second set of contacts50of the second memory cell200from ends of the conductive channels far away from the interconnection channel30of the second memory cell200(i.e., ends of the second conductive channels60far away from the second interconnection sub-channels32), so that the second set of contacts50is electrically connected with the interconnection channel30of the second memory cell200through the conductive channels.

As shown inFIGS.10and11, before forming the second set of contacts50, the outer side (i.e., the side facing away from the CMOS circuit) surface of the CMOS substrate21of the second memory cell200is first coated with a second bonding layer52; then, the second conductive channels60penetrating through the CMOS substrate21and electrically connected with the second interconnection sub-channels32may be formed by conventional technical means; the ends of the second conductive channels60far away from the second interconnection sub-channels32and the second set of contacts50are all embedded in the second bonding layer52; and the second set of contacts50is electrically connected to the CMOS circuit of the CMOS device20through the second conductive channels60, and electrically connected to the second interconnection sub-channels32of the interconnection channel30at the same time. Likewise, the specific features, functions or formation processes of the second bonding layer52and the second conductive channels60may refer to the corresponding contents in the above-mentioned three-dimensional memory device, which is not repeated here.

After forming the second set of contacts50on the outer side of the CMOS device20of the second memory cell200(i.e., a side facing away from the memory array device10, i.e., the outer side of the CMOS substrate), the manufacturing method of the three-dimensional memory device further comprises S4: stacking the second memory cell on a side of the memory array device of the first memory cell facing away from the CMOS device of the first memory cell, and bonding the memory array device of the first memory cell with the CMOS device of the second memory cell, so that the first set of contacts of the first memory cell is correspondingly electrically connected with the second set of contacts of the second memory cell.

In some implementations, referring toFIG.12, after the carrier600is bonded to the outer side of the memory array device10of the second memory cell200, the second memory cell200is turned upside down, so that the CMOS device20of the second memory cell200faces the memory array device10of the first memory cell100; then the CMOS device20of the second memory cell200is face-to-face bonded with the memory array device10of the first memory cell100, so that the first set of contacts40of the first memory cell100is correspondingly electrically connected with the second set of contacts50of the second memory cell200and then the first memory cell100electrically connects with the second memory cell200through the corresponding first set of contacts40, the second set of contacts50and the respective interconnection channel30of each memory cell. At this time, the first bonding layer42of the first memory cell100is attached to the second bonding layer52of the second memory cell200.

Referring toFIG.13, in some examples of the present disclosure, when the carrier600is bonded to the outer side of the memory array device10of the second memory cell200, after stacking the second memory cell200onto the first memory cell100and bonding the CMOS device20of the second memory cell200with the memory array device10of the first memory cell100, the manufacturing method of the three-dimensional memory device further comprises: removing the carrier600to expose the first set of contacts40of the second memory cell200.

Referring toFIG.1, in some examples of the present disclosure, after bonding the CMOS device20of the second memory cell200with the memory array device10of the first memory cell100and exposing the first set of contacts40of the second memory cell200, the manufacturing method of the three-dimensional memory device further comprises:forming an isolation layer300on a side of the memory array device10of the outer second memory cell200facing away from the CMOS device20of the outer second memory cell200, the isolation layer300covering the side of the memory array device10of the outer second memory cell200facing away from the CMOS device20of the outer second memory cell200and the first set of contacts40of the outer second memory cell200, wherein the outer second memory cell200is a second memory cell200that is stacked on the first memory cell100and farthest away from the first memory cell100along a stacking direction;disposing an array pad400within the isolation layer300, and correspondingly electrically connecting the array pad400with the first set of contacts40of the outer second memory cell; andforming a protective layer500with an opening on a side of the isolation layer300facing away from the outer second memory cell200, so that the protective layer500covers the isolation layer300and the opening exposes the array pad400,wherein the isolation layer300covers a side of the first bonding layer42of the outer second memory cell200facing away from the array substrate11; the exposed array pad400is used to connect to an external device (e.g., a control device or a drive circuit, etc.); the protective layer500is used to protect the isolation layer300against damage to ensure the connection reliability of the array pad400; and the specific features, functions or formation processes of the isolation layer300, the array pad400and the protective layer500may refer to the corresponding contents in the above-mentioned three-dimensional memory device, which is not repeated here.

In some examples of the present disclosure, through the above-mentioned operations, the first memory cell100and the second memory cell200may be stacked to constitute the three-dimensional memory device1000(as shown inFIG.1) with a high storage density, without the necessity to stack too many memory layers13in the memory array device10of each memory cell, such that the area of the array substrate11of each memory cell is not too large, which is favorable to dispose the array substrate11and the CMOS substrate21of each memory cell at a proper area ratio, and the idle utilization space in each memory cell can be further reduced and the space utilization rate of three-dimensional memory device can be increased.

In some implementations, in the three-dimensional memory device1000, the respective memory array devices10of the first memory cell100and the second memory cell200each include a preset number of layers of memory layers13, and the value of the preset number of layers is an integer greater than 0 and less than 500, e.g., 32, 64, 96 or 128 layers. The number of layers of the memory layers13in the respective memory array devices10of the first memory cell100and the second memory cell200may be the same or not the same. In some implementations, the number of layers of the memory layers13in the respective memory array devices10of the first memory cell100and the second memory cell200may be the same to be favorable to mass production of the first memory cell100and the second memory cell200in the same process.

Referring toFIG.2, in some other examples of the present disclosure, the number of the second memory cells200may be set as multiple, and the manufacturing method of the three-dimensional memory device comprises:stacking one of second memory cells200on a side of the memory array device10of the first memory cell100facing away from the CMOS device20of the first memory cell100, and bonding a CMOS device20of the one of the second memory cells200to the memory array device10of the first memory cell100, so that a second set of contacts50of the one of the second memory cells200is correspondingly electrically connected with the first set of contacts40of the first memory cell100; andstacking another one of the second memory cells200on a side of a memory array device10of an outer second memory cell200facing away from a CMOS device20of the outer second memory cell200, and bonding a CMOS device20of the another one of second memory cells200with the memory array device10of the outer second memory cell200, so that a first set of contacts40of the outer second memory cell200is correspondingly electrically connected with a second set of contacts50of the another one of the second memory cells200, and repeating this operation until multiple second memory cells200are sequentially stacked on the first memory cell100, wherein the outer second memory cell200is a second memory cell200that is stacked on the first memory cell100and farthest away from the first memory cell100along the stacking direction.

It is to be noted that, in order to avoid the deformation of the second memory cells200, a side of the memory array device10of each second memory cell200facing away from the CMOS device20may be bonded with a carrier600, and therefore, removing the carrier600is required to be performed before bonding each second memory cell200with the other memory cells (the first memory cell100or another second memory cell200). The carrier600bonded to the sides of the memory array devices10of the multiple second memory cells200may be the same carrier600, that is, after a carrier600is removed from the memory array device10of one second memory cell200, the carrier600is again bonded to the outer side of the memory array device10of a next second memory cell200to be stacked, and the carrier600is used repeatedly, which can decrease the number of the carriers600and reduce the cost. Of course, the outer side of the memory array device10of each second memory cell200may be bonded with a different carrier600.

In some other examples of the present disclosure, through the above-mentioned operations, the first memory cell100and multiple second memory cells200may be stacked sequentially to constitute a three-dimensional memory device1000b(as shown inFIG.2); the number of memory cells of the three-dimensional memory device1000bis more as compared with the three-dimensional memory device1000; therefore, the three-dimensional memory device1000bhas a higher storage density, and it is also not necessary to stack too many memory layers13in the memory array device10of each memory cell of the three-dimensional memory device1000b, thereby increasing the space utilization rate of the three-dimensional memory device1000b.

In the examples of the present disclosure, in a fabrication process of the three-dimensional memory device, a method used for bonding between the memory array device10and its CMOS device20of the first memory cell100, bonding between the memory array device10and its CMOS device20of the second memory cell200, bonding between the memory array device10of the first memory cell100and the CMOS device20of the second memory cell200, and bonding between the memory array device10of the second memory cell200and the CMOS device20of the other second memory cell200includes an Xtacking bonding process. The Xtacking bonding process refers to alignment bonding of bonding structures between different devices in the same process to achieve electrical connection of the two devices. The use of the Xtacking bonding process is favorable to select a more advanced manufacturing process to manufacture the memory array device and the CMOS device respectively, and reduce the complexity of a manufacturing procedure, so that the three-dimensional memory device obtains a higher I/O transmission speed, a higher density and a smaller volume.

The present disclosure further provides a three-dimensional memory that comprises any of the above-mentioned three-dimensional memory devices. The three-dimensional memory has the advantages of high storage density, high space utilization rate and the like of the above-mentioned three-dimensional memory devices and also has other structure features and functions of the above-mentioned three-dimensional memory devices, which is not repeated here.

One aspect of the present disclosure provides a three-dimensional memory device comprising at least two memory cells that are stacked sequentially, wherein the at least two memory cells include a first memory cell and at least one second memory cell stacked on the first memory cell, and each memory cell comprises: a memory array device and a CMOS device that are stacked and electrically connected with each other; and a first set of contacts disposed on a side of the memory array device facing away from the CMOS device, and electrically connected with the CMOS device; wherein the second memory cell further comprises a second set of contacts that is disposed on a side of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell, and is electrically connected with the CMOS device of the second memory cell; the memory array device of the first memory cell is bonded with the CMOS device of an adjacent second memory cell, and the first set of contacts of the first memory cell is correspondingly electrically connected with the second set of contacts of the adjacent second memory cell; when there is one second memory cell, the second memory cell is an outer second memory cell stacked on the first memory cell, and the first set of contacts of the outer second memory cell is used to connect to an external device; when there are multiple second memory cells, the multiple second memory cells are sequentially stacked on the first memory cell; for two adjacent ones of the second memory cells, the first set of contacts of a second memory cell close to the first memory cell is correspondingly electrically connected with the second set of contacts of a second memory cell far away from the first memory cell; a second memory cell farthest away from the first memory cell along a stacking direction is defined as an outer second memory cell; and the first set of contacts of the outer second memory cell is used to connect to an external device.

Another aspect of the present disclosure further provides a manufacturing method of a three-dimensional memory device, which comprises: providing a first memory cell and a second memory cell each comprising a first set of contacts, and a memory array device and a CMOS device that are stacked and electrically connected with each other, wherein the first set of contacts is disposed on a side of the memory array device facing away from the CMOS device and electrically connected with the CMOS device; thinning a side of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell; forming a second set of contacts on the side of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell, wherein the second set of contacts is electrically connected with the CMOS device of the second memory cell; and stacking the second memory cell on a side of the memory array device of the first memory cell facing away from the CMOS device of the first memory cell, and bonding the memory array device of the first memory cell with the CMOS device of the second memory cell, so that the first set of contacts of the first memory cell is correspondingly electrically connected with the second set of contacts of the second memory cell.

Yet another aspect of the present disclosure further provides a three-dimensional memory comprising the above-mentioned three-dimensional memory device.

Although the examples of the present disclosure have been illustrated and described, those of ordinary skill in the art may understand that various changes, modifications, substitutions and variations may be made to these examples without departing from the principles and purposes of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.