Vertical type semiconductor memory apparatus and fabrication method thereof

Semiconductor memory apparatus and a method of fabricating the same are provided. The semiconductor memory apparatus includes a semiconductor substrate in which a cell area and a peripheral area are defined, a plurality of pillars formed in the a cell area of the semiconductor substrate to a first depth, a stepped part formed in the peripheral area to a height corresponding to the first depth, a recessed part formed in the stepped part to a second depth, and a core switching device formed in the recessed part.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. 119(a) to Korean application number 10-2013-0071498, filed on Jun. 21, 2013, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments of the inventive concept relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus and a fabrication method thereof.

2. Related Art

With miniaturization of digital apparatuses, high integration and miniaturization of semiconductor memory apparatuses are required. In particular, portable digital apparatuses have been increasingly distributed, and ultra-high integration, ultra-high speed, and ultra-low power of semiconductor memory apparatuses embedded in a limited size are required to process data in the limited size with higher speed.

To meet this demand, studies on vertical memory devices have been actively made.

FIG. 1is a cross-sectional view illustrating a structure of a general vertical memory apparatus.

Referring toFIG. 1, a semiconductor substrate101in which a cell area C and a peripheral area P are defined by a device isolation layer103is provided.

A vertical memory device may be formed in the cell area C. For example, a cell switching device SW_C including a pillar201protruding perpendicular to a surface of the semiconductor substrate101, and a gate insulating layer203and a gate conductive layer205surrounding a circumference of the pillar201are formed. A lower electrode209and a data storage unit211are formed to extend from an upper surface of the pillar201to a protrusion direction of the pillar201. The data storage unit211may be formed using a material of which a resistance value is to be switched according to a voltage or a current supplied to the data storage unit211. An upper electrode213is formed on an upper surface of the data storage unit211. The upper electrode213may be coupled to a conductive line (not shown) through a metal contact215. A metal silicide layer207may be additionally formed to improve between an interface resistance between the cell switching device SW_C and the lower electrode209.

A core switching device SW_P may be formed in the peripheral area P.

The core switching device SW_P may have a structure in which a sidewall of each of a plurality of conductive stacks is surrounded by a gate insulating layer, and a hard mask303configured to protect the conductive stacks is formed on the core switching device SW_P. The core switching device SW_P may be coupled to an interconnection layer307through a junction contact305, and the interconnection layer307may be coupled to each of conductive lines (not shown) through a metal contact309.

It may be seen fromFIG. 1that the vertical cell switching device SW_C formed in the cell area C may be formed by allowing the substrate to be recessed to a predetermined depth, forming the pillar201, and forming a gate conductive layer205to surround the circumference of the pillar201.

When the pillar201is formed in the cell area C, the peripheral area P is not recessed and an initial height of the peripheral area P is kept as it is. Thus, a height of an upper surface1018of the semiconductor substrate101in the peripheral area P may be higher than a height of an upper surface101A of the semiconductor substrate101in the cell area C.

When the semiconductor device is fabricated on the stepped semiconductor substrate, a height of the memory device formed in the cell area C is determined according to a height of the core switching device SW_P formed in the peripheral area P.

The core switching device SW_P is formed high in a multi-layered structure. The cell switching device SW_C is formed in the cell area C, and the core switching device SW_P is formed in the peripheral area P that is higher than the cell area C. Then, the interlayer insulating layer107is formed in the semiconductor substrate including the core switching device SW_P and a planarization process is performed on the interlayer insulating layer. However, since the core switching device SW_P is previously formed higher than an upper surface of the cell area C, it is difficult to precisely control the planarization process due to a large difference of height between the cell area C and the peripheral area P.

To form the lower electrode209, a lower electrode contact hole is formed by patterning the interlayer insulating layer107formed in the cell area C. However, since a height of the interlayer insulating layer107depends on the height of the core switching device SW_P, an etching process of forming the lower electrode contact hole having a large aspect ratio is required. Further, since a process of gap-filling a lower electrode material in the lower electrode contact hole having the large aspect ratio is necessary, a level of difficulty in the process is increased and it is difficult to ensure yield.

Further, since a height of the lower electrode209formed in the cell area C depends on the height of the core switching device SW_P, there is a limitation in miniaturization of the semiconductor memory device.

SUMMARY

According to an aspect of an exemplary embodiment of the present invention, there is provided a semiconductor memory apparatus. The semiconductor memory apparatus may include a semiconductor substrate in which a cell area and a peripheral area are defined, a plurality of pillars formed in the cell area of the semiconductor substrate to a first depth, a stepped part formed in the peripheral area to a height substantially the same as the first depth, a recessed part formed in the stepped part to a second depth, and a core switching device formed in the recessed part.

According to an aspect of another exemplary embodiment of the present invention, there is provided a method of fabricating a semiconductor memory apparatus. The method of fabricating a semiconductor memory apparatus may include defining a cell area and a peripheral area in a semiconductor substrate, forming a plurality of pillars in the cell area by recessing a predetermined portion of the semiconductor substrate in the cell area to a first depth, forming a recessed part in the peripheral area by recessing a predetermined portion of the semiconductor substrate in the peripheral area to a second depth, and forming a core switching device in the recessed part.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments will be described in greater detail with reference to the accompanying drawings.

Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of exemplary embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing. In the drawings, lengths and sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements. It is also understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other or substrate, or intervening layers may also be present. It is also understood that in this specification, “connected/coupled” refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.

FIG. 2is a cross-sectional view illustrating a structure of a vertical memory apparatus according to an embodiment of the present invention.

Referring toFIG. 2, a semiconductor substrate401that is divided into a cell area C and a peripheral area P by a device isolation layer403is provided.

The semiconductor substrate401in the cell area C is recessed to a first depth, and a memory device600is formed on the recessed surface401A of the semiconductor device in the cell area C.

The semiconductor substrate401in the peripheral area P may protrude from the recessed surface401A by a first height substantially the same as the first depth. A core switching device SW_P1is formed in a portion (a recessed part)405in which a predetermined region of the protruding surface401B of the semiconductor substrate401in the peripheral area P is recessed to a second depth. Here, the first depth is the same as or different from the second depth.

The core switching device SW_P1may include a gate insulating layer501formed on a sidewall of the recessed part405to a predetermined height, and a gate conductive layer503filling the recessed part in which the gate insulating layer is formed. The gate conductive layer503may include a stacking structure in which a plurality of conductive layers are stacked. A height of the core switching device SW_P1may be lower than that of the recessed part405.

A hard mask505configured to protect the gate conductive layer503is formed on the core switching device SW_P1. Although not shown, a junction region may be formed in the semiconductor substrate401in an outer side of the recessed part405in which the core switching device SW_P1is formed. The junction region and the core switching device SW_P1may be coupled to an interconnection layer509through a junction contact507, and the interconnection layer509may be coupled to each of conductive lines (not shown) through a metal contact511.

The reference numeral407denotes an interlayer insulating layer.

The semiconductor memory apparatus according to an embodiment of the inventive concept forms the core switching device SW_P1in the recessed part405formed in the semiconductor substrate401of the peripheral area P. Therefore, a substantial height of the core switching device SW_P1may be lowered, and thus a height of the memory device600formed in the cell area C may be lowered.

FIG. 3is a cross-sectional view illustrating a structure of a vertical memory device according to another embodiment of the present invention.

FIG. 3illustrates the semiconductor memory device in which a vertical memory device is formed in a cell area C.

Referring toFIG. 3, a vertical cell switching device SW_C1is formed on a surface401A of a semiconductor substrate401in the cell area C, recessed to a predetermined first depth. A lower electrode609and a data storage unit611are formed on the cell switching device SW_C1. An upper electrode613is formed on an upper surface of the data storage unit611, and the upper electrode613may be coupled to a conductive line (not shown) through a metal contact615. A metal silicide layer607may be additionally formed to improve an interface resistance between the cell switching device SW_C1and the lower electrode609.

A structure of the peripheral area P inFIG. 3is the same as the structure of the peripheral area P inFIG. 2, and the reference numerals407A,407B, and407C denote interlayer insulating layers.

It may be seen fromFIG. 3that a core switching device SW_P1of the peripheral area P is formed in the recessed part405, in a buried form. Therefore, the lower electrode609may be formed without being affected by a height of the core switching device SW_P1. When compared withFIG. 1, it may be seen that a height of the lower electrode609is considerably lowered, and thus the semiconductor memory apparatus may be miniaturized.

The cell switching device (SW_C1) may be formed in a vertical surround gate type in which a circumference of the pillar601is surrounded by the gate insulating layer603and the gate conductive layer605, from a bottom of the pillar601to a predetermined height.

The data storage unit611may be formed using a material of which a resistance value may be switched according to a voltage or a current supplied thereto. For example, the material includes a phase-change material, a transition metal oxide, perovskite, a polymer, or the like, but the material is not limited thereto.

FIGS. 4 to 8are cross-sectional views illustrating a method of fabricating a vertical memory apparatus according to an embodiment of to the present invention.

As illustrated inFIG. 4, a device isolation layer703is formed in a semiconductor substrate701to define a cell area C and a peripheral area P. Predetermined portions of the semiconductor substrate in the cell area C and the peripheral area P are recessed. Thus, a pillar705protruding vertically from a surface701A of the semiconductor substrate701in the cell area C is formed in the cell area C. A recessed part709is formed to a predetermined depth from a surface701B of the semiconductor substrate in a stepped part707of the peripheral area P. A height from the surface701A of the semiconductor substrate in the cell area C to an upper surface of the pillar705may be the same as or different from a height from a bottom701C of the recessed part709to the surface701B of the semiconductor substrate in the peripheral area P. In other words, a height H1of the pillar705may be the same as or different from a height H2, which is also referred to as a depth of the recessed part709or a height of the stepped part707.

The pillar705and the recessed part709may be simultaneously formed or formed through separate processes. The process order of the pillar705and the recessed part709may be changed according to a size of the device, and a degree of maturity or difficulty in the processes.

As illustrated inFIG. 5, a cell switching device SW_C2is formed in the cell area C and a core switching device SW_P2is formed in the peripheral area P.

To form the core switching device SW_P2, a core gate insulating layer717is formed on an inner sidewall of the recessed part709to a predetermined height, and a core gate conductive layer719is buried in the recessed part709in which the core gate insulating layer717is formed. A hard mask721may be formed on the core switching device SW_P2in the recessed part709.

To form the cell switching device SW_C2, a cell gate insulating layer713and a cell gate conductive layer715may be formed on an outer sidewall of the pillar705to a predetermined height.

The formation order of the core switching device SW_P2and the cell switching device SW_C2may be selected according to a size of the device, and a degree of maturity or difficulty in the processes.

The core gate conductive layer719and the cell gate conductive layer715may be formed using the same material or different materials. When the core gate conductive layer719and the cell gate conductive layer715are formed of different materials, the core gate conductive layer719and the cell gate conductive layer715may be implemented to have different characteristics. When the core gate conductive layer719and the cell gate conductive layer715are formed of the same material, the number of processes may be reduced.

Each of the core gate conductive layer719and the cell gate conductive layer715may be formed of, for example, any material selected from the group including tungsten (W), titanium (Ti), titanium silicide (TiN), silicide (WSiX), cobalt (Co), nickel (Ni), nickel platinum (NiPt) and iron (Fe). In particular, the core gate insulating layer719may be implemented by forming a single layer or a composite layer of the materials or by stacking at least two of the materials in a stacked form.

After the core switching device SW_P2is formed, a junction region may be formed in the stepped part707in an outer side of the recessed part709to a predetermined depth. Similarly, after the cell switching device SW_C2is formed, a junction region may be formed in the semiconductor substrate of an outer side of the pillar705and in an upper portion of the pillar705.

As illustrated inFIG. 6, a first interlayer insulating layer723is formed on the semiconductor substrate including the cell switching device SW_C2and the core switching device SW_P2, and then planarized to expose the surface701B of the semiconductor substrate in the peripheral area P and an upper portion of the stepped part707. A lower electrode725and a data storage unit727are formed on a pillar in the cell area C. The data storage unit727may be formed using a material of which a resistance value is to be changed according to a voltage or a current supplied to the data storage unit727. For example, the data storage unit727may be formed using a phase-change material, a transition metal oxide, perovskite, a polymer, or the like, but the material is not limited thereto.

Although not shown, before the lower electrode725is formed, a metal silicide layer may be additionally formed to improve an interface resistance between the cell switching device SW_C2and the lower electrode725.

As illustrated inFIG. 7, a second interlayer insulating layer729is formed on the semiconductor substrate including the data storage unit727, and then planarized to expose a top of the data storage unit727. A junction contact731electrically coupled to the junction region and the gate conductive layer719in the peripheral area P is formed in the peripheral area P.

As illustrated inFIG. 8, an upper electrode733is formed on the data storage unit727of the cell area C, and an interconnection layer737is formed on the junction contact of the peripheral area P.

The upper electrode733may be coupled to a conductive line (not shown) through a metal contact (not shown) formed thereon through a subsequent process. Further, the interconnection layer735may be coupled to each of conductive lines (not shown) through a metal contact (not shown) formed thereon.

In this way, the recessed part709is formed in the stepped part707of the peripheral area, and the core switching device SW_P2is formed in the recessed part709. Since the substantial height of the core switching device SW_P2formed in the bottom701C of the recessed part709of the semiconductor substrate may be reduced, the height of the memory device formed in the cell area C, specifically, the height of the lower electrode725, may be reduced. Accordingly, a degree of difficulty in a process for formation of the lower electrode725may be reduced, and an area occupied with the peripheral area P may be reduced so that high integration and miniaturization of the memory device may be further achieved.

In the memory apparatus illustrated inFIG. 1, the lower electrode209is formed to a height similar to that of the core switching device SW_P is formed. However, in the memory apparatus illustrated inFIG. 3or8, the heights of the lower electrodes609and725are determined regardless of the heights of the core switching devices SW_P1and SW_P2, respectively. Since it is not necessary to form the lower electrodes609and725with a large height, the heights of the lower electrodes may be determined freely according to characteristics of the device to be implemented.

Accordingly, the total height of the device may be reduced, and heights in the cell area C and the peripheral area P may be substantially the same after the cell switching devices SW_C1and SW_C2and the core switching device SW_P1and SW_P2are formed. A process of depositing and planarizing the interlayer insulating layer and a process of forming the lower electrode contact hole pattern may be easily performed in a subsequent process after the cell switching devices SW_C1; and SW_C2and the core switching device SW_P1and SW_P2are formed.

The example in which the vertical memory device is formed in the cell area has been described, but the inventive concept is not limited thereto. The inventive concept may be applied to a memory apparatus in which a memory device is formed after a recess is formed in the cell area C of the semiconductor substrate, a memory apparatus in which a memory device is formed in a buried type.

The above embodiment of the present invention is illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the embodiment described herein. Nor is the invention limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.