CHIP-SUBSTRATE COMPOSITE SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer. The metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate. The method further includes providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer. The front side of the semiconductor wafer is bonded to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is connected to the plurality of electrodes. The composite wafer is separated into composite chips.

TECHNICAL FIELD

This disclosure relates generally to the field of semiconductor devices, and in particular to the field of packaging semiconductor chips.

BACKGROUND

Semiconductor device manufacturers are constantly striving to increase the performance of their products, while decreasing their cost of manufacture. A cost and device performance sensitive area in the manufacture of a semiconductor device is packaging the semiconductor chip. Packaging involves, inter alia, forming an electrical interconnect from chip electrodes (die pads) to package terminals. The interconnect technology should provide for high electrical and thermal performance and reliability of the semiconductor device. Further aspects aim at cost efficient manufacturing processes and customer benefits in view of product versatileness and package mount ability.

SUMMARY

According to an aspect of the disclosure a method of manufacturing a semiconductor device comprises forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer. The metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate wafer. The method further comprises providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer. The front side of the semiconductor wafer is bonded to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is connected to the plurality of electrodes. The composite wafer is separated into composite chips.

According to another aspect of the disclosure a semiconductor device comprises a semiconductor chip comprising a front side and a backside, wherein an electrode is disposed on the front side of the semiconductor chip. The semiconductor device further comprises a dielectric inorganic substrate comprising a pattern of metal structures which are accommodated in recesses of the dielectric inorganic substrate and at least partly connect through the dielectric inorganic substrate. The front side of the semiconductor chip is attached to the dielectric inorganic substrate and the electrode is connected to the pattern of metal structures.

DETAILED DESCRIPTION

As used in this specification, the terms “electrically connected” or “connected” or similar terms are not meant to mean that the elements are directly contacted together; intervening elements may be provided between the “electrically connected” or “connected” elements, respectively. However, in accordance with the disclosure, the above-mentioned and similar terms may, optionally, also have the specific meaning that the elements are directly contacted together, i.e. that no intervening elements are provided between the “electrically connected” or “connected” elements, respectively.

Further, the words “over” or “beneath” with regard to a part, element or material layer formed or located “over” or “beneath” a surface may be used herein to mean that the part, element or material layer be located (e.g. placed, formed, arranged, deposited, etc.) “directly on” or “directly under”, e.g. in direct contact with, the implied surface. The word “over” or “beneath” used with regard to a part, element or material layer formed or located “over” or “beneath” a surface may, however, either be used herein to mean that the part, element or material layer be located (e.g. placed, formed, arranged, deposited, etc.) “indirectly on” or “indirectly under” the implied surface, with one or more additional parts, elements or layers being arranged between the implied surface and the part, element or material layer.

Referring toFIG. 1, at S1a plurality of patterns of metal structures is formed in a dielectric inorganic substrate wafer. The metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate wafer.

At S2a semiconductor wafer comprising a front side and a backside is provided. The semiconductor wafer may, e.g., be a processed wafer in which integrated devices have already been formed. The semiconductor wafer may, e.g., be a fully front-end-of-line (FOEL) processed semiconductor wafer. A plurality of electrodes (die pads) is disposed on the front side of the semiconductor wafer.

At S3the front side of the semiconductor wafer is bonded to the dielectric inorganic substrate wafer to form a composite wafer. The plurality of patterns of metal structures is connected to the plurality of electrodes.

At S4the composite wafer is then separated into composite chips. As will be described further below in more detail, the composite chips may optionally be embedded in an encapsulant.

FIG. 2Aillustrates a schematic cross-sectional view of an exemplary semiconductor device200. The semiconductor device200may, e.g., correspond to a composite chip as produced at S4inFIG. 1by separating the composite wafer into composite chips.

The semiconductor device200includes a semiconductor chip210. The semiconductor chip210has a front side210A and a backside210B. At least one electrode (die pad)220is disposed on the front side210A of the semiconductor chip210.

A dielectric inorganic substrate250is attached to the front side210A of the semiconductor chip210. The dielectric inorganic substrate250comprises a pattern of metal structures260. The metal structures260are accommodated in recesses of the dielectric inorganic substrate250. At least a part of the metal structures260(e.g. all of them as shown in exemplaryFIG. 2A) connect through the dielectric inorganic substrate250. That is, in this case the recesses in the dielectric inorganic substrate250may form through-holes passing through the dielectric inorganic substrate250. The electrode220is connected to the pattern of metal structures260.

The dielectric inorganic substrate250may be a glass substrate or a semiconductor substrate. If the metal structures260are required to be electrically insulated from each other, glass or an intrinsic semiconductor substrate material or a semiconductor substrate having recesses with insulated side walls could be used. Recesses with insulated side walls may, e.g., be formed by applying an insulating layer (e.g. a silicon oxide layer or a silicon nitride layer) to the side walls of the recesses.

The dielectric inorganic substrate250may have a thickness TS which may be equal to or greater than or less than 25 μm or 50 μm or 100 μm or 200 μm. Depending on the thickness TS of the dielectric inorganic substrate250, the length of the metal structures260may, e.g., be a few μm greater than TS. That is, the metal structures260may protrude a small distance (e.g. a few μm) over a top surface250A and/or over a bottom surface250B of the dielectric inorganic substrate250.

The pattern of metal structures260may, e.g., be a regular array. A pitch P of the pattern of metal structures260may, e.g., be equal to or greater than or less than 15 μm or 17.5 μm or 20 μm or 22.5 μm or 25 μm or 27.5 μm or 30 μm. The distance D between adjacent metal structures260may, e.g., be equal to or greater than or less than 10 μm or 5 μm or 4 μm or 3 μm or 2 μm. The lateral dimension(s) of each metal structure260may, e.g., be equal to or greater than or less than 12.5 μm or 15 μm or 17.5 μm or 20 μm or 22.5 μm or 25 μm or 27.5 μm.

In one specific example the lateral dimension(s) of each metal structure260may be about 20 μm and the pitch P may be between 22 μm and 25 μm.

The pattern of the metal structures260may cover the complete area of the electrode220or at least a substantial portion (e.g. equal to or more than 70% or 80% or 90% or 95%) thereof. For instance, the electrode220may be a load electrode (e.g. source electrode or a drain electrode) of a power transistor and the complete load electrode area or a substantial portion thereof may be covered by the pattern of the metal structures260.

The semiconductor chip210may include integrated circuitry such as, e.g., transistor(s), in particular power transistor(s). For instance, the electrode220may form a (front side) load electrode of a power integrated circuitry. The semiconductor chip210may further be equipped with a backside electrode230. The backside electrode230may also form a load electrode of the power integrated circuitry implemented in the semiconductor chip210.

The (front side) electrode220may cover a substantial portion of the area of the semiconductor chip210, e.g. equal to or more than 50% or 60% or 70% or 80% or 90% of the area of the front side210A of the semiconductor chip210. Similarly, the backside electrode230may cover a substantial portion of the area of the semiconductor chip210, e.g. equal to or more than 50% or 60% or 70% or 80% or 90% of the area of the backside210B of the semiconductor chip210. For instance, as exemplified inFIG. 2A, the backside electrode230may cover the full area of the backside210B of the semiconductor chip210.

The semiconductor chip210may have a thickness TC equal to or less than 100 μm or 50 μm or 30 μm. As known in the art, for same integrated device such as, e.g., power devices, the smaller the thickness TC of the semiconductor chip210, the higher is the device performance which can be obtained. Therefore, in particular small values of TC (i.e. thin semiconductor chips210) may be desired to be used in the semiconductor device200.

In some embodiments, TC is equal to or smaller than TS. That is, the electrical interconnect formed by the dielectric inorganic substrate250may, e.g., be as thick as or thicker than the semiconductor chip210.

FIG. 2Billustrates a partial top view on the dielectric inorganic substrate250as seen from the viewing direction of the semiconductor chip210. As apparent fromFIG. 2Bthe metal structures260may be arranged in a densely packed array in the dielectric inorganic substrate250. Differently put, the dielectric inorganic substrate250may form a matrix for the pattern or array of metal structures260. The percentage in volume of the metal of the metal structures260in the dielectric inorganic substrate250may be high, e.g. equal to or greater than, e.g., 60% or 70% or 80%.

By virtue of the dielectric inorganic substrate250, the semiconductor device200may have advanced heat dissipation properties. Heat dissipation in semiconductor devices200relies, inter alia, on the electrical interconnect between the semiconductor chip210and an application board to which the semiconductor chip210(or a package including the semiconductor chip210) is mounted. The electrical interconnect provides a thermal conductivity to remove heat from the package and provides a heat capacity to absorb heat so as to protect the semiconductor chip210from temporary overheating.

The pattern of metal structures260in the dielectric inorganic substrate250can be optimized in terms of thermal conductivity or heat capacity. The more densely the metal structures260are packed in the dielectric inorganic substrate250, the better is the heat conductivity and the thermal capacity of the dielectric inorganic substrate250. Further, enhancing the thickness TS of the dielectric inorganic structure250increases the thermal capacity thereof because more metal is held available in the dielectric inorganic structure250for transient heat absorption.

Returning toFIG. 2B, the metal structures260may, e.g., have a polygonal (square, hexagonal, etc.) or a rounded cross-section. A square cross-sectional shape is exemplarily shown inFIG. 2B. A hexagonal cross-sectional shape may be beneficial as it provides for a particular high area packing density of metal in the dielectric inorganic structure250.

Each metal structure260may have an axial-symmetric cross-sectional shape. Further, each metal structure260may have a substantially constant cross-sectional shape along its extension through the dielectric inorganic substrate250.

Moreover, the pattern does not need to be designed as a regular array. Rather, the pattern may be composed of a plurality of different patterns or (e.g. regular) arrays. Such different patterns (i.e. sub-patterns) or arrays may distinguish from each other e.g. in terms of pitch P, distance D and/or cross-sectional shape of the metal structures260.

FIGS. 3A-3Lillustrate exemplary stages of manufacturing a semiconductor device in accordance with the disclosure, e.g. the semiconductor device200as shown inFIGS. 2A, 2B.

Referring toFIG. 3A, a dielectric inorganic substrate wafer350is provided. The dielectric inorganic substrate wafer350may, e.g., have a thickness of 400 to 700 μm. The dielectric inorganic substrate wafer350may, e.g., be a glass wafer or a semiconductor wafer.FIGS. 3A-3Lillustrate only a portion of the dielectric inorganic substrate wafer350which comprises, e.g., one semiconductor chip210, seeFIG. 3L.

FIG. 3Billustrates the formation of recesses320in a top surface350A of the dielectric inorganic substrate wafer350. The recesses320may be formed by etching. The dimensions (lateral dimensions, depths) of the recesses320may correspond to the dimensions described above for the metal structures260. That is, by way of example, the recesses320may have a lateral dimension of e.g. 20 μm and a depth of e.g. 50 μm.

According toFIG. 3B, the dielectric inorganic substrate wafer350may include (per chip) a first pattern PAT1of recesses320and a second pattern PAT2of the recesses320. As shown on the right hand side ofFIG. 3Bwhich illustrates a top view on a chip portion of the dielectric inorganic substrate wafer350, the area of PAT1may, e.g., be substantially greater than the area of PAT2. Further, as mentioned before, the parameters (P, D, shape, . . . ) of the recesses320in PAT1and in PAT2may be different from each other or may be the same. For instance, PAT1may correspond to a load electrode (e.g. source or drain electrode of a transistor) of the semiconductor chip210while PAT2may correspond to a control electrode (e.g. gate electrode of the transistor) of the semiconductor chip210.

In one embodiment, only the first pattern PAT1is formed as a pattern of recesses, while the second pattern PAT2is replaced by another type of through connection such as, e.g., a single hole serving as a through connection for, e.g., the control electrode of the semiconductor chip210.

Some of the recesses320formed in the dielectric inorganic substrate wafer350may have a depth which is smaller than the target thickness of the dielectric inorganic substrate wafer350(i.e. TS ofFIG. 2A), while other recesses320have a depth greater than the target thickness of the dielectric inorganic substrate wafer350.

Referring toFIG. 3C, a liner312may optionally be deposited over the top surface350A of the dielectric inorganic substrate wafer350. The liner312may, e.g., be an electrically conductive seed layer.

Referring toFIG. 3D, a protective layer314may be applied over the top surface of the dielectric inorganic substrate wafer350and, e.g., over the liner312. The protective layer314may be applied using a self-aligned process. That is, the protective layer314may only be applied over parts of the top surface350A of the dielectric inorganic substrate wafer350which are not recessed. The protective layer314may, e.g., be applied by a rolling and/or printing process and may, e.g., completely cover the liner312at non-recessed parts of the top surface350A of the dielectric inorganic substrate wafer350.

It is to be noted that the processes of liner312deposition and/or protective layer314deposition as shown inFIGS. 3C and 3Dare optional processes, since metal plating, as described in the following, can also be carried out without liner312and/or protective layer314deposition.FIG. 3Eshows the structure after application of the protective layer314.

Referring toFIG. 3F, metal is plated to fill the recesses320. As a result, the metal structures260are formed. The metal structures320may completely fill the recesses320.

The metal structures260may protrude a small distance over the top surface350A of the dielectric inorganic substrate wafer350. Metal plating can be carried out by electro-chemical deposition (ECD). For instance, copper or a copper alloy may be used as a plating metal, but other metals known in the art to be suitable for package interconnects can also be used.

Referring toFIG. 3H, a bonding material360may be applied on the dielectric inorganic substrate wafer350. The bonding material360may be applied on areas of the dielectric inorganic substrate wafer350which correspond to inactive areas of a semiconductor wafer310(seeFIG. 3I). For instance, the bonding material360may be applied in a kerf pattern, i.e. along designated cutting lines of the dielectric inorganic substrate wafer350and the semiconductor wafer310.

The bonding material360may comprise or be glass glue or a resin or any other material suitable to permanently bond the dielectric inorganic substrate wafer350to the semiconductor wafer310(seeFIG. 3I).

Referring toFIG. 3I, the front side of a semiconductor wafer310is combined with the dielectric inorganic substrate wafer350to form a composite wafer380. During this process the plurality of patterns of metal structures260is placed opposite the plurality of electrodes220on the semiconductor wafer310. Again, it is to be noted thatFIG. 3Ionly shows a partial view of the dielectric inorganic substrate wafer350and the semiconductor wafer310which substantially corresponds to one semiconductor chip210in the semiconductor wafer310. Hence, the first pattern PAT1of metal structures260and the second pattern PAT2of metal structures260may form sub-patterns corresponding to two electrodes220of a single semiconductor chip210of the semiconductor wafer310.

The process of combining the semiconductor wafer310and the dielectric inorganic substrate wafer350as shown inFIG. 3Imay be carried out by using optical alignment through the dielectric inorganic substrate wafer350(e.g. so-called through-glass alignment or through-semiconductor alignment). That is, an optical alignment processes may be carried out by viewing through the dielectric inorganic substrate wafer350to recognize the position of the semiconductor wafer310relative to the position of the dielectric inorganic substrate wafer350so as to combine the semiconductor wafer310and the dielectric inorganic substrate wafer350in proper alignment.

The bonding material360may have also been applied to the semiconductor wafer310rather than to the dielectric inorganic substrate wafer350.

FIG. 3Jillustrates the process of bonding the semiconductor wafer310to the dielectric inorganic substrate wafer350with the front side210A of the semiconductor wafer310facing the dielectric inorganic substrate wafer350. This process may concurrently connect the plurality of patterns of metal structures260on the dielectric inorganic substrate wafer350to the plurality of electrodes220on the semiconductor wafer310. The process may be carried out by applying heat and pressure to the composite wafer380.

By virtue of this process the bonding360material fixedly secures the semiconductor wafer310to the dielectric inorganic substrate wafer350. Further, by this or another process, the metal structures260may be electrically and mechanically fixedly connected to the electrodes220. The connections may be solder-free, i.e. no solder material may be used for establishing the electrical, mechanical and thermal connection between the electrodes220and the metal structures260. By way of example, the connection may be created by the formation of an eutectic phase between the metal of the electrodes220and the metal of the metal structures260.

Referring toFIGS. 3K and 3L, the dielectric inorganic substrate wafer350is thinned from a bottom surface350B (seeFIG. 3J) opposite the top surface350A to expose the metal of at least a part or of all of the metal structures260in the recesses320.

More specifically, thinning may, e.g., be carried out in a multi-stage process. For instance, as shown inFIG. 3K, thinning may comprise grinding the dielectric inorganic substrate wafer350down to a thickness which is only slightly larger than the depth of the recesses320. For instance, grinding may stop at a distance of equal to or less than 20 μm or 15 μm or 10 μm over the bottom of the recesses320.

The metal structures260or at least a part of them may then be exposed by etching the dielectric inorganic substrate wafer350down to the thickness TS (seeFIG. 2A). Etching may be carried out by wet or dry chemical etching. Etching may be continued until the metal structures260(or at least some of them) protrude a small distance such as, e.g., a few μm over the bottom surface of the thinned dielectric inorganic substrate wafer350. The bottom surface of the thinned dielectric inorganic substrate wafer350may correspond to the bottom surface250B of the dielectric inorganic substrate250as shown inFIG. 2A.

In the following, a number of standard back-end-of-line (BEOL) processes of chip packaging may be carried out on the composite wafer380shown inFIG. 3L. In this context, the composite wafer380is separated along dicing lines L into composite chips390. Separating the composite wafer380into composite chips390may be carried out by any suitable dicing methods, e.g. mechanical sawing, laser dicing and/or etching.

FIG. 4illustrates a semiconductor device400including a composite chip such as, e.g., composite chip390shown inFIG. 3L. The semiconductor device400is similar to semiconductor device200, and reference is made to the above description to avoid reiteration. As shown inFIG. 4, the semiconductor device400may further include an optional backside metallization layer430. The backside metallization layer430may correspond to the backside electrode230ofFIG. 2A. It is to be noted that the backside metallization layer430may have been formed on wafer level (i.e. before separating the composite wafer380into composite chips390) or may be formed after chip separation.

That is, the backside metallization layer430may be applied as a structured layer on the backside310B of the semiconductor wafer310. The structure may be a chip-wise structure, i.e. inactive regions or kerf regions of the semiconductor wafer310may remain uncovered by the backside metallization layer430. This allows to avoid dicing through the backside metallization layer430during composite chip390separation and may further allow to shape the backside electrode230in a desired manner. For instance, a circumferential frame-like uncovered area (not shown) between an outline of the backside electrode230and the edge of the composite chip390may be formed.

In this example the semiconductor device400includes three package terminals, namely the backside electrode230(e.g. structured from the backside metallization layer430), a first front side electrode420_1and a second front side electrode420_2. The first and second front side electrodes420_1,420_2or at least one of these front side electrodes420_1,420_2(e.g. a load electrode420_1) may be implemented as a pattern of metal structures260in accordance with the above description.

The front side electrodes420_1and/or420_2may be configured to be directly soldered to an application board (not shown). In other words, the composite chip390as diced out of the composite wafer380may optionally already represent the fully packaged semiconductor device400. In this case the process and the semiconductor device400described herein could be referred to as “composite wafer level packaging” by analogy with the conventional technique of “embedded wafer level packaging”.

The semiconductor chip390may further be embedded in an encapsulant (not shown). The encapsulant may be applied before or after the composite wafer380is separated into composite chips390, i.e. on (composite) wafer level in accordance with a conventional embedded wafer level packaging technique or on (composite) chip level by using a conventional chip package molding technique.

A further beneficial aspect of the process described herein may be that the standard glass carrier wafer used for handling and processing the semiconductor wafer310can be omitted since the dielectric inorganic substrate wafer350can be used to take-on its role. More specifically, in standard wafer handling and/or processing a glass carrier wafer is sometimes used as tool to stabilize the semiconductor wafer during handling and processing, e.g. during grinding. This standard glass carrier wafer is a temporary wafer which is usually demounted before wafer dicing. The dielectric inorganic substrate wafer350may replace such standard glass carrier wafer, i.e. the process described herein can be carried out without using such a standard glass carrier wafer. The dielectric inorganic substrate wafer350distinguishes from such standard glass carrier wafer by, inter alia, comprising the plurality of patterns of metal structures260and by being permanently bonded to the semiconductor wafer310.

Further,FIG. 4illustrates that the semiconductor device400is provided with an edge termination (diced bonding material360). The edge termination could cover the semiconductor chip210until its last active cell. The edge termination may provide a fully circumferential and, e.g., hermetically tight protection against environmental attack such as, e.g., humidity or other substances which could chemically impact the composite chip390. If the semiconductor device400is embedded in an encapsulant (not shown), the encapsulant my cover the edge termination (diced bonding material360) or leave the edge termination exposed.

The following examples pertain to further aspects of the disclosure:

Example 1 is a method of manufacturing a semiconductor device, the method comprising: forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer, wherein the metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate wafer; providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer; bonding the front side of the semiconductor wafer to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is connected to the plurality of electrodes; and separating the composite wafer into composite chips.

In Example 2, the subject matter of Example 1 can optionally include wherein forming a plurality of patterns of metal structures in the dielectric inorganic substrate wafer comprises: forming recesses in a first surface of the dielectric inorganic substrate wafer; metal plating to fill the recesses with metal; thinning the dielectric inorganic substrate wafer from a second surface opposite the first surface to expose the metal of at least a part of the recesses.

In Example 3, the subject matter of Example 2 can optionally include wherein thinning comprises: grinding the dielectric inorganic substrate wafer down to a thickness which is slightly larger than the depth of the recesses; and etching the dielectric inorganic substrate wafer to expose the metal.

In Example 4, the subject matter of any preceding Example can optionally include wherein bonding the front side of the semiconductor wafer to the dielectric inorganic substrate wafer comprises: applying a kerf pattern of bonding material between the semiconductor wafer and the dielectric inorganic substrate wafer; and applying heat and pressure to bond the semiconductor wafer to the dielectric inorganic substrate wafer, thereby connecting the plurality of electrodes to the plurality of patterns of metal structures.

In Example 5, the subject matter of any preceding Example can optionally include wherein a percentage in volume of metal in the dielectric inorganic substrate wafer within a pattern of metal structures is equal to or greater than 60% or 70% or 80%.

Example 10 is a semiconductor device which can include a semiconductor chip comprising a front side and a backside, wherein an electrode is disposed on the front side of the semiconductor chip; a dielectric inorganic substrate comprising a pattern of metal structures which are accommodated in recesses of the dielectric inorganic substrate and at least partly connect through the dielectric inorganic substrate; wherein the front side of the semiconductor chip is attached to the dielectric inorganic substrate and the electrode is connected to the pattern of metal structures.

In Example 7, the subject matter of Example 6 can optionally include wherein the dielectric inorganic substrate is a glass substrate or a semiconductor substrate.

In Example 8, the subject matter Example 6 or 7 can optionally include wherein adjacent metal structures are spaced apart from each other by a distance equal to or less than 10 μm or 5 μm or 4 μm or 3 μm.

In Example 9, the subject matter of any of Examples 6 to 8 can optionally include wherein a length of those metal structures which connect through the dielectric inorganic substrate is equal to or greater than 25 μm or 50 μm or 100 μm or 200 μm.

In Example 10, the subject matter of any of Examples 6 to 9 can optionally include wherein the metal structures are plated metal pillars.

In Example 11, the subject matter of any of Examples 6 to 10 can optionally include wherein the pattern is a regular array.

In Example 12, the subject matter of any of Examples 6 to 11 can optionally include wherein the semiconductor chip and the dielectric inorganic substrate have aligned cutting edges.

In Example 13, the subject matter of any of Examples 6 to 12 can optionally include wherein a percentage in volume of metal in the dielectric inorganic substrate within the pattern of metal structures is equal to or greater than 60% or 70% or 80%.

In Example 14, the subject matter of any of Examples 6 to 13 can optionally include wherein the semiconductor chip and the dielectric inorganic substrate are tightly sealed together at their edge regions.

In Example 15, the subject matter of any of Examples 6 to 14 can optionally include wherein the electrode is connected to the pattern of metal structures by solder-free connections.

In Example 16, the subject matter of any of Examples 6 to 15 can optionally include wherein the dielectric inorganic substrate is configured to be soldered to an application board, with the pattern of metal structures forming an electrical and thermal connection between the electrode of the semiconductor chip and a solder joint on the application board.

In Example 17, the subject matter of any of Examples 6 to 16 can optionally include wherein the semiconductor chip is a power semiconductor chip.