Chip package structure with multi-chip stack

A chip package structure including a circuit board, a first die, a spacer, and a second die. The first die is disposed on the circuit board, and the spacer is disposed on the circuit board, in which the spacer includes a spacer part and at least one via structure penetrating through the spacer part. The second die is disposed on the first die and the spacer, and the second die is electrically connected to the circuit board through the spacer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a chip package structure, and more particularly, to a chip package structure with multi-chip stack.

2. Description of the Prior Art

With miniaturization and multifunction of electronic products, multi-chip package structures are becoming more and more common in many electronic products, in which two or more chips are packaged in one single package structure to shrink overall volume. In common multi-chip package structures, two or more chips are disposed on the same substrate side by side. As the number of the chip is increased, the area of the package structure is accordingly enlarged by disposing chips side by side. For solving this problem, a stacking method is developed to arrange the chips. However, there are many disadvantages exist in the chip stacking method, for example, excessive high thickness of the package structure is occurred by vertically stacking the chips, and the resistance of electrical path from the top chip to the circuit board becomes larger, thereby increasing power consumption.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a chip package structure is provided and includes a circuit board, a first die, a spacer, and a second die. The first die is disposed on the circuit board, and the spacer is disposed on the circuit board, in which the spacer includes a spacer part and at least one first via structure, and the first via structure penetrates through the spacer part. The second die is disposed on the first die and the spacer, and the second die is electrically connected to the circuit board through the spacer.

By means of the spacer with the via structure, the length of the bonding wire can be effectively shortened to reduce the resistance of the bonding wire. Therefore, the efficiency of the chip package structure can be improved or the power consumption of the chip package structure can be reduced, and the overall width of the chip package structure can also be reduced.

DETAILED DESCRIPTION

FIG. 1schematically illustrates a top view of a chip package structure according to a first embodiment, andFIG. 2schematically illustrates a cross-sectional view taken along a line A-A′ ofFIG. 1. The chip package structure1includes a circuit board12, and at least one spacer14and at least two dies (such as first die161and second die162) disposed on the circuit board12, in which one of the dies (such as the first die161) is disposed on the spacer14and another one of the dies (such as the second die162), and the die disposed on the spacer14may be electrically connected to the circuit board12through the spacer14. Accordingly, a width W1of the chip package structure in a horizontal direction may be shrunk, and/or the thickness T of the chip package structure1may be reduced. The horizontal direction may for example be a direction D1or a direction D2parallel to a top surface12S of the circuit board12or other direction parallel to the top surface12S of the circuit board12and different from the direction D1and the direction D2.

The circuit board12may for example be a printed circuit board or other type circuit board, but not limited thereto. In some embodiments, the circuit board12may for example be the circuit board with wires of a single layer or wires of multi-layer. For example, the circuit board12shown inFIG. 2may include a plurality of top pads12a, a plurality of bottom pads12b, a top protection layer12c, a bottom protection layer12d, a plurality of interconnects12e, and an insulation layer12f. The top protection layer12cis disposed on the insulation layer12fand has openings exposing the top pads12a, the bottom protection layer12dis disposed under the insulation layer12fand has openings exposing the bottom pads12b, and the interconnects12epenetrate through the insulation layer12f, such that the top pads12amay be electrically connected to the corresponding bottom pads12bthrough the corresponding interconnects12e. The top surface12S may for example be an outer surface of the top protection layer12c, but not limited thereto. The circuit board12of the present invention is not limited herein, and the structure of the circuit board12may be adjusted according to the requirements.

As shown inFIG. 1andFIG. 2, the first die161may be bonded and electrically connected to the circuit board12, for example by a flip chip method. For instance, the first die161may include conductive bumps161bdisposed on the bottom surface of the first die161, and the first die161is bonded to the top pads12aof the circuit board12through the conductive bumps161b. In some embodiments, the electrical connection method between the first die161and the circuit board12is not limited to be the flip chip bonding method, and may be a wire bonding method. In some embodiments, a under fill22may be further disposed between the first die161and the circuit board12and used for enhancing bonding reliability between the first die161and the circuit board12. In this embodiment, an adhesive layer24may be further disposed under the second die162and used for sticking the second die162to the first die161and the spacer14. Also, the second die162may be electrically connected to the spacer14through the wire bonding method.

The die of the present invention may for example be an application specific integrated circuit (ASIC) chip, memory chip or other type chip, but not limited thereto. The memory chip may for example be flash memory chip or other type of memory chip, but not limited thereto. Different dies may have the same function or different functions. The die may also be known as semiconductor die, chip or integrated circuit die. In one embodiment, the first die161and the second die162may have different functions. For example, the second die162may be the memory chip, and the first die161may be the ASIC chip for controlling or driving the memory chip. In such situation, the first die161may have more input/output pads161a, so the first die161may be bonded to the circuit board12by the flip chip method; and the second die162may have less input/output pads162a, so the second die162may be electrically connected to the spacer14by the wire bonding method. For instance, the number of the input/output pads161aof the first die161may be greater than the number of the input/output pads162aof the second die162, but not limited thereto. In some embodiments, the first die161and the second die162may have the same function, for example, both are memory chips. In such situation, the first chip161may be electrically connected to the circuit board12by the wire bonding method, and the second chip162may be electrically connected to the spacer14through the wire bonding method.

The spacer14and the first die161are disposed on the circuit board12side by side, such that the spacer14and the first die161may be used for supporting the second die162. For example, the spacer14may be adhered to the circuit board12through the adhesive layer32. In this embodiment, the spacer14may include a spacer part14P and at least one first via structure TH1, and the first via structure TH1penetrates through the spacer part14P. The spacer part14P may for example include semiconductor material, polymer material or other suitable supporting material, but not limited thereto. In the embodiment shown inFIG. 2, the spacer14may include a plurality of first via structures TH1vertically penetrating through the spacer part14P, and the spacer14may further include a plurality of top pads14aand a plurality of bottom pads14b. The top pads14aare disposed on the spacer part14P and connected to the corresponding first via structures TH1, and the bottom pads14bare disposed under the spacer part14P and connected to the corresponding first via structure TH1, such that the top pads14amay be electrically connected to the corresponding bottom pads14bthrough the corresponding first via structures TH1. The bottom pad14bmay be electrically connected to the corresponding top pad12aof the circuit board12. For example, the first via structure TH1penetrates through the spacer part14P, such that the top pad14aoverlaps the bottom pad14bin the top view direction VD. The spacer14may further include a connecting element201for electrically connecting the bottom pad14bto the top pad12aof the circuit board12. In one embodiment, the top pad12aof the circuit board12may not overlap the bottom pad14bof the spacer14in the top view direction VD, so that at least one top pad12aof the circuit board12may not overlap at least one first via structure TH1to which the top pad12ais connected in the top view direction VD of the chip package structure1, but not limited thereto. In the embodiment shown inFIG. 2, the connecting element201may for example be a single conductive layer, which may for example include metal or other suitable conductive material. Although the connecting element201illustrated inFIG. 2is not connected to the bottom pad14b, the connecting element201actually may be connected to the bottom pad14bat other places, so that the bottom pad14bmay be electrically connected to the corresponding top pad12athrough the connecting element201. The bottom pad14band the connecting element201may be formed of the same conductive layer or different conductive layers. The conductive layer may for example include metal or other suitable conductive material, but not limited thereto. In some embodiments, the connecting element201may for example include redistribution layer, but not limited thereto. It is noted that in order to reduce the tilt of the second die162disposed on the spacer14and the first die161, a height of the top surface14S of the spacer part14P of the spacer14may be substantially level with the top surface161S of the first die161. For example, a distance between the top surface14S of the spacer part14P and the top surface12S of the circuit board12and a distance between the top surface161S of the first die161and the top surface12S of the circuit board12may be substantially the same.

As shown inFIG. 2, in one embodiment, the chip package structure1may include at least one first bonding wire181extending from the second die162(such as the input/output pad162aof the second die162shown inFIG. 1) to the spacer14(such as the top pad14aof the spacer14), such that the second die162may be electrically connected to the top pad14a, the first via structure TH1and the bottom pad14bof the spacer14through the first bonding wire181, thereby being electrically connected to the circuit board12through the spacer14. In one embodiment, an end of the first bonding wire181may be directly bonded to the input/output pad162aof the second die162, and another end of the first bonding wire181may be directly bonded to the top pad14aof the spacer14, but the present invention is not limited thereto. It is noted that since the height of the top pad14aof the spacer14is higher than the height of the top pad12aof the circuit board12, the length of the first bonding wire181may be shortened to reduce the resistance of the first bonding wire181. In addition, the resistance of the first via structure TH1of the spacer14may be less than the resistance of the first bonding wire181, so the resistance from the second die162to the circuit board12can be significantly reduced by decreasing the resistance of the first bonding wire181, thereby improving the efficiency of the chip package structure1or reducing the power consumption of the chip package structure1. Furthermore, since the length L1of the first bonding wire181projected onto the horizontal direction is shrunk, the overall width W1of the chip package structure1in the horizontal direction may be reduced.

In some embodiments, as shown inFIG. 1andFIG. 2, the chip package structure1may further include a third die163, another adhesive layer26, and at least one second bonding wire182. It is noted that although the cross-section view ofFIG. 2illustrates the first bonding wire181and the second bonding wire182together, the first bonding wire181and the second bonding wire182may be located in different cross-sectional views. The third die162is adhered to the second die162through the adhesive layer26, and the second bonding wire182extends from the input/output pad163a(top surface of the third die163) of the third die163to the top pad14aof the spacer14, so as to electrically connecting the third die163to the first via structure TH1of the spacer14. Accordingly, the third die163may be electrically connected to the circuit board12through the second bonding wire182and the spacer14. In one embodiment, an end of the second bonding wire182may be directly bonded to the input/output pad163aof the third die163, and another end of the second bonding wire182may be directly bonded to the corresponding top pad14aof the spacer14, but the present invention is not limited thereto. It should be noted that, the third die163and the second die162may be electrically connected to different top pads14aof the spacer14that are electrically insulated from each other, so as to transfer different signals. In some embodiments, when one of the input/output pad163aof the third die163and one of the input/output pad162aof the second die162transfer the same signal, the input/output pad163aand the corresponding input/output pad162amay electrically connected to the same top pad14aor the top pads14athat are electrically connected. It is noted that because of the disposition of the spacer14, the length of the second bonding wire182may be shortened to reduce the resistance of the second bonding wire182and improve the efficiency of the chip package structure1or reduce the power consumption of the chip package structure1. In addition, because the disposition of the spacer14reduces the height difference between two ends of the second bonding wire182, the height of a part of the second bonding wire182higher than third die163can be reduced, thereby shortening the length L2of the second bonding wire182projected onto the horizontal direction and decreasing the total width of the chip package structure1in the horizontal direction. In some embodiments, the third die163and the second die162may have the same function, for example both are memory chips. The adhesive layers24,26,32may for example include die attach film (DAF) or other suitable insulating adhesive material.

In some embodiments, the chip package structure1may include a plurality of spacers14, a plurality of second dies162, and a plurality of third dies163. In the embodiment of the chip package structure1shown inFIG. 1andFIG. 2, the number of the spacer14, the number of the second die162and the number of the third die163are respectively two for an example, but not limited thereto. In some embodiments, the spacers14may be disposed at two sides of the first die161respectively, for example, the first via structures TH1of the spacer14may be located at outer sides of the stacked dies, but not limited thereto. The second dies162not only be respectively disposed on the corresponding spacers14, but also be stacked on the same first die161, and the third dies163may be disposed on the corresponding second dies162respectively, such that the second dies162and the third dies163may be electrically connected to the circuit board12through the corresponding spacers14, thereby reducing the resistances of the first bonding wires181and the second bonding wires182. In some embodiments, the spacers14may have similar or the same structure, the second dies162may have similar or the same functions, and the third dies163may have similar or the same function, but not limited thereto.

In some embodiments, the chip package structure1may further include an encapsulation28disposed on the first die161, the second dies162, the third dies163, the first bonding wires181, the second bonding wires182, and the spacers14, and the encapsulation28seal them on the circuit board12, so as to protect the dies, bonding wires and the spacers14. In some embodiments, the chip package structure1may further include a plurality of conductive balls30respectively disposed on the bottom pads12bof the circuit board12, such that the chip package structure1may further be disposed on and electrically connected to other device, carrier or circuit board.

The chip package structure of the present invention is not limited to the above-mentioned embodiments, and other embodiments of the present invention are further detailed in the following description. In order to simplify the description, the element of different embodiments and the same element of the first embodiment will use the same label. The following contents would focus on the difference between different embodiments and the first embodiment, and the repeated portion will not be redundantly described.

FIG. 3schematically illustrates a cross-sectional view of a chip package structure according to a second embodiment of the present invention. The chip package structure2of this embodiment is different from the previous embodiment in that the connecting element202may include a redistribution layer formed on the bottom surface of the spacer part14P and the bottom pads14b. In the embodiment shown inFIG. 3, the redistribution layer may include two dielectric layers34,36and a conductive layer38, in which the conductive layer38is disposed between the dielectric layers34,36, and the dielectric layer34may have at least one opening, such that the conductive layer38may be electrically connected to at least one of the bottom pads14bthrough the opening of the dielectric layer34. Additionally, the dielectric layer36may have at least one opening corresponding to the top pad12aof the circuit board12, such that the conductive layer38may be electrically connected to the circuit board12through the conductive bump40. In some embodiments, the redistribution layer may include three or more dielectric layers and two or more conductive layers.

FIG. 4schematically illustrates a cross-sectional view of a chip package structure according to a third embodiment of the present invention. The chip package structure3of this embodiment is different from the previous embodiment in that the chip package structure3may further include at least one third bonding wire183extending from the top surface161S of the first die161to one of the top pads12aof the circuit board12, such that the first die161may be electrically connected to the circuit board12through the third bonding wire183. For example, the first die161may have less pads, so the pads are disposed on the top surface161S of the first die161. The first die161and the second die162may for example have the same function, for example they are both the memory chips. In some embodiments, the number of the third bonding wire183is not limited to be shown inFIG. 3and may be plural. It is noted that in order to reduce the damage of the third bonding wire183due to the disposition of the second die162, the thickness of the adhesive layer24used to stick the second die162to the first die161should be greater than the height of a part of the third bonding wire183on the top surface161S of the first die161. In some embodiments, the chip package structure3may adopt the embodiment shown inFIG. 2, the embodiment shown inFIG. 3or the content of the combination thereof.

FIG. 5schematically illustrates a cross-sectional view of a chip package structure according to a fourth embodiment of the present invention. The chip package structure4of this embodiment is different from the previous embodiment in that in the horizontal direction (e.g. the direction D1), the width W2of the second die462is greater than the width W3of the first die161. In some embodiments, the area of the second die462is greater than the area of the first die161but is not limited thereto. In the embodiment shown inFIG. 5, the chip package structure4may only include a single second die462disposed on the first die161and two spacers14, and the third dies163are disposed on the second die462, but the present invention is not limited thereto. In some embodiments, the area of the second die462may be adjusted according to the requirements and may be stacked on the first die161and at least one spacer14. In some embodiments, the chip package structure4may adopt the embodiment shown inFIG. 2, the embodiment shown inFIG. 3, the embodiment shown inFIG. 4or the content of the combination of at least two thereof.

FIG. 6schematically illustrates a cross-sectional view of a chip package structure according to a fifth embodiment of the present invention. The chip package structure5of this embodiment is different from the previous embodiment in that at least one second die562may further include a die body562M, at least one second via structure TH2, and a pad562adisposed on the die body562M and the second via structure TH2. The second via structure TH2penetrates through the die body562M and extends from the top surface562S1of the die body562M to the bottom surface562S2of the die body562M, and the second bonding wire182extends from the top surface163S of the third die163to the pad562aof the second die562. In one embodiment, in the top view direction VD, the second via structure TH2may overlap the pad562aso as to be electrically connected to the pad562a. Furthermore, the second die562may further include the connecting element542disposed on the bottom surface562S2of the die body562M and electrically connected to the second via structure TH2. Through the connecting element542and the second via structure TH2, the pad562aof the second die562electrically connected to the second bonding wire182may be electrically connected to the top pad14aof the spacer14. In one embodiment, one of the first via structures TH1of the spacer14electrically connected to the second via structure TH2overlap the second die562in the top view direction VD, such that the connecting element542may be electrically connected to the one of the first via structures TH1through the top pad14aof the spacer14. In one embodiment, the first via structure TH1and the second via structure TH2electrically connected to each other may overlap or may not overlap in the top view direction VD. It should be noted that the pad562aand the second via structure TH2is electrically insulated from the device562D in the die body562M; that is, the pad562ais different from and electrically insulated from the input/output pads162a(as shown inFIG. 1) of the second die562that are used to input signals to the device562D or output the signals from the device562D. Besides, the input/output pad162a(as shown inFIG. 1) of the second die562may still be electrically connected to the spacer14through the first bonding wire181. In the embodiment shown inFIG. 6, the connecting element542may for example be a single conductive layer, but not limited thereto. The conductive layer may for example include metal or other suitable conductive material, but not limited thereto. In some embodiments, the chip package structure5may just include a single third die163disposed on at least two second die562through the adhesive layer26. In some embodiments, the chip package structure5may adopt the embodiment shown inFIG. 2, the embodiment shown inFIG. 3, the embodiment shown inFIG. 4, the embodiment shown inFIG. 5or the content of the combination of at least two thereof.

It is worthy noted that by means of the disposition of the second via structure TH2, the second bonding wire182just needs to extend from the top surface163S of the third die163to the pad562aof the second die562instead of extending to the spacer14under the second die562, so the length of the second bonding wire182can be reduced. For example, the length L2of the second bonding wire182projected on the horizontal direction (e.g. the direction D1) is shortened, or the height of the part of the second bonding wire182on the top surface163S of the third die163is reduced. Therefore, the efficiency of the chip package structure5can be improved or the power consumption of the chip package structure5can be reduced, and the overall width W1of the chip package structure5can also be reduced.

FIG. 7schematically illustrates a cross-sectional view of a chip package structure according to a sixth embodiment of the present invention. The chip package structure6of this embodiment is different from the previous embodiment in that the connecting element642may include a redistribution layer formed on the bottom surface562S2of the die body562M. In the embodiment shown inFIG. 7, the redistribution layer may include two dielectric layers44,46and a conductive layer48, in which the conductive layer48is disposed between the dielectric layers44,46, and the dielectric layer44may have at least one opening, such that the conductive layer48may be electrically connected to the second via structure TH2through the opening of the dielectric layer44. Additionally, the dielectric layer46may have at least one opening corresponding to the top pad14aof the spacer14, such that the conductive layer48may be electrically connected to the spacer14through the conductive bump50, thereby being electrically connected to the circuit board12. In some embodiments, the redistribution layer may include three or more dielectric layers and two or more conductive layers. The conductive layer may for example include metal or other suitable conductive material, but not limited thereto. In some embodiments, the chip package structure6may adopt the embodiment shown inFIG. 2, the embodiment shown inFIG. 3, the embodiment shown inFIG. 4, the embodiment shown inFIG. 5or the content of the combination of at least two thereof.

In summary, in the chip package structure of the present invention, by means of the spacer with the via structure or the die with the via structure, the length of the bonding wire can be effectively shortened to reduce the resistance of the bonding wire. Therefore, the efficiency of the chip package structure can be improved or the power consumption of the chip package structure can be reduced, and the overall width of the chip package structure can also be reduced.