SEMICONDUCTOR DEVICE INCLUDING DIELECTRIC STRUCTURE INCLUDING FERROELECTRIC LAYER AND DIELECTRIC LAYER

A semiconductor device according to an embodiment includes a first electrode and a second electrode that are spaced apart from each other, and a dielectric structure disposed between the first electrode and the second electrode. The dielectric structure includes a barrier dielectric layer and a capacitor dielectric layer that are connected in series to each other. The barrier dielectric layer includes a ferroelectric material, and the capacitor dielectric layer includes a non-ferroelectric material.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. 119(a) to Korean Application No. 10-2022-0085972, filed on Jul. 12, 2022, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure generally relates to a semiconductor device and, more particularly, to a semiconductor device including a dielectric structure including a ferroelectric layer and a dielectric layer.

2. Related Art

As the feature size of a semiconductor chip decreases, the size of a unit device such as a capacitor device or a transistor device disposed in the semiconductor chip also decreases. However, the capacitance required for a dielectric layer constituting the unit device is required to maintain a predetermined reference value to ensure reliability of device operations. Accordingly, various methods for increasing the capacitance of the dielectric layer applied to the unit device are being studied.

As a representative method of increasing the capacitance of the dielectric layer, a method of applying a high-k material to the dielectric layer of the unit device is used. However, as the trend of decreasing the feature size of the semiconductor chip continues, research to improve the leakage current and breakdown voltage characteristics of the dielectric layer when a high-k material is applied to the dielectric layer is in progress.

SUMMARY

A semiconductor device according to an embodiment of the present disclosure includes a first electrode and a second electrode that are spaced apart from each other, and a dielectric structure disposed between the first electrode and the second electrode. The dielectric structure includes a barrier dielectric layer and a capacitor dielectric layer that are connected in series to each other. The barrier dielectric layer includes a ferroelectric material, and the capacitor dielectric layer includes a non-ferroelectric material.

A semiconductor device according to another embodiment of the present disclosure includes a substrate, and a capacitor disposed over the substrate. The capacitor includes a storage node electrode, a dielectric structure disposed over the storage node electrode, and a plate electrode disposed over the dielectric structure. The dielectric structure includes a capacitor dielectric layer and a barrier dielectric layer that are connected in series to each other. The capacitor dielectric layer includes a non-ferroelectric material, and the barrier dielectric layer includes a ferroelectric material.

A semiconductor device according to another embodiment of the present disclosure includes a substrate including a channel region, a gate dielectric structure disposed over the channel region, and a gate electrode disposed over the gate dielectric structure. The gate dielectric structure includes a barrier dielectric layer and a gate dielectric layer that are connected in series to each other. The barrier dielectric layer includes a ferroelectric material, and the gate dielectric layer includes a non-ferroelectric material.

A semiconductor device according to another embodiment of the present disclosure includes a substrate, an active layer disposed over the substrate, a gate dielectric structure disposed to be adjacent to the active layer, and a gate electrode disposed over the gate dielectric structure. The gate dielectric structure includes a barrier dielectric layer and a gate dielectric layer that are connected in series to each other. The barrier dielectric layer includes a ferroelectric material, and the gate dielectric layer includes a non-ferroelectric material.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, in order to clearly express the components of each device, the sizes of the components, such as width and thickness of the components, are enlarged. The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be construed to be different according to the ordinary skill in the art to which the embodiments belong. If expressly defined in detail, the terms may be construed according to the definitions. Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

In addition, expression of a singular form of a word should be understood to include the plural forms of the word unless clearly used otherwise in the context. It will be understood that the terms “comprise”, “include”, or “have” are intended to specify the presence of a feature, a number, a step, an operation, a component, an element, a part, or combinations thereof, but not used to preclude the presence or possibility of addition one or more other features, numbers, steps, operations, components, elements, parts, or combinations thereof.

According to embodiments of the present disclosure, a semiconductor device may include a dielectric structure disposed between a first electrode and a second electrode that are disposed to be spaced apart from each other. The dielectric structure may include a ferroelectric layer and a dielectric layer that are disposed in series to each other. In this specification, unless otherwise specified, the dielectric layer may refer to a non-ferroelectric layer. As an example, the non-ferroelectric layer may be a paraelectric layer.

FIG.1is a graph schematically illustrating polarization characteristics of a ferroelectric layer. Specifically,FIG.1is a graph illustrating the change in polarization of a ferroelectric layer when an electric field E is applied to both ends of the ferroelectric layer. As an example,FIG.1may be a graph10schematically illustrating the polarization characteristics of the ferroelectric layer, derived from the Landau-Ginzburg-Devonshire (LGD) theory.

Referring to the graph10ofFIG.1, the ferroelectric layer may have first and second remanent polarization Pr1and Pr2and first and second coercive fields Ec1and Ec2. The first and second remanent polarization Pr1and Pr2may be polarization that is maintained in the ferroelectric layer in a state in which no electric field is applied to the ferroelectric layer. The first and second coercive fields Ec1and Ec2may be electric fields that are required to respectively switch the polarization orientation of the ferroelectric layer in opposite directions.

Referring toFIG.1, the polarization state of the ferroelectric layer may be changed by applying an electric field E to the ferroelectric layer. As an example, an electric field E having a positive polarity may be applied to the ferroelectric layer having the second remanent polarization Pr2in an initial state in which no electric field is applied. The electric field E may be applied to the ferroelectric layer while the magnitude is increased in a sweep method. When the electric field E reaches the first coercive field Ec1, the polarization state of the ferroelectric layer may be rapidly changed from the second remanent polarization Pr2of the initial state to the first polarization P1via a negative slope portion10NC on the graph. When the electric field E is removed, the ferroelectric layer may have the first remanent polarization Pr1.

As another example, an electric field E having a negative polarity may be applied to the ferroelectric layer having the first remanent polarization Pr1in an initial state in which no electric field is applied. The electric field E may be applied to the ferroelectric layer while the magnitude is increased in a sweeping manner. When the electric field E reaches the second coercive field Ec2, the polarization of the ferroelectric layer may be changed from the first remanent polarization Pr1of the initial state to the second polarization P2via a negative slope portion10NC on the graph. When the electric field E is removed, the ferroelectric layer may have the second remanent polarization Pr2.

The capacitance of the ferroelectric layer may be proportional to the ratio ΔP/ΔE of a polarization change ΔP depending on an electric field change ΔE on the graph10. Accordingly, in the electric field section corresponding to the negative slope portion10NC of the graph10, the ferroelectric layer may exhibit a negative capacitance in which the ratio ΔP/ΔE has a negative value. That is, when the ferroelectric layer performs polarization switching in the first and second coercive fields Ec1and Ec2, the ferroelectric layer may pass through a portion of the graph10, implementing a negative capacitance. Conversely, in the remaining portions, except for the negative slope portion10NC in the graph10ofFIG.1, the ferroelectric layer may exhibit a positive capacitance in which the ratio ΔP/ΔE has a positive value.

FIG.2is a graph schematically illustrating polarization characteristics of a dielectric layer included in a dielectric structure according to an embodiment of the present disclosure.FIG.3is a graph schematically illustrating polarization characteristics of a ferroelectric layer included in the dielectric structure according to an embodiment of the present disclosure.

The graph20ofFIG.2discloses a polarization behavior of the dielectric layer (e.g., a polarization behavior of a dielectric layer20D included in a dielectric structure40D ofFIG.4) depending on an electric field E. When applying the electric field E to both ends of the dielectric layer20D while sweeping in a positive or negative direction, the polarization of the dielectric layer20D may increase from zero (0) in proportion to the applied electric field E as shown inFIG.2. When the electric field E is removed from the dielectric layer20D, the magnitude of the polarization may return to zero (0). That is, when no electric field is applied to the dielectric layer20D, the dielectric layer20D might not have remanent polarization. The capacitance of the dielectric layer20D may be proportional to the ratio ΔP/ΔE of a polarization change ΔP depending on an electric field change ΔE on the graph20. Accordingly, the dielectric layer20D may have a positive capacitance in the entire electric field section.

Referring to the graph30ofFIG.3, the ferroelectric layer included in the dielectric structure (e.g., a ferroelectric layer30D included in the dielectric structure40D ofFIG.4) according to an embodiment of the present disclosure may have a negative slope portion30IC on the graph30in an electric field section between first and second coercive fields Ec1′ and Ec2′. The ferroelectric layer30D ofFIG.4may have first and second remanent polarization Pr1′ and Pr2′ after the electric field E applied to the ferroelectric layer30D is removed, as shown inFIG.3.

The first and second coercive fields Ec1′ and Ec2′ on the graph30ofFIG.3may be much smaller than the first and second coercive fields Ec1and Ec2on the graph10ofFIG.1. That is, when the electric field E is applied from an initial state, polarization switching may occur immediately in the ferroelectric layer30D. In addition, the polarization switching may abruptly increase the magnitude of the polarization of the ferroelectric layer30D. Accordingly, the ratio ΔP/ΔE of a polarization change ΔP, depending on an electric field change ΔE of the ferroelectric layer30D in the electric field section between the first and second coercive fields Ec1′ and Ec2′ on the graph30, may be much greater than the ratio ΔP/ΔE of the polarization change of the ferroelectric layer on the graph10. As an example, the ratio ΔP/ΔE of the polarization change of the ferroelectric layer30D on the graph30may be 10 or greater. As another example, the ratio ΔP/ΔE of the polarization change of the ferroelectric layer30D on the graph30may be 20 or greater. In another example, the ratio ΔP/ΔE of the polarization change of the ferroelectric layer30D on the graph30may be 50 or greater.

As a result, when an electric field E is applied from the initial state, the ferroelectric layer30D may have a very large capacitance value that is proportional to the ratio ΔP/ΔE of the polarization change ΔP. As an example, a case in which the ferroelectric layer30D has a very large capacitance value may mean a case in which the ratio ΔP/ΔE of the polarization change ΔP, depending on the electric field change ΔE of the ferroelectric layer30D, is 10 or greater.

In an embodiment, the ferroelectric layer30D may implement the polarization characteristics of the graph30more efficiently when the ferroelectric layer30D are electrically connected with the dielectric layer having the polarization behavior ofFIG.2(e.g., the dielectric layer20D ofFIG.4). In an embodiment, as shown inFIG.4, when the ferroelectric layer30D and the dielectric layer20D are connected in series to form the dielectric structure40D, the ferroelectric layer30D in the dielectric structure40D may have the polarization characteristics of the graph30. In an embodiment, the thickness of the ferroelectric layer30D may be 5 nm or less, and the thickness of the ferroelectric layer30D may be substantially the same as or less than the thickness of the dielectric layer20D. In this case, when the thickness ratio of the ferroelectric layer30D and the dielectric layer20D is distributed within a predetermined range, the ferroelectric layer30D may have ferroelectric polarization characteristics according to the graph30ofFIG.3rather than the graph10ofFIG.1.

Although not necessarily explained by one theory, according to one of various theories, the polarization characteristics of the ferroelectric layer30D in connection with the graph30ofFIG.3may be described as follows. When the ferroelectric layer30D having spontaneous polarization in a first direction is bonded to the dielectric layer20D, a depolarization electric field that suppresses the spontaneous polarization may be generated in the ferroelectric layer30D. The depolarization electric field may be formed from an interface between the ferroelectric layer30D and the dielectric layer20D in an inward direction of the ferroelectric layer30D. In order to alleviate the depolarization electric field, first domains having a polarization orientation in the first direction and second domains having a polarization orientation in a second direction substantially opposite to the first direction may be formed alternately in the ferroelectric layer30D. In an embodiment, the first and second directions are directions that are substantially perpendicular to the interface between the ferroelectric layer30D and the dielectric layer20D.

In other words, the ferroelectric layer30D may have a stripe-type domain structure including the plurality of first domains and the plurality of second domains. In this case, as described above, when the thickness ratio of the ferroelectric layer30D and the dielectric layer20D is controlled within a predetermined range and the size of the first domain and the size of the second domain are reduced to a size of two unit cells or less or a size of three unit cells or less of the ferroelectric layer30D, the ferroelectric layer30D may exhibit the ferroelectric characteristics as illustrated inFIG.3. As an example, one unit cell of the ferroelectric layer30D may have a size of about 5 Å.

Meanwhile, as described above, when the ferroelectric layer30D has the polarization characteristics ofFIG.3when bonded with the dielectric layer20D, the dielectric structure including the bonded ferroelectric layer30D and the dielectric layer20D might not exhibit ferroelectricity as a whole. This may be because the depolarization electric field that is generated by the bonding of the ferroelectric layer30D and the dielectric layer20D functions to offset the spontaneous polarization inside the ferroelectric layer30D. As a result, the dielectric structure as a whole may exhibit non-ferroelectricity, such as paraelectricity. The non-ferroelectricity of the dielectric structure may be described in more detail with reference to an electric circuit inFIG.4.

FIG.4is a circuit diagram schematically illustrating an electric circuit configuration of a dielectric structure according to an embodiment of the present disclosure. Referring to the circuit diagram ofFIG.4, the dielectric structure40D may include a dielectric layer20D and a ferroelectric layer30D that are electrically connected in series to each other.

The dielectric layer20D and the ferroelectric layer30D may have the polarization characteristics that are described above with reference toFIGS.2and3, respectively. The dielectric structure40D may exhibit non-ferroelectricity as a whole.

Meanwhile, when a voltage is applied to both ends of the dielectric structure40D through a power supply VS, the capacitance CTof the dielectric structure40D may be calculated by Equation (1) below.

Here, CDEmay be the capacitance of the dielectric layer20D, and CFEmay be the capacitance of the ferroelectric layer30D.

When the ferroelectric layer30D has a very large capacitance, 1/(CFE) may be calculated to be a very small value and may be neglected in the calculation of Equation (1). Accordingly, the capacitance CTof the dielectric structure40D may be substantially the same as the capacitance CDEof the dielectric layer20D.

As a result, the dielectric layer20D may substantially function as a capacitor dielectric layer of the dielectric structure40D. The ferroelectric layer30D may function to prevent or alleviate the deterioration of the leakage current and breakdown voltage characteristics of the dielectric structure40D, as a barrier dielectric layer having a predetermined thickness.

FIG.5is a cross-sectional view schematically illustrating a semiconductor device1according to an embodiment of the present disclosure. Referring toFIG.5, the semiconductor device1may be a capacitor device including a first electrode110and a second electrode140that are disposed to be spaced apart from each other, and a dielectric structure1000disposed between the first electrode110and the second electrode140. The dielectric structure1000may include a ferroelectric layer120and a dielectric layer130.

The dielectric structure1000may have non-ferroelectricity. In this specification, non-ferroelectricity may mean that a dielectric material has no remanent polarization and no coercive field. As an example, non-ferroelectricity may mean paraelectricity. As described above with reference toFIG.4, the capacitance of the dielectric structure1000may be substantially the same as the capacitance of the dielectric layer130. That is, the capacitance of the dielectric structure1000may be determined by the capacitance of the dielectric layer130.

Referring toFIG.5, the ferroelectric layer120may be disposed on the first electrode110. The ferroelectric layer120may have ferroelectricity that is substantially the same as that of the ferroelectric layer30D, described above with reference toFIG.3. The ferroelectric layer120may function as a barrier dielectric layer of the dielectric structure1000, such as the ferroelectric layer30D of the dielectric structure40D described with reference toFIG.4.

The ferroelectric layer120may include a ferroelectric material. In an embodiment, the ferroelectric layer120may include hafnium zirconium oxide. In another embodiment, the ferroelectric layer120may include a dopant that is doped in the hafnium zirconium oxide. The dopant may stabilize the ferroelectricity of the ferroelectric layer120. The dopant may include, for example, carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), lanthanum (La), or a combination of two or more thereof.

In an embodiment, the ferroelectric layer120may have a crystal structure of an orthorhombic crystal system. For example, the ferroelectric layer120may have a thickness of 1 nm to 5 nm. The ferroelectric layer120may have a single crystalline or polycrystalline structure. In an embodiment, the ferroelectric layer120may be an epi-growth layer. The ferroelectric layer120may be epitaxially formed on the first electrode110through, for example, atomic layer deposition, pulsed layer deposition, or chemical vapor deposition.

Referring toFIG.5, the dielectric layer130may be disposed on the ferroelectric layer120. The dielectric layer130may have a non-ferroelectricity that is substantially the same as that of the dielectric layer20D, described above with reference toFIG.2. The dielectric layer130may have paraelectricity, for example. The dielectric layer130may function as a capacitor dielectric layer of the dielectric structure1000, such as the dielectric layer20D of the dielectric structure40D described with reference toFIG.4. The dielectric layer130may have a thickness of 1 nm to 5 nm, for example.

In an embodiment, the dielectric layer130may be an epi-growth layer. The dielectric layer130may be epitaxially formed on the ferroelectric layer120through, for example, atomic layer deposition, pulsed layer deposition, or chemical vapor deposition.

The dielectric layer130may include a non-ferroelectric material. As an example, the non-ferroelectric material may be a paraelectric material. In an embodiment, the dielectric layer130may include hafnium oxide, zirconium oxide, or a combination thereof. The dielectric layer130may have a crystal structure of a monoclinic crystal system or a tetragonal crystal system.

Referring toFIG.5again, the second electrode140may be disposed on the dielectric layer130. The second electrode140may include a conductive material. The conductive material may include, for example, doped silicon (Si), gold (Au), silver (Ag), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

The ferroelectric layer120and the dielectric layer130of the dielectric structure1000may be connected in series to each other between the first electrode110and the second electrode140. Accordingly, the dielectric structure1000may have a configuration that is substantially the same as the configuration of the dielectric structure40D ofFIG.4. That is, the dielectric structure1000may include the dielectric layer130as a capacitor dielectric layer and may include the ferroelectric layer120as a barrier dielectric layer. Despite the ferroelectric layer120and the dielectric layer130being connected in series, the dielectric structure1000may have a capacitance that is substantially the same as the capacitance of the dielectric layer130. In addition, the dielectric structure1000may improve the leakage current and breakdown voltage characteristics due to the electrical barrier function that is performed by the ferroelectric layer120.

FIG.6illustrates graphs schematically illustrating the results of simulating the charge amounts of semiconductor devices depending on applied voltages. First to third graphs501,502, and503ofFIG.6may be graphs of the charging characteristics of first to third semiconductor devices including first to third dielectric structures, respectively. In the first to third graphs501,502, and503, the charge amount changes ΔQ depending on the voltage changes ΔV, that is, the slopes of the first to third graphs501,502, and503may correspond to the capacitances of the first to third dielectric structures, respectively.

The first and second graphs501and502may represent charging characteristics of the first and second semiconductor devices, which are comparative examples of the present disclosure, and the third graph503may represent charging characteristics of the third semiconductor device, which is an embodiment of the present disclosure.

The first dielectric structure may be a paraelectric structure in which a zirconium oxide layer, an aluminum oxide layer, and a zirconium oxide layer are sequentially stacked, and may have a first thickness. Each of the zirconium oxide layer and the aluminum oxide layer may have paraelectricity. The second dielectric structure may have the same configuration as the first dielectric structure, but may have a second thickness corresponding to 40% of the first thickness. The third dielectric structure may be a paraelectric structure in which a hafnium zirconium oxide layer, which is a ferroelectric layer, and a zirconium oxide layer, which is a dielectric layer, are stacked, and may have the first thickness.

Referring toFIG.6, the charge amount change ΔQ, depending on the voltage change ΔV of the first graph501, may be the smallest. In addition, the charge amount change ΔQ, depending on the voltage change ΔV of each of the second graph502and the third graph503, may be substantially the same. Accordingly, although the third dielectric structure of the third graph501has a thickness that is 2.5 times greater than that of the second dielectric structure of the second graph502, the third dielectric structure may have substantially the same capacitance as the second dielectric structure.

FIG.7illustrates graphs schematically illustrating results of simulating leakage currents of semiconductor devices depending on applied voltages. First to third graphs601,602, and603ofFIG.7may be graphs that are obtained by calculating the leakage currents that are generated from the first to third dielectric structures when a voltage is applied to the first to third dielectric structures, described in relation toFIG.6.

Referring toFIG.7, the leakage current of the first dielectric structure of the first graph601may represent the lowest value. The first dielectric structure may include a zirconium oxide layer, an aluminum oxide layer, and a zirconium oxide layer, each of which is a paraelectric layer. The first dielectric structure may have the first thickness. In addition, the leakage current of the second dielectric structure of the second graph602may represent the highest value. The second dielectric structure may have a thickness corresponding to 40% of the thickness of the first dielectric structure. Meanwhile, the third dielectric structure of the third graph603may have a leakage current value between the leakage current values of the first dielectric structure and the second dielectric structure.

Referring toFIGS.6and7together, the third dielectric structure may have substantially the same capacitance as the second dielectric structure and may have superior leakage current characteristics than the second dielectric structure. Meanwhile, in the first to third graphs601,602, and603, when the applied voltage is equal to or greater than a breakdown voltage VBD, a weak level of breakdown may occur, and the leakage current may be increased.

FIGS.8to13are cross-sectional views schematically illustrating semiconductor devices according to various embodiments of the present disclosure. InFIGS.8to13, the same reference numerals denote the same components.FIG.8is a cross-sectional view schematically illustrating a semiconductor device2according to another embodiment of the present disclosure. In the semiconductor device2ofFIG.8, besides the components of the semiconductor device1ofFIG.5, a dielectric structure1010may further include an interfacial insulation layer201.

The interfacial insulation layer201may be disposed between a ferroelectric layer120and a dielectric layer130. The interfacial insulation layer201may suppress or reduce material exchanges between the ferroelectric layer120and the dielectric layer130. Accordingly, it is possible to prevent or alleviate the changes of the material composition of the ferroelectric layer120and the dielectric layer130. Therefore, the ferroelectricity of the ferroelectric layer120, associated withFIG.3, may be stabilized, and the non-ferroelectricity of the dielectric layer130, associated withFIG.2, may be stabilized. As a result, it is possible to reliably secure the capacitance of the dielectric structure1010through the series connection of the ferroelectric layer120and the dielectric layer130.

In addition, the interfacial insulation layer201may have a band gap energy that is greater than the band gap energy of each of the ferroelectric layer120and the dielectric layer130. Accordingly, the interfacial insulation layer201may form a potential barrier between the ferroelectric layer120and the dielectric layer130. As a result, the interfacial insulation layer201may reduce the leakage current that is generated at the interface between the ferroelectric layer120and the dielectric layer130, and the interfacial insulation layer201may increase the breakdown voltage of the dielectric structure1010during the operation of the semiconductor device2.

In an embodiment, the interfacial insulation layer201may have an amorphous crystal structure. The thickness of the interfacial insulation layer201may be sufficiently thin so that the crystal structure of the dielectric layer130in contact with the interfacial insulation layer201is influenced by the crystal structure of the ferroelectric layer120. Therefore, the dielectric layer130may grow into an epitaxial structure on the interfacial insulation layer201. That is, the dielectric layer130may have a crystal structure similar to that of the ferroelectric layer120despite the interfacial insulation layer201being inserted therebetween. However, the crystal structure of the dielectric layer130may be different from the crystal structure of the ferroelectric layer120. As an example, the ferroelectric layer120may have a crystal structure of an orthorhombic crystal system, while the dielectric layer130may have a crystal structure of a monoclinic crystal system or a tetragonal crystal system. The interfacial insulation layer201may include, for example, aluminum oxide, yttrium oxide, magnesium oxide, or a combination of two or more thereof.

FIG.9is a cross-sectional view schematically illustrating a semiconductor device3according to another embodiment of the present disclosure. Besides the components of the semiconductor device2ofFIG.8, the semiconductor device3ofFIG.9may further include an interfacial insulation layer202that is disposed between the dielectric layer130and the second electrode140. Hereinafter, the interfacial insulation layer201in the dielectric structure1010will be referred to as the first interfacial insulation layer201, and the interfacial insulation layer202that is disposed between the dielectric layer130and the second electrode140will be referred to as the second interfacial insulation layer202.

The second interfacial insulation layer202may suppress or reduce material exchanges between the dielectric layer130and the second electrode140. Accordingly, the change of the material composition of the dielectric layer130may be prevented or alleviated.

In addition, the band gap energy of the second interfacial insulation layer202may be greater than the band gap energy of the dielectric layer130. Accordingly, the second interfacial layer202may form a potential barrier between the dielectric layer130and the second electrode140. The second interfacial insulation layer202may reduce a leakage current that is generated at the interface between the dielectric layer130and the second electrode140during the operation of the semiconductor device3. As a result, the breakdown voltage of the semiconductor device3may be increased.

In an embodiment, the second interfacial insulation layer202may include, for example, aluminum oxide, yttrium oxide, magnesium oxide, or a combination of two or more thereof. The second interfacial insulation layer202may have an amorphous crystal structure.

FIG.10is a cross-sectional view schematically illustrating a semiconductor device4according to further another embodiment of the present disclosure. Besides the components of the semiconductor device3ofFIG.9, the semiconductor device4ofFIG.10may further include a reduction sacrificial layer203.

The reduction sacrificial layer203may be disposed between the second interfacial insulation layer202and the second electrode140. The reduction sacrificial layer203may serve to suppress or alleviate the second interfacial insulation layer202and the second electrode140from reacting with each other. That is, the reduction sacrificial layer203may react with the second electrode140in advance to form a compound layer, thereby preventing or alleviating the second interfacial insulation layer202from being reduced through a reaction with the second electrode140. Accordingly, the material composition of the second interfacial insulation layer202may be stably maintained. The reduction sacrificial layer203may include, for example, niobium oxide or titanium oxide.

FIG.11is a cross-sectional view schematically illustrating a semiconductor device5according to further another embodiment of the present disclosure. Besides the components of the semiconductor device3ofFIG.9, the semiconductor device5ofFIG.11may further include a third interfacial insulation layer204.

The third interfacial insulation layer204may be disposed between the first electrode110and the ferroelectric layer120. The third interfacial insulation layer204may suppress or reduce material exchanges between the first electrode110and the ferroelectric layer120. Accordingly, it is possible to prevent or alleviate the change of the material composition of the ferroelectric layer120.

In addition, the band gap energy of the third interfacial insulation layer204may be greater than the band gap energy of the ferroelectric layer120. Accordingly, the third interfacial insulation layer204may form a potential barrier between the first electrode110and the ferroelectric layer120. The third interfacial insulation layer204may reduce a leakage current that is generated at the interface between the first electrode110and the ferroelectric layer120during the operation of the semiconductor device5. As a result, the breakdown voltage of the semiconductor device5may be increased.

In an embodiment, the third interfacial insulation layer204may include, for example, aluminum oxide, yttrium oxide, magnesium oxide, or a combination of two or more thereof.

FIG.12is a cross-sectional view schematically illustrating a semiconductor device6according to yet another embodiment of the present disclosure. Besides the components of the semiconductor device ofFIG.9, the semiconductor device6ofFIG.12may further include a crystallization seed layer205.

The crystallization seed layer205may be disposed between the first electrode110and the ferroelectric layer120. The crystallization seed layer205may have a crystalline crystal structure and may induce the crystallization of the ferroelectric layer120. In an embodiment, the ferroelectric layer120may be formed in an amorphous material layer on the crystallization seed layer205and then may be converted to have a crystalline crystal structure through a crystallization heat treatment by using the crystallization seed layer205. The conversion into the crystalline structure of the ferroelectric layer120may improve the ferroelectricity of the ferroelectric layer120. The crystallization seed layer205may have a non-ferroelectric property.

Furthermore, the crystallization seed layer205may function as a buffer layer capable of reducing a difference in lattice constant between the first electrode110and the ferroelectric layer120. As an example, the crystallization seed layer205may have a lattice constant between the lattice constant of the first electrode110and the lattice constant of the ferroelectric layer120. The crystallization seed layer205may suppress or reduce defects that may occur at the interface where the first electrode110and the ferroelectric layer120directly contact each other. Accordingly, the crystallization seed layer205may reduce the leakage current that may occur at the interface between the first electrode110and the ferroelectric layer120. The crystallization seed layer205may include, for example, magnesium oxide or zirconium oxide.

FIG.13is a cross-sectional view schematically illustrating a semiconductor device7according to still yet another embodiment of the present disclosure. Referring toFIG.13, besides the components of the semiconductor device6ofFIG.10, the semiconductor device7may further include a third interfacial insulation layer204that is disposed between the first electrode110and the crystallization seed layer205. Accordingly, the semiconductor device7may perform the function of the third interfacial insulation layer204of the semiconductor device5, described with reference toFIG.11, and the function of the crystallization seed layer205of the semiconductor device6, described with reference toFIG.12, together. The configuration of the semiconductor device7may be substantially the same as that of the semiconductor device6ofFIG.10, except for the third interfacial insulation layer204. Accordingly, overlapping descriptions have been omitted.

FIG.14Ais a plan view schematically illustrating memory cells of an electronic device according to an embodiment of the present disclosure.FIG.14Bis a cross-sectional view of the memory cells ofFIG.14Ataken along line A-A′.FIG.14Cis a cross-sectional view of the memory cells ofFIG.14Ataken along line B-B′.

Referring toFIGS.14A to14C, each of the memory cells8may include a cell transistor including a buried word line308that is disposed in a substrate301, a bit line314, and a cell capacitor400.

The substrate301may include a semiconductor material. The substrate301may include device isolation layers303and active regions304. The active region304may be doped with an n-type or p-type dopant. Among the active regions304, cell regions may be doped with a p-type dopant. The active regions304may be defined as regions of the substrate301that are separated by the device isolation layers303. The device isolation layers303may be formed through a shallow trench isolation (STI) process and may be disposed in device isolation trenches302that are formed in the substrate301.

Referring toFIG.14C, word line trenches306may be formed in the substrate301. A gate insulation layer307may be disposed on an inner surface of each of the word line trenches306. The buried word line308may be disposed on the gate insulation layer307in each of the word line trenches306. The buried word line308may partially fill each of the word line trenches306.

A word line capping layer309may be disposed on the buried word line308in each of the word line trenches306. An upper surface308S of the buried word line308may be located at a lower level than a surface301S of the substrate301. The buried word line308may include a conductive material. In an embodiment, the buried word line308may be a thin film structure including a titanium nitride (TiN) layer and a tungsten (W) layer. In another embodiment, the buried word line308may include a single layer of titanium nitride (TiN) or a single layer of tungsten (W).

Referring toFIGS.14B and14C, first and second doping regions310and311may be disposed in the active regions304of the substrate301. The first and second doping regions310and311may be spaced apart from each other by the word line trenches306. One of the first and second doping regions310and311may be a source region of the cell transistor, and the other may be a drain region of the cell transistor. Each of the first and second doping regions310and311may include an n-type dopant, such as arsenide (As) or phosphorus (P).

As described above, the buried word line308and the first and second doping regions310and311may constitute the cell transistor. The buried word lines308may extend in the x-direction ofFIG.14A.

Referring toFIGS.14B and14C, a bit line contact plug313may be disposed on the substrate301. The bit line contact plug313may be electrically connected to the first doping region310. The bit line contact plug313may be disposed in a bit line contact hole312. The bit line contact hole312may be formed in the substrate301and a hard mask layer305that are disposed on the substrate301. A lower surface of the bit line contact plug313may be located at a lower level than the upper surface301S of the substrate301. The bit line contact plug313may include a conductive material. A bit line structure BL may be disposed on the bit line contact plug313. The bit line structure BL may include a bit line314in contact with the bit line contact plug313and a bit line hard mask315that is disposed on the bit line314.

Referring toFIGS.14A to14Ctogether, the bit lines314may extend in a direction (e.g., the y-direction) that crosses the buried word lines308. The bit lines314may be electrically connected to the first doping regions310through the bit line contact plugs313. Each of the bit lines314may include a conductive material. Each of the bit line hard masks315may include an insulation material.

A bit line spacer316may be disposed on sidewalls of each of the bit line structures BL. The bit line spacer316may extend to cover both sidewalls of each of the bit line contact plugs313. The bit line spacer316may include silicon oxide, silicon nitride, or a combination thereof. In another embodiment, the bit line spacer316may include an air gap. As an example, the bit line spacer316may have a nitride-air gap-nitride (NAN) structure in which an air gap is located between silicon nitride layers.

Storage node contact plugs (SNCs) may be disposed between the bit line structures BL. Each of the storage node contact plugs (SNCs) may be disposed in a storage node contact hole318. The storage node contact plugs (SNCs) may be electrically connected to the second doping regions311. In an embodiment, each of the storage node contact plugs (SNCs) may include a lower plug319and an upper plug321. Each of the storage node contact plugs (SNCs) may further include an ohmic contact layer320between the lower plug319and the upper plug321. In an embodiment, the upper plug321may include metal, the lower plug319may include doped silicon, and the ohmic contact layer320may include metal silicide.

Referring toFIG.14C, a plug isolation layer317may be disposed on the hard mask layer305. The plug isolation layer317may be an insulation layer that is disposed between neighboring bit line structures BL. The storage node contact holes318may penetrate the plug isolation layer317and the hard mask layer305to be formed over the active regions304.

Referring toFIGS.14A to14C, each cell capacitor400may be disposed on the storage node contact plug (SNC). Each of the cell capacitors400may have a configuration of one of the semiconductor device1ofFIG.5, the semiconductor device2ofFIG.8, the semiconductor device3ofFIG.9, the semiconductor device4ofFIG.10, the semiconductor device5ofFIG.11, the semiconductor device6ofFIG.12, and the semiconductor device7ofFIG.13. The configuration of the cell capacitor400will be described in more detail with reference to the embodiments ofFIGS.15A and15B,FIG.16,FIGS.17A and17B,FIGS.18A and18B,FIG.19,FIGS.20A and20B,FIG.21, andFIGS.22A and22Bbelow. In the descriptions with reference to the embodiments below, the expression of a singular form of a word herein may include the plural forms of the word unless clearly used otherwise in the context.

FIG.15Ais a cross-sectional view schematically illustrating a semiconductor device401according to an embodiment of the present disclosure.FIG.15Bis a cross-sectional view of the semiconductor device401ofFIG.15Ataken along line I-I′ and shown on the x-y plane. In an embodiment, the semiconductor device401may include a capacitor. As an example, the semiconductor device401may be applied to the cell capacitor400of the memory cell8ofFIGS.14A to14C.

Referring toFIG.15A, the semiconductor device401may have a three-dimensional structure. The semiconductor device401may include a pillar-shaped storage node electrode410a, a dielectric structure2001that is disposed on the storage node electrode410a, and a plate electrode440athat is disposed on the dielectric structure2001. The dielectric structure2001may include a capacitor dielectric layer420aand a barrier dielectric layer430athat are connected in series to each other. The capacitor dielectric layer420amay include a non-ferroelectric material, and the barrier dielectric layer430amay include a ferroelectric material. In the semiconductor device401, the storage node electrode410amay be an electrode to which an operating voltage is applied, and the plate electrode440amay be a ground electrode.

In an embodiment, the storage node electrode410amay be disposed on the storage node contact plug (SNC) of the memory cell8, described above with reference toFIGS.14A to14C. The storage node electrode410amay be electrically connected to a second doping region311of a substrate301through the storage node contact plug (SNC).

Referring toFIGS.15A and15B, the storage node electrode410amay include a pillar-shaped conductive structure. The capacitor dielectric layer420amay be disposed to cover the storage node electrode410a. The barrier dielectric layer430amay be disposed to cover the capacitor dielectric layer420a. The plate electrode440amay be disposed to cover the barrier dielectric layer430a.

In an embodiment, the semiconductor device401may correspond to the semiconductor device1, described with reference toFIG.5. As an example, the storage node electrode410a, the dielectric structure2001, and the plate electrode440aof the semiconductor device401may correspond to the second electrode140, the dielectric structure1000, and the first electrode110of the semiconductor device1, respectively.

As described above with reference toFIGS.1to4, the thickness ratio between the barrier dielectric layer430aand the capacitor dielectric layer420amay be controlled within a predetermined range. Accordingly, the barrier dielectric layer430amay exhibit the ferroelectric characteristics as illustrated inFIG.3. In addition, the dielectric structure2001including the barrier dielectric layer430aand the capacitor dielectric layer420a, connected in series to each other, with the thickness ratio within the predetermined range, may have non-ferroelectricity, described above with reference toFIG.4. That is, the capacitance of the dielectric structure2001may be substantially the same as the capacitance of the capacitor dielectric layer420a. Each of the capacitor dielectric layer420aand the barrier dielectric layer430amay have, for example, a thickness of 1 nm to 5 nm.

As for the storage node electrode410a, the pillar-shaped conductive structure may directly function as an electrode. That is, the dielectric structure2001may be directly disposed on the pillar-shaped conductive structure. The conductive structure may include, for example, doped silicon (Si), gold (Au), silver (Ag), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

Referring toFIGS.15A and15B, in the semiconductor device401of a three-dimensional structure, the capacitor dielectric layer420amay be disposed closer to the storage node electrode410athan the barrier dielectric layer430a. According to an embodiment of the present disclosure, when a voltage is applied between the storage node electrode410aand the plate electrode440a, in a case in which the barrier dielectric layer430ais disposed to surround the capacitor dielectric layer420awith respect to the storage node electrode410a, a depolarization electric field that is formed toward the barrier dielectric layer430a, that is, in an inner direction of the barrier dielectric layer430a, as shown inFIG.15B, at the interface S1between the capacitor dielectric layer420aand the barrier dielectric layer430a, may be relatively increased compared to a case in which the capacitor dielectric layer420ais disposed to surround the barrier dielectric layer430a.

That is, inFIG.15B, for example, when a positive bias is applied to the storage node electrode410ain a state in which the plate electrode440ais grounded, ferroelectric polarization FD may be formed inside the barrier dielectric layer430ain a direction substantially perpendicular to an outer circumferential surface S0of the storage node electrode410a. In this case, the negative charges that are generated by the ferroelectric polarization FD might not be sufficiently offset by the positive charges inside the capacitor dielectric layer420aat the interface S1between the capacitor dielectric layer420aand the barrier dielectric layer430a. Accordingly, the depolarization electric field, sufficient to suppress the ferroelectric polarization FD, may be easily formed in the barrier dielectric layer430ahaving ferroelectricity. As a result, the dielectric structure2001may be effectively controlled to have substantially the same capacitance as the capacitor dielectric layer420a. In addition, when an operating voltage is applied to the storage node electrode410ain a state in which the plate electrode440ais grounded, a relatively high electric field may be applied to the capacitor dielectric layer420athat is disposed to be closer to the storage node electrode410a, between the capacitor dielectric layer420aand the barrier dielectric layer430a. Accordingly, a relatively low electric field may be applied to the barrier dielectric layer430a, so that the ferroelectric hysteresis behavior of the barrier dielectric layer430amay be relatively mitigated. As a result, the dielectric structure2001may have the same dielectric characteristics as in the electric circuit ofFIG.4.

Although not illustrated inFIGS.15A and15B, in some embodiments, the semiconductor device401may further include a first interfacial insulation layer that is disposed between the capacitor dielectric layer420aand the barrier dielectric layer430a. The first interfacial insulation layer may correspond to the interfacial insulation layer201that is disposed between the ferroelectric layer120and the dielectric layer130in the semiconductor device2, described with reference toFIG.8.

Although not illustrated inFIGS.15A and15B, in some embodiments, the semiconductor device401may further include the first interfacial insulation layer that is disposed between the capacitor dielectric layer420aand the barrier dielectric layer430a, and a second interfacial insulation layer that is disposed between the capacitor dielectric layer420aand the storage node electrode410a. The first interfacial insulation layer and the second interfacial insulation layer may correspond to the first interfacial insulation layer201that is disposed between the ferroelectric layer120and the dielectric layer130, and the second interfacial insulation layer202that is disposed between the dielectric layer130and the second electrode140in the semiconductor device3, described with reference toFIG.9, respectively.

Although not illustrated inFIGS.15A and15B, in some embodiments, the semiconductor device401may further include the first interfacial insulation layer that is disposed between the capacitor dielectric layer420aand the barrier dielectric layer430a, the second interfacial insulation layer that is disposed between the capacitor dielectric layer420aand the storage node electrode410a, and a third interfacial insulation layer that is disposed between the barrier dielectric layer430aand the plate electrode440a. The first interfacial insulation layer, the second interfacial insulation layer, and the third interfacial insulation layer may correspond to the first interfacial insulation layer201that is disposed between the ferroelectric layer120and the dielectric layer130, the second interfacial insulation layer202that is disposed between the dielectric layer130and the second electrode140, and the third interfacial insulation layer204that is disposed between the ferroelectric layer120and the first electrode110in the semiconductor device5, described with reference toFIG.11, respectively.

Although not illustrated inFIGS.15A and15B, in some embodiments, the semiconductor device401may further include a reduction sacrificial layer that is disposed between the second interfacial insulation layer and the storage node electrode410a. The reduction sacrificial layer may correspond to the reduction sacrificial layer203that is disposed between the interfacial insulation layer202and the second electrode140in the semiconductor device4, described with reference toFIG.10.

FIG.16is a cross-sectional view schematically illustrating a semiconductor device402according to another embodiment of the present disclosure. Referring toFIG.16, besides the components of the semiconductor device401ofFIGS.15A and15B, the semiconductor device402may further include supporters450athat connect the storage node electrodes410ato each other. The supporters450amay serve to physically support the outer walls of the storage node electrodes410a. The supporters450amay improve the structural stability of the storage node electrodes410a. Each of the supporters450amay include, for example, silicon nitride. InFIG.16, one supporter450amay be disposed on the outer wall of each of the storage node electrodes410aalong a height direction (i.e., the z-direction) of the storage node electrode410a, but the present disclosure is not necessarily limited thereto. In some embodiments, two or more supporters may be disposed on the outer wall of each of the storage node electrodes410aalong the height direction (i.e., the z-direction) of the storage node electrode410a.

FIG.17Ais a cross-sectional view schematically illustrating a semiconductor device403according to further another embodiment of the present disclosure.FIG.17Bis a cross-sectional view of the semiconductor device403ofFIG.17Ataken along line II-II′ and shown on the x-y plane. In an embodiment, the semiconductor device403may include a capacitor device. As an example, the semiconductor device403may be applied to the cell capacitor400of the memory cell8ofFIGS.14A to14C.

Referring toFIGS.17A and17B, the semiconductor device403may be different from the semiconductor device401, described with reference toFIGS.15A and15Bin the configuration of a storage node electrode410b. The configuration of the semiconductor device403may be substantially the same as the configuration of the semiconductor device401ofFIGS.15A and15B, except for the storage node electrode410b. That is, the configurations of a dielectric structure2002including a capacitor dielectric layer420band a barrier dielectric layer430b, and the plate electrode440bof the semiconductor device403may be substantially the same as the configurations of the dielectric structure2002including the capacitor dielectric layer420aand the barrier dielectric layer430a, and the plate electrode440aof the semiconductor device401ofFIGS.15A and15B, respectively.

Referring toFIGS.17A and17B, the storage node electrode410bmay include a filling structure460that fills a trench pattern formed in a pillar-shaped conductive structure. The filling structure460may be a pillar-shaped structure that has a predetermined cross-sectional area and extends in the z-direction. As an example, the filling structure460may have a cylindrical shape. However, in another example, the filling structure460may have a polygonal pillar shape.

In an embodiment, the filling structure460may include a silicon (Si) layer. The silicon (Si) layer may be doped to have conductivity. Alternatively, the silicon (Si) layer may have an un-doped state. In an embodiment, in order to form the filling structure460, the pillar-shaped conductive structure, described above with reference toFIGS.15A and15B, may be formed, and then, the trench pattern may be formed in the conductive structure. The trench pattern may extend from an upper surface US of the pillar-shaped conductive structure to a lower surface LS. Subsequently, the trench pattern may be filled with silicon (Si) to form the filling structure460.

Referring toFIGS.17A and17B, the dielectric structure2002and the plate electrode440bmay be sequentially disposed on the storage node electrode410bincluding the filling structure460. The capacitor dielectric layer420bof the dielectric structure2002may be disposed on the storage node electrode410b, and the barrier dielectric layer430bmay be disposed on the capacitor dielectric layer420b.

FIG.18Ais a cross-sectional view schematically illustrating a semiconductor device404according to further another embodiment of the present disclosure.FIG.18Bis a cross-sectional view of the semiconductor device404ofFIG.18Ataken along line III-III′ and shown on the x-y plane. In an embodiment, the semiconductor device404may include a capacitor device. As an example, the semiconductor device404may be applied to the cell capacitor400of the memory cell8ofFIGS.14A to14C.

Referring toFIG.18A, the semiconductor device404may have a three-dimensional structure. The semiconductor device404may include a cylinder-shaped storage node electrode410c, a dielectric structure2003that is disposed on the storage node electrode410c, and a plate electrode440cthat is disposed on the dielectric structure2003. The dielectric structure2003may include a capacitor dielectric layer420cand a barrier dielectric layer430cthat are connected in series to each other. The capacitor dielectric layer420cmay include a non-ferroelectric material, and the barrier dielectric layer430cmay include a ferroelectric material. In the semiconductor device404, the storage node electrode410cmay be an electrode to which an operating voltage is applied, and the plate electrode440cmay be a ground electrode.

The semiconductor device404may be different from the semiconductor device401ofFIGS.15A and15Bin the shape of the storage nod electrode410c. The configuration of the semiconductor device404, except for the shape of the storage node electrode410c, may be substantially the same as the configuration of the semiconductor device401ofFIGS.15A and15B. Referring toFIGS.18A and18B, the storage node electrode410cmay have a cylindrical shape. Accordingly, the capacitor dielectric layer420cof the dielectric structure2003may be disposed to cover the inner wall surface IW and the outer wall surface OW of the storage node electrode410c. The barrier dielectric layer430cmay be disposed on the capacitor dielectric layer420c. The plate electrode440cmay be disposed to cover the barrier dielectric layer430c.

FIG.19is a cross-sectional view schematically illustrating a semiconductor device405according to further another embodiment of the present disclosure. Referring toFIG.19, besides the components of the semiconductor device404ofFIGS.18A and18B, the semiconductor device405may further include supporters450cthat connect the storage node electrodes410cto each other. The supporters450cmay serve to physically support the outer walls of the storage node electrodes410c. The supporters450cmay improve structural stability of the storage node electrodes410c. Each of the supporters450cmay include, for example, silicon nitride. InFIG.19, one supporter450cmay be disposed on the outer wall of each of the storage node electrodes410calong the height direction (i.e., the z-direction) of the storage node electrode410c, but the present disclosure is not necessarily limited thereto. In some embodiments, two or more supporters may be disposed on an outer wall of each of the storage node electrodes410calong the height direction (i.e., the z-direction) of the storage node electrode410c.

FIG.20Ais a cross-sectional view schematically illustrating a semiconductor device406according to further another embodiment of the present disclosure.FIG.20Bis a cross-sectional view of the semiconductor device406ofFIG.20Ataken along line IV-IV′ and shown on the x-y plane. In an embodiment, the semiconductor device406may be applied to the cell capacitor400of the memory cell8ofFIGS.14A to14C.

Referring toFIG.20A, the semiconductor device406may include a three-dimensional structure. The semiconductor device406may include a storage node electrode410dof a three-dimensional structure, a dielectric structure2004that is disposed on the storage node electrode410d, and a plate electrode440dthat is disposed on the dielectric structure2004. The dielectric structure2004may include a capacitor dielectric layer420dand a barrier dielectric layer430dthat are connected in series to each other. The capacitor dielectric layer420dmay include a non-ferroelectric material, and the barrier dielectric layer430dmay include a ferroelectric material. In the semiconductor device406, the storage node electrode410dmay be an electrode to which an operating voltage is applied, and the plate electrode440dmay be a ground electrode.

The semiconductor device406may be different from the semiconductor device401ofFIGS.15A and15Bin the shape of the storage node electrode410d. The configuration of the semiconductor device406, except for the shape of the storage node electrode410d, may be substantially the same as the configuration of the semiconductor device401ofFIGS.15A and15B. Referring toFIGS.20A and20B, the storage node electrode410dmay have a composite shape in which the pillar shape of the storage node electrode410a, illustrated inFIGS.15A and15B, and the cylinder shape of the storage node electrode410c, illustrated inFIGS.18A and18B, are combined. The capacitor dielectric420dof the dielectric structure2004may be disposed to cover the inner wall surface IW′ and the outer wall surface OW′ of the storage node electrode410d.

FIG.21is a cross-sectional view schematically illustrating a semiconductor device407according to further another embodiment of the present disclosure. Referring toFIG.21, besides the components of the semiconductor device406ofFIGS.20A and20B, the semiconductor device407may further include supporters450dthat connect storage node electrodes410d. The supporters450dmay serve to physically support the outer walls of the storage node electrodes410d. The supporters450dmay improve the structural stability of the storage node electrodes410d. Each of the supporters450dmay include, for example, silicon nitride. InFIG.21, one supporter450dmay be disposed on the outer wall of each of the storage node electrodes410dalong the height direction (i.e., the z-direction) of the storage node electrode410d, but the present disclosure is not necessarily limited thereto. In some embodiments, two or more supporters may be disposed on the outer wall of each of the storage node electrodes410dalong the height direction (i.e., the z-direction) of the storage node electrode410d.

FIG.22Ais a cross-sectional view schematically illustrating a semiconductor device408according to further another embodiment of the present disclosure.FIG.22Bis a cross-sectional view of the semiconductor device408ofFIG.22Ataken along line V-V′ and shown on the x-y plane. In an embodiment, the semiconductor device408may include a capacitor. As an example, the semiconductor device408may be applied to the cell capacitor400of the memory cell8ofFIGS.14A to14C.

Referring toFIG.22A, the semiconductor device408may include a concave-shaped storage node electrode410e, a dielectric structure2005that is disposed on the storage node electrode410e, and a plate electrode440ethat is disposed on the dielectric structure2005. The dielectric structure2005may include a capacitor dielectric layer420eand a barrier dielectric layer430ethat are connected in series to each other.

Referring toFIGS.22A and22B, the semiconductor device408may be different from the semiconductor device401ofFIGS.15A and15Bin the configuration of the storage node electrode410e. The configuration of the semiconductor device408, except for the storage node electrode410e, may be substantially the same as the configuration of the semiconductor device401ofFIGS.15A and15B.

The storage node electrode410emay have a three-dimensional structure having a concave shape HP. In an embodiment, the dielectric structure2005may be disposed on an inner wall surface IW″ and an upper surface UW″ of the storage node electrode410e. A device isolation layer470may be disposed on outer wall surface OW″ of the storage node electrode410e. The device isolation layer470may insulate neighboring storage node electrodes410efrom each other.

In an embodiment, the capacitor dielectric layer420emay be disposed on the inner wall surface IW″ and the upper surface OW″ of the storage node electrode410e, and the barrier dielectric layer430emay be disposed on the capacitor dielectric layer420e. The plate electrode440emay be disposed to cover the dielectric structure2005.

As described above, according to various embodiments of the present disclosure, each of the semiconductor devices may include a dielectric structure including a barrier dielectric layer and a capacitor dielectric layer that are connected in series to each other. The capacitance of the dielectric structure may be controlled to have substantially the same value as the capacitance of the capacitor dielectric layer, so that the capacitor dielectric layer may function as a substantial information storage dielectric layer of the semiconductor device. The barrier dielectric layer may be a barrier layer having a predetermined thickness, and may function to prevent or alleviate the deterioration of leakage current and breakdown voltage characteristics of the dielectric structure. Accordingly, according to the embodiments of the present disclosure, it is possible to provide semiconductor devices capable of effectively securing a desired capacitance while preventing or alleviating the deterioration of leakage current and breakdown voltage characteristics.

Meanwhile, in an embodiment of the present disclosure, the dielectric structure including the dielectric layer and the ferroelectric layer described above with reference toFIGS.1to4may be applied as a gate dielectric structure of a field effect transistor. The field effect transistors including the gate dielectric structure may be described in more detail through various embodiments with reference toFIGS.23to25,26A,26B,27A,27B,27C,28A,28B, and28Cbelow.

FIG.23is a cross-sectional view schematically illustrating a semiconductor device9including a gate dielectric structure according to an embodiment of the present disclosure. The semiconductor device9ofFIG.23may include a field effect transistor.

Referring toFIG.23, the semiconductor device9may include a substrate1001having a channel region1002, a gate dielectric structure G9that is disposed over the channel region1002, and a gate electrode1050that is disposed on the gate dielectric structure G9. In addition, the semiconductor device9may include a source region1003and a drain region1005that are respectively disposed at opposite edges of the channel region1002. The source region1003and the drain region1005may be portions of the substrate1001.

The gate dielectric structure G9may include a barrier dielectric layer1010and a gate dielectric layer1030that are connected in series to each other. The barrier dielectric layer1010may include a ferroelectric material, and the gate dielectric layer1030may include a non-ferroelectric material. The gate dielectric layer1030may have polarization characteristics, described above with reference toFIG.2. The barrier dielectric layer1010may have the polarization characteristics, illustrated inFIG.3, through bonding with the gate dielectric layer1030. In an embodiment, the thickness of the barrier dielectric layer1010may be equal to or less than 5 nm, and the thickness of the barrier dielectric layer1010may be substantially the same as or thinner than the thickness of the gate dielectric layer1030. In this case, when the thickness ratio between the barrier dielectric layer1010and the gate dielectric layer1030is distributed within a predetermined range, the barrier dielectric layer1010may have ferroelectric polarization characteristics in line with the graph ofFIG.3as opposed to the graph ofFIG.1. In addition, the gate dielectric structure G9including the barrier dielectric layer1010and the gate dielectric layer1030that are connected in series to each other with a thickness ratio within the predetermined range may have the non-ferroelectricity, described above with reference toFIG.4.

Referring toFIG.23, the substrate1001may be provided. The substrate1001may include a semiconductor material. Specifically, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. The substrate1001may be doped with an n-type or p-type dopant to have predetermined conductivity. In an embodiment, the substrate1001may be a single crystalline silicon substrate that is doped with an n-type or p-type dopant.

The channel region1002may be a region of the substrate1001that is positioned directly below the gate dielectric structure G9. The channel region1002may be a region of the substrate1001in which a conductive channel is formed when a gate voltage equal to or greater than a threshold voltage is applied between the gate electrode layer1050and the substrate1001. The conductive channel may electrically connect the source region1003and the drain region1005to each other. Accordingly, when a voltage is applied between the source region1003and the drain region1005, electrical carriers, such as electrons or holes, may conduct through the conductive channel.

The barrier dielectric layer1010may be disposed over the channel region1002. As illustrated inFIG.23, the barrier dielectric layer1010may be disposed on a surface1001S of the substrate1001. The barrier dielectric layer1010may include a ferroelectric material. In an embodiment, the barrier dielectric layer1010may include a hafnium zirconium oxide layer. In another embodiment, the barrier dielectric layer1010may include a dopant that is doped in the hafnium zirconium oxide layer. The dopant may stabilize the ferroelectricity of the barrier dielectric layer1010. The dopant may include, for example, carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr)), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), lanthanum (La), or a combination of two or more thereof.

In an embodiment, the barrier dielectric layer1010may have a crystal structure of an orthorhombic crystal system. The barrier dielectric layer1010may have a thickness of 1 nm to 5 nm, for example. The barrier dielectric layer1010may have a single crystalline structure or a polycrystalline structure. In an embodiment, the barrier dielectric layer1010may be an epi-growth layer. The barrier dielectric layer1010may be formed epitaxially over the channel region1002through, for example, atomic layer deposition, pulsed layer deposition, or chemical vapor deposition.

The gate dielectric layer1030may be disposed on the barrier dielectric layer1010. The gate dielectric layer1030may have the non-ferroelectricity of the dielectric layer20D, described above with reference toFIGS.2and3. The gate dielectric layer1030may have paraelectricity, for example. The gate dielectric layer1030may have substantially the same dielectric characteristics as the dielectric layer20D of the dielectric structure40D, described with reference toFIG.4.

The gate dielectric layer1030may include a non-ferroelectric material. In an embodiment, the gate dielectric layer1030may include hafnium oxide, zirconium oxide, or a combination thereof. The gate dielectric layer1030may have a crystal structure of a monoclinic crystal system or a tetragonal crystal system. The gate dielectric layer1030may have a thickness of 1 nm to 5 nm, for example.

In an embodiment, the gate dielectric layer1030may be an epi-growth layer. The gate dielectric layer1030may be epitaxially formed on the barrier dielectric layer1010through, for example, atomic layer deposition, pulsed layer deposition, or chemical vapor deposition.

The gate electrode1050may be disposed on the gate dielectric layer1030. The gate electrode1050may include a conductive material. The conductive material may include, for example, doped silicon (Si), gold (Au), silver (Ag), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

Referring toFIG.23again, the source region1003and the drain region1005may be disposed to be spaced apart from each other. The source region1003and the drain region1005may be doped with a dopant of different doping type from the substrate1001. As an example, when the substrate1001is doped with a p-type dopant, the source region1003and the drain region1005may be doped with an n-type dopant. As another example, when the substrate1001is doped with an n-type dopant, the source region1003and the drain region1005may be doped with a p-type dopant.

In some embodiments, the stacking order of the barrier dielectric layer1010and the gate dielectric layer1030over the channel region1002may be changed. That is, as an example, the gate dielectric layer1030may be disposed on the surface1001S of the substrate1001, and the barrier dielectric layer1010may be disposed on the gate dielectric layer1030. The gate electrode1050may be disposed on the barrier dielectric layer1010.

In some embodiments, an interfacial insulation layer may be disposed between the barrier dielectric layer1010and the gate dielectric layer1030. The interfacial insulation layer may suppress or reduce material exchanges between the barrier dielectric layer1010and the gate dielectric layer1030. Accordingly, the material composition of each of the barrier dielectric layer1010and the gate dielectric layer1030may be prevented or alleviated from being changed. In addition, the interfacial insulation layer may have a band gap energy that is greater than a band gap energy of each of the barrier dielectric layer1010and the gate dielectric layer1030, thereby forming a potential barrier between the barrier dielectric layer1010and the gate dielectric layer1030. The interfacial insulation layer may correspond to the interfacial insulation layer201of the semiconductor device2, described with reference toFIG.8.

In some embodiments, another interfacial insulation layer may be disposed between the gate dielectric layer1030and the gate electrode1050. The another interfacial insulation layer that is disposed between the gate dielectric layer1030and the gate electrode1050may suppress or reduce material exchanges between the gate dielectric layer1030and the gate electrode1050and may form a potential barrier between the gate dielectric layer1030and the gate electrode1050. In addition, further another interfacial insulation layer may be disposed between the substrate1001and the barrier dielectric layer1010. The further another interfacial insulation layer that is disposed between the substrate1001and the barrier dielectric layer1010may suppress or reduce material exchanges between the substrate1001and the barrier dielectric layer1010, and may form a potential barrier between the substrate1001and the barrier dielectric layer1010. The another interfacial insulation layer that is disposed between the gate dielectric layer1030and the gate electrode1050and the further another interfacial insulation layer that is disposed between the substrate1001and the barrier dielectric layer1010may correspond to the second and third interfacial insulation layers202and204of the semiconductor device5described with reference toFIG.11, respectively.

As described above, according to the embodiments of the present disclosure, the gate dielectric structure of a semiconductor device may include a barrier dielectric layer and a gate dielectric layer that are connected in series to each other. The barrier dielectric layer may include a ferroelectric material, and the gate dielectric layer may include a non-ferroelectric material. The capacitance of the gate dielectric structure may be controlled to have substantially the same value as the capacitance of the gate dielectric layer. The barrier dielectric layer may be a barrier layer having a predetermined thickness and may function to prevent or alleviate the deterioration of leakage current and breakdown voltage characteristics of the gate dielectric structure. Accordingly, according to the embodiments of the present disclosure, it is possible to provide a semiconductor device including a gate dielectric structure capable of effectively securing a desired capacitance while preventing or alleviating the deterioration of the leakage current and breakdown voltage characteristics.

FIG.24is a cross-sectional view schematically illustrating a semiconductor device10including a gate dielectric structure G10according to an embodiment of the present disclosure. The semiconductor device10ofFIG.24may include a field effect transistor. The semiconductor device10ofFIG.24may be different from the semiconductor device9ofFIG.23in the configurations of the gate dielectric structure G10and a gate electrode1150.

Referring toFIG.24, the semiconductor device10may include a substrate1101, a recess space R10that is formed in the substrate1101, the gate dielectric structure G10that is disposed in the recess space R10, and the gate electrode1150that is disposed on the gate dielectric structure G10. The gate dielectric structure G10may include a barrier dielectric layer1110and a gate dielectric layer1130. In addition, the semiconductor device10may include a source region1103and a drain region1105that are disposed in regions of the substrate1101, located at opposite sides of the recess space R10. In this case, a channel region1102of the semiconductor device10may be formed in an inner region of the substrate1101along an interface with the gate dielectric structure G10.

The material composition of the substrate1101, the source region1103, the drain region1105, the gate dielectric structure G10, and the gate electrode1150may be substantially the same as the material composition of the substrate1001, the source region1003, the drain region1005, the gate dielectric structure G9, and the gate electrode1050, described above with reference toFIG.23.

However, in the semiconductor device9ofFIG.23, the gate dielectric structure G9and the gate electrode1050may be disposed on the substrate1001, whereas in the semiconductor device ofFIG.24, a portion of each of the gate dielectric structure G10and the gate electrode1150may be disposed in the recess region R10that is formed into the substrate1101from the surface1101S of the substrate1101. In addition, another portion of each of the gate dielectric structure G10and the gate electrode1150may be located over the surface1101S of the substrate1101. Compared to the semiconductor device9ofFIG.23, the semiconductor device10may include the recess region R10, so that it is possible to secure a relatively increased channel region1102.

In an embodiment, in the gate dielectric structure G10, the barrier dielectric layer1110may be disposed closer to the channel region1102than the gate dielectric layer1130. Accordingly, the barrier dielectric layer1110may be disposed along an inner wall of the recess region R10, and the gate dielectric layer1130may be disposed on the barrier dielectric layer1110. Referring toFIG.24, the gate electrode1150, the gate dielectric layer1130, and the barrier dielectric layer1110may be respectively disposed to have convex-curved surfaces based on the recess region R10. The barrier dielectric layer1110having ferroelectricity may be disposed to surround the convex curved surface of the gate dielectric layer1130, having non-ferroelectricity with respect to the gate electrode1150, so that the electrical charges that are formed by the spontaneous polarization of the barrier dielectric layer1110might not be sufficiently canceled by the electrical charges inside the gate dielectric layer1130, as described above with reference toFIG.15B. Accordingly, a depolarization electric field that is sufficient in suppressing the spontaneous polarization may be formed in the barrier dielectric layer1110having ferroelectricity. As a result, the gate dielectric structure G10may be effectively controlled to have a capacitance that is substantially equal to the capacitance of the gate dielectric layer1130.

In an embodiment, the semiconductor device10ofFIG.24may be applied to the transistor of the memory cell8, described above with reference toFIGS.14A to14C. The substrate1101, the source region1103, the drain region1105, the gate dielectric structure G10, and the gate electrode1150of the semiconductor device10may correspond to the substrate301, the first doping region310, the second doping region311, the gate insulation layer307, and the gate electrode308of the semiconductor device8ofFIGS.14A to14C, respectively.

FIG.25is a cross-sectional view schematically illustrating a semiconductor device11including a gate dielectric structure G11according to further another embodiment of the present disclosure. The semiconductor device11ofFIG.25may include a field effect transistor. The semiconductor device11ofFIG.25may be different from the semiconductor device9ofFIG.23in the configurations of the gate dielectric structure G11and a gate electrode1250.

Referring toFIG.25, the semiconductor device11may include a substrate1201, a recess space R11that is formed in the substrate1201, the gate dielectric structure G11that is disposed in the recess space R11, and the gate electrode1250that is disposed on the gate dielectric structure G11in the recess space R11. The gate dielectric structure G11may include a barrier dielectric layer1210and a gate dielectric layer1230. In addition, the semiconductor device11may include a source region1203and a drain region1205that are disposed in the regions of the substrate1201at opposite edges of the recess space R11. In this case, a channel region1202of the semiconductor device11may be formed in an inner region of the substrate1201along an interface with the gate dielectric structure G11.

The material composition of the substrate1201, the source region1203, the drain region1205, the gate dielectric structure G11, and the gate electrode1250may be substantially the same as the material composition of the substrate1001, the source region1003, the drain region1005, the gate dielectric structure G9, and the gate electrode1050, described above with reference toFIG.23, respectively.

However, in the semiconductor device9ofFIG.23, the gate dielectric structure G9and the gate electrode1050may be disposed on the substrate1001, whereas in the semiconductor device11ofFIG.25, all of the gate dielectric structure G11and the gate electrode1250may be disposed in the recess space R11that is formed into the substrate1201from the surface1201S of the substrate1201. Accordingly, an upper surface G11S of the gate dielectric structure G11and an upper surface1250S of the gate electrode1250may be positioned at a lower level than the surface1201S of the substrate1201. Compared to the semiconductor device9ofFIG.23, the semiconductor device11may include the recess space R11, so that it is possible to secure the relatively increased channel region1202.

In an embodiment, in the gate dielectric structure G11, the barrier dielectric layer1210may be disposed to be closer to the channel region1202than the gate dielectric layer1230. Accordingly, the barrier dielectric layer1210may be disposed along an inner wall surface of the recess region R11, and the gate dielectric layer1230may be disposed on the barrier dielectric layer1210. Referring toFIG.25, the gate electrode1250, the gate dielectric layer1230, and the barrier dielectric layer1210may be disposed to have convex-curved surfaces toward the recess region R11. With respect to the gate electrode1250, the barrier dielectric layer1210having ferroelectricity may be disposed to surround the gate dielectric layer1230having non-ferroelectricity so that the magnitude of the depolarization electric field in the barrier dielectric layer1210having ferroelectricity may be increased, as described above with reference toFIG.15B. Accordingly, controlling the capacitance of the gate dielectric structure G11to be the same as the capacitance of the gate dielectric layer1230may be more effectively performed.

In an embodiment, the semiconductor device11ofFIG.25may be applied to the transistor of the memory cell8, described above with reference toFIGS.14A to14C. The substrate1201, the source region1203, the drain region1205, the gate dielectric structure G11, and the gate electrode1250of the semiconductor device11may correspond to the substrate301, the first doping region310, the second doping region311, the gate dielectric layer307, and the gate electrode308of the semiconductor device10ofFIGS.14A to14C, respectively.

FIG.26Ais a perspective view schematically illustrating a semiconductor device12according to further another embodiment of the present disclosure.FIG.26Bis a cross-sectional view of the semiconductor device12ofFIG.26Ataken along line IV-IV′. In an embodiment, the semiconductor device12ofFIGS.26A and26Bmay include a transistor of a three-dimensional structure. In addition, the semiconductor device12may include a conductive channel formed in a fin structure that is an active layer.

Referring toFIGS.26A and26B, the semiconductor device12may include a fin structure1301a, extending in a direction (e.g., the z-direction) that is substantially perpendicular to a surface1301S of a substrate1301, a base insulation layer1370that is disposed on the substrate1301to cover a portion of the fin structure1301a, a gate dielectric structure G12that is disposed on the base insulation layer1370to cover a portion of the fin structure1301a, and a gate electrode1350that is disposed over the base insulation layer1370to cover the gate dielectric structure G12. The gate dielectric structure G12may include a barrier dielectric layer1310and a gate dielectric layer1330that are connected in series to each other. The barrier dielectric layer1310may include a ferroelectric material, and the gate dielectric layer1330may include a non-ferroelectric material. In addition, the semiconductor device12may include a source region1303and a drain region1305that are formed in different portions of the fin structure1301a.

The substrate1301may include a semiconductor material. The substrate1301may be doped with an n-type or p-type dopant. The fin structure1301amay be disposed on the substrate1301to extend in a direction (e.g., the z-direction) that is perpendicular to the surface1301S of the substrate1301and in a direction (e.g., the y-direction) that is parallel to the surface1301S of the substrate1301. The fin structure1301amay be made of substantially the same material as the substrate1301. In an embodiment, the fin structure1301amay be formed by patterning the substrate1301. The fin structure1301amay correspond to an active layer for the electrical switching operation of the semiconductor device12.

The base insulation layer1370may be disposed on the substrate1301to cover the fin structure1301aby a predetermined height H. The base insulation layer1370may include, for example, oxide, nitride, oxynitride, or a combination of two or more thereof.

A portion of the fin structure1301a, protruding above the base insulation layer1370, may be covered by the gate dielectric structure G12and the gate electrode1350. Referring toFIG.26B, the portion of the fin structure1301a, covered by the gate dielectric structure G12and the gate electrode1350, may correspond to the channel region1302.

In an embodiment, the gate dielectric structure G12may have substantially the same dielectric characteristics as the gate dielectric structure G9of the semiconductor device9, described above with reference toFIG.23. That is, the gate dielectric layer1330may have the polarization characteristics, described above with reference toFIG.2. The barrier dielectric layer1310may have the polarization characteristics, illustrated inFIG.3, through bonding with the gate dielectric layer1330. In an embodiment, the thickness of the barrier dielectric layer1310may be 5 nm or less, and the thickness of the barrier dielectric layer1310may be substantially the same as or thinner than the thickness of the gate dielectric layer1330. In this case, when the thickness ratio between the barrier dielectric layer1310and the gate dielectric layer1330is distributed within a predetermined range, the barrier dielectric layer1310may have ferroelectric polarization characteristics in line with the graph ofFIG.3rather than the graph ofFIG.1. In addition, the gate dielectric structure G12including the barrier dielectric layer1310and the gate dielectric layer1330having the thickness ratio within the predetermined range and connected in series to each other may have non-ferroelectricity, described above with reference toFIG.4.

In an embodiment, the gate dielectric layer1330may be disposed to surround the channel region1302of the fin structure1301aon the base insulation layer1370, and the barrier dielectric layer1310may be disposed to cover the gate dielectric layer1330. Referring toFIG.26B, the fin structure1301a, the gate dielectric layer1330, and the barrier dielectric layer1310may be disposed to protrude upward (i.e., the z-direction) from a surface1370S of the base insulation layer1370. Based on the protruding fin structure1301a, the barrier dielectric layer1310having ferroelectricity may be disposed to surround the protruding portion of the gate dielectric layer1330having non-ferroelectricity. Accordingly, the electrical charges that are formed by the spontaneous polarization of the barrier dielectric layer1310might not be sufficiently canceled by the electrical charges inside the gate dielectric layer1330as described above with reference toFIG.15B. Accordingly, the depolarization electric field that is sufficient in suppressing the spontaneous polarization may be formed in the barrier dielectric layer1310. As a result, the gate dielectric structure G12may be effectively controlled to have a capacitance substantially equal to the capacitance of the gate dielectric layer1330.

Referring toFIGS.26A and26Bagain, the portion of the fin structure1301aprotruding above the base insulation layer1370, other than the channel region1302, may be doped with an n-type or p-type dopant to be converted into the source region1303and the drain region1305. In an embodiment, when the fin structure1301ais doped with a p-type dopant, the source region1303and the drain region1305may be doped with an n-type dopant.

When a gate voltage that is equal to or greater than a threshold voltage is applied between the gate electrode1350and the fin structure1301a, a conductive channel may be formed in the channel region1302. The conductive channel may be formed in an inner region of the fin structure1301athat forms an interface with the gate dielectric layer1330. The conductive channel may electrically connect the source region1303and the drain region1305to each other. Then, when an operating voltage is applied between the source region1303and the drain region1305, conductive carriers, such as electrons or holes, may conduct between the source region1303and the drain region1305through the conductive channel. In the embodiment of the present disclosure, the conductive channel may be implemented in the fin structure1301athat protrudes in a three-dimensional structure, thereby increasing the volume of the conductive channel. As a result, the density of the conductive carriers that conduct through the conductive channel may increase, thereby increasing the channel current of the semiconductor device12.

FIG.27Ais a perspective view schematically illustrating a semiconductor device13according to yet another embodiment of the present disclosure.FIG.27Bis a cross-sectional view of the semiconductor device13taken along line V-V′ ofFIG.27A.FIG.27Cis a cross-sectional view of the semiconductor device13taken along line VI-VI′ ofFIG.27A. In an embodiment, the semiconductor device13ofFIGS.27A to27Cmay include transistors Tc of a three-dimensional structure having a vertical channel over a substrate1401. For the convenience of description, an insulation layer surrounding the illustrated components of the semiconductor device13is omitted inFIGS.27A to27C.

Referring toFIGS.27A to27C, the semiconductor device13may include a plurality of transistors Tc that is disposed over the substrate1401. The plurality of transistors Tc may be electrically separated from each other by separation trenches T13that are formed in the substrate1401.

Each of the plurality of transistors Tc may include the substrate1401, an active pillar structure1420extending in a direction (e.g., the z-direction) substantially perpendicular to a surface1410S of the substrate1401, a gate dielectric structure G13that is disposed to surround an outer surface of the active pillar structure1420, and a gate electrode1450that is disposed on the gate dielectric structure G13. The gate dielectric structure G13may include a barrier dielectric layer1410and a gate dielectric layer1430that are connected in series to each other. The barrier dielectric layer1410may include a ferroelectric material, and the gate dielectric layer1430may include a non-ferroelectric material. In addition, the semiconductor device13may include bit lines1403buried in the substrate1401.

The substrate1401may include a semiconductor material. The substrate1410may be doped with an n-type and p-type dopant. In an embodiment, a portion of the substrate1401may be doped with a dopant to form the bit lines1403. In an embodiment, the bit lines1403may be formed, for example, by doping the substrate1401through ion implantation. In an embodiment, when the substrate1401is doped into p-type, the bit lines1403may be doped into n-type.

Each of the active pillar structures1420may correspond to an active layer for an electrical switching operation of the semiconductor device13. Each of the active pillar structures1420may include first and second pillar portions1421and1422respectively having different diameters on a cross-section cut in a direction that is substantially parallel to the surface1401S of the substrate1401. A diameter W1of the first pillar portion1421may be smaller than a diameter W2of the second pillar portion1422. The active pillar structure1420may function as a channel region of the transistor Tc. The active pillar structures1420may be made of substantially the same material as the substrate1401. In an embodiment, the substrate1401and the active pillar structures1420may be doped into p-type.

Referring toFIGS.27A to27C, the gate dielectric structure G13may be disposed to surround the first pillar portion1421of the active pillar structure1420. In an embodiment, the gate dielectric structure G13may have dielectric characteristics that are substantially the same as that of the gate dielectric structure G9of the semiconductor device9, described above with reference toFIG.23. That is, the gate dielectric layer1430may have polarization characteristics, described above with reference toFIG.2. The barrier dielectric layer1410may have the polarization characteristics, illustrated inFIG.3, through bonding with the gate dielectric layer1430. In an embodiment, the thickness of the barrier dielectric layer1410is 5 nm or less, and the thickness of the barrier dielectric layer1410may be substantially the same as or thinner than the thickness of the gate dielectric layer1430. In this case, when the thickness ratio between the barrier dielectric layer1410and the gate dielectric layer1430is distributed within a predetermined range, the barrier dielectric layer1410may have ferroelectric polarization characteristics according to the graph ofFIG.3rather than the graph ofFIG.1. In addition, the gate dielectric structure G13including the barrier dielectric layer1410and the gate dielectric layer1430, connected in series with a thickness ratio within the predetermined range, may have the non-ferroelectricity, described above with reference toFIG.4.

In an embodiment, the barrier dielectric layer1410may be disposed to cover an outer wall of the first pillar portion1421, and the gate dielectric layer1430may be disposed on the barrier dielectric layer1410. The gate electrode1450may be disposed on the gate dielectric layer1430. The material composition of the barrier dielectric layer1410, the gate dielectric layer1430, and the gate electrode1450may be substantially the same as the material composition of the barrier dielectric layer1310, the gate dielectric layer1330, and the gate electrode1350of the semiconductor device12ofFIGS.26A and26B, respectively.

Referring toFIG.27Bagain, based on the gate electrode1450, the barrier dielectric layer1410having ferroelectricity may be disposed to surround the gate dielectric layer1430having non-ferroelectricity. Through the arrangement of the barrier dielectric layer1410and the gate dielectric layer1430, the electrical charges that are formed by the spontaneous polarization of the barrier dielectric layer1410might not be sufficiently canceled by the electrical charges inside the gate dielectric layer1430, as described above with reference toFIG.15B. Accordingly, the depolarization electric field sufficient in suppressing the spontaneous polarization may be formed in the barrier dielectric layer1410. As a result, the gate dielectric structure G13may be effectively controlled to have a capacitance that is substantially equal to the capacitance of the gate dielectric layer1430. Referring back toFIGS.27A to27C, each of the bit lines1403may function as a source electrode for the first pillar portion142that is a channel region.

Referring toFIGS.27A to27C, the second pillar portion1422may be disposed on the first pillar portion1421of each of the active pillar structures1420. An insulation spacer1460may be disposed on an outer wall surface of the second pillar portion1422. Although not illustrated, a source line may be disposed on the second pillar portion1422. The source line may function as a drain electrode for the second pillar portion1422.

According to the embodiment of the present disclosure, the channel region of the transistor may be formed in the active pillar structure1420, extending in a direction (e.g., the z-direction) that is substantially perpendicular to the surface1401S of the substrate1401. The gate dielectric structure G13and the gate electrode1450may be disposed to surround the outer wall surface of the active pillar structure1420, so that the conductive channel may be formed in a direction (e.g., the z-direction) substantially perpendicular to the surface1401S of the substrate1401in the channel region. Accordingly, the area of the channel region of the transistor may be effectively secured.

FIG.28Ais a perspective view schematically illustrating a semiconductor device14according to still yet another embodiment of the present disclosure.FIG.28Bis a cross-sectional view of the semiconductor device14taken along line VII-VII′ ofFIG.28A.FIG.28Cis a cross-sectional view of the semiconductor device14taken along line VIII-VIII′ ofFIG.28A. In an embodiment, the semiconductor device14ofFIGS.28A to28Cmay include a base structure1501and a transistor Ts having a three-dimensional structure that is disposed on the base structure1501. In addition, the semiconductor device14may include a capacitor Cs that is electrically connected to the transistor Ts over the base structure1501. For convenience of description, an insulation layer surrounding the illustrated components of the semiconductor device14has been omitted inFIGS.28A to28C.

Referring toFIGS.28A to28C, the semiconductor device14may include the base structure1501. The base structure1501may include a substrate. In addition, the base structure1501may include at least one conductive layer and at least one interlayer insulation layer that are disposed on the substrate. The base structure1501may serve to support the transistor Ts and the capacitor Cs of the semiconductor device14. The substrate may include a semiconductor material.

The transistor Ts of the semiconductor device14may include an active layer1520that is disposed over the base structure1501, a gate dielectric structure G14that is disposed on an upper surface and a lower surface of the active layer1520, and a gate electrode1550that is disposed on the gate dielectric structure G14. The capacitor Cs of the semiconductor device14may include a storage node electrode1610, an information storage dielectric layer1620, and a plate electrode1630that are disposed over the base structure1501.

The active layer1520may be disposed on a plane that is substantially parallel to a surface1501S of the base structure1501. Although not illustrated, the surface1501S of the base structure1501may be a plane that is substantially parallel to the surface of the substrate. The active layer1520may include a source region1520aand a drain region1520bthat are spaced apart from each other. In addition, the active layer1520may include a channel region1520cbetween the source region1520aand the drain region1520b. The upper and lower surfaces of the channel region1520cmay be covered by the gate dielectric structure G14.

The active layer1520may include a semiconductor material. The semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. The active layer1520may be doped with an n-type or p-type dopant. In an embodiment, the source region1520aand the drain region1520bmay be doped with an n-type dopant, and the channel region1520cmay be doped with a p-type dopant. In another embodiment, the source region1520aand the drain region1520bmay be doped with a p-type dopant, and the channel region1520cmay be doped with an n-type dopant. The channel region1520cmay extend in a direction (e.g., the x-direction) substantially parallel to the surface1501S of the base structure1501.

The gate dielectric structure G14may be disposed on the upper surface and the lower surface of the active layer1520. Referring toFIG.28B, the gate dielectric structure G14may include a barrier dielectric layer1510and a gate dielectric layer1530that are connected in series to each other. The barrier dielectric layer1510may include a ferroelectric material, and the gate dielectric layer1530may include a non-ferroelectric material. As illustrated, the barrier dielectric layer1510may be disposed on the channel region1520c, and the gate dielectric layer1530may be disposed on the barrier dielectric layer1510.

In an embodiment, the gate dielectric structure G14may have substantially the same dielectric characteristics as the gate dielectric structure G9of the semiconductor device9, described above with reference toFIG.23. That is, the gate dielectric layer1530may have the polarization characteristics, described above with reference toFIG.2. The barrier dielectric layer1510may have the polarization characteristics, illustrated inFIG.3, through bonding with the gate dielectric layer1530. In an embodiment, the thickness of the barrier dielectric layer1510may be 5 nm or less, and the thickness of the barrier dielectric layer1510may be substantially the same as or thinner than the thickness of the gate dielectric layer1530. In this case, when the thickness ratio between the barrier dielectric layer1510and the gate dielectric layer1530is distributed within a predetermined range, the barrier dielectric layer1510may have ferroelectric polarization characteristics in line with the graph ofFIG.3rather than the graph ofFIG.1. In addition, the gate dielectric structure G14, including the barrier dielectric layer1510and the gate dielectric layer1530, connected in series to each other with a thickness ratio within the predetermined range, may have the non-ferroelectricity, described above with reference toFIG.4. The material composition of the barrier dielectric layer1510and the gate dielectric layer1530may be substantially the same as the material composition of the barrier dielectric layer1010and the gate dielectric layer1030of the semiconductor device9, described above with reference toFIG.23.

The gate electrode1550may be disposed on the gate dielectric structure G14. The gate electrode1550may include an upper electrode layer1550U and a lower electrode layer1550L. The upper electrode layer1550U and the lower electrode layer1550L may be electrically connected to each other and may simultaneously control the channel region1520c. Accordingly, when a gate voltage that is equal to or greater than a threshold voltage is applied to the upper electrode layer1550U and the lower electrode layer1550L, a pair of conductive channels may be formed in the channel region1520c. The material composition of the upper electrode layer1550U and the lower electrode layer1550U may be substantially the same as the material composition of the gate electrode1050of the semiconductor device9, described above with reference toFIG.23.

In some embodiments, the gate dielectric structure G14may be disposed on only one of the upper surface and lower surface of the active layer1520. Accordingly, as the gate electrode1550, only one of the upper electrode layer and the lower electrode layer may be disposed on the gate dielectric structure G14.

Referring toFIGS.28A to28C, the source region1520aof the active layer1520may be electrically connected to the bit line1503. The bit line1503may extend in a direction (e.g., the z-direction) that is substantially perpendicular to the surface1501S of the base structure1501. The bit line1503may include a conductive pillar structure. Meanwhile, the drain region1520bof the active layer1520may be electrically connected to the storage node electrode1610of the capacitor Cs.

The storage node electrode1610of the capacitor Cs may have a cylindrical shape. The information storage dielectric layer1620may be disposed on the storage node electrode1610. The plate electrode1630may be disposed to cover the information storage dielectric layer1620. Each of the storage node electrode layer1610and the plate electrode1630may include a conductive material. The information storage dielectric layer1620may include oxide, nitride, oxynitride, or a combination of two or more thereof.

In an embodiment, the configurations of the storage node electrode1610, the information storage dielectric layer1620, and the plate electrode1630of the capacitor Cs may be substantially the same as the configurations of the storage node electrode410c, the dielectric structure2003, and the plate electrode440cof the semiconductor device404, described above with reference toFIGS.18A and18B. That is, the information storage dielectric layer1620may include a capacitor dielectric layer and a barrier dielectric layer that are connected in series to each other. In this case, the capacitor dielectric layer may include a non-ferroelectric material, and the barrier dielectric layer may include a ferroelectric material.

In some embodiments not illustrated, the configuration of the storage node electrode1610, the information storage dielectric layer1620, and the plate electrode1630of the capacitor Cs may be substantially the same as the configuration of the storage node electrode410a, the dielectric structure2001, and the plate electrode440aof the semiconductor device404, described above with reference toFIGS.15A and15B. In this case, the storage node electrode1610may have a pillar shape. In some embodiments, the configurations of the storage node electrode1610, the information storage dielectric layer1620, and the plate electrode1630of the capacitor Cs may be substantially the same as the configurations of the storage node electrode410b, the dielectric structure2002, and the plate electrode440bof the semiconductor device403described with reference toFIGS.17A and17B. In this case, the storage node electrode1610may have a pillar shape including the filling structure460. In some embodiments, the configurations of the storage node electrode1610, the information storage dielectric layer1620, and the plate electrode1630of the capacitor Cs may be substantially the same as those of the storage node electrode410d, the dielectric structure2004, and the plate electrode440dof the semiconductor device406described with reference toFIGS.20A and20B. In this case, the storage node electrode1610may have a shape in which a pillar shape and a cylinder shape are combined.

Concepts have been disclosed in conjunction with some embodiments as described above. Those skilled in the art will appreciate that various modifications, additions, and substitutions are possible, without departing from the scope and spirit of the present disclosure. Accordingly, the embodiments disclosed in the present specification should be considered from not a restrictive standpoint but rather from an illustrative standpoint. The scope of the concepts is not limited to the above descriptions but defined by the accompanying claims, and all of distinctive features in the equivalent scope should be construed as being included in the concepts.