Portion isolation architecture for chip isolation test

Embodiments include methods, and processing system, and computer program products providing portion isolation design to a chip design to facilitate partial-good portion isolation test of the chip. Aspects include: retrieving a chip design file of a chip, the chip design file having pin related information from a chip design database, generating, via a pin group utility module, a pin group file according to the pin related information retrieved, combining, via a portion wrapper insertion utility module, the pin group file with one or more portion netlists to form one or more localized portion wrapper segments, stitching, via the portion wrapper insertion utility module, the one or more localized portion wrapper segments to form a portion boundary wrapper chain, and inserting, via the portion wrapper insertion utility module, the portion boundary wrapper chain into the chip design file to facilitate partial-good portion isolation test.

BACKGROUND

The present disclosure relates generally to chip manufacturing, and more particularly to methods, systems and computer program products of providing portion isolation design to a chip design to facilitate partial-good portion isolation test of a chip.

The rapid densification of very-large-scale integration (VLSI) devices, incorporating complex functions operating at extreme circuit performance, has driven the designs towards integrating many diverse functional macros or cores within these large chips. These macros range from autonomous processor cores with large cache arrays occupying relatively large portions of the chip's real estate, to a multitude of small arrays used as register stacks, trace arrays, content addressable memories, phase locked loops (PLLs), and many other special purpose logic functions. In conjunction with these higher integration densities and larger devices, current system architecture is shifting, in many applications, toward massively parallel processing utilizing multiple copies of these integrated cores. The number of processing cores can range from dual-cores to hundreds of cores per chip in the near future and to thousands of core arrays at system level. The independent logic units such as register stacks, trace arrays, content addressable memories, PLLs, as well as the cores in a processor are called “portions” of a chip here.

These highly integrated circuit functions, in conjunction with state-of-the-art semiconductor technology advances, usually result in relatively low device yields because even if one of the many portions of a chip is defective, then the entire chip is considered as defective. A further enhancement to the overall yield is to utilize partially “good” devices or devices that function acceptably with some defective portions.

The scenario outlined above surfaces several test and diagnostic problems that have driven the design and integration of many test functions within the same semiconductor devices.

Hierarchical Test and Partial Good Test testing needs portion wrapping to isolate one or more portion netlist from the logic outside its logical hierarchy. The wrapper resides at the boundary of the core and provides a way to test the portions of the semiconductor devices in isolation and also the interconnection between the various portions at its Top Level.

Therefore, heretofore unaddressed needs still exist in the art to address the aforementioned deficiencies and inadequacies.

SUMMARY

In one aspect, the present disclosure relates to a method of providing portion isolation design to a chip design having a predetermined number of portions. In certain embodiments, the method may include: retrieving a chip design file of a chip, the chip design file having pin related information from a chip design database, generating, via a pin group utility module, a pin group file according to the pin related information retrieved, combining, via a portion wrapper insertion utility module, the pin group file with one or more portion netlists to form one or more localized portion wrapper segments, stitching, via the portion wrapper insertion utility module, the one or more localized portion wrapper segments to form a portion boundary wrapper chain, and inserting, via the portion wrapper insertion utility module, the portion boundary wrapper chain into the chip design file to facilitate partial-good portion isolation test of the chip.

In another aspect, the present disclosure relates to a computer system of providing portion isolation design to a chip design having a plurality of portions. In certain embodiments, the computer system may include: a processor, and a memory storing computer executable instructions. In certain embodiments, the computer executable instructions may include: a pin group utility module and a portion wrapper insertion utility module. The pin group utility module groups a predetermined number of pins of a chip into certain number of pin groups and generates a pin group file based on the pin groups. The portion wrapper insertion utility module creates a portion boundary wrapper chain and inserts the portion boundary wrapper chain created into the chip design file of the chip to facilitate partial-good portion isolation test of the chip.

In yet another aspect, the present disclosure relates to a computer program product operable on a computer system of providing portion isolation design to a chip design having a predetermined number of portions. The computer program product may include a non-transitory computer storage medium readable by the computer system having a processor and a memory configured to store computer executable instructions for execution by the processor of the computer system for performing a method. The method may include: retrieving a chip design file of a chip, the chip design file having pin related information from a chip design database, generating, via a pin group utility module, a pin group file according to the pin related information retrieved, combining, via a portion wrapper insertion utility module, the pin group file with one or more portion netlists to form one or more localized portion wrapper segments, stitching, via the portion wrapper insertion utility module, the one or more localized portion wrapper segments to form a portion boundary wrapper chain, and inserting, via the portion wrapper insertion utility module, the portion boundary wrapper chain into the chip design file to facilitate partial-good portion isolation test of the chip.

DETAILED DESCRIPTION

The terms used in this specification generally have their ordinary meanings in the art, within the context of the disclosure, and in the specific context where each term is used. Certain terms that are used to describe the disclosure are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner regarding the description of the disclosure. It will be appreciated that same thing can be said in more than one way. Consequently, alternative language and synonyms may be used for any one or more of the terms discussed herein, nor is any special significance to be placed upon whether or not a term is elaborated or discussed herein. The use of examples anywhere in this specification including examples of any terms discussed herein is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the disclosure is not limited to various embodiments given in this specification.

As used herein, “plurality” means two or more. The terms “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to.

The term computer program, as used above, may include software, firmware, and/or microcode, and may refer to programs, routines, functions, classes, and/or objects. The term shared, as used above, means that some or all code from multiple modules may be executed using a single (shared) processor.

The term “FLIP-FLOP” or a latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. FLIP-FLOPs and latches are fundamental building blocks of digital electronics systems used in computers, communications, and many other types of systems.

Referring toFIG. 1, there is shown an embodiment of a computer system100of providing portion isolation design to a chip design to facilitate partial-good portion isolation test and implementing the teachings herein. In this embodiment, the computer system100has one or more central processing units (processors)101a,101b,101c, etc. (collectively or generically referred to as processor(s)101). In one embodiment, each processor101may include a reduced instruction set computer (RISC) microprocessor. Processors101are coupled to system memory114and various other components via a system bus113. Read only memory (ROM)102is coupled to the system bus113and may include a basic input/output system (BIOS), which controls certain basic functions of the computer system100.

Thus, as configured inFIG. 1, the computer system100includes processing capability in the form of processors101, storage capability including system memory114and mass storage104, input means such as keyboard109and mouse110, and output capability including speaker111and display115. In one embodiment, a portion of system memory114and mass storage104collectively store an operating system to coordinate the functions of the various components shown inFIG. 1. In certain embodiments, the network116may include symmetric multiprocessing (SMP) bus, a Peripheral Component Interconnect (PCI) bus, local area network (LAN), wide area network (WAN), telecommunication network, wireless communication network, and the Internet.

Hierarchical Test and Partial Good Test testing need portion wrapping to isolate a portion netlist from the logic outside its logical hierarchy. In certain embodiments, the portions may include: one or more cores, one or more partially-good cores, and one or more independent logic units. The one or more independent logic units may include register stacks, trace arrays, content addressable memories, and phase locked loops (PLL). The portion wrapper resides at the boundary of the portion and provides a way to test the portion in isolation and also the interconnection between the cores at a Top Level. Conventionally, there are 2 main existing approaches of portion wrapping for testing the portions: a dedicated boundary pulse latch for inputs and/or outputs, and a re-using the existing functional pulse latch which is getting driven by the inputs/driving the outputs. Both approaches need gating by control signals to enable testing of the portion and interconnection. A clock gating controls also need to be re-designed to control the boundary pulse latches.

If there are no dedicated pulse latches sourcing or sinking in the primary inputs and/or outputs of a portion, wrapper Pulse latches are necessary which creates hardware overhead, and techniques need to be developed to decrease this hardware overhead. Existing approaches of portion wrapping may include: dedicated pulse latches for each primary input or output of a portion, set of boundary Pulse latches or wrapper Pulse latches when the above feature not possible, and portion wrapper latches reduced by selectively providing functional and scan clocks. None of these approaches addresses logic optimization. A large number of Pulse latches causes hardware overhead. This hardware overhead may add to gating logic, chip area, leakage and active power as well.

The present disclosure provides a method of providing portion isolation design to a chip design to facilitate partial-good portion isolation test without adding hardware overhead. The portion isolation design is incorporated into the chip design.

In one aspect, the present disclosure relates to a processing system200of providing portion isolation design to a chip design of a chip, as shown inFIG. 2, according to certain exemplary embodiments of the present invention. The chip may include many portions: one or more cores, one or more partial-good cores, one or more independent logic units. In certain embodiments, the one or more independent logic units may include register stacks, trace arrays, content addressable memories, and phase locked loops (PLL), or any logic units built in the chip.

In certain embodiments, the computer system may include a processor and a memory. The memory may store computer executable instructions. In certain embodiments, the computer executable instructions may include: a pin group utility module206, and a portion wrapper insertion utility module212.

In certain embodiments, the pin group utility module206is configured to groups a predetermined number of pins of a chip into a certain number of pin groups and generates a pin group file based on the pin groups. The predetermined number of pins as well as their corresponding pin related information are generated through one or more design tools, such as timing design tool and routing tools. The pins and pin related information are stored in a chip design database. When the processing system200starts, the pin group utility module206retrieved the pins and pin related information from the chip design database. In certain embodiments, the pin related information may include pin timing information202, and placement information204. The pin timing information202may include: arrival time, and timing slack. The placement information204may include: pin arrangement information, and pin physical layout information.

In certain embodiments, the pin group utility module206is configured to perform: retrieving a chip design file216of the chip from the chip design database, the chip design file216having pin related information, and generating a pin group file according to the pin related information retrieved. The pin group file generated may include one or more pin groups.

In certain embodiments, the generating may include: retrieving a pinlist of the chip from the chip design database, the pinlist having the predetermined number of pins, and initiating a grouping loop to move each of the pins on the pinlist of the chip into the one or more pin groups until the pinlist of the chip is empty. Each iteration of the grouping loop may include: moving a pin from the pinlist to one of the one or more pin groups when a placement check is enabled and when physical location of the pin is within the boundary of the pin group based on a placement affinity threshold, and moving a pin from the pinlist to one of the one or more pin groups when a timing check is enabled and when the timing check of the pin is within the boundary limit of the pin group. Once the grouping loop is completed, a pin group file208is created based on the one or more pin groups.

The portion wrapper insertion utility module212creates a portion boundary wrapper chain and inserts the portion boundary wrapper chain created into the chip design file216of the chip to facilitate partial-good portion isolation test of the chip. In certain embodiments, the portion wrapper insertion utility module212is configured to perform: combining the pin group file208with one or more portion netlists210from the chip design database to form one or more localized portion wrapper segments, stitching the one or more localized portion wrapper segments to form a portion boundary wrapper chain214, and inserting the portion boundary wrapper chain214into the chip design file216of the chip to facilitate partial-good portion isolation test of the chip.

In another aspect, the present disclosure relates to a method300of providing portion isolation design to a chip design having a predetermined number of portions, as shown inFIGS. 2 and 3, according to certain embodiments of the present disclosure. In certain embodiments, the method300may include: retrieving a chip design file216of a chip, the chip design file216having pin related information from a chip design database, generating, via a pin group utility module206, a pin group file208according to the pin related information retrieved, combining, via a portion wrapper insertion utility module212, the pin group file208with one or more portion netlists210from the chip design database to form one or more localized portion wrapper segments, stitching, via the portion wrapper insertion utility module212, the one or more localized portion wrapper segments to form a portion boundary wrapper chain214, and inserting, via the portion wrapper insertion utility module212, the portion boundary wrapper chain214into the chip design file216to facilitate partial-good portion isolation test of the chip.

In certain embodiments, once the portion boundary wrapper chain214is inserted into the chip design file216, the portion isolation design to facilitate partial-good portion isolation test of the chip is added to the original chip design file. The chip may be made in batches according to the chip design file216that has the portion isolation design.

In certain embodiments, once the portion isolation design to facilitate partial-good portion isolation test of the chip is added to the original chip design file, the chip may be made based on the chip design file having the portion isolation design to facilitate partial-good portion isolation test of the chip.

In certain embodiments, the chip made according to the chip design file216may be tested using the portion isolation design to individually test each and every portions of the chip. The chip design having portion isolation design may reduce the hardware implementation in the Chip design and dramatically reduce the hardware overhead. The chip design having portion isolation design requires much lesser boundary pulse latches and wrapping logic. Such reductions may help in reducing congestion and routing issues.

In certain embodiments, the chip made according to the chip design file216with portion isolation design may include an on-chip service engine, an on-chip service engine memory, a first portion, a second portion, . . . , and N-th portion, each portion having a portion boundary wrapper chain such that each portion may be isolation tested according to the portion isolation design to facilitate partial-good portion isolation test. The chip may be tested a system functional testing device. The system functional testing device may include system functional test software, and the chip to be tested by the system functional testing device. The chip may be mounted on the system functional testing device for testing. The chip may include an on-chip service engine which is an on-chip highly optimized general purpose micro-controller. The on-chip service engine may have its own instruction set architecture (ISA), and acts as a bridge between an external tester such as a computer system and its intra-chip functional logic units. The on-chip service engine is capable of performing any chip operations that any external tester program can perform.

In certain embodiments, the on-chip service engine memory may be a volatile memory, such as the random-access memory (RAM), for storing the data and information during the operation of the system functional test. The service engine memory may also include a non-volatile data storage media for system functional test software and other applications. Examples of the service engine memory may include flash memory, memory cards, USB drives, hard drives, floppy disks, optical drives, or any other types of data storage devices.

The chip may include certain number of different portions: such as independent logic units, registers, arrays of memory, and one or more cores of a processor. The system functional test software, when executed at the on-ship service engine, may be configured to identify any of the portions of the chip to be good, not good, and the whether the chip is still functional when some of the portions are bad. With the built-in portion isolation design incorporated in the system functional test software, it is much easier for the system functional test software to identify good portions, bad portions, and/or partially good portion with less hardware overhead.

In certain embodiments, a hard disk of a computer system may store system functional test software for performing system functional test on the chip having partial-good portions with built-in portion isolation design. In certain embodiments, when the system functional test software is executed at a processor, the computer system may perform: initializing, by system functional test software, the service engine of the chip undergoing system functional test, performing, system functional test by the service engine, and completing the system functional test of the chip. Each of the “partial-good” portions is identified by a “partial-good” parameter. In certain embodiments, the initializing may include: loading the system functional test software into the service engine memory, identifying each “partial-good” portion of the chip according to the built-in portion isolation design, writing a “partial-good” parameter for each “partial-good” portion of the chip identified to a first predetermined location of the service engine memory.

In certain embodiments, the system functional test software is executed on the on-ship service engine, and each isolated portion of the chip is tested with the built-in portion isolation design to identify all good portions, bad portions, and partial-good portions of the chip. Once the good portions, bad portions, and partially good portions are identified, information of these good portions, bad portions, and partially good portions of the chip may be stored in a predetermined location of the service engine memory such that the chip made labeled and categorized in a later time of the chip production.

In certain embodiments, the portions may include one or more cores, one or more partially-good cores, and one or more independent logic units. The one or more independent logic units may include register stacks, trace arrays, content addressable memories, and phase locked loops (PLL). In certain embodiments, the pin related information may include pin timing information202, and placement information204. The pin timing information202may include: arrival time, and timing slack. The placement information204may include: pin arrangement information, and pin physical layout information.

In certain embodiments, the generating may include: retrieving a pinlist of the chip from the chip design database, the pinlist having a predetermined number of pins, initiating a grouping loop to move each of the pins on the pinlist of the chip into one or more pin groups until the pinlist of the chip is empty, and generating the pin group file208based on the one or more pin groups. Each iteration of the grouping loop may include: moving a pin from the pinlist to one of the one or more pin groups when a placement check is enabled and when physical location of the pin is within the boundary of the pin group based on a placement affinity threshold, and moving a pin from the pinlist to one of the plurality of pin groups when a timing check is enabled and when the timing check of the pin is within the boundary limit of the pin group.

Referring now toFIG. 3, a flow chart of an exemplary method300of providing portion isolation design to a chip design to facilitate partial-good portion isolation test according to certain embodiments of the present invention.

At block302, the pin group utility module206may retrieve a list of pins on the chip (pinlist) and their corresponding pin related information. In certain embodiments, the chip may include a predetermined number of pins on this pinlist. In certain embodiments, the pin related information may include pin timing information202, and placement information204. The pin timing information202may include: arrival time, and timing slack. The placement information204may include: pin arrangement information, and pin physical layout information.

At block304, the pin group utility module206may group the predetermined number of pins on the pinlist into one or more pin groups and generate the pin group file208. Detailed grouping operations will be described inFIG. 4.

At block306, the portion wrapper insertion utility module212may combine the pin group file208and one or more portion netlists from the chip design database to form one or more localized portion wrapper segments.

At block308, the portion wrapper insertion utility module212may stitch the one or more localized portion wrapper segments to form the portion boundary wrapper chain214. The portion boundary wrapper chain214contains the portion isolation design to the chip design to facilitate partial-good portion isolation test of the chip.

At block310, the portion wrapper insertion utility module212may insert the portion boundary wrapper chain214into the chip design file216to provide the portion isolation design to the chip design to facilitate partial-good portion isolation test of the chip.

Referring now toFIG. 4, a flow chart showing how the predetermined pins in the pinlist are grouped (block304) to form the pin group file208is shown according to certain exemplary embodiments of the present invention.

At block402, the pin group utility module206may get the list of the predetermined number of pins (the pinlist) from the chip design database.

At block404, the pin group utility module206may perform following two separate loops to each of the predetermined number of pins of the chip on the pinlist. The two loops may include a placement loop having block410through block416, and a timing loop having block420through block426.

At query block410, the pin group utility module206may check whether a placement check is enabled. When the placement check is not enabled, the placement loop having block410through block416is skipped. Otherwise, the placement loop is executed.

At block412, the pin group utility module206may go through the placement check to each and every one of the pins remaining on the pin list.

At query block414, the pin group utility module206may check whether the physical location of the pin is in the boundary limit of a pin group X, where pin group X is one of the one or more pin groups. When the physical location of the pin is in the boundary limit of the pin group X, then move the pin to pin group X at block416. Otherwise, the pin group utility module206may loop back to block412to group the next pin remaining on the pinlist.

At block416, the pin group utility module206may include the pin in the pin group X, and then remove the pin from the pinlist. Afterward, the pin group utility module206goes to block420to perform timing check.

At query block420, the pin group utility module206may check whether a timing check is enabled. When the timing check is not enabled, the timing loop having block420through block426is skipped. Otherwise, the timing loop is executed.

At block422, the pin group utility module206may go through the timing check to each and every one of the pins remaining on the pin list.

At query block424, the pin group utility module206may perform a timing check to see whether the timing check of the pin is within the boundary limit of a pin group Y, where pin group Y may be a different pin group of the one or more pin groups. When the timing check of the pin is within the boundary limit of a pin group Y, then the pin group utility module206may move the pin to pin group Y at block426. Otherwise, the pin group utility module206may loop back to block422to group the next pin remaining on the pinlist.

At block426, the pin group utility module206may include the pin in the pin group Y, and then remove the pin from the pinlist. Afterward, the pin group utility module206goes to block404to group the next pin on the pinlist, until the pin list is empty.

In yet another aspect, the present disclosure relates to a computer program product operable on a processing system of providing portion isolation design to a chip design having a predetermined number of portions. The computer program product may include a non-transitory computer storage medium readable by the computer system having a processor and a memory configured to store computer executable instructions for execution by the processor of the computer system for performing a method. The method may include: retrieving a chip design file of a chip, the chip design file having pin related information from a chip design database, generating, via a pin group utility module, a pin group file according to the pin related information retrieved, combining, via a portion wrapper insertion utility module, the pin group file with one or more portion netlists to form one or more localized portion wrapper segments, stitching, via the portion wrapper insertion utility module, the one or more localized portion wrapper segments to form a portion boundary wrapper chain, and inserting, via the portion wrapper insertion utility module, the portion boundary wrapper chain into the chip design file to facilitate partial-good portion isolation test.

In certain embodiments, the generating may include: retrieving a pinlist of the chip from the chip design database having a predetermined number of pins, initiating a grouping loop to move each of the pins on the pinlist of the chip into a plurality of pin groups until the pinlist of the chip is empty, and generating the pin group file based on the plurality of pin groups. Each iteration of the grouping loop may include: moving a pin from the pinlist to one of the pin groups when a placement check is enabled and when physical location of the pin is within the boundary of the pin group based on a placement affinity threshold, and moving a pin from the pinlist to one of the plurality of pin groups when a timing check is enabled and when the timing check of the pin is within the boundary limit of the pin group.