Semiconductor device and a method for fabricating the same

In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A source/drain region is formed. A first insulating layer is formed over the dummy gate structure and the source/drain region. A gate space is formed by removing the dummy gate structure. The gate space is filled with a first metal layer. A gate recess is formed by removing an upper portion of the filled first metal layer. A second metal layer is formed over the first metal layer in the gate recess. A second insulating layer is formed over the second metal layer in the gate recess.

TECHNICAL FIELD

The disclosure relates to a method for manufacturing a semiconductor device, and more particularly to a structure and a manufacturing method for a metal gate structure.

BACKGROUND

As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (Fin FET) and the use of a metal gate structure with a high-k (dielectric constant) material. The metal gate structure is often manufactured by using gate replacement technologies.

DETAILED DESCRIPTION

FIGS. 1A-12show exemplary sequential manufacturing process of a semiconductor device according to one embodiment of the present disclosure.FIGS. 1B-12are cross sectional views corresponding to line X1-X1ofFIG. 1A. It is understood that additional operations can be provided before, during, and after processes shown byFIGS. 1A-12, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIG. 1Ashows a top view (plan view) of a structure of a semiconductor device after dummy gate structures are formed over a substrate. InFIGS. 1A and 1B, dummy gate structures40,41and42are formed over a channel layer, for example, a part of a fin structure20. Each of the dummy gate structures40,41and42corresponds to an n-channel FET, a p-channel FET and an n-type long channel FET.

The fin structure20is formed over a substrate10and extends from an isolation insulating layer30. For explanation purpose, the dummy gate structures40,41and42are formed over the same fin structure20, but in some embodiments, dummy gate structures40,41and42are formed over different fin structures, respectively. Similarly, although two fin structures20are illustrated inFIG. 1A, the number of fin structure per one gate structure is not limited to two, and may be one, or three or more.

The substrate10is, for example, a p-type silicon substrate with an impurity concentration in a range from about 1×1015cm−3to about 1×1018cm−3. In other embodiments, the substrate is an n-type silicon substrate with an impurity concentration in a range from about 1×1015cm−3to about 1×1018cm−3. Alternatively, the substrate may comprise another elementary semiconductor, such as germanium; a compound semiconductor including Group IV-IV compound semiconductors such as SiC and SiGe, Group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AnnAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In one embodiment, the substrate is a silicon layer of an SOI (silicon-on insulator) substrate.

The fin structures20may be formed by trench-etching the substrate. After forming the fin structures20, the isolation insulating layer30is formed over the fin structures20. The isolation insulating layer30includes one or more layers of insulating materials such as silicon oxide, silicon oxynitride or silicon nitride, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. The isolation insulating layer may be formed by one or more layers of spin-on-glass (SOG), SiO, SiON, SiOCN and/or fluorine-doped silicate glass (FSG).

After forming the isolation insulating layer30over the fin structures20, a planarization operation is performed, thereby removing part of the isolation insulating layer30. The planarization operation may include a chemical mechanical polishing (CMP) and/or an etch-back process. Then, the isolation insulating layer30is further removed (recessed) so that the upper regions of the fin structures20are exposed.

Then, the dummy gate structures40,41and42are formed over the exposed fin structures20. The dummy gate structure includes a dummy gate electrode layer44made of poly silicon and a dummy gate dielectric layer43. Sidewall spacers48including one or more layers of insulating materials are also formed on sidewalls of the dummy gate electrode layer. The sidewall spacers48include one or more layers of insulating material such as silicon nitride based material including SiN, SiON, SiCN and SiOCN. The film thickness of the sidewall spacers48at the bottom of the sidewall spacers is in a range from about 3 nm to about 15 nm in some embodiments, and is in a range from about 4 nm to about 8 nm in other embodiments.

The dummy gate structures further include a mask insulating layer46, which is used to pattern a poly silicon layer into the dummy gate electrode layers. The thickness of the mask insulating layer46is in a range from about 10 nm to about 30 nm in some embodiment, and is in a range from about 15 nm to about 20 nm in other embodiments.

As shown inFIG. 2, after the dummy gate structures are formed, source/drain regions60are formed. In the present disclosure, a source and a drain are interchangeably used, and the term source/drain refers to either one of a source and a drain. In some embodiments, the fin structure20not covered by the dummy gate structures is recessed below the upper surface of the isolation insulating layer30. Then, the source/drain regions60are formed over the recessed fin structure by using an epitaxial growth method. The source/drain regions60may include a strain material to apply stress to the channel region.

Then, as shown inFIG. 3, a first etching stop layer (ESL)70and a first interlayer insulating (ILD) layer75are formed over the dummy gate structures and the source/drain regions. The first ESL70includes one or more layers of insulating material such as silicon nitride based material including SiN, SiCN and SiOCN. The thickness of the first ESL70is in a range from about 3 nm to about 10 nm in some embodiments. The first ILD layer75includes one or more layers of insulating material such as silicon oxide based material such as silicon dioxide (SiO2) and SiON.

After a planarization operation on the first ILD layer75and the ESL70, the dummy gate structures are removed, thereby making gate spaces81,82and83, as shown inFIG. 4. As shown inFIG. 4, the gate sidewall spacers48remain in the gate spaces.

Further, a first work function adjustment (WFA) layer90for a p-channel FET is formed in the gate space82. A blanket layer of a suitable conductive material is formed over the gate spaces and the first ILD layer75, and a patterning operation including lithography and etching is performed to form the first WFA layer90for a p-channel FET in the gate space82(and the surrounding area). The first WFA layer90includes one or more layers of conductive material. Examples of the first WFA layer90for a p-channel FET include Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co. In one embodiment, Ti is used. The thickness of the first WFA layer90is in a range from about 3 nm to about 10 nm in some embodiments. The first WFA layer90may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD) or other suitable method. As shown inFIG. 5, the first WFA layer90is conformally formed in the gate space82.

Then, a second WFA layer95for n-channel FETs is formed in the gate spaces81and83. A blanket layer of a suitable conductive material is formed over the gate spaces and the first WFA layer90, and a patterning operation including lithography and etching is performed to form the second WFA95for n-channel FETs in the gate spaces81and83(and the surrounding area). The second WFA layer95includes one or more layer of conductive material. Examples of the second WFA layer95for an n-channel FET include TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC. In one embodiment, TiN is used. The thickness of the second WFA layer95is in a range from about 3 nm to about 10 nm in some embodiments. The second WFA layer95may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD) or other suitable methods. As shown inFIG. 5, the second WFA layer95is conformally formed in the gate spaces81and83. It is noted that the order of forming the first WFA layer90and the second WFA layer95can be changed. The second WFA layer95is made of a different material than the first WFA layer90.

Then, as shown inFIG. 6, a first metal material101for a first metal layer100is formed over the structure ofFIG. 5. The first metal material includes one or more layers of metal material, such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, other conductive materials. In one embodiment, TiN is used. The first metal material is formed by CVD, PVD, ALD, electroplating or other suitable methods. The first metal layer100is made of a different material than at least one of the first WFA layer and the second WFA layer.

Then, as shown inFIG. 7, a planarization operation is performed, thereby removing the upper portion of the deposited first metal material101. After the planarization operation, the first metal layer100is formed in each of the gate spaces. The planarization operation may include a chemical mechanical polishing (CMP) and/or an etch-back process.

After each of the gate spaces are filled with the first metal layer100, the first metal layers100are recessed (etched-back) to form gate recesses87,88and89, as shown inFIG. 8. The upper portions of the first metal layers100are etched by using dry etching and/or wet etching. The amount (depth) D1of the recessed portion is in a range from about 20 nm to about 50 nm in some embodiments, and the height H1of the remaining first metal layer from the surface of the fin structure20is in a range from about 30 nm to about 60 nm in some embodiments.

During the recess etching, the first WFA layer90and the second WFA layer95are also etched.

Then, as shown inFIG. 9, a second metal material111for a second metal layer110is formed over the structure ofFIG. 8. The second metal material includes one or more layers of metal material, such as Al, Cu, Co, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, other conductive materials. In one embodiment, W or Co is used. The second metal material is formed by CVD, PVD, ALD, electroplating or other suitable methods. The second metal material111is made of a different material than the first metal material (and the first and second WFA layers) and has a higher durability against a gas containing Cl and/or F than the first metal material101(and the first and second WFA layers).

A planarization operation is subsequently performed, thereby removing the upper portion of the deposited second metal material111. After the planarization operation, the second metal layer110is formed in each of the gate spaces. The planarization operation may include a chemical mechanical polishing (CMP) and/or an etch-back process.

The planarized second metal layers110are further recessed in the gate spaces by using an etch-back operation, as shown inFIG. 10. The amount (depth) D2of the recessed portion is in a range from about 10 nm to about 40 nm in some embodiments, and the thickness T1of the remaining second metal layer110from the upper surface of the first metal layer100is in a range from about 10 nm to about 30 nm in some embodiments. As shown inFIG. 10, a bottom of the second metal layer110is in contact with an upper surface of the first metal layer100and an upper surface of the first and/or second WFA layers90,95.

Then, as shown inFIG. 11, cap insulating layers120are formed over the second metal layers110. The cap insulating layer120includes one or more layers of insulating material such as silicon nitride based material including SiN, SiCN and SiOCN.

To form the cap insulating layers120, a blanket layer of an insulating material having a relatively large thickness is formed over structure ofFIG. 10, and a planarization operation, such as a CMP, is performed.

Then, a second ILD130is formed over the structure ofFIG. 11, and a patterning operation is performed to form via holes. The via holes are filed with one or more conductive materials, thereby forming via plugs140,142,144,146and148, as shown inFIG. 12. Further, one or more metal wirings (not shown) are formed over the via plugs, respectively. A dual damascene method may be used to form the via plugs and the metal wirings.

In the above embodiment, the second metal layers are formed by using a blanket deposition, a planarization operation and an etch-back operation. In another embodiment, the second metal layers are directly formed over the first metal layers. For example, after the structure ofFIG. 8is formed, a selective deposition of W or Co is used to form the second metal layer over the first metal layers only in the gate spaces, to obtain the structure shown inFIG. 10. For example, by using an ALD method, Co and W can be selectively grown on the metal layers90,95and100, while Co or W are not grown on SiO2, SiN or other dielectric materials.

It is understood that the device shown inFIG. 12undergoes further CMOS processes to form various features such as interconnect metal layers, dielectric layers, passivation layers, etc. In the above embodiment, the manufacturing operations for a Fin FET are described. However, the above manufacturing process may be applied to other types of FET, such as a planar type FET.

The various embodiments or examples described herein offer several advantages over the existing art. For example, in the present disclosure, as shown inFIG. 12, the via plugs140,144and148are in contact with the second metal layers110. When via holes for the via plugs140,144and148are formed, a dry etching using a gas containing Cl and/or F is used. If the second metal layers110, which have a higher durability against Cl or F, are not used, the Ti or TiN layer exposed in the bottoms of the contact holes would be damaged (e.g., causing erosion) by the Cl or F component in the etching gas. In contrast, in the present embodiment, since the second metal layers110, which have a higher durability against Cl or F that Ti and TiN, are used, damage to the Ti or TiN layers can be avoided.

According to one aspect of the present disclosure, in a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A source/drain region is formed. A first insulating layer is formed over the dummy gate structure and the source/drain region. A gate space is formed by removing the dummy gate structure. The gate space is filled with a first metal layer. A gate recess is formed by removing an upper portion of the filled first metal layer. A second metal layer is formed over the first metal layer in the gate recess. A second insulating layer is formed over the second metal layer in the gate recess.

According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a first dummy gate structure and a second dummy gate structure are formed over a substrate. Source/drain regions are formed. A first insulating layer is formed over the first and second dummy gate structures and the source/drain regions. A first gate space and a second gate space are formed by removing the first and second dummy gate structures, respectively. A first metal layer is formed in the first gate space, and a second metal layer is formed in the first and second gate spaces. After forming the first and second metal layers, the first and second gate spaces are filled with a third metal layer. A gate recess is formed by removing upper portions of the first, second and third metal layers formed in the first gate space, and a second gate recess is formed by removing upper portions of the first and third metal layers formed in the second gate space. A first gate electrode and a second gate electrode are formed by forming metal layers in the first and second gate recesses. Second insulating layers are formed over the fourth metal layers in the first and second gate recess.

In accordance with yet another aspect of the present disclosure, a semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.