Power semiconductor devices

A process for manufacturing integrated circuits includes the following steps. First, an oxide layer is formed on at least one surface of two respective semiconductor material wafers. Next, a single semiconductor material wafer is obtained with a first layer and a second layer of semiconductor material and a buried oxide layer interposed therebetween starting from said two semiconductor material wafers by direct bonding of the oxide layers previously grown. The single wafer is submitted to a controlled reduction of the thickness of the first layer of semiconductor material and the top surface of the first layer of semiconductor material is lapped. Dopant impurities are selectively introduced into selected regions of the first layer of semiconductor material to form the desired integrated components. Trenches are formed laterally delimiting respective portions of the first layer of semiconductor material wherein integrated components are present which are to be electrically isolated from other integrated components. Finally the walls of the trenches are coated with an insulating material and filled with amorphous silicon.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a process for manufacturing integrated 
circuits, particularly of intelligent power semiconductor devices. 
2. Discussion of the Related Art 
In manufacturing integrated circuits, the problem of obtaining chip regions 
which are electrically insulated from one another exists. For example, in 
power semiconductor devices provided with on-chip driving circuitry (also 
called intelligent power semiconductor devices), the power device must be 
electrically insulated from the driving circuitry. 
The most common technique to achieve this electrical insulation is PN 
junction isolation. However, this technique gives rise to some problems, 
especially related to the introduction of parasitic components. 
Considering for example a Vertical Intelligent Power semiconductor device 
(VIP), such as an NPN power bipolar transistor constituted by an N++ 
emitter region diffused into a P-type base region which is in turn 
diffused into an N-type epitaxial layer representing the collector of the 
transistor. The driving circuitry is obtained inside a P-type well which 
is diffused into the N-type epitaxial layer and connected to the lowest 
voltage among those utilized in the chip to keep the P-type well/N-type 
epitaxial layer junction reverse biased. Inside the P-type well, vertical 
NPN transistors and lateral PNP transistors are generally obtained. In 
this structure, a number of parasitic bipolar transistors are present, 
both NPN and PNP, having base, emitter and collector represented by the 
various P-type or N-type regions inside the P-type well, the P-type well 
itself and the N-type epitaxial layer. Another PNP parasitic transistor 
has emitter, base and collector respectively represented by the P-type 
base region of the power transistor, the N-type epitaxial layer and the 
P-type well. All such parasitic components limit VIP performances. 
SUMMARY OF THE INVENTION 
In view of the state of art described, the object of the present invention 
is to develop a process for manufacturing integrated circuits, 
particularly for intelligent power semiconductor devices which creates 
devices wherein the electrical insulation between various semiconductor 
regions does not give rise to parasitic components. 
According to the present invention, this object is attained by means of a 
process for manufacturing integrated circuits which includes the following 
steps. 
An oxide layer is formed on at least one surface of two respective 
semiconductor material wafers to obtain a single semiconductor material 
wafer with a first layer and a second layer of semiconductor material and 
a buried oxide layer interposed therebetween starting from said two 
semiconductor material wafers by direct bonding of the oxide layers 
previously grown. The single wafer is exposed to a controlled reduction of 
the thickness of the first layer of semiconductor material, and then the 
top surface of the first layer of semiconductor material is lapped. Next 
dopant impurities are selectively introduced into selected regions of the 
first layer of semiconductor material to form the desired integrated 
components. An insulating material layer is then formed over the top 
surface of the first layer of semiconductor material. The insulating 
material layer, and the first layer of semiconductor material are 
selectively etched down to the buried oxide layer to form trenches 
laterally delimiting respective portions of the first layer of 
semiconductor material wherein integrated components are present which are 
to be electrically isolated from other integrated components. Finally, the 
walls of the trenches are coated with an insulating material and the 
trenches are filled with amorphous silicon. 
According to the present invention, it is possible to fabricate integrated 
circuits, particularly intelligent power semiconductor devices with an 
integrated driving circuitry, which are not affected by the presence of 
parasitic devices since the electrical isolation between the various 
devices is not accomplished by means of junction isolation, but by means 
of dielectric isolation. 
If the integrated circuit to be fabricated is an intelligent power 
semiconductor device with an integrated driving circuitry, the process 
according to the invention comprises two additional steps. 
The first semiconductor material layer is selectively etched down to the 
buried oxide layer to obtain selected portions of the single wafer wherein 
the buried oxide layer is uncovered, and dopant impurities are selectively 
introduced into selected regions of the second layer of semiconductor 
material to form the desired power device. 
It is thus possible to fabricate intelligent power semiconductor devices 
with an integrated driving circuitry which are not affected by the 
presence of parasitic devices since the electrical isolation between the 
power devices and the driving circuitry and between the various components 
of the driving circuitry is not accomplished by means of junction 
isolation, but by means of dielectric isolation. 
The features of the present invention will be made more evident by the 
following detailed description of its preferred embodiment, illustrated as 
a non-limiting example in the annexed drawings.

DETAILED DESCRIPTION 
As shown in FIG. 1, a manufacturing process according to the invention 
starts from two distinct silicon wafers 1 and 2, generally doped with 
donor impurities. A first wafer 1 comprises an N-type semiconductor bulk 9 
and an N+ heavily doped silicon layer 3 at its bottom surface. The second 
wafer 2 has resistivity and thickness values depending on the particular 
power device that is to be obtained. 
The two silicon wafers 1 and 2 are then submitted to a thermal oxidation 
process to grow on the bottom surface of the first wafer 1 and on the top 
surface of the second wafer 2 respective thermal oxide layers 5 and 6. 
During this step, thermal oxide layers 4 and 7 are also grown on the top 
surface of the first wafer 1 and the bottom surface of the second wafer 2, 
respectively. 
The two wafers 1 and 2 are then bonded together by means of the so-called 
"Silicon Direct Bonding" (SDB) technique, known per se and described for 
example in the European Patent Application No. 89202692.3. After this 
step, a single silicon wafer is obtained from the two silicon wafers 1 and 
2. The bottom oxide layer 5 of the first wafer 1 and the top oxide layer 6 
of the second wafer 2 constitute a single oxide layer 8 sandwiched between 
the second wafer 2 and the N+ layer 3 of the first wafer 1, and thus, this 
oxide layer is buried under the first wafer 1 (FIG. 2). Among the various 
Silicon On Insulator (SOI) techniques, the SDB technique produces buried 
oxide layers of better quality. 
The top oxide layer 4 of the first wafer 1 and the bottom oxide layer 7 of 
the second wafer 2 are then removed, and the N-type semiconductor bulk 9 
of the first wafer 1 is submitted to a controlled reduction of its 
thickness. The top surface of the N-type semiconductor bulk 9 of the first 
wafer 1 is then polished by means of a precision lapping and polishing 
machine (with a thickness tolerance of about 0.1 mm). The top surface of 
N-type semiconductor bulk 9 of the first wafer 1, at the end of these 
steps, represents the top side of the single silicon wafer composed by the 
two bonded silicon wafers 1 and 2 (FIG. 3). 
If the integrated device to be fabricated is a Vertical Intelligent Power 
(VIP) device, such as a bipolar power transistor, the N-type semiconductor 
bulk 9 and the N+ layer 3 of the first wafer 1 are selectively etched and 
removed down to the single oxide layer 8. At the end of this step, within 
all the regions 10 of the single silicon wafer wherein power devices are 
to be fabricated, the buried oxide layer 8 is uncovered. However, within 
all the regions 11 reserved to the driving circuitries for the power 
devices, the oxide layer 8 is still buried under the N-type semiconductor 
bulk 9 and the N+ layer 3 (FIG. 4). It is important to note that the 
etching angle a should be as small as possible, to avoid the creation of 
high steps so that the following depositions of the various layers (such 
as vapox, aluminum, nitride, etc.) is readily facilitated. 
After this step, a thermal oxide layer is grown over the entire top surface 
of the wafer, i.e. over the top surface of the N-type silicon bulk 9 (in 
the wafer regions 11) and over the uncovered oxide layer 8 (in the wafer 
regions 10). 
The power devices and their driving circuitries are fabricated in their 
respective wafer regions 10 and 11 according to a standard and per se 
known manufacturing process. It is to be noted that if the depth of field 
of the photolitographic apparatus employed in the manufacturing process is 
lower than the difference in height between the wafer regions 11 and 10, 
all the photolitographic steps in the wafer regions 10 reserved to the 
power devices are to be performed separately from those in the wafer 
regions 11 reserved to the driving circuitries. 
FIG. 5 shows on an enlarged scale a part of a wafer region 11 wherein a 
vertical NPN transistor is present. As known to anyone skilled in the art, 
the transistor comprises a P-type base region 12 diffused into the N-type 
semiconductor bulk 9, and an N+ emitter region 13 diffused into said base 
region 12. The collector region is represented by a portion of the N-type 
semiconductor bulk 9 which is located under the emitter region 13. When 
the transistor is biased in the forward active region, electrons are 
injected from the emitter region 13 into the base region 12 wherefrom they 
diffuse into the collector region. The N+ layer 3 represents a buried 
layer offering a low resistive path for the electrons to an N+ collector 
contact region 14. 
To electrically insulate the transistor shown in FIG. 5 from other 
integrated components defined in the same wafer region 11, the process 
according to the present invention provides for the realization of 
vertical trenches. To obtain said trenches, a per se known technique is 
used providing for the deposition over the top surface of the N-type 
silicon bulk 9 of an insulating material layer generally composed by three 
layers: a thin thermal oxide layer 15; a nitride layer 16 and a 
vapour-deposited oxide layer ("vpox") 17 (FIG. 5). Successively, the three 
layers 15, 16 and 17, together with the N-type semiconductor bulk 9 and 
the N+ layer 3, are selectively etched down to the buried oxide layer 8, 
to form a trench 18 around the lateral transistor shown as well as around 
all the other elements of the driving circuitry in the wafer region 11 
which are to be electrically isolated from one another (FIG. 6). In 
certain embodiments, trench 18 may be substabtially v-shaped. 
The trench 18 must then be filled with an insulation material. In one 
embodiment, the insulation materials consist only of an oxide. However, 
other materials may be used as well. For example, according to one 
technique, the walls of the trench 18 are first covered by an oxide layer 
19, and the trench 18 is filled with amorphous silicon 20. In this way the 
wafer region 11 is divided into portions which are electrically insulated 
from one another laterally by means of the trench 18 and at the bottom by 
means of the buried oxide layer 8. 
The top surface of the N-type silicon bulk 9 is then planarized, the three 
layers 15, 16 and 17 are removed from the surface of the N-type bulk 9, 
and a thermal oxide layer 21 is grown over the entire surface. Said oxide 
layer 21 is then selectively etched to form contact areas 22 (FIG. 7), and 
an aluminum layer (not shown) is deposited over the thermal oxide layer 21 
and selectively etched to form the desired pattern of interconnection 
lines between the various components. 
The process according to the present invention is suitable for the 
manufacturing of integrated circuits in general and not only of VIP 
devices. If no power devices are to be fabricated, neither the step of 
selective removal of the N-type semiconductor bulk 9 and of the N+ layer 
3, nor the subsequent thermal oxidation of the entire wafer surface, are 
performed. Apart from these differences, the process is totally similar to 
that already described. 
Having thus described one particular embodiment of the invention, various 
alterations, modifications and improvements will readily occur to those 
skilled in the art. Such alterations, modifications and improvements are 
intended to be part of this disclosure and are intended to be within the 
spirit and scope of the invention. Accordingly, the foregoing description 
is by way of example only, and not intended as limiting. The invention is 
limited only as defined in the following claims and equivalents thereto.