Insulating film pattern, method for manufacturing the same, and method for manufacturing thin film transistor substrate using the same

In an insulating film pattern, a first pattern part is formed at one surface of the insulating film pattern to form a source electrode, a drain electrode, and a semiconductor layer of the thin film transistor. The first pattern part is recessed in one surface of the insulating film pattern. The insulating film pattern is formed on a substrate through an imprint scheme, and is deposited on a base substrate having a gate electrode and a gate line through a contact print scheme. A source electrode, drain electrode, and semiconductor layer of a thin film transistor are formed through an inkjet print scheme using a first pattern part of the insulating film pattern. A gate electrode and gate line may be formed using a second pattern part of the insulating film pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 10-2008-0094787, filed on Sep. 26, 2008, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an insulating film pattern, a method for manufacturing the insulating film pattern, and a method for manufacturing a thin film transistor substrate using the insulating film pattern. More particularly, the present invention relates to an insulating film pattern that may improve the productivity and simplify the manufacturing of a thin film transistor, a method for manufacturing the insulating film pattern, and a method for manufacturing a thin film transistor substrate using the insulating film pattern.

2. Discussion of the Background

In general, a display apparatus is used to display images by changing data from an electrical format into images visible to human eyes. A liquid crystal display (LCD) is one type of display apparatus and displays images using optical characteristics of liquid crystals.

In detail, the LCD includes an LCD panel that displays images and a backlight assembly that provides light to the LCD panel. The LCD panel includes a thin film transistor (TFT) substrate, an opposite substrate facing the TFT substrate, and a liquid crystal layer interposed between the TFT substrate and the opposite substrate.

The TFT substrate includes pixels serving as a basic unit to display the image, and each pixel has a TFT to turn a pixel voltage on and off, and a pixel electrode. The pixel electrode is connected to a drain electrode of the TFT, and receives the pixel voltage from the TFT.

The TFT substrate has a multilayer structure including thin films, so the TFT substrate is generally formed by patterning the thin films through a photolithography process using expensive masks, so that the process time and manufacturing cost are greater than desired.

SUMMARY OF THE INVENTION

This invention provides an insulating film pattern that may improve the productivity and simplify the manufacturing of a TFT.

This invention also provides a method for manufacturing an insulating film pattern.

This invention also provides a method for manufacturing a TFT substrate using an insulting film pattern.

The present invention discloses an insulating film pattern including a first surface having a first pattern part to form a source electrode, a drain electrode and a semiconductor layer of a thin film transistor, and a second surface facing the first surface. Further, the first pattern part includes a source pattern that extends in a first direction and is recessed in the insulating film pattern to form the source electrode, a drain pattern that is spaced apart from the source pattern and is recessed in the insulating film pattern to form the drain electrode, and a semiconductor pattern that is arranged between the source pattern and the drain pattern and is recessed in the insulating film pattern to form the semiconductor layer.

The present invention also discloses a method for manufacturing an insulating film pattern. The method includes forming a resist layer on an upper surface of a substrate, aligning an imprint apparatus with the resist layer, the imprint apparatus including an etching pattern, bonding the imprint apparatus to the substrate with the resist layer interposed between the imprint apparatus and the substrate, forming a first pattern part on a surface of the resist layer by the etching pattern, the first pattern part comprising a source pattern, a drain pattern, and a semiconductor pattern, and separating the imprint apparatus from the substrate with the resist layer having the first pattern part as an insulating film pattern bonded to the imprint apparatus.

The present invention also discloses a method for manufacturing a thin film transistor substrate. The method includes depositing on an upper surface of a base substrate an insulating film pattern having a first pattern part on an upper surface of the insulating film pattern, the first pattern part having a source pattern, a drain pattern, and a semiconductor pattern recessed in the insulating film pattern, forming a source electrode and a drain electrode of a thin film transistor through an inkjet print scheme using the source pattern and the drain pattern, forming a gate insulting film by etching a portion of the insulting film pattern, and forming a semiconductor layer of the thin film transistor through an inkjet print scheme using the semiconductor pattern.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

It will be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it can be directly on or directly connected to the other element or layer, mechanically or electrically, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on” or “directly connected to” another element or layer, there are no intervening elements or layers present.

FIG. 1is a sectional view illustrating an LCD panel according to an exemplary embodiment of the present invention, andFIG. 2is a plan view illustrating the TFT substrate100shown inFIG. 1.

Referring toFIG. 1andFIG. 2, an LCD400includes a TFT substrate100, an opposite substrate200facing the TFT substrate100, and a liquid crystal layer300interposed between the TFT substrate100and the opposite substrate200. The liquid crystal layer300includes liquid crystals310.

The TFT substrate100includes a first base substrate110, a gate line GL, a data line DL, a pixel part PX, and a gate insulating film140.

A pixel area PA is a region on the first base substrate110, and includes a region in which images are displayed.

The gate line GL is arranged on an upper surface of the first base substrate110and extends in a first direction D1to transmit a gate signal. The data line DL is arranged on the first base substrate110. The data line DL is insulated from the gate line GL and crosses with the gate line GL. The data line DL also extends in a second direction D2substantially perpendicular to the first direction D1. The data line DL and the gate line GL define the boundaries of the pixel area PA.

The pixel part PX is arranged in the pixel area PA. The pixel part PX includes a TFT120to provide a pixel voltage according to whether the TFT120is on or off, and a pixel electrode130to receive the pixel voltage from the TFT120.

In more detail, the TFT120includes a gate electrode121, a source electrode122, a drain electrode123, and a semiconductor layer124. The gate electrode121extends from the gate line GL, and the source electrode122extends from the data line DL to at least partially overlap with the gate electrode121. The drain electrode123faces the source electrode122with the semiconductor layer124interposed there between. The semiconductor layer124is arranged in a region corresponding to the gate electrode121and may partially cover an upper surface of the source electrode122and an upper surface of the drain electrode123. In addition, the semiconductor layer124may partially cover a lower surface of the source electrode122and a lower surface of the drain electrode123.

The pixel electrode130is connected to the drain electrode123to receive the pixel voltage. The pixel electrode130may include transparent conductive material such as Indium Zinc Oxide (IZO) or Indium Tin Oxide (ITO).

The gate insulating film140is arranged on the upper part of the first base substrate110on which the gate line GL and the gate electrode121are formed. The gate insulating film140may includes organic insulating material and covers the gate line GL and the gate electrode121. The date line DL, the source electrode122, the drain electrode123and the semiconductor layer124are arranged on an upper surface of the gate insulating film140. The upper surfaces of the source electrode122and the drain electrode123may be positioned lower than the upper surface of the gate insulating film140, and the gate insulating film140may cover a side surface of the source electrode122and a side surface of the drain electrode123.

The TFT substrate100further includes a protection film150. The protection film150is arranged on an upper part of the gate insulating film140to cover the data line DL, the source electrode122, the drain electrode123, and the semiconductor layer124. A contact hole CH is arranged in the protection film150to expose the drain electrode123. The pixel electrode130is arranged on an upper surface of the protection film150and is connected to the drain electrode123through the contact hole CH.

In addition, the TFT substrate100further includes a storage line SL to transmit a storage voltage and a storage electrode SE. The storage line SL and the storage electrode SE may be formed of the same material as the gate line GL, and may be formed during a process or step of forming the gate line GL. Although not shown inFIG. 1, the storage line SL and the storage electrode SE may be arranged on the same layer as the gate line GL. The storage line SL extends in the first direction D1, and the storage electrode SE extends from the storage line SL in the second direction D2on the pixel area PA.

The opposite substrate200is provided opposite to the TFT substrate100. The opposite substrate200includes a second base substrate210, a color filter220, a black matrix230, an overcoat layer240, and a common electrode250.

In more detail, the second base substrate210faces the first base substrate110, and the color filter220and the black matrix230are arranged on a lower surface of the second base substrate210to face the first base substrate110. The color filter220is arranged in the pixel area PA and filters out predetermined colors of light from light passing through the color filter220. The black matrix230blocks light and is arranged adjacent to the color filter220on the second base substrate210. The overcoat layer240is arranged on the black matrix230and the color filter220to planarize the opposite substrate200. The common electrode250is arranged on a lower surface of the overcoat layer240to receive a common voltage.

The liquid crystal layer300is interposed between the TFT substrate100and the opposite substrate200. Transmittance of light passing through the liquid crystal layer300is adjusted according to an electric field, which is generated between the pixel electrode130and the common electrode250and affects the alignment of the liquid crystals310in the liquid crystal layer300, and the light is provided to the color filter220.

FIG. 3is a flowchart showing a method for manufacturing a TFT substrate according to an exemplary embodiment of the present invention.

Referring toFIG. 1,FIG. 2, andFIG. 3, the gate line GL and the gate electrode121are formed on the first base substrate110(S110).

An insulating film pattern501is then formed on the first base substrate110(S120). The structure of the insulating film pattern501and the process of forming the insulating film pattern501will be described below in more detail with reference toFIG. 4,FIG. 5A, andFIG. 5B.

The data line DL, the source electrode122, and the drain electrode123may be formed through an inkjet print scheme using the insulating film pattern501(S130). Then, the semiconductor layer124and the gate insulating film140are formed using the insulating film pattern501(S140). As a result, the TFT120is formed on the first base substrate100.

The process of forming the TFT120and the gate insulating film140using the insulating film pattern501will be described below in more detail with reference toFIG. 6A,FIG. 6B,FIG. 6C,FIG. 6D, andFIG. 6E.

Then, the protection film150is formed on the first base substrate100(S150), and the pixel electrode130is formed on the protection film150(S160).

Hereinafter, the method for manufacturing the insulating film pattern501and the method for manufacturing the TFT120using the insulating film pattern501will be described in more detail with reference to the drawings.

FIG. 4is a perspective view illustrating a portion of the insulating film pattern501used to manufacture the TFT substrate100shown inFIG. 3.

Referring toFIG. 2andFIG. 4, the insulating film pattern501may include organic insulating material, and a first pattern part510is arranged on an upper surface of the insulating film pattern501.

The first pattern part510includes a first line pattern511used to form the data line DL (seeFIG. 1), a source pattern512used to form the source electrode122, a drain pattern513used to form the drain electrode123, and a semiconductor pattern514used to form the semiconductor layer124.

The first line pattern511, the source pattern512, the drain pattern513, and the semiconductor pattern514are recessed in the upper surface of the insulating film pattern501.

In more detail, the first line pattern511extends in the second direction D2and the source pattern512extends from the first line pattern511in the first direction D1. The drain pattern513faces the source pattern512with the semiconductor pattern514interposed there between, and extends in the first direction D1.

When viewed in a plan view, the semiconductor pattern514has a generally I-shape elongated in the first direction D1. A middle part of the semiconductor pattern514contacts an end of the source pattern512and an end of the drain pattern513, and the middle part has a width that is less than a distance between two ends of the semiconductor pattern514facing each other in the second direction D2.

In addition, the semiconductor pattern514is recessed deeper into the insulating film pattern501than the source pattern512and the drain pattern513. That is, the first line pattern511, the source pattern512, and the drain pattern513have substantially the same depth, and the semiconductor pattern514has a depth greater than that of the source pattern512. As a result, if the semiconductor layer124(seeFIG. 1) is formed through the inkjet print scheme, the deposited amount of liquid-phase semiconductor material may be more easily controlled, and the semiconductor layer124may be formed more precisely.

As described above, bottom surfaces512aand513a, which define a lower surface of the source pattern512and the drain pattern513, respectively, are positioned higher than a bottom surface514athat defines a lower surface of the semiconductor pattern514. For this reason, if the source electrode122and the drain electrode123are formed through the inkjet print scheme, the liquid-phase metal dropped in the source pattern512and the drain pattern513might be introduced into the semiconductor pattern514.

To prevent the liquid-phase metal from being introduced into the semiconductor pattern514, the first pattern part510also includes a first partition wall515and a second partition wall516. The first partition wall515is arranged between the source pattern512and the semiconductor pattern514, and protrudes from the bottom surface512ato surround an end of the source pattern512. Accordingly, when the source electrode122is formed, the amount of ink dropped to form the source electrode122can be more easily controlled and the source electrode122can be formed more precisely because of the first partition wall515.

In an exemplary embodiment of the present invention, a distance from the bottom surface512ato an upper surface515aof the first partition wall515is less than a distance from the bottom surface512ato the upper surface of the insulating film pattern501.

The second partition wall516is arranged between the drain pattern513and the semiconductor pattern514, and protrudes from the bottom surface513ato surround an end of the drain pattern513. Accordingly, when the drain electrode123is formed, the amount of ink dropped to form the drain electrode123can be more easily controlled and the drain electrode123can be formed more precisely because of the second partition wall516.

In an exemplary embodiment of the present invention, a distance from the bottom surface513ato an upper surface516aof the second partition wall516is less than a distance from the bottom surface513ato the upper surface of the insulating film pattern501.

Hereinafter, the method for manufacturing the insulating film pattern501through an imprint scheme will be described in more detail with reference to the drawings.

FIG. 5AandFIG. 5Bare sectional views showing a method for manufacturing the insulating film pattern501shown inFIG. 4.

Referring toFIG. 5A, a resist layer620, which may include an organic insulating material, is formed on a substrate610.

An imprint apparatus700is disposed above the substrate610on which the resist layer620is formed. The imprint apparatus700includes an imprint substrate710and a mold layer720formed at one side of the imprint substrate710. The mold layer720is provided with an etching pattern721to etch the resist layer620.

With the imprint apparatus700disposed above the resist layer620, the etching pattern721of the mold layer720is then directed downward.

Then, the imprint apparatus700bonds to the substrate610with the resist layer620interposed there between.

Referring toFIG. 5B, as the imprint apparatus700is pressed against the substrate610, the resist layer620is bonded to the mold layer720. As a result, the insulating film pattern501is formed from the resist layer620, and the first pattern part510is formed on the upper surface of the insulating film pattern501in a region corresponding to the etching pattern721.

After that, the imprint apparatus700is separated from the substrate610with the mold layer720bonded to the insulating film pattern501.

Hereinafter, the method for manufacturing the TFT120using the insulating film pattern501will be described in more detail with reference to the drawings.

Referring toFIG. 6AandFIG. 6B, the imprint apparatus700bonded with the insulating film pattern501is disposed above the first base substrate110on which the gate electrode121is disposed. Although not shown inFIG. 6AandFIG. 6B, the gate line GL (seeFIG. 2), the storage line SL (seeFIG. 2) and the storage electrode SE (seeFIG. 2) can be formed on the upper surface of the first base substrate110during a process in which the gate electrode121is formed.

Then, with the insulating film pattern501interposed between the imprint apparatus700and the first base substrate110, the imprint apparatus700is bonded to the first base substrate110.

After that, with the insulating film pattern501bonded to the first base substrate110, the imprint apparatus700is separated from the first base substrate110. Accordingly, as shown inFIG. 6B, the insulating film pattern501is formed on the first base substrate110. The upper surface of the insulating film pattern501, on which the first pattern part510is formed, is exposed, and the semiconductor pattern514of the first pattern part510is disposed on the gate electrode121.

As described above, the insulating film pattern501is formed through the imprint scheme, and is deposited on the first base substrate110through a contact print scheme. Accordingly, the number of the processes to form the TFT substrate100can be reduced, the productivity may be improved and the manufacturing cost may be reduced by simplifying the manufacturing steps.

Referring toFIG. 6C, liquid-phase metal is dropped on the source pattern512and the drain pattern514of the insulating film pattern501to form the source electrode122and the drain electrode123on the insulating film pattern501.

Although not shown inFIG. 6C, the data line DL (seeFIG. 2) may be formed during a process or step in which the source electrode122and the drain electrode123are formed, and the data line DL may be formed using the first line pattern511(seeFIG. 4) through the same scheme as the source electrode122.

Referring toFIG. 6DandFIG. 6E, a portion of the insulting film pattern501, including a portion near where the source electrode122and the drain electrode123are formed, undergoes an ashing process, thereby removing the first and second partition walls515and516. During the ashing process, the insulating film pattern501is also subject to an undercut etching at a portion below the source electrode122and the drain electrode123. By these steps, the gate insulating film140is formed on the first base substrate110.

After that, the liquid-phase organic semiconductor material is dropped on the semiconductor pattern514formed in the gate insulating film140, thereby forming the semiconductor layer124. As a result, the TFT120is formed. Since the semiconductor pattern514is more deeply recessed than the source pattern512and the drain pattern514, the amount of organic semiconductor material can be more easily controlled, and the semiconductor layer124can be more precisely formed.

As described above, in the TFT substrate100, the TFT120, and the gate insulating film140are formed using the insulating film pattern501. Accordingly, the source electrode122, the drain electrode123, and the semiconductor layer124are formed through the inkjet print scheme, so that the process time may be reduced, the productivity may be improved, and the manufacturing cost may be reduced.

FIG. 7is a flowchart showing a method for manufacturing the TFT substrate100according to another exemplary embodiment of the present invention.

Referring toFIG. 1,FIG. 2, andFIG. 7, an insulating film pattern502(seeFIG. 8) is formed on the first base substrate110(S210). The structure of the insulating film pattern502and the method for manufacturing the insulating film pattern502will be described in more detail with reference toFIG. 8,FIG. 9A, andFIG. 9B.

The gate line GL and the gate electrode121are formed through the inkjet print scheme using the insulating film pattern502(S220).

The data line DL, the source electrode122, and the drain electrode123are formed through the inkjet print scheme using the insulating film pattern502(S230).

Then, the semiconductor layer124and the gate insulating film140are formed using the insulating film pattern502(S240). As a result, the TFT120is formed on the first base substrate100.

The process of forming the gate insulating film140using the insulating film pattern502will be explained below in reference toFIG. 10AandFIG. 10B.

Then, the protection film150is formed on the first base substrate100(S250), and the pixel electrode130is formed on the protection film150(S260).

FIG. 8is a perspective view illustrating a portion of the insulating film pattern502used to manufacture the TFT substrate100shown inFIG. 1.

Referring toFIG. 2andFIG. 8, the insulating film pattern502may include organic insulating material, and the first pattern part510is formed on an upper surface of the insulating film pattern502to form the source electrode122, the drain electrode123, and the semiconductor layer124of the TFT120. Since the first pattern part510according to the present exemplary embodiment is substantially similar to the first pattern part510of the insulating film pattern501shown inFIG. 4, the same reference numerals will be used to designate the same elements, and detailed description thereof will be omitted to avoid redundancy.

In addition, a second pattern part520is formed at a lower surface of the insulating film pattern502. The second pattern part520is recessed in the lower surface of the insulating film pattern502and is separated from the first pattern part510.

In more detail, the second pattern part520includes a second line pattern521used to form the gate line GL and a gate pattern522used to form the gate electrode121. The second line pattern521extends in the first direction D1, and crosses with the first line pattern511below the first pattern part510. The gate pattern522extends from the second line pattern521and is disposed in a region below and corresponding to the semiconductor pattern514of the first pattern part510.

Although not shown inFIG. 8, the second pattern part520may further include patterns to form the storage line SL and the storage electrode SE.

Hereinafter, the method for manufacturing the insulating film pattern502using the imprint scheme will be described in more detail with reference to the drawings.

FIG. 9AandFIG. 9Bare sectional views showing a method for manufacturing the insulating film pattern502shown inFIG. 8.

Referring toFIG. 9A, a dummy pattern630having a shape corresponding to the gate line GL (seeFIG. 2) and the gate electrode121(seeFIG. 1) is arranged on the substrate610. Although not shown inFIG. 9A, if the storage line SL (seeFIG. 2) and the storage electrode SE are formed together with the gate line GL and the gate electrode121, and patterns to form the storage line SL and the storage electrode SE are included in the second pattern part520, an additional pattern having a shape corresponding to the storage line SL (seeFIG. 2) and the storage electrode SE may be arranged on the substrate610together with the dummy pattern630.

Then, the resist layer620, which may include organic insulating material, is formed on the substrate610on which the dummy pattern630is formed.

The imprint apparatus700is disposed above the substrate610on which the resist layer620is formed. Since the imprint apparatus700according to the present exemplary embodiment has a structure substantially similar to that of the imprint apparatus700shown inFIG. 5A, the same reference numerals will be used to designate the same elements, and detailed description thereof will be omitted to avoid redundancy.

When the imprint apparatus700is disposed above the resist layer620, the etching pattern721of the mold layer720is directed downward.

Then, the imprint apparatus700is bonded to the substrate610with the resist layer620interposed there between.

Referring toFIG. 9B, as the imprint apparatus700is pressed against the substrate610, the resist layer620bonds to the mold layer720of the imprint apparatus700. As a result, the insulating film pattern502is formed, and the first pattern part510is formed on the upper surface of the insulating film pattern502in a region corresponding with the etching pattern721.

After that, the imprint apparatus700is separated from the substrate610with the mold layer720bonded to the insulating film pattern502. The insulating film pattern502is separated from the substrate610and the dummy pattern630, so that the second pattern part520is formed at the lower surface of the insulating film pattern502by the dummy pattern630.

Hereinafter, the method for manufacturing the TFT120using the insulating film pattern502will be described in more detail with reference to the drawings.

FIG. 10AandFIG. 10Bare sectional views showing a process of forming the TFT120using the insulating film pattern502shown inFIG. 8.

Referring toFIG. 10A, the insulating film pattern502is deposited on the first base substrate110through the contact print scheme. Since the process of depositing the insulting film pattern502according to the present exemplary embodiment is substantially similar to that shown inFIG. 6A, the detailed description thereof will be omitted in order to avoid redundancy. The upper surface of the insulating film pattern502on which the first pattern part510is formed is exposed, and the lower surface of the insulating film pattern502on which the second pattern part520is formed contacts the upper surface of the first base substrate110.

As described above, the insulting film pattern502is formed through the imprint scheme, and is deposited on the first base substrate110through the contact print scheme. Accordingly, the number of processes can be reduced, the productivity can be improved and the manufacturing cost can be reduced.

Referring toFIG. 10B, the gate electrode121is formed through the inkjet print scheme using the gate pattern522of the second pattern part520of the insulating film pattern502. Liquid-phase metal is injected into a side of the insulating film pattern502to form the gate electrode121.

Although not shown inFIG. 10B, the gate line GL (seeFIG. 2) may be formed in a process or step of forming the gate electrode121, and the gate line GL is formed through a similar manufacturing process as the gate electrode121using the second line pattern521(seeFIG. 8) of the second pattern part520.

Subsequently, liquid-phase metal is dropped on the source pattern512and the drain pattern514of the insulating film pattern502to form the source electrode122and the drain electrode123, respectively.

After that, the semiconductor layer124(seeFIG. 1) and the gate insulating film140(seeFIG. 1) are formed. Since the process of forming the semiconductor layer124and the gate insulting film140is substantially similar to that shown inFIG. 6DandFIG. 6E, the detailed description thereof will be omitted to avoid redundancy.

As described above, in the TFT substrate100, the TFT120, and the gate insulating film140are formed using the insulating film pattern502. Accordingly, the TFT120of the TFT substrate100is formed through the inkjet print scheme, so the process time may be reduced, the productivity may be improved, and the manufacturing cost may be reduced.