Audio signal circuit with in-place bit-reversal

An integrated circuit for processing audio signals from a microphone assembly, combinations thereof and methods therefor, including a multi-issue processor configured to execute multiple instructions concurrently and connectable to a memory with a plurality of locations each represented by a corresponding index. Bit-reversal is performed on a sequence of audio data bits stored in memory by concurrently performing a load or store operation related to a first index and determining whether to perform a load operation for a second index.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to digital audio signal processing and more particularly to in-place bit reversal in electrical circuits for use in microphone assemblies, combinations thereof and methods.

BACKGROUND

The processing of digital audio signals obtained from a microphone is known generally. Some such signals are obtained from a microelectromechanical systems (MEMS) microphone including a MEMS transducer and an electrical circuit disposed in a housing having a sound port and host device interface among other microphones.

DETAILED DESCRIPTION

Turning now toFIG. 1, an example implementation of a microphone assembly100is shown, according to some embodiments. Microphone assembly100can be a surface-mount component for use in a variety of electronic devices such as smart phones, laptops, and tablets. Microphone assembly100includes a MEMS transducer120that is configured to convert acoustic energy into an electrical output and an integrated circuit125that is configured to process electrical signals output from transducer120. Microphone100is also shown to include a substrate105(e.g., base, printed circuit board) on which MEMS transducer120and integrated circuit125are mounted. Substrate105can include any number of insulating layers, metal layers, and connection pads/paths. For example, processed audio signals can be provided to a host device (e.g., smart phone, laptop) via one or more connection pads on the bottom of substrate105.

In some embodiments, MEMS transducer120is a capacitive transducer. For example, MEMS transducer120can include two or more electrodes, at least one of which is movable in the presence of sound pressure to vary the capacitance. Other transducers may be embodied as a piezoelectric device. In some embodiments, transducer120is connected to integrated circuit125via wire bonds130. Electrical signals output from transducer120can be sent to integrated circuit125for processing, such as to generate an output signal representative of the sensed acoustic activity. For example, processing via integrated circuit125can include filtering, buffering, amplification, analog-to-digital conversion, digital-to-analog conversion, quantization, decimation, phase shifting, etc. Microphone100is also shown to include a cover110that is coupled to substrate105. Substrate105and cover110form a housing or packaging that encloses and protects transducer120and integrated circuit125. In the illustrated bottom port embodiment, a back volume of transducer120is defined between transducer120and the housing. In some embodiments, cover110comprises a metal material that provides radio-frequency protection and other noise reduction capabilities.

Microphone100is an example of a bottom port configuration. As shown, sound energy travels through an acoustic port115that is formed in substrate105. The configuration shown is intended to be exemplary and variations thereof are contemplated within the scope of the present disclosure. For example, MEMS transducer120could be a dual motor transducer, integrated circuit125could be embedded in the substrate, and/or one more sensors (e.g., pressure sensors, temperature sensors, etc.) could be included in various configurations not shown inFIG. 1. Further, an ingress protection element could be disposed over port115and/or port115could be formed in cover110instead of substrate105.

FIG. 2is a block diagram showing an integrated circuit202, according to some embodiments. Integrated circuit202could be disposed in the housing of microphone assembly100(e.g., integrated circuit125) or it could be coupled to an output of one or more microphone assemblies of the type shown inFIG. 1, for example as part of a host device. Thus, integrated circuit202may be embodied as an application-specific integrated circuit (ASIC) configured to process audio signals generated by one or more transducers. ASIC202is shown to include a processor210and a memory220. The integrated circuit may include a processor and a memory on one common die or the processor and memory may be fabricated on separate dies. Processor210is a multi-issue processor configured to execute at least two instructions concurrently. It will be appreciated that processor210may execute instructions at varying levels of instructions per clock cycle. In some embodiments, processor210is a dual-issue processor configured to execute two instructions concurrently; however, it should be understood that the present disclosure is not limited to dual-issue processors. In some implementations, ASIC202may be used to perform operations that utilize bit-reversal. For example, some operations performed by the ASIC as part of processing the data representative of the sensed acoustic activity may involve performing fast Fourier transform (FFT) or inverse fast Fourier transform (IFFT) calculations.

InFIG. 2, memory220can include registers, buffers, and a main memory (e.g., RAM). Data in the registers can be accessed quickly by processor210and data can be stored temporarily in the buffers. Memory can also include other parts such as caches and/or a secondary memory that is not directly connected to processor as the main memory is. It will be appreciated that the ASIC can be implemented using a variety of architectures. Moreover, the components of memory220shown inFIG. 2are not intended to be exhaustive and can also be implemented in a variety of ways.

Memory220is shown to include an input data buffer200. Buffer200can be configured to store input data associated with an audio signal generated by one or more transducers. In some embodiments, buffer200holds sixteen data values that can each be associated to an index. The indices can be expressed in binary from 0000 to 1111 or in decimal from 0 to 15. In order to perform FFT and/or IFFT calculations, the data in buffer200can be rearranged in bit-reverse order. The systems and methods described herein provide an efficient method to perform such a bit-reversal in-place (i.e., no additional buffers are used). While the present disclosure provides methods for performing bit-reversal in place using a single buffer, it should be appreciated that the techniques of the present disclosure could also be used to perform bit-reversal using multiple buffers. Likewise, a single buffer could be split (e.g., in half), and the methodology described herein could be used to perform multiple bit-reversals using a single buffer, or a single bit-reversal could be split into two or more parts using a single buffer. Processor210includes a load-store unit configured to execute load and store instructions such that the load-store unit loads data from buffer200into registers and stores data from registers back to buffer200. In some embodiments, processor210includes only this single load-store unit such that only one load or store instruction can be executed at a time.

Memory220is also shown to include a forward index A222, a reverse index A223, a forward index B224, a reverse index B225, a swap enable A226, a swap enable B227, a forward value228, a reverse value229, a max index230, and an FFT/IFFT length231. The purpose of each of these components will become apparent throughout the disclosure, especially with respect toFIGS. 5A-5Bdescribed below. Each of these indices and values can be stored in registers of memory220and are updated throughout a bit-reverse process associated with buffer200.

Forward index A222and forward index B224can be used to represent an index of buffer200being analyzed by processor210during the bit-reverse process. Processor210uses one of these indices to perform a swap while concurrently using the other index to look ahead and determine the next index of buffer200that requires a swap to complete the bit-reverse process. Reverse index A223and reverse index B225can be used by processor210to represent a bit-reverse counterpart of forward index A222and forward index B224, respectively. Processor210can be configured to determine that a swap needs to be performed for a given index pair (forward index A222and reverse index A223or forward index B224and reverse index B225) if a value (e.g., a decimal value) associated with the forward index is less than a value associated with its bit-reverse counterpart. For example, if the forward index is 0010, then the bit-reverse counterpart is 0100, and processor210determines that a swap is needed because the value 2 is less than the value 4. However, if the forward index is 1010, then the bit-reverse counterpart is 0101, and processor210determines that a swap is not needed because the value 10 is greater than the value 5. Processor210can be configured to set swap enable A226or swap enable B227(e.g., bits) to 1 if a swap is needed for a given forward/reverse index pair and set swap enable226or swap enable227to 0 if a swap is not needed. It will be appreciated that the comparison of the forward index and the reverse index could be reversed (i.e. check if forward index is greater than reverse index, and reverse associated operations) if desired. The same comparison should (greater than or less than) should be used throughout the bit-reverse process.

Forward value register228and reverse value register229can be used as temporary storage for data loaded from buffer200during the bit-reverse process. For example, if processor210determines that a swap is needed for a given index pair, processor210can execute a first load instruction to load the value in buffer200at the forward index (index222or224) into forward value register228and execute a second load instruction to load the value in buffer200at the reverse index (index223or225) into reverse value register229. Next, processor210can be configured to execute a first store instruction to store the value in forward value register228in buffer200at the reverse index and a second store instruction to store the value in reverse register229in buffer200at the forward index, thereby completing a swap for the given index pair.

Processor210can use max index230and FFT/IFFT length231during the bit-reverse process as variables to ensure that generated indices are within a specified range and that bit-reverse counterparts are generated in proper fashion for an FFT/IFFT calculation. For example, if buffer200holds 16 values, then max index230can be set to 15 (1111). FFT/IFFT length231, for example, can be set to log2(N)−1, where N is the length of the FFT/IFFT. Max index230can be set to lower values to terminate swapping earlier and save additional clock cycles. For example, if buffer200holds 16 values, then max index230can be set to the value 11 (1011) because no swapping can occur after that index.

It will be appreciated that forward index A222, reverse index A223, forward index B224, reverse index B225, swap enable A226, swap enable B227, forward value228, reverse value229, max index230, and FFT/IFFT length231can be implemented in a variety of ways within depending on the desired footprint and specific hardware environment. For example, if each index of buffer200can be represented using four bits, then indices222,223,224, and225can be contained in a single 16-bit register.

Turning now toFIG. 3, one example of buffer200contents before and after a bit-reverse operation is performed is shown, according to some embodiments. In this case, buffer200stores sixteen data values each represented by a four bit index.FIG. 3serves as an example of input data buffer200that will be referenced in more detail below.

Turning now toFIG. 4, an example of index comparison used in a bit-reverse process associated with buffer200is shown, according to some embodiments. Similar toFIG. 3, table400shows an example where buffer200stores sixteen data values each represented by a four bit index. The first and second columns of table400show a forward index (analogous to indices222and224) and the third and fourth columns of table400show the bit-reverse counterpart of the forward index (analogous to indices223and225). The fifth column of table400shows whether a swap is needed for each index pair (analogous to swap enables226and227). Table400serves as a reference to supplement the description below with respect toFIGS. 5A-5B.

Turning now toFIGS. 5A-5B, a table illustrating an in-place bit-reverse process500is shown, according to some embodiments. Process500is performed by ASIC202in order to reverse the contents of buffer200without using any other buffers. Process500is part of a larger signal processing process that generally comprises converting an input signal (e.g., audio) into an output signal (e.g., microphone output). This larger process can include analog-to-digital conversion, digital-to-analog conversion, filtering, fast Fourier transform (FFT) calculations, and inverse fast Fourier transform (IFFT) calculations, for example. When performing a power of two length (2N) FFT or IFFT calculation, a stream of digital data (i.e., a sequence of bits) can be reversed in-place with minimal processing and hardware requirements using process500.

As illustrated inFIGS. 5A-5B, processor210is a dual-issue processor configured to execute two instructions concurrently. Accordingly, each row of the table is shown to include a first instruction, a second instruction, and an associated clock cycle. As mentioned above, it will be appreciated that processor210may execute instructions at varying levels of clock cycles per instruction. For the remainder of the disclosure, an example implementation in which processor210executes instructions at a rate of one instruction per clock cycle will be described.FIGS. 5A-5Bonly depict the first eleven clock cycles of process500, however the remainder of clock cycles associated with process500can be inferred in view of these first eleven clock cycles. For a given clock cycle, the first instruction generally involves performing a load or store and the second instruction generally involves determining the next index of buffer200that requires swapping.

As shown inFIG. 5A, the first clock cycle is used for initialization (or setup). The first clock cycle of process500includes initializing forward index A222, generating reverse index A223, and generating swap enable A226. During the first clock cycle, processor210can be configured to initialize index222to 0001 (the second index of buffer200). Index222can be initialized to any value, however the example description of process500below assumes that index222is initialized to 0001. Processor210can then generate index223(also 1000) from index222and generate swap enable226based on a comparison of index222and index223. In this cycle, index222is less than index223(1<8), so processor210sets swap enable226to 1. This cycle is analogous to the second row of table400, wherein a swap is performed for the second index of buffer200. During the first clock cycle, processor210may not execute a second instruction related to process500in parallel with the initialization of index222, index223, and swap enable226as indicated inFIG. 5A(no operation). As mentioned, it will be appreciated that any index value may be used as a starting point depending on the specific application of process500. For example, a high index such as 1111 may be used as a starting point, or a middle index such as 0111 may be used as a starting point. A middle index may be a useful starting point in implementations where a single buffer is used to perform multiple bit-reversals.

During the second clock cycle of process500, processor210loads the value stored in buffer200at index222into forward value register228. This load instruction can be executed by the load-store unit of processor210, for example. In this case, index222is set to 0001, so processor210loads the value 43 into register228(referring to the example ofFIG. 3for the value 43). In the second instruction, processor210calculates forward index B224, reverse index B225, and swap enable B227based on index222as generated during the first clock cycle. Processor210sets index224to the value of index222+1. In this case, continuing with the above example, processor210sets index224to 0010, the third index of buffer200. Processor210then generates index225based on index224(0100) and sets swap enable227. In this case, swap enable227is set to 1 since index224is less than index225(2<4). This step is analogous to the third row of table400, wherein a swap is performed for the third index of buffer200.

Next, during the third clock cycle of process500, processor210is configured to load the value stored in buffer200at index223into reverse value register229. This load instruction can again be executed by the load-store unit of processor210. In this case, index223is set to 1000, so processor210loads the value 47 into register229. Concurrently, if swap enable227is 0, processor210is configured to increment index224, generate index225based on index224, and update swap enable227accordingly. In this case, since swap enable227is already 1, no updates occur.

During the fourth clock cycle of process500, if swap enable226is set to 1, processor210is configured to store the value in reverse register229in buffer200at forward index222. This store instruction can also be executed by the load-store unit of processor210. In this case, during the fourth clock cycle, swap enable226is indeed set to 1, so processor210stores the value 47 in register229to memory at index222(0001) of buffer200. This is consistent with the illustration of buffer200after the bit-reverse operation is complete as shown inFIG. 3. In parallel, if swap enable227is 0, processor210is configured to increment index224, generate index225based on index224, and update swap enable227. However, in this case, swap enable227is set to 1, so processor210does not update index224, generate index225, or update swap enable227.

During the fifth clock cycle of process500, if swap enable226is set to 1, processor210is configured to store the value in forward register228in buffer200at reverse index223. This store instruction can again be performed by the load-store unit of processor210. In this case, since swap enable226is set to 1, during the fifth clock cycle, processor210stores the value 43 in register228to memory at index223(1000). This again is consistent with the illustration of buffer200after the bit-reverse operation is complete as shown inFIG. 3. In parallel, if swap enable227is 0, processor210is again configured to increment index224, generate index225based on index224, and update swap enable227. However, in this case, swap enable227is still set to 1, so processor210does not update index224, generate index225, or update swap enable227.

During the sixth clock cycle of process500, processor210is configured to load the value stored in buffer200at index224(0010) into forward value register228. In this case, processor210loads the value 18 into register228. Concurrently, processor210is configured to set index222to the incremented value of index224, generate index223based on index222, and update swap enable226accordingly. In this case, the incremented value of index224is 0011, so processor210sets index222to 0011. During the sixth clock cycle, processor210also sets index223to 1100 (the bit-reverse counterpart of index222) and sets swap enable226to 1 since index222is less than index223(3<12). This step is analogous to the fourth row of table400.

Referring now toFIG. 5B, during the seventh clock cycle, processor210is configured to load the value stored in buffer200at index225into reverse value register229. In this case, index225is set to 0100, so processor210loads the value 11 into register229. Concurrently, if swap enable226is set to 0, processor210is configured to increment index222, update index223based on index222, and update swap enable226accordingly. In this case, since swap enable226is set to 1, no changes occur to these registers.

During the eighth clock cycle of process500, if swap enable227is set to 1, processor210is configured to store the value in reverse register229in buffer200at forward index224. In this case, processor210stores the value 11 at index 0010 of buffer200. This again is consistent with the illustration of buffer200after the bit-reverse operation is complete as shown inFIG. 3. Concurrently, if swap enable226is set to 0, processor210is configured to increment index222, update index223based on index222, and update swap enable226accordingly. However, in this case, swap enable226is still set to 1, so processor210does not make any changes to these registers.

During the ninth clock cycle of process500, if swap enable227is set to 1, processor210is configured to store the value in forward register228in buffer200at reverse index225. In this case, processor210stores the value 18 at index 0100 of buffer200. This again is consistent with the illustration of buffer200after the bit-reverse operation is complete as shown inFIG. 3. Concurrently, if swap enable226is set to 0, processor210is again configured to increment index222, update index223based on index222, and update swap enable226accordingly. However, in this case, swap enable226is still set to 1, so processor210does not increment index222, generate index223, or update swap enable226.

During the tenth clock cycle of process500, similar to the second clock cycle, processor210loads the value stored in buffer200at index222into forward value register228. Now, index222is set to 0011, so processor210loads the value 32 into register228. Concurrently, processor210is configured to set index224to the incremented value of index222, update index225based on index224, and update swap enable227accordingly. In this case, processor210sets index224to 0100, sets index225to 0010, and updates swap enable227to 0 since index224is now greater than index225(4>2). This step is analogous to the fifth row of table400, wherein a swap is not performed for the fifth index of buffer200.

During the eleventh clock cycle, similar to the third clock cycle, processor210loads the value stored in buffer200at index223into reverse value register229. Now, index223is set to 1100, so processor210loads the value 27 into register229. Concurrently, if swap enable227is set to 0, processor210is configured increment index224, generate index225based on index224, and update swap enable227accordingly. In this case, swap enable227is indeed set to 0, so processor210increments index224to 0101, sets index225to 1010, and updates swap enable227to 1 since index224is now less than index225(5<10). This step is analogous to the sixth row of table400, wherein a swap is not performed for the sixth index of buffer200. The look ahead capabilities and associated cycle reductions of process500are demonstrated in part by the “skipping” of index 0100 that occurs here.

While not shown explicitly inFIG. 5B, it can be inferred that, during the twelfth clock cycle of process500(similar to the fourth clock cycle), if swap enable226is set to 1, processor210is configured to store the value in reverse register229in buffer200at forward index222. In this case, swap enable226is indeed set to 1, so processor210stores the value 27 in register229to memory at index222(0011) of buffer200. Concurrently, processor210is configured to increment index224, generate index225based on index224, and update swap enable227accordingly if swap enable227is set to 0. In this case, swap enable227is still set to 1, so processor210does not make any updates to these registers.

It can also be inferred that, during the thirteenth clock cycle of process500, processor210completes the swap between index 0011 and index 1100 of buffer200. Moreover, in the fourteenth through seventeenth clock cycles, it can be inferred that processor completes a swap between index 0101 and index 1010 of buffer200. It can also be inferred that processor210looks ahead and skips index 0110 in parallel to executing the load and store instructions required to complete the swap between index 0101 and index 1010.

During the eighteenth clock cycle of process500, it can be inferred that processor210loads the value in buffer200at index 0111 (62) in parallel to setting the look ahead index (in this case, index222) to 1000 and accordingly setting swap enable226bit to 0 (thereby skipping memory accesses associated with index 1000). Moreover, processor210skips indices 1001 and 1010 during the nineteenth and twentieth clock cycles before loading the value in buffer200at index 1011 during the twenty-second clock cycle. Process500, as described in this example, ends during the twenty-fifth clock cycle as processor210completes the swap between indices 1011 and 1101 while concurrently determining that the look ahead index (in this case, index224) has reached the same value as max index230. Accordingly, outside of the initialization step performed during the first clock cycle, process500reverses the data in buffer200in just 24 clock cycles.

While the example described above relates to an embodiment where buffer200holds 16 values, it will be appreciated that the methods described herein apply to buffer of various sizes. For example, buffer200could also hold 32 values (25) or 64 values (26). For these larger size buffers, process500may experience some cycle penalties assuming that processor210is a dual-issue processor. For example, as shown in table400, at most three consecutive indices (1000, 1001, 1010) do not require swapping (excluding the max index 1111) for a buffer size16, so no cycle penalties occur. However, it will be appreciated that process500can still handle larger buffer sizes with only a limited number of cycle penalties.

Turning now toFIG. 6, an example table600that compares process500to previous approaches is shown, according to some embodiments. Table600shows a number of clock cycles required to complete an in-place bit reversal for buffers of size16(24) to 4096 (212). The data in table600under the “present methodology clock cycles” column assumes that processor210is a dual-issue processor. Some of the cycle reductions shown in table600can be realized through the use of max index230as described above. As shown, consistent with the example described above, for a buffer size16, process500completes the in-place bit reversal in just 24 clock cycles. When compared to previous approaches, process500achieves a speedup factor of about 1.95. These previous approaches typically involve pipelined instruction architectures and wasted clock cycles that result from unnecessary branching instructions when compared to process500. As buffer size increases, the cycle penalties described above with respect to process500can be seen in table600. However, as buffer size increases, the speedup factor associated with process500also increases.

Turning now toFIG. 7, a flow diagram of a process700for an efficient in-place bit-reversal for audio processing applications is shown, according to some embodiments. Process700can be performed by any type of audio processing circuit with a multi-issue processor such as ASIC202. Process700is related to process500, however process700provides more of a general overview of the methodology described herein. In some embodiments, process700is performed by a dual-issue processor with a single load-store unit. However, it will be appreciated that process700can be adapted for various hardware environments in order to minimize processing power and memory usage associated with an in-place bit-reversal.

Process700is shown to include storing a sequence of audio data bits in memory (step702). Process700is also shown to include initiating a bit-reverse process associated with the sequence of audio data bits stored in memory (step704). For example, processor210can be configured to initiate process500in response to a determination that the audio data bits in buffer200need to be rearranged in bit-reverse order. An example of buffer200before and after such a bit-reversal is shown above inFIG. 3. In some embodiments, the bit-reverse process is initiated by initializing indices222and223as well as swap enable226during a first clock cycle and subsequently setting indices224and225and setting swap enable227during a second clock cycle. Max index230as well as FFT/IFFT length231can also be determined as part of the initiation of the bit-reverse process.

Process700is also shown to include executing a first instruction that includes performing a load or store operation related to a first index (step706). By way of example, consider again that buffer200holds sixteen values each represented by a four bit index. In this example, also consider that step706includes loading the value in buffer200at index 0111 into forward value register228. Referring to the example of buffer200shown inFIG. 3, this means that processor210loads the value 62 into register228. It will be appreciated that in this example, step706may not be the first load instruction executed during the bit-reverse process, however index 0111 provides an example of the look ahead capabilities associated with the methodology described herein.

Process700is also shown to include executing a second instruction that includes determining whether to perform a load operation related to a second index (step708). Step708can be executed concurrently with step706. Continuing with the above example, the forward index (e.g., index224) may be set to 0111 and used by processor210during the load instruction executed in step706. Accordingly, the look ahead index (e.g., index224) may be set to 1000 (0111+1) and its bit-reverse counterpart (e.g., index225) may be set to 0001 in step708. Processor210can be configured to compare a value associated with the look ahead index and its bit-reverse counterpart and set a swap enable (e.g., swap enable227) accordingly. In this case, processor210can determine that the value 8 associated with index 1000 is greater than the value 1 associated with index 0001 and can set the swap enable to 0 (step710). Accordingly, processor210can determine that a load operation should not be performed for index 1000.

Process700is also shown to include executing a third instruction that includes performing a load or store operation related to the first index (step712). Continuing with the above example, processor210can be configured to load the value at index 1110 (the bit-reverse counterpart of the first index 0111) into reverse value register229. Referring again to the example of buffer200shown inFIG. 3, processor210can load the value 38 into register229. Concurrently, processor210can be configured to execute a fourth instruction that includes determining whether to perform a load operation related to a third index (step714). In this case, processor210can be configured to increment the look ahead index to 1001, generate the bit-reverse counterpart of the look ahead index (also 1001), and determine if a load operation should be performed for the look ahead index 1001. In this case, since the look ahead index is equal to its bit-reverse counterpart, processor210can determine that a load operation should not be performed for index 1001 and can again set the swap enable to 0.

Process700is also shown to include executing a fifth instruction that includes performing a store operation related to the first index (step716). Still continuing with the above example, processor210can be configured to store the value in reverse register229in buffer200at the forward index 0111. Meanwhile, concurrently, processor210can be configured to execute a sixth instruction that includes determining whether to perform a load operation related to a fourth index (step718). In this case, processor210can again be configured to increment the look ahead index to 1010, generate the bit-reverse counterpart of the look ahead index (0101), and determine if a load operation should be performed for the look ahead index. In this case, the look ahead index is greater than its bit-reverse counterpart (10>5), so processor210can determine that a load operation should not be performed for index 1010 and can accordingly set the swap enable to 0.