Semiconductor Device and Method of Forming Graphene-Coated Core Embedded Within TIM

A semiconductor device has a substrate and electrical component disposed over the substrate. The electrical component can be a semiconductor die, semiconductor package, surface mount device, RF component, discrete electrical device, or IPD. A TIM is deposited over the electrical component. The TIM has a core, such as Cu, covered by graphene. A heat sink is disposed over the TIM, electrical component, and substrate. The TIM is printed on the electrical component. The graphene is interconnected within the TIM to form a thermal path from a first surface of the TIM to a second surface of the TIM opposite the first surface of the TIM. The TIM has thermoset material or soldering type matrix and the core covered by graphene is embedded within the thermoset material or soldering type matrix. A metal layer can be formed between the TIM and electrical component.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of heat dissipation using graphene-coated core embedded within thermal interface material (TIM).

BACKGROUND OF THE INVENTION

Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, photo-electric, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

The SIP module includes high speed digital and RF electrical components, highly integrated for small size and low height, and operating at high clock frequencies and high power rating. The electrical components are known to generate substantial heat, which must be properly dissipated. Copper is good material to solderability and wettability of solder paste. A need still exists to improve heat dissipation, particularly in applications involving high speed digital and RF electrical components.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The features shown in the figures are not necessarily drawn to scale. Elements having a similar function are assigned the same reference number in the figures. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are disposed on a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

FIG.1ashows a semiconductor wafer100with a base substrate material102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor die or components104is formed on wafer100separated by a non-active, inter-die wafer area or saw street106. Saw street106provides cutting areas to singulate semiconductor wafer100into individual semiconductor die104. In one embodiment, semiconductor wafer100has a width or diameter of 100-450 millimeters (mm). Alternatively, wafer100can be a mold surface, organic or inorganic substrate, or target substrate suitable for graphene transfer.

FIG.1Bshows a cross-sectional view of a portion of semiconductor wafer100. Each semiconductor die104has a back or non-active surface108and an active surface110containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface110to implement analog circuits or digital circuits, such as digital signal processor (DSP), application specific integrated circuits (ASIC), memory, or other signal processing circuit. Semiconductor die104may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

An electrically conductive layer112is formed over active surface110using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer112can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer112operates as contact pads electrically connected to the circuits on active surface110.

An electrically conductive bump material is deposited over conductive layer112using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer112using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps114. In one embodiment, bump114is formed over an under bump metallization (UBM) having a wetting layer, barrier layer, and adhesive layer. Bump114can also be compression bonded or thermocompression bonded to conductive layer112. Bump114represents one type of interconnect structure that can be formed over conductive layer112. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

FIGS.2a-2gillustrate a process of forming an SiP module with graphene with the TIM over electrical component for thermal dissipation.FIG.2ashows a cross-sectional view of multi-layered interconnect substrate120including conductive layers122and insulating layer124. Conductive layer122can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layers can be formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer122provides horizontal electrical interconnect across substrate120and vertical electrical interconnect between top surface126and bottom surface128of substrate120. Portions of conductive layer122can be electrically common or electrically isolated depending on the design and function of semiconductor die104and other electrical components. Insulating layer124contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), and other material having similar insulating and structural properties. Insulating layers can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. Insulating layer124provides isolation between conductive layers122.

InFIG.2b, electrical components130a-130care disposed on surface126of interconnect substrate120and electrically and mechanically connected to conductive layers122. Electrical components130a-130care positioned over substrate120using a pick and place operation. For example, electrical components130aand130bcan be discrete electrical devices, or IPDs, such as a diode, transistor, resistor, capacitor, and inductor. Electrical component130ccan be semiconductor die104fromFIG.1cwith bumps114oriented toward surface126of substrate120. Alternatively, electrical components130a-130ccan include other semiconductor die, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPD).FIG.2cillustrates electrical components130a-130celectrically and mechanically connected to conductive layers122of substrate120. Conductive paste or solder136provides electrical and mechanical connection to terminals132and134of electrical components130aand130b, respectively. Bumps114provide electrical and mechanical connection for electrical component130c.

InFIG.2d, TIM140is deposited over surface108of electrical component130c. Alternatively, metal coating141is first deposited over surface108of electrical component130c, depending on the type of TIM. Metal coating141can be Ti, Ag, or SUS/Cu. TIM140is deposited over metal coating141. In one embodiment, TIM140is printed on surface108of electrical component130cusing a 3D printer.FIG.3aillustrates electrical component130cdisposed on printer bed142. Printer bed142is heated to 80-100° C. TIM140is dispensed from printer nozzle144onto surface108of electrical component130c. Printer bed142moves three dimensionally (x, y, z directions) to control distribution of TIM140on surface108.

FIG.3billustrates further detail of TIM140including a plurality of cores150surrounded or covered by graphene152embedded in matrix154. In one embodiment, matrix154is a thermoset material, such epoxy resin or adhesive with filler containing alumina, Al, aluminum zinc oxide, or other material having good heat transfer properties. Matrix154can be thermal grease such as silicon or polymer type such as polymethyl methacrylate (PMMA) or polyethylene terephthalate (PET).FIG.3cillustrates core150. In one embodiment, core150is Cu, Ni, phase change material (PCM), or other suitable metal or similar material.

FIG.3dillustrates graphene coating152formed around surface151of metal core150.FIG.3eillustrates further detail of graphene coating152formed as a mesh network around surface151of metal core150, collectively graphene Cu core156. Graphene152is an allotrope of carbon with one or more layers of carbon atoms each arranged in a two-dimensional (2D) honeycomb lattice. Graphene152can be formed by CVD. Metal core150is placed in a chamber heated to 900-1080° C. A gas mixture of CH4/H2/Ar is introduced into the chamber to initiate a CVD reaction. The carbon source decomposes in the high-temperature reaction chamber as the CVD reaction separates the carbon atoms from the hydrogen atoms, leaving graphene152on surface151of metal core150. The release of carbon atoms over metal core150forms continuous sheet of graphene152. Additional information related to forming graphene by CVD is disclosed in U.S. Pat. No. 8,535,553, and hereby incorporated by reference.

In another embodiment, matrix154is a polymer with dispersed graphene, carbon nanotubes, conductive polymers, and the like. Core150is PCM capable of phase change from solid to liquid phase or from liquid phase to solid phase within the operating temperature range of the semiconductor chip, e.g., 20-200° C. A first coating152is formed around PCM core150, and a second coating153is formed between the first coasting152and PCM core150, as shown inFIG.3dand discussed in published Korean application KR101465616B1. Second coating153is a polymer intermediate layer. Matrix154with graphene covered core is further disclosed in U.S. patent Ser. No. 10/421,123, and hereby incorporated by reference. Matrix154with graphene covered core offers high thermal transfer.

The properties of graphene are summarized in Table 1, as follows:

Graphene152exhibits high thermal conductivity. A plurality of graphene Cu cores156physically interconnects within thermoset material154, as shown inFIG.3b, to create a thermal path158between surface160and surface162of TIM140. Heat from electrical component130cis dissipated from surface108and surface160through thermal path158by way of connecting graphene Cu cores156to surface162.

InFIG.2e, heat sink or heat spreader170is disposed over electrical components130a-130c, including TIM140deposited over electrical component130c. Heat sink170can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable thermally conductive material.FIG.2fillustrates heat sink170mounted to substrate120with paste172and cure. Heat sink170dissipates heat generated by electrical components130a-130c, as transferred through graphene Cu core156and TIM140to the heat sink. Heat sink170may include extensions or tabs174extending vertical or perpendicular with respect to surface176of the heat sink, as inFIG.2g. Extensions174provide additional surface area for heat dissipation.

FIG.4aillustrates further detail within region180fromFIG.2fwith TIM140deposited over electrical component130cand heat sink170disposed over the TIM. TIM140including a plurality of metal cores150surrounded by graphene152embedded in thermoset material154, seeFIGS.3a-3d. A plurality of graphene Cu cores156physically connects within thermoset material154to create a thermal path158including portions of interconnected graphene152on adjacent metal cores150disposed and extending between surface160and surface162of TIM140. Heat from electrical component130cis dissipated from surface108and surface160through thermal path158by way of connecting graphene Cu cores156to surface162.

FIG.4billustrates another embodiment within region180with TIM140deposited over electrical component130cand heat sink170disposed over the TIM. TIM140including a plurality of metal cores150surrounded by graphene152embedded in soldering type matrix182. Soldering type matrix182can be indium (In) or InAg with a high thermal conductivity. In this case, metal coating141is formed over surface108of electrical component130c, and soldering type matrix182is deposited over metal coating141. A plurality of graphene Cu cores156physically connects within soldering type matrix182to create a thermal path184including portions of interconnected graphene152on adjacent metal cores150disposed and extending between surface186and surface188of TIM140. Heat from electrical component130cis dissipated from surface108and surface186through thermal path184by way of connecting graphene Cu cores156to surface188.

The combination of interconnect substrate120, electrical components130a-130c, TIM144with graphene Cu core156, and heat sink170constitute SiP200. Graphene Cu core156aids with the heat transfer capability of SiP200, particularly between electrical components130a-130c, known to generate heat, and heat sink150, useful to dissipate heat. Graphene152has a low moisture permeability and a high thermal conductivity of 4000-5000 W m−1K−1, 10 times higher than Cu at room temperature. Since carbon also has a good solderability and wettability of solder paste, TIM140and heat sink170can be readily attached. Graphene152exhibits a high degree of flexibility and remains stable against warpage. Graphene152reduces or prevents oxidation. TIM140with graphene Cu core156improves thermal conductivity, while lowering manufacturing cost.

FIG.5illustrates electrical device400having a chip carrier substrate or PCB402with a plurality of semiconductor packages disposed on a surface of PCB402, including SiP200. Electrical device400can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application.

Electrical device400can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electrical device400can be a subcomponent of a larger system. For example, electrical device400can be part of a tablet, cellular phone, digital camera, communication system, or other electrical device. Alternatively, electrical device400can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, ASIC, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the products to be accepted by the market. The distance between semiconductor devices may be decreased to achieve higher density.

InFIG.5, PCB402provides a general substrate for structural support and electrical interconnect of the semiconductor packages disposed on the PCB. Conductive signal traces404are formed over a surface or within layers of PCB402using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces404provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces404also provide power and ground connections to each of the semiconductor packages.

In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically disposed directly on the PCB. For the purpose of illustration, several types of first level packaging, including bond wire package406and flipchip408, are shown on PCB402. Additionally, several types of second level packaging, including ball grid array (BGA)410, bump chip carrier (BCC)412, land grid array (LGA)416, multi-chip module (MCM) or SIP module418, quad flat non-leaded package (QFN)420, quad flat package422, embedded wafer level ball grid array (eWLB)424, and wafer level chip scale package (WLCSP)426are shown disposed on PCB402. In one embodiment, eWLB424is a fan-out wafer level package (Fo-WLP) and WLCSP426is a fan-in wafer level package (Fi-WLP). Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electrical components, can be connected to PCB402. In some embodiments, electrical device400includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electrical devices and systems. Because the semiconductor packages include sophisticated functionality, electrical devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.