A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

TECHNICAL FIELD

Embodiments of the invention relate to power management in a processor.

BACKGROUND

A modern processor includes both logic circuitry and memory cell arrays. During operation, the voltage supplied to the processor may be dynamically adapted to its workload requirements. For example, a processor may operate according to Dynamic Voltage Frequency Scaling (DVFS) to achieve significant power savings. However, memory cell arrays are much more sensitive to voltage changes than logic gates. As the transistor threshold voltage variation increases, the memory cell arrays begin to suffer more failures.

A dual power rail architecture separates the memory cell voltage from the logic voltage. This separation allows the memory cells to have a stable voltage within a safe voltage range for nominal static noise margin. The logic voltage may be significantly lowered for dynamic power savings. When dual power rails are implemented, the processor designer has the ability to reduce the power supply significantly in the logic gates while maintaining a safe voltage supply for the memory cell arrays.

To ensure the proper operation of the memory cell array, an operating requirement is that the voltage (Vmem) of the memory cell array should not be lower than the voltage of the logic circuitry (Vlogic). In other words, the operating requirement is: Vmem≧Vlogic. At high voltage operations, Vlogicmay experience non-negligible ripples, making it difficult to meet the operating requirement.

SUMMARY

In one embodiment, a processing device is provided for dual-rail power equalization. The processing device includes a memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

In another embodiment, a method is provided for dual-rail power equalization in a computing system that includes a memory cell array and logic circuitry. The method comprises disabling a power switch for the memory cell array to receive a first voltage level supplied by a first power rail and for logic circuitry to receive a second voltage level supplied by a second power rail, wherein the first voltage level is different from the second voltage level. The method further comprises enabling the power switch to equalize voltage supplied to the memory cell array and the logic circuitry.

DETAILED DESCRIPTION

Embodiments of the invention provide a system and method for equalizing the voltages received by a memory cell array and logic circuitry in a processing device that includes dual power rails. Examples of the processing device include, but are not limited to, a central processing unit (CPU), a core, a graphics processing unit (GPU), a digital processing processor (DSP), etc. In one embodiment, the processing device may be part of a mobile computing and/or communication device (e.g., a smartphone, a tablet, laptop, etc.). In another embodiment, the processing device may be part of a cloud computing system. An example of the memory cell array is a cache memory, such as a synchronous RAM (SRAM) or other volatile or non-volatile on-processor memory. The logic circuitry may be the logic gates in an Arithmetic Logic Unit (ALU), in the peripheral controller or I/O controller of a memory cell array, or in other parts of a processing device.

Typically, the voltage of logic circuitry (Vlogic) fluctuates especially at high voltage level, while the voltage of memory cell arrays (Vmem) stays at a constant or near constant level. To satisfy the operating requirement of Vmem≧Vlogic, the processing device may selectively operate in a dual-rail mode or a single-rail mode. In one embodiment, when the operating voltage level of Vlogicis greater than or equal to a predetermined threshold, the processing device operates the memory cell array and the logic circuitry in a single-rail mode. When Vlogicis less than a predetermined threshold, the processing device operates the memory cell array and the logic circuitry in a dual-rail mode. In the dual-rail mode, the memory cell array receives Vmem(also referred to as the memory cell voltage or the first voltage) from a first power rail (i.e., memory power rail), and the logic circuitry receives Vlogic(also referred to as the logic voltage or the second voltage) from a second power rail (i.e., logic power rail). In the single-rail mode, both the memory cell array and the logic circuitry receives the same voltage. Typically, the logic power rail is capable of supplying power at a much higher level than the memory power rail. Thus, in one embodiment (such as the second embodiment shown inFIG. 2), the same voltage in the single-rail mode is Vlogicsupplied from the logic power rail.

FIG. 1andFIG. 2illustrate how the selective switching between the dual-rail mode and single-rail mode may be achieved with a power switch.

FIG. 1illustrates a processing device100including a memory cell array110and logic circuitry120according to a first embodiment. The memory cell array110is connected to a memory power rail113via a first switch115, and the logic circuitry120is connected to a logic power rail123via a second switch125. Both the first switch115and the second switch125may be semiconductor-based switches, such as metal-oxide-semiconductor field-effect transistors (MOSFET), field-effect transistors (FET), or other types of switches. In the embodiment shown inFIG. 1, both the first switch115and the second switch125are P-channel FET (PFET) switches, with their source terminals connected to the respective power rails. The processing device100also includes a power switch150, which may also be a PFET switch or another type of switch. In this embodiment, the power switch150connects the source terminals of the first switch115and the second switch125. That is, the power switch150connects the logic power rail123to the memory power rail113via the power switch150. When the power switch150is turned on, it equalizes the voltage received by the memory cell array110and the logic circuitry120.

In one embodiment, the power switch150is a PFET switch controlled by a signal DREQ_B, which is the inverse of DREQ. The power switch150is turned on when DREQ is enabled (i.e., DREQ_B becomes low). That is, the processing device100operates in the single-rail mode when DREQ is enabled. On the other hand, the power switch150is turned off when DREQ is disabled (i.e., DREQ_B becomes high). That is, the processing device100operates in the dual-rail mode when DREQ is enabled.

In one embodiment, the first switch115and the second switch125are also connected to a sleep signal and/or power down signal. For simplicity of the explanation, the term “sleep signal” is used hereinafter to represent any control signal that cuts off the power supply to the memory cell array110and the logic circuitry210. When the sleep signal is enabled, the first switch115and the second switch125are both turned off. In addition, DREQ is disabled to turn off the power switch150. When the sleep signal is disabled, the first switch115and the second switch125are both turned on, and DREQ controls the on/off of the power switch150. Table I below lists different combinations of sleep signal and DREQ, as well as the resulting voltage(s) received by the memory cell array110and the logic circuitry210. In Table I, Veq=Vlogic.

FIG. 2illustrates a processing device200that also includes the memory cell array110and the logic circuitry120according to a second embodiment. Similar to the first embodiment ofFIG. 1, the memory cell array110is connected to the memory power rail113via the first switch115, and the logic circuitry120is connected to the logic power rail123via the second switch125. In contrast to the first embodiment, the memory cell array110in the second embodiment is also connected to the logic power rail123via the power switch150. When the sleep signal is disabled, the power switch150and the first switch115are controlled by complementary signals; e.g., DREQ_B and DREQ, respectively. In an embodiment, the first switch115, the second switch125and the power switch150are P-type switches such as PFETs. Thus, when DREQ is enabled (i.e., DREQ goes high and DREQ_B goes low), the power switch150is turned on and the first switch115is turned off, resulting in the memory cell array110connected to the logic power rail123. That is, when DREQ is enabled, both the memory cell array110and the logic circuitry120receive the same voltage from the logic power rail123, and the processing device200operates in the single-rail mode. When DREQ is disabled (i.e., DREQ goes low and DREQ_B goes high), the power switch150is turned off and the first switch115is turned on, resulting in the memory cell array110connected to the memory power rail113. That is, the processing device100operates in the dual-rail mode when DREQ is disabled.

In one embodiment, the first switch115, the second switch125and the power switch150are also connected to a sleep signal. When the sleep signal is enabled, all of the three switches (the first switch115, the second switch125and the power switch150) are turned off. Table II below lists different combinations of sleep signal and DREQ, as well as the resulting voltage(s) received by the memory cell array110and the logic circuitry210.

In an alternative embodiment, the sleep signal and the DREQ values may be stored in registers. The processing device100or200may read the register values and set the switches accordingly.

FIG. 3is a flow diagram illustrating a method300for dual-rail power equalization according to one embodiment. The dual-rail power equalization can be achieved by controlling a power switch, such as the power switch150ofFIG. 1orFIG. 2. The power switch may be disabled for a memory cell array to receive a first voltage level supplied by a first power rail and for logic circuitry to receive a second voltage level supplied by a second power rail (step310). The first voltage level is different from the second voltage level; e.g., the first voltage level may be Vmemand the second voltage level may be Vlogic, as described in connection withFIGS. 1 and 2. The power switch can be enabled to equalize voltage supplied to the memory cell array and the logic circuitry (step320). The steps310and320may be performed in any order.

In one embodiment, the method300may be performed by a power control unit that generates the control signals such as DREQ or DREQ_B, or updates the register that stores DREQ or DREQ_B. The power control unit may be inside or outside the processing device100or200. In one embodiment, the power control unit may enable or disable the DREQ or DREQ_B based on whether the present operating voltage level of Vlogicexceeds a predetermined threshold voltage.

FIG. 4Ais a diagram illustrating voltage levels for dual-rail mode according to one embodiment. The flat dotted line represents Vmemand the curved line represents Vlogic. In this diagram, Vlogicoperates in a low voltage region (below a predetermined threshold voltage). Even though Vlogicfluctuates, it stays below Vmemas required by the operating requirement of Vmem≧Vlogic.FIG. 4Bis a diagram illustrating voltage levels for single-rail mode according to one embodiment. In this diagram, Vlogicoperates in a high voltage region (above a predetermined threshold voltage). To satisfy the operating requirement, voltage levels of Vmemand Vlogicare equalized; that is, the difference between Vmemand Vlogicis zero or near zero. The fluctuation in the equalized voltage generally remains within a tolerance and does not cause any problem. In the single-rail mode shown herein, the switches are configured to source power from Vlogic. This is because the Vlogiclevel is typically much higher in the dual-rail mode, and, therefore, the power supply on Vlogicis more capable of handling the additional load.

FIG. 5is a block diagram illustrating a computing system500according to one embodiment. The computing system500includes one or more processors510(also referred to as central processing units (CPUs)), and each processor includes one or more cores511. The computing system500may be part of a mobile device or a host computer. The processors510may form one or more clusters. In one embodiment, each core511includes a processing device100ofFIG. 1or the processing device200ofFIG. 2. The processing device100or200may be the core511itself, a cache memory (including memory cell arrays and associated control logic circuitry) within the core511, or other logic and memory components.

The processors510may access a system memory530(e.g., dynamic random-access memory (DRAM)) via an interconnect520. The computing system500further includes a network interface550for accessing a network560. The computing system500may also include peripheral devices such as a display, a camera, a modem, etc., and/or other devices not shown inFIG. 5.

In one embodiment, the computing system500also includes a power control unit540to detect the operating voltage of Vlogicand control the switching between the dual-rail mode and single-rail mode. The power control unit540may, alternatively, be inside each core511, outside the cores511but within each processor510, or elsewhere in the computing system500. In another embodiment, the computing system500may also include one or more GPUs, DSPs or other types of processors, which include a processing device100ofFIG. 1or the processing device200ofFIG. 2to perform the dual-rail power equalizer operations as described inFIG. 3. The processing device100or200performs the dual-rail power equalization as described inFIG. 3according to the directions of the power control unit540.

The operations of the flow diagram ofFIG. 3have been described with reference to the exemplary embodiments ofFIGS. 1, 2 and 5. However, it should be understood that the operations of the flow diagram ofFIG. 3can be performed by embodiments of the invention other than those discussed with reference toFIGS. 1, 2 and 5, and the embodiments discussed with reference toFIGS. 1, 2 and 5can perform operations different than those discussed with reference to the flow diagram. While the flow diagram ofFIG. 3shows a particular order of operations performed by certain embodiments of the invention, it should be understood that such order is exemplary (e.g., alternative embodiments may perform the operations in a different order, combine certain operations, overlap certain operations, etc.).

To sum up, the invention discloses a processing device comprising a memory cell array, logic circuitry and a power switch. The memory cell array couples to a first power rail through a first switch to receive a first voltage level. The logic circuitry couples to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The power switch couples to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

The invention further discloses a method of controlling a power switch in a processing device that includes a memory cell array and logic circuitry, comprising: disabling the power switch for the memory cell array to receive a first voltage level supplied by a first power rail and for the logic circuitry to receive a second voltage level supplied by a second power rail, wherein the first voltage level is different from the second voltage level; and enabling the power switch to equalize voltage supplied to the memory cell array and the logic circuitry.