On-chip method for measuring access time and data-pin spread

An on-chip I/O timings measurement circuit that improves measurement accuracy compared to conventional external test methods. This circuit guarantees AC timing specifications that are too small for the measurement capabilities of today's high-frequency memory testers. This system in incorporated into the SRAM via the JTAG interface and a JTAG private instruction. A private instruction refers to an unused instruction from the industry-standard public instruction set. Private instructions are usually reserved for the manufacturer, but may be provided to the user as an enhancement to the standard JTAG instruction set.

BACKGROUND OF THE INVENTION
 This invention generally relates to measuring timing characteristics of
 SRAM chips; and more specifically, the invention relates to timing
 measurements of data-pins spread and access times for such chips.
 Traditionally, at-speed component test has guaranteed all AC timing
 specifications for SRAMs. The performance of high-speed SRAMs is presently
 limited, however, by tester accuracy in the measurement of input/output
 (I/O) timings. Specifically, access-time measurements, I/O pin-to-pin skew
 measurements, and echo-clock-to-data tracking measurements may only be
 externally determined to an accuracy of +/-200 ps or more. This external
 limitation can result in high-performance components becoming
 unnecessarily downgraded to lower performance applications. This
 downgrading results in a substantial reduction in high-performance
 applications and in a substantial reduction in high-performance product
 yield. In addition, the need for ever-increasing tester accuracy causes
 high test-equipment and manufacturing test costs.
 For example, a device being tested for an access time of 1.5 ns will be
 subject to two external test constraints. First, the tester guardband is
 subtracted from the access-time strobe. For a typical high-speed tester,
 this guardband is 200 ps. Second, the access-time measurement is
 referenced to the worst-case (i.e., slowest) I/O of the chip. A 200 ps
 tester-induced pin-to-pin I/O spread results in an additional access time
 penalty because the access strobe must capture the slowest pin of the
 spread. In contrast to this wide spread induced by the tester, the
 pin-to-pin spread intrinsic to the SRAM can be as narrow as 30 ps for a
 well-matched design. A combined tester-imposed penalty of 300 ps from
 these two constraints requires that a device have an intrinsic access time
 of approximately 1.2 ns to meet a 1.5 ns specification at test. The same
 constraints apply for measurements of echo-clock to data tracking.
 SUMMARY OF THE INVENTION
 An object of this invention is to improve methods for measuring timing
 characteristics of SRAM chips.
 Another object of this invention is to provide an on-chip method for
 measuring access time and data-pins spread of SRAMs.
 These and other objectives are attained with a method and system for timing
 characteristics of an SRAM chip. The method comprises the steps of loading
 instructions onto the chip to activate sampling of data output, and
 detecting data output transitions. The method further comprises the steps
 of providing the chip with a test clock having a given state transition,
 and sweeping the test clock across detected data output transitions to
 identify timing characteristics of the circuit. Preferably this test clock
 is the JTAG clock.
 The present invention may be used to measure either, or both, the data pins
 spread or access time of an SRAM. To do this, sweeping of the test pattern
 continues from the slowest data output transition detection to the fastest
 data output transition detection and proceeds until a given transition is
 detected on the SRAM clock. The difference in timing from the sampling of
 the slowest data output transition to the sampling of the fastest data
 output transition yields the data output pin-to-pin spread. The difference
 in timing from the,sampling of the slowest data output transition to the
 sampling of the transition of the SRAM clock yields the access time.
 Guaranteeing critical AC timing specifications by design-assisted test, in
 accordance with the present invention, overcomes external tester
 measurement accuracy limitations. Design-assisted test is desirable
 because on-chip measurement circuitry provides an improvement in
 measurement accuracy over conventional external test methods. The
 preferred embodiments of the on-chip circuit techniques herein described
 measure SRAM access time with an accuracy of +/-30 ps and compare I/O-data
 to echo-clock timings with an accuracy of +/-10 ps.
 Further benefits and advantages of the invention will become apparent from
 a consideration of the following detailed description, given with
 reference to the accompanying drawings, which specify and show preferred
 embodiments of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
 The present invention, generally, relates to an on-chip I/O timing circuit
 that improves measurement accuracy compared to conventional external test
 methods. This circuit may be used to guarantee AC timing specifications
 that are too small for the measurement capabilities of today's
 high-frequency memory testers. The system is incorporated into an SRAM via
 the JTAG interface and a JTAG private instruction. A private instruction
 refers to an unused instruction from the industry-standard public
 instruction set. Private instructions are usually reserved for the
 manufacturer, but may be provided to the user as an enhancement to the
 standard JTAG instruction set. Table 1 of FIG. 1 shows the JTAG SRAM
 instruction set implemented by most SRAM manufacturers. Private
 instruction 011 activates the on-chip access measurement system. the JTAG
 private instruction PINST1 activates the I/O-timing measurement circuit.
 The JTAG clock (TCK) is then swept across one entire SRAM cycle at the
 minimum possible tester increment (10 ps or less). TCK captures the
 transitions of data output (DQ), chip-clock, and echo-clock (CQ) pins for
 each cycle. The waveform diagram in FIG. 2 shows the sweeping of TCK
 across `0` to `1` DQ transitions and the corresponding `0` to `1` SRAM
 clock transition that generates the DQ access time. FIGS. 2 and 3
 illustrate only the fastest and slowest DQs out of a group of 36. Because
 the SRAM access time can be pattern-dependent, the patterns that result in
 the slowest access time, widest DQ spread, and greatest DQ-CQ skew must be
 used for each respective measurement. These patterns may be determined
 empirically through extensive use of the I/O-timing measurement circuit
 during product characterization.
 To measure access time and DQ spread, the rising edge of TCK is
 incrementally swept to the left in 10 ps time steps. The first TCK edge
 must occur at a time when the transition of all DQs from `0` to `1` has
 occurred. The sweeping continues from the slowest DQ detection to the
 fastest DQ detection and proceeds until a `0` to `1` transition is
 detected on the SRAM clock. The difference in TCK timing from the sampling
 of the first DQ (slowest) to the sampling of the last DQ (fastest) yields
 the DQ pin-to-pin spread. The difference in TCK timing from the sampling
 of the first DQ (slowest) to the sampling of the clock's `0` to `1`
 transition yields the access time. The waveform diagram of FIG. 3 shows
 the sweeping of `1` to `0` transitions by TCK.
 FIG. 4 shows the on-chip I/O timings measurement circuit 100. The chip
 clock, DQ, and CQ inputs are amplified by identical HSTL receivers and
 connected to the test circuitry through two small buffering stages 102.
 These buffers 102 are designed to minimize loading of the receiver
 circuitry resulting from the test circuitry. Minimizing this load is
 advantageous because the test circuitry is connected in parallel with the
 regular input path. The test buffers drive to registers 104 that are
 sampled by an internal TCK signal (TCKint) upon activation of the private
 instruction PINST1. The register clock network is designed to minimize the
 by-design skew of the clock to all 41 registers. This is accomplished with
 a maximum clock skew of 5 ps.
 After any given TCK sampling of the DQs, CQs or Clock occurs, the
 registered values (ex., RDQ0) are loaded into scan registers (REG) 106 by
 a delayed version of TCKint. PINST1 is then deselected and PINST2 is
 selected to serially shift out the registered values. The JTAG output pin,
 TDO, is monitored to determine the value of the registers. Table 2 of FIG.
 5 shows an example of the test flow that measures a worst-case `0` to `1`
 access time. This test flow may be repeated to measure a `1` to `0` access
 time, DQ pin-to-in spread and CQ-to-DQ tracking skew.
 While it is apparent that the invention herein disclosed is well calculated
 to fulfill the objects stated above, it will be appreciated that numerous
 modifications and embodiments may be devised by those skilled in the art,
 and it is intended that the appended claims cover all modifications and
 embodiments as fall within the true spirit and scope of the present
 invention.