Semiconductor device and forming method thereof

A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nano structures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.

BACKGROUND

Transistors are components of modern integrated circuits. To satisfy the trend of increasingly faster speed, the drive currents of transistors need to be increasingly greater. To achieve this increase in performance, the gate lengths of transistors are scaled down. Scaling down the gate lengths leads to undesirable effects known as “short-channel effects,” in which the control of current flow by the gates is compromised. Among the short-channel effects are the Drain-Induced Barrier Lowering (DIBL) and the degradation of sub-threshold slope, both of which result in the degradation in the performance of transistors.

For example, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device is horizontal gate-all-around (HGAA) transistor, whose gate structure extends around its horizontal channel region providing access to the channel region on all sides or three sides. The HGAA transistors are compatible with complementary metal-oxide-semiconductor (CMOS) processes, allowing them to be aggressively scaled down while maintaining gate control and mitigating SCEs. However, fabrication of the HGAA transistors can be challenging. For example, nanostructure formation of HGAA transistors by the current methods is not satisfactory in all respects, especially when using a single process, such as a single epitaxial process.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In certain embodiments, the term “about” used in this context means greater or less than the stated value or the stated range of values by a percentage such as 5%, 10%, 15%, etc. of the stated values.

Reference is now made toFIGS.1-16, which are exemplary sequential processes for manufacturing the gate-all-around (GAA) FET device according to some embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.1-16, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

Referring toFIG.1, impurity ions (dopants)102are optional implanted into a substrate100to form a well region. The ion implantation is performed to prevent a punch-through effect. In some embodiments, the substrate100may include in its surface region, one or more buffer layers (not shown). The buffer layers can serve to gradually change the lattice constant from that of the substrate to that of the source/drain regions. The substrate100may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity). The dopants102are, for example, phosphorus for a p-type Fin FET.

Referring toFIG.2, stacked semiconductor layers are formed over the substrate100. The stacked semiconductor layers include first semiconductor layers110and second semiconductor layers112. Further, a mask layer120is formed over the stacked layers.

The first semiconductor layers110and the second semiconductor layers112are made of materials having different lattice constants, and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. In some embodiments, the first semiconductor layers110and the second semiconductor layers112are made of Si, a Si compound, SiGe, Ge or a Ge compound. InFIG.2, five layers of the first semiconductor layer110and five layers of the second semiconductor layer112are disposed. However, the number of the layers are not limited to five, and may be as small as 1 (each layer) and in some embodiments, 2-10 layers of each of the first and second semiconductor layers are formed. By adjusting the numbers of the stacked layers, a driving current of the GAA FET device can be adjusted.

The first semiconductor layers110and the second semiconductor layers112are epitaxially formed over the substrate100. In some embodiments, the bottommost first semiconductor layer110(the closest layer to the substrate100) is thicker than the remaining first semiconductor layers110.

In some embodiments, the mask layer120includes a first mask layer122and a second mask layer124. The first mask layer122is a pad oxide layer made of a silicon oxide, which can be formed by a thermal oxidation. The second mask layer124is made of a silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable process. The mask layer120is then patterned into a mask pattern by using patterning operations including photo-lithography and etching. Next, as shown inFIG.3, the stacked layers of the first and second semiconductor layers110,112are patterned by using the patterned mask layer, thereby the stacked layers are formed into fin structures130extending in the X direction. InFIG.3, two fin structures130are arranged in the Y direction. But the number of the fin structures is not limited to, and may be as small as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structures130to improve pattern fidelity in the patterning operations.

Referring toFIG.4, after the fin structures130is formed, an insulating material layer140including one or more layers of insulating material is formed over the substrate so that the fin structures130are fully embedded in the insulating material layer140. The insulating material for the insulating material layer140may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. An anneal operation may be performed after the formation of the insulating material layer140. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and/or an etch-back method, is performed such that the upper surface of the uppermost second semiconductor layer112is exposed from the insulating material layer140. In some embodiments, a first liner layer142is formed over the structure ofFIG.3before forming the insulating material layer140. The first liner layer142is made of SiN or a silicon nitride-based material (e.g., SiON, SiCN or SiOCN).

Then, as shown inFIG.5, the insulating material layer140(as shown inFIG.4) is recessed to form an isolation insulating layer144so that the upper portions of the fin structures130are exposed. With this operation, the fin structures130are electrically insulated from each other by the isolation insulating layer144, which is also referred to as a STI structure. In some embodiments, the insulating material layer140is recessed until the bottommost first semiconductor layer110is exposed. The first semiconductor layers110are sacrificial layers which are subsequently partially removed, and the second semiconductor layers112will serve as channel regions of a GAA FET.

After the isolation insulating layer144is formed, a sacrificial gate dielectric layer150is formed, as shown inFIG.6. The sacrificial gate dielectric layer150includes one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used.

Afterwards, a sacrificial gate layer and a mask layer (e.g., having a pad SiN layer and a silicon oxide mask layer) are formed over the sacrificial gate dielectric layer150, followed by patterning the mask layer, the sacrificial gate electrode layer and the sacrificial gate dielectric layer150into the sacrificial gate structure160, as shown inFIG.7. The sacrificial gate structure160can be referred to as dummy gate structure. The sacrificial gate structure160includes the sacrificial gate dielectric layer150, the sacrificial gate electrode layer164(e.g., poly silicon), the pad SiN layer166and the silicon oxide mask layer168. The stacked layers of the first and second semiconductor layers110,112are partially exposed on opposite sides of the sacrificial gate structure160, thereby defining source/drain (S/D) regions. In this disclosure, a source and a drain are interchangeably used and the structures thereof are substantially the same.

Referring toFIG.8, after the sacrificial gate structure160is formed, a blanket layer170of an insulating material for sidewall spacers is conformally formed by using CVD or other suitable methods. The blanket layer170is deposited in a conformal manner so that it is formed to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, horizontal surfaces, and the top of the sacrificial gate structure. In some embodiments, the blanket layer170is deposited to a thickness in a range from about 2 nm to about 10 nm. In one embodiment, the insulating material of the blanket layer170is a silicon nitride-based material, such as SiN, SiON, SiOCN or SiCN and combinations thereof.

The blanket layer170is then etched using an anisotropic process to form gate sidewall spacers172on opposite sidewalls of the sacrificial gate structure160and fin sidewall spacers174on opposite sidewalls of the fin structures130, followed by etching exposed portions of the fin structures130that extend laterally beyond the gate sidewall spacers172. The resulting structure is illustrated inFIGS.9A and9B, whereinFIG.9Bis the cross sectional view corresponding to line X1-X1ofFIG.9A. InFIG.9B, the cross section of the bottom parts of one sacrificial gate structure160is illustrated. In some embodiments, the anisotropic process can be control such that no fin sidewall spacers174remain on the STI region144.

The anisotropic etching performed on the blanket layer170can be, for example, reactive ion etching (RIE). During the anisotropic etching process, most of the insulating material is removed from horizontal surfaces, leaving the dielectric spacer layer on the vertical surfaces such as the sidewalls of the sacrificial gate structures160and the sidewalls of the exposed fin structures130. The mask layer168may be exposed from the sidewall spacers.

Subsequently, as shown inFIGS.10A and10B, the first semiconductor layers110are horizontally recessed (etched) so that the second semiconductor layers112laterally extend past opposite end surfaces of the first semiconductor layers110. In some embodiments, as shown inFIG.10B, end surfaces of the first semiconductor layers110may be substantially vertically aligned with the side surfaces of the sacrificial gate electrode layer164. Here, “substantially vertically alignment” means the horizontal offset is less than about 1 nm.

During the recess etching of the first semiconductor layers110as illustrated inFIGS.10A and10B, the second semiconductor layers112may be also horizontally etched. The recessed amount of the first semiconductor layers110is greater than the recessed amount of the second semiconductor layers112. In this way, the resulting second semiconductor layers112can laterally extend past opposite end surfaces of the first semiconductor layers110. After recess etching the first semiconductor layers110, the first semiconductor layers110have opposite curved sidewalls. For example, the curved sidewalls are concave sidewalls.

Recess etching the first semiconductor layers110results in byproducts BP attaching to surfaces of the first semiconductor layers110and surfaces of the second semiconductor layers112, as shown inFIG.10B. Byproducts BP may affect the deposition of inner spacer material layer179. Therefore, a cleaning process300is performed to remove the byproducts BP after recess etching the first semiconductor layers110, as shown inFIG.11.

The cleaning process300is performed using an oxygen-containing agent302. In particular, the oxygen-containing agent302is an oxidizing agent which can cause an oxidation reaction converting a material to an oxide. For example, the cleaning process300is performed without using de-oxidation solution such as dilute hydrofluoric (HF) and CERTAS® etch, which tend to remove oxides and without using SiCoNi plasma, which is performed using the process gases including NH3and NF3. For example, the cleaning process300may include wet chemical treatment (e.g., SC1 (standard cleaning solution 1) clean or SC2 (standard cleaning solution 2) clean), ozone (O3) treatment, or oxygen radical-containing treatment.

The SC1 clean follows according to one exemplary embodiment. The SC1 clean includes a mixture of ammonium hydroxide, hydrogen peroxide, and de-ionized water (NH4OH:H2O2:H2O) at a ratio of 1:4:20 at 40° C. to 70° C. for 1 minutes to 10 minutes. The SC2 clean follows according to one exemplary embodiment.

In some embodiments where the cleaning process300is performed using ozone treatment (e.g., a de-ionized ozone treatment), the first semiconductor layers110and the second semiconductor layers112are exposed to ozone. Ozone is a metastable form of oxygen that may be generated in a microwave or UV generator and which readily dissociated into O2and the oxygen radical O*. The ozone may be generated remotely from the substrate100and be flowed over to the substrate100without subjecting the substrate100to plasma.

The de-ionized ozone treatment may be an ozone enhanced low temperature thermal oxidation process carried out within a temperature range of about 0° C. to about 50° C. and at a pressure of about 760 torr. De-ionized ozone concentration may be varied from 10 ppm to 50 ppm.

The oxygen radical-containing treatment includes oxygen (O2) ashing procedure. For example, the oxygen radicals in the oxygen radical-containing treatment is performed at a chamber pressure of 0.5 torr to 10 torr, at RF power of about 2000 Watts to about 4000 Watts, and a standard cubic centimeter per minute (sccm) flow of O2at about 1000 sccm to about 9000 sccm at a second period. The O2ashing procedure generates oxygen radicals in the oxygen ashing step come in contact with the first semiconductor layers110and the second semiconductor layers112and thereby form non-volatile oxide regions.

The cleaning process300using the oxygen-containing agent302causes the oxidation of the outer regions of the first semiconductor layers110and outer regions of the second semiconductor layers112. For example, passivation regions110A are formed in the outer regions of the first semiconductor layers110due to the oxidation. Also, passivation regions112A are formed in the outer regions of the second semiconductor layers112due to the oxidation.

In other words, each of the first semiconductor layers110has an outer region having a composition different from a composition of an inner region of each of the first semiconductor layers110. Each of the second semiconductor layers112has an outer region having a composition different from a composition of an inner region of each of the second semiconductors layers112. The passivation regions110A and112A include oxides. The compositions of the passivation regions110A and112A depend on the materials of the first semiconductor layer110and the second semiconductor layer112. In other words, the passivation regions110A and112A include materials of the first semiconductor layers110and second semiconductor layers112, respectively. For example, in some embodiments where the first semiconductor layers110include silicon germanium, the passivation regions110A may include silicon germanium oxide, silicon oxide, germanium oxide or a combination thereof. In some embodiments where the second semiconductor layers112include silicon, the passivation regions112A may include silicon oxide.

The passivation regions110A and112A can prevent the germanium atoms from diffusing out the first semiconductor layers110during a subsequent process, for example, during forming the inner spacers (seeFIGS.12A and12B), as will be described later in greater detail. Thus the germanium percentage in the first semiconductor layers110is not degraded. One of the passivation regions112A has an L-shaped cross section.

Reference is made toFIGS.12A and12B. After the cleaning process300, an inner spacer material layer (e.g., low k materials)179is deposited. The inner spacer material layer179and the passivation region112A have different compositions. In some embodiments, the inner spacer material layer179includes insulating material such as low-k material. For example, the inner spacer material layer179may include nitrides such as SiCN, SiON, SiCON, SiN or the like. Each of the passivation region112A of the second semiconductor layers112has a surface SF facing another one of the passivation region112A. Each of the passivation region112A of the second semiconductor layers112and the inner spacer material layer179have an interface INF. The inner spacer material layer179is formed as a conformal layer so that vertical portions and horizontal portions of the inner spacer material layer179have similar thicknesses.

Reference is made toFIGS.13A and13B. After depositing the inner spacer material layer179, etching back the inner spacer material layer179by an anisotropic etching process to remove the inner spacer material layer179from the substrate100to form inner spacers180on the first semiconductor layers110and vertically between the corresponding second semiconductor layers112. In particular, the inner spacers180are in contact with the passivation regions110A of the first semiconductor layers110and the passivation regions112A of the second semiconductor layers112. Since the first semiconductor layers110have opposite curved sidewalls, the inner spacers180include curved inner sidewalls. For example, the curved inner sidewalls of the inner spacers180are convex toward the first semiconductor layers110. The passivation regions110A are conformal to the curved inner sidewalls of the inner spacers180.

As mentioned above, the passivation regions110A and the passivation regions112A can help prevent the germanium atoms in the first semiconductor layers110from diffusing out during forming the inner spacers180. If the germanium atoms in the first semiconductor layers110diffuse out, these diffused germanium atoms may accumulate at the interfaces INF and at the surfaces SF which disadvantageously affect the charges at the interfaces INF and the surfaces SF and thus cause fix charge densities at the interfaces INF and the surfaces SF difficult to be controlled.

Reference is made toFIGS.14A and14B. After the inner spacers180are formed, a high temperature (e.g., anneal) process400is performed. The anneal process is conducted at a temperature in a range from 400° C. to 600° C. In some embodiments, the anneal process may be a thermal anneal process such as steam anneal. The anneal time may be in a range from 0.5 hr to 8 hr. The anneal process can tune the fix charge densities at the interfaces INF between the second semiconductor layers112and the inner spacers180. For example, such anneal process can increase the negative charge densities at the interfaces IF and thus help retain the dopants in a subsequently formed source/drain (S/D) epitaxial layers (seeFIG.16) and maintain the low resistance of the S/D epitaxial layers such that the carrier mobility of the S/D epitaxial layers can be enhanced.FIG.14Cillustrates a graph showing the direct current (DC) versus metal gate (MG) dimension. Line1000shows devices with inner spacers undergone a anneal process. Line1002shows devices with inner spacers that did not undergo the anneal process. As compared the line1000with the line1002, it is clear that the anneal process results in an increased direct current flowing through the channel layers (SeeFIGS.19A and19B). As a result, the device performance, such as wafer acceptable test (WAT) performance, can be improved.

In some other embodiments, the high temperature process400is performed prior to etching back the inner spacer material layer179, as shown inFIG.15. In other words, after depositing the inner spacer material layer179, the high temperature process400is performed.

After the inner spacers180are annealed, source/drain (S/D) epitaxial layers190are epitaxially grown from the exposed recessed fins165between the fin sidewall spacers174, as shown inFIG.16. The S/D epitaxial layers190include one or more layers of SiGe doped with p-type dopants (e.g., boron, aluminum, or other suitable p-type dopants) for a p-channel FET. The S/D epitaxial layers190include one or more layers of SiC or SiP doped with n-type dopants (e.g., phosphorous, arsenic, or other suitable n-type dopants) for an n-channel FET. The S/D epitaxial layers190are formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE). In some embodiments, the epitaxial layers190grown from neighboring recessed fins165of the substrate100merge above the STI144and form a void in some embodiments. In some other embodiments, the epitaxial layers190grown from neighboring recessed fins165do not merged.

Subsequently, a second liner layer192is formed and then an interlayer dielectric (ILD) layer194is formed, as shown inFIG.17. The second liner layer192is made of a silicon nitride-based material, such as SiN, and functions as a contact etch stop layer in the subsequent etching operations. The materials for the ILD layer194include compounds comprising Si, O, C and/or H, such as silicon oxide, SiCOH and SiOC. Organic materials, such as polymers, may be used for the ILD layer194.

As shown inFIG.17, after the ILD layer194is formed, a planarization operation, such as CMP, is performed, so that the top portion of the sacrificial gate structure160is exposed.

Next, as shown inFIG.18, the sacrificial gate electrode layer164(seeFIG.9B) and sacrificial gate dielectric layer150(seeFIG.9B) are removed, thereby exposing the fin stack of the first and second semiconductor layers110,112and a gate trench is formed between the gate sidewall spacers172.

The ILD layer194, the second liner layer192, the gate sidewall spacers172, and/or the inner spacers180protect the S/D epitaxial layers190during the removal of the sacrificial gate structures160. The sacrificial gate structures160can be removed using plasma dry etching and/or wet etching. When the sacrificial gate electrode layer164is polysilicon and the ILD layer194is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer164. The sacrificial gate dielectric layer150is thereafter removed using plasma dry etching and/or wet etching.

After the sacrificial gate structures160are removed, the first semiconductor layers110(as shown inFIG.15) in the fin structures are removed, as shown inFIGS.19A and19B. That is, the first semiconductor layers110(seeFIG.18) are etched while the passivation regions110A of the first semiconductor layers110remain on sidewalls of the inner spacers180and vertically between the two neighboring second semiconductor layers112. The passivation regions110A can be referred to as oxide films. The passivation regions110A extend along the curved inner sidewalls of the inner spacers180. As a result, portions of the second semiconductor layers112are suspended. The passivation regions110A have a width (e.g., a horizontal width) less than a width (e.g., a horizontal width) of the inner spacers180. In the following discussion, the portions of the second semiconductor layers112suspended are also referred to as and serve as the channel layers (or nanostructures). The channel layers112are slightly etched or not etched. In the present embodiments, the channel layers112are slightly etched to form a rectangular-like shape (e.g., a nanostructure). The nanostructures may be nanowires, nanosheets, gate all around (GAA) structure or the like.FIG.19Bis the cross sectional view along the fin structure. Gaps115are left between neighboring channel layers112. The first semiconductor layers110can be removed or etched using an etchant that can selectively etch the first semiconductor layers110at a faster etching rate than etching the second semiconductor layers112. The channel layers112extend in the X-direction above the substrate100and are arranged in the Z direction perpendicular to the X-direction. The curved inner sidewalls of the inner spacers80face away from the interface between the S/D epitaxial layers190and the inner spacers180. Each of the passivation regions110A has a curved surface facing away from the curved inner sidewalls of the inner spacers180. In some embodiments where the passivation regions110A are oxide films, the oxide films face away from the curved inner sidewalls.

As discussed above, each of the channel layers112(e.g., nanostructures) has passivation regions112A. In particular, each of the channel layers112has outer regions (e.g., the passivation regions112A) having a composition different from a composition of an inner region of each of the channel layers112(e.g., nanostructures). The inner spacers180are vertically between two neighboring channel layers112. For example, the inner spacers180are vertically between the passivation regions112A of each of the channel layers112. In other words, the passivation regions112A face the inner spacers180. Each of the passivation regions112A has a sidewall portion and a bottom portion connected to the sidewall portion. In some embodiments, at least one of the passivation regions112A has a top portion, a bottom portion and a sidewall portion connected to the top portion and the bottom portion. The bottom portion of each of the passivation regions112A is in contact with a top surface of each of the inner spacers180. One of the channel layers (e.g., nanostructures)112has a silicon-to-oxide interface extending between the passivation region112A and the inner region of the one of the channel layers (e.g., nanostructures)112, and the silicon-to-oxide interface a C-shaped cross section.

In some embodiments, the first semiconductor layers110(also called sacrificial layers to be removed) are SiGe and the second semiconductor layers112(also called channel layers to be left in final GAA transistors) are silicon allowing for the selective removal of the first semiconductor layers110. In some embodiments, the selective wet etching includes an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). In some embodiments, the selective removal includes SiGe oxidation followed by a SiGeOxremoval. For example, the oxidation may be provided by O3clean and then SiGeOxremoved by an etchant such as NH4OH that selectively etches SiGeOxat a faster etch rate than it etches Si. Moreover, because oxidation rate of Si is much lower (sometimes 30 times lower) than oxidation rate of SiGe, the channel layers112may not be significantly etched by the channel release process.

In the present embodiment, since the passivation regions110A and the inner spacers180are made of a material that has etching selectivity to that of the first semiconductor layers110, the passivation regions110A and the inner spacers180can protect the source/drain epitaxial layers190from the etchant used in etching the first semiconductor layers110.

Referring toFIG.20, a metal gate structure200is formed around each channel layers112. The metal gate structure200extends in a Y direction which is perpendicular to the X direction and the Z direction. The exemplary sequential processes of the formation of the metal gate structure200will be discussed in the following figures.

FIGS.21A-25Bare various cross-sectional views of a GAA device at different stages of fabrication, according to some embodiments of the disclosure, in which “A” are the cross sectional views corresponding to line X1-X1ofFIG.20, and “B” are the cross sectional views corresponding to line Y1-Y1ofFIG.20.FIGS.21A and21Bfollow afterFIGS.19A and19B.

After the first semiconductor layers110are removed, interfacial layers206are formed on surface of the channel region, e.g., the surface of the channel layers112, and on the surface of the recessed fins165. The interfacial layers206are formed of silicon oxide or silicon oxynitride grown by a thermal oxidation process. For example, the interfacial layer206can be grown by wet oxidation, a rapid thermal oxidation (RTO) process or by an annealing process using oxygen. In some embodiments where the interfacial layers206are formed by oxidation, all exposed semiconductor surfaces may be oxidized, and thus exposed surfaces of the channel layers112and the recessed fins165are all coated with interfacial layers206.

Referring toFIGS.22A and22B, after the interfacial layers206are formed, a high-k gate dielectric layer208is formed along the gate sidewall spacers172, the surface of the inner spacer180, the surface of the ILD layer194and the interfacial layer206, by a deposition process. In some embodiments, the high-k gate dielectric layer208may include metal oxides. Examples of metal oxides used for high-k gate dielectric layer208include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof. The high-k gate dielectric layer208may be formed using a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) or other suitable method. The passivation regions110A are between the high-k dielectric layer along each of the inner spacers180.

Reference is made toFIGS.23A and23B. A work function layer210is formed on the high-k gate dielectric layer208. For example, the work function layer210is deposited to surround each of the channel layers (or nanostructures)112. A portion of the work function layer210is formed vertically between adjacent channel layers (or nanostructures)112and fills the gap115between adjacent channel layers112. Two of the passivation regions110A are laterally spaced apart by one of the work function layer210.

The work function layer210may be formed to provide a proper work function for the resulting gate structure. For example, if a P-type work function metal (P-metal) for a PMOS device is desired, P-type work function materials may be used. Examples of P-type work function materials include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other applicable materials.

On the other hand, if an N-type work function metal (N-metal) for NMOS devices is desired, N-type metal materials may be used. Examples of N-type work function materials include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and/or other applicable materials.

The work function layer210is a single-layer film or a multi-layer film. In some embodiments where the work function layer210is a multi-layer film, the work function layer may be a stack of one or more N-metal layers and one or more P-metal layers.

Reference is made toFIGS.24A and24B. A glue layer212is formed on and surrounds the work function layer210. The glue layer212may be used to increase adhesion between the work function layer210and a subsequently formed fill metal layer (seeFIGS.25A and25B) so as to prevent the fill metal layer from peeling or delaminating. The glue layer212is a conformal layer and is conformally formed over the work function layer210. In some embodiments, the glue layer212is a nitride layer. In some embodiments, the glue layer212is made of or includes TiN, TaN, TiAlN, TaCN, TaC or TaSiN, other suitable material, or a combination thereof and may be formed by CVD, ALD, PVD and/or other suitable process.

Referring toFIGS.25A and25B, a fill metal layer214is formed within a trench on the glue layer212between the gate sidewall spacers172. The fill metal layer214is deposited over the work function layer210. The fill metal layer214may be a work function layer (i.e., formed of N-metal or P-metal discussed above). In some embodiments, the fill metal layer214includes tungsten. In an embodiment, after the interfacial layers206, the high-k gate dielectric layer208, the work function layer210, the glue layer212and the fill metal layer214are deposited, a CMP process is performed to planarize a top surface of the semiconductor device10. The passivation regions110A are symmetric with respect to the metal gate structure200. The curved inner sidewalls of the inner spacers180are convex toward the gate structure200(seeFIG.20).

Referring toFIG.26, in some other embodiments, after recess etching the first semiconductor layers110′, the first semiconductor layers110′ have opposite flat sidewalls. In this case, the passivation regions110A′ have opposite flat surfaces, as shown inFIG.27. Therefore, the interface between each of the passivation regions110A′ and each of the inner spacers180are flat.

Based on the above discussion, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantages is required for all embodiments. One advantage is that a cleaning process using oxygen-containing agent after recess etching the first semiconductor layers can form the passivation regions in the outer regions of the first semiconductor layers and the second semiconductor layers. Such passivation regions can prevent germanium atoms in the first semiconductor layers from diffusing out during forming the inner spacers. Another advantage is that the fix charge density at the interface between the second semiconductor layer and the inner spacer can be tuned by the anneal process. Yet another advantage is that the dopants can be retained such that low resistance of the S/D epitaxial layers can be maintained.

In some embodiments, a semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nanostructures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer. In some embodiments, the composition of the outer region of each of the nanostructures includes oxide. In some embodiments, the gate structure further includes inner spacers vertically between each of the plurality of the nanostructures and oxide films between each of the inner spacers and each of the plurality of high-k gate dielectric layers. In some embodiments, the oxide films and the outer regions of the nanostructures include silicon oxide. In some embodiments, two of the oxide films are spaced apart by one of the plurality of nanostructures. In some embodiments, the oxide films are symmetric with respect to the gate structure. In some embodiments, one of the outer regions of the nanostructures has an L-shaped cross section. In some embodiments, one of the plurality of nanostructures has a silicon-to-oxide interface extending between the outer region and the inner region of the one of the plurality of nanostructures, and the silicon-to-oxide interface a C-shaped cross section.

In some embodiments, a semiconductor device includes a plurality of nanostructures, a plurality of inner spacers and a gate structure. The plurality of nanostructures extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The plurality of inner spacers are vertically between two of the plurality of nanostructures. The plurality of nanostructures have oxide regions facing the inner spacers. The gate structure extends in a third direction perpendicular to both the first and second directions and surrounds each of the plurality of nanostructures. The gate structure includes a plurality of high-k gate dielectric layers, a work function layer and a fill metal layer. The plurality of high-k gate dielectric layers respectively surrounds the plurality of nanostructures. The work function layer surrounds each of the plurality of high-k gate dielectric layers. The fill metal layer surrounds the work function layer. In some embodiments, the inner spacers and the oxide regions have different compositions. In some embodiments, the oxide regions include silicon oxide and the nanostructures include silicon. In some embodiments, the inner spacers have curved inner sidewalls. In some embodiments, the curved inner sidewalls of the inner spacers are convex toward the gate structure. In some embodiments, the semiconductor device further includes oxide films extending along the curved inner sidewalls of the inner spacers. In some embodiments, the oxide films are conformal to the curved inner sidewalls. In some embodiments, the oxide films have a width less than a width of the inner spacers.

In some embodiments, a method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, horizontally recessing the first semiconductor layers, after recessing the first semiconductor layers, performing a cleaning process using an oxygen-containing agent, after the cleaning process, forming inner spacers on opposite sides of the recessed first semiconductor layers, after forming the inner spacers, removing the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanostructures, forming a work function layer surrounding each of the nanostructures, and depositing a fill metal layer over the work function layer. In some embodiments, the cleaning process is performed such that outer regions of the first semiconductor layers are oxidized. In some embodiments, the cleaning process is performed such that outer regions of the second semiconductor layers are oxidized. In some embodiments, the method further includes annealing the inner spacers.