Offset-compensated switched-opamp integrator and filter

An integrator and a filter having offset compensated switched-opamp are implemented in the present invention. In the present invention, offset voltages caused by amplifiers used in a integrator or a filter can be compensated and such circuits can be operated under a low power voltage.

DETAILED DESCRIPTION OF THE INVENTION 
 Referring to FIG. 2, a preferred embodiment in accordance with the present 
 invention is shown as a non-inverting integrator circuit, including two 
 amplifiers A1 and A2 coupled in series, four capacitors C1, C2, C3, and 
 C4, and four MOS switches 10, 20, 30, and 40. 
 FIG. 3 is a timing diagram illustrating two timing waveforms 01 and 02 
 related to the FIG. 2, wherein the switches 10, 20, and 40 are in response
 to the timing waveform 01 and the switch 30 is in respond to the timing 
 wave form 02. Note that timing waveforms 01 and 02 having the same period 
 show different logic levels at the same time, that is, switches 10, 20, 
 and 40 are on/off while switch 30 is off/on while the non-inverting 
 integrator is operated. 
 When 01 rises to a high logic level, the input capacitor C1 whose initial 
 voltage is Vin(nT-T/2)-Voff1 is discharged to -Voff1, where the voltage 
 Vin is an input voltage and the voltage Voff1 is an offset voltage of the 
 amplifier A1. On the other hand, the capacitor C2 whose initial voltage is
 V1(nT-3T/2)-Voff1 is charged to V1(nT-T/2)-Voff1. Thus, the charge 
 conservation at node A gives: 
EQU C1[-Voff1-Vin(nT-T/2)+Voff1]+C2[V1(nT)-Voff1-(V1(nT-T)-Voff1)]=0 (1) 
EQU Therefore, 
EQU V1(nT-T/2)-V1(nT-3T/2)=(C1/C2)Vin(nT-T) (2) 
 It is obvious that the offset voltage Voff1 in the non-inverting integrator
 circuit of this preferred embodiment is compensated based on the present 
 invention. 
 Furthermore, when 01 rises to a high logic level, the capacitor C3 whose 
 initial voltage is V1(nT-T/2)-Voff2 is discharged to Voff1-Voff2, where 
 the voltage Voff2 is an offset voltage of the amplifier A2. On the other 
 hand, the capacitor C4 is charged from zero voltage to V2(nT)-Voff2. 
 Similarly, the charge conservation at node B gives: 
EQU C3[Voff1-Voff2-V1(nT-T/2)+voff2]+C4[V2(nT)-Voff2]=0 (3) 
 If the capacitance of the capacitor C3 is equal or similar to the 
 capacitance of the capacitor C4, equation (3) can be simplified to 
EQU V2(nT)=V1(nT-T/2)+Voff2-Voff1 (4) 
 And if the offset voltage Voff1 of the amplifier A1 is close to the voltage
 Voff2 of the amplifier A2, the purpose of offset compensation can be also 
 achieved. In addition, because all MOS switches are coupled to a ground 
 terminal or a virtual ground terminal of the amplifiers, the non-inverting
 integrator circuit can be operated under a low supply voltage. 
 FIG. 4 is a circuit diagram illustrating an inverting integrator of another
 preferred embodiment of the present invention. As shown in the figure, the
 inverting integrator comprises two amplifiers A1 and A2 coupled in series,
 four capacitors C1, C2, C3, and C4, and four MOS switches 10, 20, 30, and 
 40 which have same symbols and function as in FIG. 2. In addition, there 
 is a capacitor Ch to store the offset voltage Voff1 of the amplifier A1 
 and a switch 50 in the inverting integrator. 
 Similar to the non-inverting integrator shown in FIG. 2, the timing diagram
 having two timing waveforms 01 and 02 shown in FIG. 3 is applied to the 
 inverting integrator shown in FIG. 4, wherein the switches 10, 30, and 50 
 are in response to the timing waveform 01 and the switches 20 and 40 are 
 in response to the timing waveform 02. Note that timing waveforms 01 and 
 02 having the same period show different logic levels at the same time, 
 that is, switches 10, 30, and 50 are on/off while switch 20 and 40 are 
 off/on while the inverting integrator is operated. 
 By similar analysis as made in the non-inverting integrator, when 02 rises 
 to a high logic level in the inverting integrator in FIG. 3, the charge 
 conservation at node A' gives : 
EQU C1Vin(nT)+C2[v1(nT)-V1(nT-T)]=0 (5) 
EQU Therefore, 
EQU V1(nT)-V1(nT-T)=-(C1/C2)Vin(nT) (6) 
 On the other hand, when 01 rises to a high logic level and the capacitance 
 of the capacitor C3 is equal to the capacitance of the capacitor C4, the 
 charge conservation at node B' gives: 
EQU V2(nT-T/2)=V1(nT-T)+Voff2-Voff1 (7) 
 If the two offset voltages Voff1 and Voff2 of the relative amplifiers A1 
 and A2 are close, the purpose of offset compensation can be also achieved.
 In addition, because all MOS switches are coupled to a ground terminal or 
 a virtual ground terminal of the amplifiers, the inverting integrator 
 circuit can be operated under a low supply voltage. 
 FIG. 5 is a circuit diagram illustrating a low-pass filter of another 
 preferred embodiment of the present invention, which is constituted of 
 portions of the non-inverting and inverting integrator circuits 
 respectively shown in FIG. 2 and FIG. 4. As shown in FIG. 5., the filter 
 circuit can also be operated under a low power voltage. 
 The filter circuit shown in FIG. 5 comprises three amplifiers A1, A2 and A3
 coupled in series, capacitors C1-C8 and Ch, and MOS switches 311-318 and 
 321-326, wherein the capacitors C7 and C8 function equally as feedback 
 resistors. Similar to the circuits shown in FIG. 2 and FIG. 3, the timing 
 diagram shown in FIG. 3 is applied to operate the filter circuit in FIG. 
 5, wherein the switches 311-318 are in response to the timing waveform 01 
 and the switches 321-326 are in response to the timing waveform 02. Note 
 that timing waveforms 01 and 02 having the same period show different 
 logic levels at the same time, that is, switches 311-318 are on/off while 
 switch 321-326 are off/on while the filter is operated. 
 When 01 rises to a high logic level in the filter in FIG. 5, the charge 
 conservation gives: 
EQU V1(nT-T/2)-V1(nT-3T/2)=(C1/C2)Vin(nT-T)+{C8/C2[(Voff1-Voff2)+Vo(nT-T))]}=0 
 (8) 
 If the offset voltages Voff1 and Voff2 are close and compensate each other,
 a z-transformed result of the equation (8) is: 
EQU (z.sup.-1/2 -z.sup.-3/2)V1(z)=(C1/C2)z.sup.-1 Vin(z)+(C8/C2)z.sup.-1 Vo(z) 
 (9) 
 When 02 rises to a high logic level in the filter in FIG. 5, the charge 
 conservation gives: 
EQU V2(z)=(C3/C4)z.sup.-1/2 V1(z)+Voff3-(C3/C4)Voff1 (10) 
 If the offset voltages Voff1 and Voff3 are close and the capacitance of the
 capacitors are equal, then the offset voltages Voff1 and Voff3 are 
 compensated and the equation (10) becomes: 
EQU V2(z)=z.sup.-1/2 V1(z) (11) 
 , wherein the relation between voltages V2 and Vo is: 
EQU Vo(z)(1-z.sup.-1)=-(C5/C6)V2(z)-(C7/C6)Vo(z) (12) 
 By the equations (9), (11), and (12), the z-transform equation of the 
 low-pass filter shown in FIG. 5 can be represented as: 
EQU Vo(z)/Vin(z)=-[(C5C1)/(C6C2)]z.sup.-1 /[1+C7/C6-(C5C8)Z.sup.-1 
 /(C6C2)+Z.sup.-2] (13) 
 In fact, according to the equation (13), the circuit shown in FIG. 5 can 
 function as a low-pass filter while the proper ratios between the 
 capacitance of the capacitors are determined. 
 FIG. 1 is a low-pass filter circuit of the prior art, which comprises three
 amplifiers coupled in series A11, A12, and A13, capacitors C1-C8, and 
 switches 110-116 and 120-124, wherein there are two timing waveforms 
 having the same period show different logic levels at the same time to 
 operate the capacitors. To compare the low-pass filter in FIG. 5 disclosed
 in the present invention, both low-pass filter both have the same 
 z-transform equation (13), but two drawbacks exist in the low-pass filter 
 in FIG. 1 of the prior art. First, each amplifier needs to be switched. As
 shown in FIG. 1, the amplifiers A1, A2, and A3 are respectively switched 
 by switches 112, 123, and 124. Moreover, the offset voltages from the 
 amplifiers can not be compensated so as to reduce the operation precision 
 of the low-pass filter. 
 Consequently, the disclosed non-inverting and inverting integrator and the 
 low-pass filter of the present invention can not only be operated under a 
 low power voltage, but also compensate the offset voltages created from 
 the amplifiers, so as to increase the operation precision of the circuits.
 While the present invention has been particularly shown and described with 
 reference to a preferred embodiment, it will be readily appreciated by 
 those of ordinary skill in the art that various changes and modifications 
 may be made without departing from the spirit and scope of the invention. 
 It is intended that the claims be interpreted to cover the disclosed 
 embodiment, those alternatives which have been discussed above and all 
 equivalents thereto.