Low pass filter

A low pass filter which comprises first, second and third switched capacitor circuits connected to a power source V.sub.DD and/or a power source V.sub.SS, first and second operational amplifiers driven by the power sources V.sub.DD and V.sub.SS, and a bias circuit connected between the power sources V.sub.DD and V.sub.SS for providing a bias voltage to the non-inverting input terminals of the first and second amplifiers.

Copending U.S. patent application Ser. No. 647,280 to Sasaki, filed Sept. 
5, 1984, is noted for cross-reference purposes. Application Ser. No. 
647,280 is a continuation of U.S. patent application Ser. No. 394,612, 
filed July 2, 1982, and now abandoned. 
BACKGROUND OF THE INVENTION 
The present invention relates to a low pass filter formed of a switch 
capacitor integrator in use for electronic filters, voice recognition 
circuits and voice composing circuits. 
FIGS. 1A and 1B show a basic circuit of a switched capacitor circuit and 
FIG. 2 shows its equivalent circuit. In these figures, a switch S is 
connected at the first stationary contact a to the input terminal 11, and 
at the second stationary contact b to the output terminal 12. A common 
contact c is connected through a capacitor Cs to ground. Potentials Vi and 
Vo with respect to ground potential are applied to the input and output 
terminals, respectively. As shown in FIG. 1A, when the switch S is turned 
to the contact a, the charge Q1 stored in the capacitor Cs is given by 
Q1=Cs.times.Vi. When it is turned to the contact b, as shown in FIG. 1B, 
the charge Q2 stored in the capacitor Cs is expressed by Q2=Cs.times.Vo. 
The switching operation of the switch S from the input terminal 11 to the 
output terminal 12 is equivalent to the movement of .DELTA.Q from the 
input terminal 11 to the output terminal 12. .DELTA.Q is 
EQU .DELTA.Q=Q1-Q2=Cs(Vi-Vo) (1) 
When the switch S is switched f.sub.s times per second, an average current 
i flowing from the input terminal 11 to the output terminal 12 is given 
EQU i=.DELTA.Q.multidot.f.sub.s =Cs(Vi-Vo)f.sub.s ( 2) 
If the switching frequency f.sub.s of the switch S is sufficiently larger 
than the frequencies of the voltages Vi and Vo, the current i is equal to 
the current determined by the instantaneous values of the voltages Vi and 
Vo. Accordingly, the circuit shown in FIGS. 1A and 1B is equivalent to a 
circuit with a resistor connected between the input and output terminals 
11 and 12. Here, the resistor R is given 
##EQU1## 
As described above, in the switched capacitor circuit, the capacitor Cs 
connected at one end to the reference potential is switched at the other 
end between two different potential terminals. Equivalently, the resistor 
R is connected between the two potential terminals. The switched capacitor 
is the integrator formed by using the switched capacitor unit. 
FIG. 3 shows a mirror integrator formed using the operational amplifier 31 
and its input vs. output characteristic is mathematically expressed by the 
following equation 
##EQU2## 
where Vi is an input voltage, Vo an output voltage and Rs a resistance of 
an input resistor between the input terminal 11 and the inverting input 
terminal (-) of the amplifier 31, Cf a capacitance of a feedback capacitor 
connected between the output terminal and the inverting input terminal (-) 
of the amplifier 31, and S is the Laplacian. 
In FIG. 3, V.sub.DD and V.sub.SS are power sources, and the non-inverting 
input terminal (+) of the amplifier 31 is connected to ground. 
FIG. 4 shows a mirror integrator formed using the switched capacitor 
circuit 41 in place of the resistor Rs in the circuit shown in FIG. 3. The 
input vs. output characteristic of the circuit 41 is such that the R in 
the equation (3) is substituted into the Rs in the equation (4), and is 
given 
##EQU3## 
As seen from the equation (5), the input vs. output characteristic of the 
mirror integrator is a linear function of a capacitance ratio of the 
capacitances Cs and Cf, and the switching frequency f.sub.s of the switch 
S. This indicates that the integration time constant may be changed 
proportional to the frequency f.sub.s, and that the filter formed using 
the mirror integrator shown in FIG. 4 can switch the filtering frequency 
proportional to the switching frequency f.sub.s. 
FIGS. 5A, 5B, 6A and 6B show mirror integrators equivalent to the mirror 
integrator shown in FIG. 4. In the mirror integrators shown in these 
figures, switched capacitor circuits 50 and 60 are each provided with two 
switches S1 and S2. Both ends of the capacitor Cs can simultaneously be 
switched by the switches S1 and S2. The first stationary contact a1 of the 
switch S1 is connected to the input terminal 11; the second stationary 
contact b1 to ground; the common contact to one end of the capacitor Cs. 
The first stationary contact a2 of the switch S2 is connected to the 
inverting input terminal (-) of the amplifier 31; the second stationary 
contact b2 to ground; the common contact to the other terminal of the 
capacitor Cs. Incidentally, in the mirror integrators, the switched 
capacitor circuit is used for the resistor with a positive resistance. 
When the switches S1 and S2 are turned to the stationary contacts b1 and 
b2, respectively, as shown in FIG. 5A, the charge of the capacitor Cs is 
discharged to zero. As shown in FIG. 5B, when the switches S1 and S2 are 
connected to the stationary contacts a1 and a2, respectively, as shown in 
FIG. 5B, the charge Q given by the following equation is stored in the 
capacitor Cs. 
EQU Q=Cs(Vi-Vi') (6) 
where Vi is a voltage applied to the terminal 11 and Vi' is a voltage 
applied to the inverting input terminal (-) of the amplifier 31. 
The average current i of the capacitor Cs is given by 
EQU i=Cs(Vi-Vi')f.sub.s ( 7) 
where f.sub.s is the switching frequency of the switches S1 and S2. 
Further, the equivalent resistance R between the stationary contacts a1 
and a2 is 
##EQU4## 
The equation (8) is the same as the equation (3). The switched capacitor 
circuit 50 shown in FIGS. 5A and 5B is equivalent to the switched 
capacitor circuit 41 shown in FIG. 4. In the mirror integrators shown in 
FIGS. 6A and 6B, the switched capacitor circuit is used as a resistor with 
a negative resistance. 
As shown in FIG. 6A, when the switches S1 and S2 are turned to the first 
and second contacts a1 and b2, respectively, the charge Q given by the 
following equation is charged into the capacitor Cs. 
EQU Q=Cs.multidot.Vi (9) 
When the switches S1 and S2 are turned to the second and first stationary 
contacts b1 and a2, respectively, as shown in FIG. 6B, the charge Q stored 
in the capacitor Cs and given by the equation (9) is supplied to the 
inverting input terminal (-) of the amplifier 31. Therefore, if the 
switching frequencies f.sub.s of the switches S1 and S2 is sufficiently 
larger than that of the voltages Vi and Vi', an equivalent resistance 
circuit given by R=1/(Cs.times.f.sub.s) is formed. 
A low pass filter formed using the mirror integrator with the switched 
capacitor circuit is shown in FIG. 7. The input signal Vi supplied to the 
input terminal 71 is applied through the switched capacitor circuit 72 
serving as a positive resistor to the inverting input terminal (-) of the 
first operational amplifier 31.sub.1. The amplifier 31.sub.1 is connected 
to the two power source voltages V.sub.DD and V.sub.SS, and its output 
terminal is connected to a switched capacitor circuit 73 at the next stage 
serving as a negative resistor, and through the first feedback capacitor 
Cf1 to the inverting input terminal (-). Ground potential as a reference 
potential is coupled with the non-inverting input terminal (+) of the 
amplifier 31.sub.1. The output signal Va of the amplifier 31.sub.1 is 
applied through the switched capacitor circuit 73 to the inverting input 
terminal (-) of the second operational amplifier 31.sub.2. Two power 
source voltages V.sub.DD and V.sub.SS are applied to the amplifier 
31.sub.2. The output terminal of the amplifier 31.sub.2 is connected to 
the output terminal 75 of the device (low pass filter) and through the 
second feedback capacitor Cf2 to the inverting input terminal (-). Ground 
potential as the reference voltage is applied to the non-inverting input 
terminal (+) of the amplifier 31.sub.2. Further, the output terminal of 
the amplifier 31.sub.2 is connected to the inverting input terminal (-) of 
the amplifier 31.sub.1 through a switched capacitor circuit 74 serving as 
a positive resistor and a third capacitor Cs13 connected in parallel with 
the circuit 74. The output signal Vo of the amplifier 31.sub.2 is fed back 
to the inverting input terminal (-) of the amplifier 31.sub.1. 
In operation, the output signal Va of the amplifier 31.sub.1 is given by 
##EQU5## 
where f.sub.s is the number of switchings per second of the switched 
capacitors Cs11 and Cs12, and S is the Laplacian. 
The output signal Vo of the amplifier 31.sub.2 has a positive value since 
the switched capacitor circuit 73 is used as a negative resistor, and is 
given by the following equation 
##EQU6## 
Substituting the equation (10) into the equation (11), we have a transfer 
function H.sub.(s) between the input signal Vi and the output signal Vo as 
given by 
##EQU7## 
The transfer function of the low pass filter is generally given 
##EQU8## 
where G is a gain of the filter, w.sub.c is an angular velocity at -3 dB 
and 2.pi.f.sub.c. 
When a low pass filter of the Butterworth is used for the low pass filter, 
"bo=1" and "b1=.sqroot.2". Further, when comparing the equations (12) and 
(13), we have 
##EQU9## 
From the equations (14), (15) and (16), the following equations (17) and 
(18) are obtained. 
##EQU10## 
Therefore, the low pass filter of the Butterworth type can be formed by 
making the integration constant of the first stage containing the switched 
capacitor circuits 72 and 74 and the amplifier 31 equal to that of the 
second stage containing the switched capacitor circuit 73 and the 
amplifier 31.sub.2, and by setting the capacitance of the capacitor Cs13 
to a value .sqroot.2 times that of the capacitor Cf1. 
As shown in FIGS. 4, 5A, 5B, 6A and 6B, the switched capacitor integrator 
used as the mirror integrator needs a single power source terminal 
connected to the reference power souree Vref (ground) in addition to the 
two power source terminals connected to the two power sources V.sub.DD and 
V.sub.SS. The low pass filter formed using such mirror integrator needs 
three power source terminals. When such low pass filter is fabricated 
together with the ordinary random logic of the type using two power 
sources V.sub.DD and V.sub.SS, a reference power source terminal must 
additionally be used in addition to the two power source terminals. 
The increase of the power source terminals provides a great problem in 
fabricating the integrated circuits in that the circuit is complicated, 
the chip area increases, and the pattern design for the three power 
terminals is complicated. Further, the design of the printed circuit for 
mounting the integrated circuits is complicated, resulting in increase of 
the manufacturing cost. 
SUMMARY OF THE INVENTION 
Accordingly, an object of the present invention is to provide a low pass 
filter which can decrease the number of power source terminals and 
therefore is well adaptable for the integrated circuit. 
According to the present invention, there is provided a low pass filter 
comprising first and second power sources, first operational amplifier 
means driven by the first and second power sources, first feedback 
capacitor means connected between the inverting input terminal of the 
amplifier means and its output terminal, a first switched capacitor 
circuit connected between the signal input terminal applied with the input 
voltage signal and the inverting input terminal of the first amplifier 
means or to the first power source, second operational amplifier means 
connected to the first and second power sources, second feedback capacitor 
means connected between the inverting input terminal of the second 
amplifier means and its output terminal, second switched capacitor circuit 
connected between the output terminal of the first amplifier and the first 
power source or between the inverting input terminal of the second 
amplifier means and the second power source, a third switched capacitor 
circuit connected between the output terminal of the second amplifier 
means and the inverting input terminal or to the first power source, 
parallel connected capacitor means connected in parallel with the third 
capacitor circuit, and a bias circuit connected to the first and second 
power sources and of which a given potential point is connected to the 
non-inverting input terminals of the first and second amplifier means.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring to FIG. 8, there is shown an embodiment of a low pass filter 
according to the present invention. In the figure, an input terminal 71 is 
connected to the inverting input terminal (-) of a first operational 
amplifier 31.sub.1 through a switched capacitor circuit 72 as a positive 
resistor. The input voltage signal Vi is applied to the input terminal 71 
and the signal Vi is applied to the inverting input terminal (-) of the 
amplifier 31.sub.1 through the switched capacitor circuit 72. Two voltages 
V.sub.DD and V.sub.SS are applied as drive sources to the amplifier 
31.sub.1. The output terminal of the amplifier 31.sub.1 is connected to a 
switched capacitor circuit 73 at the next stage serving as a negative 
resistor and through the first feedback capacitor Cf1 to the inverting 
input terminal (-). The non-inverting input terminal (+) of the amplifier 
31.sub.1 is connected to a junction between the resistors R1 and R2 
connected in series between the two power sources V.sub.DD and V.sub.SS 
connected to the amplifier 31.sub.1. The amplifier 31.sub.1 is connected 
at the output terminal to the switched capacitor circuit 73 and through 
the capacitor 73 to the inverting input terminal (-) of the second 
operational amplifier 31.sub.2. Accordingly, the output voltage signal Va 
of the first amplifier 31.sub.1 is applied through the switched capacitor 
circuit 73 to the inverting input terminal (-) of the second amplifier 
31.sub.2. 
The two power sources V.sub.DD and V.sub.SS as drive sources are connected 
to the second amplifier 31.sub.2 of which the output terminal is connected 
to the output terminal of a device, i.e. a low pass filter, and through 
the second feedback capacitor Cf2 to the inverting input terminal (-). The 
non-inverting input terminal (+) of the amplifier 31.sub.2 is connected to 
a junction between two resistors connected in series between the two power 
sources V.sub.DD and V.sub.SS, as in the case of the amplifier 31.sub.1. 
The output terminal of the amplifier 31.sub.2 is connected to the 
inverting input terminal (-) of the amplifier 31.sub.1 through a switched 
capacitor circuit 74 serving as a positive resistor and a third capacitor 
Cs13 connected in parallel with the circuit 74. Accordingly, the output 
signal Vo of the amplifier 31.sub.2 is fed back to the inverting input 
terminal (-) of the amplifier 31.sub.1 through the switched capacitor 
circuit 74 and the capacitor Cs13. 
The switched capacitor circuits 72 to 74 are each formed of a single 
switched capacitor and a single switch. To be more specific, the switched 
capacitor circuit 72 is comprised of a switch capacitor Cs11, a first 
switch S1 which is connected at the first stationary contact a1 to the 
signal input terminal 71, at the second stationary contact b1 to the power 
source V.sub.DD, and at the common contact to the one end of the switched 
capacitor Cs11, and a second switch S2 which is connected at the first 
stationary contact a2 to the inverting input terminal (-) of the amplifier 
31.sub.1, and at the second stationary contact b2 to the power source 
V.sub.DD, and at the common contact to the other end of the switched 
capacitor Cs11. Switches S1 and S2 of the switch capacitor circuit 72 
operate such that the switched capacitor Cs11 is inserted between the 
signal input terminal 71 and the inverting input terminal (-) of the 
amplifier 31.sub.1 or short-circuits both ends of the switched capacitor 
Cs11. In the first switched mode, the common contacts of the switches S1 
and S2 are connected to the contacts a1 and a2, respectively, to connect 
the switched capacitor Cs11 between the signal input terminal 71 and the 
inverting input terminal (-) of the amplifier 72. In the second switched 
mode, the common contacts of the switches S1 and S2 are connected to the 
contacts b1 and b2, respectively, to short-circuit both ends of the 
switched capacitor Cs11. Since the contacts b1 and b2 are connected to the 
power source V.sub.DD, the switched capacitor Cs11 is short-circuited and 
connected to the power source V.sub.DD. 
The second capacitor circuit 73 is comprised of a switched capacitor Cs21, 
a first switch S1 which is connected at the first stationary contact a1 to 
the output terminal of the amplifier 31.sub.1, at the second stationary 
contact b1 to the power source V.sub.SS, and at the common contact to one 
end of the switched capacitor Cs21, and a second switch S2 which is 
connected at the first stationary contact a2 to the inverting input 
terminal (-) of the amplifier 31.sub.2, at the second stationary contact 
b2 to the power source V.sub.DD, and at the common contact to the other 
terminal of the switched capacitor Cs21. The switches S1 and S2 of the 
switched capacitor circuit 73 operate to change between the inverting 
input terminal (-) of the amplifier 31.sub.2 and the power source 
V.sub.SS, and between the output terminal of the amplifier 31.sub.1 and 
the power source V.sub.DD. In the first switched mode, the common contact 
of the switch S1 is connected to the contact b1, and the common contact of 
the switch S2 is connected to the contact a2. Then the switched capacitor 
Cs21 is connected to the inverting input terminal (-) of the amplifier 
31.sub.2 and the power source V.sub.SS. In the second switched mode, the 
common contact of the switch S1 is connected to the contact a1 and the 
common contact of the switch S2 to the contact b2. Then, the switched 
capacitor Cs21 is connected to the output terminal of the amplifier 
31.sub.1 and the power source V.sub.DD. 
The third switched capacitor circuit 74 is comprised of a switched 
capacitor Cs12, a first switch S1 which is connected at the first 
stationary contact a1 to the output terminal of the amplifier 31.sub.2, at 
the second stationary contact b1 to the power source V.sub.DD, and at the 
common contact to one end of the switched capacitor Cs12, and a second 
switch S2 which is connected at the first stationary contact a2 to the 
inverting input terminal (-) of the amplifier 31.sub.1, at the second 
stationary contact b2 to the power source V.sub.DD, and at the common 
contact to the other end of the switched capacitor Cs12. 
In the present embodiment, the power source V.sub.DD is supplied to the 
second contacts b1 and b2 of the switches S1 and S2 in the first and third 
switched capacitor circuits 72 and 74, the power source V.sub.SS is 
supplied to the second contact b1 of the switch S1, and the power source 
V.sub.DD is supplied to the second contact b2. A proper bias voltage 
between the power source voltage V.sub.DD and the power source voltage 
V.sub.SS is applied to the non-inverting input terminals (+) of the 
amplifiers 31.sub.1 and 31.sub.2. In this respect, the present embodiment 
is different from the prior low pass filter shown in FIG. 7. The bias 
circuit, using the power sources V.sub.DD and V.sub.SS as its drive 
source, forms the bias voltage using the power sources V.sub.DD and 
V.sub.SS, and supplies the formed bias voltage to the non-inverting input 
terminals (+) of the amplifiers 31.sub.1 and 31.sub.2. A value of the bias 
voltage is set to a proper value according to the characteristics of the 
amplifiers 31.sub.1 and 31.sub.2. For setting the bias voltage to 
"(1/2).times.(V.sub.DD -V.sub.SS)", for example, two resistors with the 
same resistances are connected in series between the power sources 
V.sub.DD and V.sub.SS and the junction between the two resistors is 
connected to the non-inverting input terminals (+) of the amplifiers 
31.sub.1 and 31.sub.2. With the two resistors having different resistances 
in place of the resistors R1 and R2, the bias voltage with a proper value 
according to a ratio of the resistances can be produced from the junction 
between the resistors. 
The operation of the mirror integrator using the switched capacitor circuit 
72 as a positive resistor in the low pass filter shown in FIG. 8 will be 
described. The operation of the mirror circuit using the switched 
capacitor circuit 74 as a positive resistor will not be described, since 
it is similar to the former integrator. In the circuit shown in FIGS. 9A 
and 9B, only the mirror integrator using the switched capacitor circuit 72 
in the low pass filter shown in FIG. 8 is illustrated. When the switches 
S1 and S2 are in the second switched mode in which the common contacts of 
the switches S1 and S2 are turned to b1 and b2, as shown in FIG. 9A, the 
switched capacitor Cs11 is short-circuited and connected to the power 
source V.sub.DD. Therefore, the charge stored in the switched capacitor 
Cs11 is discharged to zero. When the switches are in the first mode in 
which their common contacts are turned to the first contacts a1 and a2, as 
shown in FIG. 9B, the charge given by the following equation is stored in 
the capacitor Cs11. 
EQU Q=Cs11(Vi-Vi') (19) 
where Vi is a voltage of the signal input terminal 71, and Vi' is a voltage 
of the inverting input terminal (-) of the amplifier 31. The average 
current i flowing into the capacitor Cs11 is given 
EQU i=Cs11(Vi-Vi')f2 (20) 
And its equivalent resistance is 
##EQU11## 
The equation (21) is substantially equal to the equation (3). The circuit 
shown in FIGS. 9A and 9B has the same function as that of the FIGS. 5A and 
5B circuit. Accordingly, the input vs. output characteristic of the mirror 
integrator is substantially expressed by the equation (5), and is 
expressed 
##EQU12## 
As seen from the equation, even if the reference power source Vref 
connected to the capacitor circuit 50 is substituted by the power source 
V.sub.DD used as the drive power source, the operation of the mirror 
integrator is ensured. 
FIGS. 10A and 10B show only the mirror integrator using the switched 
capacitor circuit 73 as a negative resistor 73 in the low pass filter 
shown in FIG. 8. As shown in FIG. 10A, when the switches S1 and S2 are in 
the second switched mode, that is, when the common contacts of the 
switches S1 and S2 are in contact with the first contacts a1 and b2, a 
potential difference (Va-V.sub.DD) is applied across the switched 
capacitor Cs21. Accordingly, the charge Qa given by the following equation 
is stored in the capacitor Cs21. 
EQU Qa=Cs21(Va-V.sub.DD) 
As shown in FIG. 10B, when the common contact of the switch S1 is turned to 
the second contact b1 or the common contact of the switch S2 to the first 
contact a2, a potential difference (V.sub.SS -Va') is applied across the 
capacitor Cs21. Therefore, the charge Qb given by the following equation 
is stored in the capacitor Cs21. 
EQU Qb=Cs21(V.sub.SS -Va') 
When V.sub.SS =0, a moving charge quantity .DELTA.Q is 
##EQU13## 
Since the potential of (V.sub.DD /2) is applied to the non-inverting 
terminal (+) of the amplifier circuit 31.sub.1 by the bias circuit, the 
equation (22) can be rewritten into 
EQU .DELTA.Q=-Cs21(Va-Va') 
The average current i flowing between the contacts a1 and a2 and the 
equivalent resistance R are 
##EQU14## 
When comparing the equations (23) and (24) with the equations (20) and 
(21), these are identical except the minus (-) signs. This indicates that 
the switched capacitor circuit shown in FIGS. 10A and 10B operates as a 
negative resistor. Accordingly, the circuit shown in FIGS. 10A and 10B has 
the same function as that of the FIG. 6 circuit. And its input vs. output 
characteristic is given by 
##EQU15## 
As seen from the above equation, in the switched capacitor of the circuit 
shown in FIGS. 6A and 6B, even if the reference power source Vref 
connected to the second contacts b1 and b2 of the switches S1 and S2 is 
replaced by the contact b1, and the power source V.sub.CC is replaced by 
the contact b2, it operates as a mirror integrator. 
From the description on the switched capacitor circuits which has been made 
referring to FIGS. 10A and 10B, the switched capacitor circuits 72 to 74 
are driven by the two drive power sources V.sub.DD and V.sub.SS for the 
amplifiers 31.sub.1 and 31.sub.2. Accordingly, the low pass filter 
incorporating the switched capacitor circuits 72 to 74 shown in FIG. 8 are 
driven by only two power sources V.sub.DD and V.sub.SS and only two power 
source terminals are required. Thus, three power source terminals of the 
prior art device can be reduced by one. In this respect, the present 
embodiment is well adaptable for the integrated circuit fabrication. 
FIG. 11 shows a circuit diagram of the switched capacitor circuits 72 to 74 
in the low pass filter in FIG. 8 when it is fabricated into an integrated 
circuit. In FIG. 11, the switched capacitor circuits 111 to 113 correspond 
to the switched capacitor circuits 72 to 74 in the FIG. 8 filter. In the 
switched capacitor circuit 111, T1 and T3 are field effect transistors of 
the N channel type. Transistors T2 and T4 are field effect transistors of 
the P channel type. The transistor T1 serves as a first switch circuit; 
the transistor T2 as a second switch circuit. The transistors T1 and T2 
cooperate to form the selector switch S1 in the FIG. 8 filter. The 
transistor T3 serves as a third switch circuit and the transistor T4 as a 
fourth switch circuit, and the transistors T3 and T4 cooperate to form a 
selector switch S2 in the filter of FIG. 8. By clock pulses .phi.1 and 
.phi.2, the transistors T1 and T3 are controlled to be set in the same 
switched mode and the transistors T2 and T4 are similarly controlled to be 
set in the same switched mode. The switched capacitor circuit 111 will be 
described in more detail. The drain of the transistor T1 is connected to 
the signal input terminal 71. The drain of the transistor T2 is connected 
to the power source V.sub.DD. The sources of the transistors T1 and T2 are 
interconnected to each other. The junction between the transistors T1 and 
T2 is connected to one end of the capacitor Cs11. The drain of the 
transistor T3 is connected to the inverting input terminal (-) of the 
operational amplifier 31. The drain of the transistor T4 is connected to 
the power source V.sub.DD. The sources of the transistors T3 and T4 are 
interconnected each other and the junction therebetween is connected to 
the other end of the capacitor Cs11. The gates of the transistors T1 and 
T3 are connected together to the clock input terminal 114. The gates of 
the transistors T2 and T4 are connected together to the clock input 
terminal 115 through an inverter NOT. The clock input terminals 114 and 
115 are supplied with clock pulses .phi.1 and .phi.2 which have period of 
1/f.sub.s and the logic levels which are not concurrently "1". 
Accordingly, when the clock pulse .phi.1=0 and .phi.2=1, the transistors 
T1 and T3 are OFF and the transistors T2 and T4 are not ON. The result is 
that it is in the switched mode shown in FIG. 9A. When .phi.1=1 and 
.phi.2=0, the transistors T1 and T3 are ON and the transistors T2 and T4 
are OFF. The result is that it is in the switched mode shown in FIG. 9B. 
In the switched capacitor circuit 112, transistors T5 to T7 are field 
effect transistors of the N channel type, and T8 is a field effect 
transistor of the P channel type. The transistor T5 serving as the first 
switching circuit T5 and the transistor T6 serving as the second switching 
circuit cooperate to form a selector switch S1 in the switched capacitor 
circuit 73 in the filter shown in FIG. 8. The transistor T7 serving as the 
third switching circuit and the transistor T8 serving as the fourth 
switching circuit cooperate to form the selector switch S2. Under control 
of clock pulses .phi.1 and .phi.2, the transistors T5 and T8 are in the 
same switched mode and the transistors T6 and T7 are in the same switched 
mode. The drain of the transistor T5 is connected to the output terminal 
of the amplifier 31.sub.1. The source of the transistor T6 is connected to 
the power source V.sub.SS. The source of the transistor T5 and the drain 
of the transistor T6 are interconnected to each other and the junction 
therebetween is connected to one end of the capacitor Cs21. The drain of 
the transistor T7 is connected to the input terminal (-) of the amplifier 
31.sub.2. The drain of the transistor T8 is connected to the power source 
V.sub.DD. The transistors T7 and T8 are interconnected with each other and 
the junction between is connected to the other end of the capacitor Cs21. 
The gate of the transistor T5 is connected to the clock input terminal 115 
and the gates of the transistors T6 and T7 are connected together to the 
clock input terminal 114. The gate of the transistor T8 is connected to 
the clock input terminal 115 through the inverter NOT. With this 
arrangement and with the application of the clock pulses .phi.1 and 
.phi.2, the transistors T5 and T8 are ON when .phi.2="1" and the 
transistors T6 and T7 are OFF, thus being in the switched mode as shown in 
FIG. 10A. When .phi.1="1" and .phi.2="0", the transistors T5 and T8 are 
OFF and the transistors T6 and T7 are ON, thus being in the switched mode 
as shown in FIG. 10B. 
In the switched capacitor circuit 113, T9 and T11 are field effect 
transistors of the N channel type. Transistors T10 and T12 are field 
effect transistors of the P channel type. Their operation and the 
arrangement are substantially the same as those of the switched capacitor 
circuit 111, and no explanation of them will be given. 
In FIG. 11, a single transistor is used for each of the first to fourth 
switch circuits for the switched capacitors 111 to 113. In place of this, 
an analog switch such as a transistor switch, for example, a transmission 
gate may be used. 
FIG. 12 shows another embodiment of the present invention. In the present 
embodiment, the power sources V.sub.DD and V.sub.SS applied to the 
switched capacitor circuits 72 to 74 in the low pass filter of FIG. 8 are 
interchanged. With this arrangement, the switched capacitor circuits 72 to 
74 can be operated as equivalent resistor elements, as in the FIG. 8 
embodiment. 
In the embodiments as mentioned above, the bias circuit for applying the 
voltage V.sub.E, for example, (V.sub.DD -V.sub.SS)/2, to the non-inverting 
input terminals (+) of the amplifiers 31.sub.1 and 31.sub.2 may be 
modified variously in addition to the above-mentioned one. For example, a 
voltage drop circuit with small current consumption can be used for the 
bias circuit. When the MOS transistor is used at the first stage for the 
amplifier 31.sub.1, the input impedance at the non-inverting input 
terminal is almost infinite. Therefore, a high input impedance circuit may 
be used for the bias circuit for generating the voltage V.sub.E. Such a 
bias circuit has a small power consumption and therefore is well adaptable 
for the integrated circuit. 
When the output potential V.sub.E of the bias circuit in the low pass 
filter of FIG. 8 is set to 1/2(V.sub.DD -V.sub.SS), the output potential 
V.sub.E is equal to the reference potential Vref in the prior filter shown 
in FIG. 7. Accordingly, it may be considered that the output potential of 
the bias circuit in the FIG. 8 filter can be used for the reference 
potential Vref applied to the switched capacitor circuit in the prior 
filter shown in FIG. 7. This is problematic in practical use, however. The 
output of the bias circuit has a higher impedance than that of the power 
source. Therefore, in such arrangement, when the switched capacitor is 
short-circuited to be discharged, the output potential of the bias circuit 
slightly changes. The result is that the integration constant changes and 
the potential of the input signal to the input terminal (+) of the 
non-inverting input terminal (+) of the amplifier changes. With this 
potential change of the input signal, the output potential of the 
amplifier changes, possibly causing an erroneous operation of the circuit. 
For this reason, in the embodiment shown in FIG. 8, the output potential 
V.sub.E of the bias circuit is merely applied to the non-inverting input 
terminal (+), but the voltage is not applied to the switched capacitor 
circuits 72 to 74. 
As described above, in the low pass filter of the present invention, the 
power source for the operational amplifier is connected to the discharge 
path of the switched capacitor circuit and the bias circuit is formed 
using the power sources for the operational amplifier, the bias voltage 
from the bias circuit is applied for the inverting input terminal of the 
operational amplifier. With this arrangement, the number of the necessary 
power sources, i.e. the number of the power source terminals, can be 
reduced. In fabricating the circuit by the integration technology, the 
problems inherent to the prior art such as the complicated pattern design 
and the increased chip area are successfully solved. The arrangement 
according to the present invention is well adapted for integrated circuit 
fabrication.