Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, and a gate electrode formed on the substrate on a gate insulation film. The semiconductor device also includes a source diffusion layer and a drain diffusion layer which are formed on the substrate where the gate electrode is sandwiched between the source diffusion layer and the drain diffusion layer, one or more source contacts formed on the source diffusion layer; and one or more drain contacts formed on the drain diffusion layer. At least one of the source contacts and the drain contacts includes a first contact region having a first size and a second contact region having a second size larger than the first size on the same source diffusion layer or on the same drain diffusion layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-003608, filed Jan. 11, 2013, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a semiconductor device and a manufacturing method thereof.

BACKGROUND

The generation (technical node) of semiconductor devices has currently advanced through the 90 nm generation, the 64 nm generation, the 45 nm generation, the 32 nm generation and the 22 nm generation node. Further, the 28 nm generation (which is the half-node of the 32 nm generation) has been attracting attention as the design architecture and semiconductor manufacturing technique which is equivalent to the 32 nm generation node. However, although a critical layer to which the strictest design criteria is applied can be manufactured by performing a single exposure in the 32 nm generation, at 28 nm and succeeding generations, because of inherent physical limits which occur by single exposure of a feature, critical layers cannot be manufactured unless double exposure is performed, i.e., the feature must be created by twice exposing the resist, and then etching an underlying hard mask and to be etched layer.

For example, at the 28 nm generation and succeeding generations, the double exposure becomes necessary when forming a hole for a contact plug (hereinafter referred to as a “contact”). However, to reduce manufacturing costs of the semiconductor device, an attempt has been made to manufacture a contact in the 28 nm generation and succeeding generations when performing single exposure by changing the number of contacts or a size of a contact at the time of preparing a photo mask. However, when the single exposure is replaced with the double exposure in this manner, there arises a drawback in that irregular layout dependency is observed in an FET manufactured by the single exposure, and such layout dependency differs from the layout dependency of an FET manufactured by double exposure. In this case, the design and an operation verification result of the FET manufactured by double exposure cannot be utilized by the FET manufactured by single exposure and hence, it is necessary to perform operation verification independent, i.e., different from, the operation verification methodology performed on the FET manufactured by single exposure.

Further, there exists a situation where it is desirable that the same design parameters as the 32 nm generation are used at the 28 nm generation node. However, because the above-mentioned drawback exists, an operational characteristic of an FET of the 28 nm generation manufactured by single exposure becomes different from an operational characteristic of an FET of the 32 nm generation manufactured by single exposure (similar to an operational characteristic of an FET of the 28 nm generation manufactured by double exposure) and hence, the 28 nm generation cannot use the same design parameters as the 32 nm generation. As a result, the design and the operation verification methodology of the FET of the 32 nm generation cannot be utilized by an FET of the 28 nm generation and hence, also in the 28 nm generation, it is necessary for the 28 nm generation to perform the operation verification independently.

DETAILED DESCRIPTION

In general, according to one embodiment, the semiconductor device includes a substrate, and a gate electrode formed on the substrate on a gate insulation film. The semiconductor device also includes a source diffusion layer and a drain diffusion layer which are formed within the substrate, wherein the gate electrode is sandwiched between the source diffusion layer and the drain diffusion layer. One or more source contacts are formed on the source diffusion layer, and one or more drain contacts are formed on the drain diffusion layer. At least one of the source contact and the drain contact includes a first contact region having a first size and a second contact region having a second size larger than the first size on the same source diffusion layer or on the same drain diffusion layer.

Hereinafter, embodiments are explained in conjunction with the drawings.

First Embodiment

FIG. 1AtoFIG. 1Fare plan views showing the pattern of structures of a semiconductor device according to the first embodiment.FIG. 1AtoFIG. 1Cshow three examples of the layout or pattern of structures to be formed based upon design data of the semiconductor device according to the first embodiment. On the other hand,FIG. 1DtoFIG. 1Fshow the resulting formed structures of the semiconductor device when actually manufactured based on the design data shown inFIG. 1AtoFIG. 1C, respectively.

FIG. 2AandFIG. 2Bare views showing the structure of the semiconductor device shown inFIG. 1F, whereinFIG. 2Ais an enlarged plan view showing the structure shown inFIG. 1F, andFIG. 2Bis a cross-sectional view of the structure ofFIG. 2Ataken along a line I-I′ inFIG. 2A.

The semiconductor device of this embodiment is explained in detail by reference toFIG. 1hereinafter, and the explanation is also made by reference toFIG. 2, when necessary.

All drawings fromFIG. 1AtoFIG. 1Fshow one FET which is included in a semiconductor device according to this embodiment. The semiconductor device according to this embodiment includes, as constitutional elements of the FET, a substrate1, a gate insulation film2(seeFIG. 2), a gate electrode3, a source diffusion layer4, a drain diffusion layer5, an interlayer insulation film6(seeFIG. 2), one or more source contacts11, one or more drain contacts12, and a gate contact13. Although the semiconductor device according to this embodiment may be a semiconductor device of the generation where double exposure is performed (any one of generations including the 28 nm generation and the generations which follow, i.e., having a device pitch of less than the 28 nm generation, for example), the semiconductor device according to this embodiment is manufactured by performing single exposure using a technique for manufacturing a semiconductor device of this generation. Thus, the semiconductor devices in the 28 nm generation, and succeeding generations, include the semiconductor device of the 28 nm generation and semiconductor devices of the generations which follow the 28 nm generation.

The substrate1is a semiconductor substrate such as a silicon substrate, for example. InFIG. 1, the X direction and the Y direction which are parallel to a main surface of the substrate1and are orthogonal to each other, and the Z direction which is perpendicular to the main surface of the substrate1are shown. The X direction and the Y direction correspond to the longitudinal direction of the gate and the channel width direction of the FET. Here, the substrate1may be an SOI (Semiconductor On Insulator) substrate.

The gate electrode3is formed on the substrate1with the gate insulation film2therebetween. The source diffusion layer4and the drain diffusion layer5are formed within the substrate1in a state where the gate electrode3is positioned between, and at its sides, overlies the layers4,5. The interlayer insulation film6is formed on the substrate1so as to cover the FET. The source contact11, the drain contact12and the gate contact13(shown inFIG. 2Aonly) are formed on the source diffusion layer4, the drain diffusion layer5and the gate electrode3respectively within the interlayer insulation film6.

(1) Detail of Source Contact11and Drain Contact12

Next, the details of the source contact11and the drain contact12are explained by reference toFIG. 1successively.

InFIG. 1AtoFIG. 1F, for the structure of both the source contact11and the drain contact12, a first contact region C1having a first size and a second contact region C2having a second size larger than the first size are shown inFIG. 2A.

In the design architecture shown inFIG. 1A, one first contact region C1is arranged on both the source diffusion layer4and the drain diffusion layer5. In the same manner, in the semiconductor device shown inFIG. 1D, which corresponds to the semiconductor device shown inFIG. 1A, one first contact C1is arranged on each of the source diffusion layer4and the drain diffusion layer5.

In the design architecture or layout of a semiconductor device shown inFIG. 1B, two first contact regions C1are arranged on (and contact, not shown) both the source diffusion layer4and the drain diffusion layer5. On the other hand, in the actually manufactured semiconductor device using the layout ofFIG. 1Bas shown inFIG. 1E, which corresponds to the semiconductor device design or layout shown inFIG. 1B, one second contact region C2larger than the contact C1ofFIG. 1Bis formed on (and contacts, not shown) each of the source diffusion layer4and the drain diffusion layer5.

In the design architecture or layout of a semiconductor device shown inFIG. 1C, three first contact regions C1are arranged on both the source diffusion layer4and the drain diffusion layer5. On the other hand, in the semiconductor device actually manufactured using the layout ofFIG. 1Cas shown inFIG. 1F, only one first contact region C1and one second contact region C2, larger than the individual contact regions C1ofFIG. 1C, are arranged on both the source diffusion layer4and the drain diffusion layer5.

The semiconductor device according to this embodiment is the semiconductor device of the generation where double exposure is performed and hence, it is difficult to form a plurality of first contact regions C1on the same source diffusion layer4or on the same drain diffusion layer5by performing the exposure one time in the same manner as the design architecture shown inFIG. 1BandFIG. 1C. The reason is that a distance between the first contacts C1is extremely small.

To overcome this drawback, in this embodiment, a photo mask is prepared, based on design architecture shown inFIG. 1BorFIG. 1C, for single exposure by replacing two first contact regions C1arranged on the same source diffusion layer4or on the same drain diffusion layer5with one second contact region C2. In this embodiment, with the use of such a photo mask, the source contact11and the drain contact12can be predictably formed by performing the exposure one time.

As a result, in this embodiment, the semiconductor structures shown inFIG. 1EandFIG. 1Fare manufactured based on the design data shown inFIG. 1BandFIG. 1C, respectively. For example, in the semiconductor device shown inFIG. 1F, the source contact11includes both the first contact region C1and the second contact region C2on the same source diffusion layer4and, in the same manner, the drain contact12includes both the first contact region C1and the second contact region C2on the same drain diffusion layer5.

Symbol X1indicates a length of the first contact region C1to be actually manufactured in the X direction (longitudinal direction of the gate), and symbol Y1indicates a width of the first contact region C1to be actually manufactured in the Y direction (channel width direction). Further, Symbol X2indicates a length of the second contact region C2that is actually formed on the substrate in the X direction, and symbol Y2indicates a width of the second contact region C2that is actually formed on the substrate in the Y direction.

In this embodiment, the length X2is set substantially equal to the length X1, while the width Y2is set wider than the size Y1. Due to such a constitution, in this embodiment, the size (volume) of the second contact region C2is greater than the size (volume) of the first contact region C1.

Next, the detail of a resistance R1of the first contact region C1and a resistance R2of the second contact region C2is explained also by reference toFIG. 1.

As described previously, in this embodiment, in manufacturing the semiconductor device based upon the design data, two first contact regions C1arranged on the same source diffusion layer4, or on the same drain diffusion layer5, are replaced with one second contact region C2. In this case, there arises a drawback that the resistance of the source contact11or the resistance of the drain contact12is changed before and after the replacement. This change adversely influences an operating characteristic of the FET (details of this drawback are explained later in conjunction withFIG. 4).

In view of the above, in this embodiment, to allow one second contact region C2to acquire a function substantially equal to a function performed by two first contact regions C1, the resistance of one second contact region C2is set to a value substantially equal to the resistance generated when two first contact regions C1are connected to each other in parallel. Due to such setting, the relationship expressed by the following formula (1) is established between the resistance R1and the resistance R2.
1/R2=1/R1+1/R1(1)

To solve this formula (1), the resistance R2becomes ½ of the resistance R1(R2=R1/2).

Further, in this embodiment, the first contact region C1and the second contact region C2are formed using the same material. Accordingly, as expressed by the following formula (2), a ratio between the resistance R1and the resistance R2substantially corresponds to a ratio between the inverse number of an area X1Y1and the inverse number of an area X2Y2.
R1:R2=1/X1Y1:1/X2Y2(2)

When substituting the formula (2) for the formula (1), the area X2Y2then becomes two times greater than the area X1Y1(X2Y2=X1Y1×2).

Accordingly, in this embodiment, by setting a size Y2to a value two times greater than a size Y1, the area X2Y2is set to a value approximately two times greater than the area X1Y1. In this embodiment, by setting the resistance R2to a value approximately ½ of the resistance R1in this manner, it is possible to allow one second contact region C2to acquire a function substantially equal to a function acquired by two first contact regions C1.

However, in this embodiment, in general, the ratio between the resistances does not strictly correspond with the ratio between the inverse numbers of the areas which is expressed by the formula (2). One of reasons is that, as shown inFIG. 2B, a side surface of the source contact11and a side surface of the drain contact12are generally angled or inclined relative to a plane of the substrate1. Further, in a case where planar shapes of the source contact11and the drain contact12to be manufactured actually are closer to a circular shape or an elliptical shape rather than a square shape or a rectangular shape, such shapes also cause the above-mentioned disagreement between the ratios.

Accordingly, in this embodiment, in setting the resistance R2to ½ of the resistance R1, an area X2Y2may not be simply set to an area two times greater than the area X1Y1, but the area X2Y2is adjusted to an area in the range of or about the area which is twice as large as the area X1Y1by finely adjusting the area such that the resistance R2approaches ½ of the resistance R1. Such fine adjustment can be performed such that, for example, in preparing a photo mask, an area of the second contact region C2on the photo mask is finely adjusted, or Optical Proximity Correction (OPC) is applied to a pattern for a second contact region C2on the photo mask.

Further, in this embodiment, in manufacturing the semiconductor device based on design data, N (N being an integer of 2 or more) areas of the first contact region C1arranged on the same source diffusion layer4, or on the same drain diffusion layer5, may be replaced with one second contact region C2. That is, as shown inFIG. 1, this embodiment is applicable not only to a case where two first contact regions C1are replaced with one second contact region C2but also to a case where three or more first contact regions C1are replaced with one second contact region C2.

In this case, to allow one second contact region C2to have a function substantially equal to a function of N first contact regions C1, the resistance of one second contact region C2is set to a value substantially equal to the resistance of N first contact regions C1which are connected to each other in parallel. That is, the resistance R2is set to 1/N of the resistance R1. Such setting can be realized by setting the area X2Y2to an area N times as the size of the area X1Y1based on the relationship expressed by the formula (2).

In this case, by taking into account the instance where the formula (2) is not strictly established as described above, the resistance R2may have a tolerance of approximately ±10%. To be more specific, as expressed by the following formula (3), a value of the resistance R2is not always limited to R1/N which is a parallel resistance of N first contact regions C2, but may be set to a value of 0.9 times to 1.1 times as large as R1/N.
0.9×R1/N≦R2≦1.1×R1/N(3)

For example, in the instance where N is 2 (N=2) (in the case where two first contact regions C1are replaced with one second contact region C2as shown inFIG. 1), a value of the resistance R2is not always limited to R1/2 (=0.5×R1), but is set to a value which falls within a range of 0.45×R1to 0.55×R1.

Further, in this embodiment, the first and second contact regions C1, C2may be formed using only one kind of material, or may be formed using two or more kinds of materials. In the latter case, however, since a ratio between the resistance R1and the resistance R2depends on electrical resistivities of these materials, in general, it is necessary to take into account the electrical resistivities of the materials in adjusting the ratio between the resistances R1, R2.

(3) Comparison Between the First Embodiment and a Conventional Example

Next, by reference toFIG. 3andFIG. 4, the semiconductor device of the first embodiment and the semiconductor device of a conventional example are compared.

FIG. 3AtoFIG. 3Fare plan views showing the layout or pattern of structure based upon design data of the semiconductor device of the conventional example and the structure of the semiconductor device of the conventional example to be actually manufactured.FIG. 3AtoFIG. 3Cshow the design data which are equal to the design data shown inFIG. 1AtoFIG. 1Crespectively. Further,FIG. 3DtoFIG. 3Fshow the structures of the resulting semiconductor device to be actually manufactured based on the design data shown inFIG. 3AtoFIG. 3C, respectively.

In the conventional example, in the same manner as the first embodiment, it is difficult to manufacture a plurality of first contact regions C1arranged on the same source diffusion layer4, or on the same drain diffusion layer5, by performing exposure one time as in the design data shown inFIG. 3BandFIG. 3C.

Accordingly, in the conventional example, in preparing a photo mask based on design data shown inFIG. 3B, a photo mask for one-time exposure is prepared by replacing two first contact regions C1with one contact region C1′ (shown inFIG. 3E) which is larger than the first contact region C1

Further, in the conventional example, in preparing a photo mask based on the design data shown inFIG. 3C, a photo mask for one-time exposure is prepared by replacing three first contact regions C1with two contact regions C1″ (shown inFIG. 3F) which are larger than each of the first contact regions C1.

As a result, in this comparative example, the semiconductor device shown inFIG. 3EandFIG. 3Fare manufactured based on the design data shown inFIG. 3Band FIG.3C, respectively.

In this manner, in this example, in the same manner as the first embodiment, the replacement of the contact is performed when the semiconductor device is manufactured based upon design data. In this example, however, different from the first embodiment, in performing such contact area replacement, an operation to make a contact resistance before the replacement correspond with a contact resistance after the replacement is not taken into consideration. Accordingly, in this conventional example, as shown inFIG. 4, an operating characteristic of a FET is different before and after the replacement.

FIG. 4is a graph for comparing the manner of operation of the semiconductor device of the first embodiment with the manner of operation of the semiconductor device of the comparative example described inFIGS. 3A-3F.

Bars P1, P2, P3show the drive currents of FETs in instances where the semiconductor devices are manufactured by double (two-time) exposure based on the design data shown inFIG. 1AtoFIG. 1C, respectively. Here, values of all drive currents expressed by the bars P1, P2, P3are values obtained by dividing values of the drive currents of the FETs by values of the drive currents of the FETs in the semiconductor devices manufactured by double exposure based on the design data shown inFIG. 1A.

Bars Q1, Q2, Q3show drive currents of the FETs in cases where the semiconductor devices of the comparative examples shown inFIG. 3DtoFIG. 3Fare manufactured by single exposure based on the design data shown inFIG. 3AtoFIG. 3C, respectively. Here, values of all drive currents expressed by the bars Q1, Q2, Q3are values obtained by dividing values of the drive currents of the FETs by a value of the drive current of the FET in the semiconductor device of the comparative example shown inFIG. 3Dto be manufactured by single exposure.

Bars R1, R2, R3show drive currents of the FETs in cases where the semiconductor devices of the first embodiment shown inFIG. 1DtoFIG. 1Fare manufactured by single exposure based on the design data shown inFIG. 1AtoFIG. 1C, respectively. Here, values of all drive currents expressed by the bars R1, R2, R3are values obtained by dividing values of the drive currents of the FETs by a value of the drive current of the FET in the semiconductor device of the first embodiment shown inFIG. 1Dto be manufactured by single exposure based on the design data shown inFIG. 1A.

In the case of the double exposure indicated by the bars P1to P3, when the number of first contact regions C1(hereinafter referred to as “contact region number”) per one source diffusion layer4, or per one drain diffusion layer5, is increased from 1 to 2, the drive current is increased 1.3 times. Further, in the case of the bars P1to P3, when the contact region number is increased from 1 to 3, the drive current is increased 1.4 times.

On the other hand, in the case of single exposure in the comparative example indicated by bars Q1to Q3, when the contact region number is increased from 1 to 2, the drive current is increased 1.1 times. Further, in the cases of the bars Q1to Q3, when the contact region number is increased from 1 to 3, the drive current is increased 1.3 times.

In this manner, when the double exposure is replaced with single exposure of the conventional example, in the FET manufactured by single exposure, an irregular layout dependency, which is different from the layout dependency of the FET manufactured by double exposure, is generated. In this case, the design and an operation verification methodology of the FET manufactured by the double exposure method cannot be utilized in FETs manufactured by the single exposure method. Thus, it becomes necessary to perform the operation verification independently.

Further, in the case of the 28 nm generation, when such a problem exists, the design and an operation verification result of the FET of 32 nm generation manufactured by the single exposure cannot be utilized in FETs of the 28 nm generation which are manufactured by single exposure. Thus, it is necessary to perform the operation verification independently with respect to the 28 nm generation. Here, when the bars P1, P2, P3indicate operating characteristics of FETs of 28 nm, which are manufactured by double exposure under the same design environment as the 32 nm generation, the bars P1, P2, P3correspond with the operating characteristics of FETs of the 32 nm generation which are manufactured using single exposure.

Accordingly, in the first embodiment, as described previously, to allow one second contact region C2to have a function substantially equal to a function of two first contact regions C1, the resistance of one second contact region C2is set to a value substantially equal to the resistance of two first contact regions C1which are connected to each other in parallel.

As a result, in the case of the single exposure in the first embodiment indicated by the bars R1to R3, the layout dependency is substantially equal to the layout dependency when double exposure is performed, as indicated by the bars P1to P3. According to the first embodiment, the design and an operation verification result of the FET manufactured by double exposure can be utilized with FETs manufactured by single exposure. Further, the design and the operation verification result of the FET of a 32 nm generation can be utilized by FETs of the 28 nm generation, which is the half-node generation of the 32 nm generation.

(4) Modification of First Embodiment

Next, a modification of the first embodiment is explained in conjunction withFIG. 5.

FIG. 5is a plan view showing the structure of a semiconductor device according to the modification of the first embodiment.

InFIG. 5A, two first contact regions C1and two second contact regions C2are arranged on each of a source diffusion layer4and a drain diffusion layer5. In this manner, in this modification, a plurality of first contact regions C1and a plurality of second contact regions C2may be arranged on each of the same source diffusion layer4and the same drain diffusion layer5.

Here, on the source diffusion layer4shown inFIG. 5A, the first contact regions C1and the second contact regions C2are arranged alternately. In the same manner, on the drain diffusion layer5shown inFIG. 5A, the first contact regions C1and the second contact regions C2are arranged alternately. Such an arrangement has an advantageous effect that, compared with an arrangement where same kind of contacts are consecutively arranged adjacent to each other, makes it easy to balance an electric current or balance resistance in the source diffusion layer4and in the drain diffusion layer5, for example.

InFIG. 5A, both the first contact regions C1on the source diffusion layer4are arranged adjacent to second contact regions C2on the drain diffusion layer5, respectively, with a gate electrode3sandwiched therebetween. In the same manner, both the second contact regions C2on the source diffusion layer4are arranged adjacent to first contact regions C1on the drain diffusion layer5, respectively, with the gate electrode3sandwiched therebetween. Such an arrangement has an advantageous effect that, compared with an arrangement where the same kind of contacts are arranged adjacent to each other with the gate electrode3sandwiched therebetween, it is easy to balance an electric current and balance resistances in the source diffusion layer4or in the drain diffusion layer5, for example.

InFIG. 5B, a first contact region C1having a first size, a second contact region C2having a second size greater than the first size, and a third contact region C3having a third size greater than the second size are arranged on each of the source diffusion layer4and the drain diffusion layer5. In this manner, according to this modification, three or more kinds of contact regions may be arranged on each of the same source diffusion layer4and the same drain diffusion layer5. Here, the third contact region C3corresponds to an example of a second contact region in the case where the above-mentioned value of N is 3 or more.

In this embodiment, only two kinds of contacts may be used as source contacts11and drain contacts12. Alternatively, three or more kinds of contact regions may be used as shown inFIG. 5B. However, by setting a low number of kinds of contact regions to be used, it is possible to acquire an advantageous effect that the manufacture of the semiconductor device becomes easier, which includes simplification of the preparation of the photo mask. When the number of kinds of contact regions to be used is small, for example, as shown inFIG. 1(F), the number of occasions where plural kinds of contact regions are arranged on the same source diffusion layer4, or the same drain diffusion layer5, is increased.

In this embodiment, in the replacement of the first contact regions C1with the second contact region C2, the length X2and the length X1are set substantially equal to each other in length, and the width Y2is set longer than the width Y1. As an alternative example, it may be possible to set these widths and lengths such that the length X2is set to be greater than the length X1, and the width Y2and the width Y1are set to be substantially equal to each other. In this embodiment, it may be also possible to set these dimensions such that the length X2and the length X1differ from each other in length, and the size Y2and the size Y1differ from each other. For example, the area X2Y2may be set to a value two times greater than the area X1Y1by setting the length X2to a value √2 times as large as the length X1and by setting the width Y2to a value √2 times as large as the width Y1. In these cases, however, it is desirable that the dimensions and the arrangement of the contact regions are determined such that the distance between the contact regions is set so as to allow single exposure methods, i.e., they are spaced so that irregular formation thereof does not occur.

Further, in this embodiment, although the number of the source contacts11which are arranged on the source diffusion layer4and the number of the drain contacts12which are arranged on the drain diffusion layer5are set equal, the number of the source contact11and the number of the drain contact12may be different from each other.

As described above, in this embodiment, in manufacturing the semiconductor device based on the design data, the first contact regions C1arranged on the source diffusion layer4, or on the drain diffusion layer5, are replaced with the above-mentioned second contact region C2, thus manufacturing the semiconductor devices exemplified inFIG. 1EandFIG. 1F. According to this embodiment, in manufacturing the contact regions by replacing plural exposure methods to a single exposure method, it is possible to suppress irregular layout dependency.

Second Embodiment

FIG. 6is a flowchart showing a manufacturing method of a semiconductor device according to one embodiment.FIG. 6shows one example of steps for manufacturing the semiconductor devices shown inFIG. 1DtoFIG. 1Fbased upon the design data shown inFIG. 1AtoFIG. 1C.

Firstly, design data for manufacturing the semiconductor device having the structure shown inFIG. 1AtoFIG. 1Cis prepared (step S1).

Next, a photo mask is prepared based on the design data (step S2). Here, in handling the design data shown inFIG. 1A, a photo mask for single exposure is prepared for manufacturing a semiconductor device which exactly complies with the design data. On the other hand, in handling the design data shown inFIG. 1BorFIG. 1C, a photo mask for single exposure is prepared by replacing two first contact regions C1arranged on the same source diffusion layer4, or on the same drain diffusion layer5, with one second contact region C2.

Next, a semiconductor device is manufactured using the above-mentioned photo mask (step S3). Here, source contacts11or drain contacts12can be manufactured by single exposure. In this manner, the semiconductor devices shown inFIG. 1DtoFIG. 1Fare manufactured based on the design data shown inFIG. 1AtoFIG. 1Crespectively.

As described above, according to this embodiment, not only in the handling of the design data shown inFIG. 1A, but also in the handling of design data shown inFIG. 1BorFIG. 1C, it is possible to manufacture the source contact11and the drain contact12by single exposure. In this embodiment, by performing the replacement of the first contact region C1with the second contact region C2in the same manner as the first embodiment, it is possible to suppress the generation of the above-mentioned irregular layout dependency.