Current regulator system

An example of a power supply system includes a switching voltage regulator comprising at least one switch configured to conduct an input current to generate an output voltage responsive to a switching signal and based on an input voltage. The system also includes a current regulator configured to generate a current sample voltage based on an amplitude of the input current relative to a reference current defining a maximum average amplitude setpoint of the input current to set a switching time defining a switching period of the at least one switch. The system also includes a switch controller configured to provide the switching signal to control the at least one switch based on an amplitude of the output voltage relative to a reference voltage and based on the switching time.

TECHNICAL FIELD

This description relates generally to electronic circuits, and more particularly to a current regulator system.

BACKGROUND

Power supply circuits can be implemented in a variety of different ways. Examples of power supply circuits include synchronous rectifier power converters, asynchronous rectifier power converters, resonant power converters, and any of a variety of other types of switching power converters. A typical power supply circuit can thus activate one or more switches to convert an input voltage to an output voltage. Power supply circuits are typically implemented in wireless electronic devices. As a result, the input voltage is typically provided by a battery. Thus, the operational life of the battery is typically limited by the amplitude of the input current that is provided from the input voltage to generate the output voltage in the power supply circuit. For example, in a switching power supply circuit that provides current through an inductor, the operational life of the battery can be based on an average amplitude of the input current through an operating cycle of the switching power supply circuit.

SUMMARY

An example circuit includes a switching voltage regulator having a first input, a second input, and an output. The first input is coupled to a source of an input current. A current regulator has an input, a first output and a second output. The input is coupled to the source of the input current. The current regulator provides at the first output a comparison signal having a logic state responsive to a current sampling voltage. The current regulator provides a reference current at the second output proportional to a maximum average amplitude setpoint of the input current over a switching period of the switching voltage regulator. A switch controller has a first input, a second input, a third input and an output, the first input coupled to the first output of the current regulator circuit. The second input is coupled to the output of the switching voltage regulator, and the third input is adapted to be coupled to a reference voltage source. The output is coupled to the second input of the switching voltage regulator.

An example of a power supply system includes a switching voltage regulator comprising at least one switch configured to conduct an input current to generate an output voltage responsive to a switching signal and based on an input voltage. The system also includes a current regulator configured to generate a current sample voltage based on an amplitude of the input current relative to a reference current defining a maximum average amplitude setpoint of the input current to set a switching time defining a switching period of the at least one switch. The system also includes a switch controller configured to provide the switching signal to control the at least one switch based on an amplitude of the output voltage relative to a reference voltage and based on the switching time.

An example of an integrated circuit (IC) includes a switching voltage regulator comprising at least one switch configured to conduct an input current to generate an output voltage responsive to a switching signal and based on an input voltage. The IC also includes a current regulator configured to generate a current sample voltage across a sampling capacitor. The current sample voltage can be based on an amplitude of the input current relative to a reference current that is set at a first external pin and which is proportional to a maximum average amplitude setpoint of the input current to set a switching time defining a switching period of the at least one switch. The IC includes an input pin adapted to be coupled to a source of the reference current. The IC further includes a switch controller configured to provide the switching signal to control the at least one switch based on the switching time and based on an amplitude of the output voltage relative to a reference voltage that is set at a second external pin.

DETAILED DESCRIPTION

This description relates generally to electronic circuits, and more particularly to a current regulator system. The current regulator system can be included in a power supply system, such as a switching power supply system. The power supply system can also include a switching voltage regulator that includes at least one switch that is controlled by a switch signal to provide an input current from an input voltage and through an inductor to generate an output voltage. The power supply system further includes a switch controller that is configured to generate the switch signal, such as based on the output voltage relative to a reference voltage, and to a current sampling voltage that has an amplitude associated with a switching time of the switching voltage regulator to regulate an amplitude of the input current.

As an example, the input voltage is provided from a battery. Therefore, the current regulator system can be configured to regulate the amplitude of the input current to mitigate current draw from the battery, and to therefore extend the operating life of the battery. The current regulator system can include a sampling capacitor that is configured to generate the current sampling voltage that is based on a sampling current. The sampling current can be based on a charging current that is associated with the input current and a reference current. As one example, the charging current is generated based on the input current and which is proportional to the input current. As another example, the charging current is a current that has a fixed amplitude that is estimated to be proportional to the input current. The reference current can have an amplitude that is proportional to a maximum average amplitude setpoint of the input current over a switching period.

The current sampling voltage can have an amplitude that is based on the amplitude of the charging current minus a reference current during a first switching phase of the switching voltage regulator. For example, the reference current is arranged to flow from the sampling capacitor. Thus, during the first switching phase of the switching voltage regulator, the amplitude of the current sampling voltage can increase. During a second switching phase of the switching voltage regulator, the amplitude of the current sampling voltage can be based on the reference current only, such that the amplitude of the current sampling voltage can decrease during the second switching phase of the switching voltage regulator. The duration of time between the beginning of charging of the sampling capacitor in the first sampling phase to the end of the discharging of the sampling capacitor in the second sampling phase (e.g., between equal charges of approximately zero) can define the switching time of the switching voltage regulator. Thus, the switch controller can monitor the amplitude of the current sampling voltage to switch between the switching phases of the switching voltage regulator, and to thus regulate the amplitude of the output voltage and the input current.

FIG.1is an example of a block diagram of a power supply system100. The power supply system100can be implemented in any of a variety of wireless electronic devices, such as laptop computers, tablet computers, smart phones, or any of a variety of other electronic devices. The power supply system100is configured to generate an output voltage VOUTfrom an input voltage VIN. As an example, the input voltage VINis provided from a battery. As described herein, the power supply system100can provide regulation of an input current IINthat is drawn from a battery to mitigate an average amplitude of the input current IIN, and therefore to extend the operational life of the battery. As an example, the power supply system100is fabricated on or as part of an integrated circuit (IC).

The power supply system100includes a switching voltage regulator102that includes at least one switch104that is controlled by a respective at least one switching signal, shown in the example ofFIG.1as a signal SS, to generate the output voltage VOUTbased on the input voltage VIN. As an example, the switching voltage regulator102operates as a buck regulator or a boost regulator, and/or operates in buck and boost modes, to generate the output voltage VOUT. For example, the switch(es)104include a high-side switch (e.g., P-channel field effect transistor (PFET)) and a low-side transistor (e.g., N-channel field effect transistor (NFET)) that are alternately activated to provide current through an inductor to generate the output voltage VOUTat an output of the switching voltage regulator102. As described herein, the activation of the switch(es)104can be defined by switching phases, such as a first switching phase and a second switching phase, that define changes in the current through the inductor and which collectively define a switching period of the switching voltage regulator102.

The power supply system100also includes a current regulator system106that is configured to regulate an amplitude of the input current IIN. As described above, the input current TINcan be drawn from a battery, such that monitoring and regulating the amplitude of the input current IINcan result in an extension of the operational life of the battery. In the example ofFIG.1, the current regulator system106includes a reference current generator108that is configured to generate a reference current that has an amplitude that is proportional to a maximum average amplitude setpoint of the input current IINover a switching period. As an example, the reference current generator108is set at an external pin of the associated IC on which the power supply system100is fabricated (e.g., as a grounded resistor).

The current regulator system106can include a sampling capacitor that is configured to generate a current sampling voltage VSMPLthat is based on a charging current that is associated with the input current IINand based on the reference current. As one example, the charging current is a current that is generated based on the input current IINand which is proportional to the input current IIN. As another example, the charging current is a current that has a fixed amplitude that is estimated to be proportional to the input current. For example, the charging current and the reference current are each proportioned in amplitude with respect to the input current IIN, such that the reference current is proportional to the maximum average amplitude setpoint of the input current IINover a switching period.

As an example, the current sampling voltage VSMPLhas an amplitude that is based on the amplitude of the charging current minus the reference current during a first switching phase of the switching voltage regulator102, such as defined by the switching signal(s) SS. For example, the reference current flows from the sampling capacitor to pull current away from the charging current that is provided to the sampling capacitor. Thus, during the first switching phase of the switching voltage regulator102, the amplitude of the current sampling voltage VSMPLcan increase, and can be proportional to the sensed amplitude of the input current IIN. During a second switching phase of the switching voltage regulator102, the amplitude of the current sampling voltage VSMPLcan be based on the reference current but not on the charging current. For example, the switching signal(s) SS can include signals that operate switches to control the charging current being provided to the sampling capacitor. Therefore, the amplitude of the current sampling voltage VSMPLcan decrease during the second switching phase of the switching voltage regulator102, and can therefore be proportional to the target regulation amplitude of the input current IIN.

For example, the current regulator system106includes a sampling comparator that is configured to identify approximately zero volts across the sampling capacitor, and thus an approximate zero voltage amplitude of the current sampling voltage VSMPL. As described herein, the term “approximately” can include some deviation from an exact value (e.g., +/−5%). Therefore, the sampling comparator can identify an approximately equal amplitude of the current sampling voltage VSMPLacross the sampling capacitor at the beginning and end of a given switching period of the switching voltage regulator102. In the example ofFIG.1, the output of the sampling comparator is shown as a comparison signal CMP1.

The power supply system100further includes a switch controller110. The switch controller110is configured to provide the switching signal(s) SS responsive to the comparison signal CMP1. For example, the sampling comparator monitors the amplitude of the current sampling voltage VSMPLto switch from the second switching phase of the switching voltage regulator102to the first switching phase of the switching voltage regulator102, and thus to a next switching period of the switching voltage regulator102. The next switching period can also be initiated based on an amplitude of the output voltage VOUTrelative to a reference voltage VREF. As an example, the reference voltage VREFcan be set at an external pin of the associated IC on which the power supply system100is fabricated (e.g., as a fixed voltage source). Therefore, the switch controller110can control the switching time of the switching voltage regulator102based on the amplitude of the current sampling voltage VSMPL. For example, the switch controller110also includes a state machine that is configured to generate the switching signal(s) SS, such as based on the amplitude of the current sampling voltage VSMPLand the amplitude of the output voltage VOUTrelative to the reference voltage VREF.

As a result of the switch controller110controlling the switching period of the switching voltage regulator102based on the current sampling voltage VSMPL, the power supply system100can regulate the amplitude of the input current IINto mitigate the power consumption from the associated battery, thereby extending the operational life of the battery. For example, by implementing the reference current generator108to pull the reference current from the sampling capacitor and providing the switching period transition on the time between a beginning amplitude of the current sampling voltage VSMPLin the first switching phase is approximately equal to a final amplitude of the current sampling voltage VSMPLin the second switching phase, the power supply system100can reduce the average amplitude of the input current IINthrough the switching period of the switching voltage regulator102. Accordingly, the power supply system100can extend the operational life of the battery that provides the input voltage VIN. Additionally, as described in greater detail herein, the power supply system100can operate in any of a variety of waveforms of the current through the inductor of the switching voltage regulator102.

FIG.2is an example of a schematic electrical circuit diagram of a power supply circuit200. The power supply circuit200can be implemented in any of a variety of wireless electronic devices, such as laptop computers, tablet computers, smart phones, or any of a variety of other electronic devices. The power supply circuit200is configured to generate an output voltage VOUTfrom an input voltage VIN. The power supply circuit200can be the power supply system100in the example ofFIG.1. Therefore, reference is to be made to the example ofFIG.1in the following description of the example ofFIG.2.

The power supply circuit200includes a switching voltage regulator202. The switching voltage regulator202includes a high-side switch, shown as a PFET P1, a low-side switch, shown as an NFET N1, a first output switch, shown as an NFET N2, and a second output switch, shown as an NFET N3. The PFET P1interconnects the input voltage VINat a source and a switching node204at a drain, and the NFET N1interconnects the switching node204at a drain and a low-voltage rail, shown in the example ofFIG.2as ground, at a source. The NFET N2interconnects the output voltage VOUTat a drain and a switching node206at a source, and the NFET N3interconnects the switching node206at a drain and the low-voltage rail at a source. An inductor L1interconnects the switching nodes204and206and is configured to conduct a current IL.

The PFET P1is controlled by a switching signal IN1, the NFET N1is controlled by a switching signal IN2, the NFET N2is controlled by a switching signal OUT1, and the NFET N3is controlled by a switching signal OUT2. The activation of the FETs P1, N1, N2, and N3in a sequence provides the current ILthrough the inductor L1in switching phases defined by the switching signals IN1, IN2, OUT1, and OUT2, respectively. For example, the activation of the PFET P1and NFET N3provides the input current IINto flow from the input voltage VINto the switching node204during the first switching phase based on the switching signal IN1and OUT2, such that the current ILis approximately equal to the input current IINduring the first switching phase of the switching voltage regulator202. During the second switching phase of the switching voltage regulator202, the PFET P1and NFET N3are deactivated and the NFET N1and NFET N2are activated by the switching signal IN2and OUT1to conduct the current ILfrom the low-voltage rail through the inductor L1.

FIG.3is an example of timing diagrams. The timing diagrams include a first timing diagram302that shows inductor current ILplotted as a function of time for a converter operating in buck mode, and a second timing diagram304that shows inductor current ILplotted as a function of time for a converter operating in boost mode. The inductor current ILcan be the current through the inductor L1of the switching voltage regulator202in the example ofFIG.2. Therefore, reference is to be made to the example ofFIG.2in the following description of the example ofFIG.3. For simplicity sake, the transition times of the timing diagrams302and304are aligned. However, the transition times can differ between the buck and boost modes.

In the first timing diagram302, the switching voltage regulator202begins a first switching phase at a time T0. At the time T0, the PFET P1and the NFET N3are activated by the switching signals IN1and OUT2, respectively. Therefore, the input current IINflows from the input voltage VIN, through the PFET P1, and through the inductor L1as the current IL, and through the NFET N3. Thus, in the example ofFIG.3, the current ILis demonstrated as increasing from an amplitude of IL0, which is an amplitude greater than or equal to zero, to an amplitude IL1at a time T1. At the time T1, the NFET N3is deactivated by the switching signal OUT2and the NFET N2is activated by the switching signal OUT1. Therefore, the input current IINflows from the input voltage VIN, through the PFET P1, and through the inductor L1as the current IL, and through the NFET N2, such as to charge an output capacitor (not shown in the example ofFIG.2). Thus, in the example ofFIG.3, the current ILis demonstrated as increasing from the amplitude IL1to an amplitude IL2at a time T2, and thus at a lesser slope than between the times T0and T1.

The switching voltage regulator202switches from the first switching phase to the second switching phase at the time T2. At the time T2, the PFET P1is deactivated and the NFET N1is activated by the switching signals IN1and IN2, respectively, and the NFET N2remains activated. Therefore, the input current IINceases, and the current ILflows from the low-voltage rail, through the NFET N1, through the inductor L1, and through the NFET N2. Thus, in the example ofFIG.3, the current ILis demonstrated as decreasing from the amplitude IL2to an amplitude IL3at a time T3, with the amplitude IL3being less than the amplitude IL1. At the time T3, the NFET N2is deactivated by the switching signal OUT1and the NFET N3is activated by the switching signal OUT2. Therefore, the current ILflows from the low-voltage rail, through the NFET N1, through the inductor L1, and through the NFET N3. Thus, in the example ofFIG.3, the current ILis demonstrated as decreasing from the amplitude IL3to the initial amplitude IL0at a time T4. The second switching phase concludes at the time T4. The first and second switching phases can define a switching period, such that a next switching period is shown in the example ofFIG.3as beginning at the time T4. For example, an idle time at which the current ILremains at zero can occur between switching periods, such as during deactivation of the power supply circuit200or in a discontinuous mode of operation of the power supply circuit200.

The second timing diagram304is arranged similar to the first timing diagram302, and can define a boost mode of operation of the power supply circuit200. As an example, the boost mode of operation is based on a variation in topology of the power supply circuit200to vary the amplitude of the current IL. The second timing diagram304is therefore shown to demonstrate that the principle of operation of the power supply circuit200, as described herein, is applicable to any of a variety of inductor current waveforms.

Referring back to the example ofFIG.2, the power supply circuit200includes a current regulator system208that is configured to regulate an amplitude of the input current IIN. As described above, the input current IINcan be drawn from a battery, such that monitoring and regulating the amplitude of the input current IINcan result in an extension of the operational life of the battery. In the example ofFIG.2, the current regulator system208includes a transconductance amplifier210that has a first input that is coupled to the switching node204through a first switch SW1controlled by a switching signal S1and to the input voltage VINthrough a second switch SW2controlled by a switching signal S2. The transconductance amplifier210also has a second input that is coupled to the input voltage VINthrough a third switch SW3controlled by a switching signal S3and to a third switching node212. The third switching node212is coupled to the input voltage VINthrough a PFET P2. As an example, the PFET P2is a replica switch with respect to the PFET P1, such that the PFET P2has a channel width that is scaled-down by a factor of K relative to the PFET P1. In the example ofFIG.2, the PFET P2is activated by the switching signal IN1, such that the PFET P2is activated concurrently with the PFET P1to generate a charging current ICHthat has an amplitude approximately equal to the amplitude of the input current IINdivided by K (e.g., ICH=IIN/K).

The transconductance amplifier210is configured to generate a signal CT that is provided to a PFET P3to provide the charging current ICHto a sampling node214through a switch SW4controlled by a switching signal S4. A sampling capacitor CSinterconnects the sampling node214and a node220. The sampling node214and the node220are also coupled by a switch SW5that is controlled by a switching signal S5. A voltage source218provides an offset voltage VOFFto the node220. Additionally, a switch SW6that is controlled by a switching signal S6interconnects the sampling node214and a node216, and a switch SW7that is controlled by a switching signal S7interconnects the nodes216and220.

The current regulator system208also includes a current source222that is coupled to the sampling node214through a switch SW8that is controlled by a switching signal S8. The current source222be the reference current generator108in the example ofFIG.1. For example, the current source222is provided at an external pin of the associated IC on which the power supply circuit200is fabricated (e.g., as a grounded resistor). Therefore, when the switch SW8is closed, the current source222is configured to conduct the reference current IREFfrom the sampling node214, and thus from the sampling capacitor CS. For example, the offset voltage VOFF(e.g., approximately 350 mV) provides sufficient headroom for the reference current IREF. As described above, the reference current IREFcan have an amplitude that is proportional to a maximum average amplitude setpoint of the input current IINover a switching period of the switching voltage regulator202. For example, the proportionality of the reference current IREFto the maximum average amplitude setpoint of the input current IINis likewise scaled by the factor of K, and thus the proportionality constant as the charging current ICH. As an example, the reference current IREFhas an amplitude that is expressed as follows:
IREF=ITAR/KEquation 1Where: ITARis the maximum average amplitude setpoint of the input current IINover a switching period of the switching voltage regulator202.

The current regulator system208also includes a sampling comparator224that has inputs at the nodes216and220. The sampling comparator224is therefore configured to monitor the sampling voltage VSMPLon the sampling capacitor CSwhen the switch SW6is closed (e.g., based on common mode operation defined by the offset voltage VOFF). The sampling comparator224can generate a first comparison signal CMP1responsive to determining that the sampling voltage VSMPLhas an amplitude of approximately zero.

The power supply circuit200further includes a switch controller226. The switch controller226includes a state machine228. The first comparison signal CMP1is provided to the state machine228that also receives a second comparison signal CMP2from a reference comparator230. In the example ofFIG.2, the reference comparator230is configured to compare the output voltage VOUTwith a fixed reference voltage VREF. Based on the comparison signals CMP1and CMP2, the state machine228can generate the switching signals IN, OUT, and S that are provided to the respective PFETs P1through P3, the NFETs N1through N3, and the switches SW1through SW8. Therefore, the state machine228can define the first and second switching phases of the switching voltage regulator202, and therefore the switching period of the switching voltage regulator202. The state machine228can also provide the controls for operating the switches SW1through SW8to provide the operation of the current regulator system208in each of the first and second switching phases to regulate the amplitude of the input current IIN.

The example power supply circuit200can be configured differently than shown in the example ofFIG.2. For example, the switching voltage regulator202is not limited to the arrangement of the high and low-side switches P1, N1, N2, and N3. As one example, the PFET P1, and by extension the replica PFET P2, is arranged as N-channel transistors instead.

Operation of the power supply circuit200is shown in greater detail inFIGS.4-6.FIG.4is another example of timing diagrams. The timing diagrams include a first timing diagram402that shows inductor current ILplotted as a function of time for a converter operating in buck mode. The first timing diagram402is therefore the same as the first timing diagram302in the example ofFIG.3. A second timing diagram404is the sampling voltage VSMPLplotted as a function of time.FIG.5is an example of a schematic electrical circuit diagram500of current flow in in the power supply circuit200in the first switching phase of the switching voltage regulator202, andFIG.6is an example of a schematic electrical circuit diagram600of current flow in in the power supply circuit200in the second switching phase of the switching voltage regulator202. Accordingly, reference is to be made to the examples ofFIGS.4-6in the following description.

In the first timing diagram402, the switching voltage regulator202begins the first switching phase at a time T0. At the time T0, the PFET P1and the NFET N3are activated by the switching signals IN1and OUT2, respectively. Additionally, with reference to the example ofFIG.5, the switches SW1, SW4, SW7, and SW8are closed by the switching signals S1, S4, S7, and S8, respectively. Therefore, the input current IINflows from the input voltage VIN, through the PFET P1, and through the inductor L1as the current IL, and through the NFET N3. Thus, in the example ofFIG.4, the current ILis demonstrated as increasing from an amplitude of IL0to an amplitude IL1.

At the time T1, the NFET N3is deactivated by the switching signal OUT2and the NFET N2is activated by the switching signal OUT1. Therefore, the input current IINflows from the input voltage VIN, through the PFET P1, and through the inductor L1as the current IL, and through the NFET N2. Thus, the current ILcontinues to increase in amplitude from the time T1to the time T2during the first switching phase of the switching voltage regulator202. Additionally, with further reference to the example ofFIG.5, during the first switching phase defined between the times T0and T2, the input current IINis emulated by the charging current ICHthrough the replica PFET P2, based on the matched PFETs P1and P2concurrently activated by the switching signal IN1, with the charging current ICHhaving a scaled amplitude approximately equal to the amplitude of the input current IINdivided by the channel-width scale factor K (e.g., ICH=IIN/K).

Because of the closure of the switch SW1, the transconductance amplifier210receives an approximately equal voltage at each of the inputs at the switching node204and the node212due to the high gain of transconductance amplifier210. The transconductance amplifier210can be configured as a high bandwidth transconductance amplifier210to track the slope of the current IL(e.g., the input current IINduring the first switching phase of the switching voltage regulator202), and can be configured with low offset to measure the current ILas absolute, as opposed to relative. Low offset can be implemented, for example, by providing trimming, calibrating, or chopping of the transconductance amplifier210, or providing auto-zero techniques using switches SW2and SW3, as described in greater detail herein.

The transconductance amplifier210provides a control signal CT to the PFET P3to conduct the charging current ICHthrough the PFET P3and through the switch SW4to the sampling node214. While the charging current ICHis provided to the sampling node214, based on the closure of the switch SW8, the reference current IREFflows from the sampling node214. As a result, a sampling current VSMPLis provided through the sampling capacitor CS. The current VSMPLtherefore has an amplitude that is equal to the charging current ICHminus the reference current IREF. Thus, the sampling current VSMPLbegins charging the sampling capacitor CSto increase the amplitude of the sampling voltage VSMPL. Because the switch SW6is open and the switch SW7is closed during the first switching phase of the switching voltage regulator202, the sampling comparator224is not monitoring the sampling voltage VSMPL. Therefore, the first comparison signal CMP1is asserted at a logic-high state.

Referring back to the example ofFIG.4, the switching voltage regulator202switches from the first switching phase to the second switching phase at the time T2. At the time T2, the PFET P1is deactivated and the NFET N1is activated by the switching signals IN1and IN2, respectively, and the NFET N2remains activated. Additionally, with reference to the example ofFIG.6, the switches SW1, SW4, and SW7are opened by the switching signals S1, S4, and S7, respectively, and the switches SW2, SW3, and SW6are closed by the switching signals S2, S3, and S6, respectively. The switch SW8remains closed during the second switching phase of the switching voltage regulator202. Therefore, the input current IINceases, and the current ILflows from the low-voltage rail, through the NFET N1, through the inductor L1, and through the NFET N2. Thus, in the example ofFIG.4, the current ILis demonstrated as decreasing from the amplitude IL2to an amplitude IL3at a time T3. At the time T3, the NFET N2is deactivated by the switching signal OUT1and the NFET N3is activated by the switching signal OUT2. Therefore, the current ILflows from the low-voltage rail, through the NFET N1, through the inductor L1, and through the NFET N3. Thus, in the example ofFIG.4, the current ILis demonstrated as decreasing from the amplitude IL3to the initial amplitude IL0at a time T4.

With reference to the example ofFIG.6, in the second switching phase of the switching voltage regulator202, the PFETs P1and P2are both deactivated, which ceases the flow of the input current IIN, and by extension, the charging current ICH. The switches SW2and SW3are closed to provide zeroing of the transconductance amplifier210. Because the charging current ICHceases to flow, the charging current ICHis no longer provided to the sampling node214. However, the switch SW8is still closed in the second switching phase of the switching voltage regulator202, resulting in the reference current IREFcontinuing to draw charge from the sampling capacitor CS. As a result, the sampling voltage VSMPLdecreases beginning at the time T2during the second switching phase of the switching voltage regulator202.

Due to the closure of the switch SW6, the sampling comparator224compares the sampling voltage VSMPLat the sampling node214with the voltage at the node220, and therefore monitors the voltage across the sampling capacitor CS. Responsive to the sampling voltage VSMPLhaving an amplitude of approximately zero, and thus the sampling capacitor CShas approximately zero charge, the sampling comparator224can de-assert the first comparison signal CMP1. As described herein, a zero amplitude of the sampling voltage VSMPLrefers to an approximately zero amplitude across the sampling capacitor CS, based on the sampling voltage VSMPLbeing referenced to the offset voltage VOFFat the node220. The zero amplitude of the sampling voltage VSMPLcan also refer to an approximately negative amplitude of the sampling voltage VSMPLbased on the sampling capacitor CS, such that the inverting input of the sampling comparator224has a greater voltage amplitude than the sampling voltage VSMPLat the non-inverting input of the sampling comparator224.

Responsive to the de-assertion of the first comparison signal CMP1, and responsive to a logic-low amplitude of the second comparison signal CMP2as provided by the reference comparator230(e.g., responsive to the reference voltage VREFbeing greater than the output voltage VOUT), the state machine228can change the state of the switching signals IN, OUT, and S. Therefore, the state machine228can switch the switching voltage regulator202from the second switching phase to the first switching phase, and thus the beginning of a next switching period. Therefore, the state machine228can dictate the time duration of the switching periods of the switching voltage regulator202based on the amplitude of the input current IINrelative to the reference current IREF(e.g., based on the sampling voltage VSMPL) to regulate the amplitude of the input current IIN.

As an example, upon completion of a switching period, the state machine228implements an idle (e.g., sleep) mode for the power supply circuit200, such as based on a deactivation mode for the power supply circuit200or for a discontinuous mode of operation for the switching voltage regulator202. For example, during an idle mode, the switch SW8is opened by the switching signal S8to disconnect the reference voltage IREFfrom the sampling capacitor CS. Additionally, the switches SW2and SW3can remain closed to provide zeroing of the transconductance amplifier210, the switch SW5can be closed by the switching signal S5to provide zeroing of the sampling capacitor CS, and the switch SW6can remain closed to latch the first comparison signal CMP1provided by the sampling comparator224. The state machine228therefore can await a change in state of the second comparison signal CMP2to begin a next switching period.

Because the power supply circuit200provides switching times based on the amplitude of the input current IINrelative to the reference current IREF(e.g., based on the sampling voltage VSMPL), the power supply circuit200can regulate the amplitude of the input current IINin a manner that is more effective than input current regulation in a typical power supply circuit. For example, as described above, the current regulation of the power supply circuit200is implemented for more complex waveforms of the inductor current IL, as well as non-zero initial amplitudes of the inductor current IL, as opposed to being limited to triangular inductor current waveforms with an initial zero amplitude, as is the case for a typical power supply circuit. Additionally, the power supply circuit200provides real-time measurement of the input current IINduring each cycle of the switching voltage regulator202, and thus an actual peak amplitude of the inductor current IL, as opposed to regulating the input current based on a fixed peak current amplitude estimate as is provided in a typical power supply circuit. Furthermore, a typical power supply circuit requires multiple capacitors for comparing multiple charges (e.g., a charge transmitted from the input and a charge of a desired average input current) to perform input current regulation. The power supply circuit200includes only a single capacitor for current regulation (e.g., the sampling capacitor CS), which can provide for a more compact circuit and remove the requirement for matching between two or more capacitors. Accordingly, the input current regulation provided by the power supply circuit200can be substantially more effective than input current regulation of a typical power supply circuit.

FIG.7is another example of a schematic electrical circuit diagram of a power supply circuit700. The power supply circuit700can be implemented in any of a variety of wireless electronic devices, such as laptop computers, tablet computers, smart phones, or any of a variety of other electronic devices. The power supply circuit700is configured to generate an output voltage VOUTfrom an input voltage V. The power supply circuit700can be the power supply system100in the example ofFIG.1. Therefore, the description of the example ofFIG.7also refers toFIG.1. The power supply circuit700in the example ofFIG.7is provided as another example of the current regulation technique that implements an open-loop topology for a transconductance amplifier (as described in greater detail herein), as opposed to the closed-loop topology for the transconductance amplifier210in the example ofFIG.2. Therefore, the power supply circuit700need not require stability compensation resulting in support of a high slope of the inductor current ILbased on a smaller inductance of the inductor L1.

The power supply circuit700includes a switching voltage regulator702. The switching voltage regulator702includes a high-side switch, shown as a PFET P1, a low-side switch, shown as an NFET N1, a first output switch, shown as an NFET N2, and a second output switch, shown as an NFET N3. The PFET P1interconnects the input voltage VINat a source and a switching node704at a drain, and the NFET N1interconnects the switching node704at a drain and a low-voltage rail, shown in the example ofFIG.7as ground, at a source. The NFET N2interconnects the output voltage VOUTat a drain and a switching node706at a source, and the NFET N3interconnects the switching node706at a drain and the low-voltage rail at a source. An inductor L1interconnects the switching nodes704and706and is configured to conduct a current IL.

The PFET P1is controlled by a switching signal IN1, the NFET N1is controlled by a switching signal IN2, the NFET N2is controlled by a switching signal OUT1, and the NFET N3is controlled by a switching signal OUT2. The activation of the FETs P1, N1, N2, and N3in a sequence provides the current ILthrough the inductor L1in switching phases defined by the switching signals IN1, IN2, OUT1, and OUT2, respectively. For example, the activation of the PFET P1provides the input current IINto flow from the input voltage VINto the switching node704during the first switching phase based on the switching signal IN1, such that the current ILis approximately equal to the input current IINduring the first switching phase of the switching voltage regulator702. During the second switching phase of the switching voltage regulator702, the PFET P1is deactivated and the NFET N1is activated by the switching signal IN2to conduct the current ILfrom the low-voltage rail through the inductor L1. Therefore, the switching voltage regulator702operates substantially the same as the switching voltage regulator202in the example ofFIG.2.

The power supply circuit700also includes a current regulator system708that is configured to regulate an amplitude of the input current IIN. In the example ofFIG.7, the current regulator system708includes a first transconductance amplifier710that has a first input that is coupled to the switching node704through a first switch SW1controlled by a switching signal S1and to the input voltage VINthrough a second switch SW2controlled by a switching signal S2. The first transconductance amplifier710also has a second input that is coupled to the input voltage VIN. The current regulator system708also includes a second transconductance amplifier712that has a first input that is coupled to a node714and to the input voltage VINthrough a switch SW3controlled by a switching signal S3. The first and second transconductance amplifiers710and712can be fabricated approximately identically, and can therefore have an approximately equal transconductance (GM) factor. The second transconductance amplifier712also has a second input that is coupled to the input voltage VIN. The node714is coupled to the input voltage VINthrough a PFET P2. As an example, the PFET P2is a replica switch with respect to the PFET P1, such that the PFET P2has a channel width that is scaled-down by a factor of K relative to the PFET P1.

In the example ofFIG.7, the PFET P2is activated by the switching signal IN1, such that the PFET P2is activated concurrently with the PFET P1to conduct the reference current IREFthat is generated from a current source716through a switch SW4that is controlled by a switching signal S4. The current source716can be the reference current generator108in the example ofFIG.1. For example, the current source716is provided at an external pin of the associated IC on which the power supply circuit700is fabricated (e.g., as a grounded resistor). Therefore, when the switch SW4is closed, the current source716is configured to conduct the reference current IREFfrom the input voltage VINand through the PFET P2. As described above, the reference current IREFhas an amplitude that is proportional to a maximum average amplitude setpoint of the input current IINof the switching voltage regulator702. For example, the proportionality of the reference current IREFto the maximum average amplitude setpoint of the input current IIN(expressed as ITAR) is likewise scaled by the factor of K, as provided above in Equation 1.

The first transconductance amplifier710is configured to generate a charging current ICHthat is provided to a sampling node718through a switch SW5controlled by a switching signal S5. For example, the charging current ICHhas an amplitude that is expressed as follows:
ICH=GM*IIN*RDSONEquation 2Where: GM is the transconductance of the first transconductance amplifier710; RDSONis the activation resistance of the PFET P1.
Additionally, the second transconductance amplifier712is configured to generate a current IRthat is provided through a switch SW6that is controlled by a switching signal S6and through a diode-connected NFET N4. As an example, in the example ofFIG.7, the current IRhas an amplitude that is expressed as follows:
IR=GM*ITAR*K*RDSONEquation 3Where: GM is the transconductance of the second transconductance amplifier712, which is approximately equal to the transconductance of the first transconductance amplifier710;K*RDSONis the activation resistance of the PFET P2, which is approximately equal to K-times the activation resistance of the PFET P1.

The diode-connected NFET N4has a gate and drain that are coupled to a sample and hold capacitor C1and a gate of an NFET N5through a switch SW7that is controlled by a switching signal S7. Therefore, the NFETs N4and N5are arranged as a current mirror, with the current IRbeing provided to the capacitor C1when the switch SW7is closed to charge the capacitor C1. The voltage V1on the capacitor C1thus provides an activation voltage for the NFET N5to mirror the current IRthrough the NFET N5. Therefore, the NFET N5likewise conducts the current IR.

Similar to the power supply circuit200, the sampling node718is coupled to a sampling capacitor CSand has a sampling voltage VSMPL. The sampling capacitor CSinterconnects the sampling node718and a node720. The sampling node718and the node720are also coupled by a switch SW8that is controlled by a switching signal S8. A voltage source722provides an offset voltage VOFFto the node720. Additionally, a switch SW9that is controlled by a switching signal S9interconnects the sampling node718and a node724, and a switch SW10that is controlled by a switching signal S10interconnects the nodes720and724. In the example ofFIG.7, the NFET N5is coupled to the sampling node718at a drain. Therefore, the NFET N5is configured to conduct the current IRfrom the sampling node718, and thus from the sampling capacitor CS. For example, the offset voltage VOFF(e.g., approximately 350 mV) provides sufficient headroom for the current IR.

The current regulator system708includes a sampling comparator726that has inputs at the nodes724and720. Therefore, the sampling comparator726is configured to monitor the sampling voltage VSMPLon the sampling capacitor CSwhen the switch SW9is closed (e.g., based on common mode operation defined by the offset voltage VOFF). The sampling comparator726can generate a first comparison signal CMP1responsive to determining that the sampling voltage VSMPLhas an amplitude of approximately zero.

The power supply circuit700further includes a switch controller728that includes a state machine730. The first comparison signal CMP1is provided to the state machine730that also receives a second comparison signal CMP2from a reference comparator732. In the example ofFIG.7, the reference comparator732is configured to compare the output voltage VOUTwith a fixed reference voltage VREF. Based on the comparison signals CMP1and CMP2, the state machine730can generate the switching signals IN, OUT, and S that are provided to the respective PFETs P1through P3, the NFETs N1through N3, and the switches SW1through SW10, respectively. Therefore, the state machine730can define the first and second switching phases of the switching voltage regulator702, and therefore the switching period of the switching voltage regulator702. The state machine730can also provide the controls for operating the switches SW1through SW10to provide the operation of the current regulator system708in each of the first and second switching phases to regulate the amplitude of the input current IIN.

The power supply circuit700is not limited to the example shown inFIG.7. For example, the switching voltage regulator702is not limited to the arrangement of the high and low-side switches P1, N1, N2, and N3. As one example, the PFET P1, and by extension the replica PFET P2, is arranged as N-channel transistors instead.

Operation of the power supply circuit700is shown in greater detail inFIGS.4,8, and9.FIG.8is another example of a schematic electrical circuit diagram800of current flow in the power supply circuit700in the first switching phase of the switching voltage regulator702, andFIG.9is another example of a schematic electrical circuit diagram900of current flow in the power supply circuit700in the second switching phase of the switching voltage regulator702. Accordingly, the following description also refers to the examples ofFIGS.4,8, and9.

In the first timing diagram402, the switching voltage regulator702begins the first switching phase at a time T0. At the time T0, the PFET P1and the NFET N3are activated by the switching signals IN1and OUT2, respectively. Additionally, with reference to the example ofFIG.8, the switches SW1, SW4, SW5, SW6, SW7, and SW10are closed by the switching signals S1, S4, S5, S6, S7, and S10, respectively. Therefore, the input current IINflows from the input voltage VIN, through the PFET P1, and through the inductor L1as the current IL, and through the NFET N3. Thus, in the example ofFIG.4, the current ILis demonstrated as increasing from an amplitude IL0to an amplitude IL1.

At the time T1, the NFET N3is deactivated by the switching signal OUT2and the NFET N2is activated by the switching signal OUT1. Therefore, the input current IINflows from the input voltage VIN, through the PFET P1, and through the inductor L1as the current IL, and through the NFET N2. Thus, the current ILcontinues to increase in amplitude from the time T1to the time T2during the first switching phase of the switching voltage regulator702. Additionally, with further reference to the example ofFIG.8, during the first switching phase defined between the times T0and T2, the input current IINflows through the PFET P1and the reference current flows through the PFET P2based on the matched PFETs P1and P2concurrently activated by the switching signal IN1. The first transconductance amplifier710generates the charging current ICHbased on the input current IINand having an amplitude defined by Equation 2 above based on the closure of the switch SW1. Similarly, the second transconductance amplifier712generates the current IRbased on the reference current and having an amplitude defined by Equation 3 above based on the closure of the switch SW4.

Based on the closure of the switch SW5, the charging current ICHis provided from the first transconductance amplifier710to the sampling node718. Based on the closure of the switch SW6, the current IRis provided from the second transconductance amplifier712through the NFET N4. The current IRcharges the capacitor C1to provide the voltage V1at the gate of the NFET N5, and the current IRis mirrored from the NFET N4to the NFET N5. As a result, a sampling current VSMPLis provided through the sampling capacitor CS. The current VSMPLtherefore has an amplitude that is equal to the charging current ICHminus the current IR. Thus, the sampling current VSMPLbegins charging the sampling capacitor CSto increase the amplitude of the sampling voltage VSMPL. Because the switch SW9is open and the switch SW10is closed during the first switching phase of the switching voltage regulator702, the sampling comparator726is not monitoring the sampling voltage VSMPL. Therefore, the first comparison signal CMP1is asserted at a logic-high state.

Referring back to the example ofFIG.4, the switching voltage regulator702switches from the first switching phase to the second switching phase at the time T2. At the time T2, the PFET P1is deactivated and the NFET N1is activated by the switching signals IN1and IN2, respectively, and the NFET N2remains activated. Additionally, with reference to the example ofFIG.9, the switches SW1, SW4, SW5, SW6, SW7, and SW10are opened by the switching signals S1, S4, S5, S6, S7, and S10, respectively, and the switches SW2, SW3, and SW9are closed by the switching signals S2, S3, and S9, respectively. Therefore, the input current IINceases, and the current ILflows from the low-voltage rail, through the NFET N1, through the inductor L1, and through the NFET N2. Thus, in the example ofFIG.4, the current ILis demonstrated as decreasing from the amplitude IL2to an amplitude IL3at a time T3. At the time T3, the NFET N2is deactivated by the switching signal OUT1and the NFET N3is activated by the switching signal OUT2. Therefore, the current ILflows from the low-voltage rail, through the NFET N1, through the inductor L1, and through the NFET N3. Thus, in the example ofFIG.4, the current ILis demonstrated as decreasing from the amplitude IL3to the initial IL0at a time T4.

With reference to the example ofFIG.9, in the second switching phase of the switching voltage regulator702, the PFETs P1and P2are both deactivated, which ceases the flow of the input current IIN, and by extension, the reference current IREF. The switches SW2and SW3are closed to provide zeroing of the first and second transconductance amplifiers710and712. Because the charging current ICHceases to flow from the first transconductance amplifier710, the charging current ICHis no longer provided to the sampling node718. Similarly, the current IRceases to flow from the second transconductance amplifier712. However, the sampled voltage V1across the capacitor C1continues to provide activation of the NFET N5in the second switching phase of the switching voltage regulator702, resulting in the current IRcontinuing to draw charge from the sampling capacitor CS. As a result, the sampling voltage VSMPLdecreases beginning at the time T2during the second switching phase of the switching voltage regulator702.

Due to the closure of the switch SW9, the sampling comparator726compares the sampling voltage VSMPLat the sampling node718with the voltage at the node720, and therefore monitors the voltage across the sampling capacitor CS. Responsive to the sampling voltage VSMPLhaving an amplitude of approximately zero, and thus the sampling capacitor CShas approximately zero charge, the sampling comparator726can de-assert the first comparison signal CMP1. Responsive to the de-assertion of the first comparison signal CMP1, and responsive to a logic-low amplitude of the second comparison signal CMP2as provided by the reference comparator732(e.g., responsive to the reference voltage VREFbeing greater than the output voltage VOUT), the state machine730can change the state of the switching signals IN, OUT, and S. Therefore, the state machine730can switch the switching voltage regulator702from the second switching phase to the first switching phase, and thus the beginning of a next switching period. Therefore, the state machine730can dictate the time duration of the switching periods of the switching voltage regulator702based on the amplitude of the input current IINrelative to the reference current IREF(e.g., based on the sampling voltage VSMPL) to regulate the amplitude of the input current IIN.

Similar to as described above, upon completion of a switching period, the state machine730can implement an idle (e.g., sleep) mode for the power supply circuit700, such as based on a deactivation mode for the power supply circuit700or for a discontinuous mode of operation for the switching voltage regulator702. For example, during an idle mode, the switches SW2and SW3remains closed to provide zeroing of the transconductance amplifiers710and712, the switch SW8is closed by the switching signal S8to provide zeroing of the sampling capacitor CS, and the switch SW9remains closed to provide zeroing of the sampling comparator726. The state machine730therefore can await a change in state of the second comparison signal CMP2to begin a next switching period.

FIG.10is another example of a schematic electrical circuit diagram showing current flow in a power supply circuit1000. The power supply circuit1000can be implemented in any of a variety of wireless electronic devices, such as laptop computers, tablet computers, smart phones, or any of a variety of other electronic devices. The power supply circuit1000is configured to generate an output voltage VOUTfrom an input voltage VINThe power supply circuit1000can be the power supply system100in the example ofFIG.1. Therefore, the description ofFIG.10also refers toFIG.1. The power supply circuit1000in the example ofFIG.10provides another example of the current regulation technique that implements estimated values for the peak and valley amplitudes of the inductor current IL. For example, the estimates for the peak and valley amplitudes of the inductor current ILis calculated in any of a variety of ways, such as the operating modes of the power supply circuit1000, the relative amplitudes of the input voltage VINand the output voltage VOUT, duty-cycles, factory testing/calibration, or any of a variety of methods.

The power supply circuit1000includes a switching voltage regulator1002. The switching voltage regulator1002includes a high-side switch, shown as a PFET P1, a low-side switch, shown as an NFET N1, a first output switch, shown as an NFET N2, and a second output switch, shown as an NFET N3. The PFET P1interconnects the input voltage VINat a source and a switching node1004at a drain, and the NFET N1interconnects the switching node1004at a drain and a low-voltage rail, shown in the example ofFIG.10as ground, at a source. The NFET N2interconnects the output voltage VOUTat a drain and a switching node1006at a source, and the NFET N3interconnects the switching node1006at a drain and the low-voltage rail at a source. An inductor L1interconnects the switching nodes1004and1006and is configured to conduct a current IL.

The PFET P1is controlled by a switching signal IN1, the NFET N1is controlled by a switching signal IN2, the NFET N2is controlled by a switching signal OUT1, and the NFET N3is controlled by a switching signal OUT2. The activation of the FETs P1, N1, N2, and N3in a sequence provides the current ILthrough the inductor L1in switching phases defined by the switching signals IN1, IN2, OUT1, and OUT2, respectively. For example, the activation of the PFET P1provides the input current IINto flow from the input voltage VINto the switching node1004during the first switching phase based on the switching signal IN1, such that the current ILis approximately equal to the input current IINduring the first switching phase of the switching voltage regulator1002. During the second switching phase of the switching voltage regulator1002, the PFET P1is deactivated and the NFET N1is activated by the switching signal IN2to conduct the current ILfrom the low-voltage rail through the inductor L1. Therefore, the switching voltage regulator1002operates substantially the same as the switching voltage regulator202in the example ofFIG.2.

The power supply circuit1000also includes a current regulator system1008that is configured to regulate an amplitude of the input current IIN. In the example ofFIG.10, the current regulator system1008includes a first current source1010that generates a first current I1, a second current source1012that generates a second current I2, and a third current source1014that generates a third current I3. As an example, the currents I1, I2, and I3, in combination, are the charging current ICHduring the first switching phase, as described in greater detail herein. The first current source1010interconnects the input voltage VINand a switch SW1that is controlled by a switching signal S1, the second current source1012interconnects the input voltage VINand a switch SW2that is controlled by a switching signal S2, and the third current source1014interconnects the input voltage VINand a switch SW3that is controlled by a first switching signal S3. The parallel arrangements of the current source1010and the switch SW1, the current source1012and the switch SW2, and the current source1014and the switch SW3are arranged in series with a switch SW4that is controlled by a switching signal S4.

The switch SW4is coupled to a sampling node1016. A sampling capacitor CSinterconnects the sampling node1016and a node1018. The sampling node1016and the node1018are also coupled by a switch SW5that is controlled by a switching signal S5. A voltage source1020provides an offset voltage VOFFto the node1018. Additionally, a switch SW6that is controlled by a switching signal S6interconnects the sampling node1016and a node1022, and a switch SW7that is controlled by a switching signal S7interconnects the nodes1018and1022.

The current regulator system1008also includes a current source1024that is coupled to the sampling node1016through a switch SW8that is controlled by a switching signal S8. The current source1024can be the reference current generator108in the example ofFIG.1. For example, the current source1024is provided at an external pin of the associated ICon which the power supply circuit1000is fabricated (e.g., as a grounded resistor). Therefore, when the switch SW8is closed, the current source1024is configured to conduct the reference current IREFfrom the sampling node1016, and thus from the sampling capacitor CS. For example, the offset voltage VOFF(e.g., approximately 350 mV) provides sufficient headroom for the reference current IREF. As described above, the reference current IREFcan have an amplitude that is proportional to a maximum average amplitude setpoint of the input current IINof the switching voltage regulator1002. For example, the proportionality of the reference current IREFto the maximum average amplitude setpoint of the input current IIN(expressed as ITAR) is likewise scaled by the factor of K, as provided above in Equation 1. In addition, the current regulator system1008includes a current source1026that is coupled to the sampling node1016through a switch SW9that is controlled by a switching signal S9. The current source1026generates the current I3, which is approximately equal to the current I3generated by the current source1014described above.

The switching voltage regulator1008includes a sampling comparator1028that has inputs at the nodes1018and1022. The sampling comparator1028is therefore configured to monitor the sampling voltage VSMPLon the sampling capacitor CSwhen the switch SW6is closed (e.g., based on common mode operation defined by the offset voltage VOFF). The sampling comparator1028can generate a first comparison signal CMP1responsive to determining that the sampling voltage VSMPLhas an amplitude of approximately zero.

The power supply circuit1000further includes a switch controller1030that includes a state machine1032. The first comparison signal CMP1is provided to the state machine1032that also receives a second comparison signal CMP2from a reference comparator1034. In the example ofFIG.10, the reference comparator1034is configured to compare the output voltage VOUTwith a fixed reference voltage VRFFBased on the comparison signals CMP1and CMP2, the state machine1032can generate the switching signals IN, OUT, and S that are provided to the respective PFET P1, the NFETs N1through N3, and the switches SW1through SW9, respectively. Therefore, the state machine1032can define the first and second switching phases of the switching voltage regulator1002, and therefore the switching period of the switching voltage regulator1002. The state machine1032can also provide the controls for operating the switches SW1through SW9to provide the operation of the current regulator system1008in each of the first and second switching phases to regulate the amplitude of the input current IIN.

The power supply circuit1000is not limited to the circuit shownFIG.10. For example, the switching voltage regulator1002is not limited to the arrangement of the high and low-side switches P1, N1, N2, and N3. As one example, the PFET P1is arranged as an N-channel transistor instead.

Operation of the power supply circuit1000is shown in greater detail inFIGS.4and11-13.FIG.11is another example of a schematic electrical circuit diagram1100of current flow in the power supply circuit1000in the first switching phase of the switching voltage regulator1002,FIG.12is another example of a schematic electrical circuit diagram1200of current flow in the power supply circuit1000in the first switching phase of the switching voltage regulator1002, andFIG.13is another example of a schematic electrical circuit diagram1300of current flow in the power supply circuit1000in the second switching phase of the switching voltage regulator1002. Accordingly, the description ofFIG.11also refers to the examples ofFIGS.4and11-13.

In the first timing diagram402, the switching voltage regulator1002begins the first switching phase at a time T0. At the time T0, the PFET P1and the NFET N3are activated by the switching signals IN1and OUT2, respectively. Therefore, the input current IINflows from the input voltage VIN, through the PFET P1, and through the inductor L1as the current IL, and through the NFET N3. Thus, in the example ofFIG.4, the current ILis demonstrated as increasing from an amplitude of IL0to an amplitude IL1.

Additionally, with reference to the example ofFIG.11, the switches SW1, SW4, SW7, and SW8are closed by the switching signals S1, S4, S7, and S8, respectively, from the time T0to the time T1. Therefore, from the time T0and T1, the current I1flows from the current source1010, through the closed switches SW1and SW4, and to the sampling node1016. While the current I1is provided to the sampling node1016, based on the closure of the switch SW8, the reference current IREFflows from the sampling node1016. As a result, a sampling current VSMPLis provided through the sampling capacitor CS. The current VSMPLtherefore has an amplitude that is equal to the current I1minus the reference current IREF. Thus, the sampling current VSMPLbegins charging the sampling capacitor CSto increase the amplitude of the sampling voltage VSMPLfrom the time T0to the time T1. Because the switch SW6is open and the switch SW7is closed during the first switching phase of the switching voltage regulator1002, the sampling comparator1028is not monitoring the sampling voltage VSMPL. Therefore, the first comparison signal CMP1is asserted at a logic-high state.

Referring to the example ofFIG.4, at the time T1, the NFET N3is deactivated by the switching signal OUT2and the NFET N2is activated by the switching signal OUT1. Therefore, the input current IINflows from the input voltage VIN, through the PFET P1, and through the inductor L1as the current IL, and through the NFET N2. Thus, the current ILcontinues to increase in amplitude from the time T1to the time T2during the first switching phase of the switching voltage regulator1002. Additionally, with reference to the example ofFIG.12, the switch SW1is opened by the switching signal S1, the switches SW4, SW7, and SW8remain closed, the switch SW2is closed by the switching signal S2, and one of the switches SW3and SW9is closed by the respective one of the switching signals S3and S9, depending on the operational mode of the switching voltage regulator1002.

For example, for the buck mode operation of the timing diagram402(and the timing diagram302in the example ofFIG.3), the switch SW3is closed. However, for the boost mode operation shown in the timing diagram304in the example ofFIG.3, the switch SW9is closed instead. Therefore, the amplitude of the current I3is added to the amplitude of the current I2at the sampling node1016for a buck mode of operation, or the amplitude of the current I3is subtracted from the amplitude of the current I2in the boost mode of operation. While the example of FIG.12shows both switches SW3and SW9as being concurrently closed, only one of the switches SW3and SW9is closed at a given time, depending on the operational mode of the switching voltage regulator1002. Therefore, the current I1can be the charging current ICHthat is provided to the sampling node1016from the time T0to the time T1, and the combination of the currents I2and I3(additive or subtractive) can be the charging current ICHthat is provided to the sampling node1016from the time T1to the time T2.

Based on the closure of the switch SW4, the charging current ICHis provided to the sampling node1016during the first switching phase of the switching voltage regulator1002. While the charging current ICHis provided to the sampling node1016, based on the closure of the switch SW8, the reference current IREFflows from the sampling node1016. As a result, a sampling current VSMPLis provided through the sampling capacitor CS. The current VSMPLtherefore has an amplitude that is equal to the charging current ICHminus the reference current IREF. Thus, the sampling current VSMPLbegins charging the sampling capacitor CSto increase the amplitude of the sampling voltage VSMPL. Because the switch SW6is open and the switch SW7is closed during the first switching phase of the switching voltage regulator1002, the sampling comparator1028is not monitoring the sampling voltage VSMPL. Therefore, the first comparison signal CMP1is asserted at a logic-high state.

Referring back to the example ofFIG.4, the switching voltage regulator1002switches from the first switching phase to the second switching phase at the time T2. At the time T2, the PFET P1is deactivated and the NFET N1is activated by the switching signals IN1and IN2, respectively, and the NFET N2remains activated. Additionally, with reference to the example ofFIG.13, the switches SW2, SW3, SW9, SW4, and SW7are opened by the switching signals S1, S3, S9, S4, and S7, respectively, and the switch SW6is closed by the switching signal S6. The switch SW8remains closed during the second switching phase of the switching voltage regulator1002. Therefore, the current IINceases, and the current ILflows from the low-voltage rail, through the NFET N1, through the inductor L1, and through the NFET N2. Thus, in the example ofFIG.4, the current ILis demonstrated as decreasing from the amplitude IL2to an amplitude IL3at a time T3. At the time T3, the NFET N2is deactivated by the switching signal OUT1and the NFET N3is activated by the switching signal OUT2. Therefore, the current ILflows from the low-voltage rail, through the NFET N1, through the inductor L1, and through the NFET N3. Thus, in the example ofFIG.4, the current ILis demonstrated as decreasing from the amplitude IL3to the initial amplitude IL0at a time T4.

With reference to the example ofFIG.13, in the second switching phase of the switching voltage regulator1002, the currents I1, I2, and I3cease. Therefore, the charging current ICHceases to flow to the sampling node1016. However, the reference current IREFcontinues to flow from the sampling node1016, resulting in the current IREFcontinuing to draw charge from the sampling capacitor CS. As a result, the sampling voltage VSMPLdecreases beginning at the time T2during the second switching phase of the switching voltage regulator1002.

Due to the closure of the switch SW6, the sampling comparator1028compares the sampling voltage VSMPLat the sampling node1016with the voltage at the node1018, and therefore monitors the voltage across the sampling capacitor CS. Responsive to the sampling voltage VSMPLhaving an amplitude of approximately zero, and thus the sampling capacitor CShas approximately zero charge, the sampling comparator1028can de-assert the first comparison signal CMP1. Responsive to the de-assertion of the first comparison signal CMP1, and responsive to a logic-low amplitude of the second comparison signal CMP2as provided by the reference comparator1034(e.g., responsive to the reference voltage VREFbeing greater than the output voltage VOUT), the state machine1032can change the state of the switching signals IN, OUT, and S. Therefore, the state machine1032can switch the switching voltage regulator1002from the second switching phase to the first switching phase, and thus the beginning of a next switching period. Therefore, the state machine1032can dictate the time duration of the switching periods of the switching voltage regulator1002based on the amplitude of the input current IINrelative to the reference current IREF(e.g., based on the sampling voltage VSMPL) to regulate the amplitude of the input current IIN.

Similar to as described above, upon completion of a switching period, the state machine1032can implement an idle (e.g., sleep) mode for the power supply circuit1000, such as based on a deactivation mode for the power supply circuit1000or for a discontinuous mode of operation for the switching voltage regulator1002. For example, during an idle mode, the switch SW8is opened by the switching signal S8to cease the flow of the reference current IREF, and the switch SW5is closed by the switching signal S5to provide zeroing of the sampling capacitor CS. The switch SW6can remain closed to latch the first comparison signal CMP1provided by the sampling comparator1028. The state machine1032therefore can await a change in state of the second comparison signal CMP2to begin a next switching period.

Accordingly, the examples ofFIGS.7-13describe other examples of a power supply circuit that can regulate the input current IINbased on the amplitude of the input current IINrelative to the reference current IREF(e.g., based on the sampling voltage VSMPL). Therefore, similar to the power supply circuit200, the power supply circuits700and1000can regulate the amplitude of the input current IINin a manner that is more effective than input current regulation in a typical power supply circuit. For example, as described above, the current regulation of the power supply circuits700and1000is implemented for more complex waveforms of the inductor current IL, as well as non-zero initial amplitudes of the inductor current IL. Additionally, the power supply circuit700provides real-time measurement of the input current IINduring each cycle of the switching voltage regulator702, and thus an amplitude of the inductor current IL, in an open-loop manner that negates the need for bandwidth-limiting stability compensation. Alternatively, the power supply circuit1000provides measurement of an estimated amplitude of the input current IINat each cycle of the switching voltage regulator1002to provide for a more simplistic circuit that can achieve superior regulation of the input current IINrelative to a typical power supply circuit. Accordingly, the input current regulation provided by the power supply circuits700and1000can be substantially more effective than input current regulation of a typical power supply circuit.

In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is directly coupled to device B; or (b) in a second example, device A is indirectly coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B, so device B is controlled by device A via the control signal generated by device A.

Also, in this description, a device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. Furthermore, a circuit or device described herein as including certain components may instead be configured to couple to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be configured to couple to at least some of the passive elements and/or the sources to form the described structure, either at a time of manufacture or after a time of manufacture, such as by an end user and/or a third party.