Fuse cutting test circuit, fuse cutting test method, and semiconductor circuit

A fuse cutting test method to test the state of a fuse includes measuring the current flowing through the fuse and determining the fuse to be either broken, or not broken, or in a state therebetween, based on the measured current.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a fuse cutting test circuit, fuse cutting test method, and semiconductor circuit, and in particular relates to a test circuit and test method to confirm in detail the state of fuse cutting in a semiconductor storage device comprising redundant memory cells.

2. Description of the Related Art

In semiconductor storage device manufacturing processes, techniques to replace memory cells in which faults have occurred with redundant memory cells have become essential. As the method of replacement, generally a fuse is broken to perform replacement. There exist both laser beam melting-type fuses, in which the fuse is irradiated by a laser beam from outside to break the wiring, and voltage application-type fuses, in which a high voltage is applied to break the wiring or to destroy an insulating film. As process miniaturization advances and semiconductor storage devices increase in capacity, such techniques are becoming increasingly important, and fuses are being used not only in semiconductor storage devices but also to perform various switching or adjustment of circuit states.

In the above-described techniques, when cutting a fuse which is to be broken, there may be cases in which another fuse which is not to be broken is erroneously broken, as well as cases in which a fuse which is to be broken is not broken completely. For this reason, techniques for performing tests to determine whether a fuse which is to be broken has properly been broken through cutting treatment, and whether fuses which are not to be broken exist properly, are increasing in importance together with the above techniques. Conventional fuse circuits and test methods for such circuits are for example disclosed in Japanese Unexamined Patent Application Publication No. 5-242691.

As described in the above document, among inspections of fuse cutting faults, there is for example a fault mode in high-speed SRAM products which cannot be detected if the power supply is not raised gradually (slow-rise faults). This fault mode occurs when a fuse which should have been broken is not broken completely. Specifically, when a fuse is not broken completely, the fuse functions as a high-resistance. In the circuit which generates logic according to whether the fuse is broken or not broken, the signal in the stage following the fuse becomes unstable.

The circumstances of the above slow-rise fault are explained in further detail usingFIG. 7andFIG. 8.FIG. 7andFIG. 8are circuit diagrams showing the configuration of conventional fuse circuits. In the circuit shown inFIG. 7, the fuse1and a resistance2are connected in series between the power supply VCC and ground, and the potential at the point of connection of the fuse1and resistance2is inverted using an inverter3and output. The NMOS device4is a transistor to prevent floating; the capacitances5and6are used to prevent output of an erroneous signal due to transient operation of the output of the inverter3when the power supply rise is rapid, and these capacitances are Cv and Cg respectively.

FIG. 8is a circuit diagram showing a state in which the fuse1inFIG. 7is broken. After the fuse1has not been completely broken, and is only imperfectly broken, the remaining resistance after cutting of the fuse1is Rfcut, and the remaining compensating resistance of the resistance2is Rg. Cvi and Cgo are parasitic capacitances.

In a circuit such as that ofFIG. 7, when the fuse1is not completely broken, the fuse1is regarded as a high resistance, and it is unclear whether the potential appearing between the fuse1and resistance2will be selected as an “H” or as an “L” potential. For example, as shown inFIG. 9, when the power supply is raised rapidly, the program-circuit contact point (OUT) immediately after power supply input takes on a capacitance-divided potential and the NMOS device4is turned on, so that the signal becomes stable.

To explain in further detail, when the fuse1is not completely broken, the fuse1enters a high-resistance state as explained above, and the potential between the fuse1and resistance2rises via the fuse1. However, if the power supply is raised rapidly, prior to exceeding the threshold at which the potential between the fuse1and resistance2is recognized as “H”, the inverter3operates in a state in which the potential is at “L”, so that the output of the inverter3is “H” and the NMOS device4is turned on. Then the potential IN shown inFIG. 8is grounded, so that the output from the inverter3stabilizes at “H”, and a signal is output indicating that the fuse1is broken.

On the other hand, when more time is taken to raise the power supply level, operation is stabilized substantially when the resistance-divided potential IN at the program-circuit connection point exceeds the threshold, as shown inFIG. 10. In this case, the value “L” indicating that the fuse is not broken, is obtained as the output. This potential is opposite to the expected value “H” indicating that the fuse has been broken.

To explain in further detail, when the fuse1is not completely broken and is in a high-resistance state, the rise in the potential between the fuse1and resistance2via the fuse1is similar to the case of a rapid rise in the power supply level. However, when time is taken to raise the power supply level, time elapses until the inverter3begins operation, and before the inverter3operates the potential IN shown inFIG. 8may in some cases exceed the threshold recognized as “H”. In such cases, the output of the inverter3stabilizes at “L”, and a signal is output indicating that the fuse1is not broken.

In this way, in order to detect incomplete cutting of the fuse1, a test pattern in which time is taken while raising the power supply level (a slow-rise test pattern) is necessary. When a slow-rise test pattern is used, the power supply must be raised in millisecond-order time, and the time required for tests is lengthened. When using a slow-rise test pattern, if the inverter3operates before the potential IN exceeds the threshold recognized as “H”, then the potential IN is grounded, and so a signal is output indicating that the fuse1is broken; hence stable test results are not obtained.

SUMMARY OF THE INVENTION

According to one aspect of the invention, a fuse cutting test method to test the state of a fuse, comprises, measuring the current flowing through the fuse and determining the fuse to be either broken, or not broken, or in a state therebetween, based on the measured.

According to another aspect of the invention, a fuse cutting test circuit, which tests the state of a fuse, comprises a current supply, capable of supplying current at a first current value which, when flowing through the fuse, indicates that the fuse is in the unswitched state, a current comparison circuit, which compares the value of the current flowing through the fuse with the first current value and a current comparison result determination circuit, which outputs a signal indicating the state of the fuse, based on the comparison result of the current comparison circuit. The current comparison result determination circuit outputs a signal indicating that the fuse is in the switched state when no current flows in the fuse, outputs a signal indicating that the fuse is in the unswitched state when the value of the current flowing through the fuse is equal to or greater than the first current, and outputs a signal indicating that the fuse is in an incomplete state when the value of the current flowing through the fuse is neither of the above.

According to another aspect of the invention, a semiconductor circuit, in which the state of the circuit is adjusted by cutting a fuse, comprises a first path, to which the fuse is normally connected and a second path for testing the state of the fuse.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In this invention, an inspection is performed to determine whether the desired fuse is properly cut in fuse cutting to perform switching of a circuit state and the circuit state has been properly switched. In this inspection, not only whether the fuse has been cut or not, but also an incomplete state therebetween can also be detected by inspecting the value of the current flowing through the fuse. As an example of the invention, fuse cutting in order to replace faulty memory cells in a semiconductor storage device with redundant memory cells is described. Hereafter, a state in which a fuse is properly cut, and the corresponding memory cell has been switched, is called a broken state; a state in which a fuse is not cut, and the corresponding memory cell is not switched, is called an unbroken state; and a state in which a fuse is incompletely cut is called an incomplete state.

FIG. 1is a circuit diagram showing a fuse circuit100of this aspect. Similarly to the related art, a fuse101and resistance102are connected in series between the power supply VCC and ground GND. The potential at the point of connection of the fuse101and the resistance102is inverted by an inverter103and is output to the Output terminal. The NMOS device104is a transistor to prevent floating. A PMOS transistor105is connected on the power supply VCC side of the fuse101, and an NMOS transistor106is connected on the ground GND side of the fuse101. A test signal is input to the gate of the PMOS transistor105. The test signal, after inversion by the inverter107, is input to the gate of the NMOS transistor106.

On the other hand, the fuse101is also positioned between an inspection power supply VCC_FUSE and an inspection ground GND_FUSE (path A). That is, the power supply VCC and the inspection power supply VCC_FUSE are connected in parallel with the fuse101, and the ground GND and inspection ground GND_FUSE are connected in parallel with the fuse101. The PMOS transistor109is connected on the side of the inspection power supply VCC_FUSE of the fuse101, and the NMOS transistor110is connected on the side of the inspection ground GND_FUSE of the fuse101. The test signal inverted by the inverter108is input to the gate of the PMOS transistor109, and the test signal inverted by the inverter108, and inverted again by the inverter111, is input to the gate of the NMOS transistor110.

As the test signal, when the circuit shown inFIG. 1is in the normal state “L” is input, and when in the fuse break test state “H” is input. The circuit shown inFIG. 1in the normal state operates between the power supply VCC and ground GND. The circuit in the normal state outputs either an “H” or an “L” signal to the Output terminal, according to whether the fuse is broken or unbroken. On the other hand, when the circuit is in the fuse break test state, operation is between the inspection power supply VCC_FUSE and the inspection ground GND_FUSE (path A inFIG. 1).

In the fuse break test state, by measuring the current flowing in path A, the break state of the fuse101can be determined. That is, in a state in which the fuse101is not broken, the current flowing in path A is maximum, and in a state in which the fuse101is completely broken, either no current flows in path A, or the current is minimum. Normally either one of these two states exists; but in a state in which the fuse101is incompletely broken, the fuse101functions as a large resistance, and so the current flowing in the path A is a value which is above the minimum current, but is smaller than the maximum current.

Hence by measuring and storing in advance the current in path A in the unswitched state of fuse101and in the switched state of fuse101, and comparing these values with the current value in path A during fuse break testing, it is possible to detect not only whether the fuse101is properly broken and in a switched state or whether the fuse101remains properly in the unswitched state, but also whether the fuse101is in an incompletely broken state. In this way, by providing separately a path over which the fuse101is normally used in the circuit and a path over which the state of the fuse101is tested, the state of the fuse101can be tested without being affected by other elements, or with the effects of other elements held to a minimum. Below, fuse break tests are described in detail usingFIG. 2andFIG. 3.

FIG. 2shows a fuse break test circuit of this embodiment. As shown inFIG. 2, the fuse break test circuit of this embodiment has the fuse circuit100shown inFIG. 1, a current comparison circuit201, a weak current source202, a maximum current source203, and a current comparison result determination circuit204. The current comparison circuit201is connected to the terminal of the inspection power supply VCC_FUSE shown inFIG. 1, and the inspection power supply VCC_FUSE is supplied to the fuse circuit100from the terminal connected to the current comparison circuit201.

The current comparison circuit201is selectively connected to the weak current source202and maximum current source203, and compares the current values of the weak current source202or the maximum current source203with the current flowing in path A of the fuse circuit100. The comparison result is outputted to the current comparison result determination circuit204. Here, two current sources are not necessarily required, and a single current source capable of variable current output can be used to obtain the advantageous results of this embodiment. The current comparison result determination circuit204determines the comparison result according to the output signal of the current comparison circuit201, and outputs a signal indicating the state of the fuse101.

The current value of the weak current source202is an extremely weak current value, and is a current value used in determining whether the memory cell corresponding to the fuse101is in the switched state or not. The current comparison circuit201and current comparison result determination circuit204determine the fuse101to be in the broken state when the current flowing in the path A is equal to or less than the current of the weak current source202. That is, when the current flowing in path A is higher than the current of the weak current source202, the fuse101can be determined to be at least not completely broken, but in either a surviving state, or in an incomplete state.

Here, in order to put the memory cell corresponding to the fuse101into the switched state, normally the fuse101is broken, and so current does not flow in the fuse101; hence the weak current source202can have current value zero. However, it is not necessarily required that the fuse101be completely broken; it is sufficient that, in the slow-rise test shown inFIG. 10, the threshold at least be exceeded at which the input-side potential of the inverter103shown inFIG. 1be recognized at “H” before the beginning of operation of the inverter103, in order that problems arising from incomplete breaking of the fuse101not arise.

Hence even when the current value of the weak current source202is the current value flowing in the fuse101in the circuit ofFIG. 1, and the power supply for the current is raised gradually, the current value can still be such that the threshold at which the potential on the input side of the inverter103is recognized as “H” before the beginning of operation of the inverter103is not exceeded.

The current value of the maximum current source203is the current value indicating a state in which the fuse101is not broken and the memory cell corresponding to the fuse101is unswitched. In greater detail, for the potential difference from VCC_FUSE to GND_FUSE, the current is the maximum current flowing over path A, or is a value slightly lower than this current. The current comparison circuit201and the current comparison result determination circuit204determine, based on the fact that the current flowing in the path A is equal to or greater than the current of the maximum current source203, that the fuse101is not broken, but is in a surviving state. That is, when the current flowing in path A is lower than the current of the maximum current source203, the fuse101does not remain in complete condition, and can be judged to be either in the completely broken state, or in an incomplete state.

Here, when the memory cell corresponding to the fuse101is in the unswitched state, the fuse101is not broken, and so the current value of the maximum current source203is as explained above. However, when the power supply level is raised rapidly, at least as shown inFIG. 9, and if the threshold is exceeded at which the potential on the input side of the inverter103shown inFIG. 1is recognized as “H” before the beginning of operation of the inverter103, then the memory cell corresponding to the fuse101is recognized as being in the unswitched state.

Hence the current value of the maximum current source203is the current flowing in the fuse101in the circuit ofFIG. 1, and even when the power supply for the current is raised rapidly, the current value can be made such that the threshold at which the potential on the input side of the inverter103is recognized as “H” before the start of operation of the inverter103is exceeded.

Next, operation in a fuse breaking test is explained usingFIG. 3.FIG. 3is a flowchart showing operation in a fuse breaking test. First, the current comparison circuit201measures the current in the path A of the fuse circuit100(S301). The weak current source202is then selected, and the current of the weak current source202is compared with the current in path A (S302). When the current in path A is lower than the current of the weak current source202, the current comparison circuit201outputs a signal indicating this to the current comparison result determination circuit204, and the current comparison result determination circuit204determines that the fuse101is in the switched state (S303).

When the current in path A is higher than the current of the weak current source202, the current comparison circuit201selects the maximum current source203, and compares the current value of the maximum current source203with the current in path A (S304). When the current in path A is lower than the current value of the maximum current source203, the current comparison circuit201outputs a signal indicating this to the current comparison result determination circuit, and the current comparison result determination circuit204determines the fuse101to be in an incomplete state (S305).

On the other hand, when the current in path A is higher than those of either the weak current source202or of the maximum current source203, the current comparison circuit201outputs a signal indicating this to the current comparison result determination circuit, and the current comparison result determination circuit204determines that the fuse101is in an unswitched state (S306).

In the above explanation, in step S301the current comparison circuit201compares the current value in path A with the currents for each current source after measuring the current value in path A; but the current value of path A can be compared directly with the currents of each of the current sources.

In this way, by measuring the current flowing in the fuse101and comparing the result with current values set in advance, it is possible to detect not only whether the fuse101is broken or surviving or the switched or unswitched state of the memory cell corresponding to the fuse101, but also an incomplete state of the fuse101. Hence testing times are not lengthened, as in the case of tests using slow-rise test patterns as in the technology of the related art.

Further, when using a slow-rise test pattern, test results may be unstable depending on the applied voltage and temperature conditions; but as explained above, by measuring the current flowing through the fuse101, the state of the fuse101can be detected more precisely, and faults due to an incomplete fuse state can be excluded.

Moreover, the test circuit ofFIG. 2can be configured as the internal circuit shown inFIG. 4.FIG. 4shows an example in which, in a semiconductor circuit having a plurality of fuse circuits100, the fuse breaking test circuit ofFIG. 2is incorporated therewithin. As shown inFIG. 4, a plurality of fuse circuits100are connected to the current comparison circuit201via the selector207. The weak current source202and maximum current source203are connected via the selector206to the current comparison circuit201. The output of the current comparison circuit201is output to a current comparison result storage circuit (register)205instead of to the current comparison result determination circuit204.

The current comparison result storage circuit205, selector206and selector207are connected to a sequence controller208. The sequence controller208outputs control signals. That is, switching by the selectors206and207and storage of current comparison results by the current comparison result storage circuit205are controlled by the sequence controller208. Test mode signals indicating automated test entries are input to the sequence controller208.

The test mode signal includes information indicating whether the connection of the fuse101can be switched from the normal path to the path A. The sequence controller208switches the selector207based on information included by the test mode signal, to determine the fuse circuit100for testing. The sequence controller208controls the current comparison result storage circuit205, and for example changes the area for storage of current comparison results within the current comparison result storage circuit205according to the fuse circuit100being tested.

By configuration such an internal circuit, discrimination operations such as that explained inFIG. 3can be performed as background processing for operations where information on the fuse101is not required. By this means, the apparent time required for inspections of uncut fuses101can be eliminated, and the effective testing time can be shortened. Further, by storing test results in the current comparison result storage circuit205, the results of processing performed in the background can be referenced at any time.

As explained above, according to this invention, by measuring the current flowing in a fuse the state of the fuse can be determined, and discrimination of the fuse break state can be performed rapidly and precisely. In this embodiment a case of application to replacement of memory cells in a semiconductor storage device was explained; but in addition to the replacement of memory cells in a semiconductor storage device explained in this aspect, application to trimming of a circuit reference voltage and similar, and to switching or adjustment of a circuit state through fuse breaking, are possible.

In this embodiment, a weak current source202and maximum current source203are used to enable detection of three states of the fuse101, that is, the switched state, the unswitched state, and an incomplete state; but if it is assumed that the fuse101is to be broken, the maximum current source203is not necessary. For example, if the current flowing in the path A is equal to or greater than the current of the weak current source202, then it is determined that the fuse101is not broken properly, and so an operation is again performed to break the fuse101.

Further, with the fuse101in the switched state, if it is clear that current does not flow in the path A, then the weak current source202is not necessary. For example, a determination is first made as to whether current flows in the path A, and if no current flows, it can be determined that the fuse101is in the switched state. If on the other hand current flows in the fuse101, the current value is compared with the current value of the maximum current source203, and by determining which of the two current values is higher, it is possible to judge whether the fuse101is in the unswitched state or in an incomplete state.

Further, as explained inFIG. 1, in this invention a path in which the fuse101is normally used in the circuit, as well as a path for measurement of the current flowing in the fuse101, that is, a path for use in testing the state of the fuse101, are provided separately. In addition to the mode of use in which the state of the fuse is tested by measuring the current flowing in the fuse101as explained in this aspect, this configuration can also be applied to the related art as explained inFIG. 7andFIG. 8. Further, application is also possible in a semiconductor circuit in which the state of the circuit is adjusted by breaking a fuse. Hence in for example the case ofFIG. 7, the state of the fuse1can be tested without being affected by elements other than the fuse1.

Other Embodiments

FIG. 5is a circuit diagram showing another mode of use of the fuse circuit100shown inFIG. 1. In the fuse circuit100shown inFIG. 1, a test signal is used as a signal to render active the path A and as a signal to temporarily cut off the normal path. However, as shown inFIG. 5, the test signal may be used as a signal to render active the path A, and a signal different from the test signal, called a tentative cut signal, may be used to cut off the normal path temporarily. By this means, quasi-cutoff of the fuse101is possible, irregardless of break discrimination for the fuse101.

As shown inFIG. 5, an NMOS transistor105b, PMOS transistor106b, and inverter107bcan be used to render redundant the switch which, in the fuse circuit100ofFIG. 1, had consisted only of the PMOS transistor105or NMOS transistor106. By this means, on/off control of the switch can be performed with greater stability. Such a redundant switch configuration can be applied not only to the PMOS transistor105and NMOS transistor106, but to the PMOS transistor109and NMOS transistor110as well.

In the circuits shown inFIG. 1andFIG. 5, a dedicated power supply is necessary to measure the current in path A, such as the inspection power supply VCC_FUSE and inspection ground GND_FUSE. However, as shown inFIG. 6, by providing a path B parallel to path A between the inspection power supply VCC_FUSE and the inspection ground GND_FUSE, when path A is not used path B can be employed to effectively utilize the inspection power supply VCC_FUSE and inspection ground GND_FUSE.

In greater detail, the PMOS transistor113and NMOS transistor114are connected in series in path B, with a configuration employing a power supply connected between the PMOS transistor113and NMOS transistor114. A test signal is input to the gate of the PMOS transistor113, and the test signal after inversion by the inverter112is input to the gate of the NMOS transistor114, so that path A and path B are switched.

It is apparent that the present invention is not limited to the above embodiment and it may be modified and changed without departing from the scope and spirit of the invention.