Flash memory structure and method for fabricating the same

A flash memory structure comprises a semiconductor substrate having a V-groove, a first doped region positioned in the semiconductor substrate, two second doped regions positioned in the semiconductor substrate and at two sides of the V-groove, a dielectric stack having trapping sites interposed therein positioned on the V-groove, and a conductive layer positioned on the surface of the dielectric stack above the V-groove. A method for forming the V-groove comprises steps of forming a mask layer on the surface of the semiconductor substrate, forming an opening in the mask layer, etching a portion of the semiconductor substrate below the opening to form the V-groove, and removing the mask layer. The semiconductor substrate can be a (100)-oriented silicon substrate, and the V-groove has inclined surface planes with (111) orientation.

BACKGROUND OF THE INVENTION

(A) Field of the Invention

The present invention relates to a flash memory structure and method for fabricating the same, and more particularly, to flash memory structure having a V-groove profile and the method for fabricating the same.

(B) Description of the Related Art

Flash memory has been widely applied to the data storage of digital products such as laptop computers, digital assistants, cell phones, digital cameras, digital recorders, and MP3 players. Recently, a flash memory comprises a silicon-oxide-nitride-oxide-silicon (SONOS) structure, which is widely used in flash memory since it possesses the advantages of a thinner memory cell and a simpler fabrication process.

FIG. 1illustrates a flash memory cell10with a SONOS structure according to the prior art. The flash memory cell10comprises a silicon substrate12, two doped regions14and16, a tunnel oxide layer22, a silicon nitride layer24, a silicon oxide layer26, and a polysilicon layer28. Particularly, the SONOS structure consists of the silicon substrate12, tunnel oxide layer22, the silicon nitride layer24, the silicon oxide layer26, and the polysilicon layer28. While charge-trapping site in the silicon nitride layer24can capture electrons or holes penetrating the tunnel oxide22, the silicon oxide layer26serves to prevent electrons and holes from escaping the silicon nitride layer24to enter into the polysilicon layer28during writing or erasing operations of the flash memory.

When the polysilicon layer28, serving as the gate electrode, is charged to a positive potential, electrons in the silicon substrate12will inject into the silicon nitride layer24. Inversely, a portion of electrons in the silicon nitride layer24will be repulsed to inject into the silicon substrate12to form holes in the silicon nitride layer24when the polysilicon layer28is charged to a negative potential. Electrons and holes trapped in the silicon nitride layer24change the threshold voltage (Vth) of the flash memory cell10, and different threshold voltages represent that the flash memory stores different data bits, i.e., “1” and “0”.

SUMMARY OF THE INVENTION

The objective of the present invention is to provide a flash memory structure having a V-groove profile and the method for fabricating the same, which possesses a higher storage density and better step coverage property.

In order to achieve the above-mentioned objective, one embodiment of the present invention discloses a flash memory structure comprising a semiconductor substrate having a V-groove, a first doped region positioned in the semiconductor substrate and below the V-groove, two second doped regions positioned in the semiconductor substrate and at two sides of the V-groove, a dielectric stack having a plurality of trapping sites positioned at least on the surface of the V-groove, and a conductive layer positioned on the surface of the dielectric stack and above the V-groove. The semiconductor substrate can be a (100)-oriented silicon substrate, and the V-groove has inclined surface planes with (111) orientation.

One embodiment of the dielectric stack comprises a first oxide layer positioned on the surface of the semiconductor substrate, a nitride layer positioned on the surface of the first oxide layer, and a second oxide layer positioned on the surface of the nitride layer, wherein the trapping sites are generated from the nitride layer. Another embodiment of the dielectric stack comprises a first oxide layer positioned on the surface of the semiconductor substrate, a first nitride layer positioned on the surface of the first oxide layer, a silicon-containing layer made of polysilicon or silicon germanium positioned on the surface of the first nitride layer, a second nitride layer positioned on the surface of the silicon-containing layer, and a second oxide layer positioned on the surface of the second nitride layer, wherein the trapping sites are generated from the silicon-containing layer. A further embodiment of the dielectric stack comprises an oxide layer positioned on the surface of the semiconductor substrate, a nitride layer optionally positioned on the surface of the oxide layer, a plurality of nanocrystals serving as the trapping sites positioned on the surface of the nitride layer, and a cover layer made of silicon oxide or silicon nitride positioned on the surface of the nitride layer, wherein the nanocrystal is made of silicon, silicon germanium, metal, alloy of metal, or silcide.

The method for preparing a flash memory structure comprises steps of forming a first doped region in a semiconductor substrate, forming a V-groove in the semiconductor substrate and above the first doped region, forming two second doped regions in the semiconductor substrate and at two sides of the V-groove, forming a dielectric stack having a plurality of trapping sites on the V-groove, and forming a conductive layer on the surface of the dielectric stack. The step of forming a V-groove comprises forming a mask layer on the surface of the semiconductor substrate, forming an opening in the mask layer, performing an etching process to remove a portion of the semiconductor substrate below the opening to form the V-groove, and removing the mask layer. Preferably, the mask layer is an oxide layer, and the etching process uses an etchant including potassium hydroxide. The semiconductor substrate can be a (100)-oriented silicon substrate, and the V-groove has inclined surface planes with (111) orientation.

Compared to the prior art, the present flash memory structure possesses a higher storage density and the method for fabricating the flash memory possesses a better step coverage property. The present flash memory structure has two memory cells, which share the same gate electrode and the same drain electrode. In addition, these two memory cells have carrier channels positioned in the semiconductor substrate below the two inclined surfaces of the V-groove, and trapping sites positioned in the dielectric stack on the inclined surface of the V-groove in an inclined manner rather than in a horizontal manner as in the prior art. Consequently, the present invention can increase the number of memory cells in a unit substrate area, i.e., increasing the storage density. Further, the width of the V-groove is larger at the top region than at the bottom region, and the dielectric stack and the conductive layer can be prepared by deposition process with a better step coverage property, which will not form a void in the dielectric stack or in the conductive layer.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2toFIG. 7illustrate a method for fabricating a flash memory structure50according to one embodiment of the present invention. A first doped region54is formed in a silicon substrate52by an n+ ion implanting process, and the implanting energy is preferably between 20 and 30 keV to implant dopants into a depth between 1600 and 2000 angstroms. A mask layer56is formed on the surface of the silicon substrate52, and a lithographic process is then performed to form an opening58in the mask layer56, as shown inFIG. 3. Preferably, the mask layer56is a silicon oxide layer, and the silicon substrate52is (100)-oriented.

Referring toFIG. 4, an etching process is performed to remove a portion of the silicon substrate52below the opening58to form a V-groove60, and the mask layer56is then completely removed. Particularly, the etching process uses an etchant including potassium hydroxide, and the V-groove60has inclined surface planes62with (111) orientation. The etchant removes the silicon substrate52at a rate of 0.6 micrometer/minute along the planes with (100) orientation and at a rate of 0.006 micrometer/minute along the planes with (111) orientation at 80° C., i.e., the etching process is orientation-independent, which can form the V-groove60with the inclined surface planes62with (111) orientation automatically.

Referring toFIG. 5(a), another n+ion implanting process is performed to form two second doped regions72and74in the silicon substrate52and at two sides of the V-groove60. A third doped region76can be optionally formed between the two second doped regions72and74in the silicon substrate52by an n+or n−ion implanting process, and the third doped region76is positioned above the first doped region54but below the V-groove60to guide induced current, as shown inFIG. 5(b). Particularly, the first doped region54serves as the drain electrode of a transistor, and the second doped regions72and74serve as the source electrode of the transistor.

Referring toFIG. 6, deposition processes are performed to form a first oxide layer82on the surface of the silicon substrate52, a silicon nitride layer84on the surface of the first oxide layer82, and a second oxide layer86on the surface of the silicon nitride layer84so as to form a dielectric stack80on the surface of the silicon substrate52. A conductive layer78made of polysilicon is subsequently formed on the surface of the dielectric stack80and above the V-groove60to complete the flash memory structure50. Particularly, the flash memory structure50includes a plurality of carrier trapping sites66disposed in the silicon nitride layer84of the dielectric stack80on the two inclined surface planes62of the V-groove60.

FIG. 8is a three-dimensional diagram of the flash memory structure50according to one embodiment of the present invention, wherein a portion of the silicon substrate52is not shown for clarity consideration.FIG. 9illustrates a NOR flash memory designed in view of the flash memory structure50according to one embodiment of the present invention. The flash memory structure50inFIG. 8comprises two SONOS flash memory cells, which correspond to a dash-lined region inFIG. 9. These two SONOS flash memory cells share the same drain electrode (the first doped region54) and gate electrode (the conductive layer78), and the carrier channels of the two SONOS flash memory cells are positioned in the silicon substrate52and below the two inclined surface planes62of the V-groove60in an inclined manner. Particularly, the flash memory structure50inFIG. 8directly corresponds to the circuit design of the NOR flash memory inFIG. 9. The bit line1connects to the second doped region74, and bit line2connects to the second doped region72, wherein the two second doped regions72and74serve as the two source electrodes of the two SONOS flash memory cells, respectively. The contact line penetrates a dielectric layer88to connect to the first doped region54, and one end of the contact line is connected to a drain electrode for one block.

Compared to the prior art, the present flash memory structure possesses a higher storage density and the method for fabricating the flash memory possesses a better step coverage property. The present flash memory structure has two memory cells, which share use of the same gate electrode and drain electrode. In addition, these two memory cells have carrier channels positioned in the semiconductor substrate below the two inclined surfaces of the V-groove, and trapping sites positioned in the dielectric stack on the inclined surface of the V-groove in an inclined manner rather than in a horizontal manner as in the prior art. Consequently, the present invention can increase the number of memory cells in a unit silicon area, i.e., increasing the storage density. Further, the width of the V-groove is larger at the top region than that at the bottom region, and the dielectric stack and the conductive layer can be prepared by deposition process with a better step coverage property, which will not form a void in the dielectric stack or in the conductive layer.

In addition, the application of the present invention is not limited to the SONOS flash memory as describe above.FIG. 10illustrates a flash memory structure110having a dielectric stack90according to another embodiment of the present invention. The dielectric stack90can be prepared by steps of forming a first oxide layer92on the surface of the silicon substrate52, forming a first silicon nitride layer94on the surface of the first oxide layer92, forming a silicon-containing layer96made of polysilicon or silicon germanium on the surface of the first silicon nitride layer94, forming a second silicon nitride layer98on the surface of the silicon-containing layer96, and forming a second oxide layer100on the surface of the second silicon nitride layer98. Particularly, the carrier trapping sites are positioned in the silicon-containing layer96.

FIG. 11illustrates a flash memory structure130including a dielectric stack120having a plurality of carrier trapping sites disposed therein according to another embodiment of the present invention. The dielectric stack120can be prepared by forming an oxide layer122on the surface of the silicon substrate52, forming a silicon nitride layer124on the surface of the oxide layer122, forming a plurality of nanocrystals128serving as the trapping sites on the surface of the silicon nitride layer124, and forming a cover layer126made of silicon oxide or silicon nitride covering the nanocrystals128and the silicon nitride layer124. Particularly, the nanocrystals128are made of semiconductor material, metal, alloy of metal, or silcide, wherein the metal can be cobalt, nickel or tungsten, and the semiconductor material can be silicon or silicon germanium.