DRAM memory device with xtacking architecture

A semiconductor device is provided. The semiconductor device includes a first wafer having an array transistor formed therein, and a second wafer having a capacitor structure formed therein. The semiconductor device also includes a bonding interface formed between the first wafer and second wafer that includes a plurality of bonding structures. The bonding structures are configured to couple the array transistor to the capacitor structure to form a memory cell.

BACKGROUND

A dynamic random access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell having a capacitor and an array transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can be set to either a charged or discharged state. These two states are taken to represent the two values of a bit, conventionally called zero and one. The DRAM also includes periphery transistors to form periphery circuits. The periphery circuits and the array transistors handle data input/output (I/O) as well as memory cell operations (e.g., writing or reading).

As DRAM technology migrates towards higher densities and high capacities, for example to a 10 nm node, the number of capacitors dramatically increases and the size of the capacitors dramatically reduces. The changes of the number and size of the capacitors can result in a longer process time and a more complex process flow.

SUMMARY

The concepts relate to formation of a DRAM memory device, for example a DRAM memory device having an Xtacking architecture. With the Xtacking architecture, the capacitors of the DRAM memory device are processed on an array wafer, and the periphery transistors and the array transistors of the DRAM memory device are processed on a separate periphery wafer using a logic technology node that enables the desired I/O speed and functions. Once the processing of the array wafer and the periphery wafer are completed, the two wafers are connected electrically through metal VIAs (Vertical Interconnect Accesses) that are formed across an interface between the wafers in one process step. By using the Xtacking technology, a higher storage density, a simpler process flower, and a less cycle time can be achieved.

According to an aspect of the present disclosure, a semiconductor device is provided that can include a first wafer having an array transistor formed therein and a second wafer having a capacitor structure formed therein. The semiconductor device also includes a bonding interface formed between the first wafer and second wafer that includes a plurality of bonding structures. The bonding structures are configured to couple the array transistor to the capacitor structure to form a memory cell.

In some embodiments, the first wafer can have a first substrate and the second wafer can have a second substrate. The first substrate has a first side and an opposing second side. The second substrate has a first side and an opposing second side. The array transistor can be positioned in the first side of the first substrate.

Additionally, the semiconductor device can include a first dielectric stack formed over the array transistor and positioned on the first side of the first substrate, and a plurality first contact structures formed in and extending through the first dielectric stack, where a first terminal contact of the first contact structures is coupled to a first doped region of the array transistor. The semiconductor device can also include a second dielectric stack formed on the first side of the second substrate so that the capacitor structure is positioned in the second dielectric stack, where a plurality of second contact structures are formed in and further extend through the second dielectric stack. The semiconductor device can include a third dielectric stack formed on the second side of the second substrate, and a through silicon contact (TSC) that is formed in the third dielectric stack. The TSC can extend from the second side of the second substrate through the second substrate to connect to a second terminal contact of the second contact structures.

The array transistor can further include a gate structure and a second doped region. The gate structure can be coupled a word line structure of the first contact structures, and the second doped region can be coupled to a bit line structure of the first contact structures.

The capacitor structure can have a cup-shaped bottom plate. The bottom plate can be formed in the second dielectric stack. The bottom plate further extends away from the first side of the second substrate and is coupled to a bottom plate contact of the second contact structures. The capacitor structure can also have an elongated top plate that is positioned within the bottom plate and coupled to a top plate contact of the second contact structures. A high-K layer is further positioned between the bottom plate and the top plate.

In some embodiments, the bottom plate contact and the first terminal contact can be bonded together, and the bit line structure and the second terminal contact can be bonded together.

The semiconductor device can further have a periphery transistor that is formed in the first side of the first substrate. The periphery transistor can have a gate structure that is connected to a gate contact of the first contact structures, a source region that is connected to a source contact of the first contact structures, and a drain region that is connected to a drain contact of the first contact structures. Each of the gate contact, the source contact, and the drain contact can be bonded to a respective second contact structure.

In another embodiment, the semiconductor device can have a periphery transistor that is formed in the first side of the second substrate. Accordingly, the periphery transistor has a gate structure that is connected to a gate contact of the second contact structures, a source region that is connected to a source contact of the second contact structures, and a drain region that is connected to a drain contact of the second contact structures. Each of the gate contact, the source contact, and the drain contact is bonded to a respective first contact structure.

According to another aspect of the disclosure, a method for manufacturing a semiconductor device is provided. In the disclosed method, an array transistor can be formed in a first side of a first substrate. A first dielectric stack is formed over the array transistor and positioned on the first side of the first substrate, and a plurality first contact structures are formed in the first dielectric stack, where the array transistor is coupled to at least one of the first contact structures. In addition, a capacitor structure can be further formed over a first side of a second substrate. A second dielectric stack is formed on the first side of the second substrate and a plurality of second contact structures are formed in the second dielectric stack, where the capacitor structure is coupled to at least one of the second contact structures, and the capacitor structure is positioned in the second dielectric stack. The first substrate and the second substrate can be subsequently bonded together through a plurality of bonding structures so that the capacitor structure is coupled to the array transistor, and the first side of the first substrate and the first side of the second substrate face to each other.

The method can also include forming a periphery transistor in the first side of the first substrate. The periphery transistor can include a gate structure that is connected to a gate contact of the first contact structures, a source region that is connected to a source contact of the first contact structures, and a drain region that is connected to a drain contact of the first contact structures, where each of the gate contact, the source contact, and the drain contact is bonded to a respective second contact structure.

In some embodiments, forming the array transistor can include forming a gate structure, a first doped region, and a second doped region. The gate structure can be coupled a word line structure of the first contact structures, the first doped region can be coupled to a first terminal contact of the first contact structures, and the second doped region can be coupled to a bit line structure of the first contact structures.

In some embodiments, a portion of the second substrate can be removed from a second side that is opposite to the first side of the second substrate. A third dielectric stack subsequently can be formed over the second side of the second substrate. A through silicon contact (TSC) can be formed in the third dielectric stack. The TSC can extend from the second side of the second substrate and further extend through the second substrate to connect to a second terminal contact of the second contact structures.

In order to form the capacitor structure, a cup-shaped bottom plate can be formed. The bottom plate can be arranged in the second dielectric stack and extend away from the first side of the second substrate to connect to a bottom plate contact of the second contact structures. Further, an elongated top plate can be formed. The top plate can be positioned within the bottom plate and coupled to a top plate contact of the second contact structures. A high-K layer can be positioned between the bottom plate and the top plate.

In some embodiments, bonding the first substrate and the second substrate can include bonding the bottom plate contact and the first terminal contact together so that the capacitor structure is coupled to the first doped region of the array transistor, and bonding the bit line structure and the second terminal contact together so that the TSC is coupled to the second doped region of the array transistor.

In the disclosed method, a periphery transistor can also be formed in the first side of the second substrate. The periphery transistor can have a gate structure that is connected to a gate contact of the second contact structures, a source region that is connected to a source contact of the second contact structures, and a drain region that is connected to a drain contact of the second contact structures. Each of the gate contact, the source contact, and the drain contact is further bonded to a respective first contact structure.

According to yet another aspect of the disclosure, a semiconductor device is provided. The semiconductor device can have a first array region and a first periphery region that are formed over a first side of a first substrate. The first array region has at least one array transistor formed in the first side of the first substrate, and the first periphery region has at least one periphery transistor formed in the first side of the first substrate. The semiconductor device can have a second array region and a second periphery region that are formed over a first side of a second substrate. The second array region has at least one capacitor structure formed over the first side of the second substrate, and the at least one capacitor structure can be coupled to a first doped region of the at least one array transistor. The first side of the first substrate and the first side of the second substrate face each other. The semiconductor device can also have a plurality of bonding structures that are configured to bond the first array region to the second array region, and bond the first periphery region to the second periphery region.

The semiconductor device can have a first dielectric stack formed over the at least one array transistor on the first side of the first substrate, and a plurality first contact structures formed in and extending through the first dielectric stack, where a first terminal contact of the first contact structures is coupled to a first doped region of the at least one array transistor. The semiconductor device can also have a second dielectric stack that is formed on the first side of the second substrate so that the at least one capacitor structure is positioned in the second dielectric stack, and a plurality of second contact structures that are formed in and extend through the second dielectric stack. The semiconductor device can further have a third dielectric stack formed on a second side of the second substrate and at least one through silicon contact (TSC) formed in the third dielectric stack. The second side of the second substrate is opposite to the first side of the second substrate. The TSC can extend from the second side of the second substrate through the second substrate to connect to a second terminal contact of the second contact structures.

In some embodiments, the at least one array transistor can further include a gate structure that is coupled a word line structure of the first contact structures, and a second doped region that is coupled to a bit line structure of the first contact structures. In some embodiments, the at least one capacitor structure can further include a cup-shaped bottom plate, an elongated top plate, and a high-K layer. The bottom plate is formed in the second dielectric stack, extends away from the first side of the second substrate and coupled to a bottom plate contact of the second contact structures. The elongated top plate is positioned within the bottom plate and coupled to a top plate contact of the second contact structures. The high-K layer is positioned between the bottom plate and the top plate. The bottom plate contact and the first terminal contact are bonded together, and the bit line structure and the second terminal contact are bonded together.

DETAILED DESCRIPTION

A DRAM memory device can include an array region and a periphery region. The array region can include a plurality of DRAM memory cells. Each of the DRAM memory cells can be formed of a capacitor and an array transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can either be charged or discharged. These two states are taken to represent the two values of a bit, conventionally called zero and one. The capacitor can be formed in a flat configuration, a stack configuration, or a trench configuration depending on manufacturing methods. The capacitor can be coupled to a first dope region (e.g., a drain region) of the array transistor to be charged or discharged through the first dope region. A word line can be coupled to a gate of the array transistor to turn on or turn off the array transistor. A bit line can be coupled to a second doped region (e.g., a source region) of the array transistor and function as a path for charging or discharging the capacitor.

The periphery region can include a plurality of periphery transistors to form periphery circuits configured to operate the DRAM memory cells, such as writing or reading the DRAM memory cells. The periphery circuits can include row decoders, column decoders, input/output controllers, multiplexers, sense amplifiers, or the like. The row decoders are coupled to word lines of the DRAM memory cells and configured to turn on or turn off gates of the array transistors. The column decoders are coupled to bit lines of the DRAM memory cells and configured to read or write the DRAM memory cells. The input/output controllers are configured to control the input and output signals. The multiplexers are data selectors and configured to select an input signal between several input signals and forward the selected input signal to a single output line. The sense amplifiers are configured to sense low power signals from a bit line that represents a data bit (zero or one) stored in a DRAM memory cell, and amplify the small voltage swing to recognizable logic levels so the data can be interpreted properly by logic outside the DRAM memory device.

FIG.1Ais a schematic view of a DRAM memory cell formed in a flat configuration, where the capacitor is formed over and extend along a top surface of substrate (not shown).FIG.1Bis a schematic view of a DRAM memory device formed in a stack configuration, where the capacitor is formed in a dielectric stack that is positioned over a substrate (not shown).FIG.1Cis a schematic view of a DRAM memory device formed in a trench configuration, where the capacitor is positioned in the substrate (not shown). Comparing with the DRAM memory cell inFIG.1A, the DRAM memory cells inFIGS.1B-1Ccan reduce the DRAM memory cell's size and increase the storage density of the DRAM memory device.

FIG.2is a process flow for manufacturing a DRAM memory device. As shown inFIG.2, the array transistors, the periphery transistors, and the capacitors are processed sequentially in a same wafer. As DRAM technology migrates towards higher densities and high capacities, manufacturing the DRAM memory device requires longer process time, and a more complex process flow.

FIG.3is a cross-sectional view of a DRAM memory device100(also referred to as device100) that has capacitors formed in the stack configuration, and the capacitors, the array transistors and the periphery transistors are formed in a same wafer. For simplicity and clarity, an array transistor104, a periphery transistor106, and a capacitor108are illustrated inFIG.3. As shown inFIG.3, the array transistor104, the periphery transistor106, and the capacitor108are formed in a same wafer102. The wafer102can have a substrate110. The substrate110may be a semiconductor substrate, such as Si substrate. The array transistor104and the periphery transistor106are positioned in the substrate110. A dielectric stack101is formed over the substrate110. The dielectric stack101can include one or more dielectric layers. In an exemplary embodiment ofFIG.3, the dielectric stack101can include four inter layer dielectric (ILD) layers112-118. The capacitor108is formed in the dielectric stack101.

In some embodiments, the ILD layers112-118can include one of borophosphosilicate glass (BPSG), undoped silicate glass (USG), phosphosilicate glass (PSG), Tetraethylorthosilicate (TEOS), SiH4Oxide, SiO2, spin on dielectric (SOD) or other suitable dielectrics. The ILD layers112-118can have a thickness in a range 10 nm from to 10 um.

The array transistor104can have a first doped region (e.g., drain region)120that is coupled to the capacitor108through a contact structure124. The array transistor104can have a second doped region (e.g., source region)122that is coupled to a bit line through a first connection channel. The first connection channel can be formed of a contact structure126, a Via128, and a first metal (M1) layer130. The array transistor104can have a gate132that is coupled to a word line through a second connection channel. The second connection channel can be formed of a contact134, a Via136, and a M1 layer138.

In the present disclosure, a DRAM memory device is formed based on a Xtacking architecture. With the Xtacking architecture, in a first embodiment, the capacitors of the DRAM memory device are processed on an array wafer, and the periphery transistors and the array transistors of the DRAM memory devices are processed on a separate periphery wafer using the logic technology node. In alternative embodiments, the capacitors and the periphery transistors of the DRAM memory device can be processed on the periphery wafer, and the array transistor can be processed on the array wafer.

FIG.4Ais a cross-sectional view of a first exemplary DRAM memory device200A (also referred to as device200A), andFIG.4Bis a cross-sectional view of a second exemplary DRAM memory device200B (also referred to as device200B). The devices200A and200B are formed based on the Xtacking architecture. As shown inFIG.4A, the device200A can have a first array region3and a first periphery region4formed in a first wafer1, and a second array region5and a second periphery region6formed in a second wafer2. The first wafer1can have a first substrate10and the second wafer2can have a second substrate60. The first substrate10can have a first side10aand an opposing second side10b. The second substrate60can have a first side60aand an opposing second side60b.

The first array region3and the first periphery region4are formed over the first side10aof a first substrate10. The first array region3can have a plurality of array transistors, and the first periphery region4can have a plurality of periphery transistors. For simplicity and clarity, an array transistor14and a periphery transistor16are illustrated inFIG.4A. The array transistor14and the periphery transistor16can be formed in the first side10aof the first substrate10, and spaced apart from one another by a shallow trench isolation (STI)34.

The array transistor14can have a first doped region (e.g., a drain region)24and a second doped region (e.g., a source region)26that are formed in the first substrate10. The array transistor14can have a gate structure18that is positioned over the first side10aof the first substrate10, and a p-typed doped well (PW)20that is positioned in the first substrate10and functions as a body of the array transistor14. A gate dielectric layer22is positioned between the gate structure18and the PW20. Dielectric spacers21can be positioned along sidewalls of the gate structure18and the gate dielectric layer22.

The periphery transistor16can be an n-type transistor or a p-type transistor according to the circuit design. The periphery transistor16can have a first source/drain (S/D) region36and a second S/D region38that are positioned in the first substrate10. The periphery transistor16can have a gate structure40positioned over the first substrate10, and a doped well region44positioned in the first substrate10and functions as a body of the periphery transistor16. A gate dielectric layer42is positioned between the gate structure40and the doped well region44. The doped well region44can have a n-type dopant or a p-type dopant according to the structures of the periphery transistor16. Dielectric spacers41can be positioned along sidewalls of the gate structure40and the gate dielectric layer42.

In the device200A, a first dielectric stack7is formed over the array transistor14and positioned on the first side10aof the first substrate10. The first dielectric stack7can include a plurality of ILD layers. For example, three ILD layers28,30and32are illustrated inFIG.4A. A plurality of first contact structures can be formed in and further extend through the first dielectric stack7. In an exemplary embodiment ofFIG.4A, six first contact structures11a-11fare included. Each of the first contact structures11a-11fcan include a contact46, a Via48, and a M1 layer50. The first contact structures11a-11fcan include a first terminal contact11athat is coupled to the first doped region24of the array transistor14. The first contact structures11a-11fcan also include a word line structure11bthat is coupled to the gate structure18of the array transistor14. The first contact structures11a-11fcan further include a bit line structure11cthat is coupled to the second doped region26of the array transistor14. The first contact structures11d,11e, and11fcan further be coupled to the first S/D region36, the gate structure40, the second S/D region38of the periphery transistor16respectively. Accordingly, the first contact structure11dfunctions as a first S/D contact, the first contact structure1if functions as a second S/D contact, and the first contact structure11efunctions as a gate contact of the periphery transistor16.

In some embodiments, the ILD layers28,30and32can include BPSG, USG, PSG, TEOS, SiH4Oxide, SiO2, SOD or other suitable dielectric materials. The ILD layers28,30and32can have a thickness in a range 10 nm from to 10 um. Any suitable manufacturing processes can be applied to form the ILD layers28,30and32, such as a CVD process, a PVD process, an atomic layer deposition (ALD) process, a diffusion process, a sputter process, or a combination thereof.

Still referring toFIG.4A, the second array region5and the second periphery region6are formed over the first side60aof the second substrate60. The second array region5can have a plurality of capacitor structures formed over the first side60aof the second substrate60. For simplicity and clarity, a capacitor structure61is illustrated inFIG.4A. Further, a second dielectric stack8can be formed on the first side of60athe second substrate60so that the capacitor structures, such as the capacitor structure61, are positioned in the second dielectric stack8. The second dielectric stack8can have a plurality of ILD layers. For example, three ILD layers65,66and67are included inFIG.4A. The capacitor structure61can have a cup-shaped bottom plate62that is disposed in the second dielectric stack8and further extend away from the first side60aof the second substrate60. The capacitor structure61can have an elongated top plate63that is positioned within the bottom plate62. A high-K layer64is positioned between the bottom plate62and the top plate63. In some embodiments, top surfaces of the bottom plate62, the top plate63, and the high-K layer64can be co-planar.

In some embodiments, the ILD layers65-67can include BPSG, USG, PSG, TEOS, SiH4Oxide, SiO2, SOD or other suitable dielectric materials. The ILD layers65-67can have a thickness in a range 10 nm from to 10 um. Any suitable manufacturing processes can be applied to form the ILD layers65-67, such as a CVD process, a PVD process, an ALD process, a diffusion process, a sputter process, or a combination thereof.

Over the first side60aof the second substrate60, a plurality of second contact structures are positioned in and further extend through the second dielectric stack8. For example, five second contact structures68a-68eare illustrated inFIG.4A. Each of the second contact structures can have a VIA69and a M1 layer70that are connected to each other. The second contact structures68a-68ecan include one or more bottom plate contacts68c-68dthat are coupled to the bottom plate62. The second contact structures68a-68ecan include a top plate contact68ethat is coupled to the top plate63. In some embodiments, the top plate contact68ecan be supplied with a constant voltage, such as 0.5 volt. The bottom plate contacts68c-68dcan be connected to the bottom plate62. The bottom plate contact68c-68dcan further be coupled to the first terminal contact11aof the first contact structures11a-11fso that the capacitor structure61is coupled to the first doped region24of the array transistor14.

The device200A can have a third dielectric stack9formed on the second side60bof the second substrate60. The third dielectric stack9can include a plurality of ILD layers. For example, two ILD layers71and72are illustrated inFIG.4A. In some embodiments, the ILD layers71and72can include SiN, TEOS, SiH4Oxide, SiO2or other suitable dielectric materials. Further, a plurality of through silicon contacts (TSCs) can be formed in the third dielectric stack9. The TSCs can further extend from the second side60bof the second substrate60through the second substrate60to connect to the second contact structures. The device200A can also have a plurality of bottom top metals (BTMs) that function as bonding pad and positioned on the TSCs. In an exemplary embodiment ofFIG.4A, a TSC73and a BTM74are illustrated, where the BTM74can be positioned on the TSC73and function as a bonding pad. The TSCs can be connected to the second contact structures. For example, the TSC73can be connected to the second contact structure68b. In some embodiments, a barrier layer75can be disposed between the TSC73and the third dielectric stack9and the second substrate60.

In the device200A, a bonding interface76is formed between the first wafer1and the second wafer2that includes a plurality of bonding structures (not shown). The bonding structures (not shown) can be positioned on the M1 layers50and/or the M1 layers70. The bonding structures can include Cu, Ni, SnAg, or other suitable bonding materials. The bonding structures are configured to bond the first wafer1and the second wafer2together by bonding the M1 layers50to the M1 layers70. Accordingly, the first contact structures11a-11fare coupled to the second contact structures68a-68e, the first array region3is coupled to the second array region5, and the first periphery region4is coupled to the second periphery region6. In addition, the first side10aof the first substrate10and the first side60aof the second substrate60face each other.

The coupling between the first wafer1and the second wafer2can be illustrated inFIG.4A. In a first example, the bit line structure11cof the first contact structures is bonded to the second contact structure (or the second terminal contact)68b. Thus, the TSC73can be coupled to the second doped region26of the array transistor14through the bit line structure11C and the second contact structure68b. Accordingly, an operation voltage can be applied to the second doped region26of the array transistor14through a connection channel formed of the BTM74, the TSC73, the bit line structure11C and the second contact structure68B. In a second example, the bottom plate contacts68c-68dcan be bonded to the first terminal contact11aso that the capacitor structure61is coupled to the first doped region (e.g., a drain region) of the array transistor14.

In some embodiments, the first substrate10and the second substrate60can be a semiconductor substrate such as Si substrate. The first substrate10and the second substrate60may also include other semiconductors such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. The gate dielectric layers22and42can be made of SiO, HfO, a high-K dielectric material, or other suitable dielectric materials. The gate structures18and40can be made of poly Si, W, WN, Ti, TiN, TaN, AlTiC, AlTiO, AlTiN, or other suitable materials. The contacts46and69can be made of W, Ru, Co, or other suitable conductive materials. The Via48, the M1 layer50and the M1 layer70can be made of Cu, Al, Ru, Co, W, or other suitable conductive materials. The first dielectric stack7, the second dielectric stack8and the third dielectric stack9can include SiO, TEOS, USG, PSG, BPSG, SiN, SiCN or other suitable dielectric Materials. The bottom plate62and the top plate63can include Ti, TiN, poly Si, or other suitable conductive materials. The high-K layer64can include HfO, AlO, ZrO, or other suitable high-K dielectric materials. The TSC73and the BTM74can be made of Cu, Al, W or other suitable conductive materials. The barrier layer75can be made of TEOS, SiO, or other suitable dielectric materials.

FIG.4Bis a cross-sectional view of a second exemplary DRAM memory device200B. The device200B has a similar structure to the device200A. For example, the device200B has a first wafer302and a second wafer304. The first wafer302has a first array region202and a first periphery region204that formed over a first side210aof a first substrate210. The second wafer304has a second array region206and a second periphery region208that are formed over a first side212aof a second substrate212. An exemplary array transistor214is formed in the first substrate210and positioned in the first array region202. An exemplary capacitor structure216is positioned in the second array region206. However, comparing to the device200A, periphery transistors, such as an exemplary periphery transistor218, are formed in the second substrate212and positioned in the second periphery region208.

The first wafer302can have a plurality of first contact structures220a-220f. The second wafer304can have a plurality of second contact structures222a-222g. A bonding interface303can be formed between the first wafer302and the second wafer304that includes a plurality of bonding structures (not shown). The bonding structures (not shown) can be positioned on M1 layers232and/or M1 layers234. The first contact structures220a-220fand the second contact structures222a-222gcan be bonded to each other through the bonding structures so that the first array region202and the second array region206are coupled to each other, and the first periphery region204and the second periphery region208are coupled to each other. For example, the first contact structures220d-220fin the first periphery region204are bonded to the second contact structures222e-222g. The second contact structures222e-222gare further connected to the periphery transistor218. Accordingly, the first contact structures220d-220fin the first periphery region204are coupled to the periphery transistor218in the second periphery region208. Similar to device200A, a TSC226extends through the second substrate212to connect to the second contact structure222d. The TSC226further is coupled to the array transistor214through a connection channel that is formed of the second contact structure222dand the first contact structure220c.

It should be noted that the capacitor structure in device200A or200B is formed in a stack configuration. However, the capacitor structure can also be formed in a flat configuration or a trench configuration.

FIG.5Ais a schematic view of a memory cell in the first exemplary DRAM memory device200A. As shown inFIG.5A, the array transistor (also referred to as transistor inFIG.5A) is processed in a first wafer (e.g., wafer A) and the capacitor is processed in a second wafer (e.g., wafer B). A drain region of the array transistor can be coupled to a bit line, and a source region of the array transistor can be coupled to the capacitor. A gate of the array transistor is coupled to a word line.

FIG.5Bis a schematic view of a first process flow for making the first exemplary DRAM memory device200A. As shown inFIG.5B, a periphery (or periphery region) of the device200A that includes periphery transistors can be process with the array transistors in a first wafer502. In the meanwhile, capacitors of the device200A can be process in a second wafer504. The first wafer502and the second wafer504can be bonded together to form the DRAM memory device200A in a bonded wafer506that has the Xtacking architecture.

FIG.5Cis a schematic view of a second process flow for making the first exemplary DRAM memory device200A, in accordance with exemplary embodiments of the disclosure. At step S508, the periphery transistors (e.g., periphery transistor16) and array transistors (e.g., array transistor14) can be formed in a first wafer (e.g., the first wafer1). The first wafer can then be sent on to form the contacts (e.g., contact46) in step S510. At step S512, the first wafer can then be sent on for receiving a back end of line (BEOL) process, where Vias (e.g., Via48) and metal layers (e.g., M1 layers50) can be formed over the contacts. In the meanwhile, capacitors (e.g., capacitor structure61) can be formed in a second wafer (e.g., the second wafer2) at step S514. The second wafer can then be sent on to form contacts (e.g., VIA69) at step S516. Subsequently, at step S518the second wafer can be sent on for receiving a BEOL process to form metal layers (e.g., M1 layers70). At step S520, the first wafer and the second wafer can be bonded together. At step S522, passivation layers (e.g., the third dielectric stack9) and bonding pad (e.g., TSC73and BTM74) can be formed.

FIG.6Ais a schematic view of a memory cell in the second exemplary DRAM memory device200B. As shown inFIG.6A, the array transistor (also referred to as transistor inFIG.6A) is processed in a first wafer (e.g., wafer A) and the capacitor is processed in a second wafer (e.g., wafer B). A drain region of the array transistor is coupled to a bit line, and a source region of the array transistor is coupled to the capacitor. A gate of the array transistor is coupled to a word line.

FIG.6Bis a schematic view of a first process flow for making the second exemplary DRAM memory device200B. As shown inFIG.6B, a periphery (or periphery region) of the device200B that includes periphery transistors can be processed with capacitors in a first wafer604. In the meanwhile, transistors (or array transistors) of the device200B can be processed in a second wafer602. The first wafer604and the second wafer602can be bonded together to form the DRAM memory device200B in a bonded wafer606that has the Xtacking architecture.

FIG.6Cis a schematic view of a second process flow for making the second exemplary DRAM memory device200B (or device200B). At step S608, the array transistors (e.g., array transistor214) can be formed in a first wafer (e.g., the first wafer302). The first wafer can then be sent on to form the contacts (e.g., contact228) in step S610. At step612, the first wafer can then be sent on for receiving a back end of line (BEOL) process, where Vias (e.g., Via230) and metal layers (e.g., M1 layers232) can be formed over the contacts. In the meanwhile, capacitors (e.g., capacitor structure216) and periphery transistors (e.g.,218) can be formed in a second wafer (e.g., the second wafer304) at step S614. The second wafer can then be sent on to form contacts (e.g., contact238, Via236) at step S616. Subsequently, at step S618the second wafer can be sent on for receiving a BEOL process to form metal layers (e.g., M1 layers234). At step S620, the first wafer and the second wafer can be bonded together. At step S622, passivation layers (e.g., the third dielectric stack240) and bonding pad (e.g., TSC226and BTM224) can be formed.

FIGS.7-10are cross-sectional views of first various intermediate steps of manufacturing the first exemplary DRAM memory device200A, in accordance with exemplary embodiments of the disclosure. As shown inFIG.7, a first array region3, and a first periphery region4are formed in a first wafer1. The first array region3can include a plurality of array transistors, and a plurality of periphery transistors. For simplicity and clarity, an array transistor14and a periphery transistor16are illustrated inFIG.7. The first wafer1can have a first substrate10that include a first side10aand an opposing second side10b. A first dielectric stack7can be formed over the array transistors14and the periphery transistor16and positioned on the first side10aof the first substrate10. The first dielectric stack7can include one or more dielectric layers, such as three ILD layers28,30and32that are illustrated inFIG.7.

A plurality of first contact structures11a-11fcan be formed in the first dielectric stack7and coupled to the array transistor14and the periphery transistor16. For example, the first contact structures11a-11fcan include a first terminal contact11athat is coupled to a first doped region24of the array transistor14. The first contact structures11a-11fcan also include a word line structure11bthat is coupled to a gate structure18of the array transistor14. The first contact structures11a-11fcan further include a bit line structure11cthat is coupled to a second doped region26of the array transistor14. The first contact structures11d,11e, and11fcan further be coupled to a first S/D region36, a gate structure40, and a second S/D region38of the periphery transistor16respectively. Accordingly, the first contact structures11dand11ffunction as S/D contacts, and the first contact structure11efunctions as a gate contact of the periphery transistor16.

In order to produce the first wafer1mentioned above, various semiconductor manufacturing processes can be applied. The semiconductor manufacturing processes can include a deposition process, a photolithograph process, an etching process, a wet clean process, a metrology measurement process, a real-time defect analysis, a surface planarization process, an implantation process, or the like. The deposition process further can include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a diffusion process, a sputtering process, an atomic layer deposition (ALD) process, an electroplating process, and so on.

For example, the implantation process can be applied to form a p-typed doped well (PW)20, the first doped region24and the second doped region26of the array transistor14. The deposition process can be applied to form a gate dielectric layer22, a gate structure18and spacers21of the array transistor14. The first dielectric stack7can be formed by the deposition process. In order to form the first contact structures11a-11fin the first dielectric stack7, a plurality of contact openings (not shown) can be formed by applying the photolithography process and the etching process. The deposition process can be subsequently applied to fill the contact openings with conductive materials. The surface planarization process can then be applied to remove excessive conductive materials over a top surface of the first dielectric stack7.

InFIG.8, a second array region5and a second periphery region6are formed over a first side60aof a second substrate60in a second wafer2. A capacitor structure61can be formed in the second array region5. The second substrate60can have the first side60aand an opposing second side60b. A second dielectric stack8can be formed over the first side60aof the second substrate60. The second dielectric stack8can include one or more ILD layers65-67. The capacitor structure61can be positioned over the first side60aof the second substrate60and disposed in the second dielectric stack8. The capacitor structure61can have a cup-shaped bottom plate62that is disposed in the second dielectric stack8and further extend away from the first side60aof the second substrate60. The capacitor structure61can have an elongated top plate63that is positioned within the bottom plate62. A high-K layer64is positioned between the bottom plate62and the top plate63. In some embodiments, top surfaces of the bottom plate62, the top plate63, and the high-K layer64can be co-planar.

In the second wafer2, a plurality of second contact structures68a-68ecan be formed in the second dielectric stack8. The second contact structures68a-68ecan include one or more bottom plate contacts68c-68dthat are coupled to the bottom plate62. The second contact structures68a-68ecan also include a top plate contact68ethat is coupled to the top plate63.

In order to form the second wafer2, the deposition process can be applied to form the second dielectric stack8on the first side60aof the second substrate60. A patterning process that includes the photolithography process and the etching process can be applied to form a bottom plate opening (not shown). Conductive materials can be subsequently deposited by the deposition process to form the bottom plate62. A high-K layer64can be formed by the deposition process over the bottom plate62. The patterning process can be applied again to form a top plate opening (not shown) in the second dielectric stack8, and the deposition process can be applied again to fill the top plate opening with conductive materials to form the top plate63. Further, the patterning process can be applied to form the contact openings (not shown). Conductive materials can then be deposited in the contact openings to form the second contact structures68a-68e.

InFIG.9, a bonding process can be applied to bond the first wafer1and the second wafer2. In order to bond the first wafer1to the second wafer2, a plurality of bonding structures (not shown), such as pillars, can be formed over the M1 layers50in the first wafer1and/or the M1 layers70in the second wafer2. The bonding structures can include Cu, Ni, and SnAg. Further, the M1 layers50can be bonded to the M1 layers70through the bonding structures by applying a bonding process. The bonding process can be operated at a temperature more than 220° C. so that the bonding structures can be melt to form a connection between the M1 layers50in the first wafer1and the M1 layers70in the second wafer2. When the first wafer1and the second wafer2are bonded together, the first array region3in the first wafer1can be coupled to the second array region5in the second wafer2. The first periphery region4in the first wafer1can also be coupled to the second periphery region6in the second wafer2through the first contact structures and the second contact structures. For example, the second contact structure68acan be connected to the first contact structure11dand further be coupled to the first S/D region36of the periphery transistor16. The second contact structure68bis connected to the first contact structure (or bit line structure)11cand further be coupled to the second doped region26of the array transistor14.

InFIG.10, a portion of the second substrate60can be removed from the second side60bof the second substrate60to reduce a thickness of the second substrate60. A third dielectric stack9can be formed over the second side60bof the second substrate60. The third dielectric stack9can include one or more ILD layers71-72. A combination of the photolithography process and the etching process can be applied to form contact openings (not shown) in the third dielectric stack9. The contact openings can further be extended through the second substrate60to expose the second contact structures. For example, the second contact structure68bcan be exposed inFIG.10. The deposition process, such as a CVD process can be applied to form the barrier layer75, and an electroplating process, can be applied to form the TSC73. A PVD process can further be applied to form the BTM74. When the TSC73and the BTM74are formed, a DRAM memory device200A can be formed that has a similar configuration to the DRAM memory device200A inFIG.4A.

FIGS.7,8,11and12are cross-sectional views of second intermediate steps of manufacturing the first exemplary DRAM memory device200A, in accordance with exemplary embodiments of the disclosure. As mentioned above, inFIG.7, the first array region3and the first periphery region4are formed in the first wafer1. InFIG.8, the second array region5and the second periphery region6are formed in the second wafer2. The manufacturing process then proceeds to a step illustrated inFIG.11. InFIG.11, a portion of the second substrate60can be removed from the second side60bof the second substrate60to reduce a thickness of the second substrate60. A third dielectric stack9can be formed over the second side60bof the second substrate60. The third dielectric stack9can include one or more ILD layers, such as ILD layers71-72. A combination of the photolithography process and the etching process can be applied to form contact openings (not shown) in the third dielectric stack9. The contact openings can further be extended through the second substrate60to expose the second contact structures. For example, the second contact structure68bcan be exposed inFIG.11. The deposition process, such as an electroplating process, can be applied to form the TSC73. A PVD process can further be applied to form the BTM74.

InFIG.12, the first wafer1and the second wafer2can be bonded to each other by a bonding process. The bonding process can be similar to the bonding process mentioned inFIG.9, where a plurality of bonding structures (not shown) can be formed over the M1 layers50and/or the M1 layers70, and the M1 layers50and the M1 layers70can further be connected to each other by a thermal process to melt the bonding structures. When the bonding process is completed, a bonding interface76can be formed between the first wafer1and the second wafer2, and a DRAM memory device200A can be formed that has a similar configuration to the DRAM memory device200A illustrated inFIG.4A.

FIGS.13-15are cross-sectional views of intermediate steps of manufacturing the second exemplary DRAM memory device200B, in accordance with exemplary embodiments of the disclosure. As shown inFIG.13, a first array region202and a first periphery region204can be formed in a first wafer302. The first array region202can include a plurality of array transistors. For simplicity and clarity, an array transistor214is illustrated in the first array region202. The first wafer302can have a first substrate210and a first dielectric stack248formed on the first side210aof the first substrate210. A plurality of first contact structures220a-220fcan be formed in the first dielectric stack248and disposed in the first array region202and the first periphery region204. At least one of the first contact structures220a-220fis coupled to the array transistor214. For example, the first contact structures220a-220fcan include a first terminal contact220athat is coupled to a first doped region242of the array transistor214. The first contact structures220a-220fcan also include a word line structure220bthat is coupled to a gate structure246of the array transistor214. The first contact structures220a-220fcan further include a bit line structure220cthat is coupled to a second doped region244of the array transistor214.

InFIG.14, a second array region206and a second periphery region208can be formed in a second wafer304. The second wafer304can have a second substrate212that has a first side212aand an opposing second side212b. A second dielectric stack250can be formed on the first side212aof the second substrate212. A plurality capacitor structures can be formed in the second array region206and positioned in the second dielectric stack250. A plurality of periphery transistors can be formed in the second periphery region208and further extend into the first side212aof the second substrate212. For simplicity and clarity, a capacitor structure216and a periphery transistor218are illustrated inFIG.14. Further, a plurality of second contact structures222a-222gcan extend away from the first side212aof the second substrate212and be disposed in the second dielectric stack250.

The second contact structures222a-222gcan be coupled to the capacitor structure216and the periphery transistor218. For example, the second contact structures222a-222gcan include one or more bottom plate contacts222aand222cthat are coupled to a bottom plate252of the capacitor structure216. The second contact structures222a-222gcan also include a top plate contact222bthat is coupled to a top plate254of the capacitor structure216. The second contact structures222a-222gcan further include a first S/D contact222ecoupled to a first S/D region256, a gate contact222fcoupled to a gate structure258, and a second S/D contact222gcoupled to a second S/D region260of the periphery transistor218.

InFIG.15, the first wafer302and the second wafer304can be bonded together along a bonding interface303so that the first array region202and the second array region206can be coupled to each other, and the first periphery region204and the second periphery region208can be coupled to each other. Further, a portion of the second substrate212can be removed from the second side212bof the second substrate212. A third dielectric stack240can be formed on the second side212bof the second substrate212. A TSC226can be formed in the third dielectric stack240and further extend through the second substrate212to connect to the second contact structure222d. A BTM224is then formed over the TSC226. When the TSC226and the BTM224are completed, a DRAM memory device200B is formed that has a similar configuration to the device200B illustrated inFIG.4B.

FIG.16is a flowchart of a process1600for manufacturing a DRAM memory device in accordance with some embodiments. The process1600begins at step S1604where an array transistor is formed in a first side of a first substrate. The process1600then proceed to step S1604, where a first dielectric stack is formed over the array transistor on the first side of the first substrate and a plurality of first contact structures are formed in the first dielectric stack. The array transistor is coupled to at least one of the first contact structures. In some embodiments, the steps S1604and S1606can be performed as illustrated with reference toFIG.7orFIG.13. InFIG.7, a periphery transistor can also be formed in the first side of the first substrate.

The process1600then proceeds to step S1608where a second dielectric stack can be formed on a first side of the second substrate. At step S1610, a capacitor structure can be formed over the first side of a second substrate, and a plurality of second contact structures can be subsequently formed in the second dielectric stack, where the capacitor structure is coupled to at least one of the second contact structures, and the capacitor structure is positioned in the second dielectric stack. In some embodiments, the steps S1608and S1610can be performed as illustrated with reference toFIG.8orFIG.14. InFIG.14, a periphery transistor can also be formed in the first side of the second substrate.

The process1600then proceeds to step S1612, where the first substrate and the second substrate are bonded together through a plurality of bonding structures so that the capacitor structure is coupled to the array transistor, and the first side of the first substrate and the first side of the second substrate face to each other. In some embodiments, the steps S1612can be performed as illustrated with reference toFIG.9orFIG.15.

It should be noted that additional steps can be provided before, during, and after the process1600, and some of the steps described herein can be replaced, eliminated, performed in different order, or performed in parallel for additional embodiments of the process1600. In an example, when the steps S1604and S1606are process in the first substrate, the steps S1608and S1610can be processed in the second substrate in parallel. In another example, when the first substrate and the second substrate are bonded together, a portion of the second substrate can be removed from the second side of the second substrate. A third dielectric stack can be formed on the second side of the second substrate, and a plurality of TSCs can be formed in the third dielectric stack. The TSCs can further extend through the second substrate to connect to the second contact structures.

In subsequent process steps of the process1600, various additional interconnect structures (e.g., metallization layers having conductive lines and/or vias) may be formed over the DRAM memory device. Such interconnect structures electrically connect the DRAM memory device with other contact structures and/or active devices to form functional circuits. Additional device features such as passivation layers, input/output structures, and the like may also be formed.

The various embodiments described herein offer several advantages over related DRAM memory devices. For example, in the related DRAM memory devices, memory cells and periphery transistors are processed in a same wafer, which requires a longer process time, and a more complex process flow. The disclosed DRAM memory device is manufactured based on a Xtacking architecture. With the Xtacking architecture, capacitors of the DRAM memory device are processed on an array wafer, and periphery transistors and array transistors of the DRAM memory device are processed on a separate periphery wafer using the logic technology node that enables the desired I/O speed and functions. Once the processing of the array wafer and the processing of the periphery wafer are completed, the two wafers are connected electrically through bonding structures that are formed simultaneously across the whole wafer in one process step. By using the innovative Xtacking technology, a higher storage density, a simpler process flower, and a less cycle time can be achieved.