Fork Sheet with Reduced Coupling Effect

Fork sheet FET devices with airgap isolation are provided. In one aspect, a fork sheet FET device includes: at least a first nanosheet FET and a second nanosheet FET; and a dielectric pillar disposed directly between the first nanosheet FET and the second nanosheet FET, wherein the dielectric pillar includes an airgap. For instance, the first nanosheet FET and the second nanosheet FET can have nanosheets that extend horizontally on opposite sides of the dielectric pillar. A method of forming a fork sheet FET device having airgap isolation is also provided.

FIELD OF THE INVENTION

The present invention relates to fork sheet field-effect transistor (FET) devices, and more particularly, to fork sheet FET devices with airgap isolation for reduced capacitance coupling.

BACKGROUND OF THE INVENTION

Fork sheet field-effect transistor (FET) devices offer further scaling opportunities over traditional finFET and nanosheet architectures. With a fork sheet device, the spacing between the n-channel FET (NFET) and p-channel FET (PFET) devices is reduced to permit further area scaling.

The implementation of a fork sheet FET design, however, can present some notable challenges. For instance, with a fork sheet FET design the NFET source/drain region can be in very close proximity to the PFET source/drain region, and the NFET gate can be in very close proximity to the PFET gate.

With conventional approaches, a minimal insulator is employed between the NFET and PFET source/drain regions and gates. As a result, capacitance coupling between the NFET and PFET source/drain regions and/or between the NFET and PFET gates can lead to false turn-on of the transistors and/or affect read/write stability.

Therefore, improved fork sheet FET device designs with reduced capacitance coupling would be desirable.

SUMMARY OF THE INVENTION

The present invention provides fork sheet field-effect transistor (FET) devices with airgap isolation for reduced capacitance coupling. In one aspect of the invention, a fork sheet FET device is provided. The fork sheet FET device includes: at least a first nanosheet FET (e.g., an n-channel FET (NFET)) and a second nanosheet FET (e.g., a p-channel FET (PFET)); and a dielectric pillar disposed directly between the first nanosheet FET and the second nanosheet FET, wherein the dielectric pillar includes an airgap. For example, the first nanosheet FET and the second nanosheet FET contact opposite sides of the dielectric pillar.

In another aspect of the invention, another fork sheet FET device is provided. The fork sheet FET device includes: at least a first nanosheet FET and a second nanosheet FET; and a dielectric pillar disposed directly between the first nanosheet FET and the second nanosheet FET, wherein the dielectric pillar includes an airgap, and wherein the first nanosheet FET and the second nanosheet FET have nanosheets that extend horizontally on opposite sides of the dielectric pillar.

In yet another aspect of the invention, a method of forming a fork sheet FET device is provided. The method includes: forming at least a first nanosheet FET and a second nanosheet FET having a sacrificial pillar disposed directly therebetween; removing the sacrificial pillar to form an opening in between the first nanosheet FET and the second nanosheet FET, wherein a bottom portion of the opening has a width W1OPENINGand a top portion of the opening has a width W2OPENING, and wherein W2OPENING<W1OPENING; and depositing a dielectric liner into and lining the opening wherein, during the depositing, the dielectric liner pinches off the top portion of the opening before fully filling the bottom portion of the opening based on W2OPENING<W1OPENINGthereby creating a dielectric pillar having an airgap between the first nanosheet FET and the second nanosheet FET.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

As provided above, a fork sheet field-effect transistor (FET) design can present some notable challenges. Namely, placing the NFET source/drain region in very close proximity to the PFET source/drain region, and the NFET gate in very close proximity to the PFET gate increases the risk of capacitance coupling, which can lead to false turn-on of the transistors and/or affect read/write stability.

Advantageously, provided herein are fork sheet FET devices with airgap isolation which vastly reduces capacitance coupling as compared to conventional designs. Namely, with conventional designs, a dielectric material such as silicon oxide (SiOx) and/or silicon nitride (SiN) is used to separate the NFET and PFET devices in a fork sheet FET. Even so, the effect of capacitance coupling on the device performance remains significant. On the other hand, air has a significantly lower dielectric constant than these conventional oxide and nitride dielectric materials. For instance, by way of example only, at room temperature (i.e., 25 degrees Celsius (° C.)), air has a dielectric constant of 1.00059, whereas SiN has a dielectric constant of about 9.5. Thus, implementing an airgap spacer in between the NFET and PFET devices in a fork sheet FET would greatly reduce the capacitance coupling.

An exemplary methodology for fabricating a fork sheet FET device with airgap isolation in accordance with the present techniques is now described by way of reference toFIGS.1-17. In each of the following figures, a cross-sectional view through a part of the fork sheet FET device structure will be provided. See, for example,FIG.1which shows a top-down view of the general layout of the present fork sheet FET device structure and the orientations of the various cuts that will be depicted in the figures. As shown inFIG.1, according to an exemplary embodiment the present fork sheet FET device includes at least one n-channel FET (NFET) device (labeled ‘NFET’) and at least one p-channel (PFET) device (labeled ‘PFET’) separated by a pillar with airgap isolation (labeled ‘airgap pillar). For clarity, the terms ‘first’ and ‘second’ may also be used herein when referring to the NFET and PFET devices, respectively. As will be described in detail below, each NFET/PFET device contains a stack of layers (e.g., nanosheets) which extend horizontally along a first direction (in this case an X-direction) on opposite sides of the airgap pillar. As will be described in detail below, the airgap pillar is a vertical structure that is disposed directly between the NFET and PFET stacks. Gates of the fork sheet FET device (labeled ‘gates’) are present over the NFET and PFET stacks. As shown inFIG.1, the gates extend along a second direction (in this case a Y-direction) which is perpendicular to the first/X-direction.

The pattern used inFIG.1for the gates is representative of the sacrificial gates that will be placed over the NFET and PFET device stacks early on in the process. Namely, as will be described in detail below, a replacement gate process is employed in this example where these sacrificial gates serve as placeholders during source/drain region formation, and which are later replaced with the final gates of the fork sheet FET device (also referred to herein as ‘replacement gates’). It is notable, however, that the orientation of the gates with respect to the NFET and PFET device stacks is the same for both the sacrificial and replacement gates.

As shown inFIG.1, a cross-section X-X′ will provide views of cuts through the PFET device stack perpendicular to the gates. It is notable that the processes that will be depicted by way of reference to the cross-sectional cuts X-X′ through the PFET device stack are performed in exactly the same manner in the NFET device stack, and thus would appear the same. One cross-section Y1-Y1′ will provide views of cuts through, and perpendicular to, the NFET and PFET device stacks in between two of the gates. Another cross-section Y2-Y2′ will provide views of cuts through, and perpendicular to, the NFET and PFET device stacks through one of the gates.

The process begins with the formation of a stack204of alternating sacrificial and active layers on a substrate202, followed by patterning of the stack204. SeeFIG.2A(an X-X′ cross-sectional view) andFIG.2B(a Y1-Y1′ and Y2-Y2′ cross-sectional view). Namely, at this stage in the process, the Y1-Y1′ and Y2-Y2′ cross-sectional views would appear the same, i.e., as that shown inFIG.2B.

According to an exemplary embodiment, substrate202is a bulk semiconductor wafer, such as a bulk silicon (Si), bulk germanium (Ge), bulk silicon germanium (SiGe) and/or bulk III-V semiconductor wafer. Alternatively, substrate202can be a semiconductor-on-insulator (SOI) wafer. A SOI wafer includes a SOI layer separated from an underlying substrate by a buried insulator. When the buried insulator is an oxide it is also referred to herein as a buried oxide or BOX. The SOI layer can include any suitable semiconductor, such as Si, Ge, SiGe, and/or a III-V semiconductor. Substrate202may already have pre-built structures (not shown) such as transistors, diodes, capacitors, resistors, interconnects, wiring, etc.

The stack204is formed by depositing sacrificial and active layers, one on top of another, onto the substrate202. According to an exemplary embodiment, the sacrificial and active layers in the stack204are nanosheets. The term ‘nanosheet’ as used herein generally refers to a sheet or a layer having nanoscale dimensions. Further, the term ‘nanosheet’ is meant to encompass other nanoscale structures such as nanowires. For instance, the term ‘nanosheet’ can refer to a nanowire with a larger width and/or the term ‘nanowire’ can refer to a nanosheet with a smaller width, and vice versa.

In the present example, the stack204includes a (first) sacrificial layer206deposited directly on the substrate202, and alternating (second) sacrificial layers208,208′,208″,208′″, etc. and active layers210,210′,210″, etc. deposited on the first sacrificial layer206. The term ‘sacrificial’ as used herein refers to a structure(s) (such as sacrificial layer206/sacrificial layers208,208′,208″,208′″, etc.) that is/are removed, in whole or in part, during fabrication of the fork sheet FET device. By contrast, as will be described in detail below, the active layers210,210′,210″, etc. will remain in place and serve as channels of the fork sheet FET device. It is notable that the number of sacrificial layers208,208′,208″,208′″, etc., and active layers210,210′,210″, etc. shown in the figures is merely provided as an example meant to illustrate the present techniques, and embodiments are contemplated herein where more or fewer sacrificial layers208,208′,208″,208′″, etc. and/or more or fewer active layers210,210′,210″, etc. are present in the stack204than is shown.

By way of example only, the sacrificial layer206and each of the sacrificial layers208,208′,208″,208′″, etc. and active layers210,210′,210″, etc. can be deposited on the substrate202using an epitaxial growth process. According to an exemplary embodiment, the sacrificial layer206and each of the sacrificial layers208,208′,208″,208′″, etc. and active layers210,210′,210″, etc. has a thickness of from about 6 nanometers (nm) to about 25 nm and ranges therebetween.

The materials employed for the sacrificial and active layers are such that the sacrificial layers208,208′,208″,208′″, etc. can be selectively removed relative to the active layers210,210′,210″, etc. later on in the process. Further, the materials employed for the first and second sacrificial layers are such that the sacrificial layer206can be selectively removed relative to the sacrificial layers208,208′,208″,208′″, etc. later on in the process. This will enable the formation of a bottom dielectric isolation layer. Advantageously, a bottom dielectric isolation layer prevents source/drain region leakage through the substrate202.

For instance, according to an exemplary embodiment, the sacrificial layer206and each of the sacrificial layers208,208′,208″,208′″, etc. is formed from SiGe, while each of the active layers210,210′,210″, etc. is formed from Si. In that case, etchants such as wet hot SC1, vapor phase hydrogen chloride (HCl), vapor phase chlorine trifluoride (ClF3) and other reactive clean processes (RCP) can be employed for the selective removal of the SiGe sacrificial layers relative to the Si active layers.

Further, high germanium (Ge) content SiGe can be selectively removed relative to low Ge content SiGe using an etchant such as dry HCL. Thus, according to an exemplary embodiment, the sacrificial layer206is formed from SiGe having a high Ge content, whereas each of the sacrificial layers208,208′,208″,208′″, etc. is formed from SiGe having a low Ge content. By way of example only, SiGe having a high Ge content is considered herein to be SiGe having from about 50% Ge to about 100% Ge (i.e., pure Ge) and ranges therebetween. For instance, in one non-limiting example, the sacrificial layer206is formed from SiGe60 (which is SiGe having a Ge content of about 60%). By contrast, SiGe having a low Ge content is considered herein to be SiGe having from about 20% Ge to about 50% Ge and ranges therebetween. For instance, in one non-limiting example, each of the sacrificial layers208,208′,208″,208′″, etc. is formed from SiGe30 (which is SiGe having a Ge content of about 30%). This configuration will enable the sacrificial layer206to be selectively removed relative to the sacrificial layers208,208′,208″,208′″, etc. during formation of the bottom dielectric isolation layer (see below).

As highlighted above, the stack204is then patterned. Patterning of the stack204will enable shallow trench isolation (STI) regions to be formed in the substrate202at the base of the NFET and PFET stacks. Standard lithography and etching techniques can be employed to pattern the stack204. With standard lithography and etching processes, a lithographic stack (not shown), e.g., photoresist/anti-reflective coating (ARC)/organic planarizing layer (OPL), is used to pattern a hardmask212on the stack204. Suitable hardmask materials include, but are not limited to, nitride hardmask materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), and/or oxide hardmask materials such as silicon oxide (SiOx). Alternatively, the hardmask212can be formed by other suitable techniques, including but not limited to, sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and other self-aligned multiple patterning (SAMP).

An etch is then used to transfer the pattern from the hardmask212to the sacrificial and active layers of the stack204and partway through the underlying substrate202. A directional (anisotropic) etching process such as reactive ion etching (RIE) can be employed for the stack204/substrate202etch. As shown inFIG.2B, trenches214are now present in the substrate202at a base of the (patterned) stack204.

An NFET-to-PFET space304is then opened in the stack204. SeeFIG.3A(an X-X′ cross-sectional view) andFIG.3B(a Y1-Y1′ and Y2-Y2′ cross-sectional view). To do so, a patterned block mask302can first be formed on the stack204. An etch can then be used to transfer the pattern from the block mask302to the hardmask212and underlying stack204, forming the NFET-to-PFET space304in the stack204. Suitable materials for the block mask302include, but are not limited to, organic planarizing layer (OPL) materials which can be deposited onto the stack204using a casting process such as spin-on coating or spray coating, chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD). Standard lithography and etching techniques (see above) can be employed to pattern the block mask302.

A directional (anisotropic) etching process such as RIE can be employed for the NFET-to-PFET space304etch. The NFET-to-PFET space304divides the stack204into at least one NFET device stack204N and at least one PFET device stack204P. As shown inFIG.3B, the NFET device stack204N and the PFET device stack204P are separated from one another by the NFET-to-PFET space304. It is notable that the process depicted inFIGS.3A and3Bis merely one illustrative, non-limiting embodiment contemplated herein for forming the NFET-to-PFET space304. Namely, in accordance with the present techniques, the NFET-to-PFET space304can be formed using any other suitable lithography or similar patterning process.

A sacrificial material is then deposited into, and filling the NFET-to-PFET space304forming a sacrificial pillar402separating the NFET device stack204N and the PFET device stack204P, after which the block mask302is removed and STI regions404are formed in the trenches214at the base of the NFET/PFET device stacks204N/204P. SeeFIG.4(a Y1-Y1′ and Y2-Y2′ cross-sectional view). Suitable sacrificial materials for the sacrificial pillar402include, but are not limited to, aluminum oxide (AlOx), silicon carbide (SiC) and/or titanium oxide (TiOx), which can be deposited into the NFET-to-PFET space304using a process such as CVD, ALD or PVD. Following deposition, an etch back of the sacrificial material can be performed using a plasma dry etch process. As provided above, the block mask302can be formed from an OPL material. In that case, the block mask302can be removed using an ashing process.

According to an exemplary embodiment, STI regions404are formed by filling trenches214with a dielectric material such as an oxide material (also referred to herein generally as an ‘STI oxide’) and then recessing the STI oxide. Although not explicitly shown in the figures, a liner (e.g., a thermal oxide or silicon nitride (SiN)) may be deposited into the trenches214prior to the STI oxide. Suitable STI oxides include, but are not limited to, silicon oxide (SiOx). A process such as CVD, ALD, or PVD can be employed to deposit the STI oxide into the trenches214. Following deposition, an oxide-selective etch can then be used to recess the STI oxide.

To form the sacrificial gates504, a sacrificial material is first blanket deposited over the NFET and PFET device stacks204N and204P. Suitable sacrificial materials include, but are not limited to, poly-silicon (poly-Si) and/or amorphous silicon (a-Si), which can be deposited using a process such as CVD, ALD or PVD. Although not shown in the figures, a thin (e.g., from about 1 nanometer (nm) to about 5 nm) layer of silicon oxide (SiOx) is preferably first formed on the NFET and PFET device stacks204N and204P, followed by deposition of the poly-Si and/or a-Si.

Standard lithography and etching techniques (see above) are then used to pattern sacrificial gate hardmasks502on the sacrificial material marking the footprint and location of each of the sacrificial gates504. Suitable materials for the sacrificial gate hardmasks502include, but are not limited to, nitride hardmask materials such as SiN, SiON and/or silicon carbide nitride (SiCN), and/or oxide hardmask materials such as SiOx. Alternatively, the sacrificial gate hardmasks502can be formed by other suitable techniques, including but not limited to, SIT, SADP, SAQP, and other SAMP. An etch is then used to transfer the pattern from the sacrificial gate hardmasks502to the sacrificial material, forming the individual sacrificial gates504. A directional (anisotropic) etching process such as RIE can be employed for the sacrificial gate etch.

As highlighted above, sacrificial gates504will be removed later on in the process and replaced with replacement gates that will serve as the final gates of the fork sheet FET device. This is referred to as a ‘gate-last’ approach since the replacement gates are formed last, near the end of the process. Use of a gate-last approach is advantageous because it prevents exposure of the metal gate stack materials to potentially damaging conditions during subsequent processing steps. For instance, the high-κ dielectrics used in the replacement gates can become damaged by exposure to high temperatures during formation of the source/drain regions. Thus, with this scheme, the metal gate stack materials are only placed near the end of the process.

A bottom dielectric isolation layer will be formed in the cavity506below the NFET and PFET device stacks204N and204P (see below). The bottom dielectric isolation layer will serve to prevent source/drain region leakage through the substrate202. Cavity506is formed by the selective removal of the sacrificial layer206. As provided above, sacrificial layer206can be formed from high Ge content SiGe (e.g., SiGe having from about 50% Ge to about 100% Ge (i.e., pure Ge) and ranges therebetween, such as SiGe60). In that case, an etchant such as dry HCl can be used to selectively remove the sacrificial layer206to form the cavity506.

A dielectric spacer material is deposited over the sacrificial gates504and into/filling the cavity506, followed by a directional (anisotropic) etching process such as RIE that is used to pattern the dielectric spacer material into a bottom dielectric isolation layer602in the cavity506and gate spacers604alongside the sacrificial gate hardmasks502/sacrificial gates504. SeeFIG.6A(an X-X′ cross-sectional view),FIG.6B(a Y1-Y1′ cross-sectional view) andFIG.6C(a Y2-Y2′ cross-sectional view). Suitable dielectric spacer materials include, but are not limited to, SiOx, SiC, silicon oxycarbide (SiCO) and/or SiN, which can be deposited using a process such as CVD, ALD or PVD.

The sacrificial gate hardmasks502/sacrificial gates504and gate spacers604are then used as a mask to pattern trenches702in the NFET and PFET device stacks204N and204P in between the sacrificial gates504. SeeFIG.7A(an X-X′ cross-sectional view) andFIG.7B(a Y1-Y1′ cross-sectional view). A directional (anisotropic) etching process such as RIE can be employed for the trench etch. As shown inFIGS.7A and7B, the trenches702extend through each of the sacrificial layers208,208′,208″,208′″, etc. and active layers210,210′,210″, etc., stopping on the bottom dielectric isolation layer602.

Next, inner spacers802are first formed alongside the sacrificial layers208,208′,208″,208′″, etc., after which NFET and PFET source/drain regions804and806are formed in the trenches702on opposite sides of the sacrificial gates504alongside the sacrificial layers208,208′,208″,208′″, etc. and active layers210,210′,210″, etc. in the NFET and PFET device stacks204N and204P, respectively. SeeFIG.8A(an X-X′ cross-sectional view) andFIG.8B(a Y1-Y1′ cross-sectional view). To form the inner spacers802, a selective lateral etch is performed to recess the sacrificial layers208,208′,208″,208′″, etc. exposed along the sidewalls of trenches702. As shown inFIG.8A, this recess etch forms pockets along the sidewalls of the trenches702that are then filled with a spacer material to form the inner spacers802within the pockets. These inner spacers802will serve to offset the replacement gates from the NFET/PFET source/drain regions804/806(see below).

As provided above, sacrificial layers208,208′,208″,208′″, etc. can be formed from SiGe. In that case, a SiGe-selective non-directional (isotropic) etching process such as a wet chemical etch or gas phase etch can be employed for the recess etch to form the pockets. Suitable materials for the inner spacers802include, but are not limited to, SiN, SiOx, SiC and/or SiCO, which can be deposited into the pockets using a process such as CVD, ALD or PVD. Following deposition, excess inner spacer material can be removed from the trenches702using an isotropic etching process such as wet etch or selective dry etch.

According to an exemplary embodiment, the NFET/PFET source/drain regions804/806are formed from an in-situ doped (i.e., where dopants are introduced during growth) or ex-situ doped (e.g., where dopants are introduced via ion implantation) epitaxial material such as epitaxial Si, epitaxial SiGe, etc. Suitable n-type dopants include, but are not limited to, phosphorous (P) and/or arsenic (As). Suitable p-type dopants include, but are not limited to, boron (B). It is notable that, with the inner spacers802in place along the sidewalls of the trenches702, epitaxial growth of the NFET/PFET source/drain regions804/806is templated only from the ends of the active layers210,210′,210″, etc. in the NFET/PFET device stacks204N/204P exposed along the sidewalls of the trenches702. As shown inFIGS.8A and8B, the NFET/PFET source/drain regions804/806are separated from the substrate202by the bottom dielectric isolation layer602.

As shown inFIG.8B, the NFET/PFET source/drain regions804/806are disposed on opposite sides of the sacrificial pillar402. However, the sacrificial pillar402is taller than the NFET/PFET source/drain regions804/806, such that the NFET/PFET source/drain regions804/806are present alongside a bottom portion810of the sacrificial pillar402, and a top portion812of the sacrificial pillar402above the NFET/PFET source/drain regions804/806is exposed. To look at it another way, the NFET/PFET source/drain regions804/806are not present alongside that top portion812of the sacrificial pillar402.

The top portion812of the sacrificial pillar402that is exposed above the NFET/PFET source/drain regions804/806is next trimmed. SeeFIG.9(a Y1-Y1′ cross-sectional view). The (trimmed) top portion of the sacrificial pillar402is now given the reference numeral812a. A non-directional (i.e., isotropic) etching process such as a wet chemical etch or gas phase etch can be employed to trim the top portion812aof the sacrificial pillar402. Trimming the top portion812aof the sacrificial pillar402reduces its width, i.e., relative to the bottom portion810of the sacrificial pillar402. Namely, as shown inFIG.9, the bottom portion810of the sacrificial pillar402has a width W1SACRIFICIAL PILLARand the (trimmed) top portion812aof the sacrificial pillar402has a width W2SACRIFICIAL PILLAR, whereby W2SACRIFICIAL PILLARis less than W1SACRIFICIAL PILLAR, i.e., W2SACRIFICIAL PILLAR<W1SACRIFICIAL PILLAR. As will be described in detail below, this trimming of the sacrificial pillar402in this manner will advantageously enable a replacement spacer to be formed in its place containing an airgap. More specifically, the trimmed top portion812aof the sacrificial pillar402serves to create a bottle neck that gets pinched off before the underlying space can be fully filled, thereby creating an airgap. It is notable that, during the trimming, there may be some minimal loss in height of the top portion812aof the sacrificial pillar402. This effect is, however, inconsequential. Further, the trimming of the sacrificial pillar402at this stage occurs between the NFET/PFET source/drain regions804/806, thereby enabling the present airgap pillar to be formed between the NFET/PFET source/drain regions804/806. As will be described in detail below, a trimming of the sacrificial pillar402(presently under the sacrificial gates504) will also be undertaken to enable formation of the present airgap pillar between the NFET/PFET gates as well.

An interlayer dielectric (ILD)1002is then deposited over, and burying, the NFET/PFET device stacks204N/204P (and sacrificial pillar402therebetween), sacrificial gates504and gate spacers604, and the NFET/PFET source/drain regions804/806. SeeFIG.10A(an X-X′ cross-sectional view),FIG.10B(a Y1-Y1′ cross-sectional view) andFIG.10C(a Y2-Y2′ cross-sectional view). Suitable ILD1002materials include, but are not limited to, oxide low-κ materials such as SiOx and/or oxide ultralow-κ interlayer dielectric (ULK-ILD) materials, e.g., having a dielectric constant κ of less than 2.7. By comparison, silicon dioxide (SiO2) has a dielectric constant κ value of 3.9. Suitable ULK-ILD materials include, but are not limited to, porous organosilicate glass (pSiCOH). A process such as CVD, ALD, or PVD can be employed to deposit the ILD1002. Following deposition, the ILD1002can be polished using a process such as chemical mechanical polishing (CMP). According to an exemplary embodiment, the ILD1002is polished down to the sacrificial gates504, removing the sacrificial gate hardmasks502. Doing so will enable the sacrificial gates504to be selectively removed relative to the ILD1002for replacement by the gates (see below).

As highlighted above, a trimming of the sacrificial pillar402between the NFET/PFET gates is also conducted. Since this portion of the sacrificial pillar402is presently under the sacrificial gates504, a partial recess of the sacrificial gates504is first performed to expose the top portion812of the sacrificial pillar402in this region. SeeFIG.11A(an X-X′ cross-sectional view) andFIG.11B(a Y2-Y2′ cross-sectional view). A selective etching process such as RIE can be employed for the recess etch of the sacrificial gates504. As shown inFIGS.11A and11B, by only partially recessing the sacrificial gates504the underlying NFET and PFET device stacks204N and204P will remain covered and thus protected during the trimming of the sacrificial pillar402.

As shown inFIG.11B, the NFET and PFET device stacks204N and204P are disposed on opposite sides of the sacrificial pillar402. However, the sacrificial pillar402is taller than the NFET and PFET device stacks204N and204P, such that the NFET and PFET device stacks204N and204P are present alongside the bottom portion810of the sacrificial pillar402, and the top portion812of the sacrificial pillar402above the NFET and PFET device stacks204N and204P is exposed. To look at it another way, the NFET and PFET device stacks204N and204P are not present alongside that top portion812of the sacrificial pillar402.

The top portion812of the sacrificial pillar402that is exposed above the NFET and PFET device stacks204N and204P is next trimmed. SeeFIG.12(a Y2-Y2′ cross-sectional view). As above, the (trimmed) top portion of the sacrificial pillar402is given the reference numeral812a. A non-directional (i.e., isotropic) etching process such as a wet chemical etch or gas phase etch can be employed to trim the top portion812aof the sacrificial pillar402. In the same manner as described above, trimming the top portion812aof the sacrificial pillar402reduces its width, i.e., relative to the bottom portion810of the sacrificial pillar402. Namely, as shown inFIG.12, the bottom portion810of the sacrificial pillar402has the width W1SACRIFICIAL PILLARand the (trimmed) top portion812aof the sacrificial pillar402has the width W2SACRIFICIAL PILLAR, whereby W2′ is less than W1SACRIFICIAL PILLAR, i.e., W2SACRIFICIAL PILLAR<W1SACRIFICIAL PILLAR. As will be described in detail below, this trimming of the sacrificial pillar402in this manner will advantageously enable a replacement spacer to be formed in its place containing an airgap by creating a bottle neck that gets pinched off before the underlying space can be fully filled. It is notable that, during the trimming, there may be some minimal loss in height of the top portion812aof the sacrificial pillar402. This effect is, however, inconsequential. The top portion812aof the sacrificial pillar402has now been trimmed in both the source/drain region of the fork sheet FET device (i.e., between the NFET/PFET source/drain regions804/806) and in the gate region of the fork sheet FET device (i.e., between the NFET and PFET device stacks204N and204P) which, as highlighted above, will advantageously enable formation of the present airgap pillar between the NFET/PFET source/drain regions804/806and between the NFET/PFET gates.

The remainder of the sacrificial gates504is then selectively removed forming gate trenches1302in the ILD1002over the NFET and PFET device stacks204N and204P in between the NFET/PFET source/drain regions804/806, respectively. SeeFIG.13A(an X-X′ cross-sectional view) andFIG.13B(a Y2-Y2′ cross-sectional view). As shown inFIGS.13A and13B, the sacrificial layers208,208′,208″,208′″, etc., now accessible through the gate trenches1302, are also removed. Removal of the sacrificial layers208,208′,208″,208′″, etc. releases the active layers210,210′,210″, etc. from the NFET and PFET device stacks204N and204P. Gaps1304are now present in the NFET and PFET device stacks204N and204P in between the active layers210,210′,210″, etc. The active layers210,210′,210″, etc. will serve as the channels of the fork sheet FET device. Releasing the active layers210,210′,210″, etc. from the NFET and PFET device stacks204N and204P will enable the replacement gates to be formed surrounding at least a portion of the channels (i.e., active layers210,210′,210″, etc.) in a gate-all-around or GAA configuration.

Replacement gates1402are then formed in the gate trenches1302and gaps1304. SeeFIG.14A(an X-X′ cross-sectional view) andFIG.14B(a Y2-Y2′ cross-sectional view). As shown in magnified view1404, according to an exemplary embodiment, each of the replacement gates1402includes a gate dielectric1408and a gate conductor1410disposed on the gate dielectric1408. Although not explicitly shown in the figures, a thin (e.g., from about 0.3 nm to about 5 nm) interfacial oxide (e.g., silicon oxide (SiOx) which may include other chemical elements in it such as nitrogen (N), germanium (Ge), etc.) can first be formed on exposed surfaces of the active layers210,210′,210″, etc., and the gate dielectric1408can then be deposited over the interfacial oxide using a process such as CVD, ALD, or PVD.

Suitable materials for the gate dielectric1408include, but are not limited to, silicon oxide (SiOx), SiN, silicon oxynitride (SiOxNy), high-κ materials, or any combination thereof. The term “high-κ” as used herein refers to a material having a relative dielectric constant κ which is much higher than that of silicon dioxide (e.g., a dielectric constant κ is about 25 for hafnium oxide (HfO2) rather than 3.9 for SiO2). Suitable high-κ materials include, but are not limited to, metal oxides such as HfO2, hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiOxNy), tantalum oxide (TaOx), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3) and/or lead zinc niobite (Pb(Zn,Nb)O). The high-κ material can further include dopants such as lanthanum (La), aluminum (Al) and/or magnesium (Mg). The gate dielectric1408can be deposited using a process or combination of processes such as, but not limited to, thermal oxidation, chemical oxidation, thermal nitridation, plasma oxidation, plasma nitridation, CVD, ALD, etc. According to an exemplary embodiment, the gate dielectric1408has a thickness of from about 1 nm to about 5 nm and ranges therebetween.

Suitable materials for the gate conductor1410include, but are not limited to, doped polysilicon and/or at least one workfunction-setting metal. Suitable workfunction-setting metals include, but are not limited to, titanium nitride (TiN), titanium aluminum nitride (TiAlN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium carbide (TiC) titanium aluminum carbide (TiAlC), tantalum carbide (TaC) and/or hafnium carbide (HfC). The gate conductor1410can be deposited using a process or combination of processes such as, but not limited to, CVD, ALD, PVD, sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, etc. According to an exemplary embodiment, the gate conductor1410has a thickness of from about 5 nm to about 15 nm and ranges therebetween. In the exemplary embodiment shown illustrated inFIGS.14A and14B, the gate conductor1410includes at least one layer1410aof the above workfunction-setting metal(s) and a (low-resistance) fill metal1410bdisposed over the layer(s)1410aof workfunction-setting metal(s) so as to fill in any remaining space in the replacement gates1402. Suitable low-resistance fill metals include, but are not limited to, tungsten (W) and/or aluminum (Al) which can be deposited using a process or combination of processes such as, but not limited to, CVD, ALD, PVD, sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, etc. As shown inFIGS.14A and14B, the replacement gates1402, i.e., gate dielectric1408and gate conductor1410, fully surround at least a portion of each of the active layers210,210′,210″, etc. in a gate-all-around configuration.

The replacement gates1402, i.e., gate dielectric1408and gate conductor1410, are then recessed and dielectric caps1502are formed over the (recessed) replacement gates1402. SeeFIG.15A(an X-X′ cross-sectional view),FIG.15B(a Y1-Y1′ cross-sectional view) andFIG.15C(a Y2-Y2′ cross-sectional view). Suitable dielectric cap materials include, but are not limited to, SiOx and/or SiN, which can be deposited using a process such as CVD, ALD or PVD. Following deposition, the dielectric cap material can be planarized using a process such as CMP. As shown inFIG.15B, the ILD1002is also recessed during polishing of the dielectric caps1502, thereby exposing a top of the sacrificial pillar402in the source/drain region of the fork sheet FET device. As shown inFIG.15C, the polishing of the dielectric caps1502also exposes the top of the sacrificial pillar402in the gate region of the fork sheet FET device. Exposing the top of the sacrificial pillar402will enable the sacrificial pillar402to be selectively removed and replaced with the (replacement) airgap pillar.

Namely, the sacrificial pillar402is next selectively removed, forming an opening1602in between the NFET and PFET source/drain regions804and806in the source/drain region of the fork sheet FET device, and in between the replacement gates1402over the NFET and PFET device stacks204N and204P in the gate region of the fork sheet FET device. SeeFIG.16A(a Y1-Y1′ cross-sectional view) andFIG.16B(a Y2-Y2′ cross-sectional view). Based on the above-described process, the opening1602formed by removal of the sacrificial pillar402has a unique shape. Namely, by trimming the top portion of the sacrificial pillar402as described above, a bottom portion1604of the opening1602has a width W1OPENINGand a top portion1606of the opening1602has a width W2OPENING, whereby W2OPENINGis less than W1OPENING, i.e., W2OPENING<W1OPENING. This configuration of having a narrow top through which the opening1602will be filled, serves to create a bottle neck for the filling process that gets pinched off before the bottom portion1604of the opening1602can be fully filled, thereby creating an airgap.

For instance, a conformal dielectric liner1702is next deposited into and lining the opening1602. SeeFIG.17A(a Y1-Y1′ cross-sectional view) andFIG.17B(a Y2-Y2′ cross-sectional view). Based on the narrowed inlet at the top portion1606of the opening1602, though which the conformal dielectric liner1702is being deposited, the top portion1606of the opening1602will become pinched off before the bottom portion1604of the opening1602is fully filled by the dielectric liner1702. As shown inFIGS.17A and17B, the dielectric liner1702deposited in this manner will line the bottom portion1604of the opening1602, and fully surrounding an airgap1704at the center the bottom portion1604of the opening1602which is the present dielectric airgap pillar1706. Suitable materials for the dielectric liner1702include, but are not limited to, SiOx, SiN, SiON and/or SiCN, which can be deposited into the opening1602using a process such as CVD, ALD or PVD. Following deposition, excess material can be removed using a process such as CMP.

As shown inFIGS.17A and17B, based on the unique shape of opening1602, a bottom portion1708of the dielectric airgap pillar1706has a width W1AIRGAP PILLARand a top portion1710of the dielectric airgap pillar1706has a width W2AIRGAP PILLAR, whereby W2AIRGAP PILLARis less than W1AIRGAP PILLAR, i.e., W2AIRGAP PILLAR<W1AIRGAP PILLAR. The dielectric airgap pillar1706is disposed directly between the NFET and PFET nanosheet devices shown, in this particular example, to the right and to the left of the dielectric airgap pillar1706, respectively. The nanosheets (i.e., active layers210,210′,210″, etc.) of the NFET and PFET nanosheet devices extend horizontally on opposite sides of the dielectric airgap pillar1706.

Specifically, as shown inFIG.17A, the dielectric airgap pillar1706directly contacts, and separates the NFET and PFET source/drain regions804and806in the source/drain region of the fork sheet FET device. As shown inFIG.17B, the dielectric airgap pillar1706directly contacts, and separates the replacement gates1402over the NFET and PFET device stacks204N and204P (also referred to herein as ‘the NFET gates and PFET gates,’ respectively) in the gate region of the fork sheet FET device. As provided above, implementing the dielectric airgap pillar1706in this manner between the NFET and PFET devices greatly reduces capacitance coupling in the present fork sheet FET design.