Duty cycle corrector

A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a first phase and a second phase and to obtain a first threshold value based on the length of the first phase and part of the second phase and provide a first pulse and response to the first threshold value. The second circuit is configured to receive the clock signal and to obtain a second threshold value based on the length of the second phase and part of the first phase and provide a second pulse in response to the second threshold value. The time between the start of the first pulse and the start of the second pulse is substantially one half clock cycle.

BACKGROUND

Many digital circuits receive a clock signal to operate. One type of circuit that receives a clock signal to operate is a memory circuit, such as a dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), or double data rate synchronous dynamic random access memory (DDR-SDRAM). In a memory circuit operating at high frequencies, it is important to have a clock signal that has about a 50% duty cycle. This provides the memory circuit with approximately an equal amount of time on the high level phase and the low level phase of a clock cycle for transferring data, such as latching rising edge data and latching falling edge data into and out of the memory circuit.

Typically, a clock signal is provided by an oscillator, such as a crystal oscillator, and clock circuitry. The oscillator and clock circuitry often provide a clock signal that does not have a 50% duty cycle. For example, the clock signal may have a 45% duty cycle, where the high level phase is 45% of one clock cycle and the low level phase is the remaining 55% of the clock cycle. To correct or change the duty cycle of a clock signal, a duty cycle corrector provides signals with transitions separated by substantially one half of a clock cycle.

Typically, analog and digital duty cycle correctors receive many clock cycles to achieve duty cycle correction. In analog duty cycle correctors, it is difficult to keep accumulated charges for an extended length of time. Even in power saving mode, clock signals are provided to the analog duty cycle corrector to update the accumulated charges. Thus, even in power saving mode, the analog duty cycle corrector remains operable and clock buffers remain enabled, which continuously consumes power. In digital duty cycle correctors, fine delay units are difficult to make and complex control logic is needed to increase correction speed.

SUMMARY

One aspect of the present invention provides a duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a first phase and a second phase and to obtain a first threshold value based on the length of the first phase and part of the second phase and provide a first pulse and response to the first threshold value. The second circuit is configured to receive the clock signal and to obtain a second threshold value based on the length of the second phase and part of the first phase and provide a second pulse in response to the second threshold value. The time between the start of the first pulse and the start of the second pulse is substantially one half clock cycle.

DETAILED DESCRIPTION

FIG. 1is a block diagram illustrating one embodiment of an electronic system20according to the present invention. Electronic system20includes a host22and a memory circuit24. Host22is electrically coupled to memory circuit24via memory communications path26. Host22can be any suitable electronic host, such as a computer system including a microprocessor or a microcontroller. Memory circuit24can be any suitable memory, such as a memory that utilizes a clock signal to operate. In one embodiment, memory circuit24comprises a random access memory, such as a dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), or double data rate synchronous dynamic random access memory (DDR-SDRAM).

Memory circuit24includes a duty cycle corrector28that receives a clock signal CLK at30and an inverted clock signal bCLK at32. Clock signal CLK at30is the inverse of inverted clock signal bCLK at32. In one embodiment, duty cycle corrector28receives clock signal CLK at30and/or inverted clock signal bCLK at32via memory communications path26. In other embodiments, duty cycle corrector28receives clock signal CLK at30and/or inverted clock signal bCLK at32from any suitable device, such as a dedicated clock circuit that is situated inside or outside memory circuit24.

Duty cycle corrector28provides output signals OUTPUT1at34and OUTPUT2at36. Each of the output signals, OUTPUT1at34and OUTPUT2at36, includes a series of pulses. One pulse is provided in output signal OUTPUT1at34and one pulse is provided in output signal OUTPUT2at36during each clock cycle in clock signal CLK at30and inverted clock signal bCLK at32. Each pulse in output signal OUTPUT1at34starts substantially one clock cycle after the start of another pulse in output signal OUTPUT1at34. Also, each pulse in output signal OUTPUT1at34starts substantially one half clock cycle after the start of a pulse in output signal OUTPUT2at36. Each pulse in output signal OUTPUT2at36starts substantially one clock cycle after the start of another pulse in output signal OUTPUT2at36. Also, each pulse in output signal OUTPUT2at36starts substantially one half clock cycle after the start of a pulse in output signal OUTPUT1at34. Duty cycle corrector28receives clock signal CLK at30and inverted clock signal bCLK at32, which may not have 50% duty cycles, and provides pulses that are substantially one half clock cycle apart. Memory circuit24receives pulse edges that are substantially one half clock cycle apart in output signals OUTPUT1at34and OUTPUT2at36and transfers data in and out of memory circuit24.

FIG. 2is a block diagram illustrating one embodiment of a duty cycle corrector28according to the present invention. Duty cycle corrector28includes a first phase mixer52and a second phase mixer54. Phase mixer52and phase mixer54each include an early input E, a late input L, and an output O.

The early input E of phase mixer52receives clock signal CLK at56and the late input L of phase mixer52receives inverted clock signal bCLK at58. The early input E of phase mixer54receives inverted clock signal bCLK at58and the late input L of phase mixer54receives clock signal CLK at56. Clock signal CLK at56is the inverse of inverted clock signal bCLK at58. Output O of phase mixer52provides pulses in output signal OUTPUT1at60and output O of phase mixer54provides pulses in output signal OUTPUT2at62.

One pulse is provided in output signal OUTPUT1at60and one pulse is provided in output signal OUTPUT2at62during each clock cycle of clock signal CLK at56and inverted clock signal bCLK at58. Each pulse in output signal OUTPUT1at60starts one clock cycle after the start of another pulse in output signal OUTPUT1at60, and one half clock cycle after the start of a pulse in output signal OUTPUT2at62. Each pulse in output signal OUTPUT2at62starts one clock cycle after the start of another pulse in output signal OUTPUT2at62, and one half clock cycle after the start of a pulse in output signal OUTPUT1at60.

FIG. 3is a diagram illustrating one embodiment of a phase mixer52. Phase mixer52includes early input E that receives clock signal CLK at102and late input L that receives inverted clock signal bCLK at104. Also, phase mixer52includes output O that provides output signal OUTPUT1at106, which is fed back into phase mixer52at108and110. Phase mixer54(shown inFIG. 2) is similar to phase mixer52and includes early input E that receives inverted clock signal bCLK and late input L that receives clock signal CLK. Also, phase mixer54includes output O that provides output signal OUTPUT2, which is fed back into phase mixer54similar to the way output signal OUTPUT1at106is fed back into phase mixer52at108and110.

Phase mixer52includes an early signal control circuit112, a late signal control circuit114, an output circuit116, and a charge circuit118. Early signal control circuit112and late signal control circuit114control charge circuit118to charge output circuit116. In addition, early signal control circuit112and late signal control circuit114control the discharge of output circuit116.

Early signal control circuit112includes an early signal inverter120, an output signal inverter122, a first NAND gate124, a second NAND gate126, and an early signal n-channel metal oxide semiconductor (NMOS) transistor128. The input of early signal inverter120receives clock signal CLK at102and the output of early signal inverter120is electrically coupled at130to one input of first NAND gate124. The input of output signal inverter122receives output signal OUTPUT1at108and the output of output signal inverter122is electrically coupled at132to one input of second NAND gate126.

First NAND gate124and second NAND gate126are coupled in a latch configuration with the output of second NAND gate126electrically coupled at134to the other input of first NAND gate124, and the output of first NAND gate124electrically coupled at136to the other input of second NAND gate126. Also, the output of first NAND gate124is electrically coupled at136to the gate of early signal NMOS transistor128and to charge circuit118. In addition, one side of the drain-source path of early signal NMOS transistor128is electrically coupled at138to output circuit116, charge circuit118, and late signal control circuit114. The other side of the drain-source path of early signal NMOS transistor128is electrically coupled to a reference, such as ground, at140.

Late signal control circuit114includes a first late signal inverter142, a second late signal inverter144, a first NOR gate146, a second NOR gate148, and a late signal NMOS transistor150. The input of first late signal inverter142receives inverted clock signal bCLK at104and the output of first late signal inverter142is electrically coupled at152to one input of first NOR gate146. Another input of first NOR gate146receives output signal OUTPUT1at110. The input of second late signal inverter144receives inverted clock signal bCLK at104and the output of second late signal inverter144is electrically coupled at154to one input of second NOR gate148.

First NOR gate146and second NOR gate148are coupled in a latch configuration with the output of second NOR gate148electrically coupled at156to the third input of first NOR gate146, and the output of first NOR gate146electrically coupled at158to the other input of second NOR gate148. Also, the output of first NOR gate146is electrically coupled at158to the gate of late signal NMOS transistor150and to charge circuit118. In addition, one side of the drain-source path of late signal NMOS transistor150is electrically coupled at138to output circuit116, charge circuit118, and the one side of the drain-source path of early signal NMOS transistor128. The other side of the drain-source path of late signal NMOS transistor150is electrically coupled to the reference, such as ground, at140.

Output circuit116includes a capacitor160and an output inverter162. One side of capacitor160is electrically coupled at138to the input of output inverter162and to charge circuit118. Also, this one side of capacitor160is electrically coupled at138to the drain-source path of early signal NMOS transistor128and to the drain-source path of late signal NMOS transistor150. The other side of capacitor160is electrically coupled to the reference at140. The output of output inverter162provides the output signal OUTPUT1at106.

Charge circuit118includes a first p-channel metal oxide semiconductor (PMOS) transistor164and a second PMOS transistor166. One side of the drain-source path of second PMOS transistor166is electrically coupled to power VCC at168. The other side of the drain-source path of second PMOS transistor166is electrically coupled at170to one side of the drain-source path of first PMOS transistor164. The other side of the drain-source path of first PMOS transistor164is electrically coupled at138to one side of capacitor160and the input of output inverter162. Also, this side of the drain-source path of first PMOS transistor164is electrically coupled at138to the drain-source path of early signal NMOS transistor128and to the drain-source path of late signal NMOS transistor150. The gate of first PMOS transistor164is electrically coupled at136to the output of first NAND gate136, and the gate of second PMOS transistor166is electrically coupled at158to the output of first NOR gate146.

In operation, output inverter162provides a high logic level output signal OUTPUT1at106if capacitor160is discharged to a voltage value that is below the threshold voltage of output inverter162. Output signal inverter122receives the high logic level output signal OUTPUT1at108and provides a low logic level to second NAND gate126that provides a high logic level to first NAND gate124. If clock signal CLK at102is at a low logic level, early signal inverter120provides a high logic level to first NAND gate124and with both inputs at high logic levels, first NAND gate124provides a low logic level output that turns off early signal NMOS transistor128and turns on first PMOS transistor164.

With clock signal CLK at102at a low logic level, inverted clock signal bCLK at104is at a high logic level. First late signal inverter142provides a low logic level to first NOR gate146and second late signal inverter144provides a low logic level to second NOR gate148. With the output signal OUTPUT1at a high logic level, first NOR gate146provides a low logic level to the other input of second NOR gate148and with both inputs at logic low levels, second NOR gate148provides a high logic level to first NOR gate146. Also, the low logic level output of first NOR gate146turns off late signal NMOS transistor150and turns on second PMOS transistor166.

Since first and second PMOS transistors164and166are turned on and early and late signal NMOS transistors128and150are turned off, capacitor160charges to a high voltage level. As the voltage value on capacitor160rises above the threshold voltage of output inverter162, output inverter162transitions to provide a low logic level output signal OUTPUT1at106.

Output signal inverter122receives the low logic level output signal OUTPUT1at108and provides a high logic level to second NAND gate126. Since the other input of second NAND gate126is at a low logic level, the output of second NAND gate126remains at a high logic level and the output of first NAND gate124remains at a low logic level. Also, first NOR gate146receives the low logic level output signal OUTPUT1at110. Since the output of second NOR gate148is at a high logic level, the output of first NOR gate remains at a low logic level. Thus, first and second PMOS transistors164and166remain turned on and early and late signal NMOS transistors128and150remain turned off.

Next, clock signal CLK at102transitions to a high logic level and inverted clock signal bCLK at104transitions to a low logic level. The output of early signal inverter120transitions from a high logic level to a low logic level and first NAND gate124transitions to provide a high logic level that turns on early signal NMOS transistor128and turns off first PMOS transistor164. This terminates charging of capacitor160and begins discharging capacitor160via early signal NMOS transistor128. The high logic level from first NAND gate124and the high logic level from output signal inverter122are received by second NAND gate126that provides a low logic level that latches in the high logic level output of first NAND gate124.

The output of first late signal inverter142transitions to a high logic level and the output of first NOR gate146remains at a low logic level. Also, the output of second late signal inverter144transitions to a high logic level and the output of second NOR gate148transitions to a low logic level that is provided to first NOR gate146. The output of first NOR gate146remains at the low logic level.

Next, clock signal CLK at102transitions to a low logic level and inverted clock signal bCLK at104transitions to a high logic level. At this time, capacitor160is discharging via early signal NMOS transistor128and the voltage value on capacitor160remains above the threshold value of output inverter162. The output signal OUTPUT1at108remains at a low logic level and the output of output signal inverter122remains at a high logic level. The output of first NAND gate124is at a high logic level and with both inputs at high logic levels, second NAND gate126continues to provide a low logic level to first NAND gate124. The output of early signal inverter120transitions from a low logic level to a high logic level, but first NAND gate124remains at the high logic level latched in by the low logic level provided by second NAND gate126.

The output of first late signal inverter142transitions to a low logic level, while the output signal OUTPUT1at110remains at a low logic level and the output of second NOR gate148remains at a low logic level. With all three inputs at low logic levels, the output of first NOR gate146transitions to a high logic level that is provided to second NOR gate148. In this embodiment, the output of first late signal inverter142is configured to transition to a low logic level and the output of first NOR gate146is configured to transition to a high logic level before the output of second late signal inverter144transitions to a low logic level. The output of second late signal inverter144transitions to a low logic level and the output of second NOR gate148remains at a low logic level due to the high logic level provided by first NOR gate146. The high logic level provided by first NOR gate146turns on late signal NMOS transistor150and turns off first PMOS transistor166. Capacitor160is discharged via early signal NMOS transistor128and late signal NMOS transistor150, which discharges capacitor160at twice the discharge rate provided by discharging capacitor160via only early signal NMOS transistor128.

The voltage value on capacitor160decreases below the threshold voltage of output inverter162and output signal OUTPUT1at106transitions to a high logic level. Output signal inverter122receives output signal OUTPUT1at108and provides a low logic level to second NAND gate126that transitions to provide a high logic level to one of the inputs of first NAND gate124. Clock signal CLK at102is at a low logic level and early signal inverter120provides a high logic level to the other input of first NAND gate124. With both inputs at high logic levels, first NAND gate124transitions to provide a low logic level that turns off early signal NMOS transistor128and turns on first PMOS transistor164. Turning off early signal NMOS transistor128terminates discharging of capacitor160via early signal NMOS transistor128. The low logic level of first NAND gate124is provided to second NAND gate126to latch in the high logic level of second NAND gate126.

First NOR gate146receives the high logic level output signal OUTPUT1at110and provides a low logic level that turns off late signal NMOS transistor150and turns on second PMOS transistor166. Turning off late signal NMOS transistor150terminates discharging of capacitor160via late signal NMOS transistor150. Since first and second PMOS transistors164and166are turned on and early and late signal NMOS transistors128and150are turned off, capacitor160charges to a high voltage level.

The low logic level of first NOR gate146is provided to one input of second NOR gate148. Inverted clock signal bCLK at104is at a high logic level and second late signal inverter144provides a low logic level to the other input of second NOR gate148. With both inputs at low logic levels, second NOR gate148provides a high logic level to first NOR gate146to latch in the low logic level output of first NOR gate146.

As the voltage value on capacitor160rises above the threshold voltage of output inverter162, the output of output inverter162transitions to provide a low logic level output signal OUTPUT1at106. Output signal inverter122receives the low logic level output signal OUTPUT1at108and provides a high logic level to second NAND gate126. With the other input of second NAND gate126at a low logic level, the output of second NAND gate126remains at a high logic level. First NOR gate146receives the low logic level output signal OUTPUT1at110. With second NOR gate148providing a high logic level, the output of first NOR gate146remains at a low logic level. Thus, output inverter162transitions from a low logic level to a high logic level and back to a low logic level to provide a pulse for each cycle of clock signal CLK at102and inverted clock signal bCLK at104.

In another clock cycle, at the rising edge of clock signal CLK at102, early signal control circuit112begins to discharge capacitor160and at the rising edge of inverted clock signal bCLK at104, late signal control circuit114also discharges capacitor160. The voltage value on capacitor160is discharged below the threshold voltage of output inverter162and output inverter162transitions to a high logic level that begins the charging of capacitor160. As the voltage value on capacitor160rises above the threshold voltage of output inverter162, the output of output inverter162transitions to provide a low logic level output signal OUTPUT1at106and phase mixer52is ready for the next clock cycle.

Phase mixer54(shown inFIG. 2) is similar to phase mixer52. However, phase mixer54includes an early input E that receives inverted clock signal bCLK and a late input L that receives clock signal CLK. The pulse provided by phase mixer54is one half clock cycle away from the pulse provided by phase mixer52.

FIG. 4is a timing diagram illustrating the operation of phase mixer52ofFIG. 3. Clock signal CLK at200is provided to the early input E of phase mixer52and inverted clock signal bCLK at202is provided to the late input L of phase mixer52. The output of first NAND gate124is EARLY OUTPUT at204and the output of first NOR gate146is LATE OUTPUT at206. The output of output inverter162is output signal OUTPUT1at208and the voltage on capacitor160is the CAPACITOR VOLTAGE signal at210.

At time0, clock signal CLK at200transitions to a high logic level at212and inverted clock signal bCLK at202transitions to a low logic level at214. Early signal inverter120transitions to a low logic level and EARLY OUTPUT at204, which is the output of first NAND gate124, transitions to a high logic level at216. The high logic level at216turns on early signal NMOS transistor128and turns off first PMOS transistor164, which terminates charging of capacitor160and begins discharging of capacitor160via early signal NMOS transistor128. The CAPACITOR VOLTAGE at210that was charged to a voltage value of about VCC at218, discharges at a discharge rate of S at220.

The output of first late signal inverter142transitions to a high logic level and the output of first NOR gate146remains at a low logic level. Also, the output of second late signal inverter144transitions to a high logic level and the output of second NOR gate148transitions to a low logic level that is provided to first NOR gate146. The output of first NOR gate146remains at the low logic level.

At time TH, clock signal CLK at200transitions to a low logic level at222and inverted clock signal bCLK at202transitions to a high logic level at224. At226, the CAPACITOR VOLTAGE at210remains above the threshold value VTH at228of output inverter162and output signal OUTPUT1at208remains at a low logic level.

The output of output signal inverter122remains at a high logic level and EARLY OUTPUT at204remains at a high logic level. With both inputs at high logic levels, second NAND gate126provides a low logic level to first NAND gate124. The output of early signal inverter120transitions from a low logic level to a high logic level, but EARLY OUTPUT at204remains at the high logic level due to the low logic level provided by second NAND gate126.

The output of first late signal inverter142transitions to a low logic level, while the output signal OUTPUT1at208remains at a low logic level and the output of second NOR gate148remains at a low logic level. With all three inputs at low logic levels, LATE OUTPUT at206, which is the output of first NOR gate146, transitions to a high logic level at230. The high logic level at230turns on late signal NMOS transistor150and turns off first PMOS transistor166. Capacitor160is discharged via early signal NMOS transistor128and late signal NMOS transistor150and the CAPACITOR VOLTAGE at210discharges at twice the discharge rate or 2S at232.

At time TPS, the CAPACITOR VOLTAGE at210crosses at234the threshold voltage VTH at228and output signal OUTPUT1at208transitions to a high logic level at236. Output signal inverter122receives output signal OUTPUT1at208and provides a low logic level to second NAND gate126that transitions to provide a high logic level to one of the inputs of first NAND gate124. Clock signal CLK at200is at a low logic level and early signal inverter120provides a high logic level to the other input of first NAND gate124. With both inputs at high logic levels, EARLY OUTPUT at204transitions to a low logic level at238that turns off early signal NMOS transistor128and turns on first PMOS transistor164.

First NOR gate146receives the high logic level output signal OUTPUT1at208and LATE OUTPUT206provides a low logic level at240that turns off late signal NMOS transistor150and turns on second PMOS transistor166. As first and second PMOS transistors164and166are turned on and early signal and late signal NMOS transistors128and150are turned off, CAPACITOR VOLTAGE at210continues to discharge at242and begins to charge to a high voltage level at244.

The low logic level of LATE OUTPUT at206is provided to one input of second NOR gate148. Inverted clock signal bCLK at202is at a high logic level and second late signal inverter144provides a low logic level to the other input of second NOR gate148. With both inputs at low logic levels, second NOR gate148provides a high logic level to first NOR gate146to latch in the low logic level LATE OUTPUT at206.

At time TPE, the CAPACITOR VOLTAGE at210crosses at246the threshold voltage VTH at228and output signal OUTPUT1at208transitions to a low logic level at248. Output signal inverter122receives the low logic level output signal OUTPUT1at208and provides a high logic level to second NAND gate126. With EARLY OUTPUT at204that is the other input of second NAND gate126at a low logic level, the output of second NAND gate126remains at a high logic level. Also, first NOR gate146receives the low logic level output signal OUTPUT1at208and with second NOR gate148providing a high logic level, LATE OUTPUT at206, which is the output of first NOR gate146, remains at a low logic level. Thus, output signal OUTPUT1at208provides a pulse that starts at time TPS and ends at time TPE. Output signal OUTPUT1at208transitions from a low logic level to a high logic level at230and back to a low logic level at240to provide a pulse for each clock cycle of clock signal CLK at200and inverted clock signal bCLK at202. The CAPACITOR VOLTAGE at210charges to a high voltage at250of VCC.

In another clock cycle, at time TCLK, clock signal CLK at200transitions to a high logic level at252and inverted clock signal bCLK at202transitions to a low logic level at254. Early signal inverter120transitions to a low logic level and EARLY OUTPUT at204, which is the output of first NAND gate124, transitions to a high logic level at256. The high logic level at256turns on early signal NMOS transistor128and turns off first PMOS transistor164, which terminates charging of capacitor160and begins discharging of capacitor160via early signal NMOS transistor128. The CAPACITOR VOLTAGE at210discharges at a discharge rate of S at258and the sequence of events continues as previously described to provide a pulse in output signal OUTPUT1at208that begins at a time TPS and ends at a time TPE after the start of the current clock cycle.

The time TPS from the start of the current clock cycle to the start of the pulse is the same for each clock cycle in clock signal CLK at200. During the time between time0and time TH, the CAPACITOR VOLTAGE at210discharges a voltage value D1as described in Equation I.
D1=S*THEquation I

where, S is the discharge rate and TH is the discharge time.

During the time between time TH and time TPS, the CAPACITOR VOLTAGE at210discharges a voltage value D2as described in Equation II.
D2=(2*S)*(TPS−TH)  Equation II

where, (2*S) is the discharge rate and (TPS−TH) is the discharge time.

The voltage discharged between time0and time TPS is described in Equation III.
VCC−VTH=D1+D2  Equation III

where, capacitor160is charged to the high voltage level of VCC and discharged to the threshold voltage VTH of output inverter162at time TPS.

Substituting for voltage values D1and D2in Equation III and reducing results in Equation IV.
VCC−VTH=(2*S*TPS)−(S*TH)  Equation IV

Solving for TPS in Equation IV, results in Equation V.
TPS=(((VCC−VTH)/S)+TH)/2  Equation V

The time TPS is a function of the high voltage level VCC, threshold voltage VTH, discharge rate S and the length TH of the high level phase of clock signal CLK at200. Each of these values is a constant for phase mixer52and clock signal CLK at200that has a steady duty cycle. As a result, one pulse in output signal OUTPUT1at208occurs one clock cycle away from the next pulse in output signal OUTPUT1at208.

FIG. 5is a timing diagram illustrating the operation of duty cycle corrector28ofFIG. 2. Duty cycle corrector28includes phase mixer52ofFIG. 3and phase mixer54that is similar to phase mixer52. Phase mixer52includes an early input E that receives clock signal CLK at300and a late input L that receives inverted clock signal bCLK at302. Phase mixer54includes an early input E that receives inverted clock signal bCLK at302and a late input L that receives clock signal CLK at300.

Each of the phase mixers52and54includes a capacitor that is charged and discharged to provide the capacitor voltage signals CAPACITORS VOLTAGES at304. Phase mixer52provides output signal OUTPUT1at306and phase mixer54provides output signal OUTPUT2at308. Each of the output signals, OUTPUT1at306and OUTPUT2at308, includes one pulse per clock cycle of clock signal CLK at300and inverted clock signal bCLK at302. Each pulse provided by phase mixer54is one half clock cycle from a pulse provided by phase mixer52and each pulse provided by phase mixer52is one half clock cycle from a pulse provided by phase mixer54.

At time0, clock signal CLK at300transitions to a high logic level at310and inverted clock signal bCLK at302transitions to a low logic level at312. In phase mixer52, early signal inverter120transitions to a low logic level and the output of first NAND gate124transitions to a high logic level that turns on early signal NMOS transistor128and turns off first PMOS transistor164. This terminates charging of capacitor160and begins discharging of capacitor160via early signal NMOS transistor128. The voltage on capacitor160in phase mixer52, which was charged to a voltage value of about VCC at314, discharges at a discharge rate of S at316.

At time TH, clock signal CLK at300transitions to a low logic level at318and inverted clock signal bCLK at302transitions to a high logic level at320. At322, the voltage on capacitor160in phase mixer52remains above the threshold value VTH at324of output inverter162in phase mixer52and output signal OUTPUT1at306remains at a low logic level. The output of first late signal inverter142in phase mixer52transitions to a low logic level, while the output signal OUTPUT1at306remains at a low logic level and the output of second NOR gate148remains at a low logic level. With all three inputs at low logic levels, the output of first NOR gate146transitions to a high logic level that turns on late signal NMOS transistor150and turns off first PMOS transistor166. Capacitor160is discharged via early signal NMOS transistor128and late signal NMOS transistor150at twice the discharge rate or 2S at326.

In phase mixer54at time TH, the early signal inverter transitions to a low logic level and the output of the first NAND gate transitions to a high logic level that turns on the early signal NMOS transistor and turns off the first PMOS transistor. This terminates charging of the capacitor in phase mixer54and begins discharging the capacitor via the early signal NMOS transistor. The voltage on the capacitor in phase mixer54, which was charged to a voltage value of about VCC at314, discharges at a discharge rate of S at328.

At time TPS1, the voltage on capacitor160in phase mixer52crosses at330the threshold voltage VTH at324and output signal OUTPUT1at306transitions to a high logic level to provide a pulse at332.

At time TCLK, clock signal CLK at300transitions to a high logic level at334and inverted clock signal bCLK at302transitions to a low logic level at336. At338, the voltage on the capacitor in phase mixer54remains above the threshold value VTH at324of the output inverter in phase mixer54and output signal OUTPUT2at308remains at a low logic level. The output of the first late signal inverter transitions to a low logic level, while the output signal OUTPUT2at308remains at a low logic level and the output of the second NOR gate remains at a low logic level. With all three inputs at low logic levels, the output of the first NOR gate transitions to a high logic level that turns on the late signal NMOS transistor and turns off the first PMOS transistor. The capacitor in phase mixer54is discharged via the early signal NMOS transistor and the late signal NMOS transistor at twice the discharge rate or 2S at340.

In phase mixer52at time TCLK, early signal inverter120transitions to a low logic level and the output of first NAND gate124transitions to a high logic level that turns on early signal NMOS transistor128and turns off first PMOS transistor164. This terminates charging of capacitor160and begins discharging of capacitor160via early signal NMOS transistor128. The voltage on capacitor160in phase mixer52, which was charged to a voltage value of about VCC at314, discharges at a discharge rate of S at342.

At time TPS2, the voltage on the capacitor in phase mixer54crosses at344the threshold voltage VTH at324and output signal OUTPUT2at308transitions to a high logic level to provide a pulse at346. The voltage on capacitor160in phase mixer52continues to discharge at the discharge rate of S at342and the sequence repeats itself.

The rising edge of the pulse at346is at time TPS2and the rising edge of the pulse at332is at time TPS1. The time between the rising edge of the pulse at346and the rising edge of the pulse at332is one half clock cycle. The time TPS1is the same as time TPS in Equation V, where D1and D2inFIG. 4are the same as D1and D2inFIG. 5. During the time between time TH and time TCLK, the capacitor in phase mixer54discharges the voltage value D3in Equation VI.
D3=S*(TCLK−TH)  Equation VI

where, S is the discharge rate that is the same as the discharge rate S in Equation I and (TCLK-TH) is the discharge time.

During the time between time TCLK and time TPS2, the capacitor in phase mixer54discharges the voltage value D4in Equation VII.
D4=(2*S)*(TPS2−TCLK)  Equation VII

where, (2*S) is the discharge rate and (TPS2-TCLK) is the discharge time.

The voltage discharged between time TH and time TPS2is in Equation VIII.
VCC−VTH=D3+D4  Equation VIII

where, the capacitor in phase mixer54is charged to the high voltage level of VCC and discharged to the threshold voltage VTH of the output inverter in phase mixer54at time TPS2. The threshold voltage VTH of the output inverter in phase mixer54is the same as the threshold voltage VTH of output inverter162in phase mixer52.

Substituting for voltage values D3and D4in Equation VIII and reducing results in Equation IX.
VCC−VTH=(2*S*TPS2)−(S×TH)−(S*TCLK)  Equation VII

Solving for TPS2in Equation IX, results in Equation X.
TPS2=(((VCC−VTH)/S)+TH+TCLK)/2  Equation X

Subtracting TPS1, which is TPS in Equation V, from TPS2in Equation X, results in Equation XI.
(((VCC−VTH)/S)+TH+TCLK)/2−(((VCC−VTH)/S)+TH)/2=TCLK/2  Equation XI

where, TCLK is the length of a clock cycle and TCLK/2 is one half of a clock cycle.

Thus, the time between the rising edge of the pulse at346and the rising edge of the pulse at332is one half clock cycle. Also, the time between any adjacent pulses in output signals OUTPUT1and OUTPUT2is one half clock cycle. Duty cycle corrector28corrects the duty cycle of incoming clock signals by providing rising edges that are one half clock cycle apart for a duty cycle of 50%.

FIG. 6is a diagram illustrating one embodiment of a duty cycle corrector400according to the present invention. Duty cycle corrector400is similar to duty cycle corrector28ofFIG. 2. Duty cycle corrector400includes a first phase mixer402, a second phase mixer404, a first delay circuit406, and a second delay circuit408. First phase mixer402is similar to first phase mixer52(shown inFIGS. 2 and 3) and second phase mixer404is similar to second phase mixer54(shown inFIG. 2). Phase mixer402and phase mixer404each include an early input E, a late input L, and an output O.

The input of delay circuit406receives clock signal CLK at410and provides delayed clock signal CLKD at412. The input of delay circuit408receives inverted clock signal bCLK at414and provides delayed inverted clock signal bCLKD at416. Clock signal CLK at410is the inverse of inverted clock signal bCLK at414.

The early input E of phase mixer402receives delayed clock signal CLKD at412and the late input L of phase mixer402receives inverted clock signal bCLK at414. The early input E of phase mixer404receives delayed inverted clock signal bCLKD at416and the late input L of phase mixer404receives clock signal CLK at410. Output O of phase mixer402provides pulses in output signal OUTPUT1at418and output O of phase mixer404provides pulses in output signal OUTPUT2at420.

One pulse is provided in output signal OUTPUT1at418and one pulse is provided in output signal OUTPUT2at420during each clock cycle of clock signal CLK at410and inverted clock signal bCLK at414. Each pulse in output signal OUTPUT1at418starts substantially one clock cycle after the start of another pulse in output signal OUTPUT1at418, and substantially one half clock cycle after the start of a pulse in output signal OUTPUT2at420. Each pulse in output signal OUTPUT2at420starts substantially one clock cycle after the start of another pulse in output signal OUTPUT2at420, and substantially one half clock cycle after the start of a pulse in output signal OUTPUT1at418.

Phase mixer402receives delayed clock signal CLKD at412and inverted clock signal bCLK at414. In operation, the rising edge of delayed clock signal CLKD at412occurs prior to the rising edge of inverted clock signal bCLK at414to begin discharging the capacitor in phase mixer402. The rising edge of delayed clock signal CLKD at412occurs closer to the rising edge of inverted clock signal bCLK at414, than does the rising edge of clock signal CLK at410that was delayed to provide the rising edge of delayed clock signal CLKD at412. By receiving delayed clock signal CLKD at412, instead of clock signal CLK at410, at the early input E, phase mixer402provides a pulse after a shorter mixing time than duty cycle corrector28. Also, receiving delayed clock signal CLKD at412, instead of clock signal CLK at410, at the early input E provides more time for pre-charging the capacitor in phase mixer402before the next rising edge of delayed clock signal CLKD at412begins discharging the capacitor.

Phase mixer404receives delayed inverted clock signal bCLKD at416and clock signal CLK at410. In operation, the rising edge of delayed inverted clock signal bCLKD at416occurs prior to the rising edge of clock signal CLK at410to begin discharging the capacitor in phase mixer404. The rising edge of delayed inverted clock signal bCLKD at416occurs closer to the rising edge of clock signal CLK at410, than does the rising edge in inverted clock signal bCLK at414that was delayed to provide the rising edge of delayed inverted clock signal bCLKD at416. By receiving delayed inverted clock signal bCLKD at416, instead of inverted clock signal bCLK at414, at the early input E, phase mixer404provides a pulse after a shorter mixing time than duty cycle corrector28. Also, receiving delayed inverted clock signal bCLKD at416, instead of inverted clock signal bCLK at414, at the early input E provides more time for pre-charging the capacitor in phase mixer404before the next rising edge of delayed inverted clock signal bCLKD at416begins discharging the capacitor.

FIG. 7is a timing diagram illustrating the operation of duty cycle corrector400ofFIG. 6. Duty cycle corrector400includes phase mixer402and phase mixer404. Phase mixer402includes an early input E that receives delayed clock signal CLKD at500and a late input L that receives inverted clock signal bCLK at502. Phase mixer404includes an early input E that receives delayed inverted clock signal bCLKD at504and a late input L that receives clock signal CLK at506.

Phase mixer402provides output signal OUTPUT1at508and phase mixer404provides output signal OUTPUT2at510. Each of the output signals, OUTPUT1at508and OUTPUT2at510, includes one pulse per clock cycle of clock signal CLK at506and inverted clock signal bCLK at502. Each pulse provided by phase mixer404is one half clock cycle from a pulse provided by phase mixer402and each pulse provided by phase mixer402is one half clock cycle from a pulse provided by phase mixer404.

At time0, delayed clock signal CLKD at500transitions to a high logic level at512and inverted delayed clock signal bCLKD at504transitions to a low logic level at514. The output of the early signal inverter in phase mixer402transitions to a low logic level and the output of the first NAND gate in phase mixer402transitions to a high logic level, which turns on the early signal NMOS transistor and turns off the first PMOS transistor. This terminates charging of the capacitor and begins the discharging of the capacitor in phase mixer402via the early signal NMOS transistor.

At time TH1, clock signal CLK at506transitions to a low logic level at516and inverted clock signal bCLK at502transitions to a high logic level at518. The output of the first NOR gate transitions to a high logic level that turns on the late signal NMOS transistor and turns off the first PMOS transistor. The capacitor in phase mixer402is discharged via the early signal NMOS transistor and the late signal NMOS transistor. At time TPS1, the voltage on the capacitor in phase mixer402crosses the threshold voltage of the output inverter and output signal OUTPUT1at508transitions to a high logic level to provide a pulse at520.

At time TDH, delayed clock signal CLKD at500transitions to a low logic level at522and inverted delayed clock signal bCLKD at504transitions to a high logic level at524. The output of the early signal inverter in phase mixer404transitions to a low logic level and the output of the first NAND gate in phase mixer404transitions to a high logic level, which turns on the early signal NMOS transistor and turns off the first PMOS transistor. This terminates charging of the capacitor and begins the discharging of the capacitor in phase mixer404via the early signal NMOS transistor.

At time TCLK, inverted clock signal bCLK at502transitions to a low logic level at526and clock signal CLK at506transitions to a high logic level at528. The output of the first NOR gate in phase mixer404transitions to a high logic level that turns on the late signal NMOS transistor and turns off the first PMOS transistor. The capacitor in phase mixer404is discharged via the early signal NMOS transistor and the late signal NMOS transistor. At time TPS2, the voltage on the capacitor in phase mixer404crosses the threshold voltage of the output inverter and output signal OUTPUT2at510transitions to a high logic level to provide a pulse at530.

At time TDL, delayed clock signal CLKD at500transitions to a high logic level at532and inverted delayed clock signal bCLKD at504transitions to a low logic level at534. The output of the early signal inverter in phase mixer402transitions to a low logic level and the output of the first NAND gate in phase mixer402transitions to a high logic level, which turns on the early signal NMOS transistor and turns off the first PMOS transistor. This terminates charging of the capacitor and begins the discharging of the capacitor in phase mixer402via the early signal NMOS transistor.

At time TH2, clock signal CLK at506transitions to a low logic level at536and inverted clock signal bCLK at502transitions to a high logic level at538. The output of the first NOR gate transitions to a high logic level that turns on the late signal NMOS transistor and turns off the first PMOS transistor. The capacitor in phase mixer402is discharged via the early signal NMOS transistor and the late signal NMOS transistor and the pulse sequence repeats in output signals, OUTPUT1at508and OUTPUT2at510.

One pulse is provided in output signal OUTPUT1at508and one pulse is provided in output signal OUTPUT2at510during each clock cycle of clock signal CLK at506and inverted clock signal bCLK at502. Each pulse in output signal OUTPUT1at508starts one clock cycle after the start of another pulse in output signal OUTPUT1at508, and one half clock cycle after the start of a pulse in output signal OUTPUT2at510. Each pulse in output signal OUTPUT2at510starts one clock cycle after the start of another pulse in output signal OUTPUT2at510, and one half clock cycle after the start of a pulse in output signal OUTPUT1at508.

Clock signal CLK at506is delayed almost one half clock cycle to provide delayed clock signal CLKD at500. The rising edge at512of delayed clock signal CLKD at500occurs less than one half clock cycle before the rising edge at518of inverted clock signal bCLK at502to begin discharging the capacitor in phase mixer402. By receiving delayed clock signal CLKD at500, instead of clock signal CLK at506, at the early input E, phase mixer402provides the pulse at520after a shorter mixing time between the rising edge at512and the rising edge at518, as compared to the longer mixing time between the rising edge (not shown) of clock signal CLK at506and the rising edge at518. Also, by receiving delayed clock signal CLKD at500, instead of clock signal CLK at506, at the early input E, the time for charging the capacitor in phase mixer402is increased to the time between the pulse at520and the delayed rising edge at532in the delayed clock signal CLKD at500, as compared to the time between the pulse at520and the rising edge at528in clock signal CLK at506.

Inverted clock signal bCLK at502is delayed almost one half clock cycle to provide delayed inverted clock signal bCLKD at504. The rising edge at524of delayed inverted clock signal bCLKD at504occurs less than one half clock cycle before the rising edge at528of clock signal CLK at506to begin discharging the capacitor in phase mixer404. By receiving delayed inverted clock signal bCLKD at504, instead of inverted clock signal bCLK at502, at the early input E, phase mixer404provides the pulse at530after a shorter mixing time between the rising edge at524and the rising edge at528, as compared to the longer mixing time between the rising edge at518of inverted clock signal bCLK at502and the rising edge at528. Also, by receiving delayed inverted clock signal bCLKD at504, instead of inverted clock signal bCLK at502, at the early input E, the time for charging the capacitor in phase mixer404is increased to the time between the pulse at530and the next rising edge in the delayed inverted clock signal bCLKD at504, as compared to the time between the pulse at530and the rising edge at538in inverted clock signal bCLK at502.