Local IO sense accelerator for increasing read/write data transfer speed

A memory array includes: at least one differential local bit line pair; at least one differential global bit line pair; at least a column selection signal, for charging the differential local bit line pair to a predetermined voltage; at least an enable signal for coupling the differential local bit line pair to the differential global bit line pair when a voltage of the differential local bit line pair reaches a specific value; and a local sense accelerator, coupled to the differential local bit line pair, for determining a voltage of the differential local bit line pair, and enabling an accelerator signal for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value.

BACKGROUND

The present application relates to a memory array, and more particularly, to a memory array comprising a local sense accelerator that can increase the speed of data transfer during read and write processes.

A conventional semiconductor memory array contains both global (or “main”) word and bit lines and local (or “sub”) word and bit lines. Read and write processes are performed by transferring data from the global bit lines to the local bit lines and vice versa. Access to the bit lines is facilitated by the word lines.

For example,FIG. 1illustrates a conventional memory array100. As shown in the diagram, the memory array100comprises differential local I/O lines, Lio and LioF, coupled to differential global I/O lines, Gio and GioF, by means of a plurality of transistors. For simplicity, only single differential pairs of global and local I/O lines are shown.

In operation, during a conventional read process, the local bit lines are pre-charged, meaning they contain a particular value. A column selection signal CSEL (see t0in timing diagram ofFIG. 2) is fired, which selects a specific word line. This causes the corresponding differential bit lines, Lio and LioF, to “mature,” meaning that one line discharges such that separation between Lio and LioF occurs (see Lio/LioF between t0and t2in timing diagram ofFIG. 2). The lines have to reach a predetermined separation for a read process to begin (see t1in timing diagram ofFIG. 2). This separation frequently is about 300 mV. Therefore the memory array100also includes a current sense amplifier. This current sense amplifier detects a small current on the bit lines, converts the current to a voltage, and amplifies this voltage such that a stored value can be read from the memory. When the voltage reaches the minimum separation, the current sense amplifier fires a Read Enable signal (RdEn), which activates the transistors between the local and global lines, thereby allowing data transfer.

For a write process, values to be written to a local bit line are present on the global bit line. The CSEL signal (FIG. 2) is fired to select the appropriate word line, and the corresponding local bit lines begin to separate. When the current sense amplifier detects that the separation has reached approximately 300 mV, a write enable signal (WrEn) may be fired, which drives the global bit line values onto the local bit lines.

The timing of the CSEL signal and the corresponding separation of the bit lines for a read process is illustrated inFIG. 2. As shown in the diagram, the separation of the local bit lines is slow and gradual (see Lio/LioF at times t0, t1, andt2in timing diagram ofFIG. 2). Generally speaking, in order for fast read processes to occur, the voltage on the local bit lines should be as high as possible. In modern memory arrays, however, the circuit layout is often quite small, meaning that the current sense amplifier is also small and the amplification of the voltage is therefore limited.

Write processes are plagued by a similar set of problems. Additionally, an accepted phenomenon in the art is that as line length increases, so does line capacitance. In conventional memory arrays100, the local bit lines are quite long, and therefore have a relatively large line capacitance. This phenomenon contributes in turn to the slow separation of the differential local bit lines, Lio and LioF (as seen in the Lio/LioF lines ofFIG. 2), and thus causes a heavy loading problem when data is driven from the global bit lines, Gio and GioF, to the local bit lines, Lio and LioF.

In summary, characteristics of conventional memory design, such as the necessity for small sense amplifiers and the existence of line-based capacitances, induce inevitable problems with regards to read and write processes. It is therefore a priority in this field to design a system that can speed up the separation of the local bit lines.

SUMMARY

The systems and methods disclosed herein advantageously provide a memory array architecture that may accelerate separation between the local bit lines in order to increase the speed of read and write operations as well as reduce the power consumption of these processes.

In one embodiment, a memory array comprises: at least one differential local bit line pair; at least one differential global bit line pair; at least a column selection signal line, for charging the differential local bit line pair to a predetermined voltage; at least an enable signal line for coupling the differential local bit line pair to the differential global bit line pair when a voltage of the differential local bit line pair reaches a specific value; and a local sense accelerator, coupled to the differential local bit line pair, for determining a voltage of the differential local bit line pair, and enabling an accelerator signal line for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value.

In another embodiment, a method for accelerating data transfer in a memory array comprises: providing at least one differential local bit line pair; providing at least one differential global bit line pair; generating a column selection signal to charge the differential local bit line pair to a predetermined value; generating an enable signal to couple the differential local bit line pair to the differential global bit line pair when the voltage of the differential local bit line pair reaches a specific value; and enabling an accelerator signal for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value.

In another embodiment, a memory array with a local acceleration block includes: at least one differential local bit line pair, at least one differential global bit line pair coupled to the at least one differential local bit line pair, and at least one enable line coupled to either the local bit line pair or the global bit line pair. The local acceleration block is configured to selectively latch one of the differential local bit lines at a high voltage value while causing the other differential local bit line to go to a low voltage value.

These and other embodiments of the present application will be discussed more fully in the detailed description. The features and advantages may be achieved independently in various embodiments of the present application, or may be combined in yet other embodiments.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, and it is to be understood that other embodiments may be utilized and that various changes may be made without departing from the spirit and scope of the present application.

The present application discloses a new memory array layout that may eliminate many of the speed limitations inherent in conventional memory arrays. The systems and memories described herein promote rapid separation between the local bit lines, and thereby increase the speed of data transfer and reduce power consumption for both read and write processes.

FIG. 3illustrates one exemplary embodiment of a memory array layout300according to the current application. The memory array300includes differential local bit lines, Lio and LioF, coupled to differential global bit lines, Gio and GioF. A read enable and a write enable line are each coupled to a transistor pair on the differential global and local bit lines. The memory array300also includes a local sense accelerator305. The local sense accelerator305comprises two cross-coupled transistors,311and312, coupled between the local bit lines, Lio and LioF, further having their drains coupled to the source of a third transistor313which is then coupled to ground, and has a signal LSaEn line coupled to its gate. The cross-coupled transistors,311and312, are configured such that the gate of311is coupled to the source of312and to one of the differential local bit lines, while the gate of312is coupled to the source of311and the other differential local bit line.

In operation, the local sense accelerator305enables accelerated separation of the local bit lines during a read process. Initially, at a time t0, the column selection enable signal (CSEL) as shown inFIG. 4, is fired. This selects a specific word line and causes a separation of the local bit lines, Lio and LioF (see Lio/LioF lines at t0in the timing diagram ofFIG. 4). The cross-coupled transistors311and312sense the current present on the local bit lines, convert the current to a voltage, and amplify this signal. At this point, the grounded transistor313in the local sense accelerator305is inactive, or in a high impedance mode, so the local sense accelerator, or referred to more generally as a local acceleration block,305operates as a standard cross-coupled transistor pair.

When a predetermined threshold separation (typically about 300 mV) between the local bit lines, Lio and LioF, is reached, the local sense accelerator305causes the LSaEn signal to be fired, activating the grounded transistor313. As demonstrated by the Lio/LioF lines ofFIG. 4as between t0and t1, the line separation is initially gradual. Once activated, however, the third transistor313causes the cross-coupled transistors,311and312, to latch one of the Lio/LioF lines, while quickly pulling down the other line, as shown at t1in the timing diagram ofFIG. 4. The local bit lines, Lio and LioF, will therefore reach their maximum separation much faster than in the prior art. If the RdEn is fired at the same time as the LSaEn, the values present on the bit lines can be read quickly from the memory300, as shown at t1in the timing diagram ofFIG. 4.

For a write process, the local sense accelerator305functions in much the same way as a read process. Until a predetermined minimum separation of the local bit lines is reached, the memory array300will function as a conventional memory array. The write process is triggered when the CSEL fires a specific word line, as shown at t0in the timing diagram ofFIG. 5. This causes separation of the corresponding local bit lines to begin (see Lio/LioF at t0in timing diagram ofFIG. 5). Once the minimum separation is reached, the local sense accelerator305will fire the LSaEn signal, as shown at t1inFIG. 5, turning on the third transistor313and latching one of the local bit lines, Lio or LioF, at a high potential while the other bit line quickly reaches a low potential. This increases the voltage present on the bit lines so that the capacitance is decreased. Additionally, the loading for the write process is not as heavy as in the conventional art.

InFIG. 4, the RdEn is shown as being fired at the same time, t1, as the LSaEn. In practical terms, it may be desirable to have a slight delay between firing the LSaEn and the RdEn (or WrEn for a write process). This is because there may be a small delay between the LSaEn being fired and the latching and pulling down of the local bit lines by the local sense accelerator305. The exact value of this delay may be determined via simulation.

In conclusion, the local sense accelerator of the present application may increase the speed of read and write processes for a memory array, while reducing power consumption. In addition, the layout area for the memory array including the local sense accelerator does not need to be increased.

Although this application has been described in terms of certain preferred embodiments, those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the application. Accordingly, the scope of the present application is defined only by reference to the appended claims and equivalents thereof.