SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

An embodiment semiconductor device includes a conductive region extending in a first direction and a second direction intersecting the first direction and stacked in a third direction intersecting the first direction and the second direction and a termination region at an end of the conductive region in the first direction, wherein the termination region includes an n+ type substrate, an n− type layer disposed on an upper surface of the n+ type substrate and having a plurality of first trenches opening upward in the third direction, and a lower gate runner covering the plurality of first trenches and disposed on an upper surface of the n− type layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2023-0090824, filed on Jul. 13, 2023, which application is hereby incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and a method of manufacturing the same.

BACKGROUND

Semiconductor devices (MOSFET, JFET, MESFET, IGBT, etc.) are three-terminal devices that can conduct current through control of the gate terminal. In particular, power semiconductor devices for switching require high voltage and large current.

Semiconductor devices have different electrical characteristics depending on their structure, and appropriate devices are used depending on the application field. However, they commonly require high current density, low turn-on voltage, high breakdown voltage, low leakage current, and fast switching speed, and various structures have been proposed to simultaneously satisfy the above requirements.

However, the above electrical characteristics form a trade-off relationship, and structures for improving one or more characteristics while maintaining other characteristics by weakening the trade-off relationship are continuously being researched.

In particular, MOSFETs and IGBTs, which are mainly used as transistors in power conversion systems, are manufactured with a gate structure in the form of a trench as a method to reduce on-resistance, and even in the trench gate structure, the characteristics (current density and cell pitch) are improved through a buried gate where the gate polysilicon (Poly-Si) is not exposed to the surface.

SUMMARY

One embodiment of the present disclosure provides a semiconductor device and a method of manufacturing the same in which a cell density of a semiconductor device can be increased by reducing a cell pitch through a buried gate electrode structure in which the gate electrode is disposed only inside the trench, a buried gate electrode structure can be easily formed by using a gate recess process that is formed only by an etching process after deposition without forming a separate mask, and a lower gate runner can be formed by using a gate recess process, trenches with specific line widths and spacing, and a deposition method with a non-conformal step coverage.

A semiconductor device according to one embodiment includes a conductive region extending in a first direction and a second direction intersecting the first direction and stacked in a third direction intersecting the first direction and the second direction and a termination region at an end of the conductive region in the first direction.

The termination region includes an n+ type substrate, an n− type layer disposed on a third direction of the n+ type substrate and having a plurality of first trenches opening upward in the third direction, and a lower gate runner that covers the plurality of first trenches and is disposed on a third direction of the n− type layer.

The first direction spacing between the first trenches may be less than or equal to the first direction width of each of the first trenches.

The lower gate runner may have an upper portion that covers the plurality of first trenches and is disposed on a third direction of the plurality of first trenches and extended portions that are disposed inside each of the first trenches.

The extended portion may have a trench sidewall portion disposed on the sidewall of the first trench and a trench bottom portion disposed on the bottom of the first trench.

The trench sidewall portion may have a convex shape toward the inside of the first trench as it moves upward in the third direction.

The trench bottom portion may have a convex shape toward the inside of the first trench.

The first trench may have an empty space inside the first trench surrounded by an upper portion of the lower gate runner, a trench sidewall portion, and a trench bottom portion.

The empty space may have a shape whose width in the first direction becomes narrower as it moves upward in the third direction.

A gate lower insulation layer may be disposed between the first trench and an extended portion of the lower gate runner.

The semiconductor device is disposed within the n− type layer and may further include a p type region disposed on the side of the plurality of first trenches.

The termination region may further include an upper gate runner positioned on the lower gate runner.

The conductive region may include the n+ type substrate, an n− type layer disposed on the n+ type substrate in the third direction and having a second trench opening upward in the third direction, a p type region disposed within the n− type layer and disposed on a side of the second trench, a gate electrode disposed within the second trench, and a source electrode and a drain electrode disposed insulated from the gate electrode.

The gate electrode may be disposed only inside the second trench and may not protrude outside the second trench in the third direction.

The conductive region may further include a gate upper insulation layer that covers the gate electrode and is disposed on the third direction of the n− type layer.

A ratio of the first direction width of the first trench to the first direction width of the second trench may be less than or equal to about 0.9.

The first direction width of the second trench may be greater than or equal to about 0.1 μm.

A third direction depth of the second trench may be greater than or equal to about 0.5 μm.

The first direction width of the first trench may be about 0.1 μm to about 2 μm.

A third direction depth of the first trench may be greater than or equal to about 0.3 μm.

A semiconductor device according to another embodiment includes a conductive region extending in a first direction and a second direction intersecting the first direction and stacked in a third direction intersecting the first direction and the second direction and a termination region at an end of the conductive region in the first direction.

The termination region may include an n+ type substrate, an n− type layer disposed on a third direction of the n+ type substrate, a buffer layer disposed on a third direction of the n-type layer and having a plurality of first trenches opening upward in the third direction, and a lower gate runner that covers the plurality of first trenches and is disposed on the third direction of the buffer layer.

A method of manufacturing a semiconductor device according to another embodiment includes forming an n− type layer on a first direction and a third direction intersecting the second direction of an n+ type substrate extending in a first direction and a second direction intersecting the first direction, forming a plurality of first trenches opening upward in the third direction in the n− type layer, forming a preliminary gate electrode layer covering the plurality of first trenches and an upper portion of the n− type layer without filling all of the interior of the plurality of first trenches using a deposition method with a non-conformal step coverage, and etching a portion of the preliminary gate electrode layer that covers the n− type layer to form a lower gate runner that covers the plurality of first trenches and is disposed on a third direction of the n− type layer.

A third direction thickness of the portion covering the n− type layer of the preliminary gate electrode layer may be about 0.5 times or more than the first direction width of each of the plurality of first trenches.

The deposition method with a non-conformal step coverage may be a plasma-enhanced chemical vapor deposition (PECVD) method using a thermal evaporator.

The method of manufacturing a semiconductor device may further include forming a gate lower insulation layer inside the plurality of first trenches.

The method of manufacturing a semiconductor device may include forming a second trench that is open upward in a third direction in the n− type layer, forming a preliminary gate electrode layer that fills the inside of the second trench and covers the n− type layer using a deposition method with a non-conformal step coverage, etching a portion of the preliminary gate electrode layer covering the n− type layer until the upper surface of the preliminary gate electrode layer is disposed inside the second trench to form a gate electrode inside the second trench, and forming a source electrode and a drain electrode to be insulated from the gate electrode, respectively.

In the method of manufacturing a semiconductor device, a second trench may be formed together during the forming of the plurality of first trenches.

The method of manufacturing a semiconductor device may include, in the forming of the preliminary gate electrode layer, the preliminary gate electrode layer may cover the plurality of first trenches, fill all of the interior of the second trench, and cover the n− type layer without filling all of the interior of the plurality of first trenches.

In the method of manufacturing a semiconductor device, in the forming of the lower gate runner, a portion of the preliminary gate electrode layer covering the n− type layer may be etched until the upper surface of the preliminary gate electrode layer is disposed inside the second trench to form a gate electrode inside the second trench.

A method of manufacturing a semiconductor device may further include forming a gate upper insulation layer that covers a portion of the lower gate runner and forming an upper gate runner disposed on the gate upper insulation layer and connected to the lower gate runner exposed between the gate upper insulation layers.

In the semiconductor device and the manufacturing method thereof according to various embodiments, a cell density of a semiconductor device can be increased by reducing a cell pitch through a buried gate electrode structure in which the gate electrode is disposed only inside the trench, a buried gate electrode structure can be easily formed by using a gate recess process that is formed only by an etching process after deposition without forming a separate mask, and a lower gate runner can be formed by using a gate recess process, trenches with specific line widths and spacing, and a deposition method with a non-conformal step coverage.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The advantages, features, and aspects to be described hereinafter will become apparent from the following description of the embodiments with reference to the accompanying drawings, which is set forth hereinafter. However, the embodiments should not be construed as being limited to the embodiments set forth herein. Although not specifically defined, all of the terms including the technical and scientific terms used herein have meanings understood by ordinary persons skilled in the art. The terms defined in a generally used dictionary may not be interpreted ideally or exaggeratedly unless clearly defined. In addition, unless explicitly described to the contrary, the word “comprise”, and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

Further, the singular includes the plural unless mentioned otherwise.

In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Like reference numerals designate like elements throughout the specification.

Hereinafter, a semiconductor device1000according to one embodiment will be described with reference toFIGS.1to3.

FIG.1is a cross-sectional view of a semiconductor device1000according to one embodiment,FIG.2is an enlarged cross-section of area A ofFIG.1, andFIG.3is an enlarged cross-section of area B inFIG.1.

Referring toFIGS.1to3, the semiconductor device1000may extend in a first direction D1and a second direction D2intersecting the first direction D1and may be stacked in a third direction intersecting the first direction D1and the second direction D2. For example, the semiconductor device1000may extend in the first and second directions D1and D2and may have upper and lower surfaces facing each other in the third direction D3. That is, the first direction D1may be a width direction of the semiconductor device1000, the second direction D2may be an extension direction of the semiconductor device1000, and the third direction D3may be a thickness direction of the semiconductor device1000.

FIG.1is a cross-sectional view cut in the first direction D1and the third direction D3perpendicular to the second direction D2.

Referring toFIG.1, the semiconductor device1000includes a conductive region1100and a termination region1200. The conductive region1100is an area where current flows when a forward voltage is applied, and the termination region1200is an area disposed at the end of the conduction region1100in the first direction D1.

As an example, the conductive region1100of the semiconductor device1000includes an n+ type substrate100, an n− type layer200, a p type region400, a gate electrode700, a source electrode800, and a drain electrode900.

The n+ type substrate100extends in the first direction D1and the second direction D2and may have upper and lower surfaces facing each other in the third direction D3. As an example, the n+ type substrate100may be an n+ type silicon carbide (SiC) substrate.

The n− type layer200is disposed on the upper surface of the n+ type substrate100.

The n− type layer200of the conductive region1100has a second trench212. The second trench212is opened upward, that is, to the upper surface of the n− type layer200in the third direction D3.

The p type region400is disposed inside the n− type layer200and on the side of the second trench212, that is, next to the second trench212in the first direction D1.

An n+ type region500may be disposed inside the p type region400and on the side of the second trench212. Additionally, a p+ type region (not shown) may be disposed within the p type region400and may be disposed next to the n+ type region500in the first direction D1.

Inside the second trench212, a gate lower insulation layer620is disposed, and on the gate lower insulation layer620, the gate electrode700is disposed. The gate electrode700fills inside the second trench212. However, the gate electrode700may be a buried gate electrode700not protruded outside the second trench212, while the upper surface of the gate electrode700in the third direction D3is located inside the second trench212. This gate electrode700may reduce a cell pitch of the semiconductor device1000to increase cell density of the semiconductor device1000.

As an example, the gate electrode700may include polysilicon or metal.

A gate upper insulation layer630is disposed on the gate electrode700. The gate upper insulation layer630may be disposed on the n+ type region500, on the p+ type region (not shown), or on the p type region400.

The gate upper insulation layer630may include SiO2, Si2N3, SiN, Al2O3, PSG, USG, BSG, BPSG, or a combination thereof. In addition, the gate upper insulation layer630may include the same material as the gate lower insulation layer620.

On the gate upper insulation layer630, the source electrode800may be disposed. The source electrode800is insulated from the gate electrode700by the gate upper insulation layer630. The source electrode800may include an ohmic metal.

A drain electrode900is disposed on the lower surface of the n+ type substrate100. The drain electrode900may include an ohmic metal.

On the other hand, the termination region1200of the semiconductor device1000includes the n+ type substrate100, the n− type layer200, the p type region400, a p type termination structure450, a lower gate runner750, an upper gate runner760, and the drain electrode900.

The p type region400located on the side of the second trench212adjacent to the termination region1200extends to the termination region1200.

The p type region400of the termination region1200has a plurality of first trenches211. The plurality of first trenches211are opened upward, that is, to the upper surface of the p type region400in the third direction D3.FIG.1shows that the first trenches211are located in the p type region400, but embodiments of the present invention are not limited thereto, and the bottom surfaces of the first trenches211may be located inside the n− type layer200through the p type region400depending on a size of the first trenches211.

A gate lower insulation layer620may be disposed inside the first trench211. The gate lower insulation layer620may include SiO2, Si2N3, SiN, Al2O3, PSG, USG, BSG, BPSG, or a combination thereof.

The lower gate runner750is located on the n− type layer200in the third direction D3.

The lower gate runner750covers the plurality of first trenches211and is on the plurality of first trenches211in the third direction D3.

For example, the lower gate runner750may include polysilicon or metal.

The lower gate runner750covers the plurality of first trenches211and has an upper portion751on the plurality of first trenches211in the third direction D3and extended portions752and753located inside each of the first trenches211.

Herein, in the first trench211, one inner surface of the first trench211, which is generally horizontal with the surface of the p type region400and has a step of a predetermined depth downward in the third direction D3and a width in the first direction D1, may be defined as the bottom surface210of the trench, other inner surfaces of the first trench211, which connect the surface of the p type region400with the bottom surface of the first trench211, have a height in the third direction D3, and face each other in the first direction D1, may be defined as the sides of the first trench211, and a line, where one of the sides of the first trench211meets the surface of the p type region400, may be defined as an upper edge (corner) of the first trench211.

As described with reference toFIGS.5to8, since the semiconductor device1000according to one embodiment is manufactured by using a non-conformal step coverage deposition method in the step of forming a preliminary gate electrode layer700P, a deposition rate at the upper edge of the first trench211may be increased, resulting in overhang deposition. In other words, the deposition (growth) of the preliminary gate electrode layer700P proceeds around the upper edge of the first trench211.

Accordingly, spacing T1bbetween the plurality of first trenches211in the first direction D1may be smaller than or the same as a width Tia of each of the plurality of first trenches211in the first direction D1. In other words, as the plurality of first trenches211have a smaller line width and pitch, a deposition rate of the preliminary gate electrode layer700P centered on the upper edge of the first trench211may be increased during the non-conformal step coverage deposition.

In addition, a ratio of the first direction D1width Tia of the first trench211to the first direction D1width T2aof the second trench212may be less than or equal to about 0.9, less than or equal to about 0.8, less than or equal to about 0.7, less than or equal to about 0.6, less than or equal to about 0.5, less than or equal to about 0.4, less than or equal to about 0.3, or less than or equal to about 0.2, and may be greater than or equal to about 0.1, greater than or equal to about 0.2, greater than or equal to about 0.3, greater than or equal to about 0.4, greater than or equal to about 0.5, greater than or equal to about 0.6, greater than or equal to about 0.7, or greater than or equal to about 0.8. When the ratio of the first direction D1width Tia of the first trench211to the first direction D1width T2aof the second trench212is within the ranges, the deposition rate of the preliminary gate electrode layer700P centered on the upper edge of the first trench211may be increased during the non-conformal step coverage deposition.

Herein, the first direction D1width T2aof the second trench212may be greater than or equal to about 0.1 μm, the third direction D3depth of the second trench212may be greater than or equal to about 0.5 μm, the first direction D1width Tia of the first trench211may be about 0.1 μm to about 2 μm, and the third direction D3depth of the first trench211may be greater than or equal to about 0.3 μm.

Accordingly, before filling all inside the plurality of first trenches211, the openings of the plurality of first trenches211are closed during the deposition of the preliminary gate electrode layer700P, the upper portion751of the lower gate runner750is formed on the plurality of first trenches211, and the extended portions752and753of the lower gate runner750are formed inside each of the plurality of first trenches211.

In addition, the extended portions752and753of the lower gate runner750have the trench sidewall portion752located on the side wall of the first trench211and the trench bottom portion753located on the bottom surface of the first trench211. For example, the trench sidewall portion752may be a thin film disposed on the side surface of the first trench211, and the trench bottom portion753may be a thin film disposed on the bottom surface of the first trench211. The trench sidewall portion752and the trench bottom portion753may be connected or not connected to each other.

The trench sidewall portion752may have a convex shape toward the inside of the first trench211upward in the third direction D3. The reason is that as the non-conformal step coverage deposition method is used, the preliminary gate electrode layer700P is deposited (grown) to be centered on the upper edge of the first trench211and thus has a fan shape on the trench sidewall portion752below the upper edge of the first trench211.

The trench bottom portion753has a convex shape toward the first trench211. The reason is that as the non-conformal step coverage deposition method is used, since the preliminary gate electrode layer700P is deposited (grows) to be centered on the upper edge of the first trench211, the trench bottom portion753grows relatively less, wherein the trench bottom portion753grows much less at the inner edge where the bottom surface of the first trench211meets the side surface thereof relative to the center portion of the bottom surface in the first direction D1.

Before the preliminary gate electrode layer700P fills all inside the plurality of first trenches211, as the openings of the plurality of first trenches211are closed, each of the first trenches211may have an empty spaces or a void therein.

As the extended portions752and753of the lower gate runner750are located inside each of the plurality of first trenches211, the empty space may be surrounded with the upper portion751, the trench sidewall portion752, and the trench bottom portion753of the lower gate runner750.

In addition, the trench sidewall portion752may have a convex shape upward in the third direction D3toward the inside of the first trench211, wherein since the trench sidewall portions752located on both sidewalls inside the first trench211may meet each other at the top of the first trench211in the third direction D3, the empty space may have a shape of which the first direction D1width becomes narrower as it goes upward in the third direction D3.

The gate upper insulation layer630may be disposed on the lower gate runner750. The gate upper insulation layer630may not completely cover the lower gate runner750but may expose a portion of the lower gate runner750.

An upper gate runner760may be disposed on the gate upper insulation layer630and may be connected to the portion of the lower gate runner750exposed between the gate upper insulation layers630. The upper gate runner760may include the same material as the source electrode800.

The lower gate runner750and the upper gate runner760are to apply a gate voltage fast to the gate electrode700.

The p type termination structure450may be located in the n− type layer200of the termination region1200. The p type termination structure450may be located at the first direction D1side of the p type region400extended to the termination region1200.

For example, the p type termination structure450includes a plurality of regions to which p type ions are implanted, wherein the regions have a filled ring structure in which they are spaced apart from each other at a predetermined distance.

A thickness of the regions into which the p type ions are implanted and which form the p type termination structure450may be shallower than a depth of the second trench212. In addition, the thickness of the regions into which the p type ions are implanted and which form the p type termination structure450may be the same as that of the portion of the p type region400.

The gate upper insulation layer630may extend over the p type termination structure450and the n− type layer200of the termination region1200.

Hereinafter, the semiconductor device1000according to another embodiment will be described with reference toFIG.4.

FIG.4is a cross-sectional view corresponding toFIG.1illustrating the semiconductor device1000according to another embodiment.

Since the embodiment shown inFIG.4has many of the same parts as the embodiment shown inFIG.1, descriptions thereof will be omitted and the differences will be mainly explained.

FIG.1shows that the n− type layer200has the plurality of first trenches211, and the lower gate runner750is positioned on the n− type layer200.

FIG.2shows that the buffer layer610is disposed on the n− type layer200in the third direction D3and has the plurality of first trenches211opening upward in the third direction D3, and the lower gate runner750is positioned on the buffer layer610in the third direction D3. Herein, the bottom surface of the first trench211may be located inside the n− type layer200through the buffer layer610according to a size of the first trench211.

The buffer layer610may include SiO2, Si2N3, SiN, Al2O3, PSG, USG, BSG, BPSG, or a combination thereof. In addition, the buffer layer610may include the same material as the gate lower insulation layer620.

The gate upper insulation layer630may be disposed on the lower gate runner750and the buffer layer610. However, the gate upper insulation layer630may not completely cover the lower gate runner750but may expose a portion of the lower gate runner750.

The upper gate runner760may be disposed on the gate upper insulation layer630and may be connected to the lower gate runner750exposed between the gate upper insulation layers630. The upper gate runner760may include the same material as the source electrode800.

Hereinafter, a method of manufacturing the semiconductor device1000according to one embodiment will be described with reference toFIGS.5to8.

FIGS.5to8are cross-sectional views showing intermediate steps in a method of manufacturing a semiconductor device1000according to one embodiment.

Referring toFIGS.5to8, the n+ type substrate100is prepared, and the n− type layer200is formed on the upper surface of the n+ type substrate100. For example, the n− type layer200may be formed by epitaxial growth or implantation of n− type ions.

For reference, the n+ type substrate100and the n− type layer200all are included in the conductive region1100and the termination region1200.

Subsequently, the p type region400is formed in the conductive region1100, and the p type termination structure450is formed in the termination region1200. The p type region400may be formed by implanting p type ions into an upper portion of the n− type layer200. The p type region400adjacent to the termination region1200is formed to be extended to the termination region1200and spaced apart from the p type termination structure450.

The p type termination structure450is formed by implanting the p type ions into the upper portion of the n− type layer200of the termination region1200. The p type termination structure450includes a plurality of regions into which the p type ions are implanted, and the regions into which the p type ions are implanted are spaced apart from each other at a predetermined distance.

On the other hand, the p type region400may be formed in the termination region1200, even in the regions where the plurality of first trenches211are supposed to be formed. Herein, the plurality of first trenches211may be formed by etching the n− type layer200or the p type region400of the termination region1200. Herein, a second trench212may be formed together in the conductive region1100. The method of etching the n− type layer200and the p type region400may be wet etching.

When the plurality of first trenches211and the second trench212are formed, a hardmask may be formed on the n− type layer200and the p type region400excluding the regions where the plurality of first trenches211and the second trench212are supposed to be formed. The hardmask may include, for example, Si2N3.

The gate lower insulation layer620is formed inside the plurality of first trenches211and the second trench212.

Subsequently, the preliminary gate electrode layer700P is formed to cover the n-type layer200by using the non-conformal step coverage deposition method.

As the non-conformal step coverage deposition method is used, a deposition rate at an upper edge of the first trench211is increased, resulting in overhang deposition. In other words, the preliminary gate electrode layer700P is deposited (grows) to be centered on the upper edge of the first trench211.

For example, the non-conformal step coverage deposition method may be a plasma-enhanced chemical vapor deposition (PECVD) method using a thermal evaporator.

Accordingly, spacing T1bbetween the plurality of first trenches211in the first direction D1may be smaller than or equal to a width Tia of each of the plurality of first trenches211in the first direction D1. In other words, as the plurality of first trenches211has a narrower line width and pitch, a deposition rate of the preliminary gate electrode layer700P centered on the upper edge of the first trench211may be increased during the non-conformal step coverage deposition.

In addition, a portion of the preliminary gate electrode layer700P covering the n-type layer200may have a third direction D3thickness which is greater than or equal to about 0.5 times, greater than or equal to about 0.6 times, greater than or equal to about 0.7 times, greater than or equal to about 0.8 times, or greater than or equal to about 0.9 times and less than about 1 time, less than or equal to about 0.9 times, less than or equal to about 0.8 times, less than or equal to about 0.7 times, or less than or equal to about 0.6 times of the first direction D1width Tia of each of the plurality of first trenches211.

In addition, a ratio of the first direction D1width Tia of the first trench211to the first direction D1width T2aof the second trench212may be less than or equal to about 0.9, less than or equal to about 0.8, less than or equal to about 0.7, less than or equal to about 0.6, less than or equal to about 0.5, less than or equal to about 0.4, less than or equal to about 0.3, or less than or equal to about 0.2, and may be greater than or equal to about 0.1, greater than or equal to about 0.2, greater than or equal to about 0.3, greater than or equal to about 0.4, greater than or equal to about 0.5, greater than or equal to about 0.6, greater than or equal to about 0.7, or greater than or equal to about 0.8. When a ratio of the first direction D1width Tia of the first trench211to the first direction D1width T2aof the second trench212is within the ranges, the deposition rate of the preliminary gate electrode layer700P centered on the upper edge of the first trench211may be increased during the non-conformal step coverage deposition.

Herein, the first direction D1width T2aof the second trench212may be greater than or equal to about 0.1 μm, a third direction D3depth of the second trench212may be greater than or equal to about 0.5 μm, the first direction D1width Tia of the first trench211may be about 0.1 μm to about 2 μm, and a third direction D3depth of the first trench211may be greater than or equal to about 0.3 μm.

Accordingly, before the preliminary gate electrode layer700P fills in all of the plurality of first trenches211, as openings of the plurality of first trenches211are closed, the upper portion751of the lower gate runner750is formed on the plurality of first trenches211, and the extended portions752and753of the lower gate runner750are formed inside each of the plurality of first trenches211.

Before the preliminary gate electrode layer700P fills in all of the plurality of first trenches211, as the openings of the plurality of first trenches211are closed, an empty space or a void may be formed inside each of the plurality of first trenches211.

In addition, the surface of the upper portion751of the lower gate runner750may include protrusions protruding toward the first direction D1. The reason is that as the non-conformal step coverage deposition method is used, when the preliminary gate electrode layer700P is deposited (grows) to be centered on the upper edge of the first trench211, protrusions protruded toward the first direction D1may be formed on the surface of the upper portion751of the lower gate runner750above the upper edge of the first trench211.

However, in the etching step of the preliminary gate electrode layer700P, since the protruding portions on the surface of the upper portion751of the lower gate runner750are etched, the surface of the upper portion751of the lower gate runner750may be smoothed. However, this embodiment is not limited thereto, and in the etching step of the preliminary gate electrode layer700P, when the entire surface of the upper portion751of the lower gate runner750is etched at the same rate, the protruding portions may remain on the surface of the upper portion751of the lower gate runner750.

On the other hand, in the step of forming the preliminary gate electrode layer700P, the preliminary gate electrode layer700P may fill inside the second trench212.

Herein, in the step of forming the preliminary gate electrode layer700P, even though the non-conformal step coverage deposition method is used, since the first direction D1width Tia of the second trench212, that is, a line width, is sufficiently large, the preliminary gate electrode layer700P may fill all inside the second trench212.

In addition, in the step of forming the lower gate runner750, until the upper surface of the preliminary gate electrode layer700P is disposed inside the second trench212, a portion of the preliminary gate electrode layer700P covering the n− type layer200may be etched to form the gate electrode700inside the second trench212.

In other words, the gate electrode700may be a buried gate electrode structure, and the buried gate electrode structure may be simply formed by using a gate recess process with an etching process alone without a separate mask after the deposition. Accordingly, a cell pitch of the semiconductor device1000may be reduced to increase cell density of the semiconductor device1000.

The gate upper insulation layer630is formed on the gate electrode700and the lower gate runner750.

After forming a contact hole for exposing a portion of the lower gate runner750on the gate upper insulation layer630, the source electrode800is formed in the conductive region1100, and the upper gate runner760is formed in the termination region1200.

Subsequently, on the lower surface of the n+ type substrate100, the drain electrode900is formed.

While embodiments of this invention have been described in connection with what is presently considered to be practical example embodiments, it is to be understood that the embodiments of the invention are not limited to the disclosed embodiments. On the contrary, they are intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

The following reference identifiers may be used in connection with the drawings to describe various features of embodiments of the present invention.1000: semiconductor device1100: conductive region1200: termination region100: n+ type substrate200: n− type layer211: first trench212: second trench400: p type region450: p type termination structure610: buffer layer620: gate lower insulation layer630: gate upper insulation layer700: gate electrode700P: preliminary gate electrode layer750: lower gate runner751: upper portion of lower gate runner752: trench sidewall portion of lower gate runner753: trench bottom portion of lower gate runner760: upper gate runner800: source electrode900: drain electrode