SYNAPSE CIRCUIT FOR VARIATIONAL INFERENCE

The present disclosure relates to a synapse circuit (202) for a Bayesian neural network, the synapse circuit comprising: a first resistive memory device (302) coupling a first voltage rail (Vread) to a first terminal of a capacitor (308), the first terminal of the capacitor (308) being coupled to a second voltage rail via a variable conductance (306); and a second resistive memory device (304) coupling a second voltage rail (Vdata) to an output line (312) of the synapse circuit (202), wherein a second terminal of the capacitor (306) is coupled to a terminal of the second resistive memory device (304).

FIELD

The present disclosure relates generally to the field of artificial neural networks, and in particular to devices and methods for implementing Bayesian neural networks.

BACKGROUND

Artificial neural networks (ANN) are computing architectures that are developed to mimic, to a certain extent, neuro-biological systems. Such neural networks generally comprise a network of artificial neurons, which receive inputs, combine these inputs with their internal state, and often apply a function to it, in order to produce an output signal. Outputs of neurons are coupled to the inputs of other neurons by connections, which are referred to as synapses, their equivalent in the biological brain.

The synapses generally perform some processing of the signals conveyed between the neurons. For example, each synapse stores a gain factor, or weight, which is applied to the signal from the source neuron in order to increase or decrease its strength, before it is conveyed to one or more post-synaptic neurons. The synapses between each layer of neurons of the ANN are generally implemented by a matrix multiplication or dot/inner product calculation.

It is possible to categorize neural networks into two families: deterministic neural networks, which provide a deterministic output for a given input; and Bayesian, or probabilistic neural networks, which are based on Bayesian deep learning models, and which encode synaptic parameters using distributions of probability.

Bayesian deep learning models are of great interest because, since they describe parameters using probability distributions, the probability distributions of their outputs can be used to describe uncertainty in predictions. Uncertainty can be particularly useful in safety-critical applications, such as autonomous driving, where potentially dangerous actions, based on neural network outputs, should only be taken by a system if these outputs are highly certain. The uncertainty described by Bayesian synapses propagates through to the outputs of the model, thereby offering a means of characterizing the uncertainty in predictions generated by the model.

The publication by Neal, Radford M. entitled “Bayesian learning for neural networks.” Vol. 118. Springer Science & Business Media, 2012, describes a Bayesian machine learning scheme based on Markov chain Monte Carlo sampling, which is used to derive the probability distributions for encoding the synaptic weights of the network. However, a drawback of the Markov chain Monte Carlo sampling approach is that the algorithm does not scale well to the large models that are used in the context of deep learning, where there can be millions or hundreds of millions of parameters.

The publication by Blundell, Charles, et al. entitled “Weight uncertainty in neural network” International Conference on Machine Learning. PMLR, 2015, describes an approach based on variational inference, which provides a more promising solution for large models.

In order to provide a hardware implementation of a Bayesian Neural Network based on variational inference, some form of random number generation within the synapses of the network should be used. However, solutions that have been proposed for such random value generation suffer problems in terms of energy efficiency and scalability. Indeed, the random behavior generally relies on the injection of a relatively large DC current into the device, the greater the size of the network, the higher the required current.

SUMMARY

There is a need in the art for a solution for random value generation suitable for Bayesian neural network applications having reduced energy consumption and improved scalability.

It is an aim of embodiments of the present disclosure to at least partially address one or more needs in the prior art.

According to one, aspect, there is provided a synapse circuit for a Bayesian neural network, the synapse circuit comprising: a first resistive memory device coupling a first voltage rail to a first terminal of a capacitor, the first terminal of the capacitor being coupled to a second voltage rail via a variable conductance; and a second resistive memory device coupling a third voltage rail to an first output line of the synapse circuit, wherein a second terminal of the capacitor is coupled to a terminal of the second resistive memory device.

According to one embodiment, the synapse circuit further comprises a selection switch coupled in series with the second resistive memory device.

According to one embodiment, the variable conductance comprises a variable resistor.

According to one embodiment, the variable conductance is a mirroring branch of a current mirror.

According to one embodiment, the synapse circuit further comprises a current control circuit configured to regulate a biasing current conducted by the variable conductance.

According to one embodiment, the first and second resistive memory devices are each capable of being programmed to have one of a low conductance state and a high conductance state, and the first resistive memory device is programmed to have a low conductance state, and the second resistive memory device is programmed to have a high conductance state.

According to one embodiment, the first and second resistive memory devices are oxide-based resistive random access memory devices.

According to one embodiment, the synapse circuit is a Gaussian mixture synapse, wherein the first and second resistive memory devices, capacitor variable conductance and selection switch form a first sub-circuit, the synapse circuit further comprising:at least one further sub-circuit comprising a first further resistive memory device coupling the first voltage rail to a first terminal of a further capacitor, the first terminal of the further capacitor being coupled to the second voltage rail via a further variable conductance; a second further resistive memory device coupling the third voltage rail to an output line of the at least one further sub-circuit, wherein a second terminal of the further capacitor is coupled to a terminal of the second further resistive memory device; and a further selection switch coupled in series with the second further resistive memory device, wherein the first output line and the output line of the at least one further sub-circuit are coupled to a common output line of the Gaussian mixture synapse; anda selection circuit configured to control the selection switch of each sub-circuit.

According to one embodiment, the selection circuit comprises a random number generator, and a decoder circuit configured to control the selection switch of each sub-circuit based on a random value generated by the random number generator.

According to a further aspect, there is provided a cross-point memory array for implementing a synaptic weight matrix between layers of a neural network, the cross-point memory array comprising a plurality of the above synapse circuit, one being positioned at each point of the cross-point memory array.

According to a further aspect, there is provided a method of generating a current signal on an output line of a synapse circuit of a Bayesian neural network, the method comprising:programming a first resistive memory device of the synapse circuit to have a first conductance level, the first resistive memory device coupling a first voltage rail to a first terminal of a capacitor, the first terminal of the capacitor being coupled to a second voltage rail via a variable conductance;programming a second resistive memory device to have a second conductance level, the second resistive memory device coupling a third voltage rail to the output line of the synapse circuit, wherein a second terminal of the capacitor is coupled to a terminal of the second resistive memory device; andapplying a voltage to the first voltage rail in order to generate a current signal on the output line.

According to one embodiment, the method further comprises sampling the current signal to generate the current signal on the output line.

According to one embodiment, the synapse circuit further comprises a selection switch coupled in series with the second resistive memory device, and the method further comprises activating the selection switch while applying the voltage to the first voltage rail in order to generate the current signal on the output line.

DETAILED DESCRIPTION OF THE PRESENT EMBODIMENTS

For the sake of clarity, only the operations and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail. In particular, techniques for training an artificial neural network, based for example on minimizing an objective function such as a loss function, are known to those skilled in the art, and will not be described herein in detail.

FIG.1schematically illustrates a Bayesian neural network100according to an example embodiment. The network100comprises, in the example ofFIG.1, a layer L1of source neurons N1to N4, and a layer L2of destination neurons N1′ to N4′, the outputs of each of the neurons N1to N4being coupled to inputs of each of the neurons N1′ to N4′. In some cases, the layer L1may be the input layer of the network, and/or the layer L2may be the output layer of the network. Furthermore, the network100may be part of a larger network, and in particular, there may be additional layers before the layer L1and/or after the layer L2, which may or may not be of Bayesian type.

Each of the source neurons N1to N4is coupled to each of the neuros N1′ to N4′ via a corresponding synapse having an associated weight, which in the case of a Bayesian neural network is not a fixed value, but rather a probability distribution, WPDi,j, where i is the index of the source neuron, and j is the index of the destination neuron. An example of the distribution q(w|θ) of WPD1,1as represented by a graph shown as an inset inFIG.1, where q(w|θ) is the sampling distribution, with parameters θ, used to generate samples of the model, w. Upon each forward propagation through the network, a value of each of the weights WPDi,jis for example sampled based on at least two corresponding probability distribution parameters representing the probability distribution of the synapse, which is for example a Gaussian distribution.

Of course, whileFIG.1illustrates an example of two layers of a network, each layer comprising four neurons, there could be any number of layers, each with any number of neurons. Furthermore, while in the example ofFIG.1the layers L1and L2are fully connected, in alternative embodiments the layers could be only partially connected.

FIG.2schematically illustrates a cross-point memory array200implementing a synaptic weight probability distribution matrix between the layers L1and L2of the neural network ofFIG.1. Each synapse Si,jbetween source neuron i and destination neuron j is implemented by a corresponding synapse circuit202. There are thus16synapse circuits202in the example ofFIG.2, one coupling each of the four source neurons N1to N4to each of the four destination neurons N1′ to N4′. The synapse circuits202are for example arranged in columns and rows. Each synapse circuit202is for example configured to store, and sample, a probability distribution q(w|θ), as represented by a graph shown as an inset inFIG.2. The synapse circuits202of a same column are for example coupled to a common neuron output line204of each column, this line204for example being an output line of the source neuron of the synapse circuits202of the column. Furthermore, the synapse circuits202of a same column are for example coupled to common control lines206,208of each column. The synapse circuits202of a same row are for example coupled to a common neuron input line210of each row, this line210for example being coupled to an input of the destination neuron of the synapse circuits202of the row. For example, each synapse circuit202of each row generates an output current on the corresponding common neuron input line210, and the sum of these currents provides an input current ioutjto the corresponding destination neuron Nj′. As represented by another graph inset inFIG.2, the resulting probability distribution present on the common row lines is the sum of the probability distributions of each synapse circuit202of the row. The control lines206,208are for example controlled by a control circuit (CTRL)212.

FIG.3schematically illustrates a synapse circuit202of the memory array ofFIG.2in more detail according to an example embodiment of the present disclosure. The synapse circuit202is for example suitable for performing variational inference. It would also be possible to use a similar synapse circuit for Markov chain Monte Carlo sampling, with the addition of an external memory for storing all of the samples that have been accepted by the algorithm. For example, in this case, a relatively large number of samples is digitized, for example using an ADC applied to the varying voltage; and then a relatively large number of them are stored with an index that corresponds to “acceptance ratio” of that particular sample, the index being a number that can be calculated that estimates the posterior probability of that particular sample for the entire model given the data and the prior.

The synapse circuit202for example comprises two resistive memory devices302,304storing the two probability distribution parameters of the synapse. For example, the device302is programmed to have a conductance Gsigmarepresenting a standard deviation of the desired probability distribution, and the device304is programmed to have a conductance Gmurepresenting a mean of the desired probability distribution.

The resistive memory devices302,304are each for example resistive RAM (RRAM) devices. In the present description, embodiments comprising oxide-based resistive RAM (OxRAM) devices are described, which are based on so-called “filamentary switching”. However, other resistive memory technologies could be used, including for example phase change memory (PCM), conductive bridge RRAM, ferromagnetic field effect transistors, FLASH transistors, etc. Such devices are all capable of being programmed, in a non-volatile manner, to have a given conductance level.

As known by those skilled in the art, OxRAM devices have two electrodes separated by an oxide material, one example of which is hafnium dioxide. OxRAM devices are capable of being switched between high and low conductance states that respectively result from the absence or presence of a conductive oxygen vacancy filament within the oxide material. For example, OxRAM devices can be SET to a high conductance state by applying a positive voltage across the device electrodes, the resulting conductance being proportional to the level of the current. OxRAM devices can for example be RESET to the low conductive state by applying a negative voltage over the device electrodes, the resulting conductance being proportional to the magnitude of the RESET voltage.

The resistive memory device302is for example coupled in series with a variable conductance306between the control line206and a reference voltage rail, which is for example a ground voltage rail. The variable conductance306for example has a conductance of Gref. In some embodiments, the variable conductance306is implemented by a variable resistor, such as a polysilicon resistor, or by a pseudo transistor. For example, the variable conductance306is controlled in order to conduct a biasing current ibiasthat is independent of the programmed conductance level of the resistive memory device302. For example, the variable conductance306is controlled by a current control circuit (ibiasCTRL)307, for example implemented in the control circuit212.

While not illustrated inFIG.3, the resistive memory device302is, for example, coupled in series with a selection transistor that can be used to select the device302during programming. For example, the selection transistor could be an n-channel MOS (NMOS) transistor coupling the device302to the node305, or coupling the node305to the conductance306. It would also be possible for the selection transistor to form part of the circuit implementing the variable conductance306.

The control circuit212ofFIG.2for example applies a voltage Vreadto the control line206. A node305between the device302and the variable conductance306is for example coupled to one terminal of a capacitor308, the other terminal of which is coupled to one terminal of the resistive memory device304. The capacitor308for example provides a function of DC blocking. For example, the capacitor308has a capacitance in the range 1 fF to 1 pF. In some embodiment, the capacitor308is implemented by a MOSCAP.

The resistive memory device304is for example coupled in series with a selection switch310, implemented for example by an NMOS transistor, between the common neuron output line204and an output line312of the synapse circuit202. The selection switch310is for example controlled via the control line208(seeFIG.2). For example, the control line208is coupled to the gate of the transistor implementing the switch310. The source neuron (not illustrated inFIG.3) coupled to the synapse circuit202for example applies a data signal in the form of a voltage Vdatato the common neuron output line204. The data signal Vdatais for example an analog voltage level generated by the source neuron. Alternatively, the data signal Vdatacould be a binary voltage, if for example the cross-point is part of a spiking neural network. The control circuit212for example applies a voltage Vgateto the control line208.

The output current ioutof the synapse circuit202is for example provided, on the output line312, which is also the input of the destination neuron. In particular, the output line312is coupled to the common neuron input line210providing the summed currents, from each synapse circuit of the row, to the destination neuron. The summed currents, including the output current ioutof the synapse circuit202, are for example sampled by an input circuit (NEURON SAMPLING)314of the destination neuron.

In operation, the variable conductance306and the application of the read voltage Vreadcause a current to be driven through the resistive memory device302. Intrinsic Johnson-Nyquist noise (also known as conductance fluctuations), at the programmed conductance level of the device302, is converted into a voltage at the node305using the voltage division between the device302and the variable conductance306. The resistive memory device302is for example programmed to be in the low conductance state, implying that it has a relatively high resistance, for example in the mega ohms or giga ohms range, and thus relatively high levels of Intrinsic Johnson-Nyquist noise. For example, the device302is programmed to have a resistance of at least 100 k ohms, and for example of at least 1 M ohms. The voltage at the node305is thus a noisy Gaussian signal having a DC offset that depends on the values of Gsigmaand Gref. The standard deviation of this noise signal is dependent on the programmed conductance level of the device302, as given by the following equation:

where k is the Boltzmann constant, and T is the temperature. An embodiment in which this temperature can be regulated is described below with reference toFIG.5.

FIG.4Ais a graph illustrating the voltage signal across a noisy resistive memory element302of the circuit ofFIG.3. It can be seen from the graph on the left ofFIG.4that the noise voltage density respects a Gaussian form. It can be seen from the graph on the right ofFIG.4that the noise signal has a mean μ, an RMS (Root Mean Square) voltage level VnRMS corresponding to one standard deviation σ from the mean, and a peak to peak level of 3.3σ.

FIG.4Bis a graph illustrating an example of the voltage V1at the node305, corresponding to the Gaussian noise signal ofFIG.4A, added to the DC offset Vdcresulting from the voltage division between the device302and the variable conductance306.

With reference again toFIG.3, the capacitor308removes the DC offset of the signal at node305, and thus injects only the AC noisy Gaussian signal portion at the terminal of the resistive memory device304.

FIG.4Cis a graph illustrating an example of the voltage signal V2at the node between capacitor308and the device304, prior to the addition of the data encoding voltage Vdata.

With reference again toFIG.3, the resistive memory device304converts the sum of the voltages Vdataand V2into a current signal iout(t) in accordance with Ohms law. The device304is for example programmed to be in the high conductance state, and for example has a resistance of less than 20 k ohms, and for example of less than 10 k ohms. The resistance of the device304is significantly less than the resistance of the device302, for example by at least two orders of magnitude, in other words the resistance of the device304being at least hundred times less than the resistance of the device302. Thus, the amount of Intrinsic Johnson-Nyquist noise is relatively low, and can be ignored. Thus, the current signal iout(t) can be expressed as:

This current iout(t) corresponds to a Gaussian distribution centered on Gmu, with a standard deviation defined by the programmable noise of Gsigma. This current iout(t) is for example sampled at the input of the destination neuron, as represented by the neuron sampling block314inFIG.3. For example, this may involve the use, in the destination neuron, of a resistor to convert the current into a voltage signal, and a sample and hold circuit to sample and store the voltage. Alternatively, a relatively short voltage pulse is applied as the gate signal Vgate, and a relatively fast analog to digital converter in the neuron sampling circuit314is for example used to capture a digital value of the voltage measured during the voltage pulse. As yet a further example, a relatively short voltage pulse is applied as the gate signal Vgate, but the current is not converted into a voltage, but rather injected, for example via a current mirror, to a membrane capacitor of an analog neuron circuit. An example of an analog neuron circuit having such a membrane capacitor is described for example in the patent publication entitled “Neuromorphic Architecture” published as EP3855366A1. In all cases, capturing the instantaneous level of the current iout(t) is for example performed relatively quickly, such that the current/voltage fluctuations are not averaged over time. For example, the duration of the sampling operation of the voltage V2is in the picosecond or nanosecond range, for example less than 10 nanoseconds, and in some cases in the range 1 picosecond to 5 nanoseconds. In some embodiments, a calibration step is used to counteract a sampling time artefact and preserve a relatively large variation in the measured variance. For example, the calibration step involves multiplying the value of a generated by the above equation by a constant between 1 and 0, for example to between 0.9 and 1.

While in the example ofFIG.3the capacitor308is configured to inject the AC noise signal at the input line204of the circuit, in alternative embodiments the capacitor308could inject the AC noise signal at a different location. For example, rather than being coupled between the node305and the line204, the capacitor308could be coupled between the node305and the node between the device304and the transistor208, or even between the node305and the output line210. It would also be possible for the switch310to instead be coupled between the device304and the capacitor/line204.

FIG.5schematically illustrates the synapse circuit202of the memory array ofFIG.2in more detail according to an alternative embodiment to that ofFIG.3. Certain features of the embodiment ofFIG.5are the same as those of the embodiment ofFIG.3, and these features are labelled with like reference numerals, and will not be described again in detail.

In the embodiment ofFIG.5, the variable conductance306is implemented by a mirroring branch of a current mirror. For example, the current mirror comprises a transistor502forming the mirroring branch, and a transistor504forming a reference branch. The transistor502is for example coupled by its main conducting nodes between the node305and a reference voltage rail, such as the ground rail. The transistor504is for example coupled by its main conducting nodes between a reference current input line506and the reference voltage rail. The transistors502,504are for example MOS transistors having their gates coupled together and to the bias current input line506. A reference current irefof the current mirror is for example provided on the input line506, for example by a current source508. For example, in some embodiments, the current source508is selectively activated as a function of the voltage Vread, such that the current in the current mirror is present only during a read operation. In some embodiments, the current source508is variable, such that the reference current irefcan be adjusted based on the programmed resistance of the corresponding device304. For example, the current source508is capable of supplying one of a plurality of different current levels, for example at least four different current levels. This for example allows the magnitude of the noise voltage V1to be kept relatively close to a desired level, equal for example to around Vread/2. Based on the programmed resistance level of each device302, the control circuit307is for example configured to generate the control signal CTRL in order to control the current source508to supply an appropriate current.

In operation, the current ibiasis used to control the gate of the transistor502in order to provide a current through the resistive memory device302that is independent of the programmed conductance of the device302.

An advantage of the use of the current mirror inFIG.5to generate the biasing current Ibiasis that temperature can be regulated by the current Iref.

FIG. ¬6schematically illustrates a parallel arrangement600of a plurality M of the synapse circuits ofFIG.5, labelled202_1to202_M. For example, the parallel arrangement600corresponds to one row of synapse circuits202of the cross-point memory200ofFIG.2. As illustrated inFIG.6, the output lines312of the M synapse circuits are coupled together to form the common output line210of the row, which conducts a current SUM OUT, and is for example coupled to the sampling circuit (NEURON SAMPLING)314of the destination neuron.

The reference current irefprovided to each reference branch504of the current mirror of each synapse circuit202_1to202_M is for example a same current level. Thus, while an embodiment is illustrated with a reference branch per synapse circuit202_1to202_M, in alternative embodiments a common reference branch, comprising the transistor504, could be used to drive the mirroring branch of each synapse circuit. Alternatively, the reference current irefcould be adjusted for each synapse circuit202_1to202_M, as described above in relation withFIG.5, based on the programmed resistance of the corresponding device304, such that the magnitude of the noise voltage V1is kept relatively close to a desired level, equal for example to around Vread/2.

While the example ofFIG.6is based on the synapse circuit202ofFIG.5, in alternative embodiments the synapse circuits202_1to202_M could be implemented by the embodiment ofFIG.3.

FIG.7schematically illustrates a synapse circuit202of the memory array ofFIG.2in more detail according to an alternative embodiment to those ofFIGS.3and5, in which the synapse circuit202implements a Gaussian mixture synapse. This embodiment is based on Gaussian mixture model theory, which states that any arbitrary distribution can be approximated through a weighted sum of samples collected from a collection of Gaussian probability distributions. This principle is described in more detail in the publication by D. Reynolds entitled “Gaussian Mixture Models”, Encyclopedia of biometrics 741 (2009): 659-663.

In the example ofFIG.7, N synapse sub-circuits700_1to700_N are arranged in parallel, each of these sub-circuits being implemented by a corresponding instantiation of the synapse circuit202ofFIG.3. It would alternatively be possible to implement the sub-circuits based on the synapse circuit202ofFIG.5. The output lines312of the sub-circuits700_1to700_N are for example coupled together to form a single output line312′ of the synapse circuit202. The synapse circuit202ofFIG.5further comprises, for example, a random number generator (RNG)702having its output coupled to a decoder circuit (DEC)704, the decoder circuit704controlling the selection transistors310of the N sub-circuits700_1to700_N. The decoder circuit704for example stores weighting factors (WEIGHTING FACTORS)706associated with each of the probability distributions of the sub-circuits700_1to700_N. In some embodiments, all the weighting factors706sum to one. The decoder704is for example configured to provide a read signal to the transistor310of each sub-circuit700_1to700_N depending on the value generated by the random number generator702and on the weighting factors706. A dedicated random number generator702and decoder circuit704are for example provided for each synapse circuit202(i.e. each cross-point ofFIG.2). In the case of a spiking neuron network, it would however be possible to share the random number generator702by multiple synapse circuits202, as in this case a random number can be generated only upon occurrence of spike, as described for example in the patent filing entitled “Neural network and method for variational inference” sharing the same priority date as the present filing and in the name of the same applicant (attorney reference B21181).

In operation, the random number generator702for example supplies a random value to the decoder circuit704, which is for example configured to select one of the sub-circuits700_1to700_N to be activated based on the random value. For example, the random value is sampled from a uniform distribution. The range of possible values of the random value is for example divided into sub-ranges, each sub-range being associated with a corresponding one of the sub-circuits700_1to700_N. The size of each sub-range represents the weighting factor of the corresponding sub-circuit, and is for example learned during variational inference. The decoder circuit704is for example configured to compare the random value with each of the sub-ranges, and to activate the sub-circuit700_1to700_N that is associated with the sub-range within which the random value falls.

As an example, the random value could be a 5-bit value having any value between 0 and 31. There are for example two sub-circuits700_1and700_2, the sub-circuit700_1being associated with a sub-range 0 to 24, and the sub-circuit700_2being associated with a sub-range 25 to 31. If the random value falls in the range 0 to 24, the sub-circuit700_1is for example activated by the decoder circuit704, and the output current ioutof the synapse circuit202is thus provided by this sub-circuit700_1. If the random value falls in the range 25 to 31, the sub-circuit700_2is for example activated by the decoder circuit704, and the output current ioutof the synapse circuit202is thus provided by this sub-circuit700_2.

It should be noted that, during inference, many samples are generally taken of each synaptic weight per prediction, in other words there are multiple forward passes through the neural network. On each pass, a new sub-circuit is selected based on a new random value generated by the generator702, and in this way each sub-circuit is selected a number of times that is proportional to its learned probability distribution weight, resulting in a Gaussian mixture, as represented inFIG.8.

FIG.8is a graph illustrating probability density (PROBABILITY DENSITY) of a conductance (CONDUCTANCE, g (μS)) of the synapse circuit202ofFIG.7according to an example embodiment of the present disclosure. Dashed-line curves K1to K5inFIG.8represent examples of probability densities of five corresponding sub-circuits. A solid curve PD_mix illustrates an example of overall probability distribution that can be obtained by selecting a different one of the sub-circuits over many forward passes through the network.

In the embodiments described with reference toFIGS.3to8, the resistive memory devices302,304are respectively programmed based on learning during variational inference operations. In particular, the conductance Gsigmaof the device302is adjusted to an appropriate level to represent the standard deviation of the probability distribution, and the conductance Gmuof the device304is adjusted to an appropriate level to represent the mean of the probability distribution. The amounts that the conductances of the devices should by adjusted during the learning phase are for example based on standard back propagation techniques, as described for example in the publication by Blundell, Charles, et al. entitled “Weight uncertainty in neural network” International Conference on Machine Learning. PMLR, 2015, and will not be described herein in detail. Examples of programming operations that can be used to program the conductances of the devices302,304will now be described with reference toFIGS.9and10to11.

FIG.9is a graph illustrating examples of conductance levels obtained by programming an OxRAM device during a SET operation into the high conductance/low resistance state. In particular, the graph ofFIG.9represents, for a SET programming current range 11 to 120 μA (CURRENT (μA)), a median conductance (MEDIAN CONDUCTANCE (μS)) represented by a curve902with a log scale on the left-hand axis, and a cycle-to-cycle standard deviation (CYCLE-TO-CYCLE S.D. %) of the conductance state following a RESET operation on the OxRAM device, represented by a curve904with a log scale on the right-hand axis. While the standard deviation is relatively high (around 70%) for some lower conductances, the precision remains acceptable.

FIG.10schematically illustrates iterative programming of a resistive memory device according to an example embodiment. The example is based on the programming the devices304of the synapse circuits202, for by programming a high conductance state (HCS) using a SET operation.

Three of the devices304are shown in the example ofFIG.10. Each device304is coupled in series with a programming selection transistor, which is for example the transistor310ofFIG.3, or another transistor. The programming selection transistors310are for example controlled by a voltage signal Vgate, which is for example provided by the control circuit212. For example, the series connection of each device302and transistor310is coupled between a corresponding programming voltage line V[0], V[1] and V[2] and the output line312, to which is applied a common bottom electrode voltage rail VBE.

Each device302is for example programmed in turn, by applying, for example by the control circuit212, a programming voltage to the corresponding voltage line V[0], V[1] and V[2], and asserting the voltage signal Vgatein order to activate the corresponding conduction path through the device304to be programmed. In some embodiments, a sufficiently precise target conductance of the device304is not always achieved after a single programming operation. It is therefore possible to apply an iterative programming approach. According to this approach, after the programming operation, a read voltage is for example applied, by the control circuit212, to the corresponding voltage line V[0], V[1] and V[2], and the resulting current on the line312is for example compared, by the control circuit212, to a desired range in order to determine whether the conductance of the device has reached a desired conductance range, or whether it should be increased or decreased. If it is outside of the range, it is determined what adjustment should be applied to the programming voltage, and then the adjusted programming voltage is for example applied to the device in order to adjust its conductance level. In the case of a PCM device, the adjustment can be applied using a SET or RESET pulse to increase or decrease the conductance. In the case of an OxRAM device, a RESET operation is for example performed first, before then performing a new SET operation with a modified programming voltage. As represented by a graph inset inFIG.10, this process is for example repeated iteratively during several programming iterations (PROG. ITRN), until the conductance (CONDUCTANCE (μS)) reaches a desired target range.

The devices302of each synapse circuit202can for example be programmed using a similar technique to the one ofFIG.10. However, the devices302are for example programmed to the low conductance state (LCS) using a RESET operation. Rather than the transistors310, other selection transistors are used, such as the transistors502ofFIG.5, and the rather than the common line312, the selection transistors are coupled to another common line. This operation for example involves applying 0 V to the top electrode of the device302to be programmed, and applying a positive voltage to the common line, such that the device sees a negative voltage.

An advantage of the embodiments described herein is that weights respecting given learned probability distributions can be sampled by synapse circuits in a simple and energy efficient manner. Indeed, the currents used to generate the random distribution signals can be relatively low. For example, assuming a voltage Vreadof 0.4 V, which is for example chosen not to disturb the programmed state of the device302, but to be high enough so as to saturate the current mirror transistors, that an LCS of 200 Mohms is used, and that the current mirror is also providing a resistance of about 200 Mohms, then by ohms law the current for generating the random distribution signal will be of around 1 nA. This compares to currents of tens or hundreds of microamps in the prior art solutions.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily occur to those skilled in the art.

Finally, the practical implementation of the embodiments and variants described herein is within the capabilities of those skilled in the art based on the functional description provided hereinabove.