FinFET and method for manufacturing the same

Methods for manufacturing a FinFET and a FinFET are provided. In various embodiments, the method for manufacturing a FinFET includes etching a base substrate to form a trapezoidal fin structure. Next, an isolation layer is deposited covering the etched base substrate. Then, the trapezoidal fin structure is exposed. The trapezoidal fin structure includes a top surface and a bottom surface, and the top surface has a width larger than that of the bottom surface.

BACKGROUND

The semiconductor industry has experienced exponential growth. Over the course of the growth, functional density of the semiconductor devices has increased with the decrease of device feature size or geometry. The scaling down process generally provides benefits by increasing production efficiency, reducing costs, and/or improving device performance, but increases complexity of the integrated circuit (IC) manufacturing processes.

To address the increase of manufacturing complexity, various non-planar transistors, such as a fin-like field-effect transistor (FinFET), have been developed to replace a planar transistor. However, device performance of such FinFET is still not satisfactory in advanced applications of technology. Therefore, improvements in structures and methods of forming a FinFET with better device performance continue to be sought.

DETAILED DESCRIPTION

As aforementioned, device performance of a conventional fin-like field-effect transistor (FinFET) is still not satisfactory in advanced applications of technology. The FinFET formed by a conventional method is prone to form a fin structure with a top surface area smaller than a bottom surface area, which the width of the top surface of the fin structure is smaller than the width of the bottom surface of the fin structure. Therefore, only a small portion of the fin structure is capable of serving as a channel of the FinFET, and the device performance cannot be improved.

In order to solve the above-mentioned problems, the present disclosure provides a FinFET and methods for manufacturing the same, which the FinFET includes a fin structure having a top surface area larger than that of a bottom surface. Therefore, the FinFET has an enlarged effective channel region, which improves the FinFET device performance.

Referring toFIG. 1, which is a flow chart illustrating a method100for manufacturing a FinFET in accordance with some embodiments. It is understood that additional steps may be implemented before, during, and after the method, and some of the steps described may be replaced or eliminated for other embodiments of the method. It is noteworthy that sequences of the steps of the method100described herein are merely examples, and are not intended to be limiting. Various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure.

In step110, a base substrate is etched to form a trapezoidal fin structure. The formed trapezoidal fin structure includes a top surface and a bottom surface, and the top surface has a width larger than the width of the bottom surface. The trapezoidal fin structure includes a larger top surface area to enhance the effective channel area of the FinFET. The effective channel area of the FinFET is the portion of gate material interface with the fin structure, and is related to the device performance of the FinFET. When the effective channel area is enlarged, the device performance is improved.

The material of the trapezoidal fin structure may be the same as the base substrate. Examples of the material of the base substrate and the trapezoidal fin structure include but are not limited to silicon, silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide and a combination thereof.

In some embodiments, the trapezoidal fin structure has only one inclined sidewall, and the other sidewall of the trapezoidal fin structure is vertical. In some embodiments, both sidewalls of the trapezoidal fin structure are inclined, and the sidewalls may be one inwardly inclined sidewall and one outwardly inclined sidewall, or two inwardly inclined sidewalls, which the directions of the inward and the outward are relative to the center of the fin structure. For instance, when the sidewalls are both inwardly inclined sidewalls, i.e. inclined toward the center of the fin structure, the trapezoidal fin structure is an inverted trapezoidal fin structure.

In some embodiments, etching the base substrate is performed by plasma etching. The plasma etching may be performed by CH4, CHxFy, Cl2, HBr plasma, or the like, which CHxFyrepresents a fluoroalkane plasma, and x and y denote positive integers. The etching chemistry, such as flow rates, power ranges, bias voltages, etch duration and other parameters associated with the etching, may affect the shape of the formed trapezoidal fin structure. Therefore, the etching parameters in step110of the method100for manufacturing the FinFET are tuned to form the trapezoidal fin structure with a larger top surface area to enhance effective channel area of the FinFET.

In some embodiments, etching the base substrate is performed at an etching bias in a range from about 100 millivolts (mV) to about 200 mV. In general, the etching bias of a conventional method for manufacturing a FinFET is in a range from about 0 mV to about 100 mV. The formed fin structure is prone to have a large bottom surface due to less amount of ions bump against the bottom of the fin structure. The method100increases the etching bias to increase the amount of ions that bump against the bottom of the fin structure, and the fin structure with a smaller bottom surface is then formed.

In some embodiments, etching the base substrate is performed at a power in a range from about 400 Watts (W) to about 800 W. In general, the power of a conventional method for manufacturing a FinFET is in a range from about 50 mV to about 200 mV. The formed fin structure is prone to have a large bottom surface due to the reasons similar to the etching bias. The method100increases the power to form the fin structure with a smaller bottom surface.

In some embodiments, etching the base substrate is performed at a flow rate of the plasma in a range from about 50 standard cubic centimeter per minute (sccm) to about 250 sccm. In general, the flow rate of a conventional method for manufacturing a FinFET is in a range from about 0 sccm to about 50 sccm. The formed fin structure is prone to have a large bottom surface due to plasma gas deposition at the bottom of the fin structure. The method100increases the flow rate to reduce the plasma gas deposition at the bottom of the fin structure, and the fin structure with a smaller bottom surface is then formed.

In step120, an isolation layer is deposited covering the etched base substrate. Then, the trapezoidal fin structure is exposed in step130. In some embodiments, the isolation layer is formed over the etched base substrate, and the upper portion of the isolation layer is removed to expose the trapezoidal fin structure. The isolation layer may be formed by any suitable depositing methods, such as chemical vapor deposition (CVD), atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), metal-organic CVD (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), chemical solution deposition, sputtering or a combination thereof. The upper portion of the isolation layer may be removed by chemical-mechanical polishing (CMP) and/or etching such as reactive ion (RI) etching.

In some embodiments, the isolation layer is a shallow trench isolation (STI) structure. The isolation layer may be made of a dielectric material. Examples of the dielectric material include but are not limited to silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass, a low-k dielectric material and a combination thereof.

In some embodiments, the method100further includes a step of forming a gate stack across over the fin structure after step130. The gate stack may include a gate dielectric layer and a gate electrode, and may be formed by any suitable methods, such as deposition. In some embodiments, the gate dielectric layer and the gate electrode are formed by chemical vapor deposition (CVD), atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), metal-organic CVD (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), chemical solution deposition, sputtering or a combination thereof. The material of the gate electrode may be any suitable semiconductor material, such as polysillicon, germanium, combinations of silicon and germanium, metal, metal alloy, or metal silicide. Examples of the material of the metal gate electrode include but are not limited to tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), nickel (Ni), ruthenium (Ru), palladium (Pd), platinum (Pt), tungsten nitride (WNx), titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN), tungsten silicide (WSix), nickel silicide (Ni2Si), titanium silicide (TiSi2), titanium aluminide (TiAl), an alloy thereof and a combination thereof. The material of the gate dielectric layer may be any suitable material, such as silicon oxide, silicon nitride, silicon oxynitride, high-k material or other suitable insulating materials. Examples of the material of the high-k material include but are not limited to Al2O3, HfO2, ZrO2, La2O3, TiO2, SrTiO3, LaAlO3, Y2O3, Al2OxNy, HfOxNy, ZrOxNy, La2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNx, a silicate thereof, an alloy thereof and a combination thereof. Each value of x is independently from 0.5 to 3, and each value of y is independently from 0 to 2.

In some embodiments, the method100further includes a step of forming a source region and a drain region at both ends of the fin structure after step130. The source region and the drain region may be formed by any suitable methods, such as doping and epitaxy.

In some embodiments, the source region and the drain region are formed by epitaxy, which includes steps of recessing the trapezoidal fin structure and epitaxially grow the source region and the drain region in the recesses. With the increased top surface of the trapezoidal fin structure, the forming process for the epitaxial source region and drain region is easier while recessing the trapezoidal fin structure, and thus the formed epitaxial source region and drain region are with enlarged volume. The material of the epitaxial source region and drain region may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP or other suitable material.

The method100for manufacturing the FinFET tunes the etching parameters while etching the base substrate to form the trapezoidal fin structure. The formed trapezoidal fin structure includes a larger top surface area to enhance the effective channel area of the FinFET, and the device performance of the FinFET is thereby improved. In addition, the FinFET formed by the method100can have better device uniformity.

Referring toFIG. 2, which is a flow chart illustrating a method200for manufacturing a FinFET in accordance with some embodiments. It is understood that additional steps may be implemented before, during, and after the method, and some of the steps described may be replaced or eliminated for other embodiments of the method. It is noteworthy that sequences of the steps of the method200described herein are merely examples, and are not intended to be limiting. Various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure.

In step210, a fin structure is formed over a substrate. The formed fin structure includes a top surface, a bottom surface and a pair of sidewalls. The top surface has a width larger than the width of the bottom surface. In addition, at least one sidewall has more than one slope. That is, the at least one sidewall of the fin structure has changing slopes and is not a plane, which the plane is a two-dimensional, flat surface with no thickness. Further, the at least one sidewall and the isolation layer have an acute included angle, which is less than 90°. The fin structure is formed with a larger top surface area to enhance the effective channel area of the FinFET, and the device performance of the FinFET is thus improved.

The fin structure may be formed by any suitable processes, such as photolithography and etching. The photolithography may include forming a photoresist layer over the substrate, exposing the photoresist layer to form a pattern, performing post-exposure bake processes, and developing the pattern to form a photoresist mask. The aforementioned photoresist mask is used to protect a portion of the substrate while forming trenches in the substrate by the etching process, to form the fin structure. The substrate and the fin structure may be integrally formed, which the substrate and the fin structure are made of the same material.

Further, the fin structure may be formed by a recessing process and a depositing process. For instance, a hole with a desired shape is first formed in an isolation layer by a recessing process. Then, a fin material is deposited to fill the hole and to form a fin structure.

The fin structure formed in step210may be in any shape as long as the width of the top surface is larger than that of the bottom surface, at least one sidewall has more than one slopes, and the at least one sidewall and the isolation layer have an acute included angle. In some embodiments, the slopes of the pair of sidewalls of the formed fin structure are the same. That is, the sidewalls of the fin structure have the same slope profile, and the fin structure has a symmetrical cross-section along the width direction. In some embodiments, the slopes of the pair of sidewalls of the formed fin structure are different from each other. That is, the sidewalls of the fin structure have different slope profiles, and the fin structure has an unsymmetrical cross-section along the width direction. For instance, the fin structure may include a curved sidewall and an inclined sidewall.

In step220, the isolation layer is deposited covering the substrate. Then, the fin structure is exposed in step230. The isolation layer may be formed by any suitable depositing methods, such as chemical vapor deposition (CVD), atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), metal-organic CVD (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), chemical solution deposition, sputtering or a combination thereof. In some embodiments, the isolation layer is a shallow trench isolation (STI) structure. The isolation layer may be made of a dielectric material. Examples of the dielectric material include but are not limited to silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass, a low-k dielectric material and a combination thereof.

In some embodiments, the method200further includes a step of forming a gate stack across over the fin structure after step230. The gate stack may include a gate dielectric layer and a gate electrode, and may be formed by any suitable methods, such as deposition. In some embodiments, the gate dielectric layer and the gate electrode are formed by chemical vapor deposition (CVD), atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), metal-organic CVD (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), chemical solution deposition, sputtering or a combination thereof. The materials of the gate electrode and the gate dielectric layer may be any suitable materials, and examples of the materials of the gate electrode and the gate dielectric layer may refer to the related descriptions described above.

In some embodiments, the method200further includes a step of forming a source region and a drain region at both ends of the fin structure after step230. The source region and the drain region may be formed by any suitable methods, such as doping and epitaxy.

In some embodiments, the source region and the drain region are formed by epitaxy, which includes steps of recessing the fin structure and epitaxially grow the source region and the drain region in the recesses. With the increased top surface of the fin structure, the forming process for the epitaxial source region and drain region is easier while recessing the fin structure, and thus the formed epitaxial source region and drain region are with enlarged volume. The material of the epitaxial source region and drain region may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP or other suitable material.

The method200for manufacturing the FinFET forms the fin structure with a larger top surface area to enhance the effective channel area of the FinFET. The enhanced effective channel area improves the device performance of the FinFET.

Referring toFIG. 3, which is a schematic perspective view of a FinFET300in accordance with some embodiments. The FinFET300includes a substrate310, trapezoidal fin structures320, an isolation layer330and a gate stack340. The trapezoidal fin structures320are over the substrate310. The gate stack340is across over the trapezoidal fin structures320, and includes a gate dielectric layer342and a gate electrode344. The FinFET300may be formed by the method100for manufacturing a FinFET described above.

In some embodiments, the substrate310is a bulk substrate or a semiconductor-on-insulator (SOI) substrate. Examples of the material of the substrate310includes but are not limited to silicon, silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide and a combination thereof.

Each of the trapezoidal fin structures320has a trapezoidal cross-section along the width direction. A portion of each fin structure320is covered by the isolation layer330, which is used to separate the two trapezoidal fin structures320. The exposed portion of each fin structure320includes a top surface and a bottom surface. The top surface has a width w1, and the bottom surface has a width w2. The width w1is larger than the width w2. In some embodiments, the widths w1and w2of the top surface and the bottom surface of the trapezoidal fin structures320are independently in a range from about 1 nm to about 25 nm. The exposed portion of each fin structure320has a height h, which is the length of sidewall of the trapezoidal fin structures320from the top surface of the trapezoidal fin structures320to the top surface of the isolation layer330. In some embodiments, the height h of the trapezoidal fin structures320is in a range from about 10 nm to about 80 nm. In some embodiments, the substrate310and the trapezoidal fin structures320are integrally formed, which there is no boundary between the substrate310and the fin structure320. In some embodiments, the substrate310and the trapezoidal fin structures320are made of the same material.

In some embodiments, the isolation layer330is a shallow trench isolation (STI) structure. The isolation layer330is between the trapezoidal fin structures320, and is configured to separate the two trapezoidal fin structures320. The isolation layer330may be made of a dielectric material. Examples of the dielectric material include but are not limited to silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass, a low-k dielectric material and a combination thereof.

The gate dielectric layer342is across over the trapezoidal fin structures320, and the gate electrode344is over the gate dielectric layer342. The gate dielectric layer342is interposed between the trapezoidal fin structures320and the gate electrode344. In some embodiments, the gate stack has a thickness1in a range from about 5 nm to about 50 nm.

The FinFET300may further include a source region (not shown) and a drain (not shown) region at both ends of the trapezoidal fin structures320. The portion of the trapezoidal fin structures320between the source region and the drain region serves as the channel of the FinFET300. The effective channel area of the FinFET300may be calculated by the following formula I:
Effective channel area=(2h+w1)×lI

The FinFET300includes the trapezoidal fin structures320with larger top surfaces. Comparing to a conventional FinFET, which the width of the top surface of the fin structure is smaller than that of the bottom surface of the fin structure, the FinFET300includes increased width w1of the top surface of each fin structure320to enlarge the effective channel area of the FinFET300. Therefore, the device performance of the FinFET300is improved.

FIGS. 4A through 4Fare cross-sectional views at various stages of manufacturing a FinFET400, which may be cross-sectional views taken along line A-A′ inFIG. 3, i.e. the width direction of the trapezoidal fin structures320.

Referring toFIG. 4A, a first oxide layer412, a nitride layer414and a second oxide layer416are deposited over a base substrate410. The substrate410may be made of any suitable material, such as silicon, silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide and a combination thereof. The first oxide layer412serves as a buffer layer, which releases the stress during the deposition of the nitride layer414. The nitride layer414serves as a shield, which protects fin structures against etching in the subsequent manufacturing process. In some embodiments, the nitride layer414is made of silicon nitride. The second oxide layer prevents the fin structures from being etched in the subsequent manufacturing process as well.

Referring toFIG. 4B, the base substrate410, the first oxide layer412, the nitride layer414and the second oxide layer416are etched to form an etched base substrate410a, an etched first oxide layer412a, an etched nitride layer414aand an etched second oxide layer416a. Trapezoidal fin structures420are then formed over the etched base substrate410a.

In some embodiments, the etching is performed by plasma etching. The plasma etching may be performed by CH4, CHxFy, Cl2, HBr plasma, or the like. The etching parameters are tuned to form the fin structures420with a larger top surface area to enhance effective channel area of the FinFET400. In some embodiments, the etching is performed at an etching bias in a range from about 100 mV to about 200 mV, which is higher than conventional method to increase the amount of ions that bump against the bottom of the fin structure. In some embodiments, the etching is performed at a power in a range from about 400 W to about 800 W, which is larger than conventional method to form the fin structure420having a larger top surface. In some embodiments, the etching is performed at a flow rate of the plasma in a range from about 50 sccm to about 250 sccm, which is faster than conventional method to reduce the plasma gas deposition at the bottom of the fin structure.

Referring toFIG. 4C, some trapezoidal fin structures420are removed to avoid that the trapezoidal fin structures420are too close to each other, which prevent a short circuit between adjacent trapezoidal fin structures420.

Referring toFIG. 4D, the etched second oxide layer416ais removed. Then, the material of an isolation layer430was deposited to cover the etched base substrate410a. The material of the isolation layer430may be deposited by any suitable methods, such as chemical vapor deposition (CVD), atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), metal-organic CVD (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), chemical solution deposition, sputtering or a combination thereof. In some embodiments, the isolation layer was polished by chemical-mechanical polishing (CMP) after the deposition to expose the top surface of the etched nitride layer414a. In some embodiments, the isolation layer is a shallow trench isolation (STI) structure. The isolation layer may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass, a low-k dielectric material and a combination thereof.

Referring toFIG. 4F, the isolation layer430is recessed to expose the trapezoidal fin structures420, and the etched first oxide layer416ais removed, and the FinFET400is then formed. The exposed trapezoidal fin structures420are inverted trapezoidal fin structures, which the cross-sectional view of the trapezoidal fin structures420has a shape of inverted trapezoid.

After the formation of the FinFET400, conventional manufacturing processes can be performed. In some embodiments, a gate stack is formed across over the fin structures420to form the structure shown inFIG. 3. Then, a source region and a drain region may be formed at both ends the fin structures420.

The gate stack may be formed by any suitable processes, and may include depositions to form various gate materials, a CMP process to remove the excessive gate materials, and planarize the top surface of the FinFET. In some embodiments, the gate stack includes a gate dielectric layer across over the fin structures and a gate electrode over the gate dielectric layer. The gate dielectric layer and the gate electrode may be formed by deposition, and may be made of any suitable materials. The specific features of the deposition methods and materials for the gate dielectric layer and the gate electrode may refer to the related descriptions described above.

The source region and the drain region may be formed by any suitable processes, such as doping and epitaxy. In some embodiments, the source region and the drain region are epitaxial source region and drain region. With the increased top surface of the fin structures420, the formed epitaxial source region and drain region can have enlarged volume. Therefore, the FinFET400has better epitaxial stress concentrated since the epitaxial volume is enlarged. In some embodiments, the material of the epitaxial source region and drain region is Ge, Si, GaAs, AlGaAs, SiGe, GaAsP or other suitable material.

The fin structures420of the FinFET400is formed by etching with tuned etching parameters to form the fin structures420having the top surface larger than the bottom surface, which enlarges the effective channel area of the FinFET400. With the enlarged effective channel area, a greater portion of the gate material can interface with the fin structures. Therefore, the FinFET400can achieve improved FinFET device performance.

Referring toFIG. 5, which is a schematic cross-sectional view of a FinFET500in accordance with some embodiments. The FinFET500includes a substrate510, fin structures520and an isolation layer530. The fin structures520are over the substrate510. The isolation layer530is over the substrate510, and the fin structures520are protruding from the isolation layer530. Each of the trapezoidal fin structures520has a top surface, a bottom surface, and a pair of sidewalls. The width w5of the top surface of each fin structure520is larger than the width w6of the bottom surface. The slopes of the pair of sidewalls of the fin structures520are the same, which means that the fin structures520have a symmetrical cross-section along the width direction, and the sidewalls are curved and converged toward the center of the fin structure520. Included angles between the sidewalls of the fin structures520and the isolation layer530are acute. The FinFET500may be formed by the method200for manufacturing a FinFET described above.

In some embodiments, the widths w5and w6of the top surface and the bottom surface of the fin structures520are independently in a range from about 1 nm to about 25 nm. The fin structures520may have a height in a range from about 10 nm to about 80 nm.

In some embodiments, the FinFET500includes a gate stack (not shown) across over the fin structures520. The gate stack may have a thickness in a range from about 5 nm to about 50 nm. The effective channel area of the FinFET500may be calculated by the foregoing formula I with w1replaced by w5.

The FinFET500includes the fin structures520with larger top surfaces. Comparing to a conventional FinFET, which the width of the top surface of the fin structures is smaller than that of the bottom surface of the fin structure, the increased width w5of the top surface of each fin structure520enlarges the effective channel area of the FinFET500. Therefore, the device performance of the FinFET500is improved.

The FinFET500includes the fin structures520with a larger top surface area to enhance the effective channel area of the FinFET500, and the device performance of the FinFET500is thus improved.

Referring toFIG. 6, which is a schematic cross-sectional view of a FinFET600in accordance with some embodiments. The FinFET600includes a substrate610, fin structures620and an isolation layer630. The fin structures620are over the substrate610. The isolation layer630is over the substrate610, and the fin structures620are protruding from the isolation layer630. Each of the trapezoidal fin structures620has a top surface and a bottom surface, and the width w7of the top surface is larger than the width w8of the bottom surface. Each of the fin structures620includes a pair of sidewalls. The slopes of the pair of sidewalls of the fin structures620are different, which means that the fin structures620have an unsymmetrical cross-section along the width direction. Particularly, one sidewall of each fin structure620is vertical, while another sidewall of each fin structure620has two slopes and can be divided into an upper portion and a lower portion. The slope of the upper portion of the sidewall of each fin structure620is infinite, i.e. the slope of the upper portion of the sidewall is vertical. The absolute value of the slope of the lower portion of the sidewall of each fin structure620is greater than zero and less than infinite. That is, the slope of the lower portion of the sidewall of each fin structure620is inwardly inclined, which is inclined toward the center of the fin structure620, and the lower portion of the sidewall is converged. Included angles between the inclined sidewalls of the fin structures620and the isolation layer630are acute. The FinFET600may be formed by the method200for manufacturing a FinFET described above.

The difference between the FinFET600and the FinFET500is the shape of the fin structures. The sidewalls of the fin structures520are curved, while one of the sidewalls of the fin structures620includes more than one slope. The difference does not affect the functions of each component of the FinFET600. Therefore, the FinFET600has the same characteristics and advantages as the FinFET500.

The embodiments of the present disclosure discussed above have advantages over exiting methods and systems. The FinFET includes the fin structure having a larger top surface area than that of the bottom surface, which enlarges the effective channel area of the FinFET. With the enlarged effective channel area, the FinFET has improved FinFET device performance. Further, if the FinFET includes epitaxial source region and drain region, the FinFET has better epitaxial stress concentrated since epitaxial volume is enlarged. It is understood, however, that other embodiments may have different advantages, and that no particular advantages is required for all embodiments.

In accordance with some embodiments of the present disclosure, a method for manufacturing a FinFET includes etching a base substrate to form a trapezoidal fin structure. Next, an isolation layer is deposited covering the etched base substrate. Then, the trapezoidal fin structure is exposed. The trapezoidal fin structure includes a top surface and a bottom surface, and the top surface has a width larger than that of the bottom surface.

In accordance with other embodiments of the present disclosure, a method for manufacturing a FinFET includes forming a fin structure having a top surface, a bottom surface and a pair of sidewalls over a substrate. Next, an isolation layer is deposited covering the substrate. Then, the fin structure is exposed. The top surface of the fin structure has a width larger than that of the bottom surface. At least one sidewall has more than one slope. At least one sidewall and the isolation layer have an acute included angle.

In accordance with yet other embodiments of the present disclosure, a FinFET includes a substrate, a fin structure and an isolation layer. The fin structure is over the substrate and has a top surface, a bottom surface and a pair of sidewalls. The isolation layer is over the substrate, and the fin structure is protruding from the isolation layer. The top surface of the fin structure has a width larger than that of the bottom surface. At least one sidewall has more than one slope. An included angle between at least one sidewall and the isolation layer is acute.