Magnetic random access memory cells having improved size and shape characteristics

A manufacturing method to form a memory device includes: (1) forming a dielectric layer adjacent to a magnetic stack; (2) forming an opening in the dielectric layer; (3) applying a hard mask material adjacent to the dielectric layer to form a pillar disposed in the opening of the dielectric layer; and (4) using the pillar as a hard mask, patterning the magnetic stack to form a MRAM cell.

FIELD OF THE INVENTION

The invention relates generally to memory devices. More particularly, the invention relates to memory devices including magnetic random access memory (“MRAM”) cells having improved size and shape characteristics.

BACKGROUND

MRAM devices have become the subject of increasing interest, in view of the discovery of magnetic tunnel junctions having a strong magnetoresistance at ambient temperatures. MRAM devices offer a number of benefits, such as faster speed of writing and reading, non-volatility, and insensitivity to ionizing radiations. Consequently, MRAM devices are increasingly replacing memory devices that are based on a charge state of a capacitor, such as dynamic random access memory devices and flash memory devices.

In a conventional implementation, a MRAM device includes an array of MRAM cells, each one of which includes a magnetic tunnel junction formed of a pair of ferromagnetic layers separated by a thin insulating layer. One ferromagnetic layer, the so-called reference layer, is characterized by a magnetization with a fixed direction, and the other ferromagnetic layer, the so-called storage layer, is characterized by a magnetization with a direction that is varied upon writing Of the device, such as by applying a magnetic field. When the respective magnetizations of the reference layer and the storage layer are antiparallel, a resistance of the magnetic tunnel junction is high, namely having a resistance value Rmaxcorresponding to a high logic state “1”. On the other hand, when the respective magnetizations are parallel, the resistance of the magnetic tunnel junction is low, namely having a resistance value Rmincorresponding to a low logic state “0”. A logic state of a MRAM cell is read by comparing its resistance value to a reference resistance value Rref, which is derived from a reference cell or a group of reference cells and represents an inbetween resistance value between that of the high logic state “1” and the low logic state “0”.

A MRAM device is conventionally manufactured by photolithography, in which a photoresist is used as a soft mask tier patterning a stack of magnetic layers. Specifically, a photoresist layer is formed on the stack of magnetic layers, and the photoresist layer is then patterned to form an array of dots. Portions of the stack of magnetic layers exposed by the array of dots are then etched away to form a corresponding array of MRAM cells. Subsequently, the photoresist layer is stripped to result in a MRAM device.

The above-described manufacturing method can suffer from certain deficiencies. Specifically, a size of a MRAM cell is typically governed by a resolution of photolithography, thereby presenting challenges in terms of scaling down to achieve higher densities of MRAM cells. Patterning a photoresist layer to form an array of dots with small sizes can be difficult to achieve, without the use of expensive and complex photolithographic equipment and techniques that can result in higher manufacturing costs. Moreover, shapes of resulting MRAM cells can be difficult to control, given the use of a photoresist as a soft mask. Specifically, an array of dots of the photoresist can be prone to striations or other shape imperfections, such as arising from conditions during development or exposure or arising from deformations introduced during etching, given a relatively high etch-rate of the photoresist. Such shape imperfections, in turn, can be imparted onto resulting MRAM cells, resulting in a variability of shapes in an array of the MRAM cells. This variability can impact a resistance of the MRAM cells across the array and can result in a distribution of the resistance values Rminand Rmaxfor the array, thereby complicating a comparison between a measured resistance value of an individual cell and a reference resistance value Rrefduring reading.

It is against this background that a need arose to develop the memory devices and related manufacturing methods described herein.

SUMMARY

One aspect of the invention relates to a manufacturing method to form a memory device. In one embodiment, the manufacturing method includes: (1) forming a dielectric layer adjacent to a magnetic stack; (2) forming an opening in the dielectric layer; (3) applying a hard mask material adjacent to the dielectric layer to form a pillar disposed in the opening of the dielectric layer; and (4) using the pillar as a hard mask, patterning the magnetic stack to form a MRAM cell.

Another aspect of the invention relates to a memory device. In one embodiment, the memory device includes a MRAM cell and a pillar disposed on the MRAM cell. The pillar includes a hard metal, and a sidewall of the pillar is substantially aligned with a sidewall of the MRAM cell.

Other aspects and embodiments of the invention are also contemplated. The foregoing summary and the following detailed description are not meant to restrict the invention to any particular embodiment but are merely meant to describe some embodiments of the invention.

DETAILED DESCRIPTION

Definitions

The following definitions apply to some of the aspects described with respect to sonic embodiments of the invention. These definitions may likewise be expanded upon herein.

As used herein, the singular terms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to an object can include multiple objects unless the context clearly dictates otherwise.

As used herein, the term “set” refers to a collection of one or more objects. Thus, for example, a set of objects can include a single object or multiple objects. Objects of a set also can be referred to as members of the set. Objects of a set can be the same or different. In some instances, objects of a set can share one or more common characteristics.

As used herein, the terms “substantially” and “substantial” refer to a considerable degree or extent. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation, such as accounting for typical manufacturing tolerances or variability of the embodiments described herein.

As used herein, the term “adjacent” refers to being near or adjoining. Adjacent objects can be spaced apart from one another or can be in actual or direct contact with one another. In some instances, adjacent objects can be formed integrally with one another.

As used herein, the terms “connect,” “connected,” and “connection” refer to an operational coupling or linking. Connected objects can be directly coupled to one another or can be indirectly coupled to one another, such as via another set of objects.

As used herein, the term “main group element” refers to a chemical element in any of Group IA (or Group 1), Group IIA (or Group 2), Group IIIA (or Group 13), Group IVA (or Group 14), Group VA (or Group 15), Group VIA (or Group 16), Group VIIA (or Group 17), and Group VIIIA (or Group 18). A main group element is also sometimes referred to as a s-block element or a p-block element.

As used herein, the term “transition metal” refers to a chemical element in any of Group IVB (or Group 4), Group VB (or Group 5), Group VIB (or Group 6), Group VIM (or Group 7), Group VIIIB (or Groups 8, 9, and 10). Group IB (or Group 11), and Group IIB (or Group 12). A transition metal is also sometimes referred to as a d-block element.

MRAM Devices

Attention first turns toFIG. 1AandFIG. 1B, which illustrate a memory device100implemented in accordance with an embodiment of the invention. Specifically,FIG. 1Ais a cross-sectional view of the memory device100, andFIG. 1Bis a top view of the memory device100. In the illustrated embodiment, the memory device100is a MRAM device that includes a MRAM cell102, which extends upwardly from a substrate122. For ease of presentation and to motivate certain advantages and functionalities of the memory device100, the single MRAM cell102is illustrated inFIG. 1AandFIG. 1B, although it is contemplated that multiple MRAM cells can be included, such as in the form of an array.

The MRAM cell102is implemented as a magnetic tunnel junction, and includes a storage layer104, a reference layer106, and an insulating layer108that is disposed between the storage layer104and the reference layer106. Each of the storage layer104and the reference layer106includes, or is formed of, a magnetic material and, in particular, a magnetic material of the ferromagnetic type. In general, the storage layer104and the reference layer106can include the same ferromagnetic material or different ferromagnetic materials. Examples of suitable ferromagnetic materials include transition metals, rare earth elements, and their alloys, either with or without main group elements. For example, suitable ferromagnetic materials include iron (“Fe”), cobalt (“Co”), nickel (“Ni”), and their alloys, such as permalloy (or Ni80Fe20); alloys based on Ni, Fe, and boron (“B”); Co90Fe10; and alloys based on Co, Fe, and B. A thickness of each of the storage layer104and the reference layer106can be in the nanometer (“nm”) range, such as from about 1 nm to about 20 nm or from about 1 nm to about 10 nm. The insulating layer108functions as a tunnel barrier, and includes, or is formed of, an insulating material. Examples of suitable insulating materials include oxides, such as aluminum oxide (e.g., Al2O3) and magnesium oxide (e.g., MgO). A thickness of the insulating layer108can be in the run range, such as from about 1 nm to about 10 nm.

Referring toFIG. 1A, the MRAM cell102also includes a pinning layer112, which is adjacent to the reference layer106and, through exchange bias, stabilizes a magnetization of the reference layer106along a particular direction when a temperature within, or in the vicinity of, the pinning layer112is lower than a blocking temperature TBR, or another threshold temperature such as a Neel temperature. In the illustrated embodiment, the MRAM cell102is implemented for thermally assisted switching (“TAS”), and the storage layer104also is exchange biased by another pinning layer110, which is adjacent to the storage layer104and is characterized by a blocking temperature TBR, or another threshold temperature, which is smaller than the blocking temperature TBR. Below the blocking temperature TBS, a magnetization of the storage layer110is stabilized by the exchange bias, thereby retaining a stored logic state in accordance with a direction of that magnetization. Writing is carried out by heating the MRAM cell102above the blocking temperature TBS(but below TBR), thereby unpinning the magnetization of the storage layer110to allow writing, such as by applying a magnetic field. The MRAM cell102is then cooled to below the blocking temperature TBSwith the magnetic field applied, such that the magnetization of the storage layer110is retained in its written direction.

Each of the pinning layers110and112includes, or is formed of, a magnetic material and, in particular, a magnetic material of the antiferromagnetic type. Examples of suitable antiferromagnetic materials include transition metals and their alloys. For example, suitable antiferromagnetic materials include alloys based on manganese (“Mn”), such as alloys based on iridium (“Ir”) and Mn (e.g., IrMn), alloys bused on Fe and Mn (e.g., FeMn); alloys based on platinum (“Pt”) and Mn (e.g., PtMn); and alloys based on Ni and Mn (e.g., NiMn). For certain implementations, the pinning layer110can include an alloy based on Ir and Mn (or based on Fe and Mn) with a blocking temperature TBSin the range of about 120° C. to about 220° C. or about 150° C. to about 200° C., and the pinning layer112can include an alloy based on Pt and Mn (or based on Ni and Mn) with a blocking temperature TBRin the range of about 300° C. to about 350° C.

Still referring toFIG. 1A, the MRAM cell102further includes a cap layer114, which is adjacent to the pinning layer110and forms an upper portion of the MRAM cell102. The cap layer114provides electrical connectivity, as well as either, or both, thermal insulation and a protective function for underlying layers during manufacturing of the MRAM cell102, and includes, or is formed of, an electrically conductive material. Examples of suitable electrically conductive materials include metals, such as copper, aluminum, and platinum; and alloys, such as CoSiN. A thickness of the cap layer114can be in the nm range, such as from about 1 nm to about 70 nm.

Other implementations of the MRAM cell102are contemplated. For example, the relative positioning of the storage layer104and the reference layer106can be reversed, with the reference layer106disposed above the storage layer104. As another example, either, or both, of the storage layer104and the reference layer106can include multiple sub-layers in a fashion similar to that of the so-called synthetic antiferromagnetic layer. As further examples, either, or both, of the pinning layers110and112can be omitted, and the cap layer114also can be omitted.

Referring toFIG. 1AandFIG. 1B, the memory device100also includes a pillar116, which is disposed on the MRAM cell102and adjacent to the cap layer114. A dielectric layer124is disposed on the substrate122, and at least partially covers or encapsulates the MRAM cell102and the pillar116. As further explained below, the pillar116corresponds to, or is derived from, a hard mask that is used to form the MRAM cell102. The use of such a hard mask allows the MRAM cell102to be formed with improved size and shape characteristics. Specifically, a size of the pillar116can be readily scaled down, with reduced dependence upon a resolution of photolithography, and without requiring the use of expensive and complex photolithographic equipment and techniques. Moreover, a shape of the pillar116can be controlled so as to have a well-defined contour, with a substantial absence of striations or other shape imperfections. Through its use as a hard mask, such desirable size and shape characteristics of the pillar116can be imparted onto the MRAM cell102.

As illustrated inFIG. 1AandFIG. 1B, lateral extents of the MRAM cell102and the pillar116, as represented by W, are substantially the same, and are readily scaled down to below about 0.25 μm. For certain implementations, W can be scaled down to sub-lithographic sizes below a typical resolution of photolithography, such as no greater than about 0.2 μm, no greater than about 0.15 μm, no greater than about 0.13 μm, or no greater than about 0.12 μm, and down to about 0.05 μm or less. Such scaling down of W allows a higher density of the MRAM cell102and other MRAM cells in the memory device100, as well as a reduced power consumption during TAS operations. Also, contours of the MRAM cell102and the pillar116, as viewed from the top, are both well-defined, and are substantially the same, with a circumferential sidewall118of the MRAM cell102substantially aligned or co-planar with a circumferential sidewall120of the pillar116. Such well-defined contours, in turn, provide a greater uniformity in resistance and other characteristics across the MRAM cell102and other MRAM cells in the memory device100. In the illustrated embodiment, the contours of the MRAM cell102and the pillar116are both substantially circular, with W corresponding to a diameter. However, it is contemplated that the contours of the MRAM cell102and the pillar116can be formed with other shapes, such as elliptical, square-shaped, rectangular, and other polygonal or non-polygonal shapes. In the case of a non-circular shape. W can correspond to, for example, a largest lateral extent of the non-circular shape, such as a major axis in the case of an elliptical shape. A thickness of the pillar116can be comparable to an overall thickness of the MRAM cell102, such as from about 50 nm to about 400 nm or from about 100 nm to about 350 nm.

The pillar116includes, or is formed of, a hard mask material. A hard mask material can be characterized by a relatively high resistance towards deformation or etching, such as in accordance with a Vickers hardness or another measure of hardness or etch selectivity. Examples of suitable hard mask materials include hard metals, such as tungsten, molybdenum, and titanium; alloys of hard metals, either with or without main group elements, such as alloys of tungsten and titanium; and other patternable materials having a measure of hardness or etch selectivity that is comparable, or superior, to that of tungsten, molybdenum, or titanium, such as one having a Vickers hardness that is at least about 950 Megapascal (“MPa”), at least about 1,500 MPa, or at least about 3,400 MPa. A hard metal is typically electrically conductive, and, by leveraging the electrical conductivity of tungsten or another hard metal, the pillar116can serve a further function of an electrical interconnect, thereby obviating operations to form a set of vias on the MRAM cell102. However, it is contemplated that the pillar116can be used in conjunction with a set of vias to establish a desired electrical connection to the MRAM cell102.

Manufacturing Methods of MRAM Devices

FIG. 2AthroughFIG. 2Jillustrate a sequence of cross-sectional views of a manufacturing method to form a memory device, according to an embodiment of the invention. Referring first toFIG. 2A, a substrate200is provided, on which a magnetic stack202is disposed. Although not illustrated inFIG. 2A, the substrate200can include a set of dielectric layers and a set of semiconductor devices, such as transistors, which can be electrically connected to the magnetic stack202through traces, vias, or other electrical interconnect. The magnetic stack202includes a set of layers that form a magnetic tunnel junction, as well as an upper, cap layer208. Various layers of the magnetic stack202can be formed on the substrate200by a suitable deposition technique, such as chemical vapor deposition (“CVD”), plasma enhanced chemical vapor deposition (“PECVD”), vacuum deposition, or a combination of such techniques. Other implementations of the magnetic stack202are contemplated, such as one in which the cap layer208is omitted.

Still referring toFIG. 2A, a set of dielectric layers are formed on the magnetic stack202by a suitable coating or deposition technique, such as spin-on coating, CVD, PECVD, vacuum deposition, or a combination of such techniques. Specifically, a dielectric layer204is formed on the cap layer208, and then another dielectric layer206is formed on the dielectric layer204. In general, the dielectric layers204and206can include the same dielectric material or different dielectric materials. Examples of suitable dielectric materials include silicon oxide (e.g., tetraethyl orthosilicate (“TEOS”)), silicon nitride, silicon oxynitride, and silicon carbide. As illustrated inFIG. 2A, the dielectric layers204and206include different dielectric materials, such as silicon nitride and TEOS, respectively, which have different resistance towards etching or different etch-rates. In such manner, the dielectric layer206can be preferentially etched in a subsequent operation, while the dielectric layer204can remain to protect underlying layers. It is also contemplated that the dielectric layer204can be omitted.

Referring next toFIG. 2B, a set of openings210aand210bare formed in the dielectric layer206by photolithography, or another suitable patterning technique. Specifically, a photoresist layer is formed on the dielectric layer206, and a set of openings are formed in the photoresist layer at locations under which a set of MRAM cells are to be formed. Portions of the dielectric layer206exposed by the openings in the photoresist layer are then etched away to form the corresponding openings210aand210bin the dielectric layer206. Subsequently, the photoresist layer is stripped to result in a configuration as illustrated inFIG. 2B. Although the two openings210aand210bare illustrated inFIG. 2B, it is contemplated that more or less openings can be formed.

Advantageously, an array of openings having desired sizes and shapes can be more readily formed by photolithography, as compared to an array of dots. Specifically, the openings210aand210bcan be formed with small lateral extents and well-defined contours, with a substantial absence of striations or other shape imperfections. For example, the openings210aand210bcan have lateral extents that are less than about 0.25 μm and substantially circular contours when viewed from the top. Such control over size and shape characteristics of the openings210aand210b, in turn, allows control over size and shape characteristics of resulting MRAM cells. In the illustrated embodiment, desirable size and shape characteristics of the openings210aand210bcan be achieved without requiring the use of expensive and complex photolithographic equipment and techniques, such as by forming a thicker, more etch-resistant photoresist layer using a 248 nm photoresist, instead of a 193 nm photoresist, and defining small, circular openings in the photoresist layer by overexposure. Alternatively, complex photolithographic equipment and techniques can be used to yield further improvements in size and shape characteristics.

As illustrated inFIG. 2B, the openings210aand210bextend through the dielectric layer206to partially expose the dielectric layer204at locations corresponding to those of resulting MRAM cells. Because of different etch-rates of the dielectric layers204and206, the dielectric layer206is preferentially etched such that the openings210aand210bterminate substantially at a boundary between the dielectric layers204and206. Referring toFIG. 2B, sidewalls of the openings210aand210bform an angle α with respect to a horizontal plane, with the sidewalls being substantially vertical, and with the angle α at or close to 90°, such as in the range of about 80° to about 90°, about 85° to about 90°, or about 87° to about 90°. Such vertical orientation of the sidewalls of the openings210aand210bfacilitates patterning of the magnetic stack202, using a hard mask that is formed in the openings210aand210bas further explained below.

To allow the formation of MRAM cells with even smaller lateral extents, such as in the sub-lithographic range, spacers can be formed in the openings210aand210bto reduce their lateral extents resulting from photolithography. As illustrated inFIG. 2C, a liner layer212is formed on the dielectric layer206, with the liner layer212extending into the openings210aand210band partially filling the openings210aand210balong their sidewalls. The liner layer212includes TEOS or another suitable dielectric material, and is formed by a suitable coating or deposition technique, such as CVD, MCVD, vacuum deposition, a combination of such techniques, or any other conformal deposition technique. Next, portions of the liner layer212and the dielectric layers204and206are removed by etching, resulting in a configuration as illustrated inFIG. 2D. Specifically, portions of the liner layer212disposed on top of the dielectric layer206and at the bottom of the openings210aand210bare etched away, resulting in spacers214aand214bthat are disposed along the sidewalls of the openings210aand210b. In the illustrated embodiment, portions of the dielectric layer204disposed at the bottom of the openings210aand210bare also etched away. In such manner, the openings210aand210bextend through the dielectric layers204and206to partially expose the cap layer208at locations corresponding to those of resulting MRAM cells, and the openings210aand210balso have reduced lateral extents because of the presence of the spacers214aand214b. As illustrated inFIG. 2D, etching may also remove portions of the dielectric layer206, resulting in some curving or rounding of the sidewalls near the top of the openings210aand210b.

Turning next toFIG. 2E, a hard mask layer216is formed on the dielectric layer206, with the hard mask layer216extending into the openings210aand210band substantially filling, or plugging, the openings210aand210b, as circumferentially bounded by the spacers214aand214b. The hard mask layer216includes a hard mask material, such as tungsten or another hard metal, and is formed by applying the hard mask material using a suitable deposition technique, such as CVD, PECVD, vacuum deposition, a combination of such techniques, or any other conformal deposition technique. As further explained below, portions of the hard mask layer216disposed in the openings210aand210bserve as a hard mask for patterning the magnetic stack202. Advantageously, such a hard mask can have a greater resistance towards etching or a lower etch-rate, as compared to a photoresist or another dielectric material conventionally used for patterning the magnetic stack202. As a result, a shape integrity of the hard mask can be substantially preserved through etching, and resulting MRAM cells can be formed with well-defined contours, with a substantial absence of striations or other shape imperfections.

Next, portions of the hard mask layer216and the dielectric layer206are removed by chemical mechanical polishing (“CMP”) or another suitable abrasive or leveling technique, resulting in a configuration as illustrated inFIG. 2F. Specifically, CMP is carried out to expose the top of the openings210aand210b, and remaining portions of the hard mask layer216correspond to pillars218aand218b, which are disposed in the openings210aand210b, and which serve as a hard mask for patterning the underlying magnetic stack202. As illustrated inFIG. 2F, CMP also removes the curved or rounded portions of the sidewalk near the top of the openings210aand210b. In such manner, the resulting pillars218aand218bhave sidewalls that are substantially vertical to facilitate patterning of the magnetic stack202.

The dielectric layers204and206and the spacers214aand214bare next removed by selective etching, resulting in a configuration as illustrated inFIG. 20. Because of their greater etch-rates, the dielectric layers204and206and the spacers214aand214bare preferentially etched away, with the pillars218aand218bremaining on the cap layer208at locations under which MRAM cells are to be formed. The magnetic stack202is then patterned, using the pillars218aand218bas a hard mask. Specifically, portions of the magnetic stack202exposed by the pillars218aand218bare removed by ion beam etching (“IBE”) or another suitable etching technique such as reactive ion etching (“RIE”), while portions of the magnetic stack202under the pillars218aand218bare protected, thereby forming MRAM cells220aand220bas illustrated inFIG. 2H. Because of its high resistance towards etching or its low etch-rate, a shape integrity of the pillars218aand218bcan be substantially preserved through IBE or RIE, thereby imparting desirable size and shape characteristics onto the MRAM cells220aand220b. As illustrated inFIG. 2H, IBE or RIE may produce some curving or rounding near the top of the pillars218aand218b. In some implementations, a strap layer can be formed at this stage.

Turning next toFIG. 2I, a dielectric layer222is formed on the substrate200so as to cover or encapsulate the pillars218aand218band the MRAM cells220aand220b.The dielectric layer222includes TEOS or another suitable dielectric material or a combination of different dielectric layers, and is formed by a suitable coating or deposition technique, such as CVD, PECVD, vacuum deposition, a combination of such techniques, or any other conformal deposition technique. Next, portions of the dielectric layer222and the pillars218aand218bare removed by CMP or another suitable abrasive or leveling technique, resulting in a configuration as illustrated inFIG. 22. Specifically, CMP is carried out to expose the top of the pillars218aand218b, using the pillars218aand218bas a stop layer. Thus, by leveraging the hardness of tungsten or another hard metal, the pillars218aand218bcan serve dual functions of a hard mask during etching and a stop layer during CMP. As illustrated inFIG. 2J, CMP also removes the curved or rounded top portions of the pillars218aand218b, resulting in substantially planar surfaces at the top of the pillars218aand218b. In such mariner, a memory device224is formed. Because the pillars218aand218bare formed of an electrically conductive material, the pillars218aand218bcan establish electrical connections between the MRAM cells220aand220band traces or semiconductor devices, which can be formed on top of the pillars218aand218band the dielectric layer222. Thus, by leveraging the electrical conductivity of tungsten or another hard metal, the pillars218aand218bcan further serve as electrical interconnects, thereby obviating operations to form a set of vias on top of the MRAM cells220a. and220b.However, it is contemplated that the pillars218aand218bcan be used in conjunction with a set of vias to establish desired electrical connections to the MRAM cells220aand220b. For example, CMP can stop at a certain distance above the pillars218aand218b, such as from about 100 nm to about 400 nm above the pillars218aand218b, and a via can be formed through the dielectric layer222to reach the top of the pillars218aand218b. This via can be used to connect the IMAM cells220aand220bto a metal layer formed above the dielectric layer222.