DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS

A display substrate, where each sub-pixel includes lower and upper electrodes on a base substrate; the lower electrode includes multiple first and second electrode strips; the upper electrode includes multiple third and fourth electrode strips; the first and third electrode strips are electrically connected together; the second and fourth electrode strips are electrically connected together; two adjacent electrode strips in the first and/or second electrode strips are mutually spaced apart; two adjacent electrode strips in the third and/or fourth electrode strips are mutually spaced apart; M sequentially adjacent first electrode strips and N sequentially adjacent second electrode strips are alternately arranged; M sequentially adjacent third electrode strips and N sequentially adjacent fourth electrode strips are alternately arranged; M=1, 2, 3, . . . ; N=1, 2, 3, . . . ; M and N are integers; and orthographic projections of the electrode strips of the upper and lower electrodes on the base substrate are alternately arranged.

TECHNICAL FIELD

Embodiments of the present disclosure belong to the field of display technology, and in particular, relate to a display substrate, a manufacturing method thereof and a display apparatus.

BACKGROUND

An ADS (including HADS) display mode of a liquid crystal display panel belongs to a plane electric field display mode, and an electric field in a liquid crystal cell is not uniformly distributed in the transverse direction and the longitudinal direction. When positive and negative frames are changed, liquid crystal molecules are distorted and deformed due to the flexoelectric effect of the liquid crystal, so that the transmittances of the sub-pixels in the positive and negative frames are different from each other, and finally a measured VT (Voltage-Transmittance) curve is asymmetric. The VT curve is the most important basis for adjusting the sub-pixel driving voltage (i.e. Gamma tuning), and if the VT curve is asymmetric, it will result in defects such as decreased transmittance, flicker in display image, image sticking, or flicker drift.

SUMMARY

The embodiments of present disclosure provide a display substrate, a manufacturing method thereof and a display apparatus.

In a first aspect, an embodiment of the present disclosure provides a display substrate, including:a base substrate; anda plurality of sub-pixels on the base substrate and arranged in an array,where each of the plurality of sub-pixels includes a lower electrode and an upper electrode, and the lower electrode and the upper electrode are sequentially stacked in a direction away from the base substrate;the lower electrode includes a plurality of first electrode strips and a plurality of second electrode strips; the upper electrode includes a plurality of third electrode strips and a plurality of fourth electrode strips; the plurality of first electrode strips are electrically connected to the plurality of third electrode strips; the plurality of second electrode strips are electrically connected to the plurality of fourth electrode strips;two adjacent electrode strips in the first electrode strips and/or the second electrode strips are spaced apart from each other; and two adjacent electrode strips in the third electrode strips and/or the fourth electrode strips are spaced apart from each other;M number of sequentially adjacent first electrode strips and N number of sequentially adjacent second electrode strips are alternately arranged;M number of sequentially adjacent third electrode strips and N number of sequentially adjacent fourth electrode strips are alternately arranged; where M=1, 2, 3, . . . ; N=1, 2, 3, . . . ; and M and N are integers;orthographic projections of the electrode strips of the upper electrode and the electrode strips of the lower electrode on the base substrate are alternately arranged; andone of the first electrode strips and one of the fourth electrode strips are each arranged at a first place in a first direction; and the first direction is an arrangement direction of the first electrode strips and the second electrode strips and also an arrangement direction of the third electrode strips and the fourth electrode strips.

In some embodiments, all the first electrode strips and the second electrode strips have a same width; anda first spacing between any two adjacent electrode strips in the first electrode strips and/or the second electrode strips is equal.

In some embodiments, all the third electrode strips and the fourth electrode strips have a same width; anda second spacing between any two adjacent electrode strips in the third electrode strips and/or the fourth electrode strips is equal.

In some embodiments, all the first electrode strips and the third electrode strips have a same width; and/orthe first spacing and the second spacing are equal to each other.

In some embodiments, a ratio of the width of the first electrode strip to the first spacing is in a range from 1/3 to 3/4; anda ratio of the width of the third electrode strips to the second spacing is in a range from 1/3 to 3/4.

In some embodiments, the display apparatus further includes a plurality of gate lines, a plurality of data lines, a plurality of common electrode lines, and a plurality of switching transistors;each of the plurality of gate lines is between two adjacent rows of the sub-pixels;each of the plurality of data lines is between two adjacent columns of the sub-pixels;each of the plurality of common electrode lines is between two adjacent rows of the sub-pixels;the gate line connected to the sub-pixels in a same row and the common electrode line connected to the sub-pixels in the same row are on two sides of the sub-pixels in this row along an extending direction of the data line;the gate lines and the data lines are spatially crossed to form a plurality of pixel regions; andlengths of the first electrode strip, the second electrode strip, the third electrode strip and the fourth electrode strip extend along the extending direction of the data line.

In some embodiments, the lower electrode further includes a first connection part and a second connection part;the first connection part is at an end of the first electrode strip close to the common electrode line, and is connected to the first electrode strip and the common electrode line; andthe second connection part is at an end of the second electrode strip close to the gate line, and is connected to the second electrode strip and a drain of the switching transistor.

In some embodiments, the upper electrode further includes a third connection part and a fourth connection part;the third connection part is at an end of the third electrode strip close to the common electrode line, and is connected to the third electrode strip and the common electrode line; andthe fourth connection part is at an end of the fourth electrode strip close to the gate line, and is connected to the fourth electrode strip and the drain of the switching transistor.

In some embodiments, a length of the first connection part extends along an extending direction of the common electrode line;the first connection part is connected to the plurality of first electrode strips to form a comb-shaped structure;a length of the second connection part extends along an extending direction of the gate line; andthe second connection part is connected to the plurality of second electrode strips to form a comb-shaped structure.

In some embodiments, a length of the third connection part extends along the extending direction of the common electrode line;the third connection part is connected to the plurality of third electrode strips to form a comb-shaped structure;a length of the fourth connection part extends along the extending direction of the gate line; andthe fourth connection part is connected to the plurality of fourth electrode strips to form a comb-shaped structure.

In some embodiments, a gate of the switching transistor, the gate line, the common electrode line, and the lower electrode are on the base substrate;an active layer of the switching transistor is on a side of the gate away from the base substrate, and a gate insulating layer is between the gate and the active layer;a source and the drain of the switching transistor are on a side of the active layer away from the base substrate, and are arranged at two opposite ends of the active layer, respectively;the upper electrode is on a side of the source and the drain away from the base substrate, and a passivation layer is between the upper electrode, and the source and the drain;the gate insulating layer and the passivation layer each further extend between the lower electrode and the upper electrode;the first connection part and the common electrode line are formed integrally into a one-piece structure;an orthographic projection of the third connection part on the base substrate at least partially overlaps an orthographic projection of the common electrode line on the base substrate;a first via is formed in the passivation layer and the gate insulating layer at a region where the orthographic projection of the third connection part on the base substrate overlaps the orthographic projection of the common electrode line on the base substrate, and the third connection part is connected to the common electrode line through the first via.

In some embodiments, a part of the second connection part extends such that an orthographic projection of the second connection part on the base substrate overlaps an orthographic projection of the drain on the base substrate;a part of the fourth connection part extends such that an orthographic projection of the fourth connection part on the base substrate overlaps the orthographic projection of the drain on the base substrate; anda second via is formed in the passivation layer and the gate insulating layer at a region where the orthographic projections of the second connection part, the fourth connection part and the drains on the base substrate overlap each other, and the fourth connection part is connected to the drain and the second connection part through the second via.

In some embodiments, one of the third electrode strips at an edge of the upper electrode extends toward the drain to form a first sub-portion;the drain extends toward the first sub-portion to form a second sub-portion; andorthographic projections of the first sub-portion and the second sub-portion on the base substrate overlap each other.

In some embodiments, one of the first electrode strips at the edge of the lower electrode extends toward the drain to form a third sub-portion; andan orthographic projection of the third sub-portion on the base substrate overlaps the orthographic projection of the second sub-portion on the base substrate.

In some embodiments, an orthographic projection of the third electrode strip at the edge of the upper electrode on the base substrate overlaps an orthographic projection of the data line on the base substrate; anda width of the third electrode strip at the edge of the upper electrode and having the orthographic projection on the base substrate overlapping the orthographic projection of the data line on the base substrate is greater than a width of the third electrode strip in the pixel region.

In some embodiments, an orthographic projection of the first electrode strip at an edge of the lower electrode on the base substrate overlaps the orthographic projection of the data line on the base substrate; anda width of the first electrode strip at the edge of the lower electrode and having the orthographic projection on the base substrate overlapping the orthographic projection of the data line on the base substrate is greater than a width of the first electrode strip in the pixel region.

In some embodiments, the sub-pixel is divided into two domains in the extending direction of the data line;a domain boundary between the two domains extends along an extending direction of the gate line;a part of the data line near the domain boundary is bent in a direction approaching the domain boundary; andparts of the first electrode strip, the second electrode strip, the third electrode strip and the fourth electrode strip near the domain boundary are each bent in the direction approaching the domain boundary, and bent shapes of the parts are each matched with a bent shape of the data line.

In a second aspect, an embodiment of the present disclosure further provides a method of manufacturing a display substrate, where the method includes: forming a plurality of sub-pixels on a base substrate;the forming the plurality of sub-pixels includes: sequentially forming a lower electrode and an upper electrode on the base substrate;the forming the lower electrode includes: forming a plurality of first electrode strips and a plurality of second electrode strips; andthe forming the upper electrode includes: forming a plurality of third electrode strips and a plurality of fourth electrode strips.

In some embodiments, the plurality of first electrode strips and the plurality of second electrode strips are formed through one patterning process; andthe plurality of third electrode strips and the plurality of fourth electrode strips are formed through one patterning process.

In a third aspect, an embodiment of the present disclosure further provides a display apparatus, where the display apparatus includes the display substrate described above.

DETAIL DESCRIPTION OF EMBODIMENTS

In order to enable one of ordinary skill in the art to better understand the technical solutions of the embodiments of the present disclosure, a display substrate, a manufacturing method thereof, and a display apparatus provided in the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific implementations.

The embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings, and may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to one of ordinary skill in the art.

The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on a manufacturing process. Thus, the regions illustrated in the figures have schematic properties, and the shapes of the regions shown in the figures illustrate specific shapes of the regions, but are not intended to be limiting.

FIG.1Ais a top view illustrating a structure of a sub-pixel in a liquid crystal display panel of an ADS (Advanced Super Dimension Switch) or HADS (High Advanced Super Dimension Switch) display mode in the related art;FIG.1Bis a cross-sectional view illustrating a structure taken along a section line AA′ inFIG.1A;FIG.1Cis a cross-sectional view illustrating a structure taken along a section line BB′ inFIG.1A;FIG.1Dis a cross-sectional view illustrating a structure taken along a section line CC′ inFIG.1A. Referring toFIG.1A, in the related art, the display panel includes a gate line3, a data line4, a common electrode line5, and a switching transistor6; the gate lines3and the data lines4are spatially crossed to define a pixel region, and a sub-pixel2is arranged in the pixel region; the common electrode line5and the gate line3are arranged on two opposite sides of the sub-pixel2along an extending direction of the data line4, respectively; the switching transistor6is located in the pixel region and at a position where the gate line3and the data line4cross each other. The switching transistor6includes a gate60, an active layer62, a source63and a drain64; the source63and the drain64are arranged on two opposite ends of the active layer62, respectively, and are each in contact with the active layer62. The sub-pixel2includes two electrodes which are sequentially stacked on a base substrate10, the top one is a slit-shaped common electrode11, the bottom one is a planar pixel electrode12, the top electrode and the bottom electrode are insulated from each other by arranging an insulating layer13, and orthographic projections of the two electrodes on the base substrate10overlap each other. The bottom pixel electrode12is connected to the drain64of the switching transistor6through a third via14formed in the insulating layer13and a conductive structure15arranged in the same layer as the top common electrode11but not connected to the top common electrode11. The top common electrode11is connected to the bottom common electrode line5(which is arranged in the same layer as the pixel electrode12but not connected to the pixel electrode12) through a fourth via16formed in the insulating layer13.

Since the electric field in the liquid crystal cell is not uniformly distributed in the transverse direction and the longitudinal direction, the electric fields of the positive and negative frames are asymmetric to each other. When the positive and negative frames are changed, liquid crystal molecules are distorted and deformed due to the flexoelectric effect of the liquid crystal, so that the transmittances of the sub-pixels in the positive and negative frames are different from each other, and the difference is mainly at dark regions with the lowest transmittance. Referring toFIG.1E, which is a schematic diagram illustrating a difference between electric field/optical effect of the sub-pixel structure inFIG.1Ain a positive frame and electric field/optical effect of the sub-pixel structure inFIG.1Ain a negative frame, as can be seen fromFIG.1E, in the positive frame, the dark region is right above the top common electrode strip; in the negative frame, the dark region is between the top common electrode strips adjacent to each other. The more the dark regions are, the larger the difference between the light effects (i.e. transmittances) of the positive and negative frames is, and the transmittance curves of the positive and negative frames are different in the dark regions. According to the simulation and actual measurement results, referring toFIG.1F, which is a VT curve (i.e., voltage-transmittance curve) of the sub-pixel structure inFIG.1Ain positive and negative frames, it can be seen fromFIG.1Fthat the data voltage corresponding to the point with the highest transmittance (i.e., VOP voltage) in the VT curve is 6.5V, and a difference proportion between the positive and negative frame transmittances (positive frame transmittance/negative frame transmittance) is 97.3%. That is, the VT curve of the sub-pixel structure inFIG.1Ais asymmetric.

The asymmetry of the VT curve will cause the following problems. First, the transmittance is decreased; the reason for this problem is as follows: in order to ensure that the difference between the positive and negative frame transmittances is minimum, during setting the voltages on both ends (namely, data voltages corresponding to several points with high transmittances in the positive and negative frames in the VT curve), voltages corresponding to points with lower transmittances are selected (namely, in the data voltages corresponding to the several points with high transmittances in the positive and negative frames in the VT curve, data voltages corresponding to points with the lowest point transmittances in the VT curve are selected), and the other points with higher transmittances are sacrificed, so that the overall transmittance of the liquid crystal display panel is decreased. Second, the display image flickers; the reason of this problem is as follows: there is a difference between sub-pixel transmittances for the positive and negative frames, and human eyes can see flickers, and the larger the difference between the sub-pixel transmittances for the positive and negative frames is, the more obvious flickers can be seen. Third, image sticking or flicker drift; the reason for this problem is as follows: the asymmetry of the positive and negative frame electric fields (i.e. the asymmetry of the voltages at points with the high transmittance in the positive and negative frames) causes polarization of the liquid crystal, and the direct current bias voltage in the cell is generated, resulting in the defect of image sticking or flicker drift.

In view of the above problems in the prior art, in a first aspect, a display substrate is provided according to an embodiment of the present disclosure.FIG.2Ais a top view illustrating a part of a structure of the display substrate according to an embodiment of the present disclosure;FIG.2Bis a cross-sectional view of a structure taken along a section line aa′ inFIG.2A;FIG.3Ais a top view illustrating a part of a structure of a display substrate according to an embodiment of the present disclosure;FIG.3Bis a cross-sectional view illustrating a structure taken along a section line bb′ inFIG.3A. Referring toFIGS.2A,2B,3A, and3B, the display substrate includes a base substrate1, and a plurality of sub-pixels2arranged on the base substrate1in an array. The sub-pixel2includes a lower electrode21and an upper electrode22, and the lower electrode21and the upper electrode22are sequentially stacked in a direction away from the base substrate1. The lower electrode21includes a plurality of first electrode strips211and a plurality of second electrode strips212. The upper electrode22includes a plurality of third electrode strips221and a plurality of fourth electrode strips222. The first electrode strip211is electrically connected to the third electrode strip221. The second electrode strip212is electrically connected to the fourth electrode strip222. Two adjacent electrode strips in the first electrode strips211and/or the second electrode strips212are spaced apart from each other. Two adjacent electrode strips in the third electrode strips221and/or the fourth electrode strips222are spaced apart from each other. M number of sequentially adjacent first electrode strips211and N number of sequentially adjacent second electrode strips212are alternately arranged; M number of sequentially adjacent third electrode strips221and N number of sequentially adjacent fourth electrode strips222are alternately arranged; where M=1, 2, 3, . . . ; N=1, 2, 3, . . . ; and M and N are integers. Orthographic projections of the electrode strips of the upper electrode22and the electrode strips of the lower electrode21on the base substrate1are alternately arranged. The first electrode strip211(or the second electrode strip212) and the fourth electrode strip222(or the third electrode strip221) are each arranged at a first place in a first direction X, where the first direction X is a direction of arranging the first electrode strips211and the second electrode strips212and a direction of arranging the third electrode strips221and the fourth electrode strips222.

In some embodiments, the first electrode strips211, the second electrode strips212, the third electrode strips221, and the fourth electrode strips222are parallel to each other.

In some embodiments, referring toFIGS.3A and3B, M=N=2. As it should be, the number of the electrode strips is not limited in the present disclosure, and may be designed according to actual requirements.

In some embodiments, referring toFIGS.2B and3B, an orthographic projection of one electrode strip of the lower electrode21on the base substrate1is between orthographic projections of two adjacent electrode strips of the upper electrode22on the base substrate1. Similarly, an orthographic projection of one electrode strip of the upper electrode22on the base substrate1is between orthographic projections of two adjacent electrode strips of the lower electrode21on the base substrate1. The orthographic projections of the electrode strips of the upper electrode22and the electrode strips of the lower electrode21on the base substrate1do not overlap each other. With such an arrangement, a uniform and symmetrical electric field may be formed between the upper electrode22and the lower electrode21, so as to eliminate the problem of nonuniform distribution of the electric field in the liquid crystal display substrate, thereby eliminating the problem of asymmetric VT (voltage-transmittance) curve of the display panel in an ADS display mode in the prior art, and improving the display transmittance and even the display effect of the display substrate.

FIG.2Cis a cross-sectional view illustrating a structure taken along a section line aa′ inFIG.2A;FIG.3Cis a cross-sectional view of a structure taken along a section line bb′ inFIG.3A. In some embodiments, referring toFIGS.2C and3C, alternatively the orthographic projections of the electrode strips of the upper electrode22and the electrode strips of the lower electrode21on the base substrate1may partially overlap each other. For example, with respect to one electrode strip of the upper electrode22and one electrode strip of the lower electrode21, which have adjacent orthographic projections on the base substrate1, the orthographic projection of the electrode strip of the upper electrode22on the base substrate1overlaps an orthographic projection of an adjacent edge of the electrode strip of the lower electrode21on the base substrate1; for example, it is possible that an orthographic projection of the third electrode strip221on the base substrate1overlaps an orthographic projection of an adjacent edge of the second electrode strip212on the base substrate1; it is also possible that the orthographic projection of the third electrode strip221on the base substrate1overlaps an orthographic projection of an adjacent edge of the first electrode strip211on the base substrate1; it is also possible that an orthographic projection of fourth electrode strip222on the base substrate1overlaps an orthographic projection of an adjacent edge of the second electrode strip212on the base substrate1.

In some embodiments, the widths of the first electrode strip211and the second electrode strip212are equal to each other; and a first spacing s1 between any two adjacent electrode strips in the first electrode strips211and/or the second electrode strips212is equal.

In some embodiments, the widths of the third electrode strips221and the fourth electrode strips222are equal to each other; and a second spacing s2 between any two adjacent electrode strips in the third electrode strips221and/or the fourth electrode strips222is equal.

In some embodiments, the widths of the first electrode strips211and the third electrode strips221are equal to each other; and/or the first spacing s1 and the second spacing s2 are equal to each other.

In some embodiments, a ratio of the width of the first electrode strip211to the first spacing s1 is in a range from 1/3 to 3/4; and a ratio of the width of the third electrode strip221to the second spacing s2 is in a range from 1/3 to 3/4.

In some embodiments, the width of each of the first electrode strips211and the second electrode strips212is in a range from 2 μm to 3 μm; and the first spacing s1 is in a range from 4 μm to 6 μm.

In some embodiments, the width of each of the first electrode strips and the second electrode strips is in a range from 2.2 μm to 2.9 μm; and the first spacing s1 is in a range from 4.8 μm to 5.8 μm.

In some embodiments, the width of each of the third electrode strips221and the fourth electrode strips222is in a range from 2 μm to 3 μm; and the second spacing s2 is in a range from 4 μm to 6 μm.

In some embodiments, the width of each of the third electrode strips221and the fourth electrode strips222is in a range from 2.2 μm to 2.9 μm; and the second spacing s2 is in a range from 4.8 μm to 5.8 μm.

In some embodiments, referring toFIGS.2A and3A, the display substrate further includes a plurality of gate lines3, a plurality of data lines4, a plurality of common electrode lines5, and a plurality of switching transistors6. The gate line3is located between two adjacent rows of sub-pixels2. The data line4is located between two adjacent columns of sub-pixels2. The common electrode line5is located between two adjacent rows of sub-pixels2. The gate line3connecting to the sub-pixels2in a same row and the common electrode line5connecting to the sub-pixels2in the same row are located on two sides of the sub-pixels2in the same row in an extending direction of the data line4. The gate lines3and the data lines4are spatially crossed to form a plurality of pixel regions. Lengths of the first electrode strips211, the second electrode strips212, the third electrode strips221, and the fourth electrode strips222extend along the extending direction of the data line4.

A plurality of sub-pixels2are located in the plurality of pixel regions, respectively, in a one-to-one correspondence. The plurality of switching transistors6are in the plurality of pixel regions, respectively, in a one-to-one correspondence, and the switching transistor6is located at a position where the gate line3and the data line4cross each other. The switching transistor6includes a gate60, an active layer62, a source63and a drain64. The gate60is connected to the gate line3. The source63is connected to the data line4. The drain64is connected to the fourth electrode strips222in the upper electrode22and the second electrode strips212in the lower electrode21. When a scan signal is input to the gate line3, the switching transistor6is turned on, and a data voltage signal in the data line4is input to the fourth electrode strip222in the upper electrode22and the second electrode strip212in the lower electrode21. The third electrode strips221in the upper electrode22and the first electrode strips211in the lower electrode21are connected to the common electrode line5, which provides a common voltage signal for the third electrode strips221and the first electrode strips211. An electric field is formed between the upper electrode22and the lower electrode21to drive liquid crystal molecules in the display substrate to deflect, so that the display substrate displays.

FIG.2Dis a top view illustrating a structure of the lower electrode inFIG.2A; andFIG.3Dis a top view illustrating a structure of the lower electrode inFIG.3A. In some embodiments, referring toFIGS.2D and3D, the lower electrode21further includes a first connection part213and a second connection part214. The first connection part213is located at an end of the first electrode strip211close to the common electrode line5, and the first connection part213is connected to the first electrode strip211and the common electrode line5. Optionally, the first connection part213may be directly electrically connected to the common electrode line5through lapping. For example, in a manufacturing process, first, a patterned lower electrode21is formed, then, the common electrode line5is formed. In this case, the first connection part213and the common electrode line5overlap each other, and the overlapped parts may be directly electrically connected together. In this case, in the manufacturing process, the gate line3, the lower electrode21and the first connection part213may be arranged in the same layer, and then, the common electrode line5is deposited. The second connection part214is located at an end of the second electrode strip212close to the gate line3, and the second connection part214is connected to the second electrode strip212and the drain64of the switching transistor6. Referring toFIG.2D, the second connection part214includes a bulge extending toward the gate line3, and the bulge is electrically connected to the drain64.

FIG.2Eis a top view illustrating a structure of the upper electrode inFIG.2A; andFIG.3Eis a top view illustrating a structure of the upper electrode inFIG.3A. In some embodiments, referring toFIGS.2E and3E, the upper electrode22further includes a third connection part223and a fourth connection part224. The third connection part223is located at an end of the third electrode strip221close to the common electrode line5, a first via8is provided in the insulating layer under the third connection part223, and the third connection part223is electrically connected to the first connection part213of the lower electrode21through the first via8in the insulating layer. Optionally, in the process, subsequent to depositing the film layer of the first connection part213, an insulating layer is deposited, where the number of layers of the insulating layer is not limited. Subsequent to depositing the insulating layer, the first via8is formed in the insulating layer. Where the insulating layer is a multilayer, each layer may be perforated, and finally the vias overlap each other and finally are communicated with each other. Alternatively, after the last insulating layer is formed, one perforation process may be performed, which is not limited herein. Subsequent to forming a via in the insulating layer, the upper electrode22is deposited, where a part of the material of the third electrode strip221of the upper electrode22is deposited into the first via8in the insulating layer, so that the third electrode strip221is electrically connected to the first electrode strip211of the lower electrode21. Since the first electrode strip211is electrically connected to the common electrode line5, the third electrode strip221and the first electrode strip211are both electrically connected to the common electrode line5. Here, the third connection part223is connected to the third electrode strip221and the common electrode line5. The fourth connection part224is located at an end of the fourth electrode strip222close to the gate line3, and the fourth connection part224is connected to the fourth electrode strip222and the drain64of the switching transistor6. Referring toFIG.2E, the fourth connection part224includes a bulge extending toward the gate line3, and the bulge and the drain64may be electrically connected together through the first via8in the insulating layer.

It should be noted that the line widths in the drawings are only schematic line widths, and do not represent actual line widths in actual processes.

In some embodiments, referring toFIGS.2D and3D, the length of the first connection part213extends along an extending direction of the common electrode line5. The first connection part213is connected to the plurality of first electrode strips211to form a comb-shaped structure. The length of the second connection part214extends along an extending direction of the gate line3. The second connection part214is connected to the plurality of second electrode strips212to form a comb-shaped structure.

An included angle greater than 0° is formed between the extending direction of the first connection part213and the extending direction of the first electrode strips211, so that the first connection part213is connected to the plurality of first electrode strips211with the same extending direction, to form a comb-shaped structure. That is, the first connection part213corresponds to a comb handle of the comb-shaped structure, and the plurality of first electrode strips211correspond to comb teeth of the comb-shaped structure. An included angle greater than 0° is formed between the extending direction of the second connection part214and the extending direction of the second electrode strips212, so that the second connection part214is connected to the plurality of second electrode strips212with the same extending direction, to form a comb-shaped structure. That is, the second connection part214corresponds to a comb handle of the comb-shaped structure, and the plurality of second electrode strips212correspond to comb teeth of the comb-shaped structure.

In some embodiments, referring toFIGS.2E and3E, the length of the third connection part223extends along the extending direction of the common electrode line5. The third connection part223is connected to the plurality of third electrode strips221to form a comb-shaped structure. The length of the fourth connection part224extends along the extending direction of the gate line3. The fourth connection part224is connected to the plurality of fourth electrode strips222to form a comb-shaped structure.

An included angle greater than 0° is formed between the extending direction of the third connection part223and the extending direction of the third electrode strips221, so that the third connection part223is connected to the plurality of third electrode strips221with the same extending direction, to form a comb-shaped structure. That is, the third connection part223corresponds to a comb handle of the comb-shaped structure, and the plurality of third electrode strips221correspond to comb teeth of the comb-shaped structure. An included angle greater than 0° is formed between the extending direction of the fourth connection part224and the extending direction of the fourth electrode strips222, so that the fourth connection part224is connected to the plurality of fourth electrode strips222with the same extending direction, to form a comb-shaped structure. That is, the fourth connection part224corresponds to a comb handle of the comb-shaped structure, and the plurality of fourth electrode strips222correspond to comb teeth of the comb-shaped structure.

In some embodiments, referring toFIGS.4and5,FIG.4is a cross-sectional view illustrating a structure taken along a section line cc′ inFIG.2Aand a line dd′ inFIG.3A; andFIG.5is a cross-sectional view illustrating a structure taken along a section line ee′ inFIG.2Aand a line ff′ inFIG.3A. Referring toFIGS.4and5, the gate60of the switching transistor6, the gate line3, the common electrode line5, and the lower electrode21are located on the base substrate1. The active layer62of the switching transistor6is located on a side of the gate60away from the base substrate1, and a gate insulating layer61is further arranged between the gate60and the active layer62. The source63and the drain64of the switching transistor6are located on a side of the active layer62away from the base substrate1, and are arranged at two opposite ends of the active layer62, respectively. The upper electrode22is located at a side of the source63and the drain64away from the base substrate1, and a passivation layer7is further arranged between the upper electrode22and the source63and the drain64. The gate insulating layer61and the passivation layer7also each extend between the lower electrode21and the upper electrode22. The first connection part213and the common electrode line5are formed integrally into a one-piece structure. The orthographic projection of the third connection part223on the base substrate1at least partially overlaps the orthographic projection of the common electrode line5on the base substrate1. The passivation layer7and the gate insulating layer61are provided with the first via8at a region where the orthographic projections of the third connection part223and the common electrode line5on the base substrate1overlap each other, and the third connection part223is connected to the common electrode line5through the first via8.

The gate60of the switching transistor6, the gate line3, the common electrode line5and the lower electrode21are located on the base substrate1, and the first connection part213and the common electrode line5are formed integrally into a one-piece structure. The gate60, the gate line3, the common electrode line5and the lower electrode21may be manufactured through one patterning process, so that the procedure of manufacturing the display substrate is simplified, and the manufacturing cost of the display substrate is reduced.

In some embodiments, referring toFIG.5, a part of the second connection part214extends such that an orthographic projection of the second connection part214on the base substrate1overlaps an orthographic projection of the drain64on the base substrate1. A part of the fourth connection part224extends such that an orthographic projection of the fourth connection part224on the base substrate1overlaps the orthographic projection of the drain64on the base substrate1. The passivation layer7and the gate insulating layer61are provided with a second via9at a region where orthographic projections of the second connection part214, the fourth connection part224and the drain64on the base substrate1overlap each other, and the fourth connection part224is connected to the drain64and the second connection part214through the second via9.

FIG.6is a top view illustrating a part of a structure of a display substrate according to an embodiment of the present disclosure; andFIG.7is a cross-sectional view illustrating a structure taken along a section line gg′ inFIG.6. In some embodiments, referring toFIGS.6and7, the third electrode strip221at an edge of the upper electrode22extend toward the drain64to form a first sub-portion200. The drain64extends toward the first sub-portion200to form a second sub-portion640. Orthographic projections of the first sub-portion200and the second sub-portion640on the base substrate1overlap each other, thereby forming a first compensation capacitor C1. The first compensation capacitor C1can compensate for the decreased storage capacitance (i.e., the storage capacitance in the pixel circuit originally formed by the opposite area between the slit-shaped upper electrode and the planar lower electrode) due to that the upper electrode22and the lower electrode21are both formed by the electrode strips, thereby ensuring the normal display of the respective sub-pixels2in the display substrate and ensuring the display effect thereof.

FIG.8is a cross-sectional view illustrating a structure taken along a section line gg′ inFIG.6. In some embodiments, referring toFIG.8, the first electrode strip211at the edge of the lower electrode21extend toward the drain64to form a third sub-portions201. Orthographic projections of the third sub-portion201and the second sub-portion640on the base substrate1overlap each other, thereby forming a second compensation capacitor C2. That is, the total compensation capacitor in the structure inFIG.8is a superposition of the first compensation capacitor C1and the second compensation capacitor C2. That is, a total compensation capacitance is the sum of capacitances of the first compensation capacitor C1and the second compensation capacitor C2, so that the decreased storage capacitance due to that the upper electrode22and the lower electrode21are both formed by the electrode strips can be further compensated, thereby further ensuring the normal display of the respective sub-pixels2in the display substrate and ensuring the display effect thereof.

In some embodiments, referring toFIG.6, the orthographic projection of the third electrode strip221at the edge of the upper electrode22on the base substrate1overlaps the orthographic projection of the data line4on the base substrate1. A width of the third electrode strip221at the edge of the upper electrodes22, which has an orthographic projection on the base substrate1overlapping the orthographic projection of the data line4on the base substrate1, is greater than a width of the third electrode strip221located in the pixel region. The third electrode strip221having a wider width may shield the data signal in the data line4, to prevent the data voltage signal in the data line4from interfering with the liquid crystal, so that a width of the black matrix on the data line4may be reduced.

In some embodiments, the third electrode strip221at the edge of the upper electrode22, which has the orthographic projection on the base substrate1overlapping the orthographic projection of the data line4on the base substrate1, is connected to the third connection parts223, and the third connection parts223of the sub-pixels2in the same row arranged along the first direction X are connected to each other, to form a straight line. The straight line formed by connecting the third connection parts223together overlaps the common electrode line5, and is connected to the common electrode line5through the first vias8formed in the passivation layer7and the gate insulating layer61.

It should be noted that, in the display substrate inFIGS.2A and3A, a third electrode strip221, which has the orthographic projection on the base substrate1overlapping the orthographic projection of the data line4on the base substrate1, may further be arranged at the edge of the upper electrode22, and the width of this third electrode strip221may be greater than or equal to the width of the third electrode strip221located in the pixel region. Similarly, the third electrode strip221with a wider width may shield the data signal in the data line4, to prevent the data voltage signal in the data line4from interfering with the liquid crystal, so that the width of the black matrix on the data line4may be reduced.

In some embodiments, based on the above structural arrangement of the display substrate, the orthographic projection of the first electrode strip at the edge of the lower electrode on the base substrate overlaps the orthographic projection of the data line on the base substrate. The width of the first electrode strip at the edge of the lower electrode, which has an orthographic projection on the base substrate overlapping the orthographic projection of the data line on the base substrate, is greater than the width of the first electrode strip located in the pixel region. The first electrode strip with a wider width may shield the data signal in the data line, to prevent the data voltage signal in the data line4from interfering with the liquid crystal, so that the width of the black matrix on the data line4may be reduced.

In some embodiments, referring toFIGS.2A and3A, the sub-pixel2is divided into two domains along the extending direction of the data line4. A domain boundary P (i.e., a boundary between the two domains) extends in the extending direction of the gate line3. The part of the data line4near the domain boundary P is bent in a direction approaching the domain boundary P. The parts of the first electrode strip211, the second electrode strip212, the third electrode strip221, and the fourth electrode strip222near the domain boundary lines P are each bent in the direction approaching the domain boundary line P, and the bent shapes thereof are each matched with the bent shape of the data lines4. The dual domain structure can improve viewing angle and eliminate color shift.

The parts of the data line4located on the upper and lower sides of the domain boundary P are bent in the direction approaching the domain boundary P, to form a small arrow. The parts of each of the first electrode strip211, the second electrode strip212, the third electrode strip221, and the fourth electrode strip222located on the upper and lower sides of the domain boundary P are also bent as approaching the domain boundary P, and the parts of the entire electrode strip located on the upper and lower sides of the domain boundary P are bent as approaching the domain boundary P to form a small arrow. The small arrow of the data line4and the small arrow of each electrode strip are bent towards the same direction, and both of them have a same or similar shape, and are located at positions corresponding to each other.

In the embodiment of the present disclosure, referring toFIG.9, which is a schematic diagram illustrating a difference between optical effects (i.e., a difference between transmittances) of the display substrate inFIG.2Ain positive and negative frames, as can be seen fromFIG.9, under the condition of the electric field generated by the electrodes inFIG.2A, the number of dark regions is reduced, the transmittance curves of the positive and negative frames only translate relative to each other, and the morphologies of the transmittance curves of the positive and negative frames are substantially the same. Referring toFIG.10, which is a simulated VT (i.e., voltage-transmittance) curve of the display substrate inFIG.2Awhen displaying, the simulation results are as follows: the difference proportion between the positive and negative frame transmittances is 99.3%; compared with the electrode design scheme of the ADS display mode in the prior art, the symmetry of the positive and negative frame transmittances of the display substrate inFIG.2Ais improved by 2%, and transmittance curves of the positive and negative frames are approximately coincident with each other. As can be seen from the VT curve inFIG.10, the VOP voltage (the data voltage corresponding to the point with the highest transmittance in the VT curve) of the display substrate inFIG.2Ais 4.5V. Compared with the electrode design scheme of the ADS display mode in the prior art, the VOP voltage is lower, and the power consumption is reduced.

Referring toFIG.11, which is a schematic diagram illustrating a difference between optical effects (i.e., a difference between transmittances) of the display substrate inFIG.3Ain positive and negative frames, as can be seen fromFIG.11, under the condition of the electric field generated by the electrodes inFIG.3A, distribution of the dark regions is weakened, the transmittance curves of the positive and negative frames also only translate relative to each other, and the morphologies of the transmittance curves of the positive and negative frames are substantially the same. Referring toFIG.12, which is a simulated VT (i.e., voltage-transmittance) curve of the display substrate inFIG.3Awhen displaying, the simulation results are as follows: the difference proportion between the positive and negative frame transmittances is 99.1%, compared with the electrode design scheme of the ADS display mode in the related art, the symmetry of the positive and negative frame transmittances is improved by 1.8%, and the positive and negative frame transmittance curves are approximately coincident with each other. As can be seen from the VT curve inFIG.12, the VOP voltage (the data voltage corresponding to the point with the highest transmittance in the VT curve) of the display substrate inFIG.3Ais 5.5V. Compared with the electrode design scheme of the ADS display mode in the prior art, the VOP voltage is also lower, and the purpose of reducing power consumption can be also achieved.

In summary, in the display substrate according to an embodiment of the present disclosure, the M number of sequentially adjacent first electrode strips211and the N number of sequentially adjacent second electrode strips212are alternately arranged; the M number of sequentially adjacent third electrode strips221and the N number of sequentially adjacent fourth electrode strips222are alternately arranged; and the orthographic projections of the electrode strips of the upper electrode22and the electrode strips of the lower electrode21on the base substrate1are alternately arranged, so that a uniform and symmetrical electric field may be formed between the upper electrode22and the lower electrode21, so as to improve the problem of nonuniform distribution of the electric field in the liquid crystal display substrate, thereby improving the problem of asymmetric VT (voltage-transmittance) curve of the display panel in ADS display mode in the prior art, and improving the display transmittance and even the display effect of the display substrate.

In some embodiments, referring toFIG.13, which is a cross-sectional view illustrating a part of a structure of an upper electrode and a lower electrode of a display substrate according to an embodiment of the present disclosure, M>N; and M−N≤2. For example, M=2, and N=1; alternatively, N=2, and M=4. The display substrate with such an electrode structure can also improve, to a certain extent, the problem of asymmetric VT (i.e., voltage-transmittance) curve of the display panel in the prior art.

Based on the above-described structure of the display substrate, in a second aspect, an embodiment of the present disclosure further provides a method of manufacturing the display substrate.FIG.14is a schematic diagram illustrating a procedure of manufacturing the display substrate inFIG.2A. Referring toFIG.14, the manufacturing method includes: forming a plurality of sub-pixels on a base substrate. Forming the sub-pixels includes: sequentially forming a lower electrode21and an upper electrode22on a base substrate. Forming the lower electrode21includes: forming a plurality of first electrode strips211and a plurality of second electrode strips212. Forming the upper electrode22includes: forming a plurality of third electrode strips221and a plurality of fourth electrode strips222.

In some embodiments, the plurality of first electrode strips211and the plurality of second electrode strips212are formed through one patterning process. The plurality of third electrode strips221and the plurality of fourth electrode strips222are formed through one patterning process.

In some embodiments, the process of manufacturing the display substrate is as follows: in step S1, the gate line3, the gate60of the switching transistor, the common electrode line5and the lower electrode21are formed on the base substrate.

The gate line3, the gate60of the switching transistor, the common electrode line5and the lower electrode21are simultaneously formed through one patterning process. The first electrode strip211in the lower electrode21is connected to the common electrode line5.

In step S2, a gate insulating layer, the first via8and the second via9in the gate insulating layer, the active layer62, and the data line4and the source63and the drain64, are sequentially formed on the base substrate after the step S1is completed.

The data line4, the source63, and the drain64are simultaneously formed through one patterning process. The drain64is connected to the second electrode strip212in the lower electrode21through the second via9formed in the gate insulating layer.

In step S3, a passivation layer, and the first via8and the second via9in the passivation layer are sequentially formed on the base substrate after the step S2is completed.

The first via8and the second via9are simultaneously formed in the passivation layer and the gate insulating layer through one patterning process.

In step S4, the upper electrode22is formed on the base substrate after the step S3is completed.

The third electrode strip221in the upper electrode22is connected to the common electrode lines5through the first via8. The fourth electrode strip222in the upper electrode22is connected to the drain64through the second via9.

The process of manufacturing the display substrate according to the embodiment of the present disclosure is simple, and the manufacturing cost is low.

In a third aspect, an embodiment of the present disclosure further provides a display apparatus, which includes the display substrate in the foregoing embodiment.

In some embodiments, the display apparatus further includes an opposite substrate, which is aligned with the display substrate to form a cell gap. The cell gap is filled with liquid crystal.

In some embodiments, the opposite substrate includes a color filter layer, which includes red, green, and blue color filters and a black matrix. The red, green and blue color filters are arranged in a one-to-one correspondence with different sub-pixels, and the black matrix is correspondingly distributed in a region outside the sub-pixels. The color filter layer can enable the display apparatus to realize color display.

By adopting the display substrate in the embodiment described above, a uniform and symmetrical electric field may be formed in the display apparatus, so as to improve the problem of nonuniform distribution of the electric field in the display apparatus, thereby improving the problem of asymmetric VT (voltage-transmittance) curve existing in the display apparatus in the prior art, and improving the display transmittance and even the display effect of the display apparatus.

The display apparatus may be any product or component with a display function, such as an LCD panel, an LCD television, a mobile phone, a tablet computer, a notebook computer, a monitor, a digital photo frame, a navigator, or the like.

It will be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure, and the present disclosure is not limited thereto. It will be apparent to one of ordinary skill in the art that various changes and modifications can be made without departing from the spirit and scope of the present disclosure, and these changes and modifications also fall within the protection scope of the present disclosure.