Provisioning a reference voltage based on an evaluation of a pseudo-precision resistor of an IC die

Techniques and mechanisms for determining a reference voltage which is to be provided with an integrated circuit (IC) die. In an embodiment, the IC die comprises a resistor, and a hardware interface which accommodates coupling of the IC die to a test unit. The test unit provides functionality to perform an evaluation of a resistance of the resistor, wherein said resistance is indicative of the respective resistances of one or more other resistors of the IC die. Based on the evaluation, the test unit provides to the IC die an indication of a scale factor, wherein the reference voltage is generated based on the scale factor. In another embodiment, the IC die further comprises an amplifier circuit which receives the reference voltage, wherein a variable resistance circuit of the IC die is configured based on an output of the amplifier circuit.

BACKGROUND

1. Technical Field

This disclosure generally relates to the field of integrated circuits and more particularly, but not exclusively, to tuning of integrated circuit input/output circuitry.

2. Background Art

Changes in input/output (I/O) timing parameters can severely impact I/O performance, particularly with respect to high performance or high frequency I/O design. Typically, I/O circuitry is designed for operation within strict timing guidelines. Failure to operate with the intended timing parameters may prevent such I/O circuitry from operating properly. Alternatively, failure to operate within these timing parameters may prevent I/O circuitry from interfacing properly with other circuitry that does adhere to the timing parameters.

Process variations introduced during the manufacture of I/O circuitry can cause variations that detract from optimal performance even if the I/O circuitry is still operating within intended timing parameters. In some instances, process variations prevent I/O circuitry from functioning or prevent the I/O circuitry from performing in accordance with the intended timing parameters. Lack of adequate compensation for individual I/O components can result in departure from optimal performance if, for example, the timing parameters change.

DETAILED DESCRIPTION

Embodiments discussed herein variously provide techniques and mechanisms for determining a level of a reference voltage which is to be provided with an integrated circuit (IC) die. Such determining is based on the resistance of one resistor of the IC die, wherein said resistance is the same as, or otherwise corresponds to, the respective resistances of one or more other resistors of the IC die.

It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. It is pointed out that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In addition, the various elements of combinatorial logic and sequential logic discussed in the present disclosure may pertain both to physical structures (such as AND gates, OR gates, or XOR gates), or to synthesized or otherwise optimized collections of devices implementing the logical structures that are Boolean equivalents of the logic under discussion.

The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including circuitry to facilitate the evaluation of a test resistor of an IC die.

FIG.1shows features of a system100to determine a reference voltage to be provided with an IC die according to an embodiment. System100illustrates one example of an embodiment which provides functionality to use a resistor of an IC die as a basis for estimating or otherwise determining the respective resistances of one or more other resistors of the same IC die.

As shown inFIG.1, system100comprises an IC die110, and a test unit150coupled thereto. IC die110comprises a hardware interface112by which IC die110is to couple to a hardware interface152of test unit150. For example, hardware interface152comprises conductive contacts—e.g., comprising metal bumps, pads, pins, balls, leads and/or other suitable conductors—which are to variously couple each to a respective conductive contact of hardware interface112. Other embodiments are variously implemented solely with some or all of IC die110, or are implemented solely with some or all of test unit150.

IC die110comprises any of various types of integrated circuitry which, for example, provides functionality of a general-purpose processor, a graphics processor, a memory, and/or the like. In some embodiments, IC die110is a system on chip (SoC). However, various embodiments are not limited with respect to any particular functionality which IC die110might be provide in addition to that described herein.

Test unit150provides functionality to evaluate one or more performance characteristics of IC die110. In some embodiments test unit150provides configuration information to IC die110based on such evaluating, which occurs (for example) prior to packaging of IC die110, prior to an assembly of a package which includes IC die110, and/or at any of various other stages of manufacture, distribution, or use.

In an embodiment, test unit150evaluates a “pseudo-precision resistor” (or “test resistor”) of IC die110, and—based on said evaluation—configures functionality which uses or is otherwise based on the respective resistances of one or more other resistors of IC die110. The terms “pseudo-precision resistor” and “test resistor” variously refer herein to a resistor of an IC die, wherein a resistance of said resistor is used as a reference for estimating or otherwise determining a resistance of another resistor of that same IC die. In using an on-die test resistor, some embodiments provide an alternative to various conventional techniques, which instead use external, off-die resistor (commonly referred to as a “precision resistor”) for reference during the testing of an IC die.

In the example embodiment shown, test unit150comprises a current supply circuit160, a voltage sensor170, evaluation circuitry180, and communication circuitry190which are variously coupled to hardware interface152. Furthermore, a resistor116of IC die110is coupled to hardware interface112—i.e., wherein respective conductive contacts114a,154aof hardware interfaces112,152couple current supply circuit160to resistor116, and wherein respective conductive contacts114b,154bof hardware interfaces112,152couple voltage sensor170to resistor116.

In various embodiments, a resistance of resistor116is indicative of a resistance of another resistor of IC die110(e.g., wherein said other resistor is provided by the illustrative one or more resistors144shown). In one such embodiment, resistor116and some or all of the one or more resistors144are each of a similar resistor type—e.g., wherein resistor116and one or more resistors144are each similar with respect to one or more materials, dimensions, and/or other design features. Although resistor116is originally designed to provide a particular resistance, resistor116is subject to deviating from that designed resistance due to process variations. However, some embodiments nevertheless avail of resistor116as a test register for evaluating the respective resistances of one or more other resistors of IC die110, based on a tendency of those one or more other resistors to be similarly affected by the same process variations

In one such embodiment, current supply circuit160is coupled to conduct a current i1 with resistor116via hardware interfaces112,152. Furthermore, voltage sensor170is coupled to measure a voltage (e.g., at conductive contact154bof hardware interface152), wherein the voltage is based on the current i1 and the resistance of resistor116. In the example embodiment shown, current supply circuit160conducts current i1 via conductive contact154a, and voltage sensor170measures a voltage at conductive contact154b—i.e., wherein IC die110electrically shorts conductive contacts154a,154btogether via conductive contacts114a,114b. In an alternative embodiment, voltage sensor170instead measures the voltage at the same conductive contact (for example, conductive contact154a) with which current supply circuit160conducts current i1—i.e., wherein resistor116is electrically coupled to only one conductive contact of hardware interface112, and wherein test unit150is able to provide an electrical short between current supply circuit160and voltage sensor170.

Evaluation circuitry180is coupled to receive from voltage sensor170a signal172which indicates the voltage across resistor116. Based on signal172, evaluation circuitry180performs an evaluation of the resistance of resistor116. For example, evaluation circuitry180is further coupled or otherwise preconfigured to identify an amount of the current i1 which current supply circuit160conducts with resistor116, wherein the actual resistance Ract of resistor116is evaluated by evaluation circuitry180according to equation (1) below.

R⁢a⁢c⁢t=vm⁢e⁢a⁢sI⁢i⁢n⁢j(1)
In equation (1) above, Vmeas is the voltage measured by voltage sensor170—e.g., at conductive contact154b—and Iinj is an amount of the current i1 which is conducted by resistor116.

Based on identifying of the resistance Ract of resistor116, evaluation circuitry180provides to communication circuitry190a signal182which specifies or otherwise indicates a scale factor which is to be used to configure IC die110. As described herein, such a scale factor is used (for example) as a basis for determining a reference voltage to be provided with IC die110. In one such embodiment, a scale factor (SF) is equal to, otherwise based on, a ratio of the actual resistance Ract of resistor116to an expected (designed) resistance Rex of resistor116—e.g., as represented by equation (2) below.

Given the equations (1) and (2) above, such a scale factor SF can be calculated as a ratio of first value to a second value, wherein the first value represents the measured voltage Vmeas, and wherein the second value represents a product of the amount Iinj of current i1, and the expected resistance Rex of resistor116. Such a ratio is represented in equation (3) below.

Based on signal182, communication circuitry190sends to communication circuitry120of IC die110a signal122which includes an indication of the scale factor SF. For example, in various embodiments, signal182specifies to communication circuitry190the measured resistance Ract—e.g., wherein resistance Ract is in turn identified to communication circuitry120via signal122. In one such embodiment, circuitry of IC die110—e.g., circuitry which is included in or coupled to communication circuitry120or a voltage generator130—then calculates the scale factor SF based on the resistance Ract. In some alternative embodiments, evaluation circuitry180instead calculates the scale factor SF, which is then specified to communication circuitry190in signal182, and similarly specified to communication circuitry120in signal122.

Voltage generator130is one example illustration of circuitry which is configurable to operate based on the scale factor which is indicated by signal122. By way of illustration and not limitation, voltage generator130generates a reference voltage142which (for example) is provided to an amplifier circuit140of IC die110. In one such embodiment, voltage generator130includes, is coupled to, or otherwise operates based on circuitry which is configurable to provide some configuration state (represented by the illustrative state information131shown) based on the scale factor indicated by signal122. For example, voltage generator130is programmable and/or otherwise configurable—e.g., based on a signal124from communication circuitry120—to provide reference voltage142at a level which is based on the scale factor (as indicated in state information131).

In various embodiments, reference voltage142is provided to one input terminal of amplifier circuit140, wherein another input terminal of amplifier circuit140is coupled to the one or more resistors144via a node146. For example, the one or more resistors144are coupled between node146and another node which is to receive a voltage v1 (e.g., a reference voltage, such as a ground potential, or a supply voltage). Amplifier circuit140provides an output148, a voltage level of which is based on reference voltage142and a voltage at node146. Although the one or more resistors144are shown as being coupled directly to node146and the other node, in some embodiments, the one or more resistors144is coupled to one such node via switch circuitry.

In one example embodiment, IC die110further comprises additional circuitry (not shown) which includes one or more variable resistance circuits and control circuitry coupled thereto. For each of the one or more variable resistance circuits, the control circuitry is to set a respective resistance of the variable resistance circuit—e.g., wherein such setting is based on the output148of amplifier circuit140. In one such embodiment, the one or more variable resistance circuits comprise a pull-up resistor circuit or a pull-down resistor circuit. Additionally or alternatively, the one or more variable resistance circuits comprise an on-die termination circuit. In an embodiment, the control circuitry sets a first resistance of a variable pull-down resistor circuit, and then sets a second resistance of a variable pull-up resistor circuit (e.g., wherein the second resistance is based on the setting of the first resistance). In another embodiment, an adaptive current bias circuit of IC die110comprises amplifier circuit140.

FIG.2shows features of a method200to configure an IC die based on an evaluation of a test resistor of an IC die according to an embodiment. Method200illustrates one example of an embodiment which determines an actual resistance of a pseudo-precision resistor, wherein an IC which includes the pseudo-precision resistor is provided with configuration information based on said resistance. Operations such as those of method200are performed, for example, with test unit150.

As shown inFIG.2, method200comprises (at210) coupling a test unit to an IC die—e.g., wherein the coupling at210comprises coupling test unit150and IC die110to each other via their respective hardware interface112,152. While the test unit is coupled to the IC die, method200(at212) conducts a current with a resistor of the IC die—e.g., wherein the conducting at212comprises conducting current i1 with resistor116. Within the IC die, the resistor is electrically decoupled from any active circuit element of the IC die.

Method200further comprises (at214) measuring a voltage at the hardware interface, wherein the voltage is based on the current and a resistance of the resistor. Based on the voltage measured at214, method200(at216) performs an evaluation of the resistance of the resistor. For example, the measuring at214is performed with voltage sensor170, wherein the evaluation performed at216is based on equation (1) above.

Method200further comprises (at218) providing to the IC die a signal (such as signal122) which comprises an indication of a scale factor, wherein the indication is determined based on the evaluation performed at216. In an embodiment, the IC die generates a reference voltage based on the indication of the scale factor. In one such embodiment, method200comprises calculating the scale factor based on the evaluation of the resistance—e.g., wherein providing the indication at218comprises communicating to the IC die a value which specifies the scale factor. In another embodiment, providing the indication at218comprises communicating to the IC die a first value which specifies the resistance of the resistor—e.g., wherein, based on the first value, the IC die subsequently calculates a second value which specifies the scale factor.

FIG.3shows features of a method300to identify a scaling factor which is to be applied by a voltage generator of an IC die according to an embodiment. Operations such as those of method300are performed, for example, with some or all of IC die110—e.g., wherein method300includes or is otherwise based on operations of method200.

As shown inFIG.3, method300comprises (at310) conducting a current with a resistor of the IC die and a test unit which is coupled to the test unit via a hardware interface. In an embodiment, the conducting at310includes or is otherwise based on the conducting at212. In an embodiment, the resistor corresponds functionally to resistor116—e.g., wherein, within the IC die, the resistor is electrically decoupled from any active circuit element of the IC die. Based on the current conducted at310, the test unit performs an evaluation of a resistance of the resistor, and (in some embodiments) calculates a scale factor based on the evaluated resistance.

Method300further comprises (at312) receiving from the test unit a signal which comprises an indication of a scale factor, wherein the indication is based on the evaluation of the resistance by the test unit. Based on the indication received at312, method300identifies the scale factor (at314). For example, in one such embodiment, the indication comprises a value which specifies the scale factor itself—e.g., wherein the test unit calculates the scale factor according to equation (3) above. In another embodiment, the indication comprises a value which specifies the resistance of the resistor, wherein, based on said value, method300calculates a second value which specifies the scale factor.

Method300further comprises (at316) generating a reference voltage based on the scale factor. In various embodiments, an amplifier circuit of the IC die (e.g., providing functionality of amplifier circuit140) is coupled to receive the reference voltage. In one such embodiment, the amplifier circuit is further coupled to one or more other resistors of the IC die—e.g., wherein the one or more other resistors which each have a respective resistance which is substantially equal to (for example, to within 10% of) the resistance of the resistor. The scale factor is indicative of the respective resistances of such one or more other resistors.

In various embodiments, the IC die further comprises one or more variable resistance circuits, wherein, for each of the one or more variable resistance circuits, a respective resistance of the variable resistance circuit is to be set based on an output of the amplifier circuit. For example, the one or more variable resistance circuits comprise a pull-up resistor circuit or a pull-down resistor circuit. Additionally or alternatively, the one or more variable resistance circuits comprise an on-die termination circuit.

In one such embodiment, method300further comprises one or more operations (not shown) which, based on the scale factor, set the respective resistances of one or more variable resistance circuits of the IC die. By way of illustration and not limitation, setting the respective resistances comprises setting a first resistance of a variable pull-down resistor circuit. Subsequently, a second resistance of a variable pull-up resistor circuit is set based on the setting of the first resistance of the variable pull-down resistor circuit.

FIG.4shows features of an IC die400which comprises input/output (I/O) circuitry which is tunable based on an evaluation of a test resistor according to an embodiment. IC die400illustrates one example of an embodiment wherein an IC die comprises a pseudo-precision resistor, and I/O circuitry which includes (or is otherwise coupled to operate with) one or more resistors which each have a respective resistance which is similar to, or otherwise indicated by, that of the pseudo-precision resistor. In various embodiments, IC die400provides functionality such as that of IC die110—e.g., wherein one or more operations of method300are performed with IC die400.

As shown inFIG.4, a hardware interface of IC die400comprises conductive contacts414a,414bwhich, for example, correspond functionally to conductive contacts114a,114b(respectively). IC die400further comprises a resistor416, a voltage generator430, and an amplifier circuit440which—for example—provide functionality of resistor116, voltage generator130, and amplifier circuit140(respectively).

In an embodiment, voltage generator430is configured with state information431based on a signal424which specifies or otherwise indicates a scale factor that is specified or otherwise indicated to IC die400by a test unit (such as test unit150). The scale factor is determined, for example, by an evaluation of resistor416by the test unit. Signal424and state information431correspond functionally to signal124and state information131(respectively), in various embodiments.

IC die400comprises one or more resistors444, some or all of which each have a respective resistance that is equal to, or is otherwise indicated by, the resistance of resistor416. In one such embodiment, a total resistance provided by one or more resistors444is less than a resistance of resistor416—e.g., wherein the one or more resistors444comprises multiple similar resistors which are coupled in parallel with each other. By way of illustration and not limitation, in one such embodiment, resistor416is designed to provide a resistance of 1500 Ohms (Ω), wherein the one or more resistors444are designed to provide a total resistance of 500Ω. In an embodiment, the scale factor indicated by signal424is equal to, or otherwise based on, a ratio of an actual resistance of resistor416to a designed (expected) resistance of resistor416. Voltage generator430provides to a negative input terminal of amplifier circuit440a reference voltage442, a level of which is based on the scale factor. A positive input terminal of amplifier circuit440is coupled to the various switch circuits and, for example, to another conductive contact414cwhich is to transmit signals from IC die400and/or to receive signals communicated to IC die400. Although conductive contact414cis shown as supporting transceiver functionality, other embodiments facilitate calibration processes for a conductive contact which supports only one of a transmit functionality, or a receive functionality.

In various embodiments, I/O circuitry of IC die400comprises one or more variable resistance circuits, wherein, for each of the one or more variable resistance circuits, a respective resistance of the variable resistance circuit is to be set based on an output448of amplifier circuit440. For example, the one or more variable resistance circuits comprise a pullup circuit460, and a pulldown circuit450. Additionally or alternatively, the one or more variable resistance circuits comprise an on-die termination (ODT) circuit470.

In one such embodiment, switch control signals401a,401boperate a first switch circuit of IC die400to selectively provide (or prevent) a conductive path between the one or more resistors444and a positive input terminal of amplifier circuit440. Furthermore, switch control signals402a,402boperate a second switch circuit of IC die400to selectively provide (or prevent) a conductive path between pulldown circuit450and the positive input terminal of amplifier circuit440. Further still, switch control signals403a,403boperate a third switch circuit of IC die400to selectively provide (or prevent) a conductive path between pullup circuit460and the positive input terminal of amplifier circuit440. Additionally or alternatively, switch control signals404a,404boperate a fourth switch circuit of IC die400to selectively provide (or prevent) a conductive path between ODT circuit470and the positive input terminal of amplifier circuit440. Some or all of switch control signals401a,401b,402a,402b,403a,403b,404a,404bare generated, for example, by the illustrative finite state machine (FSM)480shown, or by other suitable control circuitry of IC die400which, for example, operates in combination with FSM480.

In an illustrative scenario according to one embodiment, a pull down calibration procedure comprises providing conductive paths—the providing based on switch control signals401a,401band switch control signals402a,402b—each between amplifier circuit440and a respective one of pulldown circuit450or the one or more resistors444. Concurrently, based on switch control signals403a,403band switch control signals404a,404b, conductive paths are prevented between amplifier circuit440and both pullup circuit460and ODT circuit470. During such a configuration of the switch circuits, reference voltage442is provided at a level Vref1 which, for example, is represented by the equation (4) shown below.

In the above equation (4), SF is the scale factor, Rlex is an expected total resistance which the one or more resistors444were originally designed to provide, and Rdi is a predetermined ideal resistance to be provided by pulldown circuit450. During the pull down calibration, output448represents a difference between reference voltage442and a voltage at the positive input terminal of amplifier circuit440. FSM480provides a control signal482, based on output448, to change a variable resistance of pulldown circuit450until the voltage difference indicated by output448is zero (or otherwise sufficiently negligible).

In one such embodiment, a pull up calibration procedure comprises providing conductive paths—the providing based on switch control signals402a,402band switch control signals403a,403b—each between amplifier circuit440and a respective one of pulldown circuit450or pullup circuit460. Concurrently, based on switch control signals401a,401band switch control signals404a,404b, conductive paths are prevented between amplifier circuit440and each of ODT circuit470and the one or more resistors444. During such a state of the switch circuits, reference voltage442is provided at a level Vref2 which, for example, is represented by the equation (5) shown below.

In the above equation (5), Rui is a predetermined ideal resistance to be provided by pullup circuit460, and Rdcal is the resistance of pulldown circuit450which was previously configured, during the pull down calibration, based on control signal482. During the pull up calibration, FSM480provides a control signal484, based on output448, to change a variable resistance of pullup circuit460until a voltage difference indicated by output448is zero (or otherwise sufficiently negligible).

An ODT calibration according to some embodiments is performed in a way which is similar to the above-described pull down calibration process. For example, ODT calibration takes place while conductive paths are provided each between amplifier circuit440and a respective one of ODT circuit470or the one or more resistors444, and while other conductive paths—each between amplifier circuit440and a respective one of pulldown circuit450or pullup circuit460—are prevented. During such a state of the switch circuitry, reference voltage442is provided at a level Vref3 which, for example, is represented by the equation (6) shown below.

In the above equation (6), Roi is a predetermined ideal resistance to be provided by ODT circuit470. During the ODT calibration, FSM480provides a control signal486, based on output448, to change a variable resistance of ODT circuit470until the voltage difference indicated by output448is sufficiently negligible.

FIG.5shows features of an IC die500to adaptively tune a current bias based on an evaluation of a test resistor according to an embodiment. In various embodiments, IC die500provides functionality such as that of IC die110—e.g., wherein one or more operations of method300are performed with IC die500.

As shown inFIG.5, a hardware interface of IC die500comprises conductive contacts514a,514bwhich, for example, correspond functionally to conductive contacts114a,114b(respectively). IC die500further comprises a resistor516, a voltage generator530, and a differential amplifier540which—for example—provide functionality of resistor116, voltage generator130, and amplifier circuit140(respectively). In an embodiment, voltage generator530is configured with state information531based on a signal524which specifies or otherwise indicates a scale factor that is specified or otherwise indicated to IC die500by a test unit (such as test unit150). The scale factor is determined, for example, by an evaluation of resistor516(such as resistor116) by the test unit. Signal524and state information531correspond functionally to signal124and state information131(respectively), in various embodiments.

IC die500further comprises one or more resistors544, some or all of which each have a respective resistance that is equal to, or is otherwise indicated by, the resistance of resistor516. For example, the one or more resistors544correspond functionally to the one or more resistors144. In one such embodiment, a total resistance provided by one or more resistors544is less than a resistance of resistor516—e.g., wherein the one or more resistors544comprises multiple similar resistors which are coupled in parallel with each other.

The one or more resistors544are coupled, for example, to conduct current with an output stage501of IC die500, wherein the current is based on an output voltage548from differential amplifier540. In the example embodiment shown, output stage501comprises a first p-type output stage transistor, which is coupled to receive output voltage548, and a feedback network coupling the one or more resistors544to an input of the differential amplifier540. Although some embodiments are not limited in this regard, output stage501further comprises a second p-type transistor which coupled in series between the first p-type transistor and the one or more resistors544—e.g., where the second p-type transistor is always on during operation of IC die500.

Differential amplifier540generates voltage548based on a reference voltage542from differential amplifier540—e.g., wherein reference voltage542is based on the state information531(which, in turn, is based on the scale factor indicated by signal524). In an embodiment, voltage548is based on a difference between reference voltage542, and a feedback voltage feedback voltage546which is generated with the one or more resistors544and output stage501. Accordingly, feedback voltage546facilitates a regulation of output voltage548, which in turn regulates the respective biases of one or more currents which are provided each to a respective load circuit.

By way of illustration and not limitation, output voltage548further determines a conduction of a current with an output stage502and a load510which is coupled thereto. Additionally or alternatively, output voltage548determines the conduction of another current with an output stage503and an additional load520which is coupled thereto. In other embodiments, one or more load circuits (e.g., load510and/or load520) are provided with current by IC die500, but are external to IC die500. Furthermore, it is to be appreciated that the number of output stages and load circuits shown inFIG.5is merely illustrative, and not limiting on certain embodiments.

FIG.6shows features of a variable resistance circuit600to be tuned based on an evaluation of a test resistor of an IC die according to an embodiment. Variable resistance circuit600illustrates circuitry which is to be configured based on a scale factor, wherein the scale factor is determined based on the evaluation of a test resistor of an IC die. In various embodiments, variable resistance circuit600provides functionality such as that of pulldown circuit450, pullup circuit460, or ODT circuit470—e.g., wherein one or more operations of method300are performed with variable resistance circuit600.

As shown inFIG.6, variable resistor600comprises n circuit networks (where n is a positive integer) which are coupled in parallel with each other between two nodes601,602. For example, a first circuit network of variable resistance circuit600comprises resistors R10, R12, wherein, responsive to control signals612a,612b, a switch circuit610is to selectively enable (or disable) any current conduction with the first circuit network. Responsive to control signals622a,622b, another switch circuit620is to selectively enable (or disable) a bypassing of resistor R12.

Furthermore, a second circuit network of variable resistance circuit600comprises resistors R20, R22, wherein, responsive to control signals632a,632b, a switch circuit630is to selectively enable (or disable) any current conduction with the second circuit network. Responsive to control signals642a,642b, another switch circuit640is to selectively enable (or disable) a bypassing of resistor R22. Further still, a third circuit network of variable resistance circuit600comprises resistors Rn0, Rn2, wherein, responsive to control signals652a,652b, a switch circuit650is to selectively enable (or disable) any current conduction with the third circuit network. Responsive to control signals662a,662b, another switch circuit660is to selectively enable (or disable) a bypassing of resistor Rn2.

FIG.7illustrates a computer system or computing device700(also referred to as device700), where a resistance of an IC die is tuned, in accordance with some embodiments. It is pointed out that those elements ofFIG.7having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In some embodiments, device700represents an appropriate computing device, such as a computing tablet, a mobile phone or smart-phone, a laptop, a desktop, an Internet-of-Things (IoT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, or the like. It will be understood that certain components are shown generally, and not all components of such a device are shown in device700.

In an example, the device700comprises a SoC (System-on-Chip)701. An example boundary of the SOC701is illustrated using dotted lines inFIG.7, with some example components being illustrated to be included within SOC701—however, SOC701may include any appropriate components of device700.

In some embodiments, device700includes processor704. Processor704can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, processing cores, or other processing means. The processing operations performed by processor704include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, operations related to connecting computing device700to another device, and/or the like. The processing operations may also include operations related to audio I/O and/or display I/O.

In some embodiments, processor704includes multiple processing cores (also referred to as cores)708a,708b,708c. Although merely three cores708a,708b,708care illustrated inFIG.7, the processor704may include any other appropriate number of processing cores, e.g., tens, or even hundreds of processing cores. Processor cores708a,708b,708cmay be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and/or private caches, buses or interconnections, graphics and/or memory controllers, or other components.

In some embodiments, processor704includes cache706. In an example, sections of cache706may be dedicated to individual cores708(e.g., a first section of cache706dedicated to core708a, a second section of cache706dedicated to core708b, and so on). In an example, one or more sections of cache706may be shared among two or more of cores708. Cache706may be split in different levels, e.g., level 1 (L1) cache, level 2 (L2) cache, level 3 (L3) cache, etc.

In some embodiments, a given processor core (e.g., core708a) may include a fetch unit to fetch instructions (including instructions with conditional branches) for execution by the core708a. The instructions may be fetched from any storage devices such as the memory730. Processor core708amay also include a decode unit to decode the fetched instruction. For example, the decode unit may decode the fetched instruction into a plurality of micro-operations. Processor core708amay include a schedule unit to perform various operations associated with storing decoded instructions. For example, the schedule unit may hold data from the decode unit until the instructions are ready for dispatch, e.g., until all source values of a decoded instruction become available. In one embodiment, the schedule unit may schedule and/or issue (or dispatch) decoded instructions to an execution unit for execution.

The execution unit may execute the dispatched instructions after they are decoded (e.g., by the decode unit) and dispatched (e.g., by the schedule unit). In an embodiment, the execution unit may include more than one execution unit (such as an imaging computational unit, a graphics computational unit, a general-purpose computational unit, etc.). The execution unit may also perform various arithmetic operations such as addition, subtraction, multiplication, and/or division, and may include one or more an arithmetic logic units (ALUs). In an embodiment, a co-processor (not shown) may perform various arithmetic operations in conjunction with the execution unit.

Further, an execution unit may execute instructions out-of-order. Hence, processor core708a(for example) may be an out-of-order processor core in one embodiment. Processor core708amay also include a retirement unit. The retirement unit may retire executed instructions after they are committed. In an embodiment, retirement of the executed instructions may result in processor state being committed from the execution of the instructions, physical registers used by the instructions being de-allocated, etc. The processor core708amay also include a bus unit to enable communication between components of the processor core708aand other components via one or more buses. Processor core708amay also include one or more registers to store data accessed by various components of the core708a(such as values related to assigned app priorities and/or sub-system states (modes) association.

In some embodiments, device700comprises connectivity circuitries731. For example, connectivity circuitries731includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and/or software components (e.g., drivers, protocol stacks), e.g., to enable device700to communicate with external devices. Device700may be separate from the external devices, such as other computing devices, wireless access points or base stations, etc.

In an example, connectivity circuitries731may include multiple different types of connectivity. To generalize, the connectivity circuitries731may include cellular connectivity circuitries, wireless connectivity circuitries, etc. Cellular connectivity circuitries of connectivity circuitries731refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications Systems (UMTS) system or variations or derivatives, 3GPP Long-Term Evolution (LTE) system or variations or derivatives, 3GPP LTE-Advanced (LTE-A) system or variations or derivatives, Fifth Generation (5G) wireless system or variations or derivatives, 5G mobile networks system or variations or derivatives, 5G New Radio (NR) system or variations or derivatives, or other cellular service standards. Wireless connectivity circuitries (or wireless interface) of the connectivity circuitries731refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), and/or other wireless communication. In an example, connectivity circuitries731may include a network interface, such as a wired or wireless interface, e.g., so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

In some embodiments, device700comprises control hub732, which represents hardware devices and/or software components related to interaction with one or more I/O devices. For example, processor704may communicate with one or more of display722, one or more peripheral devices724, storage devices728, one or more other external devices729, etc., via control hub732. Control hub732may be a chipset, a Platform Control Hub (PCH), and/or the like.

For example, control hub732illustrates one or more connection points for additional devices that connect to device700, e.g., through which a user might interact with the system. For example, devices (e.g., devices729) that can be attached to device700include microphone devices, speaker or stereo systems, audio devices, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, control hub732can interact with audio devices, display722, etc. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of device700. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display722includes a touch screen, display722also acts as an input device, which can be at least partially managed by control hub732. There can also be additional buttons or switches on computing device700to provide I/O functions managed by control hub732. In one embodiment, control hub732manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in device700. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

In some embodiments, control hub732may couple to various devices using any appropriate communication protocol, e.g., PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High Definition Multimedia Interface (HDMI), Firewire, etc.

In some embodiments, display722represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with device700. Display722may include a display interface, a display screen, and/or hardware device used to provide a display to a user. In some embodiments, display722includes a touch screen (or touch pad) device that provides both output and input to a user. In an example, display722may communicate directly with the processor704. Display722can be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment display722can be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

In some embodiments and although not illustrated in the figure, in addition to (or instead of) processor704, device700may include Graphics Processing Unit (GPU) comprising one or more graphics processing cores, which may control one or more aspects of displaying contents on display722.

Control hub732(or platform controller hub) may include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections, e.g., to peripheral devices724.

It will be understood that device700could both be a peripheral device to other computing devices, as well as have peripheral devices connected to it. Device700may have a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on device700. Additionally, a docking connector can allow device700to connect to certain peripherals that allow computing device700to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, device700can make peripheral connections via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

In some embodiments, connectivity circuitries731may be coupled to control hub732, e.g., in addition to, or instead of, being coupled directly to the processor704. In some embodiments, display722may be coupled to control hub732, e.g., in addition to, or instead of, being coupled directly to processor704.

In some embodiments, device700comprises memory730coupled to processor704via memory interface734. Memory730includes memory devices for storing information in device700. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory device730can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment, memory730can operate as system memory for device700, to store data and instructions for use when the one or more processors704executes an application or process. Memory730can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of device700.

In some embodiments, device700comprises temperature measurement circuitries740, e.g., for measuring temperature of various components of device700. In an example, temperature measurement circuitries740may be embedded, or coupled or attached to various components, whose temperature are to be measured and monitored. For example, temperature measurement circuitries740may measure temperature of (or within) one or more of cores708a,708b,708c, voltage regulator714, memory730, a mother-board of SOC701, and/or any appropriate component of device700.

In some embodiments, device700comprises power measurement circuitries742, e.g., for measuring power consumed by one or more components of the device700. In an example, in addition to, or instead of, measuring power, the power measurement circuitries742may measure voltage and/or current. In an example, the power measurement circuitries742may be embedded, or coupled or attached to various components, whose power, voltage, and/or current consumption are to be measured and monitored. For example, power measurement circuitries742may measure power, current and/or voltage supplied by one or more voltage regulators714, power supplied to SOC701, power supplied to device700, power consumed by processor704(or any other component) of device700, etc.

In some embodiments, device700comprises one or more voltage regulator circuitries, generally referred to as voltage regulator (VR)714. VR714generates signals at appropriate voltage levels, which may be supplied to operate any appropriate components of the device700. Merely as an example, VR714is illustrated to be supplying signals to processor704of device700. In some embodiments, VR714receives one or more Voltage Identification (VID) signals, and generates the voltage signal at an appropriate level, based on the VID signals. Various type of VRs may be utilized for the VR714. For example, VR714may include a “buck” VR, “boost” VR, a combination of buck and boost VRs, low dropout (LDO) regulators, switching DC-DC regulators, etc. Buck VR is generally used in power delivery applications in which an input voltage needs to be transformed to an output voltage in a ratio that is smaller than unity. Boost VR is generally used in power delivery applications in which an input voltage needs to be transformed to an output voltage in a ratio that is larger than unity. In some embodiments, each processor core has its own VR which is controlled by PCU710a/b and/or PMIC712. In some embodiments, each core has a network of distributed LDOs to provide efficient control for power management. The LDOs can be digital, analog, or a combination of digital or analog LDOs.

In some embodiments, device700comprises one or more clock generator circuitries, generally referred to as clock generator716. Clock generator716generates clock signals at appropriate frequency levels, which may be supplied to any appropriate components of device700. Merely as an example, clock generator716is illustrated to be supplying clock signals to processor704of device700. In some embodiments, clock generator716receives one or more Frequency Identification (FID) signals, and generates the clock signals at an appropriate frequency, based on the FID signals.

In some embodiments, device700comprises battery718supplying power to various components of device700. Merely as an example, battery718is illustrated to be supplying power to processor704. Although not illustrated in the figures, device700may comprise a charging circuitry, e.g., to recharge the battery, based on Alternating Current (AC) power supply received from an AC adapter.

In some embodiments, device700comprises Power Control Unit (PCU)710(also referred to as Power Management Unit (PMU), Power Controller, etc.). In an example, some sections of PCU710may be implemented by one or more processing cores708, and these sections of PCU710are symbolically illustrated using a dotted box and labelled PCU710a. In an example, some other sections of PCU710may be implemented outside the processing cores708, and these sections of PCU710are symbolically illustrated using a dotted box and labelled as PCU710b. PCU710may implement various power management operations for device700. PCU710may include hardware interfaces, hardware circuitries, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), to implement various power management operations for device700.

In some embodiments, device700comprises Power Management Integrated Circuit (PMIC)712, e.g., to implement various power management operations for device700. In some embodiments, PMIC712is a Reconfigurable Power Management ICs (RPMICs) and/or an IMVP (Intel® Mobile Voltage Positioning). In an example, the PMIC is within an IC chip separate from processor704. The may implement various power management operations for device700. PMIC712may include hardware interfaces, hardware circuitries, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), to implement various power management operations for device700.

In an example, device700comprises one or both PCU710or PMIC712. In an example, any one of PCU710or PMIC712may be absent in device700, and hence, these components are illustrated using dotted lines.

Various power management operations of device700may be performed by PCU710, by PMIC712, or by a combination of PCU710and PMIC712. For example, PCU710and/or PMIC712may select a power state (e.g., P-state) for various components of device700. For example, PCU710and/or PMIC712may select a power state (e.g., in accordance with the ACPI (Advanced Configuration and Power Interface) specification) for various components of device700. Merely as an example, PCU710and/or PMIC712may cause various components of the device700to transition to a sleep state, to an active state, to an appropriate C state (e.g., CO state, or another appropriate C state, in accordance with the ACPI specification), etc. In an example, PCU710and/or PMIC712may control a voltage output by VR714and/or a frequency of a clock signal output by the clock generator, e.g., by outputting the VID signal and/or the FID signal, respectively. In an example, PCU710and/or PMIC712may control battery power usage, charging of battery718, and features related to power saving operation.

The clock generator716can comprise a phase locked loop (PLL), frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of processor704has its own clock source. As such, each core can operate at a frequency independent of the frequency of operation of the other core. In some embodiments, PCU710and/or PMIC712performs adaptive or dynamic frequency scaling or adjustment. For example, clock frequency of a processor core can be increased if the core is not operating at its maximum power consumption threshold or limit. In some embodiments, PCU710and/or PMIC712determines the operating condition of each core of a processor, and opportunistically adjusts frequency and/or power supply voltage of that core without the core clocking source (e.g., PLL of that core) losing lock when the PCU710and/or PMIC712determines that the core is operating below a target performance level. For example, if a core is drawing current from a power supply rail less than a total current allocated for that core or processor704, then PCU710and/or PMIC712can temporarily increase the power draw for that core or processor704(e.g., by increasing clock frequency and/or power supply voltage level) so that the core or processor704can perform at a higher performance level. As such, voltage and/or frequency can be increased temporality for processor704without violating product reliability.

In an example, PCU710and/or PMIC712may perform power management operations, e.g., based at least in part on receiving measurements from power measurement circuitries742, temperature measurement circuitries740, charge level of battery718, and/or any other appropriate information that may be used for power management. To that end, PMIC712is communicatively coupled to one or more sensors to sense/detect various values/variations in one or more factors having an effect on power/thermal behavior of the system/platform. Examples of the one or more factors include electrical current, voltage droop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be provided in physical proximity (and/or thermal contact/coupling) with one or more components or logic/IP blocks of a computing system. Additionally, sensor(s) may be directly coupled to PCU710and/or PMIC712in at least one embodiment to allow PCU710and/or PMIC712to manage processor core energy at least in part based on value(s) detected by one or more of the sensors.

Also illustrated is an example software stack of device700(although not all elements of the software stack are illustrated). Merely as an example, processors704may execute application programs750, Operating System752, one or more Power Management (PM) specific application programs (e.g., generically referred to as PM applications758), and/or the like. PM applications758may also be executed by the PCU710and/or PMIC712. OS752may also include one or more PM applications756a,756b,756c. The OS752may also include various drivers754a,754b,754c, etc., some of which may be specific for power management purposes. In some embodiments, device700may further comprise a Basic Input/Output System (BIOS)720. BIOS720may communicate with OS752(e.g., via one or more drivers754), communicate with processors704, etc.

For example, one or more of PM applications758,756, drivers754, BIOS720, etc. may be used to implement power management specific tasks, e.g., to control voltage and/or frequency of various components of device700, to control wake-up state, sleep state, and/or any other appropriate power state of various components of device700, control battery power usage, charging of the battery718, features related to power saving operation, etc.

In various embodiments, connectivity circuitries731comprise I/O circuitry with which SoC701is to communicate with other hardware (such as hardware which computing device701includes or, alternatively, is to couple to). Such I/O circuitry connectivity circuitries731incudes a variable resistance circuit (not shown) that, for example, provide functionality such as that of one or more resistors144. In one such embodiment, SoC701comprises a test resistor (not shown) that, for example, provides functionality such as that of resistor116. The I/O circuitry of connectivity circuitries731incudes, is coupled to, or otherwise operates based on circuit logic which provides functionality (such as that of communication circuitry120and/or voltage generator130) to tune or otherwise configure the variable resistance circuit—e.g., based on an evaluation of a resistance provided by the test resistor.

In one or more first embodiments, an integrated circuit (IC) die comprises a hardware interface to couple the IC die to a test unit, a resistor coupled to the hardware interface, the resistor to conduct a current with the test unit when the hardware interface is coupled to the test unit, wherein, based on the current, the test unit is to perform an evaluation of a resistance of the resistor, first circuitry to receive a signal from the test unit via the hardware interface, wherein the signal is to comprise an indication of a scale factor, wherein the indication is based on the evaluation, and second circuitry to identify the scale factor based on the indication, and to generate a reference voltage based on the scale factor.

In one or more second embodiments, further to the first embodiment, within the IC die, the resistor is electrically decoupled from any active circuit element of the IC die.

In one or more third embodiments, further to the first embodiment or the second embodiment, the indication is to comprise a value which specifies the scale factor.

In one or more fourth embodiments, further to any of the first through third embodiments, providing the indication comprises communicating to the IC die a first value which specifies the resistance of the resistor, and wherein, based on the first value, the IC die calculates a second value which specifies the scale factor.

In one or more fifth embodiments, further to the fourth embodiment, the scale factor is calculated based on a ratio of a first value to a second value, wherein the first value represents a first voltage measured at the hardware interface, and the second value represents a product of an amount of the current, and an expected resistance of the resistor.

In one or more sixth embodiments, further to any of the first through third embodiments, the IC die further comprises an amplifier circuit which is coupled to receive the reference voltage.

In one or more seventh embodiments, further to the sixth embodiment, the IC die further comprises one or more other resistors which are coupled to the amplifier circuit, wherein the one or more other resistors each have a respective resistance which is substantially equal to the resistance of the resistor.

In one or more eighth embodiments, further to the sixth embodiment, the IC die further comprises fourth circuitry and one or more variable resistance circuits, wherein, for each of the one or more variable resistance circuits, the fourth circuitry is to set a respective resistance of the variable resistance circuit based on an output of the amplifier circuit.

In one or more ninth embodiments, further to the eighth embodiment, the one or more variable resistance circuits comprise a pull-up circuit or a pull-down circuit.

In one or more tenth embodiments, further to the eighth embodiment, the one or more variable resistance circuits comprise an on-die termination circuit.

In one or more eleventh embodiments, further to the eighth embodiment, based on the scale factor, the fourth circuitry is to set respective resistances of each of the one or more variable resistance circuits, wherein the fourth circuitry is to set a first resistance of a variable pull-down circuit, and set a second resistance of a variable pull-up circuit, wherein the second resistance is based on the first resistance.

In one or more twelfth embodiments, further to the sixth embodiment, an adaptive current bias circuit of the IC die comprises the amplifier circuit.

In one or more thirteenth embodiments, a test unit comprises a hardware interface to couple the test unit to an integrated circuit (IC) die, first circuitry to conduct a current with a resistor of the IC die via the hardware interface, and second circuitry to measure a voltage at the hardware interface, wherein the voltage is based on the current and a resistance of the resistor, third circuitry to perform an evaluation of the resistance based on the voltage, and fourth circuitry to provide to the IC die a signal which comprises an indication of a scale factor, wherein the indication is based on the evaluation, wherein the IC die is to generate a reference voltage based on the indication of the scale factor.

In one or more fourteenth embodiments, further to the thirteenth embodiment, within the IC die, the resistor is electrically decoupled from any active circuit element of the IC die.

In one or more fifteenth embodiments, further to the thirteenth embodiment or the fourteenth embodiment, the third circuitry is to calculate the scale factor based on the evaluation, wherein the fourth circuitry to provide the indication comprises the fourth circuitry to communicate to the IC die a value which specifies the scale factor.

In one or more sixteenth embodiments, further to the fifteenth embodiment, the third circuitry is to calculate the scale factor based on a ratio of a first value to a second value, wherein the first value represents a first voltage measured at the hardware interface, and the second value represents a product of an amount of the current, and an expected resistance of the resistor.

In one or more seventeenth embodiments, further to any of the thirteenth through fifteenth embodiments, the fourth circuitry to provide the indication comprises the fourth circuitry to communicate to the IC die a first value which specifies the resistance of the resistor, and wherein, based on the first value, the IC die is to calculate a second value which specifies the scale factor.

In one or more eighteenth embodiments, a system comprises an integrated circuit (IC) die comprising a hardware interface to couple the IC die to a test unit, a resistor coupled to the hardware interface, the resistor to conduct a current with the test unit when the hardware interface is coupled to the test unit, wherein, based on the current, the test unit is to perform an evaluation of a resistance of the resistor, first circuitry to receive a signal from the test unit via the hardware interface, wherein the signal is to comprise an indication of a scale factor, wherein the indication is based on the evaluation, and second circuitry to identify the scale factor based on the indication, and to generate a reference voltage based on the scale factor, and a display device coupled to the IC die, the display device to display an image based on the reference voltage.

In one or more nineteenth embodiments, further to the eighteenth embodiment, within the IC die, the resistor is electrically decoupled from any active circuit element of the IC die.

In one or more twentieth embodiments, further to the eighteenth embodiment or the nineteenth embodiment, the indication is to comprise a value which specifies the scale factor.

In one or more twenty-first embodiments, further to any of the eighteenth through twentieth embodiments, providing the indication comprises communicating to the IC die a first value which specifies the resistance of the resistor, and wherein, based on the first value, the IC die calculates a second value which specifies the scale factor.

In one or more twenty-second embodiments, further to the twenty-first embodiment, the scale factor is calculated based on a ratio of a first value to a second value, wherein the first value represents a first voltage measured at the hardware interface, and the second value represents a product of an amount of the current, and an expected resistance of the resistor.

In one or more twenty-third embodiments, further to any of the eighteenth through twentieth embodiments, the IC die further comprises an amplifier circuit which is coupled to receive the reference voltage.

In one or more twenty-fourth embodiments, further to the twenty-third embodiment, the IC die further comprises one or more other resistors which are coupled to the amplifier circuit, wherein the one or more other resistors each have a respective resistance which is substantially equal to the resistance of the resistor.

In one or more twenty-fifth embodiments, further to the twenty-third embodiment, the IC die further comprises fourth circuitry and one or more variable resistance circuits, wherein, for each of the one or more variable resistance circuits, the fourth circuitry is to set a respective resistance of the variable resistance circuit based on an output of the amplifier circuit.

In one or more twenty-sixth embodiments, further to the twenty-fifth embodiment, the one or more variable resistance circuits comprise a pull-up circuit or a pull-down circuit.

In one or more twenty-seventh embodiments, further to the twenty-fifth embodiment, the one or more variable resistance circuits comprise an on-die termination circuit.

In one or more twenty-eighth embodiments, further to the twenty-fifth embodiment, based on the scale factor, the fourth circuitry is to set respective resistances of each of the one or more variable resistance circuits, wherein the fourth circuitry is to set a first resistance of a variable pull-down circuit, and set a second resistance of a variable pull-up circuit, wherein the second resistance is based on the first resistance.

In one or more twenty-ninth embodiments, further to the twenty-third embodiment, an adaptive current bias circuit of the IC die comprises the amplifier circuit.

In one or more thirtieth embodiments, a method comprises conducting a current with a test unit and a resistor of an integrated circuit (IC) die which is coupled to the test unit via a hardware interface, and with the test unit measuring a voltage at the hardware interface, wherein the voltage is based on the current and a resistance of the resistor, based on the voltage, performing an evaluation of the resistance of the resistor, and providing to the IC die a signal which comprises an indication of a scale factor, wherein the indication is based on the evaluation, wherein the IC die generates a reference voltage based on the indication of the scale factor.

In one or more thirty-first embodiments, further to the thirtieth embodiment, within the IC die, the resistor is electrically decoupled from any active circuit element of the IC die.

In one or more thirty-second embodiments, further to the thirtieth embodiment or the thirty-first embodiment, the method further comprises calculating the scale factor at the test unit based on the evaluation, wherein providing the indication comprises communicating to the IC die a value which specifies the scale factor.

In one or more thirty-third embodiments, further to the thirty-second embodiment, the scale factor is calculated based on a ratio of a first value to a second value, wherein the first value represents a first voltage measured at the hardware interface, and the second value represents a product of an amount of the current, and an expected resistance of the resistor.

In one or more thirty-fourth embodiments, further to any of the thirtieth through thirty-second embodiments, providing the indication comprises communicating to the IC die a first value which specifies the resistance of the resistor, and wherein, based on the first value, the IC die calculates a second value which specifies the scale factor.

In one or more thirty-fifth embodiments, a method comprises conducting a current with a resistor of an IC die and a test unit which is coupled to the test unit via a hardware interface, wherein, based on the current, the test unit performs an evaluation of a resistance of the resistor, and calculates a scale factor based on the evaluation, receiving from the test unit a signal which comprises an indication of a scale factor, wherein the indication is based on the evaluation, identifying the scale factor based on the indication, and generating a reference voltage based on the scale factor.

In one or more thirty-sixth embodiments, further to the thirty-fifth embodiment, within the IC die, the resistor is electrically decoupled from any active circuit element of the IC die.

In one or more thirty-seventh embodiments, further to the thirty-fifth embodiment or the thirty-sixth embodiment, the indication comprises a value which specifies the scale factor.

In one or more thirty-eighth embodiments, further to any of the thirty-fifth through thirty-seventh embodiments, providing the indication comprises communicating to the IC die a first value which specifies the resistance of the resistor, and wherein, based on the first value, the IC die calculates a second value which specifies the scale factor.

In one or more thirty-ninth embodiments, further to the thirty-eighth embodiment, the scale factor is calculated based on a ratio of a first value to a second value, wherein the first value represents a first voltage measured at the hardware interface, and the second value represents a product of an amount of the current, and an expected resistance of the resistor.

In one or more fortieth embodiments, further to any of the thirty-fifth through thirty-seventh embodiments, an amplifier circuit of the IC die is coupled to receive the reference voltage.

In one or more forty-first embodiments, further to the fortieth embodiment, the amplifier circuit is further coupled to one or more other resistors of the IC die, wherein the one or more other resistors which each have a respective resistance which is substantially equal to the resistance of the resistor.

In one or more forty-second embodiments, further to the fortieth embodiment, the IC die further comprises one or more variable resistance circuits, and wherein, for each of the one or more variable resistance circuits, a respective resistance of the variable resistance circuit is to be set based on an output of the amplifier circuit.

In one or more forty-third embodiments, further to the forty-second embodiment, the one or more variable resistance circuits comprise a pull-up circuit or a pull-down circuit.

In one or more forty-fourth embodiments, further to the forty-second embodiment, the one or more variable resistance circuits comprise an on-die termination circuit.

In one or more forty-fifth embodiments, further to the forty-second embodiment, the method further comprises based on the scale factor, setting respective resistances of each of one or more variable resistance circuits of the IC die, wherein setting the respective resistances comprises setting a first resistance of a variable pull-down circuit, and setting a second resistance of a variable pull-up circuit, wherein the second resistance is based on the first resistance.

In one or more forty-sixth embodiments, further to the fortieth embodiment, an adaptive current bias circuit of the IC die comprises the amplifier circuit.