Method of manufacturing semiconductor element

A method of manufacturing a semiconductor element includes: a first providing step comprising providing a structure body comprising a semiconductor stacked body, the structure body including first surfaces that include surfaces defining at least one first recess; a first forming step comprising forming a first rough-surface portion at or inward of at least a portion of the surfaces defining the first recess of the structure body; a second forming step comprising forming a first metal layer at a first surface side of the structure body; a second providing step comprising providing a substrate on which a second metal layer is disposed; and a bonding step comprising heating the first metal layer and the second metal layer in a state in which the first metal layer and the second metal layer face each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims priority to Japanese Patent Application No. 2018-176121, filed on Sep. 20, 2018; the entire contents of which are incorporated herein by reference.

FIELD

The present disclosure relates to a method of manufacturing a semiconductor element.

BACKGROUND

Japanese Patent Publication No. 2016-174018 describes a method of manufacturing a semiconductor element including a step of bonding two members. In the step of bonding in Japanese Patent Publication No. 2016-174018, for example, a member having a surface with a recess is bonded to another member.

SUMMARY

A technique that allows for simplifying manufacturing steps and reducing manufacturing cost in a method of manufacturing a semiconductor element including such a bonding step would be desirable.

According to one embodiment of the present invention, a method of manufacturing a semiconductor element includes a first providing step including providing a structure body, the structure body including a semiconductor stacked body and including first surfaces that include surfaces defining at least one first recess; a first forming step including forming a first rough-surface portion at or inward of at least a portion of the surfaces defining the first recess of the structure body, the first rough-surface portion being rougher than another portion of the first surfaces; a second forming step including forming a first metal layer at a first surface side of the structure body; a second providing step including providing a substrate on which a second metal layer is disposed; and a bonding step including heating the first metal layer and the second metal layer in a state in which the first metal layer and the second metal layer face each other such that the first metal layer and the second metal layer are melted and bonded together and the melted first metal layer flows into the first recess.

The present disclosure allows for providing a method of manufacturing a semiconductor device in which steps can be simplified and manufacturing cost can be reduced.

DETAILED DESCRIPTION

Certain embodiments will be described with reference to the drawings. The same components in the drawings are designated with the same reference numerals.

FIG. 1AtoFIG. 1Hare schematic cross-sectional views illustrating steps in a method of manufacturing a semiconductor element according to one embodiment of the invention.

A structure body10shown inFIG. 1Ais provided (a first providing step). The structure body10is disposed on a substrate1, and includes a semiconductor stacked body11, a stacked body12, and an electrode film13. The structure body10includes surfaces10S (i.e., first surfaces) that include surfaces defining a recess r1(i.e., a first recess) and a recess r2(i.e., a second recess). The recess r1has a depth greater than a depth of the recess r2, extends through the stacked body12, and reaches the semiconductor stacked body11.

The semiconductor stacked body11is disposed on the substrate1. The substrate1is, for example, a sapphire substrate. The semiconductor stacked body11includes a plurality of layers made of semiconductor materials such as silicon, gallium nitride, gallium arsenide, silicon nitride, etc. In the case of using a sapphire substrate for the substrate1, it is preferable that the semiconductor stacked body11includes a semiconductor material made of a nitride semiconductor such as InXAlYGa1−X−Y(0≤X, 0≤Y, and X+Y<1), etc. The semiconductor stacked body11may include semiconductor layers doped with impurities.

In a plan view, the stacked body12is disposed on a surface of the semiconductor stacked body11overlapping a region where the recess r1is not provided. The stacked body12includes, for example, one or more insulating layers and one or more metal layers. In one example, the insulating layer in the stacked body12includes silicon nitride or silicon oxide. In one example, the metal layer in the stacked body12includes silver or aluminum.

The electrode film13is disposed along the surfaces10S. In other words, the electrode film13is located not only on the upper surface of the stacked body12but also on lateral surfaces and a bottom surface of the recess r1and lateral surfaces and a bottom surface of the recess r2. The electrode film13may be a single layer or may have a layered structure. A portion of the electrode film13on the bottom surface of the recess r1is in contact with the semiconductor stacked body11. The electrode film13is provided to increase the electrical contact area between the semiconductor stacked body11and another member bonded on the electrode film13. In one example, the electrode film13includes aluminum or an alloy having aluminum as a main component.

Next, as shown inFIG. 1B, in a third forming step, a metal layer24(i.e., a fourth metal layer) is formed along corresponding surfaces of the electrode film13. The metal layer24functions as a seed layer when forming a metal layer23aand a metal layer23bdescribed below using an electroplating technique. The metal layer24may be a single layer or may have a stacked structure. For example, the metal layer24is formed by stacking a titanium layer, a nickel layer, and a gold layer, in this order, on a surface of the electrode film13.

Then, a rough-surface portion is formed at or inward of at least a portion of surfaces of the structure body10that define the recess r1. The rough-surface portion in the recess r1is referred to as a “first rough-surface portion”. Also, another rough-surface portion is formed at or inward of at least a portion of surfaces defining the recess r2. The rough-surface portion in the recess r2is referred to as a “second rough-surface portion”. In the present embodiment, formation of the first rough-surface portion and second rough-surface portion are performed in a first forming step. For example, as shown inFIG. 1C, these rough-surface portions are formed by disposing a metal layer23a(i.e., a third metal layer) and a metal layer23b. Surfaces of the metal layer23aopposite to the metal layer24and surfaces of the metal layer23bopposite to the metal layer24are rough surfaces having an arithmetic average roughness Ra greater than the surfaces defining the recess r1and the surfaces defining the recess r2before forming the metal layer23aand the metal layer23b. With the metal layer23aand the metal layer23b, a roughness of at least a portion of the surfaces defining the recess r1and a roughness of at least a portion of the surfaces defining the recess r2are larger than a roughness of a surface of the metal layer24.

For example, the metal layer23aand the metal layer23bare formed using an electroplating technique. When forming the metal layer23aand the metal layer23b, a mask is formed on surfaces of the surfaces10S other than surfaces defining the recess r1and the recess r2. A photoresist for a photolithography technique is used to form such a mask. Subsequently, electroplating is performed on the surfaces10S via the mask. Then, the mask is removed by etching, etc. Accordingly, the metal layer23aand the metal layer23bare formed on only at least a portion of the surfaces defining the recess r1and at least a portion of the surfaces defining the recess r2, respectively. Thus, in this embodiment, the rough-surface portions are formed inward of at least a portion of the surfaces defining the first recess of the structure body. Any appropriate materials can be used for the metal layer23aand the metal layer23b. For example, the metal layer23aand the metal layer23bmay be made of nickel.

A method other than plating may be used to form the metal layer23aand the metal layer23bas long as these metal layers can be formed with roughened surface using the method. The formation of the metal layer24may be omitted when a technique other than a plating technique is used for forming of the metal layer23aand the metal layer23b.

Then, as shown inFIG. 1D, in a second forming step, a metal layer21(i.e., a first metal layer) is formed on the structure body10on which the metal layer23aand the metal layer23bare provided. For example, when forming the metal layer21, the metal layer21is disposed along the surfaces10S, in the recess r1and the recess r2.

The metal layer21is disposed to bond the structure body10to another member. Examples of a material of the metal layer21include any metal appropriate for bonding. For example, the metal layer21may be made of tin.

On the other hand, separately from the structure body10as shown inFIG. 1E, a substrate2on which a metal layer22(a second metal layer) is disposed is provided in a second providing step. For example, the substrate2made of Si, CuW, or the like. The metal layer22is provided to be bonded to the metal layer21of the structure body10. The metal layer22may be a single layer or may have a stacked structure. For example, the metal layer22is formed by stacking a platinum layer, a titanium layer, a nickel layer, and a tin layer, in this order.

Then, in a bonding step as shown inFIG. 1F, the metal layer21and the metal layer22are caused to face each other, and the metal layer21and the metal layer22are bonded together. In the bonding step, heating is performed while pressing the substrate1and the substrate2toward each other. Accordingly, the metal layer21and the metal layer22are melted and are bonded together. Also, at this time, with the rough-surface portions inside the recess r1and in the recess r2, the melted metal layer21and the melted metal layer22flow into the recess r1and into the recess r2. Thus, the recess r1and the recess r2are filled with the metal layer21, the metal layer22, respectively, and the like.

By the bonding described above, for example, as shown inFIG. 1G, corresponding ones of the metal layers21,22,23a,23b, and24are mixed and alloyed, so that an alloy layer25is formed. After bonding, for example, as shown inFIG. 1H, the substrate1at the structure body10side may be removed.

Effects obtained according to the first embodiment will be described with reference to comparative examples. Two methods described below are examples of methods of manufacturing according to the comparative examples.

In a method according to Comparative Example 1, the metal layer21is formed on the surfaces10S of the structure body10defining the recess r1without forming the metal layer23aand the metal layer23b. Subsequently, the metal layer21and the metal layer22formed on the substrate2are bonded together.

According to this method, the steps necessary for the bonding can be simplified. However, in this method, when a depth of the recess r1is increased, the melted metal layer21and the melted metal layer22do not flow sufficiently into the recess r1in the bonding step. Accordingly, in the semiconductor element after bonding, a hollow (a void) is formed at the position where the recess r1is provided. Presence of the hollow may cause reduction in the bonding strength, the electrical characteristics, and the heat dissipation of the semiconductor element.

In a method according to Comparative Example 2, a metal film with a high thickness for filling the recess is formed on the entirety of the surfaces10S of the structure body10without forming the metal layer23aand the metal layer23b. Then, a surface of the metal film is planarized by etching. Next, the metal layer21is formed on the planarized surface of the metal film. Subsequently, the metal layer21and the metal layer22formed on the substrate2are bonded.

In the method according to Comparative Example 2, the recess of the surfaces10S is filled securely with the metal film, which allows for improving the bonding strength, the electrical characteristics, and the heat dissipation of the manufactured semiconductor element. On the other hand, the number of steps are increased in the method according to Comparative Example 2, which may increase the manufacturing cost. In particular, when the recess r1has a high thickness, a metal film with a relatively high thickness needs to be formed to fill the recess r1. Therefore, a long period of time may be necessary to form and planarize the metal film, and the manufacturing cost may be further increased.

Compared to these methods, in the method of manufacturing according to the first embodiment, the metal layer23athat includes a rough-surface portion is formed at or inward of at least a portion of the surfaces defining the recess r1instead of forming a metal film with a high thickness. The inventors have found that the rough-surface portion can facilitate flowing of the metal melted in the bonding step into the recess r1. With the rough-surface portion that can facilitate flowing of the melted metal into the recess r1, generation of a hollow at the portion where the recess r1is provided in the semiconductor element after bonding can be prevented.

In other words, according to the method of manufacturing the semiconductor element according to the first embodiment, it is possible to fill the recess r1with the metal layer21and the metal layer22even without forming a metal film with a high thickness to fill the recess r1. Therefore, even when the metal film is not formed, the degradation of the electrical characteristics and decrease of heat dissipation can be reduced while ensuring the bonding strength of the manufactured semiconductor element. Also, formation of the metal film with a high thickness and planarization of the metal film are not required, which allows for simplifying the manufacturing steps, so that the manufacturing cost of the semiconductor element can be reduced.

As described above, according to the method of manufacturing the semiconductor element according to the first embodiment, it is possible to simplify the steps and reduce the manufacturing cost while reducing reduction of bonding strength, degradation of electrical characteristics, and reduction of heat dissipation.

According to the method of manufacturing according to the first embodiment, a rough-surface portion (in the metal layer23b) is formed also at or inward of at least a portion of the surfaces defining the recess r2even though the recess r2is has a thickness smaller than a thickness of the recess r1. With this structure, in the semiconductor element after bonding, generation of a hollow at the position where the recess r2is defined can be prevented, which allows for improving bonding strength, electrical characteristics, and heat dissipation.

Verifications by the inventors confirmed that the metal layer23aand the metal layer23beach having surfaces with Ra of approximately 29.6 nm, and other surfaces with Ra of approximately 4.1 nm allows the melted metal layer21and the melted metal layer22to flow sufficiently into the recess r1and the recess r2.

In the bonding step, it is desirable to heat the metal layer21and the metal layer22while pressing one of the structure body10(more specifically, the substrate1) and the substrate2toward the other of the structure body10(more specifically, the substrate1) and the substrate2. Pressing facilitates flowing of the melted metal layer21and the melted metal layer22into the recess r1and the recess r2. Also, according to the first embodiment, the melted metals easily flow into the recess r1and the recess r2, so that the load applied to the substrate1and the substrate2in bonding can be reduced. Therefore, damage of the substrate1, the substrate2, the structure body10, etc., in bonding can be suppressed, so that yield of the semiconductor element can be increased.

Any appropriate method can be used for forming the metal layer23aand the metal layer23bas long as the surfaces of these metal layers can be roughened using the method. However, a plating technique is preferable for forming these metal layers. Using a plating technique allows for reducing a time for forming the metal layer23aand the metal layer23bthat have rougher surfaces.

A thickness T1of the metal layer23aand a thickness T2of the metal layer23bare desired to be relatively small. Reduction of the thickness T1and the thickness T2allows for reducing a time necessary to form the metal layer23aand the metal layer23b. According to the first embodiment, even if the thickness T1and the thickness T2are reduced, the rough-surface portions allows the melted metal layer21and the melted metal layer22to be sufficiently flowed into the recess r1and into the recess r2. The thickness T1of the metal layer23aand the thickness T2of the metal layer23bare smaller than a depth D1of the recess r1. It is preferable that the thickness T1and the thickness T2are smaller than a depth D2and are 0.1 times to 0.5 times the depth D1, and are more preferably 0.15 times to 0.3 times the depth D1. With the thickness T1and the thickness T2that are 0.1 times the depth D1or greater, the effect of rough-surface portions can be obtained effectively, so that the melted metal layer21and the melted metal layer22can be easily flowed into the recess r1and r2. With the thickness T1and the thickness T2that are 0.5 times the depth D1or smaller, the time for forming the metal layer23acan be reduced, so that the yield can be increased. The depth D1of the recess r1can be, for example, approximately in a range of 4 μm to 7 μm. The depth D2of the recess r2can be, for example, approximately in a range of 1 μm to 3 μm. The thickness T1and the thickness T2can be, for example, approximately in a range of 1 μm to 3 μm.

Any appropriate materials may be used for the metal layers described above, it is desirable that the metal layer21contains tin and the metal layer22, the metal layer23a, and the metal layer23bcontain nickel. The metal layer21containing tin can have a lower melting point. Reduction in the melting point of the metal layer21allows reduction in the temperature when bonding the substrate1and the substrate2and reduction of damage to the structure body10due to heat. Further, when the metal layer22contains nickel, an alloy of nickel of the metal layer22and tin of the melted metal layer21is formed. The melting point of an alloy of tin and nickel is higher than the melting point of simple tin. Accordingly, the heat resistance of the semiconductor element can be improved, and melting of the alloy layer in the steps after bonding can be prevented, so that the degree of freedom and the yield of the manufacturing steps of the semiconductor element can be increased.

In the bonding step, the alloy of tin and nickel described above may also be formed in the recess r1and in the recess r2. The metal layers23aand23bin the recesses r1and r2allow a greater amount of tin to easily flow into the recesses r1and r2, respectively. When a greater amount of tin is flowed into each of the recesses r1and r2, a region far from the second metal layer22and the fourth metal layer24, which contain nickel, is more easily generated in each of the recesses r1and r2than in other alloyed portions. Nickel in the second metal layer22or the fourth metal layer24is not easily supplied to the region far from the second metal layer22and the fourth metal layer24. However, with the metal layer23aand the metal layer23bcontaining nickel in the recess r1and the recess r2, insufficiency of nickel can be compensated when forming the alloy in the recess r1and the recess r2. Accordingly, the melting point of the alloy of tin and nickel in the recess r1and the recess r2can be more surely increased, so that the yield of the semiconductor element can be increased.

Modified Example

FIG. 2A,FIG. 2B,FIG. 3A, andFIG. 3Bare schematic cross-sectional views of steps, showing modified examples of the method of manufacturing the semiconductor element according to the first embodiment of the present invention.

The metal layer23aand the metal layer23bhaving rough surfaces are disposed to form rough-surface portions at or inward of at least a portion of the surfaces defining the recess r1and the recess r2in the example shown inFIG. 1AtoFIG. 1H. Other methods may be employed for forming the rough-surface portions.

For example, in a modified example 1, after the metal layer24is formed, a metal layer23is formed on an entirety of corresponding surfaces of the metal layer24as shown inFIG. 2A. Next, a surface of the metal layer23other than where the recess r1and the recess r2are defined is covered with a mask M1. Subsequently, as shown inFIG. 2B, at least a portion of surfaces of the metal layer24in the recess r1and the recess r2not covered with the mask M1is processed, which roughens corresponding surfaces of the metal layer24. Examples of more specific methods for processing corresponding surfaces of the metal layer24include exposing the surfaces not covered with the mask M1to plasma of an active gas or an inert gas, irradiating the surfaces not covered with the mask M1with an ion beam of an inert gas, and wet etching the surfaces not covered with the mask M1using an etchant.

Alternatively, in a modified example 2, of the surfaces10S of the structure body10, surfaces other than surfaces defining the recess r1and the recess r2are covered with a mask M2without forming the metal layer24, as shown inFIG. 3A. Subsequently, as shown inFIG. 3B, of the surfaces10S of the structure body10, at least a portion of the surfaces defining the recess r1and at least a portion of the surfaces defining the recess r2, which are not covered with the mask M2, are processed, which roughens corresponding surfaces. A method similar to the method described above is used to process the surfaces10S of the structure body10.

Using these methods also allows for forming rough-surface portions at at least a portion of the surfaces defining the recess r1and inside the recess r2, as in the example shown inFIG. 1AtoFIG. 1H. In other words, using these methods also allows the melted metal layer21and the melted metal layer22to be easily flowed into the recess r1and into the recess r2in the bonding step.

Application Example

The method of manufacturing the semiconductor element according to the first embodiment is widely applicable to bonding of two members in which a recess is defined in a surface of one of the members. In the description below, as an example, a case in which the method of manufacturing according to the first embodiment is applied to a method of manufacturing a semiconductor light-emitting element will be described.

The structure of the semiconductor light-emitting element to be manufactured is described with reference toFIG. 4andFIG. 5.

FIG. 4is a schematic plan view showing the semiconductor light-emitting element manufactured using the method of manufacturing the semiconductor element according to one embodiment of the invention.

FIG. 5is a cross-sectional view taken along a line V-V ofFIG. 4.

As shown inFIG. 4andFIG. 5, a semiconductor light-emitting element100includes a substrate2, a structure body10, a metal layer24, an alloy layer25, a back surface electrode31, a p-pad electrode32, and a protective layer33.

The back surface electrode31is disposed at a back surface of the semiconductor light-emitting element100. The substrate2is disposed on the back surface electrode31. The alloy layer25is disposed on the substrate2. A portion of the alloy layer25protrudes upward at positions above which the recess r1and the recess r2of the structure body10are defined. The metal layer24and the electrode film13are disposed along corresponding surfaces of the alloy layer25.

The stacked body12is disposed on the electrode film13around the recess r1. The semiconductor stacked body11and the p-pad electrode32are disposed on the stacked body12. The p-pad electrode32is spaced apart from the semiconductor stacked body11in a plan view.

The semiconductor stacked body11includes an n-type semiconductor layer11a, a p-type semiconductor layer11b, and a light-emitting layer11c. The stacked body12includes a p-side electrode12a, an insulating layer12b, an interconnect layer12c, and an insulating layer12d.

The light-emitting layer11cis disposed between the n-type semiconductor layer11aand the p-type semiconductor layer11b.

The n-type semiconductor layer11ais disposed at an upper surface side of the semiconductor light-emitting element100in the semiconductor stacked body11. In a plan view, the p-type semiconductor layer11band the light-emitting layer11care disposed at a portion of the lower surface of the n-type semiconductor layer11aoverlapping a region where the recess r1is not defined.

The p-side electrode12ais disposed under portions of the p-type semiconductor layer11baround the recess r1. The insulating layer12bcovers the outer perimeter of the p-side electrode12aand the lower surface of the p-type semiconductor layer11bso that the interconnect layer12cis prevented from being in contact with components other than the p-side electrode12a. The interconnect layer12cis disposed under the p-side electrode12aand the insulating layer12band electrically connects the p-side electrode12aand the p-pad electrode32. The insulating layer12dinsulates the electrode film13from the interconnect layer12c, the p-type semiconductor layer11b, and the light-emitting layer11c. The electrode film13is in contact with the n-type semiconductor layer11aat the recess r1, and forms a contact surface11n.

The protective layer33covers corresponding surfaces of the semiconductor stacked body11. The upper surface of the n-type semiconductor layer11amay be a roughened surface that is configured to scatter light to improve the light extraction efficiency of the semiconductor light-emitting element100.

Examples of materials of the components will now be described.

The semiconductor stacked body11contains gallium nitride. The p-side electrode12aand the interconnect layer12ccontain a metal material such as aluminum, silver, indium, titanium, nickel, etc. The insulating layer12band the insulating layer12dcontain an insulating material such as silicon oxide, etc.

The back surface electrode31at the back surface of the substrate2contains a metal such as platinum, etc. The p-pad electrode32contains a metal such as titanium, platinum, gold, etc. The protective layer33contains a transparent insulating material such as silicon oxide, etc.

FIG. 6AtoFIG. 6Fare schematic cross-sectional views of steps, showing an application example of the method of manufacturing the semiconductor element according to one embodiment of the invention.

The structure body10is provided as shown inFIG. 6A. The structure body10includes the semiconductor stacked body11and the stacked body12described above. The surfaces10S of the structure body10include surfaces defining the recess r1and the recess r2having a depth smaller than a depth of the recess r1.

Next, the metal layer23aand the metal layer23bare formed above at least a portion of the surfaces defining the recess r1and at least a portion of the surfaces defining the recess r2of the structure body10, respectively. Then, as shown inFIG. 6B, the metal layer21is formed at the surfaces10S side of the structure body10. The metal layer21is bonded to the metal layer22on the substrate2shown inFIG. 1E, so that the structure shown inFIG. 6Cis obtained. In other words, the metal layer21and the metal layer22are bonded, and the metal layers21,22,23a,23b, and24are mixed to be alloyed, so that the alloy layer25is formed.

Then, the substrate1is removed as shown inFIG. 6D. Next, as shown inFIG. 6E, the semiconductor stacked body11and the insulating layer12bare processed, so that the p-pad electrode32and the protective layer33are formed. Subsequently, as shown inFIG. 6F, the back surface electrode31is formed at the backside of the substrate2. Then, the substrate2is diced at a dicing line DL shown inFIG. 6F. The dicing line DL is positioned in the region where the recess r2is defined. The semiconductor light-emitting element100shown inFIG. 4andFIG. 5is manufactured through the steps described above.

The embodiments described above are examples for giving a concrete form of the invention, and the scope of the present invention is not limited to the embodiments described above. Any appropriate modifications of the embodiments described above made by one skilled in the art without departing from the spirit of the present invention also are within the scope of the invention.