Adaptive parameterization for maximum current protection

An apparatus is provided which comprises: a controller to allocate, to a component, a resource budget selected from a plurality of quantization levels; and a circuitry to adaptively update the plurality of quantization levels.

BACKGROUND

One of the electrical constraints on modern computing devices is a limit on a total current delivered to a computing device, e.g., by a motherboard voltage regulator (MBVR). This constraint may become more restrictive in future computing devices, e.g., since with each generation more functionality may be added to System-on-chips (SOCs) due to an increasing transistor count per chip. In turn, more power may have to be delivered by the MBVR. Even though designing for a higher MBVR current capacity may help alleviate this issue, this might increase a cost of the system. Existing computing devices may utilize mechanisms to limit the maximum expected current.

DETAILED DESCRIPTION

FIG. 1illustrates a computing system100with multiple subsystems104a, . . . ,104N. Elements referred to herein with a common reference label followed by a particular number or alphabet may be collectively referred to by the reference label alone. For example, subsystems104a,. . . ,104N may be collectively and generally referred to as subsystems104in plural, and subsystem104in singular.

Individual subsystems104can be, for example, processing cores, processors, memory, arithmetic-logic units, on-chip interconnects, memory controllers, caches, and/or any appropriate component of a computing system. A MBVR102may supply power to the subsystems104a,. . . ,104N. In some embodiments, the MBVR102may supply power to the subsystems104a,. . . ,104N via respective voltage regulators (VR)108a,. . . ,108N. In some other embodiments, one or more of the VRs108a,. . . ,108N may be optional, and may not be present in the system100. Merely as an example, one or more of the VRs108a,. . . ,108N may be present if, for example, Dynamic Voltage and Frequency Scaling (DVFS) is implemented at the subsystem granularity.

The current consumption of a computing device (e.g. system100) may be a sum of the currents consumed by all of its subsystems (e.g., subsystems104). Different workloads may incur different activities on these subsystems, which may affect a total instantaneous current supplied by the MBVR102. Moreover, the current of a subsystem104may be based on (e.g., proportional to) to the corresponding voltage and/or frequency of the subsystem, which may be variable if the subsystem power/performance can be controlled dynamically via mechanisms such as DVFS.

In an example, the total current drawn from the MBVR102may be expressed in terms of the currents of individual subsystems104as:
IMBVR=Σk=1nCdyn,k·fk·Vk+CONSkEquation 1.

In equation 1, the index k may denote a subsystem in a computing device with n subsystems. Cdyn,kmay be the dynamic capacitance for a kthsubsystem, Vkmay be the voltage of the kthsubsystem, and fkmay be the frequency of the kthsubsystem. CONSkmay represent a current drawn by the kthsubsystem, e.g., regardless of the activity of the subsystem.

In some embodiments, dynamic capacitance of a subsystem (e.g., dynamic capacitance Cdyn,kof a kthsubsystem, as discussed with respect to equation 1) may be defined as an equivalent capacitance of the subsystem. In an example, the dynamic capacitance of the subsystem may be a function of the circuit design of the subsystem, the instantaneous activity (e.g., bit switching of the logic gates) of the subsystem, and/or the like. In an example, the dynamic capacitance Cdyn,kmay depend on the workload that is running on the computing device (e.g., running on the subsystem k).

In an example, in order to reduce the current drawn by a subsystem, the Cdynof a subsystem may be reduced (e.g., using methods such as throttling). In another example, in order to reduce the current drawn by a subsystem, the frequency f and/or voltage V may be reduced, e.g., via DVFS or by another means. In some embodiments, DVFS may be implemented at a system level, e.g., by controlling the frequency and/or the voltage of the MBVR102. Additionally, or alternatively, DVFS may also be implemented at a subsystem level, e.g., by controlling the frequency and/or the voltage of one or more of the VRs108a,. . . ,108N.

In an example, reducing current via throttling may be typically less energy and power efficient compared to DVFS. In an example, on the other hand, reducing current via throttling may be faster to execute compared to DVFS.

Various embodiments of this disclosure discuss performing guided current fitting, e.g., to dynamically adjust the power and/or performance point of the subsystems104, e.g., such that the subsystems104may stay within a current budget at a maximum or relatively high performance possible whenever the subsystem dynamic capacitances change. Some embodiments of this disclosure add a layer of dynamic adaptation, which may change how the guided current fitting is performed by the subsystems.

For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

FIG. 2illustrates a system200for controlling instantaneous current of various subsystems104a,. . . ,104N (e.g., the subsystems104ofFIG. 1), to fit available resource budget, according to some embodiments.

In an example, if there were no physical constraints on the system200, it would be beneficial to run all the subsystems104at a highest or a higher frequency and/or voltage point, e.g., since that may provide the optimal or near optimal performance. However, in most practical systems, a total current supplied by the MBVR102ofFIG. 1may be constrained, and hence, the instantaneous current of the system200has to fit an available resource budget.

In some embodiments, the system200may comprise a controller circuitry202, which may be able to track the current consumed by each subsystem104, and may budget available resource per subsystem accordingly. The system200may further comprise a communication mechanism204(e.g., comprising buses, interconnect links, interconnect fabric, etc.) between the controller circuitry202and the subsystems104.

The system200may further comprise, for each subsystem104, a corresponding current measurement and/or estimation circuitry208(e.g., circuitries208a, . . .208N), and a corresponding current reduction circuitry212(e.g., circuitries212a,. . . ,212N). A circuitry208may measure or estimate the current of a corresponding subsystem104.

In some embodiments, the communication mechanism204may communicate between the circuitry202and the circuitries208a,. . . ,208N, and may also communicate between the circuitry202and the circuitries212a,. . . ,212N.

In an example, the circuitry208may be implemented by direct current measurements, e.g., via analog sensors. In another example, a circuitry208may be implemented by dynamic capacitance estimations, e.g., via digital methods (which may later be converted to current in some examples). A subsystem104may make relatively fast (e.g., but potentially inefficient) local decisions based on this information from the corresponding circuitry208, and communicate with the controller circuitry202for more efficient decisions. In an example, an actual current of a subsystem104may not usually exceed a current value measured or estimated by the corresponding circuitry208.

In an example, the circuitry212may externally reduce the current consumption of the corresponding subsystem104(e.g., via DVFS), e.g., without altering the workload running on it (e.g., without throttling the workload).

In an example, a guided current fitting action may originate from either locally from a subsystem104, or from the controller circuitry202. The local decisions (e.g., made locally by circuitries208and/or212) may be relatively fast, but may be sub-optimal, e.g., since they do not have any information about the budget allocated to other subsystems and/or consumption of the other subsystems. On the other hand, the decisions from the controller circuitry202may be relatively slower, e.g., due to communication cost (e.g., delay due to the communication between the subsystems104and the circuitry202) and computation costs (e.g., incurred in the centralized circuitry202), but the decisions from the controller circuitry202may be based on the information collected from all the subsystems104. The controller may implement an appropriate algorithm, e.g., as long as the sum of the budgets of the subsystems104is within the total current envelope of the MBVR102ofFIG. 1.

FIG. 3illustrates a high level flowchart of a method300for operating the system200, according to some embodiments. Although the blocks in the flowchart with reference toFIG. 3are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed inFIG. 3may be optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

At304, the method300may initiate or start. At308, initial resource budget may be assigned to individual subsystems104(e.g., by the controller circuitry202). Merely as an example, a first subsystem104amay be assigned a first resource budget (e.g., a current budget), a second subsystem104bmay be assigned a second resource budget, and so on.

At312, individual subsystems104may operating in accordance with the budget. For example, a subsystem104may operate at a highest or higher performance possible, given the budget allocated to the subsystem.

At316, dynamic capacitance Cdyn,kof a kthsubsystem may change, where the kthsubsystem may be one of the subsystems104a,. . . ,104N. As a result of the change in the dynamic capacitance Cdyn,k,the current consumption of the kthsubsystem may also change accordingly. At320, a determination is made (e.g., by the circuitry208and/or the circuitry212) as to whether the updated current of the kthsubsystem is over the allocated resource budget to the kthsubsystem.

If “Yes” at320(e.g., if the updated current of the kthsubsystem is over the allocated budget), then at324, the kthsubsystem may reduce current locally (e.g., by throttling the current). Subsequent to324, the method300may proceed to328, where the kthsubsystem current may be within the budget (e.g., due to the reduction of current at324), but may potentially perform inefficient execution (e.g., because the current is throttled, the kthsubsystem may not achieve the desired performance).

Also, if “No” at320(e.g., if the updated current of the kthsubsystem is under the allocated budget), then the method300may proceed from320to328.

Subsequent to328, the method300may proceed to336, where the kthsubsystem may communicate to the controller circuitry202any budget need or any excess budget (e.g., based on the determination at320). At332, the controller circuitry202may adjust the budget allocation, and may optimize current adjustment mechanism parameters for the kthsubsystem.

In an example, there may be multiple reasons that the execution of the method300may be less than optimal, e.g., depending on how the state at328is reached and what current reduction mechanisms are used. As an example, throttling may be used as the local current reduction method by the subsystems104(e.g., by the circuitries212) at324, whereas the controller circuitry202may reduce the current via DVFS at332. This may be a reasonable assumption, e.g., as throttling may react faster than DVFS, and hence may be suitable for reacting to a budget overrun, but throttling may not be as power and energy efficient as DVFS.

For a given subsystem104(e.g., subsystem104a), if the subsystem104areaches the state of328via the “under the budget” path from320, the controller circuitry202may either shift the excess budget elsewhere (e.g., to other subsystems104), or may utilize the excess budget within the subsystem104aby increasing an operating frequency and/or voltage of the subsystem104ato a point where there is no excess budget for that subsystem104a.If the subsystem104areaches the state of328via the “over the budget” path from320, this may imply that the subsystem104ais throttling until the controller circuitry202may either assign more current to the subsystem104a,or may reduce its operating frequency and/or voltage to meet the budget.

The followingFIGS. 4A-4Billustrate the two cases explained above with respect toFIG. 3(e.g., a first path from320to328via324due to over the budget, and a second path from320directly to328due to under the budget). DVFS may be used by the controller circuitry202to fit the subsystem current to the budget. The subsystem104may use dynamic capacitance for current estimates and budgeting.

FIGS. 4A-4Billustrate plots400aand400b, respectively, showing maximum current protection flow for a subsystem104(e.g., subsystem104a) with constant current budget, and DVFS for guided current fitting by the controller circuitry202, according to some embodiments. InFIG. 4A, the Cdynof the subsystem104amay increase, e.g., due to a change in the workload; and inFIG. 4B, the Cdynof the subsystem104amay decrease, e.g., due to a change in the workload.

In bothFIGS. 4A-4B, the X axis represents time. The Y axis represents subsystem frequency, as well as the Cdynof the subsystem104a.For example, the lines402aand402bofFIGS. 4A and 4B, respectively, illustrate the frequency of the subsystem104a.The lines404aand404bofFIGS. 4A and 4B, respectively, illustrate the Cdynof the subsystem104a.Dotted lines406aand406bofFIGS. 4A and 4B, respectively, illustrate allocated Cdynbudget to the subsystem104a.

The sequence of events inFIG. 4amay be as follows. Initially, the subsystem104amay be under the allocated dynamic capacitance budget (e.g., between points1and2). Subsystem Cdynmay start increasing due to the workload running on the computing device, and the Cdyn of the subsystem104amay surpass the allocated budget (e.g., line404acrossing over and becoming higher than the line406asometime between points2and3). As a result, the subsystem may104athrottle to bring the Cdyndown to the budget after a short detection/reaction delay (short excursions may be tolerable by the MBVR), as illustrated by the sharp decline in Cdynat point3in the figure. At point4, the controller circuitry202may start reducing the subsystem frequency in order to increase the Cdynbudget of the subsystem104a—note that even though the current budget may be fixed in this example, the Cdynbudget may be increased by reducing the voltage and/or the frequency point (see Equation 1). At point5, the controller circuitry202may set a new budget, e.g., once the voltage and/or the frequency point is reduced. At point6, once the Cdynbudget is adjusted, the subsystem104amay release the previous throttling, e.g., following a signal from the controller circuitry202indicating the new budget. As a result, from point6, the Cdynmay experience a sharp increase.

The sequence of events inFIG. 4bmay be as follows. Initially, the subsystem104amay be under the allocated dynamic capacitance budget (e.g., between points1and2). The subsystem Glyn may start decreasing (e.g., starting at about or immediately prior to the point2), e.g., due to the workload running on the computing device, thereby creating a gap between the allocated current budget and the actual current consumption. In an example, the subsystem104amay communicate with the controller202for a lower budget. At point3, the controller202may lower the budget, and, for example, the controller202may start increasing the subsystem frequency from point3, e.g., in order to bring the subsystem104ato a higher performance point while reducing the allocated Cdynbudget (e.g., the current budget may still be constant). At point4, the controller202may communicate the new budget to the subsystem104a.

InFIGS. 4A and 4B, periods of possible non-optimal or sub-optimal operations are illustrated using respective arrows.

An ideal maximum current protection system may be able to track the electrical current observation with no delay and converge to an optimal or near optimal solution instantaneously. In reality, a delay may exist between the observation and the controller circuitry202adjusting the subsystems according to a solution. This delay may be due to the internal communication and/or computation costs, and on average may be expressed with the following equation.
D=CONST+F(#events).   Equation 2.

The first term in this equation, CONST, may be a constant that may depend on the SoC design, or other fixed parameters. F may be a monotonically increasing function of the number of times that controller circuitry202receives current change reports from the subsystems104(e.g., to which the controller circuitry may react via current guiding actions). A larger delay may imply that the maximum current protection system is not able to react to the changes in the subsystems fast enough, and the subsystems104may remain at the inefficient execution states for relatively longer time duration.

In some embodiments, the system500may further comprise a phase detection, profiling and adaptation circuitry510. The circuitry510may receive telemetry data560, e.g., from various subsystems554. In some embodiments, the circuitry510may generate adaptation parameters564, and may transmit the parameters564to the subsystems554and/or to the controller circuitry502, as discussed herein in details. In some embodiments, the circuitry510can be implemented externally (e.g., via a combination of hardware and/or software), and/or in a dedicated microcontroller (e.g., in the form of firmware).

In some embodiments, while in operation, the system500may undergo through various phases of operation.FIG. 6illustrates various example phases of operation of an example subsystem554(e.g., subsystem554a) of the system500, according to some embodiments.FIG. 6is a graph of Cdyn(Y axis) versus time (X axis). Merely as an example, phase1may be a compute bound phase, during which the subsystem554a(which may be, merely as an example, a processor) may have relatively high and somewhat steady Cdyn. During phase1, the subsystem554amay be engaged in active computation, e.g., may execute instructions and not waiting for data from a cache, a memory, etc.

During a phase2, the subsystem554amay wait for data to be fetched from a cache, a memory, etc. For example, the subsystem554amay be stalled, and may have low and somewhat steady Cdyn. In some embodiments, during the phase2, the subsystem554amay wait for data (e.g., be stalled) multiple times. For example, during phase2, although the subsystem554amay perform some computation, the subsystem554amay wait during a substantial portion of the phase2for data to be fetched from caches, one or more memory, etc.

During phase3, the Cdynof the subsystem554amay be bursty (e.g., rapidly changing with time) and/or may be unpredictable to some extent.

In some embodiments, the graph600ofFIG. 6may be generated by measuring current consumption of a subsystem554(e.g., subsystem554a), by monitoring logic gate activities of the subsystem554a,and/or the like.

In some embodiments, an example mechanism that may detect the phases of a program or a subsystem may include an Application Programming Interface (API) which the application can use to explicitly mark phases. Knowledge of the phases can be communicated (e.g., to the circuitry510) via this API.

In some embodiments, automatic phase detection (APD) may also be used to detect the phase. For example, APD can be applied to deduce the phases of a program, e.g., from the telemetry data560collected from a computing device. An example of an APD has been discussed in further details in U.S. patent Publication No. US20160188393, entitled “Automatic phase detection.”

In some embodiments, based on one or more of these example mechanisms (e.g., using API to detect phase, using APD to detect phase, and/or using another appropriate mechanism to detect phase), a system that recognizes and adapts to the current phase may be constructed. For example, one or both these mechanisms can be used (e.g., by circuitry510) to detect or estimate an upcoming phase and/or to estimate an ongoing phase of a subsystem. For example, the phases of a subsystem may be repetitive in nature (e.g., occurs frequently), and so, the circuitry510may estimate a current phase or an upcoming phase of a subsystem.

Referring again toFIG. 5, an input to the circuitry510may be the telemetry data560collected from the subsystems554and/or from other components of the system500. In some embodiments, based on this telemetry data560, the circuitry510(e.g., a phase detection and profiling part of the circuitry510) may deduce the characteristics of the workload execution phase. In some embodiments, the circuitry510(e.g., an adaption part of the circuitry510) may use this phase information and/or previously collected data about the phase to make a decision for the control parameter values during this phase. For example, the circuitry510may adaptively generate adaptation parameters564, based at least in part on the current phase information and/or previously collected data about the current phase. In some embodiments, such mechanism may implement a feedback-guided control system employing an optimization method (e.g., such as gradient descent) to gradually converge to the optimal set of values. Examples of such mechanism are discussed in further details in U.S. Patent Publication No. US20160179117A1, entitled “Systems and methods for dynamic temporal power steering”; in U.S. Patent Publication No. US20160179173A1, entitled “Systems and methods for dynamic spatial power steering”; and in U.S. Patent Publication No. US20160179156A1, entitled “Hybrid power management approach.” In some embodiments, the adaptation parameters may be communicated to the controller circuitry502, to the subsystems554, and/or to other components of the system500.

In some embodiments, in the system500, the per-subsystem Cdynbudget (or current budget) may be quantized into a finite number of levels (e.g., because the computations are done in the digital domain). In some embodiments, a lower number of such quantization levels may reduce the communication and computation costs (e.g., as discussed herein above at least in part with respect to equation 2), but may result in increased computational error. Each level may be expressed in terms of a higher and a lower threshold value, where the unit of the value may depend on the current measurement/estimation circuitries508. In some embodiments, the budget quantization levels may be decided adaptively, e.g., by the circuitry510. For example, the adaptation parameters564may include the adaptively determined budget quantization levels for a subsystem. Such adaptive determination of the budget quantization levels for a subsystem (e.g., the subsystem554a) may be based on an estimated phase of the subsystem554a(e.g., where the phase may be estimated by the circuitry510).

Instead of adaptively determining the budget quantization levels, the budget quantization levels may be static. However, such static budget quantization levels may typically lead to underutilization of the total current budget due to quantization errors. In order to not exceed the MBVR current constraint, subsystem current and/or Cdyn observations may be rounded up to the next quantization level. In order to alleviate the quantization errors, the quantization resolution can be increased. However, such an increase may lead to higher communication and computation costs for the maximum current protection system (e.g., see equation 2). In turn, subsystems554may receive optimal or near optimal solutions with relatively larger delays, remaining at the inefficient execution states longer. This phenomenon may particularly affect workloads which cause rapid Cdyn and/or current changes on the subsystems.

However, in some embodiments, adaptively updating the budget quantization levels may alleviate these issues, as discussed in details herein later. For example, some of the embodiments discussed herein is associated with adaptively changing threshold values of the fixed number of quantization levels, e.g., to more closely track the current consumption of the subsystems and hence, reducing the losses that arise from the quantization errors. If the quantization level thresholds are adjusted dynamically on a per workload basis via a controller algorithm that has the global view of the system500(e.g., of the subsystems554), the maximum current protection system can operate at an optimal or near optimal state, e.g., where it can track the current measurements and/or estimates fast enough, without creating a communication or computation bottleneck.

A mechanism that may aim to reduce the communication and computation costs is decision hysteresis. Decision hysteresis may introduce a concept of a no-reaction period, e.g., during which the reactions to the subsystem Glyn changes may be put on hold temporarily, thereby effectively limiting the number of current guiding actions (e.g., number of events “#events”) of equation 2. There can be a number of criteria that triggers a decision hysteresis, one of which may be high-to-low hysteresis. In an example, high-to-low hysteresis may trigger a no-reaction period to stop budget reduction actions towards a subsystem, once the budget has been increased. In some embodiments, a high-to-low hysteresis may be of interest, for example, because keeping the budget at a higher point may avoid potentially higher number of throttling events, which may not be efficient.

FIG. 7illustrates a graph700depicting hysteresis delay in switching between budget quantization levels for a subsystem554ofFIG. 5, according to some embodiments. The X axis represents time, and the Y axis illustrates Cdyn. The graph700illustrates, using solid line704, the actual Cdyn; and budgeted or allocated Cdynusing dotted line702.

Prior to time t0, the estimated Cdynof the subsystem may be less than a threshold, where the threshold may correspond to the allocated or budgeted Cdynfor the subsystem. For example, prior to time t0, the budgeted Cdynmay be at a quantization level1.

At time t0, the estimated Cdynexceeds the allocated or budgeted Cdyn, and hence, the budgeted Cdynmay be increased to quantization level2from time t0, as illustrated by the line702.

Subsequently, at time t1, the estimated Cdynmay decrease and go below the Cdynassociated with the quantization level1, and remain below the Cdynassociated with the quantization level1. However, due to the hysteresis delay, the budgeted Cdynmay not be decreased immediately from time t1—rather, the budgeted Cdynmay be decreased from time t2. The delay between t1and t2may be due to the decision hysteresis delay.

However, deferring decisions associated with hysteresis may have the similar effect of subsystems remaining at the inefficient execution states. For example, shorter hysteresis may result in rapid state change and increased computing, whereas longer hysteresis may result in the subsystem remaining at an inefficient execution state for a longer period.

In some embodiments, a hysteresis parameter may dictate the amount of hysteresis delay. As will be discussed herein, in some embodiments, the circuitry510may adaptively update the hysteresis parameter for a subsystem554(or for the system500), e.g., based on estimating a phase of operation of the subsystem554(or phase of operation of the system500) or based on another appropriate factor.

In some embodiments, the hysteresis delay may be applied when the resource budget is to be decreased, and may not be applied when the resource budget is to be increased. For example, any delay in increasing the resource budget may adversely impact the performance of the corresponding subsystem, and hence, hysteresis may not be applied when the budget is to be increased, as illustrated inFIG. 7. As discussed, the hysteresis delay applied (e.g., when the resource budget is to be decreased) may be adaptively updated, based on the estimated current and/or upcoming operational phase of a subsystem.

Thus, as discussed herein, various embodiments of this disclosure may adaptively and dynamically set the parameters related to maximum current protection (such as the quantization level thresholds and/or the decision hysteresis delay), e.g., on a per-workload or per-phase basis.

In some embodiments, in the example of adaptive budget quantization, the adaptation mechanism (e.g., in the circuitry510) may execute one or both of the following two actions to influence the computing device performance: (i) Change the threshold values in a way that the number of quantization levels is the same, but levels are spaced out differently to better track the current profile—this is demonstrated inFIGS. 8A and 8B. (ii) Change the threshold values in a way that the number of quantization levels is effectively changed (e.g., reduced) to change (e.g., lower) the computation and communication bottlenecks in the maximum current protection system—this applies to workloads with rapidly or widely changing current profiles, as demonstrated inFIGS. 9A-9B.

FIGS. 8A and 8Billustrate graphs800aand800b,respectively, illustrating effects of adaptively setting the quantization levels for a subsystem554ofFIG. 5, according to some embodiments. The X axis of graphs800aand800brepresent time, and the Y axis illustrates Cdyn. The graph800aand800billustrate, using solid line802aand802b,respectively, the actual Cdynin two scenarios. The graph800aand800billustrate, using dotted lines804aand804b,respectively, the budgeted Cdynwith two possible quantization levels. Thus,FIGS. 8A-8Bare directed to adapting to the current profile of a workload, and with two quantization levels assumed. The shaded regions illustrate quantization gaps or quantization errors. InFIG. 8A, due to the way the quantization levels are set, the quantization errors are relatively large. In some embodiments and as illustrate inFIG. 8B, the quantization levels may be set adaptively so that the quantization errors are relatively smaller.

FIGS. 9A and 9Billustrate plots showing adaptively changing a number of quantization levels used for allocating resource budget to various subsystems ofFIG. 5, according to some embodiments. For example, in these figures, the solid line illustrates the actual load, and the dotted line illustrates the change in the quantization level of the budgeted Cdyn. InFIG. 9A, there are 6 quantization levels, while inFIG. 9Bthere are 4 quantization levels. With the decrease in the quantization level, the computational load may decrease, but the quantization error may increase.

FIG. 10illustrates a flowchart depicting a method1000for adaptively updating hysteresis parameters and/or quantization level parameters, based on a current operational phase of a subsystem ofFIG. 5, according to some embodiments. Although the blocks in the flowchart with reference toFIG. 10are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed inFIG. 10may be optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

In some embodiments, at1004, a system (e.g., system500) may be operated in a tuning mode (e.g., which may also be referred to as a calibration phase), where a plurality of operational phases of the system and/or of individual subsystems554may be profiled and identified, as discussed herein above.

At1008, for each operational phase, corresponding optimal or near optimal hysteresis parameters and/or quantization level parameters may be identified or established. Such identification may be based on an appropriate optimization method (e.g., such as gradient descent) to gradually converge to the optimal or near optimal set of values.

At1012, the system500and/or individual subsystems554may be operated in a regular mode, and a current operational phase of the system500and/or individual subsystems554may be estimated.

At1016, in the regular mode, the hysteresis parameters and/or the quantization level parameters may be adaptively updated, based on the current operational phase (e.g., to correspond to the optimal or near optimal hysteresis parameters and/or quantization level parameters identified at1008for the current operational phase).

Various embodiments of this disclosure discuss adaptively or dynamically (e.g., in real-time, automatically, without user intervention, etc.) updating various parameters associated with maximum current protection mechanism (e.g., to ensure that the maximum current of the whole system does not exceed the total available budget). Examples of such parameters discussed herein include quantization parameters, hysteresis parameters, etc. However, in some embodiments, various other parameters associated with maximum current protection mechanism may also be adaptively updated, e.g., based on estimating a current operation phase of the system. Thus, updating the quantization parameters and/or hysteresis parameters are merely examples, and any parameter associated with maximum current protection mechanism may also be adaptively updated, e.g., based on estimating a current operation phase of the system.

FIG. 11illustrates a computer system, computing device or a SoC (System-on-Chip)2100, where hysteresis parameters and/or the quantization level parameters for allocating resource to individual subsystems may be adaptively and dynamically updated, according to some embodiments. It is pointed out that those elements ofFIG. 11having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In some embodiments, computing device2100represents an appropriate computing device, such as a computing tablet, a server, a workstation, a mobile phone or smart-phone, a laptop, a desktop, an IOT device, a wireless-enabled e-reader, or the like. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device2100.

In some embodiments, computing device2100includes a first processor2110. The various embodiments of the present disclosure may also comprise a network interface within2170such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

In one embodiment, computing device2100includes audio subsystem2120, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device2100, or connected to the computing device2100. In one embodiment, a user interacts with the computing device2100by providing audio commands that are received and processed by processor2110.

Display subsystem2130represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device2100. Display subsystem2130includes display interface2132, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface2132includes logic separate from processor2110to perform at least some processing related to the display. In one embodiment, display subsystem2130includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller2140represents hardware devices and software components related to interaction with a user. I/O controller2140is operable to manage hardware that is part of audio subsystem2120and/or display subsystem2130. Additionally, I/O controller2140illustrates a connection point for additional devices that connect to computing device2100through which a user might interact with the system. For example, devices that can be attached to the computing device2100might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller2140can interact with audio subsystem2120and/or display subsystem2130. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device2100. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem2130includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller2140. There can also be additional buttons or switches on the computing device2100to provide I/O functions managed by I/O controller2140.

Connectivity2170includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device2100to communicate with external devices. The computing device2100could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Connectivity2170can include multiple different types of connectivity. To generalize, the computing device2100is illustrated with cellular connectivity2172and wireless connectivity2174. Cellular connectivity2172refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface)2174refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

Peripheral connections2180include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device2100could both be a peripheral device (“to”2182) to other computing devices, as well as have peripheral devices (“from”2184) connected to it. The computing device2100commonly has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device2100. Additionally, a docking connector can allow computing device2100to connect to certain peripherals that allow the computing device2100to control content output, for example, to audiovisual or other systems.

In some embodiments, the computing device2100may comprise the controller circuitry502, the phase detection, profiling and adaptation circuitry510, and/or various components discussed with respect toFIG. 5(or other figures herein earlier). In an example, individual subsystems554a,. . . ,554N discussed with respect toFIG. 5may be any appropriate component of the computing device2100(e.g., the processor2110). In some embodiments, the circuitries502,510and/or the like may adaptively and dynamically update various parameters of the computing device2100associated with a maximum current in a system, as discussed herein in this disclosure, e.g., with respect toFIGS. 1-10. One or more of the circuitries502,510may be implemented in any of the components of the computing device2100, e.g., in the processor2110, appropriate hardware circuitry or microprocessor of the computing device2100(not illustrated inFIG. 11), and/or the like.

The following example clauses pertain to further embodiments. Specifics in the example clauses may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

Example 1. An apparatus comprising: a controller to allocate, to a component, a resource budget selected from a plurality of quantization levels; and a circuitry to adaptively update the plurality of quantization levels.

Example 2. The apparatus of example 1 or any other example, wherein the circuitry is a first circuitry, and wherein the apparatus comprises: a second circuitry to estimate an operational phase of the component, wherein the first circuitry is to adaptively update the plurality of quantization levels, based on the estimated operational phase of the component.

Example 3. The apparatus of example 1 or any other example, wherein to adaptively update the plurality of quantization levels, the circuitry is to adaptively update a number of quantization levels in the plurality of quantization levels.

Example 4. The apparatus of example 1 or any other example, wherein to adaptively update the plurality of quantization levels, the circuitry is to adaptively update values of individual quantization levels in the plurality of quantization levels.

Example 5. The apparatus of any of examples 1-4 or any other example, wherein the component is to operate in accordance with the allocated resource budget.

Example 6. The apparatus of example 5 or any other example, wherein the component is to: apply throttling to reduce a current consumed by the component, in response to the component exceeding the allocated resource budget.

Example 7. The apparatus of example 6 or any other example, wherein the resource budget is a first resource budget, and wherein the controller is to: allocate, to the component, a second resource budget selected from the plurality of quantization levels, in response to the component exceeding the allocated resource budget and subsequent to the component applying the throttling.

Example 8. The apparatus of any of examples 1-4 or any other example, wherein: the controller is to apply a hysteresis in allocating the resource budget; and the circuitry is to adaptively update a hysteresis parameter associated with the hysteresis.

Example 9. A system comprising: a memory to store instructions; a processor coupled to the memory, the processor to execute the instructions; a first circuitry to use a plurality of quantization levels to quantize an available budget for allocation to the processor; and a second circuitry to dynamically set the plurality of quantization levels.

Example 10. The system of example 9 or any other example, further comprising: a third circuitry to estimate a current and/or an upcoming operational phase of the processor, wherein the second circuitry is to dynamically set the plurality of quantization levels, based on the current and/or the upcoming operational phase of the processor.

Example 11. The system of any of examples 9-10 or any other example, wherein: the first circuitry is to apply a hysteresis delay in allocating a resource budget to the processor; and the second circuitry is to dynamically set the hysteresis delay.

Example 12. The system of any of examples 9-10 or any other example, wherein to dynamically set the plurality of quantization levels, the second circuitry is to dynamically set a number of quantization levels in the plurality of quantization levels.

Example 13. The system of any of examples 9-10 or any other example, wherein to dynamically set the plurality of quantization levels, the second circuitry is to dynamically set values of individual quantization levels in the plurality of quantization levels.

Example 14. An apparatus comprising: a controller to apply a hysteresis delay in allocating, to a component, a resource budget; and a circuitry to adaptively update the hysteresis delay, based on an operational phase of the component.

Example 15. The apparatus of example 14 or any other example, wherein the circuitry is a first circuitry, the wherein the apparatus comprises: a second circuitry to estimate the operational phase of the component.

Example 16. The apparatus of any of examples 14-15 or any other example, wherein: the controller is to apply the hysteresis delay when the controller is to decrease an allocation of the resource budget to the component.

Example 17. The apparatus of any of examples 14-15 or any other example, wherein: the controller is to refrain from applying the hysteresis delay when the controller is to increase the allocation of the resource budget to the component.

Example 18. An apparatus comprising: a first circuitry to identify a first quantization parameter and a second quantization parameter corresponding to a first operation phase and a second operation phase, respectively, of a component; a second circuitry to identify that the component is operating in the first operation phase; a third circuitry to set a plurality of quantization levels based on the first quantization parameter, in response to the identification that the component is operating in the first operation phase; and a fourth circuitry to allocate, to the component, a resource budget selected from the plurality of quantization levels.

Example 19. The apparatus of example 18 or any other example, wherein the first circuitry is to identify the first quantization parameter and the second quantization parameter corresponding to the first operation phase and the second operation phase, respectively, based on a feedback-guided control system employing a gradient descent optimization method.

Example 20. The apparatus of any of examples 18-19 or any other example, wherein to set the plurality of quantization levels, the third circuitry is to set one or both of: a number of quantization levels in the plurality of quantization levels, or values of individual quantization levels in the plurality of quantization levels.

Example 21. A method comprising: allocating, to a component, a resource budget selected from a plurality of quantization levels; applying a hysteresis in allocating the resource budget; and adaptively updating one or both of: the plurality of quantization levels, or a hysteresis parameter associated with the hysteresis.

Example 22. The method of example 21 or any other example, wherein the adaptively updating comprises: estimating an operational phase of the component; and adaptively updating, based on the estimated operational phase of the component.

Example 23. The method of any of examples 21-22 or any other example, wherein adaptively updating the plurality of quantization levels comprises one or both of: adaptively updating a number of quantization levels in the plurality of quantization levels, or adaptively updating values of individual quantization levels in the plurality of quantization levels.

Example 24. One or more non-transitory computer-readable storage media to store instructions that, when executed by a processor, cause the processor to execute a method of any of the examples 21-23.

Example 25. An apparatus comprising: means for performing the method of any of the examples 21-23.

Example 26. An apparatus comprising: means for allocating, to a component, a resource budget selected from a plurality of quantization levels; means for applying a hysteresis in allocating the resource budget; and means for adaptively updating one or both of: the plurality of quantization levels, or a hysteresis parameter associated with the hysteresis.

Example 27. The apparatus of example 26 or any other example, wherein the means for adaptively updating comprises: means for estimating an operational phase of the component; and means for adaptively updating, based on the estimated operational phase of the component.

Example 28. The apparatus of any of examples 26-27 or any other example, wherein the means for adaptively updating the plurality of quantization levels comprises one or both of: means for adaptively updating a number of quantization levels in the plurality of quantization levels, or means for adaptively updating values of individual quantization levels in the plurality of quantization levels.