Backside PN junction diode

The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

BACKGROUND

The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.

Multi-gate devices, such as fin field-effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors (also known as gate-all-around (GAA) transistors, surrounding gate transistors (SGTs), nanowire transistors, or nanosheet transistors), have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). The three-dimensional structure of the multi-gate devices, allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. However, even with the introduction of multi-gate devices, aggressive scaling down of IC dimensions has resulted in densely spaced gate structures and source/drain contacts. The densely packed gate structures and source/drain contacts pose challenges to form routing on only one side of the substrate. Some conventional techniques have been proposed to move some of the routing features to the backside of the substrate. Although structures produced by these conventional techniques are generally adequate for their intended purposes, they are not satisfactory in all aspects.

DETAILED DESCRIPTION

Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.

The present disclosure generally relates to semiconductor devices. Particularly, the present disclosure relates to back-side routing and embedded PN junction diodes.

FIG. 1illustrates a fragmentary cross-sectional view of a first semiconductor device100-1along the Y direction. In some embodiments represented inFIG. 1, the first semiconductor device100-1has a structure similar to a multi-bridge-channel (MBC) transistor that includes a plurality of bridge-like channel members (or channel structures). An MBC transistor may be referred to as a gate-all-around (GAA) transistor or a surrounding gate transistor (SGT) as its gate structure wraps around each of the channel members (or channel structures). An MBC transistor may also be referred to as nanosheet transistor or a nanowire transistor because each of the bridge-like channel members is nanoscale and may resemble a wire or a sheet. Referring now toFIG. 1, the first semiconductor device100-1includes a plurality of channel members108extending along the X direction between two p-type source/drain features116P. A gate structure110that extends lengthwise along the Y direction wraps around each of the plurality of channel members108. The Y direction is perpendicular to the X direction. As shown inFIG. 1, the gate structure110includes a gate dielectric layer112and a gate electrode114. The gate structure110is isolated from the p-type source/drain features116P by a plurality of inner spacer features118. A source/drain contact120is disposed over and electrically coupled to each of the p-type source/drain features116P. In some implementations represented inFIG. 1, the source/drain contact120includes a barrier layer122and a metal fill layer124.

In some embodiments, the channel members108may include a semiconductor material, such as silicon, germanium, or silicon germanium. The gate dielectric layer112may include an interfacial layer and a high-k dielectric layer. In some embodiments, the interfacial layer may include a dielectric material such as silicon oxide layer or silicon oxynitride. The high-k dielectric layer is formed of a high-k (dielectric constant greater than about 3.9) dielectric material that may include hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium oxide, zirconium silicon oxide, combinations thereof, or other suitable materials. The gate electrode114may include one or more work function layers and a metal fill layer. The one or more work function layers may include n-type work function layers and p-type work function layers. Example n-type work function layers may be formed of aluminum, titanium aluminide, titanium aluminum carbide, tantalum silicon carbide, tantalum silicon aluminum, tantalum silicon carbide, tantalum silicide, or hafnium carbide. Example p-type work function layers may be formed of titanium nitride, titanium silicon nitride, tantalum nitride, tungsten carbonitride, or molybdenum. The metal fill layer may be formed of a metal, such as tungsten (W), ruthenium (Ru), cobalt (Co) or copper (Cu). The p-type source/drain feature116P may be an epitaxial feature that includes a semiconductor material such as silicon germanium and is doped with a p-type dopant, such as boron (B).

The gate structure110, the p-type source/drain features116P, and the bottommost inner spacer features118are disposed on an n-type well region102N. In some implementations, the n-type well region102N is doped with an n-type dopant such as phosphorus (P) or arsenide (As) and has a first doping concentration between about 1×1018and about 5×1018atoms/cm2. The n-type well region102N is disposed over and electrically coupled to a backside conductive feature130. In some embodiments, the backside conductive feature130may be a power rail that is coupled to Vdd (i.e., positive supply voltage) or Vss (i.e., ground or negative supply voltage). To reduce contact resistance between the n-type well region102N and the backside conductive feature130, the first semiconductor device100-1further includes a first epitaxial layer126-1and a silicide layer128. In some implementations, the first epitaxial layer126-1is epitaxially grown on the n-type well region102N is thus disposed directly on the n-type well region102N. The silicide layer128interposes between the first epitaxial layer126-1and the backside conductive feature130. In some embodiments, the first epitaxial layer126-1is doped in-situ with an n-type dopant, such as phosphorus (P) or arsenide (As), and has a second doping concentration between about 1×1019and about 1×1020atoms/cm2. The second doping concentration is greater than the first doping concentration such that the first epitaxial layer126-1has increased conductivity. The silicide layer128may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN). The backside conductive feature130may be formed of tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu).

As shown inFIG. 1, measured from a bottommost inner spacer feature118, the n-type well region102N and the first epitaxial layer126-1may collectively have a first thickness T1along the Z direction. In some instances, the first thickness T1may be between about 30 nm and about 150 nm. In some implementations, the silicide layer128may have a second thickness T2along the Z direction. The second thickness T2may be between about 3 nm and about 5 nm.

Reference is now made toFIG. 2, which illustrates a cross-sectional view of the first semiconductor device100-1along the X direction. The n-type well region102N is defined in an isolation feature132. It is noted that the isolation feature132is not shown inFIG. 1as the cross-sectional plane ofFIG. 1does not cut through the isolation feature132. The n-type well region102N is formed from a substrate and the isolation feature132is disposed over the substrate. The structure shown inFIG. 2is formed after planarizing the substrate using for example, a chemical mechanical polishing (CMP) process, until a bottom surface of the n-type well region102N is coplanar with bottom surfaces of the isolation feature132. After the planar bottom surface is formed, the n-type well region102N is recessed to form a backside recess. The first epitaxial layer126-1is epitaxially grown over the exposed surface of the n-type well region102N and the silicide layer128is formed over the first epitaxial layer126-1. After a planarization process, such as a CMP process, a dielectric layer134is deposited over the isolation feature132and the silicide layer128. An opening is then formed in the dielectric layer134by use of lithography processes and etch processes to expose the silicide layer128. Thereafter, the backside conductive feature130is deposited over the silicide layer128. Another planarization process, such as a CMP process, may be performed to planarize the bottom surface such that the bottom surface of the backside conductive feature130and the top surface of the dielectric layer134are coplanar. As a result, the backside conductive feature130is disposed within the dielectric layer134. The first epitaxial layer126-1and the silicide layer128are disposed within the isolation feature132. It can be seen fromFIGS. 1 and 2that the n-type well region102N extends lengthwise along the X direction and may be regarded as an elongated semiconductor member that is doped with an n-type dopant. It is noted that the term “bottom” is used to refer to features inFIG. 2as shown and does not in any way suggest or imply the orientation of the substrate during the fabrication processes. Some of the processes described here may be performed when the first semiconductor device100-1is turned upside down.

In some embodiments, the isolation feature132may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. The isolation feature132may also be referred to as a shallow trench isolation (STI) feature132. The dielectric layer134may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials.

In some embodiments illustrated inFIG. 1, although the first semiconductor device100-1includes structures of a transistor, it does not function as one and is not electrically connected as one. As shown inFIG. 1, the gate structure110of the first semiconductor device100-1is electrically floating and is not configured to turn on the channel members108. The source/drain contacts120may be resistively coupled to a first node202and the backside conductive feature130is resistively coupled to a second node204. When connected as such, the first semiconductor device100-1may function as two parallel PN junction diodes—first PN junction diode302and the second PN junction diode304, shown in a first equivalent circuit200-1inFIG. 3. Each of the first PN junction diode302and the second PN junction diode304corresponds to one of the p-type source/drain feature116P over and in contact with the n-type well region102N.

FIG. 4illustrates a fragmentary cross-sectional view of a second semiconductor device100-2along the Y direction. In some embodiments represented inFIG. 4, the second semiconductor device100-2has a structure similar to an MBC transistor that includes a plurality of bridge-like channel members (or channel structures). An MBC transistor may be referred to as a gate-all-around (GAA) transistor or a surrounding gate transistor (SGT) as its gate structure wraps around each of the channel members (or channel structures). An MBC transistor may also be referred to as nanosheet transistor or a nanowire transistor because each of the bridge-like channel members is nanoscale and may resemble a wire or a sheet. Referring now toFIG. 4, the second semiconductor device100-2includes a plurality of channel members108extending along the X direction between two n-type source/drain features116N. A gate structure110that extends lengthwise along the Y direction wraps around each of the plurality of channel members108. As shown inFIG. 4, the gate structure110includes a gate dielectric layer112and a gate electrode114. The gate structure110is isolated from the n-type source/drain features116N by a plurality of inner spacer features118. A source/drain contact120is disposed over and electrically coupled to each of the n-type source/drain features116N. In some implementations represented inFIG. 4, the source/drain contact120includes a barrier layer122and a metal fill layer124.

The channel members108, the gate dielectric layer112, gate electrode114, the inner spacer features118, the source/drain contact120of the second semiconductor device100-2may be similar to those of the first semiconductor device100-1shown inFIG. 1. Detailed descriptions of them are therefore omitted for brevity.

The gate structure110, the n-type source/drain features116N, and the bottommost inner spacer features118are disposed on a p-type well region102P. In some implementations, the p-type well region102P is doped with a p-type dopant such as boron (B) and has a third doping concentration between about 1×1018and about 5×1018atoms/cm2. The p-type well region102P is disposed over and electrically coupled to a backside conductive feature130. In some embodiments, the backside conductive feature130may be a power rail that is coupled to Vdd (i.e., positive supply voltage) or Vss (i.e., ground or negative supply voltage). To reduce contact resistance between the p-type well region102P and the backside conductive feature130, the semiconductor device100-2further includes a second epitaxial layer126-2and a silicide layer128. In some implementations, the second epitaxial layer126-2is epitaxially grown on the p-type well region102P is thus disposed directly on the p-type well region102P. The silicide layer128interposes between the second epitaxial layer126-2and the backside conductive feature130. In some embodiments, the second epitaxial layer126-2is doped in-situ with a p-type dopant, such as boron (B), and has a fourth doping concentration between about 1×1019and about 1×1020atoms/cm2. The silicide layer128may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN). The backside conductive feature130may be formed of tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu).

Reference is now made toFIG. 5, which illustrates a cross-sectional view of the second semiconductor device100-2along the X direction. The p-type well region102P is defined in an isolation feature132. It is noted that the isolation feature132is not shown inFIG. 4as the cross-sectional plane ofFIG. 4does not cut through the isolation feature132. The p-type well region102P is formed from a substrate and the isolation feature132is disposed over the substrate. The structure shown inFIG. 5is formed after planarizing the substrate using for example, a chemical mechanical polishing (CMP) process, until a bottom surface of the p-type well region102P is coplanar with bottom surfaces of the isolation feature132. After the planar bottom surface is formed, the p-type well region102P is recessed to form a backside recess. The second epitaxial layer126-2is epitaxially grown over the exposed surface of the p-type well region102P and the silicide layer128is formed over the second epitaxial layer126-2. After a planarization process, such as a CMP process, a dielectric layer134is deposited over the isolation feature132and the silicide layer128. An opening is then formed in the dielectric layer134by use of lithography processes and etch processes to expose the silicide layer128. Thereafter, the backside conductive feature130is deposited over the silicide layer128. Another planarization process, such as a CMP process, may be performed to planarize the bottom surface such that the bottom surface of the backside conductive feature130and the top surface of the dielectric layer134are coplanar. As a result, the backside conductive feature130is disposed within the dielectric layer134. The second epitaxial layer126-2and the silicide layer128are disposed within the isolation feature132. After the planar bottom surface is formed, a dielectric layer134is deposited over the isolation feature132and the p-type well region102P. An opening is then formed in the dielectric layer134by use of lithography processes and etch processes to expose the p-type well region102P. The second epitaxial layer126-2is subsequently epitaxially grown over the exposed surface of the p-type well region102P. The silicide layer128is formed over the second epitaxial layer126-2. Thereafter, the backside conductive feature130is deposited over the silicide layer128. A planarization process, such as a chemical mechanical polishing (CMP) process, may be performed to planarize the bottom surface such that the bottom surface of the backside conductive feature130and the top surface of the dielectric layer134are coplanar. As a result, the dielectric layer134is in contact with sidewalls of the second epitaxial layer126-2, the silicide layer128, and the backside conductive feature130. Put differently, the second epitaxial layer126-2, the silicide layer128, and the backside conductive feature130are disposed within the dielectric layer134. It can be seen fromFIGS. 4 and 5that the p-type well region102P extends lengthwise along the X direction and may be regarded as an elongated semiconductor member that is doped with a p-type dopant. It is noted that the term “bottom” is used to refer to features inFIG. 5as shown and does not in any way suggest or imply the orientation of the substrate during the fabrication processes. Some of the processes described here may be performed when the second semiconductor device100-2is turned upside down.

The isolation feature132and the dielectric layer134of the second semiconductor device100-2may be similar to those of the first semiconductor device100-1shown inFIG. 1. Detailed descriptions of them are therefore omitted for brevity.

In some embodiments illustrated inFIG. 4, although the second semiconductor device100-2includes structures of a transistor, it does not function as one and is not connected as one. As shown inFIG. 4, the gate structure110is electrically floating and is not configured to turn on channel members108. The source/drain contacts120may be resistively coupled to a third node206and the backside conductive feature130is resistively coupled to a fourth node208. When connected as such, the second semiconductor device100-2may function as two parallel PN junction diodes—third PN junction diode306and the fourth PN junction diode308, shown in a second equivalent circuit200-2inFIG. 6. Each of the third PN junction diode306and the fourth PN junction diode308corresponds to one of the n-type source/drain feature116N over and in contact with the p-type well region102P.

FIG. 7illustrates a fragmentary cross-sectional view of a third semiconductor device100-3along the Y direction. In some embodiments represented inFIG. 7, the third semiconductor device100-3has a structure similar to an MBC transistor that includes a plurality of bridge-like channel members (or channel structures). An MBC transistor may be referred to as a gate-all-around (GAA) transistor or a surrounding gate transistor (SGT) as its gate structure wraps around each of the channel members (or channel structures). An MBC transistor may also be referred to as nanosheet transistor or a nanowire transistor because each of the bridge-like channel members is nanoscale and may resemble a wire or a sheet. Referring now toFIG. 7, the third semiconductor device100-3includes a plurality of channel members108extending along the X direction between a p-type source feature116PS and an n-type drain feature116ND. A gate structure110that extends lengthwise along the Y direction wraps around each of the plurality of channel members108. As shown inFIG. 7, the gate structure110includes a gate dielectric layer112and a gate electrode114. The gate structure110is isolated from the p-type source features116PS and the n-type drain feature116ND by a plurality of inner spacer features118. A source/drain contact120is disposed over and electrically coupled to each of the p-type source feature116PS and the n-type drain feature116ND. In some implementations represented inFIG. 7, the source/drain contact120includes a barrier layer122and a metal fill layer124.

The channel members108, the gate dielectric layer112, gate electrode114, the inner spacer features118, the source/drain contact120of the third semiconductor device100-3may be similar to those of the first semiconductor device100-1shown inFIG. 1. Detailed descriptions of them are therefore omitted for brevity.

The gate structure110, the p-type source feature116PS, the n-type drain feature116ND and the bottommost inner spacer features118are disposed on a p-type well region102P. In some implementations, the p-type well region102P is doped with a p-type dopant such as boron (B) and has the first doping concentration between about 1×1018and about 5×1018atoms/cm2. The p-type well region102P is disposed over and electrically coupled to a backside conductive feature130. In some embodiments, the backside conductive feature130may be a power rail that is coupled to Vdd (i.e., positive supply voltage) or Vss (i.e., ground or negative supply voltage). To reduce contact resistance between the p-type well region102P and the backside conductive feature130, the third semiconductor device100-3further includes the second epitaxial layer126-2and the silicide layer128. In some implementations, the second epitaxial layer126-2is epitaxially grown on the p-type well region102P is thus disposed directly on the p-type well region102P. The silicide layer128interposes between the second epitaxial layer126-2and the backside conductive feature130. In some embodiments, the second epitaxial layer126-2is doped in-situ with a p-type dopant, such as boron (B), and has a fourth doping concentration between about 1×1019and about 1×1020atoms/cm2. As compared to the p-type well region102P, the p-type source feature116PS is more heavily doped. In some instances, the p-type source feature116PS may also be doped at the fourth doping concentration. The silicide layer128may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN). The backside conductive feature130may be formed of tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu).

Reference is now made toFIG. 8, which illustrates a cross-sectional view of the third semiconductor device100-3along the X direction. The p-type well region102P is defined in an isolation feature132. It is noted that the isolation feature132is not shown inFIG. 7as the cross-sectional plane ofFIG. 7does not cut through the isolation feature132. The p-type well region102P is formed from a substrate and the isolation feature132is disposed over the substrate. The structure shown inFIG. 8is formed after planarizing the substrate using for example, a chemical mechanical polishing (CMP) process, until a bottom surface of the p-type well region102P is coplanar with bottom surfaces of the isolation feature132. After the planar bottom surface is formed, the p-type well region102P is recessed to form a backside recess. The second epitaxial layer126-2is epitaxially grown over the exposed surface of the p-type well region102P and the silicide layer128is formed over the second epitaxial layer126-2. After a planarization process, such as a CMP process, a dielectric layer134is deposited over the isolation feature132and the silicide layer128. Thereafter, the backside conductive feature130is deposited over the silicide layer128. Another planarization process, such as a CMP process, may be performed to planarize the bottom surfaces such that the bottom surface of the backside conductive feature130and the top surface of the dielectric layer134are coplanar. As a result, the backside conductive feature130is disposed within the dielectric layer134. The second epitaxial layer126-2and the silicide layer128are disposed within the isolation feature132. It can be seen fromFIGS. 7 and 8that the p-type well region102P extends lengthwise along the X direction and may be regarded as an elongated semiconductor member that is doped with a p-type dopant. It is noted that the term “bottom” is used to refer to features inFIG. 8as shown and does not in any way suggest or imply the orientation of the substrate during the fabrication processes. Some of the processes described here may be performed when the third semiconductor device100-3is turned upside down.

The isolation feature132and the dielectric layer134of the third semiconductor device100-3may be similar to those of the first semiconductor device100-1shown inFIG. 1. Detailed descriptions of them are therefore omitted for brevity.

In some embodiments illustrated inFIG. 7, although the third semiconductor device100-3includes structures of a transistor, it does not function as one and is not connected as one. As shown inFIG. 7, the gate structure110is electrically floating and is not configured to turn on the channel members108. The source/drain contact120over the n-type drain feature116ND may be resistively coupled to a fifth node210and the source/drain contact120over p-type source feature116PS and the backside conductive feature130may be resistively coupled together to a sixth node212. When connected as such, the third semiconductor device100-3may be representatively and functionally shown as a third equivalent circuit200-3inFIG. 9. The third equivalent circuit200-3includes a fifth PN junction diode310and a sixth PN junction diode312that are connected in parallel. The fifth PN junction diode310corresponds to the n-type drain feature116ND over and in contact with the p-type well region102P and the sixth PN junction diode312corresponds to the p-type source feature116PS coupled to the n-type drain feature116ND by way of the channel members108.

FIG. 10illustrates a fragmentary cross-sectional view of a fourth semiconductor device100-4along the Y direction. In some embodiments represented inFIG. 10, the fourth semiconductor device100-4has a structure similar to a multi-bridge-channel (MBC) transistor that includes a plurality of bridge-like channel members (or channel structures). An MBC transistor may be referred to as a gate-all-around (GAA) transistor or a surrounding gate transistor (SGT) as its gate structure wraps around each of the channel members (or channel structures). An MBC transistor may also be referred to as nanosheet transistor or a nanowire transistor because each of the bridge-like channel members is nanoscale and may resemble a wire or a sheet. Referring now toFIG. 10, the fourth semiconductor device100-4includes a plurality of channel members108extending along the X direction between an n-type source feature116NS and a p-type drain feature116PD. A gate structure110that extends lengthwise along the Y direction wraps around each of the plurality of channel members108. As shown inFIG. 10, the gate structure110includes a gate dielectric layer112and a gate electrode114. The gate structure110is isolated from the n-type source features116NS and the p-type drain feature116PD by a plurality of inner spacer features118. A source/drain contact120is disposed over and electrically coupled to each of the n-type source feature116NS and the p-type drain feature116PD. In some implementations represented inFIG. 10, the source/drain contact120includes a barrier layer122and a metal fill layer124.

The channel members108, the gate dielectric layer112, gate electrode114, the inner spacer features118, the source/drain contact120of the fourth semiconductor device100-4may be similar to those of the first semiconductor device100-1shown inFIG. 1. Detailed descriptions of them are therefore omitted for brevity.

The gate structure110, the n-type source feature116NS, the p-type drain feature116PD and the bottommost inner spacer features118are disposed on an n-type well region102N. In some implementations, the n-type well region102N is doped with an n-type dopant such as phosphorus (P) or arsenide (As) and has the first doping concentration between about 1×1018and about 5×1018atoms/cm2. The n-type well region102N is disposed over and electrically coupled to a backside conductive feature130. In some embodiments, the backside conductive feature130may be a power rail that is coupled to Vdd (i.e., positive supply voltage) or Vss (i.e., ground or negative supply voltage). To reduce contact resistance between the n-type well region102N and the backside conductive feature130, the fourth semiconductor device100-4further includes the first epitaxial layer126-1and the silicide layer128. In some implementations, the first epitaxial layer126-1is epitaxially grown on the n-type well region102N is thus disposed directly on the n-type well region102N. The silicide layer128interposes between the first epitaxial layer126-1and the backside conductive feature130. In some embodiments, the first epitaxial layer126-1is doped in-situ with an n-type dopant, such as phosphorus (P) or arsenide (As), and has a second doping concentration between about 1×1019and about 1×1020atoms/cm2. The silicide layer128may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN). The backside conductive feature130may be formed of tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu).

Reference is now made toFIG. 11, which illustrates a cross-sectional view of the fourth semiconductor device100-4along the X direction. The n-type well region102N is defined in an isolation feature132. It is noted that the isolation feature132is not shown inFIG. 10as the cross-sectional plane ofFIG. 10does not cut through the isolation feature132. The n-type well region102N is formed from a substrate and the isolation feature132is disposed over the substrate. The structure shown inFIG. 11is formed after planarizing the substrate using for example, a chemical mechanical polishing (CMP) process, until a bottom surface of the n-type well region102N is coplanar with bottom surfaces of the isolation feature132. After the planar bottom surface is formed, the n-type well region102N is recessed to form a backside recess. The first epitaxial layer126-1is epitaxially grown over the exposed surface of the n-type well region102N and the silicide layer128is formed over the first epitaxial layer126-1. After a planarization process, such as a CMP process, a dielectric layer134is deposited over the isolation feature132and the silicide layer128. An opening is then formed in the dielectric layer134by use of lithography processes and etch processes to expose the silicide layer128. Thereafter, the backside conductive feature130is deposited over the silicide layer128. Another planarization process, such as a CMP process, may be performed to planarize the bottom surface such that the bottom surface of the backside conductive feature130and the top surface of the dielectric layer134are coplanar. As a result, the backside conductive feature130is disposed within the dielectric layer134. The first epitaxial layer126-1and the silicide layer128are disposed within the isolation feature132. It can be seen fromFIGS. 10 and 11that the n-type well region102N extends lengthwise along the X direction and may be regarded as an elongated semiconductor member that is doped with an n-type dopant. It is noted that the term “bottom” is used to refer to features inFIG. 11as shown and does not in any way suggest or imply the orientation of the substrate during the fabrication processes. Some of the processes described here may be performed when the fourth semiconductor device100-4is turned upside down.

The isolation feature132and the dielectric layer134of the fourth semiconductor device100-4may be similar to those of the first semiconductor device100-1shown inFIG. 1. Detailed descriptions of them are therefore omitted for brevity.

In some embodiments illustrated inFIG. 10, although the fourth semiconductor device100-4includes structures of a transistor, it does not function as one and is not connected as one. As shown inFIG. 10, the gate structure110is electrically floating and is not configured to turn on the channel members108. The source/drain contact120over the p-type drain feature116PD may be resistively coupled to a seventh node214and the source/drain contact120over the n-type source feature116NS and the backside conductive feature130may be resistively coupled together to an eighth node216. When connected as such, the fourth semiconductor device100-4may representatively and functionally shown as a fourth equivalent circuit200-4inFIG. 12. The fourth equivalent circuit200-4includes a seventh PN junction diode314and an eighth PN junction diode316that are connected in parallel. The seventh PN junction diode314corresponds to the p-type drain feature116PD over and in contact with the n-type well region102N and the eighth PN junction diode316corresponds to the p-type drain feature116PD coupled to the n-type source feature116NS by way of the channel members108.

FIG. 13illustrates a fragmentary cross-sectional view of a fifth semiconductor device100-5along the Y direction. In some embodiments represented inFIG. 13, the fifth semiconductor device100-5is an MBC transistor that includes a plurality of bridge-like channel members (or channel structures). An MBC transistor may be referred to as a gate-all-around (GAA) transistor or a surrounding gate transistor (SGT) as its gate structure wraps around each of the channel members (or channel structures). An MBC transistor may also be referred to as nanosheet transistor or a nanowire transistor because each of the bridge-like channel members is nanoscale and may resemble a wire or a sheet. Referring now toFIG. 13, the fifth semiconductor device100-5includes a plurality of channel members108extending along the X direction between a p-type source features116PS and a p-type drain feature116PD. A gate structure110that extends lengthwise along the Y direction wraps around each of the plurality of channel members108. As shown inFIG. 13, the gate structure110includes a gate dielectric layer112and a gate electrode114. The gate structure110is isolated from the p-type source features116PS and the p-type drain feature116PD by a plurality of inner spacer features118. A source/drain contact120is disposed over and electrically coupled to each of the p-type source feature116PS and the p-type drain feature116PD. In some implementations represented inFIG. 13, the source/drain contact120includes a barrier layer122and a metal fill layer124.

The channel members108, the gate dielectric layer112, gate electrode114, the inner spacer features118, the source/drain contact120of the fifth semiconductor device100-5may be similar to those of the first semiconductor device100-1shown inFIG. 1. Detailed descriptions of them are therefore omitted for brevity.

In some embodiments illustrated inFIG. 13, the fifth semiconductor device100-5includes a backside source contact via138that couples the p-type source feature116PS to a backside conductive feature130. To reduce contact resistance between the p-type source feature116PS and the backside source contact via138, the fifth semiconductor device100-5further includes a silicide feature1280. The bottommost inner spacer features118, the gate structure110, and the p-type drain feature116PD are disposed over a filler dielectric layer136. The silicide feature1280may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN). The backside source contact via138may be formed of tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu). The filler dielectric layer136may have a composition similar to that of the dielectric layer134. In some instances, the filler dielectric layer136may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials.

In some embodiments illustrated inFIG. 13, the fifth semiconductor device100-5functions as a transistor and is electrically connected as one. As shown inFIG. 13, the gate structure110of the fifth semiconductor device100-5is resistively coupled to a first gate node218, the p-type source feature116PS is resistively coupled to a first source node220, and the p-type drain feature116PD is resistively coupled to a first drain node222. When connected as such, the fifth semiconductor device100-5may be represented as a fifth equivalent circuit200-5inFIG. 14. In some instances, the fifth equivalent circuit200-5includes a p-type transistor318.

FIG. 15illustrates a fragmentary cross-sectional view of a sixth semiconductor device100-6along the Y direction. In some embodiments represented inFIG. 15, the sixth semiconductor device100-6is an MBC transistor that includes a plurality of bridge-like channel members (or channel structures). An MBC transistor may be referred to as a gate-all-around (GAA) transistor or a surrounding gate transistor (SGT) as its gate structure wraps around each of the channel members (or channel structures). An MBC transistor may also be referred to as nanosheet transistor or a nanowire transistor because each of the bridge-like channel members is nanoscale and may resemble a wire or a sheet. Referring now toFIG. 15, the sixth semiconductor device100-6includes a plurality of channel members108extending along the X direction between an n-type source features116NS and an n-type drain feature116ND. A gate structure110that extends lengthwise along the Y direction wraps around each of the plurality of channel members108. As shown inFIG. 15, the gate structure110includes a gate dielectric layer112and a gate electrode114. The gate structure110is isolated from the n-type source features116NS and the n-type drain feature116ND by a plurality of inner spacer features118. A source/drain contact120is disposed over and electrically coupled to each of the n-type source feature116NS and the n-type drain feature116ND. In some implementations represented inFIG. 15, the source/drain contact120includes a barrier layer122and a metal fill layer124.

The channel members108, the gate dielectric layer112, gate electrode114, the inner spacer features118, the source/drain contact120of the sixth semiconductor device100-6may be similar to those of the first semiconductor device100-1shown inFIG. 1. Detailed descriptions of them are therefore omitted for brevity.

In some embodiments illustrated inFIG. 15, the sixth semiconductor device100-6includes a backside source contact via138that couples the n-type source feature116NS to a backside conductive feature130. To reduce contact resistance between the n-type source feature116NS and the backside source contact via138, the sixth semiconductor device100-6further includes a silicide feature1280. The bottommost inner spacer features118, the gate structure110, and the n-type drain feature116ND are disposed over a filler dielectric layer136. The silicide feature1280may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN). The backside source contact via138may be formed of tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu). The filler dielectric layer136may have a composition similar to that of the dielectric layer. In some instances, the filler dielectric layer136may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials.

In some embodiments illustrated inFIG. 15, the sixth semiconductor device100-6functions as a transistor and is electrically connected as one. As shown inFIG. 15, the gate structure110of the sixth semiconductor device100-6is resistively coupled to a second gate node224, the n-type source feature116NS is resistively coupled to a second source node226, and the n-type drain feature116ND is resistively coupled to a second drain node228. When connected as such, the sixth semiconductor device100-6may be represented in a sixth equivalent circuit200-6inFIG. 16. In some instances, the sixth equivalent circuit200-6includes an n-type transistor320.

Reference is now made toFIG. 17. One or more of the first semiconductor device100-1, the second semiconductor device100-2, the third semiconductor device100-3, the fourth semiconductor device100-4, the fifth semiconductor device100-5, and the sixth semiconductor device100-6may be fabricated on a substrate to form an integrated circuit (IC) device1000to perform various functions according to various design needs. In some instances when more than one of the first semiconductor device100-1, the second semiconductor device100-2, the third semiconductor device100-3, the fourth semiconductor device100-4, the fifth semiconductor device100-5, and the sixth semiconductor device100-6are fabricated on the same substrate, they may share the same backside conductive feature130, as illustrated inFIGS. 1, 4, 7, 10, 13, and15. Although the first semiconductor device100-1, the second semiconductor device100-2, the third semiconductor device100-3, the fourth semiconductor device100-4, the fifth semiconductor device100-5, and the sixth semiconductor device100-6all share similar MBC-transistor-like structures, the first semiconductor device100-1, the second semiconductor device100-2, the third semiconductor device100-3, and the fourth semiconductor device100-4offer various PN junction diode structures to meet different circuit design needs. When an IC design that includes only transistors and PN junction diodes, the IC design can be fully implemented using the semiconductor devices of the present disclosure. When an IC design that includes transistors, PN junction diodes and other active/passive devices, the number of similarly structured device can be increased by adopting the semiconductor devices of the present disclosure. Due to their structural similarities, adoption of the MBC transistors and PN junction diodes of the present disclosure can streamline fabrication processes and reduce loading-dependent defects.

In one example aspect, the present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, the elongated semiconductor member including a top surface and an opposing bottom surface, a first source/drain feature and a second source/drain feature over the top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the vertical stack of channel members, a silicide layer underlying the elongated semiconductor member, and a conductive layer disposed on the silicide layer.

In some embodiments, the semiconductor device may further include an epitaxial layer disposed between the elongated semiconductor member and the silicide layer. In some embodiments, the elongated semiconductor member and the epitaxial layer are doped with the same type of dopant and a doping concentration of the epitaxial layer is greater than a doping concentration of the elongated semiconductor member. In some implementations, the elongated semiconductor member is doped by at least one dopant of a first type, the first source/drain feature is doped by at least one dopant of a second type, the second source/drain feature is doped by at least one dopant of a third type, and the first type is different from at least one of the second type and the third type. In some implementations, the second type is different from the third type. In some instances, the second type is the same as the third type. In some embodiments, the gate structure is electrically floating. In some implementations, the first source/drain feature is resistively coupled to the second source/drain feature. In some instances, the first source/drain feature is resistively coupled to the conductive layer.

Another one aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a well region extending lengthwise along a direction and being disposed in an isolation feature, a first source/drain feature and a second source/drain feature over the well region, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the direction, a gate structure wrapping around each of the vertical stack of channel members, an epitaxial layer below the well region, a silicide layer below and in contact with the epitaxial layer, and a conductive layer below and in contact with the silicide layer.

In some embodiments, the gate structure is electrically floating. In some implementations, the first source/drain feature is resistively coupled to the second source/drain feature. In some embodiments, the first source/drain feature and the second source/drain feature are doped with a first type dopant. In some implementations, the well region is doped with a second type dopant different from the first type dopant. In some instances, the first source/drain feature is resistively coupled to the conductive layer. In some embodiments, the first source/drain feature is doped with a first type dopant and the second source/drain feature is doped with a second type dopant different from the first type dopant.

Yet another aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a transistor and a PN junction diode structure. The transistor includes a first conductive layer, a dielectric layer over the first conductive layer, a backside contact via extending through the dielectric layer, a silicide feature disposed on the backside contact via, a source feature disposed on and in contact with the silicide feature, a drain feature disposed on the dielectric layer and insulated from the first conductive layer, a first plurality of channel members each extending lengthwise between the source feature and the drain feature, and a first gate structure wrapping around each of the channel members and extending lengthwise along a first direction. The PN junction diode structure includes a second conductive layer, a silicide layer disposed on the second conductive layer, an epitaxial layer disposed on the silicide layer, an elongated semiconductor member disposed on the epitaxial layer and extending lengthwise along a second direction perpendicular to the first direction, a first source/drain feature and a second source/drain feature over the elongated semiconductor member, a second plurality of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature, and a second gate structure wrapping around each of the channel members and extending lengthwise along the first direction.

In some embodiments, the elongated semiconductor member and the epitaxial layer are doped with the same type of dopant and a doping concentration of the epitaxial layer is greater than a doping concentration of the elongated semiconductor member. In some implementations, the first source/drain feature is resistively coupled to the second conductive layer. In some instances, the second gate structure is electrically floating.