Scalable interface for a memory array

A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests.

BACKGROUND

This disclosure relates generally to a memory array and, more specifically, to a scalable interface for a memory array.

2. Related Art

Traditionally, memory array libraries have been created that include memory arrays with a different number of physical read and write ports. For example, a standard memory array library may include: a first memory array having one read port and one write port; a second memory array having two read ports and one write port; a third memory array having one read port and two write ports; and a fourth memory array having two read ports and two write ports. In this case, when a new application has required a memory array with more that two read ports or two write ports, a new custom memory array has generally been designed for the new application. Unfortunately, designing a custom memory array that supports a desired number of simultaneous memory accesses can be time-consuming and relatively expensive.

To avoid the expense associated with designing a custom memory array, at least some designers have selected an existing memory array (that does not include a desired number of physical read or write ports) from a memory array library and designed collision avoidance logic to facilitate access to the memory array (by multiple requesters) via a shared port of the memory array. In this case, a handshaking protocol (that indicates read and/or write completion) has been employed in conjunction with the collision avoidance logic to allow different requesters to access the memory array using the shared port (e.g., a read port and/or a write port). Unfortunately, the collision avoidance approach only facilitates sequential port access and generally exhibits non-fixed timing for accesses (e.g., an initial read may take four cycles and subsequent reads may take more or less than four cycles) and may adversely affect memory array function, as well as memory array performance. To avoid the expense associated with designing a custom memory array, at least some designers have implemented redundant memory arrays to provide simultaneous access to information associated with a single port of a memory array to multiple requestors. However, implementation of redundant memory arrays increases an area of an associated integrated circuit (IC) and also requires implementation of a coherency scheme to ensure that the same information is maintained in the redundant memory arrays.

SUMMARY

According to one aspect of the present disclosure, a method of accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests.

According to another aspect of the present disclosure, a memory includes a memory array and an interface coupled to the memory array. The interface includes a first circuit that is configured to receive, from multiple requesters, memory access requests directed to a single port of the memory array. A first portion of the interface is clocked with a first clock signal, a second portion of the interface is clocked with a second clock signal, and the memory array is clocked with the second clock signal. A frequency of the second clock signal is higher than a frequency of the first clock signal and the memory access requests have a fixed timing.

According to one embodiment of the present disclosure, a technique for accessing a memory includes receiving, at an interface, memory access requests directed to a single port of a memory array. In this case, the memory access requests are each associated with multiple requestors. The memory access requests associated with each of the multiple requesters are serviced. A first portion of the interface is clocked with a first clock signal, a second portion of the interface is clocked with a second clock signal, and the memory array is clocked with the second clock signal. A frequency of the second clock signal is higher than a frequency of the first clock signal and the memory access requests have a fixed timing.

DETAILED DESCRIPTION

As will be appreciated by one of ordinary skill in the art, the present invention may be embodied as a method, system, device, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module,” or “system.” For example, the present invention may take the form of one or more design files included on a computer-usable storage medium.

Any suitable computer-usable or computer-readable storage medium may be utilized. The computer-usable or computer-readable storage medium may be, for example, but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or Flash memory, a portable compact disc read-only memory (CD-ROM), an optical storage device, or a magnetic storage device. Note that the computer-usable or computer-readable storage medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory. In the context of this disclosure, a computer-usable or computer-readable storage medium may be any medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. As used herein, the term “coupled” includes both a direct electrical connection between blocks or components and an indirect electrical connection between blocks or components achieved using intervening blocks or components.

According to various aspects of the present disclosure, a memory array interface is described herein that is scalable and that maintains fixed and ascertainable timings (i.e., read and/or write latency can be readily determined) while providing multiple requesters access to a single read port or a single write port of a memory array, irrespective of the number of the multiple requesters. While the memory array described herein includes two read ports and two write ports, it should be appreciated that the disclosed techniques are applicable to memory arrays having more or less than two read ports and more or less than two write ports. Moreover, the disclosed techniques are broadly applicable to a wide variety of memory arrays, such as embedded dynamic random access memory (EDRAM), synchronous dynamic random access memory (SDRAM), and register arrays. Furthermore, a memory array interface configured according to the present disclosure may be employed in various devices, such as an application specific integrated circuit (ASIC), a processor, or a memory controller. According to various aspects of the present disclosure, a memory array interface is disclosed that facilitates multiple requesters accessing a single port of a memory array while maintaining fixed ascertainable timings.

According to one embodiment, the multiple requesters are divided into primary requesters and secondary requesters. When the memory array is incorporated within a memory controller, the primary requestor(s) may correspond to, for example, main memory and the secondary requestor(s) may correspond to, for example, a joint test action group (JTAG) interface. A memory array interface and associated memory array may be, for example, integrated in a Northbridge. In one disclosed embodiment, each physical port of a memory array has four associated virtual ports (i.e., two primary ports and two secondary ports). In this case, one of the primary ports may be accessed on a high pulse of a clock1signal cycle and the remaining one of the primary ports may be accessed on a low pulse of the clock1signal cycle. Similarly, one of the secondary ports may be accessed on a high pulse of a clock1signal cycle and the remaining one of the secondary ports may be accessed on a low pulse of the clock1signal cycle. In general, additional requesters may be added by including one or more additional buffers. For example, in the disclosed embodiment, each additional four requesters for a given port requires an additional clocked buffer.

In at least one embodiment, information (read addresses or write addresses and write data) is provided by the multiple requesters according to the clock1signal, which in one embodiment has a frequency that is one-half the frequency of a clock2signal that clocks memory elements of a memory array. For example, a frequency of the clock2signal may be 400 MHz and a frequency of the clock1signal may be 200 MHz. It should be appreciated that the clock1and clock2signal frequencies may have a different relationship, depending upon the structure of the memory array interface. For example, four requesters may be serviced by each port of a memory array by providing a clock2signal frequency that is two times a clock1signal frequency, eight requesters may be serviced by each port of a memory array by providing a clock2signal frequency that is four times a clock1signal frequency, and twelve requesters may be serviced by each port of a memory array by providing a clock2signal frequency that is eight times a clock1signal frequency.

With reference toFIG. 1, a relevant portion of an example read section100of a memory array interface is illustrated. The read section100is essentially a prioritized pipeline. As is shown, read addresses (i.e., P0P1_RA, P1P1_RA, S0P1_RA, and S1P1_RA) for four requesters (i.e., P0P1, P1P1, S0P1, and S1P1) are provided to a first port (P1) of a memory array102. It should be appreciated that a width of a read address line depends on the number of memory elements (ME) that are to be accessed. For example, assuming that thirty-two memory elements are implemented, five read address lines may be employed (25=32). In one embodiment, two-stage latches or clocked buffers (L) are employed on each of the read address lines. Multiplexers110,112and120are employed to select which of the multiple requesters provides a read address to the memory array102on read port P1. More specifically, the multiplexer110selects (based on a control signal (evenp1_sel) when the clock1signal is high) whether the ‘0’ requestor P0P1, S0P1, or a delayed S0P1is selected to provide a read address to a first input of the multiplexer120. The multiplexer112selects (based on a control signal (oddp1_sel) when the clock1signal is low) whether the ‘1’ requestor P1P1, S1P1, or a delayed S1P1is selected to provide a read address to a second input of the multiplexer120. Which of the requesters is selected by the control signals evenp1_sel and oddp1_sel is based on a priority scheme employed. The multiplexer120selects (based on a select signal (data_gate), which passes ‘0’ requesters on even clock2signal cycles and passes ‘1’ requesters on odd clock2signal cycles) whether the read address provided by the multiplexer110or the multiplexer112is provided to the read port P1of the memory array102.

As is also shown, read addresses (i.e., P0P2_RA, P1P2_RA, S0P2_RA, and S1P2_RA) for four requesters (P0P2, P1P2, S0P2, and S1P2) are provided to a second port (P2) of the memory array102. As noted above, in the disclosed embodiment, two-stage latches (L) are employed on each of the read address lines. Multiplexers114,116, and122are employed to select which of the multiple requesters provides a read address to the memory array102on the read port P2. More specifically, the multiplexer114selects (based on a control signal (evenp2_sel) when the clock1signal is high) whether the ‘0’ requestor P0P2, S0P2, or a delayed S0P2is selected to provide a read address to a first input of the multiplexer122. The multiplexer114selects (based on a control signal (oddp2_sel) when the clock1signal is low) whether the ‘1’ requestor P1P2, S1P2, or a delayed S1P2is selected to provide a read address to a second input of the multiplexer122. Which of the requesters is selected by the control signals evenp2_sel and oddp2_sel is also based on the employed priority scheme. The multiplexer122selects (based on a select signal (data_gate), which passes ‘0’ requesters on even clock2signal cycles and passes ‘1’ requesters on odd clock2signal cycles) whether the read address provided by the multiplexer114or the multiplexer116is provided to the read port P2of the memory array102.

Similar to how a read address is directed to a read port of the memory array102via a first multiplexer and latch structure, read data exits the memory array102via a second multiplexer and latch structure that is configured to maintain an order of the read data. For simplicity, only the circuitry that is applicable to the read port P1is illustrated. More specifically, multiplexers130and132select (based on a control signal (buffer_sel)) a memory element from which to read data from the memory array102. Secondary read data is staged to exit the interface a single clock1cycle later than primary read data. Multiplexers140,142,144, and146receive a control signal (crit_32b) that orders bytes of read data as the read data exits the memory array102. For example, a sixty-four byte line would include a high-order thirty-two bytes and a low-order thirty-two bytes that are provided in alternate clock1cycles. It should be appreciated that the techniques disclosed herein may be applied to a memory array in which a line of memory is read out of the memory array in a single clock1cycle. Multiplexers150and152select whether secondary read data (S0P1_RD or S1P1_RD) or delayed secondary read data is provided to a secondary requester.FIG. 3depicts an example timing diagram300that illustrates four simultaneous accesses on the same physical read port (i.e., port P1) and the availability of data at an output of the interface100. As is illustrated, a valid signal (RdVal) indicates when a read address is valid. While only one valid signal is illustrated, it should be appreciated that in a typical implementation each requestor provides a respective valid signal in conjunction with a respective read address. In the diagram300, the addresses (e.g., address0A0and1A0) are different example addresses for a requestor (i.e., P0P1).

With reference toFIG. 2, a relevant portion of an example write section200of a memory array interface is illustrated. The write section200is also essentially a prioritized pipeline. As is shown, write addresses (i.e., P0P1_WA, P1P1_WA, S0P1_WA, and S1P1_WA) for four requesters (P0P1, P1P1, S0P1, and S1P1) are provided to a first port (P1) of a memory array202. It should be appreciated that a width of a write address line depends on the number of memory elements (ME) that are to be accessed. For example, assuming that thirty-two memory elements are implemented, five write address lines may be employed (25=32). In one embodiment, two-stage latches or clocked buffers (L) are employed on each of the write address lines as illustrated. Multiplexers210,212, and220are employed to select which of the multiple requesters provides a write address to the memory array202on write port P1. More specifically, the multiplexer210selects (based on a control signal (evenp1_sel) when the clock1signal is high) whether the ‘0’ requestor P0P1, S0P1, or a delayed S0P1is selected to provide a write address to a first input of the multiplexer220. The multiplexer212selects (based on a control signal (oddp1_sel) when the clock1signal is low) whether the ‘1’ requester P1P1, S1P1, or a delayed S1P1is selected to provide a write address to a second input of the multiplexer220. Which of the requesters is selected by the control signals evenp1_sel and oddp1_sel is based on a priority scheme employed. The multiplexer220selects (based on a select signal (data_gate), which passes ‘0’ requesters on even clock2signal cycles and passes ‘1’ requesters on odd clock2signal cycles) whether the write address provided by the multiplexer210or the multiplexer212is provided to the write port P1of the memory array202.

As is also shown, write addresses (i.e., P0P2_WA, P1P2_WA, S0P2_WA, and S1P2_WA) for four requesters (i.e., P0P2, P1P2, S0P2, and S1P2) are provided to a second port (P2) of the memory array202. As noted above, in the disclosed embodiment, two-stage latches (L) are employed on each of the write address lines. Multiplexers214,216, and222are employed to select which of the multiple requesters provides a write address to the memory array202on the write port P2. More specifically, the multiplexer214selects (based on a control signal (evenp2_sel) when the clock1signal is high) whether the ‘0’ requester P0P2, S0P2, or a delayed S0P2is selected to provide a write address to a first input of the multiplexer222. The multiplexer214selects (based on a control signal (oddp2_sel) when the clock1signal is low) whether the ‘1’ requester P1P2, S1P2, or a delayed S1P2is selected to provide a write address to a second input of the multiplexer222. Which of the requesters is selected by the control signals evenp2_sel and oddp2_sel is also based on the employed priority scheme. The multiplexer222selects (based on a select signal (data_gate), which passes ‘0’ requesters on even clock2signal cycles and passes ‘1’ requesters on odd clock2signal cycles) whether the write address provided by the multiplexer214or the multiplexer216is provided to the write port P2of the memory array202.

Similar to how a write address is directed to a write port of the memory array202via a first multiplexer and latch structure, write data enters the memory array202via a second multiplexer and latch structure that is configured to maintain an order of the write data. For simplicity, only circuitry that is applicable to the write port P1is illustrated. More specifically, multiplexers250receive a control signal (crit_32b) that orders bytes of write data for writing to the memory array202. Multiplexers240,242,244, and246are employed to select which of the multiple requesters provides write data to the memory array202on the write port P2. More specifically, the multiplexer240selects (based on a control signal (evenp1_sel_d) when the clock1signal is high) whether the ‘0’ requestor P0P1, S0P1, or a delayed S0P1is selected to provide write data to a first input of multiplexer230. The multiplexer244selects (based on a control signal (oddp1_sel_d) when the clock1signal is low) whether the ‘1’ requestor P1P1, S1P1, or a delayed S1P1is selected to provide write data to a second input of the multiplexer230. Which of the requesters is selected by the control signals evenp1_sel_d and oddp1_sel_d is also based on the employed priority scheme. The multiplexer230selects (based on a select signal (data_gate), which passes ‘0’ requesters on even clock2signal cycles and passes ‘1’ requesters on odd clock2signal cycles) whether the write data provided by the multiplexer240or the multiplexer244is provided to the write port P2of the memory array202.

The multiplexer242selects (based on the control signal (oddp1_sel_d) when the clock1signal is low) whether the ‘0’ requestor P0P1, S0P1, or a delayed S0P1is selected to provide write data to a first input of the multiplexer232. The multiplexer246selects (based on the control signal (oddp1_sel_d) when the clock1signal is low) whether the ‘1’ requestor P1P1, S1P1, or a delayed S1P1is selected to provide write data to a second input of multiplexer232. Which of the requesters is selected by the control signals evenp1_sel_d and oddp1_sel_d is also based on the employed priority scheme. In the disclosed embodiment, the evenp1_sel_d clock signal corresponds to the evenp1_sel signal delayed by one clock1cycle and the oddp1_sel_d clock signal corresponds to the oddp1_sel signal delayed by one clock1cycle. The multiplexer232selects (based on a select signal (data_gate), which passes ‘0’ requesters on even clock2signal cycles and passes ‘1’ requesters on odd clock2signal cycles) whether the write data provided by the multiplexer242or the multiplexer246is provided to the write port P1of the memory array202.FIG. 4depicts an example timing diagram400that illustrates four simultaneous accesses on the same physical write port (i.e., port P1). As is illustrated, a valid signal (WtVal) indicates when a write address is valid. While only one valid signal is illustrated, it should be appreciated that in a typical implementation each requestor provides a respective valid signal in conjunction with a respective write address. In the diagram400, the addresses (e.g., address0A0and1A0) are different example addresses for a requestor (e.g., P0P1). As is illustrated, a low-order thirty-two bytes (0A0) is written in one clock1cycle and a high-order thirty-two bytes (0A1) is written in a next clock1cycle for the requestor P0P1.

With reference toFIG. 5, an example computer system500is illustrated that may include one or more circuits that employ one or more memory arrays configured according to various embodiments of the present disclosure. The computer system500includes a processor502that is coupled to a memory subsystem504, a display506, and an input device508. The processor502may include one or more memory arrays configured according to the present disclosure. The memory subsystem504includes an application appropriate amount of volatile memory (e.g., dynamic random access memory (DRAM)) and non-volatile memory (e.g., read-only memory (ROM)). The display506may be, for example, a cathode ray tube (CRT) or a liquid crystal display (LCD). The input device508may include, for example, a mouse and a keyboard. The processor502may also be coupled to one or more mass storage devices, e.g., a compact disc read-only memory (CD-ROM) drive.

With reference toFIG. 6, an example process600for operating a memory array, according to an embodiment of the present disclosure, is illustrated. In block602, the process600is initiated at which point control transfers to block604. In block604, memory access requests (i.e., read or write requests) are received by a memory array interface from multiple requesters. Next, in block606, the memory access requests are serviced by the interface while maintaining a fixed timing. The memory access requests may be serviced in an order that is based on a priority assigned to each of the multiple requesters. In various embodiments, a first portion of the interface is clocked with a first clock signal, a second portion of the interface is clocked with a second clock signal, and the memory array is clocked with the second clock signal. In this case, a frequency of the second clock signal is higher than a frequency of the first clock signal. Following block606, control transfers to block608, where the process600terminates.

Accordingly, a memory array interface has been described herein that is scalable and that maintains fixed and predictable timings (i.e., read and/or write latency can be readily determined). The memory array interface may be configured to provide multiple requesters access to a single read port or a single write port of a memory array, irrespective of the number of the multiple requesters.