Phase-locked loop (PLL) circuit containing a biased phase detector for improved frequency acquisition

An extended frequency lock range is achieved in a PLL circuit based on sampled phase detectors by modifying a conventional PLL circuit to utilize a biased phase detector to achieve frequency acquisition of the oscillator output signal, without the need for a lock detector. A biased phase detector applies more phase error correction in one direction than in the other direction. For example, a positive biased phase detector applies more positive current, I.sub.UP, over time than negative current, I.sub.DOWN. For a positive biased phase detector, the VCO control voltage is initialized to a value below the lock-in voltage, and the positive biased phase detector will cause a steady increase in the VCO control voltage until the PLL locks, thereby causing the phase error to be approximately zero. Likewise, for a negative biased phase detector, the VCO control voltage is initialized to a value above the lock-in voltage, and the negative biased phase detector will cause a steady decrease in the VCO control voltage until the PLL locks, thereby causing the phase error to be approximately zero.

FIELD OF THE INVENTION 
The present invention relates to phase-locked loop (PLL) circuits, and more 
particularly, to frequency acquisition techniques for phase-locked loop 
(PLL) circuits containing sampled phase detectors. 
BACKGROUND OF THE INVENTION 
Phase-locked loop (PLL) circuits are frequently utilized to lock an 
oscillator in phase with a reference signal. PLL circuits are often 
utilized within receivers in digital communication systems to generate a 
local clock signal that is phase aligned with an incoming reference 
signal. The phase aligned local clock signal facilitates the receipt and 
processing of synchronous data sent by a transmitter in the communication 
system. 
A conventional PLL circuit includes a phase detector, a filter and a 
voltage-controlled oscillator (VCO). In the conventional PLL circuit, the 
phase detector compares the incoming reference signal and the output of 
the VCO. The phase detector generates an error signal that is 
representative of the phase difference of the reference signal and the VCO 
output. The error signal is filtered and applied to the control input of 
the VCO to produce an output signal that tracks the phase of the reference 
signal. 
A potential problem exists, however, for a PLL circuit based on sampled 
phase detectors. Specifically, for large frequency errors, conventional 
sampled phase detectors are equally likely to generate a positive or 
negative phase correction signal, regardless of the actual polarity of the 
frequency error, since the likelihood of sampling before and after a data 
edge (due to the frequency error) is fifty percent (50%) each. Thus, it is 
necessary to ensure that large frequency errors do not occur by extending 
the frequency lock range of the PLL circuit. 
Conventional techniques for extending the frequency lock range of a PLL 
circuit based on sampled phase detectors utilize a square wave as an 
auxiliary input to initially tune the VCO, while using an additional phase 
and frequency detector (PFD) to compare the frequency of the auxiliary 
input to the VCO output. Once the VCO is tuned to the desired frequency in 
this manner, the additional phase and frequency detector (PFD) is switched 
out of the PLL feedback loop, and the sampled phase detector is utilized 
to phase lock onto the incoming data. Relying on the presence of an 
external reference signal, such as a square wave, to extend the frequency 
lock range, however, may not be practical in many receiver applications 
where the only received signal is the incoming random data. 
Improved frequency acquisition has been achieved by sweeping the frequency 
of the VCO output, V.sub.O, to search for the signal frequency. The PLL 
will lock when the frequency of the VCO output, V.sub.O, is sufficiently 
close to the frequency of the reference signal. A lock detector determines 
when the VCO locked up, and then turns off the applied voltage ramp. 
SUMMARY OF THE INVENTION 
A PLL circuit is disclosed that achieves an extended frequency lock range 
by modifying a conventional PLL circuit to utilize a biased phase detector 
to achieve frequency acquisition of the oscillator output signal. Thus, 
the PLL will lock without the need for an applied voltage ramp or lock 
detector. As used herein, a biased phase detector applies more phase error 
correction in one direction than in the other direction. For example, a 
positive biased phase detector applies more positive current, I.sub.UP, 
over time than negative current, I.sub.DOWN. 
For a positive biased phase detector, the VCO control voltage is 
initialized to a value below the lock-in voltage, and the positive biased 
phase detector will cause a steady increase in the VCO control voltage 
until the PLL locks, thereby causing the phase error to be approximately 
zero. In one implementation, a positive biased phase detector is achieved 
by suppressing the response for a predefined percentage of detected 
negative phase errors, while applying the same magnitude positive current, 
I.sub.UP, and negative current, I.sub.DOWN. For example, every second 
detected negative phase error can be ignored. Alternatively, a positive 
biased phase detector can be achieved by providing a larger magnitude 
positive current, I.sub.UP, than negative current, I.sub.DOWN. 
Likewise, for a negative biased phase detector, the VCO control voltage is 
initialized to a value above the lock-in voltage, and the negative biased 
phase detector will cause a steady decrease in the VCO control voltage 
until the PLL locks, thereby causing the phase error to be approximately 
zero. In one implementation, a negative biased phase detector is achieved 
by suppressing the response for a predefined percentage of detected 
positive phase errors, while applying the same magnitude positive current, 
I.sub.UP, and negative current, I.sub.DOWN. For example, every second 
detected positive phase error can be ignored. Alternatively, a negative 
biased phase detector can be achieved by providing a larger magnitude 
negative current, I.sub.DOWN, than positive current, I.sub.up.

DETAILED DESCRIPTION 
FIG. 1 illustrates a conventional PLL circuit 100 providing an extended 
frequency lock range by utilizing a square wave as an auxiliary input to 
initially tune the voltage-controlled oscillator (VCO) 140, while using a 
phase and frequency detector (PFD) 110 to compare the frequency of the 
auxiliary input square wave to the VCO output, V.sub.O. Once the VCO 140 
is tuned to the frequency of the auxiliary input square wave, 
V.sub.square, a switch 125 is activated to utilize a phase detector 120 to 
phase lock the VCO output, V.sub.O, onto the incoming data. 
Thus, the PLL circuit 100, shown in FIG. 1, includes a phase and frequency 
detector 110, a phase detector 120, a switch 125, a low pass filter 130 
and a voltage-controlled oscillator (VCO) 140. Initially, the phase and 
frequency detector 110 compares the incoming auxiliary reference signal, 
V.sub.square, and the output of the VCO, V.sub.O. The phase and frequency 
detector 110 generates an error signal, I.sub.err, representing the phase 
and frequency differences between the auxiliary reference signal, 
V.sub.square, and the VCO output, V.sub.O, until the VCO 140 is tuned to 
the frequency of the auxiliary input square wave, V.sub.square. The error 
signal, I.sub.err, produced by the phase and frequency detector 110 is 
filtered by the filter 130 and applied to the VCO 140 to produce an output 
signal, V.sub.O, that tracks the phase and frequency of the signal, 
V.sub.square. The VCO has a lock-in voltage defined to be the ideal 
voltage for which the PLL can lock without a cycle slip. 
Thereafter, the phase detector 120 compares the incoming reference signal, 
V.sub.data, and the output of the VCO, V.sub.O. The phase detector 120 
generates an error signal, I.sub.err, representing the phase difference 
between the incoming data signal, V.sub.data, and the VCO output, V.sub.O. 
The error signal, I.sub.err, produced by the phase detector 120 is 
filtered by the filter 130 and applied to the VCO 140 to produce an output 
signal, V.sub.O, that tracks the phase of the signal, V.sub.data. 
FIG. 2 illustrates an illustrative conventional parallel data receiver 
circuit having five parallel data samplers 211-215 for sampling incoming 
data. As shown in FIG. 3, the clock phases, .phi..sub.1 -.phi..sub.5, from 
the VCO output, V.sub.O, are skewed by an amount equal to one-fifth of a 
clock cycle or period, and their rate is one-fifth of the rate of the 
incoming data. An edge detector 220, in cooperation with the two adjacent 
data samplers 214-215, operates as a phase detector 230, clocked by a 
clock phase, .phi..sub.45, which is between .phi..sub.4 and .phi..sub.5. 
The edge detector 220 only observes every fifth data edge. The edge 
detector 220 can be embodied, for example, as a D-type flip flop or can be 
made decision directed so that it also works for the reference signal 
being a data signal. 
The edge detector 220 can be triggered by the inverse of .phi..sub.2, as 
shown in FIGS. 2 and 3. In this manner, the sampled phase detector 230 
serves to align the VCO output, V.sub.O, with the edge in between data 
bits D.sub.4 and D.sub.5. Thus, if there is a binary transition from high 
to low, for example, between data bits D.sub.4 and D.sub.5, the 
measurement of the edge detector 220 will be either high or low, 
indicating whether the sampling is being done just before or just after 
the falling edge, respectively. Likewise, if there is a binary transition 
from low to high between data bits D.sub.4 and D.sub.5, the measurement of 
the edge detector 220 will be either low or high, indicating whether the 
sampling is being done just before or just after the rising edge, 
respectively. 
According to a feature of the present invention, an extended frequency lock 
range is achieved by modifying a conventional PLL circuit to utilize a 
biased phase detector to achieve frequency acquisition of the oscillator 
output signal without the need for an applied voltage ramp or lock 
detector. Conventional techniques achieve frequency acquisition by 
sweeping the frequency of the VCO output, V.sub.O, to search for the 
signal frequency. The PLL will lock when the frequency of the VCO output, 
V.sub.O, is sufficiently close to the frequency of the reference signal. 
FIG. 4 illustrates the voltage ramp that is utilized as the input to the 
VCO for the conventional frequency sweeping process. A lock detector (not 
shown) determines that the VCO is locked at a point 410 on the voltage 
ramp, and thereafter turns off the applied voltage ramp. If the sweeping 
is performed at too high a rate, the loop will not lock. 
Thus, in accordance with the present invention, frequency acquisition is 
achieved without the need for a lock detector or a ramp voltage by 
utilizing a biased phase detector. As used herein, a biased phase detector 
applies more phase error correction in one direction than in the other 
direction. For example, a positive biased phase detector applies more 
positive current, I.sub.UP, over time than negative current, I.sub.DOWN. 
For a positive biased phase detector implementation, the VCO control 
voltage is initialized to a value below the lock-in voltage, and the 
positive biased phase detector will cause a steady increase in the VCO 
control voltage until the PLL locks, as shown in FIG. 5. In one 
implementation, a positive biased phase detector is achieved by 
suppressing the response for a predefined percentage of detected negative 
phase errors, while applying the same magnitude positive current, 
I.sub.UP, and negative current, I.sub.DOWN. For example, every second 
detected negative phase error can be ignored. Unlike conventional 
frequency sweeping techniques, the biased phase detector does not need to 
be switched off when the PLL locks. 
Likewise, for a negative biased phase detector, the VCO control voltage is 
initialized to a value above the lock-in voltage of the VCO, and the 
negative biased phase detector will cause a steady decrease in the VCO 
control voltage until the PLL locks, thereby causing the phase error to be 
approximately zero. In one implementation, a negative biased phase 
detector is achieved by suppressing the response for a predefined 
percentage of detected positive phase errors, while applying the same 
magnitude positive current, I.sub.UP, and negative current, I.sub.DOWN. 
For example, every second detected positive phase error can be ignored. 
FIG. 6 illustrates a PLL circuit 600 having a biased phase detector 620 in 
accordance with the present invention. The elements 110, 125, 130, 140 in 
the PLL circuit 600 of FIG. 6, may operate in the same manner as the 
like-numbered elements of FIG. 1. 
It is to be understood that the embodiments and variations shown and 
described herein are merely illustrative of the principles of this 
invention and that various modifications may be implemented by those 
skilled in the art without departing from the scope and spirit of the 
invention.