FERROELECTRIC DEVICE AND SEMICONDUCTOR DEVICE

A ferroelectric device including a metal oxide film having favorable ferroelectricity is provided. The ferroelectric device includes a first conductor, a metal oxide film over the first conductor, and a second conductor over the metal oxide film. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.

TECHNICAL FIELD

One embodiment of the present invention relates to a metal oxide, a ferroelectric device utilizing the metal oxide, and a manufacturing method thereof. Another embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for fabricating a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a storage device are each an embodiment of a semiconductor device. It can be said that a display device (a liquid crystal display device, a light-emitting display device, and the like), a projection device, a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, and the like include a semiconductor device.

BACKGROUND ART

In recent years, semiconductor devices have been developed, and LSIs, CPUs, memories, and the like are mainly used as the semiconductor devices. A CPU is an aggregation of semiconductor elements; the CPU includes a semiconductor integrated circuit (including at least a transistor and a memory) formed into a chip by processing a semiconductor wafer, and is provided with an electrode that is a connection terminal.

A semiconductor circuit (IC chip) of an LSI, a CPU, a memory, or the like is mounted on a circuit board, for example, a printed wiring board, to be used as one of components of a variety of electronic devices.

A technique by which a transistor is formed using a semiconductor thin film formed over a substrate having an insulating surface has been attracting attention. The transistor is used in a wide range of electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). As known semiconductor thin films which can be used for transistors, a silicon-based semiconductor material, an oxide semiconductor, and the like are used.

As described in Non-Patent Document 1, a memory array using a ferroelectric is actively researched and developed. For the next-generation ferroelectric memories, researches on hafnium oxide, such as a research on ferroelectric HfO2-based materials (Non-Patent Document 2); a research on ferroelectricity of a hafnium oxide thin film (Non-Patent Document 3); ferroelectricity of a HfO2thin film (Non-Patent Document 4); and demonstration of integration of an FeRAM using a ferroelectric Hf0.5Zr0.5O2and a CMOS (Non-Patent Document 5) have been actively carried out.

REFERENCES

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

As described in Non-Patent Document 1 to Non-Patent Document 5, various researches and developments on ferroelectrics have been carried out. For example, Non-Patent Document 1 has reported that the sign of polarization (P) changes due to oxygen atom movement at the time of “Orthorhombic phase Ferroelectric” as illustrated inFIG.8A. Furthermore, Non-Patent Document 2 has reported that the magnitude of polarization and the permittivity (εr) change depending on the proportions of Hf and Zr as illustrated inFIG.8B.

Non-Patent Document 3 has reported a writing endurance, which is a reliability test of ferroelectrics, of approximately 109cycles as shown inFIG.9. Non-Patent Document 4 has reported HfO2's diffraction intensity, polarization, and crystal structures, which are as shown inFIG.10A,FIG.10B, andFIG.10C.

Although various researches and developments on ferroelectrics have been carried out as described above, ferroelectric characteristics still have room for improvement, and improvement in characteristics such as reliability is being demanded.

In view of this, an object of one embodiment of the present invention is to provide a material having favorable ferroelectricity, that is, a metal oxide film having ferroelectricity. Another object of one embodiment of the present invention is to provide a capacitor utilizing a material that can have ferroelectricity. Another object of one embodiment of the present invention is to provide a transistor utilizing a material that can have ferroelectricity. Another object of one embodiment of the present invention is to provide a capacitor and a diode each utilizing a material that can have ferroelectricity. Another object of one embodiment of the present invention is to provide an element utilizing a material that can have ferroelectricity and utilizing tunnel junction.

Note that the description of these objects does not preclude the existence of other objects. In one embodiment of the present invention, there is no need to achieve all these objects. Other objects will be apparent from the description of the specification, the drawings, the claims, and the like, and other objects can be derived from the description of the specification, the drawings, the claims, and the like.

Means for Solving the Problems

One embodiment of the present invention is a ferroelectric device including a first conductor, a metal oxide film over the first conductor, and a second conductor over the metal oxide film. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.

Another embodiment of the present invention is a ferroelectric device including a first conductor, a metal oxide film over the first conductor, a second conductor over the metal oxide film, and a sealing film over the second conductor. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.

In the above, it is preferable that the sealing film include a first sealing film and a second sealing film over the first sealing film, the first sealing film contain oxygen and aluminum, the second sealing film contain nitrogen and silicon, and the first sealing film have a function of adsorbing or capturing hydrogen.

Another embodiment of the present invention is a semiconductor device including a transistor and a capacitor electrically connected to the transistor. The capacitor includes a first conductor, a metal oxide film over the first conductor, and a second conductor over the metal oxide film. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.

In the above embodiment, the transistor preferably contains silicon in a channel formation region.

In the above embodiment, the transistor preferably includes an oxide semiconductor in a channel formation region.

One embodiment of the present invention is a semiconductor device including a semiconductor film, a metal oxide film over the semiconductor film, and a second conductor over the metal oxide film. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.

In the above embodiment, it is preferable that the semiconductor film contain silicon or an oxide semiconductor and the semiconductor device include a source electrode and a drain electrode each of which is electrically connected to the semiconductor film.

Another embodiment of the present invention is a semiconductor device including a first conductor, a metal oxide film over the first conductor, a second conductor over the metal oxide film, and an insulator positioned at one or both of a top surface of the first conductor and a bottom surface of the second conductor. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.

In the above embodiment, the insulator preferably contains nitrogen and silicon.

In each of the above embodiments, a concentration of at least one or more of hydrogen and carbon contained in the metal oxide film is preferably lower than or equal to 5×1020atoms/cm3by SIMS analysis. In each of the above embodiments, a concentration of at least one or more of hydrogen and carbon contained in the metal oxide film is further preferably lower than or equal to 1×1020atoms/cm3by SIMS analysis. In each of the above embodiments, a concentration of chlorine contained in the metal oxide film is preferably lower than or equal to 5×1021atoms/cm3by SIMS analysis. In each of the above embodiments, a concentration of chlorine contained in the metal oxide film is further preferably lower than or equal to 1×1021atoms/cm3by SIMS analysis.

Effect of the Invention

According to one embodiment of the present invention, a material having favorable ferroelectricity, that is, a metal oxide film having ferroelectricity can be provided. According to another embodiment of the present invention, a capacitor utilizing a material that can have ferroelectricity can be provided. According to another embodiment of the present invention, a transistor utilizing a material that can have ferroelectricity can be provided. According to another embodiment of the present invention, a capacitor and a diode each utilizing a material that can have ferroelectricity can be provided. According to another embodiment of the present invention, an element utilizing a material that can have ferroelectricity and utilizing tunnel junction can be provided.

Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not have to have all these effects. Note that other effects will be apparent from the description of the specification, the drawings, the claims, and the like and other effects can be derived from the description of the specification, the drawings, the claims, and the like.

MODE FOR CARRYING OUT THE INVENTION

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, they are not limited to the illustrated scale. Note that the drawings schematically illustrate ideal examples, and embodiments of the present invention are not limited to shapes, values, and the like shown in the drawings. For example, in the actual manufacturing process, a layer, a resist mask, or the like might be unintentionally reduced in size by treatment such as etching, which might not be reflected in the drawings for easy understanding. Furthermore, in the drawings, the same reference numerals are used in common for the same portions or portions having similar functions in different drawings, and repeated description thereof is omitted in some cases. Furthermore, the same hatch pattern is used for the portions having similar functions, and the portions are not especially denoted by reference numerals in some cases.

Furthermore, especially in a top view (also referred to as a “plan view”), a perspective view, or the like, the description of some components might be omitted for easy understanding of the invention. In addition, some hidden lines and the like might not be illustrated.

The ordinal numbers such as “first” and “second” in this specification and the like are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, the term “first” can be replaced with the term “second”, “third”, or the like as appropriate. In addition, the ordinal numbers in this specification and the like do not sometimes correspond to the ordinal numbers that are used to specify one embodiment of the present invention.

Moreover, in this specification and the like, terms for describing arrangement, such as “over” and “under”, are used for convenience for describing the positional relationship between components with reference to drawings. The positional relationship between components is changed as appropriate in accordance with the direction in which the components are described. Thus, without limitation to terms described in this specification, the description can be changed appropriately depending on the situation.

When this specification and the like explicitly state that X and Y are connected, for example, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are regarded as being disclosed in this specification and the like. Accordingly, without being limited to a predetermined connection relationship, for example, a connection relationship shown in drawings or texts, a connection relationship other than one shown in drawings or texts is regarded as being disclosed in the drawings or the texts. Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. In addition, the transistor includes a region where a channel is formed (hereinafter also referred to as a channel formation region) between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and a current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows.

Furthermore, functions of a source and a drain are sometimes interchanged with each other when transistors having different polarities are used or when the direction of a current is changed in a circuit operation, for example. Therefore, the terms “source” and “drain” can sometimes be interchanged with each other in this specification and the like.

Note that a channel length refers to, for example, a distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is in an on state) and a gate electrode overlap each other or a channel formation region in a top view of the transistor. Note that in one transistor, channel lengths in all regions do not necessarily have the same value. In other words, the channel length of one transistor is not fixed to one value in some cases. Thus, in this specification, the channel length is any one of the values, the maximum value, the minimum value, or the average value in a channel formation region.

A channel width refers to, for example, the length of a channel formation region in a direction perpendicular to a channel length direction in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is in an on state) and a gate electrode overlap each other, or a channel formation region in a top view of the transistor. Note that in one transistor, channel widths in all regions do not necessarily have the same value. In other words, the channel width of one transistor is not fixed to one value in some cases. Thus, in this specification, the channel width is any one of the values, the maximum value, the minimum value, or the average value in a channel formation region.

Note that in this specification and the like, depending on the transistor structure, a channel width in a region where a channel is actually formed (hereinafter also referred to as an “effective channel width”) is sometimes different from a channel width shown in a top view of a transistor (hereinafter also referred to as an “apparent channel width”). For example, in a transistor whose gate electrode covers a side surface of a semiconductor, the effective channel width is larger than the apparent channel width, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor whose gate electrode covers a side surface of a semiconductor, the proportion of a channel formation region formed in the side surface of the semiconductor is increased in some cases. In that case, the effective channel width is larger than the apparent channel width.

In such a case, the effective channel width is sometimes difficult to estimate by actual measurement. For example, estimation of an effective channel width from a design value requires assumption that the shape of a semiconductor is known. Accordingly, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure the effective channel width accurately.

In this specification, the simple term “channel width” refers to an apparent channel width in some cases. Alternatively, in this specification, the simple term “channel width” refers to an effective channel width in some cases. Note that values of a channel length, a channel width, an effective channel width, an apparent channel width, and the like can be determined, for example, by analyzing a cross-sectional TEM image and the like.

Note that impurities in a semiconductor refer to, for example, elements other than the main components of a semiconductor. For example, an element with a concentration lower than 0.1 atomic % can be regarded as an impurity. When an impurity is contained, for example, the density of defect states in a semiconductor increases and the crystallinity decreases in some cases. In the case where the semiconductor is an oxide semiconductor, examples of an impurity which changes the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor; hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen are given as examples. Note that water also serves as an impurity in some cases. In addition, oxygen vacancies (also referred to as Vo) are formed in an oxide semiconductor in some cases by entry of impurities, for example.

Note that in this specification and the like, silicon oxynitride is a material that contains more oxygen than nitrogen in its composition. Moreover, silicon nitride oxide is a material that contains more nitrogen than oxygen in its composition.

In this specification and the like, the term “insulator” can be replaced with an insulating film or an insulating layer. Furthermore, the term “conductor” can be replaced with a conductive film or a conductive layer. Moreover, the term “semiconductor” can be replaced with a semiconductor film or a semiconductor layer.

In this specification and the like, “parallel” indicates a state where two straight lines are placed at an angle greater than or equal to −10° and less than or equal to 10°. Accordingly, the case where the angle is greater than or equal to −5° and less than or equal to 5° is also included. Furthermore, “substantially parallel” indicates a state where two straight lines are placed at an angle greater than or equal to −30° and less than or equal to 30°. Moreover, “perpendicular” indicates a state where two straight lines are placed at an angle greater than or equal to 80° and less than or equal to 100°. Accordingly, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included. Furthermore, “substantially perpendicular” indicates a state where two straight lines are placed at an angle greater than or equal to 60° and less than or equal to 120°.

In this specification and the like, a metal oxide is an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as an OS), and the like. For example, in the case where a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is referred to as an oxide semiconductor in some cases. That is, an OS transistor can also be referred to as a transistor including a metal oxide or an oxide semiconductor.

In this specification and the like, “normally off” means that a drain current per micrometer of channel width flowing through a transistor when no potential is applied to a gate or the gate is supplied with a ground potential is 1×10−20A or lower at room temperature, 1×10−18A or lower at 85° C., or 1×10−16A or lower at 125° C.

In this embodiment, a metal oxide film and a semiconductor device of one embodiment of the present invention are described with reference to FIG.1A1, FIG.1A2, FIG.1B1, FIG.1B2, FIG.1C1, FIG.1C2, FIG.1C3, and FIG.1C4.

FIG.1A1, FIG.1B1, and FIG.1C1are circuit diagrams of semiconductor devices of one embodiment of the present invention. The circuit diagram in FIG.1A1includes one transistor (a field-effect transistor, also referred to as FET) and one capacitor, and the one capacitor contains a material that can have ferroelectricity. The circuit diagram in FIG.1B1includes one transistor, and a gate insulating film of the transistor contains a material that can have ferroelectricity. The circuit diagram in FIG.1C1includes one capacitor and one diode, and the capacitor contains a material that can have ferroelectricity. Although the one capacitor and the one diode are separately illustrated in the circuit diagram in FIG.1C1, the present invention is not limited thereto. For example, in the case where one element has functions of both the one capacitor and the one diode, there is no need to separate the functions. As a structure corresponding to the circuit diagram in FIG.1C1, for example, it is possible to employ an element structure where an insulator is included between a pair of electrodes and tunnel junction between the insulator and the electrodes is utilized.

Note that the circuit diagram in FIG.1A1can be regarded as a 1Tr1C (one transistor and one capacitor) element structure, and may be referred to as an FeRAM (Ferroelectric Random Access Memory) or Type 1 structure. The circuit diagram in FIG.1B1can be regarded as a 1Tr (one transistor) element structure, and may be referred to as an FeFET (Ferroelectric Field Effect Transistor) or Type 2 structure. The circuit diagram in FIG.1C1can be regarded as one capacitor element structure utilizing tunnel junction, and may be referred to as an FTJ (Ferroelectric Tunnel Junction) or Type 3 structure.

Next, examples of a semiconductor device of one embodiment of the present invention applicable to the structures illustrated in the circuit diagrams in FIG.1A1, FIG.1B1, and FIG.1C1are described with reference to FIG.1A2, FIG.1B2, FIG.1C2, FIG.1C3, and FIG.1C4. FIG.1A2, FIG.1B2, FIG.1C2, FIG.1C3, and FIG.1C4are cross-sectional views illustrating examples of the semiconductor device of one embodiment of the present invention. Note that white circles in the circuit diagrams in FIG.1A1, FIG.1B1, and FIG.1C1represent terminals.

FIG.1A2is a cross-sectional view corresponding to the capacitor illustrated in FIG.1A1, FIG.1B2is a cross-sectional view corresponding to the transistor containing a material that can have ferroelectricity in FIG.1B1, and FIG.1C2, FIG.1C3, and FIG.1C4are each a cross-sectional view corresponding to the capacitor and the diode illustrated in FIG.1C1.

FIG.1A2includes a conductor110, an insulator130over the conductor110, and a conductor120over the insulator130. Note that the insulator130is preferably formed using a material that can have ferroelectricity. The insulator130may be rephrased as a dielectric or a ferroelectric. Although not illustrated in FIG.1A2, a structure where the conductor120is connected to a source or a drain of the transistor as illustrated in FIG.1A1is employed.

FIG.1B2includes an oxide230, the insulator130over the oxide230, and the conductor120over the insulator130. Note that the insulator130is preferably formed using a material that can have ferroelectricity. FIG.1B2can also be regarded as a structure where the oxide230is in contact with the insulator130, i.e., the material that can have ferroelectricity.

FIG.1C2includes the conductor110, an insulator115aover the conductor110, the insulator130over the insulator115a, and the conductor120over the insulator130. Note that FIG.1C2can be regarded as a structure where the insulator115ais included between the conductor110and the insulator130in FIG.1A2. FIG.1C3includes the conductor110, the insulator130over the conductor110, an insulator115bover the insulator130, and the conductor120over the insulator115b.

FIG.1C4includes the conductor110, the insulator115aover the conductor110, the insulator130over the insulator115a, the insulator115bover the insulator130, and the conductor120over the insulator115b. Note that in the structure of the circuit diagram in FIG.1C1, certain polarization is preferably obtained in the P-E (Polarization density-Electric field) characteristics. For example, in the case where a first section is set from 0 (V) to 3 (V), a second section is set from 3 (V) to 0 (V), a third section is set from −Va (V) to Va (V), a fourth section is set from 0 (V) to −3 (V), a fifth section is set from −3 (V) to 0 (V), and a sixth section is set from −Va (V) to Va (V) in the I-V characteristics, the current value preferably differs between the third section and the sixth section. In addition, Va is preferably a voltage lower than or equal to a coercive electric field (Ec) in this circuit diagram. In order to satisfy the characteristics, at least one of the film kind, the film quality, and the film thickness is made to be different between the insulator115aand the insulator115b, for example.

Next, the components are described.

The conductor110has a function of a lower electrode. The conductor110can be deposited by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like. Examples of an ALD method include a thermal ALD method, in which a precursor and a reactant react with each other only by a thermal energy, and a PEALD (Plasma Enhanced ALD) method, in which a reactant excited by plasma is used.

By using the ALD method, a conductive film with high planarity can easily be deposited as the conductor110in some cases. For example, titanium nitride is deposited by a thermal ALD method. The conductor110is formed into a pattern by a lithography method or the like as appropriate.

A surface over which the conductor110is formed (also referred to as a formation surface) or the top surface of the conductor110preferably has high planarity. For example, the surface over which the conductor110is formed or the top surface of the conductor110may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve planarity. In the case where the planarity of the surface over which the conductor110is formed or the top surface of the conductor110is improved, the crystallinity of the component above the surface, specifically the crystallinity of the insulator130, can be improved.

The insulator130is preferably formed using a material that can have ferroelectricity. The details of the insulator130will be described later.

The conductor120has a function of an upper electrode. The conductor120is placed so as to be separated from the conductor110with the insulator130therebetween. The details of the conductor120will be described later.

The details of the oxide230will be described later (refer to Embodiment 2).

The insulator115aand the insulator115bare each a paraelectric material; for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride can be used. It is particularly preferable that the insulators115aand115beach be a silicon nitride film. The insulator115aand the insulator115bcan each be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is particularly preferable that the insulator115aand the insulator115bbe deposited by a PEALD method. For example, in the case where a silicon nitride film is deposited by a PEALD method, a precursor containing halogen such as fluorine, chlorine, bromine, or iodine is suitably used. After the precursor is introduced, plasma treatment is performed in an atmosphere to which a nitriding agent such as N2, N2O, NH3, NO, NO2, or N2O2is introduced, so that a high-quality silicon nitride film can be deposited.

According to one embodiment of the present invention, a material that can have ferroelectricity, that is, a metal oxide film having ferroelectricity can be provided. According to another embodiment of the present invention, a ferroelectric device utilizing a material that can have ferroelectricity can be provided. According to another embodiment of the present invention, a capacitor utilizing a material that can have ferroelectricity can be provided. According to another embodiment of the present invention, a transistor utilizing a material that can have ferroelectricity can be provided. According to another embodiment of the present invention, a capacitor and a diode each utilizing a material that can have ferroelectricity can be provided.

In other words, a metal oxide film of one embodiment of the present invention can be used for one or more of semiconductor devices selected from a capacitor, a transistor, and a diode.

Next, a capacitor of one embodiment of the present invention and the fabrication method thereof are specifically described. Note that the structure illustrated in FIG.1A1and FIG.1A2is described as an example below; however, the structure illustrated in FIG.1B1and FIG.1B2and the structures illustrated in FIG.1C1, FIG.1C2, FIG.1C3, and FIG.1C4can also be employed when some of the components (e.g., the oxide230, the insulator115a, and the insulator115b) are changed.

Structure Example of Capacitor

In this section, structure examples of a capacitor of one embodiment of the present invention are described with reference toFIG.2AtoFIG.4CandFIG.6.

As illustrated inFIG.2A, a capacitor100of one embodiment of the present invention includes the conductor110, the conductor120, and the insulator130interposed between the conductor110and the conductor120. For example, the conductor110is placed over a substrate (not illustrated), the insulator130is placed over the conductor110, and the conductor120is placed over the insulator130. Here, the conductor110functions as a lower electrode of the capacitor100, the conductor120functions as an upper electrode of the capacitor100, and the insulator130functions as a dielectric of the capacitor100.

The insulator130is preferably formed using a material that can have ferroelectricity. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrOX(X is a real number greater than 0). Another example of the material that can have ferroelectricity is a material obtained by adding an element J1(the element J1here is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), and the like) to hafnium oxide. The atomic ratio of hafnium to the element J1can be appropriately set here; for example, the atomic ratio of hafnium to the element J1is 1:1 or the neighborhood thereof. Another example of the material that can have ferroelectricity is a material obtained by adding an element J2(the element J2here is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), and the like) to zirconium oxide. The atomic ratio of zirconium to the element J2can be appropriately set; for example, the atomic ratio of zirconium to the element J2is 1:1 or the neighborhood thereof. Alternatively, as the material that can have ferroelectricity, a piezoelectric ceramic having a perovskite structure such as PbTiOx, barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used. As the material that can have ferroelectricity, a mixture or compound containing a plurality of materials selected from the above-described materials can be used, for example. Alternatively, the insulator130can have a stacked-layer structure of a plurality of materials selected from the above-described materials. Note that since the crystal structures (properties) of hafnium oxide, zirconium oxide, HfZrOX, the material obtained by adding the element J1to hafnium oxide, and the like can be changed depending on the processes as well as the deposition conditions, a material that exhibits ferroelectricity is referred to as a material that can have ferroelectricity as well as a ferroelectric in this specification or the like.

Hafnium oxide or a material containing hafnium oxide and zirconium oxide is especially preferable as the material that can have ferroelectricity because of being able to have ferroelectricity even when processed into a several-nanometer-thick thin film. When the ferroelectric layer that can be thin is used, the capacitor100can be combined with a miniaturized semiconductor element such as a transistor to form a semiconductor device. Note that in this specification and the like, a layer of the material that can have ferroelectricity is referred to as a ferroelectric layer or a metal oxide film, in some cases. In this specification and the like, a device including such a ferroelectric layer (metal oxide film) is sometimes referred to as a ferroelectric device.

Here, the insulator130preferably has a film-like shape as illustrated inFIG.2C. InFIG.2C, the x-axis and the y-axis are parallel to the film surface of the insulator130, and the z-axis is parallel to the film thickness direction of the insulator130. Since the insulator130preferably has a film-like shape, a width w, of the insulator130in the x-direction and a width wyin the y-direction are preferably greater than a thickness t, further preferably three times or more the thickness t. For example, in the case where the thickness t of the insulator130is 3 nm, at least one of the width w, and the width wyof the insulator130is preferably greater than or equal to 3 nm, further preferably greater than or equal to 10 nm. The thickness t of the insulator130can be less than or equal to 100 nm, preferably less than or equal to 50 nm, further preferably less than or equal to 20 nm, still further preferably less than or equal to 10 nm (typically greater than or equal to 2 nm and less than or equal to 9 nm). For example, the thickness t is preferably greater than or equal to 8 nm and less than or equal to 12 nm.

Although the insulator130illustrated inFIG.2Chas a shape such that the top surface and the bottom surface are parallel to each other in the entire region, the present invention is not limited thereto. For example, the insulator130sometimes has unevenness reflecting the shape of the formation surface. In this case, when a groove portion is formed in the formation surface, a region of the insulator130overlapping with the groove portion has a depressed shape in some cases.

The material that can have ferroelectricity is an insulator and has a property in which application of an electric field from the outside causes internal polarization and the polarization remains even after the electric field is made zero. Thus, with a capacitor using such a material as a dielectric (the capacitor may be referred to as a ferroelectric capacitor below), a nonvolatile storage element can be formed. A nonvolatile storage element using a ferroelectric capacitor is sometimes referred to as an FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, or the like. For example, a ferroelectric memory can have a structure including a transistor and a ferroelectric capacitor, where one of a source and a drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Thus, the semiconductor device using the capacitor100and the transistor described in this embodiment can function as a ferroelectric memory.

Crystal structures of hafnium oxide, which is a material that can be used as the insulator130, are described with reference toFIG.6.FIG.6is a model diagram illustrating crystal structures of hafnium oxide (HfO2in this embodiment). Hafnium oxide is known to take on various crystal structures and, for example, can take on crystal structures illustrated inFIG.6such as cubic (space group: Fm-3m), tetragonal (space group: P42/nmc), orthorhombic (space group: Pbc22), and monoclinic (space group: P21/c) crystal structures. As illustrated inFIG.6, phase transition can occur between the above-described crystal structures. For example, the crystal structure of hafnium oxide can be changed from a crystal structure mainly formed of monoclinic crystals to a crystal structure mainly formed of orthorhombic crystals when the hafnium oxide is doped with zirconium to form a composite material.

In the case where hafnium oxide and zirconium oxide are alternately deposited by an ALD method or the like so as to achieve a composition ratio of hafnium oxide to zirconium oxide of approximately 1:1 as the above-described composite material, the composite material has an orthorhombic crystal structure. Alternatively, the composite material has an amorphous structure. Alternatively, the composite material has an amorphous structure, and the application of heat treatment or the like to the composite material can change the crystal structure from the amorphous structure to an orthorhombic crystal structure. In some cases, the orthorhombic crystal structure change to a monoclinic crystal structure in some cases. To make the above-described composite material have ferroelectricity, an orthorhombic crystal structure is preferred to a monoclinic crystal structure.

Here, a model of an orthorhombic crystal structure of HfZrOXis described with reference toFIG.3A.

FIG.3Ais a model diagram of the crystal structure of HfZrOX, which is Hf0.5Zr0.5O2here. InFIG.3A, the directions of the a-axis, the b-axis, and the c-axis are also indicated.FIG.3Aillustrates a structure where Zr layers are placed in the orthorhombic structure (Pca21) of HfO2including a cell optimized by first-principles calculation.

InFIG.3A, hafnium and zirconium are bonded to each other with oxygen therebetween. This can be formed by alternately depositing hafnium and zirconium by an ALD method as in the deposition sequence described later.

Application of an electric field from the outside displaces part of oxygen illustrated inFIG.3A, thereby causing internal polarization. Here, part of oxygen is displaced in the c-axis direction and polarization is caused also in the c-axis direction.

FIG.3BandFIG.3Care model diagrams of the crystal structure of HfZrOx, which is Hf0.5Zr0.5O2here.FIG.3BandFIG.3Ceach illustrate a model whose atomic arrangement is optimized by first-principles calculation. Note that the model illustrated inFIG.3Aand the model illustrated inFIG.3Bdiffer only in the manner of illustrating atoms and have substantially the same atomic arrangement.

Note that HfZrOx having an orthorhombic structure can take either the atomic arrangement illustrated inFIG.3Bor the atomic arrangement illustrated inFIG.3C. Thus, an electric field applied from the outside displaces some of the oxygen atoms in HfZrOx, thereby causing internal polarization. In addition, when the direction or intensity of the electric field is changed, some of the oxygen atoms in HfZrOx move and the sign of internal polarization changes.

FIG.3Dis a graph showing an example of the hysteresis characteristics of a ferroelectric layer. InFIG.3D, the horizontal axis represents the intensity of an electric field applied to the ferroelectric layer and the vertical axis represents the amount of polarization in the ferroelectric layer. A point61shown inFIG.3Drepresents the minimum polarization at the time when the electric field intensity is 0, and a point62shown inFIG.3Drepresents the maximum polarization at the time when the electric field intensity is 0. For example, at the minimum polarization (the point61shown inFIG.3D), atoms in HfZrOx are arranged as illustrated inFIG.3B. At the maximum polarization (the point62shown inFIG.3D), atoms in HfZrOx are arranged as illustrated inFIG.3C.

As illustrated inFIG.2A, the insulator130preferably has a crystal structure where layers each formed by crystals are stacked. Furthermore, the layers each preferably have a single crystal structure illustrated inFIG.3A. Note that dashed lines in the insulator130illustrated inFIG.2Arepresent crystal layers and a c-axis132represents the c-axis of the crystals.

As illustrated inFIG.2A, the crystal layers included in the insulator130extend in the a-b plane direction. In addition, the crystal layers included in the insulator130grow in the c-axis direction (sometimes referred to as axial growth), and the plurality of crystal layers are stacked in the c-axis direction. The c-axis preferably faces a direction substantially perpendicular to the formation surface or top surface of the insulator130. For example, as illustrated inFIG.2B, an angle θ formed by a normal134with respect to the top surface of the conductor110and the c-axis132is preferably less than or equal to 30°, further preferably less than or equal to 5°.

FIG.2Aillustrates a state where an electric field E is applied between the lower electrode (the conductor110) and the upper electrode (the conductor120) of the capacitor100. Here, it is preferable that the direction of the electric field E be substantially parallel to the c-axis132. For example, the direction of the electric field E is preferably made parallel to the normal134, in which case the angle θ formed by the direction of the electric field E and the c-axis132becomes less than or equal to 30°, preferably less than or equal to 5°.

With such a structure where the c-axis132of the insulator130is substantially parallel to the direction E of the electric field, the displacement direction of oxygen in an orthorhombic crystal is made substantially parallel to the direction E of the electric field. Thus, the electric field E can efficiently cause polarization in the insulator130. Accordingly, polarization in the insulator130can be made large.

In order to form the insulator130including the crystal layers as described above, the top surface of the conductor110serving as the base of the insulator130preferably has favorable planarity. For example, the top surface roughness of the conductor110serving as the base, which is represented by arithmetic mean roughness (Ra) or root mean square roughness (RMS), is less than or equal to 2 nm, preferably less than or equal to 1 nm, further preferably less than or equal to 0.8 nm, still further preferably less than or equal to 0.5 nm, yet still further preferably less than or equal to 0.4 nm. Making the planarity of the top surface of the conductor110favorable as described above can improve the crystallinity of the insulator130and enhance the ferroelectricity of the insulator130.

Furthermore, in order to form the insulator130including the crystal layers as described above, it is preferable that no different layer be formed at an interface between the insulator130and the conductor110and an interface between the insulator130and the conductor120. For example, in the case where TiNx is used for the conductor110(the conductor120) and HfZrOx is used for the insulator130, oxygen contained in the insulator130or the like diffuses into the conductor110(the conductor120) and TiOx might be formed as a different layer at the interface between the insulator130and the conductor110(the conductor120). The thickness of such a different layer is preferably less than or equal to 1 nm, further preferably less than or equal to 0.4 nm, still further preferably less than or equal to 0.2 nm.

FIG.4AtoFIG.4Care enlarged views illustrating the vicinity of the insulator130that functions as a ferroelectric layer and is illustrated inFIG.2Aor the like.FIG.4Ais a diagram illustrating the insulator130having the single crystal structure described with reference toFIG.2AtoFIG.2C. As described above, the insulator130illustrated inFIG.4Ahas the structure where the plurality of crystal layers are stacked. The plurality of crystal layers included in the insulator130are preferably aligned in the c-axis132direction.

Although a ferroelectric layer having a single crystal structure illustrated inFIG.4Aor the like is used as the insulator130in the example described above, the present invention is not limited thereto. For example, as illustrated inFIG.4B, the insulator130may have a polycrystalline structure including a plurality of grains136with different crystallinities. Here, at least one of the plurality of grains136preferably has an orthorhombic crystal structure. At least one of the plurality of grains136preferably has an orthorhombic crystal structure, in which case the insulator130exhibits ferroelectricity.

The insulator130may include a layer138ahaving a single crystal structure and a layer138bhaving a polycrystalline structure. For example, as illustrated inFIG.4C, a plurality of layers138ahaving a single crystal structure and a plurality of layers138bhaving a polycrystalline structure may be stacked over the conductor110.

As described above, the insulator130has a single crystal structure in at least part of its crystal structure. The insulator130may have any one or more of crystal structures selected from cubic, tetragonal, orthorhombic, and monoclinic crystal structures. The insulator130especially preferably has an orthorhombic crystal structure to exhibit ferroelectricity. Alternatively, the crystal structure of the insulator130may be an amorphous structure. Alternatively, the insulator130may have a composite structure including an amorphous structure and a crystal structure.

In order to form the insulator130with favorable crystallinity, impurities such as hydrogen, carbon, a hydrocarbon, and chlorine in the insulator130are preferably reduced. When the impurities are contained in the insulator130, crystallization of the insulator130is inhibited in some cases. Furthermore, the impurities might form oxygen vacancies in the crystal in the insulator130. As described above, in the crystal structure illustrated inFIG.3A, oxygen is displaced by an electric field from the outside and ferroelectricity is exhibited. Thus, in order to improve the ferroelectricity of the insulator130, impurities such as hydrogen, carbon, a hydrocarbon, and chlorine are preferably reduced so that oxygen vacancies are reduced.

Therefore, the insulator130is preferably formed using a material that contains no or an extremely small amount of impurities such as hydrogen, carbon, a hydrocarbon, and chlorine. For example, the concentration of hydrogen contained in the insulator130is preferably lower than or equal to 5×1020atoms/cm3, further preferably lower than or equal to 1×1020atoms/cm3. For example, the concentration of a hydrocarbon contained in the insulator130is preferably lower than or equal to 5×1020atoms/cm3, further preferably lower than or equal to 1×1020atoms/cm3, still further preferably lower than or equal to 5×1019atoms/cm3. For example, the concentration of carbon contained in the insulator130is preferably lower than or equal to 5×1020atoms/cm3, further preferably lower than or equal to 1×1020atoms/cm3, still further preferably lower than or equal to 5×1019atoms/cm3. For example, the concentration of chlorine contained in the insulator130is preferably lower than or equal to 5×1021atoms/cm3, further preferably lower than or equal to 1×1021atoms/cm3, still further preferably lower than or equal to 5×1020atoms/cm3.

Note that the impurities can be quantified by secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or auger electron spectroscopy (AES). For example, impurities such hydrogen, carbon, a hydrocarbon, and chlorine in the insulator130can be quantified by SIMS analysis.

By using a material that does not contain at least one or more of hydrogen, a hydrocarbon, carbon, and chlorine or contains an extremely small amount of at least one or more of hydrogen, a hydrocarbon, carbon, and chlorine in the insulator130as described above, the crystallinity of the insulator130can be increased and a structure with high ferroelectricity can be achieved.

For the conductor110, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like; an alloy containing any of the above metal elements; an alloy containing a combination of the above metal elements; or the like. As an alloy containing any of the above metal elements, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferable because they are oxidation-resistant conductive materials or materials that retain their conductivity even after absorbing oxygen. Alternatively, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

A stack of a plurality of conductive layers formed of the above materials may be used. For example, a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen may be employed. Alternatively, a stacked-layer structure combining a material containing the above metal element and a conductive material containing nitrogen may be employed. Alternatively, a stacked-layer structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

A conductive material that can be used for the conductor110can be used for the conductor120.

<Fabrication Method of Capacitor>

In this section, a method for fabricating a capacitor of one embodiment of the present invention is described with reference toFIG.5AtoFIG.5C.

As illustrated inFIG.5A, the conductor110is deposited over a substrate (not illustrated). The conductor110can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. By using the ALD method, a conductive film with high planarity can easily be deposited as the conductor110, in some cases. For example, titanium nitride may be deposited by a thermal ALD method. The conductor110may be formed into a pattern by a lithography method or the like as appropriate.

Next, as illustrated inFIG.5B, the insulator130is deposited over the conductor110. The insulator130can be deposited by a sputtering method, a CVD method, an ALD method, or the like. For example, the insulator130can be deposited over the conductor110with good coverage by using an ALD method. This can inhibit the occurrence of a leakage current between the upper electrode and the lower electrode of the capacitor100.

A material that can have ferroelectricity is preferably used for the insulator130. As the material that can have ferroelectricity, any of the above materials can be used. Here, the thickness of the insulator130can be less than or equal to 100 nm, preferably less than or equal to 50 nm, further preferably less than or equal to 20 nm, still further preferably less than or equal to 10 nm (typically greater than or equal to 2 nm and less than or equal to 9 nm).

In the case where a material containing hafnium oxide and zirconium oxide (HfZrOx) is used for the insulator130, a thermal ALD method is preferably used for the deposition.

Furthermore, in the case where the insulator130is deposited by a thermal ALD method, a material that does not contain a hydrocarbon (also referred to as Hydro Carbon or HC) is suitably used as a precursor. In the case where one or both of hydrogen and carbon are contained in the insulator130, crystallization of the insulator130might be inhibited. Thus, using a precursor that does not contain a hydrocarbon in the above-described manner is preferable in order to reduce the concentration of one or both of hydrogen and carbon in the insulator130. For example, as the precursor that does not contain a hydrocarbon, a chlorine-based material can be given. Note that in the case where a material containing hafnium oxide and zirconium oxide (HfZrOx) is used for the insulator130, HfCl4and ZrCl4can be used as the precursor.

In the case where the insulator130is deposited by a thermal ALD method, H2O or O3can be used as an oxidizer. As the oxidizer in the thermal ALD method, O3is more suitably used than H2O to reduce the concentration of hydrogen in the film. However, the oxidizer in the thermal ALD method is not limited thereto. For example, the oxidizer in the thermal ALD method may contain any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

Next, as illustrated inFIG.5C, the conductor120is deposited over the insulator130. Here, the conductor120is placed so as to be separated from the conductor110with the insulator130therebetween. The conductor120may have a stacked-layer structure of a conductor120aprovided over and in contact with the insulator130and a conductor120bprovided over and in contact with the conductor120a.

The conductor120amay be deposited by an ALD method, a CVD method, or the like. For example, titanium nitride can be deposited by a thermal ALD method. Here, the conductor120ais preferably deposited by a method in which deposition is performed while the substrate is heated, such as a thermal ALD method. For example, the substrate temperature during the deposition is higher than or equal to room temperature, preferably higher than or equal to 300° C., further preferably higher than or equal to 325° C., still further preferably higher than or equal to 350° C. Furthermore, the substrate temperature during the deposition is lower than or equal to 500° C., preferably lower than or equal to 450° C., for example. For example, the substrate temperature is approximately 400° C.

The deposition of the conductor120awithin the above-described temperature range enables the insulator130to have ferroelectricity even without high-temperature baking treatment (e.g., baking treatment at a heat treatment temperature of 400° C. or higher or 500° C. or higher) after the formation of the conductor120a.

When the conductor120ais deposited by an ALD method, which causes relatively little damage to a base, as described above, the crystal structure of the insulator130can be inhibited from being broken excessively, which leads to higher ferroelectricity of the insulator130.

For example, in the case where the conductor120ais formed by a sputtering method or the like, a base film, i.e., the insulator130here can be damaged. For example, in the case where a material containing hafnium oxide and zirconium oxide (HfZrOx) is used as the insulator130and the conductor120ais formed by a sputtering method, HfZrOx, which is the base film, is damaged by a sputtering method and the crystal structure of HfZrOx(typically, an orthorhombic crystal structure or the like) can be broken. Therefore, the conductor120ais preferably deposited by an ALD method, which causes relatively little damage to a base.

When heat treatment is performed after the conductor120ais deposited by a sputtering method, the damage of the HfZrOxcrystal structure can be repaired.

Here, in some cases, a dangling bond (e.g., O*) in HfZrOxis bonded to hydrogen contained in HfZrOx, making it impossible to repair the damage of the HfZrOxcrystal structure. The dangling bond in HfZrOxis formed, for example, by damage due to deposition of the conductor120aby a sputtering method.

Thus, a material that does not contain hydrogen or contains an extremely small amount of hydrogen is suitably used as the insulator130, which is HfZrOxhere. For example, the concentration of hydrogen contained in the insulator130is preferably lower than or equal to 5×1020atoms/cm3, further preferably lower than or equal to 1×1020atoms/cm3.

Furthermore, as described above, in order to reduce the concentration of hydrogen in the insulator130, the material that does not contain a hydrocarbon is suitably used as the precursor. This may make the insulator130a film that does not contain a hydrocarbon as a main component or contains an extremely small amount of hydrocarbon. For example, the concentration of hydrocarbon contained in the insulator130is preferably lower than or equal to 5×1020atoms/cm3, further preferably lower than or equal to 1×1020atoms/cm3, still further preferably lower than or equal to 5×1019atoms/cm3.

Moreover, in the case where the material that does not contain a hydrocarbon is used as the precursor in depositing the insulator130, the insulator130may be a film that does not contain carbon as a main component or contains an extremely small amount of carbon. For example, the concentration of carbon contained in the insulator130is preferably lower than or equal to 5×1020atoms/cm3, further preferably lower than or equal to 1×1020atoms/cm3, still further preferably lower than or equal to 5×1019atoms/cm3.

As the insulator130, a material that contains an extremely small amount of at least one or more of hydrogen, a hydrocarbon, and carbon is suitably used, and it is especially important to reduce the amount of hydrocarbon and carbon. Hydrocarbon molecules and carbon atoms, which are heavier than hydrogen, are difficult to remove in a subsequent step. Therefore, it is suitable to thoroughly remove a hydrocarbon and carbon when the insulator130is deposited.

By using a material that does not contain at least one or more of hydrogen, a hydrocarbon, and carbon or contains an extremely small amount of at least one or more of hydrogen, a hydrocarbon, and carbon as the insulator130as described above, the crystallinity of the insulator130can be increased and a structure with high ferroelectricity can be achieved.

Note that the amount of chlorine contained in the insulator130is also preferably reduced. For example, the concentration of chlorine contained in the insulator130is preferably lower than or equal to 5×1021atoms/cm3, further preferably lower than or equal to 1×1021atoms/cm3, still further preferably lower than or equal to 5×1020atoms/cm3.

When impurities in the film of the insulator130, which are at least one or more of hydrogen, a hydrocarbon, carbon, and chlorine here, are thoroughly removed in the above-described manner, a highly purified intrinsic film having ferroelectricity, which is a highly purified intrinsic capacitor here, can be formed. Note that the highly purified intrinsic capacitor having ferroelectricity and a highly purified intrinsic oxide semiconductor described in a later embodiment are highly compatible with each other in the manufacturing process. Thus, a method for fabricating a semiconductor device with high productivity can be provided.

As described above, in one embodiment of the present invention, as the insulator130, a ferroelectric material is formed by a thermal ALD method using a precursor that does not contain a hydrocarbon (typically, a chlorine-based precursor) and an oxidizer (typically O3), for example. Then, the conductor120ais formed by deposition by a thermal ALD method (typically, deposition at 400° C. or higher). Without performing annealing after the deposition, in other words, by utilizing the temperature during the deposition of the conductor120a, the crystallinity or ferroelectricity of the insulator130can be increased. Note that increasing the crystallinity or ferroelectricity of the insulator130by utilizing the temperature during the deposition of the conductor120awithout performing annealing after the deposition of the conductor120ais referred to as self-annealing, in some cases.

Note that the conductor120bcan be deposited by a sputtering method, an ALD method, a CVD method, or the like. For example, tungsten can be deposited by a metal CVD method.

In the above-described manner, the capacitor100illustrated inFIG.5C, which includes the insulator130between the conductor110and the conductor120, can be fabricated. As described above, in the capacitor100of this embodiment, the ferroelectricity of the insulator130can be increased even when high-temperature baking treatment is not performed after formation of the conductor120a. Thus, the step of manufacturing a ferroelectric capacitor can be eliminated, which increases productivity of a ferroelectric capacitor and a semiconductor device including the ferroelectric capacitor.

Although the example where high-temperature baking treatment is not performed after fabrication of the conductor120ais described above, the present invention is not limited thereto. For example, in the case where the conductor120aand the conductor120bare formed without substrate heating or with low-temperature substrate heating, heat treatment may be performed after formation of the conductor120. For example, the substrate temperature during the heat treatment is set to be higher than or equal to room temperature, preferably higher than or equal to 300° C., further preferably higher than or equal to 325° C., still further preferably higher than or equal to 350° C. Furthermore, for example, the substrate temperature during the deposition is set to be lower than or equal to 500° C., preferably lower than or equal to 450° C. For example, the substrate temperature is set at approximately 400° C. The heat treatment can be performed in an atmosphere containing an oxygen gas, a nitrogen gas, or an inert gas.

A method for depositing the insulator130by an ALD method and a deposition apparatus used for the deposition are described below with reference toFIG.7AandFIG.7B.

An ALD method, which enables an atomic layer to be deposited one by one using self-limiting characteristics by atoms, has advantages such as deposition of an extremely thin film, deposition on a component with a high aspect ratio, deposition of a film with a small number of defects such as pinholes, deposition with excellent coverage, and low-temperature deposition.

In an ALD method, a first source gas (also referred to as a precursor) and a second source gas (also referred to as an oxidizing gas), both of which are for reaction, are alternately introduced into a chamber and repetitive introduction of these source gases forms a film. When the precursor or the oxidizing gas is introduced, N2, Ar, or the like may be introduced into a reaction chamber as a carrier purge gas, together with the precursor or the oxidizing gas. By using the carrier purge gas, the precursor or the oxidizing gas can be prevented from being adsorbed onto an inner side of a pipe or an inner side of a valve and can be introduced into the reaction chamber (also referred to as a carrier gas). Furthermore, the precursor or the oxidizing gas remaining in the reaction chamber can be exhausted quickly (also referred to as a purge gas). Thus, the carrier purge gas can be so called because the gas has two functions of introduction (carrier) and exhaustion (purge). Using the carrier purge gas is preferable to improve the uniformity of the formed film.

FIG.7Ashows a deposition sequence of a film of the material that can have ferroelectricity (hereinafter referred to as a ferroelectric layer) by an ALD method. An example of depositing a ferroelectric layer containing hafnium oxide and zirconium oxide as the insulator130is described below.

As a precursor401, a precursor that contains hafnium and any one or more selected from chlorine, fluorine, bromine, iodine, and hydrogen can be used. Furthermore, as a precursor402, a precursor that contains zirconium and any one or more selected from chlorine, fluorine, bromine, iodine, and hydrogen can be used. Here, HfCl4is used as the precursor401containing hafnium, and ZrCl4is used as the precursor402containing zirconium.

Note that the precursor401and the precursor402are formed by gasifying a liquid source material or a solid source material by heating. The precursor401is formed of a solid source material of HfCl4, and the precursor402is formed of a solid source material of ZrCl4. Impurities are preferably reduced in the precursor401and the precursor402and also in the solid source materials thereof. Examples of the impurities include Ba, Cd, Co, Cr, Cu, Fe, Ga, Li, Mg, Mn, Na, Ni, Sr, V, and Zn. In the solid source material of HfCl4and the solid source material of ZrCl4, the above-described impurities preferably exist at less than 1000 wppb. Here, wppb is a unit representing the concentration of impurities converted by mass in parts per billion.

As an oxidizing gas403, any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2can be used. In this section, a gas containing H2O is used as the oxidizing gas403. Furthermore, as a carrier purge gas404, any one or more selected from N2, He, Ar, Kr, and Xe can be used. In this section, N2is used as the carrier purge gas404.

First, the oxidizing gas403is introduced into a reaction chamber (Step S01). Next, the introduction of the oxidizing gas403is stopped, so that only the carrier purge gas404is left to purge the oxidizing gas403remaining in the reaction chamber (Step S02). Next, the precursor401and the carrier purge gas404are introduced into the reaction chamber, and the pressure in the reaction chamber is kept constant (Step S03). In this way, the precursor401is adsorbed onto the formation surface. Next, the introduction of the precursor401is stopped, so that and only the carrier purge gas404is left to purge the precursor401remaining in the reaction chamber (Step S04). Next, the oxidizing gas403is introduced into the reaction chamber. The introduction of the oxidizing gas403causes oxidation of the precursor401to form hafnium oxide (Step S05).

Next, the introduction of the oxidizing gas403is stopped, so that only the carrier purge gas404is left to purge the oxidizing gas403remaining in the reaction chamber (Step S06).

Next, the precursor402and the carrier purge gas404are introduced into the reaction chamber, and the pressure in the reaction chamber is kept constant (Step S07). In this way, the precursor402is adsorbed onto an oxygen layer of the hafnium oxide. Next, the introduction of the precursor402is stopped, so that only the carrier purge gas404is left to purge the precursor402remaining in the reaction chamber (Step S08). Next, the process returns to Step S01, and the oxidizing gas403is introduced into the reaction chamber. The introduction of the oxidizing gas403causes oxidation of the precursor402to form zirconium oxide on hafnium oxide.

Step S01to Step S08described above is defined as one cycle, and the cycle is repeated until a desired thickness is obtained. Note that Step S01to Step S08are each performed within a temperature range of higher than or equal to 250° C. and lower than or equal to 450° C., preferably a temperature range of higher than or equal to 350° C. and lower than or equal to 400° C.

By the deposition by an ALD method in the above-described manner, a layered crystal structure where a hafnium layer, an oxygen layer, and a zirconium layer are repeated as illustrated inFIG.4can be formed. Furthermore, by the deposition using the precursors with reduced impurities in the above-described manner, hindrance to the formation of the layered crystal structure due to impurity entry during the deposition can be inhibited. Thus, when the insulator130has a layered crystal structure with high crystallinity, the insulator130can have high ferroelectricity.

Note that the insulator130does not necessarily exhibit ferroelectricity right after being deposited. As described above, the insulator130exhibits ferroelectricity not right after being deposited but after the conductor120is formed over the insulator130, in some cases.

Next, a manufacturing apparatus used for the above-described deposition by an ALD method is described with reference toFIG.7B.FIG.7Bis a schematic diagram of a manufacturing apparatus900used for deposition by the ALD method.

As illustrated inFIG.7B, the manufacturing apparatus900includes a reaction chamber901, a gas inlet903, a reaction chamber entrance904, an exhaust port905, a wafer stage907, and a shaft908. InFIG.7B, a wafer950is placed over the wafer stage907.

A heater system for heating the precursor401, the precursor402, the oxidizing gas403, and the carrier purge gas404may be placed in the reaction chamber901. Furthermore, the wafer stage907may be provided with a heater system for heating the wafer950. Moreover, the wafer stage907may be provided with a rotation mechanism which rotates horizontally with the shaft908as a rotation axis. Although not illustrated, a gas supply system for introducing each of the precursor401, the precursor402, the oxidizing gas403, and the carrier purge gas404into the gas inlet903with an appropriate timing for an appropriate time at an appropriate flow rate is placed upstream from the gas inlet. Furthermore, although not illustrated, an exhaust system including a vacuum pump is placed downstream from the exhaust port905.

The manufacturing apparatus900illustrated inFIG.7Bis what is called a crossflow ALD apparatus. The flow of the precursor401, the precursor402, the oxidizing gas403, and the carrier purge gas404in the crossflow type is described below. The precursor401, the precursor402, the oxidizing gas403, and the carrier purge gas404flow from the gas inlet903to the reaction chamber901through the reaction chamber entrance904, reach the wafer950, and are exhausted through the exhaust port905. Arrows shown inFIG.7Bschematically indicate the directions of gas flow.

As described above, in Step S05of introducing the oxidizing gas403into the reaction chamber901, which is shown inFIG.7A, the precursor401adsorbed on the wafer950is oxidized by the oxidizing gas403to form hafnium oxide. Owing to the structure of the crossflow manufacturing apparatus900, the oxidizing gas403reaches the wafer950after being exposed to a heated component in the reaction chamber for a long time. Thus, in the case of using O3as the oxidizing gas403, for example, the oxidizing gas403reacts with the high-temperature solid surface before reaching the wafer950and is decomposed to have lower oxidizability. For this reason, the deposition rate of hafnium oxide depends on the distance the oxidizing gas403flows to reach the wafer950from the reaction chamber entrance904. In the case where the wafer stage907is rotated horizontally with the shaft908as a center, the periphery of the wafer950first reaches the oxidizing gas403; therefore, the thickness of hafnium oxide becomes larger toward the periphery of the wafer950and smaller in the center portion than in the periphery.

Thus, to inhibit the oxidizing gas403from being decomposed and having reduced oxidizability, the heating temperature of the reaction chamber needs to be set at an appropriate temperature. Note that although the description has been made by giving oxidation of the precursor401as an example, the same applies to oxidation of the precursor402.

In the above-described manner, a ferroelectric layer with excellent thickness uniformity over the substrate plane can be formed. The uniformity over the substrate plane is preferably less than or equal to ±1.5%, further preferably less than or equal to ±1.0%. Furthermore, when (the maximum thickness over the substrate plane)−(the minimum thickness over the substrate plane) is defined as RANGE and the thickness uniformity over the substrate plane is defined as ±PNU (Percent Non Uniformity) (%), the thickness uniformity over the substrate plane can be calculated from ±PNU (%)=(RANGE×100)/(2×the average thickness over the substrate plane).

Furthermore, when an oxygen layer with excellent uniformity is formed with the use of the oxidizing gas403in the above-described manner, a layered crystal structure with higher regularity can be formed. Thus, when the insulator130has a layered crystal structure with high regularity, the insulator130can have high ferroelectricity.

By using the above-described method, the insulator130formed of the material that can have ferroelectricity can be formed. By forming the capacitor100using such an insulator130, the capacitor100can be a ferroelectric capacitor.

According to one embodiment of the present invention, a capacitor containing a material that can have ferroelectricity can be provided. According to another embodiment of the present invention, the above capacitor can be provided with favorable productivity. According to another embodiment of the present invention, a capacitor that can be miniaturized or highly integrated can be provided.

At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with any of those in the other embodiments, the other examples, and the like described in this specification.

In this embodiment, an example of a semiconductor device including the transistor200and the capacitor100, which is one embodiment of the present invention, and a fabrication method thereof are described with reference toFIG.11AtoFIG.17C. Here, the description of the capacitor100in Embodiment 1 can be referred to for the capacitor100used in the above semiconductor device.

Structure Example of Semiconductor Device

FIG.11AtoFIG.11Dare a top view and cross-sectional views of the semiconductor device including the transistor200and the capacitor100.FIG.11Ais a top view of the semiconductor device.FIG.11BtoFIG.11Dare cross-sectional views of the semiconductor device. Here,FIG.11Bis a cross-sectional view of a portion indicated by dashed-dotted line A1-A2inFIG.11A, and is a cross-sectional view of the transistor200in the channel length direction.FIG.11Cis a cross-sectional view of a portion indicated by dashed-dotted line A3-A4inFIG.11A, and is a cross-sectional view of the transistor200in the channel width direction.FIG.11Dis a cross-sectional view of a portion indicated by dashed-dotted line A5-A6inFIG.11A. Note that for clarity of the drawing, some components are not illustrated in the top view inFIG.11A.

The semiconductor device of one embodiment of the present invention includes an insulator212over a substrate (not illustrated), an insulator214over the insulator212, the transistor200over the insulator214, an insulator280which is over an insulator275and provided in the transistor200, an insulator282over the insulator280, an insulator283over the insulator282, an insulator274over the insulator283, and an insulator285over the insulator283and the insulator274. The insulator212, the insulator214, the insulator216, the insulator275, the insulator280, the insulator282, the insulator283, the insulator285, and the insulator274function as interlayer films. The insulator283is in contact with part of the top surface of the insulator214, the side surface of the insulator216, the side surface of the insulator222, the side surface of the insulator275, the side surface of the insulator280, and the side surface and the top surface of the insulator282.

Here, the transistor200includes a semiconductor layer, a first gate, a second gate, a source, and a drain. The other of the source and the drain of the transistor200is in contact with one electrode of the capacitor100at a position above the semiconductor layer. An insulator271(an insulator271aand an insulator271b) is provided over and in contact with the source and the drain of the transistor200.

The capacitor100is provided in an opening that is formed in the insulator271, the insulator275, the insulator280, the insulator282, the insulator283, and the insulator285and reaches one of the source and the drain of the transistor200. The capacitor100includes the conductor110that is in contact with the top surface of the one of the source and the drain of the transistor200in the opening, the insulator130placed over the conductor110and the insulator285, and the conductor120(the conductor120aand the conductor120b) placed over the insulator130. Here, the conductor110is preferably placed along the side surface and the bottom surface of the opening.

An insulator245is preferably provided between the conductor110and the insulator280. It is preferable that the insulator245have a function of inhibiting diffusion of hydrogen (e.g., at least one of a hydrogen atom, a hydrogen molecule, and the like). In addition, it is preferable that the insulator245have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like). For example, the insulator245preferably has lower permeability of one or both of oxygen and hydrogen than the insulator280.

As illustrated inFIG.11AtoFIG.11D, the transistor200includes the insulator216over the insulator214, a conductor205(a conductor205aand a conductor205b) placed to be embedded in the insulator214and/or the insulator216, the insulator222over the insulator216and the conductor205, an insulator224over the insulator222, an oxide230aover the insulator224, an oxide230bover the oxide230a, a conductor242aover the oxide230b, the insulator271aover the conductor242a, a conductor242bover the oxide230b, the insulator271bover the conductor242b, an insulator252over the oxide230b, an insulator250over the insulator252, an insulator254over the insulator250, a conductor260(a conductor260aand a conductor260b) being positioned over the insulator254and overlapping with part of the oxide230b, and the insulator275placed over the insulator222, the insulator224, the oxide230a, the oxide230b, the conductor242a, the conductor242b, the insulator271a, and the insulator271b. Here, as illustrated inFIG.11BandFIG.11C, the insulator252is in contact with the top surface of the insulator222, the side surface of the insulator224, the side surface of the oxide230a, the side surface and the top surface of the oxide230b, the side surface of the conductor242, the side surface of the insulator271, the side surface of the insulator275, the side surface of the insulator280, and the bottom surface of the insulator250. The top surface of the conductor260is placed to be substantially level with the uppermost portion of the insulator254, the uppermost portion of the insulator250, the uppermost portion of the insulator252, and the top surface of the insulator280. The insulator282is in contact with at least parts of the top surfaces of the conductor260, the insulator252, the insulator250, the insulator254, and the insulator280.

Hereinafter, the oxide230aand the oxide230bare collectively referred to as the oxide230in some cases. The conductor242aand the conductor242bare collectively referred to as the conductor242in some cases. The insulator271aand the insulator271bare collectively referred to as the insulator271in some cases.

An opening reaching the oxide230bis provided in the insulator280and the insulator275. The insulator252, the insulator250, the insulator254, and the conductor260are placed in the opening. The conductor260, the insulator252, the insulator250, and the insulator254are provided between the insulator271aand the conductor242a, and the insulator271band the conductor242bin the channel length direction of the transistor200. The insulator254includes a region in contact with the side surface of the conductor260and a region in contact with the bottom surface of the conductor260.

The oxide230preferably includes the oxide230aplaced over the insulator224and the oxide230bplaced over the oxide230a. Including the oxide230aunder the oxide230bmakes it possible to inhibit diffusion of impurities into the oxide230bfrom components formed below the oxide230a.

Although a structure where two layers, the oxide230aand the oxide230b, are stacked as the oxide230in the transistor200is described, the present invention is not limited thereto. For example, the oxide230may be provided as a single layer of the oxide230bor to have a stacked-layer structure of three or more layers, or the oxide230aand the oxide230bmay each have a stacked-layer structure.

The conductor260functions as a first gate (also referred to as a top gate) electrode, and the conductor205functions as a second gate (also referred to as a back gate) electrode. The insulator252, the insulator250, and the insulator254function as a first gate insulator, and the insulator222and the insulator224function as a second gate insulator. Note that the gate insulator is also referred to as a gate insulating layer or a gate insulating film in some cases. The conductor242afunctions as one of a source and a drain, and the conductor242bfunctions as the other of the source and the drain. At least part of a region of the oxide230overlapping with the conductor260functions as a channel formation region.

FIG.12Ais an enlarged view of the vicinity of the channel formation region inFIG.11B. Supply of oxygen to the oxide230bforms the channel formation region in a region between the conductor242aand the conductor242b. As illustrated inFIG.12A, the oxide230bincludes a region230bcfunctioning as the channel formation region of the transistor200and a region230baand a region230bbthat are provided to sandwich the region230bcand function as a source region and a drain region. At least part of the region230bcoverlaps with the conductor260. In other words, the region230bcis provided between the conductor242aand the conductor242b. The region230bais provided to overlap with the conductor242a, and the region230bbis provided to overlap with the conductor242b.

The region230bcfunctioning as the channel formation region has a smaller amount of oxygen vacancies or a lower impurity concentration than the region230baand the region230bb, and thus is a high-resistance region with a low carrier concentration. Thus, the region230bccan be regarded as being i-type (intrinsic) or substantially i-type. Performing microwave treatment in an atmosphere containing oxygen facilitates formation of the region230bc, for example. Here, the microwave treatment refers to, for example, treatment using an apparatus including a power source that generates high-density plasma with the use of a microwave. Note that in this specification and the like, a microwave refers to an electromagnetic wave having a frequency greater than or equal to 300 MHz and less than or equal to 300 GHz.

The region230baand the region230bbfunctioning as the source region and the drain region include a large amount of oxygen vacancies or have a high concentration of an impurity such as hydrogen, nitrogen, or a metal element, and thus are each a low-resistance region with an increased carrier concentration. In other words, the region230baand the region230bbare each an n-type region having a higher carrier concentration and a lower resistance than the region230bc.

The carrier concentration in the region230bcfunctioning as the channel formation region is preferably lower than or equal to 1×1018cm−3, further preferably lower than 1×1017cm−3, still further preferably lower than 1×1016cm−3, yet further preferably lower than 1×1013cm−3, yet still further preferably lower than 1×1012cm−3. Note that the lower limit of the carrier concentration in the region230bcfunctioning as the channel formation region is not particularly limited and can be, for example, 1×10−9cm−3.

Between the region230bcand the region230baor the region230bb, a region having a carrier concentration that is lower than or substantially equal to the carrier concentrations in the region230baand the region230bband higher than or substantially equal to the carrier concentration in the region230bcmay be formed. That is, the region functions as a junction region between the region230bcand the region230baor the region230bb. The hydrogen concentration in the junction region is lower than or substantially equal to the hydrogen concentrations in the region230baand the region230bband higher than or substantially equal to the hydrogen concentration in the region230bcin some cases. The amount of oxygen vacancies in the junction region is smaller than or substantially equal to the amounts of oxygen vacancies in the region230baand the region230bband larger than or substantially equal to the amount of oxygen vacancies in the region230bcin some cases.

AlthoughFIG.12Aillustrates an example where the region230ba, the region230bb, and the region230bcare formed in the oxide230b, the present invention is not limited thereto. For example, the above regions may be formed not only in the oxide230bbut also in the oxide230a.

In the oxide230, the boundaries between the regions are difficult to detect clearly in some cases. The concentration of a metal element and an impurity element such as hydrogen or nitrogen, which is detected in each region, may be gradually changed not only between the regions but also in each region. That is, the region closer to the channel formation region preferably has a lower concentration of a metal element and an impurity element such as hydrogen or nitrogen.

In the transistor200, a metal oxide functioning as a semiconductor (such a metal oxide is hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide230(the oxide230aand the oxide230b) including the channel formation region.

The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, further preferably 2.5 eV or more. With the use of such a metal oxide having a large band gap, the off-state current of the transistor can be reduced.

As the oxide230, it is preferable to use, for example, a metal oxide such as an In-M-Zn oxide containing indium, an element M, and zinc (the element M is one or more kinds selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like). Alternatively, an In—Ga oxide, an In—Zn oxide, or an indium oxide may be used as the oxide230.

The atomic ratio of In to the element M in the metal oxide used as the oxide230bis preferably greater than the atomic ratio of In to the element Min the metal oxide used as the oxide230a.

The oxide230ais placed under the oxide230bin this manner, whereby impurities and oxygen can be inhibited from diffusing into the oxide230bfrom components formed below the oxide230a.

When the oxide230aand the oxide230bcontain a common element (as the main component) besides oxygen, the density of defect states at an interface between the oxide230aand the oxide230bcan be made low. Since the density of defect states at the interface between the oxide230aand the oxide230bcan be made low, the influence of interface scattering on carrier conduction is small, and a high on-state current can be obtained.

The oxide230bpreferably has crystallinity. It is particularly preferable to use a CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide230b.

The CAAC-OS is a metal oxide having a dense structure with high crystallinity and a small amount of impurities and defects (for example, oxygen vacancies (e.g., Vo). In particular, after the formation of a metal oxide, heat treatment is performed at a temperature at which the metal oxide does not become a polycrystal (e.g., higher than or equal to 400° C. and lower than or equal to 600° C.), whereby a CAAC-OS having a dense structure with higher crystallinity can be obtained. When the density of the CAAC-OS is increased in such a manner, diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

On the other hand, a clear crystal grain boundary is difficult to observe in the CAAC-OS; thus, it can be said that a reduction in electron mobility due to the crystal grain boundary is less likely to occur. Thus, a metal oxide including a CAAC-OS is physically stable. Therefore, the metal oxide including a CAAC-OS is resistant to heat and has high reliability.

If impurities and oxygen vacancies exist in a region of an oxide semiconductor where a channel is formed, a transistor using the oxide semiconductor might have variable electrical characteristics and poor reliability. In some cases, hydrogen in the vicinity of an oxygen vacancy forms a defect that is the oxygen vacancy into which hydrogen enters (hereinafter sometimes referred to as VoH), which generates an electron serving as a carrier. Therefore, when the region of the oxide semiconductor where a channel is formed includes oxygen vacancies, the transistor tends to have normally-on characteristics (characteristics with which, even when no voltage is applied to the gate electrode, the channel exists and a current flows through the transistor). Thus, impurities, oxygen vacancies, and VoH are preferably reduced as much as possible in the region of the oxide semiconductor where a channel is formed. In other words, it is preferable that the region of the oxide semiconductor where a channel is formed have a reduced carrier concentration and be of an i-type (intrinsic) or substantially i-type.

As a countermeasure to the above, an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) is provided in the vicinity of the oxide semiconductor and heat treatment is performed, so that oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and VoH. However, supply of an excess amount of oxygen to the source region or the drain region might cause a decrease in the on-state current or field-effect mobility of the transistor200. Furthermore, a variation of oxygen supplied to the source region or the drain region in the substrate plane leads to a variation in characteristics of the semiconductor device including the transistor.

Therefore, the region230bcfunctioning as the channel formation region in the oxide semiconductor is preferably an i-type or substantially i-type region with reduced carrier concentration, whereas the region230baand the region230bbfunctioning as the source region and the drain region are preferably n-type regions with high carrier concentrations. That is, it is preferable that oxygen vacancies and VoH in the region230bcof the oxide semiconductor be reduced and the region230baand the region230bbnot be supplied with an excess amount of oxygen.

Thus, in this embodiment, microwave treatment is performed in an oxygen-containing atmosphere in a state where the conductor242aand the conductor242bare provided over the oxide230bso that oxygen vacancies and VoH in the region230bccan be reduced.

The microwave treatment in an oxygen-containing atmosphere converts an oxygen gas into plasma using a high-frequency wave such as a microwave or RF and activates the oxygen plasma. At this time, the region230bccan be irradiated with the high-frequency wave such as a microwave or RF. By the effect of the plasma, the microwave, or the like, VoH in the region230bccan be cut; thus, hydrogen H can be removed from the region230bcand an oxygen vacancy Vo can be filled with oxygen. That is, the reaction “VoH→H+Vo” occurs in the region230bc, so that the hydrogen concentration in the region230bccan be reduced. As a result, oxygen vacancies and VoH in the region230bccan be reduced to lower the carrier concentration.

In the microwave treatment in an oxygen-containing atmosphere, the high-frequency wave such as the microwave or RF, the oxygen plasma, or the like is blocked by the conductor242aand the conductor242band does not affect the region230banor the region230bb. In addition, the effect of the oxygen plasma can be reduced by the insulator271and the insulator280that are provided to cover the oxide230band the conductor242. Hence, a reduction in VoH and supply of an excess amount of oxygen do not occur in the region230baor the region230bbin the microwave treatment, preventing a decrease in carrier concentration.

In particular, microwave treatment is preferably performed in an oxygen-containing atmosphere after formation of an insulating film to be the insulator252or after formation of an insulating film to be the insulator250. By performing the microwave treatment in an oxygen-containing atmosphere through the insulator252or the insulator250in such a manner, oxygen can be efficiently supplied into the region230bc. In addition, the insulator252is placed to be in contact with the side surface of the conductor242and the surface of the region230bc, thereby inhibiting oxygen more than necessary from being supplied to the region230bcand inhibiting the side surface of the conductor242from being oxidized. Furthermore, the side surface of the conductor242can be inhibited from being oxidized when the insulating film to be the insulator250is formed.

The oxygen supplied into the region230bchas any of a variety of forms such as an oxygen atom, an oxygen molecule, an oxygen radical (an0radical, an atom or a molecule having an unpaired electron, or an ion). Note that the oxygen supplied into the region230bchas any one or more of the above forms, particularly preferably an oxygen radical. Furthermore, the film quality of the insulator252and the insulator250can be improved, leading to higher reliability of the transistor200.

In the above-described manner, oxygen vacancies and VoH can be selectively removed from the region230bcin the oxide semiconductor, whereby the region230bccan be an i-type or substantially i-type region. Furthermore, supply of an excess amount of oxygen to the region230baand the region230bbfunctioning as the source region and the drain region can be inhibited and the n-type conductivity can be maintained. As a result, a change in the electrical characteristics of the transistor200can be inhibited, and thus a variation in the electrical characteristics of the transistors200in the substrate plane can be inhibited.

As illustrated inFIG.11C, a curved surface may be provided between the side surface of the oxide230band the top surface of the oxide230bin a cross-sectional view of the transistor200in the channel width direction. In other words, an end portion of the side surface and an end portion of the top surface may be curved (hereinafter referred to as rounded).

The radius of curvature of the curved surface is preferably greater than 0 nm and less than the thickness of the oxide230bin a region overlapping with the conductor242, or less than half of the length of a region that does not have the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than or equal to 20 nm, preferably greater than or equal to 1 nm and less than or equal to 15 nm, and further preferably greater than or equal to 2 nm and less than or equal to 10 nm. Such a shape can improve the coverage of the oxide230bwith the insulator252, the insulator250, the insulator254, and the conductor260.

The oxide230preferably has a stacked-layer structure of a plurality of oxide layers with different chemical compositions. Specifically, the atomic ratio of the element M to a metal element that is a main component of the metal oxide used as the oxide230ais preferably greater than the atomic ratio of the element M to a metal element that is a main component of the metal oxide used as the oxide230b. Moreover, the atomic ratio of the element M to In in the metal oxide used as the oxide230ais preferably greater than the atomic ratio of the element M to In in the metal oxide used as the oxide230b. Furthermore, the atomic ratio of In to the element Min the metal oxide used as the oxide230bis preferably greater than the atomic ratio of In to the element Min the metal oxide used as the oxide230a.

The oxide230bis preferably an oxide having crystallinity, such as a CAAC-OS. An oxide having crystallinity, such as a CAAC-OS, has a dense structure with small amounts of impurities and defects (e.g., oxygen vacancies) and high crystallinity. This can inhibit oxygen extraction from the oxide230bby the source electrode or the drain electrode. This can reduce oxygen extraction from the oxide230beven when heat treatment is performed; thus, the transistor200is stable with respect to high temperatures in a manufacturing process (what is called thermal budget).

Here, the conduction band minimum gradually changes at a junction portion of the oxide230aand the oxide230b. In other words, the conduction band minimum at the junction portion of the oxide230aand the oxide230bcontinuously changes or is continuously connected. To achieve this, the density of defect states in a mixed layer formed at the interface between the oxide230aand the oxide230bis preferably made low.

Specifically, when the oxide230aand the oxide230bcontain a common element as a main component besides oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide230bis an In-M-Zn oxide, an In-M-Zn oxide, an M-Zn oxide, an oxide of the element M, an In—Zn oxide, indium oxide, or the like may be used as the oxide230a.

Specifically, as the oxide230a, a metal oxide with a composition of In:M:Zn=1:3:4 [atomic ratio] or in the neighborhood thereof, or a composition of In:M:Zn=1:1:0.5 [atomic ratio] or in the neighborhood thereof is used. As the oxide230b, a metal oxide with a composition of In:M:Zn=1:1:1 [atomic ratio] or in the neighborhood thereof, a composition of In:M:Zn=1:1:2 [atomic ratio] or in the neighborhood thereof, or a composition of In:M:Zn=4:2:3 [atomic ratio] or in the neighborhood thereof can be used. Note that a composition in the neighborhood includes the range of ±30% of an intended atomic ratio. Gallium is preferably used as the element M

Here, the oxide230aand the oxide230bare preferably formed using a sputtering method. Oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. Increasing the proportion of oxygen contained in the sputtering gas can increase the amount of oxygen in the deposited film. The deposition method of the oxide230aand the oxide230bis not limited to a sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like can be used as appropriate.

When the metal oxide is deposited by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide and may be the atomic ratio of a sputtering target used for depositing the metal oxide.

The oxide230may be formed by an ALD method. Here, a method for depositing the oxide230by an ALD method is described. Note that a deposition method by an ALD method is described in the above embodiment; thus, different portions are mainly described and the description in the above embodiment can be referred to for common portions.

An In-M-Zn oxide that can be used as the oxide230tends to have a layered crystal structure where a layer containing indium (In) and oxygen (hereinafter, an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, an (M,Zn) layer) are stacked. Note that the number of the (M,Zn) layers interposed between two In layers correlates with the composition of the In-M-Zn oxide. For example, in the case where the composition is In:M:Zn=1:1:m, the number of the (M,Zn) layers interposed between two In layers is likely to be (m+1).

As an example of the method for depositing the oxide230by an ALD method, a method for depositing the In-M-Zn oxide is described with reference toFIG.7C.FIG.7Cshows an example of a deposition sequence in which deposition is performed using a precursor411to a precursor413and an oxidizing gas414. Note that the deposition sequence includes Step S11to Step S13.

As the precursor411, a precursor containing indium can be used. As the precursor412, a precursor containing the element M can be used. As the precursor413, a precursor containing zinc can be used. As each of the precursor411to the precursor413, a precursor formed of an inorganic substance (sometimes referred to as an inorganic precursor) may be used, or a precursor formed of an organic substance (sometimes referred to as an organic precursor) may be used. As the oxidizing gas414, a gas that can be used as the oxidizing gas403described in the above embodiment can be used.

First, Step S11is performed. In Step S11, a step of introducing the precursor411to make a precursor containing indium be adsorbed on the formation surface, a step of stopping the introduction of the precursor411to purge the excess precursor411in a chamber, a step of introducing the oxidizing gas414to oxidize the precursor411and form an In layer, and a step of stopping the introduction of the oxidizing gas414to purge the excess oxidizing gas414in the chamber are performed in this order.

Next, Step S12is performed. In Step S12, a step of introducing the precursor412to make a precursor containing the element M be adsorbed on a surface of the In layer, a step of stopping the introduction of the precursor413to purge the excess precursor412in the chamber, a step of introducing the oxidizing gas414to oxidize the precursor412and form an M layer, and a step of stopping the oxidizing gas414to purge the excess oxidizing gas in the chamber are performed in this order.

Next, Step S13is performed. In Step S13, a step of introducing the precursor413to make a precursor containing zinc be adsorbed on a surface of the M layer, a step of stopping the introduction of the precursor413to purge the excess precursor413in the chamber, a step of introducing the oxidizing gas414to oxidize the precursor413and form a Zn layer, and a step of stopping the introduction of the oxidizing gas414to purge the excess oxidizing gas414in the chamber are performed in this order.

Step S11to Step S13are defined as one cycle and the cycle is repeated, so that an In-M-Zn oxide with a desired thickness can be formed. Note that the element M or Zn enters the In layer due to heat treatment during the deposition or after the deposition, in some cases. Alternatively, In or Zn enters the M layer in some cases. Alternatively, In or Ga enters the Zn layer in some cases.

Note that the number of times each of Step S11to Step S13is performed in one cycle is not limited to one. The number of each of Step S11to Step S13in one cycle is preferably set so that an In-M-Zn oxide with a desired composition is obtained. For example, in the case where an In-M-Zn oxide with In:M:Zn=1:1:2 [atomic ratio] is deposited, it is preferable that Step S11, Step S13, Step S12, and Step S13be defined as one cycle and the cycle be repeated. As another example, an In—Zn oxide can be deposited by repeating a cycle composed of Step S11and Step S12. In the step of introducing the precursor412in Step S12, the precursor413may also be introduced to form an (M,Zn) layer in Step S12. In the step of introducing the precursor411in Step S11, the precursor412or the precursor413may also be introduced to form an In layer containing the element M or Zn in Step S11. With such an appropriate combination, the desired oxide230can be deposited.

The description of the above embodiment can be referred to for a manufacturing apparatus used for the deposition by an ALD method. When the oxide230and the ferroelectric layer are deposited by an ALD method, the same manufacturing apparatus can be used. Furthermore, in the case where the element illustrated in FIG.1B2is fabricated, the insulator130can be successively deposited over the oxide230by changing a precursor and an oxidizing gas after deposition of the oxide230. This enables the oxide230and the insulator130to be deposited without exposure to the air, so that the vicinity of an interface between the oxide230and the insulator130can be kept clean.

Two or more manufacturing apparatuses used for the deposition by an ALD method may be incorporated into a multi-chamber deposition apparatus. In this case, setting is made such that the oxide230and the ferroelectric layer are deposited by different manufacturing apparatuses, whereby the oxide230and the ferroelectric layer can be successively deposited without changing the precursor and the oxidizing gas.

As illustrated inFIG.11Cor the like, the insulator252formed using aluminum oxide or the like is provided in contact with the top surface and the side surface of the oxide230, whereby indium contained in the oxide230is unevenly distributed, in some cases, at the interface between the oxide230and the insulator252and in its vicinity. Accordingly, the vicinity of the surface of the oxide230comes to have an atomic ratio close to that of an indium oxide or that of an In-Zn oxide. Such an increase in the atomic ratio of indium in the vicinity of the surface of the oxide230, especially the vicinity of a surface of the oxide230b, can increase the field-effect mobility of the transistor200.

When the oxide230aand the oxide230bhave the above structure, the density of defect states at the interface between the oxide230aand the oxide230bcan be made low. Thus, the influence of interface scattering on carrier conduction is small, and the transistor200can have a high on-state current and excellent frequency characteristics.

At least one of the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285preferably functions as a barrier insulating film, which inhibits diffusion of impurities such as water and hydrogen from the substrate side or above the transistor200into the transistor200. Thus, for at least one of the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285, it is preferable to use an insulating material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N2O, NO, or NO2), and a copper atom (an insulating material through which the impurities are less likely to pass). Alternatively, it is preferable to use an insulating material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like) (an insulating material through which the oxygen is less likely to pass).

Note that in this specification, a barrier insulating film refers to an insulating film having a barrier property. A barrier property in this specification means a function of inhibiting diffusion of a targeted substance (also referred to as having low permeability). In addition, a barrier property in this specification means a function of capturing and fixing (also referred to as gettering) a targeted substance.

An insulator having a function of inhibiting diffusion of oxygen and impurities such as water and hydrogen is preferably used as the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285; for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used for the insulator212, the insulator275, and the insulator283. For example, aluminum oxide or magnesium oxide, which has a function of capturing or fixing hydrogen well, is preferably used for the insulator214, the insulator271, the insulator282, and the insulator285. In this case, impurities such as water and hydrogen can be inhibited from diffusing to the transistor200side from the substrate side through the insulator212and the insulator214. Impurities such as water and hydrogen can be inhibited from diffusing to the transistor200side from an interlayer insulating film and the like which are provided outside the insulator285. Alternatively, oxygen contained in the insulator224and the like can be inhibited from diffusing to the substrate side through the insulator212and the insulator214. Alternatively, oxygen contained in the insulator280and the like can be inhibited from diffusing to above the transistor200through the insulator282and the like. In this manner, it is preferable that the transistor200be surrounded by the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285, which have a function of inhibiting diffusion of oxygen and impurities such as water and hydrogen.

Here, an oxide having an amorphous structure is preferably used for the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285. For example, a metal oxide such as AlOx(x is a given number greater than 0) or MgOy(y is a given number greater than 0) is preferably used. In such a metal oxide having an amorphous structure, an oxygen atom has a dangling bond and sometimes has a property of capturing or fixing hydrogen with the dangling bond. When such a metal oxide having an amorphous structure is used as the component of the transistor200or provided around the transistor200, hydrogen contained in the transistor200or hydrogen present around the transistor200can be captured or fixed. In particular, hydrogen contained in the channel formation region of the transistor200is preferably captured or fixed. The metal oxide having an amorphous structure is used as the component of the transistor200or provided around the transistor200, whereby the transistor200and a semiconductor device which have favorable characteristics and high reliability can be fabricated.

Although each of the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285preferably has an amorphous structure, a region having a polycrystalline structure may be partly formed. Alternatively, each of the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285may have a multilayer structure where a layer having an amorphous structure and a layer having a polycrystalline structure are stacked. For example, a stacked-layer structure where a layer having a polycrystalline structure is formed over a layer having an amorphous structure may be employed.

The insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285can be deposited by a sputtering method, for example. Since a sputtering method does not need to use a molecule containing hydrogen as a deposition gas, the hydrogen concentrations in the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285can be reduced. Note that the deposition method is not limited to a sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like may be used as appropriate.

The resistivities of the insulator212, the insulator275, and the insulator283are preferably low in some cases. For example, by setting the resistivities of the insulator212, the insulator275, and the insulator283to approximately 1×1013Ωcm, the insulator212, the insulator275, and the insulator283can sometimes reduce charge up of the conductor205, the conductor242, the conductor260, or the conductor110in treatment using plasma or the like in the fabrication process of a semiconductor device. The resistivities of the insulator212, the insulator275, and the insulator283are preferably higher than or equal to 1×1010Ωcm and lower than or equal to 1×1015Ωcm.

The insulator216, the insulator274, the insulator280, and the insulator285each preferably have a lower permittivity than the insulator214. When a material with a low permittivity is used for an interlayer film, parasitic capacitance generated between wirings can be reduced. For the insulator216, the insulator274, the insulator280, and the insulator285, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like is used as appropriate, for example.

The conductor205is placed to overlap with the oxide230and the conductor260. Here, the conductor205is preferably provided to be embedded in an opening formed in the insulator216. Part of the conductor205is embedded in the insulator214in some cases.

The conductor205includes the conductor205aand the conductor205b. The conductor205ais provided in contact with the bottom surface and the sidewall of the opening. The conductor205bis provided to be embedded in a depressed portion formed by the conductor205a. Here, the top surface of the conductor205bis substantially level with the top surface of the conductor205aand the top surface of the insulator216.

Here, for the conductor205a, it is preferable to use a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, or the like), and a copper atom. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like).

When the conductor205ais formed using a conductive material having a function of inhibiting diffusion of hydrogen, impurities such as hydrogen contained in the conductor205bcan be prevented from diffusing into the oxide230through the insulator224and the like. When the conductor205ais formed using a conductive material having a function of inhibiting diffusion of oxygen, the conductivity of the conductor205bcan be inhibited from being lowered because of oxidation. As the conductive material having a function of inhibiting diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Thus, the conductor205amay be a single layer or stacked layers of the above conductive materials. For example, titanium nitride is used for the conductor205a.

Moreover, the conductor205bis preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. For example, tungsten is used for the conductor205b.

The conductor205sometimes functions as a second gate electrode. In that case, by changing a potential applied to the conductor205not in conjunction with but independently of a potential applied to the conductor260, the threshold voltage (Vth) of the transistor200can be controlled. In particular, Vth of the transistor200can be higher in the case where a negative potential is applied to the conductor205, and the off-state current can be reduced. Thus, a drain current at the time when a potential applied to the conductor260is 0 V can be lower in the case where a negative potential is applied to the conductor205than in the case where the negative potential is not applied to the conductor205.

The electric resistivity of the conductor205is designed in consideration of the potential applied to the conductor205, and the thickness of the conductor205is determined in accordance with the electric resistivity. The thickness of the insulator216is substantially equal to that of the conductor205. The conductor205and the insulator216are preferably as thin as possible in the allowable range of the design of the conductor205. When the thickness of the insulator216is reduced, the absolute amount of impurities such as hydrogen contained in the insulator216can be reduced, thereby reducing the amount of the impurities to be diffused into the oxide230.

As illustrated inFIG.11A, the conductor205is preferably provided to be larger than a region of the oxide230not overlapping with the conductor242aor the conductor242b. As illustrated inFIG.11C, it is particularly preferable that the conductor205extend to a region outside end portions of the oxide230aand the oxide230bin the channel width direction. That is, the conductor205and the conductor260preferably overlap with each other with the insulators therebetween on the outer side of the side surface of the oxide230in the channel width direction. With this structure, the channel formation region of the oxide230can be electrically surrounded by the electric field of the conductor260functioning as a first gate electrode and the electric field of the conductor205functioning as the second gate electrode. In this specification, a transistor structure where a channel formation region is electrically surrounded by electric fields of a first gate and a second gate is referred to as a surrounded channel (S-channel) structure.

In this specification and the like, a transistor having the S-channel structure refers to a transistor having a structure where a channel formation region is electrically surrounded by the electric fields of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from a Fin-type structure and a planar structure. With the S-channel structure, resistance to a short-channel effect can be enhanced, that is, a transistor in which a short-channel effect is less likely to occur can be provided.

Furthermore, as illustrated inFIG.11C, the conductor205is extended to function as a wiring as well. However, without limitation to this structure, a structure where a conductor functioning as a wiring is provided below the conductor205may be employed. In addition, the conductor205is not necessarily provided in each transistor. For example, the conductor205may be shared by a plurality of transistors.

Although the transistor200having a structure where the conductor205is a stack of the conductor205aand the conductor205bis illustrated, the present invention is not limited thereto. For example, the conductor205may be provided to have a single-layer structure or a stacked-layer structure of three or more layers.

The insulator222and the insulator224function as a gate insulator.

It is preferable that the insulator222have a function of inhibiting diffusion of hydrogen (e.g., at least one of a hydrogen atom, a hydrogen molecule, and the like). In addition, it is preferable that the insulator222have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like). For example, the insulator222preferably has a function of inhibiting diffusion of one or both of hydrogen and oxygen more than the insulator224.

As the insulator222, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material, is preferably used. For the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Alternatively, an oxide containing hafnium and zirconium, e.g., a hafnium-zirconium oxide is preferably used. In the case where the insulator222is formed using such a material, the insulator222functions as a layer that inhibits release of oxygen from the oxide230to the substrate side and diffusion of impurities such as hydrogen from the periphery of the transistor200into the oxide230. Thus, providing the insulator222can inhibit diffusion of impurities such as hydrogen into the transistor200and inhibit generation of oxygen vacancies in the oxide230. Moreover, the conductor205can be inhibited from reacting with oxygen contained in the insulator224and the oxide230.

For example, a single layer or stacked layers of an insulator(s) containing what is called a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium-zirconium oxide may be used for the insulator222. As miniaturization and high integration of transistors progress, a problem such as a leakage current may arise because of a thinner gate insulator. When a high-k material is used for an insulator functioning as the gate insulator, a gate potential at the time when the transistor operates can be reduced while the physical thickness is maintained. Furthermore, a substance with a high permittivity such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3(BST) may be used for the insulator222.

Silicon oxide or silicon oxynitride, for example, can be used as appropriate for the insulator224that is in contact with the oxide230.

In a fabrication process of the transistor200, heat treatment is preferably performed with a surface of the oxide230exposed. For example, the heat treatment is performed at higher than or equal to 100° C. and lower than or equal to 600° C., preferably higher than or equal to 350° C. and lower than or equal to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This can supply oxygen to the oxide230to reduce oxygen vacancies (Vo). The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen, after heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere successively after heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.

Note that oxygen adding treatment performed on the oxide230can promote a reaction in which oxygen vacancies in the oxide230are repaired with supplied oxygen, i.e., a reaction of “VO+O→null”. Furthermore, hydrogen remaining in the oxide230reacts with supplied oxygen, so that the hydrogen can be removed as H2O (dehydration). This can inhibit recombination of hydrogen remaining in the oxide230with oxygen vacancies and formation of VoH.

Note that the insulator222and the insulator224may each have a stacked-layer structure of two or more layers. In that case, without limitation to a stacked-layer structure formed of the same material, a stacked-layer structure formed of different materials may be employed. The insulator224may be formed into an island shape so as to overlap with the oxide230a. In this case, the insulator275is in contact with the side surface of the insulator224and the top surface of the insulator222.

The conductor242aand the conductor242bare provided in contact with the top surface of the oxide230b. Each of the conductor242aand the conductor242bfunctions as the source electrode or the drain electrode of the transistor200.

For the conductor242(the conductor242aand the conductor242b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. As another example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are each a conductive material that is not easily oxidized or a material that maintains the conductivity even after absorbing oxygen.

Note that hydrogen contained in the oxide230bor the like diffuses into the conductor242aor the conductor242bin some cases. In particular, when a nitride containing tantalum is used for the conductor242aand the conductor242b, hydrogen contained in the oxide230bor the like is likely to diffuse into the conductor242aor the conductor242b, and the diffused hydrogen is bonded to nitrogen contained in the conductor242aor the conductor242bin some cases. That is, hydrogen contained in the oxide230bor the like is absorbed by the conductor242aor the conductor242bin some cases.

No curved surface is preferably formed between the side surface of the conductor242and the top surface of the conductor242. When no curved surface is formed in the conductor242, the conductor242can have a large cross-sectional area in the channel width direction as illustrated inFIG.11D. Accordingly, the conductivity of the conductor242is increased, so that the on-state current of the transistor200can be increased.

The insulator271ais provided in contact with the top surface of the conductor242a, and the insulator271bis provided in contact with the top surface of the conductor242b. The insulator271preferably functions as at least a barrier insulating film against oxygen. Thus, the insulator271preferably has a function of inhibiting oxygen diffusion. For example, the insulator271preferably has a function of inhibiting diffusion of oxygen more than the insulator280. As the insulator271, an insulator such as aluminum oxide or magnesium oxide is used, for example.

The insulator275is provided to cover the insulator224, the oxide230a, the oxide230b, the conductor242, and the insulator271. The insulator275preferably has a function of capturing and fixing hydrogen. In that case, the insulator275preferably includes silicon nitride, or a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide or magnesium oxide. Alternatively, for example, a stacked-layer film of aluminum oxide and silicon nitride over the aluminum oxide may be used as the insulator275.

When the above insulator271and the insulator275are provided, the conductor242can be surrounded by the insulators having a barrier property against oxygen. That is, oxygen contained in the insulator224and the insulator280can be prevented from diffusing into the conductor242. As a result, the conductor242can be inhibited from being directly oxidized by oxygen contained in the insulator224and the insulator280, so that an increase in resistivity and a reduction in on-state current can be inhibited.

The insulator252functions as part of the gate insulator. As the insulator252, a barrier insulating film against oxygen is preferably used. As the insulator252, an insulator that can be used as the insulator282described above may be used. An insulator containing an oxide of one or both of aluminum and hafnium is preferably used as the insulator252. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In this embodiment, aluminum oxide is used for the insulator252. In this case, the insulator252is an insulator containing at least oxygen and aluminum.

As illustrated inFIG.11C, the insulator252is provided in contact with the top surface and the side surface of the oxide230b, the side surface of the oxide230a, the side surface of the insulator224, and the top surface of the insulator222. That is, the regions of the oxide230a, the oxide230b, and the insulator224that overlap with the conductor260are covered with the insulator252in the cross section in the channel width direction. With this structure, the insulator252having a barrier property against oxygen can prevent release of oxygen from the oxide230aand the oxide230bat the time of heat treatment or the like. This can inhibit formation of oxygen vacancies (Vo) in the oxide230aand the oxide230b. Therefore, oxygen vacancies (Vo) and VoH formed in the region230bccan be reduced. Thus, the transistor200can have favorable electrical characteristics and higher reliability.

Even when an excess amount of oxygen is contained in the insulator280, the insulator250and the like, oxygen can be inhibited from being excessively supplied to the oxide230aand the oxide230b. Thus, the region230baand the region230bbare inhibited from being excessively oxidized by oxygen through the region230bc; a reduction in on-state current or field-effect mobility of the transistor200can be inhibited.

As illustrated inFIG.11B, the insulator252is provided in contact with the side surfaces of the conductor242, the insulator271, the insulator275, and the insulator280. This can inhibit formation of an oxide film on the side surface of the conductor242by oxidization of the side surface. Accordingly, a reduction in on-state current or field-effect mobility of the transistor200can be inhibited.

Furthermore, the insulator252needs to be provided in an opening formed in the insulator280and the like, together with the insulator254, the insulator250, and the conductor260. The thickness of the insulator252is preferably small for miniaturization of the transistor200. The thickness of the insulator252is greater than or equal to 0.1 nm and less than or equal to 5.0 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3.0 nm, further preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm. In this case, at least part of the insulator252preferably includes a region having the above-described thickness. The thickness of the insulator252is preferably smaller than that of the insulator250. In this case, at least part of the insulator252preferably includes a region having a thickness smaller than that of the insulator250.

To deposit the insulator252having a small thickness like the above-described thickness, an ALD method is preferably used for deposition. Examples of an ALD method include a thermal ALD method, in which a precursor and a reactant react with each other only by a thermal energy, and a PEALD (Plasma Enhanced ALD) method, in which a reactant excited by plasma is used. The use of plasma in a PEALD method is sometimes preferable because deposition at a lower temperature is possible.

An ALD method, which enables an atomic layer to be deposited one by one using self-limiting characteristics by atoms, has advantages such as deposition of an extremely thin film, deposition on a component with a high aspect ratio, deposition of a film with a small number of defects such as pinholes, deposition with excellent coverage, and low-temperature deposition. Therefore, the insulator252can be deposited on the side surface of the opening formed in the insulator280and the like to have a small thickness like the above-described thickness and to have favorable coverage.

Note that some of precursors usable in an ALD method contain carbon or the like. Thus, in some cases, a film provided by an ALD method contains impurities such as carbon in a larger amount than a film provided by another deposition method. Note that impurities can be quantified by secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or auger electron spectroscopy (AES).

The insulator250functions as part of the gate insulator. The insulator250is preferably placed to be in contact with the top surface of the insulator252. The insulator250can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable. The insulator250in this case is an insulator containing at least oxygen and silicon.

As in the insulator224, the concentration of impurities such as water and hydrogen in the insulator250is preferably reduced. The thickness of the insulator250is preferably greater than or equal to 1 nm and less than or equal to 20 nm, further preferably greater than or equal to 0.5 nm and less than or equal to 15.0 nm. In this case, it is acceptable that at least part of the insulator250has a region with a thickness like the above-described thickness.

AlthoughFIG.11AtoFIG.11Dand the like illustrate a single-layer structure of the insulator250, the present invention is not limited to this structure, and a stacked-layer structure of two or more layers may be employed. For example, as illustrated inFIG.12B, the insulator250may have a stacked-layer structure including two layers of an insulator250aand an insulator250bover the insulator250a.

In the case where the insulator250has a stacked-layer structure of two layers as illustrated inFIG.12B, it is preferable that the insulator250ain a lower layer be formed using an insulator that is likely to transmit oxygen and the insulator250bin an upper layer be formed using an insulator having a function of inhibiting oxygen diffusion. With such a structure, oxygen contained in the insulator250acan be inhibited from diffusing into the conductor260. That is, a reduction in the amount of oxygen supplied to the oxide230can be inhibited. In addition, oxidation of the conductor260due to oxygen contained in the insulator250acan be inhibited. For example, it is preferable that the insulator250abe provided using any of the above-described materials that can be used for the insulator250and the insulator250bbe provided using an insulator containing an oxide of one or both of aluminum and hafnium. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In this embodiment, hafnium oxide is used as the insulator250b. In this case, the insulator250bis an insulator containing at least oxygen and hafnium. The thickness of the insulator250bis greater than or equal to 0.5 nm and less than or equal to 5.0 nm, preferably greater than or equal to 1.0 nm and less than or equal to 5.0 nm, further preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm. In this case, at least part of the insulator250bmay include a region having a thickness like the above-described thickness.

In the case where silicon oxide, silicon oxynitride, or the like is used for the insulator250a, the insulator250bmay be formed using an insulating material that is a high-k material having a high dielectric constant. The gate insulator having a stacked-layer structure of the insulator250aand the insulator250bcan be thermally stable and can have a high dielectric constant. Thus, a gate potential that is applied during operation of the transistor can be reduced while the physical thickness of the gate insulator is maintained. In addition, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. Therefore, the withstand voltage of the insulator250can be increased.

The insulator254functions as part of a gate insulator. As the insulator254, a barrier insulating film against hydrogen is preferably used. This can prevent diffusion of impurities such as hydrogen contained in the conductor260into the insulator250and the oxide230b. As the insulator254, an insulator that can be used as the insulator283described above can be used. For example, silicon nitride deposited by a PEALD method may be used as the insulator254. In this case, the insulator254is an insulator containing at least nitrogen and silicon.

Furthermore, the insulator254may have a barrier property against oxygen. Thus, diffusion of oxygen contained in the insulator250into the conductor260can be inhibited.

Furthermore, the insulator254needs to be provided in an opening formed in the insulator280and the like, together with the insulator252, the insulator250, and the conductor260. The thickness of the insulator254is preferably small for miniaturization of the transistor200. The thickness of the insulator254is greater than or equal to 0.1 nm and less than or equal to 5.0 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3.0 nm, further preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm. In this case, at least part of the insulator254preferably includes a region having the above-described thickness. The thickness of the insulator254is preferably smaller than that of the insulator250. In this case, at least part of the insulator254preferably includes a region having a thickness that is smaller than that of the insulator250.

The conductor260functions as the first gate electrode of the transistor200. The conductor260preferably includes the conductor260aand the conductor260bplaced over the conductor260a. For example, the conductor260ais preferably placed to cover the bottom surface and the side surface of the conductor260b. Moreover, as illustrated inFIG.11BandFIG.11C, the top surface of the conductor260is substantially level with the top surface of the insulator250. Although the conductor260has a two-layer structure of the conductor260aand the conductor260binFIG.11BandFIG.11C, the conductor260may have a single-layer structure or a stacked-layer structure of three or more layers.

For the conductor260a, a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule, and a copper atom is preferably used. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like).

In addition, when the conductor260ahas a function of inhibiting diffusion of oxygen, the conductivity of the conductor260bcan be inhibited from being lowered because of oxidation due to oxygen contained in the insulator250. As the conductive material having a function of inhibiting diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

The conductor260also functions as a wiring and thus is preferably formed using a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used for the conductor260b. The conductor260bmay have a stacked-layer structure; for example, a stacked-layer structure of the above conductive material and titanium or titanium nitride may be employed.

In the transistor200, the conductor260is formed in a self-aligned manner to fill the opening formed in the insulator280and the like. The formation of the conductor260in this manner allows the conductor260to be placed properly in a region between the conductor242aand the conductor242bwithout alignment.

As illustrated inFIG.11C, in the channel width direction of the transistor200, with reference to the bottom surface of the insulator222, the level of the bottom surface of the conductor260in a region where the conductor260and the oxide230bdo not overlap is preferably lower than the level of the bottom surface of the oxide230b. When the conductor260functioning as the gate electrode covers the side surface and the top surface of the channel formation region of the oxide230bwith the insulator250and the like therebetween, the electric field of the conductor260can easily act on the entire channel formation region of the oxide230b. Thus, the on-state current of the transistor200can be increased and the frequency characteristics of the transistor200can be improved. With a reference to the bottom surface of the insulator222, the difference between the level of the bottom surface of the conductor260in a region where the conductor260do not overlap with the oxide230aor the oxide230band the level of the bottom surface of the oxide230bis greater than or equal to 0 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm, further preferably greater than or equal to 5 nm and less than or equal to 20 nm.

The insulator280is provided over the insulator275, and the opening is formed in a region where the insulator250and the conductor260are to be provided. In addition, the top surface of the insulator280may be planarized.

The insulator280functioning as an interlayer film preferably has a low permittivity. When a material with a low permittivity is used for an interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator280is preferably provided using a material similar to that for the insulator216, for example. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable. Materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are particularly preferable because a region containing oxygen to be released by heating can be easily formed.

The insulator280preferably includes an excess-oxygen region or excess oxygen. The concentration of impurities such as water and hydrogen in the insulator280is preferably reduced. Silicon oxide, silicon oxynitride, or the like may be used as appropriate for the insulator280, for example. When an insulator containing excess oxygen is provided in contact with the oxide230, oxygen vacancies in the oxide230can be reduced and the reliability of the transistor200can be improved. When the insulator280is formed by a sputtering method in an oxygen-containing atmosphere, the insulator280containing excess oxygen can be formed. By a sputtering method that does not need to use hydrogen as a deposition gas, the concentration of hydrogen in the insulator280can be reduced. The insulator282in contact with the top surface of the insulator280may be formed by a sputtering method in an atmosphere containing oxygen so that oxygen can be supplied to the insulator280. In the case where oxygen is supplied to the insulator280by depositing the insulator282, the deposition method of the insulator280is not limited to a sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be employed. For example, the insulator280may have a stacked-layer structure of silicon oxide deposited by a sputtering method and silicon oxynitride deposited thereover by a CVD method. Furthermore, silicon nitride may be stacked thereover.

The insulator282preferably functions as a barrier insulating film that inhibits impurities such as water and hydrogen from diffusing into the insulator280from above and preferably has a function of capturing impurities such as hydrogen. The insulator282preferably functions as a barrier insulating film that inhibits passage of oxygen. For the insulator282, a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide can be used. In this case, the insulator282is an insulator containing at least oxygen and aluminum. The insulator282, which has a function of capturing impurities such as hydrogen, is provided in contact with the insulator280in a region interposed between the insulator212and the insulator283, whereby impurities such as hydrogen contained in the insulator280and the like can be captured and the amount of hydrogen in the region can be constant. It is preferable to use, in particular, aluminum oxide having an amorphous structure for the insulator282, because hydrogen can be captured or fixed more effectively in some cases. Accordingly, the transistor200and a semiconductor device which have favorable characteristics and high reliability can be fabricated.

The insulator282is preferably formed by a sputtering method. When the insulator282is deposited by a sputtering method, oxygen can be added to the insulator280. The deposition method of the insulator282is not limited to a sputtering method; a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.

The insulator283functions as a barrier insulating film that inhibits impurities such as water and hydrogen from diffusing into the insulator280from above. The insulator283is placed over the insulator282. The insulator283is preferably formed using a nitride containing silicon such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by a sputtering method may be used for the insulator283. When the insulator283is deposited by a sputtering method, a high-density silicon nitride film can be formed. To obtain the insulator283, silicon nitride deposited by a PEALD method or a CVD method may be stacked over silicon nitride deposited by a sputtering method.

The capacitor100is placed in the opening that is formed in the insulator271, the insulator275, the insulator280, the insulator282, the insulator283, and the insulator285and includes the conductor110in contact with the top surface of the conductor242b, the insulator130over the conductor110and the insulator283, and the conductor120over the insulator130. Note that the conductor120has a stacked-layer structure of the conductor120aover the insulator130and the conductor120bover the conductor120a. Here, at least parts of the conductor110, the insulator130, and the conductor120are placed in the opening that is formed in the insulator271, the insulator275, the insulator280, the insulator282, the insulator283, and the insulator285.

The conductor110functions as a lower electrode of the capacitor100, the conductor120functions as an upper electrode of the capacitor100, and the insulator130functions as a dielectric of the capacitor100. In the capacitor100, the upper electrode and the lower electrode face each other with the dielectric therebetween on the side surface as well as the bottom surface of the opening that is formed in the insulator271, the insulator275, the insulator280, the insulator282, the insulator283, and the insulator285; thus, the capacitance per unit area can be increased. Thus, the deeper the opening is, the larger the capacitance of the capacitor100can be. Increasing the capacitance per unit area of the capacitor100in this manner can promote miniaturization or higher integration of the semiconductor device.

The shape of the opening that is formed in the insulator271, the insulator275, the insulator280, the insulator282, the insulator283, and the insulator285when seen from above may be a quadrangular shape, a polygonal shape other than a quadrangular shape, a polygonal shape with rounded corners, or a circular shape including an elliptical shape. Here, the area where the opening and the transistor200overlap each other is preferably large in the top view. For example, as illustrated inFIG.11A, the capacitor100is preferably provided so that the capacitor100can fit in the area of the conductor242bin the top view. In this case, the length of the conductor110in the channel width direction is smaller than the length of the conductor242bin the channel width direction. Such a structure can reduce the area occupied by the semiconductor device including the capacitor100and the transistor200. The structure is not limited thereto and the length of the conductor110in the channel width direction can be larger than the length of the conductor242bin the channel width direction.

The conductor110is placed along the opening that is formed in the insulator271, the insulator275, the insulator280, the insulator282, the insulator283, and the insulator285. Here, the opening preferably has a shape in which the side surface and the bottom surface of the opening is connected with a curved surface. With this structure, the conductor110can be deposited in the opening with favorable coverage.

Furthermore, part of the top surface of the conductor110is preferably substantially level with the top surface of the insulator285. The top surface of the conductor242bis in contact with the bottom surface of the conductor110. The conductor110is preferably deposited by an ALD method, a CVD method, or the like and a conductor described in the above embodiment can be used. For example, titanium nitride deposited by a thermal ALD method can be used as the conductor110.

The insulator130is placed to cover the conductor110, the insulator245, and part of the insulator285. Here, the top surface of the insulator285becomes higher in a region where the insulator285overlaps with the insulator130than in a region where the insulator285does not overlap with the insulator130, in some cases. The insulator130is preferably deposited by an ALD method, a CVD method, or the like. The insulator130is preferably formed using a material that can have ferroelectricity.

As examples of the material that can have ferroelectricity, hafnium oxide, zirconium oxide, HfZrOX(X is a real number greater than 0), a material obtained by adding the element J1(the element J1here is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), or strontium (Sr), for example) to hafnium oxide, and a material obtained by adding the element J2(the element J2here is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), or strontium (Sr), for example) to zirconium oxide can be given. As the material that can have ferroelectricity, a piezoelectric ceramic having a perovskite structure such as PbTiOx, barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used. As the material that can have ferroelectricity, a mixture or compound containing a plurality of materials selected from the above-described materials can be used, for example. Alternatively, the insulator130can have a stacked-layer structure of a plurality of materials selected from the above-described materials. Note that since the crystal structures (properties) of hafnium oxide, zirconium oxide, HfZrOX, the material obtained by adding the element J1to hafnium oxide, and the like can be changed depending on the processes as well as the deposition conditions, a material that exhibits ferroelectricity is referred to as a material that can have ferroelectricity as well as a ferroelectric in this specification or the like.

Hafnium oxide or a material containing hafnium oxide and zirconium oxide is especially preferable as the material that can have ferroelectricity because of being able to have ferroelectricity even when processed into a several-nanometer-thick thin film. Here, the thickness of the insulator130can be less than or equal to 100 nm, preferably less than or equal to 50 nm, further preferably less than or equal to 20 nm, still further preferably less than or equal to 10 nm. When the ferroelectric layer that can be thin is used, the capacitor100can be combined with the miniaturized transistor200to form a semiconductor device. Note that in this specification and the like, a layer of the material that can have ferroelectricity is referred to as a ferroelectric layer or a metal oxide film, in some cases.

The material that can have ferroelectricity is an insulator and has a property in which application of an electric field from the outside causes internal polarization and the polarization remains even after the electric field is made zero. Thus, with a capacitor using such a material as a dielectric (the capacitor may be referred to as a ferroelectric capacitor below), a nonvolatile storage element can be formed. A nonvolatile storage element using a ferroelectric capacitor is sometimes referred to as an FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, or the like. For example, a ferroelectric memory can have a structure including a transistor and a ferroelectric capacitor, where one of a source and a drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Thus, the semiconductor device including the capacitor100and the transistor200described in this embodiment can function as a ferroelectric memory.

Note that the insulator130can have a stacked-layer structure of the above-described material that can have ferroelectricity and a material having high dielectric strength, in some cases. Examples of the material having high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin. The use of such an insulator having high dielectric strength in the stacked-layer structure can increase the dielectric strength and inhibit a leakage current of the capacitor100in some cases.

The conductor120is placed to fill the opening that is formed in the insulator271, the insulator275, the insulator280, the insulator282, the insulator283, and the insulator285. Here, the conductor120preferably has a region overlapping with the insulator285with the insulator130therebetween. With such a structure, the conductor120can be insulated from the conductor110with the insulator130therebetween. Furthermore, a portion above the insulator283of the conductor120may be extended and formed as a wiring.

The conductor120preferably includes the conductor120aand the conductor120bover the conductor120a, as illustrated inFIG.11B. In this case, as the conductor120a, a thin conductive film with favorable coverage may be provided over the insulator130. The conductor120bmay be placed so as to fill the opening over the conductor120a. The conductor120ais preferably deposited by an ALD method, a CVD method, or the like and a conductor described in the above embodiment can be used. For example, titanium nitride deposited by an ALD method can be used as the conductor120a. The conductor120bis preferably deposited by an ALD method, a CVD method, a sputtering method, or the like and a conductor described in the above embodiment can be used. As the conductor120b, tungsten deposited by a sputtering method can be used. Note that the conductor120is not limited to the two-layer structure, and may have a single-layer structure or a stacked-layer structure of three or more layers.

A conductor functioning as a wiring may be placed in contact with the top surface of the conductor120. For the conductor, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used. Furthermore, the conductor may have a stacked-layer structure and may be stacked layers of the above conductive material and titanium or titanium nitride, for example. Note that the conductor may be formed to be embedded in an opening provided in an insulator.

The insulator245is preferably placed in contact with the side surface of the opening that is formed in the insulator271, the insulator275, the insulator280, the insulator282, the insulator283, and the insulator285. The conductor110is provided in contact with the inner side surface of the insulator245, the insulator130is provided in contact with the inner side surface of the conductor110, and the conductor120is provided in contact with the inner side surface of the insulator130.

As the insulator245, a barrier insulating film that can be used for the insulator275or the like can be used. For example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide can be used for the insulator245. Since the insulator245is provided in contact with the insulator283, the insulator282, the insulator275, and the insulator271, impurities such as water and hydrogen contained in the insulator280, the insulator285, or the like can be inhibited from entering the oxide230through the conductor110. In particular, silicon nitride is suitable because of its high blocking property against hydrogen. Moreover, oxygen contained in the insulator280can be prevented from being absorbed by the conductor110.

In the case where the insulator245has a stacked-layer structure illustrated inFIG.11B, a first insulator in contact with an inner wall of the opening in the insulator280and the like and a second insulator on the inner side of the first insulator are preferably formed using a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen. For example, aluminum oxide deposited by an ALD method can be used as the first insulator and silicon nitride deposited by a PEALD method can be used as the second insulator. With such a structure, oxidation of the conductor110can be inhibited, and hydrogen can be prevented from entering the conductor110.

Although the structure where the first insulator and the second insulator are stacked as the insulator245is illustrated, the present invention is not limited thereto. For example, the insulator245may have a single-layer structure or a stacked-layer structure of three or more layers.

<Component Materials of Semiconductor Device>

Component materials that can be used for the semiconductor device are described below.

As a substrate where the transistor200is formed, an insulator substrate, a semiconductor substrate, or a conductor substrate is used, for example. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate using silicon or germanium as a material and a compound semiconductor substrate including silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Another example is a semiconductor substrate having an insulator region in the semiconductor substrate described above, e.g., an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Other examples include a substrate including a metal nitride and a substrate including a metal oxide. Other examples include an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator. Alternatively, these substrates provided with elements may be used. Examples of the element provided for the substrate include a capacitor element, a resistor, a switching element, a light-emitting element, and a storage element.

Examples of the insulator include an insulating oxide, an insulating nitride, an insulating oxynitride, an insulating nitride oxide, an insulating metal oxide, an insulating metal oxynitride, and an insulating metal nitride oxide.

As miniaturization and high integration of transistors progress, for example, a problem such as a leakage current may arise because of a thinner gate insulator. When a high-k material is used for the insulator functioning as a gate insulator, the voltage during operation of the transistor can be lowered while the physical thickness of the gate insulator is maintained. In contrast, when a material with a low dielectric constant is used for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Thus, a material is preferably selected depending on the function of an insulator.

Examples of the insulator with a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

Examples of the insulator with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin.

When a transistor including a metal oxide is surrounded by an insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, the transistor can have stable electrical characteristics. As the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a single layer or stacked layers of an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum are used. Specifically, as the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride can be used.

The insulator functioning as the gate insulator is preferably an insulator including a region containing oxygen to be released by heating. For example, when a structure is employed where silicon oxide or silicon oxynitride including a region containing oxygen to be released by heating is in contact with the oxide230, oxygen vacancies included in the oxide230can be compensated for.

A stack of a plurality of conductive layers formed of the above materials may be used. For example, a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen may be employed. Alternatively, a stacked-layer structure combining a material containing the above metal element and a conductive material containing nitrogen may be employed. Alternatively, a stacked-layer structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

In the case where an oxide is used for the channel formation region of the transistor, the conductor functioning as the gate electrode preferably employs a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. When the conductive material containing oxygen is provided on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

For the conductor functioning as the gate electrode, it is preferable to use, in particular, a conductive material containing oxygen and a metal element contained in the metal oxide where the channel is formed. Alternatively, a conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may be used. With the use of such a material, hydrogen contained in the metal oxide where the channel is formed can be captured in some cases. Alternatively, hydrogen entering from an external insulator or the like can be captured in some cases.

The oxide230is preferably formed using a metal oxide functioning as a semiconductor (an oxide semiconductor). A metal oxide that can be used as the oxide230of the present invention is described below.

Note that in this specification and the like, a metal oxide containing nitrogen is also collectively referred to as a metal oxide in some cases. A metal oxide containing nitrogen may be referred to as a metal oxynitride.

<Classification of Crystal Structure>

First, the classification of the crystal structures of an oxide semiconductor will be described with reference toFIG.13A.FIG.13Ais a diagram showing the classification of crystal structures of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

As shown inFIG.13A, an oxide semiconductor is roughly classified into “Amorphous”, “Crystalline”, and “Crystal”. “Amorphous” includes completely amorphous. “Crystalline” includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and polycrystal). Note that “Crystalline” excludes single crystal, poly crystal, and completely amorphous. “Crystal” includes single crystal and poly crystal.

Note that the structures in the thick frame inFIG.13Aare in an intermediate state between “Amorphous” and “Crystal”, and belong to a new crystalline phase. That is, these structures are completely different from “Amorphous”, which is energetically unstable, and “Crystal”.

A crystal structure of a film or a substrate can be evaluated with an X-Ray Diffraction (XRD) spectrum. Here,FIG.13Bshows an XRD spectrum, which is obtained by GIXD (Grazing-Incidence XRD) measurement, of a CAAC-IGZO film classified into “Crystalline”. Note that a GIXD method is also referred to as a thin film method or a Seemann-Bohlin method. The XRD spectrum that is shown inFIG.13Band obtained by GIXD measurement may be hereinafter simply referred to as an XRD spectrum in this specification. The CAAC-IGZO film inFIG.13Bhas a composition in the neighborhood of In:Ga:Zn=4:2:3 [atomic ratio]. The CAAC-IGZO film inFIG.13Bhas a thickness of 500 nm.

InFIG.13B, the horizontal axis represents20[deg.], and the vertical axis represents intensity [a.u.]. As shown inFIG.13B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis alignment is detected at20of around 31° in the XRD spectrum of the CAAC-IGZO film. As shown inFIG.13B, the peak at20of around 31° is asymmetric with respect to the axis of the angle at which the peak intensity is detected.

A crystal structure of a film or a substrate can also be evaluated with a diffraction pattern obtained by a nanobeam electron diffraction (NBED) method (such a pattern is also referred to as a nanobeam electron diffraction pattern).FIG.13Cshows a diffraction pattern of the CAAC-IGZO film.FIG.13Cshows a diffraction pattern obtained by the NBED method in which an electron beam is incident in the direction parallel to the substrate. The composition of the CAAC-IGZO film inFIG.13Cis In:Ga:Zn=4:2:3 [atomic ratio] or the neighborhood thereof. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

As shown inFIG.13C, a plurality of spots indicating c-axis alignment are observed in the diffraction pattern of the CAAC-IGZO film.

Here, the above-described CAAC-OS, nc-OS, and a-like OS are described in detail.

Note that each of the plurality of crystal regions is formed of one or more fine crystals (crystals each of which has a maximum diameter of less than 10 nm). In the case where the crystal region is formed of one fine crystal, the maximum diameter of the crystal region is less than 10 nm. In the case where the crystal region is formed of a large number of fine crystals, the size of the crystal region may be approximately several tens of nanometers.

In the case of an In-M-Zn oxide (the element M is one or more kinds selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, an (M,Zn) layer) are stacked. Indium and the element M can be replaced with each other. Therefore, indium may be contained in the (M,Zn) layer. In addition, the element M may be contained in the In layer. Note that Zn may be contained in the In layer. Such a layered structure is observed as a lattice image in a high-resolution TEM image, for example.

The CAAC-OS is an oxide semiconductor with high crystallinity in which no clear crystal grain boundary is observed. Thus, in the CAAC-OS, reduction in electron mobility due to the crystal grain boundary is less likely to occur. Moreover, since the crystallinity of an oxide semiconductor might be decreased by entry of impurities, formation of defects, or the like, the CAAC-OS can be regarded as an oxide semiconductor that has small amounts of impurities and defects (e.g., oxygen vacancies). Thus, an oxide semiconductor including the CAAC-OS is physically stable. Therefore, the oxide semiconductor including the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable with respect to high temperatures in the manufacturing process (what is called thermal budget). Accordingly, the use of the CAAC-OS for the OS transistor can extend the degree of freedom of the manufacturing process.

Next, the above-described CAC-OS is described in detail. Note that the CAC-OS relates to the material composition.

Here, the atomic ratios of In, Ga, and Zn to the metal elements contained in the CAC-OS in an In—Ga—Zn oxide are denoted by [In], [Ga], and [Zn], respectively. For example, the first region in the CAC-OS in the In—Ga—Zn oxide has [In] higher than [In] in the composition of the CAC-OS film. Moreover, the second region has [Ga] higher than [Ga] in the composition of the CAC-OS film. For example, the first region has [In] higher than [In] in the second region and has [Ga] lower than [Ga] in the second region. Moreover, the second region has [Ga] higher than [Ga] in the first region and has [In] lower than [In] in the first region.

Specifically, the first region includes indium oxide, indium zinc oxide, or the like as its main component. The second region includes gallium oxide, gallium zinc oxide, or the like as its main component. That is, the first region can be referred to as a region containing In as its main component. The second region can be referred to as a region containing Ga as its main component.

For example, energy dispersive X-ray spectroscopy (EDX) is used to obtain EDX mapping, and according to the EDX mapping, the CAC-OS in the In—Ga—Zn oxide has a structure where the region containing In as its main component (the first region) and the region containing Ga as its main component (the second region) are unevenly distributed and mixed.

In the case where the CAC-OS is used for a transistor, a switching function (on/off switching function) can be given to the CAC-OS owing to the complementary action of the conductivity derived from the first region and the insulating property derived from the second region. That is, the CAC-OS has a conducting function in part of the material and has an insulating function in another part of the material; as a whole, the CAC-OS has a function of a semiconductor. Separation of the conducting function and the insulating function can maximize each function. Accordingly, when the CAC-OS is used for a transistor, high on-state current (Ion), high field-effect mobility (μ), and excellent switching operation can be achieved.

An oxide semiconductor has various structures with different properties. Two or more kinds among the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the CAC-OS, the nc-OS, and the CAAC-OS may be included in the oxide semiconductor of one embodiment of the present invention.

Next, the case where the above oxide semiconductor is used for a transistor is described.

When the above oxide semiconductor is used for a transistor, a transistor with high field-effect mobility can be achieved. In addition, a transistor having high reliability can be achieved.

A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases.

Accordingly, in order to obtain stable electrical characteristics of a transistor, reducing the impurity concentration in an oxide semiconductor is effective. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable that the impurity concentration in an adjacent film be also reduced. Examples of impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon.

Here, the influence of each impurity in the oxide semiconductor is described.

Furthermore, when the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type by generation of electrons serving as carriers and an increase in carrier concentration. As a result, a transistor including an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. When nitrogen is contained in the oxide semiconductor, a trap state is sometimes formed. This might make the electrical characteristics of the transistor unstable. Therefore, the concentration of nitrogen in the channel formation region in the oxide semiconductor, which is obtained by SIMS, is set lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1018atoms/cm3, further preferably lower than or equal to 1×1018atoms/cm3, still further preferably lower than or equal to 5×1017atoms/cm3.

A semiconductor material that can be used for the oxide230is not limited to the above metal oxides. A semiconductor material that has a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the oxide230. For example, a single element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layered material functioning as a semiconductor (also referred to as an atomic layer material or a two-dimensional material) is preferably used as a semiconductor material. In particular, a layered material functioning as a semiconductor is preferably used as a semiconductor material.

Here, in this specification and the like, the layered material generally refers to a group of materials having a layered crystal structure. In the layered crystal structure, layers formed by covalent bonding or ionic bonding are stacked with bonding such as the Van der Waals force, which is weaker than covalent bonding or ionic bonding. The layered material has high electrical conductivity in a monolayer, that is, high two-dimensional electrical conductivity. When a material that functions as a semiconductor and has high two-dimensional electrical conductivity is used for a channel formation region, a transistor having a high on-state current can be provided.

Examples of the layered material include graphene, silicene, and chalcogenide. Chalcogenide is a compound containing chalcogen. Chalcogen is a general term of elements belonging to Group 16, which includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenide include transition metal chalcogenide and chalcogenide of Group 13 elements.

Variation Example of Semiconductor Device

Examples of the semiconductor device of one embodiment of the present invention will be described below with reference toFIG.14AtoFIG.16B.

A of each figure is a top view of the semiconductor device. Moreover, B of each figure is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A1-A2in A of each figure. Note that for clarity of the drawing, some components are omitted in the top view of A of each figure.

Note that in the semiconductor device illustrated in A and B of each figure, components having the same functions as the components included in the semiconductor device described in <Structure example of semiconductor device> are denoted by the same reference numerals. Note that the materials described in detail in <Structure example of semiconductor device> can also be used as component materials of the semiconductor devices in this section.

Variation Example 1 of Semiconductor Device

The semiconductor device illustrated inFIG.14AandFIG.14Bis a variation example of the semiconductor device illustrated inFIG.11AtoFIG.11D. The semiconductor device illustrated inFIG.14AandFIG.14Bis different from the semiconductor device illustrated inFIG.11AtoFIG.11Din being provided with a conductor240and a conductor246. Here, the conductor240functions as a plug electrically connected to one of the source and the drain of the transistor200, and the conductor246functions as a wiring connected to the plug.

The conductor240is provided so as to be embedded in an opening formed in the insulator271, the insulator275, the insulator280, the insulator282, the insulator283, and the insulator285. The bottom surface of the conductor240is in contact with the top surface of the conductor242a. For the conductor240, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used, for example. The conductor240may have a stacked-layer structure of a thin first conductor provided along the side surface and the bottom surface of the opening and a second conductor over the first conductor.

In the case where the conductor240has a stacked-layer structure, a conductive material having a function of inhibiting passage of impurities such as water and hydrogen is preferably used as the first conductor placed in the vicinity of the insulator285and the insulator280. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. The conductive material having a function of inhibiting passage of impurities such as water and hydrogen may be used as a single layer or stacked layers. Moreover, impurities such as water and hydrogen contained in a layer above the insulator283can be inhibited from entering the oxide230through the conductor240. As the second conductor, the above-described conductive material containing tungsten, copper, or aluminum as its main component is used, for example.

Although the conductor240illustrated inFIG.14Bis a stack of the first conductor and the second conductor, the present invention is not limited thereto. For example, the conductor240may be provided to have a single-layer structure or a stacked-layer structure of three or more layers.

The conductor246may be placed in contact with the top surface of the conductor240. The conductor246is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. The conductor246may have a stacked-layer structure; for example, stacked layers of titanium or titanium nitride and the above-described conductive material may be employed. As illustrated inFIG.14B, the top surface of the insulator285is higher in a region where the insulator285overlaps with the conductor246than in a region where the insulator285does not overlap with the conductor246, in some cases. The conductor246may be formed to be embedded in an opening provided in an insulator.

An insulator241functioning as a barrier insulating film is preferably provided between the conductor240and the insulator280. The insulator245is preferably placed in contact with the side surface of the opening that is formed in the insulator271, the insulator275, the insulator280, the insulator282, the insulator283, and the insulator285. The insulator241preferably has a structure similar to that of the above-described insulator245.

In this variation example, an insulator286covering the conductor246and the insulator285is provided. The insulator286may be formed using an insulating material that can be used for the insulator285.

In this variation example, the capacitor100is formed after the conductor240and the conductor246are formed. Thus, unlike the semiconductor device illustrated inFIG.11AtoFIG.11D, part of the bottom surface of the insulator130and part of the side surface of the insulator245are in contact with the insulator286. That is, the depth of the opening in which the capacitor100is embedded is increased in accordance with the thickness of the insulator286. This can increase the capacitance of the capacitor100without increasing the area of the semiconductor device.

Variation Example 2 of Semiconductor Device

The semiconductor device illustrated inFIG.15AandFIG.15Bis a variation example of the semiconductor device illustrated inFIG.11AtoFIG.11D. The semiconductor device illustrated inFIG.15AandFIG.15Bincludes an insulator241a, a conductor240a, and a conductor246aover the conductor242ain a manner similar to that of a semiconductor device illustrated inFIG.16AandFIG.16B. Furthermore, an insulator241b, a conductor240b, and a conductor246bare included over the conductor120. Here, the conductor240bfunctions as a plug electrically connected to one of terminals of the capacitor100, and the conductor246bfunctions as a wiring connected to the plug.

Note that a conductive material similar to that for the above-described insulator241can be used for the insulator241aand the insulator241b. A conductive material similar to that for the above-described conductor240can be used for the conductor240aand the conductor240b. A conductive material similar to that for the above-described conductor246can be used for the conductor246aand the conductor246b.

Unlike the semiconductor device illustrated inFIG.16AandFIG.16B, the semiconductor device illustrated inFIG.15AandFIG.15Bhas a structure where the conductor240aand the conductor240bare formed after the capacitor100is formed. Thus, the bottom surfaces of the conductor246aand the conductor246bare in contact with the top surface of the insulator285that is formed to cover the conductor120.

Unlike the semiconductor device illustrated inFIG.11AtoFIG.11D, the semiconductor device illustrated inFIG.15AandFIG.15Bhas a structure where an interlayer insulating film is not provided between the insulator283and the insulator130and the bottom surface of the insulator130is in contact with the top surface of the insulator283.

Variation Example 3 of Semiconductor Device

The semiconductor device illustrated inFIG.16AandFIG.16Bis a variation example of the semiconductor device illustrated inFIG.15AandFIG.15B. The semiconductor device illustrated inFIG.16AandFIG.16Bis different from the semiconductor device illustrated inFIG.15AandFIG.15Bin that the insulator283is in contact with part of the top surface of the insulator212. Accordingly, the transistor200is placed in a region sealed with the insulator283and the insulator212. With the above structure, entry of hydrogen contained in a region outside the sealed region into the sealed region can be inhibited. AlthoughFIG.16AandFIG.16Billustrate the transistor200having a structure where the insulator212and the insulator283are each provided to have a single-layer structure, the present invention is not limited thereto. For example, the insulator212and the insulator283may each be provided to have a stacked-layer structure of two or more layers.

Application Example of Semiconductor Device

An example of the semiconductor device of one embodiment of the present invention will be described below with reference toFIG.17.

FIG.17Ais a top view of a semiconductor device500. InFIG.17A, the x-axis is parallel to the channel length direction of the transistor200, and the y-axis is perpendicular to the x-axis.FIG.17Bis a cross-sectional view corresponding to a portion indicated by the dashed-dotted line A1-A2inFIG.17A, and is also a cross-sectional view of the transistor200in the channel length direction.FIG.17Cis a cross-sectional view corresponding to a portion indicated by the dashed-dotted line A3-A4inFIG.17A, and is also a cross-sectional view of an opening region400and its vicinity. Note that for clarity of the drawing, some components are not illustrated in the top view ofFIG.17A.

Note that in the semiconductor device illustrated inFIG.17AtoFIG.17C, components having the same functions as the components included in the semiconductor device described in <Structure example of semiconductor device> are denoted by the same reference numerals. Note that the materials described in detail in <Structure example of semiconductor device> can also be used as component materials of the semiconductor devices in this section.

The semiconductor device500illustrated inFIG.17AtoFIG.17Cis a variation example of the semiconductor device illustrated inFIG.11AtoFIG.11D. The semiconductor device500illustrated inFIG.17AtoFIG.17Cis different from the semiconductor device illustrated inFIG.11AtoFIG.11Din that the opening region400is formed in the insulator282and the insulator280. Moreover, a sealing portion265is formed to surround a plurality of transistors200and a plurality of capacitors100, which is a different point from the semiconductor device illustrated inFIG.11AtoFIG.11D.

The semiconductor device500includes a plurality of transistors200, a plurality of capacitors100, and a plurality of opening regions400arranged in a matrix. In addition, a plurality of conductors260functioning as gate electrodes of the transistors200are provided to extend in the y-axis direction. The opening regions400are provided in regions not overlapping with the oxide230or the conductor260. The sealing portion265is formed so as to surround the plurality of transistors200, the plurality of capacitors100, the plurality of conductors260, and the plurality of opening regions400. Note that the number, the position, and the size of the transistors200, the capacitors100, the conductors260, and the opening regions400are not limited to those illustrated inFIG.17and may be set as appropriate in accordance with the design of the semiconductor device500.

As illustrated inFIG.17BandFIG.17C, the sealing portion265is provided to surround the plurality of transistors200, the insulator216, the insulator222, the insulator275, the insulator280, and the insulator282. In other words, the insulator283is provided to cover the insulator216, the insulator222, the insulator275, the insulator280, and the insulator282. In the sealing portion265, the insulator283is in contact with the top surface of the insulator214. In the sealing portion265, the insulator274is provided between the insulator283and the insulator285. The top surface of the insulator274is substantially level with the uppermost surface of the insulator283. As the insulator274, an insulator similar to the insulator280can be used.

Such a structure enables the plurality of transistors200to be surrounded (sealed) by the insulator283, the insulator214, and the insulator212. One or more of the insulator283, the insulator214, and the insulator212preferably function as a barrier insulating film against hydrogen. Accordingly, entry of hydrogen contained in the region outside the sealing portion265into a region in the sealing portion265can be inhibited. The insulator283, the insulator214, and the insulator212having such a function are referred to as sealing films in some cases.

As illustrated inFIG.17C, the insulator282has an opening portion in the opening region400. In the opening region400, the insulator280may have a groove to overlap with the opening portion in the insulator282. The depth of the groove portion of the insulator280is less than or equal to the depth at which the top surface of the insulator275is exposed and is, for example, approximately greater than or equal to ¼ and less than or equal to ½ of the maximum thickness of the insulator280.

As illustrated inFIG.17C, the insulator283is in contact with the side surface of the insulator282, the side surface of the insulator280, and the top surface of the insulator280inside the opening region400. Part of the insulator274is formed in the opening region400to fill the depressed portion formed in the insulator283, in some cases. At this time, the top surface of the insulator274formed in the opening region400is substantially level with the uppermost surface of the insulator283, in some cases.

When heat treatment is performed in such a state that the opening region400is formed and the insulator280is exposed in the opening portion of the insulator282, part of oxygen contained in the insulator280can be made to diffuse outwardly from the opening region400while oxygen is supplied to the oxide230. This enables oxygen to be sufficiently supplied to the region functioning as the channel formation region and its vicinity in the oxide semiconductor from the insulator280containing oxygen to be released by heating, and also prevents an excess amount of oxygen from being supplied thereto.

At this time, hydrogen contained in the insulator280can be bonded to oxygen and released to the outside through the opening region400. The hydrogen bonded to oxygen is released as water. Thus, the amount of hydrogen contained in the insulator280can be reduced, and hydrogen contained in the insulator280can be prevented from entering the oxide230.

InFIG.17A, the shape of the opening region400in the top view is substantially rectangular; however, the present invention is not limited to this. For example, the shape of the opening region400in the top view can be a rectangular shape, an elliptical shape, a circular shape, a rhombus shape, or a shape obtained by combining any of the above shapes. The area and arrangement interval of the opening regions400can be set as appropriate in accordance with the design of the semiconductor device including the transistor200. For example, in the region where the density of the transistors200is low, the area of the opening region400may be increased or the arrangement interval of the opening regions400may be narrowed. For example, in the region where the density of the transistors200is high, the area of the opening region400may be decreased, or the arrangement interval of the opening regions400may be increased.

According to one embodiment of the present invention, a novel transistor can be provided. According to another embodiment of the present invention, a semiconductor device with a small variation in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a highly reliable semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device with a high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with a high field-effect mobility can be provided. According to another embodiment of the present invention, a semiconductor device with favorable frequency characteristics can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

According to another embodiment of the present invention, a capacitor containing a material that can have ferroelectricity can be provided. According to another embodiment of the present invention, the above-described capacitor can be provided with favorable productivity. According to another embodiment of the present invention, a semiconductor device including the above-described capacitor and a transistor can be provided. According to another embodiment of the present invention, the above-described semiconductor device that can be miniaturized or highly integrated can be provided.

At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with any of those in the other embodiments, the other examples, and the like described in this specification.

In this embodiment, one mode of a semiconductor device will be described with reference toFIG.18.

Structure Example of Storage Device

FIG.18illustrates an example of a semiconductor device (storage device) of one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor200is provided above a transistor300, and the capacitor100is provided above the transistor300and the transistor200. Note that the transistor200described in the above embodiment can be used as the transistor200. The capacitor100described in the above embodiment can be used as the capacitor100. AlthoughFIG.18illustrates an example where the capacitor100and the transistor200illustrated inFIG.14are used, the present invention is not limited thereto; the capacitor100and the transistor200can be selected as appropriate.

A material that can have ferroelectricity, in which polarization internally occurs due to an electric field supplied from the outside and the polarization remains even when the electric field is reduced to zero, is used in the capacitor100. Thus, a nonvolatile storage element can be formed using the capacitor100. In other words, a one-transistor one-capacitor ferroelectric memory can be formed using the capacitor functioning as a ferroelectric capacitor and the transistor200.

The transistor200is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor200has a feature of a high withstand voltage. Accordingly, a high voltage can be applied to the transistor200formed using an oxide semiconductor even when the transistor200is miniaturized. The miniaturization of the transistor200can reduce the area occupied by the semiconductor device.

In the semiconductor device illustrated inFIG.18, a wiring1001is electrically connected to a source of the transistor300, and a wiring1002is electrically connected to a drain of the transistor300. A wiring1003is electrically connected to one of the source and the drain of the transistor200, a wiring1004is electrically connected to a first gate of the transistor200, a wiring1005is electrically connected to one electrode of the capacitor100, a wiring1006is electrically connected to a second gate of the transistor200, and a wiring1007is electrically connected to a gate of the transistor300.

The storage device illustrated inFIG.18can form a memory cell array when arranged in a matrix.

The transistor300is provided on a substrate311and includes a conductor316functioning as a gate, an insulator315functioning as a gate insulator, a semiconductor region313formed of part of the substrate311, and a low-resistance region314aand a low-resistance region314bfunctioning as a source region and a drain region. The transistor300may be a p-channel transistor or an n-channel transistor.

Here, in the transistor300illustrated inFIG.18, the semiconductor region313(part of the substrate311) in which a channel is formed has a protruding shape. In addition, the conductor316is provided to cover the side surface and the top surface of the semiconductor region313with the insulator315therebetween. Note that a material adjusting the work function may be used for the conductor316. Such a transistor300is also referred to as a FIN-type transistor because it utilizes a protruding portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the protruding portion may be included in contact with an upper portion of the protruding portion. Furthermore, although the case where the protruding portion is formed by processing part of the semiconductor substrate is described here, a semiconductor film having a protruding shape may be formed by processing an SOI substrate.

Note that the transistor300illustrated inFIG.18is an example and the structure is not limited thereto; an appropriate transistor is used in accordance with a circuit structure or a driving method.

Wiring layers provided with an interlayer film, a wiring, a plug, and the like may be provided between the components. A plurality of wiring layers can be provided in accordance with design. Here, a plurality of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, part of a conductor functions as a wiring in some cases and part of a conductor functions as a plug in other cases.

For example, an insulator320, an insulator322, an insulator324, and an insulator326are sequentially stacked over the transistor300as interlayer films. A conductor328, a conductor330, and the like that are electrically connected to the capacitor100or the transistor200are embedded in the insulator320, the insulator322, the insulator324, and the insulator326. Note that the conductor328and the conductor330each function as a plug or a wiring.

The insulators functioning as interlayer films may also function as planarization films that cover uneven shapes therebelow. For example, the top surface of the insulator322may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve planarity.

A wiring layer may be provided over the insulator326and the conductor330. For example, an insulator350, an insulator352, and an insulator354are sequentially stacked inFIG.18. Furthermore, a conductor356is formed in the insulator350, the insulator352, and the insulator354. The conductor356functions as a plug or a wiring.

Similarly, a conductor218, a conductor included in the transistor200(the conductor205), and the like are embedded in an insulator210, the insulator212, the insulator214, and the insulator216. Note that the conductor218has a function of a plug or a wiring that is electrically connected to the capacitor100or the transistor300.

Here, like the insulator241described in the above embodiment, an insulator217is provided in contact with the side surface of the conductor218functioning as a plug. The insulator217is provided in contact with an inner wall of an opening formed in the insulator210, the insulator212, the insulator214, and the insulator216. That is, the insulator217is provided between the conductor218and each of the insulator210, the insulator212, the insulator214, and the insulator216. Note that the conductor205and the conductor218can be formed in parallel; thus, the insulator217is sometimes formed in contact with the side surface of the conductor205.

As the insulator217, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used, for example. Since the insulator217is provided in contact with the insulator210, the insulator212, the insulator214, and the insulator222, entry of impurities such as water and hydrogen into the oxide230through the conductor218from the insulator210, the insulator216, or the like can be inhibited. In particular, silicon nitride is suitable because of its high blocking property against hydrogen. Moreover, oxygen contained in the insulator210or the insulator216can be prevented from being absorbed by the conductor218.

The insulator217can be formed in a manner similar to that of the insulator241. For example, silicon nitride can be deposited by a PEALD method and an opening reaching the conductor356can be formed by anisotropic etching.

Above the transistor200, a conductor112is provided over the insulator285and the conductor240. Note that the conductor112functions as a plug or a wiring that is electrically connected to the transistor200or the transistor300. The insulator286is provided to cover the insulator285and the conductor112. An insulator150is provided to cover the insulator286and the capacitor100.

In addition, a barrier insulating film against hydrogen may be provided to cover the insulator285and the conductor112. As illustrated inFIG.18, as barrier insulating films against hydrogen, an insulator152acovering the insulator285and the conductor112and an insulator152bover the insulator152aare preferably provided. As the insulator152aand the insulator152b, a barrier insulating film that can be used for the above-described insulator283or the like may be used. With the insulator152aand the insulator152bprovided in the above manner, impurities such as hydrogen which are contained in the insulator286and the like can be inhibited from diffusing into the transistor200through the conductor112and the conductor240.

The insulator152ais deposited by a sputtering method. For example, silicon nitride deposited by a sputtering method can be used as the insulator152a. Since a sputtering method does not need to use a molecule containing hydrogen as a deposition gas, the hydrogen concentration in the insulator152acan be reduced. Since the hydrogen concentration in the insulator152ain contact with the conductor112and the insulator285is reduced in this manner, hydrogen can be inhibited from diffusing from the insulator152ainto the conductor112and the insulator285.

The insulator152bis preferably deposited by an ALD method, particularly a PEALD method. For example, silicon nitride deposited by a PEALD method can be used as the insulator152b. Thus, the insulator152bcan be deposited with good coverage; therefore, even when a pinhole, disconnection, or the like is generated in the insulator152aowing to unevenness of the base, the insulator152bcovers it, whereby hydrogen can be inhibited from diffusing into the conductor112and the insulator285.

Note that the methods for depositing the insulator152aand the insulator152bare not limited only to a sputtering method and an ALD method; a CVD method, an MBE method, a PLD method, or the like can also be used as appropriate. Although the two-layer structure of the insulator152aand the insulator152bis described above, the present invention is not limited thereto; a single-layer structure or a stacked-layer structure of three or more layers may be used.

The insulator283and the insulator212may be a barrier insulating film with a stacked-layer structure, as in the case of the insulator152aand the insulator152b.

Furthermore, similarly, a barrier insulating film against hydrogen may be provided to cover the insulator286and the capacitor100. As illustrated inFIG.18, an insulator154acovering the insulator286and the capacitor100and an insulator154bover the insulator154aare preferably provided as barrier insulating films against hydrogen. Here, the capacitor100is sealed with the insulator154aand the insulator154b, and the insulator154aand the insulator154bfunction as sealing films. A barrier insulating film similar to the insulator152aand a barrier insulating film similar to the insulator152bcan be used as the insulator154aand the insulator154b, respectively. Providing the insulator154aand the insulator154bin this manner can inhibit impurities such as hydrogen contained in the insulator150and the like from diffusing into the transistor200through the capacitor100.

Examples of an insulator that can be used as an interlayer film include insulating oxide, insulating nitride, insulating oxynitride, insulating nitride oxide, insulating metal oxide, insulating metal oxynitride, and insulating metal nitride oxide.

For example, when a material having a low dielectric constant is used for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Thus, a material is preferably selected depending on the function of an insulator.

For example, as the insulator150, the insulator210, the insulator352, the insulator354, and the like, an insulator having a low dielectric constant is preferably included. For example, the insulator preferably includes silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like. Alternatively, the insulator preferably has a stacked-layer structure of a resin and silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide. When silicon oxide or silicon oxynitride, which is thermally stable, is combined with a resin, the stacked-layer structure can have thermal stability and a low dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon and aramid), polyimide, polycarbonate, and acrylic.

When a transistor using an oxide semiconductor is surrounded by an insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stable. Thus, the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen can be used as the insulator214, the insulator212, the insulator350, and the like.

As the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a single layer or stacked layers of an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used. Specifically, as the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; silicon nitride oxide; silicon nitride; or the like can be used.

As the conductor that can be used for a wiring or a plug, a material containing one or more kinds of metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

For example, for the conductor328, the conductor330, the conductor356, the conductor218, the conductor112, and the like, a single layer or stacked layers of conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material that is formed using the above materials can be used. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is preferable to use tungsten. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance. Furthermore, as described in the above embodiment, the conductor120ain the capacitor100is deposited by a method with substrate heating, such as a thermal ALD method, whereby the ferroelectricity of the insulator130can be enhanced even without performing high-temperature baking after the formation. Therefore, since the semiconductor device can be fabricated without performing high-temperature baking, it is possible to use a low-resistance conductive material with a low melting point, such as copper.

<Wiring or Plug in Layer Provided with Oxide Semiconductor>

In the case where an oxide semiconductor is used in the transistor200, an insulator including an excess-oxygen region is provided in the vicinity of the oxide semiconductor in some cases. In that case, an insulator having a barrier property is preferably provided between the insulator including the excess-oxygen region and a conductor provided in the insulator including the excess-oxygen region.

For example, inFIG.18, the insulator241is preferably provided between the conductor240and the insulator224and the insulator280that contain excess oxygen. Since the insulator241is provided in contact with the insulator222, the insulator282, and the insulator283, the insulator224and the transistor200can be sealed with the insulators having a barrier property.

That is, providing the insulator241can inhibit excess oxygen contained in the insulator224and the insulator280from being absorbed by the conductor240. In addition, providing the insulator241can inhibit diffusion of hydrogen, which is an impurity, into the transistor200through the conductor240.

For the insulator241, an insulating material having a function of inhibiting diffusion of oxygen and impurities such as water and hydrogen is preferably used. For example, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like is preferably used. In particular, silicon nitride is preferable because of its high blocking property against hydrogen. Alternatively, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can be used, for example.

As described in the above embodiment, the transistor200may be sealed with the insulator212, the insulator214, the insulator282, and the insulator283. Such a structure can inhibit entry of hydrogen contained in the insulator274, the insulator285, the insulator150, and the like into the insulator280and the like. In this case, the insulator212, the insulator214, the insulator282, and the insulator283function as sealing films.

Here, the conductor240penetrates the insulator283and the insulator282, and the conductor218penetrates the insulator214and the insulator212; however, as described above, the insulator241is provided in contact with the conductor240, and the insulator217is provided in contact with the conductor218. This can reduce the amount of hydrogen entering the inside of the insulator212, the insulator214, the insulator282, and the insulator283through the conductor240and the conductor218. In this manner, the transistor200is sealed with the insulator212, the insulator214, the insulator282, the insulator283, the insulator241, and the insulator217, so that impurities such as hydrogen contained in the insulator274or the like can be inhibited from entering from the outside. Note that although one transistor200is illustrated in the region sealed with the insulator212, the insulator283, and the like inFIG.18, the structure is not limited thereto; a plurality of transistors200can be provided in the sealed region.

A dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) which is provided when a large-sized substrate is divided into semiconductor elements so that a plurality of semiconductor devices are each taken as a chip is described below. Examples of a dividing method include the case where a groove (a dicing line) for dividing the semiconductor elements is formed on the substrate, and then the substrate is cut along the dicing line to divide (split) it into a plurality of semiconductor devices.

Here, for example, as illustrated inFIG.18, a region in which the insulator283and the insulator214are in contact with each other is preferably designed to overlap with the dicing line. That is, an opening is provided in the insulator282, the insulator280, the insulator275, the insulator222, and the insulator216in the vicinity of a region to be the dicing line that is provided on an outer edge of a memory cell including the plurality of transistors200.

That is, in the opening provided in the insulator282, the insulator280, the insulator275, the insulator222, and the insulator216, the insulator214is in contact with the insulator283.

For example, an opening may be provided in the insulator282, the insulator280, the insulator275, the insulator222, the insulator216, and the insulator214. With such a structure, in the opening provided in the insulator282, the insulator280, the insulator275, the insulator222, the insulator216, and the insulator214, the insulator212is in contact with the insulator283. Here, the insulator212and the insulator283may be formed using the same material and the same method. When the insulator212and the insulator283are formed using the same material and the same method, the adhesion therebetween can be increased. For example, silicon nitride is preferably used.

With the structure, the transistors200can be surrounded by the insulator212, the insulator214, the insulator282, and the insulator283. Since at least one of the insulator212, the insulator214, the insulator282, and the insulator283has a function of inhibiting diffusion of oxygen, hydrogen, and water, even when the substrate is divided into circuit regions each of which is provided with the semiconductor elements described in this embodiment to be processed into a plurality of chips, entry and diffusion of impurities such as hydrogen and water from the direction of the side surface of the divided substrate into the transistor200can be prevented.

With the structure, excess oxygen in the insulator280and the insulator224can be prevented from diffusing to the outside. Accordingly, excess oxygen in the insulator280and the insulator224is efficiently supplied to the oxide where the channel is formed in the transistor200. The oxygen can reduce oxygen vacancies in the oxide where the channel is formed in the transistor200. Thus, the oxide where the channel is formed in the transistor200can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, the transistor200can have a small variation in the electrical characteristics and higher reliability.

Variation Example 1 of Storage Device

Although the capacitor100is formed to be embedded in the insulator285, the insulator280, and the like in the storage device illustrated inFIG.18, the present invention is not limited thereto. As illustrated inFIG.19, a planar capacitor100may be provided over the insulator285.

The capacitor100includes the conductor110, the insulator130covering the conductor110, and the conductor120(the conductor120aand the conductor120b) covering the insulator130. Here, the insulator130preferably covers the top surface and the side surface of the conductor110to separate the conductor110and the conductor120. The descriptions of [Structure example of storage device] and the above embodiments can be referred to for the details of the conductor110, the insulator130, and the conductor120.

The conductor110is formed in the same layer as the conductor112and is in contact with the top surface of the conductor240. The conductor110is electrically connected to one of the source and the drain of the transistor200through the conductor240.

An insulator155is preferably provided to cover the conductor120, the insulator130, and the conductor112. As the insulator155, an insulator that can be used as the insulator214, the insulator282, or the like and has a function of capturing and fixing hydrogen is preferably used. For example, aluminum oxide (AlOx(x is a given number greater than 0)) is preferably used. The AlOxpreferably has an amorphous structure. In such a metal oxide having an amorphous structure, an oxygen atom has a dangling bond and sometimes has a property of capturing or fixing hydrogen with the dangling bond.

For example, aluminum oxide deposited by an ALD method or an aluminum oxide film deposited by a sputtering method can be used for the insulator155. Alternatively, the insulator155may be a stacked-layer film of aluminum oxide deposited by an ALD method and aluminum oxide thereover deposited by a sputtering method.

Providing the insulator155covering the capacitor100in this manner makes it possible to capture and fix hydrogen contained in the insulator130of the capacitor100to reduce the hydrogen concentration in the insulator130. This can improve the crystallinity of the insulator130and enhance the ferroelectricity of the insulator130. Moreover, a leakage current between the conductor110and the conductor120can be reduced. Note that the structure is not limited thereto, and a structure where the insulator155is not provided may be employed.

As in the storage device illustrated inFIG.18, the insulator152aand the insulator152bthat function as barrier insulating films against hydrogen are preferably provided over the conductor112and the conductor120. The insulator152aand the insulator152bare provided over the insulator155. Providing the insulator152aand the insulator152bin this manner can inhibit impurities such as hydrogen contained in the insulator286over the insulator152bfrom diffusing into the transistor200through the capacitor100, the conductor112, and the conductor240.

As illustrated inFIG.19, an insulator287functioning as a barrier insulating film against hydrogen is preferably provided over the insulator285. The conductor112, the conductor110, and the insulator155are provided over and in contact with the insulator287. Here, as the insulator287, a barrier insulating film similar to the insulator283can be used.

With such a structure, the insulator155and the insulator287are in contact with each other in a region not overlapping with the capacitor100. That is, the capacitor100is sealed with the insulator155, the insulator152a, the insulator152b, and the insulator287. The insulator155, the insulator152a, the insulator152b, and the insulator287function as sealing films. Thus, hydrogen diffusion from the outside of the insulator152band the insulator287into the capacitor100can be inhibited, and furthermore, hydrogen in the insulator152band the insulator287can be captured and fixed, so that the hydrogen concentration in the insulator130of the capacitor100can be reduced. Therefore, the ferroelectricity of the insulator130can be enhanced.

Note that in the case where the insulator155is not used, the insulator287and the insulator152aare in contact with each other in a region not overlapping with the capacitor100, and the capacitor100is sealed with the insulator152a, the insulator152b, and the insulator287.

Furthermore, as illustrated inFIG.19, the transistor200is also sealed with the insulator283, the insulator214, and the insulator212that function as barrier insulating films against hydrogen. Accordingly, diffusion of hydrogen into the transistor200from the outside of the insulator283and the insulator212can be inhibited to reduce the hydrogen concentration in the oxide semiconductor film included in the transistor200. Therefore, the electrical characteristics and reliability of the transistor200can be improved.

Although the storage device illustrated inFIG.19has a structure where the transistor200and the capacitor100are electrically connected to each other, the present invention is not limited thereto. As illustrated inFIG.20A, a structure may be employed in which the transistor200and the capacitor100are not electrically connected to each other. Here, in the storage device illustrated inFIG.20A, the transistor200and the capacitor100that are above the insulator212have structures similar to those in the storage device illustrated inFIG.19. The structure below the insulator212may be similar to that in the storage device illustrated inFIG.19, or may be a structure where the substrate311is provided below and in contact with the insulator212.

Furthermore, as illustrated inFIG.20A, an opening may be formed in the insulator286, the insulator152b, the insulator152a, and the insulator155, and a conductor288and an insulator289may be provided to fill the opening. The conductor288has a structure similar to that of the conductor240, and the insulator289has a structure similar to that of the insulator241. Here, one of the source and the drain of the transistor200is electrically connected to the wiring1003through the conductor288, and the other of the source and the drain of the transistor200is electrically connected to a wiring1008through the conductor288. One electrode (the conductor120) of the capacitor100is electrically connected to the wiring1005through the conductor288. The other electrode (the conductor110) of the capacitor100is electrically connected to a wiring1009through the conductor240, the conductor255in the same layer as the conductor205, the conductor112, and the conductor288.

As illustrated inFIG.20A, the transistor200and the capacitor100may be individually sealed with a sealing film. In the storage device illustrated inFIG.20A, the transistor200is sealed with the insulator283, the insulator214, and the insulator212. As illustrated inFIG.20A, the conductor240and the conductor255functioning as wirings or plugs connected to the capacitor100may be sealed separately from the transistor200. In this case, a region in which the insulator283and the insulator214are in contact with each other is formed between the transistor200and each of the conductor240and the conductor255.

AlthoughFIG.20Aillustrates a structure where the insulator285and the insulator287are provided between the transistor200and the capacitor100, the present invention is not limited thereto. For example, as illustrated inFIG.20B, a structure may be employed in which the insulator285and the insulator287are not provided and the bottom surfaces of the conductor112, the conductor110, and the insulator155are in contact with the insulator283. In this case, the capacitor100is sealed with the insulator152a, the insulator152b, the insulator155, and the insulator283. Thus, the insulator285and the insulator287does not need to be provided, so that the productivity of the storage device can be improved.

FIG.21Ais an enlarged view of the capacitor100illustrated inFIG.20A. As illustrated inFIG.21A, the capacitor100is sealed with the insulator287, the insulator152a, the insulator152b, and the insulator155, like the capacitor100illustrated inFIG.19. Here, the insulator155, the insulator152a, the insulator152b, and the insulator287function as sealing films. Thus, hydrogen diffusion from the outside of the insulator152band the insulator287into the capacitor100can be inhibited, and furthermore, hydrogen in the insulator152band the insulator287can be captured and fixed, so that the hydrogen concentration in the insulator130of the capacitor100can be reduced. Therefore, the ferroelectricity of the insulator130can be enhanced.

Although the capacitor100illustrated inFIG.21Ahas a structure where the insulator130is in contact with the top surface of the insulator287and the top surface and the side surface of the conductor110, the present invention is not limited thereto. As illustrated inFIG.21B, the insulator115amay be provided between the insulator130, and the insulator287and the conductor110. That is, the insulator130is in contact with the top surface of the insulator115a, and the insulator287and the conductor110are in contact with the bottom surface of the insulator115a. The insulator115aillustrated in FIG.1C2or the like in the above embodiment can be used as the insulator115ahere. The thickness of the insulator115ais greater than or equal to 0.2 nm and less than or equal to 2 nm, preferably greater than or equal to 0.5 nm and less than or equal to 1 nm. Such a structure allows the capacitor100illustrated inFIG.21Bto function as an FTJ illustrated in FIG.1C1and FIG.1C2, in which a capacitor and a diode are connected to each other.

Although the capacitor100illustrated inFIG.21Ahas a structure where the insulator130is in contact with the bottom surface of the conductor120, the present invention is not limited thereto. As illustrated inFIG.21C, the insulator115bmay be provided between the insulator130and the conductor120. That is, the insulator130is in contact with the bottom surface of the insulator115b, and the conductor120is in contact with the top surface of the insulator115b. The insulator115billustrated in FIG.1C3or the like in the above embodiment can be used as the insulator115bhere. The thickness of the insulator115bis greater than or equal to 0.2 nm and less than or equal to 2 nm, preferably greater than or equal to 0.5 nm and less than or equal to 1 nm. Such a structure allows the capacitor100illustrated inFIG.21Cto function as an FTJ illustrated in FIG.1C1and FIG.1C3, in which a capacitor and a diode are connected to each other.

As illustrated inFIG.22A, a polycrystalline region is sometimes formed in the insulator130of the capacitor100.FIG.22Aillustrates an example where a polycrystalline region131aand a polycrystalline region131bare formed in upper sides of side end portions of the conductor110. The insulator130illustrated inFIG.22Ais deposited along a step of a formation surface formed by the conductor110, and the polycrystalline region131aand the polycrystalline region131bare formed in the vicinity of upper portions of the step in some cases. The polycrystalline region131aand the polycrystalline region131bare regions where many grains or crystal grain boundaries illustrated inFIG.4Bare formed. For example, in the insulator130, the polycrystalline region131aand the polycrystalline region131binclude more grains than a region where the insulator130is in contact with the top surface of the conductor110with high planarity (the region can also be regarded as a region interposed between the polycrystalline region131aand the polycrystalline region131b). In other words, in the insulator130, the region interposed between the polycrystalline region131aand the polycrystalline region131binclude more single crystals illustrated inFIG.3than the polycrystalline region131aand the polycrystalline region131b.

Although the capacitor100illustrated inFIG.22Ahas a structure where the insulator155is provided to be in contact with the bottom surface of the insulator152a, the present invention is not limited thereto. For example, as illustrated inFIG.22B, a structure may be employed in which the insulator155is not provided and the bottom surface of the insulator152ais in contact with the top surface of the insulator287, the side surface of the insulator130, the side surface of the conductor120, and the top surface of the conductor120.

In addition, although the insulator130and the conductor120cover the side surface of the conductor110inFIG.22Aor the like, the present invention is not limited thereto. As illustrated inFIG.22C, the side surface of the insulator130and the side surface of the conductor120may be positioned on the inner side of the side surface of the conductor110. In this case, in the top view, the peripheries of the insulator130and the conductor120are positioned on the inner side of the periphery of the conductor110.

In the above structure, the insulator130and the conductor120are not formed in the vicinity of the step of the formation surface formed by the conductor110, so that the polycrystalline region131aand the polycrystalline region131billustrated inFIG.22Aare not formed in the insulator130illustrated inFIG.22C. Thus, the insulator130illustrated inFIG.22Cis entirely in contact with the top surface of the conductor110with high planarity, and includes many single crystals illustrated inFIG.3. The insulator130inFIG.22Caccordingly has a structure where a plurality of crystal layers are stacked in the c-axis direction as illustrated inFIG.4A, and sometimes can have large polarization. In the above manner, the insulator130illustrated inFIG.22Ccan have favorable ferroelectricity and the capacitor100can function as a ferroelectric device.

As illustrated inFIG.22C, the insulator155may be formed such that its side surface is positioned on the inner side of the side surface of the conductor110. In this case, the side surfaces of the insulator130, the conductor120, and the insulator155are preferably aligned with each other. In addition, the insulator152ais provided to cover the conductor110, the insulator130, the conductor120, and the insulator155. The insulator152bis provided over the insulator152a.

InFIG.22C, as inFIG.20A, the insulator286is provided over the insulator152b, and an opening reaching the conductor120is formed in the insulator155, the insulator152a, the insulator152b, and the insulator286. As inFIG.20A, the conductor288and the insulator289are placed in the opening.

Although not illustrated inFIG.20A, a conductor162is provided over and in contact with the conductor288, an insulator166is provided over the conductor162, an insulator168ais provided to cover the conductor162and the insulator166, and an insulator168bis provided over the insulator168ainFIG.22C. Although the capacitor100, the conductor288, the conductor162, and the like are illustrated in the same cross section inFIG.22C, the present invention is not limited thereto. In some cases, contact between the conductor162and the conductor120is formed in a place other than a place where the capacitor100and the conductor162overlap with each other.

The conductor162is a conductor functioning as a wiring, and may be electrically connected to the wiring1005like the conductor288illustrated inFIG.20A. For the conductor162, a conductive material that can be used for the conductor112is used.

An insulator similar to the insulator155can be used as the insulator166, an insulator similar to the insulator152acan be used as the insulator168a, and an insulator similar to the insulator152bcan be used as the insulator168b. With such a structure, the insulator286, the conductor288, and the conductor162can be interposed between the insulator168aand the insulator152bthat function as barrier insulating films against hydrogen. Furthermore, the insulator166having a function of capturing and fixing hydrogen is placed in the region interposed between the insulator168aand the insulator152b. Accordingly, hydrogen diffusion from the outside of the insulator168band the insulator152acan be inhibited, hydrogen in the insulator168band the insulator152acan be captured and fixed, and the hydrogen concentration in the insulator286, the conductor288, the conductor162, and the like can be reduced. By reducing the hydrogen concentration in the insulator286, the conductor288, the conductor162, and the like in this manner, hydrogen diffusion into the insulator130can be inhibited, and therefore the ferroelectricity of the insulator130can be enhanced.

Next, a method for fabricating the structure illustrated inFIG.22Cis described with reference toFIG.23AtoFIG.23B. Note that the description in the above embodiment, for example, can be referred to for the details of the device and the process.

First, the conductor110is deposited over the insulator287. The conductor110can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Titanium nitride can be used for the conductor110, for example. Here, CMP treatment or the like is preferably performed on the top surface of the conductor110to improve the planarity of the conductor110. For example, the top surface roughness of the conductor110represented by arithmetic mean roughness (Ra) or root mean square roughness (RMS) is less than or equal to 2 nm, preferably less than or equal to 1 nm, more preferably less than or equal to 0.8 nm, further preferably less than or equal to 0.5 nm, still further preferably less than or equal to 0.4 nm, yet still further preferably less than or equal to 0.2 nm. Improving the planarity of the top surface of the conductor110in this manner can improve the crystallinity of the insulator130formed in a later step.

Next, the conductor110is formed into a pattern by a photolithography method or the like (seeFIG.23A). Here, the conductor110is preferably formed into a pattern to cover the conductor288.

Then, the insulator130is deposited to cover the conductor110(seeFIG.23A). The insulator130can be deposited by a sputtering method, a CVD method, an ALD method, or the like. For example, the deposition is performed by a thermal ALD method. For example, HfZrOxcan be used for the insulator130. Here, a material not containing a hydrocarbon is suitably used as a precursor. With the use of such a precursor, hydrogen, carbon, a hydrocarbon, or the like in the insulator130can be reduced. For example, HfCl4and/or ZrCl4can be used as the precursor. In the case where the insulator130is deposited by a thermal ALD method, H2O, O3, or the like can be used as an oxidizer.

In the case where a precursor contains chlorine, chlorine contained in the insulator130is preferably reduced as much as possible. For example, chlorine contained in the insulator130can be reduced by setting the substrate temperature during the thermal ALD at higher than or equal to 400° C. In the case where deposition is performed according to the deposition sequence shown inFIG.7A, the introduction time of an oxidizer H2O is preferably long. This can sufficiently make chlorine bonded to a formation surface be detached therefrom, and thus can sufficiently reduce the concentration of chlorine contained in the insulator130.

As illustrated inFIG.23A, in the insulator130, the polycrystalline region131aand the polycrystalline region131bare formed in the upper sides of the side end portions of the conductor110in some cases.

Next, the conductor120ais deposited over the insulator130(seeFIG.23A). The conductor120acan be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Titanium nitride deposited by an ALD method or a sputtering method can be used as the conductor110, for example.

Next, the conductor120bis deposited over the conductor120a(seeFIG.23A). The conductor120bcan be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Tungsten deposited by a metal CVD method can be used for the conductor110, for example. Note that the conductor120bis not necessarily deposited, and the conductor120may have a single-layer structure of only the conductor120a, for example.

Furthermore, heat treatment is preferably performed after formation of the conductor120. For example, the substrate temperature during the heat treatment is set to be higher than or equal to 300° C., preferably higher than or equal to 325° C., further preferably higher than or equal to 350° C. Furthermore, the substrate temperature during the deposition is set to be lower than or equal to 600° C., preferably lower than or equal to 500° C., further preferably lower than or equal to 450° C., for example. For example, the substrate temperature is set at approximately 500° C. In addition, the heat treatment time is approximately longer than or equal to 30 seconds and shorter than or equal to 120 seconds, for example. The heat treatment can be performed in an atmosphere containing at least one of an oxygen gas, a nitrogen gas, and an inert gas.

Such heat treatment promotes crystallization of the insulator130and can improve the crystallinity. In other words, a single crystal region in the insulator130can be made large. In the case where a deposition method with substrate heating, such as a thermal ALD method, is used for the deposition of the conductor120, the insulator130can be sufficiently crystallized even without the above heat treatment in some cases.

Then, the insulator155is deposited over the conductor120b(seeFIG.23B). The insulator155can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator155, an insulator that can be used as the insulator214, the insulator282, or the like and has a function of capturing and fixing hydrogen is preferably used. For example, aluminum oxide deposited by an ALD method or a sputtering method can be used as the insulator155. The thickness of the insulator155is approximately greater than or equal to 20 nm and less than or equal to 40 nm, for example.

Providing the insulator155over the conductor120in this manner makes it possible to capture and fix hydrogen contained in the insulator130of the capacitor100to reduce the hydrogen concentration in the insulator130. Accordingly, the crystallinity of the insulator130can be improved and the ferroelectricity of the insulator130can be enhanced.

Next, the insulator130, the conductor120a, the conductor120b, and the insulator155are formed into a pattern by a photolithography method or the like (seeFIG.23C). Thus, the side surfaces of the insulator130, the conductor120a, the conductor120b, and the insulator155are positioned on the inner side of the side surface of the conductor110. Accordingly, the polycrystalline region131aand the polycrystalline region131bformed in the insulator130can be removed, so that the insulator130containing many single crystals and having high crystallinity can be formed.

Next, the insulator152ais deposited to cover the insulator287, the conductor110, the insulator130, the conductor120, and the insulator155, and the insulator152bis deposited over the insulator152a(seeFIG.23D). As the insulator152aand the insulator152b, a barrier insulating film that can be used for the above-described insulator283or the like is used. Providing the insulator152aand the insulator152bin this manner can inhibit impurities such as hydrogen contained in the insulator286and the like from diffusing into the insulator130of the capacitor100. Here, the thickness of the insulator152acan be approximately greater than or equal to 10 nm and less than or equal to 40 nm, for example. The thickness of the insulator152bcan be approximately greater than or equal to 3 nm and less than or equal to 10 nm, for example.

The insulator152ais deposited by a sputtering method. For example, silicon nitride deposited by a sputtering method can be used as the insulator152a. A deposition gas in a sputtering method need not include molecules containing hydrogen, and therefore the hydrogen concentration in the insulator152acan be reduced. Since the hydrogen concentration in the insulator152ain contact with the conductor112and the insulator285is reduced in this manner, hydrogen can be inhibited from diffusing from the insulator152ainto the conductor112and the insulator285.

The insulator152bis preferably deposited by an ALD method, particularly a PEALD method. For example, silicon nitride deposited by a PEALD method can be used as the insulator152b. Thus, the insulator152bcan be deposited with good coverage; therefore, even when a pinhole, disconnection, or the like is generated in the insulator152aowing to unevenness of the base, the insulator152bcovers it, whereby hydrogen can be inhibited from diffusing into the conductor112and the insulator285.

By forming the insulator152aand the insulator152bin this manner, the capacitor100can be sealed with the insulator155, the insulator152a, the insulator152b, and the insulator287.

Then, the insulator286is deposited over the insulator152b(seeFIG.23D). An opening reaching the conductor120is formed in the insulator286, the insulator152b, the insulator152a, and the insulator155, and the conductor288and the insulator289are formed in the opening (seeFIG.22C).

Next, the conductor162is formed over the conductor288in a manner similar to that of the conductor110, and the insulator166is formed over the conductor162in a manner similar to that of the insulator155(seeFIG.22C). The insulator168ais deposited to cover the insulator286, the conductor162, and the insulator166in a manner similar to that of the insulator152a, and the insulator168bis deposited over the insulator168ain a manner similar to that of the insulator152b(seeFIG.22C).

Heat treatment is preferably performed after the deposition of the insulator168b. For example, the substrate temperature during the heat treatment is set to be higher than or equal to 300° C., preferably higher than or equal to 325° C., further preferably higher than or equal to 350° C. Furthermore, the substrate temperature during the deposition is set to be lower than or equal to 600° C., preferably lower than or equal to 500° C., further preferably lower than or equal to 450° C., for example. For example, the substrate temperature is set at approximately 400° C. The heat treatment time is approximately longer than or equal to 1 hour and shorter than or equal to 10 hours, for example. The heat treatment can be performed in an atmosphere containing at least one of an oxygen gas, a nitrogen gas, and an inert gas. Note that the heat treatment is not necessarily performed after deposition of the insulator168b, and can be performed as appropriate after deposition of the insulator152b.

By such heat treatment, hydrogen diffusion from the outside of the insulator152band the insulator287into the capacitor100can be inhibited, and furthermore, hydrogen in the insulator152band the insulator287can be captured and fixed, so that the hydrogen concentration in the insulator130of the capacitor100can be reduced. Therefore, the ferroelectricity of the insulator130can be enhanced.

In addition, the insulator166having a function of capturing and fixing hydrogen is placed in a region interposed between the insulator168aand the insulator152b. Thus, hydrogen diffusion from the outside of the insulator168band the insulator152aduring the heat treatment can be inhibited, and furthermore, hydrogen in the insulator168band the insulator152acan be captured and fixed, so that the hydrogen concentrations in the insulator286, the conductor288, the conductor162, and the like can be reduced.

Although the storage device illustrated inFIG.20Ahaving a structure where the transistor200and the capacitor100are not electrically connected to each other is described above, the present invention is not limited thereto. In the structure illustrated inFIG.20A, one or more of the wiring1003, the wiring1004, the wiring1006, and the wiring1008that are electrically connected to the transistor200may be electrically connected to one or both of the wiring1005and the wiring1009that are electrically connected to the capacitor100. In addition, part or whole of the description of the storage devices illustrated inFIG.20AtoFIG.22Cmay be employed for devices illustrated inFIG.18,FIG.19,FIG.24toFIG.27, and the like.

Variation Example 2 of Storage Device

Although the transistor200and the capacitor100are individually sealed with the barrier insulating films against hydrogen in the storage device illustrated inFIG.19, the present invention is not limited thereto. As illustrated inFIG.24, the transistor200and the capacitor100may be collectively sealed with the barrier insulating films against hydrogen (the insulator212, the insulator152a, and the insulator152b).

In the storage device illustrated inFIG.24, an opening reaching the insulator212is formed in the insulator214, the insulator216, the insulator222, the insulator275, the insulator280, the insulator282, the insulator283, the insulator285, and the insulator155. The insulator152aand the insulator152bover the insulator155are formed along the side surface and the bottom surface of the opening. The insulator152ais in contact with the top surface of the insulator212at the bottom surface of the opening.

With such a structure, the transistor200and the capacitor100can be collectively sealed with the insulator212, the insulator152a, and the insulator152b. Thus, diffusion of hydrogen into the capacitor100and the transistor200from the outside of the insulator212and the insulator152bcan be inhibited to reduce the hydrogen concentrations in the insulator130of the capacitor100and the oxide semiconductor film of the transistor200. Therefore, the ferroelectricity of the insulator130can be enhanced and the electrical characteristics and reliability of the transistor200can be improved.

Variation Example 3 of Storage Device

Although the capacitor100is provided over the transistor200in the storage device illustrated inFIG.24, the present invention is not limited thereto. As illustrated inFIG.25, the capacitor100may be provided in the same layer as the transistor200.

As illustrated inFIG.25, the conductor110functioning as the lower electrode of the capacitor100is preferably formed using a conductor in the same layer as the conductor205functioning as the back gate of the transistor200. The insulator130is placed over the conductor110, and the conductor120(the conductor120aand the conductor120b) is placed over the insulator130. Here, the insulator130preferably covers the top surface of the conductor110and separates the conductor110and the conductor120. Note that the structures of the insulator130and the conductor120can be made similar to those illustrated inFIG.19and the like, and the description of [Structure example of storage device] and the above embodiments can be referred to for the details. The insulator222is placed to cover the insulator130and the conductor120.

The conductor240is provided in contact with the top surface of the conductor120a, and the conductor112is provided in contact with the top surface of the conductor240. The conductor112is in contact with the conductor240electrically connected to one of the source and the drain of the transistor200. In other words, the conductor120functioning as the upper electrode of the capacitor100illustrated inFIG.25is electrically connected to the one of the source and the drain of the transistor200. Furthermore, the conductor110functioning as the lower electrode of the capacitor100is electrically connected to the wiring1005.

As in the storage device illustrated inFIG.24, the transistor200and the capacitor100can be collectively sealed with the insulator212, the insulator152a, and the insulator152b. Thus, diffusion of hydrogen into the capacitor100and the transistor200from the outside of the insulator212and the insulator152bcan be inhibited to reduce the hydrogen concentrations in the insulator130of the capacitor100and the oxide semiconductor film of the transistor200. Therefore, the ferroelectricity of the insulator130can be enhanced and the electrical characteristics and reliability of the transistor200can be improved.

Variation Example 4 of Storage Device

Although the transistor200is provided over the transistor300and the capacitor100is connected to the transistor200in the storage device illustrated inFIG.19or the like, the present invention is not limited thereto. As illustrated inFIG.26A, the capacitor100may be connected to the transistor300without provision of the transistor200.

As illustrated inFIG.26A, an opening reaching the low-resistance region314aof the transistor300is formed in the insulator320, the insulator322, and the insulator287, and a conductor357is formed to be embedded in the opening. As the conductor357, a conductor similar to the conductor328and the like can be used. The top surface of the conductor357is in contact with the bottom surface of the conductor110of the capacitor100. In this manner, the conductor110functioning as the lower electrode of the capacitor100and the low-resistance region314afunctioning as one of the source and the drain of the transistor300are connected to each other through the conductor357. Note that the structures of the transistor300, the capacitor100, and the layers including them are similar to those in the structure illustrated inFIG.19, and therefore the description of the structure illustrated inFIG.19can be referred to.

Furthermore, in the storage device illustrated inFIG.26A, the capacitor100can be sealed with the insulator287, the insulator152a, and the insulator152bas in the storage device illustrated inFIG.19. Accordingly, diffusion of hydrogen into the capacitor100from the outside of the insulator287and the insulator152bcan be inhibited to reduce the hydrogen concentration in the oxide semiconductor film of the insulator130of the capacitor100. Therefore, the ferroelectricity of the insulator130can be enhanced.

Although the low-resistance region314aof the transistor300and the conductor110of the capacitor100are directly connected to each other with the conductor357in the structure illustrated inFIG.26A, the present invention is not limited thereto. The plurality of wiring layers illustrated inFIG.19and the like may be provided between the capacitor100and the transistor300. For example, as illustrated inFIG.26B, the conductor328may be formed over the transistor300, the conductor330may be formed over the conductor328, the conductor356may be formed over the conductor330, and the conductor357may be formed over the conductor356. The low-resistance region314aof the transistor300and the conductor110of the capacitor100are electrically connected to each other with the conductor328, the conductor330, the conductor356, and the conductor357. Note that the description of [Structure example of storage device] can be referred to for the conductor328, the conductor330, the conductor356, and the wiring layers including them.

Variation Example of Transistor

Although the transistor200is connected to the capacitor100containing the material that can have ferroelectricity in the structure illustratedFIG.19and the like, the present invention is not limited thereto. For example, a material that can have ferroelectricity may be used for the transistor200and an insulator provided in the vicinity thereof. The transistor with such a structure is described with reference toFIG.27AtoFIG.27C. Note that each of the transistors200illustrated inFIG.27AtoFIG.27Cis the one in which the conductor240a, the conductor240b, the conductor246a, the conductor246b, the insulator241a, and the insulator241bare provided in the transistor200illustrated inFIG.11instead of the capacitor100.

In the transistor200illustrated inFIG.27A, an insulator130ais used instead of the insulator222. A material similar to that for the insulator130, which can have ferroelectricity, can be used for the insulator130a. That is, a material that can have ferroelectricity is used for the second gate insulator of the transistor200illustrated inFIG.27A.

In the transistor200illustrated inFIG.27B, an insulator130bis used instead of the insulator252, the insulator250, and the insulator254. A material similar to that for the insulator130, which can have ferroelectricity, can be used for the insulator130b. That is, a material that can have ferroelectricity is used for the first gate insulator in the transistor200illustrated inFIG.27B. Such a structure allows the transistor200illustrated inFIG.27Bto function as an FeFET illustrated in FIG.1B1. Note that although the whole first gate insulator is formed using a ferroelectric material inFIG.27B, the present invention is not limited thereto. For example, a material that can have ferroelectricity may be used for one or more of the insulator252, the insulator250a, the insulator250b, and the insulator254, which are illustrated inFIG.12B.

In the transistor200illustrated inFIG.27C, an insulator130cis provided over the conductor260, and the conductor262is provided over the insulator130c. A material similar to that for the insulator130, which can have ferroelectricity, can be used for the insulator130c. The conductive material that can be used for the conductor260can be used for the conductor262. The insulator282is provided to cover the insulator130cand the conductor262. The semiconductor device illustrated inFIG.27Ccan also be regarded as the semiconductor device in which the gate electrode of the transistor200is provided with one terminal of the ferroelectric capacitor.

Although an example of the transistor200is described above, the present invention is not limited thereto. For example, also in the transistor300illustrated inFIG.26, a material that can have ferroelectricity can be used as in the transistor200illustrated inFIG.27AtoFIG.27C. For example, when a silicon substrate is used as the substrate311of the transistor300, the Si transistor can function as an FeFET.

At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with any of those in the other embodiments, the other examples, and the like described in this specification.

In this embodiment, a storage device of one embodiment of the present invention, which includes a transistor in which oxide is used for a semiconductor (hereinafter referred to as an OS transistor in some cases) and a ferroelectric capacitor, will be described with reference toFIG.28AandFIG.28B. The device of this embodiment is a storage device that includes at least a capacitor and an OS transistor controlling charging and discharging of the capacitor. The device of this embodiment functions as a one-transistor one-capacitor ferroelectric memory that includes a ferroelectric capacitor.

Structure Example of Storage Device

FIG.28Aillustrates a structure example of a storage device. A storage device1400includes a peripheral circuit1411and a memory cell array1470. The peripheral circuit1411includes a row circuit1420, a column circuit1430, an output circuit1440, and a control logic circuit1460.

The column circuit1430includes, for example, a column decoder, a bit line driver circuit, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging wirings. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the wirings are connected to memory cells included in the memory cell array1470, and are described later in detail. The amplified data signal is output as a data signal RDATA to the outside of the storage device1400through the output circuit1440. The row circuit1420includes, for example, a row decoder and a word line driver circuit, and can select a row to be accessed.

As power supply voltages from the outside, a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit1411, and a high power supply voltage (VIL) for the memory cell array1470are supplied to the storage device1400. Control signals (CE, WE, and RE), an address signal ADDR, and a data signal WDATA are also input to the storage device1400from the outside. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit.

The control logic circuit1460processes the control signals (CE, WE, and RE) input from the outside, and generates control signals for the row decoder and the column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. Signals processed by the control logic circuit1460are not limited thereto, and other control signals are input as necessary.

The memory cell array1470includes a plurality of memory cells MC arranged in a matrix and a plurality of wirings. Note that the number of wirings that connect the memory cell array1470and the row circuit1420depends on the structure of the memory cell MC, the number of memory cells MC in a column, and the like. The number of wirings that connect the memory cell array1470and the column circuit1430depends on the structure of the memory cell MC, the number of memory cells MC in a row, and the like.

Note thatFIG.28Aillustrates an example where the peripheral circuit1411and the memory cell array1470are formed on the same plane; however, this embodiment is not limited thereto. For example, as illustrated inFIG.28B, the memory cell array1470may be provided to overlap with part of the peripheral circuit1411. For example, the sense amplifier may be provided below the memory cell array1470so that they overlap with each other.

Note that the structures of the peripheral circuit1411, the memory cell array1470, and the like described in this embodiment are not limited to the above. The arrangement and functions of these circuits and the wirings, circuit components, and the like connected to the circuits can be changed, removed, or added as needed. The storage device of one embodiment of the present invention operates fast and can retain data for a long time.

Structure Example of Memory Cell

The circuit diagram inFIG.29Ashows a structure example of the memory cell MC described above. The memory cell MC includes a transistor Tr and a capacitor Fe. Here, as the memory cell MC, the semiconductor device including the transistor200and the capacitor100, which is described in the above embodiment, can be used, for example. In this case, the transistor Tr and the capacitor Fe correspond to the transistor200and the capacitor100, respectively. Note that the transistor Tr may have a back gate in addition to the gate or may have no back gate. The transistor Tr is illustrated as an n-channel transistor inFIG.29A, but may be a p-channel transistor.

One of a source and a drain of the transistor Tr is electrically connected to a wiring BL. The other of the source and the drain of the transistor Tr is electrically connected to one electrode of the capacitor Fe. The gate of the transistor Tr is electrically connected to a wiring WL. The other electrode of the capacitor Fe is electrically connected to a wiring PL.

The wiring WL has a function of a word line and can control on/off of the transistor Tr by controlling the potential of the wiring WL. For example, setting the potential of the wiring WL to a high potential can bring the transistor Tr into an on state; setting the potential of the wiring WL to a low potential can bring the transistor Tr into an off state. The wiring WL is electrically connected to the word line driver circuit included in the row circuit1420, and the potential of the wiring WL can be controlled by the word line driver circuit.

The wiring BL has a function of a bit line. When the transistor Tr is in an on state, a potential corresponding to the potential of the wiring BL is supplied to the one electrode of the capacitor Fe. The wiring BL is electrically connected to the bit line driver circuit of the column circuit1430. The bit line driver circuit has a function of generating data to be written to the memory cell MC. Furthermore, the bit line driver circuit has a function of reading data output from the memory cell MC. Specifically, the sense amplifier is provided in the bit line driver circuit, and data output from the memory cell MC can be read using the sense amplifier.

The wiring PL has a function of a plate line, and the potential of the wiring PL can be set to the potential of the other electrode of the capacitor Fe.

An OS transistor is preferably used as the transistor Tr. An OS transistor has a feature of high withstand voltage. Thus, the transistor Tr is an OS transistor, whereby a high voltage can be applied to the transistor Tr even when the transistor Tr is miniaturized. The miniaturization of the transistor Tr can reduce the area occupied by the memory cell MC. For example, the area occupied by one memory cell MC illustrated inFIG.29Acan be ⅓ to ⅙ of the area occupied by one SRAM cell. Accordingly, the memory cells MC can be arranged at high density. Therefore, the storage device of one embodiment of the present invention can have large storage capacity.

The capacitor Fe contains a material that can have ferroelectricity as a dielectric layer between the two electrodes. The dielectric layer included in the capacitor Fe is referred to as a ferroelectric layer in the following description.

As the material that can have ferroelectricity, the above-described material that can be used for the insulator130is used. In particular, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferable as the material that can have ferroelectricity because they can have ferroelectricity when processed into a several-nanometer-thick thin film. With the ferroelectric layer that can be made to be a thin film, the storage device combined with a miniaturized transistor can be obtained.

The ferroelectric layer has hysteresis characteristics. FIG.29B1is a graph showing an example of the hysteresis characteristics. The horizontal axis in FIG.29B1represents a voltage applied to the ferroelectric layer. The voltage can be a difference between the potential of one electrode of the capacitor Fe and the potential of the other electrode of the capacitor Fe, for example.

The vertical axis in FIG.29B1represents the amount of polarization of the ferroelectric layer and shows that negative electric charge is biased to the one electrode of the capacitor Fe and positive electric charge is biased to the other electrode of the capacitor Fe when the amount of polarization has a positive value. In contrast, when the amount of polarization has a negative value, it shows that negative electric charge is biased to the other electrode of the capacitor Fe and positive electric charge is biased to the one electrode of the capacitor Fe.

Note that the voltage represented by the horizontal axis of the graph of FIG.29B1may be a difference between the potential of the other electrode of the capacitor Fe and the potential of the one electrode of the capacitor Fe. Moreover, the amount of polarization (also referred to as polarization) represented by the vertical axis of the graph of FIG.29B1may have a positive value when negative electric charge is biased to the other electrode of the capacitor Fe and positive electric charge is biased to the one electrode of the capacitor Fe, and may have a negative value when negative electric charge is biased to the one electrode of the capacitor Fe and positive electric charge is biased to the other electrode of the capacitor Fe.

As shown in FIG.29B1, the hysteresis characteristics of the ferroelectric layer can be represented by a curve51and a curve52. Voltages at intersection points of the curve51and the curve52are referred to as VSP and −VSP. VSP and −VSP have different polarities.

After a voltage lower than or equal to −VSP is applied to the ferroelectric layer, the voltage applied to the ferroelectric layer is increased, so that the amount of polarization of the ferroelectric layer is increased according to the curve51. In contrast, after a voltage higher than or equal to VSP is applied to the ferroelectric layer, the voltage applied to the ferroelectric layer is reduced, so that the amount of polarization of the ferroelectric layer is decreased according to the curve52. Therefore, VSP and −VSP can be referred to as saturated polarization voltages. For example, VSP and −VSP may be called a first saturated polarization voltage and a second saturated polarization voltage, respectively. Although the absolute value of the first saturated polarization voltage and the absolute value of the second saturated polarization voltage are equal to each other in FIG.29B1, they may be different from each other.

Here, in the case where the amount of polarization of the ferroelectric layer is varied according to the curve51, the voltage applied to the ferroelectric layer at the time when the amount of polarization of the ferroelectric layer is 0 is referred to as Vc. When the amount of polarization of the ferroelectric layer is varied according to the curve52, the voltage applied to the ferroelectric layer at the time when the amount of polarization of the ferroelectric layer is 0 is referred to as −Vc. Vc and −Vc can be referred to as coercive voltages. The value of Vc and the value of −Vc can be values between −VSP and VSP. Note that Vc and −Vc may be called a first coercive voltage and a second coercive voltage, respectively. Although the absolute value of the first coercive voltage and the absolute value of the second coercive voltage are equal to each other in FIG.29B1, they may be different from each other.

As described above, the voltage applied to the ferroelectric layer included in the capacitor Fe can be represented by the difference between the potential of the one electrode of the capacitor Fe and the potential of the other electrode of the capacitor Fe. In addition, as described above, the other electrode of the capacitor Fe is electrically connected to the wiring PL. Thus, it is possible to control the voltage applied to the ferroelectric layer included in the capacitor Fe by controlling the potential of the wiring PL. Note that FIG.29B2is a graph showing an example of ideal hysteresis characteristics showing the amount of polarization of the ferroelectric layer. A straight line52iand a straight line51ishown in FIG.29B2represent the ideal amount of polarization of the ferroelectric layer. In order to obtain the hysteresis characteristics shown in FIG.29B2, crystallinity of the ferroelectric material is improved, leak component from the ferroelectric material and the vicinity of the material is eliminated, or the impurity concentration in the ferroelectric material is reduced, for example. The metal oxide film of one embodiment of the present invention has high purity, and thus can be expected to have the hysteresis characteristics close to the ideal ones showing the amount of polarization of the ferroelectric layer shown in FIG.29B2.

Example of Method for Driving Memory Cell

An example of a method for driving the memory cell MC illustrated inFIG.29Awill be described below. In the following description, the voltage applied to the ferroelectric layer of the capacitor Fe represents a difference between the potential of one electrode of the capacitor Fe and the potential of the other electrode of the capacitor Fe (the wiring PL). The transistor Tr is an re-channel transistor.

FIG.29Cis a timing chart showing an example of a method for driving the memory cell MC inFIG.29A. In the example shown inFIG.29C, binary digital data is written to and read from the memory cell MC. Specifically, in the example shown inFIG.29C, data “1” is written to the memory cell MC in a period from Time T01to Time T02, reading and rewriting are performed in a period from Time T03to Time T05, reading and writing of data “0” to the memory cell MC are performed in a period from Time T11to Time T13, reading and rewriting are performed in a period from Tim T14to Time T16, and reading and writing of data “1” to the memory cell MC are performed in a period from Time T17to Time T19.

The sense amplifier electrically connected to the wiring BL is supplied with Vref as a reference potential. In the reading operation shown inFIG.29Cand the like, when the potential of the wiring BL is higher than Vref, data “1” is read by the bit line driver circuit. On the other hand, when the potential of the wiring BL is lower than Vref, data “0” is read by the bit line driver circuit.

In the period from Time T01to Time T02, the potential of the wiring WL is set to a high potential. Thus, the transistor Tr is brought into an on state. In addition, the potential of the wiring BL is set to Vw. Since the transistor Tr is in an on state, the potential of the one electrode of the capacitor Fe becomes Vw. Furthermore, the potential of the wiring PL is set to GND. Thus, the voltage applied to the ferroelectric layer of the capacitor Fe becomes “Vw−GND”. Accordingly, data “1” can be written to the memory cell MC. Consequently, the period from Time T01to Time T02can be referred to as a write operation period.

Here, Vw is preferably VSP or higher, for example, preferably equal to VSP. GND can be set to a ground potential, for example; however, GND is not necessarily a ground potential as long as the memory cell MC can be driven enough to achieve an object of one embodiment of the present invention. For example, when the absolute value of the first saturated polarization voltage and the absolute value of the second saturated polarization voltage are different from each other and the absolute value of the first coercive voltage and the absolute value of the second coercive voltage are different from each other, GND can be a potential other than a ground potential.

In the period from Time T02to Time T03, the potential of the wiring BL and the potential of the wiring PL are each set to GND. Accordingly, the voltage applied to the ferroelectric layer of the capacitor Fe becomes 0 V. Since the voltage “Vw−GND” applied to the ferroelectric layer of the capacitor Fe can be higher than or equal to VSP in the period from Time T01to Time T02, the amount of polarization of the ferroelectric layer of the capacitor Fe is varied according to the curve52shown inFIG.29Bin the period from Time T02to Time T03. Thus, no polarization inversion occurs in the ferroelectric layer of the capacitor Fe in the period from Time T02to Time T03.

After the potential of the wiring BL and the potential of the wiring PL are set to GND, the potential of the wiring WL is set to a low potential. Accordingly, the transistor Tr is brought into an off state. Thus, the writing operation is completed and data “1” is retained in the memory cell MC. Note that the potentials of the wiring BL and the wiring PL can each be any potential as long as no polarization inversion occurs in the ferroelectric layer of the capacitor Fe, i.e., the voltage applied to the ferroelectric layer of the capacitor Fe is higher than or equal to −Vc that is the second coercive voltage.

In the period from Time T03to Time T04, the potential of the wiring WL is set to a high potential. Thus, the transistor Tr is turned on. Furthermore, the potential of the wiring PL is set to Vw. With the potential of the wiring PL set to Vw, the potential applied to the ferroelectric layer of the capacitor Fe becomes “GND−Vw”. As described above, the voltage applied to the ferroelectric layer of the capacitor Fe is “Vw−GND” in the period from Time T01to Time T02. Accordingly, polarization inversion occurs in the ferroelectric layer of the capacitor Fe. In the polarization inversion, a current flows through the wiring BL, whereby the potential of the wiring BL becomes higher than Vref. Thus, the bit line driver circuit can read the data “1” retained in the memory cell MC. Therefore, the period from Time T03to Time T04can be referred to as a read operation period. Note that although Vref is higher than GND and lower than Vw, Vref may be higher than Vw, for example.

Since the above-described reading is destructive reading, the data “1” retained in the memory cell MC is lost. Thus, the potential of the wiring BL is set to Vw and the potential of the wiring PL is set to GND in the period from Time T04to Time T05. Thus, data “1” is rewritten to the memory cell MC. Consequently, the period from Time T04to Time T05can be referred to as a rewrite operation period.

The potential of the wiring BL and the potential of the wiring PL are set to GND in a period from Time T05to Time T11. After that, the potential of the wiring WL is set to a low potential. Thus, the rewrite operation is completed, and the data “1” is retained in the memory cell MC.

The potential of the wiring WL is set to a high potential and the potential of the wiring PL is set to Vw in a period from Time T11to Time T12. Since the data “1” is retained in the memory cell MC, the potential of the wiring BL becomes higher than Vref, and the data “1” retained in the memory cell MC is read. Accordingly, the period from Time T11to Time T12can be referred to as a read operation period.

The potential of the wiring BL is set to GND in a period from Time T12to Time T13. Since the transistor Tr is in an on state, the potential of the one electrode of the capacitor Fe is GND. In addition, the potential of the wiring PL is Vw. Accordingly, the voltage applied to the ferroelectric layer of the capacitor Fe becomes “GND−Vw”. Thus, data “0” can be written to the memory cell MC. Consequently, the period from Time T12to Time T13can be referred to as a write operation period.

In the period from Time T13to Time T14, the potential of the wiring BL and the potential of the wiring PL are each set to GND. Accordingly, the voltage applied to the ferroelectric layer of the capacitor Fe becomes 0 V. Since the voltage “GND−Vw” applied to the ferroelectric layer of the capacitor Fe can be lower than or equal to −VSP in the period from Time T12to Time T13, the amount of polarization of the ferroelectric layer of the capacitor Fe is varied according to the curve51shown inFIG.29Bin the period from Time T13to Time T14. Thus, no polarization inversion occurs in the ferroelectric layer of the capacitor Fe in the period from Time T13to Time T14.

After the potential of the wiring BL and the potential of the wiring PL are set to GND, the potential of the wiring WL is set to a low potential. Accordingly, the transistor Tr is turned off. Thus, the writing operation is completed and data “0” is retained in the memory cell MC. Note that the potentials of the wiring BL and the wiring PL can each be any potential as long as no polarization inversion occurs in the ferroelectric layer of the capacitor Fe, i.e., the voltage applied to the ferroelectric layer of the capacitor Fe is lower than or equal to Vc that is the first coercive voltage.

In a period from Time T14to Time T15, the potential of the wiring WL is set to a high potential. Thus, the transistor Tr is brought into an on state. Furthermore, the potential of the wiring PL is set to Vw. With the potential of the wiring PL set to Vw, the potential applied to the ferroelectric layer of the capacitor Fe becomes “GND−Vw”. As described above, the voltage applied to the ferroelectric layer of the capacitor Fe is “GND−Vw” in the period from Time T12to Time T13. Accordingly, no polarization inversion occurs in the ferroelectric layer of the capacitor Fe. Thus, the amount of current flowing through the wiring BL is smaller than that in the case where polarization inversion occurs in the ferroelectric layer of the capacitor Fe. Accordingly, an increase in the potential of the wiring BL is smaller than that in the case where polarization inversion occurs in the ferroelectric layer of the capacitor Fe; specifically, the potential of the wiring BL becomes lower than or equal to Vref. Consequently, the bit line driver circuit can read the data “0” retained in the memory cell MC. Therefore, the period from Time T14to Time T15can be referred to as a read operation period.

The potential of the wiring BL is set to GND and the potential of the wiring PL is Vw in a period from Time T15to Time T16. Thus, data “0” is rewritten to the memory cell MC. Therefore, the period from Time T15to Time T16can be referred to as a rewrite operation period.

The potential of the wiring BL and the potential of the wiring PL are set to GND in a period from Time T16to Time T17. After that, the potential of the wiring WL is set to a low potential. Thus, the rewrite operation is completed, and the data “0” is retained in the memory cell MC.

The potential of the wiring WL is set to a high potential and the potential of the wiring PL is set to Vw in a period from Time T17to Time T18. Since the data “0” is retained in the memory cell MC, the potential of the wiring BL becomes lower than Vref, and the data “0” retained in the memory cell MC is read. Therefore, the period from Time T17to Time T18can be referred to as a read operation period.

The potential of the wiring BL is set to Vw in a period from Time T18to Time T19. Since the transistor Tr is in an on state, the potential of the one electrode of the capacitor Fe becomes Vw. In addition, the potential of the wiring PL is GND. Accordingly, the voltage applied to the ferroelectric layer of the capacitor Fe becomes “Vw−GND”. Thus, data “1” can be written to the memory cell MC. Therefore, the period from Time T18to Time T19can be referred to as a write operation period.

From Time T19, the potential of the wiring BL and the potential of the wiring PL are set to GND. Then, the potential of the wiring WL is set to a low potential. Thus, the write operation is completed, and the data “1” is retained in the memory cell MC.

The structure, method, and the like described in this embodiment can be used in an appropriate combination with any of other structures, methods, and the like described in this embodiment or the other embodiments.

In this embodiment, application examples of the storage device using the semiconductor device described in the above embodiment are described. The semiconductor device described in the above embodiment can be applied to, for example, storage devices of a variety of electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), video recording/reproducing devices, and navigation systems). Here, the computers refer not only to tablet computers, notebook computers, and desktop computers, but also to large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment is applied to a variety of removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives).FIG.30AtoFIG.30Eschematically illustrate some structure examples of removable storage devices. The semiconductor device described in the above embodiment is processed into a packaged memory chip and used in a variety of storage devices and removable memories, for example.

FIG.30Ais a schematic view of a USB memory. A USB memory1100includes a housing1101, a cap1102, a USB connector1103, and a substrate1104. The substrate1104is held in the housing1101. The substrate1104is provided with a memory chip1105and a controller chip1106, for example. The semiconductor device described in the above embodiment can be incorporated in the memory chip1105or the like. Therefore, the storage capacity of the USB memory1100can be further increased.

FIG.30Bis a schematic external view of an SD card, andFIG.30Cis a schematic view of the internal structure of the SD card. An SD card1110includes a housing1111, a connector1112, and a substrate1113. The substrate1113is held in the housing1111. The substrate1113is provided with a memory chip1114and a controller chip1115, for example. When the memory chip1114is also provided on the back side of the substrate1113, the capacity of the SD card1110can be increased. In addition, a wireless chip with a radio communication function may be provided on the substrate1113. With this, data can be read from and written in the memory chip1114by radio communication between a host device and the SD card1110. The semiconductor device described in the above embodiment can be incorporated in the memory chip1114or the like. Therefore, the storage capacity of the SD card1110can be further increased.

FIG.30Dis a schematic external view of an SSD, andFIG.30Eis a schematic view of the internal structure of the SSD. An SSD1150includes a housing1151, a connector1152, and a substrate1153. The substrate1153is held in the housing1151. The substrate1153is provided with a memory chip1154, a memory chip1155, and a controller chip1156, for example. The memory chip1155is a work memory of the controller chip1156, and a DOSRAM chip can be used, for example. When the memory chip1154is also provided on the back side of the substrate1153, the capacity of the SSD1150can be increased. The semiconductor device described in the above embodiment can be incorporated in the memory chip1154or the like. Therefore, the storage capacity of the SSD1150can be further increased.

At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with any of those in the other embodiments and the other examples described in this specification.

The semiconductor device of one embodiment of the present invention can be used for processors such as CPUs or GPUs, or chips. When the semiconductor device described in the above embodiment is used for processors such as CPUs or GPUs, or chips, their sizes can be reduced and their storage capacities can be increased.FIG.31AtoFIG.31Hillustrate specific examples of electronic devices each including a processor such as a CPU or a GPU or a chip of one embodiment of the present invention.

<Electronic Devices and Systems>

The GPU or the chip of one embodiment of the present invention can be mounted on a variety of electronic devices. Examples of electronic devices include a digital camera, a digital video camera, a digital photo frame, an e-book reader, a mobile phone, a portable game machine, a portable information terminal, and an audio reproducing device in addition to electronic devices provided with a relatively large screen, such as a television device, a monitor for a desktop or notebook information terminal or the like, digital signage, and a large game machine like a pachinko machine. When the GPU or the chip of one embodiment of the present invention is provided in the electronic device, the electronic device can include artificial intelligence.

The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, the electronic device can display a video, data, or the like on a display portion. When the electronic device includes the antenna and a secondary battery, the antenna may be used for contactless power transmission.

FIG.31Aillustrates a mobile phone (smartphone), which is a type of information terminal. An information terminal5100includes a housing5101and a display portion5102. As input interfaces, a touch panel is provided in the display portion5102and a button is provided in the housing5101.

When the chip of one embodiment of the present invention is applied to the information terminal5100, the information terminal5100can execute an application utilizing artificial intelligence. Examples of the application utilizing artificial intelligence include an application for recognizing a conversation and displaying the content of the conversation on the display portion5102; an application for recognizing letters, figures, and the like input to the touch panel of the display portion5102by a user and displaying them on the display portion5102; and an application for performing biometric authentication using fingerprints, voice prints, or the like.

FIG.31Billustrates a notebook information terminal5200. The notebook information terminal5200includes a main body5201of the information terminal, a display portion5202, and a keyboard5203.

When the chip of one embodiment of the present invention is applied to the notebook information terminal5200, the notebook information terminal5200can execute an application utilizing artificial intelligence like the information terminal5100described above. Examples of the application utilizing artificial intelligence include design-support software, text correction software, and software for automatic menu generation. Furthermore, with the use of the notebook information terminal5200, novel artificial intelligence can be developed.

Note that althoughFIG.31AandFIG.31Billustrate a smartphone and a notebook information terminal, respectively, as examples of the electronic device in the above description, an information terminal other than a smartphone and a notebook information terminal can be used. Examples of information terminals other than a smartphone and a notebook information terminal include a PDA (Personal Digital Assistant), a desktop information terminal, and a workstation.

FIG.31Cillustrates a portable game machine5300as an example of a game machine. The portable game machine5300includes a housing5301, a housing5302, a housing5303, a display portion5304, a connection portion5305, an operation key5306, and the like. The housing5302and the housing5303can be detached from the housing5301. When the connection portion5305provided in the housing5301is attached to another housing (not illustrated), an image to be output to the display portion5304can be output to another video device (not illustrated). In that case, the housing5302and the housing5303can each function as an operating unit. Thus, a plurality of players can play a game at the same time. The chip described in the above embodiment can be incorporated into the chip provided on a substrate in the housing5301, the housing5302and the housing5303.

FIG.31Dillustrates a stationary game machine5400as an example of a game machine. A controller5402is wired or connected wirelessly to the stationary game machine5400.

Using the GPU or the chip of one embodiment of the present invention in a game machine such as the portable game machine5300and the stationary game machine5400achieves a low-power-consumption game machine. Moreover, heat generation from a circuit can be reduced owing to low power consumption; thus, the influence of heat generation on the circuit itself, a peripheral circuit, and a module can be reduced.

Furthermore, when the GPU or the chip of one embodiment of the present invention is applied to the portable game machine5300, the portable game machine5300including artificial intelligence can be achieved.

In general, the progress of a game, the actions and words of game characters, and expressions of an event and the like occurring in the game are determined by the program in the game; however, the use of artificial intelligence in the portable game machine5300enables expressions not limited by the game program. For example, it becomes possible to change expressions such as questions posed by the player, the progress of the game, time, and actions and words of game characters.

In addition, when a game requiring a plurality of players is played on the portable game machine5300, the artificial intelligence can create a virtual game player; thus, the game can be played alone with the game player created by the artificial intelligence as an opponent.

Although the portable game machine and the stationary game machine are illustrated as examples of game machines inFIG.31CandFIG.31D, the game machine using the GPU or the chip of one embodiment of the present invention is not limited thereto. Examples of the game machine to which the GPU or the chip of one embodiment of the present invention is applied include an arcade game machine installed in entertainment facilities (a game center, an amusement park, and the like), and a throwing machine for batting practice installed in sports facilities.

The GPU or the chip of one embodiment of the present invention can be used in a large computer.

FIG.31Eillustrates a supercomputer5500as an example of a large computer.FIG.31Fillustrates a rack-mount computer5502included in the supercomputer5500.

The supercomputer5500includes a rack5501and a plurality of rack-mount computers5502. The plurality of computers5502are stored in the rack5501. The computer5502includes a plurality of substrates5504on which the GPU or the chip shown in the above embodiment can be mounted.

The supercomputer5500is a large computer mainly used for scientific computation. In scientific computation, an enormous amount of arithmetic operation needs to be processed at a high speed; hence, power consumption is large and chips generate a large amount of heat. Using the GPU or the chip of one embodiment of the present invention in the supercomputer5500achieves a low-power-consumption supercomputer. Moreover, heat generation from a circuit can be reduced owing to low power consumption; thus, the influence of heat generation on the circuit itself, a peripheral circuit, and a module can be reduced.

Although a supercomputer is illustrated as an example of a large computer inFIG.31EandFIG.31F, a large computer using the GPU or the chip of one embodiment of the present invention is not limited thereto. Other examples of large computers in which the GPU or the chip of one embodiment of the present invention is usable include a computer that provides service (a server) and a large general-purpose computer (a mainframe).

The GPU or the chip of one embodiment of the present invention can be applied to an automobile, which is a moving vehicle, and the periphery of a driver's seat in the automobile.

FIG.31Gillustrates an area around a windshield inside an automobile, which is an example of a moving vehicle.FIG.31Gillustrates a display panel5701, a display panel5702, and a display panel5703that are attached to a dashboard and a display panel5704that is attached to a pillar.

The display panel5701to the display panel5703can provide a variety of kinds of information by displaying a speedometer, a tachometer, mileage, a fuel gauge, a gear state, air-condition setting, and the like. In addition, the content, layout, or the like of the display on the display panels can be changed as appropriate to suit the user's preference, so that the design quality can be increased. The display panel5701to the display panel5703can also be used as lighting devices.

The display panel5704can compensate for view obstructed by the pillar (a blind spot) by showing an image taken by an imaging device (not illustrated) provided for the automobile. That is, displaying an image taken by the imaging device provided outside the automobile leads to compensation for the blind spot and an increase in safety. Display of an image that complements the area that cannot be seen makes it possible to confirm safety more naturally and comfortably. The display panel5704can also be used as a lighting device.

Since the GPU or the chip of one embodiment of the present invention can be applied to a component of artificial intelligence, the chip can be used for an automatic driving system of the automobile, for example. The chip can also be used for a system for navigation, risk prediction, or the like. A structure may be employed in which the display panel5701to the display panel5704display navigation information, risk prediction information, or the like.

Note that although an automobile is described above as an example of a moving vehicle, the moving vehicle is not limited to an automobile. Examples of the moving vehicle include a train, a monorail train, a ship, and a flying vehicle (a helicopter, an unmanned aircraft (a drone), an airplane, and a rocket), and these moving vehicles can each include a system utilizing artificial intelligence when the chip of one embodiment of the present invention is applied to each of these moving vehicles.

FIG.31Hillustrates an electric refrigerator-freezer5800as an example of a household appliance. The electric refrigerator-freezer5800includes a housing5801, a refrigerator door5802, a freezer door5803, and the like.

When the chip of one embodiment of the present invention is applied to the electric refrigerator-freezer5800, the electric refrigerator-freezer5800including artificial intelligence can be achieved. Utilizing the artificial intelligence enables the electric refrigerator-freezer5800to have a function of automatically making a menu based on foods stored in the electric refrigerator-freezer5800, expiration dates of the foods, or the like, a function of automatically adjusting temperature to be appropriate for the foods stored in the electric refrigerator-freezer5800, and the like.

Although the electric refrigerator-freezer is described in this example as a household appliance, examples of other household appliances include a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, a heating-cooling combination appliance such as an air conditioner, a washing machine, a drying machine, and an audio visual appliance.

The electronic devices, the functions of the electronic devices, the application examples of artificial intelligence, their effects, and the like described in this embodiment can be combined as appropriate with the description of another electronic device.

At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with any of those in the other embodiments and the other examples described in this specification.

In this example, hafnium zirconium oxide (HfZrOx) was fabricated as an insulator exhibiting ferroelectricity, and measurement results of the voltage—polarization characteristics, the fatigue characteristics, and the like of the insulator are described.

FIG.32Ais an optical micrograph showing the appearance of a sample800used for evaluation.FIG.32Bis a schematic cross-sectional view of the sample800.

The sample800was formed using single crystal silicon as a substrate801. Specifically, a 100-nm-thick thermal oxide film was formed as an insulator802on the substrate801, a conductor803(a conductor803aand a conductor803b) functioning as a lower electrode was formed over the insulator802, an insulator804was formed over the conductor803, and a conductor805(a conductor805aand a conductor805b) functioning as an upper electrode was formed over the insulator804.

In addition, an insulator806was formed over the conductor803, the insulator804, and the conductor805. Furthermore, a conductor807electrically connected to the conductor803, and a conductor808electrically connected to the conductor805were formed over the insulator806. The conductor807and the conductor808function as electrodes to which measurement signals are input.

Note that formation of the conductor803, the conductor805, the conductor807, and the conductor808, formation of a contact hole provided in the insulator806and the insulator804, and the like were performed by a known photolithography method and a known etching method.

Three samples800(a sample800A, a sample800B, and a sample800C) which differed in conditions of formation of the conductor805functioning as an upper electrode and conditions of heat treatment after the formation of the upper electrode were fabricated.

Table 1 shows deposition conditions of the conductor803a, the conductor803b, the insulator804, the conductor805a, and the conductor805b, which are provided in each of the sample800A, the sample800B, and the sample800C.

Although not shown in Table 1, 200-nm-thick silicon oxynitride was deposited as the insulator806by a PECVD method. Furthermore, a stacked-layer film of three layers of 50-nm-thick Ti, 200-nn-thick Al, and 50-nm-thick Ti was deposited as the conductor807and the conductor808by a sputtering (SP) method.

The conductor805aof each of the sample800A and the sample800B was deposited by a sputtering method, and the conductor805aof the sample800C was deposited by a metal CVD (MCVD) method. In addition, after being fabricated, the sample800B was subjected to heat treatment by an RTA method. Table 1 also shows conditions of the heat treatment.

A triangular wave with a voltage amplitude of 3 V and a frequency of 100 Hz was applied between the conductor807and the conductor803, and a change in spontaneous polarization (P-E characteristics) of the insulator804was measured.FIG.32Cshows a waveform of the input voltage. In addition, the crystal state of the HfZrOx film corresponding to the insulator804of each of the sample800A, the sample800B, and the sample800C was investigated using grazing incident X-ray diffraction (GIXD), which is a kind of XRD analysis method.

Here, a method for obtaining P-E characteristics using a triangular wave is described. First, an input voltage V, which is a triangular wave, is applied between two electrodes of a measurement target sample (capacitor) (FIG.33A), and a current flowing between the electrodes (output current I) is measured (FIG.33B). Note that the horizontal axis inFIG.33AandFIG.33Brepresents elapsed time t. Next, I-V characteristics showing the relationship between the input voltage V and the output current I are obtained (FIG.33C).

Next, the output current I is converted to polarization P using Formula 1 to obtain P-E characteristics (FIG.33D).

In Formula 1, A represents the area where the two electrodes of the capacitor overlap with each other.

From Q=CV, the relationship between the input voltage V and a capacitance C can be obtained (FIG.33E). In addition, the relationship between the input voltage V and the dielectric constant εr can be obtained (FIG.33F).

FIG.34Ashows measurement results of the P-E characteristics of the sample800A, the sample800B, and the sample800C. InFIG.34A, the relationship between electric field intensity E applied to the insulator804and the polarization P is shown for each sample.FIG.34Bshows GIXD measurement results. InFIG.34B, the relationship between a diffraction angle (2θ) of X-ray and detected signal intensity is shown for each sample.

It is found fromFIG.34Athat hysteresis characteristics are obtained in the three samples (the sample800A, the sample800B, and the sample800C), and the three samples function as ferroelectrics. Note that the amount of polarization (the difference between the maximum polarization and the minimum polarization at the time when the electric field intensity E is 0 in the P-E characteristics) of the sample800A is smaller than those of the sample800B and the sample800C, which indicates that the sample800A is close to a paraelectric.

It is found fromFIG.34Bthat in each of the three samples, no signal intensity peak is detected in the vicinity of a diffraction angle at which monoclinic crystal (m) is detected, and a signal intensity peak is observed in the vicinity of a diffraction angle indicating an orthorhombic crystal (o), a tetragonal crystal (t), or a cubit crystal (c). When the measurement results shown inFIG.34Aare taken into consideration, an orthorhombic crystal functioning as a ferroelectric is presumed to be detected. Furthermore, it is also found fromFIG.34Bthat the sample800A is closer to a paraelectric than the sample800B and the sample800C are.

In general, a larger amount of polarization (hysteresis characteristics) is preferred in a ferroelectric. A comparison between the sample800A and the sample800B, in each of which the conductor805awas deposited by a sputtering method, shows that the sample800A not subjected to heat treatment after the fabrication does not have large hysteresis characteristics. Meanwhile, the sample800C, in which the conductor805awas deposited by a metal CVD method, has an amount of polarization (hysteresis characteristics) equivalent to that of the sample800B subjected to heat treatment, even though heat treatment was not performed on the sample800C after the fabrication. Deposition of the conductor805aby a metal CVD method enables a reduction in the number of steps for fabricating the sample.

Cross-sectional TEM images of the sample800A to the sample800C fabricated in the above manner were obtained with the use of “H-9500” manufactured by Hitachi High-Technologies Corporation at an accelerating voltage of 300 kV to show the respective insulators804and the vicinities thereof.FIG.35A,FIG.36A, andFIG.37Aare the cross-sectional TEM image of the sample800A, the cross-sectional TEM image of the sample800B, and the cross-sectional TEM image of the sample800C, respectively.

Furthermore, a region A1and a region A2in the TEM image ofFIG.35A, a region B1and a region B2in the TEM image ofFIG.36A, and a region C1and a region C2in the TEM image ofFIG.37Awere subjected to FFT (Fast Fourier Transform) analysis. FFT analysis on a TEM image yields an FFT figure having a pattern reflecting reciprocal lattice space information like an electron diffraction pattern. For example, in the case of a cross-sectional TEM image of an HfZrOx film, spots having high intensity are observed in the FFT figure in some cases.

FIG.35B,FIG.36B, andFIG.37Bshow the FFT analysis results.FIG.35Bis an FFT figure of the region A1,FIG.35Cis an FFT figure of the region A2,FIG.36Bis an FFT figure of the region B1,FIG.36Cis an FFT figure of the region B2,FIG.37Bis an FFT figure of the region C1, andFIG.37Cis an FFT figure of the region C2.

In the sample800B, existence of a plurality of bright spots can be observed in the region B1and the region B2. Similarly, in the sample800C, a plurality of bright spots can be observed in the region C1and the region C2. Meanwhile, in the sample800A, a spot can be observed in the region A1but no spot can be observed in the region A2. That is, the sample800B and the sample800C were found to have higher crystallinity than the sample800A. Thus, the sample800B and the sample800C having a larger amount of polarization and higher ferroelectricity were found to have high crystallinity.

Next, cross-sectional TEM images of the sample800A to the sample800C were obtained with the use of “H-9500” manufactured by Hitachi High-Technologies Corporation at an accelerating voltage of 300 kV to show the respective vicinities of interfaces between the insulator804and the conductor805a.FIG.38A,FIG.38B, andFIG.38Care the cross-sectional TEM image of the sample800A, the cross-sectional TEM image of the sample800B, and the cross-sectional TEM image of the sample800C, respectively. Note that inFIG.38AtoFIG.38C, focused crystal lattice fringes are enlarged and shown by solid lines.

As shown inFIG.38A, in the sample800A, lattice fringes derived from crystals of TiNx were observed in the conductor805a. As shown inFIG.38B, in the sample800B, lattice fringes derived from crystals of HfZrOx were observed in the insulator804. As shown inFIG.38C, in the sample800C, lattice fringes derived from crystals of TiNx were observed in the conductor805aand lattice fringes derived from crystals of HfZrOx were observed in the insulator804. As described above, lattice fringes derived from crystals of TiNx or HfZrOx were observed in the vicinity of the interface between the insulator804and the conductor805ain each of the sample800A to the sample800C. On the other hand, in the cross-sectional TEM images inFIG.38AtoFIG.38C, no different layer (e.g., TiOx) was observed in the vicinity of the interface between the insulator804and the conductor805a. Thus, it is considered that even when a different layer exists at the interface between the insulator804and the conductor805a, the thickness of the different layer is less than or equal to 1 nm.

Then, in each of the sample800A to the sample800C, the vicinity of the interface between the insulator804and the conductor805aand the vicinity of the interface between the insulator804and the conductor803bwere subjected to analysis by energy dispersive X-ray spectroscopy (EDX). The EDX analysis was performed on points on a straight line vertically crossing the interface. In this specification and the like, such EDX analysis is referred to as line EDX analysis in some cases. Note that the line EDX analysis was performed with the use of “HD-2700” manufactured by Hitachi High-Technologies Corporation at an accelerating voltage of 200 kV.

In this line EDX analysis, oxygen atoms [atomic %] and hafnium atoms [atomic %] were detected, and the half values of the oxygen atoms [atomic %] and the hafnium atoms [atomic %] in the vicinity of the interface between the insulator804and the conductor805aand the vicinity of the interface between the insulator804and the conductor803bwere calculated. In the case where a different layer of TiOx or the like is not formed in the vicinity of the interface between the insulator804and the conductor805a(or the vicinity of the interface between the insulator804and the conductor803b), the half value of the oxygen atoms [atomic %] and the half value of the hafnium atoms [atomic %] are equal to each other. However, in the case where a different layer of TiOx or the like is formed at the interface, the half value of the oxygen atoms [atomic %] deviates to the conductor805a(or the conductor803b) side. That is, it is estimated that a difference between the half value of the oxygen atoms [atomic %] and the half value of the hafnium atoms [atomic %] corresponds to the thickness of the TiOx.

FIG.39shows the results of the line EDX analysis. The vertical axis ofFIG.39represents the thickness of TiOx [nm]. InFIG.39, the vicinities of the interfaces between the insulator804and the conductor805ain the samples are denoted by an upper portion of800A, an upper portion of800B, and an upper portion of800C. InFIG.39, the vicinities of the interfaces between the insulator804and the conductor803bin the samples are denoted by a lower portion of800A, a lower portion of800B, and a lower portion of800C.

As shown inFIG.39, in the sample800B, the thickness of the TiOx film was 0.2 nm in the upper portion and the TiOx film as the different layer was not detected in the lower portion. Similarly, in the sample800C, the thickness of the TiOx film was 0.2 nm in the upper portion and a different layer of the TiOx film was not detected in the lower portion. Meanwhile, in the sample800A, the thickness of the TiOx film was 0.4 nm in the upper portion and the thickness of the TiOx film was 0.3 nm in the lower portion. That is, the different layer of the TiOx film tended to be thinner in the sample800B and the sample800C than in the sample800A. Thus, the sample800B and the sample800C having a larger amount of polarization and higher ferroelectricity were founded to have the thinner TiOx film as the different layer in some cases.

Next, in the sample800C, the surface roughness of the conductor803bserving as a base of the insulator804was evaluated.

First, in the sample800C, Z contrast images (ZC images) of a cross section N1to a cross section N6were obtained with the use of a dark field STEM function of “HD-2700” manufactured by Hitachi High-Technologies Corporation. The ZC images of the cross section N1to the cross section N6were subjected to image analysis and the line of interface between the insulator804and the conductor803bwas drawn on each of the ZC images. Note that for the image analysis, “Image J” was used as image processing software performing interface extraction. As for the interface lines of the cross section N1to the cross section N6, arithmetic mean roughness (Ra) and root mean square roughness (RMS) were calculated.

FIG.40Ashows Ra [nm] of the cross section N1to the cross section N6, andFIG.40Bshows RMS [nm] of the cross section N1to the cross section N6. As shown inFIG.40AandFIG.40B, the top surface roughness of the sample800C represented by Ra and RMS is less than or equal to 1 nm in the cross section N1to the cross section N6. Furthermore, the roughness represented by Ra and RMS is less than or equal to 0.4 nm in the cross section N1to the cross section N5. Thus, in order to make the insulator804have higher crystallinity and exhibit ferroelectricity, the top surface roughness of the conductor803bserving as the base is less than or equal to 2 nm, preferably less than or equal to 1 nm, further preferably less than or equal to 0.8 nm, still further preferably less than or equal to 0.5 nm, yet still further preferably less than or equal to 0.4 nm.

Next, the hydrogen (H) concentration, the carbon (C) concentration, the nitrogen (N) concentration, and the chlorine (Cl) concentration in the insulator804of each of the sample800A, the sample800B, and the sample800C were measured by secondary ion mass spectrometry (SIMS).

The SIMS analysis was conducted from the conductor805btoward the conductor803a.FIG.41toFIG.44show SIMS analysis results. The horizontal axes inFIG.41toFIG.44each represent the depth from the surface of the conductor805b, the vertical axis inFIG.41represents the hydrogen concentration in the insulator804, the vertical axis inFIG.42represents the carbon concentration in the insulator804, the vertical axis inFIG.43represents the nitrogen concentration in the insulator804, and the vertical axis inFIG.44represents the chlorine concentration in the insulator804. Furthermore, the positions of the conductor805b, the conductor805a, the insulator804, the conductor803b, and the conductor803ain the depth direction, which were specified from the thicknesses and the SIMS profiles, are shown inFIG.41toFIG.44.

InFIG.41, a curve811A represents SIMS analysis results of the sample800A, a curve811B represents SIMS analysis results of the sample800B, and a curve811C represents SIMS analysis results of the sample800C. The hydrogen concentration in the insulator804was approximately 4×1020atoms/cm3in the sample800A, approximately 2×1020atoms/cm3in the sample800B, and approximately 9×1019atoms/cm3in the sample800C.

InFIG.42, a curve812A represents SIMS analysis results of the sample800A, a curve812B represents SIMS analysis results of the sample800B, and a curve812C represents SIMS analysis results of the sample800C. The carbon concentration in the insulator804was approximately 9×1018atoms/cm3in the sample800A, approximately 1×1019atoms/cm3in the sample800B, and approximately 6×1018atoms/cm3in the sample800C (seeFIG.42).

InFIG.43, a curve813A represents SIMS analysis results of the sample800A, a curve813B represents SIMS analysis results of the sample800B, and a curve813C represents SIMS analysis results of the sample800C. The nitrogen concentration in the insulator804in each of the sample800A, the sample800B, and the sample800C seems to be less than or equal to approximately 8×1020atoms/cm3.

InFIG.44, a curve814A represents SIMS analysis results of the sample800A, a curve814B represents SIMS analysis results of the sample800B, and a curve814C represents SIMS analysis results of the sample800C. The chlorine concentration in the insulator804in each of the sample800A, the sample800B, and the sample800C was approximately 1×1021atoms/cm3.

It is found fromFIG.41andFIG.42that both the hydrogen concentration in the insulator804and the carbon concentration in the insulator804are the smallest in the sample800C, in which the conductor805awas deposited by a thermal ALD method. According toFIG.43, although the nitrogen concentration in the insulator804is possibly influenced by adjacent titanium nitride (TiNx), it is less than or equal to approximately 8×1020atoms/cm3.FIG.44andFIG.34show that the existence of chlorine in the insulator804at approximately 1×1021atoms/cm3is not a factor inhibiting the ferroelectricity exhibition.

The hydrogen concentration in the insulator804is preferably lower than or equal to 5×1020atoms/cm3, further preferably lower than or equal to 1×1020atoms/cm3. The carbon concentration in the insulator804is preferably lower than or equal to 5×1019atoms/cm3, further preferably lower than or equal to 1×1019atoms/cm3.

In this example, results of fatigue characteristics measurement performed on the sample800B and the sample800C described in Example 1 are described. The measurement of fatigue characteristics was performed on two samples800B (a sample800B_1and a sample800B_2) and three samples800C (a sample800C_1, a sample800C_2, and a sample800C_3). Note that the sample800B_1and the sample800B_2are different elements fabricated over the same substrate under the same conditions as those for the sample800B. The sample800C_1, the sample800C_2, and the sample800C_3are different elements fabricated over the same substrate under the same conditions as those for the sample800B.

FIG.45Ashows the measurement results of the fatigue characteristics of the sample800B_1and the sample800B_2.FIG.45Bshows the measurement results of the fatigue characteristics of the sample800C_1and the sample800C_2.FIG.46Bshows the measurement results of the fatigue characteristics of the sample800C_3. InFIG.45A,FIG.45B, andFIG.46B, the horizontal axis represents the number of cycles and the vertical axis represents the polarization P.

Specifically, with application of a one-cycle rectangular wave with a voltage amplitude of 3 V and a frequency of 100 Hz regarded as one cycle, P-E characteristics were measured every predetermined cycles using the triangular wave described in Example 1 to obtain the minimum polarization and the maximum polarization at the time when the electric field intensity was 0.

FIG.45AandFIG.45Bshow the values of the minimum polarization and the maximum polarization at an electric field intensity E of 0 which were obtained every predetermined cycles.

The measurement was stopped after 1×108cycles in the sample800B_1and the sample800C_1. The measurement was kept performed even after 1×108cycles in the sample800B_2and the sample800C_2. Although the shown measurement results of the sample800B_2are up to those of 8.6×1010cycles, the measurement was kept performed thereafter. The sample800C_2was broken after 4.6×109cycles.

Measurement of the sample800C_3was stopped after 1×1010cycles.FIG.46Ashows initial P-E characteristics (a curve821) of the sample800C_3and P-E characteristics after 1×1010cycles (a curve822) thereof. It is found that the sample800B_1, the sample800B_2, the sample800C_1, the sample800C_2, and the sample800C_3have gentle changes in fatigue characteristics as compared withFIG.9(fatigue characteristics described in Non-Patent Document 2). Thus, achievement of tolerance to fatigue after 1×1015cycles or more can be expected.

In this example, hafnium zirconium oxide (HfZrOX) was fabricated as an insulator exhibiting ferroelectricity and measurement results of voltage—polarization characteristics, fatigue characteristics, and the like of the insulator are described.

Since the description of the sample800in Example 1 can be referred to for the appearance and the schematic cross-sectional view of a sample830used for evaluation, the detailed description thereof is omitted.

The sample830was formed with the use of single crystal silicon as the substrate801. Specifically, a 100-nm-thick thermal oxide film was formed as the insulator802on the substrate801, the conductor803(the conductor803aand the conductor803b) functioning as a lower electrode was formed over the insulator802, the insulator804was formed over the conductor803, and the conductor805(the conductor805aand the conductor805b) functioning as an upper electrode was formed over the insulator804.

Furthermore, the insulator806was formed over the conductor803, the insulator804, and the conductor805. The conductor807electrically connected to the conductor803, and the conductor808electrically connected to the conductor805were formed over the insulator806. The conductor807and the conductor808function as electrodes to which measurement signals are input.

Note that formation of the conductor803, the conductor805, the conductor807, and the conductor808, formation of a contact hole provided in the insulator806and the insulator804, and the like were performed by a known photolithography method and a known etching method.

As the sample830, 16 samples (a sample830A to a sample830P) that differ in the formation conditions and thickness of the insulator804, the formation conditions of the conductor805functioning as an upper electrode, and the heat treatment conditions after formation of the upper electrode were fabricated.

Table 2 to Table 5 show the deposition conditions of the conductor803a, the conductor803b, the insulator804, the conductor805a, and the conductor805b, which are provided in each of the sample830A to the sample830P.

Although not shown in Table 2 to Table 5, 200-nm-thick silicon oxynitride was deposited as the insulator806by a PECVD method. Furthermore, a stacked-layer film of three layers of 50-nm-thick Ti, 200-nn-thick Al, and 50-nm-thick Ti was deposited as the conductor807and the conductor808by a sputtering (SP) method.

In the sample830A to the sample830H, the insulator804was deposited by an ALD method using an inorganic precursor. Specifically, in the sample830A to the sample830H, HfCl4(hafnium chloride) and ZrCl4(zirconium chloride) were used as inorganic precursors and H2O (water) was used as an oxidizer.

In the sample830I to the sample830P, the insulator804was deposited by an ALD method using an organic precursor. Specifically, in the sample830I to the sample830P, Hf[N(CH3)2]4(TEMAH: Tetrakis(ethylmethylamino)hafnium) and Zr(Cp)[(N(CH3)2]3(Cyclopentadienyltris(dimethylamino)zirconium) were used as organic precursors and O3(ozone) was used as an oxidizer.

In the sample830A, the sample830E, the sample830I, and the sample830M, the thickness of the insulator804was 4 nm. In the sample830B, the sample830F, the sample830J, and the sample830N, the thickness of the insulator804was 6 nm. In the sample830C, the sample830G, the sample830K, and the sample830O, the thickness of the insulator804was 8 nm. In the sample830D, the sample830H, the sample830L, and the sample830P, the thickness of the insulator804was 10 nm.

In the sample830A to the sample830D and the sample830I to the sample830L, the conductor805awas deposited by a metal CVD (MCVD) method. In the sample830E to the sample830H and the sample830M to the sample830P, the conductor805awas deposited by a sputtering method. In addition, the sample830E to the sample830H and the sample830M to the sample830P were subjected to heat treatment by an RTA method after the sample fabrication. Table 2 to Table 5 also show the heat treatment conditions.

A triangular wave with a voltage amplitude of 3 V and a frequency of 100 Hz was applied between the conductor807and the conductor803, and a change in spontaneous polarization (P-E characteristics) of the insulator804was measured. Since the description in Example 1 can be referred to for the method for obtaining the input voltage waveform and the P-E characteristics, the detailed description thereof is omitted.

FIG.47shows the measurement results of the P-E characteristics of the sample830A to the sample830H.FIG.48shows the measurement results of the P-E characteristics of the sample830I to the sample830P. In each ofFIG.47andFIG.48, the relationship between the electric field intensity E applied to the insulator804and the polarization P is shown for each sample.

A voltage was applied between the conductor807and the conductor803, and a current flowing therebetween (I-V characteristics) was measured.

FIG.49shows the measurement results of the I-V characteristics of the sample830A to the sample830H.FIG.50shows the measurement results of the I-V characteristics of the sample830I to the sample830P. In each ofFIG.49andFIG.50, the relationship between the applied voltage and the flowed current is shown for each sample.

The crystal state of the HfZrOx film corresponding to the insulator804of each of the sample830A to the sample830P was investigated using grazing incident X-ray diffraction (GIXD), which is a kind of XRD analysis method.

FIG.51shows the GIXD measurement results of the sample830A to the sample830H.FIG.52shows the GIXD measurement results of the sample830I to the sample830P. In each ofFIG.51andFIG.52, the relationship between an incidence angle (2θ) of X-ray and detected signal intensity is shown for each sample. In addition, in each ofFIG.51andFIG.52, the peak positions of crystals of HfZrOx are indicated by dashed lines, and the peak position of a monoclinic crystal, the peak position of an orthorhombic crystal, the peak position of a tetragonal crystal, and the peak position of a cubic crystal are indicated by m, o, t, and c, respectively. Note that it is difficult to distinguish an orthorhombic crystal (o), a tetragonal crystal (t), and a cubic crystal (c) from each other by XRD.

The results of the above-mentioned fatigue characteristics measurement performed on the sample830H and the sample830P are described.

With application of a one-cycle rectangular wave with a voltage amplitude of 3 V and a frequency of 100 Hz regarded as one cycle, the fatigue characteristics were measured every predetermined cycles using the above-described triangular wave to obtain the minimum polarization and the maximum polarization at the time when the electric field intensity was 0.

FIG.53shows the measurement results of the fatigue characteristics of the sample830H and the sample830P. Note that the first row ofFIG.53shows the P-E characteristics at the initial stage and at the end of the fatigue characteristics measurement. The second row ofFIG.53shows the measurement results of the fatigue characteristics, with the horizontal axis representing the number of cycles and the vertical axis representing the polarization P. The third row ofFIG.53shows values normalized by the polarization P at the initial stage of the fatigue characteristics measurement.

In this example, hafnium zirconium oxide (HfZrOx) was fabricated as an insulator exhibiting ferroelectricity and evaluation results of frequency dependence of an input voltage (triangular wave) with respect to the voltage—polarization characteristics of the insulator are described.

Since the description of the sample800in Example 1 can be referred to for the appearance and the schematic cross-sectional view of samples used for evaluation, the detailed description thereof is omitted.

The sample was formed with the use of single crystal silicon as the substrate801. Specifically, a 100-nm-thick thermal oxide film was formed as the insulator802on the substrate801, the conductor803(the conductor803aand the conductor803b) functioning as a lower electrode was formed over the insulator802, the insulator804was formed over the conductor803, and the conductor805(the conductor805aand the conductor805b) functioning as an upper electrode was formed over the insulator804.

As the conductor803a,30-nm-thick W was deposited by a sputtering method. As the conductor803b,20-nm-thick TiNx was deposited by a metal CVD (MCVD) method.

As the insulator804, 10-nm-thick hafnium zirconium oxide (HfZrOx) was deposited by an ALD method using an inorganic precursor. Specifically, HfCl4(hafnium chloride) and ZrCl4(zirconium chloride) were used as inorganic precursors and H2O was used as an oxidizer. The substrate temperature at the time of depositing the hafnium zirconium oxide (HfZrOx) was 300° C.

As the conductor805a,10-nm-thick TiNx was deposited by a sputtering (SP) method. As the conductor805b,20-nm-thick W was deposited by a sputtering (SP) method.

Furthermore, the insulator806was formed over the conductor803, the insulator804, and the conductor805. The conductor807electrically connected to the conductor803, and the conductor808electrically connected to the conductor805were formed over the insulator806. The conductor807and the conductor808function as electrodes to which measurement signals are input.

Note that formation of the conductor803, the conductor805, the conductor807, and the conductor808, formation of a contact hole provided in the insulator806and the insulator804, and the like were performed by a known photolithography method and a known etching method.

In addition, heat treatment by an RTA method was performed after the sample fabrication. The heat treatment was performed in a nitrogen atmosphere at 500° C. for 60 sec.

A triangular wave with a voltage amplitude of 3 V and a frequency of 100 Hz was applied between the conductor807and the conductor803, and a change in spontaneous polarization (P-E characteristics) of the insulator804was measured. The evaluation was performed at different triangular wave frequencies: 1 kHz, 100 Hz, and 10 Hz. Since the description in Example 1 can be referred to for the method for obtaining the input voltage waveform and the P-E characteristics, the detailed description thereof is omitted.

FIG.54shows the measurement results of the P-E characteristics. InFIG.54, the relationship between the electric field intensity E applied to the insulator804and the polarization P is shown for each sample. InFIG.54, a solid line831represents data at a frequency of 10 Hz, a dashed line832represents data at 100 Hz, and a dotted line833represents data at 1 kHz.

FIG.55AandFIG.55Bare enlarged views of regions shown by dashed-dotted lines inFIG.54.FIG.55CandFIG.55Dshow the relationship between the polarization P and the triangular wave frequency.FIG.55Cshows the polarization P at the time when the electric field E is 0 MV/cm, andFIG.55Dshows the polarization P at the time when the electric field E is 3 MV/cm (at a voltage of 3 V).

As shown inFIG.54andFIG.55AtoFIG.55D, the polarization P tended to be smaller as the triangular wave frequency was higher.

<Calculation of Influence of Carbon>

In this section, influence of carbon on hafnium zirconium oxide (HfZrOx) was evaluated by calculation.

Here, a calculation model used for the calculation is described.

First, a single crystal model of zirconium oxide having an orthorhombic crystal structure was prepared. Note that the orthorhombic crystal structure belongs to the space group of Pca21(29). In addition, the number of atoms in the single crystal model is 96.

Next, half of zirconium atoms included in the single crystal model was replaced with hafnium atoms. Accordingly, the composition of the single crystal model becomes Hf:Zr:O=1:1:4.

Then, one hafnium atom in the single crystal model was replaced with a carbon atom. The single crystal model was used as a calculation model of first-principles calculation.FIG.56Ashows the calculation model. Note that some atoms are not illustrated for visibility of the diagram.

The atom arrangement was optimized by calculation using the calculation model shown inFIG.56A. For the calculation, the first-principles calculation software VASP (The Vienna Ab initio simulation) was used. The calculation conditions are listed in Table 6.

As a pseudopotential of electronic states, a potential generated by a Projector Augmented Wave (PAW) method was used, and as a functional, GGA/PBE (Generalized-Gradient-Approximation/Perdew-Burke-Emzerhof) was used. Note that the calculation model size (lattice constant and angle between axes) was constant.

FIG.56Bshows the calculation model after calculation for optimizing the atomic arrangement was performed. Note that some atoms are not illustrated for visibility of the diagram.

In the calculation model before the calculation (seeFIG.56A), seven oxygen atoms are coordinated to a hafnium atom before replacement with a carbon atom. Meanwhile, in the calculation model after the calculation (seeFIG.56B), three oxygen atoms (the oxygen atoms in a region surrounded by a dotted line inFIG.56B) were coordinated to the carbon atom. In other words, it was found that the other four oxygen atoms coordinated to the hafnium atom before replacement with the carbon atom (the oxygen atoms in a region surrounded by a dashed-dotted line inFIG.56A) were apart from the carbon atom after the calculation. Specifically, in the calculation model after the calculation, a distance between the carbon atom and each of the oxygen atoms coordinated to the carbon atom was approximately 0.13 nm, and a distance between the carbon atom and each of the four oxygen atoms apart from the carbon atom was greater than or equal to 0.30 nm and less than or equal to 0.35 nm.

The above results indicate that entry of carbon to the hafnium zirconium oxide breaks the structure of the hafnium zirconium oxide and makes it difficult to form an orthorhombic crystal structure.

The oxygen atoms coordinated to the carbon atom after the calculation (the oxygen atoms in the region surrounded by the dotted line inFIG.56B) are oxygen atoms not having inversion symmetry, that is, causing ferroelectricity. When the oxygen atoms are strongly bound by the carbon atom, there might be influence of displacement by electric field.

The oxygen atoms apart from the carbon atom after the calculation (the oxygen atoms in the region surrounded by the dashed-dotted line inFIG.56B) have a small number of bonds with a hafnium atom or a zirconium atom compared with the case of a single crystal model of hafnium zirconium oxide. It is thus presumed that the oxygen atoms are likely to form vacancies.

The above results indicate the possibility that entry of carbon to the hafnium zirconium oxide adversely affect ferroelectricity. In other words, it is indicated that in order to make the hafnium zirconium oxide exhibit ferroelectricity, the carbon concentration in the hafnium zirconium oxide is preferably low.

In this example, results of fatigue characteristics measurement performed on the sample800B described in Example 1 are described.

FIG.57Ashows the measurement system of the retention measurement.FIG.57Bshows the operation sequence of the retention measurement.FIG.58A,FIG.58B, andFIG.58Cshow the results of the retention measurement.

As shown inFIG.57A, the measurement system of the retention measurement includes at least a pulse generator and an ammeter. The measurement was performed at room temperature.

In the retention measurement, a potential is supplied to a sample using the pulse generator and a current flowing at that time is measured. The operation sequence of the retention measurement shown inFIG.57Bis described. In Period Ti, a negative potential is supplied to the sample to cause a polarization state on the negative potential side. After Period T2with a potential of 0 V, a positive potential pulse (a rectangular wave of 3 V for 5 sec) is supplied twice in Period T3to cause the polarization state on the negative potential side. Here, the pulse is supplied twice in Period T3to cancel constant leakage. Then, after Period T4with a potential of 0 V for approximately 10 seconds, a positive potential pulse similar to that in Period T3is supplied twice in Period T5. Note that Period T4is short and polarization of the sample is retained, and thus a current due to change in polarization does not flow in Period T5, but a current due to leakage flows. Next, in Period T6, for the retention measurement, retention at a potential of 0 V is performed under two retention period conditions, 10 seconds and 10 hours. Then, in Period T7, a positive potential pulse similar to that in Period T3and Period T5is supplied twice, and a current flowing in the sample is compared. In the case where a current flowing in Period T7is larger than a current flowing in Period T5, it is highly possible that the amount of polarization is reduced in Period T6. Meanwhile, in the case where a current flowing in Period T5and a current flowing in Period T7are substantially equal to each other or in the case where a current flowing in Period T7is smaller than a current flowing in Period T5, it is considered that polarization is retained in Period T6.

As the results of the retention measurement performed on the sample800B,FIG.58Ashows current change in Period T5andFIG.58Bshows current change in Period T7after 10-minute retention in Period T6.FIG.58Cshows current change in Period T7after 10-hour retention in Period T6. WhenFIG.58A,FIG.58B, andFIG.58Care compared, a current does not increase in Period T7even after 10-hour retention, which indicates that the sample800B can retain the polarization state at least for 10 hours.

In this example, an element having a structure of 1Tr1C (one transistor and one capacitor) was fabricated, and the measurement results of the electrical characteristics are described below.

Since the method for obtaining the P-V characteristics are described in Example 1, the details thereof are omitted here. A triangular wave with a voltage amplitude of 3 V and a frequency of 100 Hz was applied between a pair of electrodes of the one capacitor, and change in spontaneous polarization of an insulator or a dielectric (P-V characteristics) was measured. The horizontal axis represents the input voltage V that is a triangular wave, and the vertical axis represents a value obtained by converting the output current I into the polarization P with the use of Formula (1).

The transistor can be fabricated by a fabrication method described in Embodiment 2, and there is no particular limitation on the transistor structure. The transistor200illustrated inFIG.20A, specifically a structure where the planar capacitor100is provided over the insulator285was used, and the measurement results of the P-V characteristics of a comparative example, CVD-TiN, and SP-TiN are shown inFIG.59A.FIG.59Bshows the measurement results of the I-V characteristics.

Note that 300 electrodes each having a size of 1.265 μm×1.05 μm are arranged in parallel, so that the total size is 398.5 μm2.

In the comparative example, a stack of a tungsten film obtained by a sputtering method (substrate temperature 130° C., thickness: 30 nm) and a titanium nitride film obtained by a metal CVD method (substrate temperature 400° C., thickness: 10 nm) is used as an lower electrode; a stack of an aluminum oxide film obtained by an ALD method (substrate temperature 250° C., film thickness: 14 nm) and a silicon oxynitride film obtained by a PECVD method (substrate temperature 350° C., thickness: 7 nm) is placed over the lower electrode; and a stack of a titanium nitride film obtained by a metal CVD method (substrate temperature 400° C., thickness: 10 nm) and a tungsten film obtained by a sputtering method (substrate temperature 130° C., thickness: 20 nm) is placed thereover as an upper electrode.

The sample denoted by CVD-TiN is different from the comparative example in a film interposed between the lower electrode and the upper electrode, and uses a 10-nm-thick HfZrOx film. The deposition conditions of the HfZrOx film are the same as those of the insulator804in Example 1; an ALD method is used, a chloride-based precursor is used, the substrate temperature is 300° C., and H2O is used as an oxidizer. A remanent polarization amount Pr per unit area of the sample denoted by CVD-TiN is approximately 12.1.

In the sample denoted by SP-TiN, a film interposed between the lower electrode and the upper electrode is a 10-nm-thick HfZrOx film, and a stack of a titanium nitride film obtained by a sputtering method and a tungsten film obtained by a sputtering method (thickness: 20 nm) is placed thereover. As the deposition conditions of the titanium nitride film obtained by a sputtering method, the substrate temperature is set to room temperature. The remanent polarization amount Pr per unit area of the sample denoted by SP-TiN is approximately 12.8.

FIG.60AandFIG.60Bshow the measurement results of the ID-VGcharacteristics of transistors used in the samples of the comparative example, CVD-TiN, and SP-TiN. InFIG.60AandFIG.60B, the horizontal axis represents a top gate potential VG[V], the first vertical axis represents a drain current ID[A], and the second vertical axis represents field-effect mobility μFE [cm2/Vs] at VD=0.1 V. The drain current at VD=0.1 V is shown by a thin solid line, the drain current at VD=1.2 V is shown by a thick dashed line, and the field-effect mobility at VD=0.1 V is shown by a thin dotted line.

The shift voltage Vsh of each of the transistors was calculated from the above ID-VGmeasurement results, and the standard deviation a (Vsh) was calculated. Here, the shift voltage Vsh is defined as, in the ID-VGcurve of the transistor, VGat which the tangent at a point where the slope of the curve is the steepest intersects the straight line of ID=1 pA. The obtained standard deviation σ (Vsh) of the sample of SP-TiN inFIG.60Awas a favorable value, 64 mV. The field effect mobility μFE of the sample of SP-TiN inFIG.60Awas 14 cm2/Vs.

A shift voltage (Vsh) and a subthreshold swing value (S value) of the transistor were calculated from the obtained ID-VGcurve. The shift voltage (Vsh) is defined as, in the ID-VGcurve of the transistor, VGat which the tangent at a point where the slope of the curve is the steepest intersects the straight line of ID=1 pA. The S value of the sample of SP-TiN inFIG.60Awas 107 mV/dec.

FIG.60Bshows the electrical characteristics of one transistor in a measurement circuit in which 1Tr1C (one transistor and one capacitor) elements are arranged at a density of 8.4/μm2. Note thatFIG.60Ashows the electrical characteristics of one transistor of the case where the arrangement layout of the measurement circuit is different from that inFIG.60B.

In this example, an element having a structure of 3Tr1C (three transistors and one capacitor) was fabricated, writing operation and reading operation were performed, and the measurement results of the electrical characteristics are described below.

InFIG.61A, a transistor OS1is electrically connected to a gate line WWL, a signal line WBL, and a node SN. A gate of a transistor OS2is electrically connected to the node SN and connected to a source line SL. A transistor OS3is electrically connected to a gate line RWL and a signal line RBL. A drain electrode (or source electrode) of the transistor OS2and a source electrode (or drain electrode) of the transistor OS3are electrically connected to each other. Note that a back gate potential BG1of the transistor OS1and a back gate potential BG2of the transistor OS2and the transistor OS3are each a fixed potential, specifically 0 V.

FIG.61Aillustrates an example where a capacitor MFM is used as 1C. The capacitor MFM has a structure where a lower electrode, a 10-nm-thick HfZrOx film, and an upper electrode are stacked. The area of the capacitor MFM is 0.25 μm2. The capacitor MFM is electrically connected to the node SN and a signal line C.

The lower electrode is a stack of a tungsten film obtained by a sputtering method (substrate temperature 130° C., thickness: 30 nm) and a titanium nitride film obtained by a metal CVD method (substrate temperature 400° C., thickness: 10 nm), and the upper electrode is a stack of a titanium nitride film obtained by a metal CVD method (substrate temperature 400° C., thickness: 10 nm) and a tungsten film obtained by a sputtering method (substrate temperature 130° C., thickness: 20 nm).

Note that the fabrication process of the transistor and the capacitor is the same as that for the sample denoted by CVD-TiN described in Example 7.

Next, measurement for determining the direction of remnant polarization of the capacitor MFM as a current difference in a reading transistor (the transistor OS3) was performed.

FIG.62Ashows an example of a timing chart of the measurement. Reference symbols WWL, WBL, C, RWL, SN, RBL, and the like in the timing chart denote the wirings supplied with the potentials shown in the timing chart. Although not shown in the timing chart, the source line SL is supplied with a predetermined potential (constant potential).

First, writing and reading to and from the capacitor MFM are described with reference to FIG.62B1and FIG.62B2. Note that an equivalent circuit shown in FIG.62B1is the same as that inFIG.61A; however, denotation of BG1and BG2is omitted because BG1and BG2are 0 V.

First, the potential of the gate line WWL is set to a potential that brings the transistor OS1into an on state, so that the transistor OS1is brought into an on state. Accordingly, the potential of the signal line WBL is supplied to the gate electrode of the transistor OS2. A voltage of 3 V is applied to the signal line C in 10 ms while the transistor OS1is in an on state. The period in which 3 V is applied to the capacitor MFM is referred to as a Pr+set period. A predetermined electric charge is supplied to the gate electrode of the transistor OS2; as shown in the timing chart inFIG.62A, the potential of the signal line WBL is always 0 V in this measurement method. Then, as shown in the right half of FIG.62B2, a direction of a positive remanent polarization (Pr+) is given to the capacitor MFM (first writing). Note that the arrows shown in the right half of FIG.62B2correspond to the arrows in the Pr+set period inFIG.62A.

After that, the potential of the gate line WWL is set to a potential that brings the transistor OS1into an off state, so that the transistor OS1is brought into an off state.

In order to obtain a function as a memory cell, the gate line RWL corresponds to a read word line, the gate line WWL corresponds to a write word line, the signal line WBL corresponds to a write bit line, and the signal line RBL corresponds to a read bit line. In the case where the transistor OS1is in an off state and a potential that is not 0 V is supplied by the signal line WBL, the electric charge supplied to the gate electrode of the transistor OS2can be retained (retention). In the case where a potential is supplied to the signal line WBL, the off-state current of the transistor OS1is extremely small and thus the electric charge in the gate electrode of the transistor OS2is retained for a long time.

The transistor OS3is in an off state during the above writing operation.

Next, the transistor OS1is brought into an off state to set the node SN at a floating potential, and the transistor OS3is brought into an on state and the signal line C is swept from 0 V to 3 V (potential sweeping) to measure a current value IRBLof the signal line RBL;FIG.63Ashows the electrical characteristics (Pr+) at that time by solid lines with the vertical axis representing the current value IRBLand the horizontal axis representing a voltage Vc of the signal line C.

Next, the potential of the gate line WWL is set to a potential that brings the transistor OS1into an on state, and −3 V is applied to the signal line C in 10 ms while the transistor OS1is in an on state. The period in which −3 V is applied to the capacitor MFM is referred to as a Pr-set period. That is, a predetermined electric charge is supplied to the gate electrode of the transistor OS2, and a direction of a negative remanent polarization (Pr−) is given to the capacitor MFM as shown in the left half of FIG.62B2(second writing). Note that arrows shown in the left half of FIG.62B2correspond to the arrows in the Pr-set period inFIG.62A.

The transistor OS3is in an off state during the above writing operation.

Next, as shown in FIG.62C1, the transistor OS1is brought into an off state to set the node SN at a floating potential, and the transistor OS3is brought into an on state and the signal line C is swept from 0 V to 3 V to measure the current value IRBLof the signal line RBL;FIG.63Ashows the electrical characteristics (Pr−) at that time by a dotted line with the vertical axis representing the current value IRBLand the horizontal axis representing the voltage Vc of the signal line C. Note that an equivalent circuit shown in FIG.62C1is the same as that inFIG.61A; however, denotation of BG1and BG2is omitted because BG1and BG2are 0 V.

InFIG.63A, 20 times of sweep after 3 V application to the capacitor MFM and 20 times of sweep after −3 V application to the capacitor MFM, 40 times of sweep in total, are superimposed.

A current difference is generated between the current value IRBLread after 3 V application to the signal line C and the current value IRBLread after −3 V application to the signal line C. The direction of the positive remanent polarization in the capacitor MFM shown in FIG.62C2and the direction of the negative remanent polarization in the capacitor MFM shown in FIG.62C2can be regarded as the current difference in the reading transistor (the transistor OS3). Thus, from the measurement results shown inFIG.63A, the direction of remanent polarization in the capacitor MFM can be determined as the current difference in the reading transistor (the transistor OS3).

Since the leak current of the transistor OS1in an off state is extremely low in the element structure of 3Tr1C illustrated inFIG.61A, information can be written, retained, and read by taking advantage of the feature that the potential of the node SN can be retained.

Although one memory cell with only one element structure is illustrated here, it is also possible to form a memory cell array including a plurality of memory cells arranged inn (rows) x m (columns).

FIG.63Bshows the results obtained by using the same measurement method as the above and the same element structure as the comparative example in Example 7. In the comparative example, the measurement results of two times of sweep after 3 V application to the capacitor MFM and two times of sweep after −3 V application to the capacitor MFM, four times of sweep in total, are superimposed. The electrical characteristics (Pr+) are denoted by solid lines, and the electrical characteristics (Pr−) are denoted by dotted lines inFIG.63A.

A comparative example employs the same process as the comparative example described in Example 7. A stack of a tungsten film obtained by a sputtering method (substrate temperature 130° C., thickness: 30 nm) and a titanium nitride film obtained by a metal CVD method (substrate temperature 400° C., thickness: 10 nm) is used as the lower electrode; a stack of an aluminum oxide film obtained by an ALD method (substrate temperature 250° C., thickness: 14 nm) and a silicon oxynitride film obtained by a PECVD method (substrate temperature 350° C., thickness: 7 nm) is placed over the lower electrode; and a stack of a titanium nitride film obtained by a metal CVD method (substrate temperature 400° C., thickness: 10 nm) and a tungsten film obtained by a sputtering method (substrate temperature 130° C., thickness: 20 nm) is placed thereover as the upper electrode.

As shown inFIG.63B, no current difference was observed in the comparative example.

In this example, results of measurement of f characteristics performed using a sample fabricated in a manner similar to that in Example 7 are described.

The sample subjected to the f characteristics measurement has a structure of the capacitor100illustrated inFIG.20;300elements each having an electrode size of 1.265 μm×1.05 μm are connected through wiring layers, and the total area A is 398.5 μm2.

FIG.64Ashows the measurement system of the f characteristics.FIG.64Bshows the operation sequence of the f characteristics measurement.FIG.64CandFIG.64Dare diagrams showing assumed change in polarization.FIG.65shows the results of the retention measurement.

As shown inFIG.64A, the measurement system of the f characteristics includes at least a pulse generator and an ammeter. The measurement was performed at room temperature. In this example, DG2020A manufactured by TEKTRONIX Inc. was used as the pulse generator and a semiconductor parameter analyzer B1500A manufactured by KEYSIGHT was used as the ammeter.

In the f characteristics measurement, a potential is supplied to the sample with the use of the pulse generator, and a current flowing at that time is measured. The operation sequence of the f characteristics measurement shown inFIG.64Bis described. In Period T1, a negative potential pulse is supplied to the sample to cause a polarization state on the negative potential side. Next, after Period T2with a potential of 0 V, a positive potential pulse is supplied in Period T3to measure a current flowing at that time. Here, the pulse width (time) of the positive potential supplied in Period T3is measured under a plurality of conditions, whereby time needed for inverting polarization can be evaluated. The time needed for inverting polarization is preferably shorter because a storage element can perform higher-speed rewriting and power consumption can be lower. In this example, the measurement was performed employing a plurality of conditions as the conditions in Period T3: the pulse width of a rectangular wave of a positive potential was swept from 1 sec to 5 nsec. When the rectangular wave pulse is regarded as a half period, the condition of 1 sec and the condition of 5 nsec can be referred to as 0.5 Hz and 100 MHz, respectively. Next, after Period T4with a potential of 0 V, a positive potential pulse with a sufficient length is supplied in Period T5to measure a current flowing in the sample. The sufficient length here means the time until the value change in the current flowing in the sample substantially disappears, and is 1 sec in this example. Subsequently, in Period T6, a positive potential pulse similar to that in Period T5is supplied to measure a current flowing in the sample. Here, a difference ΔC between the amount of electric charge flowing in Period T5and the amount of electric charge flowing in Period T6is obtained, whereby the amount of electric charge derived from polarization inversion in Period T5and the amount of electric charge derived from another factor such as a leakage component can be distinguished from each other. By dividing the difference ΔC by the area A, ΔPr that is an indicator of polarization can be obtained. Here, the area A is an area where two electrodes of the capacitor overlap with each other. By graphing the value of ΔPr obtained by measurement data analysis and the pulse width (time) of Period T3, the length of period needed for inverting polarization can be known. Although not used in the measurement data analysis in this example, measurement of Period T7and/or Period T8may be performed after Period T6to improve the measurement accuracy of the difference ΔC. The specific conditions of the operation sequence of the f characteristics measurement are shown in Table 7.

The case where polarization can be inverted and the case where polarization cannot be inverted in the f characteristics measurement are described with reference toFIG.64B,FIG.64C, andFIG.64D.FIG.64Cis a diagram showing assumed change in polarization from Period T1to Period T5of the case where polarization can be inverted in Period T3, and shows a positive polarization state in Period T4as denoted by P4a.FIG.64Dis a diagram showing assumed change in polarization from Period T1to Period T5of the case where polarization cannot be inverted in Period T3, and shows a state where polarization fails to be inverted into a positive polarization state in Period T4as denoted by P4b. Whether polarization is inverted or not in Period T3can be determined by the amount of electric charge flowing in Period T5; the amount of electric charge flowing in Period T5is small when polarization can be retained and the amount of electric charge flowing in Period T5is large when polarization cannot be retained.

FIG.65shows the measurement results the f characteristics. Measurement was performed employing four conditions as the conditions of Period T3: 1 sec (0.5 Hz), 100 nsec (5 MHz), 10 nsec (50 MHz), and 5 nsec (100 MHz). As for 1 sec (0.5 Hz), measurement results of N=2 are shown. In addition, the measurement results of the case where writing was not performed in Period T3are also shown. In each measurement, as compared with the case where writing was not performed, the value of ΔPr was small enough to determine that polarization was inverted in writing in Period T3. The results suggest that the sample of this example can perform writing operation at 100 MHz at the lowest.

In this example, results of retention measurement performed on the sample800B described in Example 1 are described.

In this example, measurement was performed by a method different from that of the retention measurement described in Example 6.FIG.66Ashows the measurement system of the retention measurement.FIG.66Bshows the operation sequence of the retention measurement.FIG.66CandFIG.66Dare diagrams showing assumed change in polarization.FIG.67Ashows the results of the retention measurement.

As shown inFIG.66A, the measurement system of the retention measurement includes at least a pulse generator and an ammeter. The measurement was performed at room temperature. In this example, M9185B manufactured by KEYSIGHT was used as the pulse generator and a semiconductor parameter analyzer B1500A manufactured by KEYSIGHT was used as the ammeter. In this example, a prover provided with a stage having a temperature adjustment function was used to perform the retention measurement under a plurality of temperature conditions.

In the retention measurement, a potential is supplied to a sample with the use of the pulse generator, and a current flowing at that time is measured. The operation sequence of the retention measurement shown inFIG.66Bis described. In Period T1, a negative potential pulse is supplied to the sample to cause the polarization state on the negative potential side. Next, in Period T2, retention at a potential of 0 V is performed for a later-described period to perform retention measurement. Then, in Period T3, a positive potential pulse is supplied to measure a current flowing in the sample. Next, in Period T4, a positive potential pulse similar to that in Period T3is supplied to measure a current flowing in the sample. Here, the difference ΔC between the amount of electric charge flowing in Period T3and the amount of electric charge flowing in Period T4is obtained, whereby the amount of electric charge derived from polarization inversion in Period T3and the amount of electric charge derived from another factor such as leakage component can be distinguished from each other. By dividing the difference ΔC by the area A, ΔPr that is an indicator of polarization can be obtained. Here, the area A is an area where two electrodes of the capacitor overlap with each other. By graphing the value of ΔPr obtained by measurement data analysis and the length of the retention time of Period T2, the length of a period needed for inverting polarization can be known. Although not used in the measurement data analysis in this example, measurement of Period T5and/or Period T6may be performed after Period T4to improve the measurement accuracy of the difference ΔC. The specific conditions of the operation sequence of the f characteristics measurement are shown in Table 8.

The case where polarization can be retained and the case where polarization cannot be retained in the f characteristics measurement are described with reference toFIG.66B,FIG.66CandFIG.66D.FIG.66Cis a diagram showing assumed change in polarization from Period T1to Period T3of the case where polarization can be retained in Period T2, and polarization is retained even at the end of Period T2as shown by P2a.FIG.66Dis a diagram showing assumed change in polarization from Period T1to Period T3of the case where polarization cannot be retained in Period T2, and the amount of polarization is reduced at the end of Period T2as shown by P2b. Whether polarization is retained or not in Period T2can be determined by the amount of electric charge flowing in Period T3; the amount of electric charge flowing in Period T3is small when polarization can be retained and the amount of electric charge flowing in Period T3is large when polarization cannot be retained.

FIG.67shows the results of the retention measurement performed on the sample800B. The temperature conditions are the following three conditions: 85° C., 150° C., and 200° C. Measurement was performed employing, as the conditions of Period T2, five conditions of 1 sec, sec, 100 sec, 1000 sec, and 259200 sec (3 days) at 85° C. and four conditions of 1 sec, 10 sec, 100 sec, and 1000 sec at 150° C. and 200° C. In each measurement, the value of ΔPr allowed determining that polarization was retained.

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