SOLID-STATE IMAGING DEVICE

A voltage drop of a floating diffusion capacitor is suppressed. A solid-state imaging device includes a floating diffusion that accumulates charge generated by photoelectric conversion according to an amount of received light of a pixel, a comparison circuit that compares a voltage corresponding to accumulated charge of the floating diffusion with a reference voltage, and a boosting unit that raises a potential on one end side of the floating diffusion during photoelectric conversion.

TECHNICAL FIELD

Embodiments according to the present disclosure relate to a solid-state imaging device.

BACKGROUND ART

As a solid-state imaging device, for example, there is a complementary MOS (CMOS) image sensor that reads out photocharge accumulated in a pn junction capacitor of a photodiode that is a photoelectric conversion element via a metal oxide semiconductor (MOS) transistor. In the CMOS image sensor, for example, a read operation of the photocharge accumulated in the photodiode is executed for each pixel or each row, or the like. Thus, an exposure period during which the photocharge is accumulated cannot be matched in all pixels, and a distortion occurs at the time of imaging in a case where the subject is moving, or the like. As a method of suppressing this distortion, it is known that an analog-to-digital converter is arranged for each pixel, and respective analog signals exposed simultaneously in all pixels are digitally converted immediately.

Furthermore, in order to downsize the imaging device and improve the aperture ratio of pixels, an imaging device in which a pixel substrate on which pixels are arranged and a logic substrate (logic circuit substrate) on which a peripheral circuit is arranged are stacked is used. For example, there has been proposed an imaging device in which a pixel substrate on which pixels are arranged in a two-dimensional lattice pattern and which outputs an analog image signal and a logic substrate which processes the output analog image signal are stacked (see Patent Document 1).

CITATION LIST

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

However, in the above-described technology, the analog-to-digital converters are arranged in a two-dimensional lattice pattern on the logic substrate, and the analog image signal output from the pixel substrate is input to the analog-to-digital converters of the logic substrate. In this case, a voltage VDD supplied from the logic substrate passes through a comparator of the analog-to-digital converter, so that a voltage drop occurs. When the voltage drop occurs, the voltage input to a floating diffusion capacitor decreases, which causes noise due to the voltage relationship between the floating diffusion capacitor and the transfer transistor.

Therefore, the present disclosure provides a solid-state imaging device capable of suppressing a voltage drop of the floating diffusion capacitor.

Solutions to Problems

In order to solve the above-described problem, according to the present disclosure,there is provided a solid-state imaging device including:a floating diffusion that accumulates charge generated by photoelectric conversion according to an amount of received light of a pixel;a comparison circuit that compares a voltage corresponding to accumulated charge of the floating diffusion with a reference voltage; anda boosting unit that raises a potential on one end side of the floating diffusion during photoelectric conversion.

The boosting unit may include a first transistor that controls a current flowing through the comparison circuit in such a manner that a potential on one end side of the floating diffusion becomes high.

A current source that generates a current flowing through the comparison circuit may be further included, in whichthe first transistor may control a current generated by the current source.

A second transistor cascode-connected to the first transistor may be further included, in whichthe current source may control a current flowing through the comparison circuit according to a current flowing through the second transistor.

A current flowing through the second transistor may be controlled by a gate voltage of the first transistor.

The current source may include a third transistor that causes a current to flow in the comparison circuit, anda gate of the third transistor may be connected to a gate of the second transistor.

A gate voltage of the third transistor may be raised when the first transistor is turned on.

A gate of the third transistor may be capacitively coupled to the floating diffusion.

There may be further included:a first chip on which a pixel circuit having the floating diffusion is arranged; anda second chip stacked on the first chip and in which at least a part of the boosting unit including the first transistor is arranged.

The current source may include a third transistor that causes a current to flow in the comparison circuit, andthe first transistor may be cascode-connected to the third transistor.

The comparison circuit may include a differential transistor pair that outputs a signal corresponding to a differential voltage between a voltage corresponding to the accumulated charge of the floating diffusion and the reference voltage, andthe first transistor may be connected between the differential transistor pair and the third transistor.

The comparison circuit may include a differential transistor pair that outputs a signal corresponding to a differential voltage between a voltage corresponding to the accumulated charge of the floating diffusion and the reference voltage, andthe third transistor may be connected between the differential transistor pair and the first transistor.

The first transistor and the third transistor may be shared by a plurality of pixels each having the floating diffusion.

The first transistor and the third transistor may be arranged in a chip on which a pixel circuit having the floating diffusion is arranged.

The first transistor and the third transistor may be arranged in a pixel region of one pixel among the plurality of pixels.

The boosting unit may raise a potential on one end side of the floating diffusion using capacitive coupling.

A current source that generates a current flowing through the comparison circuit may be further included, in whichthe boosting unit may raise a potential on one end side of the floating diffusion by capacitive coupling between a gate wiring of a transistor constituting the current source and the floating diffusion.

There may be further included:a time code generator that generates a time code;a time code transfer unit that transfers the time code generated by the time code generator;a reference voltage generator that generates the reference voltage whose voltage level changes according to time; anda time code holding unit that is provided for each pixel and holds the time code when the voltage corresponding to the accumulated charge of the floating diffusion and the reference voltage match as a digital signal corresponding to the amount of received light.

The time code generator, the time code transfer unit, the reference voltage generator, and the time code holding unit may be arranged on a chip different from a chip on which a pixel circuit having the floating diffusion is arranged.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of a solid-state imaging device will be described with reference to the drawings. Although main components of the solid-state imaging device will be mainly described below, the solid-state imaging device may have components and functions that are not illustrated or described. The following description does not exclude components and functions that are not illustrated or described.

The drawings are schematic or conceptual, and the ratio of each portion and the like are not necessarily the same as actual ones. In the description and the drawings, elements similar to those described above with respect to previously described drawings are denoted by the same reference numerals, and detailed descriptions thereof are appropriately omitted.

<Schematic Configuration Example of Solid-State Imaging Device>

FIG.1illustrates a schematic configuration of a solid-state imaging device according to the present disclosure.

The solid-state imaging device1ofFIG.1includes a pixel array unit22in which pixels21are arranged in a two-dimensional array on a semiconductor substrate11using, for example, silicon (Si) as a semiconductor. The pixel array unit22is also provided with time code transfer units23that each transfer the time code generated by a time code generation unit26to each pixel21. Then, a pixel drive circuit24, a D/A converter (DAC)25, the time code generation unit26, a vertical drive circuit27, an output unit28, and a timing generation circuit29are formed around the pixel array unit22on the semiconductor substrate11.

As will be described later with reference toFIG.2, each of the pixels21arranged in a two-dimensional array is provided with a pixel circuit41and an ADC42, and the pixel21generates a charge signal corresponding to the amount of light received by a light receiving element (for example, a photodiode) in the pixel, converts the charge signal into a digital pixel signal SIG, and outputs the digital pixel signal SIG.

The pixel drive circuit24drives the pixel circuit41(FIG.2) in the pixel21. The DAC25generates a reference signal (reference voltage signal) REF, which is a slope signal whose level (voltage) monotonously decreases with the lapse of time, and supplies the reference signal REF to each pixel21. The time code generation unit26generates a time code used when each pixel21converts an analog pixel signal SIG into a digital signal (AD conversion), and supplies the time code to the corresponding time code transfer unit23. A plurality of time code generation units26is provided for the pixel array unit22, and in the pixel array unit22, the time code transfer units23are provided as many as the number of time code generation units26. That is, the time code generation units26and the time code transfer units23that transfer the time code generated therein correspond to each other on a one-to-one basis.

The vertical drive circuit27performs control to cause the output unit28to output the digital pixel signal SIG generated in the pixel21in a predetermined order on the basis of a timing signal supplied from the timing generation circuit29. The digital pixel signal SIG output from the pixel21is output from the output unit28to the outside of the solid-state imaging device1. The output unit28performs predetermined digital signal processing such as black level correction processing for correcting a black level and correlated double sampling (CDS) processing as necessary, and thereafter performs output to the outside.

The timing generation circuit29includes a timing generator that generates various timing signals and the like, and supplies the generated various timing signals to the pixel drive circuit24, the DAC25, the vertical drive circuit27, and the like.

The solid-state imaging device1is configured as described above. Note that, inFIG.1, as described above, it has been described that all the circuits constituting the solid-state imaging device1are formed on one semiconductor substrate11, but as will be described later, the circuits constituting the solid-state imaging device1may be divided and arranged on a plurality of semiconductor substrates11.

<Detailed Configuration Example of Pixel>

FIG.2is a block diagram illustrating a detailed configuration example of the pixel21.

The pixel21includes the pixel circuit41and the AD converter (ADC)42.

The pixel circuit41outputs a charge signal corresponding to the amount of received light to the ADC42as the analog pixel signal SIG. The ADC42converts the analog pixel signal SIG supplied from the pixel circuit41into a digital signal.

The ADC42includes a comparison circuit51and a data storage unit52.

The comparison circuit51compares the reference signal REF supplied from the DAC25with the pixel signal SIG, and outputs an output signal VCO as a comparison result signal indicating a comparison result. The comparison circuit51inverts the output signal VCO when the reference signal REF and the pixel signal SIG become the same (the same voltage).

The comparison circuit51includes a differential input circuit61and a voltage conversion circuit62, which will be described later in detail with reference toFIG.3.

In addition to the input of the output signal VCO from the comparison circuit51to the data storage unit52, from the vertical drive circuit27, a WR signal indicating that it is a pixel signal write operation, an RD signal indicating that it is a pixel signal read operation, and a WORD signal for controlling a read timing of the pixel21during the pixel signal read operation are supplied from the vertical drive circuit27. Furthermore, the time code generated by the time code generation unit26is also supplied via the time code transfer unit23.

The data storage unit52includes a latch control circuit71that controls a write operation and a read operation of the time code on the basis of the WR signal and the RD signal, and a latch storage unit72that stores the time code.

In the write operation of the time code, the latch control circuit71stores the time code, which is supplied from the time code transfer unit23and updated every unit time, in the latch storage unit72while a Hi (High) output signal VCO is input from the comparison circuit51. Then, when the reference signal REF and the pixel signal SIG become the same (voltage thereof) and the output signal VCO supplied from the comparison circuit51is inverted to Lo (Low), writing (updating) of the supplied time code is stopped, and the time code finally stored in the latch storage unit72is held in the latch storage unit72. The time code stored in the latch storage unit72indicates a time at which the pixel signal SIG and the reference signal REF become equal, and represents data indicating that the pixel signal SIG has been the reference voltage at that time, that is, a digitized light amount value.

After a sweep of the reference signal REF is completed and the time codes are stored in the latch storage units72of all the pixels21in the pixel array unit22, the operation of the pixels21is changed from the write operation to the read operation.

In the time code read operation, the latch control circuit71outputs the time code (digital pixel signal SIG) stored in the latch storage unit72to the time code transfer unit23when the pixel21reaches its own read timing on the basis of the WORD signal for controlling the read timing. The time code transfer unit23sequentially transfers the supplied time code in the column direction (vertical direction) and supplies the time code to the output unit28.

Hereinafter, in order to distinguish from the time code written in the latch storage unit72in the write operation of the time code, digitized pixel data indicating that the pixel signal SIG has been the reference voltage at that time, which is inverted time code when the output signal VCO read from the latch storage unit72in the time code read operation is inverted, is also referred to as AD converted pixel data.

<Configuration Example of Comparison Circuit>

FIG.3is a circuit diagram illustrating detailed configurations of the differential input circuit61and the voltage conversion circuit62constituting the comparison circuit51.

The differential input circuit61compares the pixel signal SIG output from the pixel circuit41in the pixel21with the reference signal REF output from the DAC25, and outputs a predetermined signal (current) when the pixel signal SIG is higher than the reference signal REF.

The differential input circuit61includes transistors81and82forming a differential pair, transistors83and84constituting a current mirror, a transistor85as a constant current source that supplies a current IB according to an input bias current VB, and a transistor86that outputs an output signal HVO of the differential input circuit61.

In the transistors81and82forming a differential pair, the reference signal REF output from the DAC25is input to a gate of the transistor81, and the pixel signal SIG output from the pixel circuit41in the pixel21is input to a gate of the transistor82. Sources of the transistors81and82are connected to a drain of the transistor85, and a source of the transistor85is connected to a predetermined voltage VSS (VSS<VDD).

A drain of the transistor81is connected to gates of the transistors83and84and a drain of the transistor83constituting the current mirror circuit, and a drain of the transistor82is connected to a drain of the transistor84and a gate of the transistor86. Sources of the transistors83,84, and86are connected to a first power supply voltage VDD.

The transistors81to86constituting the differential input circuit61are circuits operating at high voltages up to the first power supply voltage VDD.

The voltage conversion circuit62adjusts a level difference between an analog region and a digital region. The voltage conversion circuit62converts the output signal HVO input from the differential input circuit61into an output signal VCO with an adjusted level difference, and outputs the output signal VCO to the data storage unit52. The output signal VCO is a voltage corresponding to the gradation.

<Detailed Configuration Example of Pixel Circuit>

A detailed configuration of the pixel circuit41will be described with reference toFIG.4.

FIG.4is a circuit diagram in which details of the pixel circuit41are added to the comparison circuit51illustrated inFIG.3.

The pixel circuit41includes a photodiode (PD)121as a photoelectric conversion element, a discharge transistor122, a transfer transistor123, a reset transistor124, and a floating diffusion layer (FD)125.

The discharge transistor122is used in a case of adjusting the exposure period. Specifically, if the discharge transistor122is turned on when it is desired to start the exposure period at an arbitrary timing, charge accumulated in the photodiode121until then are discharged, and thus the exposure period is started after the discharge transistor122is turned off.

The transfer transistor123transfers the charge generated by the photodiode121to the FD125. The reset transistor124resets the charge held in the FD125. The FD125is connected to the gate of the transistor82of the differential input circuit61. Thus, the transistor82of the differential input circuit61also functions as an amplification transistor of the pixel circuit41.

A source of the reset transistor124is connected to the gate of the transistor82of the differential input circuit61and the FD125, and a drain of the reset transistor124is connected to the drain of the transistor82. Therefore, there is no fixed reset voltage for resetting the charge of the FD125. This is because the reset voltage for resetting the FD125can be arbitrarily set using the reference signal REF by controlling the circuit state of the differential input circuit61.

In the above description, it has been described that the solid-state imaging device1is formed on one semiconductor substrate11, but the solid-state imaging device1may be configured by separately forming circuits on a plurality of semiconductor substrates11.

FIG.5illustrates a conceptual diagram of forming the solid-state imaging device1by stacking two semiconductor substrates11of an upper substrate11A and a lower substrate11C.

At least the data storage unit52that stores the time code and the time code transfer unit23are formed on the upper substrate11A. At least the pixel circuit41including the photodiode121is formed on the lower substrate11C. The upper substrate11A and the lower substrate11C are bonded by, for example, metal bonding of Cu—Cu or the like.

FIG.6illustrates a circuit configuration example formed on each of the upper substrate11A and the lower substrate11C. Note that the solid-state imaging device1can also include three semiconductor substrates11.

A circuit of the ADC42excluding the transistors81,82, and85and the time code transfer unit23are formed on the upper substrate11A. The pixel circuit41and circuits of the transistors81,82, and85of the differential input circuit61of the ADC42are formed on the lower substrate11C.

First Embodiment

FIG.7is a circuit diagram illustrating a configuration example of the solid-state imaging device1according to the first embodiment.

The pixel circuit41has an FD125that accumulates charge generated by photoelectric conversion according to the amount of light received by the pixel21. Note thatFIG.7illustrates the load capacitance unit MIM and the switching transistor126to which the signal FDG is input, in addition to the pixel circuit41described inFIG.4. The switching transistor126is connected between the reset transistor124and the FD125. Furthermore, the load capacitance unit MIM is connected between the gate of the switching transistor126and the ground. The switching transistor126is turned on or off according to the signal FDG input to the gate. Thus, it is possible to switch the conversion efficiency of the FD125by switching the electrical connection between the FD125and the load capacitance unit MIM.

The comparison circuit51compares a voltage corresponding to the accumulated charge of the FD125with a reference voltage. Note that the transistors81,82, and85are hereinafter referred to as a fourth transistor Tr4, a fifth transistor Tr5, and a third transistor Tr3, respectively.

Here, in a case where the ADC42is provided for each pixel, as illustrated inFIGS.6and7, the pixel circuit41and the output side of the differential input circuit61that is a comparator circuit are connected via Cu—Cu connection. In this case, for example, when resetting the charge of the FD125, it becomes difficult to directly supply the voltage from the first power supply voltage VDD of the differential input circuit61to the FD125. This is because a voltage drop occurs across the differential input circuit61, and the input voltage to the reset transistor124decreases from the first power supply voltage VDD. In this case, the reset potential of the FD125decreases, and the potential relationship with the transfer transistor123is disadvantageous from the viewpoint of electric charge pumping. Consequently, the influence of noise increases.

Accordingly, the solid-state imaging device1of the present embodiment further includes a boosting unit130that raises the potential of (one end side of) the FD125at the time of photoelectric conversion.

In the example illustrated inFIG.7, the boosting unit130includes a first transistor Tr1that controls the current flowing through the comparison circuit51so that the potential of the FD125increases at the time of photoelectric conversion. The first transistor Tr1is, for example, a PMOS transistor.

Furthermore, more specifically, the solid-state imaging device1further includes a current source140that generates a current flowing through the comparison circuit51. The first transistor Tr1controls the current generated by the current source140. In the example illustrated inFIG.7, the current source140includes a third transistor Tr3that causes a current to flow in the comparison circuit51.

Furthermore, the solid-state imaging device1further includes a second transistor Tr2. The second transistor Tr2is, for example, an NMOS transistor. The current source140controls the current flowing through the comparison circuit51according to the current flowing through the second transistor Tr2. That is, the second transistor Tr2is arranged and connected so as to form a current mirror circuit together with the third transistor Tr3. In the example illustrated inFIG.7, the second transistor Tr2is diode-connected, and the gate of the third transistor Tr3is connected to the gate of the second transistor Tr2.

FIG.8is a diagram illustrating an example of the arrangement of the first transistor Tr1ofFIG.7in the stacked semiconductor substrates11. In the example illustrated inFIG.8, as inFIGS.5and6, the upper substrate11A is a logic substrate (logic circuit substrate), and the lower substrate11C is a pixel substrate including the pixel circuit41. Light is incident on the photodiode121from the lower side ofFIG.8toward the lower substrate11C. Furthermore, the N+region is used for a contact in each semiconductor substrate11.

In the example illustrated inFIG.8, the first transistor Tr1and the second transistor Tr2are arranged in the lower substrate11C on which the pixel circuit41is arranged. That is, the first transistor Tr1and the second transistor Tr2are provided in the same chip as the pixel region, that is, in the lower substrate11C. In the example illustrated inFIG.7, the “pixel region” is a region including the pixel circuit41, the fourth transistor, the fourth transistor Tr4, the fifth transistor Tr5, and the current source140(third transistor Tr3).

Furthermore, as illustrated inFIG.7, the first transistor Tr1is connected between the first power supply voltage VDD and the second transistor Tr2. The second transistor Tr2is connected between the first transistor Tr1and the ground. That is, the first transistor Tr1is cascode-connected to the second transistor Tr2. Therefore, a current flowing through the second transistor Tr2is controlled by a gate voltage of the first transistor Tr1. That is, the first transistor Tr1can control the input bias current VB. A gate voltage of the third transistor Tr3is raised when the first transistor Tr1is turned on. Furthermore, the gate of the third transistor Tr3is capacitively coupled to the FD125. Thus, a voltage of the FD125can be raised by the gate voltage of the first transistor Tr1.

A voltage at which the first transistor Tr1is turned on is applied to the gate of the first transistor Tr1. More specifically, for example, a voltage lower than the first power supply voltage VDD by a threshold voltage is applied to the gate of the first transistor Tr1. Furthermore, a pulsed voltage is applied to the gate of the first transistor Tr1.

FIG.9is a timing chart illustrating an example of the operation of the solid-state imaging device1.FIG.9is a diagram illustrating operations of the third transistor Tr3, the reset transistor124, the transfer transistor123, and the discharge transistor122to which pulses of the input bias currents VB, RST signal, TG signal, and OFG signal are input, respectively.

Note that a pulse voltage of the gate voltage input to the first transistor Tr1corresponds to a pulse current of the input bias current VB. The first transistor Tr1is driven in accordance with a timing of resetting the charge of the FD125. More specifically, the pulse voltage is input to the gate of the first transistor Tr1so as to be driven after operation of the reset transistor124.

First, since the RST voltage changes from low to high at time t1, the reset transistor124is turned on, and the charge accumulated in the FD125is reset. Thereafter, at time t2, the reset transistor124is turned off.

Thereafter, at time t3, the input bias current VB increases since the input bias current VB changes from low to high. That is, the third transistor Tr3causes a substantially constant current to flow through the comparison circuit51, and the first transistor Tr1increases the current flowing through the third transistor Tr3in a predetermined period after resetting the charge of the FD125. Thus, the gate voltage of the third transistor Tr3increases. Here, since the third transistor Tr3and the FD125are arranged so as to be close to each other, the potential of the FD125increases due to an increase in the gate voltage of the third transistor Tr3. Consequently, decrease in the reset potential of the FD125can be suppressed, and the influence of noise can be suppressed.

Thereafter, at time t4, since the TG voltage changes from low to high, the transfer transistor123is turned on, and the charge generated by the photodiode121is transferred to the FD125. Thereafter, at time t5, the transfer transistor123is turned off.

Thereafter, at time t6, since the OFG signal changes from low to high, the discharge transistor122is turned on, and the potential of the photodiode121is reset to the first power supply voltage VDD. This is because the drain of the discharge transistor122is connected to the first power supply voltage VDD as illustrated inFIG.7. Thereafter, at time t7, the discharge transistor122is turned off.

Thereafter, at time t8, the input bias current VB returns to the current value before time t3. Therefore, the constant current flowing through the differential transistor pair (the fourth transistor Tr4and the fifth transistor Tr5) decreases.

In this manner, the first transistor Tr1is turned on at the time of pixel reading. More specifically, for example, the first transistor Tr1is turned on after the reset of the FD125by the reset transistor124, and is turned off at the end of the P-phase (pre-charge phase) in the CDS processing.

As described above, according to the first embodiment, the third transistor Tr3and the FD125are arranged close to each other. Furthermore, the first transistor Tr1controls the current flowing through the third transistor to raise the potential of the FD125at the time of photoelectric conversion. Thus, it is possible to suppress a decrease in the reset potential of the FD125due to the passage through the differential input circuit61, and the potential of the FD125can be deepened. Consequently, the influence of noise can be suppressed.

Note that the first transistor Tr1is not limited to the pulse drive illustrated inFIG.9, and may be continuously in the ON state.

FIG.10is a circuit diagram illustrating a first modification of the configuration of the solid-state imaging device1inFIG.7.FIG.10is different fromFIG.7in that the first transistor Tr1and the second transistor Tr2are arranged on a chip different from the chip of the pixel circuit41.

FIG.11Ais a diagram illustrating an example of arrangement of the first transistor inFIG.10in the stacked semiconductor substrates11.FIG.11Ais different fromFIG.8in that the first transistor Tr1and the second transistor Tr2are arranged on the upper substrate11A.

FIG.11Bis a diagram illustrating a modification of the arrangement of the first transistor Tr1ofFIG.10in the stacked semiconductor substrates11.FIG.11Bis different fromFIG.8in that the first transistor Tr1and the second transistor Tr2are arranged on an intermediate substrate11B arranged between the upper substrate11A and the lower substrate11C.

That is, the solid-state imaging device1includes a first chip and a second chip. The pixel circuit41having the FD125is arranged on the first chip. The second chip is stacked on the first chip, and at least a part of the boosting unit130including the first transistor Tr1is arranged.

Furthermore, inFIGS.11A and11B, in a case where the first transistor Tr1and the second transistor Tr2are arranged on a chip different from the pixel circuit41, the arranged chip may be a logic substrate or a pixel substrate.

FIG.12is a circuit diagram illustrating a second modification of the configuration of the solid-state imaging device1inFIG.7.FIG.12is different fromFIG.7in that the first transistor Tr1is arranged in the pixel region. Note that, the third transistor Tr3is connected to the second transistor Tr2(not illustrated) as inFIG.7.

In the example illustrated inFIG.12, the first transistor Tr1is cascode-connected to the third transistor Tr3. Furthermore, the first transistor Tr1is, for example, an NMOS transistor.

Furthermore, more specifically, the comparison circuit51includes a differential transistor pair that outputs a signal corresponding to a differential voltage between the voltage corresponding to the accumulated charge of the FD125and the reference voltage. The differential transistor pair includes a fourth transistor Tr4and a fifth transistor Tr5. The first transistor Tr1is connected between the differential transistor pair and the third transistor Tr3.

Even in a case where the first transistor Tr1is arranged in the pixel region, the voltage of the FD125can be raised by the gate voltage.

FIG.13is a circuit diagram illustrating a third modification of the configuration of the solid-state imaging device1inFIG.7.FIG.13is different fromFIG.11in the arrangement of the first transistor Tr1in the pixel region.

In the example illustrated inFIG.13, the third transistor Tr3is connected between the differential transistor pair, the first transistor, and Tr1. That is, the first transistor Tr1is arranged between the fourth transistor Tr4and the ground.

FIG.14is a circuit diagram illustrating a fourth modification of the configuration of the solid-state imaging device1inFIG.7.FIG.13is different fromFIG.12in that the first transistor Tr1is shared by a plurality of pixel circuits41.

In the example illustrated inFIG.14, the first transistor Tr1and the third transistor Tr3are shared by a plurality of pixels21each having the FD125. That is, the first transistor Tr1is connected to a plurality of differential transistor pairs in a plurality of pixel regions. Thus, the number of the first transistors Tr1and the third transistors Tr3installed is reduced, so that the area of the pixel array unit22can be suppressed. Furthermore, the first transistor Tr1and the third transistor Tr3are arranged in a chip on which the pixel circuit41having the FD125is arranged. As illustrated inFIG.14, the first transistor Tr1and the third transistor Tr3may be arranged in the pixel array unit22, or may be arranged in a space where the area of the pixel array unit22can be suppressed. In the example illustrated inFIG.14, the first transistor Tr1and the third transistor Tr3are arranged outside the pixel region. Furthermore, the connection between the first transistor Tr1and the plurality of pixels may be directly connected by wiring, or may be connected via a diffusion layer.

FIG.15is a circuit diagram illustrating a fifth modification of the configuration of the solid-state imaging device1inFIG.7.FIG.15is different fromFIG.14in the arrangement of the shared first transistor Tr1.

In the example illustrated inFIG.15, the first transistor Tr1and the third transistor Tr3are arranged in the pixel region of one pixel21among the plurality of pixels21. That is, the first transistor Tr1in the pixel region of a certain pixel21is also connected to the differential transistor pair in the pixel region of another pixel21.

Note that, in the first embodiment, a plurality of modifications may be combined.

Second Embodiment

FIG.16is a circuit diagram illustrating a configuration example of a solid-state imaging device1according to a second embodiment.FIG.16is different fromFIG.7in that a capacitor C is used as the boosting unit130. Note that, in the example illustrated inFIG.16, the first transistor Tr1described in the first embodiment is arranged. In the second embodiment, the first transistor Tr1is not necessarily arranged. However, in a case where the first transistor Tr1is used, the voltage of the FD125can be further increased, which is more preferable from the viewpoint of noise suppression.

In the example illustrated inFIG.16, the boosting unit130raises the potential of the FD125using capacitive coupling. More specifically, the boosting unit130raises the potential of the FD125by capacitive coupling between the gate wiring of the transistor constituting the current source140and the FD125. The boosting unit130has a capacitor C that raises the voltage of the FD125. The capacitor C is, for example, an inter-wiring capacitor arranged between the FD125and the gate of the third transistor Tr3. That is, the capacitor C is generated by capacitive coupling between the wiring of the FD125and the gate wiring of the third transistor Tr3adjacent to each other.

FIG.17is a layout diagram illustrating an example of arrangement of each configuration in the pixel region ofFIG.16.

As indicated by an arrow inFIG.17, the third transistor Tr3and the FD125are arranged close to each other. Thus, the gate wiring of the third transistor Tr3can be arranged so as to be adjacent to the FD125, and the capacitor C illustrated inFIG.16is generated. Furthermore, the arrangement is not limited to the two-dimensional arrangement, and the gate wiring of the third transistor Tr3and the wiring of the FD125may be arranged to three-dimensionally overlap (traverse) at least at one position. That is, capacitive coupling via an insulating layer in a chip in which a wiring layer and an insulating layer are alternately stacked is used for the capacitor C. In this case, the distance between the wirings can be further shortened, the width (area) of the wiring can be used as the electrode area of the capacitor C, and the potential of the FD125can be further raised.

As described above, in the second embodiment, the potential of the FD125is raised by capacitive coupling between the gate wiring of the transistor constituting the current source140and the FD125. Thus, as in the first embodiment, it is possible to suppress a decrease in the reset potential of the FD125due to the passage through the differential input circuit61, and to suppress the influence of noise.

Furthermore, the first embodiment and modifications thereof may be combined with the solid-state imaging device1of the second embodiment.

FIG.18is a circuit diagram illustrating a modification of the configuration of the solid-state imaging device1according to the second embodiment.FIG.18is a diagram illustrating an example in which the second embodiment is applied toFIG.12which is a second modification of the first embodiment. As illustrated inFIG.18, the capacitor C may be connected between the gate wiring of the first transistor Tr1and the FD125. That is, the first transistor Tr1and the FD125may be arranged to be close to each other.

<Application Example to Mobile Body>

The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be achieved as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, and the like.

FIG.19is a block diagram illustrating a schematic configuration example of a vehicle control system which is an example of a moving body control system to which the technology according to the present disclosure can be applied.

The outside-vehicle information detecting unit12030detects information about the outside of the vehicle including the vehicle control system12000. For example, the outside-vehicle information detecting unit12030is connected with an imaging section12031. The outside-vehicle information detecting unit12030causes the imaging section12031to capture an image outside the vehicle, and receives the captured image. On the basis of the received image, the outside-vehicle information detecting unit12030may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section12031is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging section12031can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section12031may be visible light, or may be invisible light such as infrared rays or the like.

The in-vehicle information detecting unit12040detects information about the inside of the vehicle. The in-vehicle information detecting unit12040is, for example, connected with a driver state detecting section12041that detects the state of a driver. The driver state detecting section12041includes, for example, a camera that captures an image of the driver, and the in-vehicle information detecting unit12040may calculate the degree of fatigue or the degree of concentration of the driver, or determine whether or not the driver is dozing on the basis of detection information input from the driver state detecting section12041.

In addition, the microcomputer12051can perform cooperative control intended for automated driving, which makes the vehicle to travel in an automated manner without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle obtained by the outside-vehicle information detecting unit12030or the in-vehicle information detecting unit12040.

The sound/image output section12052transmits an output signal of at least one of a sound or an image to an output device capable of visually or auditorily notifying an occupant of the vehicle or the outside of the vehicle of information. In the example ofFIG.19, an audio speaker12061, a display section12062, and an instrument panel12063are illustrated as the output device. The display section12062may, for example, include at least one of an on-board display or a head-up display.

FIG.20is a diagram illustrating an example of the installation position of the imaging section12031.

The imaging sections12101,12102,12103,12104, and12105are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle12100as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section12101provided on the front nose and the imaging section12105provided on the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle12100. The imaging sections12102and12103provided on the sideview mirrors obtain mainly an image of the sides of the vehicle12100. The imaging section12104provided on the rear bumper or the back door obtains mainly an image of the rear of the vehicle12100. The forward image obtained by the imaging sections12101and12105are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, and the like.

Note thatFIG.20illustrates an example of imaging ranges of the imaging sections12101to12104. An imaging range12111represents the imaging range of the imaging section12101provided on the front nose, imaging ranges12112and12113represent the imaging ranges of the imaging sections12102and12103provided in the side mirrors, respectively, and an imaging range12114represents the imaging range of the imaging section12104provided in the rear bumper or the back door. A bird's-eye image of the vehicle12100as viewed from above is obtained by superimposing image data imaged by the imaging sections12101to12104, for example.

For example, on the basis of distance information obtained from the imaging sections12101to12104, the microcomputer12051can obtain a distance to each three-dimensional object in the imaging ranges12111to12114, and a temporal change of this distance (relative speed to the vehicle12100), and thereby extract, as a preceding vehicle, a three-dimensional object that is closest particularly on the traveling path of the vehicle12100and travels at a predetermined speed (for example, equal to or more than 0 km/h) in substantially the same direction as the vehicle12100. Moreover, the microcomputer12051can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel in an automated manner without depending on the operation of the driver or the like.

For example, the microcomputer12051can classify three-dimensional object data on three-dimensional objects into a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects, and the like on the basis of the distance information obtained from the imaging sections12101to12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer12051identifies obstacles around the vehicle12100as obstacles that the driver of the vehicle12100can recognize visually and obstacles that are difficult for the driver of the vehicle12100to recognize visually. Then, the microcomputer12051determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than a set value and there is a possibility of collision, the microcomputer12051can output a warning to the driver via the audio speaker12061and the display section12062, or perform forced deceleration or avoidance steering via the driving system control unit12010, to thereby perform assistance in driving for collision avoidance.

The example of the vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging sections12031,12101,12102,12103,12104, and12105, the driver state detecting section12041, and the like among the above-described configurations. Specifically, for example, the solid-state imaging device1of the present disclosure can be applied to these imaging sections and detecting section. Then, by applying the technology according to the present disclosure, noise can be suppressed, so that safer vehicle traveling can be achieved.

Note that the present technology can have configurations as follows.(1) A solid-state imaging device, including:a floating diffusion that accumulates charge generated by photoelectric conversion according to an amount of received light of a pixel;a comparison circuit that compares a voltage corresponding to accumulated charge of the floating diffusion with a reference voltage; anda boosting unit that raises a potential on one end side of the floating diffusion during photoelectric conversion.(2) The solid-state imaging device according to (1), in which the boosting unit includes a first transistor that controls a current flowing through the comparison circuit in such a manner that a potential on one end side of the floating diffusion becomes high.(3) The solid-state imaging device according to (2), further includinga current source that generates a current flowing through the comparison circuit, in whichthe first transistor controls a current generated by the current source.(4) The solid-state imaging device according to (3), further includinga second transistor cascode-connected to the first transistor, in whichthe current source controls a current flowing through the comparison circuit according to a current flowing through the second transistor.(5) The solid-state imaging device according to (4), in which a current flowing through the second transistor is controlled by a gate voltage of the first transistor.(6) The solid-state imaging device according to (4) or (5), in whichthe current source includes a third transistor that causes a current to flow in the comparison circuit, anda gate of the third transistor is connected to a gate of the second transistor.(7) The solid-state imaging device according to (6), in which a gate voltage of the third transistor is raised when the first transistor is turned on.(8) The solid-state imaging device according to (6) or (7), in which a gate of the third transistor is capacitively coupled to the floating diffusion.(9) The solid-state imaging device according to any one of (2) to (8), further includinga first chip on which a pixel circuit having the floating diffusion is arranged; anda second chip stacked on the first chip and in which at least a part of the boosting unit including the first transistor is arranged.(10) The solid-state imaging device according to (3), in whichthe current source includes a third transistor that causes a current to flow in the comparison circuit, andthe first transistor is cascode-connected to the third transistor.(11) The solid-state imaging device according to (10), in whichthe comparison circuit includes a differential transistor pair that outputs a signal corresponding to a differential voltage between a voltage corresponding to the accumulated charge of the floating diffusion and the reference voltage, andthe first transistor is connected between the differential transistor pair and the third transistor.(12) The solid-state imaging device according to (10), in whichthe comparison circuit includes a differential transistor pair that outputs a signal corresponding to a differential voltage between a voltage corresponding to the accumulated charge of the floating diffusion and the reference voltage, andthe third transistor is connected between the differential transistor pair and the first transistor.(13) The solid-state imaging device according to any one of (10) to (12), in which the first transistor and the third transistor are shared by a plurality of pixels each having the floating diffusion.(14) The solid-state imaging device according to (13), in which the first transistor and the third transistor are arranged in a chip on which a pixel circuit having the floating diffusion is arranged.(15) The solid-state imaging device according to (13) or (14), in which the first transistor and the third transistor are arranged in a pixel region of one pixel among the plurality of pixels.(16) The solid-state imaging device according to (1), in which the boosting unit raises a potential on one end side of the floating diffusion using capacitive coupling.(17) The solid-state imaging device according to (16), further includinga current source that generates a current flowing through the comparison circuit, in whichthe boosting unit raises a potential on one end side of the floating diffusion by capacitive coupling between a gate wiring of a transistor constituting the current source and the floating diffusion.(18) The solid-state imaging device according to any one of (1) to (17), further including:a time code generator that generates a time code;a time code transfer unit that transfers the time code generated by the time code generator;a reference voltage generator that generates the reference voltage whose voltage level changes according to time; anda time code holding unit that is provided for each pixel and holds the time code when the voltage corresponding to the accumulated charge of the floating diffusion and the reference voltage match as a digital signal corresponding to the amount of received light.(19) The solid-state imaging device according to (18), in which the time code generator, the time code transfer unit, the reference voltage generator, and the time code holding unit are arranged on a chip different from a chip on which a pixel circuit having the floating diffusion is arranged.

Aspects of the present disclosure are not limited to the above-described individual embodiments, but include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. That is, various additions, modifications, and partial deletions can be made without departing from the conceptual idea and spirit of the present disclosure derived from the contents defined in the claims and equivalents thereof.

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