Computer and compiling method

To provide new instruction and device suitable for tracing execution of a computer program. In an embodiment, a CPU is configured so as to supply a constant to a trace unit in response to decoding of a first instruction having an immediate field indicating the constant. In addition, the trace unit is configured so as to output trace data including the constant in response to execution of the first instruction in the CPU.

CROSS-REFERENCE TO RELATED APPLICATION

The disclosure of Japanese Patent Application No. 2013-203680 filed on Sep. 30, 2013 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a computer and is suitably used for, for example, a computer that outputs trace data based on execution of a program.

A multiprogramming environment means an environment in which a plurality of programs is, so to speak, executed in parallel by periodically switching the programs or switching a program to be executed in response to an occurrence of an event. The multiprogramming may also be referred to as multiprocess, multithread, multitask, and the like. A process, a thread, and a task mean a processing unit that is executed in parallel in the multiprogramming environment. Although these terms are often mixed up and used, generally, the process is a parallel processing unit to which a program execution environment such as a memory space is independently assigned and which is highly independent from other processes. On the other hand, the thread is a smaller parallel processing unit included in a process that is processed in parallel. In a multithread environment, a process includes a plurality of threads. Each thread can access a resource assigned to the process, and a plurality of threads in the same process shares a memory space. The thread and the process may be referred to as a task.

In order to support debug of a program executed in the multiprogramming environment, there is known a tool which displays a chart showing executions of functions, threads, or processes and transitions of these, as shown inFIG. 1. In the example ofFIG. 1, time transition of tasks (that is, threads or processes) is visually displayed. Meanwhile, the function is a packaged program module including an instruction sequence for performing specific processing. The term of “function” used in the present specification means a concept including a function in a strict sense that returns a return value and a procedure that does not return a return value, according to C and C++ that are typical of structured programming languages. The term of “function” used in the present specification can be referred to as a subroutine, a subprogram, or a method.

In order to grasp the transition of function, thread, or process, in compiling which generates assembly code from source code, a code called a marker instruction or a check point instruction is inserted in the assembly code. The marker instruction or the check point instruction is different from arithmetic instructions and load/store instructions for performing original processing described in the source code and is a debug instruction defined to trace an execution of a program. The marker instruction or the checkpoint instruction is executed on a computer configured to output trace data based on execution of a program.

For example, Japanese Patent Laid-Open No. 1998-78889 (Patent Literature 1) discloses a computer including a CPU (Central Processing Unit) and a monitor unit. In Patent Literature 1, the CPU (Central Processing Unit) supplies a marker decoding signal (a pulse signal) to the monitor unit in order to activate the monitor unit in response to decoding of the marker instruction. In addition, in response to reception of the marker decoding signal, the monitor unit acquires an address of the marker instruction (a program counter value) and a value of an accumulator, and outputs trace data including an identifier indicating the marker instruction (for example, an identifier such as “M”), the address of the marker instruction, and the value of the accumulator.

SUMMARY

As shown in Patent Literature 1, the marker instruction (or the check point instruction) is generally used in order to output trace data including an identifier indicating the marker instruction (for example, an identifier such as “M”), an address of the marker instruction, and a value of a register such as an accumulator. However, such a marker instruction (or check point instruction) and an operation of a computer according to the marker instruction may be insufficient to trace an execution of a complicated computer program.

For example, a case is considered where a computer executes a program in which the marker instruction is arranged immediately before a function. In this case, it is considered that a debugger (a debug host) identifies the function ID corresponding to the address of the marker instruction by preparing a table that defines a correspondence relationship between the marker instruction and a function ID (identifier) and by comparing the address of the marker instruction included in the trace data with the table. However, the function ID corresponding to the address of the marker instruction is not necessarily determined uniquely. For example, in an overlay program or the like, different programs may use the same instruction address. Therefore, it is not possible to uniquely distinguish the function ID only by the instruction address. When the trace data includes execution results of a plurality of marker instructions having the same instruction address, it is difficult to identify the function executed by the computer on the basis of the instruction address of the marker instruction. Therefore, there is a first problem of having difficulty in grasping the transition of function, thread, or process on the basis of the trace data, when a computer is running.

In addition, for example, values of a plurality of registers, for example, a plurality of arguments or a plurality of return values of a function or a thread, are required to be output as trace data. In this case, generally, a plurality of instructions, the number of which corresponds to the number of the registers has to be arranged in a program. Therefore, there is a second problem in which many instructions (generally, the number of instructions is the same as the number of registers whose values are outputted) are required in order to output values of a plurality of registers as trace data.

Hereinafter, a plurality of embodiments that can contribute to solving at least one of a plurality of problems including the first and the second problems described above will be described. The other problems and the new feature of the present invention will become clear from the description of the present specification and the accompanying drawings.

Means for Solving the Problems

In an embodiment, a CPU supplies a constant to a trace unit in response to decoding of a first instruction having an immediate field indicating the constant. In addition, the trace unit outputs trace data including the constant in response to execution of the first instruction in the CPU.

In another embodiment, a CPU supplies values of a plurality of registers to the trace unit in response to decoding of one instruction having a field indicating the plurality of registers. In addition, the trace unit outputs trace data including the values of the registers in response to execution of the one instruction in the CPU.

The plurality of embodiments described above can contribute to solving at least one of the first and the second problems described above.

DETAILED DESCRIPTION

Hereinafter, specific embodiments will be described in detail with reference to the drawings. In each drawing, the same reference symbol is given to the same or corresponding component and redundant description is omitted if necessary for clarity of description.

FIG. 2is a block diagram showing a computer1according to the present embodiment and peripheral devices of the computer1. The computer1according to the present embodiment is, for example, a microprocessor, a microcomputer, a microcontroller, or a SoC (System on Chip). The computer1may be configured by only one IC chip or may be configured by a plurality of IC chips. The computer1provides a multiprogramming environment. The computer1is configured so as to execute a computer program (an executable program) and to output trace data based on the execution of the computer program, and is coupled to a memory50and a storage device60.

The memory50stores a computer program (an instruction group) to be executed in the computer1, data to be calculated in the computer1, data that have been calculated in the computer1, and the like. In other words, the memory50includes an instruction memory (or an instruction cache) and a data memory (or a data cache). The memory50may be configured by a volatile memory, a non-volatile memory, or a combination of these. The volatile memory is, for example, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), or a combination of these. The non-volatile memory is, for example, a mask ROM (Read Only Memory), a programmable ROM, a flash memory, a hard disk drive, or a combination of these.

The storage device60stores trace data outputted from the computer1. The storage device60may be configured by a volatile memory, a non-volatile memory, or a combination of these. The storage device60may be arranged in the same chip as the computer1(on-chip) or may be arranged outside the computer1(off-chip). The storage device60may be arranged in a computer system (that is, a debug host) that executes debugger software and controls debugging of a target system including the computer1and the memory50.

The computer1includes a CPU (Central Processing Unit)10and a trace unit15. The CPU10can be referred to as an MPU (Micro Processing Unit), a CPU core, an MPU core, or a processor core. The CPU10reads an instruction included in the computer program from the memory50, decodes the instruction, and executes processing such as calculation, memory access (load and store), and the like according to the instruction. Furthermore, the CPU10operates so as to generate trace information in response to decoding of an instruction defined for debug or trace, included in the computer program and to supply the trace information to the trace unit15. The CPU10may include a cache memory, an instruction fetch unit, an instruction decode unit, a control unit such as a sequencer, an ALU (Arithmetic Logic Unit), a load/store unit, and other functional units. The ALU includes arithmetic operation units such as an adder, a multiplier, and a divider; a logical operation unit; a shifter, and the like.

The trace unit15receives the trace information from the CPU10, generates trace data by formatting the trace information, and outputs the trace data to the storage device60. The trace unit15may include a trace controller that controls trace, a trace buffer that temporarily stores the trace information, and an interface for communicating with the storage device60.

Furthermore, in the computer1according to the present embodiment, in response to decoding of a DBTAG instruction having an immediate field that indicates a constant, the CPU10operates so as to supply the constant indicated in the immediate field of the DBTAG instruction to the trace unit15. In addition, the trace unit15operates so as to output trace data including the constant indicated in the immediate field of the DBTAG instruction in response to execution of the DBTAG instruction in the CPU10.

The DBTAG instruction is an instruction defined in order to trace execution of the computer program executed in the CPU10. For example, the DBTAG instruction can be used in order to trace execution of a function, a thread, a process, or a task included in the computer program. In this case, the immediate field of the DBTAG instruction may indicate an identifier of the function, the thread, the process, or the task included in the computer program. The DBTAG instruction may be arranged close to a module (that is, an instruction group) corresponding to the function, the thread, the process, or the task in the computer program. For example, the DBTAG instruction may be arranged immediately before the instruction group of the function, the thread, the process or the task, in the instruction group, or immediately after the instruction group. The identifier of the function, the thread, the process, or the task may be automatically inserted in assembly code by a compiler during compiling processing in which the assembly code is generated from source code.

In addition, the DBTAG instruction may be used for other uses. For example, the DBTAG instruction may be used for a user (programmer) to output any bit string or character string as trace data. In this case, the user (programmer) may arrange a debug instruction having an immediate field indicating any bit string, in source code of a high-level language described in C language, C++ language, or the like. Furthermore, the compiler may convert the debug instruction into one DBTAG instruction.

FIG. 3shows an example of an instruction format of the DBTAG instruction. In the example shown inFIG. 3, the DBTAG instruction has 32-bit length overall including an operation code field11of 6-bit length and an immediate field12of 10-bit length. The operation code field11indicates that the instruction is the DBTAG instruction. As described above, the immediate field12is used in order to indicate an identifier of, for example, a function, a thread, a process, or a task. Meanwhile,FIG. 3is an example, and the bit length of the DBTAG instruction may not be 32 bits, the bit length of operation code field11may not be 6-bits, and the bit length of the immediate field12may not be 10 bits.

FIG. 4is a flowchart showing an example of an operation of the CPU10that executes a computer program (an executable program) including the DBTAG instruction. In step S11, the CPU10analyzes an operation code of an instruction fetched from the memory50. When the instruction decoded in step S11is the DBTAG instruction (YES in step S12), the CPU10supplies a value of the immediate field of the DBTAG instruction and a value of a program counter (PC), to the trace unit15(step S13). The program counter (PC) is an instruction address register used in order to indicate an address in the memory at which an instruction to be executed next by the CPU10is stored. The PC value supplied to the trace unit15in step S13indicates an address of the DBTAG instruction decoded in step S11. On the other hand, when the instruction decoded in step S11is not the DBTAG instruction (NO in step S12), the CPU10performs processing in accordance with the decoded instruction (step S14).

As understood from the above description, in the computer according to the present embodiment, in response to decoding of the DBTAG instruction having the immediate field that indicates a constant, the CPU10operates so as to supply the constant indicated in the immediate field of the DBTAG instruction, to the trace unit15. In addition, the trace unit15operates so as to output trace data including the constant indicated in the immediate field of the DBTAG instruction in response to execution of the DBTAG instruction in the CPU10.

For example, the immediate field of the DBTAG instruction may be used in order to indicate an identifier of a function, a thread, a process, or a task, included in a computer program. Thereby, a debugger (a debug host) can directly acquire the identifier of the function, the thread, the process, or the task by referring to the constant value indicated in the immediate field of the DBTAG instruction included in the trace data. In other words, the debugger (the debug host) need not prepare a table that defines a correspondence relationship between an address of the DBTAG instruction and a function ID (a thread ID, a process ID, or a task ID) and need not estimate the function ID (the thread ID, the process ID, or the task ID) based on the address of the DBTAG instruction. Therefore, even when debugging an overlay program in which different programs may use the same instruction address, it is possible to uniquely identify the function ID (the thread ID, the process ID, or the task ID) on the basis of a value in the immediate field of the DBTAG instruction.

Furthermore, the CPU10according to the present embodiment may be configured so that when decoding the DBTAG instruction, the CPU10supplies an immediate value of the DBTAG instruction to the trace unit15without storing the immediate value of the DBTAG instruction in a general-purpose register (GPR). It is considered that the marker instruction and the check point instruction described in Related Art are used for applications outputting the value of the GPR that stores, in advance, any value such as the function ID. However, in order to do so, the CPU has to execute an instruction (for example, a MOV instruction) to store any value such as the function ID in the GPR, before executing the marker instruction and the check point instruction. Moreover, in a method of temporarily storing any value such as the function ID in the GPR, the GPR that may be used by a user program for another purpose is used for a trace that is irrelevant to the original program flow. Therefore, the value in the GPR used by the user program may be overwritten. In order to avoid the breakdown of the register, it is necessary to temporarily save the value of the GPR in a memory or the like before storing any value such as the function ID in the GPR. In addition, it is necessary to store again the value saved in the memory or the like in the original GPR after executing the marker instruction and the check point instruction. Naturally, the program size and the processing time of the CPU increase due to the increase of the above processes. Therefore, by supplying the immediate value of the DBTAG instruction to the trace unit15without storing the immediate value of the DBTAG instruction in the GPR, it is possible to efficiently include any value such as the function ID in the trace data, without executing redundant instructions and processes.

Furthermore, the DBTAG instruction may be defined as one instruction. In other words, the DBTAG instruction may be described as one assembly instruction in assembly code. Thereby, it is possible to reduce the number of instructions added to a program for debug or trace, and to thereby reduce the program code size.

Hereinafter, a specific example of configuration and operation of the computer1according to the present embodiment will be described in further detail.FIG. 5shows a configuration example of the CPU10and the trace unit15included in the computer1. In the configuration example ofFIG. 5, the CPU10includes an instruction fetch unit101, an instruction decode unit102, a control unit103, a general-purpose register (GPR) file104, an instruction execution unit105, and a completion unit106. The instruction fetch unit101fetches an instruction from the memory50. The instruction decode unit102decodes the fetched instruction.

The control unit103controls operations of the functional units (for example, the instruction decode unit102, the general-purpose register file104, and the instruction execution unit105) in the CPU10on the basis of a decode result of the instruction. Namely, the control unit103outputs a signal according to the decoded instruction to the functional units (for example, the instruction decode unit102, the general-purpose register file104, and the instruction execution unit105) in the CPU10. For example, the control unit103outputs a control signal indicating a type of calculation to the instruction execution unit105. Furthermore, when the instruction is an immediate instruction, the control unit103supplies the immediate value to the instruction execution unit105. The control unit103may include a sequencer (a multi-cycle sequencer) for controlling issuance of a multi-cycle instruction. The control unit103may be referred to as a command generation unit and may also be referred to as a dispatch unit.

The general-purpose register file104includes a plurality of general-purpose registers (GPRs). The general-purpose register file104is versatilely used in order to temporarily store data inputted into the instruction execution unit105and data outputted from the instruction execution unit105. Therefore, the GPRs included in the general-purpose register file104are generally specified as a register operand in an instruction executed by the CPU10.

The instruction execution unit105performs specific data processing according to an instruction, such as arithmetic operation, logical operation, and load/store. The instruction execution unit105includes an ALU (Arithmetic Logic Unit) and a load/store unit. The ALU includes arithmetic operation units such as an adder, a multiplier and a divider, a logical operation unit, and a shifter. When executing a general arithmetic operation instruction, a general logical operation instruction, and a general register transfer instruction which have a register operand, the instruction execution unit105receives a value in a register from the general-purpose register file104and performs operation. The instruction execution unit105writes back an operation result to the general-purpose register file104via the completion unit106.

The completion unit106controls completion (retirement) of an instruction. For example, the completion unit106discards an entry of instruction after an interrupt or an instruction related to exception, from pipeline. Furthermore, the completion unit106of the present embodiment has an interface with the trace unit15and supplies trace information generated by execution of a trace instruction such as the DBTAG instruction, to the trace unit15.

Next, a configuration example of the trace unit15shown inFIG. 5will be described. The trace unit15shown inFIG. 5includes a trace controller151, a trace buffer152, and an interface153. The trace controller151includes an interface with the CPU10and an interface with the trace buffer152. The trace controller151receives the trace information from the CPU10, arranges the trace information into a format of trace data, and accumulates the trace data in the trace buffer152. The trace buffer152is a storage area for temporarily accumulating the trace data. The trace controller151acquires the trace data accumulated in the trace buffer152and writes the trace data to the storage device60via the interface153.

Subsequently, hereinafter, there will be described a specific example of an operation of the CPU10when the CPU10decodes the DBTAG instruction, with reference toFIG. 6. In the example ofFIG. 6, the CPU10is configured so that the CPU10does not store a constant indicated in the immediate field of the DBTAG instruction in the execution of the DBTAG instruction but supplies the constant to the trace unit15. Specifically, the instruction decode unit102notifies the control unit103of a notification DBTAG indicating the DBTAG instruction, an instruction address (PC value) PC of the DBTAG instruction, and the immediate value (the value in the immediate field) IMMEDIATE of the DBTAG instruction, in response to decoding of the DBTAG instruction. The control unit103generates a control signal indicating the DBTAG instruction and supplies the control signal, the instruction address (PC value) of the DBTAG instruction, and the immediate value of the DBTAG instruction, to the instruction execution unit105.

The instruction execution unit105shown inFIG. 6includes an ALU1051that performs arithmetic operation, logical operation and the like, a latch1052that holds output data of the ALU1051, and latches1053to1055. The latches1053to1055are arranged in order to hold the control signal indicating the DBTAG instruction, the instruction address (PC value) of the DBTAG instruction, and the immediate value of the DBTAG instruction. The instruction execution unit105holds, at the latches1053to1055, the control signal indicating the DBTAG instruction, the instruction address (PC value) of the DBTAG instruction, and the immediate value of the DBTAG instruction in an execution cycle of the DBTAG instruction, and outputs these data to the completion unit106in the next cycle. Namely, the instruction execution unit105does not supply the immediate value of the DBTAG instruction to the ALU1051and does not write the immediate value of the DBTAG instruction to the general-purpose register file104. The general-purpose register file104, the ALU1051, and the latch1052, which are shown by dashed lines inFIG. 6, indicate that these components are not used for execution of the DBTAG instruction.

The completion unit106receives, from the instruction execution unit105, the control signal indicating the DBTAG instruction, the instruction address (PC value) of the DBTAG instruction, and the immediate value of the DBTAG instruction. The completion unit106detects that the reception of the instruction address (PC value) and the immediate value from the instruction execution unit105is valid in response to reception of the control signal indicating the DBTAG instruction. In addition, the completion unit106outputs, to the trace unit15, a DBTAG trace valid signal, the instruction address (PC value) of the DBTAG instruction, and the immediate value of the DBTAG instruction. Here, the DBTAG trace valid signal notifies the trace unit15of the fact that trace information including the instruction address and the immediate value of the DBTAG instruction is valid.

According to the configuration and the operation of the CPU10shown inFIG. 6, it is possible to efficiently supply the value in the immediate field of the DBTAG instruction to the trace unit15. As an example, when the immediate field of the DBTAG instruction indicates a function ID (a thread ID, a process ID, or a task ID), the CPU10inFIG. 6can efficiently supply the function ID (the thread ID, the process ID, or the task ID) to the trace unit15. This is because the CPU10shown inFIG. 6does not require redundant operation such as writing the value of the immediate field of the DBTAG instruction to the general-purpose register file104. Furthermore, this is because the CPU10shown inFIG. 6does not require (a) processing of temporarily saving the value of GPR in the general-purpose register file104into a memory or the like before executing the marker instruction and the check point instruction, (b) processing of storing any value such as the function ID into the GPR when executing the marker instruction and the check point instruction, and (c) processing of storing the value saved in the memory or the like into the original GPR after executing the marker instruction and the check point instruction.

As understood from the above description, in the computer1according to the present embodiment, in response to decoding of the DBTAG instruction having the immediate field that indicates a constant, the CPU10operates so as to supply the constant indicated in the immediate field of the DBTAG instruction to the trace unit15. In addition, the trace unit15operates so as to output trace data including the constant indicated in the immediate field of the DBTAG instruction in response to execution of the DBTAG instruction in the CPU10. For example, the immediate field of the DBTAG instruction may be used in order to indicate an identifier of a function, a thread, a process, or a task, included in a computer program. Thereby, a debugger (a debug host) can directly acquire the identifier of the function, the thread, the process, or the task by referring to the constant value indicated in the immediate field of the DBTAG instruction included in the trace data. Therefore, even when debugging an overlay program in which different programs may use the same instruction address, it is possible to uniquely identify the function ID (the thread ID, the process ID, or the task ID) on the basis of the value in the immediate field of the DBTAG instruction, by using the computer1according to the present embodiment.

FIG. 7is a block diagram showing a computer2according to the present embodiment and peripheral devices of the computer2. The computer2according to the present embodiment includes a CPU20and a trace unit25coupled to the CPU20. The entire configuration of the computer2is the same as the configuration example of the computer1of the first embodiment shown inFIG. 2orFIG. 5.

In the computer2, in response to decoding of one DBPUSH instruction having a field indicating a plurality of registers, the CPU20operates so as to supply values of the registers specified by the DBPUSH instruction to the trace unit25. The trace unit25operates so as to output trace data including the values of the registers specified by the DBPUSH instruction in response to execution of the one DBPUSH instruction in the CPU20.

The DBPUSH instruction is an instruction defined in order to trace execution of a computer program executed in the CPU20. The DBPUSH instruction can be used in order to output, as the trace data, values of a plurality of general-purpose registers implemented in the CPU20, and the values of the general-purpose registers are outputted as the trace data by one DBPUSH instruction. Therefore, a plurality of instructions is not required in order to output the values of the general-purpose registers as the trace data, and thus the DBPUSH instruction has an advantage that the program code size can be reduced.

For example, the DBPUSH instruction can be used in order to output a plurality of arguments or a plurality of return values of a function included in the computer program. In this case, the DBPUSH instruction indicates a plurality of general-purpose registers holding the arguments of the function or the general-purpose registers holding the return values of the function. The DBPUSH instruction may be arranged close to a module corresponding to a function (that is, an instruction group). For example, the DBPUSH instruction may be arranged immediately before, at the top position of, at the tail position of, or immediately after an instruction group of a function. The DBPUSH instruction may be automatically inserted in assembly code by a complier in compiling processing.

The DBPUSH instruction may be used in order to trace values of a plurality of any registers by a user (a programmer). In this case, the DBPUSH instruction may be arranged in source code of a high-level language by the user (the programmer). In addition, the DBPUSH instruction may be automatically inserted in assembly code by a complier in the compiling processing.

FIG. 8shows an example of an instruction format of the DBPUSH instruction. In the example shown inFIG. 8, the DBPUSH instruction has 32-bit length overall including an operation code field21of 6-bit length, a first register operand field22of 5-bit length, and a second register operand field23of 5-bit length. The operation code field21indicates that the instruction is the DBPUSH instruction. The first and the second register operand fields22and23indicate a range of general-purpose registers to be outputted as the trace data. For example, the first register operand field22indicates a register number of the top register to be outputted and the second register operand field23indicates a register number of the tail register to be outputted. For example, when the first register operand field22indicates a register number2(a general-purpose register R2) and the second register operand field23indicates a register number5(a general-purpose register R5), four register values of the general-purpose registers R2, R3, R4, and R5are outputted.

FIG. 9shows another example of the instruction format of the DBPUSH instruction. In the example ofFIG. 9, a list of registers to be outputted as the trace data is specified instead of the range of the registers. Specifically, the DBPUSH instruction shown inFIG. 9has 32-bit length overall including an operation code field21of 6-bit length and an immediate field24of 26-bit length. Each bit of the immediate field24of 26-bit length is associated on a one-to-one basis with any of a plurality of general-purpose registers. In the example ofFIG. 9, twelve general-purpose registers R20to R31are associated with twelve bits of the immediate field24.

FIG. 10is a flowchart showing an example of an operation of the CPU20that executes a computer program (an executable program) including the DBPUSH instruction. In step S21, the CPU20analyzes an operation code of an instruction fetched from the memory50. When the instruction decoded in step S21is the DBPUSH instruction (YES in step S22), the CPU20supplies a program counter (PC) value of the DBPUSH instruction to the trace unit25(step S23). The program counter (PC) is an instruction address register used in order to indicate an address in the memory at which an instruction to be executed next by the CPU20is stored. The PC value supplied to the trace unit25in step S23indicates an address of the DBPUSH instruction decoded in step S21. In steps S24to S26, the CPU20sequentially reads the general-purpose registers specified by the DBPUSH instruction and supplies the read register values and the register numbers of the general-purpose registers, to the trace unit25. The CPU20repeats steps S24to S26until all the general-purpose registers specified by the DBPUSH instruction have been read. On the other hand, if the instruction decoded in step S21is not the DBPUSH instruction (NO in step S22), the CPU20performs processing according to the decoded instruction (step S27).

Subsequently, hereinafter, a specific example of an operation of the CPU20when the CPU20decodes the DBPUSH instruction will be described with reference toFIG. 11. The instruction decode unit202notifies the control unit203of a notification DBPUSH indicating the DBPUSH instruction, an instruction address (PC value) PC of the DBPUSH instruction, and a plurality of register numbers specified by the DBPUSH instruction (or a register range defined by a top register number and a tail register number) REGISTER NOS. in response to decoding of the DBPUSH instruction. The control unit203generates a control signal indicating the DBPUSH instruction and supplies the control signal and the instruction address (PC value) of the DBPUSH instruction to the instruction execution unit205.

Furthermore, the control unit203assigns a register number to a general-purpose register file204in order to read a register value from the general-purpose register file204. The general-purpose register file204supplies a register value of the register number assigned from the control unit203to the instruction execution unit205. InFIG. 11, a signal line between the control unit203and the general-purpose register file204is branched and the register number is also supplied to the instruction execution unit205. Moreover, the control unit203has a multi-cycle sequencer2031. The reading of each of the general-purpose registers specified by the DBPUSH instruction is sequentially performed for each cycle. Therefore, the multi-cycle sequencer2031controls the reading of a plurality of register values from the general-purpose register file204in multiple cycles and controls issuing of a command to the instruction execution unit205.

The instruction execution unit205shown inFIG. 11has an ALU2051that performs arithmetic operation, logical operation, and the like, a latch2052that holds output data of the ALU2051, and latches2053to2056. The latches2053to2056are arranged in order to hold the control signal indicating the DBPUSH instruction, the instruction address (PC value), the register number, and the register value of the DBPUSH instruction. The instruction execution unit205holds, at the latches2053to2056, the control signal indicating the DBPUSH instruction, the instruction address (PC value), the register number, and the register value of the DBPUSH instruction, in an execution cycle of the DBPUSH instruction and outputs these data to the completion unit206in the next cycle. Namely, the instruction execution unit205does not supply, to the ALU2051, the register value outputted from the general-purpose register file204on the basis of the DBPUSH instruction. The ALU2051and the latch2052, which are shown by dashed lines inFIG. 11, indicate that these components are not used in order to execute the DBPUSH instruction.

The completion unit206receives, from the instruction execution unit205, the control signal indicating the DBPUSH instruction, the instruction address (PC value) of the DBPUSH instruction, the general-purpose register number, and the register value outputted from the general-purpose register file204on the basis of the DBPUSH instruction. The completion unit206detects that the reception of the instruction address (PC value), the register number, and the register value, from the instruction execution unit205is valid in response to reception of the control signal indicating the DBPUSH instruction. In addition, the completion unit206outputs, to the trace unit25, a DBPUSH trace valid signal, the instruction address (PC value), the register number, and the register value of the DBPUSH instruction. Here, the DBPUSH trace valid signal notifies the trace unit25of the fact that trace information including the instruction address, the register number, and the register value of the DBPUSH instruction is valid.

As understood from the above description, in the computer according to the present embodiment, in response to decoding of one DBPUSH instruction having a field indicating a plurality of registers, the CPU20operates so as to supply values of the registers specified by the DBPUSH instruction to the trace unit25. In addition, the trace unit25operates so as to output trace data including the values of the registers specified by the DBPUSH instruction in response to execution of the one DBPUSH instruction in the CPU20. The DBPUSH instruction can be used in order to output, as the trace data, values of a plurality of general-purpose registers implemented in the CPU20, and the values of the general-purpose registers are outputted as the trace data by the one DBPUSH instruction. Therefore, through the use of the computer2according to the present embodiment, a plurality of instructions is not required in order to output the values of the general-purpose registers as the trace data, and thus the program code size can be reduced.

In the present embodiment, a modification of the second embodiment described above will be described.FIG. 12is a block diagram showing a computer3according to the present embodiment and peripheral devices of the computer3. The computer3includes a CPU30and a trace unit35coupled to the CPU30. The entire configuration of the computer3is the same as the configuration example of the computer1of the first embodiment shown inFIG. 2orFIG. 5.

The basic operation of the computer3is the same as that of the computer2described in the second embodiment. Namely, in response to decoding of one DBPUSH instruction having a field indicating a plurality of registers, the CPU30operates so as to supply values of the registers specified by the DEPUSH instruction to the trace unit35. The trace unit35operates so as to output trace data including the values of the registers specified by the DBPUSH instruction in response to execution of the one DBPUSH instruction in the CPU30.

Furthermore, the computer3according to the present embodiment can reduce the data size of the trace data based on the DBPUSH instruction by the description and the operation as described below. That is, the CPU30is configured to supply a multi-cycle signal (hereinafter, referred to as a multi-cycle status signal) to the trace unit35in sequentially supplying the values of the registers specified by the DBPUSH instruction to the trace unit35. The multi-cycle status signal indicates that the CPU30executes a multi-cycle instruction. In addition, the trace unit35recognizes the multi-cycle status signal and determines that a plurality of register values based on one DBPUSH instruction are sequentially outputted while the multi-cycle status signal is being issued. Then, the trace unit35associates the instruction address (PC value) of the one DBPUSH instruction with an output of a plurality of register numbers and the register values based on the one DBPUSH instruction in the trace data. In other words, the trace unit35eliminates redundancy of the instruction address (PC value) of the DBPUSH instruction included in the trace data. Thereby, the number of pieces of data indicating the address of the DBPUSH instruction included in the trace data is reduced so that the number of pieces of data is smaller than the number of registers specified by the DBPUSH instruction.

Hereinafter, a specific example of an operation of the CPU30when the CPU30decodes the DBPUSH instruction will be described with reference toFIG. 13. The operation of the instruction decode unit302is the same as that of the instruction decode unit202inFIG. 11. The control unit303has the same configuration and function as those of the control unit203shown inFIG. 11. Furthermore, the control unit303operates so as to supply the multi-cycle status signal to the instruction execution unit305when executing the DBPUSH instruction.

The general-purpose register file304has the same configuration and function as those of the general-purpose register file204shown inFIG. 11. The instruction execution unit305also has the same configuration and function as those of the instruction execution unit205shown inFIG. 11. The ALU3051and the latches3052to3056correspond to the ALU2051and the latches2052to2056shown inFIG. 11. However, the latch3053latches the multi-cycle status signal in addition to the control signal indicating the DBPUSH instruction.

The completion unit306outputs, to the trace unit35, the DBPUSH trace valid signal, the instruction address (PC value), the register number, and the register value of the DBPUSH instruction in the same manner as the completion unit206shown inFIG. 11. Furthermore, in addition to these data, the control unit306supplies the multi-cycle status signal to the trace unit35.

Next, the data size reduction effect of the trace data caused by the computer3will be described with reference toFIGS. 14 and 15.FIG. 14is a timing chart showing trace information (trace information based on the DBPUSH instruction) supplied from the CPU30to the trace unit35.FIG. 14shows an example in which values of 32 registers R0to R31of register numbers0to31are outputted.

A waveform (A) inFIG. 14shows a clock signal. A waveform (B) inFIG. 14shows the DBPUSH trace valid signal. The high level of the DBPUSH trace valid signal means that an output of trace information from the CPU30is valid. A waveform (C) inFIG. 14shows the multi-cycle status signal. The high level of the multi-cycle status signal means that the trace information is related to a multi-cycle instruction.

A waveform (D) inFIG. 14shows an output of the instruction address (PC value). In the example ofFIG. 14, the instruction address (PC value) has the same value (0x4000) indicating the DBPUSH instruction while the multi-cycle status signal (waveform (C)) is at a high level. Waveforms (E) and (F) inFIG. 14show the register numbers and the register values, which are outputted based on the DBPUSH instruction. While the multi-cycle status signal (waveform (C)) is at a high level, the register numbers and the register values of the registers from the register R0to the register R31are sequentially outputted.

FIG. 15shows an example of trace data generated when the trace unit35receives the trace information shown inFIG. 14. In the example ofFIG. 15, only the trace data of the top register R0(the register number=0) includes the address (0x4000) of the DBPUSH instruction. However, the trace data of the register R1(the register number=1) does not include the address (0x4000) of the DBPUSH instruction. The trace data of the registers R2to R31not illustrated do not include the address (0x4000) of the DBPUSH instruction in the same manner as the trace data of the register R1. Repeated inclusion of the same instruction address indicating the same DBPUSH instruction in the trace data of a plurality of registers based on one DBPUSH instruction is redundant. Therefore, in the example ofFIG. 15, the address (0x4000) of the DBPUSH instruction is removed from the trace data of the registers R1to R31.

In the present embodiment, a modification of the first to the third embodiments described above will be described.FIG. 16shows a configuration example of a computer4according to the present embodiment. The computer4includes a CPU40and a trace unit45. The CPU40has the same configuration and function as those of the CPUs10,20, or30described in the first to the third embodiments. The trace unit45has the same configuration and function as those of the trace units15,25, or35described in the first to the third embodiments. Further, the trace unit45has a filter454for selectively outputting trace data of a specific DBTAG instruction or trace data of a specific DBPUSH instruction.

The trace controller451filters trace information received from the CPU40by the filter454, selects only trace information that coincides with a filter condition, and accumulates the trace information in a trace buffer452. In addition, the trace controller451writes, to the storage device60, the trace information which coincides with the filter condition and is accumulated in the trace buffer452, via an interface453.

Hereinafter, a configuration example of the filter454will be described with reference toFIGS. 17 to 19. The filter454shown inFIG. 17performs filtering using an instruction address (PC value). A filter value register4541stores a value of an address to be compared with the instruction address (PC value) in the trace information. A mask value register4542holds a mask value for each bit of the instruction address. In the example ofFIG. 17, 0 is set to values of bits to be compared and 1 is set to values of bits to be masked. The filter value register4541and the mask value register4542can be set from an external debug host via a debug communication port (for example, JTAG (Joint Test Action Group) port).

An equivalence gate4543is an XNOR gate. The equivalence gate4543compares bit by bit the instruction address (PC value) with the value of the filter value register4541, and outputs 1 when the two input bits have the same value and outputs 0 when the two input bits have different values. An OR gate4544compares bit by bit output the value of the equivalence gate4543with the value of the mask value register4542and calculates logical OR for each bit. An AND circuit4545calculates logical AND of all bits of the output value from the OR gate4544. An output from the AND circuit4545indicates a matching result, and an output value of 1 indicates matching and an output value of 0 indicates mismatching.

InFIG. 18, a filtering using the immediate value included in the trace information of the DETAG instruction described in the first embodiment is performed. A filter value register4546stores a value to be compared with the immediate value in the trace information. A mask value register4547holds a mask value for each bit of the immediate value. In the example ofFIG. 18, 0 is set to values of bits to be compared and 1 is set to values of bits to be masked. The filter value register4546and the mask value register4547can be set from an external debug host via a debug communication port (for example, JTAG (Joint Test Action Group) port).

The configuration example ofFIG. 18is the same as that ofFIG. 17. Namely, the equivalence gate4548compares bit by bit the immediate value in the trace information with the value of the filter value register4546, and outputs1when the two input bits have the same value and outputs0when the two input bits have different values. An OR gate4549compares bit by bit the output value of the equivalence gate4548with the value of the mask value register4547and calculates logical OR for each bit. An AND circuit4550calculates logical AND of all bits of output values from the OR gate4549. An output from the AND circuit4550indicates a matching result. An output value of 1 indicates matching and an output value of 0 indicates mismatching.

A filter454shown inFIG. 19performs filtering using the register number included in the trace information of the DBPUSH instruction described in the second and the third embodiments. A filter value register4551stores a value to be compared with the register number in the trace information. Each bit of the filter value register4551is associated with any of register numbers. For example, when the filter value register4551is a 32-bit register, the 32 bits are sequentially associated with 32 registers R0to R31from the least significant bit of the register.

A bit conversion circuit4552receives the register number in binary notation in the trace information and generates output data in which 1 is set to bits corresponding to the register number in decimal notation and 0 is set to the other bits. For example, a case is considered in which there are 32 general-purpose registers and the register numbers indicated by the trace information is 0 to 31. When the register number is 0, the bit conversion circuit4552outputs 32-bit data in which all bits are set to 0. When the register number is 1, the bit conversion circuit4552outputs 32-bit data in which the least significant bit is set to 1 and all the other 31 bits are set to 0. When the register number is 31, the bit conversion circuit4552outputs 32-bit data in which the most significant bit is set to 1 and all the other 31 bits are set to 0.

An AND gate4553compares bit by bit the output values of the bit conversion circuit4552with the values of the filter value register4551and calculates logical AND for each bit. An OR circuit4554calculates logical OR of all bits of output values from the AND gate4553. An output from the OR circuit4554indicates a matching result. An output value of 1 indicates matching and an output value of 0 indicates mismatching.

The present embodiment can select and output only specific trace data. For example, the present embodiment can select and output only trace data in which the instruction address (PC value) coincides with a specific value or a specific range. Further, the present embodiment can select and output only trace data in which the immediate value of the DBTAG instruction coincides with a specific value or a specific range. Furthermore, the present embodiment can select and output only trace data in which a register number among a plurality of register values outputted based on the DBPUSH instruction coincides with a specific value or a specific range.

In the present embodiment, a device to generate an executable program executed by the computers according to the first to the fourth embodiments described above will be described.FIG. 20is a block diagram showing a configuration example of a computer system70according to the present embodiment. The computer system70includes a processor71, a display device72, an input device73, and a memory75. The processor71performs processing for generating an executable program759from a source code756by reading and executing computer programs such as an operating system751, a compiler752, an assembler753, and a linker754, which are stored in the memory75. The processor71includes, for example, one or a plurality of CPUs.

The display device72is a device that provides visual information to a user. The display device72is, for example, a liquid crystal display, an organic EL (electroluminescence) display, or a CRT (Cathode Ray Tube) display. The input device73is a device that receives operation information of the user. For example, the input device73is a keyboard, a pointing device (mouse, trackball, touch pad, and the like), a touch panel, or a combination of these devices.

The memory75may be configured by a volatile memory, a non-volatile memory, or a combination of these. The volatile memory is, for example, an SRAM, a DRAM (Dynamic Random Access Memory), or a combination of these. The non-volatile memory is, for example, a mask ROM, a programmable ROM, a flash memory, a hard disk drive, or a combination of these. In addition, the memory75may include a storage arranged away from the processor71. In this case, the processor71may access the memory75via a communication interface not illustrated.

FIG. 21is a conceptual diagram showing a process of converting source code into an executable program. The compiler752converts the source code756into assembly code757. The source code756includes one or a plurality of source code files. The assembly code757includes one or a plurality of assembly code files. The assembler753converts the assembly code757into object code758. The object code758includes one or a plurality of object code files. Meanwhile, the functions of the compiler752and the assembler753inFIG. 21may be collectively referred to as a compiler. In other words, the processing of converting the source code756into the object code758may be referred to as compiling.

The linker754generates one executable program759by linking the object code758with a run-time library755.

Subsequently, hereinafter, compiling processing of the compiler752will be described in further detail. The compiler752operates so as to insert, into the assembly code757, the DBTAG instruction having the immediate field indicating an identifier of a function, a thread, a process, or a task, included in the source code756. Therefore, the assembly code757includes (a) an assembly code section for performing processing of the function, the thread, the process, or the task included in the source code756and (b) the DBTAG instruction associated with the function, the thread, the process, or the task. The DBTAG instruction may be arranged immediately before, immediately after, or in the assembly code section corresponding to the function, the thread, the process, or the task. The detail of the DBTAG instruction has already been described in the first embodiment, and thus the redundant description is omitted.

The compiler752may further insert the DHPUSH instruction described in the second and the third embodiments into the assembly code757, in order to trace values of a plurality of registers that stores a plurality of arguments or a plurality of return values of the function, the thread, the process, or the task, included in the source code756.

FIG. 22is a flowchart showing an example of compiling processing according to the present embodiment. In step S31, the compiler752receives the source code756. In step S32, the compiler752detects the function in the source code756. In step S33, the compiler752assigns an identifier to the detected function. In step S34, the compiler generates an assembly code section corresponding to the detected function.

In step S35, the compiler752inserts the DBTAG instruction having the immediate field indicating an identifier of the function immediately before and immediately after the assembly code section generated in step S34. Meanwhile, in step S35, the DBTAG instruction may be inserted either immediately before or immediately after the assembly code section. In addition, the DBTAG instruction may be arranged in the assembly code section, for example, at the top position or the tail position of the assembly code section.

In step S36, the compiler752inserts the DBPUSH instruction including a field that specifies a plurality of general-purpose registers storing an argument of the detected function, immediately before the assembly code section generated in step S34. The DBPUSH instruction may be arranged at the top position of the assembly code section.

In step S37, the compiler752inserts the DBPUSH instruction including a field that specifies a plurality of general-purpose registers storing a return value of the detected function, immediately after the assembly code section generated in step S34. The DBPUSH instruction may be arranged at the tail position of the assembly code section.

The compiler752repeatedly performs processing of steps S32to S37until the last function in the source code756is processed (step S38).

Meanwhile, the flowchart inFIG. 22shows an example of the compiling processing that generates both the DBTAG instruction for tracing an identifier of a function and the DBPUSH instruction for tracing an argument and a return value of a function. As shown inFIG. 22, it is possible to trace execution of functions in the computer1in detail by using a combination of the DBTAG instruction and the DBPUSH instruction. However, the generation of the DBTAG instruction and the generation of the DBPUSH instruction may be performed independently from each other and the DBTAG instruction and the DBPUSH instruction may be used independently from each other. For example, the compiling processing according to the present embodiment may generate the DBTAG instruction for tracing an identifier of a function, a thread, or the like, and need not generate the DBPUSH instruction for tracing an argument and a return value of a function, a thread, or the like. On the contrary, the compiling processing according to the present embodiment may generate the DBPUSH instruction for tracing an argument and a return value of a function, a thread, or the like, and need not generate the DBTAG instruction for tracing an identifier of a function, a thread, or the like. The compiling processing according to the present embodiment may generate the DBTAG instruction for tracing an identifier of a function for specific functions and generate the DBPUSH instruction for tracing an argument and a return value of a function for other specific functions.

According to the computer system70or the compiler752according to the present embodiment, it is possible to use the DBTAG instruction described in the first embodiment for applications outputting, as trace data, an identifier of a function, a thread, a process, or a task. Furthermore, according to the computer system70or the compiler752, it is possible to use the DBPUSH instruction described in the second and the third embodiments for applications outputting, as trace data, a plurality of arguments or a plurality of return values of a function, a thread, a process, or a task.

The plural embodiments described above may be properly combined and carried out.

The computers1to4described in the first to the fourth embodiments may have a multi-core configuration having a plurality of CPUs (CPU cores, MPU cores, or processor cores). In a computer of the multi-core configuration, the transition of function, thread, process, or task is further complicated, and thus the use of the DBTAG instruction and the DBPUSH instruction described in the first to the fourth embodiments may be further more effective than in a single-core configuration.

Moreover, the embodiments described above are only examples of applications of technical ideas obtained by the inventors of the present invention. Namely, the technical ideas are not limited to the embodiments described above, and it is needless to say that various modifications are possible.

For example, the technical ideas obtained by the present inventors include the embodiments A1 to A19 described below.

A compiling method including

reading source code from a memory, and

analyzing the source code and converting the source code into assembly code,

in which the converting includes inserting, into the assembly code, (a) an assembly code section for executing processing of a function, a thread, a process, or a task, included in the source code and (b) a first assembly instruction having an immediate field indicating an identifier of the function, the thread, the process, or the task into the assembly code.

The compiling method described in the embodiment A1, in which when executable program code based on the assembly code is executed by a CPU (Central Processing Unit), the first assembly instruction causes the CPU to operate so as to supply the identifier indicated in the immediate field to a trace unit coupled to the CPU.

The compiling method described in the embodiment A1 or A2, in which the source code does not include an explicit instruction corresponding to the first assembly instruction.

The compiling method described in any one of the embodiments A1 to A3, in which the converting further includes generating the first assembly instruction from the source code that does not include an explicit instruction corresponding to the first assembly instruction in response to detection of the function, the thread, the process, or the task.

The compiling method described in any one of the embodiments A1 to A4, in which the inserting includes arranging the first assembly instruction immediately before the assembly code section, in the assembly code section, or immediately after the assembly code section.

The compiling method described in any one of the embodiments A1 to A5, in which the first assembly instruction does not include a register field for specifying a register operand.

The compiling method described in any one of the embodiments A1 to A6, in which the first assembly instruction includes only one instruction.

The compiling method described in any one of the embodiments A1 to A7,

in which the converting further includes inserting a second assembly instruction into the assembly code, and

the second assembly instruction has a field indicating a plurality of registers that store an argument or a return value of the function, the thread, the process, or the task.

The compiling method described in the embodiment A8, in which when executable program code based on the assembly code is executed by a CPU (Central Processing Unit), the second assembly instruction causes the CPU to operate so as to supply values of the registers to a trace unit coupled to the CPU.

A program for causing a computer to perform the compiling method described in any one of the embodiments A1 to A9.

A compiling device including

a processor configured so as to execute a compiling procedure,

in which the compiling procedure includes

reading source code from a memory, and

analyzing the source code and converting the source code into assembly code, and

the converting includes inserting, into the assembly code, (a) an assembly code section for executing processing of a function, a thread, a process, or a task, included in the source code and (b) a first assembly instruction having an immediate field indicating an identifier of the function, the thread, the process, or the task.

The compiling device described in the embodiment A11, in which when executable program code based on the assembly code is executed by a CPU (Central Processing Unit), the first assembly instruction causes the CPU to operate so as to supply the identifier indicated in the immediate field to a trace unit coupled to the CPU.

The compiling device described in the embodiment A11 or A12, in which the source code does not include an explicit instruction corresponding to the first assembly instruction.

The compiling device described in any one of the embodiments A11 to A13, in which the converting further includes generating the first assembly instruction from the source code that does not include an explicit instruction corresponding to the first assembly instruction in response to detection of the function, the thread, the process, or the task.

The compiling device described in any one of the embodiments A11 to A14, in which the inserting includes arranging the first assembly instruction immediately before the assembly code section, in the assembly code section, or immediately after the assembly code section.

The compiling device described in any one of the embodiments A11 to A15, in which the first assembly instruction does not include a register field for specifying a register operand.

The compiling device described in any one of the embodiments A11 to A16, in which the first assembly instruction includes only one instruction.

The compiling device described in any one of the embodiments A11 to A17, in which the converting further includes inserting a second assembly instruction into the assembly code, and the second assembly instruction has a field indicating a plurality of registers that store an argument or a return value of the function, the thread, the process, or the task.

The compiling device described in the embodiment A18, in which when executable program code based on the assembly code is executed by a CPU (Central Processing Unit), the second assembly instruction causes the CPU to operate so as to supply values of the registers to a trace unit coupled to the CPU.