Semiconductor dies having substrate shunts and related fabrication methods

Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer. The die structure also includes a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a doped region in the first layer that is electrically connected to the handle layer of semiconductor material, and a body region underlying the doped region that is contiguous with at least a portion of the first layer underlying a semiconductor device.

TECHNICAL FIELD

Embodiments of the subject matter described herein relate generally to semiconductor devices and related fabrication methods, and more particularly, to protecting semiconductor devices from electrostatic discharge by providing shunts that are distributed throughout a semiconductor die.

BACKGROUND

Modern electronic devices, and particularly, integrated circuits, are at risk of damage due to electrostatic discharge (ESD) events. During an ESD event, a voltage may be provided to one or more terminals of an electronic device that exceeds the design voltage of the device, which could impair subsequent operation of the device. For example, a voltage at a terminal of an electronic device during an ESD event may exceed the breakdown voltage of one or more components of the device, and thereby potentially damage those components. Accordingly, electronic devices include discharge protection circuitry that provides protection from excessive voltages across electrical components during ESD events.

Charged Device Model (CDM) testing is used to simulate an ESD event where the device carries an electrostatic charge and discharges due to contact with one of the terminals of the device. In some situations, the ESD protection circuitry may not adequately protect the core device circuitry from the relatively high peak current and/or voltage transients occurring during a CDM-type ESD event. When core device circuitry is damaged during ESD testing, substantial analysis and modifications to the core device circuitry are often required to adequately address the ESD event, which, in turn, increases development costs.

DETAILED DESCRIPTION

Embodiments of the subject matter described herein relate to semiconductor dies that include shunting regions that are distributed throughout the die and electrically connected to the substrate (or alternatively, the substrate voltage) to provide resistive paths between the substrate and the body semiconductor material underlying semiconductor devices fabricated on the die. By providing multiple resistive paths which are effectively in parallel between the substrate and the body regions, the effective substrate resistance across the die is thereby reduced. As a result, a greater percentage of the current during a CDM-type discharge event flows through the shunting regions to/from the substrate, thereby reducing the percentage of the discharge current through (or the voltage across) the semiconductor devices. As described in greater detail below, in some embodiments, the shunting regions are formed in the upper (or active) layer of a silicon-on-insulator (SOI) substrate and electrically connected to the handle layer of the SOI substrate, with the shunting regions being adjacent to semiconductor devices formed in the upper layer of the SOI substrate. An upper portion of a respective shunting region is laterally isolated from an adjacent semiconductor device by a shallow isolation region, while the underlying body region of the shunting region is integral with the body region underlying an adjacent semiconductor device. As a result, when the electrical potential (or voltage) of the body of an adjacent semiconductor device increases during an ESD event, a portion of that electrical potential (and thereby, a corresponding portion of the discharge current) is distributed through the body portion of the adjacent shunting region and to the handle layer via that adjacent shunting region, thereby reducing the voltage difference across electrodes of the semiconductor device.

Turning now toFIG. 1, in an exemplary embodiment, a device package100(or integrated circuit) includes a semiconductor die structure102and a plurality of input and/or output interfaces104,106. The semiconductor die structure102includes one or more device regions110having one or more semiconductor devices fabricated thereon, such as, for example, transistors, diodes, memory elements, sensors, or the like. In exemplary embodiments, the semiconductor die structure102is realized as a diced portion of a SOI substrate (or wafer) that includes an upper (or active) layer of semiconductor material having the semiconductor devices formed therein that overlies a buried layer of dielectric material, which, in turn, overlies a handle layer of semiconductor material, as described in greater detail below. The semiconductor devices fabricated on the semiconductor die102may be interconnected or otherwise configured to provide a desired functionality for the device package100, as will be appreciated in the art. The I/O interfaces104,106generally represent the physical interfaces for creating electrical connections to the semiconductor devices and/or any other components on the die102for transmitting electrical signals between the components on the die102and one or more external electrical components or systems.

It should be understood thatFIG. 1is a simplified representation of the device package100and the die structure102for purposes of explanation, and is not intended to limit the subject matter described herein in any way. In this regard, the semiconductor devices formed on the device regions110(and their various physical features) are not depicted inFIG. 1because the subject matter described herein is not limited to any particular type or configuration of semiconductor devices fabricated on the device regions110of the die structure102. However, for purposes of explanation, the subject matter may be described herein in the context of one or more transistor devices being fabricated on the device regions110. In practice, the semiconductor die structure102may include any number or combination of semiconductor devices and/or device regions110arranged with any sort of layout or floorplan. Additionally, althoughFIG. 1depicts the I/O interfaces104,106as pins that protrude or otherwise extend from the device package100, in other embodiments, the I/O interfaces104,106may be realized as any sort of lead, pad, terminal, wire, or other physical interfaces capable of establishing an electrical connection to the components on the die102. That is, the I/O interfaces104,106are not limited to any particular type or configuration of terminals or interconnections. For example, the I/O interfaces104,106may be realized as separate pads formed in a surface of the semiconductor die structure102or separate lead portions of a lead frame (e.g., for a flat no-leads device package100).

Still referring toFIG. 1, in exemplary embodiments, the semiconductor die102includes a plurality of shunting regions108that are distributed throughout the semiconductor die102among the semiconductor devices and/or device regions110to provide resistive paths between a substrate reference voltage for the semiconductor die102and body regions of the active layer that underlie the semiconductor devices on the device regions110. In exemplary embodiments, each of the shunting regions108is electrically connected to the handle layer of the die102to provide a resistive path from/to the body regions of the semiconductor device(s) adjacent to that respective shunting region108to/from the substrate reference voltage. For example, the first interface104of the device package100may be electrically connected to an electrode terminal of one or more of the semiconductor devices on the device region110of the die102while the second interface106of the device package100is configured to receive the substrate reference voltage and is electrically connected to the handle layer of semiconductor material for the die102. Depending on the embodiment and the type of semiconductor device(s) formed on the device region(s)110, the electrode terminal may be realized as a gate terminal, a drain terminal, a source terminal, a base terminal, a collector terminal, an emitter terminal, an anode terminal, a cathode terminal, or the like. The shunting regions108may be electrically connected to the substrate interface106at an edge of the die102, and thereby, electrically connected to the handle layer of semiconductor material and/or the substrate reference voltage. In exemplary embodiments, the density of shunting regions108(i.e., the number of shunting regions per unit of die area) is chosen based on a desired amount of ESD protection, which may vary depending on the needs of a particular application. In accordance with one or more embodiments, the shunting regions108are substantially identical to one another and spaced equidistant from neighboring shunting regions108so that they are uniformly (or evenly) distributed throughout the die102. In other embodiments, the shunting regions108may be different from one another (e.g., occupying different amounts of die area per shunting region) and/or be distributed non-uniformly throughout the die102(e.g., to accommodate various floorplans or layouts). For example, multiple shunting regions108may be aligned in a row (or column) adjacent to one another so that underlying body regions of semiconductor material of adjacent shunting regions108are contiguous with one another, in a similar manner as described in greater detail below in the context of the shunting region408and the device regions410ofFIGS. 4-8.

FIG. 2depicts an exemplary embodiment of a shunting region200suitable for use as one or more of the shunting regions108on the semiconductor die102encapsulated in the device package100ofFIG. 1. The shunting region200includes a doped contact region210formed in an upper (or active) layer of semiconductor material206of a semiconductor substrate201, with the doped contact region210being circumscribed or otherwise laterally enclosed by an isolation region212of dielectric material214formed in the upper layer of semiconductor material206. The substrate201includes a handle layer of semiconductor material202that is isolated from the upper layer of semiconductor material206by a buried layer of dielectric material204that overlies the handle layer of semiconductor material202. As described above in the context ofFIG. 1, the handle layer of semiconductor material202is electrically connected to a device package interface208(e.g., interface106of device package100) to receive a reference voltage for the substrate201. As illustrated inFIG. 2, for some instances of the shunting region200, an electrical connection220is provided (e.g., using overlying metallization and/or layers) between the shunting contact region210and the handle layer of semiconductor material202, for example, by providing the electrical connection220between the shunting contact region210and the package interface208, so that the shunting contact region210is electrically connected to the handle layer of semiconductor material202and/or the substrate reference voltage at the package interface208via the electrical connection220. In practice, a plurality of shunting regions200may be distributed throughout a die, wherein some instances of the shunting region200may be electrically connected to one another via the underlying body region207of semiconductor material206being contiguous among the adjacent shunting regions200, in which case not all of the instances of the shunting region200include an external electrical connection (e.g., electrical connection220) to its contact region210.

In exemplary embodiments, the shunting contact region210is realized as a doped region of the upper layer of semiconductor material206having a dopant concentration that is greater than a dopant concentration of the underlying body region207of semiconductor material206. For example, as described in greater detail below, in accordance with one or more embodiments, the upper layer of semiconductor material206is realized as in-situ doped epitaxially grown silicon material having a dopant concentration less than about 1×1017/cm3, and in some embodiments, in the range of about 1×1015/cm3to about 5×1015/cm3. The shunting contact region210is realized by implanting ions having a dopant concentration greater than about 1×1018/cm3into the exposed portion of the semiconductor material206that is circumscribed by the isolation region212. In some embodiments, the dopant concentration of the shunting contact region is in the range of about 1×1019/cm3to about 1×1021/cm3. In exemplary embodiments, the shunting contact region210has the same conductivity type as the underlying body region207of semiconductor material206. In alternative embodiments, the conductivity of the shunting contact region210may be opposite that of the underlying body region207of semiconductor material206.

As described in greater detail below, the isolation region212is realized as a shallow isolation region that is formed by shallow trench isolation (STI) or another suitable isolation process so that the depth of the isolation region212relative to the upper surface of the substrate201is less than the thickness of the upper layer of semiconductor material206. In exemplary embodiments, the depth of the shunting contact region210after diffusion is less than or equal to the depth of the shallow isolation region212, so that the shallow isolation region212laterally encloses the shunting contact region210to laterally isolate the shallow isolation region212from adjacent semiconductor devices. For example, as described in greater detail below, in accordance with one or more embodiments, the depth of the shallow isolation region212is in the range of about 0.05 microns to about 1 micron, and more preferably, within the range of 0.2 microns to 0.5 microns, while the depth of the shunting contact region210is in the range of about 0.05 microns to about 0.3 microns. In this regard, the shunting contact region210is located at or near the surface of the upper layer of semiconductor material206. In accordance with one or more embodiments, the shunting contact region210is formed concurrently to forming an electrode contact region for one or more semiconductor devices fabricated on the semiconductor substrate, as described in greater detail below. By virtue of the relatively high resistivity of the underlying semiconductor material206in combination with the depth of the shunting contact region210being less than the depth of the shallow isolation region212, the shunting region200does not undesirably impact performance of adjacent semiconductor devices during normal operation (e.g., in the absence of an ESD event).

FIG. 3depicts another embodiment of a shunting region300suitable for use as one or more of the shunting regions108on the semiconductor die102encapsulated in the device package100ofFIG. 1. In a similar manner as described above in the context of the shunting region200ofFIG. 2, the shunting region300includes a doped contact region310having a dopant concentration that is greater than the dopant concentration of the upper layer of semiconductor material306of the semiconductor substrate301, and the doped contact region310is circumscribed or otherwise laterally enclosed by a shallow isolation region312of dielectric material314having a depth relative to the upper surface of the substrate301that is less than the thickness of the upper layer of semiconductor material306but greater than the depth of the doped contact region310.

In the embodiment ofFIG. 3, a deep isolation region320is formed or otherwise provided within the shunting region300, wherein the deep isolation region320includes an interior (or inner) region of conductive material324that is circumscribed or otherwise laterally enclosed by a region of dielectric material322. The depth of the conductive material324of the deep isolation region320is greater than or equal to the combined thickness of the upper layer of semiconductor material306and the buried layer of dielectric material304so that the conductive material324extends through an opening in the buried layer of dielectric material304to contact or otherwise abut the handle layer of semiconductor material302. Thus, the conductive material324of the deep isolation region320is electrically connected to the handle layer of semiconductor material302. As illustrated inFIG. 3, an electrical connection330is provided (e.g., using overlying metallization and/or via layers) between the shunting contact region310and the conductive material324, so that the shunting contact region310is electrically connected to the handle layer of semiconductor material302and/or the substrate reference voltage at the package interface308via the conductive material324.

As described in greater detail below, in accordance with one or more embodiments, the conductive material324is realized as a doped semiconductor material having a dopant concentration that is greater than the dopant concentration of the upper layer semiconductor material306and greater than the dopant concentration of the handle layer semiconductor material302to provide a relatively low resistance path to the handle layer semiconductor material302. For example, in one embodiment, the dopant concentration of the conductive material324is greater than about 1×1017/cm3, while the dopant concentration of the upper layer of semiconductor material306is in the range of about 1×1015/cm3to about 1×1017/cm3, and the dopant concentration of the handle layer of semiconductor material302is in the range of about 1×1015/cm3to about 1×1017/cm3. In some embodiments, the dopant concentration of the conductive material324is in the range of about 1×1019/cm3to about 1×1021/cm3. In one or more embodiments, the dopant concentration of the conductive material324is also less than the dopant concentration of the contact region310. In exemplary embodiments, the conductive material324has the same conductivity type as the handle layer semiconductor material302.

Referring to again toFIG. 1and with reference toFIGS. 2-3, in some embodiments, the semiconductor die structure102may include one or more instances of the shunting region200in combination with one or more instances of the shunting region300. For example, a shunting region108at an interior location within the semiconductor die structure102may be realized as shunting region300with one or more shunting regions108adjacent to and/or proximate that shunting region being realized as shunting region200, with the electrical connection220being provided between those respective instances of shunting region200and the shunting contact region310of that interior instance of the shunting region300rather than connecting those instances of shunting region200at the edge of the semiconductor die structure200. Again, practical embodiments of the semiconductor die structure102may include any number or combination of shunting region200and shunting region300to suit the needs of a particular device package and/or floorplan.

FIGS. 4-8illustrate methods for fabricating an exemplary semiconductor die structure400suitable for use as the semiconductor die102in the device package100ofFIG. 1in accordance with one or more exemplary embodiments. Various steps in the manufacture of semiconductor devices are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. As described above in the context ofFIG. 1, in practice, the semiconductor die structure400may include multiple different semiconductor devices fabricated on a device region410; however, for clarity and ease of explanation, and without limitation, the subject matter may be described herein using the singular form when referring to a semiconductor device fabricated on the device region410of the semiconductor die structure400. Furthermore, whileFIGS. 4-8depict the fabrication of the shunting region300ofFIG. 3, fabrication of the shunting region200ofFIG. 2may be achieved in an equivalent manner but without the fabrication of the deep isolation region420(or the connection thereto) described below in the context ofFIGS. 6 and 8.

Referring now toFIG. 4, in exemplary embodiments, the die structure400is fabricated from a SOI substrate401having a handle (or support) layer of semiconductor material402, a buried layer of dielectric material404on or otherwise overlying the handle layer semiconductor material402, and an upper layer of semiconductor material406on or otherwise overlying the buried layer semiconductor material404. As described in greater detail below, in exemplary embodiments, the upper layer semiconductor material406is utilized to fabricate semiconductor devices thereon, and accordingly, for convenience, but without limitation, the upper layer may alternatively be referred to herein as the active layer. In an exemplary embodiment, the semiconductor material402,406of each of the layers is realized as a silicon material, wherein the term “silicon material” is used herein to encompass the relatively pure silicon materials typically used in the semiconductor industry as well as silicon admixed with other elements such as germanium, carbon, and the like. Alternatively, one or more of the layers of semiconductor material402,406may be realized as germanium, gallium arsenide, and the like, and/or one or more of the layers of semiconductor material402,406may include layers of different semiconductor materials. In accordance with one embodiment, the buried layer404is realized as an oxide layer formed in a subsurface region of the semiconductor substrate401, also known as a buried oxide (BOX) layer. For example, the buried layer dielectric material404may be formed by oxidizing a wafer of semiconductor material which is then bonded to another wafer or layer of semiconductor material to provide a buried layer of oxide material between a handle layer402and an active layer406. In exemplary embodiments, the handle layer402and the active layer406are each lightly doped. For example, the active layer406may be realized as an in-situ doped epitaxially-grown silicon material having a dopant concentration in the range of about 1×1015/cm3to about 5×1015/cm3, while the handle layer402is realized as a silicon material having a dopant concentration in the range of about 1×1015/cm3to about 5×1015/cm3. In one embodiment, the active layer semiconductor material406is realized as P-type epitaxial silicon material and the handle layer402is realized as N-type silicon material. In alternative embodiments, the active layer semiconductor material406and the handle layer semiconductor material402may have the same conductivity type as one another, that is, the active layer semiconductor material406may be realized as an N-type epitaxial silicon material and/or the handle layer semiconductor material402may be realized as a P-type silicon material. That said, for purposes of explanation, the subject matter will be described herein in the context of a P-type active layer semiconductor material406and an N-type handle layer semiconductor material402.

Referring now toFIGS. 5-6, in exemplary embodiments, fabrication of the die structure400continues by performing one or more fabrication process steps to form or otherwise fabricate one or more semiconductor devices (or components thereof) on a device region410of the substrate401adjacent to a shunting region408(e.g., shunting region200or shunting region300). Various well known semiconductor fabrication process steps, such as photolithography, etching, ion implantation, deposition, and the like, may be performed to fabricate the semiconductor devices (or components thereof) on the device region410of the substrate401. For example, the shunting region408and other portions of the active layer406may be masked with an implantation mask, and ions having a desired conductivity-determining impurity type and dopant concentration may be implanted in the active layer406using the implantation mask to form a well region412for a semiconductor device in the device region410, such as a field-effect transistor (FET). For example, a P-type well region412for an N-type field-effect transistor may be formed by implanting P-type ions, such as boron ions, with a dopant concentration that is greater than the dopant concentration of the P-type epitaxial semiconductor material406, and preferably in some embodiments, the dopant concentration of the P-well region412is within the range of about 1×1016/cm3to about 1×1019/cm3.

In the illustrated embodiment, prior to forming the well region412, shallow isolation regions414,416,418of a dielectric material415are formed in the upper portions of the shunting region408and the device region410by performing shallow trench isolation (STI). To form the shallow isolation regions414,416,418, interior portions of the shunting region408and the device region410are masked with a masking material that is patterned to expose the active layer406about the periphery of the shunting region408and the device region410. The exposed portions of the active layer406are then etched to a desired depth (which is less than the thickness of the active layer406), and a dielectric material415, such as an oxide material, may be deposited (or grown) to a thickness greater than or equal to a depth of the trenches to fill the trenches and subsequently planarized to obtain shallow isolation regions414,416,418having upper surfaces substantially aligned with the upper surfaces of the surrounding active layer406. In accordance with one or more exemplary embodiments, the depth of the shallow isolation regions414,416,418is in the range of about 0.05 microns to about 1 micron, however, it will be appreciated that the depth of the shallow isolation regions414,416,418is not constrained to any particular depth (or range thereof) and the depth may be adjusted to suit the needs of a particular application and/or fabrication process.

Turning now toFIG. 6, after forming the shallow isolation regions414,416,418, fabrication of the die structure400continues by performing deep trench isolation (DTI) to provide a deep isolation region420in the shunting region408that includes an outer dielectric material422and an inner conductive material424that extends through openings in the active layer406and the buried layer404to contact the handle layer402and establish an electrical connection between the inner conductive material424and the handle layer402. The deep isolation region420is formed at or near an edge of the shunting region408in a manner that allows at least a portion of the active layer semiconductor material406of the shunting region408proximate or otherwise adjacent to the device region410to maintain contact or contiguity with the active layer semiconductor material406of the device region410. Fabrication of the deep isolation region420may be achieved by masking the semiconductor substrate401with a masking material, patterning the masking material to expose the portion of the shallow isolation region414and/or active layer semiconductor material406to be utilized for the deep isolation region420, etching the exposed portions of the shallow isolation region414and the active layer semiconductor material406using the remaining masking material as an etch mask to form a deep trench that exposes the underlying buried layer dielectric material404. For example, a hard mask including a nitride material may be patterned and used as an etch mask while etching the exposed portions of the shallow isolation region414and the active layer semiconductor material406by reactive ion etching (RIE) with one or more anisotropic etchants and stopping on the buried layer dielectric material404.

After forming the deep trench, fabrication of the deep isolation region420may continue by forming a layer of dielectric material422in the trench, for example, by oxidizing the exposed surfaces of the active layer semiconductor material406(e.g., by thermal oxidation or chemical oxidation) to grow a layer of oxide material on the exposed surfaces, or alternatively, by conformably depositing a layer of dielectric material422overlying the substrate401. In exemplary embodiments, the dielectric material422is formed to a thickness in the range of about 200 nm to about 1000 nm, however, it will be appreciated that the thickness of the dielectric material422may be adjusted to provide a desired isolation or otherwise accommodate the voltage range for a particular application. In this regard, the dielectric material422may fill the deep trench only partially in some embodiments. After forming the dielectric material422, fabrication of the deep isolation region420continues by anisotropically etching the dielectric material422and/or the exposed buried layer dielectric material404in the interior (or central) portion of the deep trench to form a voided region within the deep trench that extends through the buried layer404and exposes the underlying handle layer semiconductor material402. After forming the voided region, fabrication of the deep isolation region420is completed by forming a layer of conductive material424in the voided region of the trench. The conductive material424abuts or otherwise contacts the handle layer semiconductor material402to provide an electrical connection to the handle layer semiconductor material402. In accordance with one or more embodiments, the conductive material424is realized as a polysilicon material that is doped so that it has the same conductivity type as the underlying handle layer402. For example, a layer of a polysilicon material or another conductive material may be conformably deposited overlying the substrate401by chemical vapor deposition (CVD) or another deposition process to a thickness chosen such that the conductive material424fills the voided region of the trench to a minimum thickness (or height) that meets or exceeds the thickness (or height) of the active layer406(e.g., a “flush” fill or overfill). In one or more exemplary embodiments, the conductive material424is in-situ doped with N-type ions, such as phosphorous ions, to provide a N-type conductive material424that contacts the N-type handle layer402. In an exemplary embodiment, the dopant concentration of the conductive material424is greater than the dopant concentration of the handle layer402, and preferably within the range of about 1×1019/cm3to about 1×1021/cm3to provide the electrical connection to the handle layer402with relatively low resistance.

After forming the conductive material424, the fabrication process continues by planarizing the conductive material424and/or the dielectric material422(e.g., by chemical-mechanical planarization (CMP) or the like) to uniformly remove any excess portions of the conductive material424and/or the dielectric material422across the semiconductor substrate401until reaching the upper surface of the active layer semiconductor material406. Thereafter, the shunting region408and other portions of the active layer406may be masked with an implantation mask while the well region412is formed in the device region410by implanting ions with a dopant concentration that is greater than the dopant concentration of the epitaxial semiconductor material406into the exposed epitaxial semiconductor material406between shallow isolation regions416,418as described above, resulting in the die structure400ofFIG. 6after ion diffusion and removal of the implantation mask.

Referring now toFIG. 7, in an exemplary embodiment, the fabrication of the die structure400continues with various semiconductor device fabrication process steps being performed to fabricate one or more semiconductor devices on the device region410. For example, a gate structure430for a transistor may be formed overlying at least an interior portion of the well region412in a conventional manner, for example, by forming a gate dielectric material432overlying the semiconductor substrate401, forming a conductive gate electrode material434overlying the gate dielectric material432, and anisotropically etching the gate dielectric material432and conductive gate electrode material434to form the gate structure430. After forming the gate structure430, fabrication of the transistor may continue by forming doped electrode contact regions436,438,440about the gate structure430. In exemplary embodiments, concurrently to forming an electrode contact region440that has the same conductivity as the active layer semiconductor material406, a doped contact region442is concurrently formed in an interior portion of the active layer406of the shunting region408between the shallow isolation regions414,416to provide an electrical contact to the underlying body region443of active layer semiconductor material406of the shunting region408that is integral or otherwise contiguous with the body region (e.g., well region412) of the active layer semiconductor material406of the device region410. As described above and in greater detail below, the doped contact region442is utilized to electrically connect the active layer semiconductor material406of the shunting region408to the handle layer semiconductor material402(e.g., via the conductive material424of the deep isolation region420or another electrical connection), and thereby, provide a resistive path (or connection) to the global substrate reference voltage for the die structure400. Accordingly, the doped contact region442may alternatively be referred to herein as the shunting contact region.

Still referring toFIG. 7, in the illustrated embodiment, for an N-type transistor having a P-type well region412, N-type source and drain electrode contact regions436,438may be formed in the P-well412proximate the gate structure430by masking the shunting region408and other portions of the device region410with an implantation mask that leaves exposed the portions of the P-well412adjacent to the gate structure430and implanting N-type ions, such as phosphorous ions, with a dopant concentration in the range of about 1×1019/cm3to about 1×1021/cm3. After forming the N-type electrode contact regions, fabrication of the transistor may continue by removing the implantation mask used for the N-type implantation and forming P-type electrode contact regions, such as body electrode contact region440along with the shunting contact region442. To form the P-type contact regions, the substrate401is masked with an implantation mask450that masks the gate structure430and the source/drain electrode contact regions436,438and leaves exposed the remaining portions of the P-well region412along with the portions of the active layer406between the shallow isolation regions414,416of the shunting region408. The P-type contact regions are then formed by implanting P-type ions, illustrated by arrows452, in the exposed portions of the P-well region412and active layer semiconductor material406using the implantation mask450, resulting in the semiconductor die structure400ofFIG. 7. The P-type contact regions440,442may be formed by implanting P-type ions, such as boron ions, with a dopant concentration in the range of about 1×1019/cm3to about 1×1021/cm3at an energy level chosen so that the depth of the P-type contact regions440,442is less than the depth of the shallow isolation regions414,416,418. In this regard, the shunting contact region442is formed in the upper surface of the active layer of semiconductor material406and is effectively located at the surface of the active layer of semiconductor material406, so that a portion of active layer semiconductor material406in the shunting region408remains between the shunting contact region442and the buried dielectric material404. For purposes of explanation, the portion of the active layer semiconductor material406within the shunting region408that underlies the shunting contact region442may be referred to as the body region443(or body portion) of the shunting region408. In some embodiments, the depth and dopant concentration of the P-type contact regions440,442are be substantially same as the depth and dopant concentration of the N-type contact regions436,438but with opposite conductivity. As illustrated inFIG. 7, the isolation region416resides between the shunting contact region442and the body electrode contact region440and the well region412and thereby laterally isolates the shunting contact region442from the body electrode412,440and the other electrodes of the transistor device on the device region410. After the P-type contact regions440,442are formed, the fabrication of the die structure400may continue by removing the implantation mask450and performing additional front-end-of-line (FEOL) fabrication process steps to complete fabrication of the semiconductor devices on the device region410.

Referring now toFIG. 8, after the appropriate FEOL fabrication process steps have been performed to fabricate the desired semiconductor devices on the device region410, fabrication of the die structure400continues by performing back-end-of-line (BEOL) fabrication process steps including forming contacts460,462on the deep trench conductive material424and the shunting contact region442concurrently to forming contacts464,466,468on the gate structure430and the transistor electrode contact regions436,438,440. In exemplary embodiments, the contacts460,462,464,466,468are realized as a metal silicide layer formed by conformably depositing a layer of silicide-forming metal onto the exposed surfaces of the contact regions436,438,440,442, the gate structure430, and the conductive material424and heating the die structure400, for example by rapid thermal annealing (RTA), to react the silicide-forming metal with the exposed silicon and form metal silicide contacts460,462,464,466,468at the top of the deep trench conductive material424, the respective contact regions436,438,440,442, and the gate structure430, with the unreacted silicide-forming metal being removed thereafter.

After forming contacts460,462,464,466,468, fabrication of the die structure400continues by forming or otherwise providing electrical connections to/from the silicide contacts, for example, using interconnect layers (e.g., metallization and/or via layers) subsequently formed overlying the semiconductor die structure400. In exemplary embodiments, the shunting contact region442is electrically connected (or shorted) to the substrate reference voltage and/or the handle layer semiconductor material402, for example, by providing a conductive electrical connection470between the shunting region contact462and the deep trench contact460. For example, terminals472,474, such as contact plugs, vias or the like, may be formed overlying the contacts460,462, and the connection470may be provided between the terminals472,474, for example, by forming the connection470using a conductive trace in an overlying metal interconnect layer. In this manner, by virtue of the electrical connection470and the contiguity of the active layer semiconductor material406between regions408,410, the shunting contact region442and the underlying body region443of active layer semiconductor material406provide a resistive connection (or path) from the body region of the active layer semiconductor material406of the device region410(e.g., well region412and/or its underlying/surrounding semiconductor material406) to the handle layer semiconductor material402. As described above in the context ofFIG. 1-3, in exemplary embodiments, the handle layer402is electrically connected, at or near an edge of the die structure400, to a device package interface480that is configured to receive a substrate reference voltage. In this manner, the shunting region408is effectively connected to the substrate reference voltage interface via the deep trench conductive material424and the electrical connection470. It should be noted that for the embodiment ofFIG. 2, where the shunting region408does not include a deep trench isolation region420, rather than terminating at the deep trench contact terminal472, the electrical connection470to the shunting region408may extend to an edge of the die structure400, at which point, the electrical connection470may be routed or otherwise configured to contact the handle layer402and/or the substrate reference voltage interface480at or near the edge of the die structure400.

In a similar manner, an electrode terminal of a semiconductor device in the device region410is electrically connected (or shorted) to an I/O interface482of a device package. For example, a terminals476, such as a contact plug, a via or the like, may be formed overlying the gate electrode contact466, and an electrical connection478may be provided between the gate electrode terminal476and the I/O device package interface482, for example, by forming the connection478using a conductive trace in an overlying metal interconnect layer. By virtue of this connection any excess voltage at the I/O package interface482resulting from a CDM ESD event (e.g., a transient voltage that is not fully clamped by ESD protection circuitry coupled to the I/O package interface482) is applied to the gate electrode, which in turn, may raise the voltage of the gate conductive material434relative to the voltage of the source electrode region436and/or the well region412and cause the transistor on the device region410to conduct current. In this regard, by virtue of the body region443of active layer semiconductor material406in the shunting region408that underlies the shunting contact region442being contiguous with the body region of active layer semiconductor material406of the device region410underlying the transistor, the shunting region408provides a resistive path to the handle layer402that conducts a percentage of the discharge current and thereby dissipates or otherwise distributes a percentage of the discharge voltage at the gate electrode. As a result, the voltage at the gate electrode (e.g., gate conductive material434) relative to the source electrode (e.g., source contact region436) is reduced, thereby reducing the proportion of the discharge current and/or voltage that is dissipated by the transistor and/or other semiconductor devices on the device region410. As described above in the context ofFIG. 1, by virtue of the plurality of shunting regions108being distributed throughout the die102, the resistive paths between the active layer semiconductor material406and the handle layer semiconductor material402are effectively electrically in parallel with one another to further reduce the effective substrate resistance across the die structure400, which, in turn, increases the percentage of the discharge current and/or voltage that is dissipated by the semiconductor substrate401(e.g., the active layer406and/or the handle layer402) relative to the percentage of the discharge current and/or voltage that must be dissipated by the transistors and/or semiconductor devices on the device region410. In this manner, the distributed shunting regions108protect adjacent or neighboring semiconductor devices on the device region410during an ESD event, particularly, during CDM-type voltage transients that may not be fully clamped by ESD protection circuitry due to the magnitude of the applied voltage pulse and/or the relatively short duration of the applied voltage pulse.

For the sake of brevity, conventional techniques related to semiconductor and/or integrated circuit fabrication, ESD protection, and other functional aspects of the subject matter may not be described in detail herein. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting. For example, the terms “first”, “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.

In conclusion, systems, devices, and methods configured in accordance with example embodiments of the invention relate to:

An apparatus for a die structure is provided in one embodiment. The die structure includes a substrate having a first layer of semiconductor material including a plurality of semiconductor devices formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer, and a plurality of shunting regions in the first layer of semiconductor material. Each shunting region includes a doped region formed in the first layer and an underlying body region of the first layer, wherein the doped region is electrically connected to the handle layer of semiconductor material and the body region is contiguous with at least a portion of the first layer underlying a semiconductor device of the plurality of semiconductor devices, the body region underlying the doped region. In some embodiments, the doped region of each shunting region is laterally enclosed by an isolation region, wherein a depth of the doped region is less than a depth of the isolation region. In one or more embodiments, the isolation region resides between the doped region and an electrode of the semiconductor device. In accordance with one or more embodiments, a shunting region of the plurality of shunting regions includes a deep isolation region having a conductive material extending through an opening in the buried layer to contact the handle layer, wherein the conductive material is electrically connected to the doped region and the handle layer. In one or more embodiments, the dopant concentration of the first layer is less than 1×1017/cm3and the dopant concentration of the doped region is greater than the dopant concentration of the first layer. In a further embodiment, a dopant concentration of the conductive material is greater than 1×1017/cm3and a dopant concentration of the handle layer is less than the dopant concentration of the conductive material. In another embodiment, the doped region and the body region have the same conductivity type. In a further embodiment, the doped region and the handle layer have the opposite conductivity type.

In another embodiment, an apparatus for a device package is provided. The device package includes a first terminal, a second terminal, and a substrate. The substrate comprises a handle layer of semiconductor material, a buried layer of dielectric material overlying the handle layer, and a first layer of semiconductor material overlying the buried layer. The handle layer is electrically connected to the first terminal. The substrate also includes a device region including at least a first semiconductor device having an electrode electrically connected to the second terminal, and a plurality of shunting regions electrically connected to the handle layer, wherein at least a first portion of the first layer of semiconductor material of each shunting region is contiguous with at least a second portion of the first layer of semiconductor material of the device region. In one embodiment, each shunting region includes a doped region located at an upper surface of the first layer and electrically connected to the handle layer, wherein the first portion of the first layer of semiconductor material of the respective shunting region underlies the doped region. In a further embodiment, the second portion of the first layer of semiconductor material of the device region underlies the first semiconductor device. In another embodiment, each shunting region includes an isolation region between the doped region and the first semiconductor device, wherein the isolation region laterally isolates the doped region and a depth of the isolation region is greater than a depth of the doped region. In a further embodiment, the device package includes a deep isolation region in the substrate, wherein the deep isolation region includes a conductive material in contact with the handle layer, and the doped region is electrically connected to the conductive material. In yet another embodiment, the first layer comprises epitaxial semiconductor material having a dopant concentration that is less than 1×1017/cm3and a dopant concentration of the doped region is greater than the dopant concentration of the epitaxial semiconductor material.

In accordance with another embodiment, a method is provided for fabricating a semiconductor device on a first layer of semiconductor material of a substrate that also comprises a handle layer of semiconductor material and a buried layer of dielectric material between the handle layer and the first layer. The method comprises forming a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a first portion of the first layer that is contiguous with a second portion of the first layer underlying the semiconductor device and a doped region overlying the first portion, and providing an electrical connection between the handle layer and the plurality of shunting regions. In one embodiment, forming each shunting region comprises forming the doped region in an upper surface of the first layer. In a further embodiment, forming each shunting region further comprises forming, in the first layer, a deep isolation region including a conductive material in contact with the handle layer, and providing the electrical connection comprises providing the electrical connection between the doped region and the conductive material. In another embodiment, the method further comprises forming a shallow isolation region in the first layer, wherein the shallow isolation region laterally isolates the doped region from the semiconductor device.