Method for manufacturing embedded memory using high-K-metal-gate (HKMG) technology

A method for manufacturing embedded memory using high-κ-metal-gate (HKMG) technology is provided. A gate stack is formed on a semiconductor substrate. The gate stack comprises a charge storage film and a control gate overlying the charge storage film. The control gate includes a first material. A gate layer is formed of the first material, and is formed covering the semiconductor substrate and the gate stack. The gate layer is recessed to below a top surface of the gate stack, and subsequently patterned to form a select gate bordering the control gate and to form a logic gate spaced from the select and control gates. An ILD layer is formed between the control, select, and logic gates, and with a top surface that is even with top surfaces of the control, select, and logic gates. The control, select, or logic gate is replaced with a new gate of a second material.

BACKGROUND

Embedded memory is electronic memory that is integrated with logic devices on a common integrated circuit (IC) die or chip. The embedded memory supports operation of the logic devices and is often used with very-large-scale integration (VLSI) IC dies or chips. The integration advantageously improves performance by eliminating interconnect structures between chips and advantageously reduces manufacturing costs by sharing process steps between the embedded memory and the logic devices.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper”, and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device or apparatus in use or operation in addition to the orientation depicted in the figures. The device or apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Even more, the terms “first”, “second”, “third”, “fourth”, and the like are merely generic identifiers and, as such, may be interchanged in various embodiments. For example, while an element (e.g., an etch, a dielectric layer, or a substrate) may be referred to as a “first” element in some embodiments, the element may be referred to as a “second” element in other embodiments.

Some integrated circuits (ICs) comprise a logic device and an embedded memory cell on a common semiconductor substrate. The logic device comprises a first pair of source/drain regions and a logic gate between the source/drain regions of the first pair. The embedded memory cell is spaced from the logic device, and comprises a second pair of source/drain region regions, an erase gate, a word line, and a gate stack. The erase gate overlies a source/drain region of the second pair, and the gate stack and the word line are spaced between the source/drain regions of the second pair, such that the word line borders the control gate. The gate stack comprises a floating gate and a control gate overlying the floating gate.

The logic gate, the control gate, the word line, the erase gate, and the floating gate are typically polysilicon. However, semiconductor devices using polysilicon gates are reaching performance and/or scaling limits. Therefore, high-κ-metal-gate (HKMG) technology is increasingly being used for at least the logic device. Methods for manufacturing the logic device using HKMG technology typically comprise forming the logic device with a dummy logic gate, and forming an interlayer dielectric (ILD) layer covering the logic device. Subsequently, a planarization is performed into the ILD layer to expose a top surface of the dummy logic gate, and the dummy logic gate is replaced with a high κ dielectric layer and a metal logic gate overlying the high κ dielectric layer.

A challenge with the foregoing methods is that the embedded memory cell is typically formed with the logic device. Further, a bottom surface of the control gate typically has minimal spacing from a top surface of the logic gate since the control gate is formed on the floating gate and the floating gate has a thickness comparable to that of the dummy logic gate. As such, during the planarization to expose the dummy logic gate, a majority of or all of the control gate may be removed, thereby destroying the embedded memory cell. While the methods could be modified to overcome this challenge, such modifications come at the cost of increased complexity and increased cost.

In view of the foregoing, various embodiments of the present application are directed towards a method for manufacturing embedded memory using HKMG technology. In some embodiments, a gate stack is formed on a semiconductor substrate. The gate stack comprises a charge storage film (e.g., an oxide-nitride-oxide (ONO) film) and a control gate overlying the charge storage film. The control gate is a first material. A gate layer is formed covering the semiconductor substrate and the gate stack. The gate layer is the first material. A top surface of the gate layer is recessed to below a top surface of the gate stack. The gate layer is patterned to form a select gate bordering the control gate, and to further form a logic gate spaced from the select and control gates. An ILD layer is formed laterally between the control, select, and logic gates, and further with a top surface that is even with top surfaces respectively of the control, select, and logic gates. The control, select, or logic gate is replaced with a new gate, and the new gate is a second material different than the first material.

Advantageously, the charge storage film has a minimal thickness relative to the control and logic gates, and the control gate has a bottom surface that is sufficiently spaced below a top surface of the logic gate for use with HKMG replacement. This is advantageous because, during HKMG replacement, a planarization may be performed to the top surface of the logic gate. If the bottom surface of the control gate is not sufficiently spaced below the top surface of the logic gate, the control gate may be completely or almost completely removed by the planarization, whereby the control gate may be too small for use in production and/or too small for replacement with a HKMG stack. Further, by using a 1.5 transistor (1.5T) flash structure (e.g., by using a common selectively-conductive channel for the gate stack and the select gate), the embedded memory may advantageously be programmed by hot carrier injection (HCI), which is fast and has low power consumption. Further yet, by using the charge storage film stack with HKMG for data storage, the embedded memory has large program and erase windows and the process for manufacturing the embedded memory is simplified.

With reference toFIG. 1, a cross-sectional view100of some embodiments of an IC comprising an embedded memory cell102and using HKMG technology is provided. As illustrated, the embedded memory cell102is on a memory region104mof a semiconductor substrate104, laterally spaced from a logic device106on a logic region1041of the semiconductor substrate104. The embedded memory cell102may be, for example, a 1.5 transistor (1.5T) semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell, a 1.5T metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell, or some other type of memory cell. The logic device106may be, for example, metal-oxide-semiconductor field-effect transistor (MOSFET), some other type of insulated gate field-effect transistor (IGFET), or some other type of semiconductor device.

The embedded memory cell102comprises a pair of memory source/drain regions108, as well as a select gate110, a control gate112, and a charge storage film114. The memory source/drain regions108are in the semiconductor substrate104, along the top surface104tof the semiconductor substrate104, and define a selectively-conductive memory channel116in the semiconductor substrate104. The selectively-conductive memory channel116extends along the top surface104tof the semiconductor substrate104, from one of the memory source/drain regions108to another one of the memory source/drain regions108.

The select gate110and the charge storage film114are spaced between the memory source/drain regions108, and the control gate112overlies the charge storage film114. The charge storage film114may be, for example, an ONO film (e.g., a pair of oxide layers and a nitride layer sandwiched between the oxide layers), an oxide-silicon nanodot-oxide film (e.g., a pair of oxide layers and a layer of silicon nanodots sandwiched between the oxide layers), or some other type of charge storage film. The select and control gates110,112may be, for example, metal (e.g., aluminum copper), doped polysilicon, or some other conductive material. Further, the select gate110may be, for example, a word line.

In operation, the charge storage film114stores charge representing a bit of data, and the select gate110, the control gate112, and the memory source/drain regions108are selectively biased to program, erase, and read the bit of data. In some embodiments, programming (e.g., setting the bit of data to a binary “0”) is performed by hot carrier injection (HCI) (e.g., source-side injection (SSI)). Further, in some embodiments, erasing (e.g., setting the bit of data to a binary “1”) is performed by Fowler-Nordheim tunneling (FNT). Advantageously, HCI is fast and has low power consumption. Further, by using the charge storage film114for data storage, the control gate112advantageously spans the majority of the memory cell thickness TMsince the charge storage film114can have a minimal thickness TS. As seen hereafter, this simplifies the integration of HKMG technology into methods for manufacturing the embedded memory cell102and the logic device106.

An inter-gate spacer118is laterally between the select and control gates110,112to laterally space the select gate110from the control gate112and from the charge storage film114. A base select gate dielectric layer120is vertically between the select gate110and the semiconductor substrate104to vertically space the select gate110from the semiconductor substrate104. The inter-gate spacer118and/or the base select gate dielectric layer120may be, for example, oxide or some other dielectric.

In some embodiments where the select gate110is metal, a high κ select gate dielectric layer122lines a bottom surface of the select gate110, between the base select gate dielectric layer120and the select gate110. Further, in some embodiments, the high κ select gate dielectric layer122lines the bottom surface of the select gate110, and further lines sidewalls of the select gate110, to cup the select gate110. In some embodiments where the control gate112is metal, a high κ control gate dielectric layer124lines a bottom surface of the control gate112, between the charge storage film114and the control gate112. Further, in some embodiments, the high κ control gate dielectric layer124lines the bottom surface of the control gate112, and further lines sidewalls of the control gate112, to cup the control gate112. As used herein, a high κ dielectric layer is a dielectric with a dielectric constant κ greater than about 3.9, 5, 10, 15, or 20. Advantageously, where the embedded memory cell102uses HKMG technology (e.g., the select gate110and/or the control gate112are metal, and the one or more metal gates overlie one or more respective high κ dielectric layers), the embedded memory cell102has low power consumption and high switching speed. Further, where the embedded memory cell102uses HKMG technology, the embedded memory cell102may advantageously be scaled in different process nodes, such as, for example, 10, 16, 20, and 28 nanometer process nodes.

In some embodiments, control gate sidewall spacers126are along sidewalls of the control gate112to laterally space the sidewalls respectively from neighboring sidewalls of the charge storage film114. For example, one of the control gate sidewall spacers126may be along a sidewall of the control gate112, between the sidewall and the inter-gate spacer118. The control gate sidewall spacers126may be, for example, ONO films or some other dielectric materials. For ease of illustration, only one of the control gate sidewall spacers126is labeled126.

The logic device106comprises a pair of logic source/drain regions128, as well as a logic gate130and a base logic gate dielectric layer132. The logic source/drain regions128are in the semiconductor substrate104, along the top surface104tof the semiconductor substrate104, and define a selectively-conductive logic channel134in the semiconductor substrate104. The selectively-conductive logic channel134extends along the top surface104tof the semiconductor substrate104, from one of the logic source/drain regions128to another one of the logic source/drain regions128.

The logic gate130and the base logic gate dielectric layer132are between the logic source/drain regions128, and the logic gate130overlies the base logic gate dielectric layer132. The base logic gate dielectric layer132may be, for example, oxide or some other dielectric, and the logic gate130may be, for example, metal (e.g., aluminum copper), doped polysilicon, or some other conductive material. In some embodiments where the logic gate130is metal, a high κ logic gate dielectric layer136lines a bottom surface of the logic gate130, between the base logic gate dielectric layer132and the logic gate130. Further, in some embodiments, the high κ logic gate dielectric layer136lines the bottom surface of the logic gate130, and further lines sidewalls of the logic gate130, such that the high κ logic gate dielectric layer136cups the logic gate130. Advantageously, where the logic device106uses HKMG technology (e.g., the logic gate130is metal and overlies the high κ logic gate dielectric layer136), the logic device106has low power consumption and high switching speed. Further, the logic device106may advantageously be scaled in different process nodes (e.g., 10 or 16 nanometer process nodes).

In some embodiments, main sidewall spacers138are along sidewalls of the logic gate130, and/or are along sidewalls of the select and control gates110,112. For example, a pair of main sidewall spacers may be on opposite side of the logic device106, such that the logic gate130is sandwiched between the main sidewall spacers. As another example, a pair of main sidewall spacers may be on opposite sides of the embedded memory cell102, such that the select and control gates110,112are sandwiched between the main sidewall spacers. The main sidewall spacers138may, for example, be oxide, nitride, or some other dielectric. Further, for ease of illustration, only some of the main sidewall spacers138are labeled138.

In some embodiments, an ILD layer140covers the embedded memory cell102and the logic device106. Further, in some embodiments, contact vias (not shown) extend through the ILD layer140to the memory source/drain regions108, the logic source/drain regions128, the control gate112, the select gate110, the logic gate130, or a combination of the foregoing. The ILD layer140may be, for example, an oxide, a low κ dielectric, or some other dielectric, and the contact vias may be, for example, tungsten, aluminum copper, copper, or some other metal or conductive material. As used herein, a low κ dielectric is a dielectric with a dielectric constant κ less than about 3.9, 3, 2, or 1.

WhileFIG. 1illustrates the select, control, and logic gates110,112,130as overlying respective high κ dielectric layers, it is to be understood that at least one or all of the high κ dielectric layers (e.g., the high κ logic gate dielectric layer136) may be omitted in some embodiments. In such embodiments, the one or more gates without high κ dielectric layers are typically polysilicon, and/or the one or more gates with high κ dielectric layers are typically metal. For example, the select and control gates110,112may be polysilicon, and the logic gate130may be metal. Further, continuing with this example, the high κ logic gate dielectric layer136may underlie the logic gate130and the high κ select and control gate dielectric layers122,124may be omitted. As another example, the select, control, and logic gates110,112,130may be metal, and the select, control, and logic gates110,112,130may respectively overlie the high κ select, control, and logic gate dielectric layers122,124,136.

With reference toFIG. 2, a cross-sectional view200of some more detailed embodiments of the IC ofFIG. 1is provided. As illustrated, a first embedded memory cell102aand a second embedded memory cell102bare on the memory region104mof the semiconductor substrate104, laterally spaced from the logic region1041of the semiconductor substrate104. As inFIG. 1, the logic region1041of the semiconductor substrate104supports the logic device106. The semiconductor substrate104may be, for example, a bulk silicon substrate or some other type of semiconductor substrate. In some embodiments, the memory and logic regions104m,1041of the semiconductor substrate104are demarcated by an isolation structure202extending into the top surface of the semiconductor substrate104. The isolation structure202may be, for example, a deep trench isolation structure, a shallow trench isolation structure, or some other type of isolation structure.

The first and second embedded memory cell102a,102bare each as the embedded memory cell102ofFIG. 1is described, except that the second embedded memory cell102bis a mirror image of the embedded memory cell102ofFIG. 1. Further, the first and second embedded memory cells102a,102bshare a common memory source/drain region108cand have individual memory source/drain regions108i. The individual memory source/drain regions108iand the common memory source/drain region108care in the semiconductor substrate104, along the top surface of the semiconductor substrate104. Further, the individual memory source/drain regions108iand the common memory source/drain region108cdefine selectively-conductive memory channels116in the semiconductor substrate104. For ease of illustration, only one of the selectively-conductive memory channels116is labeled116. The selectively-conductive memory channels116are individual to the first and second embedded memory cell102a,102b, and each extends from the common memory source/drain region108cto a respective one of the individual memory source/drain regions108i.

With reference toFIG. 3, a cross-sectional view300of some more detailed embodiments of the IC ofFIG. 2is provided. As illustrated, the first embedded memory cell102aand the second embedded memory cell102bare on the memory region104mof the semiconductor substrate104, laterally spaced from a low voltage logic region1041vof the semiconductor substrate104and a high voltage logic region104hvof the semiconductor substrate104. In some embodiments, the memory region104mof the semiconductor substrate104is spaced between the low and high voltage logic regions1041v,104hvof the semiconductor substrate104.

In some embodiments, a low voltage well3021vis in the low voltage logic region1041vof the semiconductor substrate104, and/or a high voltage well302hvis in the high voltage logic region104hvof the semiconductor substrate104. Further, in some embodiments, a threshold adjustment region304is in the memory region104mof the semiconductor substrate104. The threshold adjustment region304is a doped region of the semiconductor substrate104that adjusts threshold voltages of the select gates110.

A low voltage logic device1061vis on the low voltage logic region1041vof the semiconductor substrate104, and a high voltage logic device106hvis on the high voltage logic region104hvof the semiconductor substrate104. The low voltage logic device1061vis “low” voltage in that it is limited to a smaller gate-to-source voltage and/or a smaller source-to-drain voltage than the high voltage logic device106hv. In some embodiments, the low voltage logic device1061vis limited to a gate-to-source voltage and/or a source-to-drain voltage less than about 5, 10, 50, 100, or 200 volts. The low voltage logic device1061vand the high voltage logic device106hvare each as the logic device106ofFIG. 1is described, except that the high voltage logic device106hvhas increased electrical insulation. For example, the base logic gate dielectric layer132of the low voltage logic device1061vhas a low-voltage thickness Tlv, and the base logic gate dielectric layer132of the high voltage logic device106hvhas a high-voltage thickness Thvgreater than the low-voltage thickness Tlv.

Also illustrated by the cross-sectional view300ofFIG. 3, in some embodiments, a silicide layer306is along a top surface of the common memory source/drain region108c, the individual memory source/drain regions108i, and the logic source/drain regions128. The silicide layer306may be, for example, nickel silicide or some other type of silicide. Further, in some embodiments, the common memory source/drain region108c, the individual memory source/drain regions108i, and the logic source/drain regions128border respective lightly-doped drain (LDD) regions308. For ease of illustration, only one of the LDD regions308is labeled308. Further yet, in some embodiments, a contact etch stop layer310lines sidewalls of the main sidewall spacers138, and further covers the silicide layer306. The contact etch stop layer310may be, for example, silicon nitride, silicon oxynitride, silicon dioxide, or some other dielectric.

WhileFIGS. 2 and 3illustrate the select, control, and logic gates110,112,130as overlying respective high κ dielectric layers, it is to be understood that at least one or all of the high κ dielectric layers may be omitted in some embodiments. In such embodiments, the one or more gates without high κ dielectric layers are typically polysilicon, and/or the one or more gates with high κ dielectric layers are typically metal.

With reference toFIGS. 4-19, a series of cross-sectional views400-1900illustrate some embodiments of a method for manufacturing an IC with embedded memory using HKMG technology. The IC may, for example, be the IC ofFIG. 2.

As illustrated by the cross-sectional view400ofFIG. 4, an isolation structure202is formed extending into a top surface of a semiconductor substrate104to demarcate a logic region1041of the semiconductor substrate104and a memory region104mof the semiconductor substrate104. The isolation structure202may be, for example, a shallow trench isolation structure, a deep trench isolation structure, or some type of isolation structure. In some embodiments, a process for forming the isolation structure202comprises forming trenches demarcating the memory and logic regions104m,1041of the semiconductor substrate104, and subsequently filling the trenches with a dielectric material.

Also illustrated by the cross-sectional view400ofFIG. 4, a charge storage film402, a first dummy gate layer404, a first control gate hard mask layer406, and a second control gate hard mask layer408are formed stacked over the semiconductor substrate104. The charge storage film402is formed covering the semiconductor substrate104and the isolation structure202, and may be, for example, an ONO film or some other type of charge storage film. The first dummy gate layer404is formed covering the charge storage film402and may be, for example, polysilicon or some other material. The first control gate hard mask layer406is formed covering the first dummy gate layer404and may be, for example, oxide or another dielectric. The second control gate hard mask layer408is formed covering the first control gate hard mask layer406and may be, for example, nitride or another dielectric.

In some embodiments, a process for forming the charge storage film402, the first dummy gate layer404, the first control gate hard mask layer406, and the second control gate hard mask layer408comprises sequentially performing a plurality of growth and/or deposition processes. The growth and/or deposition processes may comprise, for example, thermal oxidation, chemical or physical vapor deposition, sputtering, some other growth or deposition process, or a combination of the foregoing.

As illustrated by the cross-sectional view500ofFIG. 5, the first and second control gate hard mask layers406,408(seeFIG. 4) and the first dummy gate layer404(seeFIG. 4) are patterned to define a pair of control gate stacks502overlying the charge storage film402. The control gate stacks502are each formed with a dummy control gate504, a first control gate hard mask506, and a second control gate hard mask508. The first control gate hard mask506is formed overlying the dummy control gate504, and the second control gate hard mask508is formed overlying the first control gate hard mask506.

In some embodiments, a process for patterning the first and second control gate hard mask layers406,408and the first dummy gate layer404comprises patterning a photoresist layer over the second control gate hard mask layer408using photolithography. Further, in some embodiments, the process comprises performing an etch into the first and second control gate hard mask layers406,408and the first dummy gate layer404with the patterned photoresist layer in place, and subsequently stripping the patterned photoresist layer.

As illustrated by the cross-sectional view600ofFIG. 6, control gate sidewall spacers126are formed over the charge storage film402(seeFIG. 5) and on sidewalls of the control gate stacks502. The control gate sidewall spacers126may, for example, be formed of nitride, oxide, an ONO film, or some other dielectric.

In some embodiments, a process for forming the control gate sidewall spacers126comprises forming a control gate sidewall spacer layer conformally covering and lining the structure ofFIG. 5. The control gate sidewall spacer layer may, for example, be formed by vapor deposition, sputtering, or some other growth or deposition process. Further, in some embodiments, the process comprises performing an etch back in to the control gate sidewall spacer layer to remove horizontal segments of the control gate sidewall spacer layer without removing vertical segments of the control gate sidewall spacer layer. The vertical segments correspond to the control gate sidewall spacers126.

Also illustrated by the cross-sectional view600ofFIG. 6, the charge storage film402(seeFIG. 5) is patterned to form a pair of individual charge storage films114respectively underlying the dummy control gates504. The control gates stacks502respectively include the individual charge storage films114. In some embodiments, a process for patterning the charge storage film402comprises performing an etch into the charge storage film402with the control gate sidewall spacers126in place, such that the control gate sidewall spacers126and the second control gate hard masks508serve as a mask during the etch.

As illustrated by the cross-sectional view700ofFIG. 7, inter-gate spacers118are formed along sidewalls respectively of the control gate sidewall spacers126and the individual charge storage films114. The inter-gate spacers118may, for example, be oxide or some other dielectric. In some embodiments, a process for forming the inter-gate spacers118comprises forming an inter-gate spacer layer conformally covering and lining the structure ofFIG. 6. The inter-gate spacer layer may, for example, be formed by high temperature oxidation (HTO) or some other oxidation process, which may, for example, be followed by rapid thermal annealing (RTA) or some other annealing process. Further, in some embodiments, the process comprises performing an etch back in to the inter-gate spacer layer to remove horizontal segments of the inter-gate spacer layer without removing vertical segments of the inter-gate spacer layer. The vertical segments correspond to the inter-gate spacers118.

As illustrated by the cross-sectional view800ofFIG. 8, a first gate dielectric layer802is formed covering and conformally lining the structure ofFIG. 7. In some embodiments, a process for forming the first gate dielectric layer802comprises rapid thermal oxidation (RTO) and/or HTO. Further, in some embodiments, the process comprises RTA.

Also illustrated by the cross-sectional view800ofFIG. 8, in some embodiments, a common memory source/drain region108cis formed in the semiconductor substrate104, between the control gate stacks502. In some embodiments, the common memory source/drain region108cis formed by ion implantation while a patterned photoresist layer covers the logic region1041of the semiconductor substrate104and a periphery of the memory region104mof the semiconductor substrate104. In other embodiments, the common memory source/drain region108cis formed by some other process for doping the semiconductor substrate104, or some other process for forming source/drain regions.

As illustrated the cross-sectional view900ofFIG. 9, spacers of the inter-gate spacers118that are between the control gate stacks502are removed, along with a portion of the first gate dielectric layer802that is between the control gate stacks502. In some embodiments, the removal comprises performing an etch into the inter-gate spacers118and the first gate dielectric layer802while a patterned photoresist layer covers the logic region1041of the semiconductor substrate104and a periphery of the memory region104mof the semiconductor substrate104.

Also illustrated by the cross-sectional view900ofFIG. 9, a second gate dielectric layer902is formed covering and conformally lining the semiconductor substrate104and the the control gate stacks502over the first gate dielectric layer802. In some embodiments, a process for forming the second gate dielectric layer902comprises in situ steam generation (ISSG), HTO, some other oxidation process, or a combination of the foregoing. Further, in some embodiments, the process comprises RTA or some other annealing process.

As illustrated by the cross-sectional view1000ofFIG. 10, the first and second gate dielectric layers802,902(seeFIG. 9) are removed from the logic region1041of the semiconductor substrate104and a periphery of the memory region104mof the semiconductor substrate104. The removal defines a common source/drain dielectric layer1002between the control gate stacks502. In some embodiments, the removal comprises an etch into the first and second gate dielectric layers802,902while a patterned photoresist layer covers a center of the memory region104mof the semiconductor substrate104.

Also illustrated by the cross-sectional view1000ofFIG. 10, a third gate dielectric layer1004is formed along a top surface of the semiconductor substrate104. The third gate dielectric layer1004may, for example, be formed of oxide or some other dielectric, and/or may, for example, be formed by thermal oxidation or some other growth or deposition process. Further, the third gate dielectric layer1004may, for example, be formed so it forms directly on semiconductor material, such as the semiconductor substrate104.

Also illustrated by the cross-sectional view1000ofFIG. 10, a second dummy gate layer1006is formed over the third gate dielectric layer1004and conformally lining the control gate stacks502. In some embodiments, the second dummy gate layer1006is formed of polysilicon or some other material. Further, in some embodiments, the second dummy gate layer1006is formed by chemical or physical vapor deposition, sputtering, or some other deposition process.

As illustrated by the cross-sectional view1100ofFIG. 11, a top surface of the second dummy gate layer1006is recessed to proximate top surfaces respectively of the dummy control gates504. For example, the top surface of the second dummy gate layer1006may be recessed to a location spaced between top surfaces respectively of the first control gate hard masks506and the top surfaces respectively of the dummy control gates504.

In some embodiments, a process for recessing the top surface of the second dummy gate layer1006comprises forming an antireflective coating (ARC) layer covering the second dummy gate layer1006, and subsequently performing a planarization into a top surface of the ARC layer. The ARC layer may, for example, be formed by spin-on deposition or some other deposition process, and photoresist or some other material may, for example, alternatively be used in place of the ARC layer. The planarization may, for example, be performed by a chemical mechanical polish (CMP) or some other planarization process. Further, in some embodiments, the process comprises performing an etch back into the second dummy gate layer1006and the ARC layer until the ARC layer is removed and the top surface of the second dummy gate layer1006is recessed to proximate the top surfaces respectively of the dummy control gates504. During the etch back, the etch back is initially limited to the ARC layer since the ARC layer covers the second dummy gate layer1006. However, once the etch back reaches the second dummy gate layer1006, the ARC layer and the second dummy gate layer1006are etched back concurrently. This continuous until the ARC layer is removed. In some embodiments, the ARC layer and the second dummy gate layer1106have substantially the same etch rates during the etch back, such that the top surfaces respectively of the ARC layer and the second dummy gate layer1006are substantially even as they are etched back. An example of the process is shown inFIGS. 37 and 38.

Also illustrated by the cross-sectional view1100ofFIG. 11, the second control gate hard masks508(seeFIG. 10) are removed, and top surfaces respectively of the inter-gate spacers118, the control gate sidewall spacers126, and the common source/drain dielectric layer1002are recessed to proximate to the top surfaces respectively of the dummy control gates504. In some embodiments, such removal and recessing is performed by etching.

As illustrated by the cross-sectional view1200ofFIG. 12, the second dummy gate layer1006(seeFIG. 11) is patterned to form a dummy logic gate1202and two dummy select gates1204. The dummy logic gate1202is formed on the logic region1041of the semiconductor substrate104. The dummy select gates1204are formed on the memory region104mof the semiconductor substrate104, respectively bordering the individual charge storage films114.

In some embodiments, a process for forming the dummy logic gate1202and the dummy select gates1204comprises forming a dummy hard mask layer covering the second dummy gate layer1006and the dummy control gates504. The dummy hard mask layer may, for example, be formed of oxide or some other dielectric, and/or may, for example, be formed by vapor deposition, sputtering, or some other deposition process. Further, in some embodiments, the process comprises patterning the dummy hard mask layer to form a dummy logic gate hard mask1206and a pair of dummy memory gate hard masks1208. The patterning may, for example, be performed using photolithography or some other patterning process. Further yet, in some embodiments, the process comprises performing an etch into the second dummy gate layer1006with the dummy logic gate hard mask1206and the dummy memory gate hard masks1208in place to form the dummy logic gate1202and the dummy select gates1204.

Advantageously, the individual charge storage films114have a minimal thickness TS, whereby bottom surfaces respectively of the dummy control gates504are substantially spaced below a top surface of the dummy logic gate1202by an amount S. In some embodiments, the minimal thickness TSis a thickness that is less than about 5%, 10%, 20%, or 30% of a thickness of the dummy control gates504, and/or that is less than about one, two, or five times a thickness of the third gate dielectric layer1004. Further, in some embodiments, the minimal thickness TSis about 140-220 angstroms, about 160-200 angstroms, or about 140-180 angstroms. The dummy control gates504, the dummy logic gate1202, and the dummy select gates1204may be replaced with HKMG stacks because the bottom surfaces of the dummy control gates504are substantially spaced below the top surface of the dummy logic gate1202. Absent the spacing, metal control gates formed as part of the HKMG stacks may have a minimal thickness, and embedded memory cells under manufacture may fail.

As illustrated by the cross-sectional view1300ofFIG. 13, main sidewall spacers138dare formed over the third gate dielectric layer1004, along sidewalls respectively of the dummy logic gate1202. Further, the main sidewall spacers138dare formed along sidewalls respectively of the dummy select gates1204that are outside a central region between the dummy control gates504, as well as along sidewalls respectively of the individual charge storage films114and the control gate sidewall spacers126that are in the central region. The main sidewall spacers138dmay, for example, be formed of oxide, nitride, or some other dielectric.

In some embodiments, a process for forming the main sidewall spacers138dcomprises forming a main sidewall spacer layer covering and conformally lining the structure ofFIG. 12. The main sidewall spacer layer may, for example, be formed by vapor deposition or some other growth or deposition process. Further, in some embodiments, the process comprises performing an etch back in to the main sidewall spacer layer to remove horizontal segments of the main sidewall spacer layer without removing vertical segments of the main sidewall spacer layer. The vertical segments correspond to the main sidewall spacers138d.

Also illustrated by the cross-sectional view1300ofFIG. 13, a pair of logic source/drain regions128and a pair of individual memory source/drain region108iare formed in the semiconductor substrate104. The logic source/drain regions128are formed respectively bordering opposite sides of the dummy logic gate1202. The individual memory source/drain regions108iare formed respectively bordering the dummy select gates1204. In some embodiments, the common memory source/drain region108cmay be enhanced (e.g., enlarged). In other embodiments, the common memory source/drain region108cis not formed atFIG. 8(as shown), and is instead formed atFIG. 13. The logic source/drain regions128and the individual memory source/drain regions108imay be formed by, for example, ion implantation, some other process for forming doped regions in the semiconductor substrate104, or some other process for forming source/drain regions. Similarly, the common memory source/drain region108cmay be formed or enhanced by, for example, ion implantation, some other process for forming doped regions in the semiconductor substrate104, or some other process for forming source/drain regions.

As illustrated by the cross-sectional view1400ofFIG. 14, the third gate dielectric layer1004(seeFIG. 13) and the common source/drain dielectric layer1002(seeFIG. 13) are patterned. The third gate dielectric layer1004is patterned to form a base logic gate dielectric layer132and a pair of base select gate dielectric layers120. The base logic gate dielectric layer132is formed underlying the dummy logic gate1202, and the base select gate dielectric layers120are respectively formed underlying the dummy select gates1204. Further, the common source/drain dielectric layer1002is patterned to form additional main sidewall spacers138cbetween the dummy control gates504. In some embodiments, the patterning is performed by an etch into the third gate dielectric layer1004and the common source/drain dielectric layer1002. The etch may, for example, use the main sidewall spacers138d, the dummy logic gate hard mask1206(seeFIG. 13), and the dummy memory gate hard masks1208(seeFIG. 13) as a mask.

Also illustrated by the cross-sectional view1400ofFIG. 14, the dummy logic gate hard mask1206(seeFIG. 13) and the dummy memory gate hard masks1208(seeFIG. 13) are removed. Further, top surfaces respectively of the main sidewall spacers138c,138dare recessed to proximate top surfaces of respective dummy gates. For example, top surfaces of main sidewall spacers along the dummy logic gate1202are recessed to proximate a top surface of the dummy logic gate1202. Further yet, top surfaces of the control gate sidewall spacers126and top surfaces of the inter-gate spacers118are recessed to proximate top surfaces of the dummy control and select gates504,1204.

In some embodiments, a process for performing the removal ofFIG. 14and the recessing ofFIG. 14comprises forming an ARC layer covering the dummy logic gate hard mask1206and the dummy memory gate hard masks1208, as well as covering the logic source/drain regions128and the memory source/drain region108i,108c. The ARC layer may, for example, be formed by spin-on deposition or some other deposition process, and photoresist or some other material may, for example, alternatively be used in place of the ARC layer. Further, in some embodiments, the process comprises performing a first etch into the ARC layer to recess the ARC layer to below a top surface of the dummy logic gate1202. Further yet, in some embodiments, the process comprises performing a second etch into the dummy logic gate hard mask1206, the dummy memory gate hard masks1208, the main sidewall spacers138c,138d, the control gate sidewall spacers126, and the inter-gate spacers118. The second etch continues until the dummy logic gate hard mask1206and the dummy memory gate hard masks1208are removed, and the main sidewall spacers138c,138d, the control gate sidewall spacers126, and the inter-gate spacers118are recessed. Further yet, in some embodiments, the process comprises removing the ARC layer after the second etch.

As illustrated by the cross-sectional view1500ofFIG. 15, a first ILD layer140ais formed covering the structure ofFIG. 14. In some embodiments, the first ILD layer140ais formed by vapor deposition, sputtering, or some other deposition process.

As illustrated by the cross-sectional view1600ofFIG. 16, a planarization is performed into the first ILD layer140ato coplanarize top surfaces respectively of the first ILD layer140a, the dummy logic gate1202, the dummy control gates504, and the dummy select gates1204. In some embodiments, the planarization is performed by a CMP.

As illustrated by the cross-sectional view1700ofFIG. 17, the dummy logic gate1202(seeFIG. 16), the dummy control gates504(seeFIG. 16), and the dummy select gates1204(seeFIG. 16) are removed, thereby forming a logic gate opening1702, a pair of select gate openings1704, and a pair of control gate openings1706. In some embodiments, a process for performing the removal comprises performing an etch into the dummy logic gate1202, the dummy control gates504, and the dummy select gates1204. An etchant for the etch may, for example, have a higher etch rate (e.g., 5, 50, 100, or 200 times higher) for the dummy gates (e.g., the dummy logic gate1202) than surrounding dielectric material (e.g., of the first ILD layer140a).

Advantageously, the individual charge storage films114have a minimal thickness TS, such that the control gate openings1706have a depth D sufficient to form HKMG stacks therein. If the individual charge storage films114were too thick, the depth D would be too small to form HKMG stacks therein. In particular, metal control gates of the HKMG stacks would be too thin for reliable operation of embedded memory cells under manufacture.

As illustrated by the cross-sectional view1800ofFIG. 18, a logic gate130and a high κ logic gate dielectric layer136are formed stacked in the logic gate opening1702(seeFIG. 17), where the logic gate130overlies the high κ logic gate dielectric layer136. Further, select gates110and high κ select gate dielectric layers122are formed stacked in the select gate openings1704(seeFIG. 17), where the select gates110respectively overlie the high κ select gate dielectric layer122. Further yet, control gates112and high κ control gate dielectric layer124are formed stacked in the control gate openings1706(seeFIG. 17), where the control gates112respectively overlie the high κ control gate dielectric layer122. In some embodiments, the logic gate130, the control gates112, and the select gates110are formed of metal.

In some embodiments, a process for forming the logic gate130, the control gates112, and the select gates110, as well as the high κ logic gate dielectric layer136, the high κ control gate dielectric layer124, and the high κ select gate dielectric layer122, comprises forming a high κ dielectric layer conformally lining and covering the structure ofFIG. 17. The high κ dielectric layer may, for example, be formed by vapor deposition or some other deposition process. Further, in some embodiments, the process comprises forming a metal layer covering the high κ dielectric layer and filling the logic gate opening1702, the select gate openings1704, and the control gate openings1706over the high κ dielectric layer. The metal layer may, for example, be formed by vapor deposition, electrochemical plating, or some other deposition or growth process. Further yet, in some embodiments, the process comprises performing a planarization into the high κ dielectric layer and the metal layer until a top surface of the first ILD layer140ais reached. The planarization may, for example, be performed by CMP or some other planarization process.

As illustrated by the cross-sectional view1900ofFIG. 19, a second ILD layer140bis formed covering the structure ofFIG. 18. The second ILD layer140bmay, for example, be formed by vapor deposition, sputtering, or some other deposition process, and/or may, for example, be formed with a planar or substantially planar top surface. In some embodiments, contact vias (not shown) are also formed extending through the first and second ILD layers140a,140bto the logic source/drain regions128, the memory source/drain regions108i,108c, the logic gate130, the select gates110, the control gates112, or a combination of the foregoing.

WhileFIGS. 4-20illustrate the replacement of the dummy logic gate1202(seeFIG. 16), the dummy control gates504(seeFIG. 16), and the dummy select gates1204(seeFIG. 16) with HKMG stacks, it is to be appreciated that the replacement may not be performed for all of the dummy gates in other embodiments. For example, the dummy select and/or control gates1204,504may not be replaced with HKMG stacks. In such embodiments, the dummy gates that are not replaced are masked during gate removal atFIG. 17and subsequently used in production.

With reference toFIG. 20, a flowchart2000of some embodiments of the method ofFIGS. 4-19is provided.

At2002, a pair of gate stacks is formed on a semiconductor substrate. The gate stacks each comprise a charge storage film, a control gate overlying the charge storage film, and a control gate hard mask overlying the control gate. See, for example,FIGS. 4-6.

At2004, a gate layer is formed covering the semiconductor substrate and the gate stacks. The gate layer conforms to the gate stacks. See, for example,FIG. 10.

At2006, a top surface of the gate layer is recessed to proximate top surfaces respectively of the control gates. Further, the first etch partially removes the control gate hard masks. See, for example,FIG. 11.

At2008, the gate layer is patterned to form a logic gate and a pair of select gates. The select gates respectively border the gate stacks. See, for example,FIG. 12.

At2010, source/drain regions are formed in the semiconductor substrate. The source/drain regions respectively border the logic gate and the select gates. See, for example,FIG. 13.

At2012, a remainder of the control gate hard masks is removed. See, for example,FIG. 14.

At2014, a planarization is performed into top surfaces respectively of the control gates, the logic gate, and the select gates to coplanarize the top surfaces. See, for example,FIGS. 15 and 16.

At2016, the control gates, the logic gate, the select gates, or a combination of the foregoing are replaced with HKMG stacks. See, for example,FIGS. 17 and 18. Each of the HKMG stacks comprises a metal gate and a high κ dielectric layer underlying the metal gate.

At2018, a back-end-of-line (BEOL) interconnect structure is formed over and electrically coupled to the source/drain regions and the HKMG stacks. See, for example,FIG. 19.

Advantageously, the charge storage films have a minimal thickness relative to the control and logic gates. As such, the control gates have bottom surfaces that are sufficiently spaced below a top surface of the logic gate for use with HKMG replacement.

With reference toFIGS. 21-53, a series of cross-sectional views2100-5300illustrate some more detailed embodiments of the method ofFIGS. 4-19. Such more detailed embodiments may, for example, be employed to manufacture the IC ofFIG. 3.

As illustrated by the cross-sectional view2100ofFIG. 21, an isolation structure202is formed extending into a top surface of a semiconductor substrate104. The isolation structure202is formed demarcating a high voltage logic region104hvof the semiconductor substrate104, a low voltage logic region1041vof the semiconductor substrate104, and a memory region104mof the semiconductor substrate104. Further, a pad layer2102is formed covering the high and low voltage logic regions104hv,1041vof the semiconductor substrate104, as well as the memory region104mof the semiconductor substrate104.

In some embodiments, a process for forming the isolation structure202comprises forming the pad layer2102over the semiconductor substrate104, and forming a second pad layer over the pad layer2102. The pad layer2102may, for example, be formed of oxide or some other dielectric layer, and/or the second pad layer may, for example, be formed of nitride or some other dielectric material. Further, in some embodiments, the process comprises patterning the pad layer2102and the second pad layer using photolithography, and performing an etch into the semiconductor substrate104with the pad layer2102and the second pad layer in place to form trenches corresponding to the isolation structure202. Further yet, in some embodiments, the process comprises filling the trenches with dielectric material, and removing the second pad layer, but not the pad layer2102.

Also illustrated by the cross-sectional view2100ofFIG. 21, a high voltage well302hvis formed in the high voltage logic region104hvof the semiconductor substrate104. In some embodiments, the high voltage well302hvis formed by ion implantation into the high voltage logic region104hvof the semiconductor substrate104while a patterned photoresist layer2104covers the low voltage logic region1041vof the semiconductor substrate104and the memory region104mof the semiconductor substrate104. In other embodiments, the high voltage well302hvis formed by some other process for forming doped regions in the semiconductor substrate104. The patterned photoresist layer2104is subsequently stripped. In some embodiments, another high voltage well (not shown) having an opposite doping type (e.g., p-type vs. n-type) as the high voltage well302hvis formed in the semiconductor substrate104. The other high voltage well may, for example, be formed in the same manner as the high voltage well302hv, except that a different patterned photoresist layer may be used.

As illustrated by the cross-sectional view2200ofFIG. 22, the pad layer2102is removed from the memory region104mof the semiconductor substrate104, but not the low and high voltage logic regions1041v,104hvof the semiconductor substrate104. In some embodiments, the removal is performed by an etch into the pad layer2102while a patterned photoresist layer2202covers the low and high voltage logic regions1041v,104hvof the semiconductor substrate104. The patterned photoresist layer2202is subsequently stripped.

As illustrated by the cross-sectional view2300ofFIG. 23, a charge storage film402, a first dummy gate layer404, a first control gate hard mask layer406, and a second control gate hard mask layer408are formed stacked over the semiconductor substrate104. Such a stack may be formed as described with regard toFIG. 4.

As illustrated by the cross-sectional view2400ofFIG. 24, the first and second control gate hard mask layers406,408(seeFIG. 23) and the first dummy gate layer404(seeFIG. 23) are patterned to define a pair of control gate stacks502overlying the charge storage film402. Each of the control gate stacks502is formed with a dummy control gate504, a first control gate hard mask506, and a second control gate hard mask508. The first control gate hard mask506is formed overlying the dummy control gate504, and the second control gate hard mask508is formed overlying the first control gate hard mask506. In some embodiments, the patterning comprises performing an etch into the first and second control gate hard mask layers406,408and the first dummy gate layer404with a patterned photoresist layer2402in place. The patterned photoresist layer2402is subsequently stripped.

As illustrated by the cross sectional view2500ofFIG. 25, a control gate sidewall spacer layer2502is formed covering and conformally lining the charge storage film402and the control gate stacks502.

As illustrated by the cross-sectional view2600ofFIG. 26, horizontal segments of the control gate sidewall spacer layer2502(seeFIG. 25) are removed without removing vertical segments of the control gate sidewall spacer layer2502. The vertical segments of the control gate sidewall spacer layer2502define control gate sidewall spacers126along sidewalls of the control gate stacks502. In some embodiments, the horizontal segments are removed by an etch back of the control gate sidewall spacer layer2502.

Also illustrated by the cross-sectional view2600ofFIG. 26, the charge storage film402(seeFIG. 25) is patterned to define a pair of individual charge storage films114respectively underlying the dummy control gates504. The control gates stacks502respectively include the individual charge storage films114. In some embodiments, the charge storage film402is patterned by continuing the etch back of the control gate sidewall spacer layer2502(seeFIG. 25) into the charge storage film402, such that the control gate sidewall spacers126and the second control gate hard masks508serve as a mask for the patterning. Further, the pad layer2102(seeFIG. 25) is removed while patterning the charge storage film402and/or during the etch back. The pad layer2102may, for example, serve as an etch stop to protect the low and high voltage logic regions1041v,104hvof the semiconductor substrate104from damage while patterning the charge storage film402and/or during the etch back.

As illustrated by the cross-sectional view2700ofFIG. 27, in some embodiments, a threshold adjustment region304is formed in the memory region104mof the semiconductor substrate104. In some embodiments, the threshold adjustment region304is formed by ion implantation while a patterned photoresist layer2702covers the low and high voltage logic regions1041v,104hvof the semiconductor substrate104. In other embodiments, the threshold adjustment region304is formed by some other process for forming doped regions in the semiconductor substrate104. The patterned photoresist layer2702is subsequently stripped.

As illustrated by the cross-sectional view2800ofFIG. 28, inter-gate spacers118are formed along sidewalls of the control gate sidewall spacers126and the individual charge storage films114. In some embodiments, a process for forming the inter-gate spacers118comprises forming an inter-gate spacer layer covering and conformally lining the structure ofFIG. 27, and performing an etch back of the inter-gate spacer layer to remove horizontal segments of the inter-gate spacer layer without removing vertical segments of the inter-gate spacer layer. The vertical segments correspond to the inter-gate spacers118. The inter-gate spacer layer may, for example, be formed by HTO or some other oxidation process, which may, for example, be followed by RTA or some other annealing process.

As illustrated by the cross-sectional view2900ofFIG. 29, a first gate dielectric layer802is formed covering and conformally lining the structure ofFIG. 27. In some embodiments, a process for forming the first gate dielectric layer802comprises RTO, HTO, some other oxidation process, or a combination of the foregoing. Further, in some embodiments, the process comprises RTA, some other annealing process, or a combination of the foregoing.

As illustrated by the cross-sectional view3000ofFIG. 30, a common memory source/drain region108cis formed in the memory region104mof the semiconductor substrate104, between the control gate stacks502. In some embodiments, the common memory source/drain region108cis formed by ion implantation while a patterned photoresist layer3002covers the low and high voltage logic regions1041v,104hvof the semiconductor substrate104and a periphery of the memory region104mof the semiconductor substrate104. In other embodiments, the common memory source/drain region108cis formed by some other process for forming doped regions in the semiconductor substrate104.

As illustrated the cross-sectional view3100ofFIG. 31, spacers of the inter-gate spacers118that are between the control gate stacks502are removed, along with a portion of the first gate dielectric layer802that is between the control gate stacks502. In some embodiments, the removal comprises performing an etch into the inter-gate spacers118and the first gate dielectric layer802while the patterned photoresist layer3002ofFIG. 30is in place. The patterned photoresist layer3002is subsequently stripped.

As illustrated by the cross-sectional view3200ofFIG. 32, a second gate dielectric layer902is formed covering and conformally lining the structure ofFIG. 31. In some embodiments, a process for forming the second gate dielectric layer902comprises ISSG, HTO, some other oxidation process, some other deposition process, or a combination of the foregoing. Further, in some embodiments, the process comprises RTA, some other annealing process, or a combination of the foregoing.

Also illustrated by the cross-sectional view3200ofFIG. 32, a low voltage well3021vis formed in the low voltage logic region1041vof the semiconductor substrate104. In some embodiments, the low voltage well3021vis formed by ion implantation while a patterned photoresist layer3202covers the high voltage logic region104hvof the semiconductor substrate104and the memory region104mof the semiconductor substrate104. The patterned photoresist layer3202is subsequently stripped. In other embodiments, the low voltage well3021vis formed by some other process for forming doped regions in the semiconductor substrate104.

In some embodiments, the first and second gate dielectric layers802,902are removed from an input/output (IO) region (not shown) of the semiconductor substrate104by, for example, a etch performed using photolithography. The10region may, for example, be adjacent to the low voltage logic region1041vof the semiconductor substrate104. Further, in some embodiments, an10dielectric layer is formed on the10region of the semiconductor substrate104by, for example, thermal oxidation, or some other growth or deposition process.

As illustrated by the cross-sectional view3300ofFIG. 33, the first and second gate dielectric layers802,902(seeFIG. 32) are removed from the low voltage logic region1041vof the semiconductor substrate104and a periphery of the memory region104mof the semiconductor substrate104. The removal defines a pair of high voltage gate dielectric layers132a,132bon the high voltage logic region104hvof the semiconductor substrate104, and a common source/drain dielectric layer1002between the dummy control gates504. In some embodiments, the removal comprises an etch into the first and second gate dielectric layers802,902while a patterned photoresist layer3302covers the high voltage logic region104hvof the semiconductor substrate104and a center of the memory region104mof the semiconductor substrate104. The patterned photoresist layer3302is subsequently stripped.

As illustrated by the cross-sectional view3400ofFIG. 34, a third gate dielectric layer1004and a second dummy gate layer1006are formed. The third gate dielectric layer1004is formed on exposed portions of the semiconductor substrate104. The second dummy gate layer1006is formed covering and conformally lining the third gate dielectric layer1004and the control gate stacks502. The third gate dielectric layer1004and/or the second dummy gate layer1006may, for example, be formed as described with regard toFIG. 10.

Also illustrated by the cross-sectional view3400ofFIG. 34, a first logic hard mask layer3402and an second logic hard mask layer3404are formed stacked over and conformally lining the second dummy gate layer1006, such that the second logic hard mask layer3404overlies the first logic hard mask layer3402. The first logic hard mask layer3402may, for example, be silicon nitride or some other dielectric, and/or the second logic hard mask layer3404may, for example, be tetraethylorthosilicate (TEOS) oxide or some other dielectric. The first and second logic hard mask layers3402,3404may, for example, be formed by vapor deposition, sputtering, or some other deposition process.

As illustrated by the cross-sectional view3500ofFIG. 35, the second logic hard mask layer3404is removed from the memory region104mof the semiconductor substrate104. In some embodiments, the removal comprises performing an etch into the second logic hard mask layer3404while a patterned photoresist layer3502covers the low and high voltage logic regions1041v,104hvof the semiconductor substrate104. The patterned photoresist layer3502is subsequently stripped.

As illustrated by the cross-sectional view3600ofFIG. 36, the first logic hard mask layer3402is removed from the memory region104mof the semiconductor substrate104. In some embodiments, the removal comprises performing an etch (e.g., a wet etch) into the first logic hard mask layer3402while the second logic hard mask layer3404(seeFIG. 35) covers the low and high voltage logic regions1041v,104hvof the semiconductor substrate104, and subsequently stripping the second logic hard mask layer3404. The second logic hard mask layer3404may, for example, be stripped by a wet etch in which the second logic hard mask layer3404is dipped in hydrofluoric (HF) solution.

As illustrated by the cross-sectional view3700ofFIG. 37, a first ARC layer3702is formed covering the first logic hard mask layer3402and the second dummy gate layer1006. The first ARC layer3702may, for example, be formed with a top surface that is planar or substantially planar.

As illustrated by the cross-sectional view3800ofFIG. 38, a top surface of the second dummy gate layer1006is recessed to proximate top surfaces of the dummy control gates504, and the first ARC layer3702(seeFIG. 37) is removed. Further, in some embodiments, the first logic hard mask layer3402, the inter-gate spacers118, the common source/drain dielectric layer1002, the second control gate hard masks508, the control gate sidewall spacers126, or a combination of the foregoing are also recessed. The recessing and removal may, for example, be performed by an etch, and the first logic hard mask layer3402may, for example, serve as an etch stop during the etch. Further, the recessing and removal may, for example, be performed as described with regard toFIG. 11.

As illustrated by the cross-sectional view3900ofFIG. 39, the first logic hard mask layer3402(seeFIG. 38) and the second control gate hard masks508(seeFIG. 38) are removed. Further, the control gate sidewall spacers126, the inter-gate spacers118, the common source/drain dielectric layer1002, the control gate sidewall spacers126, or a combination of the foregoing are also recessed back to proximate top surfaces respectively of the first control gate hard masks506. Such removal and recessing may, for example, be performed by an etch.

As illustrated by the cross-sectional view4000ofFIG. 40, a dummy gate hard mask layer4002is formed covering the structure ofFIG. 39. In some embodiments, the dummy gate hard mask layer4002conformally covers the structure ofFIG. 39. Further, in some embodiments, the dummy gate hard mask layer4002is oxide or some other dielectric, and/or is formed by vapor deposition or some other deposition process.

As illustrated by the cross-sectional view4100ofFIG. 41, the dummy gate hard mask layer4002(seeFIG. 40) is patterned to form a pair of dummy logic gate hard masks1206and a pair of dummy memory gate hard masks1208. The dummy logic gate hard masks1206are respectively formed on the high and low voltage logic regions104hv,1041vof the semiconductor substrate104. The dummy memory gate hard masks1208are formed on the memory region104mof the semiconductor substrate104, respectively overlapping the dummy control gates504. In some embodiments, the patterning comprises an etch into the dummy gate hard mask layer4002while a patterned photoresist layer4102selectively covers the dummy gate hard mask layer4002. The patterned photoresist layer4102is subsequently stripped.

Also illustrated by the cross-sectional view4100ofFIG. 41, the second dummy gate layer1006(seeFIG. 40) is patterned to form a pair of dummy logic gates1202respectively underlying the dummy logic gate hard masks1206, and to further form a pair of dummy select gates1204respectively underlying the dummy memory gate hard masks1208. In some embodiments, the second dummy gate layer1006is patterned by performing an etch into the second dummy gate layer1006while the dummy logic and memory gate hard masks1206,1208selectively cover the second dummy gate layer1006. Such an etch may be performed with or without the patterned photoresist layer4102in place.

As illustrated by the cross-sectional view4200ofFIG. 42, first main sidewall spacers138aare formed along sidewalls of the dummy logic gates1202, the dummy select gates1204, and the control gate sidewall spacers126. The first main sidewall spacers138amay be, for example, oxide, nitride, or some other dielectric. Further, for ease of illustration, only some of the first main sidewall spacers138aare labeled138a, and only one of the control gate sidewall spacers126is labeled126. In some embodiments, a process for forming the first main sidewall spacers138acomprises forming a main sidewall spacer layer covering and conformally lining the structure ofFIG. 41, and performing an etch back of the main sidewall spacer layer to remove horizontal segments of the main sidewall spacer layer without removing vertical segments of the main sidewall spacer layer. The vertical segments of the main sidewall spacer layer correspond to the first main sidewall spacers138a.

Also illustrated by the cross-sectional view4200ofFIG. 42, first LDD regions308aare formed in the low voltage logic region1041vof the semiconductor substrate104and the memory region104mof the semiconductor substrate104. For ease of illustration, only some of the first LDD regions308aare labeled308a. The first LDD regions308amay be formed by, for example, ion implantation while a patterned photoresist layer4202covers the high voltage logic region104hvof the semiconductor substrate104, and covers dummy gates (e.g., the dummy control gates504) in the low voltage logic region1041vof the semiconductor substrate104and the memory region104mof the semiconductor substrate104. The patterned photoresist layer4202is subsequently removed. Alternatively, the first LDD regions308amay be formed by, for example, some other process for forming doped regions in the semiconductor substrate104.

As illustrated by the cross-sectional view4300ofFIG. 43, second LDD regions308bare formed in the high voltage logic region104hvof the semiconductor substrate104. The second LDD regions308bmay be formed by, for example, ion implantation while a patterned photoresist layer4302covers the low voltage logic region1041vof the semiconductor substrate104and the memory region104mof the semiconductor substrate104. The patterned photoresist layer4302is subsequently removed. Dopants of the second LDD regions308band/or implant energy of the ion implantation may, for example, be selected so as to implant through the high voltage gate dielectric layers132a,132b. Alternatively, the second LDD regions308bmay be formed by, for example, some other process for forming doped regions in the semiconductor substrate104.

As illustrated by the cross-sectional view4400ofFIG. 44, second main sidewall spacers138bare formed along sidewalls of the first main sidewall spacers138a. For ease of illustration, only some of the second main sidewall spacers138bare labeled138b, and only some of the first main sidewall spacers138aare labeled138a. The second main sidewall spacers138bmay, for example, be formed in the same manner described above for the first main sidewall spacers138a.

Also illustrated by the cross-sectional view4400ofFIG. 44, logic source/drain regions128and individual memory source/drain regions108iare formed in the semiconductor substrate104. The logic source/drain regions128are formed along sidewalls of the dummy logic gates1202. The individual memory source/drain regions108iare formed respectively bordering the dummy select gates1204. In some embodiments, the common memory source/drain region108cmay be enhanced. For example, the common memory source/drain region108cmay be enhanced by enlarging the common source/drain region108c(e.g., increasing the depth and/or the width of the common source/drain region108c). In other embodiments, the common memory source/drain region108cis not formed atFIG. 30(as shown), and is instead formed atFIG. 44. The logic source/drain regions128and the memory source/drain regions108i,108cmay be formed by, for example, ion implantation, some other process for forming doped regions in the semiconductor substrate104, or some other process for forming source/drain regions.

As illustrated by the cross-sectional view4500ofFIG. 45, the common source/drain dielectric layer1002(seeFIG. 44), the third gate dielectric layer1004(seeFIG. 42), and the high voltage gate dielectric layers132a,132bare removed from the isolation structure202, the logic source/drain regions128, and the memory source/drain regions108c,108i. The removal defines a low voltage gate dielectric layer132cunderlying the dummy logic gate1202in the low voltage logic region1041vof the semiconductor substrate104. Further, the removal defines a pair of third main sidewall spacers138cbetween the dummy control gates504, as well as a pair of base select gate dielectric layers120underlying the dummy select gates1204. In some embodiments, the removal is performed by performing an etch into the common source/drain dielectric layer1002, the third gate dielectric layer1004, and the high voltage gate dielectric layers132a,132bwhile the first and second main sidewall spacers138a,138band the dummy logic and memory gate hard masks1206,1208serve as a mask.

Also illustrated by the cross-sectional view4500ofFIG. 45, a silicide layer306is formed on the logic source/drain regions128and the memory source/drain regions108c,108i. The silicide layer306may, for example, be formed of nickel silicide or some other silicide.

As illustrated by the cross-sectional view4600ofFIG. 46, a second ARC layer4602is formed covering structure ofFIG. 45. The second ARC layer4602may, for example, be formed with a planar or substantially planar top surface.

As illustrated by the cross-sectional view4700ofFIG. 47, a top surface of the second ARC layer4602is recessed to proximate top surfaces of the dummy control gates504. The recessing may, for example, be performed by an etch.

Also illustrated by the cross-sectional view4700ofFIG. 47, the dummy logic and memory gate hard masks1206,1208(seeFIG. 46) are removed. Further, the first, second, and third main sidewall spacers138a,138b,138c, the control gate sidewall spacers126, and the inter-gate spacers118are recessed. The recessing may, for example, be to below top surfaces of the select gates1204. The removal and recessing may, for example, be performed by an etch.

As illustrated by the cross-sectional view4800ofFIG. 48, the second ARC layer4602(seeFIG. 47) is removed. The removal may, for example, be performed by etching. Further, a contact etch stop layer310and a first ILD layer140aare formed stacked over the semiconductor substrate104. The contact etch stop layer310is formed conformally, and the first ILD layer140ais formed covering the contact etch stop layer310. In some embodiments, the contact etch stop layer310and/or the first ILD layer140aare formed by vapor deposition, sputtering, some other deposition process, or a combination of the foregoing.

As illustrated by the cross-sectional view4900ofFIG. 49, a planarization is performed into the contact etch stop layer310and the first ILD layer140ato coplanarize top surfaces thereof with top surfaces respectively of the dummy logic gates1202and the dummy control and select gates504,1204. The planarization may, for example, be performed by CMP or some other planarization process.

As illustrated by the cross-sectional view5000ofFIG. 50, the dummy logic gates1202(seeFIG. 49) and the dummy control and select gates504,1204(seeFIG. 49) are removed to form a pair of logic gate openings1702, a pair of select gate openings1704, and a pair of control gate openings1706respectively in place of the removed gates. Such removal may, for example, be performed by an etch into the dummy logic gates1202and the dummy control and select gates504,1004with an etchant that is highly selective (i.e., has a high etch rate) for the gates relative to surrounding structure.

As illustrated by the cross-sectional view5100ofFIG. 51, a high κ dielectric layer5102is formed conformally lining the logic, select, and control gate openings1702,1704,1706, and a metal layer5104is formed filling the logic, select, and control gate openings1702,1704,1706over the high κ dielectric layer1502. The high κ dielectric layer1502and the metal layer1504may, for example, be formed by vapor deposition, sputtering, some other deposition process, or a combination of the foregoing.

As illustrated by the cross-sectional view5200ofFIG. 52, a planarization is performed into the high κ dielectric layer5102(seeFIG. 51) and the metal layer5104(seeFIG. 51) to form a logic gate130and a high κ logic gate dielectric layer136stacked in each of the logic gate openings1702(seeFIG. 51). Further, the planarization forms a control gate112and a high κ control gate dielectric layer124stacked in each of the control gate openings1706(seeFIG. 49). Further yet, the planarization forms a select gate110and a high κ select gate dielectric layer122stacked in each of the select gate openings1704(seeFIG. 51). The planarization may be performed by, for example, CMP or some other planarization process.

As illustrated by the cross-sectional view5300ofFIG. 53, a second ILD layer140bis formed covering the structure ofFIG. 52. In some embodiments, the second ILD layer140bis formed by vapor deposition, sputtering, or some other deposition process.

WhileFIGS. 21-53illustrate the replacement of the dummy logic gates1202(seeFIG. 49) and the dummy control and select gates504,1204(seeFIG. 49) with HKMG stacks, it is to be appreciated that the replacement may not be performed for all of the dummy gates in other embodiments. For example, the dummy select and/or control gates1204,504may not be replaced with HKMG stacks. In such embodiments, the dummy gates that are not replaced are masked during gate removal atFIG. 50and are subsequently used in production.

In view of the foregoing, some embodiments of the present application provide a method for manufacturing an IC. A gate stack is formed on a semiconductor substrate. The gate stack comprises a charge storage film and a control gate overlying the charge storage film. Further, the control gate includes a first material. A gate layer is formed covering the semiconductor substrate and the gate stack. The gate layer includes the first material. A top surface of the gate layer is recessed to below a top surface of the gate stack. The gate layer is patterned to form a select gate bordering the control gate, and to further form a logic gate spaced from the select and control gates. An ILD layer is formed laterally between the control, select, and logic gates. The ILD layer is formed with a top surface that is even with top surfaces respectively of the control, select, and logic gates. The control, select, or logic gate is replaced with a new gate. The new gate includes a second material different than the first material.

Further, other embodiments of the present application provide an IC. The IC comprises a semiconductor substrate, a memory cell, and a logic device. The memory cell is on the semiconductor substrate. Further, the memory cell comprises a pair of source/drain regions in the semiconductor substrate, and further comprises a select gate, a charge storage film, a high κ control gate dielectric layer, and a control gate. The source/drain regions define a selectively-conductive channel extending continuously from one of the source/drain regions to another one of the source/drain regions. The select gate and the charge storage film are on the selectively-conductive channel. The high κ control gate dielectric layer overlies the charge storage film. The control gate is metal and overlies the high κ control gate dielectric layer. The logic device is on the semiconductor substrate, laterally spaced from the memory cell. Further, the logic device comprises a logic gate.

Further yet, other embodiments of the present application provide another method for manufacturing an IC. A pair of gate stacks is formed on a memory region of a semiconductor substrate. The gate stacks each comprise an ONO charge storage film and a polysilicon control gate overlying the ONO charge storage film. A polysilicon gate layer is formed covering and conformally lining the semiconductor substrate and the gate stacks. An ARC layer is formed covering the polysilicon gate layer. The ARC layer and the polysilicon gate layer are simultaneously etched until the ARC layer has been removed and a top surface of the polysilicon gate layer has been recessed to below top surfaces of the gate stacks. The gate layer is patterned to form a pair of polysilicon select gates on the memory region of the semiconductor substrate, respectively bordering the polysilicon control gates of the gate stacks. Further, the gate layer is patterned to further form a polysilicon logic gate on a logic region of the semiconductor substrate that is spaced from the memory region of the semiconductor substrate. An ILD layer is formed laterally between the polysilicon control, select, and logic gates. The ILD layer is formed with a top surface that is even with top surfaces respectively of the polysilicon control, select, and logic gates. The polysilicon control, select, and logic gates replaced respectively with HKMG stacks, each comprising a high κ dielectric layer and a metal gate overlying the high κ dielectric layer.