Chip to package interface

In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip disposed within an encapsulant, and a first coil disposed in the semiconductor chip. A dielectric layer is disposed above the encapsulant and the semiconductor chip. A second coil is disposed above the dielectric layer. The first coil is magnetically coupled to the second coil.

TECHNICAL FIELD

The present invention relates generally to semiconductor packages, and more particularly to chip to package interfaces.

BACKGROUND

Recently, interest in the millimeter-wave spectrum at 30 GHz to 300 GHz has drastically increased. The emergence of low cost high performance Si-based technologies has opened a new perspective for system designers and service providers because it enables the development of millimeter-wave radio at the same cost structure of radios operating in the gigahertz range or less. In combination with available ultra-wide bandwidths, this makes the millimeter-wave spectrum more attractive than ever before for supporting a new class of systems and applications ranging from ultra-high speed data transmission, video distribution, portable radar, sensing, detection and imaging of all kinds.

However, taking advantage of the millimeter-wave radio spectrum requires the ability to design and manufacture low cost, high performance RF-front-ends for millimeter-wave semiconductor devices.

SUMMARY OF THE INVENTION

In accordance with an embodiment of the present invention, a semiconductor package comprises a semiconductor chip disposed within an encapsulant. A first coil is disposed in the semiconductor chip. A dielectric layer is disposed above the encapsulant and the semiconductor chip. A second coil is disposed above the dielectric layer. The first coil is magnetically coupled to the second coil.

In accordance with an alternative embodiment of the present invention, a semiconductor device comprises a first coil of a transformer disposed within a semiconductor chip, and a second coil of the transformer disposed within an insulating material outside the semiconductor chip. The first and the second coils form the transformer.

In accordance with an alternative embodiment of the present invention, a method of forming a semiconductor package comprises forming a semiconductor chip having a first coil disposed in an uppermost metal level. A reconstituted wafer comprising the semiconductor chip is formed. A dielectric layer is formed over the reconstituted wafer. A second coil is formed over the dielectric layer. The second coil is configured to magnetically couple with the first coil.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Many applications based on wireless transmission at millimeter wave frequencies may need a package structure that protects the components within the package from mechanical and environmental stress without significantly increasing packaging costs. Further, signal loss introduced by the transition from the printed circuit board to the chip receiver/transmitter interface of the semiconductor package may limit performance of millimeter wave semiconductor chips. This problem is exacerbated when the signal transition from the millimeter wave integrated circuit chip to the printed circuit board is single ended because of losses due to the signal return path. Differential signals, which are measured between two nodes that have equal and opposite excursions around a common mode potential, in contrast, are more immune to common mode noise. However, a single ended signal interface is less complex to route on the printed circuit board. In various embodiments, these and other problems are solved using a millimeter wave embedded wafer level semiconductor package which includes a transformer for providing a single ended package input/output to the board while enabling the use of a differential signal interface at the chip.

A schematic layout of the semiconductor package will be described usingFIG. 1. Alternative layouts will be described usingFIGS. 16 and 17. Structural embodiments of the semiconductor package will be described usingFIGS. 2-5. Embodiments of fabricating the semiconductor package will be described usingFIGS. 6-15.

FIG. 1illustrates a millimeter wave semiconductor package in accordance with an embodiment.

Referring toFIG. 1, a semiconductor package50includes a semiconductor chip100, which includes a front-end circuit10for a transmitter or a receiver. The front-end circuit10is coupled to an antenna60through a transformer45. The transformer45includes a first coil30, which is part of the semiconductor chip100and a second coil40which is outside the semiconductor chip100but is part of the semiconductor package50. The antenna60may be part of the semiconductor package50or may be a separate unit coupled to the semiconductor package50through a printed circuit board.

As illustrated, the semiconductor package50has a single ended input/output, which is coupled to the antenna60. A single ended signal interface may be easily routed on the printed circuit board unlike a double ended signal path. In contrast to alternative solutions such as the use of the on-chip balun to enable a single ended chip input/output, which result in significant losses (e.g., greater than 1 dB) that sum-up with the losses of the chip-to-package connection, embodiments of the invention have much lower overall signal loss through the package. Advantageously, in various embodiments of the present invention, the chip interface is not single ended minimizing signal loss while in contrast the package interface is single ended which helps to minimize complexity at the printed circuit board level. The antenna60may also be part of the printed circuit board in other embodiments.

In various embodiments, the signal transfer from the semiconductor chip100to the semiconductor package50is implemented using a stacked transformer45, which acts as a balun, with an on-chip differential coil (first coil30) and an on-package single ended coil (second coil40). Advantageously, the first coil30(on-chip differential coil) provides a fully differential connection toward the chip stages, while the second coil40(upper on-package coil) provides direct single-ended connection to the printed circuit board. Consequently, embodiments of the invention provide on-chip differential circuits with high common-mode immunity and simple routing on the printed circuit board. As will be described in more detail, embodiments of the invention may be applied to either or both receiver and transmitter chip-in-package millimeter wave designs.

As illustrated, the front-end circuit10may include a differential signal circuit20, which may include a MOSFET differential pair in one embodiment. The MOSFET differential pair comprises a first transistor M1 and a corresponding second transistor M2 coupled to a common source node. The MOSFET differential pair has a first input voltage node V1inand a second input voltage node V2inthereby forming a differential input, and a first output voltage node V1outand a second output voltage node V2outthereby forming a differential output. As a consequence, the maximum and minimum voltage levels are well defined and independent of the input common mode. In various embodiments, the device parameters for the first transistor M1 and the second transistor M2 are identical. The transistors are biased using a common current source, and to a supply voltage VDD through the resistors.

FIG. 2, which includesFIG. 2A-2D, illustrates a semiconductor package for millimeter wave integrated circuits in accordance with embodiments of the present invention.FIG. 2Aillustrates a sectional top view whileFIGS. 2B-2Dillustrate different cross-sectional views.FIG. 2is one implementation of the semiconductor circuit illustrated inFIG. 1.

Referring toFIG. 2A, a semiconductor package50includes a chip100disposed within. The chip100includes a plurality of contact pads110disposed on a main surface. The semiconductor package50is an embedded wafer level semiconductor package in one or more embodiments. Further, the semiconductor package50is a fan-out package having a plurality of external contact pads210.

Embedded wafer level packaging is an enhancement of the standard wafer level packaging in which the packaging is realized on an artificial wafer. In a fan-out type package, some of the external contact pads210and/or conductor lines connecting the semiconductor chip100to the external contact pads210are located laterally outside of the outline of the semiconductor chip100or at least intersect the outline of the semiconductor chip100. Thus, in fan-out type packages, a peripherally outer part of the package of the semiconductor chip100is typically (additionally) used for electrically bonding the semiconductor package50to external applications, such as application boards, etc. This outer part of the semiconductor package50encompassing the semiconductor chip100effectively enlarges the contact area of the semiconductor package50in relation to the footprint of the semiconductor chip100, thus leading to relaxed constraints in view of package pad size and pitch with regard to later processing, e.g., second level assembly.

A first coil30is disposed within the semiconductor chip100at a top surface and coupled to the front-end circuit10(see alsoFIG. 2B). A second coil40is disposed over the semiconductor chip100and coupled to the plurality of external contact pads210of the semiconductor package50. Further, a plurality of redistribution lines260couple the plurality of contact pads110on the semiconductor chip100with the plurality of external contact pads210on the semiconductor package50.

FIG. 2Billustrates a cross-sectional view of the semiconductor package in accordance with an embodiment of the present invention.

Referring toFIG. 2B, the semiconductor chip100is disposed within an encapsulant220. The semiconductor chip100comprises a substrate150, which may include active devices formed within. The metallization layer stack120is disposed over the substrate150. Metallization layer stack120may comprise a number of metal levels in various embodiments, for example, the metallization layer stack120may comprise ten or more metal levels in one embodiment. In another embodiment, the metallization layer stack120may comprise four or more metal levels.

A first coil30is disposed within the metallization layer stack120. In one embodiment, the first coil30is disposed within an uppermost metal level of the metallization layer stack120.

A passivation layer130is disposed over the metallization layer stack120. The passivation layer130is configured to protect the underlying metallization layer stack120. The passivation layer130may comprise an oxide such as silicon oxide in one or more embodiments. In alternative embodiments, the passivation layer130may comprise a nitride material. In further embodiments, the passivation layer130may comprise other dielectric materials such as high-k or even low-k materials.

As illustrated, the encapsulant220surrounds the sidewalls of the semiconductor chip100. A first dielectric layer230is disposed over the encapsulant220and the semiconductor chip100. A second dielectric layer240is disposed over the first dielectric layer230. A third dielectric layer250is disposed over the second dielectric layer240. The first, the second, and the third dielectric layers230,240, and250may comprise a same or different material in different embodiments.

A second coil40is disposed within the second dielectric layer240. The second coil40is separated from the first coil30by the first dielectric layer230and the passivation layer130. Advantageously, in various embodiments of the invention, the signal coupling between the first coil30and the second coil40is performed by means of the interposed dielectric that is formed partly during the fabrication of the chip100(passivation layer130) and partly during the fabrication of the semiconductor package50(first dielectric layer230). Thus, in various embodiments, the separation between the first coil30and the second coil40may be controlled either during the chip fabrication process or subsequently during the embedded wafer level processing. Thus, the signal coupling may be controlled tightly in various embodiments of the present invention.

Referring toFIG. 2C, a plurality of redistribution lines260is disposed in the second dielectric layer240. The plurality of redistribution lines260are metal lines that couple the plurality of contact pads110with a plurality of external contact pads210of the semiconductor package50.

The plurality of external contact pads210may include a first conductive liner270such as a diffusion barrier layer. The first conductive liner270may be formed over the plurality of redistribution lines260and sidewalls of the opening in the third dielectric layer250. A second conductive liner280may be formed over the first conductive liner270. The second conductive liner280may be an under bump metallization layer (UBM) layer. A solder ball290is disposed on the second conductive liner280. Thus, the solder balls290may be mounted onto a printed circuit board. The solder balls290may comprise solder materials such as lead-tin materials. Similarly, in another embodiment, the solder balls290may comprise lead free solder materials such as 97.5 Sn/2.6 Ag (97.5/2.5). In various embodiments, the first and the second conductive liners270and280, and the solder balls290may comprise any suitable solder material. For example, in one embodiment, the solder material may comprise a lead (Pb) layer followed by a tin (Sn) layer. In another embodiment, a SnAg may be deposited as the solder material. Other examples include SnPbAg, SnPb, PbAg, PbIn, and lead free materials such as SnBi, SnAgCu, SnTn, and SiZn. In various embodiments, other suitable materials may be deposited.

FIG. 2Dillustrates a different cross-sectional view showing the first coil30, the second coil40, a redistribution line of the plurality of redistribution lines260coupled to one of the plurality of contact pads110on the chip100and to one of the plurality of external contact pads210.

Advantageously, in various embodiments, both the first and the second coils30and40are far removed away from the substrate150in contrast to on-chip transformer coils, thus reducing signal losses towards the substrate150. In various embodiments, the chip to board transition loss (including also conversion from the differential signal to single ended signal) may be lower than 2 dB at 80 GHz.

Also in various embodiments, the on chip signal pads may not be needed because the signal coupling is electromagnetic, as illustrated inFIG. 2A. This is big benefit at mm-wave frequencies because the capacitance introduced by the on-chip pad on the signal path has a low-pass behavior and therefore has a negative impact on the signal transfer. In such cases, the capacitance, which may range from 40 fF to 80 fF depending on the technology, is compensated by shunt resonance with an on-chip stub connected between the pad and ground. However, the compensation has to be frequency selective to provide a high-ohmic impedance over the operating frequency.

The elimination of the on-chip signal pads using embodiments of the invention provides more flexibility in the layout of the interface, which can be further optimized according to transition performance and taking into account only chip and package geometrical layout constraints, without limitations introduced by other devices. For example, a typical layout limitation is given by the fixed gap between the chip pad pitch (distance between adjacent pads of the plurality of contact pads110on the chip100, e.g., which is about 100 μm to about 150 μm) and the package pad pitch (distance between adjacent pads of the plurality of external contact pads210, e.g., which is about 400 μm to about 500 μm). This big difference between the chip pad pitch and the package pad pitch is partly responsible of the length of the redistribution lines260, which is directly proportional to the losses.

Further, advantageously, the absence of physical contact by metallization layers between the semiconductor package50and the chip100at the mm-wave front-end interface may enhance the robustness of the mm-wave interface of the packaged device against mechanical and/or environmental stresses and aging. Also, the electromagnetic coupling at the chip-package interface automatically implements an electro-static discharge protection device, avoiding the need to adopt other on-chip protection structure that occupy silicon area and deteriorate the performance of the mm-wave signal.

FIG. 3illustrates an mm-wave semiconductor package mounted on a printed circuit board in accordance with an embodiment of the present invention.

The semiconductor package50is mounted on to a circuit board300using the plurality of external contact pads210. The circuit board300may include the antenna (illustrated inFIG. 1) or alternatively a discrete antenna may be mounted on the circuit board300.

FIG. 4, which includesFIGS. 4A-4C, illustrates the semiconductor package in accordance with alternative embodiments of the present invention.FIG. 4A-4Billustrate top view whileFIG. 4Cillustrates a 3D drawing of an embodiment of the transformer.

In various embodiments, the semiconductor package50may include transformer coils having different configurations such as multiple coils or multiple turn or multiple loop coils.FIG. 4Aillustrates an embodiment in which the first coil30and the second coil40are configured with multiple loops. In this embodiment, the first coil30and the second coil40have a spiral shape.FIG. 4Billustrates a different alternative shape of the first and the second coils30and40. InFIG. 4B, the first coil30and the second coil40have a rectangular shaped coil.FIG. 4Cillustrates a 3D view of the first coil30and the second coil40comprising rectangular coils sketched inFIG. 4Bin another alternative embodiment of the invention. As illustrated, the first coil30may have an underpass21within the metallization layer stack120. Through the underpass21, the first coil30may be coupled to input/output nodes within the chip100while the second coil40may have an overpass22, which may be coupled to the plurality of external contact pads210of the semiconductor package50.

FIG. 5, which includesFIGS. 5A-5E, illustrates an alternative embodiment of the semiconductor package in which the transformer coils are formed over multiple metal levels.

In one embodiment, the top view is similar to the embodiment described inFIG. 2. However, as illustrated inFIG. 5Bin the cross-sectional view, the first coil30is formed over a plurality of metal levels. For example, in one embodiment, the first coil30has a first metal level coil31, a second metal level coil32, a third metal level coil33, and a fourth metal level coil34. Each of the metal level coils may be interconnected through vias36. Thus, a multi-layer coil may be formed in embodiments of the invention.FIG. 5Dillustrates a 3D drawing of an embodiment of the transformer where a two-layer coil implements the first coil30and a single-layer coil implements the second coil40. This embodiment is an example embodiment of the embodiment described usingFIG. 5B.

Further, in some embodiments as illustrated inFIG. 5C, the second coil40may also be formed in multiple metal levels over the first dielectric layer230. For example, in one embodiment, the second coil40has a first redistribution level coil41, a second redistribution level coil42coupled through a redistribution level via43. The embodiments ofFIG. 5may be combined with embodiments illustrated inFIG. 4thereby forming multi-layer and multi-turn coils in one or more embodiments.FIG. 5Eillustrates a 3D drawing of an embodiment of the transformer where a two-layer coil implements the first coil30and a two-layer coil implements the second coil40.FIG. 5Eis one example embodiment of the embodiment described usingFIG. 5C.

FIGS. 6-15illustrate a semiconductor package during various stages of fabrication in accordance with an embodiment of the present invention.

FIG. 6, which includesFIGS. 6A-6C, illustrates a semiconductor substrate after formation of device regions and metallization layers, whereinFIGS. 6A and 6Billustrates a cross-sectional view andFIG. 6Cillustrates a top view.

Referring toFIG. 6A, a semiconductor substrate150after the completion of front end processing and back end processing is illustrated. The semiconductor substrate150has a plurality of semiconductor devices, i.e., chips100, formed within. Each chip of the chips100may be any type of chip. For example, each of the chips100may be a logic chip, a memory chip, an analog chip, an RF-chip and other types of chips. Each of the chips100may comprise a plurality of devices such as transistors or diodes forming an integrated circuit or may be a discrete device such as a single transistor or a single diode.

The chips100may comprise any type of circuitry in one or more embodiments. In one or more embodiments, the semiconductor chips100may comprise an integrated circuit chip for wireless communication. In one or more embodiments, each of the semiconductor chips100comprises outputs and/or inputs for coupling to an antenna structure for wireless communication. The semiconductor chip100may be a silicon chip in one or more embodiments. In various embodiments the semiconductor chip100may be a monolithic microwave integrated circuit (MMIC) chip for microwave engineering processes. MMIC chips may perform functions such as microwave mixing, power amplification, low noise amplification, and high-frequency switching. MMIC chips may be mass-produced and are dimensionally small, for example, from around 1 mm2to about 10 mm2, which enables the operation of high-frequency devices such as smart phones and cell phones, for example.

In one embodiment, the substrate150may comprise a semiconductor wafer such as a silicon wafer. In other embodiments, the substrate150may be a wafer comprising other semiconductor materials including alloys such as SiGe, SiC or compound semiconductor materials such as GaAs, InP, InAs, GaN, sapphire, silicon on insulation, for example.

Referring toFIG. 6A, device regions101are disposed within the substrate150. The device regions101may include doped regions in various embodiments. Further, some portion of the device regions101may be formed over the substrate150. The device regions101may include active regions such as channel regions of transistors.

The substrate150comprises a top surface11and an opposite bottom surface12. In various embodiments, the device regions101are formed closer to the top surface11of the substrate150than the bottom surface12. Active devices may be formed in an upper part of the device regions101of the substrate150. Device regions101extends over a depth dDR, which depending on the device, is about 10 μm to about 200 μm, and about 50 μm in one embodiment.

In various embodiments, all necessary interconnects, connections, pads etc. for coupling between devices of the device regions101and/or with external circuitry are formed over the substrate150. Accordingly, a metallization layer stack120is formed over the substrate150. The metallization layer stack120may comprise one or more levels of metallization. Each level of metallization may comprise metal lines or vias embedded within an insulating layer. The metallization layer stack120may comprise metal lines and vias to contact the device regions101and also to couple different devices within each chip100.

FIG. 6Billustrates a magnified cross-sectional view of a single semiconductor chip100showing the metallization layer stack120. A first coil30is formed within the metallization layer stack120. In various embodiments, the first coil30is formed within the uppermost metal level of the metallization layer stack120. The first coil30may be formed using a damascene or a dual damascene process in one embodiment. In one embodiment, the first coil30comprises copper. In an alternative embodiment, the first coil30comprises aluminum formed using a blanket deposition and subtractive etch process.

A passivation layer130, which may be a protective layer, may be formed over the metallization layer stack120before further processing. The passivation layer130may be deposited or coated in various embodiments. The passivation layer130may comprise an oxide, nitride, polyimide, or other suitable materials known to one skilled in the art. The passivation layer130may comprise a hard mask in one embodiment, and a resist mask in another embodiment. The passivation layer130helps to protect the metallization layer stack120as well as the device regions101during subsequent processing.

Further, a final depth of the chip100will be determined after thinning the substrate150. The substrate150may be thinned from the bottom surface12to expose a surface of the device regions101.

FIG. 6Cillustrates a top view of the substrate150comprising a plurality of chips. Each chip100is separated from each other by a plurality of regions called scribe lines or dicing channels. The substrate150may be singulated or diced along the dicing channels to form individual chips100.

FIG. 7illustrates a magnified cross-sectional view illustrating two of the plurality of chips100. Referring toFIG. 7, the semiconductor chips100are placed over a carrier400. In various embodiments, the top surface11of the semiconductor chips100having active regions is placed facing the carrier400as illustrated inFIG. 4.

The thickness of the plurality of semiconductor chips100from the top surface11to the exposed bottom surface13may be less than 500 μm in various embodiments. The thickness of the plurality of semiconductor chips100from the top surface11to the bottom surface13may be about 200 μm to about 500 μm in one or more embodiments.

Next, the plurality of semiconductor chips100is attached to the carrier400, which provides mechanical support and stability during processing. In various embodiments, the carrier400may be a plate made of a rigid material, for example, a metal such as nickel, steel, or stainless steel, a laminate, a film, or a material stack. The carrier400may have at least one flat surface over which the plurality of semiconductor chips100may be placed. In one or more embodiments, the carrier400may be round or square-shaped although in various embodiments the carrier400may be any suitable shape. The carrier400may have any appropriate size in various embodiments. In some embodiments, the carrier400may include an adhesive tape, for example, a double sided sticky tape laminated onto the carrier400. The carrier400may comprise a frame, which is an annular structure (ring shaped) with an adhesive foil in one embodiment. The adhesive foil may be supported along the outer edges by the frame in one or more embodiments.

The plurality of semiconductor chips100may be attached to the carrier400using an adhesive layer35in various embodiments. In various embodiments, the adhesive layer35may comprise glue or other adhesive type material. In various embodiments, the adhesive layer35may be thin, for example, less than about 100 μm in one embodiment and between 1 μm to about 50 μm in another embodiment.

FIG. 8illustrates the semiconductor package during fabrication after forming a reconstituted wafer in accordance with an embodiment of the invention.

As illustrated inFIG. 8, an encapsulant220is applied over the semiconductor chips100and partially encloses the semiconductor chips100. In one embodiment, the encapsulant220is applied using a molding process such as compression molding, transfer molding process, injection molding, granulate molding, powder molding, liquid molding, as well as printing processes such as stencil or screen printing.

In various embodiments, the encapsulant220comprises a dielectric material and may comprise a mold compound in one embodiment. In other embodiments, the encapsulant220may comprise one or more of a polymer, a copolymer, a biopolymer, a fiber impregnated polymer (e.g., carbon or glass fibers in a resin), a particle filled polymer, and other organic materials. In one or more embodiments, the encapsulant220comprises a sealant not formed using a mold compound, and materials such as epoxy resins and/or silicones. In various embodiments, the encapsulant220may be made of any appropriate duroplastic, thermoplastic, a thermosetting material, or a laminate. The material of the encapsulant220may include filler materials in some embodiments. In one embodiment, the encapsulant220may comprise epoxy material and a fill material comprising small particles of glass or other electrically insulating mineral filler materials like alumina or organic fill materials. The encapsulant220may be cured, i.e., subjected to a thermal process to harden thus forming a hermetic seal protecting the semiconductor chips100. The curing process hardens the encapsulant220thereby forming a single substrate holding the semiconductor chips100. Such a substrate is referred as a reconstituted wafer5, which may be used to form a fan-out package using embedded wafer level packaging.

Embedded wafer level packaging is an enhancement of the standard wafer level packaging in which packaging is realized on an artificial wafer using wafer-like fabrication processes in which multiple packages are packaged using a common reconstituted wafer5. As described previously, in a fan-out type package at least some of the external contact pads and/or conductor lines connecting the semiconductor chip100to the plurality of external contact pads210are located laterally outside of the outline of the semiconductor chip100or at least intersect the outline of the semiconductor chip100. Thus, in fan-out type packages, a peripherally outer part of the package of the semiconductor chip100is typically (additionally) used for electrically bonding the package to external applications, such as application boards, etc. This outer part of the package encompassing the semiconductor chip100effectively enlarges the contact area of the package in relation to the footprint of the semiconductor chip100, thus leading to relaxed constraints in view of package pad size and pitch with regard to later processing, e.g., second level assembly.

FIG. 9illustrates the semiconductor package, during fabrication, after separating the reconstituted wafer from the carrier in accordance with an embodiment of the invention.

Referring toFIG. 9, the carrier400is removed to separate the reconstituted wafer5or artificial wafer. The encapsulant220provides mechanical and thermal stability during subsequent processing. Removing the carrier400also exposes the front surface of the semiconductor chip100. During subsequent processing, the reconstituted wafer5may be subjected to temperatures as high as 300° C. depending on the thermal stability of the encapsulant220in various embodiments.

FIG. 10illustrates a magnified cross-sectional view of the semiconductor package after forming openings to the chip contact pads in accordance with an embodiment of the invention. UnlikeFIGS. 6-9,FIG. 7illustrates a magnified view of a single semiconductor package.

Referring toFIG. 10, the semiconductor chip100may include a plurality of contact pads110formed within a metal layer of the metallization layer stack120. A first dielectric layer230is deposited over the encapsulant220and the chip100.

A first dielectric layer230may be formed over the reconstituted wafer5patterned forming openings410for contact pads. In various embodiments, the first dielectric layer230is an insulating layer and may be deposited or coated. In one or more embodiments, the first dielectric layer230may comprise an oxide layer or an oxide/nitride layer stack. In other embodiments, the first dielectric layer230may comprise silicon nitride, silicon oxynitride, FTEOS, SiCOH, polyimide, photoimide, BCB or other organic polymers, or combinations thereof. An optional insulating liner may be formed above the first dielectric layer230. The optional insulating liner may comprise a nitride layer, in one embodiment. In various embodiments, the optional insulating liner may comprise FTEOS, SiO2, SiCOH, or other low-k materials. Using a photolithography process, the first dielectric layer230is patterned to open the plurality of contact pads110, which are bond pads on a metal level of the semiconductor chips100.

FIG. 11illustrates a magnified view of the semiconductor package after fabrication of a seed layer for a redistribution layer in accordance with an embodiment of the invention.

Referring toFIG. 11, a conductive liner430is deposited. In various embodiments, the conductive liner430is deposited using a deposition process to form a conformal layer. The conductive liner430may comprise a diffusion barrier and a conductive seed layer in various embodiments. The diffusion barrier may comprise Ti, Ta, Ru, W, combinations thereof, or a nitride, silicide, carbide thereof. Examples of such combinations include TiN, TaN, and WN, and TiW. In various embodiments, the conductive liner430is deposited using a chemical vapor deposition, plasma vapor deposition or atomic layer deposition. In various embodiments, the diffusion barrier comprises a thickness of about 20 nm to about 200 nm. The conductive liner430may be a diffusion barrier metal and prevents out-diffusion of copper from the last metal line of the redistribution metallization layer as well as prevents intermixing with further metallic layers.

In various embodiments, the conductive seed layer is deposited using a deposition process to form a conformal layer. In various embodiments, the conductive seed layer is deposited using a chemical vapor deposition, plasma vapor deposition or atomic layer deposition. In various embodiments, the conductive seed layer comprises a thickness of about 20 nm to about 200 nm. The conductive seed layer provides the seed layer for the growth during the subsequent electroplating process. In various embodiments, the conductive seed layer may comprise copper or other metals like Al, W, Ag, Au, Ni, or Pd.

As next illustrated inFIG. 11, a thick photo resist layer440is deposited over the conductive liner430. In various embodiments, the photo resist layer440is several microns thick, and varies from about 1 μm to about 10 μm, in one embodiment. After deposition, the photo resist layer440fills the openings410previously formed in the first dielectric layer230. The photo resist layer440is exposed and developed. The patterned photo resist layer440comprises patterns for both redistribution metal lines and contact pads. As a consequence, the photo resist layer440is removed in regions allocated to form the second coil of the transformer.

FIG. 12illustrates a magnified view of the semiconductor package after fabrication of a redistribution layer in accordance with an embodiment of the invention.

Referring next toFIG. 12, redistribution lines260and a second coil40are formed by electroplating a fill metal over the conductive liner430exposed between the patterned photo resist layer440. In various embodiments, the fill metal comprises copper, although in some embodiments, other suitable conductors are used. The seed layer of the conductive liner430may comprise the same material as the material of the subsequent metal lines to enable electroplating, in one embodiment. In various embodiments, the redistribution lines260may comprise multiple layers, for example, Cu/Ni, Cu/Ni/Pd/Au, Cu/NiMoP/Pd/Au, or Cu/Sn, in one embodiment.

The patterned photo resist layer440is stripped to expose the conductive liner430. The exposed conductive liner430is selectively etched and removed, for example, using a wet etch chemistry.

FIG. 13illustrates a magnified view of the semiconductor package after forming a protective dielectric layer around the redistribution lines in accordance with an embodiment of the invention.

A second dielectric layer240is formed over the first dielectric layer230. The second dielectric layer240surrounds the redistribution lines260and the second coil40in various embodiments. The second dielectric layer240may be deposited or coated in various embodiments. The second dielectric layer240may comprise a same material as the first dielectric layer230in one or more embodiments. Alternatively, the second dielectric layer240may comprise a different material. The structure at this stage is illustrated inFIG. 13and includes redistribution lines260and the second coil40.

FIG. 14illustrates a magnified view of the semiconductor package after forming openings for contacts in a dielectric layer in accordance with an embodiment of the invention.

A third dielectric layer250is formed over the second dielectric layer240. The third dielectric layer250may be deposited or coated in various embodiments. Openings for solder contacts are made within the third dielectric layer250.

FIG. 15illustrates a magnified view of the semiconductor package after forming solder ball contacts in accordance with an embodiment of the invention.

In one or more embodiments, a solder flux and a solder material may be deposited within the openings in the third dielectric layer250. The solder material may be electroplated, although, in other embodiments, other processes such as electroless plating or deposition processes such as vapor deposition may also be used. The solder material may be a single layer or comprise multiple layers with different compositions. For example, in one embodiment, the solder material may comprises a lead (Pb) layer followed by a tin (Sn) layer. In another embodiment, a SnAg may be deposited as the solder material. Other examples include SnPbAg, SnPb, PbAg, PbIn, and lead free materials such as SnBi, SnAgCu, SnTn, and SiZn. In various embodiments, other suitable materials may be deposited.

A thermal treatment may be performed to form the solder balls290illustrated inFIG. 15. The thermal treatment reflows the solder material and the heating forms the solder balls290. For example, in the embodiment when Pb/Sb layer is deposited, after reflow, high lead alloys including 95 Pb/5 Sn (95/5) or 90 Pb/10 Sn (95/10) with melting temperatures in excess of 300° C. are formed. In a different embodiment, eutectic 63 Pb/37 Sn (63/37) with a melting temperature of 183° C. is formed. Similarly, lead free solder balls290may be formed having a composition of 97.5 Sn/2.6 Ag (97.5/2.5). The solder balls290comprise a homogeneous material and have a well-defined melting temperature. For example, the high melting Pb/Sn alloys are reliable metallurgies which are resistant to material fatigue. The metal from the plurality of external contact pads210may also diffuse and intermix during the thermal treatment in some embodiments.

The reconstituted wafer5may now be thinned and singulated to form individual semiconductor packages.

FIG. 16, which includesFIGS. 16A and 16B, illustrates a circuit schematic of a semiconductor package in accordance with an alternative embodiment of the present invention.

In this embodiment, the second coil40is also a differential coil. Therefore, unlike the embodiment illustrated inFIG. 1, in this embodiment, none of the ends of the second coil40is connected to a ground potential. For example, both the ends of the second coil40may be coupled to a antenna component61coupled to the antenna60. For example, in one case illustrated inFIG. 16A, the conversion from differential signal to single ended signal may be performed within the antenna component61, which may be part of the printed circuit board or may be a standalone unit. As discussed in prior embodiments, the second coil40is outside the chip100while the first coil30is within the chip100.

In another embodiment illustrated inFIG. 16B, the second coil40may be connected directly or by a coupling component61B to a differential antenna62, which may be part of the printed circuit board or may be a stand-alone device in various embodiments.

FIG. 17illustrates a circuit schematic of a semiconductor package illustrating both a receiver and a transmitter in accordance with an alternative embodiment of the present invention.

The transmitter circuitry is illustrated by the suffix “A” while the receiver circuitry is illustrated by the suffice “B.” Thus, a transmitter side transformer45A includes a first transmitter coil30A and a second transmitter coil40A while a receiver side transformer45B includes a first receiver coil30B and a second receiver coil40B. Similarly, a transmitter side front-end circuit10A is coupled to the transmitter side transformer45A while a receiver side front-end circuit10A is coupled to the receiver side transformer45B. The transmitter side front-end circuit10A may include a first differential signal circuit20A while the receiver side front-end circuit10B a second differential signal circuit20B.

Gain losses due to differential-to-single-ended conversions and vice versa have different effects on the transmitter side front-end circuit10A and the receiver side front-end circuit10B. For example, the input loss due to the signal conversion in the receiver side turns into noise figure degradation (conversion loss in dB is noise figure in dB) since signal amplification is provided only after conversion. This noise figure degradation cannot be compensated anymore and therefore this noise affects the overall performance of the receiver side front-end circuit10B. However, for the differential-to-single-ended conversion at the transmitter side front-end circuit10A, the signal loss can be almost completely compensated by a gain increase in the transmitter chain, which may be, for example, achieved by increasing the current.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. As an illustration, the embodiments described inFIG. 1-15may be combined with each other in various embodiments. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention.