Using a standard USB Type-C connector to communicate both USB 3.x and displayport data

According to one embodiment, an electronic device includes a USB Type-C connector connected to a second electronic device, a processor connected to the USB Type-C connector and including four terminals outputting an image signal, and a USB controller connected to the USB Type-C connector and including two terminals outputting USB 3.x signal. The USB Type-C connector includes two USB 2.0 pins D and D defined under USB Type-C standard and four USB 3.x pins TX1, RX1, TX2 and RX2 defined under the USB Type-C standard. The image signal and the USB 3.x signal are output via the two USB 2.0 pins D and D and the four USB 3.x pins TX1, RX1, TX2 and RX2.

FIELD

Embodiments described herein relate generally to connection between electronic devices.

BACKGROUND

One of examples of interfaces for connection between electronic devices is universal serial bus (USB) 3.1 standard. The standard includes USB Type-C Cable and Connector Specification (hereinafter called Type-C standard). A host or a device supports an alternate mode (or alternative mode) such as repurposing the connector for docking-specific applications, under USB Type-C standard. In the alternate mode, several pins of USB Type-C connector can be reconfigured, and it is examined that display signals, for example, DisplayPort (registered trademark) signals are assigned to several pins of USB Type-C connector. A USB dock capable of simultaneously supporting DisplayPort standard and USB 3.0/3.1 (hereinafter called USB 3.x) standard is thereby implemented.

However, the maximum bit rate is 21.6 Gbps with signal lines of four lanes (four sets) under DisplayPort standard, but the USB dock cannot simultaneously receive USB 3.x signals and DisplayPort signals of four lanes, and can receive only DisplayPort signals of two lanes (lane 0 and lane 1) together with USB 3.x signal.

DETAILED DESCRIPTION

In general, according to one embodiment, an electronic device includes a USB Type-C connector, a processor, and a USB controller. The USB Type-C connector is connectable to a second electronic device and includes two USB 2.0 pins D and D defined under USB Type-C standard and four USB 3.x pins TX1, RX1, TX2 and RX2 defined under the USB Type-C standard. The processor is connected to the USB Type-C connector and includes four terminals outputting an image signal. The USB controller is connected to the USB Type-C connector and includes two terminals outputting USB 3.x signal. The image signal and the USB 3.x signal are output via the two USB 2.0 pins D and D and the four USB 3.x pins TX1, RX1, TX2 and RX2.

FIG. 1Ashows an example of a system configuration of embodiments. A notebook-type personal computer (hereinafter called PC)10and a tower-type USB dock20are connected by a USB Type-C cable22. The PC10is also called a host, and the USB dock20is also called a device. The PC is not limited to the notebook type, but may also be a slate type or tablet type. The PC10includes a body11and a display unit12. The display unit12includes a liquid crystal display (LCD)15. The display unit12is attached to the body11so as to be rotatable by hinges16A and16B, and an opened position at which a top surface of the body11is exposed and a closed position at which the top surface of the body11is covered are changed. The body11has a housing shaped in a thin box, and a keyboard13, a touchpad14and the like are arranged on the top surface of the housing. Various connectors are provided on a back surface of the USB dock20together with a connector connected to the cable22. Various connectors include a USE connector, a DisplayPort connector, a LAN connector, an HDMI connector, a DVI connector, an audio output connector, a DC input connector connected to an AC adapter, and the like.

The connection between the PC10and the USE dock20is not limited to the connection using the cable22, but the PC10may be placed on a slate-shaped USB dock30to make direct connection between the PC10and the USB dock as shown inFIG. 1B. A receptacle is disposed on an upper surface of the USB dock30while a plug is disposed on a lower surface of the PC10or a plug is disposed on an upper surface of the USB dock30while a receptacle is disposed on a lower surface of the PC10, though not illustrated.

Electric configuration of the PC10and the USE dock20(or30, hereinafter20), of the first embodiment, will be described with reference toFIG. 2AandFIG. 2B. The PC10includes a USB Type-C receptacle40as shown inFIG. 2A, and the USB dock20includes a USB Type-C plug70as shown inFIG. 2B. The receptacle40and the plug70are hereinafter called connectors.

The USB Type-C connectors include two USB 2.0 data bus pins D+/D− and D+/D−, four USB 3.x data bus pins TX1+/TX1−, TX2+/TX2−, RX1+/RX1− and RX2+/RX2−, a USB power pin VBUS, a ground pin GND, two configuration channel pins CC1 and CC2, and a sideband use pin SBU. Each of the data bus pins D+/D−, D+/D−, TX1+/TX1−, TX2+/TX2−, RX1+/RX1− and RX2+/RX2− is a pin which delivers the differential signal. The USB power pin VBUS, the ground pin GND, and the sideband use pin SBU are not illustrated since these pins are not directly related to the operations of the embodiment.

As shown inFIG. 2A, the PC10includes at least a CPU42, a Type-C controller46, an embedded controller (hereinafter EC)48, a GPU50, a USB controller52, a demultiplexer54, first and second multiplexers56and58, and the receptacle40, in relation to the connection with the USB dock. General PC constituent elements, for example, a keyboard controller, a power supply controller and the like are not illustrated since they are not directly related to the operations of the embodiment.

The Type-C controller46carries out communications with a Type-C controller in the USB dock20which will be explained later, and determines whether the USB dock20is the dock according to the present embodiment or not. The EC48controls distribution of the demultiplexer54and selection of the second multiplexer58under control of the Type-C controller46. The Type-C controller46controls selection of the first multiplexer56. The Type-C controller46and the EC48may not be provided as separate bodies, but the Type-C controller46or the EC48may control the demultiplexer54and the second multiplexer58. The GPU50which processes a video signal includes a DisplayPort controller51which outputs DisplayPort signal. The Type-C controller46, the EC48, the GPU50, and the USB controller52are connected to a bus line44of the CPU42. The USE controller52includes terminals TX+/TX− and RX+/RX− for USB 3.x data (differential signals), and a terminal D+/D− for USB2.0 data (a differential signal).

The DP controller51outputs DisplayPort signals (differential signals) of four lanes (four sets). The DisplayPort signals of lane 0 and lane 1 are input to a first input terminal group (two terminals) of the first multiplexer56. The DisplayPort signals of lane 2 and lane 3 are input to an input terminal group (two terminals) of the demultiplexer54. The demultiplexer54distributes an input to either of two outputs, a first output terminal group (two terminals) is connected to a second input terminal group (two terminals) of the first multiplexer56, and a second output terminal group (two terminals) is connected to a first input terminal group (two terminals) of the second multiplexer58.

In the first multiplexer56, two of three inputs are selected as two outputs, and two terminals TX+/TX− and RX+/RX− of the USB controller52are connected to a third input terminal group (two terminals). A first output terminal group of the multiplexer56is connected to two pins TX1+/TX1− and RX1+/RX1− of the receptacle40, and a second output terminal group of the first multiplexer56is connected to two pins TX2+/TX2− and RX2+/RX2− of the receptacle40.

The second multiplexer58selects either of two inputs, and the terminal D+/D− of the USB controller52is commonly connected to the second input terminal group (two terminals). An output terminal group of the second multiplexer58is connected to two pins D+/D− and D+/D− of the receptacle40.

As shown inFIG. 2B, the USB dock20includes at least a Type-C controller72, a USB 3.x hub76and a plug70in relation to the connection with the PC10. The USB dock20may be supplied with the power from the PC10or may include an original power source. If the USB dock20includes a power source, the USB dock20may supply the power to the PC10. An ID indicating a type is defined for the USB dock, and the Type-C controller72includes a memory74which stores the ID. Two pins TX1+/TX1− and RX1+/RX1− of the plug70are connected to two input terminals of the USB 3.x hub76.

The USB dock20includes a DisplayPort terminal group80having four terminals and a USB 3.x terminal group78having two terminals as output terminals. Each of the terminals delivers the differential signal. Four pins TX2+/TX2−, RX2+/RX2−, D+/D−, and D+/D− of the plug70are connected to four pins of the DisplayPort pin group80, respectively. Two output terminals of the USB 3.x hub76are connected to two pins of the USB 3.x pin group78, respectively.

FIG. 3is a flowchart showing an operation of the PC10shown inFIG. 2A. The PC10is assumed to be connected to the USB dock20shown inFIG. 2Bbut may be connected to the other dock. If the PC10detects the connection of the dock, the Type-C controller46inquires the ID from the Type-C controller72of the USB dock20via the pins CC1 and CC2 in block102. The Type-C controller72sends the ID stored in the memory74to the Type-C controller46of the PC10.

The Type-C controller46determines whether a predetermined ID has been received or not, in block104. If the connected USB dock is other than the dock of the type shown inFIG. 2B, the determination result in block104is NO since a predetermined ID is not sent, and a second dock processing which will be explained later will be performed in block200. If the connected USB dock is the dock of the type shown inFIG. 2B, the determination result in block104is YES since a predetermined ID is sent, and steps following block106are performed.

If the Type-C controller46receives the predetermined ID, the EC48sets connection of the input and output of the demultiplexer54as shown inFIG. 2A, in block106. In other words, the input terminal group of the demultiplexer54is connected to the second output terminal group. For this reason, the DisplayPort signals of lane 2 and lane 3 are input to the first input terminal group of the second multiplexer58.

In block108, the Type-C controller46sets connection of the input and output of the first multiplexer56as shown inFIG. 2A. In other words, the first input terminal group of the first multiplexer56is connected to the second output terminal group, and the third input terminal group of the first multiplexer56is connected to the first output terminal group. For this reason, the DisplayPort signals of lane 0 and lane 1 are supplied to two pins TX2+/TX2− and RX2+/RX2− of the receptacle40, and two terminals TX+/TX− and RX+/RX− of the USB controller52are connected to two pins TX1+/TX1− and RX1+/RX1− of the receptacle40, respectively.

In block110, the EC48changes connection of the input and output of the second multiplexer58as shown inFIG. 2A. In other words, the first input terminal group of the second multiplexer58is connected to the output terminal group. For this reason, the DisplayPort signals of lane 2 and lane 3 are supplied to two pins D+/D− and D+/D− of the receptacle40.

For this reason, the DisplayPort signals of lane 0, lane 1, lane 2 and lane 3 are supplied to four pins of the DisplayPort pin group80, two terminals TX+/TX− and RX+/RX− of the USB controller52are connected to the USB 3.x pin group78. The USB dock capable of simultaneously supporting DisplayPort standard (four lanes) and USB 3.x standard can be implemented.

Next, it will be described that the PC10(host) shown inFIG. 2Acan also operate with a USB dock other than the USE dock20shown inFIG. 2B.FIG. 4A,FIG. 4B,FIG. 5A, andFIG. 5Bshow examples of a system configuration in a case where a USB dock20A other than the USB dock20shown inFIG. 2Bis connected to the PC10shown inFIG. 2A. The USB dock20A is a dock which cannot simultaneously support DisplayPort standard (four lanes) and USE 3.x standard, but can change the support of DisplayPort standard (four lanes) alone and the simultaneous support of DisplayPort standard (two lanes) and USB 3.x standard.FIG. 4AandFIG. 4Bshow an example of simultaneously supporting DisplayPort standard (two lanes) and USB 3.x standard, andFIG. 5AandFIG. 5Bshow supporting DisplayPort standard (four lanes) alone.

A hardware configuration of the PC10shown inFIG. 4AandFIG. 5Ais the same as that of the PC10shown inFIG. 2A, but different with respect to connection of the input and output of the demultiplexer54and the multiplexers56and58. The USE dock20A shown inFIG. 4BandFIG. 5Bincludes the DisplayPort pin group80of four lanes and the USB 3.x pin group78, similarly to the USE dock20shown inFIG. 2B, and further includes a Type-C controller88, a multiplexer82, a billboard device86and a USB 3.x hub84.

The billboard device86is connected to the USB 3.x hub84. The device includes the billboard device86to notify for the host that when the device is connected to a host which does not support an alternate mode of USB Type-C standard, the device can be operated under USB standard only. The USB dock of the embodiment shown inFIG. 2Bdoes not include a billboard device since the USB dock is assumed to be connected to the host which supports an alternate mode of USB Type-C standard. However, the USB dock20shown inFIG. 2Bincludes the ID memory74in the Type-C controller72. The USB dock shown inFIG. 4BandFIG. 5Bincludes the billboard device since the USB dock may also be connected to a host which does not support an alternate mode of USB Type-C standard. For this reason, the Type-C controller88does not include the ID memory. The billboard device86sends information for identifying the device to the host when the billboard device86receives the inquiry of the type of the device from the host via the pin D+/D−.

Two pins TX1+/TX1− and RX1+/RX1− of the plug70are connected to the first input terminal group (two terminals) of the multiplexer82, and two pins TX2+/TX2− and RX2+/RX2− of the plug70are connected to the second input terminal group (two terminals) of the multiplexer82. In the multiplexer82, two input terminal groups are selectively connected to three output terminal groups. The first output terminal group (two terminals) of the multiplexer82is connected to each of two input terminals of the USB 3.x hub84, and the second output terminal group (two terminals) and the third output terminal group (two terminals) of the multiplexer82are connected to four pins of the DisplayPort pin group80of four lanes, respectively.

The system operation shown inFIG. 4A,FIG. 4B,FIG. 5A, andFIG. 5Bwill be explained with reference to a flowchart ofFIG. 6. An example of changing operation to simultaneously support DisplayPort standard (two lanes) and USB 3.x standard and then support DisplayPort standard (four lanes) alone will be explained, but the operation may be changed to support DisplayPort standard (four lanes) alone and then simultaneously support DisplayPort standard (two lanes) and USB 3.x standard.

FIG. 6is a flowchart of second dock processing200shown inFIG. 3. In block202, the EC48sets connection of the input and output of the second multiplexer58as shown inFIG. 4A. In other words, the second input terminal group of the second multiplexer58is connected to the output terminal group. For this reason, the D+/D− terminal of the USB controller52is commonly connected to two pins D+/D− and D+/D− of the receptacle40.

In block204, the Type-C controller46sends an inquiry to the Type-C controller88of the USB dock20A via the pins CC1 and CC2 as to whether the USB dock20A is the predetermined dock or not. The Type-C controller88stores information indicating the type of the dock. The predetermined dock indicates a dock shown inFIG. 4BandFIG. 5B, which cannot simultaneously support DisplayPort standard (four lanes) and USB 3.x standard, but can change the support of DisplayPort standard (four lanes) alone and the simultaneous support of DisplayPort standard (two lanes) and USB 3.x standard.

In block210, the USB controller52determines whether the USB dock20A is the predetermined dock or not. If the USB dock20A is not the predetermined dock, the USE controller52displays an error message and ends processing.

If the USB dock20A is the predetermined dock, the Type-C controller46sets connection of the input and output of the first multiplexer56as shown inFIG. 4A, in block212. In other words, the first input terminal group of the first multiplexer56is connected to the second output terminal group, and a third input terminal group of the first multiplexer56is connected to the first output terminal group. Thus, the DisplayPort signals of lane 0 and lane 1 are supplied to two pins TX2+/TX2− and RX2+/RX2− of the receptacle40, and terminals TX+/TX− and RX+/RX− of the USB controller52are connected to two pins TX1+/TX1− and RX1+/RX1− of the receptacle40, respectively. Since the output of the demultiplexer54is not used as explained later, the connection of the input and output of the demultiplexer54does not need to be controlled.

In block214, the CPU42sets connection of the input and output of the multiplexer82by the Type-C controller88in the USB dock20A, as shown inFIG. 4B. In other words, the first input terminal group of the multiplexer82is connected to the first output terminal group, and the second input terminal group of the multiplexer82is connected to the second output terminal group. Thus, the terminals TX+/TX− and RX+/RX− of the USB controller52are connected to the USB 3.x pin group78via the USB 3.x hub84, and the DisplayPort signals of lane 0 and lane 1 are connected to two pins of the DisplayPort pin group80. As a result, the PC10of the embodiment can also be connected to the USB dock20A other than the USB dock20shown inFIG. 2Band capable of simultaneously supporting DisplayPort standard (two lanes) and USB 3.x standard.

The USB dock20A can thus simultaneously support DisplayPort standard (two lanes) and USB 3.x standard. After that, when the operation of the USB device is ended, the USE dock20A can support DisplayPort standard (four lanes) alone.

In block220inFIG. 6, the CPU42determines whether the operation of the USB device connected to the USB 3.x pin group78has been ended or not. When the CPU42detects the end of operation, the CPU42displays on a display (not shown) a message indicating whether the simultaneous support of DisplayPort standard (two lanes) and USB 3.x standard will be changed to the support of DisplayPort standard (four lanes) or not. If the user wishes the change, the user inputs an instruction for change by an input device (not shown). In block221, the CPU42determines whether the user has input the instruction for change or not and, if the user has not, the CPU42ends the operation.

If the user has input the instruction for change, the EC48sets connection of the input and output of the demultiplexer54as shown inFIG. 5A, in block224. In other words, the input terminal group of the demultiplexer54is connected to the first output terminal group. The DisplayPort signals of lane 2 and lane 3 are thereby supplied to two terminals of the second input terminal group of the first multiplexer56, respectively.

In block226, the Type-C controller46sets connection of the input and output of the first multiplexer56as shown inFIG. 5A. In other words, the first input terminal group of the first multiplexer56is connected to the first output terminal group, and the second input terminal group of the first multiplexer56is connected to the second output terminal group. Thus, the DisplayPort signals of lane 0, lane 1, lane 2 and lane 3 are supplied to four pins TX1+/TX1−, RX1+/RX1−, TX2+/TX2− and RX2+/RX2− of the receptacle40, respectively.

In block228, the CPU42sets connection of the input and output of the multiplexer82by the Type-C controller88in the USB dock20A, as shown inFIG. 5B. In other words, the first input terminal group of the multiplexer82is connected to the second output terminal group, and the second input terminal group of the multiplexer82is connected to the third output terminal group. The DisplayPort signals of lane 0, lane 1, lane 2 and lane 3 are thereby connected to four pins of the DisplayPort pin group80, respectively. As a result, the USB dock20A can support DisplayPort standard (four lanes).

After that, the CPU42displays on a display (not shown) a message indicating whether the support of DisplayPort standard (four lanes) will be changed to the simultaneous support of DisplayPort standard (two lanes) and USB 3.x standard or not. If the user wishes the change, the user inputs an instruction for change by an input device (not shown). In block229, the CPU42determines whether the user has input the instruction for change or not and, if the user has not, the CPU42ends the operation.

If the user has input the instruction for change, the processing of block212is performed again.

According to the first embodiment, the USE dock capable of simultaneously supporting DisplayPort standard (four lanes) and USB 3.x standard can be thus implemented. Furthermore, the host capable of using the USB dock can also use the other USB dock, for example, the USB dock capable of simultaneously supporting DisplayPort standard (two lanes) and USB 3.x standard or supporting DisplayPort standard (four lanes).

Next, the second embodiment will be described.

FIG. 7Ashows a PC10A of the second embodiment. Constituent elements of the PC10A are the same as those of the first embodiment, but different with respect to connection of input and output of a demultiplexer54A. According to the first embodiment, as shown inFIG. 2A, the DisplayPort signals of lane 2 and lane 3 output from the GPU50are connected to the input terminal group of the multiplexer54but, according to the second embodiment, as shown inFIG. 7A, two terminals TX+/TX− and RX+/RX− of the USB controller52are connected to the input terminal group of the demultiplexer54A. In other words, the DisplayPort signals of lane 0 and lane 1 output from the GPU50are input to the first input terminal group of the first multiplexer56, and the DisplayPort signals of lane 2 and lane 3 output from the GPU50are input to the second input terminal group of the first multiplexer56. The first output terminal group of the first multiplexer56is connected to two pins TX1+/TX1− and RX1+/RX1− of the receptacle40, and the second output terminal group of the first multiplexer56is connected to two pins TX2+/TX2− and RX2+/RX2− of the receptacle40. The output terminal group of the second multiplexer58is connected to two pins D+/D− and D+/D− of the receptacle40.

FIG. 7Bshows a USB dock20B of the second embodiment. Constituent elements of the USB dock20B are the same as those of the first embodiment, but different with respect to a connection portion of a USB 3.x hub76A. According to the first embodiment, as shown inFIG. 2B, two pins TX1+/TX1− and RX1+/RX1− of the plug70are connected to the input terminal group of the USB 3.x hub76but, according to the second embodiment, as shown inFIG. 7B, two pins D+/D− and D+/D− of the plug70are connected to an input terminal group of the USB 3.x hub76A. In other words, four pins TX1+/TX1−, RX1+/RX1−, TX2+/TX2−, and RX2+/RX2− of the plug70are connected to the DisplayPort pin group80four lanes, and two pins D+/D− and D+/D− of the plug70are connected to the two pins of the USB 3.x pin group78via the USB 3.x hub76A.

FIG. 8is a flowchart showing operations of the PC10A shown inFIG. 7A. Blocks of performing the same operations as those inFIG. 3are denoted by the same block numbers. If the PC10A detects connection of the dock, the Type-C controller46inquires the ID from the Type-C controller72of the USB dock20B via pins CC1 and CC2 in block102. The Type-C controller46determines whether the predetermined ID has been received or not, in block104. If the connected dock is other than the dock shown inFIG. 7B, the determination result in block104is NO since the predetermined ID is not sent from the dock, and the third dock processing which will be explained later will be performed in block240. If the connected dock is the dock of the type shown inFIG. 7B, the determination result in block104is YES since the predetermined ID is sent from the dock, and operations following block120are performed.

If the Type-C controller46receives the predetermined ID, the EC48changes connection of the input and output of the demultiplexer54A, in block120. In other words, the input terminal group of the demultiplexer54A is connected to the second output terminal group. For this reason, two terminals TX+/TX− and RX+/RX− of the USB controller52are connected to the first input terminal group of the second multiplexer58.

In block122, the Type-C controller46changes connection of the input and output of the first multiplexer56. In other words, the first input terminal group of the first multiplexer56is connected to the first output terminal group, and the second input terminal group of the first multiplexer56is connected to the second output terminal group. For this reason, the DisplayPort signals of lane 0, lane 1, lane 3 and lane 4 are connected to four pins TX1+/TX1−, RX1+/RX1−, TX2+/TX2− and RX2+/RX2− of the receptacle40, respectively.

In block124, the EC48sets connection of the input and output of the second multiplexer58. In other words, the first input terminal group of the second multiplexer58is connected to the output terminal group. For this reason, two terminals TX+/TX− and RX+/RX− of the USB controller52are connected to two pins D+/D− and D+/D− of the receptacle40, respectively.

As a result, the DisplayPort signals of lane 0, lane 1, lane 2 and lane 3 are supplied to four pins of the DisplayPort pin group80, two terminals TX+/TX− and RX+/RX− of the USB controller52are connected to two pins of the USB 3.x pin group78. The USB dock capable of simultaneously supporting DisplayPort standard (four lanes) and USB 3.x standard can be implemented.

Next, it will be described that the PC10A (host) shown inFIG. 7Acan also operate with a USB dock other than the USB dock20B shown inFIG. 7B.FIG. 9A,FIG. 9B,FIG. 10A, andFIG. 10Bshow an example of a system configuration in a case where a USB dock20C other than the USB dock20B shown inFIG. 7Bis connected to the PC10A shown inFIG. 7A. The USB dock20C is a dock which cannot simultaneously support DisplayPort standard (four lanes) and USB 3.x standard, but can change the support of DisplayPort standard (four lanes) alone and the simultaneous support of DisplayPort standard (two lanes) and USB 3.x standard, similarly to the USB dock20B shown inFIG. 4BandFIG. 5B.FIG. 9AandFIG. 9Bshow an example of simultaneously supporting DisplayPort standard (two lanes) and USB 3.x standard, andFIG. 10AandFIG. 10Bshow supporting DisplayPort standard (four lanes) alone.

A hardware configuration of the PC10A shown inFIG. 9AandFIG. 10Ais the same as that of the PC10A shown inFIG. 7A, but different with respect to connection of the input and output of the demultiplexer54A and multiplexers56and58. The USB dock20C shown inFIG. 9BandFIG. 10Bincludes the DisplayPort pin group80of four lanes and the USB 3.x pin group78, similarly to the USB dock20B shown inFIG. 7B, and further includes the Type-C controller88, multiplexer82, billboard device86and USB 3.x hub84.

The billboard device86is connected to the USB 3.x hub84. The billboard device86sends information for identifying the device to the host when the billboard device86receives the inquiry of the type of the device from the host via the pin D+/D−. A billboard device is unnecessary in the USB dock20B shown inFIG. 7Bsince the ID memory74is provided in the Type-C controller72, but the USB dock20C shown inFIG. 9BandFIG. 10Bincludes the billboard device84since an ID memory74is not provided in the USB dock20C.

Four pins TX1+/TX1−, RX1+/RX1−, TX2+/TX2− and RX2+/RX2− of the plug70are connected to the first input terminal group (two terminals) and the second input terminal group (two terminals) of the multiplexer82. In the multiplexer82, two input terminal groups are selectively connected to three output terminal groups. The third output terminal group (two terminals) of the multiplexer82is connected to each of two input terminals of the USB 3.x hub84. The first output terminal group (two terminals) and the second output terminal group (two terminals) of the multiplexer82are connected to four pins of the DisplayPort pin group80of four lanes, respectively.

The system operation shown inFIG. 9A,FIG. 9B,FIG. 10A, andFIG. 10Bwill be described with reference toFIG. 11. An example of changing operation to simultaneously support DisplayPort standard (two lanes) and USB 3.x standard and then support DisplayPort standard (four lanes) alone will be explained, but the operation may be changed to support DisplayPort standard (four lanes) alone and then simultaneously support DisplayPort standard (two lanes) and USB 3.x standard.

FIG. 11is a flowchart of the third dock processing240shown inFIG. 8.

In block242, the EC48changes connection of the input and output of the second multiplexer58as shown inFIG. 9A. In other words, the second input terminal group of the second multiplexer58is connected to the output terminal group. For this reason, the D+/D− terminal of the USB controller52is commonly connected to two pins D+/D− and D+/D− of the receptacle40.

In block244, the Type-C controller46inquires of the Type-C controller88of the USB dock20C via the pins CC1 and CC2 whether the USB dock20C is the predetermined dock or not. The Type-C controller88stores information indicating the type of the dock. The predetermined dock indicates the dock shown inFIG. 9BandFIG. 10B, which cannot simultaneously support DisplayPort standard (four lanes) and USB 3.x standard, but can change the support of DisplayPort standard (four lanes) alone and the simultaneous support of DisplayPort standard (two lanes) and USB 3.x standard.

In block250, the USB controller52determines whether the USB dock20C is the predetermined dock or not as shown inFIG. 9BandFIG. 10B. If the USB dock20C is not the predetermined dock, the USB controller52displays an error message and ends processing.

If the USB dock20C is the predetermined dock, the EC48sets connection of the input and output of the demultiplexer54A as shown inFIG. 9A. In other words, the input terminal group of the demultiplexer54A is connected to the first output terminal group. As a result, two terminals TX+/TX− and RX+/RX− of the USB controller52are connected to the third input terminal group of the first multiplexer56.

In block254, the Type-C controller46sets connection of the input and output of the first multiplexer56as shown inFIG. 9A. In other words, the first input terminal group of the first multiplexer56is connected to the first output terminal group, and the third input terminal group of the first multiplexer56is connected to the second output terminal group. Thus, the DisplayPort signals of lane 0 and lane 1 are supplied to two pins TX1+/TX1− and RX1+/RX1− of the receptacle40, and terminals TX+/TX− and RX+/RX− of the USB controller52are connected to two pins TX2+/TX2− and RX2+/RX2− of the receptacle40, respectively.

In block256, the EC48sets connection of the input and output of the second multiplexer58as shown inFIG. 9A. In other words, the second input terminal group of the second multiplexer58is connected to the output terminal group. As a result, the D+/D− terminal of the USB controller52is commonly connected to two pins D+/D− and D+/D− of the receptacle40.

In block258, the CPU42sets connection of the input and output of the multiplexer82by the Type-C controller88in the USB dock20C, as shown inFIG. 9B. In other words, the first input terminal group of the multiplexer82is connected to the first output terminal group, and a second input terminal group of the multiplexer82is connected to the third output terminal group. Thus, the DisplayPort signals of lane 0 and lane 1 are connected to several parts of the DisplayPort pin group80, and terminals TX+/TX− and RX+/RX− of the USB controller52are connected to the USB 3.x pin group78via the USB 3.x hub84. As a result, the PC10A of the second embodiment can also be connected to the USB dock20C capable of simultaneously supporting DisplayPort standard (two lanes) and USB 3.x standard other than the USB dock20B shown inFIG. 7B.

The USB dock20C can thus simultaneously support DisplayPort standard (two lanes) and USB 3.x standard. After that, when the operation of the USB device is ended, the USB dock20C can support DisplayPort standard (four lanes) alone.

In block260inFIG. 11, the CPU42determines whether the operation of the USB device connected to the USB 3.x pin group78has been ended or not. When the CPU42detects the end of operation, the CPU42displays on a display (not shown) a message indicating whether the simultaneous support of DisplayPort standard (two lanes) and USB 3.x standard will be changed to the support of DisplayPort standard (four lanes) or not. If the user wishes the change, the user inputs an instruction for change by an input device (not shown). In block261, the CPU42determines whether the user has input the instruction for change or not and, if the user has not, the CPU42ends the operation.

If the user has input the instruction for change, the EC48changes connection of the input and output of the first demultiplexer56as shown inFIG. 10A, in block262. In other words, the first input terminal group of the first multiplexer56is connected to the first output terminal group, and a second input terminal group of the first multiplexer56is connected to the second output terminal group. Thus, the DisplayPort signals of lane 0, lane 1, lane 2 and lane 3 are supplied to four pins TX1+/TX1−, RX1+/RX1−, TX2+/TX2− and RX2+/RX2− of the receptacle40, respectively.

In block264, the CPU42sets connection of the input and output of the multiplexer82by the Type-C controller88in the USB dock20C, as shown inFIG. 10B. In other words, the first input terminal group of the multiplexer82is connected to the first output terminal group, and the second input terminal group of the multiplexer82is connected to the second output terminal group. The DisplayPort signals of lane 0, lane 1, lane 2 and lane 3 are thereby connected to four pins of the DisplayPort pin group80, respectively. As a result, the USB dock20C can support DisplayPort standard (four lanes).

After that, the CPU42displays on a display (not shown) a message indicating whether the support of DisplayPort standard (four lanes) will be changed to the simultaneous support of DisplayPort standard (two lanes) and USB 3.x standard or not. If the user wishes the change, the user inputs an instruction for change by an input device (not shown). In block265, the CPU42determines whether the user has input the instruction for change or not and, if the user has not, the CPU42ends the operation.

If the user has input the instruction for change, the processing of block252is performed again.

According to the second embodiment, the USB dock capable of simultaneously supporting DisplayPort standard (four lanes) and USB 3.x standard can be thus implemented. Furthermore, the host capable of using the USB dock can also use the other USB dock, for example, the USB dock capable of simultaneously supporting DisplayPort standard (two lanes) and USB 3.x standard or supporting DisplayPort standard (four lanes).

In the above explanations, for example, the DisplayPort signals (lane 0 and lane 1) of two lower lanes are always assigned to several pins of USB 3.x data bus pins of the USB Type-C connector, and any of the DisplayPort signals (lane 2 and lane 3) of two upper lanes and the USB signals are assigned to any of the remaining USB 3.x data bus pins of the USB Type-C connector and the USB 2.0 data bus pins. However, any of the DisplayPort signals (lane 0 and lane 1) of two lower lanes, the DisplayPort signals (lane 2 and lane 3) of two upper lanes and the USB signals may be assigned to any of the USB 3.x data bus pins of the USB Type-C connector and the USB 2.0 data bus pins.

Furthermore, each of the multiplexer and the demultiplexer changes the connections of two signals together in the above explanations, but may change the connection of each of the signals. In this case, any of the DisplayPort signals of four lanes and two USB 3.x signals may be assigned to any of the USB 2.0 data bus pins D+/D− and D+/D− and the USB 3.x data bus pins TX1+/TX1−, TX2+/TX2−, RX1+/RX1− and RX2+/RX2− of the USB Type-C connector.