Integrated circuit device with stacked dies having mirrored circuitry

An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. The third and fourth IC dies are also coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other.

TECHNICAL FIELD

Embodiments of the present invention generally relate to integrated circuit devices, and more particularly, to an integrated circuit devices having stacked integrated circuit dies with mirrored circuitry and methods for fabricating the same.

BACKGROUND

Electronic devices often employ electronic components which leverage chip package assemblies for increased functionality and higher component density. Conventional chip packaging schemes often utilize a package substrate, often in conjunction with a through-silicon-via (TSV) interposer, to enable a plurality of integrated circuit (IC) dies to be mounted to a single package substrate. The IC dies may include memory, logic or other IC devices. These electronic devices containing one or more chip packages are frequently utilized in advanced electronic computing systems, such as found in telecomm and datacomm equipment, data centers and automotive electronics, among others.

In many chip package assemblies, the IC dies are stacked to provide increased memory or processing capabilities within a single chip package assembly. Although stacking IC dies is desirable for the increased memory or processing capabilities, stacking IC dies during the manufacture of stacked integrated circuit devices presents additional fabrication complexity, challenges and consequently cost.

Therefore, a need exists for an integrated circuit device that is more cost effective to manufacture as compared to conventions techniques.

SUMMARY

An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. The third and fourth IC dies are also coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other.

In another example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. An active side of the third die body is coupled to a substrate side of the second IC die. An active side of the fourth die body is coupled to a substrate side of the third IC die.

In yet another example, a method for fabricating an integrated circuit device is provided. The method includes mounting an active side of a first integrated circuit (IC) die to an active side of a second IC die, the first and second IC dies having an arrangement of integrated circuitry that are mirror images; and mounting a third IC die to a substrate side of the second IC die.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments.

DETAILED DESCRIPTION

An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing. The use of IC dies having circuitry formed in mirror images allow for a single mask set to be developed and qualified, while a mirror image of that mask set be utilized to produce a second IC die without the extra cost and time needed to developing a different second mask set for the second IC die. Furthermore, the pair of mirrored, stacked integrated circuit dies allows fabrication of a die stack of four of more IC dies to be produced with a reduced number of carrier attach and detach operations during device fabrication. Thus, the cost and time needed for fabrication of the integrated circuit device is further reduced. Accordingly, robust integrated circuit devices are realized that have significant cost and time to production advantages over conventional design and fabrication techniques.

Turning now toFIG. 1, a schematic top view of two integrated circuit (IC) dies102,104are illustrated prior to stacking one on top of the other while fabricating an integrated circuit (IC) device. The IC dies102,104utilized in the IC device may be configured as, but are not limited to, programmable logic devices, such as field programmable gate arrays (FPGA), application-specific integrated circuit (ASIC), memory devices, such as high band-width memory (HBM), optical devices, processors or other IC memory or logic structures. One or more of the IC dies102,104may optionally include optical devices such as photo-detectors, lasers, optical sources, and the like.

The first IC die102has a die body116containing functional and other circuitry112. The circuitry112is schematically represented by an “F” shown in phantom inFIG. 1. The circuitry112terminates on an active side106of the die body116at a plurality of contact pads110. Although only 6 contact pads110are shown inFIG. 1for simplicity, in excess of 400 contact pads110may be exposed on the active side106of the die body116.

Similarly, the second IC die104has a die body118containing functional and other circuitry114. The circuitry114is schematically represented by an “” shown in phantom inFIG. 1. The circuitry114terminates on an active side108of the die body118at a plurality of contact pads110. Although only 6 contact pads110are shown inFIG. 1for simplicity, in excess of 400 contact pads110may be exposed on the active side108of the die body118.

The circuitry112of the first IC die102has a first arrangement that is the mirror image of a second arrangement of the circuitry114of the second IC die104. For example, the contact pads110of the first IC die102are arranged in locations that are a mirror image of the locations of the contact pads110of the second IC die104. The mirrored arrangement of the circuitries112,114of the first and second IC dies102,104are further illustrated in the schematic sectional view of the IC dies102,104ofFIG. 2.

As shown inFIG. 2, the circuitry112of the first IC die102is formed through an active region202and a substrate204comprising the die body116. The active region202is formed on the substrate204and terminates at the active side106of the die body116. A back side206of the substrate204is disposed on a side of the substrate204opposite the active region202and faces away from the active side106.

The active region202includes metal and dielectric layers formed in the front end of the line (FEOL) and back end of the line (BEOL) regions of the die body116. A portion of the circuitry112disposed in the active region202has an arrangement of circuit elements220,224and routings222. Two circuit elements220,224illustrated inFIG. 2are representative of the many, many circuit elements comprising the function portion of the circuitry112. The circuit elements220,224may include, but are not limited to, any one or more of transistors, diodes, resistors, capacitors, inductors, and memory cells, among others. The circuit elements220,224are interconnect to each other and to the contact pads110disposed on the active side106of the die body116by the routing222. The routing222generally includes conductive lines and vias configured to carrier ground, power or data signals.

A portion of the circuitry112includes through silicon vias (TSVs)210formed through the substrate204. One end of the TSVs210are exposed on the back side206of the die body116, while the other end of the TSVs210are coupled to the circuit elements220,224and the contact pads110by the routing222.

Similarly, the circuitry114of the second IC die104is formed through an active region202and a substrate204comprising the die body118. The active region202is formed on the substrate204and terminates at the active side106of the die body118. A back side208of the substrate204is disposed on a side of the substrate204opposite the active region202and faces away from the active side106.

A portion of the circuitry114disposed in the active region202has an arrangement of circuit elements230,234and routings232. Two circuit elements230,234illustrated inFIG. 2are representative of the many, many circuit elements comprising the function portion of the circuitry114. The circuit elements230,234may include, but are not limited to, any one or more of transistors, diodes, resistors, capacitors, inductors, and memory cells, among others. The circuit elements230,234are interconnect to each other and to the contact pads110disposed on the active side108of the die body118by the routing232. The routing232generally includes conductive lines and via configured to carrier ground, power or data signals.

As discussed above, the circuitry112of the first IC die102has a first arranged that is a mirror image of a second arrangement comprising the circuitry114of the second IC die104. For example, the location of the contact pads110, circuit elements220,224and the routing222of the first IC die102is in the mirror image of the location of the contact pads110, circuit elements230,234and routings232of the second IC die104. Further, the location of the TSVs210within the substrate204of the first IC die102is in the mirror image of the location of the TSVs210within the substrate204of the second IC die104.

Thus, when the first IC die102is flipped such that the active side106of the first IC die102is disposed against the active side108of the second IC die104, the contact pads110of the IC dies102,104are aligned to facilitate mechanical and electrical connections either through solderless hybrid bonding or via solder connections of the contact pads110. Additionally, as the TSVs210are disposed in mirror image locations, the TSVs210exposed on the back sides206,208of the IC dies102,104may also be mated to interconnect the functional circuitries112,114.

The use of IC dies102,104having circuitry112,114formed in mirror images allow for a single mask set to be developed and qualified for the first IC die102without separate time and costs for developing and qualifying a wholly new second mask set for the second IC die104. Particularly, using a mirror image to create a new mask set from the previously designed and qualified mask set ensures that the second IC die104, fabricated using the mirrored mask set, will have the same functionality, performance and reliability as the first IC die102without the significant extra cost and time needed to developing different second mask set for the second IC die104.

FIG. 3is a block diagram of a method300for fabricating an integrated circuit device that includes the IC dies102,104illustrated inFIG. 1, or other similar mirror imaged IC dies. The various stages of fabrication of the integrated circuit device fabricated according to the method300ofFIG. 3are schematically illustrated inFIGS. 4A through 4G.

The method300begins at operation302in which a first IC die102and a second IC die104having mirrored circuitry112,114are flipped so that the active sides106,108face each other, as illustrated inFIG. 4A. At operation304, the IC dies102,104are mounted together such that the contact pads110on the active sides106,108of each die body116,118are electrically connected, as shown inFIG. 4B. The IC dies102,104may be mounted together utilizing solder connections, such as microbumps, with hybrid connections, or by other suitable technique, to form a full body, active on active (AoA) IC die stack402that include an active on active (AoA) interface410defined between mating active sides106,108of the IC dies102,104. In the embodiment depicted inFIG. 4B, the AoA interface410utilizes a hybrid connecter412comprised of metal circuit connection material disposed in a dielectric sheet to couple the contact pads110of the IC dies102,104shown inFIG. 4B.

At operation306, the second IC die104is thinned, as illustrated inFIG. 4C. For example, a portion of the back side208of the second IC die104is removed as shown such that the back side208has a new thinned surface406, resulting in a reduced thickness of the die body118. The die body118may be thinned by grinding, etching, chemical mechanical planarization or other suitable technique. In one example, the die body118is thinned by grinding the back side208to yield a thickness defined between the thinned surface406and the active side108of, but not limited to, about 50 μm to about 700 μm. As the second IC die104is secured to the first IC die102during thinning, no carriers are needed at operation306, thus saving time and expense. Operation306converts the full body, AoA IC die stack402to a thinned AoA IC die stack404.

At operation308, the thinned AoA IC die stack404is aligned for stacking with a flipped second thinned AoA IC die stack404. As illustrated inFIG. 4D, the second thinned AoA IC die stack404has an orientation that is inverted such that the thinned surface406of one thinned AoA IC die stack404is facing the thinned surface406of the other thinned AoA IC die stack404.

At operation310, the two thinned AoA IC die stacks404are mounted together such that the ends of the TSVs210, shown inFIG. 2exposed on the thinned side406(formerly the back side208prior to thinning), are electrically connected, as shown inFIG. 4E, enabling the circuitries of the die stacks404to communicate. The facing IC dies104,104of the thinned AoA IC die stacks404may be mounted together utilizing solder connections, such as microbumps, with hybrid connections, or by other suitable technique, to form a full double, AoA IC die stack408. In the embodiment depicted inFIG. 4E, hybrid connecter412, such as described above comprised of metal circuit connection material disposed in a dielectric sheet, is utilized to couple the exposed TSVs210of the adjacent IC dies104,104.

At operation312, the full double, AoA IC die stack408is thinned to form a thinned double AoA IC die stack440, as illustrated inFIG. 4F. For example, a portion of the back side206of at least one of the first IC die102is removed such that the back side206has a new thinned surface414, resulting in a reduced thickness of the die body116. The die body116may be thinned as described above, and in one example, is thinned by grinding. Although the top die102of the thinned double AoA IC die stack440is shown as thinned inFIG. 4F, the bottom die102of the thinned double AoA IC die stack440may alternatively or additionally be thinned using techniques as described above. As the full double, AoA IC die stack408provides a secure anchor for the first IC die102during thinning, no carriers are needed at operation312, thus saving time and expense during fabrication of the thinned double AoA IC die stack440.

At operation314, the thinned double AoA IC die stack440is utilized to form a chip package assembly430. The chip package assembly430includes a package substrate432and may optionally include one or more additional IC dies434. Circuitry of the thinned double AoA IC die stack440is mechanically and electrically connected to the package substrate432via solder connections436or other suitable packaging connection. The optional additional IC die434is also mechanically and electrically connected to the package substrate432via solder connections436or other suitable packaging connection. The solder connections436enable the IC die434and the thinned double AoA IC die stack440to communicate with each other and with contact pads426exposed on the opposite side of the package substrate432through routings428formed in and/or on the package substrate432. Although one additional IC die434is shown inFIG. 4G, one or more additional IC dies may be stacked on and/or next to the IC die434. The IC die434utilized in the chip package assembly430may be configured as, but are not limited to, programmable logic devices, such as field programmable gate arrays (FPGA), application-specific integrated circuit (ASIC), memory devices, such as high band-width memory (HBM), optical devices, optical devices such as photo-detectors, lasers, optical sources, and processors or other IC memory or logic structures. In the example depictedFIG. 4G, the IC die434is configured as a logic die, while the thinned double AoA IC die stack440is configured as a memory stack, such that the chip package assembly430functions as a high band-width memory (HBM) device. The IC die434may also be configured identical to one of the IC dies102,104described above.

FIG. 5is a block diagram of another method500for fabricating an integrated circuit device that includes the IC dies102,104illustrated inFIG. 1, among others. The various stages of fabrication of the integrated circuit device fabricated according to the method500ofFIG. 5are schematically illustrated inFIGS. 6A-6H.

The method500begins at operation502in which a third IC die660is secured to a carrier602, as shown inFIG. 6A. The third IC die660is named as such to maintain the prior convention of the first and second IC dies102,104with mirrored circuitry, which will be introduced later in the method500. The third IC die660generally includes a die body having an active region202disposed on a substrate204. The third IC die660may be configured as any of the IC dies102,104,434described above, or as otherwise desired. The die body includes an active side662and a back side664. The active side662of the third IC die660is releasably coupled to the carrier602by a chip attached film or other releasable adhesive.

At operation504, the third IC die660is thinned, as illustrated inFIG. 6B. For example, a portion of the back side664of the third IC die660is removed as shown such that the back side664has a new thinned surface606, resulting in a reduced thickness of the die body. The die body of the third IC die660may be thinned using any of the techniques discussed above, or other suitable technique.

At operation506, the third IC die660is mounted to a second IC die104, as shown inFIG. 6C. The IC dies660,104may be mounted together utilizing solder connections, such as microbumps, with hybrid connections, or by other suitable technique. In the example depicted inFIG. 6C, the thinned surface606of the third IC die660is mounted to the active side108of the second IC die104to form an active to back die stack610, as later shown inFIG. 6D. At operation508, the carrier602is removed from the active to back die stack610, also as shown inFIG. 6D.

At operation510, a thinned AoA IC die stack404is aligned for stacking with the active to back die stack610, as illustrated inFIG. 6E. The thinned AoA IC die stack404may be fabricated as described above, or via another suitable technique. As illustrated inFIG. 6E, the thinned AoA IC die stack404has an orientation that is inverted such that the thinned surface406of the thinned AoA IC die stack404is facing the active side662of the third IC die660of the active to back die stack610.

At operation512, the thinned AoA IC die stack404secured to the active to back die stack610, as illustrated inFIG. 6F, to form an active to back, AoA IC die stack612that includes an active on active (AoA) interface410defined between mating active sides106,108of the IC dies102,104.

At operation514, one of the IC dies102,104defining the distal ends of the active to back, AoA IC die stack612is thinned, as illustrated inFIG. 6G, to form a thinned, active to back, AoA IC die stack640. For example, a portion of the back side206of the first IC die102is removed as shown such that the back side206has a new thinned surface414, resulting in a reduced thickness of the die body116. The die body116may be thinned as described above, or by another suitable technique. As the first IC die102is secured to the active to back, AoA IC die stack612during thinning, no carriers are needed at operation514, thus saving time and expense. The second IC die may also or alternatively be thinned. Operation516converts the active to back, AoA IC die stack612to the thinned, active to back, AoA IC die stack640.

At operation516, the thinned, active to back, AoA IC die stack640is utilized to form a chip package assembly630, shown inFIG. 6H. The chip package assembly630includes a package substrate632and may optionally include one or more additional IC dies634. Circuitry of the thinned, active to back, AoA IC die stack640is mechanically and electrically connected to the package substrate632via solder connections636or other suitable packaging connection. The optional additional IC die634is also mechanically and electrically connected to the package substrate632via solder connections636or other suitable packaging connection. The solder connections636enable the IC die634and the thinned, active to back, AoA IC die stack640to communicate with each other and with contact pads626exposed on the opposite side of the package substrate632through routings628formed in and/or on the package substrate632. Although one additional IC die634is shown inFIG. 6H, one or more additional IC dies may be stacked on and/or next to the IC die634. The IC die634utilized in the chip package assembly630may be configured as described above with reference to the IC die434. In the example depictedFIG. 6H, the IC die634is configured as a logic die, while the thinned, active to back, AoA IC die stack640is configured as a memory stack, such that the chip package assembly630functions as a high band-width memory (HBM) device.

FIGS. 7-9are schematic side views of various alternative examples of integrated circuit devices that include the IC dies102,104ofFIG. 1, among others. Referring first to an integrated circuit device700illustrated inFIG. 7, the integrated circuit device700includes a thinned double AoA IC die stack440and at least one additional, or third, IC die702. The third IC die702may be configured identical to the IC die434described above. The third IC die702includes a die body having an active region202disposed on a substrate204. An active side704of the third IC die702is electrically and mechanically coupled to the thinned surface414of the first IC102disposed at the distal end of the thinned double AoA IC die stack440. The third IC die702may be mounted to the thinned double AoA IC die stack440by solder, hybrid or other suitable connections. One or both of the substrate204of the third IC die702and/or the substrate204of the first IC102disposed at the opposite end of the thinned double AoA IC die stack440may be thinned as illustrated by the phantom lines706. The integrated circuit device700may be utilized in a chip package assembly, such as for example, the chip package assembly430illustrated inFIG. 4G, with the integrated circuit device700taking the place of thinned double AoA IC die stack440.

FIG. 8is another schematic side view of an integrated circuit device800. The integrated circuit device800includes a thinned double AoA IC die stack440and at least two additional IC dies. In the example depicted inFIG. 8, a thinned AoA IC die stack404containing IC dies102,104is shown coupled to thinned double AoA IC die stack440. The stacks404,440may be configured described above, except in that the first IC die102is thinned rather than the second IC die104in the example ofFIG. 8. A thinned surface406of the thinned AoA IC die stack404is electrically and mechanically coupled to a thinned surface414of the first IC102disposed at the distal end of the thinned double AoA IC die stack440. The thinned surface406may be mounted to the thinned surface414by solder, hybrid or other suitable connections. One or both of the substrates204exposed at the distal ends of the integrated circuit device800may be thinned as illustrated by the phantom lines808. The integrated circuit device800may be utilized in a chip package assembly, such as for example, the chip package assembly430illustrated inFIG. 4G, with the integrated circuit device800taking the place of thinned double AoA IC die stack440.

FIG. 9is another schematic side view of an integrated circuit device900. The integrated circuit device900includes two thinned AoA IC die stacks404sandwiching at an additional IC die802. Although only one additional IC die802is shown between the thinned AoA IC die stacks404, more than one additional IC die802may be utilized. The IC die802may be configured identical to the IC die434described above.

In the example depicted inFIG. 9, a thinned surface406of one of the thinned AoA IC die stack404is shown coupled an active side804of the IC die802, while a thinned surface406of the other thinned AoA IC die stack404is shown coupled a back side806of the IC die802. The integrated circuit device900may be utilized in a chip package assembly, such as for example, the chip package assembly430illustrated inFIG. 4G, with the integrated circuit device900taking the place of thinned double AoA IC die stack440. Although all the IC dies of the integrated circuit device900are shown in a thinned configuration, one or more of the IC dies of the integrated circuit device900may have a full body.

Thus, integrated circuit devices and techniques for manufacturing the same have been described above that leverage two or more pairs of stacked integrated circuit dies that include circuitry arranged in mirror images to reduce the complexity of manufacturing. The mirror image IC dies allow for a single mask set to be developed and qualified for one die, while the second mask set is made in the mirrored image without the send for separate design and qualification, thus providing a significant savings in development time and cost. Furthermore, the pair of mirrored, stacked integrated circuit dies allows fabrication of a die stack of four of more IC dies to be produced with a reduced number of carriers needed during fabrication. Thus, the cost and time needed to fabrication the integrated circuit device is further reduced. Accordingly, robust integrated circuit devices are realized that have significant cost and time to production advantages over conventional fabrication techniques.

It is noted that the use of mirror dies coupled across their active sides beneficially allows the advantages described above to be realized even if utilized in a IC die stack having only two mirrored IC dies, or even more than four mirrored IC dies.

Furthermore, the fabrication sequence described above that enables the elimination of one or more carrier attach and detach operations may also be used to advantage without the use of IC dies having functional circuitry arranged in mirror images.