Power devices and methods for manufacturing the same

Power devices in which a low on-resistance can be obtained while maintaining a high breakdown voltage and a method for manufacturing the power devices are described. The power device includes a semiconductor substrate having a first conductivity type, a burying layer having a high concentration of a second conductivity type arranged deep in the semiconductor substrate, a well having a low concentration of a second conductivity type formed on the burying layer of the semiconductor substrate, a body region having a first conductivity type formed in a predetermined portion in the well having a low concentration of a second conductivity type, first and second channel stop regions having a low concentration of a second conductivity type, the first and second channel stop regions are formed in a predetermined portion of the body region and on both edges of the body region having a first conductivity type, a gate electrode including a gate insulating layer, formed on a space between the first and second channel stop regions, source and drain regions having a high concentration of a second conductivity type formed in the first and second channel stop regions on both sides of the gate electrode, and a body contact region formed in the source region. Only the body region having a first conductivity type exists between the first and second channel stop regions, and a channel is formed between the first and second channel stop regions.

REFERENCE TO RELATED APPLICATIONS

This application claims priority of Korean Patent Application No. 2002-55965, the entire disclosure of which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to power devices and methods for manufacturing such power devices. More particularly, the invention relates to power devices in which a low on-resistance can be obtained while maintaining a high breakdown voltage, as well as methods for manufacturing such power devices.

BACKGROUND OF THE INVENTION

In general, a high-voltage lateral double diffused MOS transistor (LDMOS) is one type of power device that is widely used for control, logic, or power switches. The LDMOS transistor should have a high breakdown voltage that can be sustained even when a high voltage is applied to the LDMOS. The LDMOS transistor should also have a low on-resistance so that a high switching characteristic can be maintained.

FIG. 1is a cross-sectional view illustrating a conventional LDMOS transistor. As shown inFIG. 1, a high-concentration n-type (n+) burying layer12is formed deep in a p-type substrate10, and a low-concentration n-type (n−) epitaxial layer14(or an n−well) having a predetermined thickness is grown on the n+burying layer12. A gate electrode18containing gate insulating layers16aand16bis formed in a predetermined portion on the n−epitaxial layer14. The first gate insulating layer16ahas a thin film and the second gate insulating layer16bhas a thick film. A spacer20is formed by a well-known method on both sidewalls of the gate electrode18.

A p body region24is formed under and to one side of the gate electrode18. An n+source region26and a high concentration p-type (p+) contact region28are formed in the p body region24. In this transistor, the p body region24is formed with a relatively high concentration so that punch-through can be prevented from occurring in the LDMOS transistor.

The transistor illustrated inFIG. 1also contains an n−channel stop region30with a predetermined junction depth under and on one side of the gate electrode18. This transistor also contains an n+drain region32that is formed in the n−channel stop region30. The n−channel stop region30is formed in the LDMOS transistor as a stopper for intercepting the extension of the channel. The n−channel stop region30has a concentration higher than the n−epitaxial layer14, thereby reducing the on-resistance. At the same time, the n−channel stop region30has a relatively low concentration, thereby exhibiting a high breakdown voltage. The transistor illustrated inFIG. 1also contains a gate, a source, and a drain that are connected to the gate electrode18, the source region26and the p+contact region28, and the drain region32, respectively.

The conventional LDMOS transistor illustrated inFIG. 1has a profile in which a body concentration of the channel region C is inclined. Further, the p body region24(where a channel is formed) is formed with a relatively high concentration in consideration of punch-through. Meanwhile, the n−epitaxial layer14is formed with a low concentration in consideration of the breakdown voltage. As a result, the on-resistance of the channel region C cannot be accurately controlled, and since the n−epitaxial layer14has a low concentration, a low on-resistance is not easily obtained.

SUMMARY OF THE INVENTION

In one aspect, the present invention relates to a power device. The power device includes a semiconductor substrate having a first conductivity type, a burying layer having a high concentration of a second conductivity type arranged deep in the semiconductor substrate, a well having a low concentration of a second conductivity type formed on the burying layer of the semiconductor substrate, a body region having a first conductivity type formed in a predetermined portion in the well having a low concentration of a second conductivity type, first and second channel stop regions having a low concentration of a second conductivity type, the first and second channel stop regions are formed in a predetermined portion of the body region and on both edges of the body region having a first conductivity type, a gate electrode including a gate insulating layer, formed on a space between the first and second channel stop regions, source and drain regions having a high concentration of a second conductivity type formed in the first and second channel stop regions on both sides of the gate electrode, and a body contact region formed in the source region. Only the body region having a first conductivity type exists between the first and second channel stop regions, and a channel is formed between the first and second channel stop regions such that a uniform concentration can be obtained in a channel region.

In this aspect of the invention, he first and second channel stop regions can be spaced apart from each other by a channel expected distance, and the first and second channel stop regions can have a concentration higher than that of the well. Also, the first and second channel stop regions can have enough low impurity concentration so that a desired breakdown voltage can be obtained, and the body region can have a first conductivity type with a sufficient high impurity concentration so that punch-through can be prevented. The junction depths of the source and drain regions can be the same as or smaller than those of the first and second channel stop regions. Also, the first conductivity type can be a p-type and the second conductivity type can be an n-type.

In another aspect, the present invention relates to a method for manufacturing a power device according to the following procedure. First, a burying layer having a high concentration of a second conductivity type is formed deep in a semiconductor substrate having a first conductivity type, and a well having a low concentration of a second conductivity type is formed on the burying layer having a high concentration of a second conductivity type of the semiconductor substrate. Next, a body region having a first conductivity type is formed in the well, and first and second channel stop regions having a low concentration of a second conductivity type are formed in the center and on both edges of the body region. After that, a gate electrode is formed on a space between the first and second channel stop regions, and source and drain regions having a high concentration of a second conductivity type are formed in the first and second channel stop regions on both sides of the gate electrode. Subsequently, a body contact region having a first conductivity type is formed in the source region.

In this aspect of the invention, the formation of the body region and the first and second channel stop regions can comprise implanting p-type impurities for a body region into a predetermined portion of the well, implanting n-type impurities for first and second channel stop regions into a predetermined region of the well, and activating the p-type and n-type impurities. The implantation of the p-type impurities for the body region can be performed by implanting boron (B) ions with a concentration of about 1×1013to about 2×1013atoms/cm2. The implantation of the n-type impurities for the first and second channel stop regions can be performed by implanting arsenic (As) ions with a concentration of about 2×1013to about 4×1013atoms/cm2.

FIGS. 1,2A-2D, and3illustrate specific aspects of the invention and are a part of the specification. Together with the following description, the Figures demonstrate and explain the principles of the invention. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. The same reference numerals in different drawings represent the same element, and thus their descriptions will not be repeated.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described more fully hereinafter with reference to the accompanying drawings in which a preferred aspect of the invention is shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Referring toFIG. 2A, an n+burying layer110is formed in a semiconductor substrate100(for example, a p-type silicon substrate) by any well-known method in the art. For example, the n+burying layer110may be formed by an ion implantation process and then an activation (or drive-in) process to force the ions deep in the semiconductor substrate100. Next, n-type impurities are implanted into the semiconductor substrate100above the n+burying layer110to activate the semiconductor substrate100and, therefore, form an n−well120. In one aspect of the invention, an n−epitaxial layer may be grown instead of forming the n−well120by implantation.

After that, a buffer insulating layer130is formed on the resulting structure of the semiconductor substrate100. Then, a photoresist pattern140is formed on the buffer insulating layer130so that a predetermined region of the semiconductor substrate100(i.e., where a p-body region will be formed) is exposed. In this aspect of the invention, the buffer insulating layer130serves to protect the surface of the semiconductor substrate100from the subsequent ion implantation process. Then, p-type impurities150(i.e., boron (B) ions) are implanted into the exposed part of the device where the p body region will be formed. In this case, the boron (B) ions are implanted with a concentration of about 1×1013to about 3×1013atoms/cm2and an energy of about 90 to about 110 KeV.

Next, as shown inFIG. 2B, the photoresist pattern140is removed by any well-known method. Then, another photoresist pattern (not shown) is formed and exposes a region of the device where a channel stop region is expected to be formed. Then, n−type impurities (i.e., arsenic (As) ions) are implanted in the region exposed by the photoresist pattern (i.e., the expected channel stop region). The arsenic (As) ions may be implanted with a concentration of about 2×1013to about 4×1013atoms/cm2and an energy of about 90 to about 110 KeV. After that, the ion-implanted p-type impurities150and the n−type impurities are activated (or driven-in) to form p body region160and channel stop regions170aand170b. In this aspect of the invention, even though the arsenic (As) ions and the boron (B) ions are implanted with about the same energy, the diffusion characteristics of boron (B) ions are better than that of arsenic (As) ions and, therefore, the boron ions diffuse more deeply than the arsenic ions. Thus, the depths of the channel stop regions170aand170bare shorter than the depth of the p body region160.

In this aspect of the invention, the channel stop region of the device includes the first channel stop region170aformed in the p body region160and the second channel stop region170bformed on a lateral side of the p body region160. The first channel stop region170ais a region where a source of a LDMOS transistor will be formed. The second channel stop region170bis a drift region of the LDMOS transistor, and its one side may be invaded into the lateral side of the p body region160. In one aspect of the invention, the impurity concentrations of the first and second channel stop regions170aand170bare higher than that of the n−well120. At the same time, the first and second channel stop regions170aand170bhave impurity concentrations low enough so that a high breakdown voltage can be obtained regardless of an on-resistance.

In one aspect of the invention, before or after forming the p body region160and the first and second channel stop regions170aand170b, a local oxide layer175may be formed by any well-known method in a predetermined portion of the surface of the semiconductor substrate100. The local oxide layer175can serve as a gate insulating layer for the power device and, therefore, is a thick film.

Next, as shown inFIG. 2C, the buffer insulating layer130is removed by any well-known method. Then, a gate insulating layer180is formed on the surface of the semiconductor substrate100by any well-known method. In one aspect of the invention, the buffer insulating layer130is not removed but is formed as the gate insulating layer180. Next, a gate electrode190is formed over part of the first channel stop region170a, part of the p body region160, part of the second channel stop region170b, and the local oxide layer175. In one aspect of the invention, for example, a polysilicon layer may be used as the material for the gate electrode190.

Next, as shown inFIG. 2D, a spacer195is formed by any well-known method on both sidewalls of the gate electrode190. N+impurities are then ion-implanted into the first and second channel stop regions170aand170bon both sides of the gate electrode190to form a source region220aand a drain region220b. In one aspect of the invention, the depths of the source and drain regions220aand220bmay be substantially the same as or smaller than those of the n−channel stop regions170aand170b. After that, p+impurities are implanted into a predetermined portion of the source region220a, thereby forming a body contact region210. In this aspect of the invention, the body contact region210is used to apply an electrical signal to the p body region160.

Next, an interlevel dielectric (ILD) film (not shown) is deposited on a resulting structure of the device. The ILD film is then etched so that the source and drain regions220aand220bare exposed, thereby forming a contact hole. Metallic interconnections230are formed to contact the exposed gate electrode190and the source and drain regions220aand220b. In the present invention, a transistor where the first and second channel stop regions170aand170bate formed and diffused on both sides of the p body region160is referred to as a both sides diffused MOS (BDMOS) transistor.

In the power device of the invention, the entire channel region C is formed in the p body region160. As such, the channel region C has a uniform impurity profile. In other words, as shown inFIG. 3, the channel region of a conventional power device is diffused into the p body region and the n−epitaxial layer. Thus, the conventional power device has an inclined impurity profile. The channel region of a power device according to the invention, however, is formed only in the p body region160and therefore has a uniform profile.

Since the channel region C has a uniform concentration, the length of the channel can be reduced, punch-through can be prevented, and a low on-resistance can be obtained. Further, since the second channel stop region170band the n−well120are separated from the channel, the concentrations of the channel stop regions and the n−well120can be adjusted so that a sufficiently high breakdown voltage can be obtained regardless of an on-resistance. In addition, since the n−channel stop region170bis formed in the vicinity of the surface of the semiconductor substrate100to invade the p body region160, a similar reduced surface field or RESUF (an electric field on the surface of the semiconductor substrate100) can be reduced. Further, since the source and drain regions can be formed by a self-align method, misalignment can be prevented.

As described above, in a power device according to the present invention, the concentration of a channel region of the power device is made uniform such that the length of a channel can be reduced, a uniform breakdown voltage can be maintained, and simultaneously, a low on-resistance can be obtained.

While this invention has been particularly shown and described with reference to a preferred aspect thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and equivalents thereof.