Method of determing a worst case in timing analysis

A method includes identifying a timing path in a transistor level from a graph diagram; calculating a plurality of aging costs associated with the timing path based on a plurality of forms of a DC vector; identifying a first form, associated with a first aging cost of the aging costs, from the forms; and identifying a second form, associated with a second aging cost less than the first aging cost, from the forms.

BACKGROUND

System-on-chip (SoC) technology integrates multiple functional blocks on a single silicon chip. The multiple functional blocks may include digital circuits, analog circuits, mixed-signal circuits or any combination thereof. SoC technology reduces development cycle and manufacture costs and increases product reliability, functionality and performance.

However, an SoC chip is relatively complicated. Such a complicated chip having various types of functional blocks demands a thorough reliability analysis before going through an expensive and time-consuming fabrication process. Semiconductor aging has emerged as a major factor for SoC chip's reliability. Aging induced defects include Hot Carrier Injection (HCI), which relates to the change in electrons/holes' mobility; Electron-Migration (EM), which relates to the gradual displacement of ions in a conductor as a result of current flowing through the conductor; Negative Bias Temperature Instability (NBTI), which relates to a shift of a threshold voltage of a transistor; and Time Dependent Dielectric Breakdown (TDDB), which relates to the damage caused to the gate oxide region of a transistor. In short, HCI, EM, NBTI and TDDB are major mechanisms of device degradation due to aging effects.

Conventionally, design reliability margin is given by the worst-case assumption. That is, the user usage model of a design is assumed to be operated at high voltage and temperature over expected lifetime. As a result, over design issues in early development stage are incurred. Simulation tools such as Simulation Program with Integrated Circuits Emphasis (SPICE) can be used to simulate aging induced defects.

DETAILED DESCRIPTION

FIG. 1is a circuit diagram of a logic circuit10, in accordance with some embodiments. Referring toFIG. 1, the logic circuit10is a graph diagram converted from a netlist in a transistor level. The netlist can be derived from, for example, any suitable storage devices. The logic circuit10operates in a power domain defined by a supply voltage VDD and a reference ground voltage VSS. The logic circuit10receives a DC (direct-current) vector including a combination of voltages A and B at its inputs16and18, and outputs an output signal Z in response to the DC vector at its output19. The number of voltages for a DC vector is not limited to two. The quantity is determined based on a design of a logic circuit. For example, when a logic circuit includes three inputs, the quantity is three. In an embodiment, the logic circuit10includes a CMOS logic circuit.

The logic circuit10includes transistors M1, M2, M3, M4, M5and M6, which in combination define a logic OR gate. However, the logic circuit10is not limited to a logic OR gate. The logic circuit10may include any suitable logic circuits, such as an inverter, a logic AND gate, and a logic XOR gate. Each of the transistors M1, M2and M5includes an n-type transistor, and each of the transistors M3, M4and M6includes a p-type transistor. In an embodiment, each of the transistors M1, M2and M5includes an NMOS transistor, and each of the transistors M3, M4and M6includes a PMOS transistor.

FIG. 2is a circuit diagram of the logic circuit10shown inFIG. 1with a boolean expression, in accordance with some embodiments. Referring toFIG. 2, a boolean expression for each internal nodes12and14of the logic circuit10shown on the graph diagram is determined. In the present disclosure, a term “internal node” can be interpreted as a tap between two electronic components.

In determining the boolean expression, a start point is selected. For example, a gate of the transistor M4is selected as the start point. When the transistor M4is conducted, the gate (the start point) of the transistor M4in voltage level is opposite to the internal node12. Therefore, in response to the voltage A at the gate of the transistor M4, a boolean expression at the internal node12is denoted as A. Similarly, when the transistor M3is conducted, the internal node12in voltage level is opposite to the gate of the transistor M4. Moreover, a voltage level at a drain of the transistor M3would also affect a voltage level at the internal node14. As a result, a boolean expression at the internal node14is denoted as Ā·B. The transistors M5and M6form an inverter. Accordingly, a voltage level at a gate of the transistor M6is opposite to that at its drain. As a result, by function of the inverter, a boolean expression at the output19of the logic circuit10is denoted asĀ·B.

FIG. 3Ais a circuit diagram illustrating a first timing path Pth1of the logic circuit10shown inFIG. 1with a boolean expression, in accordance with some embodiments. When a logic circuit has more than one inputs, a plurality of timing paths exist and each of which will be analyzed one by one. To identify a timing path, a start point and an end point of a flow are required to be determined. Generally, an input and an output of the logic circuit are determined as the start point and the end point, respectively. Moreover, when a flow from a start point receiving a voltage to an end point includes a transistor controlled by another voltage, to determine the boolean expression the transistor is deemed as being conducted.

Referring toFIG. 3A, the gate of the transistor M4, serving as the input16of the logic circuit10receiving the voltage A, is determined as a start point of a flow. A drain of the transistor M5, serving as the output19, which outputs the voltage Z, of the logic circuit10, is determined as an end point of the flow. Since the flow from the gate of the transistor M4receiving the voltage A to the drain of the transistor M5includes the transistor M3controlled by another voltage B, the transistor M3is deemed as being conducted. In response to the conducted state of the transistors M4and M3, the voltage level at the internal node14is logic high. Accordingly, the transistor M5is conducted. As a result, the flow is completed and the first timing path Pth1in the transistor level is identified from the graph diagram.

Moreover, to conduct the transistors M3and M4, the voltages A and B are logic low. Accordingly, the transistors M1and M2are not conducted.

Additionally, when performing a timing analysis, a previous voltage level of a voltage of a combination of a DC vector is involved and is opposite to a current voltage level of the voltage. Also, a current voltage level of a voltage at an output of a logic circuit is opposite to a previous voltage level of the voltage at the output of the logic circuit.

Taking the embodiment ofFIG. 3for instance, to currently conduct the transistor M4, a current voltage level of the voltage A is logic low. Accordingly, a previous voltage level of the voltage A is logic high. Such circumstance means that a voltage level of the voltage A falls. Moreover, in response to the current voltage level of the voltages A and B with logic low, a current voltage level of the voltage Z is logic low. Accordingly, a previous voltage level of the voltage Z is logic high. Such circumstance means that a voltage level of the voltage Z falls. Therefore, the exemplary case illustrated inFIG. 3Ais a case where the voltage A falls and the voltage Z falls, denoted A(F) & Z(F).

FIG. 3Bis a diagram illustrating the first timing path Pth1shown inFIG. 3A, in accordance with some embodiments. Referring toFIG. 3B, the first timing path Pth1is derived from the logic circuit10shown inFIG. 3A. Presenting the first timing path Pth1in a way as shown inFIG. 3Bfacilitates analysis of an aging cost, which will be described in detail below. By using the approach of the present disclosure, a worst case and a best case of forms of a DC vector can be evaluated and identified without performing a circuit simulation via, for example, an HSPICE tool. As a result, computational resource is efficient.

FIG. 4Ais a circuit diagram illustrating a second timing path Pth2of the logic circuit10shown inFIG. 1with a boolean expression, in accordance with some embodiments. Referring toFIG. 4A, a gate of the transistor M3, serving as the input18of the logic circuit10receiving the voltage B, is determined as a start point of a flow. The drain of the transistor M5, serving as the output19, which outputs the voltage Z, of the logic circuit10, is determined as an end point of the flow. To establish the flow, the transistor M3is conducted, resulting in a logic high state at the internal node14. Accordingly, the transistor M5is conducted. As a result, the flow is completed and the second timing path Pth2in the transistor level is identified from the graph diagram.

Moreover, to currently conduct the transistor M3, a current voltage level of the voltage B is logic low. Accordingly, a previous voltage level of the voltage B is logic high. Such circumstance means that a voltage level of the voltage B falls. Moreover, in response to the current voltage level of the voltages A and B with logic low, a current voltage level of the voltage Z is logic low. Accordingly, a previous voltage level of the voltage Z is logic high. Such circumstance means that a voltage level of the voltage Z falls. Therefore, the exemplary case illustrated inFIG. 4Ais a case where the voltage B falls and the voltage Z falls, denoted B(F) & Z(F).

FIG. 4Bis a diagram illustrating the second timing path Pth2shown inFIG. 4A, in accordance with some embodiments. Referring toFIG. 4B, the second timing path Pth2is derived from the logic circuit10shown inFIG. 4A. Presenting the second timing path Pth2in a way as shown inFIG. 4Bfacilitates analysis of an aging cost, as mentioned in the embodiment ofFIG. 3B. By using the approach of the present disclosure, a worst case and a best case of forms of a DC vector can be evaluated without performing a circuit simulation via, for example, an HSPICE tool. As a result, computational resource is efficient.

FIG. 5Ais a circuit diagram illustrating a third timing path Pth3of the logic circuit10shown inFIG. 1with a boolean expression, in accordance with some embodiments. Referring toFIG. 5A, a gate of the transistor M1, serving as the input16of the logic circuit10receiving the voltage A, is determined as a start point of a flow. The drain of the transistor M6, serving as the output19, which outputs the voltage Z, of the logic circuit10, is determined as an end point of the flow. To establish the flow, the transistor M1is conducted, resulting in a logic low state at the internal node14. Accordingly, the transistor M6is conducted. As a result, the flow is completed and the third timing path Pth3in the transistor level is identified from the graph diagram.

Moreover, since the flow starts at the gate of the transistor M1, the boolean expression is denoted asA+B, which equals to the boolean expression Ā·B—.

Additionally, to currently conduct the transistor M1, a current voltage level of the voltage A is logic high. Accordingly, a previous voltage level of the voltage A is logic low. Such circumstance means that a voltage level of the voltage A rises. Moreover, in response to the current voltage level of the voltage A with logic high, a current voltage level of the voltage Z is logic high. Accordingly, a previous voltage level of the voltage Z is logic low. Such circumstance means that a voltage level of the voltage Z rises. Therefore, the exemplary case illustrated inFIG. 5Ais a case where the voltage A rises and the voltage Z rises, denoted A(R) & Z(R).

FIG. 5Bis a diagram illustrating the third timing path Pth3shown inFIG. 5A, in accordance with some embodiments. Referring toFIG. 5B, the third timing path Pth3is derived from the logic circuit10shown inFIG. 5A. Presenting third timing path Pth3in a way as shown inFIG. 5Bfacilitates analysis of an aging cost, as mentioned in the embodiment ofFIG. 3B. By using the approach of the present disclosure, a worst case and a best case of forms of a DC vector can be evaluated and identified without performing a circuit simulation via, for example, an HSPICE tool. As a result, computational resource is efficient.

FIG. 6Ais a circuit diagram illustrating a fourth timing path Pth4of the logic circuit10shown inFIG. 1with a boolean expression, in accordance with some embodiments. Referring toFIG. 6A, a gate of the transistor M2, serving as the input18of the logic circuit10receiving the voltage B, is determined as a start point of a flow. The drain of the transistor M6, serving as the output19, outputting the voltage Z, of the logic circuit10, is determined as an end point of the flow. To establish the flow, the transistor M2is conducted, resulting in a logic low state at the internal node14. Accordingly, the transistor M6is conducted. As a result, the flow is completed and the fourth timing path Pth4in the transistor level is identified from the graph diagram.

Additionally, to currently conduct the transistor M2, a current voltage level of the voltage B is logic high. Accordingly, a previous voltage level of the voltage B is logic low. Such circumstance means that a voltage level of the voltage B rises. Moreover, in response to the current voltage level of the voltage B with logic high, a current voltage level of the voltage Z is logic high. Accordingly, a previous voltage level of the voltage Z is logic low. Such circumstance means that a voltage level of the voltage Z rises. Therefore, the exemplary case illustrated inFIG. 6Ais a case where the voltage B rises and the voltage Z rises, denoted B(R) & Z(R).

FIG. 6Bis a diagram illustrating the fourth timing path Pth4shown inFIG. 6A, in accordance with some embodiments. Referring toFIG. 6B, the fourth timing path Pth4is derived from the logic circuit10shown inFIG. 6A. Presenting fourth timing path Pth4in a way as shown inFIG. 6Bfacilitates analysis of an aging cost, as mentioned in the embodiment ofFIG. 3B. By using the approach of the present disclosure, a worst case and a best case of forms of a DC vector can be evaluated and identified without performing a circuit simulation via, for example, an HSPICE tool. As a result, computational resource is efficient.

To simply the discussion, only the first timing path Pth1is discussed below as shown inFIGS. 7A to 7D. However, analysis to the remaining timing paths Pth2, Pth3and Pth4are the same as that of the first timing path Pth1.

The number of the p-type transistor and the n-type transistor in the first timing path Pth1is separately calculated. In the first timing path Pth1, the number of the p-type transistor is two, the transistors M3and M4. Moreover, the number of the n-type transistor is one, the transistor M5.

Since the logic circuit10has two inputs16and18, a DC vector has four forms, (0,0), (0,1), (1,0) and (1,1), wherein a first value in a bracket represents a voltage level of the voltage A, and a second value in the bracket represents a voltage level of the voltage B. A form of the DC vector determines whether a transistor is stressed or not, which will be described in detail with reference toFIGS. 7A to 7D.

FIG. 7Ais a diagram illustrating an operation of the first timing path Pth1shown inFIG. 6Ain response to a first form (0,0) of a DC vector, in accordance with some embodiments. Referring toFIG. 7A, a value at the internal node12based on the first form (0,0) and the boolean expression Ā is determined as 1. Since the transistor M4is a p-type transistor and since a value at an output of the transistor M4is 1 as determined above, the transistor M4is stressed.

Similarly, a value at the internal node14based on the first form (0,0) and the boolean expression Ā·Bis determined as 1. Since the transistor M3is a p-type transistor and since a value at an output of the transistor M3is 1 as determined above, the transistor M3is stressed.

Also, a value at the output19based on the first form (0,0) and the boolean expressionĀ·Bis determined as 0. Since the transistor M5is an n-type transistor and since a value at an output of the transistor M3is 0 as determined above, the transistor M5is stressed.

As a result, the quantity of the stressed p-type, associated with the first form (0,0), in the first timing path Pth1is two, the transistors M3and M4. The quantity of the stressed n-type, associated with the first form (0,0), in the first timing path Pth1is one, the transistor M5.

FIG. 7Bis a diagram illustrating an operation of the first timing path Pth1shown inFIG. 6Ain response to the second form (0,1) of the DC vector, in accordance with some embodiments. Referring toFIG. 7B, a value at the internal node12based on the second form (0,1) and the boolean expression Ā is determined as 1. Since the transistor M4is a p-type transistor and since a value at an output of the transistor M4is 1 as determined above, the transistor M4is stressed.

Similarly, a value at the internal node14based on the second form (0,1) and the boolean expression Ā·Bis determined as 0. Since the transistor M3is a p-type transistor and since a value at an output of the transistor M3is 0 as determined above, the transistor M3is not stressed.

Since the transistor M3is not stressed, the determination to the transistor M5subsequent to the transistor M3is halted. In this way, computation resource is relatively efficient.

As a result, the quantity of the stressed p-type, associated with the second form (0,1), in the first timing path Pth1is one, the transistor M4. The quantity of the stressed n-type, associated with the second form (0,1), in the first timing path Pth1is zero.

FIG. 7Cis a diagram illustrating an operation of the first timing path Pth1shown inFIG. 6Ain response to the third form (1,0) of the DC vector, in accordance with some embodiments. Referring toFIG. 7C, a value at the internal node12based on the third form (1,0) and the boolean expression Ā is determined as 0. Since the transistor M4is a p-type transistor and since a value at an output of the transistor M4is 0 as determined above, the transistor M4is not stressed.

Since the transistor M4is not stressed, the determination to the transistors M5and M3subsequent to the transistor M4is halted. In this way, computation resource is relatively efficient.

As a result, the quantity of the stressed p-type, associated with the third form (1,0), in the first timing path Pth1is zero. The quantity of the stressed n-type, associated with the third form (1,0), in the first timing path Pth1is zero.

FIG. 7Dis a diagram illustrating an operation of the first timing path Pth1shown inFIG. 6Ain response to the fourth form (1,1) of the DC vector, in accordance with some embodiments. Referring toFIG. 7D, a value at the internal node12based on the fourth form (1,1) and the boolean expression Ā is determined as 0. Since the transistor M4is a p-type transistor and since a value at the output of the transistor M4is 0 as determined above, the transistor M4is not stressed.

Since the transistor M4is not stressed, the determination to the transistors M5and M3subsequent to the transistor M4is halted. In this way, computation resource is relatively efficient.

As a result, the quantity of the stressed p-type, associated with the fourth form (1,1), in the first timing path Pth1is zero. The quantity of the stressed n-type, associated with the fourth form (1,1), in the first timing path Pth1is zero.

After the analysis discussed in the embodiments ofFIGS. 7A to 7Dis completed, a cost function is calculated, thereby identifying which one among the first form (0,0), the second form (0,1), the third form (1,0) and the fourth form (1,1) results in a relatively high level or relatively low level or of an aging effect. When the one results in the most high level of the aging effect, the one is identified as a worst case. When the one results in the most low level of the aging effect, the one is identified a best case.

To calculate the cost function, a first weight value is assigned to a p-type transistor, and a second weight value is assigned to an n-type transistor. Generally, an aging effect caused by a p-type transistor is more serious than that caused by an n-type transistor. As a result, the first weight value is greater than the second weight value. However, the present disclosure is not limited thereto. To facilitate the following discussion, it is assumed that the first weight value is 1, and the second weight value is 0.

The cost function can be expressed in equation (1) as follows.

Where QP represents a quantity of a p-type transistor in a timing path, QN represents a quantity of a n-type transistor in the timing path; QSP represents the quantity of a stressed p-type transistor in the timing path; QSN represents the quantity of a stressed n-type transistor in the timing path; W1represents a first weight value; and W2represents a second weight value. A dominator in equation (1) can also be called a stress limit.

As mentioned above, the quantity of the p-type transistor in the first timing path Pth1is 2; and the quantity of the n-type transistor is the first timing path Pth1is 1. The quantity of the stressed p-type transistor and n-type transistor associated with the first, second, third and fourth forms (0,0), (0,1), (1,0) and (1,1) are discussed in the embodiments ofFIGS. 7A to 7D. As result, the cost can be tabulated as Table 1.

From Table 1, it is realized that the aging cost related to the first from (0,0) is maximum, and the aging costs related to the third and fourth forms (1,0) and (1,1) are minimum. As a result, the first form (0,0) is identified as a worst case in a case A(F)&Z(F), which means that the first form (0,0) would result in the most serious aging effect in a case A(F)&Z(F). The third and fourth forms (1,0) and (1,1) are identified as a best case in a case A(F)&Z(F).

By repeating the approaches as mentioned above, a best case and a worst case for each of the remaining timing paths Pth2, Pth3and Pt4can be identified without performing a circuit simulation via, for example, an HSPICE tool. As a result, computational resource is efficient.

In some existing approaches, it is required to perform a circuit simulation on each of the first, second, third and fourth forms (0,0), (0,1), (1,0) and (1,1) to obtain the associated performances, such as the associated setup times, of the logic circuit10, thereby determining which one is a worst case or which one is a best case in a case A(F)&Z(F). To perform the circuit simulation, a lot of computational resources are required and therefore is not efficient.

FIG. 8is a flow diagram of a method50, in accordance with some embodiments. Referring toFIG. 8, the method50includes operations500,502,504,506,508,510and512.

In operation500, a netlist, in a transistor level, of a logic circuit10is derived. In operation502, the netlist in the transistor level is converted into a graph diagram as shown inFIG. 1. In operation504, a boolean expression is determined for each internal nodes12and14of the logic circuit10shown on the graph diagram. In operation506, a timing path, such as the first timing path Pth1, in the transistor level is identified from the graph diagram. In operation508, a plurality of aging costs, such as 1, 0.48, 0 and 0 associated with the timing path, such as the first timing path Pth1, are derived based on a plurality of forms of a DC vector and the boolean expression. In operation510, a first form such as the first form (0,0), associated with a first aging cost, is identified from the forms. In operation512, a second form, associated with a second aging cost less than the first form, is identified from the forms. By using the method50, the computational resource is efficient

FIG. 9is a flow diagram of a method70, in accordance with some embodiments. Referring toFIG. 9, the method70includes operations72,74,76,77and78. In operation72, different from the method50, a timing path is identified from a logic circuit. In operation74, a boolean expression is determined at each node in the timing path. In operation76, a first value at the internal node is determined based on a first form of a DC vector and the boolean expression. In operation77, a second value at the internal node is determined based on a second form of the DC vector and the boolean expression. In operation78, the quantity of stressed transistor in the timing path is determined separately based on the first value and the second value

FIG. 10Ais a flow diagram of operation78of the method70shown inFIG. 9, in accordance with some embodiments.FIG. 10Bis a flow diagram of operation78of the method70shown inFIG. 9, in accordance with some embodiments. Referring toFIGS. 10A and 10B, operation78includes operations208,210,211,212,214,216,217,218,220,222,224,226,228,229,230,232,234and236.

In operation208, it is determined whether only one type transistor in the timing path. If negative, operation78proceeds to operation217. If affirmative, operation78proceeds to operation210, in which the quantity of a stressed transistor in the timing path is determined based on the first value. In operation211, the quantity of a stressed transistor in the timing path is determined based on the second value. In operation212, it is determined that whether the quantity of the stressed transistor associated with the first value is greater than that associated with the second value. If affirmative, then in operation214it is determined that the first form is the worst case. If not, in operation216it is determined that the second form is the worst case.

In operation217, the quantity each of a stressed p-type and n-type transistor is determined based on the first value. In operation218, the quantity each of a stressed p-type and n-type transistor is determined based on the second value. In operation220, it is determined whether the quantity of the stressed p-type transistor associated with the first value is greater than that of the stressed n-type transistor associated with the first value. If negative, operation78proceeds to operation228. If affirmative, operation78proceeds to operation222, in which it is determined whether the quantity of the stressed p-type transistor associated with the second value is greater than that of the stressed n-type transistor associated with the second value. If negative, operation78proceeds to operation228. If affirmative, operation78proceeds to operation224, in which it is determined whether the quantity of the stressed p-type transistor associated with the first value is greater than that of the stressed p-type transistor associated with the second value. If negative, operation78proceeds to operation224. If affirmative, operation78proceeds to operation226, in which it is determined that the first form is the worst case.

In operation224, a first weight value is assigned to a p-type transistor, and a second weight value is assigned to an n-type transistor. In operation226, a first form value is calculated by summing a multiplication product of the quantity of the stressed p-type transistor associated with the first value and the first weight value and a multiplication product of the quantity of the stressed n-type transistor associated with the first value and the second weight value. In operation228, a second form value is calculated by summing a multiplication product of the quantity of the stressed p-type transistor associated with the second value and the first weight value and a multiplication product of the quantity of the stressed n-type transistor associated with the second value and the second weight value.

In operation230, it is determined whether the first form value is greater than the second form value. If affirmative, operation78proceeds to operation236, in which the first form is determined as the worst case. If negative, operation78proceeds to operation234, in which the second form is determined as the worst case.

FIG. 11is a flow diagram of operations217and218of operation78shown inFIG. 10B, in accordance with some embodiments. Referring toFIG. 11, operations217and218include operations30,32,34and36. In operation30, it is determined whether a transistor whose output is the internal node in the timing path is stressed based on the first value at the internal node. In operation32, the quantity of the stressed p-type and n-type is determined based on the determination associated with the first value. In operation34, it is determined whether a transistor whose output is the internal node in the timing path is stressed based on the second value at the internal node. In operation36, the quantity of the stressed p-type and n-type is determined based on the determination associated with the second value.

FIG. 12is a flow diagram of operations30and34shown inFIG. 11, in accordance with some embodiments. Referring toFIG. 12, operations30and34includes operations300,302,304,306,308,310and312. In operation300, it is determined whether a first transistor in a timing path is a p-type transistor. If negative, operations30and34proceeds to operation310. If affirmative, it is determined whether a voltage level at an output of the first transistor is logic high. If affirmative, then in operation304the first transistor is determined as being stressed. If negative, then in operation306the first transistor306is determined as not stressed. In operation308, the determination to a second transistor subsequent to the first transistor is halted.

In operation310, it is determined whether the voltage level at the output of the first transistor is logic low. If affirmative, then in operation312the first transistor is determined as being stressed. If negative, then operation306is performed.

FIG. 13is a flow diagram of operations32and36shown inFIG. 11, in accordance with some embodiments. Referring toFIG. 13, operations32and36include operations320,322,324and326. In operation320, the quantity of the p-type transistor is determined as being stressed, associated with the first form, is summed. In operation322, the quantity of the n-type transistor is determined as being stressed, associated with the first form, is summed. In operation324, the quantity of the p-type transistor is determined as being stressed, associated with the second form, is summed. In operation326, the quantity of the n-type transistor is determined as being stressed, associated with the second form, is summed.

FIG. 14is a flow diagram of operations400,402,406,408,410,412and414in accordance with some embodiments. Referring toFIG. 14, operations400,402,406,408,410,412and414replace operations229,230,232,234and236shown inFIG. 10B. In operation400, numbers of the p-type transistor and the n-type transistor in the timing path are calculated separately. In operation402, a maximum value (or called stress limit) is calculated by summing a multiplication product of the total number of the p-type transistor and the first weight value and a multiplication product of the total number of the n-type transistor and the second weight value. In operation406, a first ratio of the first form value to the maximum value is calculated. In operation408, a second ratio of the first form value to the maximum value is calculated. In operation410, it is determined whether the first ratio is greater than the second ratio. If affirmative, in operation414the first form is determined as the worst case. If negative, in operation412the second form is determined as the worst case.

Some embodiments have one or a combination of the following features and/or advantages. In some embodiments, a method is provided. The method includes identifying a timing path of a logic circuit; determining a boolean expression at an internal node in the timing path; determining a first value at the internal node based on a first form of a DC vector and the boolean expression; determining a second value at the internal node based on a second form of the DC vector and the boolean expression; and determining the quantity of a stressed transistor in the timing path separately based on the first value and the second value, wherein the quantity of stressed transistor is a factor determining a level of an aging effect.

In some embodiments, a method is provided. The method includes deriving a logic circuit from a netlist; identifying a timing path of a logic circuit; determining a boolean expression at an internal node of the logic circuit; determining a first value at the internal node based on a first form of a DC vector and the boolean expression; determining a second value at the internal node based on a second form of the DC vector and the boolean expression; and determining the quantity of a stressed transistor in the timing path separately based on the first value and the second value, wherein the amount of stressed transistor is a factor determining a level of an aging effect.

In some embodiments, a method is provided. The method includes identifying a timing path in a transistor level from a graph diagram; calculating a plurality of aging costs associated with the timing path based on a plurality of forms of a DC vector; identifying a first form, associated with a first aging cost of the aging costs, from the forms; and identifying a second form, associated with a second aging cost less than the first aging cost, from the forms