SEMICONDUCTOR MEMORY AND FORMING METHOD THEREOF

A method of forming a semiconductor memory includes: providing comprising a storage area and a peripheral area located outside the storage area, wherein the substrate has and a plurality of bit line contact parts and a plurality of capacitor contact parts located in the storage area, and a peripheral gate contact part and a peripheral circuit contact part located in the peripheral area; forming a plurality of bit lines, and simultaneously forming a peripheral gate; forming a bit line isolation layer, and simultaneously forming a peripheral gate isolation layer; forming a first conductive capacitor layer in contact with the capacitor contact part, and simultaneously forming a first peripheral conductive layer in contact with the peripheral circuit contact part; forming a first air gap in the bit line isolation layer, and simultaneously forming a second air gap in the peripheral gate isolation layer.

BACKGROUND

A Dynamic Random-Access Memory (DRAM) is a commonly used semiconductor structure in electronic devices, such as computers, and is composed of a plurality of storage units. Each of the storage units may include a transistor and a capacitor. A gate of the transistor is electrically connected with a word line, a source is electrically connected with a bit line, and a drain is electrically connected with the capacitor. Word line voltage on the word line may control the transistor to be turned on or turned off, to read data information stored in the capacitor through the bit line or write the data information into the capacitor.

SUMMARY

The present disclosure relates to the technical field of semiconductor manufacturing, and in particular relates to a semiconductor memory and a forming method thereof.

According to the first aspect of the present application, the application provides a method of forming a semiconductor memory, which may include the following operations.

A substrate including a storage area and a peripheral area located outside the storage area is provided. The substrate has and a plurality of bit line contact parts and a plurality of capacitor contact parts located in the storage area, and a peripheral gate contact part and a peripheral circuit contact part located in the peripheral area.

A plurality of bit lines, each of which is in contact with a respective one of the bit line contact parts, are formed above the storage area, and simultaneously a peripheral gate in contact with the peripheral gate contact part is formed above the peripheral area.

A bit line isolation layer at least covering the side wall of the bit line is formed, and simultaneously a peripheral gate isolation layer at least covering the side wall of the peripheral gate is formed.

A first conductive capacitor layer in contact with the capacitor contact part is formed above the storage area, and simultaneously a first peripheral conductive layer in contact with the peripheral circuit contact part is formed above the peripheral area. The first conductive capacitor layer is filled in the gap between the adjacent bit lines, and the first peripheral conductive layer covers the side wall of the peripheral gate isolation layer.

A first air gap is formed in the bit line isolation layer, and simultaneously a second air gap is formed in the peripheral gate isolation layer.

According to the second aspect of the present application, the application provides a semiconductor memory, which may include a substrate, a plurality of bit lines, a peripheral gate, a bit line isolation layer, a peripheral gate isolation layer, a first air gap, a second air gap, a first conductive capacitor layer and a first peripheral conductive layer.

The substrate may include a storage area and a peripheral area located outside the storage area. The substrate has a plurality of bit line contact parts and a plurality of capacitor contact parts located in the storage area, and a peripheral gate contact part and a peripheral circuit contact part located in the peripheral area.

The plurality of bit lines are located above the storage area, each of the bit lines is in contact with a respective one of the bit line contact parts.

The peripheral gate is located above the peripheral area and in contact with the peripheral gate contact part.

The bit line isolation layer at least covers the side wall of the bit line.

The peripheral gate isolation layer at least covers the side wall of the peripheral gate.

The first air gap is located in the bit line isolation layer.

The second air gap is located in the peripheral gate isolation layer.

The first conductive capacitor layer is located above the storage area, in contact with the capacitor contact part, and is filled in the gap between the adjacent bit lines.

The first peripheral conductive layer is located above the peripheral area, in contact with the peripheral circuit contact part, and covers the side wall of the peripheral gate isolation layer.

DETAILED DESCRIPTION

The embodiments of a semiconductor memory and a forming method thereof provided by the application are described in detail below in combination with the drawings.

The development of the DRAM pursues high speed, high integration density, low power consumption, etc. With the miniaturization of the structural size of a semiconductor device, especially in the manufacturing process of the DRAM with the key size less than 20 nm, there are higher requirements for the material, the morphology, the size, the electrical performance and the like of the bit line, such as wider bandwidth, to ensure good insulation performance and lower dielectric constant so as to ensure small parasitic capacitance and small coupling effect. Based on the above purpose, a variety of low dielectric constant materials are widely used in semiconductor manufacturing. In order to form a bit line with better performance, the bit line of a storage area and a peripheral structure device of a peripheral area are manufactured separately. The peripheral structure may include a peripheral gate, a peripheral circuit, etc. The separate manufacturing steps are quite cumbersome, the manufacturing cost is relatively high, and the performance of the bit line and a logic gate device after being manufactured needs to be improved.

Various embodiments of the present disclosure can address how to simplify the manufacturing steps of a semiconductor memory so as to reduce the manufacturing cost of the semiconductor memory and improve the performance of the semiconductor memory.

The embodiment provides a method of forming a semiconductor memory.FIG. 1is a flowchart of a method of forming a semiconductor memory in an embodiment of the application.FIG. 2AtoFIG. 2Lare schematic cross-sectional views of a storage area in a process of forming a semiconductor memory in an embodiment of the application.FIG. 3AtoFIG. 3Iare schematic cross-sectional views of a peripheral area in a process of forming a semiconductor memory in an embodiment of the application. As shown inFIG. 1,FIG. 2AtoFIG. 2LandFIG. 3AtoFIG. 3I, a method of forming a semiconductor memory provided in the embodiment may include the follows.

At S11, a substrate is provided. The substrate may include a storage area21and a peripheral area41located outside the storage area21. The substrate has a plurality of bit line contact parts212and a plurality of capacitor contact parts213located in the storage area21, and a peripheral gate contact part413and a peripheral circuit contact part414located in the peripheral area41, as shown inFIG. 2AandFIG. 3A.

Specifically, the substrate may be, but is not limited to, a silicon substrate. The substrate may include the storage area21and the peripheral area41located outside the storage area. The peripheral area41may be only located on one side of the storage area21or distributed around the storage area21. The storage area21is configured to store data information, and the peripheral area41may include a Complementary Metal Oxide Semiconductor (CMOS) circuit and other structures for transmitting a control signal to the storage area21. The storage area21in the substrate may include the plurality of bit line contact parts212and the plurality of capacitor contact parts213. The bit line contact parts212and the capacitor contact parts213are alternately arranged in the substrate. The bit line contact part212is configured to be electrically connected with the subsequently formed bit line, and the capacitor contact part213is configured to be electrically connected with a subsequently formed capacitor contact structure. The peripheral area41in the substrate may include the peripheral gate contact part413and the peripheral circuit contact part414. The peripheral gate contact part413is configured to be electrically connected with the subsequently formed peripheral gate, and the peripheral circuit contact part414is configured to be electrically connected with the subsequently formed peripheral circuit.

At S12, a plurality of bit lines36, each of which is in contact with a respective one of the plurality of bit line contact parts212, are formed above the storage area21; and simultaneously a peripheral gate43in contact with the peripheral gate contact part413is formed above the peripheral area41, as shown inFIG. 2CandFIG. 3C.

In some embodiments, the formation of a plurality of bit lines26, each of which is in contact with a respective one of the plurality of bit line contact parts212, above the storage area21and the formation of the peripheral gate43in contact with the peripheral gate contact part413above the peripheral area41may include the following operations.

A bit line material layer is formed on the surface of the substrate, and the bit line material layer at least covers the bit line contact parts212of the storage area21and the peripheral gate contact part413of the peripheral area41, as shown inFIG. 2BandFIG. 3B.

The bit line material layer22is patterned, the bit lines26in contact with the bit line contact parts212are formed in the storage area21, and simultaneously the peripheral gate43in contact with the peripheral gate contact part413is formed in the peripheral area41, as shown inFIG. 2CandFIG. 3C.

In order to reduce the contact resistance between the bit line and the bit line contact part and between the peripheral gate and the peripheral gate contact part, and improve the electrical performance of the semiconductor memory, in some embodiments, the formation of the bit line material layer on the surface of the substrate may include the following operations.

A first conductive layer23is formed on the surface of the substrate, and the first conductive layer23at least covers the bit line contact parts212of the storage area21and the peripheral gate contact part413of the peripheral area41, as shown inFIG. 2AandFIG. 3A.

A second conductive layer24covering the first conductive layer23is formed, as shown inFIG. 2BandFIG. 3B.

A first dielectric layer25covering the second conductive layer24is formed, as shown inFIG. 2BandFIG. 3B.

In some embodiments, the patterning of the bit line material layer may include the following operations.

The first dielectric layer25, the second conductive layer24and the first conductive layer23are etched to form bit lines26in contact with the bit line contact parts212, and form bit line cover layer251located on the top surface of each bit line26in the storage area21; and simultaneously form a peripheral gate43in contact with the peripheral gate contact part413and a peripheral gate cover layer252covering the top surface of the peripheral gate43in the peripheral area41.

Specifically, as shown inFIG. 2AandFIG. 3A, the first conductive layer23is deposited on the surface of the substrate, and the first conductive layer23covers the bit line contact parts212of the storage area21of the substrate and the peripheral gate contact part413of the peripheral area41. The first conductive layer23may continuously cover the entire surface of the substrate, or may only cover the bit line contact parts212of the storage area21and the peripheral gate contact part413of the peripheral area41. Then, the second conductive layer24is deposited on the surface of the first conductive layer23. The material of the second conductive layer24may be different from that of the first conductive layer23. For example, the material of the first conductive layer23is polysilicon, and the material of the second conductive layer24is a metal material (such as tungsten). Then, the first dielectric layer25is deposited on the surface of the second conductive layer24to form a structure as shown inFIG. 2BandFIG. 3B. The material of the first dielectric layer25may be, but is not limited to, a nitride material (such as silicon nitride). The first conductive layer23, the second conductive layer24and the first dielectric layer25together form the bit line material layer. Those skilled in the art may also select other materials or a stack of other numbers of layers as the bit line material layer according to the actual requirements.

After the bit line material layer is formed in the storage area21and the peripheral area41, a first mask layer26covering the bit line material layer is formed. After the first mask layer26is patterned, the bit line material layer is etched to simultaneously form the bit lines36and the peripheral gate43, and to simultaneously form the bit line cover layer251located on the surface of each bit line36and the peripheral gate cover layer252located on the surface of the peripheral gate43. Each bit line36may include a bit line contact layer231and a bit line body layer241covering the surface of the bit line contact layer231. The bit line contact layer231is formed by the first conductive layer23remaining in the storage area21after the bit line material layer is etched, and the bit line body layer241is formed by the second conductive layer24remaining in the storage area21after the bit line material layer is etched. The peripheral gate43may include a peripheral gate contact layer232and a peripheral gate body layer242covering the surface of the peripheral gate contact layer232. The peripheral gate contact layer232is formed by the first conductive layer23remaining in the peripheral area41after the bit line material layer is etched, and the peripheral gate body layer242is formed by the second conductive layer24remaining in the peripheral area41after the bit line material layer is etched.

At S13, a bit line isolation layer at least covering the side wall of the bit line36is formed, and simultaneously a peripheral gate isolation layer at least covering the side wall of the peripheral gate43is formed, as shown inFIG. 2CandFIG. 3C.

In some embodiments, the formation of the bit line isolation layer at least covering the side wall of the bit line36and the formation of the peripheral gate isolation layer at least covering the side wall of the peripheral gate43may include the following operations.

A first isolation layer at least covering the side wall of the bit line36, the side wall of the bit line cover layer251, the side wall of the peripheral gate43and the side wall of the peripheral gate cover layer252is formed.

A second isolation layer covering the first isolation layer is formed.

A third isolation layer covering the second isolation layer is formed. A part of the first isolation layer covering the side wall of the bit line36and the side wall of the bit line cover layer251, the second isolation layer and the third isolation layer form the bit line isolation layer, and a part of the first isolation layer covering the side wall of the peripheral gate43and the side wall of the peripheral gate cover layer252, the second isolation layer and the third isolation layer form the peripheral gate isolation layer.

Specifically, the first isolation layer, the second isolation layer and the third isolation layer are sequentially deposited on the side wall of the bit line36, the side wall and top surface of the bit line cover layer251, the side wall of the peripheral gate43, and the side wall and top surface of the peripheral gate cover layer252. Then, the first isolation layer, the second isolation layer and the third isolation layer are etched. The first isolation layer (i.e., a first sub bit line isolation layer271), the second isolation layer (i.e., a second sub bit line isolation layer272) and the third isolation layer (i.e., a third sub bit line isolation layer273) remaining at the side wall of the bit line36and the side wall of the bit line cover layer251serve as the bit line isolation layer. The part of the first isolation layer (i.e., a first sub peripheral gate isolation layer421), the second isolation layer (i.e., a second sub peripheral gate isolation layer422) and the third isolation layer (i.e., a third sub peripheral gate isolation layer423) covering the side wall of the peripheral gate43and the side wall of the peripheral gate cover layer252serve as the peripheral gate isolation layer. The materials of the first isolation layer and the third isolation layer may be the same, for example, both are nitride materials (such as silicon nitride), and the material of the second isolation layer may be an oxide material (such as silicon oxide). The second isolation layer shall have a relatively high etching selection ratio with respect to the first isolation layer and the third isolation layer, so as to facilitate the subsequent removal of the second isolation layer and form an air gap.

At S14, a first conductive capacitor layer291in contact with the capacitor contact part213is formed above the storage area21, and simultaneously a first peripheral conductive layer292in contact with the peripheral circuit contact part414is formed above the peripheral area41. The first conductive capacitor layer291fills the gap between the adjacent bit lines36, and the first peripheral conductive layer292covers the side wall of the peripheral gate isolation layer, as shown inFIG. 2FandFIG. 3F.

In some embodiments, the formation of the first conductive capacitor layer291in contact with the capacitor contact part213above the storage area21and formation of the first peripheral conductive layer292in contact with the peripheral circuit contact part414above the peripheral area41may include the following operations.

The storage area21and the peripheral area41of the substrate are etched, to expose the capacitor contact part213and the peripheral circuit contact part414simultaneously, as shown inFIG. 2DandFIG. 3D.

A third conductive layer29filling the gap between the adjacent bit lines36and covering the capacitor contact part213, the peripheral circuit contact part414, the bit line isolation layer and the peripheral gate isolation layer is formed, as shown inFIG. 2EandFIG. 3E.

Part of the third conductive layer29is removed to allow the top surface of the third conductive layer29to be located below the bit line cover layer251and the peripheral gate cover layer252. A part of the third conductive layer29remaining in the storage area21forms the first conductive capacitor layer291, and a part of the third conductive layer29remaining in the peripheral area41forms the first peripheral conductive layer292.

Specifically, the storage area21and the peripheral area41of the substrate are etched, and the capacitor contact part213and the peripheral circuit contact part414are simultaneously exposed. A groove28is formed in the substrate while the storage area21is etched. Then, the third conductive layer29is deposited to fill the groove28and the gap between the adjacent bit lines36, and cover the capacitor contact part213, the peripheral circuit contact part414, the surface of the bit line isolation layer and the surface of the peripheral gate isolation layer. Then, part of the third conductive layer29is etched to form the first conductive capacitor layer291in the storage area21and simultaneously form the peripheral conductive layer292in the peripheral area41. The material of the third conductive layer29may be, but is not limited to, polysilicon.

At S15, a first air gap274is formed in the bit line isolation layer, and simultaneously a second air gap424is formed in the peripheral gate isolation layer, as shown inFIG. 2GandFIG. 3H.

In some embodiments, the formation of the first air gap274in the bit line isolation layer and the second air gap424in the peripheral gate isolation layer may include the following operations.

The second isolation layer is removed, the first air gap274is formed at the side wall of the bit line36and the side wall of the bit line cover layer251and located between the first isolation layer and the third isolation layer, and simultaneously the second air gap424is formed at the side wall of the peripheral gate43and the side wall of the peripheral gate cover layer252and located between the first isolation layer and the third isolation layer.

In some embodiments, the third isolation layer also covers the top surface of the bit line cover layer251and the top surface of the peripheral gate cover layer252. The removal of the second isolation layer may include the following operations.

A part of the third isolation layer covering the top surfaces of the bit line cover layer251and the peripheral gate cover layer252is removed, and the second isolation layer is exposed.

All of the second isolation layers are etched away.

Specifically, after the first conductive capacitor layer291and the first peripheral conductive layer292are formed, the third sub bit line isolation layer273and the third sub peripheral gate isolation layer423are synchronously etched to expose the second sub bit line isolation layer272and the second sub peripheral gate isolation layer422, as shown inFIG. 2FandFIG. 3G. Then, the second sub bit line isolation layer272in the bit line isolation layer and the second sub peripheral gate isolation layer422in the peripheral gate isolation layer are removed by a wet etching process, and the first air gap274and the second air gap424are formed simultaneously.

In the specific embodiment, by forming the first air gap274and the second air gap424, the parasitic capacitance of the bit line36and the peripheral gate43may be greatly reduced, and the contact resistance between the first conductive capacitor layer291and the capacitor contact part213may be reduced. Moreover, since the first air gap274and the second air gap424are directly formed by an etching process after the third conductive layer29is directly filled and the first conductive capacitor layer291and the first peripheral conductive layer292are formed, the operations of forming the air gap can be simplified and the efficiency of the semiconductor process can be improved.

In some embodiments, the top surface of the first conductive capacitor layer291is located below the top surface of the bit line cover layer251. After the first air gap274is formed in the bit line isolation layer and the second air gap424is formed in the peripheral gate isolation layer, it may also include the following operations.

An auxiliary layer30covering the side wall of the bit line isolation layer is formed, as shown inFIG. 2H.

A fourth conductive layer31covering the top surface of the first conductive capacitor layer291and the side wall of the auxiliary layer30is formed, as shown inFIG. 2I.

The auxiliary layer30is removed to form a capacitor contact structure including the fourth conductive layer31and the first conductive capacitor layer291, as shown inFIG. 2J.

Specifically, by depositing the fourth conductive layer31after the auxiliary layer30is formed at the side wall of the bit line isolation layer, the stepped capacitor contact structure can be obtained after the auxiliary layer30is removed. In the stepped capacitor contact structure, the width of the fourth conductive layer31in the direction parallel to the substrate is less than that of the top surface of the first conductive capacitor layer291(i.e., the surface of the first conductive capacitor layer291which contacts the fourth conductive layer31). The stepped capacitor contact structure helps to increase the contact area between the subsequently formed second conductive capacitor layer and the capacitor contact structure, so as to reduce the capacitor contact resistance. In the specific embodiment, a capacitor hole is the gap between the adjacent bit lines36.

In some embodiments, after the capacitor contact structure including the fourth conductive layer31and the first conductive capacitor layer291is formed, the method may also include the following operations.

A second conductive capacitor layer32covering the surface of the capacitor contact structure is formed, and simultaneously a second peripheral conductive layer44covering the surface of the first peripheral conductive layer292is formed, as shown inFIG. 2KandFIG. 3I.

Specifically, after the first peripheral conductive layer292as shown inFIG. 3His formed, a part of the first peripheral conductive layer292outside the peripheral circuit contact part414and above part of the peripheral circuit contact part414is partially removed to form the first peripheral conductive layer292as shown inFIG. 3I. Then, a second dielectric layer45is deposited on the surface of the substrate of the peripheral area41, and the second dielectric layer45covers the peripheral circuit contact part414and the first peripheral conductive layer292. Then, the second dielectric layer45is etched, to form a through hole, through which the top surface of the first peripheral conductive layer292(i.e., the surface of the first peripheral conductive layer292away from the peripheral circuit contact part414) is exposed, in the second dielectric layer45. The material of the second dielectric layer45may be an oxide material, such as silicon oxide. Then, a second conductive capacitor layer32covering the surface of the capacitor contact structure is formed, and simultaneously a second peripheral conductive layer44filling the through hole and covering the surface of the second dielectric layer45is formed, as shown inFIG. 2KandFIG. 3I.

After the second conductive capacitor layer32and the second peripheral conductive layer44are formed, a third dielectric layer33covering both the second conductive capacitor layer32and the second peripheral conductive layer44, and a fourth dielectric layer34located on the surface of the third dielectric layer33may also be formed. The material of the third dielectric layer33may be Amorphous Carbon (ACL), and the material of the fourth dielectric layer34may be a nitrogen oxide material, such as silicon oxynitride.

Moreover, the application further provides a semiconductor memory. The semiconductor memory provided in the specific embodiment may be formed by the method shown inFIG. 1,FIG. 2AtoFIG. 2LandFIG. 3AtoFIG. 3I. The specific structure of the semiconductor memory provided in the specific embodiment may refer toFIG. 2LandFIG. 3I. As shown inFIG. 2AtoFIG. 2LandFIG. 3AtoFIG. 3I, the semiconductor memory provided in the specific embodiment may include a substrate, a plurality of bit lines36, a peripheral gate43, a bit line isolation layer, a peripheral gate isolation layer, a first air gap274, a second air gap424, a first conductive capacitor layer291and a first peripheral conductive layer292.

The substrate may include a storage area21and a peripheral area41located outside the storage area21. The substrate has a plurality of bit line contact parts212and a plurality of capacitor contact parts213located in the storage area21, and a peripheral gate contact part413and a peripheral circuit contact part414located in the peripheral area41.

The plurality of bit lines36are located above the storage area21, and each of the bit lines36is in contact with a respective one of the bit line contact parts212.

The peripheral gate43is located above the peripheral area41and in contact with the peripheral gate contact part413.

The bit line isolation layer at least covers the side wall of the bit line36.

The peripheral gate isolation layer at least covers the side wall of the peripheral gate43.

The first air gap274is located in the bit line isolation layer.

The second air gap424is located in the peripheral gate isolation layer.

The first conductive capacitor layer291is located above the storage area21, in contact with the capacitor contact part213, and filled in the gap between the adjacent bit lines36.

The first peripheral conductive layer292is located above the peripheral area41, in contact with the peripheral circuit contact part414, and covers the side wall of the peripheral gate isolation layer.

In some embodiments, the semiconductor memory may also include a bit line cover layer251and a peripheral gate cover layer252.

The bit line cover layer251is located on the top surface of the bit line36, and the bit line isolation layer also covers the side wall of the bit line cover layer251.

The peripheral gate cover layer252is located on the top surface of the peripheral gate43, and the peripheral gate isolation layer also covers the side wall of the peripheral gate cover layer252.

In some embodiments, the semiconductor memory may also include a fourth conductive layer31.

The fourth conductive layer31is located on the top surface of the first conductive capacitor layer291. The width of the fourth conductive layer31in the direction parallel to the surface of the substrate is less than that of the first conductive capacitor layer291.

In some embodiments, the semiconductor memory may also include a second conductive capacitor layer32and a second peripheral conductive layer44.

The second conductive capacitor layer32covers the surface of the fourth conductive layer31and the surface of the first conductive capacitor layer291.

The second peripheral conductive layer44covers the surface of the first peripheral conductive layer292.

In some embodiments, the bit line isolation layer may include a first sub bit line isolation layer271and a third sub bit line isolation layer273. The first air gap274is located between the first sub bit line isolation layer271and the third sub bit line isolation layer.

The peripheral gate isolation layer may include a first sub peripheral gate isolation layer421and a third sub peripheral gate isolation layer423, and the second air gap424is located between the first sub peripheral gate isolation layer421and the third sub peripheral gate isolation layer423.

According to the semiconductor memory and the forming method thereof provided in the specific embodiment, by forming the bit line in the storage area and the peripheral gate in the peripheral area, and by forming the bit line isolation layer covering the side wall of the bit line and having the first air gap and the peripheral gate isolation layer covering the side wall of the peripheral gate and having the second air gap at the same time, the manufacturing steps of the semiconductor memory are simplified, and the manufacturing cost of the semiconductor memory is reduced. Moreover, the formation of the first air gap and the second air gap greatly reduces the parasitic capacitance of the bit line and the peripheral gate, and improves the electrical performance of the semiconductor memory.

The above is only the preferred embodiment of the application. It should be noted that ordinary technicians in the technical field may also make several improvements and refinements without departing from the principles of the application, and these improvements and refinements should also be regarded as the scope of protection of the application.