Sigma delta class D power amplifier and method thereof

A sigma delta class D power amplifier includes a loop filter, a quantizer, and an output stage. The quantizer is coupled to the loop filter and quantifies an error signal according to levels of two reference signals to output a pair of mean signals, wherein different logic combinations of the mean signals belong to one of three quantum states. The output stage is coupled to the quantizer and outputs a corresponding output signal according to the different quantum states to drive a load, wherein a driving current of the output signal belongs to one of the three driving states which include at least a steady state with no current of a power amplifier.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 97141850, filed on Oct. 30, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a power amplifier. More particularly, the present invention relates to a sigma delta class D power amplifier.

2. Description of Related Art

The power amplifier plays an important role in design of integrated circuits, and is widely applied to wireless communications, transmitters/receivers of television broadcasts, high-floutelity stereo equipments, microcomputers and other electronic devices. The power amplifier is used for increasing energy of a signal, so as to drive a load or a next stage circuit. Therefore, quality of the power amplifier is influenced by a power gain thereof, wherein the power gain is a ratio between an output power and an input power. Generally, the greater the power gain is, the better the amplification capability of the power amplifier is, and when an input signal is relatively small, a power gain curve of a general power amplifier may have satisfactory linearity.

According to applications of the power amplifiers, the power amplifiers are categorized into many classes mainly including class A, class B, class AB, class C and class D, etc. For example, the class D power amplifier is widely used for an audio signal processing of a handheld and mobile device since the class D power amplifier has high power conversion efficiency (greater than 90%). Moreover, some of the class D power amplifiers may have pulse width modulators to generate continuous pulses, and the pulse widths are varied according to amplitude of the audio signals, so as to control operations of switch circuits within the class D power amplifiers. However, as to a product having a relatively strict requirement for prevention of signal distortion, performance of the class D power amplifier is not as good as that of the class AB power amplifier. Therefore, a sigma-delta class D power amplifier is developed, which may have a relatively low signal distortion compared to that of the class AB power amplifier, and meanwhile the high power conversion efficiency of the class D power amplifier is still maintained, so that the sigma-delta class D power amplifier is competitive in the market.

However, since a sampling frequency of the conventional sigma-delta class D power amplifier is limited by an over sampling ratio (OSR), a frequency of the sigma-delta class D power amplifier is generally four to five times greater than that of the conventional class D power amplifier, so that a switching loss thereof is much greater than that of the conventional class D power amplifier. Thereby, in case of a relatively small power output, the power conversion efficiency of the conventional sigma-delta class D power amplifier is much less than that of the conventional class D power amplifier. Moreover, a direction of the driving current output by the conventional sigma-delta class D power amplifier only has two states of forward and backward, and a steady state of no current is not provided.

SUMMARY OF THE INVENTION

The present invention provides a sigma delta class D power amplifier including a loop filter, a quantizer, and an output stage module. The loop filter calculates a difference between an input signal and an output signal, and accumulates the difference to generate an error signal. The quantizer is coupled to the loop filter and quantifies the error signal according to levels of a first reference signal and a second reference signal, so as to output a corresponding first mean signal and a corresponding second mean signal. The output stage module is coupled to the quantizer and correspondingly generates the output signal according to the first mean signal and the second mean signal to drive a load, wherein a driving current of the output signal is at least in one of a first driving state, a second driving state and a steady state of no current.

The present invention provides a method for a sigma delta class D power amplifier, which is described as follows. First, an input signal is received, and a difference between the input signal and an output signal is calculated and accumulated to generate an error signal. Next, the error signal is quantified according to levels of a first reference signal and a second reference signal, so as to generate a corresponding first mean signal and a corresponding second mean signal. Next, a corresponding output signal is output according to the first mean signal and the second mean signal to drive a load, wherein a driving current of the output signal is at least in one of a first driving state, a second driving state and a steady state of no current.

In the the sigma delta class D power amplifier of the present invention, the quantizer is applied to quantify the error signal to generate the first mean signal and the second mean signal, wherein a different logic level combination of the first mean signal and the second mean signal corresponds to one of equivalent levels of at least three quantum states. Therefore, the output stage module generates a corresponding driving current according to the first mean signal and the second mean signal output by the quantizer, so as to drive the load. Here, the driving current has a steady state (an equivalent level state) of no current, so that power loss of the power amplifier is reduced.

In order to make the aforementioned and other features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

DESCRIPTION OF EMBODIMENTS

FIG. 1is a block diagram illustrating a sigma delta class D power amplifier according to an embodiment of the present invention. Referring toFIG. 1, the sigma delta class D power amplifier100includes a loop filter120, a quantizer140, an output stage module160and a level generator180.

In detail, the loop filter120calculates a difference between an input signal Vi and an output signal Vo, and accumulates the difference to generate an error signal Ve. The quantizer140is coupled to the loop filter120to receive the error signal Ve. The quantizer140quantifies the error signal Ve according to levels of a first reference signal Vrefp and a second reference signal Vrefn provided by the level generator180, so as to output a corresponding first mean signal M1and a corresponding second mean signal M2. Particularly, different logic level combinations of the mean signals M1and M2respectively correspond to one of three quantum states, wherein the three quantum states are for example, “1”, “0” and “−1”, as that shown inFIG. 4.

Moreover, the output stage module160is coupled to the quantizer140and receives the mean signals M1and M2. The output stage module160generates the corresponding output signal Vo according to different logic level combinations of the mean signals M1and M2to drive a load130. It should be noted that a driving current Io (not shown inFIG. 1) of the output signal Vo used for driving the load130also has different driving states corresponding to different quantum states, wherein the driving state is one of a first driving state, a second driving state and an equivalent level state.

FIG. 2is a circuit diagram illustrating a loop filter according to an embodiment of the present invention. In the present embodiment, the input signal Vi is, for example, differential input signals Vip and Vin, the output signal Vo is, for example, differential output signals Vop and Von, and the error signal Ve is, for example, differential error signals Vep and Ven, though the present invention is not limited thereto. Referring toFIG. 1andFIG. 2, the loop filter120includes continuous-time integrators122and an adder124. The loop filter120provides a loop response to the power amplifier100, accumulates a difference between the input signal Vip and the output signal Vop, and accumulates a difference between the input signal Vin and the output signal Von, so as to generate the differential error signals Vep and Ven after a filtering process is performed.

FIG. 3is a circuit diagram illustrating a quantizer according to an embodiment of the present invention. Referring toFIG. 1andFIG. 3, when a clock signal CLK is at a logic low level, the mean signals M1and M2are both at a logic low level “0”. When the clock signal CLK is at a logic high level, and if the error signal Vep is greater than the reference signal Vrefp, transistors N1and N3are turned on, and a current ID3is then transmitted to a ground terminal GND via transistors N3, N1and N5, so that a node A has the logic low level. Therefore, the node A having the logic low level turns on a transistor P1, so that the mean signal M1has the logic high level “1”. Meanwhile, since the node A has the logic low level, a node B has the logic high level. The node B having the logic high level turns on the transistors N1and N4, so that the mean signal M2has the logic low level “0”. Namely, when the error signal Ve input to the quantizer140is greater than the reference signals Vrefp and Vrefn, a logic level combination of the mean signals M1and M2output by the quantizer140is (1,0), i.e., the quantum state is “1”. Similarly, when the error signal Ve input to the quantizer140is less than the reference signals Vrefp and Vrefn, the logic level combination of the mean signals M1and M2output by the quantizer140is (0,1), i.e., the quantum state is “−1”. It should be noted that when the error signal Vep is less than the reference signal Vrefp, and the error signal Ven is greater than the reference signal Vrefn, the nodes A and B have the logic high level. Therefore, the logic level combination of the mean signals M1and M2output by the quantizer140is (0,0), i.e., the quantum state is “0”.

FIG. 4is a schematic diagram illustrating different logic level combinations of the mean signals M1and M2and levels of the corresponding quantum states. Referring toFIG. 3andFIG. 4, according to the aforementioned relative relation between the differential error signals Vep and Ven (i.e. the error signal Ve) and the reference signals Vrefp and Vrefn, when the differential error signals Vep and Ven (i.e. the error signal Ve) are less then the reference signals Vrefp and Vrefn, the logic level combination of the mean signals M1and M2output by the quantizer140is (0,1), wherein the quantum state corresponding to the logic level combination (0,1) of the mean signals M1and M2is “−1”, as shown inFIG. 4.

Similarly, when the differential error signals Vep and Ven (i.e. the error signal Ve) input to the quantizer140are between the reference signals Vrefp and Vrefn, the logic level combination of the mean signals M1and M2output by the quantizer140is (0,0), and the corresponding quantum state is “0”. Similarly, when the differential error signals Vep and Ven (i.e. the error signal Ve) input to the quantizer140are greater than the reference signals Vrefp and Vrefn, the logic level combination of the mean signals M1and M2output by the quantizer140is (1,0), and the quantum state corresponding to the logic level combination (1,0) of the mean signals M1and M2is “1”.

FIG. 5is a circuit diagram illustrating a quantizer according to another embodiment of the present invention. Referring toFIG. 1andFIG. 5, the error signal Ve output by the loop filter120is assumed to be a single-ended signal. The quantizer140includes comparators142and144and a logic circuit146. The comparators142and144receive the error signal Ve from the loop filter120and the reference signals Vrefp and Vrefn from the level generator180. When the error signal Ve is greater than the reference signals Vrefp and Vrefn, a logic signal L1output by the comparator142has the logic low level “0”, and a logic signal L2output by the comparator144has the logic high level “1”. Next, after the logic signals L1and L2are processed by the logic circuit146, the logic circuit146generates the mean signals M1and M2with the logic level combination of (1,0).

When the error signal Ve is less than the reference signals Vrefp and Vrefn, the comparators142and144respectively output the logic signal L1with the logic high level “1” and the logic signal L2with the logic low level “0”. The logic circuit146receives the logic signals L1and L2, and generates the mean signals M1and M2with the logic level combination of (0,1) after logical processing.

It should be noted that when the error signal Ve is between the reference signal Vrefp and the reference signal Vrefn, the logic signals L1and L2output by the comparators142and144both have logic high level “1”. Therefore, the logic circuit146outputs the mean signals M1and M2with the logic level combination of (0,0).

Therefore, by comparing the error signal Ve with the reference signals Vrefp and Vrefn and after processing of the logic circuit146, the quantizer140outputs the mean signals M1and M2. The logic level combinations of the mean signals M1and M2correspond to three different quantum states (for example, “−1”, “0” and “1”).

FIG. 6is a schematic diagram illustrating the output stage module160and a driven load130according to an embodiment of the present invention. The output signal Vo of the output stage module160is represented by Vswo1and Vswo2. Referring toFIG. 6, the output stage module160of the present embodiment is a full-bridge output stage module which not only includes power transistors Q1-Q4but also includes logic units162and164, and the load130is, for example, a speaker. The output stage module160is coupled to the quantizer140, and the logic units162and164respectively receive the mean signals M1and M2, and generate the corresponding output signal Vo (i.e. Vswo1and Vswo2ofFIG. 6) according to the logic levels of the mean signals M1and M2, so as to drive the load130. Here, the driving current Io of the output signal Vo is in one of the first driving state, the second driving state and the equivalent level state.

In detail, if the logic level of the mean signal M1received by the logic unit162is at the logic high level “1”, the logic unit162correspondingly generates signals S1and S2of (0,0). The signals S1and S2with the logic low level “0” can respectively turn on the transistor Q1and turn off the transistor Q2. Now, the output signal Vswo1has the logic high level “1”. Conversely, if the logic level of the mean signal M1received by the logic unit162is at the logic low level “0”, the logic unit162correspondingly generates the signals S1and S2of (1,1), so that the output signal Vswo1has the logic low level “0”.

Similarly, the logic unit164outputs signals S3and S4according to the logic level of the mean signal M2. Therefore, the logic unit164can turn on/off the transistors Q3and Q4according to the signals S3and S4, and further determine the logic level of the output signal Vsmo2. When the mean signal M2has the logic high level “1”, the logic unit164correspondingly generates the signals S3and S4of (0,0), so that the output signal Vswo2has the logic high level “1”. When the mean signal M2has the logic high level “0”, the logic unit164correspondingly generates the signals S3and S4of (1,1), so that the output signal Vswo2has the logic low level “0”.

FIG. 7is a waveform diagram illustrating output states of the driving current Io and the corresponding output signal Vo (i.e. Vswo1and Vswo2) according to an embodiment of the present invention. Referring toFIG. 6andFIG. 7, according to operational principles of the logic units162and164and the transistors Q1-Q4, when the logic level combination of the mean signals M1and M2received by the output stage module160is (1,0) (namely, the quantum state of the quantizer140is “1”), the logic level of the output signals Vswo1and Vswo2of the output stage module160is (1,0). Namely, the output signal Vswo1has the high logic level and the output signal Vswo2has the low logic level. Therefore, the driving current Io flows from the output signal Vswo1side to the output signal Vswo2side. In the present embodiment, as shown inFIG. 6, the driving current Io flows from a drain (i.e. a D2point marked inFIG. 6) of the transistor Q1to a drain (i.e. a D4point marked inFIG. 6) of the transistor Q4, so as to drive the load130. Now, a state of the driving current Io is defined to be the first driving state (or a forward current driving state).

Similarly, when the logic level combination of the mean signals M1and M2received by the output stage module160is (0,1) (namely, the quantum state of the quantizer140is “−1”), the logic level of the output signals Vswo1and Vswo2of the output stage module160is (0,1). Therefore, the driving current Io flows from a drain (i.e. a D4point marked inFIG. 6) of the transistor Q3to a drain (i.e. a D2point marked inFIG. 6) of the transistor Q2, so as to drive the load130. Now, a state of the driving current Io is defined to be the second driving state (or a backward current driving state).

It should be noted that when the logic level combination of the mean signals M1and M2received by the output stage module160is (0,0) (namely, the quantum state of the quantizer140is “0”), the logic level of the output signals Vswo1and Vswo2of the output stage module160is (0,0). Namely, when the level of the output signal Vswo1is equal to the level of the output signal Vswo2(in the present embodiment, the output signals Vswo1and Vswo2both have a ground level), no driving current Io flows through the load130; namely, the state of the driving current Io is defined to be the equivalent level state (or no current driving state), and now the load130has no power consumption. Those of ordinary skills in the art can also implement the equivalent level state by other methods with reference to the aforementioned descriptions based on actual requirements. For example, the output signals Vswo1and Vswo2may simultaneously have the logic high level. In other embodiments, the transistors Q1-Q4can be all turned off, so that the output signals Vswo1and Vswo2are in a floating state, so as to implement the equivalent level state.

The power amplifier100of the present embodiment utilizes the quantizer140to generate 1.5 bits mean signals M1and M2. Here, the logic level combinations of the mean signals M1and M2correspond to the three different quantum states (i.e. “−1”, “0” and “1”). The quantum states correspond to the driving states (i.e. the second driving state, the equivalent level state, and the first driving state) of the driving current Io output by the output stage module160. Here, the equivalent level state represents that no driving current Io flows through the load130. Therefore, the power amplifier100of the present embodiment can additionally provide a steady state of no current (the equivalent level state), so as to reduce a power loss of the power amplifier.

FIG. 8is a block diagram illustrating a power amplifier according to another embodiment of the present invention. Referring toFIG. 8, the power amplifier200of the present embodiment is similar to the power amplifier of the aforementioned embodiment, and a difference there between is that the power amplifier200further includes a waveform generator250. The waveform generator250generates a triangle wave (for example, a sawtooth wave) according to the reference signals Vrefp and Vrefn of a level generator280, so as to provide a reference frequency for a loop filter220. It should be noted that the levels of the reference signals Vrefp and Vrefn used by a quantizer240of the present embodiment relate to a maximum value and a minimum value of the level of the triangle wave.

FIG. 9Ais a diagram illustrating a relation between the level of the triangle wave and the levels of the reference signals. Referring toFIG. 8andFIG. 9A, the waveform generator250of the present embodiment generates a triangle wave Vf to provide the reference frequency to the loop filter220, wherein a maximum value Vfmax of the level of the triangle wave Vf is equal to the level of the reference signal Vrefp, and a minimum value Vfmin of the level of the triangle wave Vf is equal to the level of the reference signal Vrefn, wherein the maximum value Vfmax and the minimum value Vfmin of the level of the triangle wave are between a system level VDD and the ground level GND.

According to the above design, when the input signal Vi is closed to a low level signal, the quantizer240does not output a pulse-width modulation (PWM) signal with a duty cycle of 50%, but outputs a PWM signal with a duty cycle of 0%. By such means, when the input signal Vi is started to be amplified, the output stage module260can automatically and gradually amplify the duty cycle, so as to avoid an excessive inductor current and a pop-noise phenomenon occurred when the power amplifier starts to operate. Moreover, design of an extra logic circuit is unnecessary.

FIG. 9BandFIG. 9Care diagrams illustrating relations between the level of the triangle wave and the levels of the reference signals according to other embodiments of the present invention. Referring toFIG. 9BandFIG. 9C, the maximum value Vfmax of the level of the triangle wave ofFIG. 9Bis grater than the level of the reference signal Vrefp, and the minimum value Vfmin of the level of the triangle wave is less than the level of the reference signal Vrefn, wherein the level of the reference signal Vrefp is greater than the level of the reference signal Vrefn. Conversely, the maximum value Vfmax of the level of the triangle wave ofFIG. 9Cis less than the level of the reference signal Vrefp, and the minimum value Vfmin of the level of the triangle wave is greater than the level of the reference signal Vrefn. Here, the levels of the reference signals Vrefp and Vrefn are between the system level VDD and the ground level GND which are shown as the level relations inFIG. 9BandFIG. 9C.

With the loop filter220and the quantizer240of the present embodiment and the level relations of the triangle wave Vf and the reference signals Vrefp and Vrefn ofFIG. 9BandFIG. 9C, the equivalent state of the driving current Io can also be achieved. Here, the waveform generator250generates the triangle wave Vf according to the reference signals Vrefp and Vrefn, so as to provide the reference frequency to the loop filter220, and the reference signals Vrefp and Vrefn of the level generator280provide quantification reference levels for the error signal Ve quantified by the quantizer240.

The following flowchart is deduced from the aforementioned embodiments.FIG. 10is a flowchart illustrating a method of reducing a power loss of a sigma delta class D power amplifier according to an embodiment of the present invention. Referring toFIG. 10, first, the input signal Vi is received (step S301). As described in the embodiment ofFIG. 2, a difference between the input signal Vi and the output signal Vo is calculated and accumulated to generate the error signal Ve (step S302).

The error signal Ve is quantified according to the levels of the reference signals Vrefp and Vrefn to generate the mean signals M1and M2(step S303). As described in the embodiment ofFIG. 4, when the mean signal M1has the logic high level, and the mean signal M2has the logic low level, the corresponding quantum state is “1”. When the mean signal M1has the logic low level, and the mean signal M2has the logic high level, the corresponding quantum state is “−1”. When the mean signals M1and M2both have the logic low level, the corresponding quantum state is “0”.

The corresponding output signal Vo is generated according to the logic levels of the mean signals M1and M2to drive the load (step S304). As described in the embodiment ofFIG. 7, the driving current Io of the output signal Vo is in one of the first driving state, the second driving state and the equivalent level state.

In summary, the sigma delta class D power amplifier utilizes the quantizer to quantify the error signal to generate the mean signals, wherein a different logic level combination of the mean signals corresponds to one of the equivalent levels of the three quantum states. The output stage module generates a corresponding driving current according to the mean signals output by the quantizer, wherein the driving current has a steady state (the equivalent level state) of no current.

In some embodiments, with the loop filter and the quantizer of the power amplifier and the level relations of the triangle wave and the reference signals, not only the excessive inductor current and the pop-noise phenomenon occurring when the power amplifier starts to operate can be avoided, but also the driving current may have a steady state of no current.