Semiconductor apparatus and calibration method thereof

A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison voltage generation unit is disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal. The calibration unit is configured to compare a level of the reference voltage with a level of the comparison voltage and generate the calibration control signal.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean Application No. 10-2009-0093574, filed on Sep. 30, 2009, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as if set forth in full.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor apparatus, and more particularly, to a semiconductor apparatus and a calibration method thereof.

2. Related Art

Semiconductor apparatuses, specifically memory apparatuses such as a dynamic random access memory (DRAM), are constantly required to be reduced in size and increased in capacity and performance. Accordingly, memory apparatuses are highly integrated and it is necessary to increase the capacity of a unit package to meet this requirement. From this need, technologies have been developed which increase the capacity of semiconductor apparatuses while packaging a plurality of chips into a single package. Furthermore, recent studies have been extensively conducted on three-dimensional (3D) package semiconductor apparatuses using a Through Silicon Via (TSV) technology in which a via passes through a plurality of stacked chips so that they can be electrically connected together.

The plurality of chips contained in a single package operates as a single semiconductor apparatus. Thus, characteristics of the respective chips with respect to process, voltage and temperature (PVT) variations must coincide with one another. However, due to constraints imposed by semiconductor fabrication processes for fabricating a large number of chips on a wafer, the stacked chips constituting a single semiconductor apparatus inevitably have varied characteristics from one another.

SUMMARY

Various embodiments of the invention may provide a semiconductor apparatus and a calibration method thereof in which a plurality of stacked dies may have the substantially same characteristics are described herein.

In one embodiment of the present invention, a semiconductor apparatus with a plurality of stacked dies comprises: a reference voltage generation unit disposed in a reference die and configured to generate a reference voltage; a comparison voltage generation unit disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal; and a calibration unit configured to compare a level of the reference voltage with a level of the comparison voltage to generate the calibration control signal.

In another embodiment of the present invention, a method for calibrating a semiconductor apparatus with a plurality of stacked dies comprises: selecting any one of the plurality of dies as a reference die, generating a reference voltage from the reference die; comparing a level of the reference voltage with levels of comparison voltages generated from the dies other than the reference die, and calibrating the levels of the comparison voltages to be substantially equal to the level of the reference voltage.

DETAILED DESCRIPTION

Advantages and characteristics of the present invention and a method for achieving them will be apparent with reference to embodiments described below in addition to the accompanying drawings. However, the present invention is not limited to the exemplary embodiments described below but may be implemented in various forms. Therefore, the exemplary embodiments are provided to enable those skilled in the art to thoroughly understand the teaching of the present invention and to completely inform the scope of the present invention and the exemplary embodiment is just defined by the scope of the appended claims. Throughout the specification, like elements refer to like reference numerals

FIG. 1is a block diagram schematically illustrating a configuration of a semiconductor apparatus according to one is embodiment of the present invention. InFIG. 1, the semiconductor apparatus1comprises a plurality of stacked dies. The plurality of dies may be comprised in a single package. Although the semiconductor apparatus1is illustrated with five stacked dies inFIG. 1, the present invention may also be applied to any semiconductor apparatus, regardless of the number of stacked dies.

Referring toFIG. 1, the semiconductor apparatus1according to one embodiment comprises a reference die10, first to fourth stacked dies20to50, and a calibration unit100. The reference die10comprises a reference voltage generation unit11. The reference die10may be an arbitrary die selected among the plurality of dies comprised in the single package. The reference voltage generation unit11may be configured using an arbitrary logic circuit provided in the reference die10. That is, the reference voltage generation unit11may be configured using any logic circuit which is capable of generating a reference voltage Vref having a level between an external voltage VDD and a ground voltage VSS, upon operation of the semiconductor apparatus1.

The first to fourth stacked dies20to50comprise first to fourth comparison voltage generation units21,31,41and51, respectively. InFIG. 1, the first stacked die20comprises a first comparison voltage generation unit21configured to generate a first comparison voltage V1in response to a first calibration control signal cal1<0:n−1>, and the second stacked die30comprises a second comparison voltage generation unit31configured to generate a second comparison voltage V2in response to a second calibration control signal cal2<0:n−1>. Also, the third stacked die40comprises a third comparison voltage generation unit41configured to generate a third comparison voltage V3in response to a third calibration control signal cal3<0:n−1>, and the fourth stacked die50comprises a fourth comparison voltage generation unit51configured to generate a fourth comparison voltage V4in response to a fourth calibration control signal cal4<0:n−1>.

The calibration unit100compares the level of the reference voltage Vref with the levels of the first to fourth comparison voltages V1to V4, and performs a calibration operation to make the first to fourth comparison voltages V1to V4have the substantially same level as the level of the reference voltage Vref. The calibration unit100comprises a voltage comparison unit110and a calibration control unit120. The voltage comparison unit110compares the level of the reference voltage Vref with the levels of the first to fourth comparison voltages V1to V4to generate a control signal CTRL. The calibration control unit120generates the calibration control signals cal1<0:n−1> to cal4<0:n−1> in response to the control signal CTRL. The calibration control signals cal1<0:n−1> to cal4<0:n−1> may be multi-bit code signals. The control signal CTRL may be used to increase or decrease code values of the multi-bit calibration control signals cal1<0:n−1> to cal4<0:n−1>. The voltage comparison unit110may be configured with a general comparator circuit which compares the level of the reference voltage Vref with the levels of the is first to fourth comparison voltages V1to V4to generate the control signal CTRL. The calibration control unit120may be configured with a general counting circuit which increases or decreases the code values of the calibration control signals cal1<0:n−1> to cal4<0:n−1> in response to the control signal CTRL. As described above, the calibration unit100may be configured by adopting any conventional logic circuits for calibration operations.

Although the calibration unit100is shown to be disposed outside the dies10to50inFIG. 1, the calibration unit100may be disposed inside any one of the reference die10and the first to fourth stacked dies20to50. The dies10to50and the calibration unit100may be electrically connected together through a TSV. For example, when the calibration unit100is disposed in the reference die10, the first to fourth comparison voltages V1to V4may be transferred to the voltage comparison unit110disposed in the reference die10, and the calibration control signals cal1<0:n−1> to cal4<0:n−1> generated from the calibration control unit120may be transferred to the first to fourth comparison voltage generation units21,31,41, and51through the TSV, respectively.

As a representative example, the operation of calibrating the first comparison voltage V1is described below. The voltage comparison unit110of the calibration unit100compares the level of the reference voltage Vref generated from the reference voltage generation unit11with the level of the first comparison voltage V1generated from the first comparison voltage generation unit21of the first stacked die20. For example, when the level of the reference voltage Vref is higher than the level of the first comparison voltage V1, the voltage comparison unit110may generate the control signal CTRL which enables the calibration control unit120to decrease the code value of the first calibration control signal cal1<0:n−1>. On the other hand, when the level of the reference voltage Vref is lower than the level of the first comparison voltage V1, the voltage comparison unit110may generate the control signal CTRL which enables the calibration control unit120to increase the code value of the first calibration control signal cal1<0:n−1>. When the level of the first comparison voltage V1is substantially equal to the level of the reference voltage Vref, the voltage comparison unit110may generate the control signal CTRL which enables the calibration control unit120not to change the code values of the first calibration control signals cal1<0:n−1> any more and maintains the determined code values. Therefore, the level of the first comparison voltage V1is calibrated so that it becomes substantially equal to the level of the reference voltage Vref generated from the reference die10. After the calibration operation is completed, the first calibration control signal cal1<0:n−1> for generating the first comparison voltage V1substantially equal to the reference voltage Vref has information on skew between the reference die10and the first stacked die20. Hence, the first calibration control signal cal1<0:n−1> may be used in a logic circuit comprised in the first stacked die10which is required to correct the skew with respect to the reference die10. That is, the is skew between the reference die10and the first stacked die20may be corrected by the first calibration control signal cal1<0:n−1>.

The second to fourth comparison voltages V2to V4generated from the second to fourth stacked dies30to50may be calibrated to be substantially equal to the reference voltage Vref in the same manner as the case of the first comparison voltage V1. The above-described calibration operation is merely exemplary, and may be changed according to an adopted calibration scheme.

FIG. 2is a circuit diagram illustrating an example of the reference voltage generation unit11ofFIG. 1. Referring toFIG. 2, the reference voltage generation unit11may be configured with an inverter which comprises a first p-type metal oxide semiconductor (PMOS) transistor P1and an n-type metal oxide semiconductor (NMOS) transistor N1. As described above, the inverter comprising the reference voltage generation unit11is merely exemplary, and the reference voltage generation unit11may be configured using any logic circuit provided in the reference die10. The first PMOS transistor P1has a gate receiving a pull-up signal pull_up, a source connected to an external voltage (VDD) terminal, and a drain connected to a first node A. The first NMOS transistor N1has a gate receiving a pull-down signal pull-dn, a source connected to a ground voltage (VSS) terminal, and a drain connected to the first node A. Therefore, the reference voltage generation unit11may generate the reference voltage Vref through the first node A, depending on the sizes of the first PMOS transistor P1and the first NMOS transistor N1and the voltage levels of the pull-up signal pull_up and the pull-down signal pull_dn. Thus, the reference voltage Vref has a level between the external voltage VDD and the ground voltage VSS, and is an arbitrary voltage which may be varied depending on types of the logic circuit used as the reference voltage generation unit11. The pull-up signal pull_up and the pull-down signal pull_dn may be defined as general input signals of the logic circuit used as the reference voltage generation unit11.

FIG. 3is a circuit diagram illustrating an example of the first comparison voltage generation unit21ofFIG. 1according to comparison voltage generation unit21may comprise a plurality of pull-up transistors up1to upn and a plurality of pull-down transistors dn1to dnn configured to receive the first calibration control signal cal1<0:n−1>. The pull-up transistors up1to upn and the pull-down transistors dn1to dnn are connected in series to constitute a plurality of legs connected in parallel. The first pull-up transistor up1and the first pull-down transistor dn1may receive the first bit cal1<0> of the first calibration control signal cal1<0:n−1>, and the nth pull-up transistor upn and the nth pull-down transistor dnn may receive the nth bit of the first calibration control signal cal1<0:n−1>. Therefore, the pull-up transistors up1to upn may apply the external voltage VDD to a second node B according to the bit logic values of the first calibration control signals cal1<0:n−1>, and the pull-down transistors dn1to dnn may apply the ground voltage VSS to the second node B is according to the bit logic values of the first calibration control signal cal1<0:n−1>. In such a configuration, the first comparison voltage generation unit21may generate the first comparison voltage V1, whose voltage level is varied according to the first calibration control signal cal1<0:n−1>, through the second node B.

The second to fourth comparison voltage generation units31,41and51have the same configuration as the first comparison voltage generation unit21. However the difference from the first comparison voltage generation unit21is that the second to fourth calibration control signals cal2<0:n−1> to cal4<0:n−1> are applied to the second to fourth comparison voltage generation unit31,41and51, respectively.

The first to fourth comparison voltage generation units21,31,41and51are disposed in certain regions inside the first to fourth stacked dies20,30,40and50where the first to fourth comparison voltage generation units21,31,41and51are comprised, respectively, while corresponding to the region where the reference voltage generation unit11is disposed inside the reference die10. Since the semiconductor apparatus1according to the embodiment is configured to reduce the skew and variation between the plurality of stacked dies comprised in the single package, the correction of the skew and variation between the circuits provided in the regions corresponding to the respective stacked dies is the most efficient method that can correct the skew and variation between the stacked dies.

In the semiconductor apparatus1according to one embodiment, the reference die10is selected among the stacked dies10to50, and the level of the reference voltage Vref generated from the logic circuit disposed inside the reference die10, that is, the reference voltage generation unit11, is compared with the levels of the comparison voltages V1to V4generated from the comparison voltage generation units21,31,41and51disposed in the dies20to50other than the reference die10. The calibration operation is repeated until the levels of the comparison voltages V1to V4become substantially equal to the level of the reference voltage Vref. The calibration operation is stopped when the levels of the comparison voltages V1to V4become substantially equal to the level of the reference voltage Vref through the calibration operation. The calibration control signals cal1<0:n−1> to cal4<0:n−1> obtained through the calibration operation may be used in any logic circuits provided in the stacked dies20to50which require the calibration operation.

Therefore, the skew between the stacked dies may be corrected using the calibration results. That is, the respective stacked dies may have the substantially same characteristics. Consequently, normal operation between the respective dies is possible, and the increased operation speed and improved operation performance of the semiconductor apparatus may be ensured.