Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a first electronic component having a first surface and a second surface opposite the first surface. The semiconductor device package further includes a first pad disposed on the first surface of the first electronic component. The first pad has a first surface facing away from the first surface of the first electronic component, a second surface opposite the first surface of the first pad, and a lateral surface extended between the first surface of the first pad and the second surface of the first pad. The semiconductor device package further includes a second pad disposed on the first surface of the first pad. The second pad has a first surface facing away from the first surface of the first pad, a second surface opposite the first surface of the second pad, and a lateral surface extended between the first surface of the second pad and the second surface of the second pad. A width of the first surface of the second pad is greater than a width of the second surface of the second pad. A method of manufacturing a semiconductor device package is also disclosed.

BACKGROUND

1. Technical Field

The present disclosure generally relates to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package including conductive pillars and conductive pads.

2. Description of the Related Art

In comparative semiconductor structures, conductive elements (e.g., conductive pillars, pads or bumps) are used as interconnections for two or more devices. As the pitch of the conductive elements is further reduced to accommodate increasing I/O pins, it becomes more challenging to align the interconnections.

SUMMARY

In one or more embodiments, a semiconductor device package includes a first electronic component having a first surface and a second surface opposite the first surface. The semiconductor device package further includes a first pad disposed on the first surface of the first electronic component. The first pad has a first surface facing away from the first surface of the first electronic component, a second surface opposite the first surface of the first pad, and a lateral surface extended between the first surface of the first pad and the second surface of the first pad. The semiconductor device package further includes a second pad disposed on the first surface of the first pad. The second pad has a first surface facing away from the first surface of the first pad, a second surface opposite the first surface of the second pad, and a lateral surface extended between the first surface of the second pad and the second surface of the second pad. A width of the first surface of the second pad is greater than a width of the second surface of the second pad.

In one or more embodiments, a semiconductor device package includes a first electronic component having a first surface and a second surface opposite the first surface and a second electronic component having a surface facing the first surface of the first electronic component. The semiconductor device package further includes a first pad disposed on the first surface of the first electronic component. The first pad has a first surface and a second surface. The semiconductor device package further includes a second pad disposed on the first surface of the first pad. The second pad has a first surface and a second surface. The semiconductor device package further includes a conductive pillar electrically connected the surface of the second electronic component with the first surface of the second pad. A width of the second surface of the second pad is smaller a width of the second surface of the first pad.

In one or more embodiments, a method for manufacturing a semiconductor device package includes providing an electronic component and disposing a first photoresist on the electronic component. The first photoresist has an opening. The method further includes forming a first conductive layer in the opening. The first conductive layer has a first surface exposed from the first photoresist. The method further includes disposing a second photoresist to cover the first surface of the first conductive layer. The method further includes removing a part of the second photoresist to expose a part of the first surface of the first conductive layer.

DETAILED DESCRIPTION

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

FIG. 1illustrates a cross-sectional view of a semiconductor device package1in accordance with some embodiments of the present disclosure. The semiconductor device package1includes a substrate10, electronic components11and12, passivation layers13and17, a conductive layer14, a dielectric layer15, an underfill16, conductive pads18a,18b, and18c, and a conductive pillar19.

The electronic component11has a surface111(e.g., an active surface) facing the electronic component12(e.g., an active surface of the electronic component12) and a surface112opposite the surface111.

Each of the electronic components11and12may be a chip or a die including a semiconductor substrate, one or more integrated circuit devices and one or more overlying interconnection structures therein. The integrated circuit devices may include active devices such as transistors and/or passive devices such as resistors, capacitors, inductors, or a combination thereof.

The passivation layer13is disposed on the surface111of the electronic component11. The passivation layer13covers a portion of the surface111and exposes a conductive pad13aprovided on the electronic component11. In some embodiments, the passivation layer13may include, for example, silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide. In some embodiments, the conductive pad13amay include, for example, aluminum (Al), copper (Cu), or other suitable metal, or a mixture, an alloy, or other combination of two or more thereof.

The conductive layer14is disposed on the electronic component11. The conductive layer14may be partially covered by the passivation layer13. The conductive layer14is electrically connected to the conductive pad13a. The conductive layer14may include, for example, titanium (Ti), Cu, nickel (Ni), another metal, or an alloy (such as a titanium-tungsten alloy (TiW)). In some embodiments, the conductive layer14may be a seed layer.

The conductive pads18aand18care disposed on the conductive layer14. The conductive pad18cis disposed adjacent to the conductive pad18aand spaced apart from the conductive pad18a.

The conductive pad18bis disposed on the conductive pad18a. In other words, the conductive pad18ais disposed between the conductive layer14and the conductive pad18b.

The conductive pillar19is disposed on the electronic component12. The conductive pillar19may be partially covered by the passivation layer17provided on a surface of the electronic component12facing the electronic component11. The conductive pillar19is bonded with the conductive pad18bto electrically connect the electronic component12(such as the interconnection structures in the electronic component12) to the conductive pad13a.

Each of the conductive pads18a,18b, and18cand the conductive pillar19may include, for example, gold (Au), silver (Ag), Cu, Ni, palladium (Pd), another metal, a solder alloy, or a combination of two or more thereof.

In some embodiments, the conductive pads18a,18b, and18cmay be a redistribution layer (RDL) or a grounding element.

The dielectric layer15is disposed on the surface111of the electronic component11to cover or encapsulate the conductive pads18aand18c. For example, the dielectric layer15covers or encapsulates the sidewalls and the top surfaces of the conductive pads18aand18c. The dielectric layer15surrounds the sidewall of the conductive pad18b.

In some embodiments, the dielectric layer15may include, for example, one or more organic materials (e.g., phosphoric anhydride (PA), a polyimide (PI), a polybenzoxazole (PBO), an epoxy, and an epoxy-based material), or one or more inorganic materials (e.g., silicon, a glass, a ceramic, and an oxide). In some embodiments, the dielectric layer15may include, for example, photoresist, such as positive photoresist or negative photoresist.

The underfill16(or may also be referred to as a package body) is disposed between the dielectric layer15and the passivation layer17.

In some embodiments, the underfill16may include, for example, an epoxy resin, a molding compound (e.g., an epoxy molding compound or other molding compounds), a polyimide, a phenolic compound or material, a material including a silicone dispersed therein, or a combination thereof.

The substrate10is electrically connected to the electronic component11through an electrical contact10b(e.g. a solder ball) provided on the surface112of the electronic component11. The substrate10may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. The substrate10may include one or more conductive pads10ain proximity to, adjacent to, or embedded in and exposed at a surface of the substrate10.

The electrical contact10bis disposed on the conductive pads10a. In some embodiments, the electrical contact10bincludes a controlled collapse chip connection (C4) bump, a ball grid array (BGA) or a land grid array (LGA).

In some comparative embodiments, the conductive pad18bcan be omitted, and a longer conductive pillar19is electrically connected to the conductive pad13aonly through the conductive pad18a. However, the distance between the dielectric layer15and the conductive pad18a(e.g., the alignment tolerance) is about 2 micrometers (μm)—which suppresses the manufacturing speed—and the conductive pillar19may be cracked or bent by the dielectric layer15.

As shown inFIG. 1, the conductive pad18cis covered in the dielectric layer15and does not contact the conductive pillar19. The conductive pad18b, which contacts the conductive pillar19, is higher or elevated in comparison with the other conductive pads (such as the conductive pad18c). As such, the conductive pillar19contacts the conductive pad18bprecisely, achieving a highly accurate alignment and preventing the conductive pillar19from being cracked or bent by the dielectric layer15.

In addition, the alignment tolerance can be increased and the manufacturing speed can be accelerated. For example, in comparison with a device package without an elevated conductive pad for bonding to the pillar, the alignment tolerance can be increased from about 2 μm to about 20 μm, and the units produced per hour can be boosted by about 10 times.

AlthoughFIG. 1shows that there is one conductive pad that is elevated with respect to the other six conductive pads (spaced apart from the one conductive pad) to provide electrical connections between the electronic components11and12, the present disclosure is not limited thereto. In some embodiments, there may be any number of conductive pads depending on product specifications.

FIG. 2illustrates an enlarged view of a portion in a dotted box A as shown inFIG. 1in accordance with some embodiments of the present disclosure.

The conductive pad18ahas a surface18a1facing away from the electronic component11, a surface18a2opposite the surface18a1, and a lateral surface (or a sidewall)18a3extended between the surface18a2and the surface18a1.

The conductive pad18atapers toward the electronic component11. For example, the lateral surface18a3defines an acute angle with the surface18a1. For example, a width (denoted as “w2” inFIG. 2) of the surface18a1is greater than a width (denoted as “w1” inFIG. 2) of the surface18a2.

The conductive pad18bhas a surface18b1facing away from the electronic component11, a surface18b2opposite the surface18b1, and a lateral surface (or a sidewall)18b3extended between the surface18b2and the surface18b1.

The conductive pad18btapers toward the surface111of electronic component11. For example, the lateral surface18b3defines an acute angle with the surface18b1. For example, a width (denoted as “w4” inFIG. 2) of the surface18b1is greater than a width (denoted as “w3” inFIG. 2) of the surface18b2.

The width w2of the surface18a1is greater than the width w3of the surface18b2.

The surface18b2is in contact with the surface18a1. The surface18a1is partially covered by the surface18b2. For example, a part of the surface18a1is covered by the surface18b2, while the other part of the surface18a1is covered by the dielectric layer15.

The dielectric layer15surrounds or covers the lateral surface18a3of the conductive pad18a. The dielectric layer15surrounds or covers the lateral surface18b3of the conductive pad18b. The lateral surface18a3of the conductive pad18amay be fully surrounded or covered by the dielectric layer15. The lateral surface18b3of the conductive pad18bmay be fully surrounded or covered by the dielectric layer15.

The surface18b1of the conductive pad18bis not covered by the dielectric layer15. In other words, the surface18b1of the conductive pad18bis exposed from the dielectric layer15. The surface18b1of the conductive pad18bis in contact with an electrical contact19a(e.g. a solder ball) and is electrically connected to the conductive pillar19through the electrical contact19a.

In some embodiments, the dielectric layer15releases the stress concentration generated on heterojunction (as in the interface between the underfill16and the conductive pad18awhen the conductive pad18ais not surrounded by the dielectric layer15) caused by, for example, a die saw or a thermal test.

In some embodiments, the dielectric layer15fully covers the lateral surface18b3and isolates the lateral surface18b3from the electrical contact19a, thereby preventing the formation of intermetallic compounds (IMC) and enhancing the reliability of the device package.

The underfill16is in contact with the dielectric layer15and defines an interface151with the dielectric layer15. The underfill16surrounds or covers the portion of the dielectric layer15that surrounds the lateral surface18b3of the conductive pad18b. For example, the lateral surface18b3of the conductive pad18bis surrounded by the dielectric layer15and further surrounded by the underfill16. For example, a portion of the dielectric layer15is between the conductive pad18band the underfill16.

The interface151between the underfill16and the dielectric layer15has a portion151aand a portion151bconnected with and adjacent to the portion151a. The portion151ais closer to the conductive pad18b. The portion151ais proximal to the conductive pad18b, while the portion151bis distal from the conductive pad18b.

The portion151ais not coplanar with the portion151b. For example, the portion151ais recessed from the portion151b. For example, the portion151adefines a cavity, which is filled by the underfill16. In some embodiments, the recessed portion enhances the adhesion strength between the dielectric layer15and the underfill16.

In some embodiments, the portion151ais relatively rough as a result of the etching operation as illustrated inFIG. 4J. For example, the surface roughness of the portion151ais higher than the surface roughness of the portion151b. For example, the surface topography of the portion151ahas a substantially concave shape.

The portion of the dielectric layer15that surrounding the lateral surface18b3of the conductive pad18bhas a surface approximately perpendicular to the interface151between the underfill16and the dielectric layer15. For example, the dielectric layer15may have a surface approximately perpendicular to the portion151bof the interface151after the etching operation as illustrated inFIG. 4J.

FIG. 3illustrates a cross-sectional view of a semiconductor device package3in accordance with some embodiments of the present disclosure. The semiconductor device package3is similar to the semiconductor device package1inFIG. 1, and the differences therebetween are described below.

The interface151between the underfill16and the dielectric layer15is substantially at the same level or elevation. For example, no recessed portion (such as the portion151ainFIG. 2) can be observed. In some embodiments, the interface151may be uneven due to an etching operation is conducted without employing a photoresist film (or a mask) as illustrated inFIG. 5A. In such embodiments, the interface151may fluctuate at the same level, elevation, or scale throughout the interface151.

FIG. 4A,FIG. 4B,FIG. 4C,FIG. 4D,FIG. 4E,FIG. 4F,FIG. 4G,FIG. 4H,FIG. 4I,FIG. 4J,FIG. 4K, andFIG. 4L, are cross-sectional views of a semiconductor device package at various stages of fabrication, in accordance with some embodiments of the present disclosure. At least some of these figures have been simplified for a better understanding of the aspects of the present disclosure.

Referring toFIG. 4A, an electronic component11is provided. The electronic component11has a surface111and a surface112opposite the surface111. The electronic component11includes a conductive pad13aexposed from a passivation layer13provided on the surface111of the electronic component11.

Referring toFIG. 4B, a conductive layer14(or a seed layer) is disposed on the passivation layer13to electrically connect to the conductive pad13a. In some embodiments, the conductive layer14is formed by, for example, sputtering titanium and copper (Ti/Cu) or a TiW. In some embodiments, the conductive layer14may be formed by electroless plating Ni or Cu.

Referring toFIG. 4C, a photoresist20is formed on the conductive layer14by, for example, coating. One or more openings20rare formed in the photoresist20by, for example, lithographic technique, to expose a portion of the conductive layer14.

Referring toFIG. 4D, a conductive layer is disposed in the openings20rand on the exposed portion of the conductive layer14, forming a conductive pad18ahaving a surface18a1exposed from the openings20r. In some embodiments, the conductive pad18amay be formed by plating Cu, Ag, Ni, Au, or another metal. In some embodiments, the conductive pad18amay be formed by electroless plating Cu, Ni, Pb, or another metal. In some embodiments, the conductive pad18amay be formed by printing Cu, Ag, Au, or another metal.

Referring toFIG. 4E, another photoresist21is formed to cover the conductive pad18aby, for example, coating. The photoresist21fills in the openings20r(illustrated inFIG. 4D).

Referring toFIG. 4F, a part of the photoresist21is removed to expose a portion of the surface18a1of the conductive pad18a, and forming an opening21rin the photoresist21. In some embodiments, the opening21rmay be formed by, for example, lithographic technique. In some embodiments, a width of the opening21ris smaller than a width of the opening20r(illustrated inFIG. 4D).

The surface18a1of the conductive pad18ais partially exposed from the opening21rdefined by the photoresist21. The opening21ris formed to expose the conductive pad18ato be connected to a conductive pillar (such as the conductive pillar19as illustrated inFIG. 4K).

Referring toFIG. 4G, a conductive layer is disposed in the openings21rand on the exposed surface18a1of the conductive pad18a, forming a conductive pad18b.

Referring toFIG. 4H, the photoresists20and21are removed by etching, photoresist stripper or other suitable processes. After the removing operation, the conductive pad18a, the conductive pad18bdisposed on the conductive pad18a, the conductive pad18cspaced apart from the conductive pad18a, and other conductive pads on the electronic components11remain.

Referring toFIG. 4I, the conductive layer14is partially removed or etched by, for example, wet etching. Then a dielectric layer15is disposed to cover the conductive pads18a,18b, and18c. In some embodiments, the dielectric layer15is conformally formed on the conductive pads18a,18b, and18c. For example, the portion of the dielectric layer15disposed on the conductive pad18bis higher than the portion of the dielectric layer15disposed on the conductive pad18c. For example, the dielectric layer15is disposed on lateral surfaces of the conductive pad18band surrounds the conductive pad18b. In some embodiments, the dielectric layer15is formed by, for example, coating, lamination or other suitable processes. In some embodiments, the dielectric layer15is formed by, for example, a spin coater. In some embodiments, the dielectric layer15over the conductive pad18bis formed due to capillary phenomenon.

Referring toFIG. 4J, a portion of the dielectric layer15is removed by a mask22through, for example, lithographic technique. A recessing portion151ais formed on the surface151of the dielectric layer15. The portion151ais recessed from the other portion151b. The portion151amay be relatively rough, and the portion151bmay remain even or unchanged.

In some embodiments, the dielectric layer15may have a surface approximately perpendicular to the surface151after the portion151ais formed.

In some embodiments, after the portion151ais formed, plasma descum (or degunk) operation may be conducted to remove residual dielectric layer15and/or contaminants on the topmost surface18b1of the conductive pad18b.

The dielectric layer15may be a positive photoresist, and portions of the dielectric layer15exposed from the mask22may be removed, forming the recessing portion151a. Due to the inverted trapezoid shape of the conductive pad18b, a part of the dielectric layer15is unexposed and remained on the sidewall of the conductive pad18b.

Although the operation shown inFIG. 4Jillustrates a lithography operation applying positive photoresist, the present disclosure is not limited thereto. In some embodiments, a negative photoresist can be utilized.

Referring toFIG. 4K, another electronic component12is attached to the electronic component11by bonding the conductive pillar19and the electrical contact19ato the conductive pad18b.

Referring toFIG. 4L, an underfill16is formed to surround the conductive pillar19and the conductive pad18b.

In some embodiments, the structure obtained fromFIGS. 4Athru4L can be attached to a substrate (such as the substrate10as shown inFIG. 1) through an electrical contact (such as the electrical contact10bas shown inFIG. 1). An underfill may be provided to surround the electrical contact10b. The resulting structure may be similar to the semiconductor device package1inFIG. 1.

FIG. 5A,FIG. 5B,FIG. 5C, andFIG. 5Dare cross-sectional views of a semiconductor device package at various stages of fabrication, in accordance with some embodiments of the present disclosure. At least some of these figures have been simplified for a better understanding of the aspects of the present disclosure. The operation shown inFIG. 5Amay be conducted subsequent to the operation shown inFIG. 4H.

Referring toFIG. 5A, a dielectric is disposed to cover the conductive pads18a,18b, and18c. In some embodiments, the dielectric layer15may have a substantially planar surface. For example, the dielectric layer15over the conductive pad18bhas substantially the same elevation or level with the dielectric layer15over the conductive pad18c. For example, the dielectric layer15may be disposed as a blanket layer.

Referring toFIG. 5B, a portion of the dielectric layer15is removed through, for example, plasma descum (or degunk) operation. The operation inFIG. 5Bcan be conducted without a mask, which can decrease the manufacturing cost. Although not illustrated in the figures, in some embodiments, the dielectric layer15inFIG. 4I, which is conformally formed, may be partially removed without a mask as illustrated inFIG. 5B.

After the operation shown inFIG. 5B, the topmost surface18b1of the conductive pad18bis exposed from the dielectric layer15.

Referring toFIG. 5C, another electronic component12is attached to the electronic component11by bonding the conductive pillar19and the electrical contact19ato the conductive pad18b.

Referring toFIG. 5D, an underfill16is formed to surround the conductive pillar19and the conductive pad18b.

In some embodiments, the structure obtained fromFIGS. 4Athru4I, and5A thru5D can be attached to a substrate (such as the substrate10as shown inFIG. 3) through an electrical contact (such as the electrical contact10bas shown inFIG. 3). An underfill may be provided to surround the electrical contact10b. The resulting structure may be similar to the semiconductor device package3inFIG. 3.

FIG. 6AandFIG. 6Billustrate examples of different types of semiconductor device packages in accordance with some embodiments of the present disclosure.

As shown inFIG. 6A, a plurality of chips70and/or dies are placed on a square-shaped carrier71. In some embodiments, the chips70may include at least one of the semiconductor device packages1and3as shown inFIGS. 1 and 3. In some embodiments, the carrier71may include organic materials (e.g., a molding compound, bismaleimide triazine (BT), a PI, a polybenzoxazole (PBO), a solder resist, an Ajinomoto build-up film (ABF), a polypropylene (PP), an epoxy-based material, or a combination of two or more thereof) or inorganic materials (e.g., silicon, a glass, a ceramic, a quartz, or a combination of two or more thereof).

As shown inFIG. 6B, a plurality of chips70and/or dies are placed on a circle-shaped carrier72. In some embodiments, the carrier72may include organic materials (e.g., a molding compound, BT, a PI, a PBO, a solder resist, an ABF, a PP, an epoxy-based material, or a combination of two or more thereof) or inorganic materials (e.g., silicon, a glass, a ceramic, a quartz, or a combination of two or more thereof).

As used herein, the terms “approximately”, “substantially”, “substantial” and “about” are used to describe and account for small variations. When used in conduction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints unless specified otherwise. The term “substantially coplanar” can refer to two surfaces within micrometers (μm) of lying along the same plane, such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of lying along the same plane. When referring to numerical values or characteristics as “substantially” the same, the term can refer to the values lying within ±10%, ±5%, ±1%, or ±0.5% of an average of the values.

The foregoing outlines features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure.