Semiconductor device

A semiconductor device including a first electrode on a substrate, a second electrode on the first electrode, a first dielectric layer between the first electrode and the second electrode; a third electrode on the second electrode, a second dielectric layer between the second electrode and the third electrode, and a first contact plug penetrating the third electrode and contacting the first electrode, the first contact plug contacts a top surface of the third electrode and a side surface of the third electrode.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2018-0131069 filed on Oct. 30, 2018 in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present inventive concepts relate to semiconductor devices, and more particularly, to semiconductor devices including a metal-insulator-metal (MIM) capacitor.

Generally, as the integration (e.g., density) of semiconductor devices, such as random access memory (DRAM) devices, increases, the physical area (e.g., size) of a unit cell (e.g., a DRAM memory cell) decreases, and in turn the area occupied by a capacitor of the unit cell also decreases. It would be desirable for a capacitor to maintain a similar capacitance in spite of this reduction in area of the capacitor. Accordingly, structures and/or fabrication methods that increase capacitance would be desirable in order to support greater integration of semiconductor devices.

With respect to metal-insulator-semiconductor capacitors, when the thickness of a dielectric layer is reduced to increase capacitance, leakage current characteristics may deteriorate. Accordingly, it is desirable employ a high-k dielectric layer, or a dielectric layer whose dielectric constant is high. However, when a high-k dielectric layer is used in a metal-insulator-semiconductor capacitor, a low-k dielectric layer is formed between the high-k dielectric layer and a polysilicon layer that serves as a top electrode of the capacitor, with the result that a desired capacitance may not be obtained. Therefore, a metal-insulator-metal (MIM) capacitor has been introduced to replace a metal-insulator-semiconductor capacitor.

SUMMARY

Some example embodiments of the present inventive concepts provide a semiconductor device with improved electrical characteristics.

According to some example embodiments of the present inventive concepts, a semiconductor device may include a first electrode on a substrate; a second electrode on the first electrode; a first dielectric layer between the first electrode and the second electrode; a third electrode on the second electrode; a second dielectric layer between the second electrode and the third electrode; and a first contact plug penetrating the third electrode and contacting the first electrode. The first contact plug may contact a top surface of the third electrode and a side surface of the third electrode.

According to some example embodiments of the present inventive concepts, a semiconductor device may include a first electrode on a substrate, the first electrode having a first penetrating portion; a first dielectric layer on a top surface of the first electrode and in the first penetrating portion; a second electrode on the first dielectric layer, the second electrode having a second penetrating portion that does not overlap the first penetrating portion; a second dielectric layer on a top surface of the second electrode and in the second penetrating portion; a third electrode on the second dielectric layer, the third electrode having a third penetrating portion and a fourth penetrating portion, the third penetrating portion overlapping the second penetrating portion, the fourth penetrating portion overlapping the first penetrating portion; and a first contact plug in the second and third penetrating portions, the first contact plug connecting the first electrode to the third electrode.

According to some example embodiments of the present inventive concepts, a semiconductor device may include a first electrode on a substrate; a second electrode on the first electrode; a third electrode on the second electrode; a dielectric layer between the first electrode, the second electrode and the third electrode; a first contact plug connecting the first electrode to the third electrode; and a second contact plug penetrating a portion of the dielectric layer and contacting the second electrode, wherein a bottom surface of the first contact plug is positioned higher than a bottom surface of the first electrode.

DETAILED DESCRIPTION

FIG. 1illustrates a cross-sectional view showing a semiconductor device according to some example embodiments of the present inventive concepts.FIG. 2Aillustrates an enlarged view showing section A ofFIG. 1in which a surface of a contact plug is coplanar with a top surface of a third electrode.FIG. 2Billustrates an enlarged view showing section A ofFIG. 1in which a surface of a contact plug is at a lower level than a top surface of a third electrode.

Referring toFIG. 1, a first interlayer dielectric layer102may be disposed on a substrate100. The substrate100may be a semiconductor substrate. For example, the substrate100may be a single crystalline silicon wafer and/or a silicon-on-insulator (SOI) substrate. The substrate100may include a first region10and a second region20. For example, the first region10may be a device region, and the second region20may be a contact region. The first interlayer dielectric layer102may be disposed on a top surface of the substrate100. The first interlayer dielectric layer102may include a dielectric material (e.g., a silicon oxide layer and/or a silicon nitride layer). Lower connection lines104may be disposed in the first interlayer dielectric layer102. The lower connection lines104may be buried in (e.g., at least partially embedded within) the first interlayer dielectric layer102. The top surfaces of the lower connection lines104may be coplanar with the top surface of the first interlayer dielectric layer102. The lower connection lines104may include a metallic material (e.g., copper, aluminum, and/or tungsten). A first buffer dielectric layer106may be disposed on the first interlayer dielectric layer102. The first buffer dielectric layer106may cover the top surface of the first interlayer dielectric layer102and the top surfaces of the lower connection lines104. The first buffer dielectric layer106may be, for example, a silicon carbonitride (SiCN) layer. A second interlayer dielectric layer108may be disposed on the first buffer dielectric layer106. The second interlayer dielectric layer108may cover a top surface of the first buffer dielectric layer106. The second interlayer dielectric layer108may include a dielectric material (e.g., a silicon oxide layer and/or a silicon nitride layer).

A first electrode110may be disposed on the second interlayer dielectric layer108. The first electrode110may have a first penetrating portion PE1. The first penetrating portion PE1may be disposed on (e.g., within) the first region10of the substrate100. The first penetrating portion PE1may partially expose a top surface of the second interlayer dielectric layer108. On the second region20of the substrate100, the first electrode110may expose the top surface of the second interlayer dielectric layer108. The first electrode110may include, for example, one or more of TaN, Ta, Al, Ti, TiN, TaSiN, WN, and/or WSiN. A first dielectric layer112may be disposed on the first electrode110. The first dielectric layer112may cover a top surface1and side surfaces of the first electrode110. The first dielectric layer112may lie in the first penetrating portion PE1of the first electrode110and may cover the top surface of the second interlayer dielectric layer108(e.g., in the area in which the top surface of the second interlayer dielectric layer108is exposed by the first penetrating portion PE1). On the second region20of the substrate100, the first dielectric layer112may cover the top surface of the second interlayer dielectric layer108. The first dielectric layer112may have a uniform or near uniform thickness. The first dielectric layer112may include, for example, one or more of Si3N4, Ta2O5, Al2O3, and/or ZrO2.

A second electrode114may be disposed on the first dielectric layer112. The second electrode114may be disposed on the first region10of the substrate100. The second electrode114may expose the first dielectric layer112on the second region20of the substrate100. The second electrode114may have a second penetrating portion PE2. The second penetrating portion PE2may partially expose a top surface of the first dielectric layer112. The first penetrating portion PE1of the first electrode110may be horizontally spaced apart from the second penetrating portion PE2of the second electrode114. For example, the first penetrating portion PE1of the first electrode110may not vertically overlap the second penetrating portion PE2of the second electrode114. As depicted, the vertical direction as discussed herein is normal to the top surface of the substrate100such that the first interlayer dielectric layer102is further in the vertical direction than the substrate100. As discussed herein, the horizontal direction is perpendicular or nearly perpendicular to the vertical direction. The second electrode114may include, for example, one or more of TaN, Ta, Al, Ti, TiN, TaSiN, WN, and/or WSiN.

A second dielectric layer116may be disposed on the second electrode114. The second dielectric layer116may cover top and side surfaces of the second electrode114. The second dielectric layer116may cover the first dielectric layer112on (e.g., within) the second region20of the substrate100. The second dielectric layer116may cover a portion of the top surface of the first dielectric layer112(e.g., in the area in which the portion of the top surface of the first dielectric layer112is exposed by the second penetrating portion PE2of the second electrode114). The second dielectric layer116may have a uniform or near uniform thickness. The second dielectric layer116in the second penetrating portion PE2of the second electrode114may directly contact the portion of the top surface of the first dielectric layer112(e.g., in the area in which the portion of the top surface of the first dielectric layer112is exposed to the second penetrating portion PE2of the second electrode114). In example embodiments, the second electrode114may be surrounded by the first dielectric layer112and the second dielectric layer116. For example, the second dielectric layer116may surround (e.g., cover) the top and side surfaces of the second electrode114. The first dielectric layer112may surround (e.g., be covered by) a bottom surface of the second electrode114. The second dielectric layer116may include, for example, one or more of Si3N4, Ta2O5, Al2O3, and/or ZrO2.

A third electrode118may be disposed on the second dielectric layer116. The third electrode118may be disposed on the first region10of the substrate100. The third electrode118may include a third penetrating portion PE3and a fourth penetrating portion PE4. The third penetrating portion PE3may vertically overlap the second penetrating portion PE2of the second electrode114, and the fourth penetrating portion PE4may vertically overlap the first penetrating portion PE1of the first electrode110. A portion of a top surface of the second dielectric layer116may be exposed to the third penetrating portion PE3. The second dielectric layer116may be disposed between the second electrode114and the third electrode118. The fourth penetrating portion PE4may partially expose top and side surfaces of the second dielectric layer116. The third electrode118may expose the second dielectric layer116on the second region20of the substrate100. The third electrode118may include, for example, one or more of TaN, Ta, Al, Ti, TiN, TaSiN, WN, and/or WSiN.

A second buffer dielectric layer120may be disposed on the third electrode118. The second buffer dielectric layer120may cover top and side surfaces of the third electrode118. The second buffer dielectric layer120may cover the top surface of the second dielectric layer116on the second region20of the substrate100. The second buffer dielectric layer120may cover a portion of the top surface of the second dielectric layer116(e.g., in the area in which the portion of the top surface of the second dielectric layer116is exposed to the third penetrating portion PE3of the third electrode118), and also cover another portion of the top surface of the second dielectric layer116(e.g., in the area in which another portion of the top surface of the second dielectric layer116is exposed to the fourth penetrating portion PE4of the third electrode118). As shown inFIGS. 2A and 2B, the second buffer dielectric layer120may partially expose a top surface2of the third electrode118and also expose a first side surface4of the third electrode118. The top surface2of the third electrode118may be disposed to vertically overlap the second penetrating portion PE2of the second electrode114. The first side surface4the third electrode118may correspond to a sidewall the third penetrating portion PE3of the third electrode118. The second buffer dielectric layer120may include, for example, a silicon nitride layer.

A third interlayer dielectric layer122may be disposed on the second buffer dielectric layer120. The third interlayer dielectric layer122may cover a top surface of the second buffer dielectric layer120. The third interlayer dielectric layer122may include a dielectric layer (e.g., a silicon oxide layer and/or a silicon nitride layer). A third buffer dielectric layer123may be disposed on the third interlayer dielectric layer122. The third buffer dielectric layer123may include, for example, a silicon nitride layer.

Referring together toFIGS. 1, 2A, and 2B, a first contact plug124may be disposed on the first region10of the substrate100. The first contact plug124may penetrate the third buffer dielectric layer123, the third interlayer dielectric layer122, the second buffer dielectric layer120, the second dielectric layer116, and the first dielectric layer112. The first contact plug124may be disposed in the third penetrating portion PE3of the third electrode118and the second penetrating portion PE2of the second electrode114. The first contact plug124may contact the first electrode110and the third electrode118. The first contact plug124may have electrical connection with the first electrode110and the third electrode118. The first contact plug124may contact a portion of the top surface2of the third electrode118and also contact the first side surface4of the third electrode118, (e.g., the portion of the top surface2and the first side surface4that are exposed by the second buffer dielectric layer120). The first side surface4of the third electrode118may vertically overlap the second penetrating portion PE2of the second electrode114. The second buffer dielectric layer120may cover a second side surface of the third electrode118(e.g., the second side surface of the third electrode118that overlaps the second penetrating portion PE2of the second electrode114and faces the first side surface4of the third electrode118). The first contact plug124may contact a portion of the top surface1of the first electrode110. The first contact plug124may have a bottom surface8at a higher level than that of a bottom surface3of the first electrode110. For example, the bottom surface8of the first contact plug124may be disposed between the top and bottom surfaces1and3of the first electrode110.

The first contact plug124may include a first segment PA1and a second segment PA2respectively above and below the top surface2of the third electrode118overlapping the second penetrating portion PE2of the second electrode114. The first segment PA1may include a surface5exposed by the second segment PA2, and the second segment PA2may extend toward the first electrode110from the surface5of the first segment PAL The first segment PA1may have a width W1greater than a width W2of the second segment PA2(W1>W2). The first contact plug124may include a first side surface S1and a second side surface S2. The first side surface S1and the second side surface S2may face each other. In example embodiments, the first side surface S1of the first segment PA1of the first contact plug124may not be aligned (e.g., may vary horizontally) with the first side surface S1of the second segment PA2of the first contact plug124. The surface5of the first segment PA1may connect the first side surface S1of the first segment PA1to the first side surface S1of the second segment PA2. In example embodiments, the second side surface S2of the first segment PA1of the first contact plug124may be aligned with the second side surface S2of the second segment PA2of the first contact plug124. The first contact plug124may have, for example, an L shape. As shown inFIG. 2A, the surface5of the first segment PA1may be coplanar with other portion of the top surface2of the third electrode118, which other portion overlaps the third penetrating portion PE3and is covered with the second buffer dielectric layer120. As shown inFIG. 2B, the surface5of the first segment PA1may be located at a lower level than that of other portion of the top surface2of the third electrode118, which other portion is covered with the second buffer dielectric layer120.

According to some example embodiments of the present inventive concepts, there may be provided a metal-insulator-metal (MIM) capacitor including three electrodes. Accordingly, the capacitor may increase in capacitance.

According to some example embodiments of the present inventive concepts, the first contact plug124may contact two electrodes, for example, the first electrode110and the third electrode118, and may penetrate the third electrode118while contacting the first side surface4and a portion of the top surface2of the third electrode118. In this configuration, an increased contact area may be provided between the first contact plug124and the third electrode118, which may result in a reduction in resistance. In conclusion, the capacitor may have an increased capacitance (e.g., due to the reduction in resistance).

A second contact plug134may be disposed on the first region10of the substrate100. The second contact plug134may penetrate the third buffer dielectric layer123, the third interlayer dielectric layer122, the second buffer dielectric layer120, and the second dielectric layer116, contacting the second electrode114. The second contact plug134may be electrically connected to the second electrode114. The second contact plug134may be disposed in the fourth penetrating portion PE4of the third electrode118. The second contact plug134may recess a top surface7of the second electrode114on the first dielectric layer112(e.g., the top surface7of the second electrode114that overlaps the first penetrating portion PE1of the first electrode110). The first contact plug124and the second contact plug134may include a metallic material (e.g., copper, tungsten, and/or aluminum).

A first upper connection line140and a second upper connection line142may be disposed on the third buffer dielectric layer123. The first upper connection line140may be disposed on the first contact plug124, and the second upper connection line142may be disposed on the second contact plug134. The first upper connection line140may be electrically connected to the first contact plug124, and the second upper connection line142may be electrically connected to the second contact plug134. The first upper connection line140and the second upper connection line142may include a metallic material (e.g., copper, tungsten, and/or aluminum). A through plug146may be disposed on the second region20of the substrate100. The through plug146may penetrate the first buffer dielectric layer106, the second interlayer dielectric layer108, the first dielectric layer112, the second dielectric layer116, the second buffer dielectric layer120, the third interlayer dielectric layer122, and the third buffer dielectric layer123, connecting at least one of the lower connection lines104to the second upper connection line142. The through plug146may include a metallic material (e.g., copper, tungsten, and/or aluminum). In example embodiments, the first contact plug124may be supplied with a first voltage V1, and the second contact plug134may be electrically grounded. The first voltage V1may be applied to the first contact plug124through a third upper connection line (not shown) that is provided on the fourth buffer dielectric layer150and that is connected to the first upper connection line140. The second contact plug134may be electrically grounded to one of the lower connection lines104that is connected through the through plug146to the second upper connection line142.

A fourth interlayer dielectric layer148may be disposed on side surfaces of the first and second upper connection lines140and142. The fourth interlayer dielectric layer148may include a dielectric material (e.g., a silicon oxide layer and/or a silicon nitride layer). A fourth buffer dielectric layer150may be disposed on the fourth interlayer dielectric layer148. The fourth buffer dielectric layer150may cover a top surface of the fourth interlayer dielectric layer148and/or top surfaces of the first and second upper connection lines140and142. The fourth buffer dielectric layer150may include, for example, a silicon nitride layer.

FIG. 3illustrates a cross-sectional view showing a semiconductor device including first and second contact plug structures in the third interlayer dielectric layer, according to some example embodiments of the present inventive concepts. For brevity of description, components similar or the same as those of the semiconductor device discussed above are allocated the same reference numerals thereto, and a detailed explanation thereof will be omitted.

Referring toFIG. 3, a first contact plug structure CPS1may be disposed in the third interlayer dielectric layer122. The first contact plug structure CPS1may include the first contact plug124, in contact with the first electrode110and the third electrode118, and the first upper connection line140on the first contact plug124. In example embodiments, the first contact plug124and the first upper connection line140may be provided as a single body. A second contact plug structure CPS2may be disposed in the third interlayer dielectric layer122. The second contact plug structure CPS2may include the second contact plug134, the second upper connection line142, and the through plug146. The second contact plug134may be disposed on the first region10of the substrate100and may be in contact with the second electrode114. The second upper connection line142may be disposed on the second contact plug134. The through plug146may be disposed on the second region20of the substrate100. The through plug146may connect the second upper connection line142to at least one of the lower connection lines104. In example embodiments, the second contact plug134, the second upper connection line142, and the through plug146may be provided as a single body.

The third buffer dielectric layer123may be disposed on the third interlayer dielectric layer122. The third buffer dielectric layer123may cover a top surface of the first contact plug structure CPS1, a top surface of the second contact plug structure CPS2, and a top surface of the third interlayer dielectric layer122. For example, an example embodiment may include neither the fourth interlayer dielectric layer148nor the fourth buffer dielectric layer150that are shown inFIG. 2.

FIG. 4illustrates a cross-sectional view showing a semiconductor device including a T shaped contact plug, according to some example embodiments of the present inventive concepts.FIG. 5Aillustrates an enlarged view showing section B ofFIG. 4in which a surface of the T shaped contact plug is coplanar with a top surface of a third electrode.FIG. 5Billustrates an enlarged view showing section B ofFIG. 4in which a surface of the T shaped contact plug is at a lower level than a top surface of a third electrode. For brevity of description, components similar or the same as those of the semiconductor device discussed above are allocated the same reference numerals thereto, and a detailed explanation thereof will be omitted.

Referring toFIGS. 4, 5A, and 5B, the first electrode110, the second electrode114, and the third electrode118may extend onto the second region20of the substrate100. In example embodiments, the first and second regions10and20of the substrate100may all be a semiconductor device region. Although not shown, the first upper connection line140may be electrically connected to a third upper connection line (not shown) on the fourth buffer dielectric layer150. The second upper connection line142may be connected to a fourth upper connection line (not shown) on the fourth buffer dielectric layer150, and the fourth upper connection line (not shown) and one of the lower connection lines104may be connected to each other through a through plug (not shown). For example, one of the lower connection lines104may be connected to the second contact plug134though the second upper connection line142, the fourth upper connection line (not shown), and the through plug (not shown).

A first contact plug124′ may include a first segment PA1having a first surface5aand a second surface5b. The first surface5aand the second surface5bmay be parallel or nearly parallel to the top surface of the substrate100. The first surface5aand the second surface5bmay be laterally disposed across (e.g., extend laterally from) a second segment PA2of the first contact plug124′. The second segment PA2of the first contact plug124′ may extend toward the first electrode110from the first and second surfaces5aand5bof the first segment PAL The first surface5aand the second surface5bmay contact the third electrode118exposed by the second buffer dielectric layer120.

A first side surface S1of the first segment PA1of the first contact plug124′ may not be aligned with a first side surface S1of the second segment PA2of the first contact plug124′. The first surface5aof the first segment PA1may connect the first side surface S1of the first segment PA1to the first side surface S1of the second segment PA2. A second side surface S2of the first segment PA1of the first contact plug124′ may not be aligned with a second side surface S2of the second segment PA2of the first contact plug124′. The second surface5bof the first segment PA1may connect the second side surface S2of the first segment PA1to the second side surface S2of the second segment PA2. For example, the first contact plug124′ may have a T shape. The first contact plug124′ may contact first and second side surfaces4aand4bof the third electrode118. The first and second side surfaces4aand4bof the third electrode118may face each other. The first side surface4aand the second side surface4bmay be exposed by the second buffer dielectric layer120. The first side surface4aand the second side surface4bmay vertically overlap the second penetrating portion PE2of the second electrode114.

As shown inFIG. 5A, the first surface5aof the first contact plug124′ may be in contact with a portion of the top surface2of the third electrode118and may be coplanar with another portion of the top surface2of the third electrode118covered with the second buffer dielectric layer120. The second surface5bof the first contact plug124′ may be in contact with a portion of the top surface2of the third electrode118and may be coplanar with the other portion of the top surface2of the third electrode118covered with the second buffer dielectric layer120. As shown inFIG. 5B, the first surface5aof the first contact plug124′ may be in contact with a portion of the top surface2of the third electrode118and may be located at a lower level than that of the other portion of the top surface2of the third electrode118covered with the second buffer dielectric layer120. The second surface5bof the first contact plug124′ may be in contact with a portion of the top surface2of the third electrode118and may be located at a lower level than that of the other portion of the top surface2of the third electrode118covered with the second buffer dielectric layer120.

FIG. 6illustrates a cross-sectional view showing a semiconductor device according to some example embodiments of the present inventive concepts. For brevity of description, components similar or the same as those of the semiconductor device discussed above are allocated the same reference numerals thereto, and a detailed explanation thereof will be omitted.

Referring toFIG. 6, a first contact plug structure CPS1may be disposed in the third interlayer dielectric layer122. The first contact plug structure CPS1may include a first contact plug124′, in contact with the first electrode110and the third electrode118, and the first upper connection line140on the first contact plug124′. In example embodiments, the first contact plug124′ and the first upper connection line140may be provided as a single body. A second contact plug structure CSP2may be disposed in the third interlayer dielectric layer122. The second contact plug CPS2may include a second contact plug134′ and the second upper connection line142. In example embodiments, the second contact plug134′ and the second upper connection line142may be provided as a single body.

FIGS. 7A to 7Gillustrate cross-sectional views showing a method of fabricating a semiconductor device according to some example embodiments of the present inventive concepts.

Referring toFIG. 7A, a first interlayer dielectric layer102may be formed on a substrate100. The substrate100may include a first region10and a second region20. The first interlayer dielectric layer102may be formed on a top surface of the substrate100. Lower connection lines104may be formed in the first interlayer dielectric layer102. The lower connection lines104may be buried in the first interlayer dielectric layer102. The lower connection lines104may have their top surfaces coplanar with that of the first interlayer dielectric layer102.

A first buffer dielectric layer106may be formed on the first interlayer dielectric layer102. The first buffer dielectric layer106may cover the top surface of the first interlayer dielectric layer102and the top surfaces of the lower connection lines104. The first buffer dielectric layer106may include a material having an etch selectivity with respect to the first interlayer dielectric layer102. A second interlayer dielectric layer108may be formed on the first buffer dielectric layer106. The second interlayer dielectric layer108may include a material having an etch selectivity with respect to the first buffer dielectric layer106. A first electrode layer110amay be formed on the second interlayer dielectric layer108. The first electrode layer110amay be formed on the first and second regions10and20of the substrate100. The first electrode layer110amay include, for example, one or more of TaN, Ta, Al, Ti, TiN, TaSiN, WN, and/or WSiN.

Referring toFIG. 7B, the first electrode layer110amay be patterned to form a first electrode110. The formation of the first electrode110may include forming a first mask pattern201on the first electrode layer110aand performing a patterning process in which the first mask pattern201is used as an etching mask to pattern the first electrode layer110a. The patterning process may form a first penetrating portion PE1in the first electrode110. The first penetrating portion PE1may be formed on the first region10of the substrate100. The first penetrating portion PE1may partially expose a top surface of the second interlayer dielectric layer108. Due to the patterning process, the first electrode layer110amay be etched on the portion of the first electrode layer110aformed on the second region20of the substrate100. Thus, the top surface of the second interlayer dielectric layer108may be exposed on the portion of the second interlayer dielectric layer108formed on the second region20of the substrate100. The patterning process may be, for example, a dry etching process. The first mask pattern201may be, for example, a photoresist pattern. After the patterning process, the first mask pattern201may be removed by an ashing process and/or a strip process.

Referring toFIG. 7C, a first dielectric layer112may be formed on the first electrode110. The first dielectric layer112may cover top and side surfaces of the first electrode110, the top surface of the second interlayer dielectric layer108on the second region20of the substrate100, and a portion of the second interlayer dielectric layer108, exposed to (e.g., exposed by) the first penetrating portion PE1of the first electrode110. The first dielectric layer112may be conformally formed on the first electrode110and portions of the second interlayer dielectric layer108. For example, the first dielectric layer112may be formed with respect to the exposed top and side portions of both the first electrode110and the second interlayer dielectric layer108such that the first dielectric layer112covers the exposed top and side portions of both the first electrode110and the second interlayer dielectric layer108. A second electrode layer114amay be formed on the first dielectric layer112. The second electrode layer114amay conformally cover top and side surfaces of the first dielectric layer112. The second electrode layer114amay include, for example, one or more of TaN, Ta, Al, Ti, TiN, TaSiN, WN, and/or WSiN.

Referring toFIG. 7D, the second electrode layer114amay be patterned to form a second electrode114. The formation of the second electrode114may include forming a second mask pattern203on the second electrode layer114aand performing a patterning process in which the second mask pattern203is used as an etching mask to pattern the second electrode layer114a. The patterning process may form a second penetrating portion PE2in the second electrode114. The second penetrating portion PE2may be formed on the first region10of the substrate100. The second penetrating portion PE2may expose a portion of the top surface of the first dielectric layer112. The second penetrating portion PE2of the second electrode114may be horizontally spaced apart from the first penetrating portion PE1of the first electrode110. For example, the second penetrating portion PE2of the second electrode114may be formed not to vertically overlap the first penetrating portion PE1of the first electrode110. The patterning process may remove the second electrode layer114aformed on the second region20of the substrate100, and thus the top surface of the first dielectric layer112may be partially exposed. The pattering process may be, for example, a dry etching process. The second mask pattern203may be, for example, a photoresist pattern. After the patterning process, the second mask pattern203may be removed by an ashing process and/or a strip process.

Referring toFIG. 7E, a second dielectric layer116may be formed on the second electrode114. The second dielectric layer116may cover top and side surfaces of the second electrode114. The second dielectric layer116may cover a portion of the top surface of the first dielectric layer112(e.g., the portion of the top surface of the first dielectric layer112exposed to the second penetrating portion PE2of the second electrode114), and also cover another portion of the top surface of the first dielectric layer112(the portion of the top surface of the first dielectric layer112formed on the second region20of the substrate100). The second dielectric layer116may be conformally formed on the second electrode114and portions of the top surface of the first dielectric layer112. A third electrode layer118amay be formed on the second dielectric layer116. The third electrode layer118amay be conformally formed on the second dielectric layer116. The third electrode layer118amay include, for example, one or more of TaN, Ta, Al, Ti, TiN, TaSiN, WN, and/or WSiN.

A third mask pattern205may be formed on the third electrode layer118a. The third mask pattern205may include a first opening211aand a second opening211b. The first opening211aand the second opening211bmay be disposed on the first region10of the substrate100. The first opening211amay be disposed to vertically overlap the second penetrating portion PE2of the second electrode114, and the second opening211bmay be disposed to vertically overlap the first penetrating portion PE1of the first electrode110. The first and second openings211aand211bmay partially expose a top surface of the third electrode layer118a. The third mask pattern205may partially expose the top surface of the third electrode layer118aformed on the second region20of the substrate100. The third mask pattern205may be, for example, a photoresist pattern.

Referring toFIG. 7F, a patterning process may be performed in which the third mask pattern205is used as an etching mask to pattern the third electrode layer118ato form a third electrode118. The patterning process may form a third penetrating portion PE3and a fourth penetrating portion PE4in the third electrode118. The third and fourth penetrating portions PE3and PE4may expose portions of a top surface of the second dielectric layer116. The third penetrating portion PE3may be formed to vertically overlap the second penetrating portion PE2of the second electrode114, and the fourth penetrating portion PE4may be formed to vertically overlap the first penetrating portion PE1of the first electrode110. The patterning process may at least partially expose the top surface of the second dielectric layer116formed on the second region20of the substrate100. After the patterning process, the third mask pattern205may be removed by an ashing process and/or a strip process.

Referring toFIG. 7G, a second buffer dielectric layer120may be formed on the third electrode118. The second buffer dielectric layer120may conformally cover top and side surfaces of the third electrode118. The second buffer dielectric layer120may conformally cover a portion of the top surface of the second dielectric layer116(e.g., the portion of the top surface of the second dielectric layer116exposed to the third penetrating portion PE3of the third electrode118), and also conformally cover another portion of the top surface of the second dielectric layer116(e.g., the portion of the top surface of the second dielectric layer116exposed to the fourth penetrating portion PE4of the third electrode118. The second buffer dielectric layer120may conformally cover a portion of the top surface of the second dielectric layer116formed on the second region20of the substrate100. The second buffer dielectric layer120may include a material having an etch selectivity with respect to the first, second, and third electrodes110,114, and118. The second buffer dielectric layer120may include, for example, a silicon nitride layer.

A third interlayer dielectric layer122may be formed on the second buffer dielectric layer120. The third interlayer dielectric layer122may cover a top surface of the second buffer dielectric layer120. A third buffer dielectric layer123may be formed on the third interlayer dielectric layer122. The third buffer dielectric layer123may cover a top surface of the third interlayer dielectric layer122. A fourth mask pattern207may be formed on the third buffer dielectric layer123. The fourth mask pattern207may include a first opening213a, a second opening213b, and a third opening213c. The first and second openings213aand213bmay be formed on the first region10of the substrate100, and the third opening213cmay be formed on the second region20of the substrate100. The first opening213amay vertically overlap the second penetrating portion PE2of the second electrode114and the third penetrating portion PE3of the third electrode118, and the second opening213bmay vertically overlap the first penetrating portion PE1of the first electrode110. The third opening213cmay vertically overlap one of the lower connection lines104. The fourth mask pattern207may be, for example, a photoresist pattern.

An etching process may be performed in which the fourth mask pattern207is used as an etching mask to etch the third buffer dielectric layer123, the third interlayer dielectric layer122, the second buffer dielectric layer120, the second dielectric layer116, and the first dielectric layer112. The etching process may form a first through hole H1, a second through hole H2, and a third through hole H3in the third interlayer dielectric layer122. With respect to the third through hole H3, the etching process may also etch the second interlayer dielectric layer108and the first buffer dielectric layer106. The first through hole H1may expose a portion of the top surface of the first electrode110vertically overlapping the second penetrating portion PE2of the second electrode114, and also expose a first side surface4and a portion of the top surface of the third electrode118vertically overlapping the second penetrating portion PE2of the second electrode114. The second through hole H2may expose a portion of the top surface of the second electrode114vertically overlapping the first penetrating portion PE1of the first electrode110. The third through hole H3may partially expose a top surface of one of the lower connection lines104. The etching process may use an etch recipe that may etch the third interlayer dielectric layer122, the second and third buffer dielectric layers120and123, and the first and second dielectric layers112and116, which etch recipe may have an etch selectivity with respect to the first, second, and third electrodes110,114, and118. In some example embodiments, the etching process may use an etch recipe that may also etch the second interlayer dielectric layer108and the first buffer dielectric layer106and have an etch selectivity with respect to the first, second, and third electrodes110,114, and118. Thus, when the first through hole H1is formed until a portion of the top surface of the first electrode110is exposed, the third electrode118may not be etched on its portion exposed to the first through hole H1. In addition, when the third through hole H3is formed until one of the lower connection lines104is exposed on its top surface, no etching may be performed on a portion of the top surface of the first electrode110exposed to the first through hole H1and a portion of the top surface of the second electrode114exposed to the second through hole H2. The etching process may recess a portion of the top surface of the first electrode110, which portion is exposed to the first opening213a, and also recess a portion of the top surface of the second electrode114, which portion is exposed to the second through hole H2. The etching process may be, for example, a dry etching process. In example embodiments, the etching process may recess a portion of the top surface2of the third electrode118, which portion is exposed to the first opening213a.

After the first, second, and third through holes H1, H2, and H3are formed, the fourth mask pattern207may be removed. For example, the fourth mask pattern207may be removed by an ashing process and/or a strip process.

Referring back toFIG. 1, a first contact plug124, a second contact plug134, and a through plug146may be formed. The first contact plug124may be formed in the first through hole H1, the second contact plug134may be formed in the second through hole H2, and the through plug146may be formed in the third through hole H3. The formation of the plugs124,134, and146may include forming a metal layer (not shown) to cover a top surface of the third buffer dielectric layer123and to at least partially fill the first, second, and third contact holes H1, H2, and H3, and then performing a planarization process until the top surface of the third buffer dielectric layer123is exposed.

A fourth interlayer dielectric layer148, a first upper connection line140, and a second upper connection line142may be formed on the third buffer dielectric layer123. The first upper connection line140may be formed on the first contact plug124, and the second upper connection line142may be formed on the second contact plug134and the through plug146. The second upper connection line142may be formed between the second contact plug134and the through plug146. The fourth interlayer dielectric layer148may be formed on the third buffer dielectric layer123and may cover side surfaces of the first and second upper connection lines140and142. A fourth buffer dielectric layer150may be formed on the fourth interlayer dielectric layer148. The fourth buffer dielectric layer150may cover top surfaces of the first and second upper connection lines140and142.

FIG. 8illustrates a cross-sectional view showing a method of fabricating a semiconductor device including first and second contact plug structures in the third interlayer dielectric layer, according to some example embodiments of the present inventive concepts.

Referring toFIG. 8, a first recess structure RS1and a second recess structure RS2may be formed in the third interlayer dielectric layer122. The first recess structure RS1and the second recess structure RS2may be formed on the first region10of the substrate100, and the second recess structure RS2may be formed on the second region20of the substrate100. The first recess structure RS1may penetrate a portion of the second buffer dielectric layer120and also penetrate the first and second dielectric layers112and116. The first recess structure RS1may expose a portion of the top surface of the first electrode110and also expose the first side surface4and a portion of the top surface2of the third electrode118vertically overlapping the second penetrating portion PE2of the second electrode114. The second recess structure RS2may penetrate a portion of the second buffer dielectric layer120and the second dielectric layer116and may expose a portion of the top surface of the second electrode114vertically overlapping the first penetrating portion PE1of the first electrode110.

The first recess structure RS1may include a first hole P1and a first recess R1. The first recess R1may be formed on the first hole P1. The first hole P1may be formed to have a width less than that of the first recess R1. The first hole P1and the first recess R1may be spatially connected to each other. The second recess structure RS2may include a second hole P2, a third hole P3, and a second recess R2. The second recess R2may be formed on the second hole P2and the third hole P3. The second hole P2may be formed on the first region10of the substrate100, the third hole P3may be formed on the second region20of the substrate100, and the second recess R2may be formed on the first and second regions10and20of the substrate100. The second hole P2, the third hole P3, and the second recess R2may be spatially connected to each other. The third hole P3of the second recess structure RS2may also penetrate the second interlayer dielectric layer108and the first buffer dielectric layer106.

In example embodiments, a dual damascene process may be performed to form the first recess structure RS1and the second recess structure RS2. For example, the formation of the first and second recess structures RS1and RS2may include forming a first photoresist pattern (not shown) on the third interlayer dielectric layer122, using the first photoresist pattern as an etching mask to etch the third interlayer dielectric layer122(and the first and second dielectric layers112and116, the second interlayer dielectric layer108and the first buffer dielectric layer106, as discussed above) to form the first, second, and third holes P1, P2, and P3, removing the first photoresist pattern, forming on the third interlayer dielectric layer122a second photoresist pattern (not shown) having an opening width greater than that of the first photoresist pattern, using the second photoresist pattern as an etching mask to etch the third interlayer dielectric layer122to form the first recess R1on the first hole P1and also to form the second recess R2on the second and third holes P2and P3, and then removing the second photoresist pattern.

For another example, the formation of the first and second recess structures RS1and RS2may include forming a first photoresist pattern (not shown) on the third interlayer dielectric layer122, using the first photoresist pattern as an etching mask to etch the third interlayer dielectric layer122to form the first and second recesses R1and R2, removing the first photoresist pattern, forming on the third interlayer dielectric layer122a second photoresist pattern (not shown) having an opening width less than that of the first photoresist pattern, using the second photoresist pattern as an etching mask to etch the third interlayer dielectric layer122, the second buffer dielectric layer120, the second dielectric layer116, and the first dielectric layer112to form the first hole P1below the first recess R1and also to form the second and third holes P2and P3below the second recess R2(including also etching the second interlayer dielectric layer108and the first buffer dielectric layer106to form third hole P3), and then removing the second photoresist pattern.

Referring back toFIG. 3, a first contact plug structure CPS1and a second contact plug structure CPS2may be formed in the third interlayer dielectric layer122. The first contact plug structure CPS1may be formed in the first recess structure RS1, and the second contact plug structure CPS2may be formed in the second recess structure RS2. A third buffer dielectric layer123may be formed on the third interlayer dielectric layer122. The third buffer dielectric layer123may cover a top surface of the first contact plug structure CPS1, a top surface of the second contact plug structure CPS2, and a top surface of the third interlayer dielectric layer122.

According to some example embodiments of the present inventive concepts, there may be provided a metal-insulator-metal (MIM) capacitor including three electrodes. Accordingly, the capacitor may increase in capacitance.

According to some example embodiments of the present inventive concepts, a first contact plug may contact two electrodes, e.g., a first electrode and a third electrode, and may penetrate a third electrode while contacting a side surface and a portion of a top surface of the third electrode. As such, an increased contact area may be provided between the first contact plug and the third electrode, which may result in a reduction in resistance. In conclusion, the capacitor may have an increased capacitance (e.g., due to the reduction in resistance).

Spatially relative terms, such as “below,” “lower,” “above,” “upper,” “higher,” “top,” “side,” “on,” “vertical,” “horizontal,” “lateral,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. For example, as used herein, the terms “upper,” “higher,” “on” and/or “top” may refer to an element or feature further in the vertical direction (as depicted inFIG. 1) with respect to another element or feature, the terms “horizontal,” “lateral,” and/or “side” may refer to an element or feature with respect to a direction perpendicular or nearly perpendicular to the vertical direction, and the terms “lower” and/or “below” may refer to an element or feature further in a direction opposite the vertical direction with respect to another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected, contacted and/or coupled to the other element or intervening elements may be present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.

Although the present invention concepts have been described in connection with some example embodiments of the present inventive concepts illustrated in the accompanying drawings, it will be understood to those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential feature of the present inventive concepts. It will be apparent to those skilled in the art that various substitution, modifications, and changes may be thereto without departing from the scope and spirit of the present inventive concepts.