RF divider using direct digital synthesis

An RF divider directly synthesizes a desired RF as a digital pattern that can be programmed and output at a VCO frequency. An exemplary RF divider comprises a pre-sequencer and a parallel-to-serial converter. The pre-sequencer successively outputs consecutive M-bit sections of a parallel word, where the parallel word comprises one or more copies of a frequency dividing bit pattern defining a frequency divisor. The parallel-to-serial converter performs a parallel-to-serial conversion on the M-bit sections of the parallel word based on the fixed radio frequency to generate an output signal having the desired radio frequency, where the output signal comprises a serial bit stream of the parallel word.

The invention described herein relates generally to frequency dividers, and more particularly to digital frequency dividers having a non-integer divisor.

BACKGROUND

Radio frequency (RF) dividers are used in many communication systems to divide a fixed voltage controlled oscillator (VCO) frequency to a desired frequency. To meet phase noise requirements, however, conventional RF dividers typically require a lot of current, which undesirably increases the power consumption of the device. Further, conventional RF dividers typically only divide by a fixed integer number, which undesirably limits the frequencies available to the communication system.

SUMMARY

The present invention provides an RF divider that avoids many of the problems associated with conventional RF dividers by synthesizing the desired RF directly as a frequency dividing bit pattern that can be programmed and output at a fixed frequency, e.g., the frequency provided by a voltage-controlled oscillator (VCO), to generate a serial bit stream having the desired radio frequency. Because the desired RF signal is generated using direct digital synthesis, many of the phase noise problems associated with conventional RF dividers are avoided and/or may be addressed using low power digital post-processing techniques. Thus, the RF divider described herein may be configured to satisfy phase noise requirements without unduly increasing the power consumption. Further, because each bit in the output serial bit stream corresponds to some portion, e.g., half, of a VCO cycle, the synthesized pattern can realize integer dividers as well as non-integer dividers.

More particularly, the RF divider described herein digitally divides a fixed radio frequency, e.g., as provided by a VCO, by a frequency divisor defined by the frequency dividing bit pattern to provide a desired radio frequency. To that end, an exemplary RF divider comprises a pre-sequencer and a parallel-to-serial converter. The pre-sequencer successively outputs consecutive M-bit sections of a parallel word, where the parallel word comprises one or more copies of the frequency dividing bit pattern. The parallel-to-serial converter completes the digital synthesis of the desired radio frequency by performing a parallel-to-serial conversion on the M-bit sections of the parallel word based on the fixed radio frequency to generate an output signal having the desired radio frequency, where the output signal comprises a serial bit stream having a bit pattern defined by the parallel word. Embodiments disclosed herein include exemplary method and apparatus embodiments.

DETAILED DESCRIPTION

FIG. 1shows an exemplary RF divider100that outputs a serial bit stream having a desired radio frequency based on a fixed radio frequency fvcoprovided by oscillator10and an N-bit parallel word, e.g., provided by processor20. Processor20outputs the N-bit parallel word, which comprises one or more copies of a frequency dividing bit pattern, where the frequency dividing bit pattern defines the frequency divisor used to divide the fixed radio frequency fvcoto achieve the desired radio frequency, as discussed in further detail herein. It will be appreciated that processor20may be programmed to output any parallel word suitable for achieving the desired frequency divisor. The processor20is not required, however, as the desired parallel word may be hard wired to the input of the RF divider100, or provided by a static machine or other circuit.

While it is possible to directly serialize the parallel word at fvcoto generate the desired frequency, such operations are impractical at RF. To overcome this problem, RF divider100includes a pre-sequencer110and a multi-stage multiplexer120, as shown inFIG. 2, that synthesize the desired radio frequency according to the exemplary method200ofFIG. 3. Pre-sequencer110successively applies consecutive M-bit sections of the N-bit parallel word to an input of the multiplexer120(block210), where M≦N. The pre-sequencer110is clocked using a pre-sequencer frequency fpderived in divider12based on fvcoand M to apply a new M-bit section to the multiplexer120every M/(2fvco) clock cycles. As a result, pre-sequencer110is able to operate at a reduced frequency, and therefore, a reduced complexity. Multiplexer120operates as a serializer that performs a parallel-to-serial conversion on each M-bit section to generate an output signal having the desired radio frequency (block220), where the output signal comprises a serial bit stream of the parallel word, and where at least one bit is output every 1/fvcoclock cycles. While the RF divider100disclosed herein provides a 1-bit output for each clock cycle, it will be appreciated that any width could be used to generate the desired output signal. It will further be appreciated that each output bit is available for some predetermined portion of the VCO cycle, e.g., half of fvco. Thus, the oscillator frequency effectively defines the least significant bit of the RF divider100. The following describes exemplary details of the N-bit parallel word, pre-sequencer110, and multi-stage multiplexer120according to various embodiments.

The parallel word input to the RF divider100includes one or more copies of a frequency dividing bit pattern comprising P bits, where the frequency divisor of the RF divider100is derived based on the frequency dividing bit pattern. The frequency dividing bit pattern is a sequence of P bits that, when output at the VCO frequency, divides the VCO frequency by P/2 to achieve the desired radio frequency. In some embodiments P=N, while in other embodiments N is an integer multiple of P. While the frequency dividing bit pattern (FDBP) may be repeated any number of times in the N-bit parallel word, the frequency dividing bit pattern is generally repeated an even number of times in the N-bit parallel word when P is odd. Table 1 shows several exemplary (and non-limiting) parallel words along with the corresponding patterns, values for P, minimum N, and frequency divisor. Inverted and/or rotated patterns generate the same output frequency, but with a different phase relation to the VCO phase.

Pre-sequencer110generates M-bit parallel sections using M≦N consecutive bits from the N-bit parallel word. In general, pre-sequencer110generates the M-bit sections by concatenating M consecutive bits of the N-bit word. When M<N, the pre-sequencer110wraps the concatenated bits from one end of the N-bit word to the beginning of the N-bit to form a group of multiple M-bit sections, where the N-bit word repeats one or more times within the group. For example, pre-sequencer110takes the first M bits of the N-bit parallel word for the first M-bit section. The next M-bit section comprises the remaining N-M bits concatenated with the first M-(N−M) bits of the N-bit parallel word. This repeats some number of times to generate a group of x M-bit sections, where the N-bit word repeats y times in the group, where x=N/z, y=M/z, and z is the greatest common denominator of N and M.

The pre-sequencer110is clocked at a pre-sequencing frequency fp=2fvco/M to sequentially output each M-bit section to multiplexer120every 1/fpcycles. By using a lower frequency to clock the pre-sequencer110instead of the higher fvco, the RF divider100described herein operates with reduced complexity, power consumption, cost, criticality of layout, component quality, etc. The pre-sequencer110sequentially outputs each M-bit section in the group, and follows the last M-bit section in the group with the first M-bit section in the same group to provide the multi-stage multiplexer120with the M-bit sections to enable multiplexer120to output the serial bit stream without interruption.

The following provides some exemplary M-bit sections output by pre-sequencer110and examples of corresponding frequency dividing bit patterns. Each pre-sequencing operation executed by the pre-sequencer110converts the N-bit word to an M-bit section having a width that matches the input-width of the multi-stage multiplexer120. The following examples assume the multi-stage multiplexer120has an input width of 8 bits. It will be appreciated, however, that the present invention is not so limited.

In one exemplary embodiment, pre-sequencer110comprises an 8-to-8 pre-sequencer that provides divisors of 2 and 4. Because this pattern may be implemented as an 8-bit word, it will be appreciated that while pre-sequencer hardware may be used, it is not required for this embodiment. Table 2 shows the M=8 bit section used for the 8-to-8 pre-sequencer.

TABLE 2Group of 8-bit Sections for 8-to-8 Pre-sequencingSection 0p0p1p2p3p4p5p6p7
When the N-bit word is 0011 0011, the divisor is 2 because the frequency dividing bit pattern 0011 has P=4 bits. When the N-bit word is 0000 1111, the divisor is 4 because the frequency dividing bit pattern has P=8 bits.

In another exemplary embodiment, pre-sequencer110comprises a 12-to-8 pre-sequencer that provides divisors of 1.5, 3, and 6. In order to convert the N=12 bit word to an M=8 bit section, the N-bit word is repeated y=2 times within the group, and the group contains x=3 M-bit sections, as shown in Table 3.

TABLE 3Group of 8-bit Sections for 12-to-8 Pre-sequencingSection 0Section 1Section 2p0p8p4p1p9p5p2p10p6p3p11p7p4p0p8p5p1p9p6p2p10p7p3p11
When the N-bit word is 001 001 001 001, the divisor is 1.5 because the frequency dividing bit pattern 001 has P=3 bits. When the N-bit word is 000111 000111, the divisor is 3 because the frequency dividing bit pattern 000111 has P=6 bits. When the N-bit word is 000000111111, the divisor is 6 because the frequency dividing bit pattern 000000111111 has P=12 bits.

In another exemplary embodiment, pre-sequencer110comprises a 10-to-8 pre-sequencer110that provides divisors of 2.5 and 5. In order to convert the N=10 bit word to an M=8 bit section, the N-bit word is repeated y=4 times within the group, and the group contains x=5 M-bit sections, as shown in Table 4.

TABLE 4Group of 8-bit Sections for 10-to-8 Pre-sequencingWord 0Word 1Word 2Word 3Word 4p0p8p6p4p2p1p9p7p5p3p2p0p8p6p4p3p1p9p7p5p4p2p0p8p6p5p3p1p9p7p6p4p2p0p8p7p5p3p1p9
When the pattern is 00111 00111, the divisor is 2.5 because the frequency dividing bit pattern 00111 has P=5 bits. When the pattern is 0000011111, the divisor is 5 because the frequency dividing bit pattern 0000011111 has P=10 bits.

Multi-stage multiplexer120serializes the M-bit sections to generate the output bit signal having the desired frequency. The multiple stages of the multiplexer120enable the serialization of the M-bit sections while using a frequency less than fvcofor most, if not all, stages. By using the appropriate frequency dividing bit pattern and by appropriately interconnecting the pre-sequencer110and multiplexer120, the serial bit stream output by the RF divider100comprises a serial bit stream that repeats the frequency dividing bit pattern to generate an output signal having the desired radio frequency.

FIG. 4depicts one exemplary multi-stage multiplexer120comprising multiple stages122,124,126of 2:1 multiplexing elements128. In general, each stage reduces the number of outputs and increases the frequency. This enables multiplexer120to minimize the number of components operating at high frequencies, e.g., the VCO frequency, while still providing the desired performance. In the example inFIG. 4, each stage halves the number of outputs and doubles the frequency due to the 2:1 structure of the multiplexing elements128. It will be appreciated, however, that other configurations may be used, e.g., 3:1 or 4:1 multiplexing elements, depending on design preferences. In the example ofFIG. 4, multiplexer120is a three-stage multiplexer to accommodate the 8-bit sections output by pre-sequencer110. It will be appreciated, however, that multiplexer120may comprise any number of stages, and that the number of stages is dependent on M.

Each stage122,124,126of multiplexer120is clocked at a frequency defined by dividers123and fvcoto serialize the input bits. To that end, a new M-bit section is input to the first stage122every 4/fvcoclock cycles, and the multiplexing elements128in the first stage122serialize the pairs of input bits from the M-bit section every 4/fvcoclock cycles. The multiplexing elements128in the second stage124serialize the pairs of 2-bit streams output by the first stage122every 2/fvcoclock cycles, and the multiplexing element128in the final stage126serialize the pairs of 4-bit streams output by the second stage124every 1/fvcoclock cycle to generate the output signal. Because the multiplexer input words comprise sections of the parallel word provided to the input of RF divider100, and because the parallel word comprises one or more copies of the frequency dividing bit pattern, the signal output by multiplexer120comprises a serial bit stream of the parallel word, and therefore comprises a serial bit stream of sequential copies of the frequency dividing bit pattern.

Multiplexer120may use any known multiplexing element128, e.g., the multiplexing element128depicted inFIG. 5. In this example, multiplexing element128comprises five latches130and a selector switch132. The first four latches130(serially connected pairs for each of input bits in0and in1) form flip-flops for retiming purposes, and the remaining latch130(for in1) is used to create a half cycle delay relative to the switch input for in0. As a result, each bit output by switch132using the clock as a serial bit clock is only available for half of the clock cycle. For example, in the last stage where clock=fvco, each bit is only available for half of the VCO cycle.

The multi-stage multiplexer120described herein may be followed by an optional retiming stage134. The retiming stage134may be configured to remove spectral impurities introduced by jitter and other imperfections introduced by frequency dividers123and multiplexing elements128. Retiming stage134may also or alternatively be configured to retime the output bit stream to satisfy timing/phase requirements. One exemplary retiming stage134comprises a high-speed flip-flop, where the flip-flop uses the output of the multi-stage multiplexer120as either the clock or the data input.

It will be appreciated that the frequency dividers123and the multiplexing elements128in multiplexer120also add delay that reduces the timing budget of subsequent stages of the RF circuit.FIGS. 6-7depict another exemplary multiplexer embodiment, where the last two stages124,126of the multiplexer120inFIG. 4are replaced with the stages124,126shown inFIGS. 6-7. In particular, the penultimate stage124for this embodiment comprises one multiplexing element128as described above, and a modified multiplexing element128′ that adds delay elements136to offset the outputs of the multiplexing elements128,128′, e.g., by half a clock cycle. The last stage126replaces the multiplexing element128shown inFIG. 4with a logic gate129, e.g., an AND or NAND gate, to multiplex the bits output by the penultimate stage124.FIG. 8depicts one exemplary logic gate129for the embodiment ofFIG. 6, where the logic gate129preferably presents symmetric loading. Logic gate129comprises two NAND gates in parallel, where the inputs for the second NAND are swapped to balance the loading and the delay at the expense of slightly slower transitions. As shown inFIG. 9, combining two inputs offset by half a clock cycle, e.g., in a multiplexing unit128,128′ in the penultimate stage124of the multiplexer120, generates a divide by 2.5 signal. The advantage of this implementation is the fact that none of the multiplexing elements128in the RF divider100, not even those in last stage of the multiplexer120, require the full VCO frequency. It is important to balance loading of the divide by 2 element that generates the four phases (extra latch to generate the delay causes an imbalance).

The embodiment ofFIGS. 6-7does not require modification to the pre-sequencer110. However, the parallel word applied to the pre-sequencer110will need to be slightly different. In particular, the modified parallel word applied to the pre-sequencer110may be generated from the original parallel word with an OR gate for each individual bit (i) in the word. For example, the bits in a section (S) are modified such that Snew[i]=(Sold[i] OR Sold[i+1]), as shown in Table 5, where Snew[i] represents a bit in the new section S to be applied to the pre-sequencer110ofFIGS. 6-7, and Sold[i], Sold[i+1] represent adjacent bits in the old section S that would be applied to the pre-sequencer110for the embodiment ofFIG. 4.

TABLE 5Sold[i]Sold[i + 1]Snew[i]000011101111
Applying M-bit sections of the modified parallel word output by the pre-sequencer110to the multi-stage multiplexer120having the modified penultimate and last stages124,126causes the logic gate129of the last stage126to output a serial bit stream of the unmodified parallel word.

If the divider used to generate the 4-phase clock is too noisy, the retiming unit138may comprise an extra flip-flop that runs directly on the VCO frequency fvco, as shown inFIG. 7, to retime the output signal. In the embodiment ofFIGS. 6-7, the RF/2.5 is based on the assumption that the frequency dividing bit pattern is 5 bits, and M=10. It will be appreciated, however, that this embodiment is feasible for frequency dividing bit patterns having a length greater than or equal to 3.

The above-described embodiments work best when the parallel words input to the pre-sequencer110have a 50% duty cycle. However, as shown in Table 1, some parallel words have an unequal number of 1's and 0's, and therefore, do not have a 50% duty cycle. When the parallel word does not have a 50% duty cycle, the second harmonic content of the serial bit stream output by the RF divider100may be undesirably high. To correct this problem, a chain140of AC-coupled, self-biased inverters142, shown inFIG. 10, may be applied to the output of the multiplexer120. In this case, each inverter stage142removes approximately 10 dB from the second harmonic content. Thus, the number of inverter stages142may be selected based on a desired performance.

The above-described RF dividers100provide several advantages over the prior art, including power efficiency, low phase noise, and programmable phase. For example, CMOS power requirements rise steeply beyond a certain frequency, making it very difficult to realize a function, let alone achieving low power for most radio frequencies used for telecommunications. The RF divider100disclosed herein solves this problem at low frequency by using “low quality” dividers123that do not have strict phase-noise requirements to provide clocking frequencies for the pre-sequencer110and multiplexer120, and by using a power efficient multi-stage multiplexer120. Further, retiming the output signal with the VCO signal effectively removes the phase-noise of the previous stages. In addition, because the frequency dividing bit pattern is fully programmable, the absolute phase can be programmed in half VCO cycles. Shifting the frequency dividing bit pattern can provide a means to select the pattern such that interference with other (VCO-derived) frequencies is minimized. A shift can also be used to maximise the timing margin of a circuit that uses the divider output as a clock or data signal.