Recessed salicide structure to integrate a flash memory device with a high κ, metal gate logic device

An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is arranged over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A flash memory cell device is arranged over the memory region. The flash memory cell device includes a memory cell gate electrically insulated on opposing sides by corresponding dielectric regions. A silicide contact pad is arranged over a top surface of the memory cell gate. The top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate and top surfaces of the dielectric regions. A method of manufacturing the integrated circuit is also provided.

BACKGROUND

The semiconductor manufacturing industry has experienced exponential growth over the last few decades. In the course of semiconductor evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has generally decreased. One advancement has been the development of semiconductor devices, such as transistors, employing metal gates insulated by materials having a high dielectric constant (κ). Such semiconductor devices have improved performance with decreased feature sizes, relative to traditional polysilicon gates insulated by silicon dioxide.

DETAILED DESCRIPTION

A trend in the semiconductor manufacturing industry is to integrate different semiconductor components of a composite semiconductor device into a common semiconductor structure. Such integration advantageously allows lower manufacturing costs, simplified manufacturing procedures, and increased operational speed. One type of composite semiconductor device often integrated into a common semiconductor structure is a flash memory device. A flash memory device includes an array of flash memory cell devices and logic devices supporting operation of the flash memory cell devices. When the array of flash memory cell devices and the logic devices are integrated into a common semiconductor structure, the flash memory device is often referred to as an embedded flash memory device.

Common types of flash memory cell devices include stacked gate flash memory cell devices and split gate flash memory cell devices. Split gate flash memory cell devices have several advantages over stacked gate flash memory cell devices, such as lower power consumption, higher injection efficiency, less susceptibility to short channel effects, and over erase immunity. Examples of split gate flash memory cell devices include silicon-oxide-nitride-oxide-silicon (SONOS) split gate flash memory cell devices, metal-oxide-nitride-oxide-silicon (MONOS) split gate flash memory cell devices, and third generation SUPERFLASH (ESF3) memory cell devices.

Embedded flash memory devices include flash memory cell devices, which are typically formed with polysilicon gates insulated by silicon dioxide, as well as logic devices, such as, for example, address decoders or read/write circuitry. However, as semiconductor feature sizes get smaller and smaller, the logic devices of such embedded flash memory devices are reaching performance limits. High κ metal gate (HKMG) technology has become one of the front runners for the logic devices in the next generation of embedded flash memory devices. HKMG technology employs a metal gate separated from the underlying substrate by a material with a high dielectric constant κ (relative to silicon dioxide). The high κ dielectric reduces leakage current and increases the maximum drain current, and the metal gate mitigates the effects of fermi-level pinning and allows the gate to be employed at lower threshold voltages. Further, the high κ dielectric and the metal gate collectively reduce power consumption.

In forming an embedded flash memory device employing HKMG technology according to some methods, the flash memory cell devices are formed with polysilicon gates. Subsequently, the logic devices are formed with sacrificial gates insulated by a high κ dielectric. With the flash memory cell devices and the logic devices formed, silicide is formed over the source/drain regions of the memory cell devices and logic devices. The silicide advantageously reduces the resistance between the source/drain regions and subsequently formed contacts. Further, an interlayer dielectric covering the logic devices is formed and a first planarization is performed into the interlayer dielectric to the polysilicon gates. Subsequent to the first planarization, the sacrificial gates of the logic devices are replaced with metal gates, while leaving polysilicon gates of the flash memory cell devices. This includes removing the sacrificial gates to form recesses, filling the recesses with a metal layer, and performing a second planarization into the metal layer to form metal gates co-planar with the polysilicon gates. Ideally, the silicide would be formed over the polysilicon gates concurrent with the source/drain regions to reduce contact resistance. However, metal contamination may occur during the first planarization. Further, regardless of the metal contamination, the second planarization removes the silicide over the polysilicon gates during a 28 nanometer (nm) manufacture. Hence, during a 28 nm manufacture, HKMG technology is incompatible with forming silicide over the polysilicon gates before the second planarization according to the foregoing methods.

According to other methods to manufacturing embedded flash devices, silicide is formed over gates of the polysilicon gates of the flash memory cell devices after the second planarization. However, this method introduces bridge concerns between neighboring gates of the memory cell devices. For example, SONOS split gate flash memory cell devices include neighboring select and memory gates separated by a thin charge trapping dielectric. The silicide can form over the charge trapping dielectric and bridge the select and memory gates. Because the silicide is electrically conducting, this bridge, if present, can short the select and memory gates together resulting in a non-functional memory cell.

In view of the foregoing, the present disclosure is directed to an improved method of integrating a flash memory device with a high κ, metal gate logic device, as well as the resulting semiconductor structure. The improved method recesses gates of the flash memory cell devices subsequent to the metal gate planarization, and leaves a thin, dielectric projection extending upward from between the recessed gate regions. Silicide is then formed over top surfaces of the recessed gates, while the logic devices are masked. The resulting semiconductor structure includes silicide formed lower than top surfaces of neighboring dielectrics and metal gates of the logic devices. Because the dielectric projection is arranged between the recessed gate regions and has a height that is greater than that of the formed silicide, the dielectric projection prevents or limits bridging concerns between the recessed gate regions. Thus, the improved method and semiconductor structure advantageously prevent silicide bridging between neighboring gates of the flash memory cell devices by increasing (with the recessing) the distance between the top surfaces. Further, the improved method and semiconductor structure advantageously prevent metal contamination during the first planarization and reduce resistivity between the gates of the flash memory cell devices and subsequently formed contacts.

With reference toFIG. 1A, a cross-sectional view100′ of some embodiments of a semiconductor structure (e.g., representing an integrated circuit) with memory cell devices102a,102band high κ, metal gate logic devices104a-cis provided. The memory cell devices102include a first memory cell device102aand a second memory cell device102b. The memory cell devices102store data in a nonvolatile manner and are, for example, MONOS or SONOS split gate flash memory cell devices. The logic devices104include a first logic device104a, a second logic device104b, and a third logic device104c. The logic devices104coordinate to implement logic supporting operation of the memory cell devices102and are, for example, transistors.

The memory cell devices102and the logic devices104are formed over and/or within a semiconductor substrate106and covered by an interlayer dielectric108. The memory cell devices102are localized to a memory region110of the semiconductor substrate106, and the logic devices104are localized to a logic region112of the semiconductor substrate106that is typically arranged around the periphery of the memory region110. The semiconductor substrate106is, for example, a bulk substrate of silicon, germanium, or group III and group V elements. Alternatively, the semiconductor substrate106is, for example, a semiconductor-on-insulator (SOI) substrate. The interlayer dielectric108is, for example, an oxide, such as silicon dioxide, or a low-K dielectric material.

Embedded within the top surface of the semiconductor substrate106, the semiconductor substrate106includes source/drain regions114a-c. The source/drain regions114are spaced to form channel regions116a,116btherebetween that are individual to the memory cell devices102and the logic devices104. In some embodiments, the source/drain regions114include source/drain regions114bshared by multiple channel regions116a. For example, the memory cell devices102are typically formed in pairs with source/drain regions114aindividual to the memory cell devices102, and source/drain regions114bshared by the memory cell devices102of the pairs.

Over each channel region116in the logic region112, a logic device104includes a metal gate118a,118belectrically isolated from the channel region116by a high κ dielectric120. A high κ dielectric120is a dielectric with a dielectric constant κ greater than the dielectric constant of silicon dioxide (i.e., 3.9). In some embodiments, the top surface of the metal gate118is about 350-700 Angstroms (A) from the top surface of the semiconductor substrate106. A metal gate dielectric122a,122bis arranged between the semiconductor substrate106and the high κ dielectric120. For high voltage applications, the metal gate dielectric122is typically thicker than it would otherwise be. Thus, logic device104acan be a high-voltage transistor with a thick metal gate dielectric122a, while logic devices104band104ccan be low-voltage transistors with thinner metal gate dielectrics122b. Further, an etch stop124is arranged between the metal gate118and the high κ dielectric120. The metal gate118is, for example, tantalum, tantalum nitride, or niobium, the metal gate dielectric122is, for example, an oxide, such as silicon dioxide, the etch stop124is, for example, silicon nitride, and the high κ dielectric120is, for example, hafnium oxide (HfO2), aluminum oxide (AlO3), or tantalum pentoxide (Ta2O5).

Over each channel region116in the memory region110, a memory cell device102includes a select gate126and a memory gate128spaced between the source/drain regions114of the channel region116. In some embodiments, the select gate126is arranged proximate to a source/drain region114bshared with other memory cell devices102, and the memory gate128is arranged proximate to a source/drain region114aindividual to the memory cell device102. The top surfaces of both the select gate126and the memory gate128are recessed relative to top surfaces of the metal gates118by, for example, about 10-500 A or 150-400 A and, in some embodiments, substantially planar. Further, whereas the gates118of the logic devices104are metal, the gates126,128of the memory cell devices102are typically polysilicon. The select gate126has, for example, a generally rectangular profile, and the memory gate128has, for example, a generally asymmetrical, stepped profile. The generally asymmetrical, stepped profile includes a memory gate ledge130exhibiting a reduced height relative to a top surface of the memory gate128and running along a memory gate edge facing away from the select gate126. In some embodiments, the memory gate128has a height of about 100 A between the memory gate ledge130and the bottom surface of the memory gate128.

A memory gate spacer132extends vertically up from the memory gate ledge130, along an upper, inner sidewall of the memory gate128. The memory gate spacer132extends vertically up to above (e.g., 100-300 A above) the top surfaces of the memory and select gate126,128and, in some embodiments, below (e.g., 50-100 A below) top surfaces of the metal gates118. A thin spacer134is arranged to cover a lower, outer sidewall of the memory gate128adjacent to the memory gate spacer132. In some embodiments, the thin spacer134extends vertically up from approximately even with a bottom surface of the memory gate128, along sidewalls of the memory gate128and the memory gate spacer132, to approximately coplanar with the top surfaces of the memory gate spacer132.

Arranged between the semiconductor substrate106and the select gate126, a select gate dielectric136electrically isolates the select gate126from the semiconductor substrate106. Further, arranged between the semiconductor substrate106and the memory gate128, a charge trapping dielectric138electrically isolates the memory gate128from the semiconductor substrate106. The charge trapping dielectric138further extends vertically up to fill the space between the memory gate128and the select gate126and to electrically isolate the memory gate128from the select gate126. The charge trapping dielectric138extends vertically up to above (e.g., 100-300 A above) the top surfaces of the memory and select gates126,128and, in some embodiments, below (e.g., 50-100 A below) top surfaces of the metal gates118. By extending above the top surfaces of the memory and select gates126,128, the charge trapping dielectric138forms a dielectric projection139separating the top surfaces of the memory and select gates126,128. Further, in some embodiments, the charge trapping dielectric138has a thickness of about 100-200 A. The select gate dielectric136is, for example, an oxide, such as silicon dioxide, and the charge trapping dielectric138is, for example, a multilayer dielectric, such as an oxide-nitride-oxide (ONO) dielectric or an oxide-silicon dot-oxide (OSiO) dielectric. In some embodiments, where the charge trapping dielectric138is an OSiO or ONO dielectric, the oxide layer adjacent the sidewall of the select gate126is about 30 A thick, and the other oxide layer is about 80 A.

A source/drain silicide contact pad140a,140bis formed over each source/drain region114, and a memory silicide contact pad141ais formed over each select and memory gate126,128of the memory cell devices102. In some embodiments, the contact pads140,141have a height of about 50-200 A. Source/drain conductive contacts142a,142bindividual to the source/drain regions114, and memory conductive contacts143aindividual to the select and memory gates126,128of the memory cell devices102, extend vertically down through the interlayer dielectric108to corresponding silicide contact pads140,141. The silicide contact pads140,141reduce resistance between the conductive contacts142,143, the source/drain regions114and the select and memory gates126,128of the memory cell devices102by providing a better, lower resistance contact surface for the conductive contacts142,143. The silicide contact pads140,141are, for example, nickel silicide, cobalt silicide, or titanium silicide and, in some embodiments, have substantially planar top surfaces. Logic conductive contacts144individual to the metal gates118of the logic devices104also extend vertically down through the interlayer dielectric108and a dielectric mask146to the metal gates118. The dielectric mask146is typically formed of oxide and masks or covers the logic devices104. In some embodiments, the dielectric mask146has a thickness of about 50-300 A. The conductive contacts142,143,144are, for example, formed of one or more of titanium, titanium nitride, and tungsten.

A main sidewall structure148is arranged on sidewalls of the memory cell devices102and the logic devices104. The main sidewall structure148extends vertically up from the semiconductor substrate106to above (e.g., 100-300 A above) the top surfaces of the memory and select gates126,128and, in some embodiments, below (e.g., 50-100 A below) top surfaces of the metal gates118. For example, for a memory cell device102, the main sidewall structure148extends on a first side of the memory cell device102from the semiconductor substrate106, along sidewalls of the charge trapping dielectric138and the thin spacer134. On the opposing side of the memory cell device102, the main sidewall structure148extends from the semiconductor substrate106, along sidewalls of the select gate dielectric136and the select gate126. As another example, for a logic device104, the main sidewall structure148extends from the semiconductor substrate106, along opposing sidewalls of the metal gate dielectric122, the high κ dielectric120, the etch stop124, and the metal gate118. The main sidewall structure148is, for example, a dielectric, such as silicon nitride.

A contact etch stop150is arranged over the base of the semiconductor substrate106above the silicide contact pads140,141and along sidewalls of the main sidewall structure148. Top surfaces of the contact etch stop150extend to above (e.g., 100-300 A above) the top surfaces of the memory and select gate126,128and, in some embodiments, below (e.g., 50-100 A below) top surfaces of the metal gates118.

By way of recessing the top surfaces of the select and memory gates126,128of the memory cell devices102relative to the top surfaces of the metal gates118, the memory silicide contact pads141formed over the top surfaces of the select and memory gates126,128are also recessed relative to the top surfaces of the metal gates118. Further, by forming one or more of the charge trapping dielectrics138, the thin and memory gate spacers132,134, the main sidewall structure148, and the contact etch stop150to extend to above (e.g., 100-300 A above) the top surfaces of the memory and select gate126,128, the memory silicide contact pads141are also recessed relative to these structures. Advantageously, recessing the memory silicide contact pads141while leaving a dielectric projection139therebetween mitigates the possibility of forming a silicide bridge between the memory and select gates126,128, since the top surfaces of the memory and select gates126,128are spaced farther apart. Further, recessing the memory silicide contact pads141allows compatibility with HKMG technology.

In operation, each memory cell device102stores a variable amount of charge, such as electrons, in the charge trapping dielectric138. The charge is advantageously stored in a non-volatile manner so that the stored charge persists in the absence of power. The amount of charge stored in the charge trapping dielectric138represents a value, such as binary value, and is varied through program (i.e., write), read, and erase operations. These operations are performed through selective biasing of the select gate126and the memory gate128.

During a program or erase operation of a memory cell device102, the memory gate128is forward or reversed biased with a high (e.g., at least an order of magnitude higher) voltage relative a voltage applied across the channel region116and/or relative to a voltage applied to the select gate126. In some embodiments, forward biasing is used for a program operation, and reverse biasing is used for an erase operation. During a program operation, the high bias voltage promotes Fowler-Nordheim tunneling of carriers from the channel region116towards the memory gate128. As the carriers tunnel towards the memory gate128, the carriers become trapped in the charge trapping dielectric138. During an erase operation, the high bias voltage promotes Fowler-Nordheim tunneling of carriers in the charge trapping dielectric138away from the memory gate128. As the carriers tunnel away from the memory gate128, the carriers become dislodged or otherwise removed from the charge trapping dielectric138.

Charge stored in the charge trapping dielectric138of a memory cell device102screens an electric field formed between the memory gate128and the channel region116when the memory gate128is biased. This has an effect of increasing the threshold voltage Vthof the memory cell device102by an amount ΔVth. During a read operation, a voltage is applied to the select gate126to induce part of the channel region116to conduct. Application of a voltage to the select gate126attracts carriers to part of the channel region116adjacent to the select gate126. Further, a voltage greater than Vth, but less than Vth+ΔVth, is applied to the memory gate128. If the memory cell device102turns on (i.e., allows charge to flow), then it stores a first data state (e.g., a logical “0”). If the memory cell device102does not turn on, then it stores a second data state (e.g., a logical “1”).

With reference toFIG. 1B, a cross-sectional view100″ of some embodiments of a semiconductor structure (e.g., representing an integrated circuit) with memory cell devices102a,102band high κ, metal gate logic devices104a-cis provided. In contrast with the embodiments ofFIG. 1A, the memory cell devices102have a different structure. The memory cell devices102store data in a nonvolatile manner and are, for example, ESF3 split gate flash memory cell devices. The logic devices104coordinate to implement logic supporting operation of the memory cell devices102and are, for example, transistors.

Over each channel region116in the memory region110, a memory cell device102includes a floating gate152and a word line154spaced between the source/drain regions114of the channel region116. Arranged between the semiconductor substrate106and the floating gate152, a floating gate dielectric156provides electrical isolation between the semiconductor substrate106and the floating gate152. Further, arranged between the word line154and the semiconductor substrate106, a word line dielectric158provides electrical isolation between the semiconductor substrate106and the word line154. In some embodiments, the floating gate152is recessed on opposing sides proximate to the source/drain regions of the channel region116to define a pair of floating gate ledges160. The floating gate ledges160exhibit a reduced height relative to a top surface of the floating gate152and run along opposing floating gate edges facing the source/drain regions114of the channel region116. In this way, the floating gate152has a symmetrical, stepped appearance when viewed in profile. The top surface of the word line154is recessed relative to top surfaces of the metal gates118by about 10-500 A or 150-400 A. The floating gate152and the word line154are, for example, polysilicon. The floating gate and the word line dielectrics156,158are, for example, oxides, such as silicon dioxide.

The memory cell device102further includes a control gate162and an erase gate164. The erase gate164is arranged over a source/drain region114of the channel region116that is shared with a neighboring memory cell device102and on an opposite side of the floating gate152as the word line154. The top surface of the erase gate164is recessed relative to top surfaces of the metal gates118by, for example, about 10-500 A or 150-400 A and, in some embodiments, substantially planar. The control gate162is arranged over the top surface of the floating gate152with an inter-gate dielectric166arranged between the control gate162and the floating gate152. The inter-gate dielectric166electrically isolates the floating gate152from the control gate162. The top surface of the control gate162is recessed relative to top surfaces of the metal gates118by, for example, about 10-500 A or 150-400 A and, in some embodiments, substantially planar. The control gate162and the erase gate164are, for example, polysilicon. The inter-gate dielectric166is, for example, an ONO dielectric.

Arranged between the control gate162and both the erase gate164and the word line154, a floating gate spacer168provides electrical isolation. The floating gate spacer168extends vertically up from the floating gate ledges160, along sidewalls of the control gate162, to above (e.g., 100-300 A above) the top surfaces of the word line154and the erase gate164and, in some embodiments, below (e.g., 50-100 A below) top surfaces of the metal gates118. Lining a central region between neighboring memory cell devices102, a dielectric liner170insulates the erase gate164from the semiconductor substrate106, the floating gate152, and the control gate162. The dielectric liner170extends vertically up to above (e.g., 100-300 A above) the top surfaces of the word line154and the erase gate164and, in some embodiments, below (e.g., 50-100 A below) top surfaces of the metal gates118. Arranged between the word line154and the floating gate152, a thin sidewall structure172electrically isolates the word line154from the floating gate152. The thin sidewall structure172extends vertically up to above (e.g., 100-300 A above) the top surfaces of the word line154and the erase gate164and, in some embodiments, below (e.g., 50-100 A below) top surfaces of the metal gates118. By extending above the top surfaces of the word line154and the erase and control gates162,164, the floating gate spacer168, the dielectric lining170, and the thin sidewall structure172form dielectric projections139separating the top surfaces of the word line154and the erase and control gates162,164. The dielectric lining170and the thin sidewall structure172are, for example, oxides, such as silicon dioxide, and the floating gate spacer168is, for example, an ONO dielectric.

A source/drain silicide contact pad140a,140bis formed over each source/drain region114, and a memory silicide contact pad141bis formed over each word line154, control gate162, and erase gate164of the memory cell devices102. Source/drain conductive contacts142bindividual to the source/drain regions114, and memory conductive contacts143bindividual to the word lines154and the erase and control gates162,164of the memory cell devices102, extend vertically down through the interlayer dielectric108to corresponding silicide contact pads140,141. The silicide contact pads140,141are, for example, nickel silicide, cobalt silicide, or titanium silicide. The conductive contacts142,143are, for example, formed of one or more of titanium, titanium nitride, and tungsten.

By way of recessing the top surfaces of the word lines154and the erase gates164of the memory cell devices102relative to the top surfaces of the metal gates118, the memory silicide contact pads141formed over the top surfaces of the word lines154and the erase gates164are also recessed relative to the top surfaces of the metal gates118. Further, by forming one or more of the floating gate spacers168, the thin sidewall structures172, the dielectric liners170, the main sidewall structure148, and the contact etch stop150to extend to above (e.g., 100-300 A above) the top surfaces of the word lines154and the erase gates164, the memory silicide contact pads141formed over top surfaces of the word lines154and the erase gates164are also recessed relative to these structures. Advantageously, recessing the memory silicide contact pads141while leaving a dielectric projection139therebetween mitigates the possibility of forming a silicide bridge between the word lines154, the erase gates164and the control gates162, since the top surfaces are spaced farther apart. Further, recessing the memory silicide contact pads141allows compatibility with HKMG technology.

In operation, each memory cell device102stores a variable amount of charge, such as electrons, in the floating gate152. The charge is advantageously stored in a non-volatile manner so that the stored charge persists in the absence of power. The amount of charge stored in the floating gate152represents a value, such as binary value, and is varied through program (i.e., write), read, and erase operations. These operations are performed through selective biasing of the control gate162, the word line154, and the erase gate164.

During a program operation of a memory cell device102, the control gate162is biased with a high (e.g., at least an order of magnitude higher) voltage relative a voltage applied across the channel region116and/or relative to a voltage applied to the word line154. The high bias voltage promotes Fowler-Nordheim tunneling of carriers from the channel region116towards the control gate162. As the carriers tunnel towards the control gate162, the carriers become trapped in the floating gate152.

During an erase operation of a memory cell device102, the erase gate164is biased with a high (e.g., at least an order of magnitude higher) voltage relative a voltage applied across the channel region116and/or relative to a voltage applied to the control gate162. The high bias voltage promotes Fowler-Nordheim tunneling of carriers from the floating gate152towards the erase gate164. As the carriers tunnel towards the erase gate164, the carriers become dislodged or otherwise removed from the floating gate152.

Charge stored in the floating gate152of a memory cell device102screens an electric field formed between the control gate162and the channel region116when the control gate162is biased. This has an effect of increasing the threshold voltage Vthof the memory cell device102by an amount ΔVth. During a read operation, a voltage is applied to the word line154to induce part of the channel region116to conduct. Application of a voltage to the word line154attracts carriers to part of the channel region116adjacent to the word line154. Further, a voltage greater than Vth, but less than Vth+ΔVth, is applied to the control gate162If the memory cell device102turns on (i.e., allows charge to flow), then it stores a first data state (e.g., a logical “0”). If the memory cell device102does not turn on, then it stores a second data state (e.g., a logical “1”).

In view of the foregoing, it should be appreciated that the dielectric projections139ofFIGS. 1A& B mitigate the likelihood of forming a silicide bridge between neighboring gates. The dielectric projections139can be formed of one or more types of dielectric materials and one or more layers of dielectric material. Further, while the foregoing discussion focused on MONOS, SONOS, and ESF3 split gate flash memory cells, other types of memory cells can employ dielectric projections139with memory silicide contact pads141recessed relative to the dielectric projections139to mitigate the concern of silicide bridging between neighboring gates.

With reference toFIG. 2, a flow chart200of some embodiments of a method for manufacturing the semiconductor structure is provided. According to the method, a semiconductor substrate is provided (Action202). A memory cell device including a gate is formed (Action204) on a memory region of the semiconductor substrate. The memory cell device is, for example, a MONOS split gate flash memory cell device or an ESF3 flash memory cell device. For a MONOS split gate flash memory cell, the gate is, for example, the select gate or the memory gate. For an ESF3 flash memory cell, the gate is, for example, an erase gate or a word line. A logic device is formed (Action206) on a logic region of the semiconductor substrate adjacent to the memory region. The logic device includes a sacrificial gate arranged over a high κ dielectric. The sacrificial gate is typically formed of polysilicon. A main sidewall structure abutting opposing sidewalls of the logic device is formed (Action208), and the sacrificial gate of the logic device is removed (Action210) to form a recess between the main sidewall structure. A metal layer filling the recess is formed (Action212), and a planarization into the metal layer is performed (Action214) to form a metal gate with a top surface coplanar with top surfaces of the main sidewall structure and the memory region. A dielectric mask covering the logic region is formed (Action216), while leaving the memory region uncovered. An unmasked top surface of the gate of the memory cell device is recessed (Action218) relative to a top surface of the metal gate, and a silicide layer is formed (Action220) over the unmasked, recessed top surface of the gate of the memory cell device.

Advantageously, forming silicide contact pads on the polysilicon gates of the memory cell device subsequent to forming replacing the sacrificial gates with metal gates allows for compatibility with HKMG technology. Further, recessing the stop surfaces of these gates before forming the silicide contact pads reduces the likelihood of a silicide bridge between neighboring gates because the top surfaces of the neighboring gates are farther apart.

With reference toFIGS. 3A& B, a flow chart300of some embodiments of an expanded method for manufacturing the semiconductor structure is provided. The expanded is described in connection with a SONOS or MONOS split gate flash memory cell devices, but it is to be understood that it is equally applicable to other types of split gate flash memory cell devices, such as the ESF3 memory cell device.

According to the expanded method, a semiconductor substrate is provided (Action302). A pair of memory cell devices are formed (Action304) on a memory region of the semiconductor substrate. Each memory cell device includes a select gate masked by a hard mask and a memory gate. Logic devices are formed (Action306) on a logic region of the semiconductor substrate adjacent to the memory region. The logic devices each include a sacrificial gate arranged over a high κ dielectric. A main sidewall structure is formed (Action308) abutting opposing sidewalls of the memory cell devices and the logic devices. Source and drain regions are embedded (Action310) in the semiconductor substrate. A first silicide layer is formed (Action312) over the source and drain regions to form source/drain contact pads. A first etch is performed (Action314) to remove the hard masks and to etch back a top portion of the main sidewall structure and stop on the select, memory and sacrificial gates. A contact etch stop layer is conformally formed (Action316) along top surfaces of the source/drain contact pads, the main sidewall structure, and the memory cell and logic devices, as well as along sidewalls of the main sidewall structure. A first, interlayer dielectric layer is formed (Action318) over the contact etch stop layer. A first planarization is performed (Action320) into the first, interlayer dielectric layer through the contact etch stop layer to the select gates. A second etch is performed (Action322) into the sacrificial gates to remove the sacrificial gates and to form corresponding recesses between the main sidewall structure. A metal conductive layer is formed (Action324) to fill the recesses. A second planarization is performed (Action326) into the metal conductive layer to form metal gates corresponding to the logic devices and having top surfaces coplanar with top surfaces of the memory and select gates. A second dielectric layer is formed (Action328) over the planar top surfaces of the memory, select, and metal gates. A third etch is performed (Action330) to generate a dielectric mask masking the logic region, while leaving the memory region uncovered. A fourth etch is performed (Action332) to recess top surfaces of the select and memory gates relative to top surfaces of the metal gates. A second silicide layer is formed (Action334) over the recessed top surfaces of the select and memory gates to form memory contact pads. A third, interlayer dielectric layer is formed (Action336) over the semiconductor structure. Contacts extending vertically down through the interlayer dielectrics are formed (Action338) to the contact pads. Contacts extending vertically down through the interlayer dielectrics and the dielectric mask are formed (Action340) to the metal gates

With reference toFIGS. 4-26, cross-sectional views of some embodiments of the semiconductor structure at various stages of manufacture are provided to illustrate the expanded method. AlthoughFIGS. 4-26are described in relation to the expanded method, it will be appreciated that the structures disclosed inFIGS. 4-26are not limited to the expanded method, but instead may stand alone as structures independent of the expanded method. Similarly, although the expanded method is described in relation toFIGS. 4-26, it will be appreciated that the expanded method is not limited to the structures disclosed inFIGS. 4-26, but instead may stand alone independent of the structures disclosed inFIGS. 4-26.

FIG. 4illustrates a cross-sectional view400of some embodiments corresponding to Action302. As shown byFIG. 4, a semiconductor substrate106is provided. The semiconductor structure includes a memory region110and a logic region112typically arranged around the memory region110. The semiconductor substrate106is typically planar with a uniform thickness. Further, the semiconductor substrate106is, for example, a bulk substrate of silicon, germanium, or group III and group V elements. Alternatively, the semiconductor substrate106is, for example, a semiconductor-on-insulator (SOI) substrate.

As shown byFIG. 5, a first dielectric layer502, a first conductive layer504, a second dielectric layer506, and a hard mask layer508are stacked or formed in that order over a top surface of the semiconductor substrate106. Each of the layers502-508typically has a uniform thickness. The first and second dielectric layers502,506are, for example, an oxide, such as silicon dioxide. The first conductive layer504is formed from a silicon based material, such as polysilicon, for a SONOS split gate flash memory cell, and the first conductive layer504is formed from a metal or metal alloy for a MONOS split gate flash memory cell. The hard mask layer is508, for example, a nitride or a multilayer nitride-oxide-nitride (NON) film.

As shown byFIG. 6, a first etch is performed through the hard mask, second dielectric, first conductive, and first dielectric layers502-508to form a pair of spaced select gates126a,126bin the memory region110of the semiconductor substrate106. The select gates126form a central region602between the select gates126and rest upon select gate dielectrics136a,136belectrically isolating the select gates126from the semiconductor substrate106. Further, the select gates126are masked by memory hard masks604a,604belectrically isolated from the select gate126by memory hard mask dielectrics606a,606b.

As shown byFIG. 7, a charge trapping dielectric layer702, a second conductive layer704, and a third dielectric layer706are conformally formed, in that order, over the semiconductor structure. The charge trapping dielectric layer702is conformally formed over top surfaces of the semiconductor substrate106and the memory hard masks604, and along sidewalls of the select gate dielectrics136, the select gates126, the memory hard mask dielectrics606, and the memory hard masks604. The second conductive layer704is conformally formed over the charge trapping dielectric layer702, and the third dielectric layer706is conformally formed over the second conductive layer704. In some embodiments, the second conductive layer704has a thickness of about 100 A and the charge trapping dielectric has a thickness of about 100-200 A. The charge trapping dielectric layer702is, for example, a multilayer charge trapping dielectric, such as an ONO dielectric or an OSiO dielectric. The second conductive layer704is, for example, polysilicon, and the third dielectric layer706is, for example, silicon nitride.

As shown byFIG. 8, a second etch is performed through the second conductive layer704and the third dielectric layer706to form a pair of memory gates128a,128bover and laterally abutting the charge trapping dielectric702, as well as a pair of memory gate spacers132a,132bover and laterally abutting corresponding memory gates128.

As shown byFIG. 9, a third etch is performed partially into the remaining second conductive layer704′ to recess top surfaces of the memory gates128relative to top surfaces of the memory gate spacers132.

As shown byFIG. 10, a pair of thin spacers134a,134bcorresponding to the memory gates128are formed as part of a fourth dielectric layer1002to cover exposed sidewalls of the memory gates128. For example, an intermediate dielectric layer can be conformally deposited and selectively etched to form the fourth dielectric layer1002. Also, of note, portions of the fourth dielectric layer1002mask the top surfaces of the memory gates128. The fourth dielectric layer1002is, for example, silicon nitride.

As shown byFIG. 11, a mask1102is formed and a fourth etch is performed through portions of the remaining second conductive layer704′, the remaining third dielectric layer706′, and the fourth dielectric layer1002in the central region602to remove these portions from the central region602. Typically, the fourth etch is an isotropic dry etch.

As shown byFIG. 12, a fifth etch is performed through the charge trapping dielectric layer702to remove uncovered, horizontal portions of the charge trapping dielectric layer702. This results in charge trapping dielectrics138a,138bindividual to the memory gates128. In some embodiments, the uncovered portions of the charge trapping dielectric layer702include portions covering the memory hard masks604. The fifth etch can, for example, be a fully dry etch, a fully wet etch, or a combination wet and dry etch.

FIG. 13illustrates a cross-sectional view1300of some embodiments corresponding to Action306. As shown byFIG. 13, a trio of sacrificial gates1302a-cis formed over corresponding high κ dielectrics120a-cin the logic region112of the semiconductor substrate106. The sacrificial gates1302are masked by logic hard masks1304a-celectrically isolated from the sacrificial gates1302by logic hard mask dielectrics1306a-c. Further, metal gate dielectrics122a-ccorresponding to the sacrificial gates1302are formed between the semiconductor substrate106and the high κ dielectrics120, and etch stops124a-ccorresponding to the sacrificial gates1302are formed between the sacrificial gate1302and the high κ dielectrics120. For high voltage applications, the metal gate dielectric122is typically thicker than it would otherwise be. The sacrificial gates1302are, for example, polysilicon, the metal gate and logic hard mask dielectrics122,1306are, for example, an oxide, such as silicon dioxide, the etch stops124are, for example, silicon nitride, the high κ dielectrics120are, for example, HfO2, AlO3, or Ta2O5, and the logic hard masks1504are, for example, an oxide, a silicon nitride or a multilayer nitride-oxide-nitride (NON) film. In some embodiments, the logic hard masks1504have a thickness of 50-1100 A.

FIG. 14illustrates a cross-sectional view1400of some embodiments corresponding to Action308. As shown byFIG. 14, a main sidewall structure148is formed along sidewalls of the select gates126in the central region602, and along sidewalls of the charge trapping dielectrics138and the thin spacers134outside the central region602. Further, the main sidewall structure148is formed along opposing sidewalls of the sacrificial gates1302. The main sidewall structure148can be formed by, for example, conformally forming an intermediate dielectric layer and selectively etching the intermediate dielectric layer to form the main sidewall structure148. The main sidewall structure148is, for example, a dielectric, such as silicon nitride.

FIG. 15illustrates a cross-sectional view1500of some embodiments corresponding to Actions310and312. As shown byFIG. 15, source and drain regions114a-iare embedded within the semiconductor substrate106to form channel regions116a-e, and a first silicide layer is formed over the source and drain regions114to form contact pads140a-i. In some embodiments, the first silicide layer has a thickness of about 50-200 A. The first silicide layer is, for example, nickel silicide, cobalt silicide, or titanium silicide.

FIG. 16illustrates a cross-sectional view1600of some embodiments corresponding to Action314. As shown byFIG. 16, a sixth etch is performed to remove the memory and logic hard masks604,1304and the memory and logic hard mask dielectrics606,1306. The sixth etch further stops on the sacrificial gates1302, the select gates126, and the memory gates128, while minimally etching back a top, minor portion of the main sidewall structure148, the memory gate spacers132, the charge trapping dielectrics138, and the thin spacers134.

FIG. 17illustrates a cross-sectional view1700of some embodiments corresponding to Action316and318. As shown byFIG. 17, a contact etch stop layer1702is conformably formed over the semiconductor structure. The contact etch stop layer1702runs along top surfaces of the contact pads140and the memory, select, and sacrificial gates126,128,1302, as well as along sidewalls of the main sidewall structures148. Also shown, a fifth, interlayer dielectric layer1704is formed over the contact etch stop layer1702.

FIG. 18illustrates a cross-sectional view1800of some embodiments corresponding to Action320. As shown byFIG. 18, a first planarization is performed into the fifth, interlayer dielectric layer1704, through the contact etch stop layer1702, and stops on the select gates126. This forms a contact etch stop150. In some embodiments, the first planarization is also into the select gates126, the memory gates128, and the sacrificial gates1302to co-planarize top surfaces of these gates126,128,1302and/or otherwise reduce the height of these gates126,128,1302. The first planarization can, for example, be performed using a chemical machine polish (CMP).

FIG. 19illustrates a cross-sectional view1900of some embodiments corresponding to Action322. As shown byFIG. 19, a second memory hard mask1902is formed over the memory region108and a seventh etch is performed into the sacrificial gates1302to remove the sacrificial gates1302and to form corresponding recesses1904a-cbetween the main sidewall structure148. The second memory hard mask1902is, for example, 30-150 A thick and/or is, for example, formed of oxide, titanium nitride, silicon nitride, or an NON film.

FIG. 20illustrates a cross-sectional view2000of some embodiments corresponding to Action324. As shown byFIG. 20, a third, metal conductive layer2002is formed to fill the recesses1904.

FIG. 21illustrates a cross-sectional view2100of some embodiments corresponding to Action326. As shown byFIG. 21, a second planarization is performed through the second memory hard mask1902and into the metal conductive layer2002to top surfaces of the main sidewall structure148to form metal gates118a-ccorresponding to the recesses1904and having top surfaces coplanar with top surfaces of the memory and select gates126,128. In some embodiments, the second planarization is also into the select and memory gates126,128, and/or otherwise reduces the height of these gates126,128. Further, in some embodiments, the top surfaces of the metal gates118are 350-700 A above the top surface of the semiconductor substrate106. The second planarization can, for example, be performed using a CMP.

FIG. 22illustrates a cross-sectional view2200of some embodiments corresponding to Action328. As shown byFIG. 22, a sixth dielectric layer2202is formed over the planar top surfaces of the memory, select and metal gates118,126,128. The sixth dielectric layer2202typically includes a uniform thickness. In some embodiments, the sixth dielectric layer includes a thickness of about 50-300 A. Further, the sixth dielectric layer2202is, for example, and oxide, such as silicon dioxide.

FIG. 23illustrates a cross-sectional view2300of some embodiments corresponding to Action330. As shown byFIG. 23, a seventh etch is performed through part of the sixth dielectric layer2202to form a dielectric mask146over the logic region112, while leaving the memory region110exposed. In other words, the metal gates118are masked, while leaving the select and memory gates126,128exposed. In some embodiments, the seventh etch further has the effect of recessing top surfaces of the memory region110relative to top surfaces of the logic region112. For example, portions of the main sidewall structure148in the memory region110are recessed. As another example, top surfaces of the charge trapping dielectrics138and the memory gate and thin spacers132,134are recessed. The extent of the recessing is typically about 50-100 A.

FIG. 24illustrates a cross-sectional view2400of some embodiments corresponding to Action332. As shown byFIG. 24, an eighth etch is performed into the select and memory gates126,128to recess top surfaces relative to top surfaces of the metal gates118and relative to top surfaces of the neighboring dielectrics, such as the charge trapping dielectrics138. In some embodiments, the recess depth is 10-500 A or 150-400 A below top surfaces of the metal gates118and/or top surfaces of neighboring dielectrics. The eighth etch is performed by, for example, a dry etch, a wet etch, or a combination of the two. Where the select and memory gates126,128are formed of polysilicon, the dry etch chemistry can include, for example, chlorine gas (Cl2), boron trichloride (BCl3), argon (Ar), or a fluorine gas. Further, where the select and memory gates126,128are formed of polysilicon, the wet etch chemistry can include, for example, an alkali solution. In some embodiments, the eighth etch further recesses silicon dot or nitride layers of the charge trapping dielectrics138.

FIG. 25illustrates a cross-sectional view2500of some embodiments corresponding to Actions334. As shown byFIG. 25, a second silicide layer is formed over the recessed top surfaces of the select and memory gates126,128to form memory contact pads141a,141c-e. In some embodiments, the second silicide layer has a thickness of about 50-200 A. Further, in some embodiments, the top surface of the second silicide layer (i.e., the top surfaces of the memory contact pads141) is recessed about 50-100 A below neighboring dielectrics. The second silicide layer is, for example, nickel silicide, cobalt silicide, or titanium silicide.

FIG. 25illustrates a cross-sectional view2500of some embodiments corresponding to Actions334. As shown byFIG. 25, a second silicide layer is formed over the recessed top surfaces of the select and memory gates126,128to form memory contact pads141a,141c-e. The second silicide layer is, for example, nickel silicide. Advantageously, the risk of forming a silicide bridge between the select and memory gates126,128is greatly reduced by the recessed top surfaces of the select and memory gates126,128because the distance between the top surfaces is increased. Further, because the second silicide layer is formed after the second planarization, the second silicide layer persists and compatibility with HKMG technology is maintained.

FIG. 26illustrates a cross-sectional view2600of some embodiments corresponding to Actions336-340. As shown byFIG. 26, an seventh, interlayer dielectric is formed over the top surface of the semiconductor structure to form an interlayer dielectric108(collectively formed from the remaining fifth dielectric layer1704′ and the seventh dielectric layer). Also formed are source/drain contacts142a-iextending vertically down through the interlayer dielectric108to the source/drain contact pads140, memory contacts143a,143c-eextending vertically down through the interlayer dielectric108to the memory contact pads141, and logic contacts144a-cextending vertically down through the interlayer dielectric108and the dielectric mask146to the metal gates118.

Thus, as can be appreciated from above, the present disclosure provides an integrated circuit for an embedded flash memory device. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is arranged over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A flash memory cell device is arranged over the memory region. The flash memory cell device includes a memory cell gate electrically insulated on opposing sides by corresponding dielectric regions. A silicide contact pad is arranged over a top surface of the memory cell gate. The top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate and top surfaces of the dielectric regions.

In other embodiments, the present disclosure provides a method for manufacturing an embedded flash memory device. A memory cell device is formed over a memory region of a semiconductor substrate. The memory cell device includes a memory cell gate electrically insulated on opposing sides by a pair of dielectric regions. A logic device is formed over a logic region of the semiconductor substrate. The logic device has a sacrificial gate separated from the semiconductor substrate by a material with a dielectric constant exceeding 3.9. The sacrificial gate is replaced with a metal gate. A dielectric mask at least partially covering the logic region is formed, while leaving the memory region uncovered. A top surface of the memory cell gate is recessed relative to a top surface of the metal gate and relative to top surfaces of the dielectric regions. A silicide contact pad is formed over the top surface of the memory cell gate.

In yet other embodiments, the present disclosure provides an integrated circuit for an embedded flash memory device. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. The memory region includes a common source/drain region and a pair of individual source/drain regions arranged on opposite sides of the common source/drain region. A logic device is arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A pair of flash memory cell devices is arranged over the memory region. Each flash memory cell device corresponds to one of the individual source/drain regions and includes a select gate and a memory gate arranged between the common source/drain region and the corresponding individual source/drain region. Each flash memory cell device further includes a charge trapping dielectric arranged between neighboring sidewalls of the memory and select gates, and arranged under the memory gate. Silicide contact pads are respectively arranged over top surfaces of the select and memory gates. Top surfaces of the silicide contact pads are recessed relative to a top surface of the metal gate and top surfaces of the charge trapping dielectrics.