Active quenching for single-photon avalanche diode using one- shot circuit

A sensor circuit having a Single Photon Avalanche Diode (SPAD) and an active quenching circuit including a quenching transistor controlled by a one-shot (or similar) circuit is disclosed. The quenching transistor applies a reverse-bias voltage level on the cathode of the SPAD. During photon detection events, pulses generated by the SPAD's avalanche breakdown trigger the one-shot circuit to de-actuate the quenching transistor, allowing the cathode potential to drop below the SPAD's breakdown voltage. After a delay period, which is defined by the one-shot's configuration, allows reliable completion of the avalanche breakdown process, the one-shot circuit re-actuates the quenching transistor such that the SPAD's cathode is refreshed to the reverse-bias voltage level. The one-shot circuit is optionally coupled by way of capacitors to the SPAD and the quenching transistor to facilitate implementation using standard CMOS elements. The sensor is suitable for use in a LIDAR system.

FIELD OF THE INVENTION

This application relates to sensor circuits that utilize Single-Photon Avalanche Diodes (SPADs), and in particular to quenching circuits that provide rapid recovery of the SPADs after each photon detection event.

BACKGROUND OF THE INVENTION

Single-Photon Avalanche Diodes (SPADs) are solid-state photo detectors (photodiodes) capable of detecting incident photons. Most SPADs are currently fabricated using complementary metal-oxide-semiconductor (CMOS) processing techniques, which greatly facilitates their integration (i.e., on-chip incorporation) into single-photon detectors (SPDs) and other SPAD-based sensor devices that are currently utilized in many technical fields.

SPADs function in a manner similar to other avalanche photodiodes (APDs) in that they exploit the energy of incident radiation to trigger avalanche currents across a p-n junction. A fundamental difference between SPADs and APDs is that SPADs are specifically designed to operate with a reverse-bias voltage that is much greater (more positive) than the SPAD's breakdown voltage (i.e., in the so-called Geiger mode). That is, each SPAD is capable of remaining stable for a finite time after the reverse-bias voltage is applied at its cathode. When an incident photon with sufficient energy to liberate an electron enters a SPAD while the SPAD is in this reverse-biased state, the released photo-generated electron are accelerated by the high energy field in the depletion region of the p-n junction, thereby causing an avalanche breakdown (avalanche multiplication of electrons) event during which the SPAD breaks down (i.e., conducts a current generated by the reverse-bias potential). The avalanche breakdown event continues until the cathode potential falls below the SPAD's breakdown voltage, whereby the initial reverse-bias voltage is entirely discharged through the SPAD. The avalanche event produces a measurable current pulse that is detectable by a suitable detection sensor (e.g., a fast discriminator configured to sense the steep onset of the avalanche breakdown current across a 50Ω resistor, and to provide a digital output pulse synchronous with the incident photon arrival time), whereby incident photon arrival time at the location of the SPAD is registered and passed to downstream control circuitry for subsequent processing. The intensity of a photon signal is obtained by counting (photon counting) the number of output pulses generated by the SPAD within a measurement time slot, while the time-dependent waveform of the signal is obtained by measuring the time distribution of the output pulses (photon timing), which is obtained by operating the SPAD-based sensor (detector) in a Time Correlated Single Photon Counting (TCSPC) mode. Accordingly, the operation of SPADs in the Geiger mode provides an advantage over other APDs in that the current pulse generated during the avalanche breakdown event is generated by the SPAD's internal gain (i.e., by way of discharging the reverse-bias voltage), whereby SPADs are capable of functioning without the need for amplification of their detection (output) signal.

FIG. 7Ashows a simplified example of a conventional “two-terminal” SPAD40based on an early configuration developed for incorporation into CMOS fabrication flows. SPAD40is disposed in a deep N-well42formed in a P-type substrate41that is isolated from other circuit elements (e.g., by shallow-trench isolation (STI) structures). SPAD40has central anode structure formed by a P+ (heavily P-doped) P-SPAD region43disposed over an N-type N-SPAD region44, and an anode structure formed by a ring-shaped N+ (heavily N-doped) cathode contact region45formed over an N-Well region46. Note that both P+ anode region43and N+ cathode contract region45are disposed near an upper surface41U of substrate41, and are accessed by way of metal contact structures47and48, respectively. During operation, with cathode voltage VCATHODEset at a suitable reverse-bias voltage and anode voltage VANODEcoupled to ground, photons striking the diode create charge carriers, causing current to flow between the anode and the cathode, thereby initiating an associated avalanche breakdown event. SPAD40is referred to as a “two-terminal SPAD” because control circuitry can be connected to either the anode (i.e., P-SPAD43) or the cathode (i.e., N+ cathode contract region45)—that is, because both the anode and cathode of SPAD40are isolated from the bulk by way of being contained within deep N-well42, the signals applied to both the anode and the cathode may be varied during operation without affecting neighboring circuit elements. However, this shallow configuration also causes SPAD40to have a relatively shallow depletion region, whereby the peak detection efficiency of two-terminal SPAD40is limited to blue light wavelengths. That is, on average, electromagnetic energy having wavelength is absorbed at different depths in silicon, with blue light (i.e., having a relatively high frequency, high energy, and short wavelength) being absorbed close to the silicon surface (e.g., to a maximum depth D1below surface41U inFIG. 7A), and red/near infra-red (NIR) light (i.e., having a relatively low frequency, low energy, and long wavelength) is absorbed deeper below the silicon surface. In other words, it is more probable that a red photon will be absorbed (generate an electron) deeper below the silicon surface than a blue photon. Accordingly, because the depletion region of two-terminal SPAD40is limited to relatively shallow depth D1, two-terminal SPAD40is only sensitive to relatively short (e.g., blue) light wavelengths, and cannot be used for detecting red and NIR photons.

More recently, SPADs exhibiting improved sensitivity to red and NIR wavelengths have been achieved using general CMOS technology by way of utilizing wells and implants to create relatively deep avalanche breakdown regions.FIG. 7Bshows an exemplary enhanced-NIR-sensitive SPAD50including a central cathode region and a peripheral anode region, both formed in a P-type substrate51. The central cathode region includes N+ cathode contact diffusions52formed over an N-Well (N-SPAD) region53, which in turn is formed over a P-SPAD region54. The ring-shaped anode structure is formed around the central cathode region, and includes P+ cathode contact diffusions55formed in a P-well region56, which in turn is formed over a deep P-well57. Note that the anode of SPAD50is not isolated from the bulk (i.e., both the anode and cathode are formed in P-type substrate51). A benefit of this configuration is that the effective depth of the depletion region extends significantly deeper into substrate51than is possible using the two-terminal SPAD approach described above with reference to FIG.7A, which facilitates enhanced sensitivity to red and NIR photons. However, a downside to this configuration is that it restricts control operations of SPAD50to cathode voltage VCATHODE(i.e., anode voltage VANODEmust be continuously maintained at system ground (0V) in order to prevent negatively affecting the operations of adjacent circuit elements). SPADs of the type shown inFIG. 7Bare characterized herein as single-ended or one-terminal SPADs because they are typically fabricated with their anode terminal disposed in a p-substrate, and thus common to the rest of the system chip (i.e., the anode is necessarily connected to system ground), whereby quenching control of a single-ended SPAD is only possible by way of connection to the SPAD's cathode terminal. Other single-ended SPAD configurations are taught, for example, in U.S. Pat. No. 9,178,100, entitled SINGLE PHOTON AVALANCHE DIODE FOR CMOS CIRCUITS, which is incorporated herein by reference in its entirety. Another enhanced-NIR-sensitive SPAD of this type is disclosed in “Single-Photon Avalanche Diode with Enhanced NIR-Sensitivity for Automotive LIDAR Systems”, I. Takai et al. (Sensors 2016, 16, 459; doi:10.3390/s16040459).

A downside to operating all SPADs in the Geiger mode is that a quenching mechanism (circuit) is required to stop the avalanche breakdown process. That is, as mentioned, each avalanche breakdown process continues until the voltage across the SPAD drops below the SPAD's breakdown voltage (e.g., with the SPAD's anode connected to 0V (ground), the avalanche breakdown process continues until the cathode voltage drops below the SPAD's breakdown voltage). A quenching circuit is coupled to each SPAD and functions to stop the avalanche breakdown process by operably impeding or preventing current flow to the SPAD's such that voltage across the SPAD reliably drops below the SPAD's breakdown voltage during each avalanche breakdown voltage.

FIGS. 8A-8Ddepict the most basic quenching mechanism for a SPAD, which is commonly known as standard passive quenching or passive quenching passive reset (PQPR), and involves utilizing a large resistor R (e.g., 100 kΩ or more) connected in series with a SPAD between a reset voltage VRESETand ground. In the stable reset state indicated inFIG. 8A, a potential VSPADacross the SPAD is at the reset voltage level VRESET(i.e., greater than the SPAD's breakdown voltage), and zero current ISPADflows through the SPAD. As indicated inFIG. 8B, when an incident photon P enters the SPAD and initiates a breakdown event, a positive current ISPADis generated that causes a positive current ISPADto flow through the SPAD, thereby causing potential VSPADacross the SPAD to quickly drop from the reset voltage VRESETtoward the SPAD's breakdown voltage Vbd. The decreasing potential VSPADproduces a voltage drop across resistor R that generates a positive current IR, but resistor R is selected such that current ISPADis much greater than current IRso that potential VSPADis able to drop below the SPAD's breakdown voltage. The decrease of potential VSPADfrom the reset voltage VRESETis also transmitted to a detection sensor or other measurement circuit for downstream processing. As indicated inFIG. 8C, the avalanche event in the SPAD stops when the potential VSPADdrops below the SPAD's breakdown voltage Vbd(i.e., current ISPADdrops to zero) whereby the parasitic resistance of the SPAD starts to recharge by way of current IRpassing through the resistor R. As indicated inFIG. 8D, this recharge process facilitated by current IRcontinues until the potential VSPADis restored to reset voltage VRESET, at which point current IRpassing through the resistor R drops to zero, and the SPAD is reset to detect a subsequently arriving incident photon. A benefit of the passive quenching approach is that it is easily implemented, and facilitates passive (automatic) reset (recharge) of the SPAD (i.e., the reset process occurs automatically after each avalanche breakdown event, as contrasted with a scheduled/clocked reset that occurs whether an avalanche breakdown event has occurred or not.

Although passive quenching is relatively simple to implement and provides automatic reset of the SPAD, it limits SPAD reset (recharge) rates, and is thus not suited for high performance SPAD-based sensors that require rapid SPAD reset rates. Referring toFIGS. 8A-8D, the SPAD reset (recharge) process time period associated with the illustrated passive quenching example is determined by the RC time constant produced by the capacitance of the SPAD and the resistance of resistor R. This RC time constant is usually quite large due mainly to the large resistance of resistor R, which is required to allow potential VSPAD to drop below the SPAD's breakdown voltage Vbdafter each photon detection event. If a smaller resistor were utilized to reduce the SPAD reset process time period, then the SPAD may recharge too fast, which can produce a false (i.e., not triggered by photon) detection event immediately after the legitimate photon detection generated event. This false detection event occurs near the end of an avalanche breakdown event when the potential VSPADdrops below the SPADs breakdown voltage Vbd, but before the SPAD has stabilized, and is caused when the potential VSPADrecovers (rises) to the breakdown voltage level (Vbd) while electrons from the previous avalanche breakdown event are still present in the SPAD. This situation can arise when the resistor used in a passive quenching circuit is too small, and produces an “after-pulse” avalanche breakdown event that generates false detection signals.

A second quenching approach, known as active quenching, involves utilizing active circuitry to reset the bias voltage across a SPAD after a suitable “dead-time” period following each photon detection event, where the dead-time period's duration is set to avoid after-pulse events. One type of active quenching known as active quench active reset (AQAR) involves utilizing active circuitry (e.g., a fast discriminator) to detect the onset of photon-generated avalanche breakdown events, to quickly reduce the bias voltage across the SPAD to below the SPAD's breakdown voltage, and then to reset the bias voltage to above the breakdown voltage after the dead-time period. Another active quenching approach is known as active quenching passive reset (AQPR) utilizes active circuitry to quickly reduce the bias voltage across the SPAD to below the SPAD's breakdown voltage at the onset of a photon detection event, but reset of the bias voltage is performed in a manner similar to that used in the passive quenching approach described above. AQAR circuits often allow shorter dead-time periods, and significantly reduced variations between sequential dead-time periods, in comparison to AQPR circuits.

FIG. 9depicts an exemplary SPAD-based sensor including an exemplary conventional active quenching circuit in which a SPAD's cathode is connected to a high voltage source VHV and the SPAD's anode is coupled to ground by way of an NMOS transistor, which functions as an active quench “resistor” under the control of a quench enable signal. A problem with this configuration is that it requires connection to the SPAD's anode in order to avoid the high SPAD operating voltages. As discussed above, this anode-connection requirement restricts use of this active quenching approach to two-terminals SPADs, which are discussed above with reference toFIG. 7A(i.e., this approach cannot be used with single-ended SPADs, such as those described above with reference toFIG. 7B). This restriction presents a problem in light detection and ranging (LIDAR) systems, which require SPAD-based sensors including enhanced-NIR-sensitive single-ended SPADs. That presents a significant problem because LIDAR systems are finding increasing use in automobile safety systems, where the single-ended SPADs are utilized to detect the presence of pedestrians or cyclists in the host automobile's path, whereby the LIDAR system is able to prompt (warn) the driver or initiate automatic evasive action (e.g., automatically brake the host automobile to avoid collision with the detected pedestrian/cyclist). Because it cannot be utilized with single-ended SPADs, the active quenching approach described with reference toFIG. 8cannot be used in LIDAR systems.

US Pub. App. No. 20140191115A1 entitled “SPAD sensor Circuit with Biasing Circuit” discloses a quenching approach that utilizes a clock-controlled charge pump final stage circuit to periodically generate (refresh) the required reverse-bias voltage across a SPAD. The charge pump final stage circuit utilizes four transistors that are controlled by a clock signal to generate the reverse-bias voltage once during each clock cycle, and two capacitors to store and maintain the reverse-bias voltage on the SPAD. When the SPAD undergoes avalanche breakdown in response to an incident photon, the resulting voltage drop across the SPAD is detected, and then the charge pump final stage circuit subsequently refreshes the reverse-bias voltage. This approach may be utilized with single-ended SPADs, but implements a poorly defined dead-time period that can lead to erroneous detections because the reverse-bias voltage refresh rate is controlled by the clock signal, not the occurrence of photon detection events. That is, because the charge pump final stage circuit resets the reverse-bias voltage across the SPAD in accordance with the clock signal, the effective dead-time period following a given photon detection event and subsequent refresh varies depending on when the given photon detection event occurs during the clock cycle. For example, a relatively long dead-time period occurs when the given photon detection event occurs early in the clock cycle (e.g., right after a refresh event), whereby a relatively long time period passes before the next clock cycle produces a subsequent reverse-bias voltage refresh. Conversely, a relatively short dead-time period occurs when the given photon detection event occurs late in the clock cycle (e.g., right before the subsequent refresh event). The approach taught by US Pub. App. No. 20140191115A1 is therefore problematic because it can produce too-short dead-time periods that may result in undesirable after-pulse events.

What is needed is a quenching circuit for a SPAD-based sensor that combines the automatic-reset functionality of the passive quenching approach with the rapid reset functionality of an active quenching approach, and addresses the problems associated with conventional active quenching circuits mentioned above. What is particularly needed is a simple and reliable AQAR-type active quenching circuit for a SPAD-based sensor that is both configured for use with single-ended SPADs having enhanced NIR sensitivity and exhibits a consistent dead-time period.

SUMMARY OF THE INVENTION

The present invention is directed to an active quenching-recovery circuit for a SPAD-based sensor circuit that utilizes a quenching transistor and a quench control (e.g., one-shot) circuit to actively quench a SPAD for the duration of a delay (dead-time) period following each photon detection event, and to actively reset the SPAD at the end of the delay period for a subsequent photon detection event. The novel active quenching-recovery circuit is configured such that the quenching transistor is coupled between a bias voltage source and the cathode of the SPAD, such that the input terminal of the quench control circuit is coupled to the cathode of the SPAD, and such that the output terminal of the quench control circuit is coupled to a control (gate/base) terminal of the quenching transistor. With this arrangement the quench control circuit is able to actively perform quenching operations by way of receiving/detecting the characteristic pulses (triggering events) generated at the SPAD's cathode terminal that are caused by avalanche breakdown of the SPAD during photon detection events. According to an aspect of the invention, the quench control circuit is operably configured such that, in response to each triggering event, the quench control circuit turns off (de-actuates) the quenching transistor to isolate the SPAD's cathode from the bias voltage source to facilitate the quenching process, and then after a predetermined delay period during which the potential on the SPAD's cathode stabilizes at a (second) voltage that is below the SPAD's breakdown voltage, the quench control circuit turns on (re-actuates) the quenching transistor to re-couple the SPAD to the bias voltage source, whereby the SPAD is reset at the reverse-bias voltage level. The present invention thus provides several advantages over conventional quenching methods. First, the use of the quenching transistor facilitates active reset of the SPAD that is much faster in comparison than that provided by conventional passive quenching techniques, thus improving the time resolution of the SPAD. Second, the use of the quench control circuit to actively control the quenching transistor facilitates reliable generation of a well-controlled, predefined dead-time (delay) period between each trigger event and the reset operation, thereby providing the desired active-quench-active-reset (AQAR) control paradigm in which the SPAD is actively kept below its breakdown voltage (i.e., by de-coupling the SPAD from the bias voltage source) in order to prevent after-pulse events that can occur with conventional active quenching approaches, and then actively reset by way of re-actuating the quenching transistor. Another advantage is the quenching control circuit generates a shaped digital pulse that, by way of controlling the quenching transistor, functions to convert the voltage pulse generated by the SPAD into a digital (rectangle shaped) signal suitable for detection by downstream digital sensor circuitry.

According to a presently preferred embodiment, the quench control circuit of a novel active quenching circuit is implemented using a one-shot (e.g., a mono-stable multi-vibrator) circuit that is capacitively coupled to the SPAD's cathode by way of a first capacitor, and capacitively coupled to the gate terminal of an n-channel field-effect transistor (FET) by way of a second capacitor. An advantage of using a one-shot circuit to control the quench process is that one-shot circuits are simple, well-known circuits, and may be easily configured using known techniques to reliably provide a consistent dead-type period having any required duration without the need for an externally-supplied clock signal. By capacitively coupling the one-shot circuit to the SPAD in the manner described above, the one-shot circuit is isolated from the high voltages required to operate the SPAD such that it can be implemented using standard CMOS transistors that are configured to operate within a selected standard CMOS operating range (e.g., 0V to 3.3V, or 0V to 5V), thereby avoiding the need for generating the one-shot circuit using special high-voltage transistors. Note that the use of standard CMOS transistors is enabled by keeping the range of 0V to the “excess” bias voltage level (i.e., the voltage amount of the reverse-bias voltage that is above the SPAD's breakdown voltage level) within the selected standard CMOS voltage range. This configuration also facilitates forming the quenching transistor using an n-channel CMOS compatible (i.e., 3.3 Volt or 5 Volt) transistor. That is, during operation SPAD-based sensor circuit, voltage drops between the source, drain and gate of the quenching transistor are always within the range of 0V to the excess voltage level, which as set forth above is set below the CMOS system voltage (Vdd, e.g., 3.3 V or 5 V), whereby the only terminal of the quenching transistor that may experience a large voltage drop relative is the bulk node, which does not affect transistor performance or reliability. In a presently preferred embodiment, the quenching transistor is modified from the corresponding standard CMOS transistor of the underlying CMOS technology in a way that forms either a native transistor (e.g., by omitting the P-well used in the standard CMOS transistor), or by including an enhanced P-well in order to avoid breakdown at the source/P-well and drain/P-well junctions.

In an exemplary specific embodiment the one-shot (quench control) circuit is implemented using series-connected inverters that are respectively capacitively coupled to the SPAD's cathode and the control terminal of an n-channel quenching transistor by way of two (first and second) capacitors, whereby the delay period is set at least in part by the propagation time of a signal pulse through the series-connected inverters. To implement this embodiment, the output terminal of the second inverter is coupled to the bias voltage source by way of a first resistor, and the input terminal of the first inverter is coupled to a second voltage supply by way of a second resistor. Beyond the implementation of the basic concept of capacitively coupled one-shot circuit, this approach produces a bootstrapping effect that functions to improve control over the dead-time period duration. That is, the avalanche breakdown is quenched by turning off the quenching transistor (i.e., applying a 0V gate-to-source voltage), the circuit overshoots and pulls the gate forcing the gate-to-source potential below 0V, which ensures quenching of the SPAD during the entire dead-time period. At the end of the dead-time period the proposed circuitry momentarily boosts the gate-to-source potential above the required turn-on voltage, which facilitates higher conduction through the quenching transistor to reset the SPAD in a minimal amount of time.

According to a practical embodiment, a light detection and ranging (LIDAR) system is configured to utilize an enhanced-NIR-SPAD-based sensor circuit to detect NIR light reflected from an object located in the LIDAR system's field of view. An advantage of using the novel sensor circuit of the present invention is that the faster refresh (reset) rate of the novel active quenching circuit (i.e., in comparison to conventional active or passive quenching circuits) provides the LIDAR system with higher resolution, which is believed to enhance accuracy and operating safety.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention relates to an improvement in SPAD-based sensor circuits. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. The terms “coupled” and “connected”, which are utilized herein, are defined as follows. The term “connected” is used to describe a direct connection between two circuit elements, for example, by way of a metal line formed in accordance with normal integrated circuit fabrication techniques. In contrast, the term “coupled” is used to describe either a direct connection or an indirect connection between two circuit elements. For example, two coupled elements may be directly connected by way of a metal line, or indirectly connected by way of an intervening circuit element (e.g., a capacitor, resistor, inductor, or by way of the source/drain terminals of a transistor). Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

FIG. 1shows a SPAD-based sensor circuit100is fabricated on a semiconductor substrate101and includes a SPAD110and an active quenching circuit120including a quenching transistor130and a quench control circuit140. In a preferred embodiment, sensor circuit100is fabricated using CMOS processing techniques.

SPAD110includes a cathode terminal111coupled to a suitable detection sensor (not shown), and an anode112connected to ground (e.g., the substrate bulk or another fixed voltage source). Potential VSPADis utilized herein to identify the reverse voltage level across SPAD110(i.e., the voltage level at cathode111relative to anode112) at a given time during sensor operation. Consistent with conventional SPADs, SPAD110is configured to temporarily maintain/store a potential VSPADon cathode terminal111at a reverse-bias (first) voltage level (i.e., VSPAD=Vbd+Vev) that is a predetermined amount (referred to herein as an “excess” bias voltage Vev) greater than its breakdown voltage Vbdin the absence of a triggering event (e.g., an incident photon), where the breakdown voltage (Vbd) is the minimum reverse voltage level of potential VSPADat which SPAD110conducts in reverse (i.e., in the direction of arrow ISPADshown inFIG. 1). In a preferred embodiment, SPAD110is a single-ended SPAD with enhanced NIR sensitivity, such as that disclosed in U.S. Pat. No. 9,178,100 (cited above), which is configured such that its breakdown voltage Vbdis in the range of 10 V and 60 V, and such that it can temporarily maintain a reverse-bias voltage level (Vbd+Vev) in the range of 1 V and 10 V. In one embodiment, bias voltage source Vbiasis configured to maintain a fixed potential equal to the reverse-bias voltage level (Vbd+Vev) that can be temporarily maintained across SPAD110, as described above.

Quenching transistor130includes a first terminal131connected to a bias voltage source Vbias, a second terminal132connected to cathode111, and a control terminal133coupled to receive an output signal received from quench control circuit140. Control terminal133controls the on/off operating state (i.e., conduction between first terminal131and second terminal132) in accordance with an output signal received from quench control circuit140. In a preferred embodiment, quenching transistor130is implemented by an n-channel MOSFET having a drain (first) terminal131connected to a bias voltage source Vbias, a source (second) terminal132connected to cathode111, and a gate (control) terminal133. The MOSFET is fabricated in accordance with the underlying CMOS technology (e.g., 3.3 V or 5.0 V), but is either implemented as a native transistor (e.g., by omitting the standard P-well utilized in “normal” n-channel MOSFETs of the underlying CMOS technology), or altered using a modified P-well that is configured to avoid breakdown at the source-to-P-well or drain-to-P-well junctions.

Quench control circuit140includes an input terminal141coupled to cathode111of SPAD110and an output terminal142coupled to control terminal133of quenching transistor130, and is configured using known techniques to control the on/off state of quenching transistor130such that SPAD110is de-coupled (electrically isolated) from bias voltage source Vbiasfor a dead-time (delay) period following each photon detection (triggering) event. The configuration of quench control circuit140is described functionally in conjunction with the exemplary operation of sensor circuit100, which is described below with reference toFIGS. 2A to 2E. As set forth below, quench control circuit140is preferably implemented using a one-shot circuit, but those skilled in the art will recognize that the operation performed by quench control circuit140may be implemented using other circuit types as well.

FIGS. 2A to 2Edepict the operation of sensor circuit100(FIG. 1) according to the generalized embodiment. The time-varying sequence of operating states is indicated using parenthetical suffixes t1to t5, where suffix t1(FIG. 2A) indicates an initial operating state of the associated circuitry, suffix t2(FIG. 2B) indicates an associated operating state at a time subsequent to the initial operating state, etc. Note that the time duration between referenced times is not intended to be consistent (e.g., the duration between times t1and t2may be longer or shorter than the duration between times t2and t3).

FIG. 2Adepicts sensor circuit100(t1) at an initial time when SPAD110(t1) is reset (i.e., after potential VSPADis set to reverse-bias voltage level Vbd+Vev, and current ISPADis equal to zero) and before a photo detection event). As indicated by the bubble shown in the lower left portion ofFIG. 2A, an output signal V3generated at output terminal142of quench control circuit140is maintained high at time t1such that quenching transistor130(t1) remains actuated (closed or turned-on), whereby cathode terminal111is maintained at the reverse-bias voltage level by way of being coupled to bias voltage source Vbias.

FIG. 2Bdepicts sensor circuit100(t2) when an incident photon P enters SPAD110(t2) and causes an avalanche breakdown event, thereby producing a positive current ISPADthrough SPAD110(t2) that causes potential VSPADat cathode111to quickly decrease from the reverse-bias voltage level (Vbd+Vev) to a (second) voltage level that is below the SPAD's breakdown voltage Vbd. The resulting rapid change in potential VSPAD(ΔVSPAD) which is approximately equal to excess bias voltage Vev, produces a pulse that is transmitted to input terminal141of quench control circuit140(t1). As indicated by the bubble shown in the lower left portion ofFIG. 2B, quench control circuit140initially (but very briefly) maintains output voltage V3at output terminal142at the high voltage level as the low-going pulse propagates through quench control circuit140, so quenching transistor130(t2) remains turned on.

FIG. 2Cdepicts sensor circuit100(t3) immediately after time t2, after the low-going pulse has propagated through quench control circuit140(t2), and quench control circuit140(t2) has responded by switching output voltage V3at output terminal142to a low voltage level (e.g., 0V), thereby de-actuating (turning off) quenching transistor130, which effectively de-couples SPAD110(t3) from bias voltage source Vbias. As indicated in the bubble at the lower left portion ofFIG. 2C, quench control circuit140is configured to maintain its output terminal142at the low voltage state (e.g., V3=0V) during a dead-time (delay) period following the trigger event, whereby quenching transistor130(t3) will remains de-actuated (open or turned-off) for a period of time that is sufficient to allow potential VSPADto stabilize below breakdown voltage Vbd, whereby the avalanche breakdown event in SPAD110is able to fully terminate (as indicated inFIG. 2Cby current ISPADthrough SPAD110being zero). The duration of the delay (dead-time) is determined by the configuration of SPAD110and other operating conditions of sensor circuit100, and is fixedly set by way of configuring quench control circuit140using techniques such as those described in the specific examples provided below.

FIG. 2Ddepicts sensor circuit100(t4) immediately after the dead-time period has elapsed. Quench control circuit140is further configured re-actuate quenching transistor130such that SPAD110is re-coupled to bias voltage source Vbias. Due to the relatively low voltage on cathode111at the end of the avalanche breakdown process, a quenching current IQflows from bias voltage source Vbiasto cathode111, whereby potential VSPADon cathode111is reset to the desired reverse-bias voltage level Vbd+Vev. As discussed above, SPADs are characterized by their ability to store/maintain reverse-bias voltage levels that are above the SPAD's breakdown voltage, and this characteristic is depicted inFIG. 2Dby the zero current ISPADpassing through SPAD110during the resetting process. As indicated in the bubble at the lower portion ofFIG. 2D, the delay (dead-time) period DP occurs between times t2and t4, where output voltage V3is switched low at the beginning of the delay period and switched high at the end of the delay period.

FIG. 2Edepicts sensor circuit100(t5) immediately after SPAD110(t5) has been reset to the desired reverse-bias voltage level Vbd+Vev. Note that quench control circuit140(t5) maintains output terminal142at the high voltage level (i.e., V3=VHIGH) such that quenching transistor130(t5) remains turned on to couple SPAD110(t5) to bias voltage source Vbiasuntil a subsequent triggering event.

As set forth in the description ofFIGS. 2A to 2E(above), quenching circuit120is operably configured such that, during the delay period following each triggering (photon detection) event (i.e., between times t2and t4, shown inFIG. 2D), quench control circuit140de-actuates (turns off) quenching transistor130to de-couple bias voltage source Vbiasfrom cathode terminal111of SPAD110, thereby allowing SPAD110to complete the associated avalanche breakdown process, and then, after the predetermined dead-time period, re-actuates (turns on) quenching transistor130to restore potential VSPADon cathode111to the desired bias (first) voltage level Vbd+Vev(e.g., as shown inFIG. 2E). An advantage provided by active quenching circuit120is that quenching transistor130facilitates rapid reset/recharging of SPAD110back to the desired reverse-bias voltage level Vbd+Vevmuch faster than is possible using a quenching resistor, thereby improving the time resolution of sensor circuit100over conventional passive quenching approaches. In addition, configuring quench control circuit140to generate a well-controlled predefined dead-time (delay) period (i.e., between time t2(FIG. 2B) and time t4(FIG. 2D)) facilitates reliable prevention of after-pulse events that can occur using conventional approaches.

FIG. 3shows a SPAD-based sensor circuit100A including a quenching circuit120A according to a first specific embodiment of the present invention. Similar to sensor circuit100(FIG. 1), sensor circuit100A includes a SPAD110that is coupled by way of a quenching transistor130to a bias voltage source Vbias, and quenching circuit120A functions to control the on/off state of quenching transistor130in a manner consistent with the approach described above.

Sensor circuit100A differs from sensor circuit100(FIG. 1) in that the quenching circuit is implemented using a one-shot (e.g., monostable multivibrator) circuit140A. One-shot circuits are characterized by utilizing the time constant of an RC coupled circuit to switch from an unstable state to a stable state, thereby producing an output pulse when triggered by an external event. In this case, one-shot circuit140A is configured to generate a high voltage signal on output terminal132when in its stable state, and to generate a low voltage output signal when in its unstable state. One-shot circuit140A is further configured to switch from the stable state to the unstable state in response to the characteristic pulse generated at cathode111when SPAD110undergoes an avalanche breakdown (triggering) event, and to switch back to the stable state after a delay period corresponding to the predetermined dead-time period. An advantage of implementing the quench control circuit using one-shot circuit140A is that one-shot circuits are highly reliable, and are configured using known methods to generate the required dead-time period having any desired duration without the need for an external clock signal.

Sensor circuit100A also differs from sensor circuit100(FIG. 1) in that one-shot circuit140A is capacitively coupled between cathode terminal111of SPAD110and control terminal133of quenching transistor130by way of capacitors150-1and150-2. Specifically, (first) capacitor150-1is connected between cathode111and input terminal141of one-shot circuit140, and (second) capacitor150-2is connected between output terminal142of one-shot circuit140and control terminal133of the quenching transistor130. An advantage provided by capacitively coupling one-shot circuit140to SPAD110and quenching transistor130in this manner is that this arrangement serves to isolate one-shot circuit140from the non-standard (e.g., higher than standard CMOS) voltage levels typically required to operate conventional SPADs, thereby facilitating the fabrication of one-shot circuit140using standard CMOS components and voltage supplies, which both increases reliability, reduces overall circuit size, and reduces power consumption.

FIG. 4shows a SPAD-based sensor circuit100B according to a second specific embodiment. Like the previous examples, sensor circuit100B includes a SPAD110that is coupled by way of a quenching circuit120B to bias voltage source Vbias, with quenching circuit120B including an n-channel field effect transistor (FET) quenching transistor130B that is controlled by a quench control circuit140B.

Referring to the left side ofFIG. 4, quench control (one-shot) circuit140B is implemented in the present embodiment by a pair of series-connected inverters145-1and145-2. An input terminal of (first) inverter145-1is capacitively coupled to cathode terminal111by way of a (first) capacitor150-1, and an output terminal of (second) inverter147-2is capacitively coupled to control terminal133B of n-channel quenching transistor130B by way of a (second) capacitor150-2. Like the previous embodiment, this specific quenching-recovery circuit configuration facilitates fabricating inverters145-1and145-2using standard CMOS transistors that are operated within a selected standard CMOS operating range (i.e., between 0V (ground) and a standard CMOS system voltage VDDsuch as 3.3 V or 5 V)), which avoids the need for generating one-shot circuit140B using special high-voltage transistors. In the depicted specific embodiment, inverter145-1is formed by a standard CMOS n-channel transistor147-11and a standard CMOS p-channel transistor147-12connected in series between ground and system voltage VDDand controlled by voltage V1at input terminal141, and inverter145-2is formed by a standard CMOS n-channel transistor147-21and a standard CMOS p-channel transistor147-22connected in series between ground and system voltage VDDand controlled by voltage V2generated by inverter145-1. Note that the use of standard CMOS transistors147-11to147-22is enabled by configuring bias voltage source Vbiasto generate the reverse-bias voltage level such that excess bias voltage level Vevis within the standard CMOS voltage range (e.g., 0 V to 3.3 V, or 0 V to 5.0 V) of transistors147-11to147-22.

SPAD-based sensor circuit100B utilizes two resistors that further facilitate the use of standard CMOS transistors. That is, quenching circuit120B includes a first pull-up resistor R1that is connected between bias voltage source Vbiasand gate (control terminal)133B of n-channel quenching transistor130B, and one-shot circuit140B includes a second pull-up resistor R2connected between standard CMOS voltage source VDDand an input terminal of (first) inverter145-1. Note that the connection of resistor R2between voltage source VDDand input terminal141of one-shot circuit140B is made possible by way of capacitor150-1, and the length of the delay (dead-time) period is controlled by an RC time constant determined by a resistance of resistor R2and a capacitance of capacitor150-1.

FIGS. 5A to 5Cdepict voltages and on/off states of the elements forming SPAD-based sensor circuit100B during an exemplary triggering event.

FIG. 5Ashows sensor circuit100B(t1) just before the triggering event. As in the previous embodiments, SPAD110coupled to bias voltage source Vbiasby way of quenching transistor130B, whereby potential VSPADis maintained at the desired bias voltage Vbd+Vev. Voltage V1at input terminal141of one-shot circuit140B is maintained at VDDby way of pull-up resistor R2, whereby first inverter145-1generates output voltage V2at 0V, and whereby second inverter145-2generates output voltage V3at VDD, which represents the output signal generated by one-shot circuit140B. However, due to the presence of capacitor150-2and pull-up resistor150-2, voltage V4at gate terminal133B of quenching transistor130B is maintained at bias voltage Vbias. Accordingly, potential VSPADis maintained at the desired bias voltage Vbd+Vevby way of applying bias (first) voltage Vbiasto gate terminal133B of n-channel MOSFET (quenching transistor)130B.

FIG. 5Bdepicts sensor circuit100(t2) when an incident photon P enters SPAD110(t2) and causes an avalanche breakdown event, thereby producing a positive current ISPADthrough SPAD110(t2) that causes potential VSPADat cathode111to quickly decrease from the bias voltage level (Vbd+Vev) to a (second) voltage level that is below the SPAD's breakdown voltage Vbd. The resulting rapid change in potential VSPADwhich is approximately equal to excess voltage Vev, produces a pulse that is transmitted to input terminal141of one-shot circuit140B(t1), whereby voltage V1decreases from VDDto approximately VDD−Vev. The decreased voltage V1causes inverter145-1(t2) to switch output voltage V2from 0V to VDD, which in turn causes inverter145-2(t2) to switch output voltage V3from VDDto 0V. The decreasing pulse generated by output signal V3is transferred by way of capacitor150-2to gate terminal133(t2), whereby voltage V4is pulled down by an amount equal to VDD (i.e., V4=Vbias−VDD). This lower voltage V4keeps gate terminal133B(t2) of n-channel MOSFET130B below its source terminal132B, which is was drawn down to approximately Vbvby the avalanche breakdown process, thereby de-coupling SPAD110(t2) from bias voltage source Vbias. This de-actuation of n-channel MOSFET130B tolls the beginning of an intentional dead-time (delay) period during which SPAD110completes the avalanche breakdown process and potential VSPADstabilizes at a level at or slightly below breakdown voltage Vbd.

FIG. 5Cdepicts sensor circuit100(t3) at the end of the dead-time (delay) period. At this point current IR2through pull-up resistor R2causes voltage V1at input terminal141to recover to voltage VDD, and current IR2through pull-up resistor R1causes voltage V4at gate terminal133B of n-channel MOSFET130B to recover nearly to voltage VDD. At some point inverter145-1(t3) is actuated (switched) in response to the increasing voltage V1such that voltage V2is switched back to 0V, and then inverter145-2(t3) switches its output voltage V3from 0V to VDD. The pulse generated by the positive-going output voltage V3at output terminal141of one-shot circuit140(t3) is transferred through capacitor150-2to gate terminal133B(t3) of n-channel MOSFET130B, whereby voltage V4is rapidly increased by approximately VDD, thereby re-actuating (turning on) n-channel MOSFET130B such that SPAD110(t3) is re-coupled to bias voltage source Vbias. The re-actuation of n-channel MOSFET130B facilitates a fast recovery of potential VSPADback to the desired bias voltage level (i.e., Vbv+Vev). Configuring sensor circuit100B such that standard CMOS voltage VDDis greater than excess voltage level Vevprovides enhanced performance by way of providing a more reliable “off” state during the delay period (right after each triggering event) when gate voltage V4minus potential VSPADequals excess voltage Vevminus standard CMOS voltage VDD, and also provides a boost during the recovery process depicted inFIG. 5Cas well.

FIG. 6is a simplified block diagram depicting a practical embodiment of the present invention in which any of the SPAD-based sensor circuits described above are incorporated into a light detection and ranging (LIDAR) system200. LIDAR system200generally includes a light source210, a mirror215, a light scanning system220, SPAD-based sensor circuit100, and a control circuit250. Light source110may be, for example, a laser that emits light having an operating wavelength in the infrared, visible, or ultraviolet portions of the electromagnetic spectrum, and preferably in the NIR spectrum (e.g., 850 nm). Light source110emits this NIR light as an output beam225that may be continuous-wave, pulsed, or modulated in any suitable manner for a given application. Output beam225is directed by way of light scanning system220into a light source field of view (e.g., toward a remote target230located a distance in the range of approximately 1 m to 1 km from LIDAR system200). An input beam235is generated by portions of output beam225that are reflected or scattered from remote object230(or another structure in the light source field of view) back toward system200. Input beam235is directed by way of light scanning system220and/or mirror215toward SPAD-based sensor circuit100, which functions to detect photons forming input beam235in the manner set forth above. Control circuit250receives photon detection data from sensor100by way of a bus255and utilizes the photon detection data to implement one or more control procedures (e.g., in the case where LIDAR system200is utilized on an automobile, actuating an automatic braking system to prevent collision with object230). One benefit of sensor circuit100in this practical embodiment is that the faster refresh (reset) rate achieved the novel active quenching circuit (i.e., in comparison to conventional active or passive quenching circuits) provides the LIDAR system with substantially more detection data, which is believed to enhance accuracy and operating safety of LIDAR system200over conventional LIDAR systems. Specifically, the short and well-defined dead-time provided by the one-shot-based quenching recovery configuration improves the performance of LIDAR system200in two ways: first, it prevents “after-pulse” avalanche breakdown events that generate false detection signals; and second, it resets the SPAD for detection of a subsequent photon in a shorter amount of time. These improved performance characteristics provide higher resolution (i.e., greater ability to detect objects and avoid “blind spots” in the LIDAR system's field of view), which is believed to enhance the accuracy and operating safety of LIDAR system200.

Although the present invention has been described with respect to certain specific embodiments, it will be clear to those skilled in the art that the inventive features of the present invention are applicable to other embodiments as well, all of which are intended to fall within the scope of the present invention. For example, although the invention is described with particular reference to CMOS-based sensor circuits, the sensor circuits of the present invention may be implemented using other semiconductor fabrication technologies (e.g., silicon-on-insulator or BiCMOS). Moreover, the methodology implemented by the exemplary one-shot-based quenching circuits described herein may be implemented by other (i.e., non-one-shot) quench control circuit types, and therefore the appended claims are not restricted to one-shot circuits unless otherwise specified.