Switch circuit, filter circuit and test apparatus

There is provided a switch circuit for switching whether to output an input signal, including: a transmission path that transmits the input signal from an input end to an output end of the switch circuit; a first semiconductor switch that is provided on the transmission path and switches whether to transmit the input signal; a second semiconductor switch that is opened when the first semiconductor switch is short-circuited, and that is short-circuited when the first semiconductor switch is opened, thereby grounding, to a ground potential, a high-frequency signal leaked to the transmission path between the first semiconductor switch and the output end; and a voltage controller that causes a potential difference on both ends of the second semiconductor switch when the second semiconductor switch is opened.

CROSS REFERENCE TO RELATED APPLICATION

This is a continuation application of PCT/JP2007/058983 filed on Apr. 25, 2007 which claims priority from a Japanese Patent Application(s) No. 2006-131812 filed on May 10, 2006, the contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

The present invention relates to a switch circuit, a filter circuit, and a test apparatus. In particular, the present invention relates to a switch circuit for switching whether to output an input signal, and to a filter circuit and a test apparatus including the switch circuit.

2. Related Art

A T switch circuit and an L switch circuit, which use a semiconductor switch, are known to be fast and have a favorable insulation property when opened. The T switch circuit and the L switch circuit include a first semiconductor switch for switching short-circuit/opening of an input end and an output end, and a second semiconductor switch for switching short-circuit/opening of a transmission path and a ground potential, where the transmission path is of the input end and the output end.

In the T switch circuit and the L switch circuit, the second semiconductor switch is opened when the first semiconductor switch is short-circuited, and is short-circuited when the first semiconductor switch is opened. Consequently, when the first semiconductor switch is opened, the second semiconductor switch can ground, to a ground potential, a high-frequency signal inputted via a parasitic capacitance of the first semiconductor switch. Accordingly, the T switch circuit and the L switch circuit do not output a leakage signal inputted from either the input end or the output end from the other end, thereby leading to improvement in insulation property at the time of opening.

So far, no related patent document is recognized, and so the description thereof is omitted.

A semiconductor switch has a capacitance between output terminals. Therefore, while the first semiconductor switch is short-circuited, a T switch or an L switch has deformed a signal passing between the input end and the output end due to the capacitance between output terminals that depends on the voltage between terminals in the second semiconductor switch.

SUMMARY

Therefore, it is an object of an aspect of the innovations herein to provide a switch circuit, a filter circuit, and a test apparatus, which are capable of overcoming the above drawbacks accompanying the related art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the innovations herein.

According to the first aspect related to the innovations herein, provided is one exemplary switch circuit for switching whether to output an input signal, including: a transmission path that transmits the input signal from an input end to an output end of the switch circuit; a first semiconductor switch that is provided on the transmission path and switches whether to transmit the input signal; a second semiconductor switch that is opened when the first semiconductor switch is short-circuited, and that is short-circuited when the first semiconductor switch is opened, thereby grounding, to a ground potential, a high-frequency signal leaked to the transmission path between the first semiconductor switch and the output end; and a voltage controller that causes a potential difference on both ends of the second semiconductor switch when the second semiconductor switch is opened.

According to the second aspect related to the innovations herein, provided is one exemplary filter circuit for allowing a predetermined frequency component of an input signal to pass through, including: a first filter and a second filter that have different frequency characteristics from each other that determine which frequency component of the input signal is allowed to pass therethrough; a first switch circuit that switches whether to input the input signal to the first filter; and a second switch circuit that switches whether to input the input signal to the second filter, where the first switch circuit and the second switch circuit include: a transmission path that transmits the input signal from an input end to an output end of the switch circuit; a first semiconductor switch that is provided on the transmission path and switches whether to transmit the input signal; a second semiconductor switch that is opened when the first semiconductor switch is short-circuited, and that is short-circuited when the first semiconductor switch is opened, thereby grounding, to a ground potential, a high-frequency signal leaked to the transmission path between the first semiconductor switch and the output end; and a voltage controller that causes a potential difference on both ends of the second semiconductor switch when the second semiconductor switch is opened.

According to the third aspect related to the innovations herein, provided is one exemplary test apparatus for testing a device under test, the test apparatus including: a signal generator that generates a test signal to be inputted to the device under test; a filter circuit that allows a predetermined frequency component of the test signal to pass through to be inputted to the device under test; and a determining section that determines whether the device under test is defective or not, based on an output signal outputted by the device under test in response to the test signal, where the filter circuit includes: a first filter and a second filter that have different frequency characteristics from each other that determine which frequency component of the test signal is allowed to pass therethrough; a first switch circuit that switches whether to input the test signal to the first filter; and a second switch circuit that switches whether to input the test signal to the second filter, and where the first switch circuit and the second switch circuit include: a transmission path that transmits the test signal from an input end to an output end of the switch circuit; a first semiconductor switch that is provided on the transmission path and switches whether to transmit the test signal; a second semiconductor switch that is opened when the first semiconductor switch is short-circuited, and that is short-circuited when the first semiconductor switch is opened, thereby grounding, to a ground potential, a high-frequency signal leaked to the transmission path between the first semiconductor switch and the output end; a voltage controller that controls a potential at one end of the second semiconductor switch; and a voltage controller that causes a potential difference on both ends of the second semiconductor switch when the second semiconductor switch is opened.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Some aspects of the invention will now be described based on the embodiments, which do not intend to limit the scope of the present invention, but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention. The same or similar elements may occasionally be provided with the same reference numeral, with the related description thereof omitted.

FIG. 1shows a configuration of a test apparatus10according to a first embodiment of the present invention, together with a device under test100. The test apparatus10tests the device under test100. The test apparatus10includes a signal generator12, a filter circuit14, and a determining section16. The signal generator12generates a test signal to be inputted to the device under test100. The filter circuit14allows a predetermined frequency component of the test signal generated by the signal generator12to pass through and to be inputted to the device under test100. The determining section16determines whether the device under test100is defective or not based on an output signal outputted by the device under test100in response to the test signal.

FIG. 2shows the configuration of the filter circuit14according to the first embodiment. The filter circuit14includes a first filter21, a second filter22, a first switch circuit31, a second switch circuit32, a third switch circuit33, and a fourth switch circuit34. The first filter21receives the test signal generated by the signal generator12via the first switch circuit31, and allows a predetermined frequency component of the input signal to pass through and be outputted to the device under test100through the third switch circuit33. The first switch circuit31switches whether to input, to the first filter21, the test signal generated by the signal generator12. The third switch circuit33switches whether to output, to the device under test100, the signal having passed through the first filter21.

The second filter22receives the test signal generated by the signal generator12, via the second switch circuit32, and allows a predetermined frequency component of the input signal to pass through and be outputted to the device under test100via the fourth switch circuit34. The second switch circuit32switches whether to input, to the second filter22, the test signal generated by the signal generator12. The fourth switch circuit34switches whether to output, to the device under test100, the signal having passed through the second filter22. Then the first filter21and the second filter22have different frequency characteristics from each other that determine which frequency component of the input signal is allowed to pass therethrough.

The filter circuit14is controlled to short-circuit or open the first through the fourth switch circuits31-34, according to the frequency component which it passes through. For example, when passing the frequency component defined by the frequency characteristic of the first filter21, the filter circuit14controls to short-circuit the first switch circuit31and the third switch circuit33, and to open the second switch circuit32and the fourth switch circuit34. When passing the frequency component defined by the frequency characteristic of the second filter22, the filter circuit14controls to open the first switch circuit31and the third switch circuit33, and to short-circuit the second switch circuit32and the fourth switch circuit34. In this way, the filter circuit14is able to selectively output a frequency component included in the test signal (input signal) generated by the signal generator12, to the device under test100. Note that the first through the fourth switches31-34may have substantially the same configuration as each other. As follows, the first through the fourth switches31-34are collectively referred to as a switch circuit30.

In the present embodiment, the filter circuit14may include, in addition to the first filter21and the second filter22, one or more filters having different frequency characteristics from each other that determine which frequency component of the input signal is allowed to pass therethrough. In this case, the filter circuit14includes, for each filter, one or more switches for switching whether to input a test signal generated by the signal generator12to a corresponding filter, and one or more switches for switching whether to output a signal having passed a corresponding filter to the device under test100. Accordingly, the filter circuit14according to the present embodiment is able to selectively pass a multitude of frequency components.

FIG. 3shows a configuration of a switch circuit30according to the first embodiment. The switch circuit30includes a transmission path42, a first semiconductor switch44, a capacitor46, a second semiconductor switch48, a third semiconductor switch50, a voltage controller52, and an inductor54, for switching whether to output an input signal.

The transmission path42is formed between an input terminal62and an output terminal64, and transmits an input signal inputted through the input terminal62from the input terminal62to the output terminal64of the switch circuit30. The first semiconductor switch44is provided for the transmission path42, and switches whether to transmit the input signal inputted from the input terminal62through the transmission path42. That is, the first semiconductor switch44is provided between the input terminal62and the output terminal64, and switches whether to short-circuit or open the input terminal62and the output terminal64.

The capacitor46has a predetermined capacitance and is provided between the transmission path42between the first semiconductor switch44and the output terminal64, and the ground potential. Because of having a predetermined capacitance, the capacitor46is able to cut off the direct current flowing between the transmission path42between the first semiconductor switch44and the output terminal64, and the ground potential, while passing the alternate current. The second semiconductor switch48opens the capacitor46and the ground potential when the first semiconductor switch44is short-circuited. The second semiconductor switch48short-circuits the capacitor46and the ground potential when the first semiconductor switch44is opened.

The third semiconductor switch50is provided on the transmission path42between the connection point between the transmission path42and the capacitor46, and the output terminal64. The third semiconductor switch50operates in synchronization with the first semiconductor switch44. That is, the third semiconductor switch50switches short-circuit and opening of the input terminal62and the output terminal64, in synchronization with the first semiconductor switch44.

The voltage controller52controls the potential of the connection point between the capacitor46and the second semiconductor switch48. The voltage controller52may include a bias application circuit66operable to apply a predetermined bias voltage to a connection point between the capacitor46and the second semiconductor switch48. The voltage controller52may use the bias application circuit66to apply a predetermined bias voltage to the connection point between the capacitor46and the second semiconductor switch48.

The inductor54has a predetermined inductance, and is provided between the voltage controller52and a connection point that lies between the capacitor46and the second semiconductor switch48. Because of having a predetermined inductance, the inductor54is able to cut off the alternate current flowing between the voltage controller52and the connection point that lies between the capacitor46and the second semiconductor switch48, while passing the direct current.

The switch circuit30having the above-described configuration operates as follows. When being controlled to cut off the input from the output, the first semiconductor switch44and the third semiconductor switch50open the input terminal62and the output terminal64. Accordingly, the switch circuit30cuts-off the signal passing between the input terminal62and the output terminal64, and does not output an input signal. In this case, the second semiconductor switch48further short-circuits the capacitor46and the ground potential. In this way, even when the high-frequency signal inputted through the input terminal62or the output terminal64has passed through the parasitic capacitance of the first semiconductor switch44or of the third semiconductor switch50, the capacitor46and the second semiconductor switch48, in collaboration, can ground the high-frequency signal to the ground potential. Therefore, the switch circuit30does not output a leak signal inputted through the input terminal62or the output terminal64at the time of opening from the opposite terminal, thereby leading to improvement in insulation property at the time of opening.

When the switch circuit30is controlled to conduct the input to the output, the first semiconductor switch44and the third semiconductor switch50short-circuit the input terminal62and the output terminal64. Accordingly, the switch circuit30is able to connect the input terminal62and the output terminal64, to output an input signal from the output terminal64. In this case, the second semiconductor switch48further opens the capacitor46and the ground potential, and the bias application circuit66of the voltage controller52applies a predetermined bias voltage to the connection point between the capacitor46and the second semiconductor switch48.

Note that the capacitance between output terminals of a semiconductor switch becomes small when the voltage between terminals is high. Also, when the capacitance between output terminals of a semiconductor switch is small, the insulating property of the high-frequency signal improves. Therefore, when one end of the second semiconductor switch48is provided with a predetermined bias voltage and the other end thereof is provided with a ground potential, the semiconductor switch48has an increased voltage between terminals, thereby leading to improvement in insulation property of the high-frequency signal.

Consequently, the switch circuit30is able to reduce leakage of the signal passing between the input terminal62and the output terminal64, towards the ground potential via the second semiconductor switch48. That is, the switch circuit30is able to reduce the effect exerted by the second semiconductor switch48on the signal passing between the input terminal62and the output terminal64. Furthermore, since the inductor54cuts off the high frequency signal, the signal passing between the input terminal62and the output terminal64in the switch circuit30is prevented from leaking towards the ground potential through the voltage controller52.

In the switch circuit30, the change in capacitance between terminals relative to the voltage between terminals of the second semiconductor switch48may be a cause of non-linearity of the transmission characteristic between the input terminal62and the output terminal64. That is, when the change ratio of the capacitance between terminals relative to the voltage between terminals is large in the second semiconductor switch48, the switch circuit30deforms the signal passing between the input terminal62and the output terminal64. As opposed to this, the change ratio of the capacitance between output terminals of a semiconductor switch relative to the voltage between terminals becomes small as the voltage between terminals gets large. Therefore, since the voltage controller52causes a large voltage between terminals in the second semiconductor switch48, the switch circuit30is able to pass a signal between the input terminal62and the output terminal64with little deformation. Consequently, the switch circuit30is able to improve the linearity of the transmission characteristic of the transmission path42between the input terminal62and the output terminal64at the time of short-circuit.

In the voltage controller52, the bias application circuit66may apply a bias voltage corresponding to the rated voltage of the second semiconductor switch48. The bias application circuit66may apply a bias voltage, the value of which is obtained by subtracting a predetermined voltage value from the rated voltage of the second semiconductor switch48. Or, the bias voltage applied by the bias application circuit66may be close to but no greater than the rated voltage of the second semiconductor switch48. As a result, the bias application circuit66can reduce the capacitance between output terminals of the second semiconductor switch48within the range in which the operation of the second semiconductor switch48is compensated.

FIG. 4shows a first example of the configuration of the bias application circuit66, together with the capacitor46, the second semiconductor switch48, and the inductor54.FIG. 5shows a second example of the configuration of the bias application circuit66, together with the capacitor46, the second semiconductor switch48, and the inductor54. The bias application circuit66may include a constant voltage source72and a current restriction resistance74, for example. The constant voltage source72applies a bias voltage to the connection point between the capacitor46and the second semiconductor switch48. The current restriction resistance74restricts the amount of current flowing to the second semiconductor switch48from the constant voltage source72. As inFIG. 4, the constant voltage source72may be provided between the constant voltage source72and the second semiconductor switch48. The constant voltage source72may also be provided between the second semiconductor switch48and the ground potential, as shown inFIG. 5.

The bias application circuit66having the above-described configuration can apply a predetermined bias voltage to the connection point between the capacitor46and the second semiconductor switch48when the second semiconductor switch48is opened, i.e., when there is a short-circuit between the input terminal62and the output terminal64. The bias application circuit66can also restrict the current flowing to the second semiconductor switch48while not breaking the second semiconductor switch48for example, when the second semiconductor switch48is short-circuited, i.e., when the input terminal62and the output terminal64are opened.

FIG. 6shows a third example of the configuration of the bias application circuit66, together with the capacitor46, the second semiconductor switch48, and the inductor54. The bias application circuit66may include a constant current source76and a voltage defining element78, for example. The constant current source76supplies a bias current corresponding to the rated current of the second semiconductor switch48, to the connection point between the capacitor46and the second semiconductor switch48. The voltage defining element78is provided in parallel with the constant current source76, and defines the bias voltage applied to the connection point by the constant current source76.

The bias application circuit66having the above-described configuration is able to apply a predetermined bias voltage to the connection point between the capacitor46and the second semiconductor switch48, as well as restricting the current flowing to the second semiconductor switch48while not breaking the second semiconductor switch48for example, when the second semiconductor switch48is short-circuited, i.e., when the input terminal62and the output terminal64are opened.

FIG. 7shows a configuration of the switch circuit30according to a second embodiment. Note that the second embodiment has substantially the same configuration and function as the first embodiment, and so the same reference numeral is used for substantially the same component betweenFIG. 7andFIG. 3, and the explanation thereof is omitted except for the differences therebetween.

In the second embodiment, the switch circuit30switches whether to output an input signal of an alternate current. The switch circuit30further includes a first capacitor82and a second capacitor84, instead of the capacitor46. The first capacitor82is provided on the transmission path42between the first semiconductor switch44and the input terminal62, and has a predetermined capacitance. Because of having a capacitance, the first capacitor82inputs an alternate current signal and cuts off input of a direct current signal. The second capacitor84is provided on the transmission path42between the third semiconductor switch50and the output terminal64, and has a predetermined capacitance. Because of having a capacitance, the second capacitor84outputs an alternate current signal, and cuts off output of a direct current signal.

The second semiconductor switch48is provided between the transmission path42between the first semiconductor switch44and the third semiconductor switch50, and the ground potential. The second semiconductor switch48opens the transmission path42and the ground potential when the first semiconductor switch44is short-circuited, and short-circuits the transmission path42and the ground potential when the first semiconductor switch44is opened. The voltage controller52controls the potential of the connection point between the transmission path42and the second semiconductor switch48.

When the switch circuit30having the above-described configuration is controlled to cut off the input from the output, the second semiconductor switch48short-circuits the transmission path42between the first semiconductor switch44and the third semiconductor switch50, and the ground potential. Accordingly, even when a high-frequency signal inputted via the input terminal62or the output terminal64has passed the first semiconductor switch44or the third semiconductor switch50, the high-frequency signal can be grounded to the ground potential via the second semiconductor switch48. Accordingly, the switch circuit30does not output the high-frequency signal inputted through the input terminal62or the output terminal64at the time of opening from the opposite terminal, thereby leading to improvement in insulation property at the time of opening.

When controlled to conduct the input and the output, the second semiconductor switch48opens the transmission path42between the first semiconductor switch44and the third semiconductor switch50, and the ground potential, and the voltage controller52applies a predetermined bias voltage to the connection point between the transmission path42between the first semiconductor switch44and the third semiconductor switch50, and the second semiconductor switch48. Consequently, one end of the second semiconductor switch48is provided with the predetermined bias voltage, and the other end thereof is provided with a ground potential. This increases the voltage between terminals, to improve the insulation property of a high-frequency signal. Accordingly, the switch circuit30is able to improve the linearity of the transmission characteristic of the transmission path42between the input terminal62and the output terminal64at the time of short-circuit, just as in the first embodiment.

FIG. 8shows a configuration of a filter circuit14according to a third embodiment of the present invention. Note that the third embodiment has substantially the same configuration and function as the first embodiment, and so the same reference numeral is used for substantially the same component betweenFIG. 8,FIG. 2, andFIG. 3, and the explanation thereof is omitted except for the differences therebetween.

In the third embodiment, each of the first through the fourth switch circuits31-34includes a voltage controller52common to the other switch circuits. Due to this arrangement, the first through the fourth switch circuits31-34have a more simplified circuitry configuration in the present embodiment.

Moreover, in the third embodiment, the first switch circuit31and the second switch circuit32may be a so-called L-shape filter that is not equipped with a third semiconductor switch50. Moreover, in the present embodiment, the third switch circuit33and the fourth switch circuit34may be a so-called reverse L-shape filter that is not equipped with a first semiconductor switch44. Consequently, the first through the fourth switch circuits31-34have a more simplified circuitry configuration in the present embodiment.

The operations, the processes, the steps, or the like in the apparatus, the system, the program, and the method described in the claims, the specification, and the drawings are not necessarily performed in the described order. The operations, the processes, the steps, or the like can be performed in an arbitrary order, unless the output of the former-described processing is used in the later processing. Even when expressions such as “First,” or “Next,” or the like are used to explain the operational flow in the claims, the specification, or the drawings, they are intended to facilitate the understanding of the invention, and are never intended to show that the described order is mandatory.

As clear from the foregoing, one or more embodiments of the present invention improve the linearity of the transmission characteristic at the time of short-circuit between the input end and the output end.