BILAYER RDL STRUCTURE FOR BUMP COUNT REDUCTION

A method of forming semiconductor device includes forming interconnect structure over substrate; forming first passivation layer over the interconnect structure, and metal-insulator-metal capacitor in the first passivation layer; forming first redistribution layer including first pads over the first passivation layer, and first vias extending into the first passivation layer; conformally forming second passivation layer over the first redistribution layer and first passivation layer, and patterning the second passivation layer to form via openings exposing the first pads; forming second redistribution layer including second pads over the second passivation layer, and second vias in the first via openings, wherein the first and second redistribution layers include aluminum-copper alloy and copper, respectively; forming dielectric layer over the second redistribution layer, and patterning the dielectric layer to form via openings exposing some second pads; and forming bumps over the dielectric layer and in the via openings to contact exposed second pads.

BACKGROUND

The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrinking the process node towards the 5 nm node). As semiconductor devices are scaled down, new techniques are needed to maintain the electronic components' performance from one generation to the next. Device complexity is increasing as manufacturers design smaller feature sizes and more functionality into integrated circuits.

One type of capacitor is a metal-insulator-metal (MIM) capacitor, which is used in mixed signal devices and logic devices, such as embedded memories and radio frequency devices. MIM capacitors are used to store a charge in a variety of semiconductor devices. A MIM capacitor is formed horizontally over a semiconductor substrate, with two metal layers sandwiching a dielectric layer parallel to the semiconductor substrate.

Although existing processes for fabricating semiconductor devices with MIM capacitors have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, it is desirable to form a semiconductor device that includes as few conductive bumps as possible to reduce device size.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Throughout the description herein, unless otherwise specified, the same or similar reference numerals in different figures refer to the same or similar element formed by a same or similar formation method sing a same or similar material(s). In addition, unless otherwise specified, figures with the same numeral and different alphabets (e.g.,FIG.8AandFIG.8B) illustrate different views (e.g., along different cross-sections) of the same semiconductor device at the same stage of manufacturing.

The present disclosure relates to a semiconductor device including metal-insulator-metal (MIM) capacitors and a method of forming the same. In accordance with some embodiments, a bilayer redistribution layer (RDL) structure is formed over a passivation layer embedding MIM capacitors. The bilayer RDL structure includes a first RDL layer and a second RDL layer over the first RDL layer. The first RDL layer and its associated redistribution vias are configured to electrically couple underlying devices or components (e.g., the MIM capacitors and underlying circuits and/or electrical components/devices) and to electrically couple those underlying devices or components to the second RDL layer above. The second RDL layer and its associated redistribution vias are configured to provide routing of power and ground signals to devices or components in the semiconductor device. Conductive bumps formed on the second RDL layer provide the power and ground signals and provide electrical connection between the semiconductor device and an external circuitry. In accordance with some embodiments, the second RDL layer is formed of a material with a lower surface/sheet resistance than the first RDL layer. Therefore, it is more suitable (compared to the first RDL layer) for routing of the power and grounds due to lower IR drop and can help reduce the number of power and ground bumps. As a result, the bump area (and thus the device area) of the semiconductor device can also be reduced accordingly, contributing to device size reduction in advanced technology applications. Also, the redistribution vias associated with the first RDL layer have a smaller via pitch than the redistribution vias associated with the second RDL layer, which facilitates better RC delay performance when the MIM capacitors operate at high frequencies.

FIGS.1A,1B,2,3A,3B,4-7,8A,8B,9,10A, and10Billustrate cross-sectional views or plan views of a semiconductor device100at various stages of manufacturing, in accordance with some embodiments. Some corresponding processes are also reflected schematically in the process flow shown inFIG.13. The semiconductor device100may be a device wafer including active devices (e.g., transistors, diodes, or the like) and/or passive devices (e.g., capacitors, inductors, resistors, or the like), and may include multiple semiconductor chips (which are also referred to as semiconductor dies when sawed apart). For simplicity, only one die is depicted in the figures. These dies may include logic dies (e.g., central processing unit (CPU) die, graphics processing unit (GPU) die, field-programmable gate array (FPGA) die, application specific integrated circuit (ASIC) die, system-on-chip (SoC) die, system-on-integrated-chip (SoIC) die, microcontroller die, or the like), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, high bandwidth memory (HBM) die, or the like), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) die), front-end dies (e.g., analog front-end (AFE) die), the like, or combinations thereof.

In some embodiments, the semiconductor device100is an interposer wafer, which may or may not include active devices and/or passive devices. In subsequent discussion, a device wafer is used as an example of the semiconductor device100. The teaching of the present disclosure may also be applied to interposer wafers or other semiconductor structures, as those skilled in the art will readily appreciate.

As shown inFIG.1A, the semiconductor device100includes a semiconductor substrate101and electrical components102(e.g., transistors, diodes, resistors, inductors, or the like) formed in or on the semiconductor substrate101(which may also be referred to as substrate). The semiconductor substrate101may include a semiconductor material, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate101may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof. Other substrates, such as multi-layered or gradient substrates, may also be used.

InFIG.1A, electrical components102are formed in device regions of the semiconductor substrate101. Examples of the electrical components102include transistors (e.g., complementary metal-oxide semiconductor (CMOS) transistors), diodes, resistors, capacitors, inductors, and the like. The electrical components102may be formed using any suitable method, and the details are not discussed here.

In some embodiments, after the electrical components102are formed, an inter-layer dielectric (ILD) layer (not shown for simplicity) is formed over the semiconductor substrate101and over the electrical components102. The ILD layer may fill gaps between gate stacks of the transistors (not shown) of the electrical components102. In accordance with some embodiments, the ILD layer comprises silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), or the like. The ILD layer may be formed using spin coating, flowable chemical vapor deposition (FCVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), another applicable process, or a combination thereof.

Contact plugs are formed in the ILD layer to electrically couple the electrical components102to conductive features (e.g., metal lines and vias) of subsequently formed interconnect structure103. Note that in the present disclosure, unless otherwise specified, a conductive feature refers to an electrically conductive feature, and a conductive material refers to an electrically conductive material. In accordance with some embodiments, the contact plugs comprise a conductive material such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and/or multi-layers thereof. The formation of the contact plugs may include forming contact openings in the ILD layer; forming one or more conductive material(s) in the contact openings; and performing a planarization process, such as chemical mechanical polish (CMP), to level the top surface of the contact plugs with the top surface of the ILD layer.

Still referring toFIG.1A, an interconnect structure103is formed over the ILD layer, over the semiconductor substrate101, and over the electrical components102. The respective process is illustrated as process1001in the process flow1000as shown inFIG.13. The interconnect structure103comprises dielectric layers104and conductive features (e.g., metal lines and vias) formed in the dielectric layers104. The interconnect structure103is used to interconnect (e.g., being electrically coupled to) the electrical components102to form functional circuits of the semiconductor device100.

In some embodiments, each of the dielectric layers104, which may also be referred to as an inter-metal dielectric (IMD) layer, comprises a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. In accordance with some embodiments, the dielectric layers104are formed of a low-k dielectric material having a dielectric constant (k-value) lower than 3.0, such as about 2.5, about 2.0, or even lower. The formation of each of the dielectric layers104may include depositing a porogen-containing dielectric material over the ILD layer, and then performing a curing process to drive out the porogen, thereby forming the dielectric layer104that is porous. Other suitable method may also be used to form the dielectric layers104.

As shown inFIG.1A, conductive features, such as conductive lines105and conductive vias106, are formed in the dielectric layers104. In some embodiments, the conductive features include a diffusion barrier layer and a conductive material (e.g., copper, or a copper-containing material) over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), another applicable process or a combination thereof. After the diffusion barrier layer is formed, the conductive material is formed over the diffusion barrier layer. The formation of the conductive features may include a single damascene process, a dual damascene process, or the like.

Next, a passivation layer107is formed over the interconnect structure103, and metal-insulator-metal (MIM) capacitors108are formed in the passivation layer107(which may also be referred to as first passivation layer). The respective process is illustrated as process1002in the process flow1000as shown inFIG.13. The passivation layer107may include multiple sub-layers (e.g.,107A-107E shown inFIG.1B) and may be formed of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, another applicable material, or a combination thereof. The passivation layer107may be formed by CVD, FVCVD, or the like. In an example, the thickness T1of the passivation layer107may be in the range between about 10 kÅ (Ångstrom) to about 20 kÅ (e.g., about 10 kÅ), but the present disclosure is not limited thereto.

FIG.1Billustrates an enlarged view of an area109inFIG.1Ato show details of the MIM capacitors108. As shown inFIG.1B, each of the MIM capacitors108includes two metal layers108M (e.g., copper layers) and a dielectric layer108D (e.g., a high-k dielectric layer) between the metal layers108M. Each of the layers (e.g.,108M,108D, and108M) of the MIM capacitors108is formed in a respective passivation layer (e.g.,107B,107C, or107D). The upper metal layer108M and the lower metal layer108M of the MIM capacitor108may be connected to an overlying via110V and an underlying via110V, respectively, where the overlying via110V and the underlying via110V are formed in passivation layers107E and107A, respectively, in an example (see the left part ofFIG.1B). In another example (see the right part ofFIG.1B), the upper metal layer108M and the lower metal layer108M of the MIM capacitor108may be connected to a first overlying via110V1and a second overlying via110V2, respectively. The second overlying via110V2extends through the passivation layer107D and the dielectric layer108D to connect with the lower metal layer108M. Note that the second overlying via110V2is separated from (e.g., not contacting) the upper metal layer108M of the MIM capacitor108by portions of the passivation layer107D.

Referring back toFIG.1A, the lower metal layer of the MIM capacitor108may be electrically coupled to a conductive feature of the interconnect structure103, e.g., through a conductive via that extends from the lower metal layer of the MIM capacitor108to the conductive feature of the interconnect structure103. In addition, the MIM capacitors108may be electrically coupled in parallel to provide a large capacitance value. For example, the upper metal layers of the MIM capacitors108may be electrically coupled together, and the lower metal layers of the MIM capacitors108may be electrically coupled together.

Referring next toFIG.2, openings111are formed in the passivation layer107. Some openings111extend through the passivation layer107to expose conductive features of the interconnect structure103, while other some openings111extend partially through the passivation layer107to expose the upper metal layers of the MIM capacitors108. The openings111may be formed in one or more etching processes (e.g., anisotropic etching processes), and sidewalls of each of the openings111may be perpendicular to or inclined to the upper surface of the passivation layer107.

After the openings111are formed, a barrier layer112is formed conformally over the upper surface of the passivation layer107and along sidewalls and bottoms of the openings111. The barrier layer112may have a multi-layer structure, and may include a diffusion barrier layer (e.g., a TiN layer) and a seed layer (e.g., a copper seed layer) formed over the diffusion barrier layer. The barrier layer112may be formed using any suitable method, such as CVD, PVD, ALD, another applicable process, or a combination thereof.

Referring next toFIG.3A, conductive pads114P are formed over the passivation layer107, and conductive vias114V are formed in the openings111(seeFIG.2) of the passivation layer107. The formation of the conductive pads114P and the conductive vias114V may include depositing a conductive (or metal) material113(e.g., an aluminum-copper alloy) over the barrier layer112and in the openings111using a suitable deposition method such as PVD, sputtering, evaporation, or the like; forming a photoresist layer over the conductive material113using, for example, spin coating; patterning the photoresist layer (e.g., using photolithography technique) to form openings at locations where the first RDL layer114will not be formed; performing an etching process (e.g., anisotropic etching process) to remove portions of the conductive material113on which the photoresist layer is not formed (and portions of the barrier layer112below); and then removing the patterned photoresist layer by a suitable removal process, such as ashing.

As a result, portions of the conductive material113remaining over the passivation layer107form the conductive pads114P, and portions of the conductive material113that fill (i.e., extending into) the openings111in the passivation layer107form the conductive vias114V, where the conductive vias114V electrically couple the conductive pads114P to underlying conductive features of the interconnect structure103and/or the MIM capacitors108. Note that in the discussion herein, the barrier layer112in the openings111is considered part of the conductive vias114V, and the barrier layer112over the upper surface of the passivation layer107is considered part of the conductive pads114P. Although not shown inFIG.3A, conductive lines (e.g., aluminum-copper (Al—Cu) alloy lines) may also be formed over the upper surface of the passivation layer107during the same processing steps to form the conductive pads114P. The conductive pads114P (which may also be referred to as first pads) and the conductive lines may be collectively referred to as a redistribution layer (RDL)114(which may also be referred to as first RDL layer), and the conductive vias114V may be referred to as (first) redistribution vias114V. The respective process of forming the first RDL layer114and the first redistribution vias114V is illustrated as process1003in the process flow1000as shown inFIG.13.

In an example, the thickness T2of the first RDL layer114may be in the range between about 10 kÅ to about 40 kÅ (e.g., about 28 kÅ), but the present disclosure is not limited thereto. The shape of the cross-section of the conductive pad114P may be a dome shape (e.g., with a curved upper surface), a concave shape, a polygon shape, or a rectangular (or square) shape.

FIG.3Bis a schematic plan view showing the arrangement of the conductive pads114P of the first RDL layer114and the conductive vias114V inFIG.3A(where conductive lines of the first RDL layer114interconnecting the conductive pads114P are not shown for simplicity). The conductive pads114P may be arranged in multiple rows and columns over the passivation layer107, and the conductive vias114V may be arranged corresponding to the conductive pads114P. It should be understood that the configuration of the conductive pads114P and the conductive vias114V shown inFIG.3Bis merely a schematic example, and is not intended to be, and should not be constructed to be, limiting to the present disclosure. Each of the conductive pads114P and conductive vias114V inFIG.3Bis illustrated to have a square shape as a non-limiting example. Other shapes, such as circle shape, oval shape, rectangular shape, other polygon shape, or the like, are also possible and are fully intended to be included within the scope of the current disclosure.

In some embodiments, the center (line) C1of each of the conductive pads114P is aligned with the center (line) C2of the respective conductive via114V, as shown inFIG.3A, but the center line C1of the conductive pad114P may also be laterally offset from the center line C2of the respective conductive via114V in other embodiments (which will be described further later).

In the example ofFIGS.3A and3B, the (minimum) space P1between adjacent conductive vias114V may be in the range between about 5 μm (micrometer) to 7 μm (e.g., about 5 μm), and/or the (minimum) space P3between adjacent conductive pads114P may be in the range between about 4 μm to 6 μm (e.g., about 4 μm), but the present disclosure is not limited thereto.

Referring next toFIG.4, a passivation layer115(which may also be referred to as second passivation layer) is conformally formed over the first RDL layer114and the (first) passivation layer107. In some embodiments, the passivation layer115has a multi-layered structure and includes an oxide layer (e.g., silicon oxide) and a nitride layer (e.g., silicon nitride) over the oxide layer. In other embodiments, the passivation layer115has a single layer structure, e.g., having a single nitride layer. The passivation layer115may be formed using, for example, CVD, PVD, ALD, another applicable process, or a combination thereof.

Referring next toFIG.5, a photoresist layer116is formed over the passivation layer115by, e.g., spin coating. The photoresist layer116is then patterned by, e.g., photolithography techniques to form openings117at locations where second conductive/redistribution vias will be formed. Next, an etching process is performed to remove portions of the passivation layer115(i.e., patterning the passivation layer115) exposed by the openings117. It should be understood that openings (i.e., the removed portions) of patterned passivation layer115are located directly under the openings117of the photoresist layer116, so they may also be referred to as openings117after the photoresist layer116is removed in a subsequent process (not shown). In some embodiments, the etching process is a dry etch process (e.g., a plasma etching process) using a process gas comprising a mixture of CF4, CHF3, N2, and Ar. Other process gas may also be used.

After the etching process, all conductive pads114P are exposed through the openings117. Sidewalls of each of the openings117may be perpendicular to or inclined to the upper surface of the photoresist layer116. The respective process of forming and patterning the second passivation layer115is illustrated as process1004in the process flow1000as shown inFIG.13.

Referring next toFIG.6, a photoresist layer118is formed over the passivation layer115and over the conductive pads114P by, e.g., spin coating, after the photoresist layer116(seeFIG.5) is removed. The photoresist layer118is then patterned by, e.g., photolithography techniques to form openings119at locations where a second RDL layer will be formed. In some embodiments, the openings119of the patterned photoresist layer118correspond to the underlying openings117of the patterned passivation layer115, and the width W2of each of the openings119is generally greater than the width W1of the respective opening117.

After the openings119are formed, a barrier layer120is formed conformally over the upper surface of the photoresist layer118and along sidewalls and bottoms of the openings117and119. The material, structure and formation method of the barrier layer120may be the same or similar to those of the barrier layer112illustrated inFIG.2, and are not repeated here.

Referring next toFIG.7, a conductive (or metal) material121(e.g., copper) is deposited over the barrier layer120, e.g., by electrochemical plating (ECP). The conductive material121fills the remaining portions of the openings117and119. The conductive material121further includes some portions over the upper surface of the photoresist layer118. Next, a planarization process such as a chemical mechanical polish (CMP) process is performed to remove excess portions of the conductive material121and the barrier layer120, until the photoresist layer118is exposed. Afterwards, the photoresist layer118is removed by a suitable removal process, such as ashing.

As a result, portions of the conductive material121remaining over the passivation layer115form conductive pads122P, and portions of the conductive material121that fill (i.e., extending into) the openings117(seeFIG.6) in the passivation layer115form conductive vias122V, where the conductive vias122V electrically couple the conductive pads122P to the underlying conductive pads114P of the first RDL layer114, as shown inFIG.8A. Note that in the discussion herein, the barrier layer120(seeFIG.7) in the openings117is considered part of the conductive vias122V, and the barrier layer120over the upper surface of the passivation layer115is considered part of the conductive pads122P. Although not shown inFIG.8A, conductive lines (e.g., copper lines) may also be formed over the upper surface of the passivation layer115during the same processing steps to form the conductive pads122P. The conductive pads122P (which may also be referred to as second pads) and the conductive lines may be collectively referred to as a redistribution layer (RDL)122(which may also be referred to as second RDL layer), and the conductive vias122V may be referred to as (second) redistribution vias122V. The respective process of forming the second RDL layer122and the second redistribution vias122V is illustrated as process1005in the process flow1000as shown inFIG.13.

In the example ofFIG.8A, the thickness T3of the second RDL layer122is greater than the thickness T1(seeFIG.3A) of the first RDL layer114For example, the thickness T3of the second RDL layer122may be in the range between about 20 kÅ to about 80 kÅ (e.g., about 55 kÅ), but the present disclosure is not limited thereto. The shape of the cross-section of the conductive pad122P may be a dome shape (e.g., with a curved upper surface), a concave shape, a polygon shape, or a rectangular (or square) shape, similar to the conductive pads114P.

FIG.8Bis a schematic plan view showing the arrangement of the conductive pads122P of the second RDL layer122and the conductive vias122V inFIG.8A(where conductive lines of the second RDL layer122interconnecting the conductive pads122P are not shown for simplicity). The arrangement/position of the conductive pads122P and the conductive vias122V is the same as (i.e., corresponding to) the arrangement/position of the conductive pads114P of the first RDL layer114and the conductive vias114V illustrated inFIG.3B, but the present disclosure is not limited thereto. Other arrangements of the conductive pads122P and the conductive vias122V may also be used, such as different arrangements than those of conductive pads114P and the conductive vias114V. Each of the conductive pads122P and conductive vias122V inFIG.8Bis illustrated to have a square shape as a non-limiting example. Other shapes, such as circle shape, oval shape, rectangular shape, other polygon shape, or the like, are also possible and are fully intended to be included within the scope of the current disclosure.

In some embodiments, the center (line) C3of each of the conductive pads122P is aligned with the center (line) C4of the respective conductive via122V, as shown inFIG.8A, but the center line C3of each conductive pad122P may also be laterally offset from the center line C4of the respective conductive via122V in other embodiments.

In the example ofFIGS.8A and8B, the (minimum) space P2between adjacent conductive vias122V may be in the range between about 6 μm to 8 μm (e.g., about 6 μm), and/or the (minimum) space P4between adjacent conductive pads122P may be in the range between about 4 μm to 7 μm (e.g., about 4 μm), but the present disclosure is not limited thereto.

Referring next toFIG.9, a dielectric layer123is formed over the second RDL layer122, over the passivation layer115, and over the passivation layer107. Openings124(which may also be referred to as second via openings) are then formed (e.g., e.g., using photolithography and etching techniques) in the dielectric layer123to expose some of the conductive pads122P of the second RDL layer122. The dielectric layer123may be formed of, e.g., polymer, polyimide (PI), benzocyclobutene (BCB), or the like. The dielectric layer123is illustrated as a single layer inFIG.9as a non-limiting example. The dielectric layer123may also have a multi-layer structure that includes a plurality of sub-layers formed of different dielectric materials. The respective process of forming and patterning the dielectric layer123is illustrated as process1007in the process flow1000as shown inFIG.13.

In some embodiment, sidewalls1221of the second redistribution vias122V are laterally surrounded by and in contact with the second passivation layer115, and are separated from the dielectric layer123by the second passivation layer115.

Referring next toFIG.10A, conductive bumps (e.g., micro-bumps or C4 bumps)125are formed on the conductive pads122P exposed through the openings124(see FIG.9), and solder regions127(e.g., solder material) are formed on the conductive bumps125. The respective process is illustrated as process1008in the process flow1000as shown inFIG.13. The conductive bumps125and the solder regions127are configured to provide power and ground signals to devices or components in the semiconductor device100and provide electrical connection between the semiconductor device100and an external circuitry (not shown). The formation of the conductive bumps125may include forming a seed layer126over the dielectric layer123and along sidewalls and bottoms of the openings124(seeFIG.9); forming a patterned photoresist layer (not shown) over the seed layer126, where openings of the patterned photoresist layer are formed at locations where the conductive bumps125are to be formed; forming (e.g., plating) an electrically conductive material (e.g., copper) over the seed layer126in the openings; removing the patterned photoresist layer; and then removing portions of the seed layer126over which no conductive bump125is formed.

As a result, portions of the electrically conductive material that fill (i.e., extending into) the openings124form conductive bump vias125V that electrically couple the conductive bumps125to underlying exposed conductive pads122P. Note that in the discussion herein, the seed layer126in the openings124is considered part of the conductive bump vias125V, and the seed layer126over the upper surface of the dielectric layer123is considered part of the conductive bump125.

FIG.10Bis a schematic plan view showing the arrangement of the conductive bumps125(where solder regions127are not shown for simplicity). As shown in FIG. the conductive bumps125may be arranged in multiple rows and columns over the dielectric layer123, and may correspond to some of the underlying conductive pads122P (depicted in dashed lines) of the second RDL layer122. Therefore, the number of conductive bumps125is less than the number of conductive pads122P (which is equal to the number of conductive pads114P of the first RDL layer114). Each of the conductive bumps125inFIG.10Bis illustrated to have a square shape as a non-limiting example. Other shapes, such as circle shape, oval shape, rectangular shape, other polygon shape, or the like, are also possible and are fully intended to be included within the scope of the current disclosure.

In the example ofFIGS.10A and10B, the (minimum) space P5between adjacent conductive bumps125is greater than the (minimum) space P4between adjacent conductive pads122P. For example, the (minimum) space P5between adjacent conductive bumps125may be in the range between about 12 μm to 21 μm (e.g., about 12 μm), but the present disclosure is not limited thereto.

In the above-mentioned semiconductor device embodiments, a bilayer RDL structure is provided, which includes the first RDL layer114and the second RDL layer122over the first RDL layer114. The first RDL layer114and the associated (first) redistribution vias114V are configured to electrically couple underlying devices or components (e.g., the MIM capacitors108and underlying circuits and/or electrical components102) and the second RDL layer122above. The second RDL layer122and the associated (second) redistribution vias122V are configured to provide routing of power and ground signals (from the conductive bumps125) to devices or components in the semiconductor device100.

By forming the first RDL layer114with an aluminum-copper (Al—Cu) alloy material and the second RDL layer122with a copper (Cu) material as mentioned above, the second RDL layer122can have a smaller surface/sheet resistance than the first RDL layer114. For example, the sheet resistance of the second RDL layer122made of Cu (about 55 kÅ thick) is about 0.0033 ohm/sq (ohms per square), and the sheet resistance of the first RDL layer114made of Al—Cu alloy (about 28 kÅ thick) is about 0.0110, as examples. This helps the second RDL layer122to be more suitable (compared to the first RDL layer144) for routing of power and grounds due to lower IR drop, and can help further reduce the number of power and ground bumps (e.g., the number of conductive bumps125can be reduced to be less than number of conductive pads122P of the second RDL layer122, as discussed above). As a result, the bump area (and thus the device area) of the semiconductor device100can also be reduced accordingly, contributing to device size reduction in advanced technology applications.

In addition, the use of Al—Cu alloy material to form the first RDL layer114is to enable the MIM capacitors108to operate at high frequencies. As can be known by those skilled in the art, the process for forming Al—Cu RDL typically has a smaller (redistribution) via space/pitch than the process for forming Cu RDL (e.g., minimum via-to-via space: 5 μm for Al—Cu RDL; 6.9 μm for Cu RDL), so the first RDL layer114made of Al—Cu alloy helps to achieve better RC delay performance when the MIM capacitors operate at high frequencies (e.g., about 2.8 GHz).

Therefore, the advantages of reduced conductive bump count/device size and high frequency applications of MIM capacitors can be achieved at the same time by using the bilayer RDL structure of this embodiment. The same advantages cannot be obtained using a single RDL structure with Cu or Al—Cu alloy material.

It should be understood that the geometries, configurations, materials and the manufacturing methods described herein are only illustrative, and are not intended to be, and should not be constructed to be, limiting to the present disclosure. Many alternatives and modifications will be apparent to those skilled in the art, once informed by the present disclosure. For example, one skilled in the art will appreciate that the materials for the first RDL layer (and its associated vias) and second RDL layer (and its associated vias) are not limited to AlCu alloy and Cu materials, respectively. In other embodiments, the first RDL layer (and its associated vias) may comprise a first (metal) material (other than AlCu alloy) and the second RDL layer (and its associated vias) may comprise a second (metal) material (other than Cu), as long as the sheet resistance of the second material is lower than the sheet resistance of the first material.

FIG.11illustrates a cross-sectional view of a modified semiconductor device100′ in accordance with some other embodiments. The semiconductor device100′ differs from the above-described semiconductor device100only in that a passivation layer128(which may also be referred to as third passivation layer) is further provided. In the example ofFIG.11, the third passivation layer128is conformally over the second RDL layer122and the second passivation layer115and located below the dielectric layer123. The formation of the third passivation layer128precedes the formation of dielectric layer123(the respective process is illustrated as process1001in the process flow1006as shown inFIG.13). The structure and material(s) of passivation layer128may be the same as or similar to those of passivation layer115illustrated inFIG.4, and they are not repeated here. The third passivation layer128helps to block moisture and avoid oxidation of the second pad122P.

In some embodiments, the third passivation layer128is formed along the sidewalls and tops of each conductive pads122P of the second RDL layer122, except for the portions of the top surfaces of some conductive pads122P in contact with the conductive bumps125. More specifically, the third passivation layer128is in contact with sidewalls1222of each of the second pads122P, so that sidewalls1222of each second pad122P are separated from (e.g., not contacting) the dielectric layer123by the third passivation layer128. Also, the third passivation layer128extends over top surfaces of each second pad122P, and has some via openings128a(which may also be referred to as third via openings) corresponding to (e.g., located directly below the second via openings124, seeFIG.9, so the via openings128amay also be referred to as second via openings124) and exposing the second pad122P in contact with the conductive bumps125. The third passivation layer128may laterally surround the conductive bumps125.

FIG.12illustrates a cross-sectional view of a modified semiconductor device100″ in accordance with some other embodiments. The semiconductor device100″ differs from the above-described semiconductor device100′ (inFIG.11) only in that the center (line) C1of some conductive pads114P is laterally offset from the center line C2of the respective conductive via114V, so that the conductive pad114P has a relatively large area that is over (and that extends onto) the upper surface of the passivation layer107. This can improve the flatness of the upper surface of the conductive pads114P, thereby facilitating the landing of the conductive vias122V. In addition, in the example ofFIG.12, the center (line) C4of conductive vias122V, the center (line) C3of the conductive pads122P and the center (line) C5of the conductive bumps125are substantially aligned with each other, and are arranged opposite to the center (line) C2of the conductive vias114V relative to the center (line) C1of the conductive pads114P, but the present disclosure is not limited thereto. The center (lines) C3, C4and C5of the conductive pads122P, conductive vias122V and conductive bumps125may be aligned with the center (line) C1of the respective conductive pad114P in other embodiments.

The embodiments of the present disclosure have some advantageous features. By providing or forming a bilayer RDL structure over a passivation layer embedding MIM capacitors, where the upper RDL layer has a lower sheet resistance than the lower RDL layer, and the redistribution vias associated to the lower RDL layer have a smaller via pitch than the redistribution vias associated to the upper RDL layer, the benefits of reduced conductive bump count/device size and high frequency applications of MIM capacitors can be achieved simultaneously.

In accordance with some embodiments, a method of forming a semiconductor device is provided. The method includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure, and a metal-insulator-metal capacitor in the first passivation layer; forming a first redistribution layer including a plurality of first pads over the first passivation layer, and a plurality of first redistribution vias extending into the first passivation layer; conformally forming a second passivation layer over the first redistribution layer and the first passivation layer, and patterning the second passivation layer to form a plurality of first via openings exposing the first pads; forming a second redistribution layer including a plurality of second pads over the second passivation layer, and a plurality of second redistribution vias in the first via openings to contact the first pads, wherein the first redistribution layer and the first redistribution vias comprise aluminum-copper alloy, and the second redistribution layer and the second redistribution vias comprise copper; forming a dielectric layer over the second redistribution layer and the second passivation layer, and patterning the dielectric layer to form a plurality of second via openings exposing a part of the second pads; and forming a plurality of conductive bumps over the dielectric layer and in the second via openings to contact the part of the second pads.

In accordance with some embodiments, a method of forming a semiconductor device is provided. The method includes: forming an interconnect structure over a substrate and electrically coupled to an electrical component formed in or on the substrate; forming a first passivation layer over the interconnect structure, and a metal-insulator-metal capacitor in the first passivation layer; forming a first redistribution layer including a plurality of first pads over the first passivation layer, and a plurality of first redistribution vias extending into the first passivation layer; conformally forming a second passivation layer over the first redistribution layer and the first passivation layer, and patterning the second passivation layer to form a plurality of first via openings exposing the first pads; forming a second redistribution layer including a plurality of second pads over the second passivation layer, and a plurality of second redistribution vias in the first via openings to contact the first pads, wherein the first redistribution layer and the first redistribution vias comprise a first material, the second redistribution layer and the second redistribution vias comprise a second material, and the second material has a lower sheet resistance than that of the first material; forming a dielectric layer over the second redistribution layer and the second passivation layer, and patterning the dielectric layer to form a plurality of second via openings exposing a part of the second pads; and forming a plurality of conductive bumps over the dielectric layer and in the second via openings to contact the part of the second pads.

In accordance with some embodiments, a semiconductor device is provided. The semiconductor device includes: an electrical component in or on a substrate; an interconnect structure over the substrate and electrically coupled to the electrical component; a first passivation layer over the interconnect structure, and a metal-insulator-metal capacitor in the first passivation layer; a first redistribution layer including a plurality of first pads over the first passivation layer, and a plurality of first redistribution vias extending into the first passivation layer; a second passivation layer conformally over the first redistribution layer and the first passivation layer and having a plurality of first via openings exposing the first pads; a second redistribution layer including a plurality of second pads over the second passivation layer, and a plurality of second redistribution vias in the first via openings to contact the first pads, wherein the first redistribution layer and the first redistribution vias comprise a first material, the second redistribution layer and the second redistribution vias comprise a second material, and the second material has a lower sheet resistance than that of the first material; a dielectric layer over the second redistribution layer and the second passivation layer and having a plurality of second via openings exposing a part of the second pads, wherein the sidewalls of the second redistribution vias are in contact with the second passivation layer and separated from the dielectric layer by the second passivation layer; and a plurality of conductive bumps over the dielectric layer and in the second via openings to contact the part of the second pads.