ANALOG-TO-DIGITAL CONVERTER WITH INSTABILITY RECOVERY CIRCUIT

In described examples, an integrated circuit (IC) includes first and second integrators, first and second weighted summers, first and second digital-to-analog converters (DACs), and a quantizer. First and second inputs of the first weighted summer are respectively connected to an output of the first integrator and an output of the second DAC. An input of the second integrator is connected to an output of the first weighted summer. An input of the second weighted summer is connected to an output of the second integrator. An input of the quantizer is connected to an output of the second weighted summer. Inputs of the first and second DACs are connected to respective outputs of the quantizer. An output of the first DAC is connected to a first input of the first integrator. A second input of the first integrator and a third input of the first weighted summer are analog signal inputs.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of and priority to India Provisional Application No. 202341049171, filed Jul. 21, 2023, which is incorporated herein by reference.

TECHNICAL FIELD

This application relates generally to analog-to-digital converters (ADCs), and more particularly to continuous time delta sigma modulator (CTDSM) ADCs.

BACKGROUND

ADCs are used in a variety of applications to convert analog input signals into digital signals to enable digital signal processing. In some examples, increasing ADC resolution increases power or area cost of the ADC. Some applications, such as audio processing, have use cases that favor high resolution signal processing with reduced power draw and smaller device footprint. Battery powered audio devices, such as mobile phones, provide an example use case for ADCs with reduced power and area budgets.

SUMMARY

In described examples, an integrated circuit (IC) includes first and second integrators, first and second weighted summers, first and second digital-to-analog converters (DACs), and a quantizer. First and second inputs of the first weighted summer are respectively connected to an output of the first integrator and an output of the second DAC. An input of the second integrator is connected to an output of the first weighted summer. An input of the second weighted summer is connected to an output of the second integrator. An input of the quantizer is connected to an output of the second weighted summer. Inputs of the first and second DACs are connected to respective outputs of the quantizer. An output of the first DAC is connected to a first input of the first integrator. A second input of the first integrator and a third input of the first weighted summer are analog signal inputs.

In described examples, an IC includes a delta-sigma modulator (DSM) and a control circuit that operates the DSM in first and second modes. The DSM includes N>1 integrators, a first DAC, a second DAC, and a quantizer. In the first mode, the control circuit operates the DSM as an Nth order modulator, so that integrator outputs are responsive to a first feedback signal provided by the first DAC responsive to quantizer output. In the second mode, the control circuit operates the DSM as a first order modulator, so that quantizer output is responsive to an output of a single one of the integrators, to a second feedback signal provided by the second DAC responsive to quantizer output, and not to the first feedback signal. The control circuit switches from the first mode to the second mode responsive to an output of an integrator and a threshold.

In described examples, an IC includes a lowpass analog filter, a sampling circuit, first and second integrators, first and second weighted summers, first and second DACs, a quantizer, and a lowpass digital filter. An input of the sampling circuit is connected to an output of the lowpass analog filter. A first input of the first integrator is connected to an output of the sampling circuit. First, second, and third inputs of the first weighted summer are respectively connected to an output of the first integrator, an output of the second DAC, and the output of the sampling circuit. An input of the second integrator is connected to an output of the first weighted summer. An input of the second weighted summer is connected to an output of the second integrator. An input of the quantizer is connected to an output of the second weighted summer. Inputs of the first and second DACs are connected to respective outputs of the quantizer. An output of the first DAC is connected to a second input of the first integrator. A second input of the first integrator and a third input of the first weighted summer are analog signal inputs.

DETAILED DESCRIPTION

Some ADCs use a CTDSM to convert an analog signal into a digital signal. A CTDSM includes a delta block that receives the analog signal, a sigma block, a quantizer, and a feedback path from the quantizer to the delta block via a primary (first) digital-to-analog converter (DAC) that provides a feedback signal. The delta block provides a signal to the sigma block that is responsive to a differential between the analog signal and the feedback signal. The sigma block integrates (sums over time) the signals it receives from the delta block. The resulting integrated signal(s) are weighted to balance signal contributions, and the weighted results are provided to the quantizer to generate an output signal of the CTDSM.

A complexity of the sigma block is related to an order of the modulator. In some examples, a higher order (more complex) modulator enables a higher resolution (or precision) output signal, at the cost of a certain amount of reliability of the stability of the modulator. In some examples, a finite impulse response (FIR) filter, feeding the primary DAC as part of the feedback loop, further enhances a resolution of the CTDSM during nominal operation, at an additional cost of reliability of the stability of the modulator.

Certain changes in input signal amplitude may cause the CTDSM to saturate. In a saturation condition, certain internal signals of the CTDSM oscillate between a maximum level and a minimum level, preventing accurate operation of the CTDSM. In some examples, a high frequency, low amplitude change in the input signal cause the CTDSM to saturate or enter another unstable condition. In some examples, a change resulting in the CTDSM receiving a signal with amplitude equal to or greater than a maximum signal amplitude (MSA) that the CTDSM is designed to process, regardless of change frequency, causes saturation or another unstable condition. Unstable conditions of the CTDSM, including saturation, are also referred to herein as instability conditions.

The instability condition can be detected by comparing signal levels at different points within the CTDSM to different corresponding thresholds. These different internal signals may be selected so that different causes of saturation or other instability are detected, for example, high frequency, lower amplitude changes in input signals, or large amplitude (or large amplitude changes in) input signals.

When a saturation or other instability condition is detected, the CTDSM downshifts its modulator order, so that the CTDSM uses a simpler sigma block. In the simplified configuration, the CTDSM uses a second DAC that enables a smaller feedback loop (including fewer components in the loop) that feeds the simpler sigma block, avoiding an output signal from the (potentially stability-reducing) FIR filter. Reducing the modulator order and not including the FIR filter output signal within the CTDSM output signal path facilitates stabilizing the CTDSM. Meanwhile, the inputs of the FIR filter and the primary DAC continue to receive output signals from the quantizer, enabling the FIR filter and the primary DAC to continue to be updated. The FIR filter and the primary DAC being updated during downshifted operation enables a smooth return to nominal operation once the CTDSM has been stabilized.

In some examples, the CTDSM returns to nominal operation via an additional mode that is intermediate between the downshifted sigma block mode and the nominal, more complex sigma block mode. In the intermediate state, the CTDSM uses a sigma block of intermediate complexity, and uses the original feedback path via the FIR filter and primary DAC. In some examples, using the intermediate mode during recovery enables a shallower recovery path, so that transients corresponding to departures from accurate CTDSM output signals are minimized on return to nominal operation of the CTDSM in the original, full complexity configuration.

Herein, some structures or signals that are distinct but related have reference numbers that use a [number][letter] format, such as switches228a,228b, and228c. In some examples, these structures or signals are referred to generally, in the singular or as a group, using the [number] and without the [letter], such as the switches228. Also, the same reference numbers or other reference designators are used in the drawings to designate features that are related structurally and/or functionally.

FIG.1Ais a functional block diagram of an example system100that includes an ADC104with a CTDSM112controlled by an instability recovery circuit114. The system100also includes an analog input102, a digital signal processing circuit106, a DAC108, and an analog output110. In some examples, the analog input102is or includes an audio device such as a microphone or a memory circuit, or a temperature, pressure, force, voltage, current, or other sensor, with an analog output that provides an input signal to the ADC104. The ADC104includes a clock115that provides a clock signal. In some examples, the digital signal processing block106includes a processor circuit such as a central processing unit (CPU), a digital signal processor (DSP), or a microcontroller unit (MCU). In some examples, the analog input102or the analog output110includes an amplifier, such as a class D amplifier.

In some examples, the CTDSM112and the instability recovery circuit114are fabricated on an integrated circuit (IC). In some examples, the ADC104is fabricated on the IC. In some examples, the IC also includes the digital signal processing circuit106and/or the DAC108.

A CTDSM112enables sampling of analog signals at a first frequency, which are converted into relatively high resolution digital signals at a second frequency that is lower than the first frequency. This process uses a relatively low precision ADC, which is enabled to operate as a relatively high precision ADC using a combination of oversampling and noise shaping to move quantization noise out of a signal band, e.g., a bandwidth of the CTDSM112, into higher frequencies. The higher frequency noise can be filtered, leaving a signal with an elevated signal-to-noise ratio (SNR), and accordingly an elevated resolution.

In some examples, the designed gain of a CTDSM112, determined by a signal transfer function (STF) of the CTDSM112, is a constant, such as one. In some examples, an ADC converts an analog signal into a digital signal representing the same information, such as frequency and amplitude. In some examples, certain types of input signals, such as a step input, can cause instability in an output signal of the CTDSM112. A step input is a relatively large change in input amplitude in a relatively short amount of time, which can alternatively be expressed as a large change in input amplitude at a high frequency. In some examples, the meaning of a relatively large change is responsive to the duration over which the input signal amplitude changes. At sufficiently high frequencies, or equivalently over a sufficiently short amount of time, a step input capable of causing instability in an output signal of the CTDSM112can be very small compared to the MSA of the CTDSM112.

In some examples, instability in the output signal of the CTDSM112corresponds to the CTDSM112saturating. Saturation corresponds to relatively large transient overshoots in an output signal of the CTDSM112. Accordingly, instability in the output signal of the CTDSM112can correspond to the output signal of the CTDSM112departing from the designed gain of the CTDSM112. In some examples, a transfer function of the CTDSM112leads to higher gain at higher frequencies. The instability recovery circuit114controls the CTDSM112to reliably recover from an unstable condition, such as saturation, to return to accurate, stable function. The CTDSM112is further described with respect toFIG.1Band subsequent figures.

FIG.1Bis a functional block diagram of an example of the ADC104ofFIG.1A. The ADC104includes a lowpass analog filter116, an oversampling circuit118, the CTDSM112, the instability recovery circuit114, and a lowpass digital filter120. The CTDSM112includes a delta (Δ) block122, a sigma (Σ) block124, a sampling quantizer126, and a feedback DAC128. In some examples, the sampling quantizer126is implemented using a relatively low resolution ADC, such as a 1-bit DAC, a 5-bit DAC, or a 6-bit DAC.

An output of the lowpass analog filter116is connected to an input of the oversampling circuit118. An output of the oversampling circuit118is connected to a noninverting input of the delta block122. An output of the delta block122is connected to an input of the sigma block124. An output of the sigma block124is connected to an input of the sampling quantizer126. An output of the sampling quantizer126is connected to an input of the lowpass digital filter120and an input of the feedback DAC128. An output of the feedback DAC128is connected to an inverting input of the delta block122. The CTDSM112is communicatively connected with the instability recovery circuit114. An output of the lowpass digital filter120provides a digital output signal (OUT) of the ADC104. Accordingly, the CTDSM112performs analog-to-digital delta-sigma modulation on a filtered, oversampled analog signal provided by the oversampling circuit118.

The feedback DAC128provides negative feedback. The delta block122provides a differential output signal responsive to this negative feedback to continuously correct for quantization errors, and to move quantization noise to frequencies that are significantly higher than the bandwidth of the signal received from the oversampling circuit118. Accordingly, quantization noise is moved to sufficiently high frequencies for the lowpass digital filter120to filter out corresponding high-frequency noise. In some examples, the delta block122encodes information regarding the change in the input signal.

In some examples, the sigma block124accumulates the output signal of the delta block122, so that it integrates the difference between the noninverting and inverting inputs to the delta block122. Accordingly, that accumulation is responsive to a difference between the input signal based on the analog input102and the output signal of the sampling quantizer126. In some examples, the sigma block124encodes information regarding the amplitude of the input signal into the signal provided to the sampling quantizer126.

The lowpass digital filter120demodulates the output signal of the sampling quantizer126, providing a relatively high bit resolution digital output signal at a sampling frequency lower than the sampling frequency of the oversampling circuit118. An example sampling frequency of the oversampling circuit118is 64 times a sampling frequency of the sampling quantizer126. An example sampling frequency of the sampling quantizer126is 3 megahertz (MHz). An increase in bit resolution of the output signal of the lowpass digital filter120over the output signal of the sampling quantizer126is related in magnitude to the decrease in sampling frequency from the output signal of the oversampling circuit118to the output signal of the sampling quantizer126. In some examples, effects of the lowpass digital filter120include time averaging, which enables high accuracy in output amplitude.

Accordingly, oversampling by the oversampling circuit118, followed by decimation by the lowpass digital filter120, enables benefits that may include one or more of: higher accuracy in time, use of a higher linearity ADC as a sampling quantizer126, noise shaping by moving noise to higher frequencies that can be filtered by the lowpass digital filter120, and/or a reduced steepness requirement for analog lowpass anti-aliasing filters. Note that in some examples, a relatively lower bit resolution ADC is more linear than a relatively higher bit resolution ADC.

In some examples, a bandwidth of an input signal of the ADC104corresponds to an audio bandwidth, such as 20 Hz to 20 kHz. Accordingly, an example cut-off frequency of the lowpass analog filter116is 20 kHz, and an example cut-off frequency of the lowpass digital filter120is also 20 KHz.

In some examples, an oversampled ADC, such as the ADC104, uses a relatively high sampling rate compared to a Nyquist rate (or Nyquist frequency). The Nyquist rate of a signal is twice the bandwidth of the signal. A CTDSM112can be used to spread quantization noise over a bandwidth responsive to the sampling rate of the ADC, while retaining signal content within a selected bandwidth. This enables the CTDSM112to provide relatively high output signal resolution using a relatively low bit ADC in the sampling quantizer126. The CTDSM112enables this high output signal resolution by sampling the input signal at a high sampling rate compared to the Nyquist rate, and spreading quantization noise of the sampling quantizer126over a frequency range that is relatively broad compared to a bandwidth of the input signal. Quantization noise outside the selected bandwidth can be filtered, reducing noise, and accordingly increasing a signal-to-quantization-noise ratio (SQNR). In some examples, multiplying the sampling rate of the oversampling circuit118by four improves the SQNR by six decibels (dB), which corresponds to an increase in resolution of the ADC104of one bit. Noise shaping by the CTDSM112provides additional resolution improvement, as further described below.

FIG.2Ais a functional block and circuit diagram of an example of a first operating state200of the CTDSM112and instability recovery circuit114ofFIGS.1A and1B. In some examples, in the first operating state200, all of the functional blocks of the CTDSM112are active. In certain other operating states, as further described with respect toFIGS.3through5, certain functional blocks of the CTDSM112are made inactive or at least partially inactive by the instability recovery circuit114to increase stability of the CTDSM112, and/or to provide a recovery path facilitating stable initial operation on return to full, nominal functionality.

The CTDSM112includes a first integrator (integrator1)202, a second integrator (integrator2)204, a third integrator (integrator3)206, a first weighted summer (weighted sum1)208, a fourth integrator (integrator4)210, a second weighted summer (weighted sum2)212, a quantizer214, a primary finite impulse response (FIR) filter216, a primary DAC218, a sync/recovery DAC220, a compensation FIR filter222, a compensation DAC224, a first resistor226aand a second resistor226b, a recovery switch227, and a first switch228a, a second switch228b, and a third switch228c. The instability recovery circuit114includes a first instability detector (instability detector1)230, a second instability detector (instability detector2)232, and a recovery circuit233. In some examples, the first and second instability detectors230and232are comparators. In some examples, the quantizer214corresponds to the sampling quantizer126ofFIG.1B. In some examples, the instability recovery circuit114or the recovery circuit233can be described as a control circuit of the CTDSM112.

The sync/recovery DAC220is so named because it is used to compensate for loop delay, accordingly, to perform synchronization; and as part of a process by which the CTDSM112recovers from instability. These functions of the sync/recovery DAC220are further described below.

The recovery circuit233includes a memory234. In some examples, the memory234stores one or more of instructions for execution by the recovery circuit233, instability detector230and232threshold levels, timing values, weight coefficients for the weighted summers208and212, or other parameters for the recovery circuit233to use to control operation of the CTDSM112. In some examples, timing values correspond to timing for transitions between operating states such as first, second, and third operating states200,300, and400(seeFIGS.2through5). In some examples, timing values correspond to timing for changing other functions of the CTDSM112, such as by releasing a reset signal of a latch242(seeFIG.2C).

A first input terminal236areceives a plus input signal INP, and a second input terminal236breceives a minus input signal INM. For example, INP and INM are plus and minus components of a differential input signal. In some examples, INP and INM are provided by a signal sampling circuit of the ADC104, such as the oversampling circuit118. The signal sampling circuit is used to oversample an analog input signal, such as an input signal received from the analog input102, in some examples via a filter such as the lowpass analog filter116.

The first input terminal236ais connected to a first terminal of the first resistor226aand to a first input of the first weighted summer208. The second input terminal236bis connected to a first terminal of the second resistor226band to a second input of the first weighted summer208. A second terminal of the first resistor226ais connected to a first terminal of the recovery switch227, a first input of the first integrator202, and a first output of the primary DAC218. A second terminal of the second resistor226bis connected to a second terminal of the recovery switch227, a second input of the first integrator202, and a second output of the primary DAC218.

An output of the first integrator202is connected to an input of the second integrator204, a third input of the first weighted summer208, and a first input of the first instability detector230. An output of the second integrator204is connected to an input of the third integrator206and a fourth input of the first weighted summer208. An output of the third integrator206is connected to a fifth input of the first weighted summer208.

Virtual grounds of the first, second, and third integrators202,204, and206may be connected via outputs of the respective integrators202,204, and206, depending on a switching state of respective ones of the switches228. A virtual ground of the first integrator202is connected to a first terminal of the first switch228a, a virtual ground of the second integrator204is connected to a first terminal of the second switch228b, and a virtual ground of the third integrator206is connected to a first terminal of the third switch228c. The second terminal of each of the switches228is connected to a node that receives a RESET signal. Accordingly, closing any of the switches228puts the respective integrator(s)202,204, or206corresponding to the closed switch(es)228a,228b, or228cinto a reset state. In the reset state, a zero signal, such as a zero voltage and/or zero current signal, is provided at the output(s) of the corresponding integrator(s)202,204, or206. A zero signal corresponds to a signal with will not affect a sum accumulated by an integrator202,204, or206or an output signal of a weighted summer208or212. In some examples, the switches228are transistors, and connections from the recovery circuit233to the switches228correspond to connections to respective gates or other control terminals of the switches228.

Alternatively, the outputs and corresponding inputs of the first, second, and third integrators202,204, and206are differential outputs and inputs, and the inputs of the first weighted summer208are differential inputs. The first terminal of the first switch228ais connected to a first differential output of the first integrator202and a first differential input of the second integrator202, and a second terminal of the first switch228ais connected to a second differential output of the first integrator202and a second differential input of the second integrator204. The first terminal of the second switch228bis connected to a first differential output of the second integrator204and a first differential input of the third integrator206, and a second terminal of the second switch228bis connected to a second differential output of the second integrator204and a second differential input of the third integrator206. And the first terminal of the third switch228cis connected to a first differential output of the third integrator206and a first differential input of the first weighted summer208, and a second terminal of the third switch228cis connected to a third differential output of the first integrator206and a second differential input of the first weighted summer208. Accordingly (as described above), closing any of the switches228puts the respective integrator(s)202,204, or206corresponding to the closed switch(es)228a,228b, or228cinto the reset state, in which a zero signal is provided at the output(s) of the corresponding integrator(s)202,204, or206.

An output of the first weighted summer208is connected to an input of the fourth integrator210. An output of the fourth integrator210is connected to a first input of the second weighted summer212and a first input of the second instability detector232. An output of the second weighted summer212is connected to an input of the quantizer214. An output of the quantizer214is connected to an input of the primary FIR filter216, an input of the sync/recovery DAC220, an input of the compensation FIR filter222, and a first input of the recovery circuit233.

An output of the primary FIR filter216is connected to an input of the primary DAC218. An output of the compensation FIR filter222is connected to an input of the compensation DAC224. An output of the compensation DAC224is connected to a second input of the second weighted summer212. An output of the sync/recovery DAC220is connected to a sixth input of the first weighted summer208.

An output of the first instability detector230is connected to a second input of the recovery circuit233, and an output of the second instability detector232is connected to a third input of the recovery circuit233. A first output of the recovery circuit233is connected to a second input of the first instability detector230, and a second output of the recovery circuit233is connected to a second input of the second instability detector232.

A third output of the recovery circuit233corresponds to an output of the instability recovery circuit114. The third output of the recovery circuit233is connected to a control input of the CTDSM112. In some examples, the third output of the recovery circuit233is a bus that is multiple lines wide, and the control input of the CTDSM112accordingly corresponds to multiple input lines. In some examples, the control input of the CTDSM112is connected to control terminals or control inputs of the recovery switch227, the first switch228a, the second switch228b, the third switch228c, the first weighted summer208, the second weighted summer212, the sync/recovery DAC220, the compensation FIR filter222, and the compensation DAC224. For clarity, these connections from the control input of the CTDSM112to control terminals or control inputs of components of the CTDSM112are shown inFIG.2B, and not inFIG.2A. During operation in the first operating state200, the recovery circuit233controls the recovery switch227and each of the switches228to be open (nonconductive).

Connection of the inputs of the first integrator to the resistors226and to the outputs of the primary DAC218acts as the delta block122for the CTDSM112as shown inFIG.2A. The first and second resistors226convert the signals received by the input terminals236into respective currents. In some examples, the outputs of the primary DAC218are differential outputs that sink respective currents dependent on the output signal of the primary FIR filter216, which is dependent on the output signal of the quantizer214. Accordingly, currents received by respective inputs of the first integrator202are responsive to a difference between currents provided by the resistors226and currents provided by (sunk) by the primary DAC218. This enables the first integrator202to process quantization error, which is (or is related to) the difference between the input signal and the feedback signal, accordingly, the input signals of the first integrator202.

Some components described with respect to the first operating state200ofFIG.2Aare similar in function and/or structure to components described with respect to the CTDSM112ofFIG.1B. In some examples, in the first operating state200of the CTDSM112and instability recovery circuit114ofFIG.1, the connections between the first and second outputs of the primary DAC218and the first and second inputs of the first integrator202, respectively, correspond to the delta block122. The first, second, and third integrators202,204, and206, the first weighted summer208, the fourth integrator210, and the second weighted summer212correspond to the sigma block124. The quantizer214corresponds to the sampling quantizer126. And the feedback DAC128corresponds to the primary FIR filter216with the primary DAC218.

During operation in the first operating state200, the sync/recovery DAC220is used to compensate for loop delay introduced by the first, second, and third integrators202,204, and206, such as loop delay related to resistor-capacitor (RC) circuitry within the first, second, and third integrators202,204, and206. Similarly, during operation in the first operating state200, the compensation FIR filter222and compensation DAC224are used to compensate for loop delay introduced by the fourth integrator210, such as loop delay related to resistor-capacitor (RC) circuitry within the fourth integrator210. Accordingly, the sync/recovery DAC220, compensation FIR filter222, and compensation DAC224are used to achieve a designed noise transfer function (NTF) of the CTDSM112.

In some examples, precision, or bit resolution, of an ADC is proportional to the error, or noise, in the output signal of the ADC. In some examples, the bit resolution of an ADC is proportional to the SNR expressed in dB. In an example, a six bit ADC has a 36 dB SNR, and a sixteen bit ADC has a 96 dB SNR.

As described above, the quantizer214is or includes an ADC. The noise in the output signal of the quantizer214is quantization noise. In some examples, quantization noise is a type of white noise. White noise, also called flat noise, is a noise without a preferred frequency. Such noise includes low frequency content, and can be described as not changing over time. Constant noise can be described as an offset applied to the output signal of the quantizer214. The feedback DAC128, delta block122, and sigma block124together determine an input signal that controls the sampling quantizer126to produce an output signal component equal to an inverse (negative) of the offset (an inverse offset). For example, if the offset equals one, then ideally, the inverse offset equals negative one. Accordingly, the inverse offset can be determined to adjust the input signal of the quantizer214so that the low frequency noise in the output signal of the quantizer214is reduced or eliminated.

Accordingly, noise is reduced by the loop filter (the feedback loop of the CTDSM112) and by the lowpass digital filter120removing high frequency signal components. This improves SNR, which enables the lowpass digital filter120to further increase the resolution of the ADC104by (or while) reducing the sample rate of the final output signal of the ADC104. Quantization noise can be described as an additive noise source added to the output signal of the CTDSM112. An additive noise source to output transfer function, which is related to the inverse of the NTF of the CTDSM112, can be used to describe noise within the signal band of the CTDSM112as being reduced by the total gain of the integrators (202,204,206, and210, corresponding to the sigma block124). The reduced noise amplitude is transferred to higher frequencies (frequencies outside the signal band). This can be referred to as noise shaping. In an example, a sampling rate of the oversampling circuit118is 64 samples per second, the sigma block124includes four integrators, and the resolution of the ADC of the quantizer214is six bits, and the output signal sample rate of the ADC104is one sample per second and the resolution of the ADC104is sixteen bits.

The integrators202,204,206,210are called integrators because they maintain a running sum of the input signal. The integrators202,204,206,210can be described as gain blocks, providing high finite gain at low frequencies. In an example, the integrators202,204,206,210can be implemented as analog components, such as capacitors. In another example, the integrators202,204,206,210can be implemented as digital components, such as a summer with a memory to store the running sum. The contributions of the output signals of the integrators202,204,206, and210, the sync/recovery DAC220, the compensation FIR filter222, and the compensation DAC224to the input signal of the quantizer214are balanced by respective weighted summers, accordingly, the first and second weighted summers208and212.

Closing the recovery switch227causes a zero signal or null signal to be provided to the first integrator202. In some examples, providing a null signal to the first integrator202(responsive to the recovery switch227closing), the second integrator204(responsive to the first switch228aclosing), or the third integrator206(responsive to the second switch228bclosing) controls the respective integrator202,204, or206receiving the null signal to reset the running sum maintained by that respective integrator202,204, or206.

The number of integrators in a modulator corresponds to the order of the modulator. Accordingly, in the first operating state200, the CTDSM112operates as a fourth order modulator. The more integrators are present in a modulator, the more gain is available to the modulator. In some examples, integrators have high gain at low frequency and low gain at high frequency, so that signal receives more gain than quantization noise. Accordingly, an increased number of integrators can be used to enable more effective noise shaping by shifting quantization noise outside the selected bandwidth (the signal band) so that a greater proportion of quantization noise can be filtered by the lowpass digital filter120. In some examples, this can improve resolution beyond what can be achieved by oversampling without noise shaping using integrators. Accordingly, noise shaping using both integrators and oversampling enables improved SNR, and therefore a higher resolution ADC104output signal for a same sampling rate of the oversampling circuit118. In some examples, an increased number of integrators corresponds to an increased delay from a signal received at the input terminals236to the output signal of the quantizer214, which may reduce stability of the CTDSM112.

The primary FIR filter216reduces clock jitter sensitivity, improves the linearity of the signal response of the primary DAC218to reduce error in the feedback path, and filters out high frequency signal components. The clock115is used for, for example, sampling the input signal in the oversampling circuit118, providing an output signal of the sigma block124on a first clock signal edge (such as a rising edge) within a period of the clock signal, and sampling the output signal of the sigma block124using the sampling quantizer126on a second clock edge (such as a falling edge) within the period of the clock signal. In some examples, class D amplifiers, which are switching amplifiers, produce high frequency noise at particular modulator frequencies. In some examples, class D amplifiers are used in audio-related applications.

FIR filters, such as the primary FIR filter216or the compensation FIR filter222, can be described by a number of taps, corresponding to a number of samples to which an FIR filter output signal is responsive. Taps can also be described as zeroes in an STR of the FIR filter. In some examples, increasing the number of taps of a FIR filter improves the linearity and noise-filtering effects of the FIR filter, but can also increase delay and amplitude of the FIR filter output signal, reducing overall stability of the modulator. In some examples, the primary FIR filter216and the compensation FIR filter222are lowpass digital filters.

In some examples, such as at high input signal frequencies, increased delay and amplitude of the primary FIR filter output signal can lead to peaking of the STR of the primary FIR filter216. Responsively, the CTDSM112may become unstable and/or have a non-unitary gain. A CTDSM112may be more prone to these effects as the number of taps in FIR filters of the CTDSM112(such as the primary and compensation FIR filters216and222) increases. In some examples, the CTDSM112becomes unstable responsive to a step input or an input signal exceeding a designed MSA of the CTDSM112.

In some examples, instability of the CTDSM112corresponds to the CTDSM112saturating. In a saturated condition, the primary DAC218oscillates between providing a voltage signal at a maximum level, such as a level corresponding to a voltage supply or other high reference voltage, and providing the voltage signal at a minimum level, such as a level corresponding to a ground or other low reference voltage.

The first and second instability detectors230and232are used to detect instability in the CTDSM112. The recovery circuit233provides threshold voltages to respective second inputs of the first and second instability detectors230and232. In the first operating state200, a first threshold voltage is provided to the first instability detector230and a second threshold voltage is provided to the second instability detector232.

The first instability detector230compares the output signal of the first integrator202to the first threshold voltage, and the second instability detector232compares the output signal of the fourth integrator210to the second threshold voltage. Accordingly, the first instability detector230is responsive to a high frequency change in input voltage (such as a step input), which may have a lower amplitude than an MSA of the CTDSM112. The second instability detector232is responsive to a high amplitude change in the input signal, such as a lower frequency change in input voltage to a voltage near or greater than the MSA of the CTDSM112. As described above, in some examples, at a sufficiently high frequency of change of input signal level, a step input that is much smaller than the MSA of the CTDSM112may control a signal level of the output signal of the first integrator202to exceed the first threshold.

If the output signal of the first integrator202is greater than the first threshold voltage, or the output signal of the fourth integrator210is greater than the second threshold voltage, then the recovery circuit233controls the CTDSM112to transition to a second operating state300. The second operating state300is described with respect toFIG.3. Accordingly, the first threshold or second threshold voltage being exceeded, as detected by the first or second instability detector230or232(respectively), indicates a saturation condition or other unstable condition of the CTDSM112. Operation in the second operating state300enables the CTDSM112to recover from the unstable condition. Once the CTDSM112has recovered from the unstable condition, the recovery circuit233controls the CTDSM112to return to the first operating state200, either directly or via a third operating state400. The third operating state400is described with respect toFIG.4.

In some examples, the first threshold voltage and the second threshold voltage each correspond to two voltages, accordingly, differential voltages. In an example, the first threshold voltages are VDDminus 200 millivolts and VSSplus 200 millivolts, and the second threshold voltages are VDDminus 200 millivolts and VSSplus 200 millivolts.

FIG.2Bis a functional block and circuit diagram of an example of the control connections from the recovery circuit233to various components of the CTDSM112ofFIG.2A. A control output of the recovery circuit233is connected, via a bus235, to a control terminal of the recovery switch227, a control terminal of the first switch228a, a control terminal of the second switch228b, a control terminal of the third switch228c, a control input of the first weighted summer208, a control input of the second weighted summer212, a control input of the sync/recovery DAC220, a control input of the compensation FIR filter222, and a control input of the compensation DAC224. In some examples, the recovery circuit233controls additional or different components than described herein. In some examples, the recovery circuit233controls additional or different component functions than described herein.

The recovery circuit233controls whether the recovery switch227is open or closed, and whether each of the switches228is open or closed. In some examples, closing one of the switches228controls the RESET signal to be provided to a respective control input of the first, second, or third integrator202,204, or206. A respective virtual ground of the first, second, or third integrator202,204, or206accordingly receives a signal that controls an output of the first, second, or third integrator202,204, or206to provide a zero voltage signal or other null signal. As described above, in some examples, the recovery circuit233controls a different mechanism to control selected ones of the first, second, and third integrators202,204, and206to selectably provide a null signal or a normal operation signal.

The recovery circuit233also controls the compensation FIR filter222and compensation DAC224to selectably disconnect them from the CTDSM112loop or, in some examples, to provide a null signal. In subsequent figures, functional blocks that are controlled by the recovery circuit233to provide a null signal are indicated by dotted-line boxes. Corresponding communication lines carrying the null signals are indicated by dotted lines.

The recovery circuit233controls weights used by the first weighted summer208to determine an output signal responsive to signals provided by the input terminals236, the first, second, and third integrators202,204, and206, and the sync/recovery DAC220. The recovery circuit233controls weights used by the second weighted summer212to determine an output signal responsive to signals provided by the fourth integrator214and the compensation DAC224. Note that the output signal of the fourth integrator214is responsive to the output signal of the first weighted summer208.

FIG.2Cis a functional block diagram of another example of the CTDSM112and instability recovery circuit114ofFIGS.1A and1B. In the example ofFIG.2C, the instability recovery circuit includes a latch242. The output of the first instability detector230is connected to a first data input of the latch242, and the output of the second instability detector232is connected to a second data input of the latch242. A data output of the latch242is connected to an input of the recovery circuit233. A reset output of the recovery circuit233is connected to a reset input of the latch242.

The latch242stores a logic one in response to either the first or second instability detector230or232detecting an instability condition. The latch242communicates this logic one to the recovery circuit233. In response, the recovery circuit233controls the CTDSM112to transition to the second operating state300. The recovery circuit233controls the CTDSM112to remain in the second operating state300until the recovery circuit233determines, in response to the quantizer214output signal, that the CTDSM112has returned from saturation to a normal operating range.

In response to detecting the normal operating range, the recovery circuit233applies and holds (continues to apply) a reset signal at the reset output to the latch242. This controls the latch242to reset to storing a logic zero, and forces the latch242to continue to store the logic zero. Accordingly, the instability detectors230and232are unable to communicate a detected instability condition to the recovery circuit233until the recovery circuit233releases (stops transmitting) the reset signal.

The recovery circuit233continues to hold the reset signal at the reset output to the latch242until the CTDSM112returns to nominal operation in the first operating state200and a predetermined amount of time passes. In some examples, a condition other than time lapse is used to determine release of the reset signal. The recovery circuit233then releases the reset signal at the reset output to the latch242, which enables the first and second instability detectors230and232to return to detecting a saturation or other unstable condition.

FIG.3is a functional block and circuit diagram of an example of the second operating state300of the CTDSM112and instability recovery circuit114ofFIGS.1A and1B. In the second operating state300, the recovery circuit233controls the first, second, and third switches228to close, thereby controlling the first, second, and third integrators202,204, and206to provide respective null signals. This leaves the output signal of the fourth integrator210to determine the input signal of the quantizer214. Accordingly, in the second operating state300, the CTDSM112operates as a first order modulator. In some examples, an output signal closely follows an input signal in first order systems, so that first order systems are inherently stable.

Responsive to the first integrator202providing a null signal, the primary FIR filter216and primary DAC218have no effect on the output signal of the quantizer214. This is because the signal path of the output of the primary DAC218goes to the first integrator202, which, as described, is limited to providing a null output signal while the CTDSM112is in the second operating state300.

In the second operating state300, the sync/recovery DAC220performs a function analogous in some respects to (in some examples, performs the function of) the feedback DAC128, and the first weighted summer208acts as the delta block122. The recovery circuit233adjusts the weights in the first weighted summer208and/or activates a return to zero mode of the sync/recovery DAC220(described below) to enable this functionality. Accordingly, in the second operating state300, the output signal of the first weighted summer208is responsive to (non-null) signals provided by the input terminals236and the sync/recovery DAC220. In some examples, the sync/recovery DAC220provides a negative feedback loop for the CTDSM112at a high sampling rate. Accordingly, the sampling rate of the oversampling circuit118is not lowered during operation in the second operating state300.

In the second operating state300, the fourth integrator210and the second weighted summer212act as the sigma block124. The recovery circuit233adjusts the weights in the second weighted summer212to enable this functionality.

In some examples, in the first operating state200, the sync/recovery DAC220operates in a non-return to zero (NRZ) mode, and in the second operating state300, the sync/recovery DAC220operates in a return to zero (RZ) mode. In the NRZ mode, the sync/recovery DAC220transitions, on a corresponding clock edge (such as a rising or falling clock edge), from an output signal corresponding to an old input signal received by the sync/recovery DAC220to an output signal corresponding to a new input signal received by the sync/recovery DAC220, without returning to a zero signal between the old and new output signals.

In the RZ mode, the sync/recovery DAC220provides an output signal corresponding to the input signal of the sync/recovery DAC220for half of each clock cycle, such as following a rising clock edge, and returns to providing a zero signal for half of each clock cycle, such as following a falling clock edge. The RZ mode adds predictability to the output signal of the sync/recovery DAC220and reduces the weight of the output signal of the sync/recovery DAC220by one-half, as seen by the input of the quantizer214. The RZ mode adds predictability because the sync/recovery DAC220has a known output signal for half of each clock cycle. Also, switching to RZ mode provides a convenient method of retuning loop coefficients corresponding to the sync/recovery DAC220so that a designed NTF can be achieved, with designed resolution and precision, during operation in the second operating state300.

As described above, to increase stability of the CTDSM112while operating in the second operating state300, the recovery circuit233controls the compensation FIR filter222and the compensation DAC224to provide a null signal. Accordingly, in the second operating state300, the compensation FIR filter222does not affect an input signal of the quantizer214. Also, as described above, because the first integrator202provides a null output signal, the primary FIR filter216does not affect input to the quantizer214. This also increases stability of the CTDSM112.

In the second operating state300, input signals of the primary FIR filter216continue to be updated by the output signal of the quantizer214. Updating the input signals of the primary FIR filter216updates the internal multi-sample filter components of the primary FIR filter216. Accordingly, use of the sync/recovery DAC220and the first weighted summer208to provide a shortened loop-filter for the CTDSM112avoids instability related to the output signal of the primary FIR filter216without bypassing or suppressing the input of the primary FIR filter216.

Stability impact from this updating is avoided because the first integrator202receives a null signal corresponding to the recovery switch227being closed, and provides a null signal corresponding to the first switch228abeing closed. The recovery switch227being closed also enables the signal path culminating with the primary FIR filter216and primary DAC218to act as a closed loop, so that the primary FIR filter216and primary DAC218can update without interference from the differential input signal, which is shorted by the recovery switch227. This enables the primary FIR filter216to continue to be updated while the CTDSM112is in the second operating state300.

The closed shorting switches, switches227and228a, also enable the primary FIR filter216and primary DAC218to accurately determine the output signal. Accurate determination of the output signal enables initialization of the primary FIR filter216and primary DAC218to provide accurate feedback on return to nominal operation (the first operating state200). Accurate feedback promotes stable operation. Further, switches227and228abeing closed keeps the primary FIR filter216and primary DAC218out of the CTDSM112feedback loop, so that they do not erroneously affect operation in the second operating state300. In some examples, the second operating state300is referred to as a signal estimation mode in response to the accurate continued updating of the primary FIR filter216and primary DAC218.

The primary FIR filter216and primary DAC218can be kept out of the CTDSM112feedback loop because the sync/recovery DAC220provides a negative feedback loop to enable continued operation of the CTDSM112during the second operating state300. The negative feedback loop via the sync/recovery DAC220enables shaping of the quantization noise by moving quantization noise from the signal band to higher frequencies (such as frequencies outside a range allowed by the lowpass digital filter120). As described above, oversampling enables further accuracy improvement.

As described, continued updating of the primary FIR filter216during operation in the second operating state300enables continued stable operation of the CTDSM112while the modulator recovers from operation as a first order modulator in the second operating state300to return to operation as a fourth order modulator in the first operating state200. This avoids a period of instability that could be caused if inputs of the primary FIR filter216and/or primary DAC218were bypassed during recovery, and this bypass ended after return of the CTDSM112to normal operation.

Recall that the first instability detector230receives a null input signal, because the first integrator202provides a null output signal, during operation in the second operating state300. In some examples, the CTDSM112exits the second operating state300after a voltage of the output signal of the fourth integrator210is less than the second threshold voltage, indicating that the CTDSM112has recovered from the saturation or other unstable condition. In some examples, such as with respect to the instability recovery circuit114ofFIG.2C, the recovery circuit233ignores the second instability detector232while the latch242is set and while the latch242reset signal is applied. In some examples, this corresponds to behavior of the instability recovery circuit ofFIG.2C. In some examples, the recovery circuit233ignores the first instability detector230and/or the second instability detector232from detection of the saturation condition until a predetermined time after return to the first operating state200. In examples in which the recovery circuit233ignores the second instability detector232, the recovery circuit233determines when the output signal of the quantizer214returns to a normal operating range, indicating the saturation or other unstable condition has ended. The recovery circuit233controls the CTDSM112to exit the second operating state300in response to this detected end of the saturation or other unstable condition.

In some examples, the recovery circuit233does not perform comparisons to determine an end of the saturation or other unstable condition until a selected amount of time has elapsed following entry into the second operating state300. In some examples, comparison by the second instability detector232is also or alternatively suspended until the condition is satisfied. In some examples, the amount of time that comparison by the recovery circuit233and/or the second instability detector232is suspended corresponds to a number of clock cycles. In some examples, other or additional criteria are used to determine when to exit the second operating state300. An example amount of time after transition to the second operating state300before the recovery circuit233starts to perform comparisons to determine a return to normal quantizer214output signal behavior is 25 microseconds.

In some examples, comparisons by the recovery circuit233to determine whether the CTDSM112has returned to stable operation include comparing an output signal of the quantizer214to maximum and minimum codes of the quantizer214. In an example, a maximum code equals 32 and a minimum code equals −32. If the output signal of the quantizer214is less than the maximum code and greater than the minimum code, then the recovery circuit233checks on subsequent clock cycles, such as for two or three subsequent clock cycles, to determine whether an absolute value of the output signal is decreasing, accordingly, recovering. If so, then the recovery circuit233controls the CTDSM112to transition to the third operating state400.

FIG.4is a functional block and circuit diagram of an example of the third operating state400of the CTDSM112and instability recovery circuit114ofFIGS.1A and1B. The third operating state400is an intermediate recovery state between the second operating state300and the first operating state200. The CTDSM112transitions from the second operating state300to the third operating state400to reduce an amount of change in transition(s) between operating states in a recovery path towards the first operating state200. Changes between operating states can give rise to instability. Accordingly, operation in the third operating state400controls and enables the CTDSM112to return to high performance, normal operation in the first operating state200with reduced risks, such as transient overshoots, in some examples, very small or no transient overshoots, in the OUT signal.

In the third operating state400, the recovery circuit233controls the recovery switch227, the first switch228a, and the second switch228bto open, thereby controlling the primary FIR filter216, the primary DAC218, the first integrator202, and the second integrator204to function normally. The recovery circuit233also controls the third switch228cto close, thereby controlling the third integrator206to continue to provide a null signal. The output signals of the first, second, and fourth integrators202,204, and210determine the input signal of the quantizer214. Accordingly, in the third operating state400, the CTDSM112operates as a third order modulator. The recovery circuit233also controls the compensation FIR filter222and compensation DAC224to operate normally while the CTDSM112is in the third operating state400. In some examples, normal operation of the compensation FIR filter222and compensation DAC224refers to them providing or being enabled to provide non-null feedback signals to the second weighted summer212.

The third operating state400is comparable to the first operating state200, except that the third integrator206continues to be controlled to provide a null signal, and the latch242remains in a reset state. Accordingly, the recovery circuit233adjusts the coefficients of the sync/recovery DAC220, such as by returning the sync/recovery DAC220to operation in NRZ mode. Also, the recovery circuit233adjusts the weights of the first and second weighted summer208and212, to enable stable function with a designed NTF. After a selected, e.g., predetermined, amount of time has elapsed after the CTDSM112has begun operating in the third operating state400, the CTDSM112transitions to operating in the first operating state200. An example of the selected time between the transition to the third operating state400and the transition to the first operating state200is 75 microseconds.

In some examples, the ADC104suspends providing an output signal responsive to the CTDSM112while the CTDSM112is in one or more of the second operating state300or the third operating state400. In some examples, the recovery circuit233suspends detecting instabilities in one or more of the second operating state300or the third operating state400, such as discussed above with respect to the latch242. In some examples, the ADC104resumes providing output signals responsive to the CTDSM112, and/or the recovery circuit233resumes detecting instabilities, after a selected, e.g., predetermined, amount of time has elapsed after the CTDSM112has resumed operating in the first operating state200. An example amount of time after the CTDSM112resumes operating in the first operating state200before the ADC104resumes providing an output signal and/or the recovery circuit233resumes detecting instabilities is 50 microseconds.

FIG.5is an example flow diagram representing a method or process500for recovery by the CTDSM112from an unstable condition. In block502, the recovery circuit233controls the CTDSM112to operate in the first operating state200. In block504, the first instability detector230compares a voltage of the output signal of the first integrator202to a first threshold voltage, and the second instability detector232compares a voltage of the output signal of the fourth integrator210to a second threshold voltage. These checks determine whether the CTDSM112is in an unstable condition, such as saturation.

If either threshold is exceeded, then in block506, the recovery engine233controls the CTDSM112to operate in the second operating state300for a first predetermined amount of time before proceeding to block508. Otherwise, if neither threshold is exceeded, return to block502. In some examples, during block504operation of the CTDSM112in the first operating state200, block504is performed on each clock cycle (such as each rising edge of a clock cycle), or with a different rate.

In block508, after the first predetermined amount of time has elapsed, the recovery engine233checks whether the voltage of the quantizer214output signal has returned to a normal operating range of the CTDSM112, while continuing to control the CTDSM112to operate in the second operating state300. This check corresponds to a determination whether the unstable condition has ended. If the voltage of the quantizer214output signal indicates that the CTDSM112has returned to normal, stable operation, then proceed to block510. Otherwise, repeat block508. This repetition can be performed on each clock cycle (such as each rising edge of a clock cycle), or with a different rate.

In block510, the recovery engine233controls the CTDSM112to operate in the third operating state400for a second predetermined amount of time. After the second predetermined time has elapsed, in block512, the recovery engine233controls the CTDSM112to operate in the first operating state200for a third predetermined amount of time. After the third predetermined amount of time has elapsed, return to block502, so that the CTDSM112can resume checking for the saturation condition in iterations of block504.

In some examples, circuits described herein, such as the CTDSM112or the instability recovery circuit114, can be implemented using a processor such as a CPU, DSP, or MCU.

In some examples, processes described herein are implemented using software, hardware, or a combination of software and hardware.

In some examples, the sigma block includes a number of integrators other than four.

In some examples, design tools and/or MATLAB or other analysis is used to determine weights used by the weighted summers208and212. In some examples, analysis and simulation are used to iteratively refine modulator design and/or weight allocation.

In some examples that do not include the primary FIR filter216(or other FIR filters), the CTDSM112becomes unstable responsive to a step input or a signal exceeding the MSA of the CTDSM112. Some example CTDSM designs include other variations on the CTDSM112described herein. The systems and processes described herein may also be applied to such variant CTDSM designs.

In some examples, the differential analog input corresponding to INP and INM, provided by the input terminals236, can be described as a first input of the first integrator202. In some examples, the differential outputs of the primary DAC218can be described as providing a second input of the first integrator202.

In some examples, the instability detectors230and232remain effective during the second and/or third operating state(s)300and/or400. In some such examples, threshold voltages are determined responsive to whether the CTDSM112is in the first operating state200or a different operating state.

In some examples, the recovery circuit233can change or select threshold voltages or other parameters stored in the memory234, such as in response to instructions from a user.

In some examples, the recovery circuit233controls a clock signal to which timing of signal processing by the sigma block124and of sampling by the sampling quantizer126are responsive.

In some examples, the operating states are referred to as modes of the CTDSM.

In some examples, an oversampling ratio equals a sampling frequency (fs) divided by two times the Nyquist frequency. In some examples, a CTDSM112provides an improvement in SQNR of (6N+3) dB with each doubling of the oversampling ratio, where N is the order of the modulator. In some examples, an oversampling rate is approximately 64 times a Nyquist frequency corresponding to an audio bandwidth, or approximately 64 times another sampling rate responsive to the audio bandwidth.

In this description, the term “and/or” (when used in a form such as A, B and/or C) refers to any combination or subset of A, B, C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A with B; (c) A with C; (f) B with C; and (g) A with B and with C. Also, as used herein, the phrase “at least one of A or B” (or “at least one of A and B”) refers to implementations including any of: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.