Embedded chip package, a chip package, and a method for manufacturing an embedded chip package

An embedded chip package is provided. The embedded chip package includes a plurality of chips; encapsulation material embedding the plurality of chips; at least one electrical redistribution layer electrically connected to the plurality of chips; and a common terminal connected to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal.

TECHNICAL FIELD

Various embodiments relate generally to an embedded chip package, a chip package, and a method for manufacturing an embedded chip package.

BACKGROUND

Sensors of today must be extensively tested and calibrated. Different levels of pressure, in combination with different temperatures may be applied to each pressure sensor component for testing. Complex measurements are also required, particularly if testing also includes movement, such as testing gyro sensors at different angles, or with different accelerations. These complex measurements may be required if pressure sensors are combined with acceleration sensors or gyro sensors, such as those used as tire pressure sensors. Current tests are extensive and expensive as test conditions are administered serially on individual components. Current testing standards allow for only very few components to be tested in parallel. Electrical contacting of the chip for testing also presents a complex challenge.

SUMMARY

Various embodiments provide an embedded chip package including: a plurality of chips; encapsulation material embedding the plurality of chips; at least one electrical redistribution layer electrically connected to the plurality of chips; and a common terminal connected to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal.

DETAILED DESCRIPTION

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration” or the like. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

The word “over” is used herein to describe forming a feature, e.g. a layer, “over” a side or surface, and may be used to mean that the feature, e.g. the layer may be formed “directly on,” e.g. in direct contact with, the implied side or surface. The word “over” may also be used herein to describe forming a feature, e.g. a layer “over” a side or surface, and may be used to mean that the feature, e.g. the layer may be formed “indirectly on” the implied side or surface with one or more additional layers being arranged between the implied side or surface and the formed layer.

Various embodiments provide an efficient and inexpensive test for sensors. The embodiments include pressure sensors or pressure sensor modules, which may be calibrated and/or tested under different pressures and temperatures. The pressure sensors or pressure modules may be constructed or assembled using different embedding technologies, such as embedded wafer level ball grid array (eWLB) technology or BLADE technology. In the embodiments, a plurality of electrical components in a substantially regular arrangement, or an entire embedded chip package including a plurality of electrical components or chips, may be tested, before individualizing the embedded chip package into separate chip packages or modules. The embedded chip package may be round, e.g. in the case of eWLB or rectangular, e.g. in the case of BLADE technologies. The application of the test conditions, e.g. different pressures and/or temperatures and/or accelerations and/or tilting angles, may be applied to a plurality of electrical components in the embedded chip package, e.g. to a subset of all the electrical components in the embedded chip package or all the electrical components in the embedded chip package, simultaneously.

According to various embodiments, the electrical contacting and/or measurement of the plurality of components may be carried out efficiently by contacting all or at least a plurality of components in the embedded chip package at the same time. This may be carried out through a pin selection board; or using a multiplexer; or wiring the plurality of components at definite contact positions in the embedded chip package. The contacts need then only be contacted once, and may then be connected to the test equipment. Furthermore, the fabrication of the test wires may be integrated into back end processing. In other words, the test wires may be fabricated simultaneously with the fabrication of other electrical interconnects which may belong to the final chip package.

According to various embodiments, electrical wiring may be provided in the embedded chip package before individualization and/or separation of the individual chips from each other. Furthermore, as a result, test conditions, such as pressure levels, may be applied simultaneously to a subset of all the plurality of chips or all the chips in the embedded chip package. One or more further components may also be placed in the embedded chip package for testing. These further components may include logic chips and/or sensor chips such as temperature sensor chips. According to various embodiments, the electrical wiring may be carried out by forming conductive tracks in the kerf regions, which may be at least in part removed, during individualization, e.g. by dicing or sawing. In some embodiments, a logic circuit electrically connected to or forming at least part of a testing circuit may also be disposed or housed in the embedded chip package. A logic circuit in the test apparatus, which may also be formed within the embedded chip package, may allow for switching through individual components and their individual measurements.

Various embodiments therefore provide an elegant and low-cost test embedded chip package and chip arrangement for highly efficient testing.

FIG. 1shows method100for manufacturing an embedded chip package according to various embodiments. Method100may include:

embedding a plurality of chips in an encapsulation material (in110);

forming at least one electrical redistribution layer over the encapsulation material, the at least one electrical redistribution layer electrically connected to the plurality of chips (in120); and

forming a common terminal and connecting the common terminal to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal (in130).

FIGS. 2A to 2Ishow illustrations in various views for performing method100for manufacturing an embedded chip package according to various embodiments.

The method may include embedding a chips202, e.g. which may be referred to collectively as plurality of chips2021to202nin an encapsulation material to form an embedded chip package. The embedded chip package may form an intelligent workpiece or test board, which includes the plurality of chips2021to202n.

Each chip202(referred to as chip202) may include a semiconductor die. Each chip202may include at least one pressure sensor. In other words, each chip202may be a pressure sensor chip. Each chip202may include sensing portion216which may include a sensing input216A (not shown) and a sensor circuit216B (not shown). Sensing input216A may receive and react to an external stimulus of pressure, such as a change in pressure. For example, sensing input216A may include a membrane which may be configured to exhibit a change in an electrical property such as a change in electrical resistance due to a change in pressure applied to sensing input216A. Sensing circuit216B may include a circuit electrically connected to sensing input216A, which may be configured to convert a change in property of the sensing input216A in response to an applied stimulus, e.g. pressure, to an output signal237(not shown) which may be proportional to the applied stimulus. Sensing circuit216B may include, according to an embodiment, a Wheatstone bridge circuit. According to other embodiments, sensing circuit216B may include at least one of a capacitive sensing circuit, electromagnetic sensing circuit and piezoelectric sensing circuit. In other words, output signal237may include at least one of a voltage signal, capacitive signal, electromagnetic signal and piezoelectric signal.

Each chip202of plurality of chips2021to202n, may include a respective chip front side206; chip back side208; chip sidewalls212; and one or more contact pads214formed over chip front side206. Each chip202may include sensing portion216formed over chip front side206. Each chip202may include a semiconductor die, or include at least part of a semiconductor wafer. Each chip202may have undergone front end processing, e.g. front end of line (FEOL) processes and back end of line (BEOL) processes to form sensing portions216, e.g. sensing inputs216A and sensing circuits216B of chips202. Each chip202may form at least part of a semiconductor wafer, the semiconductor wafer including at least one of doped silicon or undoped silicon, germanium, gallium arsenide (GaAs), indium phosphide (InP) and silicon carbide (SiC). Sensing portion216of each chip216may be electrically connected to one or more contact pads214on each chip202. For example, sensing circuit216B of each chip216may be electrically connected to one or more contact pads214on each chip202. Contact pads214may be configured to at least one of transmit and/or receive an electrical signal to and/or from the sensing portion216. For example, contact pads214A and214B may be input terminals for providing an excitation voltage (for example, a common voltage such as Ground voltage and VDD respectively) to sensing circuit216B. In various embodiments, each chip202may include a plurality of chips in one package (multi-chip package). In various embodiments, a first chip of the plurality of chips in one package may include a sensor chip portion and a second chip of the plurality of chips in the same package may include a logic circuit, e.g. connected to the sensor chip portion of the other chip in the same package. In various embodiments, the chip202may include other chips such as e.g. transceiver chips (e.g. HF transceiver chips), amplifier chips, filter chips (e.g. surface acoustic wave filter chips and/or bulk acoustic wave filter chips).

Plurality of chips2021to202nmay be embedded in encapsulation material using various processes. It may be understood that plurality of chips2021to202nmay refer to one or more chips e.g. two, three, four, or more, or even tens, hundreds or even thousands of chips, i.e. n may be an arbitrary whole number. Each chip of the plurality of chips may have a chip thickness in the range from about 10 μm to about 775 μm.

In an embodiment, as shown in cross-sectional view210ofFIG. 2A, using an eWLB approach, plurality of chips2021to202nmay be placed or arranged over temporary carrier204. Plurality of chips2021to202nmay be arranged over temporary carrier204with each of their front sides206facing and arranged directly on temporary carrier204.

Subsequently, as shown in view220ofFIG. 2B, encapsulation material218may be formed over plurality of chips2021to202nwherein encapsulation material218may cover chip back sides208and chip sidewalls212of plurality of chips2021to202n. Encapsulation material218may therefore at least partially surround plurality of chips2021to202n. Encapsulation material218may include an electrically insulating material, such as an organic based material. Plurality of chips2021to202nmay be commonly connected to each other via encapsulation material218.

As shown in view230ofFIG. 2C, temporary carrier204may be removed leaving embedded chip package222which may also be referred to as a reformed wafer. Embedded chip package222may include plurality of chips2021to202nembedded in encapsulation material218. Embedded chip package222may be arbitrarily shaped. According to some embodiments, embedded chip package222may be round or rectangular in shape, i.e. panel sized. Contact pads214formed over each of chip front sides206may be substantially free from encapsulation material218. Sensing portion216formed over each of chip front sides206may also be substantially free from encapsulation material218. Contact pads214may be electrically connected to sensing portion216.

FIG. 2Dshows top view240of embedded chip package222including plurality of chips2021to202nembedded in encapsulation material218. Plurality of chips2021to202nmay be arranged regularly, for example, in rows (R) and/or columns (C), e.g. in reticles. Encapsulation material218may be formed between plurality of chips2021to202n. Parts of embedded chip package222not occupied by plurality of chips2021to202n, e.g. between chips, and/or edge regions of embedded chip package222, may be referred to as kerf regions219. Kerf regions may be disposed off after individualizing and dicing of chips.

As shown in cross-sectional views250and260ofFIGS. 2E and 2F, the formation of electrical redistribution layers224,228as test wires within the embedded chip package222may be carried out in kerf regions219. The formation of electrical interconnects (not shown) which are to be part of the final chip package may also be carried out together with the formation of the electrical redistribution layers. Electrical redistribution layers224,228and electrical interconnects may be carried out by at least one of: electroplating, sputtering and evaporation.

At least one electrical redistribution layer224may be electrically connected to a subset202s1of the plurality of chips2021to202n. It may be understood that a subset of plurality of chips2021to202nmay refer to a fraction (less than 1) of total number, n, of plurality of chips2021to202nin embedded chip package222. A subset may also refer to all of the total number, n, of plurality of chips2021to202nin embedded chip package222. Electrical redistribution layer224may be formed over encapsulation material218, e.g. over package front side227or over package back side229, in regions between plurality of chips2021to202n, i.e. in kerf regions219. Common terminal226may be formed over encapsulation material218, e.g. over package front side227or over package back side229, in regions between plurality of chips2021to202n. Common terminal226may also be formed and connected, e.g. electrically connected to electrical redistribution layer224. Common terminal226may provide an interface to at least one of transmit and receive a common electrical signal234between the plurality of chips, e.g. via electrical redistribution layer224, and common terminal226. Electrical redistribution layer224may be electrically connected to a respective first contact pad214A of each of the one or more contact pads214. During testing, common terminal226may be connected to a test circuit, or form at least part of a test circuit, which may provide a voltage input, e.g. Ground voltage to each respective first contact pad214A of chips202within subset202s1.

At least one further electrical redistribution layer228may be electrically connected to a subset202s1of the plurality of chips2021to202n. This may be the same subset of the plurality of chips plurality of chips2021to202nto which electrical redistribution layer224may be electrically connected. Further electrical redistribution layer228may be electrically connected to a respective second contact pad214B of each of plurality of chips2021to202n. Further electrical redistribution layer228may be formed over encapsulation material218. Similarly to electrical redistribution layer224further electrical redistribution layer228may be formed over encapsulation material218, e.g. over package front side227or over package back side229, in regions between plurality of chips2021to202n. Furthermore, further common terminal232may be formed over encapsulation material218, e.g. over package front side227or over package back side229, in regions between plurality of chips2021to202n. Further common terminal232may be formed and connected, e.g. electrically connected, to further electrical redistribution layer228, wherein further common terminal232may provide an interface to at least one of transmit and receive a further common electrical signal236between further electrical redistribution layer228and further common terminal232. During testing, further common terminal232may be connected to a test circuit, or form at least part of a test circuit, which may provide a voltage input, e.g. VDD voltage to each respective second contact pad214B of chips202within subset202s1.

In other words, both electrically redistribution layer224and further electrical redistribution layer228may be electrically connected to subset202s1of plurality of chips2021to202nin embedded chip package222.

Top view260ofFIG. 2Fshows another embodiment, wherein electrically redistribution layer224and further electrical redistribution layer228may be electrically connected to subset202s1of total number of plurality of chips2021to202n. As may be understood fromFIGS. 2G and 2H, the arrangement of plurality of chips2021to202nmay be varied according to the desired electrical wiring provided by electrically redistribution layer224and further electrical redistribution layer228. Plurality of chips2021to202nmay be arranged in regular patterns, e.g. in reticles. The one or more dies/reticles may include a specific chip for testing purposes. In these arrangements, electrical test contacts may be arranged far from sensitive components in the chip sensor, therefore, any impact of the sensor by mechanical test pins may be avoided.

FIGS. 2E and 2Fshow, for simplicity, only one electrical redistribution layer224per chip connected to each common terminal226. Similarly, only one further electrical redistribution layer228per chip is shown to be connected to each further common terminal232. It may be understood however, that various embodiments may not be restricted by these illustrations, and that it may be possible for a plurality of electrical redistribution layers224to be connected to common terminal226and similarly, for a plurality further electrical redistribution layers228per chip to be electrically connected to further common terminal232. It may also be understood that for simplicity, test wiring via electrical redistribution layer224and further electrical redistribution layer228is shown only for one subset of chips from plurality of chips2021to202n. Embedded chip package222may in fact include more than one subset of chips which may be similarly wired.

FIGS. 2G and 2Hshow cross-sectional views270and280respectively of how electrical redistribution layers224and further electrical redistribution layers228may be formed in embedded chip package222according to various embodiments. In one embodiment, as shown in view270, electrically insulating material231may be selectively formed over package front side227. Electrically insulating material231may be formed over chip front sides206as well as contact pads214. Lithography and etching may be carried out to etch through selected portions of electrically insulating material231to expose contact pads214, for example to form holes over a first portion of contact pads214by selectively removing portions of encapsulation material218. Subsequently, electrical redistribution layers224and further electrical redistribution layers228may be formed in the holes over a first portion of contact pads214. For example, electrical redistribution layer224may be formed over a first portion of first contact pad214A and further electrical redistribution layers228may be formed over a first portion of second contact pad214B. At least part of electrical redistribution layers224and further electrical redistribution layers228may also be formed over encapsulation material218.

It may be understood that electrical redistribution layers224and further electrical redistribution layers228may be configured to provide the electrical wiring for connecting to a testing circuit, and may be separated from the final chip package after testing. Electrical interconnects264,266(shown inFIG. 2I) may also be formed simultaneously during the formation of electrical redistribution layer224and further electrical redistribution layers228and/or using similar fabrication processes. Electrical interconnects264,266may provide the electrical wiring for the sensor, and may remain as part of the final chip package.

As shown in cross-sectional view290ofFIG. 2I, electrical interconnect264may be formed over a second portion of first contact pad214A and further electrical interconnect266may be formed over a second portion of second contact pad214B. At least part of electrical interconnect264and further electrical interconnect266may also be formed over encapsulation material218. Further electrically insulating material233may be formed over electrical interconnect264, further electrical interconnect266and electrical redistribution layers224and further electrical redistribution layers228. For example, further electrically insulating material233may be deposited over package front side227which covers and at least partially surrounds electrical interconnect264, further electrical interconnect266and electrical redistribution layers224and further electrical redistribution layers228. Subsequently, solder structures268,272may be joined to electrical interconnect264and further electrical interconnect266. In order for this to be achieved, portions of further electrically insulating material233covering electrical interconnect264and further electrical interconnect266may be removed to expose at least one portion respectively of electrical interconnect264and further electrical interconnect266. In a simultaneous process, portions of further electrically insulating material233covering electrical redistribution layer224and further electrical redistribution layer228may be removed to expose at least one portion respectively of electrical redistribution layer224and further electrical redistribution layer228.

Solder structures268,272, e.g. a solder ball, or solder joint, may be formed in the exposed respective parts of electrical interconnect264and further electrical interconnect266. In other words, first solder structure268may be formed in electrical connection with electrical interconnect264, and second solder structure272may be formed in electrical connection with further electrical interconnect266. Common terminal226and further common terminal232may be formed in the exposed respective parts of electrical redistribution layer224and further electrical redistribution layer228. For example, common terminal226and further common terminal232may be formed over encapsulation material218, e.g. in holes formed through further electrically insulating material233. Therefore, common terminal226may be formed in electrical connection with electrical redistribution layers224. Furthermore, further common terminal232may be formed in electrical connection with further electrical redistribution layers228.

Electrically redistribution layer224, further electrical redistribution layer228, common terminal226and further common terminal232may be formed over package front side227of embedded chip package222. Solder structures268,272may also be formed over package front side227. Electrically redistribution layer224, further electrical redistribution layer228, common terminal226and further common terminal232may each include at least one metal or alloy of at least one of copper, nickel, iron, silver, gold and palladium. Electrically redistribution layer224, further electrical redistribution layer228, common terminal226and further common terminal232may be deposited by at least one of: electroplating, sputtering and evaporation. Electrical interconnects264,266may each include at least one metal or alloy of at least one of copper, nickel, iron, silver, gold and palladium. Electrical interconnects264,266may be deposited by at least one of: electroplating, sputtering and evaporation. The above mentioned layers and interconnects may have a thickness in the range from about 3 μm to about 50 μm.

In another embodiment, as shown in view280, contact pads214may be routed from package front side227to package back side229. Electrical redistribution layer224may include first through-package-via254which may electrically redirect first contact pad214A from package front side227to package back side229and to common terminal226. Further electrical redistribution layer228may include second through-package-via255which may electrically redirect second contact pad214B from package front side227to package back side229and to further common terminal232. At least part of electrically redistribution layer224, further electrical redistribution layer228, common terminal226and further common terminal232may be formed over package back side229of embedded chip package222. Electrical interconnects264,266may also be formed simultaneously during the formation of electrical redistribution layer224and further electrical redistribution layers228, and may optionally be also routed from package front side227to package back side229. In other words, solder structures268,272may be formed on package back side229. Optionally, electrical interconnects264,266may optionally not be routed from package front side227to package back side229. In other words, solder structures268,272may be formed on package back side227.

Testing of plurality of chips2021to202nmay subsequently be carried out. During testing, it may be possible that a series of different pressures may be applied to the chips undergoing testing. It may also be possible that each pressure of the series of different pressures may be applied at various temperatures. Common electrical signal234and further common electrical signal234may be applied to the chips undergoing testing and/or a variety of devices, simultaneously. For example, common electrical signal234and further common electrical signal234may be applied to common terminal226and further common terminal232respectively, wherein common terminal226and further common terminal232may be input terminals for an excitation voltage applied to sensing circuit216B. Each chip202may include at least one third contact pad214C (not shown), which may be a designated output contact pad for transmitting and/or receiving output signal237. At least one common output terminal262(not shown) may be configured to receive a common output signal237between at least one output electrical redistribution layer and common output terminal262. It may be understood that at least one third contact pad214C, may be electrically connected to common output terminal262using processes similar to those already described above. For example, output electrical redistribution layer may be formed in a common process as electrically redistribution layer224, further electrical redistribution layer228. Similarly, common output terminal262may be formed in a common process with common terminal226and further common terminal232. The test signals, may be transmitted and/or received from terminal226and/or further common terminal232from front side206with test pins.

As an example, common electrical signal234may be provided to a subset e.g.202s1or all, of plurality of chips2021to202nsimultaneously via common terminal226. Common electrical signal234may be provided to a respective first contact pad214A of each chip in the subset of chips. Common electrical signal234may be a ground voltage. Simultaneously, further common electrical signal236may be provided to a subset e.g. subset202s1or to all of plurality of chips2021to202nvia further common terminal232. Further common electrical signal236may be provided to a respective second contact pad214B of each chip in the subset of chips. Further common electrical signal236may be a voltage VDD. Electrical redistribution layer224and further electrical redistribution layer228may electrically connect the contact pads214A,214B of each chip to common terminal226and further common terminal232respectively. Furthermore, electrical redistribution layer224and further electrical redistribution layer228may configured to provide common electrical signal234and further common electrical signal236simultaneously. Therefore, the subset of chips to be tested simultaneously, that is without serially connecting and/or reconnecting each chip to a testing circuit. In other words, common terminal226and further common terminal232may contact each respective first contact pad and each respective second contact pad214B of the subset of chips just once. Furthermore, a batch test may be applied to the subset of chips, by applying the voltages to common terminal226and further common terminal232just once. Testing may be carried out, batch-wise on embedded chip package222. For example, embedded chip package222may include a plurality of subsets of chips which may each be batch tested as described before.

Pressure P1may be applied to sensing input(s)216A of the subset of chips. Output signal237may be generated due to the applied pressure P1, wherein output signal237may be proportional to the pressure P1applied to sensing input(s)216A. Output signal may be transmitted from sensing circuit216B to third contact pad214C, to at least one output electrical redistribution layer and to common output terminal262. The testing process may be repeated for a series of pressures, e.g. P1, P2, P3, and/or for a series of temperatures, e.g. T1, T2, T3. When the subset of chips has been tested, the processes may be repeated for another subset of chips in embedded chip package222.

After testing, individualization each of the plurality of chips2021to202nfrom each other may be carried out. As shown in top view290ofFIG. 2I, plurality of chips2021to202nmay each be individualized from each other by separating through dicing lines267. For example, by dicing through electrical redistribution layer224and/or further electrical redistribution layer228. For example, each of plurality of chips2021to202nmay be separated or diced apart from each other by dicing through electrical redistribution layer224and/or further electrical redistribution layer228and/or encapsulation material218and/or electrically insulating material231and/or further electrically insulating material233. Each chip202of plurality of chips2021to202nmay be separated from at least part of electrical redistribution layer224and common terminal226. Furthermore, each chip202of plurality of chips2021to202nmay be separated from at least part of further electrical redistribution layer228and further common terminal232. It may be understood, that therefore, each chip package610may be separated from at least part of electrical redistribution layer224and/or common terminal226and/or further electrical redistribution layer228and/or further common terminal232/.

FIG. 6shows chip package610according to an embodiment. Chip package610may be obtained after dicing through dicing lines267.

Chip package610may include chip202. Chip202may include sensing portion216and one or more contact pads214electrically connected to sensing portion216. Chip package610may include electrical redistribution layer224electrically contacting at least one contact pad214A. Electrical redistribution layer224may extend from at least one contact pad214A to sidewall678of chip package610, wherein a portion of electrical redistribution layer224may be exposed at sidewall678of chip package610.

Chip package610may further include electrically insulating material231,233at least partially surrounding chip202and electrical redistribution layer224. The portion of electrical redistribution layer224exposed at sidewall678of chip package610may be free of electrically insulating material231,233. In other words, the exposed part of electrical redistribution layer224may be uncovered. Chip package may further include an electrical interconnect264electrically contacting contact pad214A. Electrical interconnect264may be at least partially surrounded by electrically insulating material231,233, wherein at least part of electrical interconnect264may be connected to solder structure268, which may be formed over electrically insulating material231,233/.

It may be understood that although only one chip202, e.g. one pressure chip, is shown per chip package610, it may be possible that each chip package610may include a system including more than one chip, i.e. more than one electrical component, and at least one pressure sensor chip202.

FIG. 3shows embedded chip package322according to various other embodiments. Embedded chip package322may include one or more or all of the features already described with respect to embedded chip package222. In one embodiment however, embedded chip package322may include at least one further chip342which may include at least one of a calibrating circuit, a testing circuit and a multiplexing circuit. Further chip342may be included only for test purposes and may be removed by the singulation process. According to an embodiment, further chip342may include a logic circuit which may form at least part of, or be connected to a multiplexer, wherein the multiplexer may be configured to selectively transmit and/or receive at least one of common signal234, further common signal236and/or output signal237to and/or from a selected chip or subset of chips. Further chip342may include a specific logic function which may simply be testing, e.g. which may enable scanning through various devices and/or temperature measurements. The further chip may be an individual chip also covered by the encapsulation material. As an alternative or in addition, the further chip may be implemented together (on the same matrix, substrate or wafer) with one chip of the plurality of chip (illustratively, this chip includes a “functional” chip as well as the test functionality as a master test chip controlling the testing of the chips all covered by the encapsulation material via the common redistribution layer).

In one embodiment, common terminal226, further common terminal232and common output terminal262(not shown) may form at least part of further chip342as shown in view310ofFIG. 3A. Further chip342may be disposed at least partially in encapsulation material218and electrically connected to plurality of chips2021to202n. Further chip342may also be electrically connected to common terminal226and/or further common terminal232. Further chip342may be configured to at least one of transmit and receive common electrical signal234, e.g. Ground voltage, via common terminal226. Furthermore, further chip342may be configured to at least one of transmit and receive further common electrical signal236, e.g. voltage VDD, via further common terminal232. Further chip342may be configured to at least one of transmit and receive common output signal237via common output terminal262.

After testing, as described above, plurality of chips2021to202nmay each be individualized from each other by separating through electrical redistribution layer224and/or further electrical redistribution layer228. For example, each of plurality of chips2021to202nmay be separated from at least part of electrical redistribution layer224, at least part of further electrical redistribution layer228, common terminal226, further common terminal232and further chip342. Dicing may be carried out through dicing lines467. It may be understood that the parts separated from plurality of chips2021to202nmay then be discarded as they do not form part of the final chip package.

Different approaches may be used for manufacturing an embedded chip package as an intelligent test board for batch testing of sensors.FIGS. 4A to 4Cshow method400for manufacturing embedded chip package422according to another embodiment. Embedded chip package422may include a BLADE package. In an embodiment, as shown in cross-sectional view410ofFIG. 4A, method400may include embedding plurality of chips2021to202n, e.g. semiconductor dies, in an encapsulation material218. As shown in view410, plurality of chips2021to202nmay be placed or arranged over carrier438, wherein chip back sides208may be arranged directly on and facing carrier438. Back sides208of plurality of chips2021to202nmay be adhered to carrier438. Back sides208may be electrically connected to carrier438or electrically insulated from carrier438depending on the type of electrical device and performance required from plurality of chips2021to202n. If an electrically conductive contact is required from chip back sides208, (e.g. with power devices, such as electronic devices with current flow between front side206and back side208) then carrier438may include or be an electrically conductive material. For example, carrier438may include a metal or alloy of at least one of copper, nickel, iron, silver, gold and palladium.

Subsequently, as shown in view420ofFIG. 4B, encapsulation material218may be formed over plurality of chips2021to202nwherein encapsulation material218may cover chip front sides206and chip sidewalls212of plurality of chips2021to202n. Encapsulation material218may cover one or more contact pads214formed on chip front sides206, whereas sensing portions216may be exposed; in other words, sensing portions216may be substantially free from encapsulation material218. Encapsulation material218may therefore at least partially surround plurality of chips2021to202n. Plurality of chips2021to202nmay be commonly connected to each other via encapsulation material218and carrier438as shown by embedded chip package322. Encapsulation material218may include an electrically insulating laminate.

Embedded chip package422may include plurality of chips2021to202nembedded in encapsulation material218and formed over carrier438. Embedded chip package422may be arbitrarily shaped. According to some embodiments, embedded chip package422may be round or rectangular in shape. Etching through selective portions of encapsulation material218may be carried out exposed contact pads214formed over each of chip front sides206, for example to form holes over contact pads214by selectively removing portions of encapsulation material218. Subsequently, electrical redistribution layers424and further electrical redistribution layers428may be formed in the through holes and over encapsulation material218. Electrical redistribution layers424and further electrical redistribution layers428may be analogous to electrical redistribution layers224and further electrical redistribution layers228respectively.

As shown in view430ofFIG. 4C, electrical redistribution layer424may be formed over encapsulation material218, wherein electrical redistribution layer424may be electrically connected to plurality of chips2021to202n. Electrical redistribution layer424may be electrically connected to a group of the plurality of chips2021to202n, for example to a subset of plurality of chips2021to202n, or to the entire group of the plurality of chips2021to202n. Furthermore, common terminal226may be formed and connected to electrical redistribution layer424. Common terminal226may provide an interface to at least one of transmit and receive a common electrical signal234between the plurality of chips, e.g. via electrical redistribution layer424, and common terminal226.

At least one electrical redistribution layer424may be formed over encapsulation material218in regions between plurality of chips. Electrical redistribution layer424may be electrically connected to a respective first contact pad214A of each of the one or more contact pads214. Common terminal226may be formed over encapsulation material218in regions between plurality of chips2021to202n, for example over front side227of embedded chip package422. At least one further electrical redistribution layer428may be formed over encapsulation material218. Further electrical redistribution layer428may be electrically connected to plurality of chips2021to202n, for example over front side227of embedded chip package422. Further electrical redistribution layer428may be electrically connected to a respective second contact pad214B of each of plurality of chips2021to202n. Furthermore, further common terminal232may be formed over encapsulation material218. Further common terminal232may be connected to further electrical redistribution layer428, wherein further common terminal232may provide an interface to at least one of transmit and receive a further common electrical signal236between further electrical redistribution layer428and further common terminal232.

After testing, individualization each of the plurality of chips2021to202nfrom each other may be carried out as described according toFIG. 2I. Plurality of chips2021to202nmay each be individualized from each other by separating through electrical redistribution layer424and/or further electrical redistribution layer428. For example, each of plurality of chips2021to202nmay be separated or diced away from each other by dicing through electrical redistribution layer424and/or further electrical redistribution layer428, encapsulation material218and carrier438. Plurality of chips2021to202nmay be separated from at least part of electrical redistribution layer424and common terminal226. Plurality of chips2021to202nmay be separated from at least part of further electrical redistribution layer428and further common terminal232.

FIGS. 5A and 5Bshows a testing arrangement and a method for performing testing on plurality of chips2021to202naccording to various embodiments.

In view510ofFIG. 5, testing is shown to be carried out on embedded chip package322as an example. Common terminal226, further common terminal232and output terminal262may be formed on chip back side208, which may be outside the pressure chamber. It may be understood, however, that similar testing may be adapted to be carried out on any of embedded chip packages222,322,422.

Embedded chip packages222,322,422may be used as an intelligent test interface and/or test board in which plurality of chips2021to202nmay be arranged. Fixture544may include one or more sealing parts546and one or more inlets548, and may be used to apply pressure simultaneously to plurality of chips2021to202n. In an embodiment, the test arrangement may also include test fixture556with test pins558.

As shown inFIG. 5B, fixture544may be placed over embedded chip package,222and/or322and/or422, e.g. over front side227of the embedded chip package. Each of sensing portions216may be separated from each other by at least one sealing part546, e.g. soft seals. Fixture544may be arranged such that chambers552may be enclosed by sealing parts546and fixture544, wherein sealing parts546may separate each sensing portion216from at least one other neighboring sensing portions216. Each chamber552may include an inlet548, wherein pressure may be applied to sensing portion216which may be sealed in chamber552. For example, during a test, air at different pressures P1, P2, P3may be applied to sensing portion216via inlet548. Fixture544may be arranged over plurality of chips2021to202nso that pressure may be applied to a plurality of sensing portions216of plurality of chips2021to202nsimultaneously.

According to the embodiment ofFIG. 5B, sealing parts546may be arranged such that each chamber522may separate a single chip202from a neighboring chip202.

As shown in view530ofFIG. 5C, it may be possible to arrange sealing parts546over package front side227such that each chamber622may separate a plurality of chips2021to202n, e.g. two chips202, three chips202or more, from a neighboring plurality of chips. In other word, sealing parts546may be arranged between arrays of devices, e.g. reticles. Chamber622may include one inlet548which may provide a pressure to a plurality of sensing portions216sealed within chamber552. Sealing parts546may be arranged or disposed in areas between chips202or arrays of chips202. For example, between rows and/or columns of chips202. As shown in view540ofFIG. 5D, it may be possible to arrange sealing parts546over such that each chamber622may separate a plurality of chips2021to202n, e.g. two chips202, three chips202or more, from a neighboring plurality of chips. Sealing parts546may be arranged over a temporary carrier574or carrier438. It may even be possible to arrange sealing parts546such that each chamber552may seal all chips in the embedded chip package in a single chamber, e.g. by sealing the pressure interface on a border region, e.g. a circumference of the embedded chip package. Chamber552may include one or more inlets548which may provide a pressure to all the chips in the embedded chip package within chamber552.

Various embodiments provide an embedded chip package including: a plurality of chips; encapsulation material embedding the plurality of chips; at least one electrical redistribution layer electrically connected to the plurality of chips; and a common terminal connected to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal (e.g. via the at least one electrical redistribution layer).

According to an embodiment, the encapsulation material at least partially surrounds the plurality of chips.

According to an embodiment, the plurality of chips are commonly connected to each other via the encapsulation material.

According to an embodiment, each or some of the plurality of chips includes a sensing portion; and one or more contact pads electrically connected to the sensing portion.

According to an embodiment, the encapsulation material covers one or more sides of each of the plurality of chips; and wherein the sensing portions of each of the plurality of chips are substantially free from the encapsulation material.

According to an embodiment, the at least one electrical redistribution layer is electrically connected to a respective first contact pad of each of the one or more contact pads.

According to an embodiment, the at least one electrical redistribution layer is formed over the encapsulation material in regions between the plurality of chips.

According to an embodiment, the common terminal is formed over the encapsulation material in regions between the plurality of chips.

According to an embodiment, the common terminal is formed at least partially in the encapsulation material.

According to an embodiment, the embedded chip package further includes at least one further electrical redistribution layer; and a further common terminal connected to the at least one further electrical redistribution layer, wherein the further common terminal provides a further interface to at least one of transmit and receive a further common electrical signal between the at least one further electrical redistribution layer and the common terminal; wherein the at least one further electrical redistribution layer is electrically connected to a respective second contact pad of each of the plurality of chips.

According to an embodiment, the embedded chip package further includes at least one further chip disposed at least partially in the encapsulation material, wherein the at least one further chip is electrically connected to the plurality of chips.

According to an embodiment, the at least one further chip is configured to at least one of transmit and receive the common electrical signal via the common terminal.

According to an embodiment, the embedded chip package further includes at least one further chip disposed at least partially in the encapsulation material, wherein the at least one further chip is electrically connected to at least one of the common terminal and the further common terminal.

According to an embodiment, the at least one further chip is configured to at least one of transmit and receive the common electrical signal via the common terminal and to at least one of transmit and receive the further common electrical signal via the further common terminal.

According to an embodiment, the at least one further chip includes at least one of a calibrating circuit, a testing circuit and a multiplexing circuit.

According to an embodiment, each sensing portion of the plurality of chips includes at least part of a pressure sensor.

Various embodiments provide a method for manufacturing an embedded chip package, the method including: embedding a plurality of chips in an encapsulation material; forming at least one electrical redistribution layer over the encapsulation material, the at least one electrical redistribution layer electrically connected to the plurality of chips; and forming a common terminal and connecting the common terminal to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips, e.g. via at least one electrical redistribution layer, and the common terminal.

According to an embodiment, embedding the plurality of chips in the encapsulation material includes forming encapsulation material over one or more sides of each of the plurality of chips wherein the sensing portions of each of the plurality of chips are substantially free from the encapsulation material.

According to an embodiment, each chip of the plurality of chips includes one or more contact pads; and the method further includes electrically connecting the at least one electrical redistribution layer to a respective first contact pad of each of one or more contact pads.

According to an embodiment, forming the at least one electrical redistribution layer over the encapsulation material includes forming the at least one electrical redistribution layer in regions between the plurality of chips.

According to an embodiment, the method further includes forming the common terminal over the encapsulation material in regions between the plurality of chips.

According to an embodiment, the method further includes forming at least one further electrical redistribution layer over the encapsulation material, the at least one further electrical redistribution layer electrically connected to the plurality of chips; and forming a further common terminal and connecting the further common terminal to the at least one further electrical redistribution layer, wherein the further common terminal provides an interface to at least one of transmit and receive a further common electrical signal between the at least one further electrical redistribution layer and the further common terminal.

According to an embodiment, the method further includes disposing at least one further chip at least partially in the encapsulation material, wherein the at least one further chip is configured to at least one of transmit and receive the common electrical signal via the common terminal.

According to an embodiment, the method further includes disposing at least one further chip at least partially in the encapsulation material, wherein the at least one further chip is configured to at least one of transmit and receive the common electrical signal via the common terminal and to at least one of transmit and receive the further common electrical signal via the further common terminal.

According to an embodiment, the method further includes individualizing the plurality of chips from each other by separating through the at least one electrical redistribution layer.

According to an embodiment, the method further includes separating the plurality of chips from at least part of the at least one electrical redistribution layer and the common terminal.

Various embodiments provide a chip package including: a chip including a sensing portion and one or more contact pads electrically connected to the sensing portion; and an electrical redistribution layer electrically contacting the at least one contact pad, wherein the electrical redistribution layer extends from the at least one contact pad to a sidewall of the chip package, wherein a portion of the electrical redistribution layer is exposed at the sidewall of the chip package.

According to an embodiment, the chip package further includes electrically insulating material at least partially surrounding the chip and the electrical redistribution layer, wherein the portion of the electrical redistribution layer exposed at the sidewall of the chip package electrical redistribution layer is free of electrically insulating material.

According to an embodiment, the chip package further includes an electrical interconnect electrically contacting the at least one contact pad and at least partially surrounded by the electrically insulating material, wherein at least part of the electrical interconnect is connected to a solder structure formed over the electrically insulating material.