Semiconductor memory device and method of forming the same

Example embodiments provide a semiconductor memory device and method of forming a semiconductor memory device that may equalize load due to a coupling capacitance between a line and a component signal when the line intersects the component signal in a memory cell array. A line may intersect a memory cell region between a transmitting point (A) and a receiving point (B) of a signal. A line between the transmitting point (A) and the receiving point (B) may be bent at two portions of each of bit lines. Because areas where the line and the bit lines extend parallel to each other may be equal in dimension at each bit line, coupling capacitances between the line and the bit lines may be equalized. The read characteristic may not be affected by the coupling capacitances.

PRIORITY STATEMENT

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Japanese Patent Application No. 2006-175551 filed on Jun. 26, 2006, the entire contents of which are hereby incorporated by reference.

BACKGROUND

Example embodiment relate to a semiconductor memory device and method of forming a semiconductor memory device, for example, to a semiconductor memory device capable of equalizing load of a coupling capacitance between a line and a component in a memory cell array when the line intersects the component.

2. Description of Related Art

FIG. 3is a schematic view of a memory cell array100in a semiconductor memory device. The memory cell array100may include a plurality of memory cells (not shown) disposed in a matrix form, and a plurality of word lines and bit lines may be disposed in the memory cell array100. A word line and a bit line may be selected by outputs of an X decoder301and a Y decoder302, and a memory cell located at intersection therebetween may be selected.

A memory region with a memory cell array may be decreased as the size of a memory cell becomes smaller.FIG. 1Aillustrates a memory cell region and a peripheral region andFIG. 1Billustrates a reduced memory cell region and a reduced peripheral region. As illustrated inFIGS. 1A and 1B, the degree of reduction of the peripheral region is relatively small, when compared with the degree of reduction of the memory cell region. The reason is that the size of a circuit and the number of signal lines increases as a semiconductor device with higher performance and/or lower power consumption may be required.

Referring toFIG. 2, a semiconductor chip10may include, for example, memory cell regions101and102and peripheral circuits201,202,203and204. When a signal used for each peripheral circuit is not synchronized with an operation of a memory cell, this may affect a word line or a bit line, and thus only the word line and the bit line may be formed in the memory cell region101and other signal lines may not be formed.

Lines between the peripheral circuits201,202,203and204may be formed such that the lines do not pass over the memory cell regions101and102. Referring toFIG. 4, digital signal processors (DSPs)211and212and memory control units (MCUs)213and214are exemplarily illustrated as peripheral circuits in a chip20.

Even though the DSPa211and the MCUa213are disposed to interpose a memory a111(for example, a flash memory) therebetween, a line connecting them may not pass over and detours around the memory a111. Similarly, even though the DSPb212and the MCUb214may be disposed to interpose a memory b112(for example, a flash memory) therebetween, a line connecting them may not pass over and detours around the memory b112. InFIG. 4, these lines are represented by relatively thick arrows401and402.

When lines are formed so as to detour memory cell regions without passing over them, a line region of a peripheral region may increase according to an increase in the number of signals. Therefore, it may be difficult to reduce the peripheral region around the memory cell regions.

Reduction of a die size may be essential to a general-purpose memory. Also, a signal line may need to be formed in a memory cell of a peripheral circuit. For example, as described above, when memories (for example, flash memories) and MCUs are mounted in the same chip, signal lines may be formed as well as word lines and/or bit lines in a memory cell, as lines501and502are illustrated inFIG. 5. InFIG. 5, the line501intersects a memory111to connect a DSPa211with a MCUa213and the line502intersects a memory112to connect a DSPb212with a MCUb214on a chip20. In this case, lines may be formed as illustrated inFIGS. 10A and 10B.

For example, when a transmitting point A and a receiving point B of a signal are located as illustrated inFIG. 10A, an A-B line600between the transmitting point A and the receiving point B may be at right angles to bit lines BL0-BL2, is bent at two portions of a bit line BL2, and is at right angles to bit lines BL2-BL4, as illustrated inFIG. 10B.

In a memory cell array, the bit line BL2corresponding to a lower one of bent portions of the line600may be affected by load of coupling capacitance between the line600and the bit lines BL0˜BL4. Therefore, coupling capacitances of the bit lines BL0˜BL4are represented as follows: BL0, BL4<BL1, BL3<BL2.

In a semiconductor memory device, the read access speed should be considered, based on a line that is most affected by load of a coupling capacitance, e.g., a line with the slowest read access speed. Therefore, inFIGS. 10A and 10B, the read access speed may be determined based on the bit line BL2that has the largest coupling capacitance. That is, the read characteristic may be deteriorated due to biased coupling capacitance in the bit lines.

As shown inFIG. 10Band discussed above, when coupling capacitances between adjoining word lines or bit lines are not uniform, it may become difficult to accurately operate the semiconductor memory device.

SUMMARY OF THE INVENTION

Example embodiments provide a semiconductor memory device that may save a line region.

Example embodiments provide a semiconductor memory device that may prevent or reduce line congestion and signal delay when the number of signal lines increases.

Example embodiments provide a semiconductor memory device including a line between a transmitting point A and a receiving point B which equalizes a coupling capacitance.

Example embodiments provide a semiconductor memory device that may reduce or minimize effects on the read characteristic by equalizing load due to coupling capacitances between a line and bit lines in a memory.

Example embodiments provide semiconductor memory devices that equalize overlap between a line and bit lines in a memory.

Example embodiments provide semiconductor memory devices including: a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at intersections of the word lines and the bit lines in a matrix form; and/or a line crossing a memory cell region provided with the plurality of memory cell to connect first and second peripheral circuits disposed in a peripheral region of the memory region to each other. Coupling capacitance between the line and each of the plurality of bit lines may be uniform.

In example embodiments, the line may include a plurality of bent portions at each of the bit lines and areas where the line and the bit lines extend parallel to each other may be equal in dimension at each bit line.

In example embodiments, the total number of the bent portions may be more than an integer multiple of the total number of the bit lines.

In example embodiments, the line may extend linearly between the first and second peripheral circuits in the memory cell region.

Example embodiments provide methods of forming a semiconductor memory device including providing a memory cell array defining a memory cell region, including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines in a matrix form and forming a line, crossing the memory cell region, to connect first and second peripheral circuits, disposed in a peripheral region, to each other, wherein a coupling capacitance between the line and each of the plurality of bit lines is equalized.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments will be more clearly understood from the detailed description taken in conjunction with the accompanying drawings.

Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.

It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the FIGS. For example, two FIGS. shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

Also, the use of the words “compound,” “compounds,” or “compound(s),” refer to either a single compound or to a plurality of compounds. These words are used to denote one or more compounds but may also just indicate a single compound.

Various embodiments of the present invention will be described in detail with reference to the attached drawings. However, example embodiments are not limited to the example embodiments, but may be embodied in various forms. In the figures, if a layer is formed on another layer or a substrate, it means that the layer is directly formed on another layer or a substrate, or that a third layer is interposed therebetween. In the following description, the same reference numerals denote the same elements.

Example embodiments will be described below in more detail with reference to the accompanying drawings.

To begin with, an example embodiment will be described.FIG. 6illustrates a transmitting point A and a receiving point B of a signal to be connected with a plurality of bit lines BL0˜BL4in an example embodiment.

As illustrated inFIG. 7, in an example embodiment, a line700between the transmitting and receiving points A and B may be bent at two portions (for example, in a step-wise pattern) of each of the bit lines BL0˜BL4. Because areas where the line700extends parallel to the bit lines BL0˜BL4may be equal to each other in dimension, coupling capacitances between the line700and each of the bit lines BL0˜BL4may be equalized. The read access speed may not decrease in any bit line, and the coupling capacitances may not affect the read characteristic.

An example embodiment is illustrated inFIG. 8. A line800is formed between the transmitting point A and the receiving point B of a signal illustrated inFIG. 6.

In an example embodiment, the line800between the transmitting point A and the receiving point B may extend straight without being bent at any of bit lines BL0˜BL4. Load due to coupling capacitances between the line800and the bit lines BL0˜BL4may be equalized, and thus the read characteristic may not be affected by the coupling capacitances.

An example embodiment will be described with reference toFIGS. 9A and 9B. In an example embodiment, a transmitting point A and a receiving point B of a signal may be located as illustrated inFIG. 9A. A line900between the transmitting point A and the receiving point B may be at right angles to each of bit lines BL0˜BL4, as illustrated inFIG. 9B. Similar to other example embodiments, coupling capacitances between the line900and the bit lines BL0˜BL4may be equalized, and the read characteristic may not be affected by the coupling capacitances.

As described above, when a line intersecting a memory cell is formed according to example embodiments, load due to coupling capacitances between the line and bit lines may be equalized. Therefore, effect on the read characteristic or the like may be reduced or minimized.

Example embodiments are exemplarily described, but are not limited thereto and various embodiments may be performed.

According to example embodiments, a line region may be effectively utilized. That is, a peripheral region may be reduced. Additionally, when the number of signal lines increases, line congestion may be easily resolved, and signal delay may be decreased by reducing a length of a signal line. Effect on the read characteristic may be reduced or minimized by equalizing load of coupling capacitances between a line intersecting a memory and bit lines.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other example embodiments, which fall within the true spirit and scope of the appended claims. Thus, to the maximum extent allowed by law, the scope of the example embodiments is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.