8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate

The present application discloses a non-volatile semiconductor memory device for storing up to eight-bits of information. The device has a semiconductor substrate of one conductivity type, a central bottom diffusion region on top of a portion of the semiconductor substrate, a second semiconductor layer on top of the bottom diffusion region, and left and right diffusion regions formed in the second semiconductor layer apart from the central bottom diffusion region thus forming a first vertical channel between the right and central bottom diffusion regions. The device further includes a trapping dielectric layer formed over exposed portions of the semiconductor substrate, left, central and right bottom diffusion regions and second semiconductor layer and a wordline formed over the trapping dielectric layer. A methods of fabricating this novel cell using trench technology is also disclosed.

BACKGROUND OF THE INVENTION
 1. Field of the Invention
 The present invention relates in general to non-volatile digital memories
 and, more particularly, to an improved cell structure for a programmable
 non-volatile memory (such as conventional EEPROM or Flash EEPROM) that can
 store up to eight-bits of information and a method for fabricating same.
 2. Background Art
 Non-volatile memory devices, such as EPROM, EEPROM, and flash EPROM
 devices, generally include a matrix of transistors which act as memory
 cells for storing a single-bit of information. Each transistor in this
 matrix has source and drain regions formed on a n- or p-type semiconductor
 substrate, a thin tunnel dielectric layer formed on the surface of the
 semiconductor substrate positioned at least between the source and drain
 regions, a floating gate (formed of polysilicon) positioned on the
 insulating layer for holding a charge, a control gate and an interpoly
 dielectric positioned between the floating gate and control gate.
 Traditionally, the interpoly dielectric had consisted of a single layer of
 silicon dioxide (SiO.sub.2). However, more recently oxide/nitride/oxide
 composites (sometimes referred to as an ONO structure) have been used in
 place of the silicon dioxide because they exhibit decreased charge leakage
 over the single oxide layer (see Chang et al. U.S. Pat. No. 5,619,052).
 U.S. Pat. No. 5,768,192 to Eitan discloses that ONO structures (as well as
 other charge trapping dielectrics) have been used as both insulator and
 floating gate. FIG. 1 shows the prior art structure disclosed in Eitan.
 Eitan teaches that by programming and reading this transistor device in
 opposite directions (i.e. reversing "source" and "drain") shorter
 programming times still result in a high increase in exhibited threshold
 voltage. Eitan suggests that this result is useful in reducing programming
 time while still preventing "punch through" (i.e. a condition where the
 lateral electric field is strong enough to draw electrons through to the
 drain, regardless of the applied threshold level).
 The semiconductor memory industry has been researching various techniques
 and approaches to lower the bit cost of non-volatile memory. Two of the
 more important approaches are dimensional shrinking and multilevel
 storage. Multilevel storage (often referred to as multilevel cells) means
 that a single cell can represent more than one bit of data. In
 conventional memory cell design, only one bit has been represented by two
 different voltage levels, such as 0V and 5V (in association with some
 voltage margin), which represent 0 or 1. In multilevel storage more
 voltage ranges/current ranges are necessary to encode the multiple bits of
 data. The multiple ranges lead to reduced margins between ranges and
 require advanced design techniques. As a result, multilevel storage cells
 are difficult to design and manufacture. Some exhibit poor reliability.
 Some have slower read times than convention single-bit cells.
 Accordingly, it is an object of the present invention to produce a
 non-volatile memory structure that achieves cost-savings by providing a
 structure capable of storing up to eight bits of data, thus significantly
 increasing the storage size of the non-volatile memory. It is an
 associated object of the present invention for this cell structure to
 operate without the use of reduced margins or advanced design techniques.
 These and other objects will be apparent to those of ordinary skill in the
 art having the present drawings, specification and claims before them.
 SUMMARY OF THE INVENTION
 The present invention discloses a single cell non-volatile semiconductor
 memory dvice for storing up to eight-bits of information. The device has a
 semiconductor substrate of one conductivity type, a central bottom
 diffusion region on top of a portion of the semiconductor substrate, a
 second semiconductor layer on top of the bottom diffusion region, and left
 and right diffusion regions formed in the second semiconductor layer apart
 from the central bottom diffusion region thus forming a first vertical
 channel between the right and central bottom diffusion regions. The device
 further includes a trapping dielectric layer formed over exposed portions
 of the semiconductor substrate, left, central and right bottom diffusion
 regions and second semiconductor layer and a wordline formed over the
 trapping dielectric layer.
 The foregoing structure can be fabricated by: (1) forming a semiconductor
 substrate of one conductivity type; (2) implanting ions in the
 semiconductor substrate a layer of conductivity type opposite to the
 conductivity type of the semiconductor substrate to form a bottom
 diffusion region; (3) growing a second semiconductor layer on at least a
 portion of said bottom diffusion region; (4) implanting ions in the second
 semiconductor layer to form in the second semiconductor layers, right and
 left diffusion regions of the same conductivity type; (5) trenching the
 resulting semiconductor wafer to form one or more free-standing cells on
 the semiconductor substrate; (6) depositing a trapping dielectric
 structure on the exposed faces of the free-standing cells and
 semiconductor substrate; and (7) depositing a polysilicon control gate on
 top of the trapping dielectric structure.

BEST MODES OF CARRYING OUT THE INVENTION
 While the present invention may be embodied in many different forms and
 produced by various different fabrication processes, there is shown in the
 drawings and discussed herein one specific embodiment and fabrication
 method with the understanding that the present disclosure is to be
 considered only as an exemplification of the principles of the invention
 and is not intended to limit the invention to the embodiment illustrated.
 FIGS. 1a and 1b show eight-bit non-volatile memory cell structures 100 that
 are formed on and incorporate a portion of semiconductor substrate 101 in
 association with the present invention. As each cell 100 is preferably
 constructed identically, the structure for cell 100a shall be described
 with the understanding that such structure is preferably found in each
 cell. Some memory cells varying from this main construct may be used in
 association with cell 100. In fact, it is contemplated that modified
 versions of cell 100 (and other types of cells) will likely be used at the
 periphery of a memory array. FIG. 1c is a front perspective view of a
 plurality of 8-bit memory cells on a semiconductor substrate.
 Cell 100 has a bottom diffusion region 102 on top of semiconductor
 substrate 101 having a conductivity type opposite to the conductivity type
 of substrate 101. On top of bottom diffusion region 102, a second
 semiconductor layer 103 having the same conductivity type of substrate 101
 is formed. Within this second semiconductor layer, left diffusion region
 104 and right diffusion region 106 are fashioned apart from one another
 both having the same conductivity type as bottom diffusion region 102 (n+
 in the disclosed embodiment). As a result, first horizontal channel region
 120 is formed between left and right diffusion regions 104 and 106; first
 vertical channel region 121 is formed between right and bottom diffusion
 regions 106 and 102; and second vertical channel region 122 is formed
 between left and bottom diffusion regions 104 and 102. Thus, there is
 basically three channels found completely within a single cell. And, as
 will be explained more fully below, each horizontal and vertical channel
 is capable of storing two bits. In view of this twin-bit storage and the
 symmetrical design, where substantially identical cells are fabricated
 adjacent one another, an additional (second) horizontal channel can be
 formed between the bottom diffusion regions of two pairs of adjacent
 cells. In particular, as shown in FIG. 1b, left second horizontal channel
 portion 123a is formed between the bottom diffusion regions 102a and 102b
 of cell pair 100a and 100b, respectively. And right second horizontal
 channel portion 123b is formed between the bottom diffusion regions 102a
 and 102c of cell pair 100a and 100c.
 Each cell 100 further includes thin (tunneling) oxide layer 110, nitride
 layer 111, and insulating oxide layer 112, which are uniformly layered
 over the exposed portions of semiconductor substrate 101, bottom diffusion
 channel 102, and second semiconductor layer 103 (including left and right
 diffusion regions) (as illustrated in FIG. 1a) to form a trapping
 dielectric layer. In one embodiment, oxide layer 110 and 112 are each
 approximately 100 micron thick whereas the nitride layer is approximately
 50 microns thick. Although these dielectric structures have been
 illustrated as being formed by sandwiching a nitride layer between a thin
 tunneling oxide and insulating oxide, other dielectric structures could be
 used instead, such as SiO.sub.2 /Al.sub.2 O.sub.3 /SiO.sub.2.
 Access to each bit in cell 100 is controlled by the combination of wordline
 115 and the diffusion regions 102, 104 and 106. Wordline 115 is formed of
 polysilicon directly on top of the ONO dielectric layer. As is known by
 those of ordinary skill in the art, diffusion regions 102, 104, 106 in a
 MOS transistor are indistinguishable in a zero-bias state; thus, the role
 of each diffusion region is defined after terminal voltages are applied
 with the drain biased higher than the source. Thus, by application of
 particular biasing voltages and a sufficient voltage on a particular
 wordline various bits can be programmed, read or erased.
 Bit storage in cell 100 is based, in part, on the discovery that by using a
 trapping dielectric layer one-bit of data can be stored and localized in a
 channel adjacent a each diffusion region. In addition, by reversing the
 program and read directions, interference between the each of the two
 charge storage regions can be avoided. The overall approach is shown for
 one particular pair (bit1/bit2) in FIGS. 3A and 3B. FIG. 3A illustrates
 the programming and reading of "bit1." To program the bit1, left diffusion
 region 104 is treated as the drain terminal (by applying a voltage of
 4-6V), right diffusion region 106 is treated as the source (by applying 0V
 or low voltage for hot-e program), wordline 115 has applied 8-10V and the
 bottom diffusion regions all have voltages applied thereto to avoid
 program disturb of bits 3-8. To read bit1, the left diffusion region is
 treated as source (by applying a voltage of 0V) and the right diffusion is
 treated as the drain (by applying a voltage of 1-2V. As depicted by FIG.
 3B, similar operations would be used to program and read bit2. This
 structure, which presents a thinner oxide layer to the programming
 currents allows for quicker programming with lower overall voltages.
 As shown in FIG. 4 (in which a charge was stored in bit2), the localized
 trapped electrons exhibit different threshold voltages if read in
 different directions. The first line depicts the threshold voltage when
 the right diffusion channel is used as drain (the same direction as in the
 program step). The second line depicts the threshold voltage when the left
 diffusion is used as drain (the reverse of the program step). As can be
 seen from these two lines, by reversing the read and program directions
 used, a more efficient threshold voltage behavior is exhibited. By
 utilizing this aspect of the design, even though both sides of a pair are
 programmed with information, only the threshold voltage of single bit is
 read by selecting either the left or right diffusion region to be the
 drain.
 It should be noted with respect to bit5 and bit6, programming and reading
 of each of these bits require proper biasing of the bottom diffusion
 region of the adjacent cell. For instance, for programming bit5, bottom
 diffusion region 102a is treated as drain and bottom diffusion region 102c
 is treated as source. As for bit6, bottom diffusion region 102a is treated
 as drain and bottom diffusion region 102b is treated as source. Although
 not shown in the drawings, it should be understood that bit5 has a twin
 storage location associated with adjacent cell 100c and similarly bit6 has
 one associated with adjacent cell 100b. In sum, programming of the
 eight-bits of a single cell can be accomplished, assuming a selected
 wordline (8-10V), with the following biasing of various diffusion regions: