Method to reduce CD non-uniformity in IC manufacturing

A method is provided for reducing Critical Dimension (CD) non-uniformity in creating a patterned layer of semiconductor material. Two masking layers are respectively created, the first masking layer comprising a main pattern, an isolated pattern and a dummy pattern, the second masking layer exposing the dummy pattern. Methods of compensating for optical proximity effects and micro-loading, as provided by the invention, are applied in creating the first masking layer. The patterned first masking layer is transposed to an underlying layer creating a first pattern therein. The second masking layer removes the dummy features from the transposed first pattern, creating a second pattern therein comprising a main pattern and an isolated pattern to which compensation for optical proximity effects and micro-loading have been applied. The second pattern serves for additional etching of underlying semiconductor material.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to further improve the imaging of patterns that are used in photolithography by providing improved enhancement effects for sub-resolution lines that are added to a line pattern, to address issues of having insufficient space in order to add sub-resolution lines and issues of avoiding printing sub-resolution lines.

(2) Description of the Prior Art

The creation of semiconductor devices requires numerous interacting and mutually supporting disciplines. Addressed at this time are the disciplines that are required to create patterns on a semiconductor surface, such as the surface of a layer of photoresist or the surface of a semiconductor substrate.

Device features are transposed from a mask onto a semiconductor surface using processes of photolithographic imaging, which requires the transfer of photo energy from a source to a target surface. It is therefore to be expected that, for target features that are created in very close proximity to each other, the transfer of photo energy interacts for these very closely spaced device features, which are most commonly interconnect lines having sub-micron spacing between adjacent lines. This interaction imposes limitations on the proximity of adjacent device features, these limitations are referred to as Critical Dimensions (CD) of a design and device layout. This CD is commonly defined as the smallest spacing or the smallest line width of an interconnect line that can be achieved between adjacent interconnect lines. This CD in current technology is approaching the 0.1 to 0.2 μm range.

The invention addresses the problems of insufficient resolution and depth-of-focus in imaging interconnect lines and the spacing that is provided between these lines. In past practices, these problems have been addressed by adding sub-resolution lines in combination with off-axis illumination. The latter improves depth of focus for closely packed lines. The sub-resolution scattering bars artificially produce close packing while the scattering bars are not being printed. The latter is due to the fact that the size of the scattering bars is below the resolution limit. This method is therefore limited by the small size of the scattering bars. Increasing the size of the scattering bars in order to enhance the resolution and depth of focus results in printing these assist features. An improved method is therefore required which addresses these issues and the issue of printing of the assist features.

U.S. Pat. No. 5,946,563 (Uchara et al.) provides for a semiconductor device and for a method of manufacturing the same.

U.S. Pat. No. 6,281,049 B1 (Lee) provides a semiconductor device mask and for a method of creating the mask.

U.S. Pat. No. 6,426,269 Bi (Haffner et al.) provides a method for the reduction of dummy features by using optical proximity effect correction.

SUMMARY OF THE INVENTION

A principle objective of the invention is to provide a method of photolithographic exposure using Full Size Assist Features (FSAF) in order to optimize the spatial frequency and the unification of the photolithographic exposure level.

Another objective of the invention is to narrow the range of the distribution of the line-to-space ratio in a given mask pattern that is used for photolithographic exposure.

A method is provided for reducing Critical Dimension (CD) non-uniformity in creating a patterned layer of semiconductor material. A substrate is provided with one or more layers of semiconductor material, a first masking layer is deposited over the one or more layers of semiconductor material. A first pattern, comprising high-density semiconductor device features, isolated semiconductor device features and dummy features, is created in the first masking layer, thereby applying methods for compensation of optical proximity effects and micro-loading. The first pattern is transposed to at least one layer of the one or more layers of semiconductor material after which the patterned first masking layer of removed. A second masking layer is deposited over the one or more layers of semiconductor material, including the patterned at least one layer of the one or more layers of semiconductor material. A second pattern is created in the second masking layer, exposing the dummy features of the at least one layer of the one or more layers of semiconductor material. The exposed dummy features are removed from the at least one layer of the one or more layers of semiconductor material after which the patterned second masking layer is removed. The at least one layer of semiconductor material is patterned in accordance with the pattern created in the at least one layer of the one or more layers of semiconductor material.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

As has been previously highlighted, close line spacing in the range of a line-width to line-spacing (L/S) ratio of 1:1 are difficult to achieve for devices having resolution-limiting size, resulting in a narrow latitude of exposure and a small depth of focus or both. To correct this problem, a well-known method is to use off-axis illumination, in the form of annular, quadruple of dipole configurations. A limitation of this method is that the location of the ring, quadruples or dipoles can be optimized only for a special frequency in the object. For example, only the image of pairs of 1:1 spaced lines (line-width to line-spacing ratio) can be optimized. In this case of optimization, lines with a L:S=1:2 ratio will benefit less from this optimization scheme, lines that are spaced further apart benefit even less. This scheme can be applied to lines with for instance L:S=1:2 but this optimization is achieved at the expense of lines with higher and lower ratios of L:S.

A frequently applied method that is applied to improve the imaging of patterns with a larger pitch (distance between adjacent images) is to add sub-resolution lines where space is available for such addition. These sub-resolution lines are not printable but they contribute spatial frequencies, creating a condition of exposure that is close to an optimized condition. The sub-resolution lines also move the exposure level of the less optimized patterns closer to the exposure level of the optimized patterns. However, the enhancement effects of these sub-resolution lines are still significantly less effective than the full size printable lines. Finally, the sub-resolution lines may still be printed in cases where careful control is not applied to the use of these sub-resolution lines.

The invention provides for application of a Full Size Assist Feature (FSAF) pattern, the FSAF is used to maximize the contribution (by the FSAF) to spatial frequency and to achieve unification of the exposure level of the desired feature. The FSAF exposure is removed by application of an additional exposure, using a specially designed mask that contains erasing features of the surface regions where the FSAF are located.

The invention therefore provides for:a first mask that comprises the desired features in addition to full-size assist featuresa second mask that comprises unpacking features that have shapes that are similar to (follow the contours of) the full-size assist featuresa second mask that comprises unpacking features that have shapes that are similar to the desired featuresthe unpacking features of the second mask of the invention have dimensions that are slightly larger than the corresponding dimensions of the full-size assist features provided on the first mask the full-size assist features are placed on the first mask of the invention at a measurable distance from the desired features; this measurable distance varies between about 0.5 and 3.0 times the width of the desired minimum featurethe size of the full-size assist feature on the first mask of the invention has a width that is between about 0.5 and 3 times the width of the minimum desired featurethe measurable distance of the full-size assist features on the first mask of the invention is determined in accordance with a combination of desired feature size or width, the shape of the desired feature and the location of the desired feature within the exposure pattern; this determination is aimed at creating the best image possible, that is at optimizing image performance, andthe size of the full-size assist features on the first mask of the invention is determined in accordance with a combination of desired feature size or width, the shape of the desired feature, and the location of the desired feature within the exposure pattern; this determination is aimed at creating the best image possible, that is at optimizing image performance.

Keeping in mind the above listed aspects of the mask of the invention, it can be stated that a key aspect of the invention is to narrow the range of the ratio of Line-Width to Line-Spacing (L:S) for a given pattern that has been created on the surface of a mask. In view of the fact that it is typically not feasible to limit the circuit designer to a range of L:S ratios, this ratio can vary between 1:1 and 1:infinity, that is between equal line-width to line-spacing to isolated lines. By adding the FSAF, the range in the ratio L:S can be significantly narrowed, making off-axis illumination extremely effective.

The conventions that are provided by the invention are next illustrated using the drawings that are part of this application.

FIGS. 1athrough1cshow an enhancement of an isolated line. By adding one FSAF to each side of the desired isolated line at a distance “d” from either edge of the desired isolated line, new spatial frequency components are created. The most prominent of these new spatial frequency components is the first order component of the newly formed pitch p=c/2+a/2+d, where “c” is the width of a given feature of the circuit design and “a” is the width of the FSAF. Preferably a=c, in which case p=c+d. The separation “d” is selected such that optimum results are obtained for a L:S ratio with a given off-axis illumination condition. These optimum results are most beneficially obtained for ratios of L:S within the range of between 1:1 and 1:2. Alternately, the value for “d” and the off-axis illumination condition are mutually adjusted until the best imaging performance is achieved, that is the best performance as measured by Depth Of Focus (DOF), exposure latitude and exposure-defocus area.

For the drawings that are shown, values of d=a and c=a have been selected as examples. The principles that are explained using these selections equally apply for different selections of these values or their ratios.FIGS. 1athrough1cshow a top view of an image where two FSAF12and14have been placed, one FSAF on each side of an isolated line10.

Shown in top view inFIGS. 1athrough1cshow are:16,FIG. 1a, the image on the surface of the packed mask; with packed mask is indicated the mask that contains an image of both the desired (or final) image and an image that will be provided in an unpacking mask;18,FIG. 1b, the image provided on the surface of the unpacking mask;20,FIG. 1c, the final image that is created by first exposing with the packed mask16, after which the same surface is exposed with the unpacking mask18; this exposure with the unpacking mask18is performed such that the unpacking images11and13are aligned with the images12and14of the packed mask.

The exposure sequence that has been highlighted usingFIGS. 1athrough1cmakes clear that the stated method of the invention is being performed. To review this method: a Full Size Assist Feature provides a FSAF pattern18, the FSAF pattern18is used to maximize the contribution by the FSAF pattern18to spatial frequency and to achieve unification of the exposure level of the desired feature, that is exposure using the mask16. The FSAF exposure12and14is removed by application of an additional exposure, using the specially designed unpacking mask18that contains erasing features11and13of the surface regions12and14where the FSAF are located.

Keeping in mind the above provided explanation of the principle of the invention, the remaining figures can be described in detail.

FIGS. 2athrough2cshow a top view of the PAR implementation, applied to enhance a line-to-spacing (L/S) ratio of 1:1, as follows:22,FIG. 2a, the image on the surface of the packed mask; two FSAF images17have been placed, one FSAF one each side of two desired or final lines15;24,FIG. 2b, the image on the surface of the unpacking mask; two unpacking images19and21have been provided in the surface of the unpacking mask24;26,FIG. 2c, the final image that is created by first exposing with the packed mask22, after which the same surface is exposed with the unpacking mask24; this exposure with the unpacking mask24is performed such that the unpacking images19and21are aligned with the images17of the packed mask22. This allows pattern19/21to maximize the contribution to spatial frequency and to achieve unification of the exposure level of the desired feature, that is the final image15shown in top view in image26.

FIGS. 3athrough3cshow a top view of the PAR implementation, applied to enhance a L/S ratio of 1:3. InFIGS. 3athrough3c, with a separation equal to “3c” between two desired features, one FSAF pattern is added between these two desired features, two additional FSAF patterns are added to the outside of the two desired features.

FIGS. 3athrough3cshow in top view:32,FIG. 3a, the image on the surface of the packed mask; one FSAF image27has been placed between two desired features28, two additional FSAF patterns29have been added to the outside of the two desired features;34,FIG. 3b, the image on the surface of the unpacking mask; three unpacking images30have been provided in the surface of the unpacking mask34;36,FIG. 3c, the final image that is created by first exposing with the packed mask32, after which the same surface is exposed with the unpacking mask34; this exposure with the unpacking mask34is performed such that the unpacking images30are aligned with the images27and29of the packed mask22. This allows pattern30, of image34to maximize the contribution to spatial frequency and to achieve unification of the exposure level of the desired feature, that is the final image28shown in top view in image36.

FIGS. 4athrough4cshow a top view of the PAR implementation, applied to enhance a L/S ratio of 1:4.1. InFIGS. 4athrough4c, with a somewhat larger separation between the lines of the desired image (L/S=1:4.1), two FSAF patterns can be added between the desired features. Since these two added FSAF patterns are in close proximity, these two patterns can be combined into one pattern. Two additional FSAF patterns are added to the outside of the two desired features.

FIGS. 4athrough4cshow in top view:38,FIG. 4a, the image on the surface of the packed mask; FSAF images31, combined into one larger image, have been placed between two desired features44, two additional FSAF patterns33have been added to the outside of the two desired features;40,FIG. 4b, the image on the surface of the unpacking mask; unpacking images37, combined into one image and two unpacking images35have been provided in the surface of the unpacking mask40;42,FIG. 4c, the final image44that is created by first exposing with the packed mask38, after which the same surface is exposed with the unpacking mask40; this exposure with the unpacking mask40is performed such that the unpacking images35/37are aligned with the images33/31respectively of the packed mask38. This allows patterns33/37, of image40to maximize the contribution to spatial frequency and to achieve unification of the exposure level of the desired feature, that is the final image44shown in top view in image42.

FIGS. 5athrough5cshow a top view of the (wide) PAR implementation, applied to enhance a L/S ratio of 1:3.9. InFIGS. 5athrough5c, with a somewhat smaller separation between the lines of the desired image (L/S=3.9), two FSAF patterns are added between the desired features. Since these two added FSAF patterns are now in close proximity, these two patterns overlap for patterns where a distance of “d” is maintained between the edge of the FSAF pattern and the adjacent desired pattern. The pattern of two inserted two FSAF patterns can therefore combined into one pattern. Alternatively, one FSAF pattern may be applied whereby however the width of this one pattern is adjusted for optimum results of exposure as measured by DOF, exposure latitude and exposure/defocus range. This latter application is shown in top view inFIGS. 6athrough6b. Two additional FSAF patterns are added to the outside of the two desired features.

FIGS. 5athrough5cshow in top view:44,FIG. 5a, the image on the surface of the packed mask; FSAF images39, combined into one larger image, have been placed between two desired features50, two additional FSAF patterns51have been added to the outside of the two desired features;46,FIG. 5b, the image on the surface of the unpacking mask; unpacking images39, combined into one image55and two unpacking images53, have been provided in the surface of the unpacking mask46;48,FIG. 5c, the final image that is created by first exposing with the packed mask44, after which the same surface is exposed with the unpacking mask46; this exposure with the unpacking mask46is performed such that the unpacking images55/53are aligned with the images39/51respectively of the packed mask44. This allows patterns53/55, of image46to maximize the contribution to spatial frequency and to achieve unification of the exposure level of the desired feature, that is the final image50shown in top view in image48.

FIGS. 6athrough6cshow a top view of the (narrow) PAR implementation, applied to enhance a L/S ratio of 1:3.9. InFIGS. 6athrough6c, the FSAF images39ofFIG. 5ahave been replaced with the one FSAF image39′, the unpacking image55ofFIG. 5bhas been replaced with the one unpacking image55′, as previously highlighted.

FIGS. 7athrough7cshow a top view of the PAR implementation, applied to enhance a L/S ratio of 1:1.5. InFIGS. 7athrough7cthe distance between the desired features is between “1c” and “2c”, L:S=1:1.5 For these cases, there is no room available between the features for the addition of a FSAF image which however still allows for the addition of FSAF images to the outside of the desired image.

FIGS. 7athrough7cshow in top view:52,FIG. 7a, the image on the surface of the packed mask; FSAF images57have been added to the outside of the two desired features5854,FIG. 7b, the image on the surface of the unpacking mask; unpacking images59have been provided in the surface of the unpacking mask54;56,FIG. 7c, the final image that is created by first exposing with the packed mask52, after which the same surface is exposed with the unpacking mask54; this exposure with the unpacking mask54is performed such that the unpacking images59are aligned with the images57of the packed mask52. This allows patterns59, of image54to maximize the contribution to spatial frequency and to achieve unification of the exposure level of the desired feature, that is the final image58shown in top view in image56.

FIGS. 8athrough8cshow a top view of the PAR implementation, applied to enhance a L/S ratio of 1:2. inFIGS. 8athrough8cthe distance between the desired features is “2c”, L:S=1:2. For this case, there is no room available between the features for the addition of a FSAF image which however still allows for the addition of FSAF images to the outside of the desired image.

FIGS. 8athrough8cshow in top view:60,FIG. 8a, the image on the surface of the packed mask; FSAF images65have been added to the outside of the two desired features6662,FIG. 8b, the image on the surface of the unpacking mask; unpacking images67have been provided in the surface of the unpacking mask62;64,FIG. 8c, the final image that is created by first exposing with the packed mask60, after which the same surface is exposed with the unpacking mask62; this exposure with the unpacking mask62is performed such that the unpacking images67are aligned with the images65of the packed mask60. This allows patterns67, of image62to maximize the contribution to spatial frequency and to achieve unification of the exposure level of the desired feature, that is the final image66shown in top view in image64.

FIGS. 9athrough9cshow a top view of the PAR implementation, applied to enhance a L/S ratio of 1:2.5. InFIGS. 9athrough9cthe distance between the desired features is between “2c” and “2c”, L:S=1:2.5. For this case, there is room available between the features for the addition of a FSAF image but the FSAF image in this case the value for “a” must be smaller than dimension “c” in order to maintain the value of parameter “d”. Two FSAF images have been added to the outside of the desired image.

FIGS. 9athrough9cshow in top view:68,FIG. 9a, the image on the surface of the packed mask; one FSAF images77has been placed between two desired features74, two additional FSAF patterns73have been added to the outside of the two desired features7470,FIG. 9b, the image on the surface of the unpacking mask; three unpacking images75have been provided in the surface of the unpacking mask70;72,FIG. 9c, the final image that is created by first exposing with the packed mask68, after which the same surface is exposed with the unpacking mask70; this exposure with the unpacking mask70is performed such that the unpacking images75are aligned with the images73/77of the packed mask68. This allows pattern75, of image70to maximize the contribution to spatial frequency and to achieve unification of the exposure level of the desired feature, that is the final image74shown in top view in image72.

It is clear from the above that, for linear exposures, the descriptions that have been provided address conditions that are required for the implementation of the invention. Additional detail will be provided relating to non-linear or 2-D exposures in the following drawings.

FIGS. 10athrough10cshow a top view of the PAR implementation, applied to first two-dimensional features.FIGS. 10athrough10cshow the top view of a typical layout for a polysilicon gate electrode. FSAF images are inserted inside and outside the two gate lines in accordance with the above stated principles.

FIGS. 10athrough10cshow in top view:76,FIG. 10a, the image on the surface of the packed mask; FSAF images83has been placed between two desired features82, two additional FSAF patterns81have been added to the outside of two desired features82, additional FSAF patterns85has been added to the outside of the desired feature8878,FIG. 10b, the image on the surface of the unpacking mask; unpacking images84,86and90have been provided in the surface of the unpacking mask78; unpacking images84,86and90of unpacking mask78align with FSAF patterns81,85and83respectively provided on the packed mask7680,FIG. 10c, the final image that is created by first exposing with the packed mask76, after which the same surface is exposed with the unpacking mask78; this exposure with the unpacking mask78is performed such that the unpacking images84,86and90are aligned with the images81,85and83respectively of the packed mask76. This allows patterns81,85and83of image78to maximize the contribution to spatial frequency and to achieve unification of the exposure level of the desired feature, that is the final image82and88shown in top view in image80.

FIGS. 11athrough11cshow a top view of the PAR implementation, applied to second two-dimensional features.FIGS. 11athrough11cshow the same images as those that have been shown in the precedingFIGS. 10athrough10c, with the exception of patterns81′ and84′, which inFIGS. 11athrough11ctake the place of patterns81and84respectively ofFIGS. 10athrough10c. An additional horizontal bar has been added to the FSAF pattern81′/84′ of exposures76and78respectively. The use of this additional horizontal bar can experimentally be determined by evaluating optimum imaging performance for the ends of polysilicon lines82that are closest to this additional horizontal bar.

It must be pointed out that the invention does not impose a limit on the number of FSAF images that are provided, just as long as there is sufficient surface area available to create these FSAF images thereover.

FIG. 12shows a top view of two packing features per side, as applied in the top view shown inFIGS. 2athrough2c.FIG. 12shows a top view that is an extension of the top view that has been shown inFIGS. 2athrough2c, the FSAF packing images17ofFIGS. 2athrough2chave been expanded to two packing images17′ and17″.

FIG. 13shows a top view that is an extension of the top view that has been shown inFIG. 12, the FSAF packing image85ofFIG. 12has been expanded to two packing images85′ and85″, the FSAF packing image81′ ofFIG. 12has been expanded to two packing images81′ and81″.

FIGS. 14athrough14cshow a top view of an unpacking mask, required for the desired features as shown in top view inFIGS. 1athrough1c. Specifically highlighted inFIG. 14bis a different way to create a layout of the unpacking mask, as follows:91are the Full Size Assist Features (FSAF)93is the desired feature95is the layout of the unpacking feature97shows the final feature.

The mask is a light-field mask, the features95of the unpacking mask are similar to and slightly larger than the desired features97.

The following comments apply to the creation of the packed and the unpacking mask of the invention. After creating the packed mask, an unpacking mask is created by repeating the FSAF image and by making each of these images slightly larger (on the unpacking mask) in order to compensate for overlay errors that may occur during the second exposure, that is the exposure of the unpacking mask. For exposures of positive photoresist, the packed mask may be a light-field mask comprising opaque surface regions for the desired features and for the FSAF images. The corresponding unpacking mask is then a dark field mask, comprising transparent surface regions for the FSAF images. Using these masks and performing first an exposure with the packed mask and second an exposure of the same surface of photoresist with the unpacking mask, photoresist features that correspond to the desired features will be created. It must thereby be pointed out that the sequence of exposure is not important and can be reversed from the sequence indicated. By using negative photoresist, the indicated combination of mask polarities creates trench type features in layer of photoresist. This latter type of photoresist image is applicable in cases where the circuit features are delineated by an additive process such as plating or lift-off as opposed to a subtractive process such as etching.

The creation of device features, thereby basing this creation of device features on the above principles of using packed and unpacking images over a first and a second mask as described in detail usingFIGS. 1athrough14c, can further be extended by special processing procedures, these processing procedures will now be explained in detail. The above principles of using packed and unpacking images over a first and a second mask, as described in detail usingFIGS. 1athrough14c, will collectively be referred to as Compensating for Optical Proximity Effects (COPE).

For the following processing procedures, it is assumed that the above Compensating for Optical Proximity Effects (COPE) is implemented. Specifically, device features are assumed to be created by:implementing the above highlighted method of photolithographic exposure using Full Size Assist Features (FSAF) in order to optimize the spatial frequency and the unification of the photolithographic exposure level, andnarrowing the range of the distribution of the line-to-space ratio in a given mask pattern that is used for photolithographic exposure.

Keeping in mind the above stated assumptions relating to the creation of device features, an extension of this process is now described.

This extension is based using the following processing steps and definitions:1. a pattern of device features can comprise densely patterned features, referred to as the main pattern, and less-densely patterned features, referred to as isolated pattern; a pattern of densely patterned device features is defined as a pattern in which a shortest distance between adjacent features of the pattern is less than or equal to 0.2 μm, a pattern of isolated patterned device features is defined as a pattern in which a shortest distance between adjacent features of the pattern exceeds 0.2 μm2. the invention addresses the simultaneous creation of both a main pattern and isolated pattern, such as the simultaneous creation of a pattern of densely spaced and isolated interconnect line3. dummy features are added close to both the main pattern and close to critical isolated patterns, converting the pattern of the isolated pattern into a dense pattern4. optical proximity correction, as this optical proximity correction has been described above usingFIGS. 1athrough14c, is applied (as the above highlighted COPE) to both the main pattern, the isolated pattern and the added dummy features, assuring the same CD for the COPE main pattern, the COPE isolated pattern and the COPE dummy features, creating a First Exposure Pattern (FEP)5. a first photo sensitive layer, such as a first layer of photoresist, is exposed to FEP6. the exposed first layer of photoresist is developed, the FEP pattern created in the first layer of photoresist remains in place7. an underlying layer of semiconductor material, such as a layer of metal in which interconnect traces are to be created, is etched in accordance with FEP the pattern created in the developed first layer of photoresist, transposing both the COPE main pattern, the COPE dummy features and the (COPE) isolated pattern to the underlying layer; as underlying layer can be used a layer of semiconductor material that is selected from the group comprising but not limited to a layer of dielectric, a layer of insulating material, a layer of passivation material, a layer of hardmask material and a layer of conductive material8. the developed first layer of photoresist is removed9. a second photo sensitive layer, such as a second layer of photoresist, is coated over the etched underlying layer10. the second layer of photoresist is exposed and developed, creating therein a Second Exposure Pattern (SEP) that comprises and exposes the dummy features, and11. the dummy features are removed from the underlying layer in accordance with the SEP, leaving the COPE main pattern and the COPE isolate pattern in place underlying layer of semiconductor material.

FIGS. 15a-15dillustrate etching bias variations between dense line patterns and isolated line patterns due to micro-loading in the etch process.

Both dense line patterns and isolated line patterns, even after compensation for optical proximity effects with the objective of having the same CD after photoresist development, still have CD variations in the etch process.

FIGS. 15aand15bshow the same CD of dense line and isolated line pattern after exposure and development, whereby optical proximity correction has been applied.

However, the dense line CD and the isolated line CD shown inFIGS. 15(c) and15(d) will be different after the etch process due to environmental variations, which is the so-called micro loading effect.

In addition, the edge line and the middle line in a dense line pattern will have different CD after etching due to the micro-loading effect. With the dummy pattern inserted through the etch process, the micro-loading effect will cause the CD variation of the dummy pattern that is illustrated inFIGS. 16(a)-16(f).

A first layer104of photoresist is patterned, using conventional method of photolithographic exposure and development.

FIGS. 15athrough15cshow a cross section of semiconductor surface100under the following conditions of processing:FIG. 15ashows a cross section of a patterned and developed layer104of photoresist for a main pattern in which no CD effect is present, that is cross section101for each of the elements of the developed layer104is the sameFIG. 15bshows a cross section of a patterned and developed layer104of photoresist for an isolated feature pattern in which no CD effect is presentFIG. 15cshows the impact of proximity effects on the elements of a main pattern that is created in the film102, for applications where the wafer is provided with full size dummy features but where no corrections have been provided for the exposure proximity effect; cross section103is larger than the cross sections101, which may be assumed to be identical to the cross sections101shown inFIG. 15a, andFIG. 15dshows the impact of proximity effects on the isolated feature ofFIG. 15bthat is created in the film102, for applications where the wafer is provided with full size dummy features but where no corrections have been provided for the exposure proximity effect; cross section107is larger than the cross sections105shown inFIG. 15b.

FIGS. 15athrough15dare shown to indicate that, for a wafer that is provided with a conventional pattern of dummy features but whereby no corrections are provided for the exposure proximity effect, that isFIGS. 15cand15d, the negative impact of the proximity effect is experienced. A pattern of dummy features is typically provided for improvements of exposure and photoresist etch.

The reduction of the CD bias in creating a main pattern and an isolated pattern is now highlighted usingFIGS. 16athrough16f. The process advances fromFIGS. 16a/16btoFIGS. 16c/16dtoFIGS. 16e/16f.

Referring first specifically to the cross section ofFIGS. 16aand16b, there are shown cross sections of a semiconductor surface100, a layer or film102of semiconductor material is deposited over surface100. A main pattern and an isolated pattern are to be created in layer102.

Patterned layer120is a layer of photosensitive material, such as a layer of photo resist, that has been patterned and developed, creating in layer120:a main pattern110a dummy pattern114close to and adjacent to the main pattern110an isolated pattern112, anda dummy pattern116close to and adjacent to the isolated pattern112.

By applying optical proximity correction, which has been explained above usingFIGS. 1athrough14c, improved CD control is assured for the main pattern110, the isolated pattern112and the dummy patterns114and116.

The pattern created in the developed layer120of photo sensitive material is now transposed (by etching) into the underlying layer102, after which the developed layer120, of photo sensitive material, is removed. This results in the cross section as shown inFIGS. 16cand16d, wherein are shown the transposed main pattern110′, the transposed dummy pattern114′, the transposed isolated pattern112′ and the transposed dummy pattern116′.

By now removing the dummy patterns114′ and116′ from the semiconductor surface100, the cross sections that are shown inFIGS. 16eand16fare obtained. Highlighted inFIGS. 16eand16fare the remaining main pattern110′ and the isolated pattern112′, both patterns having been obtained by applying proximity correction and both patterns therefore having improved CD uniformity.

The process flow of the invention is shown next usingFIGS. 17athrough17ffor this purpose. Where the cross sections ofFIGS. 16athrough16fhighlight the creation of a main pattern, an isolated pattern and dummy features,FIGS. 17athrough17fin addition show the function of the second layer of photoresist that is used to remove the dummy features. The main pattern and isolated pattern ofFIGS. 16athrough16fhave been replaced in the cross sections ofFIGS. 17athrough17fwith a simplified pattern122of two elements, since such a simplified pattern adequately describes the function of the second layer of photoresist for the removal of the dummy features.

Shown in the flow ofFIGS. 17athrough17fis the application of a developed first and second layer of photo sensitive layer and how these layers are used for the creation of a main pattern122and for the removal of the dummy features124. The process flow proceeds sequentially fromFIGS. 17athrough17f.

Shown in the cross section ofFIG. 17ais a pattern122that is to be created, applying optical proximity correction, in a film or layer102of semiconductor material. Adjacent and closely spaced to pattern122is a pattern124of dummy features, both the pattern122and pattern124that are shown in cross section inFIG. 17aare created using a photo sensitive material, such as photoresist, over layer102.

In the creation of the patterned layer120of photo sensitive material, corrections for optical proximity effects and micro-loading, as provided by the invention, are applied.

The layer102is etched, as shown in the cross section ofFIG. 17b, using the pattern122/124ofFIG. 17aas a mask, resulting in the patterns122′ and124′ in the layer102of semiconductor material. The developed layer120of photoresist has, in the cross section ofFIG. 17b, been removed after the etch of layer102has been completed.

A second layer126of photo sensitive material is next applied over the patterned layer102, as shown in the cross section ofFIG. 17c. The second layer126of photo resist is patterned and developed, creating openings123and125therethrough, shown in the cross section ofFIG. 17d, that expose the dummy features124′ previously created in layer102. These dummy features124′ are now removed, as shown in the cross section ofFIG. 17e.

After the developed layer126of photo resist is removed, the main features122remain in place as shown in the cross section ofFIG. 17f. These main features may, since layer102may be a layer of hardmask material, also comprise a patterned hard mask.

FIG. 18shows the steps of pattern generation that are provided by the invention, as follows:the general design parameters are first created for the main pattern and the isolated pattern, such as patterns110and112shown in cross section inFIGS. 16a/16b; these patterns are collectively highlighted inFIG. 18as pattern140, step130; this represents a first step that is needed for the creation of the cross section shown inFIGS. 16a/16bthe general design parameters140are, via link131advanced to function132, where dummy features are added to the general design parameters140, such as dummy features114/116shown in the cross sections ofFIGS. 16a/16b; this represents a second step that is needed for the creation of the cross section shown inFIGS. 16a/16bthe combined general design parameters for pattern140and for the dummy features142are outputted to function134for application of photolithographic exposure followed by etch via link133, andvia link135a trim mask144is created by function136to remove dummy features after the etch, such as the removal of dummy features114′/116′ shown in the cross sections ofFIGS. 16c/16d.

The steps shown in the flowchart ofFIG. 18are in accordance with the previously highlighted aspects of the invention.

The steps that are highlighted in the flowchart ofFIG. 18can be system implemented as shown in the system flowchart ofFIG. 20.

Specifically highlighted inFIG. 20are the following system functions and components:160is the central processing unit (CPU) which provides the (software) functions in support of the invention162is the data base on which the original device design resides, that is the design that previously has been highlighted as comprising main patterns and isolated patterns, this record corresponds with the device layout shown in block130ofFIG. 18a software support function, residing in CPU160, adds dummy features to the main patterns and to the isolated patterns of a semiconductor device layout; the resulting semiconductor device exposure pattern is stored on data base163via link171, the created record corresponds with the device layout shown in block132ofFIG. 18a software support function, also residing on CPU160creates, using, via link171, as input the (main pattern/isolated pattern/dummy features pattern) records stored on data base163, creates exposure patterns there-of in which the previously highlighted Compensation for Optical Proximity (COPE) is applied to the exposure pattern of the main patterns and the isolated patterns and the dummy feature pattern, these COPE patterns for the device layout are stored as (COPE implemented) device exposure patterns on date base164via link173; these records represent block134inFIG. 18and result in an exposure mask122/124as is shown in for instanceFIG. 17ayet one more software support function, residing and supported by CPU160, using as input, via link171, the (main pattern/isolated pattern/dummy features pattern) records stored on data base163, creates exposure patterns there-of that expose the dummy features of the device layout, these exposure patterns are stored on data base166via link175; these records represent block136inFIG. 18and result in an exposure as is for instance shown inFIG. 17dthe COPE record of the main pattern/isolated pattern/dummy features pattern is sent, via interconnect165, from data base164, under control of CPU160, to photolithographic exposure tool168, for the creation of a blocking mask as for instance shown in the cross section ofFIG. 17a, the patterned layer102comprising elements122/124the dummy feature exposure pattern is sent, via interconnect167, from data base166to photolithographic exposure tool170, for the removal of the dummy features, as is for instance shown in the cross section ofFIG. 17e; it is recognized that tools168and170may well be one and the same processing chamber.

Not shown in the flow diagram ofFIG. 20are means for date entry and data extraction, the former for instance comprising computer terminals and graphic display devices, the latter for instance comprising printers and graphic display devices. It is thereby further assumed that functions of data entry and data extraction or data display can be invoked and exercised by the photolithographic exposure tools168and170, so that these tools can be applied in real-time mode and so that conditions of photolithographic exposure by tools168and170can be reflected in and integrated with the software support functions that have been highlighted above as these functions are provided by CPU160.

A practical application of the invention is shown inFIGS. 19athrough19f. The particle application shown relates to the creation of a patterned layer of polysilicon such as for instance can be applied for the creation of semiconductor devices in the 248 nm technology, more particularly as can be applied for the creation of floating gates that from part of DRAM cells.

It must be noted in the cross sections ofFIGS. 19athrough19fthat, as opposed to previously highlighted cross sections, the layer of semiconductor material, such as layer102shown inFIGS. 16athrough16f, comprises for the cross sections shown inFIGS. 19athrough19ftwo layers, that is a layer152of hardmask material and a layer150of polysilicon.

The cross section ofFIG. 19ashows the cross section of a semiconductor surface100, such as the surface of a silicon substrate, over which a layer150of polysilicon has been deposited. A layer152of hardmask material is deposited over the layer150of polysilicon.

A first layer154of photoresist has been patterned, creating therein a main pattern149and a dummy pattern151.

The developed first layer154of photoresist serves as a mask for the etch of the layer152of hard mask material, as shown in the cross section ofFIG. 19b, transposing the pattern of layer154of photoresist to layer152of hardmask material, after which the developed layer154of photoresist is removed.

A second layer154of photoresist is deposited over the structure that is shown in cross section inFIG. 19b, as shown in the cross section ofFIG. 19c. The second layer154of photoresist is patterned, creating openings153and155through layer154as shown in the cross section ofFIG. 19d. Openings153and155expose the dummy pattern151′, which can now be etched resulting in the cross section shown inFIG. 19eafter the developed second layer154of photoresist has been removed. The pattern149′ of hardmask material remains in place and can now be used for the etching of the layer150of polysilicon, resulting in the pattern149″ of polysilicon that is shown in the cross section ofFIG. 19f. Based on the premise, which has been used throughout the explanation of the invention, that correction for effects of optical proximity has been applied to the various patterns that are used for the creation of pattern149″, it can be stated that this pattern149″ now has the same CD.