SEMICONDUCTOR PACKAGE

A semiconductor package may include a first dielectric structure, a first pad in the first dielectric structure, a first semiconductor chip provided on the first dielectric structure, and a bump electrically connected to the first pad. The first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad. The first pad may be provided between the bump and the first chip of the first semiconductor chip. The first pad may include a first conductive layer and a second conductive layer covered by the first conductive layer. The bump may be positioned closer to the first conductive layer than to the second conductive layer.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2023-0128344 filed on Sep. 25, 2023 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a semiconductor chip.

A semiconductor package is provided to implement an integrated circuit chip to qualify for use in electronic products. Typically, a semiconductor package is configured such that a semiconductor chip is mounted on a printed circuit board (PCB) and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the development of electronic industry, various studies have been conducted to improve reliability and durability of semiconductor packages.

SUMMARY

One or more example embodiments of the present disclosure provide a semiconductor package with improved electrical properties and increased reliability.

According to an aspect of the disclosure, a semiconductor package may include: a first dielectric structure; a first pad in the first dielectric structure; a first semiconductor chip provided on the first dielectric structure; and a bump electrically connected to the first pad, wherein the first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad, wherein the first pad is between the bump and the first chip pad of the first semiconductor chip, wherein the first pad comprises a first conductive layer and a second conductive layer covered by the first conductive layer, and wherein the bump is positioned closer to the first conductive layer than to the second conductive layer.

According to another aspect of the disclosure, a semiconductor package may include: a first dielectric structure; a first pad in the first dielectric structure; a first semiconductor chip provided on the first dielectric structure; and a bump electrically connected to the first pad, wherein the first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad, wherein the first pad comprises a first conductive layer and a second conductive layer covered by the first conductive layer, wherein the first conductive layer comprises a top surface and a bottom surface that are opposite to each other, wherein the top surface of the first conductive layer is in contact with the first chip pad of the first semiconductor chip, and wherein an area at the bottom surface of the first conductive layer is greater than an area at the top surface of the first conductive layer.

According to some embodiments of the present inventive concepts, a semiconductor package may comprise: a first dielectric structure; a first pad and a plurality of key patterns in the first dielectric structure; a first semiconductor chip in contact with the first dielectric structure; a bump electrically connected to the first pad; a second dielectric structure spaced apart from the first dielectric structure across the first semiconductor chip; a first gap-fill layer between the first dielectric structure and the second dielectric structure; a second semiconductor chip in contact with the second dielectric structure; and a second gap-fill layer that surrounds the second semiconductor chip. The first pad may include a first conductive layer and a second conductive layer in the first conductive layer. The first conductive layer may include: a first part between the bump and the second conductive layer; and a second part that surrounds the second conductive layer. The first part of the first conductive layer may include a surface in contact with a bottom surface of the second conductive layer. A top surface of the second part of the first conductive layer and a top surface of the second conductive layer may be in contact with the first chip pad.

According to another aspect of the disclosure, a method of fabricating a semiconductor package may include: forming a first dielectric structure on a carrier substrate; forming a plurality of alignment keys and a first pad in the first dielectric structure at a same manufacturing step; bonding a first semiconductor chip to the first dielectric structure; removing the carrier substrate to expose the first pad and the alignment keys; and forming a bump electrically connected to the first pad.

DETAILED DESCRIPTION OF EMBODIMENTS

The following will describe in detail a semiconductor package and its fabrication method according to some embodiments of the present inventive concepts in conjunction with the accompanying drawings.

In the present disclosure, the term “surround” may used to describe covering, enveloping, or enclosing all sides or a portion of an object. For instance, when describing a first layer surrounded by a second layer, it may be interpreted as either all sides of the first layer being covered by the second layer, or the first layer being partially covered by the second layer, with a portion of the first layer left exposed.

FIG.1Aillustrates a cross-sectional view showing a semiconductor package according to some embodiments.FIG.1Billustrates an enlarged view showing section E1ofFIG.1A.

Referring toFIGS.1A and1B, a semiconductor package may include bumps BP, bump connection pads11, a first dielectric structure IS1, first pads PA1, dummy pads DP, key patterns KP, a first semiconductor chip SC1, a first gap-fill layer GP1, a second dielectric structure IS2, second pads PA2, a second semiconductor chip SC2, a second gap-fill layer GP2, a first bonding layer BL1, a second bonding layer BL2, and a dummy substrate DS. The key pattern KP may refer to specific geometric or graphical pattern on a semiconductor package that serves as a reference or alignment feature. The key pattern KP may be also referred to as an alignment mark or an alignment key. The term “pad” may be also referred to as a contact pad or a connection pad.

The first dielectric structure IS1may include a first dielectric layer21and a second dielectric layer22on the first dielectric layer21. Each of the first dielectric layer21and the second dielectric layer22may have a plate shape elongated along a plane defined by a first direction DI and a second direction D2. The first direction D1and the second direction D2may be perpendicular to each other. For example, the first direction D1and the second direction D2may be horizontal directions that are orthogonal to each other. The first dielectric layer21and the second dielectric layer22may include their dielectric materials different from each other. For example, the first dielectric layer21may include silicon oxide, and the second dielectric layer22may include silicon carbonitride, silicon nitride, or silicon carbon oxynitride.

A top surface11_T of the bump connection pad11may be in contact with a bottom surface21_B of the first dielectric layer21of the first dielectric structure IS1. The bump connection pad11may include a conductive material. For example, the bump connection pad11may include copper.

The bump BP may be in contact with a bottom surface of the bump connection pad11. The first pad PA1may be electrically connected through the bump connection pad11to the bump BP. The first pad PA1may be disposed between the bump BP and a subsequently described first chip pad52of the first semiconductor chip SC1. The semiconductor package may be electrically connected through the bump BP to an external apparatus. The bump BP may include a conductive material. For example, the bump BP may include at least one selected from copper, tin, silver, and gold.

The first pads PA1, the dummy pads DP, and the key patterns KP may penetrate in a third direction D3through the first dielectric layer21and the second dielectric layer22of the first dielectric structure IS1. The third direction D3may be perpendicular to the first direction D1and the second direction D2. For example, the third direction D3may be a vertical direction perpendicular to the first direction DI and the second direction D2.

The first pads PA1, the dummy pads DP, and the key patterns KP may be placed within or surrounded by the first dielectric structure IS1. The first pads PA1, the dummy pads DP, and the key patterns KP may be disposed in the first dielectric structure IS1. A bottom surface PA1_B of the first pad PA1may be in contact with the top surface11_T of the bump connection pad11. A bottom surface DP_B of the dummy pad DP may be in contact with the top surface11_T of the bump connection pad11. The key pattern KP may be spaced apart from the bump connection pad11. A bottom surface KP_B of the key pattern KP may be externally exposed. The first pads PA1and the dummy pads DP may be disposed between the key patterns KP. For example, the key patterns KP may be positioned between two opposing ends of the semiconductor package in the first direction D1, and the first pads PA1and the dummy pads DP may be placed between the spaced-apart key patterns KP.

The first pads PA1may be electrically connected to the first semiconductor chip SC1. The dummy pads DP and the key patterns KP may be electrically spaced apart from the first semiconductor chip SC1.

The first pad PA1may include a first conductive layer31and a second conductive layer32surrounded by the first conductive layer31. The second conductive layer32may be disposed in the first conductive layer31. The bottom surface PA1_B of the first pad PA1may be a bottom surface of the first conductive layer31.

A distance in the third direction D3between the bump BP and the bottom surface of the first conductive layer31may be less than a distance in the third direction D3between the bump BP and a bottom surface32_B of the second conductive layer32.

The dummy pad DP may include a first dummy layer36and a second dummy layer37surrounded by the first dummy layer36. The second dummy layer37may be disposed in the first dummy layer36. The bottom surface DP_B of the dummy pad DP may be a bottom surface of the first dummy layer36.

A distance L1in the third direction D3between the bump BP and the bottom surface of the first dummy layer36may be less than a distance L2in the third direction D3between the bump BP and a bottom surface37_B of the second dummy layer37.

The key pattern KP may include a first pattern layer41and a second pattern layer42surrounded by the first pattern layer41. The second pattern layer42may be disposed in the first pattern layer41. The bottom surface KP_B of the key pattern KP may be a bottom surface of the first pattern layer41.

The first semiconductor chip SC1may be provided on the first dielectric structure IS1. A bottom surface of the first semiconductor chip SC1may be in contact with a top surface22_T of the second dielectric layer22of the first dielectric structure IS1. The first semiconductor chip SC1may be hybrid-bonded to the first dielectric structure IS1and the first pads PA1.

The first semiconductor chip SC1may include a first chip dielectric layer51, first chip pads52in the first chip dielectric layer51, a first wiring structure53on the first chip dielectric layer51, and a first substrate54on the first wiring structure53. A bottom surface of the first chip dielectric layer51may be in contact with the top surface22_T of the second dielectric layer22of the first dielectric structure IS1. The first chip dielectric layer51may include a dielectric material the same as that of the second dielectric layer22. For example, the first chip dielectric layer51may include silicon carbonitride, silicon nitride, or silicon carbon oxynitride.

The first chip pads52may be surrounded by the first chip dielectric layer51. A bottom surface52_B of the first chip pad52may be in contact with a top surface PA1_T of the first pad PA1. The dummy pad DP may be spaced apart from the first chip pad52. The key pattern KP may be spaced apart from the first chip pad52. The first chip pad52may include a conductive material. For example, the first chip pad52may include copper.

The first wiring structure53may include a first wiring dielectric layer53_1and first conductive structures53_2in the first wiring dielectric layer53_1. The first wiring dielectric layer53_1of the first wiring structure53may be provided on the first chip dielectric layer51. The first wiring dielectric layer53_1of the first wiring structure53may include a dielectric material. For example, the first wiring dielectric layer53_1of the first wiring structure53may include silicon oxide. In some embodiments, the first wiring dielectric layer53_1of the first wiring structure53may be a multiple layer including a plurality of dielectric layers.

The first conductive structure53_2of the first wiring structure53may include, for example, at least one selected from a conductive pad, a conductive via, and a conductive line. The first conductive structure53_2of the first wiring structure53may include a conductive material. The first conductive structure53_2of the first wiring structure53may be electrically connected to the first chip pad52.

The first substrate54may be a semiconductor substrate, a dielectric substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. For example, the semiconductor substrate may include silicon, germanium, silicon-germanium, gallium-phosphorus, or gallium-arsenic.

The first semiconductor chip SC1may further include a semiconductor device. For example, the first semiconductor chip SC1may be a logic semiconductor chip including a logic semiconductor device or a memory semiconductor chip including a memory semiconductor device. The logic semiconductor chip may be, for example, a central processing unit (CPU), a graphic processing unit (GPU), or an application processor (AP). The memory semiconductor device may be, for example, a dynamic random access memory (DRAM) semiconductor device, a static RAM (SRAM) semiconductor device, a thyristor RAM (TRAM) semiconductor device, a zero capacitor RAM (ZRAM) semiconductor device, a twin transistor RAM (TTRAM) semiconductor device, a Flash memory semiconductor device, a magnetic RAM (MRAM) semiconductor device, a spin-transfer torque RAM (STT-MRAM) semiconductor device, a ferroelectric RAM (FRAM) semiconductor device, a phase change RAM (PRAM) semiconductor device, a polymer RAM, or an insulator resistance change memory semiconductor device.

The first gap-fill layer GP1may be provided on the first dielectric structure IS1and the first semiconductor chip SC1. The first gap-fill layer GP1may surround the first semiconductor chip SC1. The first gap-fill layer GP1may be in contact with the top surface22_T of the second dielectric layer22, a top surface SC1_T of the first semiconductor chip SC1, and a sidewall SC1_S of the first semiconductor chip SC1. The top surface SC1_T of the first semiconductor chip SC1may be a top surface of the first substrate54. The sidewall SC1_S of the first semiconductor chip SC1may include a sidewall of the first substrate54, a sidewall of the first wiring structure53, and a sidewall of the first chip dielectric layer51. The first gap-fill layer GP1may include a dielectric material. For example, the first gap-fill layer GP1may include silicon oxide.

A top surface DP_T of the dummy pad DP may be in contact with a bottom surface GP1_B of the first gap-fill layer GP1. A top surface KP_T of the key pattern KP may be in contact with the bottom surface GP1_B of the first gap-fill layer GP1. In some embodiments, the top surface DP_T of the dummy pad DP may be in contact with the bottom surface of the first chip dielectric layer51.

The first semiconductor chip SC1may further include through vias VI. The through vias VI may extend in the third direction D3. The through vias VI may penetrate the first gap-fill layer GP1and the first substrate54. The through via VI may be electrically connected to the first conductive structure53_2of the first wiring structure53. The through via VI may include a conductive material. For example, the through via VI may include copper.

The second dielectric structure IS2may be provided on the first gap-fill layer GP1. The second dielectric structure IS2may include a third dielectric layer23and a fourth dielectric layer24on the third dielectric layer23. Each of the third dielectric layer23and the fourth dielectric layer24may have a plate shape elongated along a plane defined by the first direction D1and the second direction D2. The third dielectric layer23and the fourth dielectric layer24may include their dielectric materials different from each other. For example, the third dielectric layer23may include silicon oxide, and the fourth dielectric layer24may include silicon carbonitride, silicon nitride, or silicon carbon oxynitride.

The second dielectric structure IS2may be spaced apart in the third direction D3from the first dielectric structure IS1. The first semiconductor chip SC1may be provided between the first dielectric structure IS1and the second dielectric structure IS2. The first gap-fill layer GP1may be provided between the first dielectric structure IS1and the second dielectric structure IS2.

The second pads PA2may penetrate in the third direction D3through the third dielectric layer23and the fourth dielectric layer24of the second dielectric structure IS2. A bottom surface of the second pad PA2may be in contact with a top surface of the through via VI and a top surface of the first gap-fill layer GP1. The second pads PA2may be surrounded by the second dielectric structure IS2. The second pads PA2may be provided in the second dielectric structure IS2. The second pad PA2may be electrically connected through the through via VI to the first semiconductor chip SC1.

The second pad PA2may include a third conductive layer33and a fourth conductive layer34surrounded by the third conductive layer33. The fourth conductive layer34may be disposed in the third conductive layer33. The bottom surface of the second pad PA2may be a bottom surface of the third conductive layer33.

The second semiconductor chip SC2may be provided on the second dielectric structure IS2. A bottom surface of the second semiconductor chip SC2may be in contact with a top surface of the fourth dielectric layer24. The second semiconductor chip SC2may be hybrid-bonded to the second dielectric structure IS2and the second pads PA2.

The second semiconductor chip SC2may include a second chip dielectric layer61, second chip pads62in the second chip dielectric layer61, a second wiring structure63on the second chip dielectric layer61, and a second substrate64on the second wiring structure63. A bottom surface of the second chip dielectric layer61may be in contact with a top surface of the fourth dielectric layer24of the second dielectric structure IS2. The second chip dielectric layer61may include a dielectric material the same as that of the fourth dielectric layer24. For example, the second chip dielectric layer61may include silicon carbonitride, silicon nitride, or silicon carbon oxynitride. In some embodiments, the second chip dielectric layer61may be a multiple layer including a plurality of dielectric layers.

The second chip pads62may be surrounded by the second chip dielectric layer61. A bottom surface of the second chip pad62may be in contact with a top surface of the second pad PA2. The second chip pad62may include a conductive material. For example, the second chip pad62may include copper.

The second wiring structure63may include a second wiring dielectric layer and second conductive structures in the second wiring dielectric layer. The second wiring dielectric layer of the second wiring structure63may be provided on the second chip dielectric layer61. The second wiring dielectric layer of the second wiring structure63may include a dielectric material. For example, the second wiring dielectric layer of the second wiring structure63may include silicon oxide. In some embodiments, the second wiring dielectric layer of the second wiring structure63may be a multiple layer including a plurality of dielectric layers.

The second conductive structure of the second wiring structure63may include, for example, at least one selected from a conductive pad, a conductive via, and a conductive line. The second conductive structure of the second wiring structure63may include a conductive material. The second conductive structure of the second wiring structure63may be electrically connected to the second chip pad62.

The second substrate64may be a semiconductor substrate, a dielectric substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

The second semiconductor chip SC2may further include a semiconductor device. For example, the second semiconductor chip SC2may be a logic semiconductor chip including a logic semiconductor device or a memory semiconductor chip including a memory semiconductor device.

The second gap-fill layer GP2may be provided on the second dielectric structure IS2and the second semiconductor chip SC2. The second gap-fill layer GP2may surround the second semiconductor chip SC2. The second gap-fill layer GP2may be in contact with the top surface of the fourth dielectric layer24and a sidewall SC2_S of the second semiconductor chip SC2. The sidewall SC2_S of the second semiconductor chip SC2may include a sidewall of the second substrate64, a sidewall of the second wiring structure63, and a sidewall of the second chip dielectric layer61. The second gap-fill layer GP2may include a dielectric material. For example, the second gap-fill layer GP2may include silicon oxide.

The first bonding layer BL1may be provided on the second gap-fill layer GP2and the second substrate64of the second semiconductor chip SC2. The second bonding layer BL2may be provided on the first bonding layer BL1. The first bonding layer BL1and the second bonding layer BL2may include the same dielectric material. For example, the first bonding layer BL1and the second bonding layer BL2may include silicon carbonitride, silicon nitride, or silicon carbon oxynitride.

The dummy substrate DS may be provided on the second bonding layer BL2. The dummy substrate DS may be a semiconductor substrate, a dielectric substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

In some embodiments, the semiconductor package may not include any of the first bonding layer BL1, the second bonding layer BL2, and the dummy substrate DS. In this case, a method of fabricating the semiconductor package may include forming a glue layer on the dummy substrate DS, attaching the glue layer to the second gap-fill layer GP2and the second semiconductor chip SC2, and removing the dummy substrate DS and the glue layer.

The first conductive layer31may include a first part P1in contact with the top surface11_T of the bump connection pad11and a second part P2in contact with the bottom surface52_B of the first chip pad52. The second part P2of the first conductive layer31may surround the second conductive layer32. The second conductive layer32may be spaced apart from the bump connection pad11. The first part P1of the first conductive layer31may be interposed between the second conductive layer32and the bump connection pad11. The second part P2of the first conductive layer31may be provided on the first part P1of the first conductive layer31. The second part P2of the first conductive layer31may be located at the same level as that of the second conductive layer32. A distance in the third direction D3between the bump connection pad11and the second part P2of the first conductive layer31may be the same as a distance in the third direction D3between the bump connection pad11and the second conductive layer32.

The first part P1of the first conductive layer31may include a first surface P1_S1in contact with the top surface11_T of the bump connection pad11and a second surface P1_S2in contact with the bottom surface32_B of the second conductive layer32. The first surface P1_S1of the first part P1of the first conductive layer31may be the bottom surface PA1_B of the first pad PA1and the bottom surface of the first conductive layer31. The first surface P1_S1and the second surface P1_S2of the first part PI of the first conductive layer31may be parallel to each other. The first surface P1_S1and the second surface P1_S2of the first part Pl of the first conductive layer31may be parallel to the first direction D1and the second direction D2. The first surface P1_S1and the second surface P1_S2of the first part P1of the first conductive layer31may stand opposite to each other. An area (e.g., a planar area) at the first surface P1_S1of the first part P1of the first conductive layer31may be greater than an area (e.g., a planar area) at the second surface P1_S2of the first part P1of the first conductive layer31.

The second part P2of the first conductive layer31may include an outer sidewall P2_OS and an inner sidewall P2_IS. The inner sidewall P2_IS of the second part P2of the first conductive layer31may be in contact with an outer sidewall32_OS of the second conductive layer32. The outer sidewall P2_OS of the second part P2of the first conductive layer31may be in contact with the first dielectric layer21and the second dielectric layer22of the first dielectric structure IS1. The outer sidewall P2_OS and the inner sidewall P2_IS of the second part P2of the first conductive layer31may be parallel to the third direction D3. The outer sidewall P2_OS and the inner sidewall P2_IS of the second part P2of the first conductive layer31may stand opposite to each other.

The second part P2of the first conductive layer31may include a top surface P2_T in contact with the bottom surface52_B of the first chip pad52. The second conductive layer32may include a top surface32_T in contact with the bottom surface52_B of the first chip pad52. The top surface P2_T of the second part P2of the first conductive layer31may be coplanar with the top surface32_T of the second conductive layer32. The top surface P2_T of the second part P2of the first conductive layer31may be located at the same level as that of the top surface32_T of the second conductive layer32. The top surface P2_T of the second part P2of the first conductive layer31may be a top surface of the first conductive layer31. The top surface and the bottom surface of the first conductive layer31may stand opposite to each other. The top surface and the bottom surface of the first conductive layer31may be parallel to each other.

The area (or the planar area) at the first surface P1_S1of the first part P1of the first conductive layer31may be greater than an area (e.g., a planar area) at the top surface P2_T of the second part P2of the first conductive layer31. The top surface P2_T of the second part P2of the first conductive layer31may have a ring shape (e.g., a tetragonal ring shape or a circular ring shape) when viewed in plan. An area (e.g., a planar area) at the top surface32_T of the second conductive layer32may be greater than the area (e.g., the planar area) at the top surface P2_T of the second part P2of the first conductive layer31.

The first part P1of the first conductive layer31may have a plate shape (e.g., a tetragonal plate shape or a circular plate shape). The second part P2of the first conductive layer31may have a pipe shape (e.g., a tetragonal pipe shape or a circular pipe shape). The first part P1of the first conductive layer31may be located at a level lower than that of the second part P2of the first conductive layer31. A distance in the third direction D3between the first part P1of the first conductive layer31and the first chip pad52of the first semiconductor chip SC1may be greater than a distance in the third direction D3between the second part P2of the first conductive layer31and the first chip pad52of the first semiconductor chip SC1.

A width W1in the first direction D1of the bump connection pad11may be greater than a width W2in the first direction D1of the first pad PA1. A width W3in the first direction D1of the first chip pad52may be greater than the width W2in the first direction D1of the first pad PA1. The width W2in the first direction D1of the first pad PA1may be a width in the first direction D1of the first conductive layer31. A width W4in the first direction D1of the second conductive layer32may be less than the width in the first direction D1of the first conductive layer31.

The first conductive layer31and the second conductive layer32may include their conductive materials different from each other. The first conductive layer31may include, for example, at least one selected from tantalum nitride, tantalum, titanium nitride, and titanium, but the present inventive concepts are not limited thereto. The second conductive layer32may include, for example, copper.

In some embodiments, the first conductive layer31may be a multiple layer including a first layer and a second layer. In this case, the first layer may include one of tantalum nitride, tantalum, titanium nitride, and titanium, and the second layer may include another of tantalum nitride, tantalum, titanium nitride, and titanium.

The first dummy layer36may include a first part P3in contact with the top surface11_T of the bump connection pad11and a second part P4in contact with a bottom surface GP1_B of the first gap-fill layer GP1. The second part P4of the first dummy layer36may surround the second dummy layer37. The second dummy layer37may be spaced apart from the bump connection pad11. The first part P3of the first dummy layer36may be interposed between the second dummy layer37and the bump connection pad11. The second part P4of the first dummy layer36may be provided on the first part P3of the first dummy layer36. The second part P4of the first dummy layer36may be located at the same level as that of the second dummy layer37. A distance in the third direction D3between the bump connection pad11and the second part P4of the first dummy layer36may be the same as a distance in the third direction D3between the bump connection pad11and the second dummy layer37.

The first part P3of the first dummy layer36may include a first surface P3_S1in contact with the top surface11_T of the bump connection pad11and a second surface P3_S2in contact with the bottom surface37_B of the second dummy layer37. The first surface P3_S1of the first part P3of the first dummy layer36may be the bottom surface DP_B of the dummy pad DP. The first surface P3_S1and the second surface P3_S2of the first part P3of the first dummy layer36may be parallel to each other. The first surface P3_S1and the second surface P3_S2of the first part P3of the first dummy layer36may be parallel to the first direction D1and the second direction D2. The first surface P3_S1and the second surface P3_S2of the first part P3of the first dummy layer36may stand opposite to each other. An area (e.g., a planar area) at the first surface P3_S1of the first part P3of the first dummy layer36may be greater than an area (e.g., a planar area) at the second surface P3_S2of the first part P3of the first dummy layer36.

The second part P4of the first dummy layer36may include an outer sidewall P4_OS and an inner sidewall P4_IS. The inner sidewall P4_IS of the second part P4of the first dummy layer36may be in contact with an outer sidewall37_OS of the second dummy layer37. The outer sidewall P4_OS of the second part P4of the first dummy layer36may be in contact with the first dielectric layer21and the second dielectric layer22of the first dielectric structure IS1. The outer sidewall P4_OS and the inner sidewall P4_IS of the second part P4of the first dummy layer36may be parallel to the third direction D3. The outer sidewall P4_OS and the inner sidewall P4_IS of the second part P4of the first dummy layer36may stand opposite to each other.

The second part P4of the first dummy layer36may include a top surface P4_T in contact with the bottom surface GP1_B of the first gap-fill layer GP1. The second dummy layer37may include a top surface37_T in contact with the bottom surface GP1_B of the first gap-fill layer GP1. The top surface P4_T of the second part P4of the first dummy layer36may be coplanar with the top surface37_T of the second dummy layer37. The top surface P4_T of the second part P4of the first dummy layer36may be located at the same level as that of the top surface37_T of the second dummy layer37. The top surface P4_T of the second part P4of the first dummy layer36may be a top surface of the first dummy layer36. The area (or the planar area) at the first surface P3_S1of the first part P3of the first dummy layer36may be greater than an area (e.g., a planar area) at the top surface P4_T of the second part P4of the first dummy layer36. The top surface P4_T of the second part P4of the first dummy layer36may have a ring shape (e.g., a tetragonal ring shape or a circular ring shape) when viewed in plan. An area (e.g., a planar area) at the top surface37_T of the second dummy layer37may be greater than the area (or the planar area) at the top surface P4_T of the second part P4of the first dummy layer36.

The first part P3of the first dummy layer36may have a plate shape (or a tetragonal plate shape or a circular plate shape). The second part P4of the first dummy layer36may have a pipe shape (or a tetragonal pipe shape or a circular pipe shape). The first part P3of the first dummy layer36may be located at a level lower than that of the second part P4of the first dummy layer36. A distance in the third direction D3between the first part P3of the first dummy layer36and the first chip pad52of the first semiconductor chip SC1may be greater than a distance in the third direction D3between the second part P4of the first dummy layer36and the second chip pad52of the first semiconductor chip SC1.

The width W1in the first direction D1of the bump connection pad11may be greater than a width W5in the first direction D1of the dummy pad DP. The width W3in the first direction D1of the first chip pad52may be greater than the width W5in the first direction D1of the dummy pad DP.

The first dummy layer36and the second dummy layer37may include their conductive materials different from each other. The first dummy layer36may include at least one selected from tantalum nitride, tantalum, titanium nitride, and titanium, but the present inventive concepts are not limited thereto. The second dummy layer37may include, for example, copper.

In some embodiments, the first dummy layer36may be a multiple layer including a first layer and a second layer. In this case, the first layer may include one of tantalum nitride, tantalum, titanium nitride, and titanium, and the second layer may include another of tantalum nitride, tantalum, titanium nitride, and titanium.

The first pattern layer41may include a first part P5externally exposed and a second part P6in contact with the bottom surface GP1_B of the first gap-fill layer GP1. The second part P6of the first pattern layer41may surround the second pattern layer42. The second part P6of the first pattern layer41may be provided on the first part P5of the first pattern layer41. The second part P6of the first pattern layer41may be located at the same level as that of the second pattern layer42. A distance in the third direction D3between the bump connection pad11and the second part P6of the first pattern layer41may be the same as a distance in the third direction D3between the bump connection pad11and the second pattern layer42.

The first part P5of the first pattern layer41may include a first surface P5_S1externally exposed and a second surface P5_S2in contact with a bottom surface42_B of the second pattern layer42. The first surface P5_S1of the first part P5of the first pattern layer41may be the bottom surface DP_B of the key pattern KP. The first surface P5_S1of the first part P5of the first pattern layer41may be coplanar with the first surface P3_S1of the first part P3of the first dummy layer36, the first surface P1_S1of the first part P1of the first conductive layer31, and the bottom surface21_B of the first dielectric layer21. The first surface P5_S1of the first part P5of the first pattern layer41may be located at the same level as that of the first surface P3_S1of the first part P3of the first dummy layer36, that of the first surface P1_S1of the first part P1of the first conductive layer31, and that of the bottom surface21_B of the first dielectric layer21.

The first surface P5_S1and the second surface P5_S2of the first part P5of the first pattern layer41may be parallel to each other. The first surface P5_S1and the second surface P5_S2of the first part P5of the first pattern layer41may be parallel to the first direction D1and the second direction D2. The first surface P5_S1and the second surface P5_S2of the first part P5of the first pattern layer41may stand opposite to each other. An area (e.g., a planar area) at the first surface P5_S1of the first part P5of the first pattern layer451may be greater than an area (e.g., a planar area) at the second surface P5_S2of the first part P5of the first pattern layer41.

The second part P6of the first pattern layer41may include an outer sidewall P6_OS and an inner sidewall P6_IS. The inner sidewall P6_IS of the second part P6of the first pattern layer41may be in contact with an outer sidewall42_OS of the second pattern layer42. The outer sidewall P6_OS of the second part P6of the first pattern layer41may be in contact with the first dielectric layer21and the second dielectric layer22of the first dielectric structure IS1. The outer sidewall P6_OS and the inner sidewall P6_IS of the second part P6of the first pattern layer41may be parallel to the third direction D3. The outer sidewall P6_OS and the inner sidewall P6_IS of the second part P6of the first pattern layer41may stand opposite to each other.

The second part P6of the first pattern layer41may include a top surface P6_T in contact with the bottom surface GP1_B of the first gap-fill layer GP1. The second dummy layer42may include a top surface42_T in contact with the bottom surface GP1_B of the first gap-fill layer GP1. The top surface P6_T of the second part P6of the first pattern layer41may be coplanar with the top surface42_T of the second pattern layer42, the top surface P4_T of the second part P4of the first dummy layer36, the top surface37_T of the second dummy layer37, the top surface P2_T of the second part P2of the first conductive layer31, the top surface32_T of the second conductive layer32, and the top surface22_T of the second dielectric layer22. The top surface P6_T of the second part P6of the first pattern layer41may be located at the same level as that of the top surface42_T of the second pattern layer42, that of the top surface P4_T of the second part P4of the first dummy layer36, that of the top surface37_T of the second dummy layer37, that of the top surface P2_T of the second part P2of the first conductive layer31, that of the top surface32_T of the second conductive layer32, and that of the top surface22_T of the second dielectric layer22. The top surface P6_T of the second part P6of the first pattern layer41may be a top surface of the first pattern layer41. The area (or the planar area) at the first surface P5_S1of the first part P5of the first pattern layer41may be greater than an area (e.g., a planar area) at the top surface P6_T of the second part P6of the first pattern layer41. An area (e.g., a planar area) at the top surface42_T of the second pattern layer42may be greater than the area (e.g., the planar area) at the top surface P6_T of the second part P6of the first pattern layer41.

The first part P5of the first pattern layer41may be located at a level lower than that of the second part P6of the first pattern layer41. A distance in the third direction D3between the first part P5of the first pattern layer41and the first chip pad52of the first semiconductor chip SC1may be greater than a distance in the third direction D3between the second part P6of the first pattern layer41and the first chip pad52of the first semiconductor chip SC1.

The width W1in the first direction D1of the bump connection pad11may be greater than a width W6in the first direction D1of the key pattern KP. The width W3in the first direction D1of the first chip pad52may be greater than the width W6in the first direction D1of the key pattern KP.

The first pattern layer41and the second pattern layer42may include their conductive materials different from each other. The first pattern layer41may include at least one selected from tantalum nitride, tantalum, titanium nitride, and titanium, but the present inventive concepts are not limited thereto. The second pattern layer42may include, for example, copper.

In some embodiments, the first pattern layer41may be a multiple layer including a first layer and a second layer. In this case, the first layer may include one of tantalum nitride, tantalum, titanium nitride, and titanium, and the second layer may include another of tantalum nitride, tantalum, titanium nitride, and titanium.

The first conductive layer31, the first dummy layer36, and the first pattern layer41may include the same conductive material. The second conductive layer32, the second dummy layer37, and the second pattern layer42may include the same conductive material.

FIGS.2,3A,3B,4,5,6,7,8, and9illustrate plan and cross-sectional views showing a method of fabricating a semiconductor package according to some embodiments.

Referring toFIG.2, a first dielectric structure IS1may be formed on a carrier substrate CA. The carrier substrate CA may be, for example, a silicon substrate. The formation of the first dielectric structure IS1may include forming a first dielectric layer21on the carrier substrate CA, and forming a second dielectric layer22on the first dielectric layer21.

First pads PA1, dummy pads DP, and key patterns KP may be formed in the first dielectric structure IS1. The formation of the first pads PA1, the dummy pads DP, and the key patterns KP may include exposing the carrier substrate CA by forming first openings OP1that penetrate the first dielectric structure IS1, forming a first preliminary layer on the carrier substrate CA and the first dielectric structure IS1, forming a second preliminary layer on the first preliminary layer, and removing an upper portion of the first preliminary layer and an upper portion of the second preliminary layer. In some embodiments, the second preliminary layer may be formed by an electroplating process in which the first preliminary layer is used as a seed layer. The first preliminary layer, which is used as a seed layer, becomes the first conductive layers31, the first dummy layers36, and the first pattern layers41. The second preliminary layer becomes the second conductive layers32, the second dummy layers37, and the second pattern layers42. According to embodiments of the present disclosure, the key patterns KP may be formed on the carrier substrate at the same time or at the same manufacturing process step as the first pads PA1and the dummy pads DP. Consequently, the key patterns KP, the first pads PA1, and the dummy pads DP have the same structure of the seed layer, and the process of forming the first pads PA1and the dummy pads DP may be omitted after removal of the carrier substrate. Each of the key patterns KP, the first pads PA1, and the dummy pads DP may have an inner conductive layer and an outer conductive layer that covers the inner conductive layer. The inner conductive layer may correspond to the second conductive layers32, the second dummy layers37, and the second pattern layers42. The outer conductive layer may correspond to the first conductive layers31, the first dummy layers36, and the first pattern layers41.

The first preliminary layer and the second preliminary layer may include their conductive materials different from each other. The first preliminary layer may include at least one selected from tantalum nitride, tantalum, titanium nitride, and titanium, but the present inventive concepts are not limited thereto. The second preliminary layer may include, for example, copper. The upper portion of the first preliminary layer may be removed such that the first preliminary layer may be separated into the first conductive layers31, the first dummy layers36, and the first pattern layers41. The upper portion of the second preliminary layer may be removed such that the second preliminary layer may be separated into the second conductive layers32, the second dummy layers37, and the second pattern layers42. The upper portion of the first preliminary layer may refer to a portion protruding from or extending beyond an outermost surface of the first conductive layers31, the first dummy layers36, and the first pattern layers41, and may be considered a redundant portion. Similarly, the upper portion of the second preliminary layer may refer to a portion protruding from or extending beyond an outermost surface of the second conductive layers32, the second dummy layers37, and the second pattern layers42, and may be considered a redundant portion.

Referring toFIGS.3A and3B, a plurality of first semiconductor chips SC1may be formed. The formation of the first semiconductor chip SC1may include forming through vias VI and a first wiring structure53on a first substrate54, and forming a first chip dielectric layer51and first chip pads52on the first wiring structure53.

The plurality of first semiconductor chips SC1may be bonded to the first dielectric structure IS1. The plurality of first semiconductor chips SC1may be hybrid-bonded to the first dielectric structure IS1and the first pads PA1. The first chip dielectric layer51of the first semiconductor chip SC1may be bonded to the second dielectric layer22of the first dielectric structure IS1. The first chip pad52of the first semiconductor chip SC1may be bonded to the first pad PA1.

Referring toFIG.4, an upper portion of the first substrate54may be removed. The upper portion of the first substrate54may be removed to expose a top surface VI_T of the through via VI and a portion of a sidewall VI_S of the through via VI.

Referring toFIG.5, a first gap-fill layer GP1may be formed to surround the first semiconductor chip SC1. The first gap-fill layer GP1may be in contact with a top surface of the second dielectric layer22of the first dielectric structure IS1, a top surface of the dummy pad DP, a top surface of the key pattern KP, a sidewall of the first semiconductor chip SC1, a top surface of the first semiconductor chip SC1, and the sidewall VI_S of the through via VI.

A second dielectric structure IS2may be formed on the first gap-fill layer GP1. The second dielectric structure IS2may include a third dielectric layer23provided on the first gap-fill layer GP1, and a fourth dielectric layer24provided on the third dielectric layer23. The second dielectric structure IS2includes second pads PA2which are aligned to contact the through vias VI of the first dielectric structure IS1. The top surfaces VI_T of the through vias VI may be in contact with a bottom surface of the third dielectric layer23.

Referring toFIG.6, the second pads PA2may be formed in the second dielectric structure IS2. The formation of the second pads PA2may include exposing the through vias VI and the first gap-fill layer GP1by forming second openings OP2that penetrate the second dielectric structure IS2, forming a third preliminary layer on the through vias VI, the first gap-fill layer GP1, and the second dielectric structure IS2, forming a fourth preliminary layer on the third preliminary layer, and removing an upper portion of the third preliminary layer and an upper portion of the fourth preliminary layer. In some embodiments, the fourth preliminary layer may be formed by an electroplating process in which the third preliminary layer is used as a seed.

Conductive materials included in the third preliminary layer and the fourth preliminary layer may be different from each other. For example, the third preliminary layer may include at least one selected from tantalum nitride, tantalum, titanium nitride, and titanium, while embodiments of the present disclosure are not limited thereto. The fourth preliminary layer may include, for example, copper. The upper portion of the third preliminary layer may be removed such that the third preliminary layer may be separated into third conductive layers33. The upper portion of the fourth preliminary layer may be removed such that the fourth preliminary layer may be separated into fourth conductive layers34.

Referring toFIG.7, a plurality of second semiconductor chips SC2may be formed. The formation of the second semiconductor chip SC2may include forming a second wiring structure63on a second substrate64, and forming a second chip dielectric layer61and second chip pads62on the second wiring structure63.

The plurality of second semiconductor chips SC2may be bonded to the second dielectric structure IS2. The plurality of second semiconductor chips SC2may be hybrid-bonded to the second dielectric structure IS2and the second pads PA2. The second chip dielectric layer61of the second semiconductor chip SC2may be bonded to the fourth dielectric layer24of the second dielectric structure IS2. The second chip pad62of the second semiconductor chip SC2may be bonded to the second pad PA2.

Referring toFIG.8, a second gap-fill layer GP2may be formed to surround the second semiconductor chip SC2. The second gap-fill layer GP2may be in contact with a top surface of the fourth dielectric layer24and a sidewall of the second semiconductor chip SC2.

A first bonding layer BL1may be formed on the second gap-fill layer GP2. A second bonding layer BL2may be formed on a dummy substrate DS. A wafer bonding process may be employed to bond the first bonding layer BL1and the second bonding layer BL2to each other.

Referring toFIG.9, the carrier substrate CA and the dummy substrate DS may be turned upside down. Afterwards, the carrier substrate CA may be removed. In some embodiments, the carrier substrate CA may be removed by a grinding process. The carrier substrate CA may be removed to expose the first pads PA1, the dummy pads DP, and the key patterns KP.

A scribing line SB may be defined which will be discussed below. Neighboring scribing lines SB may be provided therebetween with the key patterns KP, the dummy pads DP, the first pads PA1, the first semiconductor chip SC1, the second pads PA2, and the second semiconductor chip SC2.

Referring toFIG.1A, bump connection pads11and bumps BP may be formed. The key patterns KP may serve as an alignment key in a process for forming the bump connection pads11and the bumps BP. In some embodiments, the key patterns KP may serve as an alignment key in a process other than the process for forming the bump connection pads11and the bumps BP.

A scribing process may be performed along the scribing lines SB. The scribing process may cut the first dielectric layer21and the second dielectric layer22of the first dielectric structure IS1, the first gap-fill layer GP1, the third dielectric layer23and the fourth dielectric layer24of the second dielectric structure IS2, the second gap-fill layer GP2, the first bonding layer BL1, the second bonding layer BL2, and the dummy substrate DS.

The first dielectric layer21may be cut and separated into a plurality of first dielectric layers21. The second dielectric layer22may be cut and separated into a plurality of second dielectric layers22. The third dielectric layer23may be cut and separated into a plurality of third dielectric layers23. The fourth dielectric layer24may be cut and separated into a plurality of fourth dielectric layers24. The first gap-fill layer GP1may be cut and separated into a plurality of first gap-fill layers GP1. The second gap-fill layer GP2may be cut and separated into a plurality of second gap-fill layers GP2. The first bonding layer BL1may be cut and separated into a plurality of first bonding layers BL1. The second bonding layer BL2may be cut and separated into a plurality of second bonding layers BL2. The dummy substrate DS may be cut and separated into a plurality of dummy substrates DS.

In a method of fabricating a semiconductor package according to some embodiments, as the key patterns KP and the first pads PA1are formed simultaneously with each other, it may be possible to omit a process for forming a pad in the first dielectric structure IS1after the carrier substrate CA is removed, which may result in a simplification of the fabrication of the semiconductor packages.

FIG.10illustrates a cross-sectional view showing a semiconductor package according to some embodiments. A semiconductor package ofFIG.10may be the same or substantially the same as the semiconductor package ofFIGS.1A and1B, except for the description below.

Referring toFIG.10, a second gap-fill layer GP2amay include a polymeric material. For example, the second gap-fill layer GP2amay include an epoxy resin.

None of a first bonding layer, a second bonding layer, and a dummy wafer may be provided on the second semiconductor chip SC2and the second gap-fill layer GP2a.The second semiconductor chip SC2and the second gap-fill layer GP2amay have externally exposed top surfaces.

FIG.11illustrates a cross-sectional view showing a method of fabricating a semiconductor package according to some embodiments.

Referring toFIG.11, similarly to that discussed inFIGS.2to7, a semiconductor package may include a carrier substrate CA, a first dielectric structure IS1, first pads PA1, dummy pads DP, key patterns KP, first semiconductor chips SC1, a first gap-fill layer GP1, a second dielectric structure IS2, second pads PA2, second semiconductor chips SC2, and a second gap-fill layer GP2a.

A glue layer GL may be formed on a dummy substrate DS. The glue layer GL may include an adhesive polymeric material. The glue layer GL may be attached to the second semiconductor chip SC2and the second gap-fill layer GP2a.

Referring toFIG.10, the dummy substrate DS and the carrier substrate CA may be turned upside down. After the carrier substrate CA is removed, bump connection pads11and bumps BP may be formed. A scribing process may be performed. The glue layer GL and the dummy substrate DS may be removed.

FIG.12illustrates a cross-sectional view showing a semiconductor package according to some embodiments. A semiconductor package ofFIG.12may be the same or substantially the same as the semiconductor package ofFIGS.1A and1B, except for the description below.

Referring toFIG.12, a first semiconductor chip SC1bmay have the same width as that of the first dielectric structure IS1, that of the second dielectric structure IS2, that of the first bonding layer BL1, that of the second bonding layer BL2, and that of the dummy substrate DS. For example, the first semiconductor chip SC1bmay have the same width in the first direction D1as that of the first dielectric structure IS1, that of the second dielectric structure IS2, that of the first bonding layer BL1, that of the second bonding layer BL2, and that of the dummy substrate DS. The first semiconductor chip SC1bmay have a sidewall coplanar with that of the first dielectric structure IS1, that of the second dielectric structure IS2, that of the first bonding layer BL1, that of the second bonding layer BL2, and that of the dummy substrate DS.

The first semiconductor chip SC1bmay include a first chip dielectric layer51b, first chip pads52, a first wiring structure53b,through vias VIb, and a first substrate54b.The first chip dielectric layer51b,the first wiring structure53b,and the first substrate54bmay have the same width as that of the first dielectric structure IS1, that of the second dielectric structure IS2, that of the first bonding layer BL1, that of the second bonding layer BL2, and that of the dummy substrate DS. For example, the first chip dielectric layer51b,the first wiring structure53b,and the first substrate54bmay have the same width in the first direction D1as that of the first dielectric structure IS1, that of the second dielectric structure IS2, that of the first bonding layer BL1, that of the second bonding layer BL2, and that of the dummy substrate DS. The first chip dielectric layer51b,the first wiring structure53b,and the first substrate54bmay have their sidewalls coplanar with that of the first dielectric structure IS1, that of the second dielectric structure IS2, that of the first bonding layer BL1, that of the second bonding layer BL2, and that of the dummy substrate DS.

The dummy pads DP and the key patterns KP may have their top surfaces in contact with a bottom surfaced of the first chip dielectric layer51b.The first substrate54bmay have a top surface in contact with a bottom surface of the third dielectric layer23. The through via VIb may have a top surface coplanar with that of the first substrate54b.The top surface of the through via VIb may be located at the same level as that of the top surface of the first substrate54b.

FIGS.13A and13Billustrate plan and cross-sectional views showing a method of fabricating a semiconductor package according to some embodiments.

Referring toFIGS.13A and13B, similarly to that discussed inFIG.2, there may be formed a carrier substrate CA, a first dielectric structure IS1, first pads PA1, dummy pads DP, and key patterns KP.

Through vias VIb may be formed on a first substrate54b.A first wiring structure53bmay be formed on the first substrate54b.A first chip dielectric layer51bmay be formed on the first wiring structure53b.First chip pads52may be formed in the first chip dielectric layer51b.

The first chip dielectric layer51band the first chip pads52may be bonded to the first pads PA1and a second dielectric layer22of the first dielectric structure IS1. The first chip dielectric layer51band the first chip pads52may be hybrid-bonded to the first pads PA1and the second dielectric layer22of the first dielectric structure IS1.

Referring toFIG.12, an upper portion of the first substrate54bmay be removed. Similarly to that discussed inFIGS.4to9, the semiconductor package may include a second dielectric structure IS2, second pads PA2, a second semiconductor chip SC2, a second gap-fill layer GP2, a first bonding layer BL1, a second bonding layer BL2, and a dummy substrate DS.

After the carrier substrate CA is removed, bump connection pads11and bumps BP may be formed. A scribing process may be performed. The scribing process may cut the first chip dielectric layer51b,the first wiring structure53b,and the first substrate54b.

The first chip dielectric layer51bmay be cut and separated into a plurality of first chip dielectric layers51b.The first wiring structure53bmay be cut and separated into a plurality of first wiring structures53b.The first substrate54bmay be cut and separated into a plurality of first substrates54b.A first semiconductor chip SC1bmay include the separated first chip dielectric layer51b,the separated first wiring structure53b,and the separated first substrate54b.

FIG.14illustrates an enlarged cross-sectional view showing a semiconductor package according to some embodiments. A semiconductor package ofFIG.14may be similar to the semiconductor package ofFIGS.1A and1B, except for the description below.

Referring toFIG.14, a semiconductor package may further include a connection structure CS between the first dielectric structure IS1and the bump connection pads11. The connection structure CS may be provided between the bump BP and the first dielectric structure IS1. A width in the first direction D1of the connection structure CS may be the same as a width in the first direction D1of the first dielectric structure IS1. A width in the second direction D2of the connection structure CS may be the same as a width in the second direction D2of the first dielectric structure IS1.

The connection structure CS may include a connection dielectric layer CI and connection conductive structures CC. A top surface of the connection dielectric layer CI may be in contact with a bottom surface of the first dielectric structure IS1. A bottom surface of the key pattern KP may be in contact with the top surface of the connection dielectric layer CI. A bottom surface of the connection dielectric layer CI may be in contact with a top surface of the bump connection pad11. In some embodiments, differently from that shown, at least one of the bump connection pad11may be provided in the connection dielectric layer CI. The connection dielectric layer CI may include a dielectric material. For example, the connection dielectric layer CI may include silicon oxide. In some embodiments, the connection dielectric layer CI may be a multiple layer including a plurality of dielectric layers.

The connection conductive structures CC may be provided in the connection dielectric layer CI. The connection conductive structures CC may be surrounded by the connection dielectric layer CI. One of the connection conductive structures CC may electrically connect the bump connection pad11to the first pad PA1. Another of the connection conductive structures CC may electrically connect the bump connection pad11to the dummy pad DP. The connection conductive structures CC may include, for example, at least one of a conductive pad, a conductive via, and a conductive line.

FIG.15illustrates an enlarged cross-sectional view showing a semiconductor package according to some embodiments. A semiconductor package ofFIG.15may be the same or substantially the same as the semiconductor package ofFIGS.1A and1B, except for the description below.

Referring toFIG.15, a semiconductor package may further include a connection structure CSc between the first dielectric structure IS1and the bump connection pads11. The connection structure CSc may be a redistribution substrate including redistribution dielectric layers RI and redistribution patterns RP.

The redistribution dielectric layers RI may be stacked along the third direction D3. The redistribution dielectric layers RI may include a photo-imageable dielectric material. The photo-imageable dielectric material may include, for example, at least one selected from photosensitive polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers.

The redistribution patterns RP may be provided in the redistribution dielectric layers RI. The redistribution patterns RP may be surrounded by the redistribution dielectric layers RI. One of the redistribution patterns RP may electrically connect the bump connection pad11to the first pad PA1. Another of the redistribution patterns RP may electrically connect the bump connection pad11to the dummy pad DP. The redistribution patterns RP may include a conductive material. The redistribution pattern RP may include a via part that extends in a vertical direction and a line part that extends in a horizontal direction.

FIG.16illustrates a plan view showing a planar structure of a semiconductor package according to some embodiments. A semiconductor package ofFIG.16may be similar to the semiconductor package ofFIGS.1A and1B, except for the description below.

Referring toFIG.16, a first pad PA1dand a dummy pad DPd may each have a circular shape when viewed in plan. A first surface of a first part included in a first conductive layer of the first pad PA1dmay have a circular shape when viewed in plan, and likewise a first surface of a first part included in a first dummy layer of the dummy pad DPd may have a circular shape when viewed in plan. When viewed in plan, a key pattern KPd may have a shape different from that of the first pad PA1dand that of the dummy pad DPd. The key pattern KPd may have a tetragonal shape when viewed in plan. A first surface of a first part included in a first pattern layer of the key pattern KPd may have a tetragonal shape when viewed in plan.

In some embodiments, the first pad PA1dand the dummy pad DPd may each have an oval shape or a polygonal shape when viewed in plan.

The first pad PA1dand the dummy pad DPd may have their planar sizes less than that of the key pattern KPd. For example, a maximum width W11in the first direction D1of the first pad PA1dand a maximum width W12in the first direction D1of the dummy pad DPd may be less than a maximum width W13in the first direction D1of the key pattern KPd, and a maximum width W14in the second direction D2of the first pad PA1dand a maximum width W15in the second direction D2of the dummy pad DPd may be less than a maximum width W16in the second direction D2of the key pattern KPd.

FIG.17illustrates a plan view showing a planar structure of a semiconductor package according to some embodiments. A semiconductor package ofFIG.17may be the same or substantially the same as the semiconductor package ofFIGS.1A and1B, except for the description below.

Referring toFIG.17, a first pad PA1eand a dummy pad DPe may each have a tetragonal shape when viewed in plan. When viewed in plan, a key pattern KPe may have a shape different from that of the first pad PA1eand that of the dummy pad DPe. The key pattern KPe may have a cross shape when viewed in plan.

In a semiconductor package according to some embodiments of the present inventive concepts, key patterns and a pad bonded to a semiconductor chip may be formed simultaneously to simplify a fabrication process of the semiconductor package.

Although embodiments of the present disclosure has been described in connection with the some embodiments of the present inventive concepts illustrated in the accompanying drawings, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and essential feature of the present inventive concepts. The above disclosed embodiments should thus be considered illustrative and not restrictive.