Differential integrator having offset and gain compensation, not requiring balanced inputs

Disclosed is a fully differential switched-capacitor integrator which accepts a single-ended or unbalanced input signal and compensates the offset and finite gain of the operational amplifier without an extra converter circuit. The proposed circuit utilizes a special input structure which adds special capacitors to store the offset and the low frequency noise of the operational amplifier. One preferred embodiment implements the switching means as transmission gates using CMOS transistors. Clock feedthrough is prevented by providing two non-overlapping clock phases with a delayed clock each, thus avoiding clock feed-through. The invention provides a good alternative for applications such as low noise filters and sigma delta modulators.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The invention relates to an electronic integrator circuit, and more 
particularly to a fully differential switched-capacitor integrator for use 
in low noise filters and sigma delta modulators. 
2. Description of the Related Art 
Fully differential circuits are more attractive in high performance, high 
precision applications for their two advantages 
a) they are less sensitive to power supply noise and 
b) they are capable of achieving a dynamic range which is approximately 
twice that of single-ended circuits. However, fully differential circuits 
usually just accept well balanced differential input signals. Therefore, a 
single-ended to differential converter circuit is needed in front of it. 
This increases the complexity of the system and adds extra noise as well. 
There are few related art circuits which convert a single-ended signal to a 
differential signal by themselves without an extra converter circuit. 
U.S. Pat. No. 4,647,865 (Westwick) proposes a switched capacitor input 
structure for a fully differential amplifier, which can accept 
single-ended signals. But the offset and low frequency noise of the 
amplifier do not cancel. This is not acceptable in some high performance 
applications. 
U.S. Pat. No. 5,410,270 (Rybicki et al.) a fully differential amplifier 
having offset cancellation is proposed. However, this circuit can only be 
used as an amplifier, it cannot change to an integrator, which is widely 
used in filter circuits and other applications. 
U.S. Pat. No. 4,896,156 (Garverick et al.) proposes a three phase system 
which complicates the timing and system design. 
U.S. Pat. No. 5,220,286 (Nadeem) discloses a single-ended to differential 
input converter which is more complex than the circuit of the invention 
and cannot compensate the offset and finite operational amplifier gain 
either. 
U.S. Pat. No. 4,746,871 (de la Plaza) describes a differential switched 
capacitor integrator but which requires two operational amplifiers and 
does not appear to accept single-ended inputs. 
It should be noted that none of the above-cited examples of the related art 
provide a fully differential switched-capacitor integrator that could 
accept single-ended or unbalanced input signals and compensates the offset 
and finite gain of the operational amplifier at the same time. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a fully differential 
switched-capacitor integrator which accepts a single-ended or unbalanced 
input signal and compensates the offset and finite gain of the operational 
amplifier without an extra converter circuit. 
Another object of the present invention is to provide a good alternative 
circuit for applications such as low noise and sigma delta modulators. 
A further object of the present invention is to avoid clock feed-through. 
These objects have been achieved by utilizing a special input structure and 
by adding special capacitors to store the offset and the low frequency 
noise of the operational amplifier. The switching means can be implemented 
as transistors, p-channel or n-channel transistors, or as transmission 
gates using CMOS transistors. Clock feedthrough is prevented by providing 
two non-overlapping clock phases with a delayed clock each.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
The present invention proposes a new kind of fully differential 
switched-capacitor integrator, which utilizes a special input structure to 
accept, in addition to a fully differential input signal, a single-ended 
or unbalanced input signal and adds two extra capacitors to compensate the 
offset and finite gain of the operational amplifier. Please refer to K. 
Nagaraj, T. Viswanathan, K. Singhal, and J. Vlach, "Switched-Capacitor 
Circuits with Reduced Sensitivity to Amplifier Gain." IEEE TRANSACTIONS ON 
CIRCUITS AND SYSTEMS., vol. CAS-34, pp 571-574, May 1987. The present 
invention is a good alternative for some applications, such as low noise 
filters and sigma delta modulators. 
Referring now to FIG. 1, we describe a block diagram of the preferred 
embodiment of the invention. The differential integrator circuit 100 is 
comprised of blocks 110, 120, 130, 140, and 150. Input section 110 has 
inputs 111 and 112 and outputs 113 and 114, the input section accepting a 
fully differential input signal through switching means during a first 
period of time, and outputs 113 and 114 providing output signals. Input 
section 110 also accepts a single ended input signal or an unbalanced 
input signal which is converted to a differential signal with offset 
cancellation. 
Offset and low noise storage section 120 has inputs 121 and 122, terminals 
A and B, and outputs 123 and 124. Inputs 121 and 122 are connected, 
through switching means sw1a and sw1b during a second period of time, to 
outputs 113 and 114, respectively. Block 120 is used to store a signal 
offset and a low frequency noise signal and compensates for the offset of 
Block 130. Block 120 also compensates for the finite gain of Block 130. 
Amplifying means 130 has inputs 131 and 132 and outputs 133 and 134, where 
inputs 131 and 132 connect to outputs 123 and 124, respectively. Outputs 
133 and 134 are connected, through switching means sw2a and sw2b during a 
first period of time, to output VOUT+ and output VOUT-, respectively. 
Upper integrator section 140 is connected between input 131 and output 133 
of Block 130 through switching means during a first period of time, and is 
connected to terminal A through switching means during a second period of 
time. 
Lower integrator section 150 is connected between input 132 and output 134 
of Block 130 through switching means during a first period of time, and is 
connected to terminal B through switching means during a second period of 
time. 
A desirable characteristic of the present invention is that outputs VOUT+ 
and VOUT- do not relate to the input common-mode voltage V.sub.IC applied 
to inputs 111 and 112 of input section 110. In addition the circuit is 
insensitive to the gain of amplifying means (Block 130). 
Referring now to FIG. 2, capacitors C1A and C1B, switches 10-13 and 35 
comprise the input section 110 (see also FIG. 1) of the preferred 
embodiment of the invention, which accepts a single-ended or unbalanced 
input signal. Capacitors C3A and C3B (Block 120 of FIG. 1) are used to 
store the offset and low frequency noise of the operational amplifier 34. 
C2A and C2B (Blocks 140 and 150 of FIG. 1) are integration capacitors. 
Again referring to FIG. 2, we now provide a more detailed description of 
the theory of operation of the invention. When phase 1 (.phi.1) is active, 
switches 10, 11, and 35 turn on, and switches 12, 13, 18, and 19 turn off. 
The input section 110 is then disconnected from the rest of the 
integrator. C1A and C1B are connected in series, forming a voltage 
divider. Signals VIN1 and VIN2 can each be considered as comprising 
common-mode voltage V.sub.IC and differential-mode voltage V.sub.ID 
components as defined by solving the following equations: 
EQU VIN1(n)=V.sub.IC (n)+0.5V.sub.ID (n) (1) 
EQU VIN2(n)=V.sub.IC (n)-0.5V.sub.ID (n) (2) 
where n stands for that instant in time. Usually, C1A=C1B=C1, C2A=C2B=C2, 
C3A=C3B=C3, then the potential at nodes 16 and 17 is V.sub.IC (n), and the 
voltage across C1A and C1B is 0.5V.sub.ID (n) and -0.5V.sub.ID (n), 
respectively. 
At the same time switches 22, 23, 26, and 27 are closed. Nodes 20 and 21 
are connected to ground, or reference potential, through switches 22 and 
23, respectively. Thus, C3A and C3B are charged to the offset voltage 
(V.sub.OS) of the operational amplifier 34. For simplicity, infinite 
operational amplifier gain and constant offset voltage are assumed. Then 
the voltage of the operational amplifier negative input terminal 28 is 
-0.5V.sub.OS, the voltage of the operational amplifier positive input 
terminal 29 is 0.5V.sub.OS. Therefore, the voltage across capacitors C3A 
and C3B is -0.5V.sub.OS and 0.5V.sub.OS, respectively, and the voltage 
across C2A and C2B is V.sup.1.sub.OUT+ (n-1)+0.5V.sub.OS and 
V.sup.1.sub.OUT- (n-1)-0.5V.sub.OS, respectively, where the superscript 1 
stands for the value at the end of .phi.1. 
In summary, the voltage across each capacitor at the end of .phi.1 is 
listed below: 
C1A: +0.5V.sub.ID (n) 
C1B: -0.5V.sub.ID (n) 
C2A: V.sup.1.sub.OUT+ (n-1)+0.5V.sub.OS 
C2B: V.sup.1.sub.OUT- (n-1)-0.5V.sub.OS 
C3A: -0.5V.sub.OS 
C3B: +0.5V.sub.OS 
When phase 2 (.phi.2) is active, C1A and C1B are disconnected from the 
input and nodes 14 and 15 are shorted to ground through switches 12 and 
13. Switches 18, 19, 24, and 25 are closed. Therefore, C2A and C1A join 
together at node 20, C2B and C1B join together at node 21. Charges stored 
in C1A and C1B during .phi.1 are transferred to C2A and C2B. Assuming the 
voltages at nodes 20 and 21 at the end of .phi.2 are V.sub.XA and 
V.sub.XB, respectively, then the voltage across each capacitor is: 
C1A: -V.sub.XA 
C1B: -V.sub.XB 
C2A: V.sup.2.sub.OUT+ (n)-V.sub.XA 
C2B: V.sup.2.sub.OUT- (n)-V.sub.XB 
C3A: -0.5V.sub.OS -V.sub.XA 
C3B: +0.5V.sub.OS -V.sub.XB 
where the superscript 2 stands for the value at the end of .phi.2. 
Because the right (+) plate of capacitors C3A and C3B is always connected 
to the input terminals of the operational amplifier, the charges on C3A 
and C3B remain unchanged from .phi.1 to .phi.2, thus: 
EQU C3A.circle-solid.(-0.5V.sub.OS -V.sub.XA)=C3A.circle-solid.(-0.5V.sub.OS) 
(3) 
EQU C3B.circle-solid.(+0.5V.sub.OS -V.sub.XB)=C3B.circle-solid.(+0.5V.sub.OS) 
(4) 
which results in V.sub.XA =V.sub.XB =0. This means that nodes 20 and 21 are 
shorted to ground during .phi.1 and become virtual ground during .phi.2. 
The voltages across each capacitor can be rewritten as follows: 
C1A: 0 
C1B: 0 
C2A: V.sup.2.sub.OUT+ (n) 
C2B: V.sup.2.sub.OUT- (n) 
C3A: -0.5V.sub.OS 
C3B: +0.5V.sub.OS 
Utilizing the charge conservation law at nodes 20 and 21: 
EQU C1A[0-0.5V.sub.ID (n)]=-C2A{V.sup.2.sub.OUT+ (n)-[V.sup.1.sub.OUT+ 
(n-1)+0.5V.sub.OS ]} (5) 
EQU C1B[0+0.5V.sub.ID (n)]=-C2B{V.sup.2.sub.OUT- (n)-[V.sup.1.sub.OUT- 
(n-1)-0.5V.sub.OS ]} (6) 
where the "0" in the first square bracket of eq.'s (5) and (6) is the 
voltage of C1A and C1B during .phi.2, respectively, and where the second 
term of the first square bracket is the voltage of C1A and C1B during 
.phi.1, respectively. 
Solving these two equations the following results are obtained: 
EQU V.sup.2.sub.OUT+ (n)=V.sup.1.sub.OUT+ 
(n-1)+(C1/C2).multidot.(0.5V.sub.ID)+0.5V.sub.OS (7) 
EQU V.sup.2.sub.OUT- (n)=V.sup.1.sub.OUT- 
(n-1)-(C1/C2).multidot.(0.5V.sub.ID)-0.5V.sub.OS (8) 
where (C1/C2) (0.5V.sub.ID) is the integration part and 0.5V.sub.OS is the 
offset part. 
Therefore, the integration is finished. But the output is contaminated by 
the offset. 
Next .phi.2 becomes inactive and .phi.1 becomes active again. As before, 
C1A and C1B are charged to the new input voltage, C3A and C3B are charged 
to the operational amplifier offset. The left (-) plate of C2A is 
connected to the operational amplifier negative (-) input terminal instead 
of node 20, the left (-) plate of C2B is connected to the operational 
amplifier positive (+) input terminal instead of node 21. No charge 
transfer occurred during this procedure. So: 
EQU C2A.circle-solid.[V.sup.1.sub.OUT+ (n)+0.5V.sub.OS 
]=C2A.circle-solid.V.sup.2.sub.OUT+ (n) (9) 
EQU C2B.circle-solid.[V.sup.1.sub.OUT- (n)-0.5V.sub.OS 
]=C2B.circle-solid.V.sup.2.sub.OUT- (n) (10) 
Substituting eq. (7) 
EQU V.sup.1.sub.OUT+ (n)=V.sup.2.sub.OUT+ (n)-0.5V.sub.OS =V.sup.1.sub.OUT+ 
(n-1)+(C1/C2).multidot.(0.5V.sub.ID) (11) 
Substituting eq. (8) 
EQU V.sup.1.sub.OUT- (n)=V.sup.2.sub.OUT- (n)+0.5V.sub.OS =V.sup.1.sub.OUT- 
(n-1)-(C1/C2).multidot.(0.5V.sub.ID) (12) 
The offset is cancelled. Also, the outputs do not relate to the input 
common-mode voltage V.sub.IC. This manifests the object of the invention 
that a balanced input signal is not required. When the input is a 
single-ended signal the invention converts the single-ended signal to a 
differential signal with offset cancellation. 
Detailed analysis carried out in the previously recited reference shows 
that the proposed circuit is insensitive to the gain of the operational 
amplifier. This characteristic relaxes the operational amplifier design. 
All the switches are con trolled by two non-overlapping clocks .phi.1 and 
.phi.2. Switches 10 and 11 are controlled by .phi.1 delayed (.phi.1d) 
which is a delayed signal of clock .phi.1. Switches 12 and 13 are 
controlled by .phi.2 delayed (.phi.2d) which is a delayed signal of clock 
.phi.2. Delayed clocks are introduced for the sake of reducing clock 
feedthrough. Switches 18, 19, and 24, 25 are controlled by clock .phi.2. 
Switches 22, 23, 26, 27, 32, 33, and 35 are controlled by clock .phi.1. 
Referring once more to FIG. 2, we describe in more detail the differential 
integrator circuit 200 of the present invention having offset and gain 
compensation and comprising an amplifier 34 and an input structure 210. 
Amplifier 34 has a minus (-) input, a plus (+) input, a +output 30, and a 
-output 31, the amplifier provides a signal with gain at the + and 
-output. 
Input structure 210 has a first and a second input VIN1 and VIN2 and 
outputs 28 and 29; input structure 210 accepts a first and a second input 
signal at inputs VIN1 and VIN2, respectively. Output 28 of input structure 
210 is connected to the -input of amplifier 34, and output 29 of input 
structure 210 is connected to the + input of amplifier 34, where input 
structure 210 converts a single ended input signal to a differential 
signal at outputs 28 and 29. 
Input structure 210 further comprises: 
a .phi.1d switching means 10 connected with one end to input VIN1, 
a .phi.1d switching means 11 connected with one end to input VIN2, 
a .phi.2d switching means 12 serially connected between the other end of 
.phi.1d switching means 10 and a reference potential G (typically ground), 
a .phi.2d switching means 13 serially connected between the other end of 
.phi.1d switching means 11 and reference potential G, 
a capacitor C1A connected with one plate to the other end of .phi.1d 
switching means 10, 
a capacitor C1B connected with one plate to the other end of .phi.1d 
switching means 11, 
a .phi.2 switching means 18 connected with one end to the other plate of 
capacitor C1A, 
a .phi.2 switching means 19 connected with one end to the other plate of 
capacitor C1B, 
a .phi.1 switching means 22 serially connected between the other end of 
.phi.2 switching means 18 and reference potential G, 
a .phi.1 switching means 23 serially connected between the other end of 
.phi.2 switching means 19 and reference potential G. 
a capacitor C3A connected with one plate to the other end of .phi.2 
switching means 18, the other plate of capacitor C3A connected to the - 
input of amplifier 34, 
a capacitor C3B connected with one plate to the other end of .phi.2 
switching means 19, the other plate of capacitor C3B connected to the + 
input of amplifier 34, 
a .phi.2 switching means 24 connected with one end to the other end of 
.phi.2 switching means 18, 
a .phi.2 switching means 25 connected with one end to the other end of 
.phi.2 switching means 19, 
a .phi.1 switching means 26 serially connected between the other end of 
.phi.2 switching means 24 and the - input of amplifier 34, 
a .phi.1 switching means 27 serially connected between the other end of 
.phi.2 switching means 25 and the + input of amplifier 34, 
a capacitor C2A connected with one plate to the other end of .phi.2 
switching means 24, the other plate of capacitor C2A connected to the + 
output 30 of amplifier 34, 
a capacitor C2B connected with one plate to the other end of .phi.2 
switching means 25, the other plate of capacitor C2B connected to the - 
output 31 of amplifier 34, 
a .phi.1 switching means 32 serially connected between the + output 30 of 
amplifier 34 and output terminal VOUT+, 
a .phi.1 switching means 33 serially connected between the -output 31 of 
amplifier 34 and output terminal VOUT-, and 
a .phi.1 switching means 35 serially connected between the other plate of 
capacitor C1A and the other plate of capacitor C1B. 
All .phi.1 switching means are activated by a clock .phi.1, and all .phi.1d 
switching means are activated by a delayed clock .phi.1. All .phi.2 
switching means are activated by a clock .phi.2, and all .phi.2d switching 
means are activated by a delayed clock .phi.2. 
Referring now to FIG. 3, four clocks are used, labeled .phi.1, .phi.1d, 
.phi.2, and .phi.2d. It can be seen that clocks .phi.2 and .phi.2d are 
non-overlapping with respect to clock .phi.1 and clock .phi.1d. 
Switching means may be implemented in many ways like transistors or, more 
typically, p-channel or n-channel metal oxide (MOS) transistors. A 
preferred embodiment of the present invention makes use of transmission 
gates employing p-channel and n-channel MOS transistors as shown in FIG. 
4, and described next. 
The circuit of FIG. 4 is essentially the same as that of circuit of FIG. 2, 
except for the substitution of transmission gates for the switching means 
of FIG. 2. Similar elements of FIGS. 2 and 4 have the same reference 
characters. In FIG. 4 the transmission gates replace the switching means 
of FIG. 2. In FIG. 4, switches 10-13, 18, 19, 22-27, 32, 33, and 35 are 
transmission gates with the p-channel and n-channel transistor of each 
transmission gate connected in parallel. 
Referring now to FIG. 5, we describe the timing diagram for the circuit of 
FIG. 4. Eight clocks are used, where .phi.1, .phi.1d, .phi.2, and .phi.2d 
of FIG. 4 are identical to those of FIG. 2 with the same designation. 
Added to FIG. 4 are the inverses (180.degree. out-of-phase, electrically) 
of each of the four clocks .phi.1, .phi.1d, .phi.2, and .phi.2d. These 
eight clocks have the suffix "+" or "-" added, to indicate to which 
transistor gate, n-channel or p-channel, each clock goes to. 
Summarizing the clocks as shown in FIG. 5: 
1) gates of each n-channel transistor and each p-channel transistor of a 
.phi.1 transmission gate are activated by a positive clock .phi.1+ and by 
a negative clock .phi.1-, respectively. 
2) gates of each n-channel transistor and each p-channel transistor of a 
.phi.1d transmission gate are activated by a delayed positive clock 
.phi.1d+ and by a delayed negative clock .phi.1d-, respectively. 
3) gates of each n-channel transistor and each p-channel transistor of a 
.phi.2 transmission gate are activated by a positive clock .phi.2+ and by 
a negative clock .phi.2-, respectively. 
4) gates of each n-channel transistor and each p-channel transistor of a 
.phi.2d transmission gate are activated by a delayed positive clock 
.phi.2d+ and by a delayed negative clock .phi.2d-, respectively. 
Similar to the clocks of FIG. 3, the timing diagram of FIG. 5 shows that 
both phases (+ and -) of clocks .phi.2 and .phi.2d are non-overlapping 
with respect to both phases (+ and -) of clocks .phi.1 and .phi.1d. 
The invention just described offers the advantages of a new kind of fully 
differential switched-capacitor integrator which: 
utilizes a special input structure to accept a single-ended or unbalanced 
input signal, 
compensates the offset and finite gain of the operational amplifier or 
amplifying means, 
provides a good alternative for applications such as low noise and sigma 
delta modulators, 
avoids clock feed-through by providing two non-overlapping clock phases 
with a delayed clock each, 
implements switching means as transistors, p-channel or n-channel 
transistors, or as transmission gates using CMOS transistors. 
While the invention has been particularly shown and described with 
reference to the preferred embodiments thereof, it will be understood by 
those skilled in the art that various changes in form and details may be 
made without departing from the spirit and scope of the invention.