Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby

The method includes forming an array of first separation walls on an underlying layer. A block co-polymer (BCP) layer is formed to fill inside regions of the first separation walls and gaps between the first separation walls. The BCP layer is phase-separated to include first domains that provide second separation walls covering inner sidewalls and outer sidewalls of the first separation walls and second domains that are separated from each other by the first domains.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2013-0088353, filed on Jul. 25, 2013, in the Korean Intellectual Property Office, which is incorporated by reference in its entirety as set forth in full.

BACKGROUND

1. Technical Field

Embodiments of the present disclosure relate to methods of fabricating a semiconductor device, and more particularly, to methods of fabricating a semiconductor device having an array of fine patterns and semiconductor devices fabricated thereby.

2. Related Art

In fabrication of electronic devices such as semiconductor devices, many efforts have been focused to integrate more patterns in a limited area of a semiconductor substrate. That is, attempts to increase the integration density of the electronic devices or the semiconductor devices have typically resulted in formation of fine patterns. Various techniques have been proposed to form the fine patterns such as small contact holes having a nano-scaled critical dimension (CD), for example, a size of about a few nanometers to about several tens of nanometers.

In the event that the fine patterns of the semiconductor devices are formed using only a photolithography process, there may be some limitations in forming the fine patterns due to image resolution limits of lithography apparatuses used in the photolithography process. Methods of forming the fine patterns using a self-assembly of polymer molecules may be considered as an alternative for overcoming the image resolution limits of optical systems used in the photolithography process and for avoiding constraints arising from wavelengths of lights generated from light sources of optical systems used in the photolithography process. However, the methods of forming the fine patterns using the self-assembly technique are still under development. Thus, there may be still some difficulties in forming the fine patterns of highly integrated semiconductor devices using the self-assembly technique.

SUMMARY

Various embodiments are directed to methods of fabricating semiconductor devices and semiconductor devices fabricated thereby.

According to some embodiments, a method of fabricating a semiconductor device includes forming an array of pillars on an underlying layer, forming a separation wall layer on the pillars and the underlying layer to provide first separation walls on sidewalls of the pillars, forming a block co-polymer (BCP) layer on the separation wall layer to fill gaps between the pillars, and phase-separating the BCP layer into first domains including second separation walls on the first separation walls and second domains separated from the pillars by the first domains.

According to further embodiments, a method of fabricating a semiconductor device includes forming an array of pillars on an underlying layer, forming first separation walls on sidewalls of the pillars, forming a block co-polymer (BCP) layer filling gaps between the pillars, and phase-separating the BCP layer into first domains including second separation walls on the first separation walls and second domains separated from the pillars by the first domains.

According to further embodiments, a method of fabricating a semiconductor device includes forming an array of first separation walls on an underlying layer. Each of the first separation walls is formed to have a cylindrical shape. A block co-polymer (BCP) layer is formed to fill inside regions of the first separation walls and gaps between the first separation walls. The BCP layer is phase-separated to include first domains that provide second separation walls covering inner sidewalls and outer sidewalls of the first separation walls and second domains that are separated from each other by the first domains.

According to further embodiments, a semiconductor device includes an array of pillars on an underlying layer, a separation wall layer including first separation walls covering sidewalls of the pillars, and a block co-polymer (BCP) layer formed on the separation wall layer to fill gaps between the pillars. The BCP layer is phase-separated to include first domains that provide second separation walls covering the first separation walls and second domains that are separated from each other by the first domains.

According to further embodiments, a semiconductor device includes an array of first separation walls on an underlying layer. Each of the first separation walls has a cylindrical shape. A block co-polymer (BCP) layer fills inside regions of the first separation walls and gaps between the first separation walls. The BCP layer is phase-separated to include first domains that provide second separation walls covering inner sidewalls and outer sidewalls of the first separation walls and second domains that are separated from each other by the first domains.

According to further embodiments, a method of fabricating a semiconductor device includes forming first and second sacrificial pillars over an underlying layer, forming first separation walls over sidewalls of the first and the second sacrificial pillars, respectively, filling a copolymer between the first separation walls, subject the copolymer to a phase-separation to convert the copolymer into first and second domains, wherein the first domain is formed in a lining pattern along the first separation walls, wherein the second domain includes remaining copolymer, removing the second domain to form a first contact hole exposing the underlying layer, removing the first and second sacrificial pillars to form second contact holes exposing the underlying layer, and patterning the exposed underlying layer using the first separation walls and the first domain as a mask.

The first contact hole has substantially a same width as the second contact holes.

A minimum pattern size available under a given condition is X. and a distance between the first contact hole and any of the second contact holes is less than the minimum pattern size X.

Each of the sacrificial pillars has the minimum pattern size.

According to further embodiments, a method of fabricating a semiconductor device includes forming first and second sacrificial pillars over an underlying layer, forming first separation walls over sidewalls of the first and the second sacrificial pillars, respectively, removing the first and second sacrificial pillars to form first contact holes, filling a copolymer (i) between the first separation walls and (i) in the first contact holes, subject the copolymer to phase-separation to convert the copolymer into first and second domains, wherein the first domain is formed in a lining pattern along the first separation walls, wherein the second domain includes the remaining copolymer, removing the second domain to form second contact holes exposing the underlying layer, patterning the exposed underlying layer using the first separation walls and the first domain as a mask.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments may provide methods of fabricating fine patterns of semiconductor devices by self-assembling domains of a block co-polymer (BCP) material. Phase-separated domains of the BCP material may be spontaneously self-assembled to produce fine structures in which the domains are repeatedly arrayed. In the event that fine patterns are formed using a self-assembly of the domains of the BCP material, the fine patterns may be realized to have a similar size to a thickness of a single molecular layer. As a result, the resolution limits of the photolithography process may be overcome by the self-assembly of the domains of the BCP material.

Some embodiments may be used in formation of cell contact holes for arraying storage nodes comprising cell capacitors of dynamic random access memory (DRAM) devices. In such a case, the cell contact holes may be formed to have a uniform size and may be repeatedly arrayed. That is, the cell contact holes may be formed to have a uniform size and a uniform shape throughout a cell array region of the DRAM device. Further, the methods according to some embodiments may also be applied to formation of cell contact holes for arraying nano-sized fine nodes disposed in cell array regions of phase changeable random access memory (PcRAM) devices or resistive random access memory (ReRAM) devices. In addition, the methods according to some embodiments may be used in fabrication of fine patterns which are regularly and repeatedly arrayed in memory devices such as static random access memory (SRAM) devices, flash memory devices, magnetic random access memory (MRAM) devices and ferroelectric random access memory (FeRAM) devices or in logic devices.

It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may only be used to distinguish one element from another element, rather than to describe some temporal or other aspect. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will also be understood that when an element is referred to as being located “under”, “beneath,” “below”, “lower,” “on”, “over”, “above,” “upper”, “side” or “aside” another element, it can be directly contact the other element, or at least one intervening element may also be present therebetween. Accordingly, the terms such as “under”, “beneath,” “below”, “lower,” “on”, “over”, “above,” “upper”, “side” “aside” and the like are not intended to limit the scope of the embodiments.

FIG. 1is a plan view illustrating an array of pillars (or sacrificial pillars)500, andFIGS. 2A and 2Bare cross-sectional views taken along lines A-A′ and B-B′ ofFIG. 1, respectively referring toFIGS. 1,2A, and2B, the pillars500may be arranged such that four pillars are located at four vertices of a tetragon. First gaps501may be disposed between the pillars500adjacent to each other in a row or in a column, and a second gap503may be disposed between the pillars500adjacent to each other in a diagonal direction. That is, one of the first gaps501may be shown in a cross-sectional view taken along the line A-A′ which is parallel with a row, and the second gap503may be shown in a cross-sectional view taken along the line B-B′ which is parallel with a diagonal direction. Accordingly, a width of the second gap503may be greater than that of the first gaps501. Since the four pillars500are respectively located at four vertex of a tetragon, the second gap503may be disposed in a central region of the tetragon. Although, in the particular example ofFIG. 1the pillars500are located at four vertex of a tetragon, embodiments are not limited thereto. For example, the pillars500may include three pillars and the three pillars may be located at three vertex of a triangle.

The pillars500may be formed on an underlying layer400disposed over a semiconductor substrate100. Before forming the underlying layer400, an etch target layer200and a hard mask layer300may be sequentially formed over the semiconductor substrate100.

The etch target layer200may be formed of an interlayer insulation layer including, e.g., a silicon oxide layer such as a tetra-ethyl-othor-silicate (TEOS) layer having a thickness of about 2200 angstroms. The etch target layer200may be used to insulate storage node contacts penetrating therethrough from each other. The storage node contacts may electrically connect storage nodes of cell capacitors of a DRAM device to the semiconductor substrate100or to cell transistors (not shown) formed in the semiconductor substrate100. Alternatively, the etch target layer200may act as a mold sacrificial layer for contact holes defining shapes of the storage nodes of the cell capacitors penetrate. In ReRAM devices, the etch target layer200may be used as an interlayer insulation layer that underlying electrodes contacting variable resistive layers penetrate.

The hard mask layer300may be formed to include an amorphous carbon layer (e.g. having a thickness of about 1500 angstroms). The hard mask layer300may be used as an etch mask layer when the etch target layer200is patterned to form contact holes in a subsequent process. The underlying layer400may be formed on the hard mask layer300. The underlying layer400may be used as an etch mask layer when the hard mask layer300is patterned in a subsequent process. The underlying layer400may be formed to include a silicon oxynitride (SiON) layer having a thickness of about 200 angstroms. In some embodiments, an interfacial layer410may be additionally formed between the hard mask layer300and the underlying layer400, and the interfacial layer410may include a silicon oxide (SiOX) layer such as an undoped silicate glass (USG) layer having a thickness of about 200 angstroms. The interfacial layer410may correspond to the underlying layer400. In such a case, the underlying layer400may include a single layer of silicon oxynitride (SiON) material or include a combination layer of a SiON layer and a USG layer on the SiON layer or a combination layer of a USG layer and a SiON layer on the USG layer.

A pillar layer for providing the pillars500may be formed on the underlying layer400and include a high temperature spin on carbon (SOC) layer having a thickness of about 800 angstroms. The pillar layer may be patterned to form an array of the pillars500. Specifically, the array of the pillars500may be formed by coating a photoresist layer (not shown) on the pillar layer, patterning the photoresist layer using a photolithography process to form a photoresist pattern, and etching the pillar layer using the photoresist pattern as an etch mask. A bottom anti-reflective coating (BARC) layer (not shown) having a thickness of about 230 angstroms may be formed between the pillar layer and the photoresist layer to enhance a resolution of the photolithography process. An interfacial layer such as an SiON layer having a thickness of about 300 angstroms may be additionally formed between the BARC layer and the pillar layer. The pillars500may be formed using a single patterning technology utilizing a photolithography process. Alternatively, the pillars500may be formed using a spacer patterning technology or a double patterning technology to obtain a finer pitch size. For example, the pillars500may be formed to have a width (e.g. of about 35 nanometers to about 59 nanometers, for example, about 40 nanometers to about 42 nanometers) using a spacer patterning technology or a double patterning technology.

FIG. 3is a plan view illustrating a step of forming a separation wall layer600, andFIGS. 4A and 4Bare cross-sectional views taken along lines A-A′ and B-B′ ofFIG. 3, respectively. Referring toFIGS. 3,4a, and4b, the separation wall layer600may be formed to cover an entire surface of the resultant structure where the pillars500are formed. The separation wall layer600may be formed of an insulation layer having an etch selectivity with respect to the underlying layer400. For example, the separation wall layer600may be formed of an ultra low temperature oxide (ULTO) layer having a thickness of about 200 angstroms. The ULTO layer may have an excellent step coverage. That is, the ULTO layer may be deposited to conformally cover sidewalls and top surfaces of the pillars500as well as a surface of the underlying layer400exposed between the pillars500. The separation wall layer600deposited on the sidewalls of the pillars500will be referred to as a first separation wall portion605. The separation wall layer600disposed over the pillars500will be referred to as a portion601.

FIG. 5is a plan view illustrating a step of forming a block co-polymer (BCP) layer700, andFIGS. 6A and 6Bare cross-sectional views taken along lines A-A′ and B-B′ ofFIG. 5, respectively. Referring toFIGS. 5,6a, and6b, the BCP layer700may be formed on the separation wall layer600to fill the first and second gaps (501and503ofFIG. 2). The BCP layer700may be formed by coating a polystyrene-poly(methyl meta acrylate) (PS-PMMA) co-polymer material or a silicon contained polystyrene-poly(di methyl siloxane) (Si contained PS-PDMS) co-polymer material. The BCP layer700may be coated to fill the first and second gaps501and503and to the portion601of the separation wall layer600which is located on top surfaces of the pillars500.

FIG. 7is a plan view illustrating a step of phase-separating the BCP layer700, andFIGS. 8A and 8Bcross-sectional views taken along lines A-A′ and B-B′ ofFIG. 7, respectively. Referring toFIGS. 7,8a, and8b, the BCP layer700may be annealed and undergo phase separation. As a result, the BCP layer700is separated into first and second domains710,730.

The first domain710serves as a second separation wall711covering the first separation wall portions605. The second domain730is spaced apart from the pillars500by the first domain710. The first domain710may be formed to fill the first gaps501between the pillars500arrayed in a row or in a column direction. Further, the second domain730may be formed in a central region surrounded by the four pillars500located at four vertex of a tetragon. In such a case, the first domain710may extend to cover the separation wall layer600on a bottom surface of the second gap503.

The second domain730may be formed to have a post shape. That is, the BCP layer700may be phase-separated such that the second domain730may be surrounded by the first domain710. The second domain730may be spaced apart from the pillars500by the first domain710. The pillars500may be separated from each other by the first domain710.

The BCP layer700may include polystyrene (PS) block component and poly methylmetaacrylate (PMMA) block component, and a volume ratio of the PS to the PMMA may be about 7:3.

Upon phase separation, the first domain710may include the PS as a majority component and the second domain730may include the PMMA as a majority component.

The BCP layer700may be a functional polymer having two or more distinct structured components that may be combined with each other by a covalent bond. The two polymer block components structures may be different from each other in mixing properties and/or solubility due to a difference in chemical structure. These differences may provide a possibility that the BCP layer700is phase-separated to form a self-assembled structure.

Forming a nano structure having a specific shape through a self-assembly of the BCP layer700may be influenced by a physical property and/or a chemical property of the polymer(s) of the BCP layer700. When a BCP layer including two distinct polymer blocks is self-assembled on a substrate, the self-assembled structure of the BCP layer may be formed to have a three dimensional cubic shape, a three dimensional double helix shape, a two dimensional hexagonal packed column shape, a two dimensional lamella shape, or another shape, depending on factors such as a volume ratio, an annealing temperature for phase separation, and/or a molecule size of the polymer(s) comprising the BCP layer.

A size of each polymer block in the various self-assembled structures may be proportional to a molecular weight of the corresponding polymer block. The separation wall layer600may function as a guide layer inducing a self-assembly of the domains of the BCP layer700in order to align the polymer block(s) of the BCP layer700.

In order to rearrange and align the polymer blocks of the BCP layer700through a phase separation of the BCP layer700, the BCP layer700may be annealed at a temperature exceeding the glass transition temperature Tg of each of the blocks of the BCP layer700. For example, the BCP layer700may be annealed at a temperature of about 100 degrees Celsius to about 190 degrees Celsius for about one hour to about twenty four hours to rearrange and align the polymer blocks of the BCP layer700.

Referring again toFIGS. 7,8A, and8B, the pillars500may be formed on the underlying layer400, and the separation wall layer600may be formed to include the first separation wall portions605on the sidewalls of the pillars500. Further, the BCP layer700may be formed on the separation wall layer600to fill the first and second gaps501and503between the pillars500, and the BCP layer700may be phase-separated to provide the first domain710that corresponds to the second separation wall711covering the first separation wall portions605and the second domain730that is spaced apart from the pillars500by the first domain710. The structure illustrated inFIGS. 7,8A,8B may be used in formation of an array of nano-scaled patterns constituting memory devices or logic devices. In such a case, the memory devices may include dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, magnetic random access memory (MRAM) devices, phase changeable random access memory (PcRAM) devices, resistive random access memory (ReRAM) devices and ferroelectric random access memory (FeRAM) devices.

FIG. 9is a plan view illustrating a step of forming a first opening301, andFIGS. 10A and 10Bare cross-sectional views taken along lines A-A′ and B-B′ ofFIG. 9, respectively. Referring toFIGS. 9,10A, and10B, the second domain730may be selectively removed to form the first opening301. That is, the first opening301may be formed by selectively removing the PMMA blocks constituting the second domain730. As illustrated inFIGS. 9,10A and10B, a shape of the first opening301may be determined by the first domain710. That is, the first opening301may be formed to have a hole shape vertically penetrating a portion of the first domain710. When the second domain730is etched and removed, a portion of the first domain710exposed by the first opening301may also be removed to expose an extension portion603of the separation wall layer600located below the first opening301.

FIG. 11is a plan view illustrating a step of exposing a first portion401of the underlying layer400located below the first opening301, andFIGS. 12aand12bare cross-sectional views taken along lines A-A′ and B-B′ ofFIG. 11. Referring toFIGS. 11,12aand12b, the portions601and603of the separation wall layer600exposed by the first domain710may be selectively removed to expose top surfaces of the pillars500and the first portion401of the underlying layer400located below the first opening301. The portions601and603of the separation wall layer600may be removed by anisotropically etching the separation wall layer600.

After the portions601and603of the separation wall layer600are removed, portions of the separation wall layer600may still remain. For example, portions615of the separation wall layer600covered with the first domain710in the first gaps501and the first separation wall portion605of the separation wall layer600covered with the first domain710in the second gap503may be remained after the portions601and603of the separation wall layer600are removed. As illustrated inFIGS. 12aand12b, each of the portions615of the separation wall layer600may remain to have a ‘U’-shaped sectional view. The first separation wall portion605of the separation wall layer600may remain to have an ‘L’-shaped sectional view. A top portion of the first domain710may be etched away while the separation wall layer600is anisotropically etched to expose the first portion401of the underlying layer400. However, the most part of the first domain710may still remain to provide the second separation wall711acting as an etch mask.

FIG. 13is a plan view illustrating a step of forming second openings305, andFIGS. 14aand14bare cross-sectional views taken along lines A-A′ and B-B′ ofFIG. 13. Referring toFIGS. 13,14a, and14b, the pillars500may be selectively removed to form second openings305whose shapes are defined by the first separation wall portion605of the separation wall layer600. The second openings305may expose second portions405of underlying layer400. When the pillars500are selectively removed to form the second openings305, the first separation wall portion605and the portions615of the separation wall layer600may still exist. Thus, the first opening301and the second openings305may be separated from each other by the first separation wall portion605and the portions615of the separation wall layer600. When the pillars500are selectively removed, the first domain710including the second separation wall711may also be removed. Alternatively, when the pillars500are selectively removed, the first domain710including the second separation wall711may still remain.

FIG. 15is a plan view illustrating a step of forming a mask pattern409, andFIGS. 16aand16bcross-sectional views taken along lines A-A′ and B-B′ ofFIG. 15, respectively. Referring toFIGS. 15,16aand16b, the first portion401and the second portions405of the underlying layer400may be etched to from the mask pattern409. When the first portion401and the second portions405of the underlying layer400are etched, the first separation wall portion605and the portions615of the separation wall layer600may be used as etch masks. Further, when the first portion401and the second portions405of the underlying layer400are etched to form the mask pattern409, the interfacial layer410may also be etched to have substantially the same shape as the mask pattern409in a plan view. As a result, portions of the hard mask layer300may be exposed by the mask pattern409and the etched interfacial layer410.

FIG. 17is a plan view illustrating a step of forming a hard mask310and contact holes201, andFIGS. 18aand18bare cross-sectional views taken along lines A-A′ and B-B′ ofFIG. 17, respectively. Referring toFIGS. 17,18a, and18b, the portions of the hard mask layer300exposed by the mask pattern (409ofFIGS. 16aand16b) may be selectively etched and removed to form the hard mask310having the same planar shape as the mask pattern409. That is, the hard mask310may also be formed to have the first opening301and the second openings305that expose portions of the etch target layer200. The portions of the etch target layer200exposed by the hard mask310may be etched and removed to form an etch target pattern210having the contact holes201. As a result, the contact holes201may be formed to be vertically aligned with the pillars500and the second domain730. Because the second domain730is uniformly formed by a self-assembly of the BCP layer700, the contact holes201may also be formed to be uniformly spaced apart from each other. That is, an array of the contact holes201may be formed to have a uniform pitch and a uniform size. The structure including the array of the contact holes201may be used in formation of an array of storage nodes or an array of storage node contacts of cell capacitors constituting a DRAM device. Alternatively. the structure including the array of the contact holes201may be used in formation of an array of lower electrodes contacting variable resistive layers of a PcRAM device or a ReRAM device.

FIG. 19is a plan view illustrating a step of forming an array of conductive electrodes800, andFIGS. 20aand20bare cross-sectional views taken along lines A-A′ and B-B′ ofFIG. 19, respectively. Referring toFIGS. 19,20a, and20b, a conductive layer may be formed on the resultant structure illustrated inFIGS. 17,18a, and18bto fill the contact holes201, and the conductive layer may be planarized until the etch target pattern210is exposed. As a result, the conductive electrodes800may be formed in respective contact holes201. The conductive electrodes800may be used as storage node contacts or storage nodes of cell capacitors of a DRAM device. Alternatively, the conductive electrodes800may be used as lower electrodes of a ReRAM device or a PcRAM device.

FIG. 21is a plan view illustrating an array of pillars1500and first separation walls1600, andFIGS. 22aand22bare cross-sectional view taken along lines A-A′ and B-B′ ofFIG. 21, respectively. Referring toFIGS. 21,22a, and22b, four pillars1500may be disposed at four vertex of a tetragon to constitute an array of the pillars1500. In some embodiments, the array of the pillars1500may include three pillars located at three vertex of a triangle. According to the present embodiments, first gaps1501may be disposed between the pillars1500adjacent to each other in a row or in a column, and a second gap1503may be disposed between the pillars1500adjacent to each other in a diagonal direction. That is, one of the first gaps1501may be shown in a cross-sectional view taken along the line A-A′ which is parallel with a row, and the second gap1503may be shown in a cross-sectional view taken along the line B-B′ which is parallel with a diagonal direction. Since the four pillars1500are respectively located at four vertex of a tetragon, the second gap1503may be disposed in a central region of the tetragon. Although, inFIG. 21, the four pillars1500are located at four vertex of a tetragon, the present embodiment is not limited thereto. For example, in some embodiments, the pillars1500may include three pillars and the three pillars may be located at three vertex of a triangle.

The pillars1500may be formed on an underlying layer1400disposed on a semiconductor substrate1100. Before forming the underlying layer1400, an etch target layer1200and a hard mask layer1300may be sequentially formed on the semiconductor substrate1100. The etch target layer1200may be formed of an interlayer insulation layer including a silicon oxide layer such as a tetra-ethyl-othor-silicate (TEOS) layer having a thickness of about 2200 angstroms. The hard mask layer1300may be formed to include an amorphous carbon layer having a thickness of about 1500 angstroms. The hard mask layer1300may be used as an etch mask layer when the etch target layer1200is patterned to form contact holes in a subsequent process. The underlying layer1400may be formed on the hard mask layer1300. The underlying layer1400may be used as an etch mask layer when the hard mask layer1300is patterned in a subsequent process. The underlying layer1400may include a silicon oxynitride (SiON) layer having a thickness of about 200 angstroms. In some embodiments, the underlying layer1400may further include a silicon oxide (SiOX) layer such as an undoped silicate glass (USG) layer having a thickness of about 200 angstroms. A pillar layer for providing the pillars1500may be formed on the underlying layer1400and include a high temperature spin on carbon (SOC) layer having a thickness of about 800 angstroms. The pillar layer may be patterned to form the array of the pillars1500.

A separation wall layer may cover the pillars1500, and the separation wall layer may be anisotropically etched to form the first separation walls1600having a spacer shape on sidewalls of the pillars1500. The first separation walls1600may include an insulation layer having an etch selectivity different from the underlying layer1400and the pillars1500. For example, the first separation walls1600may be formed by depositing an ultra low temperature oxide (ULTO) layer having a thickness of about 200 angstroms and by anisotropically etching the ULTO layer until top surfaces of the pillars1500and the underlying layer1400below the first and second gaps1501and1503are exposed. Since the first separation walls1600are formed to surround the sidewalls of the pillars1500, each of the first separation walls1600may have a cylindrical shape.

FIG. 23is a plan view illustrating a step of removing the pillars1500, andFIGS. 24aand24bare cross-sectional views taken along lines A-A′ and B-B′ ofFIG. 23. Referring toFIGS. 23,24a, and24b, the pillars1500may be selectively removed to form openings having a hole shape. As a result, an inside region1506surrounded by each first separation wall1600and an outside region (i.e., the first and second gaps1501and1503) of the first separation walls1600may expose portions of the underlying layer1400.

FIG. 25is a plan view illustrating a step of forming a BCP layer1700, andFIGS. 26aand26bare cross-sectional views taken along lines A-A′ and B-B′ ofFIG. 25. Referring toFIGS. 25,26a, and26b, the BCP layer1700may be coated to fill the inside and outside regions1506,1501and1503. The BCP layer1700may be formed by coating a polystyrene-poly(methyl meta acrylate) (PS-PMMA) co-polymer material or a silicon contained polystyrene-poly(di methyl siloxane) (Si contained PS-PDMS) co-polymer material.

FIG. 27is a plan view illustrating a step of phase-separating the BCP layer1700, andFIGS. 28aand28bare cross-sectional views taken along lines A-A′ and B-B′ ofFIG. 27, respectively. Referring toFIGS. 27,28a, and28b, the BCP layer1700may be annealed and undergo phase-separation into first domains1710and second domains1730. The first domains1710include second separation walls1711having a spacer shape and covering inner sidewalls and outer sidewalls of the first separation walls1600. The second domains1730are separated from the first separation walls1600by the first domains1710. The second domains1730may include (i) an outside region1731of the first separation walls1600, including an inside of the second gap1503, and (ii) an inside region1735of the first separation walls1600, including the inside regions1506. The first domains1710may include the second separation walls1711covering the inner sidewalls and the outer sidewalls of the first separation walls1600and extension portions1713formed over bottoms of regions1506and1503. That is, each of the first domains1710may be formed to have a ‘U’-shaped sectional view. Meanwhile, the first gaps1501may be filled with the first domain1710. The second domains1730may be separated from each other by the first separation walls1600and the second separation walls1711. Each of the second domains1730may have a post shape.

The BCP layer1700may include polystyrene (PS) blocks and poly-methyl-meta-acrylate (PMMA) blocks, and a volume ratio of the PS blocks to the PMMA blocks may be about 7:3. The first domains1710may be composed of the PS blocks which are phase-separated from the BCP layer1700and the second domains1730may be composed of the PMMA blocks which are phase-separated from the BCP layer1700.

Referring again toFIGS. 27,28a, and28b, an array of the first separation walls1600may be formed on the underlying layer1400, and the BCP layer1700may be formed to fill the inside regions1506surrounded by the first separation walls1600and the first and second gaps1501and1503. Further, the BCP layer1700may be phase-separated to form (i) the first domains1710that include the second separation walls1711covering the inner sidewalls and the outer sidewalls of the first separation walls1600and the (ii) second domains1730that are spaced apart from the first separation walls1600by the first domains1710. The structure illustrated inFIGS. 27,28a, and28bmay be used in formation of an array of nano-scaled patterns constituting memory devices or logic devices. In such a case, the memory devices may include dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, magnetic random access memory (MRAM) devices, phase changeable random access memory (PcRAM) devices, resistive random access memory (ReRAM) devices and ferroelectric random access memory (FeRAM) devices.

FIG. 29is a plan view illustrating a step of forming openings1301, andFIGS. 30aand30bare cross-sectional views respectively taken along lines A-A′ and B-B′ ofFIG. 29. Referring toFIGS. 29,30a, and30b, the second domain1730may be selectively removed to form the opening1301exposing the underlying layer1400in the inside regions1506(seeFIG. 24) or exposing the underlying layer1400in the second gap1503(seeFIG. 24). That is, the openings1301may be formed by selectively removing the PMMA blocks constituting the second domain1730. As illustrated inFIGS. 29,30a, and30b, a shape of the opening1301may be defined by the first domains1710. That is, the opening1301may be formed to have a vertical hole shape. When the second domains1730are etched and removed, the extension portions1713(seeFIG. 28) of the first domains1710is exposed by the openings1301, and then may also be removed to expose portions of the underlying layer1400.

FIG. 31is a plan view illustrating a step of forming a mask pattern1409, andFIGS. 32aand32bare cross-sectional views respectively taken along lines A-A′ and B-B′ ofFIG. 31. Referring toFIGS. 31,32a, and32b, the exposed portions of the underlying layer1400may be selectively etched to from the mask pattern1409. When the exposed portions of the underlying layer1400are etched, the first separation walls1600and the second separation walls1711may be used as etch masks. The mask pattern1409may expose portions of the hard mask layer1300.

FIG. 33is a plan view illustrating a step of forming a hard mask1310and contact holes1201, andFIGS. 34aand34bare cross-sectional views respectively taken along lines A-A′ and B-B′ ofFIG. 33. Referring toFIGS. 33,34a, and34b, the hard mask layer1300and the etch target layer1200may be etched using the mask pattern1409(seeFIG. 32) as an etch mask to form the hard mask1310and an etch target pattern1210, resulting in contact holes1201. Thus, the hard mask1310and the etch target pattern1210may be formed to have the same planar shape as the mask pattern1409. As a result, the contact holes1201may be formed to be vertically with respect to a surface of the semiconductor substrate1100.

FIG. 35is a plan view illustrating a step of phase-separating a BCP layer2700, andFIGS. 36aand36bare cross-sectional views respectively taken along lines A-A′ and B-B′ ofFIG. 36. Referring toFIGS. 35,36a, and36b, four pillars2500may be disposed at four vertex of a tetragon to constitute an array of the pillars2500. In some embodiments, the array of the pillars2500may include three pillars located at three vertex of a triangle. According to the present embodiments, first gaps may be disposed between two adjacent pillars2500in a row or in a column, and a second gap may be disposed between two adjacent pillars2500in a diagonal direction. Since the four pillars2500are respectively located at four vertex of a tetragon, the second gap may be disposed in a central region of the tetragon. Although the present embodiment is described in conjunction with an example that the four pillars2500are located at four vertex of a tetragon, the present embodiment is not limited thereto. For example, in some embodiments, the pillars2500may include three pillars and the three pillars may be located at three vertex of a triangle.

The pillars2500may be formed on an underlying layer2400disposed on a semiconductor substrate2100. Before forming the underlying layer2400, an etch target layer2200and a hard mask layer2300may be sequentially formed between the underlying layer2400and the semiconductor substrate2100.

A separation wall layer may be formed to cover the pillars2500, and the separation wall layer may be anisotropically etched to form the first separation walls2600having a spacer shape on sidewalls of the pillars2500. The first separation walls2600may be formed of an insulation layer having an etch selectivity with respect to the underlying layer2400and the pillars2500. For example, the first separation walls2600may be formed by depositing an ultra low temperature oxide (ULTO) layer having a thickness of about 200 angstroms and by anisotropically etching the ULTO layer until top surfaces of the pillars2500and the underlying layer2400are exposed. Since the first separation walls2600are formed to surround the sidewalls of the pillars2500, each of the first separation walls2600may have a cylindrical shape.

A BCP layer2700may be formed on the pillars2500and the first separation walls2600to fill the first and second gaps between the pillars2500. The BCP layer2700may be formed by coating a polystyrene-poly(methyl meta acrylate) (PS-PMMA) co-polymer material, a polystyrene-poly(di methyl siloxane) (PS-PDMS) co-polymer material, or a silicon contained polystyrene-poly(di methyl siloxane) (Si contained PS-PDMS) co-polymer material. That is, the BCP layer2700may be coated to fill the first and second gaps and to cover top surfaces of the pillars2500.

The BCP layer2700may be annealed to be phase-separated into a first domain2710including a second separation wall2711covering the first separation walls2600and a second domain2730separated from the pillars2500by the first domain2710. The first domain2710may be formed to fill the first gaps between the pillars2500disposed in a row or in a column direction. Further, the first domain2710may be formed to have a ‘U’-shaped sectional view in the second gap which is located at a central region of the array of the four pillars2500. The second domain2730may be formed to fill an inside region of the ‘U’-shaped first domain2710. That is, the second domain2730may be surrounded by the ‘U’-shaped first domain2710. As illustrated in the plan view ofFIG. 35, the second domain2730may be separated from the pillars2500by the first domain2710. Meanwhile, when the BCP layer2700is coated to cover the top surfaces of the pillars2500, the BCP layer2700may be phase-separated to include third domains2731on the pillars2500. The third domains2731may be composed of substantially the same polymer blocks as the second domain2730. Thus, the second and third domains2730and2731may have a different phase from the first domain2710.

The BCP layer2700may include polystyrene (PS) blocks and poly-di-methyl-siloxane (PDMS) blocks, and a ratio of the PS blocks to the PDMS blocks may be controlled by a volume ratio of the PS blocks to the PDMS blocks. The first domain2710may be composed of the PDMS blocks which are phase-separated from the BCP layer2700. The second and third domains2730and2731may be composed of the PS blocks which are phase-separated from the BCP layer2700.

FIG. 37is a plan view illustrating a step of forming first and second openings2307and2309, andFIGS. 38aand38bare cross-sectional views respectively taken along lines A-A′ and B-B′ ofFIG. 37. Referring toFIGS. 37,38a, and38b, the second domain2730may be selectively removed to form the first opening2307. When the second domain2730is selectively removed, the third domains2731may also be removed to expose the pillars2500. The exposed pillars2500may then be selectively removed to form the second openings2309.

That is, the first opening2307may be formed by selectively removing the second domain2730and the first domain2710below the second domain2730. The second openings2309may be formed by removing the third domains2731and the pillars2500. As illustrated in the plan view ofFIG. 37, the first opening2307may be defined by a shape of the first domain2710and the second openings2309may be defined by shapes of the pillars2500. The first and second openings2307and2309may expose portions of the underlying layer2400. The exposed portions of the underlying layer2400may be selectively removed to form mask pattern2409. Subsequently, although not shown in the drawings, the hard mask layer2300may be etched using the mask pattern2409as an etch mask to form a hard mask, and the etch target layer2200may be etched using the hard mask as an etch mask to form contact holes penetrating the etch target layer2200.

FIG. 39is a plan view illustrating a step of phase-separating a BCP layer3700, andFIGS. 40aand40bcross-sectional views respectively taken along lines A-A′ and B-B′ ofFIG. 39. Referring toFIGS. 39,40a, and40b, an array of first separation walls3600may be formed on an underlying layer disposed on a semiconductor substrate3100. Each of the first separation walls3600may be formed to have a cylindrical shape. Specifically, an array of pillars may be formed on the underlying layer. The array of the pillars may include four pillars located at four vertex of a tetragon in a plan view. In some embodiments, the array of the pillars may include three pillars located at three vertex of a triangle. Before forming the underlying layer, an etch target layer3200and a hard mask layer3300may be sequentially formed on the semiconductor substrate3100, and the underlying layer may be formed between the hard mask layer3300and the underlying layer. A separation wall layer may be formed to cover the pillars, and the separation wall layer may be anisotropically etched to form the first separation walls3600having a spacer shape on sidewalls of the pillars.

The first separation walls3600may be formed of an insulation layer having an etch selectivity with respect to the underlying layer formed of a silicon oxynitride (SiON) layer and the pillars formed of an SOC layer. For example, the first separation walls3600may be formed by depositing an ultra low temperature oxide (ULTO) layer having a thickness of about 200 angstroms and by anisotropically etching the ULTO layer until top surfaces of the pillars and the underlying layer are exposed. Since the first separation walls3600are formed to surround the sidewalls of the pillars, each of the first separation walls3600may have a cylindrical shape. The pillars may be selectively removed to form openings defined by the first separation walls3600. Thus, inside regions (i.e., the openings) and outside regions of the first separation walls3600may expose the underlying layer.

The BCP layer3700may be coated to fill the inside regions (i.e., the openings) and the outside regions of the first separation walls3600. The BCP layer3700may be formed by coating a silicon contained polystyrene-poly(di methyl siloxane) (Si contained PS-PDMS) co-polymer material. The BCP layer3700may be annealed to be phase-separated into first domains3710that includes second separation walls3711having spacer shapes covering inner and outer sidewalls of the first separation walls3600and second domains3730separated from each other by the first domains3710.

The second domains3730may include (i) the region which is surrounded by the first domain3710and located at a central region of the array of the first separation walls3600and (ii) four regions each of which is surrounded by the first domains3710formed on the inner sidewalls of the first separation walls3600, as illustrated in a plan view ofFIG. 39. The second domains3730may be separated from each other by the first domains3710and the first separation walls3600. Each of the second domains3730may be formed to have a post (or cylinder) shape, as illustrated inFIGS. 39,40a, and40b.

The BCP layer3700may include polystyrene (PS) blocks and poly-di-methyl-siloxane (PDMS) blocks, and a ratio of the PS blocks to the PDMS blocks may be controlled by a volume ratio of the PS blocks to the PDMS blocks. The first domains3710may be composed of the PDMS blocks which are phase-separated from the BCP layer3700. The second domains3730may be composed of the PS blocks which are phase-separated from the BCP layer3700.

FIG. 41is a plan view illustrating a step of forming outside and inside openings3307and3309, andFIGS. 42aand42bare cross-sectional views respectively taken along lines A-A′ and B-B′ ofFIG. 41. Referring toFIGS. 41,42a, and42b, the second domains3730may be selectively removed to form the outside opening3307located at the outside region of the first separation walls3600and to form the inside openings3309located at the inside regions of the first separation walls3600. That is, the openings3307and3309may be formed by selectively removing the PS blocks constituting the second domains3730. As illustrated in the plan views ofFIGS. 39 and 41, the openings3307and3309may be defined by the first domains3710and may be formed to have hole shapes penetrating the first domains3710. The openings3307and3309may expose portions of the underlying layer. The exposed portions of the underlying layer may be selectively removed to form mask pattern3409exposing portions of the hard mask layer3300.

Subsequently, although not shown in the drawings, the hard mask layer3300may be etched using the mask pattern3409as an etch mask to form a hard mask, and the etch target layer3200may be etched using the hard mask as an etch mask to form contact holes penetrating the etch target layer3200.

Referring toFIGS. 43 and 44, the methods of fabricating a semiconductor device according the embodiments may be performed such that the openings and the contact holes are not formed in a peripheral region adjacent to a cell array region of the semiconductor device when the openings and the contact holes repeatedly arrayed in the cell array region are formed.

As illustrated inFIG. 43, when an array of the pillars500is formed in the cell array region, a peripheral blocking pattern501may be formed to cover an entire surface of the peripheral region adjacent to the cell array region. That is, when an SOC layer is formed on a semiconductor substrate300and the SOC layer is patterned to form the pillars500in the cell array region, the SOC layer on the peripheral region is not patterned due to the peripheral blocking pattern501. Subsequently, a separation wall layer may be conformally formed, i.e., in a liner type, on an entire surface of the substrate including the pillars500and the peripheral blocking pattern501. A BCP layer may be coated on the separation wall layer to fill spaces between the pillars500. The BCP layer may be annealed to be phase-separated into first domains710, providing second separation walls711and second domains (not shown) in the cell array region. When the BCP layer may be annealed, a peripheral BCP residue703covering the peripheral blocking pattern501may also be phase-separated into a first peripheral domain713and second peripheral domains733. Subsequently, the second domains may be selectively removed to form openings301between the pillars500in the cell array region. When the second domains are selectively removed to form the openings301, no openings are formed in the peripheral region because the phase-separated peripheral BCP residue703is disposed to cover an entire surface of the peripheral blocking pattern501. The separation wall layer may then be anisotropically etched to form first separation walls605in the cell array region.

If fine patterns such as the openings301are formed in both the cell array region and the peripheral region, an extra mask and an extra etching process may be required to selectively remove the fine patterns formed in the peripheral region. In such a case, openings301adjacent to a boundary between the cell array region and the peripheral region may be damaged to have abnormal shapes when the openings301in the peripheral region are removed using the extra mask and the extra etching process. However, according to the embodiments, no openings are formed in the peripheral region even without use of the extra mask and the extra etching process. Thus, all the openings301in the cell array region may be uniformly formed in terms of the size.

As illustrated inFIG. 44, when an array of pillars is formed in the cell array region, a peripheral blocking pattern (501ofFIG. 43) is not formed in the peripheral region adjacent to the cell array region. Thus, when first separation walls1600are formed in the cell array region, no first separation wall1600is formed in the peripheral region. In such a case, when a BCP layer is formed on the substrate including the first separation walls1600and the BCP layer is annealed to be phase-separated into first domains1710and second domains (not shown) in the cell array region, a peripheral BCP residue1703on the peripheral region may also be phase-separated into a first peripheral domain1713and second peripheral domains1733. Subsequently, the second domains may be selectively removed to form openings1301in the cell array region. When the second domains are selectively removed to form the openings1301, no openings are formed in the peripheral region because the phase-separated peripheral BCP residue1703is disposed to cover an entire surface of the peripheral region.

If fine patterns such as the openings1301are formed in both the cell array region and the peripheral region, an extra mask and an extra etching process may be required to selectively remove the fine patterns formed in the peripheral region. In such a case, openings1301adjacent to a boundary between the cell array region and the peripheral region may be damaged to have abnormal shapes when the openings1301in the peripheral region are removed using the extra mask and the extra etching process. However, according to the embodiments, no openings are formed in the peripheral region even without use of the extra mask and the extra etching process. Thus, all the openings1301in the cell array region may be uniformly formed in terms of the size.

The methods of fabricating a semiconductor device according to the embodiments may be used in formation of an array of contact holes having a pitch size of about 38 nanometers or less. In addition, according to the embodiments, the contact holes may be uniformly formed without any deformation of the contact holes.

According to the embodiments described above, nano-sized structures or nano structures may be readily fabricated by forming a block co-polymer (BCP) layer on a large-sized substrate. The nano structures may be used in fabrication of polarizing plates or in formation of reflective lens of reflective liquid crystal display (LCD) units. The nano structures may also be used in fabrication of separate polarizing plates as well as in formation of polarizing parts including display panels. For example, the nano structures may be used in fabrication of array substrates including thin film transistors or in processes for directly forming the polarizing parts on color filter substrates. Further, the nano structures may be used in molding processes for fabricating nanowire transistors or memories, electronic/electric components for patterning nano-scaled interconnections, catalysts of solar cells and fuel cells, etch masks, organic light emitting diodes (OLEDs), and gas sensors.

The methods according to the aforementioned embodiments and structures formed thereby may be used in fabrication of integrated circuit (IC) chips. The IC chips may be supplied to users in a raw wafer form, in a bare die form, or in a package form. The IC chips may also be supplied in a single package form or in a multi-chip package form. The IC chips may be integrated in intermediate products such as mother boards or end products to constitute signal processing devices. The end products may include toys, low end application products, or high end application products such as computers. For example, the end products may include display units, keyboards, or central processing units (CPUs).