Semiconductor device

Provided is a semiconductor device wherein chip size is reduced, while potential on the dummy word lines is fixed. The semiconductor device is provided with: a memory cell array including a plurality of memory cells, a plurality of word lines for controlling memory operations of the plurality of memory cells, and a plurality of dummy word lines that do not participate in memory operations of the plurality of memory cells; and a guard ring surrounding the memory cell array. The plurality of dummy word lines are electrically fixed to the guard ring.

NOTICE REGARDING RELATED APPLICATION

The present invention is based upon the priority claim of Japanese Patent Application No. 2012-181799 (filed on Aug. 20, 2012), the disclosure of which is incorporated herein in its entirety by reference thereto.

TECHNICAL FIELD

The present invention relates to a semiconductor device. In particular it relates to a semiconductor device provided with embedded word lines.

BACKGROUND ART

There are constant demands for reductions in the chip size of semiconductor devices, a typical example being DRAM (Dynamic Random Access Memory). In order to reduce the chip size, embedded gate type transistors in which the gate electrodes are embedded in the surface layer of a semiconductor substrate are sometimes used as selection transistors constituting a memory cell. The gate electrode of such an embedded gate type transistor is disposed as a word line used to select a memory cell.

Further, in order to maintain the process conditions within a memory cell array, dummy word lines are sometimes provided in addition to the word lines actually used to control the memory cells. Providing dummy word lines at fixed intervals makes the density of word lines constant.

In addition, a guard ring for protecting the memory cell array from external noise is sometimes provided at the periphery of the memory cell array.

Here, patent literature article 1 discloses a technique whereby a guard ring is provided three-dimensionally in order to block noise that propagates to circuits on the semiconductor substrate. Also, patent literature article 2 discloses a power MOSFET in which the breakdown voltage is increased by providing a plurality of guard ring regions. Further, patent literature article 3 discloses a fuse device provided with a guard ring.

PRIOR ART LITERATURE

Patent literature

SUMMARY OF THE INVENTION

Problems to be Resolved by the Invention

It should be noted that each of the disclosures in the abovementioned prior art literature is incorporated herein by reference. The following analysis is performed from the viewpoint of the present invention.

As discussed hereinabove, a memory cell array is sometimes provided with dummy word lines. It is not sufficient for these dummy word lines simply to be provided within the memory cell array, and from the point of view of circuit stability and resistance to noise they are preferably fixed to a constant electric potential.

Accordingly, upon considering the layout when dummy word lines are wired to the memory cell array, the inventors devised bundling the dummy word lines in a poly/metal wiring layer in a boundary region between the memory cell array and a sub-word driver adjacent to the memory cell array.

FIG. 2is a drawing illustrating an example of the layout of a semiconductor device.FIG. 2illustrates a wiring example in which dummy word lines are bundled in a dummy word line connecting region12, which is a boundary region between a memory cell array10and a sub-word driver11. A memory cell region13consisting of a plurality of memory cells is included in the memory cell array10shown inFIG. 2. The memory cell region13and the sub-word driver11are connected by means of a plurality of embedded word lines14. For example, an embedded word line14(a gate electrode of an embedded type transistor) and a metal wiring line15are connected by means of a contact16.

On the other hand, a dummy word line17is connected to a poly/metal wiring layer18by means of a metal wiring line15aand contacts16aand16b. It should be noted that inFIG. 2, dummy word lines17are provided at intervals of five embedded word lines14.

Bundling the dummy word lines17in this way in a boundary region between the memory cell array10and the sub-word driver11necessitates the provision of a dummy word line connecting region12, which would not originally have been required. As a result, the boundary region between the memory cell array10and the sub-word driver11is enlarged, contrary to the desire for a reduction in the chip size of the semiconductor device. A semiconductor device in which the chip size is reduced while at the same time the electric potential of the dummy word lines is fixed is thus desirable.

Means of Overcoming the Problems

A first aspect of the present invention provides a semiconductor device comprising a memory cell array including a plurality of memory cells, a plurality of word lines which control storage operations of the abovementioned plurality of memory cells, and a plurality of dummy word lines which do not contribute to the storage operations of the abovementioned plurality of memory cells, and a guard ring surrounding the abovementioned memory cell array, the abovementioned plurality of dummy word lines being electrically fixed to the abovementioned guard ring.

Advantages of the Invention

According to the first aspect of the present invention there is provided a semiconductor device in which the chip size is reduced while at the same time the electric potential of the dummy word lines is fixed.

MODES OF EMBODYING THE INVENTION

One mode of embodiment will first be described in outline with reference toFIG. 1. It should be noted that the drawing reference codes appended in this outline are appended to each element for convenience, as examples to aid understanding, and the present invention is not intended to be limited to the modes of embodiment illustrated in the drawings.

As discussed hereinabove, the electric potential of the dummy word lines within a memory cell array must be fixed. Here, bundling the dummy word lines in a boundary region between a memory cell array and a sub-word driver results in an enlargement of the chip size of the semiconductor device. A semiconductor device in which the chip size is reduced while at the same time the electric potential of the dummy word lines is fixed is thus desirable.

Accordingly, the semiconductor device illustrated inFIG. 1is provided as one example. The semiconductor device illustrated inFIG. 1comprises a memory cell array100including a plurality of memory cells, a plurality of word lines which control storage operations of the plurality of memory cells, and a plurality of dummy word lines which do not contribute to the storage operations of the plurality of memory cells, and a guard ring200surrounding the memory cell array100, the plurality of dummy word lines being electrically fixed to the guard ring200.

In other words, by connecting the dummy word lines and the guard ring200, the electric potential of the dummy word lines is made to be the same as the electric potential of the guard ring200. As a result, wiring lines supplying an electric potential to the dummy word lines are not required in the boundary section between the memory cell array100and the sub-word driver (which is not shown inFIG. 1), and this contributes to reducing the chip size of the semiconductor device by reducing the surface area of the boundary section.

It should be noted that the guard ring200surrounding the memory cell array100includes a condition in which the guard ring200encompasses the memory cell array100(the condition illustrated inFIG. 1), and a condition in which a portion of the memory cell array100is in contact with a portion outside the guard ring200(a condition in which part of the guard ring200is missing).

Further, the following modes are possible.

[Mode 1] This is in line with the semiconductor device according to the abovementioned first aspect.

[Mode 2] The abovementioned plurality of word lines and the abovementioned plurality of dummy word lines are preferably disposed as gate electrodes of embedded gate type transistors formed on a semiconductor substrate.

[Mode 3] The abovementioned guard ring is preferably formed by means of a diffusion layer surrounding the abovementioned memory cell array.

[Mode 4] The abovementioned guard ring is preferably a wiring line guard ring in which the periphery of the abovementioned memory cell array is surrounded by a metal wiring line.

Specific embodiments will now be described in more detail with reference to the drawings.

First Mode of Embodiment

A first mode of embodiment will be described in more detail with reference to the drawings.

A semiconductor device will first be described in outline.

FIG. 3is a drawing illustrating an example of the overall configuration of a semiconductor device1according to this mode of embodiment. The semiconductor device1is provided with terminals such as command terminals (/RAS, /CAS, /WE), a reset terminal (/RST), address terminals ADD, power supply terminals (VDD, VSS), clock terminals (CK, /CK) and data terminals DQ.

The semiconductor device1illustrated inFIG. 3consists of an internal power supply generating circuit21, a clock input circuit22, a DLL circuit23, a command input circuit24, a command decoding circuit25, an address input circuit26, an address latch circuit27, a FIFO circuit28, an input/output buffer29and an array region30.

The internal power supply generating circuit21generates a voltage for use in the semiconductor device1.

The clock input circuit22receives a differential clock (CK, /CK) and outputs a single-phase clock CLKIN.

The DLL circuit23generates an internal clock LCLK by delaying the single-phase clock CLKIN.

Commands for the semiconductor device1are received by the command input circuit24via the command terminals. More specifically, commands consisting for example of a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE are input. Commands consisting of these signals are decoded by the command decoding circuit25, the result of the decoding being output to the array region30.

Address signals issued from outside are received by the address input circuit26and are latched by the address latch circuit27. Address signals are supplied to a column decoder32and a row decoder33within the array region30.

The array region30contains a memory cell array region31, the column decoder32and the row decoder33. The memory cell array region31contains a plurality of memory cell arrays arranged in a matrix. The column decoder32decodes a column address from the address signal, and selects a bit line of the memory cell to be accessed. The row decoder33decodes a row address from the address signal, and selects a word line.

During a data read operation, read data that have been read from the selected memory cell are output from the data terminals DQ via the FIFO circuit28and the input/output buffer29. During a data write operation, write data that have been input into the data terminals DQ are written to the selected memory cell via the input/output buffer29and the FIFO circuit28.

The memory cell array region31will now be described. The memory cell array region31contains a plurality of memory cell arrays, and sub-word drivers corresponding to the memory cell arrays.

FIG. 4is a drawing illustrating an example of the layout of the memory cell array region31. A memory cell array consists of a prescribed plurality of memory cells grouped together, a sub-word driver being connected corresponding to each memory cell array.

FIG. 5is an enlargement of the region enclosed by the dotted lines inFIG. 4. As illustrated inFIG. 5, a memory cell array40contains a plurality of embedded word lines (embedded sub-word lines). Each embedded word line is connected to sub-word drivers41and42adjacent to the memory cell array40. Further, dummy word lines are wired into the memory cell array40at fixed intervals. InFIG. 5, dummy word lines are provided in a proportion of one dummy word line for five embedded word lines. It should be noted that the memory cell array40also contains a plurality of bit lines, but these have been omitted fromFIG. 5.

The memory cell array40is surrounded by a guard ring43.

FIG. 6is an enlargement of the region enclosed by the dotted lines inFIG. 5. The embedded word line44illustrated inFIG. 6is connected to a metal wiring line46by means of a contact45. On the other hand, the dummy word line47is connected to the guard ring43by means of a contact48.

FIG. 7is a drawing illustrating an example of a section through A-A inFIG. 6. InFIG. 7, a P-well51is formed in the surface of a semiconductor substrate50, and an N-diffusion layer52is laminated thereon. The guard ring43(diffusion layer guard ring) is configured by means of the P-well51and the N-diffusion layer52. Further, the guard ring43is demarcated by means of an STI (shallow trench isolation)53. Further, a transistor gate electrode is disposed in the P-well51and the STI53as an embedded word line44. The embedded word line44is connected to the metal wiring line46by means of the contact45.

FIG. 8is a drawing illustrating an example of a section through B-B inFIG. 6. In contrast toFIG. 7, inFIG. 8the dummy word line47is connected to the P-well51of the guard ring43by means of the contact48. The electric potential of the dummy word line47connected to the P-well51is thus fixed to the electric potential of the P-well51. In this way, by connecting a dummy word line via a contact48to a guard ring43(diffusion layer guard ring) disposed at the periphery of a memory cell array, the electric potential of the dummy word line can be fixed.

As a result, the region required when dummy word lines are bundled in a boundary region between the memory cell array and the sub-word driver is no longer required (the dummy word line connecting region12inFIG. 2is not required). By reducing the surface area of the boundary region between the memory cell array and the sub-word driver it is possible to reduce the chip size of the semiconductor device1.

Second Mode of Embodiment

A second mode of embodiment will next be described in detail with reference to the drawings. There are no differences between the overall configuration and the like of the semiconductor device2according to the present mode of embodiment and the semiconductor device1, so a description ofFIG. 3toFIG. 6relating to the semiconductor device2will be omitted. The point of difference between the semiconductor device1and the semiconductor device2lies in the fact that instead of implementing the guard ring43using a diffusion layer guard ring, the guard ring is implemented using a wiring line guard ring in which the periphery of the memory cell array is surrounded by a metal wiring line.

FIG. 9is a drawing illustrating an example of a section through A-A inFIG. 6.FIG. 10is a drawing illustrating an example of a section through B-B inFIG. 6. InFIG. 9andFIG. 10the same reference codes are appended to constituent elements that are the same as inFIG. 7andFIG. 8, and a description thereof is omitted.

As illustrated inFIG. 10, if a wiring line guard ring is used as the guard ring43, the electric potential of the dummy word line47can be fixed by connecting the dummy word line47to the guard ring43(wiring line guard ring) by means of a contact48. It should be noted that the embedded word line44is connected to the metal wiring line46by means of a contact45, in the same way as inFIG. 7.

As a result, by reducing the surface area of the boundary region between the memory cell array and the sub-word driver it is possible to reduce the chip size of the semiconductor device2.

It should be noted that each of the disclosures in the abovementioned cited patent literature is incorporated herein by reference. Within the framework of the entire disclosure of the present invention (including the scope of the claims), and on the basis of its basic technical concepts, modifications and adjustments may be made to the modes of embodying the invention and to embodiments thereof. Further, various combinations of or selections from the various disclosed elements (including for example each element of each claim, each element of each embodiment, and each element of each drawing) are possible within the framework of the scope of the claims in the present invention. In other words, it goes without saying that the present invention includes various variations and modifications that could be arrived at by one skilled in the art in accordance with the entire disclosure and technical concepts therein, including the scope of the claims. In particular, with regard to ranges of numerical values set forth herein, arbitrary numerical values or sub-ranges contained within said ranges should be interpreted as being specifically set forth, even if not otherwise set forth.

EXPLANATION OF THE REFERENCE NUMBERS