A semiconductor structure includes a semiconductor substrate, a power source, and a stacked structure over the semiconductor substrate and coupled to the power source. The stacked structure includes a bottom electrode, a top electrode, and an insulation layer between the top electrode and the bottom electrode, wherein the insulation layer has a breakdown voltage lower than a pre-determined write voltage provided by the power source and higher than a pre-determined read voltage provided by the power source.

TECHNICAL FIELD

This invention relates generally to semiconductor devices, and more particularly to the structure and fabrication methods of one-time-programmable anti-fuse cells.

BACKGROUND

In the field of data storage, there are two main types of storage elements. The first type is volatile memory, in which information is stored in a particular storage element and the information is lost the instant the power is removed from the circuit. The second type is a non-volatile storage element, in which the information is preserved even when the power is removed. Of the second type, some designs allow multiple programming while other designs allow only one-time programming. Typically, the manufacturing techniques used to form non-volatile memory are quite different from standard logic processes, thereby dramatically increasing the complexity and cost.

Typically, one-time-programmable (OTP) memory devices include metal fuses, gate oxide fuses, etc. Metal fuses, as the name suggests, use metal fuses as programming elements. Gate oxide fuses include gate oxides as programming elements.

Conventional OTP memory devices were typically fabricated using aluminum interconnect technologies, which involve aluminum deposition, patterning, and etching, and thus are not compatible with current copper damascene processes, which have become standard processes. In addition, conventional OTP memory devices require either high voltage (such as gate oxide fuses) or high current (such as metal and via anti-fuses) for programming. Such high voltage or high current requirements need to be taken into design considerations, and thus the complexity and the cost of fabricating integrated circuits increases accordingly.

A logic-process-compatible one-time-programmable memory device is therefore highly desirable. Particularly, to be fully compatible with existing CMOS integrated circuits, the high programming current and/or high voltage requirements need to be lowered.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, a semiconductor structure includes a semiconductor substrate, a power source, and a stacked structure over the semiconductor substrate and coupled to the power source. The stacked structure includes a bottom electrode, a top electrode, and an insulation layer between the top electrode and the bottom electrode, wherein the insulation layer has a breakdown field/voltage lower than a pre-determined write voltage provided by the power source and higher than a pre-determined read voltage provided by the power source.

In accordance with another aspect of the present invention, a one-time-programmable (OTP) anti-fuse includes a semiconductor substrate, a first dielectric layer over the semiconductor substrate, a lower-level metal line comprising copper in the first dielectric layer, a via over the lower-level metal line wherein the via and the lower-level metal line define an area of at least partial alignment, an insulation layer between the lower-level metal line and the via and occupying the area of at least partial alignment, and an upper-level metal line comprising copper in a second dielectric layer having a low dielectric constant, wherein the upper-level metal line is over and electrically coupled to the via.

In accordance with yet another aspect of the present invention, an OTP anti-fuse includes a semiconductor substrate, a bottom metal line in the first dielectric layer, a second dielectric layer over the bottom metal line and the first dielectric layer, an opening in the second dielectric layer, a diffusion barrier layer in the opening, the diffusion barrier layer extending onto the bottom metal line and sidewalls of the opening, an insulation layer in the opening and enclosed by the diffusion barrier layer from bottom and sides, and a top metal line filling a remaining portion of the opening. The insulation layer has a breakdown field/voltage lower than a pre-determined write voltage provided by a power source and higher than a pre-determined read voltage provided by the power source.

In accordance with yet another aspect of the present invention, a method for forming an OTP anti-fuse includes providing a semiconductor substrate, pre-determining a read voltage, pre-determining a write voltage, and forming a stacked structure over the semiconductor substrate. The step of forming the stacked structure includes forming a bottom electrode, forming a top electrode, and forming an insulation layer between the top electrode and the bottom electrode, wherein the insulation layer is configured to be broken down if the write voltage is applied between the top electrode and the bottom electrode, and to not be broken down if the read voltage is applied between the top electrode and the bottom electrode.

In accordance with yet another aspect of the present invention, a method for forming an OTP anti-fuse includes providing a semiconductor substrate, forming a first dielectric layer over the semiconductor substrate, forming a lower-level metal line comprising copper in the first dielectric layer, forming an insulation layer having at least a portion over the lower-level metal line, forming a via over the insulation layer, and forming an upper-level metal line comprising copper over the via, wherein the upper-level metal line is in a second dielectric layer.

In accordance with yet another aspect of the present invention, a method for forming an integrated circuit structure includes simultaneously forming a first lower-level copper line and a second lower-level copper line in a first dielectric layer, simultaneously forming a first diffusion barrier layer having at least a portion over the first lower-level copper line and a second diffusion barrier having at least a portion over the second lower-level copper line, forming an insulation layer over the first diffusion barrier layer, simultaneously forming a third diffusion barrier layer over the insulation layer and a fourth diffusion barrier layer over the second diffusion barrier layer, simultaneously forming a first via over the third diffusion barrier layer and a second via over the fourth diffusion barrier layer, and simultaneously forming a first upper-level copper line and a second upper-level copper line in a third dielectric layer, wherein the first upper-level copper line is electrically coupled to the third diffusion barrier layer and the first via, and wherein the second upper-level copper line is electrically coupled to the second lower-level copper line and the second via.

The advantageous features of the present invention include reduced write voltages and full compatibility with the existing formation processes of integrated circuits.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A one-time-programmable (OTP) anti-fuse cell and the methods of forming the same are provided. The intermediate stages of manufacturing a preferred embodiment of the present invention are illustrated. The operations of the preferred embodiments are then discussed. Throughout the various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.

In a first embodiment, an OTP anti-fuse cell, which has a via-like structure, is formed simultaneously with a via structure. Both the OTP anti-fuse and the via structure comprise lower-level metal lines and upper-level metal lines interconnected by vias.FIG. 1illustrates two regions100and200over a semiconductor substrate20, which have devices (not shown) formed thereon. Region100is used for forming an OTP anti-fuse cell, and region200is used for forming a via.FIG. 1also illustrates a metallization layer m over the semiconductor substrate20, wherein metallization layer m includes a dielectric layer22, a lower-level metal feature102in region100and a lower-level metal feature202in region200. Metallization layer m may be any of the metallization layers except the top metallization layer. Dielectric layer22preferably comprises a material having a dielectric constant (k value) of less than 3.9, and may contain nitrogen, carbon, hydrogen, oxygen, fluorine, and combinations thereof. More preferably, dielectric layer22is a porous film with a k value of less than about 3.5. Dielectric layer22may be formed using commonly used methods, such as chemical vapor deposition (CVD), spin-on, atomic layer deposition (ALD), plasma enhanced CVD (PECVD), and the like. For simplicity, semiconductor substrate20is not shown in subsequent drawings.

In the preferred embodiment, metal lines102and202are formed using a single damascene process, in which trenches are formed first, followed by the formation of diffusion barrier layers104and204and metal lines102and202in the trenches. Diffusion barrier layers104and204are used to prevent copper in metal lines102and202from diffusing into and poisoning the neighboring dielectric materials. The preferred materials for diffusion barrier layers104and204include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and other alternatives. Preferably, metal lines102and202comprise copper or copper alloys, although they may comprise other metallic materials such as aluminum, silver, gold, and the like. In the preferred embodiment, the formation of metal lines102and202includes depositing a thin layer of seed copper or copper alloy, then plating to fill the trenches. In other embodiments, commonly used chemical vapor deposition (CVD) methods such as plasma enhanced CVD can be used. A chemical mechanical polish (CMP) is performed to remove excess material and level the surfaces of the metal lines102and202. Cap layers (not shown) may be formed on metal lines102and202to prevent copper from being in direct contact with low-k dielectric materials.

Referring toFIG. 2, a via inter-metal dielectric (IMD) layer24and a trench MD layer26are successively formed. Via IMD layer24preferably has a low k value of less than about 3.9 and may comprise carbon-doped silicon oxide, fluorine-doped silicon oxide, organic low-k materials, and/or porous low-k materials. It is preferably formed by spin-on, chemical vapor deposition (CVD), or other known methods. More preferably, dielectric layers24and/or26are porous films having low dielectric constants of less than about 3.5. In the preferred embodiment, the materials of dielectric layer22and IMD layers24and26have different etching characteristics, so that one layer may be used as an etch stop layer when the overlying layer is etched. In alternative embodiments, etch stop layers (not shown) are formed between layers22,24and26.

FIG. 3illustrates the formation of via openings128and228and trench openings130and230in regions100and200, respectively. To form via openings128and228, a photo resist (not shown) is formed and patterned over trench IMD layer26. An anisotropic etching cuts through trench IMD layer26and via IME layer24and stops at the metal lines102and202, respectively. The photo resist is then removed. Similarly, with the masking of an additional photo resist (not shown), trench openings130and230are formed, preferably by an anisotropic etching cutting through trench IMD layer26.

FIG. 4illustrates the formation of a diffusion barrier layer32, which is preferably formed of a material resistive to diffusion of copper, such as titanium, titanium nitride, tantalum, tantalum nitride, and the like, and which may have a composite structure comprising more than one layer.

A thin insulation layer34is then formed, as shown inFIG. 5. Preferably, insulation layer34includes a material having a low breakdown field/voltage. In the preferred embodiment, insulation layer34includes a low-k dielectric material, although oxides, nitrides, oxynitrides, and high-k dielectric materials can also be used. More preferably, insulation layer34has a k value of less than about 3.9, and even more preferably less than about 3.5. The preferred materials include Black Diamond® from Applied Materials (SiOCH), Coral from Novellus, fluorinated silicate glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, fluorine-doped silicon oxide, organic low-k materials, and/or porous low-k materials. In other embodiments, insulation layer34includes high-k materials (k value greater than about 3.9) that are easy to breakdown, such as HfO2, Ta2O5, ZrO2, Pr2O3, TiO2, SrTiO3, and the like. Preferably, the formation methods include plasma enhanced chemical vapor deposition (CVD), atomic layer deposition (ALD), spin on, and the like. In an exemplary embodiment, insulation layer34comprises Black Diamond and is formed using CVD. The process conditions include a reaction gas trimethylchlorsilane (TMS) at a flow rate of between about 10 sccm and about 1200 sccm, oxygen at a flow rate of between about 10 sccm and about 500 sccm, a RF power of between about 100 W and about 1000 W, a deposition temperature of between about 300° C. and about 400° C., and a deposition time of between about 0.1 seconds and about 100 seconds.

The thickness and material of the insulation layer34partially determine the breakdown field/voltage, hence the write voltage of the OTP anti-fuse. Since the electric field in a dielectric layer is inversely proportional to its thickness, a thin insulation layer34is more likely to be broken down, and the write voltage can be lowered. In the preferred embodiment, insulation layer34has a thickness of less than about 1000 Å, and more preferably between about 50 Å and about 200 Å.

Insulation layer34is preferably formed conformally on sidewalls of trench opening130and via opening128. Preferably, the thickness of the insulation layer34on the sidewalls of trench opening130and via opening128should not cause the breakdown of the insulation layer34when applied with a read voltage, for example, 1.2V. To make OTP anti-fuses fully compatible with CMOS circuits, the optimum thickness and material of the thin insulation layer34is preferably determined by the voltages that can be supplied by CMOS circuits. In the preferred embodiment, a write voltage of 5 volts or lower is preferred.

InFIG. 6, a photo resist36is formed and patterned. In the preferred embodiment, only the region over trench opening130is masked by photo resist36. The remaining portions of photo resist36are removed. Alternatively, the entire region100is masked, and region200is exposed. The exposed portions of insulation layer34are then removed, preferably by etching, and the remaining portion of the insulation layer34is denoted as dielectric layer134. Next, photo resist36is removed.

In alternative embodiments, the formation of insulation layer134includes forming a photo resist (not shown) covering region200while leaving region100exposed, and blanket forming the dielectric layer134. When the photo resist is removed, the portion of insulation layer34on the photo resist is also removed.

Referring toFIG. 7, a second diffusion barrier layer38is formed. The materials and formation methods are similar to those of first barrier layer32, thus are not repeated herein.

FIG. 8illustrates the formation of upper-level metal lines142and242connecting to vias140and240in regions100and200, respectively. As is known in the art, metal lines142and242may be formed by filling trench openings130and230and via openings128and228with a metallic material, preferably copper or copper alloys. A CMP is then performed to remove excess material. First diffusion barrier layer32, insulation layer134, and second diffusion barrier layer38may have portions over the top surface of trench IMD layer26. Preferably, these portions are also removed by CMP. The remaining portions of first diffusion barrier layer32and second diffusion barrier layer38form diffusion layers132and138in region100and diffusion layers232and238in region200.

In the previously-discussed embodiment, dual damascene processes are performed to form vias140and240and upper-level metal lines142and242. In alternative embodiments, vias140and240and upper level metal lines142and242may be formed separately by using single damascene processes. In addition, although vias and upper-level metal lines are illustrated as formed in two dielectric layers, one skilled in the art will realize that they can be formed in a single dielectric layer.

In alternative embodiments, metal lines142and242and connecting vias140and240shown inFIG. 8can be formed in the form of contacts, and the corresponding structure is shown inFIG. 9. A preferred formation process is briefly described as follows. After the formation of lower-level metal lines102and202in dielectric layer22, a diffusion barrier layer and a thin insulation layer are formed and patterned, leaving a diffusion barrier layer132and a thin dielectric layer134in region100and a diffusion barrier layer232in region200. A metal layer, which preferably comprises tungsten, aluminum, silver, gold, metal alloy, metal nitride, and combinations thereof, is then formed. By patterning the metal layer, contacts140and240are formed in regions100and200, respectively. Dielectric layer24is then formed.

In the embodiments shown inFIG. 9, upper-level metal lines142and242and lower-level metal lines102and202may also be formed using the same methods as used for forming contacts140and240, although damascene processes are preferably used. Alternatively, the anti-fuse cell in region100may be formed using methods for forming contacts, while the via structure in region200is formed using damascene processes. However, the embodiment shown inFIG. 9requires additional process steps.

Referring back toFIG. 8, metal line142, via140and diffusion barrier layer138form one electrode of an OTP anti-fuse cell150, and metal line102and diffusion barrier layer132form the other electrode. Insulation layer134electrically insulates the two electrodes, forming the anti-fuse cell150. The anti-fuse cell150can be used as an OTP memory cell, which has a high-resistance state and a low-resistance state. To program the OTP anti-fuse cell150, a voltage may be applied between the two electrodes, causing a breakdown in insulation layer134. The resulting OTP anti-fuse cell150will be in a low-resistance state.

In a second embodiment, an OTP anti-fuse having a crown-type MIM capacitor structure is formed. Referring toFIG. 10, a semiconductor substrate310is provided with an insulation layer314formed thereon. A metal line316, for example, a copper line316, is formed over insulation layer314, followed by the deposition of an inter-metal dielectric (IMD) layer320over metal line316. A damascene opening312is etched through IMD layer320, exposing metal line316.

Referring toFIG. 11, a first diffusion barrier layer322is deposited conformally within the damascene opening312and on IMD layer320. First diffusion barrier layer322may comprise titanium nitride, tantalum nitride, titanium silicon nitride, and/or tantalum silicon nitride. A first copper layer324is formed over first diffusion barrier layer322, for example, by electroplating or electroless plating. The copper is formed on the bottom and sidewalls of the damascene opening. First copper layer324will form a portion of the bottom plate of the crown-type anti-fuse. A second diffusion barrier layer326is conformally deposited over copper layer324. Second diffusion barrier layer326preferably comprises materials similar to those of first diffusion barrier layer322.

An insulation layer328is conformally deposited over second barrier layer326. Insulation layer328preferably comprises materials similar to those described for insulation layer34(refer toFIG. 5).

Next, a third diffusion barrier layer330, which is similar to first and second diffusion barrier layers322and326, is formed. A second copper layer334is then deposited to fill the damascene opening.

Referring now toFIG. 12, the previously formed layers are polished down until the layers remain only within the damascene opening312. The second copper layer334forms the top electrode of the capacitor. An OTP anti-fuse, which has dielectric layer328as the insulation layer, and metal lines316and334as portions of a bottom electrode and a top electrode, respectively, is thus formed.

In a third embodiment of the present invention, an OTP anti-fuse having a planar MIM structure, as is shown inFIG. 13, is formed. The planar anti-fuse includes a top plate412, a bottom plate414and an insulation layer410therebetween. Bottom plate414is preferably bigger than top plate412. Contact plugs416and418connect to the bottom plate414and top plate412, respectively. Each of the top and bottom plates412and414may further include diffusion barrier layers. One skilled in the art will realize the respective formation steps.

In a fourth embodiment of the present invention, an OTP anti-fuse having a convex stack, as is shown inFIG. 14, is formed. The OTP anti-fuse includes a dielectric structure510over a dielectric layer518. If viewed from the top, dielectric structure510preferably has the shape of a rectangle, and more preferably a square. The length and width of dielectric structure510are preferably similar to the dimensions of opening128shown inFIG. 5. A bottom plate516is formed on dielectric structure510, followed by the formation of an insulation layer514and a top plate512. Bottom plate516, insulation layer514and top plate512preferably extend on sidewalls of dielectric structure510. Again, each of the top and bottom plates512and516may further include diffusion barrier layers. One skilled in the art will realize the respective formation steps.

In the formation of integrated circuits, due to the size limit, it is hard to form a capacitor with a big capacitance, thus a capacitor typically requires a great area to increase the capacitance. An anti-fuse, however, does not have such a requirement, and thus its dimensions (length and width) may be small. In the preferred embodiment, the dimensions of the insulation layer are less than about 110 percent of the minimum dimension allowed by the forming technology (or design rules). More preferably, the dimensions of the insulation layer are as small as the minimum dimension allowed by the forming technology. For example, in 65 nm technology, the diameter and thickness of the insulation layer are about 100 nm and about 10 nm, respectively. The anti-fuses are preferably formed simultaneously with the formation of capacitors having similar structures in order to save cost. Preferably, the via-like, crown-type and planar anti-fuses are formed in metallization layers, and more preferably use damascene processes, so that their formation is compatible with the existing interconnect structure formation processes.

The previously discussed anti-fuse will be operated under two voltages: a relatively low voltage for read operations and a relatively high voltage for write operations. The anti-fuses are configured (formed) such that the write voltage is high enough to cause the breakdown of the insulation layer, while the read voltage is not high enough to cause the breakdown. The material and the thickness of the insulation layer will be determined accordingly.

Exemplary connections of the anti-fuse cells are illustrated inFIGS. 15 through 17.FIG. 15illustrates a preferred connection for an anti-fuse cell. The schematically illustrated OTP anti-fuse cell150is coupled in series to a low-voltage node having a source-line voltage VSLat one end and a bitline having a voltage VBLat the other end. In an exemplary embodiment, a transistor154is connected so that the selection of the anti-fuse cell150is controlled by a selection gate having a voltage VSG. VSLis preferably 0V. When a voltage VSGgreater than the threshold voltage of the transistor154is applied, the OTP anti-fuse cell150is selected. If a high-resistance state is to be written, the bitline VBLvoltage is 0V. Since voltage applied on OTP anti-fuse cell150is 0V, OTP anti-fuse cell150remains intact with a high resistance. Conversely, if a low resistance state is to be written, VBLis applied with a high voltage, such as 5V. Insulation layer134is non-conductive, thus the entire voltage (VBL−VSL) is applied on the insulation layer134, resulting in breakdown. The two electrodes of the OTP anti-fuse cell150are thus electrically connected, and the OTP anti-fuse cell150is in a low-resistance state. One skilled in the art will realize that the high-resistance state or low-resistance state can be denoted as either state “0” or “1”, depending on the design preference.

In a read operation, a voltage is applied to the selection gate to turn on the transistor154. A low voltage VBLgreater than 0V but lower than the breakdown voltage of the OTP anti-fuse cell150, such as 1.2V, is applied to the bitline. VSLis preferably 0V. If the OTP anti-fuse cell150is in a high-resistance state, a low current IBLis detected. Conversely, if the OTP anti-fuse cell150is in a low-resistance state, a high current IBLis detected. The current IBLis thus used to determine the state of the OTP anti-fuse cell150.

FIG. 16illustrates a simpler form for connecting anti-fuse cells. A voltage V, which may be either the write voltage or the read voltage, is applied between the two plates of the anti-fuse. When a write voltage is applied, insulation layer134breaks down, and the two plates are electrically connected. When a read voltage is applied, the magnitude of the current I is used to determine the state of the anti-fuse.

FIG. 17illustrates two mirror bits controlled by a MOS device. The read and write operations of the anti-fuse on the left is controlled by VBL1and VSL2, while the read and write operations of the anti-fuse on the right is controlled by VBL2and VSL1. Both bits are controlled by a gate voltage VSG.

FIG. 18illustrates a series of parallel anti-fuses1601through160n, which are connected to a drain region of a common MOS device162. Using this connection, the n anti-fuses are all controlled by MOS device162. The read and write operations of each bit are controlled by voltages VSL, VSGand the respective bitline voltages VBL1through VBLn.

The anti-fuse cells of the present invention can be used in various applications. A common use is for replacing malfunctioning circuits, such as memory cells. By breaking down the insulation layer and causing the anti-fuse to be conductive, a redundant memory cell connected to the OTP anti-fuse cell will replace a malfunctioning memory cell. Anti-fuses can also be used to represent a chip identification number, which is preferably defined by breaking down a series of OTP anti-fuse cells while leaving the rest intact. Use of the present invention also includes selecting circuit functions by enabling/disabling certain circuits and adjusting resistances for analog or digital circuit.