Structure of signal lines in the fan-out region of an array substrate

An array substrate includes a plurality of signal lines disposed in a display area; a plurality of signal pads disposed in a non-display area; and a fan-out portion disposed in the non-display. The fan-out portion includes a plurality of fan-out lines connecting the plurality of signal lines to the plurality of signal pads. Each of the plurality of fan-out lines includes a pattern electrically connected to a corresponding signal pad of the plurality of signal pads, and a straight portion electrically connected to a corresponding signal line of the plurality of signal lines. The pattern includes a first conductive layer. The straight portion includes the first conductive layer and a second conductive layer disposed on the first conductive layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 10-2015-0114553, filed on Aug. 13, 2015, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND

Field

One or more exemplary embodiments relate to electronic devices, and, more particularly, to an array substrate of an electronic device.

Discussion of the Background

A flat panel-type display apparatus typically includes two substrates with image displaying members, such as liquid crystal molecules, light-emitting devices, electrophoretic particles, etc., disposed between the two substrates. One of the two substrates may be an array substrate including a display area and a peripheral area outside the display area. The display area may include signal lines (e.g., gate lines and data lines) and pixel electrodes arranged in a matrix formation. Ends of the signal lines may extend into the peripheral area to connect to another layer or an external driving circuit. The signal lines may include a fan-out portion in which intervals between the signals lines narrow toward the ends. As the peripheral area (e.g., non-display area) of a flat panel-type display is reduced, an area of the fan-out portion may also be reduced, which, in turn, may cause increased variation in resistances of the corresponding wires in the fan-out portion.

SUMMARY

One or more exemplary embodiments provide an array substrate configured to minimize a variation in resistances of fan-out lines in a fan-out portion of the array substrate.

According to one or more exemplary embodiments, an array substrate includes a plurality of signal lines disposed in a display area; a plurality of signal pads disposed in a non-display area; and a fan-out portion disposed in the non-display. The fan-out portion includes a plurality of fan-out lines connecting the plurality of signal lines to the plurality of signal pads. Each of the plurality of fan-out lines includes a pattern electrically connected to a corresponding signal pad of the plurality of signal pads, and a straight portion electrically connected to a corresponding signal line of the plurality of signal lines. The pattern includes a first conductive layer. The straight portion includes the first conductive layer and a second conductive layer disposed on the first conductive layer.

According to one or more exemplary embodiments, an array substrate includes a plurality of signal lines disposed in a display area; a plurality of signal pads disposed in a non-display area; and a fan-out portion disposed in the non-display area. The fan-out portion includes a plurality of fan-out lines connecting the plurality of signal lines to the plurality of signal pads. Each of the plurality of fan-out lines includes: a pattern electrically connected to a corresponding signal pad of the plurality of signal pads; a straight portion electrically connected to a corresponding signal line of the plurality of signal lines; and a first contact disposed at a boundary between the pattern and the straight portion. A distance between the first contact and the corresponding signal pad reduces with increasing distance from a center portion of the fan-out portion.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Unless otherwise specified, the illustrated exemplary embodiments are to be understood as providing exemplary features of varying detail of various exemplary embodiments. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects of the various illustrations may be otherwise combined, separated, interchanged, and/or rearranged without departing from the disclosed exemplary embodiments. Further, in the accompanying figures, the size and relative sizes of layers, films, panels, regions, etc., may be exaggerated for clarity and descriptive purposes. Also, like reference numerals denote like elements.

FIG. 1is a schematic plan view of an array substrate, according to one or more exemplary embodiments.FIG. 2is a schematic cross-sectional view of a pixel of the array substrate ofFIG. 1, according to one or more exemplary embodiments.

Referring toFIG. 1, the array substrate10(hereinafter, referred to as substrate10) may include a display area DA and a peripheral area PA outside (e.g., around) the display area DA. A buffer layer11may be formed on the substrate10. The display area DA includes a plurality of gate lines GL1to GLn extending in a first direction, a plurality of data lines DL1to DLm extending in a second direction crossing the first direction, and a plurality of pixels P electrically connected to the gate lines and the data lines.

Referring toFIG. 2, each of the pixels P may include a thin film transistor TFT and a pixel electrode50. The thin film transistor TFT may include a gate electrode20formed on the substrate10, an active layer35on the gate electrode20, and a source electrode40aand a drain electrode40bformed on the active layer35. A first ohmic contact layer (not shown) may be further disposed between the active layer35and the source electrode40a, and a second ohmic contact layer (not shown) may be disposed between the active layer35and the drain electrode40b. A first insulating layer13may be disposed between the gate electrode20and the active layer35, and a second insulating layer15may be disposed between the source electrode40aand the drain electrodes40band the pixel electrode50. The gate electrode20may be connected to a corresponding gate line of the gate lines GL1to GLn. The source electrode40amay be connected to a corresponding data line of the data lines DL1to DLm. The drain electrode40bmay be connected to the pixel electrode50.

Adverting back toFIG. 1, the peripheral area PA may include a plurality of data fan-out portions DF and a plurality of gate fan-out portions GF. Each of the data fan-out portions DF includes a plurality of data fan-out lines DFL. An end of each of the data fan-out lines DFL is electrically connected to a data pad DP corresponding to the data fan-out line DFL, and the other end is electrically connected to a data line of the data lines DL1to DLm corresponding to the data fan-out line DFL. An external device (not illustrated), such as a driving integrated circuit, may be electrically connected to the data pad DP. For example, a driving integrated circuit including a data driver may be bonded to the data pads DP as a chip-on-glass (COG)-type driving integrated circuit, and may be mounted on the peripheral area PA of the substrate10. The data fan-out lines DFL in each of the data fan-out portions DF become more adjacent to each other from a data line DL side toward a data pad DP side.

Each of the gate fan-out portions GF includes a plurality of gate fan-out lines GFL. An end of each of the gate fan-out lines GFL is electrically connected to a gate pad GP corresponding thereto, and the other end of each gate fan-out line GFL is electrically connected to a corresponding gate line of the gate lines GL1to GLn. An external device (not illustrated), such as a driving integrated circuit, may be electrically connected to the gate pads GP. For example, a driving integrated circuit including a gate driver may be bonded to the gate pads GP in a COG-type driving integrated circuit, and may be mounted on the peripheral area PA of the substrate10. The gate fan-out lines GFL in each of the gate fan-out portions GF may become more adjacent to each other from a gate line GL side toward a gate pad GP side.

The data fan-out lines DFL and the gate fan-out lines GFL may include a first conductive layer formed at the same layer and including the same material as the gate lines GL1to GLn. In some parts of the data fan-out lines DFL and the gate fan-out lines GFL, a second conductive layer may overlap the first conductive layer. The second conductive layer may be formed at the same layer and including the same material as the data lines DL1to DLm. In addition, the gate fan-out portions GF and the data fan-out portions DF may have similar structures to each other, and, as such, a data fan-out portion DF will be described in more detail as an exemplary of the gate fan-out portions GF and the data fan-out portions DF.

FIG. 3is a schematic plan view of a data fan-out portion DF of the array substrate ofFIG. 1, according one or more exemplary embodiments.FIG. 4is a schematic plan view of an enlarged region C ofFIG. 3.FIG. 5is a schematic cross-sectional view of the array substrate ofFIG. 4taken along sectional line V-V ofFIG. 4, andFIG. 6is a schematic diagram of a variation in resistances of the fan-out lines in a fan-out portion of the array substrate ofFIG. 3, according to one or more exemplary embodiments.

Referring toFIGS. 3 to 5, the plurality of data fan-out lines DFL may be arranged on the data fan-out portion DF. An end of each of the plurality of data fan-out lines DFL is connected to the data pad DP, and the other end of each of the data fan-out lines DFL is connected to a corresponding data line of the data lines DL1to DLm. Each of the data fan-out lines DFL supplies a data signal to a corresponding data line of the data lines DL1to DLm.

The data fan-out lines DFL may be spaced apart from each other in a data fan-out region. The data fan-out region may include a pad portion SA1, a contact portion SA5, a first region SA2, and second regions SA3and SA4. The plurality of data pads DP may be arranged on the pad portion SA1, and a driving integrated circuit (not shown) including a data driver is mounted on the pad portion SA1. In addition, the contact portion SA5is more adjacent to the display area DA than the pad portion SA1. The first region SA2and the second regions SA3and SA4are disposed between the pad portion SA1and the contact portion SA5. The second regions SA3and SA4are formed as adjacent triangles, illustrated inFIG. 3as dashed lines. The first region SA2is defined by the pad portion SA1and the second regions SA3and SA4. In this manner, the first region SA2has an inverted triangular shape. On the pad portion SA1, the data fan-out lines DFL are connected to the data pads DP at constant intervals therebetween, and the data fan-out lines DFL are formed in straight (or substantially straight) lines.

The data fan-out lines DFL extend from the pad portion SA1to the first region SA2. In the first region SA2, the data fan-out lines DFL are arranged at constant intervals therebetween. Intervals between the data pads DP are less than intervals between the data lines DL in the display area DA. In this manner, lengths of the data fan-out lines DFL connecting the data pads DP to the data lines DL may vary. As such, there may be a variation in resistances of the data fan-out lines DFL.

To reduce the variation between the lengths of the data fan-out lines DFL, each of the data fan-out lines DFL may have a pattern DFL1in the first region SA2. For example, the pattern DFL1may be a zigzag (or serpentine) pattern, however, any other suitable pattern may be utilized in association with exemplary embodiments described herein. In addition, the number of zigzag patterns may increase from the edges of the first region SA2toward a center of the first region SA2to reduce the resistance of the pattern DFL1from the center toward the edges of the fan-out portion. In this manner, the variation in the resistances of the data fan-out lines DFL may be compensated. The pattern DFL1may include a first conductive layer20aformed at the same layer and including the same material as the gate lines GL1to GLn.

The data fan-out lines DFL extend from the first region SA2to the second regions SA3and SA4. The data fan-out lines DFL include straight portions DFL2that extend in oblique directions and are spaced apart from each other in the second regions SA3and SA4. Intervals between the straight portions DFL2in the second regions SA3and SA4increase toward the data lines DL, and lengths of the straight portions DFL2may increase from the center of the fan-out portion toward the edges of the fan-out portion. Each of the straight portions DFL2may further include a second conductive layer40overlaid on the first conductive layer20awith an insulating layer (e.g., first insulating layer13) disposed therebetween. The second conductive layer40may be formed at the same layer and include the same material as the data lines DL1to DLm, and may be connected to the first conductive layer20ain parallel. In this manner, a resistance of the straight portion DFL2may be reduced.

The second conductive layer40may be electrically connected to the first conductive layer20avia a contact. For example, the contact may include a first contact CNT1connecting an end of the second conductive layer40to the first conductive layer20a, and a second contact CNT2connecting the other end of the second conductive layer40to the first conductive layer20a. The first contact CNT1may be located at a boundary between the pattern DFL1and the straight portion DFL2. In this manner, the first contact CNT1may approach the data pad DP toward the edges of the data fan-out portion DF. As such, a length of the second conductive layer40connected to the first conductive layer20ain parallel may increase from the center toward the edges of the contact portion SA5. Accordingly, from the center toward the edges of the contact portion SA5, a reduction in the resistance of the straight portion DFL2in which the first conductive layer20aand the second conductive layer40are connected in parallel is increased. To this end, a variation in resistances of the data fan-out lines DFL may be further reduced.

According to one or more exemplary embodiments, the data fan-out lines DFL extend from the second regions SA3and SA4to the contact portion SA5, and are connected to the data lines DL in the contact portion SA5. An expansion101ahaving a greater width than the other parts may be formed at the other end of each data fan-out line DFL, and the expansion101amay be electrically connected to an expansion301aof the data line DL via a bridge electrode BEa.

FIG. 6is a diagram of a variation in resistances of fan-out lines in a fan-out portion of the array substrate ofFIG. 3according to a location of a fan-out line in the fan-out portion, according to one or more exemplary embodiments.

InFIG. 6, line (I) denotes the resistance of an example in which the pattern DFL1and the straight portion DFL2only include the first conductive layer20a, line (II) denotes the resistance of an example in which the pattern DFL1and the straight portion DFL1both include a stacked structure of the first conductive layer20aand the second conductive layer40, and line (III) denotes the resistance of an example in which the pattern DFL1includes the first conductive layer20aand the straight portion DFL2includes a stacked structure of the first conductive layer20aand the second conductive layer40(as in the exemplary embodiments described herein).

As seen in the diagram ofFIG. 6, according to line (II), the resistance R of the data fan-out lines DFL is reduced from than that of line (I), but a difference between the resistances R of the data fan-out lines DFL at the center and edges A and B of the data fan-out portion is relatively large. According to the line (III), the first contact CNT1is disposed between the pattern DFL1and the straight portion DFL2, and the length of the straight portion DFL2including the stacked structure of the first conductive layer20aand the second conductive layer40increases toward the edges A and B of the data fan-out portion. In this manner, a resistance R value of the data fan-out line DFL at the center of the data fan-out portion (e.g., a minimum resistance R value) is similar to that of line (I), and a resistance R value of the data fan-out line DFL at the edges A and B of the data fan-out portion (e.g., a maximum resistance R value) is similar to that of line (II). Accordingly, even when the area of the fan-out portion is reduced as the peripheral area PA of a display apparatus is reduced, a variation in resistances R of the data fan-out lines DFL may be reduced, as may be the resistances R of the gate fan-out lines GFL.

FIG. 7is a schematic cross-sectional view of the array substrate ofFIG. 4taken along sectional line VII-VII′, according to one or more exemplary embodiments. It is noted thatFIG. 7shows a cross-sectional view taken along sectional line VII-VII′ ofFIG. 4for descriptive convenience, but corresponds to a modified example of the substrate10ofFIG. 1. Hereinafter, a data fan-out portion DF ofFIG. 7will be described with reference toFIGS. 3, 4, and 7.

Referring toFIGS. 3, 4, and 7, each of the data fan-out lines DFL on the buffer layer11may include the pattern DFL1connected to the data pad DP, the straight portion DFL2connected to the data line DL, and the first contact CNT1located at a boundary between the pattern DFL1and the straight portion DFL2. The pattern DFL1includes the first conductive layer20a, and the straight portion DFL2may include the first conductive layer20aand the second conductive layer40that are connected to each other in parallel with the first insulating layer13disposed therebetween.

The first contact CNT1may be located at the boundary between the pattern DFL1and the straight portion DFL2. That is, a location of the first contact CNT1is more adjacent to the data pad DP toward the edges of the data fan-out portion DF from the center portion. In this manner, a variation in resistances of the data fan-out lines DFL may be reduced.

In addition, each of the data fan-out portions DFL may further include a third conductive layer40′ overlapping the first conductive layer20awith the first insulating layer13disposed therebetween. The third conductive layer40′ is in a floating state to be insulated from the data fan-out lines DFL. The third conductive layer40′ may be formed at the same layer and including the same material as the second conductive layer40. It is noted, however, that the third conductive layer40′ is isolated from the second conductive layer40due to a cut area CA, and, as such, the third conductive layer40′ may be considered a dummy electrode.

As described above, when each of the data fan-out lines DFL includes the third conductive layer40′, heights of the data fan-out lines DFL may be uniformed. As such, when a seal (not shown) for bonding the substrate10to another substrate to manufacture a display apparatus, uniformity in a seal gap may be improved. In addition, since the third conductive layer40′ is formed to overlap the first conductive layer20a, when a defect (such as a short-circuit) occurs in the first conductive layer20a, the third conductive layer40′ may repair the first conductive layer20a. As such, manufacturing efficiency of the substrate10may be improved.

According to exemplary embodiments, variation in resistances of the fan-out lines in the fan-out portions may be reduced even when the areas of the fan-out portions decrease.