Managing a mode to access a memory component or a logic component for machine learning computation in a memory sub-system

A first mode setting signal is received from a host system. The first mode setting signal indicates a first mode. A memory component is memory component to the first mode based on the first mode setting signal. In the first mode, memory cells of the memory component are exposed to the host system. A second mode setting signal is received from the host system. The second mode setting signal indicates a second mode. The memory component is set to the second mode based on the second mode setting signal. In the second mode, a machine learning operation component of the memory component is exposed to the host system.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to managing a mode to access a memory component or a logic component for machine learning computation in a memory sub-system.

BACKGROUND

A memory sub-system can be a storage device, a memory module, and a hybrid of a storage device and memory module. The memory sub-system can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components. In general, a host system can utilize a memory sub-system to store data at the memory components and to retrieve data from the memory components.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to managing a mode to access a memory component or a logic component for machine learning computation in a memory sub-system. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction withFIG. 1. In general, a host system can utilize a memory sub-system that includes one or more memory components (also hereinafter referred to as “memory devices”). The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

A conventional memory sub-system includes only memory component(s) for storing data provided by the host system. Accordingly, an interface between the host system and the memory sub-system (e.g., a system bus) need only handle data and commands directed to the memory component(s). For example, if a host system transmits a command (e.g., a write command) and corresponding data to the memory sub-system over the system bus, the command and corresponding data are automatically routed to the memory component(s). If, however, the memory sub-system were to include additional components other than the memory component(s), confusion over how to direct commands and/or data received from the host system may arise. Conventional memory sub-systems lack a specific mechanism to determine which of a number of separate components commands and/or data are directed to and to route the commands and/or data to the appropriate component. Accordingly, significant errors can occur as the commands and/or data are likely to be routed to the wrong component.

Aspects of the present disclosure address the above and other deficiencies by having a memory sub-system that provides different modes of operation that enable the host system to access different types of components (e.g., an array(s) of memory cells and a logic component (e.g., logic gates or an array(s) of resistors for performing a machine learning computation)) included in a memory component. The memory sub-system or the memory component of the memory sub-system can operate in one mode for exposing the array(s) of memory cells in the memory component to the host system. In a second mode of operation, the memory sub-system or the memory component can instead expose the logic component disposed on the memory component to the host system.

Advantages of the present disclosure include, but are not limited to, maximizing utilization of the memory sub-system (i.e., a memory component of the memory sub-system) by providing two separate operation modes—one for performing the traditional operation of storing and retrieving data and another one for performing logical operations such as machine learning computation). Moreover, by providing the two separate operation modes, the memory sub-system requires only one interface for the memory component. That is, there is no need to implement two separate interfaces each for the array of memory cells and the logic component in the memory component. Accordingly, the present disclosure simplifies implementation of the logic component in the memory component.

The host system120can be a computing device such as a desktop computer, laptop computer, network server, mobile device, or such computing device that includes a memory and a processing device. The host system120can be coupled to the memory sub-system110via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transmit data between the host system120and the memory sub-system110. The host system120can further utilize an NVM Express (NVMe) interface to access the memory components (e.g., memory devices130) when the memory sub-system110is coupled with the host system120by the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system110and the host system120.

An example of non-volatile memory devices (e.g., memory device130) includes a negative-and (NAND) type flash memory. Each of the memory devices130can include one or more arrays of memory cells such as single level cells (SLCs) or multi-level cells (MLCs) (e.g., triple level cells (TLCs) or quad-level cells (QLCs)). In some embodiments, a particular memory component can include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. Each of the memory cells can store one or more bits of data used by the host system120. Furthermore, the memory cells of the memory devices130can be grouped as memory pages or memory blocks that can refer to a unit of the memory component used to store data.

Although non-volatile memory components such as NAND type flash memory are described, the memory device130can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), magneto random access memory (MRAM), negative-or (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased.

In some embodiments, the local memory119can include memory registers storing memory pointers, fetched data, etc. The local memory119can also include read-only memory (ROM) for storing micro-code. While the example memory sub-system110inFIG. 1has been illustrated as including the memory sub-system controller115, in another embodiment of the present disclosure, a memory sub-system110may not include a memory sub-system controller115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

In some embodiments, the memory devices130include local media controllers135and a machine learning operation component137. The local media controllers135can operate in conjunction with memory sub-system controller115to execute operations on one or more memory cells of the memory devices130. The machine learning operation component137can perform a machine learning computation in association with memory cells of the memory devices130. In some embodiments, the machine learning operation component137can be coupled to or physically placed adjacent to the memory cells so that the machine learning operation component137can quickly access (and with less power) data needed for the machine learning computation from the memory cells. In other embodiments, the machine learning operation component137can be included in the memory sub-system controller115or the memory device140. In some other embodiments, the machine learning operation component137can be disposed within the memory sub-system110while being external but coupled to both the memory sub-system controller115and the memory devices130and140.

The memory sub-system110includes a mode managing component113that can configure a memory device130to operate under a memory operation mode to enable the host system120to access an array of memory cells or a machine learning operation mode to enable the host system120to access a machine learning operation component137. In some embodiments, the memory sub-system controller115includes at least a portion of the mode managing component113. For example, the memory sub-system controller115can include a processor117(processing device) configured to execute instructions stored in local memory119for performing the operations described herein. In some embodiments, the mode managing component113is a part of the host system120, an application, or an operating system.

The mode managing component113can receive a mode setting signal from the host system120. In one embodiment, the mode setting signal can indicate either the memory operation mode or the machine learning operation mode. In another embodiment, the mode managing component113can determine either the memory operation mode or the machine learning operation mode from the mode setting signal. Then, the mode managing component113can set an operation mode of the memory device130to the memory operation mode or machine learning operation mode based on the mode setting signal. In the memory operation mode, the mode managing component113can expose an array of memory cells of the memory device130to the host system120. In the machine learning operation mode, the mode managing component113can expose the machine learning operation component137of the memory device130to the host system120. Further details with regards to the operations of the mode managing component113are described below.

FIG. 2is a block diagram of an example memory sub-system200in accordance with some embodiments of the present disclosure. In one embodiment, the memory sub-system200includes a memory component210, a bus230, a switch242, and a pull up resistor244.

The memory component210can be a volatile memory device or a non-volatile memory device. In one embodiment, the memory component210includes an array of memory cells215, a machine learning operation component217, a decoding component220, and a mode selection pin250. While the memory component210has only one interface (i.e., the bus230) to the memory sub-system controller or the host system, the memory component210can operate under two separate modes—a memory operation mode and machine learning operation mode based on a signal provided through the mode selection pin250. For example, under the memory operation mode, the memory component210exposes the array of memory cells215to the host system120using mode selection signal255. Under the machine learning operation mode, the memory component210can expose the machine learning operation component217to the host system120based on a different mode selection signal255.

The array of memory cells215can include memory cells or memory units that are the smallest unit to store data. For example, the memory cells can be SLCs, MLCs, TLCs and/or QLCs. In some embodiments, the memory cells can store data associated with the machine learning computation or any data received from the host system.

The machine learning operation component217performs machine learning computation. In some embodiments, the machine learning operation component217can be included within the packaging of the memory component210or internal to the memory component210. The machine learning operation component217is coupled to the array of memory cells215to access data needed to perform the machine learning computation. The machine learning operation component217is also coupled to the decoding component220to receive execution signal for initiating the machine learning computation. The machine learning computation, in general, is performed for image recognition or classification. The machine learning computation involves processing input data (e.g., a picture in pixels) using a machine learning model and outputs prediction (e.g., classification or probability of the classification) about the input data.

A machine learning model is a mathematical representation for finding patterns in input data and classifying the input data or making other predictions or decisions. Examples of the machine learning model includes deep neural networks, convolutional neural networks, and recurrent neural networks. A neural network can include an input layer for receiving input data, an output layer for generating prediction, and a hidden layer(s), in between the input and output layers, for performing calculations (e.g., multiply-accumulate operations) on the input data to generate the prediction. Each layer is composed of a plurality of neurons or nodes. Each node can be assigned a numerical value and coupled to one or more nodes in the succeeding layer through an edge having an assigned weight value. Accordingly, when advancing from one layer to the next (i.e., from the input layer to hidden layer(s) and to output layer), one or more nodes on the current layer can be coupled with one or more nodes in the next layer. As such, a value of a node in the next layer would correspond to an outcome of the multiply-accumulate operations. For example, for each node on the current layer coupled to a node in the next layer, a product (i.e., multiplication) of a value assigned to the node on the current layer and a weight assigned to a corresponding edge that couples the node of the current layer to the respective node on the next layer is computed and then added (i.e., accumulated).

In some embodiments, the machine learning operation component217can correspond to digital logic that is used to execute the machine learning computation. The digital logic can be implemented by using digital logic gates or other such circuitry. For example, the digital logic can be used to implement a machine learning model, to receive input data for the machine learning model, and to store output data for the machine learning model. In some embodiments, the multiply and accumulate operations of the machine learning computation can be performed by the digital logic of the machine learning operation component217. As such, the machine learning operation component217can access the machine learning model and input data stored in the array of memory cells215when performing the machine learning computation.

In some other embodiments, the machine learning operation component217can correspond to a resistor array. For example, the multiply and accumulate operations of the machine learning computation can be performed by the resistor array of the machine learning operation component217. Each resistor of the machine learning operation component217can represent a node in each layer of the machine learning model and resistance values of the resistors can be programmed or tuned to correspond to a weight value of an edge between a pair of resistors that represents a pair of nodes of the neural network. Input and output of resistors can be used to process the multiply and accumulate operations in the machine learning computation. In some embodiments, the output of the last layer of the machine learning model can be coupled with an analog to digital (ADC) converter to convert one or more analog signals that are the last value(s) of the machine learning model to a digital signal that can be used to represent the output of the machine learning model.

The decoding component220decodes an input signal received via the bus230and generates a decoded signal. The decoded signal can include more bits than the input signal. The decoding component220is coupled to the bus230and thus, receives input signal from the memory sub-system controller or the host system120. Examples of such an input signal can include address, data (e.g., data associated with the machine learning computation, any control signal for setting different modes of the memory component210, an execution signal for the machine learning computation), and clock signal. The decoding component220decodes the input signal generating a decoded signal (e.g., decoded address, decoded data, decoded clock signal) for write and read operation to be performed on the array of memory cells215or for performing the machine learning computation by the machine learning operation component217. Additionally, the decoding component220can be coupled to the mode selection pin250and receive mode selection signal255as an input signal. The decoding component220can then generate decoded mode selection signal (not shown). For example, the decoding component220can receive the mode selection signal255having a value indicating the memory operation mode or the machine learning operation mode (e.g., a low value for the memory operation mode and a high value for the machine learning operation mode). The decoding component220can decode the mode selection signal225and generate the decoded mode selection signal having two or more bits enabling the host system120to access either the array of memory cells215or the machine learning operation component217.

The mode selection pin250is an input pin of the memory component210configured to provide mode selection signal to the decoding component220in association with the switch242and pull up resistor244. In some embodiments, the switch242on one end can be coupled to the ground (GND) and on the other end, be coupled to the pull up resistor244and the mode selection pin250. The switch242can receive a control signal (i.e., mode setting signal240) that closes or opens the switch. The mode setting signal240can be provided from the host system (e.g., via the memory sub-system controller by the bus230). The pull up resistor244can be a resistor with high resistance (e.g., 10 kΩ). For example, in case the mode setting signal240corresponds to a control signal to open the switch242, the mode selection pin250is effectively coupled to the pull up resistor244. Because the pull up resistor has high resistance and coupled to supply voltage (e.g., Vcc or Vdd), the mode selection pin250would receive a relatively high voltage signal (e.g., near 5V) and provide the high voltage signal to the decoding component220as the mode selection signal255to indicate one of the memory operation mode and machine learning operation mode. On the other hand, in case the mode setting signal240is provided to the switch242to close the switch, the mode selection pin250would be coupled to the GND and to the pull-up resistor244. As a result, the mode selection pin250would receive a relatively low voltage signal (e.g., near 0V) and provide the low voltage signal to the decoding component220as the255to indicate the other one of the memory operation mode and machine learning operation mode. In some other embodiments, instead of the switch242, the pull up resistor244and the mode selection pin250can be coupled to a voltage source that drives the mode selection pin250to carry the relatively high voltage signal (as a mode setting signal) for the memory operation mode and the relatively low voltage signal (as a mode setting signal) for setting the memory component210to the machine learning operation mode. The voltage source can be controlled by the host system or the memory sub-system controller via the host system.

In further embodiments, the host system can determine what the current operation mode of the memory component210. For example, the host system can determine the current operation mode by storing the last operation mode requested in a local memory of the host system, or requesting what information about the current operation mode from the memory sub-system controller or the local media controller of the memory component210. Once the host system has determined the current operation mode of the memory component210, the host system can determine whether or not to change the operation mode of the memory component210depending on a desired operation. In case the host system determines to change the operation mode, the host system can generate an appropriate mode setting signal for a desired mode (either the memory operation mode or the machine learning operation mode). As such, the host system can ensure that the memory component is in the right operation mode and routes data via the bus230to the right component (either the array of memory cells215or the machine learning operation component217).

The bus230can be a data bus in the memory sub-system200that carries signal such as address, data (e.g., data associated with the machine learning computation, any control signal for setting different modes of the memory component210, an execution signal for the machine learning computation), and clock signal for read and/or write operation or machine learning computation operation to be performed on the memory component210depending on an operation mode of the memory component210. In some embodiments, the bus230interfaces the memory sub-system controller and the memory component210.

FIG. 3is a block diagram of an example memory sub-system in accordance with some other embodiments of the present disclosure. In one embodiment, the memory sub-system300includes a memory component310and a bus330. Similar to the bus230inFIG. 2, the bus330can be a data bus in the memory sub-system300that carries signal such as address, data, and clock signal for read and/or write operation to be performed on the memory component310or for the machine learning computation to be performed by a machine learning operation component317.

The memory component310can be a volatile memory device or a non-volatile memory device. The memory component310can include an array of memory cells315, the machine learning operation component317, a decoding component320, and a mode register350. In some embodiments, the memory component310can operate under two separate modes—a memory operation mode and machine learning operation mode. When the memory component310operates in the memory operation mode, the memory component310can expose the array of memory cells315to the host system120. When the memory component310operates in the machine learning operation mode, the memory component310can expose the machine learning operation component317to the host system130.

The array of memory cells315can include memory cells or memory units that are the smallest unit to store data in the memory operation mode. For example, the memory cells can be SLCs, MLCs, TLCs and/or QLCs.

The machine learning operation component317performs machine learning computation. Similar to the machine learning operation component217inFIG. 2, the machine learning operation component317can be included within the packaging of the memory component310or is internal to the memory component310. In some embodiments, the machine learning operation component317can correspond to digital logic that is used to execute machine learning computation. In some other embodiments, the machine learning operation component317can correspond to a resistor array.

The decoding component320decodes an input signal and generates a decoded signal in a similar manner as the decoding component220inFIG. 2. The decoding component320is coupled to the bus330and thus, receives the input signal (e.g., address, data, clock signal, mode selection signal355) from the memory sub-system controller or the host system. In response, the decoding component320can generate decoded signal (e.g., address, data, clock signal, mode selection signal (not shown)). For example, the decoding component320can receive the mode selection signal355(e.g., a low value for the memory operation mode and a high value for the machine learning operation mode) and provide the decoded mode selection signal having two or more bits enabling the host system to access either the array of memory cells315or the machine learning operation component317.

The mode register350operates to configure a mode of the memory component310. The mode register350can be coupled to the bus330or a separate memory control bus (a bus in the memory sub-system carrying control signals) (not shown) to receive a control signal from the memory sub-system controller or the host system. In some embodiments, the control signal can be mode setting signal340(e.g., a mode register setting (MRS) command). The MRS command can indicate in which mode (either the memory operation mode or the machine learning operation mode) the memory component310should operate. In response, the mode register350can generate mode selection signal355. In some embodiments, the mode selection signal355can correspond to a bit(s) that indicates the memory operation mode or machine learning operation mode to the decoding component320.

In one embodiment, the host system can determine what the current operation mode of the memory component310is before providing the mode setting signal. As described above with respect toFIG. 2, the host system can confirm the current operation mode to ensure correct data is routed to the correct component (either the array of memory cells315or the machine learning operation component317). If the memory component310does not operate under a desired mode, the host system can provide an appropriate mode setting signal to change the operation mode of the memory component310.

In further embodiments, the memory component310can include both the mode register350and a mode selection input pin (e.g., the mode selection pin250inFIG. 2). The mode selection input pin would be configured similar to the mode selection pin250(i.e., coupled with a switch and a pull up resistor). In such a case, the decoding component320can be coupled with both the mode selection input pin and the mode register350and receive two separate mode selection signal in a similar manner as described above regarding theFIGS. 2 and 3. For example, for the memory operation mode, the mode register350can receive the MRS command indicating the respective mode and provide the corresponding mode selection signal to the decoding component320. At the same time, the switch associated with the mode selection input pin can be opened so that the mode selection input pin causes high voltage signal (e.g., near 5V) to be supplied to the decoding component320. On the other hand, while the mode register350receives another MRS command for the machine learning operation mode and provide the corresponding mode selection signal to the decoding component320, the switch can be closed and the mode selection input pin can cause low voltage signal (e.g., near 0V) to be provided to the decoding component320, for the machine learning operation mode.

FIG. 4is a flow diagram of an example method400to set a mode of a memory component, in accordance with some embodiments of the present disclosure. The memory component can include an array of memory cells and a machine learning operation component. The array of memory cells are to store data. The machine learning operation component is to perform a machine learning computation in association with the array of memory cells.

In performing the method400, the processing device can be coupled with a memory component of a memory sub system. In some embodiments, such memory component can include an array of memory cells and a machine learning operation component. Memory cells in the array of memory cells can store any data received from the processing device. The machine learning operation component can perform a machine learning computation in association with the array of memory cells. Within a memory component, the machine learning operation component can be coupled to or physically placed adjacent to the array of memory cells so that the machine learning operation component can quickly access (and with less power) data needed for the computation from memory cells in the array.

At operation410, the processing device receives a mode setting signal from a host system. The mode setting signal can indicate a memory operation mode of a memory component. For example, the mode setting signal can correspond to a series of binary numbers to indicate the memory operation mode (as opposed to a machine learning operation mode). In another example, the mode setting signal can correspond to a control signal that cause voltage signal that satisfies a threshold condition, such as a voltage signal to be above (or below) 2.5V to be supplied to the memory component. Such voltage signal, for example, having a voltage level above 2.5V can indicate the operation mode of the memory component as the memory operation mode. On the other hand, if the mode setting signal does not cause the voltage signal to satisfy the threshold condition, the mode setting signal can be determined to be indicating the machine learning operation mode. Further details of the mode setting signal will be discussed below with respect to operation420.

At operation420, the processing device sets the memory component to the memory operation mode based on the mode setting signal. That is, in the memory operation mode, the processing device can expose the array of memory cells of the memory component to the host system. In some embodiments, the host system can provide the mode setting signal to the memory sub-system (i.e., the processing device). The processing device can cause the memory component to operate in the memory operation mode using the mode setting signal.

In some embodiments, the memory component can include a mode selection component and a decoding component. The mode selection component can provide a mode selection signal to select either the first mode or second mode for the memory component. The processing device can cause the mode selection component to provide an appropriate mode selection signal based on the mode setting signal. For example, the mode selection component can receive the mode setting signal that indicates the memory operation mode and provide a mode selection signal selecting the memory operation mode based on the mode setting signal (and vice versa for the machine learning operation mode). In some embodiments, the mode selection component can provide mode selection signal representing ‘0’ for the memory operation mode and ‘1’ for the machine learning operation mode. In some other embodiments, the mode selection signal can be a voltage signal (e.g., a voltage signal having a voltage value above 2.5V) that represents the memory operation mode selected (whereas, a voltage signal having a voltage value equal to or below 2.5V can represent the machine learning operation mode).Accordingly, depending on the mode selection signal, the mode selection component can configure the decoding component to enable the host system to access either the array of memory cells (e.g., in the memory operation mode) or the machine learning operation component (e.g., in the machine learning operation mode) using the mode selection signal. As such, the mode selection component can indicate a selected mode to the decoding component.

In some embodiments, the mode selection component can include a dedicated pin (i.e., an input pin of the memory component dedicated for mode selection) of the memory component to provide a mode selection signal to a decoding component. For example, the dedicated pin can be coupled with a pull up resistor. The pull up resistor can be provided on the memory sub-system outside of the memory component. The pull up resistor can be a resistor with high resistance (e.g., 10 kΩ). The pull up resistor can cause the dedicated pin to provide a mode selection signal to the decoding component.

In some embodiments, the dedicated pin can be coupled to the pull up resistor as well as to a switch that can couple the dedicated pin and the pull up resistor to the ground (GND). The pull up resistor can be coupled to the dedicated pin on one end and to supply voltage (Vcc) on the other end (SeeFIG. 2 or 3). The processing device can provide the mode setting signal as a control signal to open or close the switch. When the switch is open, the dedicated pin is effectively coupled to the pull up resistor. Because the pull up resistor has high resistance and coupled to Vcc, the voltage drop across the pull up resistor is relatively small, resulting nearly 5V voltage supplied to the dedicated pin. On the other hand, the processing device can provide the mode setting signal that closes the switch. When the switch is closed, the dedicated pin would be coupled to the ground as well as to the pull-up resistor. In this case, the pull up resistor would pass a small amount of current through the closed switch to ground, resulting in a low voltage around 0V to be supplied to the dedicated pin.

Accordingly, when the processing devices provides a mode setting signal (e.g., a control signal that opens the switch, a voltage signal (e.g., a high voltage signal having a voltage value near 5V) satisfying a threshold condition (e.g., a signal having a voltage level above 2.5V) is supplied to the dedicated pin via the pull up resistor, thereby setting the operation mode to the memory operation mode. The dedicated pin can provide the high voltage signal as a mode selection signal indicating the memory operation mode to the decoding component. When the processing devices provides a different mode setting signal (e.g., a control signal causing a voltage signal (e.g., low voltage signal having a voltage value near 0V) not satisfying a threshold condition (e.g., a signal having a voltage level above 2.5V)) that closes the switch, the dedicated pin of the memory component receives, via the pull-up resistor, a low voltage signal having a voltage value near 0V. The dedicated pin can provide the low voltage signal as a mode selection signal indicating the machine learning operation mode to the decoding component.

In other embodiments, the mode selection component can include a mode register. The mode register can be coupled to a memory control bus (a bus in the memory sub-system carrying control signals) or a data bus (e.g., the bus230inFIG. 2or bus330FIG. 3) to receive a control signal from the processing device, such as the mode setting signal (e.g., a mode register setting (MRS) command). The MRS command can include certain command signals such as /CS (Chip Select), /RAS (Row Address Strobe), /CAS (Column Address Strobe), and /WE (Write Enable)) to indicate to which mode the memory component should be set. In response to receiving an MRS command, the mode register can generate corresponding mode selection signal (e.g., control signal in bits indicating either the memory operation mode or machine learning operation mode). Accordingly, the mode register can provide the mode selection signal to the decoding component.

The decoding component of the memory component can decode the received mode selection signal and generate a decoded mode selection signal (e.g., the decoded mode selection signal includes more bits than the mode selection signal) that enables the host system to access the array of memory cells or the machine learning operation component. In some embodiments, the decoded mode selection signal can be two bits (whereas the mode selection signal has one bit—‘0’ for the memory operation mode and ‘1’ for the machine learning operation mode). For the memory operation mode, the decoded mode selection signal can be provided to the array of memory cells or a local controller of the memory component so that the host system can access the array of memory cells. For the machine learning operation mode, the decoded mode selection signal can be provided to the machine learning operation component or the local controller of the memory component so that the host system can access the machine learning operation component. As such, the mode selection signal from the mode selection component can be used to enable the array of memory cells or the machine learning operation component of the memory component to be accessed by the host system.

At operation430, the processing device receives another mode setting signal from the host system. The mode setting signal can indicate a machine learning operation mode of a memory component. For example, the mode setting signal can be an MRS command pre-defined for the machine learning operation mode. In another example, the mode setting signal can be control signal that causes voltage signal having a voltage level below, for example, 2.5V (i.e., not satisfying the threshold condition—voltage signal to be above 2.5V) to be supplied to the memory component (via the dedicated pin of the memory component).

At operation440, the processing device sets the memory component to the machine learning operation mode based on the mode setting signal received at operation430. The mode setting signal can indicate the machine learning operation mode. Thus, the processing device can expose the machine learning operation component of the memory component to the host system. Similar to operation420, the processing device can provide an MRS command indicating the machine learning operation mode to the mode selection component (i.e., the mode register250inFIG. 2) to the memory component so that the memory component can be set to the machine learning operation mode. In some other embodiments, the processing device can transmit the control signal for closing a switch to the switch (i.e., the switch242inFIG. 2) that is coupled to the mode selection component (i.e., the mode selection input pin250inFIG. 2). Based on the mode setting signal, the mode selection component can provide appropriate mode selection signal (in this case, the mode selection signal selecting the machine learning operation mode having a voltage lever near 0V) to the decoding component. Accordingly, the mode selection component can configure the decoding component to enable the host system to access the machine learning operation component (e.g., in the machine learning operation mode).

FIG. 5is a flow diagram of an example method500to operate a memory component in different modes, in accordance with some embodiments of the present disclosure. The memory component can include an array of memory cells and a machine learning operation component. The array of memory cells are to store data. The machine learning operation component is to perform a machine learning computation in association with the array of memory cells.

At operation510, the processing device receives a mode setting signal from a host system. As described above with respect toFIG. 4, the mode setting signal can indicate either the memory operation mode or machine learning operation mode. In some embodiments, the mode setting signal indicating the memory operation mode and the mode setting signal indicating the machine learning operation mode can correspond to control signals that cause voltage signals having different voltage levels (e.g., approximately 0V and 5V) to be supplied to the memory component (via the dedicated pin of the memory component). In some other embodiments, the mode setting signal indicating the memory operation mode and the mode setting signal indicating the machine learning operation mode can correspond to different mode register setting (MRS) commands.

At operation520, the processing device, responsive to receiving the mode setting signal, causes the memory component to operate in one of the memory operation mode or the machine learning operation mode. For example, the host system can communicate with the processing device to perform an image recognition on a picture of an animal using a deep-neural network model to determine a type of animal species and/or a probability of a subject of the picture being the type of the animal species. To initiate the image recognition, the host system can first coordinate with the memory component (i.e., the array of memory cells in the memory component) to store pixel data of the picture in the memory operation mode. Then, the host system can request the memory component (i.e., the machine learning operation component) to perform the image recognition on the pixel data and provide a result (e.g., a type of animal species—“cat” and/or a probability of the subject in the picture being a “cat”—0.97) of the image recognition in the machine learning operation mode. Accordingly, the processing device can receive the mode setting signal for the memory operation mode from the host system at operation510. Then, at operation520, the processing device can cause the memory component to operate in the memory operation mode and store the pixel data. Subsequently, the processing device can receive the mode setting signal for the machine learning operation mode from the host system. Then, at operation520, the processing device can cause the memory component to operate in the machine learning operation mode and perform the machine learning computation. In some embodiments, the processing device can only receive the mode setting signal indicating the machine learning operation mode for performing the machine learning computation. In such a case, the host system can provide the processing device a machine learning computation execution request together with the input data.

In the memory operation mode, at operation530, the processing device receives input data from the host system for machine learning computation. In some embodiments, the input data can be in a form of pixel data representing a picture to be processed for an image recognition via the machine learning computation. In addition, in the memory operation mode, the processing device routes the input data to memory cells in the array of memory cells of the memory component for write operation.

In the machine learning operation mode, at operation540, the processing device receives an execution signal to perform the machine learning computation (e.g., the image recognition) from the host system. In some embodiments, the execution signal can indicate a type of model (e.g., a deep neural network model) and the input data (e.g., the picture of an animal) to be used for the machine learning computation. In some other embodiments, the execution signal can additionally include the input data.

Also, at operation540, the processing device routes the execution signal to the machine learning operation component of the memory component. In response, the machine learning operation component can initiate the machine learning computation by accessing and loading the indicated model and the input data from the array of memory cells based on the execution signal. In some embodiments, the processing device can instead provide the address of the model and the input data to the machine learning operation component along with or as a part of the execution signal. After processing the input data through the model (i.e., performing the multiply-accumulate operations on the input data), the machine learning operation component can provide output data (e.g., a category of the input data (e.g., a type of animal species—“cat”) and/or a probability of the input data belonging to the category (e.g., 0.97)) to an output buffer of the memory component associated with the machine learning operation component. Accordingly, the processing device can detect that the machine learning operation component has generated output data from the machine learning computation by accessing the output buffer. Then, the processing device can provide the output data to the host system. In case the execution signal includes the input data, the machine learning operation component can first store the input data in the array of memory cells before performing the machine learning computation.

In further embodiments, the memory component can switch to the memory operation mode after operating in the machine learning operation mode in response to receiving another mode setting signal for the memory operation mode from the host system while operating in the machine learning operation mode. For example, if an estimated execution time does not satisfy a threshold condition (e.g., less than 2 milliseconds), the processing device can receive another mode setting signal for the memory operation mode so that the processing device can expose the array of memory cells for the host system while waiting for completion of the machine learning computation. During the waiting period, in the memory operation mode, the processing device can enable the host system to access execution codes or operation system stored in the array of memory cells. Upon detecting that the output data of the machine learning computation is ready, the processing device can notify the host system of the completion. In response, the host system can provide a mode setting signal for the machine learning operation mode to the processing device so that the host system can access the output data. The processing device can detect the completion of the machine learning computation by determining that the output data is stored in the output buffer associated with the machine learning operation component.

The example computer system600includes a processing device602, a main memory604(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory606(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system618, which communicate with each other via a bus630.