Methods of forming fine patterns in integrated circuit devices and methods of manufacturing integrated circuit devices including the same

A method of fabricating an integrated circuit device includes forming first and second preliminary mask structures on a hard mask layer in respective first and second regions of the substrate. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures, and the first preliminary mask structure is selectively removed from between the spacers in the first region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region and a second mask pattern including the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region. An insulation layer is patterned using the first and second mask patterns as respective masks to define a first trench in the first region and a second trench in the second region having a greater width than the first trench, and first and second conductive patterns are formed in the first and second trenches.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2010-0007672 filed on Jan. 28, 2010, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

Example embodiments relate to methods of forming a wiring structure for integrated circuit devices and methods of manufacturing non-volatile semiconductor devices having the same, and more particularly, to methods of forming the wiring structure by a spacer patterning process and methods of manufacturing non-volatile semiconductor devices using the same.

2. Description of the Related Art

As the degree of integration of integrated circuit devices increases, conductive structures and wiring structures may be downsized and/or become more dense. The downsizing of the structures usually reduces the cross sectional area of the wiring structure and thus increases electrical resistance in the wiring structures of the semiconductor devices. In addition, the high density of the structures on a substrate usually causes a RC delay (resistance-capacitance delay) and an electronic interference between neighboring conductive structures and wiring structures of the semiconductor devices. Thus, the high degree of the integration may increase failures of the devices, and various research has been conducted for reducing device failures in parallel with studies for increasing the degree of integration.

For example, it has been suggested that copper (Cu) having a relatively low electrical resistance may be used for a wiring material and a low-k dielectric material having a relatively low dielectric constant may be used for an insulation interlayer.

Particularly, copper (Cu) may offer advantages of higher electrical conductivity and lower electro-migration as compared with aluminum (Al), which has been most widely used as a wiring structure in semiconductor devices. Thus, the low resistance property of the copper (Cu) may reduce an RC delay of the wiring structure to thereby reduce and/or minimize the reduction of the operation speed and power consumption of the semiconductor device. In addition, the lower electro-migration of the copper (Cu) may reduce and/or minimize the process limitations and reduce process failures of the semiconductor device, to thereby increase production yield of the semiconductor device.

However, copper (Cu) may present difficulties in patterning through conventional patterning processes including deposition processes for forming a thin layer and etching processes for etching the thin layer. For those reasons, a damascene process has been used for forming a copper pattern in which a recessed portion corresponding to the wiring structure is firstly formed in an insulation interlayer and the recessed pattern is filled with copper (Cu). That is, an insulation interlayer is first patterned to have an opening portion such as a via-hole and a trench therein, and a copper layer is formed on the insulation interlayer to a sufficient thickness to fill up the opening. Then, the copper layer may be removed from the insulation interlayer by a planarization process until a top surface of the insulation interlayer is exposed and thus the copper layer remains in the opening to form the copper wiring structure.

The above conventional damascene process may become more difficult to perform as the degree of integration of a semiconductor device increases. Conventionally, the recessed pattern having the via-hole or the trench is usually formed in the insulation interlayer by a photolithography process using a photolithography pattern on the insulation interlayer as a mask pattern. However, it may be difficult to form fine patterns in the insulation interlayer due to the resolution limitations of the lithography apparatus. In particular, it may be difficult to form fine patterns having a critical dimension (CD) of less than about 40 nm, because the theoretical CD limit for the photolithography process may be about 46 nm. Therefore, the conductive structures such as gate lines and wiring structure for recent very high integrated semiconductor device may be very difficult to form using present photolithography apparatus.

Accordingly, a double patterning technology (DPT) or a spacer patterning technology (SPT) has been suggested for forming fine patterns having a CD of less than the minimum resolution of the photolithography apparatus through consecutive photolithography processes.

In a conventional structure of the semiconductor devices, memory cells including conductive structures and wiring structures may be arranged in a cell area of a chip, and peripheral circuits for applying an electrical power and/or control signals to the memory cells may be arranged in a peripheral/core area of the chip, and a line width of a pattern in the cell area may be different from that of a pattern in the peripheral/core area. Based on the conventional structure of the semiconductor device, the DPT or the SPT performs a double exposure using a first mask pattern having a relatively small pitch and a second mask pattern having a pitch larger than that of the first mask pattern. Therefore, a first pattern having a relatively small line width or a relatively small interval is formed in the cell area of a substrate by a first photolithography process using the first mask pattern and a second pattern having a relatively large line width or a relatively large interval is formed in the peripheral/core cell area of a substrate by a second photolithography process using the second mask pattern. The DPT or the SPT process is usually performed in such a way that the first pattern has a line width smaller than the marginal resolution of the photolithography apparatus simultaneously with the second pattern of which the line width is larger than the marginal resolution of the photolithography apparatus. Therefore, the conductive structures and the wiring structures of which the line widths are varied to be smaller or larger than the marginal resolution (for example, in accordance with the cell area and the peripheral/core area) may be formed on the substrate simultaneously with each other by the DPT or the SPT process.

However, when the mask patterns used in the first and the second photolithography processes are not properly positioned on the substrate, the conductive structures or the wiring structures including both of the first and second patterns cannot be formed on the substrate. For example, in a cell area of a NAND flash memory device in which a plurality of bit lines is arranged between a string selection line (SSL) and a ground selection line (GSL), it may be describable to form each of the bit lines as a fine pattern having a line width smaller than the marginal resolution of the photolithography apparatus. Also, a node separation pattern connected to a group of the bit lines at end portions thereof may be formed into a normal pattern having a line width larger than the marginal resolution of the photolithography apparatus. Thus, the bit lines of the NAND flash memory device may be formed in the cell area of the substrate by a first damascene process using the first mask pattern, and the node separation patterns may be formed in the same cell area of the substrate by a second damascene process using the second mask pattern in a similar manner as the photolithography process for forming the wiring structures in the peripheral/core area of the substrate.

In such a case, when a first damascene position to which the first photolithography process is performed using the first mask pattern is not aligned with a second damascene position to which the second photolithography process is performed using the second mask pattern, the bit lines may not be connected to a proper node separation pattern. Thus, the bit lines neighboring to each other may make contact with each other.

Further, a spacer pattern for forming the first pattern in the cell area may be damaged in a second etching process using the second mask pattern as an etching mask in the peripheral/core area of the substrate. In a conventional DPT or SPT process, the spacer pattern may be formed in the cell area of the substrate by a first etching process using the first mask pattern as an etching mask, and then a supplementary mask pattern for forming the second pattern may be formed in the peripheral/core area by the second etching process. Thus, the spacer pattern in the cell area may be damaged in the second etching process, and the first damascene process using the spacer pattern as an etching may be insufficiently performed. For those reasons, the widths of the via-holes or the trenches may become non-uniform and thus the line widths the bit lines, which are usually formed in the via-holes or the trenches, may also become non-uniform.

SUMMARY

Example embodiments provide a method of forming a wiring structure for a semiconductor device by an SPT using a single photolithography process and a single mask pattern.

Other example embodiments provide a method of manufacturing a non-volatile memory device having the above wiring structure.

According to some example embodiments, there is provided a method of fabricating an integrated circuit device. A substrate including an insulation layer and a hard mask layer thereon is provided, and first and second preliminary mask structures are formed on the hard mask layer in respective first and second regions of the substrate. The second preliminary mask structure has a greater width than the first preliminary mask structure. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures. The first preliminary mask structure is selectively removed from between the spacers in the first region such that the second preliminary mask structure remains between the spacers in the second region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region. The insulation layer is patterned using the first mask pattern as a mask to define a first trench in the first region and using the second mask pattern as a mask to define a second trench in the second region having a greater width than the first trench. First and second conductive patterns are formed in the first and second trenches, respectively.

In an example embodiment, each of the first and second preliminary mask structures may include a sacrificial pattern and a dummy pattern thereon. The dummy pattern may have an etch selectivity relative to the sacrificial pattern. The spacers may be formed by conformally forming a spacer layer on upper surfaces and on the opposing sidewalls of the first and second preliminary mask structures, and anisotropically etching the spacer layer on the upper surfaces of the first and second preliminary mask structures to remove spacer layer therefrom and to remove the dummy pattern from the first preliminary mask structure while maintaining at least a portion of the dummy pattern of the second preliminary mask structure.

In an example embodiment, the first and second preliminary mask structures may be formed by providing a sacrificial layer and a dummy layer on the hard mask layer, and pattering the dummy layer using respective masks to define the respective dummy patterns of the first and second preliminary mask structures in the first and second regions. The sacrificial layer may be isotropically etched using the respective dummy patterns as masks to define the respective sacrificial patterns of the first and second preliminary mask structures and such that a greater portion of the dummy pattern of the first preliminary mask structure is removed as compared to the dummy pattern of the second preliminary mask structure.

In an example embodiment, the sacrificial layer may be at least one of a silicon-containing layer and a carbon-containing layer.

In an example embodiment, the first preliminary mask structure may be selectively removed by, after anisotropically etching the spacer layer, selectively etching the first and second preliminary mask structures using the portion of the dummy pattern of the second preliminary mask structure as a mask to remove the sacrificial pattern of the first preliminary mask structure without substantially removing the second preliminary mask structure.

In an example embodiment, a plurality of the first preliminary mask structures may be formed on the first region, and the spacers may have a width that is less than one half of a difference between a pitch of the first preliminary mask structures and the width of the first preliminary mask structures.

In an example embodiment, a plurality of the first conductive patterns may be formed in respective first trenches in the insulation layer in the first region, and the spacers may have a width that is less than about half of a width of the first conductive patterns.

In an example embodiment, the first region may be a memory cell active region, and the second region may be a peripheral circuit region.

In an example embodiment, the insulation layer may include a lower insulation layer, an etch stop layer, and an upper insulation layer sequentially stacked on the substrate.

According to further example embodiments of the present inventive concept, a method of manufacturing a non-volatile memory device includes forming a string selection line (SSL), a ground selection line (GSL) and a number of word lines (WL) between the SSL and the GSL extending parallel in a second direction on a substrate that has a number of active regions extending in a first direction perpendicular to the second direction. An insulation layer is formed on the substrate and on the string selection line, the ground selection line, and the word lines therebetween. The insulation layer includes a first insulation interlayer, an etch stop layer, and a second insulation interlayer thereon, and further includes a conductive plug extending therethrough to contact an active region. A hard mask layer is formed on the second insulation interlayer, and first and second preliminary mask structures are formed on the hard mask layer in a cell region and a peripheral region of the substrate, respectively. The second preliminary mask structure has a greater width than the first preliminary mask structure. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures, and the first preliminary mask structure is selectively removed from between the spacers in the cell region such that the second preliminary mask structure remains between the spacers in the peripheral region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern comprising the opposing sidewall spacers with a void therebetween in the cell region and a second mask pattern comprising the opposing sidewall spacers and the second preliminary mask structure therebetween in the peripheral region. The insulation layer is patterned using the first mask pattern as a mask to define a first trench in the cell region that exposes the conductive plug and using the second mask pattern as a mask to define a peripheral trench in the peripheral region having a greater width than the first trench. A bit line is formed in the first trench, and a peripheral wiring structure is formed in the peripheral trench.

Other devices and/or methods according to some embodiments will become apparent to one with skill in the art upon review of the following drawings and detailed description. It is intended that all such additional embodiments, in addition to any and all combinations of the above embodiments, be included within this description, be within the scope of the invention, and be protected by the accompanying claims.

DETAILED DESCRIPTION OF EMBODIMENTS

Method of Forming a Wiring Structure for a Semiconductor Device

FIGS. 1A to 1Hare cross-sectional views illustrating processing steps for a method of forming a wiring structure for a semiconductor device in accordance with an example embodiment of the present inventive concept. In the present example embodiment, a hard mask pattern for forming the wiring structure may have different sizes in accordance with local areas of a substrate. However, the hard mask pattern may be obtained by a DPT or a SPT using a single photo mask pattern, as will be described hereinafter.

Referring toFIG. 1A, a substrate10having a first area A and a second area B may be prepared and an insulation layer20, a hard mask layer30, a sacrificial layer40, a dummy or variable mask layer50and a mask pattern60amay be sequentially stacked on the substrate10. In the present example embodiment, the mask pattern60aon the dummy mask layer50may have different line widths in the first area A and the second area B according to line widths of the wiring structures in the respective first and second areas A and B.

For example, the substrate10may include a semiconductor substrate, such as a silicon wafer, and a plurality of conductive structures such as gate structures may be arranged on the substrate10. Thus, the first area A of the substrate10may include a cell array area in which a plurality of unit memory devices is arranged and the second area B may include a peripheral or a core area in which a number of peripheral circuits for driving the memory devices in the cell area may be arranged.

A first pattern having a first line width and a first gap distance may be arranged in the first area A of the substrate10and a second pattern having a second line width larger than the first line width may be arranged in the second area B of the substrate10. The first and the second line widths and the first gap distance may be varied in accordance with characteristics and kinds of the semiconductor device having the wiring structures. Thus, the first pattern having a relatively small line width may be densely formed in the first area A and the second pattern having a relatively large line width may be less densely formed in the second area B.

The insulation layer20may electrically separate underlying conductive structures and upper conductive structures and may include oxide or nitride in accordance with manufacturing conditions and product characteristics of the semiconductor device. In the present example embodiment, the insulation layer20may include a lower insulation layer1on the substrate10, an etch stop layer2on the lower insulation layer1and an upper insulation layer3on the etch stop layer2. However, the insulation layer20may also include a single layer without the etch stop layer, as would be known to one of the ordinary skill in the art.

The hard mask layer30may include a single layer or a multilayer having at least two component layers having different etching characteristics. For example, the hard mask layer30may include a silicon nitride layer.

The sacrificial layer40may be formed on the hard mask layer30by a spin coating process or a chemical vapor deposition (CVD) process and may be into a first sacrificial pattern, referenced by numeral41ainFIG. 1B, in the first area A and a second sacrificial pattern, referenced by numeral42ainFIG. 1B, in the second area B of the substrate10in a subsequent process. The first sacrificial pattern may be used as an etching mask for patterning the first pattern having a relatively smaller line width and high density in the first area A and the second sacrificial pattern may be used as an etching mask for patterning the second pattern having a relatively larger line width and low density in the second area B of the substrate10. Thus, the sacrificial layer40may include various materials in view of the underlying hard mask layer30. For example, the sacrificial layer40may include an amorphous carbon layer (ACL) and a silicon-based layer comprising silicon-based material such as silicon oxide, silicon nitride, silicon carbon nitride and polysilicon.

The dummy mask layer50may be formed on the sacrificial layer40and may comprise a material having etching selectivity with respect to the underlying sacrificial layer40. Thus, the dummy mask layer50may be formed into an etching mask for an etching process for forming the sacrificial pattern. For example, the dummy mask layer50may include a silicon-based material layer and may comprise any one of silicon oxynitride (SiON), silicon oxide, silicon nitride, silicon carbon nitride, polysilicon and combinations thereof. In contrast, the dummy mask layer50may include a metal layer and an organic material layer in other embodiments. Further, the dummy mask layer50may include a multilayer having an anti-reflection pattern for minimizing optical scattering.

In a subsequent three dimensional etching process, the dummy mask layer50may be formed into a first dummy pattern, referenced by numeral51ainFIG. 1B, in the first area A and a second dummy pattern, referenced by numeral52ainFIG. 1B, in the second area B of the substrate10. The first and the second dummy patterns may have different line width and height.

In the present example embodiment, the dummy mask layer50may have a uniform thickness irrespective of the first and the second areas A and B of the substrate10. In contrast, in other embodiments, the dummy mask layer50may have a non-uniform thickness in accordance with the first and the second areas A and B of the substrate10. For example, the dummy mask layer50may have a smaller thickness in the first area A than in the second area B of the substrate10. The dummy mask layer50may have a thickness sufficient for the subsequent three-dimensional etching process.

The mask pattern60amay be formed on the dummy mask layer50and include a first mask pattern61aarranged in the first area A and a second mask pattern62aarranged in the second area B of the substrate10. The mask pattern may function as an etching mask for an etching process against the dummy mask layer50and the sacrificial layer40in the first and the second areas A and B of the substrate10, respectively. The first mask pattern61amay have a relatively smaller line width and the second mask pattern62amay have a relatively larger line width.

The line width of the first mask pattern61amay be determined by a minimal feature size of a manufacturing target device such as a semiconductor device and the line width of the second mask pattern62amay be determined to be larger than that of the first mask pattern61a. In the present example embodiment, the first mask pattern61amay have line widths ranging from a few nm to a few tens of nm.

Referring toFIG. 1B, a sacrificial pattern40aand a dummy mask pattern50amay be formed on the hard mask layer30and thus the hard mask layer30may be partially exposed through the sacrificial pattern40aand the dummy mask pattern50a.

In an example embodiment, the dummy mask layer50may be patterned into the dummy mask pattern50aby an etching process using the mask pattern60aas an etching mask. Thus, the mask pattern60amay be transcribed into the dummy mask pattern50aand the sacrificial layer40may be partially exposed through the dummy mask pattern50a. Then, the sacrificial layer40may be patterned to the sacrificial pattern40aby an etching process using the dummy mask pattern50aas an etching mask. The hard mask layer30may be partially exposed through the sacrificial pattern40a.

Since the dummy mask pattern50amay include the first dummy mask pattern51aarranged in the first area A and the second dummy mask pattern52aarranged in the second area B, the sacrificial pattern40amay also include the first sacrificial pattern41aunderlying the first dummy mask pattern51ain the first area A and the second sacrificial pattern42aunderlying the second dummy mask pattern52ain the second area B.

Particularly, the sacrificial pattern40amay be patterned to have substantially the same line width as the mask pattern60awhile the dummy mask pattern50amay be patterned to have the line width smaller than that of the mask pattern60a, since the dummy mask pattern50amay experience an additional etching process for forming the sacrificial pattern40aas well as the etching process for forming the dummy mask pattern50a.

When the sacrificial layer40may experience the etching process using the dummy mask pattern50aas an etching mask, an isotropic etching process may be performed on the dummy mask pattern50aand thus both of corner portions C and upper surface S of the dummy mask pattern50amay be etched off at the same rate. Therefore, the corner portions C of the dummy mask pattern50amay be formed into a round shape. In such a case, since the second dummy mask pattern52amay have a sufficiently large size, the etching process against the upper surface S may be distinguished from the etching process against the corner portions C of the second dummy mask pattern52a. However, since the first dummy mask pattern51amay have such a small size that the etching process against the upper surface S may not be distinguished from the etching process against the corner portions C of the first dummy mask pattern51a. Thus, etching resistance of the second dummy mask pattern52amay be much greater than that of the first dummy mask pattern51ain the same etching process. For the above reasons, the etching against the upper surface S and the etching against the corner portions C may be overlapped and have a mutual effect on each other at the first dummy mask pattern51a. Thus, the etching process against the first dummy mask pattern51amay be performed multiple directions (referred to as three-dimensional etching process in this application) and the upper portion of the first dummy mask pattern51amay be etched off rapidly due to the intensification of the etching process. In contrast, the second dummy mask pattern52amay be more resistive to the same etching process as against the first dummy mask pattern51a, because the line width and the upper surface of the second dummy mask pattern52ais relatively larger than that of the first dummy mask pattern52a. Therefore, the upper portion of the first dummy mask pattern51amay be etched off much more rapidly than that of the second dummy mask pattern52ain the same etching process due to the three dimensional etching process. The difference of the etching rates of the first and the second dummy mask patterns51aand52amay be clearly increased as the difference of the line widths of the first and the second dummy mask patterns51aand52a.

That is, although the dummy mask layer50may be formed to a uniform thickness across the first and second areas of the substrate10, the thickness T1of the first dummy mask pattern51amay become smaller than the thickness T2of the second dummy mask pattern52awhen the first sacrificial pattern41amay be formed in the first area A and the second sacrificial pattern42amay be formed in the second area B of the substrate10.

Referring toFIG. 1C, a spacer layer70may be formed on the substrate10including the dummy mask pattern50aand the sacrificial pattern40aalong a surface profile thereof.

For example, the spacer layer70may be uniformly formed across the first and the second areas A and B of the substrate10by an atomic layer deposition (ALD) process. The spacer layer70may comprise a material having etching selectivity with respect to the dummy mask pattern50a, the sacrificial pattern40aand the hard mask layer30such as an oxide and a nitride.

Referring toFIG. 1D, the spacer layer70may be partially removed from the substrate10by an anisotropic etching process to thereby form a first spacer71on a sidewall of the first sacrificial pattern41aand a second spacer72on a sidewall of the second sacrificial pattern42a. Thus, the hard mask layer30may still be partially exposed through the sacrificial pattern40aon which the first and second spacers may be formed.

In the anisotropic etching process, the dummy mask pattern50aon the sacrificial pattern40amay also be etched off from the substrate10. Particularly, the first dummy mask pattern51amay be fully removed from the first sacrificial pattern41aby the three dimensional etching process and thus the upper surface of the first sacrificial pattern41amay be exposed. In contrast, the second dummy mask pattern52amay be partially removed from the second sacrificial pattern42aand thus the upper surface of the second sacrificial pattern42amay be still covered with the second dummy mask pattern52a. That is, the first dummy mask pattern51amay be fully removed from the first area A of the substrate10and the second dummy pattern52amay remain on the second sacrificial pattern42ain the second area B of the substrate10.

Otherwise, the process conditions of the anisotropic etching process may be intentionally controlled in such a manner that the second dummy mask pattern52amay remain on the second sacrificial pattern42a.

While the present example embodiment discloses that the spacer layer70and the dummy mask pattern50amay be removed in-situ with each other by the same anisotropic etching process, the spacer layer70and the dummy mask pattern50amay be individually removed from the substrate10by a respective etching process.

Referring toFIG. 1E, the first sacrificial pattern41amay be removed from the first area A of the substrate10. The second dummy mask pattern52aand the second spacer72may make contact with each other and thus the second sacrificial pattern42amay be sufficiently covered with the second dummy mask pattern52aand the second spacer72. Therefore, the first sacrificial pattern41amay be removed from the first area A of the substrate10by a removal process and the second sacrificial pattern42amay be protected from the same removal process by the second dummy mask pattern52aand the second spacer72. That is, the first sacrificial pattern41ais removed from the substrate while the second sacrificial pattern42amay still remain in the second area B of the substrate10.

As a result, the first spacer71amay merely remain on the hard mask layer30in the first area A of the substrate10while the second sacrificial pattern42a, the second dummy mask pattern52aand the second spacer72may remain on the hard mask layer30in the second area B of the substrate10.

For example, the removal process for removing the first sacrificial pattern41amay include a strip process, an ashing process and an etching process. A dry etching process or a wet etching may be used for removing the first sacrificial pattern41a.

Referring toFIG. 1F, a hard mask pattern30amay be formed on the insulation layer20. The hard mask pattern30amay include a first hard mask pattern31ain the first area A of the substrate10and a second hard mask pattern32ain the second area B of the substrate10.

The hard mask layer30in the first area A may be removed from the insulation layer20by an etching process using the first spacer71as an etching mask and the hard mask layer30in the second area B may be removed from the insulation layer20by an etching process using the second spacer72as an etching mask. Thus, the first hard mask pattern31amay have a line width that is relatively smaller than that of the second hard mask pattern32aand the second hard mask pattern32amay have a line width that is relatively larger than that of the first hard mask pattern31a. The second dummy mask pattern52amay be removed from the second sacrificial pattern42ain the etching process for forming the second hard mask pattern32ain the second area B of the substrate10.

Therefore, the first hard mask pattern31ahaving a relatively small line width may be formed on the insulation layer20in the first area A of the substrate10by the three dimensional etching process using the first spacer71as an etching mask, while the second hard mask pattern32ahaving a relatively large line width may be formed on the insulation layer20in the second area B of the substrate10by a normal etching process using the second spacer72. In such a case, the three dimensional etching process and the normal etching process may be simultaneously performed just merely in the same photolithography process although the first and the second hard mask patterns31aand32amay have different line widths.

Referring toFIG. 1G, the insulation layer20may be patterned into an insulation pattern20aby a damascene process using the hard mask pattern30aas an etching mask.

The insulation layer20in the first area A of the substrate10may be patterned into a first insulation pattern21aby a damascene process using the first hard mask pattern31aas an etching mask, thereby forming a first trench25through which the substrate10in the first area A may be partially exposed. Further, the insulation layer20in the second area B of the substrate10may be patterned into a second insulation pattern22aby a damascene process using the second hard mask pattern32aas an etching mask, thereby forming a second trench26through which the substrate10in the second area B may be partially exposed.

In the present example embodiment, the first insulation pattern21amay include a cell lower insulation pattern1A, a cell etch stop pattern2A and a cell upper insulation pattern3A, and the second insulation pattern22amay include a peripheral/core lower insulation pattern1B, a peripheral/core etch stop pattern2B and a peripheral/core upper insulation pattern3B.

Therefore, the insulation pattern20amay also be formed into a double damascene pattern in which the first and the second trenches25and26may have different widths at upper and lower portions thereof, respectively.

Thus, various conductive structures on the substrate10may be exposed through the first and the second trenches25and26in the insulation pattern20a. For example, a common source line (CSL) and cell drain regions of a flash memory device and a gate electrode and source/drain regions of the gate electrode for a transistor in a peripheral circuit may be simultaneously exposed through the first and the second trenches25and26.

The present embodiment exemplarily discloses the cell and the peripheral/core areas as the first and the second areas, respectively, in which two kinds of the wiring structures having different pattern sizes are positioned at each areas and contrasted with each other. However, any other pairs of areas of the substrate may also be used as the first and the second areas as long as the pattern sizes of each area are contrasted with each other, as would be known to one of the ordinary skill in the art. For example, a wiring separation pattern may be positioned in the cell area of a flash memory device so as to effectively separate various wiring structures from one another, and the width of the wiring separation pattern may be quite larger than that of a bit line of the flash memory device. In such a case, the bit line area of the substrate in which a plurality of the bit lines having a relatively larger width is arranged may be used as the first area A and the separation pattern area of the substrate in which the wiring separation pattern having a relatively smaller width is arranged may be used as the second area B.

Referring toFIG. 1H, the first and the second trenches25and26may be filled with conductive materials, to thereby form the wiring structures80aof the semiconductor device.

In an example embodiment, the conductive materials may be deposited onto the substrate10including the first and the second trenches25and26to a sufficient thickness to fill up the first and second trenches25and26, thereby forming a conductive layer (not shown) on the hard mask pattern30afilling up the first and second trenches25and26. Then, the conductive layer and the hard mask pattern30amay be removed from the insulation pattern20aby a planarization process, and thus the conductive layer may remain merely in the first and the second trenches25and26to thereby form a conductive pattern80aon the substrate10. The conductive pattern80amay function as the wiring structures of the semiconductor device.

For example, a first conductive pattern81ain the first trench25at the first area A, which may be referred to as first wiring structure, may include a bit line electrically connected to a CSL of a flash memory device and a cell metal wring applying various signals to each transistor in a cell area of the semiconductor device. In addition, a second conductive pattern82ain the second trench26at the second area B, which may be referred to as second wiring structure, may include a peripheral circuit wiring arranged in the peripheral/core area of the flash memory device and applying driving signals to peripheral circuits for driving transistors in the cell areas of the flash memory device.

In such a case, the first conductive pattern81amay be arranged at the first area of the substrate10in such a manner that the line width of each line of the first conductive pattern81amay be substantially the same as that of the first mask pattern61aand the neighboring lines of the first conductive pattern81amay be spaced apart from each other by a gap distance corresponding to the width of the first spacer71. Thus, the distribution density of the first wiring structure in the first area A may be controlled by the width of the first spacer71and the pitch of the first mask pattern61a.

FIG. 2is a view illustrating the distribution density of the first wiring structure according to the width of the first spacer in the first area of the substrate.

Referring toFIG. 2, when the first mask pattern61amay have a mask width W1and a mask pitch Pm in the first area A, the gap distance between neighboring lines of the first sacrificial pattern41amay be set to be Pm-W1. A pair of the first spacers71may be positioned between the neighboring lines of the first sacrificial pattern41aand thus the spacer width W2of the first spacer71may be set to be (Pm-W1)/2. Therefore, the gap distance between the neighboring first wiring structures81amay be controlled by variation of the spacer width W2of the first spacer71thereby controlling the distribution density of the first wiring structure in the pitch of the first mask pattern61a.

For example, when the mask pitch Pm of the first mask pattern61ais set to be about three times a pitch P of the first wiring structure and the spacer width W2of the first spacer71is set to be about 0.5 times the pitch P of the first wiring structure, a pair of the first wiring structures are arranged in the mask pitch Pm of the first mask pattern61awith being spaced apart by a gap distance P/2. Therefore, the distribution density of the first wiring structure may be doubled in the first area A of the substrate10.

According to the present example embodiment of forming the wiring structure for a semiconductor device, at least two kinds of patterns having different line width may be formed in the first and the second areas of the substrate, respectively, by a consecutive photolithography process using a single mask pattern, thereby remarkably improving a process efficiency for manufacturing the semiconductor device. In addition, the distribution density of the wiring structure in the semiconductor device may be easily controlled by variation of the width of the spacer pattern.

Non-volatile Memory Device and Method of Manufacturing the Same

FIG. 3is a plan view illustrating a flash memory device in accordance with an example embodiment of the present inventive concept.FIGS. 4A and 4Bare cross-sectional views cut along a line I-I′ and a line II-II′ of the flash memory device illustrated inFIG. 3, respectively.

Referring toFIGS. 3,4A and4B, a flash memory device900may include a semiconductor substrate100that may be divided into an active region Ar and a field region by an insulation layer103. The active region Ar may be defined by the insulation layer103and various conductive structures may be formed in the active region of the substrate100. Thus, the conductive structures in the neighboring active regions Ar may be electrically isolated from each other by the insulation layer103and may function just like independent electronic devices irrespective of the neighboring active regions Ar.

For those reasons, the insulation layer103may be sometimes called as a device isolation layer. In the present example embodiment, the active regions Ar may be defined to be a plurality of lines extending along a first direction on the substrate100.

First, second and third gate patterns120a,120band120cmay extend along a second direction substantially perpendicular to the first direction on the substrate100. Thus, the first, second and third gate patterns120a,120band120cmay extend across the active region Ar and the field region of the substrate100. In the present example embodiment, the first gate pattern120amay include a single conductive line functioning as a string selection line (SSL) of the flash memory device and the second gate pattern120bmay include a single conductive line functioning as a ground selection line (GSL) of the flash memory device. The third gate pattern120cmay include a plurality of conductive lines interposed between the SSL and the GSL and may function as word lines WL of the flash memory device.

A string selection transistor (SST) may be arranged at a crossing point of the first gate pattern120aand the active region Ar of the substrate100and a ground selection transistor (GST) may be arranged at a crossing point of the second gate pattern120band the active region Ar of the substrate100. A plurality of cell transistors (CT) may be positioned at each crossing point of the third gate pattern120cand the active region Ar of the substrate100. Each of the SST, GST and the CTs may include a gate oxide layer (not shown), a floating gate105, a gate dielectric layer107and a control gate109.

A capping layer111may be further positioned on each of the gate patterns120a,120band120cand a spacer125may be positioned on sidewalls of the gate patterns120a,120band120c. The capping layer111may include a silicon nitride layer and the spacer125may include any one of a silicon nitride layer, silicon oxide layer and a stacked multilayer thereof.

Source and drain regions (not shown) may be arranged at both side portions of each transistor of the SST, GST and CTs that are arranged on the active regions Ar of the first, second and third gate patterns120a,120band120c, respectively, along the first direction. A plurality of the memory cell arrays may be arranged at the crossing points of the active regions extending in the first direction and the word lines extending in the second direction. The SSL and the GSL may be arranged at the active region Ar off from a 1stword line120c1and an nthword line120cn. Thus, the SSL, the GSL and the WLs interposed between the SSL and the GSL may function as a unit memory block of the flash memory device, which may be called as “string” sometimes. In the string of the flash memory device, a plurality of the cell transistors, which may be arranged on the active region Ar of the third gate pattern120carranged in the first direction, may extend in series and share the source/drain regions.

An insulation layer130may be provided with the flash memory device and thus the first to third gate patterns120a,120band120cmay be electrically insulated from one another and from metal wirings over the gate patterns120ato120c.

For example, the insulation layer130may include a protection layer130aand a flat layer130b. The protection layer130amay be formed on the substrate100including the first to third gate patterns120ato120calong a surface profile thereof and thus a gap space may be provided between the neighboring gate patterns120ato120c. Therefore, the protection layer130amay include a material having good gap-fill characteristics. The gate patterns120ato120cmay be protected from a subsequent etching process by the protection layer130a. The gap space between the neighboring gate patterns may be filled up with the flat layer130bof which an upper portion may be planarized.

The insulation layer130may include a first contact hole132and a second contact hole136. Each active region Ar and the device isolation layer103interposed between the neighboring GSLs may be exposed through the first contact hole132and each active region Ar interposed between the neighboring SSTs may be exposed through the second contact hole136. The first contact hole132may be filled up with conductive materials such as polysilicon, and thus the common source line CSL134may extend along the GSL. Therefore, the active region Ar and the device isolation layer130exposed through the first contact hole132may make common contact with the GSL. An upper surface of the CSL and an upper surface of the insulation layer130may be coplanar with each other.

A first insulation interlayer pattern140ahaving first and second via holes142and146may be positioned on the insulation layer130and the CSL134and thus the contact plugs144may be electrically insulated from one another by the first insulation interlayer pattern140a. The first via hole142may expose and open into the second contact hole136and the CSL may be exposed through the second via hole146. Conductive materials may be filled into the second contact hole136and the first via hole142, and the contact plug144may be positioned in the second contact hole136and the first via hole142. Thus, the contact plug144may make contact with each active region between the SSTs. A low-resistive metal may be filled into the second via hole146, and a cell metal wiring174may be positioned in the second via hole146. The cell metal wiring174may make contact with the CSL134between the GSLs.

For example, the contact plug144may include a polysilicon layer, a metal layer comprising tungsten (W) and aluminum (Al) and a multi-layer having the polysilicon layer and the metal layer. An upper surface of the contact plug144may be coplanar with an upper surface of the first insulation interlayer pattern140a.

Since the contact plug144may be positioned adjacent to the SST at each of the active regions extending along the first direction, a number of the contact plugs144may be aligned in series along the second direction and thus a contact plug line PL may be positioned in parallel with the SSL. A first string S1including the SSL120a, the GSL120band the word lines120cinterposed between the SSL120aand GSL120bmay be arranged symmetrical to a second string S2including another SSL, GSL and WLs (not shown) with respect to the PL. Thus, the first and the second strings S1and S2may be a mirror image to each other with respect to the PL. That is, a single contact plug144may be formed between the neighboring SST in each of the active regions Ar and a pair of the SSTs adjacent to each other in the same active region may be connected to a same or common single contact plug144.

The CSL may be positioned in parallel with the GSL. Particularly, a third string may be arranged symmetrically to the first string S1with respect to the CSL134, and thus the first and the third strings S1and S3may be an mirror image to each other with respect to the CSL134. The GSTs on the GSL may be connected to a same or common CSL.

Thus, the contact plug144may be commonly connected to the drain electrodes of the SSTs of the first and second strings S1and S2and the CSL may be commonly connected to the source electrodes of the GSTs of the first and third strings S1and S3.

An etch stop layer150may be positioned on the contact plug144and the first insulation interlayer pattern140aand a second insulation interlayer pattern160amay be positioned on the etch stop layer150. The etch stop layer150may terminate an etching process for forming the second insulation interlayer pattern160a, for example, a damascene pattern.

The second insulation interlayer pattern160amay include a first trench162through which the etch stop layer150on the contact plug144may be exposed and a second trench164through which the etch stop layer150over the device isolation layer103may be exposed.

A first conductive metal may be filled into the first trench162to thereby form a bit line172making contact with the contact plug144and a second conductive metal may be filled into the second trench164to thereby form a cell metal wiring174making contact with the CSL. The first conductive metal may be substantially the same as the second conductive metal and the bit line172may be formed simultaneously with the cell metal wiring174in a single process.

The bit line172may have a width larger than that of the first via hole142and may extend along the first direction over the active region Ar and the cell metal wiring174may have a width larger than that of the second via hole146and may extend along the first direction over the device isolation layer103. Thus, the bit line172may make contact with the contact plug144exposed through the first via hole142in the active region Ar of the substrate100and other conductive structures in the same active region Ar may be electrically insulated from the bit line172by the first insulation layer130. In addition, the cell metal wiring174may make contact with the CSL134exposed through the second via hole146and penetrating through the first insulation layer130.

Particularly, the cell metal wiring174and the bit line172may be positioned on the second insulation interlayer pattern160ain the cell area of the substrate100by a double patterning process using a single photo mask, thereby increasing the density of the metal wiring174and the bit line172in the cell area. Thus, although the critical dimension (CD) of the semiconductor device may be decreased to degree less than about 40 nm, the bit line172and the cell metal wiring174may be sufficiently arranged on the second insulation interlayer pattern160a.

According to the flash memory device of the present example embodiment, the bit line and the cell metal wiring of which the widths may be different may be arranged in the cell area of the substrate at high distribution density by a double patterning process. Particularly, the distribution density of the bit line and the metal wiring may be easily controlled by variation of the width of the spacer pattern although the CD of the flash memory device may be decreased less than about 40 nm.

Hereinafter, a method of manufacturing the flash memory device illustrated inFIGS. 3,4A and4B will be described in detail with reference toFIGS. 5A to 9B.

FIGS. 5A to 9Bare cross sectional view illustrating processing steps for a method of manufacturing a non-volatile memory device shown inFIG. 3. The following disclosed process steps are merely illustrative and exemplarily embodiments for manufacturing the flash memory device shown inFIGS. 3,4A and4B and thus are not to be construed as limiting thereof. In addition, while the present example embodiment may disclose the flash memory device as an example embodiment of semiconductor device in which the wiring structure illustrated inFIG. 1Hmay be used as a bit line, any other semiconductor devices as well as the flash memory device, for example, a dynamic random access memory (DRAM) device, may also use the wiring structure illustrated inFIG. 1Has a bit line thereof, as would be known to one of the ordinary skill in the art.

Referring toFIGS. 3,5A and5B, a substrate100having a cell array region may be prepared for manufacturing the flash memory device900. A device isolation layer103may be formed on the substrate100, thereby defining an active region Ar on which conductive structures may be formed. The active region Ar may be formed into a line shape extending in a first direction.

The conductive structures including first, second and third gate patterns120a,120band120cmay be formed on the active region Ar of the substrate100. Particularly, the first gate pattern120amay function as a string selection line (SSL) of the flash memory device900and the second gate pattern120bmay function as a ground selection line (GSL) of the flash memory device900. A plurality of the third gate pattern120cmay be interposed between the first and the second gate patterns120aand120band may function as word lines (WL) of the flash memory device900.

A string selection transistor (SST) may be formed at a crossing point of the first gate pattern120aand the active region Ar of the substrate100and a ground selection transistor (GST) may be formed at a crossing point of the second gate pattern120band the active region Ar of the substrate100. A plurality of cell transistors (CT) may be formed at each crossing point of the third gate pattern120cand the active region Ar of the substrate100. Each of the SST, GST and the CTs may include a gate oxide layer (not shown), a floating gate105, a gate dielectric layer107and a control gate109.

A capping layer111may be formed on each of the gate patterns120a,120band120c. A spacer125may be further formed on sidewalls of the gate patterns120a,120band120c. A first ion implantation process may be performed onto the substrate100using the gate patterns as an ion implantation mask, thereby forming a lightly doped impurity region at surface portions of the substrate100. Then, a second ion implantation process may be performed onto the substrate100using the gate patterns and the spacers as an ion implantation mask, thereby forming a heavily doped impurity region at surface portions of the substrate100.

Then, an insulation layer130may be formed on a whole surface of the substrate100including the gate patterns and the impurity regions. For example, a plasma oxide or an undoped silicate glass may be deposited onto the substrate100including the gate patterns120a,120band120calong a surface profile, thereby forming a protection layer130aon the substrate100. Thus, the protection layer130amay include a gap space between the neighboring SSTs and the neighboring GSTs. Then, a tetra ethyl orthosilicate (TEOS) may be deposited onto the protection layer130ato a sufficient thickness to fill up the gap space by a plasma-enhanced chemical vapor deposition (PECVD) process, thereby forming a Plasma-Enhanced TetraEthylOrthoSilicate (PETEOS) layer on the protection layer130a. Then, an upper portion of the PETEOS layer may be planarized by a planarization process such as a CMP process, thereby forming a flat layer130bon the protection layer130a. Thus, the insulation layer130may include the protection layer130aand the flat layer130band the gate patterns120a,120band120cmay be electrically insulated from one another by the insulation layer130and be covered with the insulation layer130.

Then, the first insulation layer130may be partially removed from the substrate100by a first etching process, thereby forming a first contact hole132through which the active regions Ar between the neighboring GSTs and the device isolation layer103between the active regions Ar may be exposed. That is, the first contact hole132may extend in a second direction vertical to the active region in parallel with the GSL and thus the active regions Ar and the device isolation layers103between the neighboring active regions Ar may be exposed through the first contact hole132in the second direction. An implantation area may be formed on the active region Ar exposed through the first contact hole132by an ion implantation process and a cell source region and a series of the implantation areas may form a conductive line that may be in parallel with the GSL.

A first conductive layer may be formed on the insulation layer130to a sufficient thickness to fill up the first contact hole132and then may be partially removed from the insulation layer130by a planarization process such as a CMP process and an etch-back process until an upper surface of the insulation layer130may be exposed, thereby forming a common source line134in the first contact hole132. Thus, an upper surface of the CSL134may be coplanar with the upper surface of the insulation layer130. For example, the first conductive layer may comprise doped polysilicon.

Referring toFIGS. 3,6A and6B, a first insulation interlayer140may be formed on the insulation layer130to a sufficient thickness to cover the CSL134. The first insulation interlayer140may electrically insulate the CSL134from a contact plug that is to be formed hereinafter.

Then, the first insulation interlayer140and the insulation layer130under the first insulation interlayer140may be sequentially etched off from the substrate100by a second etching process, thereby forming a first via hole142in the first insulation interlayer140and a second contact hole136in the insulation layer130. The first via hole142and the second contact hole136may be communicated with each other and the active region Ar between the neighboring SSLs may be exposed through the first via hole142and the second contact hole136. Hereinafter, the insulation interlayer140including the first via hole142may be refereed to as first insulation interlayer pattern and be denoted as reference numeral140a.

A second conductive layer (not shown) may be formed on the first insulation interlayer pattern140ato a sufficient thickness to fill up the second contact hole136and the first via hole142and then may be partially removed from the first insulation interlayer pattern140aby a planarization process until an upper surface of the first insulation interlayer pattern140a, thereby forming a contact plug144in the second contact hole136and the first via hole142. Thus, an upper surface of the contact plug144may be coplanar with the upper surface of the first insulation interlayer pattern140a.

In the present example embodiment, the second conductive layer may include a polysilicon layer, a metal layer comprising tungsten (W) and aluminum (Al) and a multi-layer having the polysilicon layer and the metal layer. Particularly, when the second conductive layer may include the tungsten layer, a barrier layer (not shown) may be further formed between the tungsten layer and the first insulation interlayer pattern140aand between the tungsten layer and the substrate100, thereby reducing a contact resistance between the contact plug144and the substrate100and preventing the diffusion of the source gases into the first insulation interlayer pattern140ain a tungsten deposition process. For example, the barrier layer may comprise titanium (Ti) and/or titanium nitride (TiN).

Referring toFIGS. 3,7A and7B, an etch stop layer150may be formed on the first insulation interlayer pattern140ato cover the contact plug144. The etch stop layer150may have an etch selectivity with respect to a second insulation pattern160athat is to be formed in a subsequent process.

Referring toFIGS. 3,8A and8B, a second insulation interlayer may be formed on the etch stop layer150and then may be partially etched off from the etch stop layer150, thereby forming the second insulation interlayer pattern160aincluding a first trench162and a second trench164. The contact plug144may be exposed through the first trench162and the CSL134may be exposed through the second trench164.

For example, the second insulation interlayer may comprise an oxide like the first insulation interlayer140. Examples of the oxide may include boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), fluorinated silicate glass (FSG), tetra ethyl orthosilicate deposited by plasma enhanced CVD (PE-TEOS) and undoped silicate glass (USG), etc. These may be used alone or in combinations thereof. In the present example embodiment, both of the first and the second insulation interlayer may include a PETEOS layer. For example, the PECVD process may be performed on the etch stop layer150using tetra etoxy silane (Si(OC2H5)4) gases and oxygen (O2) or ozone (O3) gases as the source gases, thereby forming the PETEOS layer on the etch stop layer150as the second insulation interlayer. Otherwise, the second insulation interlayer may be different from the first insulation interlayer140, as would be known to one of the ordinary skill in the art.

The second insulation interlayer may be additionally removed from the etch stop layer150in a subsequent etching process for forming the first and the second trenches and a subsequent planarization process for forming the cell metal wiring, and thus the second insulation interlayer may be formed to a sufficient thickness to compensate for the additional loss in the above subsequent etching process and the planarization process.

For example, the second insulation interlayer and the etch stop layer150may be partially etched off by a single damascene process, thereby forming the first and the second trenches162and164.

Particularly, a hard mask pattern31ainFIG. 1Gmay be formed on the second insulation interlayer by the double patterning process using a single mask pattern that may be described in detail with reference toFIGS. 1A to 1G, and then a single damascene process may be performed onto the second insulation interlayer using the hard mask pattern31aas an etching mask. Accordingly, the second insulation interlayer and the etch stop layer150may be patterned to have the first trench162through which the contact plug144may be exposed and the second trench164through which the CSL134may be exposed. In such a case, the first and the second trenches162and164may have a width larger than that of the first and the second via holes142and146, respectively. Thus, the contact plug144may make sufficient contact with a bit line and the CSL134may make sufficient contact with a cell metal wiring.

A peripheral trench (not shown) may be formed in the second insulation layer simultaneously with the first and second trenches162and164by the same damascene process. A peripheral wiring structure through which a driving signal may be transferred to the cell metal wiring may be formed in the peripheral trench on a peripheral region of the substrate100. Thus, various trenches for the peripheral wiring structure, the bit line and the cell metal wiring, which may have respective widths different from one another, may be simultaneously in the same double patterning process using a single mask pattern, thereby remarkably increasing process efficiency of the flash memory device.

Particularly, various patterns having different widths may be simultaneously formed at different regions of the substrate100by a single patterning process, and thus process failures caused by misalignment of the patterns may be significantly reduced as compared with the conventional patterns that have been formed individually by a respective patterning process. For example, when a plurality of bit lines may be formed in a cell region of a NAND flash memory device, the NAND flash memory device may need a wiring separation pattern for node separation of the bit lines in the cell region. Since the wiring separation pattern may have a line width much larger than that of the bit line, the bit lines and each line of the wiring separation pattern is likely to be misaligned with each other in case that the bit lines and the wiring separation pattern may be individually formed by a respective patterning process. In such a case, the node separation of the bit lines may be insufficient and thus a wiring failure such as electric short between neighboring bit lines may be found in the flash memory device. However, according to the present example embodiment, the bit line and the wiring separation pattern may be formed in the cell region simultaneously with each other by the same patterning process using a single singe mask pattern, thereby sufficiently preventing the wiring failures caused by the misalignment of the bit line and the wiring separation pattern.

Referring toFIGS. 3,9A and9B, the bit line172and the cell metal wiring174may be formed in the first and second trenches162and164, respectively.

For example, conductive materials may be deposited onto the second insulation interlayer pattern160aincluding the first and the second trenches162and164to a sufficient thickness to fill up the first and the second trenches162and164, thereby forming a third conductive layer (not shown) on the second insulation interlayer pattern160a. The third conductive layer may comprise a metal having a good electric conductivity such as copper (Cu), tungsten (W) and aluminum (Al). In the present example embodiment, the third conductive layer may comprise copper (Cu).

A planarization process such as a CMP process and an etch-back process may be performed against the third conductive layer until an upper surface of the second insulation interlayer pattern160amay be exposed, and thus an upper portion of the third conductive layer may be removed from the second insulation interlayer pattern160aand merely remain in the first and second trenches162and164, thereby forming the conductive line170of the flash memory device900. The conductive line170may include a bit line172making contact with the contact plug144and extending in the first direction over the active region Ar and a cell metal wiring174making contact with the CSL134and extending in the first direction over the device isolation layer103. Since the contact plug144and the CSL134may be electrically insulated from each other by the first insulation interlayer pattern140a, the bit line172and the CSL134may also be electrically insulated from each other.

According to the exemplarily method of manufacturing the flash memory device, various patterns having different widths may be formed simultaneously with each other by the same double patterning process using a single mask pattern, thereby preventing wiring failures caused by the misalignment between the patterns and improving process efficiency. Particularly, when the pattern in the cell region of the substrate needs to be much finer according to the recent CD reduction, the reduced gap space and line width of the fine pattern in the cell region may be easily and accurately controlled merely by variation of the width of the spacer pattern in the double patterning process, thereby increasing the distribution density of the wiring structure in the cell region of the flash memory device.

According to the example embodiments of the present inventive concept, at least two kinds of patterns having different line width may be formed in different areas of the substrate, respectively, by a double patterning process using a single mask pattern, thereby preventing the misalignment of the patterns and improving a process efficiency for manufacturing the semiconductor device. Particularly, the bit lines and the peripheral metal wirings of a flash memory device may be formed simultaneously with each other by a double patterning process using a single photolithography process. In addition, a bit line pattern and a wiring separation pattern may be formed simultaneously in the same double patterning process, thereby preventing the wiring failures caused by misalignments of the bit line pattern and the wiring separation pattern.

A memory system including the flash memory device of the present example embodiment may be applied in various electronic equipment. For example, the memory system including the flash memory device according to some embodiments may be applied to a personal digital assistant (PDA), a personal computer system, a wireless telephone, a mobile phone such as a cellular phone and a smart phone, a digital music player, a memory card, and/or various other devices.