Semiconductor packages

A semiconductor package includes a semiconductor die and an encapsulant layer. A mark is formed on a surface of the encapsulant layer. A damage barrier layer is disposed between the mark and the semiconductor die. The damage barrier layer blocks the propagation of laser light used to form the mark from reaching the semiconductor die.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2021-0106356, filed on Aug. 11, 2021, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor package technology, and more particularly, to a semiconductor package including a mark.

2. Related Art

A semiconductor package may include a semiconductor die, a packaging substrate, and an encapsulant layer. Integrated circuits (ICs) may be integrated into the semiconductor die. The semiconductor die may be mounted on the packaging substrate. The encapsulant layer may be formed over the packaging substrate to protect the semiconductor die.

Semiconductor packages capable of implementing high density and high performance may be required. Attempts have been made to embed a plurality of semiconductor dies in a semiconductor package structure. Stack packages or multi-chip packages has been proposed. Semiconductor packages suitable for mobile devices may be required. Semiconductor packages may be required to have a smaller form factor. Semiconductor packages may be required to have a thinner thickness.

The semiconductor packages may include marks formed on a surface of the encapsulant layer. The mark may indicate information about the semiconductor package, such as identity information or manufacturing information of the semiconductor package.

SUMMARY

In accordance with an embodiment of the present disclosure is a semiconductor package including a semiconductor die, an encapsulant layer covering the semiconductor die, a mark formed on a surface of the encapsulant layer, and a damage barrier layer disposed between the mark and the semiconductor die.

In accordance with another embodiment of the present disclosure is a semiconductor package including a packaging substrate, a plurality of semiconductor dies stacked on the packaging substrate, a damage barrier layer attached to an upper surface of an uppermost semiconductor die of the plurality of semiconductor dies, an encapsulant layer covering the plurality of semiconductor dies and the damage barrier layer, and a mark formed on a portion of the encapsulant layer overlapping the damage barrier layer.

DETAILED DESCRIPTION

The terms used in the description of example embodiments of the present disclosure are terms selected in consideration of their functions, and the meaning of the terms may vary according to the intention or custom of users or operators in the technical field. The meanings of the terms used are in accordance with the defined definitions when specifically defined in the present disclosure. If no specific definition is provided for a term, the term may be interpreted as having the meaning generally recognized by those skilled in the art.

In the description of the embodiments of the present disclosure, descriptions such as “first,” “second,” “side,” “top,” and “bottom or lower” are to distinguish subsidiary materials, not used to limit the subsidiary materials themselves or to imply any particular order.

A semiconductor device may include a semiconductor substrate or a structure in which plurality of semiconductor substrates are stacked. The semiconductor device may indicate a semiconductor package structure in which a structure in which semiconductor substrates are stacked is packaged. Semiconductor substrates may refer to semiconductor wafers, semiconductor dies, or semiconductor chips on which electronic components and elements are integrated. A semiconductor chip may refer to a memory chip in which a memory integrated circuit including DRAM, SRAM, NAND FLASH, NOR FLASH, MRAM, ReRAM, FeRAM, or PcRAM is integrated, or a logic die in which a logic circuit is integrated on a semiconductor substrate or a processor such as an ASIC chip, an application processor (AP), a graphic processing unit (GPU), a central processing unit (CPU), or a system on a chip (SoC). The semiconductor device may be applied to information communication devices such as portable terminals, bio or health care related electronic devices, and wearable electronic devices. The semiconductor device may be applied to the Internet of Things.

The same reference numerals may refer to the same elements throughout the present disclosure. The same reference numerals or similar reference numerals may be described with reference to other drawings, even if they are not mentioned or described in the corresponding drawings. Further, even if a reference numeral is not indicated, it may be described with reference to other drawings.

FIG.1is a schematic cross-sectional view illustrating a semiconductor package10according to an embodiment of the present disclosure.

Referring toFIG.1, a semiconductor package10may include semiconductor dies200, an encapsulant layer600, a mark700, and a damage barrier layer500. The semiconductor package10may include a packaging substrate100, a first semiconductor die220, a second semiconductor die210, the encapsulant layer600, the mark700, and the damage barrier layer500. The semiconductor package10may further include a third semiconductor die230and a fourth semiconductor die240. The semiconductor package10may further include a first bonding wire410and a second bonding wire430. The packaging substrate100may further include outer connectors800.

The semiconductor die200may include a device in which integrated circuits (ICs) are integrated. The semiconductor die200may include a semiconductor device in which memory devices such as DRAM devices or NAND devices are integrated. The semiconductor package10may include a stack package structure in which a plurality of semiconductor dies200are stacked substantially vertically. Another semiconductor die or a plurality of semiconductor dies may be further disposed between the packaging substrate100and the stack of the semiconductor dies200.

The fourth semiconductor die240may be disposed on the packaging substrate100, and the third semiconductor die230may be stacked on the fourth semiconductor die240. The third semiconductor die230may be stacked on the fourth semiconductor die240while exposing a portion of the fourth semiconductor die240. The third semiconductor die230may be disposed while being offset by a distance from a location where the fourth semiconductor die240is disposed. The third semiconductor die230may be offset stacked on the fourth semiconductor die240while partially overlapping with the fourth semiconductor die240.

The first semiconductor die220may be offset stacked on the third semiconductor die230. The second semiconductor die210may be offset stacked on the first semiconductor die220. The second semiconductor die210may be an uppermost die positioned at the uppermost layer in the stack of the semiconductor dies200. The second semiconductor die210may be offset stacked on the first semiconductor die220in a direction opposite to a direction in which the first semiconductor die220is offset stacked on the third semiconductor die230.

The fourth semiconductor die240may be attached to the packaging substrate100by an adhesive layer300. Other adhesive layers300may be disposed between the semiconductor dies200to adhere the semiconductor dies200to each other.

The semiconductor dies200may be electrically connected to the packaging substrate100by inner connectors such as the first and second bonding wires410and430. The first bonding wire410may electrically connect the second semiconductor die210to the packaging substrate100. The first bonding wire410may be connected to the second semiconductor die210and may further extend to be connected to the packaging substrate100. One end410E of the first bonding wire410may be bonded or connected to a portion of an upper surface210S of the second semiconductor die210.

The first bonding wire410may extend to interconnect the second semiconductor die210and the first semiconductor die220. The first bonding wire410may connect the second semiconductor die210and the first semiconductor die220to the packaging substrate100. The second bonding wire430may further extend to connect the third semiconductor die230to the fourth semiconductor die240, and to connect the third semiconductor die230and the fourth semiconductor die240to the packaging substrate100. The second bonding wire430and the first bonding wire410may be positioned at opposite positions with the semiconductor dies200therebetween.

The semiconductor die200or the semiconductor dies200may be disposed over the packaging substrate100. The packaging substrate100may be an interconnection component that electrically connects the semiconductor dies200to an external device, an external module, or external components. The packaging substrate100may be configured in the form of a printed circuit board (PCB). The packaging substrate100may be configured in a redistribution layer (RDL) structure. The redistribution layer structure may include a dielectric layer and conductive patterns disposed in the dielectric layer. The outer connectors800may include solder balls or conductive bumps.

The encapsulant layer600may be formed as a layer that covers and seals the semiconductor dies200on the packaging substrate100. The encapsulant layer600may be formed on the packaging substrate100to cover the first semiconductor die220, the second semiconductor die210, and the damage barrier layer500. The encapsulant layer600may include various encapsulation materials. The encapsulant layer600may include an epoxy molding compound (EMC). The encapsulant layer600may be formed by a molding process of molding EMC to cover the semiconductor dies200on the packaging substrate100.

FIG.2is a schematic plan view illustrating an example of a mark700formed in the semiconductor package10ofFIG.1.

Referring toFIGS.2and1, the mark700may be formed on an upper surface600S of the encapsulant layer600. A marking region607of the encapsulant layer600may be a region including a portion of the upper surface600S of the encapsulant layer600. The marking region607of the encapsulant layer600may overlap with the packaging substrate100and the semiconductor dies200. The mark700may be formed in a portion of the marking area607of the encapsulant layer600. The mark700may include alphanumeric characters or other symbols that convey information. The mark700may be formed as a mark providing recognition information of the semiconductor package (10ofFIG.1). The mark700may indicate information including a run number, a manufacturing identifying number, data of manufacture, or a combination thereof. The mark700may be formed on the upper surface600S of the encapsulant layer600by a laser marking process. The mark700may be engraved on the upper surface600S of the encapsulant layer600in a groove shape or an opening shape.

FIG.3is an enlarged schematic cross-sectional view illustrating a portion of the semiconductor package10ofFIG.1including the damage barrier layer500and the second semiconductor die210.

Referring toFIGS.3and1, the damage barrier layer500may be disposed between the mark700and the semiconductor die200of the semiconductor package10. The damage barrier layer500may be attached to the upper surface210S of the second semiconductor die210. The damage barrier layer500may be limitedly attached to only a portion of the upper surface210S of the second semiconductor die210. The mark700may be formed in the marking region607of the encapsulant layer600, as illustrated inFIG.3, and the marking region607may be overlapped with the damage barrier layer500. The damage barrier layer500may be attached to the second semiconductor die210to cover a portion of the second semiconductor die210. The portion of the second semiconductor die210to which the damage barrier layer500is attached may overlap with the mark700. The damage barrier layer500may be attached to the upper surface210S of the second semiconductor die210, but might not overlap with the first bonding wire410and may be disposed at a position spaced apart from the first bonding wire410while exposing the first bonding wire410.

In the laser marking process of forming the mark700, the damage barrier layer500may substantially prevent or limit damage to the underlying second semiconductor die210. The damage barrier layer500may protect or shield the second semiconductor die210from the laser marking process. The damage barrier layer500may substantially block or attenuate the propagation of laser light used in the laser marking process to the second semiconductor die210. The damage barrier layer500may include a layer that reflects laser light. The damage barrier layer500may include a layer that absorbs or scatters laser light. It is possible to form the mark700on the upper surface600S of the encapsulant layer600by the laser marking process while preventing or mitigating damage to the second semiconductor die210by using the damage barrier layer500.

The second semiconductor die210may be disposed in the semiconductor package10such that the upper surface210S of the second semiconductor die210faces the upper surface600S of the encapsulant layer600or a portion of the upper surface210S faces the mark700. The second semiconductor die210may include a semiconductor substrate200S and a metallization structure layer200M. The metallization structure layer200M may be formed on the semiconductor substrate200S. The semiconductor substrate200S may include a semiconductor material including silicon (Si). Electronic components201may be formed in or on the semiconductor substrate200S. The electronic components201may be elements configuring an integrated circuit. The electronic components201may include active elements such as transistor devices.

The metallization structure layer200M may include a dielectric layer203, first conductive contacts204, conductive patterns205, bonding pads207, and second conductive contacts208. The conductive patterns205and the first and second conductive contacts204and208may be conductive layers providing a multilayer interconnection structure. The conductive patterns205may be electrically connected to the electronic components201through the first conductive contacts204. The dielectric layer203may be an insulating layer that insulates the conductive pattern205and the first and second conductive contacts204and208. The dielectric layer203may be formed to expose the bonding pads207.

The bonding pad207may be a connection terminal connected to an external device or other connection members. The first bonding wire410may be physically and electrically connected to the bonding pad207. One end410E of the first bonding wire410may be bonded to the bonding pad207. The second conductive contact208may electrically connect the bonding pad207to the conductive pattern205. The dielectric layer203may be a layer that provides the upper surface210S of the second semiconductor die210. The damage barrier layer500may be attached to the upper surface210S of the dielectric layer203while being spaced apart from the first bonding wire410. The dielectric layer203may include various silicon oxide (SiO2), silicon nitride (Si3N4), a low k material, or a polymer layer.

FIG.4is a schematic cross-sectional view illustrating an example of the damage barrier layer500of the semiconductor package10ofFIG.3.

Referring toFIGS.4and3, the damage barrier layer500according to an example may include a reflective layer503that reflects laser light. The reflective layer503may be composed of a layer that reflects laser light of a wavelength band used in a laser marking process. Green laser light or yttrium aluminum garnet (YAG) laser light may be used in the laser marking process. The green laser light may have a wavelength band of approximately 532 nm, and the YAG laser light may have a wavelength band of approximately 1064 nm. The reflective layer503may include a metal layer that reflects laser light in these wavelength bands.

The metal layer that may be used as the reflective layer503may include copper, brass, bronze, aluminum, gold, or silver. The metal layer that may be used as the reflective layer503may include an alloy including copper, brass, bronze, aluminum, gold, or silver. The metal layer used as the reflective layer503may include metals of different components depending on the wavelength of the laser light used in the laser marking process.

The damage barrier layer500may further include a support layer501. The support layer501may be a member that supports the reflective layer503. A metal layer may be deposited as the reflective layer503on a first surface501T of the support layer501. The metal layer may be laminated in a form of a film as the reflective layer503on the first surface501T of the support layer501. The support layer501may include a resin or a polymer. The support layer501may constitute a body or a core of the damage barrier layer500. The damage barrier layer500may further include an adhesive layer502. The adhesive layer502may be formed on a second surface501B of the support layer501. The adhesive layer502may be formed by coating an adhesive to the second surface501B of the support layer501. The adhesive layer502may be a member that bonds the damage barrier layer500or the support layer501to the upper surface210S of the second semiconductor die210.

FIG.5is a schematic cross-sectional view illustrating another example of the damage barrier layer500of the semiconductor package10ofFIG.3.

Referring toFIGS.5and3, a damage barrier layer500A according to another example may include a plurality of sub-metal layers2513and2533. The plurality of sub-metal layers2513and2533may constitute a reflective layer2503. The first sub-metal layer2513may be formed on a first surface2501T of the support layer2501. The second sub-metal layer2533may be deposited or laminated on the first sub-metal layer2513. The first sub-metal layer2513or the second sub-metal layer2533may include copper, brass, bronze, aluminum, gold, or silver. The first sub-metal layer2513and the second sub-metal layer2533may be formed of layers of different metals. The plurality of sub-metal layers2513and2533may improve the efficiency of reflecting the incident laser light.

An intermediate layer2523may be formed between the first sub-metal layer2513and the second sub-metal layer2533. The intermediate layer2523may include an adhesive layer for bonding the second sub-metal layer2533to the first sub-metal layer2513. The intermediate layer2523may include a layer of a dielectric material or may include a resin layer or a polymer layer. The intermediate layer2523may be formed as a third sub-metal layer. The third sub-metal layer may include a metal layer different from that of the first sub-metal layer2513or the second sub-metal layer2533.

A coating layer2543may be formed on the second sub-metal layer2533. The coating layer2543may include an anti-reflective material such as silicon oxynitride (SiON) or a dielectric material. The coating layer2543may be a member that reduces diffuse reflection of the light reflected by the reflective layer2503. The diffuse reflection of the laser light may cause undesired damage to the encapsulant layer (600inFIG.3) or the mark (700inFIG.3). The coating layer2543may reduce damage that may be caused by the diffuse reflection of laser light.

FIGS.6to8are schematic cross-sectional views illustrating process steps of forming the mark700on the semiconductor package10ofFIG.1.

Referring toFIG.6, the encapsulant layer600of the semiconductor package10may be molded. After forming the encapsulant layer600, a laser marking process may be performed on the marking region607of the encapsulant layer600. Referring toFIG.7, a laser irradiator900for laser marking may be introduced over the upper surface600S of the encapsulant layer600. The laser irradiator900may irradiate laser light900L onto the marking region607of the encapsulant layer600to make the mark. A portion of the upper surface600S of the encapsulant layer600may be engraved by the irradiated laser light900L. Accordingly, the mark700may be formed on the upper surface600S of the encapsulant layer600. As the laser light900L is irradiated to the encapsulant layer600, an opening shape or a groove shape may be engraved in the marking region607of the encapsulant layer600.

Referring toFIG.8, a portion900A of the laser light900L may propagate undesirably deeper into the encapsulant layer600. The portion900A of the laser light900L may pass through deeper below a bottom of the opening shape constituting the mark700. If there is no damage barrier layer500, the portion900A of the laser light900L may pass through the encapsulant layer600to reach the underlying second semiconductor die210. The damage barrier layer500may serve to block the transmitted portion900A of the laser light900L. The damage barrier layer500may reflect the transmitted portion900A of the laser light900L. The reflected light900B by the damage barrier layer500may be scattered into the encapsulant layer600or may be scattered outside the semiconductor package10.

FIG.9is a schematic cross-sectional view illustrating a process step of forming a mark70on a semiconductor package10R according to a comparative example.

Referring toFIG.9, the semiconductor package10R according to the comparative example may include a semiconductor die20and an encapsulant layer60. A laser marking process of introducing a laser irradiator90over the encapsulant layer60and irradiating laser light90L onto the encapsulant layer60may be performed. The mark70may be formed on the encapsulant layer60by irradiation of the laser light90L. While the laser light90L is irradiated to the encapsulant layer60, a portion90A of the laser light90L may undesirably propagate or transmit into the encapsulant layer60.

The transmitted portion90A of the laser light90L may pass through the encapsulant layer60and reach the semiconductor die20. The portion90A of the laser light90L may be incident on the semiconductor die20and damage the semiconductor die20. The portion90A of the laser light90L may be incident on a metallization structure layer20M of the semiconductor die20and damage the metallization structure layer20M. The portion90A of the laser light90L may damage conductive patterns25constituting the metallization structure layer20M. The transmitted portion90A of the laser light90L may be irradiated to an electronic element21configured on the semiconductor substrate20S of the semiconductor die20, whereby the electronic element21may be damaged. Such damage may cause a malfunction of the semiconductor die20and damage the reliability of the semiconductor package10R.

Referring back toFIG.8, the damage barrier layer500may block the transmitted portion900A of the laser light900L, thereby preventing damage to the second semiconductor die210by the laser light900L. Because the semiconductor package10is configured to include the damage barrier layer500, it is possible to effectively prevent damage to the semiconductor package10during the laser marking process. As such, the damage barrier layer500may contribute to improving the reliability of the semiconductor package10. The damage barrier layer500may contribute to improving the quality of the semiconductor package10and improving the product yield of the semiconductor package10.

FIG.10is a block diagram illustrating an electronic system including a memory card7800employing at least one of the semiconductor packages according to embodiments of the present disclosure. The memory card7800may include a memory device7810such as a nonvolatile memory device, and a memory controller7820. The memory device7810and the memory controller7820may store data or read out the stored data. At least one of the memory device7810and the memory controller7820may include at least one of the semiconductor packages according to the embodiments.

The memory device7810may be a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller7820may control the memory7810such that stored data is read out or data is stored in response to a read/write request from a host7830.

FIG.11is a block diagram illustrating an electronic system8710including at least one of the semiconductor packages according to embodiments of the present disclosure. The electronic system8710may include a controller8711, an input/output device8712, and a memory device8713. The controller8711, the input/output device8712, and the memory device8713may be coupled with one another through a bus8715providing a path through which data move.

In an embodiment, the controller8711may include one or more microprocessor, digital signal processor, microcontroller, and/or logic device capable of performing the same functions as these components. The controller8711and/or the memory device8713may include at least one of the semiconductor packages according to the embodiments of the present disclosure. The input/output device8712may include at least one selected among a keypad, a keyboard, a display device, a touchscreen, and so forth. The memory device8713is a device for storing data. The memory device8713may store data and/or commands to be executed by the controller8711, and the like.

The memory device8713may be a volatile memory device including DRAM and/or a nonvolatile memory device including flash memory. For example, a flash memory device may be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory device may constitute a solid state disk (SSD). In this case, the electronic system8710may stably store a large amount of data in a flash memory system.

The electronic system8710may further include an interface8714configured to transmit and receive data to and from a communication network. The interface8714may be a wired or wireless type. For example, the interface8714may include an antenna or a wired or wireless transceiver.

The electronic system8710may be realized as a mobile system, a personal computer, an industrial computer or a logic system performing various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.

If the electronic system8710is equipment capable of performing wireless communication, the electronic system8710may be used in a communication system using a technique of CDMA (code division multiple access), GSM (global system for mobile communications), NADC (north American digital cellular), E-TDMA (enhanced-time division multiple access), WCDMA (wideband code division multiple access), CDMA2000, LTE (long term evolution), or Wibro (wireless broadband Internet)

The present teachings have been disclosed in conjunction with some embodiments as described above. Those skilled in the art will appreciate that various modifications, additions, and substitutions are possible, without departing from the scope and spirit of the present disclosure. Accordingly, the embodiments disclosed in the present specification should be considered from not a restrictive standpoint but an illustrative standpoint. The scope of the present teachings is not limited to the above descriptions but defined by the accompanying claims, and all of the distinctive features in the equivalent scope should be construed as being included in the present teachings.