Method of processing substrate, post-chemical mechanical polishing cleaning method, and method of and program for manufacturing electronic device

A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface damaged layer and polishing remnants to be controlled easily. An insulating film on a substrate, which has been revealed by chemical mechanical polishing, is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film which has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of processing a substrate, a post-chemical mechanical polishing cleaning method, and a method of and program for manufacturing an electronic device, and in particular relates to a method of manufacturing an electronic device according to which the flatness of a surface is improved by carrying out plasma-less etching after polishing a conductive film formed on the surface by chemical mechanical polishing.

2. Description of the Related Art

In a method of manufacturing an electronic device in which an electronic device is manufactured from a silicon wafer (hereinafter referred to merely as a “wafer”), a lithography step of forming a photoresist layer in a desired pattern on an insulating film that has been formed on a surface of the wafer, an etching step of fabricating a conductive film into gate electrodes, or fabricating wiring grooves or contact holes in the insulating film, with plasma using the photoresist layer as a mask, a film formation step of using PVD (physical vapor deposition) or the like to form a conductive film on the surface of the insulating film in which the wiring grooves or contact holes have been fabricated, and a flattening step (etch back step) of removing the formed conductive film, thus revealing the insulating film, and flattening the surface of the revealed insulating film are repeatedly implemented in this order.

In recent years, in the flattening step, a wafer surface polishing method known as CMP (chemical mechanical polishing) has come to be used instead of conventionally used dry etching or thermal reflow. In CMP, as shown inFIG. 11, the wafer is pushed against a rotating table201having a polishing cloth200made of polyurethane or the like stuck thereon by a head (wafer holding portion)202such that a surface of the wafer comes into close contact with the polishing cloth200, a polishing agent (slurry) having silica (SiO2) as a principal component thereof is supplied onto the polishing cloth200from a slurry supply nozzle203, and a cleaning liquid is supplied, and at the same time the rotating table201and the head202are rotated independently to one another, thus polishing the surface of the wafer. In CMP, it is thought that the polishing is promoted through a synergistic effect between physical contact between SiO2particles in the polishing agent and a conductive film or insulating film on the wafer surface, and chemical reaction between the SiO2particles and the conductive film or insulating film (see, for example, Japanese Laid-open Patent Publication (Kokai) No. H9-251969.

Moreover, in recent years, to prevent a decrease in signal transmission speed due to the high dielectric constant of interlayer insulating films, which has become a conspicuous problem as the wiring rule (required dimension) for electronic devices has been made smaller, low relative dielectric constant (low-κ) materials (see Table 1) have come to be used as interlayer insulating film materials. In particular, because copper is widely used as a wiring material, recently carbon-doped SiOC type low dielectric constant materials have come to be used as low dielectric constant interlayer insulating film materials. Moreover, the use of porous materials having a yet lower dielectric constant has also been investigated. Here, a relative dielectric constant of not more than 3.0 is referred to as a “low dielectric constant”.

However, on the surface of an insulating film revealed by CMP, residue (shavings) of the insulating film arises due to erosion (caused by the polishing) of the insulating film on wiring due to a difference in the polishing characteristics of the insulating film depending on the density of the wiring pattern under the insulating film, and a reaction product between the SiO2particles and the constituent material of the insulating film also arises.

Moreover, for an interlayer insulating film made of a porous material, the mechanical strength is low and adhesion to a conductive film is weak due to the many voids in the interlayer insulating film, and hence if the wafer is pushed by the head202at a normally used pressure in the CMP, then breaking away of the interlayer insulating film from the conductive film or disintegration of the interlayer insulating film occurs. To counteract this, in the case of using a porous material as an interlayer insulating film material, the wafer must be pushed at a low pressure, for example a pressure of not more than approximately 1.0 kPa, but with such low pressure CMP, the interlayer insulating film cannot be polished sufficiently, and hence unpolished portions arise on the surface of the interlayer insulating film polished by the CMP.

Such residue, reaction product, and unpolished portions (hereinafter referred to collectively as “polishing remnants”) on the surface of an insulating film are a causal factor in abnormalities in the inter-layer capacitance of a capacitor, or the wiring resistance, in an electronic device manufactured from the wafer, and must thus be removed.

Moreover, in the case of using CMP to polish away a conductive film that has been formed on a low dielectric constant interlayer insulating film, the revealed low dielectric constant interlayer insulating film is chemically damaged due to the low dielectric constant interlayer insulating film absorbing moisture due to contact between the surface of the low dielectric constant interlayer insulating film and the slurry or cleaning liquid used in the CMP, whereby a surface damaged layer (damaged layer) having a reduced carbon concentration is formed on the surface of the low dielectric constant interlayer insulating film.

Such a surface damaged layer has similar properties to SiO2(the native oxide), undergoing volume shrinkage in a subsequently implemented heat treatment step, which causes voids to be produced in the insulating film. It is thus necessary to remove the surface damaged layer before implementing such a subsequent step.

As a process for removing such a surface damaged layer and polishing remnants from the surface of an insulating film, a cleaning process is known in which the surface of the insulating film is cleaned using a post-CMP cleaning liquid comprised of a quaternary ammonium hydroxide, a polar organic amine, or the like.

However, such a cleaning process uses a liquid chemical and is thus categorized as a wet etching process. The surface damaged layer and polishing remnants are thus readily dissolved by the cleaning liquid in the cleaning process, and hence there is a problem that it is difficult to control the amount removed of the surface damaged layer and polishing remnants. Here, if the surface damaged layer and polishing remnants are dissolved too much by the cleaning liquid, then copper wiring disposed under the insulating film will be revealed, and hence the copper wiring will be corroded by the cleaning liquid.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method of processing a substrate, a post-chemical mechanical polishing cleaning method, and a method of and program for manufacturing an electronic device, which enable a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface damaged layer and polishing remnants to be controlled easily.

To attain the above object, in a first aspect of the present invention, there is provided a method of processing a substrate having thereon an insulating film that has been revealed by chemical mechanical polishing, the method comprising an insulating film exposure step of exposing the revealed insulating film to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and an insulating film heating step of heating to a predetermined temperature the insulating film that has been exposed to the atmosphere of the mixed gas.

According to the above method, the revealed insulating film is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and then the insulating film that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature. Upon the revealed insulating film being exposed to the atmosphere of the mixed gas containing ammonia and hydrogen fluoride under the predetermined pressure, a product based on the revealed insulating film and the mixed gas is produced, and then upon the insulating film that has been exposed to the atmosphere of the mixed gas being heated to the predetermined temperature, the above product is heated and thus vaporized. Through the product being vaporized, a surface damaged layer and polishing remnants on the surface of the insulating film produced through the chemical mechanical polishing can be removed. At this time, the amount produced of the product can be controlled through parameters of the mixed gas. Control of the amount removed of the surface damaged layer and polishing remnants on the surface of the insulating film can thus be carried out easily.

Preferably, the revealed insulating film is a low dielectric constant insulating film.

Also preferably, in the insulating film exposure step, the substrate is subjected to plasma-less etching.

According to the above method, the substrate is subjected to plasma-less etching. As a result, charge is not accumulated on a gate electrode in an electronic device manufactured from the substrate, and hence degradation or destruction of a gate oxide film can be prevented. Moreover, the electronic device is not irradiated with energetic particles, and hence semiconductor damage due to being struck by such energetic particles (i.e. crystal defects) can be prevented from occurring. Furthermore, unanticipated chemical reactions caused by plasma do not occur, and hence generation of impurities can be prevented, whereby contamination of the processing chambers in which the substrate is processed can be prevented.

Preferably, in the insulating film exposure step, the substrate is subjected to dry cleaning.

According to the above method, the substrate is subjected to dry cleaning. As a result, surface roughness can be prevented from occurring, and moreover changes in properties of the substrate surface can be suppressed, and hence a decrease in wiring reliability can be reliably prevented.

Preferably, a volumetric flow rate ratio of the hydrogen fluoride to the ammonia in the mixed gas is in a range of 1 to 1/2, and the predetermined pressure is in a range of 6.7×10−2to 4.0 Pa.

According to the above method, the volumetric flow rate ratio of the hydrogen fluoride to the ammonia in the mixed gas is in a range of 1 to 1/2, and the predetermined pressure is in a range of 6.7×10−2to 4.0 Pa. As a result, production of the product can be promoted, and hence the surface damaged layer and polishing remnants on the surface of the insulating film can be reliably removed.

Also preferably, the predetermined temperature is in a range of 80 to 200° C.

According to the above method, the predetermined temperature is in a range of 80 to 200° C. As a result, vaporization of the product can be promoted, and hence the surface damaged layer and polishing remnants on the surface of the insulating film can be reliably removed.

Preferably, the method further comprises a product production condition deciding step of measuring a shape of the revealed insulating film, and deciding at least one of the volumetric flow rate ratio of the hydrogen fluoride to the ammonia in the mixed gas and the predetermined pressure in accordance with the measured shape.

According to the above method, the shape of the revealed insulating film is measured, and at least one of the volumetric flow rate ratio of the hydrogen fluoride to the ammonia in the mixed gas and the predetermined pressure is decided in accordance with the measured shape. As a result, the amount removed of the surface damaged layer and polishing remnants on the surface of the insulating film can be controlled precisely, and hence the efficiency of the substrate surface processing can be improved. Furthermore, when removing some of the insulating film so as to eliminate local erosion that has arisen due to the chemical mechanical polishing, the amount removed of the insulating film can be controlled precisely, and hence re-flattening can be carried out precisely.

Preferably, the revealed insulating film has thereon unpolished portions produced through the chemical mechanical polishing.

Preferably, the revealed insulating film has thereon a reaction product originating from a polishing agent used in the chemical mechanical polishing.

Also preferably, the insulating film has thereon a surface damaged layer having a reduced carbon concentration.

To attain the above object, in a second aspect of the present invention, there is provided a post-chemical mechanical polishing cleaning method carried out on a substrate after a conductive film formed on an insulating film formed on a surface of the substrate has been polished away by chemical mechanical polishing, the method comprising an insulating film exposure step of exposing the insulating film, which has been revealed through the chemical mechanical polishing, to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and an insulating film heating step of heating to a predetermined temperature the insulating film that has been exposed to the atmosphere of the mixed gas.

According to the above method, the insulating film that has been revealed through the chemical mechanical polishing is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and then the insulating film that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature. Upon the revealed insulating film being exposed to the atmosphere of the mixed gas containing ammonia and hydrogen fluoride under the predetermined pressure, a product based on the revealed insulating film and the mixed gas is produced, and then upon the insulating film that has been exposed to the atmosphere of the mixed gas being heated to the predetermined temperature, the above product is heated and thus vaporized. Through the product being vaporized, a surface damaged layer and polishing remnants on the surface of the insulating film produced through the chemical mechanical polishing can be removed. At this time, the amount produced of the product can be controlled through parameters of the mixed gas. Control of the amount removed of the surface damaged layer and polishing remnants on the surface of the insulating film can thus be carried out easily.

Preferably, the method further comprises an insulating film drying step of drying a surface of the revealed insulating film before exposing the revealed insulating film to the atmosphere of the mixed gas.

According to the above method, the surface of the revealed insulating film is dried before the revealed insulating film is exposed to the atmosphere of the mixed gas. The production of the product is promoted under the resulting dry environment. The removal of the surface damaged layer and polishing remnants on the surface of the insulating film can thus be promoted.

To attain the above object, in a third aspect of the present invention, there is provided a method of manufacturing an electronic device, the method comprising a wiring formation step of forming wiring made of a first conductive material in a first insulating film that has been formed on a surface of a semiconductor substrate, a second insulating film formation step of forming a second insulating film on the first insulating film so as to cover the wiring, a photoresist layer formation step of forming a photoresist layer in a predetermined pattern on the formed second insulating film, a plasma fabrication step of fabricating a connecting hole reaching the wiring in the second insulating film by plasma processing using the formed photoresist layer, an ashing step of removing the photoresist layer, a connecting hole filling step of forming a conductive film made of a second conductive material on the second insulating film so as to fill the connecting hole with the second conductive material, a conductive film polishing step of polishing away the formed conductive film by chemical mechanical polishing, a second insulating film exposure step of exposing the second insulating film, which has been revealed through the chemical mechanical polishing, to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and a second insulating film heating step of heating to a predetermined temperature the second insulating film that has been exposed to the atmosphere of the mixed gas.

According to the above method, the second insulating film that has been revealed through the chemical mechanical polishing is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and then the second insulating film that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature. Upon the revealed second insulating film being exposed to the atmosphere of the mixed gas containing ammonia and hydrogen fluoride under the predetermined pressure, a product based on the revealed second insulating film and the mixed gas is produced, and then upon the second insulating film that has been exposed to the atmosphere of the mixed gas being heated to the predetermined temperature, the above product is heated and thus vaporized. Through the product being vaporized, a surface damaged layer and polishing remnants on the surface of the second insulating film produced through the chemical mechanical polishing can be removed. At this time, the amount produced of the product can be controlled through parameters of the mixed gas. Control of the amount removed of the surface damaged layer and polishing remnants on the surface of the second insulating film can thus be carried out easily.

Preferably, the method further comprises a connecting hole surface exposure step of exposing a surface of the fabricated connecting hole to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and a connecting hole surface heating step of heating to a predetermined temperature the surface of the connecting hole that has been exposed to the atmosphere of the mixed gas.

According to the above method, the surface of the connecting hole fabricated in the second insulating film is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. As a result, a product is produced on the surface of the connecting hole, and then the product is vaporized by heating, whereby a surface damaged layer on the connecting hole produced due to the plasma processing can be removed, and hence wiring delay due to the surface damaged layer can be prevented from occurring.

More preferably, the method further comprises a connecting hole coating step of coating the surface of the connecting hole that has been heated to the predetermined temperature with a conductive barrier.

According to the above method, the surface of the connecting hole that has been heated to the predetermined temperature is coated with a conductive barrier. As a result, the surface of the connecting hole from which the surface damaged layer has been removed, and the second conductive material subsequently filled into the connecting hole can be prevented from coming into contact with one another, whereby diffusion of the second conductive material into the second insulating film can be prevented.

To attain the above object, in a fourth aspect of the present invention, there is provided a method of manufacturing an electronic device, the method comprising a wiring formation step of forming wiring made of a first conductive material in a first insulating film that has been formed on a surface of a semiconductor substrate, a second insulating film formation step of forming a second insulating film on the first insulating film so as to cover the wiring, a photoresist layer formation step of forming a photoresist layer in a predetermined pattern on the formed second insulating film, a plasma fabrication step of fabricating a connecting hole reaching the wiring in the second insulating film by plasma processing using the formed photoresist layer, a connecting hole filling step of forming a conductive film made of a second conductive material on the second insulating film so as to fill the connecting hole with the second conductive material, a conductive film polishing step of polishing away the photoresist layer and the formed conductive film by chemical mechanical polishing, a second insulating film exposure step of exposing the second insulating film, which has been revealed through the chemical mechanical polishing, to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and a second insulating film heating step of heating to a predetermined temperature the second insulating film that has been exposed to the atmosphere of the mixed gas.

According to the above method, the second insulating film that has been revealed through the chemical mechanical polishing is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and then the second insulating film that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature. Upon the revealed second insulating film being exposed to the atmosphere of the mixed gas containing ammonia and hydrogen fluoride under the predetermined pressure, a product based on the revealed second insulating film and the mixed gas is produced, and then upon the second insulating film that has been exposed to the atmosphere of the mixed gas being heated to the predetermined temperature, the above product is heated and thus vaporized. Through the product being vaporized, a surface damaged layer and polishing remnants on the surface of the second insulating film produced through the chemical mechanical polishing can be removed. At this time, the amount produced of the product can be controlled through parameters of the mixed gas. Control of the amount removed of the surface damaged layer and polishing remnants on the surface of the second insulating film can thus be carried out easily. Moreover, the photoresist layer is polished away by the chemical mechanical polishing at the same time as the conductive film, and hence the throughput can be improved.

To attain the above object, in a fifth aspect of the present invention, there is provided a program for causing a computer to execute a method of processing a substrate having thereon an insulating film that has been revealed by chemical mechanical polishing, the program comprising an insulating film exposure module for exposing the revealed insulating film to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and an insulating film heating module for heating to a predetermined temperature the insulating film that has been exposed to the atmosphere of the mixed gas.

According to the above program, effects as for the first aspect can be achieved.

To attain the above object, in a sixth aspect of the present invention, there is provided a program for causing a computer to execute a post-chemical mechanical polishing cleaning method carried out on a substrate after a conductive film formed on an insulating film formed on a surface of the substrate has been polished away by chemical mechanical polishing, the program comprising an insulating film exposure module for exposing the insulating film, which has been revealed through the chemical mechanical polishing, to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and an insulating film heating module for heating to a predetermined temperature the insulating film that has been exposed to the atmosphere of the mixed gas.

According to the above program, effects as for the second aspect can be achieved.

To attain the above object, in a seventh aspect of the present invention, there is provided a program for causing a computer to execute a method of manufacturing an electronic device, the program comprising a wiring formation module for forming wiring made of a first conductive material in a first insulating film that has been formed on a surface of a semiconductor substrate, a second insulating film formation module for forming a second insulating film on the first insulating film so as to cover the wiring, a photoresist layer formation module for forming a photoresist layer in a predetermined pattern on the formed second insulating film, a plasma fabrication module for fabricating a connecting hole reaching the wiring in the second insulating film by plasma processing using the formed photoresist layer, an ashing module for removing the photoresist layer, a connecting hole filling module for forming a conductive film made of a second conductive material on the second insulating film so as to fill the connecting hole with the second conductive material, a conductive film polishing module for polishing away the formed conductive film by chemical mechanical polishing, a second insulating film exposure module for exposing the second insulating film, which has been revealed through the chemical mechanical polishing, to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and a second insulating film heating module for heating to a predetermined temperature the second insulating film that has been exposed to the atmosphere of the mixed gas.

According to the above program, effects as for the third aspect can be achieved.

To attain the above object, in an eighth aspect of the present invention, there is provided a program for causing a computer to execute a method of manufacturing an electronic device, the program comprising a wiring formation module for forming wiring made of a first-conductive material in a first insulating film that has been formed on a surface of a semiconductor substrate, a second insulating film formation module for forming a second insulating film on the first insulating film so as to cover the wiring, a photoresist layer formation module for forming a photoresist layer in a predetermined pattern on the formed second insulating film, a plasma fabrication module for fabricating a connecting hole reaching the wiring in the second insulating film by plasma processing using the formed photoresist layer, a connecting hole filling module for forming a conductive film made of a second conductive material on the second insulating film so as to fill the connecting hole with the second conductive material, a conductive film polishing module for polishing away the photoresist layer and the formed conductive film by chemical mechanical polishing, a second insulating film exposure module for exposing the second insulating film, which has been revealed through the chemical mechanical polishing, to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and a second insulating film heating module for heating to a predetermined temperature the second insulating film that has been exposed to the atmosphere of the mixed gas.

According to the above program, effects as for the fourth aspect can be achieved.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will now be described in detail with reference to the drawings showing preferred embodiments thereof.

First, a method of processing a substrate according to an embodiment of the present invention will be described.

FIG. 1is a plan view schematically showing the construction of a substrate processing apparatus to which is applied the method of processing a substrate according to the present embodiment.

As shown inFIG. 1, the substrate processing apparatus10is comprised of a first process ship11for carrying out reactive ion etching (hereinafter referred to as “RIE”) on electronic device wafers (hereinafter referred to merely as “wafers”) (substrates) W, a second process ship12that is disposed parallel to the first process ship11and is for carrying out COR (chemical oxide removal) processing and PHT (post heat treatment) processing, described below, on the wafers W, and a loader unit13, which is a rectangular common transfer chamber to which each of the first process ship11and the second process ship12is connected.

In addition to the first process ship11and the second process ship12, the loader unit13has connected thereto three FOUP mounting stages15on each of which is mounted a FOUP (front opening unified pod)14, which is a container housing twenty-five of the wafers W, an orienter16that carries out pre-alignment of the position of each wafer W transferred out from a FOUP14, and first and second IMS's (Integrated Metrology Systems, made by Therma-Wave, Inc.)17and18for measuring the surface state of each wafer W.

The first process ship11and the second process ship12are each connected to a side wall of the loader unit13in a longitudinal direction of the loader unit13, disposed facing the three FOUP mounting stages15with the loader unit13therebetween. The orienter16is disposed at one end of the loader unit13in the longitudinal direction of the loader unit13. The first IMS17is disposed at the other end of the loader unit13in the longitudinal direction of the loader unit13. The second IMS18is disposed alongside the three FOUP mounting stages15.

A SCARA-type dual arm transfer arm mechanism19for transferring the wafers W is disposed inside the loader unit13, and three loading ports20through which the wafers W are introduced into the loader unit13are disposed in a side wall of the loader unit13in correspondence with the FOUP mounting stages15. The transfer arm mechanism19takes a wafer W out from a FOUP14mounted on a FOUP mounting stage15through the corresponding loading port20, and transfers the removed wafer W into and out of the first process ship11, the second process ship12, the orienter16, the first IMS17, and the second IMS18.

The first IMS17is an optical monitor having a mounting stage21on which is mounted a wafer W that has been transferred into the first IMS17, and an optical sensor22that is directed at the wafer W mounted on the mounting stage21. The first IMS17measures the surface shape of the wafer W, for example the thickness of a surface layer, and CD (critical dimension) values of wiring grooves, gate electrodes and so on. Like the first IMS17, the second IMS18is also an optical monitor, and has a mounting stage23and an optical sensor24. The second IMS18measures the number of particles on the surface of each wafer W.

The first process ship11has a first processing unit25as a first vacuum processing chamber in which RIE is carried out on each wafer W, and a first load lock unit27containing a link-type single pick type first transfer arm26for transferring each wafer W into and out of the first processing unit25.

The first processing unit25has a cylindrical processing chamber (chamber). An upper electrode and a lower electrode are disposed in the chamber, the distance between the upper electrode and the lower electrode is set to an appropriate value for carrying out the RIE on each wafer W. Moreover, the lower electrode has in a top portion thereof an ESC (electrostatic chuck)28for chucking the wafer W thereto using a Coulomb force or the like.

In the first processing unit25, a processing gas is introduced into the chamber and an electric field is generated between the upper electrode and the lower electrode, whereby the introduced processing gas is turned into plasma so as to produce ions and radicals. The wafer W is subjected to the RIE by the ions and radicals.

In the first process ship11, the internal pressure of the first processing unit25is held at vacuum, whereas the internal pressure of the loader unit13is held at atmospheric pressure. The first load lock unit27is thus provided with a vacuum gate valve29in a connecting part between the first load lock unit27and the first processing unit25, and an atmospheric gate valve30in a connecting part between the first load lock unit27and the loader unit13, whereby the first load lock unit27is constructed as a preliminary vacuum transfer chamber whose internal pressure can be adjusted.

Within the first load lock unit27, the first transfer arm26is disposed in an approximately central portion of the first load lock unit27; first buffers31are disposed toward the first processing unit25with respect to the first transfer arm26, and second buffers32are disposed toward the loader unit13with respect to the first transfer arm26. The first buffers31and the second buffers32are disposed above a track along which a supporting portion (pick)33moves, the supporting portion33being disposed at the distal end of the first transfer arm26and being for supporting each wafer W. After having being subjected to the RIE, each wafer W is temporarily laid by above the track of the supporting portion33, whereby swapping over of the wafer W that has been subjected to the RIE and a wafer W yet to be subjected to the RIE can be carried out smoothly in the first processing unit25.

The second process ship12has a second processing unit34as a second vacuum processing chamber in which the COR processing is carried out on each wafer W, a third processing unit36as a third vacuum processing chamber that is connected to the second processing unit34via a vacuum gate valve35and in which the PHT processing is carried out on each wafer W, and a second load lock unit49containing a link-type single-pick type second transfer arm37for transferring each wafer W into and out of the second processing unit34and the third processing unit36.

FIGS. 2A and 2Bare sectional views of the second processing unit34appearing inFIG. 1; specifically,FIG. 2Ais a sectional view taken along line II-II inFIG. 1, andFIG. 2Bis an enlarged view of a portion A shown inFIG. 2A.

As shown inFIG. 2A, the second processing unit34has a cylindrical processing chamber (chamber)38, an ESC39as a wafer W mounting stage disposed in the chamber38, a shower head40disposed above the chamber38, a TMP (turbo molecular pump)41for exhausting gas out from the chamber38, and an APC (automatic pressure control) valve42that is a variable butterfly valve disposed between the chamber38and the TMP41for controlling the pressure in the chamber38.

The ESC39has therein an electrode plate (not shown) to which a DC voltage is applied. A wafer W is attracted to and held on the ESC39through a Johnsen-Rahbek force or a Coulomb force generated by the DC voltage. Moreover, the ESC39also has a coolant chamber (not shown) as a temperature adjusting mechanism. A coolant, for example cooling water or a Galden fluid, at a predetermined temperature is circulated through the coolant chamber. A processing temperature of the wafer W held on an upper surface of the ESC39is controlled through the temperature of the coolant. Furthermore, the ESC39also has a heat-transmitting gas supply system (not shown) that supplies a heat-transmitting gas (helium gas) uniformly between the upper surface of the ESC39and a rear surface of the wafer W. The heat-transmitting gas carries out heat exchange between the wafer W and the ESC39, which is held at a desired specified temperature by the coolant, during the COR processing, thus cooling the wafer W efficiently and uniformly.

Moreover, the ESC39has a plurality of pusher pins56as lifting pins that can be made to project out from the upper surface of the ESC39. The pusher pins56are housed inside the ESC39when a wafer W is attracted to and held on the ESC39, and are made to project out from the upper surface of the ESC39so as to lift the wafer W up when the wafer W is to be transferred out from the chamber38after having been subjected to the COR processing.

The shower head40has a two-layer structure comprised of a lower layer portion43and an upper layer portion44. The lower layer portion43has first buffer chambers45therein, and the upper layer portion44has a second buffer chamber46therein. The first buffer chambers45and the second buffer chamber46are communicated with the interior of the chamber38via gas-passing holes47and48respectively. That is, the shower head40is comprised of two plate-shaped members (the lower layer portion43and the upper layer portion44) that are disposed on one another and have therein internal channels leading into the chamber38for gas supplied into the first buffer chambers45and the second buffer chamber46.

When carrying out COR processing on a wafer W, NH3(ammonia) gas is supplied into the first buffer chambers45from an ammonia gas supply pipe57, described below, and the supplied ammonia gas is then supplied via the gas-passing holes47into the chamber38, and moreover HF (hydrogen fluoride) gas is supplied into the second buffer chamber46from a hydrogen fluoride gas supply pipe58, described below, and the supplied hydrogen fluoride gas is then supplied via the gas-passing holes48into the chamber38.

Moreover, the shower head40also has a heater, for example a heating element, (not shown) built therein. The heating element is preferably disposed on the upper layer portion44, for controlling the temperature of the hydrogen fluoride gas in the second buffer chamber46.

Moreover, a portion of each of the gas-passing holes47and48where the gas-passing hole47or48opens out into the chamber38is formed so as to widen out toward an end thereof as shown inFIG. 2B. As a result, the ammonia gas and the hydrogen fluoride gas can be made to diffuse through the chamber38efficiently. Furthermore, each of the gas-passing holes47and48has a cross-sectional shape having a constriction therein. As a result, any deposit produced in the chamber38can be prevented from flowing back into the gas-passing holes47and48, and thus the first buffer chambers45and the second buffer chamber46. Alternatively, the gas-passing holes47and48may each have a spiral shape.

In the second processing unit34, the COR processing is carried out on a wafer W by adjusting the pressure in the chamber38and the volumetric flow rate ratio between the ammonia gas and the hydrogen fluoride gas. Moreover, the second processing unit34is designed such that the ammonia gas and the hydrogen fluoride gas first mix with one another in the chamber38(post-mixing design), and hence the two gases are prevented from mixing together until they are introduced into the chamber38, whereby the hydrogen fluoride gas and the ammonia gas are prevented from reacting with one another before being introduced into the chamber38.

Moreover, in the second processing unit34, a heater, for example a heating element, (not shown) is built into a side wall of the chamber38, whereby the temperature of the atmosphere in the chamber38can be prevented from decreasing. As a result, the reproducibility of the COR processing can be improved. Moreover, the heating element in the side wall also controls the temperature of the side wall, whereby by-products formed in the chamber38can be prevented from becoming attached to the inside of the side wall.

Returning toFIG. 1, the third processing unit36has a box-shaped processing chamber (chamber)50, a stage heater51as a wafer W mounting stage disposed in the chamber50, a buffer arm52that is disposed around the stage heater51and lifts up a wafer W mounted on the stage heater51, and an PHT chamber lid (not shown) as an openable/closable lid that isolates the interior of the chamber from the external atmosphere.

The stage heater51is made of aluminum having an oxide film formed on a surface thereof, and heats the wafer W mounted thereon up to a predetermined temperature through heating wires or the like built therein. Specifically, the stage heater51directly heats the wafer W mounted thereon up to 100 to 200° C., preferably approximately 135° C., over at least 1 minute.

The PHT chamber lid has a sheet heater made of silicone rubber disposed thereon. Moreover, a cartridge heater (not shown) is built into a side wall of the chamber50. The cartridge heater controls the wall surface temperature of the side wall of the chamber50to a temperature in a range of 25 to 80° C. As a result, by-products are prevented from becoming attached to the side wall of the chamber50, whereby particles due to such attached by-products are prevented from arising, and hence the time period between one cleaning and the next of the chamber50can be extended. Moreover, an outer periphery of the chamber50is covered by a heat shield.

Instead of the sheet heater described above, a UV (ultraviolet) radiation heater may alternatively be used as the heater for heating the wafer W from above. An example of such a UV radiation heater is a UV lamp that emits UV radiation of wavelength 190 to 400 nm.

After being subjected to the COR processing, each wafer W is temporarily laid by on a track of a supporting portion53of the second transfer arm37by the buffer arm52, whereby swapping over of wafers W in the second processing unit34and the third processing unit36can be carried out smoothly.

In the third processing unit36, the PHT processing is carried out on each wafer W by adjusting the temperature of the wafer W.

The second load lock unit49has a box-shaped transfer chamber (chamber)70containing the second transfer arm37. The internal pressure of each of the second processing unit34and the third processing unit36is held at vacuum, whereas the internal pressure of the loader unit13is held at atmospheric pressure. The second load lock unit49is thus provided with a vacuum gate valve54in a connecting part between the second load lock unit49and the third processing unit36, and an atmospheric door valve55in a connecting part between the second load lock unit49and the loader unit13, whereby the second load lock unit49is constructed as a preliminary vacuum transfer chamber whose internal pressure can be adjusted.

FIG. 3is a perspective view schematically showing the construction of the second process ship12appearing inFIG. 1.

As shown inFIG. 3, the second processing unit34has the ammonia gas supply pipe57for supplying ammonia gas into the first buffer chambers45, the hydrogen fluoride gas supply pipe58for supplying hydrogen fluoride gas into the second buffer chamber46, a pressure gauge59for measuring the pressure in the chamber38, and a chiller unit60that supplies a coolant into the cooling system provided in the ESC39.

The ammonia gas supply pipe57has provided therein an MFC (mass flow controller) (not shown) for adjusting the flow rate of the ammonia gas supplied into the first buffer chambers45, and the hydrogen fluoride gas supply pipe58has provided therein an MFC (not shown) for adjusting the flow rate of the hydrogen fluoride gas supplied into the second buffer chamber46. The MFC in the ammonia gas supply pipe57and the MFC in the hydrogen fluoride gas supply pipe58operate collaboratively so as to adjust the volumetric flow rate ratio between the ammonia gas and the hydrogen fluoride gas supplied into the chamber38.

Moreover, a second processing unit exhaust system61connected to a DP (dry pump) (not shown) is disposed below the second processing unit34. The second processing unit exhaust system61is for exhausting gas out from the chamber38, and has an exhaust pipe63that is communicated with an exhaust duct62provided between the chamber38and the APC valve42, and an exhaust pipe64connected below (i.e. on the exhaust side) of the TMP41. The exhaust pipe64is connected to the exhaust pipe63upstream of the DP.

The third processing unit36has a nitrogen gas supply pipe65for supplying nitrogen (N2) gas into the chamber50, a pressure gauge66for measuring the pressure in the chamber50, and a third processing unit exhaust system67for exhausting the nitrogen gas out from the chamber50.

The nitrogen gas supply pipe65has provided therein an MFC (not shown) for adjusting the flow rate of the nitrogen gas supplied into the chamber50. The third processing unit exhaust system67has a main exhaust pipe68that is communicated with the chamber50and is connected to a DP, an APC valve69that is disposed part way along the main exhaust pipe68, and an auxiliary exhaust pipe68athat branches off from the main exhaust pipe68so as to circumvent the APC valve69and is connected to the main exhaust pipe68upstream of the DP. The APC valve69controls the pressure in the chamber50.

The second load lock unit49has a nitrogen gas supply pipe71for supplying nitrogen gas into the chamber70, a pressure gauge72for measuring the pressure in the chamber70, a second load lock unit exhaust system73for exhausting the nitrogen gas out from the chamber70, and an external atmosphere communicating pipe74for releasing the interior of the chamber70to the external atmosphere.

The nitrogen gas supply pipe71has provided therein an MFC (not shown) for adjusting the flow rate of the nitrogen gas supplied into the chamber70. The second load lock unit exhaust system73is comprised of a single exhaust pipe, which is communicated with the chamber70and is connected to the main exhaust pipe68of the third processing unit exhaust system67upstream of the DP. Moreover, the second load lock unit exhaust system73has an openable/closable exhaust valve75therein, and the external atmosphere communicating pipe74has an openable/closable relief valve76therein. The exhaust valve75and the relief valve76are operated collaboratively so as to adjust the pressure in the chamber70to any pressure from atmospheric pressure to a desired degree of vacuum.

FIG. 4is a diagram schematically showing the construction of a unit-driving dry air supply system for the second load lock unit49appearing inFIG. 3.

As shown inFIG. 4, dry air from the unit-driving dry air supply system77for the second load lock unit49is supplied to a door valve cylinder for driving a sliding door of the atmospheric door valve55, the MFC in the nitrogen gas supply pipe71as an N2purging unit, the relief valve76in the external atmosphere communicating pipe74as a relief unit for releasing the interior of the chamber70to the external atmosphere, the exhaust valve75in the second load lock unit exhaust system73as an evacuating unit, and a gate valve cylinder for driving a sliding gate of the vacuum gate valve54.

The unit-driving dry air supply system77has an auxiliary dry air supply pipe79that branches off from a main dry air supply pipe78of the second process ship12, and a first solenoid valve80and a second solenoid valve81that are connected to the auxiliary dry air supply pipe79.

The first solenoid valve80is connected respectively to the door valve cylinder, the MFC, the relief valve76, and the gate valve cylinder by dry air supply pipes82,83,84, and85, and controls operation of these elements by controlling the amount of dry air supplied thereto. Moreover, the second solenoid valve81is connected to the exhaust valve75by a dry air supply pipe86, and controls operation of the exhaust valve75by controlling the amount of dry air supplied to the exhaust valve75.

The MFC in the nitrogen gas supply pipe71is also connected to a nitrogen (N2) gas supply system87.

The second processing unit34and the third processing unit36also each has a unit-driving dry air supply system having a similar construction to the unit-driving dry air supply system77for the second load lock unit49described above.

Returning toFIG. 1, the substrate processing apparatus10has a system controller for controlling operations of the first process ship11, the second process ship12and the loader unit13, and an operation controller88that is disposed at one end of the loader unit13in the longitudinal direction of the loader unit13.

The operation controller88has a display section comprised of, for example, an LCD (liquid crystal display), for displaying the state of operation of the component elements of the substrate processing apparatus10.

Moreover, as shown inFIG. 5, the system controller is comprised of an EC (equipment controller)89, three MC's (module controllers)90,91and92, and a switching hub93that connects the EC89to each of the MC's. The EC89of the system controller is connected via a LAN (local area network)170to a PC171, which is an MES (manufacturing execution system) that carries out overall control of the manufacturing processes in the manufacturing plant in which the substrate processing apparatus10is installed. In collaboration with the system controller, the MES feeds back real real-time data on the processes in the manufacturing plant to a basic work system (not shown), and makes decisions relating to the processes in view of the overall load on the manufacturing plant and so on.

The EC89is a master controller (main controller) that controls the MC's and carries out overall control of the operation of the substrate processing apparatus10. The EC89has a CPU, a RAM, an HDD and so on. The CPU sends control signals to the MC's in accordance with programs corresponding to wafer W processing methods, i.e. recipes, specified by a user using the operation controller88, thus controlling the operations of the first process ship11, the second process ship12and the loader unit13.

The switching hub93selects at least one connection among the connections between the EC89and MC's in accordance with the control signals from the EC89.

The MC's90,91and92are slave controllers (auxiliary controllers) that control the operations of the first process ship11, the second process ship12, and the loader unit13respectively. Each of the MC's is connected respectively to an I/O (input/output) module97,98or99through a DIST (distribution) board96via a GHOST network95. Each GHOST network95is realized through an LSI known as a GHOST (general high-speed optimum scalable transceiver) on an MC board of the corresponding MC. A maximum of 31 I/O modules can be connected to each GHOST network95; with respect to the GHOST network95, the MC is the master, and the I/O modules are slaves.

The I/O module98is comprised of a plurality of I/O units100that are connected to component elements (hereinafter referred to as “end devices”) of the second process ship12, and transmits control signals to the end devices and output signals from the end devices. Examples of the end devices connected to the I/O units100of the I/O module98are: in the second processing unit34, the MFC in the ammonia gas supply pipe57, the MFC in the hydrogen fluoride gas supply pipe58; the pressure gauge59, and the APC valve42; in the third processing unit36, the MFC in the nitrogen gas supply pipe65, the pressure gauge66, the APC valve69, the buffer arm52, and the stage heater51; in the second load lock unit49, the MFC in the nitrogen gas supply pipe71, the pressure gauge72, and the second transfer arm37; and in the unit-driving dry air supply system77, the first solenoid valve80, and the second solenoid valve81.

Each of the I/O modules97and99has a similar construction to the I/O module98. Moreover, the connection between the I/O module97and the MC90for the first process ship11, and the connection between the I/O module99and the MC92for the loader unit13are constructed similarly to the connection between the I/O module98and the MC91described above, and hence description thereof is omitted.

Each GHOST network95is also connected to an I/O board (not shown) that controls input/output of digital signals, analog signals and serial signals to/from the I/O units100.

In the substrate processing apparatus10, when carrying out the COR processing on a wafer W, the CPU of the EC89implements the COR processing in the second processing unit34by sending control signals to desired end devices via the switching hub93, the MC91, the GHOST network95, and the I/O units100of the I/O module98, in accordance with a program corresponding to a recipe for the COR processing.

Specifically, the CPU sends control signals to the MFC in the ammonia gas supply pipe57and the MFC in the hydrogen fluoride gas supply pipe58so as to adjust the volumetric flow rate ratio between the ammonia gas and the hydrogen fluoride gas in the chamber38to a desired value, and sends control signals to the TMP41and the APC valve42so as to adjust the pressure in the chamber38to a desired value. Moreover, at this time, the pressure gauge59sends the value of the pressure in the chamber38to the CPU of the EC89in the form of an output signal, and the CPU determines control parameters for the MFC in the ammonia gas supply pipe57, the MFC in the hydrogen fluoride gas supply pipe58, the APC valve42, and the TMP41based on the sent value of the pressure in the chamber38.

Moreover, when carrying out the PHT processing on a wafer W, the CPU of the EC89implements the PHT processing in the third processing unit36by sending control signals to desired end devices in accordance with a program corresponding to a recipe for the PHT processing.

Specifically, the CPU sends control signals to the MFC in the nitrogen gas supply pipe65, and the APC valve69so as to adjust the pressure in the chamber50to a desired value, and sends control signals to the stage heater51so as to adjust the temperature of the wafer W to a desired temperature. Moreover, at this time, the pressure gauge66sends the value of the pressure in the chamber50to the CPU of the EC89in the form of an output signal, and the CPU determines control parameters for the APC valve69, and the MFC in the nitrogen gas supply pipe65based on the sent value of the pressure in the chamber50.

According to the system controller shown inFIG. 5, the plurality of end devices are not directly connected to the EC89, but rather the I/O units100which are connected to the plurality of end devices are modularized to form the I/O modules, and each I/O module is connected to the EC89via an MC and the switching hub93. As a result, the communication system can be simplified.

Moreover, each of the control signals sent by the CPU of the EC89contains the address of the I/O unit100connected to the desired end device, and the address of the I/O module containing that I/O unit100. The switching hub93thus refers to the address of the I/O module in the control signal, and then the GHOST of the appropriate MC refers to the address of the I/O unit100in the control signal, whereby the need for the switching hub93or the MC to ask the CPU for the destination of the control signal can be eliminated, and hence smoother transmission of the control signals can be realized.

As described earlier, polishing remnants arise on a surface of an insulating film that has been revealed by CMP, and moreover in the case in particular of using a carbon-containing low dielectric constant interlayer insulating film as such an insulating film, a surface damaged layer having similar properties to SiO2(hereinafter referred to as a “pseudo-SiO2layer”) is formed on the surface of the low dielectric constant interlayer insulating film. Here, the low dielectric constant interlayer insulating film must have a certain mechanical strength, specifically must have a Young's modulus of not less than 4 GPa, so as to not be crushed by the CMP. The pseudo-SiO2layer and polishing remnants on the surface of an insulating film as described above are a causal factor in various problems with electronic devices manufactured from a wafer W, and hence must be removed. Note that such the pseudo-SiO2layer is also known as an “altered layer” or a “sacrificial layer”.

In the method of processing a substrate according to the present embodiment, to cope with the above, a wafer W having thereon an insulating film on a surface of which polishing remnants have arisen or a pseudo-SiO2layer has been formed through CMP is subjected to the COR processing and PHT processing.

The COR processing is processing in which an oxide film on an object to be processed is made to undergo chemical reaction with gas molecules to produce a product, and the PHT processing is processing in which the object that has been subjected to the COR processing is heated so as to vaporize/thermally oxidize the product that has been produced on the object to be processed through the chemical reaction in the COR processing, thus removing the product from the substrate. As described above, the COR processing and also the PHT processing are (particularly the COR processing is) processing in which the oxide film on the object to be processed can be removed without using plasma and without using water, and hence are categorized as plasma-less etching or dry cleaning.

In the method of processing a substrate according to the present embodiment, ammonia gas and hydrogen fluoride gas are used as the gas. Here, the hydrogen fluoride gas promotes corrosion of the SiO2layer or pseudo-SiO2layer, and the ammonia gas is involved in synthesis of a reaction by-product for restricting, and ultimately stopping, the reaction between the oxide film and the hydrogen fluoride gas as required. Specifically, the following chemical reactions are used in the COR processing and the PHT processing, whereby an upper layer of an SiO2insulating film is removed so as to remove polishing remnants on the surface of the insulating film, or a pseudo-SiO2layer formed on the surface of a low dielectric constant interlayer insulating film is removed.

It has been found by the present inventors that the COR processing and PHT processing using the above chemical reactions exhibit the following characteristics. Incidentally, small amounts of N2and H2are also produced in the PHT processing.

1) Selectivity (Removal Rate) for Thermal Oxide Film is High

Specifically, according to the COR processing and PHT processing, the selectivity for a thermal oxide film is high, whereas the selectivity for silicon is low. The upper layer of the insulating film comprised of an SiO2film, which is a thermal oxide film, or the pseudo-SiO2layer, which has similar properties to such an SiO2film, can thus be removed efficiently.

2) Rate of Growth of Native Oxide Film on Surface of Insulating Film from Which Upper Layer or Pseudo-SiO2Layer has Been Removed is Slow

Specifically, the time taken for growth of a native oxide film of thickness 3 Å on the surface of an insulating film from which the upper layer has been removed by wet etching is 10 minutes, whereas the time taken for growth of a native oxide film of thickness 3 Å on the surface of an insulating film from which the upper layer has been removed by the COR processing and PHT processing is over 2 hours. There is thus no unwanted oxide film formation in an electronic device manufacturing process, and hence the reliability of the electronic device can be improved.

3) Reaction Proceeds in Dry Environment

Specifically, water is not used in the reaction in the COR processing, and moreover any water produced through the COR processing is vaporized in the PHT processing. There are thus no OH groups on the surface of the insulating film from which the upper layer has been removed. The surface of the insulating film thus does not become hydrophilic, and hence the surface does not absorb moisture. A decrease in electronic device wiring reliability can thus be prevented.

4) Amount Produced of Product Levels Off After a Certain Time has Elapsed

Specifically, once a certain time has elapsed, even if the insulating film continues to be exposed to the mixed gas of ammonia gas and hydrogen fluoride gas beyond this, there is no further increase in the amount produced of the product. Moreover, the amount produced of the product is determined by parameters of the mixed gas such as the pressure of the mixed gas and the volumetric flow rate ratio. Control of the amount removed of the insulating film can thus be carried out easily.

5) Very Little Particle Formation

Specifically, even upon implementing insulating film upper layer removal for 2000 wafers W in the second processing unit34and the third processing unit36, hardly any attachment of particles to the inner wall of the chamber38or the chamber50is observed. Problems due to particles such as short-circuiting of the electronic device wiring thus do not occur, and hence the reliability of the electronic device can be improved.

FIGS. 6A to 6Dconstitute a process diagram showing the method of processing a substrate according to the present embodiment.

As shown inFIGS. 6A to 6D, first, a wafer W having thereon either an SiO2insulating film104having unpolished portions101(FIG. 6A), reaction product102(FIG. 6B) or residue (not shown) due to CMP on a surface thereof, or else an SiOCH insulating film104ahaving a pseudo-SiO2layer103formed on a surface thereof (FIG. 6C) is housed in the chamber38of the second processing unit34, the pressure in the chamber38is adjusted to a predetermined pressure, ammonia gas, hydrogen fluoride gas, and argon (Ar) gas as a diluent gas are introduced into the chamber38to produce an atmosphere of a mixed gas comprised of ammonia gas, hydrogen fluoride gas and argon gas in the chamber38, and the insulating film104or104ais exposed to the atmosphere of the mixed gas under the predetermined pressure (insulating film exposure step) (FIG. 6A,6B, or6C). As a result, a product having a complex structure is produced from the SiO2constituting the insulating film104or the pseudo-SiO2layer103, the ammonia gas and the hydrogen fluoride gas, whereby the upper layer of the insulating film104or the pseudo-SiO2layer103is altered into a product layer105made of the product.

Next, the wafer W on which the product layer105has been formed is mounted on the stage heater51in the chamber50of the third processing unit36, the pressure in the chamber50is adjusted to a predetermined pressure, nitrogen gas is introduced into the chamber50to produce viscous flow, and the wafer W is heated to a predetermined temperature using the stage heater51(insulating film heating step). At this time, the complex structure of the product layer105is thermally decomposed, the product being separated into silicon tetrafluoride (SiF4), ammonia, nitrogen, and hydrogen fluoride, which are vaporized. The vaporized molecules are entrained in the viscous flow, and thus discharged from the chamber50by the third processing unit exhaust system67. As a result, either the upper layer of the insulating film104is removed and hence the unpolished portions101, reaction product102, and residue on the surface of the insulating film104are removed, or else the pseudo-SiO2layer103is removed (FIG. 6D).

In the second processing unit34, because hydrogen fluoride gas readily reacts with moisture, it is preferable to set the volume of the ammonia gas to be greater than the volume of the hydrogen fluoride gas in the chamber38, and moreover it is preferable to remove water molecules from the chamber38as much as possible. Specifically, the volumetric flow rate (SCCM) ratio of the hydrogen fluoride gas to the ammonia gas in the mixed gas in the chamber38is preferably in a range of 1 to 1/2, and moreover the predetermined pressure in the chamber38is preferably in a range of 6.7×10−2to 4.0 Pa (0.5 to 30 mTorr). As a result, the flow rate ratio for the mixed gas in the chamber38and so on is stabilized, and hence production of the product can be promoted.

Moreover, if the predetermined pressure in the chamber38is in a range of 6.7×10−2to 4.0 Pa (0.5 to 30 mTorr), then the amount produced of the product can be made to level off reliably after a certain time has elapsed, whereby the etching depth can be reliably controlled (i.e. is self-limited). For example, in the case that the predetermined pressure in the chamber38is 1.3 Pa (10 mTorr), the etching stops proceeding after approximately 3 minutes has elapsed from commencement of the COR processing, and the etching depth at this time is approximately 15 nm. Moreover, in the case that the predetermined pressure in the chamber38is 2.7 Pa (20 mTorr), the etching stops proceeding after approximately 3 minutes has elapsed from commencement of the COR processing, and the etching depth at this time is approximately 24 nm.

Moreover, the reaction to produce the product is promoted at around room temperature, and hence the temperature of the ESC39on which the wafer W is mounted is preferably set to 25° C. using the temperature adjusting mechanism (not shown) built therein. Furthermore, the higher the temperature, the less prone by-products formed in the chamber38are to become attached to the inner wall of the chamber38, and hence the temperature of the inner wall of the chamber38is preferably set to 50° C. using the heater (not shown) embedded in the side wall of the chamber38.

The product of the reaction is a complex compound containing coordinate bonds. Such a complex compound is weakly bonded together, and hence undergoes thermal decomposition even at a relatively low temperature. In the third processing unit36, the predetermined temperature of the wafer W is thus preferably in a range of 80 to 200° C., and furthermore the time for which the wafer W is subjected to the PHT processing is preferably in a range of 60 to 180 seconds. Moreover, to produce viscous flow in the chamber50, it is undesirable to make the degree of vacuum in the chamber50high, and moreover a gas flow of a certain flow rate is required. The predetermined pressure in the chamber50is thus preferably in a range of 6.7×10 to 1.3×102Pa (500 mTorr to 1 Torr), and the nitrogen gas flow rate is preferably in a range of 500 to 3000 SCCM. As a result, viscous flow can be produced reliably in the chamber50, and hence gas molecules produced through the thermal decomposition of the product can be reliably removed.

Moreover, before subjecting each wafer W to the COR processing, it is preferable to measure the surface shape of the insulating film104or104a, for example the film thickness, or a CD value of the shape of a wiring groove, a gate electrode or the like, and in accordance with the measured surface shape, for the CPU of the EC89to decide the values of processing condition parameters in the COR processing and PHT processing based on a predetermined relationship between the surface shape of the insulating film and processing condition parameters relating to the amount removed of the upper layer of the insulating film or the amount removed of the pseudo-SiO2layer (product production condition deciding step). As a result, the amount removed of the upper layer of the insulating film104, and hence the amount removed of the unpolished portions101, reaction product102, and residue on the surface of the insulating film104, can be controlled precisely, or the amount removed of the pseudo-SiO2layer103can be controlled precisely. The efficiency of the substrate surface processing can thus be improved. Furthermore, when removing some of the insulating film104so as to eliminate local erosion of the insulating film104that has arisen due to the CMP, the amount removed of the insulating film104can be controlled precisely, and hence re-flattening of the insulating film104can be carried out precisely.

The above predetermined relationship is set based on the difference in the surface shape of the insulating film104or104abetween before and after carrying out the COR processing and PHT processing as measured by the first IMS17at the start of a lot in which a plurality of wafers W are to be processed, i.e. the amount removed of the upper layer of the insulating film104or the amount removed of the pseudo-SiO2layer103by the COR processing and PHT processing, and the processing condition parameters in the COR processing and PHT processing at this time. Examples of the processing condition parameters include the volumetric flow rate ratio of the hydrogen fluoride gas to the ammonia gas, the predetermined pressure in the chamber38, and the heating temperature of the wafer W mounted on the stage heater51. The predetermined relationship thus set is stored in the HDD of the EC89or the like, and is referred to as described above when processing subsequent wafers W in the lot.

Moreover, whether or not to re-perform the COR processing and PHT processing on a wafer W may be decided based on the difference in the surface shape of the insulating film104or104abetween before and after performing the COR processing and PHT processing on that wafer W, and furthermore in the case that it is decided to re-perform the COR processing and PHT processing, the CPU of the EC89may decide the processing condition parameters for the COR processing and PHT processing based on the above predetermined relationship in accordance with the surface shape of the insulating film104or104aafter carrying out the COR processing and PHT processing on the wafer W in question the first time. As a result, the amount removed of the insulating film104or104acan be controlled precisely, and hence re-flattening of the insulating film104or104acan be carried out precisely.

According to the method of processing a substrate of the present embodiment, a wafer W having thereon either an insulating film104having unpolished portions101, reaction product102, and residue on a surface thereof, or else an insulating film104ahaving a pseudo-SiO2layer103formed on a surface thereof is exposed to an atmosphere of a mixed gas comprised of ammonia gas, hydrogen fluoride gas and argon gas under a predetermined pressure, and then the wafer W that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature. As a result, a product having a complex structure is produced from the SiO2constituting the insulating film104or the pseudo-SiO2layer103, the ammonia gas and the hydrogen fluoride gas, and then the complex structure of the product is thermally decomposed, the product being separated into silicon tetrafluoride, ammonia and hydrogen fluoride, which are vaporized. Through the product being vaporized, an upper layer of the insulating film104can be removed so as to remove the unpolished portions101, reaction product102, and residue on the surface of the insulating film104, or else the pseudo-SiO2layer103can be removed. At this time, the amount produced of the product levels off after a certain time has elapsed, and moreover the amount produced of the product can be controlled through parameters of the mixed gas. Control of the amount removed of the unpolished portions101, reaction product102, and residue on the surface of the insulating film104, or control of the amount removed of the pseudo-SiO2layer103can thus be carried out easily.

Moreover, according to the method of processing a substrate of the present embodiment, the unpolished portions101, reaction product102, and residue are, or the pseudo-SiO2layer103is, removed by subjecting the wafer W to plasma-less etching. As a result, charge is not accumulated on a gate electrode in an electronic device manufactured from the wafer W, and hence degradation or destruction of a gate oxide film can be prevented. Moreover, the electronic device is not irradiated with energetic particles, and hence semiconductor crystal defects can be prevented from occurring. Furthermore, unanticipated chemical reactions caused by plasma do not occur, and hence generation of impurities can be prevented, whereby contamination of the chamber38and the chamber50can be prevented.

Furthermore, according to the method of processing a substrate of the present embodiment, the unpolished portions101, reaction product102, and residue are, or the pseudo-SiO2layer103is, removed by subjecting the wafer W to dry cleaning. As a result, surface roughness of the wafer W can be prevented from occurring, and moreover changes in properties of the surface of the wafer W can be suppressed, and hence a decrease in wiring reliability in an electronic device manufactured from the wafer W can be reliably prevented.

Next, a post-chemical mechanical polishing cleaning method according to an embodiment of the present invention will be described.

In the post-chemical mechanical polishing cleaning method according to the present embodiment, a pseudo-SiO2layer and polishing remnants on a surface of an insulating film are removed using the COR processing and PHT processing as described above. The COR processing and the PHT processing are implemented in the second process ship12of the substrate processing apparatus10.

FIGS. 7A to 7Econstitute a process diagram showing the post-chemical mechanical polishing cleaning method according to the present embodiment.

As shown inFIGS. 7A to 7E, first, a wiring groove107is formed by RIE or the like in an SiO2insulating film106that has been formed by thermal oxidation on a surface of a wafer W, and then a conductive film108is formed by depositing polysilicon, which is a conductive material, on the insulating film106by PVD or CVD (chemical vapor deposition) (FIG. 7A).

Next, the conductive film108is polished away by CMP so as to reveal the insulating film106, whereby wiring109is formed. At this time, unpolished portions110, reaction product111, and residue (not shown) are formed through the CMP on the surface of the revealed insulating film106(FIG. 7B).

Next, the wafer W having thereon the insulating film106having the unpolished portions110, reaction product111, and residue on the surface thereof is transferred into a drying furnace (not shown) and the surface of the insulating film106is dried, and then the wafer W having thereon the insulating film106of which the surface has been dried is housed in the chamber38of the second processing unit34, the pressure in the chamber38is adjusted to a predetermined pressure, ammonia gas, hydrogen fluoride gas, and argon gas are introduced into the chamber38to produce an atmosphere of a mixed gas comprised of ammonia gas, hydrogen fluoride gas and argon gas in the chamber38, and the insulating film106is exposed to the atmosphere of the mixed gas under the predetermined pressure (insulating film exposure step). As a result, a product having a complex structure is produced from the SiO2constituting the insulating film106, the ammonia gas and the hydrogen fluoride gas, whereby an upper layer of the insulating film106is altered into a product layer112made of the product (FIG. 7C).

Next, the wafer W on which the product layer112has been formed is mounted on the stage heater51in the chamber50of the third processing unit36, the pressure in the chamber50is adjusted to a predetermined pressure, nitrogen gas is introduced into the chamber50to produce viscous flow, and the wafer W is heated to a predetermined temperature using the stage heater51(insulating film heating step). At this time, the complex structure of the product of the product layer112is thermally decomposed, the product being separated into silicon tetrafluoride (SiF4), ammonia, nitrogen, and hydrogen fluoride, which are vaporized (FIG. 7D). The vaporized molecules are entrained in the viscous flow, and thus discharged from the chamber50by the third processing unit exhaust system67. As a result, the upper layer of the insulating film106is removed, whereby the unpolished portions110, reaction product111, and residue on the surface of the insulating film106are removed together with the upper layer of the insulating film106(FIG. 7E).

According to the post-chemical mechanical polishing cleaning method of the present embodiment, a wafer W having thereon an insulating film106having unpolished portions110, reaction product111, and residue on a surface thereof due to CMP is exposed to an atmosphere of a mixed gas comprised of ammonia gas, hydrogen fluoride gas and argon gas under a predetermined pressure, and then the wafer W that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature. As a result, a product having a complex structure is produced from the SiO2constituting the insulating film106, the ammonia gas and the hydrogen fluoride gas, and then the complex structure of the product is thermally decomposed, the product being separated into silicon tetrafluoride, ammonia and hydrogen fluoride, which are vaporized. Through the product being vaporized, an upper layer of the insulating film106can be removed so as to remove the unpolished portions110, reaction product111, and residue on the surface of the insulating film106. At this time, the amount produced of the product can be controlled through parameters of the mixed gas. Control of the amount removed of the unpolished portions110, reaction product111, and residue on the surface of the insulating film106can thus be carried out easily.

Moreover, according to the post-chemical mechanical polishing cleaning method of the present embodiment, before the revealed insulating film106is exposed to the atmosphere of the mixed gas, the surface of the revealed insulating film106is dried. The production of the product thus proceeds under a dry environment, whereby the production of the product can be promoted, and then, the removal of the unpolished portions110, reaction product111, and residue can be promoted.

In the post-chemical mechanical polishing cleaning method according to the present embodiment described above, polishing remnants on the surface of an insulating film are removed. However, in the case that an SiOCH low dielectric constant interlayer insulating film is used as the insulating film, a pseudo-SiO2layer formed on the surface of the low dielectric constant interlayer insulating film through the CMP can also be removed by exposing the pseudo-SiO2layer to the atmosphere of the mixed gas so as to alter the pseudo-SiO2layer into a product layer, and then thermally vaporizing the product layer.

Next, a method of manufacturing an electronic device according to an embodiment of the present invention will be described.

In the method of manufacturing an electronic device according to the present embodiment, a pseudo-SiO2layer and polishing remnants on a surface of a low dielectric constant interlayer insulating film are removed using the COR processing and PHT processing as described above. The COR processing and the PHT processing are implemented in the second process ship12of the substrate processing apparatus10.

FIGS. 8A to 8Jconstitute a process diagram showing the method of manufacturing an electronic device according to the present embodiment.

As shown inFIGS. 8A to 8J, first, a wiring groove is formed by RIE or the like in an SiO2insulating film113(first insulating film) that has been formed by thermal oxidation on a surface of a wafer W, and then a conductive film (not shown) made of aluminum (Al) or an aluminum alloy (first conductive material) is formed on the insulating film113. Flattening processing such as etch back is further carried out, and then the formed conductive film is polished away so as to reveal the insulating film113, whereby wiring114is formed in the insulating film113(wiring formation step) (FIG. 8A).

Next, an SiOCH low dielectric constant interlayer insulating film115(second insulating film) is formed on the insulating film113by CVD so as to cover the wiring114(second insulating film formation step), and then a photoresist layer125patterned such as to have therein an opening124through which part of the low dielectric constant interlayer insulating film115directly above the wiring114will be exposed is formed by lithography (photoresist layer formation step) (FIG. 8B).

Next, using the formed photoresist layer125as a mask, the low dielectric constant interlayer insulating film115is etched by RIE, thus fabricating in the low dielectric constant interlayer insulating film115a via hole (connecting hole)118that reaches the wiring114(plasma fabrication step) (FIG. 8C). At this time, a surface of the via hole118is covered by a damaged layer119(surface damaged layer) having a reduced carbon concentration due to the RIE.

After that, the wafer W is housed in the chamber38of the second processing unit34, and the surface of the via hole118is exposed to an atmosphere of a mixed gas comprised of ammonia gas, hydrogen fluoride gas and argon gas under a predetermined pressure (connecting hole surface exposure step), and then the wafer W that has been exposed to the atmosphere of the mixed gas is mounted on the stage heater51in the chamber50of the third processing unit36, and the surface of the via hole118is heated to a predetermined temperature (connecting hole surface heating step). As a result, the damaged layer119is altered into a product layer, and then the product layer is thermally vaporized, thus removing the damaged layer119covering the surface of the via hole118. The wafer W is then taken out from the third processing unit36, and the photoresist layer125is removed by ashing or the like (ashing step) (FIG. 8D).

Next, the surface of the low dielectric constant interlayer insulating film115, including the surface of the via hole118from which the damaged layer119has been removed, is coated with a conductive barrier film120made of silicon nitride (SiN) or silicon carbide (SiC) (connecting hole coating step) (FIG. 8E), and then copper (Cu) (a second conductive material) is deposited by CVD or PVD on the low dielectric constant interlayer insulating film115that has been coated with the conductive barrier film120, thus forming a copper conductive film121, and moreover filling the via hole118with copper (connecting hole filling step) (FIG. 8F).

Next, the conductive film121and the conductive barrier film120are polished away by CMP so as to reveal the low dielectric constant interlayer insulating film115(conductive film polishing step), whereby a via fill122is formed. At this time, a pseudo-SiO2layer124due to the CMP is formed on the surface of the revealed low dielectric constant interlayer insulating film115, and unpolished portions116, reaction product117, and residue (not shown) due to the CMP are formed on the pseudo-SiO2layer124(FIG. 8G).

Next, the wafer W having thereon the low dielectric constant interlayer insulating film115having the unpolished portions116, reaction product117, and residue, and the pseudo-SiO2layer124on the surface thereof is housed in the chamber38of the second processing unit34, the pressure in the chamber38is adjusted to a predetermined pressure, ammonia gas, hydrogen fluoride gas, and argon gas are introduced into the chamber38to produce an atmosphere of a mixed gas comprised of ammonia gas, hydrogen fluoride gas and argon gas in the chamber38, and the low dielectric constant interlayer insulating film115is exposed to the atmosphere of the mixed gas under the predetermined pressure (second insulating film exposure step). As a result, a product having a complex structure is produced from the pseudo-SiO2layer, the ammonia gas and the hydrogen fluoride gas, whereby the pseudo-SiO2layer124is altered into a product layer123made of the product (FIG. 8H).

Next, the wafer W on which the product layer123has been formed is mounted on the stage heater51in the chamber50of the third processing unit36, the pressure in the chamber50is adjusted to a predetermined pressure, nitrogen gas is introduced into the chamber50to produce viscous flow, and the wafer W is heated to a predetermined temperature using the stage heater51(insulating film heating step). At this time, the complex structure of the product in the product layer123is thermally decomposed, the product being separated into silicon tetrafluoride, ammonia and hydrogen fluoride, which are vaporized (FIG. 8I). The vaporized molecules are entrained in the viscous flow, and thus discharged from the chamber50by the third processing unit exhaust system67. As a result, the pseudo-SiO2layer124is removed, and furthermore the unpolished portions116, reaction product117, and residue on the pseudo-SiO2layer124are also removed (FIG. 8J).

According to the method of manufacturing an electronic device of the present embodiment, a wafer W having thereon a low dielectric constant interlayer insulating film115having unpolished portions116, reaction product117, and residue, and a pseudo-SiO2layer124due to CMP on a surface thereof is exposed to an atmosphere of a mixed gas comprised of ammonia gas, hydrogen fluoride gas and argon gas under a predetermined pressure, and then the wafer W that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature. As a result, a product having a complex structure is produced from the pseudo-SiO2layer, the ammonia gas and the hydrogen fluoride gas, and then the complex structure of the product is thermally decomposed, the product being separated into silicon tetrafluoride, ammonia and hydrogen fluoride, which are vaporized. Through the product being vaporized, the pseudo-SiO2layer124can be removed, and furthermore the unpolished portions116, reaction product117, and residue on the pseudo-SiO2layer124can also be removed. At this time, the amount produced of the product can be controlled through parameters of the mixed gas. Control of the amount removed of the pseudo-SiO2layer124, and control of the amount removed of the unpolished portions116, reaction product117, and residue on the pseudo-SiO2layer124can thus be carried out easily.

Moreover, according to the method of manufacturing an electronic device of the present embodiment, a surface of a via hole118fabricated in the low dielectric constant interlayer insulating film115is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. As a result, a product is produced on the surface of the via hole118, and then the product is vaporized by heating, whereby a damaged layer119on the via hole118produced due to RIE can be removed, and hence wiring delay due to the damaged layer119can be prevented from occurring.

Furthermore, according to the method of manufacturing an electronic device of the present embodiment, the surface of the via hole118from which the damaged layer119has been removed by heating to a predetermined temperature is coated with a conductive barrier film120. As a result, the surface of the via hole118, and copper filled into the via hole118can be prevented from coming into contact with one another, whereby diffusion of the copper into the low dielectric constant interlayer insulating film115can be prevented.

In the method of manufacturing an electronic device shown inFIGS. 8A to 8Jdescribed above, the photoresist layer125is removed before the via hole118is filled with copper. However, the photoresist layer125may be removed after the via hole118has been filled with copper, for example the photoresist layer125may be polished away by the CMP when polishing away the conductive film121and the conductive barrier film120by CMP. As a result, the throughput can be improved.

In the post-chemical mechanical polishing cleaning method or the method of manufacturing an electronic device according to the present embodiments described above, before removing the upper layer of an insulating film and/or a pseudo-SiO2layer, it is preferable to transfer the wafer W into the first IMS17and measure the surface shape of the insulating film, and in accordance with the measured surface shape, for the CPU of the EC89to decide target values of processing condition parameters relating to the amount removed of the upper layer of the insulating film or the amount removed of the pseudo-SiO2layer, such as the volumetric flow rate ratio of the hydrogen fluoride gas to the ammonia gas, the predetermined pressure in the chamber38, and the heating temperature of the wafer W mounted on the stage heater51, based on a predetermined relationship between the surface shape of the insulating film and these processing condition parameters. As a result, the amount removed of the upper layer of the insulating film can be controlled precisely so as to precisely control the amount removed of polishing remnants on the surface of the insulating film, or else the amount removed of the pseudo-SiO2layer can be controlled precisely; the efficiency of the manufacture of the electronic device can thus be improved. Furthermore, when removing some of the insulating film so as to eliminate local erosion of the insulating film that has arisen due to the CMP, the amount removed of the insulating film can be controlled precisely, and hence re-flattening can be carried out precisely.

Moreover, whether or not to re-perform the removal of the upper layer of the insulating film or the like may be decided based on the difference in the surface shape of the insulating film between before and after performing the removal of the upper layer of the insulating film or the like, and furthermore in the case that it is decided to re-perform the removal of the upper layer of the insulating film or the like, the CPU of the EC89may decide the volumetric flow rate ratio of the hydrogen fluoride gas to the ammonia gas and so on, or may decide to re-perform the polishing by CMP, based on the above predetermined relationship in accordance with the surface shape of the insulating film after carrying out the removal of the upper layer of the insulating film or the like the first time. As a result, the amount removed of the upper layer of the insulating film or the like when re-performing the removal can be controlled precisely, and hence re-flattening of the upper layer of the insulating film or the like can be carried out precisely.

The substrate processing apparatus to which is applied the method of processing a substrate according to the above embodiment is not limited to being a substrate processing apparatus of a parallel type having two process ships arranged in parallel with one another as shown inFIG. 1, but rather as shown inFIGS. 9 and 10, the substrate processing apparatus may instead be one having a plurality of processing units arranged in a radial manner as vacuum processing chambers in which predetermined processing is carried out on the wafers W.

FIG. 9is a plan view schematically showing the construction of a first variation of the substrate processing apparatus to which is applied the method of processing a substrate according to the present invention. InFIG. 9, component elements the same as ones of the substrate processing apparatus10shown inFIG. 1are designated by the same reference numerals as inFIG. 1, and description thereof is omitted here.

As shown inFIG. 9, the substrate processing apparatus137is comprised of a transfer unit138having a hexagonal plan view, four processing units139to142arranged in a radial manner around the transfer unit138, a loader unit13, and two load lock units143and144that are each disposed between the transfer unit138and the loader unit13so as to link the transfer unit138and the loader unit13together.

The internal pressure of the transfer unit138and each of the processing units139to142is held at vacuum. The transfer unit138is connected to the processing units139to142by vacuum gate valves145to148respectively.

In the substrate processing apparatus137, the internal pressure of the loader unit13is held at atmospheric pressure, whereas the internal pressure of the transfer unit138is held at vacuum. The load lock units143and144are thus provided respectively with a vacuum gate valve149or150in a connecting part between that load lock unit and the transfer unit138, and an atmospheric door valve151or152in a connecting part between that load lock unit and the loader unit13, whereby the load lock units143and144are each constructed as a preliminary vacuum transfer chamber whose internal pressure can be adjusted. Moreover, the load lock units143and144have respectively therein a wafer mounting stage153or154for temporarily mounting a wafer W being transferred between the loader unit13and the transfer unit138.

The transfer unit138has disposed therein a frog leg-type transfer arm155that can bend/elongate and turn. The transfer arm155transfers the wafers W between the processing units139to142and the load lock units143and144.

The processing units139to142has respectively therein a mounting stage156to159on which is mounted a wafer W to be processed. Here, the processing unit140is constructed like the first processing unit25in the substrate processing apparatus10, the processing unit141is constructed like the second processing unit34in the substrate processing apparatus10, and the processing unit142is constructed like the third processing unit36in the substrate processing apparatus10. Each of the wafers W can thus be subjected to RIE in the processing unit140, the COR processing in the processing unit141, and the PHT processing in the processing unit142.

In the substrate processing apparatus137, the method of processing a substrate according to the present invention is implemented by transferring a wafer W having thereon an insulating film having polishing remnants or a pseudo-SiO2layer on a surface thereof into the processing unit141and carrying out the COR processing, and then transferring the wafer W into the processing unit142and carrying out the PHT processing.

Moreover, in the substrate processing apparatus137, the processing unit139may be a film formation apparatus (CVD apparatus) for forming an insulating film or the like on the surface of each of the wafers W, and the processing unit140may be a polishing apparatus for subjecting each of the wafers W to CMP. In this case, the transfer arm155transfers each wafer W into the processing units139to142in this order, whereby the film formation, CMP, COR, and PHT can be carried out on each wafer W continuously. As a result, the throughput can be improved. Moreover, because each wafer W is not transferred out into the loader unit13during this continuous processing, the wafer W does not come into contact with the external atmosphere, and hence formation of an oxide film on the insulating film can be prevented, and moreover attachment of particles onto the surface of the wafer W can be prevented, whereby the wiring reliability for an electronic device manufactured from the wafer W can be improved.

Operation of the component elements in the substrate processing apparatus137is controlled using a system controller constructed like the system controller in the substrate processing apparatus10.

FIG. 10is a plan view schematically showing the construction of a second variation of the substrate processing apparatus to which is applied the method of processing a substrate according to the present invention. InFIG. 10, component elements the same as ones of the substrate processing apparatus10shown inFIG. 1or the substrate processing apparatus137shown inFIG. 9are designated by the same reference numerals as inFIG. 1orFIG. 9, and description thereof is omitted here.

As shown inFIG. 10, compared with the substrate processing apparatus137shown inFIG. 9, the substrate processing apparatus160has an additional two processing units161and162, and the shape of a transfer unit163of the substrate processing apparatus160is accordingly different to the shape of the transfer unit138of the substrate processing apparatus137. The additional two processing units161and162are respectively connected to the transfer unit163via a vacuum gate valve164or165, and respectively have therein a wafer W mounting stage166or167.

Moreover, the transfer unit163has therein a transfer arm unit168comprised of two SCARA-type transfer arms. The transfer arm unit168moves along guide rails169provided in the transfer unit163, and transfers the wafers W between the processing units139to142,161and162, and the load lock units143and144.

In the substrate processing apparatus160, as for the substrate processing apparatus137, the method of processing a substrate according to the present invention is implemented by transferring a wafer W having thereon an insulating film having polishing remnants or a pseudo-SiO2layer on a surface thereof into the processing unit141and carrying out the COR processing, and then transferring the wafer W into the processing unit142and carrying out the PHT processing.

Moreover, in the substrate processing apparatus160, as for the substrate processing apparatus137, the processing unit139(or the processing unit161) may be a film formation apparatus (CVD apparatus) for forming an insulating film or the like on the surface of each of the wafers W, and the processing unit140(or the processing unit139) may be a polishing apparatus for subjecting each of the wafers W to CMP. In this case, again, the throughput can be improved, and the wiring reliability for an electronic device manufactured from the wafer W can be improved.

Operation of the component elements in the substrate processing apparatus160is again controlled using a system controller constructed like the system controller in the substrate processing apparatus10.

Examples of the electronic device include semiconductor devices, and also non-volatile or high-capacity memory devices having therein a thin film made of an insulating metal oxide material such as a ferroelectric material or a high dielectric material, in particular a material having a perovskite crystal structure. Examples of materials having a perovskite crystal structure include lead zirconate titanate (PZT), barium strontium titanate (BST), and strontium bismuth niobium tantalate (SBNT).

It is to be understood that the object of the present invention can also be attained by supplying to a system or apparatus (the EC89) a storage medium in which a program code of software that realizes the functions of the above described embodiment is stored, and then causing a computer (or CPU, MPU, or the like) of the system or apparatus (EC89) to read out and execute the program code stored in the storage medium.

In this case, the program code itself read out from the storage medium realizes the functions of the embodiment described above, and hence the program code and the storage medium in which the program code is stored constitute the present invention.

The storage medium for supplying the program code may be, for example, a floppy (registered trademark) disk, a hard disk, a magnetic-optical disk, a CD-ROM, a CD-R, a CD-RW, a DVD-ROM, a DVD-RAM, a DVD-RW, a DVD+RW, a magnetic tape, a non-volatile memory card, and a ROM. Alternatively, the program code may be downloaded via a network.

The form of the program code may be, for example, object code, program code executed by an interpreter, or script data supplied to an OS.