Pixel with increased charge storage

A pixel circuit comprising a photodiode, a floating diffusion, a transfer gate for electrically connecting the photodiode to the floating diffusion, and a charge storage device, wherein the charge storage device comprises an electrode which is at least partly overlaying the photodiode, and which is configured and adapted to be driven so as to influence the total capacitance of the pixel.

FIELD OF THE INVENTION

The present invention relates to the field of image sensors. More specifically it relates to image sensors used in high illumination, low contrast scenes.

BACKGROUND OF THE INVENTION

A high illumination, low contrast scene is for example occurring when an airplane is landing in the mist. In such a scene the illumination level of a pixel of an image sensor is high and therefore the charge storage requirements of such a pixel are high. However, the same sensor may be used in a low-light situation, where the charge storage requirements are low. Thus pixels with a high dynamic range are required.

FIG. 1shows a schematic cross-section of a prior art 4T pixel. The illustrated pixel100comprises a pinned photodiode110, a transfer gate120, a floating diffusion130and a reset gate140. The dynamic range of the 4T pixel is thereby dependent on the storage capacity of the floating diffusion.

In order to increase the storage capacitance of optical sensors, Sugawa proposes in US 2009/0045319 to configure these optical sensors such that photocharges, overflowing from the photodiode, are stored in a plurality of storage capacitance elements. Thereby an optical device can be obtained which maintains a high sensitivity and a high S/N ratio and has a wide dynamic range. Yet these capacitors consume area and thus reduce the fill factor and/or increase the pixel size.

SUMMARY OF THE INVENTION

It is an object of embodiments of the present invention to provide pixels with increased charge storage capabilities and methods for operating these pixels in order to achieve pixels with a high dynamic range, without significantly increasing the pixels size nor reducing the fill factor.

The above objective is accomplished by a method and device according to embodiments of the present invention.

In a first aspect, the present invention provides a pixel circuit comprising a photodiode, a floating diffusion, a transfer gate for electrically connecting the photodiode to the floating diffusion, and a charge storage device. The charge storage device comprises an electrode which is at least partly overlaying the photodiode, and which is configured and adapted to be driven so as to influence the total capacitance of the floating diffusion.

It is an advantage of embodiments of the present invention that the charge storage capacity of the pixel may be increased without increasing the area of the pixel. The pixel size may for example be between 1 and 5 μm.

In a pixel circuit according to embodiments of the present invention, the electrode of the charge storage device may be positioned such that a direct transfer of charges in the charge storage device towards the floating diffusion is possible by enabling a connection between an inversion or accumulation layer under the electrode and the floating diffusion.

It is an advantage of embodiments of the present invention that no extra transfer gate is required for transferring the charges in the charge storage device towards the floating diffusion. It is an advantage that pixels according to embodiments of the present invention can be operated both at a low sensitivity but with a high charge storage capacity, as well as at a high sensitivity with a low charge storage capacity. It is an advantage of embodiments of the present invention that these different operating modes result in a programmable full well (charge storage capacity QFW) ranging between 10 k electrons and 1 M electrons or even beyond. At high illumination the photon shot noise is the dominating noise factor. It is an advantage of embodiments of the present invention that this noise factor can be limited by increasing the charge storage capacity (QFW). By limiting the photon shot noise the noise equivalent contrast is improved (NEC). It is an advantage of embodiments of the present invention that the contrast can be increased in low contrast scenes such as fog or haze.

In a pixel circuit according to embodiments of the present invention, the photodiode may be a pinned photodiode. It is an advantage of embodiments of the present invention that a low dark current can be obtained. In embodiments of the present invention charges in the charge storage device cannot transfer to the floating diffusion via the transfer gate because they are blocked by the pinning layer of the pinned photodiode. It is therefore an advantage of embodiments of the present invention that the charges in the charge storage device can directly transfer to the floating diffusion.

In embodiments of the present invention, the pinned photodiode may comprise a pinning layer and a buried layer, wherein the buried layer is fully or partly covered by the pinning layer.

In embodiments of the present invention, the charge storage device may be a metal oxide semiconductor capacitor between the electrode and a top implant of the photodiode. It is an advantage of embodiments of the present invention that standard metal oxide semiconductor (MOS) technology can be applied for obtaining the charge storage device. It is an advantage of embodiments of the present invention that the area of the pixel is not increased by adding the charge storage device.

In a pixel circuit according to embodiments of the present invention, the transfer gate is positioned such that an inversion layer (if the top implant is of n-type) or accumulation layer (if the top implant is of p-type) can be established between the photodiode and the floating diffusion when pulling the transfer gate high.

In a second aspect, the present invention provides a method for operating a pixel circuit according to embodiments of the first aspect of the present invention. Such pixel circuit comprises a photodiode, a floating diffusion, a transfer gate for electrically connecting the photodiode to the floating diffusion, and a charge storage device comprising an electrode which is at least partly overlaying the photodiode, and which is configured and adapted to be driven so as to influence the total capacitance of the floating diffusion. The method according to embodiments of the present invention comprises operating the pixel circuit using at least one of the following operating steps:illuminating the pixel circuit while tying the transfer gate and the electrode low, and accumulating charges in the photodiode; orilluminating the pixel circuit while tying the transfer gate high or at an intermediate level and while tying the electrode low, and accumulating charges in the photodiode and the floating diffusion; orilluminating the pixel circuit while tying the transfer gate low or at an intermediate level and tying the electrode high or at an intermediate level, and accumulating charges in the charge storage device and the floating diffusion;
and reading out the accumulated charge by,pulsing the transfer gate thereby transferring the accumulated charge in the photodiode towards the floating diffusion and reading out charges present on the floating diffusion, and/orbiasing the electrode such that charge accumulated in the charge storage device is transferred towards the floating diffusion and reading the floating diffusion.
Where in embodiments of the present invention reference is made to an “intermediate level”, reference is made to a level between the low and the high level.

It is an advantage of methods according to embodiments of the present invention that the pixel circuit can be operated in different operating modes: in an operating mode with a high sensitivity and a low charge storage capacity, as well as in an operating mode with a low sensitivity and a high charge storage capacity, as well as in operating modes with an intermediate charge storage capacity. It is an advantage of embodiments of the present invention that no transfer gate is required for charging or discharging the charge storage device. It is an advantage of embodiments of the present invention that the charge storage capacity of the pixel is variable by tuning the intermediate levels to which the transfer gate and the electrode are tied. This allows to have a high gain range of the pixel when it is used without the extra charge storage and a low gain range when using the extra charge storage. In the last case a high signal, hence a high signal to noise ratio (SNR) or noise equivalent contrast (NEC) can be obtained.

A method according to embodiments of the present invention may comprise the following steps, in any suitable sequence:

a step of resetting the floating diffusion,

a step of reading out the floating diffusion for obtaining a background level,

a step, which may for example be happening before or in parallel to the steps previously mentioned, of illuminating the pixel circuit while the electrode is tied low and while the transfer gate is tied low, thus storing charges in the photodiode,

a step of pulsing the transfer gate for transferring charges from the photodiode to the floating diffusion, then reading out the floating diffusion,

a step of comparing the result of the pulsing step with the background level,

a step of illuminating the pixel circuit while the transfer gate is tied low or intermediate and the electrode is tied high, thus storing charges in the charge storage device and overflowing these to the floating diffusion, and

a step of reading out the floating diffusion.

It is an advantage of embodiments of the present invention that both high as well as low illumination can be read out by the same pixel and that hence a high dynamic range can be achieved, whereby the factor of high and low illuminations can differ by a factor of 2 to more than 20.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Where in embodiments of the present invention reference is made to the “top implant” of the photodiode, reference is made to the doped region of, or on top of, the photodiode which is the closest to the surface of the pixel (i.e. the doped region of, or on top of, the photodiode which is the furthest away from the substrate). A capacitor may be formed by applying an electrode and by applying an insulator layer between the electrode and the said top implant.

Where in embodiments of the present invention reference is made to “a charge storage device”, reference is made to a means for storing an excess of charges collected by the photodiode.

Where in embodiments of the present invention reference is made to a gate or an electrode being “tied high”, reference is made to such elements being driven by a voltage at least higher than the voltage in the semiconductor material, e.g. silicon, below the gate or electrode, plus a threshold voltage. For an nMOSFET such high voltage at the gate is typically in the range 2 to 4 V, meaning that the nMOSFET is “on” or in “strong inversion”.

Where in embodiments of the present invention reference is made to a gate or an electrode being “tied low”, reference is made to such elements being driven by a voltage lower than the threshold voltage, which is typically zero or even slightly negative.

FIG. 1shows a schematic cross-section of a prior art 4T pixel100comprising a pinned photodiode110for collecting charge carriers, a floating diffusion130for storing collected charge carriers, a transfer gate120between the photodiode110and the floating diffusion130for transferring charge carriers from the photodiode to110the floating diffusion130, a power supply VDDpix150, and a reset gate140between the floating diffusion130and the power supply150, for resetting the floating diffusion130. The pinned photodiode110comprises a pinning layer112on top of a N-type buried layer114in a P-type substrate160. Photons of sufficient energy which impinge onto the substrate160, create electron-hole pairs. The electrons are attracted towards the PN junction between the buried layer114and the substrate160, and are collected by the pinned photodiode110(see also the arrow annotated with e− inFIG. 1), and then transferred over the transfer gate120to the floating diffusion130. The maximum charge that can be collected in typical pixels by the floating diffusion130(i.e. of a full well, QFW) is in the order of 10000 e− and is dominated by the parasitic capacitances of the floating diffusion node130. A floating diffusion capacitance CFDof 1.5 fF results in a QFWof about 10000 e−. The floating diffusion capacitance CFDis the total capacitance for the floating diffusion node130, including the parasitic capacitances. The charge on the floating diffusion130is sensed, under the form of a floating diffusion voltage, by an in-pixel source follower170for readout. In this example of a 4T pixel the transfer gate120does not add to the capacitance of the floating diffusion130as the transfer gate120is switched off when the floating diffusion130signals are read out.

When tying the transfer gate120permanently high, the gate capacitance of the transfer gate120adds to the total capacitance of the floating diffusion130. When tying the transfer gate120permanently high, there is a permanent inversion layer230under the transfer gate120that is electrically shunted to the floating diffusion130as is illustrated inFIG. 2. The pinned photodiode is thus also permanently shunted to the floating diffusion130, and charges can permanently flow, over the transfer gate120, from the photodiode110to the floating diffusion130. In this case the operation of the 4T pixel100becomes the same as the operation of a prior art 3T-pixel.

When for example the prior art 4T pixel100, as illustrated inFIG. 2, is operated in its 4T operation and has a floating diffusion capacitance of 2 fF, this corresponds with a QFWof about 12000 e− at 1V. Tying the transfer gate120high, as inFIG. 2, and operating the same pixel as a 3T pixel as described above results in a floating diffusion capacitance additionally including the capacitance CTGof the transfer gate of for instance 10 fF. This results in that a total QFWof 72000 e− at 1V can be obtained. The contribution of the capacitance CPDof the pinned photodiode110to the charge of the full well QFWis negligible as the capacitance of the pinned photodiode is close to zero when its potential is above the depletion potential.

In a first aspect the present invention relates to a pixel circuit comprising a charge storage device, a photodiode and a floating diffusion. The charge storage device comprises an electrode which is, at least partly, overlaying the photodiode. The electrode310is configured, e.g. shaped and positioned, and may be driven so as to influence the total capacitance of the pixel. In particular the electrode310may be tied high to increase the total capacitance of the pixel. Suitable driving means may be provided, for instance for bringing the electrode310to a high or a low potential (=voltage), depending on the needs of the application. The total capacitance of the pixel is programmable, in the sense that it can be varied so as to take on different values, by suitably driving the electrode310. In particular embodiments, the electrode310may be positioned such that, when the electrode is tied high, a direct transfer of charges from the charge storage device towards the floating diffusion is possible. The advantage thereof will become clear in view of the prior art 4T pixel ofFIG. 1and the prior art 4T pixel operated as a 3T pixel shown inFIG. 2, which are both described above.

FIG. 3andFIG. 4show a cross-section of a pixel300in accordance with an embodiment of the present invention, in two different modes of operation. The pixel300comprises a pinned photodiode110for collecting charge carriers, a floating diffusion130for storing collected charge carriers, a transfer gate120between the photodiode110and the floating diffusion130for transferring charge carriers from the photodiode to110the floating diffusion130, a power supply VDDpix150, and a reset gate140between the floating diffusion130and the power supply150, for resetting the floating diffusion130. The pinned photodiode110comprises a pinning layer112on top of a N-type buried layer114in a P-type substrate160.

According to embodiments of the present invention, a charge storage device is provided, which is partly overlaying the pinned photodiode110. In this example the charge storage device is formed by adding a separate gate, formed by an electrode310, on top of and partially covering the pinned photodiode110, in particular on top of and partially covering the pinning layer112of the pinned photodiode110. The electrode310is thereby galvanically separated from the pinned photodiode110, for instance by providing a dielectric layer between the photodiode110and the electrode310. In these embodiments of the present invention, the electrode310serves as a MOS capacitor on top of the pinned photodiode110. The electrode310does not physically touch the transfer gate120. The electrode310is made of any suitable conductive material, for instance polysilicon or metal. In case the pixel circuit according to embodiments of the present invention is to be used for front side illumination, the charge storage device, in particular the electrode310thereof, should preferably be made of or at least comprise optically transparent material, such that the charge storage device does not substantially block, preferably does not at all block, the impinging light towards the photodiode110. In such case the electrode310may for example be made of a thin layer of polysilicon, a transparent conductive oxide layer such as for instance Indium Tin Oxide (ITO), fluorine doped tin oxide (FTO) or doped zinc oxide, or any other suitable transparent electrode material. For particular applications, carbon nanotube networks or graphene may for instance be used as electrode material, which can be made to be highly transparent to infrared light.

The total capacitance of the pixel circuit300can now be drastically changed depending on the operation mode. In 4T operation (not illustrated in the drawings, as obvious from prior art), hence when the transfer gate120is only actuated, i.e. put high, during transfer of charges from the photodiode110to the floating diffusion130, with the electrode310tied low, the capacitance of the floating diffusion is, for this example for instance, 2 fF, corresponding with a QFWof 12000 e− at 1V. In 3T operation, when the transfer gate120is high during the light integration and consequently also during read-out, and with the electrode310tied low, as illustrated inFIG. 3, the capacitance of the transfer gate120(e.g. 10 fF) adds to the total floating diffusion capacitance, thus, for this example, resulting in a total capacitance of 12 fF corresponding with a QFWof 72000 e− at 1V. When in 3T operation (the transfer gate120is tied high) also the electrode310is tied high, as illustrated inFIG. 4, a layer of electrons420(inversion layer under the electrode310) and a layer of electrons430(inversion layer under the transfer gate120) are formed. The layer of electrons430is in contact with the floating diffusion, as can be seen inFIG. 4. But also, in embodiments of the present invention, the layer420of electrons is in contact with the floating diffusion130. This is not shown in the cross-section ofFIG. 4, but becomes obvious in the top view ofFIG. 8, via path820. The electrode310will thus increase the effective capacitance of the floating diffusion130. The capacitance of the floating diffusion130increases with the gate capacitance formed by the electrode310. This capacitance, e.g. 50 fF, is added to the total capacitance of the floating diffusion, thus resulting in a QFWof about 400 ke− at 1V. It is therefore an advantage of embodiments of the present invention that the capacitance of the floating diffusion can be increased without proportionally increasing the pixel size. Hence, in embodiments of the present invention, the capacitance of the floating diffusion may be programmable, triggered by the way of operation of the pixel300.

The doping level of the pinning layer112of the pinned photodiode110should be selected such that it is not so strongly doped that a MOS capacitor operation is prevented when the electrode is biased high. The doping of the pinning layer112may be in the order of 1E16/cm3and 1E17/cm3, preferably with such p-type concentration that the threshold voltage of the electrode to this layer in on the order of 0.5 to 2V.

In case of a pinned photo diode110, the MOS capacitor is formed between the electrode310and the P-type pinning layer112. In alternative embodiments of the present invention, as explained below with respect to other embodiments, the charge storage device may be a MOS capacitor between an electrode310and the photo diode110itself.

When increasing the illumination of a pixel (high illumination applications), the photon shot noise (PSN) becomes the dominating noise source in the pixel.

The photon shot noise equals:
PSN[eRMS−]=SQRT(S[eRMS−])
whereby S is the signal of the pixel. The signal to noise ratio at high signal levels where the photon shot noise is the dominant noise therefore equals:

The best signal to noise ratio is therefore obtained at the highest signal. Hence the pixel can be designed such that the maximum charge of the full well QFWcan be as large as required by the expected illumination levels. It is thereby an advantage of embodiments of the present invention that the QFWcan be adapted, by selecting different modes of operation, depending on the illumination circumstances. An improved signal to noise ratio results in an improved noise equivalent contrast (NEC) which is essential to enhance the contrast of the image in for example on-chip or off-chip post-processing. Embodiments of the present invention therefore enable enhancing the contrast in fog, haze, and other low-contrast scenes. Whereas in normal images a SNR of 1:100 is sufficient, low-contrast images require a very high SNR before enhancing the low-contrast images. For example if the SNR is 100:1, corresponding with a QFWof 10000 electrons, an [image processing] numerical contrast enhancement with a factor10results in a decrease of the SNR to 10:1 which means that the noise becomes visible and disturbing to the human eye. Contrast enhancing an image with a SNR of 1000:1, corresponding with a QFWof 1000000 electrons, with a factor10will result in a SNR of 100:1 which is still OK for the human eye. It is thus an advantage of embodiments of the present invention that a pixel with an increased maximum charge of the full well QFWcan be realized.

FIG. 5shows the cross-section of a pixel500in accordance with alternative embodiments of the present invention. The pixel500illustrated inFIG. 5is similar to the pixel300illustrated inFIG. 3andFIG. 4, and features which are similarly numbered have a same function. The main difference between the pixel500ofFIG. 5and the pixel300ofFIG. 3andFIG. 5is that in the pixel500the photodiode does not comprises a pinning layer but only a buried diode510. Hence, also this embodiment, an electrode310is provided which at least partly overlaps the photodiode formed by the buried diode510, but no pinning layer is present between the buried diode510and the electrode310. However, a galvanic separation, for instance under the form of a dielectric layer, is present in between them. In the implementation illustrated inFIG. 5, the electrode310is tied low, such that a layer520of holes (inversion layer versus the buried diode510) is present underneath the electrode310at the surface of the buried diode510. In the absence of a pinning layer between the electrode310and the buried diode510, the electrode310should be biased low to prevent that the buried diode510touches the Si—SiO2via an inversion of accumulation layer, as this would deteriorate the dark current. InFIG. 5the transfer gate120is tied high, resulting in a layer of electrons430(inversion layer versus substrate) underneath the transfer gate120. The inversion layer is the bottom electrode of the MOS capacitance of the electrode310.

Other embodiments of the present invention, not illustrated in the drawings, may have a pinning layer underneath only part of the electrode310and/or only partly covering the buried diode510.

In embodiments of the present invention where a zone440of the pinning layer112is present between the layer of electrons420(inversion layer under the electrode310) and the floating diffusion130, as for instance illustrated inFIG. 4, the layer of electrons420cannot be transferred as such towards the floating diffusion130because of the presence of this zone440of the pinning layer112. Therefore, in preferred embodiments of the present invention, the electrode310is positioned such that a direct transfer of charges from the charge storage device towards the floating diffusion is made possible. Hereto, the transfer gate120over the substrate between the photodiode110and the floating diffusion130and the electrode310are physically implemented as a single electrode610. An example of such implementation is illustrated inFIG. 6,FIG. 7andFIG. 8.

FIG. 6andFIG. 7show a cross-section of a pixel600according to embodiments of the present invention, in two different modes of operation whereby the cross-section is taken such that a path for the charges in the charge storage device towards the floating diffusion130is visible.FIG. 6illustrates the case where the electrode610is connected to a low signal, whileFIG. 7illustrates the case where the electrode610is connected to a high signal.

In the implementation illustrated inFIG. 6, no conduction path exists towards the floating diffusion130. Also no layer of electrons underneath the electrode610is present.

In the implementation illustrated inFIG. 7, where the electrode610is tied to a high signal, impinging photons result in electrons which are collected in the buried layer114of the pinned photodiode110. When the number of electrons in the buried layer114increases so much that they cannot be stored in the buried layer114, or when the potential barrier to the inversion layer underneath the electrode310can be overcome, the electrons will go to that inversion layer and sit there as a layer620of electrons. The charge storage capacity in the inversion layer underneath the electrode610is much higher than the charge storage capacity in the buried layer114of the pinned photodiode110. The charge storage capacity in the buried layer114of the pinned photodiode110is for example 2000 electrons/μm2whereas the inversion layer in a MOS structure has a typical capacity of 30000 electrons/μm2.

In embodiments of the present invention, the charge may be stored in an accumulation layer or in an inversion layer underneath the electrode310, depending on which underlying implant is considered (buried layer410or pinning layer112). In the example illustrated inFIG. 7a sheet layer of electrons620is stored in an inversion layer underneath the electrode610.

In embodiments of the present invention the charge is entering the charge storage device (capacitor formed by the electrode310on top of the photodiode110) either by:overflow through the PN junction,ohmic conduction when the bias voltage is sufficiently high,via the connection of the inversion/accumulation/electron layer620to the floating diffusion130.

The layer underneath the electrode610may be referred to as an inversion layer when it is present on a P-doped background. When present on an N-doped background the layer underneath the electrode610may be referred to as an accumulation layer.

FIG. 8is a top view of a pixel800in accordance with an embodiment of the present invention. The figure shows an electrode805and a pinned photodiode110whereby the electrode805overlays the pinned photodiode110.FIG. 8moreover shows a transfer gate120partly above the pinned photodiode110and oriented towards the floating diffusion130and a reset gate140between the floating diffusion130and a connection to a voltage supply. The electrode310is positioned such that the pixel300has two paths from the pinned photodiode110towards the floating diffusion130.

A first path810is created via the transfer gate120, whereby charge collected in the pinned photodiode110accumulates in the pinned photodiode and can be read out using a pulse on the transfer gate120, preferably by using correlated double sampling (CDS). Thereby the voltage of the floating diffusion130may be measured twice: a first time after pulsing the reset gate140and a second time after pulsing the transfer gate120. By comparing both measurements, reset noise can be eliminated.

A second path820goes from the photodiode110to the floating diffusion130via the electrode805. Thereby the electrode805is positioned such that a parallel path, parallel with the path via the transfer gate120, towards the floating diffusion130is possible. When the charge accumulated in the pinned photodiode110exceeds the charge storage capacity of the pinned photodiode110, the charge will overflow the PN junction between the pinned photodiode's P and N layers, and integrate in the inversion layer present between the pinned photodiode110and the electrode805. This charge is shared, simultaneously or later with the floating diffusion130via the second path820. This charge can therefore be read out by the floating diffusion130.

WhereFIG. 8is a top view of a pixel in accordance with embodiments of the present invention,FIG. 3andFIG. 4can be said to be a cross-sectional view along the first path810, andFIG. 6andFIG. 7can be said to be a cross-sectional view along the second path820.

It is an advantage of embodiments of the present invention that excess charge may overflow and can be stored in the inversion or accumulation layer between the electrode805and the photodiode110, and can subsequently be read out by the floating diffusion130, rather than that the charge would overflow to the substrate160which would create a blooming effect.

In embodiments of the present invention the extra charge may flow over the transfer gate120into the floating diffusion130. This may be done for instance in a manner as described in U.S. Pat. No. 14/554,327, incorporated herein by reference. In this embodiment, the transfer gate is subsequently biased to at least three different bias voltages, of which at least OFF (no transfer of charges from the photodiode to the floating diffusion), ON (full transfer of charges from the photodiode to the floating diffusion) and an intermediate bias voltage with a value in the range between the OFF bias voltage and the ON bias voltage (partial transfer of overflow of charges from the photodiode to the floating diffusion) are used. This way, any possible overflow can be controlled by means of a single transistor by the selectable intermediate bias voltage, avoiding leakage of currents and related negative effects, while simultaneously collecting the overflown charges and enabling accounting for their influence.

In a second aspect, the present invention relates to a method for operating a pixel300,600,800according to embodiments of the present invention. In embodiments of the present invention the charge storage capacity of the charge storage device, and thus of the pixel in general, is tuned at readout time. In embodiments of the present invention the signals are even read out in high gain range and low gain range simultaneously, or quickly after one another. It is thereby an advantage that a high dynamic range signal can be obtained.

FIG. 16illustrates different steps of a method1600according to embodiments of the present invention for operating a pixel300,600,800. The method1600comprises two parts, a first part1601related to illuminating of the pixel and accumulation of charge, and a second part1602related to read-out. The first part1601comprises different possible steps for operating the pixel300,600,800while illuminating it. These steps are:

Step1610: illuminating the pixel circuit while tying the transfer gate120and the electrode310,610,805low. Charges may be collected only in the photodiode.

Step1620: illuminating the pixel circuit while tying the transfer gate120high or at an intermediate level and while tying the electrode310,610,805low. Charges may be collected in the photodiode and may be stored there, or may overflow—depending on the level of the transfer gate biasing—to the floating diffusion130.

Step1630: illuminating the pixel circuit while tying the transfer gate120low and tying the electrode310,610,805high or at an intermediate level. Charges may be collected by the photodiode and if excess charges are present they may overflow to the inversion or accumulation region underneath the electrode310,610,805.

The second part1602comprises different possible steps for reading out the accumulated charge. These are:

Step1640: pulsing the transfer gate120thereby transferring the accumulated charge in the photodiode110towards the floating diffusion130for thereafter reading out the charges present in the floating diffusion.

Step1650: biasing the electrode310,610,805such that charge accumulated in the charge storage device is transferred towards the floating diffusion130and reading the floating diffusion130.

Particular embodiments of the present invention provide a high dynamic range operation (HDR), which may comprise the following steps, as illustrated inFIG. 17:In a first step1710, the floating diffusion130may be reset by conveniently pulsing the reset gate140. Hereto, the reset gate is put high, so that the floating diffusion is connected to the power supply and is discharged, whereafter the reset gate is brought low again.In a second step1720the floating diffusion voltage, after having been reset, is read out via the source follower, thus obtaining a background level of the pixel. In a third step1610the pixel800is illuminated while the electrode805is tied low, and while the transfer gate120is tied low. Charges are only stored in the photodiode.In a fourth step1640the transfer gate120is pulsed whereby it goes from a tied low to a tied high and back again to the tied low state thereby transferring the accumulated charge in the photodiode towards the floating diffusion. The pulse period may be between 0.1 μs and 10 μs. After pulsing the transfer gate120and thus transferring the charges from the photodiode to the floating diffusion130, the latter is read out.The charge read out in the fourth step result is compared with the background level in a fifth step1730. In case of low illumination, and hence low charge (not overflowing the buried layer114of the pinned photodiode), the by the pixel integrated charge is obtained in this step.In case of high light levels, a further charge integration step1630takes place, whereby the electrode805is tied high and whereby the transfer gate120is tied low. The collected charge is in first instance stored in the photodiode, but if more charge is present than can be stored in the photodiode (high illumination levels), charge may overflow the barrier between the buried layer114of the pinned photodiode110to the inversion layer underneath the electrode805, and this overflown charge is directly transferred to the floating diffusion130.The charge overflown to the floating diffusion130it is read therefrom during a further step1650, after the integration time has elapsed. In case of high illumination, and hence high charge, the integrated charge is obtained in this step.

In embodiments of the present invention the electrode805and the transfer gate120may also be biased at intermediate levels. These operation modes according to embodiments of the present invention are illustrated inFIG. 9toFIG. 13. In each of these figures the left figure corresponds with the situation at the first path810via the transfer gate120and the right figure corresponds with the situation at the second path820via the electrode805.

The left figure inFIG. 9shows the cross-section of a pixel800whereby the cross-section is taken such that the first path810via the transfer gate120is shown. In this figure the electrode310is tied at an intermediate level. The right figure inFIG. 9shows the cross-section of a pixel800whereby the cross-section is taken such that the second path820via the electrode805is shown. Also in this figure the electrode805is tied at an intermediate level.

FIG. 10,FIG. 11,FIG. 12andFIG. 13show the potential diagrams for both paths810,820. The left diagrams show the potential diagrams of the first path810via the transfer gate120. The right diagrams show the potential diagrams of the second path via the electrode805. The accumulation of charges1010in the photodiode110, the potential barrier1020of the transfer gate120, the potential level1030in the floating diffusion130, the reset barrier1040of the reset gate140, and the VDDpix level1050are shown. Impinging photons on the pixel800result in charge accumulation in the photodiode110illustrated by the charge levels1010in the left graph ofFIG. 10. The transfer gate120may be tied to an intermediate level1020(TG int.) between ON (tied high) and OFF (tied low). From this level extra charges which would be collected in the photodiode110overflow over the transfer gate120in the floating diffusion130. The right graph ofFIG. 10shows the levels1060,1030when the electrode805is tied at an intermediate level. When biasing the electrode805to an intermediate level (Vinter), the inversion layer520voltage is Vinter-Vth(where Vthis the threshold hold voltage of this MOS structure) or lower. It will not be shunted automatically to the floating diffusion130as long as the floating diffusion is at a higher voltage.

FIG. 11shows potential diagrams when the transfer gate120is off and when the electrode805is tied to an intermediate level. In this mode charge is integrated in the photodiode. This operation mode can be applied in low illumination circumstances e.g. at night. In this mode the reset level of the floating diffusion can be measured (background measurement).

FIG. 12shows the potential levels when the electrode805is tied to an intermediate level and after applying an off-on-off pulse to the transfer gate120. The transfer gate is switched on by biasing the transfer gate120high to remove the potential barrier imposed by the transfer gate. When switching the transfer gate on, the charges accumulated in the photodiode110are transferred to the floating diffusion130region. After the off-on-off pulse of the transfer gate120, the potential level1030in the floating diffusion130can be measured. Correlated double sampling can be obtained by comparing the measured signal level with the previously measured reset level (background measurement).

FIG. 13shows the levels when the electrode805is tied to a high level and after high illumination of the pixel800whereby charges are collected in the inversion layer520of the charge storage device. This operation mode can be applied in high illumination circumstances with low contrast, for example in the mist.

The noise performance of a pixel800according to embodiments of the present invention is depending on the operation mode of the pixel and is evaluated considering kTC noise and the photon shot noise (PSN). It is thereby an advantage of embodiments of the present invention that a pixel800according to embodiments of the present invention can be operated in different operation modes depending on the illumination requirements. The given numbers are exemplary and are not limiting the invention thereto.

When operating the pixel800in 4T mode (small QFW, high gain), the floating diffusion capacitance is 2 fF corresponding with a QFWof 12000e−. The kTC noise is 20 eRMS−but can be removed by correlated double sampling which is possible in the 4T operation mode. Thus, at small light strength, the noise level is smaller than the kTC noise due to the correlated double sampling operation. At higher light strength the photon shot noise is dominating. The signal to noise ratio (considering the photon shot noise) in case both signal and noise are taken at the same illumination level is equal to sqrt(QFW/e−)=110:1. At a QFWof 12000e− the pixel800quickly saturates in this operation mode. Therefore it is an advantage of embodiments of the present invention that the pixel800can be operated in the following additional operation modes.

When operating the pixel800in 3T operation mode with medium gain by biasing the transfer gate120high and biasing the electrode805low, the capacity of the transfer gate adds to the floating diffusion capacitance resulting in a capacitance of 10 fF corresponding with a QFWof 72000e−. The kTC noise is in this case 50e−. The signal to noise ratio (considering the photon shot noise) in case both signal and noise are taken at the same illumination level is equal to sqrt(QFW/e−)=250:1.

When operating the pixel800in 3T operation mode with low gain by biasing the transfer gate120high and biasing the electrode805high, also the charge storage in the electrode capacitor is used. The capacity of the electrode805capacitor thus adds to the total capacitance of the floating diffusion130(through the second path820towards the floating diffusion130via the electrode310). This results in a floating diffusion capacitance of 50 fF corresponding with a QFWof 400000e−. The kTC noise is in this case 100e−. Thus at small light strength the noise level is equal to the kTC noise which is higher than the correlated double sampling noise. At higher light strength the photon shot noise is dominating. The signal to noise ratio (considering the photon shot noise) in case both signal and noise are taken at the same illumination level is equal to sqrt(QFW/e−)=650:1.

It is thus an advantage of embodiments of the present invention that the different operating modes according to embodiments of the present invention allow to operate the pixel in high gain mode as well as in low gain mode. Thereby the signal to noise ratio is increasing when decreasing the gain. Depending on the light intensity, a different operating mode can be selected. Operating modes can even be combined in order to obtain a high dynamic range.

The noise and signal-to-noise ratio in function of the signal in the different operating modes of the pixel800according to embodiments of the present invention are illustrated inFIG. 14andFIG. 15. The left graphs inFIG. 14andFIG. 15show the noise in function of the signal. Curves1410and1510are the noise levels when operating in 4T mode with a total floating diffusion capacitance of 2 fF. At small signal levels the noise is dominated by the correlated double sampling and at increasing signal levels the photon shot noise is dominating. Curves1420and1520are the noise levels when operating the pixel by biasing the transfer gate120high. The total floating diffusion capacitance corresponding with curves1420and1520is 12 fF. At low signal levels the kTC noise is dominating, at higher signal levels the photon shot noise is dominating. Curves1430and1530are the noise levels when operating the pixel by biasing the transfer gate120high and by biasing the electrode310high. The total floating diffusion capacitance corresponding with curve1420is 62 fF and with curve1520is 187 fF. At low signal levels the kTC noise is dominating, at higher signal levels the photon shot noise is dominating.

The signal to noise ratios of the same operating modes are illustrated in the right graphs ofFIG. 14andFIG. 15. Noise curve1410corresponds with signal to noise ratio1412and corresponds with a total floating diffusion capacitance of 2 fF. For the other curves the following relations can be made:1420,1422, 12 fF;1430,1432, 62 fF;1510,1512, 2 fF;1520,1522, 12 fF;1530,1532187 fF. The signal-to-noise ratio illustrates that the saturation level is increasing with an increasing floating diffusion capacitance. At low signal levels, however, the signal-to-noise ratio is higher for operating modes with a smaller floating diffusion capacitance. It is therefore an advantage of embodiments of the present invention that the pixel800can be operated in different operating modes.