A tachometer for monitoring several functions on an implement, such as engine, shaft and ground speeds. A microprocessor receives a-c input signals which vary in frequency as the shaft or ground speeds change. A time window synchronized with a rising edge on the desired input signal is provided during which the number of falling edges are counted. A running total weighted average of a number of successive counts is used to update a digital readout indicating speed. Each new count is compared with the previous average and, if a sudden speed change occurs, the processor shifts to a fast update mode in which the new count is used to immediately update the readout. Programming switches are provided for selecting the proper ground speed time window for a given tire size and for providing a ground speed indication in either kilometers per hour or miles per hour.

BACKGROUND OF THE INVENTION 
The present invention relates generally to a speed monitor and more 
specifically to a digital tachometer. 
On certain farm implements it is advantageous to be able to monitor several 
operating parameters. On a combine, for example, proper ground speed, 
header shaft speed, cleaning fan speed and engine speed are necessary for 
efficient removal of the crop from the field. Such problems as 
malfunctions, misadjustments, clogging and excessive loading can be 
quickly detected by monitoring the various speeds. 
Although numerous digital tachometer devices are available, heretofore none 
have been completely satisfactory. Some require a separate instrument for 
each function and, as a result, are high in cost and require much panel 
space at the operator's station. 
Accuracy is a problem with many tachometers. Some respond well during 
periods when the speed monitored is steady but have a slow response during 
acceleration and deceleration. Averaging techniques are often used which 
do not provide a true indication of speed and which can even, in certain 
situations, give an indication that speed is increasing when in fact the 
speed has just begun to decrease. If the device is made to respond quickly 
for accurate readings during periods of acceleration or deceleration, the 
display often is difficult to read during operation at steady speeds since 
small changes in the reading will cause constant change in the least 
significant digit. To prevent constantly changing digits at steady speeds, 
accuracy is often compromised. 
Commonly, magnetic transducers detecting passage of teeth on a rotating 
member provide an alternating current input to the device which varies in 
amplitude with the angular velocity of the rotating member. At low speeds, 
problems of noise and sensitivity affect accuracy. Jitter often occurs 
because circuitry is used which counts the number of cycles or pulses 
occuring during a given clock period begun at random. This random counting 
can result in different counts for consecutive clock periods even if the 
speed remains constant. This causes the least significant digit to change 
constantly, which is annoying to the operator. 
Ground speed measurements are usually derived from the rotational speed of 
a drive shaft and are affected by the size of the tires provided on the 
implement. If the tire size is changed, the ground speed indicated will be 
inaccurate. To correct for such changes, or alternatively to set the 
device to read in different units such as kilometers per hour rather than 
miles per hour, often requires an adjustment of a trimming potentiometer 
while a signal generator connected to the tachometer input simulates a 
signal for a given speed. 
SUMMARY OF THE INVENTION 
It is, therefore, an object of the present invention to provide a digital 
tachometer which eliminates the aforementioned problems. 
It is another object of the present invention to provide an improved 
tachometer which monitors several fucntions. It is a further object to 
provide such a tachometer which utilizes a single microprocessor. 
It is yet another object of the present invention to provide a tachometer 
which provides accurate readings without jitter both at relatively steady 
speeds and during periods of rapid acceleration or deceleration. It is 
still another object to provide such a tachometer which has a relatively 
sensitive input highly immune to noise. 
It is a further object of the present invention to provide a tachometer 
with a digital output that is relatively jitter-free and easy to read. 
It is yet another object of the invention to provide a tachometer for 
selectively monitoring one of a plurality of functions wherein a correct 
immediate response is provided when a new function is selected. 
It is still another object of the present invention to provide a tachometer 
which provides a ground speed indication and can be quickly and easily 
adjusted for the correct reading in either metric or the U.S. equivalent 
even for varying tire sizes. 
A digital tachometer utilizes a microprocessor for monitoring several 
functions, such as combine engine RPM, cleaning fan speed, header 
backshaft speed, and ground speed. Magnetic pickup devices provide a-c 
input signals with frequencies proportional to the speeds to be monitored. 
An input circuit with a filter and Schmitt trigger connected to each 
pickup device converts the signals to square waves which are fed to a 
microprocessor. The microprocessor selectively converts the square wave 
signals to ground or shaft speed information to be displayed on a digital 
display. Time windows are provided which to prevent jitter are syncronized 
with a rising edge of the square wave signals, and a counter counts the 
number of trailing edges during a window as an indication of the speed. In 
a first mode, a running total weighted average of the counts is output to 
the display with the latest count receiving the most weight to provide a 
truer output response than with a straight average. If a large change in 
speed occurs abruptly, the processor automatically changes to a fast 
update mode wherein the latest count rather than an average is output to 
the display. Operator switches are provided to select the function to be 
monitored, but the engine RPM will automatically be displayed on startup. 
Engine RPM is constantly monitored and a signal is provided to the 
operator if engine speed drops below a preselected minimum or increases 
above a preselected maximum. Programming switches are also provided for 
choosing a proper ground speed window for various tire sizes and also for 
selecting either km/h or mph readings without need for a trimming 
potentiometer or internal circuit changes. The processor automatically 
dims the display by changing the duty cycle of the display drivers when 
ambient light falls below a preselected level. 
These and other objects, advantages and features of the present invention 
will become apparent to one skilled in the art from a reading of the 
following detailed description of a preferred embodiment of the invention 
when taken in conjunction with the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring now to FIG. 1a, there are shown input circuits 10, 12, 14 and 16, 
each connected to an output 20 of a magnetic pickup 22 (FIG. 2) which 
senses the passage of teeth 24 on a rotating member. The pickup 22 
provides a sine wave to the corresponding input circuit having a frequency 
proportional to the angular velocity of the rotating member. Signals to 
the input circuits 10, 12, 14 and 16 can correspond, for example, to the 
engine RPM, cleaning fan speed, header backshaft speed, and ground speed, 
respectively, on a self-propelled combine. 
The input circuits 10-16 are identical, each including a low-pass filter 26 
and a limiting circuit 28. The filter has a resistor 30 connected between 
a pickup output 20 and a terminal 31. A capacitor 32 is connected between 
the terminal 31 and ground. The value of the resistor and capacitor are 
chosen to provide a filter cut-off frequency in the middle of the expected 
signal range for the corresponding magnetic pickup. The limiting circuit 
28 includes a pair of diodes 34 connected between the terminal 31 and 
ground to clip the input at a positive and a negative value of about 0.6 
volt. The output from a magnetic pickup increases in amplitude as the 
angular velocity of the corresponding rotating member increases, but the 
filter 26 and clipping circuit 28 help to maintain a constant level output 
at the terminal 32. The filter 26 also eliminates high frequency noise 
which may be present on the line 20. 
A coupling capacitor 36 connects the terminal 31 with an input 38 of a 
Schmitt trigger 40. The input 38 and a second input 42 to the Schmitt 
trigger are connected to a reference voltage line 44 by resistors 46 and 
48, respectively, and are biased to about a +2 volt level. The output 50 
of the Schmitt trigger is connected via a resistor 52 to the input 42 to 
establish the hysteresis range of the circuit. The output 50 of the 
Schmitt trigger 40 is connected through a pull-up resistor 54 to a 
reference voltage line 56 maintained at a potential of about 4 volts. The 
resistors are chosen so that a positive pulse of about 300 mv. coupled 
from the terminal 32 to the input 38 causes the output 50 to switch to the 
low level, while a negative pulse of about 300 mv. is required to cause 
the output to return to the positive level determined by the reference 
voltage at 56. By setting the transition points at +300 mv., up to about 
600 mv. of noise can be tolerated on the line 20 at the lower frequencies 
and even higher noise levels at higher frequencies because of the action 
of the low-pass filter. 
The reference voltages at points 44 and 56 are determined by a voltage 
divider including resistors 58, 60, and 62 connected between a power 
supply 64 and ground. 
The input circuits 10-16 convert the signals from the transducers 22 to 
constant amplitude square waves at the outputs 50. The outputs 50 are 
connected by lines 66, 68, 70 and 72 to a microprocessor 74 which in the 
preferred embodiment is a model 8048 microcomputer available from Intel 
Corporation of Santa Clara, California. The microprocessor includes an 
input/output (I/O) device 75 (FIG. 3) with input/output lines grouped in 
three ports 76, 78 and 80. Data is transferred over bus 82 between the I/O 
device and an 8-bit accumulator 84, which is the central point for most 
data transfers within the processor. 
A 64 byte random access memory (RAM) 86 is connected by busses 88 and 90 to 
the accumulator 94. The RAM 86 includes two banks (BANK 0 and BANK 1) of 
working registers R0-R7 and R0'-R7'. Data can be transferred directly 
between the accumulator and the working registers over bus 88. The 
remaining memory is addressed indirectly by an address stored in the R0 
and R1 registers. The working registers R0-R7 can also be loaded from a 
program memory 94 via bus 96. The memory 94, a read only memory which is 
mask programmable, is connected through bus 98 to the accumulator, and 
through bus 100 to the I/O device. 
Data can be transferred between the accumulator 84 and a timer/counter 102 
on a bus 104. The timer/counter includes an 8-bit register 106. In the 
preferred embodiment, a 6 Mhz crystal oscillator 108 (FIG. 1b) is 
connected to the XTAL pins of the processor and provides a frequency 
reference for the timer/counter. 
An 8-bit program status word (PSW) 110 can be loaded to and from the 
accumulator 84 via bus 112. One bit is a working register bank switch bit 
for determining which of the two banks of R0-R7 registers in the RAM 90 is 
to be directly addressable by the accumulator. Another bit is a carry bit 
for indicating that a previous operation has resulted in overflow of the 
accumulator. The carry bit of the PSW and an 8-bit register R5 are 
utilized together to provide a 9-bit register for counting the number of 
pulses occuring during a given clock period, as will be described in 
detail below. Two flags, F0 and F1, are also provided. 
For a detailed description of the construction and operation of the 
microprocessor 74, see MCS-48.TM. Family of Single Chip Microcomputers 
User's Manual available from Intel Corporation. 
The lines 66-72 are connected to the first port 76 of the microprocessor 
74. Connected between the second part 78 and ground are ground-speed 
programming switches 116-122 (FIG. 1b). Each of the switches 116-120 is 
either opened or closed according to a chart giving switch position for up 
to 8 different tire sizes which can be used on the ground wheel drive 
system on the implement being monitored. The switch 122 is either opened 
or closed, depending on whether ground speed is to be read in miles per 
hour or kilometers per hour. The four switches 116-122 thus provide ground 
speed calibration function. Upon powering up the circuit, a 4-bit word is 
determined by the switch positions and a window time for the ground speed 
function is selected corresponding to the word. If a switch is closed, the 
corresponding line of the port 78 is grounded and the corresponding bit is 
determined to be a logic "0". If the switch is open, the bit is a logic 
"1". The program in the memory 94 acts as a map and based on the word read 
into the accumulator 84 from the programming switches, a window value from 
a look-up table in the program memory 94 is read into a 2-byte RAM 
location (R29-R30). The window values are chosen such that each falling 
edge on the square wave input for the function selected occurring during a 
window corresponding to 10 RPM or 0.1 mph (or 0.1 km/h). 
Also connected to the first port 76 are four normally off momentary 
switches, including a ground speed switch 130, a header backshaft speed 
switch 132, a fan speed switch 134 and an engine RPM switch 136 for 
selecting which of the four input lines 66-72 are to be monitored. The 
processor constantly reads the switches 130-136 and stores the 
corresponding function select information in the working registers R7 of 
the RAM. A logic "1" appears at each of the four lines from the switches 
130-136 unless a switch is depressed to ground a line and produce a logic 
"0". If two switches are depressed at the same time, the display 152 will 
be blanked. 
Also connected to an input 140 (T1) of the microprocessor 74 is an output 
line 142 (FIG. 1a) from a light detector circuit 144. This circuit 144 
includes a photodiode 146 connected between the positive and negative 
inputs of an operational amplifier 148. The positive input is grounded, 
and feedback is provided between the output line 142 and the negative 
input via a resistor 150. When light above a preselected threshold 
impinges on the diode 146, current flows from the negative to the positive 
terminal causing the output on line 142 to go to the high or logic "1" 
level to supply current through the resistor 150 to the negative input. If 
the light decreases below the threshold, the output goes to the low or 
logic "1" level. Preferably, the threshold is selected so that the output 
goes low so the T1 input 140 sees a logic "0" at the level of light 
present at dusk at the operator's station. The processor continuously 
multiplexes a 4-digit incandescent display 152, operating each digit at a 
conventional 25% duty cycle when T1 is at the high level and alternately 
at a 10% duty cycle when T1 is at the low level. The reduction to a 10% 
duty cycle is accomplished by checking the level at pin T1 each time a 
digit is illustrated and automatically turning off the digit 40% of the 
way through its conventional illumination time if T1 is low. This feature, 
described in further detail below, dims the display at night so it is 
easier to read. A green filter 154 is placed over the diode 146 which 
preferably is located near the 4-digit display, to prevent infrared light 
from the display from activating the diode at night, for example, as the 
operator moves his hand near the display. 
Terminal 160 (RESET) of the microprocessor 74 is connected to a capacitor 
162 to assure that all circuitry is reset by an internal reset pulse when 
power is turned on. A reset circuit 164 is also connected to the terminal 
160. A voltage divider including resistors 166 and 168 is connected 
between a first voltage supply V1 (11.6 volts) and ground. The positive 
input of an operational amplifier 170 is connected between the resistors, 
and the negative input is connected to the reference voltage terminal 44 
of the input circuits. Normally, the voltage at the positive input of the 
amplifier 170 is higher than at the negative input so the output 172 
remains high. If the voltage supply level should drop, the output 172 goes 
low, causing the processor circuitry to reset preventing false indications 
resulting from the voltage drop. A second operational amplifier 174 has 
its positive input connected to the output 172 and its negative input 
connected to the terminal 44 so that when the output at 172 is low (for 
example, when the power is first turned on to the microprocessor), the 
output on a line 176 from the amplifier will be low. When the voltage at 
172 exceeds the voltage at the terminal 44, the voltage on line 176 goes 
high. 
Seven lines 180-192, are connected between the bus port 80 and a segment 
enable circuit 193 of standard 7-segment control logic 194 for the 4-digit 
display 152. Four 8-bit display registers R3C-R3F in the RAM 86 
corresponding to four display digits 200-206 are each loaded with the 
7-segment code for the desired readout. A conventional multiplexing method 
is used, with each of the four individual display registers being output 
approximately 25% of the time when the ambient light level is high. 
Display drivers 208-214 each include a Darlington pair input circuit 216 
connected to the second port 78 by one of four lines 218C-218F and to a 
drive transistor 220 for supplying current in turn to the appropriate 
display digit during the time the corresponding display register is being 
output. If the voltage on terminal T1 (input 140) is high, the line 218 
for a particular digit remains high during the entire 25% of the time the 
display register for that digit is being output. If the voltage on T1 is 
low, the time that the line remains high is decreased to 10% so that each 
digit is dimmed. The working register R2 in the RAM carries a 4-bit word 
consisting of one logic "1" and three logic "0"s which are rotated as the 
program in the memory is advanced providing a logic "1" on the appropriate 
line 218. The register R0 points to the particular register in the RAM 
where the 7-segment code is located for each digit selected. There are the 
four registers, R3C-R3F, corresponding to the four lines 218C-218F. 
Only 7 bits of each of the 4 display registers R3C-R3F in the RAM are 
required to produce the desired digit from each 7-segment lamp, and the 
most significant bit (MSB) is used to illuminate one of four lamps 232-238 
which indicate the selected function, engine RPM, fan speed, header 
backshaft speed and ground speed, respectively. The 8th bit of each 
display register is therefore a function select bit for the display. For 
example, if the operator pushes the header backshaft switch 132, a logic 
"0" is provided in the MSB in the third display register R3D while logic 
"1"s are present in the MSB in the other display registers. As the first 
two display registers R3F and R3E are output to the display logic 194, 
lamps 232 and 234 remain dark since the high level on line 230 during this 
portion of the cycle causes NAND circuit 240 to remain off. When the third 
display register R3D is read in turn to control the segments of the digit 
204, the low level at the MSB of that register causes the NAND gate 
circuit 240 to switch on, allowing current from the driver circuit 212 to 
illuminate the header backshaft indicator lamp 236. Because the ground 
speed function requires a decimal point between the digits 202 and 204, a 
decimal point lamp 242 is provided and is connected in parallel with the 
ground speed lamp 238. 
An engine speed warning light or monitor 250 (FIG. 1b) is connected between 
the collector of an NPN transistor 252 and the output 251 of the driver 
208. The collector is also connected to ground through a resistor 254 to 
establish a small idle current through the light 250 when the transistor 
252 is biased to the off condition. The base of the transistor is 
connected through an input resistor 256 to a selectively activatable 
oscillator 260 having a low frequency of oscillation. The time constant of 
RC circuits 262 and 264 connected to NAND gates 268 and 270 is about one 
second. The base is also connected to the line 176 which prevents the 
transistor 252 from turning on until the supply voltage has reached a 
predetermined level and the microprocessor 74 has been initialized by the 
RESET. The control input 272 of the oscillator 260 is connected to the 
output of a reset flip-flop 280 which includes NAND gates 282 and 284. An 
input 286 of the gate 282 is connected to the program pin (PROG) 288 of 
the microprocessor, and an input 289 of the gate 284 is connected to the 
read pin (RD) 290. The inputs 286 and 289 are connected through pullup 
resistors 292 and 294 to a positive 5-volt supply. 
A pulse from pin 288 (PROG) which drops the voltage at input 286 to ground 
causes the output 272 of the flip-flop 280 to go low, diabling the 
oscillator 260 by holding the output of the NAND gate 270 at the high 
level. A negative pulse from the pin 290 resets the flip-flop so that the 
output 272 is high, enabling the oscillator 260. The output of the NAND 
gate 268 is at ground level and the transistor 252 is biased off except 
when the oscillator 260 is enabled at which time the lamp 250 will flash 
at the oscillator frequency. The duty cycle of lamp 250 while the base of 
the transistor 252 is biased above the base-emitter turn-on voltage is the 
same as the duty for the digit 200 (FIG. 1c) since the lamp is connected 
to the output 251 of the driver 208. This assures that the lamp 250 will 
be dimmed with the rest of the display 152 at night. In the preferred 
embodiment, the processor 74 constantly monitors the engine speed as well 
as the function selected by the switches 130-136 and outputs a pulse on 
the RD pin 290 to start the oscillator and cause the tolerance indicator 
250 to flash if engine speed rises above 2400 RPM or drops below 2180 RPM. 
Pins 292, 294 and 296 (EA, V.sub.ss and T0) of the microprocessor are 
grounded. Pins 300-306 (ss, INT, V.sub.cc and V.sub.dd) are connected to 
the positive 5-volt supply. 
The data memory of the RAM 86 includes an average value (A.sub.n) register 
R32-R33, an immediate value (X.sub.n) register R34-R35, and a four times 
average value (T.sub.n) register R36-R37. Also included is a time-out 
register R27-R28 utilized to insure that, when there are no pulses coming 
in, the program will not remain in the "START" routine 500 (FIG. 4b, 
described below) indefinitely. The function of the registers will become 
apparent from the description of operation of the microprocessor 74 in 
conjunction with the flowchart of FIG. 4a-4h. 
During each window the microprocessor 74 determines the number of pulses 
occurring on one of the lines 66-72 corresponding to the function selected 
by counting the number of falling edges. A weighted average of the counts 
obtained during successive windows is provided. In the preferred 
embodiment, the average A.sub.n is computed according to the following 
equation: 
EQU A.sub.n =1/4 [X.sub.n +3/4X.sub.n-1 +(3/4).sup.2 X.sub.n-2 +(3/4).sup.3 
X.sub.n-3 +. . . ] (Eqn. 1) 
where X.sub.n is the immediate value of the pulse count taken during the 
nth window. The latest count X.sub.n receives the most weight. Normally 
the average value A.sub.n stored in the average value register 
R32-R.times.is converted to 7-segment code which is stored in the four 
display registers R3C-R3F and utilized to update the display 152. However, 
the immediate value X.sub.n is first compared with the previous average 
A.sub.n-1 and, if X.sub.n is significantly different than A.sub.n-1, 
indicating rapid acceleration or deceleration, the immediate value X.sub.n 
rather than the new average is utilized to update the display 152. In the 
preferred embodiment, if the immediate count X.sub.n differs from the last 
average A.sub.n-1 by four or more counts (i.e., 40 or more RPM), the 
program calls for updating the display 152 with the immediate value 
X.sub.n. The program will remain in the immediate update mode for six 
immediate updates before returning to the averaging mode. This feature 
allows the operator to guickly adjust the selected function speed to the 
desired value without delay and overshoot, while at the same time 
providing a very accurate, non-jittering display at relatively steady 
operating speeds. 
Referring to the flow chart (FIG. 4a), the operation of the tachometer is 
as follows. The power is turned on to the circuit, and the RESET function 
described above initiallizes the processor 74. A "RESET" routine 400 is 
begun, and the display 152 is blanked (step 401) by assuring the four 
driver input lines 218 are low. The average value (A.sub.n) register 
R32-R33 and the timer/counter register 106 are cleared. A pulse output on 
the PROG pin 288 (step 404) to assure that the oscillator 260 is disabled 
so the warning lamp 250 does not flash. The output register pointer R0 and 
the digit select register R2 in the first bank (BANK 0) of the RAM, are 
initialized at 405 so that the bit corresponding to the most significant 
digit 200 is a "1". The register R2 selects which one of the digits 
200-206 is to be activated by determining which one of the lines 218 to 
the digit drivers will be high. The register R0 points to one of four 
registers R3C-R3F in the RAM 86 containing the 7-segment code for that 
particular digit. Then at step 406 the register R7, which stores a code 
that corresponds to the desired function selected by the switches 130-136, 
is loaded with the code corresponding to the engine speed function which 
is displayed initially. When a different function switch is depressed, a 
new code will be entered into R7. 
During the "RESET" routine a "0" is entered to the flag bit F1 at step 407 
signifying that the microprocessor program has not been interrupted from 
an "UPDATE" routine 600 (FIG. 4d) which is used to calculate the value to 
be displayed. The four display registers R3C-R3F are loaded with ones 
(408) so the segment enable circuit 193 turns off all 7 segments of the 
digits. The MSB in one of the display registers R3C-R3F corresponding to 
the function selected (i.e., the engine RPM on the digit 200) is blanked 
so that the NAND gate 240 is turned on to illuminate the lamp 232 during 
the portion of the cycle the line 218F is high, which is determined by the 
location of the "1" in R2. 
During step 409, the four programming switches 116-122 are read and a 
proper time window is selected from the program memory 94 on the basis of 
the switch positions. The window is chosen such that each pulse counted 
during the window corresponds to 0.1 mph (10 RPM when shaft speeds are 
measured). The window value is loaded into the window register R29-R30 of 
the RAM 86 during step 410. (Register designations are in a hexidecimal 
rather than a decimal based system.) The window value actually determines 
the number of times the processor will run through the "START" routine 
(FIG. 4b) which is a predetermined number of instruction cycles (66) no 
matter which path is taken through the routine and therefore is a 
well-defined time, subject only to inaccuracies in the crystal oscillator 
108. 
The 9-bit counter register consisting of the register R5 and the carry bit 
is cleared at step 411 so it is ready to be incremented each time a 
falling edge occurs on the selected input during a window. The time-out 
register R27-R28, which counts the number of times the program runs 
through the "START" routine without occurrence of a rising edge on one of 
the input lines 66-72 selected, is cleared. 
A working register R6 is loaded with "1"s. During operation the register R6 
stores a "1" or a "0" depending on whether the selected input was high or 
low during the last sample. A change from a "1" to a "0" indicates a 
falling edge occurred on the input, while a change from a "0" to a 
"1"indicates occurrence of a rising edge. Since the window is started on a 
rising edge of the square wave from the input circuit, loading R6 with 
"1"s assures that a falling edge and a rising edge occur before the window 
is begun after the "RESET" routine 400. 
The flag F0 is cleared during the "RESET" routine to signify that a window 
has not started. When the rising edge is detected and the window is begun 
during the "START" routine 500, a "1" is stored in F0. 
Working registers R3 and R4 together form a 2-byte window register which is 
loaded with a value corresponding to the function selected (i.e., engine 
RPM) which determines the number of cycles through the "START" routine 
during a window, thereby establishing the time of a window. 
The "START" routine 500 (FIG. 4b) has two functions. The first is the 
timer/counter interrupt handler. When program operation is in the "UPDATE" 
routine 600 (FIG. 4d) wherein the data is prepared for readout to the 
display 152, program flow is interrupted periodically by the timer/counter 
102 in order to continuously multiplex the display and examine the 
function select switches 130-136. The second function of the "START" 
routine (when entered as a normal routine) is to set up a window time 
corresponding to the function selected and then count the number of 
falling edges within this window. 
At step 501 the value in the accumulator 84 is stored in a working register 
R2' in the second bank (BANK 1) so that if the program was interrupted 
from the "UPDATE" routine (600) to examine the switches 130--130 and 
multiplex the display 152, the accumulator value would be saved for when 
the program returns to the "UPDATE" routine to finish the calculation or 
the like in progress at the time of the interrupt. 
The digit select register R2 is then output at step 502 to the lines 
218C-218F so that the line with the logic "1" level turns on the 
appropriate one of the digit drivers 208-214. At the same time, the 
pointer register R0 causes the corresponding one of the four display 
registers R3C-R3F to output the 7-segment code for that digit. 
At step 503 the timer/counter register 106 (FIG. 3) is set to a preselected 
value so that after the program is in the "UPDATE" routine 600 the 
timer/counter 102 causes the program to return to the "START" routine 
periodically. In other words, the setting of the timer/counter assures 
that scanning of the function select switches and display occur regularly. 
After one of the digits 200-206. (FIG. 1c) is refreshed, the contents of 
the registers R0 and R2 are adjusted (504) so that the next time through 
the "START" routine the next digit on the display 152 will be refreshed. 
This is accomplished by simply rotating the contents of the registers one 
location. Therefore, "1" will appear on the next line 218 and "0"s on the 
other three lines so the next digit driver for the display 152 will be 
activated, and the next display register will output the proper 7-segment 
code for that digit to the circuit 193. 
The input function select switches 130-136 are scanned each time through 
the "START" loop at step 505, and if a new function has been selected 
(506), the timer/counter interrupt function is disabled (508), a "0" is 
placed in the flag F1 and the display 152 is blanked. This assures that 
the information in "UPDATE" relating to the previous function selected 
will not be displayed. The working register R7 then receives a new code 
from the memory 94 corresponding to the function selected at step 509. If 
two or more of the switches 130-136 are depressed, the indicators 232-238 
will remain off. This is accomplished by choosing the initial digit (step 
510) on the basis of the function selected, and when two functions are 
selected, no initial digit can be determined. The display registers 
R3C-R3F are loaded with ones (511) so all segments will be blank 
initially. The MSB is then cleared in the display register corresponding 
to the function selected to cause the proper one of the indicators 232-238 
to be activated. The engine speed monitor 250 is turned off at step 512 by 
disabling the oscillator 260 with a pulse from the PROG pin 288 (FIG. 1b). 
An immediate response is provided when a new function is selected, and a 
correct value is quickly shown on the display, eliminating problems of 
false readings common with prior art devices when the function is changed. 
The block in the flow chart indicated at step 513 assures that if the 
program was interrupted during the "UPDATE" routine and a new function was 
selected by the operator, the program will not return to "UPDATE" during a 
RETURN instruction but will instead go to the "START" routine address 
jammed onto a stack location of the RAM 86. Only the RETURN instruction 
(RETR) can reset an interrupt request flip-flop in the microprocessor 74 
so that the program does not return to the "UPDATE" routine. The 
instructions are fully described in the aforementioned User's Manual. When 
a new function has been selected, all the registers are initialized (514) 
in a similar manner as that described above for the "RESET" routine 400, 
and the "START" routine is begun. 
If during the next pass through the "START" loop (FIG. 4b) no new function 
is indicated at step 506, the pin 140. (T1) is checked (step 515). If T1 
is "0", indicating low ambient light level at the photodiode 146 (FIG. 
1a), the display 152 is dimmed by reducing the duty cycle of each of the 
drivers 208-214 from 25% to 10%. The pin T1 is checked at a point in time 
approximately 40% through the instruction cycles of the "START" loop. If 
T1 is "0", the driver for the digit being refreshed during the loop is 
turned off during the remaining 60% of the instruction cycles. If T1 is 
"1", the digit driver remains on for the entire time it takes to complete 
the loop, which in the preferred embodiment is 165.0 microseconds (2.5 
microseconds per instruction). 
If the program was interrupted by the timer/counter while in the "UPDATE" 
routine 600, indicated by a "1" in the F1 flag checked at step 516, the 
program will return to finish the "UPDATE" routine 600 (517). If the F1 
flag contains a "0", the "START" loop continues with the square wave from 
one of the lines 66-72 corresponding to the function selected being 
sampled at step 518. Next, the F0 flag is checked to see if a window has 
begun in a previous pass through the "START" loop (step 519, FIG. 4c). If 
F1 is a "0" indicating the window has not yet started, the register R6 is 
checked at step 520 to see if the input sampled a rising edge (i.e., a 
transistion from a "0" to a "1" in the R6 register). If there is a rising 
edge, the window is begun (521) and a "1" is stored in the F0 flag. If no 
rising edge is detected, the time out register R27-R28 is incremented 
(522) and, if after a preselected number of passes through the "START" 
routine no rising edge is detected (523), the 9-bit count register (R5+the 
carry bit) is cleared at step 524 (FIG. 4d). In other words, if no rising 
edge is detected after a preselected time, the processor assumes that 
nothing is happening at the input line selected and clears the 9-bit 
falling edge counting register so that a zero value is supplied to the 
immediate value (X.sub.n) register R34-R35 during the "UPDATE routine 600. 
When a rising edge is detected at 520 and the window is begun (521), the 
program makes a number of passes through the "START" loop, each time 
incrementing the 9-bit register at step 526 if a falling edge is detected 
on the square wave input. Each time through the loop the 2-byte window 
register R3-R4 is decremented at step 527 until the window is finished at 
528 (R3-R4=0), at which time the program jumps (529) to the "UPDATE" 
routine 600. 
Delays 530, 531 and 532 are provided in the various paths in the "START" 
routine 500 so that regardless of the path taken, the number of 
instruction cycles, and therefore the time elapsed, will be the same for 
each pass through the loop. In the preferred embodiment there are 66 
instruction cycles in the "START" loop, and one pass takes 165.0 
microseconds. Timing the windows by counting the number of times through 
the "START" loop is more accurate than, for example, performing a timer 
interrupt since it is possible to interrupt on either a one- or a 
two-cycle instruction, providing a one-cycle time uncertainty as to the 
actual length of the window. Syncronizing the start of a window with a 
rising edge of the square wave and counting falling edges eliminates the 
jitter in the least significant digit of the display 152 that would occur 
if a window was begun at random. 
The "UPDATE" routine 600 (FIG. 4d-4f) is entered from the "START" routine 
with a new speed value (X.sub.n) which is compared with the last average 
speed value (A.sub.n-1). If .vertline.X.sub.n -A.sub.n-1 
.vertline..ltoreq.4, corresponding to a change of at least 40 RPM, the new 
value is stored in the average value (A.sub.n) register R32-R33. If 
.vertline.X.sub.n -A.sub.n-1 .vertline.&lt;4, the new average is calculated 
according to equation 1 above and is converted from binary to binary coded 
decimal, and then to 7-segment code which is stored in the display 
registers R3C-R3F read during the "START" routine 500. 
Once in the "UPDATE" routine 600, the flag F1 is loaded with a "1" which 
indicates return to the routine 600 from step 516 of the "START" routine 
is necessary after a timer/counter interrupt. The timer/counter interrupt 
is enabled at step 601 so that the function switches 130-136 will be 
scanned and the display multiplexed regularly. At step 602 the new data 
value X.sub.n, which is the binary representation of the number of falling 
edges counted during a window in the 9-bit register, is stored in the new 
data value register R34-R35. A two's compliment of the binary value of the 
last average value A.sub.n -1 is taken and added to the value X.sub.n 
(steps 603-605), which is equivalent to subtracting A.sub.n-1 from 
X.sub.n. If the absolute value of the difference between the new data 
value X.sub.n and the last average value is 4 or more (606), an immediate 
update counter in the RAM, R26 is loaded at step 607 with the number of 
immediate updates desired, which in the preferred embodiment is six. That 
is, once the difference exceeds the preselected value indicating a sudden 
increase or decrease in speed, the processor will perform six immediate 
updates in which the new data value X.sub.n is entered directly into the 
average value (A.sub.n) register R32-R33 at step 608 without averaging in 
the previous counts. T.sub.n value is calculated and stored at steps 
609-610. After the sixth immediate update after the sudden change occurred 
(611), an average A.sub.n is again computed and stored in register R32-R33 
at steps 612-617. 
When the "UPDATE" routine is not in an immediate update mode, a weighted 
average according to eqn. 1 is computed by first subtracting the previous 
average value A.sub.n-1 in the register R32-R33 from the value in the four 
times average value (T.sub.n) register R36-R37 at step 612: 
EQU (T.sub.n-1)-(A.sub.n-1)=3(A.sub.n-1) Eqn. 2 
The new data value X.sub.n is added and the result is stored in the T.sub.n 
register at steps 613 and 614: 
EQU T.sub.n =(T.sub.n -1)-(A.sub.n -1)+X.sub.n =3(A.sub.n -1)+X.sub.n Eqn. 3 
The T.sub.n value is then divided by four, rounded off and stored in the 
average value (A.sub.n) register R32-R33 at steps 615-617: 
EQU A.sub.n =1/4[X.sub.n +3(A.sub.n -1)] Eqn. 4 
Since A.sub.n -1=1/4[X.sub.n-1 +3(A.sub.n-2)]: 
##EQU1## 
Carrying this out for n samples or windows, Equation 1 is obtained. The 
new data value X.sub.n is averaged with the previous values, but the 
weight given each previous sample is less than that given a subsequent 
sample. More than just a few of the past data values are used in the 
calculation, yielding a smoothly changing, easily readable display, while 
weighting the latest pulse count X.sub.n the heaviest provides a more 
accurate representation of speed. 
After the value A.sub.n is determined at step 608 or 617, it is converted 
to a 7-segment code at step 618 (FIG. 4f) using a standard routine well 
known to those skilled in the art and stored in the display registers 
R3C-R3F. 
After the "UPDATE" routine 600 is complete, an engine speed monitor 
rountine 700, ESPDM (FIG. 4f-h), is initiated to activate the engine speed 
warning lamp 250 (FIG. 1b) if engine speed drops below or rises above 
preselected limits. If engine speed is the function selected (701), the 
accumulator 84 is loaded with the average value A.sub.n at step 702. The 
value in the accumulator is compared with the high and low limit values at 
703 and 704 (FIG. 4h). If engine speed is within the range of the values, 
control is returned to the "START" routine 500 (FIG. 4b). Prior to 
returning, a pulse is sent on the PROG pin to assure that the indicator 
250 is off (705). The timer/counter interrupt is enabled at 706 to assure 
constant scanning and multiplexing, and the registers are initiallized at 
707 as in step 514 described above. The interrupt is then disabled at 708 
and the flag F1 is set to "0" to signify that the program is no longer in 
the "UPDATE" routine (step 709). If the engine speed is not within the 
range, the indicator 250 is turned on at step 710 by sending a pulse on 
the READ pin 290 described above. 
When a function other than engine speed has been selected, the "ESPDM" 
routine 700 counts the number of falling edges on the engine speed signal 
on the line 66 for a single window (FIG. 4f-4g) in a manner generally 
identical to that used with the "START" routine 500, except the time of 
the window is cut in half to minimize the time required for the "ESPDM" 
routine. Therefore each pulse counted on the line 66 represents 20 RPM 
instead of 10. The count is stored in the R5' register at step 720 (FIG. 
4g) and after the window is complete (721-722) is compared with the 
preselected limits at steps 723-725 to provide a pulse on the READ pin if 
engine speed is not within the desired range. If engine speed is within 
the range (725), control is returned to the "START" routine as described 
above. If no rising edge is detected on the engine speed signal after a 
predetermined time (730, FIG. 4g), the lamp 250 is flashed. 
The "ESPDM" routine 700 allows the engine speed to be constantly monitored 
to control the warning lamp 250 regardless of the function selected by the 
switches 130-136. It should be noted that the pulse count provided by the 
"ESPDM" routine in the register R5' is not used to update the display 152 
but merely controls the lamp 250. The display 152 is multiplexed and the 
function switches are scanned at steps 732-737 of the "ESPDM" rountine. 
Having fully described the preferred embodiment, it will be apparent that 
many modifications and variations may be effected without departing from 
the scope of the novel concepts of this invention. Although reference is 
made to a specific microprocessor and flow chart, it will be apparent to 
one skilled in the art that numerous programming methods and techniques 
may be used without departing from the scope of the claims below. Discrete 
components and other forms of large scale integration rather than a 
processor may also be used.