A low noise receiver includes a downconverter configured to receive a radio frequency (RF) signal, the downconverter comprising a switching architecture configured to generate a plurality of output phases based on a respective plurality of local oscillator (LO) signals, a differencing circuit configured to combine the plurality of output phases such that an nth output phase is differenced with an (n+K)th output phase, resulting in gain-added output phases, and a summation filter configured to receive the gain-added output phases and configured to combine the gain-added output phases such that a response of the receiver effectively reduces odd harmonics of the RF signal.

BACKGROUND

Portable communication devices, such as cellular telephones, personal digital assistants (PDAs), WIFI transceivers, and other communication devices transmit and receive communication signal at various frequencies. For efficient communication, the frequency of the transmit and receive signals is many times higher than the baseband information signal that carries the information to be communicated. Therefore, a transceiver must upconvert the transmit signal and downconvert the receive signal.

Usually, one or more mixers are used to upconvert the transmit signal and downconvert the receive signal. In many radio frequency (RF) communication methodologies, and in a quadrature modulation methodology in particular, a mixer can be implemented using a series of switches that switch differential components of a quadrature signal according to a local oscillator (LO) signal. The frequency of the LO signal is chosen so that a radio frequency signal mixed with the LO signal is converted to a desired frequency.

Signal upconversion and signal downconversion is performed by using mixers, which are typically implemented using semiconductor switches. In deep sub-micron technology the availability of passive switches providing low noise operation and highly efficient operating characteristics enables the use of passive mixers where low current consumption and high performance is desired. Rail to rail voltages used in the switch clock path and issues due to poor isolation between the in-phase (I) and quadrature-phase (Q) paths in the mixer impose limitations on the use of a passive mixer.

A SAW filter is typically used to protect the receive frequency band from interfering signals that may be out of the receive band, but that may still cause interference, particularly at certain multiples (harmonics) of the receive frequency. An LNA is typically used to amplify the relatively weak receive signal so that the information contained therein can be extracted. For a multiband receiver, a separate SAW filter is needed for each band, and a separate LNA is needed to accept the output of each SAW filter. Thus SAW filters and LNAs typically add complexity to the receiver architecture. Further, the LNAs consume power, and this power consumption must be sufficiently high to allow the LNAs to pass large blocking signals without compressing small desired signals.

Therefore, it would be desirable to have a low noise receiver architecture that may not rely on these additional elements.

SUMMARY

Embodiments of a low noise receiver include a downconverter configured to receive a radio frequency (RF) signal, the downconverter comprising a switching architecture configured to generate a plurality of output phases based on a respective plurality of local oscillator (LO) signals, a differencing circuit configured to combine the plurality of output phases such that an nth output phase is differenced with an (n+K)th output phase, resulting in gain-added output phases, and a summation filter configured to receive the gain-added output phases and configured to combine the gain-added output phases such that a response of the receiver effectively reduces odd harmonics of the RF signal.

DETAILED DESCRIPTION

Although described with particular reference to a portable transceiver, the SAW-less, LNA-less low noise receiver (also referred to herein as the low noise receiver), can be used in any device that uses signal downconversion in a receiver.

For a quad-band communication device operating in the GSM/EDGE frequency spectrum, the low noise receiver described herein eliminates four external SAW filters and on-chip low noise amplifiers (LNAs) that are typically used in quad-band cell phone solutions, leading to large cost and area savings. The elimination of the SAW filters and LNAs is achieved, at least in part, by implementing the highly linear, low noise, passive, mixer architecture mentioned above, and partly by the careful design of input and output matching circuitry.

The low noise receiver can be implemented in hardware, or a combination of hardware and software. When implemented in hardware, the passive mixer and high Q RF filter using a passive mixer can be implemented using specialized hardware elements and logic. When the low noise receiver is implemented partially in software, the software portion can be used to precisely control the various components. The software can be stored in a memory and executed by a suitable instruction execution system (microprocessor). The hardware implementation of the low noise receiver can include any or a combination of the following technologies, which are all well known in the art: discrete electronic components, a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit having appropriate logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), etc.

The software for low noise receiver comprises an ordered listing of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.

FIG. 1is a block diagram illustrating a simplified portable transceiver100. Embodiments of the low noise receiver can be implemented in any RF receiver, RF transmitter or RF transceiver, and in this example, are implemented in an RF receiver120associated with a portable transceiver100. The portable transceiver100illustrated inFIG. 1is intended to be a simplified example and to illustrate one of many possible applications in which the low noise receiver can be implemented. One having ordinary skill in the art will understand the operation of a portable transceiver. The portable transceiver100includes a transmitter110, a receiver120, a baseband subsystem130, a digital-to-analog converter (DAC)160and an analog-to-digital converter (ADC)170. The transmitter110includes a modulator116and an upconverter117. In an embodiment, the upconverter117can be a subsystem of the modulator116. In alternative embodiments, the upconverter117can be a separate circuit block or circuit element.

The transmitter also includes any other functional elements that modulate and upconvert a baseband signal. The receiver120includes filter circuitry and a downconverter200that enable the recovery of the information signal from the received RF signal. The downconverter200implements portions of and embodiments of the low noise receiver, as described herein.

The portable transceiver100also includes a power amplifier140. The output of the transmitter110is provided over connection112to the power amplifier140. Depending on the communication methodology, the portable transceiver may also include a power amplifier control element (not shown).

The receiver120and the power amplifier140are connected to a front end module144. The front end module144can be a duplexer, a diplexer, or any element that separates the transmit signal from the receive signal. The front end module144also contains appropriate band switching devices to control the application of a received signal to the receiver120. The front end module144is connected to an antenna138over connection142.

In transmit mode, the output of the power amplifier140is provided to the front end module144over connection114. In receive mode, the front end module144provides a receive signal to the receiver120over connection146.

If portions of the low noise receiver are implemented in software, then the baseband subsystem130also includes receiver software155that can be executed by a microprocessor135, or by another processor, to control at least some of the operation of the low noise receiver to be described below.

When transmitting, the baseband transmit signal is provided from the baseband subsystem130over connection132to the DAC160. The DAC160converts the digital baseband transmit signal to an analog signal that is supplied to the transmitter110over connection134. The modulator116and the upconverter117modulate and upconvert the analog transmit signal according to the modulation format prescribed by the system in which the portable transceiver100is operating. The modulated and upconverted transmit signal is then supplied to the power amplifier140over connection112.

When receiving, the filtered and downconverted receive signal is supplied from the receiver120to the ADC170over connection136. The ADC digitizes the analog receive signal and provides the analog baseband receive signal to the baseband subsystem130over connection138. The baseband subsystem130recovers the received information.

FIG. 2is a schematic diagram of an embodiment of a known single-ended voltage-mode downconverter implemented as a passive mixer using an approximate 25% duty cycle topology. A passive mixer is an example of an implementation of the downconverter200ofFIG. 1. Although voltage mode operation is illustrated in the embodiment shown inFIG. 2, a current mode implementation can also be used.FIG. 2illustrates an example of utilizing 25% duty cycle LO signals to control the mixer switching. In practice less than 25% duty cycle might be desirable to prevent overlap between the on-times of the switches.

In a voltage mode mixer implementation, such as shown inFIG. 2, reducing the duty cycle to 20% or below is possible, but it also quickly reaches the point of diminishing returns where noise contributions due to aliasing of undesired input signals or noise around harmonics of the LO frequency degrade performance. Duty cycle between 20-25% is chosen in this implementation. In the topology shown inFIG. 2, LO and 2LO multiplication (described in greater detail inFIG. 3) is done in the LO path rather than the RF path.

The voltage signal on connection146is provided to switches222,224,226and228. The switches222,224,226and228can be implemented using any switch technology such as, for example, bipolar junction transistor (BJT) technology, field effect transistor (FET) technology, or any other switching technology. The switches222,224,226and228can also be implemented using pass gates, each of which are typically implemented by a combination of an NFET and PFET transistor, as known in the art. The switches222,224,226and228are illustrated inFIG. 2as simple single-pole single-throw switches to illustrate that any type of switches can be used to generate the switching signals described herein.

In the embodiment described herein, the in-phase (I) and quadrature-phase (Q) signals are differential. Therefore, the I signal includes a VI+signal and a VI−signal. Similarly, the Q signal includes a VQ+signal and a VQ−signal. The switch222generates the I+ signal, the switch224generates the I− signal, the switch226generates the Q+ signal and the switch228generates the Q− signal. The clock signals that drive the switches222,224,226and228are illustrated as having a 25% duty cycle and can be generated as will be described below. The clock signal232drives the switch222, the clock signal234drives the switch226, the clock signal236drives the switch224and the clock signal238drives the switch228. In accordance with providing an approximate 25% duty cycle topology, none of the clock signals232through238have any time period during which they overlap, or which are positive at the same time.

The output of the switch222is terminated by a capacitance256and a resistance257, and is provided to one input of the amplifier252. The output of the switch224is terminated by a capacitance258and a resistance259, and is provided to the other input of the amplifier252. The output of the switch226is terminated by a capacitance266and a resistance267, and is provided to one input of the amplifier262. The output of the switch228is terminated by a capacitance268and a resistance269, and is provided to the other input of the amplifier262. The output of the amplifier252on connection254is the differential VI+and VI−output signal; and the output of the amplifier262on connection264is the differential VQ+and VQ−output signal.

FIG. 3is a graphical illustration showing the LO signals utilized by an embodiment of the passive mixer200described inFIG. 2. The in-phase LO signal includes differential components LO_I andLO_I. The quadrature-phase LO signal includes differential components LO_Q andLO_Q. The 2LO signal is an LO signal that occurs at twice the frequency of the I and Q LO signals. The inverse of the 2LO signal is referred to as2LO.

The 2LO signal is shown at trace302, the LO_I signal is shown at trace304, and theLO_Isignal is shown as trace305. The LO_Q signal is shown at trace306and theLO_Qsignal is shown as trace307. These five signals are combined as follows to generate the four LO waveforms that are applied to the downconverter200.

The 2LO*LO_I signal is shown at trace308. The signal308represents the LO_I+ signal. The 2LO*LO_Isignal is shown at trace312. The signal312represents the LO_I− signal. The2LO*LO_Q signal is shown at trace314. The signal314represents the LO_Q+ signal. The2LO*LO_Qsignal is shown at trace316. The signal316represents the LO_Q− signal.

The effective in-phase differential LO signal, eLO_I, is shown as trace318and the effective quadrature-phase differential LO signal, eLO_Q, is shown as trace322. These signals are derived respectively as LO_I+−LO_I− and LO_Q+−LO_Q−. As shown inFIG. 3, the effective in-phase differential LO signal, eLO_I,318and the effective quadrature-phase differential LO signal, eLO_Q,322provide an approximate 25% duty cycle at each polarity and ensure that switching takes place only on the transitions of the 2LO signal302, thus minimizing any influence of switching noise, and minimizing any I and Q signal overlap due to the LO_I signal304and the LO_Q signal306. The trace326is a continuous-wave example showing the sampling of an RF input signal by the I+ signal328, the Q+ signal332, the I− signal334and the Q− signal336.

FIG. 4is a schematic diagram illustrating an embodiment of a low noise receiver400. According to the 3GPP standard, the low noise receiver400should be able to demodulate a desired signal at strength of approximately −99 dBm, in the presence of a 0 dBm out-of-band non-spurious blocker at greater than 20 MHz offset from the desired receive frequency, or in the presence of a −43 dBm out-of-band spurious blocker, such as one that may occur at a harmonic of the desired receive frequency.

The low noise receiver400receives a signal from an antenna138that supplies the received signal to a front end module144. The front end module144comprises, in this example, an antenna filter402that supplies the filtered signal to a transmit receive (T/R) switch module404. In the embodiment shown inFIG. 4, the T/R switch module404is a single pole four-throw (SPFT) switch that switches transmit high band, transmit low band (circuitry not shown for simplicity); and receive high band and receive low band. In this quad-band example, the transmit receive switch module404can be implemented using any type of switches as known in the art.

The receive signal is provided from the appropriate switch element within the T/R switch module404to a low pass filter module410. In the embodiment shown inFIG. 4, the low pass filter module410includes circuitry for both the receive low band and the receive high band. The low pass filter module410operates as a harmonic reject filter, and as an impedance matching network. The low pass filter module410attenuates out of band blocking signals that may occur at an odd harmonic, for example the third and fifth harmonic, of the desired receive frequency; and also provides impedance matching from the T/R switch module404to the input of the downconverter200. In an embodiment, the inductors412and417can have a value of 10 nanohenrys (nH) and the capacitors414and416can have a value of 3.0 picofarads (pF); and the inductors418and422can have a value of 3.3 nH and the capacitors419and421can have a value of 1.5 pF.

The low band filter circuitry comprises an inductor412, a capacitor414, an inductor417and a capacitor416. Similarly, the high band filter circuitry comprises an inductor418, a capacitor419, an inductor422and a capacitor421. In an embodiment, the low pass filter module410provides impedance matching from the relatively low impedance source to the relatively high impedance load and in the process, provides a voltage gain by acting as a step-up transformer, as known in the art. As an example, the input of the low pass module410has an impedance of approximately 50Ω, which should be matched to the approximate 400Ω impedance at the input to the downconverter200. A filter network providing such a match will step up the voltage by SQRT(400/50), which in dB is 20*log (SQRT(400/50))=9 dB.

The low noise receiver400also includes an embodiment of the downconverter200shown inFIG. 2. In the example shown inFIG. 4, the downconverter200is a two band low noise passive mixer comprising transistor switches424,426,427and428for the low band and transistor switches429,431,432and434for the high band. Only the high band or low band switches are employed at a time, according to the band of operation. According to this embodiment, the transistor switches424,426,427, and428, or the transistor switches429,431,432, and434, are switched according to a 25% local oscillator (LO) duty cycle, with the LO waveforms and their phases as described inFIGS. 2 and 3. According to this operation, no two transistor switches in either of the high band or low band segments of the downconverter200will be operating at the same instant.

The 25% duty cycle LO drive for the transistor switches424,426,427, and428, or the transistor switches429,431,432, and434, provides isolation between the I and Q baseband outputs on the capacitors, CLofFIG. 4, by connecting only one of the capacitors to the single-ended RF input at any given instant. This prevents charge sharing between I and Q capacitors, enhancing mixer gain, noise figure (NF) and the quality factor (Q) of the band pass filtering response at the RF input of the downconverter200. Single-ended to differential conversion in this voltage mode sample-and-hold topology has the advantage of approximately 6 dB of additional voltage gain. It can be shown that the gain in this topology approaches 5.1 dB due to the sample/hold mixer operation and single-ended to differential downconversion. Additional gain due to impedance step-up from approximately 50 ohm (Ω) to approximately 400Ω in the low pass filter410enhances the total gain to approximately 14.1 dB from antenna input to passive mixer output. It is noteworthy that this mixer gain is achieved without any active stages or bias current in the signal path. It should also be noted that this front-end design may benefit greatly from future technology scaling, as performance of the passive switches and mixer LO generation circuitry improves at lower gate lengths.

The output of the downconverter200is supplied to a resistive/capacitive (RC) filter network436. Specifically, the output of the transistor424or429is supplied to resistor437and capacitor438. The output of transistor426or431is supplied to resistor439and capacitor441. The output of transistor427or transistor432is supplied to resistor442and capacitor444, and the output of transistor428or transistor434is supplied to resistor446and capacitor447.

The following description will be made with particular reference to the output of the transistor424and the filter network comprising resistor437and capacitor438and the output of the transistor426and the filter network comprising resistor439and capacitor441as an example only. The balance of the circuit performs in the same manner. The capacitor438performs a sample-and-hold function and performs single-ended to differential conversion for the signal output from the transistor424. Each time the transistor424is conductive for the period of time corresponding to the 25% duty cycle described above, the output of transistor424is stored on capacitor438to provide the sample-and-hold function. Then, with example reference to the in-phase signal, the differential conversion is performed by the capacitor438and the capacitor441. The capacitor438charges during the interval328(FIG. 3) and the capacitor441charges during the interval334(FIG. 3). Then, these outputs are differenced, resulting in a 2× magnitude because the signals are of opposite polarity. As an example, the value of the combined signals is approximately 6 dB.

The resistors437and439provide a common-mode voltage (Vcm) because a non-zero common-mode voltage is used in a differential system that uses a single supply voltage. The parallel combination of the capacitor438, resistor437and the resistance through the transistor424forms an RC low pass filter. In an embodiment these element values are chosen to provide an RC low pass filter bandwidth of +/−1 MHz. It is this low pass filter response that is reflected through the downconverter200that causes a 2 MHz wide RF band pass response to appear at the input to the downconverter200, as is illustrated inFIG. 5.

The output of the RC network436is then supplied to a high gain trans-admittance amplifier450. In this embodiment, the low noise receiver comprises four instances of the high gain trans-admittance amplifier450. The high gain trans-admittance amplifier450includes a current source452, a transistor454and a resistor456configured to receive an output of the resistor437and capacitor438. Similarly the output of the resistor439and capacitor441is supplied to a high gain trans-admittance amplifier comprising current source457, transistor device458and resistor459. Similarly, the output of the resistor442and the capacitor444is supplied to a high gain trans-admittance amplifier comprising current source461, transistor462and resistor464. Finally, the output of the resistor446and the capacitor447is supplied to a high gain trans-admittance amplifier comprising current source466, transistor467and resistor468. In an embodiment, the downconverter200and the high gain trans-admittance amplifier450can operate from a 1.2V regulated supply.

The output of the high gain trans-admittance amplifier450is provided to an RC lowpass filter470. The RC lowpass filter470comprises resistor471, capacitor472and resistor474. The RC lowpass filter470also comprises resistor476, capacitor477, and resistor478.

The output of the RC lowpass filter470is provided to a filter480, comprising amplifier481and related resistors (R1and R2) and capacitors (C1and C2), and amplifier491and related resistors (R1and R2) and capacitors (C1and C2). The filters470and480are not completely independent and affect each other due to loading at their interface. The composite characteristics of the filters470and480can be adjusted using resistors471,476, capacitors472and477, resistor R1, resistor R2, capacitor C1and capacitor C2to obtain a desired filter response. The overall receiver gain can be scaled using resistors456,459,464and468or adjusting resistors471and476, capacitors472and477, resistor R1, resistor R2, capacitor C1and capacitor C2. The concept is not limited to the use of the particular active filter topology shown; other topologies may be used including other op-amp-based active filter topologies as well as passive RC filters.

The output voltage of the filter480is provided to an analog-to-digital converter (ADC)490. The output voltage of the amplifier481is provided to the ADC492, and the output voltage of the amplifier491is provided to the ADC494. The digital output of the ADC490is provided to the baseband subsystem130.

FIG. 5is a graphical illustration500showing an example frequency spectrum within which the low noise receiver operates. The abscissa502represents frequency and the ordinate504represents signal level. The region506illustrates the receive frequency range from 925 MHz to 960 MHz. The region506also illustrates the filter region that would be provided by a SAW filter if a SAW filter were present in the system. The signal508represents the desired signal and the region512depicts a 2 MHz wide frequency response covering region518, centered at the desired receive frequency (tuning frequency516) that is provided by the operation of the downconverter200. In an embodiment, the downconverter200can be referred to as a “filtering mixer.”

An out-of-band blocking signal, also referred to as an out-of-band interfering signal, is depicted inFIG. 5using reference numeral522. In this example, the out-of-band blocking signal522is approximately 20 MHz higher in frequency than the upper frequency range of 960 MHz. The downconverter200exhibits the frequency response512, thereby passing signals within frequency range 518, and substantially rejecting signals outside frequency range 518, thereby preventing out-of-band blocking signals from interfering with the desired signal508. The frequency response512is a band pass response with very high Q around the tuning frequency516(the frequency of the LO (fLO)) having a 3 dB bandwidth of 2 MHz centered at the tuning frequency516. This high Q band pass response is established by the low pass pole due to capacitor438and resistor437ofFIG. 4(for example, CLand RB,) being effectively reflected through the transistors in the downconverter200to present a band pass pole centered on the LO frequency at the downconverter input. For higher offsets around LO, a 20 dB/decade drop in input impedance is observed, until the response reaches a floor that is determined by the finite on resistance of the passive switches used in the downconverter200. By means of this high Q filter at the downconverter input, a 20 MHz blocker in the GSM 950 MHz band is attenuated by more than 12 dB.

As the local oscillator frequency applied to the downconverter200ofFIG. 4changes, the 2 MHz wide region512will shift with the tuning frequency516. Any channel to which the receiver400is tuned will have this 2 MHz wide filter region around the tuning frequency516, thus eliminating any out-of-band (beyond 2 MHz) blocking signals. This eliminates the need for the SAW filter at the input to the low noise receiver400.

This ‘tracking filter” operation together with the low noise provided by the downconverter200allows the elimination of a low noise amplifier, as shown inFIG. 4where the front end module144is connected directly to the low pass filter410at the input to the downconverter200. The 25% duty cycle LO, derived by the LO 2LO method described inFIG. 3, applied to the downconverter200, providing non-overlapping downconverter phases as shown inFIG. 3, allows approximately 6 dB voltage gain to be provided by the downconverter200, thus further justifying the omission of a low noise amplifier between the front end module144and the low pass filter410.

However, if the out-of-band blocking signal522occurs at a frequency that is either three or five times the tuning frequency516of the desired signal508(commonly referred to as the third or fifth harmonic of the fundamental frequency), then, through a phenomenon referred to as mixer aliasing, the full amplitude of the out-of-band blocking signal522would be superimposed over the desired signal508, thus degrading receiver sensitivity at the tuning frequency516.

In order to prevent an out-of-band blocking signal522that may occur at an odd harmonic, for example, the third or fifth harmonic, of the desired signal508from interfering with the desired signal508, the low pass filter410(FIG. 4) is implemented to reduce receiver sensitivity at the third and fifth harmonic frequency of the desired signal508. The total number of matching components used in the low pass filter410is less than or equal to that used in typical quad-band receiver matching circuits. A simple fourth order filter provides more than 30 dB rejection for the unwanted components at three or five times the desired receive frequency. By appropriate choice of components, this rejection can be increased to more than 65 dB by the utilization of component self-resonances.

Further, as will be described below inFIG. 7, taking advantage of the output phases available from the downconverter200, the phases can be summed in order to further attenuate out-of-band blocking signals occurring predominately at odd harmonics, for example, at the third and fifth harmonics, of the desired signal.

FIG. 6is a schematic diagram illustrating an alternative embodiment of the low noise receiver ofFIG. 4. Elements inFIG. 6that are similar to elements inFIG. 4will be numbered using the convention 6XX, where the “XX” inFIG. 6refers to a similar element inFIG. 4. Further, some of the reference numerals inFIG. 6are not shown for simplicity. The low noise receiver600is similar to the low noise receiver400, except that the embodiment ofFIG. 6shows an exemplary baseband filter implementation where the output current from the baseband V-I conversion stage provided by a high gain trans-admittance amplifier650is applied directly to the virtual ground of a continuous time ADC690, comprising ADC elements692and694, after passive low pass filtering in the RC lowpass filter670.

FIG. 7is a schematic diagram illustrating another alternative embodiment of the low noise receiver ofFIG. 4. The embodiment of the low noise receiver ofFIG. 7illustrates only one band (the low band) and shows an example of generating eight (8) output phases of the downconverter200. Additional attenuation of out-of-band blocking signals that may occur at odd harmonics, for example at the third and fifth harmonics of the desired receive frequency, can be obtained by taking advantage of the output phases available from the downconverter200. The output phases from the downconverter200can be summed in order to further attenuate out-of-band blocking signals at, for example, the third and fifth harmonics of the desired signal.

The embodiment of the low noise receiver700illustrates only the low band for simplicity of illustration. The low noise receiver700includes an implementation of a downconverter200shown using simple switches instead of transistor devices and illustrates only the low band (LB) signal chain for simplicity. The LO drive signals for the switches are shown using the graphical illustration750. The embodiment of the downconverter715includes 2K taps, taking a total of 2K samples per complete cycle of the LO frequency. In a general 2K tap downconverter715, the duty cycle of each LO waveform is less than LO/2K. The gain of the downconverter715approaches 0 dB as K increases. For the case of a single-ended downconverter, the gain approaches 6 dB from the combination of single-ended to differential conversion and the sample and hold (S/H) operation described above. Any voltage step-up in the low pass filter module710provides additional gain, as discussed above.

The 2K tap implementation where K is 4, 8, 16, etc., allows configurations where harmonics of the input RF frequency can be rejected by simple weighted summation of the outputs of the downconverter715. An example of the summation of three output phases that provide a waveform that carries no third or fifth harmonics is described inFIG. 8.

The signal from the low pass filter module710is provided to downconverter715which is shown for simplicity as an array of switches. Each switch is shown with the designation of the LO waveform750that drives it (LO_0through LO_(2K−1)). In the general implementation shown inFIG. 7, 2K switches (LO_0through LO_(2K−1)) are used in the signal path, each switch having a duty cycle≦(100/2K) %. The period of the LO frequency is T, and each LO waveform exhibits an active pulse width of T/2K. The implementation discussed in this example is a specific case for K=4, so each LO waveform750exhibits an active pulse width of T/8. However, any number K of baseband outputs could be used in receiver topologies depending on application. As the number K increases, the sample-and-hold gain approaches 0 dB. For example, a 3rdand 5thharmonic rejection receiver architecture might use K=4 to generate the 0, 45, 90, 135, 180, 225, 270 and 315 degree samples of the RF waveform. The outputs denoted by V(0), V(1), . . . V(2K−1) inFIG. 7, for the case of K=4, correspond to the 0, 45, 90, 135, 180, 225, 270 and 315 degree samples, respectively. The outputs V(0), V(1), . . . V(2K−1) are grouped in pairs where each pair comprises outputs differing in phase by 180 degrees. For instance, the difference of V(0) and V(K), the difference of V(1) and V(K+1), and the difference of V(K−1) and V(2K−1). The difference of each of these pairs is then determined by a respective difference amplifier785-1through785-K. Difference amplifiers785-1through785-K may also include low pass filters, as described inFIG. 4as filters480. Since the signals being differenced are 180 degrees out of phase, 6 dB gain is achieved. In the specific case for K=4, the resulting outputs of difference amplifiers785-1through785-K represent gain-added phases of the received signal at 0, 45, 90, and 135 degrees with the added 6 dB gain. The outputs of difference amplifiers785-1through785-K are applied to ADCs790-1through790-K. Outputs of ADCs790-1through790-K are then applied to baseband system130. Within baseband system130, harmonic rejection summing can be implemented using weighted summations of these multiple phases, as will be described below.

The technique shown inFIG. 7is an effective way of splitting the RF signal in the time domain into K separate paths without adding extra circuit blocks that could severely degrade performance or increase power consumption and die area.

FIG. 8illustrates a known method of generating a waveform in which 3rdand 5thharmonics are rejected.FIG. 8shows only the signals relating to the in-phase (I) signal. For simplicity, the example inFIG. 8shows an example of the summation of three output phases that provide a waveform that carries no third or fifth harmonics. Other numbers of output phases can be combined to achieve a similar output waveform.

The waveform820represents the fundamental LO signal according to the equation:

The waveform810represents the fundamental LO signal820advanced 45 degrees relative to the signal820. Signal810is represented according to the equation:

The waveform830represents the fundamental LO signal820retarded by 45 degrees relative to signal820. Signal830is represented according to the equation:

The waveform840represents the combination of the above three waveforms in the appropriate proportions such that the third and fifth harmonics of the fundamental LO signal820are rejected. The combination is formed according to the equation:
LO_harm_rej(t)=√{square root over (2)}U1(t)+U2(t)+U3(t)

Returning now toFIG. 7, the effective LO outputs of the downconverter715can be combined as generally described above with respect toFIG. 8, and as will be described below inFIG. 10for the case of eight output phases, to provide additional harmonic rejection, which further simplifies the requirements for the low pass filter410(FIG. 4). For K=4, a downconverter configuration is obtained that provides third and fifth harmonic rejection, allowing the receiver to reject input signals at three times and five times the desired RF signal.

FIG. 9is a graphical illustration showing the eight LO phases utilized by the low noise receiver ofFIG. 7for the case of K=4. The trace902shows a 4LO waveform with 50% duty cycle. The traces904and906show two quadrature phases of 2LO, respectively referred to as 2LO_I and 2LO_Q. The traces908and912show two 45 degree offset phases of LO, respectively referred to as LO_I and LO_Q. The signals represented by the traces902,904,906,908and912are multiplied in the eight combinations shown by traces922,924,926,928,932,934,936and938to produce eight respective LO waveforms, referred to as LO_0, LO_4, LO_1, LO_5, LO_2, LO_6, LO_3and LO_7, each of which exhibits a ⅛ duty cycle.

FIG. 10is a graphical illustration showing the effective quadrature LO waveforms, each with 3rdand 5thharmonics rejected, that are generated by weighted combining of the eight LO phases utilized by the low noise receiver ofFIG. 7for the case of k=4.

InFIG. 10, the eight ⅛-duty-cucle waveforms LO_0through LO_7, shown respectively by traces922,924,926,928,932,934,936and938are combined in the baseband subsystem130in the appropriate proportions to form effective quadrature waveforms eLO_I1002and eLO_Q1004, as will be further illustrated inFIG. 11andFIG. 13. The waveforms eLO_I1002and eLO_Q1004exhibit the same harmonic-rejecting characteristic shape for a signal having eight combined output phases as that shown by trace840inFIG. 8for a combination of three output phases.

Suppression of harmonics greater than the fifth harmonic can be achieved by increasing the number of output phases. For example, using 16 output phases and the proper choice of weighting coefficients, a frequency response suppressing the 3rd, 5th, 7th, 9th, 11th, and 13th, harmonics could be achieved. Such a response would look similar to the plot1220(FIG. 12), extended out to 16 GHz, with big lobes only at 1 GHz and 15 GHz. In such a case the waveforms eLO_I and eLO_Q would exhibit a finer-toothed quantization compared to the plots1002and1004inFIG. 10. As the number of output phases further increases toward infinity, eLO_I and eLO_Q would become pure sine waves, which contain no harmonics at all.

FIG. 11is a schematic diagram illustrating an embodiment of a low noise receiver that implements the effective quadrature LO waveforms ofFIG. 10. The low noise receiver1100is an alternative embodiment of the low noise receiver700ofFIG. 7and combines the effective quadrature LO waveforms ofFIG. 10to provide additional rejection of 3rd and 5thharmonics at the input of the downconverter. The switches that comprise the downconverter1115are controlled by the 8 LO phases shown by traces922,924,926,928,932,934,936and938inFIG. 9. The embodiment shown inFIG. 11includes 8 phases of the LO signal, and as such, the 8 LO signals are represented as LO_0through LO_7, as shown in the graphical illustration1150.

Combining the eight LO phases to provide additional rejection of the 3rdand 5thharmonics occurs in two parts: The first combining of the 8 LO phases occurs in the analog domain using analog difference amplifiers1185-1,1185-2,1185-3and1185-4. Every nth sample of the received signal is differenced with the (n+4)th sample by the respective analog difference amplifiers1185. The LO_0signal is combined with the LO_4signal by the analog difference amplifier1185-1. The LO_1signal is combined with the LO_5signal by the analog difference amplifier1185-2. The LO_2signal is combined with the LO_6signal by the analog difference amplifier1185-3. The LO_3signal is combined with the LO_7signal by the analog difference amplifier1185-4. The respective outputs of the analog difference amplifiers1185-1through1185-4represent phases of the received signal at 0, 45, 90 and 135 degrees with an approximate 6 dB added gain, as described above inFIG. 7.

The outputs of the analog difference amplifiers1185are converted to the digital domain by respective ADC elements1190. The output of the analog difference amplifier1185-1is supplied to the ADC1190-1. The output of the analog difference amplifier1185-2is supplied to the ADC1190-2. The output of the analog difference amplifier1185-3is supplied to the ADC1190-3. The output of the analog difference amplifier1185-4is supplied to the ADC1190-4.

The second combining of the eight LO phases occurs in the digital domain using a digital summation harmonic reject filter1125, which can be implemented in hardware, software, or a combination of hardware and software. In an embodiment, the digital summation harmonic reject filter1125is part of the operation of the receiver software155and is executed by the processor135. The receiver software155performs a summation represented by summation elements1130and1132. The output of the ADC1190-1is provided to multiplying element1142and to the multiplying element1144. The output of the ADC1190-2is provided to multiplying element1146and to the multiplying element1148. The output of the ADC1190-3is provided to multiplying element1152and to the multiplying element1154. The output of the ADC1190-4is provided to multiplying element1156and to the multiplying element1158. Each multiplying element digitally amplifies the signal passing though it by its respective weighting factor shown inFIG. 11. For example, the output of ADC1190-1is digitally amplified by multiplying element1142by a factor of 1+√{square root over (2)}/2. The summation of the weighted signals is performed in the summation elements1130and1132, resulting in baseband outputs I and Q. Importantly, the switches in the downconverter1115do not interfere with one another due to the non-overlapping LO signals that drive them. Further, the summation performed by the summation elements1130and1132is done at baseband, but has the effect of rejecting harmonics, particularly 3rdand 5thharmonics, at RF. Therefore the baseband outputs I and Q represent a faithful reproduction of the baseband signals carried on the desired RF carrier to which the receiver is tuned, without any substantial interference due to the presence of undesired RF blocking signals that may exist at the 3rdand 5thharmonics of the desired RF carrier.

FIG. 12is a graphical illustration showing an example of the frequency response of embodiments of the low noise receiver. The example inFIG. 12shows the response for a 1 GHz receive signal. The plot1210illustrates the effective response of the switching and summing actions of downconverter200ofFIG. 4, for which K=2. Plot1210does not include the effect of LC harmonic rejection filter410. In plot1210the even harmonics are rejected but the odd harmonics remain. Thus, the LC harmonic rejection filter410inFIG. 4must provide all the attenuation of the 3rd, 5th, and 7thharmonics.

The plot1220illustrates the effective response of the switching and summing actions of the low noise receiver1100ofFIG. 11, for which K=4. Plot1220does not include the effect of any LC antenna filter. In this case, the 3rdand 5thharmonics are greatly rejected due to the 8-phase switching and the harmonic-rejection summation, leaving only the 7thharmonic. Thus, when an LC antenna filter is added to the system ofFIG. 11such LC antenna filter need only reject the 7thharmonic, which is far easier than rejecting the 3rdand 5thharmonics as described above.

FIG. 13is a schematic diagram illustrating an alternative embodiment of the low noise receiver ofFIG. 11. The embodiment1300shown inFIG. 13shows analog summation of the LO signals, LO_0through LO_7described inFIG. 10for the case of K=4. The switches that comprise the downconverter1315are controlled by the 8 LO phases shown by traces922,924,926,928,932,934,936and938inFIG. 9. The embodiment shown inFIG. 13includes 8 phases of the LO signal, and as such, the 8 LO signals are represented as LO_0through LO_7, as shown in the graphical illustration1350.

Combining the eight LO phases occurs in two parts. The first combining of the 8 LO phases occurs in the analog domain using analog difference amplifiers1385-1,1385-2,1385-3and1385-4. Every nth sample of the received signal is differenced with the (n+4)th sample by the analog difference amplifiers1385. The LO_0signal is combined with the LO_4signal by the analog difference amplifier1385-1. The LO_1signal is combined with the LO_5signal by the analog difference amplifier1385-2. The LO_2signal is combined with the LO_6signal by the analog difference amplifier1385-3. The LO_3signal is combined with the LO_7signal by the analog difference amplifier1385-4.

In this embodiment, the second combining of the eight LO phases also occurs in the analog domain in an analog summation reject filter1325. The filter1325performs a summation using summation elements1330and1332. The output of the analog difference amplifier1385-1is provided to amplifier1342and to the amplifier1344. The output of the analog difference amplifier1385-2is provided to amplifier1346and to the amplifier1348. The output of the analog difference amplifier1385-3is provided to amplifier1352and to the amplifier1354. The output of the analog difference amplifier1385-4is provided to amplifier1356and to the amplifier1358. Each amplifier1342,1344,1346,1348,1352,1354,1356and1358amplifies the signal passing though it by its respective weighting factor shown inFIG. 13. For example, the output of analog difference amplifier1385-1is amplified by amplifier1342by a factor of 1+√{square root over (2)}/2. The summation of the weighted signals is performed in the summation elements1330and1332, resulting in analog I and Q signals. Importantly, the switches in the downconverter1315do not interfere with one another due to the non-overlapping LO signals that drive them.

Further, the summation performed by the summation elements1330and1332is done at baseband, but has the effect of rejection of harmonics at RF. Therefore the baseband outputs I and Q represent a faithful reproduction of the baseband signals carried on the desired RF carrier to which the receiver is tuned, without any substantial interference due to the presence of undesired RF blocking signals that may exist at the 3rdand 5thharmonics of said desired RF carrier.

The in-phase output of the summing element1330is provided to an ADC1395for conversion to the digital domain. The quadrature-phase output of the summing element1332is provided to an ADC1396for conversion to the digital domain. The digital in-phase signal and the digital quadrature-phase signal are then provided to the baseband subsystem130(FIG. 1) for further processing.

Typical rejection for harmonics of the desired signal frequency, with harmonic rejection summation performed in the analog domain as shown inFIG. 13, is limited to approximately 35 dB to 40 dB, due to analog component tolerances, while the digital implementation shown in FIG. andFIG. 11can achieve greater than 40 dB rejection since the only analog tolerances remaining in the implementation ofFIG. 11are those of the sampling capacitors, difference amplifiers and ADCs. Proportional summation in the digital domain, as shown inFIG. 11potentially allows for implementation of least mean squares (LMS) based algorithms that can maximize the rejection at n times the desired signal by further compensating for any analog mismatches in the various paths.

FIGS. 14A through 14Dare graphical illustrations showing an example frequency response of an embodiment of the low noise receiver ofFIG. 11orFIG. 13, with the addition of a low pass filter module between the antenna and the input to the downconverter, operating with a receive frequency of 1 GHz.FIG. 14Aillustrates an example response of a 4th-order low pass filter module410. In this example the filter is designed with a wide bandwidth and gentle slope, as it is required to provide rejection only at the 7thharmonic, and not the 3rdor 5thharmonic.FIG. 14Bshows the 2 MHz-wide passband at 1 GHz (caused by the switching and the RC), plus all the unwanted similar responses that occur at harmonics due to aliasing.FIG. 14Cshows the response formed by the harmonic-rejection summation ofFIG. 11orFIG. 13.FIG. 14Dshows the cascaded response ofFIGS. 14A,14B and14C. In the cascaded response ofFIG. 14Dis shown the desirable characteristics of the 2 MHz-wide response that tracks the receiver's tuned frequency, with similar responses rejected at the 3rdand 5thharmonics, and substantially suppressed at the 7thharmonic.

While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of the invention. For example, the invention is not limited to a specific type of radio receiver or transceiver. Embodiments of the invention are applicable to different types of radio receivers and transceivers and are applicable to any receiver that downconverts or filters a received signal.