Structure and method to reduce shorting in STT-MRAM device

A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode.

BACKGROUND

The present invention relates to spin-transfer torque magnetoresistive random access memory (STT-MRAM devices), and more specifically, to stack structures and etch processes in STT-MRAM devices.

STT-MRAM devices have some benefits over semiconductor-based memories, such as dynamic random-access memory (DRAM) and static random-access memory (SRAM). However, in order to compete with DRAM and SRAM, the STT-MRAM devices are integrated into the wiring layers of standard silicon logic and memory chips.

A STT-MRAM device is a type of solid state, non-volatile memory that uses tunneling magnetoresistance (TMR or MR) to store information. MRAM includes an electrically connected array of magnetoresistive memory elements, referred to as magnetic tunnel junctions (MTJs). Each MTJ includes a free layer and fixed/reference layer that each includes a magnetic material layer. The free and reference layers are separated by a non-magnetic insulating tunnel barrier. The free layer and the reference layer are magnetically de-coupled by the tunnel barrier. The free layer has a variable magnetization direction, and the reference layer has an invariable magnetization direction.

An MTJ stores information by switching the magnetization state of the free layer. When the free layer's magnetization direction is parallel to the reference layer's magnetization direction, the MTJ is in a low resistance state. Conversely, when the free layer's magnetization direction is antiparallel to the reference layer's magnetization direction, the MTJ is in a high resistance state. The difference in resistance of the MTJ may be used to indicate a logical ‘1’ or ‘0’, thereby storing a bit of information. The TMR of an MTJ determines the difference in resistance between the high and low resistance states. A relatively high difference between the high and low resistance states facilitates read operations in the MRAM.

SUMMARY

According to an embodiment, a method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode.

According to another embodiment, a method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material, the MTJ comprising a reference layer positioned in contact with the spacer material, a free layer, and a tunnel barrier layer arranged between the reference layer and the free layer, the reference layer and the free layer including a magnetic material; patterning a hard mask on the free layer of the MTJ; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer (ILD) on and around the hard mask, the MTJ, and the spacer material; etching through the ILD to form a trench that extends to a surface of the hard mask, along a sidewall of the hard mask, and along a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode; wherein etching the MTJ redeposits a portion of the magnetic material of the reference layer or the free layer onto the sidewall of the spacer material beneath the insulating layer.

Yet, according to another embodiment, a magnetic random access memory (MRAM) device includes a spacer disposed on an electrode; a magnetic tunnel junction (MTJ) disposed on the spacer, the MTJ comprising a reference layer, a free layer, and a tunnel barrier layer between the reference layer and the free layer, and the reference layer positioned in contact with the spacer; a hard mask disposed on the free layer of the MTJ; an interlayer (ILD) disposed on and around the hard mask, the MTJ, and the spacer; an insulating layer positioned along a sidewall of the hard mask, MTJ, and spacer; and a trench that extends through the ILD and includes a metal that forms a contact electrode, the contact electrode positioned in contact with a surface of the hard mask, a sidewall of the hard mask, and a sidewall of a portion of the MTJ.

DETAILED DESCRIPTION

One challenge of integrating STT-MRAM devices into the wiring layers of silicon logic and memory chips is subtractive etching of the magnetic stack from a blanket film, which defines the STT-MRAM device. Specialized reactive ion etches (RIE) and inert ion beam etches (IBE) may be used for the subtractive etching. However, RIE processes for etching MRAM may cause device degradation. Although IBE processes may not induce magnetic damage, they may cause metal redeposition. The metal redeposition may induce shorting across the tunnel barrier in the STT-MRAM stack, which may detract from yield. Oxidizing the redeposited metal to make it insulative may remove the redeposited metal, but the oxidation process itself could cause device degradation.

For example,FIGS. 1A-1Cillustrate methods of making MRAM devices that may result in redeposition shorting.FIG. 1Ais a cross-sectional side view of a patterned hard mask110disposed on a MTJ stack105. The MTJ stack105includes a reference layer102, a tunnel barrier layer103, and a free layer104. The reference layer102and the free layer104include conductive, magnetic metals or metal alloys. The MTJ stack105is disposed on a contact electrode101(bottom contact). A hard mask110is disposed on the MTJ stack105. The hard mask110is then patterned.

FIG. 1Bis a cross-sectional side view after transferring the pattern of the hard mask110into the free layer104and the tunnel barrier layer103of the MTJ stack105. The free layer104and the tunnel barrier layer103are etched, by, for example, a RIE or IBE process. During the etch process, the magnetic material of the free layer104is redeposited along the sidewalls of the free layer104, the tunnel barrier layer103, and the hard mask110.

FIG. 1Cis a cross-sectional side view after etching the reference layer102of the MTJ stack105. Etching the reference layer104results in even more magnetic material being deposited along the sidewalls of the MTJ stack105, including along the reference layer102sidewalls. The redeposited magnetic material may induce shorting along the tunnel barrier103.

Another challenge of integrating MRAM devices is making an electrical contact to the top of the device. A damascene metal wire contacting process, in which the damascene trench etch is used to make contact to the top of the hard mask of the device, may be used to form the contact. In some integration schemes, the trench should be deep enough that the metal damascene trench extends sufficiently close to the tunnel barrier, which may change or improve the device performance. In such a scheme, a dielectric spacer that etches more slowly than the interlayer dielectric and leaves a thin dielectric separating the trench from the MRAM device may mitigate shorting. However, the “deep trench” scheme may still lead to shorting to the bottom contact when the tunnel barrier is close to the bottom contact.

For example,FIGS. 2A-2Cillustrate methods of making MRAM devices that may result in top metal trench shorting.FIG. 2Ais a cross-sectional side view of a patterned MTJ stack105surrounded by an interlayer dielectric (ILD) layer201. The MTJ stack105includes a reference layer102, a tunnel barrier layer103, and a free layer104. The reference layer102and the free layer104include conductive, magnetic metals or metal alloys. The MTJ stack105is disposed on a contact electrode101(bottom contact). A patterned hard mask110is disposed on the MTJ stack105. The pattern of the hard mask110extends through the MTJ stack105. An insulating layer220surrounds the hard mask110and the MTJ stack105. The insulating layer220may include, for example, silicon nitride. An ILD layer201surrounds the insulating layer220and contacts the contact electrode101. The ILD layer201may include, for example, an oxide, e.g., silicon dioxide.

Although redeposition of magnetic material may occur along sidewalls of the MTJ stack105and/or hard mask110when the MTJ stack105is etched, any redeposited magnetic material is not shown because it may be removed by, for example, oxidation or other methods.

FIG. 2Bis a cross-sectional side view after forming a trench202in the ILD layer201. The trench202extends through the ILD layer201down to a level alongside the tunnel barrier layer103or the reference layer102.

FIG. 2Cis a cross-sectional side view after depositing a metal230, e.g., copper, using a metallization process in the trench202to form a top contact. Because the surface of the metal230in the trench202is close to the contact electrode101, shorting in the region240may occur.

Accordingly, various embodiments provide a stack structure and etch processes that reduce the probability of shorting caused by metal redeposition on the MTJ sidewalls, as well as reduce the probability of the trench shorting to the bottom contact. The methods include disposing a conductive spacer layer under the MTJ stack. The conductive spacer layer is deposited as part of the MTJ stack deposition process. RIE and/or IBE processes etch the conducting layer with selectivity against the hard mask. The conducting layer may be, for example, ruthenium (Ru). Although, other metals and semiconductors may be used for the conducting layer. The conductive spacer layer is etched, except for the portion disposed beneath the MTJ stack.

The etching also partially recesses the contact/substrate around the STT-MRAM device. The recessed contact/substrate is a source of the magnetic material redeposition. Because the recessed contact/substrate is further away from the tunnel barrier, redeposition is less likely to collect on the tunnel barrier, and therefore, shorting is less likely.

Furthermore, since the tunnel barrier is effectively raised further above the bottom contact, a deep trench, which extends down to a level near the tunnel barrier, is further from the bottom contact, which also reduces the chances of shorting to the bottom contact. Like reference numerals refer to like elements across different embodiments.

It will also be understood that when an element, such as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present, and the element is in contact with another element.

Turning again to the Figures,FIGS. 3A-3Cillustrate exemplary methods of making MRAM devices according to various embodiments.FIG. 3Ais a cross-sectional side view after patterning a hard mask310on a MTJ stack306disposed on a spacer305. The MTJ stack306includes a reference layer302, a tunnel barrier layer303, and a free layer304. The spacer305is disposed on a contact electrode301.

The contact electrode301includes a conductive material(s) and forms the bottom contact electrode of the MRAM device. Non-limiting examples of conductive materials for the contact electrode include tantalum, tantalum nitride, titanium, or any combination thereof.

The contact electrode301may be formed by depositing a conductive material(s) onto a surface. The conductive material(s) may be deposited by, for example, physical vapor deposition (PVD), ion beam deposition (IBD), atomic layer deposition (ALD), or like processes.

The spacer305is formed on the contact electrode301. The spacer305may be formed by performing a deposition process, for example, a physical vapor deposition process (PVD) (e.g., sputtering), to deposit one or more conductive materials on the contact electrode305. The spacer305may include one layer or multiple layers of conductive materials. For example, the spacer305may include ruthenium, niobium, palladium, or any combination thereof. The spacer305may include a highly doped semiconductor material that is conductive. For example, the spacer305may include, for example, doped polysilicon.

The thickness of the spacer305may generally vary and is not intended to be limited. In some embodiments, the thickness of the spacer305is in a range from about 20 to about 50 nm. In other embodiments, the thickness of the spacer305is in a range from about 25 to about 45 nm.

To form the MTJ stack306, the reference layer302is formed on the spacer305, the tunnel barrier layer303is formed on the reference layer302, and the free layer304is formed on the tunnel barrier layer303.

The reference layer302and the free layer304include conductive, magnetic materials, for example, metals or metal alloys. The reference layer302and the free layer may be formed by employing a deposition process, for example, PVD, IBD, ALD, or other like processes.

The reference layer302and the free layer304may include one layer or multiple layers. The reference layer302and the free layer304may include the same materials and/or layers or different materials and/or layers.

The reference layer302has a thickness that may generally vary and is not intended to be limited. In some embodiments, the reference layer302has a thickness in a range from about 5 to about 25 nm. In other embodiments, the reference layer302has a thickness in a range from about 10 to about 15 nm.

The free layer304has a thickness that may generally vary and is not intended to be limited. In some embodiments, the free layer304has a thickness in a range from about 5 to about 25 nm. In other embodiments, the free layer304has a thickness in a range from about 10 to about 15 nm.

The tunnel barrier layer303includes a non-magnetic, insulating material. A non-limiting example of an insulating material for the tunnel barrier layer330includes magnesium oxide (MgO). The tunnel barrier layer303may be formed on the reference layer302by, for example, radiofrequency (RF) sputtering in some embodiments. Alternatively, the tunnel barrier layer303is formed by oxidation (e.g., natural or radical oxidation) of a magnesium (Mg) layer deposited on the reference layer302. After oxidation, the MgO layer may then be capped with a second layer of Mg.

A hard mask material layer is disposed on the MTJ stack305. The hard mask material layer may include one or more conductive materials. The material forming the hard mask may be deposited by employing a deposition process, for example, PVD, IBD, or other like processes. Non-limiting examples of conductive materials for the hard mask material layer include tantalum nitride, titanium, titanium nitride, or any combination thereof.

The hard mask material layer is then patterned by etching to form the hard mask310. The hard mask310may be etched by employing a reactive ion etch (RIE) process or a halogen-based chemical etch process (e.g., including chlorine-containing gas and/or fluorine-containing gas chemistry). The hard mask310and the free layer304are etched at different rates such that the hard mask310is etched and the free layer304remains un-etched.

FIG. 3Bis a cross-sectional side view after etching the MTJ stack306and spacer305. The pattern from the hard mask310is transferred into the free layer304, tunnel barrier layer303, reference layer302, and the spacer305. The free layer304, tunnel barrier layer303, and reference layer302are etched by, for example, performing a MRAM stack etch process. The stack etch process may be a RIE process or an ion beam etch (IBE) process.

The stack etch process etches the spacer305without substantially further etching the hard mask310. Etching the MTJ stack306and the spacer305does not substantially degrade the hard mask310.

Because the MTJ stack306includes magnetic materials (e.g., metal or metal alloys), etching the MTJ stack redeposits a portion of the magnetic material along a portion of the sidewall of the spacer305, as shown inFIG. 3C(redeposition321).

FIG. 3Cis a cross-sectional side view after depositing an insulating layer320and an ILD layer330, forming a trench in the ILD layer330, and disposing a metal340in the trench to form a second contact.

The insulating layer320may include one or more insulating materials. Initially, the insulating layer320encapsulates the hard mask310, the free layer304, the tunnel barrier layer303, the reference layer302, and the spacer305. The insulating layer320is deposited on the exposed surface and sidewalls of the hard mask310, sidewalls of the MTJ306, and sidewalls of the spacer305.

The insulating layer320may be formed by performing a deposition process, for example, plasma enhanced chemical vapor deposition (PECVD), CVD, PVD, IBD, or other like processes. Non-limiting examples of materials for the insulating layer320include silicon nitride, aluminum oxide (Al2O3), amorphous carbon (a-C), silicon SiBCN, SiOCN, or any combination thereof.

The thickness of the insulating layer320may generally vary and is not intended to be limited. In some embodiments, the thickness of the insulating layer320is in a range from about 10 to about 60 nm. In other embodiments, the thickness of the insulating layer320is in a range from about 20 to about 40 nm.

Initially, the insulating layer320covers the hard mask310and contacts sidewalls of the hard mask110, free layer304, tunnel barrier layer303, reference layer302, and spacer305. Then the insulating layer303is etched to expose the surface of the hard mask110. The insulating layer320may be etched during the ILD layer330trench etch process, discussed below.

The ILD layer330is deposited on the contact electrode301and the hard mask310and around the MTJ stack306and spacer305. The ILD layer330may include a low-k dielectric oxide, including but not limited to, silicon dioxide, spin-on-glass, a flowable oxide, a high-density plasma oxide, or any combination thereof. The ILD layer330may be formed by performing deposition process, including, but not limited to CVD, PVD, plasma enhanced CVD, atomic layer deposition (ALD), evaporation, chemical solution deposition, or like processes.

The ILD layer330is etched to form a trench that is then filled with a metal340. The ILD layer330is etched to form a trench that extends to a surface of the hard mask310, along the sidewalls of the hard mask310, and along the sidewalls of a portion of the MTJ stack306. For example, the trench may extend to a level that is parallel to the reference layer302, the tunnel barrier layer303, or the free layer304.

The ILD layer330is etched using a wet etch chemical process. For example, a fluorocarbon etch chemistry, e.g., CF4or CHF3, or a plasma etch chemistry may be employed to form the trench in the ILD layer330. The insulating layer320may also be etched during the trench formation. As the trench in the ILD layer330is etched it reaches the top of the hardmask610, which is covered by insulating layer320. The exposed portion of the insulating layer320is etched away.

A metallization process is employed to deposit a metal340into the trench within the ILD layer330. The metal340within the trench forms the top contact electrode. The metal340may be deposited by performing a deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, or sputtering. Non-limiting examples of materials for the metal340include copper, aluminum, or any combination thereof.

The spacer305raises the bottom of the metal340containing contact sufficiently far above the contact electrode301so that any redeposition321collects at the base along sidewalls of the spacer305beneath the insulating layer320, which is far below the tunnel barrier layer303where shorting would occur (seeFIGS. 1C and 2C). The tunnel barrier layer303is substantially free of any redeposited magnetic material because the redeposited magnetic material is confined to sidewalls of the spacer305. In some embodiments, the MTJ stack306is substantially free of redeposited magnetic material.

As described above, various embodiments provide a stack structure and etch processes that reduce the probability of shorting caused by metal redeposition on the MTJ sidewalls, as well as reduce the probability of the trench shorting to the bottom contact. The methods include disposing a conductive spacer layer under the MTJ stack. The conductive spacer layer is deposited as part of the MTJ stack deposition process. RIE and/or IBE processes etch the conducting layer with selectivity against the hard mask. The conducting layer may be, for example, ruthenium (Ru). Although, other metals and semiconductors may be used for the conducting layer. The conductive spacer layer is etched, except for the portion disposed beneath the MTJ stack. The etching also partially recesses the contact/substrate around the STT-MRAM device. The recessed contact/substrate is a source of the magnetic material redeposition. Because the recessed contact/substrate is further away from the tunnel barrier, redeposition is less likely to collect on the tunnel barrier, and therefore, shorting is less likely. Furthermore, since the tunnel barrier is effectively raised further above the bottom contact, a deep trench, which must extend down to a level near the tunnel barrier, is further from the bottom contact, which also eliminates shorting to the bottom contact. Like reference numerals refer to like elements across different embodiments.