Semiconductor device and display device

An object is to reduce power consumption of a semiconductor device including a DC-DC converter circuit. The semiconductor device includes a DC-DC converter circuit and a microprocessor. The DC-DC converter circuit includes a conversion circuit including an inductor and a transistor, and a control circuit including a comparison circuit and a logic circuit. In the control circuit, the comparison circuit compares an output of the conversion circuit and a reference value, and the logic circuit performs an arithmetic operation between an output of the comparison circuit and a clock signal of the microprocessor. In the conversion circuit, the transistor controls a current flowing through the inductor in accordance with an output of the logic circuit, and the output of the conversion circuit is generated in accordance with the current flowing through the inductor.

TECHNICAL FIELD

The technical field relates to a semiconductor device and a method for driving the semiconductor device, and a display device and a method for driving the display device.

BACKGROUND ART

In recent years, a circuit that converts a given DC voltage into another DC voltage (also referred to as a DC-DC converter circuit or a DC to DC converter) is used in a variety of electronic devices when a stable power supply voltage is generated from a voltage with large fluctuation or when a plurality of different power supply voltages are needed, for example.

An example of the DC-DC converter circuit is a non-isolated DC-DC converter circuit formed using a coil, a diode, and a transistor, for example (e.g., Patent Document 1). The non-isolated DC-DC converter circuit has advantages of a small circuit area and low production cost.

REFERENCE

DISCLOSURE OF INVENTION

An object is to provide a novel circuit structure or a novel driving method for a semiconductor device including a DC-DC converter circuit. Another object is to reduce power consumption of a DC-DC converter circuit. Another object is to increase the power conversion efficiency of a DC-DC converter circuit.

A semiconductor device includes a DC-DC converter circuit and a microprocessor. The DC-DC converter circuit is controlled using a clock signal of the microprocessor and converts an input voltage (also referred to as an input signal) into an output voltage (also referred to as an output signal). Note that the input and output of the DC-DC converter circuit may alternatively be current or the like.

According to one embodiment of the present invention, a semiconductor device includes a DC-DC converter circuit and a microprocessor. The DC-DC converter circuit includes a conversion circuit including an inductor and a transistor, and a control circuit including a comparison circuit and a logic circuit. In the control circuit, the comparison circuit compares an output of the conversion circuit and a reference value (also referred to as a reference voltage or a reference signal), and the logic circuit performs arithmetic operation of an output of the comparison circuit and a clock signal of the microprocessor. In the conversion circuit, the transistor controls a current flowing through the inductor in accordance with an output of the logic circuit, and the output of the conversion circuit is generated in accordance with the current flowing through the inductor.

According to another embodiment of the present invention, a display device includes a DC-DC converter circuit, a microprocessor, and a display portion including a pixel. The DC-DC converter circuit includes a conversion circuit including an inductor and a transistor, and a control circuit including a comparison circuit and a logic circuit. In the control circuit, the comparison circuit compares an output of the conversion circuit and a reference value, and the logic circuit performs arithmetic operation of an output of the comparison circuit and a clock signal of the microprocessor. In the conversion circuit, the transistor controls a current flowing through the inductor in accordance with an output of the logic circuit, and the output of the conversion circuit is generated in accordance with the current flowing through the inductor. In the display portion, the pixel is driven in accordance with the output of the conversion circuit.

According to another embodiment of the present invention, a display device includes a DC-DC converter circuit, a microprocessor, and a display portion including a pixel. The DC-DC converter circuit includes a conversion circuit including an inductor and a transistor, and a control circuit including a comparison circuit, an amplification circuit, and a logic circuit. In the control circuit, one of a first operation and a second operation is performed. In the first operation, the comparison circuit compares an output of the conversion circuit and a first reference value, and the logic circuit performs arithmetic operation of an output of the comparison circuit and a clock signal of the microprocessor. In the second operation, the amplification circuit amplifies a difference between the output of the conversion circuit and a second reference value, and the comparison circuit compares an output of the amplification circuit and a triangle wave. In the conversion circuit, the transistor controls a current flowing through the inductor in accordance with an output of the logic circuit through the first operation or an output of the comparison circuit through the second operation, and the output of the conversion circuit is generated in accordance with the current flowing through the inductor. In the display portion, one of first driving and second driving is performed. A video signal is written into the pixel at intervals of from 1 to 600 seconds in the first driving, and at intervals of 1/60 seconds or less in the second driving. In the display portion, the pixel is driven in accordance with the output of the conversion circuit through the first operation when the first driving is performed, and the pixel is driven in accordance with the output of the conversion circuit through the second operation when the second driving is performed.

In a semiconductor device or a display device according to one embodiment of the present invention, power consumption of a DC-DC converter circuit can be reduced. Moreover, the power conversion efficiency of the DC-DC converter circuit can be increased.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments will be described below with reference to the accompanying drawings. Note that the following embodiments can be implemented in many different modes, and it is apparent to those skilled in the art that modes and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments. In the drawings for explaining the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and description of such portions is not repeated.

In this embodiment, examples of a structure and a driving method of a semiconductor device will be described.

FIG. 1Ais an example of a block diagram of a semiconductor device including a DC-DC converter circuit.

The semiconductor device includes a DC-DC converter circuit101and a microprocessor103. The DC-DC converter circuit101includes a conversion circuit105and a control circuit107. The DC-DC converter circuit101generates an output voltage Voutby conversion of an input voltage Vin.

FIGS. 1B and 1Ceach illustrate an example of the conversion circuit105.FIG. 1Billustrates a step-up converter (Vin<Vout), andFIG. 1Cillustrates a step-down converter (Vin>Vout).

The conversion circuit105at least includes a transistor Tr and an inductor L.

The transistor Tr functions as a switch element and controls current flowing through the inductor L by being switched on (conduction state) and off (non-conduction state). Note that the state of the transistor Tr is determined by a pulse signal generated in the control circuit107.

The inductor L generates electromotive force depending on the current flowing therethrough, and generates the output voltage Voutof the conversion circuit105(also called an output voltage of the DC-DC converter circuit101). The current value is determined by the level of the input voltage Vinor the like. In such a manner, the input voltage Vincan be converted into the output voltage Vout. In this embodiment, the inductor L is a coil, for example.

Next, a specific structure and operation of the conversion circuit105will be described, using the circuit inFIG. 1B.

The conversion circuit105inFIG. 1Bincludes the transistor Tr, the inductor L, a diode D, and a capacitor C. A gate of the transistor Tr is electrically connected to the control circuit107. One of a source and a drain of the transistor Tr is electrically connected to one terminal of the inductor L and an anode of the diode D. The other terminal of the inductor L is electrically connected to an input terminal A cathode of the diode D is electrically connected to one terminal of the capacitor C and an output terminal. The other of the source and the drain of the transistor Tr and the other terminal of the capacitor C are electrically connected to a wiring to which a predetermined potential is input. Here, the predetermined potential is a ground potential, for example.

Note thatFIG. 1Billustrates the example in which the diode D is used for rectification and the capacitor C is used for smoothing; this embodiment is not limited to using these components.

The conversion circuit105has two operations corresponding to the on state and the off state of the transistor Tr. The conversion circuit105steps up the input voltage Vinby alternately repeating the two operations.

First, when the transistor Tr is on, the inductor L generates electromotive force in accordance with current flowing therethrough. The current value is determined by the input voltage Vin.

Then, when the transistor Tr is off, the inductor L generates reverse electromotive force so as to maintain the current. The input voltage Vinis added to the electromotive force generated at this time, and Voutbecomes αVin.

Here, α is determined by the ratio of an on-state period to one switching cycle (an on-state period Ton+an off-state period Toff) of the transistor Tr, that is, by a duty ratio D (=Ton/(Ton+Toff), where 0<D<1). In the case of using the step-up circuit, the input voltage Vinis stepped up with α=1/(1−D)>1.

Then, the output voltage Voutof the conversion circuit105is fed back to the control circuit107. In the case where a feedback voltage VFBis higher than a desired level, the control circuit107decreases the duty ratio D of the pulse signal. On the other hand, in the case where the feedback voltage VFBis lower than a desired level, the control circuit107increases the duty ratio D of the pulse signal.

Then, the transistor Tr controls the current flowing through the inductor L in accordance with the duty ratio D of the pulse signal input from the control circuit107, and converts the input voltage Vininto the voltage with another level to generate the output voltage Vout.

By feeding back the output voltage Voutthe control circuit107in such a manner, the output voltage Voutcan be closer to a desired level. DC-DC conversion can be performed in this manner.

Similarly, in the case of using the step-down circuit inFIG. 1C, the transistor Tr is controlled in accordance with the duty ratio D (0<D<1) of the pulse signal of the control circuit107, and Voutbecomes αVin. In the case of using the step-down circuit, the input voltage Vinis stepped down with 0<α=D<1.

As the transistor Tr, a thin film transistor, a power MOSFET, or the like can be used, and a p-channel transistor or an n-channel transistor can be used as appropriate. The transistor Tr may have a top-gate structure or a bottom-gate structure. Moreover, the transistor Tr may have a channel-etch structure or a channel-stop structure. For a semiconductor material of the transistor Tr, a silicon semiconductor such as silicon or silicon germanium, an oxide semiconductor, an organic semiconductor, a compound semiconductor, or the like can be used. Alternatively, an amorphous semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, a single crystal semiconductor, or the like can be used.

Next, a specific structure and operation of the control circuit107will be described.FIG. 1Dillustrates an example of the control circuit107.

The control circuit107includes a comparison circuit109and a logic circuit111.FIG. 1Dillustrates an example where a comparator is used as the comparison circuit109and an AND circuit is used as the logic circuit111; alternatively, any of other comparison circuits and logic circuits can be used without limitation to this example.

As described above, the feedback voltage VFBfrom the conversion circuit105is input to the comparison circuit109. The comparison circuit109compares the feedback voltage VFBand a reference voltage Vref, and outputs a positive voltage (also referred to as an H voltage or VH) or a negative voltage (also referred to as an L voltage or VL).

The output voltage of the comparison circuit109and a clock signal CLK of the microprocessor103are input to the logic circuit111. The logic circuit111performs arithmetic operation of these two signals, generates a pulse signal with a desired duty ratio D, and outputs the pulse signal to the gate of the transistor Tr. The on/off state of the transistor Tr is controlled in accordance with the duty ratio D of the pulse signal. Such control is called hysteresis control.

This embodiment features the use of the clock signal CLK of the microprocessor103. By using the clock signal CLK, the duty ratio D can be controlled with extreme accuracy. In other words, the output voltage Voutof the conversion circuit105can be stable, and the reliability of the DC-DC converter circuit101can be improved. Moreover, the microprocessor103can be used also by a circuit other than the DC-DC converter circuit101; thus, production cost can be reduced.

In particular, the use of the clock signal CLK is extremely effective in the case of using the step-up circuit illustrated inFIG. 1Bbecause it is theoretically difficult to obtain a desired duty ratio D in the comparison circuit109.

Next, a specific example of generation of a pulse signal in the control circuit107will be described.FIG. 2Aillustrates a structure of a DC-DC converter circuit in which the circuit inFIG. 1Bis used as the conversion circuit105and the circuit inFIG. 1Dis used as the control circuit107. That is, the circuit inFIG. 2Ais a step-up DC-DC converter circuit.

FIG. 2Bis a timing chart. The timing chart inFIG. 2Bshows the feedback voltage VFBfrom the conversion circuit105, an output voltage Vcmpof the comparison circuit109, the clock signal CLK of the microprocessor103, and an output voltage Visof the logic circuit111(also referred to as an output voltage of the control circuit107or a gate voltage of the transistor Tr).

Here, the case where the feedback voltage VFBhas a sawtooth wave is described. The comparison circuit109compares the inputted feedback voltage VFBand a reference voltage Vref. When VFB>Vref, the output voltage Vcmpbecomes VL. On the other hand, when Vref>VFB, the output voltage Vcmpbecomes VH.

Then, the logic circuit111performs arithmetic operation of the inputted output voltage Vcmpand the clock signal CLK of the microprocessor103. An AND circuit is used as the logic circuit111in this embodiment; therefore, the output voltage Visis VHwhen both of the two signals are VHand is VLin any other case.

In such a manner, the duty ratio D of the pulse signal is determined in accordance with the level of the output voltage Vis. Moreover, the on/off state of the transistor Tr is controlled in accordance with the duty ratio D, and DC-DC conversion is performed. A load115is driven in response to the converted output voltage Vout.

In this embodiment, examples of a structure and a driving method of a semiconductor device will be described.

FIG. 3Ais an example of a block diagram of a semiconductor device including a DC-DC converter circuit.

The semiconductor device inFIG. 3Ahas a structure where an amplification circuit113is additionally provided in the structure ofFIG. 1A. Except for the amplification circuit113,FIGS. 1B to 1Dcan be employed.

FIG. 3Billustrates a specific circuit structure. A feature of this embodiment is that the feedback voltage VFBfrom the conversion circuit105is input to one of the comparison circuit109and the amplification circuit113in the control circuit107. Therefore, the control circuit107performs two operations (a first operation and a second operation). The two operations are switched and selected by a multiplexer MUX and an external signal HC-MODE for controlling the multiplexer MUX.

Arrows inFIG. 4Arepresent the case where the first operation is selected by control of the multiplexer MUX. The control with the first operation is hysteresis operation shown in Embodiment 1. That is, the feedback voltage VFBis input to the comparison circuit109. The comparison circuit109compares the feedback voltage VFBand a reference voltage Vref1. The logic circuit111performs arithmetic operation of the output voltage of the comparison circuit109and the clock signal CLK of the microprocessor103. The output voltage of the logic circuit111controls the on/off state of the transistor Tr.

Arrows inFIG. 4Brepresent the case where the second operation is selected by control of the multiplexer MUX. In the second operation, the feedback voltage VFBis input to the amplification circuit113. The amplification circuit113amplifies a difference between the feedback voltage VFBand a reference voltage Vref2. The comparison circuit109compares the output voltage of the amplification circuit113and a triangle wave. The output voltage of the comparison circuit109controls the on/off state of the transistor Tr. As the amplification circuit113, an error amplifier is used, for example. The control with the second operation is called PWM (pulse width modulation) control.

Next, a specific example of generation of a pulse signal in the control circuit107will be described. Generation of a pulse signal in the first operation is as shown inFIG. 2B.

FIG. 5is a timing chart in the second operation.FIG. 5shows the feedback voltage VFBfrom the conversion circuit105, an output voltage Vampof the amplification circuit113, and the output voltage Visof the comparison circuit109(also referred to as the output voltage of the control circuit107or the gate voltage of the transistor Tr).

Here, the case where the feedback voltage VFBhas a sawtooth wave is described. The amplification circuit113amplifies a difference between the inputted feedback voltage VFBand the reference voltage Vref2. Here, the output voltage Vamprepresents a steady-state voltage and corresponds to the integral of amplified differences.

Then, the comparison circuit109compares the inputted output voltage Vampand the triangle wave. When Vamp>triangle wave, the output voltage VGSbecomes VL. On the other hand, when triangle wave>Vamp, the output voltage VGSbecomes VH.

In such a manner, the duty ratio D of the pulse signal is determined in accordance with the level of the output voltage VGS. Moreover, the on/off state of the transistor Tr is controlled in accordance with the duty ratio D, and DC-DC conversion is performed. The load115is driven in response to the converted output voltage Vout.

Note that it is important to increase the power conversion efficiency of the DC-DC converter circuit101. The power conversion efficiency n is represented as n=Pout/Pin<1, where Pinis an input power and Poutis an output power of the DC-DC converter circuit101. The power conversion efficiency n is increased depending on the value of the load.

In this embodiment, when the first operation is performed, the amplification circuit113, a circuit for generating the triangle wave, and the like can be turned off, so that power consumption of the DC-DC converter circuit101can be reduced. A reduction in power consumption of the DC-DC converter circuit101(=Pin−Pout) can increase the power conversion efficiency n even if the load is small. In other words, the first operation is effective in the case where the load is small.

When the second operation is performed, the duty ratio D of the pulse signal of the control circuit107can be approximately equal to 1 (D≈1), which is larger than that in the first operation; thus, the output voltage Voutof the DC-DC converter circuit101can be increased. By increasing the output voltage Voutof the DC-DC converter circuit101, the output power Poutis increased in the case where the load is large, and the power conversion efficiency n can be increased. In other words, the second operation is effective in the case where the load is large.

In the semiconductor device including the DC-DC converter circuit in this embodiment, the operation is switched in accordance with the load in such a manner; thus, the power conversion efficiency n can be increased.

A microprocessor can be not only used for DC-DC conversion but have another function. For example, in a lighting device, a microprocessor may be used for sensing ambient light so that the illuminance is automatically controlled. When a device is thus provided with a sensor function or a control function using a microprocessor, a reduction in power consumption and higher functionality can be achieved at the same time. Note that this structure can also be applied to home appliances such as air conditioners and refrigerators and other various electronic devices.

In this embodiment, a structure and a driving method of a display device will be described.

A display device in this embodiment includes the DC-DC converter circuit disclosed in this specification and a display panel (also referred to as a display portion) driven in accordance with the output voltage Voutof the DC-DC converter circuit. The load115illustrated inFIG. 1A,FIG. 2A,FIGS. 3A and 3B, andFIGS. 4A and 4Bcorresponds to a display panel.

FIG. 6Aillustrates an example of a display panel. The display panel includes pixels PX, and a driver circuit GD and a driver circuit SD that drive the pixels PX. The pixels PX are arranged in matrix.

FIG. 6Billustrates an example of the pixel PX. The pixel PX includes a switching transistor Ts, a liquid crystal element LC, and a capacitor Cs. When the transistor Ts is on, a video signal is written into the liquid crystal element LC from the driver circuit SD through a wiring S, and display based on the video signal is performed. When the transistor Ts is off, the capacitor Cs holds the video signal written into the liquid crystal element LC, so that display is maintained. The on/off state of the transistor Ts is controlled with a signal input from the driver circuit GD through a wiring G Note that the pixel PX is not limited to having this structure.

The display panel in this embodiment (the load115) features two kinds of driving (first driving and second driving).

First, in the first driving, a video signal is written into the pixel PX at intervals of 1 to 600 seconds, for example. With the first driving, writing is not performed on the pixel PX between the intervals, so that the write cycles can be reduced, leading to a reduction in power consumption. In other words, the load of the display panel is small in the first driving. Note that the first operation can be applied when pixels PX display a still image. Further, the interval may be longer than 600 seconds.

The first operation (hysteresis operation) performed in the control circuit107as illustrated inFIG. 4Ais effective in the case where the first driving with a small load is performed. The first operation can reduce power consumption of the DC-DC converter circuit, so that the power conversion efficiency can be increased even when the load is small.

Then, in the second driving, a video signal is written into the pixel PX at intervals of 1/60 seconds or less. That is, a video signal is written into the pixel PX 60 times or more per second. Specific examples of the intervals are 1/60 seconds (60 Hz), 1/120 seconds (120 Hz), and 1/240 seconds (240 Hz). Power consumption is increased because of a large number of write cycles. In other words, the load of the display panel is large in the second driving. Note that the second operation can be applied when pixels PX display a moving image.

The second operation (PWM control) performed in the control circuit107as illustrated inFIG. 4Bis effective in the case where the second driving with a large load is performed. Since the duty ratio D can be approximately equal to 1 (D≈1) in the second operation, the output power of the DC-DC converter circuit can be increased when the load is large, and the power conversion efficiency can be increased.

The operation of the control circuit in the DC-DC converter circuit is switched in accordance with a method for driving the display panel as described above, so that it is possible to provide a display device in which power consumption of the DC-DC converter circuit and the display panel can be reduced and the power conversion efficiency of the DC-DC converter circuit can be increased.

Next, a specific example of switching the operation (the first operation and the second operation) of the DC-DC converter circuit in accordance with the driving (the first driving and the second driving) of the display panel will be described with reference toFIGS. 4A and 4BandFIGS. 6A and 6B.

InFIGS. 4A and 4B, the microprocessor103performs analysis, arithmetic operation, and processing of electronic data to be displayed, and generates a video signal. Here, the case where electronic data includes still image data and moving image data and the microprocessor103distinguishes a still image and a moving image so that different signals (distinction signals) are output for the still image and the moving image will be described.

In the case where electronic data to be displayed is still image data, a distinction signal indicating that the image to be displayed is a still image and a video signal corresponding to the electronic data for the still image are input to the display panel. Further, in the case where electronic data is moving image data, signals are input in a similar manner. At that time, the distinction signal is also input to the DC-DC converter circuit101and can be used as the external signal HC-MODE for controlling the multiplexer MUX illustrated inFIGS. 4A and 4B. In such a manner, the microprocessor103can be used by both the DC-DC converter circuit101and the display panel.

Note that when a difference between successive electronic data is calculated and found to be equal to or larger than a predetermined reference value, it is judged that the data is for a moving image; whereas when the difference is smaller than the reference value, it is judged that the data is for a still image. Judgment can be made with a comparator or the like.

In the display panel, the on/off state of the transistor Ts is controlled by the driver circuit GD in accordance with a distinction signal. Moreover, the driver circuit SD performs writing on the pixel PX in accordance with a video signal. Note that a circuit for controlling the driver circuit GD and the driver circuit SD may be provided; the circuit outputs a start signal, a clock signal, and a power supply voltage to the driver circuit GD and the driver circuit SD in accordance with the distinction signal.

The first driving is applied to a still image, and a video signal is written into the pixel PX at intervals of 1 to 600 seconds. On the other hand, the second driving is applied to a moving image, and a video signal is written into the pixel PX at intervals of 1/60 seconds or less.

Further, in the DC-DC converter circuit101, the multiplexer MUX is controlled in accordance with the distinction signal, and the first operation or the second operation is selected. When the distinction signal indicating a still image is input, the first operation inFIG. 4Ais performed and the output voltage Voutis generated. When the distinction signal indicating a moving image is input, the second operation inFIG. 4Bis performed and the output voltage Voutis generated.

As described above, the operation of the DC-DC converter circuit101can be switched in accordance with the amount of load of the display panel so that the DC-DC converter circuit101performs the first operation (hysteresis operation) when the display panel performs the first driving with a small load (displays a still image), and performs the second operation (PWM control) when the display panel performs the second driving with a large load (displays a moving image).

In this embodiment, an example of a transistor included in a semiconductor device which is one embodiment of the disclosed invention will be described. Specifically, an example of a transistor in which a channel formation region is formed using an oxide semiconductor layer, that is, a transistor including an oxide semiconductor layer will be described.

In the transistor described in this embodiment, a channel formation region is formed using an oxide semiconductor layer. The oxide semiconductor layer is purified to be electrically intrinsic (i-type) or substantially intrinsic. Purification means the following concepts: hydrogen which is an n-type impurity is removed from an oxide semiconductor so that the oxide semiconductor contains impurities other than the main components as little as possible, and oxygen which is one of main components of an oxide semiconductor is supplied to an oxide semiconductor layer so that defects due to oxygen vacancy in the oxide semiconductor layer are reduced.

The number of carriers in the purified oxide semiconductor is very small, and the carrier concentration is less than 1×1012/cm3, preferably less than 1×1011/cm3. Here, a semiconductor with a carrier concentration lower than 1×1011/cm3is called an intrinsic (i-type) semiconductor, and a semiconductor with a carrier concentration equal to or higher than 1×1011/cm3and lower than 1×1012/cm3is called a substantially intrinsic (substantially i-type) semiconductor.

Since the number of carriers in the oxide semiconductor is very small, the off-state current can be extremely low. For example, in a transistor including a purified oxide semiconductor layer, the off-state current at room temperature (per channel width of 1 μm) can be 1 aA/μm (1×10−18A/μm) or lower, and further can be 100 zA/μm (1×10−19A/μm) or lower.

The off-state current can be extremely low in a transistor in which a channel formation region is formed using an oxide semiconductor layer that is purified by the removal of hydrogen contained therein and the supply of oxygen to reduce defects due to oxygen vacancy therein. Therefore, charge stored at one of a source and a drain of the transistor can be retained for a long time.

An example of a structure and a manufacturing method of a transistor whose channel formation region is formed using an oxide semiconductor layer will be described with reference toFIGS. 7A to 7D.

FIGS. 7A to 7Dare cross-sectional views illustrating an example of a structure and a manufacturing process of a transistor whose channel formation region is formed using an oxide semiconductor layer.

The transistor illustrated inFIG. 7Dincludes a conductive layer401, an insulating layer402, an oxide semiconductor layer403, a conductive layer405, and a conductive layer406.

The conductive layer401is provided over a substrate400. The insulating layer402is provided over the conductive layer401. The oxide semiconductor layer403is provided over the conductive layer401with the insulating layer402placed therebetween. The conductive layer405and the conductive layer406are each provided over part of the oxide semiconductor layer403.

Part of a top surface of the oxide semiconductor layer403(part of the oxide semiconductor layer403over which the conductive layer405and the conductive layer406are not provided) is in contact with an oxide insulating layer407. A protective insulating layer409is provided over the oxide insulating layer407.

The transistor illustrated inFIG. 7Dhas a bottom-gate type structure and is also referred to as an inverted staggered transistor. Moreover, the transistor has a channel-etch structure and a single-gate structure. However, the structure of the transistor is not limited to the above. For example, the transistor may have a top-gate structure instead of a bottom-gate structure, a channel protective structure instead of a channel-etch structure, and/or a multi-gate structure instead of a single-gate structure.

A process for manufacturing the transistor will be described below with reference toFIGS. 7A to 7D.

First, the substrate400is prepared, and a first conductive film is formed over the substrate400. There is no limitation on the substrate400as long as it can withstand subsequent manufacturing steps. Examples of the substrate400are an insulating substrate such as a glass substrate, a semiconductor substrate such as a silicon substrate, a conductive substrate such as a metal substrate, and a flexible substrate such as a plastic substrate. Moreover, an insulating layer can be provided over the substrate400. In that case, the insulating layer serves as a base that prevents diffusion of impurities from the substrate. For example, the insulating layer serving as a base can be formed with a single-layer structure or a stacked structure including two layers or more, using an insulating layer of silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, or the like. Note that it is preferable that the insulating layer contain hydrogen and water as little as possible.

Examples of the first conductive film are a film of a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, and a film of an alloy material that contains any of the metal materials as a main component. Alternatively, the first conductive film can be a stack of layers of any of materials that can be applied to the first conductive film.

Next, a first photolithography process is carried out: a first resist mask is formed over the first conductive film, the first conductive film is selectively etched using the first resist mask to form the conductive layer401, and the first resist mask is removed. The conductive layer401serves as a gate electrode of the transistor.

Then, the insulating layer402is formed over the conductive layer401. The insulating layer402serves as a gate insulating layer of the transistor. As the insulating layer402, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer can be used, for example. Alternatively, the insulating layer402can be a stack of layers of any of the materials applicable to the insulating layer402.

For example, the insulating layer402can be formed by depositing an insulating film by high-density plasma CVD. For example, high-density plasma CVD using microwaves (e.g., a frequency of 2.45 GHz) is preferable because a dense insulating film with high breakdown voltage and high quality can be deposited. When a high-quality insulating layer is formed by depositing an insulating film by high-density plasma CVD, the interface state density between the gate insulating layer and a channel formation layer of the transistor can be reduced and interface characteristics can be favorable.

Alternatively, the insulating layer402can be formed by sputtering, plasma CVD, or the like. Further, heat treatment may be performed after the formation of the insulating layer402. The heat treatment can improve the quality of the insulating layer402and the interface characteristics between the insulating layer402and the oxide semiconductor.

Next, an oxide semiconductor film530with a thickness ranging from 2 nm to 200 nm, preferably from 5 nm to 30 nm, is formed over the insulating layer402. For example, the oxide semiconductor film530can be formed by sputtering.

Note that before the formation of the oxide semiconductor film530, powdery substances (also referred to as particles or dust) attached on a surface of the insulating layer402are preferably removed by reverse sputtering in which an argon gas is introduced and plasma is generated. The reverse sputtering is a method in which voltage is applied to a substrate side with the use of an RF power supply in an argon atmosphere without applying voltage to a target side and plasma is generated in the vicinity of the substrate so that a substrate surface is modified. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used.

The oxide semiconductor film530can be formed using an In—Sn—Ga—Zn—O-based oxide semiconductor, an In—Ga—Zn—O-based oxide semiconductor, an In—Sn—Zn—O-based oxide semiconductor, an In—Al—Zn—O-based oxide semiconductor, a Sn—Ga—Zn—O-based oxide semiconductor, an Al—Ga—Zn—O-based oxide semiconductor, a Sn—Al—Zn—O-based oxide semiconductor, an In—Zn—O-based oxide semiconductor, a Sn—Zn—O-based oxide semiconductor, an Al—Zn—O-based oxide semiconductor, a Zn—Mg—O-based oxide semiconductor, a Sn—Mg—O-based oxide semiconductor, an In—Mg—O-based oxide semiconductor, an In—Ga—O-based oxide semiconductor, an In—O-based oxide semiconductor, a Sn—O-based oxide semiconductor, a Zn—O-based oxide semiconductor, or the like. Here, an In—Ga—Zn—O-based oxide semiconductor is an oxide semiconductor containing at least In, Ga, and Zn, and there is no particular limitation on the composition ratio thereof. Further, the In—Ga—Zn—O-based oxide semiconductor may contain an element other than In, Ga, and Zn. The above oxide semiconductors can contain SiO2.

Furthermore, the oxide semiconductor film530can be formed using an oxide semiconductor represented by the chemical formula, InMO3(ZnO)m(m>0). Here, M denotes one or more of metal elements selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, or Ga and Co.

For example, the oxide semiconductor film530can be formed by sputtering with the use of an In—Ga—Zn—O-based oxide target (FIG. 7A). The atmosphere in which the oxide semiconductor film530is formed can be a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen.

As a sputtering gas used for forming the oxide semiconductor film530, a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydride are removed is preferably used, for example.

Next, a second photolithography process is carried out: a second resist mask is formed over the oxide semiconductor film530, the oxide semiconductor film530is selectively etched using the second resist mask to process the oxide semiconductor film530into an island-shaped oxide semiconductor layer403, and the second resist mask is removed.

For example, dry etching, wet etching, or both dry etching and wet etching can be employed for etching of the oxide semiconductor film530.

Next, the oxide semiconductor layer is subjected to first heat treatment. With the first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer can be conducted. The temperature of the first heat treatment is equal to or higher than 400° C. and lower than the strain point of the substrate (seeFIG. 7B).

A heat treatment apparatus used for the heat treatment is not limited to an electric furnace and may be an apparatus for heating an object by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (rapid thermal annealing) apparatus such as a GRTA (gas rapid thermal annealing) apparatus or an LRTA (lamp rapid thermal annealing) apparatus can be used as the heat treatment apparatus. An LRTA apparatus is an apparatus for heating an object by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. A GRTA apparatus is an apparatus for heat treatment using a high-temperature gas. An example of the high-temperature gas is an inert gas that does not react with an object by heat treatment, such as nitrogen or a rare gas like argon.

For example, as the first heat treatment, GRTA may be performed in the following manner: the substrate is transferred to an inert gas that has been heated to a high temperature of 650° C. to 700° C., heated for several minutes, and transferred from the heated inert gas.

In addition, after the first heat treatment is performed on the oxide semiconductor layer with an electric furnace, a high-purity oxygen gas or N2O gas of 6N purity or higher (preferably 7N purity or higher) may be introduced into the same electric furnace while the temperature is maintained or decreased from the heat treatment temperature. In that case, it is preferable that the oxygen gas or the N2O gas do not contain water, hydrogen, and the like. By the effect of the oxygen gas or the N2O gas, oxygen that has been reduced through the step of eliminating impurities by the dehydration or dehydrogenation treatment is supplied; thus, the oxide semiconductor layer403can be purified.

Next, a second conductive film is formed over the insulating layer402and the oxide semiconductor layer403.

As the second conductive film, a film of a metal material such as aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten or an alloy material that contains any of the metal materials as a main component can be used, for example.

Alternatively, a layer containing a conductive metal oxide can be used as the second conductive film. Examples of the conductive metal oxide are indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), an alloy of indium oxide and tin oxide (In2O3—SnO2, referred to as ITO), an alloy of indium oxide and zinc oxide (In2O3—ZnO), and such a metal oxide material containing silicon oxide.

The second conductive film may be formed by stacking films applicable to the second conductive film.

Then, a third photolithography process is carried out: a third resist mask is formed over the second conductive film, the second conductive film is selectively etched with the use of the third resist mask to form the conductive layers405and406, and the third resist mask is removed (seeFIG. 7C). The conductive layers405and406each serve as a source electrode or a drain electrode of the transistor.

Next, the oxide insulating layer407is formed over the oxide semiconductor layer403, the conductive layer405, and the conductive layer406. At this time, the oxide insulating layer407is formed in contact with part of the top surface of the oxide semiconductor layer403.

The oxide insulating layer407can be formed to a thickness of at least 1 nm using a method by which an impurity such as water or hydrogen is not introduced into the oxide insulating layer407, such as sputtering. If hydrogen is mixed into the oxide insulating layer407, entry of hydrogen to the oxide semiconductor layer or extraction of oxygen in the oxide semiconductor layer by hydrogen might cause the backchannel of the oxide semiconductor layer to have lower resistance (to have an n-type conductivity), so that a parasitic channel may be formed. Therefore, in order to form the oxide insulating layer407containing as little hydrogen as possible, it is preferable that a method in which hydrogen is not used be employed for forming the oxide insulating layer407.

For example, a 200-nm-thick silicon oxide film can be formed as the oxide insulating layer407by sputtering. The substrate temperature at the time of deposition is in the range of room temperature to 300° C. Examples of the atmosphere in which the oxide insulating layer407is formed are a rare gas (typically argon) atmosphere, an oxygen atmosphere, and a mixed atmosphere of a rare gas and oxygen.

As a target for forming the oxide insulating layer407, a silicon oxide target or a silicon target can be used, for example. As a sputtering gas used for forming the oxide semiconductor layer407, a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydride are removed is preferably used, for example.

Before the oxide insulating layer407is formed, plasma treatment with the use of a gas of N2O, N2, Ar, or the like may be performed to remove water or the like adsorbed on an exposed surface of the oxide semiconductor layer403. In the case where plasma treatment is performed, the oxide insulating layer407that is in contact with part of the top surface of the oxide semiconductor layer403is preferably formed without exposure to the air.

Moreover, after the oxide insulating layer407is formed, second heat treatment (preferably at temperatures in the range of 200° C. to 400° C., for example, in the range of 250° C. to 350° C.) can be performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, the second heat treatment can be performed at 250° C. for one hour in a nitrogen atmosphere. In the second heat treatment, heat is applied while part of the top surface of the oxide semiconductor layer403is in contact with the oxide insulating layer407.

When a silicon oxide layer having a lot of defects is used as the oxide insulating layer407, impurities such as hydrogen, moisture, hydroxyl groups, or hydride contained in the oxide semiconductor layer403are diffused into the oxide insulating layer407with heat treatment performed after formation of the silicon oxide layer, so that the impurities contained in the oxide semiconductor layer can be further reduced. Note that a doping process using oxygen or halogen (e.g., fluorine or chlorine) may be performed after the second heat treatment. For the doping process, plasma doping with inductively coupled plasma is preferably employed. With the doping process, hydrogen in the oxide semiconductor layer403is extracted by oxygen or halogen and removed. Further, the doping process can produce a similar effect when performed before the second heat treatment, before formation of the oxide insulating layer407, before formation of the conductive layers405and406, before the first heat treatment, or before formation of the oxide semiconductor layer403. In addition, when doping is performed with high-density plasma generated using microwaves (e.g., a frequency of 2.45 GHz), the interface state density between the oxide semiconductor layer403and the insulating layer402can be reduced and interface characteristics can be favorable.

The protective insulating layer409may be further formed over the oxide insulating layer407. As the protective insulating layer409, an inorganic insulating layer such as a silicon nitride layer, an aluminum nitride layer, a silicon nitride oxide layer, or an aluminum nitride oxide layer can be used, for example. Alternatively, the protective insulating layer409can be a stack of layers of any of the materials applicable to the protective insulating layer409. For example, the protective insulating layer409can be formed by RF sputtering. RF sputtering is preferably used as a film formation method of the protective insulating layer409because of its high productivity.

After the protective insulating layer409is formed, heat treatment may be further performed at 100° C. and 200° C. for 1 hour to 30 hours in the air. This heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100° C. to 200° C. and then decreased to a room temperature.

Through the above steps, impurities such as hydrogen, moisture, hydroxyl groups, or hydride (also referred to as a hydrogen compound) can be removed from the oxide semiconductor layer, and in addition, oxygen can be supplied to the oxide semiconductor layer. Accordingly, the oxide semiconductor layer can be purified. The transistor including the purified oxide semiconductor layer is manufactured through the above process.

Note that the structure of the transistor is not limited to that illustrated inFIG. 7D. The transistor inFIG. 7Dhas a bottom-gate structure, a channel-etch structure, and a single-gate structure. Alternatively, the transistor may have a top-gate structure. Moreover, the transistor may have a channel protective structure instead of a channel-etch structure and/or a multi-gate structure instead of a single-gate structure. Even when the transistor has a different structure, layers included in the transistor can be formed using the methods for forming the layers in the transistor inFIG. 7Das appropriate.

The transistor including the purified oxide semiconductor layer in this embodiment was subjected to a bias temperature test (BT test) at 85° C. with 2×106V/cm for 12 hours. As a result, electrical characteristics of the transistor hardly changed, which suggested that the transistor has stable electrical characteristics.

The carrier concentration of the purified oxide semiconductor layer in this embodiment can be lower than 1×1012/cm3and still lower than 1×1011/cm3; thus, change in characteristics due to temperature variation can be suppressed.

The transistor including the purified oxide semiconductor layer in this embodiment has electrical characteristics of much lower off-state current than a transistor including silicon or the like. For example, in the transistor including the purified oxide semiconductor layer, the off-state current at room temperature (per channel width of 1 μm) can be 1 aA/μm (1×10−18A/μm) or lower, and further can be 100 zA/μm (1×10−19A/μm) or lower.

In the transistor including the purified oxide semiconductor layer in this embodiment, the off-state current does not exceed the above-described limit even when the temperature changes. For example, the off-state current of the transistor can be 100 zA/μm or lower even when the temperature of the transistor is 150° C.

As has been described, the off-state current can be extremely low in the transistor in which a channel formation region is formed using the purified oxide semiconductor layer. Therefore, charge stored at one of a source and a drain of the transistor can be retained for a long time.

For example, when the above transistor is used as the transistor Ts in the pixel PX inFIG. 6B, variation in display state of the pixel due to the off-state current of the transistor Ts can be suppressed; thus, a retention period of a unit pixel corresponding to one write operation of a video signal can be made longer. Therefore, the interval between write operations of video signals can be prolonged. For example, the interval between write operations of video signals can be 1 second or longer, preferably 60 seconds or longer, further preferably 600 seconds or longer. In addition, when a video signal is not written, a circuit that operates at the time of writing a video signal can be stopped; thus, power consumption can be further reduced as the interval between write operations of video signals is longer. In other words, the load of the display panel can be reduced.

Furthermore, when the above transistor is used as the transistor Tr in the DC-DC converter circuit101inFIG. 1Aand the like, the off-state current can be extremely low, so that the output voltage of the DC-DC converter circuit101can be stable. That is, the reliability of the DC-DC converter circuit101can be improved.

EXPLANATION OF REFERENCES

This application is based on Japanese Patent Application serial No. 2010-116934 filed with Japan Patent Office on May 21, 2010, the entire contents of which are hereby incorporated by reference.