Display device with built-in touch sensors

A display device with built-in touch sensors comprises: a display panel with built-in touch sensors; and a touch driver that converts a sensed voltage of the touch sensors into sensed data, wherein the touch driver comprises: an enable signal generator that compares the sensed voltage with a preset offset voltage and outputs an enable signal at a first level if the sensed voltage is higher than or equal to the offset voltage and outputs the enable signal at a second level if the sensed voltage is lower than the offset voltage; and an analog-to-digital converter that converts the sensed voltage into the sensed data when the enable signal is at the first level.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of Korean Patent Application No. 10-2017-0153999, filed on Nov. 17, 2017, which is incorporated herein by reference for all purposes as if fully set forth herein.

BACKGROUND

Technical Field

The present disclosure relates to a display device with built-in touch sensors.

Description of the Related Art

In recent years, flat-panel displays (or display devices) that can be made in large sizes, are cheap, and offer high display quality (video representation, resolution, brightness, contrast ratio, color reproducibility, etc.) are being actively developed, in order to meet the need for display devices capable of properly displaying multimedia content, along with multimedia development. For such flat-panel displays, various input devices, such as a keyboard, a mouse, a trackball, a joystick, a digitizer, etc., may be used to configure an interface between a user and a display device.

Recently, a touch sensor was proposed which detects an input when the user enters information while viewing the display device by directly touching the screen with their hand or a pen or moving it near the screen.

Touch sensors for use in display devices may be implemented as in-cell touch sensors that are embedded in a display panel. An in-cell touch display uses a method in which a touch sensor's touch electrode and the display panel's common electrode are used together. Here, driving is done in a time-sharing manner, separately in a display period and a touch driving period.

Since the display panel and the touch sensors are driven in a time-sharing manner, the driving time is not sufficient. Moreover, the lack of time for driving the touch sensors leads to a touch sensitivity problem. A long touch driving period is needed to drive the touch sensors when an analog digital converter converts a sensed voltage from a touch sensor into sensed data. Increasing the number of analog digital converters to reduce the touch driving period has some disadvantages, such as high costs and making the display device larger in size.

BRIEF SUMMARY

An exemplary embodiment of the present disclosure provides display device with built-in touch sensors comprises: a display panel with built-in touch sensors; and a touch driver that converts a sensed voltage of the touch sensors into sensed data, wherein the touch driver comprises: an enable signal g enerator that compares the sensed voltage with a preset offset voltage and outputs an enable signal at a first level if the sensed voltage is higher than or equal to the offset voltage and outputs the enable signal at a second level if the sensed voltage is lower than the offset voltage; and an analog-to-digital converter that converts the sensed voltage into the sensed data when the enable signal is at the first level.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the attached drawings. Throughout the specification, like reference numerals denote substantially like components. In describing the present disclosure, a detailed description of known functions or configurations related to the present disclosure will be omitted when it is deemed that they may unnecessarily obscure the subject matter of the present disclosure. The terms and names of elements used herein are chosen for ease of description and may be different from the names of parts used in actual products.

FIG. 1is a view of a display device with built-in touch sensors according to the present disclosure.FIG. 2is a view showing a display panel.FIG. 3is a view showing part of a display area shown inFIG. 2. Although individual touch sensors and sensing lines inFIGS. 2 and 3are indicated by the respective reference numerals, they will be referred to as touch sensors TC and sensing lines TW in the detailed description when commonly designated regardless of their position.

Referring toFIGS. 1 to 3, a display device with built-in touch sensors according to the present disclosure comprises a display panel100, a host system105, a timing controller110, a data driver120, a gate driver130, a touch driver200, and a touch coordinate generator300.

The display panel100comprises pixels P and touch sensors TC. The display panel100comprises an upper substrate and a lower substrate that face each other, with a liquid crystal layer LC in between. A pixel array on the display panel100comprises data lines DL, gate lines GL, thin-film transistors TFT formed at the intersections of the data lines DL and the gate lines GL, pixel electrodes5connected to the thin-film transistors TFT, and storage capacitors Cst connected to the pixel electrodes5. The thin-film transistors TFT turn on in response to gate pulses from the gate lines GL, and supply the pixel electrodes5with data voltages applied through the data lines DL. A liquid crystal layer LC is driven by the voltage difference between the data voltages stored in the pixel electrodes5and a common voltage Vcom applied to a touch common electrode7to adjust the amount of light transmission.

The touch sensors TC are connected to a plurality of pixels, and implemented as capacitive touch sensors to sense touch input. A plurality of pixels P are coupled to each touch sensor TC. The common electrode7is coupled to each touch sensor TC, and, as a result, the area occupied by the common electrode7may be designated as the touch sensors TC. One sensing line TW is allocated and connected to each touch sensor TC. For example, the sensing line TW[1,1] in the first row and first column is connected to the touch sensor TC[1,1] in the first row and first column, and the sensing line TW[1,2] in the first row and second column is connected to the touch sensor TC[1,2] in the first row and second column.FIG. 2depicts touch sensors TC arranged in i rows and j columns.

The common electrode7is supplied with a common voltage VCOM, which is a reference voltage for the pixels, during a display period, and is supplied with a touch drive voltage during a touch driving period.

The timing controller110receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a main clock MCLK, etc., from a host system105, and synchronizes the operation timings of the data driver120and gate driver130. Gate timing control comprise a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, etc. Data timing control signals comprise a source sampling clock SSC, a source output enable signal SOE, etc.

The host system105may be implemented as any one of the following: a television system, a set-top box, a navigation system, a DVD player, a Blue-ray player, a personal computer PC, a home theater system, and a phone system. The host system105comprises a system-on-chip (SoC) with a scaler embedded in it, and converts digital video data RGB of an input image into a format suitable for display on the display panel DIS. The host system105transmits the timing signals Vsync, Hsync, DE, and MCLK, along with the digital video data, to the timing controller110. Moreover, the host system105executes an application program associated with coordinate information (Txy) of touch data input from the touch coordinate generator300.

The data driver120receives image data from the timing controller110and converts it to positive/negative gamma compensation voltages and outputs positive/negative data voltages. The data voltages are supplied to the data lines DL.

The gate driver130sequentially supplies gate pulses to the gate lines GL under the control of the timing controller110. The gate pulses output from the gate driver130are synchronized with the data voltages. The gate driver130may be directly formed on the lower substrate of the display panel100, along with the pixel array, through a gate-in-panel (GIP) process.

The touch driver200receives a sensed voltage from a touch sensor TC, and converts the sensed voltage into digital sensed data Tdata. The touch driver200transmits the sensed data Tdata obtained by driving the touch sensor TC to the touch coordinate generator300.

The touch coordinate generator300executes a preset touch recognition algorithm. The touch recognition algorithm compares touch raw data received from a touch sensor TC sensed with a predetermined threshold value, and identifies the touch raw data as touch input data obtained from touch sensors TC at a touch input position if the touch raw data is higher than the threshold value. The touch recognition algorithm allocates an identification code to each touch input data that is higher than the threshold value, and calculates the coordinates of each touch input position. The touch coordinate generator300may transmit to the host system105the identification code and touch coordinate information Txy of each touch input data.

The timing controller110, data driver120, gate driver130, touch driver200, and touch coordinate generator300may be mounted in one integrated circuit IC and bonded to the display panel100, as shown inFIG. 2

FIG. 4is a view showing the configuration of a touch driver according to the present disclosure.

Referring toFIG. 4, the touch driver200according to the present disclosure comprises a multiplexer Mux, an enable signal generator210, a multiplexer controller220, an ADC controller230, and an analog-to-digital converter (hereinafter, ADC)240.

The multiplexer Mux comprises first to nth switches M1to Mn that selectively connect channels CH1to CHn and a multiplexer output end Mout. Each of the channels CH1to CHn is connected to a sensing line TW and receives a sensed voltage Vsen from the sensing line TW. If there are i×j touch sensors TC, the number (n) of channels CH1to CHn is i×j. First to nth switches M1to Mn of the multiplexer Mux connect one of the sensing lines TW and the enable signal generator210, in response to an enable signal EN outputted from the multiplexer controller220.

The enable signal generator210compares a sensed voltage, which may also be called a sensed voltage Vsen, outputted through the multiplexer Mux and obtained by a certain sensing line TW, with an offset voltage Vofs, that can also be termed a threshold voltage or a reference voltage. The enable signal generator determines the voltage level of the enable signal EN based on the comparison with the threshold voltage, namely, Vofs, and the sensed voltage Vsen. The enable singal EN has a first voltage level or second voltage level depending on the relative values of the sensed voltage Vsen and offset voltage Vofs. In this specification, a description will be given with respect to an exemplary embodiment in which, if the sensed voltage Vsen is higher than or equal to the offset voltage Vofs, the enable signal generator210outputs an enable signal EN at high level, which is a first voltage level, and if the sensed voltage Vsen is lower than the offset voltage Vofs, the enable signal generator210outputs an enable signal EN at low level, which is a second voltage level.

The value of the offset voltage Vofs is selected and then set based on the desired sensitity of the system to being touched. It is set to be lower than a voltage level at which the ADC240regards the sensed voltage Vsen as being valid touch data Tdata. If the offset voltage Vofs is set too low, the number of operations of the ADC240increases and many signals are output as being touches which might not be valid touches. If the offset voltage Vof is high, sensitivity may be degraded and a valid touch might be not recongized. The offset voltage Vofs may be set within a range in which the number of operations and outputs as touches from the ADC240can be efficiently reduced without degrading sensitivity.

The multiplexer controller220outputs switching control signals SQ in response to an enable signal EN. The switching control signals SQ control the operation of the switches M1to Mn. A detailed configuration of the multiplexer controller220will be described below.

ViewingFIG. 4, the ADC controller230receives an enable signal EN and outputs an ADC control signal S_a. The ADC control signal S_a controls the operation of the ADC240. An output period of the ADC control signal S_a varies with the voltage level of the enable signal EN. The output period of the ADC control signal S_a when the enable signal EN is applied at high level is set longer than the output period of the ADC control signal S_a when the enable signal EN is applied at low level. If the enable signal EN is applied at a high level, the sensed voltage Vsen may be estimated to be a voltage obtained by changing the sensed voltage Vsen by an intended touch operation by a user. Thus, the ADC240needs to change the sensed voltage Vsen to touch data Tdata. Accordingly, if the enable signal EN is at high level, the ADC control signal S_a has an output period in which the ADC240can be run during one sensed period1T. On the contrary, if the enable signal EN is at low level, the sensed voltage Vsen may not be regarded as touch operation, so the ADC240does not need to be run. Thus, the controller230may reduce the time needed to sense all channels CH1to CHn of the display panel100by reducing the ADC output period.FIG. 5is a view showing a multiplexer controller.

Referring toFIG. 5, the multiplexer controller220comprises a counter221, a clock output part223, and a shift register225.

The counter221receives an enable signal EN and counts the number of times the enable signal EN is inputted at low level during a touch driving period. The counter221outputs a clock selection control signal SC at the point in time when the enable signal EN is inputted. The clock selection control signal SC varies depending on the number of times the enable signal EN is inputted at low level. The clock selection control signal SC may comprise first to twelfth clock selection control signals SC1to SC12, as shown in Table 1 to be described later. The counter221applies an initial clock selection control signal SC to the clock output part223at the point in time when the touch driving period starts. The counter221maintains the output of the first clock selection control signal SC1while the enable signal EN is not inverted to low level.

The clock output part223receives the first to twelfth clock signals SC1to SC12and the clock selection control signal SC and outputs a control clock signal CCLK.

The shift register225receives a start signal VST and a control clock signal CCLK outputted from the clock output part223, and charges output nodes Q1to Qn with a turn-on voltage. In this specification, a description will be given with respect to an exemplary embodiment in which, when the output nodes Q1to Qn are turned on at high-level voltage, the output nodes Q1to Qn output switch control signals SQ1to SQn of the turn-on voltage.

A first switch control signal SQ1outputted from the first output node Q1controls the operation of the first switch M1, and a second switch control signal SQ2outputted from the second output node Q2controls the operation of the second switch M2. Likewise, an nth switch control signal SQn outputted from the nth output node Mn controls the operation of the nth switch Mn. The charging period of each of the output nodes Q1to Qn varies with the control clock signal CCLK.

FIG. 6is a view showing first to twelfth clock signals supplied to the clock output part223.

Referring toFIG. 6, one cycle of each of the first to twelfth clock signals CLK1to CLK12is set longer than or equal to one sensed period1T and has a phase difference of 1/12 of one cycle. One sensed period is set longer than the time it takes for the ADC240to convert a sensed voltage Vsen received from one channel CH into touch data Tdata.

Table 1 is a table showing clock selection control signals SC the counter221outputs relative to the number of times the enable signal EN falls.

TABLE 1Number of times EN falls01234567891011Sc183105127294116

Referring to Table 1, the clock selection control signals SC comprise first to twelfth clock selection control signals SC. For example, the counter221outputs a first clock selection control signal SC1when the enable signal EN falls for the first time, and outputs a second clock selection control signal SC2when the enable signal EN falls for the second time. Likewise, the counter221outputs an eleventh clock selection control signal SC11when the enable signal EN falls for the eleventh time.

As in Table 1, when the enable signal EN falls, the counter221selects a clock selection control signal SC to select a clock signal for shortening a low-level period of the control clock signal CCLK. Accordingly, the clock selection control signal SC selected by the counter221may vary with the phase and cycle of the clock signal provided to the clock output part223.

The clock output part223selects one of the first to twelfth clock signals CLK1to CLK12in response to a clock selection control signal SC. The clock output part223receives a kth clock selection control signal SCk (k is a natural number less than or equal to 12) and outputs a kth clock signal CLKk. For example, the clock output part223receives the first clock selection control signal SC1and outputs the first clock signal CLK1, and receives the twelfth clock selection control signal SC12and outputs the twelfth clock signal CLK12.

FIG. 7is a view showing control clock signals relative to clock selection control signals outputted from the counter.

Referring toFIG. 7, when the enable signal EN continues to maintain the high level, the counter221applies the first clock selection control signal SC1to the clock output part223. The clock output part223applies the first clock signal CLK1to the shift register225, in response to the first clock selection control signal SC1. When the enable signal EN falls to low level for the first time, the counter221outputs a clock selection control signal SC for selecting a clock signal whose rising edge timing is the fastest after the application of the enable signal EN. For example, if clock signals have 12 phases as shown inFIG. 6, an eighth clock signal CLK8is a clock signal whose rising edge timing is the fastest at the point in time when the enable signal EN is applied. Accordingly, when the first enable signal EN is applied, the counter221applies the eighth clock selection control signal SC8to the clock output part223. The clock output part223applies the eighth clock signal CLK8to the shift register225, in response to the eighth clock selection control signal SC8.

Likewise, a third clock signal CLK3is a clock signal whose rising edge timing is the fastest at the point in time when the enable signal EN falls for the second time. Accordingly, when the enable signal EN falls to low level for the second time, the counter221applies the third clock signal CLK3to the shift register225, in response to a third clock selection control signal SC3.

As a result, the clock output part223outputs the first clock signal CLK1at the point in time when the touch driving period starts, and sequentially outputs the eighth clock signal CLK8and the third clock signal CLK3when the enable signal EN falls to low level.

FIGS. 8 to 10are views showing an exemplary embodiment in which the shift register charges the output nodes. InFIGS. 8 to 10, the first timing refers to the point in time when the touch driving period starts.

FIG. 8is a view showing an exemplary embodiment in which the shift register charges the output nodes when the enable signal continues to maintain the high level.

Referring toFIG. 8, the shift register225receives a start signal VST at the rising edges of a control clock signal CCLK at a first timing t1. When the enable signal EN continues to maintain the high level, the control clock signal CCLK applied to the shift register225maintains the state of the first clock signal CLK1. The shift register225charges the first output node Q1when the start signal VST and the control clock signal CCLK are in synchronization with each other.

The control clock signal CCLK rises for the second time at a second timing t2. At the second timing t2, the shift register225discharges the first output node Q1to low level and starts to charge the second output node Q2. In this way, at each rising edge of the control clock signal CCLK, the shift register225discharges a (r−1)th output node Q(r−1) (which is a natural number that is 1<r<12) and charges the Q(r−1)th output node Q(r−1).

FIG. 9is a view showing an exemplary embodiment in which the shift register charges the output nodes when the enable signal falls to low level two times.

Referring toFIG. 9, the shift register225receives a start signal VST at the first timing t1, in synchronization with the rising edge of the control clock signal CCLK.

As discussed above, the low-level period of the control clock signal CCLK becomes shorter when the enable signal falls to low level. As a result, the rising edge of the control clock signal CCLK comes faster. That is, the charging period of the second output node Q2becomes shorter as the interval between the second timing t2and the third timing t3becomes shorter. Likewise, the low-level period of the control clock signal CCLK becomes shorter at a fourth timing t4when the enable signal EN falls for the second time. As a result, the charging period of the third output node Q3becomes shorter. In this way, the charging period of the second output node Q2and third output node Q3becomes shorter when the enable signal EN falls to low level.

Since the enable signal EN maintains the high level after the fourth timing t4, the cycle of the control clock signal CCLK is not changed. As a result, the charging period of the fourth output node Q4and fifth output node Q5has one sensed period1T after the fourth timing t4.

FIG. 10is a view showing an exemplary embodiment in which the shift register charges the output nodes when the enable signal falls to low level three times or more.

Referring toFIG. 10, the shift register225receives a start signal VST at a first timing t1, in synchronization with the rising edge of the control clock signal CCLK.

The low-level period of the control clock signal CCLK becomes shorter when the enable signal falls to low level. As a result, the rising edge of the control clock signal CCLK comes faster. That is, the charging period of the second output node Q2becomes shorter as the interval between the second timing t2and the third timing t3becomes shorter. Likewise, the low-level period of the control clock signal CCLK becomes shorter at a fourth timing t4when the enable signal EN falls for the second time. As a result, the charging period of the third output node Q3becomes shorter. In this way, the charging period of the second output node Q2, third output node Q3, fourth output node Q4, and fifth output node Q5becomes shorter when the enable signal EN repeatedly falls to low level.

FIGS. 11A and 11Bshows output periods of multiplexer control signals and an ADC control signal.FIG. 11Ais a view showing output periods of multiplexer control signals and an ADC control signal when sensed voltages of first and second channels are higher than or equal to an offset voltage.FIG. 11Bis a view showing output periods of multiplexer control signals and an ADC control signal when a sensed voltage of the first channel is higher than or equal to the offset voltage and a sensed voltage of the second channel is lower than the offset voltage.

Referring toFIGS. 11A and 11B, an ADC control signal S_a corresponds to output periods of multiplexer control signals SQ1and SQ2. As shown inFIG. 11A, when the enable signal EN is at high level, the output periods of multiplexer control signals SQ1and SQ2correspond to one sensed period1T. As shown inFIG. 11B, when the enable signal EN is at low level in the sensed process of the second channel, the output period1T′ of the multiplexer control signal SQ12is shorter than one sensed period1T. Accordingly, when the enable signal EN is at high level, the output period of the ADC control signal S_a corresponds to one sensed period1T, and when the enable signal EN is at low level, the output period1T of the ADC control signal S_a is shorter than one sensed period1T. As discussed above, in the present disclosure, touch data Tdata is obtained only from touch sensors TC that are assumed to have touch input, rather than converting sensed voltages from every touch sensor TC into touch data Tdata. Moreover, when a sensed voltage Vsen is obtained from touch sensors TC that are regarded as having no touch input, the ADC240is not run during the touch driving period. Thus, in the present disclosure, the total operation time of the ADC240is not reduced. As a result, a plurality of touch sensors TC may be driven using a small number of ADCs240. Since the touch sensors TC are driven using a smaller number of ADCs240compared to the area of the display panel100, the present disclosure is more suitable for a large-sized display panel100. A large-sized display panel100can be driven by fewer ADC's240, saving area, power and manufacturing costs.

As seen above, a display device with built-in touch sensors according to the present disclosure obtains touch data only from touch sensors that are assumed to have touch input, rather than converting sensed voltages from every touch sensor into touch data. Moreover, when a sensed voltage is obtained from touch sensors that are regarded as having no touch input, the ADC is not run. Thus, in the present disclosure, the total operation time of the ADC is not reduced during the touch driving period. As a result, a plurality of touch sensors may be driven using a small number of ADCs.