Data writing method and data storage device

The invention provides a data writing method for a flash memory. First, a target block for storing write data is selected from a plurality of blocks of the flash memory. A target pair page is then selected from a plurality of pair pages of the target block according to a pair page record table, wherein the pair page comprises a strong page and a weak page. The flash memory is then directed to write a data page of the write data to the strong page of the target pair page. The flash memory is then also directed to write first predetermined data to the weak page of the target pair page, wherein the weak page storing the first predetermined data extends the data duration of the strong page of the target pair page. Selecting of the target pair page, writing of the data page, and writing of the first predetermined data are repeated until all of the write data are written to the target block.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of Taiwan Patent Application No. 99114905, filed on May 11, 2010, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to flash memories, and more particularly to data writing of flash memories.

2. Description of the Related Art

Flash memories are divided into single level cell (SLC) flash memories, multi level cell (MLC) flash memories, and triple level cell (TLC) flash memories. A memory cell of an SLC flash memory stores a single data bit. On the other hand, a memory cell of an MLC flash memory stores two data bits, and a memory cell of a TLC flash memory stores three data bits. If an SLC flash memory has the same number of memory cells with those of an MLC flash memory and a TLC flash memory, the data capacity of the MLC flash memory is double that of the SLC flash memory, and the data capacity of the TLC flash memory is triple of that of the SLC flash memory.

A memory cell of an MLC flash memory stores two data bits, wherein one of the data bits is a least significant bit (LSB), and the other of the data bits is a most significant bit (MSB). A plurality of pages of the MLC flash memory are therefore divided into a plurality of pair pages, and each pair page comprises a strong page and a corresponding weak page, wherein the strong page comprises the least significant bits of a set of memory cells, and the weak page comprises the most significant bits of the same set of memory cells. Because the strong page and the weak page of a pair page store data in a single set of memory cells, the data content stored in the strong page affects the data content stored in the corresponding weak page, and the data content stored in the weak page affects the data content stored in the corresponding strong page.

A memory cell of a TLC flash memory stores three data bits, wherein one of the data bits is a least significant bit (LSB), another of the data bits is a center significant bit (CSB), and the other of the data bits is a most significant bit (MSB). A plurality of pages of the MLC flash memory are therefore divided into a plurality of pair pages, and each pair page comprises a strong page, a weak page, and a very weak page, wherein the strong page comprises the least significant bits of a set of memory cells, the weak page comprises the center significant bits of the same set of memory cells, and the very weak page comprises the most significant bits of the same set of memory cells. Because the strong page, the weak page, and the very weak page of a pair page store data in a single set of memory cells, the data content stored in the strong page affects the data content stored in the corresponding weak page and very weak page, and the data content stored in the weak page and the very weak page affects the data content stored in the corresponding strong page.

Referring toFIG. 1, a schematic diagram of a plurality of pair pages of a block of a TLC flash memory is shown. The block of the TLC flash memory comprises 192 pages with page numbers ranging from 0˜191, wherein every three pages form a pair page, and the block, therefore, comprises 64 pair pages. A first pair page comprises pages with page numbers 0, 4, and 10, wherein the page 0 is a strong page, the page 4 is a weak page, and the page 10 is a very weak page. A second pair page comprises pages with page numbers 1, 5, and 11, wherein the page 1 is a strong page, the page 5 is a weak page, and the page 11 is a very weak page. A third pair page comprises pages with page numbers 2, 8, and 16, wherein the page 2 is a strong page, the page 8 is a weak page, and the page 16 is a very weak page.

When data is stored in a flash memory, the data can only be read from the flash memory with a limited frequency threshold. If the data is read from the flash memory with a frequency greater than the frequency threshold, read-out data read from the flash memory would have a high error rate. The frequency threshold is referred to as data retention. For managing the data access of the flash memory, a controller stores important system data in the flash memory. To maintain the correctness of the important system data, the data retention of the system data must be extended. A data writing method capable of extending data retention of system data for a flash memory is therefore required.

BRIEF SUMMARY OF THE INVENTION

The invention provides a data writing method for a flash memory. First, a target block for storing write data is selected from a plurality of blocks of a flash memory. A target pair page is then selected from a plurality of pair pages of the target block according to a pair page record table, wherein the pair page comprises a strong page and a weak page. The flash memory is then directed to write a data page of the write data to the strong page of the target pair page. The flash memory is then also directed to write first predetermined data to the weak page of the target pair page, wherein the weak page storing the first predetermined data extends the data duration of the strong page of the target pair page. Selecting of the target pair page, writing of the data page, and writing of the first predetermined data are repeated until all of the write data are written to the target block.

The invention provides a data writing method for a flash memory. First, a target block for storing write data is selected from a plurality of blocks of the flash memory. A target page is then selected from a plurality of pages of the target block. Whether the target page is a strong page is then determined according to a pair page record table. When the target page is the strong page, the flash memory is directed to write a data page of the write data to the target page. When the target page is not the strong page, the flash memory is directed to write predetermined data to the target page, wherein the weak page storing the first predetermined data extends the data duration of the strong page of the target pair page. Selecting of the target page, determining of whether the target page is the strong page, and writing of the data page or writing of the predetermined data are then repeated until all of the write data are written to the target block.

The invention also provides a data storage device. In one embodiment, the data storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each of the blocks comprises a plurality of pair pages, and each of the pair pages comprises a strong page and a weak page. The controller is coupled to the flash memory, selects a target block from a plurality of blocks of the flash memory, writes user data or system data to the strong pages of the target block, and writes first predetermined data to the weak pages of the target block, wherein the weak pages storing the first predetermined data extends the data duration of the corresponding strong pages.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 2, a block diagram of a data storage device204capable of extending data retention of important data according to the invention is shown. The data storage device204is coupled to a host202. In one embodiment, the data storage device204comprises a controller212and a flash memory214. In one embodiment, the flash memory214is an MLC flash memory or a TLC flash memory. The flash memory214comprises a plurality of blocks221˜22K for storing data. Each block comprises a plurality of pages. For example, the block221comprises pages221a˜221n, and the block22kcomprises pages22ka˜22kn. The pages of each block can be further divide into a plurality of pair pages. When the flash memory214is an MLC flash memory, each pair page comprises a strong page and a weak page. When the flash memory214is a TLC flash memory, each pair page comprises a strong page, a weak page, and a very weak page.

Before the controller212writes target data to the flash memory214, the controller212determines whether the target data is important data. If the target data is ordinary data rather than important data, the controller212writes the target data to the flash memory214according an ordinary procedure. For example, if the controller212wants to write ordinary data to the block221, the controller212directs the flash memory214to sequentially write to the pages221a˜221nof the block221without determining whether the pages221a˜221nare strong pages, weak pages, or very weak pages. On the other hand, when the target data is important data, the controller212merely uses strong pages of a block to store the target data, and write predetermined data to the weak pages and the very weak pages corresponding to the strong pages, wherein the predetermined data, stored in the weak pages and the very weak pages, extends the data duration of the target data stored in the corresponding strong pages. Thus, when the important data is read from the flash memory214with a high frequency, the read-out important data still has a low error rate.

Referring toFIG. 3, a flowchart of a method300for writing data to a flash memory214according to the invention is shown. First, the controller212obtains a write data to be written to the flash memory214(step302). The write data may be user data obtained from the host202, or may be system data directly generated by the controller212. When the controller212determines the write data to be important data, the controller212must ensure the write data of long data duration. The controller212therefore selects a target block for storing the write data from a plurality of blocks221˜22k(step304). The controller212then selects a target pair page from a plurality of pages of the target block according to a pair page record table230(step306). The pair page record table230records page numbers of a plurality of pair pages of a block. In one embodiment, the pair page record table records information as shown inFIG. 1. The controller212can therefore determine whether a specific page of the block is a strong page, a weak page, or a very weak page according to the information stored in the pair page record table230.

Assume that the flash memory214is a TLC flash memory. Thus, the target pair page selected by the controller212in the step306comprises a strong page, a weak page, and a very weak page. First, the controller212directs the flash memory214to write a data page of the write data to a strong page of the target pair page (step308). The controller212then directs the flash memory214to write a first predetermined data to a weak page of the target pair page (step310), wherein the weak page storing the first predetermined data extends the data duration of the storing page storing the data page of the write data. In one embodiment, the first predetermined data is a data page filled with merely bits “1”. The controller212then directs the flash memory214to write a second predetermined data to a very weak page of the target pair page (step312), wherein the very weak page storing the second predetermined data extends the data duration of the storing page storing the data page of the write data. In one embodiment, the second predetermined data is a data page filled with merely bits “1”. In another embodiment, the second predetermined data is a data page filled with merely bits “0”. Because only one data page of the write data has been written to the flash memory214, the controller212selects another pair page from the flash memory214as a new target pair page according to the step306, and respectively writes a subsequent data page, the first predetermined data, and the second predetermined data to the strong page, the weak page, and the very weak page of the new target pair page according to the steps308,310, and312. The steps306˜312are repeatedly performed until all data pages of the write data has been written to the target block (step314). If the flash memory214is an MLC flash memory, the controller212can still write data to the flash memory214according to the method300shown inFIG. 3, except that the step312is omitted.

At steps308,310, and312, the controller212respectively write the write data, the first predetermined data, and the second predetermined data to a strong page, a weak page, and a very weak page of a target pair page of the flash memory214. In one embodiment, the controller212sends a Joint Page Programming Command to the flash memory214to perform the steps308,310, and312. First, the controller212sends a first portion code 0x82 of the Joint Page Programming Command, a code 0x13, and the address of the strong page to the flash memory214to direct the flash memory214to write the data page of the write data to the strong page. The controller212then sends a second portion code 0x83 of the Joint Page Programming Command, the code 0x13, and the address of the weak page to the flash memory214to direct the flash memory214to write the first predetermined data to the weak page. The controller212then sends a third portion code 0x84 of the Joint Page Programming Command, the code 0x13, and the address of the very weak page to the flash memory214to direct the flash memory214to write the second predetermined data to the very weak page.

Referring toFIGS. 4A,4B, and4C, a plurality of stages of data writing of the flash memory214according to an embodiment of the invention is shown. Assume that the controller212obtains important data to be written to a target block of the flash memory214, and the target block comprises a plurality of pages P0˜P191. The pages P0·P191of the target block is divided into a plurality of pair pages, wherein the pages P0, P4, and P10are respectively a strong page, a weak page, and a very weak page of a first pair page, the pages P1, P5, and P11are respectively a strong page, a weak page, and a very weak page of a second pair page, and the pages P2, P8, and P16are respectively a strong page, a weak page, and a very weak page of a third pair page. First, the controller212determines to write data to the first pair page of the target block. The controller212therefore writes a first data page D1of the important data to the strong page P0of the first pair page, then writes first predetermined data DAto the weak page P4of the first pair page, and then writes second predetermined data DBto the very weak page P10of the first pair page, as shown inFIG. 4A.

The controller212then determines to write data to the second pair page of the target block. The controller212therefore writes a second data page D2of the important data to the strong page P1of the second pair page, then writes first predetermined data DAto the weak page P5of the second pair page, and then writes second predetermined data DBto the very weak page P11of the second pair page, as shown inFIG. 4B. The controller212then determines to write data to the third pair page of the target block. The controller212therefore writes a third data page D3of the important data to the strong page P2of the third pair page, then writes first predetermined data DAto the weak page P8of the third pair page, and then writes second predetermined data DBto the very weak page P16of the third pair page, as shown inFIG. 4C. Because first predetermined data and second predetermined data are respectively written to the weak pages and the very weak pages of the first pair page, the second pair page, and the third pair page, the data duration of the data pages of the important data stored in the strong pages of the first pair page, the second pair page, and the third pair page may be therefore extended.

In one embodiment, the important data D1, D2, and D3is system data. For example, the important data D1, D2, and D3is an address or a number of error blocks in the flash memory214, or data of a link table which stores information about logical addresses and corresponding physical addresses required by the controller212to access the flash memory214. In one embodiment, the first predetermined data DAis a data page filled with bits “1”, and the second predetermined data DBis a data page filled with bits “1” or “0”. The bit contents of the first predetermined data DAand the second predetermined data DBstored in the weak pages and the very weak pages can extend the data duration of the system data D1, D2, and D3stored in the strong pages. In another embodiment, the important data is user data, such as an image file, a video file, or a text file, wherein the format of the image file may be JPG or GIF, the format of the video file may be AVI, and the format of the text file may be a WORD file.

Referring toFIG. 5, a schematic diagram of data writing of a pair page of a TLC flash memory is shown. A pair page of a TLC flash memory comprises a strong page, a weak page, and a very weak page. The controller sequentially writes data into the strong page, the weak page, and the very weak page of the pair page. First, the controller writes a least significant bit (LSB) into the strong page, wherein the least significant bit mat be a bit0or a bit1, and a memory cell written with the LSB has a voltage distribution521or522as shown inFIG. 5. The controller then writes a center significant bit (CSB) into the weak page. When the center significant bit is a bit1, the voltage distribution of the memory cell written with the CSB has a voltage distribution511or514as shown inFIG. 5. The voltage difference between the voltage distribution511and514is greatest in comparison with other voltage distributions. When the memory cell is read, the controller can therefore easily determine whether the LSB of the memory cell is a bit1or a bit0by easily identifying the voltage distribution511from the voltage distribution514. Thus, when the predetermined data written to the weak page of a pair page is a bit1, the data duration of the data bit stored in the corresponding strong page is extended.

The controller then writes a most significant bit (MSB) into the very weak page. When the most significant bit is a bit1, the voltage distribution of the memory cell written with the MSB has voltage distribution501or508as shown inFIG. 5. When the most significant bit is a bit0, the voltage distribution of the memory cell written with the MSB has voltage distribution502or507as shown inFIG. 5. The voltage difference between the voltage distribution501and508is large in comparison with other voltage distributions. When the memory cell is read, the controller can therefore easily determine whether the LSB of the memory cell is a bit1or a bit0by easily identifying the voltage distribution501from the voltage distribution508. Thus, when the predetermined data written to the weak page of a pair page is a bit1, the data duration of the data bit stored in the corresponding strong page is extended. Similarly, the voltage difference between the voltage distribution502and507is large in comparison with other voltage distributions. When the memory cell is read, the controller can therefore easily determine whether the LSB of the memory cell is a bit1or a bit0by easily identifying the distribution of the voltage502from the distribution of the voltage507. Thus, when the predetermined data written to the weak page of a pair page is a bit0, data duration of the data bit stored in the corresponding strong page is also extended.

Referring toFIG. 6, a flowchart of a data writing method600of a flash memory214according to the invention is shown. First, the controller212obtains a write data to be written to the flash memory214(step602). The write data may be user data obtained from the host202, or may be system data directly generated by the controller212. When the controller212determines the write data to be important data, the controller212must extend the data duration of the write data. The controller212therefore selects a target block for storing the write data from a plurality of blocks221˜22k(step604). The controller212then selects a target page from a plurality of pages of the target block (step606). Assume that the flash memory214is a TLC flash memory. The controller212then determines whether the target page is a strong page, a weak page, or a very weak page according to a pair page record table230(step608). In one embodiment, the pair page record table records information as shown inFIG. 1. The controller212can therefore determine whether the target page of the block is a strong page, a weak page, or a very weak page according to the information stored in the pair page record table230.

When the controller212determines the target page to be a strong page (step610), the controller212directs the flash memory to write a data page of the write data to the target page (step612). Otherwise, when the controller212determines the target page to be a weak page (step614), the controller212directs the flash memory to write the first predetermined data to the target page (step616), wherein the first predetermined data stored in the target page extends a data duration of a strong page corresponding to the target page. In one embodiment, the first predetermined data is a data page filled with bits “1”. When the controller212determines the target page to be a very weak page (step614), the controller212directs the flash memory to write the second predetermined data to the target page (step618), wherein the second predetermined data stored in the target page extends a data duration of a strong page corresponding to the target page. In one embodiment, the second predetermined data is a data page filled with bits “1”. In another embodiment, the second predetermined data is a data page filled with bits “0”. The controller212then selects a subsequent page of the target page to be a new target page (step622), and writes data to the new target page according to steps608˜618until all of the write data has been written to the target block (step620). When the flash memory214is an MLC flash memory, the controller212still writes data to the flash memory214according to the method600, wherein the step618of method600is omitted.

Referring toFIGS. 7A,7B, and7C, a plurality of stages of data writing of the flash memory214according to an embodiment of the invention is shown. Assume that the controller212obtains important data to be written to a target block of the flash memory214, and the target block comprises a plurality of pages P0˜P191. The pages P0˜P191of the target block are divided into strong pages, weak pages, and very weak pages, wherein the pages P0˜P3and P6˜P7are strong pages, the pages P4˜P5and P8˜P9are weak pages, and the pages P10˜P11and P16˜P17are very weak pages. First, the controller212determines to sequentially write data to the pages P0˜P3of the target block. The controller212therefore writes a first data page D1of the important data to the strong page P0, then writes a second data page D2of the important data to the strong page P1, then writes a third data page D3of the important data to the strong page P2, and then writes a fourth data page D4of the important data to the strong page P3, as shown inFIG. 7A.

The controller212then determines to sequentially write data to the pages P4˜P7of the target block. Because the pages P4and P5are weak pages, the controller212therefore writes first predetermined data DAto the weak pages P4and P5. Because the pages P6and P7are strong pages, the controller212therefore writes a fifth data page D5of the important data to the strong page P6, and then writes a sixth data page D6of the important data to the strong page P7, as shown inFIG. 7B. The controller212then determines to sequentially write data to the pages P8˜P11of the target block. Because the pages P8and P9are weak pages, the controller212therefore writes first predetermined data DAto the weak pages P8and P9. Because the pages P10and P11are very weak pages, the controller212therefore writes second predetermined data DBto the weak pages P10and P11, as shown inFIG. 7C. Because first predetermined data and second predetermined data are respectively written to the weak pages and the very weak pages, the data duration of the data pages of the important data stored in the corresponding strong pages is therefore extended.

In one embodiment, the important data D1, D2, and D3is system data. For example, the important data D1, D2, and D3is an address or a number of error blocks in the flash memory214, or data of a link table which stores information about logical address and corresponding physical address required by the controller212to access the flash memory214. In one embodiment, the first predetermined data DAis a data page filled with bits “1”, and the second predetermined data DBis a data page filled with bits “1” or “0”. The bit contents of the first predetermined data DAand the second predetermined data DBstored in the weak pages and the very weak pages can extend the data duration of the system data D1, D2, and D3stored in the strong pages. In another embodiment, the important data is user data, such as an image file, a video file, or a text file, wherein the format of the image file may be JPG or GIF, the format of the video file may be AVI, and the format of the text file may be a WORD file.