Method of fabricating a semiconductor device with raised diffusions and isolation

A method of forming a MOS FET in which the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The sidewalls that are used to form an LDD source and drain separate a gate contact from source and drain contacts.

TECHNICAL FIELD 
The field of the invention is that of CMOS integrated circuit processing. 
BACKGROUND ART 
In the field of integrated circuit processing, it is essential to isolate 
one transistor from a neighboring transistor or other component. The art 
currently uses a trench isolation in which a trench is etched into the 
electrically active silicon and filled with oxide, or LOCOS isolation in 
which thermal oxide is grown downwardly into the silicon. Variations on 
these schemes are well known in the art, all commonly having the factor 
that there is an insulator, usually SiO.sub.2, of a thickness sufficient 
to prevent voltage on an interconnection line above the insulator from 
inverting the silicon beneath the insulator and thereby creating a 
parasitic channel; and that all or part of the isolation is recessed to 
provide for smaller step height for the interconnection. Throughout the 
years, the art has tended to smooth topographical features in the 
isolation while maintaining protection against parasitic channel 
formation. 
Before the introduction of LOCOS, when design rules were above 5 .mu.m, a 
blanket oxide was grown over the wafer before any of the elements of the 
transistors were fabricated. Apertures were etched into the blanket 
insulation to hold the transistors. In this case, topographical features 
were severe, which caused significant reduction in yield as design ground 
rules became smaller and the step to be traversed by interconnects became 
sharper. One distinguishing feature of this old prior art work compared 
with more recent prior art work was that there was a direct line between 
adjacent transistors along the surface of the single crystal silicon. 
Since the minimum distance between transistors was on the order of 5 
.mu.m, there was considerable resistance on this path that is not present 
in modern submicron technology. 
A number of problems have also become apparent in the case of trench 
isolations, which are preferred to the old blanket approach because of 
their planar surfaces and because of the elimination of the "bird's beak" 
associated with LOCOS isolations, thereby permitting a shorter, smaller 
transverse dimension than LOCOS isolations. The approaches in the art have 
attempted to reduce step size by recessing the insulator into the single 
crystal area, with the result that there was an increased risk of creating 
defects in the single crystal material in the process of forming the 
isolation. The art has long sought a method of isolation in which the 
smallest transverse distance can be obtained without compromising the 
effectiveness of the isolation. 
SUMMARY OF THE INVENTION 
A method of forming an integrated circuit from a set of transistors, the 
sources, drains, and isolations of which are all raised above the surface 
of the single crystal silicon and includes the steps of depositing a 
blanket gate stack including the gate oxide and a set of gate layers, 
cutting through the gate stack to form isolation apertures that are filled 
with oxide, and depositing source and drain connections in apertures 
etched in the gate stack using the gate oxide as an etch stop. Sidewalls 
in the source and drain apertures provide the LDD source and drain. A 
layer of dielectric is deposited and/or grown over the source and drain 
contacts. A self-aligned gate contact is formed by selectively removing 
through the dielectric and nitride on the gate stack or an aligned contact 
is formed, leaving nitride sidewalls to isolate the gate contact from the 
source and drain connections.

BEST MODE OF CARRYING OUT THE INVENTION 
Referring now to FIG. 1, there is shown in cross-section a portion of a 
silicon integrated circuit formed in single crystal substrate 100 having a 
surface 50. The epitaxial layer 10 of the single crystal silicon has been 
previously prepared by forming N-wells and/or P-wells and with the use of 
blanket threshold implants as is conventional in the art. These 
preliminary steps will be referred to as preparing the epitaxial layer. 
The surface has been planarized in a conventional chemical-mechanical 
process and a set of three layers has been formed across the wafer. The 
set of layers is referred to as the gate stack, and denoted by the 
numerals 102, 110 and 120, in which layer 102 is the gate oxide 
(.ltoreq.100.ANG. SiO.sub.2, formed by conventional dry thermal oxidation) 
of the final transistor gates that will be used, layer 110 is a layer of 
about 150-200 nm of polycrystalline silicon (poly) doped N.sup.+, and 
layer 120 is a layer of about 100nm of nitride (Si.sub.3 N.sub.4) that 
protects layer 110. Poly layer 110 and subsequent poly layers are doped by 
ion implantation after being put down. These implants are not heated in a 
diffusion step until after a poly gate contact has been made and both the 
bit line and the word line are in place. An intervening layer 124, shown 
as a thick line, is a layer of oxide of 50-100 .ANG. formed for use as an 
etch stop when the nitride is removed. Apertures 150 have been opened in 
the gate stack in areas that will be the field isolation. An optional 
field implant may be performed at this time. A typical field implant (152) 
for a P.sup.- doped substrate might be about 5.times.10.sup.17 /cm.sup.3 
(boron). 
Referring now to FIG. 2, there are shown two isolation members of oxide 60 
which have been deposited in a conventional low pressure CVD oxide 
process, e.g. TEOS. A conventional etching process such as reactive ion 
etching (RIE) was used to cut apertures for isolation members 60 down 
through nitride 120 and poly 110, stopping on oxide 102. If oxide 102 is 
removed during the process of opening the apertures, a thin oxide layer 
may be grown to provide a stable surface under oxide 60. This layer will 
be comparable in thickness to the gate oxide, so that the isolation oxide 
does not penetrate below the gate oxide as it did in the prior art. After 
deposition, oxide isolation members 60 have been chemical-mechanically 
polished in a conventional fashion as illustrated in U.S. Pat. No. 
5,015,594, so that there is a planar surface, referred to as the isolation 
surface, in which the oxide 60 is coplanar with the top of nitride 120. 
Isolation 60 extends in front of and behind the plane of the cross section 
to isolate the cell. It is evident in this figure that this method of 
isolation provides a planar reference at the top of the gate area (in the 
center of the drawing), so that contacts from the gate or the source or 
drain may extend smoothly over the isolation without any steps. The 
portion of the gate stack that remains covers the entire active device 
area which will contain a gate electrode, a source, and a drain. 
Referring now to FIG. 3, there is shown the next step before cutting source 
and drain apertures 155 through the gate stack using the same RIE process 
as used to cut apertures for oxide 60. Photoresist 70 defines what will be 
the gate. After the etch step, oxide 102 at the bottom of the apertures 
has been stripped by a selective oxide etch, e.g. buffered HF solution 
(BHF). At this time, a light implant, the first dose of an LDD (Lightly 
Doped Drain) may be performed. A typical implant is 
.about.5.times.10.sup.14 /cm.sup.2. of arsenic or phosphorous for an 
N-channel device. 
Referring now to FIG. 4, the area is shown after the light implant has been 
made and a set of conformal sidewalls denoted collectively with the 
numerals 62 has been formed on the sides of all the apertures. These 
sidewalls are illustratively, a first layer (.apprxeq.100.ANG.) of thermal 
oxide followed by a layer (.apprxeq.400.ANG.) of nitride or CVD oxide. 
Sidewalls 62 isolate the gate stack from the strap connection that will be 
formed and also serves as the implant mask for the second source/drain 
implant. Next, a heavier source/drain implant is made, for example 
3-5.times.10.sup.15 /cm.sup.2 of As at 50-80 KeV in which sidewalls 62 
protect the LDD portion of the transistor from the heavier dose so that 
the more heavily doped areas forming the sources and drains have been 
formed without affecting the previous light dose. 
In FIG. 5, a layer of polysilicon (doped in-situ) has been deposited in the 
apertures and polished back using nitride layer 120 as a polish stop. The 
portion of this poly layer in the former aperture 155 is a contact from 
source 152 that will be connected to an interconnection line in a later 
step as a connector 115. The high degree of planarity is evident, as the 
poly contact 115 is coplanar with oxide 60. An optional insulating layer 
(oxide) 113 has been grown to protect poly contacts 115 while nitride 120 
is removed. 
In FIG. 6, nitride 120 has been etched to expose gate 110 and provide for a 
gate contact 112. A typical etchant is hot phosphoric acid. Layer 124 is 
then removed with BHF. Additional layers will be formed on top of layer 
112 to establish the lines connected to contact 115 and other 
interconnections (the "back end" processes), as is conventional. Those 
skilled in the art will readily appreciate that the process illustrated 
here can readily be applied in many circuits such as DRAMS, CPUs, SRAMS, 
video rams, application specific integrated circuits, and the like. 
An advantageous feature of the invention is that isolation 60 is formed 
above the surface of the silicon, surface 50. Referring for convenience to 
FIG. 6, it can be seen that there is a straight path along a surface 50 
between the single crystal substrate and the bottom of oxide 60 between 
the electrode on one transistor and a corresponding electrode on the other 
side of isolation 60. In the prior art of submicron critical dimension, a 
straight line on the surface was not tolerated and a shallow trench was 
typically cut to provide an insulator thickness great enough to prevent a 
channel from being induced by voltage applied to conductive lines passing 
above. Also, when the trench was cut down below the surface, any 
conductive path due to the finite conductivity of the material had to 
travel an irregular line of greater length. In LOCOS isolation, the 
thermal isolation oxide also grows down into the single-crystal substrate. 
In operation, one capacitor may be charged up to the nominal voltage of 
the device (5 volts or so) while the other is at ground providing a 
potential path for a "punch-through" leakage path to form through the 
short distance between them. In the case of the example illustrated, the 
groundrule is a nominal 0.25 micron, so that the potential for leakage is 
evident. 
Another advantage of the invention is illustrated in FIGS. 12A and 12B. 
FIG. 12A illustrates an I-V curve from a conventional transistor isolated 
with a shallow trench isolation. A shoulder is evident that results from 
the existence of a parasitic transistor on the edge of the trench. As the 
gate voltage is increased, the portion of the gate at the edge of the 
transistor causes the parasitic to turn on, so that there is a greater 
slope in the voltage range for which the parasitic is turning on. This is 
a disadvantage because there is an early "turn-on" of the device, i.e. it 
turns on at a lower gate voltage than is specified. Additionally, there is 
a gate oxide reliability exposure since it is observed that the gate oxide 
is thinner as it wraps around the corner of a shallow trench. This is one 
of several contributing causes of parasitic devices. The other causes are 
field intensification at the corner and high interface charge in the 
vertical sidewall insulator which is difficult to overcome since field 
implants strike the flat bottom of the trench in much greater 
concentration than the sides. 
In contrast, FIG. 12B illustrates a corresponding I-V curve for a 
transistor constructed according to the invention, showing a smooth curve 
with no shoulder. 
An alternative process is illustrated in FIGS. 7 and 8 showing that, after 
the step in FIG. 5, the whole gate stack (layers 120 and 110) may be 
removed and a channel implant of .apprxeq.2.times.10.sup.12 /cm.sup.2 
(boron) for short channel effects in an N-channel transistor may be made. 
After the implant, a substitute gate poly 112' is deposited. 
Another alternative is illustrated in FIGS. 9-11, in which nitride 120 is 
removed before the source/drain apertures 55 are cut and replaced with a 
second poly layer 114. A new nitride layer 121 is patterned in FIG. 10 to 
define the gate and the source/drain apertures, implants and sidewalls are 
done as before. In FIG. 11, a conformal layer of phospho-silicate glass 
(PSG) 122 has been put down to isolate the poly source/drain contacts that 
will be put down from the gate. An aperture will be opened through the PSG 
and nitride to form a gate contact behind the plane of the paper. 
Additionally, the use of poly layers in the gate stack that are implanted 
after deposition and the deferring of heat treatment to diffuse the 
implants and activate the source and drain until just before the word line 
is deposited avoids a problem in the prior art in which heat treatment of 
doped poly increased the grain size which, in turn, permitted subsequent 
oxide etch steps to penetrate along grain boundaries and damage underlying 
layers. In this process, the poly is not exposed to an oxide etch after 
the heat treatment, so the possibility of penetration does not arise. 
Referring now to FIG. 13, there is shown an alternative embodiment of the 
invention in which a field plate is used for improved isolation. In FIG. 
13A, the same gate stack has been deposited and patterned for apertures 
150 as in FIG. 1. Sidewalls 65 have been deposited on the walls of 
aperture 150 as in FIG. 4. An oxide 202 has been either deposited or grown 
within apertures 150 after which poly field plate 210 has been deposited 
and oxide 213 has been deposited or grown over field plate 210. Field 
plate 210 will be connected to ground as is conventional. FIG. 13C shows 
the results of additional steps in which source and drain apertures have 
been formed and sidewalls 65' have been formed on the edge of the gate 
stack, together with the usual implantation of source and drain. The 
apertures have then been filled with poly contacts 115' that have been 
polished using oxide 213 and nitride 120 as a polish stop. This embodiment 
combines the lack of intrusion into the substrate characteristic of the 
previous embodiments with the advantages of a field plate. 
Those skilled in the art will readily appreciate that the invention may be 
practiced in a variety of embodiments. For example, the illustrations have 
shown N-channel MOS field effect transistors (FETs), but the invention may 
be practiced with P-channel FETs or with bipolar or biCMOS technology as 
well. Similarly, a number of methods of transistor formation have been 
illustrated and those skilled in the art will readily be able to apply the 
invention to many other methods of transistor construction. The invention 
is not meant to be limited to the embodiments shown here, but only by the 
scope of the claims.