Semiconductor integrated circuit device

A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.

This application claims priority to prior application JP 2003-428888, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuit (IC) device. In particular, the present invention relates to a semiconductor IC device including a stacked dynamic random access memory (stacked DRAM) or a chip on chip DRAM (COC DRAM).

2. Description of the Related Art

FIG. 1shows an example of a memory system which is presently studied by Joint Electron Device Engineering Council (JEDEC).

The memory system shown inFIG. 1includes a chip set4mounted on a motherboard (not shown) and a plurality of (two of them are shown here) dual inline memory modules (DIMMs)1aand1bfor transmitting/receiving signals to/from the chip set4. A buffer2aor2band a plurality of (8 in this case) DRAM chips3aor3bare mounted on each of the DIMMs1aand1b.

The chip set4is connected to the buffer2aof the DIMM1aand the buffers2aand2bof the adjoining DIMMs1aand1bare connected to each other so that signals are transmitted/received therebetween by point-to-point. The data rate of the signals is estimated to be about 6.4 to 9.6 Gbps. The signals transmitted/received between the chip set4and each of the DIMMs1aand1binclude a DQ (data) signal and a CA (command address) signal. These signals are transmitted as differential transmission signals. About 150 to 200 signal lines are required for transmitting these signals.

On each of the DIMMs1aand1b, the buffer2and each DRAM chip3are connected by using different methods depending on the types of signals. Specifically, point-to-point connection is used for DQ signals (DQ signal and DQS (strobe) signal). The data rate thereof is estimated to be about 1.6 Gbps. On the other hand, fly-by connection is used for a CA signal and a CLK (clock) signal. In the fly-by connection, a DRAM is placed on a main bus disposed in a module substrate such that the DRAM is connected to the main bus. The number of signal lines led from the buffer2is about 200 to 250, including those for differential transmission signals and single-end transmission signals.

The size of the package of the buffer2is set to about 21 mm×21 mm to 25 mm×25 mm by considering space for signal balls, VDD balls, GND balls, and no connection, if a ball pitch is 0.8 mm.

Although not shown inFIG. 1, a terminating resistor is provided in a receiving side in point-to-point connection. In fly-by connection, a terminating resistor is provided at a farthest end.

On the other hand, techniques of stacking a plurality of IC chips or large-scale integration (LSI) chips for a purpose of high integration of an IC have been suggested (for example, see Japanese Laid-Open Patent Publication No. 6-291250 (Document 1); U.S. Pat. No. 6,133,640 (Document 2); PCT Japanese Laid-Open Patent Publication No. 9-504654 (Document 3); and the Research Achievement of 2002 by Association of Super-Advanced Electronics Technologies (ASET) (Document 4)).

Document 1 describes a technique of connecting pads for signals of same attribute, such as address signals, by through electrodes. Document 2 describes a technique of stacking a memory-array circuit and a controller circuit. Document 3 describes a technique of stacking a memory chip and an interface LSI. Further, Document 4 describes a technique of forming a transmission line by using a Si interposer.

In the known memory system shown inFIG. 1, the distance between each of the DRAM chips and the buffer2in each DIMM is different one from another. Therefore, in this memory system, the buffer must operate according to the farthest DRAM chip, so that it is difficult to increase the operation speed. This problem can be solved to some extent by allowing the buffer to perform synchronizing processing or the like. In that case, however, another problem will arise, that is, the performance of the entire system is degraded and the cost increases.

Also, in the known memory system, the topology of a CLK signal or the like is different from the topology of DQ signals in each DIMM, and thus the difference in arrival time (propagation time) between a CLK signal and a DQS signal is caused in each DRAM chip. The difference must not exceed 15% of one clock cycle in view of the system design, and this cannot be realized if a clock frequency increases.

Further, in the known memory system, a terminating resistor must be provided in every transmission line, so that a large amount of electric power is consumed by the terminating resistors disadvantageously.

Still further, in the known memory system, a single-chip DRAM or a stacked (2-chip) DRAM is used as each DRAM. With this configuration, the occupied area increases as the memory capacity increases.

The above-mentioned Documents 1 to 4 do not at all disclose the entire configuration of the memory system, in particular, the configuration of the interposer, a method for placing through electrodes in a stacked DRAM, or a method for providing a terminating resistor.

Further, in the technique described in Document 4, the thickness of the insulating layer is no less than 10 μm (10 times thicker than an insulating layer which is usually used in LSI). Such a thick insulating layer is difficult to fabricate in an ordinary LSI manufacturing process. In addition, DC resistance Rdc of a transmission line shown in Document 4, having a width of 12.5 μm, a thickness of 1 μm, and a length of 10 mm, is Rdc=(1/58e6)×(10e−3)/((1e−6)×(12.5e−6))=14 Ω). This value is a little too large for a transmission line using a terminating resistor of about 50 Ω.

SUMMARY OF THE INVENTION

The present invention has been made in view of the problems of the above-described known art, and an object of the present invention is to provide a semiconductor integrated circuit device which enables a higher-speed operation, lower power consumption, and larger capacity.

In order to achieve the object, the present invention adopts a stacked DRAM structure (chip on chip (COC) DRAM structure). In this structure, a mismatch of characteristic impedance and an increase in DC resistance which occur in a signal transmission line of point-to-point connection between a chip set and an interface LSI (I/F LSI) are improved by using an interposer including a silicon (Si) unit and a printed circuit board (PCB).

When the I/F LSI is disposed face up, about 400 through electrodes must be provided in the I/F LSI. Since the area for providing these through electrodes is limited, the pitch of the through electrodes is about 40 μm at some parts. Therefore, it is difficult to directly connect the I/F LSI and the PCB, which has a via pitch of about 0.8 mm, and thus silicon, which is the material of the I/F LSI, is needed as an interposer. That is, a Si interposer is required for pitch conversion of signals (electrodes or connection terminals).

Further, electrode terminals on the lower surface of the Si interposer are connected to the PCB by means of flip-chip connection, which has almost the same size as the Si interposer. Also, solder balls are provided on the lower surface of the PCB, and the PCB is connected to a motherboard. With this configuration, the reliability of the system is increased. Further, a group of the COC DRAM, I/F LSI, Si interposer, and PCB can be regarded as one unit, which can be easily handled. Still further, by providing a reference plane for signal wiring in the Si interposer in the PCB, the characteristic impedance and the DC resistance of the wiring provided in the Si interposer can be set to appropriate values. That is, the PCB is essential in terms of electrical characteristic, reliability, and easy handling. A combination of the Si interposer and the PCB can be regarded as a two-layered interposer.

Also, in order to achieve the above-described object, in the present invention, the wiring topology of each signal (e.g., DQS signal and CLK signal) between the I/F LSI and the stacked DRAM is set to the same so as to eliminate difference of signal delay. Further, a terminating resistor for each signal is removed.

Further, in order to reduce the area occupied by DRAM chips, a COC DRAM structure is adopted. In this structure, a plurality of DRAM chips, each having a thickness of about 50 μm, are stacked, and the DRAM chips are connected by through electrodes.

Specifically, according to an aspect of the present invention, a semiconductor integrated circuit device includes a motherboard on which a chip set is mounted; and a memory unit which is mounted on the motherboard and which is connected to the chip set. A stacked DRAM including a plurality of stacked DRAM chips is used as the memory unit, and an interposer is used for mounting the stacked DRAM on the motherboard.

Preferably, the interposer includes a silicon unit including wiring for electrically connecting the stacked DRAM and the chip set. A reference plane, which gives a potential reference to the wiring, is disposed nearer the motherboard in relation to the silicon unit.

The semiconductor integrated circuit device may further include an interface LSI for mediating signal transmission/reception between the stacked DRAM and the chip set, the interface LSI being disposed between the stacked DRAM and the interposer. The interface LSI and the chip set are connected by point-to-point connection via the interposer and the motherboard.

Further, the interposer includes a printed circuit board which is disposed under the silicon unit and which has substantially the same size as that of the silicon unit, and the reference plane is disposed in the printed circuit board.

The semiconductor integrated circuit device includes a plurality of groups, each group including the stacked DRAM and the interposer. The plurality of groups are connected to the chip set by point-to-point connection or by common connection.

The semiconductor integrated circuit device includes a plurality of groups, each group including the stacked DRAM and the interposer. Main buses for a command-address signal and main buses for a data signal are disposed in the motherboard such that the main buses for the command-address signal are orthogonal to those for the data signal immediately under each group so that the plurality of groups are connected to the chip set by fly-by connection. A stub length from each of the main buses for the command-address signal and the data signal to the stacked DRAM of each group is 2 mm or less.

Alternatively, the interposer may be a Si interposer-interface LSI for mediating transmission/reception of signals between the stacked DRAM and the chip set.

The semiconductor integrated circuit device includes a plurality of groups, each group including the stacked DRAM and the Si interposer-interface LSI. The plurality of groups are arranged in a matrix pattern, and main buses for a command-address signal and main buses for a data signal are arranged in a grid pattern in the motherboard such that the main buses for the command-address signal are orthogonal to those for the data signal in an area provided with each group so that the plurality of groups are connected to the chip set by fly-by connection.

The semiconductor integrated circuit device includes a plurality of groups, each group including the stacked DRAM and the Si interposer-interface LSI. The plurality of groups are arranged in a matrix pattern, and main buses for a command-address signal and main buses for a data signal are arranged in parallel in the motherboard such that the main buses are parallel to each other immediately under each group so that the plurality of groups are connected to the chip set by fly-by connection.

The semiconductor integrated circuit device includes a plurality of groups, each group including the stacked DRAM and the Si interposer-interface LSI. The plurality of groups are arranged in a matrix pattern. The groups in the nearest row to the chip set are connected to the chip set by point-to-point connection. Whereas, in the groups belonging to the other rows, adjoining groups in each line are connected to each other by point-to-point connection.

According to the present invention, the skew of each signal can be reduced because stacked DRAMs are used. Also, impedance matching of each signal line can be easily realized because an interposer is disposed between the stacked DRAM and a motherboard. Accordingly, the present invention can provide a semiconductor integrated circuit device (memory system) capable of performing a high-speed operation.

Also, according to the present invention, since the stacked DRAM can be regarded as lumped constant, a terminating resistor need not be provided in each DRAM chip. With this configuration, the number of terminating resistors can be reduced compared to the known art and thus power consumption by the terminating resistors can be reduced. Accordingly, the present invention can provide a semiconductor integrated circuit device (memory system) of low power consumption.

Further, according to the present invention, since the stacked DRAMs are used, the capacity of memory can be increased by increasing the number of stacked DRAM chips. Accordingly, the present invention can provide a semiconductor integrated circuit device (memory system) of large capacity for its occupied area.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 2A and 2Bschematically show the configuration of a memory system (semiconductor integrated circuit (IC) device) according to a first embodiment of the present invention, in whichFIG. 2Ais a longitudinal cross-sectional view andFIG. 2Bis a plan view.

The memory system shown inFIGS. 2A and 2Bincludes a chip set4mounted on a motherboard5and a plurality of (two of them are shown here) stacked DRAMs14aand14b. Each of the stacked DRAMs14aand14bincludes a chip on chip DRAM (COC DRAM)6a(6b) including 8 to 16 stacked DRAM chips, an interface LSI (I/F LSI)12a(12b) on which the COC DRAM6a(6b) is stacked, and an interposer7a(7b) which is disposed under the I/F LSI12a(12b) and which includes a silicon (Si) unit10a(10b) and a printed circuit board (PCB)11a(11b).

The Si unit10a(10b) of the interposer7a(7b) includes a Si substrate8a(8b) and an insulating-layer unit9a(9b). The Si unit10a(10b) and the PCB11a(11b) of the interposer7a(7b) are connected to each other by means of flip-chip connection. The PCB11a(11b) of the interposer7a(7b) is connected to the motherboard5by using solder balls.

Signal transmission between the chip set4and the I/F LSI12ais performed by point-to-point connection. In the motherboard5, the chip set4and the I/F LSI12aare wired so as to have characteristic impedance Z0. In the interposer7a, this wiring is realized as a wiring line15arunning in the horizontal direction in the insulating-layer unit9a.

Likewise, signal transmission between the I/F LSis12aand12bis performed by point-to-point connection. In the motherboard5, a signal line between the I/F LSis12aand12bis provided so that the characteristic impedance is Z0. In the interposer7b, the wiring is realized as a wiring line15brunning in the horizontal direction in the insulating-layer unit9b.

GND reference planes16aand16b, which provide a potential reference to the wiring lines15aand15bin the interposers7aand7b, are disposed in the PCBs11aand11b, respectively. By using the function of the GND reference planes16aand16b, the characteristic impedance of each of the wiring lines15aand15bis set to Z0and the DC resistance thereof is set to about 3Ω or less. The wiring line15and the GND reference plane16in the interposer7will be described in detail later.

In the above-described manner, the characteristic impedance at the point-to-point connection is set to Z0throughout the wiring in the memory system shown inFIGS. 2A and 2B. Further, the receiving side of the point-to-point connection is terminated by terminating resistance Z0, and the driver side is impedance-matched by source resistance Z0. As a result, in signal transmission at the point-to-point connection, reflections can be suppressed and favorable signal integrity can be obtained.

Signals at the point-to-point connection are so-called protocol signals, including information such as a DQ signal and a CA signal, and the number of signal lines is 150 to 200. The signals at the point-to-point connection are transmitted at a data rate 4 to 6 times faster than that of DRAM. For example, when the data rate of the DRAM is 1.6 Gbps, the data rate at the point-to-point connection is 6.4 to 9.6 Gbps. Incidentally, the stacked DRAM should preferably have a ×64 bits structure when 1 channel is 8 bytes.

In each of the stacked DRAMs14aand14b, signal transmission between the I/F LSI12and the COC DRAM6is performed via a through electrode17which is disposed through the COC DRAM6in the stacking direction (vertical direction). Although only one through electrode17is shown inFIGS. 2A and 2B, a required number of through electrodes are actually provided for DQ, CA, and power-supply signals. The signals include a DQ signal, a DQS signal, a CA signal, a CLK signal, etc., which are transmitted/received by being distinguished from each other. However, all wiring lines including the through electrode17have the same topology, and thus a skew of each signal is hardly generated. Further, the length of the through electrode17is short, about 0.4 mm in 8-chip stack, and this portion can be regarded as a lumped-constant circuit. Therefore, no terminating resistor is required. With this configuration, power consumption by a terminating resistor does not occur when a signal is transmitted between the I/F LSI12and the COC DRAM6, so that an operation at low power consumption can be realized.

As described above, signals are transmitted/received by point-to-point connection between the chip set4and the I/F LSI12aand between the adjoining I/F LSIs12aand12b. The data rate is about 6.4 to 9.6 Gbps. The signals include differential transmission protocol signals, including information such as a DQ (data) signal and a CA (command address) signal required for a memory, and the number of signal lines is about 150 to 200. On the other hand, the number of balls at the PCB11is about 300 to 400, including those for the power supply and the ground (GND). The total number of balls is 500 to 600, including a window and no connection. Herein, when the ball pitch is 0.8 mm, the size of the PCB11is about 20 mm×20 mm.

On the other hand, signals transmitted/received between the I/F LSI12and the COC DRAM6include DQ, CA, and CLK (clock) signals, which are transmitted/received by type of signals. The data rate of DQ signals is about 1.6 Gbps. The number of signal lines used herein is about 200 to 250, including those for differential transmission signals and single-ended transmission signals.

The size of the COC DRAM6is about 10 mm×10 mm, and the size of the I/F LSI12is set correspondingly. When the I/F LSI12is disposed face up, approximately 400 through electrodes must be provided in the I/F LSI12, including those for the power supply and the GND.

In the I/F LSI12, the place for providing the through electrodes is limited, and thus the pitch of the through electrodes must be set to about 40 μm in some cases. Therefore, it is difficult to directly connect the I/F LSI12and the PCB11, which has a via pitch of about 0.8 mm. For this reason, the Si unit10, which serves as an interposer for converting the pitch of signal lines (wiring lines) and which comprises the same material as that of the I/F LSI12, is disposed between the I/F LSI12and the PCB11.

The PCB11, which has almost the same size as that of the Si unit10, is connected to electrode terminals on the lower surface of the Si unit10by flip chip connection. The PCB11is connected to the motherboard5by using solder balls formed on a lower surface thereof. With this configuration, the reliability of the memory system is enhanced. Further, the stacked DRAM14including the COC DRAM6, the I/F LSI12, the Si unit10, and the PCB11can be regarded as a single package, which can be easily handled. Furthermore, since the GND reference plane16for providing a potential reference to signal lines is disposed in the PCB11, the characteristic impedance and DC resistance of the wiring line15provided in the Si unit10can be set to appropriate values. In this way, the PCB11enables improved electrical characteristic, reliability, and easy handling.

The length of the wiring line15in the interposer7may be about 10 to 15 mm, so it is important to allow the wiring in the interposer7to have a favorable transmission characteristic in the above-describe manner.

Next, the operation of the memory system shown inFIGS. 2A and 2Bwill be described.

First, a case where data in the chip set4is written into the COC DRAM6awill be described. The chip set4outputs a protocol signal, including information such as a DQ signal and a CA signal, to the I/F LSI12a. The I/F LSI12adecodes the signal from the chip set4according to the protocol, and outputs a CA signal, a DQ signal, a CLK signal, and so on to the COC DRAM6a. Then, the COC DRAM6awrites the data in a predetermined address according to the signals output from the I/F LSI12a.

When the data is to be written in the COC DRAM6b, the I/F LSI12atransmits a protocol signal to the I/F LSI12b, and the I/F LSI12bdecodes the signal according to the protocol and outputs a CA signal, a DQ signal, a CLK signal, and so on to the COC DRAM6b. As a result, as the COC DRAM6a, the COC DRAM6bwrites the data in a predetermined address according to the signals output from the I/F LSI12b.

Next, a case where data is read from the COC DRAM6awill be described.

The chip set4supplies a protocol signal, including information such as a CA signal, to the I/F LSI12a. The I/F LSI12adecodes the signal from the chip set4according to the protocol and outputs a CA signal, a CLK signal, and so on to the COC DRAM6a. The COC DRAM6aresponds to the CA signal and so on from the I/F LSI12aand reads the data from a predetermined address. The I/F LSI12acaptures the read data and outputs the data as a protocol signal to the chip set4.

When the data is to be read from the COC DRAM6b, the chip set4supplies a protocol signal, including information such as a CA signal, to the I/F LSI12bvia the I/F LSI12a. The I/F LSI12bdecodes the signal from the chip set4according to the protocol and outputs a CA signal, a CLK signal, and so on to the COC DRAM6b. The COC DRAM6bresponds to the CA signal and so on from the I/F LSI12band reads the data from a predetermined address. The I/F LSI12bcaptures the read data and outputs the data as a protocol signal to the chip set4via the I/F LSI12a.

Next, the principle of the interposer7used in the system memory shown inFIGS. 2A and 2Bwill be described with reference toFIG. 3.

FIG. 3is a cross-sectional view of the left half of the stacked DRAM14shown inFIGS. 2A and 2B.

As described above, the Si unit10of the interposer7includes the Si substrate8and the insulating-layer unit9. The insulating-layer unit9includes a plurality of insulating layers each having a thickness of about 1 μm and wiring layers between the insulating layers. The wiring line15is formed by patterning the wiring layers in the insulating-layer unit9. Also, the wiring line15is electrically connected to a connecting terminal disposed on the lower surface of the Si unit10via a blind via. The wiring line15has a width of 100 μm and a thickness of 0.5 μm, for example. Further, the Si unit10includes a through electrode22which is disposed through the Si substrate8and the insulating-layer unit9and which is connected to the wiring line15. The insulating-layer unit9and the wiring line15of the Si unit10have a size which can be realized by an ordinary LSI manufacturing process, and thus are suitable for industrial production.

The reference plane16(GND layer plane) in the PCB11is disposed at a distance of about 100 μm from the upper surface of the PCB11. The GND reference plane16forms a transmission-line structure together with the wiring line15of the Si unit10. Because the distance between the GND reference plane16and the wiring line15is more than 100 μm, the characteristic impedance of this transmission-line structure is about 50 Ω. The DC resistance Rdc of the wiring line15is, assuming that the length thereof is 10 mm, Rdc=(1/58e6)×(10E−3)/((0.5e−6)×(100e−6))=3.4 Ω. The resistance Rdc can be lowered by adjusting the thickness and width of the wiring line15.

A plurality of solder balls are disposed on the lower surface of the PCB11, at a pitch of about 800 μm. The solder balls are connected to and fixed to the motherboard5, as described above.

A signal which has entered a solder ball20for a signal passes through a via21in the PCB11and enters the Si unit10. Then, the signal is transmitted to a predetermined position under the I/F LSI12via the wiring line15running in the insulating-layer unit9, and is then input to the I/F LSI12via the through electrode22which is disposed through the Si unit10and the I/F LSI12. The signal which has entered the I/F LSI12passes a logic circuit23in the I/F LSI12, and then reaches each DRAM chip via the through electrode17of the COC DRAM6. A signal from each DRAM chip traces the opposite route and reaches the motherboard5via the solder ball20.

A GND potential is supplied to a solder ball24, enters the Si unit10via a via25in the PCB11, and is supplied to each DRAM chip via a through electrode26, which is disposed through the Si unit10, the I/F LSI12, and the COC DRAM6. The GND potential is also supplied to the reference plane (GND layer plane)16in the PCB11.

Next, the necessity of providing the PCB11in the interposer7will be described with reference toFIG. 4.

FIG. 4is a cross-sectional view of the left half of a stacked DRAM including an interposer which has only a Si unit30.

The Si unit30includes the Si substrate8and an insulating-layer unit31. The insulating-layer unit31includes a plurality of insulating layers each having a thickness of 1 μm, and a wiring line34and a GND layer plane38are disposed between the insulating layers. Each of the wiring line34and the GND reference plane38is disposed between different insulating layers.

Further, the Si unit30includes a through electrode33which is disposed through the Si substrate8and the insulating-layer unit31and which is connected to the wiring line34, a through electrode37which is disposed through the Si substrate8, the insulating-layer unit31, and the COC DRAM6and which is connected to the GND reference plane38, and a plurality of flip-chip electrodes on the lower surface of the Si unit30.

A signal which has entered the Si unit30via a flip-chip electrode32for a signal passes the through electrode33in the Si unit30and the wiring line34running in the insulating-layer unit31and is input to a through electrode35in the I/F LSI12. The signal entered the I/F LSI12passes a logic circuit23in the I/F LSI12and reaches the through electrode17of the COC DRAM6, and is input to each DRAM chip. A signal from each DRAM chip toward the chipset4traces the opposite route and reaches the flip-chip electrode32.

A GND potential is supplied to a flip-chip electrode36, enters the Si unit30, is supplied to the through electrode37which is disposed through the Si unit30, the I/F LSI12, and the COC DRAM6, and is then supplied to each DRAM chip and the GND reference plane38.

In the interposer shown inFIG. 4, the wiring line34forms a transmission-line structure in conjunction with the GND reference plane38. In order to obtain a characteristic impedance of about 50 μl in this structure, the size of the wiring line34must be about 1 μm wide and 0.5 μm thick. In this case, however, the DC resistance Rdc of the wiring line34is, assuming that the length thereof is 10 mm, Rdc=(1/58e6)×(10e−3)/((0.5e−6)×(1e−6))=340 Ω. This resistance is too large for a transmission line. That is, it is difficult to fabricate an interposer having a transmission-line structure which satisfies both of preferable DC resistance and characteristic impedance in a suitable size for industrial production by using only the Si unit.

When the insulating-layer unit is placed in the COC DRAM side and when the Si substrate is placed in the motherboard side as in the Si unit30shown inFIG. 4, by providing a PCB including a reference plate under the Si unit30, a transmission-line structure having a favorable characteristic can be formed as in the interposer7shown inFIG. 3. In that case, however, since the Si substrate8which has a large relative permittivity εr (=12) is placed between the wiring line and the reference plane, the characteristic impedance is small if the size is the same as inFIG. 3.

Next, the interposer7will be described more specifically with reference toFIG. 5.

FIG. 5shows a specific configuration of the interposer7, and shows the cross-section of the left half of the stacked DRAM14as inFIG. 3. The points different fromFIG. 3are that the insulating-layer unit9of the Si unit10includes five insulating layers, that a VDD line, a GND line, and first and second signal lines are disposed between the insulating layers, and that through electrodes or vias connected thereto are provided.

In the interposer7shown inFIG. 5, a signal which has entered a solder ball40passes a via41in the PCB11and enters the Si unit10. The signal entered the Si unit10is transmitted to a predetermined position under the I/F LSI12through a wiring line42running in the insulating-layer unit9and then reaches a through electrode43which is disposed through the Si unit10and the I/F LSI12. Then, the signal enters the I/F LSI12via the through electrode43, passes the logic circuit23in the I/F LSI12, and then reaches each DRAM chip via the through electrode17in the COC DRAM6. A signal from each DRAM chip traces the opposite route and reaches the solder ball40.

Likewise, a signal which has entered a solder ball44reaches the COC DRAM6in the same way. However, this signal passes through a wiring line45, which is disposed in a different wiring layer from that of the wiring line42, which is used for transmitting the signal entered the solder ball40. By providing the wiring lines42and45in different wiring layers, the number of wiring lines in each wiring layer can be reduced and the layout can be simplified.

Although not shown, a signal entered a solder ball under the I/F LSI12traces the same route. However, wiring provided in the insulating-layer unit9may be unnecessary depending on the position of the through electrode which is disposed through the Si unit10and the I/F LSI12.

A GND potential supplied to a solder ball46enters the Si unit10via a via47in the PCB11and is supplied to each DRAM chip via a through electrode48which is disposed through the Si unit10, the I/F LSI12, and the COC DRAM6. Also, the GND potential is supplied to the GND reference plane16in the PCB11and a GND reference line49in the Si unit10.

A GND potential supplied to a solder ball50, which is disposed under an area outside the I/F LSI12area, is supplied to the GND reference plane16via a via51in the PCB11and is also supplied to the GND reference line49via a through electrode52in the Si unit10. Herein; a blind via may be used instead of the through electrode52. However, when the through electrode52is used, a decoupling capacitor can be connected between the through electrode52and a through electrode53, which will be described later. The decoupling capacitor can be disposed on the upper surface of the Si unit10.

A VDD potential supplied to a solder ball54enters the Si unit10via a via55in the PCB11and is supplied to each DRAM chip via a through electrode56which is disposed through the Si unit10, the I/F LSI12, and the COC DRAM6. Also, the VDD potential is supplied to a VDD plane57in the PCB11and to a VDD line58in the Si unit10.

A VDD potential supplied to a solder ball59, which is disposed under an area outside the I/F LSI12area, is supplied to the VDD plane57via a via60in the PCB11and is also supplied to the VDD line58via the through electrode53in the Si unit10. Herein, a blind via may be used instead of the through electrode53. However, by using the through electrode53, a decoupling capacitor can be connected between the through electrode53and the through electrode52for GND potential, as described above.

The GND reference plane16in the PCB11is disposed at a distance of about 100 μm from the upper surface of the PCB11. Each of the wiring lines42and45running in the insulating-layer unit9has a width of about 100 μm and a thickness of about 0.5 μm. Each insulating layer in the insulting-layer unit9has a thickness of about 1 μm. These wiring lines and insulating layers have size which can be realized in an ordinary LSI manufacturing process, and are thus suitable for industrial production.

The wiring lines42and45and the GND reference plane16form a transmission-line structure. The characteristic impedance of this structure is about 50Ω. On the other hand, the DC resistance Rdc of each of the wiring lines42and45is, assuming that the length thereof is 10 mm, Rdc=(1/58e6)×(10e−3)/((0.5e−6)×(100e−6))=3.4Ω. The DC resistance Rdc can be set at a smaller value by adjusting the thickness and width of each wiring line.

InFIG. 5, the GND reference plane16in the PCB11is positioned in the Si unit10side in relation to the VDD plane57. Alternatively, the VDD plane57may be positioned in the Si unit10side, that is, above the GND plane16. In that case, the VDD plane57serves as a reference plane for giving a potential reference to the wiring lines42and45. That is, the wiring lines42and45forms a transmission-line structure in conjunction with the VDD reference plane57.

Also, in the example shown inFIG. 5, the VDD line58and the GND line49are provided in the Si unit10. These lines are provided for reinforcing power supply, and are not always necessary. Further, the VDD line58and the GND line49must be arranged so that they do not serve as the reference of the wiring lines42and45running in the insulating-layer unit9. In other words, the VDD line58and the GND line49must not overlap the wiring lines42and45viewed from the above.

According to this embodiment, the entire part between the chip set4and the I/F LSI12connected by point-to-point connection can be a transmission-line structure, as described above. With this configuration, by matching the terminating resistance and source resistance with the characteristic impedance of the transmission line, signal integrity can be enhanced and transmission speed can be increased.

Also, according to this embodiment, the I/F LSI12is connected to the COC DRAM6via a through electrode in a short distance. Specifically, when eight DRAM chips, each having a thickness of 50 μm, are stacked, the distance is 0.4 mm. With this configuration, skew of each signal hardly occurs in the COC DRAM6, so that a high-speed operation can be realized. Also, since the signal propagation time between the I/F LSI12and the COC DRAM6is shorter than rise time/fall time of a signal, the COC DRAM6can be used as a lumped-constant circuit. Therefore, a terminating resistor need not be provided in each DRAM chip of the COC DRAM6and thus power consumption by a terminating resistor does not occur, so that an operation at low power consumption can be realized.

Also, according to this embodiment, when the memory capacity of the DRAM should be increased, DRAM chips are three-dimensionally stacked instead of being aligned two-dimensionally. In this way, the memory capacity can be increased without increasing an occupied area. In this case, an increase in the height is about 50 μm per chip.

In the above-described embodiment, the reference plane is provided in the PCB11. It is also possible in principle to provide the reference plane in the motherboard. In that case, the PCB11is not necessary, so that the Si unit10is directly connected to the motherboard5by flip-chip connection.

Next, the positional relationship of through electrodes which are disposed through the Si unit10of the interposer7, the I/F LSI12, and the COC DRAM6will be described with reference toFIGS. 6 and 7.

As shown inFIG. 6, the major part of an element formation area of a DRAM chip70is occupied by memory-cell array areas71. Since many transistors are densely disposed in the memory-cell array areas71, no through electrode can be disposed in these areas. An area in which a through electrode can be provided is limited to a peripheral-circuit area72(center-line area) between the memory-cell array areas71or a chip peripheral area73around the memory-cell array areas71. Under the limitations, the through electrodes which are disposed through the Si unit10of the interposer7, the I/F LSI12, and the COC DRAM6are positioned in the manner shown inFIG. 7.

FIG. 7is a plan perspective view showing the positions of the through electrodes which are disposed through the Si unit10of the interposer7, the I/F LSI12, and the COC DRAM6. The number of through electrodes shown in this figure is smaller than that in the actual interposer7. The parts which are the same as those inFIG. 5are denoted by the same reference numerals.

InFIG. 7, the outermost large square corresponds to the interposer7(Si unit10and PCB11) and the inner small square corresponds to the COC DRAM6and the I/F LSI12.

In each of double circles arranged in a matrix pattern, the outer circle (bigger circle) represents a solder ball disposed on the lower surface of the interposer7. Among these bigger circles, a white circle represents a solder ball for a signal, a black circle represents a solder ball for GND, and a hatched circle represents a solder ball for VDD or Vref.

The inner circle of each double circle and the other single circles (small circles) represent vias disposed in the PCB11and through electrodes disposed individually or in common through the Si unit10, the I/F LSI12, and the COC DRAM6. Among the small circles, black circles represent through electrodes in the COC DRAM6. On the other hand, the inner circles of the double circles basically represent the vias in the PCB11which are disposed immediately above the balls.

As described above with reference toFIG. 6, an area for disposing through electrodes in the COC DRAM6is limited to the peripheral-circuit area and the chip peripheral area of the DRAM chip. A through electrode which is disposed through the Si unit10of the interposer7and the I/F LSI12is placed so that the through electrode can be easily connected to the through electrode in the COC DRAM6and the via in the PCB11which correspond to each other.

A via in the PCB11disposed on a solder ball for a signal, which is disposed outside the small square, is connected to a through electrode which is disposed through the Si unit10and the I/F LSI12via a wiring line running in the insulating-layer unit9of the Si unit10of the interposer7. A through electrode which is disposed through the I/F LSI12is connected to a through electrode which is disposed through the COC DRAM6via the internal circuit23. For example, the via41in the PCB11, which is disposed on the solder ball40, is connected to the through electrode43which is disposed through the Si unit10and the I/F LSI12via the wiring line42. Further, the through electrode43is connected to the through electrode17in the COC DRAM6via the internal circuit of the I/F LSI12. In this way, by providing the through electrodes of the COC DRAM6in the peripheral-circuit area and the chip peripheral area outside the memory-cell array areas, the DRAM chips can be efficiently laid out.

If a through electrode76, which is disposed through the Si unit10and the I/F LSI12, exists immediately above a via in the PCB11disposed on a solder ball75for a signal inside the small square, the via is directly connected to the through electrode76by bypassing the wiring line running in the insulating-layer unit9. On the other hand, a via in the PCB11above which a through electrode in the Si unit10does not exist is connected to a through electrode which is disposed through the Si unit10and the I/F LSI12via the wiring line running in the insulating-layer unit9, as the via which is placed on a solder ball outside the small square.

The via47in the PCB11, which is disposed on the solder ball46for a GND potential positioned inside the small square, is connected to the immediately above through electrode48which is disposed through the Si unit10, the I/F LSI12, and the COC DRAM6by bypassing the wiring line in the insulating-layer unit9.

Likewise, the via55in the PCB11, which is disposed on the solder ball54for a VDD potential, is connected to the immediately above through electrode56which is disposed through the Si unit10, the IF/LSI12, and the COC DRAM6, by bypassing the wiring line in the insulating-layer unit9. This is the same for the via disposed on a solder ball77for a Vref potential.

The via51in the PCB11, which is disposed on the solder ball50for a GND potential outside the small square, is directly connected to the through electrode52which is disposed immediately above the via51through the Si unit10.

Likewise, the via60in the PCB11, which is disposed on the solder ball59for a VDD potential, is directly connected to the through electrode53which is disposed immediately above the via60through the Si unit10.

As described above, by placing the vias in the PCB11and the through electrodes which are disposed through the Si unit10, the I/F LSI12, and the COC DRAM6immediately above the solder balls for GND and VDD in the area under the I/F LSI12(inside the small square), GND and VDD potentials can be supplied to each DRAM chip in the shortest distance. Further, the vias in the PCB11and the through electrodes which are disposed through the Si unit10are placed immediately above the solder balls for GND and VDD outside the area under the I/F LSI12(outside of the small square), so that GND and VDD potentials are supplied to the COC DRAM6via the GND plane and the VDD plane in the PCB11and the GND line and the VDD line in the Si unit10. Accordingly, electric power can be stably supplied to each DRAM chip.

Further, by providing the VDD-potential through electrode53and the GND-potential through electrode52, which are disposed through the Si unit10, in the outside of the area under the I/F LSI12, a decoupling capacitor78can be connected therebetween. By using the decoupling capacitor, electric power can be supplied to the COC DRAM6more stably. The decoupling capacitor can be provided in another position.

FIG. 8is a schematic view showing the configuration of a memory system according to a second embodiment of the present invention. InFIG. 8, parts which are the same as those inFIGS. 2A and 2Bare denoted by the same reference numerals.

The basic configuration of the memory system according to the second embodiment is the same as that in the first embodiment. The difference between these embodiments is that coaxial compact high-frequency connectors80are used instead of solder balls for connecting the PCB11and the motherboard5. By using the connectors, the high-speed performance can be further enhanced.

Next, a method for placing the I/F LSI12, which is common to the memory systems according to the first and second embodiments, will be explained with reference toFIGS. 9A and 9B.

As will be understood fromFIGS. 9A and 9B, when the number of signals85(in this case, 1) input/output to/from the I/F LSI12through its lower surface is different from the number of signals86(in this case, 2) input/output to/from the I/F LSI12through its upper surface, the number of through electrodes which must be provided in the I/F LSI12varies depending on whether the I/F LSI12is placed face up or face down. That is, when the number of signals86input/output through the upper surface is larger than the number of signals85input/output through the lower surface, the I/F LSI12should be placed face up as shown inFIG. 9A, so as to reduce the number of through electrodes. Herein, a face-up placement means that the I/F LSI12is placed such that the transistor-formed area of the I/F LSI12is directed upward (the side of COC DRAM6).

In the memory system according to the first and second embodiments, the number of signals input/output to/from the I/F LSI12through the upper surface is larger than the number of signals input/output through the lower surface. Therefore, by placing the I/F LSI12face up, the number of through electrodes can be reduced. Accordingly, manufacture yield ratio can be improved.

FIG. 10Ashows an example of the configuration of the I/F LSI12used in the memory system according to the first and second embodiments.FIG. 10Bshows an example of the configuration of a typical (or commonly used) I/F LSI.

The typical I/F LSI90shown inFIG. 10Breceives a CLK (or clock signal), which is input from the lower side, by a buffer92, and supplies the CLK via through electrodes17-1and17-2to DRAM chips91-1and91-2.

In the DRAM chip91-1, a CLK distributing circuit93-1distributes the CLK to the chip, and a buffer94-1supplies the distributed CLK to a flip-flop group95-1. Likewise, in the DRAM chip91-2, a CLK distributing circuit93-2distributes the CLK to the chip, and a buffer94-2supplies the distributed CLK to a flip-flop group95-2.

Herein, delay time of the buffer92is ta, delay time of the CLK distributing circuit93-1is tb1, delay time of the buffer94-1is tc1, delay time of the CLK distributing circuit93-2is tb2, and delay time of the buffer94-2is tc2. Further, delay time of one chip in a through electrode is 3 ps. Under this condition, the time period required by the CLK to reach the flip-flop group95-1after entering the I/F LSI90is represented by ta+tb1+tc1+3 ps. On the other hand, the time period required by the CLK to reach the flip-flop group95-2after entering the I/F LSI90is represented by ta+tb2+tc2+6ps. The difference between these time periods is obtained by calculating (tb2−tbl)+(tc2−tcl)+3 ps. The time difference includes characteristic variation of the CLK distributing circuit93and the buffer94in the DRAM chips.

On the other hand, in the I/F LSI12shown inFIG. 10A, a buffer92areceives a CLK input from the lower side, a CLK distributing circuit93adistributes the CLK to the chip, and a buffer94aoutputs the distributed CLK to a through electrode17-1a. The through electrode17-1asupplies the CLK from the buffer94ato a DRAM chip6-1and a through electrode17-2a, and the through electrode17-2asupplies the CLK to a DRAM chip6-2. The CLK supplied to the DRAM chips6-1and6-2is supplied to flip-flop groups95-1and95-2.

As described above, the I/F LSI12shown inFIG. 10Aincludes the CLK distributing circuit93aand the buffer94arequired for each DRAM chip in common, so that the structure of each DRAM chip can be simplified.

Herein, delay time of the buffer92ais ta′, delay time of the CLK distributing circuit93ais tb′, delay time of the buffer94ais tc′, and delay time of one chip in a through electrode is 3 ps. Under this condition, the time period required by the CLK to reach the flip-flop group95-1after entering the I/F LSI12is represented by ta′+tb′+tc′+3 ps, and the time period required by the CLK to reach the flip-flop group95-2is represented by ta′+tb′+tc′+6 ps. The difference therebetween is constant at 3 ps.

In this way, by using the I/F LSI12shown inFIG. 10A, the time difference of CLK input to the flip-flop groups95-1and95-2in each DRAM chip can be constant. That is, in the I/F LSI12shown inFIG. 10A, CLK can be distributed without being affected by the characteristic variations of the COC DRAM6. Therefore, such I/F LSI can be effectively used for transmitting a CLK signal, in which occurrence of variation is not desirable.

Next, a memory system according to a third embodiment of the present invention will be described with reference toFIGS. 11A and 11B. InFIGS. 11Aand11B, parts which are the same as those inFIGS. 2A and 2Bare denoted by the same reference numerals.

The difference between the memory system shown inFIGS. 11A and 11Band that inFIGS. 2A and 2Bis that each of stacked DRAMs100does not include the I/F LSI12and that a chip set102and the stacked DRAMs100are connected by a kind of point-to-point connection (one to plurality connection). That is, in the memory system according to the third embodiment, each of the stacked DRAMs100includes the COC DRAM6and the interposer7, and a corresponding ball of all the stacked DRAM100is connected to each ball under the chip set102. The chip set102and the COC DRAM6directly transmit/receive signals without using the I/F LSI12.

The characteristic impedance of each signal line for connecting the chip set102and the stacked DRAM100is set at Z0. Further, a terminating resistor is connected to each signal line. The terminating resistor will be described later together with the operation of this memory system.

Signals transmitted/received between the chip set102and the stacked DRAM100include DQ and DQS signals, which are bidirectional signals, and CA and CLK signals, which are unidirectional signals. These signals are directly transmitted/received between the chip set102and the DRAM100and are not so-called protocol signals. The data rate of the signals is 1.6 Gbps when the data rate of the DRAM is 1.6 Gbps. The stacked DRAM should preferably have a x64 bits structure when 1 channel is 8 bytes.FIGS. 11A and 11Bshow a case of one-channel structure.

Next, the operation of the memory system of this embodiment and a method for providing a terminating resistor (method of termination) will be described.

First, a case where data in the chip set102is written into the COC DRAM6awill be described.

Assume that a DQ signal of 64 bits and a CA signal of about 25 bits are output from the chip set102. At this time, since one of the balls of the chip set102is connected to the two COC DRAMs6aand6b, the same signal is input to the COC DRAMs6aand6b. Then, the chip set102outputs a control signal to the COC DRAM6aand6bfrom other independent balls. As a result, the COC DRAM6acaptures the DQ signal and so on from the chip set102, but the COC DRAM6bdoes not capture the signals.

Each signal line is terminated by providing far-end terminators to both stacked DRAMs100aand100b. The far-end terminator is provided in the COC DRAM6. The far-end terminator may be provided in each DRAM chip or in the top DRAM chip. By providing the terminator in the stacked DRAM, ON/OFF operation of a terminating resistor can be easily controlled.

Alternatively, the far-end terminator may be provided in the Si unit10of the interposer7. In that case, several MOS transistors must be provided in the Si unit10. Only the COC DRAM6is connected from the far-end terminator onward in the signal line, and the length of the wiring is about 0.4 mm. Therefore, the signal integrity is not substantially degraded. Also, a terminating resistor need not be provided in the DRAM, so that the load for the DRAM is small and heat can be easily emitted.

Alternatively, the far-end terminator may be provided in the PCB11of the interposer7. In that case, only the Si unit10of the interposer7and the COC DRAM6are connected from the far-end terminator onward in the signal line, and the wiring length is about 0.5 mm. Therefore, the signal integrity is not substantially degraded. Also, a terminating resistor need not be provided in the DRAM, so that the load for the DRAM is small and heat can be easily emitted. In this case, it is difficult to allow a terminating resistor to be turned OFF. However, problems do not arise if an open-drain driver is used as an output driver of the COC DRAM6at a reading operation.

Likewise, the data in the chip set102may be written into the COC DRAM6bin the same manner as described above.

Next, a case where data is read from the COC DRAM6awill be described.

First, a CA signal and so on are supplied from the chip set102to the COC DRAM6a. The CA signal and so on are also supplied to the COC DRAM6bas in the writing operation, but a control signal prevents the COC DRAM6bfrom capturing the signals. The COC DRAM6adecodes the signals supplied from the chip set102and reads data from a corresponding address. The data read from the COC DRAM6ais transmitted to the chip set102and is captured therein. Also, the data transmitted to the chip set102is transmitted to the side of the COC DRAM6bvia a ball of the chip set102. Therefore, a terminator must be provided in the COC DRAM6bside. Desirably, the ON resistance of the driver of the COC DRAM6ais set to Z0. When the driver of the COC DRAM6ais push-pull type, terminator on the COC DRAM6aside shown inFIGS. 11A and 11Bis not necessary.

Likewise, the data can be read from the COC DRAM6bin the same manner as described above.

According to the memory system of this embodiment, the same advantages as those in the memory system shown inFIGS. 2A and 2Bcan be obtained. Further, the memory system of this embodiment does not include an I/F LSI, and thus the power consumption and cost are lower than the memory system shown inFIGS. 2A and 2B. Further, the number of balls of the chip set102can be reduced.

Next, a memory system according to a fourth embodiment of the present invention will be described with reference toFIGS. 12A and 12B.

The memory system shown inFIGS. 12A and 12Bis basically the same as the memory system shown inFIGS. 11A and 11B, but is different in that a chip set103and each COC DRAM6transmit/receive signals in a one-to-one relationship. That is, the chip set103includes a terminal for the COC DRAM6aand a terminal for the COC DRAM6b.

A signal line is connected between one of the balls of the chip set103and the stacked DRAM100aincluding the COC DRAM6aand the interposer7a, and another signal line is connected between another signal ball and the stacked DRAM100bincluding the COC DRAM6band the interposer7b. Signals transmitted therebetween include bidirectional signals such as DQ and DQS signals and unidirectional signals such as CA and CLK signals. These signals are directly transmitted/received between the chip set103and the stacked DRAM100and are not so-called protocol signals.

The chip set103and the stacked DRAMs100aand100bare connected by point-to-point connection, and the characteristic impedance of the entire lines is set to Z0. The data rate of a signal is 1.6 Gbps if the data rate of the DRAM is 1.6 Gbps. The stacked DRAM should preferably have a +64 bits structure when 1 channel is 8 bytes. The memory system shown inFIGS. 12A and 12Bis of a 2-channel structure.

Next, the operation of the memory system shown inFIGS. 12A and 12Band a method for providing a terminating resistor will be described.

First, a case where data in the chip set103is written into the COC DRAM6awill be described. A DQ signal of 64 bits and a CA signal of about 25 bits are output from the chip set103.

When the signal line should be terminated, a far-end terminator is provided in the stacked DRAM100a. As described above with reference toFIGS. 11A and 11B, three places can be considered as a place for providing the far-end terminator. Preferably, the ON resistance of the driver of the chip set103is matched with the characteristic impedance of the transmission line.

Likewise, the data in the chip set103can be written into the COC DRAM6bin the same manner as described above. In this case, the COC DRAMs6aand6bcan operate independently. That is, a 2-channel operation can be realized.

Next, a case where data is read from the COC DRAM6awill be described. A CA signal and so on are supplied from the chip set103to the COC DRAM6a. The COC DRAM6adecodes the signals and reads data from a corresponding address. The read data is transmitted to the chip set103and is captured therein. Therefore, a terminating resistor is provided in the chip set103. Preferably, the ON resistance of the driver of the COC DRAM6ais set to Z0. If the driver of the COC DRAM6ais a push-pull driver, the terminator in the COC DRAM6aside shown inFIGS. 12A and 12Bis not necessary.

Likewise, data can be read from the COC DRAM6bin the same manner as described above.

According to the memory system of this embodiment, the same advantages as those in the memory system shown inFIGS. 11A and 11Bcan be obtained. Further, since a two-channel operation can be performed, the system performance can be enhanced.

FIGS. 13A and 13Billustrate an example of assignment of signals to solder balls120of the interposer7in the memory system shown inFIGS. 11A and 11BandFIGS. 12A and 12B.FIG. 13Ais a cross-sectional view of the stacked DRAM100andFIG. 13Bis a plan perspective view. The number of wiring layers in the interposer7is determined by considering the density of wiring.

In the system structure shown inFIGS. 11A and 11BandFIGS. 12A and 12B, signals are transmitted/received between the chip set and the COC DRAM6by type of signals such as DQ and CA signals, and thus the skew of each signal should be small. Therefore, by making the time period after a signal enters the interposer7until the signal reaches the COC DRAM6constant in each type of signal, high-speed operation can be promoted. In order to achieve this, signals of the same attribute are assigned to balls on concentric circles (or the vicinity of the circles), the center of the circles being the center of the interposer7. For example, inFIG. 13B, DQ signals are assigned to the balls indicated by black circles along the largest circle, and DQS signals for capturing DQ signals are assigned to the balls indicated by white circles along the next inner circle. Also, CA signals and CLK signals for capturing CA signals are assigned to the balls indicated by black circles along the inner circle next to the circle for the DQS signals. In this way, by assigning signals to the balls of the interposer7, the delay time of signals output from the chip set102or103and input to the balls of the interposer7can be made constant in each type of signals, and thus the signals can be transmitted/received between the chip set102or103and the COC DRAM6with a small skew.

FIG. 14is an enlarged view of the upper right portion ofFIG. 13B.FIG. 14shows the assignment of balls, and an example of wiring connection between the balls for CA and CLK signals and terminals130of the through electrode17in the COC DRAM6. As can be understood fromFIG. 14, the balls for CA and CLK signals and the terminals130are connected in almost the same length. The wiring lines for other types of signals can also be set to almost the same length.

Next, a memory system according to a fifth embodiment will be described with reference toFIGS. 15A and 15B. In the memory systems according to the first to fourth embodiment, the plane size of the interposer7is larger than that of the COC DRAM6. However, in the memory system according to this embodiment, the plane size of the interposer is equivalent to that of the COC DRAM. Such configuration is suitable when the number of signals is small, for example, when the COC DRAM is of +8 bits structure.

The memory system shown inFIGS. 15A and 15Bincludes a motherboard142, a chip set143mounted on the mother board142, and a plurality of stacked DRAMs144.

Each stacked DARM144includes a COC DRAM140having four stacked DRAM chips and an interposer141.

When each COC DRAM140is of +8 bits structure and when one channel is 64 bits, eight stacked DRAMs144are used as one group.FIGS. 15A and 15Bshow an example of 2-channel structure, and 8×2 rows stacked DRAMs144are shown. The rows of stacked DRAMs are arranged in one direction from the chip set143.

A Si interposer or a PCB interposer may be used as the interposer141. When the pitch of through electrodes in the COC DRAM140is set to about 40 μm at the minimum, the Si interposer is used. In that case, the Si interposer is connected to the motherboard142by flip-chip connection or is connected to a PCB of the same size (not shown) by flip-chip connection and is connected to the motherboard142by using solder balls of the PCB. When a combination of the Si interposer and the PCB is used, the entire combination can be regarded as an interposer.

On the other hand, when the pitch of through electrodes in the COC DRAM140is about 0.8 mm, the PCB interposer may be used. In that case, the COC DRAM140and the PCB interposer141are connected by flip-chip connection and the PCB interposer141is connected to the motherboard142by using solder balls. Alternatively, the COC DRAM140may be connected to the motherboard142by flip-chip connection.

Transmission of DQ and DQS signals between the chip set143and the COC DRAM140is performed by using signal lines connected by a fly-by method, as shown in the figure. That is, among 64 bits of the DQ and DQS signals transmitted/received between the chip set143and the stacked DRAM144, the first 8 bits are transmitted/received to/from stacked DRAMs144a1and144b1, the next 8 bits are transmitted/received to/from stacked DRAMs144a2and144b2, and the last 8 bits are transmitted/received to/from stacked DRAMs144a8and144b8. When the characteristic impedance of the motherboard142is Z0, these signal lines are terminated at the far end by a terminating resistor R1which is lower than Z0. Since a load is connected to the transmission line, causing an increase in capacity, and the effective characteristic impedance decreases, the resistance of the terminating resistor R1is matched with the effective characteristic impedance.

Transmission of a CA signal between the chip set143and the COC DRAM140is performed by using signal lines which is connected by the fly-by method as shown in the figure and which is orthogonal to signal lines for DQ and DQS signals. A one copy of CA signal is transmitted/received to/from the stacked DRAMs144a1,144a2, . . . , and144a8, and another copy of CA signal is transmitted/received to/from the stacked DRAMs144b1,144b2, . . . , and144b8. Also, a CLK signal for capturing the CA signal is transmitted by similar signal lines. Each of these signal lines is terminated at the far end by a terminating resistor R2which is lower than Z0, if the characteristic impedance of the motherboard142is Z0.

Herein, each of the DQ and CA signals is branched from a main bus running in the motherboard142to the COC DRAM. If the stub length thereof is long, a large amount of reflection occurs at that point, so that signal integrity deteriorates. Therefore, the stub length of each signal line should be preferably about 2 mm or less.

Next, the operation of the memory system shown inFIGS. 15A and 15Bwill be described.

First, a case where data in the chip set143is written into the COC DRAM140awill be described.

DQ and CA signals are output from the chip set143. Preferably, the ON resistance of the driver of the chip set143should be matched with the effective characteristic impedances R1and R2of each main bus.

The COC DRAM140adecodes the command signal from the chip set143and writes the data in a corresponding address.

A process of writing data into the COC DRAM140bis performed in the same manner.

Next, a case where data is read from the COC DRAM140awill be described.

A CA signal is output from the chip set143. The COC DRAM140adecodes the command signal from the chip set143and reads data from a corresponding address. The read data is transmitted to the chip set143and is captured therein. Preferably, in the reading operation, a terminating resistor is provided in the chip set143. The resistance is R1.

A process of reading data from the COC DRAM140bis performed in the same manner.

According to the memory system of this embodiment, no I/F LSI is required and the interposer need not have a transmission-line structure. Further, the data rate of signals is the same as the DRAM speed, and xN high speed is not used. Therefore, a packaging design at low cost can be realized.

FIG. 16is a schematic diagram for examining the positioning of through electrodes in the COC DRAM140of the memory system shown inFIGS. 15A and 15B. InFIG. 16, large circles indicate the positions of balls of the interposer141and small black circles indicate the positions of through electrodes in the COC DRAM140. As described above with reference toFIG. 6, the place for providing the through electrodes of the COC DRAM140is limited, so the through electrodes are disposed in the peripheral area of the chip.

A signal which has entered from the motherboard142to a ball of the interposer141must be transmitted in the horizontal direction to the position of a through electrode in the COC DRAM140. A stub is used as the wiring for that purpose. In the example shown inFIG. 16, the length of wiring lines150and151is 3 mm or more, which is not suitable for high-speed transmission.

In order to improve this configuration, in the memory system shown inFIGS. 15A and 15B, through electrodes of the COC DRAM140are arranged in the manner shown inFIG. 17. That is, through electrodes are provided not only in the periphery of the chip but also in the peripheral-circuit area such as center lines. By arranging the through electrodes of the COC DRAM140in this manner, the distance between each through electrode and a corresponding ball of the interposer141, that is, the stub length, can be shortened. Further, the through electrodes connected to VDD and GND are provided immediately above solder balls160and161, to which VDD and GND are assigned. Alternatively, through electrodes are provided in an area nearest to solder balls162and163assigned to VDD and GND, and the through electrodes and the solder balls are connected by wide (or thick) wires. In this case, the through electrodes may be connected to each other.

In the example shown inFIG. 17, the pitch of the through electrodes is large, about 0.8 mm. Thus, a PCB can be used as the interposer141, so that the cost can be reduced.

FIG. 18shows another example of the positioning of the through electrodes of the COC DRAM140which can be applied to the memory system shown inFIGS. 15A and 15B. The difference from the example shown inFIG. 17is that the through electrodes of the COC DRAM140are provided on the center line to a possible extent. In the current DRAMs, most part of pads is often provided on the center line, and thus the layout can be effectively utilized and a designing period can be shortened. Of course, the stub length is short.

In this case, the pitch of the through electrodes is small, about 40 μm at the minimum, so that a Si interposer need be used as the interposer141.

FIG. 19is a longitudinal cross-sectional view showing the structure of the COC DRAM140having the through electrodes positioned in the manner shown inFIG. 18and the Si interposer141on which the COC DRAM140is stacked. InFIG. 19, through electrodes for power supply are disposed through the interposer141and the COC DRAM140. On the other hand, regarding through electrodes for signals, the position of a through electrode in the interposer141does not always match the position of a through electrode in the COC DRAM140.

The same configuration as inFIG. 19is used when the PCB interposer is used.

Next, a memory system according to a sixth embodiment of the present invention will be described with reference toFIGS. 20A and 20B.

The memory system according to this embodiment is different from the memory system shown inFIGS. 15A and 15Bin that a Si interposer-I/F LSI190, which serves as an interposer and also as an I/F LSI, is used instead of the interposer141. That is, the COC DRAM140including four stacked DRAM chips is stacked on the Si interposer-I/F LSI190, so that a stacked DRAM193is formed.

A PCB191shown inFIGS. 20A and 20Bis provided for ensuring reliability, but is not required in terms of the characteristic.

The chip set143and a plurality of stacked DRAMs are arranged on the motherboard142in the same layout and connection as inFIGS. 15A and 15B. When DQ and DQS signals are transmitted between the chip set143and the COC DRAM140, the first 8 bits are transmitted to/from stacked DRAMs193a1and193b1, the next 8 bits are transmitted to/from stacked DRAMs193a2and193b2, and the last 8 bits are transmitted to/from stacked DRAMs193a8and193b8. A fly-by method as shown in the figure is used as a connecting method, and the Si interposer-I/F LSI190is disposed between the chip set143and the COC DRAM140. When the characteristic impedance of the motherboard142is Z0, each signal line may be terminated by connecting a terminating resistor R3which is lower than Z0to the far end of a DQ main bus. Since a load (Si interposer-I/F LSI190) is connected to the transmission line, causing an increase in capacity, and the effective characteristic impedance decreases, the resistance of the terminating resistor R3is matched with the effective characteristic impedance.

When a CA signal is transmitted between the chip set143and the COC DRAM140, one copy of CA signal is transmitted to/from stacked DRAMs193a1,193a2, . . . , and193a8, and another copy of CA signal is transmitted to/from stacked DRAMs193b1,193b2, . . . , and193b8. This is the same for a CLK signal for capturing the CA signal. The connection method is a fly-by method as shown in the figure, and the signal lines for CA and CLK signals are orthogonal to the signal lines for DQ and DQS signals. In the signal lines for these signals, too, the Si interposer-I/F LSI190exists between the chip set143and the COC DRAM140. When the characteristic impedance of the motherboard142is Z0, a terminating resistor R4which is lower than Z0is connected to the far end of a CA main bus.

In the memory system according to this embodiment, every wiring line for DQ and CA signals branches from the main bus in the motherboard142to the Si interposer-I/F LSI190, and is not directly wired to the COC DRAM as inFIGS. 15A and 15B. Therefore, the stub length is short and a high-speed operation can be realized.

Next, the operation of the memory system shown inFIGS. 20A and 20Bwill be described.

First, a case where data in the chip set143is written into the COC DRAM140awill be described.

A DQ signal, a CA signal, and so on are output from the chip set143. Preferably, the ON resistance of the driver of the chip set143should be matched with the effective characteristic impedance of each main bus.

The Si interposer-I/F LSI190abuffers the signals input from the chip set143and outputs the signals to the COC DRAM140a. The COC DRAM140adecodes the command signal from the Si interposer-I/F LSI190aand writes the data in a corresponding address. Herein, a terminator is not required between the Si interposer-I/F LSI190aand the COC DRAM140a.

A process of writing data into the COC DRAM140bis performed in the same way.

Next, a case where data is read from the COC DRAM140awill be described.

A CA signal and so on are output from the chip set143. The CA signal and so on output from the chip set143are supplied via the Si interposer-I/F LSI190ato the COC DRAM140a. The COC DRAM140adecodes the command signal and reads the data from a corresponding address. The read data is transmitted via the Si interposer-I/F LSI190ato the chip set143and is captured therein. Preferably, in the reading process, a terminating resistor R3is provided in the chip set143. A terminator is not necessary between the Si interposer-I/F LSI190aand the COC DRAM140ain the reading process.

The same process is performed when data is read from the COC DRAM140b.

According to the memory system of this embodiment, a signal is once shut off at the Si interposer-I/F LSI190, so that the stub length can be shortened and high-speed operation can be realized. Further, even if the number of stacked DRAM chips in the COC DRAM140increases, the load of the main bus does not change, that is, the load is only the Si interposer-I/F LSI190. Accordingly, both capacity and speed can be increased. Further, the stub length can be short even if the size of the Si interposer-I/F LSI190is large.

FIG. 21shows an example of the positional relationship of the through electrodes in the COC DRAM and the through electrodes and balls of the Si interposer-I/F LSI in the stacked DRAM of the memory system shown inFIGS. 20A and 20B.

InFIG. 21, large circles indicate to the balls of the Si interposer-I/F LSI, white small circles indicate the through electrodes in the Si interposer-I/F LSI, and black small circles indicate the through electrodes in the COC DRAM.

As described above with reference toFIG. 6, the through electrodes of the COC DRAM may be provided at the periphery of the chip and a peripheral-circuit area of the chip such as a center line, and thus they are provided in those areas. Further, through electrodes of the I/F LSI and the COC DRAM are disposed immediately above the balls assigned to VDD and GND. Through electrodes of the I/F LSI are disposed immediately above the balls assigned to signals.

By arranging the through electrodes in the above described manner, VDD and GND potentials are supplied to the Si interposer-I/F LSI190and the COC DRAM140in the shortest distance. Accordingly, stable power supply can be realized.

FIG. 22shows another example of the positional relationship of the through electrodes in the COC DRAM and the through electrodes and balls of the Si interposer-I/F LSI in the stacked DRAM of the memory system shown inFIGS. 20A and 20B. The major difference fromFIG. 21is that the through electrodes in the COC DRAM140are aligned on the center line to a possible extent. Since the most part of pads is often provided on the center line in current DRAMs, the layout of the current DRAM chip can be utilized and a designing period can be shortened.

FIG. 23is a longitudinal cross-sectional view showing the structure of the stacked DRAM shown inFIGS. 20A and 20B, orFIG. 21or22. InFIG. 23, a through electrode for power supply is disposed through the Si interposer-I/F LSI190and the COC DRAM140. Through electrodes for a signal are separately provided in the Si interposer-I/F LSI190and the COC DRAM140. These through electrodes are connected to each other via a logic circuit and the like in the Si interposer-I/F LSI190. The connection in the Si interposer-I/F LSI190is performed bidirectionally for a DQ signal because the DQ signal is a bidirectional signal.

As can be understood from the description, the length of a stub branched from the motherboard142into the Si interposer-I/F LSI190is short.

Next, a memory system according to a seventh embodiment of the present invention will be described with reference toFIGS. 24A and 24B.

In the memory system shown inFIGS. 24A and 24B, the speed of the main bus is increased by N times, e.g., 4 times. The memory system includes a plurality of stacked DRAMs234, each having a COC DRAM231including 4 to 8 stacked DRAM chips and an interposer (Si interposer-I/F LSI232and PCB235) having the same plane size as that of the COC DRAM231. Also, the memory system includes a motherboard233for mounting the stacked DRAMs234and a chip set230mounted on the motherboard233.

The COC DRAM231is of +32 bits structure. When one channel is 64 bits, two stacked DRAMs234(234a1and234a2) as a pair are placed in parallel as shown inFIG. 24B. A plurality of pairs of stacked DRAMs234are aligned in one direction from the chip set230. InFIG. 24B, four pairs of stacked DRAMs234are shown.

The Si interposer-I/F LSI232is connected to the PCB235, which has the same plane size as that of the Si interposer-I/F LSI232, by flip-chip connection as shown inFIG. 24A, and is further connected to the motherboard233by using solder balls of the PCB235. In this case, a combination of the Si interposer232and the PCB235may be regarded as an interposer. Alternatively, the Si interposer-I/F LSI232may be directly mounted on the motherboard233by using flip-chip connection.

Transmission of DQ and DQS signals between the chip set230and the COC DRAM231is performed by using signal lines connected in a fly-by method. That is, the chip set230transmits 8 bits of the DQ and DQS signals to the stacked DRAMs234a1to234d1at quadruple speed, and transmits the other 8 bits to the stacked DRAMs234a2to234d2at quadruple speed.

When the characteristic impedance of the wiring of the motherboard233is Z0, the signal lines for DQ and DQS signals are terminated by connecting a terminating resistor R5which is lower than Z0to the far end of the main bus. Since a load is connected to the transmission line, causing an increase in capacity and a decrease in the effective characteristic impedance, the value of the terminating resistor R5is matched with the effective characteristic impedance.

Transmission of a CA signal between the chip set230and the COC DRAM231is performed by using signal lines of a fly-by method, as the signal lines for DQ and DQS signals. These signal lines are provided in parallel with the signal lines for DQ and DQS signals. The chip set230transmits/receives one copy of CA signal to/from the DRAMs234a1to234d1, and transmits/receives another copy of CA signal to/from the DRAMs234a2to234d2. This is the same for a CLK signal for capturing the CA signal.

When the characteristic impedance of the motherboard233is Z0, the signal line for the CA signal is terminated by connecting a terminating resistor R6which is lower than Z0to the far end.

Each of the signal lines for DQ and CA signals branches from the main bus running in the motherboard233toward each COC DRAM231. If the stub by the branch is long, the amount of signal reflection becomes large at that point, so that the signal integrity is deteriorated. In the memory system according to this embodiment, the Si interposer-I/F LSI232is disposed between the COC DRAM231and the main bus. Therefore, the stub length is short and high signal integrity can be realized.

Next, the operation of the memory system shown inFIGS. 24A and 24Bwill be described.

First, a case where data in the chip set230is written into the COC DRAM231awill be described.

A DQ signal, a CA signal, and so on are output from the chip set230. Preferably, the ON resistance of the driver of the chip set230should be matched with the effective characteristic impedance of each main bus.

The Si interposer-I/F LSI232abuffers the input signals from the chip set230or performs speed conversion and outputs the signals to the COC DRAM231a. Herein, a terminator is not necessary between the Si interposer-I/F LSI232aand the COC DRAM231a.

The COC DRAM231adecodes the input command signal and writes the data in a corresponding address.

The same process is performed in a case where data is written into another COC DRAM, such as the COC DRAM231b.

Next, a case where data is read from the COC DRAM231awill be described.

A CA signal and so on are output from the chip set230. The Si interposer-I/F LSi232aoutputs the CA signal and so on from the chip set230to the COC DRAM231a. The COC DRAM231adecodes the input command signal and reads data from a corresponding address. The read data is transmitted via the Si interposer-I/F LSI232ato the chip set230and is captured therein. Therefore, a terminating resistor should be provided in the chip set230in the reading process. The value of the terminating resistor is equal to the effective characteristic impedance of the main bus. That is, the value is equal to that of the terminating resistor R5or R6. A terminator is not required between the Si interposer-I/F LSI232aand the COC DRAM231ain the reading process.

The same process is performed in a case where data is read from another COC DRAM, such as the COC DRAM231b.

According to the memory system of this embodiment, since a signal is once shut off at the Si interposer-I/F LSI232, the stub length is short and high-speed operation can be realized. Further, even if the number of DRAM chips of the COC DRAM increases, the load of the main bus does not change, that is, the load is only the Si interposer-I/F LSI232. Accordingly, both capacity and speed can be increased. Further, even if the bit structure of the DRAM increases and the size of the Si interposer-I/F LSI232increases, the stub length can be kept short.

FIGS. 25A and 25Bshow a memory system according to an eighth embodiment of the present invention. This memory system is different from that inFIGS. 24A and 24Bin that a plurality of COC DRAMs241of +16 bits structure are included.

More specifically, this memory system includes the motherboard233, a chip set240mounted on the motherboard233, and a plurality of stacked DRAMs244.

Each of the stacked DRAMs244includes 8 to 16 stacked DRAM chips, a Si interposer-I/F LSI242, and a PCB245. The Si interposer-I/F LSI242is connected to the PCB245by flip-chip connection, and the PCB245is connected to the motherboard233by using solder balls. The PCB245is not always necessary, and the Si interposer-I/F LSI242may be directly connected to the motherboard233by flip-chip connection.

When one channel is 64 bits, four stacked DRAMs244are used as one group (only two of them for 0.5 channels are shown in the figure). According to the storage capacity, a plurality of groups of stacked DRAMs are arranged in one direction from the chip set240. The four stacked DRAMs244in each group are at substantially the same distance from the chip set240.

A signal transmission line is provided between the chip set240and the Si interposer-I/F LSI242by point-to-point connection. The wiring in the motherboard233has characteristic impedance Z0. Also, a signal transmission line between adjoining Si interposers-I/F LSIs242is connected by point-to-point connection. The wiring is provided at characteristic impedance Z0in the motherboard233. The receiving side of each transmission line of point-to-point connection is terminated by terminating resistance Z0and the driver side is matched with source resistance Z0. In this way, reflection of a transmitted signal at a point-to-point connection can be suppressed and favorable signal integrity can be obtained.

Signal transmission between the Si interposer-I/F LSI242and the COC DRAM241is performed via a through electrode246, which is disposed in the COC DRAM241. Only one through electrode is shown in each COC DRAM241inFIG. 25A, but a required number of through electrodes for a DQ signal, power supply, and so forth, are provided. The transmitted signals include a DQ signal, a DQS signal, a CA signal, and a CLK signal. These signals are transmitted/received by type. All the wiring lines for these signals have the same topology, and thus skew of each signal is hardly generated. Further, the length of the through electrode in the COC DRAM241is short, about 0.4 mm when 8 DRAM chips are stacked. Therefore, this transmission part can be regarded as a lumped-constant circuit and a terminating resistance is not required. Accordingly, since a terminating resistor need not be provided in a signal transmission line between the Si interposer I/F LSI242and the COC DRAM241, operation at low power consumption can be realized.

Next, the operation of the memory system according to this embodiment will be described.

First, a case where data in the chip set240is written into the COC DRAM241awill be described.

A protocol signal, including information such as a DQ signal and a CA signal, is supplied from the chip set240to the Si interposer-I/F LSI242a. The Si interposer-I/F LSI242adecodes the signal from the chip set240according to the protocol, and outputs a CA signal, a DQ signal, a CLK signal, and so on to the COC DRAM241a. The COC DRAM241awrites the data in a corresponding address according to the input CA signal and so on.

When data is to be written into the COC DRAM241b, a protocol signal output from the chip set240is transmitted via the Si interposer-I/F LSI242ato the Si interposer-I/F LSI242b. The Si interposer-I/F LSI242bdecodes the input signal according to the protocol and outputs a CA signal, a DQ signal, a CLK signal, and so on to the COC DRAM241b. The COC DRAM241bwrites the data in a corresponding address according to the signals from the Si interposer-I/F LSI242b.

Writing of data into another COC DRAM241cor the like is performed in the same way.

Next, a case where data is read from the COC DRAM241awill be described.

A protocol signal, including information such as a CA signal, is supplied from the chip set240to the Si interposer-I/F LSI242a. The Si interposer-I/F LSI242adecodes the signals according to the protocol and outputs a CA signal, a CLK signal, and so on to the COC DRAM241a. The COC DRAM241areads data from a corresponding address according to the signals from the Si interposer-I/F LSI242a. The read data is captured into the Si interposer-I/F LSI242aand is then transmitted as a protocol signal to the chip set240.

When data is to be read from the COC DRAM241b, a protocol signal, including information such as a CA signal, is supplied from the chip set240to the Si interposer-I/F LSI242bvia the Si interposer-I/F LSI242a. The Si interposer-I/F LSI242bdecodes the input signal according to the protocol and outputs a CA signal, a CLK signal, and so on to the COC DRAM241b. The COC DRAM241breads data from a predetermined address according to the input signals. The read data is captured into the Si interposer-I/F LSI242b, and is transmitted as a protocol signal to the chip set240via the Si interposer-I/F LSI242a.

A process of reading data from the COC DRAM241cor the like can be performed in the same manner.

According to the memory system of this embodiment, the bit structure of the COC DRAM241is small and the data rate of a protocol signal is high. Therefore, the size of the SI interposer-I/F LSI242can be equivalent to that of the COC DRAM241, so that an interposer of a transmission-line structure is not required. Further, high-speed operation can be realized because point-to-point connection is used at each signal line.

Next, a method for stacking a COC DRAM and an I/F LSI which can be applied to the memory systems according to the fifth to eighth embodiments will be described with reference toFIGS. 26A to 26F. The I/F LSI of the above-described memory system includes through electrodes, but the method described below is for stacking an I/F LSI which does not include any through electrode (difficult to provide through electrode).

First, as shown inFIG. 26A, a DRAM core253-1, in which through electrodes252are disposed in the upper surface, is connected and fixed to a supporter250by using an adhesive251.

Then, the DRAM core253-1is grinded from the rear side so that the through electrodes are exposed. Then, through electrode terminals254are attached to the exposed through electrodes, as shown inFIG. 26B. In this way, one layer of DRAM chip is formed.

After that, another DRAM core253-2, which is the same as the DRAM core253-1, is stacked on the DRAM core253-1provided with the through electrode terminals254, as shown inFIG. 26C. Then, the rear surface of the DRAM core253-2is grinded so that the through electrodes are exposed, and through electrode terminals are attached thereto.

Then, steps of stacking a DRAM core, grinding it, and attaching through electrode terminals are repeated, so as to form a desired number of layers of DRAM chips.

Then, as shown inFIG. 26D, an I/F LSI256which does not include any through electrode is connected to/stacked on through electrode terminals of the last DRAM chip such that the I/F LSI256is disposed face up.

Then, as shown inFIG. 26E, the supporter250is removed and the adhesive251is peeled.

Finally, flip-chip connection terminals257or the like are connected to the through electrodes on the upper surface of the stacked DRAM, as shown inFIG. 26F.

Next, the flow of a signal in the stacked DRAM manufactured by using the stacking method shown inFIGS. 26A to 26Fwill be described.

A signal which has entered the flip-chip connection terminal257is once input to the I/F LSI256via a through electrode258. The signal input to the I/F LSI256is processed by logical operation or the like therein, is output to a through electrode259, and is supplied to each DRAM chip253via the through electrode259.

A signal output from the COC DRAM253traces the opposite route.

In this way, in the stacked DRAM manufactured by the stacking method shown inFIGS. 26A to 26F, a signal input from the upper side of the COC DRAM is once led to the I/F LSI on the rear side, so that the distance of signal transmission line is long. However, since the thickness of each DRAM chip is about 50 μm, delay and reflection of the signal do not cause a significant problem. Therefore, by using this stacking method, a memory system using a COC DRAM can be formed even if it is difficult to provide through electrodes in the I/F LSI.

Next, a method for stacking a COC DRAM, an I/F LSI, and an interposer will be described with reference toFIGS. 27A to 27E. In this method, no supporter is used unlike the method ofFIGS. 26A to 26F.

First, as shown inFIG. 27A, a DRAM core253-1, which includes through electrodes252in its upper surface and through electrode terminals260attached to the through electrodes252, is connected and fixed to an I/F LSI256serving as a supporter.

Then, the DRAM core253-1is grinded from its rear side so that the through electrodes are exposed. Then, through electrode terminals254are attached to the exposed through electrodes, as shown inFIG. 27B.

Then, a DARM core253-2, which is the same as the DRAM core253-1, is stacked on the lower surface of the DRAM core253-1provided with the through electrode terminals254, as shown inFIG. 27C. Then, the rear surface of the DRAM core253-2is grinded so that the through electrodes are exposed. Then, through electrode terminals are attached to the exposed through electrodes.

After that, the above-described process is repeated so as to stack a desired number of DRAM chips.

Then, as shown inFIG. 27D, an interposer264including through electrodes in its upper side is stacked on the bottom DRAM chip, so that the through electrode terminals disposed in the DRAM chip are connected to the through electrodes of the interposer264.

Finally, the rear surface of the interposer264is grinded so that the through electrodes are exposed, and flip-chip connection terminals261are connected to the exposed through electrodes, as shown inFIG. 27E. When the interposer264is not required, the flip-chip connection terminals may be connected to the exposed through electrodes of the bottom DRAM chip253-3.

Next, the flow of a signal in the stacked DRAM manufactured by the stacking method shown inFIGS. 27A to 27Ewill be described.

A signal which has entered the flip-chip connection terminal261is input to the I/F LSI256via a through electrode262. The signal entered the I/F LSI256is processed therein by logical signal processing and is then output to a through electrode263. The signal output to the through electrode263is supplied to each DRAM chip.

A signal output from the COC DRAM253traces the opposite route.

According to the method shown inFIGS. 27A to 27E, a step of removing a supporter is not performed unlike in the method ofFIGS. 26A to 26F, so that fracture of a chip caused in the removing step can be prevented.

As in the stacked DRAM manufactured by the method ofFIGS. 26A to 26F, the thickness of each DRAM chip of the stacked DRAM manufactured by the method ofFIGS. 27A to 27Eis about 50 μm. With this configuration, delay and reflection of a signal do not cause a significant problem even if the signal input from the lower side is supplied to each DRAM chip via the I/F LSI on the upper side. Therefore, by using this stacking method, a memory system using an interposer and a COC DRAM can be formed even if it is difficult to provide through electrodes in the I/F LSI.