Image sensor for suppressing readout time of image signal and focus detection signal, control method therefor, and image capturing apparatus

An image sensor comprises: a pixel array having a plurality of photoelectric conversion portions provided for each of a plurality of microlenses arranged in matrix; a plurality of signal output lines provided for each column of the pixel array; signal readout circuits each provided for each column of the pixel array; and a control circuit that controls to output a signal of a selected row to one of the plurality of signal output lines and controls to process the signal by the corresponding signal readout circuit. The control circuit performs control such that while a signal of a first row output to one of the plurality of signal output lines is processed by the corresponding signal readout circuit, a signal from a second row is output to another of the plurality of signal output lines.

BACKGROUND OF THE INVENTION

Field of the invention

The present invention relates to an image sensor, a control method therefor, and an image capturing apparatus, and more specifically to an art of circuit configuring an image sensor.

Description of the Related Art

In recent years, in image capturing apparatuses using image sensors such as CMOS sensors, multifunctionality has progressed, and not only generation of captured images such as still images/moving images, but also control of image capturing apparatuses such as focus adjustment, for example, are performed based on information obtained from the image sensors.

For example, Japanese Patent Laid-Open No. 2001-124984 discloses a technique capable of performing focus detection using a pupil division method by using signals obtained from an image sensor. In Japanese Patent Laid-Open No. 2001-124984, by providing one microlens (ML) and two photodiodes (PD) for each pixel of the image sensor, respective PDs capture light passing through different pupil regions of the imaging lens. By comparing output signals from the two PDs of each pixel, focus detection becomes possible, and it is also possible to generate a captured image by adding the output signals from the two PDs for each pixel.

In addition, Japanese Patent Laid-Open No. 2016-21052 discloses a technique of acquiring signals for focus detection only from a part of rows in a screen.

However, in the conventional technique disclosed in the above-mentioned Japanese Patent Laid-Open No. 2001-124984, since it is necessary to read a focus detection signal in addition to an image signal, the readout time increases.

Further, in the technique disclosed in Japanese Patent Laid-Open No. 2016-21052, an increase in the readout time is suppressed by reading the focus detection signal only from a part of the rows in the screen. However, the readout time differs between in a row from which only the image signal is read out and in a row from which both the image signal and focus detection signals are read out. Consider, for example, a case where a subject moving at a high speed is captured by the rolling shutter driving method disclosed in Japanese Patent Laid-Open No. 2016-21052. In this case, in addition to the conventionally known rolling distortion phenomenon, distortion also occurs between the rows from which only the image signal is read out and the rows from which the image pickup signal and the focus detection signals are read out, and there is concern about giving the user a feeling of discomfort.

SUMMARY OF THE INVENTION

The present invention has been made in consideration of the above situation, and suppresses an increase in readout time for obtaining an image signal and focus detection signals.

According to the present invention, provided is an image sensor comprising: a pixel array having a plurality of photoelectric conversion portions provided for each of a plurality of microlenses arranged in matrix; a plurality of signal output lines provided for each column of the pixel array; signal readout circuits each provided for each column of the pixel array; and a control circuit that controls to output a signal of a selected row to one of the plurality of signal output lines and controls to process the signal by the corresponding signal readout circuit, wherein the control circuit performs control such that while a signal of a first row output to one of the plurality of signal output lines is processed by the corresponding signal readout circuit, a signal from a second row, different from the first row, is output to another of the plurality of signal output lines.

Further, according to the present invention, provided is an image capturing apparatus including: an image sensor comprising: a pixel array having a plurality of photoelectric conversion portions provided for each of a plurality of micro lenses arranged in matrix; a plurality of signal output lines provided for each column of the pixel array; signal readout circuits each provided for each column of the pixel array; and a control circuit that controls to output a signal of a selected row to one of the plurality of signal output lines and controls to process the signal by the corresponding signal readout circuit, and a processor that processes a signal output from the image sensor, wherein the control circuit performs control such that while a signal of a first row output to one of the plurality of signal output lines is processed by the corresponding signal readout circuit, a signal from a second row, different from the first row, is output to another of the plurality of signal output lines.

Furthermore, according to the present invention, provided is a control method of an image sensor that has a pixel array having a plurality of photoelectric conversion portions provided for each of a plurality of microlenses arranged in matrix, a plurality of signal output lines provided for each column of the pixel array, and signal readout circuits each provided for each column of the pixel array, the method comprising: processing, while outputting a signal from a first row to one of the plurality of signal output lines, a signal output from a row different from the first row to another of the plurality of signal output lines by the corresponding signal readout circuit; and outputting, while processing the signal output from the first row to the one of the plurality of signal output lines by the corresponding signal readout circuit, a signal output from a row different from the first row to another of the plurality of signal output lines.

DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the present invention will be described in detail in accordance with the accompanying drawings.

FIG. 1is a diagram showing a circuit configuration of a unit pixel10according to an embodiment. Each unit pixel10is formed for each of a plurality of microlenses (ML), not shown, which are arranged in a matrix. The unit pixel10has photodiodes (PD)11aand11b(photoelectric conversion portions), transfer switches12aand12b,a floating diffusion portion (PD)13, an amplification MOS amplifier14, a row selection switch15, and a reset switch16.

The PDs “11aand11bare formed under one microlens, and generate electric charges corresponding to light incident through different pupil regions of an imaging optical system that will be described later. The transfer switches12aand12bare driven by transfer pulses ϕTXA and ϕTXB input to their gate terminals, and transfer the charge generated at the PD11aand PD11bto the FD13. In a case where only the transfer switch12a(or12b) is controlled, a signal can be read out only from the PD11a(or11b). Further, in a case where both of the transfer switches12aand12bare simultaneously controlled, the charge generated at the PD11aand PD11bare added in the FD13, and thereby it is possible to read out an added signal of the PD11aand PD11b.Hereinafter, an image obtained from the signal read out from the PD11ais referred to as an A image, an image obtained from the signal read out from the PD11bis referred to as a B image, and an image obtained from an added signal read out from PD11aand PD11bis referred to as an A+B image.

The FD13functions as a charge voltage converting unit that temporarily accumulates the charge and converts the accumulated charge into a voltage signal. The amplification MOS amplifier14functions as a source follower together with constant current circuits22aand22bto be described later, and a signal that has undergone charge-voltage conversion by the FD13is input to the gate thereof.

The row selection switch15is driven by a row selection pulse ϕSELR input to its gate, its drain is connected to the amplification MOS amplifier14, and its source is connected to a vertical output line21(signal output line) to be described later. The row selection switch15provided with the row selection pulse ϕSELR of a high level enters a conducting state, and the source of the amplification MOS amplifier14corresponding thereto is connected to the vertical output line21.

The reset switch16has its drain connected to the power supply line VDD and is driven by a reset pulse ϕRES input to its gate to remove the charge accumulated in the FD13. Also, by turning ON the reset switch16and the transfer switches12aand12bat the same time, the PDs11aand11bcan be reset. It should be noted that the amplification MOS amplifier14outputs a reset signal to the vertical output line21when the FD13is reset by the reset pulse ϕRES. In addition, when the charge generated in the PDs11aand11bis transferred by the transfer pulses ϕTXA and ϕTXB, a transferred signal including a signal obtained by the photoelectric conversion of the PDs11aand11bis output.

FIG. 2shows the configuration of a signal readout circuit20according to this embodiment. The signal readout circuit20is configured with two vertical output lines21aand21band one signal readout circuit per unit pixel. To the signal readout circuit20, the signals of the two vertical output lines21aand21bare input. The constant current circuits22aand22bare connected to the two vertical output lines21aand21b,respectively, and function as source follower circuits together with the amplification MOS amplifier14. At this time, the potential of a signal in the FD13is reflected in the potential of the vertical output line21aor21b.

The signal readout circuit20includes two input changeover switches23aand23b,two clamp capacitors24aand24b,a differential amplifier25, a gain capacitor26, a clamp switch27, and an AD conversion circuit (ADC)28. The two clamp capacitors24aand24bare connected to corresponding vertical output lines21aand21b,respectively.

The input changeover switches23aand23bare driven by vertical output line switching pulses ϕSELCa and ϕSELCb input to the respective gates to switch connection/disconnection between the differential amplifier25and the clamp capacitors24aand24b.As a result, the clamp capacitors24aand24bcan be selectively connected to the differential amplifier25. The differential amplifier25, the clamp capacitors24aand24b,and the gain capacitor26operate as analog gain amplifiers by being connected as shown in the figure, and output analog signals to the AD conversion circuit28.

The clamp switch27is driven by a clamp pulse ϕC0R input to its gate to short between the output terminal and one of the input terminals of the differential amplifier25. A reference voltage VC0R is input to the other input terminal of the differential amplifier25, and when the clamp switch27becomes an active level (high level), the output terminal and the input terminal of the differential amplifier25are reset to the reference voltage VC0R.

The AD conversion circuit28is connected to the output terminal of the differential amplifier25, and converts the analog signal outputted from the differential amplifier25into a digital signal and outputs it. In this embodiment, the circuit that operates as an analog gain amplifier is provided upstream of the AD conversion circuit28. However, this circuit may be omitted and the vertical output lines21aand21band the AD conversion circuit28may be connected via the input changeover switches23aand23b.

In the above description, only one unit pixel and one signal readout circuit are described, however, unit pixels are actually arranged by rows and columns in a matrix, and the signal readout circuit20is configured for each column of unit pixels.

FIG. 3is a block diagram showing a configuration of part of an image sensor1in this embodiment. The image sensor1includes a pixel array100in which the unit pixels10shown inFIG. 1are arranged in a matrix, a plurality of signal readout circuits20each provided for each column of the pixel array100, and a readout control circuit30for controlling signal readout on a row-by-row basis. In the example shown inFIG. 3, the unit pixels10located in the odd rows are connected to the vertical output lines21a,and the unit pixels10located in the even rows are connected to the vertical output lines21b.InFIG. 3, the unit pixels10for 4 rows and 4 columns are shown as the pixel array100, but normally the pixel array100is composed of hundreds of thousands to tens of millions of the unit pixels10.

The readout control circuit30supplies the row selection pulse ϕSELR, the reset pulse ϕRES, and the transfer pulses ϕTXA and ϕTXB to one of the unit pixel rows to control the signal output operation to the vertical output lines21aand21b.In addition, the readout control circuit30supplies the vertical output line switching pulses ϕSELCa and ϕSELCb and the clamp pulse ϕC0R to the signal readout circuits20to control the signal readout operation of the vertical output lines21aand21b.In the description ofFIG. 3and the subsequent description, the “reset pulse ϕRES for the n-th row” is referred to as “reset pulse ϕRES(n)” with the suffix n. This also applies to the transfer pulses ϕTXA and ϕTXB and the row selection pulse ϕSELR.

Also, in this embodiment, a configuration in which the signal readout circuit20is shared by pixel units10in each column of the pixel array100is explained, but the gist of the present invention is not limited thereto, and various configurations can be adopted. For example, in a stacked type image sensor having a first substrate and a second substrate connected via a bump junction or the like, the pixel array100is provided on the first substrate, and a plurality of the signal readout circuits20may be arranged on the second substrate so that each signal readout circuit20is provided for each unit pixel10or for each group of unit pixels10.

Hereinafter, a driving method for reading out the focus detection signals at high speed in addition to the image signal according to a first embodiment of the present invention will be described. Before explaining in detail the operation of reading out the signal of the unit pixel10, the outline of the operation in the first embodiment will be described.FIG. 4is a diagram schematically showing a flow of a signal output operation executed by the unit pixel10and a signal readout operation executed by the signal readout circuit20under control of the readout control circuit30. Reading out of the signal of the unit pixel10is broadly divided into the following six operations A to F.Operation A: The readout control circuit30turns on the reset switch16of the unit pixel10and causes a signal output operation to be executed, wherein the signal output operation is to output a reset signal to either of the vertical output lines21aand21bto which the unit pixel10is connected. Then waiting for the reset signal outputted to one of the vertical output lines21aand21bto settle is performed.Operation B: The readout control circuit30causes the signal readout circuit20to execute a signal readout operation, wherein the signal readout operation is to read out the reset signal output to one of the vertical output lines21aand21bto the signal readout circuit20.Operation C: The readout control circuit30turns on the transfer switch12aor12bof the unit pixel10to output a transferred signal from the PD11aor the PD11bto the FD13, and causes a signal output operation to be executed, wherein the signal output operation is to output the signal held in the FD13to either of the vertical output lines21aand21bto which the unit pixel10is connected. Then, waiting for the transferred signal output to one of the vertical output lines21aand21bto settle is performed. In the first embodiment, it is assumed that the transfer switch12ais turned on, and a transferred signal A from the PD11ais output to one of the vertical output lines21aand21b.Operation D: The readout control circuit30causes the signal readout circuit20to execute a signal readout operation, wherein the signal readout operation is to read out the transferred signal A output to one of the vertical output lines21aand21bvia the signal readout circuit20.Operation E: The readout control circuit30turns on the transfer switch12aor12bof the unit pixel10which was not turned on in the operation C to output a transferred signal A+B from the PD11aand the PD11bin the FD13, and causes a signal output operation to be executed, wherein the signal output operation is to output the signal A+B held in the FD13to either of the vertical output lines21aand21bto which the unit pixel10is connected. Then, waiting for the transferred signal A+B output to one of the vertical output lines21aand21bto settle is performed.Operation F: The readout control circuit30causes the signal readout circuit20to execute a signal readout operation, wherein the signal readout operation is to read out the transferred signal A+B output to one of the vertical output lines21aand21bvia the signal readout circuit20.

The readout control circuit30executes the operation A(n) for the n-th row and outputs a reset signal to the vertical output line21a.At this time, as will be described in detail later, the operation F(n−1) is executed for the (n−1)-th row. In the operation A(n), the vertical output line21ais used, however, the signal readout circuit20is not used. Accordingly, in the first embodiment, while performing the operation A(n), the operation F is performed for another unit pixel row using the other vertical output line21b.

Next, the readout control circuit30executes the operation B(n) by controlling the signal readout circuit20, and the reset signal output to the vertical output line21ais read out to the signal readout circuit20. In addition, the readout control circuit30executes the operation A(n+1) for the (n+1)-th row. In other words, the readout control circuit30executes the operation B(n) of reading out the reset signal output from the unit pixels10in the n-th row and the operation A(n+1) of outputting the reset signal output from the unit pixels10in the (n+1)-th row to the vertical output line21bin parallel.

Next, the readout control circuit30controls the signal readout circuit20to execute the operation B(n+1) of reading out the reset signal of the (n+1)-th row, thereby reading out the reset signal output to the vertical output line21bto the signal readout circuit20. In this way, after the operation B(n) of reading out the reset signal of the n-th row is completed, the operation B(n+1) of reading out the reset signal output to the vertical output line21bcan be immediately performed without waiting for time required for performing the operation A(n+1) of outputting the reset signal of the (n+1)-th row. As a result, it is possible to increase the readout speed.

in the operation B(n+1) of reading out the reset signal of the (n+1)-th row to the signal readout circuit20, the vertical output line21band the signal readout circuit20is used, but the vertical output line21ais not used. Accordingly, in the first embodiment, while performing the operation B (n+1), the operation C(n) is performed for the n-th row using the other vertical output line21a,and the transferred signal A from the PDs11ain the n-th row is output to the vertical output line21a.

Thereafter, similarly to the above operation, the readout control circuit30controls to concurrently read out the signals from the unit pixels10in the n-th row and the signals from the unit pixels10in the (n+1)-th row using the two vertical output lines21aand21b.Namely, the readout control circuit30controls to concurrently execute the operation D(n) for the n-th row and the operation C(n+1) for the (n+1)-th row, then, to concurrently execute the operation E(n) for the n-th row and the operation D(n+1) for the (n+1)-th row. Furthermore, the readout control circuit30controls to concurrently execute the operation F(n) for the n-th row and the operation E(n+1) for the (n+1)-th row.

After the operation F(n) for the n-th row is finished, then the operation A(n+2) for the (n+2)-th row and the operation F(n+1) for the (n+1)-th row is are performed. Then, similarly to the above operation, signals are read out from the unit pixels10of all of the pixel array100by 2 rows.

Since it becomes possible to perform the operations A, C and E in which the vertical output line21aor21bsettle in parallel with the operations B, D and F that use the signal readout circuit20, as explained above, it is possible to increase the readout speed.

It should be noted that, in the above example, the case where the operation B(n) for the n-th row and the operation A(n+1) for the (n+1)-th row are performed in parallel has been described. However, the present invention is not limited thereto, and readout of a signal that has been output to the vertical output line21bfor the (n+1)-th line to the signal readout circuit20needs to be performed while reading out a signal from the unit pixels10in the nth row to the vertical output line21a.For example, control may be made to perform the operation B(n) and the operation C(n+1) in parallel.

With the operation above, it is possible to obtain the A image and the A+B image. The A+B image is used as a captured image, and it is possible to perform a focus detection by generating a B image by subtracting the A image from the A+B image, and comparing the A image and the B image.

Next, a specific operation performed by the readout control circuit30in the first embodiment will be described in detail using a timing chart.FIG. 5is a timing chart showing the signal output operation and the signal readout operation performed by the readout control circuit30in the first embodiment. In this timing chart, control pulses, “Vline a” that indicates the potential of the vertical output line21a,and “Vline b” that indicates the potential of the vertical output line21bare illustrated. In the following explanation, the pulse level that turns on each switch is expressed as a high level “H”, and the pulse level that turns off each switch is expressed as a low level “L”.

In a period t1, the row selection pulse ϕSELR(n) becomes “H”, and the unit pixel10in the n-th row starts outputting a signal to the corresponding vertical output line21a.At the same time, the reset pulse ϕRES(n) becomes “H” to eliminate the unnecessary charge of the FDs13in the nth row, and it becomes “L” after resetting the potential of the FDs13. At this time, the unit pixels10in the n-th row outputs a reset signal to the vertical output line21a.The reset signal is reflected on the vertical output line21aover the settling time as indicated by Vline a (operation A(n)).

In a period t2, the vertical output line switching pulse ϕSELCa becomes “H” and the vertical output line switching pulse ϕSELCb becomes “L”, thereby the differential amplifier25is connected to the vertical output line21avia the clamp capacitor24a.At this time, the signal readout circuit20reads out the reset signal from the vertical output line21a.At the same time, the clamp pulse ϕC0R becomes “H”, and the input terminal and the output terminal of the differential amplifier25are reset to the reference voltage VC0R. Thereafter, the clamp pulse ϕC0R becomes “L”, and the clamp capacitor24aclamps (holds) the reset signal of the n-th row to the reference voltage VC0R (Operation B(n)). Further, in the same period t2, the row selection pulse ϕSELR(n+1) becomes “H”, and each of the unit pixels10in the (n+1)-th row starts outputting a signal to the corresponding vertical output line21b.At the same time, the reset pulse ϕRES(n+1) becomes “H” to eliminate the unnecessary charging of the FDs13in the (n+1)-th row, and it becomes “L” after resetting the potential of the FDs13. At this time, the unit pixels10in the (n+1)-th row output the reset signal to the vertical output line21b.The reset signal is reflected on the vertical output line21bover the settling time as indicated by Vline b (operation A(n+1)).

In a period t3, the vertical output line switching pulse ϕSELCa becomes “L” and the vertical output line switching pulse ϕSELCb becomes “H”, so that the clamp capacitor24ais disconnected from the differential amplifier25, and the clamp capacitor24bis connected instead. At this time, the signal readout circuit20reads out the reset signal from the vertical output line21b.The clamp pulse ϕC0R is “H”, and the input terminal and the output terminal of the differential amplifier25are reset to the reference voltage VC0R. Thereafter, when the clamp pulse ϕC0R becomes “L”, the clamp capacitor24bclamps (holds) the reset signal of the (n+1)-th row to the reference voltage VC0R (operation B(n+1)). Further, in the same period t3, the transfer pulse ϕTXA(n) becomes “H”, and the charge accumulated in the PDs11ain the n-th row is transferred to the FDs13. Thereafter, the transfer pulse ϕTXA(n) becomes “L”, and each of the unit pixels10in the n-th row outputs the transferred signal to the corresponding vertical output line21a.The transferred signal A is reflected on the vertical output line21aover the settling time (operation C(n)).

In a period t4, the vertical output line switching pulse ϕSELCb becomes “L”, and the clamp capacitor24bis disconnected from the differential amplifier25. Further, the clamp pulse ϕC0R becomes “H” and the input terminal and the output terminal of the differential amplifier25are reset to the reference voltage VC0R.

In a period t5, the clamp pulse ϕC0R becomes “L” and the vertical output line switching pulse ϕSELCa becomes “H”, and the clamp capacitor24ais connected to the differential amplifier25. As a result, the signal readout circuit20reads the transferred signal A of the n-th row from the settled vertical output line21a.The differential amplifier25performs signal amplification according to the signal gain determined by the capacitance ratio of the clamp capacitor24and the gain capacitor26, and outputs the result to the AD conversion circuit28. Strictly speaking, since the reset signal is clamped to the reference voltage VC0R by the clamp capacitor24, the difference between the reset signal and the transferred signal A is amplified. The AD conversion circuit28converts the signal input from the differential amplifier25into a digital signal and outputs it to outside of the image sensor1(operation D(n)). Further, in the same period t5, the transfer pulse ϕTXA(n+1) becomes “H”, and the charge accumulated in the PDs11ain the (n+1)-th row is transferred to the FDs13. Thereafter, the transfer pulse ϕTXA(n+1) becomes “L”, and each of the unit pixels10in the (n+1)-th row outputs the transferred signal A to the vertical output line21b.The transferred signal A is reflected on the vertical output line21bover the settling time (operation C(n+1)).

In a period t6, the vertical output line switching pulse ϕSELCa becomes “L”, and the clamp capacitor24ais disconnected from the differential amplifier25. Further, the clamp pulse ϕC0R becomes “H” and the input terminal and the output terminal of the differential amplifier25are reset to the reference voltage VC0R.

In a period t7, the clamp pulse ϕC0R becomes “L” and the vertical output line switching pulse ϕSELCb becomes “H”, and the clamp capacitor24bis connected to the differential amplifier25. As a result, the signal readout circuit20reads the transferred signal A of the (n+1)-th row from the settled vertical output line21b.The differential amplifier25performs signal amplification, and outputs the result to the AD conversion circuit28. The AD conversion circuit28converts the signal input from the differential amplifier25into a digital signal and outputs it to the outside of the image sensor1(operation D(n+1)). Further, in the same period t7, the transfer pulse ϕTXB(n) becomes “H”, and the charge accumulated in the PDs11bin the n-th row is transferred to the FDs13in addition to the charge of the PDs11ain the n-th row transferred in the period t3. As a result, the FDs13hold the transferred signal A+B. Thereafter, the transfer pulse ϕTXB(n) becomes “L”, and each of the unit pixels10in the n-th row outputs the transferred signal A+B to the vertical output line21a.The transferred signal A+B is reflected on the vertical output line21aover the settling time (operation E(n)).

In a period t8, the vertical output line switching pulse ϕSELCb becomes “L”, and the clamp capacitor24bis disconnected from the differential amplifier25. Further, the clamp pulse ϕC0R becomes “H” and the input terminal and the output terminal of the differential amplifier25are reset to the reference voltage VC0R.

In a period t9, the clamp pulse ϕC0R becomes “L” and the vertical output line switching pulse ϕSELCa becomes “H”, and the clamp capacitor24ais connected to the differential amplifier25. As a result, the signal readout circuit20reads the transferred signal A+B of the n-th row from the settled vertical output line21a.The differential amplifier25performs signal amplification, and outputs the result to the AD conversion circuit28. The AD conversion circuit28convert the signal input from the differential amplifier25into a digital signal and outputs it to the outside of the image sensor1(operation F(n)). Further, in the same period t9, the transfer pulse ϕTXB(n+1) becomes “H”, and the charge accumulated in the PDs11bin the (n+1)-th row is transferred to the FDs13in addition to the charge of the PDs11ain the (n+1)-th row transferred in the period t4. As a result, the FDs13hold the transferred signal A+B. Thereafter, the transfer pulse ϕTXB(n+1) becomes “L”, and each of the unit pixels10in the (n+1)-th row outputs the transferred signal A+B to the vertical output line21b.The transferred signal A+B is reflected on the vertical output line21bover the settling time (operation B(n+1)).

In a period t10, the row selection pulse ϕSELR(n) becomes “L”, and the unit pixels10in the n-th row is disconnected from the vertical output line21a.Further, the vertical output line switching pulse ϕSELCa becomes “L”, and the clamp capacitor24ais disconnected from the differential amplifier25. Furthermore, the clamp pulse ϕC0R becomes “H” and the input terminal and the output terminal of the differential amplifier25are reset to the reference voltage VC0R.

In a period t11, the clamp pulse ϕC0R becomes “L” and the vertical output line switching pulse ϕSELCb becomes “H”, and the clamp capacitor24bis connected to the differential amplifier25. As a result, the signal readout circuit20reads the transferred signal A+B of the (n+1)-th row from the settled vertical output line21b.The differential amplifier25performs signal amplification, and outputs the result to the AD conversion circuit28. The AD conversion circuit28converts the signal input from the differential amplifier25into digital signal and outputs it to the outside of the image sensor1(operation F(n+1)). Although it is not shown, in the same period t11, the row selection pulse ϕSELR(n+2) becomes “H”, and each of the unit pixels10in the (n+2)-th row starts to output a signal to the vertical output line21a.At the same time, the reset pulse ϕRES(n+2) becomes “H” to eliminate the unnecessary charge of the FDs13, and it becomes “L” after resetting the potential of the FDs13. At this time, each of the unit pixels10in the (n+2)-th row outputs a reset signal to the vertical output line21a.The reset signal is reflected on the vertical output line21aover the settling time (operation A(n+2)). Thereafter, by repeating the same operation as from the period t2, the signals of the unit pixels10are sequentially read out.

According to the first embodiment as described above, each of the signal readout circuits20has a configuration that selects and connects one of a plurality of the vertical output lines21, and the signal readout operation from one of the vertical output lines21and the signal output operation to another vertical output lines21are performed in parallel between adjacent columns.

In the conventional technique, the operations A to F are repeated sequentially for each row without performing operations in parallel between the adjacent rows. Here, let periods required for reading signals of two rows with the operations according to the first embodiment and with the operations of the conventional technique be compared. With the operations of the conventional technique, a period for performing the operations A to F for the n-th row and the (n+1)-th row, namely, a period for performing12processes, is needed. By contrast, with the operations of the first embodiment, a period for performing the operations A to F for the n-th row and the operation F for the (n+1)-th row, namely, a period for performing the total of 7 operations, is needed. Consequently, it is possible to increase the speed by a period corresponding to 5 operations. Assuming that the operations A to F respectively take the same period, reading can be completed in about 58% of a period of the operations performed using the conventional technique.

Next, a second embodiment of the present invention will be described. In the above-described first embodiment, the readout operation for reading out the A image and the A+B image from all the unit pixels10of the pixel array100at high speed has been described. Hereinafter, the readout operation described in the first embodiment is referred to as a first readout operation, and a mode for reading out the A image and the A+B image from all the unit pixels10by the first readout operation is called a first mode. Effects of the technique of the present invention are exerted in terms of image quality not only in the case of reading out the A image and the A+B image from all the unit pixels10but also in the case of reading out the A image and the A+B image only from some rows of the pixel array100and reading out the A+B image from the other rows. In the second embodiment, an operation method in which the A image and the A+B image are read out by the first readout operation only from a part of the rows of the pixel array100and the A+B image is read out from the other rows (hereinafter referred to as a second mode) will be described.

In the second embodiment, the control by the readout control circuit30is different, from that in the above-described first embodiment, and the configuration of the image sensor1is the same as that described with reference toFIGS. 1 to 3, and therefore, the explanation thereof is omitted. Further, since the operations A to F in the following description are also the same as the operations A to F described in the first embodiment, the description of each operation will be omitted.

In the second embodiment, in addition to the operations A to F, the operations G and H are executed. Operations G and H will be described below.Operation G: The readout control circuit30turns on the transfer switches12aand12bof the unit pixel10to hold a transferred signal A+B from the PD11aand the PD11bin the FD13. Then the signal output operation is performed to output the transferred A+B held in the FD13to either of the vertical output lines21aand21bto which the unit pixel10is connected, then waited to settle.Operation H. The readout control circuit30causes the signal readout circuit20to execute a signal readout operation, wherein the signal readout operation is to read out the transferred signal A+B output to one of the vertical output lines21aand21bvia the signal readout circuit20.

FIG. 6is a diagram schematically showing a flow of a signal output operation when reading out only the transferred signal A+B. The difference from the readout operation in the first embodiment explained with reference toFIG. 4will be described below.

In the first embodiment, output and readout of the reset signal are performed in the operations A and B, output and readout of a transferred signal A in the are performed in the operations C and D, and output and readout of a transferred signal A+B are performed in operations H and F. On the other hand, in the second embodiment, a transferred signal A for focus detection is not read out and a transfer signal A+B is output in the operation G after readout of the reset signal is completed in the operation B.

That is, after outputting and reading out the reset signal in the operations A and B, the readout control circuit30controls to perform the operation. G(n) for the n-th row and the operation B(n+1) for the (n+1)-th row.

Next, the operation H(n) is performed for the n-th row and the operation G(n+1) is executed for the (n+1)-th row.

When the operation H(n) is ended for the n-th row, next, the operation A(n+2) is executed for the (n+2)-th row and the operation H(n+1) is executed for the (n+1)-th row. Thereafter, signals are read out from all the unit pixels10of the pixel array100in a similar manner. By the above-described operation, an A+B image can be obtained.

As described above, it is possible to execute the operations A and G that includes signals in the vertical output line21aor21bsettling in parallel with the operations B and H using the signal readout circuit20, therefore, it is possible to increase the readout speed. Hereinafter, the readout operation described with reference toFIG. 6is referred to as a second readout operation.

Next, a specific procedure of the second readout operation will be described.FIG. 7is a timing chart showing the signal output operation and the signal readout operation performed by the readout control circuit30in the second embodiment. Here, only the portion different from the operation described with reference toFIG. 5in the first embodiment will be described.

Operations in a period t21and a period t22are the same as those in the period t1and the period t2. In a period t23, the vertical output line switching pulse ϕSELCa becomes “L” and the vertical output line switching pulse ϕSELCb becomes “H”, so that the clamp capacitor24ais disconnected from the differential amplifier25, and the clamp capacitor24bis connected instead. At this time, the signal readout circuit20reads out the reset signal from the vertical output line21b.The clamp pulse ϕC0R is “H”, and the input terminal and the output terminal of the differential amplifier25are reset to the reference voltage VC0R. Thereafter, when the clamp pulse ϕC0R becomes “L”, the clamp capacitor24bclamps (holds) the reset signal of the (n+1)-th row to the reference voltage VC0R (operation B(n+1)).

Further, in the same period t23, the transfer pulses ϕTXA(n) and ϕTXB(n) simultaneously becomes “H”, and charge accumulated in the PDs11aand PDs11bin the n-th row are simultaneously transferred to the FDs13. Thereafter, the transfer pulses ϕTXA(n) and ϕTXB(n) simultaneously becomes “L”, and each of the unit pixels10in the n-th row outputs the transferred signal A+B to the vertical output line21a.The transferred signal A+B is reflected on the vertical output line21aover the settling time (operation G(n)).

The operation in the period t24is same as that in the period t4.

Then, in the period t25, the clamp pulse ϕC0R becomes “L” and the vertical output line switching pulse ϕSELCa becomes “H”, so that the clamp capacitor24ais connected to the differential amplifier25. By this operation, the signal readout circuit20reads out the transferred signal A+B of the nth row from the settled vertical output line21a.The differential amplifier25performs signal amplification according to the signal gain determined by the capacitance ratio of the clamp capacitor24and the gain capacitor26, and outputs the result to the AD conversion circuit28. Strictly speaking, since the reset signal is clamped to the reference voltage VC0R by the clamp capacitor24, the difference between the reset signal and the transferred signal A+B is amplified. The AD conversion circuit28converts the signal input from the differential amplifier25into a digital signal and outputs it to the outside of the image sensor1(operation H(n)).

Further, in the same period t25, the transfer pulse ϕTXA(n+1) and the transfer pulse ϕTXB(n+1) simultaneously become “H”, and the charge accumulated in the PDs11aand PDs11bin the (n+1)-th row is simultaneously transferred to the FDs13. Thereafter, the transfer pulse ϕTXA(n+1) and the transfer pulse ϕTXB(n+1) becomes “L”, and each of the unit pixels10in the (n+1)-th row outputs the transferred signal A+B to the vertical output line21b.The transferred signal A+B is reflected on the vertical output line21bover the settling time (operation G(n+1)).

The operations in the periods t26and t27are same as those the period t10and t11.

In the conventional technique, the operations A, B, G and H are repeated sequentially for each row without performing operations in parallel between the adjacent rows. Here, let periods required for reading signals of two rows with the operations according to the second embodiment and with the operations of the conventional technique be compared. With the operations of the conventional technique, a period for performing the operations A, B, G and H for the n-th row and the (n+1)-th row, namely, a period for performing8processes, is needed. By contrast, with the operations of the second embodiment, a period for performing the operations A, B, G and H for the n-th row and the operation H for the (n+1)-th row, namely, a period for performing the total of 5 operations, is needed. Consequently, it is possible to increase the speed by a period corresponding to 3 operations. Assuming that the operations A, B, G and H respectively take the same period, reading can be completed in about 63% of a period of the operations performed using the conventional technique.

Next, with reference toFIG. 8, the second mode of reading out the A image and the A+B image from a part of rows of the pixel array100, and reading out the A+B image from the other rows will be explained.

FIG. 8shows an example of readout control in the second mode. In pixel array100, an area701, indicated as the hatched portion is read by the first readout operation and the area702indicated as the white portion is read by the second readout operation.

By performing the first readout operation that takes a longer readout period than the second readout operation for a part of rows, it is possible to further reduce a readout period for reading out signals from one frame.

On the other hand, in the case of performing operation in which the readout time is different for each region, if a subject moving at high speed is captured with a rolling shutter in addition to the conventionally known rolling distortion phenomenon, another distortion between regions caused by different readout periods (referred to as “second rolling distortion phenomenon”, hereinafter) occurs.

Here the effect of speed up by the first readout operation and the second readout operation with respect to the conventional drive will be compared. Assuming that the operations A to H are executed in the same period respectively, in the conventional driving method,12operations are needed for reading out the transferred signal A for the A image and the transferred signal A+B for the A+B image from two rows. By contrast, in the first readout operation, reading can be completed in about 58% of a perod of the operations performed using the conventional technique. Further, in the conventional driving method, 8 operations are needed for reading out the transferred signal A+B for the A+B image from two rows. By contrast, in the second readout operation, reading can be completed in about 63% of a period of the operations performed using the conventional technique. That is, the effect of speeding up is greater in the first readout operation than in the second readout operation. This is because the time for operating in parallel is longer in the first readout operation because the signal for focus detection needs to be read out.

This means that the difference between the readout periods in the first readout operation and in the second readout operation is reduced, and the second rolling distortion phenomenon can be reduced.

In addition, the second mode may be used only in the case of shooting conditions in which rolling distortion phenomenon and second rolling distortion phenomenon do not occur (for example, shooting operation using a mechanical shutter). Then, operation method may be switched according to image shooting conditions such as driving in first mode when performing rolling drive for moving images and the like.

For the sake of simplicity, the above-described effects of the speeding up are explained in a case where each operation is performed in the same period, however, the period of each actual operation is appropriately determined according to the design of the image sensor. However, even when the period of each operation is appropriately determined according to the design, it is still possible to perform operations in parallel, and the effects of the speeding up can be sufficiently expected.

In addition, if the difference in the readout period with respect to the first readout operation can be reduced by using the conventional readout operation which requires 8 operations for reading only the transferred signals A+B from two rows by setting the appropriate operation period, the readout operation for reading only the transferred signal A+B may be performed using the conventional readout operation. By operating in this way, the time required for readout becomes longer as compared with the case of performing the second readout operation, but the second rolling distortion phenomenon can be reduced.

Next, a third embodiment of the present invention will be described. In the third embodiment, an example of an image capturing apparatus equipped with the image sensor1described in the first or second embodiment will be described with reference toFIG. 9.FIG. 9is a block diagram showing a schematic configuration of the image capturing apparatus according to the third embodiment.

InFIG. 9, a lens unit801forms an optical image of a subject on the image sensor1. Further, zoom control, focus control, aperture control and so forth are performed by a lens driving device802.

A mechanical shutter803controls exposure and light shielding of the image sensor1, and is controlled by a shutter driving device804. An image signal processing circuit806performs various corrections and data compression, calculation for focus detection, and so forth, on the image signal and focus detection signal output from the image sensor1. A shooting mode/timing generation unit807outputs various timing signals, such as a switching signal for switching between the first mode and the second mode or a signal for performing the first readout operation and the second readout operation, to the image sensor1and the image signal processing circuit806.

A memory unit808functions as a memory for temporarily storing image data, and an overall control arithmetic unit809is a circuit that performs various arithmetic operations and control of the entire image capturing apparatus. A recording medium control I/F unit810is an interface for recording or reading on a recording medium, a recording medium811is a removable semiconductor memory for recording or reading out image data, and a display unit812is a device for displaying various information and captured images.

Next, the operation of the image capturing apparatus having the above-described configuration at the time of photographing will be described. When the main power supply is turned on, the power supply to the control system is turned on, and then the power supply to a circuit of the image pickup system such as the image signal processing circuit806is turned on. Thereafter, when a release button (not shown) is pressed, an image shooting operation is started.

Upon completion of the image shooting operation, the image signal output from the image sensor1is subjected to image processing by the image signal processing circuit806, and written into the memory unit808according to an instruction from the overall control arithmetic unit809. The data written in the memory unit808is recorded on the removable recording medium811such as a semiconductor memory through the recording medium control I/F unit810under the control of the overall control arithmetic unit809. Further, the image may be processed by inputting directly to a computer or the like through an external I/F unit (not shown).

This application claims the benefit of Japanese Patent Application No. 2017-030247, filed on Feb. 21, 2017 which is hereby incorporated by reference herein in its entirety.