Data access apparatus and data access method

A data access apparatus includes: a flash memory controller; a mirror means; and a flash memory including at least one data region and at least one mirror region. The mirror means copies data to form mirror data to the mirror region when the flash controller writes the data into the data region. The flash memory controller reads the mirror data to replace the data if the flash memory controller determines that the data include error(s) while the data are being read.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a data access apparatus, and more particularly, to a data access apparatus utilizing a mirror mechanism for increasing data access speed and ensuring data correctness.

2. Description of the Prior Art

Conventionally, data stored in a storage apparatus are protected by error correction codes (ECC). For example, data stored in a storage apparatus can be corrected by a corresponding ECC when the data are found to contain errors. However, the ECC utilized for error-correction has some limitations. For example, the ECC cannot be used for correcting errors included in data when the number of errors in the data is larger than a specific value (e.g. N bits). In many modern electronic devices, conventional hard disks are replaced by storage devices (e.g. flash memory) with faster access speed, and using the ECC for error correction is time-consuming. ECC is therefore unable to meet the requirements of fast access in modern electronic devices.

SUMMARY OF THE INVENTION

Therefore, one of the objectives of the present invention is to provide a data access apparatus, to increase data access speed and provide improved data correctness.

According to one embodiment of the present invention, a data access apparatus is disclosed. The data access apparatus includes: a flash memory controller; a mirror means; and a flash memory including at least one data region and at least one mirror region. The mirror means copies data to form mirror data to the mirror region when the flash controller writes the data into the data region. The flash memory controller reads the mirror data to replace the data if the flash memory controller determines that the data include error(s) while the data are being read.

According to another embodiment of the present invention, a data access apparatus is disclosed. The data access apparatus includes: a flash memory controller; a mirror means; a first flash memory including at least one data region; and a second flash memory including at least one mirror region for use by the first flash memory. The mirror means copies data to form mirror data to the mirror region when the flash controller writes the data into the data region. The flash memory controller reads the mirror data to replace the data if the flash memory controller determines that the data include error(s) while the data are being read.

According to yet another embodiment of the present invention, a data access apparatus is disclosed. The data access apparatus includes: a flash memory controller; a mirror means; a first flash memory; a second flash memory including at least one data region; and a third flash memory including at least one mirror region for use in the second flash memory. The mirror means copies data to form mirror data to the mirror region when the flash controller writes the data into the second flash memory. The flash memory controller reads the mirror data to replace the data if the flash memory controller determines that the data include error(s) while the data are being read.

As a person skilled in the art can readily understand the related data access method after reading the above embodiments, so further description is omitted here for brevity.

The above embodiments perform error-correction operations without utilizing the ECC, so the access speed of the flash memory can be increased and the data can be stored in the mirror region to improve the data correctness, thereby solving the above-mentioned problems.

DETAILED DESCRIPTION

FIG. 1is a diagram illustrating a data access apparatus100according to an exemplary embodiment of the present invention. As shown inFIG. 1, the data access apparatus100includes a data transmission interface101, a buffer103, a flash memory A (105), a flash memory B (107), a flash memory C (109), a flash memory controller A (111), a flash memory controller B (113), a flash memory controller C (115), a mirror means A (117), a mirror means B (119), a mirror means C (121), a processor123and a bus125. When the data access apparatus100wants to write data into the flash memory A, B, C (105,107,109), the processor123receives data (e.g. receives data from a server or a host) via the data transmission interface101and stores the data into the buffer103via the bus125. Then, the flash memory controller A, B, C (111,113,115) copies the data stored in the buffer103and writes the data into the flash memory A, B, C (105,107,109) via the bus125.

The flash memories A-C (105-109) include data regions127-131and mirror regions133-137, respectively. The flash memory controller A, B, C (111,113,115) copies the data stored in the buffer103and writes the data into the data region127,129,131of the flash memory A, B, C (105,107,109). When the flash memory controller A, B, C (111,113,115) writes the data into the data region127,129,131, the mirror means A, B, C (117,119,121) copies the data to form mirror data and stores the mirror data into the mirror region133,135,137, and the flash memory controller A, B, C (111,113,115) determines whether the data are correct according to the ECC corresponding to the data while the data are being read. When the data are not correct, the flash memory controller A, B, C (111,113,115) reads the mirror data corresponding to the data, and determines whether the mirror data are correct according to an ECC corresponding to the mirror data (or the mirror data can be recovered to correct data by the ECC). When the mirror data are correct, the flash memory controller A, B, C (111,113,115) transmits the mirror data, instead of the data, to the host or the server. In detail, the flash memory controller A, B, C (111,113,115) reads the mirror data to replace the data if the number of errors of the data is more than a reparable amount (e.g. larger than the number of error bits that ECC can correct) while the data are being read.

The above-mentioned mirror means A, B, C (117,119,121) can be implemented by software, firmware or hardware. In addition, the flash memory A, B, C (105,107,109) can include a plurality of data regions and a plurality of mirror regions, and the flash memory controller can perform data partitioning and then data mirroring, or perform data mirroring and then data partitioning to process the data to be written into the flash memory.

In detail, the method of performing data partitioning and then data mirroring is that, when the flash memory controller A, B, C (111,113,115) writes data into the flash memory A, B, C (105,107,109), the flash memory controller A, B, C (111,113,115) partitions the data into a plurality of parts and writes the parts into the data region127,129,131, and the mirror means A, B, C (117,119,121) copies the parts of the data and then stores them into the mirror region133,135,137. The method of performing data mirroring and then data partitioning is that, the mirror means A, B, C (117,119,121) copies data to form mirror data, and then the flash memory controller A, B, C (111,113,115) partitions the mirror data into a plurality of parts and stores them in the mirror region133,135,137. No matter whether a single data region and single mirror region or multiple data regions and multiple mirror regions are used, an address table needs to be established during data writing to provide lookup and reference for following data reading. As a person skilled in the art can readily understand the functionality and related operations of the address table, further description is omitted here for brevity.

FIG. 2is a diagram illustrating a data access apparatus200according to an exemplary embodiment of the present invention. The data access apparatus200includes a data transmission interface201, a buffer203, a mirror means205, a flash memory A1controller (207), a flash memory A2controller (209), a flash memory B1controller (211), a flash memory B2controller (213), a flash memory A1(215), a flash memory A2(217), a flash memory B1(219), a flash memory B2(221), a processor223and a bus225. The difference between the data access apparatus200shown inFIG. 2and the data access apparatus100shown inFIG. 1is that the data region and the corresponding mirror region of the data access apparatus100are implemented in the same flash memory, but the data region and the corresponding mirror region of the data access apparatus200are implemented in different flash memories.

For example, a data region216of the flash memory A1(215) is implemented in the flash memory A1(215), but a mirror region218of the flash memory A1(215) is implemented in the flash memory A2(217). Similarly, a data region220of the flash memory B1(219) is implemented in the flash memory B1(219), and a mirror region222of the flash memory B1(219) is implemented in the flash memory B2(221). The storage spaces of the flash memory A2(217) and the flash memory B2(221) can be fully or partial occupied by the mirror region218of the flash memory A1(215) and the mirror region222of the flash memory B1(219), respectively. That is, the size of the mirror region can be part of the available space of the flash memory or equal to the whole available space of the flash memory.

Please note that the components, number of components, and the structure of the above-mentioned data access apparatus100,200are merely for illustrative purposes, and should not be considered as limitations to the scope of the present invention. For example, each of the flash memories in the data access apparatus100,200cooperates with a flash memory controller, but the different flash memories, in fact, can also share the same flash memory controller. Moreover, each of the flash memories in the data access apparatus100cooperates with a mirror means, and all of the flash memories in the data access apparatus200cooperate with only one mirror means; however, the arrangements of the data access apparatuses100,200are merely examples for illustration, and should not be considered as limitations to the scope of the present invention.

FIG. 3is a diagram illustrating a data access apparatus300according to an exemplary embodiment of the present invention. The data access apparatus300includes a data transmission interface301, a buffer303, a mirror means305, a flash memory D controller (307), a flash memory E controller (309), a flash memory F controller (311), a flash memory D (315), a flash memory E (317), a flash memory F (319), a processor323and a bus325. In this embodiment, the flash memory D (315) is a higher-quality flash memory, such as a single level cell (SLC) flash memory, which has lower access error probability. The flash memory E (317) is a poorer-quality flash memory, such as a multi level cell (MLC) flash memory or a downgrade memory, which has higher access error probability.

In this embodiment, the mirror means305selectively performs a mirror process upon the data to be stored into the data access apparatus300. For example, when a host (not shown inFIG. 3) wants to store data d into the data access apparatus300, the processor323determines that the data d should be stored in the flash memory D (315) according to a logic address LAdcorresponding to the data d, and the mirror means305does not perform a mirror process upon the data d because the flash memory D (315) is a higher-quality flash memory with lower access error probability. When the host wants to store data e into the data access apparatus300, the processor323determines that the data e should be stored in a data region316of the flash memory E (317) according to a logic address LAecorresponding to the data e, and the mirror means305performs a mirror process upon the data e because the flash memory E (317) is a poorer-quality flash memory with higher access error probability. The mirror means305will copy the data e to form mirror data e′ and store the mirror data e′ into a mirror region318of the flash memory F (319).

Please note that the data e and the mirror data e′ can be stored in the corresponding physical addresses of the flash memory E (317) and the flash memory F (319), respectively, in an embodiment of the present invention. For example, the data e are stored in a physical address 0x0001 of the flash memory E (317), and the mirror data e′ are stored in a physical address 0x0001 of the flash memory F (319). Thus, when the data stored in the physical address 0x0001 of the flash memory E (317) have a read error, the flash memory E controller (309) reports the read error to the processor323, and then the processor323can directly control the flash memory F controller (311) to read the mirror data e′ stored in the physical address 0x0001 of the F flash memory319without looking up the physical address of the mirror data e′. In this way, the processing speed can be improved. However, this embodiment is not a limitation of the present invention. The physical addresses of the data e and the mirror data e′ can also be stored in a look-up table, and the physical address of the mirror data e′ (physical address of the data e) can be found through the look-up table and the physical address of the data e (physical address of the mirror data e′).

In another embodiment, when a host wants to store data d into the data access apparatus300, the processor323determines that the data d should be stored in the flash memory D (315) according to a logic address LAdcorresponding to the data d. The flash memory D controller (307) determines that the data d should be stored in a physical address PAdof the flash memory D (315) according to the logic address LAd. The flash memory D controller (307) determines that the physical address PAdis at a physical storage unit with higher access error probability. For example, the physical storage unit (e.g., a block, a page, etc) had at least a recoverable access error (ECC error) during previous accessing operation. The erroneous bits of the recoverable ECC error are approximated to an upper-bound of the ECC correction capability (or exceed a threshold value). By way of example, the upper-bound of the ECC correction capability is 8 bits, and an access error with 6 erroneous bits has occurred in the storage unit in the past. In order to prevent the non-recoverable ECC errors from occurring in the storage unit, the flash memory D controller (307) reports this situation to the processor323, and then the processor323controls the mirror means305to copy data d to form mirror data d′ and controls the flash memory F controller (311) to store the mirror data d′ into the mirror region318of the F flash memory319. The processor323can establish a look-up table for defining the relations of the physical addresses of the data d and the mirror data d′. The data mirror operation is similar to the above-mentioned embodiment, so further description is omitted here for brevity.

As a person skilled in the art can readily understand the related data access method after reading the above embodiments, further description is omitted here for brevity.

Due to the data processing as described in the above embodiments, mirror data can persevere in the mirror region to improve the data correctness, thereby solving the problems associated with the prior art.