Commanded device states for a memory system

Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

FIELD OF TECHNOLOGY

The following relates to one or more systems for memory, including commanded device states for a memory system.

BACKGROUND

Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any one of which may be stored by the memory cell. To access information stored by a memory device, a component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component may write (e.g., program, set, assign) one or more memory cells within the memory device to corresponding states.

DETAILED DESCRIPTION

A memory system may be associated with various resources that support operations of the memory system, such as processing resources, memory resources, power resources, resources that support parallel operations, or resources that support error control operations, among other examples. In some examples, a memory system may be configured with a static allocation of such resources to support the performance criteria of a particular design, such as a throughput criteria, a latency criteria, an error robustness criteria, or a power consumption criteria. However, a memory system may be coupled with a host system that is associated with one or more performance criteria that change over time, such as performance criteria that depend on application being supported by the host system or on an operating state of the host system. A host system may be aware of changes to such operating conditions, but may lack a capability to indicate changes to performance criteria to be supported by a memory system. Accordingly, an allocation of resources of the memory system may not be adaptable to changing operating conditions of the host system.

In accordance with examples as disclosed herein, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., a respective feature set) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands or requests for a memory system to enter a desired device state of the memory system. Accordingly, the described techniques support an adaptable allocation of resources of a memory system that is responsive to parameters of operating the host system, which provide an adaptable balance of throughput, latency, error control, degradation, power consumption, among other performance characteristics, during different operating conditions of a host system over time.

Features of the disclosure are initially described in the context of systems and devices with reference toFIG.1. Features of the disclosure are described in the context of a process flow with reference toFIG.2. These and other features of the disclosure are further illustrated by and described in the context of block diagrams and a flowchart that relate to commanded device states for a memory system with reference toFIGS.3-6.

FIG.1illustrates an example of a system100that supports commanded device states for a memory system in accordance with examples as disclosed herein. The system100includes a host system105coupled with a memory system110.

The memory system controller115may also include a local memory120. In some cases, the local memory120may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) executable by the memory system controller115to perform functions ascribed herein to the memory system controller115. In some cases, the local memory120may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller115for internal storage or calculations, for example, related to the functions ascribed herein to the memory system controller115. Additionally, or alternatively, the local memory120may serve as a cache for the memory system controller115. For example, data may be stored in the local memory120if read from or written to a memory device130, and the data may be available within the local memory120for subsequent retrieval for or manipulation (e.g., updating) by the host system105(e.g., with reduced latency relative to a memory device130) in accordance with a cache policy.

In some cases, planes165may refer to groups of blocks170, and in some cases, concurrent operations may take place within different planes165. For example, concurrent operations may be performed on memory cells within different blocks170so long as the different blocks170are in different planes165. In some cases, an individual block170may be referred to as a physical block, and a virtual block180may refer to a group of blocks170within which concurrent operations may occur. For example, concurrent operations may be performed on blocks170-a,170-b,170-c, and170-dthat are within planes165-a,165-b,165-c, and165-d, respectively, and blocks170-a,170-b,170-c, and170-dmay be collectively referred to as a virtual block180. In some cases, a virtual block may include blocks170from different memory devices130(e.g., including blocks in one or more planes of memory device130-aand memory device130-b). In some cases, the blocks170within a virtual block may have the same block address within their respective planes165(e.g., block170-amay be “block 0” of plane165-a, block170-bmay be “block 0” of plane165-b, and so on). In some cases, performing concurrent operations in different planes165may be subject to one or more restrictions, such as concurrent operations being performed on memory cells within different pages175that have the same page address within their respective planes165(e.g., related to command decoding, page address decoding circuitry, or other circuitry being shared across planes165).

In some cases, to update some data within a block170while retaining other data within the block170, the memory device130may copy the data to be retained to a new block170and write the updated data to one or more remaining pages of the new block170. The memory device130(e.g., the local controller135) or the memory system controller115may mark or otherwise designate the data that remains in the old block170as invalid or obsolete and may update a logical-to-physical (L2P) mapping table to associate the logical address (e.g., LBA) for the data with the new, valid block170rather than the old, invalid block170. In some cases, such copying and remapping may be performed instead of erasing and rewriting the entire old block170due to latency or wearout considerations, for example. In some cases, one or more copies of an L2P mapping table may be stored within the memory cells of the memory device130(e.g., within one or more blocks170or planes165) for use (e.g., reference and updating) by the local controller135or memory system controller115.

In some cases, L2P mapping tables may be maintained and data may be marked as valid or invalid at the page level of granularity, and a page175may contain valid data, invalid data, or no data. Invalid data may be data that is outdated due to a more recent or updated version of the data being stored in a different page175of the memory device130. Invalid data may have been previously programmed to the invalid page175but may no longer be associated with a valid logical address, such as a logical address referenced by the host system105. Valid data may be the most recent version of such data being stored on the memory device130. A page175that includes no data may be a page175that has never been written to or that has been erased.

In some cases, a memory system controller115or a local controller135may perform operations (e.g., as part of one or more media management algorithms) for a memory device130, such as wear leveling, background refresh, garbage collection, scrub, block scans, health monitoring, or others, or any combination thereof. For example, within a memory device130, a block170may have some pages175containing valid data and some pages175containing invalid data. To avoid waiting for all of the pages175in the block170to have invalid data in order to erase and reuse the block170, an algorithm referred to as “garbage collection” may be invoked to allow the block170to be erased and released as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting a block170that contains valid and invalid data, selecting pages175in the block that contain valid data, copying the valid data from the selected pages175to new locations (e.g., free pages175in another block170), marking the data in the previously selected pages175as invalid, and erasing the selected block170. As a result, the quantity of blocks170that have been erased may be increased such that more blocks170are available to store subsequent data (e.g., data subsequently received from the host system105).

The system100may include any quantity of non-transitory computer readable media that support commanded device states for a memory system. For example, the host system105, the memory system controller115, or a memory device130(e.g., a local controller135) may include or otherwise may access one or more non-transitory computer readable media storing instructions (e.g., firmware) for performing the functions ascribed herein to the host system105, memory system controller115, or memory device130. For example, such instructions, if executed by the host system105(e.g., by the host system controller106), by the memory system controller115, or by a memory device130(e.g., by a local controller135), may cause the host system105, memory system controller115, or memory device130to perform one or more associated functions as described herein.

The memory system110may be associated with various resources that support operations of the memory system110, such as processing resources (e.g., resources of a memory system controller115, resources of one or more local controllers135), memory resources (e.g., resources of local memory120, resources of one or more memory devices130), power resources, resources that support parallel operations, or resources that support error control operations, among other examples. In some examples, the memory system110may be configured with a static allocation of such resources to support the performance criteria, such as a throughput criteria, a latency criteria, an error robustness criteria, or a power consumption criteria for a particular design. However, the memory system110may be coupled with a host system105that is associated with one or more performance criteria that change over time, such as performance criteria that depend on application being supported by the host system105or on an operating state of the host system105. The host system105(e.g., a host system controller106) may be aware of changes to such operating conditions, but may lack a capability to indicate changes to performance criteria to be supported by the memory system110. Accordingly, an allocation of resources of the memory system110may not be adaptable to changing operating conditions of the host system105.

In accordance with examples as disclosed herein, the memory system110may be configured with different device states that are each associated with a respective allocation of resources (e.g., a respective feature set) for operations of the memory system110. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system110, which may support different tradeoffs between performance characteristics of the memory system110. The host system105(e.g., a host system controller106) may be configured to evaluate various parameters of operating the host system105, and to transmit commands for the memory system110to enter a desired device state of the memory system110. Accordingly, the described techniques support an adaptable allocation of resources of the memory system110(e.g., by the memory system controller115) that is responsive to parameters of operating the host system105, which provide an adaptable balance of throughput, latency, error control, degradation, power consumption, among other performance characteristics, during different operating conditions of the host system105over time.

The system100may include any quantity of non-transitory computer readable media that support commanded device states for a memory system. For example, the host system105(e.g., a host system controller106), the memory system110(e.g., a memory system controller115), or a memory device130(e.g., a local controller135) may include or otherwise may access one or more non-transitory computer readable media storing instructions (e.g., firmware, logic, code) for performing the functions ascribed herein to the host system105, the memory system110, or a memory device130. For example, such instructions, if executed by the host system105(e.g., by a host system controller106), by the memory system110(e.g., by a memory system controller115), or by a memory device130(e.g., by a local controller135), may cause the host system105, the memory system110, or the memory device130to perform associated functions as described herein.

FIG.2illustrates an example of a process flow200and related signaling that support commanded device states for a memory system in accordance with examples as disclosed herein. Operations of the process flow200may be performed by one or more components of a host system105-a(e.g., a host system controller106of the host system105-a) and a memory system110-a(e.g., a memory system controller115of the memory system110-a, a local controller135of the memory system110-a, or a combination thereof) of a system100-a, which may be examples of the respective components described with reference toFIG.1. In some examples, the memory system110-amay be an example of an MNAND system or other managed memory system, which may include operations of one or more memory devices130of the memory system110-athat are managed by a memory system controller115of the memory system110-a.

At205, the process flow200may include evaluating operations of the host system105-a. For example, the host system105-amay determine one or more parameters of operating the host system105-a, such as a throughput of information (e.g., read information, write information, or any combination thereof exchanged between the host system105-aand the memory system110-a), a latency tolerance (e.g., a target latency, an allowable latency, whether latency is relevant to a given operating condition), an error tolerance (e.g., whether data errors may be tolerated, a degree of error control expected from the memory system), a power condition, among other parameters associated with operating the host system105-a.

In some examples, the evaluation of host system operations at205may involve measurements performed by the host system105-a, such as a measurement of throughput (e.g., a commanded throughput associated with read commands or write commands, a status of an access command buffer), a measurement of power consumption (e.g., a measurement of current at a power supply voltage), a measurement of power availability or identification of a power source (e.g., whether the host system105-ais operating on battery power or wired power, a measurement of a battery charge state), among other measurements. In some examples, such a determination may include an estimate or inference of parameters of operating the host system105-a, such as an expected throughput, a desire to maximize throughput or minimize latency, a tolerance of access errors (e.g., an ability to support operations with a non-zero rate or write errors or read errors, such as content streaming or caching of transient information), or a tolerance of relatively low throughput or high latency that would support operating the memory system in a lower-performance state, among other parameters associated with operating the host system105-a.

In various examples, the evaluation of host system operations at205may include a determination of parameters as an aggregate characterization of operations of the host system105-a, or a determination of parameters for each of a set of one or more applications being supported by the host system105-a(e.g., in accordance with determining one or more parameters of an application associated with operating the host system105-a), or various combinations thereof. For example, the host system105-amay identify support of an active application associated with relatively high throughput criteria, or relatively low latency tolerance criteria, or both. In some examples, the host system105-amay prioritize evaluated parameters for certain applications (e.g., prioritizing an ability to satisfy operating criteria, such as throughput, latency, or error robustness, for high-priority applications), or the host system105-amay evaluate parameters of operating the host system105-afor meeting or exceeding a minimum operating criteria for one or more (e.g., all) of the applications being supported by the host system105-a(e.g., to emphasize performance if relatively resource-intensive applications are being supported, to deemphasize performance if relatively few or relatively low-demand applications are being supported).

In some examples, an evaluation at205may include identifying an operating mode of the host system105-a. For example, the system100-amay be in an idle mode, in a maintenance mode, or be otherwise inactive, such as circumstances in which the system100-ais a phone that is being charged (e.g., without user interaction or active applications), or in which the system100-ais a vehicle in a parked or idle state (e.g., without being driven), among other examples. In some such examples, the corresponding host system105-amay determine that a throughput parameter is low, or that a latency tolerance parameter is high (e.g., corresponding to a tolerance for relatively slower operations). Additionally, or alternatively, the system100-amay be in a power conservation mode, such as circumstances in which the system100-ais a phone, a vehicle, or another device operating with a battery having a charge state that is at or below some threshold (e.g., below 15% charge capacity). In some such examples, the corresponding host system105-amay determine that a power condition parameter of operating the host system105-ais low. In some other examples, operations of the system100-amay involve high data rates to be written at high frequencies such as in high user interaction applications (e.g., gaming) or while performing a benchmark test (e.g., of the system100-a, of the memory system110-a). In such examples, the host system105-amay determine parameters associated with a high-performance mode. For example, the host system105-amay determine that an information throughput criteria is high, that a latency tolerance criteria is low, or that an error tolerance criteria is high, among other parameters of the host system105-a.

At210, the process flow200may include determining a target state (e.g., for the memory system110-a), which may be based on one or more of the evaluations of host system operations at205. Such a determination may include a selection (e.g., by the host system105-a) from a plurality of device states supported by the memory system110-a, where each device state may be associated with a respective allocation of resources of the memory system110-afor prioritizing different performance criteria. For example, a relatively high-performance state of the memory system110-amay be selected to support some applications of the host system105-a(e.g., a user using a mobile phone, a car driving with an infotainment system turned on, a computer supporting a gaming application), whereas other applications may be associated with other (e.g., relatively lower-performance) criteria. In an illustrative example, for a mobile phone or other application with a display turned off, the host system105-amay select a state of the memory system110-athat corresponds to reduced power consumption even with less performance (e.g., lower throughput, higher latency). In another illustrative example, for a vehicle infotainment system that is operating in a vehicle with an engine turned off or otherwise not recharging batteries, the host system105-amay select a relatively lower-performance state in which the memory system110-acan consume less power. Accordingly, based on the activity of the host system105-a(e.g., a command flow, an operating mode, evaluated parameters of operating the host system105-a), the host system105-amay determine (e.g., define, select), through an appropriate algorithm, a desired state for the memory system110-a, which may correspond to a desired allocation of resources of the memory system110-afor trading off various performance criteria.

In some cases, the host system105-amay select a “Balanced” state (e.g., a generic state, an “all-purpose” state) as the target state for the memory system110-a. In various examples, the Balanced state may be a default state of the memory system110-a, or the host system105-amay select the Balanced state to support relatively balanced operations of the system100-a. In some examples, while configured in the Balanced state, among other states, the memory system110-amay operate without making an implicit decision about the operating mode.

In some cases, the host system105-amay select a “Performance” state as the target state for the memory system110-a. In the Performance state, resources of the memory system110-amay be allocated in a manner that prioritizes relatively high throughput and relatively low latency (e.g., to minimize or otherwise reduce read operation latency or write operation latency), or to maximize or otherwise increase operation throughput, which may be accompanied by relatively higher power consumption, relatively lower available storage capacity, or relatively higher degradation, among other tradeoffs. In some examples, the Performance state may be selected if the host system105-ais running an application that requires relatively high (e.g., maximum) performance, such as a benchmark application or a gaming application.

In some cases, the host system105-amay select a “Battery” state as the target state for the memory system110-a. In the Battery state, resources of the memory system110-amay be allocated in a manner that prioritizes relatively low power consumption, or relatively low peak current draw, which may be accompanied by relatively lower throughput, or relatively higher latency, among other tradeoffs. In some examples, the Battery state may be selected if the host system105-adetermines that the system100-ais operating with a low battery level or otherwise reduced power supply. For example, if the system100-ais powered by a battery (e.g., a mobile phone, a battery-powered vehicle) the Battery state may be selected if the battery reaches or falls below a threshold (e.g., 15% of capacity). Additionally, or alternatively, the Battery state may be selected if the system100-ais operating using battery power rather than wired (e.g., plugged) power.

In some cases, the host system105-amay select an “Endurance” state as the target state for the memory system110-a. In the Endurance state, resources of the memory system110-amay be allocated in a manner that prioritizes relatively few access operations on memory cells of the memory system110-a(e.g., relatively few access operations on a memory device130that experiences memory cell degradation), relatively benign access operations, such (e.g., using trim parameters of one or more memory devices130that are associated with relatively low-magnitude access voltages or access currents), or an emphasis on wear-leveling across one or more memory devices130. In some examples, the Endurance state may be selected if the host system105-aidentifies an inactive mode (e.g., a phone operating in nightly mode) that supports the memory system110-aoperating in a manner that prioritizes endurance, which be accompanied by relatively lower throughput, relatively higher latency, or relatively lower available capacity, among other tradeoffs.

In some cases, the host system105-amay select a “Background” state as the target state for the memory system110-a. In the Background state, resources of the memory system110-amay be allocated in a manner that supports relatively greater availability for memory management operations, such as garbage collection, wear leveling, refresh, folding, and others, which may be accompanied by relatively lower throughput, relatively higher latency, or relatively higher power consumption, among other tradeoffs. In some examples, the Background state may be associated with the memory system110-asupporting some threshold (e.g., minimum) set of performance criteria. The Background state may be selected if the host system105-adetermines that the system100-ais operating with activity that is at or below some threshold (e.g., a low level activity), such that the host system105-acan indicate that the memory system110-amay prioritize internal operations (e.g., indicating an idle time or low-activity time). For example, the Background state may be selected if the system100-ais not being actively used (e.g., is inactive) or actively supporting an application, or is operating in a maintenance mode, such as when a phone is in a wall-charge mode or when a vehicle is parked without a driver being present, among other examples.

In some cases, the host system105-amay select an “Automatic” state as the target state for the memory system110-a. In the Automatic state, the host system105-amay leave resource allocation decisions to the memory system110-a, which may involve the memory system110-aselecting a device state (e.g., the Balanced state, the Performance state, the Battery state, the Endurance state, the Background state) based on characteristics of the memory system110-a. In other words, the memory system110-amay infer performance criteria that are to be supported by the memory system110-a, and may select a device state accordingly (e.g., based on heuristic algorithms internal to the memory system110-a, without a specific command or request of a device state from the host system105-a).

Thus, in accordance with these and other examples, at210, the host system105-amay determine a device state for the memory system110-a, or may signal a permissive state in which the memory system110-aitself may select a device state, which may support various techniques for dynamic allocations of resources at the memory system110-a.

At215, the process flow200may include a transmission of a state command. For example, the host system105-amay transmit a command for the memory system110-ato enter the target state determined at210(e.g., a device state of the memory system110-a, a permissive state in which the memory system110-amay determine a device state or allocation of resources). In some other examples, the signaling of215may be associated with a request from the host system105-afor the memory system110-ato enter a desired device state, rather than a command, which may be accepted or denied by the memory system110-a.

In some cases, to support the signaling of the command of215, the memory system110-amay implement a register associated with the device states of the memory system110-a, such as a descriptor register. For example, to signal the command of215, the host system105-amay transmit a command to the memory system110-ato write an indication of the device state in the register of the memory system110-a. Table 1 illustrates an example of such a register, where a value of a one byte descriptor (e.g., bCurrDevState) may be associated with a device state of the memory system110-a.

TABLE 1Register Values and Corresponding Device StatesRegister ValueDevice State0 × 0Balanced0 × 1Performance0 × 2Battery0 × 3Endurance0 × 4Background0 × 5Automatic
In the example of system100-a, such a register, or value thereof, may also be used by the memory system110-ato indicate a device state status. For example, the memory system110-amay write a value to such a register to indicate whether the memory system110-ahas entered a commanded device state, or to indicate a device state selected by the memory system (e.g., when commanded or requested to operate in an Automatic state).

At220, the process flow200may include changing a state of the memory system110-a. For example, based on receiving the command of215, the memory system110-amay set one or more parameters of the memory system110-athat correspond to the allocation of resources associated with the commanded device state. In some examples, the memory system110-amay change state based on reading a register value (e.g., a value of a descriptor register, a register value of Table 1) and setting memory operation parameters associated with the register. The setting of parameters at220may be associated with establishing a resource allocation at the memory system110-athat supports the prioritized performance criteria of the device state commanded or requested by the host system105-a.

In some examples, the operations of220may include the memory system110-asetting a quantity of logic levels to be stored in memory cells of the memory system. For example, a relatively lower quantity of logic levels (e.g., two levels, an SLC configuration) may be associated with relatively lower latency (e.g., due to relatively faster read or write operations, due to relatively fewer reference voltages for read operations) or relatively lower memory cell deterioration (e.g., higher endurance, due to relatively lower-magnitude access biasing), among other characteristics associated with relatively fewer logic levels per memory cell. Alternatively, a relatively higher quantity of logic levels (e.g., more than two levels, in a multiple-level cell configuration), may be associated with relatively higher storage capacity (e.g., due to storing more bits per memory cells), or relatively fewer memory management operations (e.g., due to storing information more compactly), among other characteristics associated with relatively greater logic levels per memory cell.

In some examples, the operations of220may include the memory system110-asetting a proportion of volatile memory (e.g., of local memory120, of a memory device130, an SRAM array) for supporting operations of the memory system110-a. For example, enabling (e.g., powering, activating) a relatively higher proportion of volatile memory, such as all of a volatile memory array, may support higher throughput or lower latency (e.g., due to increased caching, due to increased L2P table availability), whereas enabling a relatively lower proportion of volatile memory (e.g., disabling at least a portion of volatile memory, disabling one or more power domains of volatile memory) may be associated with relatively reduced power consumption, among other characteristics associated with enabling different proportions of a volatile memory of the memory system110-a.

In some examples, the operations of220may include the memory system110-asetting a degree of parallelism (e.g., a quantity of data paths operating in concurrently, a quantity of memory devices130or portions thereof operating concurrently). For example, enabling a higher degree of parallelism may be support higher throughput or reduced latency (e.g., due to supporting more access operations in parallel), whereas a relatively lower degree of parallelism may support relatively lower power consumption or relatively higher availability for memory management operations (e.g., garbage collection, wear leveling, refresh), among other characteristics associated with setting different degrees of parallelism.

In some examples, the operations of220may include the memory system110-asetting an error control configuration (e.g., whether error control functions are operational, a quantity bits of error detection, a quantity of bits of error correction, an activation or deactivation of a redundant array of independent NAND (RAIN)). For example, enabling aspects of an error control configuration may be associated with relatively fewer data errors (e.g., due to performing error control operations, due to performing error control operations in accordance with a higher quantity of error bits), whereas disabling aspects of an error control configuration may be associated with higher throughput or reduced latency, among other characteristics associated with different error control configuration settings.

In some examples, the operations of220may include the memory system110-asetting a memory management configuration (e.g., whether memory management functions are operational or inhibited, a rate at which memory management functions are performed). For example, disabling or reducing a rate for memory management operations may be associated with relatively higher throughput or reduced latency, whereas enabling or increasing a rate of memory management operations may be associated with greater available capacity (e.g., due to garbage collection operations), improved endurance performance (e.g., due to wear leveling), or improved data integrity (e.g., due to refresh operations), among other characteristics associated with different memory management configuration settings.

In some examples, the operations of220may include the memory system110-asetting one or more trim parameters (e.g., clock timing or scaling, access operation timing, read or write signal magnitudes, burst configurations). For example, some trim parameter settings may be associated with relatively higher throughput or reduced latency (e.g., due to faster access operation timing) or relatively improved data retention (e.g., due to higher write signal magnitudes), whereas some other trim parameter settings may be associated with relatively higher endurance performance or relatively lower power consumption (e.g., due to relatively lower access signal magnitudes, due to relatively slower access operation timing), among other characteristics associated with different trim parameters.

In some examples, the operations of220may include the memory system110-asetting wear-out thresholds (e.g., parameters for managing endurance of a memory device130, parameters for selecting which portions of a memory device to access). For example, setting relatively high thresholds for wear-out considerations may be associated with relatively high throughput or low latency (e.g., due to increasing a proportion of memory cells available for write operations), whereas setting relatively low thresholds for wear-out considerations may be associated with improved endurance performance (e.g., due to balancing wear across a memory array, due to performing memory management to mitigate degradation), among other characteristics associated with different wear-out thresholds.

Thus, according to these and other examples, the memory system110-amay configure aspects of a resource allocation of the memory system110-a, in response to signaling from the host system105-a, which may support performance characteristics that are adaptable to different operating conditions of the host system105-a.

In some cases, the operations of220may include the memory system110-asetting a combination of parameters to support a resource allocation in accordance with the Balanced state (e.g., normal operation). For example, the Balanced state may be associated with moderate or default settings for parameters such as a quantity of logic levels per cell, a proportion of enabled volatile memory, a degree of parallelism (e.g., operating up to three memory dies in parallel), an error control configuration (e.g., enabling error control operations in a default configuration), a memory management configuration, or trim parameters, or various combinations thereof.

In some cases, the operations of220may include the memory system110-asetting a combination of parameters to support a resource allocation in accordance with the Performance state, in which the memory system110-amay be configured to minimize read or write operation latency and maximize operation throughput. In some examples, such operations may include configuring the memory system110-awith relatively high clock scaling (e.g., overclocking), or relatively fast trim parameters, or any combination thereof. Additionally, or alternatively, such operations may include the memory system110-aallocating all available memory of a local memory120(e.g., a full proportion of an SRAM array) to store L2P tables, which may reduce an exchange of L2P table information between a local memory120and a memory device130. Additionally, or alternatively, such operations may include the memory system110-adisabling or reducing error control functionality (e.g., error correction code (ECC) functionality) or redundancy techniques such as redundant array of independent NAND (RAIN) protection, which may increase the possibility of read errors or write errors, but such errors may be tolerable in the context of supporting higher throughput or reduced latency (e.g., for conditions in which data may be likely to be overwritten, such as during benchmark or streaming application).

Further, for operations in the Performance state, the memory system110-amay additionally, or alternatively, enable writing to SLC buffers rather than multiple-level cell buffers (e.g., reducing a quantity of logic levels associated with a buffer area of a memory device130), or otherwise set at least a portion of a memory device to operate in accordance with relatively fewer logic states per memory cell (e.g., where the memory system110-amay operate proactively in a write-booster configuration). Additionally, or alternatively, the memory system110-amay set a relatively high degree of parallelism (e.g., full parallelism), such as enabling parallel access operations on up to 8 memory dies (e.g., of one or more memory devices130). Additionally, or alternatively, the memory system may set a relatively high wear-out threshold, which may be associated with accessing memory cells having relatively high levels of degradation, to support the increased throughput and reduced latency. In some examples, a memory management configuration in the Performance state may be set such that operations are performed upon request from the host system105-a, but the memory system110-amay not, itself, initiate such operations without such a request. In some cases, the memory system110-amay be configured to program content into the memory devices130in large bursts of data to reduce latency of page programming.

In some cases, the operations of220may include the memory system110-asetting a combination of parameters to support a resource allocation in accordance with the Battery state, in which the memory system110-amay be configured to minimize power consumption or limit power-consuming operations. In some examples, such operations may include setting a relatively low degree of parallelism (e.g., enabling access of a single memory die at a time), or otherwise reducing a rate of access operations (e.g., implementing relatively slower trim parameters), which may avoid relatively high currents. Additionally, or alternatively, such operations may include the memory system110-adisabling at least a portion of a local memory120(e.g., switching off internal power domains of a local memory120, switching off some SRAM banks). Additionally, or alternatively, such operations may include the memory system110-adisabling or reducing a rate of housekeeping operations to a minimum configuration of operations for the system100-ato function.

In some cases, the operations of220may include the memory system110-asetting a combination of parameters to support a resource allocation in accordance with the Endurance state, in which the memory system110-amay be configured to maximize endurance of one or more memory devices130, or memory cells thereof. In various examples, such operations may include prioritizing wear-leveling, reducing memory cell access (e.g., disabling or reducing a rate of at least some memory management operations such as garbage collection), setting relatively low wear-out thresholds (e.g., to prioritize access of memory cells with relatively low degradation), or setting relatively benign trim parameters (e.g., associated with relatively low degradation, relatively low-magnitude cell biasing), among other characteristics. In some examples, while operating in the Endurance state, the memory system110-amay evaluate whether to honor SLC write requests from the host system105-a(e.g., whether to honor a write-boost command or request), which may depend on a wear-out status of an SLC block of a memory device130and a wear-out threshold of the Endurance state. In some cases, performance of the memory system110-a(e.g., related to throughput, latency) may be reduced to support evaluations by a memory system controller115, such as determinations of which memory cells to access for a given operation, or evaluations of utilization patterns (e.g., data written together, garbage data collected together), among other operations to support improved endurance.

In some cases, while operating in the Endurance state, the memory system110-amay be configured to program content into the memory devices130using small peaks of current in order to increase reliability and endurance of the programmed content (e.g., for an application that stores data for a relatively long period. Additionally, or alternatively, the memory system110-amay configure garbage collection to erase older memory blocks or memory blocks otherwise associated with a higher probability of errors. Additionally, or alternatively, the memory system110-amay write similar content to different memory blocks so that the memory blocks may be refreshed at the same time due to similar lifespans.

In some cases, the operations of220may include the memory system110-asetting a combination of parameters to support a resource allocation in accordance with the Background state, in which the memory system110-amay be configured to support some threshold level of performance (e.g., a minimum level of performance) and leverage idle time to perform housekeeping operations. In some examples, such operations may include configuring the memory system110-ato perform memory management operations as soon as idle time is available (e.g., to perform memory management operations that may have been inhibited due to intense user activity or a configuration in the Performance state). Additionally, or alternatively, such operations may include configuring the memory system110-ato perform maintenance tasks (e.g., folding, garbage collection, refresh, wear leveling) more proactively (e.g., in accordance with a lower threshold, performing maintenance tasks even if a threshold of another device state has not been reached).

In some cases, the operations of220may include the memory system110-asetting a combination of parameters to support a resource allocation in accordance with the Automatic state, in which the memory system110-amay be configured to internally determine a resource allocation (e.g., a device state or other resource allocation) based on internal heuristic algorithms. In some examples, such operations may include the memory system110-adetermining, from operations supported by the memory system110-a, to prioritize high throughput and low latency, or to prioritize low power consumption (e.g., in response to an evaluation of a power condition), or to prioritize endurance (e.g., in response to an evaluation of degradation conditions) among other performance criteria, and configure a resource allocation accordingly. In some examples, the memory system110-amay indicate a device state it has selected, which may include writing a register value associated with the selected state that can be read by the host system105-a.

At225, the process flow200may include performing operations of the memory system110-ain accordance with the commanded device state (e.g., in accordance with a selected or commanded allocation of resources of the memory system110-a). For example, the host system105-amay issue commands (e.g., write commands, read commands, memory management commands), to which the memory system110-amay respond by performing operations in accordance with the allocation of resources established at220. Additionally, or alternatively, the memory system110-amay perform internal operations (e.g., memory management operations), among other operations in accordance with such an allocation of resources. In some examples, the operations of225may include the memory system110-atransmitting (e.g., to the host system105-a) an indication that the memory system has entered the device state.

FIG.3shows a block diagram300of a memory system320that supports commanded device states for a memory system in accordance with examples as disclosed herein. The memory system320may be an example of aspects of a memory system as described with reference toFIGS.1and2. The memory system320, or various components thereof, may be an example of means for performing various aspects of commanded device states for a memory system as described herein. For example, the memory system320may include a state command reception component325, a resource configuration component330, a memory operation component335, a device state status transmission component340, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The state command reception component325may be configured as or otherwise support a means for receiving a command to operate in a device state of a plurality of device states of the memory system320, where each device state of the plurality of device states is associated with a respective allocation of resources for operations of the memory system320. The resource configuration component330may be configured as or otherwise support a means for setting one or more parameters of the memory system320corresponding to the respective allocation of resources associated with the device state based at least in part on receiving the command. The memory operation component335may be configured as or otherwise support a means for performing the operations of the memory system320in accordance with the respective allocation of resources associated with the device state based at least in part on setting the one or more parameters.

In some examples, to support setting the one or more parameters of the memory system320, the resource configuration component330may be configured as or otherwise support a means for setting an error control configuration, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system320based at least in part on receiving the command.

In some examples, to support setting the one or more parameters of the memory system320, the resource configuration component330may be configured as or otherwise support a means for setting a trim parameter, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system320based at least in part on receiving the command.

In some examples, to support setting the one or more parameters of the memory system320, the resource configuration component330may be configured as or otherwise support a means for setting a degree of parallelism, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system320based at least in part on receiving the command.

In some examples, to support setting the one or more parameters of the memory system320, the resource configuration component330may be configured as or otherwise support a means for setting a memory management configuration, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system320based at least in part on receiving the command.

In some examples, to support setting the one or more parameters of the memory system320, the resource configuration component330may be configured as or otherwise support a means for setting a wear-out threshold, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system320based at least in part on receiving the command.

In some examples, to support setting the one or more parameters of the memory system320, the resource configuration component330may be configured as or otherwise support a means for setting a quantity of logic levels, corresponding to the respective allocation of resources associated with the device state, for operating memory cells of one or more memory devices of the memory system320based at least in part on receiving the command.

In some examples, to support setting the one or more parameters of the memory system320, the resource configuration component330may be configured as or otherwise support a means for enabling a proportion, corresponding to the respective allocation of resources associated with the device state, of a volatile memory device of the memory system320for supporting operations of the memory system320based at least in part on receiving the command.

In some examples, the device state status transmission component340may be configured as or otherwise support a means for transmitting an indication that the memory system320has entered the device state.

In some examples, to support receiving the command to enter the device state, the state command reception component325may be configured as or otherwise support a means for receiving a command (e.g., from a host system coupled with the memory system320) to write an indication of the device state in a register of the memory system320.

FIG.4shows a block diagram400of a host system420that supports commanded device states for a memory system in accordance with examples as disclosed herein. The host system420may be an example of aspects of a host system as described with reference toFIGS.1through2. The host system420, or various components thereof, may be an example of means for performing various aspects of commanded device states for a memory system as described herein. For example, the host system420may include a host operation evaluation component425, a memory device state determination component430, a state command transmission component435, a device state status reception component440, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The host operation evaluation component425may be configured as or otherwise support a means for determining one or more parameters of operating the host system420. The memory device state determination component430may be configured as or otherwise support a means for determining a device state of a plurality of device states of a memory system based at least in part on the one or more parameters of operating the host system420, where each device state of the plurality of device states is associated with a respective allocation of resources for operations of the memory system. The state command transmission component435may be configured as or otherwise support a means for transmitting a command for the memory system to enter the determined device state, where the command is associated with the memory system setting one or more parameters of the memory system corresponding to the respective allocation of resources associated with the determined device state.

In some examples, to support determining the one or more parameters of operating the host system420, the host operation evaluation component425may be configured as or otherwise support a means for determining a throughput of information associated with operating the host system420.

In some examples, to support determining the one or more parameters of operating the host system420, the host operation evaluation component425may be configured as or otherwise support a means for determining a latency tolerance associated with operating the host system420.

In some examples, to support determining the one or more parameters of operating the host system420, the host operation evaluation component425may be configured as or otherwise support a means for determining an error tolerance associated with operating the host system420.

In some examples, to support determining the one or more parameters of operating the host system420, the host operation evaluation component425may be configured as or otherwise support a means for determining a power condition associated with operating the host system420.

In some examples, to support determining the one or more parameters of operating the host system420, the host operation evaluation component425may be configured as or otherwise support a means for determining a parameter of an application associated with operating the host system420.

In some examples, the device state status reception component440may be configured as or otherwise support a means for receiving an indication that the memory system has entered the device state.

In some examples, to support transmitting the command to enter the device state, the state command transmission component435may be configured as or otherwise support a means for transmitting a command to the memory system to write an indication of the device state in a register of the memory system.

FIG.5shows a flowchart illustrating a method500that supports commanded device states for a memory system in accordance with examples as disclosed herein. The operations of method500may be implemented by a memory system or its components as described herein. For example, the operations of method500may be performed by a memory system as described with reference toFIGS.1through3. In some examples, a memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the memory system may perform aspects of the described functions using special-purpose hardware.

At505, the method may include receiving (e.g., at a memory system) a command to operate in a device state of a plurality of device states of the memory system, where each device state of the plurality of device states is associated with a respective allocation of resources for operations of the memory system. The operations of505may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of505may be performed by a state command reception component325as described with reference toFIG.3.

At510, the method may include setting one or more parameters of the memory system corresponding to the respective allocation of resources associated with the device state based at least in part on receiving the command. The operations of510may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of510may be performed by a resource configuration component330as described with reference toFIG.3.

At515, the method may include performing the operations of the memory system in accordance with the respective allocation of resources associated with the device state based at least in part on setting the one or more parameters. The operations of515may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of515may be performed by a memory operation component335as described with reference toFIG.3.

Aspect 1: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving (e.g., at a memory system) a command to operate in a device state of a plurality of device states of the memory system, where each device state of the plurality of device states is associated with a respective allocation of resources for operations of the memory system; setting one or more parameters of the memory system corresponding to the respective allocation of resources associated with the device state based at least in part on receiving the command; and performing the operations of the memory system in accordance with the respective allocation of resources associated with the device state based at least in part on setting the one or more parameters.

Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1 where setting the one or more parameters of the memory system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for setting an error control configuration, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system based at least in part on receiving the command.

Aspect 3: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 2 where setting the one or more parameters of the memory system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for setting a trim parameter, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system based at least in part on receiving the command.

Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 3 where setting the one or more parameters of the memory system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for setting a degree of parallelism, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system based at least in part on receiving the command.

Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 4 where setting the one or more parameters of the memory system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for setting a memory management configuration, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system based at least in part on receiving the command.

Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 5 where setting the one or more parameters of the memory system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for setting a wear-out threshold, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system based at least in part on receiving the command.

Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 6 where setting the one or more parameters of the memory system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for setting a quantity of logic levels, corresponding to the respective allocation of resources associated with the device state, for operating memory cells of one or more memory devices of the memory system based at least in part on receiving the command.

Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 7 where setting the one or more parameters of the memory system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for enabling a proportion, corresponding to the respective allocation of resources associated with the device state, of a volatile memory device of the memory system for supporting operations of the memory system based at least in part on receiving the command.

Aspect 9: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 8, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for transmitting an indication that the memory system has entered the device state.

Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 9 where receiving the command to enter the device state includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving a command, from a host system coupled with the memory system, to write an indication of the device state in a register of the memory system.

FIG.6shows a flowchart illustrating a method600that supports commanded device states for a memory system in accordance with examples as disclosed herein. The operations of method600may be implemented by a host system or its components as described herein. For example, the operations of method600may be performed by a host system as described with reference toFIGS.1,2, and4. In some examples, a host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the host system may perform aspects of the described functions using special-purpose hardware.

At605, the method may include determining (e.g., at a host system) one or more parameters of operating a host system. The operations of605may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of605may be performed by a host operation evaluation component425as described with reference toFIG.4.

At610, the method may include determining (e.g., at the host system) a device state of a plurality of device states of a memory system based at least in part on the one or more parameters of operating the host system, where each device state of the plurality of device states is associated with a respective allocation of resources for operations of the memory system. The operations of610may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of610may be performed by a memory device state determination component430as described with reference toFIG.4.

At615, the method may include transmitting a command for the memory system to enter the determined device state, where the command is associated with the memory system setting one or more parameters of the memory system corresponding to the respective allocation of resources associated with the determined device state. The operations of615may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of615may be performed by a state command transmission component435as described with reference toFIG.4.

Aspect 11: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining (e.g., at a host system) one or more parameters of operating a host system; determining (e.g., at the host system) a device state of a plurality of device states of a memory system based at least in part on the one or more parameters of operating the host system, where each device state of the plurality of device states is associated with a respective allocation of resources for operations of the memory system; and transmitting a command for the memory system to enter the determined device state, where the command is associated with the memory system setting one or more parameters of the memory system corresponding to the respective allocation of resources associated with the determined device state.

Aspect 12: The method, apparatus, or non-transitory computer-readable medium of aspect 11 where determining the one or more parameters of operating the host system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining a throughput of information associated with operating the host system.

Aspect 13: The method, apparatus, or non-transitory computer-readable medium of any of aspects 11 through 12 where determining the one or more parameters of operating the host system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining a latency tolerance associated with operating the host system.

Aspect 14: The method, apparatus, or non-transitory computer-readable medium of any of aspects 11 through 13 where determining the one or more parameters of operating the host system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining an error tolerance associated with operating the host system.

Aspect 15: The method, apparatus, or non-transitory computer-readable medium of any of aspects 11 through 14 where determining the one or more parameters of operating the host system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining a power condition associated with operating the host system.

Aspect 16: The method, apparatus, or non-transitory computer-readable medium of any of aspects 11 through 15 where determining the one or more parameters of operating the host system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining a parameter of an application associated with operating the host system.

Aspect 17: The method, apparatus, or non-transitory computer-readable medium of any of aspects 11 through 16, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving an indication that the memory system has entered the device state.

Aspect 18: The method, apparatus, or non-transitory computer-readable medium of any of aspects 11 through 17 where transmitting the command to enter the device state includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for transmitting a command to the memory system to write an indication of the device state in a register of the memory system.

Aspect 19: An apparatus, comprising: one or more memory devices of a memory system; and a controller of the memory system coupled with the one or more memory devices and configured to cause the apparatus to: receive a command to operate in a device state of a plurality of device states of the memory system, wherein each device state of the plurality of device states is associated with a respective allocation of resources for operations of the memory system; set one or more parameters of the memory system corresponding to the respective allocation of resources associated with the device state based at least in part on receiving the command; and perform the operations of the memory system in accordance with the respective allocation of resources associated with the device state based at least in part on setting the one or more parameters.

Aspect 20: The apparatus of aspect 19, wherein, for setting the one or more parameters of the memory system, the controller is configured to cause the apparatus to: set a quantity of logic levels, corresponding to the respective allocation of resources associated with the device state, for operating memory cells of one or more memory devices of the memory system based at least in part on receiving the command.

Aspect 21: The apparatus of any of aspects 19 through 20, wherein, for setting the one or more parameters of the memory system, the controller is configured to cause the apparatus to: enable a proportion, corresponding to the respective allocation of resources associated with the device state, of a volatile memory device of the memory system for supporting operations of the memory system based at least in part on receiving the command.

Aspect 22: The apparatus of any of aspects 19 through 21, wherein, for setting the one or more parameters of the memory system, the controller is configured to cause the apparatus to: set a degree of parallelism, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system based at least in part on receiving the command.

Aspect 23: The apparatus of any of aspects 19 through 22, wherein, for setting the one or more parameters of the memory system, the controller is configured to cause the apparatus to: set an error control configuration, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system based at least in part on receiving the command.

Aspect 24: The apparatus of any of aspects 19 through 23, wherein, for setting the one or more parameters of the memory system, the controller is configured to cause the apparatus to: set a memory management configuration, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system based at least in part on receiving the command.

Aspect 25: The apparatus of any of aspects 19 through 24, wherein, for setting the one or more parameters of the memory system, the controller is configured to cause the apparatus to: set a trim parameter, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system based at least in part on receiving the command.

Aspect 26: The apparatus of any of aspects 19 through 25, wherein, for setting the one or more parameters of the memory system, the controller is configured to cause the apparatus to: set a wear-out threshold, corresponding to the respective allocation of resources associated with the device state, for operating one or more memory devices of the memory system based at least in part on receiving the command.

Aspect 27: The apparatus of any of aspects 19 through 26, wherein the controller is further configured to cause the apparatus to: transmit an indication that the memory system has entered the device state.

Aspect 28: The apparatus of any of aspects 19 through 27, wherein, for receiving the command to enter the device state, the controller is configured to cause the apparatus to: receive a command, from a host system coupled with the memory system, to write an indication of the device state in a register of the memory system.

Aspect 29: An apparatus, comprising: a controller configured to couple with a memory system, wherein the controller is configured to cause the apparatus to: determine one or more parameters of operating the apparatus; determine a device state of a plurality of device states of a memory system based at least in part on the one or more parameters of operating the apparatus, wherein each device state of the plurality of device states is associated with a respective allocation of resources for operations of the memory system; and transmit a command for the memory system to enter the determined device state, wherein the command is associated with the memory system setting one or more parameters of the memory system corresponding to the respective allocation of resources associated with the determined device state.

Aspect 30: The apparatus of aspect 29, wherein, for determining the one or more parameters of operating the apparatus, the controller is configured to cause the apparatus to: determine a throughput of information associated with operating the apparatus.

Aspect 31: The apparatus of any of aspects 29 through 30, wherein, for determining the one or more parameters of operating the apparatus, the controller is configured to cause the apparatus to: determine a latency tolerance associated with operating the apparatus.

Aspect 32: The apparatus of any of aspects 29 through 31, wherein, for determining the one or more parameters of operating the apparatus, the controller is configured to cause the apparatus to: determine an error tolerance associated with operating the apparatus.

Aspect 33: The apparatus of any of aspects 29 through 32, wherein, for determining the one or more parameters of operating the apparatus, the controller is configured to cause the apparatus to: determine a power condition associated with operating the apparatus.

Aspect 34: The apparatus of any of aspects 29 through 33, wherein, for determining the one or more parameters of operating the apparatus, the controller is configured to cause the apparatus to: determine a parameter of an application associated with operating the apparatus.

Aspect 35: The apparatus of any of aspects 29 through 34, wherein the controller is further configured to cause the apparatus to: receive an indication that the memory system has entered the device state.

Aspect 36: The apparatus of any of aspects 29 through 35, wherein, for transmitting the command to enter the device stat, the controller is configured to cause the apparatus to: transmit a command to the memory system to write an indication of the device state in a register of the memory system.