Analog-to-digital converter, low-dropout regulator and comparison control circuit thereof

A comparison control circuit is adapted to analog-to-digital converters and low-dropout regulators. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor set and a logic circuit. The comparator is configured to output a comparison signal according to a first input signal and a second input signal, wherein the comparison signal is a first high voltage potential or a first low voltage potential. The Schmitt trigger is configured to output a trigger signal according to the comparison signal and a voltage potential range, wherein the voltage potential range is in a range from the first low voltage potential to the first high voltage potential. The capacitor set is configured to adjust the second input signal when being controlled. The logic circuit is configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

CROSS-REFERENCE TO RELATED APPLICATION

This non-provisional application claims priority under 35 U.S.C. § 119(a) to Patent Application No. 110130032 filed in Taiwan, R.O.C. on Aug. 13, 2021, the entire contents of which are hereby incorporated by reference.

BACKGROUND

Technical Field

The present application relates to a comparison control circuit, an analog-to-digital converter having the same and a low-dropout regulator having the comparison control circuit.

Related Art

Comparator is a common semiconductor device whose function is to compare the magnitude of the voltages received at the two input terminal and to output a comparison signal. The comparators are widely applied in various types of circuits, such as analog-to-digital converters (ADCs), analog low-dropout regulators (LDOs), and so on. However, the comparator often outputs unclean comparison signal for the reason that being affected by input signal noise, power noise or larger bandwidth, etc., such that the circuit may occur misjudged problem during the operating process, which in turn leads the circuit to output wrong signals.

SUMMARY

In order to solve the aforementioned problem, the inventor proposes a comparison control circuit. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor set and a logic circuit. The comparator has a first input terminal, a second input terminal and a first output terminal. The comparator is configured to output a comparison signal at the first output terminal according to a first input signal received at the first input terminal and a second input signal received at the second input terminal, wherein the comparison signal is a first high voltage potential or a first low voltage potential. The Schmitt trigger has a third input terminal and a second output terminal. The Schmitt trigger is configured to output a trigger signal at the second output terminal according to the comparison signal received at the third input terminal and a voltage potential range, wherein the trigger signal is a second high voltage potential or a second low voltage potential, and the voltage potential range is in a range from the first low voltage potential to the first high voltage potential. The capacitor set is configured to adjust the second input signal when being controlled. The logic circuit is configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

In some embodiments, the comparator is a comparator with single-ended input.

In some embodiments, the first high voltage potential is 1 volt (V), and the first low voltage is 0 volt (V).

In some embodiments, the second high voltage potential is 1 volt (V), and the second low voltage is 0 volt (V).

In some embodiments, the capacitor set comprises a plurality of capacitors from C1to CN, and each of the plurality of capacitors has a first terminal and a second terminal.

In some embodiments, the first terminal of each of the plurality of capacitors is electrically connected to the second input terminal, and the second terminal of each of the plurality of capacitors is electrically connected to a reference voltage source or a ground selectively when being controlled.

According to some embodiment, an analog low-dropout regulator includes an error amplifier, a pass transistor, a voltage divider circuit and the aforementioned comparison control circuit. The error amplifier has a positive input terminal, a negative input terminal and a third output terminal. The error amplifier is configured to output a control voltage at the third output terminal according to a feedback voltage received at the positive input terminal and a stable reference voltage potential received at the negative input terminal. The pass transistor has a gate terminal, a drain terminal and a source terminal. The pass transistor is configured to output an output voltage at the drain terminal according to the control voltage received at the gate terminal. The voltage divider circuit is configured to divide the output voltage and the feedback voltage, such that a value of the feedback voltage is the same as the stable reference voltage potential, thereby a value of the output voltage is the same as the stable reference voltage potential. The aforementioned comparison control circuit is configured to stabilize the output voltage, wherein the second input terminal is electrically connected to the drain terminal.

In some embodiments, the voltage divider circuit comprises a first voltage dividing resistor and a second voltage dividing resistor, wherein a resistance of the first voltage dividing resistor is much smaller than a resistance of the second voltage dividing resistor.

According to some embodiment, an analog-to-digital converter includes the aforementioned comparison control circuit, wherein the first input signal is an analog input signal, the second input signal is a comparison voltage potential, and the logic circuit is further configured to store and output a digital output signal.

In some embodiments, a capacitance of capacitor Ciin the analog-to-digital converter is twice a capacitance of capacitor Ci+1, a capacitance of capacitor CN−1is equal to a capacitance of capacitor CN, and wherein i=1˜N−2.

In some embodiments, a capacitor set of the analog-to-digital converter is a capacitive digital-to-analog converter.

In some embodiments, a logic circuit of the analog-to-digital converter is a successive approximation register (SAR)

To sum up, in some embodiments, the comparison control circuit can be applied in various types of circuits, such that the circuit can avoid the noise problem caused by the input signal or power supply during the operating process, thereby ensuring the circuit that outputs a correct and clean signal.

DETAILED DESCRIPTION

Some embodiments of the present application are illustrated in the drawings. For the sake of clear illustration, many practical details will be illustrated together in the following description, but this is not to limit the scope of claims of the present application.

Please refer toFIG.1.FIG.1illustrates a functional block diagram of a comparison control circuit100according to an embodiment of the present application. The comparison control circuit100includes a comparator110, a Schmitt trigger120, a logic circuit130and a capacitor set140. The comparator110has a first input terminal111, a second input terminal112and a first output terminal113. The Schmitt trigger120has a third input terminal121and a second output terminal122. As shown inFIG.1, the third input terminal121of the Schmitt trigger120is electrically connected to the first output terminal113of the comparator110, the logic circuit130is electrically connected to the second output terminal122of the Schmitt trigger120, and the capacitor set140is electrically connected to the second input terminal112and the logic circuit130.

In some embodiments, the comparator110is a comparator with single-ended input, wherein the comparator110receives a first input signal Vin1at the first input terminal111and receives a second input signal Vin2at the second input terminal112. The comparator110is configured to compare the first input signal Vin1and the second input signal Vin2and to output a comparison signal at the first output terminal113, wherein the comparison signal is a first high voltage potential or a first low voltage potential. Please refer toFIG.2A,FIG.2BandFIG.2C.FIG.2Aillustrates a waveform diagram of the voltage of an external input signal received by the comparator110of the comparison control circuit100according to an embodiment of the present application.FIG.2Billustrates a waveform diagram of the voltage of a clock of the comparator110of the comparison control circuit100according to an embodiment of the present application, wherein the clock of the comparator110is configured to trigger the comparator110to output the comparison signal.FIG.2Cillustrates a waveform diagram of the voltage of the comparison signal output by the comparator110of the comparison control circuit100according to an embodiment of the present application, wherein a waveform in a solid line represents the waveform of the comparison signal, and a waveform in a three-dotted chain line represents the waveform led by noise. In the waveform diagrams of theFIG.2A,FIG.2BandFIG.2C, the horizontal axis represents time in nanoseconds (ns). The vertical axis represents the magnitude of voltage, and the unit is volts (V). In this embodiment, the first high voltage potential is 1 volt, and the first low voltage potential is 0 volt. The first input signal Vin1is the external input signal, and the second input signal Vin2is a comparison voltage potential Vcom, wherein the value of the comparison voltage potential Vcomis 0.5 volts. When the value of the first input signal Vin1(as illustrated in a dotted line L1shown inFIG.2A) received at the first input terminal111of the comparator110is greater than or equal to the second input signal Vin2, the clock of the comparator110will trigger the comparator110at the falling edge (as illustrated in a dotted line L1shown inFIG.2B), such that the comparator110outputs the first high voltage potential (as illustrated in a box R1formed by a single-dotted chain shown inFIG.2C) at the first output terminal113. When the value of the first input signal Vin1(as illustrated in a dotted line L2shown inFIG.2A) received at the first input terminal11I of the comparator110is less than the second input signal Vin2, the clock of the comparator110will trigger the comparator110at the rising edge (as illustrated in a dotted line L2shown inFIG.2B), such that the comparator110outputs the first low voltage potential (as illustrated in a box R2formed by a single-dotted chain shown inFIG.2C) at the first output terminal113.

The Schmitt trigger120is configured to output a trigger signal at the second output terminal122according to the comparison signal received at the third input terminal121and a voltage potential range, wherein the trigger signal is a second high voltage potential or a second low voltage potential. In some embodiments, the user can define the voltage potential range of the Schmitt trigger120. In this embodiment, the voltage potential range of the Schmitt trigger120is in a range from the first low voltage potential to the first high voltage potential. When the value of the comparison signal received by the Schmitt trigger120is greater than or equal to the upper limit of the voltage potential range, the Schmitt trigger120outputs the second high voltage potential at the second output terminal122. When the value of the comparison signal received by the Schmitt trigger120is within the voltage potential range (i.e., the value of the comparison signal is greater than or equal to the lower limit of the voltage potential range, and the value of the comparison signal is less than the upper limit of the voltage potential range), the Schmitt trigger120does not perform any action. When the value of the comparison signal received by the Schmitt trigger120is less than the lower limit of the voltage potential range, the Schmitt trigger120outputs the second low voltage potential at the second output terminal122. In some embodiments, the second high voltage potential is 1 volt, and the second low voltage potential is 0 volt. Since the Schmitt trigger120has better noise immunity to analog signals, the noise generated by the power source or the noise of the comparison signal output by the comparator110can be effective against by disposing the Schmitt trigger120in the comparison control circuit100, thereby avoiding problems during the operating process of the comparison control circuit100.

The capacitor set140is configured to adjust the second input signal Vin2when being controlled by the logic circuit130. In some embodiments, the capacitor set140includes N capacitors C1-CNand N switches S1-SN, wherein each of the capacitors C1-CNhas a first terminal and a second terminal. The first terminal of each of the capacitors C1-CNis electrically connected to the second input terminal112of the comparator110. The second terminal of each of the capacitors C1-CNcan be selectively electrically connected to a reference voltage source Vrefor ground through the corresponding switch when being controlled. When a second terminal of a capacitor is electrically connected to the reference voltage source Vref, the capacitor will be charged. When a second terminal of a capacitor is electrically connected to the ground, the capacitor will be discharged.

The logic circuit130is configured to control the capacitor set140according to the trigger signal to correspondingly adjust the comparison voltage potential Vcom. In other words, the logic circuit130will control the corresponding switch(es) in the capacitor set140according to the value of the trigger signal. Then, the corresponding capacitor(s) will be electrically connected to the reference voltage source Vrefor ground for charging or discharging. Finally, the capacitor set140will calculate an adjusted comparison voltage potential according to the capacitance of each capacitor and output the adjusted comparison voltage potential to the second input terminal112of the comparator110.

In some embodiments, the structure of the comparison control circuit100can be applied in an analog-to-digital converter200. Please refer toFIG.3.FIG.3illustrates a schematic circuit diagram of the analog-to-digital converter200according to an embodiment of the present application. The analog-to-digital converter200includes a comparator210, a Schmitt trigger220, a logic circuit230and a capacitor set240. As shown inFIG.3, a third input terminal221of the Schmitt trigger220is electrically connected to a first output terminal213of the comparator210, the logic circuit230is electrically connected to a second output terminal222of the Schmitt trigger220, and the capacitor set240is electrically connected to a second input terminal212of the comparator210and the logic circuit230. In this embodiment, the signal received at the first input terminal211of the comparator210is an analog input signal Vain, the signal received at the second input terminal212of the comparator210is a comparison voltage potential Vcom, and the signal received at the third input terminal221of the Schmitt trigger220is a comparison signal.

The analog-to-digital converter200is configured to convert the analog input signal Vaininto a digital output signal with N bits. In some embodiments, the analog-to-digital converter200starts the conversion from the most significant bit (MSB) of the digital output signal and sequentially converts the remaining bits until the least significant bit (LSB) is converted, which complete a complete analog-to-digital conversion. In some embodiments, the analog-to-digital converter200outputs a digital output signal Vdoutthrough the logic circuit230, wherein the logic circuit230is a successive approximation register (SAR).

The capacitor set240of the analog-to-digital converter200includes a plurality of switched capacitor groups. Each of the switched capacitor groups includes a capacitor and a switch in series, and each of the switched capacitor groups is in parallel with each other, wherein a parallel point of each switched capacitor group is electrically connected to the second input terminal212of the comparator210. Each switch of the capacitor set240is electrically connected to a reference voltage source Vrefor ground selectively when being controlled, wherein the reference voltage source Vrefis a fixed voltage value. In some embodiments, the capacitance of the capacitor Ciis twice the capacitance of the capacitor Ci+1, and the capacitance of the capacitor CN−1is equal to the capacitance of the capacitor CN, wherein i=1˜N−2. In some embodiments, the capacitor set240is a capacitive digital-to-analog converter, wherein the capacitive digital-to-analog converter converts a digital signal into an analog signal by using capacitors to store charges. For example, in this embodiment, the capacitor set240includes four capacitors C1-C4and four switches S1-S4. If a digital signal received by the capacitor set240is (1100), the capacitors C1and C2are electrically connected to the reference voltage source Vref, and the capacitors C1and C2are electrically connected to the ground. It is assumed that the value of the reference voltage source Vrefis 1 volt and the capacitance of the capacitor C4is C. Since the total capacitance of the capacitors in parallel is equal to the sum of the capacitance of the capacitors, and the impedance of a capacitor is inversely proportional to its capacitance, the comparison voltage potential Vcomoutput by the capacitor set240to the comparator210is 0.75 volts. The formula is as follows:

Please refer toFIG.4.FIG.4illustrates a flow diagram of the operation of the analog-to-digital converter200according to an embodiment of the present application. As shown inFIG.4, when the analog input signal Vainis input to the analog-to-digital converter200, the analog-to-digital converter200samples (Sample-and-Hold, S&H) the analog input signal Vain, and inputs the analog input signal Vainto comparator210. The purpose of sampling is to make the analog-to-digital converter200to maintain the consistency of the analog input signal Vainduring the operating process, so as to avoid errors in the digital output signal Vdout. In step S20, the comparator210compares the analog input signal Vainof the first input terminal211and the comparison voltage potential Vcomof the second input terminal212and outputs, at the first output terminal213, a comparison signal to the Schmitt trigger220of the analog-to-digital converter200. In step S30, the Schmitt trigger220outputs, at the second output terminal222, a trigger signal to the logic circuit230of the analog-to-digital converter200according to the comparison signal and a voltage potential range.

In step S40, the logic circuit230stores the trigger signal in order as the corresponding bits in the analog input signal Vain(from the most significant bit to the least significant bit). Then, the logic circuit230control the corresponding switch in the capacitor set240of the analog-to-digital converter200according to the trigger signal, such that the corresponding capacitor is electrically connected to the reference voltage source Vrefor ground. For example, if the current conversion sequence is the second bit, it represents that the logic circuit230will store the trigger signal as the second valid bit of the analog input signal Vain. If the value of the trigger signal is 1, the logic circuit230will control the switch S2of the capacitor set240, such that the capacitor C2of the capacitor set240is electrically connected to the reference voltage source Vreffor charging.

In step S50, the capacitor set240calculates an adjusted comparison voltage potential Vcomaccording to the capacitance of each capacitor and outputs the adjusted comparison voltage potential Vcomto the comparator210. In step S60, the analog-to-digital converter200repeats steps S20-S50to perform the next round of bit conversion until all the bits in the analog input signal Vainare converted, then proceeds to step S70. Since the magnitude of capacitance of each capacitor in the capacitor set240is different, the value of the comparison voltage potential Vcomoutput by the capacitor set240in each round of bit conversion is also different. With the proceeding of each round of bit conversion, the value of the comparison voltage potential Vcomreceived by the comparator210will gradually approach the value of the analog input signal Vain. When the value of the comparison voltage potential Vcomreceived by the comparator210is equal to the value of the analog input signal Vain, it represents that the analog-to-digital converter200has completely converted the analog input signal Vaininto all bits of the digital output signal Vdout. Therefore, in step S70, the analog-to-digital converter200will output a digital output signal Vdoutthrough the logic circuit230and end the analog-to-digital conversion this time.

In another embodiment, the comparison control circuit100can also be applied in an analog low-dropout regulator300. Please refer toFIG.5.FIG.5illustrates a schematic circuit diagram of the analog low-dropout regulator300according to an embodiment of the present application. The analog low-dropout regulator300includes an error amplifier310, a pass transistor320, a voltage divider circuit330and a comparison control circuit340. The error amplifier310has a positive input terminal312, a negative input terminal311and a third output terminal313. The pass transistor320has a gate terminal321, a drain terminal322and a source terminal. The comparison control circuit340includes a comparator341, a Schmitt trigger342, a logic circuit343and a capacitor set344. As shown inFIG.5, the gate terminal321of the pass transistor320is electrically connected to the third output terminal313of the error amplifier310, the voltage divider circuit330is electrically connected to the drain terminal322of the pass transistor320and the positive input terminal312of the error amplifier310, and a second input terminal341bof the comparator341is electrically connected to the drain terminal322of the pass transistor320. In this embodiment, the signal received at a first input terminal341aof the comparator341is the comparison voltage potential Vcom, and the signal received at the second input terminal341bof the comparator341is an output voltage Vout.

The error amplifier310is configured to output a control voltage at the third output terminal313according to a feedback voltage Vfbreceived at the positive input terminal312and a stable reference voltage potential Vsrefreceived at the negative input terminal311, wherein the control voltage is configured to control the voltage of the gate terminal321of the pass transistor320. When the feedback voltage Vfbis greater than the stable reference voltage potential Vsref, the error amplifier310will adjust the voltage of the gate terminal321of the pass transistor320, so that the value of a current flowing through the pass transistor320decreases to reduce the output voltage Vout. When the feedback voltage Vie is less than the stable reference voltage potential Vsref, the error amplifier310will adjust the voltage of the gate terminal321of the pass transistor320, so that the value of the current increases to increase the output voltage Vout.

The pass transistor320is configured to output the output voltage Voutat the drain terminal322according to the control voltage received at the gate terminal321. In some embodiments, the pass transistor320receives an input voltage Vinat the source terminal323. When the gate terminal321of the pass transistor320receives the control voltage from the error amplifier310, the pass transistor320outputs the output voltage Voutat the drain terminal322, wherein the value of the input voltage Vinis greater than the value of the output voltage Vout. In some embodiments, the pass transistor320is a PMOS (p-channel metal oxide semiconductor).

The voltage divider circuit330is configured to divide the output voltage Voutand the feedback voltage Vfb, such that the value of the feedback voltage Vfbis the same as the value of the stable reference voltage potential Vsref, further such that the value of the output voltage Voutis the same as the value of the stable reference voltage potential Vsref, wherein the stable reference voltage potential Vsrefis a fixed voltage not affected by temperature or signal noise. In some embodiments, the voltage divider circuit330includes a first voltage dividing resistor Rfb1and a second voltage dividing resistor Rfb2, wherein the resistance of the first voltage dividing resistor Rfb1is much smaller than the resistance of the second voltage dividing resistor Rfb2. It is assumed that the error amplifier310is an ideal amplifier, the value of the output voltage Voutis the same as the value of the stable reference voltage potential Vsrefcan be calculated, and the formula is as follows:

In some embodiments, the comparison control circuit340is configured to stabilize the output voltage Vout. When the pass transistor320outputs an output voltage Voutat the drain terminal322, the output voltage Voutbecomes more stable by being adjusted through the comparison control circuit340. In some embodiments, the output voltage Voutis input to the comparison control circuit340through the second input terminal341bof the comparator341, and the output voltage Voutis compared with comparison voltage potential Vcomreceived at the first input terminal341aof the comparator341. When the value of the output voltage Voutis greater than the comparison voltage potential Vcom, the comparison control circuit340control the capacitor set344through the logic circuit343to reduce the value of the output voltage Voutto the comparison voltage potential Vcom. When the value of the output voltage Voutis less than the comparison voltage potential Vcom, the comparison control circuit340control the capacitor set344through the logic circuit343to increase the value of the output voltage Voutto the comparison voltage potential Vcom. In some embodiments, the comparison voltage potential Vcomreceived at the first input terminal341aof the comparator341is equal to the stable reference voltage potential Vsref.

In some embodiments, the user can define the number of capacitors in the capacitor set344and the capacitance of each capacitor according to the value of the output voltage Vout. If the more number of capacitors in the capacitor set344, it represents that the voltage value output by the capacitor set344will have more variations; and if the less number of capacitors in the capacitor set344, it represents that the voltage value output by the capacitor set344will have fewer variations. If the more capacitance of a capacitor, it represents that the voltage range output by the capacitor set344will be larger; if the less capacitance of a capacitor, it represents that the voltage range output by the capacitor set344will be smaller. For example, if the value of the output voltage Voutis small (e.g., the value of the output voltage Voutis 1 volt), the user can set a smaller number of capacitors with smaller capacitance in the capacitor set344to save cost.

Please refer toFIG.6.FIG.6illustrates a flow diagram of the operation of the analog low-dropout regulator300according to an embodiment of the present application. As shown inFIG.6, in step S80, the analog low-dropout regulator300inputs an input voltage Vinto the source terminal323of the pass transistor320. In step S90, the analog low-dropout regulator300respectively inputs a stable reference voltage potential Vsrefand a feedback voltage Vfbto the negative input terminal311and the positive input terminal312. At this time, the error amplifier310outputs a control voltage to the gate terminal321of the pass transistor320according to the stable reference voltage potential Vsrefand the feedback voltage Vfb. In step S100, the gate terminal321of the pass transistor320receives the control voltage, such that the pass transistor320enters a conductive state and outputs an output voltage Voutat the drain terminal322. At this time, if the value of the output voltage Voutis not equal to the stable reference voltage potential Vsref, the analog low-dropout regulator300adjusts the output voltage Voutthrough the voltage divider circuit330and the error amplifier310, such that the value of the output voltage Voutis equal to the stable reference voltage potential Vsref.

In step S110, when the value of the output voltage Voutis equal to the stable reference voltage potential Vsref, the comparator341of the comparison control circuit340receives the output voltage Voutthrough the second input terminal341band outputs, according to the output voltage Voutand the comparison voltage potential Vcomreceived at the first input terminal341a, a comparison signal at the first output terminal341cto the third input terminal342aof the Schmitt trigger340. In step S120, the Schmitt trigger342outputs, according to the comparison signal and a voltage potential range, a trigger signal to the logic circuit343of the comparison control circuit340at the second output terminal342b. In step S130, the logic circuit343controls the corresponding switch in the capacitor set344of the comparison control circuit340according to the trigger signal, such that the corresponding capacitor in the capacitor set344is charged or discharged. Finally, in step S140, the capacitor set344calculates an adjusted output voltage Voutaccording to the capacitance of each capacitor and outputs it.

To sum up, according to some embodiments of the comparison control circuit100, even if the input signal or power signal in various types of circuits is mixed with noise, these circuits can immune the noise through the comparison control circuit100, thereby avoiding operation failure or to output wrong results. For example, applying the structure of the comparison control circuit100in the analog-to-digital converter200can make the analog-to-digital converter200outputting a more accurate digital output signal Vdout. The analog low-dropout regulator300can adjust the output voltage Voutthrough the comparison control circuit340, such that the output voltage Voutbecomes more stable.

Although the present application has been disclosed by the embodiments as aforementioned, it is not intended to limit the creation of the present application. Those skilled in the art may make some modifications and changes without departing from the spirit and scope of the present application, but such modifications and changes are still within the scope of the present application.