Storage array including a bridge module interconnect to provide bridge connections to different protocol bridge protocol modules

A storage array and systems for configuring a storage array are provided. In one example, the storage array includes a motherboard. The motherboard includes a first compute module and an input/output (I/O) mid-plane that is routed to the first compute module. The I/O mid-plane has a plurality of peripheral component interconnect express (PCIe) lanes coupled to the first compute module. A bridge module interconnect is routed to the I/O mid-plane via one or more of the plurality of PCIe lanes of the I/O mid-plane. The bridge module interconnect provides bridge connections to receive to two or more types of protocol bridge modules. A storage mid-plane provides integrated routing between each of a plurality of drive connectors and each of the bridge connections of the two or more types of protocol bridge modules of the bridge module interconnect.

FIELD OF THE DISCLOSURE

The embodiments described in this disclosure relate to storage systems, and in particular, storage systems that enable reconfiguration in accordance with a desired protocol of storage drives, with minimal redesign and engineering.

BACKGROUND

Storage arrays are computer systems that are designed to store data and efficiently serve data to processing applications. Typically, storage arrays are provisioned for entities that require specific storage capacity and performance. Often, one or more storage arrays are provisioned for entities having multiple clients, local or remote, that require efficient access to mission critical data. In some configurations, storage arrays are installed in data centers, where multiple storage arrays are clustered together to deliver either higher storage capacity and/or performance.

Although storage arrays work well, storage arrays are commonly designed by different manufacturers in unique custom configurations. For example, these unique custom configurations provide for routing between compute modules and storage drives that may be connected to the storage array. Although this works, manufacturers of storage arrays must continue to redesign internal systems depending on the types of drives and protocols to be serviced. As the options for drive types and protocols continue to change and evolve, manufacturers of storage arrays also must continue to change their designs, which increases cost and design cycles. What is needed is an infrastructure that enables modularity and capability to be changed with minimal configuration.

It is in this context that embodiments of this disclosure arise.

SUMMARY

Embodiments are provided for a modular motherboard configuration that enables connection of different protocol storage drives via universal-type connectors and preconfigured routing for connecting to specific bridge boards coupled to a bridge module interconnect. The motherboard further includes an I/O mid-plane with pre-wired and routed PCIe lanes and a storage mid-plane with pre-wired and routed connections to drive connectors that can receive connection from different types of drives that follow different protocols.

In one embodiment, a storage array is provided. The storage array includes a motherboard. The motherboard includes a first compute module and an input/output (I/O) mid-plane that is routed to the first compute module. The I/O mid-plane has a plurality of peripheral component interconnect express (PCIe) lanes coupled to the first compute module. A bridge module interconnect is routed to the I/O mid-plane via one or more of the plurality of PCIe lanes of the I/O mid-plane. The bridge module interconnect provides bridge connections to receive to two or more types of protocol bridge modules. A storage mid-plane provides integrated routing between each of a plurality of drive connectors and each of the bridge connections of the two or more types of protocol bridge modules of the bridge module interconnect.

In some embodiments, the first compute module actively uses select ones of the PCIe lanes based the type of protocol bridge modules coupled to the bridge connections to the bridge module interconnect and based on a type of protocol of one or more storage drives connected to the plurality of drive connectors.

In some embodiments, the plurality of drive connectors is configured with routing to each one of the bridge connections of the bridge module interconnect via the storage mid-plane. In one example, any type of protocol of the one or more storage drives connected to the plurality of drive connectors is provided with communication with a corresponding one or more of the protocol bridge modules for the one or more storage drives.

In some embodiments, the two or more types of protocol bridge modules are selected from a serial attached SCSI (SAS) protocol bridge module and a non-volatile memory express (NVME) protocol bridge module.

In some embodiments, the motherboard further includes a bridge board module that provides a passive interface to a predefined set of the plurality of drive connectors for interconnection to a predefined set of NVME storage drives.

In some embodiments, the motherboard further includes a second compute module. The first compute module is provided for a first controller and the second compute module provided for a second controller, and the first and second controllers provide failover compute processing for the storage array. The second compute module is routed to the I/O mid-plane via a corresponding set of the plurality of PCIe lanes. The second compute module is routed to the bridge module interconnect using the corresponding set of the plurality of PCIe lanes.

In some embodiments, the bridge connections of the bridge module interconnect provide communication between the PCIe lanes of the I/O mid-plane and the integrated routing of the storage mid-plane.

In some embodiments, the bridge module interconnect is configured to receive two protocol bridge modules of a serial attached SCSI (SAS) type, and receive storage drives having a SAS circuit.

In some embodiments, the storage drives having the SAS circuit are configured to include storage media selected from a hard disk drive (HDD) or solid state drive (SSD).

In some embodiments, the motherboard further includes a bridge board module that provides a passive interface to a set of four (4) NVME storage drives via two of said drive connectors routed through the storage mid-plane and said first and second compute module routed via eight (8) PCIe lanes.

In some embodiments, the bridge module interconnect is configured to receive two protocol bridge modules of a non-volatile memory express (NVME) type, and receive storage drives having a NVME circuit.

In some embodiments, the storage drives having the NVME circuit are configured to include storage media selected from NVME solid state drives (SSD).

In some embodiments, the motherboard further includes a bridge board module that provides a passive interface to a set of four (4) NVME storage drives via two of said drive connectors routed through the storage mid-plane and said first and second compute module routed via eight (8) PCIe lanes.

In some embodiments, each of the plurality of drive connectors has a plurality of pins that are connected to the integrated routing of the storage mid-plane to provide connection to different protocol type storage drives, and each type of protocol storage drive when connected to a respective drive connector provides interconnection to a corresponding type of protocol bridge module when connected to ones of the bridge connections of the bridge module interconnect.

DETAILED DESCRIPTION

The disclosed embodiments relate to a storage array that includes an internal motherboard configured that is optimized to operate in multiple configurations of storage protocols. By way of the example, the motherboard has been arranged to separate compute modules from storage modules, which enables customization of the motherboard to operate in any one of a plurality of protocol modes. Depending on the protocol mode, a bridge module interconnect can be configured to receive protocol bridge modules that are selected based on a type of protocol of the storage drives to be connected in the storage array.

The configurability of the storage array is facilitated by the inclusion of an input/output (I/O) mid-plane and a storage mid-plane. The bridge module interconnect is disposed between the I/O mid-plane and the storage mid-plane. In one configuration, the I/O mid-plane has routed therein a plurality of peripheral component interconnect express (PCIe) lanes, which are configured to interconnect protocol bridge modules that are connected to the bridge module interconnect. In one configuration, the storage mid-plane includes a plurality of routed connections between the bridge module interconnect and drive connectors that are to receive storage drives.

The drive connectors, in one configuration, have pin connectors that enable connection to different types of drive protocols. As a result, depending on the configuration of the storage array, the storage array can receive storage drives of a specific protocol type and also receive protocol bridge modules of that specific protocol type. Because the motherboard has the routing in the I/O mid-plane and the storage mid-plane preconfigured to any type of protocol, the interconnection, routing and communication between the storage drives and the compute modules will be made functional, as all routing is already present on the I/O and storage mid-planes.

In some configurations of the storage array, the types of protocol bridge modules are selected from a serial attached SCSI (SAS) protocol bridge module and a non-volatile memory express (NVME) protocol bridge module. For instance, some configurations may require SAS solid state drives (SSDs) or a serial AT attachment (SATA) solid state drives (SSDs). As described below and shown in the figures, one configuration includes providing a storage drive that includes a SAS interposer or circuit, which enables the storage drive to communicate using the SAS protocol. Thus, if storage drives that communicate using the SAS protocol are to be used in the storage array, the bridge module interconnect is adjusted to receive protocol bridge modules to support the SAS protocol.

If the storage array is to be configured to receive NVME storage drives, the bridge module interconnect is adjusted to receive protocol bridge modules to support the NVME protocol. In further configurations, the motherboard may include a second compute module, wherein a first compute module is provided for a first controller and the second compute module is provided for a second controller. Thus, the first and second controllers provide failover compute processing for the storage array. In still another embodiment, the bridge module interconnect may be provided with a bridge board module that provides a passive interface to a set of four NVME storage drives via two of said drive connectors routed through the storage mid-plane.

In this configuration, first and second compute modules are routed via eight PCIe lanes. Thus, it is possible to construct a storage arrays having different configurations of storage drives and storage drives that implement different communication protocols. One advantage, of many, is the flexibility of the motherboard configuration and its flexibility to be changed from one configuration to another. This flexibility provides an ability to reuse the same motherboard for multiple types of storage array product lines that may have different suites of drive configurations and/or drive communication protocols.

FIG. 1illustrates a motherboard100having components for flexibly changing a configuration of a system based on a desired protocol of storage drives to be used in a storage array. The motherboard100includes a compute module102, and I/O mid-plane104, a bridge module interconnect105, a storage mid-plane110, drive connectors114, and storage drives112. This configuration shows an embodiment where a single compute module102is provided. The motherboard100can therefore be integrated into a storage array, defined by the multiple storage drives130that may be connected to connectors114that are interfaced with the storage mid-plane110.

As will be described in more detail below, the compute module102may include one or more CPUs, dedicated memory (e.g., double data rate fourth-generation synchronous dynamic random-access memory (DDR4×4), buses, interconnect slots, and connections to network interface cards (NICs). The I/O mid-plane104is configured to include a plurality of integrated routes for PCIe lanes, which integrate with the compute module102and the bridge module interconnect105. The bridge module interconnect105is configured with the capability of receiving different types of protocol bridge modules106, which are selected based on the type of communication protocol desired for the storage drives130. The protocol bridge modules106may be connected to the bridge module interconnect105by way of connectors, which enables specific types of protocol bridge modules106to be connected to the motherboard100, depending on the protocol used for the storage drives130. In one configuration, a bridge board module108may also be provided. The bridge board module108can either be a plug-in board module, or an integrated board module that couples to or as part of the motherboard100. In this configuration, the bridge board module108can be provided with passive components, which enable the passing of signals between the storage mid-plane110and the I/O mid-plane104.

FIG. 2illustrates another configuration of a motherboard200, where multiple compute modules are integrated thereon, to provide a storage array having standby controllers for redundancy. As shown, a compute module A102aand a compute module B102bare connected to the motherboard200, and are respectively connected to the I/O mid-plane104. In this configuration, the I/O mid-plane104also has a plurality of pre-integrated PCIe lanes, which couple to each of the compute modules102aand102b. Further shown is integrated connections between each of the compute modules102aand102bwith the bridge board module108.

The connections between the I/O mid-plane104and the protocol bridge modules106aand106bare configured with integrated route lines between the PCIe lanes of the I/O mid-plane104and connectors disposed on the motherboard200for making communication with the protocol bridge modules that may be connected to said connectors. As will be described in greater detail below, the protocol bridge modules106aand106b, are selected based on the type of protocol to be used by the storage drives130, which are connected to the drive connectors114. Broadly speaking, the connectors114will include connection pins that are suitable to connect to any type of storage drive protocol, and the connection pins are all routed through the storage mid-plane110leading to the connectors of the bridge module interconnect105. This enables a specific type of bridge protocol module106aand106bto be inserted into the bridge module interconnect105to match the type of storage drives130connected to the storage mid-plane110via the drive connectors114.

The storage mid-plane110therefore provides integrated routing between the storage drives130and the respective connectors114and the connector locations in each of the protocol bridge modules106aand106b. This configuration allows for a fixed integrated wiring and routing to be disposed in the I/O mid-plane104for routing PCIe lanes to the compute modules, and fixed integrated wiring and routing to be disposed in the storage mid-plane110that lead to the storage drives130. In the middle of the motherboard200will reside the bridge module interconnect105, which can be custom tailored to receive protocol bridge modules106aand106bfor the specific types of storage drives130that are to be connected to the drive connectors114. This configuration of the motherboard200, and the components integrated therein provide for a flexible packaging form factor that allows for a quick configuration of different types of storage arrays.

Some storage arrays can be configured with different storage drives by simply exchanging the protocol bridge modules106aand106b, leaving the integrated routing in the storage mid-plane110and the I/O mid-plane104intact. This is possible because routing is provided in both the I/O mid-plane104and the storage mid-plane110in such a way that routing is present depending on the type of protocol being used for the storage drives130and the protocol used by the protocol bridge modules106. If a particular type of protocol bridge module106is not being used, the routing leading to connectors in the bridge module interconnect105will simply not be used. The same can be said for the drive connectors114, which may include pins that are not connected to specific storage drives130when connected to the drive connector114.

FIG. 3illustrates a more detailed diagram of the motherboard100ofFIG. 1, and specific routing between the specific components, in accordance with one embodiment. As shown, the compute module102ais routed to the protocol bridge modules106, and also to the bridge board module108. In this illustration, the protocol bridge modules106include an NVME bridge board302that is coupled to the bridge module interconnect105via a connector380. Further shown is a SAS bridge board304coupled to the bridge module interconnect105via a connector382. This illustration is provided to show the option of coupling an NVME bridge board302or a SAS bridge board304to the bridge module interconnect105, depending on the design of the storage array, and the type of storage drives112that are to be coupled to drive connectors114.

In a specific implementation, the bridge module interconnect105will simply include one or the other of the NVME bridge board302and the SAS bridge board304. Most configurations will not include both bridge boards302and304at the same time, as the storage drives130will dictate which type of bridge board will be connected to the bridge module interconnect105. However, this illustration is provided to show that one or the other type of bridge board may be coupled to the motherboard100, defining the functionality and communication protocol of the resulting storage array.

Continuing with the illustration of the protocol bridge modules106, the NVME bridge board302will include a PCIe switch310, which can communicate with a plurality of integrated routed lines via the storage mid-plane110to each of the storage drives112coupled to the storage array. If the configuration of the storage array is to support SAS drives or SATA drives, then the SAS bridge board304can be connected by way of connector382to the bridge module interconnect105, instead of the NVME bridge board302. The SAS bridge board304is also provided with an EXP x48 chip312and a SAS host bus adapter (HBA) chip314.

It should be understood that the example chips provided on the bridge boards can be changed, depending on the number of buses, processing power, operations, and other design considerations. In accordance with one embodiment of the present invention, the routing to each one of these bridge boards is configured to be integrated into the I/O mid-plane104for communicating PCIe lanes to the compute module102aand integrated routing in the storage mid-plane110to each of the drive connectors114.

This illustration also shows that the bridge board module108is a passive NVME bridge board, which allows NVME connection to selected drive connectors114of the storage array. In one configuration, a set number of drive connectors114will be prewired with the passive connections. In some embodiments, the bridge board module108may also include a fan control306and temperature sensors308, among other components. Furthermore, it is shown that the power supply320acan provide power to components disposed in the bridge board module108as well as to other bridge module interconnect105boards and the storage drives112.

Further shown is the ability of the motherboard100to include predefined connections between the protocol bridge modules106and expansion ports324and326. This provides for expansion outside of the storage array, such as to couple more than one or multiple storage arrays to form a cluster, or other larger storage configuration. Broadly speaking, the I/O mid-plane104is also referred to as a controller I/O mid-plane, as this I/O mid-plane104provides access to compute module102a.

FIG. 4provides a more detailed diagram of an example motherboard200, as shown inFIG. 2. In this illustration, it is shown that a first compute module102aand a second compute module102bare respectively interconnected to the I/O mid-plane104. As mentioned above, the I/O mid-plane104is configured to route PCIe lanes to and from the compute modules102aand102b. This configuration would be used when the compute modules provide for redundancy, such as for failover protection in a storage array. By way of example, the upper half of the illustrated motherboard200may be associated with a first controller A and the bottom half may be associated with a second controller B, and the respective protocol bridge modules106aand106bwill service the respective controllers.

In the case of a failover, where an active controller fails or is required to proceed with storage processing applications, a standby controller can actively take its place and resume its storage tasks without risking loss of data or access to data. This example also shows the integration of power supply320ain association with compute module102aand power supply320bin association with compute module102b. Respective expansion ports324aand326aare associated with compute module102a, and expansion ports324band326bare associated with compute module102b.

This illustration ofFIG. 4is provided to show that the bridge module interconnect105can be populated with NVME bridge boards302for interfacing with compute modules102aand102bvia the I/O mid-plane104and the drive connector114via the storage mid-plane110. Alternatively, the bridge module interconnect105can be populated with SAS bridge boards304for interfacing with compute modules102aand102bvia the I/O mid-plane104and the drive connector114via the storage mid-plane110. It is also shown in more detail that the storage mid-plane110will include preconfigured routing between the storage connectors114and each of the locations where connectors380and382are disposed in the bridge module interconnect105. This allows for different types of protocol bridge modules106aand106bto be connected to the respective connectors380and382that service the compute modules102aand102b.

The bridge board module108is also shown disposed between the compute modules102aand102b, and as noted above this bridge board module108provides for a passive NVME bridge. The passive NVME bridge provides direct connection to select ones of the storage connectors114, no matter the type of protocol bridge board106that may be connected to the bridge module interconnect105. In one specific embodiment, the bridge board module108will provide eight (8) PCIe lanes for connecting to four (4) storage connectors114. These four (4) storage connectors114may be provided with high-performance NVME storage drives130b, as shown below inFIG. 5C. The remaining storage drives130connected to the remaining storage connectors114may be selected depending on whether and NVME bridge boards302or SAS bridge boards304were connected to the bridge module interconnect105.

FIG. 5Aillustrates an example of storage drive130, being a generic storage drive, connected to the drive connector114that couples with routed interconnected wiring of the storage mid-plane110. As shown, the storage drive130will include a connector314, which is insertable into the drive connector114. The storage drive130will include a drive protocol circuit342and storage media340. The type of drive protocol circuit342will depend on the type of storage media340, and the protocol. Broadly speaking, the drive protocol circuit342can be defined by one or more circuits, chips, integrated logic, and other communication and electrical wiring. The storage media340is designed to store data, and the form will depend upon the type of storage media340to be part of the storage drive130. In accordance with one configuration, the connector314will have specific pins that will connect into the drive connector114.

However, in accordance with one embodiment, only the pins of connected314that relate to the protocol of the storage drive130will make contact with the specific pins within drive connector114. Therefore, there will be pin connections in the drive connector114that will be unused, simply because the storage drive130is not of that type of protocol.

In one embodiment, the drive connector114, and by way of example, may be a connector referred to as a U.2, SFF 8634 or SFF-8639 connector. This type of connector provides the ability to support connection to storage drives130that have an interface to the connector, but will only be active depending on the pins that may contact with specific pins of the U.2 connector. If the drive is of a particular protocol, only certain ones of the pins on the drive will make contact to specific pins in the U.2 connector, thus leaving other pins inactive. Again it is emphasized that the U.2 connector is only one example of a connector that can receive connection from different types of drives, and may contact only the pins that relate to that specific protocol. It is envisioned that as protocols change and or bandwidth and/or design needs are modified, different connectors that provide the same functionality or modularity can be used and may replace the U.2connector example provided herein.

FIG. 5Billustrates an example of a storage drive130a, which includes a SAS circuit352. The SAS circuit352may be viewed as an interposer circuit, which allows for conversion of communication signals coming from SATA SSD storage media350of the storage drive130a. The result is that the storage drive130a, by way of the SAS circuit352, will be connecting to the drive connector114using connector314ain accordance with a SAS protocol. Therefore, the pins for the SAS protocol will be exposed by connector314a, and the drive connector114will only make contact with those pins that are for the SAS protocol, leaving other pins unused.

FIG. 5Cillustrates an example of a storage drive130b, which includes an NVME circuit362, and NVME SSD storage media360. In this configuration, the connector314bwill have pins that correspond to connectors used for the NVME protocol, and therefore when connected to the drive connector114, only those pins within drive connector114that correspond to the NVME protocol will be used, leaving the other pins unused. Because connections between the drive connector114and the storage mid-plane110will include routing for any type of protocol, depending on the type of pins that make contact with the drive connector114, will dictate which of the lines that are routed in the storage mid-plane110will eventually be activated and will be communicating with the respective protocol bridge modules106that may be connected to the bridge module interconnect105.

FIG. 5Dillustrates another embodiment, where a storage drive130cis provided with a SAS circuit372, for a hard disk drive (HDD)370. The connector314c, will therefore communicate using the SAS protocol and therefore the pins in drive connector114associated with the SAS protocol will be making contact and the remaining will remain unused. The flexibility provided by this design, and integration of drive connector114with a storage mid-plane110provides for the flexibility of connecting any type of storage drive130, which may be able to meet with drive connector114and utilize only those pins consistent with the protocol of the storage drive130.

FIG. 6illustrates one example of compute modules102aand102b, in accordance with one embodiment. As shown, the compute modules102includes CPUs602aand602b, which are respectively coupled to memory604a,604b,606a, and606b. Further shown is that PCIe lanes coming from the I/O mid-plane104couple to specific lanes within the compute module102aand102b. As shown, PCIe lanes from the I/O mid-plane104couple to PCIe switch608, SAS HBA609, fixed NVME610, and NTB/Mirror612that couples between the two compute modules102aand102b. An internal bus then communicates with separate PCIe slots (S1, S2, S3)622.

The slots can be connected to specific cards that provide an interface to communicate with different types of networking protocols. By way of example, the networking protocol can be an Ethernet connection, a Fibre Channel connection, a mixed connection, or various other high-speed connectors that allow for the storage array to be connected to a network and/or other devices. For more information regarding the integrated PCIe slots622, reference may be made to U.S. Pat. No. 8,949,502, entitled “PCIe NVRAM card based on NVDIMM,” issued on Feb. 3, 2015, which is incorporated herein by reference.

The internal bus is also shown connected to a PCIe Lane that communicates between the two CPUs602aand602b. Further, the internal bus communicates with an integrated 10GBT×2 connector/interface628. The compute modules also include an USB×2 connector626, a POE (Power-Over-Ethernet)-BMC connector624, and a (Baseboard Management Controller) BMC630that couples to the respective power supplies320aand320b. The internal bus is further shown connected to an internal 10GBT module620, which can be provided to communicate with other internal components of the storage array. As noted above, expansion ports324aand324b, and expansion ports326aand326b, are further integrated between the compute modules102aand102b.

The specific configuration of these example compute modules102aand102bcan change depending on the design power of the system, based on technology improvements, based on necessity for additional connections to the internal bus, and other design requisites. However, embodiments of the present design allow for each of the connections between the compute modules102aand102bto be routed to the various PCIe lanes that will be coupled directly to the I/O mid-plane104that are prewired to the specific locations of connectors380and382for receiving specific protocol bridge modules106, depending on the drive configuration of the storage array.

FIG. 7illustrates a detailed diagram of motherboard200, which may be integrated into a storage array, in accordance with one embodiment. In this example, it is possible to define a storage array that is a 4U storage array. In the illustrated front view of the 4U storage array, it is shown that 24 3.5″ drive bays can be provided, which may be a U.2 connector compliant. As mentioned above, reference to the U.2 connector is only by way of example, and other connectors having or providing similar functionality may be used. An aspect of the described embodiments is that the I/O mid-plane104has pre-routed PCIe lanes integrated directly into the motherboard200, which interfaces the compute modules102aand102bwith the bridge module interconnect105.

This illustration ofFIG. 7also shows a fully populated bridge module interconnect105, which includes both NVME and SAS bridge boards302and304. However, as mentioned above, in a functional configuration the motherboard is preferably populated with either the SAS bridge boards304or the NVME bridge boards302. This illustration also shows that bridge aboard module108has eight (8) routed PCIe lanes coupled in a fixed configuration to four (4) NVME SSDs and storage drives130b. In one embodiment, these NVME slots can be used for right buffer and/or hybrid flash cache operations.

For example, if the protocol bridge modules106that are populated are only the SAS bridge boards304, the bridge board module108can still provide the eight (8) PCIe lanes to the dedicated NVME drives. In other embodiments, it is possible to omit the bridge board module108, if the dedicated PCIe lanes are not desired. Further, it is possible to design the bridge board module108to either be fixed on the motherboard200, or connected to the motherboard200in a similar way that the protocol bridge modules106are connected.

FIG. 8illustrates an example of the motherboard200, having been configured with SAS bridge boards304, and omitting the NVME boards302. The reason for omitting the NVME boards302is that this storage configuration will be designed for storage drives130a, having a SAS interposer, which can communicate with SATA SSD drives. For more reference regarding the use of a SAS interposer, reference may be made to U.S. patent application Ser. No. 14/949,837, entitled “Storage Array Having Multi-Drive Sled Assembly,” filed on Nov. 23, 2015, which is herein incorporated by reference. As mentioned above, the fixed bridge, referred to as the bridge board module108is still able to route to PCIe lanes to the four NVME SSD drives, which are part of NVME drives130b.

FIG. 9illustrates another configuration of motherboard200of a storage array, in accordance with one embodiment. This illustration shows that the same SAS bridge boards304are maintained, but the drive slots of all the storage drives130ahave been occupied with dual SATA SSDs, which are connected through the SAS interposer's to the connectors314that couple to the connectors114of the storage mid-plane110. Thus, it is possible to populate all of the drive bays of the storage array and not connect any of the NVME drives130b, since the drive connectors114can meet to any type of drive connector314pending on the protocol, which utilize the specific pins for the respective protocols.

FIG. 10illustrates another embodiment of the motherboard200where the bridge module interconnect105is populated with NVME bridge boards302, instead of the SAS bridge boards304. This simple connection of the NVME bridge boards302to the bridge module interconnect105, will therefore enable communication with storage drives130b, which include SSDs that communicate using the NVME protocol. In this example, all 24 drive bays, which utilize U.2 compliant connectors for interfacing between drive connectors114and connectors314(discussed inFIGS. 5A-5Dabove), will enable the specific storage drives to communicate with the storage mid-plane110.

FIG. 11illustrates another embodiment of the motherboard200, where SAS bridge boards304have been connected to the bridge module interconnect105, so as to connect and communicate with storage drives130d. In this example, the construction of the storage array will enable a 2U form factor that allows for 36 U.2 SSDs. The storage drives130dare shown to be SAS protocol solid-state drives (SSD's). This configuration has been shown to illustrate that the storage mid-plane110and the I/O mid-plane104will remain fully integrated and routed, and the only modifications required will be to insert the proper bridge board into the motherboard200and insert the desired type of storage drives that communicate with connectors114.

FIG. 12illustrates yet another example where the motherboard200has been modified to receive NVME bridge boards302, to enable the construction of a storage array that can hold 36 U.2 SSDs in a 2U form factor. The illustration ofFIG. 12is similar to the embodiment ofFIG. 11. However, by simply changing the bridge boards connected to the bridge module interconnect105, is possible to instantly allow for different types of storage drives of different protocol configurations to be connected to the motherboard200by way of the connectors114that couple to the storage mid-plane110. In this example, it is shown that 36 NVME storage drives130ehave been coupled to the storage mid-plane110, and are provided with communication that has been pre-integrated and wired to the connectors that allow connection of the NVME bridge boards302.

These examples were provided to show the substantial advancement in the design and packaging of storage arrays. By simple modifications to what is plugged in to the bridge module interconnect105, the personality (i.e., functionality) of the storage array is instantly changed to a specific type of storage array that can handle different types of storage drive protocols. The integrated design within the I/O mid-plane104and the storage mid-plane110enable for a consistent motherboard design that can integrate to the types of storage drive protocols being utilized. The I/O mid-plane104further provides a simplified connection of integrated PCIe lanes, which remove the complexity of designing compute modules specific for different connections to different protocols. In accordance with the embodiments described herein, designers of storage array motherboards and infrastructure can simply design a system by plugging in different bridge boards that are consistent with the protocol of the storage drives that are to be connected to the storage array.

As used herein, the NVME protocol is also referred to by the acronym NVMe. Generally, an NVME protocol is a communications interface developed for SSDs. For example, the NVME protocol is designed to take advantage of the unique properties of pipeline-rich, random access, memory-based storage.

One or more processing functions can also be defined by computer readable code on a non-transitory computer readable storage medium. The non-transitory computer readable storage medium is any non-transitory data storage device that can store data, which can thereafter be read by a computer system. For example, the processing operations performed by any one of the modules may include computer readable code, which is or can be executed. The code can be, in some configurations, embodied in one or more integrated circuit chips that execute instructions of the computer readable code. In some examples, the integrated circuit chips may be in the form of general processors or special purpose integrated circuit devices. In some cases, the processing may access memory for storage in order to render one or more processing operations.

By way of example, the storage controller of the storage array can include a processor, one or more memory systems and buses for exchanging data when processing storage access operations. In some embodiments, the storage array may include redundant systems, such as an active controller and a standby controller. The active controller operates as the primary computing system for the storage array, while the standby controller is ready to take over during a failover operation. In each case, a controller, e.g., storage controller is configured to interface with connections and electronics of a backplane to interface to the many storage drives of the storage array. In this case, the storage array101includes many sled assemblies, of which may include one or two SSD drives. Furthermore, the storage array may be a hybrid system, wherein the both HDDs and SSDs make up the storage capacity of the storage array. These examples are simply provided to illustrate the integrated computing nature of a storage array and the tight interchange needed with drives, e.g., HDDs and SSD, which forms the physical storage of the storage array. Still further, other examples of non-transitory computer readable storage medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes and other optical and non-optical data storage devices. The non-transitory computer readable storage medium can include computer readable storage medium distributed over a network-coupled computer system so that the computer readable code is stored and executed in a distributed fashion.