Organic light emitting diode display device and method of fabricating the same

An organic light emitting diode display device comprises a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed on the first semiconductor layer. The device further includes a storage capacitor including a first capacitor electrode electrically coupled to a drain electrode of the driving thin film transistor, a buffer layer formed on the first capacitor electrode, a second semiconductor layer formed on the buffer layer, and a second capacitor electrode formed on the second semiconductor layer and electrically coupled to a gate electrode of the driving thin film transistor. The device also includes an organic light emitting diode connected to the drain electrode of the driving transistor. The gate insulating layer has at least one hole in a region where the gate insulating layer overlaps the second semiconductor layer, thereby exposing the second semiconductor layer to the second capacitor electrode.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims the priority benefit of Korean Patent Application No. 10-2013-0161519 filed in the Republic of Korea on Dec. 23, 2013, which is hereby incorporated by reference in their entirety.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to an organic light emitting diode display device, and more particularly, to an organic light emitting diode display device that increases capacitance of a storage capacitor and a method of fabricating the same.

2. Discussion of the Related Art

Recently, flat panel displays have been widely developed and applied to various fields because of their thin profile, light weight, and low power consumption.

Among the flat panel displays, organic light emitting diode (OLED) display devices, which may be referred to as organic electroluminescent display devices, emit light during loss of electron-hole pairs formed by injecting charges into a light emitting layer between a cathode for injecting electrons and an anode for injecting holes.

The OLED display devices include a flexible substrate such as plastic; because they are self-luminous, the OLED display devices have excellent contrast ratios; the OLED display devices have a response time of several micro seconds, and there are advantages in displaying moving images; the OLED display devices have wide viewing angles and are stable under low temperatures; since the OLED display devices are driven by a low voltage of direct current (DC) 5V to 15V, it is easy to design and manufacture driving circuits; and the manufacturing processes of the OLED display device are simple since only deposition and encapsulation steps are required.

The OLED display devices are classified into a passive matrix type and an active matrix type according to driving methods. Active matrix type display devices have been widely used because of their low power consumption, high definition and large-sized possibility.

FIG. 1is a circuit diagram of one pixel region of an OLED display device according to the related art.

As shown inFIG. 1, an OLED display device includes a gate line GL, a data line DL, a switching thin film transistor Ts, a driving thin film transistor Td, a storage capacitor Cst and a light emitting diode De. The gate line GL and the data line DL cross each other to define a pixel region P. The switching thin film transistor Ts, the driving thin film transistor Td, the storage capacitor Cst and the light emitting diode De are formed in the pixel region P.

More particularly, a gate electrode of the switching thin film transistor Ts is connected to the gate line GL and a source electrode of the switching thin film transistor Ts is connected to the data line DL. A gate electrode of the driving thin film transistor Td is connected to a drain electrode of the switching thin film transistor Ts, and a source electrode of the driving thin film transistor Td is connected to a high voltage supply VDD. An anode of the light emitting diode De is connected to a drain electrode of the driving thin film transistor Td, and a cathode of the light emitting diode De is connected to a low voltage supply VSS. The storage capacitor Cst is connected to the gate electrode and the drain electrode of the driving thin film transistor Td.

In operation of the OLED display device, when the switching thin film transistor Ts is turned on by a gate signal applied through the gate line GL, a data signal from the data line DL is applied to the gate electrode of the driving thin film transistor Td and an electrode of the storage capacitor Cst through the switching thin film transistor Ts. When the driving thin film transistor Td is turned on by the data signal, an electric current flowing through the light emitting diode De is controlled, thereby displaying an image. The light emitting diode De emits light due to the current supplied through the driving thin film transistor Td from the high voltage supply VDD.

Namely, the amount of the current flowing through the light emitting diode De is proportional to the magnitude of the data signal, and the intensity of light emitted by the light emitting diode De is proportional to the amount of the current flowing through the light emitting diode De. Thus, the pixel regions P show different gray levels depending on the magnitude of the data signal, and as a result, the OLED display device displays an image.

The storage capacitor Cst maintains charges corresponding to the data signal for a frame when the switching thin film transistor Ts is turned off. Accordingly, even if the switching thin film transistor Ts is turned off, the storage capacitor Cst allows the amount of the current flowing through the light emitting diode De to be constant and the gray level shown by the light emitting diode De to be maintained until a next frame.

To do this, capacitance of the storage capacitor Cst needs to be over a predetermined value. However, to implement high definition display devices, the size of the pixel region P decreases, and an area for the storage capacitor Cst also decreases. Therefore, the capacitance of the storage capacitor Cst is lowered. If the area for the storage capacitor Cst is increased, an effective emission area and an area for a compensation circuit are restricted. Accordingly, it is difficult to obtain sufficient capacitance of the storage capacitor Cst.

SUMMARY

An object of the present disclosure is to provide an organic light emitting diode display device and a method of fabricating the same that increase capacitance of a storage capacitor and improve the aperture ratio and brightness.

Another object of the present disclosure is to provide organic light emitting diode display device and a method of fabricating the same that increase design margins.

Additional features and advantages of these embodiments will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments. The objectives and other advantages will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, according to one or more embodiments, an organic light emitting diode display device includes a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed on the first semiconductor layer, a gate electrode formed on the gate insulating layer, a source electrode, and a drain electrode, the source electrode and the gate electrode formed co-planar with the gate electrode on a same side with respect to the gate insulating layer. The device further comprises a storage capacitor including a first capacitor electrode electrically coupled to the drain electrode of the driving thin film transistor, a buffer layer formed on the first capacitor electrode, a second semiconductor layer formed on the buffer layer, and a second capacitor electrode formed on the second semiconductor layer and electrically coupled to the gate electrode of the driving thin film transistor The device additionally includes an organic light emitting diode (OLED) connected to the drain electrode of the driving thin film transistor and configured to emit light by current driven through the OLED by the driving thin film transistor. In one or more embodiments, the gate insulating layer has at least one hole in a region where the gate insulating layer overlaps the second semiconductor layer, thereby exposing the second semiconductor layer to the second capacitor electrode.

In another aspect, a method of fabricating an organic light emitting diode display device includes forming a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed on the first semiconductor layer, a gate electrode formed on the gate insulating layer, a source electrode, and a drain electrode, the source electrode and the gate electrode formed co-planar with the gate electrode on a same side with respect to the gate insulating layer; forming a storage capacitor including a first capacitor electrode electrically coupled to the drain electrode of the driving thin film transistor, a buffer layer formed on the first capacitor electrode, a second semiconductor layer formed on the buffer layer, and a second capacitor electrode formed on the second semiconductor layer and electrically coupled to the gate electrode of the driving thin film transistor; and forming an organic light emitting diode (OLED) connected to the drain electrode of the driving thin film transistor and configured to emit light by current driven through the OLED by the driving thin film transistor. In one or more embodiments, the buffer layer, the second semiconductor layer and the gate insulating layer are formed subsequent to forming of the first capacitor electrode and prior to forming of the second capacitor electrode. In one or more embodiments, forming the gate insulating layer includes forming at least one hole in the gate insulating layer in a region where the gate insulating layer overlaps the second semiconductor layer by patterning the gate insulating layer to expose the second semiconductor layer through the gate insulating layer to the second capacitor electrode.

In another aspect, a method of fabricating an organic light emitting diode display device includes forming a first capacitor electrode over a substrate; forming a buffer layer over the first capacitor electrode; forming a first semiconductor layer and a second semiconductor layer over the buffer layer; and forming a gate insulating layer over the first semiconductor layer and the second semiconductor layer. The method also comprises forming at least one hole in the gate insulating layer in a region where the gate insulating layer overlaps the second semiconductor layer by patterning the gate insulating layer, the hole exposing the second semiconductor layer through the gate insulating layer. The method further comprises forming a gate electrode on the gate insulating layer and forming a second capacitor electrode on the second semiconductor layer in the hole of the gate insulating layer, the second capacitor electrode being electrically coupled to the gate electrode. The method additionally comprises forming an inter insulating layer over the gate electrode and the second capacitor electrode; forming source and drain electrodes over the inter insulating layer, the drain electrode being electrically coupled to the first capacitor electrode; forming a passivation layer over the source and drain electrodes; and sequentially forming a first OLED electrode, an organic light emitting layer and a second OLED electrode over the passivation layer.

In one or more embodiments, an organic light emitting display (OLED) device comprises a thin film transistor that includes a first semiconductor layer on a buffer layer, a gate insulating layer on the first semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The device further comprises a first capacitor electrically coupled between the gate electrode and either the drain electrode or the source electrode of the thin film transistor, the first capacitor formed in a second region of the substrate, the first capacitor including a first capacitor electrode, the buffer layer on the first capacitor electrode, a second semiconductor layer on the buffer layer, and a second capacitor electrode on the second semiconductor layer. In one or more embodiments, the second semiconductor layer is thinner than the gate insulating layer.

In one or more embodiments, an organic light emitting display (OLED) device comprises a thin film transistor formed in a first region of a substrate; an OLED formed in a second region of the substrate; a first capacitor coupled between a gate electrode and a drain electrode of the thin film transistor, the first capacitor formed at least partially in the second region of the substrate; and a second capacitor adjacent to the first capacitor and formed at least partially in the second region of the substrate, the second capacitor coupled between the gate and the drain electrodes of the thin film transistor and connected in parallel with the first capacitor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the preferred embodiment, examples of which are illustrated in the accompanying drawings.

FIG. 2is a cross-sectional view of an OLED display device according to an embodiment of the present invention.FIG. 2shows one pixel region.

InFIG. 2, a light-blocking layer112and a first capacitor electrode116of a conductive material such as metal are formed on an insulating substrate110.

A buffer layer120of an insulating material is formed on the light-blocking layer112and the first capacitor electrode116substantially all over the substrate110.

A first oxide semiconductor layer122and a second oxide semiconductor layer126of an oxide semiconductor material are formed on the buffer layer120. The first oxide semiconductor layer122is disposed over the light-blocking layer112, and the second oxide semiconductor layer126is disposed over the first capacitor electrode116. The first oxide semiconductor layer122has a wider width than the light-blocking layer112, and a central portion of the first oxide semiconductor layer122overlaps the light-blocking layer112. The second oxide semiconductor layer126overlaps the first capacitor electrode116. At this time, the second oxide semiconductor layer126has a smaller area than the first capacitor electrode116, and a portion of the first capacitor electrode116does not overlap the second oxide semiconductor layer126.

A gate insulating layer130of an insulating material is formed on the first oxide semiconductor layer122and the second oxide semiconductor layer126substantially all over the substrate110. The gate insulating layer139has a hole130aexposing the second oxide semiconductor layer126and a capacitor contact hole130bexposing the first capacitor electrode116. The capacitor contact hole130bis also formed in the buffer layer120under the gate insulating layer130. Meanwhile, although not shown in the figure, the gate insulating layer130and the buffer layer120have a gate contact hole exposing the light-blocking layer112.

A gate electrode132, a connection pattern134and a second capacitor electrode136of a conductive material such as metal are formed on the gate insulating layer130. In addition, a gate line (not shown) is formed on the gate insulating layer130. The gate line extends in a first direction.

The gate electrode132overlaps the light-blocking layer112and has a narrower width than the light-blocking layer112. Although not shown in the figure, the gate electrode132contacts the light-blocking layer112through the gate contact hole. Additionally, the connection pattern134contacts the first capacitor electrode116through the capacitor contact hole130b. The second capacitor electrode136is spaced apart from the connection pattern134, and the second capacitor electrode136overlaps the first capacitor electrode116and contacts the second oxide semiconductor layer126through the hole130a. Although not shown in the figure, the second capacitor electrode136is connected to the gate electrode132.

An inter insulating layer140of an insulating material is formed on the gate electrode132, the connection pattern134and the second capacitor electrode136substantially all over the substrate110. The inter insulating layer140includes first and second contact holes140aand140bexposing top surfaces of both sides of the first oxide semiconductor layer122. The first and second contact holes140aand140bare spaced apart from the gate electrode132, and the first and second contact holes140aand140bare also formed in the gate insulating layer130. In addition, the inter insulating layer140has a third contact hole140aexposing the connection pattern134.

A source electrode152, a drain electrode154and a third capacitor electrode156of a conductive material such as metal are formed on the inter insulating layer140. In addition, a data line (not shown) a power supply line (not shown) are formed on the inter insulating layer140. The data line and the power supply line extend in a second direction. The data line crosses the gate line to define a pixel region.

The source and drain electrodes152and154are spaced apart from each other with respect to the gate electrode132. The source and drain electrodes152and154contact both sides of the first oxide semiconductor layer122through the first and second contact holes140aand140b, respectively. The source and drain electrodes152and154are spaced apart from the gate electrode132and overlap the light-blocking layer112. The drain electrode154is connected to the third capacitor electrode156and contacts the connection pattern134through the third contact hole140c. In the meantime, the third capacitor electrode156overlaps the second capacitor electrode136.

Here, the drain electrode154may directly contact the first capacitor electrode116. Namely, the capacitor contact hole130aand the connection pattern134may be omitted, and the third contact hole140cmay be formed in the inter insulating layer140, the gate insulating layer130and the buffer layer120to expose the first capacitor electrode116. The drain electrode154may contact the first capacitor electrode116through the third contact hole140c.

Meanwhile, the first capacitor electrode116and the second capacitor electrode136form a first capacitor C1with the buffer layer120and the second oxide semiconductor layer126interposed therebetween as a dielectric. The second capacitor electrode136and the third capacitor electrode156form a second capacitor C2with the inter insulating layer140interposed therebetween as a dielectric. The first capacitor C1and the second capacitor C2are connected to each other in parallel to constitute a storage capacitor. In other words, in one or more embodiments, the first capacitor electrode116and the third capacitor electrode156are both connected to either a source152or a drain electrode154of the thin film transistor through a common connection pattern134through the third contact hole140c. Both the gate insulating layer130and the inter insulating layer140absent in a vicinity of the connection pattern134.

A passivation layer160of an insulating material is formed on the source and drain electrodes152and154and the third capacitor electrode156substantially all over the substrate110. The passivation layer160has a flat top surface and has a drain contact hole160aexposing the drain electrode154. In the figure, although the drain contact hole160ais formed directly over the second contact hole140b, the drain contact hole160amay be spaced apart from the second contact hole140b.

A first electrode172of a conductive material having relatively high work function is formed on the passivation layer160. The first electrode172is disposed in each pixel region and contacts the drain electrode154through the drain contact hole160a. Here, the first electrode172may be formed of a transparent conductive material.

A bank layer180of an insulating material is formed on the first electrode172. The bank layer180covers edges of the first electrode172and exposes a central portion of the first electrode172.

An organic light emitting layer182of an organic material is formed on the first electrode172exposed by the bank layer180. The organic light emitting layer182may have a multi-layered structure of a hole transporting layer, a light-emitting material layer, and an electron transporting layer sequentially layered on the first electrode172. The organic light emitting layer182may further include a hole injecting layer under the hole transporting layer and an electron injecting layer on the electron transporting layer.

A second electrode192of a conductive material having relatively low work function is formed on the organic light emitting layer182substantially all over the substrate110. The second electrode192may be formed of an opaque metallic material.

The first electrode172, the organic light emitting layer182and the second electrode192constitute an organic light emitting diode De. The first electrode172functions as an anode, and the second electrode192serves as a cathode. Here, the OLED display device may be a bottom emission type in which light from the organic light emitting layer182is outputted to the outside through the first electrode172.

In the meantime, the gate electrode132, the first oxide semiconductor layer122, the source electrode152and the drain electrode154constitute a thin film transistor. The thin film transistor may have a top gate-type coplanar structure in which the first oxide semiconductor layer122as an active layer is disposed at the bottom, the gate electrode132is disposed at the top, and the gate electrode132and the source and drain electrodes152and154are disposed at a side of the oxide semiconductor layer122.

In the present embodiments, since the light-blocking layer112is formed under the first oxide semiconductor layer122, light from the outside or light from the organic light emitting layer182is prevented from reaching the first oxide semiconductor layer122. The first oxide semiconductor layer122is prevented from being degraded by light, and a lifetime of the thin film transistor is prevented from being shortened. Moreover, the light-blocking layer112is electrically connected to the gate electrode132at the top and is used as an additional gate electrode. Thus, the thin film transistor of the present invention has a double gate structure and has further improvement in current characteristics.

The thin film transistor ofFIG. 2corresponds to a driving thin film transistor of an OLED display device. Although not shown in the figure, a switching thin film transistor, which has the same structure as the driving thin film transistor, is formed over the substrate110.

In addition, a sensing thin film transistor having the same structure as the driving thin film transistor may be further formed.

Here, a gate electrode of the switching thin film transistor is connected to the gate line, and a source electrode of the switching thin film transistor is connected to the data line. The gate electrode132of the driving thin film transistor is connected to a drain electrode of the switching thin film transistor, and the source electrode152of the driving thin film transistor is connected to the power supply line.

As stated above, the drain electrode154of the driving thin film transistor is connected to the first electrode172of the organic light emitting diode De, and the drain electrode154of the driving thin film transistor is also connected to the first capacitor electrode116and the third capacitor electrode156of the storage capacitor. The gate electrode132of the driving thin film transistor is connected to the second capacitor electrode136of the storage capacitor.

The positions and names of the source electrode152and the drain electrode154of the driving thin film transistor are determined according to carriers, and the positions and names of the source electrode152and the drain electrode154may be changed to each other.

In the meantime, as mentioned above, the storage capacitor of the present invention includes the first and second capacitors C1and C2connected in parallel and has larger capacitance than a capacitor having the same area as the storage capacitor of the present invention. At this time, to decrease a distance between the first capacitor electrode116and the second capacitor electrode136, the gate insulating layer130between the first capacitor electrode116and the second capacitor electrode136is removed, and the buffer layer120is prevented from being etched by using the second oxide semiconductor layer126as an etching-prevention layer. Since the second oxide semiconductor layer126has a thinner thickness than the gate insulating layer130, the distance between the first and second capacitor electrodes116and136decreases, and the capacitance of the first capacitor C1further increases.

Accordingly, the area for the storage capacitor can be decreased by an increase in the capacitance. The effective emission area where light from the organic light emitting layer182is emitted increases in the bottom emission type OLED display device, and brightness of the display device increases.

The structure of the storage capacitor of the present invention may be applied to a top emission type OLED display device in addition to the bottom emission type OLED display device. That is, the OLED display device may be a top emission type where the first electrode172is formed of an opaque conductive material or includes a transparent conductive layer and a reflective layer under the transparent conductive layer, the second electrode182transmits light, and light from the organic light emitting layer182is outputted to the outside through the second electrode192. At this time, since the area for the storage capacitor decreases by an increase in the capacitance of the first capacitor C1, other thin film transistors and capacitors for compensation can be added, and design margins increase.

Hereinafter, a method of fabricating an OLED display device according to an embodiment of the present disclosure with reference to accompanying drawings.

FIGS. 3A to 3Jare cross-sectional views of an OLED display device in steps of fabricating the display device according to an embodiment of the present disclosure.

InFIG. 3A, a first conductive material layer (not shown) is formed on an insulating substrate110by depositing a conductive material such as metal by a sputtering method, for example, and the first conductive material layer is selectively removed through a photolithographic process using a mask, thereby forming a light-blocking layer112and a first capacitor electrode116.

Here, the insulating substrate110may be a glass substrate or a plastic substrate. The light-blocking layer112and the first capacitor electrode116may be formed of at least one of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), nickel (Ni), tungsten (W), and an alloy thereof.

InFIG. 3B, a buffer layer120is formed on the light-blocking layer112and the first capacitor electrode116by depositing an insulating material substantially all over the substrate110. The buffer layer120may be formed of an inorganic insulating material such as silicon oxide (SiO2).

Next, an oxide semiconductor layer (not shown) is formed on the buffer layer120by depositing an oxide semiconductor material, and the oxide semiconductor layer is selectively removed through a photolithographic process using a mask, thereby forming a first oxide semiconductor layer122over the light-blocking layer112and a second oxide semiconductor layer126over the first capacitor electrode116. Here, the first oxide semiconductor layer122has a wider width than the light-blocking layer112, and a central portion of the first oxide semiconductor layer122overlaps the light-blocking layer112. Meanwhile, the second oxide semiconductor layer126overlaps the first capacitor electrode116. At this time, the second oxide semiconductor layer126has a smaller area than the first capacitor electrode116, and a portion of the first capacitor electrode116does not overlap the second oxide semiconductor layer126.

In one or more embodiments, the second semiconductor layer126and the first semiconductor layer122are formed in a same process with a same thickness. The first and second oxide semiconductor layers122and126may be formed of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium oxide (IGO), or indium aluminum zinc oxide (IAZO).

InFIG. 3C, a gate insulating layer130is formed on the first and second oxide semiconductor layers122and126by depositing an insulating material substantially all over the substrate110by a chemical vapor deposition method, for example. The gate insulating layer130may be formed of an inorganic insulating material such as silicon oxide (SiO2).

Next, the gate insulating layer130and the buffer layer120thereunder are selectively removed through a photolithographic process using a mask, thereby forming a hole130aexposing the second oxide semiconductor layer126, a capacitor contact hole130bexposing the first capacitor electrode116, and a gate contact hole (not shown) exposing the light-blocking layer112. Here, the hole130ais formed only in the gate insulating layer130, and the capacitor contact hole130band the gate contact hole are formed in the gate insulating layer130and the buffer layer120. In other words, forming the gate insulating layer includes forming at least one hole (e.g.,130a) in the gate insulating layer130in a region where the gate insulating layer130overlaps the second semiconductor layer126, by patterning the gate insulating layer130.

InFIG. 3D, a second conductive material layer (not shown) is formed on the gate insulating layer130by depositing a conductive material such as metal by a sputtering method, for example, and the second conductive material layer is selectively removed through a photolithographic process using a mask, thereby forming a gate electrode132, a connection pattern134, a second capacitor electrode136, and a gate line (not shown).

The gate electrode132has a narrower width than the light-blocking layer112and overlaps the light-blocking layer112. The gate electrode132contacts the light-blocking layer112through the gate contact hole (not shown). The connection pattern134contacts the first capacitor electrode116through the capacitor contact hole130b. The second capacitor electrode136is spaced apart from the connection pattern134, and the second capacitor electrode136overlaps the first capacitor electrode116and contacts the second oxide semiconductor layer126through the hole130a. In other words, the second semiconductor layer126is exposed through the gate insulating layer130(at hole130a) to the second capacitor electrode136. In such embodiments, the second semiconductor layer126is formed thinner than the gate insulating layer130. Although not shown in the figure, the second capacitor electrode136is connected to the gate electrode132, and the gate line extends in a first direction.

The gate electrode132, the connection pattern134, the second capacitor electrode136, and the gate line may be formed of at least one of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), nickel (Ni), tungsten (W), and an alloy thereof.

InFIG. 3E, an inter insulating layer140is formed on the gate electrode132, the connection pattern134, the second capacitor electrode136, and the gate line by depositing or applying an insulating material substantially all over the substrate110, and the inter insulating layer140is selectively removed through a photolithographic process using a mask, thereby forming first and second contact holes140aand140band a third contact hole140c. The first and second contact holes140aand140bexpose top surfaces of both sides of the first oxide semiconductor layer122, respectively, and the third contact hole140cexposes the connection pattern134. Although the third contact hole140cis disposed directly over the capacitor contact hole130b, the third contact hole140cmay be spaced apart from the capacitor contact hole130b.

The inter insulating layer140may be formed of an inorganic insulating material such as silicon oxide (SiO2) and silicon nitride (SiNx) or an organic insulating material such as benzocyclobutene and photo acryl.

Next, inFIG. 3F, a third conductive material layer (not shown) is formed on the inter insulating layer140by depositing a conductive material such as metal by a sputtering method, for example, and the third conductive material layer is selectively removed through a photolithographic process using a mask, thereby forming source and drain electrodes152and154, a third capacitor electrode156, a data line (not shown), and a power supply line (not shown).

The source and drain electrodes152and154are spaced apart from each other with respect to the gate electrode132. The source and drain electrodes152and154contact both sides of the first oxide semiconductor layer122through the first and second contact holes140aand140b, respectively. In addition, the source and drain electrodes152and154are spaced apart from the gate electrode132and overlap the light-blocking layer112. The drain electrode154is connected to the third capacitor electrode156and contacts the connection pattern134through the third contact hole140c. In the meantime, the third capacitor electrode156overlaps the second capacitor electrode136. The data line and the power supply line extend in a second direction. The data line crosses the gate line to define a pixel region.

As stated above, the drain electrode154may directly contact the first capacitor electrode116. Namely, the capacitor contact hole130aand the connection pattern134may be omitted, and the third contact hole140cmay be formed in the inter insulating layer140, the gate insulating layer130and the buffer layer120to expose the first capacitor electrode116. The drain electrode154may contact the first capacitor electrode116through the third contact hole140c.

The source and drain electrodes152and154, the third capacitor electrode156, the data line and the power supply line may be formed of at least one of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), nickel (Ni), tungsten (W), and an alloy thereof.

InFIG. 3G, a passivation layer160is formed on the source and drain electrodes152and154, the third capacitor electrode156, the data line and the power supply line by depositing or applying an insulating material substantially all over the substrate110, and the passivation layer160is selectively removed through a photolithographic process using a mask, thereby forming a drain contact hole160aexposing the drain electrode154. The drain contact hole160ais formed directly over the second contact hole140b. Alternatively, the drain contact hole160amay be spaced apart from the second contact hole140b.

The passivation layer160may be formed of an inorganic insulating material such as silicon oxide (SiO2) and silicon nitride (SiNx) or an organic insulating material such as benzocyclobutene and photo acryl. Beneficially, the passivation layer160may be formed of an organic insulating material to flatten a top surface thereof.

Next, inFIG. 3H, a first electrode material layer (not shown) is formed on the passivation layer160by depositing a conductive material having relatively high work function by a sputtering method, for example, and the first electrode material layer is selectively removed through a photolithographic process using a mask, thereby forming a first electrode172. The first electrode172is disposed in each pixel region and is connected to the drain electrode154through the drain contact hole160a.

The first electrode172may be formed of a transparent conductive material such as indium tin oxide and indium zinc oxide.

InFIG. 3I, a bank material layer (not shown) is formed on the first electrode172by depositing or applying an insulating material, and the bank material layer is selectively removed through a photolithographic process using a mask, thereby forming a bank layer180. The bank layer180covers edges of the first electrode172and exposes a central portion of the first electrode172.

Meanwhile, although not shown in the figure, a spacer may be further formed on the bank layer180.

InFIG. 3J, an organic light emitting layer182is formed on the first electrode172exposed by the bank layer180by selectively depositing an organic material over the substrate110including the bank layer180by an evaporation method, for example. The organic light emitting layer182may have a multi-layered structure of a hole transporting layer, a light-emitting material layer, and an electron transporting layer sequentially layered on the first electrode172. The organic light emitting layer182may further include a hole injecting layer under the hole transporting layer and an electron injecting layer on the electron transporting layer.

Next, a second electrode192is formed on the organic light emitting layer182by depositing a conductive material having relatively low work function substantially all over the substrate110by a sputtering method, for example.

The second electrode192may be formed of an opaque metallic material such as aluminum and chromium.

The first electrode172, the organic light emitting layer182and the second electrode192constitute an organic light emitting diode De. The first electrode172functions as an anode, and the second electrode192serves as a cathode. Here, the OLED display device may be a bottom emission type in which light from the organic light emitting layer182is outputted to the outside through the first electrode172. Alternatively, the OLED display device may be a top emission type where a reflective layer is further formed under the first electrode172and a thickness of the second electrode182is adjusted to transmit light.

In the present invention, a storage capacitor is formed by first and second capacitors C1and C2, which are constituted by the first, second and third capacitor electrodes116,136and156and are connected to each other in parallel. Here, when the gate contact hole (not shown) and the storage contact hole130bare formed, the gate insulating layer130between the first capacitor electrode116and the second capacitor electrode136is removed using the second oxide semiconductor layer126as an etching prevention layer. Thus, without an increase in a process, since a thickness of the second oxide semiconductor layer126is thinner than the gate insulating layer130, a distance between the first and second capacitor electrodes116and136decreases, and the capacitance of the first capacitor C1increases. Therefore, an area for the storage capacitor can be decreased by the increase in the capacitance. Accordingly, in the bottom emission type OLED display device, the effective emission area, and brightness of the display device increases. In the top emission type OLED display device, other thin film transistors and capacitors for compensation can be added, and design margins increase.

In the embodiment of the present invention, the thin film transistor includes oxide semiconductor as an active layer. Alternatively, the thin film transistor may include low temperature polycrystalline silicon (LTPS) as an active layer. In this case, a step of doping impurities may be further performed, and the gate insulating layer130and the buffer layer120may be formed of an inorganic insulating material such as silicon nitride (SiNx) in addition to silicon oxide (SiO2).

Meanwhile, in the embodiment of the present disclosure, the storage capacitor has one hole130aexposing the second oxide semiconductor layer126. Alternatively, the number and size of holes and a distance between adjacent holes may be varied. In other words, in one or more embodiments, the gate insulating layer130has a plurality of spatially separated holes in the region where the storage capacitor is formed, between the second capacitor electrode136and the second semiconductor layer126to expose the second semiconductor layer126to the second capacitor electrode136. Furthermore, the gate insulating layer130extends partially into a region between the second capacitor electrode136and the second semiconductor layer126to cover a part of the second semiconductor layer126.

FIGS. 4A to 4Care views of schematically illustrating holes of a storage capacitor according to an embodiment of the present invention.FIGS. 4A to 4Cshow the number and size of holes and the distance between adjacent holes with respect to an area of the storage capacitor.

InFIG. 4A, the storage capacitor may include a hole op1, and the hole op1may have a size corresponding to electrodes of the storage capacitor. For example, the size of the hole op1may be 34 micrometers by 84 micrometers.

InFIG. 4B, the storage capacitor may include a plurality of holes op2. For example, the number of holes op2may be 21, the size of each hole op2may be 8 micrometers by 6 micrometers, and the holes op2may be disposed with a distance of about 6 micrometers therebetween.

InFIG. 4C, the storage capacitor may include a plurality of holes op3. For example, the number of holes op3may be 55, the size of each hole op3may be 3 micrometers by 3 micrometers, and the holes op3may be disposed with a distance of about 5 micrometers therebetween.

For instance, in a reference case that the storage capacitor does not include a hole, the capacitance of the storage capacitor is 512.6 fF. InFIG. 4Awhere the storage capacitor includes the hole op1, the capacitance is 723.8 fF and increases by about 141.2% as compared with the reference case. InFIG. 4Bwhere the storage capacitor includes the holes op2, the capacitance is 695 fF and increases by about 135.58% as compared with the reference case. InFIG. 4Cwhere the storage capacitor includes the holes op3, the capacitance is 733.8 fF and increases by about 143.15% as compared with the reference case.

Here, the holes op3ofFIG. 4Chave a smaller total area than the hole op1ofFIG. 4A, and the capacitance inFIG. 4Cis larger than the capacitance inFIG. 4Abecause of a fringe field effect at edges of the holes op3.

Accordingly, the storage capacitor with the hole op1or holes op2or op3can have the capacitance increased by about 35% to about 43% in comparison to the storage capacitor without a hole.

In the present invention, by forming the hole or holes having various sizes, numbers and distances therebetween, the capacitance of the storage capacitor can be increased.