Compensation of environmental drift by tracking switched capacitor impedance versus resistor impedance

A method may include, for a signal path comprising a passive antialiasing filter sampled by a switched-capacitor front-end, monitoring a change of a first impedance of a resistor of the passive antialiasing filter responsive to an environmental condition relative to a second impedance of a switched capacitor of the switched-capacitor front end and compensating the signal path for a change in gain of the signal path resulting from the change of the first impedance.

FIELD OF DISCLOSURE

The present disclosure relates in general to methods and systems for calibrating for temperature and other drift that may occur in an antialiasing filter.

BACKGROUND

Delta-sigma modulators are typically used in electronic circuits such as analog-to-digital converters (ADCs). Often, such ADCs employ an antialiasing filter to filter an analog input signal that may be sampled by a sampling network at the input of the delta-sigma modulator for conversion into an equivalent digital signal by the ADC. An example of such a sampling network is a switched capacitor circuit.

A resistive antialiasing filter may be directly loaded by a switched capacitor sampling front-end, with equivalent resistance of the switched capacitors loading a resistor (or resistors) of the antialiasing filter. Further, the larger the filter resistor, the more it may be loaded by the switched capacitors. In addition, the smaller the equivalent resistance of the switched capacitors (i.e., equivalent resistance decreases as sampling frequency and/or capacitance increases), the more the switched capacitors load the filter.

Due to temperature changes and/or other environmental factors, gain of the filter and switched capacitor circuit may vary. Thus, it is desirable to track and correct for such changes.

SUMMARY

In accordance with the teachings of the present disclosure, the disadvantages and problems associated with gain drift due to temperature or other environmental factors/variations in an antialiasing filter may be reduced or eliminated.

In accordance with embodiments of the present disclosure, a method may include, for a signal path comprising a passive antialiasing filter sampled by a switched-capacitor front-end, monitoring a change of a first impedance of a resistor of the passive antialiasing filter responsive to an environmental condition relative to a second impedance of a switched capacitor of the switched-capacitor front end and compensating the signal path for a change in gain of the signal path resulting from the change of the first impedance.

In accordance with these and other embodiments of the present disclosure, a system may include monitoring circuitry configured to monitor a change of a first impedance of a resistor of a passive antialiasing filter of a signal path responsive to an environmental condition relative to a second impedance of a switched capacitor of the switched-capacitor front end, wherein the passive antialiasing filter is sampled by a switched-capacitor front end and compensation circuitry configured to compensate the signal path for a change in gain of the signal path resulting from the change of the first impedance.

Technical advantages of the present disclosure may be readily apparent to one having ordinary skill in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.

DETAILED DESCRIPTION

The description below sets forth example embodiments according to this disclosure. Further example embodiments and implementations will be apparent to those having ordinary skill in the art. Further, those having ordinary skill in the art will recognize that various equivalent techniques may be applied in lieu of, or in conjunction with, the embodiment discussed below, and all such equivalents should be deemed as being encompassed by the present disclosure.

FIG.1illustrates an example system100including a differential input ADC104having an antialiasing filter102at its input, with calibration circuitry for compensating for gain error resulting from environmental variations, in accordance with embodiments of the present disclosure. Such calibration circuitry may include an environmental monitor106, a gain calculator108, and a gain element110.

Antialiasing filter102may comprise any suitable system, device, or apparatus, for receiving an analog input signal, for example in the form of a differential voltage VDiff, and low-pass filtering the analog input signal to generate a filtered analog input signal to be received by the input of ADC104. As shown inFIG.1, antialiasing filter102may comprise resistors112, each resistor112coupled between a respective input and a respective output of antialiasing filter102. In addition, antialiasing filter102may include a capacitor114coupled between the outputs of antialiasing filter102. Further, antialiasing filter102may include capacitors116, each capacitor116coupled between a respective output of antialiasing filter102and ground.

ADC104may comprise any suitable system, device, or apparatus configured to sample the filtered analog signal generated at a sampling frequency fsand generate a digital signal DINTequivalent to such filtered analog signal. As shown inFIG.1, ADC104may include an input sampling network comprising switched capacitors118and sampling switches120that may operate in accordance with a sampling clock φSoperating at sampling frequency fs. An input sampling network may be more complex than that depicted inFIG.1and may include other components besides switched capacitors118and sampling switches120. Only switched capacitors118and sampling switches120are shown for purposes of clarity and exposition.

A combiner122may combine digital signal DINTwith an offset value OFFSET that may offset for mismatches between resistors112, capacitors116, and/or any other sources of offset in the differential path of system100. The calculation of offset value OFFSET may be made in any suitable manner, and is beyond the scope of the present disclosure.

Environmental monitor106may comprise any system, device, or apparatus configured to detect a change in temperature and/or other environmental condition in system100that may cause a change in a resistance RLPFof resistors112, which in turn may cause a change in signal gain within system100, and generate a digital tuning signal Dtuneas a function of such change in resistance RLPF. In general, environmental monitor106may measure a resistor impedance that changes in a manner similar to that of resistance RLPFin response to environmental changes, and compare such impedance to an impedance similar to equivalent resistance of switched capacitors118(which may be largely non-responsive and remain fixed in response to environmental changes) to track an effect of the environmental changes to resistance RLPFof resistors112. Examples of an environmental monitor106are depicted inFIGS.2and3, described below.

Gain calculator108may comprise any system, device, or apparatus configured to, based on digital tuning signal Dtune, calculate a digital gain G to be applied to digital signal DINT(or offset-corrected digital signal DINToutput by combiner122) in order to compensate for changes to resistance RLPFof resistors112responsive to environmental changes. Such gain G may be determined in any suitable manner, including offline characterization (e.g., during pre-delivery characterization of system100), that may define a function relating digital tuning signal Dtuneto gain G (e.g., an algebraic formula, lookup table, mapping, etc.).

Gain element110may multiply gain G to offset-corrected digital signal DINToutput by combiner122in order to generate a digital output signal DOUTequivalent to differential voltage VDiff. Such digital output signal DOUTmay be further processed by other digital circuitry as may be suitable to the application for which system100is used.

FIG.2illustrates an example environmental monitor106A implemented using a phase-locked loop (PLL) and/or frequency-locked loop (FLL) with a tunable resistive-capacitive oscillator208, in accordance with embodiments of the present disclosure. In some embodiments, environmental monitor106A may be used to implement environmental monitor106. As shown inFIG.2, environmental monitor106A may include a crystal oscillator202, a phase and/or frequency detector204, a low-pass filter206, resistive-capacitive oscillator208, and an ADC210.

Crystal oscillator202(or another stable low-drift clock source) may comprise any suitable system, device, or apparatus configured to drive a periodic (e.g., sine wave) clock signal.

Phase and/or frequency detector204may comprise any suitable system, device, or apparatus configured to generate an error signal based on the difference between the periodic clock signal generated by crystal oscillator202and a feedback oscillation signal generated by resistive-capacitive oscillator208. Such difference may be a phase difference between the periodic clock signal generated by crystal oscillator202and the feedback oscillation signal generated by resistive-capacitive oscillator208and/or a frequency difference between the periodic clock signal generated by crystal oscillator202and the feedback oscillation signal generated by resistive-capacitive oscillator208. Low-pass filter206may filter such error signal in the analog domain, thus generating a voltage tuning signal Vtuneto be applied to the input of resistive-capacitive oscillator208in order to minimize the error signal generated by phase and/or frequency detector204.

Assuming the resistor(s) of resistive-capacitive oscillator208are of the same type of resistor as resistors112, and also assuming that the capacitor(s) of resistive-capacitive oscillator208are substantially non-responsive to changes in temperature and/or other environmental variations, then the change in resistance of resistor(s) of resistive-capacitive oscillator208relative to the equivalent impedance of capacitor(s) of resistive-capacitive oscillator208may be a proxy for (e.g., substantially proportional to) the change of resistance RLPFrelative to the equivalent impedance of switched capacitors118. Because voltage tuning signal Vtunemay be a function of the change in resistance of resistor(s) of resistive-capacitive oscillator208relative to the equivalent impedance of capacitor(s) of resistive-capacitive oscillator208, voltage tuning signal Vtunemay in effect measure the change of resistance RLPFrelative to the equivalent impedance of switched capacitors118.

Based on the resulting filtered error signal it receives, resistive-capacitive oscillator208may generate the feedback oscillation signal. Further, ADC210may convert voltage tuning signal Vtuneinto an equivalent digital signal—digital tuning signal Dtune—thus enabling gain calculator108to calculate gain G based on the change of resistance RLPFrelative to the equivalent impedance of switched capacitors118.

FIG.3illustrates an example environmental monitor106B implemented using a time-to-digital converter304with a tunable digitally-controlled resistive-capacitive oscillator308, in accordance with embodiments of the present disclosure. In some embodiments, environmental monitor106B may be used to implement environmental monitor106. As shown inFIG.3, environmental monitor106B may include a crystal oscillator302, a time-to-digital converter304, a low-pass filter306, and resistive-capacitive oscillator308. In many practical respects, environmental monitor106B has similar functionality to that of environmental monitor106A.

Crystal oscillator302(or another stable low-drift clock source) may comprise any suitable system, device, or apparatus configured to drive a periodic (e.g., sine wave) clock signal.

Time-to-digital converter304may comprise any suitable system, device, or apparatus configured to generate a digital error signal based on a phase and/or frequency difference between the periodic clock signal generated by crystal oscillator302and a feedback oscillation signal generated by digitally-controlled resistive-capacitive oscillator308. Low-pass filter306may filter such digital error signal in the digital domain, thus generating digital tuning signal Dtuneto be applied to the input of resistive-capacitive oscillator308in order to minimize the error signal generated by time-to-digital converter304.

Assuming the resistor(s) digitally modeled in digitally-controlled resistive-capacitive oscillator308are of the same type of resistor as resistors112, and also assuming that the capacitor(s) digitally modeled in digitally-controlled resistive-capacitive oscillator308are substantially non-responsive to changes in temperature and/or other environmental variations, then the change in resistance of resistor(s) of resistive-capacitive oscillator308relative to the equivalent impedance of capacitor(s) of resistive-capacitive oscillator308may be a proxy for (e.g., substantially proportional to) the change of resistance RLPFrelative to the equivalent impedance of switched capacitors118. Because digital tuning signal Dtunemay be a function of the change in resistance of resistor(s) of resistive-capacitive oscillator208relative to the equivalent impedance of capacitor(s) of resistive-capacitive oscillator208, digital tuning signal Dtunemay in effect measure the change of resistance RLPFrelative to the equivalent impedance of switched capacitors118.

Alternatively to the approaches described above, a replica of antialiasing filter102and ADC104may be used to measure changes in resistance RLPFin response to environmental variations. For example,FIG.4illustrates an example system400including a differential input ADC104having an antialiasing filter102at its input, and a replica antialiasing filter402and replica ADC404operating in parallel with antialiasing filter102and differential input ADC104, in accordance with embodiments of the present disclosure.

Replica antialiasing filter402may comprise any suitable system, device, or apparatus, for receiving an analog input signal, for example in the form of a differential voltage VDiff, and low-pass filtering the analog input signal to generate a filtered replica analog input signal to be received by the input of replica ADC404. As shown inFIG.4, replica antialiasing filter402may comprise resistors412, each resistor412coupled between a respective input and a respective output of replica antialiasing filter402and having a resistance RREPwhich may be substantially equal to or substantially different from resistance RLPFof resistors112. In addition, antialiasing filter402may include a capacitor414coupled between the outputs of replica antialiasing filter402and having a capacitance CREPwhich may be substantially equal to or substantially different from capacitance CLPFof capacitor114.

Replica ADC404may comprise any suitable system, device, or apparatus configured to sample the filtered analog signal generated at a sampling frequency fREP, which may be substantially equal to or substantially different from sampling frequency fS, and generate a replica digital signal DREPequivalent to such filtered analog signal. As shown inFIG.4, replica ADC404may include a replica input sampling network comprising replica switched capacitors418and replica sampling switches420that may operate in accordance with a replica sampling clock φREPoperating at replica sampling frequency fREP.

In operation, replica antialiasing filter402and replica ADC404may be configured to generate replica digital signal DREP, which may track the gain error due to environmental variations with higher sensitivity than digital signal DINT. Gain calculator408may then apply any suitable mathematical combination to calculate gain G to be applied to off-set corrected digital signal DINT. For example, in some embodiments, gain G may be calculated as G=DINT/DREP.

In some embodiments, RREP>RLPFand/or CREP<CLPF, with fREP=fS. For example, as shown inFIG.5, RREP=2RLPFand CREP=0.5CLPF. Further, in some embodiments, RREP=RLPFand CREP<CLPF. In addition, in yet other embodiments, RREP>RLPFand CREP=CLPF. In any case, in the embodiments represented byFIGS.4and5, a gain difference and/or ratio between digital signal DINTand replica digital signal DREPmay be used to track variation of resistors112responsive to environmental variations and correct for such variation. In some instances, such approach may be used to provide runtime in-situ calibration responsive to environmental variations.

In some embodiments, fREP≠fSwhile RREP=RLPFand CREP=CLPF, as depicted inFIG.6. In other words, replica antialiasing filter402may have impedances substantially identical to that of antialiasing filter102, with replica ADC404having a known replica sampling frequency fREPdifferent than that of sampling frequency fS(e.g., fREP=k·fS). Again, as in the arrangement shown inFIG.5, a gain difference and/or ratio between digital signal DINTand replica digital signal DREP(generated at such other sampling frequency) may be used to track variation of resistors112responsive to environmental variations and correct for such variation. In some instances, such approach may be used to provide runtime in-situ calibration responsive to environmental variations.

One alternative approach to that shown inFIG.6is to configure system400such that fREP=fS, RREP=RLPF, and CREP=CLPF, but with replica sampling capacitors418having a different (e.g., significantly higher) capacitance than that of sampling capacitors118. Again, as in the arrangement shown inFIGS.5and6, a gain difference and/or ratio between digital signal DINTand replica digital signal DREPmay be used to track variation of resistors112responsive to environmental variations and correct for such variation. In some instances, such approach may be used to provide runtime in-situ calibration responsive to environmental variations.

Alternatively to the approach of the previous paragraph, replica antialiasing filter402and replica ADC404may be absent, and ADC102may be run at two different sampling rates and calibration for environmental variations may be determined based on the difference or ratio between the measurements of digital signal DINTat the two different sampling rates.

FIG.7illustrates an example system700including an input integrator701(which may be an input integrator of an ADC) having an antialiasing filter102at its input, with gain correction performed by filtering of a reference voltage Vrefto integrator701, in accordance with embodiments of the present disclosure. As shown inFIG.7, reference voltage Vrefmay be filtered by a resistive-capacitive filter702loaded by a switched-capacitor reference path of integrator701, such that a front-end drop in gain due to environmental variations that affect resistance RLPFmay be inherently corrected by an increase of the gain of ADC704comprising integrator701due to the drop in reference voltage Vref. Thus, with proper sizing of capacitor ratios Rref:Crefand RLPF:CLPF, an inherent calibration of temperature coefficient may be achieved, without a need for any additional bench or in-situ calibration (e.g., using the approaches ofFIGS.1-6). In other words, in a data converter (e.g., an ADC) wherein a reference voltage is filtered by a resistive-capacitive filter loaded by the switched-capacitor reference path of the data converter, a front-end gain drop may be calculated by gain calculator708and compensated for, by monitoring the drop in the reference voltage as a result of switched-capacitor loading on the reference path resistive-capacitive filter.