Buffer control circuit, semiconductor memory device for memory module including the buffer control circuit, and control method of the buffer control circuit

A buffer control circuit, a semiconductor memory device for a memory module including the buffer control circuit, and a control method of the buffer control circuit, in which power consumption can be reduced. The buffer control circuit includes a first control signal generator that generates an internal buffer control signal in response to write latency signals and internal control signals, and a second control signal generator that generates a buffer control signal in response to the internal buffer control signal and a termination control signal. It is therefore possible to reduce unnecessary power consumption incurred by a data input buffer.

BACKGROUND

1. Field of the Invention

The present invention generally relates to a semiconductor memory device, and more particularly, to a buffer control circuit of a semiconductor memory device and control method thereof.

2. Discussion of Related Art

In general, a semiconductor memory device includes a data input buffer that receives data from an external device and outputs the externally input data to an internal core circuit including a memory cell array, during a write operation. When the data input buffer is enabled to perform the operation of receiving the external input data, current consumption of the semiconductor memory device rises abruptly. This is because the data input buffer receives the external input data through an external transmission line having a relatively high resistance value.

To reduce current consumption by the data input buffer, it is very important to control the data input buffer to be disabled during the remaining periods except for the period in which the data input buffer must operate. To this end, the semiconductor memory device includes a buffer control circuit for enabling or disabling the data input buffer by generating a control signal.

The construction and operation of the buffer control circuit in the related art will be described in short below with reference toFIGS. 1 and 2.FIG. 1is a block diagram of a buffer control circuit and data I/O circuits of a semiconductor memory device in the related art.

Data input buffers INB1to INBJ and data output buffers OUTB1to OUTBJ of data I/O circuits DATC1to DATCJ (J is an integer) are connected to I/O pads P1to PJ, respectively. For example, the data input buffer INB1and the data output buffer OUTB1can be connected to the I/O pad P1. The data input buffers INB1to INBJ are enabled or disabled in response to a buffer control signal ENDINDSB1.

Preferably, when the buffer control signal ENDINDSB1is disabled, the data input buffers INB1to INBJ is enabled. When the data input buffers INB1to INBJ are enabled, they receive external input data WDAT1to WDATJ, respectively, through the I/O pads P1to PJ and output internal input data INDAT1to INDATJ, respectively. The data output buffers OUTB1to OUTBJ receive the internal output data OUTDAT1to OUTDATJ, respectively, and output external output data RDAT1to RDATJ, respectively, to the I/O pads P1to PJ.

Meanwhile, a buffer control circuit10generates the buffer control signal ENDINDSB1in response to write latency signals WL1to WL3and internal control signals CKEBCOM, RASIDLE, DOFFB1, and WTSTDB. In more detail, the buffer control circuit10disables the buffer control signal ENDINDSB1when the internal control signal RASIDLE is disabled and enables the buffer control signal ENDINDSB1when the internal control signal DOFFB1or the internal control signal RASIDLE is enabled.

During the read operation of the semiconductor memory device including the buffer control circuit10, the internal control signal DOFFB1is enabled while the data output buffers OUTB1to OUTBJ output the external output data RDAT1to RDATJ to the I/O pads P1to PJ, respectively. As a result, the buffer control circuit10enables the buffer control signal ENDINDSB1in response to the control signal DOFFB1during the period in which the control signal RASIDLE is disabled (i.e., during the active period of the semiconductor memory device). However, in the event that the buffer control circuit10generates the buffer control signal ENDINDSB1based on the control signal DOFFB1, a circuit designer may encounter lots of difficulties in designing the buffer control circuit10.

In more detail, the buffer control circuit10is disposed close to the data input buffer in order to rapidly execute the control operation of the data input buffer. However, a control signal generator (not shown) that generates the control signal DOFFB1is disposed far away from the data input buffer because it has to receive a variety of control signals of a control circuit block (not shown). As semiconductor chips are miniaturized due to the developments of semiconductor manufacturing technology, however, a designing work for routing a signal line that transfers the control signal DOFFB1from the control signal generator to the buffer control circuit10becomes more difficult.

In the case where the buffer control circuit10generates the buffer control signal ENDINDSB1based on the control signal DOFFB1, a problem arises because the buffer control circuit10operates even during a period in which the data input buffers INB1to INBJ need not to be driven actually. This problem may become more profound when the semiconductor memory device including the buffer control circuit10is applied to semiconductor devices in which a plurality of semiconductor memory devices (i.e., memory ranks) are disposed on one chip in the same manner as the memory module.

The operation of the buffer control circuit10when the semiconductor memory device including the buffer control circuit10is disposed in a memory module will be described below with reference toFIG. 2. It is assumed that the memory module includes first to Uth(U is an integer) semiconductor memory devices (not shown), each of which has the buffer control circuit10. It is also assumed that after an active command ACT is inputted to the first to Uthsemiconductor memory devices at the same time and read commands READ1to READU are sequentially inputted to the first to Uthsemiconductor memory devices, a precharge command PRECH is inputted to the first to Uthsemiconductor memory devices at the same time.

InFIG. 2, chip selection signals CSB1to CSBU are signals for selecting the first to Uthsemiconductor memory devices, respectively, and internal control signals DOFFB1to DOFFBU are generated from the first to Uthsemiconductor memory devices, respectively. Furthermore, the buffer control signal ENDINDSB1enables or disables the data input buffers INB1to INBJ of the first semiconductor memory device.

If the active command ACT is inputted to the first to Uthsemiconductor memory devices at the same time, the first to Uthsemiconductor memory devices are respectively activated. Thereafter, if the read commands READ1to READU are sequentially inputted to the first to Uthsemiconductor memory devices, respectively, the first to Uthsemiconductor memory devices sequentially operate the read operation. At this time, the internal control signals DOFFB1to DOFFBU are respectively enabled only when corresponding ones of the first to Uthsemiconductor memory devices output the external output data RDAT1to RDATJ to the outside. It is to be understood that only timing diagrams of the external output data RDAT1of each of the first to Uthsemiconductor memory devices is shown inFIG. 2for simplification.

The internal control signal DOFFB1is enabled while the first semiconductor memory device outputs the external output data RDAT1to the outside. Accordingly, the buffer control circuit10of the first semiconductor memory device enables the buffer control signal ENDINDSB1during a period T1in which the internal control signal DOFFB1is enabled and disables the buffer control signal ENDINDSB1again after the period T1. As a result, the data input buffers INB1to INBJ of the first semiconductor memory device are disabled during the period T1and are enabled again after the period T1.

It is not necessary for the data input buffers INB1to INBJ of the first semiconductor memory device to operate during the period T2in which each of the second to Uthsemiconductor memory devices performs the read operation. As a result, there is a problem in that the data input buffers INB1to INBJ of the first semiconductor memory device consume power unnecessarily during the period T2.

There is also a problem in which the data input buffers INB1to INBJ of each of the second to Uthsemiconductor memory devices consume power unnecessarily during periods other than the read operation period of each of the second to Uthsemiconductor memory devices. This problem may become more profound when the number of semiconductor memory devices included in a memory module is increased.

SUMMARY OF THE INVENTION

An embodiment of the present invention is that it provides a buffer control circuit, in which it can reduce unnecessary power consumption incurred by a data input buffer, by generating a buffer control signal based on a control signal for a termination unit.

Another embodiment of the present invention is that it provides a semiconductor memory device for a memory module, in which it can reduce unnecessary power consumption incurred by a data input buffer, by generating a buffer control signal based on a control signal for a termination unit.

Further another embodiment of the present invention is that it provides a control method of a buffer control circuit, in which it can reduce unnecessary power consumption incurred by a data input buffer, by generating a buffer control signal based on a control signal for a termination unit.

According to an aspect of the present invention, a buffer control circuit includes a first control signal generator and a second control signal generator. The first control signal generator generates an internal buffer control signal in response to write latency signals and internal control signals. The second control signal generator generates a buffer control signal in response to the internal buffer control signal and a termination control signal. The termination control signal may be enabled for a predetermined time during a read operation of a semiconductor memory device including a termination unit and the buffer control circuit. The predetermined time may be decided by a read command inputted to the semiconductor memory device, and Column Address Strobe (CAS) latency and a burst length burst length set in the semiconductor memory device. The termination unit may be enabled or disabled in response to the termination control signal.

According to another aspect of the present invention, a semiconductor memory device for a memory module includes a buffer control circuit, a plurality of data input buffers, and a plurality of termination units. The buffer control circuit generates a buffer control signal in response to write latency signals, internal control signals, and a termination control signal. The plurality of data input buffers are connected to a plurality of I/O pads, respectively, through a plurality of data input lines. The input buffers receive external input data, which are respectively inputted to the plurality of I/O pads, respectively, and output internal input data to an internal circuit including a core circuit, in response to the buffer control signal during a write operation of the semiconductor memory device. The plurality of termination units are connected to the plurality of data input lines, respectively, and match impedances of the plurality of data input lines to predetermined values, respectively, in response to the termination control signal.

According to further another aspect of the present invention, a semiconductor memory device for a memory module includes a buffer control circuit, a plurality of data input buffers, and a plurality of termination units. The plurality of buffer control circuits generate a plurality of buffer control signals, respectively, in response to write latency signals, internal control signals, and a termination control signal, respectively. The plurality of data input buffers are connected to a plurality of I/O pads, respectively, through a plurality of data input lines. The data input buffers receive external input data, which are respectively inputted to the plurality of I/O pads, respectively, and output internal input data to an internal circuit including a core circuit, in response to the plurality of buffer control signals, respectively, during a write operation of the semiconductor memory device. Furthermore, the plurality of termination units are connected to the plurality of data input lines, respectively, and match impedances of the plurality of data input lines to predetermined values, respectively, in response to the termination control signal.

According to further another aspect of the present invention, there is provided a control method of a buffer control circuit that controls at least one data input buffer in a semiconductor memory device for a memory module, including the at least one data input buffer and at least one termination unit, including the steps of generating an internal buffer control signal in response to write latency signals and internal control signals, and generating a buffer control signal in response to the internal buffer control signal and a termination control signal, thereby enabling or disabling the at least one data input buffer. The termination control signal may control the operation of the at least one termination unit and may be enabled for a predetermined time during a read operation of the semiconductor memory device. The predetermined time may be decided by a read command inputted to the semiconductor memory device, and CAS latency and a burst length set in the semiconductor memory device.

DETAILED DESCRIPTION OF EMBODIMENTS

The present invention will now be described in detail in connection with certain exemplary embodiments with reference to the accompanying drawings.

FIG. 3is a block diagram of a buffer control circuit according to an embodiment of the present invention. Referring toFIG. 3, a buffer control circuit100includes a first control signal generator110, and a second control signal generator120.

The first control signal generator110generates an internal buffer control signal ENDISB in response to write latency signals WL1to WL3and internal control signals CKEBCOM, RASIDLE, and WTSTDB. The write latency signals WL1to WL3are respectively enabled or disabled according to write latency set in a semiconductor memory device (for example, SMD1) (refer toFIG. 6), which includes the buffer control circuit100.

The term “write latency” refers to a time from which a write command is inputted to the semiconductor memory device SMD1to when external input data IDQ1_1to IDQ1_N (N is an integer) are inputted to data input buffers IDB1to IDBN, respectively, of the semiconductor memory device SMD1.

For example, when the write latency is 1 (i.e., 1tCK (1tCK=1 clock cycle)), the write latency signal WL1is enabled and the write latency signals WL2, WL3are disabled. Furthermore, when the write latency is 2 (i.e., 2tCK), the write latency signal WL2is enabled and the write latency signals WL1, WL3are disabled. Furthermore, when the write latency is 3 (i.e., 3tCK), the write latency signal WL3is enabled and the write latency signals WL1, WL2are disabled.

The internal control signal CKEBCOM is disabled when the internal clock signal CLK of the semiconductor memory device SMD1is toggled. The internal control signal RASIDLE is disabled in synchronization with an active command ACT (refer toFIG. 7) when the active command ACT is inputted to the semiconductor memory device SMD1and is enabled in synchronization with a precharge command PRECH1(refer toFIG. 7) when the precharge command PRECH1is inputted to the semiconductor memory device SMD1.

The internal control signal WTSTDB is generated by a control circuit (not shown) based on the write command input to the semiconductor memory device SMD1, and write latency and a burst length set in the semiconductor memory device SMD1. In more detail, the control circuit disables the internal control signal WTSTDB for a time decided by the write latency and the burse length in response to the write command.

At this time, it is assumed that a point of time at which the write command is inputted to the semiconductor memory device SMD1is “A” and delay time when the internal control signal WTSTDB is disabled from the point of time A1is “ΔD”. In this case, the internal control signal WTSTDB is disabled at a point of time (A+ΔD+[(WL−1)×1tCK]) and keeps disabled during a time ([(BL/2)+2]×1tCK). “WL” denotes write latency set in the semiconductor memory device SMD1and “BL” denotes a burst length set in the semiconductor memory device SMD1. Meanwhile, “ΔD” denotes a delay time at which the internal clock signal CLK is generated asynchronously. Accordingly, a point of time at which the internal control signal WTSTDB is disabled may be varied depending on “ΔD”.

The second control signal generator120generates a buffer control signal IDBCTLB in response to the internal buffer control signal ENDISB and a termination control signal ODTENB. The termination control signal ODTENB is enabled while it is decided by a read command input to the semiconductor memory device SMD1during the read operation and Column Address Strobe (CAS) latency and a burst length set in the semiconductor memory device SMD1.

In more detail, assuming that a point of time delayed as much as CAS latency after the read command is inputted to the semiconductor memory device SMD1is “B”, the termination control signal ODTENB is enabled at a point of time (B+[(CL−1)×1tCK]) and then keeps enabled during a time ([(BL/2)+2]×1tCK). The reason why the termination control signal ODTENB keeps enabled during the time [(BL/2)+2]×1tCK) is that external output data (for example, ODQ1_1) (refer toFIG. 6) can be output from the semiconductor memory device SMD1stably.

That is, in the case where an termination unit ODT1is enabled while a data output buffer ODB1that shares an I/O buffer IOP1together with a data input buffer (for example, IDB1) (refer toFIG. 6) outputs the external output data ODQ1_1to the I/O buffer IOP1, the data output buffer ODB1cannot output the external output data ODQ1_1stably. For this reason, it is preferred that a point of time at which the termination control signal ODTENB is enabled is one clock cycle earlier that that at which the data output buffer ODB1outputs the external output data ODQ1_1. It is also preferred that a point of time at which the termination control signal ODTENB is disabled one clock cycle later than that at which the data output buffer ODB1completes the output operation of the external output data ODQ1_1.

Meanwhile, termination units ODT1to ODTN (refer toFIG. 6) included in the semiconductor memory device SMD1are enabled or disabled in response to the termination control signal ODTENB. In more detail, when the termination control signal ODTENB is enabled, the termination units ODT1to ODTN are disabled.

The construction and operation of the first control signal generator110and the second control signal generator120will be described in more detail below with reference toFIGS. 4 and 5.

Referring toFIG. 4, the first control signal generator110includes internal logic circuits130,140and a select output circuit150.

The internal logic circuit130outputs a selection control signal G1in response to the write latency signals WL1to WL3. In more detail, when any one of the write latency signals WL1to WL3is enabled, the internal logic circuit130enables the selection control signal G1.

The internal logic circuit130includes a NOR gate131and an inverter132. The NOR gate131outputs an internal logic signal L1in response to the write latency signals WL1to WL3. The inverter132inverts the internal logic signal L1and outputs an inverted signal as the selection control signal G1. Alternatively, as shown inFIG. 5, the internal logic circuit130may be implemented using an OR gate.

The internal logic circuit140generates a control logic signal G2in response to the internal control signals CKEBCOM, RASIDLE. In more detail, when one of the internal control signals CKEBCOM, RASIDLE is enabled, the internal logic circuit140enables the control logic signal G2.

The internal logic circuit140includes a NOR gate141and an inverter142. The NOR gate141outputs an internal logic signal L2in response to the internal control signals CKEBCOM, RASIDLE. The inverter142inverts the internal logic signal L2and outputs an inverted signal as the control logic signal G2. Alternatively, as shown inFIG. 5, the internal logic circuit140may be implemented using an OR gate.

The select output circuit150includes selection circuits160,170and a latch circuit180.

The selection circuit160receives the control logic signal G2in response to the selection control signal G1and outputs the signal G2as a selection signal SEL. The selection circuit160includes inverters161,162. The inverter161inverts the selection control signal G1and outputs an inverted selection control signal G1B. The inverter162may be implemented using a tri-state inverter. The inverter162is enabled or disabled in response to the selection control signal G1and the inverted selection control signal G1B. Preferably, when the selection control signal G1is enabled, the inverter162may be enabled to receive the control logic signal G2and to output the control logic signal G2as the selection signal SEL. In more detail, the inverter162inverts the control logic signal G2and outputs an inverted signal as the selection signal SEL.

The selection circuit170receives the internal control signal WTSTDB in response to the selection control signal G1and outputs the signal as the selection signal SEL. The selection circuit170includes inverters171,172. The inverter171inverts the selection control signal G1and outputs an inverted selection control signal G1B. The inverter172may also be implemented using a tri-state inverter in a similar way to the inverter162. The inverter172is enabled or disabled in response to the selection control signal G1and the inverted selection control signal G1B. Preferably, when the selection control signal G1is disabled, the inverter172may be enabled to receive the internal control signal WTSTDB and to output the internal control signal WTSTDB as the selection signal SEL. In more detail, the inverter172inverts the internal control signal WTSTDB and outputs an inverted signal as the selection signal SEL. Preferably, when one of the inverters162,172is enabled, the other of the inverters162,172is disabled. Consequently, when one of the selection circuits160,170performs the output operation of the selection signal SEL, the other of the selection circuits160,170stops the output operation of the selection signal SEL.

The latch circuit180includes inverters181,182. The latch circuit180latches the selection signal SEL and outputs a latched signal as the internal buffer control signal ENDISB. As a result, when any one of the write latency signals WL1to WL3is enabled, the first control signal generator110outputs the internal buffer control signal ENDISB in response to the internal control signals CKEBCOM, RASIDLE.

Furthermore, when all the write latency signals WL1to WL3are disabled (i.e., when the write latency set in the semiconductor memory device is greater than 3), the first control signal generator110outputs the internal buffer control signal ENDISB in response to the internal control signal WTSTDB. The reason why the first control signal generator110does not use the internal control signal WTSTDB when the write latency is smaller than 3 as described above is that the internal control signal WTSTDB is disabled at a point of time (A+ΔD+[(WL−1)×1tCK]). This will be described in more detail below.

As the operating frequency of the semiconductor memory device increases, the cycle of the internal clock signal CLK reduces. Accordingly, a point of time at which external input data are inputted to the semiconductor memory device becomes more fast. However, since the time ΔD is a signal asynchronous to the internal clock signal CLK, a point of time at which the internal control signal WTSTDB is disabled is slower than that at which the external input data are input.

Accordingly, the first control signal generator110outputs the internal buffer control signal ENDISB in response to the internal control signal WTSTDB and the second control signal generator120outputs the buffer control signal IDBCTLB in response to the internal buffer control signal ENDISB. Consequently, the point of time at which the data input buffer is enabled in response to the buffer control signal IDBCTLB becomes slower than that at which the external input data are input.

The second control signal generator120includes a NOR gate121and an inverter122. The NOR gate121outputs an internal logic signal L3in response to the internal buffer control signal ENDISB and the termination control signal ODTENB. The inverter122inverts the internal logic signal L3and outputs an inverted signal as the buffer control signal IDBCTLB. Alternatively, as shown inFIG. 5, the second control signal generator120may be implemented using an OR gate.

As described above, the buffer control circuit100outputs the buffer control signal IDBCTLB such that the data input buffer is disabled not only during a period in which a semiconductor memory device including the buffer control circuit100actually performs the read operation, but also during a period in which the termination control signal ODTENB is enabled (i.e., a period in which the termination unit is disabled). Accordingly, the buffer control circuit100can prevent unnecessary operations of the data input buffer, thereby reducing unnecessary power consumption.

FIG. 6is a block diagram of semiconductor memory devices for a memory module according to an embodiment of the present invention.FIG. 6illustrates an example in which the semiconductor memory devices SMD1to SMDK (K is an integer) are included in one memory module. The semiconductor memory devices SMD1to SMDK have the same construction and operations and only the semiconductor memory device SMD1will be described below as an example.

The semiconductor memory device SMD1includes a buffer control circuit100, an internal circuit200, data I/O circuits DIOC1to DIOCN (N is an integer), and termination units ODT1to ODTN (N is an integer).

The buffer control circuit100includes a first control signal generator110and a second control signal generator120. The construction and operation of the first control signal generator110and the second control signal generator120are substantially the same as those that have been described with reference toFIGS. 3 to 5. Description thereof will be omitted for simplicity.

The internal circuit200includes a core circuit (not shown). Each of the data I/O circuits DIOC1to DIOCN includes a data input buffer and a data output buffer. For example, the data I/O circuit DIOC1may include a data input buffer IDB1and a data output buffer ODB1and the data I/O circuit DIOCN may include a data input buffer IDBN and a data output buffer ODBN. The data input buffers IDB1to IDBN are connected to I/O pads IOP1to IOPN, respectively, through data input lines DIL1to DILN, respectively.

During the write operation of the semiconductor memory device SMD1, the data input buffers IDB1to IDBN receive the external input data IDQ1_1to IDQ1_N, which are respectively inputted to the I/O pads IOP1to IOPN, respectively, in response to a buffer control signal IDBCTLB1generated by the buffer control circuit100, and output internal input data ID1to IDN, respectively, to the internal circuit200.

During the read operation of the semiconductor memory device SMD1, the data output buffers ODB1to ODBN receive internal output data OD1to ODN, respectively, from the internal circuit200and output external output data ODQ1_1to ODQ1_N, respectively, to the I/O pads IOP1to IOPN, respectively.

The termination units ODT1to ODTN are connected to the data input lines DIL1to DILN, respectively. The termination units ODT1to ODTN are enabled or disabled in response to a termination control signal ODTENB. Preferably, when the termination control signal ODTENB is disabled, the termination units ODT1to ODTN may be enabled. When the termination units ODT1to ODTN are enabled, they match the impedances of the data input lines DIL1to DILN to preset values, respectively, thereby minimizing the distortion of the external input data IDQ1_1to IDQ1_N inputted to the semiconductor memory device SMD1.

A circuit designer may use various types of On-Die Termination (ODT) schemes as the termination units ODT1to ODTN of the semiconductor memory device SMD1. For example, each of the termination units ODT1to ODTN may be implemented using a PMOS transistor. In this case, a resistance value of the PMOS transistor may be set to be appropriate for matching one of the impedances of the data input line DIL1to DILN to a set value.

Furthermore, in the case where each of the termination units ODT1to ODTN is implemented using a PMOS transistor, the PMOS transistor has a source connected to an internal voltage VDDQ and a drain connected to one of the data input line DIL1to DILN though not shown inFIG. 6. In addition, the PMOS transistor has a gate to which the termination control signal ODTENB is inputted. When the termination control signal ODTENB is disabled, the PMOS transistor is turned on to supply the internal voltage VDDQ to any one of the data input lines DIL1to DILN. To the contrary, when the termination control signal ODTENB is enabled, the PMOS transistor is turned off.

A method of allowing the buffer control circuit100to control the operation of each of the data input buffers IDB1to IDBN will be described in more detail below with reference toFIG. 7. In the present embodiment, only the operation of the buffer control circuit100of the semiconductor memory device SMD1will be described as an example.

For convenience of description, it is assumed that the CAS latency and the write latency set in each of the semiconductor memory devices SMD1to SMDK are 2, respectively, and a burst length is 4. It is also assumed that the active command ACT is inputted to the semiconductor memory devices SMD1to SMDK at the same time, and after read commands READ1to READK are sequentially inputted to the semiconductor memory devices SMD1to SMDK, a precharge command PRECHK is inputted to the semiconductor memory devices SMD1to SMDK at the same time.

InFIG. 7, chip selection signals CSB1to CSBK (K is an integer) are signals for selecting the semiconductor memory devices SMD1to SMDK, respectively. Furthermore, the semiconductor memory devices SMD1to SMDK are commonly applied with a Row Address Strobe (RAS) control signal RASB, a CAS control signal CASB, and a write enable signal WEB.

If the internal clock signal CLK is toggled, the internal control signal CLEBCOM is disabled. Thereafter, if the entire chip selection signals CSB1to CSBK and the RAS control signal RASB become logical lows and the active command ACT is inputted to the semiconductor memory devices SMD1to SMDK at the same time, each of the semiconductor memory devices SMD1to SMDK becomes active.

Alternatively, the active command ACT may be selectively inputted to one or a part of the semiconductor memory devices SMD1to SMDK. In this case, a part of the chip selection signals CSB1to CSBK, which correspond to the remaining semiconductor memory devices other than a semiconductor memory device that must be activated, are kept to logical highs.

The internal control signal RASIDLE1corresponding to the semiconductor memory device SMD1is disabled when the active command ACT is inputted to the semiconductor memory device SMD1. Thereafter, the internal control signal RASIDLE1keeps disabled until the precharge command PRECHK is inputted to the semiconductor memory device SMD1.

Meanwhile, since the write latency set in the semiconductor memory device SMD1is 2, the write latency signal WL2is enabled and the write latency signals WL1, WL3are disabled. As a result, the first control signal generator110of the buffer control circuit100generates an internal buffer control signal ENDISB1in response to the internal control signals RASIDLE1, WTSTDB1. Since the internal control signal RASIDLE1has been disabled, the first control signal generator110disables the internal buffer control signal ENDISB1. The termination control signal ODTENB1is initially disabled. Accordingly, the termination units ODT1to ODTN of the semiconductor memory device SMD1are enabled in response to the termination control signal ODTENB1.

The second control signal generator120of the buffer control circuit100disables the buffer control signal IDBCTLB1in response to the termination control signal ODTENB1and the internal buffer control signal ENDISB1. As a result, the data input buffers IDB1to IDBN of the semiconductor memory device SMD1are enabled in response to the buffer control signal IDBCTLB1.

Thereafter, if the read command READ1is inputted to the semiconductor memory devices SMD1to SMDK at the same time when the CAS control signal CASB and the chip selection signal CSB1become logical lows and the chip selection signals CSB2to CSBK become logical highs, the semiconductor memory device SMD1performs the read operation. At this time, the semiconductor memory devices SMD2to SMDK do not perform the read operation.

Meanwhile, the termination control signal ODTENB1is enabled at a point of time TM. Thereafter, since the burst length is 4 bits, the termination control signal ODTENB1keeps enabled during 4tCK. The second control signal generator120of the semiconductor memory device SMD1enables the buffer control signal IDBCTLB1in response to the termination control signal ODTENB1. As a result, the data input buffers IDB1to IDBN of the semiconductor memory device SMD1are disabled in response to the buffer control signal IDBCTLB1.

When the CAS control signal CASB and the chip selection signal CSB2become logical lows and the chip selection signals CSB1, CSB3to CSBK become logical highs after 4tCK, the read command READ2is inputted to the semiconductor memory devices SMD1to SMDK at the same time. Accordingly, the semiconductor memory device SMD2performs the read operation, but the semiconductor memory devices SMD1, SMD3to SMDK do not perform the read operation.

Since the read command READ2is inputted to the semiconductor memory device SMD1after 4tCK, the termination control signal ODTENB1keeps enabled by the read command READ2. As shown inFIG. 7, since the semiconductor memory device SMD1receives one of the read commands READ3to READK every 3tCK, the termination control signal ODTENB1keeps enabled for a time T11and is then disabled.

Accordingly, the second control signal generator120of the semiconductor memory device SMD1enables the buffer control signal IDBCTLB1until the read operations of the semiconductor memory devices SMD1to SMDK are all completed (i.e., a time T12), and then disables the buffer control signal IDBCTLB1, in response to the termination control signal ODTENB1.

As a result, the data input buffers IDB1to IDBN of the semiconductor memory device SMD1keep disabled during the time T12and are then enabled. Consequently, during the time T12, unnecessary power consumption by the data input buffers IDB1to IDBN can be reduced.

Thereafter, if the precharge command PRECHK is inputted to the semiconductor memory devices SMD1to SMDK at the same time when the RAS control signal RASB, the write enable signal WEB, and the chip selection signals CSB1to CSBK become logical lows, the semiconductor memory devices SMD1to SMDK perform the precharge operation. The internal control signal RASIDLE1is enabled when the precharge command PRECHK is inputted to the semiconductor memory device SMD1.

When the internal control signal RASIDLE1is enabled, the first control signal generator110enables the internal buffer control signal ENDISB1. The second control signal generator120enables the buffer control signal IDBCTLB1in response to the internal buffer control signal ENDISB1. As a result, the data input buffers IDB1to IDBN of the semiconductor memory device SMD1are disabled again in response to the buffer control signal IDBCTLB1.

Alternatively, the precharge operations of the semiconductor memory devices SMD1to SMDK may selectively be executed one by one. In this case, the precharge commands PRECH1to PRECHK shown inFIG. 7decide the precharge operation times of the semiconductor memory devices SMD1to SMDK, respectively. This will be described in more detail below.

If the precharge command PRECHK is inputted to the semiconductor memory devices SMD1to SMDK at the same time when the RAS control signal RASB, the write enable signal WEB, and the chip selection signal CSB1become logical lows, the semiconductor memory device SMD1performs the precharge operation. Meanwhile, when the precharge command PRECHK is inputted to the semiconductor memory devices SMD1to SMDK, the chip selection signals CSB2to CSBK become logical highs as indicated by a dotted line inFIG. 7. Accordingly, the semiconductor memory devices SMD2to SMDK do not perform the precharge operation. Furthermore, when the precharge command PRECH1is inputted to the semiconductor memory device SMD1, the internal control signal RASIDLE1is enabled as indicated by a dotted line inFIG. 7.

When the internal control signal RASIDLE1is enabled, the first control signal generator110enables the internal buffer control signal ENDISB1. The second control signal generator120enables the buffer control signal IDBCTLB1in response to the internal buffer control signal ENDISB1. As a result, the buffer control signal IDBCTLB1is enabled at the point of time TM and then keeps enabled as indicated by a dotted line inFIG. 7. Thereafter, the precharge operations of the semiconductor memory devices SMD2to SMDK are performed in a similar way to the precharge operation of the semiconductor memory device SMD1.

As described above, in the semiconductor memory device SMD1, the buffer control circuit100generates the buffer control signal IDBCTLB1in response to the termination control signal ODTENB1. Accordingly, unnecessary power consumption by the data input buffers IDB1to IDBN can be reduced. Furthermore, the buffer control circuit100disposed close to the data input buffers IDB1to IDBN employs the termination control signal ODTENB1to control the termination units ODT1to ODTN. Accordingly, a designer can easily route the signal line SL for transferring the termination control signal ODTENB1in the buffer control circuit100.

FIG. 8is a block diagram of semiconductor memory devices for a memory module according to another embodiment of the present invention. The construction and operation of each of the semiconductor memory devices SMD1to SMDK shown inFIG. 8are substantially the same as those that have been described with reference toFIG. 6except for one thing. Therefore, only the difference will be described in the present embodiment. Furthermore, inFIG. 8, the semiconductor memory devices SMD1to SMDK have the same construction and operations and only the semiconductor memory device SMD1will be described below as an example.

The construction of the semiconductor memory device SMD1shown inFIG. 8is different from that shown inFIG. 6in that the buffer control circuit100is replaced with the buffer control circuits BFC1to BFCN. Each of the buffer control circuits BFC1to BFCN generates one of the buffer control signal IDBCTLB1to IDBCTLBN in response to the write latency signals WL1to WL3and the internal control signals CKEBCOM, RASIDLE1, and WTSTDB1. As a result, the data input buffers IDB1to IDBN are enabled or disabled in response to the buffer control signals IDBCTLB1to IDBCTLBN, respectively.

In the case where the data input buffers IDB1to IDBN are controlled according to the buffer control signal IDBCTLB1to IDBCTLBN, respectively, as described above, the data input buffers IDB1to IDBN can be enabled or disabled much rapidly compared with the data input buffers IDB1to IDBN shown inFIG. 6. This is because a delay time which is taken for the buffer control signals IDBCTLB1to IDBCTLBN to reach the data input buffers IDB1to IDBN is shortened since the buffer control circuits BFC1to BFCN are disposed corresponding to the data input buffers IDB1to IDBN, respectively.

As described above, in accordance with the buffer control circuit, the semiconductor memory device for the memory module including the buffer control circuit, and control method of the buffer control circuit according to the present invention, a buffer control signal is generated based on a control signal for a termination unit. It is therefore possible to reduce unnecessary power consumption incurred by a data input buffer.

Furthermore, a design work for routing the signal line for transferring the control signal for the termination unit in the buffer control circuit can be facilitated.