Half-swing line precharge method and apparatus

A method and apparatus of precharging data and/or address lines each having a large number of loads to a voltage midway between high and low using a source-follower configuration, and optionally driving only one-half of the precharge circuit based on a previous logical value on the line being precharged. In some embodiments, a driver circuit drives an output node either high or low during a first phase of each clock cycle, and a precharge circuit then precharges the output node to an intermediate voltage during a second phase of the clock cycle in preparation for the following clock cycle. Some embodiments include source-follower configured FETs to precharge, wherein these FETs turn off once the output voltage reaches an intermediate value.

FIELD OF THE INVENTION

This invention relates to the field of digital CMOS electronic circuits, and more specifically to a method and apparatus of precharging lines having a large number of loads to a voltage midway between high and low using a source-follower configuration, and optionally driving only one-half of the circuit based on a previous logical value on the line being precharged.

BACKGROUND OF THE INVENTION

High-current driver circuits are often used to drive signal lines having a large number of loads. Complementary field-effect transistor (FET) technology, such as CMOS, typically have very little DC loading when driving gate inputs, since there is almost no current drawn across the gate, however there is an AC capacitive load due to capacitance of the gate. In order to achieve high-speed switching, a high-current driver is needed to provide or to remove the electron charge on that capacitance.

A computer system can include a plurality of vector processors, as well as scalar processors, memory, input/output subsystems, and other features.

Advanced vector processors include a large number of elements (e.g., 128 elements) in each vector register, and a relatively large number of vector registers in each vector processor. Data being stored to a vector register will typically need to be driven to at least one or two gates for every element of a vector register (e.g., 128 or 256 gates or more).

Further, high-speed vector processors often use a clocking scheme in which a high number of successive results on successive clocks to successive elements of a vector register.

Thus, there is a need for a high current driver that will quickly switch a large number of loads. There is also a need for a clocking scheme for the high-current driver that maximizes data throughput.

SUMMARY OF THE INVENTION

The present invention provides method and apparatus of precharging data and/or address lines each having a large number of loads to a voltage midway between high and low using a source-follower configuration, and optionally driving only one-half of the precharge circuit based on a previous logical value on the line being precharged. In some embodiments, a driver circuit drives an output node either high or low during a first phase of each clock cycle, and a precharge circuit then precharges the output node to an intermediate voltage during a second phase of the clock cycle in preparation for the following clock cycle.

DESCRIPTION OF PREFERRED EMBODIMENTS

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. It is understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

The leading digit(s) of reference numbers appearing in the Figures generally corresponds to the Figure number in which that component is first introduced, such that the same reference number is used throughout to refer to an identical component which appears in multiple Figures. Signals and connections may be referred to by the same reference number or label, and the actual meaning will be clear from its use in the context of the description.

FIG. 1shows a schematic representation of a precharge-driver circuit100of one embodiment of the present invention. Circuit100includes a driver circuit portion110and a precharge circuit portion120. Driver circuit110includes a pair of complementary transistors111and112that drive output node150. In some embodiments, pull-up transistor111is a PFET transistor and pull-down transistor112is an NFET transistor. In some embodiments, VSSsupply voltage132is at ground, and VDDsupply voltage132is either 2.5 volts, 1.8 volts, or 1.5 volts, or some other suitable voltage, depending on the semiconductor technology and dimensions. In other embodiments, other voltages are used, to suit the technology and the design objectives. As dimensions of the transistors shrink and speeds increase, lower voltages are typically used.

Referring to driver circuit110for circuit100, when the input signal191of transistor111is low, transistor111turns on, and when the input signal192of transistor112is low, transistor112turns off, thus connecting output node150to VDDsupply voltage131and driving the voltage of output node150high (an inverting function for the data). The voltage timing diagram300ofFIG. 3shows this during clock phase311. Similarly, when the input signal192of transistor112is high, transistor112turns on, and when the input signal191of transistor111is high, transistor111turns off, connecting output node150to Vss supply voltage132and driving the voltage of output node150low (an inverting function for the data). The voltage timing diagram300ofFIG. 3shows this during clock phase313. During a first phase of clock109(i.e., phases311and313ofFIG. 3are both during the first phase of clock109), switches113and114are both in the up position. Thus, during this first phase when input data D-bar is present at the inputs of transistors111and112(e.g., in this example, when clock109is high), either one or the other of transistors111and112are on and the other is off, so the output data Q on output node150is the inverse of that data. In some embodiments, an input data signal D is inverted using an invertor (such as invertor401ofFIGS. 4A,4B, and4C) to generate input data signal D-bar.

When the input signal191of transistor111is high, transistor111turns off, disconnecting output node150from VDDsupply voltage131and letting other transistors drive the voltage of output node150(a tri-state function for the circuit). Similarly, when the input signal192of transistor112is low, transistor112turns off, disconnecting output node150from VSSsupply voltage132and letting other transistors drive the voltage of output node150(a tri-state function for the circuit). During a second phase of clock109, switches113and114are both in the down position. Thus, during this second phase when high voltage (e.g., VDD) is present at the input of transistor111and low voltage (e.g., VSS) is present at the input of transistor112, both transistors are off and disconnected from output node150.

Thus, during the first phase of clock109, driver circuit110actively drives output node150with the inverse of input data D-bar, and during the second phase of clock109, driver circuit110is turned off (tri-stated to high impedance).

Precharge circuit120includes a pair of complementary transistors121and122that drive output node150(in a mode often called a source-follower mode). In some embodiments, pull-up transistor121is an NFET transistor connected to power VDDsupply voltage131and pull-down transistor122is a PFET transistor connected to power VSSsupply voltage132. Due to the respective threshold voltages of pull-up transistor121and pull-down transistor122, neither can drive output node150close to the respective supply voltages, and in fact, even when the inputs are active, each of pull-up transistor121and pull-down transistor122will stop conducting when the output voltage reaches an intermediate voltage (e.g., about one-half of the VDDminus VSSdifference, or about 0.9 volts for 1.8-volt technology).

Further, in some embodiments, when transistor121is turned on, the output voltage on node150will approach VDDminus VTHRESHOLDminus VINPUT, so by adjusting the voltage of the active-high input193, transistor121can be made to turn itself off once it has driven output node150to the desired intermediate voltage. In some embodiments, the width/length ratio of transistor121is adjusted relative to the clock timing such that the voltage of output node150reaches the desired intermediate voltage at the end of the second phase of clock109even though the voltage would continue past the desired point if the second phase of the clock cycle were longer.

Referring to precharge circuit120inFIG. 1, when the input signal193of transistor131is low, transistor121turns off, disconnecting output node150from VDDsupply voltage131and letting other transistors drive the voltage of output node150(a tri-state function for the circuit). Similarly, when the input signal194of transistor122is high, transistor122turns off, disconnecting output node150from VSSsupply voltage132and letting other transistors drive the voltage of output node150(a tri-state function for the circuit). During a first phase of clock109, electronic switches123and124are both in the up position (i.e., these schematically shown switches include transistors (e.g., as shown inFIGS. 5 and 6) that connect to the upper (“up position”) or lower (down position) input signals). Thus, during this first phase when low voltage (e.g., VSS) is present at the input of transistor121and high voltage (e.g., VDD) is present at the input of transistor122, both transistors121and122are off and disconnected from output node150, allowing the one driver transistor (111or112) that is on in driver circuit110to drive output node150.

Further, when the input signal193of transistor121is high, transistor121turns on (in a mode often called a source-follower mode), and when the input signal194of transistor122is high, transistor122turns off, thus connecting output node150to VDDsupply voltage131and driving the voltage of output node150upwards (a source-follower type of non-inverting function for the D-bar data input through switch123). The loads on output node150(typically a high number of FET gates) are capacitive, and the current drives the voltage upward. However, since the threshold voltage of transistor121stops transistor121from conducting at some intermediate voltage (rather than a voltage close to VDD), the output node150and its loads, starting at a low voltage near VSS, are precharged to that intermediate voltage, but no further. The voltage timing diagram300ofFIG. 3shows this precharging during clock phase314.

In some embodiments, the same D-bar data that drove transistors111and112during the first phase of the clock cycle is used to drive transistors121and122during the second phase of the clock cycle. In other embodiments, the D-bar data is inverted an even number of times to generate a version of the data called T-bar such as shown inFIGS. 4A,4B, and4C.

Similarly, when the input signal194of transistor122is low, transistor122turns on (in the mode often called source-follower mode), and when the input signal193of transistor121is low, transistor121turns off, connecting output node150to VSSsupply voltage132and driving the voltage of output node150low (a source-follower type of non-inverting function for the D-bar data input through switch124). The voltage timing diagram300ofFIG. 3shows this during clock phase312.

During the first phase of clock109(i.e., phases311and313ofFIG. 3are both during the first phase of clock109), switches123and124are both in the up position. Thus, during this first phase when VSSis present at the input of transistor121and VDDis present at the input of transistor122(e.g., in this example, when clock109is high), both transistors121and122are off.

During the second phase of clock109(i.e., phases312and314ofFIG. 3are both during the second phase of clock109), switches123and124are both in the down position. Thus, during this second phase when D-bar is present at the inputs of both transistors121and122(e.g., in this example, when clock109is low), only one of transistors121or122is on, and the other is off. Because of the source follower configuration, the “on” transistor will only precharge the output node and its loads to the intermediate voltage.

FIG. 2shows a schematic representation of a precharge-driver circuit200of one embodiment of the present invention. This circuit is substantially identical to that ofFIG. 1, except that when switch123is connected in the down position, it connects the gate of transistor121to VDD, and switch124connects the gate of transistor122to VSS. This, during the second phase of the clock cycle of clock109, turns on both transistors121and122in the source follower mode, which may draw somewhat more current than the circuit ofFIG. 1. However, due to the threshold voltage of each transistor, only one will primarily conduct current initially, while the other is essentially off.

FIG. 3shows a schematic representation of a timing diagram300and equivalent circuit of one embodiment of the present invention. Waveform310represents a voltage-time graph of clock signal109, while waveform320represents a voltage-time graph of the signal of output node150. During first phase311of a first clock cycle of clock waveform310, transistor111(e.g., a PFET transistor) is turned on so the voltage321rises to approach VDD(voltage value331). During second phase312of the first clock cycle of clock waveform310, transistor122(e.g., also a PFET transistor) is turned on so the voltage321falls toward VSS, but stops well short of VSSat intermediate voltage value333. During first phase313of a second clock cycle of clock waveform310, transistor111(e.g., a NFET transistor) is turned on so the voltage323falls to approach VSS(voltage value332). During second phase314of the second clock cycle of clock waveform310, transistor121(e.g., also a NFET transistor) is turned on so the voltage324rises toward VDD, but stops well short of VDDagain at intermediate voltage value333.

FIGS. 4A,4B, and4C show a schematic representation of a precharge-driver circuit400of one embodiment of the present invention. Circuit400includes an LSSD (level-sensitive scan design) master latch460and an LSSD slave latch470. Input signal441is inverted by invertor401(including transistor P4having a width-length ratio of about 28.5 in some embodiments, and transistor N4having a width-length ratio of about 10.2 in some embodiments) to generate D-bar signal442, which is used to drive the output stage480. The rest of invertor chain410(i.e., transistors N5and P5which generate D2 signal442, transistors N6and P6which generate D3-bar signal443, transistors N7and P7which generate D4 signal445, and transistors N8and P8which generate D5-bar signal446) provides additional inversions and re-inversions of the logical signal to generate D5-bar signal446.

During the first phase of the clock cycle of C1_CLK, the pass gate of transistors P9and N9gates signal446to node447, and it is then inverted by the invertor of transistors P15and N15to form T1 signal448, which is then inverted by the invertor of transistors P16and N16to form T1-bar signal449.

FIGS. 4A,4B, and4C show the width-length ratio of each of PFET transistors P1through P27and NFET transistors N1through N27for one embodiment of the invention. The invertor of P1and N1has an input of C1_CLK and provides an output of C1_CLK-bar. C1_CLK and C1_CLK-bar are used throughout circuit400to control the switches for the first phase and second phase of the clock cycle. The invertor of P2and N2has an input of A_CLK and provides an output of A_CLK-bar. A_CLK and A_CLK-bar are used throughout circuit400to control latching of scan data into the LSSD master460. The invertor of P3and N3has an input of B_CLK and provides an output of B_CLK-bar. B_CLK and B_CLK-bar are used throughout circuit400to control latching of scan data into the LSSD slave470.

During the first phase of the clock cycle of C1_CLK, the transistor N17of pass gate413gates D-bar signal442as signal451to the gate of driver transistor111(also referenced as PFET P21), which turns transistor111on if D-bar is low (driving output node450high) and turns transistor111off if D-bar is high. Also during the first phase of the clock cycle of C1_CLK, the transistor P18of pass gate414gates D-bar signal442as signal452to the gate of driver transistor112(also referenced as NFET N21), which turns transistor112on if D-bar is high (driving output node450low) and turns transistor112off if D-bar is low. Thus, signal Q on output node450is driven to the value D of input signal441during the first phase of C1_CLK. During the second phase of C1_CLK, both transistors111and112are turned off by gating VDD to the gate of transistor111through pass transistor P17and gating VSSto the gate of transistor112through pass transistor N18.

During the first phase of the clock cycle of C1_CLK, both transistors121and122are turned off by gating VSSas signal453to the gate of transistor121(NFET N22) through pass transistor N19and gating VDDas signal454to the gate of transistor122(PFET P22) through pass transistor P20. The transistor N17of pass gate413(transistors P17and N17) gates D-bar signal442to the gate of driver transistor111(also referenced as PFET P21), which turns transistor111on if D-bar is low (driving output node450high) and turns transistor111off if D-bar is high. Also during the first phase of the clock cycle of C1_CLK, the transistor P18of pass gate414(transistors P18and N18) gates D-bar signal442to the gate of driver transistor112(also referenced as NFET N21), which turns transistor112on if D-bar is high (driving output node450low) and turns transistor112off if D-bar is low. Thus, signal Q on output node450is driven to the value D of input signal441during the first phase of C1_CLK.

During the second phase of C1_CLK, T1-bar signal449is gated through transistor P18of pass gate423(transistors P19and N19) to the gate of N22NFET121, which is in a source-follower configuration. T1-bar signal449maintains the data value of D1-bar for this second phase of C1_CLK. Thus, if the output Q signal450was driven low during the first phase of C1_CLK, and T1-bar will be high, turning on transistor121to increase the voltage towards VDD(transistor122will be off if T1-bar is high), but transistor121, being an NFET, will turn off before driving the output to VDDdue to the threshold voltage of transistor121. This will leave the output node450as a voltage approximately half way between VDDand VSS, precharged for the next clock cycle of C1_CLK.

Conversely, during the second phase of C1_CLK, T1-bar signal449is also gated through transistor N20of pass gate424(transistors P20and N20) to the gate of P22PFET122, which is also in a source-follower configuration. Thus, if the output Q signal450was driven high during the first phase of C1_CLK, and T1-bar will be low, turning on transistor122to decrease the voltage towards VSS, but transistor122, being a PFET, will turn off before driving the output to VSSdue to the threshold voltage of transistor122. This will leave the output node450as a voltage approximately half way between VDDand VSS, precharged for the next clock cycle of C1_CLK.

During the second phase of the clock cycle of C1_CLK, both transistors111and112are turned off by gating VDDas signal451to the gate of transistor111(PFET P21) through pass transistor P17and gating VSSas signal452to the gate of transistor112(NFET N21) through pass transistor N18.

Thus, the output node450is driven to the value of input signal D441during the first phase of C1_CLK, and is driven, during the second phase of C1_CLK, to a voltage approximately half way between VDDand VSS, precharged for the next clock cycle of C1_CLK. This increases the speed at which the operating voltage for the data for the next cycle is established, and thus increases the speed of the system.

FIG. 5shows a schematic representation of a precharge-driver circuit500of one embodiment of the present invention. Circuit500includes an input inverter501(in some embodiments, having a PFET relative gate width of 12, and an NFET relative gate width of 8), which inverts input signal D502and generates signal D-bar503(the inverted value of data signal D). Clock signal C1504is high for the first phase and low during the second phase and clock signal C2505is the inverse of C1504and is low during the first phase and high during the second phase. Thus, during the first phase when C1504is high, NFET transistor514(relative gate width of 9.3, in some embodiments) is on, transmitting D-bar to the gate of PFET transistor111(relative gate width of 76, in some embodiments), and C2505is low turning on PFET transistor515(relative gate width of 9.3, in some embodiments) transmitting D-bar to the gate of NFET transistor112(relative gate width of 30, in some embodiments). Thus transistors111and112invert signal D-bar to form signal Q on output node550for the first phase (when C1504is high), and transistors522and521are both turned off. Thus, during the first phase when C1504is high, output node550(signal Q) is driven to the data value of input signal D502.

During the second phase when C1504is low, transistors514and515are off but PFET transistor513(relative gate width of 18.6, in some embodiments) is on, transmitting VDDto the gate of PFET transistor111turning it off, and C2505is high turning on NFET transistor516(relative gate width of 4.6, in some embodiments) transmitting VSSto the gate of NFET transistor112turning it off. Thus, both transistors111and112are off and not driving output node550. However, during the second phase, C2505is high, which turns on transistor521only if output Q at node550is low (transistor522is off in this case) driving the output node450to a higher voltage, and transistor521turns off once the output node550reaches an intermediate voltage between VDDand VSSdue to the threshold voltage of transistor521. Further, during the second phase, C1504is low, which turns on transistor522only if output Q at node550is high (transistor521is off in this case), driving the output node450to a lower voltage and transistor521turns off once the output node550reaches an intermediate voltage between VDDand VSSdue to the threshold voltage of transistor522. Thus, during the second phase when C1504is low, output node550is precharged for the next clock cycle.

In some embodiments, one or more of the drivers described above are used to drive the input circuits for a set of vector registers. In other embodiments, they drive any other suitable receiving circuit line that benefits from the speed increase resulting from driving the input line to a half-swing voltage before driving data to that line.

FIG. 6shows a schematic representation of a tri-state driver circuit600of one embodiment of the present invention. Clock signal C1604is high for the first phase and low during the second phase and clock signal C2605is the inverse of C1604and is low during the first phase and high during the second phase. When input signal D602is high, NFET transistor615is on driving internal node621low (to VSS), and PFET transistor616is off floating internal node622. Thus when input D602is high, during the first phase when C1604is high, NFET transistor614is on, transmitting D-bar (low value) to the gate of PFET transistor111turning it on and driving output node650high, and transistor608is on, transmitting node621's D-bar (low value) to the gate of NFET transistor112turning it off. When input signal D602is low, PFET transistor616is on driving internal node622high (to VDD), and PFET transistor615is off floating internal node621. Thus when input D602is low, then during the first phase when C2605is low, PFET transistor617is on, transmitting D-bar (high value) to the gate of NFET transistor112turning it on and driving output node650low, and transistor609is on, transmitting node622's D-bar (high value) to the gate of PFET transistor111turning it off.

During the second phase, C1is low and C2is high, which turns off transistors614,608,617, and609disconnecting signal D from the output transistors111and112. This also turns on PFET transistor613connecting VDDto the gate of PFET output transistor111turning it off, and also turns on NFET transistor618connecting VSSto the gate of NFET output transistor112turning it off. Thus transistors111and112drive the value of signal D to form signal Q on output node650for the first phase (when C1is high). During the second phase, both transistors111and112are turned off. In some embodiments, this tri-state driver is used to drive the input circuits for a set of vector registers.

FIG. 7shows a schematic of an information-processing system700. System700includes a memory730. (including one or more sections), an input-output subsystem710, one or more processing elements720, each including a vector processing unit721operatively coupled to the memory730and to the input-output subsystem710, the vector processing unit721further comprising a set of vector registers722, wherein the set of vector registers includes an input724, and a clocked vector register drive-and-precharge circuit723, wherein the drive-and-precharge circuit includes one or more of the above described circuits ofFIGS. 1,2,3,4,5, and/or6. Circuit723in general includes a driver circuit having an output node connected to the input of the set of vector registers and a pair of complementary drive transistors configured to drive a first data signal onto the output node during a first phase of a clock cycle and configured to turn off during a second phase of the clock cycle, and a precharge circuit coupled to the output node and configured to turn off during the first phase of the clock cycle and configured to drive the output node to an intermediate voltage during the second phase of the clock cycle.

One embodiment of the invention provides a drive-and-precharge circuit including a driver circuit having an output node and a pair of CMOS drive transistors including an NMOS driver transistor having a gate and having a controlled current path connected between a VSSvoltage and the output node and a PMOS driver transistor having a gate and having a controlled current path connected between a VDDvoltage and the output node, a first driver input circuit that couples a first data signal to the gate of the NMOS driver transistor during a first phase of a clock cycle and couples a voltage that turns off the NMOS driver transistor during a second phase of the clock cycle, and a second driver input circuit that couples the first data signal to the gate of the PMOS driver transistor during the first phase of the clock cycle and couples a voltage that turns off the PMOS driver transistor during the second phase of the clock cycle. The drive-and-precharge circuit also includes a PMOS precharge transistor having a gate and having a controlled current path connected between the VSSvoltage and the output node, an NMOS precharge transistor having a gate and having a controlled current path connected between the VDDvoltage and the output node, a first precharge input circuit that couples a second data signal to the gate of the PMOS precharge transistor during the second phase of the clock cycle and couples a voltage that turns off the PMOS precharge transistor during the first phase of the clock cycle, and a second precharge input circuit that couples the second data signal to the gate of the NMOS precharge transistor during a second phase of a clock cycle and couples a voltage that turns off the NMOS precharge transistor during the first phase of the clock cycle.

Some embodiments of the invention include a clocked vector register drive-and-precharge circuit. This circuit includes a driver circuit having an output node and a pair of complementary drive transistors configured to drive a first data signal onto the output node during a first phase of a clock cycle and configured to turn off during a second phase of the clock cycle, and a precharge circuit coupled to the output node and configured to turn off during the first phase of the clock cycle and configured to drive the output node to an intermediate voltage during the second phase of the clock cycle.

In some embodiments, the precharge circuit substantially reduces its current flow once the output node approaches the intermediate voltage.

In some embodiments, a value of the first data signal is coupled to the precharge circuit during to control a direction of change in voltage of the output node.

In some embodiments, the pair of complementary drive transistors includes an N-type drive transistor and a P-type drive transistor.

In some embodiments, the precharge circuit includes a P-type precharge transistor having a first node electrically connected to a first node of the N-type drive transistor and having second node electrically connected to a second node of the N-type drive transistor and to the output node, and an N-type precharge transistor having a first node electrically connected to a first node of the P-type drive transistor and to the output node and having second node electrically connected to a second node of the P-type drive transistor.

Some embodiments further include a first transistor that connects a voltage to a gate of the P-type precharge transistor that turns off the P-type precharge transistor during the first phase of the clock cycle, a second transistor that connects a voltage to a gate of the N-type precharge transistor that turns off the N-type precharge transistor during the first phase of the clock cycle, a third transistor that connects a first data signal to a gate of the P-type drive transistor during the first phase of the clock cycle, a fourth transistor that connects the first data signal to a gate of the N-type drive transistor during the first phase of the clock cycle, a fifth transistor that connects a voltage to a gate of the P-type drive transistor that turns off the P-type drive transistor during the second phase of the clock cycle, a sixth transistor that connects a voltage to a gate of the N-type drive transistor that turns off the N-type drive transistor during the second phase of the clock cycle, a seventh transistor that connects a second data signal to a gate of the P-type precharge transistor during the second phase of the clock cycle, wherein a value of the second data signal during the second phase of the clock cycle is based on a value of the first data signal during the first phase of the clock cycle, and a eighth transistor that connects the second data signal to a gate of the N-type precharge transistor during the second phase of the clock cycle.

In some embodiments, the pair of complementary drive transistors includes an N-type drive transistor and a P-type drive transistor, and wherein the precharge circuit includes a P-type precharge transistor having a first node electrically connected to a first node of the N-type drive transistor and having second node electrically connected to a second node of the N-type drive transistor and to the output node, and an N-type precharge transistor having a first node electrically connected to a first node of the P-type drive transistor and to the output node and having second node electrically connected to a second node of the P-type drive transistor, and the circuit further includes:a first transistor that connects a voltage to a gate of the P-type precharge transistor that turns off the P-type precharge transistor during the first phase of the clock cycle,a second transistor that connects a voltage to a gate of the N-type precharge transistor that turns off the N-type precharge transistor during the first phase of the clock cycle,a third transistor that connects a first data signal to a gate of the P-type drive transistor during the first phase of the clock cycle,a fourth transistor that connects the first data signal to a gate of the N-type drive transistor during the first phase of the clock cycle,a fifth transistor that connects a voltage to a gate of the P-type drive transistor that turns off the P-type drive transistor during the second phase of the clock cycle,a sixth transistor that connects a voltage to a gate of the N-type drive transistor that turns off the N-type drive transistor during the second phase of the clock cycle,a seventh transistor that connects a second data signal to a gate of the P-type precharge transistor during the second phase of the clock cycle, wherein a value of the second data signal during the second phase of the clock cycle is based on a value of the first data signal during the first phase of the clock cycle, anda eighth transistor that connects the second data signal to a gate of the N-type precharge transistor during the second phase of the clock cycle.

Another aspect of the invention provides embodiments that have a clocked vector register drive-and-precharge circuit that includes a driver circuit having an output node and a pair of complementary drive transistors including an N-type driver transistor having a gate and having a controlled current path connected between a first supply voltage and the output node and a P-type driver transistor having a gate and having a controlled current path connected between a second supply voltage and the output node, a first driver input circuit that couples a first data signal to the gate of the N-type driver transistor during a first phase of a clock cycle and couples a signal that turns off the N-type driver transistor during a second phase of the clock cycle, a second driver input circuit that couples the first data signal to the gate of the P-type driver transistor during the first phase of the clock cycle and couples a voltage that turns off the P-type driver transistor during the second phase of the clock cycle, a P-type precharge transistor having a gate and having a controlled current path connected between the first supply voltage and the output node, a N-type precharge transistor having a gate and having a controlled current path connected between the second supply voltage and the output node, a first precharge input circuit that couples a voltage that turns off the P-type precharge transistor during the first phase of the clock cycle and couples a second data signal to the gate of the P-type precharge transistor during the second phase of the clock cycle, and a second precharge input circuit that couples a voltage that turns off the N-type precharge transistor during the first phase of the clock cycle and couples the second data signal to the gate of the N-type precharge transistor during a second phase of a clock cycle.

In some embodiments, the N-type drive transistor is an NMOS device, the P-type drive transistor is a PMOS device, the N-type precharge transistor is an NMOS device, and the P-type precharge transistor is a PMOS device.

In some embodiments, a threshold voltage of the P-type precharge transistor reduces current flow through the P-type precharge transistor once the output node reaches an intermediate voltage, and wherein a threshold voltage of the N-type precharge transistor reduces current flow through the N-type precharge transistor once the output node reaches an intermediate voltage.

Another aspect of the invention includes embodiments that have an information-processing system700including a memory730, an input-output processing elements720, each PE720including a vector processing unit721operatively coupled to the memory730and to the input-output subsystem710, the vector processing unit721further comprising a set of vector registers722, wherein the set of vector registers722includes an input724, and a clocked vector register drive-and-precharge circuit723, wherein the drive-and-precharge circuit includes a driver circuit having an output node connected to the input of the set of vector registers and a pair of complementary drive transistors configured to drive a first data signal onto the output node during a first phase of a clock cycle and configured to turn off during a second phase of the clock cycle, and a precharge circuit coupled to the output node and configured to turn off during the first phase of the clock cycle and configured to drive the output node to an intermediate voltage during the second phase of the clock cycle.

In some such embodiments, the precharge circuit substantially reduces its current flow once the output node approaches the intermediate voltage.

In some embodiments, a value of the first data signal is coupled to the precharge circuit to control a direction of change in voltage of the output node.

In some embodiments, the pair of complementary drive transistors includes an N-type drive transistor and a P-type drive transistor, and wherein the precharge circuit includes a P-type precharge transistor having a first node electrically connected to a first node of the N-type drive transistor and having second node electrically connected to a second node of the N-type drive transistor and to the output node, and an N-type precharge transistor having a first node electrically connected to a first node of the P-type drive transistor and to the output node and having second node electrically connected to a second node of the P-type drive transistor.

In some embodiments, the pair of complementary drive transistors includes an N-type drive transistor and a P-type drive transistor, and wherein the precharge circuit includes a P-type precharge transistor having a first node electrically connected to a first node of the N-type drive transistor and having second node electrically connected to a second node of the N-type drive transistor and to the output node, and an N-type precharge transistor having a first node electrically connected to a first node of the P-type drive transistor and to the output node and having second node electrically connected to a second node of the P-type drive transistor. The circuit further includes a first transistor that connects a voltage to a gate of the P-type precharge transistor that turns off the P-type precharge transistor during the first phase of the clock cycle, a second transistor that connects a voltage to a gate of the N-type precharge transistor that turns off the N-type precharge transistor during the first phase of the clock cycle, a third transistor that connects a first data signal to a gate of the P-type drive transistor during the first phase of the clock cycle, a fourth transistor that connects the first data signal to a gate of the N-type drive transistor during the first phase of the clock cycle, a fifth transistor that connects a voltage to a gate of the P-type drive transistor that turns off the P-type drive transistor during the second phase of the clock cycle, a sixth transistor that connects a voltage to a gate of the N-type drive transistor that turns off the N-type drive transistor during the second phase of the clock cycle, a seventh transistor that connects a second data signal to a gate of the P-type precharge transistor during the second phase of the clock cycle, wherein a value of the second data signal during the second phase of the clock cycle is based on a value of the first data signal during the first phase of the clock cycle, and a eighth transistor that connects the second data signal to a gate of the N-type precharge transistor during the second phase of the clock cycle.

Another aspect of the invention provides (in some embodiments) a method for driving a clocked vector register drive-and-precharge circuit including driving an output node of the clocked vector register drive-and-precharge circuit to a data value during a first phase of a clock cycle, if a voltage corresponding to the data value of the output node is high during the first phase of the clock cycle, then driving the output node down toward an intermediate voltage during a second phase of the clock cycle, and if the voltage corresponding to the data value of the output node is low during the first phase of the clock cycle, then driving the output node up toward the intermediate voltage during the second phase of the clock cycle.

In some such embodiments, the driving the output node down toward an intermediate voltage includes providing a relatively high initial amount of current and then reducing the amount of current drive as the output node approaches the intermediate voltage.

In some embodiments, the driving the output node up toward an intermediate voltage includes providing a relatively high initial amount of current and then reducing the amount of current drive as the output node approaches the intermediate voltage.

In some embodiments, the first phase of the clock cycle and the second phase of the clock cycle are each approximately one-half of the clock cycle.

Some embodiments of the invention include a system for driving a clocked vector register drive-and-precharge circuit including a clock signal, and means as described herein, operatively coupled to the clock signal, for driving an output node of the clocked vector register drive-and-precharge circuit to a data value during a first phase of the clock signal, and if a voltage corresponding to the data value of the output node is high during the first phase of the clock cycle, then driving the output node down toward an intermediate voltage during a second phase of the clock signal, and if the voltage corresponding to the data value of the output node is low during the first phase of the clock signal, then driving the output node up toward the intermediate voltage during the second phase of the clock cycle.