Memory system and control method of memory system

A memory system includes a host interface, a nonvolatile memory, a power supply circuit, a protection circuit, and a first voltage monitor circuit. The power supply circuit is between the host interface and the nonvolatile memory, and supplies primary power to the nonvolatile memory. The protection circuit is between the host interface and the power supply circuit, and configured to clamp a power supply signal supplied from the host interface to the power supply circuit to a first voltage. The first voltage monitor circuit is between the host interface and the protection circuit, and configured to monitor a voltage level of the power supply signal supplied from the host interface and cause the voltage level of the power supply signal supplied to the power supply circuit to be decreased from the first voltage to a second voltage when the monitored voltage level is below a first threshold voltage.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-058064, filed Mar. 23, 2017, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a memory system and a control method of the memory system.

BACKGROUND

Generally, in a memory system, a power supply voltage received from outside is supplied to a nonvolatile memory or the like via a power supply circuit. When the power supply voltage is supplied to the power supply circuit, it is desirable to appropriately protect the power supply circuit.

DETAILED DESCRIPTION

Embodiments provide a memory system and a control method of the memory system that can appropriately protect a power supply circuit.

In general, according to one embodiment, a memory system includes a host interface, a nonvolatile memory, a power supply circuit, a protection circuit, and a first voltage monitor circuit. The power supply circuit is between the host interface and the nonvolatile memory, and supplies primary power to the nonvolatile memory. The protection circuit is between the host interface and the power supply circuit, and configured to clamp a power supply signal supplied from the host interface to the power supply circuit to a first voltage. The first voltage monitor circuit is between the host interface and the protection circuit, and configured to monitor a voltage level of the power supply signal supplied from the host interface and cause the voltage level of the power supply signal supplied to the power supply circuit to be decreased from the first voltage to a second voltage when the monitored voltage level is below a first threshold voltage.

Hereinafter, the memory system according to the exemplary embodiment will be described in detail with reference to the drawings. The disclosure is not limited by the exemplary embodiment.

Exemplary Embodiment

FIG. 1is a block diagram illustrating a configuration of a memory system1.

The memory system1is, for example, a solid state drive (SSD), which can be communicably connected to a host device HA, and can function as an external storage medium for the host device HA. The host device HA may be, for example, an information processing device such as a personal computer, a server, a storage box, a mobile phone, an imaging device; may be a mobile terminal such as a tablet computer or a smart phone; may be a game device; or may be an in-vehicle terminal such as a car navigation system.

As illustrated inFIG. 1, the memory system1includes a host interface2, a volatile memory group3, a controller4, a power supply device5, a DDC (DC-DC converter) group8, a protection circuit6, and a plurality of nonvolatile memory groups11(11-1to11-8). In one embodiment, these elements are mounted on a circuit board.

The host interface2includes a connector. The connector can be arranged at, for example, an end portion of the circuit board. The connector includes power pins and data pins. The host interface2supplies data received from the host device HA via the data pins to the controller4, or transmits data received from the controller4to the host device HA via the data pins. In addition, the host interface2supplies a power received from the host device HA via the power pins to the power supply device5via the protection circuit6.

The power supply device5is arranged between the host interface2and the nonvolatile memory group11. The power supply device5can be mounted on the circuit board in the vicinity of the connector as a plurality of components (not illustrated). As illustrated inFIG. 2, the power supply device5includes a power supply circuit51. The power supply device5includes an input terminal IN, an output terminal OUT, and a control output terminal PO. The input terminal IN is connected the protection circuit6. The output terminal OUT is connected to the DDC group8. The control output terminal PO is connected to the controller4. The power supply circuit51generates a power supply voltage for internal use of the memory system1from a power supply voltage received in the input terminal IN from the host interface2via the protection circuit6. The power supply circuit51supplies the generated power supply voltage to the DDC group8via the output terminal OUT.

Returning toFIG. 1, the power supply device5detects a rising of the external power supply voltage, generates a power-on reset signal, and supplies the generated power-on reset signal to the controller4via the control output terminal PO.

The DDC group8includes a plurality of DDCs81to88as illustrated inFIG. 2. Each of the DDCs81to88is a DC-DC converter, and receives a power supply voltage Vdd from the power supply circuit51, converts the power supply voltage Vdd to a different voltage level, and outputs the converted power supply voltage Vps. The plurality of DDCs81to88corresponds to a plurality of nonvolatile memory groups11, controllers4, and volatile memory group3. Each of the DDCs81to88outputs the converted power supply voltage Vps to the corresponding nonvolatile memory group11, the controller4, and the volatile memory group3.

The controller4can be mounted, for example, on the circuit board in the vicinity of the connector as a system on chip (SoC) package. The controller4generally controls each unit of the memory system1.

The volatile memory group3can be mounted, for example, on the circuit board in the vicinity of the connector as a plurality of volatile memory packages. Each volatile memory group3is, for example, SDRAM, DRAM, or SRAM. The volatile memory group3functions as a buffer when a signal (for example, a command, data or the like) is communicated between the host device HA or the nonvolatile memory group11and the controller4, or functions as a work area for the controller4.

The plurality of nonvolatile memory groups11are mounted on the circuit board. The nonvolatile memory group11can be mounted, for example, on both sides of the circuit board as a plurality of nonvolatile memory packages.

In each nonvolatile memory package, a plurality of chips of the nonvolatile memory (for example, a NAND flash memory) device are stacked to be accommodated. The nonvolatile memory device stores data in a nonvolatile manner. The nonvolatile memory device includes a memory cell array in which a plurality of memory cells are arrayed in a planar or a three-dimensional matrix configuration. Each memory cell may be capable of multi-level storage using, for example, an upper page and a lower page. In the nonvolatile memory device, data is erased on a block basis, and data writing and data reading are performed for each page. The block is configured with a plurality of pages.

The protection circuit6is arranged between the host interface2and the power supply device5. The protection circuit6can be mounted as, for example, a protection circuit package. Returning toFIG. 1, the protection circuit6includes an input terminal IN, an output terminal OUT, an enable terminal EN, and a slew rate control terminal SR. In the protection circuit6, the power pins of the host interface2are connected to the input terminal IN and the power supply device5is connected to the output terminal OUT. The protection circuit6is in an ON state when an electric potential at the enable terminal EN is at an active level (for example, L level). When the protection circuit6is in the ON state, the input terminal IN and the output terminal OUT are electrically connected. The protection circuit6becomes in OFF state when the electric potential at the enable terminal EN is at a non-active level (for example, H level). When the protection circuit6is in the OFF state, the connection between the input terminal IN and the output terminal OUT is electrically disconnected. In the protection circuit6, a capacitance element C1is electrically connected externally to the slew rate control terminal SR. The protection circuit6can adjust a rise time of the protection circuit6in the ON state according to the capacitance value of the capacitance element C1externally connected to the slew rate control terminal SR.

The protection circuit6is an eFuse that performs a circuit operation for protecting the system from an overvoltage, and a predetermined clamp voltage (for example, 15V) is set in advance. The protection circuit6has a function of clamping the input voltage to the clamp voltage. Since the clamp voltage is set in the protection circuit6as a fixed value, the clamp voltage cannot be changed after shipment.

In the memory system1, the power supply voltage is input to the protection circuit6from outside via the power pins of the host interface2. When the input power supply voltage exceeds the clamp voltage, the protection circuit6clamps the power supply voltage to the clamp voltage, and outputs the clamped power supply voltage to the power supply device5. In this way, it is possible to prevent the power supply voltage exceeding the clamp voltage from being supplied to the power supply circuit51. That is, if an allowable upper limit voltage of the power supply circuit51is higher than the clamp voltage, the power supply circuit51can be protected from destruction due to the overvoltage by the clamping function of the protection circuit6.

However, as the miniaturization of the elements included in the power supply circuit51progresses, the allowable upper limit voltage of the power supply circuit51can become lower than the clamp voltage (for example, to 14V). In this case, when the power supply voltage clamped to the clamp voltage (for example, 15V) is supplied to the power supply circuit51, there is a possibility that the power supply circuit51may be destroyed by the overvoltage.

Therefore, in the exemplary embodiment, in the memory system1, by configuring the protection circuit6so as to monitor the level of the power supply voltage input to the protection circuit6such that the protection circuit6goes into the OFF state in a case where the power supply voltage has a value lower than the clamp voltage and close to the allowable upper limit voltage of the power supply circuit51, the power supply circuit51can be prevented from being destroyed due to the overvoltage.

Specifically, the memory system1further includes a high voltage monitor circuit7. The high voltage monitor circuit7is arranged between the host interface2and the protection circuit6. The high voltage monitor circuit7is electrically inserted between a line L1and the protection circuit6. The line L1electrically connects the power pins of the host interface2and the input terminal IN of the protection circuit6. The high voltage monitor circuit7can be mounted as a high voltage monitor circuit package. The high voltage monitor circuit7includes a monitor terminal MR and the output terminal OUT. In the high voltage monitor circuit7, the monitor terminal MR is connected to the line L1, and the output terminal OUT is connected to the enable terminal EN of the protection circuit6. The high voltage monitor circuit7monitors whether or not the electric potential at the line L1exceeds a threshold voltage Vov.

Specifically, the high voltage monitor circuit7is configured as illustrated inFIG. 3.FIG. 3is a circuit diagram illustrating a configuration of a high voltage monitor circuit7. The configuration illustrated inFIG. 3is an example, and other configurations may be used as long as the circuit monitors whether or not the electric potential at the line L1exceeds a threshold voltage Vov.

The high voltage monitor circuit7includes a power terminal VDD, the monitor terminal MR, the output terminal OUT, a comparator CP1, and a voltage source E1. In the comparator CP1, a power supply node is electrically connected to the power terminal VDD, a ground node is electrically connected to a ground potential, a non-inverting input terminal is electrically connected to the monitor terminal MR, an inverting input terminal is electrically connected to the voltage source E1, and an output node is electrically connected to the output terminal OUT. The voltage source E1generates the threshold voltage Vov as a reference voltage and supplies the reference voltage to the comparator CP1. The reference voltage is a voltage which is equal the threshold voltage to be monitored by the high voltage monitor circuit7, and has a level between a voltage level of the power supply voltage Vdd and the ground level.

If the electric potential at the monitor terminal MR is lower than the threshold voltage Vov, the comparator CP1supplies a signal of L level to the output terminal OUT as a comparison result. When the electric potential at the monitor terminal MR becomes higher than the threshold voltage Vov, the comparator CP1supplies a signal of H level to the output terminal OUT as a comparison result.

For example, as illustrated inFIG. 4, the high voltage monitor circuit7monitors whether or not the electric potential at the line L1exceeds the threshold voltage Vov. The threshold voltage Vov is a value lower than the allowable upper limit voltage (for example, 14V), higher than the normal electric potential level (for example, substantially close to 12V) at the line L1, and further, close to the allowable upper limit voltage of the power supply circuit51. The threshold voltage Vov is, for example, 13.5V. The allowable upper limit voltage of the high voltage monitor circuit7is higher than the allowable upper limit voltage of the power supply circuit51.

In a period before timing t1, the high voltage monitor circuit7outputs the L level to the output terminal OUT according to the fact that electric potential at the line L1is lower than the threshold voltage Vov. The L level can also be regarded as a monitoring result indicating that the electric potential at the line L1is lower than the threshold voltage Vov. That is, the high voltage monitor circuit7makes the enable terminal EN of the protection circuit6be at the L level. In this way, during the period in which the electric potential at the line L1is lower than the threshold voltage Vov, the protection circuit6is maintained to be in ON state, and thus, the power supply voltage is supplied to the power supply device5from the power pins of the host interface2via the line L1and the protection circuit6.

At the timing t1, the high voltage monitor circuit7outputs the H level from the output terminal OUT according to the fact that the electric potential at the line L1becomes higher than the threshold voltage Vov. The H level can also be regarded as a monitoring result indicating that the electric potential at the line L1is higher than the threshold voltage Vov. That is, the high voltage monitor circuit7makes the enable terminal EN of the protection circuit6be at the H level. In this way, the protection circuit6is maintained to be in OFF state after the timing t1according to the fact that the electric potential at the line L1becomes higher than the threshold voltage Vov. That is, even if the electric potential at the line L1is lower than the clamp voltage (for example, 15V), in a case where the electric potential at the line L1is close to the allowable upper limit voltage (for example, 14V) of the power supply circuit51and exceeds the threshold voltage Vov (for example, 13.5V), since the protection circuit6can be in an OFF state, it is possible to prevent the power supply circuit51from being destroyed due to the overvoltage.

At this time, since the power supply to the power supply device5from the power pins of the host interface2is disconnected by the protection circuit6, the memory system1is configured in such a manner that the power is switched to the auxiliary power supply and the power loss data protection (PLP) processing is performed. In the PLP processing, data can be prevented from loss by transferring the data to the nonvolatile memory group11from the volatile memory group3during the period of power supply from the auxiliary power supply.

As illustrated inFIG. 1andFIG. 2, specifically, the memory system1further includes the auxiliary power supply circuit9. The auxiliary power supply circuit9includes a DDC91, a DDC92, and a back-up battery93. The back-up battery is, for example, a capacitor, a super capacitor, an electrolytic capacitor, a secondary battery, or the like. InFIG. 2, illustrates a case where the back-up battery93is a capacitor. The DDC91is a DC-DC converter that receives the power supply voltage Vdd from the power supply circuit51, adjust the level of the power supply voltage Vdd to a level suitable for charging the back-up battery93(for example, step down or boost), and supplies the result to the back-up battery93. The DDC92is a DC-DC converter that includes an enable terminal EN. The DDC92is in an OFF state when a control signal of the non-active level (for example, L level) is received by the enable terminal EN. In this way, the auxiliary power supply circuit9is in an OFF state. The DDC92is in ON state when the control signal of active level (for example, H level) is received by the enable terminal EN, and adjusts the voltage taken out from the back-up battery93to a level suitable for the operation of the DDC group8(for example, boost or step down), and supplies the result to the DDC group8. In this way, the auxiliary power supply circuit9is in an ON state.

In order to quickly perform the switching of the power to the auxiliary power supply and starting of the PLP processing, a function of monitoring the power-off is added to the functions of the power supply device5. As illustrated inFIG. 2, the power supply device5further includes a low voltage monitor circuit52. The low voltage monitor circuit52is arranged between the protection circuit6and the auxiliary power supply circuit9. The low voltage monitor circuit52is electrically inserted between the line L2and the auxiliary power supply circuit9. The line L2electrically connects the protection circuit6and the power supply circuit51. The low voltage monitor circuit52includes a monitor terminal MR and an output terminal OUT. In the low voltage monitor circuit52, the monitor terminal MR is connected to the line L2, and the output terminal OUT is respectively connected to the enable terminal EN of the DDC92in the auxiliary power supply circuit9via a control output terminal PD and the controller4via the control output terminal PD. The low voltage monitor circuit52monitors whether or not the electric potential at the line L2is lower than a threshold value Vbu.

Specifically, the low voltage monitor circuit52is configured as illustrated inFIG. 5.FIG. 5is a circuit diagram illustrating a configuration of the low voltage monitor circuit52. The configuration illustrated inFIG. 5is one example, and another configuration can be used as long as the circuit monitors whether or not the electric potential at the line L2is lower than a threshold value Vbu.

The low voltage monitor circuit52includes a power terminal VDD, a monitor terminal MR, an output terminal OUT, a comparator CP2, and a voltage source E2. In the comparator CP2, the power supply node is electrically connected to the power terminal VDD, a ground node is electrically connected to the ground electric potential, an inverting input terminal is electrically connected to the monitor terminal MR, a non-inverting input terminal is electrically connected to the voltage source E2, and an output node is electrically connected to the output terminal OUT. The voltage source E2generates the threshold value Vbu as a reference voltage and supplies the reference voltage to the comparator CP2. The reference voltage is a voltage which is equal to the threshold voltage to be monitored by the low voltage monitor circuit52and has a level between the electric potential of the power supply voltage VDD and the ground level. The reference voltage (the threshold value Vbu) is set to a value lower than the reference voltage (the threshold voltage Vov) (refer toFIG. 3) in the high voltage monitor circuit7.

If the electric potential at the monitor terminal MR is higher than the threshold value Vbu, the comparator CP2supplies a signal of L level to the output terminal OUT as a comparison result. When the electric potential at the monitor terminal MR becomes lower than the threshold value Vbu, the comparator CP2supplies a signal of H level to the output terminal OUT as a comparison result.

For example, as illustrated inFIG. 4, the low voltage monitor circuit52monitors whether or not the electric potential at the line L2is lower than the threshold value Vbu. The threshold value Vbu is a value lower than the threshold voltage Vov in the high voltage monitor circuit7. That is, the threshold value Vbu is a value lower than the voltage level at the line L2(for example, substantially close to 12V), and is a value indicating that the power-off occurs. The threshold value Vbu is, for example, 8.5V.

In a period before timing t2, the low voltage monitor circuit52outputs the L level to the output terminal OUT according to the fact that the electric potential at the line L2is higher than the threshold value Vbu. The L level can also be regarded as a monitoring result indicating that the electric potential at the line L2is higher than the threshold value Vbu. That is, the low voltage monitor circuit52makes the enable terminal EN of the DDC92in the auxiliary power supply circuit9be at the L level. In this way, during the period in which the electric potential at the line L2is higher than the threshold value Vbu, the auxiliary power supply circuit9is maintained to be in OFF state.

At the timing t2, the low voltage monitor circuit52outputs the H level from the output terminal OUT according to the fact that the electric potential at the line L2is lower than the threshold value Vbu.

The H level can also be regarded as a monitoring result indicating that the electric potential at the line L2is lower than the threshold value Vbu. That is, the low voltage monitor circuit52makes the enable terminal EN of the DDC92in the auxiliary power supply circuit9be at the H level, and supplies the H level to the controller4as a notification of the power-off.

The auxiliary power supply circuit9is in an ON state, and the power is switched to the auxiliary power supply from the main power supply. That is, according to the fact that the supply of the main power supply from the power supply circuit51to the DDC group8is disconnected), the DDC92in the auxiliary power supply circuit9is in an ON state at the timing t2, and is maintained to be in ON state thereafter, and thus, the auxiliary power supply is continuously supplied to the DDC group8from the auxiliary power supply circuit9. Along with that, the controller4receives the notification of the power-off, and starts the PLP processing using the auxiliary power supply.

For example, as the PLP processing, the controller4writes dirty data in a write buffer in the volatile memory group3into an emergency transfer block in the nonvolatile memory group11such that the data becomes nonvolatile. The emergency transfer block is dedicated block used for the PLP processing performed while the power-off occurs. In addition, as the PLP processing, the controller4writes administration information (e.g., logical-physical address conversion table, or the like) in the cache area in the volatile memory group3into the emergency transfer block in the nonvolatile memory group11such that the information becomes nonvolatile. Furthermore, as the PLP processing, the controller4logically disconnects the link (such as communication connection) to the host device HA (that is, stops the communication with the host device HA due to the abnormal power supply). As part of the PLP processing, the controller4may cancel the in-processed write command/read command that are not acknowledged as being completed to the host device HA.

At a timing t3, the high voltage monitor circuit7outputs the L level to the output terminal OUT according to the fact that the electric potential at the line L1is lower than the threshold voltage Vov. That is, the high voltage monitor circuit7makes the enable terminal EN of the protection circuit6be at the L level. In this way, the protection circuit6is changed to be in an ON state according to the fact that the electric potential at the line L1is lower than the threshold voltage Vov.

The electric potential at the line L2gradually increases after the timing t3according to the fact that the protection circuit6is in the ON state.

At a timing t4, the low voltage monitor circuit52outputs the L level to the output terminal OUT according to the fact that the electric potential at the line L2is higher than the threshold value Vbu. That is, the low voltage monitor circuit52makes the enable terminal EN of the DDC92in the auxiliary power supply circuit9be at the L level and supplies the L level to the controller4as a notification of releasing the power-off.

In this way, the auxiliary power supply circuit9is in an OFF state and the power is switched to the main power supply from the auxiliary power supply. That is, the DDC92in the auxiliary power supply circuit9is in an OFF state, and auxiliary power supply circuit9is maintained to be in the OFF state after the timing t4. That is, the state is returned to the state in which the power supply voltage is supplied to the power supply device5from the power pins of the host interface2via the line L1and the protection circuit6, and then the main power supply is supplied from the power supply device5to the DDC group8. Along with that, the controller4receives the notification of releasing the power-off, and rewrites the data retracted to the emergency transfer block into the volatile memory group3using the PLP processing, and restores the data.

As described above, the memory system1in the exemplary embodiment monitors the level of the power supply voltage input to the protection circuit6, and makes the protection circuit6be in an OFF state in a case where the monitored level of the power supply voltage is lower than the clamp voltage of the protection circuit6and is close to the allowable upper limit voltage of the power supply circuit51. In this way, it is possible to prevent the power supply circuit51from being destroyed due to the overvoltage.

Specifically, the memory system1in the exemplary embodiment includes a high voltage monitor circuit7. In a case where the electric potential at the line L1connecting the host interface2and the protection circuit6exceeds the threshold voltage Vov, the high voltage monitor circuit7supplies a signal indicating that the electric potential exceeds the threshold voltage Vov to the enable terminal EN of the protection circuit6. The threshold voltage Vov is a value lower than the allowable upper limit voltage (for example, 14V) of the power supply circuit51, higher than the normal electric potential level (for example, substantially, close to 12V) at the line L1, and is close to the allowable upper limit voltage of power supply circuit51. In this way, in a case where the electric potential is close to the allowable upper limit voltage of the power supply circuit51even if it is lower than the clamp voltage of the power supply circuit51, it is possible to make the protection circuit6be in the OFF state.

If an inverter is electrically inserted between the output terminal OUT of the high voltage monitor circuit7and the enable terminal EN of the protection circuit6, in the signal supplied to the enable terminal EN of the protection circuit6from the high voltage monitor circuit7, a logic level indicating that the electric potential exceeds the threshold voltage Vov and a logic level making the protection circuit6be in the OFF state may be inverted. For example, the high voltage monitor circuit7may be configured so as to output the H level when the electric potential at the line L1is equal to or lower than the threshold voltage Vov, and output the L level when the electric potential at the line L1exceeds the threshold voltage Vov. That is, when the electric potential at the line L1exceeds the threshold voltage Vov, the signal at the L level from the high voltage monitor circuit7indicating that the electric potential exceeds the threshold voltage Vov is logically inverted by the inverter and converted to a signal at the H level, making the protection circuit6be in the OFF state, and then, the resulting signal is supplied to the enable terminal EN of the protection circuit6.

Alternatively, the low voltage monitor circuit52may be provided on the outside of the power supply device5as long as the low voltage monitor circuit52monitors whether or not the electric potential at the line L2lower than the threshold value Vbu and supplies the monitoring result to the enable terminal EN of the DDC92and the controller4.

Alternatively, the protection circuit6illustrated inFIG. 1may be a bidirectional switch circuit6ias illustrated inFIG. 6, performing the protection circuit operation, instead of the eFuse.FIG. 6is a circuit diagram illustrating a configuration of the protection circuit6iin a modification example of the exemplary embodiment. In the protection circuit6i, the power pins of the host interface2are connected to an input node6i1, the power supply device5is connected to an output node6i2, and the high voltage monitor circuit7is connected to an enable node6i3. The protection circuit6iincludes a diode D1, a diode D2, a transistor M1, and a transistor M2.

An anode of the diode D1is connected to the input node6i1and a cathode is connected to a common connection node N1. An anode of the diode D2is connected to the output node6i2and a cathode is connected to the common connection node N1. A gate of the transistor M1is connected to the enable node6i3, a source is connected to the input node6i1, and a drain is connected to the common connection node N1. A gate of the transistor M2is connected to the enable node6i3, a source is connected to the common connection node N1, and a drain is connected to the output node6i2.

In this configuration also, in a case where the electric potential at the line L1where the host interface2and the protection circuit6are connected to each other exceeds the threshold voltage Vov, it is possible to make the protection circuit6ibe in OFF state by the high voltage monitor circuit7supplying the H level to the enable terminal EN of the protection circuit6.

Alternatively, as illustrated inFIG. 7, an auxiliary power supply circuit9jmay be partially incorporated in a power supply device5j.FIG. 7is a diagram illustrating a configuration of the power supply device5jand the auxiliary power supply circuit9jin another modification example of the exemplary embodiment.

For example, a DDC91and a DDC92in the auxiliary power supply circuit9jare provided in the power supply device5j, and a back-up battery93is externally connected to a node N2between the DDC91and the DDC92via a terminal PE. The DDC91receives the power supply voltage Vdd output from the power supply circuit51via a terminal PIN, adjust the level of the power supply voltage Vdd to a level suitable for charging the back-up battery93(for example, step down or boost), and supplies the result to the back-up battery93. A terminal OUT of the low voltage monitor circuit52is connected to a control output terminal PD and an enable terminal EN of the DDC92. The DDC92is in an ON state when receiving an active level control signal at the enable terminal EN, adjust the voltage in accordance with an amount of electric charges charged in the back-up battery93to a level suitable for an operation of the DDC group8(for example, boost or step down), and supplies the result to the DDC group8via a terminal POUT.