SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a gate stack structure including a plurality of conductive layers stacked to be spaced apart from each other in a first direction, the gate stack structure surrounding the periphery of a polygonal opening. The semiconductor memory device also includes a stepped structure formed along a sidewall of the polygonal opening.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2022-0082440, filed on Jul. 5, 2022, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

1. Technical Field

The present disclosure generally relates to a semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device.

2. Related Art

A semiconductor memory device includes a memory cell array and a peripheral circuit structure connected to the memory cell array. The memory cell array includes a plurality of memory cells capable of storing data. The peripheral circuit structure may supply various operating voltages to the memory cells, and control various operations of the memory cells.

A memory cell array of a three-dimensional semiconductor memory device may include a plurality of memory cells stacked in one direction. As the stacked number of memory cells is increased, the degree of integration of the three-dimensional semiconductor memory device may be improved, and the stacked number of conductive layers used as gate electrodes of the memory cells may be increased.

SUMMARY

In accordance with an embodiment of the present disclosure is a semiconductor memory device including: a gate stack structure including a cell array region, a first region adjacent to the cell array region, second and third regions which extend from the first region in a direction away from the cell array region and face each other, and a fourth region which faces the first region and connects the second region to the third region; a first sub-stepped structure disposed in the first region of the gate stack structure; a second sub-stepped structure disposed in the second region of the gate stack structure; a third sub-stepped structure disposed in the third region of the gate stack structure; and a fourth sub-stepped structure disposed in the fourth region of the gate stack structure, wherein the first, second, third, and fourth sub-stepped structures are disposed at different levels in a first direction.

In accordance with an embodiment of the present disclosure is a semiconductor memory device including: a first stack structure including a plurality of first conductive layers stacked to be spaced apart from each other in a first direction, the plurality of first conductive layers surrounding a first opening; a second stack structure including a plurality of second conductive layers stacked on the first stack structure to be spaced apart from each other in the first direction, the plurality of second conductive layers surrounding a second opening; a third stack structure including a plurality of third conductive layers stacked on the second stack structure to be spaced apart from each other in the first direction, the plurality of third conductive layers surrounding a third opening; and a fourth stack structure including a plurality of fourth conductive layers stacked on the third stack structure to be spaced apart from each other in the first direction, the plurality of fourth conductive layers surrounding a fourth opening, wherein each of the first, second, third, and fourth openings includes a stepped sidewall, a first sidewall facing the stepped sidewall, and second and third sidewalls which are disposed between the first sidewall and the stepped sidewall and face each other, and wherein a gradient of each of the first, second, and third sidewalls is greater than a gradient of the stepped sidewall.

In accordance with an embodiment of the present disclosure is a semiconductor memory device including: a gate stack structure including a plurality of conductive layers stacked to be spaced apart from each other in a first direction, the gate stack structure surrounding the periphery of a polygonal opening; and a stepped structure formed along a sidewall of the polygonal opening, wherein, from a planar viewpoint, the stepped structure becomes lower with decreasing distance to the center of the polygonal opening, and becomes lower clockwise or counterclockwise.

In accordance with an embodiment of the present disclosure is a semiconductor memory device including: a plurality of conductive layers stacked to be spaced apart from each other in a first direction, the plurality of conductive layers connected to a memory cell array, and a stepped structure including a plurality of end portions of the plurality of conductive layers, the stepped structure continuously extending to surround an opening, wherein the stepped structure includes a first sub-stepped structure and a second sub-stepped structure adjacent to each other clockwise, wherein the plurality of conductive layers include lower conductive layers stacked to be spaced apart from each other in the first direction and upper conductive layers stacked over the lower conductive layers to be spaced apart from each other in the first direction, wherein the first sub-stepped structure includes first end portions of the upper conductive layers, wherein the second sub-stepped structure includes second end portions of the lower conductive layers, and wherein the first end portions and the second end portions are disposed at different levels in the first direction

DETAILED DESCRIPTION

The specific structural and functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be modified in various forms and replaced with other equivalent embodiments. Thus, the present disclosure should not be construed as limited to the embodiments set forth herein.

It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and the order or number of components is not limited by the terms.

Embodiments provide a semiconductor memory device capable of improving a degree of integration.

FIG.1is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present disclosure.

Referring toFIG.1, the semiconductor memory device50may include a peripheral circuit structure40and a memory cell array10.

The peripheral circuit structure40may be configured to perform a program operation for storing data in the memory cell array10, a read operation for outputting data stored in the memory cell array10, and an erase operation for erasing data stored in the memory cell array10. In an embodiment, the peripheral circuit structure40may include an input/output circuit21, a control circuit23, a voltage generating circuit31, a row decoder33, a column decoder35, a page buffer37, and a source line driver39.

The memory cell array10may include a plurality of memory cells which are three-dimensionally arranged. Each memory cell may be provided for a NAND flash memory device. Hereinafter, the embodiment of the present disclosure is described based on the memory cell array10of the NAND flash memory device, but the present disclosure is not limited thereto. In an embodiment, the memory cell array10may include a plurality of memory cells for a variable resistance memory device or a plurality of memory cells for a ferroelectric memory device.

The plurality of memory cells for the NAND flash memory device may form a plurality of memory cell strings. Each memory cell string may be connected to a drain select line DSL, a plurality of word lines WL, a source select line SSL, a plurality of bit lines BL, and a common source line CSL.

The input/output circuit21may transfer, to the control circuit23, a command CMD and an address ADD, which received from an external device (e.g., a memory controller) of the semiconductor memory device50. The input/output circuit21may exchange data DATA with the external device and the column decoder35.

The control circuit23may output an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD in response to the command CMD and the address ADD.

The voltage generating circuit31may generate various operating voltages Vop used for a program operation, a read operation, and an erase operation in response to the operation signal OP_S.

The row decoder33may transfer the operating voltages Vop to the drain select line DSL, the word lines WL, and the source select line SSL in response to the row address RADD.

The column decoder35may transmit data DATA input from the input/output circuit21to the page buffer37or transmit data DATA stored in the page buffer37to the input/output circuit21in response to the column address CADD. The column decoder35may exchange data DATA with the input/output circuit21through a column line CL. The column decoder35may exchange data DATA with the page buffer through a data line DL.

The page buffer37may temporarily store data DATA received through the bit line BL in response to the page buffer control signal PB_S. The page buffer37may sense a voltage or current of the bit line BL in a read operation.

The source line driver39may control a voltage applied to the common source line CSL in response to the source line control signal SL_S.

To improve the degree of integration of the semiconductor memory device, the memory cell array10may overlap with the peripheral circuit structure40.

FIGS.2A and2Bare views illustrating arrangements of a peripheral circuit structure, a memory cell array, a plurality of bit lines, and a doped semiconductor structure in accordance with embodiments of the present disclosure.

Referring toFIGS.2A and2B, a semiconductor memory device may include a doped semiconductor structure DSP, a memory cell array10, and a plurality of bit lines BL. The doped semiconductor structure DSP may include at least one of an n-type impurity and a p-type impurity. The doped semiconductor structure DPS may include a surface facing the plurality of bit lines BL. Hereinafter, a direction in which the surface of the above-described doped semiconductor structure DPS faces the plurality of bit lines is defined as a first direction DR1. In an embodiment, the first direction DR1may be a Z-axis direction.

The memory cell array10may be disposed between the plurality of bit lines BL and the doped semiconductor structure DPS.

Referring toFIG.2A, a peripheral circuit structure40of the semiconductor memory device may be adjacent to the doped semiconductor structure DPS. Although not shown in the drawing, a plurality of interconnections may be disposed between the peripheral circuit structure40and the doped semiconductor structure DPS, or a plurality of interconnections and a plurality of conductive bonding pads may be disposed between the peripheral circuit structure40and the doped semiconductor structure DPS.

Referring toFIG.2B, the peripheral circuit structure40of the semiconductor memory device may be adjacent to the plurality of bit lines BL. Although not shown in the drawing, a plurality of interconnections may be disposed between the peripheral circuit structure40and the plurality of bit lines BL, or a plurality of interconnections and a plurality of conductive bonding pads may be disposed between the peripheral circuit structure40and the plurality of bit lines BL.

Referring toFIGS.2A and2B, the doped semiconductor structure DPS, the memory cell array10, and the plurality of bit lines BL may overlap with the peripheral circuit structure40. From a planar viewpoint, the plurality of bit lines BL may extend in a second direction DR2, and be arranged in a third direction DR3. From a planar viewpoint, the second direction DR2and the third direction DR3may be defined as directions in which axes intersecting each other face. In an embodiment, the second direction DR2may be an X-axis direction, and the third direction DR3may be a Y-axis direction.

A process for forming the memory cell array10may be performed in various manners. In an embodiment, the process for forming the memory cell array10may be performed on the peripheral circuit structure40. In another embodiment, a first structure including the memory cell array10may be formed separately from a second structure including the peripheral circuit structure40. The first structure and the second structure may be bonded to each other through a plurality of conductive bonding pads.

The memory cell array10may be connected to the common source line CSL shown inFIG.1via the doped semiconductor structure DPS. The memory cell array10may be connected to the plurality of bit lines BL via a plurality of bit line connection structures. The memory cell array10may include a plurality of conductive layers stacked to be spaced apart from each other in the first direction DR1. The plurality of conductive layers may be provided as the plurality of word lines, the drain select line, and the source select line, which are described with reference toFIG.1. The plurality of conductive layers of the memory cell array10may be connected to the peripheral circuit structure40via a plurality of conductive contacts and a plurality of conductive lines.

FIG.3is a circuit diagram illustrating a memory cell array and a block select circuit structure in accordance with an embodiment of the present disclosure.

Referring toFIG.3, a memory cell array may include a plurality of cell strings CS. Each memory cell string CS may include at least one lower select transistor LST, a plurality of memory cells MC, and at least one upper select transistor UST.

The plurality of memory cells MC may be connected in series between the lower select transistor LST and the upper select transistor DST. One of the lower select transistor LST and the upper select transistor DST may be used as a source select transistor, and the other of the lower select transistor LST and the upper select transistor DST may be used as a drain select transistor. The plurality of memory cells MC may be connected to the doped semiconductor structure DPS shown inFIG.2A or2Bvia the source select transistor. The plurality of memory cells MC may be connected to a corresponding bit line among the plurality of bit lines BL shown inFIG.2A or2Bvia the drain select transistor.

The plurality of memory cells MC may be respectively connected to a plurality of word lines WL. An operation of each memory cell MC may be controlled by a gate signal applied to a word line WL corresponding thereto. The lower select transistor LST may be connected to a lower select line LSL. An operation of the lower select transistor LST may be controlled by a gate signal applied to the lower select line LSL. The upper select transistor UST may be connected to an upper select line USL. An operation of the upper select transistor UST may be controlled by a gate signal applied to the upper select line USL.

The lower select line LSL, the upper select line USL, and the plurality of word lines WL may be connected to a block select circuit structure BSC. The block select circuit structure BSC may be included in the row decoder33described with reference toFIG.1. In an embodiment, the block select circuit structure BSC may include a plurality of pass transistors PT respectively connected to the lower select line LSL, the upper select line USL, and the plurality of word lines WL. A plurality of gate electrodes of the plurality of pass transistors PT may be connected to a block select line BSEL. The plurality of pass transistors PT may be configured to transfer signals applied to a plurality of global lines GLSL, GUSL, and GWL to the lower select line LSL, the upper select line USL, and the plurality of word lines WL in response to a block select signal applied to the block select line BSEL.

The block select circuit structure BSC may be connected to the lower select line LSL, the upper select line USL, and the plurality of word lines WL via a plurality of conductive contacts GCT and PCT and a plurality of conductive lines CPL. The plurality of conductive contacts GCT and PCT may include a plurality of conductive gate contacts GCT and a plurality of conductive peripheral circuit contacts PCT. The plurality of conductive gate contacts GCT may be connected to the lower select line LSL, the upper select line USL, and the plurality of word lines WL. The plurality of conductive peripheral circuit contacts PCT may be connected to the block select circuit structure BSC of the peripheral circuit structure. The plurality of conductive lines CPL may be configured to connect the plurality of conductive gate contacts GCT to the plurality of conductive peripheral circuit contacts PCT.

The plurality of conductive gate contacts GCT described above may be connected to a plurality of conductive layers provided as the lower select line LSL, the upper select line USL, and the plurality of word lines WL. The plurality of conductive layers may be stacked to be spaced apart from each other in the first direction DR1to form a gate stack structure. The plurality of conductive layers may be formed in a stepped structure to provide an area (landing area) which the plurality of conductive gate contacts GCT reach.

FIG.4is a plan view illustrating a gate stack structure of a semiconductor memory device in accordance with embodiments of the present disclosure.

Referring toFIG.4, the semiconductor memory device may include a plurality of gate stack structures GST partitioned by a slit153. Each gate stack structure GST may include a cell array region CAR and a contact region CTR extending from the cell array region CAR.

The gate stack structure GST may include a plurality of horizontal layers L1to L14stacked in the first direction DR1. Each of the horizontal layers L1to L14may extend along the second direction DR2and the third direction DR3intersecting each other from a planar viewpoint.

Each of the horizontal layers L1to L14may extend from the cell array region CAR to the contact region CTR. The plurality of horizontal layers L1to L14may form a stepped structure in the contact region CTR.

The contact region CTR may include an opening163. The gate stack structure GST in the contact region CTR may surround the periphery of the opening163. The opening163may have a polygonal shape such as a triangular shape or a quadrangular shape from a planar viewpoint, and the contact region CTR may include at least three regions continuously arranged clockwise or counterclockwise. In an embodiment, the opening163may have a quadrangular shape from a planar viewpoint, and the contact region CTR may include a first region AR1, a second region AR2, a third region AR3, and a fourth region AR4. The first region AR1may be adjacent to the cell array region CAR. The second region AR2and the third region AR3may extend from the first region AR1in a direction away from the cell array region CAR and face each other. The fourth region AR1may connect the second region AR2and the third region AR3to each other and face the first region AR1. Accordingly, it may be considered that the first region AR1, the second region AR2, the fourth region AR4, and the third region AR3are continuously arranged while surrounding the periphery of the quadrangular opening163clockwise.

The gate stack structure GST may include a stepped structure surrounding the periphery of the opening163. The stepped structure may have a step difference changed clockwise or counterclockwise along regions around the opening regions163. The stepped structure may include at least three sub-stepped structures corresponding to the above-described at least three regions. Each sub-stepped structure may become lower as becoming closer to the center thereof. Hereinafter, the embodiment of the present disclosure will be described in detail, based on a case where the stepped structure includes first to fourth sub-stepped structures SS1to SS4respectively corresponding to the first to fourth regions AR1to AR4around the opening163.

The first sub-stepped structure SS1may be formed in the first region AR1, the second sub-stepped structure SS2may be formed in the second region AR2, the third sub-stepped structure SS3may be formed in the third region AR3, and the fourth sub-stepped structure SS4may be formed in the fourth region AR4. Each of the first to fourth sub-stepped structures SS1to SS4may become lower as becoming closer to the center of the opening163. More specifically, the first sub-stepped structure SS1may become lower as becoming more distant from the cell array region CAR. The second sub-stepped structure SS2may become lower as becoming closer to the third region AR3. The third sub-stepped structure SS3may become lower as becoming closer to the second region AR2. The fourth sub-stepped structure SS4may become lower as becoming closer to the first area AR1.

The opening163may include a stepped sidewall corresponding to each sub-stepped structure. In an embodiment, the opening163may include a first stepped sidewall SW1corresponding to the third sub-stepped structure SS3, a second stepped sidewall SW2corresponding to the fourth sub-stepped structure SS4, a third stepped sidewall SW3corresponding to the second sub-stepped structure SS2, and a fourth stepped sidewall SW4corresponding to the first sub-stepped structure SS1.

The first to fourth sub-stepped structures SS1to SS4or the first to fourth stepped sidewalls SW1to SW4may be located at different levels in the first direction DR1. Each of the first stepped sidewall SW1and the third sub-stepped structure SS3may be formed with a plurality of first horizontal layers L1, L2, and L3, and each of the second stepped sidewall SW2and the fourth sub-stepped structure SS4may be formed with a plurality of second horizontal layers L4, L5, and L6. Each of the third stepped sidewall SW3and the second sub-stepped structure SS2may be formed of a plurality of third horizontal layer L7, L8, and L9, and each of the fourth stepped sidewall SW4and the first sub-stepped structure SS1may be formed of a plurality of fourth horizontal layers L10, L11, and L12. The number of horizontal layers constituting each sub-stepped structure is not limited to the number shown in the drawing and may vary.

The plurality of horizontal layers may include the above-described first to fourth horizontal layers L1to L12, and further include at least one horizontal layer disposed on the plurality of fourth horizontal layers L10, L11, and L12. In an embodiment, the plurality of horizontal layers may further include a fifth horizontal layer L13and a sixth horizontal layer L14, which are stacked in the first direction DR1on the plurality of fourth horizontal layers L10, L11, and L12. The sixth horizontal layer L14may be isolated into two or more line structures L14A, L14B, and L14C by a line insulating structure173. Each of the plurality of first to fourth horizontal layers L1to L12and the fifth horizontal layer L13may continuously extend in the second direction DR2and the third direction DR3not to be penetrated by the line insulating structure173but to overlap with the two or more line structures L14A, L14B, and L14C. The fifth horizontal layer L13may protrude laterally toward the contact region CTR as compared with the sixth horizontal layer14, and surround the first to fourth regions AR1to AR4in the contact region CTR.

The plurality of horizontal layers L1to L14may extend to the contact region CTR from the cell array region CAR. The plurality of first horizontal layers L1, L2, and L3may continuously extend to the first to fourth regions AR1to AR4from the cell array region CAR. The plurality of second horizontal layers L4, L5, and L6may continuously extend to the first region AR1, the second region AR2, and the fourth region AR4from the cell array region CAR. The plurality of third horizontal layers L7, L8, and L9may continuously extend to the first region AR1and the second region AR2from the cell array region CAR. The plurality of fourth horizontal layers L10, L11, and L12may continuously extend to the first region AR1from the cell array region CAR.

The plurality of horizontal layers L1to L14in the cell array region CAR may be penetrated by a plurality of cell plugs120extending in the first direction DR1. The memory cell string CS shown inFIG.3may be defined along each cell plug120.

FIGS.5A,5B, and5Care sectional views illustrating a semiconductor memory device in accordance with embodiments of the present disclosure.FIGS.5A to5Cillustrate sectional views of the semiconductor memory device taken along line I-I′ shown inFIG.4. Hereinafter, repeated descriptions of components identical to the above-described components will be omitted.

Referring toFIGS.5A to5C, the semiconductor memory device may include a doped semiconductor structure DPS, a first insulating layer113on the doped semiconductor structure DPS, a plurality of horizontal layers L1to L14stacked on the first insulating layer113, at least one interposition insulating layer151and175on the plurality of horizontal layers L1to L14, and a bit line BL on the at least one interposition insulating layer151and175. Hereinafter, the embodiments of the present disclosure are described based on an example in which the bit line BL is spaced apart from the plurality of horizontal layers L1to L14with a first interposition insulating layer151and a second interposition insulating layer175on the first interposition insulating layer151, which are interposed therebetween, but the present disclosure is not limited thereto.

The doped semiconductor structure DPS may include at least one doped semiconductor layer.

Referring toFIG.5A, the doped semiconductor layer DPS may include a first doped semiconductor layer101, a second doped semiconductor layer103, and a third doped semiconductor layer105, which are stacked in the first direction DR1. Each of the first doped semiconductor layer101, the second doped semiconductor layer103, and the third doped semiconductor layer105may include at least one of an n-type impurity and a p-type impurity. In an embodiment, the first doped semiconductor layer101, the second doped semiconductor layer103, and the third doped semiconductor layer105may include an impurity of the same conductivity type as a majority carrier. In another embodiment, the first doped semiconductor layer101may include, as a majority carrier, an impurity of a conductivity type opposite to a conductivity type of the second doped semiconductor layer103and the third doped semiconductor layer105.

Referring toFIGS.5B and5C, the doped semiconductor structure DSP may include a single doped semiconductor layer107or109. The doped semiconductor layer107or109may include at least one of an n-type impurity and a p-type impurity. In an embodiment, the doped semiconductor layer107or109may include an n-type impurity as a majority carrier. In another embodiment, the doped semiconductor layer107or109may include a p-type impurity as a majority carrier. In still another embodiment, the doped semiconductor layer107or109may include a source region including an n-type impurity as a majority carrier and a well region including a p-type impurity as a majority carrier.

The first insulating layer113may extend in the second direction DR2and the third direction DR3to cover a surface of the doped semiconductor structure DPS, which faces in the first direction DR1.

The plurality of horizontal layers L1to L14may be stacked in the first direction DR1on the first insulating layer113. The plurality of horizontal layers L1to L14may be configured with a plurality of conductive layers115A to115F and a plurality of interlayer insulating layers117A to117F alternately disposed in the first direction DR1with the plurality of conductive layers115A to115F. The plurality of conductive layers115A to115F may constitute a plurality of pairs with the plurality of interlayer insulating layers117A to117F. The plurality of pairs may respectively correspond to the plurality of horizontal layers. For example, a first horizontal layer L1may be formed with a pair of a first conductive layer115A and a first interlayer insulating layer117, which correspond thereto.

A plurality of first conductive layers115A and a plurality of first interlayer insulating layers117A of a plurality of first horizontal layers L1, L2, and L3may form a first stack structure ST1. The plurality of first conductive layers115of the first stack structure ST1may be spaced apart from each other in the first direction DR1by the first interlayer insulating layers117A. A plurality of second conductive layers1158and a plurality of second interlayer insulating layers1178of a plurality of second horizontal layers L4, L5, and L6may form a second stack structure ST2. The second stack structure ST2may be disposed on the first stack structure ST1. The plurality of second conductive layers1158may be spaced apart from each other in the first direction DR1by the plurality of second interlayer insulating layers1178. A plurality of third conductive layers115C and a plurality of third interlayer insulating layers117C of a plurality of horizontal layers L7, L8, and L9may form a third stack structure ST3. The third stack structure ST3may be disposed on the second stack structure ST2. The plurality of third conductive layers115C may be spaced apart from each other in the first direction DR1by the plurality of third interlayer insulating layers117C. A plurality of fourth conductive layers115D and a plurality of fourth interlayer insulating layers117D of a plurality of fourth horizontal layers L10, L11, and L12may form a fourth stack structure ST4. The fourth stack structure ST4may be disposed on the third stack structure ST3. A fifth horizontal layer L13may include a fifth conductive layer115E and a fifth interlayer insulating layer117E, which are stacked on the fourth stack structure ST4, and a sixth horizontal layer L14may include a sixth conductive layer115F and a sixth interlayer insulating layer117F, which are stacked on the fifth horizontal layer L13.

Among the first to sixth conductive layers115A to115F of the plurality of horizontal layers L1to L14, at least one conductive layer adjacent to the doped semiconductor structure DSP may be provided as a source select line, at least one conductive layer adjacent to the bit line BL may be provided as a drain select line, and the other conductive layers may be provided as a plurality of word lines. In an embodiment, a lowermost first conductive layer adjacent to the doped semiconductor structure DSP among the plurality of first conductive layers115A may be provided as a source select line, and the sixth conductive layer115F may be provided as a drain select line. The line insulating structure173may penetrate the sixth conductive layer115F to partition the drain select line.

A cell plug120A,120B, or120C may penetrate the plurality of horizontal layers L1to L14. The cell plug120A,120B, or120C may include a channel structure CH and a memory layer121extending along a sidewall of the channel structure CH. The channel structure CH may include a channel layer123and a capping doped semiconductor pattern127. The channel layer123may be provided as a channel of a memory cell string. The channel layer123may include a semiconductor material such as silicon, germanium, or any combination thereof. The channel layer123may be formed to have a hollow type. When the channel layer123is formed to have the hollow type, a central region of the channel layer123may be filled with a core insulating layer125and the capping doped semiconductor pattern127. The capping doped semiconductor pattern127may fill a top end of the central region of the channel layer123on the core insulating layer125. Although not shown in the drawings, the memory layer121may include a tunnel insulating layer surrounding an outer wall of the channel structure CH, a data storage layer surrounding an outer wall of the tunnel insulating layer, and a blocking insulating layer surrounding an outer wall of the data storage layer. The data storage layer may include a charge trap layer, a floating gate layer, a variable resistance layer, or a ferroelectric layer. In an embodiment, the data storage layer may be formed of a nitride layer in which charges can be trapped. The blocking insulating layer may include oxide capable of blocking charges, and the tunnel insulating layer may include silicon oxide through which charges can tunnel.

The cell plug120A,120B, or120C may extend to penetrate the first interposition insulating layer151. The second interposition insulating layer175may extend in the second direction DR2and the third direction DR3to cover the first interposition insulating layer151and the cell plug120A,120B, or120C.

The bit line BL may be connected to the capping doped semiconductor pattern127of a cell plug120A,120B, or120C corresponding thereto via a bit line connection structure179penetrating the second interposition insulating layer175.

The doped semiconductor structure DPS may form a contact surface with the channel layer123of the cell plug120A,120B, or120C in various manners.

Referring toFIG.5A, the channel layer123of the cell plug120A may penetrate the third doped semiconductor layer105of the doped semiconductor structure DPS, and extend to the inside of the first doped semiconductor layer101. The channel layer123may extend along a surface of the core insulating layer125, which faces in the opposite direction of the first direction DR1. The second doped semiconductor layer103may be in contact with a portion of a sidewall of the channel layer123between the first doped semiconductor layer101and the third doped semiconductor layer105, and surround the portion of the sidewall of the channel layer123. Accordingly, the contact surface between the doped semiconductor structure DSP and the channel layer123may be defined as the second doped semiconductor layer103and the portion of the sidewall of the channel layer123are in contact with each other. The memory layer121may be isolated into a first memory pattern121A and a second memory pattern121B by the second doped semiconductor layer103. The first memory pattern121A may be disposed between the channel layer123and the first doped semiconductor layer101, and the second memory pattern121B may extend in the first direction DR1along the sidewall of the channel layer123from between the channel layer123and the third doped semiconductor layer105.

Referring toFIG.5B, the channel layer123of the cell plug120B may be in contact with the surface of the doped semiconductor structure DPS, which faces in the first direction DR1. The channel layer123may extend between the doped semiconductor structure DSP and the core insulating layer125to have a closed end portion facing the doped semiconductor structure DPS. Accordingly, the contact surface between the doped semiconductor structure DPS and the channel layer123may be defined as the closed end portion of the channel layer123and the doped semiconductor structure DPS are in contact with each other.

Although not shown in the drawing, an epitaxial lower channel layer may be additionally disposed between the channel layer123and the doped semiconductor structure DPS. The epitaxial lower channel layer and the doped semiconductor structure DPS may be in contact with each other, and the channel layer123may be connected to the doped semiconductor structure DPS via the epitaxial lower channel layer.

Referring toFIG.5C, the channel layer123of the cell plug120C may extend to the inside of the doped semiconductor structure DPS. The channel layer123may extend to be interposed between the core insulating layer125and the doped semiconductor structure DPS. The channel layer123may include a protrusion part protruding to the inside of the doped semiconductor structure DPS as compared with the memory layer121. The protrusion part of the channel layer123may form a contact surface with the doped semiconductor structure DPS.

The memory cell string CS described with reference toFIG.3may be defined along the channel layer123shown inFIGS.5A to5C. Specifically, a source select transistor may be formed at an intersection portion of a conductive layer (e.g., a lowermost layer115A) provided as a source select line among the first to sixth conductive layers115A to115F shown inFIGS.5A to5Cand the channel layer123, and a drain select transistor may be formed at an intersection portion of a conductive layer (e.g.,115F) provided as a drain select line among the first to sixth conductive layers115A to115F shown inFIGS.5A to5Cand the channel layer123. In addition, a plurality of memory cells may be formed at intersection portions of a plurality of conductive layers (e.g.,1158to115E) provided as a plurality of word lines among the first to sixth conductive layers115A to115F shown inFIGS.5A to5Cand the channel layer123. The source select transistor, the plurality of memory cells, and the drain select transistor, which are described above, may be connected in series by the channel layer123shown inFIGS.5A to5Cto form the memory cell string CS shown inFIG.3.

FIG.6is a plan view illustrating a connection structure of a semiconductor memory device in accordance with embodiments of the present disclosure. Hereinafter, repeated descriptions of components identical to the above-described components will be omitted.

Referring toFIG.6, a plurality of conductive layers115A to115F corresponding to a plurality of horizontal layers L1to L14may include an end portion disposed in a contact region CTR. The end portion of the plurality of conductive layers115A to115F may form a stepped structure in the contact region CTR.

An end portion of a plurality of first conductive layers115A, an end portion of a plurality of second conductive layers1158, an end portion of a plurality of third conductive layers115C, and an end portion of a plurality of fourth conductive layers115D may form first to fourth sub-stepped structures SS1to SS4as described with reference toFIG.4. Specifically, the third sub-stepped structure SS3corresponding to a first stepped sidewall SW1of an opening163may be formed by the end portion of the plurality of conductive layers115A, and the fourth sub-stepped structure SS4corresponding to a second stepped sidewall SW2of the opening163may be formed by the end portion of the second conductive layers115B. In addition, the second sub-stepped structure SS2corresponding to a third stepped sidewall SW3of the opening163may be formed by the end portion of the plurality of third conductive layers115C, and the first sub-stepped structure SS1corresponding to a fourth stepped sidewall SW4of the opening163may be formed by the end portion of the plurality of fourth conductive layers115D.

A fifth conductive layer115E and a sixth conductive layer115F do not overlap with the first to fourth sub-stepped structures SS1to SS4in the contact region CTR, and may include an end portion exposed by the stepped structure.

A plurality of conductive gate contacts GCT1, GCT2, and GCT3may be connected to the end portion of the above-described plurality of conductive layers115A to115F. The plurality of conductive gate contacts GCT1, GCT2, and GCT3may extend in the first direction DR1from the end portion of the plurality of conductive layers115A to115F. The plurality of conductive gate contacts GCT1, GCT2, and GCT3may be connected to a plurality of conductive peripheral circuit contacts PCT1, PCT2, and PCT3through a plurality of conductive lines CPL1, CPL2, and CPL3. The plurality of conductive peripheral circuit contacts PCT1, PCT2, and PCT3may be disposed in the opening163, and extend in the first direction DR1.

The plurality of conductive gate contacts GCT1, GCT2, and GCT3may include a plurality of first conductive gate contacts GCT1, a second conductive gate contact GCT2, and a third conductive gate contact GCT3. The plurality of first conductive gate contacts GCT1may extend in the first direction DR1from the first to fourth conductive layers115A to115D of the first to fourth sub-stepped structures SS1to SS4. The second conductive gate contact GCT2may extend in the first direction DR1from the fifth conductive layer115E. The third conductive gate contact GCT may extend in the first direction DR1from the sixth conductive layer115F.

The plurality of conductive lines CPL1, CPL2, and CPL3may include a plurality of first conductive lines CPL1corresponding to the first conductive gate contacts GCT1, a second conductive line CPL2corresponding to the second conductive gate contact GCT2, and a third conductive line CPL3corresponding to the third conductive gate contact GCT3. The plurality of conductive peripheral circuit contacts PCT1, PCT2, and PCT3may include a plurality of first conductive peripheral circuit contacts PCT1corresponding to the plurality of first conductive lines CPL1, a second conductive peripheral circuit contact PCT2corresponding to the second conductive line CPL2, and a third conductive peripheral circuit contact PCT3corresponding to the third conductive line CPL3.

A stepped structure having a step difference changed clockwise or counterclockwise may be defined by the first to fourth sub-stepped structures SS1to SS4in accordance with the embodiments of the present disclosure. In addition, a plurality of first to fourth horizontal layers L1to L12may be continuous toward the cell array region CAR shown inFIG.4from the end portions defining the first to fourth sub-stepped structures SS1to SS4. The arrangement efficiency of the plurality of first conductive gate contacts GCT1, the plurality of first conductive peripheral circuit contacts PCT, and the plurality of first conductive lines CPL1per area may be improved by the above-described first to fourth sub-stepped structures SS1to SS4.

FIG.7is a sectional view illustrating a semiconductor memory device taken along line II-II′ shown inFIG.6in accordance with embodiments of the present disclosure. Hereinafter, repeated descriptions of components identical to the above-described components will be omitted.

Referring toFIG.7, a plurality of horizontal layers L1to L14on a first insulating layer113may form a stepped structure, and the stepped structure may be covered with a filling insulating layer141. The filling insulating layer114may be formed to fill the opening163shown inFIG.6, and a surface of the filling insulating layer114may be planarized. A first interposition insulating layer151and a second interposition insulating layer175may extend to overlap with the filling insulating layer141.

Each of a plurality of conductive gate contacts may extend in the first direction DR1from a conductive layer corresponding thereto among a plurality of conductive layers115A to115F, and penetrate an interlayer insulating layer corresponding thereto among a plurality of interlayer insulating layers117A to117F, the filling insulating layer141, the first interposition insulating layer151, and the second interposition insulating layer175. For example, a first conductive gate contact GCT1may extend in the first direction DR1from a conductive layer (e.g.,115D) corresponding thereto among a plurality of first to fourth conductive layers115A to115D of first to fourth stack structures ST1to ST4, and penetrate an interlayer insulating layer (e.g.,117D) corresponding thereto among a plurality of first to fourth interlayer insulating layers117A to117D of the first to fourth stack structures ST1to ST4.

The semiconductor memory device may include a peripheral circuit structure overlapping with a doped semiconductor structure DPS. The peripheral circuit structure may include a plurality of transistors TR. The plurality of transistors TR may include the pass transistor PT of the block select circuit structure BSC shown inFIG.3.

Each of the plurality of transistors TR may include a gate insulating layer213and a gate electrode215, which are stacked on an active region of a semiconductor substrate201, and include junctions211formed in the active region at both sides of the gate electrode215. The semiconductor substrate201may extend in the second direction DR2and the third direction DR3. The active region of the semiconductor substrate201may be partitioned by an isolation layer203. The junctions211are regions defined by implanting at least one of an n-type impurity and a p-type impurity into the active region of the semiconductor substrate201, and may be provided as a source region and a drain region.

An insulating structure219may be disposed between the plurality of transistors TR and the doped semiconductor structure DPS. The doped semiconductor structure DPS may be insulated from the plurality of transistors TR by the insulating structure219.

The insulating structure219may include multi-layered insulating layers. First to third connection structures217A to217C connected to each transistor TR may be buried inside the insulating structure219. Each of the first third connection structures217A to217C may be configured with conductive patterns having various structures. The first and second connection structures217A and217B may be respectively connected to the junctions211of the transistor TR, and the third connection structure217C may be connected to the gate electrode215of the transistor TR.

The doped semiconductor structure DPS may be partitioned by a source insulating layer111. The source insulating layer111may be disposed at the substantially same level as the doped semiconductor structure DPS.

The plurality of conductive peripheral circuit contacts may extend in the first direction DR1from a connection structure corresponding thereto among the first to third connection structures217A to217C, and penetrate the insulating structure219, the source insulating layer111, the first insulating layer113, the filling insulating layer141, the first interposition insulating layer151, and the second interposition insulating layer175. For example, a first conductive peripheral circuit contact PCT1may extend in the first direction DR1from the first connection structure217A connected to the pass transistor of the block select circuit structure among the plurality of transistors TR.

Each of a plurality of conductive lines may be disposed on the second interposition insulating layer175, and connect a conductive gate contact corresponding thereto and a conductive peripheral circuit contact to each other. For example, a first conductive line CPL1may connect the first conductive gate contact GCT1and the conductive peripheral circuit contact PCT1to each other.

FIG.8is a perspective view illustrating a contact region of a gate stack structure in accordance with embodiments of the present disclosure. Hereinafter, repeated descriptions of components identical to the above-described components will be omitted.

Referring toFIG.8, a plurality of first to fourth horizontal lines L1to L12may be divided into 4N (N is a natural number equal to or greater than 2) horizontal layers, and each of a plurality of first horizontal layers L1, L2, and L3, a plurality of second horizontal layers L4, L5, and L6, a plurality of third horizontal layers L7, L8, and L9, and a plurality of fourth horizontal layers L10, L11, and L12may be equally configured with N horizontal layers. For example, the plurality of first horizontal layers L1, L2, and L3may be configured with three horizontal layers, and the plurality of first to fourth horizontal layers L1to L12may be configured with twelve horizontal layers.

The plurality of first horizontal layers L1, L2, and L3, the plurality of second horizontal layers L4, L5, and L6, the plurality of third horizontal layers L7, L8, and L9, and the plurality of fourth horizontal layers L10, L11, and L12may define a first step difference changed toward the center of an opening163and a second step difference D2changed clockwise or counterclockwise. The second step difference D2may be greater than the first step difference D1. In an embodiment, the first step difference D1may correspond to only a thickness of each horizontal layer in the first direction DR1, and the second step difference D2may correspond to a total thickness of N horizontal layers in the first direction DR1.

FIGS.9A and9Bare exploded perspective views illustrating a contact region of a gate stack structure in accordance with embodiments of the present disclosure. Hereinafter, repeated descriptions of components identical to the above-described components will be omitted.

Referring toFIGS.9A and9B, a plurality of first conductive layers115A and a plurality of first interlayer insulating layers117A of a first stack structure ST1may surround a first opening163A, and a plurality of second conductive layers115B and a plurality of second interlayer insulating layers117B of a second stack structure ST2may surround a second opening1638. In addition, a plurality of third conductive layers115C and a plurality of third interlayer insulating layers117C of a third stack structure ST3may surround a third opening163C, and a plurality of fourth conductive layers115D and a plurality of fourth interlayer insulating layers117D of a fourth stack structure ST4may surround a fourth opening163D.

The first to fourth openings163A to163D may be connected to each other to form the opening163shown inFIG.8. Each of the first to fourth openings163A to163D may include a stepped sidewall SW1, SW2, SW3, or SW4, a first sidewall1S1,2S1,3S1, or4S1, a second sidewall1S2,2S2,3S2, or4S2, and a third sidewall1S3,2S3,3S3, or4S3.

The stepped sidewall may include a first stepped sidewall SW1of the first opening163A, a second stepped sidewall SW2of the second opening1638, a third stepped sidewall SW3of the third opening163C, and a fourth stepped sidewall SW4of the fourth opening163D. The first to fourth stepped sidewalls SW1to SW4may face in different directions. For example, the first stepped sidewall SW1may face in the second direction DR2, the second stepped sidewall SW2may face in the third direction DR3, the third stepped sidewall SW3may face in a direction opposite to the second direction DR2, and the fourth stepped sidewall SW4may face in a direction opposite to the third direction DR3.

The first sidewall1S1,2S1,3S1, or4S1may be disposed to face a stepped sidewall SW1, SW2, SW3, or SW4corresponding thereto. The second sidewall1S2,2S2,3S2, or4S2and the third sidewall1S3,2S3,3S3, or4S3may be disposed between the stepped sidewall SW1, SW2, SW3, or SW4and the first sidewall1S1,2S1,3S1, or4S1. The second sidewall1S2,2S2,3S2, or4S2may face a third sidewall1S3,2S3,3S3, or4S3corresponding thereto. A gradient of each of the first sidewall1S1,2S1,3S1, or4S1, the second sidewall1S2,2S2,3S2, or4S2, and the third sidewall1S3,2S3,3S3, or4S3may be greater than a gradient of the stepped sidewall SW1, SW2, SW3, or SW4. For example, a gradient θ2of each of first, second, and third sidewalls3S1,3S2, and3S3of the third opening163C may be greater than a gradient θ1of the third stepped sidewall SW3.

The first stepped sidewall SW1may be exposed by the second, third, and fourth openings163B,163C, and163D, the second stepped sidewall SW2may be exposed by the third and fourth openings163C and163D, and the third stepped sidewall may be exposed by the fourth opening163D.

The plurality of first conductive layers115A are disposed more distant from the center of the first opening163A as becoming closer to the second stack structure ST2, to form the first stepped sidewall SW1. The plurality of second conductive layers115B are disposed closer to the center of the second opening163B as becoming closer to the first stack structure ST1, to form the second stepped sidewall SW2. The plurality of third conductive layers115C are disposed more distant from the center of the third opening163C as becoming closer to the fourth stack structure ST4, to form the third stepped sidewall SW3. The plurality of fourth conductive layers115D are disposed closer to the center of the fourth opening163D as becoming closer to the third stack structure ST3, to form the fourth stepped sidewall SW4.

FIGS.10A,10B,11,12A,12B,12C, and12Dare views illustrating a manufacturing method of a stepped stack structure in accordance with embodiments of the present disclosure.

FIG.10Ais a plan view illustrating a preliminary stepped stack structure,FIG.10Bis a sectional view of the preliminary stepped stack structure taken along line III-III′ shown inFIG.10A, andFIG.11is a perspective view of the preliminary stepped stack structure.

Referring toFIGS.10A,10B, and11, the preliminary stepped stack structure PST may include an opening331, and include a plurality of preliminary horizontal layers PL1to PL14. The plurality of preliminary horizontal layers PL1to PL14of the preliminary stepped stack structure PST may have a step difference changed toward the center of the opening331.

The preliminary stepped stack structure PST may be formed on a first insulating layer313. The first insulating layer313may be formed on a pre-prepared lower structure (not shown). The lower structure may include a peripheral circuit structure and a doped semiconductor structure, or include a sacrificial substrate. Each of the preliminary horizontal layers PL1to PL14may extend along the second direction DR2and the third direction DR3, which intersect each other from a planar viewpoint.

The plurality of preliminary horizontal layers PL1to PL14may include a plurality of first preliminary horizontal layers PL1to PL3of a first preliminary stack structure PST1, a plurality of second preliminary horizontal layers PL4to PL6of a second preliminary stack structure PST2, a plurality of third preliminary horizontal layers PL7to PL9of a third preliminary stack structure PST3, a plurality of fourth preliminary horizontal layers PL10to PL12of a fourth preliminary stack structure PST4, a fifth preliminary horizontal layer PL13, and a sixth preliminary horizontal layer PL14.

The plurality of preliminary horizontal layers PL1to PL14may include a plurality of first material layers315A to315F and a plurality of second material layers317A to317F, which are alternately disposed in the first direction DR1on the first insulating layer313. The plurality of second material layers317A to317F may be formed of a material different from a material of the plurality of first material layers315A to315F. In an embodiment, each of the plurality of second material layers317A to317F may be formed of an insulating material for interlayer insulating layers, and each of the plurality of first material layers315A to315F may be formed of a material having an etch selectivity with respect to the plurality of second material layers317A to317F. In an embodiment, each of the plurality of second material layers317A to317F may include an oxide layer such as silicon oxide, and each of the plurality of first material layers315A to315F may include a nitride layer such as silicon nitride. In another embodiment, each of the plurality of second material layers317A to317F may be formed of an insulating material for interlayer insulating layers, and each of the plurality of first material layers315A to315F may be formed of a conductive material for conductive layers. Hereinafter, the manufacturing method is described based on an embodiment in which the plurality of second material layer317A to317F are provided as interlayer insulating layers and the plurality of first material layers315A to315F are provided as conductive layers, but the embodiment of the present disclosure is not limited thereto.

The plurality of first material layers315A to315F and the plurality of second material layers317A to317F may be divided into a plurality of pairs constituting the plurality of preliminary horizontal layers PL1to PL14. For example, the sixth preliminary horizontal layer PL14may be configured with a first material layer315F and a second material layer317F, which constitute a pair corresponding thereto.

The process of forming the preliminary stepped stack structure PST may include a process of exposing the fifth preliminary horizontal layer PL13by etching the first material layer315F and the second material layer317F of the sixth preliminary horizontal layer PL14, a process of forming the opening331penetrating the plurality of first preliminary horizontal layers PL1from the fifth preliminary horizontal layer PL13by etching the first to fifth preliminary horizontal layers PL1to PL13, and a process of forming a stepped structure surrounding the periphery of the opening331by using a step etching process.

The step etching process may be performed such that a first sub-stepped structure321is formed. The first sub-stepped structure321may be defined by an end portion of the plurality of fourth preliminary horizontal layers PL10to PL12. The fifth preliminary horizontal layer PL13may be etched to expose the first sub-stepped structure321.

The end portion of the plurality of fourth preliminary horizontal layers PL10to PL12may extend clockwise or counterclockwise, to form the first sub-stepped structure321surrounding the periphery of the opening331. The first sub-stepped structure321may include first to fourth regions AR1′ to AR4′ arranged clockwise or counterclockwise. The first region AR1′ may be adjacent to the sixth preliminary horizontal layer PL14. The second region AR2′ and the third region AR3′ may extend, from the first region AR1, in a direction becoming distant from the sixth preliminary horizontal layer PL14, and face each other. The fourth region AR4′ may face the first region AR1′.

FIG.12Ais a plan view illustrating a process of forming a second sub-stepped structure323.

Referring toFIG.12A, a first mask pattern351including a first opening region OP1may be formed on the preliminary stepped stack structure PST described with reference toFIGS.10A,10B, and11. The first opening region OP1may expose the second region AR2′ of the first sub-stepped structure321shown inFIG.10A. Subsequently, the end portion of the plurality of fourth preliminary horizontal layers PL10to PL12shown inFIG.10Amay be etched in the second region AR2′ of the first sub-stepped structure321shown inFIG.10A. Accordingly, an end portion of the plurality of third preliminary horizontal layers PL7to PL9may be exposed, and the second sub-stepped structure323may be defined by the end portion of the plurality of third preliminary horizontal layers PL7to PL9. After the second sub-stepped structure323is formed, the first mask pattern351may be removed.

FIG.12Bis a plan view illustrating a process of forming a third sub-stepped structure325.

Referring toFIG.12B, a second mask pattern353including a second opening region OP2may be formed on the preliminary stepped stack structure including the second sub-stepped structure323shown inFIG.12A. The second opening region OP2may expose the fourth region AR4′ of the first sub-stepped structure321shown inFIG.10A. Subsequently, the end portion of the plurality of fourth preliminary horizontal layers PL10to PL12and the end portion of the plurality of third preliminary horizontal layers PL7to PL9, which are shown inFIG.10A, may be etched in the fourth region AR4′ of the first sub-stepped structure321shown inFIG.10A. Accordingly, an end portion of the plurality of second preliminary horizontal layers PL4to PL6may be exposed, and the third sub-stepped structure325may be defined by the end portion of the plurality of second preliminary horizontal layers PL4to PL6. After the third sub-stepped structure325is formed, the second mask pattern353may be removed.

FIG.12Cis a plan view illustrating a process of forming a fourth sub-stepped structure327.

Referring toFIG.12C, a third mask pattern355including a third opening region OP3may be formed on the preliminary stepped stack structure including the third sub-stepped structure325shown inFIG.12B. The third opening region OP3may expose the third region AR3′ of the first sub-stepped structure331shown inFIG.10A. Subsequently, the end portion of the plurality of fourth preliminary horizontal layers PL10to PL12, the end portion of the plurality of third preliminary horizontal layers PL7to PL9, and the end portion of the plurality of second preliminary horizontal layers PL4to PL6, which are shown inFIG.10A, may be etched in the third region AR3′ of the first sub-stepped structure331shown inFIG.10A. Accordingly, an end portion of the plurality of first preliminary horizontal layers PL1to PL3may be exposed, and the fourth sub-stepped structure327may be defined by the end portion of the plurality of first preliminary horizontal layers PL1to PL3. After the fourth sub-stepped structure327is formed, the third mask pattern355may be removed.

FIG.12Dis a plan view illustrating a process of forming a trench341.

Referring toFIG.12D, the sixth preliminary horizontal layer PL14may be etched, thereby forming the trench341penetrating the sixth preliminary horizontal layer PL14. The sixth preliminary horizontal layer PL14may be isolated into a plurality of line patterns by the trench341.

When the plurality of first material layers315A to315F shown inFIG.10Bare formed of a nitride layer, a replace process for replacing the plurality of first material layers315A to315F with a plurality of conductive layers may be performed before the trench341is formed.

Subsequently, subsequent processes for forming conductive gate contacts, conductive peripheral circuit contacts, and conductive lines may be performed.

FIGS.13A and13Bare plan views illustrating a contact region of a gate stack structure in accordance with embodiments of the present disclosure.

Referring toFIG.13A, a plurality of horizontal layers L1A to L10A stacked in one direction may form a gate stack structure. The plurality of horizontal layers L1A to L10A may form a stepped structure surrounding the periphery of a triangular opening463A. The plurality of horizontal layers L1A to L10A may include a plurality of first horizontal layers L1A to L3A forming a first sub-stepped structure401A in a first region, a plurality of second horizontal layers L4A to L6A forming a second sub-stepped structure403A in a second region, a plurality of third horizontal layers L7A to L9A forming a third sub-stepped structure405A in a third region, and a fourth horizontal layer L10A surrounding the periphery of the first to third sub-stepped structures401A,403A, and405A.

The first to third sub-stepped structures401A,403A, and405A may become lower as becoming closer to the center of the triangular opening463A, and be located at different levels. More specifically, the first to third sub-stepped structures401A,403A, and405A may be disposed to have a step difference clockwise or counterclockwise.

Referring toFIG.13B, a plurality of horizontal layers L1B to L19B stacked in one direction may form a gate stack structure. The plurality of horizontal layers L1B to L19B may form a stepped structure surrounding the periphery of a hexagonal opening463B. The plurality of horizontal layers L1B to L19B may include a plurality of first to sixth horizontal layers forming first, second, third, fourth, fifth, and sixth stepped structures401B,403B,405B,407B,409B, and411B in first, second, third, fourth, fifth, and sixth regions.

Each of the first sub-stepped structure401B formed by a plurality of first horizontal layers L1B to L3B, the second sub-stepped structure403B formed by a plurality of second horizontal layers L4B to L6B, the third sub-stepped structure405B formed by a plurality of third horizontal layers L7B to L9B, the fourth sub-stepped structure407B formed by a plurality of fourth horizontal layers L10B to L12B, the fifth sub-stepped structure409B formed by a plurality of fifth horizontal layers L13B to L15B, and the sixth sub-stepped structure411B formed by a plurality of sixth horizontal layers L16B to L18B may become lower as becoming closer to the center of the hexagonal opening463B. The first to sixth sub-stepped structures401B to411B may be located at different levels. More specifically, the first to sixth sub-stepped structures401B to411B may be arranged to have a step difference clockwise or counterclockwise.

The plurality of horizontal layers LIB to L19B may further include a seventh horizontal layer L19B surrounding the periphery of the first to sixth sub-stepped structures401B to411B.

As described above, the gate stack structure in accordance with the embodiments of the present disclosure may include three or more regions arranged clockwise or counterclockwise at the periphery of an opening of a polygon. In accordance with embodiments of the present disclosure, sub-stepped structures may be respectively disposed in the three or more regions, and each of the sub-stepped structures may have a step difference changed toward the center of the opening. Also, the sub-stepped structures may be formed to make a step difference at a boundary between different regions. In accordance with the embodiments of the present disclosure, the area allocated to a dummy stepped structure in the regions surrounding the openings may be removed, and the sub-stepped structures may be used as contact regions of conductive gate contacts involved in an operation of the semiconductor memory device.

FIG.14is a block diagram illustrating a configuration of a memory system in accordance with an embodiment of the present disclosure.

Referring toFIG.14, a memory system1100includes a memory device1120and a memory controller1110.

The memory device1120may be a multi-chip package configured with a plurality of flash memory chips. The memory device1120may include a plurality of conductive layers stacked while surrounding the periphery of a polygonal opening, and a stepped structure formed along a sidewall of the polygonal opening. The stepped structure may include a plurality of steps which become lower as becoming closer to the center of the polygonal opening and become lowers clockwise or counterclockwise.

The memory controller1110controls the memory device1120. The memory controller1110may include Static Random Access Memory (SRAM)1111, a Central Processing Unit (CPU)1112, a host interface1113, an error correction block1114, and a memory interface1115. The SRAM1111is used as operation memory of the CPU1112, the CPU1112performs overall control operations for data exchange of the memory controller1110, and the host interface1113includes a data exchange protocol for a host connected with the memory system1100. The error correction block1114detects errors included in a data read from the memory device1120, and corrects the detected error. The memory interface1115interfaces with the memory device1120. The memory controller1110may further include Read Only Memory (ROM) for storing code data for interfacing with the host, and the like.

The memory system1100configured as described above may be a memory card or a Solid State Disk (SSD), in which the memory device1120is combined with the controller1110. For example, when the memory system1100is an SSD, the memory controller1100may communicated with the outside (e.g., the host) through one of various interface protocols, such as a Universal Serial Bus (USB) protocol, a Multi-Media Card (MMC) protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial-ATA (SATA) protocol, a Parallel-ATA (PATA) protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, and an Integrated Drive Electronics (IDE) protocol.

FIG.15is a block diagram illustrating a configuration of a computing system in accordance with an embodiment of the present disclosure.

Referring toFIG.15, a computing system1200may include a CPU1220, random access memory (RAM)1230, a user interface1240, a modem1250, and a memory system1210, which are electrically connected to a system bus1260. When the computing system1200is a mobile device, a battery for supplying an operation voltage to the computing system1200may be further included, and an application chip set, an image processor, mobile DRAM, and the like may be further included.

The memory system1210may be configured with a memory device1212and a memory controller1211. The memory device1212may have the same configuration as the memory device1120described above with reference toFIG.14. The memory controller1211may have the same configuration as the memory controller1110described above with reference toFIG.14.

In accordance with embodiments of the present disclosure, a sidewall of a gate stack structure surrounding the periphery of an opening of the gate stack structure has a step difference changed clockwise or counterclockwise. Accordingly, the area for a stepped structure may be efficiently used from a planar viewpoint, and the area allocated to the stepped structure may be reduced. Thus, the degree of integration of the semiconductor memory device may be improved.