Phase interpolation-based clock and data recovery for differential quadrature phase shift keying

In one embodiment, a method includes receiving N input streams; generating a recovered clock signal based on the input data bits in the N input streams, the recovered clock signal having a clock frequency and a recovered clock phase; generating a clock signal for each one of the N input streams based on the recovered clock signal having the clock frequency and a respective phase at a respective phase offset relative to the recovered clock phase; detecting a phase difference between each of the N input bit streams and the respective N clock signals; and adjusting the phases of the N clock signals to eliminate the respective phase differences, the adjusting comprising shifting the N respective clock phase offsets such that each of the N clock signals is locked to the input data bits in the respective one of the N input streams.

TECHNICAL FIELD

The present disclosure relates generally to clock and data recovery (CDR).

BACKGROUND

CDR circuits (or systems) are generally used to sample an incoming data signal, extract (or recover) the clock from the incoming data signal, and retime the sampled data to produce one or more recovered data bit streams. A phase-locked loop (PLL)-based CDR circuit is a conventional type of CDR circuit. A PLL circuit is an electronic control system that may be used, in part or in whole, to generate or maintain one signal that is locked onto the phase and frequency of another signal. By way of example, in a conventional PLL-based CDR, a phase detector compares the phase between input data bits from a serial input data stream and a clock signal generated by a voltage-controlled oscillator (VCO). In response to the phase difference between the input data and the clock, the phase detector generates phase or frequency correction signals. A charge pump drives a current to or from a loop filter according to the correction signals. The loop filter outputs a control voltage VCTRLfor the VCO based on the current driven by the charge pump. The loop acts as a feedback control system that tracks the phase and frequency of the input data stream with the phase and frequency of the clock that the loop generates.

One significant problem with conventional CDR systems comprising two CDR circuits that each receive a respective input data bit stream is that such CDR systems are suitable only for full-rate CDR within each individual CDR circuit without data demultiplexing; that is, when the frequencies of the recovered clock signals generated for each input data bit stream and the data rates (or frequencies) of the recovered data bit streams generated for each input data bit stream share the same frequency or rate as the respective input data bit streams. Otherwise, there exists an uncertainty in the relative clock and data phases from each CDR circuit and the system may operate erroneously. Unfortunately, many, or even most, practical CDR systems in, for example, high speed optical communication applications, use either half-rate or quarter-rate CDR architectures, or demultiplex each of the input data bit streams to two, four, or more individual streams to, for example, cope with high input data rates.

DESCRIPTION OF EXAMPLE EMBODIMENTS

Particular embodiments relate to an electronic circuit, device, system, or method for clock and data recovery (CDR) for a serial communication system application. More particularly, the present disclosure provides examples of a CDR architecture that receives two or more input data bit streams, generates a clock signal for each of the input data bit streams based on the input data bits in the input data bit streams, recovers the data bits in each of the input data bit streams, and outputs a recovered data bit stream for each input data bit stream with the recovered bits from the respective input data bit stream. In some embodiments, the CDR architecture then combines the recovered data bits from the recovered data bit streams and outputs one or more output data bit streams in which the recovered bits from the two or more input data bit streams are interleaved. By way of example, in one example embodiment, the CDR architecture receives two input data bit streams each of which is generated by demodulating or decoding a single symbol stream such as, for example, a Differential Quadrature Phase Shift Keying (DQPSK)-modulated symbol stream in which each symbol encodes two bits of data. In such example embodiments, the CDR architecture may recombine the recovered data bits from the input data bit streams to output one or more output data bit streams that reconstruct the values and ordering of the bits in the original DQPSK-modulated symbol stream from which the two input data bit streams were generated.

Generally, various described embodiments can be used for any N-input CDR application; however, particular embodiments relate to the use of a CDR architecture within a deserializer utilized in optical communication. By way of example, particular embodiments may be utilized in a DQPSK optical transponder. In particular embodiments described below with reference to a two-input CDR architecture, the two input data bit streams have the same data rate and are each generated by demodulating or decoding a DQPSK-modulated symbol stream in which each symbol of the DQPSK symbol stream encodes two data bits (e.g., binary data bits). However, alternative embodiments may be utilized in other specific applications and for non-optical communication (e.g., hard-wired communication using electrons), where appropriate. Particular embodiments may be utilized in high speed communication systems (e.g., data bit rates greater than 10 Gigabits per second (Gb/s)) and in even more particular embodiments, in communication systems having data rates at or exceeding 20 Gb/s or 40 Gb/s. Particular embodiments may be implemented with a complementary metal-oxide-semiconductor (CMOS) architecture. As used herein, one stream may refer to one wire, and vice versa, where appropriate, or alternately, one stream may refer to one bus (e.g., multiple wires or communication lines), and vice versa, where appropriate. Furthermore, as used herein, “or” may imply “and” as well as “or;” that is, “or” does not necessarily preclude “and,” unless explicitly stated or implicitly implied.

FIG. 1illustrates an example CDR architecture, system, device, or circuit100(“CDR100”). CDR100is configured to receive first input data bits from a first input data bit stream din1and second input data bits from a second input data bit stream din2. In particular embodiments, the first and the second input data bit streams din1and din2are generated by demodulating or decoding a single symbol stream, and each includes input data bits at an input data bit frequency (in this example, the input data bit frequency is half the symbol frequency of the stream from which the two input data bit streams were generated). In particular embodiments, the symbol stream is a DQPSK-modulated data stream. In particular embodiments, and as described in the present disclosure, the first input data bits in the first input data bit stream din1may be even-numbered bits from the DQPSK symbol stream while the second input data bits in the second input data bit stream din2may be odd-numbered bits from the DQPSK symbol stream (or vice versa); that is, for example, the first bit of each demodulated symbol from the DQPSK symbol stream may be output to the first input data bit stream din1while the second bit of each demodulated symbol from the DQPSK symbol stream may be output to the second input data bit stream din2. In particular embodiments, each of first and second input data bit streams din1and din2is transmitted in the form of a differential signal (e.g., a signal that is formed by the difference of a data signal and its complement).

DQPSK is a modulation technique in which two bits at a time are grouped and used to phase-modulate an output. By way of example, in an example implementation, two bits per symbol are encoded in the phases of light. The modulation is differential, which means that the input symbol (two bits) corresponds not to a particular phase of the output, but to the change of the phase relative to the phase of the previous symbol.FIG. 2illustrates an example DQPSK modulation scheme. In the example illustrated inFIG. 2, symbol 00 causes zero change in the output phase, symbol 01 causes a phase change of π/2, symbol 11 causes a phase change of π, and symbol 10 causes a phase change of 3π/2. In this way the demodulation may be made insensitive to a phase shift in the communication medium.

A DQPSK receiver demodulates the DQPSK symbol stream to obtain two bits per symbol, and thus two streams of binary data, din1and din2, which may then be amplified and sent to CDR100. The two input data streams din1and din2, examples of which are illustrated inFIG. 3for didactic purposes (in which each bit is represented by a letter), have the same data rate (input data bit frequency), but the exact phase relationship between the two input data streams din1and din2is unknown due to, for example, mismatches in the paths from the DQPSK demodulator to CDR100. A proper CDR circuit should not only recover the clock and individual data from the input data bit streams, but also correctly recombine the recovered bits from the two input data bit streams; that is, in particular embodiments, determine which bits from din1and din2correspond to the same corresponding symbols from the DQPSK symbol stream and output these bits in the proper order as they were received from the DQPSK symbol stream. By way of example, referring to the example data bits illustrated inFIG. 3, the recovered and recombined bits should be ordered as a, b, c, d, e, f, g, and so on.

In the embodiment illustrated inFIG. 1, CDR100includes a primary feedback loop that comprises phase detectors (PDs)102and104, charge pumps (CPs)106and108, loop filter110, voltage-controlled oscillator (VCO)112, and phase interpolators (PIs)114and116. In particular embodiments, CDR100additionally includes two local loops each with complementary outputs, one for each input to the respective one of the phase interpolators114or116, which set the control of the respective phase interpolators114and116, which generate clock signals Clk1and Clk2, respectively. In particular embodiments, after a number of iterations or short time period, the recovered data in recovered data bit streams dout1and dout2are synchronous to their local clock signals Clk1and Clk2, respectively, and should thus subsequently be synchronized to the global clock signal, which may be Clk1, Clk2, or Clk0, as described below. Of particular note, the embodiments illustrated and described with reference toFIG. 1do not restrict the rate of CDR100; that is, in general, CDR100may be a ½K-rate CDR (e.g., where K is 1, 2, 4 or some other desired number), where each of phase detectors102and104demultiplex the input data bit streams din1and din2, respectively, into K individual streams. In such embodiments, each of the K data bit streams generated by demultiplexing the respective input data bit stream din1or din2are at 1/K the data rate of the respective input data bit stream din1or din2, and the frequencies of each of the recovered clocks (Clk0, Clk1, and Clk2) are at 1/K the frequency or data rate of each of input data bit streams din1and din2. Furthermore, in such embodiments, the recovered data bit streams dout1and dout2may then comprise K individual streams each comprising selected ones of the recovered bits from the demultiplexed input data bit streams din1and din2, respectively, at 1/K the data rate of the respective input data bit stream din1or din2. In alternate notation, the recovered data bit stream dout1may be written as Dout1 [1, 3, 5, . . . 2K−1], where each number in the brackets corresponds to a corresponding one of the recovered K bits (per K-bit data cycle of din1and, thus, 2K-bit cycle of the original symbol stream from which din1was generated) from a corresponding individual one of the K recovered data bit streams that collectively comprise dout1. Similarly, in alternate notation, the recovered data bit stream dout2may be written as Dout2[2, 4, 6, . . . 2K], where each number in the brackets corresponds to a corresponding one of the recovered K bits (per K-bit data cycle of din2and, thus, 2K-bit cycle of the original symbol stream from which din2was generated) from a corresponding individual one of the K recovered data bit streams that collectively comprise dout2.

In one example embodiment, each of phase detectors102and104comprises a sampler or sampling circuit for sampling each of the input data bits received from the input data bit streams din1and din2, respectively, based on the generated clock signals Clk1and Clk2, respectively. Phase detectors102and104then output recovered data bit streams dout1and dout2, respectively, based on the sampled bits from input data bit streams din1and din2, respectively. In one embodiment, each of phase detectors102and104oversamples the respective input data bit stream din1or din2by a factor of n. In such embodiments, each of phase detectors102and104may comprise a selector or selecting circuit for selecting one of the oversampled bits sampled by the respective sampler for output to recovered output bit stream dout1or dout2, respectively (e.g., the sample that best corresponds to the center of the eye of the respective data bit). Additionally, although each of phase detectors102and104are illustrated as a single circuit block or element, each of phase detectors102and104may generally include one or more individual circuits or circuit elements, respectively. More generally, each of phase detectors102and104, as well as any other component of CDR100described herein, may comprise any suitable components or devices of hardware or logic or a combination of two or more such components or devices operable to perform or carry out the embodiments described herein.

In particular embodiments, phase detectors102and104detect (or determine) phase differences between din1or din2, respectively, and the clock signal Clk1or Clk2, respectively, asFIG. 1illustrates. In embodiments in which each of the input data bit streams din1and din2are demultiplexed to K individual streams, the clock signals Clk1and Clk2may each be multi-phase clock signals (e.g., K-phase clock signals each having 1/K the frequency or data rate of each of input data bit streams din1and din2but having the same frequency or data rate as each of the other K individual streams obtained by demultiplexing the respective one of the input data bit streams din1or din2) where each phase of each clock signal in a given clock cycle triggers a corresponding sampler to sample a corresponding bit from a corresponding one of the K individual data bit streams obtained by demultiplexing the respective input data bit stream din1or din2. Based on the detected phase difference (if any) between din1and Clk1, phase detector102may generate one or more phase correction signals that are then output to charge pump106. Similarly, based on the detected phase difference (if any) between din2and Clk2, phase detector104may generate one or more phase correction signals that are then output to charge pump108. In particular embodiments, based on the phase correction signals received from phase detectors102and104, charge pumps106and108effect the raising, lowering, or maintaining of a responding current ICP, which is filtered by loop filter110. Loop filter110generally affects the dynamic behavior of the feedback loop and filters out any high frequency noise associated with the current ICPoutput from the charge pumps106and108. Loop filter110outputs a control voltage VCTRLbased on ICPthat controls the frequency and phase of the clock signal Clk0, and consequently the clock signals Clk1and Clk2, output from VCO112(thereby forming the primary feedback loop mentioned above). In such a manner, CDR100is configured to receive input data bit streams din1and din2, and over a number of iterations, generate clock signals Clk1and Clk2that match the frequencies and phases of input data bit streams din1and din2(or demultiplexed streams generated therefrom) as described in further detail below.

Based on the control voltage VCTRLoutput from loop filter110, VCO112generates the clock signal Clk0, which may be a multiphase (e.g., K-phase) clock signal in some embodiments. In particular embodiments, the phase of clock signal Clk0is effectively locked to the middle of the phase offset between the phase of din1and the phase of din2. In particular embodiments, loop filter110is, or comprises, a low-pass filter (or low pass filter circuit). In particular embodiments, the clock signal Clk0is output to each of phase interpolators114and116.

In some example embodiments, each of phase interpolators114and116is an analog phase interpolator, in which case each of the phase interpolators114and116is controlled by an analog voltage VPIor −VPI(i.e., −VPIis the complement of VPI), respectively, output from low-pass filter (LPF)118. In other example embodiments, each of phase interpolators114and116is a digital phase interpolator, in which case each of phase interpolators114and116is controlled by a digital code PICODEor −PICODE, respectively, output from LPF118. Whichever the case (analog or digital), the controls (VPIand −VPIor PICODEand −PICODE) cause the respective phase interpolators114or116to skew the phase of Clk0by the same magnitude, but in opposite directions, to generate the respective clock signals Clk1and Clk2. That is, for example, if the value of VPIis such that it causes phase interpolator114to skew the phase of Clk0(or phases if Clk0and Clk1are multi-phase clock signals) forward to generate Clk1(e.g., to advance the phase(s) of Clk1relative to din1), then the value of −VPIconsequently causes phase interpolator116to skew the phase of Clk0(or phases if Clk0and Clk2are multi-phase clock signals) backward to generate Clk2(e.g., to delay the phase(s) of Clk2relative to din2) by the same phase magnitude, and vice versa.

In particular embodiments, to avoid interdependence between the convergence of each of the local loops, one of the inputs to CDR100is enabled only after the primary loop has converged. By way of example, this may be achieved by enabling phase detector104(or alternately phase detector102) only after the primary loop converges; that is, when the phase of the clock signal Clk1matches that of the input data bit stream din1(or, in embodiments in which din1is demultiplexed into K individual streams, the phases of the K-phase clock signal Clk1match the phases of the data bits in the K individual streams obtained from demultiplexing din1).

In particular embodiments, LPF118receives as input the UP1, DN1, UP2, and DN2output from the phase detectors102and104and generates the complementary analog voltages VPIand −VPIor complementary digital codes PICODEand −PICODEdepending on whether the phases interpolators114and116are analog or digital, respectively. More particularly, in one example embodiment, LPF118averages the two differences (UP1−DN1and UP2−DN2); that is averages the expression (1) below.
UP1+UP2−DN1−DN2(1)

In this way, in such embodiments, by using the symmetry of the phase interpolators114and116with respect to their respective control inputs (i.e., either analog voltages VPIand −VPIor digital codes PICODEand −PICODE), the phase of the clock signal Clk0generated by VCO112is guaranteed to be the average of the phases of the clock signals Clk1and Clk2. Furthermore, the phase offset between Clk1and Clk2is guaranteed, upon loop convergence, to equal the phase offset between din1and din2, and thus compensate for the phase offset between din1and din2.

In particular embodiments, phase interpolators114and116are each configured to have a phase interpolation range less than ±UI/4 (where UI is the unit interval of the input data bits in the input data bit streams din1or din2). In such embodiments, the total relative phase offset between Clk1and Clk2is less than ±UI/2. Configuring the phase interpolators114and116to have a range of less than ±UI/4 is done in particular embodiments to avoid an incorrect ordering of bits in the recovered output data bit streams dout1and dout2, which otherwise may occur in some implementations if in the process of CDR lock (i.e., loop convergence and locking of the phases of the clock signals Clk1and Clk2to the input bit streams din1and din2, respectively), the phase interpolators114and116lock to adjacent input bits as in cases2and3illustrated inFIGS. 4B and 4C. If such different cases (i.e., cases2and3) were allowed to exist, a relatively complicated control circuit would be needed in such embodiments to detect the occurrence of cases2or3, and reset CDR100to guarantee a proper locking as in cases1, whichFIG. 4Aillustrates. Moreover, by construction, the ordering of the recovered bits in each of the recovered bit streams is known relative to the other recovered bit streams, and hence, recombining the recovered bits is trivial.

As described earlier, in particular embodiments, CDR100not only recovers the clock and individual data from input data bit streams din1and din2, but also recombines the recovered bits from the two input data bit streams din1and din2; that is, determines which bits from din1and din2correspond to the same corresponding symbols from the DQPSK symbol stream from which the bits in input data bit streams din1and din2were obtained and outputs these bits in the proper order as they were in the DQPSK symbol stream (e.g., a, b, c, d, e, f, g, and so on). Thus, in particular embodiments, CDR100further includes a data combiner that interleaves, or combines the bits from recovered data bit streams dout1and dout2and generates one or more output streams in which the values and ordering of the bits in the one or more output streams correspond to the values and ordering of the bits in the DQPSK symbol stream. By way of example, the data combiner may combine recovered data bit streams dout1and dout2and output the combined bits onto an output bus having any number of wires (e.g., 1, 2, 4, 8, etc.) each carrying an output stream that comprises respective bits from the combined recovered data bit streams dout1and dout2. In one example embodiment, the data combiner requires no actual hardware, but bundles the recovered data dout1[K:1] and dout2[K:1] to a single stream or bus dout[2K:1] such that dout[2i−1]=dout1[i], and dout[2i]=dout2[i], for i=1 . . . K.

FIG. 5illustrates an example CDR500that is a variation of the CDR architecture ofFIG. 1generalized to N input data streams din1, din2, . . . dinN. CDR500comprises N phase detectors5021through502N, each of which is configured to receive a corresponding one of the N input data bit streams and to recover the respective data bits in the respective one of the N input data bit streams to generate a respective one of the recovered data bit streams dout1, dout2, . . . doutN. As described above, each of phase detectors5021through502Nmay demultiplex the respective one of the input data bit streams it receives into K individual streams. Thus, in alternate notation, for example, dout1may be written as Dout1[1, N+1, 2N+1, . . . (K−1)N+1], while dout2may be written as Dout2[2, N+2, 2N+2, . . . (K−1)N+2], and so on with doutNwritten as DoutN[N, 2N, 3N, . . . KN]. CDR500further comprises charge pumps5041through504N, loop filter506, VCO508, phase interpolators5101through510N, and low-pass filter512, each of which may be configured similarly as described above but modified as illustrated inFIG. 5and as described below.

In particular embodiments, the controls VPI1through VPIN(for analog phase interpolators) or PICODE1through PICODEN(for digital phase interpolators) for each of the phase interpolators5101through510N, respectively, are obtained by LPF512by filtering the difference of the corresponding UP and DN phase correction signals generated by the respective one of the phase detectors5021through502N(e.g., UP1-DN1for phase interpolator5101), respectively, attenuated by the average of the differences of the UP and DN phase correction signals received by LPF512from all of the phase detectors5021through502N. By way of example,FIG. 6illustrates an example N-input/N-output low pass filtering architecture or circuit suitable for use as LPF512for performing the filtering function just described. In the embodiment illustrated inFIG. 6, LPF512includes adders6141through614Nthat receive the respective phase correction signal differences from the respective phase detectors5021through502N. LPF512further includes adder616that receives all of the aforementioned phase correction signal differences and that outputs the sum to divider618, which divides the sum by N. Adders6141through614Neach then subtract the divided sum (the average) from the respective phase correction signal difference received from the respective one of the phase detectors. Each of the adders6141through614Nthen outputs the result to a corresponding one of the low-pass filters6201through620N, which generate and output the respective analog or digital controls to the respective phase interpolators5101through510N. In this way, the common mode of the inputs to all individual channels is guaranteed to be zero. Therefore, if the individual filters6201through620Nhave no poles at DC or the proper initialization is applied in the case that one or more of these filters has poles at DC, the phase interpolator analog or digital controls will maintain the same property. In this manner, the phase of the clock signal Clk0generated by VCO508is again guaranteed to be the average of all the clock signals Clk1through ClkNoutput from the respective phase interpolators5101through510N, respectively.

The described embodiments offer one or more advantages over conventional CDR circuits. In particular, the described embodiments do not require a full-rate architecture. Furthermore, the described embodiments may utilize a single VCO, which may reduce the area and power consumption required by the CDR architecture as well as eliminate the potentially damaging coupling that may otherwise occur between VCOs in CDR architectures that utilize multiple VCOs.