Circuit for generating refresh period signal and semiconductor integrated circuit using the same

Circuits for generating refresh period signals and semiconductor integrated circuits using the same are presented. The refresh period signal generation circuit can include an oscillator, a pulse generation unit, and a signal controller. The oscillator is configured to generate an oscillation signal in response to a refresh duration correction signal. The pulse generation unit is configured to generate a refresh period signal in response to the oscillation signal. The signal controller configured to generate the refresh duration correction signal, which corrects an active time of a refresh duration signal, in response to the oscillation signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2009-0044814 filed on May 22, 2009, the entire contents of which are incorporated herein by reference.

BACKGROUND

This disclosure relates to semiconductor circuits, and more particularly, to a circuit for generating a refresh period signal (i.e., refresh period signal generation circuit) and a semiconductor integrated circuit using the same.

Semiconductor integrated circuits, e.g., volatile memories such as dynamic random access memories (DRAMs) are often times essentially equipped with refresh operations for retaining data stored in their memory cells.

These DRAMs are generally designed to periodically conduct the refresh operations even when in standby states for which there is no event of reading or writing operations.

In operation of DRAMs, refresh period signals are normally used for defining periods of the refresh operations.

FIG. 1illustrates a general organization of a refresh period signal generation circuit.

As shown inFIG. 1, the general refresh period signal generation circuit1includes an oscillator10, a frequency divider20, and a pulse generation unit30.

The oscillator10is shown generating an oscillation signal OSC in response to a refresh duration signal SREF that functions to determine a refresh period.

The frequency divider20is shown generating a plurality of frequency signals operating in 1 μs, 2 μs, 4 μs, 8 μs and 16 μs by dividing the oscillation signal OSC.

The pulse generation unit30is shown outputting a refresh period signal SREFP from one of the frequency signals (1 μs, 2 μs, 4 μs, 8 μs and 16 μs) which is selected in accordance with a fuse option signal FSEL.

FIG. 2shows a waveform of an output signal generated from the period signal generation circuit ofFIG. 1.

The refresh duration signal SREF is inactivated when there is an input of a refresh escape command SREX. The refresh escape command SREX is generated regardless of an operating status of the refresh period signal generation circuit. In other words, without relevance to output signals of the oscillator10, the frequency divider20and the pulse generation unit30, the refresh escape signal SREX is independently generated to inactivate the refresh duration signal SREF.

It is first assumed that the pulse generation unit30makes the refresh period signal SREFP from one of the plural frequency signals (1 μs, 2 μs, 4 μs, 8 μs and 16 μs), e.g., the 8 μs frequency signal.

As shown inFIG. 2, when the refresh duration signal SREF is inactivated by the refresh escape command SREX at the time when the oscillation signal OSC is generated, i.e., when the refresh duration signal SREF is inactivated by the refresh escape command SREX while the 8 μs frequency signal is generated from the oscillation signal OSC, the 8 μs frequency signal may be abnormally generated without a sufficient timing margin.

Owing to such an insufficient timing margin of the 8 μs frequency signal, the refresh period signal SREFP responding thereto is also generated in a form of glitch without a sufficient timing margin.

As the refresh operation to memory cells is carried out by selecting a row address corresponding to the memory cells in accordance with a pulse of the refresh period signal SREFP, the abnormal glitch of the refresh period signal SREFP causes the row address not to be selected.

Therefore, cell data are prone to being damaged or compromised because the memory cells corresponding to the row address that has not been yet selected are abnormally conditioned in an incomplete state of the refresh operation.

Such a timing distortion between the refresh escape command SREX and the oscillation signal OSC occurs irregularly, resulting in the glitch of the refresh period signal SREFP. For that reason, it is practically difficult to predict when the refresh period signal SREFP is generated with such an insufficient and abnormal pulse in the glitch. And it is difficult to make the glitch effect reemerged even by a test process because the refresh escape command SREX is independently applied thereto regardless of an operating status of the refresh period signal generation circuit. Simply adjusting a delay time of a signal involved therein does not bring about a adequate solution against the trouble of timing distortion between the refresh escape command SREX and the oscillation signal OSC. As a result, there would be an inadvertent defect in the memory apparatus such as DRAM.

SUMMARY OF THE INVENTION

There is provided a refresh period signal generation circuit enabling a refresh period signal stably generated, regardless of a refresh escape command, in a semiconductor integrated circuit.

In one embodiment, a refresh period signal generation circuit may include: an oscillator, a pulse generator, and a signal controller. The oscillator is configured to generate an oscillation signal in accordance with a refresh duration correction signal. The pulse generator is configured to generate a refresh period signal in accordance with the oscillation signal. The signal controller is configured to generate the refresh duration correction signal that corrects an active time of a refresh duration signal by using the oscillation signal.

In another embodiment, a semiconductor integrated circuit may include: a signal controller, a period signal generator, a refresh address counter, and a memory cell block. The signal controller is configured to generate a refresh duration correction signal that corrects an active time of a refresh duration signal by using an oscillation signal. The period signal generator is configured to generate a refresh period signal by using the oscillation signal generated in accordance with the refresh duration correction signal. The refresh address counter is configured to count and to output a refresh address in accordance with the refresh period signal. The memory cell block is configured to refresh memory cells corresponding to the refresh address.

A further understanding of the nature and advantages of the present invention herein may be realized by reference to the remaining portions of the specification and the attached drawings.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

As aforementioned with relevance to the conventional case, since a timing distortion between a refresh escape command and an oscillation signal occurs irregularly, it is practically impossible to predict a time of the erroneous pulse generation (e.g., glitch) of the refresh period signal and to make the erroneous generation reemerged. Further, just adjusting a delay time of a signal could not be completely helpful in solving such a timing difficulty.

An exemplary embodiment of the present invention uses a scheme of correcting an active time of a refresh period signal by finding a generation state of an oscillation signal.

Hereinafter, it will be described about an exemplary embodiment of the present invention in conjunction with the accompanying drawings.

FIG. 3illustrates a configuration of a refresh period signal generation circuit in accordance with an embodiment of the present invention.

Referring toFIG. 3, the refresh period signal generation circuit100according to this embodiment of the present invention is comprised of an oscillator10, a frequency divider20, a pulse generation unit30, and a signal controller200.

The oscillator10, the frequency divider20and the pulse generation unit30can be similarly configured as shown inFIG. 1, and therefore these will not be further described.

The signal controller200is configured to generate a refresh duration correction signal SREF_C for correcting an active time of the refresh duration signal SREF by means of the oscillation signal OSC. The signal controller200includes a refresh beginning detector210, a refresh end detector220, and a latch230.

The refresh beginning detector210is configured to detect a start point of an active time of the refresh duration correction signal SREF_C in response to activation of the refresh duration signal SREF. The refresh beginning detector210includes a pulse generator211, and a first transistor M1. The pulse generator211of the refresh beginning detector210outputs a negative pulse from the refresh duration signal SREF. The first transistor M1of the refresh beginning detector210applies a power source voltage VDD to a node A in response to the negative pulse.

The refresh end detector220is configured to detect an end point of an active time of the refresh duration correction signal SREF_C in accordance with a combination of the refresh duration signal SREF and the oscillation signal OSC supplied from the oscillator10. The refresh end detector220operates to initialize the refresh duration correction signal SREF_C in accordance with a power-up signal PWRUP. The refresh end detector220includes a plurality of logical devices, i.e., a NOR gate NR1, an inverter IV1and a NAND gate ND1, executing an OR operation on an input of the refresh duration signal SREF and of the oscillation signal OSC, and executing a not-AND (NAND) output operation using the result of the OR operation and using the power-up signal PWRUP, and outputting the NAND result at a gate of a second transistor M2connecting the node A and to a ground voltage VSS.

The latch230is configured to hold an active level state of the refresh duration correction signal SREF_C in response to an output of the refresh beginning detector210and to inactivate the refresh duration correction signal SREF_C in response to an output of the refresh end detector220.

FIG. 4shows waveforms about an operation with an output signal from the refresh period signal generation circuit ofFIG. 3.

Referring toFIG. 4, responding to the power-up signal PWRUP, the NAND gate ND1of the refresh end detector220outputs a high level state signal and the second transistor M2is turned on to discharge the node A to a low level state. By the low level state of the node A, the latch230initializes the refresh duration correction signal SREF_C. That is, the refresh duration correction signal SREF_C is set on a low level state as an initial condition.

The power-up signal PWRUP goes to a high level state from a low level state when the power source voltage VDD of the semiconductor memory is stabilized on a target level state.

Afterward, when the refresh duration signal SREF is activated to a high level state from a low level state, then the pulse generator211generates a negative pulse to make the first transistor M1transition an input of the latch230to a high level state.

Then, the latch230holds the high level state input thereat. From the latch230, the high level state signal is provided to the oscillator10as the refresh duration correction signal SREF_C.

The oscillator10generates the oscillation signal OSC in response to the refresh duration correction signal SREF_C of high level state.

The frequency divider20generates a plurality of frequency signals, which are operating in the cycle periods of 1 μs, 2 μs, 4 μs, 8 μs and 16 μs, by dividing the oscillation signal OSC.

The pulse generation unit30operates to generate the refresh period signal SREFP from one of the divided frequency signals (1 μs, 2 μs, 4 μs, 8 μs and 16 μs), e.g., the 8 μs frequency signal, which is selected by a fuse option signal FSEL.

During this, as the power-up signal PWRUP is conditioned in a high level state, the NAND gate ND1outputs a low level state signal to maintain the node A on a high level state while the refresh duration signal SREF is being on a high level state.

Accordingly, the refresh duration correction signal SREF_C is also held on a high level state by the latch230.

When the refresh duration signal SREF goes to a low level state by the refresh escape command SREX and the oscillation signal OSC is then set to a low level state, the NAND gate ND1outputs a high level state signal to set the node A transition into a low level state. Then, the refresh duration correction signal SREF_C is set at a low level state by the latch230.

Since the refresh duration correction signal SREF_C is now set at a low level state, the oscillator10, then the frequency divider20and the pulse generation unit30stop operating and the pulse of the refresh period signal SREFP is not further generated.

In the meantime, if the oscillation signal OSC is still conditioned in a high level state, although the refresh duration signal SREF has already transitioned to a low level state by the refresh escape command SREX, i.e., if the oscillation signal OSC remains being generated, then the NAND gate ND1outputs a low level state signal to keep the node A at a high level state. Thereby, the refresh duration correction signal SREF_C from the latch230is also maintained at a high level state as shown inFIG. 4.

Since the refresh duration signal SREF_C is in a high level state even though the refresh duration signal SREF has already transitioned into a low level state, then the oscillator10generates the oscillation signal OSC with a sufficient timing margin. Thus, the divided frequency signals of 1 μs, 2 μs, 4 μs, 8 μs and 16 μs are accordingly generated with sufficient timing margins.

Then, the pulse generation unit30generates the refresh period signal SREFP with a sufficient timing margin from one of the divided frequency signals of 1 μs, 2 μs, 4 μs, 8 μs and 16 μs, e.g., the 8 μs frequency signal, which have sufficient timing margins.

The refresh period signal generation circuit according to the exemplary embodiment of the present invention is featured by finding a generation state of the oscillation signal OSC and correcting an active time of the refresh period signal SREFP. It is also permissible to utilize one of the divided frequency signals of 1 μs, 2 μs, 4 μs, 8 μs and 16 μs instead of the oscillation signal OSC. In a preferred embodiment, the oscillation signal OSC can be advantageously used to correctly optimize the active time of the refresh period signal SREFP because of its earlier generation than others.

FIG. 5illustrates a schematic organization of a semiconductor integrated circuit in accordance with an embodiment of the present invention.

Referring toFIG. 5, the semiconductor integrated circuit300is comprised of a signal controller400, a period signal generator500, a refresh address counter600and a memory cell block700.

The signal controller400is configured to generate the refresh duration correction signal SREF_C for correcting an active time of the refresh duration signal SREF by means of the oscillation signal OSC.

The period signal generator500is configured to generate the refresh period signal SREFP from the refresh duration correction signal SREF_C.

The refresh address counter600is configured to count and output a row address RA in accordance with the refresh period signal SREFP.

In the memory cell block700, a word line corresponding to the row address RA is activated to conduct the refresh operation to memory cells coupled to the word line.

FIG. 6exemplarily illustrates configurations of the signal controller400and the period signal generator500shown inFIG. 5.

The signal controller400may be implemented in substantially the same manner as the signal controller200shown inFIG. 3, so it will not be further described.

The period signal generator500may be comprised of the oscillator10, the frequency divider20and the pulse generation unit30. The oscillator10, the frequency divider20and the pulse generation unit30may be implemented in substantially the same manner as those ofFIG. 3, so they will not be further described.

An operation of the semiconductor integrated circuit ofFIG. 5will be now described hereinafter.

Responding to activation of the power-up signal PWRUP, the NAND gate ND1of the refresh end detector220outputs a high level state signal and thereby the second transistor M2is turned on to set the node A at a low level state. With the low level state signal at the node A, the latch230initializes the refresh duration correction signal SREF_C. That is, the refresh duration correction signal SREF_C is maintained on a low level state.

The power-up signal PWRUP goes to a high level state from a low level state when the power source voltage VDD of the semiconductor memory is stabilized on a target level state.

Afterward, if the refresh duration signal SREF is activated at a high level state from a low level state, the pulse generator211generates a negative pulse to make the first transistor M1transition an input of the latch230to a high level state.

Then, the latch230holds the high level state input thereat. From the latch230, the high level state signal is provided to the oscillator10as the refresh duration correction signal SREF_C.

The oscillator10generates the oscillation signal OSC in response to the refresh duration correction signal SREF_C at a high level state.

The frequency divider20generates a plurality of frequency signals, which are operating in the cycle periods of 1 μs, 2 μs, 4 μs, 8 μs and 16 μs, by dividing the oscillation signal OSC.

The pulse generation unit30operates to generate the refresh period signal SREFP from one of the divided frequency signals (1 μs, 2 μs, 4 μs, 8 μs and 16 μs), e.g., the 8 μs frequency signal, which is selected by a fuse option signal FSEL.

During this, as the power-up signal PWRUP is conditioned at a high level state, the NAND gate ND1outputs a low level state signal to maintain the node A at a high level state while the refresh duration signal SREF is at a high level state. Accordingly, the refresh duration correction signal SREF_C is also held at a high level state by the latch230.

When the refresh duration signal SREF goes to a low level state by the refresh escape command SREX and the oscillation signal OSC is then set to a low level state, the NAND gate ND1outputs a high level state signal to set the node A transition into a low level state. Then, the refresh duration correction signal SREF_C goes to a low level state by the latch230.

Since the refresh duration correction signal SREF_C is now set at a low level state, then the oscillator10, the frequency divider20and the pulse generation unit30stop operating and the pulse of the refresh period signal SREFP is not further generated.

In the meantime, if the oscillation signal OSC is still conditioned in a high level state, although the refresh duration signal SREF has already transitioned to a low level state by the refresh escape command SREX, i.e., if the oscillation signal OSC remains being generated, then the NAND gate ND1outputs a low level state signal to keep the node A at a high level state. Thereby, the refresh duration correction signal SREF_C from the latch230is also maintained at a high level state as shown inFIG. 4.

As the refresh duration correction signal SREF_C is in a high level state even though the refresh duration signal SREF has already transitioned into a low level state, then the oscillator10generates the oscillation signal OSC with a sufficient timing margin. Thus, the divided frequency signals of 1 μs, 2 μs, 4 μs, 8 μs and 16 μs are accordingly generated with sufficient timing margins.

Then, the pulse generation unit30generates the refresh period signal SREFP with a sufficient timing margin from one of the divided frequency signals of 1 μs, 2 μs, 4 μs, 8 μs and 16 μs, e.g., the 8 μs frequency signal, which have sufficient timing margins.

The refresh address counter600operates to count and output a row address RA in accordance with the refresh period signal SREFP.

In the memory cell block700, a word line corresponding to the row address RA is activated to refresh memory cells coupled thereto.