Method of forming electronic dies wherein each die has a layer of solid diamond

A process is described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. A thin diamond layer is formed on a sacrificial wafer, and an integrated circuit is then formed on the thin diamond layer. The sacrificial wafer is then removed to expose the thin diamond layer. The resulting combination wafer is subsequently diced into individual dies. Each die has an exposed diamond layer forming the majority of the die and serving to conduct heat from the integrated circuit to a backside of the die, from where the heat can convect or be conducted away from the die.

BACKGROUND OF THE INVENTION

1). Field of the Invention

This invention relates to a method of manufacturing a combination wafer, dies from the wafer, and an electronic assembly including such a die, wherein the die has a layer of diamond for purposes of conducting heat.

2). Discussion of Related Art

Integrated circuits are usually formed on silicon wafers which are subsequently sawed into individual dies. Each die then has a portion of the silicon wafer with a respective integrated circuit formed thereon. Electronic signals can be provided to and from the integrated circuit. Operation of the integrated circuit causes heating thereof and an increase of temperature of the integrated circuit may cause its destruction. The heat usually conducts from the integrated circuit through the portion of the silicon wafer through a backside of the die. Silicon has traditionally been preferred because, in the case of monocrystalline silicon, it is possible to manufacture transistors and other components of integrated circuits therein and thereon. The silicon is typically between 700 and 800 microns thick, and has a relatively low thermal conductivity.

DETAILED DESCRIPTION OF THE INVENTION

First, second, and third processes are described respectively with respect toFIGS. 1a-g,FIGS. 2a-h, andFIGS. 3a-jwhereby, in each case, a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. The die has a diamond layer which primarily serves to spread heat from hot spots of an integrated circuit in the die.

In the first process, a relatively thick layer is formed which spreads more heat. The first process however utilizes a relatively cumbersome grinding operation. Because the diamond layer is relatively thick, a specialized laser cutting operation is utilized for cutting through the diamond layer.

In the second process, the grinding operation of the first process is eliminated and a shearing operation is utilized instead. A thick diamond layer is also formed in the second process, with associated advantages and disadvantages.

In the third process a shearing operation is also used to eliminate a grinding operation, but a thin diamond layer is formed which is easier to cut with a conventional saw. The thin diamond layer is also covered by a sacrificial polysilicon wafer so that a combined wafer is formed having silicon upper and lower surfaces. Such a combined wafer may be more “transparently” used in conventional machinery for processing conventional silicon wafers. The sacrificial polysilicon wafer also provides the structural support lacking in the thin diamond layer.

The fourth process is similar to the third process, except that the sacrificial polysilicon wafer is removed at wafer level, i.e., before the wafer is singulated into individual dies, so that the resulting dies each have an exposed diamond layer. Such dies are ideal for constructing three-dimensional packages wherein a number of the dies are stacked on top of one another. A thermally conductive heat slug can also be located directly against the diamond to minimize thermal resistance.

Utilizing a Grinding Operation in the Production of a Thick Diamond Layer

FIG. 1aof the accompanying drawings illustrates a monocrystalline (single crystal) silicon wafer10on which a thick diamond layer12is deposited. Monocrystalline silicon wafers are manufactured according to a known process. A long thin vertical SEED of monocrystalline silicon (a semiconductor material) is contacted with molten silicon in a crucible. The seed is then drawn vertically upwardly out of the bath. Monocrystalline silicon grows on the seed while it is drawn out of the bath so that a monocrystalline silicon ingot is formed having a diameter much larger than a diameter of the core. Presently, such an ingot has a diameter of approximately 300 mm and a height which is a multiple of the diameter. The ingot is then sawed into many wafers. Presently, a wafer sawed from an ingot has a thickness of approximately 750 microns. The monocrystalline silicon wafer10thus has a diameter of approximately 300 mm and a thickness of approximately 750 microns.

The thick diamond layer12is deposited utilizing plasma-enhanced chemical vapor diamond deposition (PECVDD) technology. The monocrystalline silicon wafer10is located in the PECVDD chamber and heated to a relatively high temperature of for example approximately 1000° C. Gases are then introduced into the chamber which react with one another to form diamond. The diamond then deposits out of the gases onto an entire upper surface of the monocrystalline silicon wafer10. The diamond that deposits on the monocrystalline silicon wafer10is solid multicrystalline diamond having a thermal conductivity of approximately 1000 W/mK and is attached to an upper surface of the monocrystalline silicon wafer10. The process is continued until the thick diamond layer12has a thickness of between 300 microns and 500 microns. The resulting thick diamond layer12thus has a diameter of 300 mm. The combination wafer ofFIG. 1ais then removed from the PECVDD chamber and allowed to cool. Further aspects of deposition of multicrystalline diamond are known in the art and are not further elaborated on herein.

As shown inFIG. 1b, the combination wafer ofFIG. 1ais then flipped so that the monocrystalline silicon wafer10is at the top. The thick diamond layer12is then located on a surface of a grinding machine. A grinding head of the grinding machine then grinds the monocrystalline silicon wafer10down.

FIG. 1cillustrates the combination wafer after the monocrystalline silicon wafer10is ground down. The monocrystalline silicon wafer10typically has a thickness of between 10 and 25 microns. The combination wafer shown inFIG. 1cis then removed from the grinding machine. Because the thick diamond layer12has a thickness of between 300 and 500 microns, the combination wafer does not break when removed from the grinding machine and subsequently handled. The thick diamond layer12thus provides the structural support for the relatively thin monocrystalline silicon wafer10. The upper surface of the monocrystalline silicon wafer10is subsequently etched and polished to obtain a desired finish. Stresses due to the grinding operation are also removed.

FIG. 1dillustrates subsequent fabrication that is carried out on the monocrystalline silicon wafer10. First, an epitaxial silicon layer14is grown on the monocrystalline silicon wafer10. The epitaxial silicon layer14follows the crystal structure of the monocrystalline silicon wafer10and is thus also monocrystalline. A primary difference between the epitaxial silicon layer14and the monocrystalline silicon wafer10is that the expitaxial silicon layer14includes dopants. As such, the epitaxial silicon layer14is either n-doped or p-doped.

Next, integrated circuits16A and16B are formed. An integrated circuit16A or16B includes a plurality of semiconductor electronic components such as transistors, capacitors, diodes, etc., and upper level metalization which connect the electronic components. A transistor has source and drain regions that are implanted into the epitaxial silicon layer14. These source and drain regions have opposite doping than the bulk of the epitaxial silicon layer14. The source and drain regions are implanted to a required depth into the epitaxial silicon layer14but usually not all the way through the epitaxial silicon layer14so that some of the unimplanted epitaxial silicon remains below the respective source or drain region. The metalization includes metal lines which are all located above the epitaxial silicon layer14. Contact pads are then formed on the integrated circuits16A and16B. The integrated circuits16A and16B are identical to one another and are separated from one another by a small scribe street18. Bumps20are then formed on the contact pads on the integrated circuits16A and16B. Although not shown, the bumps20are in an array and rows and columns on a respective integrated circuit16A and16B.

FIG. 1eillustrates the combination wafer ofFIG. 1dfrom above. The combination wafer has an outer edge22having a diameter of approximately 300 mm. Many of the integrated circuits16are formed in rows and columns within the edge22. Each integrated circuit16has a rectangular outline. A respective scribe street is located between a respective row or column.

The combination wafer ofFIG. 1eis then laser cut through the scribe streets18into a plurality of dies. Each die thereby includes only one of the integrated circuits16. Cutting of a wafer is also referred to as “singulation” or “dicing.” The thick diamond layer12is extremely hard, and because of its thickness it may be difficult to cut the thick diamond layer12utilizing a conventional sawing operation, hence the reason for the more sophisticated laser cut.

FIG. 1fillustrates two dies24A and24B. Each die24A and24B includes a respective portion of the thick diamond layer12, the monocrystalline silicon wafer10, and the epitaxial silicon layer14. The die24A includes the integrated circuit16A and the die24B includes the integrated circuit16B. Each die24A and24B includes a respective set of the bumps20.

FIG. 1gillustrates and electronic assembly including a package substrate30and the die24A. The die24A is flipped relative to its position inFIG. 1fso that the bumps20are at the bottom and the thick diamond layer12is at the top. Each bump20is located on a respective contact pad (to shown) on the package substrate. The electronic assembly28is subsequently located in a furnace which melts the bumps20, and is then cooled so that the bumps20are attached to the contact pads on the package substrate30.

In use, electronic signals can be provided through metal lines and vias in the package substrate32and from the bumps20. The electronic signals transmit through the bumps20to and from the integrated circuit16A. Operation of the integrated circuit16A causes heating thereof. Heating of the integrated circuit16A is not uniform from one point thereof to another. Hot spots are thus created at various locations across the integrated circuit16A.

The heat conducts from the integrated circuit16A through the epitaxial silicon layer14and the monocrystalline silicon wafer10to the thick diamond layer12. Heat conducts easily to the thick diamond layer12because the monocrystalline silicon wafer10is relatively thin. Because of the relatively high thermal conductivity of the thick diamond layer12, the heat from the hot spots conduct horizontally to cooler areas of the thick diamond layer12. The temperatures at the hot spots thus can be reduced. More heat can conduct horizontally through the thick diamond layer12than compared to a thin diamond layer.

Utilizing a Shearing Operation in the Production of a Thick Diamond Layer

FIG. 2aillustrates a sacrificial polysilicon wafer50on which a thick diamond layer52is deposited, followed by a polysilicon layer54. Processes for manufacturing polysilicon wafers are known. A polysilicon ingot is typically manufactured in a casting operation and wafers are then sawed from the ingot. The thick diamond layer52is deposited according to the same high-temperature technique discussed with reference toFIG. 1aand also has a thickness of between 300 and 500 microns. The polysilicon layer54is deposited utilizing known techniques and has a thickness of between 10 and 15 microns.

As shown inFIG. 2b, the combination wafer is then flipped so that the polysilicon layer54is at the bottom.

FIG. 2cillustrates a monocrystalline wafer56of the kind described with reference toFIG. 1a. The monocrystalline wafer56also has a diameter of approximately 300 mm and a thickness of approximately 750 microns. Hydrogen ions58are implanted into an upper surface of the monocrystalline wafer56.

FIG. 2dillustrates the monocrystalline silicon wafer56ofFIG. 2cafter implantation of the ions58. The ions58create a boundary60at a location about 10 to 25 microns below an upper surface of the monocrystalline silicon wafer56ofFIG. 2c. For further discussion, the portion below the boundary60is referred to as the “monocrystalline silicon wafer56A” and the region above the boundary is referred to as the “final monocrystalline silicon film56B.” Voids are formed at the boundary60. The voids weaken attachment of the final monocrystalline silicon form56B to the monocrystalline silicon wafer56A.

As shown inFIG. 2e, the polysilicon layer56is located on the final monocrystalline silicon film56B and bonded thereto utilizing known silicon bond. The boundary60is never exposed to the high PECVDD temperatures used for forming the thick diamond layer52which could destroy the boundary60.

As shown inFIG. 2f, the sacrificial polysilicon wafer50is removed in an etching operation. There is no need for tight control over the etching operation because the thick diamond layer52acts as an etch stop. The sacrificial polysilicon wafer50can thus be removed relatively fast.

InFIG. 2g, the combination wafer ofFIG. 2fis then flipped so that the monocrystalline silicon wafer56A is at the top.

As shown inFIG. 2h, the monocrystalline silicon wafer56A is removed from the final monocrystalline silicon film56B in a shearing operation. The shearing operation may for example involve a jet of gas which impinges on the monocrystalline silicon wafer56A. Because of the voids, the monocrystalline silicon wafer56A shears from the final monocrystalline silicon film56B at the boundary60, thus leaving only the final monocrystalline silicon film56B on the polysilicon layer54. The final monocrystalline silicon film56B is then etched and polished and subsequent processing in carried out as hereinbefore described with reference toFIGS. 1d-g.

The process described with reference toFIGS. 2a-hdiffers from the process described with reference toFIGS. 1a-gbecause the grinding operation to obtain the combined wafer ofFIG. 1cis eliminated. A much faster shearing operation is utilized to obtain the combination wafer ofFIG. 2h.

As shown inFIG. 2h, a thick diamond layer52is produced. The thick diamond layer52has the same advantages and disadvantages as the thick diamond layer12ofFIG. 1c.

Utilizing a Shearing Operation in the Production of a Thin Diamond Layer

InFIG. 3a, a sacrificial polysilicon wafer70is provided in which a thin diamond layer72is deposited followed by a polysilicon layer74. The thin diamond layer72is between 50 and 150 microns thick and is deposited utilizing the same PECVDD technology hereinbefore described. InFIG. 3b, the combination wafer ofFIG. 3ais flipped so that the polysilicon layer74is at the bottom. InFIG. 3c, a monocrystalline silicon wafer80is implanted with ions82. As shown inFIG. 3d, the ions create a boundary84between a lower monocrystalline silicon wafer56A and then upper final monocrystalline silicon film56B. InFIG. 3ethe polysilicon layer74is bonded to the final monocrystalline silicon film56B. The similarities betweenFIGS. 3a-3ewithFIGS. 2a-2eare evident. InFIG. 3f, the combination wafer ofFIG. 3eis flipped so that the monocrystalline silicon wafer56A is at the top. As shown inFIG. 3g, the monocrystalline silicon wafer56A is then sheared from the final monocrystalline silicon film56B. The shearing is similar to the shearing described with reference toFIG. 2h. An upper surface of the final monocrystalline silicon film56B is then etched and polished.

As shown inFIG. 3h, further processing is then carried out to form integrated circuits80A and80B followed by the formation of solder bump contacts82. The sacrificial polysilicon wafer70provides the structural support for all the layers and components formed thereon. The thin diamond layer72is generally not thick enough to support the layers thereon without the sacrificial polysilicon layer70. The sacrificial polysilicon layer70provides a lower silicon surface which is similar to conventional silicon wafers. Conventional tools and equipment which are designed to process conventional silicon wafers can be used to also process the combined wafer ofFIGS. 3gand3h.

A conventional saw is then used to saw through a scribe street90between the integrated circuits80A and80B. The saw cuts through the final monocrystalline silicon film56B, the polysilicon layer74, the thin diamond layer72, and the sacrificial polysilicon wafer70. A conventional saw blade can be used for cutting through the thin diamond layer72because it is merely between 50 and 150 microns thick.

FIG. 3iillustrates an electronic assembly100including a package substrate102and one die104on the package substrate102. The die104includes respective portions of the sacrificial polysilicon wafer70, the thin diamond layer72, the polysilicon layer74, the final monocrystalline silicon film56B and the epitaxial silicon layer78. The die74also includes the integrated circuit80A, and some of the bumps82. The bumps82are located on contacts on the package substrate102.

The assembly100is then locating in a furnace so that the bumps82are melted, and then removed from the furnace so that the bumps82solidify and attach to the contact pads on the package substrate102thereby securing die104to the package substrate102.

The package substrate102is sufficiently thick and strong to support the die104without the sacrificial polysilicon wafer70. As shown inFIG. 3j, the sacrificial polysilicon wafer70may then be removed for example in an etching operation. Without removal of the polysilicon wafer70, the thin diamond layer may still be able to transfer heat from hot spots of the integrated circuit80A. However, heat is more easily removed from an upper surface of the thin diamond layer72if the sacrificial polysilicon wafer70is removed. After removal of the sacrificial polysilicon wafer70, the relatively thin die104is structurally supported by the package substrate102.

Dies with Bare Diamond

InFIG. 4a, a sacrificial polysilicon wafer106is provided in which a thin diamond layer108is deposited followed by a polysilicon layer110. The thin diamond layer108is between 50 and 200 microns thick and is deposited utilizing the same PECVDD technology hereinbefore described. InFIG. 4b, the combination wafer ofFIG. 4ais flipped so that the polysilicon layer110is at the bottom. InFIG. 4c, a monocrystalline silicon wafer112is implanted with ions114. As shown inFIG. 4d, the ions create a boundary116between a lower monocrystalline silicon wafer112A and then upper final monocrystalline silicon film112B. InFIG. 4ethe polysilicon layer110is bonded to the final monocrystalline silicon film112B. The similarities betweenFIGS. 4a-4ewithFIGS. 3a-3eare evident. InFIG. 4f, the combination wafer ofFIG. 4eis flipped so that the monocrystalline silicon wafer112A is at the top. As shown inFIG. 4g, the monocrystalline silicon wafer112A is then sheared from the final monocrystalline silicon film112B. The shearing is similar to the shearing described with reference toFIG. 2h. An upper surface of the final monocrystalline silicon film112B is then etched and polished.

As shown inFIG. 4h, further processing is then carried out to form an epitaxial silicon layer115and integrated circuits116A and116B followed by the formation of solder bump contacts118. The sacrificial polysilicon wafer106provides the structural support for all the layers and components formed thereon. The thin diamond layer108is generally not thick enough to support the layers thereon without the sacrificial polysilicon layer106. The sacrificial polysilicon layer106provides a lower silicon surface which is similar to conventional silicon wafers. Conventional tools and equipment which are designed to process conventional silicon wafers can be used to also process the combined wafer ofFIGS. 4gand4h.

As illustrated inFIG. 4i, the sacrificial polysilicon wafer106ofFIG. 4his then entirely removed to expose a lower surface of the thin diamond layer108. An initial portion of the sacrificial polysilicon wafer106is removed by grinding it down to near the thin diamond layer108. A remainder of the sacrificial polysilicon wafer106is then etched until it is entirely removed to expose the thin diamond layer108. An etchant is used which selectively removes the material of the sacrificial polysilicon wafer106over the material of the thin diamond layer108, so that the thin diamond layer108acts as an etch stop.

What remains, then, is a combination wafer which has a circular edge (seeFIG. 1e) with the thin diamond layer108comprising the bulk thereof. The thin diamond layer108, as mentioned, is between 50 and 200 microns thick. All the other layers thereon may in combination be 10 to 20 microns thick. The combination wafer ofFIG. 4imay, for example, have a diameter of 300 mm and a thickness of 100 microns. The diamond is stiff enough to prevent the combination wafer from cracking, especially when compared to a silicon die having the same thickness.

A convention saw may then be used to singulate the combination wafer ofFIG. 1iinto individual dies120as illustrated inFIG. 4j. Each die120has a portion of the thin diamond layer108which is exposed and forming a backside thereof. Each die120also has a plurality of the contacts118on an opposing side thereof. The contacts118are exposed, i.e., unattached, and form an array across a width of the paper and into the paper.

As illustrated inFIG. 4k, respective sets of the dies120are mounted back-to-back with an epoxy131between them. Each die120is also positioned against a package substrate130, with the contacts118against the respective package substrate130. The combination illustrated inFIG. 4kis then transferred through a reflow oven, whereafter each die120is bonded to a respective package substrate130. A very compact stacked arrangement is formed because the dies120are so thin, especially when compared to a typical silicon die.

As illustrated inFIG. 4l, one of the dies120A may alternatively be mounted to a package substrate130, and a thermally conductive metal heat slug132may be mounted against the thin diamond layer108thereof. Heat can conduct from the integrated circuit116A through the thin diamond layer108to the heat slug132, from where the heat can be convected away. The thin diamond layer108, forming the bulk of the die120A, conducts a large amount of heat away from the integrated circuit116a. A thermal resistance between the thin diamond layer108and the thermal heat slug132is kept at a minimum by locating the thermal heat slug132directly against the thin diamond layer108.