Display panel and display device

A display panel includes a frame region and a display region. The frame region includes a substrate, a base layer, a voltage signal trace, a planar layer, and a lead-out trace, and a packaging layer. The packaging layer extends to an outer side of the planar layer and is connected to the substrate. The display region includes an anode, and the lead-out trace extends outward from a side of the anode and overlaps the voltage signal trace. A length of an overlapping portion between the lead-out trace and the voltage signal trace is greater than a length of an orthographic projection of the overlapping portion on the substrate.

BACKGROUND OF INVENTION

Field of Invention

The preset invention relates to a display technology, and more particularly, to a display panel and a display device.

Description of Prior Art

With development of display technology, people are increasingly demanding high-quality display panels. For some high-resolution display panels, narrow frame display panels are required.

Referring toFIG. 1, it is a schematic view of narrow frame display panel in the prior art. There are components shown in theFIG. 1, for example, a substrate100′, a GOA driving circuit unit101′, an organic planar layer102′, an anode103′, a pixel defining layer104′, a cathode105′, a first inorganic layer106′ of a packaging layer, an organic layer107′ of a packaging layer, a second inorganic layer108′ of a packaging layer, a source/drain metal layer109′, which is a VSS signal trace, and a second blocking wall110′.

A distance from the second inorganic layer108′ to an edge of the second blocking wall110′ is L′ at the left and right frames of the panel in theFIG. 1. The greater the L′ value, the greater contact area between first inorganic layer106′, the second inorganic layer108′ of the packaging layer and the substrate100′. Since the contact area is greater, a binding force between the packaging layer and the substrate100′ is greater, and that peeling phenomenon is less likely to occur. However, in order to achieve the narrow frame display panel, it is necessary to compress the distance of L′ value, which results in peeling phenomenon occurred between the packaging layer and the substrate100′. Simultaneously, this causes poor edge packaging.

SUMMARY OF INVENTION

In one embodiment, a display panel and a display device are provided to solve the technical problem that current narrow frame display panels have a weak binding force between the packaging layer and the substrate when the frame width is compressed, which results in poor edge packaging.

A display panel includes a display region and a frame region disposed on both sides of the display region, and the frame region includes a substrate and a base layer, a voltage signal trace, a planar layer, and a lead-out trace, and a packaging layer that are sequentially disposed on the substrate, and the packaging layer extends to an outer side of the planar layer and is connected to the substrate. The display region includes the substrate and a driving circuit unit, the planar layer, and an anode that are sequentially disposed on the substrate, and the lead-out trace extends outward from a side of the anode and overlaps the voltage signal trace. A length of an overlapping portion between the lead-out trace and the voltage signal trace is greater than a length of an orthographic projection of the overlapping portion on the substrate. The base layer is provided with a plurality of trenches, and the voltage signal trace is formed on the base layer and the voltage signal trace is configured as a concave-convex structure. The display region further includes a pixel defining layer, a cathode, and the packaging layer that are disposed on the anode. The packaging layer corresponding to the display region includes a first inorganic layer, an organic layer, and a second inorganic layer that are disposed on the cathode.

In one embodiment, the lead-out trace is configured as a concave-convex structure and is overlapped with the voltage signal trace.

In one embodiment, the packaging layer comprises a first inorganic layer disposed on the lead-out trace, and an overlapping region of the first inorganic layer and the lead-out trace is configured as a concave-convex structure.

In one embodiment, the base layer is an insulating organic layer or an insulating inorganic layer.

In one embodiment, the voltage signal trace is a VSS trace or a VDD trace.

A display panel includes a display region and a frame region disposed on both sides of the display region, and the frame region includes a substrate and a base layer, a voltage signal trace, a planar layer, a lead-out trace, and a packaging layer that are sequentially disposed on the substrate, and the packaging layer extends to an outer side of the planar layer and is connected to the substrate. The display region includes the substrate and a driving circuit unit, the planar layer, and an anode that are sequentially disposed on the substrate, and the lead-out trace extends outward from a side of the anode and overlaps the voltage signal trace. A length of an overlapping portion of the lead-out trace and the voltage signal trace is greater than a length of an orthographic projection of the overlapping portion on the substrate.

In one embodiment, the base layer is provided with a plurality of trenches, and the voltage signal trace is formed on the base layer and the voltage signal trace is configured as a concave-convex structure.

In one embodiment, the lead-out trace is configured as a concave-convex structure and overlapped with the voltage signal trace.

In one embodiment, the packaging layer includes a first inorganic layer disposed on the lead-out trace, and an overlapping region of the first inorganic layer and the lead-out trace is configured as a concave-convex structure. The frame region further includes a first blocking wall and a second blocking wall122that are disposed at an end of the lead-out trace. The first blocking wall is disposed near to the display region and the second blocking wall122is disposed away from the display region.

In one embodiment, the base layer is an insulating organic layer or an insulating inorganic layer.

In one embodiment, the voltage signal trace is a VSS trace or a VDD trace.

In one embodiment, the display region further includes a pixel defining layer, a cathode, and the packaging layer that are disposed on the anode, and the packaging layer corresponding to the display region includes a first inorganic layer, an organic layer, and a second inorganic layer that are disposed on the cathode.

A display device includes a display panel, and the display panel includes a display region and a frame region disposed on both sides of the display region, and the frame region includes a substrate and a base layer, a voltage signal trace, a planar layer, a lead-out trace, and a packaging layer that are sequentially disposed on the substrate, and the packaging layer extends to an outer side of the planar layer and is connected to the substrate. The display region includes the substrate and a driving circuit unit, the planar layer, and an anode that are sequentially disposed on the substrate, and the lead-out trace extends outward from a side of the anode and overlaps the voltage signal trace. A length of an overlapping portion between the lead-out trace and the voltage signal trace is greater than a length of an orthographic projection of the overlapping portion on the substrate.

In one embodiment, the base layer is provided with a plurality of trenches, and the voltage signal trace is formed on the base layer and the voltage signal trace is configured as a concave-convex structure.

In one embodiment, the lead-out trace is configured as a concave-convex structure and overlapped with the voltage signal trace.

In one embodiment, the packaging layer includes a first inorganic layer disposed on the lead-out trace, and an overlapping region of the first inorganic layer and the lead-out trace is configured as a concave-convex structure.

In one embodiment, the base layer is an insulating organic layer or an insulating inorganic layer.

In one embodiment, the voltage signal trace is a VSS trace or a VDD trace.

In one embodiment, the display region further includes a pixel defining layer, a cathode, and the packaging layer that are disposed on the anode, and the packaging layer corresponding to the display region includes a first inorganic layer, an organic layer, and a second inorganic layer that are disposed on the cathode.

Compared the display panel and the display device according to the embodiment of the present invention with conventional narrow frame display panels, a length of an overlapping between of the lead-out trace and the voltage signal trace is greater than a length of an orthographic projection of the overlapping portion on the substrate, so a length of projection of the voltage signal trace on the substrate is reduced. Thus, it is not necessary to reduce a distance from an edge of the packaging layer to an edge of the second blocking wall when a width of panel frame is reduced. Therefore, the technical problem that the current narrow frame display panel has a weak binding force between the packaging layer and the substrate when the frame width is compressed, which results in poor edge packaging, is solved.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Please refer to the attached drawings, in which the same reference numeral represents the same component. The following description is based on specific embodiments of the present invention as illustrated, and should not be construed as limiting the specific embodiments that are not described herein.

ReferringFIG. 2, it is a schematic view of a display panel according to one embodiment of the present invention. The display panel100includes display region10a(a part of the display panel shown in theFIG. 2) and a frame region10bdisposed on both sides of the display region10a.

The frame region10bincludes a substrate11and a base layer12, a voltage signal trace13, a planar layer14, a lead-out trace15, and a packaging layer16that are sequentially disposed on the substrate11. The packaging layer16extends from the display region10ato an outer side of the planar layer14and is connected to the substrate11.

The display region10aincludes a substrate11and a driving circuit unit17, a planar layer14, an anode18, a pixel defining layer19, cathode120, and a packaging layer16that are sequentially disposed on the substrate11. The packaging layer16corresponding to the display region10aincludes a first inorganic layer161, an organic layer162, and a second inorganic layer163that are disposed on the anode120.

The lead-out trace15extends outward from a side of the anode18and overlaps the voltage signal trace13.

A length of an overlapping portion between the lead-out trace15and the voltage signal trace13is greater than a length of an orthographic projection of the overlapping portion on the substrate11.

In the display panel100, a length of an overlapping portion between the lead-out trace15and the voltage signal trace13is greater than a length of an orthographic projection of the overlapping portion on the substrate11, so a length of projection of the voltage signal trace13on the substrate11is reduced. Thus, it is not necessary to reduce a distance L from an edge of the packaging layer16to an edge of the second blocking wall122when a width of panel frame is reduced.

In the display panel100, the base layer12is provided with a plurality of trenches121. The plurality of trenches121are disposed at interval from each other. The voltage signal trace13is formed on the base layer12, and thus the voltage signal trace13is present as a concave-convex structure. The voltage signal trace13, which is a concave-convex structure, not only ensures an effective overlapping length with the lead-out trace13but also compresses a plane projection width of the voltage signal trace13. Therefore, a distance L from an edge of the packaging layer16to an edge of the second blocking wall122is increased, and the frame region12bof the panel is improved to have a good packaging effect.

In addition, the base layer12is an insulating organic layer or an insulating inorganic layer. In one embodiment, the base layer12is an organic layer.

The base layer12including an organic material can improve the frame region12bto bend. A longitudinal cross-sectional shape of the voltage signal trace13, which is a convex-concave structure, also improves a bending performance of the voltage signal trace13. The voltage signal trace13may be a VSS trace or a VDD trace. It should be noted that, in the organic light emitting diode (OLED) display panel circuit, the VDD trace is connected to an anode terminal of the OLED for transmitting anode voltage, and the VSS trace is connected to a cathode terminal of the OLED for transmitting cathode voltage.

In the display panel100, the lead-out trace15is present as a concave-convex structure and overlapped with the voltage signal trace such that the lead-out trace15and the voltage signal trace13are sufficiently overlapped to achieve a maximum overlap length of the lead-out trace15and the voltage signal trace13.

In the display panel100, the packaging layer16includes a first inorganic layer161disposed on the lead-out trace15, and an overlapping region of the first inorganic layer161and the lead-out trace15is present as a concave-convex structure such that an overlapping area of the first inorganic layer161and the lead-out trace15is increased, thereby increasing a bonding area of the first inorganic layer161and the lead-out trace15, and a packaging stability is also improved.

A portion of the packaging layer16corresponding to the overlapping region further includes a second inorganic layer163. The second inorganic layer163is formed on the first inorganic layer161. In the portion corresponding to the overlapping region, the first inorganic layer161is fittingly overlapped with the second inorganic layer163such that such that an overlapping area of the first inorganic layer161and the second inorganic layer163is increased, thereby increasing a bonding area of the first inorganic layer161and the second inorganic layer163, and a packaging stability is also improved.

In addition, the frame region10bfurther includes a first blocking wall121and a second blocking wall122that are disposed at an end of the lead-out trace15. The first blocking wall121is disposed near to the display region10aand the second blocking wall122is disposed away from the display region10a.

The display panel100includes a substrate11, and a first setting region and a second setting region are disposed on the substrate11. The display region10ais disposed in the first setting region and the frame region10bis disposed in the second setting region.

A process of manufacturing the display panel100is described as follows.

In the first step, a buffer layer, a gate metal layer, an insulating layer, an active layer, and an interlayer dielectric layer are sequentially formed on the first setting region of the substrate11, and another interlayer dielectric layer is formed on the second setting region of the substrate11.

In the second step, the interlayer dielectric layer corresponding to the second setting region is processed to form a base layer12having a plurality of trenches121by a halftone mask.

In the third step, a voltage signal trace13is formed on the base layer12, and a source and drain metal layer is formed at the interlayer dielectric layer corresponding to the first setting region to achieve a driving circuit unit17disposed in the display region10a.

In the fourth step, a planar layer14is formed on the driving circuit unit17and the voltage signal trace13.

In the fifth step, the lead-out trace15, a first blocking wall121, and a second blocking wall122are sequentially formed on the planar layer14corresponding the first setting region, and an anode18, a pixel defining layer19, and a cathode are sequentially formed on the planar layer14corresponding to the second setting region.

Finally, a packaging layer16is formed on the above structure, so the manufacturing process is completed.

In another embodiment, a display device includes a display panel, and the display panel includes a display region and a frame region disposed on both sides of the display region, and the frame region includes a substrate and a base layer, a voltage signal trace, a planar layer, a lead-out trace, and a packaging layer that are sequentially disposed on the substrate, and the packaging layer extends to an outer side of the planar layer and is connected to the substrate, and the display region includes the substrate and a driving circuit unit, the planar layer, and an anode that are sequentially disposed on the substrate, and the lead-out trace extends outward from a side of the anode and overlaps the voltage signal trace, and a length of an overlapping portion between the lead-out trace and the voltage signal trace is greater than a length of an orthographic projection of the overlapping portion on the substrate.

In the display device, the base layer is provided with a plurality of trenches, and the voltage signal trace is formed on the base layer and the voltage signal trace is configured as a concave-convex structure.

In the display device, the lead-out trace is configured as a concave-convex structure and overlapped with the voltage signal trace.

In the display device, the packaging layer comprises a first inorganic layer disposed on the lead-out trace, and an overlapping region of the first inorganic layer and the lead-out trace is configured as a concave-convex structure.

In the display device, the base layer is an insulating organic layer or an insulating inorganic layer.

In the display device, the voltage signal trace is a VSS trace or a VDD trace.

In the display device, the display region further includes a pixel defining layer, a cathode, and the packaging layer that are disposed on the anode, and the packaging layer corresponding to the display region comprises a first inorganic layer, an organic layer, and a second inorganic layer that are disposed on the cathode.

Compared the display panel and the display device according to the embodiment of the present invention with conventional narrow frame display panels, a length of an overlapping portion between the lead-out trace and the voltage signal trace is greater than a length of an orthographic projection of the overlapping portion on the substrate, so a length of projection of the voltage signal trace on the substrate is reduced. Thus, it is not necessary to reduce a distance from an edge of the packaging layer to an edge of the second blocking wall when a width of panel frame is reduced. Therefore, the technical problem that the current narrow frame display panel has a weak binding force between the packaging layer and the substrate when the frame width is compressed, which results in poor edge packaging, is solved.

In the above, the present invention has been described in the above preferred embodiments, but the preferred embodiments are not intended to limit the scope of the invention, and a person skilled in the art may make various modifications without departing from the spirit and scope of the present invention. The scope of the present invention is determined by claims.