Method of forming molded panel embedded die structure

Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using large panel format and use of molding to improve rigidity of the panel, as well as to embed the die in a non-sacrificial mold material. The methods and structures described include methods for manufacturing thin, coreless substrate architectures which possess low warpage.

BACK GROUND OF THE INVENTION

As semiconductor technology advances for higher processor performance, advances in packaging architectures may include coreless package structures, such as bumpless build-up Layer (BBUL-C) package architectures and other such assemblies. Current process flows for coreless packages involve building the substrate up on a temporary core/carrier capped with copper foil, which is then etched off after the package is separated from the core. For example, typical embedded die package structures and coreless high density interconnect (HDI) substrates depend on the use of sacrificial panel cores.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

Methods and associated structures of forming and utilizing microelectronic structures, such as package structures comprising molded panels with embedded die, are described. Those methods/structures may include forming a first thin foil on a first side of a base foil and a second thin foil on a second side of the base foil, forming a first molding material directly on the first thin foil and forming a first molding material directly on the second thin foil, wherein the first mold material is non-sacrificial, and then coupling at least one die to the first molding material. The molded panel package structures enables dual sided processing of molded panel substrate core architectures, wherein the molded panel is retained in the final package structure.

FIGS. 1a-1hdepict cross-sectional views of embodiments of forming molded panel substrate structures. InFIG. 1a, a first thin foil102may be formed on/attached to a first side103of a base foil and a second thin foil102′ may be formed on/attached to a second side105of the base foil100. In an embodiment, the base foil100and the first and second thin foil102,102′ may comprise a copper material, but may comprise other suitable conductive materials in an embodiment. In an embodiment, the base foil100may comprise a thickness of about 20 to about 100 microns, and at least one of the first and second thin foils102,102′ may comprise a thickness of about 5 to about 10 microns. In an embodiment, the base foil100thickness may be optimized depending upon the particular stiffness required for a particular packaging application. In an embodiment, the first and second thin foils102,102′ may be attached to the base foil100with an adhesive material. In an embodiment, fiducial structures101may be formed on/in the first and second thin foils102,102′. The fiducials101may be formed by a drilling and/or marking processes. The fiducials101may be spaced apart from one another to facilitate subsequent placement of die on the first and second thin foils102,102′.

At least one die108may be attached to the first thin foil102and may be attached to the second thin foil102′ (FIG. 1b). The at least one die108may comprise a die backside film106, a die body104and interconnect structures109. The fiducial structures101may serve as alignment fiducials to allow for precise placement of the at least one die108on the first and second layers of thin foil102,102′.

In an embodiment, a non-sacrificial molding material110,110′ may be applied to both the first thin foil102and the second thin foil102′ respectively (FIG. 1c). In an embodiment, the molding material may comprise a first molding material110and a second molding material110′. The molding material110,110′ may comprise any suitable molding material according to the particular application, and may surround the at least one die108. In some embodiments, the molding material110,110′ may comprise materials such as epoxy materials, epoxy-silica composites and/or other thermosetting systems such as silicone-silica composites, and/or epoxy-silicone silica composites. In an embodiment, the molding material110,110′ may comprise a thickness of between about 100 to about 400 microns, but may vary according to the particular application. In an embodiment, the molding material110,110′ may be applied using such techniques as compression molding, injection molding and/or transfer molding techniques. In an embodiment, the at least one die108may be embedded in the molding material110,110′.

In an embodiment, the interconnect structures109of the at least one die108may be protected during the molding process by the use of a flexible film that may be placed between the interconnect structures109and a top surface of the mold material110,110′. A mold compound flash step may be employed after the mold material110,110′ is cured, so that remnants of the mold material110,110′ disposed on top of the interconnect structures109may be removed. In addition, additional mold residue that mat be present on top of the interconnect structures109may be removed prior to a subsequent conductive seed layer deposition, by using either a pre deposition plasma clean, or a desmear process. The mold compound110,110′ may be chosen to optimize desired thermo mechanical properties such that package structures utilizing the molded panel structures disclosed herein may provide stiffening for the entire stack once the mold compound is cured, and to provide package warpage benefits after singulation of die from the molded panel structures, as well as providing mechanical support during subsequent processing such as surface mount attach processing.

At least one build up layer115,115′ may be formed on the mold material110,110′ (FIG. 1d). The at least on build up layer115,115′ may comprise a dielectric layer112and conductive layer114. In an embodiment, a plurality of build up layers115,115′ may be stacked upon each other according to the particular application. In an embodiment, a multi-layer dual sided molded panel120may be formed comprising non-sacrificial molding110,110′.

In an embodiment, each side of the molded panel120may be de-paneled at the thin foil102,102′-base foil100interface, thus creating two individual molded panels121,121comprising embedded die108(FIG. 1e). The thin foil102,102′ may be removed in an embodiment from the molded panels121,121′ (depicting molded panel121only) (FIG. 1f). The foil102,102′ may be removed using an etching process in some embodiments. Bumps116, which may comprise solder interconnect bumps116, may be formed on/coupled with the build up layers115,115′ (FIG. 1g). Individual die of the least one die108may be singulated from the molded panels121,121′ to create embedded, molded die packages123(FIG. 1h). In an embodiment, the base foil100maybe recycled to create another molded panel.

In another embodiment, a molded panel core architecture may be formed comprising molding material formed directly on the foil (FIGS. 2a-2g). InFIG. 2a, a thin foil202may be formed/attached on a first side203of a base foil200and a thin foil202′ may be formed/attached on a second side205of the base foil200. A lamination process may be used to attach the thin foil202,202′ to the base foil200. In an embodiment, the base foil200and the thin foil202,202′ may comprise a copper material, and their respective thicknesses may be optimized depending upon the requirements of a particular application. In an embodiment, fiducial structures201may be formed on/in the thin foil202,202′. The fiducials201may be formed by a drilling and/or marking processes (such as by utilizing a laser and or a mechanical process). The fiducials201may be used to align the placement of die to be subsequently attached to the core structure.

In an embodiment, a molding material210,210′ may be applied directly to both the thin foil202disposed an the first side203of the base foil200and the thin foil202′ disposed on the second side205of the base foil200(FIG. 2b). The molding material210,210′ may comprise any suitable molding material according to the particular application. In an embodiment, the molding material210,210′ may comprise a thickness of between about 100 to about 400 microns.

At least one build up layer215,215′ may be formed on the mold material210,210′ (FIG. 2c). The at least one build up layer215,215′ may comprise dielectric layer212and conductive layer214. In an embodiment, a plurality of build up layers215,215′ may be stacked upon each other on the first side203of the base foil200and on the second side205of the base foil200, according to the particular application. In an embodiment, the initial build up layers215may be formed directly on the molding material210,210′ on both sides of the base foil200.

In an embodiment, a thin, careless multi layered, dual sided panel220may be formed, wherein the panel dual sided panel220comprises minimal warpage due to the non-sacrificial210,210′ molding material incorporated into the panel220. In an embodiment, the dual sided panels220may be separated/de-paneled at the base material200(FIG. 2d) to form two individual molded panels217,217′, and the thin foil202,202′ may be removed from the thin molding material110,110′ (depicting individual panel217) (FIG. 2e).

Bumps216, which may comprise solder interconnect bumps,216, may be formed on/coupled with the build up layers215,215′. In an embodiment, the molding material210,210′ may be patterned and etched to form openings218(FIG. 2f). At least one die208may be coupled with the openings218in the molding material210,210′ of the panels217,217′. In an embodiment, the at least one die208may be singulated from the molded panels217,217′ to create a careless, molded die package223(FIG. 2g).

In another embodiment, a molded panel core architecture may be formed comprising molding material formed directly on the fail (FIGS. 3a-3h). InFIG. 3a, a thin foil302may be formed/attached on a first side303of a base foil300and a thin foil302′ may be formed/attached on a second side305of the base foil300. A lamination process may be used to attach the thin foil302,302′ to the base foil300. In an embodiment, the base foil300and the thin foil302,302′ may comprise a copper material, and their respective thicknesses may be optimized depending upon the requirements of a particular application. In an embodiment, fiducial structures301may be formed on/in the thin foil302,302′. The fiducials301may be formed by a drilling and/or marking processes.

In an embodiment, a thin molding material310,310′ may be applied directly to both the thin foil302disposed on the first side303of the base foil300and the thin foil302′ disposed on the second side305of the base foil300(FIG. 3b). The thin molding material310,310′ may comprise any suitable molding material according to the particular application, and may comprise a first molding material310,310′ in an embodiment. In an embodiment, the thin molding material310,310′ may comprise a thickness of between about 100 to about 400 microns.

At least one die308may be attached to the thin molding material310,310′ (FIG. 3c). The at least one die308may comprise a die backside film306, a die body304and interconnect structures309. The fiducial structures301may serve as alignment fiducials to allow for precise placement of the at least one die308on the layers of thin molding material310,310′, wherein the at least one die308may be positioned between fiducial structures301.

In an embodiment, a molding material311,311may be applied to the thin molding material310,310′ and may surround the at least one die308, wherein the interconnect structures309of the at least one die308are exposed (FIG. 3d). The molding material311,311′ may comprise a second mold material311,311′. The molding material311,311′ may comprise with any suitable molding material according to the particular application, and may surround the at least one die308. In an embodiment, the molding material311,311′ may comprise a thickness of between about 100 to about 400 microns, but may vary according to the particular application. In an embodiment, the molding material311,311′ may be applied using a compression injection or a transfer molding technique, wherein the interconnect structures309of the at least one die308are exposed.

At least one build up layer315,315′ may be formed on the second molding material311,311′ and may the interconnect structures309of the at least one die308may be coupled with a conductive layer314of the at least one build up layer315,315′ (FIG. 3e). The at least one build up layer315,315′ may comprise a dielectric layer312and conductive layer314. In an embodiment, a ball grid array land may be formed within the build up layer315,315′, wherein the conductive layer314may serve as a ball grid array pad. In another embodiment, a package on package (PoP) land may be formed within the build up layer315,315′, wherein a portion of the conductive layer may serve as a PoP pad.

In an embodiment, a thin, coreless multi layered, dual sided panel317,317′ may be formed, wherein the panels317,317′ comprise minimal warpage due to the non-sacrificial310,310′ molding material incorporated into the panel317,317′. In an embodiment, the dual sided panels317,317′ may be separated at the base material300(FIG. 3f), and the thin foil302,302′ may be removed from the base foil300(depicting only individual panel317) (FIG. 3g). In an embodiment, the molding material310,310′ may be patterned and etched to form openings320(FIG. 3h). The openings may comprise through mold vias320. In an embodiment, a package on package (PoP) pad can be embedded in the buildup layer315,315′ above the at least one die, wherein the openings320may expose the PoP pad, which may be adjacent the at least one die308in some cases.

Bumps316, which may comprise solder interconnect bumps,316, may be formed on/coupled with the build up layers315,315′. In an embodiment, the at least one die308may be singulated from the molded panels317,317′ to create an embedded, molded die package.

The various embodiments of the package structures herein enable the fabrication of low cost, dual sided, embedded die, coreless substrates. Low warpage, HDI package structures are enabled. Panel level compression injection or transfer molding techniques may be utilized herein to produce molded panel core substrates. Non-sacrificial molding is used during the packaging structure fabrication, which provides rigidity, lowers warpage and lowers fabrication cost. Keep out zones are not required since the use of strip level molding is avoided. The embedded packages herein may be employed/coupled with in system on chip (SOC), central processing units (CPU), chipsets, radio devices, for example, to provide a low cost alternative to embedded die packaging.

In an embodiment, the package substrates of the embodiments herein (such as the package structures depicted inFIGS. 1h, 2g, 3h, for example), which may comprise molding compounds coupled with conductive layers that may be built up and separated by insulating materials (build up layers), wherein the molded panel structures may be coupled with various microelectronic devices. The devices may comprise such devices as a microelectronic memory die and a central processing unit (CPU) die in some cases, but may comprise any type of suitable device according to the particular application. In an embodiment, the package substrates herein may comprise a portion of an organic core package, and a careless, bumpless build up layer (BBUL) package structure, and may comprise PoP packages and through mold vies (TMV).

In an embodiment, the package structures of the embodiments herein may comprise any type of package substrate capable of providing electrical communications between a microelectronic device, such as a die and a next-level component to which the package structures may be coupled (e.g., a circuit board). In another embodiment, the package substrates herein may comprise any suitable type of package structures capable of providing electrical communication between a die and an upper integrated circuit (IC) package coupled with the device layer.

In some embodiments the package substrate/structure may further comprise a plurality of dies, which may be stacked upon one another, depending upon the particular embodiment. In some cases the die(s) may be located/attached/embedded on either the front side, back side or on/in some combination of the front and back sides of a package structure. In an embodiment, the die(s) may be partially or fully embedded in a package structure of the embodiments. The package structure may comprise a multi-chip 3D package structure that may include a central processing unit (CPU) in combination with other devices in an embodiment.

Turning now toFIG. 4, illustrated is an embodiment of a computing system400. The system400includes a number of components disposed on a mainboard410or other circuit board. Mainboard410includes a first side412and an opposing second side414, and various components may be disposed on either one or both of the first and second sides412,414. In the illustrated embodiment, the computing system400includes a package structure440disposed on the mainboard's first side412, wherein the package structure440may comprise any of the package substrates with molded panel core structure embodiments described herein.

System400may comprise any type of computing system, such as, for example, a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a nettop computer, etc.). However, the disclosed embodiments are not limited to hand-held and other mobile computing devices and these embodiments may find application in other types of computing systems, such as desk-top computers and servers.

Mainboard410may comprise any suitable type of curt board or other substrate capable of providing electrical communication between one or more of the various components disposed on the board. In one embodiment, for example, the mainboard410comprises a printed circuit board (PCB) comprising multiple metal layers separated from one another by a layer of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route —perhaps in conjunction with other metal layers—electrical signals between the components coupled with the board410. However, it should be understood that the disclosed embodiments are not limited to the above-described PCB and, further, that mainboard314may comprise any other suitable substrate.

In addition to the package structure440, one or more additional components may be disposed on either one or both sides412,414of the mainboard410. By way of example, as shown in the figures, components401amay be disposed on the first side412of the mainboard410, and components401bmay be disposed on the mainboard's opposing side414. Additional components that may be disposed on the mainboard410include other IC devices (e.g., processing devices, memory devices, signal processing devices, wireless communication devices, graphics controllers and/or drivers, audio processors and/or controllers, etc.), power delivery components (e.g., a voltage regulator and/or other power management devices, a power supply such as a battery, and/or passive devices such as a capacitor), and one or more user interface devices (e.g., an audio input device, an audio output device, a keypad or other data entry device such as a touch screen display, and/or a graphics display, etc.), as well as any combination of these and/or other devices.

In one embodiment, the computing system400includes a radiation shield. In a further embodiment, the computing system400includes a cooling solution. In yet another embodiment, the computing system400includes an antenna. In yet a further embodiment, the assembly400may be disposed within a housing or case. Where the mainboard410is disposed within a housing, some of the components of computer system400—e.g., a user interface device such as a display or keypad, and/or a power supply, such as a battery—may be electrically coupled with the mainboard410(and/or a component disposed on this board) but may be mechanically coupled with the housing.

FIG. 5is a schematic of a computer system500according to an embodiment. The computer system500(also referred to as the electronic system500) as depicted can include a package structure/substrate that includes any of the several disclosed embodiments and their equivalents as set forth in this disclosure. The computer system500may be a mobile device such as a netbook computer. The computer system500may be a mobile device such as a wireless smart phone. The computer system500may be a desktop computer. The computer system500may be a hand-held reader. The computer system500may be integral to an automobile. The computer system500may be integral to a television.

In an embodiment, the electronic system500is a computer system that includes a system bus520to electrically couple the various components of the electronic system500. The system bus520is a single bus or any combination of busses according to various embodiments. The electronic system500includes a voltage source530that provides power to the integrated circuit510. In some embodiments, the voltage source530supplies current to the integrated circuit510through the system bus520.

The integrated circuit510is electrically, communicatively coupled to the system bus520and includes any circuit, or combination of circuits according to an embodiment, including the package/device of the various embodiments included herein. In an embodiment, the integrated circuit510includes a processor512that can include any type of packaging structures according to the embodiments herein. As used herein, the processor512may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor512includes any of the embodiments of the package structures disclosed herein. In an embodiment, SRAM embodiments are found in memory caches of the processor.

Other types of circuits that can be included in the integrated circuit510are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit514for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios and similar electronic systems. In an embodiment, the processor512includes on-die memory516such as static random-access memory (SRAM). In an embodiment, the processor512includes embedded on-die memory516such as embedded dynamic random-access memory (eDRAM).

In an embodiment, the integrated circuit510is complemented with a subsequent integrated circuit511. In an embodiment, the dual integrated circuit511includes embedded on-die memory517such as eDRAM. The dual integrated circuit511includes an RFIC dual processor513and a dual communications circuit515and dual on-de memory517such as SRAM. The dual communications circuit515may be configured for RF processing.

At least one passive device580is coupled to the subsequent integrated circuit511. In an embodiment, the electronic system500also includes an external memory540that in turn may include one or more memory elements suitable to the particular application, such as a main memory542in the form of RAM, one or more hard drives544, and/or one or more drives that handle removable media546, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory540may also be embedded memory548. In an embodiment, the electronic system500also includes a display device550, and an audio output560. In an embodiment, the electronic system500includes an input device such as a controller570that may be a keyboard mouse, touch pad, keypad, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system500. In an embodiment, an input device570includes a camera. In an embodiment, an input device570includes a digital sound recorder. In an embodiment, an input device570includes a camera and a digital sound recorder.

Although the foregoing description has specified certain steps and materials that may be used in the methods of the embodiments, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the embodiments as defined by the appended claims. In addition, the Figures provided herein illustrate only portions of exemplary microelectronic devices and associated package structures that pertain to the practice of the embodiments. Thus the embodiments are not limited to the structures described herein.