ACTIVE CAPACITOR CIRCUIT FOR DISPLAY VOLTAGE STABILIZATION

This disclosure provides systems, methods and apparatus including computer programs encoded on computer storage media for stabilization of display voltages when driving electromechanical display devices. In one aspect, a display apparatus is provided. The display apparatus includes a display array having row electrodes and column electrodes. The row electrodes are driven by a first voltage and the column electrodes are driven by a second voltage corresponding to image data. The display apparatus further includes a capacitor having a first side coupled to one or more row electrodes. The display apparatus further includes an active circuit having an output terminal coupled to a second side of the capacitor and an input terminal coupled to the one or more row electrodes. The active circuit is configured to output a base voltage applied to the second side of the capacitor.

DETAILED DESCRIPTION

The electrodes of the interferometric modulator (IMOD) display elements may be driven by different voltages to change the position of one electrode in relation to another. For example, voltages corresponding to image data may be driven to a first series of electrodes while a second series of electrodes is maintained at desired hold voltages to allow selectively changing of particular display element states without affecting the states of others. To prevent interference with display element operation, the voltages applied to the second series of electrodes is maintained substantially stable for a time period during which voltage transitions are being made to the first series of conductive layers. However, as the conductive layers form a capacitor structure, voltage changes according to the image data applied to the first electrodes cause voltage variations on the second electrodes. As such, a storage capacitor to damp these transients is included. The storage capacitor has a first side coupled to the second electrodes. The storage capacitor is provided to maintain the voltages applied to the second electrodes substantially stable while avoiding additional power consumption from a power supply that is applying a voltage to the second electrodes. If the storage capacitor is of a sufficient size, the voltage applied to the second electrodes may be maintained within a desired range during transitions on the first electrodes.

To reduce the size of the storage capacitor, an active circuit having an output coupled to the second side of the storage capacitor is included. The active circuit outputs a “base” voltage applied to the second side of the storage capacitor. The base voltage is at a level such that resulting charge flow between the display element and the storage capacitor causes the voltage applied to the second electrode to be maintained substantially stable. The active circuit may have an input coupled to the second electrode such that the base voltage is adjusted in response to the voltage on the second electrode. The active circuit may include a switching regulator such as a buck converter. The active circuit may adjust the base voltage applied to the second side of the storage capacitor to maintain the voltage of the second electrode substantially stable in response to changes in voltages applied to the first electrodes.

Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. Using an active circuit for applying a voltage on the second side of the storage capacitor according to the implementations described herein reduces the size of the storage capacitor. The size of the storage capacitor may be reduced while maintaining a voltage applied on the second electrodes substantially stable. Furthermore, the size and cost of the storage capacitor is reduced while ensuring power consumption used by the active circuit is not excessive. An overall reduction in one or more of capacitor size, power consumption, and transient amplitude is achievable over conventional systems without the active circuit.

An example of a suitable EMS or MEMS device or apparatus, to which the described implementations may apply, is a reflective display device. Reflective display devices can incorporate interferometric modulator (IMOD) display elements that can be implemented to selectively absorb and/or reflect light incident thereon using principles of optical interference. IMOD display elements can include a partial optical absorber, a reflector that is movable with respect to the absorber, and an optical resonant cavity defined between the absorber and the reflector. In some implementations, the reflector can be moved to two or more different positions, which can change the size of the optical resonant cavity and thereby affect the reflectance of the IMOD. The reflectance spectra of IMOD display elements can create fairly broad spectral bands that can be shifted across the visible wavelengths to generate different colors. The position of the spectral band can be adjusted by changing the thickness of the optical resonant cavity. One way of changing the optical resonant cavity is by changing the position of the reflector with respect to the absorber.

FIG. 1is an isometric view illustration depicting two adjacent interferometric modulator (IMOD) display elements in a series or array of display elements of an IMOD display device. The IMOD display device includes one or more interferometric EMS, such as MEMS, display elements. In these devices, the interferometric MEMS display elements can be configured in either a bright or dark state. In the bright (“relaxed,” “open” or “on,” etc.) state, the display element reflects a large portion of incident visible light. Conversely, in the dark (“actuated,” “closed” or “off,” etc.) state, the display element reflects little incident visible light. MEMS display elements can be configured to reflect predominantly at particular wavelengths of light allowing for a color display in addition to black and white. In some implementations, by using multiple display elements, different intensities of color primaries and shades of gray can be achieved.

The IMOD display device can include an array of IMOD display elements which may be arranged in rows and columns. Each display element in the array can include at least a pair of reflective and semi-reflective layers, such as a movable reflective layer (i.e., a movable layer, also referred to as a mechanical layer) and a fixed partially reflective layer (i.e., a stationary layer), positioned at a variable and controllable distance from each other to form an air gap (also referred to as an optical gap, cavity or optical resonant cavity). The movable reflective layer may be moved between at least two positions. For example, in a first position, i.e., a relaxed position, the movable reflective layer can be positioned at a distance from the fixed partially reflective layer. In a second position, i.e., an actuated position, the movable reflective layer can be positioned more closely to the partially reflective layer. Incident light that reflects from the two layers can interfere constructively and/or destructively depending on the position of the movable reflective layer and the wavelength(s) of the incident light, producing either an overall reflective or non-reflective state, for each display element. In some implementations, the display element may be in a reflective state when unactuated, reflecting light within the visible spectrum, and may be in a dark state when actuated, absorbing and/or destructively interfering light within the visible range. In some other implementations, however, an IMOD display element may be in a dark state when unactuated, and in a reflective state when actuated. In some implementations, the introduction of an applied voltage can drive the display elements to change states. In some other implementations, an applied charge can drive the display elements to change states.

The depicted portion of the array inFIG. 1includes two adjacent interferometric MEMS display elements in the form of IMOD display elements12. In the display element12on the right (as illustrated), the movable reflective layer14is illustrated in an actuated position near, adjacent or touching the optical stack16. The voltage Vbiasapplied across the display element12on the right is sufficient to move and also maintain the movable reflective layer14in the actuated position. In the display element12on the left (as illustrated), a movable reflective layer14is illustrated in a relaxed position at a distance (which may be predetermined based on design parameters) from an optical stack16, which includes a partially reflective layer. The voltage Voapplied across the display element12on the left is insufficient to cause actuation of the movable reflective layer14to an actuated position such as that of the display element12on the right.

InFIG. 1, the reflective properties of IMOD display elements12are generally illustrated with arrows indicating light13incident upon the IMOD display elements12, and light15reflecting from the display element12on the left. Most of the light13incident upon the display elements12may be transmitted through the transparent substrate20, toward the optical stack16. A portion of the light incident upon the optical stack16may be transmitted through the partially reflective layer of the optical stack16, and a portion will be reflected back through the transparent substrate20. The portion of light13that is transmitted through the optical stack16may be reflected from the movable reflective layer14, back toward (and through) the transparent substrate20. Interference (constructive and/or destructive) between the light reflected from the partially reflective layer of the optical stack16and the light reflected from the movable reflective layer14will determine in part the intensity of wavelength(s) of light15reflected from the display element12on the viewing or substrate side of the device. In some implementations, the transparent substrate20can be a glass substrate (sometimes referred to as a glass plate or panel). The glass substrate may be or include, for example, a borosilicate glass, a soda lime glass, quartz, Pyrex, or other suitable glass material. In some implementations, the glass substrate may have a thickness of 0.3, 0.5 or 0.7 millimeters, although in some implementations the glass substrate can be thicker (such as tens of millimeters) or thinner (such as less than 0.3 millimeters). In some implementations, a non-glass substrate can be used, such as a polycarbonate, acrylic, polyethylene terephthalate (PET) or polyether ether ketone (PEEK) substrate. In such an implementation, the non-glass substrate will likely have a thickness of less than 0.7 millimeters, although the substrate may be thicker depending on the design considerations. In some implementations, a non-transparent substrate, such as a metal foil or stainless steel-based substrate can be used. For example, a reverse-IMOD-based display, which includes a fixed reflective layer and a movable layer which is partially transmissive and partially reflective, may be configured to be viewed from the opposite side of a substrate as the display elements12ofFIG. 1and may be supported by a non-transparent substrate.

The optical stack16can include a single layer or several layers. The layer(s) can include one or more of an electrode layer, a partially reflective and partially transmissive layer, and a transparent dielectric layer. In some implementations, the optical stack16is electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more of the above layers onto a transparent substrate20. The electrode layer can be formed from a variety of materials, such as various metals, for example indium tin oxide (ITO). The partially reflective layer can be formed from a variety of materials that are partially reflective, such as various metals (e.g., chromium and/or molybdenum), semiconductors, and dielectrics. The partially reflective layer can be formed of one or more layers of materials, and each of the layers can be formed of a single material or a combination of materials. In some implementations, certain portions of the optical stack16can include a single semi-transparent thickness of metal or semiconductor which serves as both a partial optical absorber and electrical conductor, while different, electrically more conductive layers or portions (e.g., of the optical stack16or of other structures of the display element) can serve to bus signals between IMOD display elements. The optical stack16also can include one or more insulating or dielectric layers covering one or more conductive layers or an electrically conductive/partially absorptive layer.

In some implementations, at least some of the layer(s) of the optical stack16can be patterned into parallel strips, and may form row electrodes in a display device as described further below. As will be understood by one having ordinary skill in the art, the term “patterned” is used herein to refer to masking as well as etching processes. In some implementations, a highly conductive and reflective material, such as aluminum (Al), may be used for the movable reflective layer14, and these strips may form column electrodes in a display device. The movable reflective layer14may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the row electrodes of the optical stack16) to form columns deposited on top of supports, such as the illustrated posts18, and an intervening sacrificial material located between the posts18. When the sacrificial material is etched away, a defined gap19, or optical cavity, can be formed between the movable reflective layer14and the optical stack16. In some implementations, the spacing between posts18may be approximately 1-1000 μm, while the gap19may be approximately less than 10,000 Angstroms (A).

In some implementations, each IMOD display element, whether in the actuated or relaxed state, can be considered as a capacitor formed by the fixed and moving reflective layers. When no voltage is applied, the movable reflective layer14remains in a mechanically relaxed state, as illustrated by the display element12on the left inFIG. 1, with the gap19between the movable reflective layer14and optical stack16. However, when a potential difference, i.e., a voltage, is applied to at least one of a selected row and column, the capacitor formed at the intersection of the row and column electrodes at the corresponding display element becomes charged, and electrostatic forces pull the electrodes together. If the applied voltage exceeds a threshold, the movable reflective layer14can deform and move near or against the optical stack16. A dielectric layer (not shown) within the optical stack16may prevent shorting and control the separation distance between the layers14and16, as illustrated by the actuated display element12on the right inFIG. 1. The behavior can be the same regardless of the polarity of the applied potential difference. Though a series of display elements in an array may be referred to in some instances as “rows” or “columns,” a person having ordinary skill in the art will readily understand that referring to one direction as a “row” and another as a “column” is arbitrary. Restated, in some orientations, the rows can be considered columns, and the columns considered to be rows. In some implementations, the rows may be referred to as “common” lines and the columns may be referred to as “segment” lines, or vice versa. Furthermore, the display elements may be evenly arranged in orthogonal rows and columns (an “array”), or arranged in non-linear configurations, for example, having certain positional offsets with respect to one another (a “mosaic”). The terms “array” and “mosaic” may refer to either configuration. Thus, although the display is referred to as including an “array” or “mosaic,” the elements themselves need not be arranged orthogonally to one another, or disposed in an even distribution, in any instance, but may include arrangements having asymmetric shapes and unevenly distributed elements.

FIG. 2is a system block diagram illustrating an electronic device incorporating an IMOD-based display including a three element by three element array of IMOD display elements. The electronic device includes a processor21that may be configured to execute one or more software modules. In addition to executing an operating system, the processor21may be configured to execute one or more software applications, including a web browser, a telephone application, an email program, or any other software application.

The processor21can be configured to communicate with an array driver22. The array driver22can include a row driver circuit.24and a column driver circuit26that provide signals to, for example a display array or panel30. The cross section of the IMOD display device illustrated inFIG. 1is shown by the lines1-1inFIG. 2. AlthoughFIG. 2illustrates a 3×3 array of IMOD display elements for the sake of clarity, the display array30may contain a very large number of IMOD display elements, and may have a different number of IMOD display elements in rows than in columns, and vice versa.

FIG. 3is a graph illustrating movable reflective layer position versus applied voltage for an IMOD display element. For IMODs, the row/column (i.e., common/segment) write procedure may take advantage of a hysteresis property of the display elements as illustrated inFIG. 3. An IMOD display element may use, in one example implementation, about a 10-volt potential difference to cause the movable reflective layer, or mirror, to change from the relaxed state to the actuated state. When the voltage is reduced from that value, the movable reflective layer maintains its state as the voltage drops back below, in this example, 10 volts, however, the movable reflective layer does not relax completely until the voltage drops below 2 volts. Thus, a range of voltage, approximately 3-7 volts, in the example ofFIG. 3, exists where there is a window of applied voltage within which the element is stable in either the relaxed or actuated state. This is referred to herein as the “hysteresis window” or “stability window.” For a display array30having the hysteresis characteristics ofFIG. 3, the row/column write procedure can be designed to address one or more rows at a time. Thus, in this example, during the addressing of a given row, display elements that are to be actuated in the addressed row can be exposed to a voltage difference of about 10 volts, and display elements that are to be relaxed can be exposed to a voltage difference of near zero volts. After addressing, the display elements can be exposed to a steady state or bias voltage difference of approximately 5 volts in this example, such that they remain in the previously strobed, or written, state. In this example, after being addressed, each display element sees a potential difference within the “stability window” of about 3-7 volts. This hysteresis property feature enables the IMOD display element design to remain stable in either an actuated or relaxed pre-existing state under the same applied voltage conditions. Since each IMOD display element, whether in the actuated or relaxed state, can serve as a capacitor formed by the fixed and moving reflective layers, this stable state can be held at a steady voltage within the hysteresis window without substantially consuming or losing power. Moreover, essentially little or no current flows into the display element if the applied voltage potential remains substantially fixed.

In some implementations, a frame of an image may be created by applying data signals in the form of “segment” voltages along the set of column electrodes, in accordance with the desired change (if any) to the state of the display elements in a given row. Each row of the array can be addressed in turn, such that the frame is written one row at a time. To write the desired data to the display elements in a first row, segment voltages corresponding to the desired state of the display elements in the first row can be applied on the column electrodes, and a first row pulse in the form of a specific “common” voltage or signal can be applied to the first row electrode. The set of segment voltages can then be changed to correspond to the desired change (if any) to the state of the display elements in the second row, and a second common voltage can be applied to the second row electrode. In some implementations, the display elements in the first row are unaffected by the change in the segment voltages applied along the column electrodes, and remain in the state they were set to during the first common voltage row pulse. This process may be repeated for the entire series of rows, or alternatively, columns, in a sequential fashion to produce the image frame. The frames can be refreshed and/or updated with new image data by continually repeating this process at some desired number of frames per second.

The combination of segment and common signals applied across each display element (that is, the potential difference across each display element or pixel) determines the resulting state of each display element.FIG. 4is a table illustrating various states of an IMOD display element when various common and segment voltages are applied. As will be readily understood by one having ordinary skill in the art, the “segment” voltages can be applied to either the column electrodes or the row electrodes, and the “common” voltages can be applied to the other of the column electrodes or the row electrodes.

As illustrated inFIG. 4, when a release voltage VCRELis applied along a common line, all IMOD display elements along the common line will be placed in a relaxed state, alternatively referred to as a released or unactuated state, regardless of the voltage applied along the segment lines, i.e., high segment voltage VSHand low segment voltage VSL. In particular, when the release voltage VCRELis applied along a common line, the potential voltage across the modulator display elements or pixels (alternatively referred to as a display element or pixel voltage) can be within the relaxation window (seeFIG. 3, also referred to as a release window) both when the high segment voltage VSHand the low segment voltage VSLare applied along the corresponding segment line for that display element.

When a hold voltage is applied on a common line, such as a high hold voltage VCHOLD—Hor a low hold voltage VCHOLD—L, the state of the IMOD display element along that common line will remain constant. For example, a relaxed IMOD display element will remain in a relaxed position, and an actuated IMOD display element will remain in an actuated position. The hold voltages can be selected such that the display element voltage will remain within a stability window both when the high segment voltage VSHand the low segment voltage VSLare applied along the corresponding segment line. Thus, the segment voltage swing in this example is the difference between the high VSHand low segment voltage VSL, and is less than the width of either the positive or the negative stability window.

When an addressing, or actuation, voltage is applied on a common line, such as a high addressing voltage VCADD—Hor a low addressing voltage VCADD—L, data can be selectively written to the modulators along that common line by application of segment voltages along the respective segment lines. The segment voltages may be selected such that actuation is dependent upon the segment voltage applied. When an addressing voltage is applied along a common line, application of one segment voltage will result in a display element voltage within a stability window, causing the display element to remain unactuated. In contrast, application of the other segment voltage will result in a display element voltage beyond the stability window, resulting in actuation of the display element. The particular segment voltage which causes actuation can vary depending upon which addressing voltage is used. In some implementations, when the high addressing voltage VCADD—His applied along the common line, application of the high segment voltage VSHcan cause a modulator to remain in its current position, while application of the low segment voltage VSLcan cause actuation of the modulator. As a corollary, the effect of the segment voltages can be the opposite when a low addressing voltage VCADD—Lis applied, with high segment voltage VSHcausing actuation of the modulator, and low segment voltage VSLhaving substantially no effect (i.e., remaining stable) on the state of the modulator.

In some implementations, hold voltages, address voltages, and segment voltages may be used which produce the same polarity potential difference across the modulators. In some other implementations, signals can be used which alternate the polarity of the potential difference of the modulators from time to time. Alternation of the polarity across the modulators (that is, alternation of the polarity of write procedures) may reduce or inhibit charge accumulation that could occur after repeated write operations of a single polarity.

FIG. 5Ais an illustration of a frame of display data in a three element by three element array of IMOD display elements displaying an image.FIG. 5Bis a timing diagram for common and segment signals that may be used to write data to the display elements illustrated inFIG. 5A. The actuated IMOD display elements in FIG.5A, shown by darkened checkered patterns, are in a dark-state, i.e., where a substantial portion of the reflected light is outside of the visible spectrum so as to result in a dark appearance to, for example, a viewer. Each of the unactuated IMOD display elements reflect a color corresponding to their interferometric cavity gap heights. Prior to writing the frame illustrated inFIG. 5A, the display elements can be in any state, but the write procedure illustrated in the timing diagram ofFIG. 5Bpresumes that each modulator has been released and resides in an unactuated state before the first line time60a.

During the first line time60a: a release voltage70is applied on common line 1; the voltage applied on common line 2 begins at a high hold voltage72and moves to a release voltage70; and a low hold voltage76is applied along common line 3. Thus, the modulators (common 1, segment 1), (1,2) and (1,3) along common line 1 remain in a relaxed, or unactuated, state for the duration of the first line time60a, the modulators (2,1), (2,2) and (2,3) along common line 2 will move to a relaxed state, and the modulators (3,1), (3,2) and (3,3) along common line 3 will remain in their previous state. In some implementations, the segment voltages applied along segment lines 1, 2 and 3 will have no effect on the state of the IMOD display elements, as none of common lines 1, 2 or 3 are being exposed to voltage levels causing actuation during line time60a(i.e., VCREL—relax and VCHOLD—L—stable).

During the second line time60b, the voltage on common line 1 moves to a high hold voltage72, and all modulators along common line 1 remain in a relaxed state regardless of the segment voltage applied because no addressing, or actuation, voltage was applied on the common line 1. The modulators along common line 2 remain in a relaxed state due to the application of the release voltage70, and the modulators (3,1), (3,2) and (3,3) along common line 3 will relax when the voltage along common line 3 moves to a release voltage70.

During the third line time60c, common line 1 is addressed by applying a high address voltage74on common line 1. Because a low segment voltage64is applied along segment lines 1 and 2 during the application of this address voltage, the display element voltage across modulators (1,1) and (1,2) is greater than the high end of the positive stability window (i.e., the voltage differential exceeded a characteristic threshold) of the modulators, and the modulators (1,1) and (1,2) are actuated. Conversely, because a high segment voltage62is applied along segment line 3, the display element voltage across modulator (1,3) is less than that of modulators (1,1) and (1,2), and remains within the positive stability window of the modulator; modulator (1,3) thus remains relaxed. Also during line time60c, the voltage along common line 2 decreases to a low hold voltage76, and the voltage along common line 3 remains at a release voltage70, leaving the modulators along common lines 2 and 3 in a relaxed position.

During the fourth line time60d, the voltage on common line 1 returns to a high hold voltage72, leaving the modulators along common line 1 in their respective addressed states. The voltage on common line 2 is decreased to a low address voltage78. Because a high segment voltage62is applied along segment line 2, the display element voltage across modulator (2,2) is below the lower end of the negative stability window of the modulator, causing the modulator (2,2) to actuate. Conversely, because a low segment voltage64is applied along segment lines 1 and 3, the modulators (2,1) and (2,3) remain in a relaxed position. The voltage on common line 3 increases to a high hold voltage72, leaving the modulators along common line 3 in a relaxed state. Then, the voltage on common line 2 transitions back to the low hold voltage76.

Finally, during the fifth line time60e, the voltage on common line 1 remains at high hold voltage72, and the voltage on common line 2 remains at the low hold voltage76, leaving the modulators along common lines 1 and 2 in their respective addressed states. The voltage on common line 3 increases to a high address voltage74to address the modulators along common line 3. As a low segment voltage64is applied on segment lines 2 and 3, the modulators (3,2) and (3,3) actuate, while the high segment voltage62applied along segment line 1 causes modulator (3,1) to remain in a relaxed position. Thus, at the end of the fifth line time60e, the 3×3 display element array is in the state shown inFIG. 5A, and will remain in that state as long as the hold voltages are applied along the common lines, regardless of variations in the segment voltage which may occur when modulators along other common lines (not shown) are being addressed.

In the timing diagram ofFIG. 5B, a given write procedure (i.e., line times60a-60e) can include the use of either high hold and address voltages, or low hold and address voltages. Once the write procedure has been completed for a given common line (and the common voltage is set to the hold voltage having the same polarity as the actuation voltage), the display element voltage remains within a given stability window, and does not pass through the relaxation window until a release voltage is applied on that common line. Furthermore, as each modulator is released as part of the write procedure prior to addressing the modulator, the actuation time of a modulator, rather than the release time, may determine the line time. Specifically, in implementations in which the release time of a modulator is greater than the actuation time, the release voltage may be applied for longer than a single line time, as depicted inFIG. 5A. In some other implementations, voltages applied along common lines or segment lines may vary to account for variations in the actuation and release voltages of different modulators, such as modulators of different colors.

In some implementations, the packaging of an EMS component or device, such as an IMOD-based display, can include a backplate (alternatively referred to as a backplane, back glass or recessed glass) which can be configured to protect the EMS components from damage (such as from mechanical interference or potentially damaging substances). The backplate also can provide structural support for a wide range of components, including but not limited to driver circuitry, processors, memory, interconnect arrays, vapor barriers, product housing, and the like. In some implementations, the use of a backplate can facilitate integration of components and thereby reduce the volume, weight, and/or manufacturing costs of a portable electronic device.

FIGS. 6A and 6Bare schematic exploded partial perspective views of a portion of an EMS package91including an array36of EMS elements and a backplate92.FIG. 6Ais shown with two corners of the backplate92cut away to better illustrate certain portions of the backplate92, whileFIG. 6Bis shown without the corners cut away. The EMS array36can include a substrate20, support posts18, and a movable layer14. In some implementations, the EMS array36can include an array of IMOD display elements with one or more optical stack portions16on a transparent substrate, and the movable layer14can be implemented as a movable reflective layer.

The backplate92can be essentially planar or can have at least one contoured surface (e.g., the backplate92can be formed with recesses and/or protrusions). The backplate92may be made of any suitable material, whether transparent or opaque, conductive or insulating. Suitable materials for the backplate92include, but are not limited to, glass, plastic, ceramics, polymers, laminates, metals, metal foils, Kovar and plated Kovar.

As shown inFIGS. 6A and 6B, the backplate92can include one or more backplate components94aand94b, which can be partially or wholly embedded in the backplate92. As can be seen inFIG. 6A, backplate component94ais embedded in the backplate92. As can be seen inFIGS. 6A and 6B, backplate component94bis disposed within a recess93formed in a surface of the backplate92. In some implementations, the backplate components94aand/or94bcan protrude from a surface of the backplate92. Although backplate component94bis disposed on the side of the backplate92facing the substrate20, in other implementations, the backplate components can be disposed on the opposite side of the backplate92.

The backplate components94aand/or94bcan include one or more active or passive electrical components, such as transistors, capacitors, inductors, resistors, diodes, switches, and/or integrated circuits (ICs) such as a packaged, standard or discrete IC. Other examples of backplate components that can be used in various implementations include antennas, batteries, and sensors such as electrical, touch, optical, or chemical sensors, or thin-film deposited devices.

In some implementations, the backplate components94aand/or94bcan be in electrical communication with portions of the EMS array36. Conductive structures such as traces, bumps, posts, or vias may be formed on one or both of the backplate92or the substrate20and may contact one another or other conductive components to form electrical connections between the EMS array36and the backplate components94aand/or94b. For example,FIG. 6Bincludes one or more conductive vias96on the backplate92which can be aligned with electrical contacts98extending upward from the movable layers14within the EMS array36. In some implementations, the backplate92also can include one or more insulating layers that electrically insulate the backplate components94aand/or94bfrom other components of the EMS array36. In some implementations in which the backplate92is formed from vapor-permeable materials, an interior surface of backplate92can be coated with a vapor barrier (not shown).

The backplate components94aand94bcan include one or more desiccants which act to absorb any moisture that may enter the EMS package91. In some implementations, a desiccant (or other moisture absorbing materials, such as a getter) may be provided separately from any other backplate components, for example as a sheet that is mounted to the backplate92(or in a recess formed therein) with adhesive. Alternatively, the desiccant may be integrated into the backplate92. In some other implementations, the desiccant may be applied directly or indirectly over other backplate components, for example by spray-coating, screen printing, or any other suitable method.

In some implementations, the EMS array36and/or the backplate92can include mechanical standoffs97to maintain a distance between the backplate components and the display elements and thereby prevent mechanical interference between those components. In the implementation illustrated inFIGS. 6A and 6B, the mechanical standoffs97are formed as posts protruding from the backplate92in alignment with the support posts18of the EMS array36. Alternatively or in addition, mechanical standoffs, such as rails or posts, can be provided along the edges of the EMS package91.

Although not illustrated inFIGS. 6A and 6B, a seal can be provided which partially or completely encircles the EMS array36. Together with the backplate92and the substrate20, the seal can form a protective cavity enclosing the EMS array36. The seal may be a semi-hermetic seal, such as a conventional epoxy-based adhesive. In some other implementations, the seal may be a hermetic seal, such as a thin film metal weld or a glass frit. In some other implementations, the seal may include polyisobutylene (PIB), polyurethane, liquid spin-on glass, solder, polymers, plastics, or other materials. In some implementations, a reinforced sealant can be used to form mechanical standoffs.

In alternate implementations, a seal ring may include an extension of either one or both of the backplate92or the substrate20. For example, the seal ring may include a mechanical extension (not shown) of the backplate92. In some implementations, the seal ring may include a separate member, such as an O-ring or other annular member.

In some implementations, the EMS array36and the backplate92are separately formed before being attached or coupled together. For example, the edge of the substrate20can be attached and sealed to the edge of the backplate92as discussed above. Alternatively, the EMS array36and the backplate92can be formed and joined together as the EMS package91. In some other implementations, the EMS package91can be fabricated in any other suitable manner, such as by forming components of the backplate92over the EMS array36by deposition.

FIG. 7is an illustration of one implementation of array driver circuitry with an associated power supply840. In many implementations of interferometric modulator display arrays, rows of display elements are configured to reflect different colors. In the simplified array ofFIG. 7, the top row842is a red row, the center row844is a green row, and the bottom row846is a blue row. Different color rows utilize different voltage levels for hold, actuate, etc., and so each different color row is selectively connected through a multiplexer850to one of the five different voltages shown inFIG. 4, where each set of five voltages may be different for each color. In many implementations, there will be hundreds or even thousands of rows of each color, each one associated with a multiplexer coupled to the set of five power supply outputs suitable for the color of that row. Because three different color rows are generally used in a color display (e.g. one third of the rows are red, one third are green, and one third are blue), each hold voltage output may be connected to about one third of the row electrodes in the array. The multiplexers850are controlled by timing/control logic circuitry860, which controls the multiplexers850to output the appropriate voltage to each row and each column with the desired timing to produce write waveforms such as shown above inFIG. 5Bto write image data to the display array.

As described above with reference toFIGS. 2-5, before image data is written to an interferometric modulator (IMOD) display element12, a row driver circuit24drives row electrodes of the display panel30with a hold voltage72or76, VCHOLD—Hor VCHOLD—L(hereinafter collectively VCHOLD). As an example, VCHOLDmay be about positive and negative 12 Volts (V), and as noted above, may vary for different color rows. While VCHOLDis applied to the row electrodes, the column driver circuit26drives the column electrodes of the display panel with voltages VSHor VSL62or64corresponding to image data to be written to that row. As an example, VSHand VSLmay be about positive or negative 2V. Thereafter, the row driver circuit24drives the row electrodes with VCADD—Hor VCADD—Lsuch that the display elements along a row selectively actuate, or are maintained in an un-actuated state depending on the total voltage across each display element12along that row during the application of VCADD—Hor VCADD—L. As used herein, the term “row” is synonymous with “common line,” and receives a data independent strobing signal. The term “column” is synonymous with “segment line,” and receives a data dependent signal. The terms row and column are not intended to denote any particular geometric orientation.

As can be seen inFIG. 5B, there is a time period when the row driver circuit24maintains the row electrodes at VCHOLDwhile the column driver circuit26changes voltages applied to the column electrodes of the display panel. See, for example, the boundary between line time60cand60d, where common lines 1 and 2 are at positive and negative VCHOLDwhile segment lines 2 and 3 transition to different voltage states. Because of the capacitive coupling between the row electrodes and the column electrodes at each display element, the voltage transition applied to the column electrodes on one side of this capacitance causes voltage transients to appear on the row electrodes on the opposite side of this capacitance.

FIG. 8is a schematic diagram of an implementation of the driver circuit ofFIG. 7with transient suppression capacitors802to reduce transients described above. With this circuit, voltage transients on the row electrodes are reduced using output capacitors802having one side coupled to each hold voltage output and the other side coupled to ground. The capacitor802is of a sufficient size and material such that a voltage of VCHOLDis maintained within a desired tolerance on the row electrode while the driver circuit causes voltages to transition between VSHand VSLon the column electrode when switching the column multiplexers between states. For example, in some implementations the capacitor802may be a tantalum capacitor of about 20-30 μF or more.

FIG. 9is a plot showing example voltage waveforms when driving an array of display elements according to the implementation shown inFIG. 8. The plot900shows voltage transients that appear at two different locations on a row electrode when the waveform908is applied to a set of column electrodes while the row driver circuit applies VCHOLDfrom the power supply to a set of row electrodes. In this simple model for illustrating the transient generation, the same signal908is applied to all the column electrodes, and the capacitive coupling between the row electrodes and the column electrodes remains constant. When actually writing data to a display array, at a given transition time, different column electrodes may undergo different polarity transitions (or no transition), the capacitive coupling will change as the state of the display elements of the array change, and thus each transient peak amplitude may be different depending on these generally changing factors. The voltage transients of the waveforms902and906show the increased impact of column electrode transitions at the far end of the row electrode when compared to the near end of the row electrode, due to series resistance along the row electrode. The magnitude of each transient peak will depend on the capacitance of the output capacitor802, the magnitude and polarity of the segment line transitions that occur, and the capacitive coupling between column electrodes undergoing transitions and the row electrodes coupled to the VCHOLDpower supply output. It is important that the voltage transients illustrated inFIG. 9be small enough that they do not interfere with the desired actuated and/or released state of the display elements following the application of the write pulse. Accordingly, the capacitance of the capacitors802ofFIG. 8are selected to be large enough so that even if all the columns transition in the same direction and all the display elements coupled to the VCHOLDoutput are in the high capacitance actuated state, the transients will still be maintained below a threshold for essentially error free data writing. In some implementations, it is desirable to use a capacitor802of sufficient size such that the worst case transients are limited to a maximum of about 80 mV.

While the passive capacitor circuit shown inFIG. 8reduces transients and relaxes the peak output power requirements of the row driver circuit24for maintaining VCHOLDduring column electrode transitions, the capacitor802may be large and expensive. The magnitude of VCHOLDis relatively large, often 15-20 V, and supplying current from the VCHOLDsupply uses power proportional to the square of this voltage. To minimize power losses, this capacitor802is of high capacitance, and the VCHOLDpower supply has a high output impedance to limit its current output in response to transient voltage changes on the column electrodes due to segment line transitions. Accordingly, certain aspects described herein provide different implementations for reducing the size of the capacitor802and while maintaining VCHOLDsufficiently stable to prevent voltage variations due to column electrode transitions to interfere with display element operation and/or actuation. In one aspect, the implementations described below may be able to prevent transients substantially above 80 mV to avoid interfering with operating margins, yield, and frame rate while utilizing an output capacitor802of far smaller capacitance than the capacitor normally utilized to suppress transients of the same degree.

FIG. 10is a schematic diagram of another implementation of a circuit for driving a display array while allowing the use of smaller and cheaper transient suppression capacitors802. Similar toFIG. 8, capacitors802have a first side coupled to the power supply hold voltage outputs. However, rather than connecting the other side of capacitors802to ground as inFIG. 8, an active circuit1002is included having an output terminal coupled to a second side of each capacitor802. The active circuit1002outputs a “base” voltage to the second side of each capacitor802. The active circuit1002may receive one or more inputs from the power supply840or the timing/control logic860to generate an appropriate base voltage output with the appropriate timing. As applied to this circuit, the term “active” means it receives inputs from the display array and/or driver circuitry and is configured to adjust its output(s) in response to row and/or column driving activities which occur during the image data writing process.

Initially, prior to writing a frame or series of frames of image data, the base voltages output by the active circuit1002may be driven to 0 V and the capacitors802may be charged to the desired hold voltages for each color and polarity by the power supply804. When writing image data, as the driver circuit transitions voltages of the column electrodes, a potentially non-zero base voltage is driven. The active circuit1002adjusts the base voltage to maintain the desired hold voltages on the row electrodes.

The active circuit1002can maintain the voltages applied to the row electrodes sufficiently stable while allowing for a relatively small size capacitor802. As such, a smaller and less expensive capacitor802may be used, for example as compared to the capacitor802ofFIG. 8. When the second side of the capacitors802are connected directly to ground, the size of the voltage transients is determined in part by the relative size of the capacitor802and the capacitance between the segment lines and the common lines connected to a given hold voltage output. With no active circuit, a 20 μF capacitor802may be required. With an active circuit1002, the transients will depend on both the size of the capacitor802, and also on the magnitudes of the voltage swings that can be applied to the second side of the capacitor. For example, in some implementations the capacitor802shown inFIG. 10may be on the order of 1 μF, and the base voltages applied by the active circuit1002may vary between about VSLand VSH. Although power consumption may be higher as compared to the implementation described above with reference toFIG. 8when a capacitor much larger than 1 μF is used, the implementation described with reference toFIG. 10allows for decreasing the expense and physical size of the capacitor802. Comparing the circuit ofFIG. 8with that ofFIG. 10for the same capacitor size, the power drain of the circuit is lower in the implementation ofFIG. 10, as the base voltage at which current is supplied to the capacitor is much less than VCHOLD, being generally between zero and VSLor VSH, which may be in the 1-2 V range, rather than 15-20 V range. The active circuit ofFIG. 10thus provides a way to provide an overall improvement and a better balance between the different characteristics of power draw, capacitor size, and transient amplitude as may be desired in a particular application.

FIG. 11is a schematic diagram of an implementation of the active transient compensation circuit1002ofFIG. 10for driving a display array.FIG. 11shows examples of components that may be included in the active circuit1002described above with reference toFIG. 10. The schematic ofFIG. 11shows only one capacitor802. To implement the system ofFIG. 10with a circuit as illustrated inFIG. 11, the active circuit1002would include six separate implementations of the circuit ofFIG. 11, one for each hold voltage output and corresponding capacitor.

InFIG. 11, C1represents the capacitance between the first column electrode and all the row electrodes that this hold voltage output is connected to (e.g., one third of the row electrodes of the array as described above), which will depend on the current actuated or released states of each display element at the intersections of the first column electrode and each row electrode this hold voltage output is connected to. The value ΔV1represents the magnitude of the voltage transition that the first column electrode sees during the data transition, which will depend on the voltage currently applied to the first column electrode and the voltage to be applied to the first column electrode to write the desired data. This transition may be from VSHto VSL, from VSLto VSH, or no transition may be performed on this column. The values of C2through Cnand ΔV1through ΔVnare defined similarly for column electrodes2through n of the display array.

The active circuit1002illustrated inFIG. 11includes a feedback amplifier1102that may receive a target voltage Vrefat the positive input and the voltage on the power supply output to the row electrodes at the negative input. The amplifier will adjust the base voltage on the capacitor802to the level necessary to maintain the voltage on the row electrodes at Vref, which may be set at the desired hold voltage VCHOLDfor that output. The base voltage output by the amplifier1102at each transition time depending on the values of C2through Cnand ΔV1through ΔVnat that transition time. The voltage Vrefmay be generated separately by the power supply840or the timing/control logic, and be unaffected by any loading of other power supply outputs during the image data writing process. If the capacitance of the capacitor802is equal to or greater than the maximum possible sum of C1through Cn(which for many interferometric modulator display array implementaitons will be less than 2 μF, then the operational amplifier1102can be driven with the VSHand VSLpower supply outputs, since the maximum required base voltage swing will be the same as the maximum transition on the column electrodes, and in most cases will be less because not all column electrodes will undergo a transition, not all display elements will be actuated.

FIG. 12is a diagram of another implementation of the active transient compensation circuit1002ofFIG. 10. In this implementation, the base voltage for each capacitor802is digitally controlled by the timing/control logic860. In this implementation, the timing/control logic860computes the required base voltage adjustment that will compensate for the next transition of segment voltages in preparation for writing the next row of data. To compute this adjustment, the timing/control logic860determines the capacitance between the first column electrode and all the row electrodes that the hold voltage output is connected to. This is illustrated as C1inFIG. 12, as described above with reference toFIG. 11. This determination will depend on the actuation state of all the display elements between the first column electrode and the row electrodes the hold voltage output is connected to because the capacitance of the display elements depends on actuation state. The timing/control logic860may store this information as it writes data to the display array, so it can know what these states are to accurately compute this capacitance. This is repeated for each column electrode of the array, shown as C2through CninFIG. 12. The timing/control logic860may then determine the segment voltage transition that will occur at each column electrode during the next transition time. It knows this information because it knows the current state of the multiplexers850ofFIG. 10, and it also knows the state it is going to put them in for writing the next line. The base voltage adjustment may be computed with the following formula (where Cois the value of capacitor802, and the index i runs from column electrode 1 to the last column electrode n of the array):

The timing/control logic860adjusts its digital output to the digital to analog converter1204by the amount determined by this formula, which drives a buffer amplifier1206to set the base voltage on the capacitor802. In some implementations, the buffer amplifier1206may be replaced with a hysteretic buck converter, with the output of the digital to analog converter1204providing the reference voltage controlling the level of the buck converter output. This may be a more energy efficient way of driving the second side of capacitor802.

With the implementation ofFIG. 12, the active circuit1002may control the timing of base voltage adjustments as well. For example, base voltage adjustments may be made by the timing/control logic806simultaneously with the application of column electrode transitions. In one aspect, applying the pulse at the time voltage transitions occur on the column electrodes may reduce the feedthrough pulse on the display elements at far ends of the row electrodes.

FIG. 13is a plot1300showing modeled voltage waveforms when driving an array of display elements according to the implementation shown inFIG. 12. The plot1300shows voltage transients on a row electrode under the same conditions asFIG. 9. Base voltage1310transitions in opposite polarity to the column electrode transitions1308. For this model, as with the model ofFIG. 9, all of the column electrodes of the array are transitioned in the same direction as shown by waveform1308. In this model, the capacitor802is slightly larger than the capacitive coupling between the rows and the columns, so the base voltage adjustments are smaller than the column electrode transitions. Transients in the waveforms1302and1306are reduced with respect toFIG. 9, and the capacitor802may still be much smaller.

FIG. 14is a flowchart of an example of a method1600for operating a display apparatus while maintaining voltage stability. The method1600ofFIG. 14may be used in conjunction with the implementation described above with reference toFIGS. 10-12. At block1602a power supply output is connected to at least one row electrode of a display array. The power supply output may, for example, nominally supply a voltage of VCHOLD. In one implementation, a row driver circuit applies the first voltage to a set of row electrodes. At block1604, a voltage is modified on at least one column electrode of the display array. The voltage modification on the at least one column electrode may correspond to a transition from VSHto VSLor vice versa. In one implementation, a column driver circuit modifies the voltage(s) on the at least one column electrode. At block1606, a voltage is applied to a first side of a capacitor having a second side coupled to the power supply output. The voltage is applied in response to the modification of the voltage(s) on the at least one column electrode. In one implementation, an active circuit applies the voltage to the first side of the capacitor. The voltage applied to the first side of the capacitor may depend on the polarities and magnitudes of the voltage modifications on the at least one column electrode, on the capacitive coupling between the at least one column electrode and the at least one row electrode, and on the capacitance of the capacitor.

FIGS. 15A and 15Bare system block diagrams illustrating a display device40that includes a plurality of IMOD display elements. The display device40can be, for example, a smart phone, a cellular or mobile telephone. However, the same components of the display device40or slight variations thereof are also illustrative of various types of display devices such as televisions, computers, tablets, e-readers, hand-held devices and portable media devices.

The display device40includes a housing41, a display30, an antenna43, a speaker45, an input device48and a microphone46. The housing41can be formed from any of a variety of manufacturing processes, including injection molding, and vacuum forming. In addition, the housing41may be made from any of a variety of materials, including, but not limited to: plastic, metal, glass, rubber and ceramic, or a combination thereof. The housing41can include removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.

The display30may be any of a variety of displays, including a bi-stable or analog display, as described herein. The display30also can be configured to include a flat-panel display, such as plasma, EL, OLED, STN LCD, or TFT LCD, or a non-flat-panel display, such as a CRT or other tube device. In addition, the display30can include an IMOD-based display, as described herein.

The components of the display device40are schematically illustrated inFIG. 15A. The display device40includes a housing41and can include additional components at least partially enclosed therein. For example, the display device40includes a network interface27that includes an antenna43which can be coupled to a transceiver47. The network interface27may be a source for image data that could be displayed on the display device40. Accordingly, the network interface27is one example of an image source module, but the processor21and the input device48also may serve as an image source module. The transceiver47is connected to a processor21, which is connected to conditioning hardware52. The conditioning hardware52may be configured to condition a signal (such as filter or otherwise manipulate a signal). The conditioning hardware52can be connected to a speaker45and a microphone46. The processor21also can be connected to an input device48and a driver controller29. The driver controller29can be coupled to a frame buffer28, and to an array driver22, which in turn can be coupled to a display array30. One or more elements in the display device40, including elements not specifically depicted inFIG. 17A, can be configured to function as a memory device and be configured to communicate with the processor21. In some implementations, a power supply50can provide power to substantially all components in the particular display device40design.

The network interface27includes the antenna43and the transceiver47so that the display device40can communicate with one or more devices over a network. The network interface27also may have some processing capabilities to relieve, for example, data processing requirements of the processor21. The antenna43can transmit and receive signals. In some implementations, the antenna43transmits and receives RF signals according to the IEEE 16.11 standard, including IEEE 16.11(a), (b), or (g), or the IEEE 802.11 standard, including IEEE 802.11a, b, g, n, and further implementations thereof. In some other implementations, the antenna43transmits and receives RF signals according to the Bluetooth® standard. In the case of a cellular telephone, the antenna43can be designed to receive code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), GSM/General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunked Radio (TETRA), Wideband CDMA (W-CDMA), Evolution Data Optimized (EV-DO), 1xEV-DO, EV-DO Rev A, EV-DO Rev B, High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Evolved High Speed Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals that are used to communicate within a wireless network, such as a system utilizing 3G, 4G or 5G technology. The transceiver47can pre-process the signals received from the antenna43so that they may be received by and further manipulated by the processor21. The transceiver47also can process signals received from the processor21so that they may be transmitted from the display device40via the antenna43.

In some implementations, the transceiver47can be replaced by a receiver. In addition, in some implementations, the network interface27can be replaced by an image source, which can store or generate image data to be sent to the processor21. The processor21can control the overall operation of the display device40. The processor21receives data, such as compressed image data from the network interface27or an image source, and processes the data into raw image data or into a format that can be readily processed into raw image data. The processor21can send the processed data to the driver controller29or to the frame buffer28for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation and gray-scale level.

The processor21can include a microcontroller, CPU, or logic unit to control operation of the display device40. The conditioning hardware52may include amplifiers and filters for transmitting signals to the speaker45, and for receiving, signals from the microphone46. The conditioning hardware52may be discrete components within the display device40, or may be incorporated within the processor21or other components.

The driver controller29can take the raw image data generated by the processor21either directly from the processor21or from the frame buffer28and can re-format the raw image data appropriately for high speed transmission to the array driver22. In some implementations, the driver controller29can re-format the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array30. Then the driver controller29sends the formatted information to the array driver22. Although a driver controller29, such as an LCD controller, is often associated with the system processor21as a stand-alone Integrated Circuit (IC), such controllers may be implemented in many ways. For example, controllers may be embedded in the processor21as hardware, embedded in the processor21as software, or fully integrated in hardware with the array driver22.

The array driver22can receive the formatted information from the driver controller29and can re-format the video data into a parallel set of waveforms that are applied many times per second to the hundreds, and sometimes thousands (or more), of leads coming from the display's x-y matrix of display elements.

In some implementations, the driver controller29, the array driver22, and the display array30are appropriate for any of the types of displays described herein. For example, the driver controller29can be a conventional display controller or a bi-stable display controller (such as an IMOD display element controller). Additionally, the array driver22can be a conventional driver or a bi-stable display driver (such as an IMOD display element driver). Moreover, the display array30can be a conventional display array or a bi-stable display array (such as a display including an array of IMOD display elements). In some implementations, the driver controller29can be integrated with the array driver22. Such an implementation can be useful in highly integrated systems, for example, mobile phones, portable-electronic devices, watches or small-area displays.

In some implementations, the input device48can be configured to allow, for example, a user to control the operation of the display device40. The input device48can include a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a rocker, a touch-sensitive screen, a touch-sensitive screen integrated with the display array30, or a pressure- or heat-sensitive membrane. The microphone46can be configured as an input device for the display device40. In some implementations, voice commands through the microphone46can be used for controlling operations of the display device40.

The power supply50can include a variety of energy storage devices. For example, the power supply50can be a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. In implementations using a rechargeable battery, the rechargeable battery may be chargeable using power coming from, for example, a wall socket or a photovoltaic device or array. Alternatively, the rechargeable battery can be wirelessly chargeable. The power supply50also can be a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell or solar-cell paint. The power supply50also can be configured to receive power from a wall outlet.

In some implementations, control programmability resides in the driver controller29which can be located in several places in the electronic display system. In some other implementations, control programmability resides in the array driver22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.

Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein. Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of, e.g., an IMOD display element as implemented.