SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device includes a first and second channel separation structures extending in a first direction and spaced apart from each other in a second direction, first gate structures spaced apart from each other in the first direction between the first and second channel separation structures and in contact with the first and second channel separation structures, first and second channel patterns including first and second sheet patterns, respectively, spaced apart from each other in a third direction and in contact with the corresponding first and second channel separation structures, first and second source/drain patterns between the first and second channel separation structures, the first source/drain patterns in contact with the first channel patterns and the first channel separation structure, the second source/drain patterns in contact with the second channel patterns and the second channel separation structure, and first gate separation structures between the first and second source/drain patterns.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority from Korean Patent Application No. 10-2023-0084900 filed on Jun. 30, 2023 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. § 119, the contents of which in its entirety are herein incorporated by reference.

BACKGROUND

The present disclosure relates to a semiconductor device and a method of fabricating the same.

As a scaling technique for increasing the density of integrated circuit devices, the concept of a multi-gate transistor has been proposed in which a silicon body in the form of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the silicon body.

The multi-gate transistor takes advantage of its three-dimensional (3D) channel, allowing for easy scaling both up and down. Additionally, the multi-gate transistor offers improved control over the current without the need to increase the gate length. Furthermore, the multi-gate transistor effectively mitigates the short channel effect (SCE), which is the phenomenon where the electric potential of a channel region is affected by the drain voltage.

Meanwhile, with the decrease in the pitch size of semiconductor devices, there is a need for research on methods to reduce capacitance between contacts and secure electrical stability.

SUMMARY

Aspects of the present disclosure provide a semiconductor device capable of improving device performance and device integration.

Aspects of the present disclosure also provide a method of fabricating a semiconductor device capable of improving device performance and device integration.

According to an aspect of the present disclosure, there is provided a semiconductor device comprising a first channel separation structure extending in a first direction, a second channel separation structure spaced apart from the first channel separation structure in a second direction and extending in the first direction, a plurality of first gate structures spaced apart from each other in the first direction between the first and second channel separation structures, the first gate structures being in contact with the first and second channel separation structures and including first gate electrodes and first gate insulating films, first channel patterns including a plurality of first sheet patterns, which are spaced apart from each other in a third direction and are in contact with the first channel separation structure, second channels pattern including a plurality of second sheet patterns, which are spaced apart from each other in the third direction and are in contact with the second channel separation structure, first source/drain patterns between the first and second channel separation structures and in contact with the first channel patterns and the first channel separation structure, second source/drain patterns between the first and second channel separation structures and in contact with the second channel patterns and the second channel separation structure and first gate separation structures between the first source/drain patterns and the second source/drain patterns.

According to another aspect of the present disclosure, there is provided a semiconductor device comprising a first channel separation structure extending in a first direction, a second channel separation structure spaced apart from the first channel separation structure in a second direction and extending in the first direction, a plurality of first gate structures spaced apart from each other in the first direction between the first and second channel separation structures, the first gate structures being in contact with the first and second channel separation structures and including first gate electrodes and first gate insulating films, gate capping patterns on the gate electrodes and in contact with the first and second channel separation structures, gate spacers on sidewalls of the first gate structures, first channel patterns including a plurality of first sheet patterns, which are spaced apart from each other in a third direction and are in contact with the first channel separation structure, second channels pattern including a plurality of second sheet patterns, which are spaced apart from each other in the third direction and are in contact with the second channel separation structure, first source/drain patterns between the first and second channel separation structures and in contact with the first channel patterns, second source/drain patterns between the first and second channel separation structures and in contact with the second channel patterns and first gate separation structures between the first source/drain patterns and the second source/drain patterns, wherein an upper surface of the first channel separation structure is on the same plane as (i.e., coplanar with) an upper surface of the first gate separation structures, and an upper surface of the first channel separation structure is on the same plane as (i.e., coplanar with) an upper surface of the gate capping patterns.

According to still another aspect of the present disclosure, there is provided a semiconductor device comprising a first lower pattern extending in a first direction, a second lower pattern extending in the first direction and spaced apart from the first lower pattern in a second direction, a field insulating film between the first and second lower patterns, a first channel separation structure on the first lower pattern and extending in the first direction, part of the first channel separation structure being in the first lower pattern, a second channel separation structure on the second lower pattern and extending in the first direction, part of the second channel separation structure being in the second lower pattern, a plurality of gate structures spaced apart from each other in the first direction between the first and second channel separation structures and in contact with the first and second channel separation structures, the gate structures including gate electrodes and gate insulating films, first channel patterns between the first channel separation structure and the gate structures and including a plurality of first sheet patterns, which are spaced apart from each other in a third direction and are in contact with the first channel separation structure, second channel patterns between the second channel separation structure and the gate structures and including a plurality of second sheet patterns, which are spaced apart from each other in the third direction and are in contact with the second channel separation structure, first source/drain patterns between the first and second channel separation structures and in contact with the first channel patterns, second source/drain patterns between the first and second channel separation structures and in contact with the second channel patterns and gate separation structures between the first source/drain patterns and the second source/drain patterns that face the first source/drain patterns in the second direction, the gate separation structures being in contact with the field insulating film.

According to still another aspect of the present disclosure, there is provided a method of fabricating a semiconductor device comprising forming first and second mold fin-type patterns, which extend in a first direction and are spaced apart from each other in a second direction, the first mold fin-type pattern including a first lower pattern and a first pre-pattern structure, the second mold fin-type pattern including a second lower pattern and a second pre-pattern structure, and each of the first and second pre-pattern structures including pre-active patterns and pre-sacrificial patterns that are alternately stacked with the pre-active patterns, forming a dummy gate electrode on the first and second mold fin-type patterns, the dummy gate electrode including extension portions, which extend in the second direction, and a connection portion, which extends in the first direction, the extension portions of the dummy gate electrode intersecting the first and second mold fin-type patterns, and the connection portion of the dummy gate electrode connecting the extension portions of the dummy gate electrode between the first and second mold fin-type patterns, forming first and second pre-source/drain recesses in the first and second mold fin-type patterns, respectively, using the dummy gate electrode as a mask, forming first upper pattern structures on the first lower pattern by forming a first channel separation structure, which extends in the first direction, in the first pre-pattern structure, the first channel separation structure dividing the first pre-source/drain recess into two first source/drain recesses, forming second upper pattern structures on the second lower pattern by forming a second channel separation structure, which extends in the first direction, in the second pre-pattern structure, the second channel separation structure dividing the second pre-source/drain recess into two second source/drain recesses and each of the first upper pattern structures and second upper pattern structures including active patterns and sacrificial patterns that are alternately stacked with the active patterns, forming first source/drain patterns, which are in contact with the first upper pattern structures, in the first source/drain recesses, forming second source/drain patterns, which are in contact with the second upper pattern structures, in the second source/drain recesses, forming a gate trench, which exposes the first upper pattern structures and the second upper pattern structures, by removing the dummy gate electrode, the gate trench including gate trench extension portions, which extend in the second direction, and a gate trench connection portion, which connects the gate trench extension portions, forming first sheet patterns, which are in contact with the first source/drain patterns and the first channel separation structure, by removing exposed sacrificial patterns of the first upper pattern structures, forming second sheet patterns, which are in contact with the second source/drain patterns and the second channel separation structure, by removing exposed sacrificial patterns of the second upper pattern structures, forming a pre-gate electrode in the gate trench, the pre-gate electrode including pre-gate electrode extension portions, which intersect the first sheet patterns and the second sheet patterns, and a pre-gate electrode connection portion, which connects the pre-gate electrode extension portions and forming gate electrodes by forming gate separation structures, which separate extension portions of the pre-gate electrode that are adjacent to each other in the first direction.

According to still another aspect of the present disclosure, there is provided a method of fabricating a semiconductor device comprising forming first and second mold fin-type patterns, which extend in a first direction and are spaced apart from each other in a second direction, the first mold fin-type pattern including a first lower pattern and a first pre-pattern structure, the second mold fin-type pattern including a second lower pattern and a second pre-pattern structure, and each of the first and second pre-pattern structures including pre-active patterns and pre-sacrificial patterns that are alternately stacked with the pre-active patterns, forming a plurality of dummy gate electrodes, which intersect the first and second mold fin-type patterns and extend in the second direction, on the first and second mold fin-type patterns, forming gate separation structures, which connect dummy gate electrodes that are adjacent to each other in the first direction, between the first and second mold fin-type patterns, forming first and second pre-source/drain recesses in the first and second mold fin-type patterns, respectively, using the dummy gate electrodes as a mask, forming first upper pattern structures on the first lower pattern by forming a first channel separation structure, which extends in the first direction, in the first pre-pattern structure, the first channel separation structure dividing the first pre-source/drain recess into two first source/drain recesses, forming second upper pattern structures on the second lower pattern by forming a second channel separation structure, which extends in the first direction, in the second pre-pattern structure, the second channel separation structure dividing the second pre-source/drain recess into two second source/drain recesses and each of the first upper pattern structures and second upper pattern structures including active patterns and sacrificial patterns that are alternately stacked with the active patterns, forming first source/drain patterns, which are in contact with the first upper pattern structures, in the first source/drain recesses, forming second source/drain patterns, which are in contact with the second upper pattern structures, in the second source/drain recesses, forming a gate trench, which exposes the first upper pattern structures and the second upper pattern structures, by removing the dummy gate electrodes, forming first sheet patterns, which are in contact with the first source/drain patterns and the first channel separation structure, by removing exposed sacrificial patterns of the first upper pattern structures, forming second sheet patterns, which are in contact with the second source/drain patterns and the second channel separation structure, by removing exposed sacrificial patterns of the second upper pattern structures and forming gate electrodes, which intersect the first sheet patterns and the second sheet patterns, in the gate trench.

It should be noted that the effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will be apparent from the following description.

DETAILED DESCRIPTION

It should be understood that ordinal terms, such as “first,” “second,” “third,” etc., used herein to describe various elements, components, regions, layers, and/or sections are employed for the purpose of distinguishing one element, component, region, layer, or section from another and are not intended to convey a particular order or relation of one element, component, region, layer, or section to another. Therefore, a first element, component, region, layer, or section described below could also be referred to as a second element, component, region, layer, or section, without deviating from the essence and scope of the present disclosure.

Transistors including nanowires or nanosheets are depicted as examples of semiconductor devices according to some embodiments of the present disclosure, but the present disclosure is not limited thereto. The technological principles described herein are also applicable to two-dimensional (2D) material-based field-effect transistors (FETs) and their heterostructures.

Moreover, the semiconductor devices according to some embodiments of the present disclosure may encompass fin-type FETs (FinFETs), tunneling FETs, and three-dimensional (3D) transistors including channel regions featuring fin-shaped patterns. Additionally, the semiconductor devices according to some embodiments of the present disclosure may include other types of transistors, such as bipolar junction transistors, lateral double-diffused metal-oxide semiconductor (LDMOS) transistors, among others.

A semiconductor device according to some embodiments of the present disclosure will hereinafter be described with reference toFIGS.1through12.

FIG.1is a layout (i.e., plan) view of a semiconductor device according to some embodiments of the present disclosure.FIGS.2,3,4,5, and6are cross-sectional views taken along lines A-A, B-B, C-C, D-D, and E-E, respectively, ofFIG.1.FIG.7is a perspective view conceptually depicting the shape of a first sheet pattern ofFIG.2.FIGS.8through12are plan views of region P of the semiconductor device shown inFIG.1.

FIG.1depicts the semiconductor device according to some embodiments of the present disclosure, with the exception of first source/drain contacts180(FIG.2), second source/drain contacts280(FIG.3), third source/drain contacts380(FIG.5), and fourth source/drain contacts480(FIG.5).FIGS.8through12may be plan views taken at a level where the first source/drain contacts180, the second source/drain contacts280, the third source/drain contacts380, and the fourth source/drain contacts480are located.

Referring toFIGS.1through12, the semiconductor device according to some embodiments of the present disclosure may include a first lower pattern BP1, a second lower pattern BP2, a first channel pattern CH1, a second channel pattern CH2, a third channel pattern CH3, a fourth channel pattern CH4, a first channel separation structure CCW1, a second channel separation structure CCW2, a plurality of first gate electrodes120, first source/drain patterns150, second source/drain patterns250, third source/drain patterns350, fourth source/drain patterns450, and first gate separation structures GCS1.

A first substrate100may have first (upper) and second (bottom) surfaces100US and100BS, respectively, which are opposite to each other in a third direction D3perpendicular to the upper surface100US of the substrate100. The first gate electrodes120, the first source/drain patterns150, the second source/drain patterns250, the third source/drain patterns350, the fourth source/drain patterns450, the first channel patterns CH1, the second channel patterns CH2, the third channel patterns CH3, and the fourth channel patterns CH4may be disposed on the first surface100US of the first substrate100, and the first surface100US of the first substrate100may be the upper surface of the first substrate100. The second surface100BS of the first substrate100, which is opposite to the first surface100US of the first substrate100, may be the bottom surface of the first substrate100.

The first substrate100may be formed of or include a semiconductor material. The first substrate100may be a silicon (Si) substrate) or a silicon-on-insulator (SOI) substrate. Alternatively, the first substrate100may include silicon germanium (SiGe), SiGe-on-insulator (SGOI), indium antimonide, lead tellurium compounds, indium arsenic, indium phosphide, gallium arsenic, or gallium antimonide, but the present disclosure is not limited thereto.

The first lower pattern BP1may protrude (i.e., extend) from the first substrate100in the third direction D3. More particularly, the first lower pattern BP1may extend upwardly (i.e., in the third direction D3) from the first surface100US of the first substrate100. The first lower pattern BP1may extend in a first direction D1parallel to the upper surface100US of the substrate100.

The second lower pattern BP2may protrude from the first substrate100in the third direction D3. More particularly, the second lower pattern BP2may extend upwardly (in the third direction D3) from the first surface100US of the first substrate100. The second lower pattern BP2may extend in the first direction D1. The second lower pattern BP2may be spaced apart from the first lower pattern BP1in a second direction D2parallel to the upper surface100US of the substrate and intersecting the first direction D1.

For example, the third direction D3may correspond to the vertical direction of the first substrate100. The first and second directions D1and D2may correspond to the horizontal direction and are perpendicular to the third direction D3.

The first and second lower patterns BP1and BP2may be separated by a fin trench FT, which extends in the first direction D1. For example, the first surface100US of the first substrate100may correspond to the bottom surface of the fin trench FT. The first lower pattern BP1may have sidewalls BP1_SW, which extend in the first direction D1, and the second lower pattern BP2may have sidewalls BP2_SW, which extend in the first direction D1. The sidewalls BP1_SW of the first lower pattern BP1and the sidewalls BP2_SW of the second lower pattern BP2may be defined by the fin trench FT.

For example, the first lower pattern BP1may be positioned in a p-type metal-oxide semiconductor (PMOS) region, and the second lower pattern BP2may be positioned in an n-type metal-oxide semiconductor (NMOS) region.

Each of the first and second lower patterns BP1and BP2may be formed by partially etching the first substrate100or may include an epitaxial layer grown from the first substrate100. The first and second lower patterns BP1and BP2may include an element semiconductor material, such as Si or germanium (Ge). The first and second lower patterns BP1and BP2may also include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

The group IV-IV compound semiconductor may be a binary or ternary compound containing at least two of carbon (C), Si, Ge, and tin (Sn), or a compound formed by doping the binary or ternary compound with a group IV element.

The group III-V compound semiconductor may be a binary, ternary, or quaternary compound formed by combining at least one group III element, such as aluminum Al, gallium (Ga), and indium (In), with a group V element, such as phosphorus (P), arsenic (As), or antimony (Sb).

A field insulating film105may be disposed on the first substrate100. For example, the field insulating film105may be disposed on the first surface100US of the first substrate100. The field insulating film105may at least partially fill the fin trench FT, which separates the first and second lower patterns BP1and BP2. The term “fill” (or “filling,” “filled,” or like terms), as may be used herein, is intended to refer broadly to either completely filling a defined space (e.g., fin trench FT) or partially filling the defined space; that is, the defined space need not be entirely filled but may, for example, be partially filled or have voids or other spaces throughout. The field insulating film105is not disposed on an upper surface BP1_US of the first lower pattern BP1and an upper surface BP2_US of the second lower pattern BP2.

The field insulating film105may have an upper surface105US and a bottom surface105BS, which are opposite to each other in the third direction D3. The bottom surface105BS of the field insulating film105may face the first substrate100.

For example, the field insulating film105may generally cover the sidewalls BP1_SW of the first lower pattern BP1and the sidewalls BP2_SW of the second lower pattern BP2. The term “cover” (or “covering, or other like terms), as may be used herein, is intended to broadly refer to a material, layer or structure being on or over another material, layer or structure, but does not require the material, layer or structure to entirely cover the other material, layer or structure. Thus, for example, a material or layer having openings or holes therein may still be considered to cover another material or layer. In another example, not explicitly shown, the field insulating film105may cover parts of the sidewalls BP1_SW of the first lower pattern BP1and parts of the sidewalls BP2_SW of the second lower pattern BP2. In this example, parts of the first and second lower patterns BP1and BP2may protrude beyond (i.e., extend upwardly from) the upper surface105US of the field insulating film105in the third direction D3.

The upper surface105US of the field insulating film105is illustrated as being flat (i.e., planar), but the present disclosure is not limited thereto. The field insulating film105may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. The field insulating film105is illustrated as being a single film, but the present disclosure is not limited thereto.

A plurality of first channel patterns CH1may be disposed on the first lower pattern BP1. The first channel patterns CH1may overlap with the first lower pattern BP1in the third direction D3. The term “overlap” (or “overlapping,” or like terms), as used herein, is intended to broadly refer to a first element that intersects with at least a portion of a second element in the vertical direction (i.e., third direction D3), but does not require that the first and second elements be completely aligned with one another in a horizontal plane (i.e., in the first direction D1and/or second direction D2). The first channel patterns CH1may be aligned with one another in the first direction D1.

A plurality of second channel patterns CH2may be disposed on the second lower pattern BP2. The second channel patterns CH2may overlap with the second lower pattern BP2in the third direction D3. The second channel patterns CH2may be aligned with one another in the first direction D1.

A plurality of third channel patterns CH3may be disposed on the first lower pattern BP1. The third channel patterns CH3may overlap with the first lower pattern BP1in the third direction D3. The third channel patterns CH3may be aligned with one another in the first direction D1. The third channel patterns CH3may be disposed to correspond to the first channel patterns CH1. The third channel patterns CH3and their corresponding first channel patterns CH1may be spaced apart from each other in the second direction D2.

A plurality of fourth channel patterns CH4may be disposed on the second lower pattern BP2. The fourth channel patterns CH4may overlap with the second lower pattern BP2in the third direction D3. The fourth channel patterns CH4may be aligned with one another in the first direction D1. The fourth channel patterns CH4may be disposed to correspond to the second channel patterns CH2. The fourth channel patterns CH4and their corresponding second channel patterns CH2may be spaced apart from each other in the second direction D2.

For example, the first channel patterns CH1and the third channel patterns CH3may be included in PMOS channel regions, and the second channel patterns CH2and the fourth channel patterns CH4may be included in NMOS channel regions.

Each of the first channel patterns CH1, second channel patterns CH2, third channel patterns CH3, and fourth channel patterns CH4may include a plurality of sheet patterns that are spaced apart from one another in the third direction D3. Each of the first channel patterns CH1, second channel patterns CH2, third channel patterns CH3, and fourth channel patterns CH4is illustrated as including three sheet patterns, but the present disclosure is not limited thereto.

Each of the first channel patterns CH1may include a plurality of first sheet patterns NS1. The first sheet patterns NS1may be disposed on the upper surface BP1_US of the first lower pattern BP1. The first sheet patterns NS1may be arranged on the first lower pattern BP1in the third direction D3. The first sheet patterns NS1may be spaced apart from one another in the third direction D3. Each of the first sheet patterns NS1may have an upper surface NS1_US and a bottom surface NS1_BS, which are opposite to each other in the third direction D3.

Each of the second channel patterns CH2may include a plurality of second sheet patterns NS2. The second sheet patterns NS2may be disposed on the upper surface BP2_US of the second lower pattern BP2. The second sheet patterns NS2may be arranged on the second lower pattern BP2in the third direction D3. The second sheet patterns NS2may be spaced apart from one another in the third direction D3. Each of the second sheet patterns NS2may have an upper surface NS2_US and a bottom surface NS2_BS, which are opposite to each other in the third direction D3.

Each of the third channel patterns CH3may include a plurality of third sheet patterns NS3. The third sheet patterns NS3may be disposed on the upper surface BP1_US of the first lower pattern BP1. The third sheet patterns NS3may be spaced apart from one another in the third direction D3. Each of the fourth channel patterns CH4may include a plurality of fourth sheet patterns NS4. A plurality of fourth sheet patterns NS4may be disposed on the upper surface BP2_US of the second lower pattern BP2. Each of the fourth sheet patterns NS4may be spaced apart from one another in the third direction D3.

Each of the first sheet patterns NS1may have first sidewalls NS1_SW1, which are opposite to each other in the first direction D1, and second sidewalls NS1_SW2, which are opposite to each other in the second direction D2. The upper surface NS1_US and the bottom surface NS1_BS of each of the first sheet patterns NS1may be connected by the first sidewalls NS1_SW1and the second sidewalls NS1_SW2of the corresponding first sheet pattern NS1. The first sidewalls NS1_SW1of each of the first sheet patterns NS1may be connected to and in contact with their corresponding first source/drain patterns150. The above description of the first sheet patterns NS1may be directly applicable to the second sheet patterns NS2, the third sheet patterns NS3, and the fourth sheet patterns NS4.

Sheet patterns (NS1, NS2, NS3, and NS4) may include one of an element semiconductor material (e.g., Si or Ge), a group IV-IV compound semiconductor, and a group III-V compound semiconductor. The first sheet patterns NS1and the third sheet patterns NS3may include the same material as the first lower pattern BP1or a different material from the first lower pattern BP1. The second sheet patterns NS2and the fourth sheet patterns NS4may include the same material as the second lower pattern BP2or a different material from the second lower pattern BP2.

The first and second lower patterns BP1and BP2may be silicon (Si) lower patterns containing Si. The sheet patterns (NS1, NS2, NS3, and NS4) may be Si sheet patterns containing Si.

The channel patterns (CH1, CH2, CH3, and CH4) will hereinafter be described, with a particular focus on the first channel patterns CH1and the second channel patterns CH2as illustrative examples.

The first channel separation structure CCW1may be disposed on the first lower pattern BP1. The first channel separation structure CCW1may extend in the first direction D1. The first channel separation structure CCW1may include sidewalls CCW1_SW, which extend in the first direction D1.

The first channel separation structure CCW1separates the first channel patterns CH1and the third channel patterns CH3. The first channel separation structure CCW1may not separate the first lower pattern BP1. Part of the first channel separation structure CCW1may be disposed partially in the first lower pattern BP1. The first lower pattern BP1may cover parts of the sidewalls CCW1_SW of the first channel separation structure CCW1.

The first channel separation structure CCW1may be in contact with the first lower pattern BP1. The first channel patterns CH1and the third channel patterns CH3may be in contact with the first channel separation structure CCW1(e.g., the sidewalls CCW1_SW of the first channel separation structure CCW1). A plurality of first sheet patterns NS1and a plurality of third sheet patterns NS3may be in contact with the first channel separation structure CCW1. The first sheet patterns NS1and the third sheet patterns NS3may extend from the sidewalls CCW1_SW of the first channel separation structure CCW1in the second direction D2. For example, one of the second sidewalls NS1_SW2of each of the first sheet patterns NS1may be in contact with one of the sidewalls CCW1_SW of the first channel separation structure CCW1, and one of the second sidewalls of each of the third sheet patterns NS3may be in contact with the other sidewall CCW1_SW of the first channel separation structure CCW1.

Similarly, the second channel separation structure CCW2may be disposed on the second lower pattern BP2. The second channel separation structure CCW2may extend in the first direction D1. The second channel separation structure CCW2may include sidewalls CCW2_SW, which extend in the first direction D1. The second channel separation structure CCW2may be spaced apart from the first channel separation structure CCW1in the second direction D2. The sidewalls CCW2_SW of the second channel separation structure CCW2may face the sidewalls CCW1_SW of the first channel separation structure CCW1.

The second channel separation structure CCW2separates the second channel patterns CH2and the fourth channel patterns CH4. The second channel separation structure CCW2may not separate the second lower pattern BP2. Part of the second channel separation structure CCW2may be disposed in the second lower pattern BP2. The second lower pattern BP2may cover parts of the sidewalls CCW2_SW of the second channel separation structure CCW2.

The second channel separation structure CCW2may be in contact with the second lower pattern BP2. The second channel patterns CH2and the fourth channel patterns CH4may be in contact with the second channel separation structure CCW2. A plurality of second sheet patterns NS2and a plurality of fourth sheet patterns NS4may be in contact with the second channel separation structure CCW2. The second sheet patterns NS2and the fourth sheet patterns NS4may protrude from the sidewalls CCW2_SW of the second channel separation structure CCW2in the second direction D2. For example, one of the second sidewalls NS2_SW2of each of the second sheet patterns NS2may be in contact with one of the sidewalls CCW2_SW of the second channel separation structure CCW2, and one of the second sidewalls of each of the fourth sheet patterns NS4may be in contact with the other sidewall CCW2_SW of the second channel separation structure CCW2.

The first channel patterns CH1and the second channel patterns CH2may be disposed between the first and second channel separation structures CCW1and CCW2, which are adjacent to each other in the second direction D2.

The first and second channel separation structures CCW1and CCW2may include an insulating material. The first and second channel separation structures CCW1and CCW2may include at least one of, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and a combination thereof, but the present disclosure is not limited thereto. The first and second channel separation structures CCW1and CCW2are illustrated as being single films, but the present disclosure is not limited thereto. Since the first and second channel separation structures CCW1and CCW2are formed at the same time, the first and second channel separation structures CCW1and CCW2may include the same material.

A height H11from the bottom surface105BS of the field insulating film105to the upper surface BP1_US of the first lower pattern BP1is greater than a height H21from the bottom surface105BS of the field insulating film105to a lowermost part of the first channel separation structure CCW1. The upper surface105US of the field insulating film105may be higher than the lowermost part of the first channel separation structure CCW1with respect to the first surface100US of the first substrate100.

A plurality of first gate structures GS1may be disposed on the first surface100US of the first substrate100. The first gate structures GS1may extend in the second direction D2. The first gate structures GS1may be adjacent to one another in the first direction D1.

The first gate structures GS1may be disposed between the first and second channel separation structures CCW1and CCW2, which are adjacent to each other in the second direction D2. The first gate structures GS1may be in contact with the first and second channel separation structures CCW1and CCW2.

The first gate structures GS1may be disposed on the first and second lower patterns BP1and BP2. The first gate structures GS1may intersect the first and second lower patterns BP1and BP2. The first gate structures GS1may overlap with parts of the first and second lower patterns BP1and BP2in the third direction D3.

The first gate structures GS1may be in contact with the upper surface105US of the field insulating film105. The first gate structures GS1may be in contact with the upper surface BP1_US and BP2_US of the first and second lower patterns BP1and BP2.

The first gate structures GS1may include the first gate electrodes120and first gate insulating films130. The first gate insulating films130of the first gate structures GS1may be in contact with the upper surface105US of the field insulating film105and the upper surface BP1_US and BP2_US of the first and second lower patterns BP1and BP2, respectively. The first gate insulating films130of the first gate structures GS1may be in contact with the sidewalls CCW1_SW of the first channel separation structure CCW1and the sidewalls CCW2_SW of the second channel separation structure CCW2.

The first channel patterns CH1may be disposed between the first gate structure GS1and the first channel separation structure CCW1. The first sheet patterns NS1may be disposed between the first gate structures GS1and the first channel separation structure CCW1. As the first sheet patterns NS1are in contact with the first channel separation structure CCW1, the first gate structures GS1may not surround the first sheet patterns NS1in a cross-sectional view.

The second channel patterns CH2may be disposed between the first gate structure GS1and the second channel separation structure CCW2. The second sheet patterns NS2may be disposed between the first gate structures GS1and the second channel separation structure CCW2. As the second sheet patterns NS2are in contact with the second channel separation structure CCW2, the first gate structures GS1may not surround the second sheet patterns NS2in a cross-sectional view.

Each of the first gate structures GS1may include first inner gate structures INT_GS1. The first inner gate structures INT_GS1may be disposed between the first lower pattern BP1and their corresponding first sheet patterns NS1and between the corresponding first sheet patterns NS1, which are adjacent to one another in the third direction D3. The first inner gate structures INT_GS1may be disposed between the second lower pattern BP2and their corresponding second sheet patterns NS2and between the corresponding second sheet patterns NS2, which are adjacent to one another in the third direction D3.

The first inner gate structures INT_GS1are in contact with the upper surface BP1_US of the first lower pattern BP1and the upper surface NS1_US and the bottom surface NS1_BS of the corresponding first sheet patterns NS1. The first inner gate structures INT_GS1may be in contact with the upper surface BP2_US of the second lower pattern BP2and the upper surface NS2_US and the bottom surface NS2_BS of the corresponding second sheet patterns NS2.

A plurality of first gate electrodes120may be disposed between the first and second channel separation structures CCW1and CCW2, respectively. As first gate insulating films130are disposed between the first gate electrodes120and the first channel separation structure CCW1and between the first gate electrodes120and the second channel separation structure CCW2, the first gate electrodes120may not be in contact with the first and second channel separation structures CCW1and CCW2. The term “contact,” as may be used herein, is intended to broadly refer to electrical and/or physical contact between two or more layers, structures or other elements.

The first gate electrodes120may be disposed on the first and second lower patterns BP1and BP2. The first gate electrodes120may overlap with parts of the first and second lower patterns BP1and BP2in the third direction D3.

For example, the first gate electrodes120may include first, second, and third connection gate electrodes120_1,120_2, and120_3, which are arranged in the first direction D1. The second connection gate electrode120_2may be disposed between the first and third connection gate electrodes120_1and120_3.

Upper surface120US of the first gate electrodes120are illustrated inFIGS.2and3as being concave surface, but the present disclosure is not limited thereto. Alternatively, the upper surface120US of the first gate electrodes120may be flat.

The first gate electrodes120may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The first gate electrodes120may include at least one of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (NiPt), niobium (Nb), niobium Nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and a combination thereof, but the present disclosure is not limited thereto. Here, the conductive metal oxide and the conductive metal oxynitride may encompass oxidized forms of the above-mentioned materials, but the present disclosure is not limited thereto.

The first gate insulating films130may extend along the upper surface105US of the field insulating film105and the upper surface BP1_US and BP2_US of the first and second lower patterns BP1and BP2. The first gate insulating films130may extend along parts of the sidewalls CCW1_SW of the first channel separation structure CCW1and parts of the sidewalls CCW2_SW of the second channel separation structure CCW2. In a cross-sectional view, the first gate insulating films130may be disposed along parts of the perimeters (i.e., periphery) of the first sheet patterns NS1. The first gate insulating films130may be disposed along parts of the perimeters of the second sheet patterns NS2. The first gate electrodes120are disposed on the first gate insulating films130. The first gate insulating films130are disposed between the first gate electrodes120and the first sheet patterns NS1and between the first gate electrodes120and the second sheet patterns NS2. The first gate insulating films130included in the second inner gate structures INS_GS1may be in contact with the first source/drain patterns150and the second source/drain patterns250.

The first gate insulating films130may include silicon oxide, silicon oxynitride, silicon nitride, or a high-k material with a greater dielectric constant than silicon oxide. The high-k material may include at least one of, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

The first gate insulating films130are illustrated as being single films, but the present disclosure is not limited thereto. Alternatively, the first gate insulating films130may include stacks of multiple films. The first gate insulating films130may include interfacial layers, which are disposed between the first channel patterns CH1and the first gate electrodes120and between the second channel patterns CH2and the first gate electrodes120, and high-k (i.e., high-dielectric constant) insulating films. For example, the interfacial films may not be formed along the profile of the upper surface105US of the field insulating film105.

The semiconductor device according to some embodiments of the present disclosure may include a negative capacitance (NC) field-effect transistor (FET) using a negative capacitor. For example, each of the first gate insulating films130may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and have positive capacitance, the total capacitance of the two or more capacitors may be lower than the capacitance of each of the two or more capacitors individually. On the contrary, if at least one of the two or more capacitors has negative capacitance, the total capacitance of the two or more capacitors may have a positive value and may be greater than the absolute value of the capacitance of each of the two or more capacitors.

If the ferroelectric material film having a negative capacitance and the paraelectric material film having a positive capacitance are connected in series, the total capacitance of the ferroelectric material film and the paraelectric material film may increase. Accordingly, a transistor having the ferroelectric material film can have a sub-threshold swing (SS) of less than 60 mV/decade at room temperature.

The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. For example, the hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). In another example, the hafnium zirconium oxide may be a compound of hafnium (Hf), Zr, and oxygen (O).

The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of Al, Ti, Nb, lanthanum (La), yttrium (Y), magnesium (Mg), silicon, calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium, scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant may vary depending on the type of material of the ferroelectric material film.

If the ferroelectric material film includes hafnium oxide, the dopant of the ferroelectric material film may include at least one of, for example, Gd, Si, Zr, Al, and Y.

If the dopant of the ferroelectric material film is Al, the ferroelectric material film may include about 3 atomic percent (at %) to about 8 at % of Al. Here, the ratio of the dopant in the ferroelectric material film may refer to the ratio of the sum of the amounts of Hf and Al to the amount of Al in the ferroelectric material film.

If the dopant of the ferroelectric material film is Si, the ferroelectric material film may include about 2 at % to about 10 at % of Si. If the dopant of the ferroelectric material film is Y, the ferroelectric material film may include about 2 at % to about 10 at % of Y. If the dopant of the ferroelectric material film is Gd, the ferroelectric material film may include about 1 at % to about 7 at % of Gd. If the dopant of the ferroelectric material film is Zr, the ferroelectric material film may include about 50 at % to about 80 at % of Zr.

The paraelectric material film may include paraelectric properties. The paraelectric material film may include at least one of, for example, silicon oxide and a high-k metal oxide. The high-k metal oxide may include at least one of, for example, hafnium oxide, zirconium oxide, and aluminum oxide, but the present disclosure is not limited thereto.

The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, if the ferroelectric material film and the paraelectric material film include hafnium oxide, the hafnium oxide included in the ferroelectric material film may have a different crystalline structure from the hafnium oxide included in the paraelectric material film.

The ferroelectric material film may be thick enough to exhibit ferroelectric properties. The ferroelectric material film may have a thickness of, for example, about 0.5 nm to about 10 nm, but the present disclosure is not limited thereto. A critical thickness that can exhibit ferroelectric properties may vary depending on the type of ferroelectric material, and thus, the thickness of the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

For example, each of the first gate insulating films130may include one ferroelectric material film. In another example, each of the first gate insulating films130may include a plurality of ferroelectric material films that are spaced apart from one another. Each of the first gate insulating films130may have a structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

First gate spacers140may be disposed on the sidewalls of the first gate structures GS1. For example, the first gate spacers140may include first portions that extend in the second direction D2. The first gate spacers140may include second portions that extend in the first direction D1, depending on the locations of the first gate separation structures GCS1. The first portions of the first gate spacers140may be directly connected to the second portions of the first gate spacers140. The first portions of the first gate spacers140may be disposed on the sidewalls of the first gate structures GS1that extend in the second direction D2.

The first gate spacers140may not be disposed between the first lower pattern BP1and their corresponding first sheet patterns NS1and between the corresponding first sheet patterns NS1, which are adjacent to one another in the third direction D3. The first gate spacers140may not be disposed between the second lower pattern BP2and their corresponding second sheet patterns NS2and between the corresponding second sheet patterns NS2, which are adjacent to one another in the third direction D3.

The details regarding the shape of the first gate spacers140will be further described in the description section pertaining to the first gate separation structures GCS1.

The first gate spacers140may include at least one of, for example, SiN, SiON, SiO2, SiOCN, SiBN, SiOBN, SiOC, and a combination thereof. The first gate spacers140are illustrated as being single films, but the present disclosure is not limited thereto.

First gate capping patterns145may be disposed on the first gate structures GS1. The first gate capping patterns145may be disposed on the upper surface120US of the first gate electrodes120.

The first gate capping patterns145may be disposed on the upper surface of the first gate spacers140. The first gate capping patterns145may cover the upper surface of the first gate spacers140. Although not explicitly depicted, in some embodiments the first gate capping patterns145may be disposed between the first gate spacers140. In this case, an upper surface145US of the first gate capping patterns145may be disposed on the same plane as (i.e., coplanar with) the upper surface of the first gate spacers140.

The first gate capping patterns145may be disposed between the first and second channel separation structures CCW1and CCW2. The first gate capping patterns145may be in contact with the sidewalls CCW1_SW of the first channel separation structure CCW1and the sidewalls CCW2_SW of the second channel separation structure CCW2.

The height from the bottom surface105BS of the field insulating film105to the upper surface145US of the first gate capping patterns145may be the same as a height “H21+H22” from the bottom surface105BS of the field insulating film105to an upper surface CCW1_US of the first channel separation structure CCW1. For example, the upper surface145US of the first gate capping patterns145may be disposed on the same plane as the upper surface CCW1_US of the first channel separation structure CCW1. For example, the upper surface145US of the first gate capping patterns145may be disposed on the same plane as the upper surface CCW2_US of the second channel separation structure CCW2.

The first gate capping patterns145may include at least one of, SiN, SiON, SiCN, SiOCN, and a combination thereof.

Although not explicitly depicted, in some embodiments the first gate capping patterns145may not be disposed on the first gate structures GS1. In this case, the height from the bottom surface105BS of the field insulating film105to the upper surface of the first gate structures GS1may be the same as the height from the bottom surface105BS of the field insulating film105to the upper surface CCW1_US of the first channel separation structure CCW1, i.e., H21+H22. The upper surface of the first gate structures GS1may include the upper surface120US of the first gate electrodes120.

The first source/drain patterns150may be disposed on the first lower pattern BP1. The first source/drain patterns150may be disposed on the side surface (i.e., sidewalls) of the first gate electrodes120. The first source/drain patterns150may be connected to the first channel patterns CH1. The first source/drain patterns150may be in contact with the first channel patterns CH1. The first source/drain patterns150may be in contact with the first sheet patterns NS1. For example, the first source/drain patterns150may be in contact with the first inner gate structures INT_GS1.

The second source/drain patterns250may be disposed on the second lower pattern BP2. The second source/drain patterns250may be disposed on the side surface of the first gate electrodes120. The second source/drain patterns250may be connected to the second channel patterns CH2. The second source/drain patterns250may be in contact with the second channel patterns CH2. The second source/drain patterns250may be in contact with the second sheet patterns NS2. For example, the second source/drain patterns250may be in contact with the first inner gate structures INT_GS1.

The third source/drain patterns350may be disposed on the first lower pattern BP1. The first channel separation structure CCW1may be disposed between the first source/drain patterns150and the third source/drain patterns350. Although not specifically illustrated, the third source/drain patterns350may be connected to the third channel patterns CH3. The third source/drain patterns350may be in contact with the third channel patterns CH3.

The fourth source/drain patterns450may be disposed on the second lower pattern BP2. The second channel separation structure CCW2may be disposed between the second source/drain patterns250and the fourth source/drain patterns450. Although not specifically illustrated, the fourth source/drain patterns450may be connected to the fourth channel patterns CH4. The fourth source/drain patterns450may be in contact with the fourth channel patterns CH4.

The first source/drain patterns150and the second source/drain patterns250may be disposed between the first and second channel separation structures CCW1and CCW2. The first source/drain patterns150and the second source/drain patterns250may be spaced apart from one another in the second direction D2.

The first source/drain patterns150may be in contact with the first channel separation structure CCW1. For example, the first source/drain patterns150may be in contact with the sidewalls CCW1_SW of the first channel separation structure CCW1. The second source/drain patterns250may be in contact with the second channel separation structure CCW2. For example, the second source/drain patterns250may be in contact with the sidewalls CCW2_SW of the second channel separation structure CCW2.

The first source/drain patterns150may be in contact with the first sheet patterns NS1and the first lower pattern BP1. The second source/drain patterns250may be in contact with the second sheet patterns NS2and the second lower pattern BP2.

The third source/drain patterns350may be in contact with the first channel separation structure CCW1. The fourth source/drain patterns450may be in contact with the second channel separation structure CCW2.

The first source/drain patterns150, the second source/drain patterns250, the third source/drain patterns350, and the fourth source/drain patterns450may be disposed on the first surface100US of the first substrate100. The first source/drain patterns150may be included in the sources/drains of transistors using the first sheet patterns NS1as channel regions. The second source/drain patterns250may be included in the sources/drains of transistors using the second sheet patterns NS2as channel regions. The third source/drain patterns350may be included in the sources/drains of transistors using the third sheet patterns NS3as channel regions. The fourth source/drain patterns450may be included in the sources/drains of transistors using the fourth sheet patterns NS4as channel regions.

The first source/drain patterns150, the second source/drain patterns250, the third source/drain patterns350, and the fourth source/drain patterns450may include epitaxial patterns. The first source/drain patterns150, the second source/drain patterns250, the third source/drain patterns350, and the fourth source/drain patterns450may include a semiconductor material.

The first source/drain patterns150and the third source/drain patterns350may include a p-type dopant. The p-type dopant may include at least one of boron (B) and gallium (Ga), but the present disclosure is not limited thereto. The second source/drain patterns250and the fourth source/drain patterns450may include an n-type dopant. The n-type dopant may include at least one of P, As, Sb, and bismuth (Bi), but the present disclosure is not limited thereto.

Source/drain etch stopper films185may extend along the outer sidewalls of the first gate spacers140, the sidewalls of the first source/drain patterns150, the sidewalls of the second source/drain patterns250, the sidewalls of the third source/drain patterns350, and the sidewalls of the fourth source/drain patterns450. The source/drain etch stopper films185may extend along the upper surface105US of the field insulating film105.

Parts of the source/drain etch stopper films185may extend along the sidewalls CCW1_SW of the first channel separation structure CCW1and the sidewalls CCW2_SW of the second channel separation structure CCW2. The source/drain etch stopper films185on the sidewalls CCW1_SW of the first channel separation structure CCW1and the sidewalls CCW2_SW of the second channel separation structure CCW2may potentially be remaining portions that are not removed during the formation of the first source/drain contacts180, the second source/drain contacts280, the third source/drain contacts380, and the fourth source/drain contacts480.

The source/drain etch stopper films185may not extend along the sidewalls of the first gate capping patterns145. Although not explicitly depicted, in some embodiments the source/drain etch stopper films185may extend along the sidewalls of the first gate capping patterns145.

Upper interlayer insulating films190may be disposed on the first surface100US of the first substrate100. The upper interlayer insulating films190may be disposed on the source/drain etch stopper films185. The upper interlayer insulating films190may be disposed on the first source/drain patterns150, the second source/drain patterns250, the third source/drain patterns350, and the fourth source/drain patterns450.

The upper interlayer insulating films190may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k (low-dielectric constant) material. The low-k material may have a dielectric constant less than 3.9, which is the dielectric constant of silicon oxide.

The first gate separation structures GCS1may be disposed on the first surface100US of the first substrate100. The first gate separation structures GCS1may be disposed on the field insulating film105. Parts of the first gate separation structures GCS1may be disposed in the upper interlayer insulating film190.

The first gate separation structures GCS1may be in contact with the field insulating film105. Parts of the first gate separation structures GCS1may be recessed into the field insulating film105.

The first gate separation structures GCS1may be disposed between the first and second channel separation structures CCW1and CCW2. The first gate separation structure CGS1may be disposed between the first source/drain patterns150and the second source/drain patterns250. For example, the first gate separation structures GCS1may be disposed between the first source/drain patterns150and the second source/drain patterns250that face the first source/drain patterns150in the second direction D2. For example, the first gate separation structures GCS1may not be in contact with the first source/drain patterns150and the second source/drain patterns250.

The first gate separation structures GCS1may be disposed between first gate structures GS1that are adjacent to one another in the first direction D1. The first gate separation structures GCS1separate the first gate structures GS1. For example, the first gate separation structures GCS1may separate the first gate structures GS1that are adjacent to one another in the first direction D1.

The first gate separation structures GCS1may be in contact with the first gate structures GS1. For example, the first gate separation structures GCS1may be in contact with the first gate electrodes120and the first gate insulating films130.

Referring toFIG.6, each of the first gate separation structure GCS1may include sidewalls that are opposite to each other in the first direction D1. The first gate insulating films130may not extend along the sidewalls of the first gate separation structures GCS1. The first gate insulating films130may not extend along the boundaries between the first gate separation structures GCS1and the first gate electrodes120.

Referring toFIGS.8through12, the first gate electrodes120may include contact surface120_CS, which are in contact with the first gate separation structures GCS1. Referring toFIGS.8through10and12, the contact surface120_CS of the first gate electrodes120may include a concave surface in a plan view. Referring toFIG.11, the contact surface120_CS of the first gate electrodes120may appear as straight lines in a plan view.

Although not specifically illustrated, the contact surface120_CS of the first gate electrodes120ofFIGS.9,10, and12may appear as straight lines in a plan view.

The planar configuration between the first and second connection gate electrodes120_1and120_2and their corresponding first gate separation structure GCS1will hereinafter be described with reference toFIGS.8through12. The content described inFIGS.8through12may also be applicable to the planar configuration between the second and third connection gate electrodes120_2and120_3, respectively, and their corresponding first gate separation structure GCS1.

Referring toFIGS.8through12, the first gate spacers140may extend along the sidewalls of the first connection gate electrode120_1and the sidewalls of the second connection gate electrode120_2.

Referring toFIGS.8through11, the first gate spacers140on the sidewalls of the first connection gate electrode120_1may be separated from the first gate spacers140on the sidewalls of the second connection gate electrode120_2by the first gate separation structure GCS1.

Referring toFIG.12, an embodiment is shown in which the first gate spacers140on the sidewalls of the first connection gate electrode120_1are not separated from the first gate spacers140on the sidewalls of the second connection gate electrode120_2by the first gate separation structure GCS1.

Referring toFIGS.8through12, each of the first and second connection gate electrodes120_1and120_2may include a first gate electrode line portion120L, which extends in the second direction D2.

Referring toFIGS.8,11, and12, each of the first and second gate electrodes120_1and120_2may further include a first gate electrode protrusion portion120P, which extends from the first gate electrode line portion120L in the first direction D1. The first gate electrode protruding portions120P of the first and second connection gate electrodes120_1and120_2may be in contact with the first gate separation structure GCS1.

Referring toFIGS.8and11, a width W12of the first gate electrode protrusion portions120P of the first gate electrode structures GS1in the second direction D2may be less than a width W11of the first gate separation structure GCS1in the second direction D2.

Referring toFIG.12, in some embodiments the width W12of the first gate electrode protrusion portions120P of the first gate electrode structures GS1in the second direction D2may be the same as the width W11of the first gate separation structure GCS1in the second direction D2. Although not explicitly depicted, if the first gate separation structure GCS1removes parts of the first gate spacers140, the width W12of first gate electrode structures GS1including first gate electrode protrusion portions120P in the second direction D2may be less than the width W11of the first gate separation structure GCS1in the second direction D2.

Referring toFIG.9, the second connection gate electrode120_2may include a first gate electrode line portion120L and a first gate electrode protrusion portion120P, which extends from the first gate electrode line portion120L in the first direction D1. The first connection gate electrode120_1may include a first gate electrode line portion120L, but no first gate electrode protrusion portion120P. The first gate electrode protrusion portion120P of the second connection gate electrode120_2and the first gate electrode line portion120L of the first connection gate electrode120_1may be in contact with the first gate separation structure GCS1.

Referring toFIG.10, each of the first and second connection gate electrodes120_1and120_2may not include a first gate electrode protrusion portion120P.

As shown, for example, inFIGS.4and5, the height “H21+H22” from the bottom surface105BS of the field insulating film105to the upper surface CCW1_US of the first channel separation structure CCW1may be the same as a height “H31+H32” from the bottom surface105BS of the field insulating film105to upper surface GCS1_US of the first gate separation structures GCS1. For example, the upper surface GCS1_US of the first gate separation structures GCS1may be disposed on the same plane as the upper surface CCW1_US of the first channel separation structure CCW1.

A height H22of the first channel separation structure CCW1, in the third direction D3, may be different from a height H32, in the third direction D3, of the first gate separation structures GCS1.

For example, the height H22of the first channel separation structure CCW1in the third direction D3may be less than the height H32of the first gate separation structures GCS1in the third direction D3. A height H31from the bottom surface105BS of the field insulating film105to a lowermost part of the first gate separation structures GCS1may be less than the height H21from the bottom surface105BS of the field insulating film105to the lowermost part of the first channel separation structure CCW1. The height H11from the bottom surface105BS of the field insulating film105to the upper surface BP1_US of the first lower pattern BP1may be greater than the height H31from the bottom surface105BS of the field insulating film105to the lowermost part of the first gate separation structures GCS1. A height H12from the bottom surface105BS to the upper surface105US of the field insulating film105may be greater than the height H31from the bottom surface105BS of the field insulating film105to the lowermost part of the first gate separation structures GCS1.

For example, a distance W21between the first gate separation structures GCS1and the first channel separation structure CCW1in the second direction D2may be the same as a distance W22between the first gate separation structures GCS1and the second channel separation structure CCW2in the second direction D2. The distance W21between the first gate separation structures GCS1and the first channel separation structure CCW1in the second direction D2may be measured from the upper surface GCS1_US of the first gate separation structures GCS1and the upper surface CCW1_US of the first channel separation structure CCW1.

The first gate separation structures GCS1may include an insulating material. The first gate separation structures GCS1may include at least one of, SiN, SiON, SiO2, SiOCN, SiBN, SiOBN, SiOC, AlO, and a combination thereof. The first gate separation structure GCS1is illustrated as being a single film, but the present disclosure is not limited thereto.

The first source/drain contacts180may be disposed on the first source/drain patterns150. The first source/drain contacts180are electrically connected to the first source/drain patterns150. The first source/drain contacts180are disposed between the first channel separation structure CCW1and the first gate separation structures GCS1. The first source/drain contacts180may be disposed on the upper interlayer insulating film190. Parts of the source/drain etch stopper films185may be disposed between the first source/drain contacts180and the first channel separation structure CCW1.

The second source/drain contacts280may be disposed on the second source/drain patterns250. The second source/drain contacts280are electrically connected to the second source/drain patterns250. The second source/drain contacts280are disposed between the second channel separation structure CCW2and the first gate separation structures GCS1. The second source/drain contacts280may be disposed on the upper interlayer insulating film190. Parts of the source/drain tch stopper films185may be disposed between the second source/drain contacts280and the second channel separation structure CCW2.

The third source/drain contacts380may be disposed on the third source/drain patterns350. The third source/drain contacts380are electrically connected to the third source/drain patterns350. The fourth source/drain contacts480may be disposed on the fourth source/drain patterns450. The fourth source/drain contacts480are electrically connected to the fourth source/drain patterns450.

First contact silicide films155may be disposed between the first source/drain contacts180and the first source/drain patterns150. Second contact silicide films255may be disposed between the second source/drain contacts280and the second source/drain patterns250. Third contact silicide films355may be disposed between the third source/drain contacts380and the third source/drain patterns350. Fourth contact silicide films455may be disposed between the fourth source/drain contacts480and the fourth source/drain patterns450.

Although not specifically illustrated, gate contacts on the first gate electrodes120may be disposed in the first gate capping patterns145.

The first source/drain contacts180, the second source/drain contacts280, the third source/drain contacts380, and the fourth source/drain contacts480are illustrated as having a single conductive film structure, but the present disclosure is not limited thereto. Alternatively, each of the first source/drain contacts180, the second source/drain contacts280, the third source/drain contacts380, and the fourth source/drain contacts480may have a multilayer conductive film structure consisting of a barrier film and a plug film. The first source/drain contacts180, the second source/drain contacts280, the third source/drain contacts380, and the fourth source/drain contacts480may include at least one of, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The first contact silicide films155, the second contact silicide films255, the third contact silicide films355, and the fourth contact silicide films455may include a metal silicide material.

The 2D material may include a 2D allotrope or a 2D compound, for example, graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and tantalum sulfide, but the present disclosure is not limited thereto. That is, various other 2D materials are also applicable to the semiconductor device according to some embodiments of the present disclosure.

FIGS.13through16are cross-sectional or plan views of a semiconductor device according to some embodiments of the present disclosure. For convenience, the embodiment ofFIGS.13through16will hereinafter be described, highlighting the differences with the embodiment ofFIGS.1through12.

Specifically,FIGS.13and14are cross-sectional views taken along lines D-D and E-E, respectively, of the device shown inFIG.1.FIGS.15and16are plan views of region P of the device shown inFIG.1.

Referring toFIGS.13through16, first gate electrodes120may not be in contact with first gate separation structures GCS1.

Each of the first gate separation structures GCS1may have first sidewalls that are opposite to each other in a first direction D1, and first gate insulating films130may extend along the first sidewalls of their corresponding first gate separation structures GCS1. The first gate insulating films130may extend along boundaries between the first gate separation structures GCS1and the first gate electrodes120.

Each of first and second connection gate electrodes120_1and120_2may include only a first gate electrode line portion (e.g.,120L inFIG.11), which extends in a second direction D2. Each of the first and second connection gate electrodes120_1and120_2may not include a first gate electrode protrusion portion (e.g., “120P” ofFIG.11), which protrudes from the first gate electrode line portion120L in the first direction D1. The sidewalls of the first gate separation structures GCS1that face first gate structures GS1may appear as straight lines in a plan view.

Referring toFIG.15, the first gate structures GS1may be in contact with a first gate separation structure GCS1. For example, the first gate insulating films130may be in contact with the first gate separation structure GCS1.

Referring toFIG.16, parts of first gate spacers140may be disposed between the first gate structure GS1and the first and second connection gate structures120_1and120_2. The first and second connection gate structures120_1and120_2may not be in contact with the first gate separation structure GCS1. The first gate spacers140may include first portions and second portions. The first portions of the first gate spacers140overlap with the first gate separation structure GCS1in the first direction D1. The second portions of the first gate spacers140do not overlap with the first gate separation structure GCS1in the first direction D1. The thickness of the second portions of the first gate spacers140in the first direction D1may be greater than the thickness of the first portions of the first gate spacers140in the first direction D1.

Referring toFIG.13, a field insulating film105may include protrusion portions105_PI. The protrusion portions105_PI of the field insulating film105may extend in the third direction D3, perpendicular to and away from a first substrate100. The protrusion portions105_PI of the field insulating film105may be formed during the formation of pre-source/drain recesses (“150R_P” and “250R_P” ofFIG.73). The first gate spacers140, which extend in the first direction D1along the first gate separation structures GCS1, may be disposed on the protrusion portions105_PI of the field insulating film105. Source/drain etch stopper films185may cover the sidewalls of the protrusion portions105_PI of the field insulating film105.

FIGS.17and18are cross-sectional views of semiconductor devices according to some embodiments of the present disclosure. For convenience, the embodiments ofFIGS.17and18will hereinafter be described, highlighting the differences with the embodiment ofFIGS.1through12.

Referring toFIG.17, the height of a first channel separation structure CCW1may be the same as the height of a first gate separation structure GCS1.

A height H31from a bottom surface105BS of a field insulating film105to a lowermost part of the first gate separation structure GCS1may be the same as a height H21from the bottom surface105BS of the field insulating film105to a lowermost part of the first channel separation structure CCW1.

Referring toFIG.18, the height of a first channel separation structure CCW1may be greater than the height of a first gate separation structure GCS1.

A height H31from a bottom surface105BS of a field insulating film105to a lowermost part of the first gate separation structure GCS1may be greater than a height H21from the bottom surface105BS of the field insulating film105to a lowermost part of the first channel separation structure CCW1.

FIG.19is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. For convenience, the embodiment ofFIG.19will hereinafter be described, highlighting the differences with the embodiment ofFIGS.13through16.

Referring toFIG.19, a first gate separation structure GCS1may be disposed on protrusion portions105_PI of a field insulating film105.

The first gate separation structure GCS1may not be recessed into the field insulating film105. First gate spacers140, which extend in a first direction D1along the first gate separation structure GCS1, may be disposed on the protrusion portions105_PI of the field insulating film105.

FIGS.20through22are cross-sectional views of a semiconductor device according to some embodiments of the present disclosure. For convenience, the embodiment ofFIGS.20through22will hereinafter be described, highlighting the differences with the embodiment ofFIGS.1through12.

Referring toFIGS.20through22, the semiconductor device according to some embodiments of the present disclosure may further include first, second, third, and fourth lower insulating patterns BDI1, BDI2, BDI3, and BDI4.

The first lower insulating pattern BDI1may be disposed between a first lower pattern BP1and a first channel pattern CH1in the third direction D3. The first lower insulating pattern BDI1may be in contact with an upper surface BP1_US of the first lower pattern BP1. The first lower insulating pattern BDI1may extend in the first direction D1along the upper surface BP1_US of the first lower pattern BP1.

The second lower insulating pattern BDI2may be disposed between a second lower pattern BP2and a second channel pattern CH2in the third direction D3. The second lower insulating pattern BDI2may be in contact with an upper surface BP2_US of the second lower pattern BP2. The second lower insulating pattern BDI2may extend in the first direction D1along the upper surface BP2_US of the second lower pattern BP2.

The third lower insulating pattern BDI3may be disposed between the first lower pattern BP1and a third channel pattern CH3in the third direction D3. The third lower insulating pattern BDI3may be in contact with the upper surface BP1_US of the first lower pattern BP1. The third lower insulating pattern BDI3may extend in the first direction D1along the upper surface BP1_US of the first lower pattern BP1.

The fourth lower insulating pattern BDI4may be disposed between the second lower pattern BP2and a fourth channel pattern CH4in the third direction D3. The fourth lower insulating pattern BDI4may be in contact with the upper surface BP2_US of the second lower pattern BP2. The fourth lower insulating pattern BDI4may extend in the first direction D1along the upper surface BP2_US of the second lower pattern BP2.

The first lower insulating pattern BDI1may be spaced apart from the third lower insulating pattern BDI3in a second direction D2. A first channel separation structure CCW1may separate the first and third lower insulating patterns BDI1and BDI3.

The second lower insulating pattern BDI2may be spaced apart from the fourth lower insulating pattern BDI4in the second direction D2. A second channel separation structure CCW2may separate the second and fourth lower insulating patterns BDI2and BDI4.

The first, second, third, and fourth lower insulating patterns BDI1, BDI2, BDI3, and BDI4may not extend along an upper surface105US of a field insulating film105. The first, second, third, and fourth lower insulating patterns BDI1, BDI2, BDI3, and BDI4may not cover the upper surface105US of the field insulating film105.

The first channel pattern CH1may further include first sheet patterns NS1and a first dummy sheet pattern NSD1, which is disposed between the first lower insulating pattern BDI1and the first sheet patterns NS1in the third direction D3. The first dummy sheet pattern NSD1may be in contact with the first lower insulating pattern BDI1.

The second channel pattern CH2may further include second sheet patterns NS2and a second dummy sheet pattern NSD2, which is disposed between the second lower insulating pattern BDI2and the second sheet patterns NS2in the third direction D3. The second dummy sheet pattern NSD2may be in contact with the second lower insulating pattern BDI2.

The third channel pattern CH3may further include third sheet patterns NS3and a third dummy sheet pattern NSD3, which is disposed between the third lower insulating pattern BDI3and the third sheet patterns NS3in the third direction D3. The third dummy sheet pattern NSD3may be in contact with the third lower insulating pattern BDI3.

The fourth channel pattern CH4may further include fourth sheet patterns NS4and a fourth dummy sheet pattern NSD4, which is disposed between the fourth lower insulating pattern BDI4and the fourth sheet patterns NS4in the third direction D3. The fourth dummy sheet pattern NSD4may be in contact with the fourth lower insulating pattern BDI4.

The thickness of the first, second, third, and fourth dummy sheet patterns NSD1, NSD2, NSD3, and NSD4in the third direction D3may be less than the thickness of the first sheet patterns NS1, the second sheet patterns NS2, the third sheet patterns NS3, and the fourth sheet patterns NS4in the third direction D3. The first, second, third, and fourth dummy sheet patterns NSD1, NSD2, NSD3, and NSD4may include the same material as the first sheet patterns NS1, the second sheet patterns NS2, the third sheet patterns NS3, and the fourth sheet patterns NS4, although embodiments are not limited thereto.

The first lower insulating pattern BDI1may have an upper and a bottom surface that are opposite to each other in the third direction D3. The bottom surface of the first lower insulating pattern BDI1may be in contact with the upper surface BP1_US of the first lower pattern BP1. The upper surface of the first lower insulating pattern BDI1may be higher than the upper surface105US of the field insulating film105with respect to a bottom surface105BS of the field insulating film105. The upper surface of the first lower insulating pattern BDI1may protrude beyond an upper surface105US of the field insulating film105. As the first dummy sheet pattern NSD1is in contact with the upper surface of the first lower insulating pattern BDI1, first gate insulating films130may not be in contact with the upper surface of the first lower insulating pattern BDI1.

First source/drain patterns150may be in contact with the first dummy sheet pattern NSD1and the first sheet patterns NS1. The first source/drain patterns150may be in contact with the first lower insulating pattern BDI1. The first source/drain patterns150may not be in contact with the first lower pattern BP1.

Second source/drain patterns250may be in contact with the second dummy sheet pattern NSD2and the second sheet patterns NS2. The second source/drain patterns250may be in contact with the second lower insulating pattern BDI2. The second source/drain patterns250may not be in contact with the second lower pattern BP2.

Third source/drain patterns350may be in contact with the third dummy sheet pattern NSD3and the third sheet patterns NS3. The third source/drain patterns350may be in contact with the third lower insulating pattern BDI3. The third source/drain patterns350may not be in contact with the first lower pattern BP1.

Fourth source/drain patterns450may be in contact with the fourth dummy sheet pattern NSD4and the fourth sheet patterns NS4. The fourth source/drain patterns450may be in contact with the fourth lower insulating pattern BDI4. The fourth source/drain patterns450may not be in contact with the second lower pattern BP2.

FIG.23is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.FIGS.24and25are cross-sectional views of a semiconductor device according to some embodiments of the present disclosure.FIGS.26and27are cross-sectional views of a semiconductor device according to some embodiments of the present disclosure. For convenience, the embodiments ofFIGS.23through27will hereinafter be described, highlighting the differences with the embodiment ofFIGS.20through22.

The first source/drain patterns150may be in contact with the first lower insulating patterns BDI1and a first lower pattern BP1.

As the first lower insulating patterns BDI1are separated from one another by the first source/drain patterns150, a plurality of first lower insulating patterns BDI1may be disposed on an upper surface BP1_US of a first lower pattern BP1. The first lower insulating patterns BDI1may be arranged in the first direction D1. The first lower insulating patterns BDI1may be positioned to overlap with first gate structures GS1in the third direction D3.

For example, the above description of the first source/drain patterns150and the first lower insulating patterns BDI1may also be applicable to second source/drain patterns250and second lower insulating patterns BDI2, third source/drain patterns350and third lower insulating patterns BDI3, and fourth source/drain patterns450and fourth lower insulating patterns BDI4. In another example, the above description of the first source/drain patterns150and the first lower insulating patterns BDI1may also be applicable to the third source/drain patterns350and the third lower insulating patterns BDI3, but not to the second source/drain patterns250and second lower insulating patterns BDI2and the fourth source/drain patterns450and the fourth lower insulating patterns BDI4.

Referring toFIGS.24and25, first channel patterns CH1do not include dummy sheet patterns (“NSD1” ofFIGS.20and21) between a first lower insulating pattern BDI1and their corresponding sets of first sheet patterns NS1.

As no dummy sheet patterns are disposed between the first lower insulating pattern BDI1and the sets of first sheet pattern NS1, first gate insulating films130may be in contact with the upper surface of the first lower insulating pattern BDI1.

Similarly, in this embodiment, second channel patterns CH2, third channel patterns CH3, and fourth channel patterns CH4do not include dummy sheet patterns.

Referring toFIGS.26and27, the semiconductor device according to some embodiments of the present disclosure may further include sacrificial semiconductor patterns160SC, sacrificial pattern capping films160IP, a rear source/drain contact175, and a rear wiring line290.

First and second lower patterns BP1and BP2may be disposed on a second substrate

200. The second substrate200may have first and second surfaces200US and200BS, respectively, which are opposite to each other in the third direction D3. The first and second lower patterns BP1and BP2may be disposed on the first surface200US, which may be an upper surface of the second substrate200.

The second substrate200may include an insulating material, such as at least one of silicon oxide, silicon nitride, and a combination thereof. The second substrate200may be a substrate formed by a deposition process after the removal of the first substrate100ofFIGS.2through6.

The field insulating film105may be in contact with the second substrate200. The bottom surface105BS of the field insulating film105faces the second substrate200.

The sacrificial semiconductor patterns160SC may be disposed in the first and second lower patterns BP1and BP2. The sacrificial semiconductor patterns160SC may be disposed between the second substrate200and first source/drain patterns150, second source/drain patterns250, third source/drain patterns350, and fourth source/drain patterns450. The sacrificial semiconductor patterns160SC may overlap with the first source/drain patterns150, the second source/drain patterns250, the third source/drain patterns350, and the fourth source/drain patterns450in the third direction D3.

The sacrificial pattern capping films160IP may be disposed between the first source/drain patterns150and the sacrificial semiconductor patterns160SC and between the second source/drain patterns250and the sacrificial semiconductor patterns160SC. The sacrificial pattern capping films160IP may be disposed between the third source/drain patterns350and the sacrificial semiconductor patterns160SC and between the fourth source/drain patterns450and the sacrificial semiconductor patterns160SC.

The sacrificial semiconductor patterns160SC may include a material with etch selectivity with respect to the first and second lower patterns BP1and BP2. In a case where the first and second lower patterns BP1and BP2are Si patterns, the sacrificial semiconductor patterns160SC may include SiGe. The sacrificial pattern capping films160IP may include an insulating material.

The rear wiring line290may be disposed in the second substrate200. The rear wiring line290may include a line portion and a via portion. The line portion of the rear wiring line290is illustrated as extending in a first direction D1, but the present disclosure is not limited thereto. The via portion of the rear wiring line290may extend upwardly from the line portion of the rear wiring line290in the third direction D3. Contrary to what is depicted, the rear wiring line290may not include the via portion.

The rear source/drain contact175may be disposed between the first source/drain patterns150and the rear wiring line290. The rear source/drain contact175electrically connects the first source/drain contacts150and the rear wiring line290.

The rear source/drain contact175is illustrated as being connected to some of the first source/drain patterns150, but the present disclosure is not limited thereto. Although not explicitly depicted, the rear source/drain contact175may be connected to the second source/drain patterns250, the third source/drain patterns350, and the fourth source/drain patterns450.

A rear contact silicide film156may be disposed between the rear source/drain contact175and the first source/drain patterns150.

The rear source/drain contact175and the rear wiring line290are illustrated as being single conducive films, but the present disclosure is not limited thereto. Although not explicitly depicted, at least one of the rear source/drain contact175and the rear wiring line290may have a multilayer conductive film structure including a barrier film and a filling film. The rear source/drain contact175and the rear wiring line290may include at least one of, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a 2D material.

FIGS.28through30are cross-sectional views of semiconductor devices according to some embodiments of the present disclosure. For convenience, the embodiments ofFIGS.28through30will hereinafter be described, highlighting the differences with the embodiment ofFIGS.1through12.

Referring toFIG.28, a first gate separation structure GCS1may be in contact with first and second source/drain patterns150and250.

Source/drain etch stopper films185may not be disposed on a field insulating film105between the first source/drain pattern150and the first gate separation structure GCS1. The source/drain etch stopper films185may not be disposed between the second source/drain pattern250and the first gate separation structure GCS1.

Referring toFIG.29, a distance W21in the second direction D2between a first gate separation structure GCS1and a first channel separation structure CCW1may be greater than a distance W22in the second direction D2between the first gate separation structure GCS1and a second channel separation structure CCW2.

The first gate separation structure GCS1may not be in contact with a first source/drain pattern150. The first gate separation structure GCS1may be in contact with a second source/drain pattern250.

Referring toFIG.30, the semiconductor device according to some embodiments of the present disclosure may further include inner spacers140IN, which are disposed between second source/drain patterns250and first inner gate structures INT_GS1.

The inner spacers140IN may be disposed between a second lower pattern BP2and their corresponding second sheet patterns NS2and between the corresponding second sheet patterns NS2, which are adjacent to one another in a third direction D3. The first inner gate structures INT_GS1may not be in contact with the second source/drain patterns250.

The inner spacers140IN may include at least one of, for example, SiN, SiON, SiO2, SiOCN, SiBN, SiOBN, SiOC, and a combination thereof.

FIG.31is a layout view of a semiconductor device according to some embodiments of the present disclosure.FIGS.32through35are cross-sectional views taken along lines A-A, B-B, C-C, and E-E of the device shown inFIG.31. For convenience, the embodiment ofFIGS.31through35will hereinafter be described, highlighting the differences with the embodiment ofFIGS.1through12.

Referring toFIGS.31through35, the semiconductor device according to some embodiments of the present disclosure may further include second and third gate electrodes220and320, respectively, between the first gate electrodes120.

Second and third gate structures GS2and GS3may be disposed between first gate structures GS1that are adjacent to each other in a first direction D1. The second and third gate structures GS2and GS3may be aligned with one another in a second direction D2.

The second and third gate structures GS2and GS3may be spaced apart from each other in the second direction D2. A first gate separation structure GCS1may separate the second and third gate structures GS2and GS3. For example, the first gate structures GS1may be separated by the first gate separation structure GCS1, and as a result, the second and third gate structures GS2and GS3may be formed.

The second gate structure GS2may be disposed between a first channel separation structure CCW1and the first gate separation structure GCS1. The second gate structure GS2may be in contact with the first channel separation structure CCW1and the first gate separation structure GCS1. The second gate structure GS2may be disposed on a first lower pattern BP1.

The third gate structure GS3may be disposed between a second channel separation structure CCW2and the first gate separation structure GCS1. The third gate structure GS3may be in contact with the second channel separation structure CCW2and the first gate separation structure GCS1. The third gate structure GS3may be disposed on a second lower pattern BP2.

The second gate structure GS2may be in contact with an upper surface105US of a field insulating film105and an upper surface BP1_US of a first lower pattern BP1. Some of a plurality of first channel patterns CH1may be disposed between the second gate structure GS2and the first channel separation structure CCW1.

The third gate structure GS3may be in contact with the upper surface105US of the field insulating film105and an upper surface BP2_US of the second lower pattern BP2. Some of a plurality of second channel patterns CH2may be disposed between the third gate structure GS3and the second channel separation structure CCW2.

The second gate structure GS2may include the second gate electrode220and a second gate insulating film230. The third gate structure GS3may include the third gate electrode320and a third gate insulating film330.

The second gate structure GS2may include second inner gate structures INT_GS2. The second inner gate structures INT_GS2may be disposed between the first lower pattern BP1and their corresponding first sheet patterns NS1and between the corresponding first sheet patterns NS1, which are adjacent to one another in a third direction D3. The third gate structure GS3may include third inner gate structures INT_GS3. The third inner gate structures INT_GS3may be disposed between the second lower pattern BP2and their corresponding second sheet patterns NS2and between the corresponding second sheet patterns NS2, which are adjacent to one another in the third direction D3.

The second and third gate electrodes220and320may be disposed between the first and second channel separation structures CCW1and CCW2, which are adjacent to each other in the second direction D2. The second and third gate electrodes220and320may be aligned in the second direction D2. The second and third gate electrodes220and320may be disposed between the first gate electrodes120that are adjacent to each other in the first direction D1. For example, the second and third gate electrodes220and320may be disposed between first and third connection gate electrodes120_1and120_3.

The second gate insulating film230may extend (in the first direction D1and/or second direction D2) along the upper surface105US of the field insulating film105and the upper surface BP1_US of the first lower pattern BP1. The second gate insulating film230may extend along parts of sidewalls CCW1_SW of the first channel separation structure CCW1. The second gate insulating film230is disposed between the second gate electrode220and the first sheet patterns NS1.

The third gate insulating film330may extend along the upper surface105US of the field insulating film105and the upper surface BP2_US of the second lower pattern BP2. The third gate insulating film330may extend along parts of sidewalls CCW2_SW of the second channel separation structure CCW2. The third gate insulating film330is disposed between the third gate electrode320and the second sheet patterns NS2.

Second gate spacers240may be disposed on the sidewalls of the second gate structure GS2. Third gate spacers340may be disposed on the sidewalls of the third gate structure GS3.

A second gate capping pattern245may be disposed on the second gate structure GS2. The second gate capping pattern245may be disposed between the first channel separation structure CCW1and the first gate separation structure GCS1. The second gate capping pattern245may be in contact with the first channel separation structure CCW1and the first gate separation structure GCS1.

A third gate capping pattern345may be disposed on the third gate structure GS3. The third gate capping pattern345may be disposed between the second channel separation structure CCW2and the first gate separation structure GCS1. The third gate capping pattern345may be in contact with the second channel separation structure CCW2and the first gate separation structure GCS1.

The first gate separation structure GCS1may be in contact with the second and third gate structures GS2and GS3, respectively. The first gate separation structure GCS1may be in contact with the second gate electrode220and the second gate insulating film230. The first gate separation structure GCS1may be in contact with the third gate electrode320and the third gate insulating film330.

FIG.36is a layout view of a semiconductor device according to some embodiments of the present disclosure.FIGS.37and38are cross-sectional views taken along lines C-C and E-E of the device shown inFIG.36.FIGS.39through41are plan views of region Q of the device shown inFIG.36. For convenience, the embodiment ofFIGS.36through41will hereinafter be described, highlighting the differences with the embodiment ofFIGS.1through12.

Referring toFIGS.36through41, the semiconductor device according to some embodiments of the present disclosure may further include a second gate separation structure GCS2, a second gate electrode220, and a third gate electrode320.

A second gate structure GS2, including the second gate electrode220, and a third gate structure GS3, including the third gate electrode320, may be substantially the same as their corresponding counterparts ofFIGS.31through35and will hereinafter be described, focusing mainly on the differences from their corresponding counterparts ofFIGS.31through35.

A second gate separation structure GCS2may be disposed between the second and third gate structures GS2and GS3. The second gate separation structure GCS2may be disposed between first gate separation structures GCS1, which are adjacent to each other in a first direction D1.

The second gate separation structure GCS2separates the second and third gate structures GS2and GS3. For example, first gate structures GS1may be separated by the second gate separation structure GCS2in the first direction D1, and as a result, the second and third gate structures GS2and GS3may be formed.

A second gate capping pattern245may be disposed between a first channel separation structure CCW1and the second gate separation structure GCS2. The second gate capping pattern245may be in contact with the first channel separation structure CCW1and the second gate separation structure GCS2.

A third gate capping pattern345may be disposed between a second channel separation structure CCW2and the second gate separation structure GCS2. The third gate capping pattern345may be in contact with the second channel separation structure CCW2and the second gate separation structure GCS2.

The second gate separation structure GCS2may be in contact with the second and third gate structures GS2and GS3. The second gate separation structure GCS2may be in contact with the second gate electrode220and a second gate insulating film230. The second gate separation structure GCS2may be in contact with the third gate electrode320and a third gate insulating film330. The second gate separation structure GCS2may be in contact with the first gate separation structures GCS1, which are disposed on both sides of the second gate separation structure GCS2in the first direction D1.

The second gate separation structure GCS2may include an insulating material. The second gate separation structure GCS2may include at least one of, for example, SiN, SiON, SiO2, SiOCN, SiBN, SiOBN, SiOC, AlO, and a combination thereof. The second gate separation structure GCS2is illustrated as being a single film, but the present disclosure is not limited thereto.

A height “H21+H22” from a bottom surface105BS of a field insulating film105to an upper surface CCW1_US of the first channel separation structure CCW1in the third direction D3may be the same as a height “H41+H42” from the bottom surface105BS of the field insulating film105to an upper surface GCS2_US of the second gate separation structure GCS2. For example, the upper surface GCS2_US of the second gate separation structure GCS2may be disposed on the same plane as the upper surface CCW1_US of the first channel separation structure CCW1.

A height H22, in the third direction D3, of the first channel separation structure CCW1may be different from a height H42, in the third direction D3, of the second gate separation structure GCS2. A height H41from the bottom surface105BS of the field insulating film105to a lowermost part of the second gate separation structure GCS2in the third direction D3may be different from a height H21from the bottom surface105BS of the field insulating film105to a lowermost part of the second gate separation structure GCS2. Contrary to what is depicted, the height H22of the first channel separation structure CCW1may be the same as the height H42of the second gate separation structure GCS2.

A height H32, in the third direction D3, of the first gate separation structure GCS1may be different from a height H42, in the third direction D3, of the second gate separation structure GCS2. A height H41from the bottom surface105BS of the field insulating film105to the lowermost part of the second gate separation structure GCS2may be different from a height H31from the bottom surface105BS of the field insulating film105to the lowermost part of the first gate separation structure GCS1. Contrary to what is depicted, the height H32of the first gate separation structure GCS1may be the same as the height H42of the second gate separation structure GCS2.

Referring toFIG.39, a width W31of the first gate separation structure GCS1in a second direction D2may be the same as a width W32of the second gate separation structure GCS2in the second direction D2. For example, the width W31of the first gate separation structure GCS1in the second direction D2may be measured on an upper surface GCS1_US of the first gate separation structure GCS1.

A distance W33between the first channel separation structure CCW1and the second gate separation structure GCS2in the second direction D2may be the same as a distance W34between the second channel separation structure CCW2and the second gate separation structure GCS2in the second direction D2.

Referring toFIG.40, the width W31of the first gate separation structure GCS1in the second direction D2may be different from the width W32of the second gate separation structure GCS2in the second direction D2. For example, the width W31of the first gate separation structure GCS1in the second direction D2may be greater than the width W32of the second gate separation structure GCS2in the second direction D2, but the present disclosure is not limited thereto.

Referring toFIG.41, the distance W33between the first channel separation structure CCW1and the second gate separation structure GCS2in the second direction D2may be different from the distance W34between the second channel separation structure CCW2and the second gate separation structure GCS2in the second direction D2.

FIGS.42through67are layout views or cross-sectional views illustrating intermediate steps of an example method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Referring toFIGS.42through44, first and second mold fin-type patterns FMS1and FMS2may be formed on a first substrate100.

The first and second mold fin-type pattern FMS1and FMS2may extend in a first direction D1. The first and second mold fin-type patterns FMS1and FMS2may be spaced apart from each other in a second direction D2. The first and second mold fin-type patterns FMS1and FMS2may be defined by fin trenches FT, which extend in the first direction D1.

The first mold fin-type pattern FMS1may include a first lower pattern BP1and a first pre-pattern structure PFS1. The second mold fin-type pattern FMS2may include a second lower pattern BP2and a second pre-pattern structure PFS2. The first pre-pattern structure PFS1is formed on the first lower pattern BP1. The second pre-pattern structure PFS2is formed on the second lower pattern BP2.

Each of the first and second pre-pattern structures PFS1and PFS2may include a plurality of pre-sacrificial patterns SC_L and a plurality of pre-active patterns ACT_L, which are alternately stacked with the pre-sacrificial patterns SC_L in a third direction D3. For example, the pre-active patterns ACT_L may include silicon films, and the pre-sacrificial patterns SC_L may include SiGe films.

A field insulating film105may be formed on the first substrate100. The field insulating film105may partially fill the fin trenches FT.

Referring toFIGS.45through48, a dummy gate electrode120DP may be formed on the first and second mold fin-type patterns FMS1and FMS2.

The dummy gate electrode120DP may include extension portions120DP_L, which extend in the second direction D2, and a connection portion120DP_E, which intersects the extension portions120DP_L and extends in the first direction D1. In a plan view, the dummy gate electrode120DP may be configured to have a mesh shape.

The extension portions120DP_L of the dummy gate electrode120DP may be formed on the first and second mold fin-type patterns FMS1and FMS2. The extension portions120DP_L of the dummy gate electrode120DP may intersect the first and second mold fin-type patterns FMS1and FMS2.

The connection portion120DP_E of the dummy gate electrode120DP may connect each set of extension portions120DP_L that are adjacent to one another in the first direction D1. The connection portion120DP_E of the dummy gate electrode120DP may be formed between the first and second mold fin-type patterns FMS1and FMS2. The connection portion120DP_E of the dummy gate electrode120DP may be formed on the field insulating film105.

Dummy gate insulating films130P are formed between the dummy gate electrode120DP and the first mold fin-type pattern FMS1and between the dummy gate electrode120DP and the second mold fin-type pattern FMS2. A dummy gate capping film120HM is formed on the dummy gate electrode120DP. The dummy gate capping film120HM is formed along the upper surface of the dummy gate electrode120DP.

The dummy gate insulating films130P may include, for example, silicon oxide, but the present disclosure is not limited thereto. The dummy gate electrode120DP may include, for example, polysilicon, but the present disclosure is not limited thereto. The dummy gate capping film120HM may include, for example, silicon nitride, but the present disclosure is not limited thereto.

Referring toFIGS.49through51, dummy gate spacers140P may be formed on the sidewalls of the dummy gate electrode120DP.

During the formation of the dummy gate spacers140P, a first pre-source/drain recess150R_P may be formed in the first mold fin-type pattern FMS1using the dummy gate electrode120DP as a mask.

Also, a second pre-source/drain recess250R_P may be formed in the second mold fin-type pattern FMS2using the dummy gate electrode120DP as a mask. The first and second pre-source/drain recesses150R_P and250R_P may be formed at the same time.

The first and second pre-source/drain recesses150R_P and250R_P may be formed between their corresponding sets of extension portions120DP_L that are adjacent to one another in the first direction D1. The first pre-source/drain recess150R_P may be formed by removing at least a portion of the first pre-pattern structure PFS1. The second pre-source/drain recess250R_P may be formed by removing at least a portion of the second pre-pattern structure PFS2.

Referring toFIGS.52through55, a sacrificial insulating film50may be formed on the first substrate100.

The sacrificial insulating film50may fill the first and second pre-source/drain recesses150R_P and250R_P. The sacrificial insulating film50may fill the spaces in the dummy gate electrode120DP. The sacrificial insulating film50may be formed up to the upper surface of the dummy gate capping film120HM.

Thereafter, a first channel separation structure CCW1may be formed on the first lower pattern BP1. The first channel separation structure CCW1may extend in the first direction D1. The first channel separation structure CCW1may be formed in the first pre-pattern structure PFS1and the sacrificial insulating film50. The first channel separation structure CCW1may separate the first pre-pattern structure PFS1into two parts. As a result, first upper pattern structures UP1and third upper pattern structures UP3may be formed on the first lower pattern BP1. Also, the first channel separation structure CCW1may separate the first pre-source/drain recess150R_P into two first source/drain recesses150R.

A second channel separation structure CCW2may be formed on the second lower pattern BP2. The second channel separation structure CCW2may extend in the first direction D1. The second channel separation structure CCW2may be formed in the second pre-pattern structure PFS2and the sacrificial insulating film50. The second channel separation structure CCW2may separate the second pre-pattern structure PFS2into two parts. As a result, second upper pattern structures UP2and fourth upper pattern structures UP4may be formed on the second lower pattern BP2. Also, the second channel separation structure CCW2may separate the second pre-source/drain recess250R_P into two second source/drain recesses250R. The first and second channel separation structures CCW1and CCW2may be formed at the same time.

Each of the first upper pattern structures UP1, second upper pattern structures UP2, third upper pattern structures UP3, and fourth upper pattern structures UP4may include a plurality of sacrificial patterns SC_P and a plurality of active patterns ACT_P, which are alternately stacked with the sacrificial patterns SC_P in the third direction D3.

The dummy gate spacers140P may be separated by the first and second channel separation structures CCW1and CCW2. As a result, first gate spacers140may be formed. Referring toFIGS.52through58, the sacrificial insulating film50is removed.

As a result, the first source/drain recesses150R and the second source/drain recesses250R may be exposed. In other words, the first upper pattern structures UP1, the second upper pattern structures UP2, the third upper pattern structures UP3, and the fourth upper pattern structures UP4may be exposed.

First source/drain patterns150and third source/drain patterns350may be formed in the first source/drain recesses150R. The first source/drain patterns150and the third source/drain patterns350may be formed on the first lower pattern BP1.

The first source/drain patterns150and the third source/drain patterns350may be separated by the first channel separation structure CCW1. The first source/drain patterns150and the third source/drain patterns350may be in contact with the first channel separation structure CCW1. The first source/drain patterns150may be in contact with the first upper pattern structures UP1. Although not specifically illustrated, the third source/drain patterns350may be in contact with the third upper pattern structures UP3.

Second source/drain patterns250and fourth source/drain patterns450may be formed in the second source/drain recesses250R. The second source/drain patterns250and the fourth source/drain patterns450may be formed on the second lower pattern BP2.

The second source/drain patterns250and the fourth source/drain patterns450may be separated by the second channel separation structure CCW2. The second source/drain patterns250and the fourth source/drain patterns450may be in contact with the second channel separation structure CCW2. The second source/drain patterns250may be in contact with the second upper pattern structures UP2. Although not specifically illustrated, the fourth source/drain patterns450may be in contact with the fourth upper pattern structures UP4.

Referring toFIGS.56-58, the second source/drain patterns250, the third source/drain patterns350, and the fourth source/drain patterns450may be in contact with the second upper pattern structures UP2, the third upper pattern structures UP3, and the fourth upper pattern structures UP4, respectively.

After the formation of the first source/drain patterns150and the third source/drain patterns350, the second source/drain patterns250and the fourth source/drain patterns450may be formed. Alternatively, after the formation of the second source/drain patterns250and the fourth source/drain patterns450, the first source/drain patterns150and the third source/drain patterns350may be formed.

Thereafter, source/drain etch stopper films185and upper interlayer insulating films190may be formed on the first source/drain patterns150, the second source/drain patterns250, the third source/drain patterns350, and the fourth source/drain patterns450. During the formation of the source/drain etch stopper films185and the upper interlayer insulating films190, the dummy gate capping film120HM may be removed. The dummy gate electrode120DP may be exposed.

Referring toFIGS.59through61, a gate trench120tmay be formed by removing the dummy gate electrode120DP and the dummy gate insulating films130P (seeFIG.58).

The gate trench120tmay expose the first upper pattern structures UP1, the second upper pattern structures UP2, the third upper pattern structures UP3, and the fourth upper pattern structures UP4. The gate trench120tmay include extension portions120t_L, which extend in the second direction D2, and a connection portion120t_E, which intersects the extension portions120t_L and extends in the first direction D1.

The extension portions120t_L of the gate trench120tmay be formed at the locations where the extension portions120DP_L of the dummy gate electrode120DP have been removed. The connection portion120t_E of the gate trench120tmay be formed at the location where the connection120DP_E of the dummy gate electrode120DP has been removed. The gate trench120tmay have a mesh shape.

Referring toFIGS.62and63, by removing the sacrificial patterns SC_P of each of the first upper pattern structures UP1, exposed by the gate trench120t,first sheet patterns NS1, which are in contact with the first channel separation structure CCW1and the first source/drain patterns150, may be formed.

By removing the sacrificial patterns SC_P of each of the second upper pattern structures UP2, exposed by the gate trench120t,second sheet patterns NS2, which are in contact with the second channel separation structure CCW2and the second source/drain patterns250, may be formed.

By removing the sacrificial patterns SC_P of each of the third upper pattern structures UP3, exposed by the gate trench120t,third sheet patterns NS3may be formed, and by removing the sacrificial patterns SC_P of each of the fourth upper pattern structures UP4, exposed by the gate trench120t,fourth sheet patterns NS4may be formed.

Referring toFIGS.62through66, a pre-gate structure, which includes a pre-gate electrode120PP and first gate insulating films130, may be formed in the gate trench120t.

First gate capping patterns145may be formed on the pre-gate electrode120PP and the first gate insulating films130. The pre-gate electrode120PP may include extension portions120PL and a connection portion120PE. The extension portions120PL of the pre-gate electrode120PP extend in the second direction D2. The extension portions120PL of the pre-gate electrode120PP may be formed in the extension portions120t_L of the gate trench120t.The extension portions120PL of the pre-gate electrode120PP may intersect the first sheet patterns NS1and the second sheet patterns NS2.

The connection portion120PE of the pre-gate electrode120PP extends in the first direction D1. The connection portion120PE of the pre-gate electrode120PP may be formed in the connection portion120t_E of the gate trench120t.The connection portion120PE of the pre-gate electrode120PP connects each set of extension portions120PL of the pre-gate electrode120PP that are adjacent to one another in the first direction D1.

Referring toFIGS.64through67, a first gate separation structure GCS1may be formed between extension portions120PL of the pre-gate electrode120PP that are adjacent to each other in the first direction D1.

The first gate separation structure GCS1may separate the extension portions120PL of the pre-gate electrode120PP that are adjacent to each other in the first direction D1. During the formation of the first gate separation structure GCS1, the connection portion120PE of the pre-gate electrode120PP may be removed.

At least parts of the first gate insulating films130, which extend along the sidewalls and the bottom surface of the connection portion120PE of the pre-gate electrode120PP, may be removed. As a result, first gate electrodes120may be formed.

Although not specifically illustrated, the first gate separation structure GCS1may separate at least one extension portion120PL of the pre-gate electrode120PP into two parts. In this case, the two parts may become the second and third gate electrodes220and320ofFIG.34.

FIGS.68through78are layout views or cross-sectional views illustrating intermediate steps of an example method of fabricating a semiconductor device according to some embodiments of the present disclosure. Specifically,FIGS.68and69illustrate steps to be performed after the steps depicted inFIGS.42through44.

Referring toFIGS.68and69, a plurality of dummy gate electrodes120DP may be formed on first and second mold fin-type patterns FMS1and FMS2.

The dummy gate electrodes120DP may extend in a second direction D2. The dummy gate electrodes120DP are not connected to one another. The dummy gate electrodes120DP may have a linear shape. The dummy gate electrodes120DP may intersect the first and second mold fin-type patterns FMS1and FMS2.

Cross-sectional views taken along lines A-A and C-C ofFIG.68may be the same asFIGS.46and47, respectively.

Referring toFIGS.70and71, first gate separation structures GCS1may be formed on a field insulating film105.

The first gate separation structures GCS1may be formed between the first and second mold fin-type patterns FMS1and FMS2. The first gate separation structures GCS1connect pairs of dummy gate electrodes120DP that are adjacent to each other in the first direction D1.

Cross-sectional views taken along lines A-A and C-C ofFIG.70may be the same asFIGS.46and47, respectively.

Referring toFIGS.72and73, dummy gate spacers140P may be formed on the sidewalls of the dummy gate electrodes120DP and the sidewalls of the first gate separation structures GCS1.

During the formation of the dummy gate spacers140P, first pre-source/drain recesses150R_P and second pre-source/drain recesses250R_P may be formed using the dummy gate electrodes120DP as a mask. The first pre-source/drain recesses150R_P may be formed in the first mold fin-type pattern FMS1. The second pre-source/drain recesses250R_P may be formed in the second mold fin-type pattern FMS2.

A cross-sectional view taken along line A-A ofFIG.72may be the same asFIG.50.

Referring toFIGS.74and75, a first channel separation structure CCW1may be formed on a first lower pattern BP1. A second channel separation structure CCW2may be formed on a second lower pattern BP2.

During the formation of the first and second channel separation structures CCW1and CCW2, first upper pattern structures UP1, second upper pattern structures UP2, third upper pattern structures UP3, and fourth upper pattern structures UP4may be formed. Also, first source/drain recesses150R and second source/drain recesses250R may be formed. First gate spacers140may be formed.

The formation of the first and second channel separation structures CCW1and CCW2may be performed in substantially the same manner as that described above with reference toFIGS.52through55.

First source/drain patterns150and third source/drain patterns350may be formed in the first source/drain recesses150R. Second source/drain patterns250and fourth source/drain patterns450may be formed in the second source/drain recesses250R.

Thereafter, source/drain etch stopper films185and upper interlayer insulating films190may be formed on the first source/drain patterns150, the second source/drain patterns250, the third source/drain patterns350, and the fourth source/drain patterns450. The dummy gate electrodes120DP may be exposed.

The steps depicted inFIG.76may be substantially the same as the steps described with reference toFIGS.56through58.

Referring toFIGS.59through63and76through78, a gate trench120tmay be formed by removing the dummy gate electrodes120DP and the dummy gate insulating films130P.

The gate trench120tmay expose the first upper pattern structures UP1, the second upper pattern structures UP2, the third upper pattern structures UP3, and the fourth upper pattern structures UP4. Sacrificial patterns SC_P may be removed from each of the first upper pattern structures UP1, second upper pattern structures UP2, third upper pattern structures UP3, and fourth upper pattern structures UP4that are exposed. Consequently, first sheet patterns NS1, second sheet patterns NS2, third sheet patterns NS3, and fourth sheet patterns NS4may be formed.

Thereafter, first gate electrodes120and first gate insulating films130may be formed in the gate trench120t.The first gate electrodes120may intersect the first sheet patterns NS1and the second sheet patterns NS2.

FIGS.79through83are cross-sectional views illustrating intermediate steps of an example method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Referring toFIGS.79and80, a first mold fin-type pattern FMS1may include a lower buffer pattern BBF, which is disposed between a first lower pattern BP1and a first pre-pattern structure PFS1in the third direction D3. The first pre-pattern structure PFS1may further include a pre-dummy active pattern ACT_DL.

Similarly, a second mold fin-type pattern FMS2may include a lower buffer pattern BBF, which is disposed between a second lower pattern BP2and a second pre-pattern structure PFS2in the third direction D3. The second pre-pattern structure PFS2may further include a pre-dummy active pattern ACT_DL.

Alternatively, contrary to what is depicted, in some embodiments the first and second pre-pattern structures PFS1and PFS2may not include the pre-dummy active patterns ACT_DL.

For example, the pre-dummy active patterns ACT_DL may include Si films. The lower buffer patterns BBF may include a material with an etch selectivity with respect to pre-active patterns ACT_L and pre-sacrificial patterns SC_L.

For example, the pre-sacrificial patterns SC_L may include SiGe films doped with C, and the lower buffer patterns BBF may include SiGe films. In another example, the pre-sacrificial patterns SC_L may include SiGe films, and the lower buffer patterns BBF may include SiGe films doped with C. The etch rate of a SiGe film may vary depending on whether or not the SiGe film is doped with C. That is, the pre-sacrificial patterns SC_L may have an etch selectivity with respect to the lower buffer patterns BBF.

The etch selectivity of the lower buffer patterns BBF and the pre-active patterns ACT_L is not particularly limited. The material of the lower buffer pattern BBF is not restricted to a specific type as long as it exhibits etch selectivity toward the pre-active patterns ACT_L and the pre-sacrificial patterns SC_L.

Referring toFIGS.81through83, dummy gate electrodes120DP may be formed on the first and second mold fin-type patterns FMS1and FMS2.

Thereafter, the lower buffer patterns BBF may be redisposed with pre-lower insulating patterns BDI_D. Specifically, spaces may be formed between the first lower pattern BP1and the first pre-pattern structure PFS1and between the second lower pattern BP2and the second pre-pattern structure PFS2by removing the lower buffer patterns BBF. As the lower buffer patterns BBF have etch selectivity toward the pre-sacrificial patterns SC_L and the lower buffer patterns BBF, the lower buffer patterns BBF can be selectively removed. The spaces between the first lower pattern BP1and the first pre-pattern structure PFS1and between the second lower pattern BP2and the second pre-pattern structure PFS2can be filled with an insulating material. As a result, pre-lower insulating patterns BDI_D may be formed.

Thereafter, the steps depicted inFIGS.49through67may be performed. During the formation of first and second channel separation structures CCW1and CCW2, each of the pre-lower insulating patterns BDI_D may be separated into two parts.

Alternatively, the steps depicted inFIGS.68through78may be performed after the steps depicted inFIGS.79and80.

Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and may be implemented in various different forms. Those of ordinary skill in the technical field to which the present disclosure belongs will be able to understand that the present disclosure may be implemented in other specific forms without changing the technical idea or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments as described above are not restrictive but illustrative in all respects.