Wide input DC/DC resonant converter to control reactive power

A DC/DC resonant converter system includes a primary converter unit having a split resonant tank circuit. The resonant converter unit further includes a plurality of primary switching units that control the current flowing into the split resonant tank circuit. A controlled secondary rectifier unit includes a plurality of rectifier switching units to reduce reactive power in the primary converter unit. A phase-shift controller is in electrical communication with the primary converter unit and the controlled secondary rectifier unit. The phase-shift controller is configured to determine a rectifier phase-shift angle based on the plurality of primary switching units and to control switching of the plurality of rectifier switching units based on the rectifier phase-shift angle.

BACKGROUND

The present disclosure relates generally to DC/DC resonant converters, and more specifically, a wide input DC/DC resonant converter that limits reactive power.

Conventional DC/DC switched-mode power converters, and in particular resonant converters, often use phase-shift modulation (PSM) control that reduce switching losses and noise by operating in a Zero-Voltage Switching (ZVS) mode. The ZVS mode may be utilized with a high switching frequency to provide a compact and low-loss power converter. During light load conditions the ZVS mode becomes ineffective, and in high input line conditions excessive reactive power occurs.

A conventional method of improving ZVS during light load conditions is to introduce an additional inductive current, i.e., a lagging current source, into the converter nodes coupled to the switching transistors. The lagging current source extends the range of low-loss switching to light loads, but often compromises efficiency at mid-range and full loads. For example, conventional series resonant converter (SRC) topologies are designed to deliver the full rated power at the lowest input voltage. However, the power stored in the resonant tank at any given half-cycle interval is proportional to the square of the input voltage. Consequently, in full-load conditions, any increase of the input voltage generates both reactive power and circulating currents that reduces efficiency at high input voltages.

SUMMARY

A direct current to direct current (DC/DC) resonant converter system includes a primary converter unit having a split resonant tank circuit. The resonant converter unit further includes a plurality of primary switching units that regulates the current flowing into the split resonant tank circuit. A controlled secondary rectifier unit includes a plurality of rectifier switching units to reduce reactive power in the primary converter unit. A phase-shift controller is in electrical communication with the primary converter unit and the controlled secondary rectifier unit. The phase-shift controller is configured to determine a rectifier phase-shift angle based on the plurality of primary switching units and to control switching of the plurality of rectifier switching units based on the rectifier phase-shift angle.

According to another embodiment, a method of controlling a resonant power in a DC/DC converter comprises determining transfer coefficients of the DC/DC converter, and determining an input voltage of the DC/DC converter. The method further includes determining at least one of an output voltage and an output current of the DC/DC converter, and generating an initial phase-shift angle based on the input voltage and the transfer coefficients. The method further includes generating a related phase-shift angle based on at least one of the output voltage and the output current, and a threshold value. The method further includes adjusting the related phase-shift angle based on a comparison between one of the output voltage and a reference voltage, or the output current and a reference current.

In still another embodiment, a method of controlling a resonant power in a DC/DC converter comprises determining transfer coefficients of the DC/DC converter, and determining an input voltage of the DC/DC converter. The method further includes determining at least one of an output voltage and an output current of the DC/DC converter. The method further includes generating an initial phase-shift angle of the resonant power in a DC/DC converter based on the input voltage and the transfer coefficients. The method further includes determining a plurality of zero-voltage switching (ZVS) feedback currents of the resonant power in a DC/DC converter. The method further includes adjusting the initial phase shift angle based on a comparison between each ZVS feedback current to a respective ZVS reference current.

DETAILED DESCRIPTION

Referring now toFIG. 1, a block diagram of a wide input DC/DC resonant converter system100is illustrated according to an embodiment of the disclosure. According to at least one embodiment, the DC/DC converter system utilizes a series resonant converter (SRC) topology and a controlled rectifier (CR) to form a SRC-CR system. The DC/DC resonant converter system100is configured to reduce reactive power at the high input line of the converter while providing zero voltage switching (ZVS) assistance currents that achieves low-loss switching across a wide range of loads (i.e., light load to full load) and a wide range of input voltages. For example, the input voltage may be a low input voltage of approximately 385 Vdc, a nominal input voltage of approximately 560 Vdc, or a high input voltage of approximately 720 Vdc. The loads may range from light loads of about 0 W (watts) to about 5 W consumed, to high loads of about 1000 W to about 5000 W consumed.

The wide input DC/DC resonant converter system100includes a primary converter unit102, a controlled secondary rectifier unit, i.e., a controlled rectifier (CR)104, and a phase-shift controller106. The primary converter unit102includes a resonant tank circuit108and a plurality of primary switching units Q1-Q4. The resonant tank circuit108may include a split resonant tank circuit108, as further illustrated inFIG. 1. The split resonant tank circuit108includes a resonant capacitor Cr interposed between a first half winding unit Lr1/T1-1and a second half winding unit T1-2/Lr2. The first half and second half windings may have an inductance of approximately 2.5 microhenries (μH) for example.

The plurality of primary switching units (Q1-Q4) may be formed as semiconductor devices, such as a field effect transistor (FET), and may include a first set of FETs Q1,Q2, and a second set of FETs Q3, Q4to form a primary H-bridge circuit. The first set of FETs Q1,Q2form a first leg103of the primary H-bridge circuit, and the second set of FETs Q3, Q4for a second leg105of the primary H-bridge circuit. One end of the first half winding unit Lr1/T1-1may be connected to the source of FET Q1and the drain of the FET Q2, while the opposite end of the first half winding unit Lr1/T1-1may be connected to a first end of the resonant capacitor Cr. One end of the second half winding unit T1-2/Lr2may be connected to the opposite end of the resonant capacitor Cr, while the opposite end of the second half winding unit T1-2/Lr2may be connected to the source of FET Q3and the drain of the FET Q4. Each vertical leg, i.e., segment, of the H-bridge is selectively controlled via a respective FET among the plurality of FETs (Q1-Q4). The primary converter unit102may further include a plurality of clamping diodes (D1-D4) to clamp the voltage realized across the resonant capacitor Cr. The resonant capacitor may have a capacitance of approximately 0.01 μf for example.

The primary converter unit102operates according to a fixed frequency phase-shift modulation control. The primary FETs Q1,Q2are alternately switched with approximately a 50% duty cycle leaving only a short time “dead time” interval, for example 60 nanoseconds (ns). The FETs may be switched at a low frequency of approximately 600 kHz, a nominal frequency of approximately 750 kHz, or a high frequency of approximately 900 kHz. Referring toFIG. 2, the FET Q4is activated, i.e., turned on, with respect to FET Q1by a first phase-shift angle φ1. The FET Q3is delayed with respect to FET Q2by the same phase-shift angle φ1. The duty cycle of voltage (Vr) applied to the diagonal of the H-bridge circuit108(i.e., Vr=Va−Vb) increases in response to decreasing the phase-shift angle φ1. Accordingly, modulation of the phase-shift angle φ1results in pulse-width modulation (PWM) control of the output power. The output power (Po) may have a value, for example, of 3 kW.

The CR104includes a plurality of rectifier switching units Q5, Q6to reduce reactive power in the primary converter unit102. The rectifier switching units Q5, Q6may be formed from semiconductor devices such as FETs. The CR104further includes a controlled bridge110including a third leg and a fourth leg. The third leg comprises a first bridge diode (D8), and a diode (D5) connected to rectifier switching unit Q5to define a first unidirectional switching unit107. The fourth leg comprises a second bridge diode (D9), and a diode (D6) connected to rectifier switching unit Q6to define a second unidirectional switching unit109. Each of the first and second unidirectional switches107,109are configured to block the reverse voltage.

The controlled bridge110further includes a center-tapped secondary winding T1-3/T1-4and a center-tap diode (D7). An end of the secondary winding T1-3is connected between the first unidirectional switching unit107and the first bridge diode D8. An end of the secondary winding T1-4is connected between the second unidirectional switching unit109and the second bridge diode D9. The center-tap diode D7has an anode connected at the center of the secondary winding T1-3/T1-4, and a cathode commonly connected to the first and second switching units107,109. An output capacitor Comay be connected across the output of the CR104to filter noise from the output signal realized by the load (RL). The load resistance may be, for example, approximately 1.2 ohms (Ω), and the output power may be, for example, approximately 3 kW.

Based on the structure of the controlled bridge110described above, the third leg107and the fourth leg109may over-ride current flowing through the center-tapped secondary winding T1-3/T1-4. For example, when the first and second unidirectional switches107,109are deactivated, current flows through the center-tap diode D7. In response to activating at least one of the first and second unidirectional switches107,109, the effective primary impedance is increased, and current flowing through the center-tap diode D7and the center-tapped secondary winding T1-3/T1-4is reduced. The controlled bridge110, therefore, provides a feature of adjusting the turn ratio of the center-tapped secondary winding T1-3/T1-4to control the current flowing therethrough, thereby controlling the reactive power of the wide input DC/DC resonant converter system100. In one example, the turns ratio may be adjusted to provide a 2:1 input voltage range, for example. The ratio, however, is not limited to exactly a 2:1 ratio and may include values ranging therebetween.

According to at least one embodiment of the wide input DC/DC resonant converter system100, the CR104is controlled according to a second phase-shift angle φ2. The second phase-shift angle φ2delays conduction of the rectifier FETs Q5and Q6with respect to the individual FETs Q4and Q3of the second leg105. That is, the third leg of the controlled bridge110, which comprises the first unidirectional switching unit107, is phase-shifted with respect to Q3of the second leg105. The fourth leg of the controlled bridge110, which comprises the second unidirectional switching unit109, is phase shifted with respect to Q4of the second leg105.

In terms of the energy stored in the primary converter unit102, quality factor (Qf) of the resonant tank circuit108may be controlled on a cycle-by-cycle basis. For example, if the second phase-shift angle φ2=0, such that Q5is in phase with Q3and Q6is in phase with Q3, the full secondary winding T1-3/T1-4, i.e., both the first half and second half of the secondary winding, is conducting and the quality factor is high, for example Q(n)=approximately 0.24. During the fraction of the cycle when the second phase-shift angle φ2is greater than zero, one half of the secondary winding T1-3/T1-4does not conduct and the quality factor is low, for example Q(2n)=approximately 0.06, and the power drawn from the input source is reduced. Increasing the second-phase shift angle φ2proportionally to the input voltage reduces the reactive power circulating through the primary converter unit102at the high end of the input voltage range, for example approximately 720 Vdc. At the same time, even though a reduced reactive power is drawn from the input source, the primary converter unit102is capable of providing certain ZVS assistance currents to the primary FETs Q1-Q4. The operation of the wide input DC/DC resonant converter system100will be discussed in greater detail below.

The wide input DC/DC resonant converter system100also achieves a zero voltage switching-zero voltage current switching (ZVS-ZCS) switching method. More specifically, the wide input DC/DC resonant converter system100may be unidirectional, thereby inhibiting regenerative power. The primary converter unit102may operate according to ZVS, while the CR104operates with zero current switching (ZCS). Because voltage across secondary semiconductors has a high rate of change during switching transitions, losses caused by the discharge of switches' equivalent output capacitance will grow at high output voltages. Accordingly, applications corresponding to this topology may utilize an output voltage range of tens to low hundreds of volts, for example, unless switching units having low capacitance are used and the switching frequency is relatively low, for example, approximately 500 kHz.

Referring now toFIGS. 3 and 4, a diagram of waveforms showing the operating behavior and operating regions of the FETs included in the wide input DC/DC resonant converter system100operating at full power is illustrated according to at least one exemplary embodiment. Under nominal conditions, for example, an input voltage of approximately 560 VDC, a frequency of approximately 750 kHz and a full load of approximately 3 kW, primary FET Q4of the second leg of the primary converter unit102is delayed with respect to primary FET Q1of the first leg of the primary converter unit102by a first phase-shift angle φ1=34°. The primary FET Q3of the second leg is delayed with respect to primary FET Q2of the first leg by the same first phase-shift angle, i.e., φ1=34°. The rectifier FET Q5of the third leg of the controlled bridge110, however, is delayed with respect to the primary FET Q4of the second leg by a second phase-shift angle φ2=30°. The rectifier FET Q6of the fourth leg is also delayed with respect to the primary FET Q3of the second leg by the same second-phase shift angle, i.e., φ2=30°. It can be seen by examining the input current (Iin) waveform that during the time interval corresponding to the sum of the first and second phase-shift angles (φ1+φ2), the power flows back to the input source. Also during the interval of D7conduction, the primary converter unit102is coupled to the load with a reduced quality factor Q(2n)=0.06 because only one half of the secondary winding T1-3/T1-4conducts current, as illustrated inFIG. 4. Operation with lower Qfproduces lower output power and reduces the reactive power and circulating currents in the primary converter unit102.

Referring now toFIGS. 5 and 6, a diagram of waveforms showing the operating behavior and regions of the FETs included in the wide input DC/DC resonant converter system100at half power is illustrated according to at least one exemplary embodiment. The primary converter unit102operates according to the nominal input voltage (560 VDC) and nominal frequency (750 kHz) mentioned above. At half-load, i.e., 50% load of 1500 W, the first phase-shift angle φ1=51° and the second phase-shift angle φ2=30°. It has similar conduction patterns and waveforms, but with lower currents. The extended conduction interval for D7corresponds to the longer time interval for the low Q region and the shorter time interval for the high Q region.

Referring toFIGS. 7 and 8, a diagram of waveforms showing the operating behavior and operating regions of the FETs included in the wide range DC/DC resonant converter system100at low power is illustrated according to at least one embodiment. In this scenario, the wide range DC/DC resonant converter system100operates with a light load of 70 W (i.e., approximately 2.3% of the rated power) under the nominal input voltage (560 VDC) and nominal frequency (750 kHz). At light load, the first phase-shift angle φ1=118° and the second phase-shift angle φ2=30°, as further shown inFIGS. 7 and 8. Accordingly, the wide range DC/DC resonant converter system100achieves reduced currents. For clarity, the currents are scaled by a factor of ten as illustrated inFIGS. 7 and 8. The conduction interval of D7is further extended leaving a small fraction of the cycle time for the high Q operation. Even at this light load, the primary FETs Q1-Q4keep some negative current to maintain ZVS.

Referring again toFIG. 1, the phase-shift controller106may be in electrical communication with the primary converter unit102and the CR104to control the switching of the primary FETs (Q1-Q4) and the rectifier FETs (Q5and Q6), respectively. The wide range DC/DC resonant converter system100may employ phase-shift modulation (PSM) to generate the first phase-shift angle φ1, which is applied to the primary FETs (Q1-Q4). The CR104may employ a feed-forward PSM derived from the input voltage to generate the second phase-shift angle φ2. For example, the second phase-shift angle φ2may be generated according to the following algorithm:
0<Vin≦400Vφ2=0  (1)
400V<Vin≦720V φ2=A+k*Vin(2)
whereA=−75° andk=0.1875°/V  (3)

Accordingly, the second phase-shift angle lags, i.e., is delayed, with respect to the first phase-shift angle φ1. For example, applying the first and second phase-shift angles to the primary converter unit102and the CR104, respectively, causes Q5to lag behind Q4by the second phase-shift angle φ2, and causes Q6to lag behind Q3by the same angle, i.e., the second phase-shift angle φ2. Although at least one embodiment of the100uses a piecewise linear feed-forward function of the input voltage to generate the second phase-shift angle φ2, other methods may be used including, but not limited to, an independent feedback loop. Operation of the phase-shift controller106is described in greater detail below.

Referring now toFIG. 9, a diagram illustrates a second phase-shift angle corresponding to the CR unit104versus the input voltage according to an exemplary embodiment. For the function shown inFIG. 9, the input voltage breakpoint=400V and φ2max=60°. It is appreciated, however, that other values may be selected. Also, other independent variables including, but not limited to, the resonant tank currents and output power, may be included in this function to more precisely define the region of ZVS of the primary converter unit102. In addition, other function types including, but not limited to, polynomial functions and exponential functions, may be used instead of a piecewise linear one described above. An additional feedback loop may also be used to substitute or supplement the feed-forward described above to enable control of the second phase-shift angle φ2with increased accuracy.

Referring toFIG. 10, a diagram illustrates circuit transfer characteristics of a conventional resonant converter over a full range of input voltages. More specifically,FIG. 10illustrates three input voltages corresponding to the function of φ1(Vin) over full operating ranges of a conventional resonant converter with φ2fixed at 0°. As illustrated inFIG. 10, the conventional resonant converter operates efficiently only at the lowest input voltage (Vin=385 V). As the input voltage is increased, however, the conventional resonant converter draws in additional power that circulates in the series resonator converter unit. The added power returns to the input source, thereby generating energy losses.

Referring now toFIG. 11, a diagram illustrates the circuit transfer characteristics over a full range of input voltages of a wide input DC/DC resonant converter system100according to an exemplary embodiment of the disclosure. In contradistinction to the conventional resonant converter discussed above, the wide input DC/DC resonant converter system100significantly reduces excessive circulating power and improves efficiency at higher input voltages. That is, as the input voltage is increased, the CR104is controlled such that additional energy is inhibited from becoming stored in the resonant tank circuit108, thereby improving the overall efficiency of the DC/DC resonant converter system100over a wide input voltage range.

Referring now toFIG. 12, the phase-shift controller106is illustrated according to an exemplary embodiment. The phase-shift controller106may receive power from a bias power supply and may include a series resonant converter-controlled rectifier controller module112that determines the first and second phase-shift angles φ1, φ2. The series resonant converter-controlled rectifier controller module112may also generate one or more primary gate drive signals based on the first phase-shift angle φ1to drive a respective primary FET (Q1-Q4), and may generate one or more rectifier drive signals based on the second phase-shift angle φ2to drive a respective rectifier FET (Q5, Q6). A signal interface114may electrically communicate signals output from the phase-shift controller106to and/or from the primary converter unit102and/or the CR104.

The converter-rectifier module112may comprise a phase-shift logic network116and a phase-shift signal generator118. The phase-shift logic network116is configured to electronically calculate various parameters of the drive signal that drive the primary converter unit102and the CR104. For example, the phase-shift logic network116may include a digital control law (DCL) that determines the duty ratio value of gate signals to drive the FETs Q1-Q6based on reference voltage and current signals and/or feedback voltage and current signals. The phase-shift logic network116may further determine the first phase-shift angle and the second phase shift-angle.

The phase-shift signal generator118is configured to generate one or more converter control signals that drive the primary converter unit102and CR104and may be configured as a digital-to-analog (D/A) converter. The phase-shift signal generator118may include a digital pulse-width modulator and/or a digital phase-shift modulator to generate pulsed waveforms that control the FETs Q1-Q6at the duty ratio and phase-shift angles determined by the phase-shift logic network116. For example, the phase-shift signal generator118may generate a first pulse waveform that drives FETS Q1-Q4at a duty cycle according to the first phase-shift angle φ1, and may generate a second pulse waveform that drives FETS Q5and Q6at a duty cycle according to the second phase-shift angle φ2. The phase-shift signal generator118is also configured to generate one or more rectifier control signals that drive the CR104according to the second phase-shift angle φ2.

More specifically, the converter-rectifier module112has one or more feedback loops from the output. The one or more feedback loops may include, but are not limited to, a voltage feedback signal and a current feedback signal. It is appreciated that other feedback loops, for example, an output power feedback loop and/or current fold-back may be added if desired. The main loops may include two average feedback signals. For example, the feedback signals may include, but are not limited to, an average output voltage (Vo) and an average output current (Io). An additional inner loop injects the resonant tank currents into the main loops to improve dynamic characteristics of the converter system100. In addition to feedback signals, the phase-shift controller106receives second phase-shift angle φ2function definition signals and data describing the overall converter characteristics of the converter system100(e.g., start-up time, output over-voltage protection, current and power limits, etc.). The phase-shift controller106may also receive commands from a higher-level control layer and output status signals. As described above, the phase-shift controller106may operate the converter system100such that the primary converter unit102realizes minimum reactive power, while inherently generating assistance currents to the primary FETs Q1-Q4to achieve low-loss switching across a wide range of loads (i.e., light loads to full loads) and a wide range of input voltage. The phase-shift controller106, therefore, may operate the100at a wide input voltage range and at high efficiency.

Referring toFIG. 13, a phase-shift controller106is illustrated according to another exemplary embodiment. The phase-shift controller106includes a converter control module120and a separate rectifier control module122. The converter control module120includes a primary logic network124and a primary phase-shift signal generator126. The primary logic network124determines the first phase-shift angle φ1, and the primary phase-shift signal generator126generates one or more primary gate drive signals based on the first phase-shift angle φ1to drive a respective primary FET (Q1-Q4). The rectifier control module122includes a CR logic network128and a CR phase-shift signal generator130. The CR logic network128determines the second phase-shift angle φ2, and the CR phase-shift signal generator130may generate one or more rectifier drive signals based on the second phase-shift angle φ2to drive a respective rectifier FET (Q5, Q6).

More specifically, the phase-shift controller106illustrated inFIG. 13includes two independent channels: a first dual-loop channel controlling the output, and a second ZVS control channel with two separate closed loops corresponding to a first set of primary FETs (Q1, Q2) and a second set of primary FETs (Q3, Q4). The second channel receives data describing the ZVS current reference, the minimum currents required for maintaining ZVS of the primary FETs Q1-Q4. The data may be provided, for example, by a higher level control layer. Different ZVS currents may be required by the two legs of the H-bridge circuit included with the primary converter unit102.

Primary drive currents (IQ1-IQ4) are digitized by first and second analog-to-digital converters (ADC7and ADC8) and subtracted from the ZVS current reference signals via a subtractor. The resultant signal is processed by a digital control law (DCL2). The control signal is input to the CR digital pulse width modulation (DPWM) and digital phase-shift modulation (DPSM) blocks to generate gate drive signals for the rectifier FETs Q5and Q6. As described in detail above, the phase-shift controller106may receive data describing the overall converter characteristics of the converter system100(e.g. start-up time, output over-voltage protection, current and power limits, etc.) A signal interface114may also electrically communicate signals output from the phase-shift controller106to and/or from the primary converter unit102and/or the CR104. Accordingly, the phase-shift controller may operate the converter system100with a relatively narrow input voltage range. In this embodiment, the phase-shift controller maximizes ZVS assistance currents and, as a byproduct, inherently reduces the reactive power realized by the primary converter unit102. It is appreciated that embodiments ofFIGS. 12 and 13do not contradict each other because reducing reactive power and maintaining ZVS may be achieved using the same variable i.e., the second phase-shift angle φ2.

Referring now toFIG. 14, a flow diagram illustrates a method of operating a wide input DC/DC resonant converter system according to an embodiment of the disclosure. At operation1400, output voltage and current values of the wide input DC/DC resonant converter system are determined. It is appreciated that other values of the wide input DC/DC resonant converter system may be determined including, but not limited to, output power, phase-shift angle transfer function coefficients, resonant tank current values, average current values, average voltage values, zero voltage switching current reference values, and zero voltage switching feedback current values. At operation1402, a first phase-shift angle φ1and a second phase-shift angle φ2are determined. At operation1404, a first gate drive signal according to the first phase-shift angle φ1is generated and a second gate drive signal according to the second phase-shift angle φ2is generated. Accordingly, the switching elements of the secondary rectifier unit are lagged via the second phase-shift angle φ2. That is, the secondary rectifier unit is controlled to operate at a delay with respect to the primary converter unit using the second phase-shift angle. At operation1406, a primary converter unit included in the wide input DC/DC resonant converter system is driven according to the first gate drive signal, and the method ends. According to one embodiment, for example, semiconductor switching elements, e.g., FETs, of the primary converter unit are switched according to the first phase-shift angle φ1. A secondary rectifier unit, i.e., a controlled rectifier, included in the wide input DC/DC resonant converter system is driven according to the second gate drive signal. Therefore, semiconductor switching elements of the controlled rectifier may be switched according to the second phase-shift angle φ2.

Turning now toFIG. 15, a flow diagram illustrates a method of regulating power to a load according to an exemplary embodiment. At operation1500, a controller for regulating power to the load is enabled. At operation1502, input signals are generated. The input signals may include, but are not limited to, signals indicative of transfer function coefficients (A and k) and signals defining digital control law. At operation1504, state variables are initialized. At operation1506, the SRC-CR is enabled. At operation1508, state variables are input to the controller. The state variables may include, but are not limited to, input voltage (Vin), output voltage (Vo), output current (Io), a first tank feedback current (ILr1) and a second tank feedback current (ILr2). At operation1510, an initial phase-shift angle, for example, (φ2) is determined.

Turning to operation1514, a determination is made whether to adjust the signals representing a related phase-shift angle, for example (φ1), based on a comparison between the Vo and Vref, or Io and Iref. If Vo or Io does not satisfy, (e.g., mismatches) the reference value, the signals representing φ1are adjusted at operation1516, and the adjusted signals are input to the controller at operation1518. At operation1520, the PWM and PSM signals are generated according to the adjusted φ1input signals. Accordingly, the SRC-CR state variables are monitored at operation1522, and method returns to operation1508where state variables are input to the controller.

Turning again to operation1514, if Vo or Io satisfies, (e.g., matches) the reference value, then the signals representing φ1are not adjusted at operation at operation1524, and the non-adjusted signals are input to the digital control law block at operation1526. Accordingly, PWM and PSM signals are generated at operation1528. At operation1530, the SRC-CR state variables are monitored, and the power is regulated to the loads accordingly at operation1532. In at least one embodiment, the system may then return to operation1508to deal with any possible disturbances or changes in the input state variables.

Referring now toFIGS. 16A-16B, a flow diagram illustrates another method of regulating power to a load according to an exemplary embodiment. At operation1600, a controller for regulating power to the load is enabled. At operation1602, input signals are generated. The input signals may include, but are not limited to, signals indicative of transfer function coefficients (A and k) and signals defining digital control law. At operation1604, state variables are initialized, and the SRC-CR is enabled at operation1606. At operation1608, state variables are input to the controller. The state variables may include, but are not limited to, input voltage (Vin), output voltage (Vo), output current (Io), a first tank feedback current (ILr1), a second tank feedback current (ILr2), and primary drive currents IQ1-IQ4. At operation1610, an initial phase-shift angle (φ2) is determined.

At operation1612, the ZVS feedback current signals corresponding to Q1-Q4are compared to the ZVS reference currents signals, respectively. If the ZVS feedback currents do satisfy (e.g., match) the ZVS reference current signals, the signals representing φ2are not adjusted at operation1614. At operation1616, the non-adjusted signals are input to the controller as digital control law, and a PWM and PSM signals corresponding to φ2are generated at operation1618. At operation1620, the primary drive currents IQ1-IQ4are monitored, and the method returns to operation1608to input the state variables.

Turning again to operation1612, if the ZVS feedback currents do not satisfy, (i.e., mismatch) the ZVS reference current signals, then the signals representing φ2are adjusted at operation1622. The adjusted signals are then input to the controller as digital control law at operation1624. At operation1626, the PWM and PSM signals corresponding to φ2are generated, and the primary drive currents IQ1-IQ4are monitored at operation1628.

Turning now to operation1630, a related phase-shift angle (φ1) is determined using the output voltage or the output current and a respective reference value. At operation1632, a determination is made whether to adjust the signals representing φ1based on a comparison between the Vo and Vref, or Io and Iref. If Vo or Io does not satisfy (e.g., mismatches) the reference value, the signals representing φ1are adjusted at operation1634, and the adjusted signals are input to the controller at operation1636. At operation1638, the PWM and PSM signals are generated according to the adjusted φ1input signals. Accordingly, the SRC-CR state variables are monitored at operation1640, and method returns to operation1608where state variables are input to the controller.

Turning again to operation1632, if Vo or Io satisfies (e.g., matches) the reference value, then signals representing φ1are not adjusted at operation at operation1642, and the non-adjusted signals are input to the digital control law block at operation1644. Accordingly, PWM and PSM signals are generated at operation1646. At operation1648, the SRC-CR state variables are monitored, and the power is regulated to the loads accordingly at operation1650. In at least one embodiment, the system may then return to operation1608to deal with any possible disturbances or changes in the input state variables.

As will thus be appreciated, among the technical features discussed above, at least one embodiment of the inventive teachings provides a wide range DC/DC resonant converter system that reduces reactive power at high input voltage with dual-angle control of a primary convert and a secondary rectifier using first and second phase-shift angles, respectively. In addition, at least one embodiment provides a wide range DC/DC resonant converter system including a primary converter unit that operates using zero voltage switching (ZVS), and a secondary controlled rectifier that operates using zero current switching (ZCS). Further, at least one embodiment of the inventive teachings provides a wide range DC/DC resonant converter system that generates ZVS assistant currents of a primary converter unit using two independent closed loop channels such that reactive power at high input voltage may be automatically reduced.