Package structure and method of manufacturing the same

A package structure and a method of forming the same are provided. The package structure includes a first die, an encapsulant, a first RDL structure, and a conductive terminal. The encapsulant is aside the first die, encapsulating sidewalls of the first die. The first RDL structure is on the first die and the encapsulant. The conductive terminal is electrically connected to first die through the RDL structure. The first RDL structure comprises a first polymer layer and a first RDL, the first polymer layer comprises a non-shrinkage material and a top surface of the first polymer layer is substantially flat.

BACKGROUND

The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from continuous reductions in minimum feature size, which allows more of the smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than previous packages. Some smaller types of packages for semiconductor components include quad flat packages (QFPs), pin grid array (PGA) packages, ball grid array (BGA) packages, and so on.

Currently, integrated fan-out packages are becoming increasingly popular for their compactness.

DETAILED DESCRIPTION

FIG. 1AtoFIG. 1Hare schematic cross-sectional views illustrating a forming method of a package structure according to a first embodiment of the disclosure.FIG. 4is a schematic cross-sectional view illustrating a RDL according to some embodiments of the disclosure.

Referring toFIG. 1A, a carrier10is provided. The carrier10may be a glass carrier, a ceramic carrier, or the like. In some embodiments, the carrier10has a de-bonding layer11formed thereon. The de-bonding layer11is formed by, for example, a spin coating method. In some embodiments, the de-bonding layer11may be formed of an adhesive such as an Ultra-Violet (UV) glue, a Light-to-Heat Conversion (LTHC) glue, or the like, or other types of adhesives. The de-bonding layer11is decomposable under the heat of light to thereby release the carrier10from the overlying structures that will be formed in subsequent steps.

In some embodiments, a die20aand a die20bare attached side by side to the de-bonding layer11over the carrier10through an adhesive layer12such as a die attach film (DAF), silver paste, or the like. In some embodiments, the die20aand the die20bmay be any one of a system-on-chip (SoC) device, a memory device, or any other suitable types of devices. In some embodiments, the die20aand the die20bmay respectively be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, a memory chip or the like. The die20aand the die20bmay be the same types of dies or the different types of dies. In some embodiments, the two dies20aand20bare two small die partitions with different function of a larger single die. The size (refers to the height and/or the width) of the two dies20aand20bmay be the same or different. In some embodiments, a gap21is existed between the two dies20aand20b. The number of the dies attached to the carrier10is not limited to that is shown inFIG. 1A. In some other embodiments, one die or more than two dies are attached to the carrier10.

In some embodiments, the two dies20aand20bhave similar structures. For the sake of brevity, the die20ais taken for example. The die20aincludes a substrate13a, a pad14a, a passivation layer15a, connectors19aand a protection layer16a.

In some embodiments, the substrate13ais made of silicon or other semiconductor materials. Alternatively or additionally, the substrate13aincludes other elementary semiconductor materials such as geimanium, gallium arsenic, or other suitable semiconductor materials. In some embodiments, the substrate13may further include other features such as various doped regions, a buried layer, and/or an epitaxy layer. Moreover, in some embodiments, the substrate13ais made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Furthermore, the substrate13amay be a semiconductor on insulator such as silicon on insulator (SOI) or silicon on sapphire.

The pads14amay be a part of an interconnection structure (not shown) and electrically connected to the devices (not shown) formed on the substrate13a. In some embodiments, the devices may be active devices, passive devices, or a combination thereof. In some embodiments, the devices are integrated circuit devices. The devices16are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or the like. The passivation layer15ais formed over the substrate13aand covers a portion of the pads14a. A portion of the pads14ais exposed by the passivation layer15aand serves as an external connection of the die20a. The passivation layer15aincludes an insulating material such as silicon oxide, silicon nitride, polymer, or a combination thereof. The polymer includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like, for example.

The protection layer16ais located over the passivation layer15aand aside the connectors19ato cover the sidewalls of the connectors19a. The protection layer16amay be formed of a material the same as or different from that of the passivation layer15a.

The connectors19aare formed on and electrically connected to the pads14aexposed by the passivation layer15a. The connectors19aare formed on and electrically connected to the pads14anot covered by the passivation layer15a. The connector19aincludes solder bumps, gold bumps, copper bumps, copper posts, copper pillars, or the like. The cross section shape of the connector19amay be T-shaped, square or rectangle, but the disclosure is not limited thereto. The sidewalls of the connector19amay be straight or inclined. In some embodiments, the connector19aincludes a seed layer17aand a conductive post18a. The seed layer17ais a copper seed layer or other suitable metal seed layer. In some embodiments, the seed layer17ais a composite layer including titanium and copper. The conductive post18aincludes copper, for example. In some embodiments, the seed layer17acovers and surrounds the sidewalls and the bottom surfaces of the conductive posts18a, and is located between the conductive posts18aand the protection layer16a, between the conductive posts18aand the passivation layer15a, and between the conductive posts18aand the pads14a. That is, the conductive post18ais separated from the protection layer16aby the seed layer17atherebetween. In some embodiments of the disclosure, the connector19amay be formed by the method described as below.

FIG. 3AtoFIG. 3Fare schematic cross-sectional views illustrating a forming method of the connectors19aand the protection layer16aof the die20aaccording to some embodiments of the disclosure.

Referring toFIG. 3AandFIG. 3B, the passivation layer15awith a plurality of openings OP1is formed on the pads14aand the substrate13a. The openings OP1expose portions of the top surface of the pads14a. The passivation layer15amay be formed by firstly forming a passivation material layer over the substrate13aand the pads14a, thereafter, a laser drilling process or exposure and development processes is/are performed to remove a portion of the passivation material layer on the pads14a, so as to form the passivation layer15ahaving a plurality of openings OP1.

A protection material layer16is formed on the passivation layer15aand on the pads14a. The protection material layer16covers the passivation layer15a, and fills into the openings OP1to cover the exposed top surfaces of the pads14a. The material of the protection material layer16may be the same as or different from the material of the passivation layer15a. In some embodiments, the protection material layer16includes a non-shrinkage material. The non-shrinkage material includes, epoxy, phenol, copolymer, or a combination thereof. In some embodiments, the copolymer is formed through a cross-linking reaction between a pre-copolymer and photo acid. The forming method of the protection material layer16includes a spin coating process and a soft bake process, for example. In some embodiments, the temperature of the soft bake process ranges from 80° C. to 115° C. Herein, non-shrinkage material refers to a material substantially does not shrink or the shrinkage rate thereof is very low after a curing process is performed in subsequent process. The shrinkage rate of the non-shrinkage material is less than 2%, for example. In some embodiments, the shrinkage rate of the non-shrinkage material is 0, that is, the non-shrinkage material does not shrink.

Referring toFIG. 3BandFIG. 3C, the protection material layer16is patterned to form a protection layer16awith a plurality of openings OP2, and the openings OP1are exposed. In some embodiments, the openings OP2and the openings OP1are holes, exposing portions of the top surfaces of the pads14a. The openings OP2are located over and in spatial communication with the openings OP1. In other words, the openings OP2and the openings OP1are partially overlapped when projected to a top surface of the substrate13a. The sidewalls of the openings OP1and OP2may be straight or inclined. The width W2of the opening OP2may be larger than or equal to the width W1of the opening OP1.

Referring toFIG. 3BandFIG. 3C, in some embodiments, the patterning method of the protection material layer16includes exposure and development processes, and a curing process (or referred as hard bake process) is further performed to cure the protection layer16a. In some embodiments, the temperature of the curing process is higher than the temperature of the soft bake process, and ranges from 170° C. to 230° C. In some embodiments, the temperature of the curing process is higher than 170° C. The shrinkage rate of the protection layer16amay be calculated according to Equation 1:
shrinkage rate=|T1−T2|/T1×100,
wherein T1refers to the thickness of the protection material layer16after the soft bake process is performed, T2refers to the thickness of the protection layer16aafter the curing process is performed. In the embodiments in which the protection material layer16is formed of the non-shrinkage material, the shrinkage rate of the non-shrinkage material is in a range of 0 to 2%. In other word, the ratio of T2to T1ranges from 98% to 100%.

Referring toFIG. 3D, a seed layer17is formed over the substrate13aby a physical vapor deposition (PVD) process such as a sputtering process. In some embodiments, the seed layer17is a conformal seed layer. That is, the seed layer17has a substantially equal thickness extending along the region on which the seed layer17is formed. In detail, the seed layer17covers the top surface of the protection layer16a, and fills into the openings OP2and OP1to cover the sidewalls and bottom surfaces of the openings OP2and OP1. In other words, the seed layer17covers the top surface and sidewalls of the protection layer16a, the sidewalls and a portion of the top surface of the passivation layer15a, and portions of the top surfaces of the pads14a. The seed layer17is in electrical contact with the top surface of the pad14a.

Referring toFIG. 3E, a conductive layer18is then formed on the seed layer17by, for example, an electroplating process. The conductive layer18covers the top surface of the seed layer17, and fills into the openings OP1and OP2, so as to cover the sidewalls and bottom surfaces of the seed layer17.

Referring toFIG. 3EandFIG. 3F, a planarization process is performed to remove the seed layer17and the conductive layer18over the top surface of the protection layer16a, and the seed layer17aand the conductive post18ain the openings OP1and OP2are remained. The seed layer17aand the conductive post18aform the connector19a. The planarization process includes a polishing or grinding process, such as a chemical mechanical polishing (CMP) process. In some embodiments, the top surface of the protection layer16a, the top surface of the seed layer17aand the top surface of the conductive post18aare substantially coplanar with each other.

Referring toFIG. 3F, the die20ais thus completed. In this embodiment, since the protection layer16ais formed before the connector19ais formed, and the protection layer16ais formed of a non-shrinkage material, the deformation of the protection layer16aor bubble issue that may occur in the protection layer16aare effectively avoided.

Referring back toFIG. 1A, similar to the die20a, the die20bincludes a substrate13b, a pad14b, a passivation layer15b, and a connector19b. The connector19bincludes a seed layer17band a conductive post18b. In some embodiments, the structure and the forming method of the die20bmay be substantially the same as those of the die20a, but the disclosure is not limited thereto.

In some embodiments, the structure of the die20bis similar to that of the die20a, and different from the die20ain that, the sidewalls of the conductive post18bin the opening of the protection layer16bis not covered by the seed layer17b, but is in contact with the protection layer16b. The die20bmay be formed by a method the same as or different from the forming method of the die20adescribed above.

Referring toFIG. 1B, an encapsulant material layer22is formed on the carrier10and the two dies20aand20bby a suitable fabrication technique such as spin-coating, lamination, deposition, molding process or similar processes. The encapsulant material layer22encapsulates sidewalls and top surfaces of the dies20aand20b. The material of the encapsulant material layer22may be the same as or different from the material of the protection layer16a. In some embodiments, the encapsulant material layer22includes a molding compound, a molding underfill, a resin such as epoxy, a combination thereof, or the like. In some other embodiments, the encapsulant21includes a photo-sensitive material such as PBO, PI, BCB, a combination thereof, or the like, which may be easily patterned by exposure and development processes or laser drilling process. In alternative embodiments, the encapsulant21includes nitride such as silicon nitride, oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like.

In yet another embodiment, the encapsulant material layer22includes a composite material including a polymer and a plurality of fillers22′. The filler22′ may be a single element, a compound such as nitride, oxide, or a combination thereof. The fillers22′ may comprise silicon oxide, aluminum oxide, boron nitride, alumina, silica, and the like, for example. The cross-section shape of the filler22′ may be circle, oval, or any other shape. The particle size of the filler22′ ranges from 2 μm to 30 μm, for example. In some embodiments, the particle size is referred to the average particle size D50. In some embodiments, the filler22′ is a hollow filler, but the disclosure is not limited thereto. In some other embodiments, the filler22′ may be a solid filler.

Referring toFIG. 1BandFIG. 1C, a planarization process is performed to remove the encapsulant material layer22over the top surfaces of the dies20aand20b, and an encapsulant22ais formed. The planarization process includes a polishing or grinding process, such as a CMP process. In some embodiments, the top surface of the encapsulant22aand the top surfaces of the dies20aand20bare substantially coplanar with each other.

Referring toFIG. 1C, in some embodiments, one or more pits (or referred as recesses)23may be formed in the encapsulant22aafter the planarization process. In some embodiments, the height H1of the pit23ranges from 10 μm to 30 μm.

Still referring toFIG. 1BandFIG. 1C, in some embodiments in which the encapsulant material layer22includes fillers22′, some of fillers22′ are completely removed, some of the fillers22′ are partially removed during the planarization process. In the embodiments in which the filler22′ is a hollow filler and partially removed, the top of the hollow filler22′ may be removed. In other word, the top of the filler22a′ is open and a filler22a′ having a pit23is formed. The height H1of the pit23is related to the particle size of the filler22′.

Referring toFIG. 1D, a polymer layer PM1is formed on the encapsulant22aand the two dies20aand20b. The polymer layer PM1has a plurality of openings24. In some embodiment, the openings24are via holes, exposing the top surfaces of the connectors19aof the die20aand the top surfaces of the connectors19bof the die20b. In some embodiments, the cross-section shape of the opening24is square, rectangle, trapezoid, inverted trapezoid, or the like. The base angle of the opening24is an acute angle, a right angle, or an obtuse angle, for example.

The material of the polymer layer PM1may be the same as or different from the material of the protection layer16aand the material of the encapsulant22a. In some embodiments, the polymer layer PM1includes a non-shrinkage material. The non-shrinkage material includes, epoxy, phenol, copolymer, or a combination thereof. In some embodiments, the copolymer is formed through a cross-linking reaction between a pre-copolymer and photo acid.

In some embodiments, the polymer layer PM1may be formed by forming a polymer material layer on the encapsulant22aand the dies20aand20bby a spin coating process and a soft bake process. In some embodiments, the temperature of the soft bake process ranges from 80° C. to 115° C. Thereafter, the polymer material layer is patterned by, for example, exposure and development processes, and a curing process (or referred as hard bake process) is performed to cure the polymer layer PM1. In some embodiments, the temperature of the curing process is higher than the temperature of the soft bake process. In some embodiments, the temperature of the curing process ranges from 170° C. to 230° C. In some embodiments, the temperature of the curing process is higher than 170° C. The shrinkage rate of the polymer layer PM1after the curing process may be calculated by a method similar to the calculation method of the protection layer16a. In some embodiments, the shrinkage rate of the polymer layer PM1ranges from 0 to 2%. That is to say, the ratio of the thickness of the polymer layer PM1to the thickness of the polymer material layer ranges from 98% to 100%.

Still referring toFIG. 1D, the polymer layer PM1fills into the pits23of the encapsulant22a. In this embodiment, since the polymer layer is formed of a non-shrinkage material, the problem of pits or recesses that may occur in the polymer layer PM1during the curing process due to the pits23in the encapsulant22aare effectively avoided or reduced, and the polymer layer PM1may have a substantially flat top surface. In some embodiments, the surface roughness Ra of the polymer layer PM1is less than 0.2 μm.

Referring to the enlarged view of the polymer layer PM1and the encapsulant22ainFIG. 1D, the polymer layer PM1is extending into the encapsulant22aalong a first direction D1, and is laterally surrounded by the encapsulant22aalong a second direction D2. The first direction D1is a direction parallel with the normal line of the top surface of the die20aor20b. The second direction D2is a direction parallel with the top surface of the die20aor20b. Specifically, the polymer layer PM1is filled in the pit23of the hollow fill22a′ whose top is open. The polymer layer PM1in the pit23is laterally located aside the die20aor20b. In some embodiments, the polymer layer PM1has a recess23′ over the pit23. The height H2of the recess23′ is much less than the height H1of the pit23. The height H2of the recess23′ ranges from 0 to 0.2 μm, 0 to 0.1 μm or 0 to 50 nm, for example. It is noted that the height H2is 0 refers that no recess is formed in the polymer layer PM1. In some embodiments, the height H2of the recess23′ ranges from 0.1 μm to 0.2 μm. The width W4of the recess23′ ranges from 10 μm to 30 μm. The aspect ratio (that is, the ratio of height H2to width W4) of the recess23′ ranges from 0.01 to 0.02. In some embodiments, the height H1of the pit23ranges from 10 μm to 30 μm. The width W3of the pit23ranges from 10 μm to 30 μm. The aspect ratio (that is, the ratio of height H1to width W3) of the pit23ranges from 0.3 to 1. In some embodiments, the width W4and the width W3respectively refer to the top width of the recess23′ and the top width of the pit23.

Referring toFIG. 1E, a seed material layer25ais formed on the polymer layer PM1by, for example, a sputtering process. The seed layer25is a copper seed layer or other suitable metal seed layer. In some embodiments, the seed layer25is a composite layer including titanium and copper. In some embodiments, the seed material layer25ais conformal with the polymer layer PM1. Thereafter, a photoresist PR is formed on the seed material layer25a. The photoresist PR has a plurality of openings40. In some embodiments, the openings40are trenches, exposing the seed material layer25ain the openings24, and a portion of the seed material layer on the top surface of the polymer layer PM1. The conductive layer26is then formed on the seed material layer25aexposed by the openings40of the photoresist PR through, for example, an electroplating process. The conductive layer26includes copper or other suitable metals, for example.

Referring toFIG. 1EandFIG. 1F, the photoresist PR is stripped, and the seed material layer25anot covered by the conductive layer26is removed by an etching process, and the seed layer25underlying the conductive layer26is formed.

Referring toFIG. 1F, the conductive layer26and the underlying seed layer25form a redistribution layer RDL1. The redistribution layer RDL1is on the polymer layer PM1and on the two dies20aand20b. The redistribution layer RDL1fills into the openings24to be in electrical contact with the connectors19aand19b. Referring toFIG. 1F, in some embodiments, the redistribution layer RDL1includes a plurality of vias V and a plurality of traces T connected to each other. The via V is formed of the seed layer25and the conductive layer26in the opening24of the polymer layer PM1, the top (or topmost) surface of the via V is substantially coplanar with the top surface of the polymer layer PM1. The trace T is formed of the seed layer25and the conductive layer26on the top surface of the polymer layer PM1. The via V penetrates trough the polymer layer PM1to be in electrical contact with the top surface of the connector19a/19b. The trace T is extending on the top surface of the polymer layer PM1, and is electrically connected to the connectors19a/19bthrough the via V.

Referring toFIG. 4which is an enlarged view of the RDL1according to some embodiments of the disclosure, in some embodiments, the redistribution layer RDL1has a top surface60and a top surface61. In some embodiments, the top surface60and the top surface61are not coplanar with each other. The top surface60is lower than the top surface of the polymer layer PM1, and the top surface61is higher than the top surface of the polymer layer PM1, but the disclosure is not limited thereto. In some embodiments, the sidewalls of the via V may be straight or inclined. In some embodiments, the sidewalls of the via V is parallel to the normal line of the top surface of the die20a/20b. The base angle α of the via V is a right angle, but the disclosure is not limited thereto. In some other embodiments, the base angle α of the via V may be an acute angle, or an obtuse angle. The base angel α may be in a range of 85° to 90°, 90° to 92°, or 90° to 105°, for example. In some embodiments, the top width TCD of the via V equals to the bottom width BCD of the via V. In some embodiments, the top surface of the via V is not flat. The via V has a recess27within the opening24of the polymer layer PM1. In some embodiments, the recess27may have an arced surface, but the disclosure is not limited thereto. The height Δz of the recess27ranges from 2 μm to 3 μm, or 1 μm to 3 μm, for example. Herein, the top width TCD of the via V refers to the distance between the end point A and the end point B of the topmost surface41of the via V. The height Δz of the recess27refers to the height difference between the topmost surface41of the via V to the bottommost point of the recess27.

Referring toFIG. 1G, polymer layers PM2, PM3, PM4and redistribution layers RDL2, RDL3, RDL4are formed on the polymer layer PM1and the redistribution layer RDL1. The redistribution layer RDL2penetrates through the polymer layer PM2and is electrically connected to the redistribution layer RDL1. The redistribution layer RDL3penetrates through the polymer layer PM3and is electrically connected to the redistribution layer RDL2. The redistribution layer RDL4penetrates through the polymer layer PM4and is electrically connected to the redistribution layer RDL3. The materials and the forming methods of the polymer layers PM2, PM3, PM4may be similar to or different from those of the polymer layer PM1. In some embodiments, the polymer layers PM2, PM3, PM4include non-shrinkage materials substantially the same as the material of the polymer layer PM1, but the disclosure is not limited thereto. The structure, materials and the forming methods of the redistribution layers RDL2, RDL3, RDL4may be similar to or different from those of the redistribution layer RDL1. For the sake of the brevity, the seed layers and the conductive layers in redistribution layers RDL1, RDL2, RDL3, RDL4are not shown specifically inFIG. 1F. Similarly, the redistribution layers RDL2, RDL3, RDL4respectively include vias V and traces T. The vias V penetrates through the polymer layers PM1, PM2, PM3and PM4to connect the traces T of the redistribution layers RDL1, RDL2, RDL3and RDL4, and the traces T are respectively located on the polymer layers PM1, PM2, PM3and PM4, and are respectively extending on the top surface of the polymer layers PM1, PM2, PM3and PM4.

The polymer layers PM1, PM2, PM3, PM4and the redistribution layers RDL1, RDL2, RDL3, RDL4are stacked alternately, and form a redistribution layer (RDL) structure28. In some embodiments, the RDL structure28is located at a front side (that is, a side close to the connectors19aand19b) of the dies20aand20b, and is referred as a front side RDL structure. In some embodiments, the die20aand the die20bare electrically connected to each other through the RDL structure28.

In some embodiments, the redistribution layer RDL4is the topmost redistribution layer of the RDL structure28, and is also referred as an under-ball metallurgy (UBM) layer for ball mounting.

Thereafter, a plurality of connectors30are formed over and electrically connected to the redistribution layer RDL4of the RDL structure28. In some embodiments, the connectors30are referred as conductive terminals. In some embodiments, the connectors30may be ball grid array (BGA) connectors, solder balls, controlled collapse chip connection (C4) bumps, or a combination thereof. In some embodiments, the material of the connector30includes copper, aluminum, lead-free alloys (e.g., gold, tin, silver, aluminum, or copper alloys) or lead alloys (e.g., lead-tin alloys). The connector30may be formed by a suitable process such as evaporation, plating, ball dropping, screen printing and reflow process, a ball mounting process or a C4 process. In some embodiments, metal posts or metal pillars may further be formed between the redistribution layer RDL4and the connectors30. The connectors30are electrically connected to the two dies20aand20bthrough the RDL structure28.

Referring toFIG. 1GandFIG. 1H, the carrier10is released with the de-bonding layer11decomposed under the heat of light. The adhesive layer12may be optionally removed or remained.

Still referring toFIG. 1H, a package structure50ais thus completed. The package structure50aincludes two dies20aand20b, the encapsulant22a, the RDL structure28, and the connectors30. The encapsulant22amay include pits23therein. The protection layer16a/16bof the die20a/20band the polymer layers PM1, PM2, PM3, PM4include a non-shrinkage material, and have substantially flat top surfaces.

FIG. 2AtoFIG. 2Fare schematic cross-sectional views illustrating a method of forming a package structure according to a second embodiment of the disclosure. The second embodiment differs from the first embodiment in that a back side RDL structure and a plurality of through integrated fan-out vias (TIVs) are further formed.

Referring toFIG. 2A, a carrier10is provided. A de-bonding layer11is formed on the carrier10. The materials of the carrier10and the de-bonding layer11are similar to those in the first embodiment, which is not described again.

A RDL structure35is formed on the carrier10. In some embodiments, the RDL structure35includes polymer layers PM1′, PM2′, PM3′ and the redistribution layer RDL1′. The redistribution layer RDL1′ includes vias V′ and traces T′. The traces T′ are extending on the top surface of the polymer layer PM1′ and surrounded by the polymer layer PM2′. The via V′ penetrates through the polymer layer PM3′ to connect to the traces T′. In some embodiments, the top surface of the vias V′ are substantially coplanar with the top surface of the polymer layer PM3′, but the disclosure is not limited thereto. In some embodiments, the sidewalls of the via V′ and the sidewalls of the trace T′ may be straight or inclined.

In some embodiments, the polymer layers PM1′, PM2′, PM3′ respectively include a non-shrinkage material. The non-shrinkage material includes, epoxy, phenol, copolymer, or a combination thereof. In some embodiments, the copolymer is formed through a cross-linking reaction between a pre-copolymer and photo acid. The material of the polymer layer PM1′, PM2′, PM3′ may be the same as or different from the material of the polymer layer PM1described in the first embodiment. The materials of the polymer layers PM1′, PM2′, PM3′ may be the same or different. In some embodiments, the polymer layer PM3′ is the topmost polymer layer of the RDL structure35, and includes a non-shrinkage material, the polymer layers PM1′ and PM2′ may not include a non-shrinkage material. That is to say, at least the polymer layer PM3′ is formed of non-shrinkage material.

Since at least the polymer layers PM3′ is formed of non-shrinkage material, the top surface of the polymer layer PM3′ is substantially flat. In some embodiments, the surface roughness Ra of the polymer layer PM3′ is less than 0.2 μm. In some embodiments, as shown in the enlarged view of the top surface of the polymer layer PM3′, the polymer layer PM3′ may have a recess31, the height H3of the recess31is less than 0.2 μm, less than 0.1 μm, or less than 50 nm. In some embodiments, the height H3may equal to 0, that is to say, no recess is formed in the polymer layer PM3′.

A plurality of through integrated fan-out vias (TIVs)29are formed on the RDL structure35. The TIVs29are formed on the vias V′, so as to electrically connect to the RDL structure35. In some embodiments, the TIVs29include copper, nickel, solder, alloys thereof, or the like. In some embodiments, the TIV29includes a seed layer and a conductive layer formed thereon (not shown). The seed layer is, for example, a titanium or/and copper composited layer. The conductive layer is, for example, a copper layer. An exemplary forming method of the TIVs29includes forming a photoresist layer such as a dry film resist on the RDL structure35. Thereafter, openings (or referred as holes) are formed in the photoresist layer, the openings expose the top surfaces of the vias V′, and a portion of the top surface of the polymer layer PM3′, and the TIVs29are then formed in the openings by electroplating. In some other embodiments, the TIVs29further include a barrier layer (not shown) under the seed layer to prevent metal diffusion. The material of the barrier layer includes, for instance, metal nitride such as titanium nitride, tantalum nitride, or a combination thereof.

In some embodiments, the via V′ and the TIV29may be formed simultaneously, and may be formed by method described as below. In some embodiments, the polymer layer PM3′ including a plurality of openings43are formed on the polymer layer PM2′. The openings43are via holes, exposing a portion of the top surface of the trace T′. The polymer layer PM3′ may be formed by forming a polymer material layer on the polymer layer PM2′ and the trace T′ through, for example, a spin coating process and a soft bake process. Thereafter, the polymer material layer is patterned to form the openings43by exposure and development processes, and a curing process. The process parameters (such as the temperature of soft bake process and the temperature of the curing process) for forming the polymer layer PM3′ may be substantially the same as those of the polymer layer PM1(FIG. 1D) as described in the first embodiment. Afterwards, the via V′ and the TIV29are formed simultaneously on the trace T′ exposed by the openings43by, for example, sputtering, electroplating, or a combination thereof.

Two dies20aand20bare attached to the RDL structure35through adhesive layers12such as a die attach film (DAF), silver paste, or the like. The dies20aand20bare similar to those described in the first embodiment, which is not described again. In this embodiment, the adhesive layer12is located between the die20a/20band the polymer layer PM3′ of the RDL structure35, the width of the adhesive layer12is substantially equal to the width of the die20a/20b. It is mentioned that, the dies20aand20bmay be attached to the RDL structure35before or after the TIV29is formed.

Still referring toFIG. 2A, since the polymer layer PM3′ has a substantially flat surface, the problem of void between the adhesive layer12and the polymer layer PM3′ is avoided or reduced, and the adhesion between the adhesive layer12and the polymer layer PM3′ is thus increased.

In some embodiments, the dies20aand20bare disposed between the TIVs29. In other words, the TIVs29are aside or around the dies20aand20b. In some embodiments, the top surfaces of the TIVs29are substantially coplanar with the top surfaces of the connectors19aand19bof the dies20aand20b, but the disclosure is not limited thereto. In some other embodiments, the top surface of the TIVs29may be higher than the top surfaces of the dies20aand20b.

Referring toFIG. 2B, an encapsulant material layer22is formed on the RDL structure, the dies20aand20b, and the TIVs29. The encapsulant material layer22encapsulates the top surface of the RDL structure35, the top surfaces and sidewalls of the TIVs29, the top surfaces and sidewalls of the dies20aand20b. The material and the forming method of the encapsulant material layer22are substantially the same as those described in the first embodiment, which is not described again.

Referring toFIG. 2BandFIG. 2C, a planarization process is performed to at least remove the encapsulant material layer22over the top surfaces of the dies20aand20band the TIVs29, and an encapsulant22ais formed. The planarization process includes a polishing or grinding process, such as a CMP process. In some embodiments, the top surface of the encapsulant22a, the top surfaces of the dies20aand20band the top surfaces of the TIVs29are substantially coplanar with each other. In the embodiments in which the top surfaces of the TIVs29are substantially coplanar with the top surfaces of the connectors19aand19bof the dies20aand20b, a portion of the encapsulant material layer22is removed during the planarization process. In the embodiments in which the top surface of the TIV29is higher than the top surfaces of the dies20aand20b, a portion of the encapsulant material layer22and a portion of the TIVs29are removed during the planarization process.

Referring toFIG. 2C, in some embodiments, one or more pits (or referred as recesses)23may be formed in the encapsulant22aafter the planarization process.

The redistribution layer RDL1penetrates through the polymer layer PM1and is electrically connected to the connectors19aand19bof the dies20aand20b. The redistribution layer RDL2penetrates through the polymer layer PM2and is electrically connected to the redistribution layer RDL1. The redistribution layer RDL3penetrates through the polymer layer PM3and is electrically connected to the redistribution layer RDL2. The redistribution layer RDL4penetrates through the polymer layer PM4and is electrically connected to the redistribution layer RDL3.

The redistribution layers RDL1, RDL2, RDL3and RDL4respectively includes a plurality of vias V and a plurality of traces T connected to each other. The vias V vertically penetrate through the polymer layers PM1, PM2, PM3and PM4to connect the traces T of the redistribution layers RDL1, RDL2, RDL3and RDL4, and the traces T are respectively located on the polymer layers PM1, PM2, PM3and PM4, and are respectively horizontally extending on the top surface of the polymer layers PM1, PM2, PM3and PM4.

The RDL structure28is electrically connected to the connectors19aand19bof the dies20aand20band the TIVs29. The structure, the material and the forming method of the RDL structure28is similar to those in the first embodiment, which is not described again.

Still referring toFIG. 2D, a plurality of connectors30are formed on the redistribution layer RDL4. In some embodiments, a passive device39is further connected to the redistribution layer RDL4through a conductive bump38therebetween. In some embodiments, the passive device39is an integrated passive device (IPD). In some embodiments, the passive device39is a surface-mounting semiconductor device (SMD). The passive device39may be a capacitor, a resistor, an inductor or the like, or a combination thereof. The passive device39is optionally connected to the RDL structure28, and the number of the passive device39is not limited to that is shown inFIG. 2E, but may be adjusted according to the design of the product. The connectors30and the passive device39are electrically connected to the connectors19aand19bof the dies20aand20bthrough the RDL structure28.

Referring toFIG. 2E, the carrier10is released with the de-bonding layer11decomposed under the heat of light. A package structure50bis thus completed. The package structure50bincludes the RDL structure35, two dies20aand20b, the encapsulant22a, the TIVs29, the RDL structure28, the connectors30, and the passive device39. The encapsulant22amay include pits23therein. In some embodiments, the protection layer16a/16bof the die20a/20band the polymer layers PM1′, PM2′, PM3′, PM1, PM2, PM3, PM4include a non-shrinkage material, and have substantially flat top surfaces.

In the embodiments of the disclosure, the connector of the die is formed after the protection layer is formed, and the protection layer of the die and the polymer layers of the RDL structure are formed of a non-shrinkage material. Therefore, the deformation and bubble issue of the protection layer is avoided or reduced. The problem of recess may occur in the polymer layer due to the pits in the encapsulant is avoided, and the RDL trace broken is thus avoided. On the other hand, in some embodiments, the base angle of the via of the RDL is a right angle, that is, a top width of the via is equal to the bottom width of the via, therefore, more traces are allowed to go through in a certain area.

In accordance with some embodiments of the disclosure, a package structure includes a first die, an encapsulant, a first RDL structure, and a conductive terminal. The encapsulant is aside the first die, encapsulating sidewalls of the first die. The first RDL structure is on the first die and the encapsulant. The conductive terminal is electrically connected to first die through the RDL structure. The first RDL structure comprises a first polymer layer and a first RDL, the first polymer layer comprises a non-shrinkage material and a top surface of the first polymer layer is substantially flat.

In accordance with alternative embodiments of the disclosure, a package structure includes a die, an encapsulant, a RDL structure and a conductive terminal. The die comprises a connector and a protection layer aside the connector. The connector comprises a seed layer and a conductive post. The seed layer surrounds and covers sidewalls and bottom surfaces of the conductive post. The encapsulant is aside the die, encapsulating sidewalls of the die. The RDL structure is on the die and the encapsulant, and comprises a polymer layer and a redistribution layer. The conductive terminal is electrically connected to die through the RDL structure

In accordance with some embodiments of the disclosure, a method of manufacturing a package structure includes the following steps. An encapsulant is formed aside the die to encapsulate sidewalls of the die. A RDL structure is formed on the die. A conductive terminal is electrically connected to the die through the RDL structure. The die is formed by the following steps. A protection layer is formed on a pad. The protection layer is patterned to form an opening in the protection layer. The opening exposes a portion of a top surface of the pad. A connector is formed in the opening of the protection layer to be in electrical contact with the pad.