SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME

This semiconductor device (100) includes: a gate electrode (12) formed on a substrate (10); a gate insulating layer (20) formed over the gate electrode; an oxide semiconductor layer (18) formed on the gate insulating layer; source and drain electrodes (14, 16) connected to the oxide semiconductor layer; and an insulating layer (22) formed over the source and drain electrodes. The insulating layer includes a silicon nitride layer (22a) which contacts with at least a part of the upper surface of the source and drain electrodes and of which the thickness is greater than 0 nm and equal to or smaller than 30 nm, and a silicon oxide layer (22b) which has been formed on the silicon nitride layer and which has a thickness of more than 30 nm.

TECHNICAL FIELD

The present invention relates to a semiconductor device (such as an active-matrix substrate) which is formed with an oxide semiconductor, and also relates to a method for producing such a device.

BACKGROUND ART

An active-matrix substrate for use in a liquid crystal display device and other devices includes switching elements such as thin-film transistors (which will be hereinafter simply referred to as “TFTs”), each of which is provided for an associated one of pixels. As such switching elements, a TFT which uses an amorphous silicon film as its active layer (and will be hereinafter referred to as an “amorphous silicon TFT”) and a TFT which uses a polysilicon film as its active layer (and will be hereinafter referred to as a “polysilicon TFT”) have been used extensively.

Recently, people have proposed that a material other than amorphous silicon or polysilicon be used as a material for the active layer of a TFT. For example, Patent Document No. 1 discloses a liquid crystal display device, of which the TFT's active layer is formed out of an oxide semiconductor film of InGaZnO (that is an oxide made up of indium, gallium and zinc). Such a TFT will be hereinafter referred to as an “oxide semiconductor TFT”.

The oxide semiconductor TFT can operate at higher speeds than an amorphous silicon TFT. Also, such an oxide semiconductor film can be formed by a simpler process than a polysilicon film, and therefore, is applicable to even a device that needs to cover a large area. That is why an oxide semiconductor TFT has been used more and more often in a display device and other devices as an active element which achieves even higher performance in its switching operation and which can be fabricated with the number of manufacturing process steps and the manufacturing cost cut down.

In addition, since an oxide semiconductor has high electron mobility, even an oxide semiconductor TFT of a smaller size than a conventional amorphous silicon TFT could achieve performance that is equal to or higher than that of the amorphous silicon TFT. For that reason, by using oxide semiconductor TFTs, the area occupied by the TFT in a pixel region of a display device or any other device can be decreased, and therefore, the aperture ratio of the pixel can be increased. Consequently, a display operation can be performed with even higher luminance or the power dissipation can be reduced by decreasing the quantity of light emitted from a backlight.

For example, in a small-sized high-definition liquid crystal display device for use in a smartphone and other electronic devices, it is not easy to increase the aperture ratio of a pixel due to the limit on the minimum width of lines (i.e., the process rule). That is why if the aperture ratio of the pixel can be increased by using an oxide semiconductor TFT, a high-definition display operation can be carried out with the power dissipation cut down, which is advantageous.

CITATION LIST

Patent Literature

Patent Document No. 1: PCT International Application Publication No. 2009/075281

SUMMARY OF INVENTION

Technical Problem

In its manufacturing process, an oxide semiconductor TFT is usually subjected to a heat treatment at a relatively high temperature (e.g., about 300° C. or more) in order to improve the performance of the device. This heat treatment is often carried out after a passivation layer (protective layer) has been formed to cover the oxide semiconductor layer and source and drain electrodes. If the source and drain electrodes are covered with the passivation layer, it is possible to prevent their surface from being oxidized and coming to have increased resistance during the heat treatment.

Examples of known passivation layers for use in an oxide semiconductor TFT include a silicon oxide (SiOx) film, a silicon oxynitride (SiOxNy, where x>y) film, a silicon nitride oxide (SiNxOy, where x>y) film and a silicon nitride (SiNx) film. Meanwhile, Patent Document No. 2 discloses a technique for forming a passivation layer with a multilayer structure by alternately stacking an insulator including nitrogen such as silicon oxynitride and an insulator including nitrogen and fluorine one upon the other.

Such a passivation layer that has been formed to cover TFTs sometimes includes hydrogen at a relatively high percentage. For example, if a silicon nitride (SiNx) film is formed by CVD process using SiH4(mono-silane) gas and NH3gas as source gases, then hydrogen will be included at a relatively high percentage in the silicon nitride film formed. If the heat treatment described above is carried out with such an insulating film including a lot of hydrogen provided, then the hydrogen will diffuse inside the oxide semiconductor layer and sometimes cause deterioration in the performance of TFTs.

The present inventors perfected our invention in order to overcome these problems by providing high-performance semiconductor devices with good stability and at a good yield.

Solution to Problem

A semiconductor device according to an embodiment of the present invention includes: a substrate; a gate electrode which has been formed on the substrate; a gate insulating layer which has been formed over the gate electrode; an oxide semiconductor layer which has been formed on the gate insulating layer; source and drain electrodes which are electrically connected to the oxide semiconductor layer; and an insulating layer which has been formed over the source and drain electrodes. The insulating layer includes a silicon nitride layer which contacts with at least a part of the upper surface of the source and drain electrodes and of which the thickness is greater than 0 nm and equal to or smaller than 30 nm, and a silicon oxide layer which has been formed on the silicon nitride layer and of which the thickness is greater than 30 nm.

In one embodiment, the silicon oxide layer has a thickness of 50 nm to 400 nm.

In one embodiment, the upper surface of the source and drain electrodes that contacts with the silicon nitride layer is made of a conductive material including at least one element selected from the group consisting of Mo, Ti, Cu and Al.

In one embodiment, the contact surface of the source and drain electrodes is made of molybdenum nitride.

In one embodiment, the semiconductor device further includes an etch stop layer which has been formed over a channel region of the oxide semiconductor layer.

In one embodiment, the oxide semiconductor layer is made of an In—Ga—Zn—O based semiconductor.

A method for fabricating a semiconductor device according to an embodiment of the present invention includes the steps of: (a) providing a substrate; (b) forming a gate electrode on the substrate; (c) forming an oxide semiconductor layer over the substrate so that the oxide semiconductor layer is insulated from the gate electrode and faces the gate electrode; (d) forming source and drain electrodes to be connected to the oxide semiconductor layer on the substrate; (e) forming an insulating layer which contacts with at least a part of the upper surface of the source and drain electrodes over the substrate; and (f) conducting a heat treatment at a temperature of 230° C. to 480° C. after the step (e) has been performed. The step (e) includes the steps of: forming a first insulating region including nitrogen so that the first insulating region contacts with the source and drain electrodes and has a thickness of more than 0 nm to equal to or smaller than 30 nm; and forming a second insulating region including oxygen over the first insulating region so that the second insulating region has a thickness of more than 30 nm.

In one embodiment, the first insulating region is formed out of a silicon nitride layer and the second insulating region is formed out of a silicon oxide layer.

In one embodiment, the step (d) includes forming the surface of the source and drain electrodes out of a conductive material including at least one element selected from the group consisting of Mo, Ti, Cu and Al.

In one embodiment, the step of forming the silicon nitride layer in the step (e) is performed by a plasma CVD process using source gases including SiH4and NH3gases.

Advantageous Effects of Invention

A semiconductor device according to an embodiment of the present invention contributes to fabricating a TFT substrate including oxide semiconductor TFTs with good device performance at a good yield.

DESCRIPTION OF EMBODIMENTS

First of all, a semiconductor device according to an embodiment of the present invention will be outlined with reference to semiconductor devices as comparative examples shown inFIGS. 1(a) and1(b).

FIG. 1(a) illustrates a semiconductor device900as a first comparative example (which is a TFT substrate for use in a liquid crystal display device in this example). The TFT substrate900includes a substrate10, on which an oxide semiconductor layer18is arranged with a gate electrode12and a gate insulating film20interposed between them so as to overlap with the gate electrode12. Source and drain electrodes14and16are connected to the oxide semiconductor layer18. These members together form a TFT (oxide semiconductor TFT)95. The TFT95is covered with a passivation layer92which is provided as a protective layer. The TFT substrate900further includes an upper transparent electrode30which is connected to the drain electrode16of the TFT95and a lower transparent electrode32which is arranged under the upper transparent electrode30with a dielectric layer26interposed between them. However, description thereof will be omitted herein.

In this TFT substrate900, the passivation layer92is formed out of an SiNx (silicon nitride) film and typically has a thickness of 100 to 400 nm. An SiNx film is dense enough to protect the TFT95effectively.

However, if the passivation layer92is formed out of a silicon nitride film, hydrogen included in the silicon nitride film sometimes diffuses toward the oxide semiconductor layer18during a heat treatment process, for example. Particularly when a silicon nitride film which has been formed using SiH4(mono-silane) and NH3gases as source gases is used, that film includes hydrogen at a relatively high percentage, and therefore, hydrogen will enter the oxide semiconductor layer18easily.

That hydrogen affects the channel region of the oxide semiconductor layer18(on the back channel side). As a result, when the module fabricated goes through an aging treatment, its threshold value will shift (i.e., the TFT performance will vary). That is why if a display panel is fabricated using the TFT substrate900, the display quality of the panel deteriorates due to generation of off-state leakage current or shortage of on-state current. For that reason, diffusion of hydrogen into the oxide semiconductor layer18should be reduced as much as possible.

To overcome such a problem, according to a known configuration, an insulating layer (etch stop layer)21is arranged under the source and drain electrodes14,16so as to cover the channel region of the oxide semiconductor layer18as shown inFIG. 1(a). In the process step of forming the source and drain electrodes14,16by etching a conductive film, the etch stop layer21works to prevent the oxide semiconductor layer18from getting etched. Also, if the etch stop layer21is made of an oxide (such as SiO2), diffusion of hydrogen from the passivation layer92to the oxide semiconductor layer18can be minimized. As a result, the reduction reaction of the oxide semiconductor layer18can be reduced on the back channel side, and therefore, deterioration of the TFT performance can be minimized. Such a configuration including an etch stop layer21is called a “channel protected type (or etch stop type)” as will be described later.

However, even if such a channel-protected TFT95is formed, the passivation layer92should not include a lot of hydrogen, because that will cause deterioration in the performance of the device. In addition, if the etch stop layer21needs to be provided, an additional manufacturing process step should be performed for that purpose, which is also a problem.

Thus, to overcome such a problem, it was proposed that the passivation layer94be made of a material that would affect the oxide semiconductor layer18to a lesser degree as in a second comparative example shown inFIG. 1(b). For example, the passivation layer94may be made of an oxide film such as an SiO2film. Such an idea of making the protective layer of an oxide semiconductor TFT of an oxide is disclosed in Patent Document No. 1, for example.

As shown inFIG. 1(b), in the TFT substrate902of the second comparative example, the passivation layer94is made of an SiO2film, and therefore, no etch stop layer is provided to cover the channel region of the oxide semiconductor layer18. That is to say, in this TFT substrate902, not the channel-protected TFTs described above but “channel-etched” TFTs96(to be described later) have been formed.

However, the present inventors discovered and confirmed via experiments that when the passivation layer94was formed out of an oxide film such as an SiO2film, the surface of the source and drain electrodes14,16got oxidized easily during the heat treatment process to be carried out after that. This is because an oxidation reduction reaction would occur between the metal and the oxide film at the interface between the source and drain electrodes14,16and the passivation layer94. If an oxide film has been formed on the surface of the source and drain electrodes14,16in this manner, the closeness of contact of the passivation layer94sometimes decreases. As a result, the passivation layer94might peel off in a subsequent process step, thus causing a decrease in yield.

Particularly if the surface of the source and drain electrodes14,16is made of a metallic material (such as MoN) including Mo, Ti, Cu or Al and if a metal oxide film is formed on the surface, the SiO2film will peel off easily from the surface of the source and drain electrodes14,16.

Thus, to overcome such a problem, the present inventors carried out intensive researches. As a result, the present inventors discovered that a thin silicon nitride layer (such as an SiN film)22awith a thickness of 30 nm or less should be provided so as to contact with the surface of the source and drain electrodes14,16and a silicon oxide layer (such as an SiO2film)22bshould be provided on the silicon nitride layer22aas shown inFIG. 3(a).

According to such a configuration, the passivation layer22as a whole includes so little hydrogen that the influence on the oxide semiconductor layer18and deterioration of the TFT performance can be reduced. In addition, since no oxide film is arranged directly on the source and drain electrodes14,16, it is possible to prevent the surface of the source and drain electrodes14,16from getting oxidized and losing closeness of contact during the heat treatment. The present inventors discovered that the decrease in the closeness of contact of the passivation layer22could be checked sufficiently just by interposing a thin silicon nitride layer with a thickness of as small as 30 nm or less. As a result, the occurrence of film peeling due to a decrease in the closeness of contact of the passivation layer22could be prevented with the device performance of the oxide semiconductor TFT kept high.

A semiconductor device as an embodiment of the present invention and a method for fabricating that device will now be described. A semiconductor device according to an embodiment of the present invention just needs to include a thin-film transistor with an active layer made of an oxide semiconductor (which will be hereinafter referred to as an “oxide semiconductor TFT”). The semiconductor device is broadly applicable to an active-matrix substrate and various kinds of display devices and electronic devices.

In the following description, an oxide semiconductor TFT with a bottom-gate structure, in which a gate electrode is arranged under an oxide semiconductor layer, will be described. In an oxide semiconductor TFT with a bottom-gate structure, source and drain electrodes are ordinarily formed by etching a conductive layer which has been formed on the oxide semiconductor layer (in a source/drain dividing process step). In this process step, to minimize the damage to be done on the oxide semiconductor layer through etching, the conductive layer may be etched with the channel region of the oxide semiconductor layer covered with a protective film (i.e., the etch stop layer21described above). A TFT thus obtained will be hereinafter referred to as a “channel-protected type (or etch stop type)”. On the other hand, a TFT to be obtained by etching a conductive layer without covering the channel portion with a protective film will be hereinafter referred to as a “channel-etched type”.

In the following description, a semiconductor device including a TFT of the channel-protected type will be described as a first embodiment, and a semiconductor device including a TFT of the channel-etched type will be described as a second embodiment.

FIG. 2andFIGS. 3(a) and3(b) illustrate a semiconductor device100as a first embodiment. In this embodiment, the semiconductor device100is implemented as a TFT substrate (active-matrix substrate)100for use in a liquid crystal display device.FIG. 2schematically illustrates a planar structure of the TFT substrate100, andFIGS. 3(a) and3(b) illustrate cross-sections as respectively viewed on the planes A-A′ and D-D′ shown inFIG. 2.

As shown inFIG. 2, this TFT substrate100includes a display area (active area)120which contributes to a display operation and a peripheral area (frame area)110which is located outside of the display area120.

In the display area120, a plurality of gate lines2and a plurality of source lines4have been formed, and each region surrounded with these lines defines a “pixel”. Those pixels are arranged in a matrix pattern. In each pixel, a thin-film transistor (TFT)5is arranged as an active element in the vicinity of each intersection between the gate lines2and the source lines4. Each TFT5is electrically connected to its associated pixel electrode30provided for each pixel. By controlling the voltage applied to the pixel electrode30, a display operation can be performed.

In the peripheral area110, terminal portions2T,4T, each of which electrically connects either a gate line2or a source line4to an external line, have been formed. The gate line terminal portion2T and source line terminal portion4T are respectively connected to a gate driver and a source driver (neither is shown) which are provided outside of the TFT substrate100via an external line and an FPC.

Next, the configuration of the TFT substrate100in the vicinity of the TFT5will be described with reference toFIG. 3(a).

As shown inFIG. 3(a), the TFT substrate100includes, on a substrate10, a gate electrode12, a gate insulating layer20which covers the gate electrode12, and an oxide semiconductor layer (such as an In—Ga—Zn—O based semiconductor layer)18which is arranged so as to overlap with the gate electrode12with the gate insulating layer20interposed between them. An etch stop layer21has been formed on the oxide semiconductor layer18. Through the holes21hthat have been cut through the etch stop layer21, source and drain electrodes14and16are connected to the oxide semiconductor layer18so as to be separated from each other. A TFT5is formed of these members. When an ON-state voltage is applied to the gate electrode12, the TFT5turns ON, and the source and drain electrodes14,16get electrically conductive with each other via the channel region of the oxide semiconductor layer18.

In this embodiment, the source and drain electrodes14,16have a triple layer structure consisting of MoN, Al and MoN layers. The lowermost MoN layer14a,16acontacts with the oxide semiconductor layer18. An Al layer14b,16bis provided as a middle layer. And the uppermost MoN layer14c,16carranged on the Al layer forms the surface of the source and drain electrodes14,16, and contacts with a passivation layer22to be described later.

A passivation layer22has been formed as a protective insulating layer which covers the TFT5. The passivation layer22is comprised of a lower insulating layer22awhich is arranged so as to contact with the source and drain electrodes14,16(more specifically, their uppermost

MoN layer14c,16c) and an upper insulating layer22barranged on the lower insulating layer22a.In this embodiment, the lower insulating layer22ais formed out of a silicon nitride (SiNx) layer with a thickness of more than 0 nm to equal to or smaller than 30 nm, and the upper insulating layer22bis formed out of a silicon oxide (SiOx) layer with a thickness of more than 30 nm.

The lower insulating layer22ais formed out of a silicon nitride layer, and therefore, typically includes some hydrogen. However, the thickness of this lower insulating layer22afalls within the range of 0 to 30 nm as described above, and is much smaller than that of an ordinary passivation layer22(which usually falls within the range of 100 to 400 nm). For that reason, the content of hydrogen in the lower insulating layer22ais sufficiently smaller than in a situation where the passivation layer consists of a single SiNx layer as in the conventional configuration. Meanwhile, the upper insulating layer22bto be formed on the lower insulating layer22ais formed out of an SiOx layer, of which the hydrogen content is even smaller than that of the lower insulating layer22b.Consequently, the overall hydrogen content of the passivation layer22is small.

As can be seen, the passivation layer22has a configuration in which the lower and upper insulating layers22aand22bare stacked one upon the other, and its hydrogen content is not uniform in the thickness direction. That is to say, a portion of the passivation layer22which is located closer to the source and drain electrodes14,16is a region with the higher hydrogen content, while the rest of the passivation layer22which is located more distant from the source and drain electrodes14,16is a region with the lower hydrogen content.

Also, in the passivation layer22with such a structure, the lower insulating layer22awhich contacts with the source and drain electrodes14,16is formed out of a silicon-based insulating layer with a high nitrogen concentration (or including nitrogen but not including oxygen), while the upper insulating layer22bis formed out of a silicon-based insulating layer with a high oxygen concentration (or including oxygen but not including nitrogen).

Optionally, the passivation layer22may include a silicon oxynitride (SiOxNy, where x>y) layer or a silicon nitride oxide (SiNxOy, where x>y) layer. In that case, the closer to the source and drain electrodes14,16, the higher the nitrogen concentration of the passivation layer22should be. However, the passivation layer22does not have to be comprised of two layers as in this embodiment, but may also be comprised of three or more layers.

Over the passivation layer22, formed is an interlayer insulating layer24which is typically made of an organic resin material. The interlayer insulating layer24not only secures electrical insulation between layers but also functions as a layer that planarizes the surface of the substrate.

On the interlayer insulating layer24, arranged is a lower transparent electrode32made of ITO or IZO. The lower transparent electrode32has a hole32H and is formed so as to be electrically insulated from the TFT5(or the drain electrode16). Over the lower transparent electrode32, arranged is an upper transparent electrode30of ITO or IZO with a dielectric layer (insulating layer)26interposed between them.

The lower transparent electrode32may function as a common electrode, for example. On the other hand, the upper transparent electrode30may function as a pixel electrode, for example. A storage capacitor is formed by the lower transparent electrode32, the upper transparent electrode30and the dielectric layer26interposed between them. If a storage capacitor is formed by using the lower transparent electrode32in this manner, there is no need to provide any storage capacitor line on the same layer as the gate line2, and therefore, the aperture ratio can be increased.

Through the interlayer insulating layer24and the dielectric layer26, a contact hole CH has been cut to reach the surface of the drain electrode16of the TFT5(or a drain contact portion16′ as an extension of the drain electrode16). Also, inside the hole32H of the lower transparent electrodes32, a transparent connecting portion32C is arranged inside the contact hole CH independently of the lower transparent electrode32. The drain electrode16and the upper transparent electrode (pixel electrode)30are electrically connected together inside the contact hole CH via the transparent connecting portion32C.

Meanwhile, as shown inFIG. 3(b), in the peripheral area110of the TFT substrate100, arranged is a gate line terminal portion2T which has been formed in the same process step as the gate electrode12and the gate line2. Inside the contact hole that runs through the gate insulating film20, etch stop layer21, passivation layer22, interlayer insulating layer24and dielectric layer26, the gate line terminal portion2T is connected to a transparent connecting terminal portion30T on the same layer as the upper transparent electrode30via the transparent connecting portion32T on the same layer as the lower transparent electrode32.

The TFT substrate100with such a configuration is used in a liquid crystal display device. By injecting and sealing a liquid crystal layer between the TFT substrate100and a counter substrate (not shown), a liquid crystal display device can be obtained.

Next, it will be described with reference toFIGS. 4 through 6how to fabricate the TFT substrate100of the first embodiment shown inFIGS. 2,3(a) and3(b).

FIGS. 4(a) through4(e),FIGS. 5(f) through5(i) andFIGS. 6(j) through6(l) illustrate respective manufacturing process steps to fabricate the TFT substrate100. On the left-hand side of these drawings, illustrated is a region in the vicinity of the TFT shown inFIG. 3(a). On the other hand, on the right-hand side of these drawings, illustrated is a region in the vicinity of the terminal portion shown inFIG. 3(b).

First of all, as shown inFIG. 4(a), a substrate10is provided. The substrate10may be a glass substrate, a silicon substrate, or a plastic or resin substrate with thermal resistance. Examples of the plastic or resin substrates include substrates made of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), an acrylic resin, and a polyimide resin.

Next, a conductive film to be a gate line12and other members is deposited to a thickness of 50 nm to 300 nm over the substrate10. The conductive film may be made of a metallic element selected appropriately from the group consisting of aluminum (Al), tungsten (W), molybdenum (Mo), Ta (tantalum), Cr (chromium), Ti (titanium), and Cu (copper) or an alloy or metal nitride thereof. Or the conductive film may also be a stack of multiple layers of any of these metallic elements.

In this embodiment, a stack of conductive films consisting of an aluminum (Al) layer as the lower layer and a molybdenum-niobium (MoNb) alloy as the upper layer (of which the thicknesses are approximately 200 nm and 100 nm, respectively) is formed by sputtering process, and then patterned into an intended shape by photolithographic process using a resist mask, thereby forming a gate electrode12. As a result of this process step, a gate line2and a gate line terminal portion2T (seeFIG. 2) are also formed.

Thereafter, as shown inFIG. 4(b), a gate insulating film20is formed over the gate electrode12by plasma CVD process, for example. The gate insulating film20may be formed appropriately out of a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy, where x>y) layer, or a silicon nitride oxide (SiNxOy, where x>y) layer, for example.

Optionally, the gate insulating layer20may have a multilayer structure. To prevent dopants from diffusing from the substrate10, a lower gate insulating layer may be provided. The lower gate insulating film may be formed out of a silicon nitride layer or a silicon nitride oxide layer, for example. On the other hand, the upper gate insulating layer may be formed out of a silicon oxide layer or a silicon oxynitride layer, for example. To form a dense gate insulating film with little gate leakage current at a lower deposition temperature, a rare gas element such as argon may be added to the reactive gas so as to be introduced into the gate insulating layer. In this embodiment, a silicon nitride layer was deposited to a thickness of 100 nm to 400 nm with SiH4and NH3gases used as reactive gases.

Thereafter, as shown inFIG. 4(c), an oxide semiconductor film is deposited by sputtering process to a thickness of 30 to 100 nm over the gate insulating layer20and then etched and patterned into a predetermined shape (typically into islands) by photolithographic process using a resist mask, thereby obtaining an oxide semiconductor layer18. Optionally, the oxide semiconductor layer18thus formed may be subjected to oxygen plasma processing. The oxide semiconductor layer18suitably has a thickness of about 30 nm to about 100 nm, and may have a thickness of 50 nm, for example.

In this example, the oxide semiconductor layer18is obtained by patterning an In—Ga—Zn—O based amorphous oxide semiconductor film including In, Ga and Zn at a ratio of one to one to one, for example. However, In, Ga and Zn do not have to have the ratio described above but may also have any other appropriately selected ratio. Alternatively, the oxide semiconductor layer18may also be made of another oxide semiconductor film, instead of the In—Ga—Zn—O based semiconductor film.

More specifically, examples of other oxide semiconductor films include an InGaO3(ZnO)5film, a magnesium zinc oxide (MgxZn1−xO) film, a cadmium zinc oxide (CdxZn1−xO) film and a cadmium oxide (CdO) film. Still alternatively, the oxide semiconductor layer18may also be formed out of a ZnO film to which one or multiple dopant elements selected from the group consisting of Group I, Group XIII, Group XIV, Group XV and Group XVII elements have been added, or may naturally be a ZnO film to which no dopant elements have been added at all. The ZnO film may be in an amorphous state, a polycrystalline state, or a microcrystalline state (which is a mixture of amorphous and polycrystalline states).

If an amorphous In—Ga—Zn—O based semiconductor film is used as a material for the oxide semiconductor layer18, the oxide semiconductor layer18can be formed at a low temperature and high mobility can be achieved. The amorphous In—Ga—Zn—O based semiconductor film may be replaced with an In—Ga—Zn—O based semiconductor film which exhibits crystallinity with respect to a predetermined crystal axis (C-axis).

The top layer of the gate insulating layer20(i.e., the layer that contacts with the oxide semiconductor layer18) is suitably an oxide layer (such as an SiO2layer). In that case, even if there are oxygen deficiencies in the oxide semiconductor layer18, the oxygen deficiencies can be covered by oxygen included in the oxide layer. As a result, such oxygen deficiencies of the oxide semiconductor layer18can be reduced effectively.

Subsequently, an insulating layer21′ may be formed out of an SiOx film, for example, so as to cover the oxide semiconductor layer18as shown inFIG. 4(d). Thereafter, as shown inFIG. 4(e), the insulating layer21′ is patterned, thereby forming an etch stop layer21including a portion which covers the channel region of the oxide semiconductor layer18. As described above, the etch stop layer21is suitably made of an oxide layer, because the oxygen deficiencies of the oxide semiconductor layer18can be reduced effectively. In the embodiment illustrated inFIG. 4, the etch stop layer21has a pair of holes21hwhich are arranged to face two opposing sides of an island of the oxide semiconductor layer18(seeFIG. 2). Inside these holes21h, the oxide semiconductor layer18is exposed. However, this embodiment is only an example and any other embodiment may also be adopted. For example, the etch stop layer21may also be provided as islands to cover only the channel region of the oxide semiconductor layer18.

Meanwhile, in the peripheral area, while this process step of forming an etch stop layer21is being performed, the gate insulating film20and insulating film21′ are etched away from over the gate line terminal portion2T and the surface of the gate line terminal portion2T gets exposed.

After that, as shown inFIG. 5(f), the conductive film formed by sputtering process, for example, is patterned into a predetermined shape by photolithographic process, thereby forming source and drain electrodes14,16. In this process step, a source line4and a source line terminal portion4T (seeFIG. 2)are also formed simultaneously.

In this embodiment, the source and drain electrodes14and16have been formed to have a triple layer structure consisting of MoN, Al and MoN layers (i.e., the lowermost MoN layer14a,16a,the middle Al layer14b,16b,and the uppermost MoN layer14c,16c). The lowermost MoN layer14a,16amay have a thickness of 30 nm to 70 nm, for example. The middle Al layer14b,16bmay have a thickness of 100 nm to 250 nm, for example. And the uppermost MoN layer14c,16cmay have a thickness of 50 nm to 150 nm. The lower MoN layer14a,16asuitably has higher nitrogen content than the upper MoN layer14c,16c.If the source and drain electrodes16,18have such a structure, the source and drain electrodes14and16can have a tapered cross-sectional shape.

As a conductive material to make the source and drain electrodes14,16, molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al) or any other suitable metal or an alloy or a metal nitride thereof may be used appropriately. Optionally, the source and drain electrodes14and16may include a layer which is made of a material with a light transmitting property such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide including silicon dioxide (ITSO), indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO) or titanium nitride. Typically, however, the surface of the source and drain electrodes14,16is made of a material including Mo, Ti, Cu or Al (such as MoN).

Also, the etching process to be performed in the photolithographic process to form the source and drain electrodes14,16may be either a dry etching process or a wet etching process. To process a substrate with a large area, however, a dry etching process which will cause a little variation in line width or size is suitably adopted. When this etching process step is performed, the etch stop layer21has already been formed on the oxide semiconductor layer18, and therefore, it is possible to prevent the oxide semiconductor layer18from getting etched unintentionally.

Next, as shown inFIG. 5(g), a passivation layer22is formed as a protective insulating layer so as to cover the TFT5. The process step of forming a passivation layer22includes the steps of forming an insulating region including nitrogen to a thickness of more than 0 nm to equal to or smaller than 30 nm so that the region contacts with the source and drain electrodes14,16and then forming an insulating region including oxygen to a thickness of more than 30 nm. More specifically, the process step of forming the passivation layer22includes the steps of forming a silicon nitride layer (lower insulating layer)22ato a thickness of 30 nm or less and stacking a silicon oxide layer (upper insulating layer)22bto a thickness of more than 30 nm on the silicon nitride layer22a.

The silicon nitride layer22amay be formed by plasma CVD process, for example, using a mixture of SiH4, NH3and N2gases as a reactive gas. On the other hand, the silicon oxide layer22bmay be formed by plasma CVD process, for example, using a mixture of SiH4and N2O gases as a reactive gas. Alternatively, at least one of the silicon nitride layer22aand silicon oxide layer22bmay be formed by sputtering process.

In this example, the silicon nitride layer22ais formed so as to have a thickness of more than 0 nm to equal to or smaller than 30 nm. The thickness of the silicon nitride layer22acan be controlled easily by adjusting the film deposition process time. The silicon nitride layer22amore suitably has a thickness of 2 nm to 10 nm. On the other hand, the silicon oxide layer22bis formed to be thicker than the silicon nitride layer22a,and suitably has a thickness of 50 nm to 400 nm, more suitably 100 nm to 300 nm.

Optionally, the passivation layer22may include a silicon oxynitride (SiOxNy, where x>y) layer or a silicon nitride oxide (SiNxOy, where x>y) layer. In that case, the passivation layer22is suitably formed so that the closer to the source and drain electrodes14,16, the higher its nitrogen concentration gets. The passivation layer22does not have to be comprised of two layers as described above, but may also be comprised of three or more layers.

By subjecting the entire substrate to a heat treatment (annealing process) at approximately 350° C. after the passivation layer22including multiple regions of different film qualities in the thickness direction has been formed and before an interlayer insulating layer24(to be described later) is formed, the device characteristic and reliability of the TFT can be improved. If the heat treatment is carried out at this timing, it is possible to prevent the surface of the source and drain electrodes14,16which is covered with the passivation layer22from getting oxidized and coming to have increased wiring resistance. In addition, by carrying out the heat treatment before the interlayer insulating layer24is formed, even if oxygen deficiencies have been produced in the channel region of the oxide semiconductor layer18, those oxygen deficiencies can be oxidized and easily reduced. As a result, intended TFT performance is realized easily.

Since the silicon nitride layer22ais in contact with the upper layer14c,16cof the source and drain electrodes during this heat treatment, it is possible to prevent a metal oxide film from being formed on the surface (i.e., on the upper layer14c,16c) of the source and drain electrodes. As a result, a decrease in the closeness of contact of the passivation layer22can be minimized. In addition, since the silicon nitride layer22ais a thin layer and is comprised mostly of the silicon oxide layer22b,the passivation layer22has so small hydrogen content that the influence of hydrogen on the back channel of the oxide semiconductor layer18can be only a little. Consequently, even after having been subjected to the aging treatment, the threshold value of the TFT hardly shifts and it is possible to prevent OFF-state leakage current or shortage of ON-state current from deteriorating the display quality of the panel.

The heat treatment temperature is not particularly limited but typically falls within the range of 230° C. to 480° C., and suitably falls within the range of 250° C. to 350° C. The heat treatment process time is not particularly limited, either, but may be 30 to 120 minutes, for example. Depending on the material of the interlayer insulating layer24, the heat treatment may be carried out after the interlayer insulating layer24has been formed.

Subsequently, as shown inFIG. 5(h), an interlayer insulating layer (planarizing layer)24of a photosensitive resin film or any other suitable material is formed on the passivation layer22. The interlayer insulating layer24is suitably made of an organic material. A hole has been cut through the interlayer insulating layer24and over a drain contact portion16′ which is an extended portion of the drain electrode16. Meanwhile, in the peripheral area, holes are created over the gate line terminal portion2T and over the source line terminal portion4T (not shown).

Thereafter, as shown inFIG. 5(i), by etching the passivation layer22using the interlayer insulating layer24with holes as a mask, a contact hole CH1is created to reach the extended portion of the drain electrode16(i.e., the drain contact portion16′). In addition, a contact hole CH1′ reaching the gate line terminal portion2T (and the source line terminal portion2T) is also created.

After that, as shown inFIG. 6(j), by patterning a transparent conductive film of ITO, IZO or any other suitable material, a lower transparent electrode32is formed on the interlayer insulating layer24. At the same time, a transparent connecting portion32C separated from the lower transparent electrode32is formed so as to contact with the drain contact portion16′ which is exposed inside the contact hole CH1. The transparent connecting portion32C may cover the sidewall of the contact hole CH1, for example. Meanwhile, in the peripheral area, a transparent connecting portion32T is formed so as to contact with the gate line terminal portion2T (and the source line terminal portion4T) inside the contact hole CH1′.

Thereafter, as shown inFIG. 6(k), a dielectric layer26is deposited over the entire surface of the substrate to cover the lower transparent electrode32and other members, and then another contact hole CH2is cut through the dielectric layer26so as to overlap with the contact hole CH1that has already been cut. In this manner, a contact hole CH which makes it connectible to the drain contact portion16′ of the TFT5is obtained.

The dielectric layer26is obtained by forming a silicon nitride film or silicon oxide film to a thickness of 100 nm to 300 nm by sputtering process or CVD process. Alternatively, the dielectric layer26may also be formed out of a silicon nitride oxide film or a silicon oxynitride film. The etching process to cut the contact hole CH2may be performed by photolithographic process.

Subsequently, as shown inFIG. 6(l), by patterning the transparent conductive film of ITO, IZO or any other suitable material, an upper transparent electrode (pixel electrode)30is formed on the dielectric layer26. Meanwhile, in the peripheral area, a transparent connecting portion30T which is connected to the gate line terminal portion2T (and source line terminal portion4T) inside the contact hole CH′ is formed.

The upper transparent electrode30is electrically connected to the drain contact portion16′ via the transparent connecting portion32C inside the contact hole CH. The upper transparent electrode30is typically formed on a pixel-by-pixel basis so as to cover entirely the area surrounded with the gate line2and the source line4.

The TFT substrate100thus obtained can be used effectively as an active-matrix substrate for a liquid crystal display device. Optionally, the shape of the pixel electrode30may be selected appropriately depending on the display mode. For example, if the pixel electrode30is formed so as to include a plurality of elongate electrodes that run parallel to each other and if an oblique electric field is generated between the pixel electrode30and the lower transparent electrode32, the TFT substrate100can also be used in a liquid crystal display device which operates in the FFS mode. Naturally, either a vertical or horizontal alignment film may be provided over the pixel electrode30depending on the display mode.

A TFT substrate100including an oxide semiconductor TFT has been described as a semiconductor device according to a first embodiment. By using this TFT substrate100, a display device of good display quality can be fabricated at a good yield.

FIG. 7andFIGS. 8(a) and8(b) illustrate a TFT substrate200as a second embodiment. In the TFT substrate200of this embodiment, no etch stop layer24is provided on the oxide semiconductor layer18, which is a difference from the TFT substrate100of the first embodiment. That is to say, the TFT substrate200of this embodiment includes a TFT6of a channel-etched type. In the following description, any component having substantially the same function as its counterpart of the first embodiment will be identified by the same reference numeral as its counterpart's and a detailed description thereof will be omitted herein.

As shown inFIGS. 8(a) and8(b), in this TFT substrate200, a passivation layer23which covers the TFT6is arranged so as to contact with not only the source and drain electrodes14,16but also the channel region of the oxide semiconductor layer18as well.

Just like the passivation layer22of the first embodiment, the passivation layer23of this embodiment is also comprised of a lower insulating layer23aand an upper insulating layer23bwhich is arranged on the lower insulating layer23a.The lower insulating layer23ais formed out of a silicon nitride (SiNx) layer with a thickness of more than 0 nm to equal to or smaller than 30 nm, and the upper insulating layer23bis formed out of a silicon oxide (SiOx) layer with a thickness of more than 30 nm.

The lower insulating layer23ais formed out of a silicon nitride layer, and therefore, typically includes some hydrogen. However, the thickness of this lower insulating layer23ais 30 nm or less as described above, and is much smaller than that of an ordinary passivation layer23(which usually falls within the range of 100 to 400 nm). For that reason, the content of hydrogen in the lower insulating layer23ais sufficiently smaller than in a situation where the passivation layer23consists of a single SiNx layer as in the conventional configuration. Meanwhile, the upper insulating layer23bto be formed on the lower insulating layer23ais formed out of an SiOx layer, of which the hydrogen content is even smaller than that of the lower insulating layer23a. Consequently, the overall hydrogen content of the passivation layer23is small.

As can be seen, even if the passivation layer23contacts with the channel region of the oxide semiconductor layer18, diffusion of hydrogen into the oxide semiconductor layer18does not affect the TFT's performance so seriously, because the lower insulating layer23ais a thin layer. That is why an oxide semiconductor TFT6with good device performance can be obtained as in the first embodiment described above.

In addition, since the silicon nitride layer as the lower insulating layer23acontacts with the source and drain electrodes14,16, the closeness of contact does not decrease even during the heat treatment, and the TFT substrate200can be manufactured at a good yield with film occurrence of film peeling prevented.

FIGS. 9(a) to9(e) andFIGS. 10(f) to10(j) illustrate manufacturing process steps to fabricate the TFT substrate200. The process steps shown inFIGS. 9(a) to9(c) are the same as the manufacturing process steps of the first embodiment shown inFIGS. 4(a) to4(c), respectively, and description thereof will be omitted herein.

As shown inFIG. 9(d), according to this embodiment, after the oxide semiconductor layer18has been formed, source and drain electrodes14,16are formed separately from each other so as to be connected to the oxide semiconductor layer18with no etch stop layer21provided between them. As can be seen, since there is no need to perform the process step of forming an etch stop layer21, the manufacturing process can be simplified compared to the first embodiment.

Nevertheless, if an etching process is carried out to separate the source and drain electrodes from each other in the process step shown inFIG. 9(d), the channel region of the oxide semiconductor layer18could be over-etched. In addition, as the conductive film to make the source and drain electrodes14,16directly contacts with the channel region of the oxide semiconductor layer18, the metallic element included in the metal film that forms the bottom of this conductive film could diffuse toward and enter the oxide semiconductor layer18.

It should be noted that the structure and material of the source and drain electrodes14,16may be the same as those of the first embodiment described above. The surface of the source and drain electrodes14,16is typically made of a material including Mo, Ti, Cu or Al (such as MoN).

Thereafter, a passivation layer23is formed as shown inFIG. 9(e). Since no etch stop layer is provided in this embodiment, the passivation layer23is formed to contact with the source and drain electrodes14,16and the oxide semiconductor layer18.

After that, a heat treatment is carried out as in the first embodiment, and the device performance of the TFT6can be improved as a result. Since the silicon nitride layer23ais in contact with the upper layer14c,16cof the source and drain electrodes in this process step, it is possible to prevent a metal oxide film from being formed on the surface of the source and drain electrodes. As a result, a decrease in the closeness of contact of the passivation layer23can be minimized. In addition, since the silicon nitride layer23ais a thin layer, the influence of hydrogen on the back channel of the oxide semiconductor layer18can be only a little.

The process steps shown inFIGS. 10(f) to10(j) to be performed after that are substantially the same as the process steps shown inFIGS. 5(h),5(g) andFIGS. 6(j) to6(l), and description thereof will be omitted herein. However, since no etch stop layer is provided, there is no need to etch the etch stop layer when a contact hole CH1′ is cut in the peripheral area, which is a difference from the first embodiment.

By using a TFT substrate200thus obtained, a display device of good display quality can be fabricated at a good yield.

Even though some embodiments of the present invention have been described above, those embodiments are naturally modifiable in various manners. For example, although a bottom-gate-type TFT, of which the gate electrode is arranged under a semiconductor layer, has been described, the present invention is also applicable to a TFT with a top gate structure. In a TFT with the top gate structure, a protective insulating layer (passivation layer) is also arranged so as to cover metallic lines and electrodes. Thus, by providing a silicon nitride layer with a thickness of 30 nm or less in a region of the passivation layer which contacts with the metallic lines and then stacking a silicon oxide layer thereon, a good device characteristic is realizable with film peeling eliminated. Also, in the embodiments described above, the upper surface of the semiconductor layer contacts with the source and drain electrodes. However, the present invention is also applicable to a TFT with a bottom-contact structure which is obtained by forming source and drain electrodes first and then forming islands of semiconductor layer over the source and drain electrodes.

Also, although an active-matrix substrate for use in a liquid crystal display device has been described, an active-matrix substrate for use to make an organic EL display device may also be fabricated. In an organic EL display device, a light-emitting element which is provided for each pixel includes an organic EL layer, a switching TFT and a driver TFT. And a semiconductor device according to an embodiment of the present invention can be used as any of those TFTs. Furthermore, by arranging those TFTs as an array and using them as select transistors, a storage element (i.e., an oxide semiconductor thin-film memory) can also be formed. The present invention is also applicable to an image sensor.

INDUSTRIAL APPLICABILITY

A semiconductor device according to an embodiment of the present invention and a method for fabricating such a device can be used effectively as a TFT substrate for a display device and a method for fabricating such a device, for example.

REFERENCE SIGNS LIST