Method for simulation of negative bias and temperature instability

An apparatus and method to accurately simulate negative bias and temperature instability (NBTI) and its effect. According to a first simulation method, a simulation netlist is automatically scanned for any P-type devices that are in a conductive state after application of an initial condition. Each conductive P-type device is automatically replaced with an NBTI device model and a first simulation cycle is executed. After the first cycle, each conductive P-type device is again replaced with an NBTI model and a second simulation cycle is executed. In a second simulation method, only those P-type devices transitioning from a non-conductive state to a conductive state are automatically replaced with an NBTI model prior to each half cycle of the second simulation method. The first simulation method provides robustness, while the second simulation method provides worst case verification in less time as compared to the first simulation method.

FIELD OF THE INVENTION

The present invention generally relates to circuit simulations, and more particularly, to the simulation of the negative bias and temperature instability (NBTI) phenomenon on deep, sub-micron circuits.

BACKGROUND

Recent advances in the field of semiconductor integrated circuits have brought about higher levels of integration. Semiconductor manufacturing process advancements are driving the corresponding geometric dimensions for semiconductor devices to decreasingly smaller values. As semiconductor manufacturing processes advance, so must the corresponding simulation algorithms that are used to characterize the circuits manufactured by the advanced processes.

Semiconductor devices implemented using 130 nm process rules, for example, behave differently when those devices are implemented with sub-100 nm, e.g., 90 nm or 65 nm, process rules. In particular, negative bias and temperature instability (NBTI) is one example of a device degradation mechanism that has been identified with sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs).

NBTI causes a threshold voltage increase in P-type MOSFETs (PMOSFETs), which results in a degraded transistor current drive. Such a degradation in current drive also affects the switching speed of circuits that incorporate NBTI-affected PMOS devices. The amount of time required to switch the output of an inverter, for example, from a logic high level to a logic low level actually decreases due to the degraded current drive of the NBTI affected PMOSFET within the inverter. Conversely, the amount of time required to switch the output of the inverter from a logic low level to a logic high level increases due to the degraded current drive of the NBTI affected PMOS transistor within the inverter.

NBTI effects become prevalent when the gate of a PMOS device is negatively biased for an extended period of time, e.g., several years, at elevated temperatures. In such instances, interface traps and fixed charges are created, whereby the silicon oxide of the PMOS gate interacts with the crystal lattice of the silicon substrate to trap holes, i.e., positive charge, within the channel inversion layer. The fixed charges and interface traps are of the same polarity, i.e., positive, and combine to increase the threshold voltage, VT, of the PMOS device.

Due to the NBTI phenomenon, therefore, designers must consider the bias conditions of each PMOS transistor throughout the PMOS transistor's lifetime. Typically, consideration of the bias conditions must allow for at least 10 years of operation in a conductive state at high temperature. In a particular simulation scenario, therefore, two PMOS transistor models may exist: a first PMOS model having normal threshold voltage, i.e., a PMOS model that is not affected by the NBTI phenomenon; and a second PMOS model exhibiting increased threshold voltage due to the NBTI phenomenon.

Prior art simulation methods have incorporated a manual process, whereby the circuit designer first identifies those PMOS transistors in the simulation netlist that are in a conductive state. Next, the circuit designer manually replaces all conductive PMOS transistor models with PMOS transistor models exhibiting increased threshold voltage due to the NBTI phenomenon. Finally, the circuit designer executes the simulation on the manually modified simulation netlist.

Such a manual simulation process may be plausible for relatively small netlists. However, the manual simulation process quickly becomes unmanageable and cumbersome for larger netlists. What is needed then, is an automated technique to simulate the affect of the NBTI phenomenon on deep, sub-100 nm circuits using existing simulation technologies.

SUMMARY

To overcome limitations in the prior art, and to overcome other limitations that will become apparent upon reading and understanding the present specification, various embodiments of the present invention disclose an apparatus and method for simulation of negative bias and temperature instability (NBTI) effect on deep, sub-100 nm circuits.

In accordance with one embodiment of the invention, a method of circuit simulation comprises identifying a set of devices within a simulation netlist having a first conductivity type, automatically replacing a simulation model of the set of devices with a modified simulation model, programming a first portion of the set of devices to exhibit a negative bias and temperature instability (NBTI) effect, executing a first simulation cycle, programming a second portion of the set of devices to exhibit the NBTI effect, and executing a second simulation cycle.

In accordance with another embodiment of the invention, a method of circuit simulation comprises identifying a first set of transistors within a simulation netlist having a first conductivity type that are transitioning from a first conductivity state to a second conductivity state in response to a first half simulation cycle, programming the first set of transistors to exhibit a negative bias and temperature instability (NBTI) effect, executing the first half simulation cycle, identifying a second set of transistors within the simulation netlist having the first conductivity type that are transitioning from the first conductivity state to the second conductivity state in response to a second half simulation cycle, programming the second set of transistors to exhibit the NBTI effect, and executing the second half simulation cycle.

In accordance with another embodiment of the invention, a circuit simulation system comprises a processor that is adapted to simulate negative bias and temperature instability (NBTI) effects. The processor is adapted to perform functions including, identifying devices affected by NBTI within a simulation netlist, replacing the identified devices within the simulation netlist with one of a plurality of NBTI device models, and executing one or more simulation cycles on the modified simulation netlist.

DETAILED DESCRIPTION

Generally, various embodiments of the present invention provide an apparatus and method to accurately simulate negative bias and temperature instability (NBTI) and its effect on circuits that implement devices affected by NBTI, e.g., P-type metal oxide semiconductor field effect transistors (PMOSFETs). In particular, PMOSFETs have been shown to be affected by the NBTI phenomenon, to the exclusion of their N-type metal oxide semiconductor field effect transistor (NMOSFET) counterparts, since interface states and fixed charges of the NMOSFET inversion channel are of opposite polarity and eventually cancel each other.

In a first simulation method, i.e., the static simulation method, the simulation netlist is automatically scanned for any PMOS devices that are in a conductive state at time, e.g., t=0. It is assumed that any such PMOS devices have been conductive for a continuous amount of time and, therefore, are affected by the NBTI phenomenon. As such, the conductive PMOS devices are automatically modeled as NBTI PMOS devices, i.e., PMOS devices exhibiting NBTI affects, just prior to executing a first transition of the simulation clock.

After the first transition, some, or all, of the NBTI PMOS devices transition from a conductive state to a non-conductive state. Upon the second transition of the simulation clock, some, or all, of the NBTI PMOS devices will return to a conductive state. As discussed in more detail below, those NBTI PMOS devices returning to the conductive state exhibit worst case NBTI induced delay and, therefore, are of particular interest during simulation. Of similar importance, however, are those NBTI PMOS devices that switch from a conductive state to a non-conductive state. In such instances, transitions are actually accelerated due to the NBTI phenomenon and thus become important when race conditions may affect circuit performance.

In an alternate simulation method, i.e., the dynamic simulation method, any PMOS devices that are in a non-conductive state are automatically modeled as NBTI PMOS devices prior to any simulation clock transition. Once the simulation transition occurs, the NBTI PMOS devices are automatically remodeled as non-NBTI PMOS devices to prepare for the subsequent transition from the conductive state to the non-conductive state. In such an instance, only those PMOS devices transitioning from a non-conductive state to a conductive state are modeled as NBTI PMOS devices, so as to simulate a worst-case delay scenario.

As discussed in more detail below, it is noted that both the static and dynamic simulation methods utilize a combination of currently known simulation elements, such as voltage controlled voltage sources (VCVSs), to generate the NBTI PMOS models. As such, both the static and dynamic simulation methods utilize existing simulation tools to allow circuit designers to optimize their circuits by allowing simulation of the NBTI phenomenon without adding new functionality to existing simulation workstations.

Turning toFIG. 1, an exemplary simulation workstation100is illustrated, which may be used to generate the circuit definition files, NBTI PMOS models, and circuit simulation algorithms, as necessary to simulate the NBTI phenomenon and its effect on circuit performance. The exemplary simulation workstation includes simulator138, which includes a central processor (CPU)102that is coupled to random access memory (RAM)104and read-only memory (ROM)106. The ROM106may also include other types of storage media to store programs, such as programmable ROM (PROM), electronically erasable PROM (EEPROM), etc. The processor102may also communicate with other internal and external components through input/output (I/O) circuitry108.

Simulator138may also include one or more data storage devices, including hard and floppy disk drives112, CD-ROM drives114, and other hardware capable of reading and/or storing information such as DVDs, tape drives, etc. Software for facilitating NBTI PMOS modeling, circuit definition files, and circuit simulations may be stored and distributed on a CD-ROM116, diskette118or other forms of media capable of portably storing information. These storage media may be inserted into, and read by, devices such as the CD-ROM drive114, the disk drive112, etc.

The software for facilitating the circuit definition files, NBTI PMOS models, and circuit simulation algorithms may also be transmitted to simulator138via data signals that are downloaded electronically via a network, such as Internet136. Simulator138is coupled to a display120, which may be any type of known display or presentation screen, such as LCD displays, plasma display, cathode ray tubes (CRT), etc. A user input interface122is provided, including one or more user interface mechanisms such as a mouse, keyboard, microphone, touch pad, touch screen, voice-recognition system, etc.

Processor102may be used to execute simulation tools132to aid in simulation operations. Simulation generator124, for example, generates the baseline simulation files that correspond to particular simulation models, including NBTI PMOS device models. Simulation optimizer126receives the simulation files from simulation generator124and optionally performs reduction methods to optimize the simulation files. Sub-circuit generator128then receives the optimized simulation files and generates the circuit definition files that are required by circuit simulator130to characterize the sub-circuit's operation.

Turning toFIG. 2A, an exemplary flow diagram of a static simulation method is illustrated, which is explained in relation to the exemplary circuits ofFIGS. 2B and 2C. In step202, initial conditions for the circuit are set, whereby in one embodiment, the input to inverter232may be set to a logic high level. Accordingly, the input to inverter234is set to a logic low level and the input to inverter236is set to a logic high level. Pass transistors212and214are set to their respective conductive states.

In step204, each PMOSFET rendered conductive by the initial conditions is automatically replaced with a PMOS model that is affected by the NBTI phenomenon. Each PMOSFET affected by the NBTI phenomenon is said to be automatically replaced with an NBTI PMOS model because no manual interaction with the simulation algorithm is necessary. In other words, simulation tools132ofFIG. 1may be manipulated by processor102to automatically replace PMOSFET devices within the simulation netlist with the appropriate device model as required, and no interaction by the simulation operator is necessary.

Since the inputs to inverters232and236are at a logic high level, PMOSFETs216and224are rendered non-conductive, and are thus modeled as PMOS devices that are not affected by the NBTI phenomenon. Since the input to inverter234is at a logic low level, on the other hand, PMOSFET210is rendered conductive, and is thus modeled as an NBTI PMOS device as indicated by the dotted circle surrounding PMOSFET210as illustrated inFIG. 2B. Pass gates212and214are each rendered conductive as well, and are similarly modeled as NBTI PMOS devices as indicated by the dotted circle surrounding PMOSFETs212and214. NMOSFETs218,222, and226, as discussed above, are not affected by the NBTI phenomenon and thus are modeled as typical NMOS devices.

Thus, the circuit ofFIG. 2Bis representative of the circuit that is to be simulated during the first simulation cycle of the static simulation method. The simulation is then allowed to progress from the initial condition through two transitions as illustrated in signal trace270by high-to-low transition228and low-to-high transition230. During high-to-low transition228, PMOSFET210transitions from a conductive state to a non-conductive state. The drain to source current conducted by PMOSFET210is reduced by the NBTI effect, which decreases the delay through inverter234during high-to-low transition228.

During low-to-high transition230, PMOSFET210transitions from a non-conductive state back to its originally conductive state. Due to the reduced drain to source current conducted by NBTI affected PMOSFET210, however, inverter234exhibits a worst case delay during low-to-high transition230. Thus, during the first simulation cycle of step204, the performance of inverter234is evaluated both in its minimum delay configuration during high-to-low transition228and in its worst case delay configuration during low-to-high transition230.

If the current simulation cycle is the first simulation cycle, as determined in step206, then the static simulation continues as in step208. In particular, the initial condition of step202is reversed and then each PMOSFET rendered conductive by the reversed initial condition is replaced with a PMOS model that is affected by the NBTI phenomenon. Since the inputs to inverters232and236are at a logic low level, PMOSFETs216and224are rendered conductive and are thus modeled as NBTI PMOS devices as indicated by the dotted circle surrounding PMOSFETs216and224as illustrated inFIG. 2C. Since the input to inverter234is at a logic high level, on the other hand, PMOSFET210is rendered non-conductive, and is thus modeled as a PMOS device that is not affected by the NBTI phenomenon. Pass gates212and214are each rendered conductive as well, and are similarly modeled as NBTI PMOS devices as indicated by the dotted circle surrounding PMOSFETs212and214.

Thus, the circuit ofFIG. 2Cis representative of the circuit that is to be simulated during the second simulation cycle of the static simulation method. The simulation is then allowed to progress from the reversed initial condition through two transitions as illustrated in signal trace280by low-to-high transition252and high-to-low transition254. During low-to-high transition252, PMOSFETs216and224transition from a conductive state to a non-conductive state. The drain to source current conducted by PMOSFETs216and224is reduced by the NBTI phenomenon, which decreases the delay through inverters232and236during low-to-high transition252.

During high-to-low transition254, on the other hand, PMOSFETs216and224transition from a non-conductive state to a conductive state. Due to the reduced drain to source current conducted by NBTI affected PMOSFETs216and224, however, inverters232and236exhibit worst case delay during high-to-low transition254. Thus, during the second simulation cycle of step208, the performance of inverters232and236are evaluated both in their minimum delay configuration during low-to-high transition252and in their worst case delay configuration during high-to-low transition254.

It can be seen, therefore, that the static simulation method ofFIG. 2Arepresents a robust simulation, whereby both decreased delay and increased delay of the NBTI affected devices is characterized. An execution time penalty is incurred, however, since two simulation cycles must be executed. Turning toFIG. 3A, an alternate simulation method is exemplified, whereby worst case NBTI effects may be characterized without incurring the added simulation cycle time.

The exemplary flow diagram of a dynamic simulation method is illustrated inFIG. 3Aand is explained in relation to the exemplary circuits ofFIGS. 3B and 3C. In step302, initial conditions for the circuit are set, whereby in one embodiment, the input to inverter332may be set to a logic low level. Accordingly, the input to inverter334is set to a logic high level and the input to inverter336is set to a logic low level. Pass transistors312and314are set to their respective conductive states.

In step302, each PMOSFET that is rendered non-conductive by the initial conditions, but that will be rendered conductive after the first half cycle of simulation, is automatically replaced with a PMOS model that is affected by the NBTI phenomenon. Each PMOSFET is said to be automatically replaced with an NBTI PMOS model because no manual interaction with the simulation algorithm is necessary. In other words, simulation tools132ofFIG. 1may be manipulated by processor102to automatically replace PMOSFET devices within the simulation netlist with the appropriate device model as required, and no interaction by the simulation operator is necessary.

Thus, it is assumed that all non-conductive PMOS devices have previously been in a conductive state for a long period of time, e.g., 10 years, and are, therefore, affected by the NBTI phenomenon. All other conductive PMOS devices are modeled as PMOS devices that are not affected by the NBTI phenomenon, since they will transition from a conductive state to a non-conductive state after the first half cycle of simulation.

Since the input to inverter334is at a logic high level, PMOSFET310is rendered non-conductive, and is thus modeled as an NBTI PMOS device, as indicated by the dotted circle surrounding PMOSFET310inFIG. 3B, because PMOSFET310is set to transition to a conductive state after the first half cycle of the simulation. Since the input to inverters332and336are at a logic low level, on the other hand, PMOSFETs316and324are rendered conductive, and are thus modeled as PMOS devices that are not affected by the NBTI phenomenon. Pass gates212and214are each rendered conductive and thus are similarly modeled as PMOS devices that are not affected by the NBTI phenomenon. NMOSFETs318,322, and326, as discussed above, are not affected by the NBTI phenomenon and thus are modeled as typical NMOS devices.

Thus, the circuit ofFIG. 3Bis representative of the circuit that is to be simulated during the first half cycle of the dynamic simulation method. The simulation is then allowed to progress through a single transition as illustrated by low-to-high transition330of step304. During low-to-high transition330, PMOSFET310transitions from a non-conductive state to a conductive state. Due to the reduced drain to source current conducted by NBTI affected PMOSFET310, inverter334exhibits a worst case delay during low-to-high transition330. Thus, during the first half cycle of the dynamic simulation, the performance of inverter334is evaluated in its worst case delay configuration during low-to-high transition330.

If the simulation cycle is in its first half simulation cycle, as determined in step306, then the dynamic simulation continues as in step308. In particular, all PMOS transistors that have been rendered non-conductive after the first half cycle of the simulation are automatically modeled as NBTI PMOS devices. All other PMOS transistors are modeled as PMOS devices that are not affected by the NBTI phenomenon.

Since the inputs to inverters332and336are at a logic high level, PMOSFETs316and324are rendered non-conductive and are thus modeled as NBTI PMOS devices as indicated by the dotted circle surrounding PMOSFETs316and324as illustrated inFIG. 3C. Since the input to inverter334is at a logic low level, on the other hand, PMOSFET310is rendered conductive, and is thus modeled as a PMOS device that is not affected by the NBTI phenomenon. Pass gates312and314are each rendered conductive as well, and are similarly modeled as PMOS devices that are not affected by the NBTI phenomenon.

Thus, the circuit ofFIG. 3Cis representative of the circuit that is to be simulated during the second half cycle of the dynamic simulation method. The simulation is then allowed to progress through the second half cycle of the simulation as illustrated by high-to-low transition354of step308. During high-to-low transition354, PMOSFETs316and324transition from a non-conductive state to a conductive state. Due to the reduced drain to source current conducted by NBTI affected PMOSFETs316and324, inverters332and336exhibit worst case delay during high-to-low transition354. Thus, during the second half cycle of the dynamic simulation method, the performance of inverters332and336are evaluated in their worst case delay configuration during high-to-low transition354.

It can be seen, therefore, that the dynamic simulation method, as discussed above in relation toFIGS. 3A-3C, requires half the number of simulation cycles relative to the static simulation method, as discussed above in relation toFIGS. 2A-2C. However, the dynamic simulation method is less robust as compared to the static simulation method, since only maximum delays are characterized in the dynamic simulation method, whereas the static simulation method characterizes both maximum delay and minimum delay.

Turning toFIG. 4A, an exemplary schematic diagram of NBTI PMOSFET model400is illustrated, which may be utilized during the dynamic simulation method as discussed above in relation toFIGS. 3A-3C. Through activation/deactivation of voltage controlled voltage sources (VCVSS)408-412, the appropriate increase/decrease in threshold voltage, VT, of PMOS device402may be simulated. In particular, a VTincrease may be simulated by an appropriate increase in voltage, Vg, at node406. Alternately, a VTdecrease may be simulated by an appropriate decrease in voltage, Vg, at node406.

The following voltage equation may be verified for operation of NBTI PMOSFET model400:
Vg1=Vg+(Vgs+Vdd)*X,(1)
where Vg1is the voltage at node404, Vg is the voltage at node406, Vgs is the voltage generated by VCVS412, Vdd is the voltage generated by VCVS410, and X is a multiplier used by VCVS408to scale the VTincrease appropriately, depending upon the PMOS device being modeled. For example, the VTshift due to the NBTI phenomenon for a core PMOS device operating at, e.g., 1 volt, may be equal to, for example, 80 mV, while the VTshift due to the NBTI phenomenon for an input/output (I/O) PMOS device operating at, e.g., 3.3 volts, may be equal to, for example, 200 mV.

In operation, the gate to source voltage, Vgs, of a particular PMOSFET device within the simulation netlist is measured. Should Vgs be measured to be equal −Vdd, for example, then the PMOS device is in a conductive state. In such an instance, Vg1=Vg in accordance with equation (1), whereby no increase in VTis simulated. Thus, all conductive PMOS devices are not modeled as being affected by the NBTI phenomenon, i.e., their threshold voltage is not increased, as discussed above in relation to the dynamic simulation method ofFIGS. 3A-3C, and equation (1) is verified.

After a programmable time delay, TD, VCVS412is programmed to a voltage of 0 volts, where Vg1=Vg+Vdd*X in accordance with equation (1). In such an instance, each PMOS device modeled using NBTI PMOS model400is automatically converted from a PMOS device exhibiting no NBTI effect to a PMOS device that is affected by the NBTI phenomenon after time delay, TD. Thus, after the first half cycle of the dynamic simulation method, each PMOS device is automatically converted to the correct PMOS device type in preparation for the second half cycle.

Turning toFIG. 4B, an exemplary schematic diagram of NBTI PMOSFET model450is illustrated, which may be utilized during the static simulation method as discussed above in relation toFIGS. 2A-2C. Through activation/deactivation of voltage controlled voltage sources (VCVSs)458and462, the appropriate increase/decrease in threshold voltage, VT, of PMOS device452may be simulated. In particular, a VTincrease may be simulated by an appropriate increase in voltage, Vg, at node456. Alternately, a VTdecrease may be simulated by an appropriate decrease in voltage, Vg, at node456.

The following voltage equation may be verified for operation of NBTI PMOSFET model450:
Vg1=Vg+Vsg*X,(2)
where Vg1is the voltage at node454, Vg is the voltage at node456, Vsg is the voltage generated by VCVS462, and X is a multiplier used by VCVS458to scale the VTincrease appropriately, depending upon the PMOS device being modeled.

In operation, the source to gate voltage, Vsg, of a particular PMOSFET device within the simulation netlist is measured. Should Vsg be measured to be equal +Vdd, for example, then the PMOS device is in a conductive state. In such an instance, Vg1=Vg+Vdd*X in accordance with equation (2), whereby an increase in VTis simulated. Thus, all conductive PMOS devices are modeled as being affected by the NBTI phenomenon, i.e., their threshold voltage is increased, as discussed above in relation to the static simulation method ofFIGS. 2A-2C, and equation (2) is verified.

After a programmable time delay, TD, VCVS412is programmed to a voltage of 0 volts, where Vg1=Vg in accordance with equation (2). In such an instance, each PMOS device modeled using NBTI PMOS model450is automatically converted from a PMOS device exhibiting the NBTI effect to a PMOS device that is not affected by the NBTI phenomenon after time delay, TD. Thus, after the first full cycle of the static simulation method, each PMOS device is automatically converted to the correct PMOS device type in preparation for the second full cycle of the static simulation method.