Integrated circuits with fets having nanowires and methods of manufacturing the same

Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a stack overlying a substrate. The stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first germanium concentration. The stack is condensed to produce a second germanium concentration in the germanium layer, where the second germanium concentration is greater than the first germanium concentration. A fin is formed that includes the stack, and a gate is formed overlying the fin.

TECHNICAL FIELD

The technical field generally relates to integrated circuits and methods for manufacturing integrated circuits, and more particularly relates to integrated circuits with FETs having nanowires and methods of manufacturing such integrated circuits.

BACKGROUND

The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A FET includes a gate electrode as a control electrode overlying a semiconductor channel and spaced-apart source and drain regions on opposite sides of the channel between which a current can flow. A gate dielectric layer is disposed between the gate electrode and the channel to electrically isolate the gate electrode from the channel. A control voltage applied to the gate electrode controls the flow of current through the channel between the source and drain regions. The FETs are generally “N” or “P” type FETs, (“nFET” or “pFET”) where the source and drain for nFETs are implanted with “N” type dopants, and the source and drain for pFETs are implanted with “P” type dopants.

A number of challenges arise as feature sizes of FETs and integrated circuits get smaller. For example, significant downsizing of traditional planar FETs leads to electrostatic issues and electron mobility degradation. Scaled-down planar FETS have shorter gate lengths that make it more difficult to control the channel. New device architectures such as nanowires allow further scaling of the integrated circuits, in part because the gate wraps around the channel and provides better control with lower leakage current, faster operations, and lower output resistance. The “gate all around” structure of a FET with nanowires has advantageous short channel characteristics over the electrostatics that the conventional planar FETs or FinFETs provide. Multiple nanowires can be used in the gate of a FET to increase the current capacity. However, there are process challenges in enabling large scale fabrication of nanowire FETs because of the size and structure. Hence nanowire FETs have not been incorporated into current commercial integrated circuit manufacturing.

Accordingly, it is desirable to provide integrated circuits with FETs having nanowires and methods of manufacturing integrated circuits with FETs having nanowires. In addition, it is desirable to provide integrated circuits with FETs using nanowires, where the FETs are manufactured using techniques that allow for further scaling, such as the use of fins and/or replacement metal gates. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.

BRIEF SUMMARY

Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a stack overlying a substrate. The stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first germanium concentration. The stack is condensed to produce a second germanium concentration in the germanium layer, where the second germanium concentration is greater than the first germanium concentration. A fin is formed that includes the stack, and a gate is formed overlying the fin.

A method for fabricating a nanowire is provided in another embodiment. A stack is epitaxially formed over a substrate, where the stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first silicon germanium layer volume. The stack is condensed to produce a second silicon germanium layer volume less than the first silicon germanium layer volume, and a nanowire is formed from the silicon germanium layer.

An integrated circuit is provided in yet another embodiment. The integrated circuit includes a fin and a gate overlying the fin. The fin includes a nanowire, where the nanowire includes germanium with a germanium concentration of from about 70 to about 90 weight percent. A nanowire insulator overlies the nanowire, where the nanowire insulator is silicon dioxide. A gate dielectric is between the fin and the gate.

DETAILED DESCRIPTION

According to various embodiments described herein, FETs with nanowire channels are formed from a layered stack within a fin using a replacement metal gate. Alternating layers of silicon and silicon germanium are deposited to form the stack overlying a substrate, and the stack is annealed to produce alternating layers of silicon dioxide and silicon germanium, where the concentration of germanium in the silicon germanium layers increases during the anneal. The annealed stack is formed into a fin, a replacement metal gate is formed over the fin, and a source and drain are formed. The concentrated silicon germanium layer serves as a nanowire within the fin, and the silicon dioxide forms a nanowire insulator that separates different nanowires within the fin.

In an exemplary embodiment illustrated inFIG. 1, an integrated circuit8is formed with a silicon germanium layer (SixGeylayer)12and a silicon layer (Si layer)14overlying a substrate10. As used herein, the term “overlying” means “over” such that an intervening layer may lie between the SixGeylayer12and the substrate10, and “on” such the SixGeylayer12physically contacts the substrate10. Also as used herein, the term “substrate”10encompasses semiconductor materials conventionally used in the semiconductor industry from which to make electrical devices. Semiconductor materials include monocrystalline silicon materials, such as the relatively pure or lightly impurity-doped monocrystalline silicon materials typically used in the semiconductor industry, as well as polycrystalline silicon materials, and silicon admixed with other elements such as germanium, carbon, and the like. Semiconductor material also includes other materials such as relatively pure and impurity-doped germanium, gallium arsenide, zinc oxide, glass, and the like. In an exemplary embodiment, the substrate10is a monocrystalline silicon material. The silicon substrate10may be a bulk silicon wafer (as illustrated) or may be a thin layer of silicon on an insulating layer (commonly known as silicon-on-insulator or SOI) that, in turn, is supported by a carrier wafer.

In an exemplary embodiment, the SixGeylayer12is formed from a mixture of silicon and germanium that is deposited by epitaxial growth using a mixture of silane and germane such that the SixGeylayer12has a monocrystalline structure. Either a SixGeylayer12or a Si layer14may directly contact the substrate10as the first (or lowest) of the SixGeyand Si layers12,14, and there may be a plurality of SixGeylayers12and Si layers14alternately formed overlying the substrate10. As such the SixGeylayer12and the Si layer14form a stack16, where the stack16includes one or more alternating SixGeylayers12and Si layers14. In an exemplary embodiment, the SixGeylayer12is from about 70 to about 80 weight percent silicon and from about 20 to about 30 weight percent germanium, or from about 75 to about 80 weight percent silicon and from about 20 to about 25 weight percent germanium. In this description, the weight percent silicon or germanium in the SixGeylayer12is based on the total weight of the SixGeylayer12. In one embodiment, the SixGeylayer12is about 77 percent silicon and about 23 percent germanium. As such, the SixGeylayer12has a first germanium concentration of from about 20 to about 30 weight percent germanium, or from about 20 to about 25 weight percent germanium, or about 23 weight percent germanium in various embodiments. The SixGeylayer12may have a first SixGeylayer thickness of from about 3 to about 15 angstroms (Å), or from about 3 to about 10 Å, or from about 5 to about 10 Å in various embodiments. The SixGeylayer12has a first SixGeylayer volume that depends in part on the SixGeylayer thickness.

The SixGeylayer12is eventually formed into a nanowire and used as a channel for a pFET or for an nFET. In some embodiments, the SixGeylayer12may be formed to include “N” type conductivity determining ions or “P” type conductivity determining ions, but in other embodiments the SixGeylayer12does not include appreciable quantities of conductivity determining ions. Reference to the SixGeylayer12not including appreciable quantities of conductivity determining ions means the concentration of conductivity determining ions is low enough that the conductivity determining ions do not change the conductivity of the SixGeylayer12by more than about 5% from the conductivity of pure silicon germanium. “N” type conductivity determining ions (also referred to as “dopants”) include arsenic or phosphorous, but antimony, other materials, or combinations thereof can also be used. “P” type conductivity determining ions primarily include boron, aluminum, gallium, and indium, but other materials could also be used.

In a similar manner, the Si layer14is formed by epitaxial growth with silane. In an exemplary embodiment, the Si layer14is about 95 weight percent or more silicon, or about 98 weight percent silicon or about 99 weight percent silicon in alternate embodiments. The Si layer14may have a first Si layer thickness of from about 5 to about 70 Å, or from about 10 to about 50 Å, or from about 10 to about 30 Å in various embodiments. The Si layer14has a first silicon layer volume related to the first Si layer thickness. The Si layer14may not include appreciable amounts of conductivity determining ions.

The stack16may be formed over the entire substrate10in some embodiments, and the stack16may be removed at locations where nanowires are not desired, such as locations for resistors, capacitors, or other electronic components that do not include nanowires. The stack16may be removed with a reactive ion etch using a fluorinated compound, such as silicon hexafluoride, but other etchants can be used in various embodiments. In an alternate embodiment illustrated inFIG. 2, the stack16is formed at desired locations overlying the substrate10, but the stack16is not formed over the entire substrate10. One or more shallow trench isolations18may be formed in the substrate10using methods and techniques well known to those skilled in the art, and a stack hard mask20may be formed overlying the portions of the substrate10where no stack16is to be formed. The stack hard mask20may be silicon nitride, which can be deposited by chemical vapor deposition using ammonia and dichlorosilane, and selected areas of the stack hard mask20may be covered by photoresist (not illustrated). The exposed areas of the stack hard mask20can then be removed, such as with a wet etch using hot phosphoric acid, so the surface of the substrate10is exposed where the stack16is to be formed and the surface of the substrate10is covered by the stack hard mask20at other locations. The stack16is formed by epitaxially growing alternating SixGeylayer(s)12and Si layer(s)14, as described above. The SixGeyand Si layers12,14grow from the exposed monocrystalline structure of the substrate10but not from the structure of the stack hard mask20or the shallow trench isolation18.

Referring to an exemplary embodiment inFIG. 3, the stack16is condensed by annealing to modify the SixGeyand Si layers12,14. The condensing process (also referred to as an anneal) involves heating the stack16for a certain period of time. For example, the stack16may be condensed at a temperature of from about 900 degrees centigrade (° C.) to about 1,100° C. for a time of from about 0.5 hours to about 1.5 hours. Lower temperatures may be used for longer periods of time, or the time can be reduced with higher temperatures. The condensation is performed in an oxygen ambient in some embodiments. During the condensation, the composition of the SixGeylayer12changes, where some of the silicon from SixGeylayer12migrates out such that the concentration of the germanium in the SixGeylayer12increases. For example, a second germanium concentration after the anneal may be from about 70 to about 90 weight percent, or from about 75 to about 85 weight percent, or from about 78 to about 82 weight percent in various embodiments. As such, the second germanium concentration after the anneal is greater than the first germanium concentration before the anneal. The SixGeylayer thickness decreases to a second SixGeylayer thickness as the silicon migrates out of the SixGeylayer12during the condensation, so the SixGeylayer12has a second SixGeylayer volume after the condensation that is less than the first SixGeylayer volume from before the condensation. For example, the second SixGeylayer thickness may be about 3 to about 10 Å, or about 3 to about 7 Å in various embodiments, but other thicknesses are also possible. The silicon and germanium in the SixGeylayer12is electrically conductive, so the SixGeylayer12is eventually incorporated into a FET as the nanowire.

Silicon in the Si layer14is oxidized to form silicon dioxide during the condensation. As mentioned above, the condensation is performed in an oxygen ambient at high temperatures, thus resulting in oxidation of the silicon in the Si layer14. As the silicon oxidizes, the thickness of the Si layer14increases to a second Si layer thickness greater than the first Si layer thickness. For example, the second Si layer thickness may be from about 20 to about 100 Å, or from about 20 to about 50 Å in various embodiments, but other thicknesses are also possible. As the silicon layer thickness increases to the second silicon layer thickness, the silicon layer volume also increases to a second silicon layer volume. The second silicon layer volume after the condensation is greater than the first silicon layer volume before the anneal. Silicon from the SixGeylayer12migrates into the Si layer14during the anneal, and the migrating silicon is oxidized to form silicon dioxide, so the migrating silicon further increases the second silicon layer volume and the silicon layer thickness after the anneal. The silicon dioxide formed in the Si layer14is an electrical insulator, so the Si layer14can serve as a nanowire insulator that electrically separates the SixGeylayer12nanowires from each other. The nanowire insulator formed of the Si layer14alternates between the SixGeylayer(s)12that serves as the nanowire, so the nanowire insulator overlies and underlies the SixGeylayer12nanowire.

Reference is made to the exemplary embodiment illustrated inFIG. 4, with continuing reference toFIG. 3. The stack16can be formed into a fin22, where the fin22may extend into the substrate10in some embodiments. As such, the fin22includes the SixGeyand Si layers12,14of the stack16, with a well23defined between adjacent fins22. In an exemplary embodiment, a fin hard mask24and fin photoresist (not illustrated) are formed overlying the stack16. The fin hard mask24may be silicon nitride, which can be deposited by low pressure chemical vapor deposition using ammonia and dichlorosilane, but other materials can be used in alternate embodiments. The fin photoresist and fin hard mask24are patterned and etched to leave the fin hard mask24overlying the fin22, as understood by those skilled in the art. The stack16is removed to form the well23except for where it is protected by the fin hard mask24to form a fin22or a plurality of fins22. The stack16can be removed with an anisotropic reactive ion etch using a fluorine-containing material, such as sulfur hexafluoride, but other etches are also possible. The fin22includes the SixGeylayers12and the Si layers14alternating along a height of the fin22, and the fin22may extend into the substrate10underlying the stack16.

Referring toFIG. 5, with continuing reference toFIGS. 3 and 4, an interface insulating layer28is formed overlying the fins22. The interface insulating layer28may be conformally deposited, such as by atomic layer deposition. In an exemplary embodiment, the interface insulating layer28is silicon nitride, which can be deposited using ammonia and dichlorosilane. A fin isolation insulator26is formed between adjacent fins22and overlying the interface insulating layer28. The fin isolation insulator26is silicon oxide in some embodiments, which may be deposited by chemical vapor deposition using silane and oxygen. The fin isolation insulator26may be silicon nitride or other insulating materials in alternate embodiments. The fin isolation insulator26is recessed such that it only partially fills the wells23between the fins22. In this regard, the fin isolation insulator26may be deposited and then planarized, such as to about a level equal to the top of the fin22, with chemical mechanical planarization. The fin isolation insulator26may then be further recessed with an etchant selective to the material of the fin isolation insulator26over the material of the interface insulating layer28. For example, a wet etch with dilute hydrofluoric acid removes silicon oxide preferentially to silicon nitride. The fin hard mask24is removed when the fin isolation insulator26is recessed between the fins22.

In an exemplary embodiment, the fin isolation insulator26is recessed to a level above the bottom of the stack16such that one or more SixGeylayers12of the stack16closest to the substrate10are closer to the substrate10than the exposed fin isolation insulator surface27. In alternate embodiments, the fin isolation insulator surface27may be recessed to a point closer to the substrate10than any of the SixGeylayers12in the stack16. The fin hard mask24can be removed when the fin isolation insulator26is recessed to the desired level, such as with an etchant selective to silicon nitride over silicon oxide. A wet etch with hot phosphoric acid is selective to silicon nitride, for example.

A dummy gate30is formed overlying the fins22, adjacent to a sidewall of the fins22, and overlying the fin isolation insulator26, as illustrated inFIG. 6. In an exemplary embodiment, the dummy gate30is formed by depositing polysilicon overlying the fins22, the substrate10, the interface insulating layer28, and the fin isolation insulator26. Polysilicon can be deposited by low pressure chemical vapor deposition in a silane ambient. A dummy gate hard mask32is then formed overlying the polysilicon, and patterned with photoresist (not illustrated) to leave the dummy gate hard mask32overlying the portion of the polysilicon to form the dummy gate30. The dummy gate hard mask32is silicon nitride in an exemplary embodiment, but other materials can also be used. The polysilicon is then selectively etched anisotropically to leave the dummy gate30overlying a central portion of the fins22, as well as overlying a portion of the fin isolation insulator26, as illustrated. A reactive ion etch with hydrogen bromide can be used, but other etchants are also effective, as understood by those skilled in the art. A spacer liner33may be formed overlying the dummy gate30, the fins22, and other portions of the integrated circuit8. The spacer liner33includes silicon dioxide in an exemplary embodiment, which may be deposited as described above.

Reference is made to the exemplary embodiment illustrated inFIG. 7, with continuing reference toFIG. 6. Spacers34are formed on opposite sides and adjacent to the dummy gate30. The spacers34can be formed by depositing silicon nitride overlying the dummy gate30, the dummy gate hard mask32, the fins22, the fin isolation insulator26, and the interface insulating layer28, and then anisotropically etching the silicon nitride to leave spacers34next to vertical side surfaces of the dummy gate30. A dry plasma etch with hydrogen and nitrogen trifluoride can be used to anisotropically remove the silicon nitride. The silicon nitride anisotropic etch is stopped before the dummy gate hard mask32is etched from over the dummy gate30. In an embodiment with a silicon dioxide spacer liner33and a silicon nitride interface insulating layer28, the spacer liner33may protect the interface insulating layer28from the nitride etch. In some embodiments, the ends of the fin22that extend beyond the spacers34are removed to form a source cavity36and a drain cavity38(the drain cavity38is hidden by the dummy gate30and the spacers34, but is a mirror reflection of the illustrated source cavity36). The ends of the fin22are removed with an anisotropic etchant that is selective to silicon oxide and silicon germanium over silicon nitride, and the exposed portion of the interface insulating layer28is removed from over the fin isolation insulator26. A dilute hydrofluoric acid wet etch can be used to remove the silicon oxide layers. The silicon germanium in the SixGeylayers12can be removed with an anisotropic reactive ion etch using an etchant such as sulfur fluoride or nitrogen trifluoride. In an exemplary embodiment, the source and drain cavities36,38extend from one shallow trench isolation18to an adjacent shallow trench isolation18, where the shallow trench isolation18on the right hand side ofFIG. 7and the following perspective views not illustrated to better show the structure.

A source40and drain42are then formed in the source cavity36and the drain cavity38, as illustrated in the exemplary embodiment inFIGS. 8 and 9, with continuing reference toFIG. 7, whereFIG. 9is a plan view. The source40and drain42are regrown epitaxially, so the source40and drain42grow from the exposed monocrystalline silicon (or silicon germanium) within the source and drain cavities36,38, respectively. However, the source40and drain42do not epitaxially grow from the silicon nitride or silicon oxide exposed in areas other than the source and drain cavities36,38. The source40and drain42may be formed of silicon germanium, such that the source40and drain42impart a compressive strain on the nanowires, where the nanowires are the SixGeylayer12remaining in the fin22underlying the dummy gate30and the spacers34. Alternatively, the source40and drain42may be formed of silicon carbon to impart an expansive strain on the SixGeylayer12. The source40and drain42are formed in contact with the fin22, so the source40and drain42are electrically coupled to the electrically conducive SixGeylayer12that serves as the nanowire. For a pMOS, the source40and drain42may include SixGe(1-x)where X varies from about 0.6 to about 0.8, but other concentrations or compositions are also possible. For pMOS, the source40and drain42may include silicon carbon with about 2 to about 4 weight percent carbon, but the source40and drain42may include high purity silicon or other compositions in alternate embodiments.

In some embodiments, the source40and drain42are epitaxially grown with conductivity imparting ions appropriate for the FET being formed. However, in other embodiments the source40and drain42are implanted with conductivity imparting ions, as understood by those skilled in the art. The conductivity imparting ions can be sequentially implanted in the source40and drain42for nFETs and pFETs, so each type of FET has the appropriate type of conductivity imparting ions in the source40and drain42. Alternatively, the source40and drain42can be sequentially grown with the conductivity imparting ions, so each type of FET has the appropriate type of conductivity imparting ions. In some embodiments, the source40and drain42for nFETs are formed of silicon with very little or no germanium, and the source40and drain42may include carbon to induce an expansive strain on the SixGeylayer12. The source40and drain42for pFETs may include silicon and germanium to impart a compressive strain on the SixGeylayer12, where the source40and drain42for nFETs and for pFETs are sequentially formed, as understood by those skilled in the art. For example, the source40and drain42for nFETs may include about 95 weight percent silicon, or about 98 weight percent silicon, or about 99 weight percent silicon in various embodiments. Alternatively, the source40and drain42for an nFET may be formed from silicon and germanium, and then relaxed.

Reference is made to the exemplary embodiment illustrated inFIG. 10, with continuing reference toFIGS. 8 and 9. An insulating layer50is formed between adjacent dummy gates30and overlying the fins22, the fin isolation insulator26, and the source40and drain42. The insulating layer50may be formed by depositing a silicon and nitrogen containing film using a flowable chemical vapor deposition (FCVD) process, but other materials or processes are used in alternate embodiments. In an exemplary embodiment, the FCVD is a plasma chemical vapor deposition process that can use a low carbon or carbon-free silicon containing precursor that includes silicon along with a nitrogen containing precursor. The silicon precursor may be trisilylamine, disilylamine, monosilylamine, silane, or other precursors, and the nitrogen containing precursor may be ammonia, nitrogen gas, or other compounds. The FCVD material can be converted to silicon oxide by infusion with water followed by a steam anneal, which is optionally followed by a dry anneal to densify the silicon oxide. Chemical mechanical planarization then recesses the insulating layer50to a level about even with the top of the dummy gate hard mask32.

The dummy gate30is removed after the insulating layer50is formed, but the spacers34are retained. In an exemplary embodiment, the dummy gate30is removed by first etching the dummy gate hard mask32with a hot phosphoric acid solution, and then selectively etching the polysilicon dummy gate30, such as with a reactive ion etch using hydrogen bromide, but other etch chemistries can also be used. The spacer liner33may be completely or partially removed with a selective etch in different embodiments. For example, in embodiments where the spacer liner33includes silicon dioxide, a wet etch with dilute hydrofluoric acid can be used, but other etchants are also possible. This step may be carefully optimized to terminate the etch when the desired portions of the spacer liner33are removed. The spacers34are somewhat protected by the insulating layer50. Therefore, the spacers34are largely left in place from the etch of the dummy gate hard mask32, but some recessing of the spacers34may occur. Removal of the dummy gate30exposes the portion of the fin22and the interface insulating layer28that was covered by the dummy gate30. The interface insulating layer28protects the fin22from unintended etching during the removal of the dummy gate30. The insulating layer50and the spacer34cover the remaining portion of the fin22, the source40and drain42, and the fin isolation insulator26.

Referring toFIGS. 11 and 12, with continuing reference toFIGS. 9 and 10, a replacement metal gate52is formed in the space where the dummy gate30was located.FIG. 11is a cross sectional view along plane11-11fromFIG. 10. A gate dielectric layer54is formed overlying fin22and the fin isolation insulator26. The gate dielectric layer54may be a high K dielectric material in some embodiments. As used herein, a “high K dielectric” is a dielectric material with a dielectric constant (K) of about 3.7 or greater, where K is the ratio of a material's permittivity ∈ to the permittivity of vacuum ∈o, so k=∈/∈o. Since the dielectric constant is a ratio of two similar quantities, it is dimensionless. The gate dielectric layer54may be a wide variety of materials, such as hafnium oxide or zirconium silicate. The gate dielectric layer54is formed by atomic layer deposition in an exemplary embodiment. A work function layer58may be formed overlying the gate dielectric layer54, where the work function layer58is formed from appropriate materials for the type of FET being formed.

A replacement metal gate52is then formed in the space previously occupied by the dummy gate30, but other types of gates are used in alternate embodiments. As such, the replacement metal gate52is positioned between the spacers34, and the gate dielectric layer54is positioned between the replacement metal gate52and the interface insulating layer28. The replacement metal gate52may be tungsten, aluminum, or other metals in various embodiments. For example, an aluminum replacement metal gate52may be deposited by atomic layer deposition using triisobutylaluminium. Overburden from the deposition of the replacement metal gate52may be removed by chemical mechanical planarization. The replacement metal gate52forms a FET56with nanowires (formed from the SixGeylayers12) and the other components described above. The number of SixGeylayers12in the stack16determines the number of nanowires in the FET56, and the size and number of nanowires determines the current in the FET56. The FET56can then be incorporated into an integrated circuit8using methods and techniques well known to those skilled in the art.