Latching annihilation based logic gate

The present invention provides a precharge circuit that has a first precharged node, a second precharged node, and a latch device. The first precharged node is charged to a high value during a precharge state. In response to a transition from the precharge state to an evaluate state, it either discharges to a low value or remains charged at its high value. The second precharged node has a value in the evaluate state that is based on the value of the first precharged node upon the circuit transitioning to the evaluate state. The latch device is connected to the second precharged node for latching this value in the evaluate state. With the latching device, this value is not affected by the first precharged node once the circuit has sufficiently transitioned to the evaluate state.

BACKGROUND

Precharge devices are synchronous logic circuits that generate an output depending upon a predetermined combination of inputs for implementing a logical function. Two common uses for precharge devices are as decoders and as comparators. Decoders output a unique signal (high or low) if and only if all of the bits of an input match a predetermined set of values. A decoder may thereby enable a particular write line in a matrix of memory cells if and only if an input memory address matches the predetermined address of a line of memory cells to which the decoder is connected. Similarly, a comparator will output a unique signal if and only if two inputs, each containing multiple data bits, are identical.

Precharge devices are characterized by two states, precharge and evaluate. In the precharge state, a node is charged to a known or predetermined voltage level. In the evaluate state, an array or tree of transistors configured in a basic logical function (e.g., NAND, NOR) is given the opportunity to discharge the node to a second known or predetermined voltage level or to allow the charge to persist. The logical function input signals are connected, typically, to the gates of one or more of the transistors in the logical section tree. The final charge on the node may thereby be controlled by the particular values of the inputs. The final voltage at the node, high or low, acts as the output of the precharge device after being suitably buffered and, perhaps, inverted.

Two basic logical section structures include stacked NAND and parallel NOR structures. In a stacked NAND logical section, two or more transistors are stacked in series with one another and to the precharge node. The precharged node is discharged if and only if all of the transistor gate inputs are active (e.g., high). With the parallel NOR configuration, two or more transistors are arranged in parallel with one another and across the precharged node. If any of the transistor gate inputs are active, the precharge node is discharged. In other words, the precharged node is not discharged if and only if all of the transistor gate inputs are not active. Of course, with the use of inverted or non-inverted inputs, any logical function such as a decoder may be implemented with either structure. An important concept to be understood with precharged circuits however, is monotonicity. This is a property of a signal such that it may only transition in a single direction (i.e., high to low, or low to high) during the evaluate portion of the cycle. Monotonic circuits are reset to the default value during the precharge portion of the cycle. For example, the output of a precharged NOR gate with inverted input is indeed a logical AND, but the output will have the wrong direction of transition and therefore will be unsuitable as an input to other monotonic precharged gates. For additional information relating to precharge devices, reference may be made to U.S. Pat. No. 5,291,076 to Bridges et al ( Bridges ).

In high performance applications with complicated functions that require numerous inputs, the stacked NAND structure may not be practical because the time required for discharging through a relatively large stack of transistors can be prohibitive. In fact, it is usually not feasible to use stacks of more than four transistors. Thus, the parallel NOR structure is favored. However, the primary problem with NOR structures is that for monotonic logic, they can only compute OR functions, not AND functions since inverters are necessary to achieve the correct logical sense. The Bridges reference disclosed a parallel NOR device with a screening transistor, which in effect, screens the charged node of the parallel NOR section from the output section and creates a separate charged node that discharges when the parallel charged node is to persist and persists when the parallel charged node is to discharge. Bridges also disclosed a precharge device with latching transistors for improving the device's resistance to inherent circuit instabilities. Unfortunately, neither the Bridges design (nor any other design known of in the prior art) did anything for unstable logic inputs. Separate latches are needed for each input to ensure that it is sufficiently stable to ensure that the precharge output properly reflects the input states when the circuit goes from the precharge to the evaluate phase.

Accordingly, what is needed is an improved circuit that is capable of providing a stable output without the need for stable inputs throughout the evaluation phase.

SUMMARY OF THE INVENTION

These and other objects, features and technical advantages are achieved by a system and method which the present invention provides a precharge circuit that has a first precharged node, a second precharged node, and a latch device. The first precharged node is charged to a high value during a precharge state. In response to a transition from the precharge state to an evaluate state, it either discharges to a low value or remains charged at its high value. The second precharged node has a value in the evaluate state that is based on the value of the first precharged node upon the circuit transitioning to the evaluate state. The latch device is connected to the second precharged node for latching this value in the evaluate state. With the latching device, this value is not affected by the first precharged node once the circuit has sufficiently transitioned to the evaluate state.

DETAILED DESCRIPTION

With reference to FIG. 1 , one embodiment of a precharge circuit 100 of the present invention is shown. Precharge circuit 100 performs a NOR function with inputs at A and B and an output at Z, which is monotonic. Output Z is always low in the precharge state. It can only change in one direction during the transition to the evaluate state. If circuit 100 evaluates False, Z stays low, and if it evaluates True, Z changes from low to high during the evaluate state.

Precharge device 100 includes precharge transistors Q 1 , Q 2 , evaluate transistor Q 5 , logic section 110 , clamping section 120 , screening transistor Q 4 , and output section 140 . The logic section 116 includes transistors Q 10 and Q 11 . The clamping section 120 includes inverter U 1 and clamping transistors Q 8 and Q 9 . The output section 140 includes high latch transistors Q 6 and Q 7 , low latch transistor Q 3 , and inverter U 2 , which also serves as a buffer. In the depicted embodiment, each of the transistors Q 1 -Q 11 are NFET type transistors, with the exception of Q 1 , Q 2 and Q 3 , which are PFET type transistors. The specific transistors used to implement circuit 100 are not critical. However, in one embodiment, low latch transistor Q 3 should be smaller than Q 4 and Q 5 . Inverters U 1 and U 2 are conventional inverters that may be implemented with a conventionally stacked PFET/NFET pair.

The source of precharge PFET Q 1 is connected to V DD , and its drain is connected to the node labeled ANN , which is a precharged node of the circuit. The gate of Q 1 is connected to a clock ( CLK ) signal. Transistors Q 10 and Q 11 of logic section 110 are arranged in parallel with one another with their drains and sources connected together forming a NOR gate with inputs at a and b and an output at the ANN node. The a and b inputs are at the respective gates of transistors Q 10 and Q 11 , and the ANN output is at their commonly connected drains. Their commonly connected sources are at the node marked DNG.

The ANN precharged node is connected to the input of inverter U 1 , and the output of inverter U 1 is connected to the gate of clamping transistor Q 8 . The drain of Q 8 is connected to the ANN node, and its source is connected to the DNG node. Clamping NFET Q 9 is connected in parallel across Q 8 , with its drain connected at the ANN node and its source connected at the DNG node. Its gate is connected to the circuit's output at z .

The ANN node is also connected as an input to the gate of screening transistor Q 4 . The source of screening transistor Q 4 is connected to the DNG node, which is also connected to the drain of evaluate transistor Q 5 . The gate of evaluate transistor Q 5 is connected to the clock signal, and its source is connected to ground.

The drain of screening transistor Q 4 serves as a second precharged node NOH that is inversely based on the precharged node at ANN during an evaluate state. The NOH node is connected to the drain of low latch transistor Q 3 , the input of inverter U 2 , and the drain of high latch transistor Q 6 . The source of high latch transistor Q 6 is connected to the drain of high latch transistor Q 7 , and the source of Q 7 is connected to ground. The gate of high latch transistor Q 7 is connected to the clock signal, and the gate of high latch transistor Q 6 is connected to output node Z at inverter U 2 . The gate of low latch transistor Q 3 is also connected to the Z output node, and its source is connected to V DD . Finally, the gate of precharged transistor Q 2 is connected to the clock signal, and its source is connected to V DD .

The operation of the circuit will now be described. In the depicted embodiment, the precharge state corresponds to the clock being low, and the evaluate state corresponds to the clock being high. Thus, in the precharge state when clock is low, precharge transistors Q 1 and Q 2 (which are PFETs) are turned on, and evaluate transistor Q 5 and high latch transistor Q 7 are turned off. Since Q 5 is the only possible path to ground for the precharged node ANN, node ANN is charged high with Q 1 being on during the precharge state. Likewise, as a result of Q 2 being on and Q 7 being off, the precharge node at NOH will also be high during the precharge state. Accordingly, output Z will be low, which causes low latch transistor Q 3 to be turned on and high latch transistor Q 6 to be turned off, which is consistent with NOH being high. As will be addressed in greater detail below, low and high latch transistors Q 3 , Q 6 , respectively, serve as output latches for latching the NOH node and thereby latching the output at Z during the evaluate state. It is noted that precharge circuit 100 provides a monotonic output at Z. That is, during a.transition from the precharge to evaluate state, the output can only change in one direction. In the depicted embodiment, output Z is always low during the precharge state and thus can either only transition from low to high or remain low during the evaluate state. With circuit 100 , if output Z stays low, the circuit has evaluated False. Conversely, if it transitions from low to high, the circuit has evaluated True.

The operation of the circuit in the evaluate state will now be described. For a short time after the clock transitions to the evaluate state, the ANN precharged node stays high if the A and B inputs are both low during the clock transition. This corresponds to a True evaluation, and it causes the Z output to transition from low to high. Conversely, the ANN node goes low almost concurrently with the clock's transition to the evaluate state if either A or B is high upon this transition. This corresponds to a False evaluation, and it causes the output at Z to remain low.

The case where the circuit evaluates True will now be described. For this case, reference may also be made to FIG. 2 A. With the clock transitioning from low to high, precharge transistors Q 1 and Q 2 turn off, and evaluate transistor Q 5 and high latch transistor Q 7 turn on. When both inputs and A and B are low, neither transistor Q 10 or Q 11 turns on, which allows the charge at the ANN precharge node to persist and maintain its high value long enough to turn on screening transistor Q 4 . Since evaluate transistor Q 5 is also now turned on, with the clock going from low to high, the charge at precharged node NOH is discharged through Q 4 and Q 5 , which causes NOH to go low. This causes the output at Z to switch to a high value, which corresponds to its True evaluation.

The high value at Z turns on the high latch transistor Q 6 . With Q 7 also being on at this time (with the clock going high) a direct alternative ground path is provided to NOH by high latch transistors Q 6 and Q 7 , which causes NOH to stay low whether or not Q 4 stays on. Thus, as their names imply, high latch transistors Q 6 , Q 7 serve as a latch for latching output Z high regardless of what happens with the inputs at A and B after the clock transitions to the evaluate state. All that is required for the circuit to properly evaluate high is for the A and B inputs to be low when the clock transitions to the evaluate state.

Once Z goes high, clamping transistor Q 9 turns on. This clamps the ANN node down to a low value for the remainder of the evaluate state, which makes the circuit more stable.

With reference to FIGS. 1 and 2B , the case where the circuit evaluates False will be discussed. Again, with the clock transitioning from low to high, precharge transistors Q 1 and Q 2 turn off, and evaluate transistor Q 5 and high latch transistor Q 7 turn on.

If either or both of the A and B inputs are high, one or both of transistors Q 10 and Q 11 turn on, which causes the ANN precharged node to discharge through evaluate transistor Q 5 . This results in the ANN node going low. This occurs as soon as the evaluate transistor Q 5 turns on because the activated logic section transistor(s) (Q 10 , Q 11 ) is turned on by A and/or B at least just prior to the transition. In fact, ANN goes low quickly enough to turn off screening transistor Q 4 before it can discharge precharged node NOH through evaluate transistor Q 5 . With node NOH remaining high, output Z remains low, which corresponds to a False evaluation. This keeps the low latch transistor Q 3 turned on, which reinforces the charge at NOH. In this way, low latch transistor Q 3 functions as a latch for maintaining a low value at the output Z during the evaluate state so long as Q 4 is not turned on. This is where clamping transistor Q 8 comes into play.

Clamping transistor Q 8 ensures that Q 4 does not turn on during this time when the output at Z is suppose to be low. With the ANN node being low during the evaluate state, the output at inverter U 1 is high, which causes Q 8 to turn on and clamp ANN low. This prevents it from floating and possibly going high if both A and B go low within the evaluate state. Thus, clamping transistor Q 8 ensures that screening transistor Q 4 will not turn on during the evaluate state, which would cause Z to errantly go high.

FIG. 3 shows a preferred embodiment of a precharge circuit 300 of the present invention. Like circuit 100 , precharge circuit 300 performs a NOR function with inputs at A and B and an output at Z, which is monotonic. As with circuit 100 , Z is always low in the precharge state. It can only change in one direction during a transition to the evaluate state. If circuit 300 evaluates False, Z stays low, and if it evaluates True, Z changes from low to high.

Circuit 300 generally includes precharge transistors Q 21 and Q 22 , evaluate transistor Q 25 , logic section 300 , clamping section 320 , screening transistor Q 24 , and an output section 340 . The logic section 310 , which performs a NOR gate function, includes transistors Q 30 and Q 31 . The clamping section 320 includes inverter U 21 and transistors Q 28 and Q 29 . Finally, the output section 340 includes low latch transistor Q 23 , high latch transistors Q 26 and Q 27 , and output inverter U 22 .

In the depicted embodiment, each of the transistors are NFET type transistors, with the exception of precharge transistors Q 21 and Q 22 , low latch transistor Q 23 , and clamping transistor Q 29 , which are each PFET type transistors. Particular transistor types and sizes are not generally critical so long as they properly cooperate with one another. However, in the depicted embodiment's PFET/NFET implementation, Q 29 is smaller than Q 30 and Q 31 , and Q 23 is smaller than Q 24 and Q 25 .

The precharge transistor Q 21 has its source connected to V DD , its drain connected to a precharged node marked ANN, and its gate connected to a clock ( CLK ) signal. Within logic section 310 , transistors Q 30 and Q 31 are connected in parallel with one another with their drains connected at the ANN node and sources connected at the node marked DNG. The gate of transistor Q 30 is connected to the A input, and the gate of transistor Q 31 is connected to the B input. The commonly connected sources at the DNG node are connected to the drain of evaluate transistor Q 25 . The gate of evaluate transistor Q 25 is connected to the CLK signal, and its source is connected to ground. The ANN node is also connected to the input of inverter U 21 . The output of U 21 is connected to the commonly-connected gates of clamping transistors Q 28 and Q 29 , which are connected to one another in an inverted stacked configuration. Their commonly connected drains are connected to the ANN precharged node. The source of Q 29 is connected to V DD , and the source of Q 28 is connected to the DNG node.

The ANN node is also connected to the gate of screening transistor Q 24 . The source of screening transistor Q 24 is connected to the drain of evaluate transistor Q 25 , which is at the DNG node. The drain of screening transistor Q 24 defines a second precharged node marked NOH. This NOH node is connected to the drains of precharge transistor Q 22 , low latch transistor Q 23 , and high latch transistor Q 26 . It is also connected to the input of output inverter U 22 . The output of output inverter U 22 defines the output of circuit 300 and is marked Z. This Z output is connected to the gates of low latch transistor Q 23 and high latch transistor Q 26 . Finally, the drain of high latch transistor Q 27 is connected to the source of high latch transistor Q 26 , and the source of high latch transistor Q 27 is connected to ground.

The operation of circuit 300 will now be discussed. Precharge circuit 300 is fairly similar to precharge circuit 100 , except that it includes a PFET type clamping transistor Q 29 for holding up the ANN charge throughout the evaluate state when it is to turn on screening transistor Q 24 .

Again, in the depicted embodiment, the precharge state occurs when the clock is low, and the evaluate state occurs when the clock is high. With circuit 300 being edge-triggered (as was circuit 100 )), the output at Z is based on the input values at A and B when the clock transitions from its low phase (precharge state) to its high phase (evaluate state).

In the precharge state with the clock being low, precharge transistors Q 21 and Q 22 are turned on, and evaluate transistor Q 25 and high latch transistor Q 27 are turned off Thus, during the precharge state, the ANN and NOH precharged nodes are charged to high values. With NOH being high, output Z is low during the precharge state.

With additional reference to FIG. 4A , the operation of circuit 300 will be described for the case when it evaluates true. This occurs when both A and B are low causing the ANN precharge node to be high during the evaluate transition from the precharge state. When the clock transitions from low to high, precharge transistors Q 21 and Q 22 are turned off, and evaluate transistor Q 25 and high latch transistor Q 27 turn on. With both Q 30 and Q 31 turned off, precharged node ANN remains charged to a high value. This causes screening transistor Q 24 to turn on and provide precharge node NOH with a path to ground through evaluate transistor Q 25 . This causes the precharge node NOH to discharge to a low value. As a result, output Z goes from low to high, which turns off low latch transistor Q 23 and turns on high latch transistor Q 26 . Thus, an additional ground path is provided to precharge node NOH through high latch transistors Q 26 and Q 27 . Thus, once Z goes high, high latch transistors Q 26 and Q 27 latch precharge node NOH low (which latches Z high) during the evaluate state regardless of whether Q 24 stays on or not. In other words, the NOH precharge node stays low regardless of what happens at inputs A and B during the evaluate state.

An important aspect of circuit 300 is the operation of clamping PFET Q 29 for this True evaluation case when ANN is high. With ANN being high, inverter U 21 generates a low at its output, which turns on clamping transistor Q 29 . This assists ANN in turning on the screening transistor Q 24 . This counters problematic capacitive coupling effects within screening transistor Q 24 . With advanced circuits, which have very small transistors, the effects of capacitive parasitics can be magnified. NFET Q 24 can have relatively significant capacitances between its drain and gate and between its gate and source. When the clock transitions from low to high, the NOH and DNG nodes go from high to low at approximately the same time, which induces capacitive charge sharing at its gate. This causes the voltage at ANN to droop. If the droop is severe enough, screening transistor Q 24 may not be on long enough to sufficiently discharge precharge node NOH, which would cause the output at Z to errantly stay low. However, with clamping transistor Q 29 turned on when ANN is high, any necessary additional charge is supplied to the gate at screening transistor Q 24 to ensure that it properly turns on to discharge precharged node NOH.

With additional reference to FIG. 4B , the case where circuit 300 evaluates False will be discussed. This corresponds to either of inputs A or B being high, which corresponds to either transistor Q 30 or Q 31 being turned on. With either of these transistors on, a discharge path through evaluate transistor Q 25 is provided to precharged node ANN when the clock transitions to the evaluate phase. This causes ANN to go low during this transition. With ANN going low, Q 24 is turned off, which allows the charge at recharge node NOH to persist and remain at a high value. This causes the output at Z to remain low during the evaluate state, which keeps low latch transistor Q 23 turned on and high latch transistor Q 26 turned off. This latches node NOH low so long as Q 4 remains off.

Clamping transistor Q 28 operates in the same way as clamping transistor Q 8 from circuit 100 . With ANN being low, inverter U 21 provides a high at its output, which turns on clamping transistor Q 28 . This clamps ANN low and prevents screening transistor Q 24 from inadvertently turning on and discharging node NOH. Thus, clamping transistor Q 28 serves as a latch for holding the output at Z low when the circuit is to evaluate False. In this way, the low output at Z is captured and maintained as long as either or both of inputs A and B are high when the clock transitions to the evaluate state.

The present invention provides a precharge 1 circuit that is capable of latching an output based on logical inputs during the transition from a precharge to an evaluate state. Stable input signals for the duration of the evaluate state are not required. Accordingly, separate latches for each input are not needed, which reduces the size and complexity of an IC implementation thereof.

It should be recognized that while logic sections have been described that perform NOR functions, any logical function may be implemented within the logical section and the overall precharge circuit. For example, if the inputs to A and B are inverted, the NOR gate logical section becomes an AND section. In addition, for convenience, only two inputs (A, B) have been used. However, skilled persons will recognize that any number of inputs can be attained by incorporating additional transistors into the logic section. For example, if a 32 bit decoder is desired, a logic section with 32 parallel-configured transistors could be utilized.