System and method for providing a unified global navigation satellite system (GNSS) receiver

A method and system are provided. The method includes receiving, by a GNSS receiver, a GNSS signal, rotating, by a carrier rotator, samples of the GNSS signal with carrier phase inputs, inverting, by a chip matched filter (CMF), the rotated samples, and generating, by the CMF, an output based on the inverted samples.

FIELD

The present disclosure is generally related to global navigation satellite system (GNSS) signal processing. In particular, the present disclosure is related to a unified GNSS receiver.

BACKGROUND

A GNSS receiver receives and processes signals from a GNSS satellite constellation to determine a location/position of the receiver. A GNSS receiver typically focusses on bi-phased shift keying (BPSK) modulated signals. Satellite signals are recovered and sampled at 8fx sampling rate.

Due to the emergence of GNSS such as Galileo, Beidou, and Glonass, in addition to the global positioning system (GPS), efficient and spectrally relevant signals are desired. For example, Galileo and GPS will share two central frequencies and will both send several signals on common carriers. This means that other signal modulations may be required to minimize inter-system and intra-system interference. For example, a binary offset carrier (BOC) modulation scheme provides a split spectrum that spectrally isolates the signal from the BPSK modulation. Thus, it is desirable to receive both the existing L1 signals and the new signals to enhance overall system performance. Various types of BOC signals are introduced for GPS L1C, Beidou B1C, Galileo and Glonass code division multiple access (CDMA) navigation systems.

SUMMARY

According to one embodiment, a method includes receiving, by a GNSS receiver, a GNSS signal, rotating, by a carrier rotator, samples of the GNSS signal with carrier phase inputs, inverting, by a chip matched filter (CMF), the rotated samples, and generating, by the CMF, an output based on the inverted samples.

According to one embodiment, a system includes a GNSS receiver configured to receive a GNSS signal, a carrier rotator configured to rotate samples of the GNSS signal with carrier phase inputs, and a CMF configured to invert the rotated samples and generate an output based on the inverted samples.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that the same elements will be designated by the same reference numerals although they are shown in different drawings. In the following description, specific details such as detailed configurations and components are merely provided to assist with the overall understanding of the embodiments of the present disclosure. Therefore, it should be apparent to those skilled in the art that various changes and modifications of the embodiments described herein may be made without departing from the scope of the present disclosure. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness. The terms described below are terms defined in consideration of the functions in the present disclosure, and may be different according to users, intentions of the users, or customs. Therefore, the definitions of the terms should be determined based on the contents throughout this specification.

The present disclosure may have various modifications and various embodiments, among which embodiments are described below in detail with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to the embodiments, but includes all modifications, equivalents, and alternatives within the scope of the present disclosure.

The terms used herein are merely used to describe various embodiments of the present disclosure but are not intended to limit the present disclosure. Singular forms are intended to include plural forms unless the context clearly indicates otherwise. In the present disclosure, it should be understood that the terms “include” or “have” indicate existence of a feature, a number, a step, an operation, a structural element, parts, or a combination thereof, and do not exclude the existence or probability of the addition of one or more other features, numerals, steps, operations, structural elements, parts, or combinations thereof.

The electronic device according to one embodiment may be one of various types of electronic devices. The electronic devices may include, for example, a portable communication device (e.g., a smart phone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to one embodiment of the disclosure, an electronic device is not limited to those described above.

The terms used in the present disclosure are not intended to limit the present disclosure but are intended to include various changes, equivalents, or replacements for a corresponding embodiment. With regard to the descriptions of the accompanying drawings, similar reference numerals may be used to refer to similar or related elements. A singular form of a noun corresponding to an item may include one or more of the things, unless the relevant context clearly indicates otherwise. As used herein, each of such phrases as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C,” may include all possible combinations of the items enumerated together in a corresponding one of the phrases. As used herein, terms such as “1st,” “2nd,” “first,” and “second” may be used to distinguish a corresponding component from another component, but are not intended to limit the components in other aspects (e.g., importance or order). It is intended that if an element (e.g., a first element) is referred to, with or without the term “operatively” or “communicatively”, as “coupled with,” “coupled to,” “connected with,” or “connected to” another element (e.g., a second element), it indicates that the element may be coupled with the other element directly (e.g., wired), wirelessly, or via a third element.

The present system and method provide an architecture for tracking BPSK modulated L1 signals and BOC modulated signal combinations. This allows optimal design techniques by utilizing different signal properties, enhancing the system performances and improving interference-impairment sensitivities. The architecture is design configurable to fit for both high-performance and cost-effective low-power product design.

The present disclosure provides a GNSS receiver design architecture as a unified design. The example design is showing a multiple of 12fx sampling rate domain functions (where fx=1.0230625 MHz) to handle both legacy GNSS signals and the new navigation signals.

Compared to existing legacy designs, the present system and method is capable of receiving the common legacy GNSS L1 signals as well as the new satellite signals with mixed BOC combinations such as GPS L1C with TMBOC and Beidou B1C with quadrature-multiplexed BOC (QMBOC), and helps to achieve optimal system performances. QMBOC is the TMBOC used by Beidou B1C. The present system and method are also dynamically evolving to receive future new satellite signals, projecting the future trend of new satellite signals in the mixed BOC combinations. It can be designed to support both high performance required products and cost-effective required low power products.

The present system and method handles all the GNSS satellite signals covering not only legacy GPS signals for example but also the advanced GNSS signals with various BOC signal combinations. The present system and method architecture is also dynamically evolving (i.e., the architecture can be dynamically evolved to support new satellite signals), adding benefits of time to market with the new signal support features.

The present system and method provides enhanced CMF architecture to combine time offset signals modified in a fashion to handle the various GNSS signal structures like mixed BOC and future GNSS signals, using inversion and scaling of the time segments for example. The present system and method provides a HRCE and a widely configurable correlation engine (WCCE) design architecture to utilize the enhanced CMF to produce correlation results. The HRCE is a correlation engine used to perform high resolution correlations. The WCCE is a correlation engine is used to perform widely configurable matched filter (MF) correlations and is used for satellite acquisition and tracker operations.

FIG. 1illustrates a diagram of a GNSS receiver, according to an embodiment. The GNSS receiver includes a digital mixer102, a low pass filter (LPF)104, a first-in first-out (FIFO) operation block106, a WCCE108and HRCE110. The GNSS receiver100receives a GNSS signal and passes it through the mixer102, the LPF104and the FIFO operation106. The WCCE108is used to perform widely configurable matched filter (MF) correlations and is used for satellite acquisition and tracker operations. The sampling rate is dynamically configurable with examples of 12fx and 2fx. The hardware architecture is designed to perform tracking loops in hardware or software. The HCCE110is used to perform high resolution correlations with 4 bits IQ samples and 24fx sampling. The outputs of the WCCE108and the HCCE110are buffered to a memory for software to perform GNSS satellite acquisition and tracking measurements, allowing the software to perform various GNSS signal data combining to enhance the overall system performances.

FIG. 2illustrates a diagram of different GNSS signal waveforms, according to an embodiment.FIG. 2shows a GPS signal202, a BOC(1,1) signal204, a BOC(6,1) signal206, a CBOC data signal208, and a CBOC pilot signal210.

FIG. 3illustrates a TMBOC signal, according to an embodiment. A TMBOC signal is time modulated between BOC(1,1) and BOC(6,1).FIG. 4illustrates a QMBOC signal, according to an embodiment. A QMBOC signal is concurrently transmitted between BOC(1,1) and BOC(6,1) using in-phase and quadrature-phase.

FIG. 5illustrates a diagram of a carrier rotator and CMF, according to an embodiment. As shown inFIG. 5, samples502and carrier phases504generated by a carrier phase generator506are fed into the carrier phase rotation and CMF block508to provide an output510.

FIG. 6illustrates a diagram of a CMF configuration for a GPS signal in 12fx sampling, according to an embodiment. The CMF600receives six samples (samp[0]-samp[5]). For ease of description, the first track602will be described, but the description applies to all tracks shown. The CMF600processes the signal through a rotate function604with a carrier phase input (carrPh[0]). The CMF600processes the output of the rotate function604through a scaling operation606and combines the output of the scaling operation606with the output of the rotate function604at608. The CMF600processes the output of608through an inverter610and combines the output of608with the output of the inverter610at612. The CMF600sums the output of each track at613. The CMF600sends the summation to a register delay function (reg) block614that provides a 1 clock delay to the data path and to an accumulator616. The CMF600processes the output of the reg block614through an inverter618and combines the output of the reg block614with the output of the inverter618at620. The CMF600accumulates the output of620with the summation to produce output signal622. The scaling operation606, the inverter610and the inverter618are unused for the design mode.

FIG. 7illustrates a diagram of a CMF configuration for a GPS signal in 24fx sampling, according to an embodiment. The CMF700receives twelve samples (samp[0]-samp[11]). For ease of description, the first track702will be described, but the description applies to all tracks shown. The CMF700processes the signal through a rotate summation function704with a carrier phase inputs (carrPh[0,1]). The CMF700processes the output of the rotate function704through a scaling operation706and combines the output of the scaling operation706with the output of the rotate function704at708. The CMF700processes the output of708through an inverter710and combines the output of708with the output of the inverter710at712. The CMF700sums the output of each track at713. The CMF700sends the summation to a reg block714and to an accumulator716. The CMF700processes the output of the reg block714through an inverter718and combines the output of the reg block714with the output of the inverter718at720. The CMF700accumulates the output of720with the summation to produce output signal722. The scaling operation706, the inverter710and the inverter718are unused for the design mode.

FIG. 8illustrates a diagram of a rotate summation function, according to an embodiment. The rotate summation function800includes a first rotate function802and a second rotate function804. The first rotate function802receives a sample (samp[0]) and rotates it with a carrier phase signal (carrPh[0]). The second rotate function804receives a sample (samp[1]) and rotates with a carrier phase signal (carrPh[1]). The output of each rotation function are combined with the accumulator806.

FIG. 9illustrates a diagram of a CMF configuration for a BOC(1,1) signal in 12fx sampling, according to an embodiment. The CMF900receives six samples (samp[0]-samp[5]). For ease of description, the first track902will be described, but the description applies to all tracks shown. The CMF900processes the signal through a rotate function904with a carrier phase input (carrPh[0]). The CMF900processes the output of the rotate function904through a scaling operation906and combines the output of the scaling operation906with the output of the rotate function904at908. The CMF900processes the output of908through an inverter910and combines the output of908with the output of the inverter910at912. The CMF900sums the output of each track at913. The CMF900sends the summation to a reg block914and to an accumulator916. The CMF900processes the output of the reg block914through an inverter918and combines the output of the reg block914with the output of the inverter918at920. The CMF900accumulates the output of920with the summation to produce output signal922. The scaling operation906, the inverter910and the connection between the reg block914and920are unused for the design mode.

FIG. 10illustrates a diagram of a CMF configuration for a BOC(1,1) signal in 24fx sampling, according to an embodiment. The CMF1000receives twelve samples (samp[0]-samp[11]). For ease of description, the first track1002will be described, but the description applies to all tracks shown. The CMF1000processes the signal through a rotate summation function1004with a carrier phase inputs (carrPh[0,1]). The CMF1000processes the output of the rotate function1004through a scaling operation1006and combines the output of the scaling operation1006with the output of the rotate function1004at1008. The CMF1000processes the output of1008through an inverter1010and combines the output of1008with the output of the inverter1010at1012. The CMF1000sums the output of each track at1013. The CMF1000sends the summation to a reg block1014and to an accumulator1016. The CMF1000processes the output of the reg block1014through an inverter1018and combines the output of the reg block1014with the output of the inverter1018at1020. The CMF1000accumulates the output of1020with the summation to produce output signal1022. The scaling operation1006, the inverter1010and the connection between the reg block1014and1020are unused for the design mode.

FIG. 11illustrates a diagram of a CMF configuration for a BOC(6,1) signal in 12fx sampling, according to an embodiment. The CMF1100receives six samples (samp[0]-samp[5]). For ease of description, the first track1102will be described, but the description applies to all tracks shown. The CMF1100processes the signal through a rotate function1104with a carrier phase input (carrPh[0]). The CMF1100processes the output of the rotate function1104through a scaling operation1106and combines the output of the scaling operation1106with the output of the rotate function1104at1108. The CMF1100processes the output of1108through an inverter1110and combines the output of1108with the output of the inverter1110at1112. The CMF1100sums the output of each track at1113. The CMF1100sends the summation to a reg block1114and to an accumulator1116. The CMF1100processes the output of the reg block1114through an inverter1118and combines the output of the reg block1114with the output of the inverter1118at1120. The CMF1100accumulates the output of1120with the summation to produce output signal1122. The scaling operation1106, the inverter1110and the connection between the reg block1114and1120, as well as the scaling operation1132and the connection between1134and1136in the second track1130are unused for the design mode. The unused operations for the design mode are similar for each pair of tracks.

FIG. 12illustrates a diagram of a CMF configuration for a BOC(6, 1) signal in 24fx sampling, according to an embodiment. The CMF1200receives twelve samples (samp[0]-samp[11]). For ease of description, the first track1202will be described, but the description applies to all tracks shown. The CMF1200processes the signal through a rotate summation function1204with a carrier phase inputs (carrPh[0,1]). The CMF1200processes the output of the rotate function1204through a scaling operation1206and combines the output of the scaling operation1206with the output of the rotate function1204at1208. The CMF1200processes the output of1208through an inverter1210and combines the output of1208with the output of the inverter1210at1212. The CMF1200sums the output of each track at1213. The CMF1200sends the summation to a reg block1214and to an accumulator1216. The CMF1200processes the output of the reg block1214through an inverter1218and combines the output of the reg block1214with the output of the inverter1218at1220. The CMF1200accumulates the output of1220with the summation to produce output signal1222. The scaling operation1206, the inverter1210and the connection between the reg block1214and1220, as well as the scaling operation1232and the connection between1234and1236in the second track1230are unused for the design mode. The unused operations for the design mode are similar for each pair of tracks

FIG. 13illustrates a diagram of a CMF configuration for a CBOC signal in 12fx sampling, according to an embodiment. The CMF1300receives six samples (samp[0]-samp[5]). For ease of description, the first track1302and the second track1303will be described, but the description applies to all track pairs shown. The CMF1300processes the signal through a rotate function1304with a carrier phase input (carrPh[0,1]). The CMF1300processes the output of the rotate function1304through an inverter1306and combines the output of the rotate function1304and the out of the inverter1306at1308. The CMF1300processes the output of1309through a scaling function1311. The CMF1300processes the output of1309through a first summation function1312and the output of the scaling function1311through a second summation function1314. The second track1303processes the sample (samp[1]) similarly to the first track1302. However, in the second track1303, the CMF1300processes the output of1316in the first summation function1312and the output of the scaling function1318through the second summation function1314. The output of the first summation function1312and the second summation function1314are combined at1320and1322. The CMF1300processes the output of1320through a reg block1324and the output of1322through an inverter1326. The CMF1300accumulates the output of the reg block1324and the output of the inverter1326with the accumulator1328to produce an output signal1330. The inverter1306is unused in design mode. For CBOC data, sum1 is the second input of1320and sum0 is the first input to1322. For CBOC pilot, sum1 is the first input of1320and sum0 is the second input to1322. For CBOC pilot,1308,1309and1322are inactive and1320is active.

FIG. 14illustrates a diagram of a CMF configuration for a CBOC signal in 24fx sampling, according to an embodiment. The CMF1400receives twelve samples (samp[0]-samp[11]). For ease of description, the first track1402and the second track1403will be described, but the description applies to all track pairs shown. The CMF1400processes the signal (samp[0,1]) through a rotate summation function1404with a carrier phase input (carrPh[0,1]). The CMF1400processes the output of the rotate summation function1404through an inverter1406and combines the output of the rotate summation function1404and the out of the inverter1406at1408. The CMF1400processes the output of1408through a scaling function1410. The CMF1400processes the output of1408through a first summation function1412and the output of the scaling function1410through a second summation function1414. The second track1403processes the samples (samp[2,3]) similarly to the first track1402. However, in the second track1403, the CMF1400processes the output of1409in the first summation function1412and the output of the scaling function1411through the second summation function1414. The output of the first summation function1412and the second summation function1414are combined at1420and1422. The CMF1400processes the output of1420through a reg block1424and the output of1422through an inverter1426. The CMF1400accumulates the output of the reg block1424and the output of the inverter1426with the accumulator1428to produce an output signal1430. The inverter1406is unused in design mode. For CBOC data, sum1 is the first input of1422and sum0 is the second input to1420. For CBOC pilot, sum1 is the first input of1420and sum0 is the second input to1422. For CBOC pilot,1408,1409and1422are inactive, and1422is active.

A single output stream of samples is produced with samples separated from each other by one microsecond (usec). It is desirable to produce multiple concurrent streams of samples, with each stream containing samples on usec apart, but the streams offset from each other by a fraction of a usec. This allows correlation against a reference code to provide correlation taps that are a fraction of a usec apart.

FIG. 15illustrates a diagram of multiple stream CMF in GPS and BOC(1,1), according to an embodiment. For WCCE, there are 6 outputs according to a 1/12 chip separation. For HRCE, there are 12 outputs according to a 1/24 chip separation. The logic produced multiple outputs of the same functionality using delay chains. Six input samples1502-1512are rotated at1514with their corresponding carrier phases. Samples1504-1512are processed at corresponding delay functions1520-1528and are summed at1530to produce ½ chip summations1532. In GPS, the delayed ½ chip summations are added to the ½ chip summations to produce the full 1 us chip summation. In BOC(1, 1), the delayed ½ chip summations are subtracted from the ½ chip summations to produce the full 1 us chip summation. Delay chains are used to created six delayed copies (twelve for a 1/24 chip spaced example) of the full chip summations.

FIG. 16illustrates a diagram of multiple stream CMF in BOC(6,1) and CBOC, according to an embodiment.FIG. 16shows the CMF functions used in HRCE and WCCE for BOC(6, 1) and CBOC with 1/12 chip spacing. Six input samples1602-1612are rotated at1614with their corresponding carrier phases. Samples1604-1612are processed at corresponding delay functions1620-1628. The six rotated outputs are alternately inverted (scaled instead of inverted for CBOC) with the outputs of delay functions1620-1628as represented by the alternating squares and circles at1630and are then summed to produce the chip summations1632. The delayed ½ chip summations are subtracted from the ½ chip summations to produce the full 1 us chip summation. The delay chains1620-1628are used to create six delayed copies of the full chip summations. With 1/24 chip spacing (not shown), twelve input samples are rotated with their corresponding carrier phases. Adjacent pairs of the rotated samples are added together. The six added outputs are alternatively inverted (scaled instead of inverted for CBOC) and then summed together to produce ½ chip summations.

FIG. 17illustrates a diagram of full chip summation of two ½ chips, according to an embodiment. The circuit1702receives ½ chip summations1704and processes the ½ chip summation through a reg block1706. The output of the reg block1706is processed through a BOC selection block1708for inversion selection. The summation1704is added at1710with the output of the BOC selection block1708, and the result is passed to a quantizer1712. The output of the circuit1702is the 1 us summation1714. For GPS, the delayed ½ chip summations are added to the ½ chip summations to produce the full 1 us chip summation. For BOC(1, 1), BOC(6, 1) and CBOC, the delayed ½ chip summations are subtracted from the ½ chip summations to produce the full 1 us chip summation.

FIG. 18illustrates a diagram of an HRCE, according to an embodiment. The HRCE corresponds to TMBOC. The HRCE1800includes a carrier rotator1802and a CMF1804. The CMF1804outputs a BOC(1, 1) signal and a BOC(6, 1) signal. The system processes the output of the CMF1804through a BOC selection block1806corresponding to an n selection. The system processes the selection of the BOC selection block1806with a correlator bank1808that correlates the selection from the BOC selection block1806with a PN code for the n selection. The system also processes the output of the CMF1804through a BOC selection block1810for an n+1 selection. The system processes the selection of the BOC selection block1810with a correlator bank1812that correlates the selection of the BOC selection block1810with a pseudo node (PN) code for the n+1 selection. The system processes the outputs of the correlator banks1808and1812through a register array1814. Samples are selected on code chip by code chip basis between BOC(1,1) and BOC(6,1). The BOC(1,1)/BOC(6,1) selection is time aligned with the generated PN code. The design is enabled to achieve optimal system performances using both BOC(1,1) signal and BOC(6,1) signal. Compared to BOC(1,1) based designs it allows a gain in C/N0 of about 1.12 dB.

FIG. 19illustrates a diagram of an HRCE, according to an embodiment. The HRCE corresponds to QMBOC. The HRCE1900includes a carrier rotator1902and a CMF1904. The CMF1904outputs a BOC(1, 1) signal and a BOC(6, 1) signal. The system processes the output of the CMF1904through a BOC selection block1906corresponding to a sample selection. The system processes the selection of the BOC selection block1906with a correlator bank1908that correlates the selection from the BOC selection block1906with a PN code for the n selection. The system also processes the output of the CMF1904through a BOC selection block1910for a sample selection. The system processes the selection of the BOC selection block1910with a correlator bank1912that correlates the selection of the BOC selection block1910with a PN code for the n+1 selection. The system processes the outputs of the correlator banks1910and1912through a register array1914. The QMBOC signal is handled as an example shown using 2 channels, one for BOC(1,1) and one for BOC(6,1). The combination produces the complex IQ correlation. Compared to BOC(1,1) based designs it allows a gain in C/N0 of about 0.56 dB.

FIG. 20illustrates a diagram of a WCCE, according to an embodiment. The WCCE corresponds to TMBOC. The WCCE2000includes a carrier rotator2002, a CMF2004and a matched filter (MF)2005. The CMF2004outputs a BOC(6, 1) sample and a BOC(1, 1) sample. The system processes the samples at a BOC selection block2006. Based on a BOC(6, 1) selection output of a coder2008, the system selects a sample with the BOC selection block2006. The selected sample is then processed with a PN code output from the coder2008, and by coherent integration2010, the system produces an output2012. The WCCE2000shown is illustrated for the WCCE architecture for TMBOC with 12fx sampling. TMBOC is handled by the CMF2004producing both BOC(1,1) and BOC(6,1) into concurrent sample delay chains. Samples are selected on slice by slice basis between BOC(1,1) and BOC(6,1). The BOC(1,1)/BOC(6,1) selection is time aligned with the generated PN code. Compared to BOC(1,1) based designs it allows a gain in C/N0 of about 1.12 dB. The system includes multiple MF slices (e.g.,2014).

FIG. 21illustrates a diagram of a matched filter slice in TMBOC, according to an embodiment. The MF slice2102includes a correlation output2104. The BOC selection block2106selects a BOC sample based on a BOC(6, 1) selection from a coder2108. The selected sample is then accumulated at2110with a PN code from the coder2108to produce the correlation output2104.

FIG. 22illustrates a diagram of a WCCE, according to an embodiment. The WCCE corresponds to QMBOC. The WCCE2200includes a carrier rotator2202, a CMF2204and an MF2205. The CMF2204outputs a BOC(6, 1) sample and a BOC(1, 1) sample. The system processes the samples at a BOC selection block2206. The selected sample is then processed with a PN code output from the coder2208, and by coherent integration2210, the system produces an output2212. The WCCE2200shown is illustrated for the WCCE architecture for QMBOC with 12fx sampling. It also works for legacy GPS and Galileo designs. For QMBOC, it is shown by using 2 channels as an example, one for BOC(1,1) and one for BOC(6,1). The combination produces the complex IQ correlation. Compared to BOC(1,1) based designs it allows a gain in C/N0 of about 0.56 dB. The WCCE2200also gives a unified design for both legacy signals and new BOC signal combinations. The system includes multiple matched filter (MF) slices (e.g.,2214).

FIG. 23illustrates a diagram of a matched filter slice in QMBOC, according to an embodiment. The MF slice2302includes a correlation output2304. A sample is selected at a BOC selection block2306based on an input sample selection2308. The selected sample2310is then accumulated at2314with a PN code output from a coder2312to produce the correlation output2304.

FIG. 24illustrates a block diagram of an electronic device2401in a network environment2400, according to one embodiment. Referring toFIG. 24, the electronic device2401in the network environment2400may communicate with another electronic device2402via a first network2498(e.g., a short-range wireless communication network), or another electronic device2404or a server2408via a second network2499(e.g., a long-range wireless communication network). The electronic device2401may also communicate with the electronic device2404via the server2408. The electronic device2401may include a processor2420, a memory2430, an input device2450, a sound output device2455, a display device2460, an audio module2470, a sensor module2476, an interface2477, a haptic module2479, a camera module2480, a power management module2488, a battery2489, a communication module2490, a subscriber identification module (SIM)2496, or an antenna module2497. In one embodiment, at least one (e.g., the display device2460or the camera module2480) of the components may be omitted from the electronic device2401, or one or more other components may be added to the electronic device2401. In one embodiment, some of the components may be implemented as a single integrated circuit (IC). For example, the sensor module2476(e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) may be embedded in the display device2460(e.g., a display).

The processor2420may execute, for example, software (e.g., a program2440) to control at least one other component (e.g., a hardware or a software component) of the electronic device2401coupled with the processor2420, and may perform various data processing or computations. As at least part of the data processing or computations, the processor2420may load a command or data received from another component (e.g., the sensor module2476or the communication module2490) in volatile memory2432, process the command or the data stored in the volatile memory2432, and store resulting data in non-volatile memory2434. The processor2420may include a main processor2421(e.g., a central processing unit (CPU) or an application processor (AP)), and an auxiliary processor2423(e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that is operable independently from, or in conjunction with, the main processor2421. Additionally or alternatively, the auxiliary processor2423may be adapted to consume less power than the main processor2421, or execute a particular function. The auxiliary processor2423may be implemented as being separate from, or a part of, the main processor2421.

The auxiliary processor2423may control at least some of the functions or states related to at least one component (e.g., the display device2460, the sensor module2476, or the communication module2490) among the components of the electronic device2401, instead of the main processor2421while the main processor2421is in an inactive (e.g., sleep) state, or together with the main processor2421while the main processor2421is in an active state (e.g., executing an application). According to one embodiment, the auxiliary processor2423(e.g., an ISP or a CP) may be implemented as part of another component (e.g., the camera module2480or the communication module2490) functionally related to the auxiliary processor2423.

The memory2430may store various data used by at least one component (e.g., the processor2420or the sensor module2476) of the electronic device2401. The various data may include, for example, software (e.g., the program2440) and input data or output data for a command related thereto. The memory2430may include the volatile memory2432or the non-volatile memory2434.

The program2440may be stored in the memory2430as software, and may include, for example, an operating system (OS)2442, middleware2444, or an application2446.

The input device2450may receive a command or data to be used by other component (e.g., the processor2420) of the electronic device2401, from the outside (e.g., a user) of the electronic device2401. The input device2450may include, for example, a microphone, a mouse, or a keyboard.

The sound output device2455may output sound signals to the outside of the electronic device2401. The sound output device2455may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as playing multimedia or recording, and the receiver may be used for receiving an incoming call. According to one embodiment, the receiver may be implemented as being separate from, or a part of, the speaker.

The display device2460may visually provide information to the outside (e.g., a user) of the electronic device2401. The display device2460may include, for example, a display, a hologram device, or a projector and control circuitry to control a corresponding one of the display, hologram device, and projector. According to one embodiment, the display device2460may include touch circuitry adapted to detect a touch, or sensor circuitry (e.g., a pressure sensor) adapted to measure the intensity of force incurred by the touch.

The audio module2470may convert a sound into an electrical signal and vice versa. According to one embodiment, the audio module2470may obtain the sound via the input device2450, or output the sound via the sound output device2455or a headphone of an external electronic device2402directly (e.g., wired) or wirelessly coupled with the electronic device2401.

The sensor module2476may detect an operational state (e.g., power or temperature) of the electronic device2401or an environmental state (e.g., a state of a user) external to the electronic device2401, and then generate an electrical signal or data value corresponding to the detected state. The sensor module2476may include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

The interface2477may support one or more specified protocols to be used for the electronic device2401to be coupled with the external electronic device2402directly (e.g., wired) or wirelessly. According to one embodiment, the interface2477may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

A connecting terminal2478may include a connector via which the electronic device2401may be physically connected with the external electronic device2402. According to one embodiment, the connecting terminal2478may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

The haptic module2479may convert an electrical signal into a mechanical stimulus (e.g., a vibration or a movement) or an electrical stimulus which may be recognized by a user via tactile sensation or kinesthetic sensation. According to one embodiment, the haptic module2479may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

The camera module2480may capture a still image or moving images. According to one embodiment, the camera module2480may include one or more lenses, image sensors, ISPs, or flashes.

The power management module2488may manage power supplied to the electronic device2401. The power management module2488may be implemented as at least part of, for example, a power management integrated circuit (PMIC).

The battery2489may supply power to at least one component of the electronic device2401. According to one embodiment, the battery2489may include, for example, a primary cell which is not rechargeable, a secondary cell which is rechargeable, or a fuel cell.

The communication module2490may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device2401and the external electronic device (e.g., the electronic device2402, the electronic device2404, or the server2408) and performing communication via the established communication channel. The communication module2490may include one or more CPs that are operable independently from the processor2420(e.g., the AP) and supports a direct (e.g., wired) communication or a wireless communication. According to one embodiment, the communication module2490may include a wireless communication module2492(e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module2494(e.g., a local area network (LAN) communication module or a power line communication (PLC) module). A corresponding one of these communication modules may communicate with the external electronic device via the first network2498(e.g., a short-range communication network, such as Bluetooth™, wireless-fidelity (Wi-Fi) direct, or a standard of the Infrared Data Association (IrDA)) or the second network2499(e.g., a long-range communication network, such as a cellular network, the Internet, or a computer network (e.g., LAN or wide area network (WAN)). These various types of communication modules may be implemented as a single component (e.g., a single IC), or may be implemented as multiple components (e.g., multiple ICs) that are separate from each other. The wireless communication module2492may identify and authenticate the electronic device2401in a communication network, such as the first network2498or the second network2499, using subscriber information (e.g., international mobile subscriber identity (IMSI)) stored in the subscriber identification module2496.

The antenna module2497may transmit or receive a signal or power to or from the outside (e.g., the external electronic device) of the electronic device2401. According to one embodiment, the antenna module2497may include one or more antennas, and, therefrom, at least one antenna appropriate for a communication scheme used in the communication network, such as the first network2498or the second network2499, may be selected, for example, by the communication module2490(e.g., the wireless communication module2492). The signal or the power may then be transmitted or received between the communication module2490and the external electronic device via the selected at least one antenna.

At least some of the above-described components may be mutually coupled and communicate signals (e.g., commands or data) therebetween via an inter-peripheral communication scheme (e.g., a bus, a general purpose input and output (GPIO), a serial peripheral interface (SPI), or a mobile industry processor interface (MIPI)).

According to one embodiment, commands or data may be transmitted or received between the electronic device2401and the external electronic device2404via the server2408coupled with the second network2499. Each of the electronic devices2402and2404may be a device of a same type as, or a different type, from the electronic device2401. All or some of operations to be executed at the electronic device2401may be executed at one or more of the external electronic devices2402,2404, or2408. For example, if the electronic device2401should perform a function or a service automatically, or in response to a request from a user or another device, the electronic device2401, instead of, or in addition to, executing the function or the service, may request the one or more external electronic devices to perform at least part of the function or the service. The one or more external electronic devices receiving the request may perform the at least part of the function or the service requested, or an additional function or an additional service related to the request, and transfer an outcome of the performing to the electronic device2401. The electronic device2401may provide the outcome, with or without further processing of the outcome, as at least part of a reply to the request. To that end, a cloud computing, distributed computing, or client-server computing technology may be used, for example.

One embodiment may be implemented as software (e.g., the program2440) including one or more instructions that are stored in a storage medium (e.g., internal memory2436or external memory2438) that is readable by a machine (e.g., the electronic device2401). For example, a processor of the electronic device2401may invoke at least one of the one or more instructions stored in the storage medium, and execute it, with or without using one or more other components under the control of the processor. Thus, a machine may be operated to perform at least one function according to the at least one instruction invoked. The one or more instructions may include code generated by a complier or code executable by an interpreter. A machine-readable storage medium may be provided in the form of a non-transitory storage medium. The term “non-transitory” indicates that the storage medium is a tangible device, and does not include a signal (e.g., an electromagnetic wave), but this term does not differentiate between where data is semi-permanently stored in the storage medium and where the data is temporarily stored in the storage medium.

Although certain embodiments of the present disclosure have been described in the detailed description of the present disclosure, the present disclosure may be modified in various forms without departing from the scope of the present disclosure. Thus, the scope of the present disclosure shall not be determined merely based on the described embodiments, but rather determined based on the accompanying claims and equivalents thereto.