Inter-thread load arbitration control detecting information registered in commit stack entry units and controlling instruction input control unit

The information processing device in the simultaneous multi-threading system is operated in an inter-thread performance load arbitration control method, and includes: an instruction input control unit for sharing among threads control of inputting an instruction in an arithmetic unit for acquiring the instruction from memory and performing an operation on the basis of the instruction; a commit stack entry provided for each thread for holding information obtained by decoding the instruction; an instruction completion order control unit for updating the memory and a general purpose register depending on an arithmetic result obtained by the arithmetic unit in an order of the instructions input from the instruction input control unit; and a performance load balance analysis unit for detecting the information registered in the commit stack entry and controlling the instruction input control unit.

FIELD

The present invention relates to an information processing device, and more specifically to an information processing device in a simultaneous multi-threading system, and also to a load arbitration control method for arbitrating a performance load balance among a plurality of threads.

BACKGROUND

Recently, in the field of information processing devices, a super-scalar system for improving the use efficiency of each execution unit by parallelizing the processes of arithmetic operations, an out-of-order instruction executing system for improving the use efficiency of the execution unit by sequentially executing a plurality of independent instructions regardless of the occurrence order in a program, etc., are generally well known as means for improving overall performance.

However, in an information processing devices using the above-mentioned systems, all the internal execution units (arithmetic unit etc.) are operating, and the parallelism is not best utilized.

Therefore, a system of best utilizing the parallelism specific to an information processing device by processing instruction sequences not related to one another among a plurality of threads after distributing internal resources that are not being completely used in a single thread to the plurality of threads has been proposed as simultaneous multi-threading (SMT).

In SMT, even if a resource is shared by instruction sequences of a plurality of threads to improve the use efficiency, the resource cannot be used by other threads while the shared resource is used by one thread. Therefore, once a thread occupies the shared resource for a long time, another thread cannot continue processing, which is a problem.

SUMMARY

The present invention has been developed to solve the above-mentioned problem, and provides an information processing device in a simultaneous multi-threading system for arbitrating the performance load balance among threads by qualitatively determining the load balance among the threads, and also provides an inter-thread performance load arbitration control method.

The information processing device in the simultaneous multi-threading system according to an aspect of the present invention includes: an instruction input control unit for sharing among threads control of inputting an instruction to an arithmetic unit for acquiring the instruction from memory and performing an operation on the basis of the instruction; a commit stack entry provided for each thread for holding information obtained by decoding the instruction; an instruction completion order control unit for updating, in an order of the instructions input from the instruction input control unit, the memory and a general purpose register depending on an arithmetic result obtained by the arithmetic unit; and a performance load balance analysis unit for detecting the information registered in the commit stack entry and controlling the instruction input control unit on the basis of the result of the detection.

It is preferable that the instruction completion order control unit define the time in which the information is not registered in the commit stack entry as the time in which the thread does not perform instruction processing, and generate an empty flag indicating only the commit stack entry in which the information is not registered is empty.

It is preferable that the performance load balance analysis unit predetermine an instruction input priority request threshold for each commit stack entry, count the time in which the empty flag generated for each commit stack entry is issued, compare a priority thread value resulting from the counting on the commit stack entry with the instruction input priority request threshold, and generate an instruction input priority request flag for switching to the thread corresponding to the commit stack entry in which the empty flag is issued when the priority thread value exceeds the instruction input priority request threshold.

It is preferable that the performance load balance analysis unit predetermine a release threshold for release of the instruction input priority request flag for each commit stack entry, calculate a difference value indicating a difference between the priority thread value and a second priority thread value as a calculation of the time in which the empty flag generated for each commit stack entry in which another instruction input priority request flag is generated is issued, compare the difference value with the release threshold, and release an instruction input priority request flag for switching to the thread corresponding to the commit stack entry in which the empty flag is issued when the difference value exceeds the release threshold.

It is preferable that the instruction completion order control unit include an instruction continuing time monitor unit for outputting to the instruction input control unit a hang-up warning to avoid causing a hang-up by forcibly fixing the thread so as to release the instruction input priority of the thread which has input the instruction when the instruction processing of a suppressed thread is suspended for a predetermined time.

It is preferable that the instruction input control unit switch the thread in each cycle when all threads can input the instruction in a timely manner, and select a thread that can input the instruction when only one thread can input the instruction in a timely manner.

The present invention is an inter-thread performance load arbitration control method in a simultaneous multi-threading system, and includes: an instruction input control step of controlling an input timing of an instruction so as to acquire the instruction from memory and perform an operation on the basis of the instruction for each thread; and a performance load balance analyzing step of detecting information registered in the commit stack entry provided for each thread for holding the information obtained by decoding the instruction, and controlling the input of the instruction on the basis of the result of the detection.

It is preferable that the performance load balance analyzing step define the time in which the information is not registered in the commit stack entry as the time in which the thread does not perform instruction processing, and generate an empty flag indicating that only the commit stack entry in which the information is not registered is empty.

It is preferable that the performance load balance analyzing step predetermine an instruction input priority request threshold for each commit stack entry, count the time in which the empty flag generated for each commit stack entry is issued, compare a priority thread value resulting from the counting on the commit stack entry with the instruction input priority request threshold, and generate an instruction input priority request flag for switching to the thread corresponding to the commit stack entry in which the empty flag is issued when the priority thread value exceeds the instruction input priority request threshold.

It is preferable that the performance load balance analyzing step predetermine a release threshold for release of the instruction input priority request flag for each commit stack entry, calculate a difference value indicating a difference between the priority thread value and a second priority thread value as a calculation of the time in which the empty flag generated for each commit stack entry in which another instruction input priority request flag is generated is issued, compare the difference value with the release threshold, and release an instruction input priority request flag for switching to the thread corresponding to the commit stack entry in which the empty flag is issued when the difference value exceeds the release threshold.

It is preferable that the instruction input priority of the thread which has input the instruction is released when the instruction processing of a suppressed thread is suspended for a predetermined time.

It is preferable that the instruction input control step switch the thread in each cycle when all threads can input the instruction in a timely manner, and select a thread that can input the instruction when only one thread can input the instruction in a timely manner.

According to the present invention, the load balance among threads can be qualitatively determined, and the performance load balance among the threads can be arbitrated.

DESCRIPTION OF EMBODIMENTS

(Explanation of the Principle)

The information processing device according to an embodiment of the present invention is operated in a super-scalar system and an out-of-order instruction executing system, and realizes a simultaneous multi-threading system. The information processing device has a constitution wherein an instruction input control unit for controlling the input of an instruction from memory to an arithmetic unit is shared among threads, and an instruction completion order management unit for managing an instruction completion order can be multiplexed for each thread. The information processing device also has a performance load balance analysis unit for detecting, on the basis of the use situation of an instruction completion order unit, that there is occurring an unbalanced number of instruction execution cycles of each thread.

According to the information processing device configured above, when a bias in a performance load balance is detected, a thread for inputting an instruction is fixed. In addition, the performance load balance of each thread is arbitrated. Further, fixing a thread for inputting an instruction is suppressed so as not to over-suppress the process of a thread having a low priority.

The embodiments of the present invention are described below in detail with reference to the attached drawings.

FIG. 1illustrates a configuration of an information processing device1in the simultaneous multi-threading system. In the present embodiment, the information processing device1is configured by memory2, an instruction acquisition control unit3, an instruction input control unit4, an instruction analysis unit5, an instruction issue control unit6, an instruction completion order control unit7, an arithmetic unit8, and a performance load balance analysis unit9.

The memory2functions as cache or the like in the information processing device1. The instruction acquisition control unit3is provided with an instruction buffer10, performs control to acquire an instruction to perform an operation from the memory2, and holds the acquired instruction in the instruction buffer10.

The instruction input control unit4reads the instruction held in the instruction buffer10, and transfers it to the instruction analysis unit5. In addition, the instruction input control unit4limits the processing in the same cycle to one thread with respect to the instruction held in the instruction buffer10, and inputs the instruction of one thread to the instruction analysis unit5while switching threads in each cycle as necessary.

The instruction analysis unit5decodes the instruction transferred from the instruction input control unit4. The instruction issue control unit6controls an issuing of an instruction for performing the process corresponding to each code decoded by the instruction analysis unit5. The arithmetic unit8performs an operation or the like on the basis of an operand provided from the instruction issue control unit6.

The instruction completion order control unit7provides each thread with a commit stack entry12A (CSE0) and a commit stack entry12B (CSE1) for holding the information about the instruction decoded by the instruction analysis unit5, determines whether or not the instruction can be completed according to the information registered in the commit stack entries12A and12B, and resets the information about the instruction upon completion of the instruction. That is, information is registered in the commit stack entries12A and12B between a dispatch stage and a commit stage, and during this time, any kind of instruction processing can be executed.

The instruction completion order control unit7is also provided with an instruction continuing time monitor unit11. The instruction continuing time monitor unit11is a circuit for monitoring the hang-up.

A commit stack entry (CSE: Commit Stack Entry) is a buffer, and is assigned one entry for each instruction, and is used in monitoring the progress of the instruction being executed. In addition, the entries of the commit stack entry are nullified when an instruction executed in order according to the order of the instructions of the program is committed.

In addition, inFIG. 1, there are only two commit stack entries for the 2SMT, but two or more commit stack entries can be provided. The instruction completion order control unit7is connected to the instruction analysis unit5and determines whether or not the instruction can be completed according to the information registered in the commit stack entries12A and12B. Upon completion of the instruction, the information about the instruction is reset.

The performance load balance analysis unit9is connected to the instruction completion order control unit7, detects the contents of the commit stack entries12A and12B, and controls the instruction input control unit4on the basis of the result of the detection.

In addition, it is assumed that the information processing device according to the present invention is operated in the SMT system, and each thread is operated in the super-scalar and out-of-order systems.

As illustrated inFIG. 2, it is assume that the information processing device1has a fetch stage, a present stage, a decode stage, a dispatch stage, an execute stage, an update-buffer stage, and a commit stage in an instruction pipeline.

In the fetch stage, an instruction is read from the memory2to the instruction buffer10to allow the arithmetic unit8for executing the instruction to execute the instruction on the basis of the control of the instruction acquisition control unit3.

In the present stage, an instruction is input from the instruction buffer10to the instruction analysis unit5on the basis of the control of the instruction input control unit4.

In the decode stage, an instruction is decoded by the instruction analysis unit5.

In the dispatch stage, an instruction is issued to the instruction execution resources such as the arithmetic unit8etc. under the control of the instruction issue control unit6.

In the execute stage, an instruction is executed by the instruction execution resources such as the arithmetic unit8.

In the update-buffer stage, an execution result is awaited.

In the commit stage, the memory2and a general purpose register (although not illustrated in the attached drawings, connected to the arithmetic unit8via the data transfer bus and the control bus) are updated under the control of the instruction completion order control unit7in the instruction order on the basis of the execution result.

In these stages, the fetch stage, the present stage, the decode stage, and the commit stage are operated in order in the instruction order. The dispatch stage, the execute stage, and the update-buffer stage are operated not in the instruction order but in an out-of-order system in which instructions are executed when they are ready for execution regardless of the instruction order.

(Performance Load Balance Analysis Unit)

FIG. 3illustrates a circuit of the performance load balance analysis unit9. The performance load balance analysis unit9is connected to the instruction input control unit4and the instruction completion order control unit7.

The performance load balance analysis unit9predetermines an instruction input priority request threshold for each commit stack entry. Then, the performance load balance analysis unit9counts the time in which an empty flag generated for each commit stack entry is issued, and compares the priority thread value resulting from the counting corresponding to the commit stack entry with the instruction input priority request threshold. When the priority thread value exceeds the instruction input priority request threshold, it is determined that the instruction processing balance is biased to the thread opposite the thread in which the empty flag is issued, and an instruction input priority request flag of the thread in which the empty flag is issued is generated to arbitrate the instruction processing balance.

In addition, the performance load balance analysis unit9predetermines a release threshold for release of an instruction input priority request flag for each commit stack entry. The performance load balance analysis unit9calculates a difference value between the priority thread value and a second priority thread value as a calculation of the time in which the empty flag generated for each commit stack entry in which another instruction input priority request flag is generated is issued. Then, the difference value is compared with the release threshold, and when the difference value exceeds the release threshold, it is determined that the bias of the instruction processing balance has been corrected, and the instruction input priority request flag of the thread in which the empty flag is issued is released.

In the present embodiment, an SMT having two thread is described for simplicity.

Assuming that a cycle in which no information is registered in a commit stack entry of a thread is a time in which the thread is not performing instruction processing, and an instruction input priority request flag (BALANCE_PRIORITY_REQ_TH_0) indicating that only one commit stack entry is empty is issued (defined as a load balance analysis element).

The performance load balance analysis unit9is configured by a counter circuit31, a comparator32(for thread0), a comparator33(for thread1), a comparator34(for thread0), a comparator35(for thread1), a latch circuit36(for thread0), and a latch circuit37(for thread1).

The counter circuit31is connected to the instruction completion order control unit7to acquire an empty flag indicating that only the commit stack entry12A of the thread0is empty. The counter circuit31is also connected to the input terminals of the comparator32, the comparator33, the comparator34, and the comparator35.

In addition, the counter circuit31is a counter for acquiring an empty flag (CSE_EMPTY_TH_0_ONLY) indicating that only the thread0is empty from the commit stack entry12A in the instruction completion order control unit7, and an empty flag (CSE_EMPTY_TH_1_ONLY) indicating that only the thread1is empty from the commit stack entry12B in the instruction completion order control unit7, and performing counting when these empty flags are “high”.

The set terminal (SET) of the latch circuit36is connected to the output terminal of the comparator32. The reset terminal (RESET) of the latch circuit36is connected to the output terminal of the comparator33. The output signal of the latch circuit36is output to the instruction input control unit4.

The set terminal (SET) of the latch circuit37is connected to the output terminal of the comparator34. The reset terminal (RESET) of the latch circuit37is connected to the output terminal of the comparator35. The output signal of the latch circuit37is output to the instruction input control unit4.

Since the 2SMT is assumed in the present embodiment, the area can be reduced by the configuration of a counter specialized for the 2SMT.

Since the purpose of the counter circuit31is to distinguish the difference of a cycle in which only the commit stack entry of one thread is empty, it is configured as a counter for adding −1 when the level of CSE_EMPTY_TH_0_ONLY is “high”, and +1 when the level of CSE_EMPTY_TH_1_ONLY is “high”. That is, it is understood that the instruction processing of one thread only for either is being performed.

For example, when the state in which only the commit stack entry12B of the thread1is empty continues and the bias to the instruction processing of the thread0is detected, the value of the counter is added by CSE_EMPTY_TH_1_ONLY to indicate the level of the bias by the value of “+”, and is reduced by CSE_EMPTY_TH_0_ONLY to indicate the correction of the bias. On the other hand, when the bias to the thread1is detected, the bias is indicated by the value of “−”.

In the thread1, an instruction input priority request threshold (+A) of “+” is set for the comparator34. In the thread0, an instruction input priority request threshold (−A) of “−” is set for the comparator32.

When the value (difference value) of the counter of the counter circuit31is smaller than “−A”, it is determined that a large bias to the thread1is detected, and an instruction input priority request (BALANCE_PRIORITY_REQ_TH_0) of the thread0is issued.

The set terminal of the latch circuit36is set to “high” and is output to the instruction input control unit4.

On the other hand, when the value of the counter of the counter circuit31exceeds “+A”, it is determined that a large bias to the thread0is detected, and the instruction input priority request (BALANCE_PRIORITY_REQ_TH_1) of the thread1is set to “high” and output to the instruction input control unit4.

As for correction of the bias, other thresholds, “+B”/“−B”, which indicate release thresholds are set. When the value (difference value) of the counter circuit31becomes smaller than “+B”, it is determined that the bias of the thread1has been corrected, and BALANCE_PRIORITY_REQ_TH_1is set to “low”. Thus, BALANCE_PRIORITY_REQ_TH_1is controlled so that it is set to “high” only when the bias is large.

Also, when the value (difference value) of the counter circuit31becomes larger than “−B”, it is determined that the bias of the thread0has been corrected, and BALANCE_PRIORITY_REQ_TH_0is set to “low”. Thus, BALANCE_PRIORITY_REQ_TH_0is controlled so that it is set to “high” only when the bias is large.

Since BALANCE_PRIORITY_REQ_TH_0and BALANCE_PRIORITY_REQ_TH_1are set when the values of the counter are “−A” or less and “+A” or more respectively, they are not simultaneously set to “high”.

In the present embodiment, the case using the counter circuit31is described above, but the counter can be prepared for each thread so as to use the value for comparison.

FIG. 4illustrates a circuit of the instruction input control unit4. The instruction input control unit4outputs an instruction to the instruction analysis unit5while switching the threads at a specific timing. When the instruction can be input in all threads in a timely manner, the threads are switched every cycle. When the instruction can be input by only one thread in a timely manner, the thread capable of inputting instructions is selected and outputs the instruction to the instruction analysis unit5, thereby performing an instruction inputting operation with a minimized loss.

The circuit for the thread0of the instruction input control unit4is configured by an AND circuit41(3-input logical product circuit), an AND circuit42(2-input logical product circuit), an AND circuit43(2-input logical product circuit), an AND circuit44(3-input logical product circuit), an AND circuit45(2-input logical product circuit), an OR circuit46(3-input logical sum circuit), an OR circuit47(3-input logical sum circuit), and a latch circuit48.

The circuit for the thread1of the instruction input control unit4is configured by the AND circuit44(3-input logical product circuit), an AND circuit410(2-input logical product circuit), an AND circuit411(2-input logical product circuit), the AND circuit41(3-input logical product circuit) an AND circuit413(2-input logical product circuit), an OR circuit414(3-input logical sum circuit), an OR circuit415(3-input logical sum circuit), and a latch circuit416.

A circuit for the thread0is described below.

The a input terminal of the AND circuit41is connected to the performance load balance analysis unit9for acquisition of BALANCE_PRIORITY_REQ_TH_0when a thread instruction input priority request is issued. The b input terminal of the AND circuit41acquires an instruction input enable request (ENABLE_PRESENT_OPERATION_TH_0) indicating that an instruction can be input in the thread0from the instruction buffer10to the instruction analysis unit5. The b input terminal of the AND circuit41is also connected to the a input terminal of the AND circuit42, the a input terminal of the AND circuit43, and the a input terminal (inverse input) of the OR circuit47.

The c input terminal of the AND circuit41is connected to the instruction continuing time monitor unit11to acquire a hang-up warning (WARNING_TO_HANG_OPERATION) described later. The c input terminal of the AND circuit41is also connected to the c input terminal (inverse input) of the AND circuit44. The output terminal (FORCE_THREAD_TO_0) of the AND circuit41is connected to the a input terminal of the OR circuit46.

PRESENT_OPERATION_TH_1for the thread1of the instruction input control unit4described later is input to the b input terminal of the AND circuit42. The output terminal of the AND circuit42is connected to the b input terminal of the OR circuit46.

The instruction input enable request (ENABLE_PRESENT_OPERATION_TH_1) indicating that an instruction can be input in the thread0from the instruction buffer10to the instruction analysis unit5is input to the b input terminal (inverse input) of the AND circuit43. The b input terminal of the AND circuit43is also connected to the b input terminal of the AND circuit44and the a input terminal of the AND circuit45. The output terminal of the AND circuit43is connected to the c input terminal of the OR circuit46.

The a input terminal of the AND circuit44is connected to the performance load balance analysis unit9to acquire BALANCE_PRIORITY_REQ_TH_1. The output terminal (FORCE_THREAD_TO_1) of the AND circuit44is connected to the b input terminal of the OR circuit47. The output terminal of the AND circuit45is connected to the c input terminal of the OR circuit47.

The output terminal of the OR circuit46is connected to the set terminal (SET) of the latch circuit48, and the output of the OR circuit47is connected to the reset terminal (RST) of the latch circuit48.

The output terminal (PRESENT_OPERATION_TH_0) of the latch circuit48is connected to the b input terminal of the AND circuit45.

A circuit for the thread1is described below.

The a input terminal of the OR circuit414is connected to the output FORCE_THREAD_TO_1of the AND circuit44described above relating to the circuit for the thread0.

The b input terminal of the OR circuit415is connected to the output FORCE_THREAD_TO_0of the AND circuit41described above relating to the circuit for the thread0.

PRESENT_OPERATION_TH_0for the thread0of the instruction input control unit4described later is input to the b input terminal of the AND circuit410. The output terminal of the AND circuit410is connected to the b input terminal of the OR circuit414.

The instruction input enable request (ENABLE_PRESENT_OPERATION_TH_0) indicating that an instruction can be input in the thread0from the instruction buffer10to the instruction analysis unit5is input to the b input terminal (inverse input) of the AND circuit411. The b input terminal of the AND circuit411is also connected to the a input terminal of the AND circuit413. The output terminal of the AND circuit411is connected to the c input terminal of the OR circuit414.

The output terminal of the AND circuit413is connected to the c input terminal of the OR circuit415.

The output terminal of the OR circuit414is connected to the set terminal (SET) of the latch circuit416, and the output of the OR circuit415is connected to the reset terminal (RST) of the latch circuit416.

The output terminal (PRESENT_OPERATION_TH_1) of the latch circuit416is connected to the b input terminal of the AND circuit413.

When a bias occurs in the performance load balance, the instruction input control unit4with the configuration above prioritizes the thread0when BALANCE_PRIORITY_REQ_TH_0is “high”, prioritizes the thread1when BALANCE_PRIORITY_REQ_TH_1is “high”, and selects the thread of the instruction output to the instruction analysis unit5, thereby realizing the arbitration of the performance load balance.

However, when the thread in which an instruction is input on a priority basis is suspended for any reason, the process cannot be performed even though the instruction is input. Therefore, there is a possibility that the processes will be suspended in both threads at worst. Accordingly, a thread is selected fixedly on a priority basis only when the thread to be prioritized is in a state in which an instruction can be input (ENABLE_PRESENT_OPERATION_TH_1) in a timely manner, thereby reducing the possibility of a hang-up (WARNING_TO_HANG_OPERATION) due to the suppression of the input of an instruction in the opposite thread.

That is, in the AND circuit41, if a thread instruction input priority request in the thread0is issued, BALANCE_PRIORITY_REQ_TH_0is “high”, ENABLE_PRESENT_OPERATION_TH_0is “high” and an instruction can be input in a timely manner, and WARNING_TO_HANG_OPERATION is “low” without an occurrence of a hang-up, then the output FORCE_THREAD_TO_0is set to “high”. In this case, the latch circuit48is set to “high” regardless of the level of the other input terminal of the OR circuit46.

The AND circuit42sets the latch circuit48as “high” once in two cycles if an instruction can be input in the threads0and1. That is, if an instruction is input in the thread1in the preceding cycle, PRESENT_OPERATION_TH_1becomes “high”, and ENABLE_PRESENT_OPERATION_TH_0is “high”. Therefore, the output of the AND circuit42becomes “high”.

The AND circuit43sets “high” for the latch circuit48if an instruction can be input only in the thread0. Since ENABLE_PRESENT_OPERATION_TH_0is “high” and ENABLE_PRESENT_OPERATION_TH_1is “low”, the output of the AND circuit43becomes “high”.

The latch circuit48is set to “high” depending on the above condition determined by the AND circuit41, the AND circuit42, and the AND circuit43.

The output of the AND circuit44becomes “high” when the thread1is designated. That is, when a thread instruction input priority request is issued in the thread0, BALANCE_PRIORITY_REQ_TH_1becomes “high”. If ENABLE_PRESENT_OPERATION_TH_1is “high” and an instruction can be input in a timely manner, and WARNING_TO_HANG_OPERATION is “low” without an occurrence of a hang-up, the AND circuit44sets the output FORCE_THREAD_TO_1as “high”. In this case, the latch circuit48is reset to “low” regardless of the level of the other input terminal of the OR circuit47.

The AND circuit45resets the latch circuit48as “low” once in two cycles if an instruction can be input in the threads0and1. That is, if an instruction is input in the thread0in the preceding cycle, PRESENT_OPERATION_TH_0becomes “high” and ENABLE_PRESENT_OPERATION_TH_1is “high”. Therefore, the output of the AND circuit45becomes “high”.

The latch circuit48is reset to “low” depending on the above condition determined by the AND circuit44, the AND circuit45, and ENABLE_PRESENT_OPERATION_TH_0.

The control is performed on the circuit for the thread1as in the thread0.

That is, in the AND circuit44, when a thread instruction input priority request in the thread1is issued and FORCE_THREAD_TO_1becomes “high”, the latch circuit416is set to “high” regardless of the level of the other input terminal of the OR circuit414.

The AND circuit410sets the latch circuit416as “high” once in two cycles if an instruction can be input in the threads0and1. That is, if an instruction is input in the thread0in the preceding cycle, PRESENT_OPERATION_TH_0becomes “high”, and ENABLE_PRESENT_OPERATION_TH_1is “high”. Therefore, the output of the AND circuit410becomes “high”.

The AND circuit411sets the latch circuit416as “high” if an instruction can be input only in the thread0. Since ENABLE_PRESENT_OPERATION_TH_1is “high” and ENABLE_PRESENT_OPERATION_TH_0is “low”, the output of the AND circuit411becomes “high”.

The latch circuit416is set to “high” depending on the above condition determined by the AND circuit44, the AND circuit410, and the AND circuit411.

When a thread instruction input priority request in the thread0is issued and FORCE_THREAD_TO_0becomes “high” in the AND circuit41, the latch circuit416is reset to “low” regardless of the level of the other input terminal of the OR circuit415.

If an instruction can be input in the threads0and1, the AND circuit413resets the latch circuit416as “low” once in two cycles. If an instruction is input in the thread1in the preceding cycle, PRESENT_OPERATION_TH_1becomes “high” and ENABLE_PRESENT_OPERATION_TH_0is “high”. Therefore, the output of the AND circuit413becomes “high”.

The latch circuit416is reset to “low” depending on the above condition determined by the AND circuit41, the AND circuit413, and ENABLE_PRESENT_OPERATION_TH_0.

(Instruction Continuing Time Monitor Unit)

Furthermore, by releasing a fixing of a thread in which an instruction is input when the instruction processing of a suppressed thread is suspended for a predetermined time, the possibility of causing a hang-up by forcibly fixing a thread can be avoided.

The instruction continuing time monitor unit11is a circuit for monitoring the hang-up. The instruction continuing time monitor unit11prepares a counter for resetting a value upon completion of the process of an instruction by performing counting every cycle. Since the counter continues counting while an instruction is not completed, it indicates the time in which the instruction of the thread is suspended in some stage to the commit stage. In the present embodiment, the instruction continuing time monitor unit11sets a threshold “C” of the counter, and when the counter value exceeds the threshold “C” in any thread, it outputs a hang-up warning (WARNING_TO_HANG_OPERATION) to the instruction input control unit4and requests that the arbitration of the performance load balance stop.

In the present embodiment, the case in the 2SMT is described. It is also possible, when the number of threads increases, to prioritize inputting an instruction to a thread when the cycle in which a commit stack entry of each thread is empty is counted and the difference becomes larger after comparing the counter value of the thread with a value of the other thread. With this configuration, the performance load balance can be arbitrated.

FIG. 5illustrates a circuit of the instruction continuing time monitor unit11.

The instruction continuing time monitor unit11is configured by a counter circuit51, a counter circuit52, a comparator53, a comparator54, and an OR circuit55(2-input logical sum circuit).

The counter circuit51inputs a clock (CLK) from an input terminal (+) and performs counting. An instruction completion notification in the thread0output from the instruction completion order control unit7, that is, COMMIT_OPERATION_TH_0, is received by the reset terminal (RST).

The counter circuit52inputs a clock (CLK) from the input terminal (+) and performs counting. An instruction completion notification in the thread1output from the instruction completion order control unit7, that is, COMMIT_OPERATION_TH_1, is received by the reset terminal (RST).

The comparator53predetermines “C” as a threshold of a counter, and outputs “high” from the output terminal when the count value of the counter circuit51exceeds “C”.

The comparator54predetermines “C” as a threshold of the counter, and outputs “high” from the output terminal when the count value of the counter circuit51exceeds “C”.

The OR circuit55(2-input logical sum circuit) inputs the output of the comparator53and the comparator54to the a input terminal and the b input terminal respectively, and outputs a hang-up warning (WARNING_TO_HANG_OPERATION).

(Operation of Information Processing Device)

FIG. 6is a time chart of an operation of the information processing device according to the present embodiment. The operation of the circuit described above is described with reference to the time chart.

From period1to period2, the empty flag (1) CSE_EMPTY_TH_0_ONLY indicating that only the commit stack entry12A is empty changes from “low” to “high”.

While (1) CSE_EMPTY_TH_0_ONLY input to the counter circuit31of the performance load balance analysis unit9is “high”, the counter circuit31continues counting, and the count value (3) BALANCE_COUNTER is output from the output terminal of the counter circuit31.

From period3, the counter circuit31adds “−1” for each clock. The count value is increased, and the addition is performed up to period5in which a preset value “−A” is reached.

In period6, the output of the comparator32changes to “high”, and the latch circuit36is set to “high”. As a result, the output (4) BALANCE_PRIORITY_REQ_TH_0of the latch circuit36is changed to “high”. In this case, if BALANCE_PRIORITY_REQ_TH_0is input to the instruction input control unit4and to the a terminal of the AND circuit41, and the instruction input enable request ENABLE_PRESENT_OPERATION_TH_0is “high”, then (7) WARNING_TO_HANG_OPERATION is “low”. Therefore, the output (8) FORCE_THREAD_TO_0of the AND circuit41becomes “high”. The latch circuit48is set to “high”.

In period7, the addition is further performed in the thread0and the count value becomes “−X”. In period8, since the commit stack entry12A is not empty any more, the empty flag (1) CSE_EMPTY_TH_0_ONLY changes from “high” to “low”. Since both CSE_EMPTY_TH_0_ONLY and CSE_EMPTY_TH_1_ONLY are “low”, the count value does not change as the output of the counter circuit31until period9.

In period10, the empty flag (2) CSE_EMPTY_TH_1_ONLY indicating that only the commit stack entry12B is empty changes from “low” to “high”.

In period11, “1” is added to “−X”, then the count value is increased for each clock, and the addition is performed up to period16in which a predetermined value “−B” is reached.

In period14, when the value of (6) HANG_COUNTER exceeds a predetermined threshold “C” and (7) WARNING_TO_HANG_OPERATION becomes “high”, “high” is input to the c input terminal of the AND circuit41, and the output FORCE_THREAD_TO_0of the AND circuit41becomes “low”. In this case, forcing the inputting of an instruction in the thread0is released.

In period16, the count value of the counter circuit31becomes larger than “−B”. Thus, it is determined that the bias of the instruction processing balance among the threads has been corrected, the output of the comparator33outputs “high”, and the latch circuit36is reset. Therefore, BALANCE_PRIORITY_REQ_TH_0becomes “low”.

From period17to period18, CSE_EMPTY_TH_0_ONLY keeps “high” as is, and when the addition is performed until a predetermined value “+A” is reached, (5) BALANCE_PRIORITY_REQ_TH_1becomes “high”. In this case, since (7) WARNING_TO_HANG_OPERATION is kept at “high”, the forcible selection of the thread in which an instruction is input is cancelled.

(Flowchart of the Operation of the Present Embodiment)

FIG. 7is an explanatory view of the flowchart of the operation in the thread0according to the present embodiment.

The steps S71through S79are described below (performance load balance analyzing step).

In step S71, it is determined whether or not the commit stack entry in the thread0is empty. If the commit stack entry in the thread0is empty, control is passed to step S72. If it is not empty, control is passed to step S76.

In step S72, it is determined whether or not the commit stack entry in the thread1is empty. If the commit stack entry in the thread1is empty, control is passed to step S710. If it is not empty, control is passed to step S73. When CSE_EMPTY_TH_0_ONLY output from the commit stack entry12A in the thread0is “high”, control is passed to step S73.

In step S73, while CSE_EMPTY_TH_0_ONLY is “high”, “−1” is added to the counter for monitoring the balance for each clock. That is, while “high” is input to the input terminal (−1) of the counter circuit31illustrated inFIG. 3, “−1” is added for each clock.

In step S74, it is determined whether or not the count value of the counter for monitoring the balance is larger than a predetermined instruction input priority request threshold “−A”. If it is larger than “−A”, control is passed to step S710. If it is equal to or smaller than “−A”, control is passed to step S75.

The value of the output BALANCE_COUNTER of the counter circuit31is compared with the instruction input priority request threshold set in the comparator32, and the result is output.

In step S75, BALANCE_PRIORITY_REQ_TH_0is set to “high”.

In this case, the RST input terminal of the latch circuit36is “low”.

In step S76, it is determined whether or not a commit stack entry in the thread1is empty. If the commit stack entry in the thread1is empty, control is passed to step S710. If it is not empty, control is passed to step S77. When CSE_EMPTY_TH_1_ONLY output from the commit stack entry12A in the thread1is “high”, control is passed to step S77.

In step S77, “+1” is added to the counter for monitoring the balance. When CSE_EMPTY_TH_0_ONLY becomes “low”, and while CSE_EMPTY_TH_1_ONLY is “high”, “+1” is added for each clock. That is, while “high” is input to the input terminal (+1) of the counter circuit31illustrated inFIG. 3, “+1” is added for each clock.

In step S78, it is determined whether or not the count value of the balance monitor counter is smaller than a predetermined release threshold “−B”. If it is smaller than “−B”, control is passed to step S710. If it is equal to or larger than “−B”, control is passed to step S79.

The value of the output BALANCE_COUNTER of the counter circuit31is compared with the release threshold set in the comparator33. If the count value (difference value) exceeds the release threshold, “high” is output.

In step S710, it is determined whether or not an instruction can be input in the thread0. If an instruction can be input, control is passed to step S711. If it cannot be input, control is passed to step S717. It is determined whether or not ENABLE_PRESENT_OPERATION_TH_0indicating that an instruction in the thread0can be input from the instruction acquisition control unit3is “high”.

In step S711, it is determined whether or not BALANCE_PRIORITY_REQ_TH_0is “high”. If it is “high”, control is passed to step S712. If it is “low”, control is passed to step S713.

In step S712, if the instruction continuing time of both threads is smaller than a predetermined hang-up threshold “C”, control is passed to step S716. If it is larger than the hang-up threshold “C”, control is passed to step S713. That is, if WARNING_TO_HANG_OPERATION is “low”, an instruction in the thread0can be input.

In step S713, it is determined whether or not an instruction in the thread1is input in the preceding cycle.

If it is input, control is passed to step S716. If it is not input, control is passed to step S714. It is determined whether or not PRESENT_OPERATION_TH_1is “high”.

In steps S714and S717, it is determined whether or not an instruction in the thread1can be input. If it can be input, control is passed to step S715. It is determined whether or not ENABLE_PRESENT_OPERATION_TH_1is “high”.

In step S715, an instruction in the thread1is input. In step S716, an instruction in the thread0is input. In step S718, no instruction is input.

The operation of the thread1is similar to the operation of the thread0. Steps S71′ through S718′ correspond to steps S71through S718.

In step S71′, it is determined whether or not a commit stack entry in the thread1is empty. If the commit stack entry in the thread1is empty, control is passed to step S72′. If it is not empty, control is passed to step S76′.

In step S72′, it is determined whether or not the commit stack entry in the thread0is empty. If the commit stack entry in the thread0is empty, control is passed to step S710′. If it is not empty, control is passed to step S73′. When CSE_EMPTY_TH_1_ONLY output from the commit stack entry12B in the thread1is “high”, control is passed to step S73′.

In step S73′, while CSE_EMPTY_TH_1_ONLY is “high”, “+1” is added to the counter for monitoring the balance for each clock. That is, while “high” is input to the input terminal (+1) of the counter circuit31illustrated inFIG. 3, “+1” is added for each clock.

In step S74′, it is determined whether or not the count value of the counter for monitoring the balance is smaller than a predetermined instruction input priority request threshold “+A”. If it is smaller than “+A”, control is passed to step S710′. If it is equal to or smaller than “+A”, control is passed to step S75′

The value of the output BALANCE_COUNTER of the counter circuit31is compared with the instruction input priority request threshold set in the comparator34, and the result is output.

In step S75′, BALANCE_PRIORITY_REQ_TH_1is set to “high”. In this case, the RST input terminal of the latch circuit37is “low”.

In step S76′, it is determined whether or not the commit stack entry in the thread0is empty. If the commit stack entry in the thread0is empty, control is passed to step S710′. If it is not empty, control is passed to step S77′. When CSE_EMPTY_TH_0_ONLY output from the commit stack entry12B in the thread0is “high”, control is passed to step S77′.

In step S77′, “−1” is added to the counter for monitoring the balance. When CSE_EMPTY_TH_1_ONLY becomes “low” and while CSE_EMPTY_TH_0_ONLY is “high”, “−1” is added for each clock. That is, while “high” is input to the input terminal (−1) of the counter circuit31illustrated inFIG. 3, “−1” is added for each clock.

In step S78′, it is determined whether or not the count value of the balance monitor counter is larger than a predetermined release threshold “+B”. If it is larger than “+B”, control is passed to step S710′. If it is equal to or smaller than “+B”, control is passed to step S79′

The value of the output BALANCE_COUNTER of the counter circuit31is compared with the thread set in the comparator35, and if the count value (difference value) exceeds the release threshold, “high” is output.

In step S710′, it is determined whether or not an instruction in the thread1can be input. If it can be input, control is passed to step S711′. If it cannot be input, control is passed to step S717′. It is determined whether or not ENABLE_PRESENT_OPERATION_TH_1indicating that an instruction in the thread1can be input from the instruction acquisition control unit3is “high”.

In step S711′, it is determined whether or not BALANCE_PRIORITY_REQ_TH_1is “high”. If it is “high”, control is passed to step S712′. If it is “low”, control is passed to step S713′.

In step S712′, if the instruction continuing time of both threads is smaller than a predetermined hang-up threshold “C”, control is passed to step S716′. If it is larger than the hang-up threshold “C”, control is passed to step S713′. That is, if WARNING_TO_HANG_OPERATION is “low”, an instruction in the thread1can be input.

In step S713′, it is determined whether or not an instruction in the thread0is input in the preceding cycle. If it is input, control is passed to step S716′. If it is not input, control is passed to step S714′. It is determined whether or not PRESENT_OPERATION_TH_0is “high”.

In steps S714′ and S717′, it is determined whether or not an instruction in thread0can be input. If it can be input, control is passed to step S715′. It is determined whether or not ENABLE_PRESENT_OPERATION_TH_1is “high”.

In step S715′, an instruction in the thread0is input. In step S716′, an instruction in the thread1is input. In step S718′, no instruction is input.

The present invention is not limited to the embodiments above, but can be flexibly improved and changed within the scope of the gist of the present invention.