SOI substrates and SOI devices, and methods for forming the same

An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.

FIELD OF THE INVENTION

The present invention generally relates to improved semiconductor-on-insulator (SOI) substrates and SOI devices, and methods for forming such SOI substrates and SOI devices. More specifically, the present invention relates to SOI substrates that contain patterned buried insulator layers at varying depths, and SOI devices that are formed in such SOI substrates with the patterned buried insulator layers self-aligned to the SOI device junctions.

BACKGROUND OF THE INVENTION

Semiconductor-on-insulator (SOI) technology is becoming increasingly important in semiconductor processing. A SOI substrate structure typically contains a buried insulator layer, which functions to electrically isolate a top semiconductor layer from a bottom semiconductor substrate. Active devices, such as transistors, are typically formed in the top semiconductor layer of the SOI substrate.

Devices formed using SOI technology (i.e., SOI devices) offer many advantages over their bulk counterparts, including, but not limited to: reduction of junction leakage, reduction of junction capacitance, reduction of short channel effects, better device performance, higher packing density, and lower voltage requirements.

However, a charge can build up in the body of the SOI devices, which in turn leads to undesirable floating body effects that adversely impact the device performance. Further, as the SOI devices are scaled down, the contact resistance in the SOI devices is significantly increased. In order to reduce the contact resistance, raised source and/or drain structures are typically employed in ultra-thin SOI devices, which increases the manufacturing costs as well as the defect density of the SOI devices.

There is therefore a need for improved SOI substrates and SOI devices with reduced floating body effects and reduced contact resistance. There is also a need for a simple and effective method of fabricating the improved SOI substrates and SOI devices at reduced costs with fewer defects.

SUMMARY OF THE INVENTION

The present invention solves the above-described problems of conventional SOI structures by providing improved SOI substrates comprising patterned buried insulator layers located at varying depths of such SOI substrates. Further, improved SOI devices can be formed in such SOI substrates with the patterned buried insulator layers self-aligned to the SOI device junctions in such a manner as to reduce the floating body effects and the contact resistance, but without increasing the junction leakage and the junction capacitance.

In one aspect, the present invention relates to a semiconductor-on-insulator (SOI) substrate having a substantially planar upper surface with a patterned buried insulator layer located therein, wherein the SOI substrate comprises first regions that do not contain any buried insulator, second regions that contain first portions of the patterned buried insulator layer at a first depth from the substantially planar upper surface, and third regions that contain second portions of the patterned buried insulator layer at a second depth from the substantially planar upper surface, and wherein the first depth is larger than the second depth.

Preferably, the first depth ranges from about 20 nm to about 200 nm, and the second depth ranges from about 10 nm to about 100 nm.

The first portions of the patterned buried insulator layer may have an average thickness that is either substantially the same as, or smaller/larger than, that of the second portions of the patterned buried insulator layer.

When the first portions of the patterned buried insulator layer have an average thickness that is substantially the same as that of the second portions of the patterned buried insulator layer, it is preferred that both the first and second portions of the patterned buried insulator layer have an average thickness ranging from about 10 nm to about 200 nm.

Alternatively, when the first portions of the patterned buried insulator layer have an average thickness that is smaller than that of the second portions of the patterned buried insulator layer, it is preferred that the first portions of the patterned buried insulator layer have an average thickness ranging from about 10 nm to about 200 nm, and the second portions of the patterned buried insulator layer have an average thickness ranging from about 20 nm to about 400 nm.

Further, when the first portions of the patterned buried insulator layer have an average thickness that is larger than that of the second portions of the patterned buried insulator layer, it is preferred that the first portions of the patterned buried insulator layer have an average thickness ranging from about 20 nm to about 400 nm, and the second portions of the patterned buried insulator layer have an average thickness ranging from about 10 nm to about 200 nm.

In another aspect, the present invention relates to a semiconductor device that comprises one or more field effect transistors (FETs). Specifically, the one or more FETs comprise: (1) one or more channel regions located in a semiconductor-on-insulator (SOI) substrate that has a substantially planar upper surface, wherein the channel regions do not contain any buried insulator, (2) source and drain regions located in the SOI substrate on opposite sides of the one or more channel regions, wherein the source and drain regions contain first portions of a patterned buried insulator layer at a first depth from the substantially planar upper surface of the SOI substrate, and (3) source and drain extension regions located in the SOI substrate between the channel regions and the source and drain regions, respectively, wherein the source and drain extension regions contain second portions of the patterned buried insulator layer at a second depth from the substantially planar upper surface of the SOI substrate, and wherein the first depth is larger than the second depth.

In this manner, the patterned buried insulator layer of the SOI substrate is self-aligned to the channel regions, source/drain regions, and source/drain extension regions of the one or more FETs, so as to reduce the floating body effects and the source/drain contact resistance, but without increasing the junction leakage and the junction capacitance in the FETs.

In still another aspect, the present invention relates to a method for forming a semiconductor-on-insulator (SOI) substrate, which comprises:

forming a semiconductor substrate having a substantially planar upper surface with predetermined first, second, and third regions;

conducting one or more ion implantation steps to selectively implant oxygen and/or nitrogen ions into the second and third regions, but not the first regions, of the semiconductor substrate; and

conducting one or more annealing steps to convert the implanted oxygen and/or nitrogen ions into buried insulator,

wherein the first regions of the semiconductor substrate do not contain any buried insulator, wherein the second regions of the semiconductor substrate contain first portions of a patterned buried insulator layer at a first depth from the substantially planar upper surface, wherein the third regions of the semiconductor substrate contain second portions of the patterned buried insulator layer at a second depth from the substantially planar upper surface, and wherein the first depth is larger than the second depth.

In a specific embodiment of the present invention, a single ion implantation step is employed for implanting oxygen and/or nitrogen ions into the second and third regions, but not the first regions, of the semiconductor substrate. Preferably, the first regions of the semiconductor substrate are covered during the single ion implantation step by first masking structures that are sufficient to completely block implantation of oxygen and/or nitrogen ions in the first regions. The second regions of the semiconductor substrate are exposed during the single ion implantation step so that oxygen and/or nitrogen ions are implanted into the second regions at the first depth. The third regions of the semiconductor substrate are covered during the single ion implantation step by second masking structures that are sufficient to reduce implantation depth of oxygen and/or nitrogen ions in the third regions to the second depth.

More specifically, the first masking structures may comprise either dielectric block masks or gate conductors with dielectric block masks located thereover. The second masking structures may comprise either dielectric spacers that are formed by a deposition and etching process or oxide masks that are formed by a high-density plasma (HDP) process.

In an alternative embodiment of the present invention, at least a first and a second ion implantation steps are employed to implant oxygen and/or nitrogen ions into the second and third regions of the semiconductor substrate. Preferably, but not necessarily, the first ion implantation step implants oxygen and/or nitrogen ions at the first depth from the substantially planar upper surface of the semiconductor substrate, and the second implantation step implants oxygen and/or nitrogen ions at the second depth from the substantially planar upper surface of the semiconductor substrate. During both the first and second ion implantation steps, the first regions of the semiconductor substrate are covered, so that no oxygen and/or nitrogen ions are implanted in the first regions. The second regions of the semiconductor substrate are implanted with oxygen and/or nitrogen ions only during the first ion implantation step so that ion implantation depth in the second regions is equal to the first, larger depth. The third regions of the semiconductor substrate are implanted with oxygen and/or nitrogen ions either only during the second ion implantation step, or during both the first and second ion implantation steps, so that the final ion implantation depth in the third regions is equal to the second, smaller depth.

In a further alternative embodiment of the present invention, multiple ion implantation and multiple annealing steps are employed in order to form a high quality patterned buried insulator layer as described hereinabove.

In yet another aspect, the present invention relates to a method for fabricating a semiconductor device, which comprises:

forming a semiconductor-on-insulator (SOI) substrate having a substantially planar upper surface with a patterned buried insulator layer located therein, wherein the SOI substrate comprises first regions that do not contain any buried insulator, second regions that contain first portions of the patterned buried insulator layer at a first depth from the substantially planar upper surface, and third regions that contain second portions of the patterned buried insulator layer at a second depth from the substantially planar upper surface, and wherein the first depth is larger than the second depth; and
forming one or more field effect transistors (FETs), which comprise: (1) one or more channel regions located in the first regions of the SOI substrate, (3) source and drain regions located in the second regions of the SOI substrate, and (4) source and drain extension regions located in the third regions of the SOI substrate.

Other aspects, features and advantages of the invention will be more fully apparent from the ensuing disclosure and appended claims.

DETAILED DESCRIPTION OF THE INVENTION

The term “patterned” as used herein refers to the discontinuity of a layered structure. For example, a patterned buried insulator layer is discontinuous in the SOI substrate, i.e., it extends to certain regions of the SOI substrate, but is completely absent in other regions of the SOI substrate.

The term “substantially planar” as used herein refers to the smoothness of a surface defined by surface protrusions or depressions of less than about 10 nm in height or depth.

The term “depth” as used in association with the patterned buried insulator layer (or portions thereof) refers to the average distance between an upper surface of the patterned buried insulator layer (or portions thereof) and an upper surface of the substrate in which the patterned buried insulator layer is located.

The term “thickness” as used herein refers to the average thickness of a layer or similar structure.

The term “substantially the same” as used herein refers to a parameter variation of not more than ±10%.

The present invention provides improved SOI substrates that comprise patterned buried insulator layers located at varying depths of such SOI substrates. Specifically, each of the SOI substrates of the present invention has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth.

The present invention also provides improved SOI devices, which are formed in the above-described SOI substrates. Specifically, the patterned buried insulator layers are self-aligned to the SOI device junctions in such a manner as to reduce the floating body effects and the contact resistance, but without increasing the junction leakage and the junction capacitance.

FIG. 1shows a cross-sectional view of an exemplary SOI device, which contains two FETs20and40located in a SOI substrate10.

The SOI substrate10may comprise any semiconductor material including, but not limited to: Si, SiC, SiGe, SiGeC, Ge alloys, GaAs, InAs, InP, other III-V or II-VI compound semiconductors, or organic semiconductor structures. In some embodiments of the present invention, it is preferred that the SOI substrate10be composed of a Si-containing semiconductor material, i.e., a semiconductor material that includes silicon. Further, the SOI substrate10may be doped, undoped, or contain both doped and undoped regions therein (not shown).

The SOI substrate10has a substantially planar upper surface11, and it contains a patterned (i.e., discontinuous) buried insulator layer12therein. The patterned buried insulator layer12may comprise any suitable insulator material(s), and it typically comprises an oxide, a nitride, or an oxynitride in either a crystalline phase or a non-crystalline phase.

The patterned buried insulator layer12extends only to certain regions (e.g., regions22A,22B,24A,24B,42A,42B,44A, and44B) of the SOI substrate10, but is completely absent from other regions (e.g., regions23and43) of the SOI substrate10, as shown inFIG. 1.

Further, the patterned buried insulator layer12has different portions that are located in different regions of the SOI substrate10at varying depths. For example, certain portions of the patterned buried insulator layer12are located in regions22A,22B,42A, and42B of the SOI substrate10at a first depth (D1), as measured from an upper surface11of the substrate10. Other portions of the patterned buried insulator layer12are located in regions24A,24B,44A, and44B of the SOI substrate10at a second depth (D2), also measured from the upper surface11. The first depth (D1) is larger than the second depth (D2), as shown inFIG. 1. Preferably, the first depth (D1) ranges from about 20 nm to about 200 nm, and the second depth (D2) ranges from about 10 nm to about 100 nm. More preferably, the first depth (D1) ranges from about 50 nm to about 100 nm, and the second depth (D2) ranges from about 10 nm to about 20 nm.

One or more isolation regions30are typically formed in the SOI substrate10to provide isolation between adjacent FETs20and40. The isolation regions30may be a trench isolation region or a field oxide isolation region. The trench isolation region is formed utilizing a conventional trench isolation process well known to those skilled in the art. For example, lithography, etching and filling of the trench with a trench dielectric may be used in forming the trench isolation region. Optionally, a liner may be formed in the trench prior to trench fill, a densification step may be performed after the trench fill and a planarization process may follow the trench fill as well. The field oxide may be formed utilizing a so-called local oxidation of silicon process.

The FETs20and40can both be n-channel FETs or p-channel FETs. Alternatively, one of20and40is an n-channel FET, while the other is a p-channel FET. The FETs20and40comprise at least channel regions23and43, S/D regions22A,22B,42A, and42B, and S/D extension regions24A,24B,44A, and44B, which are all located in the SOI substrate10, as shown inFIG. 1. Specifically, channel regions23and43do not contain any buried insulator. The S/D regions22A,22B,42A, and42B contain first portions of the patterned buried insulator layer12at the first depth D1. The S/D extension regions24A,24B,44A, and44B contain second portions of the patterned buried insulator layer12at the second depth D2. As mentioned hereinabove, D1is larger than D2. The FETs20and40further comprise gate dielectrics26and46, gate electrodes28and48, and one or more optional sidewall spacers (not shown).

Typically, the first portions of the patterned buried insulator layer12located in the S/D regions22A,22B,42A, and42B has an average thickness of T1, and the second portions of the patterned buried insulator layer12located in the S/D extension regions24A,24B,44A, and44B has an average thickness of T2. T1can be substantially the same as T2, as shown inFIG. 1. Alternatively, T1can be either larger or smaller than T2, as shown inFIGS. 2 and 3.

Specifically, when T1is substantially the same as T2, as shown inFIG. 1, it is preferred that T1and T2both range from about 10 nm to about 200 nm. When T1is larger than T2, as shown inFIG. 2, it is preferred that T1ranges from about 20 nm to about 400 nm, and T2ranges from about 10 nm to about 200 nm. Further, when T1is smaller than T2, as shown inFIG. 3, it is preferred that T1ranges from about 10 nm to about 200 nm, and T2ranges from about 20 nm to about 400 nm.

Note that whileFIGS. 1-3illustratively demonstrate exemplary SOI substrates and SOI devices according to specific embodiments of the present invention, it is clear that a person ordinarily skilled in the art can readily modify such substrate and device structures for adaptation to specific application requirements, consistent with the above descriptions. For example, although the exemplary SOI devices as shown inFIGS. 1-3each contains two FETs, it is readily understood that the SOI devices may comprise any number of FETs. For another example, although the patterned buried insulator layers as shown inFIGS. 1-3are located at only two different depths in the SOI substrates, it is understood that such patterned buried insulator layers may be located at more than two different depths in the SOI substrates. Further, the SOI substrates of the present invention can be readily used for forming other semiconductor devices, such as transistors, diodes, capacitors, resistors, inductors, etc., besides the FETs as shown inFIGS. 1-3.

The present invention provides not only improved SOI substrate and device structures as described hereinabove, but also various improved methods for forming such SOI substrate and device structures at reduced costs with less defects. Such methods will be illustrated in greater details hereinafter with reference toFIGS. 4A-8G.

Specifically,FIGS. 4A-4Gshow exemplary processing steps for forming the SOI device ofFIG. 1by using a single ion implantation step and a replacement gate step, according to one embodiment of the present invention.

A substrate10, which is either a bulk semiconductor substrate containing no buried insulator material or a SOI substrate containing one or more preformed buried insulator layers (not shown), is first provided. The substrate10has a substantially planar upper surface11and one or more isolation regions30located therein, as shown inFIG. 4A.

Further, a thin dielectric layer102is formed over the upper surface11of the substrate10. The thin dielectric layer102may comprise any suitable dielectric material(s), including, but not limited to: oxides, nitrides, and oxynitrides, and it can be formed by a thermal growth process such as, for example, oxidation, nitridation or oxynitridation. Alternatively, the thin dielectric layer102can be formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma-assisted CVD, atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition and other like deposition processes. In a particularly preferred embodiment of the present invention, the thin dielectric layer102comprises an oxide. The physical thickness of the thin dielectric layer102may vary, but typically, it has a thickness from about 0.5 to about 10 nm, with a thickness from about 0.5 to about 3 nm being more typical.

Next, a blanket dielectric mask layer104is formed over the thin dielectric layer102, as shown inFIG. 4B. The blanket dielectric mask layer104may comprise any suitable dielectric masking material(s), including, but not limited to: oxides, nitrides, and oxynitrides. Preferably, but not necessarily, the blanket dielectric mask layer104comprises silicon nitride. The blanket dielectric mask layer104may be formed by any conventional deposition process, including, but not limited to: chemical vapor deposition (CVD), plasma-enhanced CVD, sputtering, evaporation, chemical solution deposition, and other like deposition processes. Alternatively, it may be formed by a conventional thermal oxidation, nitridation or oxynitridation process.

The physical thickness of the blanket dielectric mask layer104is adjusted so as to completely block implantation of oxygen and/or nitrogen ions in subsequent ion implantation step(s), and it therefore depends on the specific energy level of the implanted ions (which determines the ion implantation depth under normal conditions, i.e., when no masking structure is provided). Typically, the blanket dielectric mask layer104has a thickness ranging from about 100 nm to about 2000 nm, and more typically from about 400 nm to about 1200 nm.

Next, the blanket dielectric mask layer104is patterned into dielectric masks106and108, one for the FET20and the other for the FET40, as shown inFIG. 4C. The patterned dielectric masks106and108specifically define channel regions23and43for the FETs20and40. The processes that can be used for patterning the blanket dielectric mask layer104are well known in the art and are therefore not described in detail here. Preferably, the blanket dielectric mask layer104is patterned by conventional processes such as lithography or RIE.

A selectively etchable layer110is subsequently formed over the entire structure, as shown inFIG. 4D. The selectively etchable layer110may comprise any suitable dielectric material, which includes, but is not limited to: oxide, nitride, and oxynitride, as long as such a dielectric material is different from that contained by the dielectric masks106and108. In this manner, the selectively etchable layer110can be selectively etched against the dielectric masks106and108. When the dielectric masks106and108comprise silicon nitride, it is preferred that the selectively etchable layer110comprises silicon oxide (SiO2) or silicon oxynitride (SiOxNy) that is formed by a chemical vapor deposition. The material is chosen such that it acts as an etch stop for the subsequent nitride spacer.

Subsequently, dielectric spacers112and114are formed along sidewalls of the patterned dielectric masks106and108, thereby defining S/D extension regions24A,24B,44A, and44B (which are regions located directly under the dielectric spacers112and114) as well as S/D regions22A,22B,42A, and42B (which are regions located neither under the spacers112and114nor under the dielectric masks106and108), as shown inFIG. 4E.

The dielectric spacers112and114may comprise any suitable dielectric material(s), including, but not limited to: oxides, nitrides, and oxynitrides. Preferably, but not necessarily, the dielectric spacers112and114comprise silicon nitride. Dielectric spacers112and114can be readily formed by a dielectric deposition step followed by a dielectric patterning step. Preferably, the dielectric patterning is carried out using dry etching techniques, such as reactive ion etching (RIE).

The average thickness of the dielectric spacers112and114is adjusted in order to reduce the implantation depth of oxygen and/or nitrogen ions in subsequent ion implantation step(s) from the normal ion implantation depth (D1) to a predetermined, reduced depth (D2). Therefore, the average thickness of the dielectric spacers112and114depends not only on the specific energy level of the implanted ions (which determines the normal ion implantation depth D1), but also on the predetermined, reduced depth D2. Typically, the dielectric spacers112and114have an average thickness ranging from about 10 nm to about 200 nm, and more typically from about 20 nm to about 100 nm.

After formation of the dielectric spacers112and114, a single ion implantation step is carried out to implant oxygen and/or nitrogen ions116into the S/D regions22A,22B,42A, and42B and the S/D extension regions24A,24B,44A, and44B, but not the channel regions23and33, as shown inFIG. 4F. Consequently, a discontinuous implanted ion layer118, which extends only to the S/D regions22A,22B,42A, and42B and the S/D extension regions24A,24B,44A, and44B, is formed in the substrate10.

During the single ion implantation step shown byFIG. 4F, the S/D regions22A,22B,42A, and42B are exposed without any masking structures thereon. Therefore, oxygen and/or nitrogen ions116are implanted into the S/D regions22A,22B,42A, and42B without obstruction, and the portions of the implanted ion layer118in the S/D regions22A,22B,42A, and42B are located at a first depth (D1) that are determined solely by the ion implantation energy level. The S/D extension regions24A,24B,44A, and44B are covered by the dielectric spacers112and114. Therefore, the implantation depth of oxygen and/or nitrogen ions116is significantly reduced in the S/D extension regions24A,24B,44A, and44B, and consequently, the portions of the implanted ion layer118in the S/D extension regions24A,24B,44A, and44B are located at a second, reduced depth (D2). The channel regions23and43are covered by the dielectric masks106and108during the single implantation step ofFIG. 4F. Therefore, implantation of oxygen and/or nitrogen ions116is completely blocked by the dielectric masks106and108over the channel regions23and43, and consequently, the implanted ion layer118does not extend to the channel regions23and43. Note that D1and D2as discussed in this specific embodiment are the same as those shown previously inFIG. 1.

The varying depths of the implanted ion layer118are, on one hand, achieved by adjusting the implantation energy level, the thicknesses of the dielectric masks106,108, and the thicknesses of the dielectric spacers112,114. On the other hand, the average thickness of the implantation ion layer118is determined by the implantation dose. In this manner, by adjusting the implantation energy level, the thicknesses of the dielectric masks106,108and the dielectric spacers112,114, and the implantation dose, specific dimensions and locations of the implanted ion layer118can be readily controlled. Note that because the same implantation dose is used to form different portions of the implanted ion layer118, layer118has a substantially uniform thickness throughout different portions thereof.

The ion implantation step as shown inFIG. 4F, which is referred to herein as the base ion implantation step, is typically carried out using an energy beam having an energy level of from about 60 KeV to about 200 KeV and an ion dose from about 5.0×1016cm−2to about 5.0×1018cm−2at a temperature ranging from about 20° C. to about 800° C. Preferably, the ion implantation step is carried out using an energy beam having an energy level of from about 100 KeV to about 150 KeV and an ion dose from about 2.0×1017cm−2to about 2.0×1018cm−2at a temperature ranging from about 20° C. to about 600° C. If desired, the base ion implantation step may be followed by one or more supplemental ion implantation steps (not shown), which are carried over the same structure but under different implantation conditions, to form a high quality implanted ion layer118.

Next, the entire structure is annealed at a sufficiently high temperature to convert the implanted oxygen and/or nitrogen ions into buried insulator material(s) such as, for example, oxides, nitrides, or oxynitrides.

The annealing is typically carried out at a temperature above 1250° C., and more typically at a temperature ranging from about 1300° C. to about 1350° C. Duration of annealing typically ranges from about 1 hour to about 100 hours, with a duration of from about 2 hours to about 24 hours being more typical. Preferably, the annealing is carried out in an oxidizing ambient that includes from about 0.1% to about 100% oxygen (by total volume) and from about 99.9% to about 0% inert gas such as He, Ar, and N2. In one preferred embodiment, Ar is employed as the inert gas. More preferably, the annealing step of the present invention is carried out in an oxidizing ambient that includes from about 0.1% to about 50% oxygen (by total volume) and from about 50% to about 99.9% inert gas.

The annealing step may be carried out by simply heating the substrate at a specific temperature ramp rate to the targeted annealing temperature, or various ramp and soak cycles may be employed. During the various ramp and soak cycles, it is possible to vary the content of the annealing ambient within the ranges mentioned hereinabove.

As a result, the implanted ion layer118is converted into the patterned buried insulator layer12, as shown inFIG. 4G. The patterned buried insulator layer12so formed has a substantially uniform thickness throughout the S/D regions22A,22B,42A, and42B and the S/D extension regions24A,24B,44A, and44B, because a single ion implantation step with a single ion dose is used to form the implanted ion layer118, which has a substantially uniform thickness throughout.

Subsequently, the selectively etchable layer110, the dielectric masks106and108, and the dielectric spacers112and114can be removed, followed by a convention replacement gate process to form gate dielectrics26,46and gate electrodes28,48, as shown inFIG. 1.

FIGS. 5A-5Fshow exemplary processing steps for forming the SOI device ofFIG. 1by using a single ion implantation step without the replacement gate step, according to one embodiment of the present invention.

Specifically, a blanket gate conductor layer120and a dielectric cap layer122(instead of a single blanket dielectric mask layer104) are formed on an upper surface of the thin dielectric layer102, as shown inFIG. 5A.

The blanket gate conductor layer120may comprise any suitable conductive materials that can be used for forming the gate electrodes of the FETs20and40. For example, the blanket gate conductor layer120may comprise metal, metal alloy, metal nitride, metal silicide, or a semiconductor material such as Si or SiGe alloy in polycrystalline or amorphous form. The blanket gate conductor layer120can be formed by any known deposition processes, such as, for example, CVD, PVD, ALD, evaporation, reactive sputtering, chemical solution deposition, etc. When the blanket gate conductor layer120comprises a semiconductor material, such a semiconductor material is preferably doped either in situ or after deposition. The thickness, i.e., height, of the blanket gate conductor layer120may vary depending on the deposition process used. Typically, the blanket gate conductor layer120has a vertical thickness from about 20 to about 180 nm, with a thickness from about 40 to about 150 nm being more typical.

The blanket dielectric cap layer122may comprise any suitable dielectric masking material(s), including, but not limited to: oxides, nitrides, and oxynitrides. Preferably, but not necessarily, the blanket dielectric cap layer122comprises silicon nitride. The physical thickness of the blanket dielectric cap layer122is adjusted so as to completely block implantation of oxygen and/or nitrogen ions into the substrate10and the gate conductor layer120during subsequent ion implantation step(s), and it therefore depends on the specific energy level of the implanted ions (which determines the ion implantation depth under normal conditions, i.e., when no masking structure is provided). Typically, the blanket dielectric cap layer122has a thickness ranging from about 100 nm to about 2000 nm, and more typically from about 400 nm to about 1200 nm.

Next, the blanket dielectric cap layer122and the blanket gate conductor layer120are patterned into gate conductors26,46and dielectric masks128and130for the FETs20and40, as shown inFIG. 5B. The patterned gate conductors26and46and dielectric masks106and108specifically define channel regions23and43for the FETs20and40.

A selectively etchable layer132, which is similar to layer110as described hereinabove, is formed over the entire structure, as shown inFIG. 5C. Subsequently, dielectric spacers134and136, which are similar to spacers112and114as described hereinabove, are formed along sidewalls of the patterned gate conductors26and46, thereby defining S/D extension regions24A,24B,44A, and44B (which are regions located directly under the dielectric spacers134and136) as well as S/D regions22A,22B,42A, and42B (which are regions located neither under the spacers134and136nor under the gate conductors26and46), as shown inFIG. 5D.

After formation of the dielectric spacers134and136, a single ion implantation step is carried out to implant oxygen and/or nitrogen ions138into the S/D regions22A,22B,42A, and42B and the S/D extension regions24A,24B,44A, and44B, but not the channel regions23and33, as shown inFIG. 5E. Consequently, a discontinuous implanted ion layer140, which is similar to layer118as described hereinabove, is formed in the substrate10.

During the single ion implantation step shown byFIG. 5E, the S/D regions22A,22B,42A, and42B are exposed without any masking structures thereon. Therefore, oxygen and/or nitrogen ions138are implanted into the S/D regions22A,22B,42A, and42B without obstruction, and the portions of the implanted ion layer140in the S/D regions22A,22B,42A, and42B are located at a first depth (D1) that are determined solely by the ion implantation energy level. The S/D extension regions24A,24B,44A, and44B are covered by the dielectric spacers134and136. Therefore, the implantation depth of oxygen and/or nitrogen ions138is significantly reduced in the S/D extension regions24A,24B,44A, and44B, and consequently, the portions of the implanted ion layer140in the S/D extension regions24A,24B,44A, and44B are located at a second, reduced depth (D2). The channel regions23and43as well as the patterned gate electrodes26and46are covered by the dielectric masks128and130during the single implantation step ofFIG. 5E. Therefore, implantation of oxygen and/or nitrogen ions138is completely blocked by the dielectric masks128and130, and consequently, no oxygen or nitrogen ions are implanted into the channel regions23and43or the patterned gate electrodes26and46. Note that D1and D2as discussed in this specific embodiment are the same as those shown previously inFIG. 1.

Next, the entire structure is annealed at a sufficiently high temperature to convert the implanted oxygen and/or nitrogen ions into buried insulator material(s) such as, for example, oxides, nitrides, or oxynitrides.

As a result, the implanted ion layer140is converted by the annealing step into the patterned buried insulator layer12, as shown inFIG. 5F. The patterned buried insulator layer12so formed has a substantially uniform thickness throughout the S/D regions22A,22B,42A, and42B and the S/D extension regions24A,24B,44A, and44B, because a single ion implantation step with a single ion dose is used to form the implanted ion layer140, which has a substantially uniform thickness throughout.

Subsequently, the selectively etchable layer132, the dielectric masks128and130, and the dielectric spacers134and136can be removed. The thin dielectric layer102can be patterned into gate dielectrics26and46using the patterned gate electrodes26and46as masks, thereby forming the device structure as shown inFIG. 1. Note that the embodiment as shown inFIGS. 5A-5Gdoes not require a replacement gate process.

FIGS. 6A-6Fshow exemplary processing steps for forming the SOI device ofFIG. 1by using high-density plasma (HDP) oxide masks during the single ion implantation step, according to one embodiment of the present invention.

Specifically, after formation of the patterned gate conductors26,46and the dielectric masks128and130for the FETs20and40(as shown inFIG. 5B), an oxide layer150is deposited over the entire structure by a high-density plasma (HDP) deposition process, as shown inFIG. 6A. The high-density plasma (HDP) deposition process is anisotropic, i.e., it deposits over a horizontal surface at a significantly faster rate than that over a vertical surface. Consequently, the oxide layer150so deposited can achieve sufficient layer thickness over the horizontal upper surface of the thin dielectric layer102, with little or no accumulation over sidewalls of the patterned dielectric masks128and130and the gate electrodes26and46.

The thickness of the HDP oxide layer150is adjusted in order to reduce the implantation depth of oxygen and/or nitrogen ions in subsequent ion implantation step(s) from the normal ion implantation depth (D1) to a predetermined, reduced depth (D2). Therefore, the thickness of the HDP oxide layer150depends not only on the specific energy level of the implanted ions (which determines the normal ion implantation depth D1), but also on the predetermined, reduced depth D2. Typically, the HDP oxide layer150has an average thickness ranging from about 20 nm to about 300 nm, and more typically from about 30 nm to about 150 nm.

Unlike the dielectric spacers112,114,134, and136, the thickness of the HDP oxide layer150is adjusted by the HDP deposition process, not by an etching process. The HDP deposition process allows more precise thickness control, in comparison with the etching process.

Sacrificial spacers152and154are formed as masks for selective etching of the HDP oxide layer150, thereby forming HDP oxide spacers156and158, as shown inFIGS. 6B-6C. The sacrificial spacers152and154may comprise any suitable material against which the HDP oxide layer150can be selectively etched. In a preferred, but not necessary, embodiment of the present invention, sacrificial spacers152and154comprises polysilicon, so that the HDP oxide layer can be selectively etched by a RIE process. After formation of the HDP oxide spacers156and158, the sacrificial spacers152and154are removed, thereby exposing the HDP oxide spacers156and158, as shown inFIG. 6D.

The HDP oxide spacers156and158so formed define S/D extension regions24A,24B,44A, and44B (which are regions located directly under the spacers156and158) and S/D regions22A,22B,42A, and42B (which are regions located neither under the spacers156and158nor under the gate conductors26and46), as shown inFIG. 6D.

After formation of the HDP oxide spacers156and158, a single ion implantation step is carried out to implant oxygen and/or nitrogen ions160into the S/D regions22A,22B,42A, and42B and the S/D extension regions24A,24B,44A, and44B, but not the channel regions23and33, as shown inFIG. 6E. Consequently, a discontinuous implanted ion layer162, which is similar to layers118and140as described hereinabove, is formed in the substrate10.

During the single ion implantation step shown byFIG. 6E, the S/D regions22A,22B,42A, and42B are exposed without any masking structures thereon. Therefore, oxygen and/or nitrogen ions160are implanted into the S/D regions22A,22B,42A, and42B without obstruction, and the portions of the implanted ion layer162in the S/D regions22A,22B,42A, and42B are located at a first depth (D1) that are determined solely by the ion implantation energy level. The S/D extension regions24A,24B,44A, and44B are covered by the HDP oxide spacers156and158. Therefore, the implantation depth of oxygen and/or nitrogen ions162is significantly reduced in the S/D extension regions24A,24B,44A, and44B, and consequently, the portions of the implanted ion layer162in the S/D extension regions24A,24B,44A, and44B are located at a second, reduced depth (D2). The channel regions23and43as well as the patterned gate electrodes26and46are covered by the dielectric masks128and130during the single implantation step ofFIG. 6E. Therefore, implantation of oxygen and/or nitrogen ions160is completely blocked by the dielectric masks128and130, and consequently, no oxygen or nitrogen ions are implanted into the channel regions23and43or the patterned gate electrodes26and46. Note that D1and D2as discussed in this specific embodiment are the same as those shown previously inFIG. 3.

Next, the entire structure is annealed at a sufficiently high temperature to convert the implanted oxygen and/or nitrogen ions into buried insulator material(s). As a result, the implanted ion layer162is converted into the patterned buried insulator layer12, as shown inFIG. 6F. The patterned buried insulator layer12so formed has a substantially uniform thickness throughout the S/D regions22A,22B,42A, and42B and the S/D extension regions24A,24B,44A, and44B.

Subsequently, the dielectric masks128and130and the HDP oxide spacers156and158can be removed. The thin dielectric layer102can be patterned into gate dielectrics26and46using the patterned gate electrodes26and46as masks, thereby forming the device structure as shown inFIG. 1.

FIGS. 7A-7Fshow exemplary processing steps for forming the SOI device ofFIG. 2by using two ion implantation steps, one for S/D ion implantation and the other for S/D extension ion implantation, according to one embodiment of the present invention.

Specifically, after formation of the selectively etchable layer132over the entire structure (as shown inFIG. 5C), dielectric spacers164and166are deposited over the sidewalls of the patterned dielectric masks128and130and the gate electrodes26and46to thereby define S/D extension regions24A,24B,44A, and44B (which are regions located directly under the spacers164and166) and S/D regions22A,22B,42A, and42B (which are regions located neither under the spacers164and166, nor under the gate conductors26and46), as shown inFIG. 7A.

The dielectric spacers164and166are similar to the above-described dielectric spacers112,114,134, and136, except that the dielectric spacers164and166have an average thickness that is significantly larger than that of the dielectric spacers112,114,134, and136. Specifically, the average thickness of the dielectric spacers164and166is adjusted in order to completely block implantation of oxygen and/or nitrogen ions into the S/D extension regions24A,24B,44A, and44B during subsequent ion implantation step(s). Therefore, the average thickness of the dielectric spacers164and166typically ranges from about 100 nm to about 2000 nm, and more typically from about 400 nm to about 1200 nm.

After formation of the dielectric spacers164and166, a first ion implantation step is carried out to implant oxygen and/or nitrogen ions167into the S/D regions22A,22B,42A, and42B, but not the S/D extension regions24A,24B,44A, and44B and the channel regions23and33, as shown inFIG. 7B. Consequently, first portions168of a discontinuous implanted ion layer are formed in the S/D regions22A,22B,42A, and42B of the substrate10at a first depth (D1) with a first thickness (T1). D1and T1can be readily controlled by adjusting the implantation energy level and the implantation dose of the first ion implantation step.

Next, a resist coating170is deposited over the entire structure, followed by chemical vapor deposition and recess etching to expose the dielectric spacers164and166, as shown inFIG. 7C. The dielectric spacers164and166are then selectively removed against the resist coating170and the selectively etchable layer132, thereby forming trenches172directly above the S/D extension regions24A,24B,44A, and44B, as shown inFIG. 7D.

A second ion implantation step is then carried out to implant oxygen and/or nitrogen ions174into the S/D extension regions24A,24B,44A, and44B, but not the S/D regions22A,22B,42A, and42B and the channel regions23and33, as shown inFIG. 7E. Consequently, second portions176of the discontinuous implanted ion layer are formed in the S/D extension regions24A,24B,44A, and44B of the substrate10at a second depth (D2) with a second thickness (T2). D2and T2are independently controlled by adjusting the implantation energy level and the implantation dose of the second ion implantation step. Typically, D2is smaller than D1, as described hereinabove. On the other hand, T2can be larger than, smaller than, or substantially the same as T1, although in the specific embodiment shown byFIG. 7E, T2is significantly smaller than T1. Note that D1, D2, T1, and T2as discussed herein are the same as those shown previously inFIG. 2.

Next, the entire structure is annealed at a sufficiently high temperature to convert the implanted oxygen and/or nitrogen ions into buried insulator material(s). As a result, the implanted ion layer containing the first portions168and the second portions176is converted by the annealing step into the patterned buried insulator layer12, as shown inFIG. 7F. The patterned buried insulator layer12so formed has a significantly larger thickness in the S/D regions22A,22B,42A, and42B than in the S/D extension regions24A,24B,44A, and44B, because two separate ion implantation steps with two different ion doses are independently used to form the first portions168and the second portions176of the implanted ion layer.

Subsequently, the resist coating170, the dielectric masks128and130, and the selectively etchable layer132are removed. The thin dielectric layer102can be patterned into gate dielectrics26and46using the patterned gate electrodes26and46as masks, thereby forming the device structure as shown inFIG. 2.

FIGS. 8A-8Gshow exemplary processing steps for forming the SOI device ofFIG. 3by using two ion implantation steps, one of which implants oxygen and/or nitrogen ions in both the S/D and the extension regions, and the other of which implants oxygen and/or nitrogen ions only in the extension regions, according to one embodiment of the present invention.

Specifically, after formation of the patterned into gate conductors26,46and dielectric masks128and130for the FETs20and40(as shown inFIG. 5B), a first ion implantation step is directly carried out to implant oxygen and/or nitrogen ions178into the S/D regions22A,22B,42A, and42B and the S/D extension regions24A,24B,44A, and44B, but not the channel regions23and33, as shown inFIG. 8A. Consequently, first portions180of a discontinuous implanted ion layer are formed in the S/D regions22A,22B,42A, and42B and the S/D extension regions24A,24B,44A, and44B of the substrate10at a first depth (D1) with a first thickness (T1). D1and T1can be readily controlled by adjusting the implantation energy level and the implantation dose of the first ion implantation step.

Next, a selectively etchable layer132as described hereinabove is formed over the entire structure, as shown inFIG. 8B. Subsequently, dielectric spacers164and166as described hereinabove are formed along sidewalls of the patterned dielectric masks128and130and the gate conductors26and46, as shown inFIG. 8C.

A resist coating170as described hereinabove is deposited over the entire structure, followed by chemical vapor deposition and recess etching to expose the dielectric spacers164and166, as shown inFIG. 8D. The dielectric spacers164and166are then selectively removed against the resist coating170and the selectively etchable layer132, thereby forming trenches172directly above the S/D extension regions24A,24B,44A, and44B, as shown inFIG. 8E.

A second ion implantation step is then carried out to implant oxygen and/or nitrogen ions182into the S/D extension regions24A,24B,44A, and44B, but not the S/D regions22A,22B,42A, and42B and the channel regions23and33, as shown inFIG. 8F. Consequently, second portions184of the discontinuous implanted ion layer are formed in the S/D extension regions24A,24B,44A, and44B of the substrate10at a second depth (D2) with a second thickness (T+). D2and T+are independently controlled by adjusting the implantation energy level and the implantation dose of the second ion implantation step. Typically, D2is smaller than D1, as described hereinabove. On the other hand, T+can be larger than, smaller than, or substantially the same as T1. Because the second portions184of the discontinuous implanted ion layer are formed directly over the first portions180in the S/D extension regions24A,24B,44A, and44B, the final thickness (T2) of the discontinuous implanted ion layer in the S/D extension regions24A,24B,44A, and44B equals the sum of T1and T+. Therefore, T2is larger than T1in this specific embodiment. Note that D1, D2, T1, and T2as discussed herein are the same as those shown previously inFIG. 3.

Next, the entire structure is annealed at a sufficiently high temperature to convert the implanted oxygen and/or nitrogen ions into buried insulator material(s). As a result, the implanted ion layer containing the first portions180and the second portions184is converted by the annealing step into the patterned buried insulator layer12, as shown inFIG. 8G. The patterned buried insulator layer12so formed has a significantly larger thickness in the S/D extension regions24A,24B,44A, and44B than in the S/D regions22A,22B,42A, and42B.

Subsequently, the resist coating170, the dielectric masks128and130, and the selectively etchable layer132are removed. The thin dielectric layer102can be patterned into gate dielectrics26and46using the patterned gate electrodes26and46as masks, thereby forming the device structure as shown inFIG. 3.

WhileFIGS. 1-8Gillustratively demonstrate several exemplary device structures and processing steps that can be used to form such device structures, according to specific embodiments of the present invention, it is clear that a person ordinarily skilled in the art can readily modify such device structures as well as the process steps for adaptation to specific application requirements, consistent with the above descriptions. For example, while the device structures shown inFIGS. 1-3are designed as field effect transistors typically used in the CMOS technology, it is clear that a person ordinarily skilled in the art can readily modify the device structures of the present invention for use in other applications. It should therefore be recognized that the present invention is not limited to the specific embodiment illustrated hereinabove, but rather extends in utility to any other modification, variation, application, and embodiment, and accordingly all such other modifications, variations, applications, and embodiments are to be regarded as being within the spirit and scope of the invention.