Semiconductor device and method for manufacturing the same

In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2008-319938 filed on Dec. 16, 2008 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a technique for manufacturing the same. Particularly, the present invention relates to a technique applicable effectively to the improvement in reliability of a semiconductor device of a structure having semiconductor packages stacked in multiple stages.

With high integration of semiconductor devices there has been developed an SIP (System In Package) type semiconductor device wherein a semiconductor chip as memory and a semiconductor chip as controller for controlling the memory chip are together mounted in a single semiconductor device to build one system.

The capacity of the memory chip incorporated in the semiconductor device can be changed in accordance with the purpose of use of the product. Such a POP (Package On Package) type configuration as shown in Patent Literature 1 has been considered effective (see, for example, Patent Literature 1).

SUMMARY OF THE INVENTION

However, in the case of such a POP type semiconductor device as shown in Patent Literature 1, ball electrodes (bump electrodes) for coupling an upper wiring substrate and a lower wiring substrate electrically with each other are arranged around a semiconductor chip mounted on the lower wiring substrate. Therefore, a sealing body for protecting the semiconductor chip mounted on the lower wiring substrate is formed by a top gate method wherein a gate portion for the fill (supply) of resin is provided above the semiconductor chip.

Having made studies about such a semiconductor device, the present inventors found out the following problems.

On a main surface of the lower wiring substrate the sealing body is formed at only a central part, and at the periphery of the sealing body the upper wiring substrate is coupled electrically to the lower wiring substrate through a plurality of bump electrodes. That is, the sealing body is not formed up to the peripheral edge portion of the lower wiring substrate. Moreover, the lower wiring substrate, lower semiconductor chip, upper wiring substrate, and upper semiconductor chip are different in thickness and size. Therefore, the respective thermal expansion coefficients are also different from one another.

Consequently, in a heat treatment process for melting and bonding the bump electrodes, there occur warps of both upper and lower wiring substrates (particularly at the peripheral edge portion of the lower wiring substrate), giving rise to the problem that a state of non-coupling occurs at the bonded portions of the bump electrodes.

Further, in the case of the top gate method, the resin supplied from the gate portion is allowed to gather on the main surface of the lower wiring substrate.

Consequently, the air remaining within a cavity formed in a die is difficult to be discharged to the outside of the sealing body-forming region. Thus, the air is apt to remain in the interior of the sealing body formed.

It is an object of the present invention to provide a technique able to improve the reliability of a semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.

Typical modes of the present invention as disclosed herein will be outlined below.

According to the present invention, a planar shape of a first substrate main surface of a first wiring substrate is a quadrangular shape having a pair of first sides and a pair of second sides intersecting the first sides, a first sealing body is formed from a central part of one of the second sides of the first wiring substrate toward a central part of the other second side of the first wiring substrate, and a plurality of first substrate main surface-side lands are disposed between the first sealing body and the first sides of the first wiring substrate.

According to the present invention, moreover, a planar shape of a first substrate main surface of a first wiring substrate is a quadrangular shape having a pair of first sides and a pair of second sides intersecting the first sides, a plurality of first substrate main surface-side lands are arranged between a to-be-resin-supplied region and the first sides of the first wiring substrate, and in a resin sealing step, the resin is supplied from a central part of one of the second sides of the first wiring substrate toward a central part of the other second side of the first wiring substrate to form a sealing body.

The following is an outline of effects obtained by the typical modes of the present invention as disclosed herein.

Since plural lands formed on the main surface of the lower wiring substrate are arranged distributively on both sides of a chip mounting region positioned centrally of the lower wiring substrate, it is possible to adopt a through molding method. As a result, the sealing body on the lower wiring substrate can be formed over an area from one end to the opposite end of the substrate. Consequently, it is possible to enhance the strength against warping of the wiring substrate and hence possible to improve the reliability of the semiconductor device.

Since the through molding method can be adopted, the air remaining within the cavity can be discharged outside the sealing body-forming region. Consequently, it is possible to diminish the formation of voids in the interior of the sealing body and hence possible to improve the reliability of the semiconductor device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following embodiments, explanations of the same or similar portions will not be repeated in principle except where specially needed.

The following embodiments will each be described dividedly into plural sections or embodiments where required for the sake of convenience, but unless otherwise specified, it is to be understood that they are not unrelated to each other, but one is in a relation of modification or detailed or supplementary explanation of part of or the whole of the other.

When reference is made to, for example, the number of elements (including the number of pieces, numerical value, quantity, and range) in the following embodiments, no limitation is made to the specified number, but numbers above and below the specified number will do unless otherwise specified and except in the case where limitation is made to the specified number clearly.

Embodiments of the present invention will be described below in detail with reference to the drawings. In all of the drawings for illustrating the embodiments, members having the same functions are identified by the same reference numerals and repeated explanations thereof will be omitted.

First Embodiment

FIG. 1is a plan view showing a structural example of a semiconductor device according to a first embodiment of the present invention,FIG. 2is a bottom view showing a structural example of a back surface side of the semiconductor device ofFIG. 1,FIG. 3is a sectional view taken along line A-A inFIG. 2, showing a structural example,FIG. 4is a sectional view taken along line B-B inFIG. 2, showing a structural example, andFIG. 5is an enlarged partial sectional view showing a structural example of a portion A inFIG. 3.FIG. 6is a plan view showing a structural example of a first semiconductor package in the semiconductor device ofFIG. 1,FIG. 7is a plan view showing the structure of the first semiconductor package ofFIG. 6as seen through a sealing body,FIG. 8is a bottom view showing the structure of a back surface side of the first semiconductor package ofFIG. 6,FIG. 9is a plan view showing a structural example of a second semiconductor package in the semiconductor device ofFIG. 1as seen through a sealing body, andFIG. 10is a bottom view showing the structure of a back surface side of the second semiconductor package ofFIG. 9. Further,FIG. 11is a circuit block diagram showing an example of a circuit block configuration in the semiconductor device ofFIG. 1.

The semiconductor device of this first embodiment shown inFIGS. 1 to 5is a POP (Package On Package) type semiconductor device8of a structure comprising semiconductor packages stacked in multiple stages. In this first embodiment, a second semiconductor package17as an upper package is stacked on a first semiconductor package7as a lower package.

In the POP type semiconductor device8of this first embodiment, a first semiconductor chip as a controller chip is mounted on the first semiconductor package7as a lower package, while a second semiconductor chip as a memory chip is mounted on the second semiconductor package17as an upper package. The second semiconductor chip as a memory chip is controlled by the first semiconductor chip as a controller chip. Thus, the POP type semiconductor device8serves also as an SIP type semiconductor device.

The POP type semiconductor device8will be described below dividedly with respect to the first semiconductor package7as a lower package and the second semiconductor package17as an upper package.

First, a description will be given about the configuration of the first semiconductor package7as a lower package. The first semiconductor package7is comprised of a controller chip1which is the first semiconductor chip as a controller chip, a first wiring substrate2with the controller chip1mounted thereon, a plurality of wires3as a first conductive member which couples the controller chip1and the first wiring substrate2electrically with each other, a first sealing body4which seals the controller chip1and the wires3with resin, and a plurality of solder balls5provided on a back surface2bof the first wiring substrate2.

As shown inFIGS. 5 and 7, the first wiring substrate2includes a main surface (a first substrate main surface)2ahaving a first chip mounting region2dwith a plurality of first bonding leads2cformed therein and also includes a plurality of main surface-side lands (first substrate main surface-side lands)2e, the main surface-lands2ebeing coupled electrically to the first bonding leads2crespectively and arranged around the first chip mounting region2don the main surface2a. The first wiring substrate2further includes a back surface (a first substrate back surface)2bpositioned on the side opposite to the main surface2aand a plurality of back surface-side lands (first substrate back surface-side lands)2fcoupled electrically to the first bonding leads2crespectively and arranged on the back surface2b.

As shown inFIG. 5, the first wiring substrate2includes a core member2g, wiring portions2iformed on both the surface and back surface of the core member, a through hole wiring2jfor coupling the wiring portions2ion both the surface and back surface electrically with each other, and solder resist films2hwhich are insulating films covering the wiring portions2irespectively. Consequently, the main surface-side lands2e, the first bonding leads2cand the back surface-side lands2fare coupled together electrically via the wiring portions2iand the through hole wiring2j. The solder resist films2hcover the wiring portions2i, but at the main surface-side lands2eand the first bonding leads2cand further at the back surface-side lands2f, the solder resist films2hcover only the peripheral edge portions of those electrodes, with central portions being open. This permits electrical coupling of the electrodes, i.e., the main surface-side lands2e, first bonding leads2cand back surface-side lands2f.

Like the layout of solder balls5inFIGS. 2 to 4, the back surface-side lands2fare arranged peripherally in two rows along the outer peripheral portion of the back surface2bof the first wiring substrate2.

As shown inFIG. 7, the controller chip1as the first semiconductor chip mounted on the first semiconductor package7is positioned in the first chip mounting region2dof the first wiring substrate2and has a control circuit. As shown inFIG. 5, the controller chip1further includes a main surface (a first chip main surface)1a, a plurality of first pads (first electrode pads)1cformed on the main surface1a, and a back surface (a first chip back surface)1b(FIGS. 3 and 4) positioned on the side opposite to the main surface1a.

As shown inFIG. 7, the first pads1con the main surface1aof the controller chip1are arranged side by side along the peripheral edge portions of four sides of the main surface1a. As shown inFIG. 5, the controller chip1is fixed to the main surface2aof the first wiring substrate2with use of a die bonding material6such as, for example, a paste material or a filmy adhesive.

The first pads1con the controller chip1and the first bonding leads2con the first wiring substrate2are coupled together electrically through wires (first conductive members)3respectively.

Moreover, as shown inFIGS. 6 and 7, a first sealing body4is formed on the main surface2aof the first wiring substrate2in such a manner that the main surface-side lands2eare exposed. The controller chip1, the wires3and the main surface2aof the first wiring substrate2are resin-sealed by the first sealing body4.

Further, as shown inFIGS. 5 and 8, solder balls5are bonded respectively to the back surface-side lands2fon the back surface2bof the first wiring substrate2.

Next, a description will be given about the configuration of the second semiconductor package17as an upper package. The second semiconductor package17is comprised of a non-volatile memory11which is the second semiconductor chip as a memory chip, a second wiring substrate12with the non-volatile memory11mounted thereon, a plurality of wires13as second conductive members for coupling the non-volatile memory11and the second wiring substrate12electrically with each other, a second sealing body14for sealing the non-volatile memory11and the wires13with resin, and a plurality of solder balls15provided on a back surface12bof the second wiring substrate12.

As shown inFIGS. 5 and 9, the second wiring substrate12includes a main surface (a second substrate main surface)12ahaving a second chip mounting region12dwith a plurality of second bonding leads12cformed therein, a back surface (a second substrate back surface)12bpositioned on the side opposite to the main surface12a, and a plurality of back surface-side lands (second substrate back surface-side lands)12fcoupled electrically to the second bonding leads12crespectively and arranged on the back surface12b.

Like the first wiring substrate2, as shown inFIG. 5, the second wiring substrate12further includes a core member12g, wiring portions12iformed on both the surface and back surface of the core member, a through hole wiring12jfor coupling the surface and back surface wiring portions12iwith each other, and solder resist films12hwhich are insulating films covering the wiring portions12irespectively. Consequently, the second bonding leads12cand the back surface-side lands12fare coupled together electrically via the wiring portions12iand the through hole wiring12j. Like the first wiring substrate2, the solder resist films12hcover the wiring portions12irespectively, but at the second bonding leads12cand the back surface-side lands12f, the solder resist films12hcover only the peripheral edge portions of those electrodes, with central portions being open. This permits electrical coupling of the electrodes, i.e., the second bonding leads12cand the back surface-side lands12f.

Like the array of solder balls15shown inFIG. 10and that of the main surface-side lands2eon the first wiring substrate2shown inFIG. 7, the back surface-side lands12fare arranged side by side along one set of opposed sides on the back surface12bof the second wiring substrate12.

As shown inFIG. 9, the non-volatile memory11as the second semiconductor chip mounted on the second semiconductor package17is positioned in the second chip mounting region12dof the second wiring substrate12and has a memory circuit. As shown inFIG. 5, the non-volatile memory11further includes a main surface (a second chip main surface)11a, a plurality of second pads (second electrode pads)11cformed on the main surface11a, and a back surface (a second chip back surface)11bpositioned on the side opposite to the main surface11a.

As shown inFIG. 9, the second pads11con the main surface11aof the non-volatile memory11are arranged side by side along one of four sides of the main surface11a. As shown inFIG. 5, like the controller chip1, the non-volatile memory11is also fixed to the main surface12aof the second wiring substrate12with use of a die bonding material16such as, for example, a paste material or a filmy adhesive.

The non-volatile memory11is controlled by the controller chip1.

The second pads11cof the non-volatile memory11and the second bonding leads12con the second wiring substrate12are coupled together electrically through wires (second conductive members)13.

Further, as shown inFIG. 5, a second sealing body14is formed on the main surface12aof the second wiring substrate12. The non-volatile memory11, the wires13and the main surface12aof the second wiring substrate12are resin-sealed by the second sealing body14.

As shown inFIGS. 5 and 10, solder balls (second outer terminals, bump electrodes)15are bonded respectively to the back surface-side lands12fon the back surface12bof the second wiring substrate12, and the back surface-side lands (electrodes, lands)12fon the second wiring substrate12as an upper substrate and the main surface-side lands (electrodes, lands)2eon the first wiring substrate2as a lower substrate are coupled together electrically through solder balls15.

As shown inFIG. 5, the solder balls15are much larger than the solder balls5because they must be higher than the first sealing body4in the first semiconductor package7as a lower package.

In the POP type semiconductor device8of this first embodiment, as shown inFIG. 7, the main surface2aof the first wiring substrate2in the first semiconductor package7as a lower package has a quadrangular plane shape having a pair of first sides2mand a pair of second sides2nintersecting the first sides2m. In the POP type semiconductor device8, the sides positioned along the layout direction of the main surface-side lands2eon the first wiring substrate2are made to be the first sides2m, while the sides positioned in a direction intersecting the first sides2mare made to be the second sides2n.

In the POP type semiconductor device8, as shown inFIG. 6, the first sealing body4on the first wiring substrate2in the first semiconductor package7as a lower package is formed from a central part of one second side2nof the first wiring substrate2toward a central part of the other second side2n. That is, the first sealing body4is formed so as to extend from one second side2nand reach the other second side2n.

The main surface-side lands2eare arranged on both sides of the first sealing body. More specifically, the main surface-side lands2eare arranged in one row along one first side2mof the first wiring substrate2in the area between the first sealing body4and one first side2mand likewise are arranged in one row along the other first side2min the area between the first sealing body4and the other first side2m. However, the main surface-side lands2emay be arranged in plural rows along the associated first side2mon each side of the first sealing body4.

That is, on the main surface2aof the first wiring substrate2in the POP type semiconductor device8, the first sealing body4is formed so as to extend from one second side2nand reach the other second side2nand at a width narrower than each second side2n, which width is a slightly larger width than the first chip mounting region2d. Further, the main surface-side lands2eare distributed to both sides of the first sealing body4and are arranged side by side along the first sides2m.

A description will now be given about the difference in the number of electrode pads between the non-volatile memory11which is the second semiconductor chip in the second semiconductor package17as an upper package and the controller chip (microcomputer chip)1which is the first semiconductor chip in the first semiconductor package7as a lower package. In the POP type semiconductor device8of this first embodiment, the non-volatile memory11is mounted on the second semiconductor package17as an upper package, while the controller chip1for controlling the non-volatile memory11as an upper chip is mounted on the first semiconductor package7as a lower package. The non-volatile memory (e.g., flash memory)11is a storage means for storage of data to be read out and storage of written data.

As shown in the circuit block diagram ofFIG. 11, the controller chip1includes a memory interface (an internal interface) for input and output (electrical coupling) of signals from and to the non-volatile memory11in order to control the non-volatile memory11which is positioned in the interior of the POP type semiconductor device8, i.e., a system built by both controller chip1and non-volatile memory11. The controller chip1also includes an external interface for the exchange (input and output) (electrical coupling) of signals with the exterior (or external devices mounted outside the system) of the POP type semiconductor device8, i.e., the system. More specifically, the first pads1cformed on the controller chip1have pads for internal interface and pads for external interface. On the other hand, the non-volatile memory11does not exchange signals directly with external devices and thus the difference in the number of electrode pads between the controller chip1and the non-volatile memory11is evident, the former being the larger in the number of electrode pads. That is, in the POP semiconductor device, the number (total number) of the first pads1cwhich the controller chip1has is larger than that of the second pads11cwhich the non-volatile memory11has.

Further, in the POP type semiconductor device8of this first embodiment, the type of memory mounted on the second semiconductor package17as an upper package is only one type. Therefore, the number of electrode pads in the non-volatile memory11is small inevitably.

Thus, in the POP type semiconductor device8of this first embodiment, since not only the semiconductor chip mounted on the second semiconductor package as an upper package is a memory chip but also the type thereof is only one type, it is possible to reduce the number of the back surface-side lands12fin the second semiconductor package17as an upper package. As a result, it is also possible to reduce the number of the main surface-side lands2ein the first semiconductor package7as a lower package. Accordingly, it becomes possible to arrange the main surface-side lands2edistributively on both sides of the first sealing body4.

Consequently, the first sealing body4can be disposed up to ends of the main surface2aof the first wiring substrate2. Therefore, a gate portion in resin molding can be disposed near an end of the main surface2aof the first wiring substrate2, thus permitting the adoption of a through molding method (a block molding method; plural device regions are together covered with one cavity of a resin molding die and are molded with resin) at the time of forming the first sealing body4.

Therefore, as shown inFIG. 6, the first sealing body4can be formed so as to extend from a central part of one second side2nof the first wiring substrate2and reach a central part of the other second side2nopposed to the one second side2n. As a result, the first sealing body4can be formed from an end (side) on the main surface2aof the first wiring substrate2up to the opposite end (side), so that it is possible to enhance the rigidity of the first semiconductor package7.

Thus, the first sealing body4in the first semiconductor package7as a lower package of the POP type semiconductor device8of this first embodiment is formed by the through molding method.

Next, the following description is provided about a method for manufacturing the POP type semiconductor device8of this first embodiment.

FIG. 12is a plan view showing a structural example of a wiring substrate used in assembling the first semiconductor package in the semiconductor device ofFIG. 1,FIG. 13is a back view showing a structural example of a back surface side of the wiring substrate ofFIG. 12,FIG. 14is an enlarged partial plan view showing the structure of a portion A inFIG. 12,FIG. 15is a sectional view taken along line A-A inFIG. 14, showing a structural example, andFIG. 16is a sectional view taken along line B-B inFIG. 14, showing a structural example.FIG. 17is a partial enlarged plan view showing a structural example after die bonding in assembling the first semiconductor package of FIG.6,FIG. 18is a sectional view taken along line A-A inFIG. 17, showing a structural example, andFIG. 19is a sectional view taken along line B-B inFIG. 17, showing a structural example.FIG. 20is a partial enlarged plan view showing a structural example after wire bonding in assembling the first semiconductor package ofFIG. 6,FIG. 21is a sectional view taken along line A-A inFIG. 20, showing a structural example, andFIG. 22is a sectional view taken along line B-B inFIG. 20, showing a structural example. Further,FIG. 23is a partial enlarged plan view showing a structural example after resin molding in assembling the first semiconductor package ofFIG. 6,FIG. 24is a sectional view taken along line A-A inFIG. 23, showing a structural example,FIG. 25is a sectional view taken along line B-B inFIG. 23, showing a structural example,FIG. 26is a back view showing a structural example after ball mounting at a portion A inFIG. 13, andFIG. 27is a sectional view taken along line A-A inFIG. 26, showing a structural example.

A description will be given first about a method for manufacturing the first semiconductor package7as a lower package.

As shown inFIGS. 12 to 16, there is provided a matrix substrate9(a first wiring substrate2) formed with a plurality of device regions9a, the matrix substrate9including in each of the device regions9aa main surface2ahaving a first chip mounting region2d, a plurality of main surface-side lands2earranged around the first chip mounting region2don the main surface2a, a back surface2bpositioned on the side opposite to the main surface2a, and a plurality of back surface-side lands2farranged on the back surface2b. As shown inFIG. 12, a plurality of first bonding leads2care formed in the first chip mounting region2dof the main surface. As shown inFIG. 14, the main surface-side lands2eare coupled to the first bonding leads2celectrically. Moreover, as shown inFIGS. 12 and 14, gate portions9dare disposed between second sides2nof the device regions9aand a side (closest to the second sides2n) of the matrix substrate9adjacent to the second sides2nand positioned outside the device regions9a. An Au plating layer is formed on the surface of each gate portion9dand resin charged into pot portions (not shown) is supplied through the gate portions9dinto the device regions9a. Thus, an Au plating layer is formed on the surface of each gate portion9d, so in a gate breaking step for separating a part of a sealing body18formed in a later process, a part of the sealing body18can be separated (peeled) easily from the matrix substrate9. The back surface-side lands2fshown inFIGS. 15 and 16are also coupled electrically to the first bonding leads2crespectively.

Thereafter, die bonding is performed. In this step, as shown inFIGS. 17 to 19, a plurality of controller chips1each including a main surface1a, a plurality of first pads1cformed on the main surface1a, and a back surface1bpositioned on the side opposite to the main surface1a, are mounted respectively onto the first chip mounting regions2dshown inFIG. 14in the device regions9aof the matrix substrate9(the first wiring substrate2). At this time, as shown inFIG. 5, each controller chip1is mounted onto the first wiring substrate2through a die bonding material6.

Subsequently, wire bonding is performed. In this process, as shown inFIGS. 20 to 22, the first pads1con the controller chips1and the first bonding leads2con the first wiring substrate2are coupled together through a plurality of wires3(e.g., gold wires).

Thereafter, resin molding is performed. In this step, as shown inFIGS. 23 to 25, the controller chips1, the wires3and the main surface2aof the first wiring substrate2are together blocked with resin in such a manner that the main surface-side lands2eare exposed. In a foregoing gate breaking step, stepped portions are formed in part (not shown) of an upper molding die corresponding to the gate portions9das shown inFIG. 25in order to facilitate separation of the unnecessary sealing body18(gate resin) formed on the gate portions9dfrom the sealing body18which seals the semiconductor chip1. Consequently, the surface (thickness) of the sealing body18formed on each gate portion9dbecomes lower (thinner) than that of the sealing body18formed in each device region9a.

As shown inFIG. 7, a planar shape of the main surface2aof the first wiring substrate2is a quadrangular shape having a pair of first sides2mand a pair of second sides2nintersecting the first sides2m. The main surface-side lands2eare arranged between the resin-supplied region (the region where the sealing body18(the first sealing body4) is formed; a molding region2k) and one first side2mof the first wiring substrate2(and between the resin-supplied region and the other first side2m) (along the first sides2m). In the resin sealing process, the resin is supplied from a central part of one second side2nof the first wiring substrate2toward a central part of the other second side2nopposed to the one second side2nto form an integral sealing body18as shown inFIG. 23.

In the POP type semiconductor device8, since the semiconductor chip mounted on the second semiconductor package17as an upper package is a memory chip and the type thereof is only one type, it is possible to reduce the number of back surface-side lands12fin the second semiconductor package17as an upper package, with the result that the number of main surface-side lands2ein the first semiconductor package7as a lower package can also be reduced. Thus, it becomes possible to arrange the main surface-side lands2edistributively on both sides of a molding region2kshown inFIG. 20. Consequently, the sealing body18can be formed so as to extend from a central part of one second side2nof the first wiring substrate2shown inFIG. 7and reach a central part of the other second side2nopposed to the one side2n. Accordingly, as a resin molding method it is possible to adopt a through molding method (a block molding method; plural device regions are together covered with one cavity of a resin molding die and are molded with resin). That is, resin can be supplied to the first wiring substrate2in a resin flowing direction10shown inFIG. 23, which runs along the first sides2mof the first wiring substrate2inFIG. 7, and in accordance with the through molding method. The resin flowing direction10may be a direction opposite 180° to the direction shown inFIG. 23.

Thus, in assembling the POP type semiconductor device8of this first embodiment, it is possible, in the resin molding step, to seal the device regions9aall at a time by adopting the through molding method, whereby an elongated integral sealing body18can be formed.

Subsequently, ball mounting is performed. In this step, as shown inFIGS. 26 and 27, a plurality of solder balls5as first external terminals are formed respectively on the back surface-side lands2fof the first wiring substrate2ofFIG. 5. Then, the matrix substrate is subjected to package dicing to complete the assembly of the first semiconductor package7as a lower package.

The following description is now provided about a method for manufacturing the second semiconductor package17as an upper package.

FIG. 28is a plan view showing a structural example of a wiring substrate used in assembling the second semiconductor package in the semiconductor device ofFIG. 1,FIG. 29is a back view showing a structural example of a back surface side of the wiring substrate ofFIG. 28,FIG. 30is an enlarged partial plan view showing the structure of a portion A inFIG. 28,FIG. 31is a sectional view taken along line A-A inFIG. 30, showing a structural example, andFIG. 32is a sectional view taken along line B-B inFIG. 30, showing a structural example.FIG. 33is a partial enlarged plan view showing a structural example after die bonding in assembling the second semiconductor package shown inFIG. 9,FIG. 34is a sectional view taken along line A-A inFIG. 33, showing a structural example, andFIG. 35is a sectional view taken along line B-B inFIG. 33, showing a structural example.FIG. 36is a partial enlarged plan view showing a structural example after wire bonding in assembling the second semiconductor package ofFIG. 9,FIG. 37is a sectional view taken along line A-A inFIG. 36, showing a structural example, andFIG. 38is a sectional view taken along line B-B inFIG. 36, showing a structural example.FIG. 39is a partial enlarged plan view showing a structural example after resin molding in assembling the first semiconductor package ofFIG. 9,FIG. 40is a sectional view taken along line A-A inFIG. 39, showing a structural example, andFIG. 41is a sectional view taken along line B-B inFIG. 39, showing a structural example. Further,FIG. 42is a back view showing a structural example after ball mounting at a portion A inFIG. 29,FIG. 43is a sectional view taken along line A-A inFIG. 42, andFIG. 44is a sectional view taken along line B-B inFIG. 42, showing a structural example.

First, as shown inFIGS. 28 to 32, there is provided a matrix substrate9b(a second wiring substrate12) formed with a plurality of device regions9c, the matrix substrate9bincluding in each of the device regions9ca main surface12ahaving a second chip mounting region12dshown inFIG. 30, a back surface12bpositioned on the side opposite to the main surface12a, and a plurality of back surface-side lands12farranged on the back surface12b. As shown inFIG. 30, a plurality of second bonding leads12care formed in the second chip mounting region12dof the main surface12a. However, it goes without saying that the number of the second bonding leads12con the second wiring substrate12is smaller than that of the first bonding leads2con the first wiring substrate2. The back surface-side lands12fshown inFIGS. 31 and 32are coupled electrically to the second bonding leads12crespectively.

Thereafter, die bonding is performed. In this step, as shown inFIGS. 33 to 35, a plurality of non-volatile memories11each having a main surface11a, a plurality of second pads11cformed on the main surface11a, and a back surface11bpositioned on the side opposite to the main surface11aare mounted respectively onto the second chip mounting regions12dshown inFIG. 30and formed respectively in the device regions9cof the matrix substrate9b(the second wiring substrate12). At this time, the non-volatile memories11are mounted onto the second wiring substrate12through a die bonding material16, as shown inFIG. 5.

Then, wire bonding is performed. In this step, as shown inFIGS. 36 to 38, the second pads11cof each non-volatile memory11and the second bonding leads12con the second wiring substrate12are coupled together electrically through wires13(e.g., gold wires).

Subsequently, resin molding is performed. In this step, as shown inFIGS. 39 to 41, the non-volatile memories11, the wires13and the main surface12aof the second wiring substrate12are together sealed with resin. In this case, the device regions9care together sealed with resin to form a sealing body18which covers all of the device regions9cshown inFIG. 36.

Thereafter, ball mounting is performed. In this step, as shown inFIGS. 42 to 44, a plurality of solder balls15as second external terminals are formed on the back surface-side lands12frespectively of the second wiring substrate12which lands have been formed at the same pitch as that of the main surface-side lands2eof the first wiring substrate2shown inFIG. 5. Then, the matrix substrate is subjected to package dicing to complete the assembly of the second semiconductor package17as an upper package.

Subsequently, the second semiconductor package17as an upper package is stacked onto the first semiconductor package7as a lower package.

More specifically, the second wiring substrate12of the second semiconductor package17with the non-volatile memory11mounted on the second wiring substrate12and with the back surface-side lands12fdisposed on the back surface12bopposite to the main surface12ais mounted onto the first wiring substrate2of the first semiconductor package7through solder balls15. With this arrangement, the main surface-side lands2eof the first wiring substrate2and the back surface-side lands12fof the second wiring substrate12are coupled together electrically through solder balls15.

In this case, a plurality of solder balls15are provided beforehand on the back surface-side lands12fof the second wiring substrate12in the second semiconductor package17, then the solder balls15, in their mounted state onto the second semiconductor package17, are disposed onto the main surface-side lands2eof the first wiring substrate2, and thereafter the main surface-side lands2eof the first semiconductor package7and the back surface-side lands12fof the second semiconductor package17are coupled together electrically through the solder balls15.

In this way the assembly of the POP type semiconductor device8of this first embodiment is completed.

The solder balls15formed on the back surface-side lands12fof the second wiring substrate12in the second semiconductor package17as an upper package need not always be formed on the second wiring substrate12beforehand. That is, when stacking the second wiring substrate12onto the first wiring substrate2, the stacking (mounting) may be done through the solder balls15.

According to the POP type semiconductor device8and the method for manufacturing the same according to this first embodiment, the main surface-side lands2eformed on the first wiring substrate2in the first semiconductor package7as a lower package are disposed distributively on both sides of the first chip mounting region2das a boundary positioned at a central part of the first wiring substrate2, whereby the first sealing body4can be disposed up to ends of the main surface2aof the first wiring substrate2.

Consequently, the gate portions used in resin molding can each be disposed near an end of the main surface2aof the first wiring substrate2, thus permitting the adoption of the through molding method in resin molding.

As a result, the first sealing body4on the first wiring substrate2in the first semiconductor package7as a lower package can be formed over the area from one end (second side2n) of the first wiring substrate2up to the other end (second side2n) opposed thereto, whereby the rigidity of the first semiconductor package7can be enhanced. Accordingly, it is possible to enhance the strength of the first wiring substrate2against warping and improve the reliability of the POP type semiconductor device8.

Moreover, since it is possible to adopt the through molding method, the air remaining within the cavity of the resin molding die can be exhausted to the outside of the region where the first sealing body4is formed. Consequently, it is possible to diminish the formation of voids in the interior of the first sealing body4and improve the reliability of the POP type semiconductor device8.

Next, a description will be given below about a modification of the first embodiment.

In connection with the first embodiment a description has been given above about the POP type semiconductor device8up to the process wherein the second semiconductor package17with completed assembly of the second wiring substrate12as an upper substrate is stacked onto the first semiconductor package7as a lower package. However, the first semiconductor package7as a lower package may be shipped upon completion of its manufacture. By so doing, it becomes easier to change the capacity of the non-volatile memory11(e.g., flash memory) according to the purpose of use of product and before mounting onto a mother board.

Moreover, although in the first embodiment a description has been given about a process wherein a memory chip is mounted onto the second wiring substrate12as an upper substrate to fabricate the second semiconductor package17as an upper package and thereafter the second semiconductor package is stacked onto the first semiconductor package7as a lower package, the first semiconductor package7as a lower package may first be fabricated and then the second semiconductor package17as an upper package provided in advance may be stacked onto the first semiconductor package. By so doing it is possible to reduce the number of manufacturing steps for the second semiconductor package17as an upper package, so that the manufacturing cost of the completed POP type semiconductor device8can be reduced.

Second Embodiment

FIG. 45is a plan view showing a structural example of a first semiconductor package in a semiconductor device according to a second embodiment of the present invention as seen through a sealing body andFIG. 46is a sectional view taken along line B-B inFIG. 45, showing a structural example of the semiconductor device of the second embodiment. Further,FIG. 47is a plan view showing a structural example of a first semiconductor package in a first modification of the semiconductor device of the second embodiment as seen through a sealing body,FIG. 48is a sectional view taken along line B-B inFIG. 47, showing the structure of the first modification of the semiconductor device of the second embodiment, andFIG. 49is a circuit block diagram showing an example of a circuit block configuration of the semiconductor device ofFIG. 46.

Like the first embodiment, the semiconductor device of the second embodiment shown inFIGS. 45 and 46is a POP type semiconductor device19of a structure wherein semiconductor packages are stacked in multiple stages, with a second semiconductor package17as an upper package being stacked on a first semiconductor package7as a lower package.

In the POP type semiconductor device19of this second embodiment, a first semiconductor chip as a controller chip is mounted on the first semiconductor package7as a lower package and a third semiconductor chip as a memory chip is mounted on the same package sideways of the first semiconductor chip. On the second semiconductor package17as an upper package there is mounted only a second semiconductor chip as a memory chip as in the POP type semiconductor device8of the first embodiment. The third semiconductor chip as a memory chip mounted on the first semiconductor package7as a lower package is, for example, SDRAM (Synchronous Dynamic Random Access Memory)21, having a memory circuit with a memory function different from that of a non-volatile memory11which is the second semiconductor chip mounted on the first semiconductor package7as an upper package. The first semiconductor chip mounted on the first semiconductor package7as a lower package is a controller chip1as in the first embodiment.

The SDRAM21is provided, for example, as a cache memory of the controller chip1, which is a storage means for temporary storage of arithmetic data. As shown inFIG. 45, the SDRAM21is disposed next to the controller chip1which is disposed in a direction along first sides2mof a first wiring substrate2as shown inFIG. 45. The SDRAM21has a main surface21afacing upward and a back surface21bbonded to a main surface2aof the first wiring substrate2.

As shown in the circuit block diagram of the POP type semiconductor device19ofFIG. 49, the non-volatile memory11as an upper memory and the SDRAM21as a lower chip are both controlled by the controller chip1as a lower chip. As is the case with the POP type semiconductor device8of the first embodiment, the non-volatile memory11and the SDRAM21do not exchange signals with external devices, but only the controller chip1makes exchange of signals with external devices. Therefore, the number of first pads (first electrode pads)1cwhich the controller chip1has is larger than that of second pads (second electrode pads)11cshown inFIG. 5and which the non-volatile memory11has and is also larger than that of third pads (third electrode pads)21cwhich the SDRAM21has. That is, like the non-volatile memory11, the number of third pads21cof the SDRAM21is also smaller than that of first pads1cof the controller chip1.

Thus, also in the POP type semiconductor device of this second embodiment, since the type of the memory chip mounted on the second semiconductor package17as an upper package is one type, it is possible to decrease the number of back surface-side lands12fin the second semiconductor package17as an upper package. As a result, it is possible to decrease the number of main surface-side lands2ein the first semiconductor package7as a lower package.

Consequently, as shown inFIG. 45, it becomes possible to distribute the main surface-side lands2edistributively on both sides of a first sealing body4shown inFIG. 46.

The SDRAM21is a cache memory of the controller chip1and is preferably disposed near the controller chip1in order to attain a high signal processing speed. Therefore, the SDRAM21is mounted on the first semiconductor package7as a lower package. In this case, the main surface (third chip main surface)21aof the SDRAM21is smaller than a main surface11aof the non-volatile memory11and the SDRAM21is mounted next to the controller chip1in a direction along first sides2mof the first wiring substrate2, thus permitting the SDRAM21to be mounted near the controller chip1as a lower chip without enlarging the width of the first sealing body4. With this arrangement, also in the POP type semiconductor device19, like the POP type semiconductor device8of the first embodiment, the first sealing body4can be formed by the through molding method.

The SDRAM21has a rectangular plane shape (the shape of the main surface21a) and the third pads (third electrode pads)21cformed on the main surface21aare arranged along the long sides of the main surface21a, as shown inFIG. 45. That is, the third pads21care arranged side by side in a direction along second sides2nof the first wiring substrate2at a central part of the main surface21aof the SDRAM21in a direction along first sides2mof the first wiring substrate2(a central part in the width direction of the rectangular main surface21aof the SDRAM21). Thus, the third pads21care arranged in a so-called center pad layout. In the center pad layout it is optional whether the third pads21care to be arranged in one row or in plural rows.

Further, the third pads21cformed on the main surface21aof the SDRAM21are coupled electrically to a plurality of third bonding leads (electrodes)2pon the main surface2aof the first wiring substrate2through a plurality of wires3.

The wires3are laid in a direction along the first sides2mof the first wiring substrate2. That is, the wires3for coupling the third pads21cof the SDRAM21and the third bonding leads2pof the first wiring substrate2electrically with each other are each formed along the short sides of the SDRAM21.

Thus, since the wires3coupled to the SDRAM21are laid along the short sides of the SDRAM21(the first sides2mof the first wiring substrate2), they extend along a resin flowing direction10in forming the first sealing body4, so that it is possible to diminish obstruction of the wires3to the flow of resin.

Consequently, it is possible to diminish peeling-off of the wires and the formation of voids.

That is, it is preferable that the wires3coupled to the SDRAM21be laid along the resin flowing direction10in resin molding. Particularly, in the case of the center pad layout of the SDRAM21, the wire length becomes long, so that wiring along the resin flowing direction is more effective against obstruction to the flow of resin.

Other structural points of the POP type semiconductor device19of this second embodiment, as well as other effects obtained by the POP type semiconductor device19, are the same as those described above in connection with the POP type semiconductor device8of the first embodiment, so repeated explanations thereof will be omitted here.

Next, a modification of the second embodiment will be described below with reference toFIGS. 47 and 48.

In a POP type semiconductor device19shown inFIGS. 47and48, chip parts20are mounted, in addition to the controller chip1and the SDRAM21, onto the wiring substrate2of the first semiconductor package7as a lower package.

More specifically, in the first semiconductor package7as a lower package of the POP type semiconductor device19, chip parts20may be mounted next to the controller chip1or the SDRAM21. As shown inFIG. 48, the controller chip1and the SDRAM21, as well as the chip parts20mounted peripherally of those chips, are all resin-sealed by the first sealing body4.

Third Embodiment

FIG. 50is a plan view showing a structural example of a first semiconductor package in a semiconductor device according to a third embodiment of the present invention as seen through a sealing body andFIG. 51is a sectional view taken along line B-B inFIG. 50, showing a structural example of the semiconductor device of the third embodiment.FIG. 52is a plan view showing the structure of a first semiconductor package in a first modification of the semiconductor device of the third embodiment as seen through a sealing body,FIG. 53is a sectional view taken along line B-B inFIG. 52, showing the structure of the first modification of the semiconductor device of the third embodiment,FIG. 54is a plan view showing the structure of a first semiconductor package in a second modification of the semiconductor device of the third embodiment as seen through a sealing body, andFIG. 55is a sectional view taken along line B-B inFIG. 54, showing the structure of the second modification of the semiconductor device of the third embodiment. Further,FIG. 56is a plan view showing the structure of a second semiconductor package in the semiconductor device ofFIG. 55as seen through a sealing body andFIG. 57is a bottom view showing a structural example of a back surface side of the semiconductor device ofFIG. 55.

The semiconductor device of this third embodiment shown inFIGS. 50 and 51, like the semiconductor device of the second embodiment, is a POP type semiconductor device22of a structure wherein semiconductor packages are stacked in multiple stages, with a second semiconductor package17as an upper package being stacked on a first semiconductor package7as a lower package.

In the POP type semiconductor device22of this third embodiment, reinforcing lands (third lands)2qfor improving the mounting strength of a second wiring substrate12in the second semiconductor package17as an upper package are provided on a first wiring substrate2.

More specifically, in the POP type semiconductor device22, a sealing body4formed on the first semiconductor package7is comprised of a first sealing portion4afor sealing a controller chip1and second sealing portions4bintegral with the first sealing portion4aand formed on both sides of the first sealing portion4awhich extends in a direction along first sides2m. On a main surface2aof the first wiring substrate2, reinforcing lands2qas third lands are formed on both sides of the second sealing portions4bin a direction along second sides2n. In the semiconductor package7shown inFIGS. 50 and 51, the reinforcing lands2qare formed at four positions peripherally of the first sealing portion4a. The reinforcing lands2qare also coupled to the second wiring substrate12as an upper substrate through solder balls15, whereby the mounting strength of the second wiring substrate12as an upper substrate can be improved.

The reinforcing lands2qare positioned between main surface-side lands2eserving as signal transfer paths and the second sealing portions4b.

In the POP type semiconductor device22, the width of each second sealing portion4bin a direction along the second sides2nis formed smaller than that of the first sealing portion4ain the same direction in order to sidestep the reinforcing lands2q.

That is, for sidestepping the reinforcing lands2q, the width in a direction along the second sides2nof each second sealing portion4bformed peripherally of the controller chip1is set smaller than the width in the same direction of the first sealing portion4awhich seals the controller chip1.

However, the thickness of each second sealing portion4bis larger than that of the first sealing portion4a, as shown inFIG. 51.

That is, as a result of sidestepping the reinforcing lands2q, the second sealing portions4blocated outside the first sealing portion4aare each smaller in width but larger in height than the first sealing portion4a.

With such first sealing portion4aand second sealing portions4b, resin can be allowed to flow at a stable flow velocity when resin is supplied in the resin molding step.

Other structural points of the POP type semiconductor device22of this third embodiment, as well as other effects obtained by the POP type semiconductor device22, are the same as those described above in connection with the POP type semiconductor device19of the second embodiment, so repeated explanations thereof will be omitted here.

Next, a description will be given below about a modification of the third embodiment.

According to a first modification of the third embodiment shown inFIGS. 52 and 53, chip parts20mounted on the main surface2aof the first wiring substrate2in the first semiconductor package7are sealed by the second sealing portion4b.

That is, the chip parts20are in many cases larger in thickness (mounting height) than the controller chip1and the SDRAM21and even high chip parts20can be sealed by the second sealing portion4b.

Next, a description will be given below about a second modification of the third embodiment shown inFIGS. 54 to 57.

As described above in the first modification, the second sealing portions4bare each thicker than the first sealing portion4a. In other words, the first sealing portion4ais thinner than the second sealing portions4b.

That is, the height of the first sealing portion4awhich corresponds to near the central part of the first sealing body4comprised of the first sealing portion4aand the second sealing portions4bis smaller than that of the second sealing portions4blocated outside the first sealing portion4a.

Therefore, in the case where a planar size of the second wiring substrate12shown inFIG. 56is smaller than that of the first wiring substrate2shown inFIG. 54, a back surface12bof the second wiring substrate12is disposed at a position higher than the first sealing portion4aand lower than the second sealing portions4b, as shown inFIG. 55.

More specifically, in the case where an outline size of the second wiring substrate12as an upper substrate is smaller than that of the first wiring substrate2as a lower substrate (in the case where the size of a second chip mounting region12dis almost equal to that of a main surface12aof the second wiring substrate12, as shown inFIG. 56), the thickness of the first sealing portion4ais made smaller than that of each second sealing portion4bto form a concaved stepped portion4c, as shown inFIG. 55, whereby the second wiring substrate12can be disposed in the concaved stepped portion4cand hence it is possible to reduce the package height of the completed POP type semiconductor device22.

In this third embodiment, even where the reinforcing lands2qare not provided (whether or not the reinforcing lands2qare provided), chip parts20large in height can be sealed by the second sealing portions4bby making the second sealing portions4bthicker than the first sealing portion4a.

Fourth Embodiment

FIG. 58is an enlarged partial plan view showing the structure after resin molding in assembling a first semiconductor package in a semiconductor device according to a fourth embodiment of the present invention andFIG. 59is a sectional view taken on line A-A inFIG. 58, showing the structure of the semiconductor device of the fourth embodiment.

The semiconductor device of this fourth embodiment shown inFIGS. 58 and 59, like the semiconductor device of the third embodiment, is a POP type semiconductor device23of a structure in which semiconductor packages are stacked in multiple stages, with a second semiconductor package17as an upper package being stacked on a first semiconductor package7as a lower package.

The POP type semiconductor device23of this fourth embodiment is formed with third sealing portions4dfor improving the strength of a first wiring substrate2of the first semiconductor package7as a lower package.

More specifically, in the first semiconductor package7as a lower package, the third sealing portions4dare each formed outside a row of plural main surface-side lands2eon a main surface2aof the first wiring substrate and along a first side2m, and end portions of a back surface12bof a second wiring substrate12in the second semiconductor package17as an upper package are supported by the third sealing portions4d.

More specifically, an elongated third sealing portion4dis formed outside and along each row of the main surface-side lands2eon the main surface2aof the first wiring substrate2in the first semiconductor package7, and end portions of the back surface12bof the second wiring substrate12as an upper substrate are supported by the third sealing portions4d.

With this arrangement, it is possible to improve the strength of the first wiring substrate2as a lower substrate.

In the case of mounting such chip parts20as shown inFIG. 53onto the first wiring substrate2as a lower substrate, the chip parts20may be sealed with a third sealing portion4d.

The thickness of each third sealing portion4dis made larger than that of a first sealing body4(a first sealing portion4aand second sealing portions4b) which seals a controller chip1. In other words, by making the first sealing body4sealing the controller chip1thinner than the third sealing bodies4dto form a gap24between the first sealing body4and the second wiring substrate12, the first sealing body4can be prevented from pushing up the overlying second wiring substrate12even when the first wiring substrate2as a lower substrate warps convexly.

Moreover, since the second wiring substrate12is supported by the third sealing portions4d, it is possible to cope with stress imposed thereon from the upper side and hence possible to prevent cracking of the first semiconductor package7. Besides, since the second semiconductor package17as an upper package is supported by the third sealing portions4d, it is possible to lessen collapse of solder balls15.

Consequently, it is possible to prevent short-circuit between adjacent solder balls15.

Further, since it is possible to diminish collapse of solder balls15, the diameter of each solder ball15can be made small beforehand. That is, the distance between the first wiring substrate2as a lower substrate and the second wiring substrate12as an upper substrate can be shortened and the number of solder balls15to be provided can be increased by making the size of each solder ball15small and by setting the ball mounting pitch small.

Other structural points of the POP type semiconductor device23of this fourth embodiment and other effects obtained by the POP type semiconductor device23are the same as those described above in connection with the POP semiconductor device22of the third embodiment, so repeated explanations thereof will be omitted here.

Although the present invention has been described above concretely by way of embodiments thereof, it goes without saying that the present invention is not limited to the above embodiments and that various changes may be made within the scope not departing from the gist of the invention.

For example, in the above first to fourth embodiments, the second semiconductor chip mounted on the second semiconductor package17as an upper chip is a memory chip (non-volatile memory11) and one such memory chip is mounted. However, also in the second semiconductor package17as an upper package there may be mounted plural memory chips in a stacked fashion. In this case, by using one type of memory chips to be stacked, it is possible to use terminals in common and plural memory chips can be stacked without increasing the number of terminals.

The size in a planar direction of the first semiconductor package7as a lower package and that of the second semiconductor package17as an upper package may be the same or different.

The present invention is suitable for an electronic device having a plurality of semiconductor chips.