A semiconductor device includes a first drain region that is made primarily of SiC, a drift layer, a channel region, a first source region, a source electrode that is formed on the first source region, a second drain region that is connected to the first source region, a second source region that is formed separated from the second drain region, a first floating electrode that is connected to the second source region and to the channel region, first gate electrodes, and a second gate electrode that is connected to the first gate electrodes.

BACKGROUND OF THE INVENTION

Technical Field

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

Wide-bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and diamond (C) are expected to have numerous applications, particularly in power devices, due to having excellent performance characteristics such as high dielectric breakdown field strength and high thermal conductivity. Among these, SiC in particular has attracted attention due to allowing oxide films (SiO2) to be formed using thermal oxidation processes, similar to when working with pure silicon (Si).

Semiconductor devices that use wide-bandgap semiconductors exhibit higher dielectric breakdown field strength than those that use Si. For example, 4H—SiC, GaN, and diamond respectively make it possible to achieve dielectric breakdown field strengths of approximately 10, 11, and 19 times greater than with Si. For a device of a given breakdown voltage, this makes it possible to increase the impurity concentration and decrease the thickness of a low concentration n-type (n−) drift layer, thereby making it possible to achieve a high breakdown voltage and a low on-resistance.

If the SiC body diode is used as the path for this reverse current, the on-resistance increases (this is a well-known phenomenon).

This increase in on-resistance is thought to be due to an increase in the portion of the current path through which it is difficult for current to flow that occurs when a forward current flows across the body diode after the conductivity is modulated (see Non-Patent Document 1, for example). The specific reason behind this increase in the portion through which it is difficult for current to flow is thought to be the formation of stacking faults in the crystal structure of the SiC due to the recombination energy of the majority carriers and the minority carriers.

One method of preventing current from flowing through the SiC body diode is to allow current to flow through the channel of the MOSFET, for example. However, switching ON the switching elements in both the upper and lower arms at the same time can cause a short-circuit in the power supply. Moreover, switching OFF some of the switching elements in order to prevent multiple switching elements from being ON at the same time results in an increase in OFF time (or so-called dead time). Furthermore, a forward current will still flow through the SiC body diode during this dead time.

Another method of preventing current from flowing through the SiC body diode is to connect diodes (Schottky diodes) in parallel with each switching element. However, if the forward voltage across these diodes becomes greater than or equal to the built-in voltage of the body diode of the switching element (which is approximately 2.3V for SiC), current begins to flow through the SiC body diode. This creates a need to reduce the forward voltage Vf of the diodes, which typically makes it necessary to prepare larger-area diodes and results in an overall increase in cost.

RELATED ART DOCUMENT

Non-Patent Document 1: A New Degradation Mechanism in High-Voltage SiC Power MOSFETs, Agarwal et al., IEEE Electron Device Letters, Volume 28 Issue 7 Pages 587-589, 2007

SUMMARY OF THE INVENTION

The present invention was made in view of the abovementioned problems and aims to provide an SiC semiconductor device and a method of manufacturing the same that make it possible to prevent an increase in on-resistance. Accordingly, the present invention is directed to a scheme that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in one aspect, the present disclosure provides a semiconductor device, including: a first drain region of a first conductivity type and made primarily of silicon carbide, in the substrate; a drift layer of the first conductivity type above the first drain region; a channel region of a second conductivity type above the drift layer; a first source region of the first conductivity type in a portion of an upper surface of the channel region; a source electrode above the first source region; a second drain region of the first conductivity type disposed in a portion of the upper part of the channel region and having a pattern connected to the first source region; a second source region of the first conductivity type in a portion of the upper surface of the channel region and separated from the second drain region; a first floating electrode connected to the second source region and the channel region; a first gate electrode controlling a surface potential of a path for current that flows from the first source region in the channel region to the drift layer; and a second gate electrode that is connected to the first gate electrode and that controls a surface potential of the channel region between the second drain region and the second source region.

In another aspect, the present disclosure provides: a method of manufacturing a semiconductor device, including: forming, on a first drain region made of silicon carbide, a drift layer of a first conductivity type and a lower concentration of impurities than the first drain region; forming a channel region of a second conductivity type above the drift layer; forming, in a portion of an upper surface of the channel region, a first source region of the first conductivity type, a second drain region of the first conductivity type to be connected to the first source region, and a second source region of the first conductivity type separated from the second drain region; forming a gate insulating film above the channel region; forming, above the gate insulating film, a first gate electrode controlling a surface potential of a path for current that flows from the first source region in the channel region to the drift layer, and a second gate electrode connected to the first gate electrode and controlling a surface potential of the channel region between the second drain region and the second source region; forming a source electrode on the first source region; and forming a first floating electrode separated from the source electrode and connected to the second source region and the channel region.

The semiconductor device and the method of manufacturing the semiconductor device according to the present invention make it possible to provide an SiC semiconductor device and a method of manufacturing the same that make it possible to prevent an increase in on-resistance.

DETAILED DESCRIPTION OF EMBODIMENTS

Next, Embodiments 1 to 8 of the present invention will be described. In the figures described below, the same or similar reference characters are used for components that are the same or similar. Note, however, that the figures are only intended to be schematic illustrations, and the relationships between thickness and planar dimensions, the proportional relationships between the thicknesses of each device and each component, and the like may be different than in the actual devices. Therefore, specific thicknesses and dimensions should be determined by referencing the descriptions below. Similarly, the illustrated dimensional relationships and proportions of components in the figures may differ from one figure to the next.

Moreover, in the following descriptions, the “left and right” and the “up and down” directions are defined only for the purposes of convenience and do not limit the technical concepts of the present invention in any way. Therefore, the figures may be rotated by 90° such that the “left and right” and the “up and down” directions are interchanged, or the figures may be rotated by 180° such that the “left” direction becomes the “right” direction and the “right” direction becomes the “left” direction, for example.

Furthermore, in the present specification and the attached drawings, the letters “n” and “p” are used to indicate whether the majority carriers in a region or layer are electrons or holes, respectively. Moreover, the symbols + and − are appended to the letters n and p to indicate that the corresponding semiconductor region has a higher or lower impurity concentration, respectively, than a semiconductor region for which the symbols + and − are not appended to the letters n and p. More, even when regions have the same notation (such as when two regions are both labeled as n+), this does not necessarily mean that those regions have exactly the same impurity concentrations.

As illustrated inFIG. 1, a semiconductor device according to Embodiment 1 includes an active portion in which a plurality of stripe-shaped basic cells . . . ,1001j−1,1001j,1001j+1, . . . and . . . ,1002j−1,1002j,1002j+1, . . . are arranged and an edge termination structure300formed around the periphery of the active portion. In a front view of the upper surface of the semiconductor device, the plurality of basic cells . . . ,1001j−1,1001j,1001j+1, . . . and . . . ,1002j−1,1002j,1002j+1, . . . are embedded in the active portion on the inner side of the frame-shaped edge termination structure300.

As illustrated inFIG. 2, each basic cell100ij(where i=1 or 2 and j=1 to n, where n is a positive number greater than or equal to 2) includes a standard unit110ij(a region through which a primary current flows) and a built-in transistor120ij(a region for short-circuiting an SiC body region (3,4) and a source region in the standard unit110ij) that is connected to the standard unit110ij. Here, the “body region (3,4)” is an SiC region that includes a channel region3and a base region4. One or more standard units110ijand one or more built-in transistors120ijmay be arranged within each basic cell100ij.

The plurality of basic cells . . . ,1001j−1,1001j,1001j−1, . . . and . . . ,1002j−1,1002j,1002j+1, each have a stripe-shaped topology that is elongated in the vertical direction inFIG. 1, and these stripes are arranged parallel to one another in a line in the left-to-right direction. In the active portion, a substantially square-shaped gate pad400is formed towards the right side thereof and in the center in the height direction inFIG. 1, and a gate runner500is arranged extending out from the left edge of the gate pad400and extending in the left side direction of the gate pad400through the center portion.

The active portion is thus roughly divided vertically into two regions by the gate pad400and the gate runner500. The plurality of basic cells . . . ,1001j−1,1001j,1001j−1, . . . are arranged in the upper region except for on the ends in the left-to-right direction. Similarly, the plurality of basic cells . . . ,1002j−1,1002j,1002j+1, . . . are arranged in the lower region.

Note that although the active portion is divided vertically into two regions in Embodiment 1, the active portion may be divided into m or more regions i=1 to m in the vertical direction (where m is a positive number greater than or equal to 1). Moreover, as illustrated by the region in the dashed circle A at the bottom end of the basic cell1002jinFIG. 1, a pair of the built-in transistors1202j(that is, the built-in transistors120ij; schematically illustrated by the dashed rectangular regions) are formed respectively at each end of each stripe.

The basic cells100ijof the semiconductor device according to Embodiment 1 include a high concentration n-type (n+) first drain region1that is made primarily of SiC and is formed spanning across the respective standard units110ijand the respective built-in transistors120ij. An n-type drift layer2that has a lower impurity concentration than the first drain region1is formed on top of the first drain region1.

The drift layer2can be formed by being epitaxially grown on the first drain region1, for example. For an SiC element in the 1200V breakdown voltage class, for example, the impurity concentration and thickness of the drift layer2should be approximately 1.0×1016cm−3and approximately 10 μm, respectively, and further increasing the breakdown voltage requires the impurity concentration to be decreased and the thickness to be increased. The high concentration p-type (p+) base region4is formed on top of the drift layer2. The base region4prevents punchthrough from occurring in the channel region3when a high reverse bias is applied to the p-n junction between the channel region3and the drift layer2.

The basic cells100ijof the semiconductor device according to Embodiment 1 also include the p-type channel region3, which is formed on a portion of the upper surface of the base region4and has a lower impurity concentration than the base region4. The channel region3can be formed by being epitaxially grown on the base region4, for example. The drift layer2, the base region4, and the channel region3are all formed spanning across the standard units110ijand the built-in transistors120ij.

The drain region1and the drift layer2have the same structures in both the standard units110ijand the built-in transistors120ijof the basic cells100ij, while the structures of the upper layers (the base region4and above) are different for the standard units110ijand for the built-in transistors120ij.

(Structure of Standard Unit)

FIG. 2is a cross-sectional view illustrating the structure of the standard unit110ijas viewed along line D-D inFIG. 3. As illustrated inFIG. 3, the standard unit includes a high concentration n-type (n+) first source region5formed in a portion of the upper surface of the channel region3and running parallel to the lengthwise direction of the stripe of the basic cell100ij.

The first source region5has a surface pattern in which openings that go through the first source region5and expose the upper surface of the channel region3are arranged in a pattern running in the vertical direction and parallel to the lengthwise direction of the basic cell100ij.FIG. 3primarily illustrates the structure of the plane on the surface side of the SiC as viewed from above. Note that inFIG. 3, components such as a first insulating film and a second insulating film that are positioned above the channel region3and the first source region5are not illustrated.

The first source region5in which the pattern of openings that go through the first source region5are formed can be formed in a frame shape when viewed in a plan view. The portions of the channel region3that are exposed by the openings in the first source region5are substantially rectangular. Rectangular first potential barrier layers13a1and13a2are respectively formed in the lower and upper exposed portions of the channel region3inFIG. 3. The plurality of openings that expose the channel region3are arranged separated from one another at a prescribed interval, and therefore the first source region5has a ladder-shaped pattern.

FIG. 4illustrates the structure of a cross section taken along line B-B inFIG. 3. As illustrated inFIG. 4, high concentration n-type (n+) JFET regions2b1and2b2are formed at a position beneath low concentration n-type inverted regions2a1and2a2in both sides of the base region4beneath the channel region3(of which a portion of the top thereof is enclosed by the first source region5).

In other words, the inverted regions2a1and2a2are formed above the JFET regions2b1and2b2so as to sandwich the channel region3. The inverted regions2a1and2a2are both formed by using ion implantation of n-type impurity elements to invert the conductivity of the p-type channel region to n-type. The carriers flowing through the inversion layer in the surface of the channel region3travel through the inverted regions2a1and2a2and the JFET regions2b1and2b2and towards the drift layer2.

Furthermore, as illustrated inFIG. 2, a first insulating film7is selectively formed on the channel region3in the standard unit110ij. Moreover, a plurality of first gate electrodes (two first gate electrodes inFIG. 4; not illustrated in the cross section inFIG. 2) are formed on the first insulating film7and extend above the first source region5illustrated inFIG. 3and parallel to the lengthwise direction of the first source region5(the vertical direction inFIG. 3).

The first insulating film7(which functions as the gate insulating film for the first gate electrodes) is an oxide film (SiO2) or the like. High-breakdown voltage elements are typically driven at gate voltages of approximately 15V to 30V, and therefore the thickness of the first insulating film7should typically be 50 nm to 150 nm in order to ensure reliability. In addition, an interlayer insulating film11is formed on the first insulating film7and the first gate electrodes.

Moreover, as illustrated inFIGS. 2 and 3, the first potential barrier layers13a1and13a2are formed on the channel region3where exposed by the openings in the first source region5in order to prevent the majority carriers from being injected into the channel region3. A metal film such as gold (Au), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), or chromium (Cr) that forms a Schottky junction with the channel region3can be used for the first potential barrier layers13a1and13a2, for example.

As illustrated inFIG. 4, a source electrode9is formed contacting the channel region3in channel contact areas17b, with the first potential barrier layers13a1and13a2formed by the Schottky junction with the channel region3interposed therebetween. As illustrated inFIGS. 2 and 3, a first ohmic contact layer12is formed on the first source region5at a position centered between the two openings that expose the channel region3. The first ohmic contact layer12corresponds to the “first ohmic contact layer” in the present invention.

The first ohmic contact layer12may be made of a silicide film that contains a metal such as Ni or an NiAl compound of Ni and aluminum (Al), for example. As illustrated inFIG. 5, the source electrode9contacts the first source region5in a source contact area17a, with the first ohmic contact layer12interposed therebetween.

Furthermore, as illustrated inFIG. 4, the interlayer insulating film11is formed on the first gate electrodes8, and the source electrode9contacts the first ohmic contact layer12and the first potential barrier layers13a1and13a2via openings in the interlayer insulating film11. The source electrode9is thus electrically connected to the first source region5via the first ohmic contact layer12and is electrically connected to the channel region3via the first potential barrier layers13a1and13a2.

The built-in transistor120ijillustrated inFIGS. 1 to 3is a lateral MOSFET that includes a second drain region5aand a second source region5bthat both have a first conductivity type and are formed at the same depth as the first source region5of the standard unit110ij. As illustrated in the figures, the second drain region5acontacts and is integrated with the first source region5. Similar to the first source region5, the second drain region5ais a high concentration n-type (n+) region.

The high concentration n-type (n+) second source region5bis included in a portion of the upper surface of the channel region3in the built-in transistor120ijregion and is formed separated from the second drain region5a. In addition, a high concentration p-type (p+) base contact region6athat contacts the second source region5bis formed in the channel region3in the built-in transistor120ijregion.

As illustrated inFIG. 2, the depth of the base contact region6ais greater than the thickness of the channel region3, and the base contact region6areaches a portion of the upper surface of the base region4. Furthermore, a second insulating film7ais formed on the channel region3between the second drain region5aand the second source region5b, and a second gate electrode8athat is electrically connected to the first gate electrodes8is formed on the second insulating film7a.

Similar to the first insulating film7, the second insulating film7ais an oxide film (SiO2) or the like and functions as the gate insulating film of the second gate electrode8a. As described above, the two first gate electrodes8extend out from both sides of the second gate electrode8ain the vertical direction inFIG. 3, and the first gate electrodes8are connected to the second gate electrode8aon at least one end thereof. As illustrated inFIG. 2, a portion of the interlayer insulating film11is formed spanning across the standard unit110ijand the built-in transistor120ijabove the second gate electrode8a.

The built-in transistor120ijincludes a second ohmic contact layer12athat is formed on the SiC surface in order to make it possible to form a short-circuit between the surface of the base contact region6aand the surface of the second source region5bvia a contact hole that goes through the second insulating film7a. Similar to the first ohmic contact layer12, the second ohmic contact layer12amay be made of a silicide film that contains a metal such as Ni or NiAl.

The same metal or different metals may be used for the portions that respectively contact the surfaces of the base contact region6aand the second source region5b. Furthermore, a first floating electrode9ais formed and is connected to the second ohmic contact layer12avia a contact hole that goes through the interlayer insulating film11in the built-in transistor120ijregion. The base contact region6aand the second source region5bare thus connected to the first floating electrode9avia the second ohmic contact layer12a.

Each basic cell100ijof the semiconductor device according to Embodiment 1 can be represented by the equivalent circuit illustrated inFIG. 6, for example. InFIG. 6, the upper left MOSFET represents the standard unit110ij, and the other MOSFET represents the built-in transistor120ijthat is connected between the channel region3and the source electrode9(that is, to the back gate of the former MOSFET).

Moreover, a parasitic body diode121of the built-in transistor120ijand a p-type Schottky diode130formed between the channel region3and the first potential barrier layers13a1and13a2can be represented as being connected in parallel to the built-in transistor120ij. Similarly, a parasitic junction capacitor140that represents the sum of the junction capacitance of the built-in transistor120ij, the p-type Schottky diode130, and the like can also be represented as being connected in parallel to the built-in transistor120ij.

When a voltage of greater than or equal to a threshold value relative to the source electrode9is applied to the first gate electrodes8, the electric potential of the surface of the channel region3that is directly beneath the first gate electrodes8changes, thereby forming an inversion layer in the surface of the channel region3. If, in this state, a positive voltage relative to the source electrode9is then applied to a drain electrode10, electron paths are formed on both the left and right sides ofFIG. 5.

The path on the left side ofFIG. 5includes the source electrode9, the first ohmic contact layer12, the first source region5, the inversion layer in the surface of the channel region3, the inverted region2a1, the JFET region2b1, the drift layer2, the drain region1, and the drain electrode10.

Similarly, the path on the right side ofFIG. 5includes the source electrode9, the first ohmic contact layer12, the first source region5, the inversion layer in the surface of the channel region3, the inverted region2a2, the JFET region2b2, the drift layer2, the drain region1, and the drain electrode10. As a result, current flows from the drain electrode10to the source electrode9, thus switching the standard unit110ijto the ON state.

While the standard unit110ijis in the ON state, the electric potential of the second gate electrode8aof the built-in transistor120ijthat is connected to the first gate electrodes8causes the built-in transistor120ijto be switched ON as well. As a result, electrons flow from the first source region5, through the second drain region5aand the second source region5bof the built-in transistor120ijthat are connected to the first source region5, and to the first floating electrode9aof the built-in transistor120ij. At this time, the first floating electrode9afunctions as the source electrode of the built-in transistor120ij, which in turn functions as a MOSFET.

The flowing electrons then undergo electron-hole conversion in the second ohmic contact layer12aor the first floating electrode9athat contact the high concentration p-type (p+) base contact region6a. After this conversion, the holes are supplied to the channel region3and the base region4, and therefore the channel region3and the base region4take the same electric potential as the first source region5.

Meanwhile, when a voltage of less than the threshold value relative to the source electrode9of the standard unit110ijis applied to the first gate electrodes8, the inversion layer in the surface of the channel region3disappears, thus switching the standard unit110ijto the OFF state in which no current flows. If a negative voltage is then applied to the first gate electrodes8, the holes get trapped in the interface between the channel region3and the gate oxide film. Here, because the first potential barrier layers13a1and13a2are formed between the channel region3and the source electrode9, the presence of the resulting Schottky junctions prevents the holes from being injected into the channel region3.

The barrier height of the Schottky junctions to the holes must be at least 0.5 eV to ensure that the current density does not exceed the level required for holes to cross the barrier and be injected into the channel region and cause growth of stacking faults due to thermal excitation, and it is preferable that the barrier height be greater than or equal to 1 eV. Meanwhile, to prevent hole current from causing the parasitic bipolar effect when avalanche breakdown occurs during inductive loading or the like, it is also preferable that the barrier height be less than or equal to 2.26 eV (that is, at least 1 eV less than the 3.26 eV bandgap of the 4H—SiC) in order to make it possible to keep the voltage drop of the p-type body region due to the hole current less than or equal to approximately 1V.

The channel region3and the base region4take a negative electric potential relative to the electric potential of the source electrode9, but this is not a problem while in the OFF state. Instead, this actually improves the breakdown voltage because the JFET regions2b1and2b2sandwiched between the base region4become slightly easier to pinch off. Meanwhile, when a negative voltage is applied to the drain electrode10, the Schottky junctions become reverse-biased, and only a small amount of current flows for a short time that depends on the capacitance of the Schottky junctions.

COMPARISON EXAMPLE 1

A semiconductor device according to Comparison Example 1 as illustrated inFIG. 7is a planar vertical SiC power MOSFET in which similar to inFIG. 5, a first ohmic contact layer12is formed on the surfaces of a base contact region6and a first source region5.

This first ohmic contact layer12forms respective ohmic contacts with the base contact region6and the first source region5. However, this configuration does not include the first potential barrier layers13a1and13a2or the built-in transistor120ijillustrated inFIGS. 2 and 3and the like.

Assume that the semiconductor device according to Comparison Example 1 and the semiconductor device according to Embodiment 1 are respectively used to create single-phase inverters of the type illustrated inFIG. 8, in which four MOSFETs20ato20dare connected to a load inductor24. When the two MOSFETs20aand20dare ON, a current Iaflows to the load inductor24. Moreover, when the two MOSFETs20aand20dare switched OFF, the current flowing through the load inductor24gets reversed and becomes a current Ibthat flows through two diodes21cand21b.

In the single-phase inverter that uses the semiconductor device according to Comparison Example 1, the four diodes21a,21b,21c, and21dmust be relatively large-area diodes in order to prevent current from flowing through the SiC and ensure that the forward voltage of the diodes does not become greater than the built-in voltage of the SiC.

Meanwhile, in the single-phase inverter in which the semiconductor device according to Embodiment 1 is used for the four MOSFETs20ato20d, the first potential barrier layers13a1and13a2prevent the holes from being continuously injected into the body region (3,4) at low reverse voltages. Therefore, even when the four diodes21a,21b,21c, and21dare relatively small-area diodes with a high forward voltage, current will not flow through the body diodes of the SiC semiconductor devices if the diodes are connected in parallel to those semiconductor devices.

COMPARISON EXAMPLE 2

FIG. 9illustrates an SiC semiconductor device according to Comparison Example 2, which was developed by the same inventor who developed the present invention and has a structure in which a Schottky junction or heterojunction is formed in a channel region3, thereby preventing holes from being continuously injected into the channel region3, making it possible to extract holes when avalanche breakdown occurs, and making it possible to prevent the parasitic bipolar effect. Similar to in the semiconductor device according to Embodiment 1, in the semiconductor device according to Comparison Example 2, a first potential barrier layers13ais formed on the surfaces of a base contact region6and a first source region5.

Also similar to in the semiconductor device according to Embodiment 1, a first ohmic contact layer12is formed on the surface of the first source region5. However, the built-in transistor120ijof the semiconductor device according Embodiment 1 is not included.

It is well-known that in this type of MOSFET that is made of an SiC semiconductor material, a large number of energy levels are present at the MOSFET interfaces. The inventor's research revealed that the presence of these interface levels results in an increase in gate threshold voltage Vth as well as an increase in the JFET effect. Next, this phenomenon will be described with reference to the band diagram inFIGS. 10A and 10Bof a channel portion of the MOSFET. InFIGS. 10A and 10B, the channel region3that is indicated by the solid lines and the first source region5that is indicated by the dashed lines are superimposed on one another, and the overlapping portions indicated by the dotted line represent portions that have the same energy.

FIG. 10Ais a band diagram of a case in which a negative voltage is applied to the gate of the MOSFET and an accumulation layer is therefore formed on the surface of the channel region3. In this state, the holes in the accumulation layer get trapped in the interface level. Meanwhile,FIG. 10Bis a band diagram of a case in which a voltage greater than or equal to the gate threshold voltage Vth is applied to the gate of the MOSFET. Here, electrons fall from the first source region5and through the inversion layer in the channel region3down to the interface level and are annihilated upon recombining with the trapped holes. This phenomenon is the mechanism behind the so-called charge pumping method, which provides the same results as other methods of studying the energies and density distributions of the interface levels.

Note that although the above description ofFIGS. 10A and 10Bassumes that hole trapping occurs, the holes are only supplied from the channel region3, and the electrons are only supplied from the first source region5, and therefore the same phenomenon occurs in electron trapping situations as well. Therefore, as illustrated in the equivalent circuit diagram inFIG. 11, alternately applying voltages that produce the states illustrated inFIGS. 10A and 10Bto the gate of the MOSFET causes a current Icpto flow from the channel region3to the first source region5.

When the duration for which a voltage continues to be applied to the gate is sufficiently greater than a trapping time constant and a recombination time constant, this current Icpcan be given by equation (1), where f is the frequency of the voltage applied to the gate.
Icp=q·(Nh+Ne)f(1)
Here, Nhis the number of trapped holes and Neis the number of trapped electrons (which are determined by the amplitude of the gate voltage and the trapping energy distribution), while q is the elementary charge. Also, inFIG. 11, the current Icprepresents the average value of the current that flows.

Due to this current Icp, the p-type body region (3,4) takes a negative electric potential, but this electric potential is balanced by leakage current in the Schottky junction or in the junction between the first source region5and the channel region3or the like. Therefore, when a larger number of carriers are trapped and the leakage currents are smaller, the channel region3takes a larger negative electric potential relative to the electric potential of the source.

As a result, the gate threshold voltage Vth of the MOSFET increases due to the so-called back-gate effect, and the JFET effect also becomes more prominent due to the increase in the reverse bias of the p-n junctions between the p-type body region (3,4) and the JFET regions2b1and2b2. This, in turn, causes the on-voltage of the MOSFET to increase. Hole trapping also depends on the flat-band voltage of the channel region but does not occur at gate voltages near 0V.

However, in normal applications such as the bridge circuit illustrated inFIG. 8, for example, switching ON the MOSFET20awhile the MOSFET20cin the opposite arm is in the OFF state causes the maximum rate of increase dV/dt for the source-drain voltage of the MOSFET20cto change. This change in the maximum rate of increase dV/dt causes a current to flow due to the resulting drain-gate capacitance of the MOSFET20c, and the voltage drop associated with the gate resistance created by this current causes the gate voltage to increase and erroneously switch the MOSFET to the ON state. To prevent the MOSFET from being erroneously switched ON in this manner, a negative bias is typically applied to the gate while the MOSFET is in the OFF state.

In the semiconductor device according Comparison Example 2, the interface levels described above are present in the MOSFET. In most cases, states in which holes get trapped only occur when the gate voltage is less than or equal to approximately 0V (although this also depends on other factors such as the flat-band voltage and the gate threshold voltage Vth as well). Therefore, in devices that have a low gate threshold voltage Vth, there are also cases in which holes do not get trapped when a gate voltage of 0V is applied. However, this phenomenon still occurs in devices with lower gate threshold voltages Vth because such devices are more prone to being erroneously switched ON, and therefore a larger negative bias must be applied to the gate to prevent the device from being erroneously switched ON. Meanwhile, in the semiconductor device according to Embodiment 1, the presence of the built-in transistor120ijthat short-circuits the p-type body region (3,4) and the first source region5while the device is ON makes it possible to prevent increases in the on-voltage due to increases in the gate threshold voltage Vth or the JFET resistance resulting from the charge pumping effect, which occurs due to the trapping levels at the gate oxide film and channel region interfaces.

In the semiconductor device according to Embodiment 1, instead of being an ohmic contact, the junction between the p-type body region (3,4) and the source electrode9is a potential barrier layer that prevents the majority carriers from being injected into the body region (3,4). Therefore, even when relatively small-area diodes with a high forward voltage are connected in parallel to the semiconductor device, holes are not continuously injected into the body region, and a current does not flow through the body diode of the semiconductor device. This prevents growth of stacking faults due to recombination, thereby making it possible to effectively solve the problem of deterioration in on-resistance.

Moreover, in the semiconductor device according to Embodiment 1, the built-in transistors120ijare embedded in portions near the edge termination structure300, in portions near the gate pad400, or in portions near the gate runner500. Arranging the built-in transistors120ijof the basic cells100ijin this manner makes it possible to easily connect to the source electrode9using wire bonding or the like even when the built-in transistors120ijeach include the first floating electrode9athat is separated from the source electrode9.

(Method of Manufacturing Semiconductor Device)

Next, an example of a method of manufacturing the semiconductor device according Embodiment 1 will be described with reference toFIGS. 12 to 17. First, as illustrated inFIG. 12, an n+4H—SiC semiconductor substrate1subis prepared, for example, and an n-type drift layer2is formed by epitaxially growing a layer of monocrystalline 4H—SiC on the upper surface of this semiconductor substrate1sub.

Next, a photolithography technology is used to form a mask for selectively implanting ions, and p-type impurities such as Al are ion-implanted at prescribed locations. In addition, a p-type channel region3is formed continuously over the top of a base region4by epitaxially growing another layer of monocrystalline 4H—SiC.

Epitaxially growing the channel region3prevents the decrease in channel mobility that occurs due to ion implantation damage when the channel region3is formed using an ion implantation method (such as in the so-called DMOS). This makes it possible to provide a high-performance semiconductor device with high channel mobility.

Next, a photolithography technology is used to form a resist mask for selectively implanting ions, and ions of an n-type impurity element such as nitrogen (N) ions are implanted in portions of the upper surface of the channel region3using a multi-stage ion implantation process in order to form inverted regions2a1and2a2.

Here, setting the concentration of JFET regions2b1and2b2to be higher than the concentration of the drift layer2makes it possible to reduce the JFET resistance. Moreover, a current spreading layer (CSL) that reduces carrier spreading resistance may be formed at the same time as the JFET regions2b1and2b2by also introducing a higher concentration of impurities than in the drift layer2at the boundaries between the base region4and the drift layer2as well.

Next, a photolithography technology is used to form another resist mask for selectively implanting ions, and ions of an n-type impurity element are implanted in portions of the upper surface of the channel region3using an ion implantation process. As illustrated inFIG. 13, an n+first source region5, an n+second drain region5a, and an n+second source region5bare all selectively formed at the same time.

Furthermore, a photolithography technology may be used to form another resist mask for selectively implanting ions, and a multi-stage ion implantation process that includes various acceleration voltages may be used to implant ions of an p-type impurity element in portions of the upper surface of the channel region3in a region that is reserved for forming a built-in transistor120ijin a later step.

This multi-stage ion implantation process may be performed in multiple stages while changing the acceleration voltage such that the projected range is adjusted to a level that cause the impurities to reach a portion of the upper surface of the base region4in order to selectively form a p+base contact region6athat contacts the second source region5b.

Next, as illustrated inFIG. 14, a thermal oxidation treatment is applied to the upper surface of the semiconductor substrate1subin order to create an SiO2film layer as an insulating film7z. Then, a doped polysilicon film to which impurity elements have been added is formed on the insulating film7zusing a chemical vapor deposition (CVD) process or the like. Next, this doped polysilicon film is selectively removed and patterned using a photolithography technology and an etching technology or the like in order to form a pattern that includes first gate electrodes8and a second gate electrode8a.

Then, an SiO2film is formed on the first gate electrodes8and the second gate electrode8ausing a CVD process or the like, for example, in order to form an insulating film11z. Next, using a photolithography technology, an etching mask for forming contact holes in a channel contact area17band a source/channel contact area17cis formed.

Then, using this etching mask and a reactive ion etching (RIE) process or the like, the insulating film7zand the insulating film11zare selectively removed at locations above openings in the first source region5where the upper surface of the channel region3is exposed. At the same time, the portions of the insulating film7zand the insulating film11zthat are positioned above locations between adjacent openings in the first source region5and above the second source region5band the base contact region6aare also removed.

In this way, as illustrated inFIG. 15, a first insulating film7and an interlayer insulating film11are formed and patterned to have contact holes in a region that is reserved for forming a standard unit110ij. At the same time, a second insulating film7aand the interlayer insulating film11are similarly formed and patterned to have contact holes in the reserved formation region for the built-in transistor120ij.

Next, as illustrated inFIG. 16, a metal film made of Ni, NiAl, or the like is formed on the upper surface of the semiconductor substrate1subusing a method such as sputtering or vacuum deposition, for example. Then, a photolithography technology is used to form an etching mask that will leave this metal film remaining only on the upper surfaces of a source contact area17aand the source/channel contact area17c.

Next, using this etching mask, the portions of the metal film other than those on the upper surfaces of the source contact area17aand the source/channel contact area17care etched and removed, thereby simultaneously forming a first ohmic contact layer12and a second ohmic contact layer12a. The first ohmic contact layer12and the second ohmic contact layer12amay alternatively be formed using a lift-off process.

Next, the thickness of the bottom surface side of the semiconductor substrate1subis reduced using a chemical mechanical polishing (CMP) process to form a drain region1of the type illustrated inFIG. 1. Then, a metal film made of Ni or the like is formed on the surface of the drain region1to form a drain electrode10.

Next, the overall substrate is heat treated (sintered) to improve the ohmic contact between the first source region5and the first ohmic contact layer12and second ohmic contact layer12aas well as the ohmic contact between the drain electrode10and the drain region1. Moreover, when the first ohmic contact layer12and the second ohmic contact layer12aare formed as silicide films, this heat treatment causes silicidation.

Next, a metal film for forming a Schottky junction is formed on the upper surface of the semiconductor substrate1subusing a method such as sputtering or vacuum deposition. Then, similar to the first ohmic contact layer12and the second ohmic contact layer12a, this metal film is selectively removed using a photolithography technology and an etching technology or the like in order to simultaneously form first potential barrier layers13a1and13a2.

Next, as illustrated inFIG. 17, a metal film9zmade of Al or the like is formed over the entire surface using a method such as sputtering or vacuum deposition. Then, using a photolithography technology, a source electrode9is formed contacting the first potential barrier layers13a1and13a2and the first ohmic contact layer12as illustrated inFIG. 2. At the same time, a first floating electrode9aof a pattern separated from the source electrode9is formed contacting the second ohmic contact layer12a. Next, a passivation film (not illustrated in the figures) are formed on the source electrode9, the first floating electrode9a, and the interlayer insulating film11, thus completing the semiconductor device illustrated inFIGS. 1 to 3.

A semiconductor device according to Embodiment 2 is different than Embodiment 1 in that first potential barrier layers13band13care formed not only on the exposed portions of the surface of a channel region3but also on a first ohmic contact layer12, a second ohmic contact layer12a, and an interlayer insulating film11.

As illustrated inFIG. 18, the semiconductor device according to Embodiment 2 includes a basic cell100aijthat includes one or more standard units110aijand one or more built-in transistors120aij. The semiconductor device according to Embodiment 2 also includes a high concentration n-type (n+) first drain region1that is made primarily of SiC and is formed spanning across the standard unit110aijand the built-in transistor120aij.

Furthermore, the semiconductor device according to Embodiment 2 includes an n-type drift layer2that is formed on the first drain region1and has a lower impurity concentration than the first drain region1, as well as a high concentration p-type (p+) base region4that is formed on the drift layer2. The basic cell100aijof the semiconductor device according to Embodiment 2 also includes a p-type channel region3, which is formed on a portion of the upper surface of the base region4and has a lower impurity concentration than the base region4.

In addition, the basic cell100aijof the semiconductor device according to Embodiment 2 includes a high concentration n-type (n+) first source region5formed in a portion of the upper surface of the channel region3of the standard unit110aijand running parallel to the lengthwise direction of the stripe shape of the basic cell100aij. Furthermore, a first insulating film7is selectively formed on the channel region3in the standard unit110aij.

Moreover, first gate electrodes are formed on the first insulating film7and extend parallel to the lengthwise direction of the first source region5. In addition, the first ohmic contact layer12is formed on the first source region5at a position centered between two openings that expose the channel region3. Furthermore, a source electrode9is formed on the first potential barrier layer13bthat is formed on the interlayer insulating film11and the first ohmic contact layer12.

The basic cell100aijof the semiconductor device according to Embodiment 2 also includes a second drain region5aof a first conductivity type that is formed in a portion of the upper surface of the channel region3in the built-in transistor120aijregion and that is electrically connected to the first source region5. The second drain region5ais formed as an integrated part of the first source region5.

Furthermore, the basic cell100aijof the semiconductor device according to Embodiment 2 also includes a high concentration n-type (n+) second source region5bthat is formed in a portion of the upper surface of the channel region3in the built-in transistor120aijregion and that is separated from the second drain region5a.

Furthermore, a second insulating film7ais formed on the channel region3between the second drain region5aand the second source region5b, and a second gate electrode8athat is electrically connected to the first gate electrodes8is formed on the second insulating film7a. The rest of the components of the structure of the semiconductor device according to Embodiment 2 are the same as the corresponding layers, regions, and the like of the semiconductor device according to Embodiment 1, and therefore a redundant description will be omitted here.

As illustrated inFIG. 19, in the semiconductor device according to Embodiment 2, the first potential barrier layer13bthat is arranged on the openings in the first source region5is formed not only on the exposed surfaces of the channel region3but is also formed on the interlayer insulating film11in a continuous manner with the portions on those surfaces. As illustrated inFIG. 20, the first potential barrier layer13bextends over the interlayer insulating film11in the standard unit110aijregion and is also formed on the first ohmic contact layer12that is arranged on the first source region5between the adjacent openings therein.

When a Schottky electrode made of a Schottky metal such as Ti is used for the first potential barrier layers13band13c, the first potential barrier layers13band13cfunction as barrier layers and prevent deterioration in the performance of the semiconductor device. Moreover, forming the first potential barrier layers13band13cas a film over the entire upper surface of the semiconductor substrate and then etching the first potential barrier layers13band13cusing the same photomask used to form the source electrode9makes it possible to reduce the number of manufacturing steps. The rest of the effects of the semiconductor device according to Embodiment 2 are the same as those of the semiconductor device according to Embodiment 1.

A semiconductor device according to Embodiment 3 is different than Embodiment 1 in that p-type (p+) regions3awith a relatively high impurity concentration of approximately 1×1018cm−3, for example, are formed in portions of a channel region3that contact first potential barrier layers13a1and13a2.

As illustrated inFIG. 21, the semiconductor device according to Embodiment 3 includes a basic cell200ijthat includes one or more standard units210ijand one or more built-in transistors220ij. The semiconductor device according to Embodiment 3 also includes a high concentration n-type (n+) first drain region1that is made primarily of SiC and is formed spanning across the standard unit210ijand the built-in transistor220ij.

Furthermore, the basic cell200ijof the semiconductor device according to Embodiment 3 includes an n-type drift layer2that is formed on the first drain region1and has a lower impurity concentration than the first drain region1, as well as a high concentration p-type (p+) base region4that is formed on the drift layer2. The basic cell200ijof the semiconductor device according to Embodiment 3 also includes a p-type channel region3, which is formed on a portion of the upper surface of the base region4and has a lower impurity concentration than the base region4.

The semiconductor device according to Embodiment 3 also includes a high concentration n-type (n+) first source region5formed in a portion of the upper surface of the channel region3of the standard unit210ijand running parallel to the lengthwise direction of the stripe shape of the basic cell200ij. Furthermore, a first insulating film7is selectively formed on the channel region3in the standard unit210ij. Moreover, first gate electrodes are formed on the first insulating film7and extend parallel to the lengthwise direction of the first source region5.

In addition, the first potential barrier layers13a1and13a2are formed on the channel region3where exposed by openings in the first source region5in order to prevent the majority carriers from being injected into the channel region3. A first ohmic contact layer12is formed on a portion of the first source region5where no opening is present. Furthermore, a source electrode9is formed on an interlayer insulating film11, the first ohmic contact layer12, and the first potential barrier layers13a1and13a2.

The basic cell200ijof the semiconductor device according to Embodiment 3 also includes a second drain region5aof a first conductivity type that is formed in a portion of the upper surface of the channel region3in the built-in transistor220ijregion and that is electrically connected to the first source region5. The second drain region5ais formed as an integrated part of the first source region5.

Furthermore, the basic cell200ijof the semiconductor device according to Embodiment 3 also includes a high concentration n-type (n+) second source region5bthat is formed in a portion of the upper surface of the channel region3in the built-in transistor220ijregion and that is separated from the second drain region5a. Furthermore, a second insulating film7ais formed on the channel region3between the second drain region5aand the second source region5b, and a second gate electrode8athat is electrically connected to the first gate electrodes8is formed on the second insulating film7a.

As illustrated inFIG. 22, the p-type regions3aare substantially rectangular, and the rectangular outer peripheries thereof are positioned on the inner periphery side of the openings in the first source region5and between the outer peripheries of the substantially rectangular first potential barrier layers13a1and13a2and the inner peripheries of the substantially rectangular openings. Moreover, as illustrated inFIG. 23, the p-type regions3ahave substantially the same thickness as the channel region3. The rest of the components of the structure of the semiconductor device according to Embodiment 3 are the same as the corresponding layers, regions, and the like of the semiconductor devices according to Embodiments 1 and 2, and therefore a redundant description will be omitted here.

The semiconductor device according to Embodiment 3 makes it possible to reduce the voltage drop caused by the current that flows when holes that are created due to avalanche breakdown or the like are expelled via the Schottky junction, thereby making it possible to reduce occurrence of the parasitic bipolar effect. This remains effective even when the impurity concentration of the overall channel region3is increased and the gate threshold voltage Vth is increased. The rest of the effects of the semiconductor device according to Embodiment 3 are the same as those of the semiconductor device according to Embodiment 1.

As illustrated inFIG. 24, the semiconductor device according to Embodiment 4 is different than Embodiment 1 in that n-type Schottky cells . . . ,6001j−1,6001j,6001j+1, . . . and . . . ,6002j−1,6002j,6002j+1, . . . are formed in the active portion. These n-type Schottky cells600ijare embedded in the active portion and interspersed among normal basic cells100ij.

In other words, similar to in the basic cells100ijin the semiconductor device according to Embodiment 1, the semiconductor device according to Embodiment 4 includes a high concentration n-type (n+) first drain region1that is made primarily of SiC and is formed spanning across standard units110ijand built-in transistors120ijas well as an n-type drift layer2that is formed on the first drain region1and has a lower impurity concentration than the first drain region1.

The basic cells100ijof the semiconductor device according to Embodiment 4 also include a high concentration p-type (p+) base region4that is formed on the drift layer2and a p-type channel region3that is formed on a portion of the upper surface of the base region4and has a lower impurity concentration than the base region4.

In addition, the basic cell100ijof the semiconductor device according to Embodiment 4 includes a high concentration n-type (n+) first source region5formed in a portion of the upper surface of the channel region3of the standard unit110ijand running parallel to the lengthwise direction of the stripe shape of the basic cell100ij. Furthermore, a first insulating film7is selectively formed on the channel region3in the standard unit110ij.

Moreover, first gate electrodes are formed on the first insulating film7and extend parallel to the lengthwise direction of the first source region5. In addition, first potential barrier layers13a1and13a2are formed on the channel region3where exposed by openings in the first source region5in order to prevent the majority carriers from being injected into the channel region3.

A first ohmic contact layer12is formed on the first source region5between adjacent openings therein. Furthermore, a source electrode9is formed on an interlayer insulating film11, the first ohmic contact layer12, and the first potential barrier layers13a1and13a2.

The basic cell100ijof the semiconductor device according to Embodiment 4 also includes a second drain region5aof a first conductivity type that is formed in a portion of the upper surface of the channel region3in the built-in transistor120ijregion and that is electrically connected to the first source region5. The second drain region5ais formed as an integrated part of the first source region5.

Furthermore, the basic cell100ijof the semiconductor device according to Embodiment 4 also includes a high concentration n-type (n+) second source region5bthat is formed in a portion of the upper surface of the channel region3in the built-in transistor120ijregion and that is separated from the second drain region5a. In addition, a second insulating film7ais selectively formed on the channel region3between the second drain region5aand the second source region5b.

A second gate electrode8athat is electrically connected to the first gate electrodes8is formed on the second insulating film7a. The rest of the components in the structure of the basic cell100ijof the semiconductor device according to Embodiment 4 are the same as the corresponding layers, regions, and the like of the semiconductor devices according to Embodiments 1 to 3, and therefore a redundant description will be omitted here.

As illustrated in the region surrounded by the dotted line inFIG. 25, in the n-type Schottky cells600ij, the channel region3and the base region4beneath the channel region3as illustrated inFIG. 2are not formed, and the upper surface of an inverted region2a3is exposed on the surface of a body region. As illustrated inFIG. 26, a first potential barrier layer13dthat is made of a Schottky metal is formed on the upper surface of the inverted region2a3and overlapping with the portion of the channel region3that surrounds the inverted region2a3. Moreover, as illustrated inFIG. 26, a high concentration n-type (n+) JFET region2b3is formed beneath the inverted region2a3.

It is preferable that the gap in the channel region3that sandwiches the inverted region2a3be the same as in the basic cell100ijin order to maintain the breakdown voltage. Moreover, the width of the n-type Schottky cells600ijmay be greater than that of the basic cells100ij. However, increasing the width of the n-type Schottky cells600ijdecreases the breakdown voltage, and therefore in this case a plurality of channel regions3and base regions4should be formed in the n-type Schottky cells600ijin order to keep the gaps in the channel region3uniform.

Furthermore, as illustrated inFIG. 27, the first potential barrier layer13dis connected to the source electrode9via a source/channel contact area17c(which is a Schottky contact area). In addition, the channel region3and the base region4beneath the channel region3are connected to the basic cells100ijby the ends of the n-type Schottky cells600ij.

Although in Embodiment 4 the first potential barrier layer13dis also formed on a portion of the channel region3, the first potential barrier layer13dand the contact area may alternatively be formed just on the inverted regions2a1and2a2.

The same p-type or n-type metal may be used throughout for the Schottky metal used to form the first potential barrier layer13d, or different metals with the optimal conductivity types for those metals may be used.

Moreover, in the n-type Schottky cell600ijillustrated inFIGS. 24 to 27, a lateral MOSFET that functions as a built-in transistor120ijis not formed. However, a built-in transistor120ijmay be formed by extending the first source region5from the adjacent basic cell100to form a second drain region5afor that built-in transistor120ij.

In the semiconductor device according to Embodiment 4, the n-type Schottky junctions can function as a built-in Schottky diode that is connected in parallel to the semiconductor device, thereby removing the need to connect a separate Schottky diode to the semiconductor device externally. Moreover, the semiconductor device according to Embodiment 4 makes it possible to form Schottky barrier diodes on the same chip without increasing the number of manufacturing steps.

P-type Schottky junctions currently do not yet exhibit satisfactory levels of performance. This is because for a given concentration of p-type or n-type impurities, the p-type impurities exhibit a larger resistance and a relatively large contact resistance. Therefore, in order to prevent the voltage drop and the parasitic bipolar effect from being significant when hole current flows to the source electrode due to avalanche breakdown or the like, relatively large Schottky regions would need to be formed.

The n-type Schottky junctions in the semiconductor device of the present invention are therefore particularly advantageous in that these Schottky junctions can have a smaller area, which minimizes any increases in chip area and also removes the need for die bonding components or wire bonding processes for connecting external Schottky diodes. The rest of the effects of the semiconductor device according to Embodiment 4 are the same as those of the semiconductor device according to Embodiment 1.

In the semiconductor devices illustrated inFIGS. 1 to 27, the first gate electrodes8were all planar gates. A semiconductor device according to Embodiment 5 is therefore different than Embodiment 1 in that this semiconductor device has a trench-gate structure in which trenches18aand18bare formed in inverted regions2a1and2a2and in portions of a channel region3that contacts the inverted regions2a1and2a2.

As illustrated inFIG. 28, the semiconductor device according to Embodiment 5 includes a basic cell700ijthat includes one or more standard units710ijand one or more built-in transistors720ij. The basic cells700ijof the semiconductor device according to Embodiment 5 include a high concentration n-type (n+) first drain region1that is made primarily of SiC and is formed spanning across the respective standard units710ijand the respective built-in transistors720ij.

Furthermore, the basic cell700ijof the semiconductor device according to Embodiment 5 includes an n-type drift layer2that is formed on the first drain region1and has a lower impurity concentration than the first drain region1, as well as a high concentration p-type (p+) base region4that is formed on the drift layer2. The basic cell700ijof the semiconductor device according to Embodiment 5 also includes the p-type channel region3, which is formed on a portion of the upper surface of the base region4and has a lower impurity concentration than the base region4.

In addition, the basic cell700ijof the semiconductor device according to Embodiment 5 includes a high concentration n-type (n+) first source region5formed in a portion of the upper surface of the channel region3of the standard unit710ijand running parallel to the lengthwise direction of the stripe shape of the basic cell700ij. Furthermore, first potential barrier layers13a1and13a2are formed on the channel region3where exposed by openings in the first source region5in order to prevent the majority carriers from being injected into the channel region3.

Moreover, a first ohmic contact layer12is formed on the first source region5between adjacent openings therein. In addition, a source electrode9is formed on an interlayer insulating film11, the first ohmic contact layer12, and the first potential barrier layers13a1and13a2.

The basic cell700ijof the semiconductor device according to Embodiment 5 also includes a second drain region5aof a first conductivity type that is formed in a portion of the upper surface of the channel region3in the built-in transistor720ijregion and that is electrically connected to the first source region5. The second drain region5ais formed as an integrated part of the first source region5.

Furthermore, the basic cell700ijof the semiconductor device according to Embodiment 5 also includes a high concentration n-type (n+) second source region5bthat is formed in a portion of the upper surface of the channel region3in the built-in transistor720ijregion and that is separated from the second drain region5a. The rest of the components of the structure of the semiconductor device according to Embodiment 5 are the same as the corresponding layers, regions, and the like of the semiconductor devices according to Embodiments 1 to 4, and therefore a redundant description will be omitted here.

As illustrated inFIG. 28, the trenches18aand18bare formed at positions corresponding to the areas directly beneath the first gate electrodes8in the semiconductor device according to Embodiment 1. In other words, the trenches18aand18bare formed at positions corresponding to the exposed portions of the channel region3and the inverted regions2a1and2a2on the SiC surface of the semiconductor device illustrated inFIG. 3.

As illustrated inFIG. 29, trench-type first gate electrodes8a1and8b1are respectively formed inside the trenches18aand18bwith a first insulating film7interposed therebetween. Moreover, as illustrated inFIG. 30, the high concentration p-type (p+) base region4is selectively formed in the upper portion of the drift layer2such that the upper surface of the base region4contacts the bottom surface of the channel region3. The rest of the effects of the semiconductor device according to Embodiment 5 (that is, the effects other than those due to having a trench structure) are the same as the effects of the semiconductor device according to Embodiment 1.

Moreover, in the semiconductor device according to Embodiment 5, extending the first gate electrodes8a1and8b1of the standard unit710ijtowards the built-in transistor720ijside makes it possible to use those extended portions as a second gate electrode in the built-in transistor720ij. However, when using the gate electrodes of the standard unit710ijalso as the gate electrode of the built-in transistor720ijin this way, the channel width of the built-in transistor720ijbecomes equal to the depth of the second source region5band the second drain region5a.

In other words, the channel width is less than in the planar structure illustrated inFIG. 3. Therefore, as an alternative, a planar-gate MOSFET structure may be formed just on the built-in transistor720ijside by forming a second insulating film7aand a second gate electrode8aof the type illustrated inFIG. 2on the surface of the SiC body region.

As illustrated in the plan view inFIG. 33, a semiconductor device according to Embodiment 6 is different than Embodiment 1 in that the structure inside openings in a first source region5is different. InFIG. 3, the channel region3is exposed inside of the openings in the first source region5, while inFIG. 33a channel region3is not exposed inside of the openings in the first source region5.

Due to the differences in the planar structure illustrated inFIG. 33, the cross-sectional structure illustrated inFIG. 32is also different than the structure inside of the openings in the first source region5as illustrated inFIG. 2. The semiconductor device includes an active portion in which a plurality of stripe-shaped basic cells800ijare arranged and an edge termination structure300formed around the periphery of the active portion.

As illustrated inFIG. 32, the basic cell800ijof the semiconductor device according to Embodiment 6 includes one or more standard units810ijand one or more built-in transistors820ij. The standard unit810ijis a region through which a primary current flows, and the built-in transistor820ijis connected to the standard unit810ijin order to be able to form a short-circuit between an SiC body region (3,4) and a source region of the standard unit810ij.

The basic cells800ijof the semiconductor device according to Embodiment 6 include a high concentration n-type (n+) first drain region1that is made primarily of SiC and is formed spanning across the respective standard units810ijand the respective built-in transistors820ij. Furthermore, the basic cell800ijof the semiconductor device according to Embodiment 6 includes an n-type drift layer2that is formed on the first drain region1and has a lower impurity concentration than the first drain region1, as well as a high concentration p-type (p+) base region4that is formed on the drift layer2.

The basic cell800ijof the semiconductor device according to Embodiment 6 also includes the p-type channel region3, which is formed on a portion of the upper surface of the base region4and has a lower impurity concentration than the base region4. In addition, the basic cell800ijof the semiconductor device according to Embodiment 6 includes a high concentration n-type (n+) first source region5formed in a portion of the upper surface of the channel region3of the standard unit810ijand running parallel to the lengthwise direction of the stripe shape of the basic cell800ij.

Moreover, a first ohmic contact layer12is formed on the first source region5between the adjacent openings therein. In addition, a source electrode9is formed on an interlayer insulating film11and on the first ohmic contact layer12. The basic cell800ijof the semiconductor device according to Embodiment 6 also includes a second drain region5aof a first conductivity type that is formed in a portion of the upper surface of the channel region3in the built-in transistor820ijregion and that is electrically connected to the first source region5.

The second drain region5ais formed as an integrated part of the first source region5. Furthermore, the basic cell800ijof the semiconductor device according to Embodiment 6 also includes a high concentration n-type (n+) second source region5bthat is formed in a portion of the upper surface of the channel region3in the built-in transistor820ijregion and that is separated from the second drain region5a.

As illustrated inFIG. 32, the semiconductor device according to Embodiment 6 includes n-type inverted regions2a4and2a5that are formed in a region of the channel region3that is surrounded by the first source region5. The semiconductor device according to Embodiment 6 also includes high concentration p-type (p+) base contact regions6b1and6b2that are formed in the inverted regions2a4and2a5.

The semiconductor device according to Embodiment 6 also includes second potential barrier layers13b1and13b2that contact the inverted regions2a4and2a5as well as third ohmic contact layers12b1and12b2that contact the base contact regions6b1and6b2. Second floating electrodes9b1and9b2are respectively connected to the second potential barrier layers13b1and13b2and to the third ohmic contact layers12b1and12b2in the regions surrounded by the first source region. The third ohmic contact layers12b1and12b2correspond to “second ohmic contact layers” in the present invention.

As illustrated inFIG. 33, the inverted regions2a4and2a5have a frame shape when viewed in a plan view and are formed contacting at least a portion of the first source region5. As illustrated inFIG. 34, and similar to a base contact region6aof the built-in transistor820ij, the base contact regions6b1and6b2have a depth that reaches the upper portion of the base region4. Moreover, the cross-sectional structure of the basic cell800ijof the semiconductor device according to Embodiment 6 at the position of a source contact area17a(that is, the structure as taken along a line corresponding to line C-C inFIG. 3) is the same as the cross-sectional structure of the basic cell100ijof the semiconductor device according to Embodiment 1 as illustrated inFIG. 5.

The second potential barrier layers13b1and13b2are formed on a portion of the surfaces of the inverted regions2a4and2a5and in Schottky region contact areas17dthat are formed in openings in the interlayer insulating film11. As illustrated inFIG. 33, the second potential barrier layers13b1and13b2of the semiconductor device according to Embodiment 6 have a frame shape when viewed in a plan view. The second potential barrier layers13b1and13b2are made of a Schottky metal and form Schottky junctions with the inverted regions2a4and2a5.

The third ohmic contact layers12b1and12b2are formed on a portion of the surfaces of the base contact regions6b1and6b2and in contact region contact areas17ethat are formed in openings in the interlayer insulating film11. As illustrated inFIG. 33, the third ohmic contact layers12b1and12b2are rectangular when viewed in a plan view. The third ohmic contact layers12b1and12b2are silicide layers. The second floating electrodes9b1and9b2are formed inside of the interlayer insulating film11on the second potential barrier layers13b1and13b2and the third ohmic contact layers12b1and12b2and are thus insulated from the source electrode9.

The second floating electrodes9b1and9b2are respectively connected to the inverted regions2a4and2a5via the second potential barrier layers13b1and13b2and are also respectively connected to the base contact regions6b1and6b2via the third ohmic contact layers12b1and12b2. As illustrated inFIG. 34, the inverted regions2a4and2a5may be formed at the same time that inverted regions2a1and2a2are formed beneath the first gate electrodes8. Alternatively, in order to reduce the on-resistance of the Schottky diodes formed by the second potential barrier layers13b1and13b2and the inverted regions2a4and2a5, the inverted regions2a4and2a5may be formed in a separate ion implantation process and using a higher impurity concentration.

As illustrated inFIG. 33, in the basic cells800ijof the semiconductor device according to Embodiment 6, the standard units810ijare arranged in a repeating manner such that the Schottky region contact areas17dand the contact region contact areas17eare formed alternately in a direction going from the end on the built-in transistor820ijside towards the center of the device.

As illustrated by the second floating electrode9b1inFIG. 35(which has been vertically inverted relative to the state illustrated inFIG. 32), the second floating electrodes9b1and9b2have a plate shape that is rectangular when viewed in a plan view and includes a recess surrounded by sidewalls that are extruded up from the four sides of the rectangle. A protrusion is formed in the center of the recess and separated from the peripheral sidewalls. The protrusion has a rectangular shape when viewed in a plan view, and a surface91of the protrusion (the hatched upper surface inFIG. 35) contacts the third ohmic contact layer12b1.

Meanwhile, the peripheral sidewalls have a frame shape when viewed in a plan view, and a surface92of the sidewalls (the hatched upper surface inFIG. 35) contacts the second potential barrier layer13b1. The rest of the components of the structure of the semiconductor device according to Embodiment 6 are the same as the corresponding layers, regions, and the like of the semiconductor devices according to Embodiments 1 to 5, and therefore a redundant description will be omitted here.

To switch device to the ON state (that is, to make the electric potential of a drain electrode10higher than the electric potential of the source electrode9), a voltage of greater than or equal to the gate threshold voltage Vth is applied to the first gate electrodes8, thereby causing an inversion layer to be formed in the surface of the channel region3that is directly beneath the first gate electrodes8. Current then flows through a path that includes the drain electrode10, the drain region1, the drift layer2, a JFET region2b1illustrated on the left side inFIG. 34, the inverted region2a1, the inversion layer in the surface of the channel region3, the first source region5, the first ohmic contact layer12, and the source electrode9.

Current also flows through a path that includes the drain electrode10, the drain region1, the drift layer2, a JFET region2b2illustrated on the right side inFIG. 34, the inverted region2a2, the inversion layer in the surface of the channel region3, the first source region5, the first ohmic contact layer12, and the source electrode9.

At this time, the voltage greater than or equal to the gate threshold voltage Vth is also applied to the second gate electrode8aof the built-in transistor820ij. The base region4and the channel region3are connected to the source electrode9via the base contact region6aof the built-in transistor820ij, the second source region5b, the inversion layer in the surface of the channel region3directly beneath the second gate electrode8a, the second drain region5a, and the first source region5. Therefore, the channel region3(that is, the back gate of the standard unit810ij) takes substantially the same electric potential as the source electrode9, and the device functions the same as a normal vertical MOSFET.

Meanwhile, when the first gate electrodes8are set to an electric potential less than the gate threshold voltage Vth in order to switch the device OFF, the inversion layer in the surface of the channel region3disappears, and current stops flowing through the standard unit810ij. Here, the electric potential of the drain electrode is increased by the supply voltage, and the p-n junctions between the n-type regions such as the inverted regions2a1and2a2and the JFET regions2b1and2b2and the p-type regions such as the base region4and the channel region3become reverse-biased, thereby resulting in the formation of depletion layers and maintaining the breakdown voltage.

In order for the depletion layers to be formed, current must flow from the base region4and the channel region3to the source electrode9side. Here, in the Schottky region contact area17d, the Schottky diodes formed by the second potential barrier layers13b1and13b2(which are made of a Schottky metal) and the inverted regions2a4and2a5become biased in the forward direction. As a result, in the Schottky region contact area17d, current flows from the base region4and the channel region3through a path that includes the base contact regions6b1and6b2, the third ohmic contact layers12b1and12b2, the second floating electrodes9b1and9b2, the second potential barrier layers13b1and13b2, the inverted regions2a4and2a5, and the first source region5.

Furthermore, in the source contact area17a, the current that has flowed to the first source region5then continues to flow from the first source region5through a path that includes the first ohmic contact layer12and the source electrode9. A current that flows through this same path also flows when holes are generated in the drift layer2due to avalanche breakdown when the device is isolated using an inductance load or the like, thereby making it possible to prevent occurrence of the parasitic bipolar transistor effect.

As the device is repeatedly switched ON and OFF as described above, the base region4and the channel region3become negatively biased relative to the source electrode9due to the charge pumping effect. However, because the Schottky diodes formed by the second potential barrier layers13b1and13b2and the inverted regions2a4and2a5become reverse-biased, holes cannot be supplied to the base region4and the channel region3through the Schottky junctions. Therefore, the base region4and the channel region3remain negatively biased.

However, even when the base region4and the channel region3are negatively biased while the device is in the OFF state, the built-in transistor820ijwill still be switched ON when the device is switched ON. Therefore, holes are supplied to the base region4and the channel region3through the built-in transistor820ijas well, thereby making it possible to give the base region4and the channel region3substantially the same electric potential as the source electrode9. This prevents an increase in the on-resistance due to an increase in the gate threshold voltage Vth or an increase in the JFET effect.

Moreover, even when the base region4and the channel region3become negatively biased in the OFF state, the gate threshold voltage Vth increases, which has advantages such as reducing channel leaks, promoting pinch-off of the JFET regions2b1and2b2due to the JFET effect, and improving the breakdown voltage, all without causing any associated disadvantages.

Next, the operation of the bridge circuit illustrated inFIG. 8while the current Ibis flowing will be described for a case in which the semiconductor device according to Embodiment 6 is applied to the MOSFETs20ato20d. When the current Ibis flowing, the electric potential of the drain electrode10is more negative than the electric potential of the source electrode9.

Here, recall that when using Comparison Example 1 as illustrated inFIG. 7, when the on-voltage of the diode21c(a Schottky diode) that is connected in parallel to the MOSFET20cexceeds the built-in voltage of the body diode of the MOSFET20c, holes from the base region4and the channel region3are injected into the drift layer2and cause deterioration due to growth of stacking faults.

However, when using the semiconductor device according to Embodiment 6, the Schottky diodes formed by the second potential barrier layers13b1and13b2and the inverted regions2a4and2a5become reverse-biased, and therefore holes are not supplied from the source electrode9to the base region4and the channel region3. Therefore, even during periods of dead time in which the MOSFET20aand the MOSFET20care both OFF, deterioration does not occur due to hole injection. However, the inductance of the load inductor24creates a large voltage while current is not flowing, and therefore the diode21c(a Schottky diode) remains necessary even if this diode only has a small area.

Furthermore, when the MOSFET20cis switched ON after the dead time, the built-in transistor820ijis switched ON at the same time, thereby making it possible to supply holes to the base region4and the channel region3via the built-in transistor820ij. However, because the MOSFET20cis in the ON state, the channel of the MOSFET20cshort-circuits the body diode of the MOSFET20c, and therefore current does not flow through the body diode.

An equivalent circuit diagram for the semiconductor device according to Embodiment 6 can be represented using the same equivalent circuit diagram illustrated inFIG. 6for the semiconductor device according to Embodiment 1. InFIG. 6, the parasitic body diode121corresponds to a parasitic body diode in the built-in transistor820ijof the semiconductor device according to Embodiment 6.

The p-type Schottky diode130inFIG. 6corresponds to the Schottky diodes formed by the second potential barrier layers13b1and13b2and the inverted regions2a4and2a5in the semiconductor device according to Embodiment 6. The parasitic junction capacitor140inFIG. 6corresponds to parasitic junction capacitance that includes the junction capacitance of the built-in transistor820ijand the Schottky diodes in the semiconductor device according to Embodiment 6.

The semiconductor device according to Embodiment 6 includes the built-in transistor820ij, similar to the semiconductor device according to Embodiment 1. This makes it possible to prevent increases in the gate threshold voltage Vth or the JFET effect resulting from the charge pumping effect that occurs due to the trapping levels at the gate oxide film and channel region interfaces, thereby making it possible to prevent increases in the on-voltage.

Moreover, in the semiconductor device according to Embodiment 6, a plurality of n-type Schottky diodes are connected in series in order to achieve satisfactory Schottky properties between the p-type body region (3,4) and the source electrode9. Therefore, even when relatively small-area diodes with a high forward voltage are connected in parallel to the semiconductor device, holes are not continuously injected into the body region, and a current does not flow through the body diode of the semiconductor device. This prevents growth of stacking faults due to recombination, thereby making it possible to effectively solve the problem of deterioration in on-resistance. The rest of the effects of the semiconductor device according to Embodiment 6 are the same as in the semiconductor device according to Embodiment 1.

A semiconductor device according to Embodiment 7 is different than Embodiment 6 in that this semiconductor device has the same structure as in Embodiment 4, in which n-type Schottky cells . . . ,6001j−1,6001j,6001j+1, . . . and . . . ,6002j−1,6002j,6002j+1, . . . are formed in the active portion and connected in parallel to the semiconductor device.

In other words, in the semiconductor device according to Embodiment 7, these n-type Schottky cells600ijare embedded in the active portion and interspersed among the basic cells800ijdescribed in Embodiment 6. Therefore, a plan view of the semiconductor device according to Embodiment 7 can be the same as the plan view of the semiconductor device illustrated inFIG. 24except in that the basic cells100ijare replaced by the basic cells800ij. Similarly, the upper surfaces of the n-type Schottky cells600ijof the semiconductor device according to Embodiment 7 can be illustrated the same as in the n-type Schottky cell600ijas illustrated inFIG. 25.

Similar to the semiconductor device according to Embodiment 6 as illustrated inFIG. 33, the semiconductor device according to Embodiment 7 includes the basic cell800ijthat includes one or more standard units810ijand one or more built-in transistors820ij. The standard unit810ijis a region through which a primary current flows, and the built-in transistor820ijis connected to the standard unit810ijin order to be able to form a short-circuit between an SiC body region (3,4) and a source region of the standard unit810ij.

The basic cells800ijof the semiconductor device according to Embodiment 7 include a high concentration n-type (n+) first drain region1that is made primarily of SiC and is formed spanning across the respective standard units810ijand the respective built-in transistors820ij. Furthermore, the basic cell800ijof the semiconductor device according to Embodiment 7 includes an n-type drift layer2that is formed on the first drain region1and has a lower impurity concentration than the first drain region1, as well as a high concentration p-type (p+) base region4that is formed on the drift layer2.

The basic cell800ijof the semiconductor device according to Embodiment 7 also includes a p-type channel region3that is formed on a portion of the upper surface of the base region4and has a lower impurity concentration than the base region4. In addition, the basic cell800ijof the semiconductor device according to Embodiment 7 includes a high concentration n-type (n+) first source region5formed in a portion of the upper surface of the channel region3of the standard unit810ijand running parallel to the lengthwise direction of the stripe shape of the basic cell800ij.

Moreover, a first ohmic contact layer12is formed on the first source region5between adjacent openings therein. In addition, a source electrode9is formed on an interlayer insulating film11and on the first ohmic contact layer12. The basic cell800ijof the semiconductor device according to Embodiment 7 also includes a second drain region5aof a first conductivity type that is formed in a portion of the upper surface of the channel region3in the built-in transistor820ijregion and that is electrically connected to the first source region5.

The second drain region5ais formed as an integrated part of the first source region5. Furthermore, the basic cell800ijof the semiconductor device according to Embodiment 7 also includes a high concentration n-type (n+) second source region5bthat is formed in a portion of the upper surface of the channel region3in the built-in transistor820ijregion and that is separated from the second drain region5a.

The semiconductor device according to Embodiment 7 also includes n-type inverted regions2a4and2a5that are formed in a region of the channel region3that is surrounded by the first source region5. The semiconductor device according to Embodiment 7 also includes high concentration p-type (p+) base contact regions6b1and6b2that are formed in the inverted regions2a4and2a5.

Moreover, the semiconductor device according to Embodiment 7 includes second potential barrier layers13b1and13b2that contact the inverted regions2a4and2a5as well as third ohmic contact layers12b1and12b2that contact the base contact regions6b1and6b2. Second floating electrodes9b1and9b2are respectively connected to the second potential barrier layers13b1and13b2and to the third ohmic contact layers12b1and12b2in the regions surrounded by the first source region. The rest of the components of the structure of the semiconductor device according to Embodiment 7 are the same as the corresponding layers, regions, and the like of the semiconductor devices according to Embodiments 1 to 6, and therefore a redundant description will be omitted here.

FIG. 36is an equivalent circuit diagram of the semiconductor device according to Embodiment 7 and includes a MOSFET that represents the standard unit810ijand a MOSFET that represents the built-in transistor820ijthat is connected between the channel region3and the source electrode9(that is, to the back gate of the former MOSFET).

Moreover, a parasitic body diode821of the built-in transistor820ijand a p-type Schottky diode830formed between the channel region3and the second potential barrier layers13b1and13b2are represented as being connected in parallel to the built-in transistor820ij. Similarly, a parasitic junction capacitor840that represents the sum of the junction capacitance of the built-in transistor820ij, the p-type Schottky diode830, and the like is also represented as being connected in parallel to the built-in transistor820ij. Furthermore, a Schottky diode formed by the n-type Schottky cells600ijis connected in parallel between the source and the drain.

Similar to the semiconductor device according to Embodiment 4, the semiconductor device according to Embodiment 7 makes it possible to form Schottky barrier diodes on the same chip without increasing the number of manufacturing steps, thereby removing the need for die bonding components or wire bonding processes for connecting external Schottky diodes. The rest of the effects of the semiconductor device according to Embodiment 7 (that is, the effects other than those due to the inclusion of the n-type Schottky cells600ij) are the same as the effects of the semiconductor device according to Embodiment 6.

A semiconductor device according to Embodiment 8 is different from Embodiment 6 in that as illustrated inFIG. 37, this semiconductor device has a trench-gate structure in which trenches18a1and18b1are formed in inverted regions2a1and2a2and in portions of a channel region3that contacts the inverted regions2a1and2a2.

Similar to the semiconductor device according to Embodiment 6 as illustrated inFIG. 33, the semiconductor device according to Embodiment 8 includes a basic cell900ijthat includes one or more standard units910ijand one or more built-in transistors920ij. The standard unit910ijis a region through which a primary current flows, and the built-in transistor920ijis connected to the standard unit910ijin order to be able to form a short-circuit between an SiC body region (3,4) and a source region of the standard unit910ij.

The basic cell900ijof the semiconductor device according to Embodiment 8 includes a high concentration n-type (n+) first drain region1that is made primarily of SiC and is formed spanning across the standard unit910ijand the built-in transistor820ij. Furthermore, the basic cell900ijof the semiconductor device according to Embodiment 8 includes an n-type drift layer2that is formed on the first drain region1and has a lower impurity concentration than the first drain region1, as well as a high concentration p-type (p+) base region4that is formed on the drift layer2.

The basic cell900ijof the semiconductor device according to Embodiment 8 also includes a p-type channel region3that is formed on a portion of the upper surface of the base region4and has a lower impurity concentration than the base region4. In addition, the basic cell900ijof the semiconductor device according to Embodiment 8 includes a high concentration n-type (n+) first source region5formed in a portion of the upper surface of the channel region3of the standard unit910ijand running parallel to the lengthwise direction of the stripe shape of the basic cell900ij.

Moreover, a first ohmic contact layer12is formed on the first source region5between adjacent openings therein. In addition, a source electrode9is formed on an interlayer insulating film11and on the first ohmic contact layer12. The basic cell900ijof the semiconductor device according to Embodiment 8 also includes a second drain region5aof a first conductivity type that is formed in a portion of the upper surface of the channel region3in the built-in transistor920ijregion and that is electrically connected to the first source region5.

The second drain region5ais formed as an integrated part of the first source region5. Furthermore, the basic cell900ijof the semiconductor device according to Embodiment 8 also includes a high concentration n-type (n+) second source region5bthat is formed in a portion of the upper surface of the channel region3in the built-in transistor920ijregion and that is separated from the second drain region5a.

The semiconductor device according to Embodiment 8 also includes n-type inverted regions2a4and2a5that are formed in a region of the channel region3that is surrounded by the first source region5. In addition, the semiconductor device according to Embodiment 8 includes high concentration p-type (p+) base contact regions6b1and6b2that are formed in the inverted regions2a4and2a5.

Moreover, the semiconductor device according to Embodiment 8 includes second potential barrier layers13b1and13b2that contact the inverted regions2a4and2a5as well as third ohmic contact layers12b1and12b2that contact the base contact regions6b1and6b2. Second floating electrodes9b1and9b2are respectively connected to the second potential barrier layers13b1and13b2and to the third ohmic contact layers12b1and12b2in the regions surrounded by the first source region.

As illustrated inFIG. 38, the base contact regions6b1and6b2are formed on a base region4b. Moreover, the cross-sectional structure of the basic cell900ijof the semiconductor device according to Embodiment 8 at the position of a source contact area17a(that is, the structure as taken along a line corresponding to line M-M inFIG. 28) is the same as the cross-sectional structure of the basic cell700ijof the semiconductor device according to Embodiment 5 as illustrated inFIG. 30.

As illustrated inFIG. 37, the trenches18a1and18b1are kept within the standard unit910ijon the built-in transistor920ijside thereof and do not extend into the region on the built-in transistor920ijside.

It is preferable that a second gate electrode of the built-in transistor920ijbe formed on a surface of the SiC body region similar to the second gate electrode8aof the built-in transistor820ijillustrated inFIG. 32. This is because this configuration makes it possible to avoid the decrease in the channel width of the built-in transistor920ijthat would result from forming the second gate electrode by extending first gate electrodes8a1and8b1of the standard unit910ijtowards the built-in transistor920ijside, as described above in Embodiment 5. The rest of the components of the structure of the semiconductor device according to Embodiment 8 are the same as the corresponding layers, regions, and the like of the semiconductor devices according to Embodiments 1 to 7, and therefore a redundant description will be omitted here.

Moreover, the rest of the effects of the semiconductor device according to Embodiment 8 (that is, the effects other than those due to having a trench structure) are the same as the effects of the semiconductor device according to Embodiment 6.

The present invention was described with reference to Embodiments 1 to 8 as described above. However, none of the descriptions or drawings of this disclosure should be understood to limit the present invention in any way. It should instead be understood that various alternative embodiments, other embodiments, and applied technologies based on this disclosure are obvious to a person skilled in the art.

For example, in all of Embodiments 1 to 8 as described above, potential barriers formed by n-type Schottky junctions were used to prevent hole injection. However, hole injection may instead be prevented using potential barriers formed by heterojunctions. Alternatively, even when polycrystalline silicon (doped polysilicon) layers are used as the potential barrier layers, these layers have a functionality equivalent to that of Schottky junctions and therefore still make it possible to prevent hole injection.

Furthermore, aspects of the configurations of Embodiments 1 to 8 may be combined to form new configurations of the present invention. As described above, the present invention includes various other embodiments and the like that are not explicitly described above. In addition, the technical scope of the present invention is defined only by the characterizing features of the invention as disclosed in claims derived appropriately from the descriptions above.

INDUSTRIAL APPLICABILITY

The present invention is suitable for application to power semiconductor devices made using wide-bandgap materials and intended for use in inverters, switching power supplies, or the like, and is particularly suitable for application to SiC semiconductor devices.