Semiconductor Device Comprising Electrostatic Discharge Protection Structure

A semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further comprises a first isolation layer on the first surface of the semiconductor body, and an electrostatic discharge protection structure on the first isolation layer. The electrostatic discharge protection structure includes a first terminal and a second terminal. The semiconductor device further comprises a heat dissipation structure having a first end in direct contact with the electrostatic discharge protection structure and a second end in direct contact with an electrically isolating region. The electrostatic discharge protection structure comprises first and second outdiffusion regions of the same conductivity type being self-aligned to the heat dissipation structure and further comprising a net dopant profile declining with increasing distance from the heat dissipation structure in a lateral direction between the first terminal and the second terminal.

BACKGROUND

A key component in semiconductor applications is a solid-state switch. As an example, switches turn loads of automotive applications or industrial applications on and off. Solid-state switches typically include, for example, field effect transistors (FETs) like metal-oxide-semiconductor FETs (MOSFETs) or insulated gate bipolar transistors (IGBTs).

In these applications, a damage of a gate dielectric between gate and source of the transistors may be caused by an electrostatic discharge event between a gate contact area and a source contact area of the semiconductor device. To protect the gate dielectric from an electrostatic discharge event, electrostatic discharge (ESD) protection structures are provided, which protect the transistors from electrostatic discharge during assembly or operation, for example. These ESD protection structures require non-negligible area within the integrated semiconductor device.

It is further beneficial to increase the thermoelectric safe operating area of an ESD structure to achieve a predetermined electrostatic discharge robustness while having at the same time a reduced area consumption of the ESD protection structure.

It is thus desirable to provide a semiconductor device structure with enhanced ESD protection and thermal characteristics, having at the same time an optimized area efficiency.

SUMMARY

According to an embodiment of a semiconductor device, the semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further comprises a first isolation layer on the first surface of the semiconductor body, and an electrostatic discharge protection structure on the first isolation layer. The electrostatic discharge protection structure includes a first terminal and a second terminal. The semiconductor device further comprises a heat dissipation structure having a first end in direct contact with the electrostatic discharge protection structure and a second end in direct contact with an electrically isolating region. The electrostatic discharge protection structure comprises first and second outdiffusion regions of the same conductivity type being self-aligned to the heat dissipation structure and further comprising a net dopant profile declining with increasing distance from the heat dissipation structure in a lateral direction between the first terminal and the second terminal.

According to an embodiment of a method of manufacturing a semiconductor device, the method comprises forming a first isolation layer on a semiconductor body. A polysilicon layer of a first conductivity type is formed on the first isolation layer. A second isolation layer is formed on the polysilicon layer. A trench penetrating the second isolation layer and the polysilicon layer is formed. A heat dissipation structure is formed in the trench. First and second outdiffusion regions of a second conductivity type are formed in the polysilicon layer to form an electrostatic discharge protection structure.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustrations specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the scope of the present invention. For example features illustrated or described for one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention include such modifications and variations. The examples are described using specific language, which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and for illustrative purpose only. For clarity, corresponding elements have been designated by the same references in the different drawings if not stated otherwise.

The terms “having”, “containing”, “including”, “comprising” and the like are open and the terms indicate the presence of stated structures, elements or features but not preclude additional elements or features.

The terms “one after another”, “successively” and the like indicate a loose ordering of elements not precluding additional elements placed in between the ordered elements.

The articles “a”, “an”, and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

In this specification, n-type or n-doped may refer to a first conductivity type while p-type or p-doped is referred to a second conductivity type. Semiconductor devices can be formed with opposite doping relations so that the first conductivity type can be p-doped and the second conductivity type can be n-doped. Furthermore, some figures illustrate relative doping concentrations by indicating “−” or “+” next to the doping type. For example, “n−” means a doping concentration less than the doping concentration of an “n”-doping region while an “n+”-doping region has a larger doping concentration than the “n”-doping region. Indicating the relative doping concentration does not, however, mean that doping regions of the same relative doping concentration have the same absolute doping concentration unless otherwise stated. For example, two different n+regions can have different absolute doping concentrations. The same applies, for example, to an n+and a p+region.

The first conductivity type may be n- or p-type provided that the second conductivity type is complementary.

The term “electrically connected” describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via a metal and/or highly doped semiconductor.

The terms “wafer”, “substrate”, “semiconductor body” or “semiconductor substrate” used in the following description may include any semiconductor-based structure that has a semiconductor surface. Wafer and structure are to be understood to include silicon (Si), silicon-on-insulator (SOI), silicon-on sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. The semiconductor need not be silicon-based. The semiconductor could as well be silicon germanium (SiGe), germanium (Ge) or gallium arsenide (GaAs). According to other embodiments, silicon carbide (SiC) or gallium nitride (GaN) may form the semiconductor substrate material.

The term “horizontal” as used in this specification intends to describe an orientation substantially parallel to a first or main surface of a semiconductor substrate or body. This can be for instance the surface of a wafer or a die.

The term “vertical” as used in this specification intends to describe an orientation which is substantially arranged perpendicular to the first surface, i.e. parallel to the normal direction of the first surface of the semiconductor substrate or body.

Processing of a semiconductor wafer may result in semiconductor devices having terminal contacts such as contact pads (or electrodes) which allow electrical contact to be made with the integrated circuits or discrete semiconductor devices included in the semiconductor body. The electrodes may include one or more electrode metal layers which are applied to the semiconductor material of the semiconductor chips. The electrode metal layers may be manufactured with any desired geometric shape and any desired material composition. The electrode metal layers may, for example, be in the form of a layer covering an area. Any desired metal, for example Cu, Ni, Sn, Au, Ag, Pt, Pd, and an alloy of one or more of these metals may be used as the material. The electrode metal layer(s) need not be homogenous or manufactured from just one material, that is to say various compositions and concentrations of the materials contained in the electrode metal layer(s) are possible. As an example, the electrode layers may be dimensioned large enough to be bonded with a wire.

In embodiments disclosed herein one or more conductive layers, in particular electrically conductive layers, are applied. It should be appreciated that any such terms as “formed” or “applied” are meant to cover literally all kinds and techniques of applying layers. In particular, they are meant to cover techniques in which layers are applied at once as a whole like, for example, laminating techniques as well as techniques in which layers are deposited in a sequential manner like, for example, sputtering, plating, molding, CVD (Chemical Vapor Deposition), physical vapor deposition (PVD), evaporation, hybrid physical-chemical vapor deposition (HPCVD), etc.

The applied conductive layer may comprise, inter alia, one or more of a layer of metal such as Cu or Sn or an alloy thereof, a layer of a conductive paste and a layer of a bond material. The layer of a metal may be a homogeneous layer. The conductive paste may include metal particles distributed in a vaporizable or curable polymer material, wherein the paste may be fluid, viscous or waxy. The bond material may be applied to electrically and mechanically connect the semiconductor chip, e.g., to a carrier or, e.g., to a contact clip. A soft solder material or, in particular, a solder material capable of forming diffusion solder bonds may be used, for example solder material comprising one or more of Sn, SnAg, SnAu, SnCu, In, InAg, InCu and InAu.

A dicing process may be used to divide the semiconductor wafer into individual chips. Any technique for dicing may be applied, e.g., blade dicing (sawing), laser dicing, etching, etc. The semiconductor body, for example a semiconductor wafer may be diced by applying the semiconductor wafer on a tape, in particular a dicing tape, apply the dicing pattern, in particular a rectangular pattern, to the semiconductor wafer, e.g., according to one or more of the above mentioned techniques, and pull the tape, e.g., along four orthogonal directions in the plane of the tape. By pulling the tape, the semiconductor wafer gets divided into a plurality of semiconductor dies (chips).

FIG. 1is a schematic cross-sectional view of a portion of a semiconductor device10in accordance with an embodiment. The semiconductor device10comprises a semiconductor body100having a first surface101and a second surface102opposite to the first surface101. The semiconductor device10further comprises a first isolation layer200on the first surface101of the semiconductor body100and an electrostatic discharge protection structure310on the first isolation layer200. The electrostatic discharge protection structure310includes a first terminal312and a second terminal314. The semiconductor device10further comprises a heat dissipation structure700, which has a first end701in direct contact with the electrostatic discharge protection structure310and a second end702, which is in direct contact with an electrically isolating region.

The electrostatic discharge protection structure310comprises a first outdiffusion region320and a second outdiffusion region322of the same conductivity type. The first and second outdiffusion regions320,322are self-aligned to the heat dissipation structure700. The first and second outdiffusion regions320,322further comprise a net dopant profile declining with increasing distance from the heat dissipation structure700in a lateral direction x between the first terminal312and the second terminal314.

Due to the structure of the semiconductor device10, a well-defined dopant profile within the electrostatic discharge protection structure310may be achieved, which is furthermore centered with regard to the heat dissipation structure700. Thus, both good heat dissipation characteristics and well-defined electric characteristics of the electrostatic discharge protection structure310can be achieved. Lithographic misalignment when placing the heat dissipation structure700on the electrostatic discharge protection structure310can thus be avoided or counteracted.

The semiconductor device10may comprise power semiconductor elements such as IGBTs (insulated gate bipolar transistors), e.g. RC-IGBTs (reverse-conducting IGBTs), RB-IGBT (reverse-blocking IGBTs, and IGFETs (insulated gate field effect transistors) including MOSFETs (metal oxide semiconductor field effect transistors). The semiconductor device10may also comprise a superjunction transistor, a trench field effect transistor, or any further transistor device controlling a load current via a control terminal.

When reducing the chip size of the semiconductor device10, a smaller input capacitance results in an enhanced risk of damage caused by an electrostatic discharge event between the gate and the source of the semiconductor device10. Thus, the electrostatic discharge protection structure310may be applied in a power semiconductor element to protect a gate dielectric between a gate and source of a transistor from damage by dissipating energy caused by an electrostatic discharge event between a gate contact area and a source contact area.

FIGS. 2A and 2Bare schematic plan views of portions of a semiconductor device10in accordance with different embodiments. As shown inFIG. 2A, a first electrode500is provided in a corner portion of the semiconductor device10and may act as a gate contact area510(cf.FIG. 8), which may include a gate pad. The gate pad may be used for providing a bonding or soldering contact to the first electrode500to be connected to an external device or element. A second electrode600is arranged next to the first electrode500and may act as a source contact area610(cf.FIG. 8), by which source zones150of transistor cells20in the semiconductor body100are contacted.

When forming the semiconductor device10as a power semiconductor element, a resulting thickness of the metallization of the first electrode500and the second electrode600may be in a range of 1 μm to 10 μm or 3 μm to 7 μm, and the first electrode500and the second electrode600may be separated by a minimum distance B in a range of 5 μm to 20 μm or 10 μm to 15 μm. As shown inFIG. 2B, the first electrode500may be also be arranged in a middle part of the semiconductor device10, wherein the second electrode600surrounds the first electrode500. Possible locations of the electrostatic discharge protection structure310are indicated by dashed lines, wherein the indicated places are only exemplary and should not be understood as limiting.

FIG. 3is a schematic cross-sectional view of a portion of the semiconductor device10taken along a section plane A-A′ ofFIG. 2AorFIG. 2Bin accordance with an embodiment.

The semiconductor body100may be provided from a single-crystalline semiconductor material, for example silicon Si, silicon carbide SiC, germanium Ge, a silicon germanium crystal SiGe, gallium nitride GaN or gallium arsenide GaAs. A distance between the first and second surfaces101,102is selected to achieve a specified voltage blocking capability and may be at least 20 μm, for example at least 50 μm. Other embodiments may provide semiconductor bodies100with a thickness of several 100 μm. The semiconductor body100may have a rectangular shape with an edge length in the range of several millimeters.

The normal to the first and second surfaces101,102defines a vertical direction z and directions orthogonal to the normal direction are lateral directions. As can be seen, for example, fromFIG. 2AandFIG. 2B, the lateral direction x is defined to be extended between the first terminal312and the second terminal314. Thus, the lateral direction x is effectively parallel to the direction of a breakdown current within the electrostatic discharge protection structure310. For the sake of an unambiguous understanding of the invention, the lateral direction x may be defined to be extended along the section plane A-A′ ofFIG. 2AorFIG. 2B. However, it can easily understood by a person skilled in the art that within a electrostatic discharge protection structure310′ as shown inFIG. 2A, the lateral direction x has to be defined as a direction being orthogonal to the above-defined lateral direction x. Furthermore, as can be seen fromFIG. 8, the lateral direction x may be extended even in opposite directions.

The first isolation layer200is formed on the first surface101of the semiconductor body100. The first isolation layer200may include any dielectric or a combination of dielectrics adapted to isolate the semiconductor body100from the electrostatic discharge protection structure310on the first isolation layer200. The first isolation layer200may include one or any combination of an oxide, nitride, oxynitride, a high-k material, an imide, an insulating resin or glass, for example. The first isolation layer200may include a field dielectric such as a field oxide and/or a gate dielectric such as a gate oxide. The first isolation layer200may include a field oxide formed e.g. by a local oxidation of silicon (LOCOS) process, deposited oxide or STI (shallow trench isolation). The thickness of the field dielectric of the first isolation layer200may be in a range of 0.5 μm to 5 μm or 1 μm to 3 μm, the thickness of the gate dielectric of the first isolation layer200may be in a range of 5 nm to 200 nm or 40 nm to 120 nm.

The second isolation layer400is formed on the electrostatic discharge protection structure310and the first isolation layer200. The second isolation layer may comprise silicon nitride. The second isolation layer400may comprise a stack of a first and a second dielectric layers410and420. According to an embodiment, the first dielectric layer410may include a tetraethyl orthosilicate (TEOS)/undoped silicate glass (USG) film. The thickness of the first dielectric layer of the second isolation layer400may be in a range of 50 nm to 500 nm. The second dielectric layer420may include a phosphosilicate glass (PSG) or a borophosphosilicate glass (BPSG). The thickness of the second dielectric layer of the second isolation layer400may be in a range of 200 nm to 2 μm.

The first electrode500is formed on the second isolation layer400. Next to the first electrode500, the second electrode600is formed on the second isolation layer400, which may be spaced apart from the first electrode500by the distance B (cf. alsoFIG. 2AandFIG. 2B). On the first electrode500and the second electrode600, a passivation layer1000is formed, which may include one or any combination of an imide, a nitride, an oxide or an oxynitride, for example.

The first electrode500and the second electrode600may be separate parts, e.g. due to lithographic patterning of a common metal wiring layer, wherein the semiconductor device10comprises only a single metal wiring layer. The first electrode500and the second electrode600may be formed as a metal layer structure, which may consist of or contain, as main constituent(s), aluminum Al, copper Cu or alloys of aluminum or copper, for example AlSi, AlCu, or AlSiCu. According to other embodiments, the first electrode500and the second electrode600may contain one, two, three or more sub-layers, each sub-layer containing, as a main constituent, at least one of nickel Ni, titanium Ti, silver Ag, gold Au, tungsten W, platinum Pt, tantalum Ta and palladium Pd. For example, a sub-layer may contain a metal nitride or a metal alloy containing Ni, Ti, Ag, Au, W, Pt, Co and/or Pd.

The electrostatic discharge protection structure310may include a series connection of at least one polysilicon diode. As shown inFIG. 3, the electrostatic discharge protection structure310may comprise a polysilicon layer300on the first isolation layer200having first regions316and at least one second region318of opposite conductivity type alternatingly arranged along the lateral direction x. The second region318comprises the first and second outdiffusion regions320,322. According to the embodiment as shown inFIG. 3, the first terminal312and the second terminal314within the polysilicon layer300may have the same conductivity type as the second region318. The first regions316and the first and second outdiffusion regions320,322may comprise first dopants of a first conductivity type, and the first and second outdiffusion regions320,322may further comprise second dopants of the second conductivity type overcompensating the first dopants.

As will be described in more detail below, the electrostatic discharge protection structure310may be manufactured by forming trenches penetrating the polysilicon layer300of a first conductivity type, and forming the first and second outdiffusion regions320,322of a second conductivity type in the polysilicon layer300to form alternatingly arranged first regions316of the first conductivity type and second regions318of the second conductivity type. The trenches therefore may be filled with a conductive material or a highly doped polysilicon material.

As can be seen fromFIG. 3and in more detail inFIG. 4, the electrostatic discharge protection structure310may further comprise an intermediate region324. The intermediate region324may be sandwiched between the first and second outdiffusion regions320,322in the lateral direction x. The intermediate region324may be further sandwiched between the first isolation layer200and the first end701of the heat dissipation structure700in the vertical direction z.

The second region318may comprise the first outdiffusion region320, the intermediate region324and the second outdiffusion region322consecutively arranged in this order along the lateral direction x. The intermediate region324and the heat dissipation structure700may include a same material. According to an embodiment, the intermediate region324may comprise n-doped polysilicon having a net dopant concentration higher than 1×1017cm−3, or higher than 1×1018cm−3, or higher than 1×1019cm−3, or higher than 5×1019cm−3, or higher than 2×1020cm−3. According to another embodiment, the intermediate region324may comprise a metal. Basically the electrostatic discharge protection function of the electrostatic discharge protection structure310may also be provided by employing an intermediate region324comprising n-doped polysilicon having a net dopant concentration lower than 1×1016cm−3. A lower net dopant concentration, however, may lead to an enhancement of the differential path resistance and a breakdown voltage of the electrostatic discharge protection structure310. However, the benefit of a self-aligned ESD protection structure will be preserved.

As a result, a polysilicon diode chain or string arranged in a lateral direction having alternating pn-junctions (diodes) at the region boundaries of the first and second regions316,318in the polysilicon layer300is formed. In an embodiment, the doping concentrations of the regions are adapted such that series connections of Zener diodes are formed within the polysilicon layer300. By the number of consecutive diodes each including a first region316and a second region318, the breakdown voltage of the electrostatic discharge protection structure310can be adjusted.

The polysilicon layer300deposited on the first isolation layer200may have a large grain-size of polysilicon. Thus, the lateral dimension of the electrostatic discharge protection structure310comprising a poly Zener diode chain may be e.g. in a range of 1 μm to 10 μm or 3 μm to 5 μm. By extending the electrostatic discharge protection structure310over a plurality of grain boundaries of the polysilicon layer300, a stable breakdown characteristic of the electrostatic discharge protection structure310is provided. In some embodiments, a plurality of grain boundaries within the polysilicon layer300may lead to an electron mobility in a range of 1 cm2/Vs to 5 cm2/Vs. In case of improving the granular structure of the polysilicon layer300, the electron mobility may be increased to 50 cm2/Vs due to less grain boundaries within the polysilicon layer300. A further improvement may be achieved by depositing amorphous silicon followed by a laser melting process. Such a polycrystalline silicon is called low temperature polysilicon (LTPS). The electron mobility of low temperature polysilicon is in a range of 100 cm2/Vs to 700 cm2/Vs.

Even higher electron mobility values may be achieved by polycrystalline silicon having even greater grain-boundary sizes. An example of such a polycrystalline silicon is a continuous-grain-silicon (CGS), which leads to an electron mobility in a range of 500 cm2/Vs to 700 cm2/Vs. By provision of a continuous grain silicon within the polysilicon layer300, electron mobility values may be achieved, which are comparable to that within the bulk region of the semiconductor body100.

The polysilicon layer300may thus comprise at least one of a low temperature polysilicon (LTPS) and a continuous grain silicon (SGS).

The length of the electrostatic discharge protection structure310between the first terminal312and the second terminal314, respectively, may be in a range of 5 μm to 150 μm or 20 μm to 50 μm. An area of the electrostatic discharge protection structure310according toFIGS. 2A and 2BorFIGS. 3 and 8may be in a range of 100 μm×50 μm×2=10000 μm2, by providing a small gate pad length of 100 μm, an electrostatic discharge protection structure310on two orthogonal sides (FIG. 2A) or symmetrical on two opposite sides (FIG. 2B) of the gate pad. The area of the electrostatic discharge protection structure310may be up to 500 μm×50 μm×2=50000 μm2or up to 2000 μm×50 μm×2=200.000 μm2, by providing a large gate pad length of 1000 μm. The area of the electrostatic discharge protection structure310does not increase the total chip area, because the diode is constructed between and partially beneath the metal.

An electrostatic discharge protection structure310having a diode width in a range between 1000 μm to 2000 μm may be integrated along the gate contact area510or furthermore within an edge termination structure of the semiconductor device10, wherein the semiconductor device10may be a superjunction metal oxide semiconductor field effect transistor device or an insulated gate bipolar transistor (IGBT) device. Such an embodiment may be advantageous in case of providing a semiconductor device10having a small die area (smaller than 1 mm2), wherein a robustness of the electrostatic discharge protection structure310with respect to HBM (Human Body Model) tests may be in a range of 1 kV to 4 kV. Assuming a breakdown current of 1 mA per μm diode width, a robustness of the electrostatic discharge protection structure310with respect to HBM (Human Body Model) tests may be in a range of 300 V to 4 kV.

The area of the electrostatic discharge protection structure310may be appropriately chosen for dissipating energy caused by an electrostatic discharge event (ESD event) between the first electrode500and the second electrode600.

The first electrode500may be electrically coupled to the first terminal312of the electrostatic discharge protection structure310via a first contact structure800and the second electrode600may be electrically coupled to the second terminal314of the electrostatic discharge protection structure310via a second contact structure900. The heat dissipation structure700extends through the second isolation layer400, wherein the first end701is in contact with the electrostatic discharge protection structure310and the second end702is not in direct electrical contact to any conduction region such as the first electrode500or the second electrode600.

As shown inFIG. 3, the second end702is in direct contact to an electrically isolating region, which is formed by the passivation layer1000covering the second isolation layer400. The second end702is thus electrically isolated from the first terminal312and the second terminal314provided that the connection of the second end702to the first and second terminals312,314via the first end701of the heat dissipation structure700and the electrostatic discharge protection structure310is not considered. In other words, there is no further conducting path from the second end702to the first and second terminals312,314except the conducting path via the first end701and the electrostatic discharge protection structure310. According to an embodiment, the heat dissipation structure700may be embedded with an electrically isolating region formed by the second isolation layer400and the passivation1000, wherein only the first end701of the heat dissipation structure700is in direct electrical contact to the electrostatic discharge protection structure310.

The heat dissipation structure700may extend in a lateral direction different to the lateral direction x along the boundary of the first electrode500and/or the second electrode600(cf.FIGS. 2A and 2B). Both possible arrangements of the heat dissipation structure700are illustrated inFIG. 2A. Further rows of the heat dissipation structure700may be provided, as can be seen, for example, inFIG. 2A.

The heat dissipation structure700may be formed simultaneously with the first and second contact structures800and900by forming trenches450,450a,450bthrough the second isolation layer400and the polysilicon layer300, as will be discussed below. The simultaneous formation of the first and second contact structures800and900together with the heat dissipation structure700leads to a beneficial manufacturing process. When forming the first electrode500and the second electrode600on the second isolation layer400to be electrically coupled with the first contact structure800and the second contact structure900, respectively, the bottom side501(FIG. 10G) of the first electrode500and the bottom side601of the second electrode600are at a same vertical level as the second end702of the heat dissipation structure700. The second end702of the heat dissipation structure700may be flush with the top surface402of the second isolation layer400in case the second isolation layer400has a planarized top surface402.

The electrostatic discharge protection structure310embedded between the first isolation layer200and the second isolation layer400has a high thermal impedance due to the thermal isolation by materials like PSG, TEOS, polyoxide or field oxides. The thickness of the electrostatic discharge protection structure310may be in a range of 100 nm to 1000 nm, or in a range of 200 nm to 600 nm, or may be in a range between 200 nm to 500 nm, for example. Due to the small thickness of the electrostatic discharge protection structure310in comparison to its lateral dimensions, the transient thermal capacity, i.e. the thermal capacity which may buffer short thermal dissipation peaks, is low, which may lead to a deterioration of the electrostatic discharge protection structure310or further damages of the semiconductor device10.

Due to the provision of the heat dissipation structure700, the thermal capacity of the electrostatic discharge protection structure310is increased. A thickness of the heat dissipation structure700along a lateral direction (extending from the first terminal312to the second terminal314of the electrostatic discharge protection structure310) may be in a range of 100 nm to 3000 nm and a thickness of the heat dissipation structure700along a vertical direction may be in a range of 1000 nm to 2000 nm or 350 nm to 3500 nm.

Thus, a ratio of a thickness of the heat dissipation structure700along a vertical direction and a thickness of the electrostatic discharge protection structure along a vertical direction may be greater than 1, greater than 2, greater than 3, or greater than 10. By providing the heat dissipation structure700, the effective thickness relevant for the thermal capacity is increased, leading to an improved electrostatic discharge protection structure310with enhanced thermal robustness.

As can be seen fromFIG. 4, which is a detailed view of a portion of the semiconductor device10ofFIG. 3, the first outdiffusion region320and the second outdiffusion region322may be self-aligned to a first lateral side710of the first end701of the heat dissipation structure700and a second lateral side720opposite to the first lateral side710of the first end701of the heat dissipation structure700.

The first end701of the heat dissipation structure700is a plane area of the heat dissipation structure700facing the boundary surface between the electrostatic discharge protection structure310and the second isolation layer400. The first end701is a boundary plane area between the heat dissipation structure700and the intermediate region324of the second region318of the electrostatic discharge protection structure310. As can be seen fromFIG. 4, the first end701is a plane area, which is flush to the boundary surface between the electrostatic discharge protection structure310or the polysilicon layer300and the second isolation layer400.

As mentioned above, the second region318in the electrostatic discharge protection structure310is formed by forming a trench penetrating the second isolation layer400and the polysilicon layer300, wherein the trench is filled with a polysilicon or metal material. Thus, the first end701is not a boundary surface between regions of different material composition. Rather, the material composition of the intermediate region324and the heat dissipation structure700may be the same. The heat dissipation structure700is in contact with the electrostatic discharge protection structure310at its first end701. The first lateral side710and the second lateral side720of the first end701is located at corners between the heat dissipation structure700and the polysilicon layer300at a first lateral side and a second lateral side of the heat dissipation structure700, respectively.

A boundary surface between the intermediate region324and the first outdiffusion region320is formed by a plane being extended vertically from the first lateral side710of the first end701of the heat dissipation structure700. A boundary surface between the intermediate region324and the second outdiffusion region322is formed by a plane being extended vertically from the second lateral side720of the first end701of the heat dissipation structure700. The first and second outdiffusion regions320,322are extended from the intermediate region324into the polysilicon layer300by a lateral dimension c. The boundary surface between the first/second outdiffusion region320,322and the first region316is formed by a pn-junction between the first/second outdiffusion region320,322of a second conductivity type and the first region316of a first conductivity type.

The lateral dimension b of the second region318is a sum of the lateral dimension a of the heat dissipation structure700at its first end701, i.e. the distance between the first lateral side710and the second lateral side720of the first end701, and the lateral dimensions c of the two outdiffusion regions320,322.

According to an embodiment, a ratio of the lateral dimension b of the second region318and of the lateral dimension a of the heat dissipation structure700at the first end701of the heat dissipation structure700is less than 3.0, or less than 2.0, or less than 1.5, or less than 1.2, or less than 1.1. Due to the manufacturing method of the first and second outdiffusion regions320,322, as will be discussed below, the lateral dimension c of the outdiffusion region320or322can be kept at small dimensions, wherein the net dopant gradient at the pn-junction between the first region316and the second region318can be achieved to be relatively high. According to an embodiment, the lateral dimension b of the second region318exceeds the lateral dimension a of the heat dissipation structure700at the first end701of the heat dissipation structure700by less than 2 μm, or by less than 1.5 μm, or by less than 1 μm. Thus, the lateral dimension c of the first and second outdiffusion region320,322may be less than 1 μm, or less than 750 nm, or less than 500 nm.

FIG. 5Ais a diagram illustrating a net dopant profile cnet(x) along the lateral direction x within an electrostatic discharge projection structure310of a semiconductor device in accordance with an embodiment. The net dopant profile cnet(x) is a net dopant profile cnet(x,z) in the polysilicon layer300being averaged within the vertical direction z.

According to an embodiment, a net dopant concentration cnet(−x1) of the first outdiffusion region320at a first lateral distance x1from a center O of the heat dissipation structure700equals a net dopant concentration cnet(x1) of the second outdiffusion region322at the first lateral distance x1in opposite direction from the center O of the heat dissipation structure700. As can be seen fromFIG. 5A, the net dopant profiles of the first and second outdiffusion regions320,322are mirror symmetric in the lateral direction x with respect to the heat dissipation structure700. As can be seen fromFIG. 5A, the net dopant profile cnet(x) declines with increasing distance from the heat dissipation structure700(the center O) in a lateral direction x.

FIG. 5Bis a diagram illustrating a first net dopant profile cnet_1(x) along a lateral direction x within an electrostatic discharge protection structure310of a semiconductor device10in accordance with an embodiment in comparison to a second dopant profile cnet_2along a lateral direction x within an electrostatic discharge protection structure according to an example. As can be seen fromFIG. 5B, the lateral dimension b of a second region318having the net dopant profile cnet_1(x) can be formed with significant lower dimensions than the lateral dimension b′ of a second region in a polydiode structure having the net dopant profile cnet_2(x). In addition, the net dopant gradient at a pn-junction between a first and a second region316,318is higher in the net dopant profile cnet_1(x) in comparison to the net dopant profile cnet_2(x).

FIG. 6Ais a detailed cross-sectional view of a portion of a semiconductor device10illustrating the first net dopant profile cnet_1(x,z) within an electrostatic discharge protection structure310of a semiconductor device10in accordance with an embodiment.FIG. 6Bis a detailed cross-sectional view of a portion of a semiconductor device10illustrating the second dopant profile cnet_2(x,z) within an electrostatic discharge protection structure according to an example. The net dopant profiles inFIGS. 6A and 6Bare illustrated by equi-concentration lines in the plane spanned by the lateral direction x and the vertical direction z.

The pn-junctions between a second region318and a first region316have different structures in the devices as shown inFIG. 6A and 6B. Depending on diffusion of the dopants in silicon grain, grain boundaries and segregation effects, the diffusion front in x direction may be concave, convex, perpendicular or mixed. As long as the curvature of the resulting pn-junctions has no acute angles, the breakdown behaviour results from an average of the polysilicon grain structure with a symmetry concerning x=0 inFIG. 5A.

The difference between the two illustrated net dopant profiles inFIGS. 6A and 6Bresults from the different manufacturing processes. In particular, in the structure as shown inFIG. 6A, the polysilicon layer300is already doped with dopants of a p-type having a p+-concentration, wherein, after forming trenches in the polysilicon layer300and filling the trenches with a polysilicon material of an n-type having an n++-concentration, the n-dopants are thermally diffused into the p+-region to form a second region318neighbouring a first region316of a p-type. In comparison thereto, in the structure ofFIG. 6B, an n-type polysilicon layer300is doped with a p++-dopant in a first region316. In order to make the structures ofFIGS. 6A and 6Bcomparable, the second region318inFIG. 6A and 6Bhas been simulated to be formed in a same manner.

Thus, as can be seen fromFIG. 5B,FIG. 6A and 6B, the cathode regions may be significantly reduced in dimension. This results in a reduced collector/emitter-series resistance and in a higher emitter efficiency such that high injection effects only occur at higher breakdown currents.

FIG. 7is a graph illustrating a first I-V-characteristic I1(V) of an electrostatic discharge protection structure310of a semiconductor device10in accordance with an embodiment in comparison to a second I-V-characteristic I2(V) of an electrostatic discharge protection structure of a semiconductor device in accordance to an example.FIG. 7shows a simulated diode breakdown current characteristics I1(V) of an electrostatic discharge protection structure310manufactured in accordance with a manufacturing method according to an embodiment in comparison to a simulated diode breakdown current characteristics I2(V) of an electrostatic discharge protection structure being manufactured by a separate masking process of the first region316of a p-type. Compared to the I-V-characteristic I2(V), the first I-V-characteristic I1(V) has a four times or five times higher diode current in a breakdown current scenario. This results in a four times higher electrostatic discharge robustness and in a five times higher electrostatic discharge voltage window, since the differential resistance in that part of the I-V-characteristic is reduced drastically. Due to the self-alignment and the symmetry of the second region318within the electrostatic discharge protection structure310, the electrostatic discharge voltage window is symmetrically in both current directions within the lateral direction x.

A reduction of the electrostatic discharge voltage window for positive and negative voltages is important for an optimal fitting of the electrostatic discharge protection structure310to gate oxide screening tests of a load MOS device having an integrated electrostatic discharge diode. The smaller the variance of the device parameters, the nearer the breakdown voltage of an anti-serial diode chain may be brought to a desired value such as a maximum allowable voltage between gate and source (VGS value). Thus, a small diode reverse current at respective low self-heating of the semiconductor device10may be achieved. As can be seen fromFIG. 7, the electrostatic discharge voltage window Delta_V1of the first I-V-characteristic I1(V) is five times smaller than the electrostatic discharge voltage window Delta_V2of an polydiode chain according to an example.

FIG. 8is a schematic cross-sectional view of a portion of a semiconductor device10taken along a section plane A-A′ ofFIG. 2AorFIG. 2Bin accordance with an embodiment.

As can be seen fromFIG. 8, the semiconductor device10further comprises the second isolation layer400on the electrostatic discharge protection structure310. The second isolation layer400comprises the first dielectric layer410as discussed above and further a third dielectric layer430.

The third dielectric layer430of the second isolation layer400may include at least one of a silicon oxide, a nitride or an oxynitride layer. The thickness of the third dielectric layer430of the second isolation layer400may be in a range of 40 nm to 1000 nm, or in a range of 100 nm to 300 nm. On the second isolation layer400, a gate contact area510is formed, wherein the gate contact area510is electrically coupled to the first terminal312of the electrostatic discharge protection structure310via the first contact structure800. The second isolation layer400in the semiconductor device10ofFIG. 8may also comprise the second dielectric layer420as discussed above with regard toFIG. 3.

The semiconductor device10ofFIG. 8further comprises a source contact area610on the second isolation layer400, wherein the source contact area610is electrically coupled to the second terminal314of the electrostatic discharge protection structure310via the second contact structure900. The third dielectric layer430is formed between the gate contact area510and the second contact structure900, to electrically isolate the gate contact area510from the source contact area610. The passivation layer1000is formed on the second isolation layer400, the gate contact area510and the source contact area610, wherein the heat dissipation structure700of the electrostatic discharge protection structure310is formed such that its second end702is either in contact with the passivation layer1000or the third dielectric layer430.

As can be seen fromFIG. 8, the first isolation layer200may be a gate dielectric. The electrostatic discharge protection structure310is formed on the first isolation layer200, which leads to reduced thermal transient impedance due to the enhanced thermal coupling between the electrostatic discharge protection structure310and the semiconductor body100. The gate dielectric may be a silicon oxide having a thickness in a range of 5 nm to 200 nm, or in a range 40 nm to 120 nm. The semiconductor device10further comprises transistor cells20arranged in an overlap area between the gate contact area510and the semiconductor body100. Each of the transistor cells20comprise a gate electrode330formed on the first isolation layer200, source zones150being in contact with the first surface101of the semiconductor body100and extending into the semiconductor body100, and body zones160, in which the source zones150are embedded. The source zones150are of the first conductivity type and the body zones160are of the second conductivity type. Furthermore, the drain region110of the first conductivity type is provided at the second surface102of the semiconductor body100. The drift region120is formed between the drain region110and the body zones160and is of a first conductivity type. In case of a superjunction device, columns or bubbles of the first conductivity type and the second conductivity type can be implemented both beneath the semiconductor well region140and the active transistor cell field. Furthermore, columns or bubbles of the second conductivity type can be overlapping with the semiconductor well region140.

According to an embodiment, the gate electrodes330are formed simultaneously with the electrostatic discharge protection structure310, and may be part of the polysilicon layer300. The second contact structure900is provided to electrically connect the source contact area610with the second terminal314of the electrostatic discharge protection structure310. The second contact structure900may be further provided to connect the source contact area610with the source zones150of the transistor cells20. According to an embodiment, the first contact structure800and the heat dissipation structure700may include a same material. In addition, according to an embodiment, the second contact structure900and the heat dissipation structure700may include a same material. Furthermore, the first contact structure800, the second contact structure900and the heat dissipation structure700may include a same material. The first contact structure800, the second contact structure900and the heat dissipation structure700may be formed simultaneously, as will be discussed later.

As can be seen fromFIG. 8, the electrostatic discharge protection structure310may have two second terminals314being arranged at opposite sides from the first terminal312. Thus, the lateral direction x may be directed to opposite sides, depending on the direction from the first terminal312to the second terminal314. As can be seen fromFIG. 8, a bottom side511of the gate contact area510and/or a bottom side611of the source contact area610and a top side702of the heat dissipation structure700may be at a same vertical level, which may result from a specific manufacturing process, as will be discussed below. The semiconductor device10thus comprises transistor cells20comprising source and body zones150,160in the semiconductor body100, wherein the source zones150are electrically coupled to the source contact area610via the second contact structure900. The second contact structure900and the heat dissipation structure700may include a same material.

The thickness of the first isolation layer200may be in a range between 0.1 μm to 10 μm, or between 0.5 μm to 10 μm, or between 0.5 μm to 5 μm, or between 1 μm and 2.5 μm, or between 1.5 μm and 2 μm in case of a field oxidation process. The thickness of the polysilicon layer300may be in a range of 100 nm to 1000 nm, or in a range of 200 nm to 600 nm, or may be in a range between 200 nm to 500 nm. Due to the relatively small vertical dimension of the polysilicon layer300, the topology of the layer structure may be well-defined. Thus, an improved depth of sharpness region may be achieved at an lithographic process for forming contact holes on active regions and field regions. In order to reach an ESD robustness of 1 to 4 kV, the current density at the diode width as discussed above may be sufficient within the gate pad region and the boundary regions.

When forming the body zones160in the area of the transistor cells20after forming the polysilicon layer300, the trench450may be lined with a metal layer of, for example titanium, having a thickness in a range between 20 nm to 70 nm and may be processed to form a silicide locally at a bottom region of the trench450. To prevent a Schottky contact, the trenches450,450a,450bmay be formed deep enough such that no silicide in the bottom area of the trenches450,450a,450bmay be formed. In case a boron implantation for forming body contact zones160aat the transistor cells20is performed, the implantation may be removed to a grand part by etching the trenches450,450a,450bfor the second contact structure900into the semiconductor body100. It is however, also possible to mask the polysilicon layer300in case of performing a ion implantation for forming the body contact regions160a.

In case the polysilicon layer300is formed on a first isolation layer200being a gate oxide layer, an etch stop layer may be deposited below the polysilicon layer300, which comprises an oxide or a nitride material. By providing an etch stop layer between the polysilicon layer300and the first isolation layer200it can be prevented that the first isolation layer200being a relatively thin gate oxide is thinned within etching the trench450penetrating the polysilicon layer300and further penetrating into the first isolation layer200. In case of providing a trench penetrating into the semiconductor body100(which is filled with the second contact structure900), the same penetration depth in the polysilicon layer300may be achieved.

According to an embodiment, the polysilicon plugs of heat dissipation structure700being, for example of an n+-type serve as a self-aligned dopant source and the first and second contact structures800,900for an anti-serial diode structure acting as an electrostatic discharge protection structure310. Thus, the at least one second region316as well as the first and second contact structure800,900are self-aligned to each other, leading to a reduction of electric parameter variants and in particular to a bidirectional width of the electrostatic discharge voltage window at low differential series resistance. The integration of an electrostatic discharge protection structure310in a solid-state switch as discussed above may lead to cost reductions of about500.

Although no multilayer metallization structure is shown, the electrostatic discharge protection structure310as described above may be used in discrete semiconductor devices or integrated circuits with multilayer wiring systems, when using polysilicon plugs.

FIG. 9illustrates a schematic process charge of a method of manufacturing a semiconductor device10in accordance with an embodiment.

Process feature5110includes forming a first isolation layer on a semiconductor body.

Process feature5120includes forming a polysilicon layer of a first conductivity type on the first isolation layer.

Process feature5130includes forming a second isolation layer on the polysilicon layer.

Process feature5140includes forming a trench penetrating the second isolation layer and the polysilicon layer.

Process feature S150includes forming a heat dissipation structure in the trench.

Process feature S160includes forming first and second outdiffusion regions of a second conductivity type in the polysilicon layer to form a self-aligned electrostatic discharge protection structure.

InFIGS. 10A to 10G, a method of manufacturing the semiconductor device10according to an embodiment will be described with reference to cross-sectional views for illustration of selected processes.

InFIG. 10A, a semiconductor body100, as described above, is provided. As shown inFIG. 10B, the first isolation layer200such as a silicon oxide layer is formed on the semiconductor body100. The oxide layer of the first isolation layer200may be formed by a field oxidation or deposition process or may be formed as a gate oxide layer.

As shown inFIG. 10C, a polysilicon layer300of a first conductivity type is formed on the first isolation layer200. The polysilicon layer300may be patterned to have a structure within the lateral plane as shown inFIG. 2AorFIG. 2B(cf. the structures inFIG. 2A and 2Bdefined by the dashed lines). The thickness of the polysilicon layer300in a vertical direction z may be in a range of 100 nm to 1000 nm, or 200 nm to 600 nm, or 200 nm to 500 nm. The thickness of the polysilicon layer300may be limited by the penetration depth of the dopants of the first conductivity type in an ion implantation and diffusion process.

According to an embodiment, boron ions may be used to dope the undoped or weakly n doped polysilicon layer300in an ion implantation process. The polysilicon layer300may also be of second conductivity type with a lower doping concentration and can be overcompensated by implantation of, for example the body implant, into the first conductivity type.

In case of using boron ions as dopants, the diode parameters of the electrostatic discharge protection structure310formed in the polysilicon layer300may be fine-tuned. However, according to another embodiment, phosphorus ions may be used for doping the polysilicon layer300in an ion implantation process. The net dopant concentration of the polysilicon layer300of the first conductivity type may be in a range of 5×1016cm−3to 5×1019cm−3, or in a range of 5×1016cm−3to 5×1018cm−3, or in a range of 1×1017cm−3to 1×1018cm−3.

According to an embodiment, the polysilicon layer300may be of a p-type. In case the first isolation layer200is formed in a field oxidation process, the first isolation layer200may be removed within an area comprising transistor cells20to form a gate oxide acting as the first isolation layer200in the transistor cell area. The thickness of the gate oxide in a vertical direction z may be in a range of 5 nm to 200 nm, or 70 nm to 90 nm or 40 nm to 120 nm. After forming a gate oxide on the semiconductor body100, a polysilicon layer may be formed on the first isolation layer200having a second conductivity type, which is patterned to form a gate electrode layer330as shown inFIG. 8.

An ion implantation of dopants of a first conductivity type to form the body zones160within the semiconductor body100may be combined with an ion implantation of dopants of the first conductivity type within the polysilicon layer300. Thus, the body zones160and the doping of the polysilicon layer300with dopants of a first conductivity type may be formed in one process. According to another embodiment, the polysilicon layer300may have a net dopant concentration of a first conductivity type or second conductivity type, which is below a net dopant concentration of 1×1017cm−3, or may further be an undoped polysilicon layer300, wherein the final net dopant concentration of the polysilicon layer300of the first conductivity type can be set in the sequent implantation step of the body zones160. As can be further seen fromFIG. 8, source zones150and body contact zones160aare formed in the semiconductor body100.

As can be seen fromFIG. 10D, the second isolation layer400is formed on the polysilicon layer300. As discussed above, the second isolation layer400may comprise a first dielectric layer410and a second dielectric layer420, wherein the first dielectric layer410may comprise an USG layer having a thickness in a vertical direction z in a range between 50 nm to 500 nm, or 200 nm to 400 nm. The second dielectric layer420may comprise a BPSG-layer having a thickness in a range of 200 nm to 2000 nm, or 1100 nm to 1300 nm. The first and second dielectric layer410may further comprise the materials or have a structure as discussed above.

InFIG. 10E, a trench450penetrating the second isolation layer400and the polysilicon layer300is formed. The trench450may extend up to a distance of 300 nm into the polysilicon layer300. The trench450fully penetrates the polysilicon layer300to ensure that the polysilicon layer300acts as a polydiode structure, as will be discussed below. There may be more than one trench450provided to be filled with a respective heat dissipation structure700. Thus, the heat dissipation structure700may be provided multiple times and may be sequentially aligned in equidistant spacing from each other. The multiple heat dissipation structures700as shown, for example inFIG. 8, may be arranged in an isolation region comprising the first isolation layer200, the second isolation layer400and the passivation layer1000and form a polydiode structure of diodes being connected in an anti-serial cascade within the polysilicon layer300. Such a structure cannot be achieved with a common power metallization layer (having, for example, a thickness of 5 μm) due to common design rules. Thus, a fine structure of pn-junctions having lateral dimensions in a range of 1 μm to 10 μm, or in a range between 4 μm to 5 μm can be manufactured with a common power metallization.

The trench450to be filled with the heat dissipation structure700may be formed at the same time with a trench450ato be filled with the first contact structure800and a trench450bto be filled with the second contact structure900. As can be seen fromFIG. 8, the trench450to be filled with the heat dissipation structure700may be formed at the same time together with the trench450bto be filled with the second contact structure900to contact the source zones150and the body zone160(via the body contact zone160a). Herein, the trench450bto be filled with the second contact structure900may extend up to 300 nm into the semiconductor body100.

As can be seen fromFIG. 10F, the heat dissipation structure700is formed in the trench450, wherein further first and second outdiffusion regions320,322of a second conductivity type are formed in the polysilicon layer300, to form an electrostatic discharge protection structure310.

Exemplary embodiments for forming the heat dissipation structure700and the electrostatic discharge protection structure310will be discussed below with regard toFIGS. 11A to 11C,FIGS. 12A to 12C, andFIGS. 13A to 13D.

As can be seen fromFIG. 10F and 10G, the first contact structure800, the second contact structure900and the heat dissipation structure700may be formed by the following process. Firstly, the trenches450,450aand450bare formed within the second isolation layer400and the polysilicon layer300, e.g. by an anisotropic etching process. Thereafter, an electrically and thermally conductive material may be deposited on the second isolation layer400to fill the trenches450,450a,450bwith an electrically and thermally conductive material. The electrically and thermally conductive material on the top surface402of the second isolation400may be removed by a planarization process, e.g. a chemical mechanical polishing (CMP) process. By this process, a planarized top surface402of the second isolation layer400may be formed, with first and second contact structures800,900and the heat dissipation structure700. The second end702of the heat dissipation structure700may be in direct contact with the passivation layer1000covering the first electrode500, the second isolation layer400and the second electrode600.

In the following, two embodiments of forming the heat dissipation structure700and the electrostatic discharge protection structure310will be discussed.

FIGS. 11A to 11Care cross-sectional views illustrating a method of forming a heat dissipation structure700and first and second outdiffusion regions320,322in accordance with an embodiment.

As shown inFIG. 11A, the trench450is formed in the second isolation layer400and the polysilicon layer300, wherein the trench450fully penetrates the polysilicon layer300and the second isolation layer400. Herein, the first isolation layer200may be used an etch stop layer. The trench450may be formed by an appropriate process, e.g. dry and/or wet etching. As an example, the trench450may be formed by an anisotropic plasma etch process, e.g. reactive ion etching (RIE) using an appropriate etch gas, e.g. at least one of Cl2, Br2, CCl4, CHCl3, CHBr3, BCl3, HBr. According to an embodiment, trench sidewalls451of the trench450may be slightly tapered, e.g. including a taper angle between 88° and 90°. Slightly tapered trench sidewalls451may be beneficial with regard to avoiding trench cavities when filling up trenches.

As can be seen fromFIG. 11B, the trench450is filled with a polysilicon material730of a second conductivity type to form the heat dissipation structure700. The polysilicon material730may be of an n-type in case the polysilicon layer300is of a p-type. According to an embodiment, the net dopant concentration in the polysilicon material730is of such a magnitude that the polysilicon material730may be used as an transient infinite dopant source. The net dopant concentration of the second conductivity type in the polysilicon material730may be higher than 1×1019cm−3, or higher than 5×1019cm−3, or higher than 1×1020cm−3. The net dopant concentration of the second conductivity type in the polysilicon material730may be lower than 5×1020cm−3. According to an embodiment, the n+-doped polysilicon material730may be doped with phosphorus. At a thickness in the lateral direction x of the trench450being in a range of 300 nm to 1500 nm, or in a range of 500 nm to 1200 nm, or in a range of 500 nm to 1000 nm, at a vertical dimension of the trench450being in a range of 1000 nm to 2500 nm, or in a range of 1500 nm to 2000 nm, or in a range of 1750 nm to 1850 nm, and at annealing processes having a relatively low temperature budget. In particular, annealing processes may be performed for activating the source/body contacts and the dopants within the polysilicon material730, the polysilicon material730can be regarded as a transient infinite dopant source. The annealing processes may be performed at temperatures between 900° C. to 975° C. and at annealing periods of 30 second to 5 minutes, or 30 seconds to 100 minutes. Alternatively, rapid thermal annealing (RTP) process steps can be performed at temperatures up to 1100° C. and several seconds annealing time.

As can be seen fromFIG. 11C, the annealing and activation step leads to a thermally induced diffusion of dopants of the second conductivity type from the heat dissipation structure700(or from the polysilicon material730) into the polysilicon layer300to form the first and second outdiffusion regions320,322. Due to the specific annealing and activation step as shown inFIG. 11C, the first and second outdiffusion regions320,322may be provided with a relatively short lateral dimension, i.e. having a lateral dimension being in a range between 100 nm to 700 nm, or in a range of 200 nm to 500 nm. At the same time, the first and second outdiffusion regions320,322have a relatively high net dopant concentration (in a range between 1×1019cm−3to 1×1020cm−3) combined with a high net dopant profile gradient at the pn-junction between the polysilicon layer300of the first conductivity type and the first or second outdiffusion region320,322of the second conductivity type. The high gradient at the pn-junction between the second region318(including the first and second outdiffusion regions320,322) and the first region316(including the polysilicon layer300of the first conductivity type remaining after forming the first and second outdiffusion regions320,322) has already been discussed with regard toFIGS. 5A and 5B, in particular at the pn-junction at a lateral dimension b/2from the center point0. Due to the high gradient of the pn-junction within the first and second region316,318, a relatively low emitter/collector-series resistance may be achieved.

FIGS. 12A to 12Care cross-sectional views illustrating a method of forming a heat dissipation structure700and first and second outdiffusion regions320,322in accordance with another embodiment. The process steps as shown inFIGS. 12A to 12Care basically the same steps as shown inFIGS. 11A to 11C, subject to forming the trench450within the polysilicon layer300, which not fully penetrates the polysilicon layer300. The dimension of the trench450in a vertical direction z may be in a range of 50% to 90% of the dimension of the polysilicon layer300in the vertical direction z. As can be seen fromFIGS. 12B and 12C, the annealing and activation step leads to a thermally induced diffusion of dopants of the second conductivity type from the heat dissipation structure700(or from the polysilicon material730) into the polysilicon layer300to form the first and second outdiffusion regions320,322. Herein, the diffusion of dopants into the polysilicon layer occurs not only mainly along the lateral direction x, but also along a vertical direction z. Due to the diffusion of dopants of the second conductivity type from the bottom area of the trench450into the polysilicon layer300located below the trench450, a complete penetration of the intermediate region324with dopants of the second conductivity type can be achieved, leading to a polydiode structure in the polysilicon layer300. When processing the trench450together with trenches in the active area, for example an active transistor cell area, silicide processes and/or contact implants applied to the trenches in the active area may be masked with respect to the trench450, for example.

FIGS. 13A to 13Dare cross-sectional views illustrating a method of forming a heat dissipation structure700and first and second outdiffusion regions320,322in accordance with still another embodiment.

FIG. 13Aillustrates the process step of forming a trench450penetrating the second isolation layer400and the polysilicon layer300, as already discussed above with regard toFIG. 11A. It shall be emphasized that the following process steps illustrated inFIG. 13B to 13Dmay also be performed when starting with a structure as shown inFIG. 12A, in which a trench450is formed within the polysilicon layer300, which not fully penetrates the polysilicon layer300.

As shown inFIG. 13B, after forming the trench450, a part320a,322aof the polysilicon layer is doped via trench sidewalls451of the trench450by dopants of a second conductivity type.

According to an embodiment, dopants of a second conductivity type may be introduced uniformly in the polysilicon layer300via the trench sidewalls451of the at least one trench450by a plasma doping process. Plasma doping of the part of the polysilicon layer300via trench sidewalls451of the trench450allows high dose implants at low energies and is also known as PLAD (plasma doping) or PIII (plasma immersion ion implantation).

These methods allow for a precise doping of the part of the polysilicon layer300at the trench sidewalls451. A conformal doping of the part of the polysilicon layer300at the trench sidewalls451can be achieved by applying a voltage to a substrate surrounded by a radio frequency (RF) plasma including a dopant gas. Collisions between ions and neutral atoms as well as the biasing of the semiconductor body100lead to a broad annular distribution of the dopants allowing for a homogeneous doping over the trench sidewalls451. Also a small vertical gradient in dose of doping in the part of the polysilicon layer300may be achieved by plasma doping. This allows for a vertical variation of a degree of charge compensation improving stability of manufacture and/or avalanche robustness. A vertical variation of dose of doping may be smaller 20%, or smaller than 10% or smaller than 5%.

When doping with PLAD, the semiconductor body100having the trench450is exposed to a plasma including ions of dopants. These ions are accelerated by an electric field towards the semiconductor body100and are implanted into an exposed surface of the polysilicon layer300. An implanted dose can be adjusted or controlled via DC voltage pulses, e.g. negative voltage pulses. A Faraday system allows to adjust or control the dose. Two sets of coils, i.e. a horizontal coil and a vertical coil allow to generate the plasma and keep it homogeneous. An ion density can be adjusted via a distance between the coils and the substrate. Interaction between the vertical coils and the horizontal coils allows to adjust or control homogeneity and the ion density.

A penetration depth of the dopants into the polysilicon layer300and the implant dose may be adjusted via a pulsed DC voltage applied between the semiconductor body100and a shield ring surrounding it.

According to an embodiment, doping the part of the polysilicon layer300by plasma doping includes introducing the dopants into the part of the polysilicon layer300via the trench sidewalls451at a dose in a range of 5×1011cm−2to 3×1013cm−2, or in a range of 1×1012cm−2to 2×1013cm−2. This comparatively low dose requires modifications of the pulsed DC voltage typically used. Typically doses exceeding 1015cm−2are implanted by these techniques. According to an embodiment, a pulse distance of the DC voltage pulses is adjusted in a range of 100 μs to 10 ms, in particular between 500 μs and 5 ms. A DC voltage pulse rise time is set to a value smaller than 0.1 μs, for example. According to an embodiment a pulse width ranges between 0.5 μs to 20 μs, or between 1 μs to 10 μs.

Thereafter, as shown inFIG. 13C, the dopants of the second conductivity type are thermally induced diffused from the trench sidewalls451into the polysilicon layer300, to form the first and second outdiffusion regions320,322.

As shown inFIG. 13D, the trench450may be filled with a conductive material740to form the heat dissipation structure. The conductive material740may be a metal. The conductive material740is a material having a thermal and electric conductivity, to ensure electric conductance within the polysilicon layer300between the first outdiffusion region320and the second outdiffusion region322. The conductive material740may also be a semiconductor material or a polysilicon material of a first conductivity type, to form a polydiode structure between the first outdiffusion region320, the material740and the second outdiffusion region322. The conductive material740may comprise, for example tungsten or titanium.

According to an embodiment, the trench450may be etched, thereafter the trench sidewalls451may be doped or be lined with an PSG/anneal/PSG glass wet etch. Herein, in a first step, the trench450is etched through the oxide stack of the second isolation layer400, stopping on the polysilicon layer300. Then, for selective wet etching of the later deposited PSG glass (and not the BPSG of the second dielectric layer420), a thin nitride layer (e.g. in a range of 20 to 50 nm) Si3N4(or SiON) may be deposited on BPSG top and BPSG sidewalls. This is followed by the silicon trench process, PSG fill and outdiffusion, and wet etching of PSG and nitride. Thereafter the trench sidewalls451are lined with TiSi2or CoSi2, TiN and a material740such as W, AlCu, AlSiCu, or Cu.

An advantage of the structure as described above is the stable manufacturing process, since a vertical relative variation of implantation tails, which occur at a variation or a change of layer thickness in a vertical direction of the polysilicon layer300or straying oxides does not have an impact on the forming of the electrostatic discharge protection structure.