Semiconductor device having an air gap along a gate spacer

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

BACKGROUND

The semiconductor industry has experienced rapid growth. Technological advances in semiconductor materials and design have produced generations of semiconductor devices where each generation has smaller and more complex circuits than the previous generation. In the course of integrated circuit (IC) evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, these advances have also increased the complexity of processing and manufacturing semiconductor devices.

For example, as integrated circuit (IC) technologies progress towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure, or portion thereof, disposed over more than one side of a channel region. Fin-like field effect transistors (FinFETs) and gate-all-around (GAA) transistors (both also referred to as non-planar transistors) are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. A FinFET has an elevated channel wrapped by a gate on more than one side (for example, the gate wraps a top and sidewalls of a “fin” of semiconductor material extending from a substrate). A GAA transistor has a gate structure that can extend, partially or fully, around a channel region to provide access to the channel region on two or more sides. The channel region of the GAA transistor may be formed from nanowires, nanosheets, other nanostructures, and/or other suitable structures.

As the dielectric layers between a gate structure and a source/drain contact of a multi-gate device become thinner, parasitic capacitance between the gate structure and the source/drain contact may impact device performance. Various measures have been proposed to reduce such parasitic capacitance. Some of these measures may compromise dielectric structures around the gate structure, resulting in reduced process windows. Therefore, although conventional multi-gate devices and methods are generally adequate for their intended purposes, they are not satisfactory in all aspects.

DETAILED DESCRIPTION

The present disclosure is generally related to semiconductor devices and fabrication methods thereof, and more particularly to the formation of air gaps between source/drain (S/D) contacts and neighboring gate structures. As multi-gate technologies progress towards smaller technology nodes, decreasing active region pitch places significant constraints on materials that can be used between gate structures and neighboring S/D contacts. To lower or minimize parasitic capacitance, insulating (or dielectric) materials with relatively low dielectric constants (k), such as low-k dielectrics and/or air (by forming an air gap, for example), may be incorporated between various conductive features in a semiconductor device. In some instances, self-aligned contact (SAC) dielectric features or capping layers overlying gate structures and gate spacer layers may be breached in order to form such low-K dielectric features or air gaps. However, when the self-aligned contact (SAC) dielectric features or capping layers are breached, protection of the gate structure and gate spacer layers may become less protected during etch processes for forming source/drain contact openings.

The present disclosure provides methods for forming air gaps between gate structures and source/drain contacts without forming vertical openings through SAC dielectric features or capping layers disposed over the gate structures and gate spacer layers. In an example process of the present disclosure, a first dummy spacer layer and a second dummy spacer layer are formed over a dummy gate stack and source/drain features. After the top facing portion of the second dummy spacer layer is etched back, an etch stop layer (ESL) and an interlayer dielectric (ILD) layer are deposited over the first and second dummy spacer layers. The dummy gate stack is removed and replaced with a functional gate structure. A SAC dielectric feature or a capping layer is then formed over the gate structure, the first dummy spacer layer and the second dummy spacer layer. Source/drain contacts that extends through ESL and the ILD layer are fabricated over the source/drain features. Using the source/drain contact and the SAC dielectric feature as the etch mask, a portion of the ILD layer adjacent ends of the source/drain contact are recessed to expose sidewalls of the ESL. A lateral opening is then formed through the exposed sidewalls of the ESL to expose the second dummy layer. The second dummy layer under the SAC dielectric feature is then laterally removed to form an air gap. A seal layer is then deposited to seal the air gap. Because the seal layer may be formed of a material different from that of a further ILD layer deposited over the SAC dielectric feature (or the capping layer), the further ILD layer may be selectively removed to form slot-shaped source/drain contact vias. By way of lateral removal of the second dummy spacer layer to form the air gap, the SAC dielectric layer (or the capping layer) remains disposed over the ESL and the first dummy spacer layer to provide protection from misaligned source/drain contact vias.

The various aspects of the present disclosure will now be described in more detail with reference to the figures.FIG.1illustrates a flowchart of a method100of forming a semiconductor device on a workpiece200(not shown inFIG.1but shown inFIGS.2A-17).FIG.18illustrates a flowchart of a method300of forming a semiconductor device on a workpiece200(not shown inFIG.18but shown inFIGS.19A-34). Methods100and300are each merely an example and not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after method100or method300, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. Method100is described below in conjunction withFIGS.2A,2B,3A,3B,4A,4B,5A,5B,6A,6B,7A,7B,8A,8B,9A,9B,10A,10B,11A,11B,12A,12B,13A,13B, and14-17, each of which illustrate a fragmentary cross-sectional view or a top view of the workpiece200during various operations of method100. Method300is described below in conjunction withFIGS.19A,19B,20A,20B,21A,22B,23A,23B,24A,24B,25A,26A,26B,27A,27B,28A,28B,29A,29B,30A,30B, and31-34, each of which illustrate a fragmentary cross-sectional view or a top view of the workpiece200during various operations of method300. The workpiece200may be an intermediate device fabricated during processing of an IC, or a portion thereof, that may comprise static random-access memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and/or other memory cells. The present disclosure is not limited to any particular number of devices or device regions, or to any particular device configurations. For example, though the workpiece200as illustrated includes three-dimensional FinFET devices, the present disclosure may also provide embodiments for fabricating GAA devices. Additional features can be added in semiconductor devices fabricated on the workpiece200, and some of the features described below can be replaced, modified, or eliminated in other embodiments of the semiconductor device to be fabricated on the workpiece200. Because a semiconductor device is to be formed from the workpiece200at the conclusion of the processes described in the present disclosure, the workpiece200may be referred to as a semiconductor device200as the context requires.

For better illustration of various aspects of the present disclosure,FIGS.2-13each include a figure ending with A and another figure ending with B. A figure ending with A, such asFIGS.2A-13A, illustrates a fragmentary cross-sectional view of the workpiece200along the cross-section I-I′ that extends along the X direction through the active region204. A figure ending with B, such asFIGS.2B-13B, illustrates a fragmentary cross-sectional view of the workpiece200the cross-section II-IF that extends along the X but does not extend through the active region204. Figures sharing the same number but ending with different letters may be collectively referred to by the number. For example,FIGS.9A and9Bmay be collectively referred to asFIG.9.

Referring toFIGS.1,2A and2B, method100includes a block102where a workpiece200is received. The workpiece200includes a dummy gate stack206over a channel region10of an active region204, a first spacer layer212over the dummy gate stack206, a second spacer layer214over the first spacer layer212, a source/drain feature216over a source/drain region20of the active region204. The workpiece200includes active region204(or a fin-shaped region204) connected to and arising from the substrate202. The active region204may include one or more channel regions of a multi-gate device. For example, the active region204may be a fin structure of an FinFET or may a stack of alternating epitaxial layers of a gate-all-around (GAA) transistor. The active region204includes a channel region10and a source/drain region20adjacent the channel region10. The channel region10may be disposed between two source/drain regions20. The workpiece200includes a dummy gate stack206that includes a dummy electrode208and a hard mask210. A first gate spacer212is disposed over sidewalls of the dummy gate stack206and a second gate spacer214is disposed on sidewalls of the first gate spacer212. Although not shown inFIG.2A, the dummy gate stack206may also include a dummy gate dielectric layer disposed between the dummy electrode208and the channel region10of the active region204.

The active region204is formed over a substrate202. The substrate202may include an elementary (single element) semiconductor, such as silicon, germanium, and/or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and/or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and/or other suitable materials. The substrate202may be a single-layer material having a uniform composition. Alternatively, the substrate202may include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, the substrate202may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a silicon oxide layer. In another example, the substrate202may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. In some embodiments where the substrate202includes FETs, various doped regions, such as source/drain regions, are disposed in or on the substrate202. The doped regions may be doped with n-type dopants, such as phosphorus or arsenic, and/or p-type dopants, such as boron or BF2, depending on design requirements. The doped regions may be formed directly on the substrate202, in a p-well structure, in an n-well structure, in a dual-well structure, or using a raised structure. Doped regions may be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and/or other suitable techniques.

The active regions204may be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer (resist) overlying the substrate202, exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element (not shown) including the resist. The masking element is then used for etching recesses into the substrate202, leaving the active regions204on the substrate202. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. Numerous other embodiments of methods for forming the active regions204may be suitable. For example, the active regions204may be patterned using double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the active regions204.

While not explicitly shown inFIG.2A, the active region204may be separated from an adjacent active region204by an isolation feature, which may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable materials. The isolation feature may include shallow trench isolation (STI) features. In one embodiment, the isolation feature may be formed by etching trenches in the substrate202during the formation of the fin structures204. The trenches may then be filled with an isolating material described above by a deposition process, followed by a chemical mechanical planarization (CMP) process. Other isolation structure such as field oxide, local oxidation of silicon (LOCOS), and/or other suitable structures may also be implemented as the isolation feature. Alternatively, the isolation feature may include a multi-layer structure, for example, having one or more thermal oxide liner layers. The isolation feature may be deposited by any suitable method, such as chemical vapor deposition (CVD), flowable CVD (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof.

In some embodiments, the dummy gate electrode208may be formed of polysilicon. The hard mask210may be a single layer or a multi-layer and may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The first spacer layer212and the second spacer layer214may be each formed of a dielectric material selected from silicon nitride, hafnium silicide, aluminum oxynitride, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium nitride, silicon carbide, zinc oxide, silicon oxycarbonitride, silicon, yittrium oxide, tantalum carbonitride, zirconium silicide, silicon carbonitride, zirconium aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide. In some implementations, the first spacer layer212and the second spacer layer214may be formed of different dielectric materials. As shown inFIG.2A, in some embodiments, the dummy gate stack206and the first spacer layer212are disposed over the channel region10of the active region204. The gate dummy gate stack206is not only disposed over a top surface of the channel region10of the active region204but also extends along sidewalls of the active region204. As shown inFIG.2B, outside the active region204, the first spacer layer212and the second spacer layer214are disposed along sidewalls of the dummy gate stack206.

Source/drain features216may be formed by any suitable techniques, such as etching processes followed by one or more epitaxy processes, in the source/drain regions20. In one example, using the dummy gate stack206, the first spacer layer212and the second spacer layer214as an etch mask, one or more etching processes are performed to remove portions of the active region204in the source/drain regions20to form recesses (not explicitly shown) therein, respectively. A cleaning process may be performed to clean the recesses with a hydrofluoric acid (HF) solution or other suitable solution. Subsequently, one or more epitaxial growth processes are performed to grow epitaxial features in the recesses. Each of the source/drain features may be suitable for a p-type metal-oxide-semiconductor (PMOS) device (e.g., including a p-type epitaxial material) or alternatively, an n-type MOS (NMOS) device (e.g., including an n-type epitaxial material). The p-type epitaxial material may include one or more epitaxial layers of silicon germanium (SiGe), where the silicon germanium is doped with a p-type dopant such as boron, germanium, indium, and/or other p-type dopants. The n-type epitaxial material may include one or more epitaxial layers of silicon (Si) or silicon carbon (SiC), where the silicon or silicon carbon is doped with an n-type dopant such as arsenic, phosphorus, and/or other n-type dopant. In some implementations, each of the epitaxial growth processes may include different in-situ doping levels of suitable dopants. The epitaxial growth processes to form the source/drain features216may include vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), a cyclic deposition and etching (CDE) process, molecular beam epitaxy (MBE), and/or other suitable processes. As shown inFIG.2A, the source/drain feature216is in contact with the channel region10of the active region204. InFIG.2B, in areas outside the active region204, the source/drain feature216is in contact with the second spacer layer214.

Referring toFIGS.1,3A and3B, method100includes a block104where the first spacer layer212and the second spacer layer214on sidewalls of the dummy gate stack206are removed. At block104, in order to make room for a first dummy spacer layer218and a second dummy spacer layer220(to be formed at block106below), the first spacer layer212and the second spacer layer214above the source/drain feature216are substantially removed. A suitable dry etch process or a suitable wet etch process that are selective to the first spacer layer212and the second spacer layer214may be performed at block104to remove the first spacer layer212and the second spacer layer214.

Referring toFIGS.1,4A and4B, method100includes a block106where a first dummy spacer layer218and a second dummy spacer layer220are deposited over the dummy gate stack206. In some embodiments, each of the first dummy spacer layer218and the second dummy spacer layer220may be formed of silicon nitride, hafnium silicide, aluminum oxynitride, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium nitride, silicon carbide, zinc oxide, silicon oxycarbonitride, silicon, yittrium oxide, tantalum carbonitride, zirconium silicide, silicon carbonitride, zirconium aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide. As illustrated inFIG.4A, along the active region204, the first dummy spacer layer218may be disposed on the source/drain feature216, a portion of the channel region10of the active region204, sidewalls of the dummy gate stack206, and a top surface of the hard mask210. As illustrated inFIG.4B, outside the active region204, the first dummy spacer layer218may be disposed on the source/drain feature216, top surfaces of the first spacer layer212and the second spacer layer214, sidewalls of the dummy gate stack206, and a top surface of the hard mask210. As shown inFIGS.4A and4B, the second dummy spacer layer220is disposed on the first dummy spacer layer218. It is noted while the first dummy spacer layer218and the second dummy spacer layer220are formed of a material selected from a similar collection of dielectric materials set forth above, the first dummy spacer layer218and the second dummy spacer layer220have different compositions. The different compositions of the first dummy spacer layer218and the second dummy spacer layer220allow the second dummy spacer layer220to be selectively etched without substantially etching the first dummy spacer layer218. From a top view shown inFIGS.4A and4B, the second dummy spacer layer220is blanketly deposited over the workpiece200. In some embodiments, the first dummy spacer layer218may be formed to a thickness between about 1 nm and about 10 nm and the second dummy spacer layer220may be formed to a thickness between about 1 nm and about 10 nm.

Referring toFIGS.1,5A and5B, method100includes a block108where a top facing portion of the second dummy spacer layer220is removed. At block108, a selective and anisotropic etch process may be performed to remove the second dummy spacer layer220from top-facing surfaces of the workpiece200. As shown inFIGS.5A and5B, the selective etching at block108may leave behind a vertical portion of the second dummy spacer layer220disposed along sidewalls of first dummy spacer layer218disposed along sidewalls of the dummy gate stack206. The etching process at block108may also reduce the thickness of the first dummy spacer layer218on top facing surfaces of the workpiece200.

Referring toFIGS.1,6A and6B, method100includes a block110where a first etch stop layer (ESL)222and a first interlayer dielectric (ILD) layer224are deposited over the workpiece200. The first ESL222and the first ILD layer224are blanketly deposited over the workpiece200, including over the first dummy spacer layer218, over the source/drain features216, and over the sidewalls of the left-over second dummy spacer layer220. In some embodiments, the first ESL222may include semiconductor nitride, such as silicon nitride. In some implementations, the first ILD layer224may include a dielectric material, such as tetraethylorthosilicate (TEOS), un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), other suitable dielectric materials, or combinations thereof. In the depicted embodiment, the first ILD layer224includes an oxide-containing dielectric material. The first ILD layer224may include a multi-layer structure or a single-layer structure and may be formed by a deposition process such as, for example, CVD, flowable CVD (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof.

Referring toFIGS.1,6A and6B, method100includes a block112where the workpiece200is planarized to expose the dummy gate stack206. At block112, a planarization process, such as a chemical mechanical polishing (CMP), may be performed to the workpiece200to remove excess first ESL222, excess first ILD layer224, and the hard mask210over the dummy gate electrode208. As illustrated inFIGS.6A and6B, upon conclusion of the operations at block110, the workpiece200includes a planar top surface where top surfaces of the first ILD layer224, the first ESL222, the first dummy spacer layer218, the second dummy spacer layer220, and the dummy electrode layer208are coplanar.

Referring toFIGS.1,7A and7B, method100includes a block114where the dummy gate stack206is replaced with a gate structure232. In some embodiments, the dummy gate stack206serves as a placeholder for the functional gate structure232and is selectively etched away at block114. In instances where the dummy gate electrode208is formed of polysilicon, an etch process that is selective to the dummy gate electrode208may be used to remove the dummy gate electrode208to expose the channel region10of the active region204. In some embodiments, the gate structure232includes a gate dielectric layer228and a gate electrode230. The gate dielectric layer228may include an interfacial layer on the channel region10of the active region204and one or more high-k dielectric layers (i.e., having a dielectric constant greater than that of silicon oxide, which is about 3.9) over the interfacial layer. In some implementations, the interfacial layer may include silicon oxide and the high-k dielectric layer may include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, the like, or combinations thereof. The interfacial layer functions to enhance adhesion of the high-k dielectric layers to the channel region10of the active region204. The gate electrode230may include at least one work function metal layer and a metal fill layer disposed thereover. Depending on the conductivity type of the semiconductor device200, the work function metal layer may be a p-type or an n-type work function metal layer. Exemplary work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or combinations thereof. The metal fill layer may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or combinations thereof and may be deposited using physical vapor deposition (PVD), CVD, ALD, or other suitable processes. In some embodiments, the gate structure232may further include liners, barrier layers, other suitable layers, or combinations thereof.

Referring toFIGS.1,8A and8B, method100includes a block116where a first self-align contact (SAC) feature226is formed over the gate structure232. In some embodiments, the first ESL222, the second dummy spacer layer220, the first dummy spacer layer218, the gate structure232are selectively etched to form a SAC contact opening (not explicitly shown inFIGS.7A and7B). In some implementations, the selective etching may etch the functional gate structure232at a faster rate, resulting in a T-shaped SAC opening when viewed along the Y direction. A dielectric material is then deposited into the T-shaped SAC opening to form the first SAC feature226, which is also T-shaped when viewed along the Y direction. In some embodiments, the dielectric material may include silicon nitride, hafnium silicide, aluminum oxynitride, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium nitride, silicon carbide, zinc oxide, silicon oxycarbonitride, silicon, yittrium oxide, tantalum carbonitride, zirconium silicide, silicon carbonitride, zirconium aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide. In some instances, the T-shaped first SAC feature226may include a lower portion226L adjacent the gate structure232and an upper portion226U over the lower portion226L. In some implementations illustrated inFIGS.8A and8B, the upper portion226U is disposed over the lower portion226L and top surfaces of the first ESL222, the second dummy space layer220, and the first dummy spacer layer218. The lower portion226L of the first SAC feature226is disposed between the first dummy spacer layers218. In some instances, the upper portion226U may have a thickness along the Z direction between about 1 nm and about 30 nm and the lower portion226L may have a thickness along the Z direction between about 1 nm and about 30 nm. The first SAC feature226may also be referred to as a capping layer226.

Referring still toFIGS.1,8A and8B, method100includes a block118where a source/drain contact236is formed over the source/drain feature216. While not explicitly shown, a source/drain contact opening is formed over a portion of the source/drain feature216to expose such portion of the source/drain feature216. A silicide feature234is then formed over the exposed portion of the source/drain feature216by depositing a metal material over the source/drain feature216and annealing the workpiece200to bring about a silicidation reaction between the metal material and the source/drain feature216. In some instances, the metal material may include titanium (Ti), nickel (Ni), cobalt (Co), tantalum (Ta), or tungsten (W) and the silicide feature234may include titanium silicide, nickel silicide, cobalt silicide, tantalum silicide, tungsten silicide. The silicide feature234functions to reduce contact resistance. After the formation of the source/drain contact openings, source/drain contacts236are deposited in the source/drain contact openings. Each of the source/drain contacts236may be formed of a metal selected from copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), nickel (Ni), other suitable materials, or combinations thereof and deposited using PVD, CVD, ALD, or other suitable processes. After deposition of the source/drain contacts236, the workpiece200is planarized to remove excess metal of the source/drain contacts236over the first ILD layer224such that top surfaces of the source/drain contacts236and the first ILD layer224are coplanar.

Referring toFIGS.1,9A and9B, method100includes a block120where the first ILD layer224is recessed to expose a portion of the first ESL222. In some embodiments, a selective etch process is performed at block120to partially recess the first ILD layer224. In these embodiments, the first ILD layer224is selectively etched using the first SAC feature226and the source/drain contacts236as an etch mask to form the recessed first ILD layer224′. In some implementations illustrated inFIGS.9A and9B, the first ILD layer224is recessed to expose a portion of the sidewalls of the first ESL222. In some instances, because the first ESL222is formed of a material different from that of the first ILD layer224, the first ILD layer224may be selectively recessed at block120without substantially damaging the first ESL222. In some instances, the first ESL22may have a thickness between about 1 nm and about 10 nm.

Referring toFIGS.1,10A and10B, method100includes a block122where the exposed portion of the first ESL222is etched to form a lateral opening237to expose the second dummy spacer layer220. In some embodiments, the etching chemistry of the etch process at block122is selected such that the exposed sidewalls of the first ESL222may be laterally etched without substantially damaging the first SAC feature226and the recessed first ILD layer224. It is noted that the opening237does not extend vertically along the Z direction but rather, it extends horizontally along the X direction. As illustrated inFIG.10B, the opening237is disposed under the upper portion226U of the first SAC feature226. The lateral opening237provides access to the second dummy spacer layer220, allowing it to be selectively removed at block124.

Referring toFIGS.1,11A and11B, method100includes a block124where the second dummy spacer layer220is selectively removed to form an air gap238. Via the opening237formed at block122, the second dummy spacer layer220may be selectively removed to form the air gap238. As described above, the materials of the first dummy spacer layer218and the second dummy spacer layer220are selected such that the second dummy spacer layer220may be selectively removed without substantially etching the first dummy spacer layer218. According to the present disclosure, the materials for the first ESL222and the first SAC feature226are also selected to be different from that of the second dummy spacer layer220such that the air gap238may be formed by removing of the second dummy spacer layer220. As shown inFIGS.11A and11B, the air gap238is defined by the upper portion226U, the first ESL222, and the first dummy spacer layer218and extends under the upper portion226U along Y direction. It can be seen that each gate structure232is disposed between two air gaps238along the X direction and each of the air gap238extend along the Y direction between two openings237. Each of the air gaps238is in fluid communication with the two opening237.

Referring toFIGS.1,12A,12B,13A, and13Bmethod100includes a block126where a seal layer240is deposited to seal the air gap238. In some embodiments, the seal layer240may include silicon nitride, hafnium silicide, aluminum oxynitride, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium nitride, silicon carbide, zinc oxide, silicon oxycarbonitride, silicon, yittrium oxide, tantalum carbonitride, zirconium silicide, silicon carbonitride, zirconium aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide. In some implementations, the seal layer240is deposited using CVD or a suitable deposition technique. It is noted that the material for the seal layer240is selected such that the first ILD layer224and the first SAC feature226may be selectively etched without substantially etching the seal layer240. As will be described below, the seal layer240allows formation of slot source/drain contact vias. As illustrated inFIGS.12A and12B, the seal layer240seals off the air gap238. Even though some of the seal layer240may intrude into the opening237, at least a portion of the opening237may become a part of the air gap238after the seal layer240is deposited.

Reference is still made toFIG.12A. The air gap238is disposed between the first ESL222and a vertical portion of the first dummy spacer layer218along the X direction and is disposed between the upper portion226U of the first SAC feature226and a horizontal portion of the first dummy spacer layer218. The vertical portion of the first dummy spacer layer218extends along sidewalls of the gate structure232and sidewalls of the lower portion226L of the first SAC feature226. The horizontal portion of the first dummy spacer layer218is disposed on the channel region10of the active region204and the source/drain feature216. As shown inFIG.12A, the air gap238is also disposed between the source/drain contact236and the gate structure232as well as between the source/drain contact236and the lower portion226L of the first SAC feature226. The air gap238extends past both ends of the source/drain contact236along the Y direction. Referring toFIG.12B, along section II-II′, the air gap238may include a portion of the opening237and may have an inverse L-shape when viewed along the Y direction. In addition, along section II-II′, the air gap238is defined by the first dummy spacer layer218, the first ESL222, the seal layer240, and the upper portion226U.

Reference is now made toFIGS.13A and13B. In some alternative embodiments, a liner242lines the sidewalls of the source/drain contact236. As illustrated inFIG.13A, the liner242may be disposed between the source/drain contact236and the seal layer240, between the source/drain contact236and the upper portion226U of the first SAC feature226, between the source/drain contact236and the first ESL222, and between the source/drain contact236and the horizontal portion of the first dummy spacer layer218. Because the liner242is not shown along the cross-section liner242is not visible when viewed along the Y direction. In some implementations, the liner242may include silicon nitride, hafnium silicide, aluminum oxynitride, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium nitride, silicon carbide, zinc oxide, silicon oxycarbonitride, silicon, yittrium oxide, tantalum carbonitride, zirconium silicide, silicon carbonitride, zirconium aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide. In some instances, the liner242may have a thickness between about 1 nm and about 10 nm. In some instances, the liner242may be omitted entirely. In instances where the liner242is present, the liner242may be formed to a thickness between about 1 nm and bout 10 nm.

Process variations may bring about various features as a result of the formation of the air gap238according to method100. Some of the examples are shown inFIG.14. In some implementations, the formation of the SAC contact opening at block116may round top edges of the first dummy spacer layer218. The recess of the first ILD layer224at block120may form rounded edges of the upper portion226U of the first SAC feature226. In addition, the recess of the first ILD layer224may form a dip241in the first ILD layer224such that a portion of the seal layer240may be disposed in the dip241of the first ILD layer224. The dip241may have a depth between about 0.1 nm and about 20 nm. In embodiments where the deposition of the seal layer240is carried out using CVD, a void244may be formed in the seal layer240. As illustrated inFIG.14, the air gap238has a first width W1between the first ESL222and the vertical portion of the first dummy spacer layer218, a second width W2between the seal layer240and the first dummy spacer layer218, and a first height H1between the upper portion226U and the horizontal portion of the first dummy spacer layer218. The portion of the air gap238that is disposed between the first ESL222and the vertical portion of the first dummy spacer layer218may be referred to as a bottom portion. The portion of the air gap238that is disposed between the seal layer240and the first dummy spacer layer218may be referred to as a top portion. In some instances, the first width W1may be between about 1 nm and about 10 nm, the second width W2may be between about 2 nm and about 15 nm, and the first height H1may be between about 2 nm and about 80 nm. The first ILD layer224over the first ESL222has a second height H2. In some implementations, the second height H2may be such that the first ILD layer224may be higher or lower than the adjacent first ESLs222. In these implementations, the difference between first ILD layer224and the first ESL222may be about 10 nm. In some instances, the second height H2may be between about 2 nm and about 40 nm. The seal layer240over the first ILD layer224has a third height H3. In some instances, the third height H3may be between about 2 nm and about 30 nm. The void244in the seal layer240may have a fourth height H4between about 0.1 nm and about 10 nm.

Referring toFIGS.1,15,16, and17, method100includes a block128where further processes are performed. Such further processes may include deposition of a second ESL246, deposition of a second ILD layer248, and formation of a source/drain contact via250(including a first source/drain contact via250-1inFIG.15, a second source/drain contact via250-2inFIG.16, and a third source/drain contact via250-3inFIG.17). Reference is first made toFIG.15, where the first source/drain contact via250-1is formed. In some embodiments, after the seal layer240is formed to seal the air gap238, the second ESL246is deposited over the workpiece200and the second ILD layer248is deposited over the second ESL246. A source/drain contact via opening is then formed through the second ESL246and the second ILD layer248to expose the source/drain contact236. Thereafter, a conductive material, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), nickel (Ni), is then deposited in the source/drain contact via opening to form the first source/drain contact via250-1, which is in contact with the source/drain contact236. The second ESL246and the second ILD layer248may be substantially similar to the first ESL222and the first ILD layer224, respectively, in terms of compositions and formation processes.FIG.35AandFIG.35B illustrate, respectively, a top view and a cross-sectional view of a workpiece200where the first source/drain contact vias250-1are formed. It can be seen that adjacent source/drain contacts236are separated along the Y direction by not only the first ILD layer224but also the seal layer240. A plurality of the first source/drain contact vias250-1are then formed through the second ILD layer248and the second ESL246to be in contact with the source/drain contact. As illustrated inFIG.35B, in some implementations, no further SAC layer is formed over the source/drain contacts236.

The second source/drain contact via250-2is illustrated inFIG.16. Different from the first source/drain contact via250-1shown inFIG.15, a top portion of the source/drain contact236is recessed to form a SAC recess and a second SAC feature (not shown inFIG.16but shown inFIG.36B).FIG.36AandFIG.36Billustrate, respectively, a top view and a cross-sectional view of a workpiece200where the second source/drain contact vias250-2are formed. As shown inFIG.36B, a second SAC feature252is formed in the SAC recess formed into the source/drain contact236such that the second SAC feature252is disposed between seal layer240. The second source/drain contact via250-2therefore extends through the second ILD layer248, the second ESL246, and the second SAC feature252to be in contact with the source/drain contact236.

Reference is now made toFIG.17, wherein the third source/drain contact via250-3is formed. In some implementations, the third source/drain contact via250-3is a slot via where more than one contact vias to different source/drain contacts236are formed simultaneously. Similar to formation of the second source/drain contact via250-2, the second ESL246is deposited over the workpiece200and the second ILD layer248is deposited over the second ESL246. A slot opening is then formed by an etch process through the second ESL246and the second ILD layer248to expose at least two neighboring source/drain contacts236. A conductive material, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), nickel (Ni), is then deposited in the slot opening. A planarization process, such as a CMP process, is then used to remove the second ESL246and the second ILD layer248. In some implementations, the material of the seal layer240may be selected such that the etch process for forming the slot opening is selective to the second ESL246and the second ILD layer248. Without the seal layer240, the etch process may indifferently etch the first ILD layer224and the second ILD layer248and a slot via like the third source/drain contact via250-3would not be possible. With the seal layer240of the present disclosure, the etch process does not substantially etch the seal layer240, allowing it to separate adjacent third source/drain contact vias250-3, as illustrated inFIG.37B. Due to formation of the slot opening that spans over two adjacent source/drain contacts236, adjacent third source/drain contact vias250-3are only divided by the seal layer240, as the second SAC feature252between adjacent third source/drain contact vias250-3is substantially removed during the slot opening formation process. Formation of slot vias is one of the measures to form device features or openings beyond the lithography resolution limit. The etching selectivity provided by the seal layer240of the present disclosure help to align the source/drain contact via openings to respective source/drain contacts236. In this sense, a process to form slot vias may be regarded as a self-aligned via formation process.

FIGS.15,16and17illustrate some benefits of the present disclosure. Formation of the first source/drain contact via250-1, the second source/drain contact via250-2, and the third source/drain contact via250-3require formation of source/drain contact via openings over the source/drain contact236. As it is difficult to completely avoid misalignment of masks, the source/drain contact via openings may not always be squarely on the source/drain contact236. By lateral removal of the second dummy spacer layer220, the upper portion226U of the first SAC feature226may be preserved to offer etch selectivity needed to prevent the source/drain contact via opening from breaching into the air gap238or expanding too far toward the gate structure230. As a result, methods of the present disclosure may improve process windows, reduce parasitic capacitance, and increase yield.

Reference is now turned to method300inFIG.18. Method300is described below in conjunction withFIGS.19A,19B,20A,20B,21A,22B,23A,23B,24A,24B,25A,26A,26B,27A,27B,28A,28B,29A,29B,30A,30B, and31-34, each of which illustrate a fragmentary cross-sectional view or a top view of the workpiece200during various operations of method300.

Referring toFIGS.18,19A and19B, method300includes a block302where a workpiece200is received. The workpiece200includes a dummy gate stack206over a channel region10of an active region204, a first spacer layer212over the dummy gate stack206, a second spacer layer214over the first spacer layer212, a source/drain feature216over a source/drain region20of the active region204. The workpiece200includes active region204(or a fin-shaped region204) connected to and arising from the substrate202. The active region204may include one or more channel regions of a multi-gate device. For example, the active region204may be a fin structure of an FinFET or may a stack of alternating epitaxial layers of a gate-all-around (GAA) transistor. The active region204includes a channel region10and a source/drain region20adjacent the channel region10. The channel region10may be disposed between two source/drain regions20. The workpiece200includes a dummy gate stack206that includes a dummy electrode208and a hard mask210. A first gate spacer212is disposed over sidewalls of the dummy gate stack206and a second gate spacer214is disposed on sidewalls of the first gate spacer212. Although not shown inFIG.19A, the dummy gate stack206may also include a dummy gate dielectric layer disposed between the dummy electrode208and the channel region10of the active region204.

Throughout the present disclosure, similar reference numerals are used to denote similar features. As most features on the workpiece200are substantially described above in conjunction with method100, detailed descriptions thereof may be omitted for brevity.

Referring toFIGS.18,20A and20B, method300includes a block304where a portion of the first spacer layer212and the second spacer layer214on sidewalls of the dummy gate stack206are removed. At block304, in order to make room for a third dummy spacer layer219and a second dummy spacer layer220(to be formed at block306below), a portion of the first spacer layer212and the second spacer layer214above the source/drain feature216are substantially removed, leaving behind a thinned first spacer layer212′. A suitable dry etch process or a suitable wet etch process that etches the second spacer layer214faster than the first spacer layer212may be performed at block304to completely remove the second spacer layer214and partially remove the first spacer layer212. The thinned first spacer layer212′ may have a thickness between about 1 nm and about 10 nm.

Referring toFIGS.18,21A and21B, method300includes a block306where a third dummy spacer layer219and a second dummy spacer layer220are deposited over the dummy gate stack206. In some embodiments, each of the third dummy spacer layer219and the second dummy spacer layer220may be formed of silicon nitride, hafnium silicide, aluminum oxynitride, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium nitride, silicon carbide, zinc oxide, silicon oxycarbonitride, silicon, yittrium oxide, tantalum carbonitride, zirconium silicide, silicon carbonitride, zirconium aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide. As illustrated inFIG.21A, along the active region204, the third dummy spacer layer219may be disposed on the source/drain feature216, the thinned first spacer layer212′, and a top surface of the hard mask210. As illustrated inFIG.21B, outside the active region204, the third dummy spacer layer219may be disposed on the source/drain feature216, top surfaces of the second spacer layer214, the thinned first spacer layer212′, and a top surface of the hard mask210. As shown inFIGS.21A and21B, the second dummy spacer layer220is disposed on the third dummy spacer layer219. It is noted while the third dummy spacer layer219and the second dummy spacer layer220are formed of a material selected from a similar collection of dielectric materials set forth above, the third dummy spacer layer219and the second dummy spacer layer220have different compositions. The different compositions of the third dummy spacer layer219and the second dummy spacer layer220allow the second dummy spacer layer220to be selectively etched without substantially etching the third dummy spacer layer219. From a top view shown inFIGS.21A and21B, the second dummy spacer layer220is blanketly deposited over the workpiece200. In some embodiments, the third dummy spacer layer219may be formed to a thickness between about 0.5 nm and about 5 nm and the second dummy spacer layer220may be formed to a thickness between about 1 nm and about 10 nm. Because both the thinned first spacer layer212′ and the third dummy spacer layer219function to protect the dummy gate stack206, the presence of the thinned first spacer layer212′ allows the third dummy spacer layer219to have a reduced thickness. On the contrary, the first dummy spacer layer218, which is formed according to method100, is required to single-handedly protect the dummy gate stack206. Therefore, the thickness of the third dummy spacer layer219is smaller than that of the first dummy spacer layer218.

Referring toFIGS.18,22A and22B, method300includes a block308where a top facing portion of the second dummy spacer layer220is removed. At block308, a selective and anisotropic etch process may be performed to remove the second dummy spacer layer220from top-facing surfaces of the workpiece200. As shown inFIGS.22A and22B, the selective etching at block308may leave behind a vertical portion of the second dummy spacer layer220disposed along sidewalls of third dummy spacer layer219disposed along sidewalls of the thinned first spacer layer212′. The etching process at block308may also reduce the thickness of the third dummy spacer layer219on top facing surfaces of the workpiece200.

Referring toFIGS.18,23A and23B, method300includes a block310where a first etch stop layer (ESL)222and a first interlayer dielectric (ILD) layer224are deposited over the workpiece200. The first ESL222and the first ILD layer224are blanketly deposited over the workpiece200, including over the third dummy spacer layer219, over the source/drain features216, and over the sidewalls of the left-over second dummy spacer layer220. In some embodiments, the first ESL222may include semiconductor nitride, such as silicon nitride. In some implementations, the first ILD layer224may include a dielectric material, such as tetraethylorthosilicate (TEOS), un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), other suitable dielectric materials, or combinations thereof. In the depicted embodiment, the first ILD layer224includes an oxide-containing dielectric material. The first ILD layer224may include a multi-layer structure or a single-layer structure and may be formed by a deposition process such as, for example, CVD, flowable CVD (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof.

Referring toFIGS.18,23A and23B, method300includes a block312where the workpiece200is planarized to expose the dummy gate stack206. At block312, a planarization process, such as a chemical mechanical polishing (CMP), may be performed to the workpiece200to remove excess first ESL222, excess first ILD layer224, and the hard mask210over the dummy gate electrode208. As illustrated inFIGS.23A and23B, upon conclusion of the operations at block310, the workpiece200includes a planar top surface where top surfaces of the first ILD layer224, the first ESL222, the third dummy spacer layer219, the second dummy spacer layer220, the thinned first spacer layer212′, and the dummy electrode layer208are coplanar.

Referring toFIGS.18,24A and24B, method300includes a block314where the dummy gate stack206is replaced with a gate structure232. In some embodiments, the dummy gate stack206serves as a placeholder for the functional gate structure232and is selectively etched away at block314. In instances where the dummy gate electrode208is formed of polysilicon, an etch process that is selective to the dummy gate electrode208may be used to remove the dummy gate electrode208to expose the channel region10of the active region204. In some embodiments, the gate structure232includes a gate dielectric layer228and a gate electrode230. The gate dielectric layer228may include an interfacial layer on the channel region10of the active region204and one or more high-k dielectric layers (i.e., having a dielectric constant greater than that of silicon oxide, which is about 3.9) over the interfacial layer. In some implementations, the interfacial layer may include silicon oxide and the high-k dielectric layer may include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, the like, or combinations thereof. The interfacial layer functions to enhance adhesion of the high-k dielectric layers to the channel region10of the active region204. The gate electrode230may include at least one work function metal layer and a metal fill layer disposed thereover. Depending on the conductivity type of the semiconductor device200, the work function metal layer may be a p-type or an n-type work function metal layer. Exemplary work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or combinations thereof. The metal fill layer may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or combinations thereof and may be deposited using physical vapor deposition (PVD), CVD, ALD, or other suitable processes. In some embodiments, the gate structure232may further include liners, barrier layers, other suitable layers, or combinations thereof.

Referring toFIGS.18,24A and24B, method300includes a block316where a first self-align contact (SAC) feature226is formed over the gate structure232. In some embodiments, the first ESL222, the second dummy spacer layer220, the third dummy spacer layer219, the gate structure232are selectively etched to form a SAC contact opening (not explicitly shown inFIGS.24A and24B). In some implementations, the selective etching may etch the functional gate structure232at a faster rate, resulting in a T-shaped SAC opening when viewed along the Y direction. A dielectric material is then deposited into the T-shaped SAC opening to form the first SAC feature226, which is also T-shaped when viewed along the Y direction. In some embodiments, the dielectric material may include silicon nitride, hafnium silicide, aluminum oxynitride, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium nitride, silicon carbide, zinc oxide, silicon oxycarbonitride, silicon, yittrium oxide, tantalum carbonitride, zirconium silicide, silicon carbonitride, zirconium aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide. In some instances, the T-shaped first SAC feature226may include a lower portion226L adjacent the gate structure232and an upper portion226U over the lower portion226L. In some implementations illustrated inFIGS.25A and25B, the upper portion226U is disposed over the lower portion226L and top surfaces of the first ESL222, the second dummy space layer220, the thinned first spacer layer212′, and the third dummy spacer layer219. The lower portion226L of the first SAC feature226is disposed between the thinned first spacer layers212′. In some instances, the upper portion226U may have a thickness along the Z direction between about 1 nm and about 30 nm and the lower portion226L may have a thickness along the Z direction between about 1 nm and about 30 nm. The first SAC feature226may also be referred to as a capping layer226.

Referring still toFIGS.1,25A and25B, method300includes a block318where a source/drain contact236is formed over the source/drain feature216. While not explicitly shown, a source/drain contact opening is formed over a portion of the source/drain feature216to expose such portion of the source/drain feature216. A silicide feature234is then formed over the exposed portion of the source/drain feature216by depositing a metal material over the source/drain feature216and annealing the workpiece200to bring about a silicidation reaction between the metal material and the source/drain feature216. In some instances, the metal material may include titanium (Ti), nickel (Ni), cobalt (Co), tantalum (Ta), or tungsten (W) and the silicide feature234may include titanium silicide, nickel silicide, cobalt silicide, tantalum silicide, tungsten silicide. The silicide feature234functions to reduce contact resistance. After the formation of the source/drain contact openings, source/drain contacts236are deposited in the source/drain contact openings. Each of the source/drain contacts236may be formed of a metal selected from copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), nickel (Ni), other suitable materials, or combinations thereof and deposited using PVD, CVD, ALD, or other suitable processes. After deposition of the source/drain contacts236, the workpiece200is planarized to remove excess metal of the source/drain contacts236over the first ILD layer224such that top surfaces of the source/drain contacts236and the first ILD layer224are coplanar.

Referring toFIGS.18,26A and26B, method300includes a block320where the first ILD layer224is recessed to expose a portion of the first ESL222. In some embodiments, a selective etch process is performed at block320to partially recess the first ILD layer224. In these embodiments, the first ILD layer224is selectively etched using the first SAC feature226and the source/drain contacts236as an etch mask to form the recessed first ILD layer224′. In some implementations illustrated inFIGS.26A and26B, the first ILD layer224is recessed to expose a portion of the sidewalls of the first ESL222. In some instances, because the first ESL222is formed of a material different from that of the first ILD layer224, the first ILD layer224may be selectively recessed at block320without substantially damaging the first ESL222. In some instances, the first ESL22may have a thickness between about 1 nm and about 10 nm.

Referring toFIGS.18,27A and27B, method100includes a block322where the exposed portion of the first ESL222is etched to form a lateral opening237to expose the second dummy spacer layer220. In some embodiments, the etching chemistry of the etch process at block322is selected such that the exposed sidewalls of the first ESL222may be laterally etched without substantially damaging the first SAC feature226and the recessed first ILD layer224. It is noted that the opening237does not extend vertically along the Z direction but rather, it extends horizontally along the X direction. As illustrated inFIG.27B, the opening237is disposed under the upper portion226U of the first SAC feature226. The lateral opening237provides access to the second dummy spacer layer220, allowing it to be selectively removed at block324.

Referring toFIGS.18,28A and28B, method100includes a block324where the second dummy spacer layer220is selectively removed to form an air gap239. Via the opening237formed at block322, the second dummy spacer layer220may be selectively removed to form the air gap239. As described above, the materials of the third dummy spacer layer219and the second dummy spacer layer220are selected such that the second dummy spacer layer220may be selectively removed without substantially etching the third dummy spacer layer219. According to the present disclosure, the materials for the first ESL222and the first SAC feature226are also selected to be different from that of the second dummy spacer layer220such that the air gap239may be formed by removing of the second dummy spacer layer220. As shown inFIGS.28A and28B, the air gap239is defined by the upper portion226U, the first ESL222, and the third dummy spacer layer219and extends under the upper portion226U along Y direction. It can be seen that each gate structure232is disposed between two air gaps239along the X direction and each of the air gap239extend along the Y direction between two openings237. Each of the air gaps239is in fluid communication with the two opening237.

Referring toFIGS.18,29A,29B,30A, and30Bmethod300includes a block326where a seal layer240is deposited to seal the air gap239. In some embodiments, the seal layer240may include silicon nitride, hafnium silicide, aluminum oxynitride, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium nitride, silicon carbide, zinc oxide, silicon oxycarbonitride, silicon, yittrium oxide, tantalum carbonitride, zirconium silicide, silicon carbonitride, zirconium aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide. In some implementations, the seal layer240is deposited using CVD or a suitable deposition technique. It is noted that the material for the seal layer240is selected such that the first ILD layer224and the first SAC feature226may be selectively etched without substantially etching the seal layer240. As will be described below, the seal layer240allows formation of slot source/drain contact vias. As illustrated inFIGS.29A and29B, the seal layer240seals off the air gap239. Even though some of the seal layer240may intrude into the opening237, at least a portion of the opening237may become a part of the air gap239after the seal layer240is deposited.

Reference is still made toFIG.29A. The air gap239is disposed between the first ESL222and a vertical portion of the third dummy spacer layer219along the X direction and is disposed between the upper portion226U of the first SAC feature226and a horizontal portion of the third dummy spacer layer219along the Z direction. The vertical portion of the third dummy spacer layer219extends along sidewalls of the thinned first spacer layer212′. The horizontal portion of the third dummy spacer layer219is disposed on a horizontal portion of the thinned first spacer layer212′ and the source/drain feature216. The vertical portion of the third dummy spacer layer219is disposed between the thinned first spacer layer212′ and the air gap239along the X direction. As shown inFIG.29A, the air gap239is also disposed between the source/drain contact236and the gate structure232as well as between the source/drain contact236and the lower portion226L of the first SAC feature226. The air gap239extends past both ends of the source/drain contact236along the Y direction. Referring toFIG.29B, along section II-II′, the air gap239may include a portion of the opening237and may have an inverse L-shape when viewed along the Y direction. In addition, along section II-II′ the air gap239is defined by the third dummy spacer layer219, the first ESL222, the seal layer240, and the upper portion226U.

Reference is now made toFIGS.30A and30B. In some alternative embodiments, a liner242lines the sidewalls of the source/drain contact236. As illustrated inFIG.30A, the liner242may be disposed between the source/drain contact236and the seal layer240, between the source/drain contact236and the upper portion226U of the first SAC feature226, between the source/drain contact236and the first ESL222, and between the source/drain contact236and the horizontal portion of the third dummy spacer layer219. Because the liner242is not shown along the cross-section liner242is not visible when viewed along the Y direction inFIG.30B. In some implementations, the liner242may include silicon nitride, hafnium silicide, aluminum oxynitride, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium nitride, silicon carbide, zinc oxide, silicon oxycarbonitride, silicon, yittrium oxide, tantalum carbonitride, zirconium silicide, silicon carbonitride, zirconium aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide. In some instances, the liner242may have a thickness between about 1 nm and about 10 nm. In some instances, the liner242may be omitted entirely. In instances where the liner242is present, the liner242may be formed to a thickness between about 1 nm and bout 10 nm.

Process variations may bring about various features as a result of the formation of the air gap239according to method300. Some of the examples are shown inFIG.31. In some implementations, the formation of the SAC contact opening at block316may round top edges of the thinned first spacer layer212′ and the third dummy spacer layer219. Because the etching process to form the SAC contact opening may have different etch rates for the thinned first spacer layer212′ and the third dummy spacer layer219, the top surfaces of the thinned first spacer layer212′ and the third dummy spacer layer219may not be smooth and continuous. The recess of the first ILD layer224at block320may form rounded edges of the upper portion226U of the first SAC feature226. In addition, the recess of the first ILD layer224may form a dip241in the first ILD layer224such that a portion of the seal layer240may be disposed in the dip241of the first ILD layer224. The dip241may have a depth between about 0.1 nm and about 20 nm. In embodiments where the deposition of the seal layer240is carried out using CVD, a void244may be formed in the seal layer240. As illustrated inFIG.31, the air gap239has a first width W1between the first ESL222and the vertical portion of the third dummy spacer layer219, a second width W2between the seal layer240and the third dummy spacer layer219, and a fifth height H5between the upper portion226U and the horizontal portion of the third dummy spacer layer219. The portion of the air gap239that is disposed between the first ESL222and the vertical portion of the third dummy spacer layer219may be referred to as a bottom portion. The portion of the air gap238that is disposed between the seal layer240and the third dummy spacer layer219may be referred to as a top portion. In some instances, the first width W1may be between about 1 nm and about 10 nm, the second width W2may be between about 2 nm and about 15 nm, and the fifth height H5may be between about 12 nm and about 60 nm. Because the difference in thicknesses of the first dummy spacer layer218and the third dummy spacer layer219, the fifth height H5of the air gap239may be different from the first height H1of the air gap238. In some instances, the fifth height H5is greater than the first height H1. The first ILD layer224over the first ESL222has a second height H2. In some implementations, the second height H2may be such that the first ILD layer224may be higher or lower than the adjacent first ESLs222. In these implementations, the difference between first ILD layer224and the first ESL222may be about 10 nm. In some instances, the second height H2may be between about 2 nm and about 40 nm. The seal layer240over the first ILD layer224has a third height H3. In some instances, the third height H3may be between about 2 nm and about 30 nm. The void244in the seal layer240may have a fourth height H4between about 0.1 nm and about 10 nm.

Referring toFIGS.18,32,33, and34, method300includes a block328where further processes are performed. Such further processes may include deposition of a second ESL246, deposition of a second ILD layer248, and formation of a source/drain contact via250(including a first source/drain contact via250-1inFIG.32, a second source/drain contact via250-2inFIG.33, and a third source/drain contact via250-3inFIG.34). Reference is first made toFIG.32, where the first source/drain contact via250-1is formed. In some embodiments, after the seal layer240is formed to seal the air gap239, the second ESL246is deposited over the workpiece200and the second ILD layer248is deposited over the second ESL246. A source/drain contact via opening is then formed through the second ESL246and the second ILD layer248to expose the source/drain contact236. Thereafter, a conductive material, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), nickel (Ni), is then deposited in the source/drain contact via opening to form the first source/drain contact via250-1, which is in contact with the source/drain contact236. The second ESL246and the second ILD layer248may be substantially similar to the first ESL222and the first ILD layer224, respectively, in terms of compositions and formation processes.FIG.35AandFIG.35B illustrate, respectively, a top view and a cross-sectional view of a workpiece200where the first source/drain contact vias250-1are formed. It can be seen that adjacent source/drain contacts236are separated along the Y direction by not only the first ILD layer224but also the seal layer240. A plurality of the first source/drain contact vias250-1are then formed through the second ILD layer248and the second ESL246to be in contact with the source/drain contact. As illustrated inFIG.35B, in some implementations, no further SAC layer is formed over the source/drain contacts236.

The second source/drain contact via250-2is illustrated inFIG.33. Different from the first source/drain contact via250-1shown inFIG.32, a top portion of the source/drain contact236is recessed to form a SAC recess and a second SAC feature (not shown inFIG.33but shown inFIG.36B).FIG.36AandFIG.36Billustrate, respectively, a top view and a cross-sectional view of a workpiece200where the second source/drain contact vias250-2are formed. As shown inFIG.36B, a second SAC feature252is formed in the SAC recess that extends into the source/drain contact236such that the second SAC feature252is disposed between seal layer240. The second source/drain contact via250-2therefore extends through the second ILD layer248, the second ESL246, and the second SAC feature252to be in contact with the source/drain contact236. Adjacent second source/drain contact vias250-2are separated by the seal layer240and the second SAC feature252.

Reference is now made toFIG.34, wherein the third source/drain contact via250-3is formed. In some implementations, the third source/drain contact via250-3is a slot via where more than one contact vias to different source/drain contacts236are formed simultaneously. Similar to formation of the second source/drain contact via250-2, the second ESL246is deposited over the workpiece200and the second ILD layer248is deposited over the second ESL246. A slot opening is then formed by an etch process through the second ESL246and the second ILD layer248to expose at least two neighboring source/drain contacts236. A conductive material, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), nickel (Ni), is then deposited in the slot opening. A planarization process, such as a CMP process, is then used to remove the second ESL246and the second ILD layer248. In some implementations, the material of the seal layer240may be selected such that the etch process for forming the slot opening is selective to the second ESL246and the second ILD layer248. Without the seal layer240, the etch process may indifferently etch the first ILD layer224and the second ILD layer248and a slot via like the third source/drain contact via250-3would not be possible. With the seal layer240of the present disclosure, the etch process does not substantially etch the seal layer240, allowing it to separate adjacent third source/drain contact vias250-3, as illustrated inFIG.37B. Due to formation of the slot opening that spans over two adjacent source/drain contacts236, adjacent third source/drain contact vias250-3are only divided by the seal layer240, as the second SAC feature252between adjacent third source/drain contact vias250-3is substantially removed during the slot opening formation process. Because the seal layer240is denser (less porous) than the first ILD layer224, the use of the seal layer240to separate contact vias may prevent time-dependent dielectric breakdown (TDDB). Formation of slot vias is one of the measures to form device features or openings beyond the lithography resolution limit. The etching selectivity provided by the seal layer240of the present disclosure help to align the source/drain contact via openings to respective source/drain contacts236. In this sense, a process to form slot vias may be regarded as a self-aligned via formation process.

FIGS.32,33and34illustrate some benefits of the present disclosure. Formation of the first source/drain contact via250-1, the second source/drain contact via250-2, and the third source/drain contact via250-3require formation of source/drain contact via openings over the source/drain contact236. As it is difficult to completely avoid misalignment of masks, the source/drain contact via openings may not always be squarely on the source/drain contact236. By lateral removal of the second dummy spacer layer220, the upper portion226U of the first SAC feature226may be preserved to offer etch selectivity needed to prevent the source/drain contact via opening from breaching into the air gap239or expanding too far toward the gate structure230. As a result, methods of the present disclosure may improve process windows, reduce parasitic capacitance, and increase yield.

Although not intended to be limiting, one or more embodiments of the present disclosure provide benefits. For example, the present disclosure provides embodiments of semiconductor devices where air gaps between a gate structure and a source/drain contact may be formed without compromising a capping layer or a SAC feature on the gate structure. When viewed along the lengthwise direction of the gate structure, the SAC feature over the gate structure is substantially T-shaped and the air gaps formed according to the present disclosure are at least partially disposed under a portion of the T-shaped SAC feature. This structure is made possible by formation of lateral openings and lateral removal of a dummy spacer layer. The air gaps are sealed with a seal layer that is different from an adjacent ILD layer in terms of materials and etching selectivity. Such a seal layer allows formation of slot vias. Because the process for forming slot vias has a greater process window than the process for forming individual vias, the use of seal layers in the present disclosure improves the process window.

Thus, in one embodiment, a semiconductor device is provided. The semiconductor device includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

In some embodiments, the semiconductor device may further include a first gate spacer layer and an etch stop layer. The air gap is disposed between the first gate spacer layer and the etch stop layer along the first direction, the first gate spacer layer is disposed between the gate structure and the air gap along the first direction, and the etch stop layer is disposed between the air gap and the source/drain contact along the first direction. In some implementations, the first gate spacer layer includes silicon nitride, hafnium silicide, aluminum oxynitride, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium nitride, silicon carbide, zinc oxide, silicon oxycarbonitride, silicon, yittrium oxide, tantalum carbonitride, zirconium silicide, silicon carbonitride, zirconium aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide. In some instances, the gate structure extends from the channel region along a second direction perpendicular to the first direction and the air gap is disposed between the upper portion of the dielectric feature and the first gate spacer layer along the second direction. In some implementations, the gate structure extends from the channel region along a second direction perpendicular to the first direction and the etch stop layer is disposed between the upper portion of the dielectric feature and the first gate spacer layer along the second direction. In some embodiments, the semiconductor device may further include a liner layer disposed between the source/drain contact and the etch stop layer along the first direction. In some implementations, the semiconductor device may further include a second gate spacer layer disposed between the first gate spacer layer and the gate structure along the first direction. In some embodiments, a portion of the first gate spacer layer is disposed over the second gate spacer layer.

In another embodiment, a semiconductor device is provided. The semiconductor device includes a gate structure, a first gate spacer layer extending along a sidewall of the gate structure, a source/drain feature adjacent the gate structure, a seal layer over source/drain feature, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed below the upper portion of the dielectric feature. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed between the seal layer and the first gate spacer layer along the first direction.

In some embodiments, the seal layer is in contact with the upper portion of the dielectric feature. In some implementations, the semiconductor device may further include an etch stop layer over the source/drain feature and the air gap extends between the etch stop layer and the first gate spacer layer. In some embodiments, a portion of the air gap is directly over a portion of the etch stop layer. In some instances, the first gate spacer layer includes a horizontal portion disposed on the source/drain feature and the etch stop layer is disposed over the horizontal portion of the first gate spacer layer. In some embodiments, the semiconductor device may further include an interlayer dielectric layer disposed over the etch stop layer and the seal layer is disposed over the interlayer dielectric layer.

In yet another embodiment, a method is provided. The method includes receiving a workpiece including active region that includes a channel region and a source/drain feature adjacent the channel region, forming a dummy gate stack over the channel region, forming a first dummy spacer layer over the dummy gate stack and the source/drain feature, forming a second dummy spacer layer over the first dummy spacer layer and the source/drain feature, recessing the second dummy spacer layer to expose top-facing surfaces of the first dummy spacer layer while sidewalls of the first dummy spacer layer remain covered by the second dummy spacer layer, depositing an etch stop layer over the first dummy spacer layer and the second dummy spacer layer, depositing an interlayer dielectric layer over the etch stop layer, replacing the dummy gate stack with a gate structure, recessing the gate structure, the first dummy spacer layer, the second dummy spacer layer, and the etch stop layer to form a self-aligned contact (SAC) opening, forming a dielectric feature in the SAC opening, forming a contact feature extending through the etch stop layer, the interlayer dielectric layer, and the first dummy spacer layer to be in contact with the source/drain feature, selectively recessing the interlayer dielectric layer and the etch stop layer without substantially etching the dielectric feature and the contact feature to form an opening adjacent the contact feature and to expose a portion of the second dummy spacer layer, and selectively removing the second dummy spacer layer to form an air gap.

In some embodiments, the forming of the dielectric feature includes forming a lower portion of the dielectric feature on the gate structure and an upper portion of the dielectric feature over the lower portion, the first dummy spacer layer, the second dummy spacer layer and the air gap is disposed below an upper portion of the dielectric feature. In some embodiments, the method may further include after the selectively removing of the second dummy spacer layer, depositing a seal layer over the interlayer dielectric layer. The seal layer is in contact with the upper portion of the dielectric feature. In some implementations, the active region extends lengthwise along a first direction, a bottom portion of the air gap is disposed between the etch stop layer and the first dummy spacer layer along the first direction, and a top portion of the air gap is disposed between the seal layer and the first dummy spacer layer along the first direction. In some instances, the gate structure extends lengthwise along a second direction perpendicular to the first direction and the air gap extends across an entire length of the contact feature along the second direction. In some embodiments, the gate structure extends from the channel region along a third direction perpendicular to the first direction and the second direction and the air gap is disposed between the upper portion of the dielectric feature and the first dummy spacer layer along the third direction.