Systems and methods for fault-resilient system management random access memory

A method may include, during a PEI phase BIOS, responsive to a flag being set in a previous boot session of an information handling system to test a first designated region of a memory of the information handling system: testing the first designated region for a memory fault; in response to detecting the memory fault, mapping out the first designated region and designating an additional region of the memory as a designated region for SMRAM and repeating testing of additional designated regions, mapping out of failed additional designated regions, and designating new additional regions of the memory until a designated region passes testing without memory fault; and in response to detecting passage of testing without memory fault of a designated region comprising either of the first designated region or an additional region of the memory, configuring the designated region for use as the SMRAM for the information handling system.

TECHNICAL FIELD

The present disclosure relates in general to information handling systems, and more particularly to methods and systems for ensuring fault-resilience in a system management random access memory (SMRAM) in an information handling system.

BACKGROUND

Self-healing and proactive remediation of memory regions is often desirable in response to faults occurring in memory. However, existing approaches to performing self-healing and proactive remediation in SMRAM are lacking. Accordingly, faults occurring in SMRAM may lead at first to slower boot times as portions of SMRAM with faults are remediated through standard cyclic-redundancy checks, and eventually lead to boot failures of a basic input/output system when faults are no longer correctable with cyclic-redundancy checks. Boot failures can lead to significant downtime, as they often require replacement of a memory module (e.g., a dual-inline memory module) in order to again enable successful boot. Accordingly, methods and systems for enabling self-healing and proactive remediation of SMRAM are desirable.

SUMMARY

In accordance with the teachings of the present disclosure, the disadvantages and problems associated with remediating memory faults in SMRAM may be reduced or eliminated.

In accordance in with embodiments of the present disclosure, an information handling system may include a processor, a memory communicatively coupled to the processor, and a basic input/output system communicatively coupled to the processor and comprising a program of executable instructions configured to, during a Pre-Extensible Firmware Interface Initialization (PEI) phase of the basic input/output system, responsive to a flag being set in a previous boot session to test a first designated region of the memory for System Management Random Access Memory (SMRAM): test the first designated region for a memory fault; in response to detecting the memory fault, map out the first designated region and designate an additional region of the memory as a designated region for SMRAM and repeat testing of additional designated regions, mapping out of failed additional designated regions, and designating new additional regions of the memory until a designated region passes testing without memory fault; and in response to detecting passage of testing without memory fault of a designated region comprising either of the first designated region or an additional region of the memory, configure the designated region for use as the SMRAM for the information handling system.

In accordance in with these and other embodiments of the present disclosure, a method may include, during a Pre-Extensible Firmware Interface Initialization (PEI) phase of a basic input/output system of an information handling system, responsive to a flag being set in a previous boot session of the information handling system to test a first designated region of a memory of the information handling system, the first designated region to be used for System Management Random Access Memory (SMRAM): testing the first designated region for a memory fault; in response to detecting the memory fault, mapping out the first designated region and designating an additional region of the memory as a designated region for SMRAM and repeating testing of additional designated regions, mapping out of failed additional designated regions, and designating new additional regions of the memory until a designated region passes testing without memory fault; and in response to detecting passage of testing without memory fault of a designated region comprising either of the first designated region or an additional region of the memory, configuring the designated region for use as the SMRAM for the information handling system.

In accordance in with these and other embodiments of the present disclosure, an article of manufacture may include a non-transitory computer-readable medium and computer-executable instructions carried on the computer-readable medium, the instructions readable by a processor, the instructions, when read and executed, for causing the processor to, during a Pre-Extensible Firmware Interface Initialization (PEI) phase of a basic input/output system of an information handling system, responsive to a flag being set in a previous boot session of the information handling system to test a first designated region of a memory of the information handling system, the first designated region to be used for System Management Random Access Memory (SMRAM): test the first designated region for a memory fault; in response to detecting the memory fault, map out the first designated region and designate an additional region of the memory as a designated region for SMRAM, and repeat testing of additional designated regions, mapping out of failed additional designated regions, and designating new additional regions of the memory until a designated region passes testing without memory fault; and in response to detecting passage of testing without memory fault of a designated region comprising either of the first designated region or an additional region of the memory, configuring the designated region for use as the SMRAM for the information handling system.

DETAILED DESCRIPTION

Preferred embodiments and their advantages are best understood by reference toFIGS.1and2, wherein like numbers are used to indicate like and corresponding parts.

FIG.1illustrates a block diagram of an example information handling system102, in accordance with embodiments of the present disclosure. In some embodiments, an information handling system102may comprise a personal computer. In some embodiments, an information handling system102may comprise or be an integral part of a server. In other embodiments, an information handling system102may comprise a portable information handling system (e.g., a laptop or notebook, etc.). As depicted inFIG.1, an information handling system102may include a processor103, a memory104communicatively coupled to processor103, a BIOS105communicatively coupled to processor103, and a network interface108communicatively coupled to processor103.

As shown inFIG.1, memory104may include a portion of memory designated as SMRAM106. SMRAM106may be used by a System Management Mode (SMM) of information handling system102. SMM is a special-purpose operating mode provided for information handling system-wide functions such as power management, system hardware control, or proprietary vendor-designed code. It is typically intended for use only by system firmware (a basic input/output system), but not by applications software or general-purpose systems software. SMM may offer a distinct and easily-isolated processor environment that operates transparently to the operating system or executive and software applications.

In order to achieve transparency, SMM imposes certain rules. For example, SMM may typically only be entered through a System Management Interrupt (SMI). Processor103may execute SMM code in a separate address space of memory104(i.e., SMRAM106) that may be configured by system firmware to be inaccessible to other operating modes of processor103.

BIOS105may include any system, device, or apparatus configured to identify, test, and/or initialize information handling resources of information handling system102, and/or initialize interoperation of information handling system102with other information handling systems. “BIOS” may broadly refer to any system, device, or apparatus configured to perform such functionality, including without limitation, a Unified Extensible Firmware Interface (UEFI). In some embodiments, BIOS105may be implemented as a program of instructions that may be read by and executed on processor103to carry out the functionality of BIOS105. In these and other embodiments, BIOS105may comprise boot firmware configured to be the first code executed by processor103when information handling system102is booted and/or powered on. As part of its initialization functionality, code for BIOS105may be configured to set components of information handling system102into a known state, so that one or more applications (e.g., an operating system or other application programs) stored on compatible media (e.g., disk drives) may be executed by processor103and given control of information handling system102.

Network interface108may comprise any suitable system, apparatus, or device operable to serve as an interface between information handling system102and one or more other information handling systems via an in-band management network. Network interface108may enable information handling system102to communicate using any suitable transmission protocol and/or standard. In these and other embodiments, network interface108may comprise a network interface card, or “NIC.” In some embodiments, network interface108may comprise a 10 gigabit Ethernet network interface. In these and other embodiments, network interface108may be enabled as a local area network (LAN)-on-motherboard (LOM) card. Network interface108may be configured to communicate via wire-line transmissions, wireless transmission, or both.

In addition to processor103, memory104, BIOS105, and network interface108, information handling system102may include one or more other information handling resources.

In operation, BIOS105may be configured, during a Pre-EFI Initialization (PEI) phase of the execution of BIOS105, and before configuration of SMRAM106, to perform testing, self-healing, and remediation of SMRAM106, as described in greater detail below with respect toFIG.2.

FIG.2illustrates a flowchart of an example method200for ensuring fault-resilience in SMRAM106, in accordance with embodiments of the present disclosure. According to certain embodiments, method200may begin at step202. As noted above, teachings of the present disclosure may be implemented in a variety of configurations of information handling system102. As such, the preferred initialization point for method200and the order of the steps comprising method200may depend on the implementation chosen.

At step202, upon restart, reset, or other initialization of information handling system102, BIOS105may begin execution, including execution within the PEI phase. At step204, during the PEI phase, BIOS105may determine if a flag to test SMRAM106was set during a previous boot session of information handling system102. For example, in some embodiments, such a flag may be set in response to memory diagnostics tests being executed during the previous boot session, either on-demand (e.g., by a user) or by an automatic process such as a diagnostics program. As another example, in these and other embodiments, such a flag may be set in response to execution of an SMI exception handler (e.g., when a check occurs due to a memory fault) during the previous boot session. If the flag is set, method200may proceed to step206. Otherwise method200may proceed to step222.

At step206, in response to the flag being set, BIOS105may, during the PEI phase, test the region of memory104designated for use by SMRAM106. At step208, BIOS105may, during the PEI phase, determine if the test indicated a fault or failure of the designated region for SMRAM106. If a fault or failure is detected, method200may proceed to step210. Otherwise, method200may proceed to step216.

At step210, in response to a fault or failure of the designated region, BIOS105may, during the PEI phase, increment an SMRAM failure count stored in a non-volatile memory associated with or otherwise accessible to BIOS105. In addition, at step212, BIOS105may, during the PEI phase, map out the failed designated region so that such region may not ever be used again by BIOS105or an operating system of information handling system102. Further, at step214, BIOS105may, during the PEI phase, choose and designate another region for SMRAM106. After completion of step214, method200may proceed again to step208, at which BIOS105may test the newly-designated region.

At step216, in response to the designated region of memory104passing the test, BIOS105may, during the PEI phase, configure the designated region of memory104that passed the test for use as SMRAM106.

At step218, BIOS105may, during the PEI phase, determine if the SMRAM failure count has reached a threshold level. If the threshold level has been reached, method200may proceed to step220. Otherwise, method200may proceed to step222.

At step220, if response to the threshold level for the SMRAM failure count being reached, BIOS105may trigger a process to have a replacement memory module delivered to a user (e.g., administrator, owner, end user, etc.) of information handling system102, such that the user may install the replacement memory module within information handling system102in place of an existing memory module of memory104.

At step222, BIOS105may complete its execution, and information handling system102may complete its boot process. After completion of step222, method200may end.

AlthoughFIG.2discloses a particular number of steps to be taken with respect to method200, it may be executed with greater or fewer steps than those depicted inFIG.2. In addition, althoughFIG.2discloses a certain order of steps to be taken with respect to method200, the steps comprising method200may be completed in any suitable order.

Method200may be implemented using information handling system102, components thereof or any other system operable to implement method200. In certain embodiments, method200may be implemented partially or fully in software and/or firmware embodied in computer-readable media.