Manufacturing method of gallium nitride substrate

A method of manufacturing a gallium nitride substrate, the method including forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein; forming a second buffer layer on the first buffer layer such that the second buffer layer has one or more holes therein; and forming a GaN layer on the second buffer layer, wherein the one or more holes of the first buffer layer are filled by the second buffer layer.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2016-0171563, filed on Dec. 15, 2016, in the Korean Intellectual Property Office, and entitled: “Manufacturing Method of Gallium Nitride Substrate,” is incorporated by reference herein in its entirety.

BACKGROUND

Embodiments relate to a manufacturing method of a gallium nitride substrate.

2. Description of the Related Art

Gallium nitride (GaN) is a material that is useful for fabricating a light emitting element having a short wavelength region (as a wide bandgap semiconductor material that has bandgap energy of about 3.39 eV and is a direct transition type).

SUMMARY

The embodiments may be realized by providing a method of manufacturing a gallium nitride substrate, the method including forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein; forming a second buffer layer on the first buffer layer such that the second buffer layer has one or more holes therein; and forming a GaN layer on the second buffer layer, wherein the one or more holes of the first buffer layer are filled by the second buffer layer.

The embodiments may be realized by providing a method of manufacturing a gallium nitride substrate, the method including forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein; forming a silicon nitride region on the silicon substrate exposed by the one or more holes; and forming a GaN layer on the first buffer layer.

The embodiments may be realized by providing a method of manufacturing a gallium nitride substrate, the method including forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein; forming a silicon nitride region on the silicon substrate exposed by the one or more holes; forming a second buffer layer on the first buffer layer such that the second buffer layer has one or more holes therein; forming an insulating layer pattern at an edge of an upper surface of the second buffer layer; forming a GaN layer on the second buffer layer and the insulating layer pattern; and removing the insulating layer pattern.

The embodiments may be realized by providing a method of manufacturing a gallium nitride substrate, the method including providing a silicon substrate; forming a first buffer layer on the silicon substrate such that the first buffer layer includes at least one hole therethrough exposing a portion of the silicon substrate; forming a barrier at the at least one hole in the first buffer layer; forming a GaN layer on the first buffer layer such that the GaN layer is physically separated from the silicon of the silicon substrate; and separating the GaN layer.

DETAILED DESCRIPTION

Hereinafter, a method of manufacturing a gallium nitride substrate according to an exemplary embodiment will be described in detail with reference to the accompanying drawings.

FIG. 1illustrates a cross-sectional view of stages in a manufacturing process of a gallium nitride substrate according to an exemplary embodiment.

Referring to part (a) ofFIG. 1, first, a substrate110may be prepared. The substrate110may be a silicon substrate.

The silicon substrate110may be a substrate that is most widely used in a general semiconductor process and may have features that the price is low, a large wafer may be fabricated, and thermal conductivity may be excellent. In an implementation, a surface orientation of the silicon substrate110formed with a buffer layer and the like may be {111}. A surface of the silicon substrate110having the surface orientation of {111} may have a lattice constant of about 3.8403 Å. A surface of the silicon substrate110having a surface orientation of {100} may have a lattice constant of about 5.40 Å. Accordingly, when considering that the lattice constant of gallium nitride is about 3.189 Å, the surface orientation of the silicon substrate110may be {111}.

The silicon substrate110may have a thickness of 100 μm to 1,000 μm. A diameter of the gallium nitride substrate may be determined according to a diameter of the silicon substrate110, and a large-area silicon substrate110may be used for manufacturing a large-area gallium nitride substrate. In an implementation, the silicon substrate110may have a diameter of 6 inches to 18 inches.

Next, referring to part (b) ofFIG. 1, a first buffer layer121may be formed on the silicon substrate110. The first buffer layer121may include a material having a small difference in lattice constant from a GaN layer140(to be grown in a subsequent process). The first buffer layer121may be included to help reduce and/or prevent melt back. Melt back is a phenomenon in which when GaN is grown on the silicon substrate110, if the silicon and the GaN were to directly contact each other, a phenomenon in which the silicon is diffused into the GaN to etch the surface of the silicon substrate110could occur.

For example, the first buffer layer121may help reduce a crystal defect, which could otherwise be generated due to differences in lattice constant mismatch and thermal expansion coefficient between the GaN layer140and the silicon substrate110while the GaN layer140is formed on the silicon substrate110. The first buffer layer121may help remove or compensate for stress caused in the GaN layer140and help prevent cracks from being generated in the GaN layer140, help prevent melt-back etching by a chemical action of the silicon substrate110, and help prevent Ga atoms of the GaN layer140from penetrating into the silicon substrate110.

In an implementation, the first buffer layer121may include, e.g., AlN, TaN, TiN, HfN or HfTi. In an implementation, a material of the first buffer layer121may be selected with a view toward preventing Ga atoms from contacting the silicon substrate110, and may not include Ga.

The first buffer layer121may be formed by, e.g., a hydride vapor phase epitaxy (HVPE) method or a metal organic chemical vapor deposition (MOCVD) method.

In the case where the first buffer layer121is AlN, the first buffer layer121may be formed by the following method as an example. First, an Al coating layer may be formed on the silicon substrate110using (e.g., providing) a trimethyl aluminum (TMAl) source at a high temperature (e.g., 1,000° C. to 1,200° C.). Next, at a temperature of 1,000° C. to 1,200° C. and under a hydrogen atmosphere, NH3may react with the Al coating layer by flowing NH3on an upper surface of the silicon substrate110(e.g., on the Al coating layer) to form an aluminum nitride (AlN) layer. The formed aluminum nitride layer may be the first buffer layer121.

In an implementation, the first buffer layer121may be formed by other suitable methods.

The first buffer layer121may have a thickness of, e.g., 5 nm to 10 μm. In an implementation, the first buffer layer121may have a thickness of, e.g., 500 nm to 1.5 μm.

In the process of forming the first buffer layer121, if contaminants or foreign particles11are present in a deposition chamber, the first buffer layer121may not formed on (e.g., portions of) the surface of the silicon substrate110. The foreign particles11may include, e.g., inorganic particles such as gallium particles in the deposition chamber1000. For example, in the process of depositing the GaN layer140and the like in the deposition chamber1000, some Ga particles could remain as contaminants in the chamber without being deposited on the substrate. If the residual foreign particles11were to find their way onto the silicon substrate110in the process of depositing the first buffer layer121, the first buffer layer121could not deposited on the surface of the silicon substrate110(e.g., where the foreign particle11is on the silicon substrate110). In an implementation, the size of the particle11may be, e.g., 10 nm to 1000 nm.

Referring to part (b) ofFIG. 1, in a region where the particles11are positioned, sources could be concentrated in the particles11and thus the silicon substrate10around the particles11may not be covered by the first buffer layer121, but rather may remain exposed. For example, the first buffer layer121may include at least one hole21, e.g., a plurality of holes21, exposing the silicon substrate110.

FIG. 2illustrates an image when the silicon substrate is not covered by foreign particles in an actual depositing process. Part (a) ofFIG. 2illustrates an image in which holes where the buffer layer is not formed are formed around or at the particles in the process of depositing the buffer layer by positioning the particles. Part (b) ofFIG. 2illustrates an image in which the silicon substrate is exposed by the holes of the buffer layer after the particles are removed.

In the region where the silicon substrate110is not covered by the first buffer layer121and remains exposed, in a subsequent process of depositing the GaN layer140, the silicon and the Ga source could meet and thus a melt back phenomenon could occur. The melt back could occur where the silicon and the GaN directly contact each other when the GaN is grown on the silicon substrate110to cause breakage and the like in the formed GaN layer140.

The buffer layer and the like may be formed therebetween (e.g., between the silicon substrate110and the GaN layer) to help prevent the silicon substrate110and the GaN layer140from directly contacting each other. Even when the buffer layer is formed, a region where the buffer layer is not formed or is incompletely formed (e.g., due to the presence of the foreign particles11in the deposition chamber1000as described above) may be generated. Thus, the melt back phenomenon may not be completely prevented.

In an implementation, after the first buffer layer121is formed, the particles11may be removed by physically cleaning the first buffer layer121, and a second buffer layer122may be formed on the first buffer layer121to help prevent the melt back phenomenon from occurring.

For example, referring to part (c) ofFIG. 1, the first buffer layer121may be physically cleaned. For example, the physical cleaning may be performed in the cleaning apparatus2000outside the deposition chamber1000. For example, forming the first buffer layer121may be performed in the deposition chamber1000, and the physical cleaning may be performed by a separate process in the cleaning apparatus2000after the silicon substrate110with the first buffer layer121is taken out of the deposition chamber1000.

The physical cleaning may include, e.g., nano spray or ultrasonic wave cleaning. The nano spray is a method of spraying water onto the substrate using a nano spray apparatus to clean the substrate. The ultrasonic wave cleaning is a method of cleaning the substrate by applying high-frequency vibration energy to a liquid as a technique of using a cavitation effect and a particle acceleration effect of ultrasound for cleaning. As such, the cleaning of the first buffer layer121according to the exemplary embodiment may be physically performed by using water and may not include a separate chemical cleaning process. For example, the particles on the first buffer layer121may be inorganic particles, e.g., Ga particles, rather than organic particles. Inorganic particles may not be removed well by a chemical cleaning of simply using a cleaning solution or the like, and may need to be physically cleaned by using physical pressure or energy to be removed.

Next, referring to part (d) ofFIG. 1, the second buffer layer122may be formed on the first buffer layer121. The second buffer layer122may include, e.g., AlN, TaN, TiN, HfN, or HfTi. The second buffer layer122may be formed by an HVPE method or an MOCVD method. The description of the deposition process of the second buffer layer122may be the same as the description for the deposition process of the first buffer layer121. A repeated detailed description for the same process may be omitted.

In an implementation, the first buffer layer121and the second buffer layer122may be made of the same material or different materials. In an implementation, both the first buffer layer121and the second buffer layer122may include, e.g., AlN.

The second buffer layer122may be formed on the first buffer layer121, and the holes21of the first buffer layer121may be filled by the second buffer layer122. In the process of forming the second buffer layer122, the foreign particles11may be positioned on the first buffer layer121, and the second buffer layer122may not be formed on the surface of the first buffer layer121(e.g., where the contaminant or particles11end up), and the at least one hole21may be formed. For example, like the process of forming the first buffer layer121, the inorganic particles such as gallium particles in the deposition chamber may end up in or on the first buffer layer121to hinder the growth of the second buffer layer122. For example, the second buffer layer122may include the at least one hole21, e.g., a plurality of holes21.

The holes of the first buffer layer121and the second buffer layer122may not overlap with each other, e.g., may be offset or may not be aligned with each other. The first buffer layer121may be positioned below the second buffer layer122(e.g., such that the first buffer layer121is between the second buffer layer122and the silicon substrate110), and the hole21in the second buffer layer122may not expose the silicon substrate110.

Next, referring to parte (e) ofFIG. 1, the second buffer layer122may be physically cleaned. For example, the physical cleaning may be performed in the cleaning apparatus2000outside the deposition chamber1000. The physical cleaning may include nano spray or ultrasonic wave cleaning. The physical cleaning of the second buffer layer122may be the same as the description for the physical cleaning for the first buffer layer121described above. A repeated detailed description for the same process may be omitted.

In an implementation, the physical cleaning of the second buffer layer122may be omitted. For example, the first buffer layer121may be positioned below the second buffer layer122, and even if the particles on the second buffer layer122are not removed, a problem may not occur in a subsequent process. In an implementation, for simplifying the process, the physical cleaning of the second buffer layer122may be omitted.

In an implementation, the buffer layer may include the first buffer layer121and the second buffer layer122. In an implementation, the buffer layer may include three or more buffer layers. For example, an nthbuffer layer (in which n is an integer of 3 to 10) may be formed on the second buffer layer122and the forming process is the same as those described in the forming of the first buffer layer121and the second buffer layer122above. For example, a total of 3 to 10 buffer layers may be formed on the silicon substrate110(prior to forming the GaN layer140).

Next, referring to part (f) ofFIG. 1, an intermediate layer130may be formed on the second buffer layer122. The intermediate layer130may help alleviate a lattice defect between the second buffer layer122and the GaN layer140to be deposited thereafter. The intermediate layer130may help control a crystal defect of the GaN layer140formed on the top thereafter to help improve quality of the GaN layer140.

In an implementation, the intermediate layer130may include, e.g., AlGaN or GaN. For example, when the intermediate layer130includes GaN, at a temperature of 1,000° C. to 1,2000° C. and under a hydrogen atmosphere, the intermediate layer130may be formed by flowing trimethyl gallium (TMGa) and NH3on the surface of the second buffer layer122. For example, when the intermediate layer130includes AlGaN, at a temperature of 1,000° C. to 1,200° C. and under a hydrogen atmosphere, the intermediate layer130may be formed by flowing TMAl, TMGa and NH3on the surface of the second buffer layer122.

In an implementation, forming the intermediate layer130may be omitted. In an implementation, in order to simplify the process, a process of forming the GaN layer140immediately or directly on the second buffer layer122(e.g., without forming the intermediate layer130) is also possible.

Referring to part (g) ofFIG. 1, the GaN layer140may be formed on the intermediate layer130. When the process of forming the intermediate layer130is omitted, the GaN layer140may be formed directly on the second buffer layer121. The forming of the GaN layer140may be performed in the deposition chamber1000.

The GaN layer140may be formed by flowing TMGa and NH3onto the upper surface of the intermediate layer130, e.g., at a temperature of 950° C. to 1,200° C. and under a hydrogen atmosphere. In an implementation, the GaN layer140may be deposited by a hybrid vapor phase epitaxy (HVPE) method. The growth rate of GaN in the case of using the HVPE method may be larger than that in the MOCVD method, and a thick GaN layer140may be grown with a large area. For example, in an HVPE reactor, HCl and Ga metal may react with each other to form GaCl and then GaCl may react with NH3to grow the GaN layer140on the second buffer layer121.

In an implementation, the GaN layer140may be deposited with or to a thickness of, e.g., 10 nm to 10 cm. In an implementation, the GaN layer140may be deposited with or to a thickness of, e.g., 1 cm to 5 cm.

In the previous step, through the physical cleaning process of the first buffer layer121and the process of forming the second buffer layer122on the first buffer layer121, the GaN layer140deposited in the present step may not contact the silicon substrate110. Accordingly, the melt back phenomenon that could otherwise occur due to contact between the silicon substrate110and the GaN layer140may be advantageously prevented.

Next, referring to part (h) ofFIG. 1, a gallium nitride substrate200made of only the GaN layer140may be formed by removing remaining structures except for the GaN layer140. For example, the silicon substrate110, the first buffer layer121, the second buffer layer122and the intermediate layer130may be removed from the GaN layer by a chemical reaction using gas such as HCl or Cl2. In this case, a temperature at which the silicon substrate110and the like are removed may be 500° C. to 1,200° C. In an implementation, the silicon substrate110, the first buffer layer121, the second buffer layer122and the intermediate layer130may be removed by wet etching or dry etching.

As described above, the manufacturing method of the gallium nitride substrate according to the exemplary embodiment may help prevent the melt back phenomenon from occurring by physically cleaning the first buffer layer121and forming the second buffer layer on the first buffer layer. For example, the first buffer layer121with the plurality of holes21may be formed by removing the foreign particles11by physical cleaning, and the holes of the first buffer layer121may be filled by the second buffer layer122by forming the second buffer layer122on the first buffer layer121, thereby preventing the silicon substrate110from contacting the GaN layer140(e.g., as the GaN layer140is being formed) and preventing the melt back phenomenon.

A manufacturing process of a gallium nitride substrate according to another exemplary embodiment will be described.FIG. 3illustrates stages in a manufacturing process of a gallium nitride substrate according to another exemplary embodiment.

Referring to part (a) ofFIG. 3, a silicon substrate110may be prepared. The substrate110may be a silicon substrate having a surface orientation of {111}.

Next, referring to part (b) ofFIG. 3, a first buffer layer121may be formed on the silicon substrate110. The first buffer layer121may include, e.g., AlN, TaN, TiN, HfN, or HfTi. In an implementation, the first buffer layer121may be formed with a view toward preventing Ga atoms from contacting the silicon substrate110, and may not include Ga. The first buffer layer121may have a thickness of, e.g., 5 nm to 10 μm. In an implementation, the first buffer layer121may have a thickness of, e.g., 500 nm to 1.5 μm. At least one hole21may be formed in the first buffer layer121due to the presence of a particle11.

Next, referring to part (d) ofFIG. 3, the first buffer layer121may be physically cleaned to remove foreign particles11. In this case, the physical cleaning may be performed in the cleaning apparatus2000outside the deposition chamber1000. The physical cleaning may include nano spray or ultrasonic wave cleaning. In the step, the first buffer layer121may include at least one hole21exposing the silicon substrate110.

The process corresponding to parts (a) to (c) ofFIG. 3of the exemplary embodiment is the same as the description of the process for parts (a) to (c) ofFIG. 1described above. A repeated detailed description for the same process may be omitted.

Next, referring to part (d) ofFIG. 3, a silicon nitride region111may be formed on or at the surface of the silicon substrate110, which is exposed by the hole21in the first buffer layer121. For example, the silicon nitride region111may be formed by flowing N2and NH3onto the upper surface of the silicon substrate110(e.g., the portion of the silicon substrate110) exposed by or through the hole21in the first buffer layer121, and reacting silicon (of the silicon substrate110) with the N2and NH3. The forming of the silicon nitride region111may be performed in the deposition chamber1000. For example, the deposition chamber1000may already include N2and NH3sources and the like, and a separate reaction chamber for forming the silicon nitride region111may not be required.

In the step, the portion of the silicon substrate110covered by the first buffer layer121may not react with NH3and the like, and the portion of the silicon substrate110exposed by or through the hole21of the first buffer layer121may react with NH3. Accordingly, a part of the silicon substrate110may be converted to silicon nitride to form the silicon nitride region.

In an implementation, the silicon nitride region111may include various silicon nitride materials, e.g., SiN, Si2N3, and Si3N4. For example, SiNxor SixNy(in which x and y are natural numbers of 1 to 4) may be included.

In the case where the silicon nitride region111is formed, when forming the GaN layer140in a subsequent step, contact between Ga of the GaN layer140and Si of the silicon substrate110may be avoided to help prevent the melt back from occurring. For example, the silicon nitride region111may have an insulating characteristic to separate the silicon substrate110and the GaN layer140from each other. A thickness of the silicon nitride region111may be, e.g., 1 Å to 10 nm.

Next, referring to part (e) ofFIG. 3, the second buffer layer122may be formed on the first buffer layer121. The second buffer layer122may include, e.g., AlN, TaN, TiN, HfN, or HfTi. In an implementation, the first buffer layer121and the second buffer layer122may be made of the same material or different materials. In an implementation, both the first buffer layer121and the second buffer layer122may include AlN. The second buffer layer122may be formed on the first buffer layer121, and the at least one hole21in the first buffer layer121may be filled by the second buffer layer122. In the process of forming the second buffer layer122, the foreign particles11may be on the first buffer layer121, and the second buffer layer122may not formed on the surface of the first buffer layer121where the particles11are found, and at least one hole21in the second buffer layer122may be formed. In an implementation, the at least one hole21in the second buffer layer122and the at least one hole21in the first buffer layer121may not overlap with each other, e.g., may be offset or otherwise vertically misaligned with each other.

Next, referring to part (f) ofFIG. 3, the second buffer layer122may be physically cleaned. In an implementation, the physical cleaning process of the second buffer layer122may be omitted. The forming and physical cleaning processes of the second buffer layer122in parts (e) and (f) ofFIG. 3may be the same as described in parts (d) and (e) ofFIG. 1described above. The detailed description for the same process may be omitted.

In an implementation, in the manufacturing method of the gallium nitride substrate according to the exemplary embodiment, the forming of the second buffer layer122may be omitted. For example, in the exemplary embodiment ofFIG. 1, the second buffer layer122may be formed on the first buffer layer121including the at least one hole21, and the second buffer layer122may fill the at least one hole21in the first buffer layer121to prevent the GaN layer140and the silicon substrate110from contacting each other. In the present embodiment, the silicon nitride region111may be formed in the silicon substrate110exposed by or through the at least one hole21in the first buffer layer121, and even if the second buffer layer121is omitted, the silicon substrate110and the GaN layer140may not contact each other. In an implementation, the buffer layer may include the first buffer layer121alone or both the first buffer layer121and the second buffer layer122. In an implementation, an nthbuffer layer (in which n is an integer of 3 to 10) may be formed on the second buffer layer122, and the forming process may be the same as those described in the forming of the first buffer layer121and the second buffer layer122above.

Next, referring to part (g) ofFIG. 3, an intermediate layer130may be formed on the second buffer layer122. The intermediate layer130may help alleviate a lattice defect between the second buffer layer122and the GaN layer140to be deposited thereafter. The intermediate layer130may help control a crystal defect of the GaN layer140formed thereon to help improve quality of the GaN layer140.

The intermediate layer130may include, e.g., AlGaN or GaN. In an implementation, the forming of the intermediate layer130may be omitted.

Next, referring to part (h) ofFIG. 3, the GaN layer140may be formed on the intermediate layer130. When the process of forming the intermediate layer130is omitted, the GaN layer140may be formed on, e.g., directly on, the second buffer layer122. In an implementation, when both the process of forming the intermediate layer130and the process of forming the second buffer layer122are omitted, the GaN layer140may be formed on, e.g., directly on, the first buffer layer121. The GaN layer140may be deposited with or to a thickness of 10 nm to 10 cm. In an implementation, the GaN layer140may be deposited to a thickness of 1 cm to 5 cm. The GaN layer140may be formed by a MOCVD or HVPE method.

Next, referring to part (i) ofFIG. 3, a gallium nitride substrate made of only the GaN layer140may be formed by removing the remaining structures except for the GaN layer140, e.g., by isolating the GaN layer140. The steps of parts (g) to (i) ofFIG. 3are the same as described in the steps of parts (f) to (h) ofFIG. 1above. A repeated detailed description for the same process may be omitted.

As such, in the manufacturing method of the gallium nitride substrate according to the present embodiment, the particles11may be removed by physically cleaning the first buffer layer121, and the silicon nitride region111may be formed in the region of the silicon substrate110exposed through the at least one 21 of the first buffer layer121to prevent the silicon substrate110and the GaN layer140from contacting each other. Accordingly, the melt back phenomenon may be prevented.

A manufacturing process of a gallium nitride substrate according to yet another exemplary embodiment will be described with reference toFIG. 4.

FIG. 4illustrates stages in a manufacturing process of a gallium nitride substrate according to yet another exemplary embodiment. Referring toFIG. 4, the manufacturing process of the gallium nitride substrate according to the exemplary embodiment may be similar to the manufacturing process of the gallium nitride substrate according to the exemplary embodiment ofFIG. 1. A repeated detailed description of the same or similar processes may be omitted.

For example, referring to part (a) ofFIG. 4, a silicon substrate110may be prepared. The substrate110may be a silicon substrate having a surface orientation of {111}.

Next, referring to part (b) ofFIG. 4, a first buffer layer121may be formed on the silicon substrate110. The first buffer layer121may include, e.g., AlN, TaN, TiN, HfN, or HfTi. In an implementation, the first buffer layer121may be formed with a view toward preventing Ga atoms from contacting the silicon substrate110, and may not include Ga. The first buffer layer121may have a thickness of 5 nm to 10 μm. In an implementation, the first buffer layer121may have a thickness of 500 nm to 1.5 μm. At least one hole21may be present in the first buffer layer121due to the presence of a contaminant or particle11on the silicon substrate110.

Next, referring to part (c) ofFIG. 4, the first buffer layer121may be physically cleaned to remove foreign particles11. For example, the physical cleaning may be performed in the cleaning apparatus2000outside the deposition chamber1000. The physical cleaning may include nano spray or ultrasonic wave cleaning. In the step, the first buffer layer121may include at least one, e.g., a plurality of holes21, exposing portions of the silicon substrate110.

Next, referring to part (d) ofFIG. 4, the second buffer layer122may be formed on the first buffer layer121. The second buffer layer122may include, e.g., AlN, TaN, TiN, HfN, or HfTi. In an implementation, the first buffer layer121and the second buffer layer122may be made of the same material or different materials. In an implementation, both the first buffer layer121and the second buffer layer122may include aluminum nitride.

The second buffer layer122may be formed on the first buffer layer121, and any holes21in the first buffer layer121may be filled by the second buffer layer122. In the process of forming the second buffer layer122, foreign particles11may be present on the first buffer layer121, the second buffer layer122may not be formed on the surface of the first buffer layer121where the contaminants or particles11are present, and at least one hole21may be formed or may be present in the second buffer layer122. In an implementation, the hole(s)21in the second buffer layer122and the hole(s)21in the first buffer layer121may not overlap with each other.

Next, referring to part (e) ofFIG. 4, the second buffer layer122may be physically cleaned in the cleaning apparatus2000. In an implementation, the physical cleaning process of the second buffer layer122may be omitted. The steps of parts (a) to (e) ofFIG. 4may be similar to the steps of parts (a) to (e) ofFIG. 1above. A repeated detailed description for the same or similar constituent elements may be omitted.

In an implementation, the buffer layer may include both the first buffer layer121and the second buffer layer122or may include three layers or more. For example, an nthbuffer layer (in which n is an integer of 3 to 10) may be formed on the second buffer layer122and the forming process may be the same as those described in the forming of the first buffer layer121and the second buffer layer122above.

Referring to part (f) ofFIG. 4, an insulating layer150may be formed on the second buffer layer122. The forming of the insulating layer150may be performed in a reactor3000. The insulating layer150may be formed by a CVD, sputtering, or evaporation method. A thickness of the insulating layer150may be 1 nm to 100 μm. The insulating layer150may include, e.g., silicon oxide, silicon nitride, alumina, or hafnium oxide.

Next, referring to part (g) ofFIG. 4, an insulating layer pattern152may be formed at an edge of the upper surface of the second buffer layer122(e.g., a surface of the second buffer layer122that faces away from the silicon substrate110) by patterning the insulating layer150. In the case where the silicon substrate110has a circular shape, the insulating layer pattern152may have a circular band or ring shape positioned along a circumference of the circle. The patterning of the insulating layer150may be performed by wet etching or dry etching. A width of the insulating layer pattern152may be approximately 0.5 mm to 5 mm.

Next, referring to part (h) ofFIG. 4, a structure may be put in the deposition chamber1000again and the GaN layer140may be formed on the second buffer layer122. The GaN layer140may be formed by an HVPE method or an MOCVD method. In this case, a monocrystal GaN layer140may be grown on the second buffer layer122, and a polycrystalline GaN layer142may be formed on the insulating layer pattern152. For example, the insulating layer pattern152may include silicon oxide, silicon nitride, alumina, or hafnium oxide, which may not be suitable for growing GaN to a monocrystal.

Next, referring to part (i) ofFIG. 4, a gallium nitride substrate200made of only the GaN layer140may be formed by removing the remaining structures except for the GaN layer140(e.g., by isolating the GaN layer140). This step may be the same as described with respect to part (h) ofFIG. 1, above. The detailed description for the same process may be omitted.

In the removing step, the polycrystalline GaN layer142on the insulating layer pattern152may be removed together. The monocrystal GaN layer140and the polycrystalline GaN layer142may be easily released due to a difference in crystal structure. Accordingly, the polycrystalline GaN layer142may be easily detached from the monocrystal GaN layer140.

In the case where the insulating layer pattern152is formed and the polycrystalline GaN layer142is formed thereon and removed, the melt back may be prevented from occurring as compared with the case where the processes are not included. For example, in the manufacturing process of the gallium nitride substrate, cracks on the buffer layer could mainly be generated in an edge region, and in the manufacturing method according to the exemplary embodiment, the insulating layer pattern may be formed on the edge region and the melt back may be prevented from occurring through the cracks. Accordingly, a large-area GaN substrate having good quality may be manufactured on the silicon substrate.

A manufacturing process of a gallium nitride substrate according to still another exemplary embodiment will be described with reference toFIG. 5.FIG. 5illustrates stages in a manufacturing process of a gallium nitride substrate according to still another exemplary embodiment. Referring toFIG. 5, the manufacturing process of the gallium nitride substrate according to the exemplary embodiment may include forming a first buffer layer121including at lest one hole and a second buffer layer122including at least one, forming a silicon nitride region111on a silicon substrate110exposed through the at least one hole21in the first buffer layer121, and forming an insulating layer pattern152on the second buffer layer122.

Referring to part (a) ofFIG. 5, a silicon substrate110may be prepared. The substrate110may be a silicon substrate having a surface orientation of {111}.

Next, referring to part (b) ofFIG. 5, a first buffer layer121may be formed on the silicon substrate110. The first buffer layer121may include, e.g., AlN, TaN, TiN, HfN, or HfTi. In an implementation, the first buffer layer121may be formed with a view toward preventing Ga atoms from contacting the silicon substrate110and thus may not include Ga.

Next, referring to part (c) ofFIG. 5, the first buffer layer121may be physically cleaned in a cleaning apparatus2000to remove foreign particles11. In the step, the first buffer layer121may include at least one hole21exposing the silicon substrate110. The processes of parts (a) to (c) ofFIG. 5may be the same as the processes of parts (a) to (c) ofFIG. 1, above. A repeated detailed description for the same constituent elements may be omitted.

Next, referring to part (d) ofFIG. 5, a silicon nitride region111may be formed on a region of the silicon substrate110that is exposed by the at least one hole21in the first buffer layer121. The silicon nitride region111may be formed in the deposition chamber1000and may be formed by flowing N2and NH3onto the surface of the silicon substrate110exposed through the at least one hole21in the first buffer layer121to thus react silicon and N2and NH3. The silicon nitride region111may include various silicon nitride materials, e.g., SiN, Si2N3, and Si3N4. For example, SiNx or SixNy (x and y are natural numbers of 1 to 4) may be included. A thickness of the silicon nitride region111may be 1 Å to 10 nm.

Next, referring to part (e) ofFIG. 5, the second buffer layer122may be formed on the first buffer layer121. The second buffer layer122may include, e.g., AlN, TaN, TiN, HfN, or HfTi. In an implementation, the first buffer layer121and the second buffer layer122may be made of the same material or different materials. In an implementation, both the first buffer layer121and the second buffer layer122may include aluminum nitride. The second buffer layer122may be formed on the first buffer layer121, and the at least one hole21in the first buffer layer121may be filled by the second buffer layer122. In the process of forming the second buffer layer122, the foreign particles11may be on the first buffer layer121, and the second buffer layer122may not be formed on the front surface of the first buffer layer121(where the foreign particles11have come to rest), and the at least one hole21may be formed. In an implementation, the at least one hole21in the second buffer layer122and the at least one hole21in the first buffer layer121may not overlap with each other.

Next, referring to part (f) ofFIG. 5, the second buffer layer122may be physically cleaned. In an implementation, the physical cleaning process of the second buffer layer122may be omitted.

The processes of parts (d) to (f) ofFIG. 5may be the same as those described in parts (d) to (f) ofFIG. 3, above. A repeated detailed description for the same or similar constituent elements may be omitted.

Next, referring to part (g) ofFIG. 5, an insulating layer150may be formed on the second buffer layer122. The insulating layer150may be formed in a reactor3000and the insulating layer150may include, e.g., silicon oxide, silicon nitride, alumina, or hafnium oxide.

Next, referring to part (h) ofFIG. 5, an insulating layer pattern152may be formed at an edge area of the upper surface of the second buffer layer122by patterning the insulating layer150. In the case where the silicon substrate110has a circular shape, the insulating layer pattern152may have a circular stripe or ring shape positioned along a circumference of the circle.

Next, referring to part (i) ofFIG. 5, a structure may be put in the deposition chamber1000again and the GaN layer140may be formed on the second buffer layer122. The GaN layer140may be formed by an HVPE method or an MOCVD method. In this case, a monocrystal GaN layer140may be grown on the second buffer layer122, and a polycrystalline GaN layer142may be formed on the insulating layer pattern152.

Next, referring to part (j) ofFIG. 5, a gallium nitride substrate200made of only the GaN layer140may be formed by removing the remaining structures except for the GaN layer140.

The processes of parts (g) to (j) ofFIG. 5may be the same as those described in parts (f) to (i) ofFIG. 4, above. A repeated detailed description for the same or similar constituent elements may be omitted.

For example, in the manufacturing method of the gallium nitride substrate according to the exemplary embodiment, it is possible to help prevent a melt back phenomenon by physically cleaning the first buffer layer121and forming the second buffer layer122on the first buffer layer121, to help prevent a melt back phenomenon from occurring through cracks in the edge region by forming the insulating layer pattern152on the second buffer layer122and growing GaN thereon, and to help prevent the melt back by forming the silicon nitride region111on the silicon substrate110exposed by the holes21of the first buffer layer121.

By way of summation and review, GaN monocrystal may require a high temperature (of approximately 1,500° C.) and a nitrogen atmosphere (of approximately 20,000 atms) for a liquid crystal growth due to high nitrogen vapor pressure at a melting point, and it may be difficult to mass-produce the GaN monocrystal. The GaN monocrystal may be a thin film type having a currently usable crystal size of about 100 mm2and thus it may be difficult to use the GaN monocrystal for fabricating an element.

A GaN thin film may be grown on heterogeneous substrates by using methods such as metal organic chemical vapor deposition (MOCVD) and hydride vapor phase epitaxy (HVPE).

A GaN layer may be grown on a sapphire substrate and then a GaN substrate may be manufactured by removing the sapphire substrate. In the sapphire substrate, it may be difficult to prepare a substrate having a size of approximately 6 inches or more and the price may be expensive. Thus, it may be difficult to use the sapphire substrate for manufacturing a large-area GaN substrate.

A method of growing the GaN layer by using a large-area silicon substrate has been considered. When GaN is grown on the silicon substrate, in the case of directly contacting silicon and GaN, silicon may be diffused into GaN and the silicon substrate surface could be etched. As a result, melt back may occur, and tensile stress may occur on the silicon substrate during GaN growth due to differences in thermal expansion coefficient and lattice constant between the silicon and the GaN and thus cracks could be generated.

The embodiments may provide a method of manufacturing a gallium nitride substrate having advantages of preventing melt back of a silicon substrate and GaN.