Multilayer electronic device including a high precision inductor

A multilayer electronic device may include a plurality of dielectric layers and a signal path having an input and an output. An inductor may include a conductive layer formed on one of the plurality of dielectric layers and may be electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground. The inductor may include an outer perimeter that includes a first straight edge facing outward in a first direction and a second straight edge parallel to the first straight edge and facing outward in the first direction. The second straight edge may be offset from the first straight edge by an offset distance that is less than about 500 microns and less than about 90% of a first width of the inductor in the first direction at the first straight edge.

BACKGROUND OF THE DISCLOSURE

Multilayer electronic devices often include inductors. For example, multilayer filters often include one or more inductors that are designed to provide specific inductance values. However, precision control over the inductance of such inductors can be difficult to achieve as it involves precisely controlling the dimensions of the inductor.

Filtering of high frequency signals, such as high frequency radio signal communication, has recently increased in popularity. The demand for increased data transmission speed for wireless connectivity has driven demand for high frequency components, including those configured to operate at high frequencies, including 5G spectrum frequencies. High frequency applications often require inductors having very low, yet precise inductance values. Achieving smaller inductance values requires smaller inductors, further increasing the difficulty associated with precisely controlling the inductance values. As such, a multilayer filter including a high precision inductor would be welcomed in the art.

SUMMARY OF THE DISCLOSURE

In accordance with one embodiment of the present disclosure, a multilayer electronic device may include a plurality of dielectric layers and a signal path having an input and an output. The multilayer electronic device may include an inductor including a conductive layer overlying one of the plurality of dielectric layers. The inductor may be electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground. The inductor may have an outer perimeter including a first straight edge that faces outward in a first direction and a second straight edge that is parallel to the first straight edge and faces outward in the first direction. The second straight edge may be offset from the first straight edge by an offset distance that is less than about 500 microns and less than about 90% of a first width of the inductor in the first direction at the first straight edge.

In accordance with another embodiment of the present disclosure, a method of forming a multilayer electronic device may include providing a plurality of dielectric layers and forming a plurality of conductive layers on at least some of the plurality of dielectric layers to form a signal path having an input and an output. The signal path may include an inductor electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground. The inductor may have an outer perimeter including a first straight edge that faces outward in a first direction and a second straight edge that is parallel to the first straight edge and faces outward in the first direction. The second straight edge may be offset from the first straight edge by an offset distance that is less than about 500 microns and less than about 90% of a first width of the inductor in the first direction at the first straight edge.

In accordance with another embodiment of the present disclosure, a method of designing an inductor for a multilayer electronic device may include selecting an effective length and a width for the inductor based on a target inductance value for the inductor. The method may include sizing an offset distance associated with a protrusion of the inductor. The offset distance may be between a first straight edge of a perimeter of the inductor and a second straight edge of the perimeter of the inductor. The offset distance may be less than 500 microns and less than about 90% of a first width of the inductor in a first direction at the first straight edge. The first straight edge may face outward in a first direction, and the second straight edge may be parallel with the first straight edge and may face outward in the first direction.

DETAILED DESCRIPTION OF REPRESENTATIVE EMBODIMENTS

Generally speaking, the present disclosure is directed to a multilayer electronic device including a plurality of dielectric layers and a signal path having an input and an output. The multilayer electronic device includes an inductor that includes a conductive layer formed on one of the plurality of dielectric layers. The inductor may be electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground.

The inductor may have an outer perimeter including a first straight edge that faces outward in a first direction and a second straight edge that is parallel to the first straight edge and faces outward in the first direction. The second straight edge may be offset from the first straight edge by an offset distance that is less than about 500 microns and less than about 90% of a first width of the inductor in the first direction at the first straight edge.

A protrusion may be associated with the offset distance. The protrusion may slightly increase the average width of the inductor and decreases the inductance of the inductor. Inductance is generally proportional to the length of an inductor, but inversely proportional to a width of the inductor. In other words, inductance may be proportional to a length-to-average-width ratio of the inductive element. As such, small adjustments to the width and length of inductive elements can be used to fine tune inductance. Thus, such protrusions may provide a more precise adjustment to the inductance of the inductor than adjusting the entire width of the inductor.

The multilayer filter may include one or more dielectric materials. In some embodiments, the one or more dielectric materials may have a low dielectric constant. The dielectric constant may be less than about 100, in some embodiments less than about 75, in some embodiments less than about 50, in some embodiments less than about 25, in some embodiments less than about 15, and in some embodiments less than about 5. For example, in some embodiments, the dielectric constant may range from about 1.5 and 100, in some embodiments from about 1.5 to about 75, and in some embodiments from about 2 to about 8. The dielectric constant may be determined in accordance with IPC TM-650 2.5.5.3 at an operating temperature of 25° C. and frequency of 1 MHz. The dielectric loss tangent may range from about 0.001 to about 0.04, in some embodiments from about 0.0015 to about 0.0025.

In some embodiments, the one or more dielectric materials may include organic dielectric materials. Example organic dielectric include polyphenyl ether (PPE) based materials, such as LD621 from Polyclad and N6000 series from Park/Nelco Corporation, liquid crystalline polymer (LCP), such as LCP from Rogers Corporation or W. L. Gore & Associates, Inc., hydrocarbon composites, such as 4000 series from Rogers Corporation, and epoxy-based laminates, such as N4000 series from Park/Nelco Corp. For instance, examples include epoxy based N4000-13, bromine-free material laminated to LCP, organic layers with high K material, unfilled high-K organic layers, Rogers 4350, Rogers 4003 material, and other thermoplastic materials such as polyphenylene sulfide resins, polyethylene terephthalate resins, polybutylene terephthalate resins, polyethylene sulfide resins, polyether ketone resins, polytetraflouroethylene resins and graft resins, or similar low dielectric constant, low-loss organic material.

In some embodiments, the dielectric material may be a ceramic-filled epoxy. For example, the dielectric material may include an organic compound, such as a polymer (e.g., an epoxy) and may contain particles of a ceramic dielectric material, such as barium titanate, calcium titanate, zinc oxide, alumina with low-fire glass, or other suitable ceramic or glass-bonded materials.

Additionally, in some embodiments, non-organic dielectric materials may be used including a ceramic, semi-conductive, or insulating materials, such as, but not limited to barium titanate, calcium titanate, zinc oxide, alumina with low-fire glass, or other suitable ceramic or glass-bonded materials. Alternatively, the dielectric material may be an organic compound such as an epoxy (with or without ceramic mixed in, with or without fiberglass), popular as circuit board materials, or other plastics common as dielectrics. In these cases, the conductor is usually a copper foil which is chemically etched to provide the patterns. In still further embodiments, dielectric material may comprise a material having a relatively high dielectric constant (K), such as one of NPO (COG), X7R, X5R X7S, ZSU, Y5V and strontium titanate. In such examples, the dielectric material may have a dielectric constant that is greater than 100, for example within a range from between about 100 to about 4000, in some embodiments from about 1000 to about 3000.

One or more conductive layers may be directly formed on the dielectric layers. Alternatively a coating or intermediate layer may be located between the conductive layers and respective dielectric layers. As used herein, “formed on” may refer to either a conductive layer that is directly formed on a dielectric layer or a conductive layer that overlies the dielectric layer with an intermediate layer or coating therebetween.

The conductive layers may include a variety of conductive materials. For example, the conductive layers may include copper, nickel, gold, silver, or other metals or alloys.

In some embodiments, the multilayer electronic device may include a signal path having an input and an output. The signal path may include one or more conductive layers overlying one or more of the dielectric layers and connected with one or more vias.

Vias may be formed in one or more of the dielectric layers. For example, a via may electrically connect a conductive layer on one dielectric layer with a conductive layer on another dielectric layer. The via may include a variety of conductive materials, such as copper, nickel, gold, silver, or other metals or alloys. The vias may be formed by drilling (e.g., mechanical drilling, laser drilling, etc.) through holes and plating the through holes with a conductive material, for example using electroless plating or seeded copper. The vias may be filled with conductive material such that a solid column of conductive material is formed. Alternatively, the interior surfaces of the through holes may be plated such that the vias are hollow.

The multilayer electronic device may include an inductor. The inductor may include a conductive layer formed on one of the plurality of dielectric layers. The inductor may be electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground. For example, the inductor may form a portion of the signal path or may be connected between the signal path and ground.

In some embodiments, the inductor may include at least one corner. The corner may have an angle greater than about 20 degrees, (e.g., 90 degrees). The inductor may have from one to nine corners, or more, in some embodiments, the inductor may have fewer than six corners, in some embodiments fewer than four corners, in some embodiments fewer than three corners, and in some embodiments fewer than two corners. In some embodiments, the inductor may be free of any corners. In some embodiments, the inductor may define a full “loop” or less. For example, the inductor may define less than one half of a “loop.”

In some embodiments, at least some of the dielectric layers may have thicknesses that are less than about 180 microns, in some embodiments less than about 120 microns, in some embodiments less than about 100 microns in some embodiments less than about 80 microns, in some embodiments less than 60 microns, in some embodiments less than about 50 microns, in some embodiments less than about 40 microns, in some embodiments less than about 30 microns, and in some embodiments less than about 20 microns. For example, the conductive layer of the inductor may be formed on a dielectric layer having a thickness that is less than about 180 microns, in some embodiments less than about 100 microns, and in some embodiments less than about 80 microns.

One or more vias may be formed in the dielectric layers. The via(s) may electrically connect the different conductive layers. For example, a via may be formed in the dielectric layer on which the conductive layer of the inductor is formed. Such via may connect the inductor with another part of the filter, such as a portion of the signal path or the ground (e.g., a ground plane). In some embodiments, the length of such via in a Z-direction may be equal to the thickness of the dielectric layer in which such via is formed. For example, such via may have a length that less than about 180 microns, in some embodiments less than about 100 microns, and in some embodiments less than about 80 microns.

In some embodiments, a series of vias and intermediary layers may be vertically arranged to connect the inductor with another conductive layer, such as the ground plane or a portion of the signal path. A total vertical length in the Z-direction of the series of vias and intermediary layers may range from about 10 microns to about 500 microns, in some embodiments from about 30 microns to about 300 microns, in some embodiments from about 40 microns to about 200 microns, and in some embodiments from about 60 microns to about 150 microns.

The via(s) may have a variety of suitable widths. For example, in some embodiments the width of the via may range from about 20 microns to about 200 microns, in some embodiments from about 40 microns to about 180 microns, in some embodiments from about 60 microns to about 140 microns, and in some embodiments from about 80 microns to about 120 microns.

In some embodiments, the multilayer electronic device may be configured as a multilayer filter. The multilayer filter may be configured for operation at high frequencies. The multilayer filter may have a characteristic frequency (e.g., a low pass frequency, a high pass frequency, an upper bound of a bandpass frequency, or a lower bound of the bandpass frequency) that is greater than 6 GHz. In some embodiments, the filter may have a characteristic frequency that is greater than about 6 GHz, in some embodiments greater than about 10 GHz, in some embodiments greater than about 15 GHz, in some embodiments greater than about 20 GHz, in some embodiments greater than about 25 GHz, in some embodiments greater than about 30 GHz, in some embodiments greater than about 35 GHz, in some embodiments greater than about 40 GHz, in some embodiments greater than about 45 GHz, in some embodiments greater than about 50 GHz, in some embodiments greater than about 60 GHz, in some embodiments greater than about 70 GHz, and in some embodiments in some embodiments greater than about 80 GHz.

The multilayer filter may exhibit excellent performance characteristics, such as low insertion loss for frequencies within a pass band frequency range of the multilayer filter. For example, the average insertion loss for frequencies within the pass band frequency range may be greater than −15 dB, in some embodiments greater than −10 dB, in some embodiments greater than −5 dB, in some embodiments greater than −2.5 dB or more.

Additionally, the multilayer filter may exhibit excellent rejection of frequencies outside the pass band frequency range. In some embodiments, the insertion loss for frequencies outside the pass band frequency range may be less than about −15 dB, in some embodiments less than about −25 dB, in some embodiments less than about −35 dB, and in some embodiments less than about −40 dB.

Additionally, the multilayer filter may exhibit steep roll-off from the passband frequency range to frequencies outside the passband. For example, for frequencies immediately outside the passband frequency range, the insertion loss may decrease at a rate of about 0.1 dB/MHz, in some embodiments greater than about 0.2 dB/MHz, in some embodiments greater than about 0.3 dB/MHz, and in some embodiments greater than about 0.4 dB/MHz.

The multilayer filter may also exhibit consistent performance characteristics (e.g., insertion loss, return loss, etc.) across a wide range of temperatures. In some embodiments, the insertion loss of the multilayer filter may vary less than 5 dB or less across large temperature ranges. For example, the multilayer filter can exhibit a first insertion loss at about 25° C. and at a first frequency. The multilayer filter can exhibit a second insertion loss at a second temperature and at about the first frequency. A temperature difference between the first temperature and the second temperature can be about 70° C. or greater, in some embodiments about 60° C. or greater, in some embodiments about 50° C. or greater, in some embodiments about 30° C. or greater, and in some embodiments about 20° C. or greater. As an example, the first temperature can be 25° C., and the second temperature can be 85° C. As another example, the first temperature can be 25° C., and the second temperature can be −55° C. The difference between the second insertion loss and the first insertion loss can be about 5 dB or less, in some embodiments about 2 dB or less, in some embodiments about 1 dB or less, in some embodiments, about 0.75 dB or less, in some embodiments about 0.5 dB or less, and in some embodiments, about 0.2 dB or less.

However, it should be understood that in other embodiments, the multilayer electronic device may be any suitable type of device that includes an inductor. For example the multilayer electronic device may be a multilayer inductor, multilayer inductor array, multilayer transformer (e.g., a balun), etc.

In some embodiments, the device may have an overall length that ranges from about 0.5 mm to about 30 mm, in some embodiments, from about 1 mm to about 15 mm, and in some embodiments from about 2 mm to about 8 mm.

In some embodiments, the device may have an overall width that ranges from about 0.2 mm to about 20 mm, in some embodiments from about 0.5 mm to about 15 mm, in some embodiments from about 1 mm to about 10 mm, and in some embodiments from about 2 mm to about 8 mm.

The device may generally be low-profile or thin. For example, in some embodiments, the device may have an overall thickness that ranges from about 100 microns to about 2 mm, in some embodiments from about 150 microns to about 1 mm, and in some embodiments from about 200 microns to about 300 microns.

Regardless of the particular configuration employed, the present inventors have discovered that through selective control over the shape of conductive layers of an inductor of a multilayer electronic device, precise control over the inductance of the inductor can be achieved. More specifically, an average width of the inductor may be precisely adjusted using one or more protrusions. The protrusions may provide excellent control over a length-to-average-width ratio of the inductor, which allows precise control of the inductance value of the inductor.

The multilayer electronic device may include conductive layers. The conductive layers may be formed using a variety of suitable techniques. Subtractive, semi-additive or fully additive processes may be employed with panel or pattern electroplating of the conductive material followed by print and etch steps to define the patterned conductive layers. Photolithography, plating (e.g., electrolytic), sputtering, vacuum deposition, printing, or other techniques may be used to for form the conductive layers. For example, a thin layer (e.g., a foil) of a conductive material may be adhered (e.g., laminated) to a surface of a dielectric layer. The thin layer of conductive material may be selectively etched using a mask and photolithography to produce a desired pattern of the conductive material on the surface of the dielectric material.

A finite resolution is achievable for any such process. A “minimum line width” may be defined as the smallest, accurately producible feature size of the process employed. In some embodiments, the minimum line width may be about 100 microns or less, in some embodiments about 75 microns or less, in some embodiments about 50 microns or less, in some embodiments about 20 microns or less, in some embodiments about 10 microns or less, and in some embodiments about 5 microns or less. A “minimum area unit” may be defined as the minimum line width squared. The minimum area unit may be about 0.01 mm2or less, in some embodiments about 0.005 mm2or less, in some embodiments about 0.0025 mm2or less, and in some embodiments about 0.0001 mm2or less.

In some embodiments, inductors that are short and/or wide may be employed to achieve very low inductance values. Such low inductance values may be desirable for high frequency applications. A length-to-average-width ratio may be defined as the length of the inductor divided by an average width of the inductor. In some embodiments, the length-to-average-width ratio may be less than about 60, in some embodiments less than about 20, in some embodiments less than about 10, in some embodiments less than about 8, in some embodiments, less than about 6, in some embodiments less than about 4, in some embodiments less than about 2, in some embodiments less than about 1, and in some embodiments less than about 0.5.

The inductor may have an average width that is less than about 1000 microns, in some embodiments less than about 500 microns, in some embodiments less than about 300 microns, in some embodiments less than about 200 microns, and in some embodiments less than about 100 microns.

In some embodiments, the inductor may have an effective length between the first location and the second location. The effective length may be defined as the length along the conductive layer between the first location and the second location. For example, the effective length may equal a sum of lengths of various straight portions of the inductor (e.g., in the X-Y plane) connected between the first location and the second location. The effective length of the inductor may be less than about 5 mm, in some embodiments less than about 3 mm, in some embodiments less than about 2 mm, in some embodiments less than about 1 mm, in some embodiments less than about 800 microns, in some embodiments less than about 500 microns, in some embodiments less than about 300 microns, in some embodiments less than about 200 microns, and in some embodiments less than about 100 microns.

The inductor may include a feature (e.g., a protrusion) that slightly increases the width of the inductor, which may slightly decrease the inductance of the inductor. More specifically, the inductor may have an outer perimeter that includes a first straight edge that faces outward in a first direction and a second straight edge that is parallel to the first straight edge and faces outward in the first direction. The second straight edge may be offset from the first straight edge by an offset distance. The protrusion may be formed by the second straight edge being offset from the first straight edge.

The offset distance may be less than about 500 microns, in some embodiments less than about 400 microns, in some embodiments less than about 300 microns, in some embodiments less than about 200 microns, in some embodiments less than about 100 microns, in some embodiments less than about 75 microns, and in some embodiments less than about 50 microns. The offset distance may be about 8 minimum line widths or less, in some embodiments about 4 minimum line widths or less, in some embodiments about 2 minimum line widths or less, and in some embodiments approximately 1 minimum line width.

The offset distance may be about 90 percent or less of a first width of the inductor in the first direction at the first straight edge, in some embodiments 80 percent or less, in some embodiments 70 percent or less, in some embodiments 60 percent or less, in some embodiments, in some embodiments 50 percent or less, 40 percent or less, in some embodiments 30 percent or less, in some embodiments 20 percent or less, in some embodiments 10 percent or less, in some embodiments 5 percent or less, and in some embodiments 2 percent or less. The protrusion may decrease the length-to-average-width ratio of the inductor by 30 percent or less, in some embodiments by 20 percent or less, in some embodiments by 10 percent or less, in some embodiments by 5 percent or less, and in some embodiments by 2 percent or less.

Thus, a ratio of the second width of the inductor at the second straight edge to the first width of the inductor at the first straight edge may be less than about 1.9, in some embodiments less than about 1.8, in some embodiments less than about 1.7, in some embodiments less than about 1.6, in some embodiments less than about 1.5, in some embodiments less than about 1.4, in some embodiments less than about 1.3, in some embodiments less than about 1.2, in some embodiments less than about 1.1, in some embodiments less than about 1.05, and in some embodiments less than about 1.02. In some embodiments the ratio of the second width of the inductor at the second straight edge to the first width of the inductor at the first straight edge may be greater than about 1.02, in some embodiments greater than about 1.05, in some embodiments greater than about 1.1, in some embodiments greater than about 1.2. Such dimensions may allow the protrusion to fine tune the width of the inductor at the protrusion and thereby fine tune the inductance of the inductor.

In some embodiments, the protrusion or tab may have an effective length of about 70 microns or more, in some embodiments greater than about 100 microns, in some embodiments greater about 120 microns, in some embodiments greater than about 150 microns, in some embodiments greater about 200 microns, and in some embodiments greater than about 220 microns.

In some embodiments, the inductor may include multiple protrusions. For example, the inductor may include a pair of protrusions. The pair of protrusions may be symmetric about a centerline of the inductor that extends from the first location to the second location along the inductor. In some embodiments, the pair of protrusions may be symmetric about a lateral centerline.

A width discontinuity edge may extend between the first straight edge and the second straight edge. The width discontinuity edge may be perpendicular to the first straight edge and second straight edge. The width discontinuity edge may be spaced apart from a corner of a longitudinal centerline of the inductor by at least about 30 microns, in some embodiments at least 50 microns, in some embodiments at least 80 microns, in some embodiments at least 100 microns, in some embodiments at least 200 microns, in some embodiments at least 300 microns, n some embodiments at least 500 microns.

FIG.1is a simplified schematic of a multilayer filter100according to aspects of the present disclosure. The filter100may include one or more inductors102,104,106, and one or more capacitors108,110,112. An input voltage (represented by ViinFIG.1) may be input to the filter100, and an output voltage (represented by VoinFIG.1) may be output by the filter100. The band pass filter100may significantly reduce low and high frequencies while allowing frequencies within a passband frequency range to be transmitted through the filter100substantially unaffected. It should be understood that the simplified filter100described above is merely a simplified example of a band pass filter and that aspects of the present disclosure may be applied to more complex band pass filters. Additionally, aspects of the present disclosure may be applied to other types of filters, including, for example, a low-pass filter or a high-pass filter.

FIG.2is a schematic of an example embodiment of a band pass filter200according to aspects of the present disclosure. A signal path201may be defined between an input202and an output204of the filter200. An input voltage (represented by V; inFIG.1) may be input to the filter200between the input202and a ground206of the filter200. An output voltage (represented by VoinFIG.1) may be output by the filter200between the output204and the ground206.

The filter200may include a first inductor208and a first capacitor210electrically connected in parallel with each other. The first inductor208and first capacitor210may be electrically connected between the signal path201and the ground206. The filter200may include a second inductor212and second capacitor214electrically connected in parallel with each other. The second inductor212and second capacitor214may be connected in series with the signal path201(e.g., may form a portion of the signal path201). The filter200may include a third inductor210and third capacitor214electrically connected in parallel with each other. The third inductor210and third capacitor214may be electrically connected between the signal path201and the ground206. The third inductor210and third capacitor214may be connected in series with the signal path201(e.g., may form a portion of the signal path201). The filter200may include a fourth inductor220and fourth capacitor222electrically connected in parallel with each other. The fourth inductor220and fourth capacitor222may be electrically connected between the signal path201and the ground206.

The inductance values of the inductors208,212,216,220and the capacitance values of the capacitors210,214,218,222may be selected to produce the desired band pass frequency range of the band pass filter200. The band pass filter200may significantly reduce frequencies outside of the passband frequency range while allowing frequencies within a passband frequency range to be transmitted through the filter200substantially unaffected.

FIGS.3A and3Bare perspective views of an example band pass filter300according to aspects of the present disclosure.FIG.3Cis a side elevation view of the filter300ofFIGS.3A and3B. Referring toFIGS.3A through3C, the band pass filter300may include a plurality of dielectric layers (transparent for clarity). Referring toFIG.3C, a first dielectric layer304, second dielectric layer306, and third dielectric layer308may be stacked to form a monolithic structure. The filter300may be mounted to a mounting surface302, such as a printed circuit board. Conductive layers303,305,307,309may be formed on the dielectric layers304,306,308. Conductive layer303may be formed on a bottom surface of the first dielectric layer304. Conductive layers305,307may be formed on a top surface and a bottom surface, respectively of the second dielectric layer306. A ground may include a ground plane312that is exposed and/or terminated along a bottom surface of the filter300(the bottom surface of conductive layer303. The mounting surface may include one or more terminals310for connection with the ground plane312.

FIGS.4A through4Eare a series of sequential top down views of the filter300in which an additional layer is shown in each Figure. More specifically,FIG.4Aillustrates the mounting surface302and the first conductive layer303.FIG.4Billustrates the ground plane312formed on the bottom surface of the first dielectric layer304.FIG.4Cadditionally illustrates the conductive layer305formed on the top surface of the first dielectric layer304.FIG.4Dadditionally illustrates conductive layer307that is formed on the second dielectric layer306.FIG.4Eillustrates the conductive layer309formed on the third layer308. The dielectric layers304,306,308are transparent to show the relative relocations of the various patterned conductive layers303,305,307,309.

The band pass filter300may include a signal path316having an input318and an output320. The signal path316may electrically connect the input318and the output320. More specifically, the signal path316may include a plurality of dielectric layers and/or vias formed in and on the plurality of dielectric layers304,306,308and electrically connected between the input318and the output320. The signal path316may include one or more vias322may electrically connecting the input318with an intermediary conductive layer324disposed between the first layer304and second layer306. The signal path316may include one or more vias326electrically connecting the intermediary layer324with a conductive layer328formed on the second dielectric layer306.

A first capacitor may be formed between a portion336of the signal path316formed on an upper surface of the second layer360and a conductive layer330formed on a lower surface of the second layer306of dielectric material. The conductive layer330may be electrically connected with the ground plane312. The first capacitor of the filter300may correspond with the first capacitor210of the circuit diagram200ofFIG.2. The conductive layer330may be capacitively coupled with a portion336of the signal path316. The conductive layer330may be spaced apart from the portion336of the signal path316in a Z-direction. The conductive layer330may be electrically connected with the ground plane312by one or more vias334.

The first capacitor may be insensitive to relative misalignment of the electrodes of the first capacitor, which may be described as being “self-aligning.” As best seen inFIG.4D, the portion336of the signal path316may generally be dimensionally smaller (e.g., in the X- and Y-directions) than the conductive layer330of the first capacitor. Additionally the portion336of the signal path316may define connections in the X-Y plane with other elements and other parts of the signal path316. Such connections may be sized such that a slight misalignment in the X-direction or Y-direction does not change a capacitive area of the first capacitor. More specifically, a size of an effective overlap area (e.g., in the X-Y plane) between the conductive layer330and the portion336of the signal path316may be insensitive to slight misalignment in the X-direction or Y-direction of the second and third layers304,306.

For example, the portion336of the signal path316may include a tab337(e.g., extending in the X-direction) that has a width (e.g., in the Y-direction) equal to a width (e.g., in the Y-direction) of the connector portion338on an opposite side of the portion336. Similarly, connections340may extend from opposite sides of the portion336(e.g., in the Y-direction) that may have equal widths. As a result, relative misalignment in the Y-direction may not alter the overlapping area between the conductive layer330and the portion336of the signal path316.

The filter300may include a first inductor342electrically connected with the signal path316and ground plane312. The first inductor342of the filter300may correspond with the first inductor208of the circuit diagram200ofFIG.2. The first inductor342may be connected with the portion336of the signal path316that forms the first capacitor by a connector portion338. The first inductor342may be electrically connected with the ground plane312by one or more vias344(best seen inFIG.3B).

The signal path316of the filter300may include a second inductor346, which may correspond with the second inductor212of the circuit diagram200ofFIG.2. The second inductor346may be formed on the third layer308(best seen inFIG.3C).The second inductor346may be electrically connected at each of a first location349and a second location351with the signal path316. In other words, the second inductor346may form a portion of the signal path316between the input318and the output320.

One or more vias348may connect the second inductor346at the first location349with a portion354of the signal path316on the second layer306(best seen inFIGS.3B,4D, and4E). One or more vias348may connect the first inductive element346at the second location351with each of a portion369of the signal path316on the top surface of the second layer306and with a conductive layer352on the bottom surface of the second layer306(which forms a second capacitor with the portion354of the signal path316, described below). As best seen inFIGS.3A and4E, the inductor346may have four corners. As such, the first inductor346may form greater than half of a “loop.”

The second capacitor may be formed between the conductive layer352and the portion354of the signal path316. The second capacitor may correspond with the second capacitor214of the circuit diagram200ofFIG.2. The second capacitor may be a self-aligning capacitor.

The third inductor356of the filter300may correspond with the third inductor216of the circuit diagram200ofFIG.2. The third inductor356may be connected by one or more vias360at a first location357with the portion369of the signal path316that is connected with the second inductor346. The third inductor356may be connected by one or more vias360at a second location359with the portion361of the signal path316that is connected with the output320. The portion361of the signal path316may be electrically connected with the output320by one or more vias366and/or intermediary layers368. In other words, the third inductor356may form a portion of the signal path316between the second inductor346and the output320. The third inductor356may have a greater width at a protrusion364than along other portions of the third inductor356.

A third capacitor may be formed in parallel with third inductor356. The third capacitor may correspond with the third capacitor214of the circuit diagram200ofFIG.2. The third capacitor of the filter300may include a conductive layer367that is capacitively coupled with the portion369of the signal path316.

A fourth inductor370may be electrically connected with the signal path316at a first location371and with the ground plane312at a second location373by vias374. The vias374may be connected by intermediary layers376. The fourth inductor370of the filter300may correspond with the fourth inductor220of the of the circuit diagram200ofFIG.2The fourth inductor370of the filter300may be connected with the signal path316at the portion361of the signal path316that is electrically connected with the output320. The fourth inductor370may have three corners372and form approximately one quarter of a loop.

A fourth capacitor may include a conductive layer380that is capacitively coupled with the portion361of the signal path316that is connected with the output320. The conductive layer380of the fourth capacitor may be electrically connected with the ground plane312by vias382. The fourth capacitor may correspond with the fourth capacitor222of the circuit diagram200ofFIG.2.

Inductance is generally proportional to the length of an inductive element, but inversely proportional to a width of the inductive element. In other words, the inductance may be proportional to a length-to-average-width ratio of the inductive element. As such, small adjustments to the width and length of an inductive element can be used to fine tune inductance. This may be particularly useful for inductors designed to exhibit very low inductance, for example, for high frequency applications.

FIG.5Ais a top down view of the third inductor356of the filter300, described above with reference toFIGS.3A through4E. As indicated above, the inductor356may be connected with vias360at the first location357and the second location359.

The inductor356may have an outer perimeter502. The outer perimeter502may define the boundary of the conductive layer that forms the inductor356.

The outer perimeter502may include a first straight edge504that faces outward in a first direction (e.g., the positive Y-direction). The outer perimeter502may include a second straight edge506that is parallel to the first straight edge504and faces outward in the first direction (e.g., the positive Y-direction). The second straight edge506may be offset from the first straight edge504by an offset distance508. The offset distance508may be less than about 500 microns. In some embodiments, offset distance508may be less than about 90% of a first width510of the inductor at the first straight edge504. In some embodiments, the offset distance508may be approximately equal to a single minimum line width510(e.g., about 50 microns). The minimum line width510(represented by grid points inFIG.5A) may be defined as the smallest feature size that can be accurately patterned.

The outer perimeter502may include a width discontinuity edge509extending between the first straight edge504and the second straight edge506. The width discontinuity edge509may be perpendicular to the first straight edge504and second straight edge506.

The inductor356may have the first width510at the first straight edge504(e.g., proximate the width discontinuity edge509). The first width510may be defined in a local width direction (e.g., the Y-direction) that is perpendicular to the first straight edge504. The inductor356may have a second width512at the second straight edge506(e.g., proximate the width discontinuity edge509). The second width512may be defined in the local width direction (e.g., the Y-direction). The second width512may be greater than the first width510. The offset distance508may be equal to the second width512minus the first width510.

As described above with reference toFIGS.3A through4E, the inductor356may be connected with vias at the first location537and the second location538. A longitudinal centerline514may extend along the inductor356between the first location537and the second location538. The longitudinal centerline514may have a length equal to an effective length of the inductor356. The longitudinal centerline514may include one or more corners516. The width discontinuity edge509may be spaced apart from a corner516of the longitudinal centerline514of the inductor356by a distance518. The distance518may be at least 30 microns. In this example, the distance518corresponds with an effective length of a tab or protrusion364which acts to the increase the width of the inductor356.

The inductor356may have a variety of widths defined in respective local width directions that are perpendicular to the longitudinal centerline514of the inductor356. The inductor356may have an average width that is an average of the widths of the inductor356respectively weighted by lengths associated with each along the longitudinal centerline514. A length-to-average-width ratio of the inductor356may be defined as the effective length of the inductor356divided by the average width of the inductor356.

Adjusting the dimensions (e.g., offset distance508, effective length518) of the one or more of the protrusions364can be used to finely tune the average width and length-to-average-width ratio of the inductor356, and thereby finely tune the inductance of the inductor356. Example average widths and length-to-average-width-ratios are provided in the “Examples” section.

Referring toFIG.5B, an inductor530may be similar to a third inductor820of a filter800described below with reference toFIGS.8A through9E, except that the inductor530illustrated inFIG.5Bincludes offset edges according to aspects of the present disclosure.

The inductor530may have an outer perimeter532. The outer perimeter532may define the boundary of the conductive layer that forms the inductor530. The outer perimeter502may include a first straight edge534that faces outward in a first direction (e.g., the positive Y-direction). The outer perimeter532may include a second straight edge536that is parallel to the first straight edge534and faces outward in the first direction (e.g., the positive Y-direction). The second straight edge536may be offset from the first straight edge534by an offset distance538. The offset distance538may be less than about 500 microns. In some embodiments, the offset distance538may be approximately equal to a single minimum line width510(e.g., about 50 microns).

The outer perimeter532may include a width discontinuity edge539extending between the first straight edge534and the second straight edge536(e.g., in the Y-direction). The width discontinuity edge539may be perpendicular to the first straight edge534and second straight edge536.

The inductor530may have a third straight edge540and a second discontinuity edge542extending between the second straight edge536and the third straight edge540. The third straight edge540may be parallel and aligned with the first straight edge534such that a tab or protrusion544is formed. The protrusion544may have a length546in a direction parallel with the second straight edge536.

The inductor530may be connected with vias at a first location550and a second location552. A longitudinal centerline554may extend along the inductor530between the first location550and the second location552. The longitudinal centerline554may have a length556equal to an effective length of the inductor530.

The inductor530may include an additional protrusion558. The additional protrusion558may be defined with respect to straight edges560and width discontinuity edges561of the outer perimeter532of the inductor530in the same manner as the protrusion544. An offset distance562associated with the additional protrusion558may be defined between the straight edged560in the same manner as the protrusion544.

The additional protrusion558(including associated width discontinuity edges561) may be symmetric about the longitudinal centerline554and/or a lateral centerline563with the protrusion554(including associated with discontinuity edges539,542). The entire inductor540may be symmetric about the longitudinal centerline554and/or the lateral centerline563.

The inductor530may have a first width564at the first straight edge534. The first width564may be defined in a local width direction (e.g., the Y-direction) that is perpendicular to the first straight edge534. The inductor530may have a second width566at the second straight edge536(e.g., proximate the width discontinuity edge539). The second width566may be defined in the local width direction (e.g., the Y-direction). The second width566may be greater than the first width564. In this example, a difference between the second width566and the first width564may be equal to the sum of the offset distances542,561.

The inductor530may have first lengths570along the longitudinal centerline554associated with the first width564. The inductor530may have a length along the second width566that is equal to the length of the546of the protrusions554,558. The inductor530may have an average width that is a weighted average of the widths564,566of the inductor530according to the lengths546,570associated with the widths564,566. A length-to-average-width ratio of the inductor530may be defined as the effective length556of the inductor530divided by the average width of the inductor530.

Adjusting the dimensions and/or locations of one or more of the protrusions558can be used to finely tune the average width and length-to-average-width ratio of the inductor530, and thereby finely tune the inductance of the inductor530. Example average widths and length-to-average-width-ratios are provided in the “Examples” section.

FIG.5Cis a top down view of an inductor572according to aspects of the present disclosure. The inductor572may be similar to a third inductor1020of a filter1000described below with reference toFIGS.10A through11D, except that the inductor572may include a first straight edge576and a second straight edge577that is offset from the first straight edge576by an offset distance575in the manner described above with reference toFIGS.5A and5B. The first straight edge576may be perpendicular to second straight edge577. A width discontinuity edge578may be connected between the straight edges576,577. The width discontinuity edge578may be perpendicular to the straight edges576,577. The offset distance575may be defined in a direction perpendicular to the straight edges576,577. The inductor572may include a protrusion574associated with the with the width discontinuity edge578.

The inductor572may be connected with vias at a first location581and a second location583. A longitudinal centerline571may be defined between the first location and second location581,583. An effective length579of the inductor572may be defined along the longitudinal centerline571between the first location and second location581,583. The inductor572may have a first width580and a second width582that may be defined relative to the edges576,577in the same manner as described above with reference toFIGS.5A and5B. The inductor572may have first and second lengths584,585that are respectively associated with the first and second widths580,582.

The inductor572may have an average width that is a weighted average of the widths580,582of the inductor572according to the respective associated lengths584,585along the longitudinal centerline571. A length-to-average-width ratio of the inductor572may be defined as the effective length579of the inductor572divided by the average width of the inductor572. Adjusting the dimensions and/or locations the protrusion574can be used to finely tune the average width and length-to-average-width ratio of the inductor572, and thereby finely tune the inductance of the inductor572. Example average widths and length-to-average-width-ratios are provided in the “Examples” section.

Referring toFIG.5D, an inductor587may include two protrusions588defined relative to various respective straight edges589, lengths596, offset distances597, and discontinuity edges596in the manner described with reference toFIGS.5A and5B. The inductor587may be similar to a fourth inductor1024of the filter1000described below with reference toFIGS.10A through11D, except that the inductor587includes the two protrusions588.

The inductor587may have an effective length equal to a sum of a first length590and a second length591along a longitudinal centerline592between a first location593and a second location594. The first and second lengths590,591may be defined parallel with the longitudinal centerline592. The inductor587and longitudinal centerline592may include a corner595.

The inductor587may have various widths measured perpendicular to the straight edges589. The various widths may be defined along the longitudinal centerline592. The inductor587may have an average width that is calculated in a similar manner as described above with reference toFIG.5A. Adjusting the dimensions and/or locations of one or more of the protrusions586can be used to finely tune average width and length-to-average-width ratio of the inductor587, and thereby finely tune the inductance of the inductor587. Example average widths and length-to-average-width-ratios are provided in the “Examples” section.

III. Additional Example Embodiments

FIG.6Aillustrates a perspective view of another embodiment of a multilayer filter600according to aspects of the present disclosure.FIG.6Billustrates another perspective view of the multilayer filter600ofFIG.6A. The filter600may generally be configured in a similar manner as the filter300described above with reference toFIGS.3through5D. The filter600may include an input602, an output604, and a signal path606connecting the input602and the output604. The filter600may also include a ground plane608electrically connected with one or more ground electrodes610.

The filter600may include a first inductor612that is electrically connected with the ground plane608. The first inductor612may correspond with the first inductor208of the circuit diagram200described above with reference toFIG.2. The filter600may include a first capacitor614electrically coupled with the ground plane608. The first capacitor614may correspond with the first capacitor210of the circuit diagram200described above with reference toFIG.2.

The filter600may include a second inductor616and a second capacitor618that are connected in parallel with each other. The second inductor616and second capacitor618may correspond with the second inductor212and second capacitor214, respectively, of the circuit diagram200described above with reference toFIG.2. The second inductor616and second capacitor618may form a portion of the signal path606between the input602and the output604. The filter600may include a third inductor620and third capacitor622that are connected in parallel with each other and may form a portion of the signal path606between the input602and the output604. The third inductor620and third capacitor622may correspond with the third inductor216and third capacitor218, respectively, of the circuit diagram200described above with reference toFIG.2. Lastly, the filter600may include a fourth inductor624and fourth capacitor626that are connected in parallel with each other and connected between the signal path606and the ground plane608. The fourth inductor624and fourth capacitor626may correspond with the fourth inductor220and the fourth capacitor222, respectively, of the circuit diagram200described above with reference toFIG.2.

The inductors612,616,620,624and capacitors614,618,622,626may be connected by vias627in a similar manner as described above with reference toFIGS.3through5D. Each of the inductors612,616,620,624may be connected with the signal path606at a respective first location and connected with the signal path606or the ground plane608at a respective second location. Each of the inductors612,616,620,624may have a respective effective length (e.g., in the X-Y plane) between the first location and the second location. Additionally, each of the inductors612,616,620,624may have a respective width along its respective effective length.

FIG.6Cis a side elevation view of the filter600ofFIGS.6A and6B. The band pass filter600may include a plurality of dielectric layers (transparent for clarity inFIGS.6A and6B). Referring toFIG.6C, a first layer632, a second layer636, and a third layer640may be stacked to form a monolithic structure. Conductive layers630,634,638,642may be formed on the dielectric layers632,636,640. Conductive layer630may be formed on a bottom surface of the first dielectric layer632. Conductive layers634,638may be formed on a top surface and a bottom surface, respectively of the second dielectric layer636. Conductive layer642may be formed on a top surface of the third dielectric layer640.

FIGS.7A through7Dare a series of sequential top down views of the filter600ofFIGS.6A through6Cin which an additional dielectric layer is shown in each Figure. More specifically,FIG.7Aillustrates a mounting surface628, such a printed circuit board. The first conductive layers630may include the ground plane608, which may be formed on a bottom surface and a top surface of the first layer632.FIG.7Badditionally illustrates the second conductive layer634formed on the first dielectric layer632. The second conductive layer634may include the first capacitor614, second capacitor618, third capacitor622and forth capacitor626.FIG.7Cadditionally illustrates the third conductive layer638that is formed on the second dielectric layer636. The third conductive layer638may include portions of the signal path606and the first inductor612.FIG.7Dillustrates the fourth conductive layer642formed on the fourth dielectric layer640. The fourth conductive layer642may include the second inductor616, third inductor622, and fourth inductor624. The dielectric layers632,636,640are transparent to show the relative relocations of the various patterned conductive layers630,634,638,642.

FIG.8Aillustrates a perspective view of another embodiment of a multilayer filter800according to aspects of the present disclosure. The filter800may generally be configured in a similar manner as the filter300described above with reference toFIGS.3through5D. The filter800may include an input802, an output804, and a signal path806connecting the input802and the output804. The filter800may also include a ground plane808electrically connected with one or more ground electrodes810.

The filter800may include a first inductor812that is electrically connected with the ground plane808. The first inductor812may correspond with the first inductor208of the circuit diagram200described above with reference toFIG.2. The filter800may include a first capacitor814electrically coupled with the ground plane808. The first capacitor814may correspond with the first inductor capacitor210of the circuit diagram200described above with reference toFIG.2. The filter800may include a second inductor816and second capacitor818that are connected in parallel with each other. The second inductor816and second capacitor818may correspond with the second inductor212and second capacitor214, respectively, of the circuit diagram200described above with reference toFIG.2. The second inductor816and second capacitor818may form a portion of the signal path806between the input802and the output804. The filter800may include a third inductor820and third capacitor822that are connected in parallel with each other and may form a portion of the signal path806between the input802and the output804. The third inductor820and third capacitor822may correspond with the third inductor216and third capacitor218, respectively, of the circuit diagram200described above with reference toFIG.2. Lastly, the filter800may include a fourth inductor824and fourth capacitor826that are connected in parallel with each other and connected between the signal path806and the ground plane808. The fourth inductor824and fourth capacitor826may correspond with the fourth inductor220and the fourth capacitor222, respectively, of the circuit diagram200described above with reference toFIG.2.

The inductors812,816,820,824and capacitors814,818,822,826may be connected by vias827in a similar manner as described above with reference toFIGS.3through5D. Each of the inductors812,818,820,824may be connected with the signal path806at a respective first location and connected with the signal path806or the ground plane808at a respective second location. Each of the inductors812,818,820,824may have a respective effective length (e.g., in the X-Y plane) between the first location and the second location. Additionally, each of the inductors812,818,820,824may have a respective width along its respective effective length.

FIG.8Bis a side elevation view of the filter800ofFIG.8A. The band pass filter800may include a plurality of dielectric layers (transparent for clarity inFIG.8A). Referring toFIG.8B, a first layer832, a second layer836, and a third layer840may be stacked to form a monolithic structure. Conductive layers830,834,838,842may be formed on the dielectric layers832,836,840. Conductive layer830may be formed on a bottom surface of the first dielectric layer832. Conductive layers834,838may be formed on a top surface and a bottom surface, respectively of the second dielectric layer836. Conductive layer842may be formed on a top surface of the third dielectric layer840.

FIGS.9A through9Dare a series of sequential top down views of the filter600ofFIGS.8A and8Bin which an additional dielectric layer is shown in each Figure. More specifically,FIG.9Aillustrates a mounting surface828, such as a printed circuit board. The first conductive layers830may include the ground plane808, which may be formed on a bottom surface and a top surface of the first layer832.FIG.9Badditionally illustrates the second conductive layer834formed on the first dielectric layer832. The second conductive layer834may include the first capacitor814, second capacitor818, third capacitor822and forth capacitor826.FIG.9Cadditionally illustrates the third conductive layer838that is formed on the second dielectric layer836. The third conductive layer838may include portions of the signal path806and the first inductor812.FIG.9Dillustrates the fourth conductive layer842formed on the fourth dielectric layer840. The fourth conductive layer842may include the second inductor816, third inductor822, and fourth inductor824. The dielectric layers832,836,840are transparent to show the relative relocations of the various patterned conductive layers830,834,838,842.

FIG.10Aillustrates a perspective view of another embodiment of a multilayer filter1000according to aspects of the present disclosure.FIG.10Billustrates another perspective view of the multilayer filter1000ofFIG.10A. The filter1000may generally be configured in a similar manner as the filter300described above with reference toFIGS.3through5D. The filter1000may include an input1002, an output1004, and a signal path1006connecting the input1002and the output1004. The filter1000may also include a ground plane1008electrically connected with one or more ground electrodes1010.

The filter1000may include a first inductor1012that is electrically connected with the ground plane1008. The first inductor1012may correspond with the first inductor208of the circuit diagram200described above with reference toFIG.2. The filter1000may include a first capacitor1014electrically coupled with the ground plane1008. The first capacitor1014may correspond with the first inductor capacitor210of the circuit diagram200described above with reference toFIG.2. The filter1000may include a second inductor1016and second capacitor1018that are connected in parallel with each other. The second inductor1016and second capacitor1018may correspond with the second inductor212and second capacitor214, respectively, of the circuit diagram200described above with reference toFIG.2. The second inductor1016and second capacitor1018may form a portion of the signal path1006between the input1002and the output1004. The filter1000may include a third inductor1020and third capacitor1022that are connected in parallel with each other and may form a portion of the signal path1006between the input1002and the output1004. The third inductor1020and third capacitor1022may correspond with the third inductor216and third capacitor218, respectively, of the circuit diagram200described above with reference toFIG.2. Lastly, the filter1000may include a fourth inductor1024and fourth capacitor1026that are connected in parallel with each other and connected between the signal path1006and the ground plane1008. The fourth inductor1024and fourth capacitor1026may correspond with the fourth inductor220and the fourth capacitor222, respectively, of the circuit diagram200described above with reference toFIG.2.

The inductors1012,1016,1020,1024and capacitors1014,1018,1022,1026may be connected by vias1027in a similar manner as described above with reference toFIGS.3through5D. Each of the inductors1012,10110,1020,1024may be connected with the signal path1006at a respective first location and connected with the signal path1006or the ground plane1008at a respective second location. Each of the inductors1012,10110,1020,1024may have a respective effective length (e.g., in the X-Y plane) between the first location and the second location. Additionally, each of the inductors1012,10110,1020,1024may have a respective width along its respective effective length.

FIG.10Bis a side elevation view of the filter1000ofFIGS.10A and10B. The band pass filter1000may include a plurality of dielectric layers (transparent for clarity inFIG.10A). Referring toFIG.10B, a first layer1032, a second layer1036, a third layer1040may be stacked to form a monolithic structure. Conductive layers1030,1034,1038,1042may be formed on the dielectric layers1032,1036,1040. Conductive layer1030may be formed on a bottom surface of the first dielectric layer1032. Conductive layers1034,1038may be formed on a top surface and a bottom surface, respectively of the second dielectric layer1036. Conductive layer1042may be formed on a top surface of the third dielectric layer1040.

FIGS.11A through11Dare a series of sequential top down views of the filter600ofFIGS.10A and10Bin which an additional dielectric layer is shown in each Figure. More specifically,FIG.11Aillustrates a mounting surface1028, such a printed circuit board. The first conductive layer1030may include the ground plane1008, which may be formed on a bottom surface and a top surface of the first layer1030.FIG.11Badditionally illustrates the second conductive layer1034formed on the first dielectric layer1032. The second conductive layer1034may include the first capacitor1014, second capacitor1018, third capacitor1022and forth capacitor1026.FIG.11Cadditionally illustrates the third conductive layer1038that is formed on the second dielectric layer1036. The third conductive layer1038may include portions of the signal path1006and the first inductor1012.FIG.11Dillustrates the fourth conductive layer1042formed on the fourth dielectric layer1040. The fourth conductive layer1042may include the second inductor1016, third inductor1022, and fourth inductor1024. The dielectric layers1032,1036,1040are transparent to show the relative relocations of the various patterned conductive layers1030,1034,1038,1042.

The various embodiments of the filter described herein may find application in any suitable type of electrical component. The filter may find particular application in devices that receive, transmit, or otherwise employ high frequency radio signals. Example applications include smartphones, signal repeaters (e.g., small cells), relay stations, and radar.

V. Testing and Simulation Data

Computer modeling was used to simulate multilayer filters according to aspects of the present disclosure. Additionally, filters were built and tested.

The thicknesses of the dielectric layers may generally be less than about 180 micrometers (“microns”). For instance, in some embodiments, the first layers304,632,832,1032may be about 60 microns thick. The second layers306,636,836,1036may be about 20 microns thick. The third layers308,640,840,1040may be about 60 microns thick.

In some embodiments, the overall length of the filters may be 4.3 mm. The overall width may be about 4 mm. The overall thickness may be about 230 microns.

FIGS.12-17present test results and simulation data for the various filters. Referring toFIG.12, a multilayer filter according to aspects of the present disclosure was built and tested. Measured insertion loss (S21) values and measured return loss (S11) values are plotted from 0 GHz to 45 GHz. Simulated insertion loss (S21) values and simulated return loss (S11) values are plotted from 0 GHz to 35 GHz. The measured pass band is from about 13.2 GHz to about 15.8 GHz.

Referring toFIG.13, a multilayer filter according to aspects of the present disclosure was built and tested. Measured insertion loss (S21) values and measured return loss (S11) values are plotted from 0 GHz to 45 GHz. Simulated insertion loss (S21) values and simulated return loss (S11) values are plotted from 0 GHz to 35 GHz. The pass band is from about 16.1 GHz to about 18.2 GHz.

Referring toFIG.14, the multilayer filter300described above with reference toFIGS.3A through4Ewas both simulated and built and physically tested. Measured insertion loss (S21) values and measured return loss (S11) values are plotted from 0 GHz to 45 GHz. Simulated insertion loss (S21) values and simulated return loss (S11) values are plotted from 0 GHz to 35 GHz. The pass band is from about 17.0 GHz to about 21.2 GHz.

Referring toFIG.15, the multilayer filter600described above with reference toFIGS.6A through7Dwas simulated. Simulated insertion loss (S21) values and simulated return loss (S11) values are plotted from 0 GHz to 50 GHz. The pass band is from about 24.6 GHz to about 27.8 GHz.

Referring toFIG.16, the multilayer filter800described above with reference toFIGS.8A through9Dwas simulated. Simulated insertion loss (S21) values and simulated return loss (S11) values are plotted from 0 GHz to 55 GHz. The pass band is from about 34.6 GHz to about 37.4 GHz.

Referring toFIG.17, the multilayer filter1000described above with reference toFIGS.10A through11Dwas simulated. Simulated insertion loss (S21) values and simulated return loss (S11) values are plotted from 0 GHz to 70 GHz. The pass band is from about 42.9 GHz to about 46.6 GHz.

EXAMPLES

It should be understood that the following dimensions and ratios are merely given as examples and do not limit the scope of the present disclosure. For example, in some embodiments, processes may be employed that can achieve greater precision in shaping the conductive layers, resulting in a smaller minimum line width.

Referring again toFIG.5A, the inductor356may have dimensions as shown where each minimum line width510(in the X-direction and Y-direction) is about 51 microns. In other words, for the purposes of this Examples section,FIG.5Amay be considered drawn to scale. The inductor356has an average width of approximately 5.36 minimum line widths501(e.g., about 272 microns). The total effective length is 14 minimum line widths501(e.g., about 711 microns). Thus the length-to-average-width ratio of the inductor356is approximately 2.61.

In comparison, a similar inductor lacking the protrusion364would have an average width of about 5.14 minimum line widths501(e.g., about 261 microns) and a length-to-average-width ratio of about 2.72. Thus, the protrusion364increased the average width by about 4 percent and decreased the length-to-average-width ratio by about 4 percent. Furthermore, increasing the distance518(e.g., length) associated with the protrusion364by a single minimum line width501(e.g., about 51 microns) would increase the average width of the inductor534by only about 1.3 percent and decrease the length-to-average-width ratio by only about 1.3 percent. Thus, adjusting the dimensions of the protrusion364can be used to finely tune the length-to-average-width ratio, and thereby finely tune the inductance of the inductor356.

Referring again toFIG.5B, the inductor530may have dimensions as shown where each minimum line width510(in the X-direction and Y-direction) is about 51 microns. In other words, for the purposes of this Examples section,FIG.5Bmay be considered drawn to scale. The inductor530may have an average width of about 5.29 minimum line widths501(e.g., about 269 microns) and a length-to-average-width ratio of about 1.32. In comparison, a similar inductor lacking the protrusions588would have an average width of 4 minimum line widths501(e.g., about 203 microns) and a length-to-average-width ratio of about 1.75. Thus, the protrusions544,558increased the average width by about 32 percent and decreased the length-to-average-width ratio by about 24 percent. Furthermore, increasing the length546of either protrusion558by a single minimum line width510would increase the average width of the inductor530by only about 8.1 percent and decrease the length-to-average-width ratio by only about 8.8 percent. Thus, adjusting the dimensions of one or more of the protrusions544,558can be used to finely tune the length-to-average-width ratio, and thereby finely tune the inductance of the inductor530.

Referring again toFIG.5C, the inductor572may have dimensions as shown where each minimum line width510(in the X-direction and Y-direction) is about 51 microns. In other words, for the purposes of this Examples section,FIG.5Cmay be considered drawn to scale. The inductor572may have an average width of about 6.8 minimum line widths501(e.g., about 345 microns) and a length-to-average-width ratio of about 0.88. In comparison, a similar inductor lacking the protrusion574would have an average width of 6 minimum line widths501(e.g., about 305 microns) and a length-to-average-width ratio of about 1. Thus, the protrusion574increased the average width by about 14 percent and decreased the length-to-average-width ratio by about 12 percent.

Furthermore, decreasing an effective length (the second length585) of the protrusion574by a single minimum line width510(e.g., about 51 microns) would increase the average width of the inductor572by only about 2.5 percent and decrease the length-to-average-width ratio by only about 2.44 percent. Thus, adjusting the dimensions of the protrusion574can be used to finely tune the length-to-average-width ratio, and thereby finely tune the inductance of the inductor572.

Referring again toFIG.5D, the inductor587may have an average width of about 4.8 minimum line widths501(e.g., about 244 microns) and a length-to-average-width ratio of about 2.08. In comparison, a similar inductor lacking the protrusions588would have an average width of 4.4 minimum line widths510(e.g., about 224 microns) and a length-to-average-width ratio of about 2.27. Thus, the protrusions588increased the average width by about 9.1 percent and decreased the length-to-average-width ratio by about 8.3 percent.

Furthermore, increasing the effective length596of either protrusion588by a single minimum line width510(e.g., about 51 microns) would increase the average width of the inductor587by only about 2.08 percent and decrease the length-to-average-width ratio by only about 2.04 percent. Thus, adjusting the dimensions of one or more of the protrusions588can be used to finely tune the length-to-average-width ratio, and thereby finely tune the inductance of the inductor587.

Test Methods

Referring toFIG.18, a testing assembly1800can be used to test performance characteristics, such as insertion loss and return loss, of a multilayer filter1802according to aspects of the present disclosure. The filter1802can be mounted to a test board1804. An input line1806and an output line1808were each connected with the test board1804. The test board1804may include microstrip lines1810electrically connecting the input line1806with an input of the filter1802and electrically connecting the output line1808with an output of the filter1802. An input signal was applied to the input line using a source signal generator (e.g., a 1806 Keithley 2400 series Source Measure Unit (SMU), for example, a Keithley 2410-C SMU) and the resulting output of the filter1802was measured at the output line1808(e.g., using the source signal generator). This was repeated for various configurations of the filter.