Systems and methods for memory structure comprising a PPROM and an embedded flash memory

A memory structure that combines embedded flash memory and PPROM. The PPROM can be used as a memory structure. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. The PPROM cells are stacked on top of the flash memory cells and the PPROM density can be increased by implementing three-dimensional PPROM structure.

BACKGROUND

1. Field of the Invention

The invention relates generally to memory structures, and more particularly to the design, fabrication, and use of memory structures that combine embedded flash memory and Physical Programmable Read-Only Memory (PPROM) structures.

2. Background of the Invention

Because of its small size and low cost, PPROM Technology is used in many conventional memory applications. In order to further increase the density of PPROM memory devices, three-dimensional PPROM structures can be used. In a three-dimensional PPROM structure, layers of PPROM cells are stacked on top of each other. In general, several techniques can be used to create three-dimensional PPROM structures; however, these approaches are well known and will not be discussed herein beyond the approaches used in the embodiments described below.

Many conventional memory devices also use flash memory cells. Many conventional flash memory cells use floating gate technology to store one or more bits of information in the floating gate when program voltages are applied. The operation of floating gate flash memory devices is well known and will not be discussed herein for the sake of brevity. More recently, however, floating gate technology has been displaced by the use of other technologies that can be scaled to meet increasing memory density demands. For example, SONOS technology has become more prevalent in many applications. In a SONOS cell, the cell comprises a silicon layer (S), an oxide layer (O), a nitride layer (N), another oxide layer (O), and another silicon layer (S). A programming voltage applied to the SONOS stack causes a bit of data, or a charge, to be stored in the nitride layer. Then applying the appropriate read voltages to a SONOS cell, it can be determined whether the cell has been programmed.

While there have been advancements in conventional memory cell design, such as the development of PPROM and SONOS flash memory, new applications are constantly driving new memory requirements that cannot necessarily be met by the use of conventional memory structures. As such demands are likely to continue, and even increase, in the future, it is important to develop new techniques for memory structure design and fabrication.

SUMMARY

A memory structure that combines embedded flash memory and PPROM. The PPROM can be used as a memory structure. The flash memory can be used, e.g., as error replacement cells or back up memory, or additional memory cells.

In one aspect, the PPROM cells are stacked on top of the flash memory cells.

In another aspect, the PPROM density can be increased by implementing three-dimensional PPROM structures.

These and other features, aspects, and embodiments of the invention are described below in the section entitled “Detailed Description.”

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The systems and methods described below are directed to memory structures that combine PPROM cells with flash memory cells. In the embodiments described, the flash memory cells are generally SONOS cells; however, this should not necessarily be seen as limiting the systems and methods described herein to the use of SONOS cells.

It will be clear that other, and future, flash cell structures can be used with the systems and methods described herein in order to achieve the benefits described. Further, while certain specific embodiments of memory structures combining PPROM and flash cells are described below, the specific embodiments described should not be seen as limiting the systems and methods described herein to any particular architecture or design. It will be clear that other combinations, stacking, and arrangements of PPROM and flash memory cells are possible.

As mentioned above PPROM structures can be preferred for their compact size and low cost. Also as explained above, a PPROM structure is programmed by applying appropriate program voltages to the PPROM cell, which then creates a diode within the cell. Poly-diode100illustrated inFIG. 1is an example of a conventional PPROM cell. As can be seen, poly-diode100comprises a P-type poly-silicon layer102and an N-type poly-silicon layer104, separated by an oxide layer106. When appropriate programming voltages are applied to poly-diode100, a breach is created in oxide layer106. The programming voltage is typically a high voltage applied between P-type poly-silicon layer102and N-type poly-silicon layer104. For example, a relatively high voltage, such as 5-20 volts, can be applied between the two conductors. This can be affected by connecting N-type poly-silicon layer104to ground and applying a, e.g., a 5-20 volt programming voltage to P-type poly-silicon layer102. Alternatively, N-type poly-silicon layer104can be coupled with a negative voltage, while P-type poly-silicon layer is coupled with a positive voltage. When no voltage is applied across poly-diode100then the oxide layer is not breached and a diode is not formed.

Thus, by selecting cells and applying a program voltage, or voltages, diodes can be selectively formed so as to program an array of poly diodes comprising a PPROM device. Often, the programming voltage is applied with a polarity such that the more positive voltage is applied to the anode of the diode while the more negative voltage is applied to the cathode; however, it is also possible to program a poly diode using a reverse biasing potential. In order to sense whether poly diode100has been programmed, a voltage, typically lower than that used for programming, is applied to the poly diode. The voltage is applied so as to forward bias diode100. The forward biasing creates a current through diode100that can then be sensed, e.g., using a sense amplifier in order to determine whether oxide layer106is intact or has been breached. If oxide layer106is intact, i.e., meaning a diode has not been formed, then the sense amplifier will not sense any current through cell100. If on the other hand, oxide layer106has been breached, then application of the read voltage will cause the diode formed in cell100to be forward biased, which will result in a current that can be sensed by the sense amplifier.

FIGS. 2a-2cillustrate various poly diode structures that can be used in accordance with the systems and methods described herein.FIG. 2a, for example, is the same as the poly diode structure illustrated inFIG. 1comprising a P-type poly-silicon layer102separated from an N-type poly-silicon layer104by an oxide layer106. InFIG. 2b, however, oxide layer106is on top of a P-type poly-silicon layer102which is on top of a N-type poly-silicon layer104. InFIG. 2c, oxide layer106is below P-type poly-silicon layer102and N-type poly-silicon layer104. It will be clear that any of the various poly-silicon structures known and/or described herein can be used in accordance with the systems and methods described below.

As mentioned, the systems and methods described herein combine PPROM with a flash memory cell such as a SONOS flash memory cell.FIGS. 3-6illustrate various example embodiments of combined PPROM and flash memory structures designed, fabricated, and used in accordance with the systems and methods described herein. It will be apparent, however, that the systems and methods described herein are not necessarily limited to the embodiments illustrated inFIGS. 3-6. As such, the embodiments illustrated inFIGS. 3-6are by way of example only and should not be seen as limiting the systems and methods described herein to any particular embodiment or any particular combination of PPROM and flash memory.

FIG. 3is a diagram illustrating an example memory structure300that combines PPROM with flash memory in accordance with one embodiment of the systems and methods described herein. As can be seen, memory structure300comprises a PPROM cell layer302and a flash memory cell layer304. PPROM cell layer302comprises P-type poly-silicon layers324, thin oxide layer328, and N-type poly-silicon layer310. Thus, PPROM cell layer302comprises individual poly diode structures306formed from P-type poly-silicon layer324, the area326of N-type poly-silicon layer310, that is below the corresponding P-type poly-silicon layer324, and by thin oxide layer328, which separates the two. In the embodiment ofFIG. 3, each poly diode structure306is separated from adjacent poly diode structures by oxide layers330.

Flash memory cell layer304also makes use of N-type poly-silicon layer310, which is separated from a silicon substrate318by oxide layer312, nitrite layer314, and oxide layer316. Thus, in the embodiment ofFIG. 3, memory structure300comprises a SONOS flash memory cell308. Flash memory cell308also comprises a source320and drain322constructed, e.g., by implanting the appropriate type poly-silicon layers within silicon substrate318.

Thus, as can be seen, flash memory cell308and poly diodes306share a poly-silicon line between them. In other words, N-type poly-silicon layer310, which comprises the gate of flash memory cell308, also forms part of poly diode306. Such a construction, i.e., comprising a co-used poly-silicon line, can be preferred in order to reduce the size and complexity of memory structure300. As will be illustrated below, however, other embodiments can be constructed without the use of co-used poly-silicon lines.

In fact,FIG. 4is a diagram illustrating an example memory structure400that does not use co-used poly-silicon lines in accordance with one embodiment of the systems and methods described herein. In structure400, PPROM cell layer402is separated from flash memory cell layer404by an isolation oxide layer410. Thus, each poly diode406comprises an area of P-type poly-silicon layer412above an N-type poly-silicon layer414. The area of poly-silicon layer412above N-type poly-silicon layer414is separated from N-type poly-silicon layer414by thin oxide layer418. Further, each N-type poly-silicon layer414is separated by an oxide layer416.

Flash cell408is then formed by N-type poly layer418, which is separated from silicon substrate426by oxide layer420, nitrite layer422, and oxide layer424. Thus, as mentioned, flash memory cell408is a SONOS-type memory cell. Flash memory cell408also comprises source428and drain430regions within silicon substrate layer426.

As can be seen, poly diode406and flash cell408do not share a common poly-silicon line as with the embodiment illustrated inFIG. 3.

In order to increase the PPROM density, three-dimensional PPROM structures can be implemented in accordance with the systems and methods described herein. For example,FIG. 5is a diagram illustrating a memory structure500comprising a three-dimensional PPROM structure and a flash memory in accordance with one embodiment of the systems and methods described herein. memory structure500comprises a PPROM layer502and a second PPROM layer504above a flash memory cell layer506.

PPROM layer502is constructed from an N-type poly-silicon layer518separated from P-type poly-silicon areas522by a thin oxide layer520. Each poly diode510within PPROM layer502is then separated by oxide layers526. An isolation oxide layer516can also be placed on top of the structure.

FIG. 6is a diagram illustrating an example memory structure600that includes a three-dimensional PPROM structure in accordance with another embodiment of the systems and methods described herein. Structure600comprises a first PPROM layer602, a second PPROM layer604, and a flash memory cell layer606. Unlike the embodiment ofFIG. 5, poly diodes614, comprising PPROM layer602, and poly diode616, comprising PPROM layer604, do not share any co-used poly-silicon lines.

Flash memory cell layer606comprises flash cell608constructed from N-type poly-silicon layer626, ONO layer628, and silicon substrate630with source and drain regions632and634respectively. Thus, there are no co-used poly-silicon layers common to PPROM layer604and flash memory cell layer606.

FIGS. 3-6illustrates specific implementations of a memory structure that comprises PPROM and flash memory in accordance with the systems and methods described herein. It will be clear, however, that the systems and methods described herein are not limited solely to the implementations illustrated inFIGS. 3-6. For example, other implementations can use co-used poly-silicon lines or not use co-used poly-silicon lines in ways not illustrated by the embodiments ofFIGS. 3-6.

Depending on the embodiment, the bottom flash memory can be used, e.g., as an error replacement cell, or a memory storage cell. The use of the flash memory cell will be dependent on the specific implementation. Thus, the specific requirements of a particular implementation will dictate how the flash memory cells used.

FIGS. 7A-7Dillustrate an example method for fabricating a memory structure comprising PPROM and flash memory cells in accordance with one of the embodiment of the systems and methods described herein. The process begins inFIG. 7Awith a deposition of an ONO layer702on top of silicon substrate706. Next, photo resist704is deposited on top of ONO layer702as illustrated. In the next step, photo resist704is photo defined. Electron implantation then is used to define the source708and drain710within silicon substrate706.

Next, as illustrated inFIG. 7B, photo resist layer704is removed and a poly-silicon layer, in this case N-type layer712, is deposited. It will be understood that poly-silicon layer712will be deposited in areas defined by the photo definition process described above. Next, photo resist layer714is then deposited on top of poly-silicon layer712and photo resist layer714is photo defined. Poly-silicon layer712can then be poly etched as required.

In the next step, photo resist layer714can be removed. This step can be followed by the deposition of oxide layer716. Oxide layer716can then be etched back, and this can be followed by the deposition of thin oxide layer718. Next, P-type poly-silicon layer720can be deposited and photo resist layer722can be deposited above poly-silicon layer720as illustrated. Photo resist layer722can then be photo defined, and poly-silicon layer720can be poly etched in accordance with the requirements of the particular design.

Next, as illustrated inFIG. 7d, photo resist layer722can be removed and oxide layer724can then be etched back. Isolation oxide layer726can then be deposited on top of the structure as shown.

The process illustrated byFIG. 7a-7dis just one example process for fabricating a memory structure that includes PPROM and flash memory cells in accordance with the systems and methods described herein. It will be understood that other fabrication processes and techniques can be used in order to achieve a memory structure that includes PPROM and flash memory cells configured as described herein.

For example,FIGS. 8a-8cillustrate one alternative method for fabricating a memory structure that includes PPROM and flash memory cells in accordance with the systems and methods described herein. First, as illustrated inFIG. 8a, an ONO layer804can be deposited on a silicon substrate802. A photo resist layer806can then be deposited on top of ONO layer804, and then photo resist layer806can be photo defined in the next step. This can be followed by implantation of source810and drain808within silicon substrate802.

Next, as illustrated inFIG. 8b, photo resist layer806can be removed and N-type poly-silicon layer812can be deposited on top of ONO layer804. Photo resist layer814can then be deposited on top of poly-silicon layer812and photo resist layer814can then be photo defined in the next step. This can be followed by poly etching of poly-silicon layer812.

Then, as illustrated inFIG. 8c, photo resist layer814can be removed and oxide layer824can be deposited and etched back in the following steps. After oxide layer824is etched back, N-type poly-silicon818can be deposited on top of an isolation oxide layer816as shown. Photo resist layer820can then be deposited and photo defined. This can be followed by poly etching of poly-silicon layer818.

Next, as illustrated inFIG. 8d, photo resist layer820can be removed, oxide layers828and830can be deposited and etched back followed by deposition of thin oxide layer832. P-type poly-silicon layer834can then be deposited. This can then be followed by the deposition of another photo resist layer, which can then be photo defined. This can be followed by poly etching of poly-silicon layer834, and the deposition of isolation oxide layer836, which can then be etched back in the following step.

Thus, the fabrication process illustrated inFIGS. 8a-8dillustrate an example process for fabricating a PPROM and flash memory cell structure in which the PPROM and flash memory cell structures do not share any co-used poly-silicon lines. Again, it will be understood that the process ofFIGS. 8a-8dserve as an example only and that other processes and techniques are possible.

While certain embodiments of the inventions have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the inventions should not be limited based on the described embodiments. Rather, the scope of the inventions described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.