APPLICATION PROGRAMMING INTERFACE TO INDICATE PERFORMANCE OF BARRIER INSTRUCTION

Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Indian Provisional Application No. 202241043444, filed Jul. 29, 2022, entitled “APPLICATION PROGRAMMING INTERFACES FOR THREAD BLOCKS,” the disclosure of which is incorporated herein by reference.

FIELD

At least one embodiment pertains to processing resources used to execute one or more CUDA programs. For example, at least one embodiment pertains to processing resources used to execute one or more CUDA programs that set parameters of one or more clusters of one or more groups of instructions, get parameters of one or more clusters of one or more groups of instructions, share resources between one or more clusters of one or more groups of instructions, and/or synchronize execution between one or more clusters of one or more groups of instructions.

BACKGROUND

Performing computational operations can use significant memory, time, or computing resources. Computer programs can be organized in different ways without various portions that can be performed independently or dependently from one another. Despite computer hardware advances that accelerate or otherwise assist the performance of the various components of a computer program, the advances are generally unable to take into account all the various ways in which computer programs can be structured. A processor may, for example, be unable to take into account various aspects of a computer program, thereby causing delay or other inefficiencies.

DETAILED DESCRIPTION

FIG.1illustrates an example computer system100where software kernels are launched using block clusters, in accordance with at least one embodiment. In at least one embodiment, a processor102executes or otherwise performs one or more commands to generate a software kernel104and to launch a software kernel106. In at least one embodiment, processor102is a single-core processor, a multi-core processor, a graphics processors, a parallel processor, a general purpose graphics processor, and/or some other processor such as those described herein in connection withFIGS.36to67.

In at least one embodiment, software kernel comprises a set of one or more executable functions, as described herein. In at least one embodiment, a software kernel is generated (e.g., when processor102executes or otherwise performs one or more commands to generate a software kernel104) from one or more functions as described herein at least in connection withFIGS.63A,63C, and64. In at least one embodiment, a software kernel is launched (e.g., when processor102executes or otherwise performs one or more commands to launch a software kernel106using systems and methods such as those described herein at least in connection withFIGS.63A,63C, and64. In at least one embodiment, a software kernel is referred to as a kernel when, for example, a kernel is being generated and launched on graphics processor hardware such as that described herein. In at least one embodiment, not shown inFIG.1, one or more additional processors may be elements of example computer system100.

In at least one embodiment, processor102executes or otherwise performs one or more commands to launch software kernel106by causing a software kernel to be executed using a graphics processor108. In at least one embodiment, graphics processor108is a single-core graphics processor, a multi-core graphics processor, a parallel processor, a general purpose graphics processor, and/or some other graphics processor such as those described herein in connection withFIGS.45A to54. In at least one embodiment, not shown inFIG.1, one or more additional graphics processors may be elements of example computer system100.

In at least one embodiment, graphics processor108includes one or more compute units (e.g., compute unit110and/or compute unit122). In at least one embodiment, compute unit110(and/or compute unit122) is a compute unit such as those described herein at least in connection withFIG.66. In at least one embodiment, compute unit110(and/or compute unit122) is a programmable streaming multiprocessor (“SM”)5314as described herein at least in connection withFIG.53. In at least one embodiment, compute unit110(and/or compute unit122) is a streaming multiprocessor (“SM”)5400as described herein at least in connection withFIG.54.

In at least one embodiment, compute unit110implements one or more block clusters such as those described herein (e.g., block cluster112, block cluster120, and/or block cluster118) using systems and methods such as those described herein. In at least one embodiment, processor102executes or otherwise performs one or more commands to launch software kernel106by causing a software kernel to be executed using block cluster112of compute unit110on graphics processor108. In at least one embodiment, compute unit110may include one or more additional block clusters such as block cluster120that may be used to launch one or more other software kernels by a processor such as processor102and/or by another processor not shown inFIG.1. In at least one embodiment, block cluster120may be used to launch one or more other software kernels before, during, or after processor102executes or otherwise performs one or more commands to launch software kernel106using block cluster112. In at least one embodiment, not shown inFIG.1, block cluster120may be on a different compute unit (e.g., compute unit122) than block cluster112. In at least one embodiment, not shown inFIG.1, block clusters such as block cluster112, block cluster118, and/or block cluster120include one or more thread blocks such as thread block202, as described herein at least in connection withFIG.2.

In at least one embodiment, processor102may also execute or otherwise perform one or more commands to generate another software kernel114and to launch another software kernel116. In at least one embodiment, software kernel114is identical to software kernel104. In at least one embodiment, software kernel114is different from software kernel104. In at least one embodiment, processor102executes or otherwise performs one or more commands to launch software kernel116by causing a software kernel to be executed using block cluster118of compute unit110on graphics processor108. In at least one embodiment, block cluster118may be used to launch software kernel116before, during, or after processor102executes or otherwise performs one or more commands to launch software kernel106using block cluster112. In at least one embodiment, not shown inFIG.1, block cluster118may be on a different compute unit (e.g., compute unit122) than block cluster112.

In at least one embodiment, not shown inFIG.1, processor102executes or otherwise performs one or more commands to launch software kernel106by causing a software kernel to be executed using a plurality of block clusters such as block cluster112, on a plurality of compute units using a graphics processor108. In at least one embodiment, for example, processor102executes or otherwise performs one or more commands to launch software kernel106by launching a portion of a software kernel on a block cluster112on compute unit110and by launching a second portion of a software kernel on a block cluster (not illustrated inFIG.1) on compute unit122.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate one or more dimensions of one or more clusters of one or more groups of instructions. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate two or more blocks of threads to be scheduled in parallel using an API such as set block cluster dimension API802, described herein at least in connection withFIG.8. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate one or more dimensions of one or more clusters of one or more groups of instructions using an API such as set block cluster dimension API802, described herein at least in connection withFIG.8.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to obtain one or more dimensions of a one or more clusters of one or more groups of instructions. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to determine which of two or more blocks of threads to be scheduled in parallel using an API such as get cluster dimension API902, described herein at least in connection withFIG.9. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to obtain one or more dimensions of a one or more clusters of one or more groups of instructions using an API such as get cluster dimension API902, described herein at least in connection withFIG.9.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate a scheduling policy of one or more clusters of one or more groups of instructions. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed using an API such as set scheduling policy API1202, described herein at least in connection withFIG.12. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate a scheduling policy of one or more clusters of one or more groups of instructions using an API such set scheduling policy API1202, described herein at least in connection withFIG.12.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to obtain a scheduling policy of one or more clusters of one or more groups of instructions. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads using an API such as get scheduling policy API1302, described herein at least in connection withFIG.13. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to obtain a scheduling policy of one or more clusters of one or more groups of instructions using an API such as get scheduling policy API1302, described herein at least in connection withFIG.13.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to obtain a limit of a number of allowable clusters of one or more groups of instructions. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate a maximum number of blocks of threads capable of being scheduled in parallel using an API such as number of blocks supported API1502, described herein at least in connection withFIG.15. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to obtain a limit of a number of allowable clusters of one or more groups of instructions using an API such as number of blocks supported API1502, described herein at least in connection withFIG.15.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to obtain one or more attributes of one or more clusters of one or more groups of instructions. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads using an API such as indicate cluster parameters API1702, described herein at least in connection withFIG.17. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to obtain one or more attributes of one or more clusters of one or more groups of instructions using an API such as indicate cluster parameters API1702, described herein at least in connection withFIG.17.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to obtain a limit of a number of concurrently performable clusters of one or more groups of instructions. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate a maximum number of blocks of threads to be scheduled in parallel using an API such as maximum cluster size supported API1902, described herein at least in connection withFIG.19. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to obtain a limit of a number of concurrently performable clusters of one or more groups of instructions using an API such as maximum cluster size supported API1902, described herein at least in connection withFIG.19.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause a software kernel to be performed using one or more clusters of one or more groups of instructions. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel using an API such as launch kernel with block clusters API2102, described herein at least in connection withFIG.21. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause a software kernel to be performed using one or more clusters of one or more groups of instructions using an API such as launch kernel with block clusters API2102, described herein at least in connection withFIG.21.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to obtain one or more parameters of one or more clusters of one or more groups of instructions of a set of one or more clusters of one or more groups of instructions. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads using an API such as get attributes API2602, described herein at least in connection withFIG.26. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to obtain one or more parameters of one or more clusters of one or more groups of instructions of a set of one or more clusters of one or more groups of instructions using an API such as get attributes API2602, described herein at least in connection withFIG.26.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API indicate arrival at a barrier instruction of a cluster of one or more groups of instructions. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction using an API such as kernel barrier arrive API3002, described herein at least in connection withFIG.30. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate arrival at a barrier instruction of a cluster of one or more groups of instructions using an API such as kernel barrier arrive API3002, described herein at least in connection withFIG.30.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause one or more first instructions to be prevented from being performed until a cluster of one or more groups of instructions have performed one or more second instructions. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction using an API such as kernel barrier wait API3102, described herein at least in connection withFIG.31. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause one or more first instructions to be prevented from being performed until a cluster of one or more groups of instructions have performed one or more second instructions using an API such as kernel barrier wait API3102, described herein at least in connection withFIG.31.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction using an API such as a kernel barrier sync API3202, described herein at least in connection withFIG.32. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause one or more first instructions to be prevented from being performed until a cluster of one or more groups of instructions have performed one or more second instructions using an API such as a kernel barrier sync API3202, described herein at least in connection withFIG.32.

In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause memory to be shared between two or more groups of blocks of thread. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause one or more memory locations of first cluster of one or more groups of instructions to be accessible to a second cluster of one or more groups of instructions. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause memory to be shared between two or more groups of blocks of thread using an API such as map shared memory API3402, described herein at least in connection withFIG.34. In at least one embodiment, processor102and/or graphics processor108comprise one or more circuits to perform an API to cause one or more memory locations of first cluster of one or more groups of instructions to be accessible to a second cluster of one or more groups of instructions using an API such as map shared memory API3402, described herein at least in connection withFIG.34.

FIG.2illustrates an example diagram200of a thread block202where execution threads are organized, in accordance with at least one embodiment. In at least one embodiment, thread block202includes one or more threads. In at least one embodiment, thread block202is a three-dimensional (3D) thread block that has dimensions (Tx, Ty, Tz) (e.g., there are Tx×Ty×Tzthreads). In at least one embodiment, for example, if Txis 8, Tyis 8, and Tzis 4, thread block202includes 256 threads. In at least one embodiment, thread block202may be one-dimensional (e.g., may have Txthreads), or may be two-dimensional (e.g., may have Tx×Tythreads), may be four-dimensional (e.g., may have Tx×Ty×Tz×Twthreads), or may have some other dimensionality. In at least one embodiment, thread block202is a thread block such as thread blocks6630(1,1)-6630(BX,BY), described herein at least in connection withFIG.66.

In at least one embodiment, thread block202includes a plurality of threads in a grid (e.g., a Tx×Ty×Tzgrid) which are threads such as threads6640(1,1)-6640(TX,TY) as described herein at least in connection withFIG.66. In at least one embodiment, threads of thread block202may be used to execute a software kernel such those described. In at least one embodiment, for example, threads of thread block202may be used to execute a software kernel when processor102launches kernel106using block cluster112, as described herein at least in connection withFIG.1.

FIG.3illustrates an example diagram300of a compute unit302where thread blocks are processed, in accordance with at least one embodiment. In at least one embodiment, compute unit302is a compute unit such as compute unit110and/or compute unit122, as described herein at least in connection withFIG.1. In at least one embodiment, compute unit302has one or more thread blocks such as thread block202, as described herein at least in connection withFIG.2. In at least one embodiment, compute unit302includes shared memory304, which is shared memory such as shared memory6660(1) and/or shared memory6660(2), as described herein at least in connection withFIG.66. In at least one embodiment, shared memory304comprises one or more memory locations accessible by one or more threads, one or more thread blocks, and/or one or more block clusters. In at least one embodiment, shared memory304includes one or more physical memory locations. In at least one embodiment, shared memory304includes one or more virtual memory locations. In at least one embodiment, shared memory304is memory hosted by a processor and/or a graphics processing unit (GPU) such as those described herein.

In at least one embodiment, not shown inFIG.3, blocks (e.g., thread blocks) are executed using an entire graphics processor such as graphics processor108, described herein at least in connection withFIG.1, with one or more blocks (e.g., thread blocks) executing on each of a plurality of compute units such as compute unit302. In at least one embodiment, blocks of a grid of blocks as illustrated inFIG.3are organized as a logical grid so that, for example, block (1,1,1) may be hosted on a first compute unit and a logically neighboring block (e.g., block (1,1,2), block (1,2,1), block (2,1,1), etc.) may be on a different compute unit.

In at least one embodiment, compute unit302has a three-dimensional (3D) grid of thread block that has dimensions (Bx, By, Bz) (e.g., there are Bx×By×Bzthread blocks). In at least one embodiment, for example, if Bxis 4, Byis 4, and Bzis 4, compute unit302includes 64 thread blocks. In at least one embodiment, where, for example, a thread block has 256 threads, compute unit302may have 16,384 threads. In at least one embodiment, compute unit302may be one-dimensional (e.g., may have Bxthread blocks), or may be two-dimensional (e.g., may have Bx×Bythread blocks), may be four-dimensional (e.g., may have Bx×By×Bz×Bwthread blocks), or may have some other dimensionality. In at least one embodiment, thread blocks of compute unit302are used to execute a software kernel such those described. In at least one embodiment, for example, thread blocks of compute unit302are used to execute a software kernel when processor102launches kernel106using block cluster112, as described herein at least in connection withFIG.1.

FIG.4illustrates an example diagram400of a compute unit402where threads of a thread block are processed, in accordance with at least one embodiment. In example computer system400illustrated inFIG.4, thread blocks406are illustrated in two dimensions for clarity (e.g., a Bzdimension of a compute unit402is 1). In at least one embodiment, compute unit402is a compute unit such as those described herein. In at least one embodiment, compute unit402is referred to as a grid. In at least one embodiment, compute unit402includes shared memory404and one or more thread blocks406. In at least one embodiment, thread blocks406are contained in one or more block clusters, as described herein. In at least one embodiment, thread blocks406of compute unit402are used to execute a software kernel such those described. In at least one embodiment, for example, thread blocks406of compute unit402are used to execute a software kernel when processor102launches kernel106using block cluster112, as described herein at least in connection withFIG.1.

In at least one embodiment, not shown inFIG.4, thread blocks are executed using an some or all of a graphics processor such as graphics processor108, described herein at least in connection withFIG.1, with one or more thread blocks executing on each of a plurality of compute units such as compute unit402, as described herein. In at least one embodiment, dimensions of thread blocks of a grid of blocks on a compute unit, as illustrated inFIG.4, are organized logically as described herein and have different dimensions so that, for example, a first compute unit may have a grid size of (3,4,1), a second compute unit may have a grid size of (2,2,2), etc.

FIG.5illustrates an example diagram500of a compute unit502where block clusters are processed, in accordance with at least one embodiment. In example computer system500illustrated inFIG.5, thread blocks of block clusters506are illustrated in two dimensions for clarity (e.g., a Bzdimension of a compute unit502is 1). In at least one embodiment, compute unit502is a compute unit such as those described herein. In at least one embodiment, compute unit502includes shared memory504and one or more thread blocks in one or more block clusters506.

In at least one embodiment, block clusters506includes twelve thread blocks (e.g., a 3×4×1 grid of thread blocks) that are distributed among six block clusters (e.g., a 2D 2×3 grid of block clusters). In at least one embodiment, a block cluster508includes four thread blocks. In at least one embodiment, thread block (1,1) of block cluster508is thread block (1,1,1) of thread blocks406, thread block (1,2) of block cluster508is thread block (1,2,1) of thread blocks406, thread block (2,1) of block cluster508is thread block (2,1,1) of thread blocks406, and thread block (2,2) of block cluster508is thread block (2,2,1) of thread blocks406, described herein at least in connection withFIG.4. In at least one embodiment, block cluster508has identifier (1,1) and has dimensions of (2,2).

In at least one embodiment, a block cluster510includes two thread blocks. In at least one embodiment, thread block (1,1) of block cluster510is thread block (1,3,1) of thread blocks406and thread block (2,1) of block cluster510is thread block (2,3,1) of thread blocks406, described herein at least in connection withFIG.4. In at least one embodiment, block cluster510has identifier (1,2) and has dimensions of (2,1).

In at least one embodiment, a block cluster512includes two thread blocks. In at least one embodiment, thread block (1,1) of block cluster512is thread block (1,4,1) of thread blocks406and thread block (2,1) of block cluster512is thread block (2,4,1) of thread blocks406, described herein at least in connection withFIG.4. In at least one embodiment, block cluster512has identifier (1,3) and has dimensions of (2,1).

In at least one embodiment, a block cluster514includes two thread blocks. In at least one embodiment, thread block (1,1) of block cluster514is thread block (3,1,1) of thread blocks406and thread block (1,2) of block cluster512is thread block 3,2,1) of thread blocks406, described herein at least in connection withFIG.4. In at least one embodiment, block cluster514has identifier (2,1) and has dimensions of (1,2).

In at least one embodiment, a block cluster516includes one thread block. In at least one embodiment, thread block (1,1) of block cluster516is thread block (3,3,1) of thread blocks406, described herein at least in connection withFIG.4. In at least one embodiment, block cluster516has identifier (2,2) and has dimensions of (1,1). In at least one embodiment, a block cluster518includes one thread block. In at least one embodiment, thread block (1,1) of block cluster518is thread block (3,4,1) of thread blocks406, described herein at least in connection withFIG.4. In at least one embodiment, block cluster518has identifier (2,3) and has dimensions of (1,1).

In at least one embodiment, thread blocks of block clusters506of compute unit502are used to execute a software kernel such those described. In at least one embodiment, for example, thread blocks of block clusters506of compute unit402are used to execute a software kernel when processor102launches kernel106using block cluster112, as described herein at least in connection withFIG.1. In at least one embodiment, threads, thread blocks, block clusters, and compute units (also referred to herein as grids) are organized and/or indexed as illustrated inFIG.5. In at least one embodiment, threads, thread blocks, block clusters, and compute units (also referred to herein as grids) are organized and/or indexed using some other method including, but not limited to, one or more dynamic methods that may be used to determine dimensions, indices, and/or identifiers of threads, thread blocks, block clusters, and/or compute units based, at least in part, on GPU architecture, number of compute units of a GPU, number of cores of a GPU, etc. In at least one embodiment, dimensions, indices, and/or identifiers of threads, thread blocks, block clusters, and/or compute units are referred to as properties of a group of blocks of threads.

In at least one embodiment, block clusters such as those illustrated inFIG.5execute on different compute units (not illustrated inFIG.5) so that, for example, block cluster508executes on a first compute unit, block cluster510executes on a second compute unit, block cluster512executes on a third compute unit, etc. In at least one embodiment, one or more block clusters execute on a single compute unit and a plurality of block clusters execute on a plurality of compute units. In at least one embodiment, as described herein, thread blocks if a block cluster (e.g., block cluster508) are organized logically so that, for example, thread block (1,1) executes on a first compute unit, thread block (1,2) executes on a second compute unit, etc.

In at least one embodiment, a block cluster is a group of thread blocks within a higher level of a hierarchy that organizes threads, where a group of thread blocks can be an organizational construct that comprises one or more thread blocks. In at least one embodiment, a block cluster (which may also be referred to in other ways, such as a cluster) is a subset of a grid of thread blocks. In at least one embodiment, a block cluster is a partition of a partitioning of a set of thread blocks, such as a partitioning of a grid of thread blocks or a partitioning of a set of thread blocks that comprise a software kernel. In at least one embodiment, a block cluster is a subset of a set of thread blocks (e.g., of a grid or of a software kernel), where a set is organized into subsets of thread blocks and where subsets can overlap (e.g., have one or more thread blocks that are common to a plurality of subsets) or where subsets are disjoint (e.g., have no thread block that is a member of multiple subsets). In at least one embodiment, application programming interfaces (APIs), such as described below and elsewhere herein, which may be CUDA APIs, OneAPI APIs, HIP APIs and/or other APIs such as described herein, are callable to obtain information about and otherwise manage block clusters and other hierarchical groupings of threads, such as grids, thread blocks, warps, and other groupings of threads. In at least one embodiment, one or more APIs such as those described herein are used to manage one or more portions of a block cluster, using systems and methods such as those described herein. In at least one embodiment, as used herein, an application programming interface is referred to as an API.

FIG.6illustrates an example process600to launch software kernels using block clusters, in accordance with at least one embodiment. In at least one embodiment, a processor such as processor102(e.g., a CPU), described herein at least in connection withFIG.1, executes or otherwise performs one or more commands to perform example process600. In at least one embodiment, a graphics processor such as graphics processor108, described herein at least in connection withFIG.1, executes or otherwise performs one or more commands to perform example process600. In at least one embodiment, a processor such as one or more of those described herein, executes or otherwise performs one or more commands to perform example process600.

In at least one embodiment, at step602of example process600, a processor performing example process600receives a kernel specification. In at least one embodiment, a kernel specification received at step602is an argument of an API such as those described herein. In at least one embodiment, at step602, a kernel specification received at step602may be used to generate and/or launch a software kernel, as described herein. In at least one embodiment, at step602, a kernel specification received at step602may be used to generate and/or launch a software kernel using one or more block clusters, as described herein. In at least one embodiment, after step602, example process600advances to step604.

In at least one embodiment, at step604of example process600, a processor performing example process600receives cluster parameters. In at least one embodiment, a cluster parameters received at step604are arguments of an API such as those described herein. In at least one embodiment, at step604, cluster parameters received are cluster parameters that describe one or more aspects of a block cluster including, but not limited to, size of one or more block clusters, shape of one or more block clusters, scheduling policies, execution priorities, memory management techniques, synchronization methods, and/or other cluster parameters such as those described herein. In at least one embodiment, at step604, cluster parameters are received using one or more application programming interfaces (APIs) such as those described herein. In at least one embodiment, after step604, example process600advances to step606.

In at least one embodiment, at step606of example process600, a processor performing example process600sets one or more known cluster parameters. In at least one embodiment, at step606, a processor performing example process600sets one or more known cluster parameters as a result of execution of an API such as those described herein. In at least one embodiment, at step606, a processor performing example process600sets one or more known cluster parameters by altering one or more values in a data structure used to store cluster parameters of block clusters. In at least one embodiment, at step606a processor performing example process600sets one or more known cluster parameters by calculating parameters, reading parameters from memory, deriving parameters, and/or storing parameters, as described herein. In at least one embodiment, at step606, a processor performing example process600sets one or more default values of cluster parameters where cluster parameters received at step604do not include parameters and/or where default values are specified to indicate missing parameters. In at least one embodiment, at step606, for example, a block cluster may have a default size that may be used in an embodiment where one or more known cluster parameters received at step606does not include a size parameter. In at least one embodiment, after step606, example process600advances to step608.

In at least one embodiment, at step608of example process600, a processor performing example process600determines whether other parameters are needed to complete a specification of a block cluster. In at least one embodiment, at step608, some parameters received at step606may not be specified and, accordingly, other parameters may be needed to complete a specification of a block cluster. In at least one embodiment, at step608, if a processor performing example process600determines that other parameters are needed to complete a specification of a block cluster (“YES” branch) example process600advances to step610. In at least one embodiment, at step608, if a processor performing example process600determines that other parameters are not needed to complete a specification of a block cluster (“NO” branch) example process600advances to step612.

In at least one embodiment, at step610of example process600, a processor performing example process600sets one or more other cluster parameters are set (e.g., parameters not set at step606), using systems and methods such as those described herein. In at least one embodiment, at step610, a processor performing example process600sets one or more other cluster parameters using default parameters, as described herein. In at least one embodiment, at step610, a processor performing example process600derives one or more other cluster parameters from existing parameters. In at least one embodiment, for example, if dimension parameters are received at step604(e.g., a dimension of X, Y, Z, as described herein), at step610, a size parameter (e.g., X times Y time Z) is derived from dimensions. In at least one embodiment, after step610, example process600advances to step612.

In at least one embodiment, at step612of example process600, a processor performing example process600sets one or more cluster attributes, using systems and methods such as those described herein. In at least one embodiment, at step612, a processor performing example process600sets one or more cluster attributes using one or more APIs, such as described herein. In at least one embodiment, at step612, a processor performing example process600sets one or more cluster attributes using one or more compile-time APIs, as described herein. In at least one embodiment, at step612, a processor performing example process600sets one or more cluster attributes using one or more launch-time APIs, as described herein. In at least one embodiment, at step612, a processor performing example process600sets one or more cluster attributes using one or more run-time APIs, as described herein. In at least one embodiment, after step612, example process600advances to step614.

In at least one embodiment, at step614of example process600, a processor performing example process600determines whether one or more cluster attributes have been set. In at least one embodiment, at step614, if it is determined that one or more cluster attributes have not been set (“NO” branch) example process600advances to step616. In at least one embodiment, at step614, if it is determined that one or more cluster attributes have been set (“YES” branch) example process600advances to step618.

In at least one embodiment, at step616of example process600, a processor performing example process600returns an error. In at least one embodiment, a processor performing example process600returns an error as a result of determining that one or more cluster attributes have not been set (e.g., at step614). In at least one embodiment, at step616, a processor performing example process600returns an error to a calling process such as those described herein. In at least one embodiment, after step616, example process600terminates. In at least one embodiment, not shown inFIG.6, after step616, example process600continues at step602to receive another kernel specification.

In at least one embodiment, at step618of example process600, a processor performing example process600launches a kernel using one or more block clusters using systems and methods such as those described herein. In at least one embodiment, a processor performing example process600causes some other processor such as those described herein to launch a kernel using one or more block clusters. In at least one embodiment, after step618, example process600advances to step620.

In at least one embodiment, at step620of example process600, a processor performing example process600returns an indicator of success. In at least one embodiment, a processor performing example process600returns an indicator of success as a result of determining that one or more cluster attributes have been set (e.g., at step614) and after launching a kernel using a cluster (e.g., at step618). In at least one embodiment, at step620, an indicator of success is returned to a calling process such as those described herein. In at least one embodiment, after step620, example process600terminates. In at least one embodiment, not shown inFIG.6, after step620, example process600continues at step602to receive another kernel specification.

In at least one embodiment, operations of example process600are performed in a different order than is illustrated inFIG.6. In at least one embodiment, operations of example process600are performed simultaneously or in parallel. In at least one embodiment, for example, operations that do not depend on each other (e.g., are order independent) are performed simultaneously or in parallel. In at least one embodiment, operations of example process600are performed by a plurality of threads executing on a processor such as those described herein.

FIG.7illustrates an example diagram700where sizes and dimensions of block clusters are shown, in accordance with at least one embodiment. In at least one embodiment, an operation to set block cluster size702is performed as described herein (e.g., using set block cluster dimension API802, described herein at least in connection withFIG.8). In at least one embodiment, set block cluster size702specifies a block cluster size (e.g., 8). In at least one embodiment, set block cluster size702specifies one or more block cluster dimensions (e.g., (2,2,2) or (2,4,1), or (4,2,1), or (8,1,1)), or some other such dimensions. In at least one embodiment, set block cluster size702specifies size but not dimension. In at least one embodiment, set block cluster size702specifies dimension but not size. In at least one embodiment, dimensions are computed from size. In at least one embodiment, size is computed from dimensions.

In at least one embodiment, a block cluster704with eight blocks that has dimensions (2,2,2) is created. In at least one embodiment, a block cluster706with eight blocks that has dimensions (2,4,1) is created. In at least one embodiment, a block cluster708with eight blocks that has dimensions (8,1,1) is created. In at least one embodiment, a block cluster that has two dimensions is created (e.g., (2,4) or (8,1)). In at least one embodiment, a block cluster that has one dimension is created (e.g., (8)). In at least one embodiment, a block cluster that has four (or more) dimensions is created (e.g., (2,1,2,2), (2,1,2,1,2), etc.).

FIG.8illustrates an example application programming interface800to indicate dimensions of a block cluster, in accordance with at least one embodiment. In at least one embodiment, example application programming interface800for indicating dimensions of a block cluster is a set block cluster dimension API802. In at least one embodiment, an API such as set block cluster dimension API802is performed by a processor, such as those described herein. In at least one embodiment, an API such as set block cluster dimension API802is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as set block cluster dimension API802is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as set block cluster dimension API802is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as set block cluster dimension API802, when performed, is to indicate two or more blocks of threads to be scheduled in parallel.

In at least one embodiment, set block cluster dimension API802is an API to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, set block cluster dimension API802is an API to indicate one or more dimensions of one or more clusters of one or more groups of instructions. In at least one embodiment, set block cluster dimension API802is an API to set sizes and/or dimensions of block clusters as described herein at least in connection withFIG.7. In at least one embodiment, set block cluster dimension API802receives one or more parameters including, but not limited to, a dimension attribute804, a dimension value806, and a kernel identifier808. In at least one embodiment, set block cluster dimension API802returns a return value818.

In at least one embodiment, dimension attribute804of set block cluster dimension API802is an attribute that indicates that set block cluster dimension API802is setting a dimension value806. In at least one embodiment, for example, dimension attribute804may be a three-dimensional attribute and dimension value806may be three values (e.g., one value corresponding to each of three dimensions). In at least one embodiment, kernel identifier808is an identifier of a kernel that will be launched using a block cluster of dimensions specified in set block cluster dimension API802using systems and methods such as those described herein.

In at least one embodiment, not shown inFIG.8, set block cluster dimension API802receives one or more additional parameters and/or of flags that specify how dimension attribute804, dimension value806, and/or kernel identifier808will be used to indicate dimensions of a block cluster. In at least one embodiment, when additional parameters and/or of flags that specify how dimension attribute804, dimension value806, and/or kernel identifier808will be used to indicate dimensions of a block cluster are not received, one or more default parameters and/or flags may be used by set block cluster dimension API802to obtain dimensions of a block cluster, using systems and methods such as those described herein.

In at least one embodiment, set block cluster dimension API802causes a processor such as those described herein to execute one or more commands to verify block cluster dimension attributes and attribute values810and set block cluster dimensions of a kernel812, as identified by kernel identifier808. In at least one embodiment, set block cluster dimension API802causes a processor such as those described herein to execute one or more commands to launch a kernel814using a block cluster as described herein. In at least one embodiment, not shown inFIG.8, one or more commands to launch a kernel814are executed at a different time and/or by a different API.

In at least one embodiment, set block cluster dimension API802returns success or failure816using return value818. In at least one embodiment, set block cluster dimension API802returns success using return value818when set block cluster dimension API802sets block cluster dimension attributes of a kernel, as described herein. In at least one embodiment, set block cluster dimension API802returns failure using return value818when set block cluster dimension API802does not set block cluster dimension attributes of a kernel, as described herein.

In at least one embodiment, set block cluster dimension API802returns success or failure816using return value818to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, set block cluster dimension API802returns success or failure816using return value818to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.9illustrates an example application programming interface900to obtain dimensions of a block cluster, in accordance with at least one embodiment. In at least one embodiment, example application programming interface900to obtain dimensions of a block cluster is a get cluster dimension API902. In at least one embodiment, an API such as get cluster dimension API902is performed by a processor, such as those described herein. In at least one embodiment, an API such as get cluster dimension API902is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as get cluster dimension API902is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as get cluster dimension API902is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as get cluster dimension API902, when performed, is to determine which of two or more blocks of threads to be scheduled in parallel.

In at least one embodiment, get cluster dimension API902is an API to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, get cluster dimension API902is an API to obtain one or more dimensions of a one or more clusters of one or more groups of instructions. In at least one embodiment, get cluster dimension API902is an API to is an API to get sizes and/or dimensions of block clusters as described herein at least in connection withFIG.7. In at least one embodiment, get cluster dimension API902receives one or more parameters including, but not limited to, a cluster identifier904. In at least one embodiment, get cluster dimension API902returns a return value912.

In at least one embodiment, cluster identifier904of get cluster dimension API902is an identifier used to identify a cluster using systems and methods such as those described herein. In at least one embodiment, for example, cluster identifier904is an indexed value of a cluster that is based on a total number of clusters of a compute unit. In at least one embodiment, cluster identifier904is a location of a cluster within a group of clusters.

In at least one embodiment, not shown inFIG.9, get cluster dimension API902receives one or more additional parameters and/or of flags that specify how cluster identifier904will be used to obtain dimensions of a block cluster. In at least one embodiment, when additional parameters and/or of flags that specify how cluster identifier904will be used to obtain dimensions of a block cluster are not received, one or more default parameters and/or flags may be used by get cluster dimension API902to obtain dimensions of a block cluster, using systems and methods such as those described herein.

In at least one embodiment, get cluster dimension API902causes a processor such as those described herein to execute one or more commands to determine906whether dimensions of a cluster are set, as described herein. In at least one embodiment, if it is determined that dimensions are not set (“NO” branch), a default return value908may be returned (e.g., (0,0,0)). In at least one embodiment, if it is determined that dimensions are set (“YES” branch), dimensions of a cluster are returned910. In at least one embodiment, get cluster dimension API902returns dimensions or default values using return value912.

In at least one embodiment, get cluster dimension API902returns dimensions or default values using return value912to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, get cluster dimension API902returns dimensions or default values using return value912to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.10illustrates an example diagram1000where a spread scheduling policy of block clusters is shown, in accordance with at least one embodiment. In at least one embodiment, a block cluster1002with a spread scheduling policy1004causes thread blocks to be distributed to multiple compute units, for example, as many compute units as possible. In at least one embodiment, spread scheduling policy1004is set using set scheduling policy API1202, described herein at least in connection withFIG.12. In at least one embodiment, for example, block cluster1002with spread scheduling policy1004distributes four thread blocks to four compute units (e.g., thread block1006to compute unit1014, thread block1008to compute unit1016, thread block1010to compute unit1018, and thread block1012to compute unit1020). In at least one embodiment, a scheduling policy such as spread scheduling policy1004is a preferred scheduling policy so that, for example, when thread blocks are distributed to compute units, a scheduling policy may be satisfied or may be violated (e.g., multiple thread blocks may be distributed to a single compute unit). In at least one embodiment, a scheduling policy such as spread scheduling policy1004is a default scheduling policy.

FIG.11illustrates an example diagram1100where a balance scheduling policy of block clusters is shown, in accordance with at least one embodiment. In at least one embodiment, a block cluster1102with a balance scheduling policy1104causes thread blocks to be balanced among available compute units so that work loading is evenly distributed between compute units. In at least one embodiment, balance scheduling policy1104is set using set scheduling policy API1202, described herein at least in connection withFIG.12. In at least one embodiment, for example, thread block1106is distributed to compute unit1114, where compute unit1114has thread block1122(e.g., from a different block cluster, not shown inFIG.11), thread block1108and thread block1110are distributed to compute unit1116, which has no other thread blocks, thread block1112is distributed to compute unit1120, which has no other thread blocks, and no thread blocks from block cluster1102are distributed to compute unit1118, because compute unit1118already has thread block1124and thread block1126(e.g., from a different block cluster not shown inFIG.11). In at least one embodiment, a scheduling policy such as balance scheduling policy1104is a preferred scheduling policy so that, for example, when thread blocks are distributed to compute units, a scheduling policy may be satisfied or may be violated (e.g., thread blocks may be distributed to compute unit in an unbalanced manner). In at least one embodiment, a scheduling policy such as balance scheduling policy1104is a default scheduling policy.

FIG.12illustrates an example application programming interface1200to indicate a scheduling policy of a block cluster, in accordance with at least one embodiment. In at least one embodiment, example application programming interface1200to indicate a scheduling policy of a block cluster is a set scheduling policy API1202. In at least one embodiment, an API such as set scheduling policy API1202is performed by a processor, such as those described herein. In at least one embodiment, an API such as set scheduling policy API1202is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as set scheduling policy API1202is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as set scheduling policy API1202is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as set scheduling policy API1202, when performed, is to cause a scheduling policy of one or more blocks of one or more threads to be performed.

In at least one embodiment, set scheduling policy API1202is an API comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, set scheduling policy API1202is an API to indicate a scheduling policy of one or more clusters of one or more groups of instructions. In at least one embodiment, set scheduling policy API1202is an API to set a scheduling policy such as spread scheduling policy1004, described herein at least in connection withFIG.10. In at least one embodiment, set scheduling policy API1202is an API to set a scheduling policy such as balance scheduling policy1104, described herein at least in connection withFIG.11. In at least one embodiment, set scheduling policy API1202receives one or more parameters including, but not limited to, a scheduling policy attribute1204, a scheduling policy value1206, and/or a kernel identifier1208. In at least one embodiment, set scheduling policy API1202returns a return value1218.

In at least one embodiment, scheduling policy attribute1204of set scheduling policy API1202is an attribute that indicates that set scheduling policy API1202is setting a scheduling policy value1206of a block cluster. In at least one embodiment, scheduling policy value1206is a spread scheduling policy, as described herein. In at least one embodiment, scheduling policy value1206is a balance scheduling policy, as described herein. In at least one embodiment, scheduling policy value1206is a default scheduling policy, as described herein. In at least one embodiment, kernel identifier1208is an identifier of a kernel that will be launched using a block cluster with a scheduling policy specified using set scheduling policy1202, using systems and methods such as those described herein.

In at least one embodiment, not shown inFIG.12, set scheduling policy API1202receives one or more additional parameters and/or of flags that specify how scheduling policy attribute1204, scheduling policy value1206, and/or kernel identifier1208will be used to indicate a scheduling policy of a block cluster. In at least one embodiment, when additional parameters and/or of flags that specify how scheduling policy attribute1204, scheduling policy value1206, and/or kernel identifier1208will be used to indicate a scheduling policy of a block cluster are not received, a default set of parameters and/or flags may be used by set scheduling policy API1202to indicate a scheduling policy of a block cluster, using systems and methods such as those described herein.

In at least one embodiment, set scheduling policy API1202causes a processor such as those described herein to execute one or more commands to verify block cluster scheduling policy attributes and attribute values1210and set block cluster scheduling policies of a kernel1212, as identified by kernel identifier1208. In at least one embodiment, set scheduling policy API1202causes a processor such as those described herein to execute one or more commands to launch a kernel1214using a block cluster as described herein. In at least one embodiment, not shown inFIG.12, one or more commands to launch a kernel1214are executed at a different time and/or by a different API.

In at least one embodiment, set scheduling policy API1202returns success of failure1216using return value1218. In at least one embodiment, set scheduling policy API1202returns success using return value1218when set scheduling policy API1202sets a block cluster scheduling policy successfully, as described herein. In at least one embodiment, set scheduling policy API1202returns failure using return value1218when set scheduling policy API1202does not set a block cluster scheduling policy successfully, as described herein.

In at least one embodiment, set scheduling policy API1202returns success or failure1216using return value1218to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, set scheduling policy API1202returns success or failure1216using return value1218to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.13illustrates an example application programming interface1300to obtain a scheduling policy of a block cluster, in accordance with at least one embodiment In at least one embodiment, example application programming interface1300to obtain a scheduling policy of a block cluster is a get scheduling policy API1302. In at least one embodiment, an API such as get scheduling policy API1302is performed by a processor, such as those described herein. In at least one embodiment, an API such as get scheduling policy API1302is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as get scheduling policy API1302is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as get scheduling policy API1302is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as get scheduling policy API1302, when performed, is to indicate a scheduling policy of one or more blocks of one or more threads.

In at least one embodiment, get scheduling policy API1302is an API comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, get scheduling policy API1302is an API to obtain a scheduling policy of one or more clusters of one or more groups of instructions. In at least one embodiment, get scheduling policy API1302is an API to is an API to get a scheduling policy such as spread scheduling policy1004, described herein at least in connection withFIG.10. In at least one embodiment, get scheduling policy API1302is an API to is an API to get a scheduling policy such as balance scheduling policy1104, described herein at least in connection withFIG.11. In at least one embodiment, get scheduling policy API1302receives one or more parameters including, but not limited to, a cluster identifier1304. In at least one embodiment, get scheduling policy API1302returns a return value1312.

In at least one embodiment, cluster identifier1304of get scheduling policy API1302is an identifier used to identify a cluster using systems and methods such as those described herein. In at least one embodiment, for example, cluster identifier1304is an indexed value of a cluster that is based on a total number of clusters of a compute unit. In at least one embodiment, cluster identifier1304is a location of a cluster within a group of clusters.

In at least one embodiment, not shown inFIG.13, get scheduling policy API1302receives one or more additional parameters and/or of flags that specify how cluster identifier1304will be used to obtain a scheduling policy of a block cluster. In at least one embodiment, when additional parameters and/or of flags that specify how cluster identifier1304will be used to obtain a scheduling policy of a block cluster are not received, one or more default parameters and/or flags may be used by get scheduling policy API1302to obtain a scheduling policy of a block cluster, using systems and methods such as those described herein.

In at least one embodiment, get scheduling policy API1302causes a processor such as those described herein to execute one or more commands to determine1306whether a scheduling policy of a cluster is set. In at least one embodiment, if it is determined that a scheduling policy is not set (“NO” branch), a default return value1308may be returned (e.g., a spread scheduling policy). In at least one embodiment, if it is determined that a scheduling policy is set (“YES” branch), a scheduling policy of cluster is returned. In at least one embodiment, get scheduling policy API1302returns a scheduling policy1310using return value1312.

In at least one embodiment, get scheduling policy API1302returns a scheduling policy1310using return value1312to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, get scheduling policy API1302returns a scheduling policy1310using return value1312to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.14illustrates an example computer system1400where a maximum number of clusters supported by hardware is obtained, in accordance with at least one embodiment. In at least one embodiment, a processor1402(which is a processor such as processor102, described herein at least in connection withFIG.1), executes or otherwise performs one or more commands to request a number of clusters supported1404that can be used to execute a kernel, as described herein. In at least one embodiment, processor1402executes or otherwise performs one or more commands to request a number of clusters supported1404that can be used to execute a kernel based, at least in part, on a configuration (not shown inFIG.14). In at least one embodiment, processor1402executes or otherwise performs one or more commands to request a number of clusters supported1404that can be used to execute a kernel based using number of blocks supported API1502, described herein at least in connection withFIG.15.

In at least one embodiment, a graphics processor1406(which is a graphics processor such as graphics processor108, described herein at least in connection withFIG.1), determines a maximum number of clusters1408that can be used to execute a kernel. In at least one embodiment, graphics processor1406determines a maximum number of clusters1408that can be used to execute a kernel based at least on kernel parameters, a kernel configuration, hardware capabilities of graphics processor1406, available resources, and/or other such factors. In at least one embodiment, graphics processor1406returns a determined maximum number of clusters1410to processor1402using methods such as those described herein.

In at least one embodiment, not illustrated inFIG.14, a processor such as processor1402determines information such as, for example, a maximum number of clusters supported by hardware, without executing or otherwise performing one or more commands to request a number of clusters supported1404that can be used to execute a kernel. In such an embodiment, processor1402may store information such as maximum number of clusters1408in memory associated with processor1402.

FIG.15illustrates an example application programming interface1500to obtain a maximum number of clusters supported by hardware, in accordance with at least one embodiment. In at least one embodiment, example application programming interface1500to obtain a maximum number of clusters supported by hardware is a number of blocks supported API1502. In at least one embodiment, an API such as number of blocks supported API1502is performed by a processor, such as those described herein. In at least one embodiment, an API such as number of blocks supported API1502is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as number of blocks supported API1502is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as number of blocks supported API1502is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as number of blocks supported API1502, when performed, is to indicate a maximum number of blocks of threads capable of being scheduled in parallel.

In at least one embodiment, number of blocks supported API1502is an API to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, number of blocks supported API1502is an API to obtain a limit of a number of allowable clusters of one or more groups of instructions. In at least one embodiment, number of blocks supported API1502is an API to request a maximum number of clusters supported1404, as described herein at least in connection withFIG.14. In at least one embodiment, number of blocks supported API1502receives one or more parameters including, but not limited to, a stored number of clusters1504, a kernel1506, and/or a launch configuration1508. In at least one embodiment, number of blocks supported API1502returns a return value1516.

In at least one embodiment, stored number of clusters1504is a location that is used by get of number of blocks supported API1502to return a number of clusters supported by hardware. In at least one embodiment, kernel1506is a kernel that will be executed by graphics hardware using systems and methods such as those described herein. In at least one embodiment, launch configuration1508includes one or more parameters such as those described herein that may be used to launch kernel1506using block clusters, as described herein.

In at least one embodiment, not shown inFIG.15, number of blocks supported API1502receives one or more additional parameters and/or of flags that specify how kernel1506and/or launch configuration1508will be used to obtain a maximum number of clusters supported by hardware. In at least one embodiment, when additional parameters and/or of flags that specify how kernel1506and/or launch configuration1508will be used to obtain a maximum number of clusters supported by hardware are not received, one or more default parameters and/or flags may be used by number of blocks supported API1502to obtain a maximum number of clusters supported by hardware, using systems and methods such as those described herein.

In at least one embodiment, number of blocks supported API1502causes a processor such as those described herein to execute one or more commands to determine number of clusters1510using systems and methods such as those described herein at least in connection withFIG.14and stores a determined value1512in stored number of clusters1504. In at least one embodiment, number of blocks supported API1502returns success or failure1514using return value1516. In at least one embodiment, number of blocks supported API1502returns success using return value1516when a number of clusters is determined. In at least one embodiment, number of blocks supported API1502returns failure using return value1516when a number of clusters is not determined or when a sufficient number of clusters is not available.

In at least one embodiment, number of blocks supported API1502returns success or failure1514using return value1516to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, number of blocks supported API1502returns success or failure1514using return value1516to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.16illustrates an example diagram1600where block cluster attributes are indicated and obtained, in accordance with at least one embodiment. In at least one embodiment, a cluster size must be set at launch attribute1602is used to determine whether a cluster size must be sent at launch of a cluster. In at least one embodiment, cluster size must be set at launch attribute1602is used by indicate cluster parameters API1702, described herein at least in connection withFIG.17, to determine whether a cluster size must be sent at launch of a cluster. In at least one embodiment, cluster size must be set at launch attribute1602that is false indicates that a block cluster such as those described herein can be launched without a set cluster size and, in such an embodiment, a block cluster can be launched without a set cluster size. In at least one embodiment, cluster size must be set at launch attribute1602that is true indicates that a block cluster such as those described herein cannot be launched without a set cluster size and, in such an embodiment, a block cluster cannot be launched without a set cluster size. In at least one embodiment, a graphics processor1606(which is a graphics processor such as graphics processor108, described herein at least in connection withFIG.1) determines an attribute value1608of a cluster size must be set at launch attribute1602and returns an attribute value1604to a calling thread or process (e.g., a calling thread or process that performs indicate cluster parameters API1702, described herein at least in connection withFIG.17). In at least one embodiment, as illustrated inFIG.16, cluster size must be set at launch attribute1602is read-only (e.g., cannot be set by a calling process). In at least one embodiment, not illustrated inFIG.16, cluster size must be set at launch attribute1602is writable (e.g., can be set by a calling process).

In at least one embodiment, a non-portable cluster size allowed attribute1610is used to determine whether a non-portable (e.g., not forward compatible) cluster size can be used to launch of a cluster. In at least one embodiment, non-portable cluster size allowed attribute1610is used by indicate cluster parameters API1702, described herein at least in connection withFIG.17, to determine whether a non-portable (e.g., not forward compatible) cluster size can be used to launch of a cluster. In at least one embodiment, a non-portable cluster size is a cluster size that may not be supported in other hardware configurations of graphics processor1606but is supported by a current hardware configuration of graphics processor1606. In at least one embodiment, non-portable cluster size allowed attribute1610that is true indicates that a block cluster such as those described herein can be launched with a non-portable cluster size and, in such an embodiment, a block cluster can be launched with a non-portable cluster size. In at least one embodiment, non-portable cluster size allowed attribute1610that is false indicates that a block cluster such as those described herein cannot be launched with a non-portable cluster size and, in such an embodiment, a block cluster cannot be launched with a non-portable cluster size. In at least one embodiment, a graphics processor1606determines an attribute value1614of a non-portable cluster size allowed attribute1610and returns an attribute value1612to a calling thread or process (e.g., a calling thread or process that performs indicate cluster parameters API1702, described herein at least in connection withFIG.17). In at least one embodiment, as illustrated inFIG.16, non-portable cluster size allowed attribute1610is read-write (e.g., can be set by a calling process). In at least one embodiment, not illustrated inFIG.16, non-portable cluster size allowed attribute1610is read-only (e.g., cannot be set by a calling process).

In at least one embodiment, one or more other attributes1616of a block cluster can be indicated and/or obtained including, but not limited, those described herein such as, for example, cluster size, cluster dimension, cluster scheduling policies, etc. In at least one embodiment, one or more other attributes1616of a block cluster are used by indicate cluster parameters API1702, described herein at least in connection withFIG.17, to determine one or more other attributes of a cluster. In at least one embodiment, graphics processor1606determined attribute values1620of one or more other attributes1616and returns one or more attribute values1618to a calling process. In at least one embodiment, at least one of one or more other attributes1616is read-write (e.g., can be set by a calling process). In at least one embodiment, at least one of one or more other attributes1616is read-only (e.g., cannot be set by a calling process).

FIG.17illustrates an example application programming interface1700to indicate and obtain attributes of block clusters, in accordance with at least one embodiment. In at least one embodiment, example application programming interface1700to indicate and obtain attributes of block clusters is an indicate cluster parameters API1702. In at least one embodiment, an API such as indicate cluster parameters API1702is performed by a processor, such as those described herein. In at least one embodiment, an API such as indicate cluster parameters API1702is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as indicate cluster parameters API1702is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as indicate cluster parameters API1702is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as indicate cluster parameters API1702, when performed, is to indicate one or more attributes of one or more groups of blocks of one or more threads.

In at least one embodiment, indicate cluster parameters API1702is an API comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, indicate cluster parameters API1702is an API to obtain one or more attributes of one or more clusters of one or more groups of instructions. In at least one embodiment, indicate cluster parameters API1702is an API to get or set cluster attributes as described herein at least in connection withFIG.16. In at least one embodiment, indicate cluster parameters API1702receives one or more parameters including, but not limited to, an attribute1704, an attribute value1706, and an indicator1708as to whether to set or get an attribute. In at least one embodiment, indicate cluster parameters API1702returns return value1728.

In at least one embodiment, attribute1704of indicate cluster parameters API1702is an attribute such as those described herein that indicates one or more parameters of one or more block clusters. In at least one embodiment, attribute value1706of indicate cluster parameters API1702is a value of attribute1704. In at least one embodiment, indicator1708of indicate cluster parameters API1702is used to determine whether a value stored in attribute value1706is used to set an attribute1704or is used to store a value of an attribute1704.

In at least one embodiment, not shown inFIG.17, indicate cluster parameters API1702receives one or more additional parameters and/or of flags that specify how attribute1704, attribute value1706, and/or indicator1708will be used to indicate and/or obtain attributes of block clusters. In at least one embodiment, when additional parameters and/or of flags that specify how attribute1704, attribute value1706, and/or indicator1708will be used to indicate and/or obtain attributes of block clusters are not received, one or more default parameters and/or flags may be used by indicate cluster parameters API1702to indicate and/or obtain attributes of block clusters, using systems and methods such as those described herein.

In at least one embodiment, indicate cluster parameters API1702causes a processor such as those described herein to execute one or more commands to determine1712whether indicator1708is to get or to set a value of an attribute. In at least one embodiment, if it is determined that indicator1708is to get an attribute (“GET” branch), indicate cluster parameters API1702causes a processor such as those described herein to execute one or more commands to get an attribute1714, store an attribute1716(e.g., using storage in attribute value1706), and return success1718using return value1728.

In at least one embodiment, if it is determined that indicator1708is to set an attribute (“SET” branch), indicate cluster parameters API1702causes a processor such as those described herein to execute one or more commands to determine1720whether an attribute is settable. In at least one embodiment, if it is determined that an attribute is not settable (“NO” branch), indicate cluster parameters API1702causes a processor such as those described herein to execute one or more commands to return failure1722using return value1728. In at least one embodiment, if it is determined that an attribute is settable (“YES” branch), indicate cluster parameters API1702causes a processor such as those described herein to execute one or more commands to set an attribute1724using attribute value1706and to return success1726using return value1728.

In at least one embodiment, indicate cluster parameters API1702returns success1718, returns failure1722, or returns success1726using return value1728to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, indicate cluster parameters API1702returns success1718, returns failure1722, or returns success1726using return value1728to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.18illustrates an example computer system1800where a maximum cluster size that can be simultaneously performed is obtained, in accordance with at least one embodiment. In at least one embodiment, a processor1802(which is a processor such as processor102, described herein at least in connection withFIG.1), executes or otherwise performs one or more commands to request a maximum cluster size that can be supported by graphics hardware1804, as described herein. In at least one embodiment, processor1802executes or otherwise performs one or more commands to request a maximum cluster size that can be supported by graphics hardware1804to execute a kernel based, at least in part, on a configuration (not shown inFIG.18). In at least one embodiment, processor1802executes or otherwise performs one or more commands to request a maximum cluster size that can be concurrently executed by graphics hardware.

In at least one embodiment, a graphics processor1806(which is a graphics processor such as graphics processor108, described herein at least in connection withFIG.1), determines a maximum cluster size1808that can be used to execute a kernel. In at least one embodiment, graphics processor1806determines a maximum cluster size1808that can be used to execute a kernel based at least on kernel parameters, a kernel configuration, hardware capabilities of graphics processor1806, available resources, and/or other such factors. In at least one embodiment, graphics processor1806returns a determined maximum cluster size1810to processor1802using methods such as those described herein.

In at least one embodiment, not illustrated inFIG.18, a processor such as processor1802determines information such as, for example, a maximum cluster size that can be simultaneously performed, without executing or otherwise performing one or more commands to request a maximum cluster size that can be supported by graphics hardware1804to execute a kernel. In such an embodiment, processor1802may store information such as maximum cluster size1808in memory associated with processor1802.

FIG.19illustrates an example application programming interface1900to obtain a maximum cluster size that can be simultaneously performed by hardware, in accordance with at least one embodiment. In at least one embodiment, example application programming interface1900to obtain a maximum cluster size that can be simultaneously performed by hardware is a maximum cluster size supported API1902. In at least one embodiment, an API such as maximum cluster size supported API1902is performed by a processor, such as those described herein. In at least one embodiment, an API such as maximum cluster size supported API1902is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as maximum cluster size supported API1902is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as maximum cluster size supported API1902is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as maximum cluster size supported API1902, when performed, is to indicate a maximum number of blocks of threads to be scheduled in parallel.

In at least one embodiment, maximum cluster size supported API1902is an API to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, maximum cluster size supported API1902is an API to obtain a limit of a number of concurrently performable clusters of one or more groups of instructions. In at least one embodiment, maximum cluster size supported API1902is an API to determine a request a maximum cluster size that can be supported by graphics hardware1804, as described herein at least in connection withFIG.18. In at least one embodiment, maximum cluster size supported API1902receives one or more parameters including, but not limited to, a stored maximum cluster size1904, a kernel1906, and/or a launch configuration1908. In at least one embodiment, maximum cluster size supported API1902returns a return value1916.

In at least one embodiment, stored maximum cluster size1904is a location that is used by maximum cluster size supported API1902to return a maximum cluster size that can be simultaneously performed by hardware. In at least one embodiment, kernel1906is a kernel that will be executed by graphics hardware using systems and methods such as those described herein. In at least one embodiment, launch configuration1908includes one or more parameters such as those described herein that may be used to launch kernel1906using block clusters, as described herein.

In at least one embodiment, not shown inFIG.19, maximum cluster size supported API1902receives one or more additional parameters and/or of flags that specify kernel1906and/or launch configuration1908will be used to obtain a maximum cluster size that can be simultaneously performed by hardware. In at least one embodiment, when additional parameters and/or of flags that specify how kernel1906and/or launch configuration1908will be used to obtain a maximum cluster size that can be simultaneously performed by hardware are not received, one or more default parameters and/or flags may be used by maximum cluster size supported API1902to obtain a maximum cluster size that can be simultaneously performed by hardware, using systems and methods such as those described herein.

In at least one embodiment, maximum cluster size supported API1902causes a processor such as those described herein to execute one or more commands to determine maximum cluster size1910using systems and methods such as those described herein at least in connection withFIG.18and stores a determined value1912in stored maximum cluster size1904. In at least one embodiment, maximum cluster size supported API1902returns success or failure1914using return value1916. In at least one embodiment, maximum cluster size supported API1902returns success using return value1916when a maximum cluster size is determined. In at least one embodiment, maximum cluster size supported API1902returns failure using return value1916when a maximum cluster size is not determined.

In at least one embodiment, maximum cluster size supported API1902returns success or failure1914using return value1916to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, maximum cluster size supported API1902returns success or failure1914using return value1916to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.20illustrates an example computer system2000where a software kernel is executed using block clusters, in accordance with at least one embodiment. In at least one embodiment, a processor2002(which is a processor such as processor102, described herein at least in connection withFIG.1) executes or otherwise performs one or more commends to receive cluster parameters2004, generate a kernel2006, and launch a kernel2008using block clusters, based at least in part on cluster parameters2004, using systems and methods such as those described herein.

In at least one embodiment, when cluster parameters2004indicate a spread scheduling policy as described herein, processor2002launches kernel2008using a first block cluster2014on compute unit2014using graphics processor2010(which is a graphics processor such as graphics processor108, described herein at least in connection withFIG.1) and using a second block cluster2018on compute unit2016using graphics processor2010. In at least one embodiment, not illustrated inFIG.20, when cluster parameters2004indicate a balance scheduling policy as described herein, processor2002may launch kernel2008using a first block cluster2014on compute unit2014and may also launch second block cluster2018on compute unit2014or may launch kernel2008using a first block cluster2014on compute unit2016and may also launch second block cluster2018on compute unit2016, or may launch kernel2008using some other distribution of block clusters, based at least in part on cluster parameters2004.

FIG.21illustrates an example application programming interface2100to execute a software kernel using block clusters, in accordance with at least one embodiment. In at least one embodiment, example application programming interface2100to execute a software kernel using block clusters is a launch kernel with block clusters API2102. In at least one embodiment, an API such as launch kernel with block clusters API2102is performed by a processor, such as those described herein. In at least one embodiment, an API such as launch kernel with block clusters API2102is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as launch kernel with block clusters API2102is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as launch kernel with block clusters API2102is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as launch kernel with block clusters API2102, when performed, is to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel.

In at least one embodiment, launch kernel with block clusters API2102is an API to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, launch kernel with block clusters API2102is an API to cause a software kernel to be performed using one or more clusters of one or more groups of instructions. In at least one embodiment, launch kernel with block clusters API2102is an API to launch a kernel using block clusters as described herein at least in connection withFIG.20. In at least one embodiment, launch kernel with block clusters API2102receives one or more parameters including, but not limited to, a kernel2104and one or more cluster parameters2106such as those described herein (e.g., cluster dimensions, cluster scheduling policy, etc.). In at least one embodiment, launch kernel with block clusters API2102returns a return value2114.

In at least one embodiment, kernel2104of launch kernel with block clusters API2102is an identifier of a kernel to launch using block clusters, using systems and methods such as those described herein and cluster parameters2116are parameters such as those described herein that are used to specify how a kernel2104is to be launched using block clusters. In at least one embodiment, not shown inFIG.21, launch kernel with block clusters API2102receives one or more additional parameters and/or of flags that specify how kernel2104and/or cluster parameters2106will be used to execute a software kernel using block clusters. In at least one embodiment, when additional parameters and/or of flags that specify how kernel2104and/or cluster parameters2106will be used to execute a software kernel using block clusters are not received, one or more default parameters and/or flags may be used by launch kernel with block clusters API2102to execute a software kernel using block clusters, using systems and methods such as those described herein.

In at least one embodiment, launch kernel with block clusters API2102causes a processor such as those described herein to execute one or more commands to validate one or more cluster parameters2108as described herein, to launch a kernel using block clusters2110, and to return success or failure2112using return value2114. In at least one embodiment, launch kernel with block clusters API2102returns success using return value2114when launch kernel with block clusters API2102does successfully launch a kernel using block clusters2110. In at least one embodiment, launch kernel with block clusters API2102returns failure using return value2114when launch kernel with block clusters API2102does not successfully launch a kernel using block clusters2110.

In at least one embodiment, launch kernel with block clusters API2102returns success or failure2112using return value2114to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, launch kernel with block clusters API2102returns success or failure2112using return value2114to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.22illustrates an example diagram2200where a hierarchy of threads, thread blocks, block clusters, compute units, and graphics processors is shown, in accordance with at least one embodiment. In at least one embodiment, a graphics processor2202(which is a graphics processor such as graphics processor102, described herein at least in connection withFIG.1) includes one or more compute units. In at least one embodiment, graphics processor2202includes a first compute unit2204(which is a compute unit such as compute unit110, described herein at least in connection withFIG.1). In at least one embodiment, compute unit2204includes one or more block clusters. In at least one embodiment, compute unit2204includes a first block cluster2208(which is a block cluster such as block cluster112, block cluster118, and/or block cluster120, all described herein at least in connection withFIG.1). In at least one embodiment, block cluster2208includes one or more thread blocks. In at least one embodiment, block cluster2208includes a first thread block2212(which is a thread block such as thread block202, described herein at least in connection withFIG.2). In at least one embodiment, thread block2212includes one or more threads (e.g., thread2216, thread2218, etc.), which are threads such as those described herein.

In at least one embodiment, graphics processor2202includes one or more additional compute units (e.g., compute unit2206). In at least one embodiment, a compute unit such as compute unit2206can include one or more block clusters, not illustrated inFIG.22. In at least one embodiment, compute unit2204includes one or more additional block clusters (e.g., block cluster2210). In at least one embodiment, block clusters such as block cluster2210can include one or more thread blocks, not illustrated inFIG.22. In at least one embodiment, block cluster2208includes one or more additional thread blocks (e.g., thread block2214). In at least one embodiment, a thread block such as thread block2214can include one or more threads, not illustrated inFIG.22.

In at least one embodiment, a block cluster such as block cluster2208executes on multiple compute units, as described herein. In at least one embodiment, a block cluster such as block cluster2208executes on a portion of compute units of a graphics processor such as graphics processor2202. In at least one embodiment, a block cluster such as block cluster2208executes on all compute units of a graphics processor such as graphics processor2202. In at least one embodiment, a block cluster such as block cluster2208executes on a plurality of graphics processors such as graphics processor2202so that, for example, a first set of thread blocks of a block cluster execute on a first compute unit of a first graphics processor, a second set of thread blocks of a block cluster execute on a second compute unit of a first graphics processor, a third set of thread blocks of a block cluster execute on a first compute unit of a second graphics processor, a fourth set of thread blocks of a block cluster execute on a second compute unit of a second graphics processor, etc. In at least one embodiment, a plurality of graphics processors are graphics processors of a compute cluster of graphics processors that are connected using one or more technologies such as those described herein. In at least one embodiment, a graphics processor such as graphics processor2202is a virtual graphics processor that spans (or includes) a plurality of physical graphics processors such as those described herein.

FIG.23illustrates an example diagram2300where thread attributes of a calling thread are obtained, in accordance with at least one embodiment. In at least one embodiment, a calling thread2306executes or otherwise performs one or more commands to get thread block and/or block cluster attributes2320associated with calling thread2306. In at least one embodiment, calling thread2306executes or otherwise performs one or more commands to get thread block and/or block cluster attributes2320associated with calling thread2306using get attributes API2602, described herein at least in connection withFIG.26. In at least one embodiment, some other process or processor executes or otherwise performs one or more commands to get thread block and/or block cluster attributes2320associated with calling thread2306using get attributes API2602such as, for example, a process operating on a CPU or a GPU, such as those described herein. In at least one embodiment, calling thread2306is a thread of thread block2304(e.g., a thread block such as those described herein), which has n1threads (e.g., calling thread2306and n1−1 other threads such as thread2308to thread2310). In at least one embodiment, thread block2304is a thread block of block cluster2302(e.g., a block cluster such as those described herein), which has thread block2312with n2threads, thread block2314with n3threads, etc.

In at least one embodiment, calling thread2306executes or otherwise performs one or more commands to get thread block and/or block cluster attributes2320including, for example, a number of threads in a cluster2316, which returns a total number of threads in block cluster2302(e.g., n=n1+n2+n3+ . . . ). In at least one embodiment, an attribute such as number of threads in a cluster2316is referred to as thread-level information. In at least one embodiment, an attribute such as number of threads in a cluster2316is referred to as cluster-level information. In at least one embodiment, calling thread2306executes or otherwise performs one or more commands to get thread block and/or block cluster attributes2320including, for example, an identifier2318of calling thread2306, which returns an index (or rank) from [1, n] where n is a total number of threads in block cluster2302. In at least one embodiment, an attribute such as identifier2318of calling thread2306is referred to as thread-level information.

FIG.24illustrates an example diagram2400where block cluster attributes of a calling thread are obtained, in accordance with at least one embodiment. In at least one embodiment, a calling thread2406executes or otherwise performs one or more commands to get thread block and/or block cluster attributes2416associated with calling thread2406. In at least one embodiment, calling thread2406executes or otherwise performs one or more commands to get thread block and/or block cluster attributes2416associated with calling thread2406using get attributes API2602, described herein at least in connection withFIG.26. In at least one embodiment, some other process or processor executes or otherwise performs one or more commands to get thread block and/or block cluster attributes2416associated with calling thread2406using get attributes API2602such as, for example, a process operating on a CPU or a GPU, such as those described herein. In at least one embodiment, calling thread2406is a thread of thread block2404, which may include one or more other threads (e.g., thread2408). In at least one embodiment, thread block2404is a thread block of block cluster2402, which includes Bx×By×Bzthread blocks (e.g., thread block2410, thread block2412, thread block2414, etc.).

In at least one embodiment, calling thread2406executes or otherwise performs one or more commands to get thread block and/or block cluster attributes2416including, for example, dimensions of a cluster2418, which returns a three-dimensional size of block cluster2402(e.g., (Bx, By, Bz)). In at least one embodiment, an attribute such as dimensions of a cluster2418is referred to as cluster-level information. In at least one embodiment, calling thread2406executes or otherwise performs one or more commands to get thread block and/or block cluster attributes2416including, for example, a block index2420of thread block2404of calling thread2406, which returns a three-dimensional index of thread block2404(e.g., an index from ([1,Bx], [1,By], [1,Bz])). In at least one embodiment, an attribute such as block index2420of thread block2404of calling thread2406is referred to as block-level information. In at least one embodiment, calling thread2406executes or otherwise performs one or more commands to get thread block and/or block cluster attributes2416including, for example, a number of blocks in a cluster2422, which returns a total number of blocks in block cluster2402(e.g., Bx×By×Bz) (e.g., cluster-level information) In at least one embodiment, calling thread2406executes or otherwise performs one or more commands to get thread block and/or block cluster attributes2416including, for example, a block identifier2424of a thread block2404of calling thread2406, which returns an index of thread block2404(e.g., from [1, Bx×By×Bz]) (e.g., block-level information).

FIG.25illustrates an example diagram2500where block cluster group attributes of a calling thread are obtained, in accordance with at least one embodiment. In at least one embodiment, a calling thread2508executes or otherwise performs one or more commands to get thread block, block cluster, and/or compute unit attributes2522associated with calling thread2508. In at least one embodiment, calling thread2508executes or otherwise performs one or more commands to get thread block, block cluster, and/or compute unit attributes2522associated with calling thread2508using get attributes API2602, described herein at least in connection withFIG.26. In at least one embodiment, some other process or processor executes or otherwise performs one or more commands to get thread block, block cluster, and/or compute unit attributes2522associated with calling thread2508using get attributes API2602such as, for example, a process operating on a CPU or a GPU, such as those described herein. In at least one embodiment, calling thread2508is a thread of thread block2506. In at least one embodiment, thread block2506is a thread block of block cluster2504. In at least one embodiment, block cluster2504includes one or more additional thread blocks (e.g., thread block2510, thread block2512, thread block2514, etc.). In at least one embodiment, block cluster2504is a block cluster of compute unit2502. In at least one embodiment, compute unit2502includes Cx×Cy×Czblock clusters (e.g., block cluster2516, block cluster2518, block cluster2520, etc.).

In at least one embodiment, calling thread2508executes or otherwise performs one or more commands to get thread block, block cluster, and/or compute unit attributes2522including, for example, cluster dimensions of a grid2524, which returns a three-dimensional size of block clusters in compute unit2502(e.g., (Cx, Cy, Cz)). In at least one embodiment, calling thread2508executes or otherwise performs one or more commands to get thread block, block cluster, and/or compute unit attributes2522including, for example, a cluster index2526of block cluster2504of thread block2506of calling thread2508, which returns a three-dimensional index of block cluster2504(e.g., an index from ([1,Cx], [1,Cy], [1,Cz])). In at least one embodiment, calling thread2508executes or otherwise performs one or more commands to get thread block, block cluster, and/or compute unit attributes2522including, for example, a number of block clusters of grid2528, which returns a total number of block clusters of compute unit2502(e.g., Cx×Cy×Cz). In at least one embodiment, calling thread2508executes or otherwise performs one or more commands to get thread block, block cluster, and/or compute unit attributes2522including, for example, a block cluster identifier2530of block cluster2504of thread block2506of calling thread2508, which returns an index of block cluster2504(e.g., from [1, Cx×Cy×Cz]).

FIG.26illustrates an example application programming interface2600to obtain thread, thread block, block cluster, and block cluster group attributes of a calling thread, in accordance with at least one embodiment. In at least one embodiment, example application programming interface2600to obtain thread, thread block, block cluster, and block cluster group attributes of a calling thread is a get attributes API2602. In at least one embodiment, an API such as get attributes API2602is performed by a processor, such as those described herein. In at least one embodiment, an API such as get attributes API2602is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as get attributes API2602is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as get attributes API2602is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as get attributes API2602, when performed, is to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads.

In at least one embodiment, get attributes API2602is an API comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, get attributes API2602is an API to obtain one or more parameters of one or more clusters of one or more groups of instructions of a set of one or more clusters of one or more groups of instructions. In at least one embodiment, get attributes API2602is an API to obtain thread block, block cluster, and/or compute unit attributes of a calling thread as described herein at least in connection withFIGS.23-25. In at least one embodiment, get attributes API2602receives one or more parameters including, but not limited to, a calling thread ID2604, an attribute2606, and/or an attribute type2608. In at least one embodiment, get attributes API2602returns a return value2616.

In at least one embodiment, calling thread ID2604of get attributes API2602is an identifier of a calling thread that calls get attributes API2602and attribute2606of get attributes API2602is an attribute of calling thread identified by calling thread ID2604such as those described herein at least in connection withFIGS.23-25. In at least one embodiment, attribute type2608of get attributes API2602is a return type of attribute2606(e.g., a value, or a three-dimensional value, etc.).

In at least one embodiment, not shown inFIG.26, get attributes API2602receives one or more additional parameters and/or of flags that specify how attribute2606and/or attribute type2608will be used to obtain thread, thread block, block cluster, and block cluster group attributes of a calling thread identified by calling thread ID2604(e.g., attributes of a thread hierarchy of which a calling thread identified by calling thread ID2604is a member). In at least one embodiment, when additional parameters and/or of flags that specify how attribute2606and/or attribute type2608will be used to obtain thread, thread block, block cluster, and block cluster group attributes of a calling thread identified by calling thread ID2604(e.g., attributes of a thread hierarchy of which a calling thread identified by calling thread ID2604is a member) are not received, one or more default parameters and/or flags may be used by get attributes API2602to obtain thread, thread block, block cluster, and block cluster group attributes of a calling thread, using systems and methods such as those described herein.

In at least one embodiment, get attributes API2602causes a processor such as those described herein to execute one or more commands to identify2610a thread, thread block, block cluster, and/or grid of a calling thread identified by calling thread ID2604and to determine2612a value of a requested attribute2606, as described herein. In at least one embodiment, get attributes API2602returns a determined attribute2614using return value2616.

In at least one embodiment, get attributes API2602returns a determined attribute2614using return value2616to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, get attributes API2602returns a determined attribute2614using return value2616to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.27illustrates an example diagram2700where threads of a block cluster are waiting on other threads to perform a barrier instruction, in accordance with at least one embodiment. In at least one embodiment, a first thread2706of a thread block2704of a block cluster2702is being performed and first thread2706has not reached a barrier instruction2708, as described herein. In at least one embodiment, a second thread2710of thread block2704of block cluster2702is waiting and second thread2710has reached barrier instruction2708, as described herein. In at least one embodiment, second thread2710is waiting because second thread2710has performed barrier instruction2708.

In at least one embodiment, a third thread2714of a thread block2712of block cluster2702is waiting and third thread2714has reached barrier instruction2708, as described herein. In at least one embodiment, third thread2714is waiting because third thread2714has performed barrier instruction2708. In at least one embodiment, a fourth thread2716of thread block2712of block cluster2702is waiting and fourth thread2716has reached barrier instruction2708, as described herein. In at least one embodiment, fourth thread2716is waiting because fourth thread2716has performed barrier instruction2708.

FIG.28illustrates an example diagram2800where threads of a block cluster have performed a barrier instruction, in accordance with at least one embodiment. In at least one embodiment, threads illustrated in example diagram2800are identical to threads illustrated in example diagram2700where example diagram2800follows after first thread2806has arrived at barrier instruction2808. In at least one embodiment, a first thread2806(which is first thread2706of example diagram2700) of a thread block2804(e.g., thread block2704of example diagram2700) of a block cluster2802(e.g., block cluster2702of example diagram2700) has reached a barrier instruction2808(e.g., barrier instruction2708of example diagram2700). In at least one embodiment, first thread2806is waiting because first thread2806has performed barrier instruction2808. In at least one embodiment, a second thread2810(e.g., second thread2710of example diagram2700) of thread block2804of block cluster2802is waiting, as described herein.

In at least one embodiment, a third thread2814(e.g., third thread2714of example diagram2700) of a thread block2812(e.g., thread block2712of example diagram2700) of block cluster2802is waiting, as described herein. In at least one embodiment, a fourth thread2816(e.g., fourth thread2716of example diagram2700) of thread block2812of block cluster2802is waiting, as described herein.

FIG.29illustrates an example diagram2900where threads of a block cluster resume after performing a barrier instruction, in accordance with at least one embodiment. In at least one embodiment, threads illustrated in example diagram2800are identical to threads illustrated in example diagram2800where example diagram2800follows after first thread2906has arrived at barrier instruction2908and all threads have resumed execution. In at least one embodiment, all threads illustrated in example diagram2900have resumed as all threads illustrated in example diagram2900have performed barrier instruction2908and may thus resume execution.

In at least one embodiment, a first thread2906(which is first thread2806of example diagram2800) of a thread block2904(e.g., thread block2804of example diagram2800) of a block cluster2902(e.g., block cluster2802of example diagram2800) has reached a barrier instruction2908(e.g., barrier instruction2808of example diagram2800) and has resumed execution beyond barrier instruction2908. In at least one embodiment, a second thread2910(e.g., second thread2810of example diagram2800) of thread block2904is has resumed execution beyond barrier instruction2908, a third thread2914(e.g., third thread2814of example diagram2800) of a thread block2912(e.g., thread block2812of example diagram2800) has resumed execution beyond barrier instruction2908, and a fourth thread2916(e.g., fourth thread2818of example diagram2800) of thread block2912has resumed execution beyond barrier instruction2908.

FIG.30illustrates an example application programming interface3000to determine if threads of a block cluster have performed a barrier instruction, in accordance with at least one embodiment. In at least one embodiment, example application programming interface3000to determine if threads of a block cluster have performed a barrier instruction is a kernel barrier arrive API3002. In at least one embodiment, an API such as kernel barrier arrive API3002is performed by a processor, such as those described herein. In at least one embodiment, an API such as kernel barrier arrive API3002is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as kernel barrier arrive API3002is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as kernel barrier arrive API3002is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as kernel barrier arrive API3002, when performed, is to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction.

In at least one embodiment, kernel barrier arrive API3002is an API to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, kernel barrier arrive API3002is an API to indicate arrival at a barrier instruction of a cluster of one or more groups of instructions. In at least one embodiment, kernel barrier arrive API3002is an API to manage synchronization of one or more threads of block clusters, as described herein at least in connection withFIGS.27-29. In at least one embodiment, kernel barrier arrive API3002receives one or more parameters including, but not limited to, a calling thread ID3004. In at least one embodiment, kernel barrier arrive API3002returns a return value3014.

In at least one embodiment, calling thread ID3004of kernel barrier arrive API3002is an identifier of a thread that executes or otherwise performs one or more commands to perform kernel barrier arrive API3002. In at least one embodiment, not shown inFIG.30, kernel barrier arrive API3002receives one or more additional parameters and/or of flags that specify how calling thread ID3004will be used to determine if threads of a block cluster have performed a barrier instruction. In at least one embodiment, when additional parameters and/or of flags that specify how calling thread ID3004will be used to determine if threads of a block cluster have performed a barrier instruction are not received, one or more default parameters and/or flags may be used by kernel barrier arrive API3002to determine if threads of a block cluster have performed a barrier instruction, using systems and methods such as those described herein.

In at least one embodiment, kernel barrier arrive API3002causes a processor such as those described herein to execute one or more commands to identify3006a thread, thread block, block cluster, and/or compute group of a calling thread identified by calling thread ID3004, determine3008whether a barrier instruction has been reached by a calling thread identified by calling thread ID3004, and determine3010whether to wait or proceed with thread execution based, at least in part, on determining whether a barrier instruction has been reached by a calling thread identified by calling thread ID3004. In at least one embodiment, a determination of whether a barrier instruction has been reached by a calling thread identified by calling thread ID3004may be a determination of whether a barrier instruction has not been reach by a calling thread identified by calling thread ID3004. In at least one embodiment, for example, kernel barrier arrive API3002may determine3008that no threads, including a calling thread identified by calling thread ID3004, have reached a barrier instruction. In at least one embodiment, kernel barrier arrive API3002causes a processor such as those described herein to execute one or more commands to report a barrier arrival status3012based, at least in part, on determining whether a barrier instruction has been reached by a calling thread identified by calling thread ID3004.

In at least one embodiment, kernel barrier arrive API3002reports barrier arrival status3012using return value3014. In at least one embodiment, kernel barrier arrive API3002reports barrier arrival status3012using return value3014to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, kernel barrier arrive API3002reports barrier arrival status3012using return value3014to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.31illustrates an example application programming interface3100to determine if a thread should stop until all other threads of a block cluster have performed a barrier instruction, in accordance with at least one embodiment. In at least one embodiment, example application programming interface3100to determine if a thread should stop until all other threads of a block cluster have performed a barrier instruction is a kernel barrier wait API3102. In at least one embodiment, an API such as kernel barrier wait API3102is performed by a processor, such as those described herein. In at least one embodiment, an API such as kernel barrier wait API3102is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as kernel barrier wait API3102is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as kernel barrier wait API3102is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as kernel barrier wait API3102, when performed, is to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction.

In at least one embodiment, kernel barrier wait API3102is an API to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, kernel barrier wait API3102is an API to cause one or more first instructions to be prevented from being performed until a cluster of one or more groups of instructions have performed one or more second instructions. In at least one embodiment, kernel barrier wait API3102is an API to manage synchronization of one or more threads of block clusters, as described herein at least in connection withFIGS.27-29. In at least one embodiment, kernel barrier wait API3102receives one or more parameters including, but not limited to, a calling thread ID3104. In at least one embodiment, kernel barrier wait API3102returns a return value3112.

In at least one embodiment, calling thread ID3104of kernel barrier wait API3102is an identifier of a calling thread that executes or otherwise performs one or more commands to perform kernel barrier wait API3102. In at least one embodiment, not shown inFIG.31, kernel barrier wait API3102receives one or more additional parameters and/or of flags that specify how calling thread ID3104will be used to determine if a calling thread identified by calling thread ID3104should stop until all other threads of a block cluster have performed a barrier instruction. In at least one embodiment, when additional parameters and/or of flags that specify how calling thread ID3104will be used to determine if a calling thread identified by calling thread ID3104should stop until all other threads of a block cluster have performed a barrier instruction are not received, one or more default parameters and/or flags may be used by kernel barrier wait API3102to determine if a thread should stop until all other threads of a block cluster have performed a barrier instruction, using systems and methods such as those described herein.

In at least one embodiment, kernel barrier wait API3102causes a processor such as those described herein to execute one or more commands to identify3106a thread, thread block, block cluster, and/or compute group of a calling thread identified by calling thread ID3104and determine3108whether a barrier instruction has been reached one or more other threads associated with a block cluster of a calling thread identified by calling thread ID3104. In at least one embodiment, a determination of whether a barrier instruction has been reached one or more other threads associated with a block cluster of a calling thread identified by calling thread ID3104may be a determination of whether a barrier instruction has not been reached one or more other threads associated with a block cluster of a calling thread identified by calling thread ID3104. In at least one embodiment, for example, kernel barrier wait API3102may determine3108that no threads, including a calling thread identified by calling thread ID3104, have reached a barrier instruction. In at least one embodiment, kernel barrier wait API3102causes a processor such as those described herein to execute one or more commands to report a determination of whether a calling thread identified by calling thread ID3104should wait or proceed3110based, at least in part, on whether a barrier instruction has been reached one or more other threads associated with a block cluster of a calling thread identified by calling thread ID3104.

In at least one embodiment, kernel barrier wait API3102returns a determination whether to wait or proceed3110using return value3112. In at least one embodiment, kernel barrier wait API3102returns determination whether to wait or proceed3110using return value3112to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, kernel barrier wait API3102returns determination whether to wait or proceed3110using return value3112to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.32illustrates an example application programming interface3200to determine if threads of a block cluster have performed a barrier instruction and to stop until all other threads of a block cluster have performed a barrier instruction, in accordance with at least one embodiment. In at least one embodiment, example application programming interface3200to determine if threads of a block cluster have performed a barrier instruction and to stop until all other threads of a block cluster have performed a barrier instruction is a kernel barrier sync API3202. In at least one embodiment, an API such as kernel barrier sync API3202is performed by a processor, such as those described herein. In at least one embodiment, an API such as kernel barrier sync API3202is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as kernel barrier sync API3202is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as kernel barrier sync API3202is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as kernel barrier sync API3202, when performed, is to indicate whether one or more threads within a group of blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction.

In at least one embodiment, kernel barrier sync API3202is an API to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, kernel barrier sync API3202is an API to cause one or more first instructions to be prevented from being performed until a cluster of one or more groups of instructions have performed one or more second instructions. In at least one embodiment, kernel barrier synch API3202is an API to manage synchronization of one or more threads of block clusters, as described herein at least in connection withFIGS.27-29. In at least one embodiment, kernel barrier sync API3202receives one or more parameters including, but not limited to, a calling thread ID3204. In at least one embodiment, kernel barrier sync API3202returns a return value3218.

In at least one embodiment, calling thread ID3204of kernel barrier sync API3202is an identifier of a calling thread that executes or otherwise performs one or more commands to perform kernel barrier sync API3202. In at least one embodiment, not shown inFIG.32, kernel barrier sync API3202receives one or more additional parameters and/or of flags that specify how calling thread ID3204will be used to determine if threads of a block cluster have performed a barrier instruction and to stop until all other threads of a block cluster have performed a barrier instruction. In at least one embodiment, when additional parameters and/or of flags that specify how calling thread ID3204will be used to determine if threads of a block cluster have performed a barrier instruction and to stop until all other threads of a block cluster have performed a barrier instruction are not received, one or more default parameters and/or flags may be used by kernel barrier sync API3202to determine if threads of a block cluster have performed a barrier instruction and to stop until all other threads of a block cluster have performed a barrier instruction, using systems and methods such as those described herein.

In at least one embodiment, kernel barrier sync API3202causes a processor such as those described herein to execute one or more commands to identify3206a thread, thread block, block cluster, and/or compute group of a calling thread identified by calling thread ID3204, determine3208whether a barrier instruction has been reached by a calling thread identified by calling thread ID3204and determine3210whether to wait or proceed with thread execution based, at least in part, on determining whether a barrier instruction has been reached by a calling thread identified by calling thread ID3204. In at least one embodiment, as described herein, a determination of whether a barrier instruction has been reached by a calling thread identified by calling thread ID3204may be a determination that a barrier instruction has not been reached by a calling thread identified by calling thread ID3204or a determination that no threads have reached a barrier instruction.

In at least one embodiment, kernel barrier sync API3202causes a processor such as those described herein to execute one or more commands to determine3212whether a barrier instruction has been reached one or more other threads associated with a block cluster of a calling thread identified by calling thread ID3204and determine3214whether to wait or proceed with thread execution based, at least in part, on whether a barrier instruction has been reached one or more other threads associated with a block cluster of a calling thread identified by calling thread ID3204. In at least one embodiment, a determination of whether to wait or proceed with thread execution based, at least in part, on determining whether a barrier instruction has been reached by a calling thread identified by calling thread ID3204may be combined with a determination of whether to wait or proceed with thread execution based, at least in part, on whether a barrier instruction has been reached one or more other threads associated with a block cluster of a calling thread identified by calling thread ID3204. In at least one embodiment, kernel barrier sync API3202causes a processor such as those described herein to execute one or more commands to report a barrier arrival status3216based, at least in part, on determining whether a barrier instruction has been reached by a calling thread identified by calling thread ID3204.

In at least one embodiment, kernel barrier sync API3202returns barrier arrival status3216using return value3218. In at least one embodiment, kernel barrier sync API3202returns barrier arrival status3216using return value3218to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, kernel barrier sync API3202returns barrier arrival status3216using return value3218to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.33illustrates an example diagram3300where shared memory of a compute unit is mapped between threads of a block cluster, in accordance with at least one embodiment. In at least one embodiment, a block cluster3306of a compute unit3302has thread block3308and thread block3318, as described herein. In at least one embodiment, shared memory3304includes thread memory3314of a thread3310of thread block3308and thread memory3316of a thread3312of thread block3308. In at least one embodiment, shared memory3304also includes thread memory3322of thread3320of thread block3318.

In at least one embodiment, a thread such as thread3320causes execution of one or more commands to execute an API such as map shared memory API3402, described herein at least in connection withFIG.34to map3324thread memory3316of thread3312to thread3320so that thread3320can access thread memory3316. In at least one embodiment, thread3320executes or otherwise performs one or more commands to map3324thread memory3316read-only, so that thread3320can read from thread memory3316but cannot write to thread memory3316. In at least one embodiment, thread3320executes or otherwise performs one or more commands to map3324thread memory3316as writable, so that thread3320can write to thread memory3316.

In at least one embodiment, not shown inFIG.33, a thread such as thread3320is part of a first thread block of a first block cluster of a first compute unit of a graphics processor such as those described herein and thread memory3316of thread3312is of a second (e.g., different) compute unit of a graphics processor so that thread3320accesses thread memory in shared memory of a different compute unit. In at least one embodiment, not shown inFIG.33, a thread such as thread3320is part of a first thread block of a first block cluster of a first compute unit of a first graphics processor such as those described herein and thread memory3316of thread3312is of a different compute unit of a second (e.g., different) graphics processor so that thread3320accesses thread memory in shared memory of a different compute unit of a different graphics processor, as described herein.

FIG.34illustrates an example application programming interface3400to map memory between threads of a block cluster, in accordance with at least one embodiment. In at least one embodiment, example application programming interface3400to map memory between threads of a block cluster is a map shared memory API3402. In at least one embodiment, an API such as map shared memory API3402is performed by a processor, such as those described herein. In at least one embodiment, an API such as map shared memory API3402is performed as one or more steps of a computer-implemented method, as described herein. In at least one embodiment, an API such as map shared memory API3402is performed by one or more processors of a computer system, as described herein. In at least one embodiment, an API such as map shared memory API3402is stored as instructions on a machine-readable medium, which can be performed using one or more processors, as described herein. In at least one embodiment, an API such as map shared memory API3402], when performed, is to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, map shared memory API3402is an API to cause memory to be shared between two or more groups of blocks of threads. In at least one embodiment, map shared memory API3402is an API to cause one or more memory locations of first cluster of one or more groups of instructions to be accessible to a second cluster of one or more groups of instructions. In at least one embodiment, map shared memory API3402is an API to map thread memory between threads of a block cluster, as described herein at least in connection withFIG.33. In at least one embodiment, map shared memory API3402receives one or more parameters including, but not limited to, a calling thread3404, a memory address3406, and/or a block rank3408. In at least one embodiment, map shared memory API3402returns a return value3418.

In at least one embodiment, calling thread3404of map shared memory API3402is an identifier of a thread that executes or otherwise performs one or more commands to perform map shared memory API3402. In at least one embodiment, memory address3406is a memory address that is used to generate a translated memory address. In at least one embodiment, block rank3408is a rank of a block within a block cluster that is determined as described herein.

In at least one embodiment, not shown inFIG.34, map shared memory API3402receives one or more additional parameters and/or of flags that specify how calling thread3404, memory address3406, and/or block rank3408will be used to map memory between threads of a block cluster. In at least one embodiment, when additional parameters and/or of flags that specify how calling thread3404, memory address3406, and/or block rank3408will be used to map memory between threads of a block cluster are not received, one or more default parameters and/or flags may be used by map shared memory API3402to map memory between threads of a block cluster, using systems and methods such as those described herein.

In at least one embodiment, map shared memory API3402causes a processor such as those described herein to execute one or more commands to identify3410a thread, thread block, block cluster, and/or compute group of calling thread3404, translate3412memory address3406based at least in part on a thread block, block cluster, and/or compute group of calling thread3404and/or based at least in part on block rank3408. In at least one embodiment, map shared memory API3402causes a processor such as those described herein to execute one or more commands to store3414and/or to return3416a translated address to that calling thread3404can map memory using a translated address. In at least one embodiment, map shared memory API3402returns a translated address using return value3418. In at least one embodiment, not shown inFIG.34, map shared memory API3402returns success and/or failure as described herein.

In at least one embodiment, map shared memory API3402returns a translated address using return value3418to a calling process such as example process600described herein at least in connection withFIG.6. In at least one embodiment, map shared memory API3402returns a translated address using return value3418to a calling process using integer value, or using a Boolean value, or using an enumerated value, or using a flag, or using a signal, or using a semaphore, or using an event, or using a combination of these and/or other such return value types including, but not limited to, those described herein.

FIG.35illustrates an example software stack3500where application programming interface calls associated with block clusters are processed, in accordance with at least one embodiment. In at least one embodiment, example software stack3500is at least a part of a software stack such as those described herein. In at least one embodiment, an application3502executes a command to determine if a feature3504is supported. In at least one embodiment, an application3502executes a command to determine if feature3504to perform an API such as those described herein is supported.

In at least one embodiment, application3502uses3506one or more runtime APIs3508to determine if feature3504is supported. In at least one embodiment, runtime APIs3508use3510one or more driver APIs3512to determine if feature3504is supported. In at least one embodiment, not shown inFIG.35, application3502uses one or more driver APIs3512to determine if feature3504is supported. In at least one embodiment, driver APIs3512query3514computer system hardware3516to determine if feature3504is supported.

In at least one embodiment, computer system hardware3516determines if feature3504is supported by a processor3534, by querying a set of capabilities associated with processor3534. In at least one embodiment, processor3534is a processor such as processor102, described herein at least in connection withFIG.1. In at least one embodiment, computer system hardware3516determines if a feature3504is supported by processor3534, using an operating system of processor3534. In at least one embodiment, computer system hardware3516determines if feature is supported by a graphics processor3536by querying a set of capabilities associated with graphics processor3536. In at least one embodiment, graphics processor3536is a graphics processor such as graphics processor108, described herein at least in connection withFIG.1. In at least one embodiment, computer system hardware3516determines if feature3504is supported by graphics processor3536using an operating system of processor3534. In at least one embodiment, computer system hardware3516determines if feature3504is supported by graphics processor3536, using an operating system of graphics processor3536.

In at least one embodiment, after computer system hardware3516determines whether feature3504is supported, computer system hardware3516returns3518a determination result using driver APIs3512, which may return3520a determination result using runtime APIs3508, which may return3522a determination result to application3502. In at least one embodiment, if application3502receives a determination result that indicates that feature3504is supported3524, application3502performs a feature3526using one or more APIs such as those described herein at least in connection withFIGS.7-34(e.g., set block cluster dimension API802, get cluster dimension API902, set scheduling policy API1202, get scheduling policy API1302, number of blocks supported API1502, indicate cluster parameters API1702, maximum cluster size supported API1902, launch kernel with block clusters API2102, get attributes API2602, kernel barrier arrive API3002, kernel barrier wait API3102, kernel barrier sync API3202, and/or map shared memory API3402). In at least one embodiment, application3502performs feature3526using systems and methods such as those described herein.

In at least one embodiment, application3502performs feature3526using3528runtime APIs3508including, but not limited to, runtime versions of APIs such as those described herein at least in connection withFIGS.7-34(e.g., set block cluster dimension API802, get cluster dimension API902, set scheduling policy API1202, get scheduling policy API1302, number of blocks supported API1502, indicate cluster parameters API1702, maximum cluster size supported API1902, launch kernel with block clusters API2102, get attributes API2602, kernel barrier arrive API3002, kernel barrier wait API3102, kernel barrier sync API3202, and/or map shared memory API3402).

In at least one embodiment, runtime APIs3508perform feature3526using3530driver APIs3512including, but not limited to, driver versions of APIs such as those described herein at least in connection withFIGS.7-34(e.g., set block cluster dimension API802, get cluster dimension API902, set scheduling policy API1202, get scheduling policy API1302, number of blocks supported API1502, indicate cluster parameters API1702, maximum cluster size supported API1902, launch kernel with block clusters API2102, get attributes API2602, kernel barrier arrive API3002, kernel barrier wait API3102, kernel barrier sync API3202, and/or map shared memory API3402). In at least one embodiment, not shown inFIG.35, application3502performs feature3526using3530driver APIs3512. In at least one embodiment, driver APIs3512perform feature3526using3532computer system hardware3516.

In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concepts may be practiced without one or more of these specific details.

Data Center

FIG.36illustrates an exemplary data center3600, in accordance with at least one embodiment. In at least one embodiment, data center3600includes, without limitation, a data center infrastructure layer3610, a framework layer3620, a software layer3630and an application layer3640.

In at least one embodiment, as shown inFIG.36, data center infrastructure layer3610may include a resource orchestrator3612, grouped computing resources3614, and node computing resources (“node C.R.s”)3616(1)-3616(N), where “N” represents any whole, positive integer. In at least one embodiment, node C.R.s3616(1)-3616(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (“FPGAs”), data processing units (“DPUs”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input/output (“NW I/O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s from among node C.R.s3616(1)-3616(N) may be a server having one or more of above-mentioned computing resources.

In at least one embodiment, resource orchestrator3612may configure or otherwise control one or more node C.R.s3616(1)-3616(N) and/or grouped computing resources3614. In at least one embodiment, resource orchestrator3612may include a software design infrastructure (“SDI”) management entity for data center3600. In at least one embodiment, resource orchestrator3612may include hardware, software or some combination thereof.

In at least one embodiment, as shown inFIG.36, framework layer3620includes, without limitation, a job scheduler3632, a configuration manager3634, a resource manager3636and a distributed file system3638. In at least one embodiment, framework layer3620may include a framework to support software3652of software layer3630and/or one or more application(s)3642of application layer3640. In at least one embodiment, software3652or application(s)3642may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer3620may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system3638for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler3632may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center3600. In at least one embodiment, configuration manager3634may be capable of configuring different layers such as software layer3630and framework layer3620, including Spark and distributed file system3638for supporting large-scale data processing. In at least one embodiment, resource manager3636may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system3638and job scheduler3632. In at least one embodiment, clustered or grouped computing resources may include grouped computing resource3614at data center infrastructure layer3610. In at least one embodiment, resource manager3636may coordinate with resource orchestrator3612to manage these mapped or allocated computing resources.

In at least one embodiment, software3652included in software layer3630may include software used by at least portions of node C.R.s3616(1)-3616(N), grouped computing resources3614, and/or distributed file system3638of framework layer3620. One or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software.

In at least one embodiment, application(s)3642included in application layer3640may include one or more types of applications used by at least portions of node C.R.s3616(1)-3616(N), grouped computing resources3614, and/or distributed file system3638of framework layer3620. In at least one or more types of applications may include, without limitation, CUDA applications.

In at least one embodiment, any of configuration manager3634, resource manager3636, and resource orchestrator3612may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions may relieve a data center operator of data center3600from making possibly bad configuration decisions and possibly avoiding underutilized and/or poor performing portions of a data center.

In at least one embodiment, at least one component shown or described with respect toFIG.36is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads. In at least one embodiment, at least one of grouped computing resources3614and node C.R.3616(1-N) is used to perform at least one aspect described with respect to example computer system100, example diagram200, diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

The following figures set forth, without limitation, exemplary computer-based systems that can be used to implement at least one embodiment.

FIG.37illustrates a processing system3700, in accordance with at least one embodiment. In at least one embodiment, processing system3700includes one or more processors3702and one or more graphics processors3708, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors3702or processor cores3707. In at least one embodiment, processing system3700is a processing platform incorporated within a system-on-a-chip (“SoC”) integrated circuit for use in mobile, handheld, or embedded devices.

In at least one embodiment, processing system3700can include, or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, processing system3700is a mobile phone, smart phone, tablet computing device or mobile Internet device. In at least one embodiment, processing system3700can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In at least one embodiment, processing system3700is a television or set top box device having one or more processors3702and a graphical interface generated by one or more graphics processors3708.

In at least one embodiment, one or more processors3702each include one or more processor cores3707to process instructions which, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores3707is configured to process a specific instruction set3709. In at least one embodiment, instruction set3709may facilitate Complex Instruction Set Computing (“CISC”), Reduced Instruction Set Computing (“RISC”), or computing via a Very Long Instruction Word (“VLIW”). In at least one embodiment, processor cores3707may each process a different instruction set3709, which may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core3707may also include other processing devices, such as a digital signal processor (“DSP”).

In at least one embodiment, processor3702includes cache memory (‘cache”)3704. In at least one embodiment, processor3702can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor3702. In at least one embodiment, processor3702also uses an external cache (e.g., a Level 3 (“L3”) cache or Last Level Cache (“LLC”)) (not shown), which may be shared among processor cores3707using known cache coherency techniques. In at least one embodiment, register file3706is additionally included in processor3702which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). In at least one embodiment, register file3706may include general-purpose registers or other registers.

In at least one embodiment, one or more processor(s)3702are coupled with one or more interface bus(es)3710to transmit communication signals such as address, data, or control signals between processor3702and other components in processing system3700. In at least one embodiment interface bus3710, in one embodiment, can be a processor bus, such as a version of a Direct Media Interface (“DMI”) bus. In at least one embodiment, interface bus3710is not limited to a DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., “PCI,” PCI Express (“PCIe”)), memory buses, or other types of interface buses. In at least one embodiment processor(s)3702include an integrated memory controller3716and a platform controller hub3730. In at least one embodiment, memory controller3716facilitates communication between a memory device and other components of processing system3700, while platform controller hub (“PCH”)3730provides connections to Input/Output (“I/O”) devices via a local I/O bus.

In at least one embodiment, memory device3720can be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as processor memory. In at least one embodiment memory device3720can operate as system memory for processing system3700, to store data3722and instructions3721for use when one or more processors3702executes an application or process. In at least one embodiment, memory controller3716also couples with an optional external graphics processor3712, which may communicate with one or more graphics processors3708in processors3702to perform graphics and media operations. In at least one embodiment, a display device3711can connect to processor(s)3702. In at least one embodiment display device3711can include one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device3711can include a head mounted display (“HMD”) such as a stereoscopic display device for use in virtual reality (“VR”) applications or augmented reality (“AR”) applications.

In at least one embodiment, platform controller hub3730enables peripherals to connect to memory device3720and processor3702via a high-speed I/O bus. In at least one embodiment, I/O peripherals include, but are not limited to, an audio controller3746, a network controller3734, a firmware interface3728, a wireless transceiver3726, touch sensors3725, a data storage device3724(e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device3724can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as PCI, or PCIe. In at least one embodiment, touch sensors3725can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver3726can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (“LTE”) transceiver. In at least one embodiment, firmware interface3728enables communication with system firmware, and can be, for example, a unified extensible firmware interface (“UEFI”). In at least one embodiment, network controller3734can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples with interface bus3710. In at least one embodiment, audio controller3746is a multi-channel high definition audio controller. In at least one embodiment, processing system3700includes an optional legacy I/O controller3740for coupling legacy (e.g., Personal System 2 (“PS/2”)) devices to processing system3700. In at least one embodiment, platform controller hub3730can also connect to one or more Universal Serial Bus (“USB”) controllers3742connect input devices, such as keyboard and mouse3743combinations, a camera3744, or other USB input devices.

In at least one embodiment, an instance of memory controller3716and platform controller hub3730may be integrated into a discreet external graphics processor, such as external graphics processor3712. In at least one embodiment, platform controller hub3730and/or memory controller3716may be external to one or more processor(s)3702. For example, in at least one embodiment, processing system3700can include an external memory controller3716and platform controller hub3730, which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with processor(s)3702.

In at least one embodiment, at least one of processor(s)3702or external graphics processor3712is used to perform at least one aspect described with respect to example computer system100, example diagram200, diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.38illustrates a computer system3800, in accordance with at least one embodiment. In at least one embodiment, computer system3800may be a system with interconnected devices and components, an SOC, or some combination. In at least on embodiment, computer system3800is formed with a processor3802that may include execution units to execute an instruction. In at least one embodiment, computer system3800may include, without limitation, a component, such as processor3802to employ execution units including logic to perform algorithms for processing data. In at least one embodiment, computer system3800may include processors, such as PENTIUM® Processor family, Xeon™, Itanium®, XScale™ and/or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system3800may execute a version of WINDOWS' operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux for example), embedded software, and/or graphical user interfaces, may also be used.

In at least one embodiment, computer system3800may include, without limitation, processor3802that may include, without limitation, one or more execution units3808that may be configured to execute a Compute Unified Device Architecture (“CUDA”) (CUDA® is developed by NVIDIA Corporation of Santa Clara, CA) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in a CUDA programming language. In at least one embodiment, computer system3800is a single processor desktop or server system. In at least one embodiment, computer system3800may be a multiprocessor system. In at least one embodiment, processor3802may include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor3802may be coupled to a processor bus3810that may transmit data signals between processor3802and other components in computer system3800.

In at least one embodiment, processor3802may include, without limitation, a Level 1 (“L1”) internal cache memory (“cache”)3804. In at least one embodiment, processor3802may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor3802. In at least one embodiment, processor3802may also include a combination of both internal and external caches. In at least one embodiment, a register file3806may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer register.

In at least one embodiment, execution unit3808, including, without limitation, logic to perform integer and floating point operations, also resides in processor3802. Processor3802may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit3808may include logic to handle a packed instruction set3809. In at least one embodiment, by including packed instruction set3809in an instruction set of a general-purpose processor3802, along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in a general-purpose processor3802. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using full width of a processor's data bus for performing operations on packed data, which may eliminate a need to transfer smaller units of data across a processor's data bus to perform one or more operations one data element at a time.

In at least one embodiment, execution unit3808may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system3800may include, without limitation, a memory3820. In at least one embodiment, memory3820may be implemented as a DRAM device, an SRAM device, flash memory device, or other memory device. Memory3820may store instruction(s)3819and/or data3821represented by data signals that may be executed by processor3802.

In at least one embodiment, a system logic chip may be coupled to processor bus3810and memory3820. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”)3816, and processor3802may communicate with MCH3816via processor bus3810. In at least one embodiment, MCH3816may provide a high bandwidth memory path3818to memory3820for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH3816may direct data signals between processor3802, memory3820, and other components in computer system3800and to bridge data signals between processor bus3810, memory3820, and a system I/O3822. In at least one embodiment, system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH3816may be coupled to memory3820through high bandwidth memory path3818and graphics/video card3812may be coupled to MCH3816through an Accelerated Graphics Port (“AGP”) interconnect3814.

In at least one embodiment, computer system3800may use system I/O3822that is a proprietary hub interface bus to couple MCH3816to I/O controller hub (“ICH”)3830. In at least one embodiment, ICH3830may provide direct connections to some I/O devices via a local I/O bus. In at least one embodiment, local I/O bus may include, without limitation, a high-speed I/O bus for connecting peripherals to memory3820, a chipset, and processor3802. Examples may include, without limitation, an audio controller3829, a firmware hub (“flash BIOS”)3828, a wireless transceiver3826, a data storage3824, a legacy I/O controller3823containing a user input interface3825and a keyboard interface, a serial expansion port3827, such as a USB, and a network controller3834. Data storage3824may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

In at least one embodiment,FIG.38illustrates a system, which includes interconnected hardware devices or “chips.” In at least one embodiment,FIG.38may illustrate an exemplary SoC. In at least one embodiment, devices illustrated inFIG.38may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system3800are interconnected using compute express link (“CXL”) interconnects.

In at least one embodiment, at least one component shown or described with respect toFIG.38is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, processor3802is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, processor3802is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, processor3802is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, processor3802is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, processor3802is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, processor3802is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, processor3802is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, processor3802is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, processor3802is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, processor3802is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, processor3802is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, processor3802is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, processor3802is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, processor3802is used to perform at least one aspect described with respect to example computer system100, example diagram200, diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.39illustrates a system3900, in accordance with at least one embodiment. In at least one embodiment, system3900is an electronic device that utilizes a processor3910. In at least one embodiment, system3900may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more on-premise or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

In at least one embodiment, system3900may include, without limitation, processor3910communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor3910is coupled using a bus or interface, such as an I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a USB (versions 1, 2, 3), or a Universal Asynchronous Receiver/Transmitter (“UART”) bus. In at least one embodiment,FIG.39illustrates a system which includes interconnected hardware devices or “chips.” In at least one embodiment,FIG.39may illustrate an exemplary SoC. In at least one embodiment, devices illustrated inFIG.39may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components ofFIG.39are interconnected using CXL interconnects.

In at least one embodiment,FIG.39may include a display3924, a touch screen3925, a touch pad3930, a Near Field Communications unit (“NFC”)3945, a sensor hub3940, a thermal sensor3946, an Express Chipset (“EC”)3935, a Trusted Platform Module (“TPM”)3938, BIOS/firmware/flash memory (“BIOS, FW Flash”)3922, a DSP3960, a Solid State Disk (“SSD”) or Hard Disk Drive (“HDD”)3920, a wireless local area network unit (“WLAN”)3950, a Bluetooth unit3952, a Wireless Wide Area Network unit (“WWAN”)3956, a Global Positioning System (“GPS”)3955, a camera (“USB 3.0 camera”)3954such as a USB 3.0 camera, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”)3915implemented in, for example, LPDDR3 standard. These components may each be implemented in any suitable manner.

In at least one embodiment, other components may be communicatively coupled to processor3910through components discussed above. In at least one embodiment, an accelerometer3941, an Ambient Light Sensor (“ALS”)3942, a compass3943, and a gyroscope3944may be communicatively coupled to sensor hub3940. In at least one embodiment, a thermal sensor3939, a fan3937, a keyboard3936, and a touch pad3930may be communicatively coupled to EC3935. In at least one embodiment, a speaker3963, a headphones3964, and a microphone (“mic”)3965may be communicatively coupled to an audio unit (“audio codec and class d amp”)3962, which may in turn be communicatively coupled to DSP3960. In at least one embodiment, audio unit3962may include, for example and without limitation, an audio coder/decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”)3957may be communicatively coupled to WWAN unit3956. In at least one embodiment, components such as WLAN unit3950and Bluetooth unit3952, as well as WWAN unit3956may be implemented in a Next Generation Form Factor (“NGFF”).

In at least one embodiment, at least one component shown or described with respect toFIG.39is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, processor3910is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, processor3910is used to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, processor3910is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, processor3910is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, processor3910is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, processor3910is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, processor3910is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, processor3910is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, processor3910is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, processor3910is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, processor3910is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, processor3910is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, processor3910is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, processor3910is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.40illustrates an exemplary integrated circuit4000, in accordance with at least one embodiment. In at least one embodiment, exemplary integrated circuit4000is an SoC that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit4000includes one or more application processor(s)4005(e.g., CPUs, DPUs), at least one graphics processor4010, and may additionally include an image processor4015and/or a video processor4020, any of which may be a modular IP core. In at least one embodiment, integrated circuit4000includes peripheral or bus logic including a USB controller4025, a UART controller4030, an SPI/SDIO controller4035, and an I2S/I2C controller4040. In at least one embodiment, integrated circuit4000can include a display device4045coupled to one or more of a high-definition multimedia interface (“HDMI”) controller4050and a mobile industry processor interface (“MIPI”) display interface4055. In at least one embodiment, storage may be provided by a flash memory subsystem4060including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller4065for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine4070.

In at least one embodiment, at least one component shown or described with respect toFIG.40is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, at least one of application processor4005, graphics processor4010, image processor4015, or video processor4020is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.41illustrates a computing system4100, according to at least one embodiment; In at least one embodiment, computing system4100includes a processing subsystem4101having one or more processor(s)4102and a system memory4104communicating via an interconnection path that may include a memory hub4105. In at least one embodiment, memory hub4105may be a separate component within a chipset component or may be integrated within one or more processor(s)4102. In at least one embodiment, memory hub4105couples with an I/O subsystem4111via a communication link4106. In at least one embodiment, I/O subsystem4111includes an I/O hub4107that can enable computing system4100to receive input from one or more input device(s)4108. In at least one embodiment, I/O hub4107can enable a display controller, which may be included in one or more processor(s)4102, to provide outputs to one or more display device(s)4110A. In at least one embodiment, one or more display device(s)4110A coupled with I/O hub4107can include a local, internal, or embedded display device.

In at least one embodiment, processing subsystem4101includes one or more parallel processor(s)4112coupled to memory hub4105via a bus or other communication link4113. In at least one embodiment, communication link4113may be one of any number of standards based communication link technologies or protocols, such as, but not limited to PCIe, or may be a vendor specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s)4112form a computationally focused parallel or vector processing system that can include a large number of processing cores and/or processing clusters, such as a many integrated core processor. In at least one embodiment, one or more parallel processor(s)4112form a graphics processing subsystem that can output pixels to one of one or more display device(s)4110A coupled via I/O Hub4107. In at least one embodiment, one or more parallel processor(s)4112can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s)4110B.

In at least one embodiment, a system storage unit4114can connect to I/O hub4107to provide a storage mechanism for computing system4100. In at least one embodiment, an I/O switch4116can be used to provide an interface mechanism to enable connections between I/O hub4107and other components, such as a network adapter4118and/or wireless network adapter4119that may be integrated into a platform, and various other devices that can be added via one or more add-in device(s)4120. In at least one embodiment, network adapter4118can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter4119can include one or more of a Wi-Fi, Bluetooth, NFC, or other network device that includes one or more wireless radios.

In at least one embodiment, computing system4100can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, that may also be connected to I/O hub4107. In at least one embodiment, communication paths interconnecting various components inFIG.41may be implemented using any suitable protocols, such as PCI based protocols (e.g., PCIe), or other bus or point-to-point communication interfaces and/or protocol(s), such as NVLink high-speed interconnect, or interconnect protocols.

In at least one embodiment, one or more parallel processor(s)4112incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (“GPU”). In at least one embodiment, one or more parallel processor(s)4112incorporate circuitry optimized for general purpose processing. In at least embodiment, components of computing system4100may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processor(s)4112, memory hub4105, processor(s)4102, and I/O hub4107can be integrated into an SoC integrated circuit. In at least one embodiment, components of computing system4100can be integrated into a single package to form a system in package (“SIP”) configuration. In at least one embodiment, at least a portion of the components of computing system4100can be integrated into a multi-chip module (“MCM”), which can be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, I/O subsystem4111and display devices4110B are omitted from computing system4100.

In at least one embodiment, at least one of processor(s)4102or parallel processor(s)4112is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

Processing Systems

The following figures set forth, without limitation, exemplary processing systems that can be used to implement at least one embodiment.

FIG.42illustrates an accelerated processing unit (“APU”)4200, in accordance with at least one embodiment. In at least one embodiment, APU4200is developed by AN/ID Corporation of Santa Clara, CA. In at least one embodiment, APU4200can be configured to execute an application program, such as a CUDA program. In at least one embodiment, APU4200includes, without limitation, a core complex4210, a graphics complex4240, fabric4260, I/O interfaces4270, memory controllers4280, a display controller4292, and a multimedia engine4294. In at least one embodiment, APU4200may include, without limitation, any number of core complexes4210, any number of graphics complexes4250, any number of display controllers4292, and any number of multimedia engines4294in any combination. For explanatory purposes, multiple instances of like objects are denoted herein with reference numbers identifying the object and parenthetical numbers identifying the instance where needed.

In at least one embodiment, core complex4210is a CPU, graphics complex4240is a GPU, and APU4200is a processing unit that integrates, without limitation,4210and4240onto a single chip. In at least one embodiment, some tasks may be assigned to core complex4210and other tasks may be assigned to graphics complex4240. In at least one embodiment, core complex4210is configured to execute main control software associated with APU4200, such as an operating system. In at least one embodiment, core complex4210is the master processor of APU4200, controlling and coordinating operations of other processors. In at least one embodiment, core complex4210issues commands that control the operation of graphics complex4240. In at least one embodiment, core complex4210can be configured to execute host executable code derived from CUDA source code, and graphics complex4240can be configured to execute device executable code derived from CUDA source code.

In at least one embodiment, core complex4210includes, without limitation, cores4220(1)-4220(4) and an L3 cache4230. In at least one embodiment, core complex4210may include, without limitation, any number of cores4220and any number and type of caches in any combination. In at least one embodiment, cores4220are configured to execute instructions of a particular instruction set architecture (“ISA”). In at least one embodiment, each core4220is a CPU core.

In at least one embodiment, each core4220includes, without limitation, a fetch/decode unit4222, an integer execution engine4224, a floating point execution engine4226, and an L2 cache4228. In at least one embodiment, fetch/decode unit4222fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate micro-instructions to integer execution engine4224and floating point execution engine4226. In at least one embodiment, fetch/decode unit4222can concurrently dispatch one micro-instruction to integer execution engine4224and another micro-instruction to floating point execution engine4226. In at least one embodiment, integer execution engine4224executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine4226executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit4222dispatches micro-instructions to a single execution engine that replaces both integer execution engine4224and floating point execution engine4226.

In at least one embodiment, each core4220(i), where i is an integer representing a particular instance of core4220, may access L2 cache4228(i) included in core4220(i). In at least one embodiment, each core4220included in core complex4210(j), where j is an integer representing a particular instance of core complex4210, is connected to other cores4220included in core complex4210(j) via L3 cache4230(j) included in core complex4210(j). In at least one embodiment, cores4220included in core complex4210(j), where j is an integer representing a particular instance of core complex4210, can access all of L3 cache4230(j) included in core complex4210(j). In at least one embodiment, L3 cache4230may include, without limitation, any number of slices.

In at least one embodiment, graphics complex4240can be configured to perform compute operations in a highly-parallel fashion. In at least one embodiment, graphics complex4240is configured to execute graphics pipeline operations such as draw commands, pixel operations, geometric computations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex4240is configured to execute operations unrelated to graphics. In at least one embodiment, graphics complex4240is configured to execute both operations related to graphics and operations unrelated to graphics.

In at least one embodiment, graphics complex4240includes, without limitation, any number of compute units4250and an L2 cache4242. In at least one embodiment, compute units4250share L2 cache4242. In at least one embodiment, L2 cache4242is partitioned. In at least one embodiment, graphics complex4240includes, without limitation, any number of compute units4250and any number (including zero) and type of caches. In at least one embodiment, graphics complex4240includes, without limitation, any amount of dedicated graphics hardware.

In at least one embodiment, each compute unit4250includes, without limitation, any number of SIMD units4252and a shared memory4254. In at least one embodiment, each SIMD unit4252implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit4250may execute any number of thread blocks, but each thread block executes on a single compute unit4250. In at least one embodiment, a thread block includes, without limitation, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit4252executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize together and communicate via shared memory4254.

In at least one embodiment, fabric4260is a system interconnect that facilitates data and control transmissions across core complex4210, graphics complex4240, I/O interfaces4270, memory controllers4280, display controller4292, and multimedia engine4294. In at least one embodiment, APU4200may include, without limitation, any amount and type of system interconnect in addition to or instead of fabric4260that facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be internal or external to APU4200. In at least one embodiment, I/O interfaces4270are representative of any number and type of I/O interfaces (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I/O interfaces4270In at least one embodiment, peripheral devices that are coupled to I/O interfaces4270may include, without limitation, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, and so forth.

In at least one embodiment, display controller AMD92 displays images on one or more display device(s), such as a liquid crystal display (“LCD”) device. In at least one embodiment, multimedia engine4294includes, without limitation, any amount and type of circuitry that is related to multimedia, such as a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, memory controllers4280facilitate data transfers between APU4200and a unified system memory4290. In at least one embodiment, core complex4210and graphics complex4240share unified system memory4290.

In at least one embodiment, APU4200implements a memory subsystem that includes, without limitation, any amount and type of memory controllers4280and memory devices (e.g., shared memory4254) that may be dedicated to one component or shared among multiple components. In at least one embodiment, APU4200implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 caches4328, L3 cache4230, and L2 cache4242) that may each be private to or shared between any number of components (e.g., cores4220, core complex4210, SIMD units4252, compute units4250, and graphics complex4240).

In at least one embodiment, at least one element of core complex4210or graphics complex4240is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.43illustrates a CPU4300, in accordance with at least one embodiment. In at least one embodiment, CPU4300is developed by AMD Corporation of Santa Clara, CA. In at least one embodiment, CPU4300can be configured to execute an application program. In at least one embodiment, CPU4300is configured to execute main control software, such as an operating system. In at least one embodiment, CPU4300issues commands that control the operation of an external GPU (not shown). In at least one embodiment, CPU4300can be configured to execute host executable code derived from CUDA source code, and an external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, CPU4300includes, without limitation, any number of core complexes4310, fabric4360, I/O interfaces4370, and memory controllers4380.

In at least one embodiment, core complex4310includes, without limitation, cores4320(1)-4320(4) and an L3 cache4330. In at least one embodiment, core complex4310may include, without limitation, any number of cores4320and any number and type of caches in any combination. In at least one embodiment, cores4320are configured to execute instructions of a particular ISA. In at least one embodiment, each core4320is a CPU core.

In at least one embodiment, each core4320includes, without limitation, a fetch/decode unit4322, an integer execution engine4324, a floating point execution engine4326, and an L2 cache4328. In at least one embodiment, fetch/decode unit4322fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate micro-instructions to integer execution engine4324and floating point execution engine4326. In at least one embodiment, fetch/decode unit4322can concurrently dispatch one micro-instruction to integer execution engine4324and another micro-instruction to floating point execution engine4326. In at least one embodiment, integer execution engine4324executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine4326executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit4322dispatches micro-instructions to a single execution engine that replaces both integer execution engine4324and floating point execution engine4326.

In at least one embodiment, each core4320(i), where i is an integer representing a particular instance of core4320, may access L2 cache4328(i) included in core4320(i). In at least one embodiment, each core4320included in core complex4310(j), where j is an integer representing a particular instance of core complex4310, is connected to other cores4320in core complex4310(j) via L3 cache4330(j) included in core complex4310(j). In at least one embodiment, cores4320included in core complex4310(j), where j is an integer representing a particular instance of core complex4310, can access all of L3 cache4330(j) included in core complex4310(j). In at least one embodiment, L3 cache4330may include, without limitation, any number of slices.

In at least one embodiment, fabric4360is a system interconnect that facilitates data and control transmissions across core complexes4310(1)-4310(N) (where N is an integer greater than zero), I/O interfaces4370, and memory controllers4380. In at least one embodiment, CPU4300may include, without limitation, any amount and type of system interconnect in addition to or instead of fabric4360that facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be internal or external to CPU4300. In at least one embodiment, I/O interfaces4370are representative of any number and type of I/O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I/O interfaces4370In at least one embodiment, peripheral devices that are coupled to I/O interfaces4370may include, without limitation, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, and so forth.

In at least one embodiment, memory controllers4380facilitate data transfers between CPU4300and a system memory4390. In at least one embodiment, core complex4310and graphics complex4340share system memory4390. In at least one embodiment, CPU4300implements a memory subsystem that includes, without limitation, any amount and type of memory controllers4380and memory devices that may be dedicated to one component or shared among multiple components. In at least one embodiment, CPU4300implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 caches4328and L3 caches4330) that may each be private to or shared between any number of components (e.g., cores4320and core complexes4310).

In at least one embodiment, at least one element of core complex4310(1)-4310(n) is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.44illustrates an exemplary accelerator integration slice4490, in accordance with at least one embodiment. As used herein, a “slice” comprises a specified portion of processing resources of an accelerator integration circuit. In at least one embodiment, the accelerator integration circuit provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines included in a graphics acceleration module. The graphics processing engines may each comprise a separate GPU. Alternatively, the graphics processing engines may comprise different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoders/decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module may be a GPU with multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

An application effective address space4482within system memory4414stores process elements4483. In one embodiment, process elements4483are stored in response to GPU invocations4481from applications4480executed on processor4407. A process element4483contains process state for corresponding application4480. A work descriptor (“WD”)4484contained in process element4483can be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, WD4484is a pointer to a job request queue in application effective address space4482.

Graphics acceleration module4446and/or individual graphics processing engines can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting up process state and sending WD4484to graphics acceleration module4446to start a job in a virtualized environment may be included.

In at least one embodiment, a dedicated-process programming model is implementation-specific. In this model, a single process owns graphics acceleration module4446or an individual graphics processing engine. Because graphics acceleration module4446is owned by a single process, a hypervisor initializes an accelerator integration circuit for an owning partition and an operating system initializes accelerator integration circuit for an owning process when graphics acceleration module4446is assigned.

In operation, a WD fetch unit4491in accelerator integration slice4490fetches next WD4484which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module4446. Data from WD4484may be stored in registers4445and used by a memory management unit (“MMU”)4439, interrupt management circuit4447and/or context management circuit4448as illustrated. For example, one embodiment of MMU4439includes segment/page walk circuitry for accessing segment/page tables4486within OS virtual address space4485. Interrupt management circuit4447may process interrupt events (“INT”)4492received from graphics acceleration module4446. When performing graphics operations, an effective address4493generated by a graphics processing engine is translated to a real address by MMU4439.

In one embodiment, a same set of registers4445are duplicated for each graphics processing engine and/or graphics acceleration module4446and may be initialized by a hypervisor or operating system. Each of these duplicated registers may be included in accelerator integration slice4490. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

TABLE 1Hypervisor Initialized Registers1Slice Control Register2Real Address (RA) Scheduled Processes Area Pointer3Authority Mask Override Register4Interrupt Vector Table Entry Offset5Interrupt Vector Table Entry Limit6State Register7Logical Partition ID8Real address (RA) Hypervisor Accelerator Utilization RecordPointer9Storage Description Register

Exemplary registers that may be initialized by an operating system are shown in Table 2.

TABLE 2Operating System Initialized Registers1Process and Thread Identification2Effective Address (EA) Context Save/Restore Pointer3Virtual Address (VA) Accelerator Utilization Record Pointer4Virtual Address (VA) Storage Segment Table Pointer5Authority Mask6Work descriptor

In one embodiment, each WD4484is specific to a particular graphics acceleration module4446and/or a particular graphics processing engine. It contains all information required by a graphics processing engine to do work or it can be a pointer to a memory location where an application has set up a command queue of work to be completed.

In at least one embodiment, at least one component shown or described with respect toFIG.44is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, processor4407is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, processor4407is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, processor4407is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, processor4407is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, processor4407is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, processor4407is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, processor4407is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, processor4407is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, processor4407is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, processor4407is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, processor4407is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, processor4407is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, processor4407is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, processor4407is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIGS.45A-45Billustrate exemplary graphics processors, in accordance with at least one embodiment. In at least one embodiment, any of the exemplary graphics processors may be fabricated using one or more IP cores. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processors are for use within an SoC.

FIG.45Aillustrates an exemplary graphics processor4510of an SoC integrated circuit that may be fabricated using one or more IP cores, in accordance with at least one embodiment.FIG.45Billustrates an additional exemplary graphics processor4540of an SoC integrated circuit that may be fabricated using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, graphics processor4510ofFIG.45Ais a low power graphics processor core. In at least one embodiment, graphics processor4540ofFIG.45Bis a higher performance graphics processor core. In at least one embodiment, each of graphics processors4510,4540can be variants of graphics processor4010ofFIG.40.

In at least one embodiment, graphics processor4510includes a vertex processor4505and one or more fragment processor(s)4515A-4515N (e.g.,4515A,4515B,4515C,4515D, through4515N−1, and4515N). In at least one embodiment, graphics processor4510can execute different shader programs via separate logic, such that vertex processor4505is optimized to execute operations for vertex shader programs, while one or more fragment processor(s)4515A-4515N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor4505performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s)4515A-4515N use primitive and vertex data generated by vertex processor4505to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s)4515A-4515N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API.

In at least one embodiment, graphics processor4510additionally includes one or more MMU(s)4520A-4520B, cache(s)4525A-4525B, and circuit interconnect(s)4530A-4530B. In at least one embodiment, one or more MMU(s)4520A-4520B provide for virtual to physical address mapping for graphics processor4510, including for vertex processor4505and/or fragment processor(s)4515A-4515N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in one or more cache(s)4525A-4525B. In at least one embodiment, one or more MMU(s)4520A-4520B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s)4005, image processors4015, and/or video processors4020ofFIG.40, such that each processor4005-4020can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s)4530A-4530B enable graphics processor4510to interface with other IP cores within an SoC, either via an internal bus of the SoC or via a direct connection.

In at least one embodiment, graphics processor4540includes one or more MMU(s)4520A-4520B, caches4525A-4525B, and circuit interconnects4530A-4530B of graphics processor4510ofFIG.45A. In at least one embodiment, graphics processor4540includes one or more shader core(s)4555A-4555N (e.g.,4555A,4555B,4555C,4555D,4555E,4555F, through4555N−1, and4555N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor4540includes an inter-core task manager4545, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores4555A-4555N and a tiling unit4558to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

In at least one embodiment, at least one of graphics processor4510or graphics processor4540is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.46Aillustrates a graphics core4600, in accordance with at least one embodiment. In at least one embodiment, graphics core4600may be included within graphics processor4010ofFIG.40. In at least one embodiment, graphics core4600may be a unified shader core4555A-4555N as inFIG.45B. In at least one embodiment, graphics core4600includes a shared instruction cache4602, a texture unit4618, and a cache/shared memory4620that are common to execution resources within graphics core4600. In at least one embodiment, graphics core4600can include multiple slices4601A-4601N or partition for each core, and a graphics processor can include multiple instances of graphics core4600. Slices4601A-4601N can include support logic including a local instruction cache4604A-4604N, a thread scheduler4606A-4606N, a thread dispatcher4608A-4608N, and a set of registers4610A-4610N. In at least one embodiment, slices4601A-4601N can include a set of additional function units (“AFUs”)4612A-4612N, floating-point units (“FPUs”)4614A-4614N, integer arithmetic logic units (“ALUs”)4616-4616N, address computational units (“ACUs”)4613A-4613N, double-precision floating-point units (“DPFPUs”)4615A-4615N, and matrix processing units (“MPUs”)4617A-4617N.

In at least one embodiment, FPUs4614A-4614N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while DPFPUs4615A-4615N perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs4616A-4616N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs4617A-4617N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs4617-4617N can perform a variety of matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix to matrix multiplication (“GEMM”). In at least one embodiment, AFUs4612A-4612N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

In at least one embodiment, at least one component shown or described with respect toFIG.46Ais used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, graphics core4600is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, graphics core4600is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, graphics core4600is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, graphics core4600is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, graphics core4600is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, graphics core4600is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, graphics core4600is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, graphics core4600is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, graphics core4600is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, graphics core4600is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, graphics core4600is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, graphics core4600is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, graphics core4600is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, graphics core4600is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.46Billustrates a general-purpose graphics processing unit (“GPGPU”)4630, in accordance with at least one embodiment. In at least one embodiment, GPGPU4630is highly-parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU4630can be configured to enable highly-parallel compute operations to be performed by an array of GPUs. In at least one embodiment, GPGPU4630can be linked directly to other instances of GPGPU4630to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU4630includes a host interface4632to enable a connection with a host processor. In at least one embodiment, host interface4632is a PCIe interface. In at least one embodiment, host interface4632can be a vendor specific communications interface or communications fabric. In at least one embodiment, GPGPU4630receives commands from a host processor and uses a global scheduler4634to distribute execution threads associated with those commands to a set of compute clusters4636A-4636H. In at least one embodiment, compute clusters4636A-4636H share a cache memory4638. In at least one embodiment, cache memory4638can serve as a higher-level cache for cache memories within compute clusters4636A-4636H.

In at least one embodiment, GPGPU4630includes memory4644A-4644B coupled with compute clusters4636A-4636H via a set of memory controllers4642A-4642B. In at least one embodiment, memory4644A-4644B can include various types of memory devices including DRAM or graphics random access memory, such as synchronous graphics random access memory (“SGRAM”), including graphics double data rate (“GDDR”) memory.

In at least one embodiment, compute clusters4636A-4636H each include a set of graphics cores, such as graphics core4600ofFIG.46A, which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for computations associated with CUDA programs. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters4636A-4636H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations.

In at least one embodiment, multiple instances of GPGPU4630can be configured to operate as a compute cluster. Compute clusters4636A-4636H may implement any technically feasible communication techniques for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU4630communicate over host interface4632. In at least one embodiment, GPGPU4630includes an I/O hub4639that couples GPGPU4630with a GPU link4640that enables a direct connection to other instances of GPGPU4630. In at least one embodiment, GPU link4640is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU4630. In at least one embodiment GPU link4640couples with a high speed interconnect to transmit and receive data to other GPGPUs4630or parallel processors. In at least one embodiment, multiple instances of GPGPU4630are located in separate data processing systems and communicate via a network device that is accessible via host interface4632. In at least one embodiment GPU link4640can be configured to enable a connection to a host processor in addition to or as an alternative to host interface4632. In at least one embodiment, GPGPU4630can be configured to execute a CUDA program.

In at least one embodiment, at least one component shown or described with respect toFIG.46Bis used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, GPGPU4630is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, GPGPU4630is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, GPGPU4630is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, GPGPU4630is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, GPGPU4630is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, GPGPU4630is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, GPGPU4630is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, GPGPU4630is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, GPGPU4630is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, GPGPU4630is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, GPGPU4630is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, GPGPU4630is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, GPGPU4630is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, GPGPU4630is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.47Aillustrates a parallel processor4700, in accordance with at least one embodiment. In at least one embodiment, various components of parallel processor4700may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (“ASICs”), or FPGAs.

In at least one embodiment, parallel processor4700includes a parallel processing unit4702. In at least one embodiment, parallel processing unit4702includes an I/O unit4704that enables communication with other devices, including other instances of parallel processing unit4702. In at least one embodiment, I/O unit4704may be directly connected to other devices. In at least one embodiment, I/O unit4704connects with other devices via use of a hub or switch interface, such as memory hub4705. In at least one embodiment, connections between memory hub4705and I/O unit4704form a communication link. In at least one embodiment, I/O unit4704connects with a host interface4706and a memory crossbar4716, where host interface4706receives commands directed to performing processing operations and memory crossbar4716receives commands directed to performing memory operations.

In at least one embodiment, when host interface4706receives a command buffer via I/O unit4704, host interface4706can direct work operations to perform those commands to a front end4708. In at least one embodiment, front end4708couples with a scheduler4710, which is configured to distribute commands or other work items to a processing array4712. In at least one embodiment, scheduler4710ensures that processing array4712is properly configured and in a valid state before tasks are distributed to processing array4712. In at least one embodiment, scheduler4710is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller implemented scheduler4710is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on processing array4712. In at least one embodiment, host software can prove workloads for scheduling on processing array4712via one of multiple graphics processing doorbells. In at least one embodiment, workloads can then be automatically distributed across processing array4712by scheduler4710logic within a microcontroller including scheduler4710.

In at least one embodiment, processing array4712can include up to “N” clusters (e.g., cluster4714A, cluster4714B, through cluster4714N). In at least one embodiment, each cluster4714A-4714N of processing array4712can execute a large number of concurrent threads. In at least one embodiment, scheduler4710can allocate work to clusters4714A-4714N of processing array4712using various scheduling and/or work distribution algorithms, which may vary depending on the workload arising for each type of program or computation. In at least one embodiment, scheduling can be handled dynamically by scheduler4710, or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing array4712. In at least one embodiment, different clusters4714A-4714N of processing array4712can be allocated for processing different types of programs or for performing different types of computations.

In at least one embodiment, processing array4712can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array4712is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing array4712can include logic to execute processing tasks including filtering of video and/or audio data, performing modeling operations, including physics operations, and performing data transformations.

In at least one embodiment, processing array4712is configured to perform parallel graphics processing operations. In at least one embodiment, processing array4712can include additional logic to support execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array4712can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit4702can transfer data from system memory via I/O unit4704for processing. In at least one embodiment, during processing, transferred data can be stored to on-chip memory (e.g., a parallel processor memory4722) during processing, then written back to system memory.

In at least one embodiment, when parallel processing unit4702is used to perform graphics processing, scheduler4710can be configured to divide a processing workload into approximately equal sized tasks, to better enable distribution of graphics processing operations to multiple clusters4714A-4714N of processing array4712. In at least one embodiment, portions of processing array4712can be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters4714A-4714N may be stored in buffers to allow intermediate data to be transmitted between clusters4714A-4714N for further processing.

In at least one embodiment, processing array4712can receive processing tasks to be executed via scheduler4710, which receives commands defining processing tasks from front end4708. In at least one embodiment, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler4710may be configured to fetch indices corresponding to tasks or may receive indices from front end4708. In at least one embodiment, front end4708can be configured to ensure processing array4712is configured to a valid state before a workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated.

In at least one embodiment, each of one or more instances of parallel processing unit4702can couple with parallel processor memory4722. In at least one embodiment, parallel processor memory4722can be accessed via memory crossbar4716, which can receive memory requests from processing array4712as well as I/O unit4704. In at least one embodiment, memory crossbar4716can access parallel processor memory4722via a memory interface4718. In at least one embodiment, memory interface4718can include multiple partition units (e.g., a partition unit4720A, partition unit4720B, through partition unit4720N) that can each couple to a portion (e.g., memory unit) of parallel processor memory4722. In at least one embodiment, a number of partition units4720A-4720N is configured to be equal to a number of memory units, such that a first partition unit4720A has a corresponding first memory unit4724A, a second partition unit4720B has a corresponding memory unit4724B, and an Nth partition unit4720N has a corresponding Nth memory unit4724N. In at least one embodiment, a number of partition units4720A-4720N may not be equal to a number of memory devices.

In at least one embodiment, memory units4724A-4724N can include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM, including GDDR memory. In at least one embodiment, memory units4724A-4724N may also include 3D stacked memory, including but not limited to high bandwidth memory (“HBM”). In at least one embodiment, render targets, such as frame buffers or texture maps may be stored across memory units4724A-4724N, allowing partition units4720A-4720N to write portions of each render target in parallel to efficiently use available bandwidth of parallel processor memory4722. In at least one embodiment, a local instance of parallel processor memory4722may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

In at least one embodiment, any one of clusters4714A-4714N of processing array4712can process data that will be written to any of memory units4724A-4724N within parallel processor memory4722. In at least one embodiment, memory crossbar4716can be configured to transfer an output of each cluster4714A-4714N to any partition unit4720A-4720N or to another cluster4714A-4714N, which can perform additional processing operations on an output. In at least one embodiment, each cluster4714A-4714N can communicate with memory interface4718through memory crossbar4716to read from or write to various external memory devices. In at least one embodiment, memory crossbar4716has a connection to memory interface4718to communicate with I/O unit4704, as well as a connection to a local instance of parallel processor memory4722, enabling processing units within different clusters4714A-4714N to communicate with system memory or other memory that is not local to parallel processing unit4702. In at least one embodiment, memory crossbar4716can use virtual channels to separate traffic streams between clusters4714A-4714N and partition units4720A-4720N.

In at least one embodiment, multiple instances of parallel processing unit4702can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit4702can be configured to inter-operate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and/or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit4702can include higher precision floating point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit4702or parallel processor4700can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and/or embedded systems.

In at least one embodiment, at least one component shown or described with respect toFIG.47Ais used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, parallel processor4700is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, parallel processor4700is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, parallel processor4700is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, parallel processor4700is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, parallel processor4700is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, parallel processor4700is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, parallel processor4700is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, parallel processor4700is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, parallel processor4700is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, parallel processor4700is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, parallel processor4700is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, parallel processor4700is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, parallel processor4700is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, parallel processor4700is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.47Billustrates a processing cluster4794, in accordance with at least one embodiment. In at least one embodiment, processing cluster4794is included within a parallel processing unit. In at least one embodiment, processing cluster4794is one of processing clusters4714A-4714N ofFIG.47. In at least one embodiment, processing cluster4794can be configured to execute many threads in parallel, where the term “thread” refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single instruction, multiple data (“SIMD”) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction, multiple thread (“SIMT”) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster4794.

In at least one embodiment, operation of processing cluster4794can be controlled via a pipeline manager4732that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager4732receives instructions from scheduler4710ofFIG.47and manages execution of those instructions via a graphics multiprocessor4734and/or a texture unit4736. In at least one embodiment, graphics multiprocessor4734is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures may be included within processing cluster4794. In at least one embodiment, one or more instances of graphics multiprocessor4734can be included within processing cluster4794. In at least one embodiment, graphics multiprocessor4734can process data and a data crossbar4740can be used to distribute processed data to one of multiple possible destinations, including other shader units. In at least one embodiment, pipeline manager4732can facilitate distribution of processed data by specifying destinations for processed data to be distributed via data crossbar4740.

In at least one embodiment, each graphics multiprocessor4734within processing cluster4794can include an identical set of functional execution logic (e.g., arithmetic logic units, load/store units (“LSUs”), etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. In at least one embodiment, same functional-unit hardware can be leveraged to perform different operations and any combination of functional units may be present.

In at least one embodiment, instructions transmitted to processing cluster4794constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor4734. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor4734. In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of the processing engines may be idle during cycles in which that thread group is being processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor4734. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor4734, processing can be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor4734.

In at least one embodiment, graphics multiprocessor4734includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor4734can forego an internal cache and use a cache memory (e.g., L1 cache4748) within processing cluster4794. In at least one embodiment, each graphics multiprocessor4734also has access to Level 2 (“L2”) caches within partition units (e.g., partition units4720A-4720N ofFIG.47A) that are shared among all processing clusters4794and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor4734may also access off-chip global memory, which can include one or more of local parallel processor memory and/or system memory. In at least one embodiment, any memory external to parallel processing unit4702may be used as global memory. In at least one embodiment, processing cluster4794includes multiple instances of graphics multiprocessor4734that can share common instructions and data, which may be stored in L1 cache4748.

In at least one embodiment, each processing cluster4794may include an MMU4745that is configured to map virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMU4745may reside within memory interface4718ofFIG.47. In at least one embodiment, MMU4745includes a set of page table entries (“PTEs”) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, MMU4745may include address translation lookaside buffers (“TLBs”) or caches that may reside within graphics multiprocessor4734or L1 cache4748or processing cluster4794. In at least one embodiment, a physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss.

In at least one embodiment, processing cluster4794may be configured such that each graphics multiprocessor4734is coupled to a texture unit4736for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor4734and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor4734outputs a processed task to data crossbar4740to provide the processed task to another processing cluster4794for further processing or to store the processed task in an L2 cache, a local parallel processor memory, or a system memory via memory crossbar4716. In at least one embodiment, a pre-raster operations unit (“preROP”)4742is configured to receive data from graphics multiprocessor4734, direct data to ROP units, which may be located with partition units as described herein (e.g., partition units4720A-4720N ofFIG.47). In at least one embodiment, PreROP4742can perform optimizations for color blending, organize pixel color data, and perform address translations.

In at least one embodiment, at least one component shown or described with respect toFIG.47Bis used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, graphics multiprocessor4734is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, graphics multiprocessor4734is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.47Cillustrates a graphics multiprocessor4796, in accordance with at least one embodiment. In at least one embodiment, graphics multiprocessor4796is graphics multiprocessor4734ofFIG.47B. In at least one embodiment, graphics multiprocessor4796couples with pipeline manager4732of processing cluster4794. In at least one embodiment, graphics multiprocessor4796has an execution pipeline including but not limited to an instruction cache4752, an instruction unit4754, an address mapping unit4756, a register file4758, one or more GPGPU cores4762, and one or more LSUs4766. GPGPU cores4762and LSUs4766are coupled with cache memory4772and shared memory4770via a memory and cache interconnect4768.

In at least one embodiment, instruction cache4752receives a stream of instructions to execute from pipeline manager4732. In at least one embodiment, instructions are cached in instruction cache4752and dispatched for execution by instruction unit4754. In at least one embodiment, instruction unit4754can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core4762. In at least one embodiment, an instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit4756can be used to translate addresses in a unified address space into a distinct memory address that can be accessed by LSUs4766.

In at least one embodiment, register file4758provides a set of registers for functional units of graphics multiprocessor4796. In at least one embodiment, register file4758provides temporary storage for operands connected to data paths of functional units (e.g., GPGPU cores4762, LSUs4766) of graphics multiprocessor4796. In at least one embodiment, register file4758is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file4758. In at least one embodiment, register file4758is divided between different thread groups being executed by graphics multiprocessor4796.

In at least one embodiment, GPGPU cores4762can each include FPUs and/or integer ALUs that are used to execute instructions of graphics multiprocessor4796. GPGPU cores4762can be similar in architecture or can differ in architecture. In at least one embodiment, a first portion of GPGPU cores4762include a single precision FPU and an integer ALU while a second portion of GPGPU cores4762include a double precision FPU. In at least one embodiment, FPUs can implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor4796can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment one or more of GPGPU cores4762can also include fixed or special function logic.

In at least one embodiment, GPGPU cores4762include SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment GPGPU cores4762can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores4762can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (“SPMD”) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for an SIMT execution model can executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

In at least one embodiment, memory and cache interconnect4768is an interconnect network that connects each functional unit of graphics multiprocessor4796to register file4758and to shared memory4770. In at least one embodiment, memory and cache interconnect4768is a crossbar interconnect that allows LSU4766to implement load and store operations between shared memory4770and register file4758. In at least one embodiment, register file4758can operate at a same frequency as GPGPU cores4762, thus data transfer between GPGPU cores4762and register file4758is very low latency. In at least one embodiment, shared memory4770can be used to enable communication between threads that execute on functional units within graphics multiprocessor4796. In at least one embodiment, cache memory4772can be used as a data cache for example, to cache texture data communicated between functional units and texture unit4736. In at least one embodiment, shared memory4770can also be used as a program managed cached. In at least one embodiment, threads executing on GPGPU cores4762can programmatically store data within shared memory in addition to automatically cached data that is stored within cache memory4772.

In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host/processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to host processor/cores over a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, a GPU may be integrated on the same package or chip as cores and communicatively coupled to cores over a processor bus/interconnect that is internal to a package or a chip. In at least one embodiment, regardless of the manner in which a GPU is connected, processor cores may allocate work to the GPU in the form of sequences of commands/instructions contained in a WD. In at least one embodiment, the GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions.

In at least one embodiment, at least one component shown or described with respect toFIG.47Cis used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, graphics multiprocessor4796is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, graphics multiprocessor4796is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.48illustrates a graphics processor4800, in accordance with at least one embodiment. In at least one embodiment, graphics processor4800includes a ring interconnect4802, a pipeline front-end4804, a media engine4837, and graphics cores4880A-4880N. In at least one embodiment, ring interconnect4802couples graphics processor4800to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor4800is one of many processors integrated within a multi-core processing system.

In at least one embodiment, graphics processor4800receives batches of commands via ring interconnect4802. In at least one embodiment, incoming commands are interpreted by a command streamer4803in pipeline front-end4804. In at least one embodiment, graphics processor4800includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s)4880A-4880N. In at least one embodiment, for 3D geometry processing commands, command streamer4803supplies commands to geometry pipeline4836. In at least one embodiment, for at least some media processing commands, command streamer4803supplies commands to a video front end4834, which couples with a media engine4837. In at least one embodiment, media engine4837includes a Video Quality Engine (“VQE”)4830for video and image post-processing and a multi-format encode/decode (“MFX”) engine4833to provide hardware-accelerated media data encode and decode. In at least one embodiment, geometry pipeline4836and media engine4837each generate execution threads for thread execution resources provided by at least one graphics core4880A.

In at least one embodiment, graphics processor4800includes scalable thread execution resources featuring modular graphics cores4880A-4880N (sometimes referred to as core slices), each having multiple sub-cores4850A-550N,4860A-4860N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor4800can have any number of graphics cores4880A through4880N. In at least one embodiment, graphics processor4800includes a graphics core4880A having at least a first sub-core4850A and a second sub-core4860A. In at least one embodiment, graphics processor4800is a low power processor with a single sub-core (e.g., sub-core4850A). In at least one embodiment, graphics processor4800includes multiple graphics cores4880A-4880N, each including a set of first sub-cores4850A-4850N and a set of second sub-cores4860A-4860N. In at least one embodiment, each sub-core in first sub-cores4850A-4850N includes at least a first set of execution units (“EUs”)4852A-4852N and media/texture samplers4854A-4854N. In at least one embodiment, each sub-core in second sub-cores4860A-4860N includes at least a second set of execution units4862A-4862N and samplers4864A-4864N. In at least one embodiment, each sub-core4850A-4850N,4860A-4860N shares a set of shared resources4870A-4870N. In at least one embodiment, shared resources4870include shared cache memory and pixel operation logic.

In at least one embodiment, at least one component shown or described with respect toFIG.48is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, graphics processor4800is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, graphics processor4800is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, graphics processor4800is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, graphics processor4800is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, graphics processor4800is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, graphics processor4800is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, graphics processor4800is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, graphics processor4800is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, graphics processor4800is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, graphics processor4800is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, graphics processor4800is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, graphics processor4800is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, graphics processor4800is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, graphics processor4800is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.49illustrates a processor4900, in accordance with at least one embodiment. In at least one embodiment, processor4900may include, without limitation, logic circuits to perform instructions. In at least one embodiment, processor4900may perform instructions, including x86 instructions, ARM instructions, specialized instructions for ASICs, etc. In at least one embodiment, processor4910may include registers to store packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif In at least one embodiment, MMX registers, available in both integer and floating point forms, may operate with packed data elements that accompany SIMD and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, AVX, or beyond (referred to generically as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processors4910may perform instructions to accelerate CUDA programs.

In at least one embodiment, processor4900includes an in-order front end (“front end”)4901to fetch instructions to be executed and prepare instructions to be used later in processor pipeline. In at least one embodiment, front end4901may include several units. In at least one embodiment, an instruction prefetcher4926fetches instructions from memory and feeds instructions to an instruction decoder4928which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder4928decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called “micro ops” or “uops”) for execution. In at least one embodiment, instruction decoder4928parses instruction into an opcode and corresponding data and control fields that may be used by micro-architecture to perform operations. In at least one embodiment, a trace cache4930may assemble decoded uops into program ordered sequences or traces in a uop queue4934for execution. In at least one embodiment, when trace cache4930encounters a complex instruction, a microcode ROM4932provides uops needed to complete an operation.

In at least one embodiment, some instructions may be converted into a single micro-op, whereas others need several micro-ops to complete full operation. In at least one embodiment, if more than four micro-ops are needed to complete an instruction, instruction decoder4928may access microcode ROM4932to perform instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder4928. In at least one embodiment, an instruction may be stored within microcode ROM4932should a number of micro-ops be needed to accomplish operation. In at least one embodiment, trace cache4930refers to an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM4932. In at least one embodiment, after microcode ROM4932finishes sequencing micro-ops for an instruction, front end4901of machine may resume fetching micro-ops from trace cache4930.

In at least one embodiment, out-of-order execution engine (“out of order engine”)4903may prepare instructions for execution. In at least one embodiment, out-of-order execution logic has a number of buffers to smooth out and re-order the flow of instructions to optimize performance as they go down a pipeline and get scheduled for execution. Out-of-order execution engine4903includes, without limitation, an allocator/register renamer4940, a memory uop queue4942, an integer/floating point uop queue4944, a memory scheduler4946, a fast scheduler4902, a slow/general floating point scheduler (“slow/general FP scheduler”)4904, and a simple floating point scheduler (“simple FP scheduler”)4906. In at least one embodiment, fast schedule4902, slow/general floating point scheduler4904, and simple floating point scheduler4906are also collectively referred to herein as “uop schedulers4902,4904,4906.” Allocator/register renamer4940allocates machine buffers and resources that each uop needs in order to execute. In at least one embodiment, allocator/register renamer4940renames logic registers onto entries in a register file. In at least one embodiment, allocator/register renamer4940also allocates an entry for each uop in one of two uop queues, memory uop queue4942for memory operations and integer/floating point uop queue4944for non-memory operations, in front of memory scheduler4946and uop schedulers4902,4904,4906. In at least one embodiment, uop schedulers4902,4904,4906, determine when a uop is ready to execute based on readiness of their dependent input register operand sources and availability of execution resources uops need to complete their operation. In at least one embodiment, fast scheduler4902of at least one embodiment may schedule on each half of main clock cycle while slow/general floating point scheduler4904and simple floating point scheduler4906may schedule once per main processor clock cycle. In at least one embodiment, uop schedulers4902,4904,4906arbitrate for dispatch ports to schedule uops for execution.

In at least one embodiment, execution block4911includes, without limitation, an integer register file/bypass network4908, a floating point register file/bypass network (“FP register file/bypass network”)4910, address generation units (“AGUs”)4912and4914, fast ALUs4916and4918, a slow ALU4920, a floating point ALU (“FP”)4922, and a floating point move unit (“FP move”)4924. In at least one embodiment, integer register file/bypass network4908and floating point register file/bypass network4910are also referred to herein as “register files4908,4910.” In at least one embodiment, AGUSs4912and4914, fast ALUs4916and4918, slow ALU4920, floating point ALU4922, and floating point move unit4924are also referred to herein as “execution units4912,4914,4916,4918,4920,4922, and4924.” In at least one embodiment, an execution block may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units, in any combination.

In at least one embodiment, register files4908,4910may be arranged between uop schedulers4902,4904,4906, and execution units4912,4914,4916,4918,4920,4922, and4924. In at least one embodiment, integer register file/bypass network4908performs integer operations. In at least one embodiment, floating point register file/bypass network4910performs floating point operations. In at least one embodiment, each of register files4908,4910may include, without limitation, a bypass network that may bypass or forward just completed results that have not yet been written into register file to new dependent uops. In at least one embodiment, register files4908,4910may communicate data with each other. In at least one embodiment, integer register file/bypass network4908may include, without limitation, two separate register files, one register file for low-order thirty-two bits of data and a second register file for high order thirty-two bits of data. In at least one embodiment, floating point register file/bypass network4910may include, without limitation, 128-bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.

In at least one embodiment, execution units4912,4914,4916,4918,4920,4922,4924may execute instructions. In at least one embodiment, register files4908,4910store integer and floating point data operand values that micro-instructions need to execute. In at least one embodiment, processor4900may include, without limitation, any number and combination of execution units4912,4914,4916,4918,4920,4922,4924. In at least one embodiment, floating point ALU4922and floating point move unit4924may execute floating point, MMX, SIMD, AVX and SSE, or other operations. In at least one embodiment, floating point ALU4922may include, without limitation, a 64-bit by 64-bit floating point divider to execute divide, square root, and remainder micro ops. In at least one embodiment, instructions involving a floating point value may be handled with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs4916,4918. In at least one embodiment, fast ALUS4916,4918may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU4920as slow ALU4920may include, without limitation, integer execution hardware for long-latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load/store operations may be executed by AGUs4912,4914. In at least one embodiment, fast ALU4916, fast ALU4918, and slow ALU4920may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU4916, fast ALU4918, and slow ALU4920may be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating point ALU4922and floating point move unit4924may be implemented to support a range of operands having bits of various widths. In at least one embodiment, floating point ALU4922and floating point move unit4924may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

In at least one embodiment, uop schedulers4902,4904,4906dispatch dependent operations before parent load has finished executing. In at least one embodiment, as uops may be speculatively scheduled and executed in processor4900, processor4900may also include logic to handle memory misses. In at least one embodiment, if a data load misses in a data cache, there may be dependent operations in flight in pipeline that have left a scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations might need to be replayed and independent ones may be allowed to complete. In at least one embodiment, schedulers and replay mechanisms of at least one embodiment of a processor may also be designed to catch instruction sequences for text string comparison operations.

In at least one embodiment, the term “registers” may refer to on-board processor storage locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside of a processor (from a programmer's perspective). In at least one embodiment, registers might not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packed data.

In at least one embodiment, at least one component shown or described with respect toFIG.49is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, processor4900is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, processor4900is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, processor4900is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, processor4900is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, processor4900is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, processor4900is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, processor4900is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, processor4900is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, processor4900is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, processor4900is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, processor4900is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, processor4900is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, processor4900is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, processor4900is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.50illustrates a processor5000, in accordance with at least one embodiment. In at least one embodiment, processor5000includes, without limitation, one or more processor cores (“cores”)5002A-5002N, an integrated memory controller5014, and an integrated graphics processor5008. In at least one embodiment, processor5000can include additional cores up to and including additional processor core5002N represented by dashed lined boxes. In at least one embodiment, each of processor cores5002A-5002N includes one or more internal cache units5004A-5004N. In at least one embodiment, each processor core also has access to one or more shared cached units5006.

In at least one embodiment, internal cache units5004A-5004N and shared cache units5006represent a cache memory hierarchy within processor5000. In at least one embodiment, cache memory units5004A-5004N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as an L2, L3, Level 4 (“L4”), or other levels of cache, where a highest level of cache before external memory is classified as an LLC. In at least one embodiment, cache coherency logic maintains coherency between various cache units5006and5004A-5004N.

In at least one embodiment, processor5000may also include a set of one or more bus controller units5016and a system agent core5010. In at least one embodiment, one or more bus controller units5016manage a set of peripheral buses, such as one or more PCI or PCI express buses. In at least one embodiment, system agent core5010provides management functionality for various processor components. In at least one embodiment, system agent core5010includes one or more integrated memory controllers5014to manage access to various external memory devices (not shown).

In at least one embodiment, one or more of processor cores5002A-5002N include support for simultaneous multi-threading. In at least one embodiment, system agent core5010includes components for coordinating and operating processor cores5002A-5002N during multi-threaded processing. In at least one embodiment, system agent core5010may additionally include a power control unit (“PCU”), which includes logic and components to regulate one or more power states of processor cores5002A-5002N and graphics processor5008.

In at least one embodiment, processor5000additionally includes graphics processor5008to execute graphics processing operations. In at least one embodiment, graphics processor5008couples with shared cache units5006, and system agent core5010, including one or more integrated memory controllers5014. In at least one embodiment, system agent core5010also includes a display controller5011to drive graphics processor output to one or more coupled displays. In at least one embodiment, display controller5011may also be a separate module coupled with graphics processor5008via at least one interconnect, or may be integrated within graphics processor5008.

In at least one embodiment, a ring based interconnect unit5012is used to couple internal components of processor5000. In at least one embodiment, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques. In at least one embodiment, graphics processor5008couples with ring interconnect5012via an I/O link5013.

In at least one embodiment, I/O link5013represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module5018, such as an eDRAM module. In at least one embodiment, each of processor cores5002A-5002N and graphics processor5008use embedded memory modules5018as a shared LLC.

In at least one embodiment, processor cores5002A-5002N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores5002A-5002N are heterogeneous in terms of ISA, where one or more of processor cores5002A-5002N execute a common instruction set, while one or more other cores of processor cores5002A-50-02N executes a subset of a common instruction set or a different instruction set. In at least one embodiment, processor cores5002A-5002N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more cores having a lower power consumption. In at least one embodiment, processor5000can be implemented on one or more chips or as an SoC integrated circuit.

In at least one embodiment, at least one of processor5000or graphics processor5008is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.51illustrates a graphics processor core5100, in accordance with at least one embodiment described. In at least one embodiment, graphics processor core5100is included within a graphics core array. In at least one embodiment, graphics processor core5100, sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core5100is exemplary of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core5100can include a fixed function block5130coupled with multiple sub-cores5101A-5101F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed function logic.

In at least one embodiment, fixed function block5130includes a geometry/fixed function pipeline5136that can be shared by all sub-cores in graphics processor5100, for example, in lower performance and/or lower power graphics processor implementations. In at least one embodiment, geometry/fixed function pipeline5136includes a 3D fixed function pipeline, a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers.

In at least one embodiment, fixed function block5130also includes a graphics SoC interface5137, a graphics microcontroller5138, and a media pipeline5139. Graphics SoC interface5137provides an interface between graphics core5100and other processor cores within an SoC integrated circuit. In at least one embodiment, graphics microcontroller5138is a programmable sub-processor that is configurable to manage various functions of graphics processor5100, including thread dispatch, scheduling, and pre-emption. In at least one embodiment, media pipeline5139includes logic to facilitate decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline5139implements media operations via requests to compute or sampling logic within sub-cores5101-5101F.

In at least one embodiment, SoC interface5137enables graphics core5100to communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within an SoC, including memory hierarchy elements such as a shared LLC memory, system RAM, and/or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface5137can also enable communication with fixed function devices within an SoC, such as camera imaging pipelines, and enables use of and/or implements global memory atomics that may be shared between graphics core5100and CPUs within an SoC. In at least one embodiment, SoC interface5137can also implement power management controls for graphics core5100and enable an interface between a clock domain of graphic core5100and other clock domains within an SoC. In at least one embodiment, SoC interface5137enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. In at least one embodiment, commands and instructions can be dispatched to media pipeline5139, when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline5136, geometry and fixed function pipeline5114) when graphics processing operations are to be performed.

In at least one embodiment, graphics microcontroller5138can be configured to perform various scheduling and management tasks for graphics core5100. In at least one embodiment, graphics microcontroller5138can perform graphics and/or compute workload scheduling on various graphics parallel engines within execution unit (EU) arrays5102A-5102F,5104A-5104F within sub-cores5101A-5101F. In at least one embodiment, host software executing on a CPU core of an SoC including graphics core5100can submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on an appropriate graphics engine. In at least one embodiment, scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In at least one embodiment, graphics microcontroller5138can also facilitate low-power or idle states for graphics core5100, providing graphics core5100with an ability to save and restore registers within graphics core5100across low-power state transitions independently from an operating system and/or graphics driver software on a system.

In at least one embodiment, graphics core5100may have greater than or fewer than illustrated sub-cores5101A-5101F, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core5100can also include shared function logic5110, shared and/or cache memory5112, a geometry/fixed function pipeline5114, as well as additional fixed function logic5116to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic5110can include logic units (e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within graphics core5100. Shared and/or cache memory5112can be an LLC for N sub-cores5101A-5101F within graphics core5100and can also serve as shared memory that is accessible by multiple sub-cores. In at least one embodiment, geometry/fixed function pipeline5114can be included instead of geometry/fixed function pipeline5136within fixed function block5130and can include same or similar logic units.

In at least one embodiment, graphics core5100includes additional fixed function logic5116that can include various fixed function acceleration logic for use by graphics core5100. In at least one embodiment, additional fixed function logic5116includes an additional geometry pipeline for use in position only shading. In position-only shading, at least two geometry pipelines exist, whereas in a full geometry pipeline within geometry/fixed function pipeline5116,5136, and a cull pipeline, which is an additional geometry pipeline which may be included within additional fixed function logic5116. In at least one embodiment, cull pipeline is a trimmed down version of a full geometry pipeline. In at least one embodiment, a full pipeline and a cull pipeline can execute different instances of an application, each instance having a separate context. In at least one embodiment, position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example, in at least one embodiment, cull pipeline logic within additional fixed function logic5116can execute position shaders in parallel with a main application and generally generates critical results faster than a full pipeline, as a cull pipeline fetches and shades position attribute of vertices, without performing rasterization and rendering of pixels to a frame buffer. In at least one embodiment, a cull pipeline can use generated critical results to compute visibility information for all triangles without regard to whether those triangles are culled. In at least one embodiment, a full pipeline (which in this instance may be referred to as a replay pipeline) can consume visibility information to skip culled triangles to shade only visible triangles that are finally passed to a rasterization phase.

In at least one embodiment, additional fixed function logic5116can also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for accelerating CUDA programs.

In at least one embodiment, each graphics sub-core5101A-5101F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. In at least one embodiment, graphics sub-cores5101A-5101F include multiple EU arrays5102A-5102F,5104A-5104F, thread dispatch and inter-thread communication (“TD/IC”) logic5103A-5103F, a 3D (e.g., texture) sampler5105A-5105F, a media sampler5106A-5106F, a shader processor5107A-5107F, and shared local memory (“SLM”)5108A-5108F. EU arrays5102A-5102F,5104A-5104F each include multiple execution units, which are GPGPUs capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. In at least one embodiment, TD/IC logic5103A-5103F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitate communication between threads executing on execution units of a sub-core. In at least one embodiment, 3D sampler5105A-5105F can read texture or other 3D graphics related data into memory. In at least one embodiment, 3D sampler can read texture data differently based on a configured sample state and texture format associated with a given texture. In at least one embodiment, media sampler5106A-5106F can perform similar read operations based on a type and format associated with media data. In at least one embodiment, each graphics sub-core5101A-5101F can alternately include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of sub-cores5101A-5101F can make use of shared local memory5108A-5108F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory.

In at least one embodiment, at least one component shown or described with respect toFIG.51is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, graphics processor core5100is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, graphics processor core5100is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, graphics processor core5100is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, graphics processor core5100is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, graphics processor core5100is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, graphics processor core5100is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, graphics processor core5100is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, graphics processor core5100is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, graphics processor core5100is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, graphics processor core5100is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, graphics processor core5100is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, graphics processor core5100is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, graphics processor core5100is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, graphics processor core5100is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.52illustrates a parallel processing unit (“PPU”)5200, in accordance with at least one embodiment. In at least one embodiment, PPU5200is configured with machine-readable code that, if executed by PPU5200, causes PPU5200to perform some or all of processes and techniques described herein. In at least one embodiment, PPU5200is a multi-threaded processor that is implemented on one or more integrated circuit devices and that utilizes multithreading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) on multiple threads in parallel. In at least one embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured to be executed by PPU5200. In at least one embodiment, PPU5200is a GPU configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data in order to generate two-dimensional (“2D”) image data for display on a display device such as an LCD device. In at least one embodiment, PPU5200is utilized to perform computations such as linear algebra operations and machine-learning operations.FIG.52illustrates an example parallel processor for illustrative purposes only and should be construed as a non-limiting example of a processor architecture that may be implemented in at least one embodiment.

In at least one embodiment, one or more PPUs5200are configured to accelerate High Performance Computing (“HPC”), data center, and machine learning applications. In at least one embodiment, one or more PPUs5200are configured to accelerate CUDA programs. In at least one embodiment, PPU5200includes, without limitation, an I/O unit5206, a front-end unit5210, a scheduler unit5212, a work distribution unit5214, a hub5216, a crossbar (“Xbar”)5220, one or more general processing clusters (“GPCs”)5218, and one or more partition units (“memory partition units”)5222. In at least one embodiment, PPU5200is connected to a host processor or other PPUs5200via one or more high-speed GPU interconnects (“GPU interconnects”)5208. In at least one embodiment, PPU5200is connected to a host processor or other peripheral devices via a system bus or interconnect5202. In at least one embodiment, PPU5200is connected to a local memory comprising one or more memory devices (“memory”)5204. In at least one embodiment, memory devices5204include, without limitation, one or more dynamic random access memory (DRAM) devices. In at least one embodiment, one or more DRAM devices are configured and/or configurable as high-bandwidth memory (“HBM”) subsystems, with multiple DRAM dies stacked within each device.

In at least one embodiment, high-speed GPU interconnect5208may refer to a wire-based multi-lane communications link that is used by systems to scale and include one or more PPUs5200combined with one or more CPUs, supports cache coherence between PPUs5200and CPUs, and CPU mastering. In at least one embodiment, data and/or commands are transmitted by high-speed GPU interconnect5208through hub5216to/from other units of PPU5200such as one or more copy engines, video encoders, video decoders, power management units, and other components which may not be explicitly illustrated inFIG.52.

In at least one embodiment, I/O unit5206is configured to transmit and receive communications (e.g., commands, data) from a host processor (not illustrated inFIG.52) over system bus5202. In at least one embodiment, I/O unit5206communicates with host processor directly via system bus5202or through one or more intermediate devices such as a memory bridge. In at least one embodiment, I/O unit5206may communicate with one or more other processors, such as one or more of PPUs5200via system bus5202. In at least one embodiment, I/O unit5206implements a PCIe interface for communications over a PCIe bus. In at least one embodiment, I/O unit5206implements interfaces for communicating with external devices.

In at least one embodiment, I/O unit5206decodes packets received via system bus5202. In at least one embodiment, at least some packets represent commands configured to cause PPU5200to perform various operations. In at least one embodiment, I/O unit5206transmits decoded commands to various other units of PPU5200as specified by commands. In at least one embodiment, commands are transmitted to front-end unit5210and/or transmitted to hub5216or other units of PPU5200such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly illustrated inFIG.52). In at least one embodiment, I/O unit5206is configured to route communications between and among various logical units of PPU5200.

In at least one embodiment, a program executed by host processor encodes a command stream in a buffer that provides workloads to PPU5200for processing. In at least one embodiment, a workload comprises instructions and data to be processed by those instructions. In at least one embodiment, buffer is a region in a memory that is accessible (e.g., read/write) by both a host processor and PPU5200—a host interface unit may be configured to access buffer in a system memory connected to system bus5202via memory requests transmitted over system bus5202by I/O unit5206. In at least one embodiment, a host processor writes a command stream to a buffer and then transmits a pointer to the start of the command stream to PPU5200such that front-end unit5210receives pointers to one or more command streams and manages one or more command streams, reading commands from command streams and forwarding commands to various units of PPU5200.

In at least one embodiment, front-end unit5210is coupled to scheduler unit5212that configures various GPCs5218to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit5212is configured to track state information related to various tasks managed by scheduler unit5212where state information may indicate which of GPCs5218a task is assigned to, whether task is active or inactive, a priority level associated with task, and so forth. In at least one embodiment, scheduler unit5212manages execution of a plurality of tasks on one or more of GPCs5218.

In at least one embodiment, scheduler unit5212is coupled to work distribution unit5214that is configured to dispatch tasks for execution on GPCs5218. In at least one embodiment, work distribution unit5214tracks a number of scheduled tasks received from scheduler unit5212and work distribution unit5214manages a pending task pool and an active task pool for each of GPCs5218. In at least one embodiment, pending task pool comprises a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC5218; active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by GPCs5218such that as one of GPCs5218completes execution of a task, that task is evicted from active task pool for GPC5218and one of other tasks from pending task pool is selected and scheduled for execution on GPC5218. In at least one embodiment, if an active task is idle on GPC5218, such as while waiting for a data dependency to be resolved, then the active task is evicted from GPC5218and returned to a pending task pool while another task in the pending task pool is selected and scheduled for execution on GPC5218.

In at least one embodiment, work distribution unit5214communicates with one or more GPCs5218via XBar5220. In at least one embodiment, XBar5220is an interconnect network that couples many units of PPU5200to other units of PPU5200and can be configured to couple work distribution unit5214to a particular GPC5218. In at least one embodiment, one or more other units of PPU5200may also be connected to XBar5220via hub5216.

In at least one embodiment, tasks are managed by scheduler unit5212and dispatched to one of GPCs5218by work distribution unit5214. GPC5218is configured to process task and generate results. In at least one embodiment, results may be consumed by other tasks within GPC5218, routed to a different GPC5218via XBar5220, or stored in memory5204. In at least one embodiment, results can be written to memory5204via partition units5222, which implement a memory interface for reading and writing data to/from memory5204. In at least one embodiment, results can be transmitted to another PPU5204or CPU via high-speed GPU interconnect5208. In at least one embodiment, PPU5200includes, without limitation, a number U of partition units5222that is equal to number of separate and distinct memory devices5204coupled to PPU5200.

In at least one embodiment, a host processor executes a driver kernel that implements an application programming interface (“API”) that enables one or more applications executing on host processor to schedule operations for execution on PPU5200. In at least one embodiment, multiple compute applications are simultaneously executed by PPU5200and PPU5200provides isolation, quality of service (“QoS”), and independent address spaces for multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause a driver kernel to generate one or more tasks for execution by PPU5200and the driver kernel outputs tasks to one or more streams being processed by PPU5200. In at least one embodiment, each task comprises one or more groups of related threads, which may be referred to as a warp. In at least one embodiment, a warp comprises a plurality of related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, cooperating threads can refer to a plurality of threads including instructions to perform a task and that exchange data through shared memory.

In at least one embodiment, at least one component shown or described with respect toFIG.52is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, parallel processing unit5200is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, parallel processing unit5200is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.53illustrates a GPC5300, in accordance with at least one embodiment. In at least one embodiment, GPC5300is GPC5218ofFIG.52. In at least one embodiment, each GPC5300includes, without limitation, a number of hardware units for processing tasks and each GPC5300includes, without limitation, a pipeline manager5302, a pre-raster operations unit (“PROP”)5304, a raster engine5308, a work distribution crossbar (“WDX”)5316, an MMU5318, one or more Data Processing Clusters (“DPCs”)5306, and any suitable combination of parts.

In at least one embodiment, operation of GPC5300is controlled by pipeline manager5302. In at least one embodiment, pipeline manager5302manages configuration of one or more DPCs5306for processing tasks allocated to GPC5300. In at least one embodiment, pipeline manager5302configures at least one of one or more DPCs5306to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC5306is configured to execute a vertex shader program on a programmable streaming multiprocessor (“SM”)5314. In at least one embodiment, pipeline manager5302is configured to route packets received from a work distribution unit to appropriate logical units within GPC5300and, in at least one embodiment, some packets may be routed to fixed function hardware units in PROP5304and/or raster engine5308while other packets may be routed to DPCs5306for processing by a primitive engine5312or SM5314. In at least one embodiment, pipeline manager5302configures at least one of DPCs5306to implement a computing pipeline. In at least one embodiment, pipeline manager5302configures at least one of DPCs5306to execute at least a portion of a CUDA program.

In at least one embodiment, PROP unit5304is configured to route data generated by raster engine5308and DPCs5306to a Raster Operations (“ROP”) unit in a partition unit, such as memory partition unit5222described in more detail above in conjunction withFIG.52. In at least one embodiment, PROP unit5304is configured to perform optimizations for color blending, organize pixel data, perform address translations, and more. In at least one embodiment, raster engine5308includes, without limitation, a number of fixed function hardware units configured to perform various raster operations and, in at least one embodiment, raster engine5308includes, without limitation, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. In at least one embodiment, a setup engine receives transformed vertices and generates plane equations associated with geometric primitive defined by vertices; plane equations are transmitted to a coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for a primitive; the output of the coarse raster engine is transmitted to a culling engine where fragments associated with a primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. In at least one embodiment, fragments that survive clipping and culling are passed to a fine raster engine to generate attributes for pixel fragments based on plane equations generated by a setup engine. In at least one embodiment, the output of raster engine5308comprises fragments to be processed by any suitable entity such as by a fragment shader implemented within DPC5306.

In at least one embodiment, each DPC5306included in GPC5300comprise, without limitation, an M-Pipe Controller (“MPC”)5310; primitive engine5312; one or more SMs5314; and any suitable combination thereof. In at least one embodiment, MPC5310controls operation of DPC5306, routing packets received from pipeline manager5302to appropriate units in DPC5306. In at least one embodiment, packets associated with a vertex are routed to primitive engine5312, which is configured to fetch vertex attributes associated with vertex from memory; in contrast, packets associated with a shader program may be transmitted to SM5314.

In at least one embodiment, SM5314comprises, without limitation, a programmable streaming processor that is configured to process tasks represented by a number of threads. In at least one embodiment, SM5314is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently and implements a SIMD architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on same set of instructions. In at least one embodiment, all threads in group of threads execute same instructions. In at least one embodiment, SM5314implements a SIMT architecture wherein each thread in a group of threads is configured to process a different set of data based on same set of instructions, but where individual threads in group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, a call stack, and an execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within a warp diverge. In another embodiment, a program counter, a call stack, and an execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. In at least one embodiment, an execution state is maintained for each individual thread and threads executing the same instructions may be converged and executed in parallel for better efficiency. At least one embodiment of SM5314is described in more detail in conjunction withFIG.54.

In at least one embodiment, MMU5318provides an interface between GPC5300and a memory partition unit (e.g., partition unit5222ofFIG.52) and MMU5318provides translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In at least one embodiment, MMU5318provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in memory.

In at least one embodiment, at least one component shown or described with respect toFIG.53is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, general processing cluster5300is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, general processing cluster5300is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, general processing cluster5300is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, general processing cluster5300is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, general processing cluster5300is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, general processing cluster5300is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, general processing cluster5300is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, general processing cluster5300is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, general processing cluster5300is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, general processing cluster5300is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, general processing cluster5300is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, general processing cluster5300is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, general processing cluster5300is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, general processing cluster5300is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.54illustrates a streaming multiprocessor (“SM”)5400, in accordance with at least one embodiment. In at least one embodiment, SM5400is SM5314ofFIG.53. In at least one embodiment, SM5400includes, without limitation, an instruction cache5402; one or more scheduler units5404; a register file5408; one or more processing cores (“cores”)5410; one or more special function units (“SFUs”)5412; one or more LSUs5414; an interconnect network5416; a shared memory/L1 cache5418; and any suitable combination thereof. In at least one embodiment, a work distribution unit dispatches tasks for execution on GPCs of parallel processing units (PPUs) and each task is allocated to a particular Data Processing Cluster (DPC) within a GPC and, if a task is associated with a shader program, then the task is allocated to one of SMs5400. In at least one embodiment, scheduler unit5404receives tasks from a work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM5400. In at least one embodiment, scheduler unit5404schedules thread blocks for execution as warps of parallel threads, wherein each thread block is allocated at least one warp. In at least one embodiment, each warp executes threads. In at least one embodiment, scheduler unit5404manages a plurality of different thread blocks, allocating warps to different thread blocks and then dispatching instructions from a plurality of different cooperative groups to various functional units (e.g., processing cores5410, SFUs5412, and LSUs5414) during each clock cycle.

In at least one embodiment, “cooperative groups” may refer to a programming model for organizing groups of communicating threads that allows developers to express granularity at which threads are communicating, enabling expression of richer, more efficient parallel decompositions. In at least one embodiment, cooperative launch APIs support synchronization amongst thread blocks for execution of parallel algorithms. In at least one embodiment, APIs of conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., syncthreads( ) function). However, in at least one embodiment, programmers may define groups of threads at smaller than thread block granularities and synchronize within defined groups to enable greater performance, design flexibility, and software reuse in the form of collective group-wide function interfaces. In at least one embodiment, cooperative groups enable programmers to define groups of threads explicitly at sub-block and multi-block granularities, and to perform collective operations such as synchronization on threads in a cooperative group. In at least one embodiment, a sub-block granularity is as small as a single thread. In at least one embodiment, a programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. In at least one embodiment, cooperative group primitives enable new patterns of cooperative parallelism, including, without limitation, producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

In at least one embodiment, a dispatch unit5406is configured to transmit instructions to one or more of functional units and scheduler unit5404includes, without limitation, two dispatch units5406that enable two different instructions from same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit5404includes a single dispatch unit5406or additional dispatch units5406.

In at least one embodiment, each SM5400, in at least one embodiment, includes, without limitation, register file5408that provides a set of registers for functional units of SM5400. In at least one embodiment, register file5408is divided between each of the functional units such that each functional unit is allocated a dedicated portion of register file5408. In at least one embodiment, register file5408is divided between different warps being executed by SM5400and register file5408provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM5400comprises, without limitation, a plurality of L processing cores5410. In at least one embodiment, SM5400includes, without limitation, a large number (e.g., 128 or more) of distinct processing cores5410. In at least one embodiment, each processing core5410includes, without limitation, a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes, without limitation, a floating point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, floating point arithmetic logic units implement IEEE 754-2008 standard for floating point arithmetic. In at least one embodiment, processing cores5410include, without limitation, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

In at least one embodiment, tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing cores5410. In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

In at least one embodiment, matrix multiply inputs A and B are 16-bit floating point matrices and accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, tensor cores operate on 16-bit floating point input data with 32-bit floating point accumulation. In at least one embodiment, 16-bit floating point multiply uses 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with other intermediate products for a 4×4×4 matrix multiply. Tensor cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements, in at least one embodiment. In at least one embodiment, an API, such as a CUDA-C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, a warp-level interface assumes 16×16 size matrices spanning all 32 threads of a warp.

In at least one embodiment, each SM5400comprises, without limitation, M SFUs5412that perform special functions (e.g., attribute evaluation, reciprocal square root, and like). In at least one embodiment, SFUs5412include, without limitation, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, SFUs5412include, without limitation, a texture unit configured to perform texture map filtering operations. In at least one embodiment, texture units are configured to load texture maps (e.g., a 2D array of texels) from memory and sample texture maps to produce sampled texture values for use in shader programs executed by SM5400. In at least one embodiment, texture maps are stored in shared memory/L1 cache5418. In at least one embodiment, texture units implement texture operations such as filtering operations using mip-maps (e.g., texture maps of varying levels of detail). In at least one embodiment, each SM5400includes, without limitation, two texture units.

In at least one embodiment, each SM5400comprises, without limitation, N LSUs5414that implement load and store operations between shared memory/L1 cache5418and register file5408. In at least one embodiment, each SM5400includes, without limitation, interconnect network5416that connects each of the functional units to register file5408and LSU5414to register file5408and shared memory/L1 cache5418. In at least one embodiment, interconnect network5416is a crossbar that can be configured to connect any of the functional units to any of the registers in register file5408and connect LSUs5414to register file5408and memory locations in shared memory/L1 cache5418.

In at least one embodiment, shared memory/L1 cache5418is an array of on-chip memory that allows for data storage and communication between SM5400and a primitive engine and between threads in SM5400. In at least one embodiment, shared memory/L1 cache5418comprises, without limitation, 128 KB of storage capacity and is in a path from SM5400to a partition unit. In at least one embodiment, shared memory/L1 cache5418is used to cache reads and writes. In at least one embodiment, one or more of shared memory/L1 cache5418, L2 cache, and memory are backing stores.

In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, capacity is used or is usable as a cache by programs that do not use shared memory, such as if shared memory is configured to use half of capacity, texture and load/store operations can use remaining capacity. In at least one embodiment, integration within shared memory/L1 cache5418enables shared memory/L1 cache5418to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. In at least one embodiment, fixed function GPUs are bypassed, creating a much simpler programming model. In at least one embodiment and in a general purpose parallel computation configuration, a work distribution unit assigns and distributes blocks of threads directly to DPCs. In at least one embodiment, threads in a block execute the same program, using a unique thread ID in a calculation to ensure each thread generates unique results, using SM5400to execute a program and perform calculations, shared memory/L1 cache5418to communicate between threads, and LSU5414to read and write global memory through shared memory/L1 cache5418and a memory partition unit. In at least one embodiment, when configured for general purpose parallel computation, SM5400writes commands that scheduler unit5404can use to launch new work on DPCs.

In at least one embodiment, PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), a PDA, a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and more. In at least one embodiment, PPU is embodied on a single semiconductor substrate. In at least one embodiment, PPU is included in an SoC along with one or more other devices such as additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter (“DAC”), and like.

In at least one embodiment, PPU may be included on a graphics card that includes one or more memory devices. In at least one embodiment, a graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, PPU may be an integrated GPU (“iGPU”) included in chipset of motherboard.

In at least one embodiment, at least one component shown or described with respect toFIG.54is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, streaming multiprocessor5400is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, streaming multiprocessor5400is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

Software Constructions for General-Purpose Computing

The following figures set forth, without limitation, exemplary software constructs for implementing at least one embodiment.

FIG.55illustrates a software stack of a programming platform, in accordance with at least one embodiment. In at least one embodiment, a programming platform is a platform for leveraging hardware on a computing system to accelerate computational tasks. A programming platform may be accessible to software developers through libraries, compiler directives, and/or extensions to programming languages, in at least one embodiment. In at least one embodiment, a programming platform may be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL™ is developed by Khronos group), SYCL, or Intel One API.

In at least one embodiment, a software stack5500of a programming platform provides an execution environment for an application5501. In at least one embodiment, application5501may include any computer software capable of being launched on software stack5500. In at least one embodiment, application5501may include, but is not limited to, an artificial intelligence (“AI”)/machine learning (“ML”) application, a high performance computing (“HPC”) application, a virtual desktop infrastructure (“VDI”), or a data center workload.

In at least one embodiment, application5501and software stack5500run on hardware5507. Hardware5507may include one or more GPUs, CPUs, FPGAs, AI engines, and/or other types of compute devices that support a programming platform, in at least one embodiment. In at least one embodiment, such as with CUDA, software stack5500may be vendor specific and compatible with only devices from particular vendor(s). In at least one embodiment, such as in with OpenCL, software stack5500may be used with devices from different vendors. In at least one embodiment, hardware5507includes a host connected to one more devices that can be accessed to perform computational tasks via application programming interface (“API”) calls. A device within hardware5507may include, but is not limited to, a GPU, FPGA, AI engine, or other compute device (but may also include a CPU) and its memory, as opposed to a host within hardware5507that may include, but is not limited to, a CPU (but may also include a compute device) and its memory, in at least one embodiment.

In at least one embodiment, software stack5500of a programming platform includes, without limitation, a number of libraries5503, a runtime5505, and a device kernel driver5506. Each of libraries5503may include data and programming code that can be used by computer programs and leveraged during software development, in at least one embodiment. In at least one embodiment, libraries5503may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and/or message templates. In at least one embodiment, libraries5503include functions that are optimized for execution on one or more types of devices. In at least one embodiment, libraries5503may include, but are not limited to, functions for performing mathematical, deep learning, and/or other types of operations on devices. In at least one embodiment, libraries5503are associated with corresponding APIs5502, which may include one or more APIs, that expose functions implemented in libraries5503.

In at least one embodiment, application5501is written as source code that is compiled into executable code, as discussed in greater detail below in conjunction withFIGS.60-62. Executable code of application5501may run, at least in part, on an execution environment provided by software stack5500, in at least one embodiment. In at least one embodiment, during execution of application5501, code may be reached that needs to run on a device, as opposed to a host. In such a case, runtime5505may be called to load and launch requisite code on the device, in at least one embodiment. In at least one embodiment, runtime5505may include any technically feasible runtime system that is able to support execution of application S01.

In at least one embodiment, runtime5505is implemented as one or more runtime libraries associated with corresponding APIs, which are shown as API(s)5504. One or more of such runtime libraries may include, without limitation, functions for memory management, execution control, device management, error handling, and/or synchronization, among other things, in at least one embodiment. In at least one embodiment, memory management functions may include, but are not limited to, functions to allocate, deallocate, and copy device memory, as well as transfer data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions to launch a function (sometimes referred to as a “kernel” when a function is a global function callable from a host) on a device and set attribute values in a buffer maintained by a runtime library for a given function to be executed on a device.

Runtime libraries and corresponding API(s)5504may be implemented in any technically feasible manner, in at least one embodiment. In at least one embodiment, one (or any number of) API may expose a low-level set of functions for fine-grained control of a device, while another (or any number of) API may expose a higher-level set of such functions. In at least one embodiment, a high-level runtime API may be built on top of a low-level API. In at least one embodiment, one or more of runtime APIs may be language-specific APIs that are layered on top of a language-independent runtime API.

In at least one embodiment, device kernel driver5506is configured to facilitate communication with an underlying device. In at least one embodiment, device kernel driver5506may provide low-level functionalities upon which APIs, such as API(s)5504, and/or other software relies. In at least one embodiment, device kernel driver5506may be configured to compile intermediate representation (“IR”) code into binary code at runtime. For CUDA, device kernel driver5506may compile Parallel Thread Execution (“PTX”) IR code that is not hardware specific into binary code for a specific target device at runtime (with caching of compiled binary code), which is also sometimes referred to as “finalizing” code, in at least one embodiment. Doing so may permit finalized code to run on a target device, which may not have existed when source code was originally compiled into PTX code, in at least one embodiment. Alternatively, in at least one embodiment, device source code may be compiled into binary code offline, without requiring device kernel driver5506to compile IR code at runtime.

In at least one embodiment, at least one element of software stack5500of a programming platform is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.56illustrates a CUDA implementation of software stack5500ofFIG.55, in accordance with at least one embodiment. In at least one embodiment, a CUDA software stack5600, on which an application5601may be launched, includes CUDA libraries5603, a CUDA runtime5605, a CUDA driver5607, and a device kernel driver5608. In at least one embodiment, CUDA software stack5600executes on hardware5609, which may include a GPU that supports CUDA and is developed by NVIDIA Corporation of Santa Clara, CA.

In at least one embodiment, application5601, CUDA runtime5605, and device kernel driver5608may perform similar functionalities as application5501, runtime5505, and device kernel driver5506, respectively, which are described above in conjunction withFIG.55. In at least one embodiment, CUDA driver5607includes a library (libcuda.so) that implements a CUDA driver API5606. Similar to a CUDA runtime API5604implemented by a CUDA runtime library (cudart), CUDA driver API5606may, without limitation, expose functions for memory management, execution control, device management, error handling, synchronization, and/or graphics interoperability, among other things, in at least one embodiment. In at least one embodiment, CUDA driver API5606differs from CUDA runtime API5604in that CUDA runtime API5604simplifies device code management by providing implicit initialization, context (analogous to a process) management, and module (analogous to dynamically loaded libraries) management. In contrast to high-level CUDA runtime API5604, CUDA driver API5606is a low-level API providing more fine-grained control of the device, particularly with respect to contexts and module loading, in at least one embodiment. In at least one embodiment, CUDA driver API5606may expose functions for context management that are not exposed by CUDA runtime API5604. In at least one embodiment, CUDA driver API5606is also language-independent and supports, e.g., OpenCL in addition to CUDA runtime API5604. Further, in at least one embodiment, development libraries, including CUDA runtime5605, may be considered as separate from driver components, including user-mode CUDA driver5607and kernel-mode device driver5608(also sometimes referred to as a “display” driver).

In at least one embodiment, CUDA libraries5603may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and/or signal/image/video processing libraries, which parallel computing applications such as application5601may utilize. In at least one embodiment, CUDA libraries5603may include mathematical libraries such as a cuBLAS library that is an implementation of Basic Linear Algebra Subprograms (“BLAS”) for performing linear algebra operations, a cuFFT library for computing fast Fourier transforms (“FFTs”), and a cuRAND library for generating random numbers, among others. In at least one embodiment, CUDA libraries5603may include deep learning libraries such as a cuDNN library of primitives for deep neural networks and a TensorRT platform for high-performance deep learning inference, among others.

In at least one embodiment, at least one element of CUDA software stack5600is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.57illustrates a ROCm implementation of software stack5500ofFIG.55, in accordance with at least one embodiment. In at least one embodiment, a ROCm software stack5700, on which an application5701may be launched, includes a language runtime5703, a system runtime5705, a thunk5707, and a ROCm kernel driver5708. In at least one embodiment, ROCm software stack5700executes on hardware5709, which may include a GPU that supports ROCm and is developed by AMD Corporation of Santa Clara, CA.

In at least one embodiment, application5701may perform similar functionalities as application5501discussed above in conjunction withFIG.55. In addition, language runtime5703and system runtime5705may perform similar functionalities as runtime5505discussed above in conjunction withFIG.55, in at least one embodiment. In at least one embodiment, language runtime5703and system runtime5705differ in that system runtime5705is a language-independent runtime that implements a ROCr system runtime API5704and makes use of a Heterogeneous System Architecture (“HSA”) Runtime API. HSA runtime API is a thin, user-mode API that exposes interfaces to access and interact with an AMD GPU, including functions for memory management, execution control via architected dispatch of kernels, error handling, system and agent information, and runtime initialization and shutdown, among other things, in at least one embodiment. In contrast to system runtime5705, language runtime5703is an implementation of a language-specific runtime API5702layered on top of ROCr system runtime API5704, in at least one embodiment. In at least one embodiment, language runtime API may include, but is not limited to, a Heterogeneous compute Interface for Portability (“HIP”) language runtime API, a Heterogeneous Compute Compiler (“HCC”) language runtime API, or an OpenCL API, among others. HIP language in particular is an extension of C++ programming language with functionally similar versions of CUDA mechanisms, and, in at least one embodiment, a HIP language runtime API includes functions that are similar to those of CUDA runtime API5604discussed above in conjunction withFIG.56, such as functions for memory management, execution control, device management, error handling, and synchronization, among other things.

In at least one embodiment, thunk (ROCt)5707is an interface5706that can be used to interact with underlying ROCm driver5708. In at least one embodiment, ROCm driver5708is a ROCk driver, which is a combination of an AMDGPU driver and a HSA kernel driver (amdkfd). In at least one embodiment, AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs similar functionalities as device kernel driver5506discussed above in conjunction withFIG.55. In at least one embodiment, HSA kernel driver is a driver permitting different types of processors to share system resources more effectively via hardware features.

In at least one embodiment, various libraries (not shown) may be included in ROCm software stack5700above language runtime5703and provide functionality similarity to CUDA libraries5603, discussed above in conjunction withFIG.56. In at least one embodiment, various libraries may include, but are not limited to, mathematical, deep learning, and/or other libraries such as a hipBLAS library that implements functions similar to those of CUDA cuBLAS, a rocFFT library for computing FFTs that is similar to CUDA cuFFT, among others.

In at least one embodiment, at least one element of ROCm software stack5700is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.58illustrates an OpenCL implementation of software stack5500ofFIG.55, in accordance with at least one embodiment. In at least one embodiment, an OpenCL software stack5800, on which an application5801may be launched, includes an OpenCL framework5810, an OpenCL runtime5806, and a driver5807. In at least one embodiment, OpenCL software stack5800executes on hardware5609that is not vendor-specific. As OpenCL is supported by devices developed by different vendors, specific OpenCL drivers may be required to interoperate with hardware from such vendors, in at least one embodiment.

In at least one embodiment, application5801, OpenCL runtime5806, device kernel driver5807, and hardware5808may perform similar functionalities as application5501, runtime5505, device kernel driver5506, and hardware5507, respectively, that are discussed above in conjunction withFIG.55. In at least one embodiment, application5801further includes an OpenCL kernel5802with code that is to be executed on a device.

In at least one embodiment, OpenCL defines a “platform” that allows a host to control devices connected to the host. In at least one embodiment, an OpenCL framework provides a platform layer API and a runtime API, shown as platform API5803and runtime API5805. In at least one embodiment, runtime API5805uses contexts to manage execution of kernels on devices. In at least one embodiment, each identified device may be associated with a respective context, which runtime API5805may use to manage command queues, program objects, and kernel objects, share memory objects, among other things, for that device. In at least one embodiment, platform API5803exposes functions that permit device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices, among other things. In addition, OpenCL framework provides various built-in functions (not shown), including math functions, relational functions, and image processing functions, among others, in at least one embodiment.

In at least one embodiment, a compiler5804is also included in OpenCL frame-work5810. Source code may be compiled offline prior to executing an application or online during execution of an application, in at least one embodiment. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment may be compiled online by compiler5804, which is included to be representative of any number of compilers that may be used to compile source code and/or IR code, such as Standard Portable Intermediate Representation (“SPIR-V”) code, into binary code. Alternatively, in at least one embodiment, OpenCL ap-plications may be compiled offline, prior to execution of such applications.

In at least one embodiment, at least one element of OpenCL software stack5800is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.59illustrates software that is supported by a programming platform, in accordance with at least one embodiment. In at least one embodiment, a programming platform5904is configured to support various programming models5903, middlewares and/or libraries5902, and frameworks5901that an application5900may rely upon. In at least one embodiment, application5900may be an AI/ML application implemented using, for example, a deep learning framework such as MXNet, PyTorch, or TensorFlow, which may rely on libraries such as cuDNN, NVIDIA Collective Communications Library (“NCCL”), and/or NVIDA Developer Data Loading Library (“DALI”) CUDA libraries to provide accelerated computing on underlying hardware.

In at least one embodiment, programming platform5904may be one of a CUDA, ROCm, or OpenCL platform described above in conjunction withFIG.56,FIG.57, andFIG.58, respectively. In at least one embodiment, programming platform5904supports multiple programming models5903, which are abstractions of an underlying computing system permitting expressions of algorithms and data structures. Programming models5903may expose features of underlying hardware in order to improve performance, in at least one embodiment. In at least one embodiment, programming models5903may include, but are not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++ AMP”), Open Multi-Processing (“OpenMP”), Open Accelerators (“OpenACC”), and/or Vulcan Compute.

In at least one embodiment, libraries and/or middlewares5902provide implementations of abstractions of programming models5904. In at least one embodiment, such libraries include data and programming code that may be used by computer programs and leveraged during software development. In at least one embodiment, such middlewares include software that provides services to applications beyond those available from programming platform5904. In at least one embodiment, libraries and/or middlewares5902may include, but are not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. In addition, in at least one embodiment, libraries and/or middlewares5902may include NCCL and ROCm Communication Collectives Library (“RCCL”) libraries providing communication routines for GPUs, a MIOpen library for deep learning acceleration, and/or an Eigen library for linear algebra, matrix and vector operations, geometrical transformations, numerical solvers, and related algorithms.

In at least one embodiment, application frameworks5901depend on libraries and/or middlewares5902. In at least one embodiment, each of application frameworks5901is a software framework used to implement a standard structure of application software. Returning to the AI/ML example discussed above, an AI/ML application may be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning frameworks, in at least one embodiment.

In at least one embodiment, at least one component shown or described with respect toFIG.59is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, application5900is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, application5900is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, application5900is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, application5900is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, application5900is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, application5900is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, application5900is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, application5900is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, application5900is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, application5900is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, application5900is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, application5900is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, application5900is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, application5900is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.60illustrates compiling code to execute on one of programming platforms ofFIGS.55-58, in accordance with at least one embodiment. In at least one embodiment, a compiler6001receives source code6000that includes both host code as well as device code. In at least one embodiment, complier6001is configured to convert source code6000into host executable code6002for execution on a host and device executable code6003for execution on a device. In at least one embodiment, source code6000may either be compiled offline prior to execution of an application, or online during execution of an application.

In at least one embodiment, source code6000may include code in any programming language supported by compiler6001, such as C++, C, Fortran, etc. In at least one embodiment, source code6000may be included in a single-source file having a mixture of host code and device code, with locations of device code being indicated therein. In at least one embodiment, a single-source file may be a .cu file that includes CUDA code or a .hip.cpp file that includes HIP code. Alternatively, in at least one embodiment, source code6000may include multiple source code files, rather than a single-source file, into which host code and device code are separated.

In at least one embodiment, compiler6001is configured to compile source code6000into host executable code6002for execution on a host and device executable code6003for execution on a device. In at least one embodiment, compiler6001performs operations including parsing source code6000into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment in which source code6000includes a single-source file, compiler6001may separate device code from host code in such a single-source file, compile device code and host code into device executable code6003and host executable code6002, respectively, and link device executable code6003and host executable code6002together in a single file, as discussed in greater detail below with respect toFIG.61.

In at least one embodiment, host executable code6002and device executable code6003may be in any suitable format, such as binary code and/or IR code. In the case of CUDA, host executable code6002may include native object code and device executable code6003may include code in PTX intermediate representation, in at least one embodiment. In the case of ROCm, both host executable code6002and device executable code6003may include target binary code, in at least one embodiment.

In at least one embodiment, at least one component shown or described with respect toFIG.60is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, at least one of host executable code6002or device executable code6003specified in source code6000is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.61is a more detailed illustration of compiling code to execute on one of programming platforms ofFIGS.55-58, in accordance with at least one embodiment. In at least one embodiment, a compiler6101is configured to receive source code6100, compile source code6100, and output an executable file6110. In at least one embodiment, source code6100is a single-source file, such as a .cu file, a .hip.cpp file, or a file in another format, that includes both host and device code. In at least one embodiment, compiler6101may be, but is not limited to, an NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in .cu files, or a HCC compiler for compiling HIP code in .hip.cpp files.

In at least one embodiment, compiler6101includes a compiler front end6102, a host compiler6105, a device compiler6106, and a linker6109. In at least one embodiment, compiler front end6102is configured to separate device code6104from host code6103in source code6100. Device code6104is compiled by device compiler6106into device executable code6108, which as described may include binary code or IR code, in at least one embodiment. Separately, host code6103is compiled by host compiler6105into host executable code6107, in at least one embodiment. For NVCC, host compiler6105may be, but is not limited to, a general purpose C/C++ compiler that outputs native object code, while device compiler6106may be, but is not limited to, a Low Level Virtual Machine (“LLVM”)-based compiler that forks a LLVM compiler infrastructure and outputs PTX code or binary code, in at least one embodiment. For HCC, both host compiler6105and device compiler6106may be, but are not limited to, LLVM-based compilers that output target binary code, in at least one embodiment.

Subsequent to compiling source code6100into host executable code6107and device executable code6108, linker6109links host and device executable code6107and6108together in executable file6110, in at least one embodiment. In at least one embodiment, native object code for a host and PTX or binary code for a device may be linked together in an Executable and Linkable Format (“ELF”) file, which is a container format used to store object code.

In at least one embodiment, at least one component shown or described with respect toFIG.61is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, executable file6110implemented using source code6100is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, executable file6110implemented using source code6100is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.62illustrates translating source code prior to compiling source code, in accordance with at least one embodiment. In at least one embodiment, source code6200is passed through a translation tool6201, which translates source code6200into translated source code6202. In at least one embodiment, a compiler6203is used to compile translated source code6202into host executable code6204and device executable code6205in a process that is similar to compilation of source code6000by compiler6001into host executable code6002and device executable6003, as discussed above in conjunction withFIG.60.

In at least one embodiment, a translation performed by translation tool6201is used to port source6200for execution in a different environment than that in which it was originally intended to run. In at least one embodiment, translation tool6201may include, but is not limited to, a HIP translator that is used to “hipify” CUDA code intended for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, translation of source code6200may include parsing source code6200and converting calls to API(s) provided by one programming model (e.g., CUDA) into corresponding calls to API(s) provided by another programming model (e.g., HIP), as discussed in greater detail below in conjunction withFIGS.63A-64. Returning to the example of hipifying CUDA code, calls to CUDA runtime API, CUDA driver API, and/or CUDA libraries may be converted to corresponding HIP API calls, in at least one embodiment. In at least one embodiment, automated translations performed by translation tool6201may sometimes be incomplete, requiring additional, manual effort to fully port source code6200.

In at least one embodiment, at least one component shown or described with respect toFIG.62is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, at least one of host executable code6204or device executable code6205specified in source code6200is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

Configuring GPUs for General-Purpose Computing

The following figures set forth, without limitation, exemplary architectures for compiling and executing compute source code, in accordance with at least one embodiment.

FIG.63Aillustrates a system63A00configured to compile and execute CUDA source code6310using different types of processing units, in accordance with at least one embodiment. In at least one embodiment, system63A00includes, without limitation, CUDA source code6310, a CUDA compiler6350, host executable code6370(1), host executable code6370(2), CUDA device executable code6384, a CPU6390, a CUDA-enabled GPU6394, a GPU6392, a CUDA to HIP translation tool6320, HIP source code6330, a HIP compiler driver6340, an HCC6360, and HCC device executable code6382.

In at least one embodiment, CUDA source code6310is a collection of human-readable code in a CUDA programming language. In at least one embodiment, CUDA code is human-readable code in a CUDA programming language. In at least one embodiment, a CUDA programming language is an extension of the C++ programming language that includes, without limitation, mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, device code is source code that, after compilation, is executable in parallel on a device. In at least one embodiment, a device may be a processor that is optimized for parallel instruction processing, such as CUDA-enabled GPU6390, GPU63192, or another GPGPU, etc. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In at least one embodiment, a host is a processor that is optimized for sequential instruction processing, such as CPU6390.

In at least one embodiment, CUDA source code6310includes, without limitation, any number (including zero) of global functions6312, any number (including zero) of device functions6314, any number (including zero) of host functions6316, and any number (including zero) of host/device functions6318. In at least one embodiment, global functions6312, device functions6314, host functions6316, and host/device functions6318may be mixed in CUDA source code6310. In at least one embodiment, each of global functions6312is executable on a device and callable from a host. In at least one embodiment, one or more of global functions6312may therefore act as entry points to a device. In at least one embodiment, each of global functions6312is a kernel. In at least one embodiment and in a technique known as dynamic parallelism, one or more of global functions6312defines a kernel that is executable on a device and callable from such a device. In at least one embodiment, a kernel is executed N (where N is any positive integer) times in parallel by N different threads on a device during execution.

In at least one embodiment, each of device functions6314is executed on a device and callable from such a device only. In at least one embodiment, each of host functions6316is executed on a host and callable from such a host only. In at least one embodiment, each of host/device functions6316defines both a host version of a function that is executable on a host and callable from such a host only and a device version of the function that is executable on a device and callable from such a device only.

In at least one embodiment, CUDA source code6310may also include, without limitation, any number of calls to any number of functions that are defined via a CUDA runtime API6302. In at least one embodiment, CUDA runtime API6302may include, without limitation, any number of functions that execute on a host to allocate and deallocate device memory, transfer data between host memory and device memory, manage systems with multiple devices, etc. In at least one embodiment, CUDA source code6310may also include any number of calls to any number of functions that are specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API that is designed for use by CUDA code. In at least one embodiment, CUDA APIs include, without limitation, CUDA runtime API6302, a CUDA driver API, APIs for any number of CUDA libraries, etc. In at least one embodiment and relative to CUDA runtime API6302, a CUDA driver API is a lower-level API but provides finer-grained control of a device. In at least one embodiment, examples of CUDA libraries include, without limitation, cuBLAS, cuFFT, cuRAND, cuDNN, etc.

In at least one embodiment, CUDA compiler6350compiles input CUDA code (e.g., CUDA source code6310) to generate host executable code6370(1) and CUDA device executable code6384. In at least one embodiment, CUDA compiler6350is NVCC. In at least one embodiment, host executable code6370(1) is a compiled version of host code included in input source code that is executable on CPU6390. In at least one embodiment, CPU6390may be any processor that is optimized for sequential instruction processing.

In at least one embodiment, CUDA device executable code6384is a compiled version of device code included in input source code that is executable on CUDA-enabled GPU6394. In at least one embodiment, CUDA device executable code6384includes, without limitation, binary code. In at least one embodiment, CUDA device executable code6384includes, without limitation, IR code, such as PTX code, that is further compiled at runtime into binary code for a specific target device (e.g., CUDA-enabled GPU6394) by a device driver. In at least one embodiment, CUDA-enabled GPU6394may be any processor that is optimized for parallel instruction processing and that supports CUDA. In at least one embodiment, CUDA-enabled GPU6394is developed by NVIDIA Corporation of Santa Clara, CA.

In at least one embodiment, CUDA to HIP translation tool6320is configured to translate CUDA source code6310to functionally similar HIP source code6330. In a least one embodiment, HIP source code6330is a collection of human-readable code in a HIP programming language. In at least one embodiment, HIP code is human-readable code in a HIP programming language. In at least one embodiment, a HIP programming language is an extension of the C++ programming language that includes, without limitation, functionally similar versions of CUDA mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, a HIP programming language may include a subset of functionality of a CUDA programming language. In at least one embodiment, for example, a HIP programming language includes, without limitation, mechanism(s) to define global functions6312, but such a HIP programming language may lack support for dynamic parallelism and therefore global functions6312defined in HIP code may be callable from a host only.

In at least one embodiment, HIP source code6330includes, without limitation, any number (including zero) of global functions6312, any number (including zero) of device functions6314, any number (including zero) of host functions6316, and any number (including zero) of host/device functions6318. In at least one embodiment, HIP source code6330may also include any number of calls to any number of functions that are specified in a HIP runtime API6332. In at least one embodiment, HIP runtime API6332includes, without limitation, functionally similar versions of a subset of functions included in CUDA runtime API6302. In at least one embodiment, HIP source code6330may also include any number of calls to any number of functions that are specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API that is designed for use by HIP code and/or ROCm. In at least one embodiment, HIP APIs include, without limitation, HIP runtime API6332, a HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, etc.

In at least one embodiment, CUDA to HIP translation tool6320converts each kernel call in CUDA code from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in a CUDA API, and a HIP call is a call to a function specified in a HIP API. In at least one embodiment, CUDA to HIP translation tool6320converts any number of calls to functions specified in CUDA runtime API6302to any number of calls to functions specified in HIP runtime API6332.

In at least one embodiment, CUDA to HIP translation tool6320is a tool known as hipify-perl that executes a text-based translation process. In at least one embodiment, CUDA to HIP translation tool6320is a tool known as hipify-clang that, relative to hipify-perl, executes a more complex and more robust translation process that involves parsing CUDA code using clang (a compiler front-end) and then translating resulting symbols. In at least one embodiment, properly converting CUDA code to HIP code may require modifications (e.g., manual edits) in addition to those performed by CUDA to HIP translation tool6320.

In at least one embodiment, HIP compiler driver6340is a front end that determines a target device6346and then configures a compiler that is compatible with target device6346to compile HIP source code6330. In at least one embodiment, target device6346is a processor that is optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver6340may determine target device6346in any technically feasible fashion.

In at least one embodiment, if target device6346is compatible with CUDA (e.g., CUDA-enabled GPU6394), then HIP compiler driver6340generates a HIP/NVCC compilation command6342. In at least one embodiment and as described in greater detail in conjunction withFIG.63B, HIP/NVCC compilation command6342configures CUDA compiler6350to compile HIP source code6330using, without limitation, a HIP to CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to HIP/NVCC compilation command6342, CUDA compiler6350generates host executable code6370(1) and CUDA device executable code6384.

In at least one embodiment, if target device6346is not compatible with CUDA, then HIP compiler driver6340generates a HIP/HCC compilation command6344. In at least one embodiment and as described in greater detail in conjunction withFIG.63C, HIP/HCC compilation command6344configures HCC6360to compile HIP source code6330using, without limitation, an HCC header and a HIP/HCC runtime library. In at least one embodiment and in response to HIP/HCC compilation command6344, HCC6360generates host executable code6370(2) and HCC device executable code6382. In at least one embodiment, HCC device executable code6382is a compiled version of device code included in HIP source code6330that is executable on GPU6392. In at least one embodiment, GPU6392may be any processor that is optimized for parallel instruction processing, is not compatible with CUDA, and is compatible with HCC. In at least one embodiment, GPU6392is developed by AMD Corporation of Santa Clara, CA. In at least one embodiment GPU,6392is a non-CUDA-enabled GPU6392.

For explanatory purposes only, three different flows that may be implemented in at least one embodiment to compile CUDA source code6310for execution on CPU6390and different devices are depicted inFIG.63A. In at least one embodiment, a direct CUDA flow compiles CUDA source code6310for execution on CPU6390and CUDA-enabled GPU6394without translating CUDA source code6310to HIP source code6330. In at least one embodiment, an indirect CUDA flow translates CUDA source code6310to HIP source code6330and then compiles HIP source code6330for execution on CPU6390and CUDA-enabled GPU6394. In at least one embodiment, a CUDA/HCC flow translates CUDA source code6310to HIP source code6330and then compiles HIP source code6330for execution on CPU6390and GPU6392.

A direct CUDA flow that may be implemented in at least one embodiment is depicted via dashed lines and a series of bubbles annotated A1-A3. In at least one embodiment and as depicted with bubble annotated A1, CUDA compiler6350receives CUDA source code6310and a CUDA compile command6348that configures CUDA compiler6350to compile CUDA source code6310. In at least one embodiment, CUDA source code6310used in a direct CUDA flow is written in a CUDA programming language that is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment and in response to CUDA compile command6348, CUDA compiler6350generates host executable code6370(1) and CUDA device executable code6384(depicted with bubble annotated A2). In at least one embodiment and as depicted with bubble annotated A3, host executable code6370(1) and CUDA device executable code6384may be executed on, respectively, CPU6390and CUDA-enabled GPU6394. In at least one embodiment, CUDA device executable code6384includes, without limitation, binary code. In at least one embodiment, CUDA device executable code6384includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime.

An indirect CUDA flow that may be implemented in at least one embodiment is depicted via dotted lines and a series of bubbles annotated B1-B6. In at least one embodiment and as depicted with bubble annotated B1, CUDA to HIP translation tool6320receives CUDA source code6310. In at least one embodiment and as depicted with bubble annotated B2, CUDA to HIP translation tool6320translates CUDA source code6310to HIP source code6330. In at least one embodiment and as depicted with bubble annotated B3, HIP compiler driver6340receives HIP source code6330and determines that target device6346is CUDA-enabled.

In at least one embodiment and as depicted with bubble annotated B4, HIP compiler driver6340generates HIP/NVCC compilation command6342and transmits both HIP/NVCC compilation command6342and HIP source code6330to CUDA compiler6350. In at least one embodiment and as described in greater detail in conjunction withFIG.63B, HIP/NVCC compilation command6342configures CUDA compiler6350to compile HIP source code6330using, without limitation, a HIP to CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to HIP/NVCC compilation command6342, CUDA compiler6350generates host executable code6370(1) and CUDA device executable code6384(depicted with bubble annotated B5). In at least one embodiment and as depicted with bubble annotated B6, host executable code6370(1) and CUDA device executable code6384may be executed on, respectively, CPU6390and CUDA-enabled GPU6394. In at least one embodiment, CUDA device executable code6384includes, without limitation, binary code. In at least one embodiment, CUDA device executable code6384includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime.

A CUDA/HCC flow that may be implemented in at least one embodiment is depicted via solid lines and a series of bubbles annotated C1-C6. In at least one embodiment and as depicted with bubble annotated C1, CUDA to HIP translation tool6320receives CUDA source code6310. In at least one embodiment and as depicted with bubble annotated C2, CUDA to HIP translation tool6320translates CUDA source code6310to HIP source code6330. In at least one embodiment and as depicted with bubble annotated C3, HIP compiler driver6340receives HIP source code6330and determines that target device6346is not CUDA-enabled.

In at least one embodiment, HIP compiler driver6340generates HIP/HCC compilation command6344and transmits both HIP/HCC compilation command6344and HIP source code6330to HCC6360(depicted with bubble annotated C4). In at least one embodiment and as described in greater detail in conjunction withFIG.63C, HIP/HCC compilation command6344configures HCC6360to compile HIP source code6330using, without limitation, an HCC header and a HIP/HCC runtime library. In at least one embodiment and in response to HIP/HCC compilation command6344, HCC6360generates host executable code6370(2) and HCC device executable code6382(depicted with bubble annotated C5). In at least one embodiment and as depicted with bubble annotated C6, host executable code6370(2) and HCC device executable code6382may be executed on, respectively, CPU6390and GPU6392.

In at least one embodiment, after CUDA source code6310is translated to HIP source code6330, HIP compiler driver6340may subsequently be used to generate executable code for either CUDA-enabled GPU6394or GPU6392without re-executing CUDA to HIP translation tool6320. In at least one embodiment, CUDA to HIP translation tool6320translates CUDA source code6310to HIP source code6330that is then stored in memory. In at least one embodiment, HIP compiler driver6340then configures HCC6360to generate host executable code6370(2) and HCC device executable code6382based on HIP source code6330. In at least one embodiment, HIP compiler driver6340subsequently configures CUDA compiler6350to generate host executable code6370(1) and CUDA device executable code6384based on stored HIP source code6330.

In at least one embodiment, at least one element of system6300is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.63Billustrates a system6304configured to compile and execute CUDA source code6310ofFIG.63Ausing CPU6390and CUDA-enabled GPU6394, in accordance with at least one embodiment. In at least one embodiment, system6304includes, without limitation, CUDA source code6310, CUDA to HIP translation tool6320, HIP source code6330, HIP compiler driver6340, CUDA compiler6350, host executable code6370(1), CUDA device executable code6384, CPU6390, and CUDA-enabled GPU6394.

In at least one embodiment and as described previously herein in conjunction withFIG.63A, CUDA source code6310includes, without limitation, any number (including zero) of global functions6312, any number (including zero) of device functions6314, any number (including zero) of host functions6316, and any number (including zero) of host/device functions6318. In at least one embodiment, CUDA source code6310also includes, without limitation, any number of calls to any number of functions that are specified in any number of CUDA APIs.

In at least one embodiment, CUDA to HIP translation tool6320translates CUDA source code6310to HIP source code6330. In at least one embodiment, CUDA to HIP translation tool6320converts each kernel call in CUDA source code6310from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in CUDA source code6310to any number of other functionally similar HIP calls.

In at least one embodiment, HIP compiler driver6340determines that target device6346is CUDA-enabled and generates HIP/NVCC compilation command6342. In at least one embodiment, HIP compiler driver6340then configures CUDA compiler6350via HIP/NVCC compilation command6342to compile HIP source code6330. In at least one embodiment, HIP compiler driver6340provides access to a HIP to CUDA translation header6352as part of configuring CUDA compiler6350. In at least one embodiment, HIP to CUDA translation header6352translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs to any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, CUDA compiler6350uses HIP to CUDA translation header6352in conjunction with a CUDA runtime library6354corresponding to CUDA runtime API6302to generate host executable code6370(1) and CUDA device executable code6384. In at least one embodiment, host executable code6370(1) and CUDA device executable code6384may then be executed on, respectively, CPU6390and CUDA-enabled GPU6394. In at least one embodiment, CUDA device executable code6384includes, without limitation, binary code. In at least one embodiment, CUDA device executable code6384includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime.

In at least one embodiment, at least one element of system6304is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.63Cillustrates a system6306configured to compile and execute CUDA source code6310ofFIG.63Ausing CPU6390and non-CUDA-enabled GPU6392, in accordance with at least one embodiment. In at least one embodiment, system6306includes, without limitation, CUDA source code6310, CUDA to HIP translation tool6320, HIP source code6330, HIP compiler driver6340, HCC6360, host executable code6370(2), HCC device executable code6382, CPU6390, and GPU6392.

In at least one embodiment and as described previously herein in conjunction withFIG.63A, CUDA source code6310includes, without limitation, any number (including zero) of global functions6312, any number (including zero) of device functions6314, any number (including zero) of host functions6316, and any number (including zero) of host/device functions6318. In at least one embodiment, CUDA source code6310also includes, without limitation, any number of calls to any number of functions that are specified in any number of CUDA APIs.

In at least one embodiment, CUDA to HIP translation tool6320translates CUDA source code6310to HIP source code6330. In at least one embodiment, CUDA to HIP translation tool6320converts each kernel call in CUDA source code6310from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in source code6310to any number of other functionally similar HIP calls.

In at least one embodiment, HIP compiler driver6340subsequently determines that target device6346is not CUDA-enabled and generates HIP/HCC compilation command6344. In at least one embodiment, HIP compiler driver6340then configures HCC6360to execute HIP/HCC compilation command6344to compile HIP source code6330. In at least one embodiment, HIP/HCC compilation command6344configures HCC6360to use, without limitation, a HIP/HCC runtime library6358and an HCC header6356to generate host executable code6370(2) and HCC device executable code6382. In at least one embodiment, HIP/HCC runtime library6358corresponds to HIP runtime API6332. In at least one embodiment, HCC header6356includes, without limitation, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, host executable code6370(2) and HCC device executable code6382may be executed on, respectively, CPU6390and GPU6392.

In at least one embodiment, at least one element of system6306is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.64illustrates an exemplary kernel translated by CUDA-to-HIP translation tool6320ofFIG.63C, in accordance with at least one embodiment. In at least one embodiment, CUDA source code6310partitions an overall problem that a given kernel is designed to solve into relatively coarse sub-problems that can independently be solved using thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads. In at least one embodiment, each sub-problem is partitioned into relatively fine pieces that can be solved cooperatively in parallel by threads within a thread block. In at least one embodiment, threads within a thread block can cooperate by sharing data through shared memory and by synchronizing execution to coordinate memory accesses.

In at least one embodiment, CUDA source code6310organizes thread blocks associated with a given kernel into a one-dimensional, a two-dimensional, or a three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads, and a grid includes, without limitation, any number of thread blocks.

In at least one embodiment, a kernel is a function in device code that is defined using a “_global_” declaration specifier. In at least one embodiment, the dimension of a grid that executes a kernel for a given kernel call and associated streams are specified using a CUDA kernel launch syntax6410. In at least one embodiment, CUDA kernel launch syntax6410is specified as “KernelName<<<GridSize, BlockSize, SharedMemorySize, Stream>>>(KernelArguments);”. In at least one embodiment, an execution configuration syntax is a “<<< . . . >>>” construct that is inserted between a kernel name (“KernelName”) and a parenthesized list of kernel arguments (“KernelArguments”). In at least one embodiment, CUDA kernel launch syntax6410includes, without limitation, a CUDA launch function syntax instead of an execution configuration syntax.

In at least one embodiment, “GridSize” is of a type dim3 and specifies the dimension and size of a grid. In at least one embodiment, type dim3 is a CUDA-defined structure that includes, without limitation, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, then z defaults to one. In at least one embodiment, if y is not specified, then y defaults to one. In at least one embodiment, the number of thread blocks in a grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, “BlockSize” is of type dim3 and specifies the dimension and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread that executes a kernel is given a unique thread ID that is accessible within the kernel through a built-in variable (e.g., “threadIdx”).

In at least one embodiment and with respect to CUDA kernel launch syntax6410, “SharedMemorySize” is an optional argument that specifies a number of bytes in a shared memory that is dynamically allocated per thread block for a given kernel call in addition to statically allocated memory. In at least one embodiment and with respect to CUDA kernel launch syntax6410, SharedMemorySize defaults to zero. In at least one embodiment and with respect to CUDA kernel launch syntax6410, “Stream” is an optional argument that specifies an associated stream and defaults to zero to specify a default stream. In at least one embodiment, a stream is a sequence of commands (possibly issued by different host threads) that execute in order. In at least one embodiment, different streams may execute commands out of order with respect to one another or concurrently.

In at least one embodiment, CUDA source code6310includes, without limitation, a kernel definition for an exemplary kernel “MatAdd” and a main function. In at least one embodiment, main function is host code that executes on a host and includes, without limitation, a kernel call that causes kernel MatAdd to execute on a device. In at least one embodiment and as shown, kernel MatAdd adds two matrices A and B of size N×N, where N is a positive integer, and stores the result in a matrix C. In at least one embodiment, main function defines a threadsPerBlock variable as 16 by 16 and a numBlocks variable as N/16 by N/16. In at least one embodiment, main function then specifies kernel call “MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);”. In at least one embodiment and as per CUDA kernel launch syntax6410, kernel MatAdd is executed using a grid of thread blocks having a dimension N/16 by N/16, where each thread block has a dimension of 16 by 16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in such a grid executes kernel MatAdd to perform one pair-wise addition.

In at least one embodiment, while translating CUDA source code6310to HIP source code6330, CUDA to HIP translation tool6320translates each kernel call in CUDA source code6310from CUDA kernel launch syntax6410to a HIP kernel launch syntax6420and converts any number of other CUDA calls in source code6310to any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax6420is specified as “hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemory Size, Stream, KernelArguments);”. In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel launch syntax6420as in CUDA kernel launch syntax6410(described previously herein). In at least one embodiment, arguments SharedMemorySize and Stream are required in HIP kernel launch syntax6420and are optional in CUDA kernel launch syntax6410.

In at least one embodiment, a portion of HIP source code6330depicted inFIG.64is identical to a portion of CUDA source code6310depicted inFIG.64except for a kernel call that causes kernel MatAdd to execute on a device. In at least one embodiment, kernel MatAdd is defined in HIP source code6330with the same “_global_” declaration specifier with which kernel MatAdd is defined in CUDA source code6310. In at least one embodiment, a kernel call in HIP source code6330is “hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);”, while a corresponding kernel call in CUDA source code6310is “MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);”.

In at least one embodiment, at least one component shown or described with respect toFIG.64is used to implement techniques and/or functions described in connection withFIGS.1-35. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface to indicate two or more blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface to determine which of two or more blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface comprising one or more parameters to cause a scheduling policy of one or more blocks of one or more threads to be performed. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface comprising one or more parameters to indicate a scheduling policy of one or more blocks of one or more threads. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface to indicate a maximum number of blocks of threads capable of being scheduled in parallel. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface comprising one or more parameters to indicate one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface to indicate a maximum number of blocks of threads to be scheduled in parallel. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface comprising one or more parameters to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform an application programming interface to cause memory to be shared between two or more groups of blocks of threads.

In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool6420, or HIP Source Code6430is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.65illustrates non-CUDA-enabled GPU6392ofFIG.63Cin greater detail, in accordance with at least one embodiment. In at least one embodiment, GPU6392is developed by AMD corporation of Santa Clara. In at least one embodiment, GPU6392can be configured to perform compute operations in a highly-parallel fashion. In at least one embodiment, GPU6392is configured to execute graphics pipeline operations such as draw commands, pixel operations, geometric computations, and other operations associated with rendering an image to a display. In at least one embodiment, GPU6392is configured to execute operations unrelated to graphics. In at least one embodiment, GPU6392is configured to execute both operations related to graphics and operations unrelated to graphics. In at least one embodiment, GPU6392can be configured to execute device code included in HIP source code6330.

In at least one embodiment, GPU6392includes, without limitation, any number of programmable processing units6520, a command processor6510, an L2 cache6522, memory controllers6570, DMA engines6580(1), system memory controllers6582, DMA engines6580(2), and GPU controllers6584. In at least one embodiment, each programmable processing unit6520includes, without limitation, a workload manager6530and any number of compute units6540. In at least one embodiment, command processor6510reads commands from one or more command queues (not shown) and distributes commands to workload managers6530. In at least one embodiment, for each programmable processing unit6520, associated workload manager6530distributes work to compute units6540included in programmable processing unit6520. In at least one embodiment, each compute unit6540may execute any number of thread blocks, but each thread block executes on a single compute unit6540. In at least one embodiment, a workgroup is a thread block.

In at least one embodiment, each compute unit6540includes, without limitation, any number of SIMD units6550and a shared memory6560. In at least one embodiment, each SIMD unit6550implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit6550includes, without limitation, a vector ALU6552and a vector register file6554. In at least one embodiment, each SIMD unit6550executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize together and communicate via shared memory6560.

In at least one embodiment, programmable processing units6520are referred to as “shader engines.” In at least one embodiment, each programmable processing unit6520includes, without limitation, any amount of dedicated graphics hardware in addition to compute units6540. In at least one embodiment, each programmable processing unit6520includes, without limitation, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of render back ends, workload manager6530, and any number of compute units6540.

In at least one embodiment, compute units6540share L2 cache6522. In at least one embodiment, L2 cache6522is partitioned. In at least one embodiment, a GPU memory6590is accessible by all compute units6540in GPU6392. In at least one embodiment, memory controllers6570and system memory controllers6582facilitate data transfers between GPU6392and a host, and DMA engines6580(1) enable asynchronous memory transfers between GPU6392and such a host. In at least one embodiment, memory controllers6570and GPU controllers6584facilitate data transfers between GPU6392and other GPUs6392, and DMA engines6580(2) enable asynchronous memory transfers between GPU6392and other GPUs6392.

In at least one embodiment, GPU6392includes, without limitation, any amount and type of system interconnect that facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be internal or external to GPU6392. In at least one embodiment, GPU6392includes, without limitation, any number and type of I/O interfaces (e.g., PCIe) that are coupled to any number and type of peripheral devices. In at least one embodiment, GPU6392may include, without limitation, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU6392implements a memory subsystem that includes, without limitation, any amount and type of memory controllers (e.g., memory controllers6570and system memory controllers6582) and memory devices (e.g., shared memories6560) that may be dedicated to one component or shared among multiple components. In at least one embodiment, GPU6392implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache6522) that may each be private to or shared between any number of components (e.g., SIMD units6550, compute units6540, and programmable processing units6520).

In at least one embodiment, at least one component shown or described with respect toFIG.65is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.66illustrates how threads of an exemplary CUDA grid6620are mapped to different compute units6540ofFIG.65, in accordance with at least one embodiment. In at least one embodiment and for explanatory purposes only, grid6620has a GridSize of BX by BY by 1 and a BlockSize of TX by TY by 1. In at least one embodiment, grid6620therefore includes, without limitation, (BX*BY) thread blocks6630and each thread block6630includes, without limitation, (TX*TY) threads6640. Threads6640are depicted inFIG.66as squiggly arrows.

In at least one embodiment, grid6620is mapped to programmable processing unit6520(1) that includes, without limitation, compute units6540(1)-6540(C). In at least one embodiment and as shown, (BJ*BY) thread blocks6630are mapped to compute unit6540(1), and the remaining thread blocks6630are mapped to compute unit6540(2). In at least one embodiment, each thread block6630may include, without limitation, any number of warps, and each warp is mapped to a different SIMD unit6550ofFIG.65.

In at least one embodiment, warps in a given thread block6630may synchronize together and communicate through shared memory6560included in associated compute unit6540. For example and in at least one embodiment, warps in thread block6630(BJ,1) can synchronize together and communicate through shared memory6560(1). For example and in at least one embodiment, warps in thread block6630(BJ+1,1) can synchronize together and communicate through shared memory6560(2).

In at least one embodiment, at least one thread of exemplary CUDA grid6620is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

FIG.67illustrates how to migrate existing CUDA code to Data Parallel C++ code, in accordance with at least one embodiment. Data Parallel C++ (DPC++) may refer to an open, standards-based alternative to single-architecture proprietary languages that allows developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and also perform custom tuning for a specific accelerator. DPC++ use similar and/or identical C and C++ constructs in accordance with ISO C++ which developers may be familiar with. DPC++ incorporates standard SYCL from The Khronos Group to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer that builds on underlying concepts, portability and efficiency of OpenCL that enables code for heterogeneous processors to be written in a “single-source” style using standard C++. SYCL may enable single source development where C++ template functions can contain both host and device code to construct complex algorithms that use OpenCL acceleration, and then re-use them throughout their source code on different types of data.

In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code which can be deployed across diverse hardware targets. In at least one embodiment, a DPC++ compiler is used to generate DPC++ applications that can be deployed across diverse hardware targets and a DPC++ compatibility tool can be used to migrate CUDA applications to a multiplatform program in DPC++. In at least one embodiment, a DPC++ base tool kit includes a DPC++ compiler to deploy applications across diverse hardware targets; a DPC++ library to increase productivity and performance across CPUs, GPUs, and FPGAs; a DPC++ compatibility tool to migrate CUDA applications to multi-platform applications; and any suitable combination thereof.

In at least one embodiment, a DPC++ programming model is utilized to simply one or more aspects relating to programming CPUs and accelerators by using modern C++ features to express parallelism with a programming language called Data Parallel C++. DPC++ programming language may be utilized to code reuse for hosts (e.g., a CPU) and accelerators (e.g., a GPU or FPGA) using a single source language, with execution and memory dependencies being clearly communicated. Mappings within DPC++ code can be used to transition an application to run on a hardware or set of hardware devices that best accelerates a workload. A host may be available to simplify development and debugging of device code, even on platforms that do not have an accelerator available.

In at least one embodiment, CUDA source code6700is provided as an input to a DPC++ compatibility tool6702to generate human readable DPC++6704. In at least one embodiment, human readable DPC++6704includes inline comments generated by DPC++ compatibility tool6702that guides a developer on how and/or where to modify DPC++ code to complete coding and tuning to desired performance6706, thereby generating DPC++ source code6708.

In at least one embodiment, CUDA source code6700is or includes a collection of human-readable source code in a CUDA programming language. In at least one embodiment, CUDA source code6700is human-readable source code in a CUDA programming language. In at least one embodiment, a CUDA programming language is an extension of the C++ programming language that includes, without limitation, mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, device code is source code that, after compilation, is executable on a device (e.g., GPU or FPGA) and may include or more parallelizable workflows that can be executed on one or more processor cores of a device. In at least one embodiment, a device may be a processor that is optimized for parallel instruction processing, such as CUDA-enabled GPU, GPU, or another GPGPU, etc. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In least one embodiment, some or all of host code and device code can be executed in parallel across a CPU and GPU/FPGA. In at least one embodiment, a host is a processor that is optimized for sequential instruction processing, such as CPU. CUDA source code6700described in connection withFIG.67may be in accordance with those discussed elsewhere in this document.

In at least one embodiment, DPC++ compatibility tool6702refers to an executable tool, program, application, or any other suitable type of tool that is used to facilitate migration of CUDA source code6700to DPC++ source code6708. In at least one embodiment, DPC++ compatibility tool6702is a command-line-based code migration tool available as part of a DPC++ tool kit that is used to port existing CUDA sources to DPC++. In at least one embodiment, DPC++ compatibility tool6702converts some or all source code of a CUDA application from CUDA to DPC++ and generates a resulting file that is written at least partially in DPC++, referred to as human readable DPC++6704. In at least one embodiment, human readable DPC++6704includes comments that are generated by DPC++ compatibility tool6702to indicate where user intervention may be necessary. In at least one embodiment, user intervention is necessary when CUDA source code6700calls a CUDA API that has no analogous DPC++ API; other examples where user intervention is required are discussed later in greater detail.

In at least one embodiment, a workflow for migrating CUDA source code6700(e.g., application or portion thereof) includes creating one or more compilation database files; migrating CUDA to DPC++ using a DPC++ compatibility tool6702; completing migration and verifying correctness, thereby generating DPC++ source code6708; and compiling DPC++ source code6708with a DPC++ compiler to generate a DPC++ application. In at least one embodiment, a compatibility tool provides a utility that intercepts commands used when Makefile executes and stores them in a compilation database file. In at least one embodiment, a file is stored in JSON format. In at least one embodiment, an intercept-built command converts Makefile command to a DPC compatibility command.

In at least one embodiment, intercept-build is a utility script that intercepts a build process to capture compilation options, macro defs, and include paths, and writes this data to a compilation database file. In at least one embodiment, a compilation database file is a JSON file. In at least one embodiment, DPC++ compatibility tool6702parses a compilation database and applies options when migrating input sources. In at least one embodiment, use of intercept-build is optional, but highly recommended for Make or CMake based environments. In at least one embodiment, a migration database includes commands, directories, and files: command may include necessary compilation flags; directory may include paths to header files; file may include paths to CUDA files.

In at least one embodiment, DPC++ compatibility tool6702migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ wherever possible. In at least one embodiment, DPC++ compatibility tool6702is available as part of a tool kit. In at least one embodiment, a DPC++ tool kit includes an intercept-build tool. In at least one embodiment, an intercept-built tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, a compilation database generated by an intercept-built tool is used by DPC++ compatibility tool6702to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, DPC++ compatibility tool6702generates human readable DPC++6704which may be DPC++ code that, as generated by DPC++ compatibility tool6702, cannot be compiled by DPC++ compiler and requires additional plumbing for verifying portions of code that were not migrated correctly, and may involve manual intervention, such as by a developer. In at least one embodiment, DPC++ compatibility tool6702provides hints or tools embedded in code to help developers manually migrate additional code that could not be migrated automatically. In at least one embodiment, migration is a one-time activity for a source file, project, or application.

In at least one embodiment, DPC++ compatibility tool67002is able to successfully migrate all portions of CUDA code to DPC++ and there may simply be an optional step for manually verifying and tuning performance of DPC++ source code that was generated. In at least one embodiment, DPC++ compatibility tool6702directly generates DPC++ source code6708which is compiled by a DPC++ compiler without requiring or utilizing human intervention to modify DPC++ code generated by DPC++ compatibility tool6702. In at least one embodiment, DPC++ compatibility tool generates compile-able DPC++ code which can be optionally tuned by a developer for performance, readability, maintainability, other various considerations; or any combination thereof.

In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files at least partially using DPC++ compatibility tool6702. In at least one embodiment, CUDA source code includes one or more header files which may include CUDA header files. In at least one embodiment, a CUDA source file includes a <cuda.h> header file and a <stdio.h> header file which can be used to print text. In at least one embodiment, a portion of a vector addition kernel CUDA source file may be written as or related to:

In at least one embodiment and in connection with CUDA source file presented above, DPC++ compatibility tool6702parses a CUDA source code and replaces header files with appropriate DPC++ and SYCL header files. In at least one embodiment, DPC++ header files includes helper declarations. In CUDA, there is a concept of a thread ID and correspondingly, in DPC++ or SYCL, for each element there is a local identifier.

In at least one embodiment and in connection with CUDA source file presented above, there are two vectors A and B which are initialized and a vector addition result is put into vector C as part of VectorAddKernel( ). In at least one embodiment, DPC++ compatibility tool6702converts CUDA thread IDs used to index work elements to SYCL standard addressing for work elements via a local ID as part of migrating CUDA code to DPC++ code. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool6702can be optimized—for example, by reducing dimensionality of an nd_item, thereby increasing memory and/or processor utilization.

In at least one embodiment and in connection with CUDA source file presented above, memory allocation is migrated. In at least one embodiment, cudaMalloc( ) is migrated to a unified shared memory SYCL call malloc_device( ) to which a device and context is passed, relying on SYCL concepts such as platform, device, context, and queue. In at least one embodiment, a SYCL platform can have multiple devices (e.g., host and GPU devices); a device may have multiple queues to which jobs can be submitted; each device may have a context; and a context may have multiple devices and manage shared memory objects.

In at least one embodiment and in connection with CUDA source file presented above, a main( ) function invokes or calls VectorAddKernel( ) to add two vectors A and B together and store result in vector C. In at least one embodiment, CUDA code to invoke VectorAddKernel( ) is replaced by DPC++ code to submit a kernel to a command queue for execution. In at least one embodiment, a command group handler cgh passes data, synchronization, and computation that is submitted to the queue, parallel_for is called for a number of global elements and a number of work items in that work group where VectorAddKernel( ) is called.

In at least one embodiment and in connection with CUDA source file presented above, CUDA calls to copy device memory and then free memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating point variables) is migrated as is, without being modified by DPC++ compatibility tool6702. In at least one embodiment, DPC++ compatibility tool6702modify CUDA APIs for memory setup and/or host calls to execute kernel on the acceleration device. In at least one embodiment and in connection with CUDA source file presented above, a corresponding human readable DPC++6704(e.g., which can be compiled) is written as or related to:

In at least one embodiment, human readable DPC++6704refers to output generated by DPC++ compatibility tool6702and may be optimized in one manner or another. In at least one embodiment, human readable DPC++6704generated by DPC++ compatibility tool6702can be manually edited by a developer after migration to make it more maintainable, performance, or other considerations. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool67002such as DPC++ disclosed can be optimized by removing repeat calls to get_current_device( ) and/or get_default_context( ) for each malloc_device( ) call. In at least one embodiment, DPC++ code generated above uses a 3 dimensional nd range which can be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, a developer can manually edit DPC++ code generated by DPC++ compatibility tool6702replace uses of unified shared memory with accessors. In at least one embodiment, DPC++ compatibility tool6702has an option to change how it migrates CUDA code to DPC++ code. In at least one embodiment, DPC++ compatibility tool6702is verbose because it is using a general template to migrate CUDA code to DPC++ code that works for a large number of cases.

In at least one embodiment, a CUDA to DPC++ migration workflow includes steps to: prepare for migration using intercept-build script; perform migration of CUDA projects to DPC++ using DPC++ compatibility tool6702; review and edit migrated source files manually for completion and correctness; and compile final DPC++ code to generate a DPC++ application. In at least one embodiment, manual review of DPC++ source code may be required in one or more scenarios including but not limited to: migrated API does not return error code (CUDA code can return an error code which can then be consumed by the application but SYCL uses exceptions to report errors, and therefore does not use error codes to surface errors); CUDA compute capability dependent logic is not supported by DPC++; statement could not be removed. In at least one embodiment, scenarios in which DPC++ code requires manual intervention may include, without limitation: error code logic replaced with (*,0) code or commented out; equivalent DPC++ API not available; CUDA compute capability-dependent logic; hardware-dependent API (clock( )); missing features unsupported API; execution time measurement logic; handling built-in vector type conflicts; migration of cuBLAS API; and more.

In at least one embodiment, one or more techniques described herein utilize a oneAPI programming model. In at least one embodiment, a oneAPI programming model refers to a programming model for interacting with various compute accelerator architectures. In at least one embodiment, oneAPI refers to an application programming interface (API) designed to interact with various compute accelerator architectures. In at least one embodiment, a oneAPI programming model utilizes a DPC++ programming language. In at least one embodiment, a DPC++ programming language refers to a high-level language for data parallel programming productivity. In at least one embodiment, a DPC++ programming language is based at least in part on C and/or C++ programming languages. In at least one embodiment, a oneAPI programming model is a programming model such as those developed by Intel Corporation of Santa Clara, CA.

In at least one embodiment, oneAPI and/or oneAPI programming model is utilized to interact with various accelerator, GPU, processor, and/or variations thereof, architectures. In at least one embodiment, oneAPI includes a set of libraries that implement various functionalities. In at least one embodiment, oneAPI includes at least a oneAPI DPC++ library, a oneAPI math kernel library, a oneAPI data analytics library, a oneAPI deep neural network library, a oneAPI collective communications library, a oneAPI threading building blocks library, a oneAPI video processing library, and/or variations thereof.

In at least one embodiment, a oneAPI DPC++ library, also referred to as oneDPL, is a library that implements algorithms and functions to accelerate DPC++ kernel programming. In at least one embodiment, oneDPL implements one or more standard template library (STL) functions. In at least one embodiment, oneDPL implements one or more parallel STL functions. In at least one embodiment, oneDPL provides a set of library classes and functions such as parallel algorithms, iterators, function object classes, range-based API, and/or variations thereof. In at least one embodiment, oneDPL implements one or more classes and/or functions of a C++ standard library. In at least one embodiment, oneDPL implements one or more random number generator functions.

In at least one embodiment, a oneAPI math kernel library, also referred to as oneMKL, is a library that implements various optimized and parallelized routines for various mathematical functions and/or operations. In at least one embodiment, oneMKL implements one or more basic linear algebra subprograms (BLAS) and/or linear algebra package (LAPACK) dense linear algebra routines. In at least one embodiment, oneMKL implements one or more sparse BLAS linear algebra routines. In at least one embodiment, oneMKL implements one or more random number generators (RNGs). In at least one embodiment, oneMKL implements one or more vector mathematics (VM) routines for mathematical operations on vectors. In at least one embodiment, oneMKL implements one or more Fast Fourier Transform (FFT) functions.

In at least one embodiment, a oneAPI data analytics library, also referred to as oneDAL, is a library that implements various data analysis applications and distributed computations. In at least one embodiment, oneDAL implements various algorithms for preprocessing, transformation, analysis, modeling, validation, and decision making for data analytics, in batch, online, and distributed processing modes of computation. In at least one embodiment, oneDAL implements various C++ and/or Java APIs and various connectors to one or more data sources. In at least one embodiment, oneDAL implements DPC++ API extensions to a traditional C++ interface and enables GPU usage for various algorithms.

In at least one embodiment, a oneAPI deep neural network library, also referred to as oneDNN, is a library that implements various deep learning functions. In at least one embodiment, oneDNN implements various neural network, machine learning, and deep learning functions, algorithms, and/or variations thereof.

In at least one embodiment, a oneAPI collective communications library, also referred to as oneCCL, is a library that implements various applications for deep learning and machine learning workloads. In at least one embodiment, oneCCL is built upon lower-level communication middleware, such as message passing interface (MPI) and libfabrics. In at least one embodiment, oneCCL enables a set of deep learning specific optimizations, such as prioritization, persistent operations, out of order executions, and/or variations thereof. In at least one embodiment, oneCCL implements various CPU and GPU functions.

In at least one embodiment, a oneAPI threading building blocks library, also referred to as oneTBB, is a library that implements various parallelized processes for various applications. In at least one embodiment, oneTBB is utilized for task-based, shared parallel programming on a host. In at least one embodiment, oneTBB implements generic parallel algorithms. In at least one embodiment, oneTBB implements concurrent containers. In at least one embodiment, oneTBB implements a scalable memory allocator. In at least one embodiment, oneTBB implements a work-stealing task scheduler. In at least one embodiment, oneTBB implements low-level synchronization primitives. In at least one embodiment, oneTBB is compiler-independent and usable on various processors, such as GPUs, PPUs, CPUs, and/or variations thereof.

In at least one embodiment, a oneAPI video processing library, also referred to as oneVPL, is a library that is utilized for accelerating video processing in one or more applications. In at least one embodiment, oneVPL implements various video decoding, encoding, and processing functions. In at least one embodiment, oneVPL implements various functions for media pipelines on CPUs, GPUs, and other accelerators. In at least one embodiment, oneVPL implements device discovery and selection in media centric and video analytics workloads. In at least one embodiment, oneVPL implements API primitives for zero-copy buffer sharing.

In at least one embodiment, a oneAPI programming model utilizes a DPC++ programming language. In at least one embodiment, a DPC++ programming language is a programming language that includes, without limitation, functionally similar versions of CUDA mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, a DPC++ programming language may include a subset of functionality of a CUDA programming language. In at least one embodiment, one or more CUDA programming model operations are performed using a oneAPI programming model using a DPC++ programming language.

In at least one embodiment at least one component shown or described with respect toFIG.67is used to perform at least one aspect described with respect to example computer system100, example diagram200, example diagram300, example diagram400, example diagram500, example process600, example diagram700, example application programming interface800, example application programming interface900, example diagram1000, example diagram1100, example application programming interface1200, example application programming interface1300, example computer system1400, example application programming interface1500, example diagram1600, example application programming interface1700, example computer system1800, example application programming interface1900, example computer system2000, example application programming interface2100, example diagram2200, example diagram2300, example diagram2400, example diagram2500, example application programming interface2600, example diagram2700, example diagram2800, example diagram2900, example application programming interface3000, example application programming interface3100, example application programming interface3200, example diagram3300, example application programming interface3400, example software stack3500, and/or other systems, methods, or operations described herein.

It should be noted that, while example embodiments described herein may relate to a CUDA programming model, techniques described herein can be utilized with any suitable programming model, such HIP, oneAPI (e.g., using oneAPI-based programming to perform or implement a method disclosed herein), and/or variations thereof.

In at least one embodiment, one or more components of systems and/or processors disclosed above can communicate with one or more CPUs, ASICs, GPUs, FPGAs, or other hardware, circuitry, or integrated circuit components that include, e.g., an upscaler or upsampler to upscale an image, an image blender or image blender component to blend, mix, or add images together, a sampler to sample an image (e.g., as part of a DSP), a neural network circuit that is configured to perform an upscaler to upscale an image (e.g., from a low resolution image to a high resolution image), or other hardware to modify or generate an image, frame, or video to adjust its resolution, size, or pixels; one or more components of systems and/or processors disclosed above can use components described in this disclosure to perform methods, operations, or instructions that generate or modify an image.

At least one embodiment of the disclosure can be described in view of the following clauses:1. A processor comprising:one or more circuits to perform an application programming interface (API) to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction.2. The processor of clause 1, wherein the two or more bocks of threads are in a group of multiple groups of blocks of threads of a software kernel.3. The processor of clause 1 or 2, wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads.4. The processor of any of clauses 1-3, wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads, the partitioning comprising multiple partitions.5. The processor of any of clauses 1-4, wherein the barrier instruction is in each thread within the two or more blocks of threads.6. The processor of any of clauses 1-5, wherein the two or more blocks of threads are of a grid of blocks of threads, wherein each thread of the two or more blocks of threads are to have performance stopped until all threads of the two or more blocks of threads have performed the barrier instruction, and wherein the grid of blocks of threads comprises at least one thread whose performance is not dependent on whether any threads of the two or more blocks of threads have performed the barrier instruction.7. The processor of any of clauses 1-6, wherein the barrier instruction prevents performance of one or more instruction until a condition has been satisfied, the condition based, at least in part, on performance of the barrier instruction by each thread of the two or more blocks of threads.8. The processor of any of clauses 1-7, wherein the API is further to cause performance of the one or more threads to stop until a condition is satisfied.9. The processor of any of clauses 1-8, wherein the API is further to cause performance of the one or more threads to stop until all threads in the group of blocks have performed the barrier instruction.10. A computer-implemented method comprising:performing an application programming interface (API) to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction.11. The computer-implemented method of clause 10, wherein the two or more bocks of threads are in a group of multiple groups of blocks of threads of a software kernel.12. The computer-implemented method of clause 10 or 11, wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads.13. The computer-implemented method of any of clauses 10-12, wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads, the partitioning comprising multiple partitions.14. The computer-implemented method of any of clauses 10-13, wherein the barrier instruction is in each thread within the two or more blocks of threads.15. The computer-implemented method of any of clauses 10-14, wherein the two or more blocks of threads are of a grid of blocks of threads, wherein each thread of the two or more blocks of threads are to have performance stopped until all threads of the two or more blocks of threads have performed the barrier instruction, and wherein the grid of blocks of threads comprises at least one thread whose performance is not dependent on whether any threads of the two or more blocks of threads have performed the barrier instruction.16. The computer-implemented method of any of clauses 10-15, wherein the barrier instruction prevents performance of one or more instruction until a condition has been satisfied, the condition based, at least in part, on performance of the barrier instruction by each thread of the two or more blocks of threads.17. The computer-implemented method of any of clauses 10-16, wherein the API is further to cause performance of the one or more threads to stop until a condition is satisfied.18. The computer-implemented method of any of clauses 10-17, wherein the API is further to cause performance of the one or more threads to stop until all threads in the group of blocks have performed the barrier instruction.19. A computer system comprising:one or more processors and memory storing executable instructions that, if performed by the one or more processors, are to perform an application programming interface (API) to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction.20. The computer system of clause 19, wherein the two or more bocks of threads are in a group of multiple groups of blocks of threads of a software kernel.21. The computer system of clause 19 or 20, wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads.22. The computer system of any of clauses 19-21, wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads, the partitioning comprising multiple partitions.23. The computer system of any of clauses 19-22, wherein the barrier instruction is in each thread within the two or more blocks of threads.24. The computer system of any of clauses 19-23, wherein the two or more blocks of threads are of a grid of blocks of threads, wherein each thread of the two or more blocks of threads are to have performance stopped until all threads of the two or more blocks of threads have performed the barrier instruction, and wherein the grid of blocks of threads comprises at least one thread whose performance is not dependent on whether any threads of the two or more blocks of threads have performed the barrier instruction.25. The computer system of any of clauses 19-24, wherein the barrier instruction prevents performance of one or more instruction until a condition has been satisfied, the condition based, at least in part, on performance of the barrier instruction by each thread of the two or more blocks of threads.26. The computer system of any of clauses 19-25, wherein the API is further to cause performance of the one or more threads to stop until a condition is satisfied.27. The computer system of any of clauses 19-26, wherein the API is further to cause performance of the one or more threads to stop until all threads in the group of blocks have performed the barrier instruction.28. A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, are to perform an application programming interface (API) to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction.29. The machine-readable medium of clause 28, wherein the two or more bocks of threads are in a group of multiple groups of blocks of threads of a software kernel.30. The machine-readable medium of clause 28 or 29, wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads.31. The machine-readable medium of any of clauses 28-30, wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads, the partitioning comprising multiple partitions.32. The machine-readable medium of any of clauses 28-31, wherein the barrier instruction is in each thread within the two or more blocks of threads.33. The machine-readable medium of any of clauses 28-32, wherein the two or more blocks of threads are of a grid of blocks of threads, wherein each thread of the two or more blocks of threads are to have performance stopped until all threads of the two or more blocks of threads have performed the barrier instruction, and wherein the grid of blocks of threads comprises at least one thread whose performance is not dependent on whether any threads of the two or more blocks of threads have performed the barrier instruction.34. The machine-readable medium of any of clauses 28-33, wherein the barrier instruction prevents performance of one or more instruction until a condition has been satisfied, the condition based, at least in part, on performance of the barrier instruction by each thread of the two or more blocks of threads.35. The machine-readable medium of any of clauses 28-34, wherein the API is further to cause performance of the one or more threads to stop until a condition is satisfied.36. The machine-readable medium of any of clauses 28-35, wherein the API is further to cause performance of the one or more threads to stop until all threads in the group of blocks have performed the barrier instruction.

In at least one embodiment, an arithmetic logic unit is a set of combinational logic circuitry that takes one or more inputs to produce a result. In at least one embodiment, an arithmetic logic unit is used by a processor to implement mathematical operation such as addition, subtraction, or multiplication. In at least one embodiment, an arithmetic logic unit is used to implement logical operations such as logical AND/OR or XOR. In at least one embodiment, an arithmetic logic unit is stateless, and made from physical switching components such as semiconductor transistors arranged to form logical gates. In at least one embodiment, an arithmetic logic unit may operate internally as a stateful logic circuit with an associated clock. In at least one embodiment, an arithmetic logic unit may be constructed as an asynchronous logic circuit with an internal state not maintained in an associated register set. In at least one embodiment, an arithmetic logic unit is used by a processor to combine operands stored in one or more registers of the processor and produce an output that can be stored by the processor in another register or a memory location.

In at least one embodiment, as a result of processing an instruction retrieved by the processor, the processor presents one or more inputs or operands to an arithmetic logic unit, causing the arithmetic logic unit to produce a result based at least in part on an instruction code provided to inputs of the arithmetic logic unit. In at least one embodiment, the instruction codes provided by the processor to the ALU are based at least in part on the instruction executed by the processor. In at least one embodiment combinational logic in the ALU processes the inputs and produces an output which is placed on a bus within the processor. In at least one embodiment, the processor selects a destination register, memory location, output device, or output storage location on the output bus so that clocking the processor causes the results produced by the ALU to be sent to the desired location.