Load reduced memory module and memory system including the same

A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a memory module and a memory system including the same, and more particularly relates to a Load Reduced memory module and a memory system including the same.

2. Description of Related Art

A memory module such as a DIMM (Dual Inline Memory Module) has a configuration in which a large number of memory chips such as DRAMs (Dynamic Random Access Memories) are mounted on a module printed circuit board (PCB). Such a memory module is inserted in a memory slot provided on a motherboard, thereby a data transfer is performed between a memory controller and the memory module. In recent years, because a system requires a considerable amount of memory capacity, it is hard to provide the required memory capacity with a single memory module. Therefore, in most cases, the motherboard includes a plurality of memory slots, so that a plurality of memory modules can be mounted on the motherboard.

However, when a plurality of memory modules are mounted on a motherboard, a load capacity of a data line on the motherboard increases, resulting in a degradation of signal quality. Although it does not cause a serious problem when a data transfer rate between the memory controller and the memory module is relatively low, it may cause a serious problem that the data transfer cannot be performed in a proper manner due to the degradation of the signal quality when the data transfer rate increases to a certain level. In recent years, a data transfer rate as high as about 1.6 Gbps to 3.2 Gbps is required, and in order to realize such a high speed data transfer, it is necessary to reduce the load capacity of the data line on the motherboard to a sufficiently low level.

A so-called Fully Buffered memory module is known as a memory module in which the load capacity of the data line can be reduced (Japanese Patent Application Laid-open No. 2008-135597). In a write operation of the Fully Buffered memory module, a dedicated chip called an Advanced Memory Buffer (AMB) once receives all write data supplied from the memory controller, and then the AMB supplies the write data to a predetermined memory chip. A read operation is opposite to the write operation, in which all read data output from a memory chip is once supplied to the AMB, and then the read data is supplied from the AMB to the memory controller. As a result, because the memory controller does not experience the load capacity of each memory chip, the load capacity of the data line is considerably reduced.

However, because the AMB employed in the Fully Buffered memory module is a sophisticated chip, which is relatively expensive, it causes a problem that the cost of the memory module considerably increases. Further, because an interface between the memory controller and the AMB is different from a typical interface between the memory controller and the memory chip in the Fully Buffered memory module, it causes another problem that a conventional memory controller cannot be used as it is.

Because of such a background, a memory module called a Load Reduced memory module has been recently proposed. The Load Reduced memory module is a memory module in which a register buffer is used instead of the AMB. Because the register buffer is a chip that only buffers signals such as data and command/address, it can be provided at low cost. In addition, because an interface between the memory controller and the register buffer has no difference from the typical interface between the memory controller and the memory chip in the Load Reduced memory module, the conventional memory controller can be used as it is.

However, from a result of extensive researches on the Load Reduced memory module by the present inventors, it has been found that, when the data transfer rate is considerably high, simply using a single register buffer is not sufficient to maintain the signal quality on the module PCB. To deal with this problem, the present inventors performed further researches on a Load Reduced memory module in which a considerably high data transfer rate can be realized. The present invention has been achieved as a result of such researches.

SUMMARY

In one embodiment, there is provided a memory module comprising: a circuit board including a plurality of data connectors and a plurality of command/address/control connectors; a plurality of memory chips mounted on the circuit board; a plurality of data register buffers mounted on the circuit board, each of the data register buffers being assigned to at least two memory chips; and a command/address/control register buffer mounted on the circuit board, wherein each of the data register buffers receives write data transferred via corresponding data connectors, outputs the write data to corresponding memory chips, receives read data transferred from the corresponding memory chips, and outputs the read data to the corresponding data connectors, the command/address/control register buffer includes a register circuit that receives a command/address/control signal supplied via the command/address/control connectors, and a control signal generating circuit that generates a control signal based on the command/address/control signal, the register circuit of the command/address/control register buffer supplies the command/address/control signal to the memory chips, and the control signal generating circuit of the command/address/control register buffer supplies the control signal to the data register buffers.

Further, in another embodiment, there is provided a memory system comprising a memory module and a memory controller, wherein the memory module includes: a circuit board including a plurality of data connectors and a plurality of command/address/control connectors electrically connected to the memory controller; a plurality of memory chips mounted on the circuit board; a plurality of data register buffers mounted on the circuit board, each of the data register buffers being assigned to at least two memory chips; and a command/address/control register buffer mounted on the circuit board, each of the data register buffers receives write data transferred from the memory controller via corresponding data connectors, outputs the write data to corresponding memory chips, and supplies read data transferred from the corresponding memory chips to the memory controller by receiving the read data and outputting the read data to the corresponding data connectors, the command/address/control register buffer includes a register circuit that receives a command/address/control signal supplied from the memory controller via the command/address/control connectors, and a control signal generating circuit that generates a control signal based on the command/address/control signal, the register circuit of the command/address/control register buffer supplies the command/address/control signal to the memory chips, and the control signal generating circuit of the command/address/control register buffer supplies the control signal to the data register buffers.

According to the present invention, because a plurality of data register buffers are mounted on a module PCB and a command/address/control register buffer is mounted on the module PCB separately from the data register buffers, a line length between a data register buffer and a memory chip is considerably shortened, as compared to a case that a single register buffer is used. This makes it possible to enhance the signal quality on the module PCB. As a result, it is possible to realize a considerably high data transfer rate.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a schematic diagram of a configuration of a memory module100according to an embodiment of the present invention.

As shown inFIG. 1, the memory module100according to the present embodiment includes a module PCB110, a plurality of memory chips200mounted on the module PCB110, a plurality of data register buffers300, and a command/address/control register buffer400.

In the present embodiment, the memory module100includes thirty-six memory chips200. When it is necessary to specify each of the memory chips, the memory chips are respectively represented by memory chips200-0to200-35. Furthermore, in the present embodiment, the memory module100includes nine data register buffers300. When it is necessary to specify each of the data register buffers, the data register buffers are respectively represented by data register buffers300-0to300-8. On the other hand, the command/address/control register buffer400is provided as a single unit. However, it is not essential to set the number of units of the command/address/control register buffer400to one, but two or more units of the command/address/control register buffer400can be mounted without any limitation.

The module PCB110is a printed circuit board that includes a multilayer wiring. The planar shape of the module PCB110is substantially rectangle, as shown inFIG. 1, with a long side in the X direction and a short side in the Y direction. On one side of the module PCB110along the X direction, which is the long side, a plurality of data connectors120and a plurality of command/address/control connectors130are provided. The data connectors120and the command/address/control connectors130are terminals for making an electrical connection with a memory controller via a memory slot, which will be described later.

The data connectors120are connectors for exchanging write data to be written in the memory chip200and read data read from the memory chip200between the memory module100and the memory controller. Although it is not particularly limited, the number of pins of the data connectors120is seventy two in the present embodiment. As shown inFIG. 1, among the seventy-two data connectors120, data connectors corresponding to the memory chips200-0to200-19are arranged in an area110athat is located substantially right below the memory chips200-0to200-19, and data connectors corresponding to the memory chips200-20to200-35are arranged in an area110bthat is located substantially right below the memory chips200-20to200-35.

The command/address/control connectors130are connectors for supplying a command signal, an address signal, a control signal, and a clock signal to be supplied to the command/address/control register buffer400. As shown inFIG. 1, the command/address/control connectors130are arranged in an area110cthat is located between the area110aand the area110b.

The memory chips200are, for example, DRAMs. The memory chips200-0,200-2, . . . with even branch numbers are mounted on one surface of the module PCB110(a first surface), and the memory chips200-1,200-3, . . . with odd branch numbers are mounted on the other surface of the module PCB110(a second surface). Two corresponding memory chips, for example, the memory chips200-0and200-1are mounted at positions facing each other across the module PCB110, respectively.

The memory module100according to the present embodiment has a so-called 4-Rank configuration. The number of Ranks indicates the number of memory spaces that can be selected in an exclusive manner. Although the same address is assigned to each of the Ranks, one of the Ranks is selected by exclusively activating a chip select (CS) signal or a clock enable (CKE) signal.

In the present embodiment, four memory chips200constitute a single group (a single set), and the four memory chips200constituting the single group belong to different Ranks from each other. For example, the memory chips200-0to200-3constitute a single group, and the memory chips200-0to200-3belong to different Ranks from each other.

As shown inFIG. 1, the four memory chips200constituting a single group are connected to one of the data register buffers300. For example, the group of the memory chips200-0to200-3is connected to the data register buffer300-0. Among the memory chips200-0to200-3, the memory chips200-0and200-1that are mounted on the upper side of the module PCB110are connected to the data register buffer300-0via a data line L1, and the memory chips200-2and200-3that are mounted on the lower side of the module PCB110are connected to the data register buffer300-0via a data line L2. An arrow of each of the data lines L1and L2shown inFIG. 1indicates a line of 1 byte (8 bits). Both the data lines L1and L2are formed inside the module PCB110.

An operation of the memory chip200is controlled based on the command signal, the address signal, the control signal, and the clock signal supplied from the command/address/control register buffer400. Details on the memory chip200will be described later.

A single data register buffer300is allocated for every four memory chips200, as described above, so that nine data register buffers300are arranged along the X direction, which is the long side. The data register buffer300is a chip for buffering write data that is transferred via a data line L0and outputting the write data to either one of the data lines L1and L2, and at the same time, buffering read data that is transferred via either one of the data lines L1and L2and outputting the read data to the data line L0. The data line L0is also formed inside the module PCB110.

With the above configuration, the single data register buffer300, the data connectors120and the four memory chips200corresponding to the data register buffer300constitute a group G. The memory chips200, the data register buffer300, and the data connectors120included in the same group are arranged along the Y direction, which is the short side, and a plurality of groups G formed in the above manner are arranged along the X direction, which is the long side. Therefore, a relative positional relationship between each of the data register buffers300and corresponding four memory chips200becomes constant in all the groups G.

With this arrangement, a line length of the data line L0can be shortened, and at the same time, the line length of the data line L0can be made substantially equal among the groups. Similarly, line lengths of the data lines L1and L2can be shortened, and at the same time, the line lengths of the data lines L1and L2can be made substantially equal among the groups.

An operation of the data register buffer300is controlled based on the control signal supplied from the command/address/control register buffer400. Details on the data register buffer300will be described later.

Only a single command/address/control register buffer400is mounted on the module PCB110. As shown inFIG. 1, the command/address/control register buffer400is arranged at an approximate center portion of the module PCB110in the X direction, which is the long side.

The command/address/control register buffer400receives the command signal, the address signal, the control signal, and the clock signal (in some cases, collectively referred to as a command/address/control signal and the like) that are supplied from the command/address/control connectors130through an input terminal401, buffers the signals, and supplies the signals to the memory chips200. At the same time, the command/address/control register buffer400generates a control signal. The command/address/control signal to be supplied to the memory chips200are output through an output terminal402, and the control signal to be supplied to the data register buffers300are output through an output terminal403.

The output terminal402is provided at each of the left side and the right side of the command/address/control register buffer400. For example, the output terminal402at the left side is commonly connected to the memory chips200-0to200-19except for a control signal that is used to select the Rank. That is, the command signal, the address signal, and the clock signal are commonly supplied to the memory chips200-0to200-19. Similarly, the output terminal403is provided at each of the left side and the right side of the command/address/control register buffer400. For example, the output terminal403at the left side is commonly connected to the data register buffers300-0to300-4, so that the generated control signal is commonly supplied to the data register buffers300-0to300-4.

In addition, on the module PCB110, a terminating resistor R1is provided at both edges in the X direction to prevent a reflection of the command/address signal and the control signal output from the command/address/control register buffer400. Furthermore, in order to prevent a reflection wave of the command/address/control signal that is input to the command/address/control register buffer400, a stub resistor R2is inserted on a command/address/control line L3that connects the command/address/control connectors130and the command/address/control register buffer400. Details on the command/address/control register buffer400will be described later.

FIG. 2is a block diagram of a configuration of an information processing system10including the memory module100according to the present embodiment.

The information processing system10shown inFIG. 2includes a CPU11, a memory control hub (MCH)12, and various devices that are connected to the CPU11via an interface controller hub (ICH)13.

The memory module100shown inFIG. 1and a graphic controller15are connected to the MCH12. As shown inFIG. 2, the memory module100and the MCH12constitute a memory system20, where the MCH12has a controller function for the memory module100. That is, the MCH12functions as a memory controller for the memory module100.

A storage device16, an I/O device17, and a BIOS (Basic Input/Output System)18are connected to the ICH13. The storage device16includes a magnetic drive such as a hard disk drive, an optical drive such as a CD-ROM drive, and the like. The I/O device17includes an input device such as a keyboard and a mouse, an output device such as a speaker, and a network device such as a modem and a LAN. The BIOS18is a kind of firmware that stores therein various pieces of basic information about the information processing system10, which is formed by a nonvolatile memory such as a flash memory.

FIG. 3is a perspective view of a part of a configuration of a motherboard21on which the memory system20is mounted.

As shown inFIG. 3, a memory slot22is provided on the motherboard21, so that the memory module100is inserted in the memory slot22. On the other hand, a memory controller12is directly mounted on the motherboard21. As described above, a plurality of memory chips200are mounted on the memory module100.

On a signal path between the memory controller12and the memory chips200, there exist a line23formed on the motherboard21and the data line L0and the command/address/control line L3formed on the module PCB110. However, as described above referring toFIG. 1, in the memory module100according to the present embodiment, because the data register buffer300is connected to the data line L0, the memory controller12cannot experience the load capacity of the memory chips200that exist on the signal path beyond the data register buffer300. Similarly, because the command/address/control register buffer400is connected to the command/address/control line L3, the memory controller12cannot experience the load capacity of the memory chips200that exist on the signal path beyond the command/address/control register buffer400. Therefore, the load capacity of the signal path that connects the memory controller12and the memory module100is reduced, making it possible to ensure an excellent signal quality even with a high data transfer rate.

Although only a single memory slot22is provided on the motherboard21in the memory system20shown inFIG. 3, in actual cases, a plurality of memory slots (for example, four) are provided on the memory system, so that the memory module100is mounted on each of the memory slots. As the number of units of the memory module100increases, the load capacity of the signal path increases by the number of memory modules. However, according to the present embodiment, because the load capacity per memory module is considerably smaller than that of a conventional memory module, it is possible to perform a high speed data transfer even when a plurality of memory modules are mounted.

A configuration of the memory chip200is explained next.

FIG. 4is a block diagram of a configuration of the memory chip200.

The memory chip200is a DRAM, which includes, as shown inFIG. 4, a clock terminal201, a command terminal202, a control terminal206, an address terminal203, a data input/output terminal204, and a data strobe terminal205as external terminals. Among these terminals, the clock terminal201, the command terminal202, the control terminal206, and the address terminal203are connected to the command/address/control register buffer400via a command/address/control line L5shown inFIG. 1. The data input/output terminal204and the data strobe terminal205are connected to the data register buffer300via the data line L1or the data line L2shown inFIG. 1. Although not shown inFIG. 1, the memory chip200further includes other terminals such as a power supply terminal.

The clock terminal201is a terminal to which a clock signal CK is supplied. The clock signal CK is then supplied to an internal clock generating circuit211. An internal clock ICLK, which is an output of the internal clock generating circuit211, is supplied to various internal circuits. The clock signal CK is also supplied to a DLL circuit212. The DLL circuit212takes a role of generating an internal clock LCLK and supplying the internal clock LCLK to a data input/output circuit213and a data strobe signal input/output circuit214. The internal clock LCLK is a signal that is phase-controlled with respect to the clock signal CK, of which a phase is slightly advanced with respect to the clock signal CK such that phases of read data DQ and a data strobe signal DQS match with a phase of the clock signal CK.

It is selected based on a set content in a mode register whether to use the DLL circuit212. That is, when “DLL on mode” is set in a mode register215, the DLL circuit212is enabled, so that the internal clock LCLK is phase-controlled with respect to the clock signal CK. On the other hand, when “DLL off mode” is set in the mode register215, the DLL circuit212is disabled (the clock signal CK is shortcut), so that the internal clock LCLK is not phase-controlled with respect to the clock signal CK.

The command terminal202is a terminal to which a command signal CMD that includes a row address strobe (RAS) signal, a column address strobe (CAS) signal, a write enable (WE) signal, and the like is supplied. The control terminal206is a terminal to which a control signal CTRL for each Rank, such as a chip select (CS) signal, a clock enable (CKE) signal, and an on die termination (ODT) signal, is supplied. By the chip select (CS) signal, a DRAM for which a command is to be issued is switched, and an activation of a clock system and a control of an on die termination in the DRAM are performed. The command signal CMD is supplied to a command decoder216. The command decoder216is a circuit that generates various internal commands ICMD by storing, decoding, and counting the command signal in synchronization with the internal clock ICLK. The generated internal commands are supplied to various control circuits (not shown) including the mode register215. The control signal CTRL is supplied to a control circuit218. The control circuit218is a circuit that generates an internal control signal such as the ODT signal based on the control signal CTRL.

The address terminal203is a terminal to which an address signal ADD is supplied. The address signal is then supplied to an address latch circuit217. The address latch circuit217is a circuit that latches the address signal ADD in synchronization with the internal clock ICLK. Among the address signals ADD that are latched in the address latch circuit217, a row address is supplied to a row decoder221and a column address is supplied to a column decoder222. In addition, upon entering a mode register set, the address signal ADD is supplied to the mode register215, by which a content of the mode register215is updated.

The row decoder221is a circuit that selects one of word lines WL included in a memory cell array230. In the memory cell array230, a plurality of word lines WL and a plurality of bit lines BL intersect with each other, and a memory cell MC is arranged at each intersection point (only a single word line WL, a single bit line BL, and a single memory cell MC are shown inFIG. 4). The bit line BL is connected to one of sense amplifiers SA that are included in a sense amplifier array231. The column decoder222performs a selection of the sense amplifier SA.

The selected sense amplifier SA is connected to the data input/output circuit213. The internal clock LCLK and an internal data strobe signal PDQS are supplied to the data input/output circuit213. In a read operation, the data input/output circuit213outputs read data in synchronization with the internal clock LCLK, and in a write operation, the data input/output circuit213loads write data in synchronization with the internal data strobe signal PDQS. With this arrangement, in the read operation, the read data read out from the memory cell array230is output from the data input/output terminal204, and in the write operation, the write data received from the data input/output terminal204is supplied to the memory cell array230.

The data strobe terminal205is a terminal for performing input and output of the data strobe signal DQS, which is connected to the data strobe signal input/output circuit214. The data strobe signal input/output circuit214generates the internal data strobe signal PDQS described above, and supplies it to the data input/output circuit213.

The ODT signal, which is an output of the control circuit218, is also supplied to the data input/output circuit213and the data strobe signal input/output circuit214. When the ODT signal is activated, both the data input/output circuit213and the data strobe signal input/output circuit214function as terminating resistors.

The overall configuration of the memory chip200is as described above. A configuration of the data register buffer300is explained next.

FIG. 5is a block diagram of the configuration of the data register buffer300.

As shown inFIG. 5, the data register buffer300includes a FIFO (Write) circuit301and a FIFO (Read) circuit302. The FIFO (Write) circuit301buffers data DQ that is supplied via an input/output terminal340with a data strobe signal DQS that is supplied via an input/output terminal350. The FIFO (Read) circuit302buffers data DQ that is supplied via an input/output terminal341or342with a data strobe signal DQS that is supplied via an input/output terminal351or352. A strobe generating circuit376generates a data strobe signal DQS to be supplied to the data connectors120, in synchronization with an internal clock LCLKR that is generated by a DLL circuit310. A strobe generating circuit374generates a data strobe signal DQS to be supplied to the memory chip200, in synchronization with an internal clock LCLKW that is generated by the DLL circuit310.

The FIFO circuits301and302shown inFIG. 5are circuits that perform input and output of 1-bit data, so that in an actual case, the number of sets of the FIFO circuits301and302as many as a width of input/output data are provided. In the present embodiment, because a single data register buffer300inputs and outputs 1-byte data, 8 sets of the FIFO circuits301and302are required.

The input/output terminals340and350are connected to the data connectors120via the data line L0. On the other hand, the input/output terminals341and351are connected to the memory chip200via the data line L1, and the input/output terminals342and352are connected to the memory chip200via the data line L2. In this manner, for the data register buffer300, the number of the input/output terminals (M) to be connected to the memory controller12and the number of the input/output terminals (N) to be connected to the memory chip200are different from each other, which is, in the present embodiment, N=2M. In other words, the number of the data lines L1and L2is N/M times the number of the data line L0(two times in the present embodiment).

An output operation timing of the FIFO (Write) circuit301is defined by the internal clock LCLKW that is generated by the DLL circuit310. An output operation timing of the FIFO (Read) circuit302is defined by the internal clock LCLKR that is generated by the DLL circuit310. The DLL circuit310is a circuit that generates the internal clocks LCLKW and LCLKR based on the clock signal CK that is supplied from the command/address/control register buffer400, having the same circuit configuration and function as that of the DLL circuit212provided in the memory chip200. It is selected based on a set content in a data register control circuit320whether to use the DLL circuit310. The DLL circuit310can be replaced with a PLL circuit.

The data register control circuit320is a circuit that controls the operation of the data register buffer300based on a control signal DRC that is supplied from the command/address/control register buffer400. Specifically, the data register control circuit320controls operations of an input buffer INB and an output buffer OUTB by generating a buffer control signal BC, and at the same time, controls operations of selectors331to334by generating a select signal SEL. Contents of controlling the output buffer OUTB include, for example, an adjustment of output impedance and an on/off control of an ODT operation. It is selected based on a set content in a mode register321that is included in the data register control circuit320whether to use the ODT function.

In addition, the data register control circuit320generates a feedback signal DRF and supplies it to the command/address/control register buffer400. The feedback signal DRF is a signal indicating a current status of the data register buffer300.

Furthermore, the data register control circuit320includes a write leveling circuit322and a read leveling circuit323. The write leveling circuit322is a circuit for performing a write leveling operation, and the read leveling circuit323is a circuit for performing a read leveling operation. Details on the write leveling operation and the read leveling operation will be described later.

The selector333is a circuit that supplies data DQ that is an output of the FIFO (Write) circuit301to either one of the input/output terminals341and342. The selector334is a circuit that selects data DQ input from either one of the input/output terminals341and342and supplies the selected data DQ to the FIFO (Read) circuit302. The selectors331and332perform the similar functions as those of the selectors333and334, respectively. Specifically, the selector332selects a data strobe signal DQS input from either one of the input/output terminals351and352. A phase of the selected data strobe signal DQS is delayed by about 90 degrees by a delay circuit372, and then the data strobe signal DQS is supplied to the FIFO (Read) circuit302as an input trigger signal. The selector331supplies the data strobe signal DQS that is supplied from the strobe generating circuit374to either one of the input/output terminals351and352. A phase of the data strobe signal DQS generated by the strobe generating circuit374is delayed by about 90 degrees with respect to the internal clock LCLKW by a delay circuit370. Each of the selections by the selectors331to334is specified by the select signal SEL that is an output of the data register control circuit320.

In this manner, the data register buffer300buffers the write data that is transferred via the data line L0and outputs the write data to either one of the data lines L1and L2, and buffers the read data that is transferred via either one of the data lines L1and L2and outputs the read data to the data line L0. Because the data register buffer300only performs the buffering of the data, transfer rates of the write data and the read data that are transferred via the data line L0and transfer rates of the write data and the read data that are transferred via the data lines L1and L2are equal to each other.

Therefore, the data register buffer300can be implemented with a chip that is provided at relatively low cost instead of an expensive chip such as an AMB used in a Fully Buffered memory module.

The overall configuration of the data register buffer300is as described above. A configuration of the command/address/control register buffer400is explained next.

FIG. 6is a block diagram of the configuration of the command/address/control register buffer400.

As shown inFIG. 6, the command/address/control register buffer400includes the input terminal401for connecting to the command/address/control connectors130, the output terminal402for connecting to the memory chip200, and the output terminal403and an input terminal404for connecting to the data register buffer300.

The command/address/control signal that is supplied from the memory controller12is input from the input terminal401. Among input command/address/control signals, the command signal CMD, the address signal ADD, and the control signal CTRL are supplied to a register circuit410, and the clock signal CK is supplied to a PLL circuit420. The register circuit410is a circuit that buffers the command signal CMD, the address signal ADD, and the control signal CTRL, and the buffered command signal CMD, address signal ADD, and control signal CTRL are supplied to the memory chip200via the output terminal402.

An operation timing of the register circuit410is defined by an internal clock LCLKCA that is generated by the PLL circuit420. The PLL circuit420is a circuit that generates the internal clock LCLKCA based on the clock signal CK supplied from the memory controller12having the same circuit configuration and function as that of the DLL circuit212provided in the memory chip200. It is selected based on a set content in a mode register431that is included in a control signal generating circuit430whether to use the PLL circuit420. The PLL circuit420can be replaced with a DLL circuit.

The control signal generating circuit430is a circuit that generates the control signal DRC to be supplied to the data register buffer300based on the command/address/control signal supplied via the input terminal401, of which an operation is performed in synchronization with the internal clock LCLKCA. The control signal DRC for the data register buffer300is supplied to the data register buffer300via the output terminal403. The feedback signal DRF is supplied to the control signal generating circuit430from the data register buffer300via the input terminal404.

The control signal DRC includes signals such as a signal indicating a direction of transmitting and receiving data, a signal for controlling an ODT timing at the data line L0side of the data register buffer300, a signal for controlling an ODT timing at the data lines L1and L2side, a signal for controlling on and off of the DLL circuit, a signal for controlling enable and disable of the data register buffer300, and a signal for performing a mode switching of the data register buffer300and a mode register set and the like. A separate line can be allocated to each of these signals, or a single common line can be allocated to a plurality of these signals. Alternatively, these signals can be transmitted to the data register buffer300as commands.

The overall configuration of the command/address/control register buffer400is as described above.

FIG. 7is a connection diagram of the memory module100according to the present embodiment.

As shown inFIG. 7, in the present embodiment, the data register buffer300intervenes between the data connectors120and the memory chips200. The data connectors120and the data register buffer300are connected to each other with the data line L0, and the data register buffer300and the memory chips200are connected to each other with the data line L1or L2. InFIG. 7, a plurality of data transferred through the data line L0is represented by data DQ-Pre, and a plurality of data transferred through the data lines L1and L2is represented by data DQ-Post. Similarly, a data strobe signal transferred through the data line L0is represented by a data strobe signal DQS-Pre, and a data strobe signal transferred through the data line L1or L2is represented by a data strobe signal DQS-Post.

Although the data DQ-Pre and the data DQ-Post have the same content, because the data DQ is buffered by the data register buffer300, the timing is off between the data DQ-Pre and the data DQ-Post. The same is true for a relationship between the data strobe signal DQS-Pre and the data strobe signal DQS-Post. Therefore, in the present embodiment, it is required to perform a timing adjustment between the memory chips200and the data register buffer300and a timing adjustment between the data register buffer300and the memory controller in a separate manner. Details on the timing adjustments will be described later.

As described above, in the present embodiment, the four memory chips200are allocated to a single data register buffer300. The four memory chips200are memory chips that constitute different Ranks from each other, which are exclusively activated by the chip select (CS) signal or the clock enable (CKE) signal included in the control signal CTRL. The address signal ADD and the command signal CMD are commonly supplied to the four memory chips200.

The address signal ADD, the command signal CMD, the control signal CTRL, and the clock signal CK supplied to the memory chips200are supplied from the command/address/control register buffer400. The control signal DRC supplied to the data register buffer300is also supplied from the command/address/control register buffer400.

As shown inFIG. 7, the command/address/control connectors130and the command/address/control register buffer400are connected to each other with the command/address/control line L3, the command/address/control register buffer400and the data register buffer300are connected to each other with a control line L4, and the command/address/control register buffer400and the memory chips200are connected to each other with a command/address/control line L5. InFIG. 7, a command/address/control signal transferred through the command/address/control line L3is represented by a command/address signal ADD/CMD-Pre, and a command/address signal transferred through the command/address/control line L5is represented by a command/address signal ADD/CMD-Post. Similarly, a control signal transferred through the command/address/control line L3is represented by a control signal CNTRL-Pre, and a control signal transferred through the command/address/control line L5is represented by a control signal CNTRL-Post.

The clock signal CK to be supplied to the memory chip200and the data register buffer300is supplied from the command/address/control register buffer400. InFIG. 7, a clock signal transferred through the command/address/control line L3is represented by a clock signal Clock-Pre, and a clock signal transferred through the command/address/control line L5is represented by a clock signal Clock-Post.

FIGS. 8A and 8Bare schematic diagrams for explaining a data transfer path for transferring 1-bit data in the memory module100according to the present embodiment, whereFIG. 8Ais a layout diagram andFIG. 8Bis a connection diagram.

As shown inFIGS. 8A and 8B, the 1-bit data is transferred via a predetermined connector121of the data connectors120. The connector121is connected to the data register buffer300via a single data line L0. As explained above referring toFIG. 5, in the present embodiment, two data lines L1and L2are allocated to a single data line L0. Specifically, the data line L1is commonly connected to the memory chips200-0and200-1, and the data line L2is commonly connected to the memory chips200-2and200-3.

With the above configuration, the load capacity of a single data line L1or L2is reduced, the number of branch points decreases, and a line length from a branch point is shortened. As a result, the signal quality of data transferred on the data lines L1and L2is enhanced. Specifically, terminals connected to the single data line L1are only three terminals total including data input/output terminals of the memory chips200-0and200-1and a data output terminal of the data register buffer300. Furthermore, because the memory chips200-0and200-1are arranged facing each other across the module PCB110, as shown inFIG. 8A, if a branch point P is arranged in an area sandwiched by the memory chips200-0and200-1, the line length from the branch point to each of the memory chips200-0and200-1is considerably shortened. In addition, because the memory chips200-0to200-3are mounted at positions close to each other, a perspective difference in edges of the memory chips200-0to200-3is also suppressed to the minimum.

FIGS. 9A and 9Bare schematic diagrams for explaining a data transfer path for transferring 1-bit data when the data lines L1and L2are put together in a single data line, whereFIG. 9Ais a layout diagram andFIG. 9Bis a connection diagram.

As shown inFIGS. 9A and 9B, when the data lines L1and L2are put together in a single data line L1, the data register buffer300and the four memory chips200-0to200-3are commonly connected with the single data line L1. Therefore, as compared to the configuration shown inFIGS. 8A and 8B, the load capacity of the single data line L1increases, the number of branch points increases, and the line length from the branch point also increases. Specifically, terminals connected to the single data line L1become five terminals total including data input/output terminals of the memory chips200-0to200-3and the data output terminal of the data register buffer300. In addition, because the configuration becomes such that the line is branched into two at a branch point P1and further branched into two at a branch point P2, a line length from the branch point P1to each of the memory chips200-0to200-3increases.

On the other hand, in the present embodiment, because the two data lines L1and L2are employed, as shown inFIGS. 8A and 8B, the signal quality of data in the module PCB can be enhanced. Using the two data lines L1and L2doubles the number of lines for connecting the memory chips200and the data register buffer300. However, in the present embodiment, because the memory chips200and the data register buffer300constituting the same group G are arranged in the direction of the short side on the module PCB110as explained referring toFIG. 1, there is an enough room for the line space. Therefore, even if the number of lines extending in the direction of the short side is doubled, it is possible to form the lines without difficulty.

Meanwhile, when a layout is taken in which data are concentrated in the center of the module PCB, as in the case of the Fully Buffered memory module, it is required to form a plurality of long data lines in the direction of the long side of the module PCB. In such a layout, because the total length of the data lines increases by a considerable amount as compared to the layout of the present embodiment, it is required to take a measure such as significantly increasing the number of insulating layers forming the module PCB in order to double the number of the data lines. However, according to the present embodiment, because it does not cause such a problem, it is possible to double the number of lines for connecting the memory chips200and the data register buffer300without increasing the number of insulating layers forming the module PCB110.

FIG. 10is a timing chart for explaining an interleaving operation using the two data lines L1and L2.

FIG. 10shows a consecutive read operation from a Rank0to a Rank3with a case that a burst length is 4 bits (BL=4) (or a case that a burst operation is stopped at 4 bits by a burst chop). In the example shown inFIG. 10, a read command is issued at times T0, T2, T4, and T6that are synchronized with the clock signal CK in the order of the Rank0, the Rank2, the Rank1, and the Rank3. In response to these read commands, after a lapse of a predetermined CAS latency (in this example, CL=12), 4-bit read data DQ is burst output.

As a result, in a period from a time T12to a time T14, a data transfer is performed from the memory chip200of the Rank0using the data line L1, in a period from the time T14to a time T16, a data transfer is performed from the memory chip200of the Rank2using the data line L2, in a period from the time T16to a time T18, a data transfer is performed from the memory chip200of the Rank1using the data line L1, and in a period from the time T18to a time T20, a data transfer is performed from the memory chip200of the Rank3using the data line L2. That is, the data lines L1and L2are used in an alternate manner.

The read data sequentially transferred in the above manner are supplied to the data register buffer300, and after being buffered in a FIFO circuit included in the data register buffer300, output to the data line L0. In the example, shown inFIG. 10, since the read data is input to the data register buffer300, the read data is output with one cycle delay.

In this manner, in the present embodiment, because the interleaving operation can be performed using the two data lines L1and L2, it is possible to perform a read operation for a plurality of memory chips without interruption. As a result, the read data output from the data register buffer300can also be supplied to the memory controller without interruption, so that the usage efficiency of a bus can be enhanced. Although the data lines L1and L2are not simultaneously used in the present embodiment, if the data lines L1and L2are put together in a single data line, it is required to spare a time equal to or longer than one cycle between read data output from different memory chips. On the other hand, in the present embodiment, because the two data lines L1and L2are alternately used, it is not necessary to put a time between read data output from different memory chips.

Although the read operation is explained as an example inFIG. 10, a similar interleaving operation can be applied for a write operation.

The operation of the memory module100according to the present embodiment is explained below in more detail.

FIG. 11is a timing chart for explaining a read operation of the memory module100according to the present embodiment.

In the read operation, an active command ACT and a read command Read are issued in order from the memory controller12. In the example shown inFIG. 11, the active command ACT reaches the command/address/control connectors130at a time T-5that is synchronized with the clock signal CK, and the read command Read reaches the command/address/control connectors130at a time T0.

The commands ACT and Read reaching the command/address/control connectors130are input to the command/address/control register buffer400. At this moment, there occurs a predetermined time difference (Flight Time) between a timing at which the commands ACT and Read reaches the command/address/control connectors130and a timing at which the commands ACT and Read are input to the command/address/control register buffer400.

The command/address/control register buffer400registers the received commands ACT and Read with an input clock signal in the register circuit410shown inFIG. 6, and then outputs them to the memory chip200. At this time, a synchronization with the output of the commands ACT and Read is taken by delaying the output of the clock signal CK by an amount equivalent to an additional ½ clock cycle. In addition, the command/address/control register buffer400supplies a read command Read to the data register buffer300as a part of the control signal DRC.

The memory chip200receives the commands ACT and Read, and starts an actual read operation. At this moment, there occurs a predetermined time difference (Flight Time) between a timing at which the commands ACT and Read are output from the command/address/control register buffer400and a timing at which the commands ACT and Read are input to the memory chip200.

Because CL=5 in the example shown inFIG. 11, the memory chip200starts a burst output of read data DQ at a time T5in five clock cycles after receiving the read command Read. In the example shown inFIG. 11, the burst length is 8 bits (BL=8). The read data DQ and a data strobe signal DQS burst output from the memory chip200are supplied to the data register buffer300.

The data register buffer300loads the read data DQ that is output from the memory chip200in the FIFO (Read) circuit302with a data strobe signal DQS that is delayed by a predetermined phase amount (for example, phase difference of about 90 degrees). At this moment, there occurs a predetermined time difference (Flight Time) between a timing at which the read data DQ and the data strobe signal DQS are output from the memory chip200and a timing at which the read data DQ and the data strobe signal DQS are input to the data register buffer300.

Thereafter, the data register buffer300performs a re-timing in synchronization with the internal clock LCLKR using the FIFO (Read) circuit302to convert CL into CL=6, and outputs the read data DQ and the data strobe signal DQS. With this configuration, it becomes possible for the memory controller to receive the read data DQ in a correct manner.

The read operation of the memory module100according to the present embodiment is as described above. A write operation of the memory module100is explained next.

FIG. 12is a timing chart for explaining the write operation of the memory module100according to the present embodiment.

In the write operation, the memory controller issues an active command ACT and a write command Write in order, and after a lapse of a write latency (WL) since the write command Write is issued, burst outputs write data. In the example shown inFIG. 12, the active command ACT reaches the command/address/control connectors130at the time T-5that is synchronized with the clock signal CK, and the write command Write reaches the command/address/control connectors130at the time T0. In this example, WL=4, so that write data DQ is input to the data connectors120from a time T4.

Because a flow of the command is similar to that in the read operation shown inFIG. 11, redundant explanations will be omitted. The write data DQ reaching the data connectors120is input to the data register buffer300. At this moment, there occurs a time difference (Flight Time) between a timing at which the write command reaches the command/address/control connectors130and a timing at which the write command (Direction Control) is input to the data register buffer300. In consideration of this point, the memory controller outputs the write data DQ by delaying it by an amount equivalent to the Flight Time.

The data register buffer300loads the received write data DQ in the FIFO (Write) circuit301with a data strobe signal DQS that is delayed by a predetermined phase amount (for example, phase difference of about 90 degrees). The data register buffer300then performs a re-timing in synchronization with the internal clock LCLKW using the FIFO (Write) circuit301to convert WL into WL=5, and outputs the write data DQ and the data strobe signal DQS. As described above, the write data is transferred from the data register buffer300to the memory chip200using either one of the two data lines L1and L2. The data line to be used is determined by a designated Rank.

The memory chip200receives the write data DQ that is burst output from the data register buffer300, and writes it in the memory cell array. At this time, there occurs a predetermined time difference (Flight Time) between a timing at which the write data DQ and the data strobe signal DQS are output from the data register buffer300and a timing at which the write data DQ and the data strobe signal DQS are input to the memory chip200. In consideration of this point, the data register buffer300outputs the write data DQ earlier by an amount equivalent to the Flight Time. With this configuration, it becomes possible for the memory chip200to receive the write data DQ in a correct manner.

An initializing operation of the memory module100according to the present embodiment at the time of activation is explained next.

FIG. 13is a flowchart for explaining the initializing operation of the memory module100at the time of activation.

With a power-on of the system (Step S1), each of the memory chip200, the data register buffer300, and the command/address/control register buffer400internally activates a reset signal to reset the internal circuit (Step S2). By resetting the internal circuit, each of the memory chip200, the data register buffer300, and the command/address/control register buffer400performs the initializing operation. The initializing operation includes a mode register setting operation by which predetermined mode information is set in the mode registers215,321, and431that are included in the memory chip200, the data register buffer300, and the command/address/control register buffer400, respectively (Step S3).

Upon completing the mode register setting operation, a leveling operation between the data register buffer300and the memory chip200is performed (Step S4). The leveling operation is to adjust a write timing or a read timing in consideration of a propagation time of a signal. The adjustment of the write timing is performed by a write leveling operation, and the adjustment of the read timing is performed by a read leveling operation.

When the leveling operation between the data register buffer300and the memory chip200is completed, a leveling operation between the memory controller and the data register buffer300is performed (Step S5).

FIGS. 14A and 14Bare timing charts for explaining the write leveling operation between the data register buffer300and the memory chip200, whereFIG. 14Ais a timing chart at the time of starting the leveling andFIG. 14Bis a timing chart at the time of ending the leveling. This operation is performed by the write leveling circuit322shown inFIG. 5.

In the write leveling operation between the data register buffer300and the memory chip200, as shown inFIG. 14A, the data register buffer300outputs a data strobe signal DQS that is synchronized with the clock signal CK. The clock signal CK is a signal that is supplied from the command/address/control register buffer400, which is also supplied to the memory chip200as described above. Because it takes a certain amount of propagation time until the data strobe signal DQS reaches the memory chip200, input timings of the clock signal CK and the data strobe signal DQS are not always the same on the memory chip200side.

In the example inFIG. 14A, there is shown a case that a logical level of the clock signal CK at a rising edge of the data strobe signal DQS is “High level”. In response to the logical level of the clock signal CK, the memory chip200outputs a signal DQ of “High level” from the data input/output terminal204. The signal DQ is input to the data register buffer300, by which the data register buffer300can find a direction of phase shift of the clock signal CK and the data strobe signal DQS.

The write leveling circuit322of the data register buffer300changes an output timing of the data strobe signal DQS by displacing the internal clock LCLKW based on the direction of the phase shift. In the example shown inFIG. 14A, because the data strobe signal DQS is retarded as compared to a rising edge of the clock signal CK reaching the memory chip200, the data register buffer300advances the output timing of the data strobe signal DQS.

By repeating the above operation, as shown inFIG. 14B, the logical level of the clock signal CK is changed to “Low level” at the rising edge of the data strobe signal DQS on the memory chip200side. This leads to an end of the write leveling operation, and the data register buffer300can find a timing to output the data strobe signal DQS based on the input clock signal CK. A result of the write leveling operation is stored in the data register control circuit320in the data register buffer300. Upon completing the write leveling operation in this manner, the phases of the clock signal CK and the data strobe signal DQS input to the memory chip200are substantially matched with each other.

FIG. 15is a timing chart for explaining the read leveling operation between the data register buffer300and the memory chip200. This operation is performed by the read leveling circuit323shown inFIG. 5.

In the read leveling operation between the data register buffer300and the memory chip200, as shown inFIG. 15, the command/address/control register buffer400outputs the clock signal CK, and at the same time, issues the active command ACT and the read command Read. The clock signal CK is supplied to the memory chip200and the data register buffer300, and the commands ACT and Read are supplied to the memory chip200. The read command Read is also supplied to the data register buffer300as a part of the control signal DRC.

In the example shown inFIG. 15, the active command ACT is issued at the time T-5that is synchronized with the clock signal CK, and the read command Read is issued at the time T0. Therefore, a RAS-CAS delay (tRCD) is five clock cycles.

The memory chip200receives the read command Read and performs an actual read operation. In the example shown inFIG. 15, the CAS latency is set to five clock cycles (CL=5), so that an output of read data DQ begins at the time T5. The read data DQ at the time of the read leveling is, for example, a signal in which a High level and a Low level are repeated in an alternate manner.

The read data DQ output from the memory chip200reaches the data register buffer300, by which the data register buffer300can find a time A from an input timing of the read command Read that is input as a part of the control signal DRC until the read data DQ is input. The time is measured for each of the memory chips200, stored in the data register control circuit320in the data register buffer300, and used in an adjustment of an activation timing of the input buffer circuit INB and the like. InFIG. 15, two cases are shown including a first case that the time A from the input of the read command Read until the input of the read data DQ is short (between the memory chip200-0and the data register buffer300-0) and a second case that the time A is long (between the memory chip200-19and the data register buffer300-4).

FIGS. 16A and 16Bare timing charts for explaining the write leveling operation between the memory controller12and the data register buffer300, whereFIG. 16Ais a timing chart at the time of starting the leveling andFIG. 16Bis a timing chart at the time of ending the leveling. This operation is performed by a write leveling circuit12ashown inFIG. 2.

In the write leveling operation between the memory controller12and the data register buffer300, as shown inFIG. 16A, the memory controller12outputs the clock signal and the data strobe signal DQS. The clock signal CK is supplied to the data register buffer300via the command/address/control register buffer400, and the data strobe signal DQS is directly supplied to the data register buffer300. Therefore, input timings of the clock signal CK and the data strobe signal DQS are not always the same on the data register buffer300side.

In the example shown inFIG. 16A, on the data register buffer300, a case that in which the logical level of the clock signal CK at the rising edge of the data strobe signal DQS is “Low level”. In response to the logical level of the clock signal CK, the data register buffer300outputs a signal DQ of “Low level” from the input/output terminal340. The signal DQ is supplied to the memory controller12, by which the memory controller12can find a direction of phase shift of the clock signal CK and the data strobe signal DQS.

The memory controller12changes an output timing of the data strobe signal DQS based on the direction of the phase shift. In the example shown inFIG. 16A, because the data strobe signal DQS reaches the data register buffer300earlier than the rising edge of the clock signal CK reaching the data register buffer300, the memory controller12delays the output timing of the data strobe signal DQS.

By repeating the above operation, as shown inFIG. 16B, the logical level of the clock signal CK is changed to “High level” at the rising edge of the data strobe signal DQS on the data register buffer300side. This leads to an end of the write leveling operation, and the memory controller12can find a timing to output the data strobe signal DQS based on the clock signal CK that is output from the memory controller12itself. A result of the write leveling operation is stored in an internal circuit of the memory controller12. Upon completing the write leveling operation in this manner, the phases of the clock signal CK and the data strobe signal DQS input to the data register buffer300are substantially matched with each other.

FIG. 17is a timing chart for explaining the read leveling operation between the memory controller12and the data register buffer300. This operation is performed by a read leveling circuit12bshown inFIG. 2.

In the read leveling operation between the memory controller12and the data register buffer300, as shown inFIG. 17, the memory controller12outputs the clock signal CK, and at the same time, issues an active command ACT and a read command Read. The clock signal CK is supplied to the data register buffer300, and the commands ACT and Read are supplied to the data register buffer300via the command/address/control register buffer400as a part of the control signal DRC.

In the example shown inFIG. 17, the active command ACT is issued at the time T-5that is synchronized with the clock signal CK, and the read command Read is issued at the time T0. Therefore, a RAS-CAS delay (tRCD) is five clock cycles.

The data register buffer300receives the read command Read, and after a lapse of a predetermined CAS latency, outputs dummy data DQ. The dummy data DQ is not the read data read out from the memory chip200but data that is automatically generated by the data register control circuit320in the data register buffer300. In the example shown inFIG. 17, the CAS latency is set to six clock cycles (CL=6), so that an output of the dummy data DQ begins at a time T6. The dummy data DQ is, for example, a signal in which a High level and a Low level are repeated in an alternate manner.

The dummy data DQ output from the data register buffer300reaches the memory controller12, by which the memory controller12can find a time B from an issuance timing of the read command Read until the read data DQ is input. The time is measured for each of the data register buffers300, stored in the internal circuit of the memory controller12, and used in an adjustment of an activation timing of an input buffer circuit (not shown) and the like. InFIG. 17, two cases are shown including a first case that the time B from the issuance of the read command Read until the input of the read data DQ is short (between the memory controller12and the data register buffer300-0) and a second case that the time B is long (between the memory controller12and the data register buffer300-4).

The initializing operation of the memory module100according to the present embodiment is as described above. A relationship between the DLL circuit and the ODT function of the memory module100according to the present invention is explained next.

As described above, the DLL circuit is a circuit that generates an internal clock signal of which a phase is controlled with respect to an external clock signal, which is used for matching the phases of the read data DQ and the data strobe signal DQS with the phase of the clock signal CK. In a recent high speed memory such as a DDR3 DRAM, a use of the DLL circuit is substantially essential. If the DLL circuit is not used, it is difficult to perform a data transfer in a proper manner. On the other hand, the DLL circuit has a problem of relatively large power consumption.

Meanwhile, the ODT function is a function of incorporating a terminating resistor inside a memory chip, which is used for preventing a degradation of signal quality due to a reflection of the signal. In a typical memory module, a large number of memory chips are commonly connected to a single data line. Therefore, in a recent high speed memory, a use of the ODT function is substantially essential. If the ODT function is set to off, a signal waveform is significantly degraded. On the other hand, if the ODT function is set to on, it causes a problem of increasing the power consumption. In addition, because the ODT operation necessitates a synchronization with a data input/output operation, the use of the DLL circuit is basically assumed.

FIG. 18is a timing chart for explaining a problem that occurs when performing the ODT operation without using the DLL circuit.

In the example shown inFIG. 18, the ODT signal is activated just before the time T0. In response to the activation of the ODT signal, the internal circuit of the memory chip200turns on the ODT function in synchronization with the clock signal at the time T0. However, the ODT impedance (impedances of the data input/output terminal204and the data strobe terminal205) does not reach a desired value immediately, and it is not changed from a high impedance state (RTT_OFF) unless tAONDFmin passes. In the present example, the tAONDFmin is about three clock cycles.

After a lapse of the tAONDFmin, although the ODT impedance becomes no longer the high impedance state according to a condition such as the power supply voltage and the chip temperature, it still does not reach the desired impedance RTT_ON depending on the condition. Under the worst condition, the desired impedance RTT_ON is obtained after tAONDFmax passes from the time T0. In the present example, the tAONDFmax is about eight clock cycles.

Therefore, in a period from a time T3at which the ODT impedance becomes an undefined state to a time T9that is next to a cycle at which the ODT impedance becomes the desired value RTT, the impedance becomes undefined. Accordingly, this period becomes a loss cycle in which an access to another memory chip is not allowed. In this manner, when the ODT operation is performed without using the DLL circuit, a switching between on and off controls of the ODT function is not synchronized, resulting in an increase of the period in which the impedance is undefined during which the read/write operation is inhibited.

In consideration of the loss cycle problem described above, it is desirable not to use the ODT function when the DLL circuit is not used. However, the ODT function is substantially essential in the typical memory module, so that it is difficult to turn the function off.

However, in the memory module100according to the present embodiment, because the load capacities of the data lines L1and L2connected to the memory chip200are considerably small, even when a high speed memory such as a DDR3 DRAM is used, the ODT operation can be set off in an actual operation. Besides, because a distance between the memory chip200and the data register buffer300is considerably short, even if a synchronization control is not performed using a DLL circuit, it is possible to perform a data transfer in a correct manner. That is, because both the ODT function and the DLL circuit can be set to off, it is possible to reduce the power consumption by a considerable amount. In addition, because the ODT function and the DLL circuit can be eliminated from the memory chip200, it is also possible to reduce the chip dimension.

A difference in operation timings depending on the use of the ODT function and the DLL circuit is explained next.

FIG. 19is a timing chart for explaining a read-to-read operation when both the ODT function and the DLL circuit are in an ON state.

As shown inFIG. 19, a read operation timing in a state where both the ODT function and the DLL circuit are set to on is basically the same as the operation timing shown inFIG. 11. In the example shown inFIG. 19, a read command Read is issued for the Rank0at the time T0, and another read command Read is issued for the Rank1at the time T6. Because the memory chip200of the Rank0and the memory chip200of the Rank1are commonly connected to the data line L1, they cause an influence on each other.

Accordingly, in a period from the time T5to the time T9during which read data DQ is burst output from the memory chip200of the Rank0, an impedance of the data input/output terminal204of the memory chip200of the Rank1is set to Rtt_Nom by the ODT function. Similarly, in a period from a time T11to a time T15during which read data DQ is burst output from the memory chip200of the Rank1, an impedance of the data input/output terminal204of the memory chip200of the Rank0is set to Rtt_Nom by the ODT function.

In this manner, during the read data DQ is output from the memory chip200on one side, the memory chip200on the other side performs the ODT operation, which prevents a reflection of a signal. However, as described above, current consumption is generated due to the usage of the ODT function and the DLL circuit.

FIG. 20is a timing chart for explaining the read-to-read operation when both the ODT function and the DLL circuit are in an OFF state.

As shown inFIG. 20, when the DLL circuit is set to off, an output timing of the read data DQ is asynchronous with the clock signal CK. However, in the present embodiment, because the distance between the memory chip200and the data register buffer300is considerably short, the data register buffer300can correctly receive the read data DQ that is output in an asynchronous manner. In addition, because the memory chip of the Rank0and the memory chip of the Rank1are arranged at substantially the end of the data line L1, an influence of a reflection of a signal from the memory chip200on the non-operating side is considerably small. The read data DQ output in an asynchronous manner is subjected to a re-timing by the data register buffer300, and then output to the memory controller12.

In this manner, in the present embodiment, even when both the ODT function and the DLL circuit of the memory chip200are set to off, it is possible to perform the same read operation as in a case that the ODT function and the DLL circuit are set to on. Rather, the output timing of the read data DQ is made earlier because the timing adjustment by the DLL circuit is not performed, which makes it possible to realize an even higher speed access.

FIG. 21is a timing chart for explaining a write-to-write operation when both the ODT function and the DLL circuit are in an ON state.

As shown inFIG. 21, a write operation timing in a state where both the ODT function and the DLL circuit are set to on is basically the same as the operation timing shown inFIG. 12. In the example shown inFIG. 21, a write command Write is issued for the Rank0at the time T0, and another write command Write is issued for the Rank1at the time T6. As described above, because the memory chip200of the Rank0and the memory chip200of the Rank1are commonly connected to the data line L1, they cause an influence on each other.

Accordingly, in a period from the time T5to the time T9during which write data DQ is burst input to the memory chip200of the Rank0, an impedance of the data input/output terminal204of the memory chip200of the Rank1is set to Rtt_Nom by the ODT function. Similarly, in a period from the time T11to the time T15during which write data DQ is burst input to the memory chip200of the Rank1, an impedance of the data input/output terminal204of the memory chip200of the Rank0is set to Rtt_Nom by the ODT function.

In this manner, during the memory chip200on one side receives the write data DQ, the memory chip200on the other side performs the ODT operation, which prevents a reflection of a signal. However, as described above, current consumption is generated due to the usage of the ODT function and the DLL circuit.

FIG. 22is a timing chart for explaining the write-to-write operation when both the ODT function and the DLL circuit are in an OFF state.

As shown inFIG. 22, when the ODT function is set to off, the data input/output terminal204of the memory chip200on the non-operating side becomes in a high impedance state, from which a reflection of a signal occurs. However, in the present embodiment, because the distance between the memory chip200and the data register buffer300is considerably short and the memory chip of the Rank0and the memory chip of the Rank1are arranged at substantially the end of the data line L1, the influence of the reflection of the signal from the memory chip200on the non-operating side is considerably small. Therefore, it is possible for each of the memory chips200to receive the write data DQ in a correct manner.

In this manner, in the present embodiment, even when both the ODT function and the DLL circuit of the memory chip200are set to off, that is, the current consumption due to the ODT function and the DLL circuit is made zero, it is possible to perform the same write operation as in a case that the ODT function and the DLL circuit are set to on. Rather, because an operation for switching the ODT impedance is not necessary, it is also possible to make an input timing of the write data DQ earlier. Actually, the speed of the write-to-write operation is increased by one clock cycle in the operation timing shown inFIG. 22than in the operation timing shown inFIG. 21.

Some modifications of the present invention are explained nest.

FIGS. 23A and 23Bare schematic diagrams for explaining a data transfer path for transferring 1-bit data in a memory module according to a modification of the present embodiment, whereFIG. 23Ais a layout diagram andFIG. 23Bis a connection diagram.

In the example shown inFIGS. 23A and 23B, unlike the embodiment described above, only a single memory chip200is connected to each of the data lines L1and L2. Specifically, only the memory chip200-0is connected to the data line L1, and only the memory chip200-1is connected to the data line L2. The present invention also includes this type of mode. That is, the number of memory chips200allocated to a single data line (L1or L2) that connects the memory chip200and the data register buffer300is not limited to a particular number. However, in order to reduce the load capacities of the data lines L1and L2, the branch points, and the line lengths, it is preferable that the number of the memory chips200connected to a single data line should be equal to or less smaller than two.

FIGS. 24A and 24Bare schematic diagrams for explaining a data transfer path for transferring 1-bit data in a memory module according to another modification of the present embodiment, whereFIG. 24Ais a layout diagram andFIG. 24Bis a connection diagram.

In the example shown inFIGS. 24A and 24B, unlike the embodiment described above, four data lines L1a, L1b, L2a, and L2bare allocated to a single data line L0. Specifically, only the memory chip200-0is connected to the data line L1a, only the memory chip200-1is connected to the data line L1b, only the memory chip200-2is connected to the data line L2a, and only the memory chip200-3is connected to the data line L2b. The present invention also includes this type of mode. That is, the number of the memory chips200allocated to a single data register buffer300is not limited to a particular number as long as it is equal to or larger than two.

FIG. 25is a schematic diagram of a configuration of a memory module according to still another modification of the present embodiment.

The memory module shown inFIG. 25has such a configuration that a plurality of memory chips200forming the same group and a single data register buffer300are integrated in a sub-module500. By using the sub-module500, the data lines L1and L2can be formed on a substrate of the sub-module, so that a line density of the module PCB110can be relieved. In addition, because the number of parts to be mounted on the module PCB110is reduced by a considerable amount, the mounting process on the module PCB110can be simplified.

FIG. 26is a plan view showing a configuration of the sub-module500; andFIG. 27is a cross section of the sub-module500cut along a line Y1-Y1′ shown inFIG. 26. InFIG. 26, external terminals formed on the other side are shown transparently.

The sub-module500shown inFIGS. 26 and 27is configured with a sub-module PCB510, two memory chips200and a data register buffer300mounted on the sub-module PCB510, and external terminals (solder balls)520formed on the other side of the sub-module PCB510. The memory chips200and the data register buffer300are sealed with a sealant530.

The external terminals520include DQ balls521for performing an exchange of data, Control balls522for performing a reception of a control signal to be supplied to the data register buffer300, and CA balls523for performing a reception of a command/address/control signal. The DQ balls521and the Control balls522are arranged on the other side of the sub-module PCB510near an area in which the data register buffer300is mounted. On the other hand, the CA balls523are arranged on the other side of the sub-module PCB510near an area in which the memory chips200are mounted.

The DQ balls521and the Control balls522are connected to the data register buffer300via internal lines511and514that are formed on the sub-module PCB510. The CA balls523are connected to the memory chips200via internal lines513that are formed on the sub-module PCB510.

Using the sub-module500configured in the above manner eliminates a necessity of forming the data lines L1and L2for connecting the memory chips200and the data register buffer300on the module PCB110. As a result, a freedom in the layout of the module PCB110is enhanced.

FIG. 28is a plan view showing another configuration of the sub-module500; andFIG. 29is a cross section of the sub-module500cut along a line Y2-Y2′ shown inFIG. 28. InFIG. 28, external terminals formed on the other side are shown transparently.

The sub-module500shown inFIGS. 28 and 29has basically the same configuration as that of the sub-module500shown inFIGS. 26 and 27, with a difference in that eight memory chips200are mounted on the sub-module PCB510. The eight memory chips200are formed with four layered bodies in each of which two memory chips200are layered. The four layered bodies are two-dimensionally mounted on the sub-module PCB510. Using the sub-module500configured in the above manner makes it possible to increase a memory capacity of the memory module.

It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention. For example, while the above embodiment has described a memory chip that includes a DLL circuit therein as the memory chip200, a memory chip that does not include a DLL circuit therein can be alternatively used. In this case, the DLL circuit included in the data register buffer300is used to adjust the input/output timing.