Capacity planning for systems with multiprocessor boards

Methods of analyzing and capacity planning for multi-core, multi-chip, multi-threaded computer system environments by analyzing the scalability of a fourth layer complexity, the processor boards, and incorporating this factor into the calculation of the expected throughput of a system constructed with multiple processor boards. In particular, the method may comprise identifying a system for which system performance prediction is desired, specifying a simulation model, and determining configuration parameters for the system, the system with at least one processor board, at least one chip per board, at least one core per chip, and at least one thread per core. The method may further comprise obtaining scalability factors based on the configuration data for the system, executing a simulation process for the simulation model for a deterministic simulation time, calculating a throughput of the system as a prediction of the performance of the system, and storing the results in a storage device.

BACKGROUND

The disclosure relates generally to capacity planning for computer systems, and more specifically to a method for capacity planning for systems with multiprocessor boards.

SUMMARY

According to one embodiment of the disclosure, a method comprises identifying a system for which system performance prediction is desired, specifying a simulation model, determining configuration parameters for the system, the system comprising at least one processor board, at least one chip per board, at least one core per chip, and at least one thread per core, obtaining scalability factors based on the configuration data for the system, executing a simulation process for the simulation model for a predetermined simulation time, calculating a throughput of the system as a prediction of the performance of the system, and storing the results in a storage device.

Other features and advantages of the present disclosure are apparent to persons of ordinary skill in the art in view of the following detailed description of the disclosure and the accompanying drawings.

DETAILED DESCRIPTION

Any combination of one or more computer readable media may be utilized. The computer readable media may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a random access memory (“RAM”), a read-only memory (“ROM”), an erasable programmable read-only memory (“EPROM” or Flash memory), an appropriate optical fiber with a repeater, a portable compact disc read-only memory (“CD-ROM”), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

While certain example systems and methods disclosed herein may be described with reference to mainframes in cloud computing, systems and methods disclosed herein may be related to architecture and information technology (“IT”) service and asset management in cloud computing, as well as usability and user experience in middleware and common services. Systems and methods disclosed herein may be applicable to a broad range of applications that monitor various parameters associated with various disciplines, such as, for example, IT systems and other activities of importance to the user.

Referring now toFIG. 1, a network1allows a user to access and use a system performance analysis module and a system performance prediction module. The system performance analysis module and the system performance prediction module may be internally provided or sourced through third parties. In addition, the system performance analysis module and system performance prediction module may be stored in a memory for use with a computer, or maintained and accessible via cloud storage, as discussed below. In particular, network1may comprise one or more clouds2, which may be public clouds, private clouds, or community clouds. Each cloud2may permit the exchange of information and services among users that are connected to such clouds2. In certain configurations, cloud2may be a wide area network, such as the Internet. In some configurations, cloud2may be a local area network, such as an intranet. Further, cloud2may be a closed, private network in certain configurations, and cloud2may be an open network in other configurations. Cloud2may facilitate wired or wireless communications of information among users that are connected to cloud2.

Network1may comprise one or more servers3and other devices operated by service providers and users. Network1also may comprise one or more devices4utilized by users. Service providers and users may provide information to each other utilizing the one or more servers3, which connect to the one or more devices4via cloud2. Servers3may comprise, for example, one or more of general purpose computing devices, specialized computing devices, mainframe devices, wired devices, wireless devices, monitoring devices, infrastructure devices, and other devices configured to provide information to service providers and users. Devices4may comprise, for example, one or more of general purpose computing devices, specialized computing devices, mobile devices, wired devices, wireless devices, passive devices, routers, switches, mainframe devices, monitoring devices, infrastructure devices, and other devices utilized by service providers and users. Example items may include network1, cloud2, servers3, and devices4.

Moreover, network1may comprise one or more systems100that may provide a system performance analysis module and/or a system performance prediction module. System100may be, for example, one or more of a general purpose computing device, a specialized computing device, a wired device, a wireless device, a mainframe device, an infrastructure device, a monitoring device, and any other device configured to provide the system performance analysis module and the system performance prediction module. System100may also be configured to collect data from one or more data sources (e.g., servers, sensors, networks, interfaces, other devices). System100may collect information from network1, cloud2, servers3, devices4, and other devices connected to cloud2. System100may connect to cloud2and monitor network1, cloud2, servers3, devices4, and other devices connected to cloud2for available information. The available information may include processor board information, chips per board information, cores per chip information, threads per core information, measured throughput rate information (e.g., based on industry testing), and other information provided to the system performance analysis module and the system performance prediction module. By collecting the available information from network1, cloud2, servers3, devices4, and other devices connected to cloud2, system100may perform one or more tasks associated with using the system performance analysis module and the system performance prediction module, which is discussed in more detail below. In some configurations, one or more of servers3and devices4may comprise system100. In other configurations, system100may be separate from servers3and devices4.

Generally, computer server capacity planning and enterprise application performance engineering have become areas of considerable interest for businesses looking to optimize performance of their business applications in large and complex systems. In particular, the workloads processed by these applications and infrastructure in which they execute change over time. As such, these companies are primarily interested in determining (1) the impact of such anticipated or hypothetical changes, and (2) when anticipated increases in workload levels will exceed the capacity of the existing infrastructure. To do this, these companies may measure the current performance of their business applications, load-test their applications in a test lab or estimate such measurements during application design, and then build performance models using these measurements and using these models to predict how performance will change in response to anticipated or hypothetical changes to the workloads, applications, and infrastructure.

U.S. Pat. No. 7,957,948 B2, and the continuation Patent Application Publication No. US 2012/0130680 (collectively, “the patent”), which are incorporated herein by reference in their entirety, describe systems and methods for capacity planning for systems with multithreaded multicore multiprocessor resources. This patent generally describes processor architectures utilizing a plurality of CPU chips, with a plurality of cores per chip and multithreading per core, and is directed to facilitating the evaluation of the performance effects of all anticipated changes to workloads, applications, and infrastructure in view of this chip-core-thread structure. For example, this patent discusses the scenario where a source data center configuration is analyzed and source parameters are determined, and a destination data center configuration is analyzed and destination parameters are determined, to help an IT manager to understand what the performance of the destination data center configuration will be relative to the source data center configuration so as to optimize the destination data center configuration for performance, cost, upgradeability or other features. This analysis is particularly important due to the non-linear scalability effects in multi-chip, multi-core and multi-thread environments when hardware resources such as cache memory and disks are shared by these multiple chip, multiple cores and multiple threads. Even with the introduction of multiple levels of cache memory (L2 or L3 cache), memory access continues to be a performance issue because processor speeds (clock rates) have increased by orders of magnitude while memory access speeds have only increased by factors in single or double digits. Thus, this patent provides for a method of analyzing a multi-chip, multi-core, multi-threaded system architecture for the purposes of producing capacity planning in multi-chip, multi-core, and multi-thread environments.

As an example,FIG. 2depicts a multichip-multicore-multithread system. Processor chips200are shown wherein each chip may contain a plurality of microprocessor cores210, a microprocessor core having, for example, its own instruction pipeline. Within each core210, it is possible to fork the instruction pipeline into multiple logical processor threads220, wherein each thread may be activated to execute program instructions for different programs or may be activated to execute instructions in parallel for a single program.

Programming instructions assigned to and being executed on a processor thread is referred to as a task; the terminology “active thread” means a processor thread with a task currently assigned and executing. When processor threads220are activated, the operating system will typically allocate tasks to processor threads most efficiently by minimizing the number of active threads per chip200and minimizing the number of active threads per core210so that on-chip resources are less likely to require sharing.

More recently, however, with the increase in number of cores per chip, computer architects have responded by adding more and larger caches to reduce the number of required access to memory as the memory bus was becoming a performance bottleneck. With even more cores per chip, corresponding to supporting more threads of execution, a common architectural approach has been to design processor boards which incorporate two or four processor chips, and their associated caches, memory chips and a memory bus on a single board. Larger systems are created by supporting multiple such boards in a system running a single instance of an operating system. Inter-board cabling supports access to memory and cache coherency between an execution thread on one board and the memory on a different board but the operating system is “board-aware” and will allocate CPU and memory resources associated with a thread of execution on the same board to the extent possible. Thus, this resource allocation policy significantly reduces the amount of NUMA (“Non-Uniform Memory Access”) behavior exhibited by execution streams.

Since each processor board effectively has memory dedicated to its threads of execution and a private memory bus, there is less contention for access to memory than would occur on a similar sized system with a single shared memory and memory bus. As a result, systems constructed of multiple processor boards typically exhibit higher overall performance that similarly sized systems with a single shared memory and bus. For example, adding another processor board to an existing system will typically exhibit an increase in performance that is closer to linear than adding an equivalent amount of processors and memory to a single, shared memory system.

As an example,FIG. 3depicts a multi-board, multi-chip, multi-core, multi-thread system. Processor boards300are shown wherein each board may contain a plurality of processor chips310, each chip310may contain a plurality of microprocessor cores320, and each core320may have multiple logical processor threads330, wherein each thread may be activated to execute program instructions for different programs or may be activated to execute instructions in parallel for a single program. When processor threads330are activated, the operating system will typically allocate tasks to processor threads most efficiently by minimizing the number of active processor threads per processor core320, minimizing the number of active threads per chip310, and minimizing the number of active threads per processor board300, so that on-board, on-chip, and on-core resources are less likely to be shared.

Thus, the present disclosure seeks to extend the methods of analyzing and capacity planning for multi-chip, multi-core, multi-threaded system environments by analyzing the scalability of a fourth layer of complexity, the processor boards, and incorporating this factor into the calculation of the expected throughput of a system constructed with multiple processor boards. In doing so, the teachings of the present disclosure may provide a system performance analysis module that gathers performance data and analyzes the data by type of boards and chips, number of boards, number of chips per board, number of cores per chip, and number of supported threads per core for the purpose of determining a set of scalability factors, and then employing these scalability factors to multi-board, multi-chip, multi-core, multi-thread system architectures for the purposes of capacity planning.

Referring now toFIG. 4A, system400, which may provide a system performance analysis module, is now described. The system performance analysis module may gather CPU performance data and analyze the characteristics of the operating system, the number of boards, the number of chips per board, the number of cores per chip, and the number of supported threads per core to determine a set of scalability factors, which includes both linear and exponential scaling factors. It is noted that these scalability factors are all less than or equal to 1 for all analyzed systems to date (over 6000) because scalability factors greater than 1.0 would imply that the system becomes more efficient as more boards/chips/cores/threads are added, for which no extant commercial systems have been observed—but neither the analysis methodology nor the scalability representation specifically exclude this (unlikely) possibility.

The system performance analysis module may be located on a device4and accessible via system400, or may be located on cloud2(e.g., a virtual system) and accessible via system400. System100may reside on one or more networks1. System400may comprise a memory402, a CPU104, and an input and output (“I/O”) device406.

Memory102may store computer-readable instructions that may instruct system400to perform certain processes. As discussed above, memory402may comprise, for example, RAM, ROM, EPROM, Flash memory, or any suitable combination thereof. In particular, when executed by CPU404, the computer-readable instructions stored in memory402may instruct CPU404to operate as one or more devices.

CPU404may operate as one or more of a module display device410and a system performance analysis device420. System performance analysis device420may comprise one or more of a work determining device422, a throughput performance determining device424, a thread scalability determining device426, a core scalability determining device428, a chip scalability determining device430, a board scalability determining device432, a total scalability determining device434, and an expected throughput determining device436, as discussed in detail below.

I/O device406may receive one or more of data from networks1, data from other devices connected to system400, and input from a user and/or a system and provide such data to CPU404. I/O device406may transmit data to networks1, may transmit data to other devices connected to system400, and may transmit information to a user (e.g., display the information via a display device). Further, I/O device406may implement one or more of wireless and wired communication between system400and other devices.

Referring now toFIG. 4B, system450, which may provide a system performance prediction module, is now described. The system performance prediction module may employ the scalability factors determined by the system performance analysis module for multi-thread, multi-core, multi-chip, and multi-board system architectures for the purposes of capacity planning.

The system performance prediction module may be located on a device4and accessible via system450, or may be located on cloud2(e.g., a virtual system) and accessible via system450. System450may reside on one or more networks1. System450may comprise a memory452, a CPU454, and an input and output (“I/O”) device456. Similar to memory402and I/O device406described above with respect toFIG. 4A, memory452may store computer-readable instructions that may instruct system450to perform certain processes, and I/O device456may receive data from network1, data from other devices connected to system450, input from a user and/or a system to provide such data to CPU454; transmit data to networks1, other devices connected to system450, and transmit data to a user; and implement one or more of wireless and wired communication between system450and other devices.

CPU454may operate as one or more of a module display device460and a system performance prediction device470. System performance prediction device470may comprise one or more of a system configuration data determining device472, a scalability factor collecting device474, a workload specification device476, and an expected throughput determining device478, as discussed in detail below.

Referring now toFIGS. 5 and 6, processes performed by system performance analysis device420, which analyzes the collected performance data for the purpose of determining a set of scalability factors, are now described.

In step501ofFIG. 5, system performance analysis device420, operating as work determining device422, determines the amount of work performed by a single thread in a single core in a single chip in a single board of a system612comprising a number of N processor boards, where N is an integer greater than or equal to 1 (i.e., measured single thread performance650). System612, for example, may be a Unisys ES7000 Model 7600R, with a processor type Xeon X7460 with a nominal clock frequency of 2667 MHz (FIG. 6). As shown inFIG. 6, N can equal 2, 3, or 4 process boards614(or any other suitable integer number of process boards based on system capabilities). The measured single thread performance650may be determined from SPECint2006, from Standard Performance Evaluation Corporation (SPEC), found on the SPEC.org website.

Then, in step502ofFIG. 5, system performance analysis device420, operating as throughput performance determining device424, determines a plurality of measured throughput performance rates652for each of the number of N processor boards. The measured throughput performance rates652may be determined from SPECint_rate2006, from Standard Performance Evaluation Corporation (SPEC), found on the SPEC.org website. In addition, as shown inFIG. 6, the system with 2 processor boards corresponds to a measured throughput performance rate of 527, the system with 3 processor boards corresponds to a measured throughput performance rate of 788, and the system with 4 processor boards corresponds to a measured throughput performance rate of 1050.

In step503ofFIG. 5, system performance analysis device420, operating as thread scalability determining device426, determines a fit to thread scalability. Specifically, system performance analysis device420determines a fit to thread scalability by determining the number of threads per core associated with the system, determines linear and exponential scalability factors based on the performance throughput of the threads per core, and calculates an effective threads per core result640based on the linear and exponential thread scalability factors. It is noted that both linear and exponential scalability factors are less than or equal to 1.0, as described in Section [33].

Ideally, to determine the thread scalability factors the measured throughput performance data would include measurements with only one thread per core active, two threads per core active, etc., up to the maximum number of threads per core for the system under analysis. In practice, this level of detailed performance data is not available but can be approximated by dividing the maximum throughput of a board by the number of cores (not chips) on the board with the result being a (fairly accurate) estimate of the throughput of a single core with all threads active. If there is a maximum of two threads per core for the system under analysis, this represents a complete set of thread performance data. In this case, the thread scalability can be represented with only a linear scalability factor and the exponential scalability factor set to 1.0. For systems with more than two threads per core (e.g., four or eight) it may be necessary to apply some experience from similar systems to select appropriate linear and exponential factors to fit the two available data points. (For example, from prior experience it may be known that the performance throughput contribution of additional threads beyond two for a particular processor architecture provide limited increases in throughput which will imply an exponential scalability factor smaller (i.e., having a greater impact on performance degradation) than a processor architecture which produces more linear contributions to throughput as additional threads per core become active.)

In the degenerate case where there is a maximum of one thread per core (as in the following example) both the linear and exponential thread scalability factors are set to 1.0 which means that there is no implication to performance throughput attributable to thread scalability. Note that this analysis was discussed extensively in the prior patent.

For example, as shown inFIG. 6, system612may have one thread per core638for each of 2 processor boards, 3 processor boards, or 4 processor boards. In other words, system612only supports one thread per core. Then, because there is only one thread per core, linear thread scalability factor642is determined to be 1, and exponential thread scalability factor644is determined to be 1. In other words, because there is only one thread, no clashing of resources and no scalability effects will occur due to multiple threads per core.

The effective threads per core result640(i.e., the throughput equivalent number of threads per core in use at any time in view of the available resources) is calculated based on the determined linear thread scalability factor642and exponential thread scalability factor644. Specifically, the effective threads per core result640is determined according to:
[1+(T−1)×L(T)]×E(T){circumflex over ( )}(T−1),  Equation 1A
whereT=the number of threads per core associated with the system,L(T)=the linear thread scalability factor, andE(T)=the exponential thread scalability factor.

For system612, the effective threads per core result640is equal to 1 whether the number of processor boards equals 2, 3, or 4 ([1+(1−1)×1]×1{circumflex over ( )}(1−1)=1). In fact, in this analysis based on the maximum throughput of the system for each of the number of boards installed in the system, the effective threads per core in independent of the number of boards installed.

Alternatively, the effective threads per core result640may be determined according to Equation 1B as follows, which is preferable in some cases, but similarly effective in all other cases:
1+[(T−1×L(T)]×E(T){circumflex over ( )}(T−1),  Equation 1B
whereT=the number of threads per core associated with the system,L(T)=the linear thread scalability factor, andE(T)=the exponential thread scalability factor.

Next, in step504ofFIG. 5, system performance analysis device420, operating as core scalability determining device428, determines a fit to core scalability. Specifically, system performance analysis device420determines a fit to core scalability by determining the number of cores per chip associated with the system, determining linear and exponential scalability factors based on the number of cores per chip, and calculating an effective cores per chip result based on the linear and exponential core scalability factors. Ideally, to determine the core scalability factors the measured throughput performance data would include measurements with only one core per chip active (and all threads on that core active), two cores per chip active, etc., up to the maximum number of cores per chip for the system under analysis. In practice, this level of detailed performance data is not available but can be approximated by dividing the maximum throughput of a board by the number of chips on the board with the result being a (fairly accurate) estimate of the throughput of a single chip with all cores and threads active. Using the previously determined single thread throughput performance650and the effective threads per core result640the throughput of a single active core can be computed. If there is a maximum of two cores per chip for the system under analysis, this represents a complete set of core performance data—throughput per core with only one core active and with two (all) cores active. In this case, the core scalability can be represented with only a linear scalability factor and the exponential scalability factor set to 1.0. For systems with more than two cores per chip (e.g., four or eight or sixteen) it may be necessary to apply some experience from similar systems to select appropriate linear and exponential factors to fit the two available data points. (For example, from prior experience it may be known that the performance throughput contribution of additional cores beyond two for a particular processor architecture provide limited increases in throughput which will imply an exponential scalability factor smaller (i.e., having a greater impact on performance degradation) than a processor architecture which produces more linear contributions to throughput as additional cores per chip become active.)

In the degenerate case where there is a maximum of one core per chip both the linear and exponential thread scalability factors are set to 1.0 which means that there is no implication to performance throughput attributable to core scalability. Note that this analysis was discussed extensively in the prior patent.

For example, as shown inFIG. 6, system612may have 6 cores per chip630for each of 2 processor boards, 3 processor boards, and 4 processor boards. In other words, system612supports the use of up to 6 cores per chip. Then, linear core scalability factor634is determined to be 0.98, and exponential core scalability factor636is determined to be 0.90. These scalability factors may be estimated based on, for example, analysis of other similar or suitable systems.

The effective cores per chip result632(i.e., the throughput equivalent number of cores per chip in use at any time in view of the available resources) is calculated based on the determined linear core scalability factor634and exponential core scalability factor636. Specifically, the effective cores per chip result632is determined according to:
[1+(C−1)×L(C)]×E(C){circumflex over ( )}(C−1),  Equation 2A
whereC=the number of cores per chip associated with the system,L(C)=the linear core scalability factor, andE(C)=the exponential core scalability factor.

For system612, the effective cores per chip result632is equal to 3.48 whether the number of processor boards equals 2, 3, or 4 (i.e., [1+(6−1)×0.98]×0.90{circumflex over ( )}(6−1)=3.48). In effect, as the number of active cores per chip increases, due to conflicts in accessing resources, the effective cores per chip result does not scale linearly (the exponential factor is less than 1.0).

Alternatively, the effective cores per chip result632may be determined according to Equation 2B as follows, which is preferable in some cases, but similarly effective in all other cases:
1+[(C−1)×L(C)]×E(C){circumflex over ( )}(C−1),  Equation 2B
whereC=the number of cores per chip associated with the system,L(C)=the linear core scalability factor, andE(C)=the exponential core scalability factor.

Next, in step505ofFIG. 5, system performance analysis device420, operating as board scalability device432, determines a fit to board scalability. Specifically, system performance analysis device420determines linear and exponential board scalability factors based on the relationships of corresponding measured throughput performance rates652associated with N processor boards and N+1 processor boards, and calculates an effective boards result616based on the linear and exponential board scalability factors.

For example,FIG. 6illustrates an exemplary example of the calculation of the expected throughput of a system. As shown inFIG. 6, the number of processor boards614for system612may include 2 processor boards, 3 processor boards, or 4 processor boards. The measured SPECint2006_Rate (throughput)652for the 2, 3 and 4 board configurations are 527, 788 and 1050, respectively. The ratios of these throughput performance values exhibit the scalability of this system as additional boards are added to it. The ratio of the throughput of the three-board system to the two-board system (788/527) is 1.495-almost 1.5. The ratio of the throughput of the four-board to the three-board system (1050/788) is 1.3325-almost 1.33333. The ratio of the throughput of the four-board system to the two-board system (1050/527) is 1.9924-almost 2.0. Clearly, the board scalability of this system is almost “perfect”—doubling the number of boards from 2 to 4 resulted in very nearly doubling the throughput of the system. Since the board scalability appears almost “perfect”, initially set the board exponential scalability to 1.0. Now, using the two-to-four board ration above as a guide, estimate a trial board linear scalability as 0.99. Then, using these trial linear board scalability factor618and exponential board scalability factor620, the effective boards values for each of the 2, 3 and 4 board configuration can be determined from the following equation:
[1+(B−1)×L(B)]×E(B){circumflex over ( )}(B−1), where  Equation 3A:B=the number of N boards associated with the system (i.e., N=2, 3, and 4),L(B)=the linear board scalability factor, andE(B)=the exponential board scalability factor.
Using these trial scalability factors the computed effective boards results616values are 1.99, 2.97 and 3.96, respectively. Use these values to compute scalability ratios corresponding to those previously computed from the measured SPECint2006_Rate throughput. The ratios for the computed effective boards values for three-to-two, four-to-three and four-to-two are 1.4924, 1.3333 and 1.990, respectively. These ratios are almost identical to those computed from the measured throughput values—1.495, 1.3325 and 1.9924, respectively. These board scalability values—0.99 linear and 1.0 exponential—clearly reflect the board scalability expressed in the measured throughput data.
In cases where the computed effective boards ratios do not correspond quite so well to the ratios from the measurement data, some adjustment to the linear and/or exponential board scalability factors may be required to arrive at a set of final board scalability factors.

Alternatively, the effective boards result616may be determined according to Equation 3B as follows, which is preferable in some cases, but similarly effective in all other cases:
1+[(B−1)×L(B)]×E(B){circumflex over ( )}(B−1),  Equation 3B
whereB=the number of N boards associated with the system (i.e., N=2, 3, and 4),L(B)=the linear board scalability factor, andE(B)=the exponential board scalability factor.

Next, in step506ofFIG. 5, system performance analysis device420, operating as chip scalability device430, determines a fit to a chip scalability. Specifically, system performance analysis device420determines a fit to chip scalability by determining the number of chips per board associated with system612, determining linear and exponential scalability factors based on the number of chips per board, and calculating an effective chips per board result based on the linear and exponential chip scalability factors.

Ideally, to determine the chip scalability factors the measured throughput performance data would include measurements with only one chip per board active (and all threads of all cores on that chip active), two chips per board active, etc., up to the maximum number of chips per board for the system under analysis. In practice, this level of detailed performance data is not available but an effective chips per board result624can be calculated based on the previously determined effective threads per core result640, the effective cores per chip result632, the effective boards result616and the measured single thread performance650and throughput performance rate652of the plurality of measured throughput performance rate. This provides a computed effective chips per board result624for each of the throughput performance measurements. Specifically, the set of effective chips per board results624is determined according to:
P(N)/[SP*EB(N)*EC(N)*ET(N)],  Equation 4
whereN is the number of boards for which a measured throughput performance is knownP(N) is the measured throughput performance652for a specific NSP is the single thread performance650of the systemEB(N) is the effective boards value616for a specific NEC(N) is the effective cores value632ET(N) is the effective threads value640

The plurality of computed effective chips per board results624will typically be very similar in value, limited by the accuracy and consistency of the measurement data. A mean or median value may be selected from the set for the effective chips per board values.

From this effective chips per board value624the linear626and exponential628scalability factors can be inferred. If there is a maximum of two chips per board for the system under analysis, the chip scalability can be represented with only a linear scalability factor and the exponential scalability factor set to 1.0. For systems with more than two chips per board (e.g., four or eight) it may be necessary to apply some experience from similar systems to select appropriate linear and exponential factors to fit the computed effective chips per board result.

For example, as shown inFIG. 6, system612has 4 chips per board622for each of 2 processor boards, 3 processor boards, or 4 processor boards. The computed effective chips per board values for the 2, 3, and 4 board configurations are 3.0318, 3.0375, and 3.0356, respectively. An initial estimate of the effective chips per board value may be chosen as 3.035. Note that this estimate was calculated without consideration of operating system scalability. (Determination of operating system “OS”) scalability is described in the prior patent.) In the attached spreadsheet operating system scalability is included in the calculation (since the measured throughput performance was subject to OS as well as hardware scalability) so some minor adjustments may be required to the chip scalability when the OS scalability is included. The finalized linear chip scalability factor626is determined to be 0.937, and exponential chip scalability factor628is determined to be 0.930, resulting in a final effective chips value of 3.07.

The effective chips per board result624(i.e., the throughput equivalent number of chips in use per board at any time in view of the available resources) is calculated based on the determined linear chip scalability factor626and exponential chip scalability factor628. Specifically, the effective chips per board result624is determined according to:
[1+(Ch−1)×L(Ch)]×E(Ch){circumflex over ( )}(Ch−1),  Equation 5A
whereCh=the number of chips per board associated with the system,L(Ch)=the linear chip scalability factor, andE(Ch)=the exponential chip scalability factor.

Alternatively, the effective chips per board result624may be determined according to Equation 5B as follows, which is preferable in some cases, but similarly effective in all other cases:
1+[(Ch−1)×L(Ch)]×E(Ch){circumflex over ( )}(Ch−1),  Equation 5BCh=the number of chips per board associated with the system,L(Ch)=the linear chip scalability factor, andE(C)=the exponential chip scalability factor.

In step507ofFIG. 5, system performance analysis device420, operating as total scalability determining device434, combines (e.g., multiplies) the thread scalability with the core scalability with the chip scalability with the board scalability for each of the number of N processor boards to produce a plurality of total scalability results (i.e., the number of equivalent CPUs)646, wherein each total scalability result646of the plurality of total scalability results is associated with each of the number of N processor boards. For example, as shown inFIG. 6, the total scalability result associated with 2 processor boards is 21, the total scalability result associated with 3 processor boards is 31.43, and the total scalability result associated with 4 processor boards is 41.85. Specifically, the total scalability result is determined according to:
{1+[(B×Ch×C×T)−1]×L(OS)}×E(OS){circumflex over ( )}[(B×Ch×C×T)−1]×(Ef(B)/B)×(Ef(Ch)/Ch)×(Ef(C)/C)×(Ef(T)/T),  Equation 6A
whereB=the number of boards associated with the system,Ch=the number of chips per board associated with the system,C=the number of cores per chip associated with the system,T=the number of threads per core associated with the system,L(OS)=the linear OS system scalability factor (e.g., 0.99),E(OS)=the exponential OS system scalability factor (e.g., 1.00),Ef(B)=the effective boards,Ef(Ch)=the effective chips,Ef(C)=the effective cores, andEf(T)=the effective threads.

It is noted that the linear and exponential OS system scalability factors are determined based on the operating system (e.g., the SUSE® LINUX Enterprise Server 10 (“SLES 10”)) that is being used by system612, and may be determined by measuring system parameters. For example, for system612, the linear OS system scalability factor may be 0.99, and the exponential OS system scalability factor may be 1.00. In addition, it is noted that the computed single thread throughput648is determined by dividing each of the plurality of measured throughput performance rates652(i.e., determined in step502) by the total scalability result646for each of the number of N processor boards. Consistency with the measured single thread throughput650in the plurality of computed single thread throughput648is used as one of the checks on correctness of scalability analysis. A monotonic increase or decrease in these values would imply an error in the board scalability analysis; an outlier usually indicates an error in the measured system throughput performance652.

Alternatively, the total scalability result646may be determined according to Equation 6B as follows, which is preferable in some cases, but similarly effective in all other cases:
1+{[((B×Ch×C×T)−1)×L(OS)]×E(OS){circumflex over ( )}[(B×Ch×C×T)−1]}×(Ef(B)/B)×(Ef(Ch)/Ch)×(Ef(C)/C)×(Ef(T)/T),  Equation 6A
whereB=the number of boards associated with the system,Ch=the number of chips per board associated with the system,C=the number of cores per chip associated with the system,T=the number of threads per core associated with the system,L(OS)=the linear OS system scalability factor (e.g., 0.99),E(OS)=the exponential OS system scalability factor (e.g., 1.00),Ef(B)=the effective boards,Ef(Ch)=the effective chips,Ef(C)=the effective cores, andEf(T)=the effective threads.

Then, in step508ofFIG. 5, system performance analysis device420, operating as expected throughput determining device436, multiplies each of the plurality of total scalability results646with the measured single thread performance650(i.e., the amount of work performed by a single thread in a single core in a single chip in a single board of the system) determined in step501. For example, as shown inFIG. 6, for 2 processor boards, the expected throughput of the system654is determined to be 527.15 (i.e., 21×25.1). For 3 processor boards, the expected throughput of the system654is determined to be 788.81 (i.e., 31.43×25.1). For 4 processor boards, the expected throughput of the system612is determined to be 1050.47 (i.e., 41.85×25.1). In comparing the expected throughput of the system654with the measured throughput performance rates652for each of the number of N processor boards (i.e., determined in step502), it can be seen that the expected throughput of the system654is determined to be very close to the measured throughput performance rates652. Thus, using the above-discussed process, an improved correspondence between the measured and computed performance of system612can be achieved, resulting in the determination of board, chip, core, and thread scalability factors that can better predict real-life system performance.

Referring now toFIGS. 7-10, processes performed by system performance prediction module470, which employing the above-determined scalability factors to multi-board, multi-chip, multi-core, multi-thread system architectures for the purposes of capacity planning (e.g., by computing the predicted throughput of a specific system), is now described.

Referring first toFIG. 7, in step701, system performance prediction module470may identify a system for which performance prediction is desired.

In step702, system performance prediction module470, operating as system configuration data determining device472, obtains configuration data for the system. For example, system performance prediction module470may obtain data from data repository480(e.g., which may be stored in memory402of system400), as shown inFIG. 8. Performance data is tabulated into a set of records800, wherein each record represents a system configuration containing at least a system description802, a processor board type804, a number of processor boards in the system806, a processor chip type808, a number of chips per board810, a number of cores per chip812, a number of threads per core814, a measured single thread throughput performance S_meas816, and a measured system throughput performance rate R_meas818. The measured performances816and818are preferably the SPECint2006 and the SPECint_rate2006 from Standard Performance Evaluation Corporation (SPEC) (which may be found on the World Wide Web at www.spec.org). In one embodiment, SPECint2006 and SPECint_rate2006 data may be periodically scraped from the SPEC website. Alternatively, this performance data may be obtained from other sources such as actual lab measurements or from systems manufacturers. In addition, system configuration data determining device472may further obtain data on hardware resources (e.g., disk drives, memory, and network interface cards), network topography (e.g., describing how the system is interconnected including software dependencies), applications that will run on the system and be simulated, and workload information (e.g., the rate at which applications submit CPU requests to the system, measured CPU utilizations for workloads, etc.).

Proceeding withFIG. 7, in step703, system performance prediction module470may specify a simulation model, as will be further explained with regard toFIGS. 10 and 11below. Then, in step704, system performance prediction module470, operating as scalability factors collecting device474, may look up scalability factors from stored scalability factors (e.g., from data repository460) including linear scalability factors and exponential scalability factors collected based on the specific system configuration. For example, as discussed in detail above with regard toFIGS. 5 and 6, for a Unisys ES7000 Model 7600R system with a Xeon X7460 processor, the scalability factors for board scalability, chip scalability, core scalability, and thread scalability (i.e., taken fromFIG. 6) are shown in Table900ofFIG. 9.

Going back toFIG. 7, in step705, system performance prediction module470, operating as simulation execution device476, may use the scalability factors for the system of interest in the execution of a simulation process for a predetermined simulation time, and then stops the simulation process after it has reached the predetermined end time and outputs a set of results. Then, in step706, system performance prediction module470, operating as an expected throughput determining device478, may determine the throughput of the system and predict the performance of the specific system configuration of the multi-board, multi-chip, multi-core, multi-thread system from the set of simulation results.

In step707, system performance prediction module470, operating as a results storage device480, may store the results of the simulation process (e.g., in memory452or another suitable storage device). After the results are stored, the process terminates.

Different types of results may be determined based on different modeling techniques. For example,FIG. 10illustrates an example of a discrete event simulation process for analyzing the performance of a computer system configuration. In step1001, system performance prediction module470may specify a discrete event simulation model of a computer system configuration using the system parameters described above. Then, in step1002, system performance prediction module470looks up the relevant scalability factors based on the system architecture (e.g., the multi-board, multi-chip, multi-core, multi-thread system). Next, in step1003, system performance prediction module470, using the system parameters and scalability factors, executes the simulation process until a predetermined simulation condition has been reached, at which point the simulation stops. (Predetermined simulation conditions may include, but not be limited to, wall clock simulation elapsed time, a maximum simulated time, achieving a minimum level of statistical stability of results, or a variety of internal conditions such as simulation of the completion of a given number of transactions.) In step1004, system performance prediction module470stores the simulation results, which may include at least average response times for CPU requests and average CPU utilizations, and may also include “break-out” results such as CPU utilization by specific users, user classes, specific applications or transaction types; and larger scale results such as user end-to-end response time including other resource usage. After simulation results are stored, the process terminates.

As another example,FIG. 11illustrates an example of an analytic simulation process for analyzing performance of a computer system configuration. In step1101, system performance prediction module470may specify an analytic model of a computer system configuration using the system parameters described above. Then, in step1102, system performance prediction module470looks up the relevant scalability factors based on the system architecture (e.g., the multi-board, multi-chip, multi-core, multi-thread system), in addition to system scalability factors (e.g., scalability factors that are stored in the memory of the host machine and are available for use in analytic calculations to compute service rate vectors and estimated service times per workload used for standard queuing theory analysis). Next, in step1103, system performance prediction module470computes and stores service rate vectors and estimated service times (based on both the scalability factors associated with the system architecture and the system scalability factors). Then, in step1104, the stored service rate vectors and estimated service times are used to perform queuing theory analysis. After queuing theory analysis is complete, in step1105, results are generated and stored, and these results may include at least the average response time per workload and the estimated average CPU utilization per workload or per sets of workloads submitted at certain submission rates. After results are stored, the process terminates.