Semiconductor structure formed with inductance elements

A semiconductor structure in which the upper and lower semiconductor wafers are bonded by a hybrid bonding method is provided. The two semiconductor wafers each have discontinuous multiple metal traces or spiral coil-shaped metal traces. By hybrid bonding the two semiconductor wafers, multiple discontinuous metal traces are bonded together to form an inductance element with a continuous and non-intersecting path, or the two spiral coil-shaped metal traces are bonded together to form an inductance element. In this semiconductor structure, the inductance element formed by hybrid bonding has the advantage that the inductance value is easily adjusted.

FIELD OF THE INVENTION

The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure formed with inductance elements.

BACKGROUND OF THE INVENTION

A three-dimensional integrated circuit (3DIC) is the latest development of semiconductor packaging, in which a plurality of semiconductor dies are stacked by packaging technology such as package-on-package (PoP) or system-in-package (SiP). Some three-dimensional integrated circuits are formed by stacking semiconductor wafers or dies and using through silicon via (TSV) or Cu—Cu connections to form electrical connections in the vertical direction. Compared with the planar process in prior art, 3D semiconductor devices can not only reduce the occupied area, but also reduce power loss and improve performance.

A hybrid bonding technology is to perform a planarization process on the upper and lower wafers first, and then make the planarized surfaces of the upper and lower wafers contact each other and maintain relative alignment, and then activate the upper and lower wafers to assist the bonding of the upper and lower wafers, and then provide heat treatment and contact pressure to the wafer assembly, and then perform an annealing process to hybrid bond the upper and lower wafers.

Among the various technologies used to stack semiconductor wafers, hybrid bonding technology is currently a project that the industry pays attention to and is actively developed because it can form a high-density electrical connection structure.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor structure, which forms an inductance element with a continuous and non-intersecting path in a hybrid bonding manner, so that the inductance element can produce a required inductance value.

The semiconductor structure provided by the present invention includes a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a first semiconductor substrate and a first inductance layer. The first inductance layer is disposed on the first semiconductor substrate. One side of the first inductance layer away from the first semiconductor substrate has a first bonding surface. The first inductance layer includes a first metal trace, a first interconnect structure and a first insulating layer. The first insulating layer covers the first metal trace. The first interconnect structure is embedded in the first insulating layer and electrically connected to the first metal trace. The second semiconductor wafer includes a second semiconductor substrate and a second inductance layer. The second inductance layer is disposed on the second semiconductor substrate. One side of the second inductance layer away from the second semiconductor substrate has a second bonding surface. The second inductance layer includes a second metal trace, a second interconnect structure and a second insulating layer. The second insulating layer covers the second metal trace. The second interconnect structure is embedded in the second insulating layer and electrically connected to the second metal trace. The first semiconductor wafer and the second semiconductor wafer are coupled to each other. The first bonding surface of the first inductance layer is bonded to the second bonding surface of the second inductance layer. The first insulating layer on the first bonding surface and the second insulating layer on the second bonding surface form a first bond. The first interconnect structure on the first bonding surface and the second interconnect structure on the second bonding surface form a second bond.

In one embodiment of the present invention, the first metal trace has an input terminal and a first terminal. The second metal trace corresponds to the first metal trace. The second metal trace has a connection terminal and a second terminal.

In one embodiment of the present invention, the first interconnect structure is electrically connected to the first terminal. The second interconnect structure is electrically connected to the connection terminal. The second bond is formed by the second interconnect structure and the first interconnect structure. The first metal trace, the first interconnect structure, the second metal trace and the second interconnect structure form a continuous and non-intersecting path between the input terminal and the second terminal and constitute an inductance element.

In one embodiment of the present invention, the first metal trace includes a first coil spiraling inward from the input terminal to the first terminal. The second metal trace includes a second coil spiraling outward from the connection terminal to the second terminal. The second terminal functions as an output terminal.

In one embodiment of the present invention, the first metal trace includes a first coil spiraling outward from the input terminal to the first terminal. The second metal trace includes a second coil spiraling inward from the connection terminal to the second terminal. The second terminal functions as an output terminal.

In one embodiment of the present invention, the first coil and the second coil are arranged correspondingly, and the first coil and the second coil have a same current flow direction.

In one embodiment of the present invention, the first interconnect structure and the first metal trace are integrally formed, and the second interconnect structure and the second metal trace are integrally formed.

The semiconductor structure provided by the present invention includes a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a first semiconductor substrate and a first inductance layer. The first inductance layer is disposed on the first semiconductor substrate. One side of the first inductance layer away from the first semiconductor substrate has a first bonding surface. The first inductance layer includes a start metal trace, a first metal trace, a first interconnect structure and a first insulating layer. The start metal trace and the first metal trace are arranged side by side. The start metal trace has an input terminal and a first terminal. Each of the first metal traces has a first connection terminal and a second connection terminal. The first insulating layer covers the start metal trace and the first metal trace. The first interconnect structure is embedded in the first insulating layer. The first terminal, each of the first connection terminals, and each of the second connection terminals are each electrically connected to one of the first interconnect structures. The second semiconductor wafer includes a second semiconductor substrate and a second inductance layer. The second inductance layer is disposed on the second semiconductor substrate. One side of the second inductance layer away from the second semiconductor substrate has a second bonding surface. The second inductance layer includes a second metal trace, a second interconnect structure and a second insulating layer. The second metal traces are arranged side by side. The second metal trace has a third connection terminal and a fourth connection terminal. The second insulating layer covers the second metal trace. The second interconnect structure is embedded in the second insulating layer. The third connection terminal and the fourth connection terminal are each electrically connected to one of the second interconnect structures. The first semiconductor wafer and the second semiconductor wafer are coupled to each other. The first bonding surface of the first inductance layer is bonded to the second bonding surface of the second inductance layer. The first insulating layer on the first bonding surface and the second insulating layer on the second bonding surface form a first bond. The first interconnect structure on the first bonding surface and the second interconnect structure on the second bonding surface form a second bond. The start metal trace, the first metal trace, the first interconnect structure, the second metal trace and the second interconnect structure form a multi-circle continuous and non-intersecting path and constitute an inductance element.

In one embodiment of the present invention, the first inductance layer further includes an end metal trace. The end metal trace and the first metal trace are arranged side by side. One end of the end metal trace is electrically connected to the one of the second metal traces farthest from the start metal trace, and the other end of the end metal trace functions as an output terminal, so that the start metal trace, the first metal trace, the first interconnect structure, the second metal trace, the second interconnect structure and the end metal trace form a multi-circle continuous and non-intersecting path between the input terminal and the output terminal.

In one embodiment of the present invention, the second inductance layer further includes an end metal trace. The end metal trace and the second metal trace are arranged side by side. One end of the end metal trace is electrically connected to the one of the second metal traces farthest from the start metal trace, and the other end of the end metal trace functions as an output terminal, so that the start metal trace, the first metal trace, the first interconnect structure, the second metal trace, the second interconnect structure and the end metal trace form a multi-circle continuous and non-intersecting path between the input terminal and the output terminal.

In one embodiment of the present invention, the first metal trace is L-shaped and includes a first long side, a first short side, and a first bending portion formed between the first long side and the first short side. The first short side extends along a first direction. The first connection terminal is located at an end of the first long side away from the first bending portion, and the second connection terminal is located at an end of the first short side away from the first bending portion.

In one embodiment of the present invention, a shape of the second metal trace corresponds to that of the first metal trace and is arranged backwards with the first metal trace. The second metal trace includes a second long side, a second short side, and a second bending portion formed between the second long side and the second short side. The second short side extends along a second direction opposite to the first direction. The third connection terminal is located at an end of the second long side away from the second bending portion, and the fourth connection terminal is located at an end of the second short side away from the second bending portion.

In the embodiments of the present invention, by the hybrid bonding of the first semiconductor wafer and the second semiconductor wafer, the conductive traces located on the first semiconductor wafer and the second semiconductor wafer form a continuous and non-intersecting path to form an inductance element with a continuous and non-intersecting path. In addition, the inductance element may produce the required inductance value by adjusting the quantity of discontinuous multi-segment conductive traces or the quantity of loops of the spiral conductive traces in the first semiconductor wafer and the second semiconductor wafer.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG.1is a schematic diagram of a layered cross-section of a semiconductor structure according to an embodiment of the present invention.FIG.2is a schematic cross-sectional diagram of a semiconductor structure according to an embodiment of the present invention. As shown inFIG.1, the semiconductor structure10includes a first semiconductor wafer12and a second semiconductor wafer14. As shown inFIG.2, the first semiconductor wafer12and the second semiconductor wafer14are vertically bonded by hybrid bonding.

The first semiconductor wafer12includes a first semiconductor substrate16and a first inductance layer18. The first inductance layer18is disposed on the first semiconductor substrate16. The side of the first inductance layer18away from the first semiconductor substrate16has a first bonding surface181. The first inductance layer18includes a first metal trace20, a first interconnect structure22and a first insulating layer24. The first insulating layer24covers the first metal trace20. The first interconnect structure22is embedded in the first insulating layer24. One end of the first interconnect structure22is electrically connected to the first metal trace20, and the other end of the first interconnect structure22is exposed on the first bonding surface181. Correspondingly, the second semiconductor wafer14includes a second semiconductor substrate26and a second inductance layer28. The second inductance layer28is disposed on the second semiconductor substrate26. The side of the second inductance layer28away from the second semiconductor substrate26has a second bonding surface281. The second inductance layer28includes a second metal trace30, a second interconnect structure32and a second insulating layer34. The second insulating layer34covers the second metal trace30. The second interconnect structure32is embedded in the second insulating layer34. One end of the second interconnect structure32is electrically connected to the second metal trace30, and the other end of the second interconnect structure32is exposed on the second bonding surface281. The material of the first insulating layer24and the second insulating layer34is silicon dioxide, for example. The material of the first metal trace20, the second metal trace30, the first interconnect structure22and the second interconnect structure32is copper, for example. In an embodiment, the first interconnect structure22and the first metal trace20may be integrally formed; and the second interconnect structure32and the second metal trace30may be integrally formed.

Continue the above description. As shown inFIG.2, hybrid bonding is performed on the first semiconductor wafer12and the second semiconductor wafer14, so that the first bonding surface181(labeled inFIG.1) of the first inductance layer18is bonded to the second bonding surface281(labeled inFIG.1) of the second inductance layer28. The first insulating layer24on the first bonding surface181and the second insulating layer34on the second bonding surface281form a first bond36. The first interconnect structure22on the first bonding surface181and the second interconnect structure32on the second bonding surface281form a second bond38.

In an embodiment, the first semiconductor wafer12and the second semiconductor wafer14may be planarized first when the hybrid bonding is performed, and then the planarized first bonding surface181of the first semiconductor wafer12and the planarized second bonding surfaces281of the second semiconductor wafer14are arranged face-to-face and aligned. Specifically, the first interconnect structure22is aligned and contacts the second interconnect structure32, and the first insulating layer24is aligned and contacts the second insulating layer34. The first bonding surface181and the second bonding surface281are pre-bonded by, for example, Van der Waals force. In an embodiment, an activation process (e.g., plasma treatment) can be performed on the first bonding surface181and the second bonding surface281. The activation process can assist the hybrid bonding of the first semiconductor wafer12and the second semiconductor wafer14. Specifically, the activation process advantageously allows lower contact pressure and heat treatment temperature to be used in the subsequent annealing to hybrid bond the first semiconductor wafer12and the second semiconductor wafer14. In an embodiment, the annealing can strengthen the bonding between the first bonding surface181and the second bonding surface281. For example, the first bonding surface181and the second bonding surface281may be annealed at a temperature of 200° C. to 400° C., and the annealing may be performed for a period of 1 hour to 2 hours. During the annealing, the metals in the first interconnect structure22and the second interconnect structure32contact and then diffuse each other due to thermal expansion to form a metal-to-metal bond. The corresponding first insulating layer24and second insulating layer34can also be bonded to each other at a specified temperature.

FIG.3is a schematic diagram of the configuration of the metal traces and the interconnect structures of the two semiconductor wafers according to a first embodiment of the present invention.FIG.4is a schematic diagram of the metal traces and the interconnect structures of the two semiconductor wafers shown inFIG.3after bonding. As shown inFIG.3, the quantity of the metal traces of the first inductance layer18(labeled inFIGS.1and2) can be plural. For the convenience of description, the plurality of metal traces includes a start metal trace20a, a plurality of first metal traces20band an end metal trace20c. The start metal trace20a, the first metal traces20band the end metal trace20care arranged side by side, and the first metal traces20bare located between the start metal trace20aand the end metal trace20c. The start metal trace20ahas an input terminal201and a first terminal202. Each of the first metal traces20bhas a first connection terminal203and a second connection terminal204. The end metal trace20chas an end connection terminal205and an output terminal206. In an embodiment as shown inFIG.3, the input terminal201, the second connection terminals204and the end connection terminal205are located on the same side (e.g., located on the first side); and the first terminal202, the first connection terminals203and the output terminal206are located on the same side (e.g., located on the second side). The second connection terminals204and the end connection terminal205are each connected to a first interconnect structure22; and the first terminal202and the first connection terminals203are each electrically connected to a first interconnect structure22′.

Correspondingly, the quantity of the second metal traces of the second inductance layer28(labeled inFIGS.1and2) is plural, and the second metal traces30are also arranged side by side. Each of the second metal traces30has a third connection terminal301and a fourth connection terminal302. The fourth connection terminals302are, for example, located on the same side as the input terminal201and the second connection terminals204(e.g., located on the first side). The fourth connection terminals302are each connected to a second interconnect structure32. The third connection terminals301are, for example, located on the same side as the first terminal202and the first connection terminals203(e.g., located on the second side). The third connection terminals301are each connected to a second interconnect structure32′. In an embodiment, the second interconnect structure32electrically connected to the fourth connection terminal302of the second metal trace30(the one farthest from the start metal trace20a) corresponds to the first interconnect structure22electrically connected to the end connection terminal205of the end metal trace20c.

Continue the above description. After the first semiconductor wafer12(labeled inFIGS.1and2) and the second semiconductor wafer14(labeled inFIGS.1and2) are hybrid bonded, the first insulating layer24and the second insulating layer34form the first bond36as shown inFIG.2, and, in addition, the first interconnect structure22/22′ and the second interconnect structure32/32′ respectively form a second bond38/38′ as shown inFIG.4. By the second bonds38and38′, the start metal trace20a, the first metal traces20b, the second metal traces30and the end metal trace20cform a multi-circle continuous and non-intersecting path which constitutes an inductance element40. The output terminal206and the input terminal201are respectively functioned as the output terminal and the input terminal of the inductance element40.

In the above-mentioned first embodiment, the output terminal206of the inductance element40is located on the first semiconductor wafer12as an example. In an embodiment not shown, the end metal trace20cwith the output terminal206is disposed on the second semiconductor wafer14. It is understood that in a figure not shown, the end metal trace20cand the second metal traces30are arranged side by side, and the end connection terminal205of the end metal trace20cis electrically connected with the second metal trace30(the one farthest from the start metal trace20a).

In the above-mentioned first embodiment, the first metal trace20band the second metal trace30are L-shaped, the shape of the second metal trace30corresponds to the shape of the first metal trace20b, and the first metal trace20band the second metal trace30are arranged backwards. In an embodiment as shown inFIG.3, specifically, the first metal trace20bhas a first long side207, a first short side208, and a first bending portion209formed between the first long side207and the first short side208. The first short side208extends along the first direction D1. The first connection terminal203is located at the end of the first long side207away from the first bending portion209. The second connection terminal204is located at the end of the first short side208away from the first bending portion209. Correspondingly, the second metal trace30has a second long side303, a second short side304, and a second bending portion305formed between the second long side303and the second short side304. The second short side304extends along the second direction D2, wherein the first direction D1and the second direction D2are opposite to each other. The third connection terminal301is located at the end of the second long side303away from the second bending portion305. The fourth connection terminal302is located at the end of the second short side304away from the second bending portion305. As shown inFIGS.3and4, the first long side207of the first metal trace20band the second long side303of the second metal trace30are in one-to-one correspondence, so that the first interconnect structure22/22′ and the second interconnect structures32/32′ correspond and bond respectively.

FIG.5is a schematic diagram of the configuration of the metal traces and the interconnect structures of the two semiconductor wafers according to a second embodiment of the present invention.FIG.6is a schematic diagram of the metal traces and the interconnect structures of the two semiconductor wafers shown inFIG.5after bonding. As shown inFIG.5, the first metal trace20has an input terminal201, a first terminal202, and a first coil42that spirals inward from the input terminal201to the first terminal202, for example. The second metal trace30has a connection terminal306, a second terminal307, and a second coil44that spirals outward from the connection terminal306to the second terminal307, for example. The second terminal307may function as an output terminal. The quantity of loops and the shape of the first coil42roughly correspond to those of the second coil44. The first interconnect structure22is provided at the first terminal202of the first metal trace20, and the second interconnect structure32is provided at the connection terminal306of the second metal trace30.

Continue the above description. After the first semiconductor wafer12(labeled inFIGS.1and2) and the second semiconductor wafer14(labeled inFIGS.1and2) are hybrid bonded, the first insulating layer24and the second insulating layer34form the first bond36as shown inFIG.2, and, in addition, the first interconnect structure22and the second interconnect structure32form the second bond38as shown inFIG.6. By the second bond38, the first coil42and the second coil44constitute an inductance element50. The output terminal206and the second terminal307are respectively functioned as the output terminal and the input terminal of the inductance element50. In an embodiment, the currents in the first coil42and the second coil44have the same current flow direction I.

In the above-mentioned second embodiment as shown inFIG.6, the first coil42spirals inward from the input terminal201to the first terminal202, and the second coil44spirals outward from the connection terminal306to the second terminal307(output terminal), so as to form a bond between the inner circle end of the first coil42and the inner circle end of the second coil44; however, the invention is not limited thereto. In an embodiment not shown, the first coil42may spiral outward from the input terminal201to the first terminal202, and the second coil44may spiral inward from the connection terminal306to the second terminal307(output terminal), that is, the first interconnect structure22and the second interconnect structure32form a bond at the outer circle end of the first coil42and the outer circle end of the second coil44.

In the above-mentioned first and second embodiments, by the hybrid bonding of the first semiconductor wafer and the second semiconductor wafer, the conductive traces located on the first semiconductor wafer and the second semiconductor wafer form a continuous and non-intersecting path to form an inductance element with a continuous and non-intersecting path. In addition, the inductance element may produce the required inductance value by adjusting the quantity of discontinuous multi-segment conductive traces or the quantity of loops of the spiral conductive traces in the first semiconductor wafer and the second semiconductor wafer. In addition, the formation of the inductance element has been directly integrated in the back-end process of the wafer and the process of the hybrid bond, and thus, no additional process is required and the effect of simplifying the process is achieved.