Dynamic signal processing

As part of a signal processing event, the maximum frequency of an input signal can be determined with a processor. The maximum frequency can be compared to a value generated with a decimator/interpolator. Based on the comparison, the sampling rate for sampling the input signal with the processor can be set as part of the digital signal processing event. The sampling rate can be adjusted as the frequency of the input signal varies during the signal processing event.

BACKGROUND

The present disclosure relates to signal processing systems, and more particularly, to digitally processing signals exhibiting variable frequencies.

Digital signal processing (DSP) is in many instances an important component of the way in which a computer or similar type system receives externally generated signals and processes the signals into usable data output. DSP is for many such systems the technology that allows a system to interact with and “understand” the environment in which the system operates. Signal processing techniques have broad applicability in fields such as image recognition, speech recognition, autonomous vehicles, robotics, machine learning and many other applications. Such applications are usually implemented with a system having considerable processing capabilities, as the processing requirements are directly proportional to the bandwidth of the system. Accordingly, such systems can be characterized as processor-intensive. The maximum bandwidth the system supports can dictate the system's power requirements.

SUMMARY

A method includes determining, with a processor, a maximum frequency of an input signal. The method can include comparing the maximum frequency to a current decimator/interpolator value. Based on the comparison, the method can include setting a sampling rate for sampling the input signal with the processor as part of a digital signal processing event.

A system includes at least one processor programmed to initiate executable operations. The executable operations can include determining a maximum frequency of an input signal. Additionally, the executable operations can include comparing the maximum frequency to a current decimator/interpolator value. The executable operations also can include setting a sampling rate for sampling the input signal based on the comparison as part of a digital signal processing event.

A computer program product includes a computer-readable storage medium having program code stored thereon, the program code executable by a computer to initiate operations. The operations can include determining, with a processor, a maximum frequency of an input signal. Additionally, the operations can include comparing the maximum frequency to a current decimator/interpolator value. The operations also can include setting a sampling rate for sampling the input signal with the processor, based on the comparison, as part of a digital signal processing event.

DETAILED DESCRIPTION

The present disclosure pertains to signal processing systems. The processing requirements of such a system are in many instances directly proportional to the bandwidth supported by the system.

For a discrete signal processing system, the sampling rate is at least twice the desired maximum frequency. The frequency (e.g., the desired maximum frequency) is usually the highest frequency which a sampled data system can reproduce without error. For example, if in processing an audio signal with a speech recognition system the expected maximum frequency of the speaker's speech is 3 kHz, then the sampling rate must be at least 6 kHz to capture the expected maximum frequency. Downstream filters and processing blocks also operate at the rate of at least 6 kHz. Similarly, with fast Fourier transform (FFT) analysis used, for example, in image recognition the same requirement applies with respect to edge detection and image characterization algorithms. Other examples apply equally as well.

There is a direct relationship between the bandwidth a system supports and the system's power requirements. Accordingly, the maximum bandwidth a system is designed to support dictates the system's power requirements. To conserve power, some systems are designed to operate in two states, namely, an active state and a power-conserving idle state. Such a system conserves power by severely constraining or ceasing processing while in an idle state.

The methods, systems, and computer program product disclosed herein provide a different approach to signal processing by implementing a signal processing system that dynamically adjusts data rate processing frequency as signal frequencies vary. According to one embodiment, a dynamic data rate signal processing system enables adjustment of the processing frequency of a central processing unit (CPU) or other processor in real time.

A dynamic data rate signal processing system, as disclosed herein, can provide just enough processing speed to ensure capture of the highest frequency of a data stream by a signal processor or processing algorithm. If, for example, the frequency within the data stream fluctuates, the system processor's speed is capable of adjusting so that the signal processor or processing algorithm has adequate processing resources to handle the data stream without undue expenditure of energy. The system thus tends to minimize energy usage. The benefit of such an approach is especially pronounced for any signal processing system designed to process an incoming data stream at a frequency that is dynamic over a broad range. If the variation is considerable, the system can generate substantial reductions in power consumption.

FIG. 1depicts certain operative features100of one embodiment of a system for dynamically setting rates for sampling a signal input. A signal from a source (not shown) is received at block102. The signal can be, for example, the output of an analog-to-digital converter (ADC). The received signal can be a digital stream from, for example, a voice recording or other source of digitized signals. The data enters the system at a fixed number of samples per second. Although the system receives a fixed-rate data stream, in other embodiments, the system can receive a variable-rate data stream.

The signal is filtered at block104by a low-pass filter. The filter can be, for example, a finite impulse response (FIR) filter or other type of filter for facilitating the processing of digital signals in the context of different applications. A value representing the frequency of the sample is extracted at block106by a frequency extractor. The value can be extracted for example by the process of conjugate multiplication (e.g., multiplication of a complex representation of the signal by the signal's complex conjugate). The multiplier (gain) value can be fixed and is related to the sampling rate (samples per second) by the radians-per-second gain of the output at block108.

As noted above, the system's power consumption is influenced by the signal bandwidth that the system is required to handle during a signal processing event. Power consumption is also affected by the nature and extent of the signal processing performed. For example, if the low-pass filter is a FIR filter, the filter architecture comprises a sequence of coefficient-delay pairs, typically termed “taps.” Referring additionally toFIG. 2, the logical structure of an example FIR filter is shown, with outputs y2, y1, y0generated by feeding inputs f2, f1, f0into the three-tap filter comprising coefficients h2, h1, h0; the delays are indicated as z−1. Although, FIR filter200illustratively comprises only three taps, it is not unusual for such a filter to comprise as many as 1,000 or more taps. Thus, for every sample input into the system, that sample and the 999 prior samples must run through the filter to generate an output sample. Other signal processing systems exhibit similar processing intensity-resource consumption correlations.

In the context of digital signal processing, one consideration is the number of samples of the signal needed per period to capture the maximum frequency of the signal bandwidth. According to Nyquist's theorem, accurate representation of the signal requires that the system sample the signal at a sampling rate greater than twice the highest frequency component present in the signal. This consideration underpins the approach taken with the system disclosed herein for dynamically setting rates for sampling a signal.

Following the approach, the system adjusts a processor's core frequency as the frequency of a signal processed by the system varies. The core frequency indicates the processing speed of a processor (e.g., CPU) or a single core of a multi-core processor and is typically measured as clock cycles per second or, equivalently, Hertz. The system affects the processor core frequency by dynamically adjusting signal sampling frequency as the frequency of the signal input, or data stream, being sampled varies. The system can dynamically adjust the signal sampling frequency in real time. The system dynamically sets the system's sampling rate depending on the highest frequency component of the signal input, or data stream, that the system needs to capture to adequately process the signal input.

The sampling rate of the input signal can be changed at block110by interposing between the signal input and the downstream low-pass filter a mechanism for setting the sampling rate. The mechanism can comprise a dual-function sampling rate decimator/interpolator. The decimator/interpolator can decrease or increase the sampling rate in response to a control signal.

The decimator/interpolator increases the sampling rate by estimating intermediate sample values (interpolation), each of which is inserted into the sequence at the point of interpolation. The decimator/interpolator decreases the sampling rate by a process of decimation. A sequence of sampled values is decimated, or “downsampled,” by a factor of D if every Dthsample is retained and the remaining samples are discarded. Accordingly, relative to the original sample rate fold, the new sample rate fnewis
fnew=fold/D

For example, to decimate a sequence xold(n) by a factor of D=3, xold(0) is retained while xold(1) and xold(2) are discarded; xold(3) is retained while xold(4) and xold(5) are discarded; xold(6) is retained, and so on. Accordingly, xnew(n)=xold(3n), where n=0, 1, 2, . . . , N (N is any integer). The sample resulting from the decimation process is that which would have been generated by sampling the same signal albeit at a rate of fnew.

Referring additionally toFIG. 3, decimation200is illustrated by juxtaposing the original sequence300(a) and the newly decimated-by-three sequence300(b). Also referring additionally toFIG. 4, the spectral implications of decimation are illustrated assuming an original continuous signal. The spectrum of the original bandlimited signal is indicated by the solid lines.400(a) shows Xold(m), the discrete replicated spectrum of xold(n).300(b) shows Xnew(m), the discrete spectrum of xnew(n)=xold(3n).

Referring still toFIG. 1, as needed, an adjustment to the sampling rate is made at block110by incrementing (e.g., interpolating) or decrementing (e.g., decimating) the current sampling rate. The determination of whether—and if so, by how much—to increment or decimate the signal sampling rate at block110is made through feedback loop112. Two inputs are fed to feedback loop112: the maximum frequency of the sample, determined by frequency extraction at block114, and a current decimator/interpolator value for adjusting/setting the sampling rate. (The value is zero if no adjustment is needed; otherwise the value indicates how many samples to decimate or interpolate.) If the current sampling rate is below a rate necessary to capture the highest frequency component of the signal, the decimator/interpolator increases the rate by implementing the interpolation process described above. Conversely, the sampling rate is decimated if the current sampling rate is above the rate need to capture the highest frequency component, which per the Nyquist theorem should be above twice the highest frequency component of the signal. The sampling rate changes in response to the feedback provided by feedback loop112as the frequency of the input signal, or data stream, varies.

For example, if the system as currently configured samples at a rate of 6 kHz but need only process a 2.5 kHz signal, the decimator/interpolator at block110decimates or downsamples the sampling rate to 5 kHz, twice the 2.5 kHz signal. A gain value for the filter can be calculated in real time to ensure a ±2.5 kHz output. Optionally, a response “window” of x % can be added to the highest frequency, which enables feedback loop112to scale up or down to ensure adequate bandwidth coverage. For example, a 10% window would ensure that though a 2.5 kHz bandwidth is assumed, the system can accurately measure up to 2.75 kHz.

When the input frequency increases up to the maximum of the x %-window, the system in one embodiment reverts to the maximum sampling rate the system is configured to handle (e.g., with a maximum 3 kHz bandwidth, a 6 kHz sampling rate can be the default setting that is decimated only if the system needs to capture a lower frequency). If the system is oversampling at that rate, the decimator/interpolator at block110can repeat the procedure of downsampling until the signal input frequency is within the x %-window. In alternative embodiment, the decimator/interpolator block at110can respond to the signal input frequency reaching the x %-window maximum by iteratively increasing the sampling rate (up to a maximum imposed, for example, by hardware constraints). The sampling rate can be increased by the system halting downsampling so that no samples from a data stream are discarded. If needed to further increase the sampling rate, additional samples can be obtained by interpolation. Sampling can be increased until a new x %-window is centered on the maximum frequency component of the signal input.

In one embodiment, the system receives a fixed-rate data stream and is configured to operate at a default data rate that is decimated only if the default data rate is higher than that of the received data stream. If the default rate of the system is higher than that of the received data stream, the system is capable of scaling down to the appropriate data rate to match that of the received data stream. For example, if as in the previous example, the default setting is a 6 kHz sampling rate but the rate of the received data stream is 2.5 kHz, then the system can scale down to a 5 kHz sampling rate. The system, as described above, resets to the default data rate when the system detects a reset condition (e.g., detect data stream frequency at the top of the x %-window, detect a reset signal, detect lack of input signal for a predetermined length of time).

As described below, the system can change the processor core frequency as the sampling rate changes. To conserve power, the processor core frequency can be reduced as the sampling rate is decreased. In the event that the signal input frequency reaches the x %-window maximum, the system can increase the processor core frequency to accommodate a corresponding increase in the sampling rate as the system adjusts the maximum and minimum of the x %-window to the now-higher maximum frequency.

In one embodiment, feedback loop112for adjusting the decimator/interpolator at block110is implemented with proportional, integral, and derivative (PID) control. A proportional component or coefficient, Kp, can reflect a difference between a current sampling rate and a rate that captures the highest frequency component. An integral component or coefficient, Ki, can reflect, and if necessary, compensate for any differences accumulated over time. A derivative component or coefficient, Kd, can compensate, if necessary, for rapid fluctuations in the difference between the sampling rate and the rate that captures the highest frequency component. The Kp, Ki, and Kd coefficients can be tuned, or adjusted, to generate a new decimator/interpolator value based on comparing the maximum frequency of the sample, determined by frequency extraction at block114, and the current decimator/interpolator value. The new decimator/interpolator value determines the decrease or increase in the sampling rate as the input signal frequency changes up or down.

In another embodiment, the signal filtering at block104dynamically adjusts rates for sampling a signal input in the specific context of digital signal processing performed with a FIR filter. Power consumption in processing a signal with a FIR filter can be influenced by the number of taps (coefficient-delay pairs) of the FIR filter. The number of taps can be affected by the sampling rate. For example, the so-called “Harris rule of thumb” approximates the number of taps, Ntaps, with the following equation: Ntaps=attenuation (dB)/(22*BT), where BTis a normalized transition band equal to the ratio the difference between the stop and pass band frequencies, ΔF=Fstop−Fpass, relative to the sampling rate, Fs. (See, e.g.,Multirate Signal Processing for Communication Systems, Fredric J. Harris (2004), at p. 216.)

With this embodiment, the system includes multiple groups of pre-calculated FIR taps, each group corresponding to a specific sampling frequency. For example, the system can be implemented with a lookup table, each entry of which is a row vector vT=(fsi, ci1, . . . , cin), i=1, 2, . . . , m, where m and n are any, not necessarily equal, integers; fsiis a sampling rate extracted based on the incoming signal as described above; and ci1, . . . , cin, are the pre-calculated coefficients of the ithgroup of taps corresponding to frequency fsi. If the FIR filter is implemented with processor-executable code, the coefficient values can be read from the table and used to process in the signal input. If the FIR filter is implemented in hardwire circuitry, the coefficient values can be used to set the filter parameters. For a particular frequency, the system selects a correct one of the m groups of taps for filtering the incoming signal, the group of taps configured to provide sufficient processing capability but no more than necessary to thereby mitigate power consumption. For example, one group of taps can comprise 100 taps whereas another only 50 taps. In one embodiment, the latter group of taps is constructed by including every other tap (first, third, etc.) of the former group and is used when signal processing can be performed with only 50 taps, making the use of 100 taps an unnecessary drain of power.

In one embodiment, frequency is extracted at blocks106and114using quadrature demodulation (e.g., with a quadrature demodulator). A quadrature demodulator performs conjugate multiplication and in complex number theory provides an output with a linear relationship to the frequency contained within an I/Q stream. (The I/Q stream can be generated using I/Q digital signal processing and multiplying the discrete sample values by a complex exponent ejω=cos ω+j sin ω, where ω denotes the frequency.)

In other embodiments, the frequency extraction at blocks106and114can be implemented using various techniques. In one embodiment, for example, the system can use fast Fourier transforms (implemented, for example, in processor-executable code). In another embodiment (also implemented, for example, in processor-executable code), frequency extraction can be implemented using for example wavelet transforms that break down the input signal as a weighted sum of time-limited functions (wavelets). Other known techniques also can be used to extract a frequency as part of dynamically setting sampling rates.

FIG. 5depicts an example arrangement (processor-executable code, hardwired circuitry, or a combination thereof) that in some embodiments can be used for extracting a signal frequency at block106and/or block114using conjugate multiplication. The example arrangement operates by generating an I/Q digital stream from an incoming signal (illustratively, an analog signal) and extracting the signal frequency by conjugate multiplication. Signal source502is illustratively input into delay unit506. Delay unit506creates a sine and a cosine signal. The cosine signal is generated by delaying the sine signal by 90°. The output of delay unit506refers to the signal diagram520. Multiplier508receives the output signals of the signal source502and the delay unit506for the Q stream; and multiplier510receives an output of the delay unit506for the I stream. A float-to-complex converter512uses the Q data stream and the I data stream as input. An output signal of the float-to-complex converter512is shown in the diagram522, in particular, the I/Q data stream overlaid on the source signal.

Low pass filter514follows in the signal stream with, for example, the following characteristics: decimation: 1 [1/sec]; sample rate 44.1 [kHz]; cut-off frequency: 1.5 [kHz]; transition width: 200; window: Hamming beta: 6.76. The output of low pass filter514is fed to quadrature demodulator516, which illustratively has a gate of 7.01874 k. Quadrature demodulator516is a conjugate multiplication block and thus in complex number theory provides an output with a linear relationship to the frequency contained within the I/Q stream. Low pass filter518illustratively has the following characteristics: decimation: 1 [1/sec]; gate 1; sample rate 44.1 [kHz]; cut-off frequency: 400 [Hz]; transitions width10; window: Hamming beta 6.76. It is noted that, here, the term ‘decimation’ specifically relates to a decimation of signal samples per second. So, if one has 1000 samples per second and one decimates by 10 then there are only 100 samples as output. (This also can relieve the processor and other circuits from an overload, as well as mitigate power consumption.) The transition width makes the −3 dB frequency window. An extracted frequency pattern is shown in diagram526.

FIG. 6depicts an example system for dynamically setting rates for sampling a signal input, according to one embodiment, in which the input is digitized and enters the system at a fixed number of samples per second. Signal source602provides a digital signal having the following characteristics: sample rate: 10 [kHz]; waveform: cosine; frequency: 10 [kHz]; amplitude: 1; offset: 0. Low pass filter604has the following characteristics: decimation 1 [1/sec]; gain: 1; sample rate 80 [kHz]; cutoff frequency 20 [kHz]; transition width800; beta 6.76. Interposed between signal source602and low pass filter604is sample rate decimator606(decimation initially 1, as above inFIG. 5) and quadrature demodulator608(gain: 25.4648). Quadrature demodulator608performs conjugate multiplication to extract a value representing frequency, which is provided to PID control loop610. PID control loop610controls sample rate decimator606, changing the sampling rate by decimating or increasing the current rate as necessary such that the sampling rate is just enough greater than twice the signal's highest frequency component to accurately process the signal. The filtered signal output from low pass filter is fed to quadrature modulator612(gain: 25.4648·decimation as set by sample rate decimator606). Quadrature modulator612extracts frequency (conjugate multiplication) output614. The frequency output614can be input into a control loop that controls a decimator/interpolator for dynamically setting a sampling rate as the frequency of the input signal varies.

FIG. 7depicts one embodiment of a method700of dynamically setting sampling rates during a data processing event. The method can be performed by a system having the operative features and capabilities described inFIGS. 1-6. The system illustratively determines the maximum frequency component of an input signal at702. At704, the system compares the maximum frequency component to a current value of a decimator/interpolator, the current value being the amount by which the sampling rate is decimated or interpolated. The system sets the sampling rate for sampling the input signal at706. The system sets the sampling rate based on the comparison of the maximum frequency component and decimator/interpolator value made at704.

Method700provides a mechanism for dynamically adjusting sampling rates, which in turn can mitigate power consumption of a system during a data processing event.FIG. 8illustrates a method, according to another embodiment, of influencing a system's power consumption by setting a core processing rate in conjunction with and based on a dynamically set sampling rate. The method can be performed by a system having the operative features and capabilities described inFIGS. 1-6.

As illustrated inFIG. 8, method800can begin with the system determining a maximum frequency component of an input signal at802. At804, the system compares the maximum frequency component with a current decimator/interpolator value. The system adjusts the sampling rate at806. The sampling rate can be thus be set to ensure the system can accurately process the system by sampling at a rate just greater than twice the frequency of the highest component present in the signal (based on the Nyquist theorem). The sampling rate need only be slightly greater than twice the maximum frequency component. If the sampling rate is much higher, the system can decimate the sampling rate until the rate is just high enough to capture the highest frequency component, but no higher. The system at808generates a core frequency control value and adjusts the processor core frequency of a signal processor based on the generated core frequency control value. Specifically, in one embodiment, the core frequency control value, CPUf, is pre-calculated as a ratio between samples per second through the signal processing system and a CPU core frequency. The CPU core frequency is set as follows: CPU core frequency=F*CPUf, where F is the highest frequency component.

FIG. 9depicts another embodiment a method900for dynamically setting sampling rates during a data processing event. The method also can be performed by a system having the operative features and capabilities described inFIGS. 1-6. The system determines a maximum frequency component of an input signal at902. At904, the system compares the maximum frequency and a current value of a decimation/interpolator. If the current sampling rate is just slightly more than twice the maximum frequency component (e.g., sampling rate=[2×(maximum frequency component)]+ε; 0<ε<<1), the sampling rate is set at that rate at908. Otherwise, at906the sampling rate is adjusted up (e.g., interpolation) or down (e.g., decimation or downsampling). The adjustment of the sample rate is repeated as necessary until the current sampling rate is just slightly more twice the maximum frequency component and set at that rate at908.

The methods described inFIGS. 7-9for dynamically setting a rate for sampling a signal can be implemented in processor-executable code, in hardwired circuitry, or a combination code and circuitry. Dynamically setting the rate for sampling a signal can be performed (e.g., in real time) during a signal processing event. Dynamic rate setting as disclosed herein can be performed as part of a signal processing procedure (e.g., digital signal processing) executed on a computer or by another system or device for performing signal processing.

FIG. 10depicts a signal processing environment1000in which a rate for sampling a signal can be dynamically set. Signal processing environment1000illustratively includes an example computer1012with which sampling rates can be dynamically set in conjunction with the processing of a signal as the signal frequency varies. The sampling rate can be adjusted as the frequency varies to thereby set a rate that mitigates power consumption by the computer. Computer1012is only one example of a suitable system for implementing the various signal processing operations and procedures disclosed herein. Accordingly, computer1012is not intended to suggest any limitation as to the scope of use or functionality of embodiments described herein. Regardless, computer1012is capable of implementing and/or performing any of the functionality set forth hereinabove.

Computer1012is operational with numerous other general- or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and/or configurations that are suitable for use with computer1012include, but are not limited to, personal computers, servers, thin clients, thick clients, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed cloud computing environments that include any of the above systems or devices, and the like.

Illustratively, computer1012is a general-purpose computing device. The components of computer1012can include, but are not limited to, one or more processors1016, a memory1028, and a bus1018that couples various system components including memory1028to processor1016.

Computer1012typically includes a variety of computer-readable media. Such media can be any available media that is accessible by computer1012, and includes both volatile and non-volatile media, removable and non-removable media.

Memory1028can include computer-readable media in the form of volatile memory, such as random-access memory (RAM)1030and/or cache memory1032. Computer1012can further include other removable/non-removable, volatile/non-volatile computer storage media. By way of example, storage system1034can be provided for reading from and writing to a non-removable, non-volatile magnetic media (not shown and typically called a “hard drive”). Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”), and an optical disk drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media can be provided. In such instances, each can be connected to bus1018by one or more data media interfaces. As further depicted and described below, memory1028can include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.

Program/utility1040, having a set (at least one) of program modules1042, can be stored in memory1028by way of example, and not limitation, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data or some combination thereof, can include an implementation of a networking environment. Program modules1042generally carry out the functions and/or methodologies of embodiments of the invention as described herein.

Program/utility1040is executable by processor1016. Program/utility1040and any data items used, generated, and/or operated upon are functional data structures that impart functionality. As defined within this disclosure, a “data structure” is a physical implementation of a data model's organization of data within a physical memory. As such, a data structure is formed of specific electrical or magnetic structural elements in a memory. A data structure imposes physical organization on the data stored in the memory as used by an application program executed using a processor.

Computer1012can also communicate with one or more external devices1014such as a keyboard, a pointing device, a display1024, etc.; one or more devices that enable a user to interact with computer1012; and/or any devices (e.g., network card, modem, etc.) that enable computer1012to communicate with one or more other computing devices. Such communication can occur via input/output (I/O) interfaces1022. Computer1012can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet) via network adapter1020. As depicted, network adapter1020communicates with the other components of computer1012via bus1018. It is understood that, although not shown, other hardware and/or software components could be used in conjunction with computer1012. Examples include, but are not limited to, the following: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems.

The processing speed of computer1012is determined by the core frequency of processor1016. The processor core frequency can be controlled by core frequency controller1050.

Computer1012can digitally process an input signal, or data stream, received from one of external devices1014via I/O interface1022. The input signal can be, for example, the output of an ADC that converts an analogue signal into a digital stream or a digital stream such as a voice or video recording. The input signal can thus be received at fixed number of samples per second. The computer1012performs digital signal processing on the input signal by executing with processor1016processor-executable code stored in memory1028and conveyed to the processor from the memory via bus1018.

A system for dynamically setting the sampling rate of the input signal and setting a core frequency control value, as described above, can be implemented as processor-executable code, which also can be stored in memory1028and executed by processor1016when conveyed to the processor from the memory via bus1018. The system dynamically sets the sampling rate and based on the sampling rate determines core frequency control value1052. Core frequency control value1052is fed to core frequency controller1050. Operatively, as the frequency of the input signal varies, the sampling rate is adjusted accordingly and a new core frequency control value determined, which is then conveyed to the core frequency controller1050to adjust the processor core frequency.

FIG. 11depicts a processing device1100that operates in conjunction with a system1102for dynamically adjusting the rate for sampling an input signal, or data stream, and setting a core frequency control value based on adjusted sampling rates, according to another embodiment. Processing device1100can comprise a general-purpose or application-specific computer or other device having signal processing capabilities (e.g., digital signal processor). Processing device1100illustratively includes processor1104, memory1106, and I/O interface1108, each communicatively coupled via bus1110. The processing speed of processing device1100is controlled by core frequency controller1112.

Processing device1100processes an input signal, or data stream, received from an external source (not shown) via I/O device1108. As the input signal frequency varies, system1102dynamically adjusts the sampling rate as described above. As also described above, system1102determines a core frequency control value based on each sampling rate. The core frequency control value is conveyed to core frequency controller1112, which determines based on the core frequency control value the processor core frequency of processor1104. As the frequency of the input signal varies, the sampling rate is adjusted accordingly and a new core frequency control value is determined, which is conveyed to the core frequency controller1112. Thus, the processor core frequency varies as the input signal frequency varies in a manner that mitigates power consumption by the processing device1100.

Core frequency controller1112is illustratively a separate component of processing device1100. In other embodiments, however, core frequency controller can be implemented in processor1104(e.g., as processor-executable code). System1102also can be implemented in hardwired circuitry within processing device1100or as a separate device, external to and detachably connectable with (e.g., adapter or plug-in), the circuitry of processing device1100. In other embodiments, system1102like core frequency controller1112also can be implemented in processor1104(e.g., as processor-executable code as described in reference toFIG. 10). Accordingly, the energy-saving benefits of setting a core frequency based on a dynamically adjusted sampling rate can be achieved without specialized circuitry.

The methods disclosed herein also can be implemented in a computer program. The computer program can be stored and implemented in a computer program product. A computer program product includes a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out the various operations disclosed herein.

Computer readable program instructions for carrying out operations of the present invention can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the “C” programming language or similar programming languages.

With respect to any aspects of the embodiments described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products, it is to be understood that each such flowchart illustration, block diagram, and combination of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

FIGS. 1-11are conceptual illustrations allowing for full explanation of the embodiments disclosed herein. The figures and examples disclosed are not meant to limit the scope of the disclosure to a single embodiment, as other embodiments are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the disclosure are described; detailed descriptions of other portions of such known components are omitted so as not to obscure any aspects of the embodiments disclosed. In the present specification, an embodiment showing a singular component should not necessarily be limited to other embodiments including a plurality of the same component, and vice-versa, unless explicitly stated otherwise herein. Moreover, applicants do not intend for any term in the specification or claims to be ascribed an uncommon or special meaning unless explicitly set forth as such. Further, the disclosure encompasses present and future known equivalents to the known components referred to herein by way of illustration.