ESD transistor and a method to design the ESD transistor

An IC design that has an ESD transistor is disclosed. The IC includes a transistor, a ballast resistor, a routing structure and a coupling. The transistor includes a gate, a source and a drain. The ballast resistor is extending parallel to the gate of the transistor. The coupling connects the source of the drain of the transistor the ballast resistor. The routing structure connects the ballast resistor to the remaining of the circuitry. A method to design the IC is also disclosed. The ESD transistor provides means of protection against the ESD surges.

BACKGROUND

Electrostatic discharge (ESD) is defined as a sudden and momentary electric current that flows between objects. ESD occurs when there is a significant electrical potential difference in between two objects. ESD may occur through a direct contact or through an electrostatic field induction. ESD is a common problem in a semiconductor industry and poses a serious threat to integrated circuits (ICs) in particular. ICs may suffer permanent damage when subjected to the relatively high voltages that occur during ESD events. As a result, there are now a number of ESD protective devices that help to prevent permanent damage.

The circuitry commonly used to protect ICs during an ESD event is an ESD transistor. The ESD transistor only permits a constant current between input and output (TO) paths. Such feature of only permitting a constant current provides protection against damages to the IC in the event of ESD. The ESD transistor functions like a ballast resistor towards the ESD current. In the event of ESD, the ballast resistor provides protection to critical circuitries within the ICs.

As the IC industry moves from one process node to another, the ESD transistor has moved from a design to another design accordingly. At different process nodes, different design rules are applicable. The ESD transistor designs that work on a former process might not work for a different process node. In addition, for newer generation process nodes, the distance in between structures within the IC continues to shrink. Ballast resistance is a function that depends on distances the ESD current propagates on the ballast resistor. The ballast resistor design from the older process generation, typically, may not function as effectively on the newer generation process. As the ESD transistor structure shrinks, the ballast resistance effectiveness decreases and the ESD transistor may be unable to be placed in a smaller node.

It is within this context that the embodiments described herein arise.

SUMMARY

Embodiments of present invention provide an ESD transistor and a method to design the ESD transistor.

It should be appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.

In one embodiment, an IC that has an ESD transistor is described. The IC includes a transistor, a ballast resistor, routing structures, and couplings. The transistor further includes a gate, a source and a drain. The ballast resistor is placed adjacent to the transistor and extends parallel to the gate of the transistor. In one embodiment the ballast resistor is placed on a non-diffused area of the IC. The ballast resistor is connected to the source or the drain by a coupling. The coupling includes a metal strip disposed in a layer located above the transistor and a first connector that connects the metal strip to the diffused area and a second connector that connects the metal strip to the ballast resistor. The first and second connectors are located in a plane perpendicular to the plane where ballast resistor is placed. The metal strip is in the plane parallel to the ballast resistor. A routing structure connects the ballast resistor to remainders of the IC. The routing structure includes a metal strip and a connector. The connector, for the routing structure, connects the ballast resistor to the metal strip. The connector is in a plane perpendicular to the ballast resistor and the metal strip is parallel to the ballast resistor in one embodiment.

In another embodiment, a method to design the IC with the ESD transistor is described. The method includes designing two diffused regions with a different dopant type than the dopant on the substrate. Then, a gate composed of a polysilicon or a metallic material, wherein the gate has the purpose of switching on or off for the transistor, is placed in between the diffusion area, i.e., the two diffused regions. Another gate composed of a polysilicon material and also referred as the ballast resistor or dummy gate is placed adjacent to one of the two diffused regions. Couplings are designed to connect the diffused region to the ballast resistor or the dummy gate. Then, the routing structures are designed to connect the ballast resistor or the dummy gate to the remainder of the IC. The routing structure and the coupling are positioned sequentially in alternating fashion along the ballast resistor or the dummy gate in one embodiment. The distance between the sequential coupling and routing structure is adjusted to attain an optimized ballast resistance.

DETAILED DESCRIPTION

The following embodiments describe an Electrostatic Discharge (ESD) transistor and a method to design the ESD transistor.

It will be obvious, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present invention.

The embodiments described below illustrate an ESD transistor and a method to design the ESD transistor. The ESD transistor provides protection against electrical surges to vital circuitries within the IC. The ESD transistor adheres to the limitations for each process technology node and is designed to provide effective protection against electrical surges. The ESD transistor functions as a ballast resistor towards ESD surges, as will be illustrated in one embodiment. In addition, the ESD transistor provides for area savings on a substrate. The embodiments also describe a method to designing the ESD transistor and obtaining the desired ballast resistance.

FIG. 1, meant to be illustrative and not limiting, illustrates an IC layout separated by functionalities. The IC40includes a core fabric10, an ESD protective area20and Input Output (IO) area30. The core fabric10includes circuitries that define the ICs functionalities. The core fabric10can be represented by different circuitries e.g., Logic Elements (LE) for a Field Programmable Gate Array (FPGA), memory elements for Dynamic Random Access Memory (DRAM), etc., depending upon the functionalities of the IC40. The IO area30provides a gateway to external interfaces. The IO area30functionalities include (i) transferring signals from the external interfaces to the core fabric10or (ii) transferring signals from the core fabric10to the external interfaces. In one embodiment, the IO area30is located at the peripherals of the IC40. The ESD protective area20is located in between the core fabric10and IO area30, on the same plane. The ESD protective area20provides protection to the core fabric10against ESD surges, such as voltage spikes or current spikes. The ESD protective area20includes ESD transistors. The ESD transistor provides a ballast resistance to voltage or current surges. The ballast resistor is defined as a resistor that maintains a substantially constant current flow by compensating for fluctuations, such as ESD surges, through increasing the resistance when the current increases. In the event of the ESD surge, a voltage spike increases the potential difference across the external interface and the IC40that incurs a high current flowing through the IO area30. The ballast resistor property of the ESD transistor within the ESD protective area20then varies the ballast resistance accordingly towards the incoming current and limits the current to a level that can be tolerated by the core fabric10. The ESD transistor design in the ESD protective area20varies based on design rules, process limitations and types of expected ESD surges.

FIG. 2A, meant to be illustrative and not limiting, illustrates a layout of the ESD transistor in accordance with one embodiment. The ESD transistor100includes a source diffused area120, a drain diffused area140, a first gate130, dummy gates110and150, a plurality of couplings170and a plurality of routing structures160. Each of the couplings170includes a metal strip185, a first connector175and a second connector180. Each of the routing structures160includes a metal strip165and a connector155. The source diffused area120, the drain diffused area140and the first gate130is grouped as a transistor within the ESD transistor100. The first gate130is in between the source diffused area120and the drain diffused area140. The dummy gates110and150are located in a non-diffused area and adjacent to diffused area. In another embodiment, the dummy gates110and150are known as ballast resistors. The ballast resistor provides a ballast resistance which, provides ESD protection functionality to the ESD transistor100. The dummy gates110and150are also located within close proximity to the diffused areas. In one embodiment, the first gate130and the dummy gates110and150are composed from polysilicon or metallic materials. One skilled in the art appreciates that the polysilicon material can be doped with either N-type materials or P-type materials for altering the conductivity properties. The properties of polysilicon in dummy gates110and150can be altered to attain an optimized ballast resistance for the ESD transistor100. The first gate130is disposed above a substrate and extends in a direction along the surface of the substrate. The dummy gates110and150are placed substantially parallel to the first gate130. One skilled in the art appreciates that parallelism between the dummy gate110and150to the first gate130depends on the process capabilities. Therefore, the parallelism is subjected to process variation and tolerances of a given process node.

Still referring toFIG. 2A, the coupling170provides a signal connection from the diffused area140to the dummy gate150. Within the coupling170, the metal strip185is connected to the drain diffused area140or source diffused area120through the first connector175. Also within the coupling170, the metal strip185is connected to the dummy gate150or the dummy gate110through the second connector180. The metal strip185is placed in a metal layer above the substrate. A person skilled in the art appreciates that a metal layer in semiconductor devices is composed of aluminum or copper signal routing structures. In addition, the connector, e.g. connectors155,175and185, interconnect one layer to another layer and are typically a conductive through hole via. In one embodiment, the first connector175provides an interconnection from a bottom surface of the metal strip185located in a metal layer above the substrate to an upper surface of the drain diffused area140. The second connector185provides an interconnection from the bottom surface of the metal strip185to an upper surface of the dummy gate150. The first connector175and the second connector185are oriented perpendicular to the plane of first gate130. The routing structure160includes metal strip165and a connector155. The routing structure160provides a signal path from the dummy gate150to remaining circuitries of the IC. The metal strip165is located in a metal layer above the substrate. The connector155interconnects a bottom surface of the metal strip165to an upper surface of the dummy gate140. The ESD transistor100includes a plurality of the couplings170and a plurality of the metal routings160disposed sequentially along the dummy gate110or150. In one embodiment, the distance between each sequential coupling and metal routing determines the ballast resistance of the ESD structure100. It should be appreciated that the distance between sequential coupling170and metal routing160among the plurality of couplings170and metal routings160is either (i) fixed or (ii) varied along the dummy gate. The connecting area depends on the process capabilities, e.g., through hole via diameter size.

FIG. 2B, meant to be illustrative and not limiting, illustrates a 3 Dimensional illustration of the ESD transistor. The ESD transistor includes elements described inFIG. 2Aon top of a substrate200. The substrate200is composed of semiconductor material, e.g., silicon or germanium arsenide. During an ESD surge, an ESD current proceeds through the ESD transistor. The ESD current goes from the source diffused area120to the drain diffused area140through the first gate130. The first gate130is in an “on” state during the propagation of input or output signals. The ESD current flows from the drain diffused area140to the dummy gate150, through the first connector175, then the metal strip185and finally through the second connector180. The ESD current then flows along the dummy gate150from second connector180to the connector155. The dummy gate150provides the ballast resistance to the ESD current. The dummy gate150increases the resistance when the ESD current, typically a high current, is flowing through. Under normal conditions, the dummy gate150remains within the desired operating range thereby providing a moderate resistance. The ESD current then flows to the remainder of the IC from the metal strip165through the connector155. As mentioned above, the functionality of the ESD transistor depends on the ballast resistance. The ballast resistance is imposed to the ESD current when the ESD current flows in the dummy gate150. Thus, the distance between the second connector180and the connector155determines the ballast resistance for the ESD transistor. In one embodiment, there are multiple paths connecting the ESD current from the second connector180to the connector155across the ESD transistor. Advantages of the multiple paths are (i) increasing the overall resistance to the ESD current flowing within ESD transistor (ii) providing a larger area for the ESD current to flow and (iii) providing a parallel ballast resistance to the ESD current.

FIG. 3, meant to be illustrative and not limiting, illustrates a relationship of ballast resistance to pitch distance. The pitch distance is referred to the distance between the coupling170to the routing structure160as illustrated inFIG. 2A. TheFIG. 210illustrates a linear relationship between the ballast resistances to the pitch distance. The linear relationship illustrates the property wherein the resistance increases linearly as the area that the current passes through increases linearly. In this case, as the pitch distance increases, the area that the current passes through increases and therefore the resistance increases.

FIG. 4, meant to be illustrative and not limiting, illustrates a relationship of ballast resistance with the ion implantation. The ion implantation herein refers to implantation of N-type or P-type dopant into the second gate150as illustrated inFIG. 2Athat is composed of the polysilicon material. TheFIG. 310illustrates an inverse relationship of ballast resistance towards the duration under ion implantation process. The inverse relationship is due to the increase of resistance linearly as the decrease of conductivity. If the duration under ion implantation process is relatively low, the amount of dopants implanted is in a smaller amount. Hence, electrical carriers generated due to the dopants within the gate is lesser, thus the gate imposes a higher resistance to an oncoming current. If the duration of ion implantation process is high, the amount of dopants implanted is higher. The gate has a higher amount of carriers and hence the gate imposes a lower resistance to the oncoming current. As the duration of the ion implantation process time increases, the ballast resistance reaches a saturation point as illustrated by an asymptote line of the relationship representing ballasts resistance with ion implantations.

FIG. 5, meant to be illustrative and not limiting, illustrates a flowchart of a method to design an IC in accordance with one embodiment. The method to design the IC400includes placements of two diffusion areas within the IC substrate as in operation420. In one embodiment, one of the diffusion areas is a source diffused area120and the other is a drain diffused area140as illustrated inFIG. 2B. On a p-type substrate, the diffusion areas are designed to be of n-type dopant region and on an n-type substrate the diffusion areas are designed to be of p-type dopant region. The two areas are placed a channel length distance apart. The channel length is a distance between the source and the drain on a Complementary Metal Oxide Semiconductor (CMOS) transistor, typically depending on the process node the CMOS transistor is built upon. A first gate is placed in between the two diffusion area as in operation430, but on a layer above the substrate. In one embodiment, the first gate extends substantially parallel along the two areas and is in a plane parallel to the two areas. In one embodiment, the first gate is illustrated by the first gate130inFIG. 2B. A person skilled in the art appreciates there is an oxide layer that is inserted directly below the first gate and directly above the substrate. A second gate is designed on a non-diffused substrate area that is adjacent to the diffused area as in operation440. The second gate is designed within a close proximity to the diffusion area therefore providing a connection to the diffused area. The second gate is placed substantially parallel to the first gate. One skilled in the art appreciates that the close proximity of the second gate and being substantially parallel to the first gate depends on multiple factors, such as the process capability and tolerances. In one embodiment, the second gate is illustrated by the second gate150inFIG. 2B.

Still referring to theFIG. 5, the diffused area is then connected to the second gate as in operation450. The diffused area is connected to the second gate through a first interconnection. In one embodiment, the first interconnection is a coupling as illustrated inFIG. 2Athat is a combination of the first connector, the metal strip and the second connector as illustrated inFIG. 2B. The method to design the first interconnection includes placing a metal strip on one of the layers above the substrate. Then, the first connector connects the metal strip's bottom surface that is just above the diffusion area to a top surface of the diffusion area. The second connector then connects the metal strip's bottom surface that is just above the second gate to a top surface of the second gate. The first and second connectors are through-hole vias in one embodiment. The metal strip is in a plane parallel to the surface of the substrate. The first and second connectors are in a plane perpendicular to the surface of the substrate. The first interconnection occupies only a portion of an overall area provided by the diffusion area and the second gate. In one embodiment, the first interconnections are placed in an equidistance manner along the second gate.

Still referring toFIG. 5, the second gate is connected to other circuitry and logic in IC as in operation460. The second gate is connected to a remaining portion of the circuit through a second interconnection. In one embodiment, the second interconnection is the routing structure as illustrated inFIG. 2Athat is a combination of the connector and the metal strip as illustrated inFIG. 2B. The second gate is connected to the remainder of the circuit through a metal strip placed on one of the layers above the substrate. A connector connects a part of the metal strips bottom surface that is just above the second gate area to the second gate. The portion of the metal strip that is not above the second gate is connected to the remainder of the circuit. The connector is a through hole via in one embodiment. It should be appreciated that the metal strip is also placed in a plane parallel to the surface of the substrate, while the connector is located in a plane perpendicular to the surface of the substrate. The second interconnection occupies only a portion of an area of the second gate. In one embodiment, the second interconnections are placed in an equidistance manner along the second gate. In another embodiment, the first interconnection and the second interconnection are placed sequentially one after another along the second gate as illustrated inFIG. 2A.

Still referring toFIG. 5, a ballast resistance on the ESD structure is calculated as in operation470. If the ballast resistance is within an expected range, the method to design completes as in operation490. If the ballast resistance is not within the expected range, the distance between the first and second interconnection is adjusted as in operation480. The ballast resistance is adjusted using the relationship as illustrated through graph210inFIG. 3, wherein increasing the pitch distance between the first and second interconnection increases the ballast resistance and vice versa. The cycle of calculating and checking the ballast resistance470and adjusting the distance between first and second interconnection480is continued until a satisfactory ballast resistance is achieved.

The embodiments, thus far, were described with respect to integrated circuits. The method and apparatus described herein may be incorporated into any suitable circuit. For example, the method and apparatus may be incorporated into numerous types of devices such as microprocessor or programmable logic devices. Exemplary of programmable logic devices include programmable arrays logic (PALs), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FPGAs), application specific standard products (ASSPs), application specific integrated circuits (ASICs), just name a few.

Although the method of operations were described in a specific order, it should be understood that other operation may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows occurrence of the processing operation at various intervals associated with the processing, as long as the processing of the overlay operations are performed in a desired way.