System and method for detecting processing speed of integrated circuit

A system for detecting the processing speed of an integrated circuit (IC) includes a flip-flop, a delay module, and a judge unit. The flip-flop receives a clock signal as a trigger signal and generates an inverted output signal. The delay module receives the inverted output signal, adjusts the delay time of the inverted output signal according to a selection signal, and outputs a delay signal to the flip-flop to have the flip-flop generate the output signal. The judge unit receives the output signal and generates a judge signal, which is enabled when the clock period of the output signal is longer than that of the clock signal.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The invention relates to a detection system and method and, more particularly, to a detection system and method capable of detecting the processing speed of an integral circuit (IC).

(b) Description of the Related Art

Typically, each IC product may tend to have a different processing speed due to different factors, e.g. the situation of the environment, the stability of temperature, etc, during the manufacturing processes. However, since all IC products in the same batch must have the same processing speed that conform to a specific specification, they must be ranked according to their respective processing speeds, and then speed compensation is made thereon to allow all IC products in the same batch to have identical processing speeds.

FIG. 1shows a conventional detection system for detecting the processing speed of an IC. The detection system10includes a ring oscillator11built inside the IC, and an external test unit12built outside the IC. The external test unit12includes a frequency elimination device121and a test platform122. Alternatively, the frequency elimination device121of the external test unit12may be built inside the IC. In a typical detection of the processing speed of the IC, the ring oscillator11outputs an oscillation frequency signal Hf, which is in positive correlation to the processing speed, to the external test unit12to allow the test unit12to detect the processing speed of the IC. Then, all ICs in the same batch are ranked according to their respective processing speeds, and, subsequently, the speed compensation is made thereon.

However, though the ring oscillator11and the external test unit12together may accurately detect the processing speed of an IC, the frequency of the oscillation frequency signal Hf, about 1 GHz to 2 GHz, is considerably high. Since a typical test platform may increase its detecting frequency range up to only several hundreds of MHz, the frequency elimination device121that consists of multiple frequency eliminators1211is additionally required to lower the frequency of the oscillation frequency signal Hf to an accepted detection range for the test platform122.

Further, since the test platform becomes more expensive as a broader detecting frequency range is provided, the cost of the test platform is reduced when the frequency of the oscillation frequency signal Hf is lowered. Thus, the number of the frequency eliminators1211must be increased to the extent that up to more than three, such as five or ten frequency eliminators1211. However, it is clearly seen that the overall cost and power consumption of the test unit12are elevated as the number of the frequency eliminators1211is increased. Besides, in case the numerous frequency eliminators1211are built inside an IC, the occupied space of an IC will inevitably expand.

On the other hand, the ring oscillator11and the external test unit12that operate at a high frequency may also result in high power consumption.

BRIEF SUMMARY OF THE INVENTION

Hence, an object of the invention is to provide a detection system and method capable of accurately detecting the processing speed of an integral circuit (IC) in an efficient way where the design complexity, production cost, and power consumption are all reduced.

According to the invention, the detection system includes a flip-flop, a delay module, and a judge unit. The flip-flop receives a reset signal that sets an output signal of the flip-flop to a preset voltage level (logic 1 or 0(a high level 1 or a low level 0)) and receives a clock signal as a trigger signal, and an inverted output signal is generated via its inverted output port. The delay module receives the inverted output signal, adjusts the delay time of the inverted output signal according to a selection signal, and outputs a delay signal whose delay time is variable to the flip-flop. Then the flip-flop generates the output signal according to the delay signal. Finally, the judge unit receives the output signal and generates a judge signal. When the clock period of the output signal is longer than the clock period of the clock signal, the judge signal is enabled by the judge unit. This indicates that the present delay time is exactly the delay time in positive correlation to the processing speed of the IC, and therefore the desired processing speed of the IC can be obtained according to the present delay time.

Further, the subject invention also provides a detection method for detecting the processing speed of an IC. First, a clock signal is provided and an inverted output signal is generated according to the clock signal. Then, the time of the inverted output signal is adjusted or delayed to generate an output signal according to a selection signal. Finally, a judge signal is provided where it is enabled when the clock period of the output signal is longer than the clock period of the clock signal.

Through the design of the invention, since the detection system of the invention requires only one flip-flop, and a clock signal rather than a high-frequency signal is used for the speed detection, the design complexity, production cost, and power consumption are all reduced.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2shows a schematic diagram illustrating a detection system20of the invention for detecting the processing speed of an IC. The detection system20includes a clock output device21and a judge unit22. The clock output device21of this embodiment is built inside the IC and used for outputting a signal in positive correlation to the processing speed. The judge unit22checks the clock status of the signal to detect the processing speed of the IC. Note that the judge unit22of the invention can be easily built inside the IC for its simplified and compact design.

The clock output device21of this embodiment includes a flip-flop211and a delay module212. The flip-flop211includes an input port D, a timing port CK, an output port Q, an inverted output port QN, and a reset port RS. In this embodiment, the timing port CK is a falling-edge trigger port. Alternatively, the timing port CK may be a rising-edge trigger port. The reset port RS receives a reset signal R1to set the output signal O of the flip-flop211to a preset level (logic 1 or 0(a high level 1 or a low level 0)). The flip-flop211receives a clock signal C as a trigger signal via the timing port CK and outputs an inverted output signal ON via the inverted output port QN.

The delay module212receives the inverted output signal ON, adjusts the delay time of the inverted output signal ON according to a first selection signal S1, and then outputs a delay signal Od to the input port D of the flip-flop211. Wherein the delay time of the inverted output signal ON is variable. So that the flip-flop211is allowed to output an output signal O. Referring toFIG. 3, the delay module212includes a delay unit212a, m clock-adjusting units (d1, d2, d3. . . dm, where m is a positive integer), and a first multiplexer212b. The delay unit212acoarsely adjusts the delay time, while the m clock-adjusting units d1-dm could finely adjust the delay time. The delay unit212areceives the inverted output signal ON of the flip-flop211and delays the inverted output signal ON to generate a delay clock signal Dt. The first clock-adjusting unit d1receives and then delays the delay clock signal Dt to generate a first clock-adjusting signal T1, where the total delay time of the first clock-adjusting signal T1equals Dt+1dt (Dt is far longer than dt). The clock-adjusting unit may be constructed by a delay cell, multiple serially coupled NOT gates, or other device capable of delaying signals. The mthclock-adjusting unit dm receives and then delays the (m−1)thclock-adjusting signal T(m−1) to generate the mthclock-adjusting signal Tm. For example, the second clock-adjusting unit d2receives and then delays the first clock-adjusting signal T1of the first clock-adjusting unit to generate a second clock-adjusting signal T2(=Dt+2dt), and so on. In this embodiment, the delay time of each of the clock-adjusting units d1−dm equals 1dt. However, the length of delay time is not limited and is selected according to designer's actual demand. Specifically, under the condition that a fixed sum of an overall delay time caused by all clock-adjusting units is given, if the number of the clock-adjusting units increases, the delay time dt for each clock-adjusting unit is reduced, and the detection accuracy of the detection system is increased as a result. The first multiplexer212breceives the delay clock signal Dt and m clock-adjusting signals T1−Tm and selects either the delay clock signal Dt or one of the clock-adjusting signals T1−Tm according to a first selection signal S1to generate the aforesaid delay signal Od.

The judge unit22receives the output signal O of the flip-flop211and generates a judge signal Or. When the clock period of the output signal O is longer than that of the clock signal C, the judge unit22enables the judge signal Or to allow it to have a high level 1(otherwise, the judge unit22disables the judge signal Or to allow it to have a low level 0), which indicates the present delay time adjusted by the delay module212is exactly the delay time in positive correlation to the processing speed of the IC, and therefore the desired processing speed of the IC can be obtained according to the delay time. Specifically, under the circumstance that each IC has a different processing speed, the test criterion of the invention is established on an identical output result for each IC where the clock period of the output signal O is lager than that of the clock signal C. Hence, an IC with a faster processing speed requires a shorter time to obtain the same result, and thus a longer delay time is needed. On the contrary, an IC with a slower processing speed requires a longer time to obtain the same result, and thus a shorter delay time is needed. Therefore, a positive correlation between the required delay time and the procession speed is established and exactly reflects the actual procession speed of an IC.

Note that the judge unit22includes, but is not limited to, logic gates or a flip-flop, and any logic unit capable of comparing the clock period of the output signal O with that of the clock signal C can also be used. For example, as shown inFIG. 4A, the judge unit22may include a flip-flop221a, a flip-flop221bwith a built-in multiplexing function, and an exclusive NOR gate222. The flip-flop221bis different to the flip-flop221ain that the former further includes an output signal control end TI and a selection signal end TE. When the selection signal end TE receives the high level 1, the judge signal Or outputted via the output port Q may have a level identical with that of the output signal control end TI, which is in connection with VDD having the high level 1. On the contrary, when the selection signal end TE receives the low level 0, the judge signal Or outputted via the output port Q may have a level identical with that of the input port D. Referring toFIG. 4A, when the clock period of the output signal O is equal to or shorter than that of the clock signal C, two input ends A and B of the exclusive NOR gate222alternatively receive the output signal O and an output signal of the flip-flop221ahaving a sequence of alternate high and low levels, so that the exclusive NOR gate222may output a signal having the low level 0 to the flip-flop221b. In that case, the flip-flop21bmay output the judge signal Or having the low level 0 without being influenced by the output signal control end TI. On the contrary, when the clock period of the output signal O is larger than that of the clock signal C, the output signal O and an output signal of the flip-flop221areceived by the two input ends A and B of the exclusive NOR gate222may have the same high or low level, so that the exclusive NOR gate222may output a signal having the high level 1 to the flip-flop221b. In that case, the flip-flop21bmay output the judge signal Or having the high level 1 with being influenced by the output signal control end TI. Certainly, the flip-flop221bwith a built-in multiplexing function may be replaced by a common flip-flop221, for the multiplexing function is incorporated to merely achieve a more accurate result. Hence, compared to a conventional external test unit12that requires at least three flip-flops as frequency eliminators1211, the judge unit22of the invention requires only two flip-flops. Besides, the clock output device21outputs a clock signal rather than a high-frequency signal to the judge unit22for the speed detection, and thus design complexity and production cost for a test platform and power consumption during operation are all reduced.

FIG. 4Billustrates another embodiment of the judge unit according to the invention, where a judge unit22′ includes six flip-flops, four exclusive NOR gates, and a AND gate. Though the number of the flip-flops is larger than that shown inFIG. 4A, it still can reduce the design complexity and production cost for a test platform122since a clock signal rather than a high-frequency signal is employed.

FIGS. 5A–5Dshow timing diagrams illustrating how the detection system of the invention detects the processing speed of an IC. First, at time t0, a reset signal R1is fed to a flip-flop211from a device external to the IC, so that the output signal O of the flip-flop211is set to a high level 1. Meanwhile, a clock signal C used as a trigger clock (falling-edge trigger here) is fed to the flip-flop211from an oscillator inside the IC or a device external to the IC, and an inverted output signal ON is outputted by the flip-flop211at the same time. Then, a delay unit212areceives the inverted output signal ON and performs a coarse adjustment of delay time thereon, where the inverted output signal ON is delayed with a period longer than the delay time of a clock-adjusting unit dm to generate a delay clock signal Dt, which is fed to a multiplexer212b. A clock-adjusting unit d1receives the delay clock signal Dt and performs a fine adjustment of delay time thereon to generate a clock-adjusting signal T1(=Dt+1dt), which is fed to the multiplexer212b. As shown inFIG. 5A, the multiplexer212breceives a first selection signal S1to choose the clock-adjusting signal T1and generates a delay signal Od (Dt+1dt), which is fed to the flip-flop211via its input port D. Then, the flip-flop211outputs an output signal O (Dt+1dt) to a judge unit22. Referring toFIG. 5A, since the delay time Dt+1dt of the delay signal Od (Dt+1dt) is shorter than the clock period Ct of the clock signal C, the output signal O (Dt+1dt) alters its level as triggered by the clock signal C at a falling edge of the clock signal C (indicated by an arrow a). Also, since the clock period of the output signal O (Dt+1dt) is shorter than that of the clock signal C, the judge unit22will disable a judge signal Or. Next, as shown inFIG. 5B, even the delay time of the delay signal Od is increased by 1 dt to become Dt+2dt, it is still shorter than the clock period Ct of the clock signal C. Thus, the output signal O (Dt+2dt) still alters its level as triggered by the clock signal C at the falling edge of the clock signal C (indicated by an arrow a). Also, since the clock period of the output signal O (Dt+2dt) is shorter than that of the clock signal C, the judge unit22will disable the judge signal Or. Then, as shown inFIG. 5C, the delay time of the delay signal Od is further increased by 1dt to become Dt+3dt, which is longer than the clock period Ct of the clock signal C, and thus the output signal O (Dt+3dt) is not triggered at a falling edge of the clock signal C (indicated by an arrow b) but triggered at a next falling edge of the clock signal C (indicated by an arrow c) to alter its level from 0 to 1. Also, since the clock period of the output signal O (Dt+3dt) is twice longer than that of the clock signal C, the judge unit22will enable the judge signal Or so that the required delay time Dt+3dt for the IC is detected and serves to achieve the same output result of the output signal O of the flip-flop211. In that case, the required delay time that equals Dt+3dt is in positive correlation to the procession speed to reflect the actual procession speed of the IC.

Further,FIG. 5Dshows a timing diagram illustrating an embodiment of detecting the processing speed of another IC. Referring toFIG. 5D, the delay time Dt+4dt of the delay signal Od (Dt+4dt) is longer than the clock period Ct of the clock signal C, and thus the output signal O (Dt+4dt) is not triggered at a falling edge of the clock signal C (indicated by an arrow b) but triggered at a next falling edge of the clock signal C (indicated by an arrow c) to alter its level from 0 to 1. Also, as shown inFIG. 5D, the clock period of the output signal O (Dt+4dt) is twice longer than that of the clock signal C. Hence, it can be seen that the IC requires a longer delay time of Dt+4dt to meet the requirement where the clock period of the output signal O (Dt+4dt) is longer than that of the clock signal C.

Comparing the two ICs above, it is seen that the delay time Dt+3dt of the first IC is shorter than the delay time Dt+4dt of the second IC, which means the first IC has a slower processing speed to consume a longer operation time and thus requires a shorter delay time compared to the second IC. Hence, the detection system20of the invention may detect the processing speed of an IC according to its delay time, and all the ICs in the same batch can be ranked according to their respective processing speeds by the test results.

Note that it is not necessary for the delay module212to choose the same increment of the delay time but to choose it in the most efficient way during the speed detection. For example, the delay time may first extend to Dt+2dt, next extend to Dt+8dt, and then shrink to Dt+6Dt if an excess delay time is detected.

FIG. 6shows another embodiment of the delay module according to the invention. Referring toFIG. 6, the delay module212′ includes a delay unit212a′, m clock-adjusting units (d1′, d2′, d3′ . . . dm′, where m is a positive integer), and a first multiplexer212b′. The delay unit212a′ receives and then delays an inverted output signal ON to generate a delay clock signal Dt′. The clock-adjusting units d1′−dm′ receive and then delay the delay clock signal Dt′to generate clock-adjusting signals T1′−Tm′. Note that each of the clock-adjusting units has a different delay time. For example, the delay time of the clock-adjusting unit d2′ equals 2dt, the delay time of the clock-adjusting unit d3′ equals 3dt, and so on. The first multiplexer212b′ receives the delay clock signal Dt′ and clock-adjusting signals T1′−Tm′ and selects either the delay clock signal Dt′ or one of the clock-adjusting signals T1′−Tm′ to generate a delay signal Od. Further, in order to obtain a more fine adjustment of the delay time caused by the delay module212, the delay unit212ashown inFIG. 3may be replaced by the delay unit212a″ shown inFIG. 7Aor delay unit212a′″ shown inFIG. 7B, where a second selection signal S2is used in the selection of the delay time. The delay unit212a″ includes m clock-adjusting units (d1″, d2″, d3″ . . . dm″, where m is a positive integer) and a second multiplexer212b″. The delay unit212a′″ includes m clock-adjusting units (d1′″, d2′″, d3′″ . . . dm′″, where m is a positive integer) and a second multiplexer212b′″.

FIG. 8shows a flowchart illustrating a detection method for detecting the processing speed of an IC. The method includes the steps described below.

Step S804: Provide a reset signal to set an output signal to a preset level (ether a high level 1 or a low level 0).

Step S806: Provide a clock signal and generate an inverted output signal according to the clock signal. The clock signal may be a rising-edge trigger signal or a falling-edge trigger signal.

Step S808: Adjust the delay time of the inverted output signal according to a selection signal to generate a delay signal whose delay time is variable.

Step S810: Generate an output signal according to the delay signal.

Step S812: Determine whether the clock period of the output signal is longer than that of the clock signal. If no, go back to step S806; if yes, go to the next step.

Step S814: Enable a judge signal.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. For example, as shown inFIG. 9, the delay clock signal Dt and the clock-adjusting signals T1–T9are fed to a multiplexer212b, and the clock-adjusting signals T0–Tm are fed to another multiplexer212b″″. That is, the delay clock signal Dt together with the clock-adjusting signals may divided into several groups, and a plurality of multiplexers are provided to receive their respective groups of signals.

Also, as shown inFIG. 10, m clock-adjusting units may direct receive the inverted output signal ON to omit the delay unit212ashown inFIG. 3. Certainly, as shown inFIG. 11, m clock-adjusting units may direct receive the inverted output signal ON to omit the delay unit212a′ shown inFIG. 6. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.