Method for fabricating nonvolatile memory device

A method for fabricating a nonvolatile memory device is provided. The method includes forming a transistor including an impurity region formed in a substrate, forming a first interlayer insulation layer covering the transistor, the first interlayer insulation layer including a protrusion overlapping the impurity region, and forming an information storage unit on the protrusion, the information storage unit exposing side surfaces of the protrusion using point cusp magnetron-physical vapor deposition (PCM-PVD) and electrically connected to the impurity region.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2013-0024115 filed on Mar. 6, 2013 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which in its entirety are herein incorporated by reference.

FIELD

The present invention relates to a method of fabricating a nonvolatile memory device.

BACKGROUND

Nonvolatile memories using resistance materials include phase-change random access memories (PRAMs), resistive RAMs (RRAMs), and magnetic RAMs (MRAMs). While dynamic RAMs (DRAMs) or flash memories store data using charge, nonvolatile memories using resistance materials store data using a state change of a phase-change material, such as chalcogenide alloy (in the case of PRAMs), a resistance change of a variable resistance material (in the case of RRAMs), or a resistance change of a magnetic tunnel junction (MTJ) thin film according to a magnetization state of a ferromagnetic material (in the case of MRAMs).

Semiconductor products may need to process high capacity data while they are gradually becoming more compact. Accordingly, there is demand for increasing the operating speed and integration level of memory devices used in such semiconductor products. To meet such demand, there have been proposed magnetic memory devices implementing memory functions using a resistance change depending on a change in the polarity of a magnetic material, and various studies of the magnetic memory devices are being conducted.

SUMMARY

The present invention provides a method of fabricating a nonvolatile memory device, which forms a magnetic tunnel junction (MTJ) on a top surface of a lower electrode terminal patterned in a three-dimensional pillar shape using point cusp magnetron-physical vapor deposition (PCM-PVD).

The above and other objects of the present invention will be described in or be apparent from the following description of the embodiments.

According to an aspect of the present invention, there is provided a method of fabricating a nonvolatile memory device, the method including forming a transistor including an impurity region formed in a substrate, forming a first interlayer insulation layer covering the transistor, the first interlayer insulation layer including a protrusion overlapping the impurity region, and forming an information storage unit on the protrusion, the information storage unit exposing side surfaces of the protrusion using point cusp magnetron-physical vapor deposition (PCM-PVD) and electrically connected to the impurity region.

According to another aspect of the present invention, there is provided a method of fabricating a nonvolatile memory device, the method including forming a transistor including an impurity region formed in a substrate, forming a lower contact electrically connected to the impurity region, forming a first interlayer insulation layer on the lower contact, forming a first trench and a second trench in the first interlayer insulation layer, the first trench extending in a first direction and the second trench extending in a second direction different from the first direction, and forming an information storage unit electrically connected to the lower contact on a top surface of the first interlayer insulation layer using point cusp magnetron-physical vapor deposition (PCM-PVD) and forming a dummy information storage unit on bottom surfaces of the first and second trenches.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1is an equivalent circuit view for explaining a nonvolatile memory device fabricated according to embodiments of the present inventive subject matter, andFIG. 2is a layout view illustrating the nonvolatile memory device shown inFIG. 1.

Referring toFIG. 1, a magnetic memory array includes unit cells U of a plurality of magnetic memory devices arrayed in a matrix configuration. Each of the unit cells U of the plurality of magnetic memory devices includes an access part C and a memory cell MC. The unit cells U of the plurality of magnetic memory devices are electrically connected to word lines WL and bit lines BL. In addition, as shown inFIG. 1, when the access part C is a transistor, a source line SL may further be formed to be electrically connected to a source region of the access part C. WhileFIG. 1shows that one access part C is connected to one source line SL, a plurality of access parts C may be connected to one source line SL. The word lines WL and bit lines BL may be arranged in a two-dimensional manner at a predetermined angle, for example, at a right angle. Alternatively, the word lines WL and bit lines BL may be arranged at a predetermined angle with respect to each other, for example, to be parallel with each other.

The access part C controls current supply to the memory cell MC according to the voltage of the word line WL. The access part C may be a MOS transistor, a bipolar transistor or a diode.

The memory cell MC may include a magnetic material or a magnetic tunnel junction (MTJ). In addition, the memory cell MC may perform a memory function using a spin transfer torque (STT) phenomenon in which a magnetization direction of the magnetic material varies according to the current input thereto.

Referring toFIG. 2, the transistor100is formed to extend lengthwise in a second direction DR2. A gate electrode included in the transistor100may function as, for example, the word line shown inFIG. 1. A first wiring110may be formed between neighboring transistors100extending lengthwise in the second direction DR2. The first wiring110is electrically connected to a common source/drain disposed between neighboring transistors100by a first contact115. The first wiring110may be, for example, the source line SL shown inFIG. 1.

In the neighboring transistors, an information storage unit130is formed on a source/drain that is not electrically connected to the first wiring110. The information storage unit130is electrically connected to the source/drain that is not electrically connected to the first wiring110by means of the second contact120.

The second wiring140is formed to extend lengthwise in a first direction DR1. The second wiring140is formed to cross the transistor100and the first wiring110. The second wiring140may be, for example, the bit line shown inFIG. 1. The second wiring140is electrically connected to a plurality of information storage units130arranged in the first direction DR1.

In the following description, the method for fabricating a nonvolatile memory device will be described in view of cross sections taken along the lines A-A and B-B.

An information storage unit in a method for fabricating a nonvolatile memory device according to embodiments of the present inventive subject matter will be described with reference toFIGS. 3A and 3B.

FIG. 3Ais a cross-sectional view illustrating an example of an information storage unit in a method for fabricating a nonvolatile memory device according to embodiments of the present inventive subject matter, andFIG. 3Bis a cross-sectional view illustrating another example of an information storage unit in a method for fabricating a nonvolatile memory device according to embodiments of the present inventive subject matter.

Referring toFIG. 3A, the information storage unit130according to the embodiment of the present inventive subject matter may include a reference pattern130c, a free pattern130e, and a tunnel barrier pattern130ddisposed between the reference pattern130cand the free pattern130e. The reference pattern130chas a magnetization direction (i) pinned in one direction, and the free pattern130ehas a magnetization direction (ii) variable to be parallel to or anti-parallel to the magnetization direction (i) of the reference pattern130c. The magnetization directions i and ii of the reference pattern130cand the free pattern130emay be parallel to one surface of the tunnel barrier pattern130dmaking contact with the free pattern130e. The reference pattern130c, the tunnel barrier pattern130dand the free pattern130emay constitute a magnetic tunnel junction (MTJ).

If the magnetization direction (ii) of the free pattern130eis parallel to the magnetization direction (i) of the reference pattern130c, the information storage unit130may have a first resistance value. If the magnetization direction (ii) of the free pattern130eis anti-parallel to the magnetization direction (i) of the reference pattern130c, the information storage unit130may have a second resistance value. Here, the first resistance value may be less than the second resistance value. The information storage unit130may store logic data using a difference between the first and second resistance values. The magnetization direction (ii) of the free pattern130emay be changed by spin torque of electrons in program current.

The reference pattern130cand the free pattern130emay include a ferromagnetic material. The reference pattern130cmay further include an anti-ferromagnetic material pinning a magnetization direction of the ferromagnetic material in the reference pattern130c. The tunnel barrier pattern130dmay include, for example, at least one of magnesium oxide, titanium oxide, aluminum oxide, magnesium-zinc oxide and magnesium-boron oxide.

The information storage unit130may further include a lower electrode130aand an upper electrode130b. The reference pattern130c, the tunnel barrier pattern130dand the free pattern130emay be disposed between the lower electrode130aand the upper electrode130b. As shown inFIG. 3A, the reference pattern130c, the tunnel barrier pattern130dand the free pattern130emay be, sequentially disposed on the lower electrode130a, and the upper electrode130bmay be disposed on the free pattern130e. Alternatively, the free pattern130e, the tunnel barrier pattern130d, and the reference pattern130cmay be sequentially disposed on the lower electrode130a. The lower electrode130aand the upper electrode130bmay include, for example, a conductive metal nitride, such as titanium nitride, tantalum nitride, or tungsten nitride.

Referring toFIG. 3B, the information storage unit130according to an embodiment of the present inventive subject matter may include a reference vertical pattern130h, a free vertical pattern130, and a tunnel barrier pattern130iinterposed between the reference vertical pattern130hand the free vertical pattern130. The reference vertical pattern130hmay have a magnetization direction (iii) pinned in one direction, and the free vertical pattern130may have a magnetization direction (iv) variable to be parallel to or anti-parallel to the magnetization direction (iii) of the reference vertical pattern130h. Here, the magnetization directions (iii) and (iv) of the reference and free vertical patterns130hand130jmay be substantially perpendicular to one surface of the tunnel barrier pattern130imaking contact with the free vertical pattern130.

The reference vertical pattern130hand the free vertical pattern130may include, for example, at least one of a vertical magnetic material such as CoFeTb, CoFeGd, or CoFeDy, a vertical magnetic material having an L10structure, CoPt having a hexagonal close packed lattice, and a vertical magnetic structure. The vertical magnetic material having an L10structure may include, for example, at least one of L10ordered FePt, L10ordered FePd, L10ordered CoPd, and L10ordered CoPt. The vertical magnetic structure may include magnetic layers and non-magnetic layers alternately and repeatedly stacked. For example, the vertical magnetic structure may include, for example, at least one of (Co/Pt)n, (CoFe/Pt)n, (CoFe/Pd)n, (Co/Pd)n, (Co/Ni)n, (CoNi/Pt)n, (CoCr/Pt)n and (CoCr/Pd)n, where n is the number of stacks.). Here, the reference vertical pattern130hmay be thicker than the free vertical pattern130, and a coercive force of the reference vertical pattern130hmay be greater than that of the free vertical pattern130.

The tunnel barrier pattern130imay include, for example, at least one of magnesium oxide, titanium oxide, aluminum oxide, magnesium zinc oxide, and magnesium boron oxide. The information storage unit130may include a lower electrode130fand an upper electrode130g. As shown, the reference vertical pattern130h, the tunnel barrier pattern130iand the free vertical pattern130may be sequentially stacked on the lower electrode130f, and the upper electrode130gmay be stacked on the free vertical pattern130. Alternatively, the free vertical pattern130, the tunnel barrier pattern130iand the reference vertical pattern130hmay be sequentially stacked on the lower electrode130f, and the upper electrode130gmay be stacked on the reference vertical pattern130h. The lower and upper electrodes130fand130gmay be made of, for example, conductive metal nitride.

A method for fabricating a nonvolatile memory device according to an embodiment of the present inventive subject matter will be described with reference toFIGS. 4 to 11.

FIGS. 4 to 11illustrate intermediate process steps for fabricating a nonvolatile memory device according to an embodiment of the present inventive subject matter.

Referring toFIGS. 4 and 5, a transistor100is formed on a substrate10, the transistor100including a first impurity region104and a second impurity region102formed in the substrate10. A first interlayer insulation layer20covering the transistor100is formed on the substrate10having the transistor100.

A second contact120passing through the first interlayer insulation layer20is formed in the first interlayer insulation layer20. The second contact120is electrically connected to the second impurity region102. In detail, the second lower contact122passes through the first interlayer insulation layer20and is electrically connected to the second impurity region102.

In detail, an isolation layer105is formed in the substrate10to define an active region. The isolation layer105may be, for example, a trench-type isolating pattern. The substrate10may include, for example, a semiconductor layer including silicon (Si), silicon germanium (SiGe) and/or silicon carbide (SiC), a conductive layer including titanium (Ti), titanium nitride (TiN), aluminum (Al), tantalum (Ta), tantalum nitride (TaN) and/or titanium aluminum nitride (TiAlN), and a dielectric layer including silicon oxide, titanium oxide, aluminum oxide, zirconium oxide and hafnium oxide. In addition, the substrate10may include an epitaxial layer, a silicon on insulator (SOI) layer and/or a semiconductor on insulator (SEOI) layer. In addition, the substrate10may include a conductive line or other semiconductor elements. The substrate10may be a substrate doped with a first impurity.

The transistor100may be formed on the substrate10having the active region defined thereon. The transistor100may include a first impurity region104and a second impurity region formed at opposite sides of a spacer of the transistor100. The first impurity region104and the second impurity region102may be formed in the substrate10. The first impurity region104is a region to which a first contact115shared by a neighboring transistor100is connected, and the second impurity region102is a region to which a second contact (120ofFIG. 10A) connected to each information storage unit (130ofFIG. 10A) is connected. The first and second impurity regions102and104may be formed by doping impurity of a conductivity type opposite to that of the substrate10.

The transistor100is formed to extend in a second direction DR2and may extend over a plurality of active regions separated from each other by the isolation layer105. A gate electrode of the transistor100may include, for example, a doped semiconductor and/or a metal. A gate insulation layer of the transistor100may include, for example, silicon oxide, SiON, GexOyNz, GexSiyOz, a high-k material, or a combination thereof, or may have a stacked structure having layers made of these materials sequentially stacked. The spacer of the transistor100may include, for example, at least one of an oxide layer, an oxynitride layer and a nitride layer.

In the method of fabricating a nonvolatile memory device according to an embodiment of the present inventive subject matter, the transistor100may be a planar transistor, but not limited thereto. That is to say, the transistor100may have various structures, including a buried channel array transistor (BCAT), a vertical channel array transistor (VCAT) formed on a pillar-shaped unit active region, and other structures.

After the transistor100is formed, the first lower interlayer insulation layer22covering the transistor100may be formed on the substrate10. The first lower interlayer insulation layer22may include, for example, at least one of an oxide layer, an oxynitride layer, and a nitride layer, and may be formed by chemical vapor deposition (CVD).

The first contact115formed in the first lower interlayer insulation layer22may be formed on the first impurity region104in a dot type to then be electrically connected to the first impurity region104. The first contact115may be arranged in a second direction DR2. The first contact115may include, for example, at least one of a doped semiconductor, a metal, a conductive metal nitride, and a metal-semiconductor compound.

In the method of fabricating a nonvolatile memory device according to an embodiment of the present invention, the first contact115is formed in a dot type, but is not limited thereto. That is to say, the first contact115may be typed of a line connecting the first impurity region104in the second direction DR2.

The first contact115may be formed in the first contact hole115hpassing through the first lower interlayer insulation layer22and exposing the first impurity region104. The first contact hole115hmay be formed by forming a mask pattern on the first lower interlayer insulation layer22and patterning the first lower interlayer insulation layer22using the mask pattern as an etch mask. The first contact115may be formed by filling the first contact hole115hwith a conductive material and planarizing the resultant product. As the result of the planarizing for forming the first contact115, a top surface of the first lower interlayer insulation layer22may also be planarized.

The first wiring110is formed on the first lower interlayer insulation layer22and extends lengthwise in the second direction DR2. The first wiring110is electrically connected to the first impurity region104by the first contact115formed in the first lower interlayer insulation layer22. The first wiring110may include, for example, at least one of a doped semiconductor, a metal, a conductive metal nitride, and a metal-semiconductor compound.

After forming the first wiring110, a first upper interlayer insulation layer24covering the first lower interlayer insulation layer22and the first wiring110is formed on the substrate10. The first upper interlayer insulation layer24may include, for example, at least one of an oxide layer, an oxynitride layer, and a nitride layer, and may be formed by chemical vapor deposition (CVD).

The second lower contact122may be formed in the first upper interlayer insulation layer24and the first lower interlayer insulation layer22. That is to say, the second lower contact122may be formed in the first interlayer insulation layers22and24while passing through the first interlayer insulation layer20. The second lower contact122is formed on the second impurity region102formed in the substrate10to then be electrically connected to the second impurity region102. The second lower contact122may be arranged in the second direction DR2. The second lower contact122and the first contact115may be arranged in the first direction DR1. The second lower contact122may include, for example, at least one of a doped semiconductor, a metal, a conductive metal nitride, and a metal-semiconductor compound.

The second lower contact122may be formed in the second lower contact hole122hpassing through the first interlayer insulation layer20and exposing the second impurity region102. The second lower contact hole122hmay be formed by forming a mask pattern on the first interlayer insulation layer20and patterning the first interlayer insulation layer20using the mask pattern as an etch mask. The second lower contact122may be formed by filling the second lower contact hole122hwith a conductive material and planarizing the resultant product.

In addition, a lower conductive pad may further be formed on the second lower contact122, but aspects of the present inventive subject matter are not limited thereto. The lower conductive pad may be formed for the purpose of securing a contact margin in forming a second upper contact124in a later operation.

Referring toFIGS. 4 and 6, a second interlayer insulation layer30may be formed on the first interlayer insulation layer20, and a second upper contact124may be formed in the second interlayer insulation layer30. The second upper contact124may be formed to overlap the second lower contact122.

The second upper contact124is electrically connected to the second lower contact122and is electrically connected to the second impurity region102by means of the second lower contact122. The second upper contact124and the second lower contact122may be arranged in a line and formed on the second impurity region102.

In detail, the second interlayer insulation layer30covering the second lower contact122may be formed on the first interlayer insulation layer20. The second interlayer insulation layer30may include, for example, at least one of an oxide layer, an oxynitride layer, and a nitride layer, and may be formed by chemical vapor deposition (CVD).

Thereafter, the second upper contact124may be formed in the second interlayer insulation layer30. That is to say, the second upper contact124may be formed while passing through the second interlayer insulation layer30. The second upper contact124may include, for example, at least one of a doped semiconductor, a metal, a conductive metal nitride, and a metal-semiconductor compound.

The second upper contact124may be formed in the second upper contact hole124hpassing through the second interlayer insulation layer30and exposing the second lower contact122. The second upper contact hole124hmay be formed by forming a mask pattern on the second interlayer insulation layer30and patterning the second interlayer insulation layer30using the mask pattern as an etch mask. The second upper contact124may be formed by filling the second upper contact hole124hwith a conductive material and planarizing the resultant product. As the result of the planarizing for forming the second upper contact124, a top surface of the second interlayer insulation layer30may also be planarized.

The second upper contact124is formed in the second interlayer insulation layer30, thereby forming the second contact120electrically connected to the second impurity region102. The second contact120may be formed while passing through the second interlayer insulation layer30and the first interlayer insulation layer20through operations of forming contacts multiple times.

Referring toFIGS. 7 and 8, a first trench32and a second trench34are formed in the second interlayer insulation layer30, thereby forming protrusions40. In detail, the first trench32may extend in the second direction DR2and may be formed in the second interlayer insulation layer30. The second trench34may extend in the first direction DR1and may be formed in the second interlayer insulation layer30. Each of the protrusions40shaped of, for example, a square pillar, may be formed on portions of the second interlayer insulation layer30, where the first trench32and the second trench34are not formed.

The second upper contact124remains in the protrusions40formed by the first trench32and the second trench34. That is to say, the first trench32and the second trench34are formed at a region not overlapping the second upper contact124formed in the second interlayer insulation layer30. Because the second upper contact124overlaps the underlying second impurity region102, the protrusions40overlap the second impurity region102formed in the substrate10.

In other words, the first and second interlayer insulation layers20and30are formed to cover the transistor100. The first and second interlayer insulation layers20and30may include the protrusions40defined by the first trench32and the second trench34. The protrusions40overlap the second impurity region102. That is to say, the first and second interlayer insulation layers20and30covering the transistor100include the protrusions40overlapping the second impurity region102.

A first trench32extending in the second direction DR2is formed between neighboring second contacts120arranged in the first direction DR1. The first contact115disposed between the neighboring second contacts120overlaps a bottom surface of the first trench32.

Because the protrusions40are formed by the first trench32and the second trench34crossing each other, one of opposed side surfaces40sof the protrusions40may correspond to side surfaces of the first trench32, the other of opposed side surfaces40sof the protrusions40may correspond to side surfaces of the second trench34. That is to say, as shown inFIG. 8, the side surfaces of the first trench32are shown from the cross-sectional view taken along the line A-A, and the side surfaces of the second trench34are shown from the cross-sectional view taken along the line B-B.

The top surface40uof the protrusion40may be the same plane as the top surface of the second interlayer insulation layer30before the first trench32and the second trench34are formed. Therefore, the top surface40uof the protrusion40exposes the second contact120, specifically, the second upper contact124.

In detail, a mask pattern covering the second contact120arranged in the second direction DR2is formed to extend in the second direction DR2. At least a portion of the second interlayer insulation layer30is removed using the mask pattern as an etch mask. The first trench32extending lengthwise in the second direction DR2is formed in the second interlayer insulation layer30by removing the at least a portion of the second interlayer insulation layer30. Thereafter, a mask pattern covering the first contact115and the second contact120arranged in the first direction DR1is formed to extend in the first direction DR1. At least a portion of the second interlayer insulation layer30is removed using the mask pattern as an etch mask. The second trench34extending lengthwise in the first direction DR1is formed in the second interlayer insulation layer30by removing the at least a portion of the second interlayer insulation layer30.

In addition, rectangular mask patterns covering the second contact120are formed to be spaced apart from each other in the first and second directions DR1and DR2. The first trench32and the second trench34may be simultaneously formed by removing the at least a portion of the second interlayer insulation layer30using the mask patterns as etch masks.

The etching for forming the first trench32and the second trench34may include at least one of dry etching and wet etching.

InFIG. 8, a depth of each of the first trench32and the second trench34is less than a height of the second upper contact124, but aspects of the present inventive subject matter are not limited thereto. That is to say, depths of the first trench32and/or the second trench34are equal to a thickness of the second interlayer insulation layer30, so that the bottom surface of the first trench32and/or the second trench34may correspond to the top surface of the first interlayer insulation layer20. In addition, the bottom surface of the first trench32and/or the second trench34is positioned in the first interlayer insulation layer20, so that the depth of each of the first trench32and the second trench34may be greater than the height of the second upper contact124.

Shapes of the protrusions40will now be described in detail with reference toFIGS. 7,9A and9B.

Referring toFIGS. 7 and 9A, the protrusion40may be shaped as a three-dimensional right prism.

It is assumed that the first interlayer insulation layer20is formed on the substrate10to have the same thickness. In this case, a normal line on the top surface of the substrate10is substantially parallel to a normal line NL on the top surface of the first interlayer insulation layer20. Here, for the protrusion40to have the three-dimensional right prism shape, the side surfaces40sof the protrusion40may be substantially parallel to the normal line NL on the top surface of the first interlayer insulation layer20. The terms “the same thickness” used herein may mean that thicknesses at two locations compared are perfectly equal to each other and may include a negligible thickness difference due to a processing margin, for example.

In addition, because the protrusion40is formed by the first trench32and the second trench34, it may have a three-dimensional right prism shape when the side surfaces40sof the first trench32and the bottom surface of the first trench32meet at right angle.

Referring toFIGS. 7 and 9B, the protrusion40according to an embodiment of the present inventive subject matter may be shaped as an inverted quadrangular pyramid.

That is to say, a width of the top portion of the protrusion40is a first width W1, and a width of the bottom surface of the protrusion40is a second width W2. Because the width W1of the top portion of the protrusion40is greater than the width W2of the bottom surface of the protrusion40, the protrusion40is shaped as an inverted quadrangular pyramid. In addition, the bottom portion of the protrusion40entirely overlaps the top portion of the protrusion40. The width of the protrusion40may continuously decrease from the top portion to the bottom portion of the protrusion40, but aspects of the present inventive subject matter are not limited thereto.

Referring toFIGS. 10A and 10B, an information storage unit130exposing the side surface40sof the protrusion40is formed on the protrusion40using PCM-PVD. The information storage unit130formed on the protrusion40is electrically connected to the second upper contact124formed in the protrusion40.

In other words, the information storage unit130is formed on the top surface40uof the protrusion40defined by the first trench32and the second trench34. That is to say, because the top surface40uof the protrusion40corresponds to the top surface of the second interlayer insulation layer30before the first trench32and the second trench34are formed, the information storage unit130is formed on the top surface of the second interlayer insulation layer30, which is not removed by the first trench32and the second trench34.

Because the second upper contact124is electrically connected to the second lower contact122, the information storage unit130is connected to the second lower contact122by means of the second upper contact124. Further, the information storage unit130is electrically connected to the second impurity region102.

Because the protrusion40is formed to overlap the second impurity region102, the second impurity region102, the second lower contact122, the second upper contact124and the information storage unit130overlap one another and are arranged in a line.

A dummy information storage unit132is formed on bottom surfaces of the first trench32and the second trench34. The dummy information storage unit132is formed at the same level as the information storage unit130formed on the protrusion40. The term “the same level” used herein may mean that two elements compared are formed by the same manufacturing process. While the dummy information storage unit132surrounds the circumference of the information storage unit130formed on the protrusion40, there is a step difference between the information storage unit130and the dummy information storage unit132, so that the information storage unit130and the dummy information storage unit132are electrically disconnected from each other.

The information storage unit130formed on the protrusion40and exposing the side surface40sof the protrusion40has the same structure as described above with reference toFIGS. 3A and 3B, and a repeated description of the information storage unit130will be omitted.

Referring toFIG. 10A, the information storage unit130is formed on the top surface40uof the protrusion40but is not formed on the side surface40sof the protrusion40. That is to say, the information storage unit130is not formed on the side surfaces of the first trench32and the second trench34.

Processing conditions of the PCM-PVD used in forming the information storage unit130, thereby forming the information storage unit130on the top surface40uof the protrusion40while not forming the information storage unit130on the side surface40sof the protrusion40, which will later be described in detail with reference toFIGS. 16 to 18.

Referring toFIG. 10B, the information storage unit130is formed on a portion of the side surface40sof the protrusion40as well as on the top surface40uof the protrusion40. That is to say, the information storage unit130covers portions of the upper side surfaces of the first trench32and the second trench34.

In detail, while a pre-information storage unit is formed on the second interlayer insulation layer30including the protrusion40. A thickness of the pre-information storage unit formed on the top surface40uof the protrusion40is greater than that of the pre-information storage unit formed on the side surface40sof the protrusion40, the pre-information storage unit may also be formed on the side surface40sof the protrusion40according to the processing condition.

After forming the pre-information storage unit, at least a portion of the pre-information storage unit formed on the side surface40sof the protrusion40is removed, thereby exposing the side surface40sof the protrusion40. In such a manner, the information storage unit130exposing the side surface40sof the protrusion40may be formed on the protrusion40. Nodes of the information storage unit130and the dummy information storage unit132are separated from each other by removing the at least a portion of the pre-information storage unit formed on the side surface40sof the protrusion40.

The removing of the pre-information storage unit formed on the side surface40sof the protrusion40may include performing an etching process using particles incident into the top surface40uof the protrusion40with a tilt angle. For example, the removing of the pre-information storage unit formed on the side surface40sof the protrusion40may be performed by etching using ion beam. When the pre-information storage unit formed on the side surface40sof the protrusion40is removed, the upper electrode described with reference toFIGS. 3A and 3Bmay be used as an etch mask, and a portion of the upper electrode may be removed by a sacrificial layer.

In the PCM-PVD used in forming the information storage unit130, a thickness of a layer formed on the top surface40uof the protrusion40is greater than that of a layer formed on the side surface40sof the protrusion40. However, when the information storage unit130is formed using the PCM-PVD, it may also be formed on the side surface40sof the protrusion40. Thus, the information storage unit formed on the side surface40sof the protrusion40is removed for node separation.

Hereinafter, the PCM-PVD used in forming the information storage unit130and experimental data carried out using the PCM-PVD will be described.

FIG. 16is a schematic view illustrating a point cusp magnetron-physical vapor deposition (PCM-PVD) used in the method for fabricating a nonvolatile memory device according to embodiments of the present inventive subject matter, andFIGS. 17 and 18illustrate experimental data obtained by depositing an information storage unit using the PCM-PVD shown inFIG. 16.

Referring toFIG. 16, at the same time when plasma is generated by applying RF current to a target, a point-cusp magnetic field is formed from magnets arranged on the target, thereby generating high-density plasma using PCM-PVD.

The point-cusp magnetic field is formed through arrangement of magnets disposed on the target. That is to say, neighboring magnets are arranged to have opposite polarities and all of the magnets are arranged at equal intervals. Such magnet arrangement forms a strong magnetic field, but a surface of a substrate is not affected by the point-cusp magnetic field. Thus, in a case of PCM-PVD, the substrate may be less damaged by plasma.

When a thin film is deposited using PCM-PVD, processing parameters may include, for example, RF power (W) of a target side for generating plasma, argon (Ar) gas pressure (Pa) for generating plasma through excitation, substrate bias power (W), and other parameters.

Referring toFIGS. 17 and 18, experimental data were obtained by conducting experiments after the target RF power was fixed to a constant value.

FIG. 17is a graph illustrating experimental data of side deposition rate (%) depending on the partial pressure of argon (Ar) gas used as a plasma source.

Referring toFIG. 17, as the partial pressure of argon (Ar) gas increases from 0 to 20 Pa, the side deposition rate is gradually reduced. The term “side deposition rate” used herein may mean a value obtained by dividing a thickness of a thin film deposited on a side surface of a protruding structure having a rectangular cross section by a thickness of a thin film deposited on a top surface of the protruding structure and multiplying by 100.

If the partial pressure of argon (Ar) gas increases, secondary electrons emitted from the target may contribute to an increased plasma density. In such a manner, if the plasma density in the PCM-PVD increases, the side deposition rate is reduced.

Under a deposition pressure having the partial pressure of argon (Ar) gas ranging from 10 Pa to 20 Pa, the side deposition rate is reduced to 15% or less. If the side deposition rate is reduced, the etching process for node separation may be performed, as described above with reference toFIG. 10B.

FIG. 18is a graph illustrating experimental data of side deposition rate (%) depending on the substrate bias power. Referring toFIG. 18, the experimental data were obtained by conducting experiments after the partial pressure of argon (Ar) gas used as a plasma source was fixed to 10 Pa.

Referring toFIG. 18, as the substrate bias power increases from 0 to 50 W, the side deposition rate is gradually reduced. That is to say, as the substrate bias power increases from 0 to 50 W, the side deposition rate is reduced from 15% to 0%.

In detail, if the substrate bias power is between 20 W and 50 W, the side deposition rate is reduced to 5% or less, and if the substrate bias power is greater than or equal to 30 W, the side deposition rate approaches nearly 0%. That is to say, the thin film is formed only on the top surface of the protruding structure while not being formed on lateral surfaces of the protruding structure.

Such experimental data may be attributable to increased straightness of a material emitted from the target to be deposited when the bias power applied to the substrate increases.

In addition, as confirmed from the experimental data shown inFIG. 17, when the partial pressure of argon (Ar) gas increased from about 10 Pa to about 20 Pa, the side deposition rate approaches nearly 0% even with a small amount of the bias power applied to the substrate.

In the method for fabricating a nonvolatile memory device according to the embodiment of the present inventive subject matter, the information storage unit130may be formed under a deposition pressure having the partial pressure of argon (Ar) gas ranging from about 10 Pa to about 20 Pa. In addition, the information storage unit130may be formed by applying bias power of about a 10 to about 50 W to the substrate.

Referring toFIG. 11, a third interlayer insulation layer50covering the information storage unit130and the dummy information storage unit132is formed. After forming the third interlayer insulation layer50, a second wiring140electrically connected to the information storage unit130is formed. The second wiring140may be electrically connected to the information storage unit130by a second wiring plug142, but aspects of the present inventive subject matter are not limited thereto. InFIG. 2, the second wiring140may be formed to extend lengthwise in the first direction DR1to then be electrically connected to the information storage unit130arranged in the first direction DR1.

The third interlayer insulation layer50may include, for example, at least one of an oxide layer, an oxynitride layer, and a nitride layer, and may be formed by chemical vapor deposition (CVD). The second wiring140and the second wiring plug142may include, for example, at least one of a metal and a conductive metal nitride. In detail, the second wiring140and the second wiring plug142may include copper (Cu).

In the method of fabricating a nonvolatile memory device according to an embodiment of the present inventive subject matter, the second wiring140is electrically connected to the information storage unit130by means of the second wiring plug142, but aspects of the present inventive subject matter are not limited thereto. That is to say, the second wiring140may be directly electrically connected to the information storage unit130without the second wiring plug142.

Next, a method for fabricating a nonvolatile memory device according to another embodiment of the present inventive subject matter will be described with reference toFIGS. 7 and 10Ato13.

FIGS. 12 and 13illustrate intermediate process steps for fabricating a nonvolatile memory device according to another embodiment of the present inventive subject matter.

Referring toFIG. 12, a transistor100is formed on a substrate10, the transistor100including a first impurity region104and a second impurity region102formed in the substrate10. After forming the transistor100, a first interlayer insulation layer20and a second interlayer insulation layer30covering the transistor100are formed. A second contact120is formed in the first interlayer insulation layer20and the second interlayer insulation layer30. The second contact120is electrically connected to the second impurity region102.

In detail, after forming the transistor100, the first interlayer insulation layer20covering the transistor100may be formed on the substrate10. A first contact115electrically connected to the first impurity region104is formed in the first interlayer insulation layer20. In addition, a first wiring110electrically connected to the first contact115and extending in the second direction DR2is formed on the first interlayer insulation layer20. Thereafter, a second interlayer insulation layer30covering the first wiring110is formed on the first interlayer insulation layer20.

The second contact120is formed in the first interlayer insulation layer20and the second interlayer insulation layer30. That is to say, the second contact120may be formed such that it continuously passes through the first interlayer insulation layer20and the second interlayer insulation layer30. The second contact120is formed on the second impurity region102formed in the substrate10to be electrically connected to the second impurity region102. The second contact120may include, for example, at least one of a doped semiconductor, a metal, a conductive metal nitride, and a metal-semiconductor compound.

The second contact120may be formed in a second contact hole120hsuch that it continuously passes through the second interlayer insulation layer30and the first interlayer insulation layer20to expose the second impurity region102. The second contact hole120hmay be formed by forming a mask pattern on the second interlayer insulation layer30and patterning the first interlayer insulation layer20and the second interlayer insulation layer30using the mask pattern as an etch mask. The second contact120may be formed by filling the second contact hole120hwith a conductive material and planarizing the resultant product.

Referring toFIGS. 7 and 13, a first trench32and a second trench34are formed in the second interlayer insulation layer30, thereby forming protrusions40. In detail, the first trench32may extend in a second direction DR2to then be formed in the second interlayer insulation layer30. The second trench34may extend in a first direction DR1to then be formed in the second interlayer insulation layer30. The protrusions40shaped of for example, a square pillar defined by the first trench32and the second trench34, may be formed in the second interlayer insulation layer30.

The first trench32extending in the second direction DR2is formed between neighboring second contacts120arranged in the first direction DR1. The first contact115disposed between the neighboring second contacts120overlaps a bottom surface of the first trench32.

Because the first wiring110covered by the second interlayer insulation layer30may not be exposed by the first trench32, a depth of the first trench32is less than a thickness of the second interlayer insulation layer30.

Thereafter, referring toFIGS. 10A to 11, an information storage unit130is formed on a top surface40uof the protrusion40, and a second wiring140electrically connected to the information storage unit130is then formed.

In the method of fabricating a nonvolatile memory device according to an embodiment of the present inventive subject matter, the information storage unit130includes lower electrodes130aand130fshown inFIGS. 3A and 3B, but aspects of the present inventive subject matter are not limited thereto. That is to say, referring toFIGS. 6 and 12, after forming the second contact120, a lower electrode layer may be formed on the second interlayer insulation layer30. In such a case, in the course of forming the first trench32and the second trench34to define the protrusion40, the lower electrode layer may also be patterned. The patterned lower electrode layer remains on the top surface40uof the protrusion40. The lower electrode layer remaining on the top surface40uof the protrusion40becomes lower electrodes130aand130f. An information storage unit130to later be formed may be formed by sequentially stacking reference patterns130cand130h, tunnel barrier patterns130dand130i, free patterns130eand130jand upper electrodes130band130g, except for the lower electrodes130aand130f.

The nonvolatile memory device fabricated according to embodiments of the present invention may be implemented as various semiconductor packages. For example, the nonvolatile memory device according to embodiments of the present inventive subject matter may be mounted in various packages, such as PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), or Wafer-Level Processed Stack Package (WSP).

FIG. 14is a schematic block diagram illustrating a system including a nonvolatile memory device fabricated according to embodiments of the present inventive subject matter.

Referring toFIG. 14, the system900according to an embodiment of the present inventive subject matter may be applied to a wireless communication device, for example, a personal digital assistant (PDA), a laptop computer, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or all devices capable of transmitting and/or receiving information under wireless environments.

The system900may include a controller910, an input/output (I/O) device such as a key pad, a key board, or a display, a memory930, and a wireless interface940, which are connected to each other through a bus. The controller910may include, for example, at least one of a microprocessor, a digital signal processor, and the like. The memory930may store data and/or commands (or user data) processed by the controller910, for example. The memory930may include nonvolatile memories according to various embodiments of the present invention. The memory930may further include different types of memories, a volatile memory accessible at an arbitrary time, and other kinds of memories.

The system900may use a wireless interface940to transmit data to a wireless communication network or receive data from the communication network. For example, the wireless interface940may include an antenna or a wireless transceiver.

The system900according to an embodiment of the present inventive subject matter may be used in a communication interface protocol for a next-generation communication system, such as Code Division Multiple Access (CDMA), Global System for Mobile Communication (GSM), North American Digital Cellular (NADC), Time Division Multiple Access (TDMA), Extended Time Division Multiple Access (E-TDMA), Wideband Code Division Multiple Access (WCDMA), or Code Division Multiple Access 2000 (CDMA2000). The nonvolatile memory device fabricated according to an embodiment of the present inventive subject matter may be applied to a memory card to be described later with reference toFIG. 15.

FIG. 15is a schematic block diagram illustrating a memory card to which a nonvolatile memory device fabricated according to embodiments of the present inventive subject matter is applied.

Referring toFIG. 15, the memory card1000according to an embodiment of the present inventive subject matter may include an encryption circuit1010, a logic circuit1020, a digital signal processor (DSP)1030, which is a dedicated processor, and a main processor1040. In addition, the memory card1000may include a nonvolatile memory device1100according to various embodiments of the present inventive subject matter, and other various types of memories including, for example, SRAM1050, DRAM1060, ROM1070, a flash memory1120, and other memories.

The memory card1000may include an RF (high frequency wave/microwave) circuit1080and an input/output circuit1090. Various functional blocks1010-1120provided in the memory card1000may be connected to each other through a system bus1200. The memory card1000operates under the control of an external host. The nonvolatile memory device1100according to an embodiment of the present inventive subject matter may store data or may output stored data under the control of the host.