Display device which is capable of implementing an LED in a non-transfer manner and method of manufacturing the same

Provided is a display device. The display device includes a first substrate and a second substrate which are formed of different materials; a first LED disposed on the first substrate; and a second LED and a third LED disposed on the second substrate, in which the first LED, the second LED, and the third LED are disposed between the first substrate and the second substrate. Therefore, in consideration of the growth efficiency of the LEDs which emit different colored light, the first LED is disposed on the first substrate and the second LED and the third LED are disposed on the second substrate which is formed of a different material from the first substrate, thereby improving the growth efficiency of the plurality of LEDs.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Korean Patent Application No. 10-2018-0140534 filed on Nov. 15, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

BACKGROUND

Technical Field

The present disclosure relates to a display device and a method of manufacturing the same, and more particularly to, a display device using a micro light emitting diode (LED) and a method of manufacturing the same.

Description of the Related Art

As display devices which are used for a monitor of a computer, a television, or a cellular phone, there are an organic light emitting display device (OLED) which is a self-emitting device and a liquid crystal display device (LCD) which typically has a separate light source.

An applicable range of the display device is diversified to personal digital assistants as well as monitors of computers and televisions and a display device with a large display area and a reduced volume and weight is being studied.

Further, in recent years, a display device including an LED is attracting attention as a next generation display device. Since the LED is formed of an inorganic material, rather than an organic material, reliability is excellent so that a lifespan thereof is longer than the liquid crystal display device or the organic light emitting display device. Further, the LED has a fast lighting speed, excellent luminous efficiency, and strong impact resistance so that stability is excellent and an image having high luminance can be displayed.

BRIEF SUMMARY

In order to manufacture an light emitting diode (LED), an epitaxial layer is grown on one wafer to form a plurality of LEDs. The LED which is completely manufactured in the wafer is transferred onto a backplane substrate to form a display device. However, when the display device including an LED is manufactured by individually transferring the plurality of LEDs, a process time is increased, and a manufacturing cost is also increased.

Therefore, in order to simplify the LED transferring process, inventors of the present disclosure invented a display device including a non-transfer type LED in which a driving unit including a thin film transistor and a capacitor is formed on a wafer on which the LED is grown.

However, growth efficiency of a red LED, a blue LED, and a green LED varies depending on the type of wafers so that it is difficult to concurrently grow the red LED, the blue LED, and the green LED on one wafer. Therefore, in order to implement a non-transfer type LED, the inventors of the present disclosure recognized that even though a plurality of driving units is formed on a wafer on which any one of the red LED, the blue LED, and the green LED is grown, it is difficult to grow LEDs which emit remaining color light on the wafer on which the plurality of driving units is formed. That is, the inventors of the present disclosure recognized that some LEDs can be implemented by a non-transfer type by forming a driving unit on the wafer, but the remaining LEDs should be transferred onto a wafer on which some LEDs are formed.

Therefore, the inventors of the present disclosure invented a display device which is capable of implementing all a red LED, a blue RED, and a green RED in a non-transfer manner and a method of manufacturing the same.

Various embodiments of the present disclosure provide a display device and a method of manufacturing the same in which a transferring process of a plurality of LEDs are simplified by using a wafer on which the plurality of LEDs is grown, as an upper substrate and a lower substrate of the display device.

Various embodiments of the present disclosure provide a display device and a method of manufacturing the same in which LEDs which emit different color light are grown on different substrates in consideration of growth efficiency to improve the efficiency of the LEDs.

Various embodiments of the present disclosure provide a display device and a method of manufacturing the same in which a plurality of LEDs and a plurality of driving units are formed on the same substrate to shorten a process time.

The various embodiments of the present disclosure are not limited to the above-mentioned embodiments, and other embodiments, which are not mentioned above, can be clearly understood by those skilled in the art from the following descriptions.

According to an embodiment of the present disclosure, a display device includes a first substrate and a second substrate that are formed of different materials, a first LED on the first substrate, and a second LED and a third LED on the second substrate, in which the first LED, the second LED, and the third LED are positioned between the first substrate and the second substrate. Therefore, in consideration of the growth efficiency of the LEDs which emit different colored light, the first LED is on the first substrate, and the second LED and the third LED are on the second substrate which is formed of a different material from the first substrate, thereby improving the growth efficiency of the plurality of LEDs.

According to another embodiment of the present disclosure, a display device includes a first substrate, a first light emitting diode (LED) on a surface of the first substrate, a second substrate, and a second LED and a third LED on a surface of the second substrate. The surface of the first substrate faces the surface of the second substrate. Growth efficiency of the first LED on the surface of the first substrate is higher than that on the second substrate, and growth efficiency of the second LED and the third LED on the surface of the second substrate is higher than that on the first substrate. Therefore, the first substrate on which the first LED is disposed and the second substrate on which the second LED and the third LED are disposed are disposed to be opposite to each other, thereby disposing the plurality of LEDs in a non-transfer manner.

According to still another embodiment of the present disclosure, a method of manufacturing a display device includes forming a first LED on one surface of a first substrate, forming a second LED and a third LED on one surface of a second substrate, and bonding the first substrate and the second substrate such that one surface of the first substrate and one surface of the second substrate are opposite to each other. Therefore, a wafer on which the plurality of LEDs is grown is used as an upper substrate and a lower substrate of the display device so that a transferring process of the LED is omitted, and the process time may be shortened.

According to the present disclosure, a plurality of LEDs is implemented in a display device in a non-transfer manner to shorten a process time as compared with a transferring manner.

According to the present disclosure, a plurality of LEDs is implemented in a display device in a non-transfer manner to reduce a non-adhering failure of the plurality of LEDs.

According to the present disclosure, a plurality of LEDs which is grown on different substrates in consideration of growth efficiency of the LED is disposed in a display device to improve luminous efficiency of the plurality of LEDs.

DETAILED DESCRIPTION

FIG.1is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure. InFIG.1, for the convenience of description, among various components of a display device100, only a first substrate110a, a second substrate110b, and a pixel PX are illustrated.

The first substrate110aand the second substrate110bare components for supporting various components included in the display device100. For example, the first substrate110aand the second substrate110bmay be formed of sapphire, gallium nitride, gallium arsenide, gallium phosphide, silicon, glass, or resin. Further, the first substrate110aand the second substrate110bmay be formed to include polymer or plastic or may be formed of a plastic material having flexibility.

The first substrate110aand the second substrate110binclude a display area AA and a non-display area NA.

The display area AA is an area where a plurality of pixels PX is disposed to display images. A display element and a driving circuit for driving the display element may be disposed in each of the plurality of pixels PX of the display area AA. For example, a display element and a semiconductor element for driving the display element may be disposed in each of the plurality of pixels PX.

The non-display area NA is an area where no image is displayed and various wiring lines and driver ICs for driving the plurality of pixels PX disposed in the display area AA are disposed. For example, in the non-display area NA, various ICs and driving circuits such as a gate driver IC and a data driver IC may be disposed.

The plurality of pixels PX is defined in the display area AA of the first substrate110aand the second substrate110b. The plurality of pixels PX is individual units which emit light and each of the plurality of pixels PX may include a plurality of sub pixels. One pixel may emit various color light by a combination of the plurality of sub pixels. For example, each of the plurality of pixels PX may be formed of a red sub pixel, a green sub pixel, and a blue sub pixel, but is not limited thereto.

Hereinafter, the light emitting diode (LED) and the driving unit disposed in each of the plurality of pixels PX will be described with reference toFIG.2.

FIG.2is a schematic cross-sectional view of one pixel of a display device according to an exemplary embodiment of the present disclosure. InFIG.2, for the convenience of description, only a first substrate110a, a second substrate110b, a plurality of LEDs120,130, and140, a plurality of driving units DP, a second drain pad electrode163P, a plurality of power lines PL, a first protective layer114, a second protective layer116, a filling member117, and a connecting unit180are schematically illustrated.

Referring toFIG.2, a plurality of LEDs120,130, and140is disposed on one surface of the first substrate110aand one surface of the second substrate110b. Each of the plurality of LEDs120,130, and140is disposed in each of the plurality of sub pixels SPX1, SPX2, and SPX3, respectively. The plurality of LEDs120,130, and140is a light emitting device which emits light at the time of applying a voltage. The plurality of LEDs120,130, and140may include LEDs which emit red light, green light, and blue light and implement various colored light including white by a combination of the LEDs.

The plurality of LEDs120,130, and140includes a first LED120, a second LED130, and a third LED140.

The first LED120is disposed in a first sub pixel SPX1on one surface of the first substrate110a. The second LED130is disposed in a second sub pixel SPX2on one surface of the second substrate110b. The third LED140is disposed in a third sub pixel SPX3on one surface of the second substrate110b.

Hereinafter, for the convenience of description, an upper surface of the first substrate110aon which the first LED120is disposed and which is opposite to the second LED130and the third LED140is assumed as one surface of the first substrate110a. Further, a lower surface of the second substrate110bon which the second LED130and the third LED140are disposed and which is opposite to the first LED120is assumed as one surface of the second substrate110b.

In the meantime, when the plurality of LEDs120130, and140emits different colored light, some of the plurality of LEDs120,130, and140may be a red LED which emits red light and the other of the plurality of LEDs120,130, and140may be a green LED which emits green light, and the rest of the plurality of LEDs120,130, and140may be a blue LED which emits blue light. Since the plurality of LEDs120,130, and140emits different colored light, a member such as a color conversion layer may be omitted. Hereinafter, it is assumed that among the plurality of LEDs120,130, and140, a first LED120is a red LED, a second LED130is a blue LED, and a third LED140is a green LED.

The plurality of driving units DP is disposed on the plurality of sub pixels SPX1, SPX2, and SPX3, respectively, on one surface of the first substrate110a. The plurality of driving units DP is driving circuits for driving the plurality of LEDs120,130, and140. The plurality of driving units DP includes a plurality of semiconductor elements and capacitors, which will be described below with reference toFIG.3.

Among the plurality of driving units DP, a driving unit DP disposed in the first sub pixel SPX1drives the first LED120of the first sub pixel SPX1on one surface of the first substrate110a. The driving unit DP disposed in the first sub pixel SPX1is connected to the first LED120through the second drain pad electrode163P. Among the plurality of driving units DP, a driving unit DP disposed in the second sub pixel SPX2drives the second LED130of the second sub pixel SPX2on one surface of the second substrate110b. The driving unit DP disposed in the second sub pixel SPX2is connected to the second LED130through the connecting unit180. Among the plurality of driving units DP, a driving unit DP disposed in the third sub pixel SPX3drives the third LED140of the third sub pixel SPX3on one surface of the second substrate110b. The driving unit DP disposed in the third sub pixel SPX3is connected to the third LED140through the connecting unit180.

The second drain pad electrode163P is an electrode which is electrically connected to a second drain region of the second semiconductor element of the driving unit DP and electrically connects the second semiconductor element to the first LED120. The second drain pad electrode163P will be described below with reference toFIGS.3to6.

The plurality of power lines PL is disposed on one surface of the first substrate110a. The plurality of power lines PL transmits power voltages to the plurality of sub pixels SPX1, SPX2, and SPX3, respectively. The plurality of power lines PL may extend from the display area AA to the non-display area NA and receive the power voltage from the driver IC disposed in the non-display area NA to transmit the power voltage to the plurality of LEDs120,130, and140.

The first protective layer114is disposed on one surface of the first substrate110aso as to cover the first LED120, the plurality of driving units DP, and the plurality of power lines PL of the first substrate110a. The first protective layer114is a layer for protecting the first LED120, the plurality of driving units DP, and the plurality of power lines PL on the first substrate110a. The first protective layer114may be configured by a single layer or a double layer of translucent epoxy, silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto. Further, even though inFIG.2, it is illustrated that the upper surface of the first protective layer114is flat, the first protective layer114may be formed in accordance with the shapes of the first LED120, the plurality of driving units DP, and the plurality of power lines PL, but is not limited thereto.

The second protective layer116is disposed on one surface of the second substrate110bso as to cover the second LED130and the third LED140of the second substrate110b. The second protective layer116is a layer for protecting the second LED130and the third LED140on one surface of the second substrate110b. The second protective layer116may be configured by a single layer or a double layer of translucent epoxy, silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto. Further, even though inFIG.2, it is illustrated that a lower surface of the second protective layer116which is opposite to the upper surface of the first protective layer114is flat, the second protective layer116may be disposed in accordance with the shapes of the second LED130and the third LED140, but is not limited thereto.

The filling member117is disposed between the first protective layer114and the second protective layer116. The filling member117is disposed to fill the space between the upper surface of the first protective layer114and the lower surface of the second protective layer116. That is, the filling member117may be disposed between one surface of the first substrate110aand one surface of the second substrate110bwhich are opposite to each other. The filling member117may minimize foreign matters from permeating between one surface of the first substrate110aand one surface of the second substrate110band support the first substrate110aand the second substrate110bto maintain a strong bonded state.

In order to connect the plurality of driving units DP disposed on one surface of the first substrate110aand the second LED130and the third LED140disposed on one surface of the second substrate110b, a plurality of connecting units180is disposed. The plurality of connecting units180electrically connects the second LED130of the second substrate110bto the driving unit DP and the power line PL disposed in the second sub pixel SPX2of the first substrate110a. The plurality of connecting units180electrically connects the third LED140of the second substrate110bto the driving unit DP and the power line PL disposed in the third sub pixel SPX3of the first substrate110a. Therefore, the voltage may be supplied from the power line PL and the driving unit DP to the second LED130and the third LED140of one surface of the second substrate110bthrough the plurality of connecting units180and light may be emitted from the second LED130and the third LED140. The plurality of connecting units180will be described in more detail below with reference toFIGS.4and6.

In the display device100according to one exemplary embodiment of the present disclosure, the first LED120, the plurality of driving units DP, and the plurality of power lines PL are disposed on one surface of the first substrate110aand the second LED130and the third LED140are disposed on one surface of the second substrate110b. In this case, the first substrate110aand the second substrate110bmay be disposed such that one surface of the first substrate110aand one surface of the second substrate110bare opposite to each other. Further, the plurality of driving units DP and the plurality of power lines PL of the first substrate110aare electrically connected to the second LED130and the third LED140of the second substrate110bthrough the plurality of connecting units180so that one display device100may be implemented.

Hereinafter, each of the plurality of sub pixels SPX1, SPX2, and SPX3will be described in more detail with reference toFIGS.3to6.

FIG.3is a plan view of one pixel on one surface of a first substrate of a display device according to an exemplary embodiment of the present disclosure.FIG.4is a plan view of one pixel on one surface of a second substrate of a display device according to an exemplary embodiment of the present disclosure.FIG.5is a cross-sectional view of a display device taken along the line ofFIG.3.FIG.6is a cross-sectional view of a display device taken along the line IV-IV′ ofFIG.3. In the meantime, for the convenience of description, inFIG.3, a reflective layer190is omitted.

Referring toFIGS.3,5, and6, the first LED120, the plurality of driving units DP, the plurality of wiring lines, and a first connecting unit181among the plurality of connecting units180are disposed on one surface of the first substrate110a.

The first LED120is disposed in the first sub pixel SPX1. The first LED120includes a first n-type semiconductor layer121, a first light emitting layer122, a first p-type semiconductor layer123, a first n-type electrode121P, and a first p-type electrode123P.

The first n-type semiconductor layer121is disposed on one surface of the first substrate110aand the first p-type semiconductor layer123is disposed on the first n-type semiconductor layer121. The first n-type semiconductor layer121and the first p-type semiconductor layer123may be formed by implanting n-type and p-type impurities into gallium nitride GaN. For example, the p-type impurity may be magnesium (Mg), zinc (Zn), and beryllium (Be), and the n-type impurity may be silicon (Si), germanium (Ge), and tin (Sn), but are not limited thereto.

The first light emitting layer122is disposed between the first n-type semiconductor layer121and the first p-type semiconductor layer123. The first light emitting layer122is supplied with holes and electrons from the first n-type semiconductor layer121and the first p-type semiconductor layer123to emit light. For example, the first light emitting layer122is supplied with holes and electrons from the first n-type semiconductor layer121and the first p-type semiconductor layer123to emit red light. Hereinafter, it is assumed that the first LED120including the first light emitting layer122is a red LED.

The first light emitting layer122may be formed by a single layer or a multi-quantum well (MQW) structure, for example, the first light emitting layer122may be formed of indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

A part of the first n-type semiconductor layer121outwardly protrudes from the first light emitting layer122and the first p-type semiconductor layer123. The first light emitting layer122and the first p-type semiconductor layer123may have a smaller area than the first n-type semiconductor layer121so as to expose an upper surface of the first n-type semiconductor layer121. The first n-type semiconductor layer121may be exposed from the first light emitting layer122and the first p-type semiconductor layer123so as to be electrically connected to the first n-type electrode121P.

A first passivation layer112is disposed so as to cover the first n-type semiconductor layer121, the first light emitting layer122, and the first p-type semiconductor layer123. The first passivation layer112is an insulating layer which protects components below the first passivation layer112and suppresses the electrical short circuit of the first n-type semiconductor layer121and the first p-type semiconductor layer123. Specifically, the first n-type semiconductor layer121and the first p-type semiconductor layer123are electrically connected to different electrodes to supply electrons and holes to the first light emitting layer122. When the electrode which is electrically connected to the first n-type semiconductor layer121or the first p-type semiconductor layer123is in contact with the first p-type semiconductor layer123or the first n-type semiconductor layer121, the short circuit may be caused. Therefore, the first passivation layer112may be disposed as an insulating layer which insulates the first n-type semiconductor layer121from the first p-type semiconductor layer123. For example, the first passivation layer112may be configured by a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

In the meantime, the plurality of LEDs may be formed by various structures such as a lateral structure, a vertical structure, and a flip-chip structure. A lateral type LED includes a light emitting layer and an n-type electrode and a p-type electrode which are horizontally disposed on both sides of the light emitting layer. The lateral type LED emits light by coupling electrons supplied to the light emitting layer through the n-type electrode and holes supplied to the light emitting layer through the p-type electrode. A vertical type LED includes a light emitting layer and an n-type electrode and a p-type electrode which are disposed above and below the light emitting layer, respectively. Similarly to the lateral type LED, the vertical type LED also emits light by coupling the electrons and holes supplied from the n-type electrode and the p-type electrode. The flip-chip LED has substantially the same structure as the lateral type LED. However, the flip-chip LED120may be directly bonded to a printed circuit board by omitting a medium such as a metal wire. Hereinafter, for the convenience of description, among the plurality of LEDs120,130, and140of the display device100according to one exemplary embodiment of the present disclosure, it is assumed that the first LED120has a lateral structure, and the second LED130and the third LED140have a flip-chip structure. However, the present disclosure is not limited thereto.

The first n-type electrode121P and the first p-type electrode123P are disposed on the first passivation layer112. The first n-type electrode121P may be electrically connected to the first n-type semiconductor layer121and the first p-type electrode123P may be electrically connected to the first p-type semiconductor layer123. Specifically, a contact hole which exposes a part of the upper surface of the first n-type semiconductor layer121is disposed on the first passivation layer112. The first n-type electrode121P may be in contact with the upper surface of the first n-type semiconductor layer121through the contact hole. A contact hole which exposes a part of the upper surface of the first p-type semiconductor layer123is disposed on the first passivation layer112. The first p-type electrode123P may be in contact with the upper surface of the first p-type semiconductor layer123through the contact hole. Therefore, the first n-type electrode121P and the first p-type electrode123P may be in contact with the first n-type semiconductor layer121and the first p-type semiconductor layer123through the contact hole of the first passivation layer112to be electrically connected thereto.

The plurality of driving units DP is disposed in the plurality of sub pixels SPX1, SPX2, and SPX3, respectively. The plurality of wiring lines is disposed along boundaries between the plurality of sub pixels SPX1, SPX2, and SPX3. The plurality of driving units DP is disposed in the first sub pixels SPX1, the second sub pixels SPX2, and the third sub pixels SPX3, respectively and each of the plurality of driving units DP is configured by the first semiconductor element150, a second semiconductor element160, and a capacitor170.

The plurality of wiring lines includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of power lines PL, and a plurality of common lines CL and the plurality of lines is connected to the plurality of driving units DP, respectively, to drive the plurality of driving units DP.

First, a driving unit DP disposed in the first sub pixel SPX1includes a first semiconductor element150, a second semiconductor element160, and a capacitor170.

The first semiconductor element150and the second semiconductor element160are disposed in the first sub pixel SPX1of one surface of the first substrate110a. The first semiconductor element150and the second semiconductor element160may be used as driving elements of the display device100. The first semiconductor element150and the second semiconductor element160may be a field effect transistor (FET) such as a thin film transistor (TFT), an N-channel metal oxide semiconductor (NMOS), a P-channel metal oxide semiconductor (PMOS), and a complementary metal oxide semiconductor (CMOS), but are not limited thereto. Hereinafter, it is assumed that the first semiconductor element150and the second semiconductor element160are N-channel metal oxide semiconductors among the field effect transistors, but are not limited thereto.

The first semiconductor element150includes a first gate electrode151, a first source region152, and a first drain region153.

The first source region152and the first drain region153are spaced apart from each other to be disposed on one surface of the first substrate110a. The first source region152and the first drain region153may be formed by doping n-type or p-type impurities on the first substrate110a. In this case, the first substrate110amay be a p-type or an n-type substrate. For example, when the first substrate110ais a p-type substrate, the first source region152and the first drain region153may be formed by injecting the n-type impurities such as arsenic and phosphorus. Further, when the first substrate110ais an n-type substrate, the first source region152and the first drain region153may be formed by injecting the p-type impurities such as boron. Hereinafter, it is assumed that the first substrate110ais a p-type substrate and n-type impurities are injected into the first source region152and the first drain region153, but the present disclosure is not limited thereto.

A gate insulating layer111is disposed between the first source region152and the first drain region153. The gate insulating layer111is a layer for insulating the first source region152and the first drain region153from the first gate electrode151. The gate insulating layer111is formed of an insulating material. For example, the gate insulating layer111may be configured by a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

A first gate electrode151is disposed on the gate insulating layer111. The first gate electrode151may be electrically connected to a gate line GL. When a gate voltage is applied from the gate line GL to the first gate electrode151, the first semiconductor element150may be turned on. For example, the first gate electrode151may be formed of a conductive material such as poly silicon or molybdenum (Mo), but is not limited thereto.

In this case, the first passivation layer112is disposed on the first semiconductor element150. The first passivation layer112may be disposed so as to cover the first gate electrode151, the first source region152, and the first drain region153of the first semiconductor element150, together with the first n-type semiconductor layer121, the first light emitting layer122, and the first p-type semiconductor layer123of the first LED120.

A first gate pad electrode151P, a first source pad electrode152P, and a first drain pad electrode153P are disposed on the first passivation layer112. The first gate pad electrode151P, the first source pad electrode152P, and the first drain pad electrode153P may be electrically connected to the first gate electrode151, the first source region152, and the first drain region153, respectively.

First, the first gate pad electrode151P electrically connects the first gate electrode151and the gate line GL. The first gate pad electrode151P is integrally formed with the gate line GL to be in contact with the first gate electrode151.

Specifically, a contact hole which exposes the upper surface of the first gate electrode151may be disposed on the first passivation layer112. Further, the first gate pad electrode151P extending from the gate line GL to the first gate electrode151may be in contact with the upper surface of the first gate electrode151through the contact hole of the first passivation layer112. Therefore, the gate line GL and the first gate electrode151may be electrically connected to each other by the first gate pad electrode151P.

The first source pad electrode152P electrically connects the first source region152and the data line DL to each other. Specifically, a contact hole which exposes the first source region152may be disposed on the first passivation layer112. One end of the first source pad electrode152P may be in contact with the first source region152through the contact hole of the first passivation layer112. Further, the other end of the first source pad electrode152P extends to the data line DL to be electrically connected to the data line DL. Accordingly, one end of the first source pad electrode152P is in contact with the first source region152and the other end is in contact with the data line DL so that the first source region152of the first semiconductor element150may be electrically connected to the data line DL.

The first drain pad electrode153P may be electrically connected to the first drain region153. Specifically, a contact hole which exposes the first drain region153may be disposed on the first passivation layer112. One end of the first drain pad electrode153P may be in contact with the first drain region153through the contact hole of the first passivation layer112. Accordingly, the first drain pad electrode153P may be electrically connected to the first drain region153through the contact hole of the first passivation layer112.

In this case, a first capacitor electrode171which extends from the first drain pad electrode153P is disposed on the first passivation layer112. The first capacitor electrode171is included in the capacitor170together with a dielectric layer172and a second capacitor electrode173which will be described below.

In the meantime, the first drain region153of the first semiconductor element150and the second gate electrode161of the second semiconductor element160are electrically connected to each other through the first drain pad electrode153P, the first capacitor electrode171, and a second gate pad electrode161P to be described below. The first drain pad electrode153P, the first capacitor electrode171, and the second gate pad electrode161P may be integrally formed with each other. As the second gate pad electrode161P which is integrally formed with the first drain pad electrode153P is in contact with the second gate electrode161of the second semiconductor element160, the first drain region153of the first semiconductor element150may be electrically connected to the second gate electrode161of the second semiconductor element160. Therefore, the first drain region153of the first semiconductor element150and the second gate electrode161of the second semiconductor element160are electrically connected to each other by the first drain pad electrode153P, the first capacitor electrode171, and the second gate pad electrode161P which are integrally formed.

The second semiconductor element160includes a second gate electrode161, a second source region162, and a second drain region163.

The second source region162and the second drain region163are spaced apart from each other to be disposed on one surface of the first substrate110a. The second source region162and the second drain region163may be formed by doping n-type or p-type impurities on a p-type or an n-type substrate. As described above, it is assumed that the first substrate110ais a p-type substrate and n-type impurities are injected into the second source region162and the second drain region163, but the present disclosure is not limited thereto.

The gate insulating layer111is disposed between the second source region162and the second drain region163, and the second gate electrode161is disposed on the gate insulating layer111. For example, the second gate electrode161may be formed of a conductive material such as poly silicon and molybdenum (Mo), but is not limited thereto.

The second gate electrode161is electrically connected to the first drain region153of the first semiconductor element150. Specifically, the second gate electrode161may be electrically connected to the first drain region153of the first semiconductor element150through the second gate pad electrode161P, the first capacitor electrode171, and the first drain pad electrode153P. The first semiconductor element150transmits the voltage to the second semiconductor element160which is electrically connected thereto through the first drain region153to control the second semiconductor element160to be turned on or off.

The first passivation layer112is disposed on the second semiconductor element160and the second gate pad electrode161P, the second source pad electrode162P, and the second drain pad electrode163P are disposed on the first passivation layer112. The second gate pad electrode161P, the second source pad electrode162P, and the second drain pad electrode163P may be electrically connected to the second gate electrode161, the second source region162, and the second drain region163, respectively.

The second gate pad electrode161P electrically connects the second gate electrode161to the first drain region153of the first semiconductor element150. Specifically, a contact hole which exposes a part of an upper surface of the second gate electrode161may be disposed on the first passivation layer112. The second gate pad electrode161P may be in contact with the upper surface of the second gate electrode161through the contact hole of the first passivation layer112. In this case, the second gate pad electrode161P is integrally formed with the first drain pad electrode153P and the first capacitor electrode171. Therefore, the second gate electrode161may be electrically connected to the first drain region153of the first semiconductor element150through the second gate pad electrode161P, the first capacitor electrode171, and the first drain pad electrode153P.

In the meantime, the second drain pad electrode163P is electrically connected to the first LED120. The second drain pad electrode163P is integrally formed with the first n-type electrode121P of the first LED120to electrically connect the second drain region163to the first n-type semiconductor layer121. However, the second drain pad electrode163P and the first n-type electrode121P may not be integrally formed with each other, but may be individually disposed, and the present disclosure is not limited thereto.

The gate line GL and the power line PL are disposed on the first passivation layer112. The gate line GL transmits the gate voltage to the driving units DP of the plurality of sub pixels SPX1, SPX2and SPX3. Specifically, the gate line GL transmits the gate voltage to the first gate electrode151of the first semiconductor element150of each of the plurality of driving units DP. The gate line GL may extend from the display area AA to the non-display area NA. The gate line GL may be supplied with the gate voltage from the gate driver IC disposed in the non-display area NA to transmit the gate voltage to the first gate electrode151of the first semiconductor element150of each of the plurality of driving units DP.

The power line PL transmits the power voltage to the plurality of LEDs120,130, and140of the plurality of sub pixels SPX1, SPX2and SPX3, respectively. Specifically, the power line PL transmits the power voltage to the p-type electrodes123P,133P, and143P of the plurality of LEDs120,130, and140. The power line PL may extend from the display area AA to the non-display area NA. The power line PL may be supplied with the power voltage from the driver IC disposed in the non-display area NA to transmit the power voltage to the plurality of LEDs120,130, and140of the plurality of sub pixels SPX1, SPX2, and SPX3.

In the meantime, the power line PL is electrically connected to the first LED120. Specifically, the power line PL and the first p-type electrode123P of the first LED120are integrally formed with each other to electrically connect the power line PL to the first p-type semiconductor layer123. However, the power line PL and the first p-type electrode123P may not be integrally formed with each other, but may be individually formed and the present disclosure is not limited thereto.

A second passivation layer113is disposed on the gate line GL, the power line PL, the first gate pad electrode151P, the first source pad electrode152P, the first drain pad electrode153P, the second gate pad electrode161P, the second source pad electrode162P, the second drain pad electrode163P, and the first capacitor electrode171. The second passivation layer113is a layer for protecting and insulating components below the second passivation layer113and may be formed of an insulating material. For example, the second passivation layer113may be configured by a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

The data line DL and the common line CL are disposed on the second passivation layer113.

The data line DL transmits a data voltage to the driving units DP of the plurality of sub pixels SPX1, SPX2and SPX3, respectively. Specifically, the data line DL transmits the data voltage to the first source region152of the first semiconductor element150of each of the plurality of driving units DP. The data line DL may extend from the display area AA to the non-display area NA. The data line DL may be supplied with the data voltage from the data driver IC disposed in the non-display area NA to transmit the data voltage to the first source region152of the first semiconductor element150of each of the plurality of driving units DP.

The common line CL transmits a common voltage to the driving units DP of the plurality of sub pixels SPX1, SPX2and SPX3, respectively. Specifically, the common line CL may extend from the display area AA to the non-display area NA. The common line CL may transmit the common voltage from the gate driver IC disposed in the non-display area NA to the second capacitor electrode173and the second source region162of the second semiconductor element160of each of the plurality of driving units DP.

The second capacitor electrode173is disposed on the second passivation layer113so as to overlap the first capacitor electrode171. The dielectric layer172is disposed between the first capacitor electrode171and the second capacitor electrode173. Specifically, the first capacitor electrode171and the second capacitor electrode173overlap each other with the dielectric layer172therebetween to form the capacitor170. The capacitor170stores the data voltage to maintain the plurality of LEDs120,130, and140in the same state until a next gate voltage is applied to the gate line GL.

A contact hole which exposes the first capacitor electrode171may be disposed on the second passivation layer113. Further, the dielectric layer172may be disposed to fill the contact hole of the second passivation layer113. The dielectric layer172may insulate the first capacitor electrode171from the second capacitor electrode173. The dielectric layer172may improve a capacitance of the capacitor170. Specifically, the permittivity of the dielectric layer172may be in proportional to the charging capacity of the capacitor170so that the dielectric layer172is formed of a high-K material having a large dielectric constant to improve the capacitance of the capacitor170. However, the dielectric layer172may be omitted and instead of the dielectric layer172, the second passivation layer113may serve as a dielectric layer172which insulates the first capacitor electrode171from the second capacitor electrode173and forms the capacitor170.

The second capacitor electrode173is disposed on the dielectric layer172so as to overlap the first capacitor electrode171. The second capacitor electrode173may be electrically connected to the common line CL. For example, the second capacitor electrode173may extend from the common line CL to the first capacitor electrode171. The second capacitor electrode173and the common line CL may be integrally formed.

In this case, the second capacitor electrode173extends to the second source region162of the second semiconductor element160to be electrically connected to the second source region162. Specifically, the second capacitor electrode173extends to the second source region162to be in contact with the second source pad electrode162P which is electrically connected to the second source region162. Therefore, the second capacitor electrode173which is integrally formed with the common line CL may be electrically connected to the second source region162of the second semiconductor element160through the second source pad electrode162P.

The first protective layer114is disposed on the second capacitor electrode173, the common line CL, and the data line DL. As described above, the first protective layer114is a layer for protecting the plurality of first LEDs120, the plurality of driving units DP, and the plurality of wiring lines of one surface of the first substrate110a. Further, the filling member117, the second protective layer116, and the second substrate110bare disposed on the first protective layer114.

In the meantime, even though inFIGS.3and5, it is illustrated that each of the plurality of driving units DP includes the first semiconductor element150, the second semiconductor element160, and the capacitor170, the number of the semiconductor elements and the capacitors of each of the plurality of driving units DP and the arrangement thereof are not limited thereto.

In the meantime, referring toFIG.3, in the second sub pixel SPX2and the third sub pixel SPX3, the plurality of connecting units180is disposed. The plurality of connecting units180is a configuration for electrically connecting the plurality of driving units DP and the plurality of wiring lines of one surface of the first substrate110ato the second LED130and the third LED140of one surface of the second substrate110b, which will be described in more detail with reference toFIGS.4and6.

Referring toFIGS.4and6, the second LED130, the third LED140, and a second connecting unit182of the plurality of connecting units180are disposed on one surface of the second substrate110b.

First, the second LED130is disposed in the second sub pixel SPX2on one surface of the second substrate110b. The second LED130includes a second n-type semiconductor layer131, a second light emitting layer132, a second p-type semiconductor layer133, a second n-type electrode131P, and a second p-type electrode133P.

The second n-type semiconductor layer131is disposed on one surface of the second substrate110band the second p-type semiconductor layer133is disposed on the second n-type semiconductor layer131. The second n-type semiconductor layer131and the second p-type semiconductor layer133may be formed by injecting n-type and p-type impurities into gallium nitride.

Further, the second light emitting layer132is disposed between the second n-type semiconductor layer131and the second p-type semiconductor layer133. The second light emitting layer132is supplied with holes and electrons from the second n-type semiconductor layer131and the second p-type semiconductor layer133to emit light. For example, the second light emitting layer132is supplied with holes and electrons from the second n-type semiconductor layer131and the second p-type semiconductor layer133to emit blue or green light.

A third passivation layer115is disposed so as to cover the second n-type semiconductor layer131, the second light emitting layer132, and the second p-type semiconductor layer133. The third passivation layer115is an insulating layer which protects components below the third passivation layer115and suppresses the electrical short circuit of the second n-type semiconductor layer131and the second p-type semiconductor layer133. For example, the third passivation layer115may be configured by a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

The second n-type electrode131P and the second p-type electrode133P are disposed on the third passivation layer115. The second n-type electrode131P may be electrically connected to the second n-type semiconductor layer131and the second p-type electrode133P may be electrically connected to the second p-type semiconductor layer133. Specifically, a contact hole which exposes a part of the upper surface of the second n-type semiconductor layer131is disposed on the third passivation layer115. The second n-type electrode131P may be in contact with the upper surface of the second n-type semiconductor layer131through the contact hole. A contact hole which exposes a part of the upper surface of the second p-type semiconductor layer133is disposed on the third passivation layer115. The second p-type electrode133P may be in contact with the upper surface of the second p-type semiconductor layer133through the contact hole. Therefore, the second n-type electrode131P and the second p-type electrode133P may be in contact with the second n-type semiconductor layer131and the second p-type semiconductor layer133through the contact hole of the third passivation layer115to be electrically connected thereto.

The third LED140is disposed in the third sub pixel SPX3on one surface of the second substrate110b. The third LED140includes a third n-type semiconductor layer141, a third light emitting layer142, a third p-type semiconductor layer143, a third n-type electrode141P, and a third p-type electrode143P.

The third n-type semiconductor layer141is disposed on one surface of the second substrate110band the third p-type semiconductor layer143is disposed on the third n-type semiconductor layer141. The third n-type semiconductor layer141and the third p-type semiconductor layer143may be formed by injecting n-type and p-type impurities into gallium nitride.

Further, the third light emitting layer142is disposed between the third n-type semiconductor layer141and the third p-type semiconductor layer143. The third light emitting layer142is supplied with holes and electrons from the third n-type semiconductor layer141and the third p-type semiconductor layer143to emit light. For example, the third light emitting layer142is supplied with holes and electrons from the third n-type semiconductor layer141and the third p-type semiconductor layer143to emit green or blue light.

Hereinafter, it is assumed that the second LED130including the second light emitting layer132is a blue LED and the third LED140including the third light emitting layer142is a green LED, but the second LED130may be a green LED and the third LED140may be a blue LED. However, the present disclosure is not limited thereto.

The third passivation layer115is disposed so as to cover the third n-type semiconductor layer141, the third light emitting layer142, and the third p-type semiconductor layer143. The third n-type electrode141P and the third p-type electrode143P are disposed on the third passivation layer115. The third n-type electrode141P may be electrically connected to the third n-type semiconductor layer141and the third p-type electrode143P may be electrically connected to the third p-type semiconductor layer143. Specifically, a contact hole which exposes a part of the upper surface of the third n-type semiconductor layer141is disposed on the third passivation layer115. The third n-type electrode141P may be in contact with the upper surface of the third n-type semiconductor layer141through the contact hole. A contact hole which exposes a part of the upper surface of the third p-type semiconductor layer143is disposed on the third passivation layer115. The third p-type electrode143P may be in contact with the upper surface of the third p-type semiconductor layer143through the contact hole. Therefore, the third n-type electrode141P and the third p-type electrode143P may be in contact with the third n-type semiconductor layer141and the third p-type semiconductor layer143through the contact hole of the third passivation layer115to be electrically connected thereto.

The second protective layer116is disposed on one surface of the second substrate110bso as to cover a plurality of second LEDs130and a plurality of third LEDs140. As described above, the second protective layer116is a layer for protecting the plurality of second LEDs130and the plurality of third LEDs140on one surface of the second substrate110b.

The plurality of connecting units180is disposed on the first protective layer114and the second protective layer116. The plurality of connecting units180includes a first connecting unit181and a second connecting unit182. The first connecting unit181is disposed on the first protective layer114to be connected to the plurality of driving units DP and the plurality of wiring lines of the first substrate110a. The second connecting unit182is disposed on the second protective layer116to be connected to the second LED130and the third LED140of the second substrate110b.

Referring toFIG.6, the first connecting unit181is electrically connected to the plurality of driving units DP and the plurality of wiring lines of one surface of the first substrate110a. Specifically, the contact hole which exposes the plurality of power lines PL, the second drain pad electrode163P of the driving unit DP disposed in the second sub pixel SPX2, and the second drain pad electrode163P of the driving unit DP disposed in the third sub pixel SPX3may be disposed on the first protective layer114of one surface of the first substrate110a. The first connecting unit181may be in contact with the plurality of power lines PL and the top surfaces of the second drain pad electrodes163P of the second sub pixel SPX2and the third sub pixel SPX3through the contact hole. Therefore, the first connecting unit181disposed on the top surface of the first protective layer114may be electrically connected to the plurality of power lines PL and the second drain pad electrodes163P of the second sub pixel SPX2and the third sub pixel SPX3through the contact hole of the first protective layer114.

Referring toFIGS.4and6, the second connecting unit182is electrically connected to the second LED130and the third LED140of one surface of the second substrate110b. Specifically, the contact hole which exposes the second n-type electrode131P and the second p-type electrode133P of the second LED130may be disposed on the second protective layer116which covers the second LED130of one surface of the second substrate110b. The contact hole which exposes the third n-type electrode141P and the third p-type electrode143P of the third LED140may be disposed on the second protective layer116which covers the third LED140of one surface of the second substrate110b. The second connecting unit182may be in contact with the upper surfaces of the second n-type electrode131P and the second p-type electrode133P of the second LED130and the third n-type electrode141P and the third p-type electrode143P of the third LED140. Therefore, the second connecting unit182disposed on the upper surface of the second protective layer116may be electrically connected to the second LED130and the third LED140through the contact hole of the second protective layer116.

Referring toFIG.6, the first connecting unit181of the first substrate110aand the second connecting unit182of the second substrate110bmay be electrically connected to each other. Specifically, one surface of the first substrate110aand one surface of the second substrate110bare disposed to be opposite to each other. The first connecting unit181disposed on one surface of the first substrate110aand the second connecting unit182disposed on one surface of the second substrate110bmay be in contact with each other. In this case, the first connecting unit181and the second connecting unit182may be bonded to each other by means of a conductive ball or a Eutectic bonding method to be fixed.

For example, when the conductive ball is used, the conductive ball is not disposed between the first protective layer114and the second protective layer116, but the conductive ball is disposed only between the first connecting unit181and the second connecting unit182to electrically connect the first connecting unit181and the second connecting unit182to each other. In this case, when the conductive ball is disposed in an area between the first protective layer114and the second protective layer116which does not overlap the first connecting unit181and the second connecting unit182, the light emission from the first LED120of the first substrate110amay be interrupted. Therefore, the conductive ball may be selectively disposed only between the first connecting unit181and the second connecting unit182.

For example, when the Eutectic bonding method is used, the first connecting unit181and the second connecting unit182are subjected to the hot pressure welding process at a high temperature without applying a separate adhesive material to bond the first connecting unit181and the second connecting unit182to each other. In this case, the first connecting unit181and the second connecting unit182may be formed of Eutectic metal for the Eutectic bonding and for example, may be formed of tin (Sn), indium (In), Zinc (Zn), lead (Pb), nickel (Ni), gold (Au), platinum (Pt), and copper (Cu), but is not limited thereto.

A first connecting unit181which is connected to the power line PL among the first connecting units181may be in contact with a second connecting unit182which is connected to the second p-type electrode133P of the second LED130and the third p-type electrode143P of the third electrode140among the second connecting units182. Therefore, the power line PL may be electrically connected to the second p-type electrode133P and the second p-type semiconductor layer133of the second LED130through the first connecting unit181and the second connecting unit182. The power line PL may be electrically connected to the third p-type electrode143P and the third p-type semiconductor layer143of the third LED140through the first connecting unit181and the second connecting unit182.

A first connecting unit181which is connected to the second drain pad electrodes163P of the second sub pixel SPX2and the third sub pixel SPX3among the first connecting units181may be in contact with a second connecting unit182which is connected to the second n-type electrode131P and the third n-type electrode141P of the second sub pixels SPX2and the third sub pixels SPX3among the second connecting units182. Therefore, the second semiconductor element160of the second sub pixel SPX2may be electrically connected to the second n-type electrode131P and the second n-type semiconductor layer131of the second LED130through the first connecting unit181and the second connecting unit182. The second semiconductor element160of the third sub pixel SPX3may be electrically connected to the third n-type electrode141P and the third n-type semiconductor layer141of the third LED140through the first connecting unit181and the second connecting unit182. Therefore, the second LED130and the third LED140of the second substrate110bmay be electrically connected to the power line PL of the first substrate110aand the second semiconductor element160of the plurality of driving units DP to emit light.

The reflective layer190is disposed between the first protective layer114and the second protective layer116. Specifically, the reflective layer190may be disposed so as to overlap only the sub pixels SPX2, and SPX3in which the LEDs130, and140are disposed on one surface of the second substrate110b, among the plurality of sub pixels SPX1, SPX2, and SPX3. For example, when the second LED130and the third LED140are disposed in the second sub pixel SPX2and the third sub pixel SPX3of one surface of the second substrate110b, respectively, the reflective layer190may be disposed so as to overlap only the second sub pixels SPX2and the third sub pixel SPX3. The reflective layer190disposed in the second sub pixels SPX2and the third sub pixel SPX3may overlap the second LED130and the third LED140of the second substrate110b.

In contrast, when the reflective layer190is disposed so as to overlap only the first sub pixel SPX1in which the first LED120is disposed on one surface of the first substrate110aamong the plurality of sub pixels SPX1, SPX2, and SPX3, the reflective layer190may interrupt the light emitted from the first LED120of one surface of the first substrate110afrom being discharged through the second substrate110b. Therefore, the reflective layer190may be disposed so as not to overlap the first LED120disposed on one surface of the first substrate110a, but to overlap only the second LED130and the third LED140disposed on one surface of the second substrate110b.

In the meantime, the light emitted from the plurality of LEDs120,130, and140may be discharged through the second substrate110b. Therefore, the second substrate110bmay be formed of a transparent substrate. Further, the reflective layer190which is disposed on the first protective layer114so as to overlap the second LED130and the third LED140reflects light which is directed to the first substrate110aamong light emitted from the second LED130and the third LED140toward the second substrate110b, thereby increasing the optical efficiency. Therefore, the reflective layer190is disposed on the first protective layer114to reflect again the light emitted below the second LED130and the third LED140on the first protective layer114to one surface of the second substrate110b, that is, an opposite surface of one surface of the second substrate110b, thereby improving the optical efficiency. The reflective layer190may be formed of a non-conductive material having a high reflectance, and for example, the reflective layer190may be a distributed Bragg reflector or titanium oxide TiO2, but is not limited thereto.

In the meantime, even though not illustrated in the drawing, a black matrix may be further disposed along boundaries of the first sub pixels SPX1, the second sub pixel SPX2, and the third sub pixels SPX3, on the second substrate110b. For example, in the second protective layer116of the second substrate110b, the black matrix is further disposed at the boundaries of the first sub pixels SPX1, the second sub pixel SPX2, and the third sub pixels SPX3, on the second substrate110bto reduce the color mixture of the light emitted from the plurality of LEDs120,130, and140.

The display device100according to one exemplary embodiment of the present disclosure may implement the display device100by bonding the first substrate110aon which the plurality of first LEDs120is grown and the second substrate110bon which the plurality of second LEDs130and the plurality of third LEDs140are grown. The first LED120is disposed on one surface of the first substrate110aand the second LED130and the third LED140are disposed on one surface of the second substrate110b. Further, the plurality of driving units DP which drives the first LED120, the second LED130, and the third LED140is disposed on one surface of the first substrate110a. The plurality of second LEDs130and the plurality of third LEDs140are disposed on one surface of the second substrate110b. Further, one surface of the first substrate110ais disposed so as to be opposite to one surface of the second substrate110bto electrically connect some driving units DP of the plurality of driving units DP and some power lines PL among the plurality of power lines PL of one surface of the first substrate110ato the second LED130and the third LED140of one surface of the second substrate110b. Therefore, the plurality of LEDs120,130, and140disposed on different substrates is electrically connected to the plurality of driving units DP, and the plurality of wiring lines to implement one display device100. Therefore, the plurality of LEDs120,130, and140disposed on different substrates is not transferred onto different substrates, but the first substrate110aand the second substrate110bare disposed so as to be opposite to each other so that the plurality of LEDs120,130, and140may be connected to the plurality of driving units DP and the plurality of wiring lines in a non-transfer manner.

Hereinafter, a display device100and a manufacturing method of a display device100according to an exemplary embodiment of the present disclosure will be described in detail with reference toFIGS.7A to7O.

FIGS.7A to7Oare schematic views of processes for explaining a display device and a manufacturing method of a display device according to an exemplary embodiment of the present disclosure.FIGS.7A to7Eare schematic cross-sectional views for explaining a process of forming a first LED120, a plurality of driving units DP, and a plurality of wiring lines in a first sub pixel SPX1of one surface of a first substrate110a.FIGS.7F to7Hare schematic cross-sectional views for explaining a process of forming a first connecting unit181in a second sub pixel SPX2of one surface of the first substrate110a.FIGS.7I to7Mare schematic cross-sectional views for explaining a process of forming a second LED130and a third LED140on one surface of a second substrate110b.FIGS.7N and7Oare schematic cross-sectional views for explaining a bonding process of a first substrate110aand a second substrate110b.

A process of forming a first LED120, a plurality of driving units DP, and a plurality of wiring lines in a first sub pixel SPX1of one surface of a first substrate110awill be described with reference toFIGS.7A to7E.

Referring toFIG.7A, a first epitaxial layer120mis formed on one entire surface of the first substrate110a.

The first epitaxial layer120mis used to form the plurality of first LEDs120of the first substrate110a. The first epitaxial layer120mhas a structure in which materials which form a first n-type semiconductor layer121, a first light emitting layer122, and a first p-type semiconductor layer123of the plurality of first LEDs120are sequentially laminated. For example, the first epitaxial layer120mmay be formed of a first n-type semiconductor material layer121m, the first light emitting material layer122m, and a first p-type semiconductor material layer123m.

In this case, a first n-type semiconductor material layer121m, a first light emitting material layer122m, and a first p-type semiconductor material layer123mof the first epitaxial layer120mmay be grown on one surface of the first substrate110aby a metal organic chemical vapor deposition (MOCVD) method or a sputtering method, but the growth method of the first epitaxial layer120mis not limited thereto.

In the meantime, the first LED120is a red LED which emits red light, as described above. The first light emitting material layer122mwhich is a material forming the first light emitting layer122of the first LED120is configured to emit red light. In this case, the growth efficiency of the first epitaxial layer120mincluding the first light emitting material layer122mmay vary depending on the type of the first substrate110a.

For example, when the first substrate110ais a sapphire substrate, it may be difficult to grow the first epitaxial layer120mincluding the first light emitting material layer122mwhich is configured to emit red light on the first substrate110a. In contrast, when the first substrate110ais a gallium arsenide substrate or a gallium phosphide substrate, the first epitaxial layer120mincluding the first light emitting material layer122mwhich is configured to emit red light may be efficiently grown on the first substrate110a. Therefore, since the first LED120is a red LED which emits red light, the first substrate110amay be formed of a gallium arsenide substrate or a gallium phosphide substrate which may efficiently grow the red LED, but is not limited thereto.

In this case, the light emitted from the plurality of LEDs120,130, and140may be discharged not to the first substrate110a, but to the second substrate110b. Therefore, the first substrate110amay be formed of an opaque substrate so as not to emit light from the plurality of LEDs120,130, and140through the first substrate110a.

Referring toFIG.7B, the first epitaxial layer120mis etched to form a first n-type semiconductor layer121, a first light emitting layer122, and a first p-type semiconductor layer123of the first LED120, a first gate electrode151of the first semiconductor element150, and a second gate electrode161of the second semiconductor element160may be formed.

First, the first p-type semiconductor material layer123mwhich is an uppermost end of the first epitaxial layer120mmay be etched. For example, the first p-type semiconductor material layer123mis left only in an area overlapping the first p-type semiconductor layer123of the first LED120and the first p-type semiconductor material layer123mmay be etched in the remaining area. Therefore, the first p-type semiconductor layer123which is formed of the first p-type semiconductor material layer123mmay be formed.

Next, after etching the first p-type semiconductor material layer123m, the first light emitting material layer122mmay be etched. For example, the first light emitting material layer122mis left only in an area overlapping the first p-type semiconductor layer123and the first light emitting material layer122mmay be etched in the remaining area. Therefore, the first light emitting layer122which is formed of the first light emitting material layer122mmay be formed.

Next, after etching the first p-type semiconductor material layer123mand the first light emitting material layer122m, a part of the first n-type semiconductor material layer121mwhich is exposed from the first p-type semiconductor layer123and the first light emitting layer122may be selectively etched. For example, the first n-type semiconductor material layer121mmay be etched leaving only the first n-type semiconductor material layer121moverlapping the first p-type semiconductor layer123and the first light emitting layer122and a partial first n-type semiconductor material layer121mwhich outwardly protrudes from the first p-type semiconductor layer123and the first light emitting layer122. Therefore, the first n-type semiconductor layer121which partially outwardly protrudes from the first p-type semiconductor layer123and the first light emitting layer122may be formed.

Next, a gate insulating material layer111mand a gate electrode material layer Gm are sequentially formed to cover the first n-type semiconductor layer121, the first light emitting layer122, and the first p-type semiconductor layer123.

The gate insulating material layer111mis a material which forms the gate insulating layer111and may be configured by a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

The gate electrode material layer Gm is a material which forms the first gate electrode151of the first semiconductor element150and the second gate electrode161of the second semiconductor element160of each of the plurality of driving units DP. For example, the gate electrode material layer Gm may be formed of a conductive material such as polysilicon and molybdenum (Mo), but is not limited thereto.

Referring toFIG.7C, the gate electrode material layer Gm and the gate insulating material layer111mare etched to form the first gate electrode151, the second gate electrode161, and the gate insulating layer111and forms the first source region152and the first drain region153and the second source region162and the second drain region163.

First, the gate electrode material layer Gm is etched to form the first gate electrode151and the second gate electrode161.

Next, the gate insulating material layer111mis etched in an area excluding an area overlapping the first gate electrode151and the second gate electrode161to form the gate insulating layer111. The gate insulating material layer111mis left only below the first gate electrode151and the second gate electrode161and the gate insulating material layer111mis etched in the remaining area to form the gate insulating layer111.

Next, the first source region152, the first drain region153, the second source region162, and the second drain region163may be formed. Specifically, a photoresist may be formed excluding an area overlapping the first source region152, the first drain region153, the second source region162, and the second drain region163. n-type or p-type impurities may be injected into the area exposed from the photoresist. Finally, after injecting the n-type or p-type impurities, an annealing process may be performed for electrical activation. Therefore, the photoresist is formed to inject the n-type or p-type impurities into the first source region152, the first drain region153, the second source region162, and the second drain region163.

Therefore, the formation of the first semiconductor element150which is formed of the first gate electrode151, the first source region152, and the first drain region153and the second semiconductor element160which is formed of the second gate electrode161, the second source region162, and the second drain region163may be completed.

In the meantime, depending on the type of the first substrate110a, the first source region152and the first drain region153of the first semiconductor element150and the second source region162and the second drain region163of the second semiconductor element160may be directly formed on the first substrate110a, but may be formed on the first n-type semiconductor material layer121mof the first LED120.

For example, when the first substrate110ais a gallium arsenic substrate, the n-type or p-type impurity may not be appropriately injected into the gallium arsenic substrate so that defect of the first source region152, the first drain region153, the second source region162, and the second drain region163may be caused. Therefore, the reliability of the first semiconductor element150and the second semiconductor element160which are formed by injecting the n-type or p-type impurities in the gallium arsenic substrate may be low. Therefore, when the first n-type semiconductor material layer121mis etched, the first n-type semiconductor material layer121mmay be left in an area where the first semiconductor element150and the second semiconductor element160are to be formed. Further, the p-type impurity is injected into the first n-type semiconductor material layer121mto form the first source region152, the first drain region153, the second source region162, and the second drain region163having a low degree of defectiveness. However, the design and the type of the first semiconductor element150and the second semiconductor element160may vary depending on the type of the first substrate110a, but is not limited thereto.

Referring toFIG.7D, the first passivation layer112is formed on the first semiconductor element150, the second semiconductor element160, and the first n-type semiconductor layer121, the first light emitting layer122, and the first p-type semiconductor layer123of the first LED120.

A first passivation material layer may be formed to cover the first semiconductor element150, the second semiconductor element160, and the first LED120.

Next, the first passivation material layer which is formed to cover the first semiconductor element150, the second semiconductor element160, and the first LED120is etched to form a contact hole. For example, a contact hole which exposes the first gate electrode151, the first source region152, and the first drain region153of the first semiconductor element150, a contact hole which exposes the second gate electrode161, the second source region162, and the second drain region163of the second semiconductor element160, and a contact hole which exposes the first n-type semiconductor layer121and the first p-type semiconductor layer123of the first LED120may be formed. Therefore, the formation of the first passivation layer112may be completed by forming contact holes which partially expose the first semiconductor element150, the second semiconductor element160, and the first LED120on the first passivation material layer.

Next, a gate line GL, a power line PL, a first gate pad electrode151P, a first source pad electrode152P, a first drain pad electrode153P, a second gate pad electrode161P, a second source pad electrode162P, a second drain pad electrode163P, a first n-type electrode121P, and a first p-type electrode123P are formed on the first passivation layer112.

Specifically, a conductive material layer may be formed on the first passivation layer112.

Next, a plurality of gate lines GL, a plurality of power lines PL, the first gate pad electrode151P, the first source pad electrode152P, the first drain pad electrode153P, the second gate pad electrode161P, the second source pad electrode162P, the second drain pad electrode163P, the first n-type electrode121P, and the first p-type electrode123P are formed by etching the conductive material layer.

For example, the conductive material layer is etched excluding a conductive material layer which is disposed to fill the contact hole of the first passivation layer112which exposes the first gate electrode151, the first source region152, and the first drain region153of the first semiconductor element150and the second gate electrode161, the second source region162, and the second drain region163of the second semiconductor element160of each of the plurality of driving units DP. By doing this, the first gate pad electrode151P, the first source pad electrode152P, the first drain pad electrode153P, the second gate pad electrode161P, the second source pad electrode162P, and the second drain pad electrode163P may be formed.

The conductive material layer is etched to form a first capacitor electrode171which is integrally formed with the first drain pad electrode153P and the second gate pad electrode161P.

When the second drain pad electrode163P is formed, the first n-type electrode121P which is integrally formed with the second drain pad electrode163P and is in contact with the first n-type semiconductor layer121of the first LED120may also be formed.

Concurrently, the conductive material layer is etched to form the gate line GL which is integrally formed with the first gate pad electrode151P and horizontally extends.

The first n-type electrode121P and the first p-type electrode123P may be formed on the first passivation layer112which partially exposes the first n-type semiconductor layer121and the first p-type semiconductor layer123of the first LED120. Therefore, the formation of the first LED120which includes the first n-type semiconductor layer121, the first light emitting layer122, the first p-type semiconductor layer123, the first n-type electrode121P, and the first p-type electrode123P may be completed.

In this case, when the first p-type electrode123P is formed, the power line PL which is integrally formed with the first p-type electrode123P and horizontally extends may also be formed.

Therefore, after forming the first passivation layer112on the first semiconductor element150, the second semiconductor element160, and the first n-type semiconductor layer121, the first light emitting layer122, and the first p-type semiconductor layer123of the first LED120, a plurality of contact holes is formed to form the first passivation layer112.

Further, after forming the conductive material layer to fill the plurality of contact holes of the first passivation layer112on the first passivation layer112, the conductive material layer is etched to form the gate line GL, the power line PL, the first gate pad electrode151P, the first source pad electrode152P, the first drain pad electrode153P, the second gate pad electrode161P, the second source pad electrode162P, the second drain pad electrode163P, the first n-type electrode121P, and the first p-type electrode123P.

Referring toFIG.7E, a second passivation material layer may be formed so as to cover a plurality of gate lines GL, a plurality of power lines PL, the first gate pad electrode151P, the first source pad electrode152P, the first drain pad electrode153P, the second gate pad electrode161P, the second source pad electrode162P, the second drain pad electrode163P, the first n-type electrode121P, and the first p-type electrode123P.

Next, the second passivation material layer is etched to form a contact hole. For example, in order to form a contact hole for connecting the second source pad electrode162P to a second capacitor electrode173which will be formed later, the second passivation material layer which covers the upper surface of the second source pad electrode162P may be partially etched.

Further, in order to form a dielectric layer172of the capacitor, the second passivation material layer which covers the first capacitor electrode171may be partially etched.

In order to form a contact hole for connecting the first source pad electrode152P and the data line DL, the second passivation material layer which covers the upper surface of the first source pad electrode152P may be partially etched.

Therefore, in an area overlapping the first capacitor electrode171, the second source pad electrode162P, and the first source pad electrode152P, the second passivation material layer is etched to complete the formation of the second passivation layer113.

Next, the common line CL, the data line DL, the dielectric layer172, and the second capacitor electrode173are formed on the second passivation layer113and the first protective layer114is formed.

The dielectric layer172may be formed so as to cover the upper surface of the first capacitor electrode171which is exposed from the second passivation layer113.

Next, a conductive material layer may be formed on the dielectric layer172and the second passivation layer113.

Next, the conductive material layer is etched excluding the area overlapping the dielectric layer172and the second source pad electrode162P to form the second capacitor electrode173. Therefore, the formation of the capacitor170which is formed of the first capacitor electrode171, the dielectric layer172, and the second capacitor electrode173may be completed.

Concurrently, the conductive material layer is etched to form a common line CL which is integrally formed with the second capacitor electrode173.

Further, the conductive material layer is etched to form the data line DL which is in contact with the first source pad electrode152P exposed from the second passivation layer113.

Next, the first protective layer114may be formed on the capacitor170, the common line CL, and the data line DL. The first protective layer114may be formed so as to cover the plurality of driving units DP, the plurality of wiring lines, and the plurality of first LEDs120of one surface of the first substrate110a.

Hereinafter, a process of forming a first connecting unit181in a second sub pixel SPX2of one surface of the first substrate110awill be described with reference toFIGS.7F to7H. The process of forming the first connecting unit181in the second sub pixel SPX2and the third sub pixel SPX3is the same so that hereinafter, for the convenience of description, only the process of forming the first connecting unit181in the second sub pixels SPX2is illustrated.

Referring toFIG.7F, the processes for forming the first semiconductor element150, the second semiconductor element160, and the first passivation layer112in each of the second sub pixel SPX2and the third sub pixels SPX3on one surface of the first substrate110aare the same as the process of forming the driving unit DP of the first sub pixel SPX1.

After completing the formation of the first passivation layer112, the gate line GL, the power line PL, the first gate pad electrode151P, the first source pad electrode152P, the first drain pad electrode153P, the second gate pad electrode161P, the second source pad electrode162P, and the second drain pad electrode163P are formed on the first passivation layer112.

Specifically, a conductive material layer may be formed on the first passivation layer112.

Next, the conductive material layer is etched to form a plurality of gate lines GL, a plurality of power lines PL, the first gate pad electrode151P, the first source pad electrode152P, the first drain pad electrode153P, the second gate pad electrode161P, the second source pad electrode162P, and the second drain pad electrode163P.

In this case, the plurality of LEDs120,130, and140is not formed in the second sub pixels SPX2and the third sub pixels SPX3on one surface of the first substrate110a, so that the n-type electrode and the p-type electrode are not formed and the first n-type electrode121P and the first p-type electrode123P are formed only in the first sub pixel SPX1in which the first LED120is disposed.

Next, referring toFIG.7G, the second passivation layer113is formed on the plurality of gate lines GL, the plurality of power lines PL, the first gate pad electrode151P, the first source pad electrode152P, the first drain pad electrode153P, the second gate pad electrode161P, the second source pad electrode162P, and the second drain pad electrode163P.

In this case, the second passivation layer113may be formed to have a contact hole which exposes the first drain pad electrode153P and the first source pad electrode152P.

Next, the common line CL, the data line DL, the dielectric layer172, and the second capacitor electrode173are formed on the second passivation layer113and the first protective layer114is formed.

Next, referring toFIG.7H, the first connecting unit181is formed on the first protective layer114.

First, the first protective layer114and the second passivation layer113are etched to form a contact hole which exposes the second drain pad electrode163P and the power line PL.

Next, a conductive material layer may be formed on the first protective layer114to fill the contact hole of the first protective layer114. The conductive material layer is etched to form the first connecting unit181connected to the second drain pad electrode163P and the first connecting unit181connected to the power line PL.

Finally, the reflective layer190is formed on the first protective layer114. Specifically, the reflective layer190may be formed so as to overlap the second sub pixel SPX2and the third sub pixel SPX3. The reflective layer190may be formed to overlap the second LED130and the third LED140formed on the second substrate110bwhich is bonded such that one surface is opposite to one surface of the first substrate110a.

Hereinafter, a process of forming a second LED130and a third LED140on one surface of a second substrate110bwill be described with reference toFIGS.7I to7M.

Referring toFIG.7I, a second epitaxial layer130mis formed on one entire surface of the second substrate110b.

The second epitaxial layer130mis used to form the plurality of second LEDs130of the second substrate110b. The second epitaxial layer130mhas a structure in which materials which form a second n-type semiconductor layer131, a second light emitting layer132, and a second p-type semiconductor layer133of the plurality of second LEDs130are sequentially laminated. For example, the second epitaxial layer130mmay be formed of the second n-type semiconductor material layer131m, the second light emitting material layer132m, and the second p-type semiconductor material layer133m.

In the meantime, the second LED130is a blue LED which emits blue light, as described above. The second light emitting material layer132mwhich is a material forming the second light emitting layer132of the second LED130is configured to emit blue light. In this case, the growth efficiency of the second epitaxial layer130mincluding the second light emitting material layer132mmay vary depending on the type of the second substrate110b, similarly to the first epitaxial layer120m.

For example, when the second substrate110bis a gallium arsenic substrate, it may be difficult to grow the second epitaxial layer130mincluding the second light emitting material layer132mwhich is configured to emit blue light on the second substrate110b. In contrast, when the second substrate110bis a sapphire substrate, the second epitaxial layer130mincluding the second light emitting material layer132mwhich is configured to emit blue light may be efficiently grown on the first substrate110a.

In the meantime, the light emitted from the plurality of LEDs120,130, and140including the second LED130is discharged toward the second substrate110b. That is, the second substrate110bmay be formed of a transparent substrate and efficiently grow the blue LED. For example, the second substrate110bmay efficiently grow the blue LED and may be formed of a transparent sapphire substrate or a gallium nitride substrate, but is not limited thereto.

Referring toFIG.7J, in the second sub pixel SPX2, the second epitaxial layer130mis etched to form a part of the second LEDs130and in the third sub pixels SPX3, the second epitaxial layer130mis etched leaving only a lower portion131m′ of the second n-type semiconductor material131m.

First, the second p-type semiconductor material layer133mand the second light emitting material layer132mof the second epitaxial layer130mare partially etched in the second sub pixel SPX2to form the second p-type semiconductor layer133and the second light emitting layer132of the second LED130.

Next, only an upper portion of the second n-type semiconductor material layer131mwhich is exposed from the second p-type semiconductor layer133and the second light emitting layer132is etched. The lower portion131m′ of the second n-type semiconductor material layer131mmay be left so as to cover the entire one surface of the second substrate110b.

In the third sub pixel SPX3, the entire second p-type semiconductor material layer133m, the entire second light emitting material layer132m, and only an upper portion of the second n-type semiconductor material layer131mof the second epitaxial layer130mare etched. In the third sub pixel SPX3, only the lower portion131m′ of the second n-type semiconductor material layer131mmay be left.

Next, referring toFIG.7K, a third epitaxial layer140mis formed only in an area overlapping the third sub pixel SPX3excluding the second sub pixel SPX2.

The third epitaxial layer140mis used to form the plurality of third LEDs140of the second substrate110b. The third epitaxial layer140mhas a structure in which materials which form a third n-type semiconductor layer141, a third light emitting layer142, and a third p-type semiconductor layer143of the plurality of third LEDs140are sequentially laminated. For example, the third epitaxial layer140mmay be formed of the third n-type semiconductor material layer141m, the third light emitting material layer142m, and the third p-type semiconductor material layer143m.

The third epitaxial layer140mof the third sub pixels SPX3may be formed to cover the lower portion131m′ of the second n-type semiconductor material layer131m. In this case, the second n-type semiconductor material layer131mand the third n-type semiconductor material layer141mmay be formed of the same material. Therefore, since the second n-type semiconductor material layer131mperforms the same function as the third n-type semiconductor material layer141m, the third light emitting material layer142mmay be directly formed on the second n-type semiconductor material layer131m. However, when the second epitaxial layer130mis etched, the upper surface of the lower portion131m′ of the second n-type semiconductor material layer131mmay be partially damaged due to the influence of the etching. Therefore, when the third light emitting material layer142mis directly formed on the lower portion131m′ of the second n-type semiconductor material layer131m, the reliability of the third LED140may be low. Therefore, after growing the third n-type semiconductor material layer141mon the lower portion131m′ of the second n-type semiconductor material layer131m, the third light emitting material layer142mand the third p-type semiconductor material layer143mmay be grown.

In the meantime, when the third epitaxial layer140mis formed in the third sub pixels SPX3, in order to protect the second p-type semiconductor layer133, the second light emitting layer132, and the second n-type semiconductor layer131of the second LED130formed in the second sub pixel SPX2, after forming a protective layer which covers the second sub pixels SPX2, the third epitaxial layer140mmay be formed.

After forming the protective layer on the second p-type semiconductor layer133in the second sub pixels SPX2, the third epitaxial layer140mmay be grown on the entire one surface of the second substrate110b. In this case, a part of the third epitaxial layer140mformed in the second sub pixel SPX2may be removed together by removing the protective layer. For example, the protective layer may be formed of silicon oxide SiO2 and the protective layer may be etched using the buffered oxide etchant (BOE) in a state when the third epitaxial layer140mis formed on the protective layer. Therefore, as the protective layer is etched, a part of the third epitaxial layer140mwhich covers the second LED130may be removed from the second sub pixel SPX2.

In the meantime, the third LED140is a green LED which emits green light, as described above. The third light emitting material layer142mwhich is a material forming the third light emitting layer142of the third LED140is configured to emit green light. In this case, the growth efficiency of the third epitaxial layer140mincluding the third light emitting material layer142mmay vary depending on the type of the second substrate110b.

However, in the second substrate110b, both the second epitaxial layer130mfor forming the second LED130and the third epitaxial layer140mfor forming the third LED140are grown, so that the second substrate110bmay be a substrate having a high growth efficiency of both the second epitaxial layer130mand the third epitaxial layer140m. For example, the second substrate110bmay efficiently grow the blue LED and the green LED and may be formed of a transparent substrate. Therefore, the second LED130and the third LED140are formed on one surface of the second substrate110b.

Next, referring toFIG.7I, the third epitaxial layer140mand a lower portion131m′ of the second n-type semiconductor material layer131mare etched to form the second n-type semiconductor layer131, the second light emitting layer132, and the second p-type semiconductor layer133of the second LED130and the third n-type semiconductor layer141, the third light emitting layer142, and the third p-type semiconductor layer143of the third LED140and also form the third passivation layer115.

First, in the third sub pixel SPX3, the third p-type semiconductor material layer143m, the third light emitting material layer142m, the third n-type semiconductor material layer141m, and a lower portion131m′ of the second n-type semiconductor material layer131mof the third epitaxial layer140mare sequentially etched to form the third p-type semiconductor layer143, the third light emitting layer142, and the third n-type semiconductor layer141of the third LED140.

In this case, the third n-type semiconductor layer141of the third LED140is formed of the lower portion131m′ of the second n-type semiconductor material layer131mand the third n-type semiconductor material layer141m. Specifically, the third epitaxial layer140mfor forming the third LED140is grown on the lower portion131m′ of the second n-type semiconductor material layer131m. Further, the third epitaxial layer140mand the lower portion131m′ of the second n-type semiconductor material layer131mare etched together to form the third p-type semiconductor layer143, the third light emitting layer142, and the third n-type semiconductor layer141of the third LED140. Therefore, the third n-type semiconductor layer141of the third LED140is defined to be formed of the third n-type semiconductor material layer141mand the lower portion131m′ of the second n-type semiconductor material layer131m.

Concurrently, the lower portion131m′ of the second n-type semiconductor material layer131mis etched from the second sub pixels SPX2to form the second n-type semiconductor layer131of the second LED130.

Next, the third passivation layer115is formed so as to cover the second p-type semiconductor layer133, the second light emitting layer132, and the second n-type semiconductor layer131of the second LED130and the third p-type semiconductor layer143, the third light emitting layer142, and the third n-type semiconductor layer141of the third LED140. In this case, the third passivation layer115is formed so as to have a contact hole which exposes upper portions of the second p-type semiconductor layer133and the second n-type semiconductor layer131of the second LED130and the third p-type semiconductor layer143and the third n-type semiconductor layer141of the third LED140.

Next, the conductive material layer is applied on the third passivation layer115. The conductive material layer is etched in an area excluding an area overlapping the contact hole of the third passivation layer115to form a second n-type electrode131P and a second p-type electrode133P of the second LED130and a third n-type electrode141P and the third p-type electrode143P of the third LED140.

Therefore, the formation of the second LED130which is formed of the second n-type semiconductor layer131, the second light emitting layer132, the second p-type semiconductor layer133, the second n-type electrode131P, and the second p-type electrode133P may be completed. Therefore, the formation of the third LED140which is formed of the third n-type semiconductor layer141, the third light emitting layer142, the third p-type semiconductor layer143, the third n-type electrode141P, and the third p-type electrode143P may be completed.

Next, the second protective layer116may be formed so as to cover the second LED130and the third LED140.

Referring toFIG.7M, the second connecting unit182is formed on the second protective layer116.

Specifically, the second protective layer116is etched to form a contact hole which exposes the second n-type electrode131P and the second p-type electrode133P of the second LED130. The second protective layer116is etched to form a contact hole which exposes the third n-type electrode141P and the third p-type electrode143P of the third LED140.

Next, a conductive material layer may be formed on the second protective layer116to fill the contact hole of the second protective layer116. The conductive material layer is etched to form the second connecting unit182which is connected to the second n-type electrode131P, the second p-type electrode133P, the third n-type electrode141P, and the third p-type electrode143P.

Hereinafter, a bonding process of a first substrate110aand a second substrate110bwill be described with reference toFIGS.7N and7O.

The first substrate110aand the second substrate110bare bonded such that one surface of the first substrate110aon which the formation of the first LED120, the plurality of driving units DP, and the plurality of wiring lines is completed and one surface of the second substrate110bon which the formation of the second LED130and the third LED140is completed are opposite to each other. Further, the filling member is filled in the space between the first substrate110aand the second substrate110b.

First, referring toFIG.7N,FIG.7Nis a cross-sectional view of the first sub pixel SPX1after bonding the first substrate110aand the second substrate110b.

Referring toFIG.7N, after bonding the first substrate110aand the second substrate110b, the filling member117is charged between the first substrate110aand the second substrate110b.

The filling member117may be charged to fill the space between the first substrate110aand the second substrate110b. The filling member117may be formed of a transparent material so that the light emitted from the first LED120of one surface of the first substrate110ais discharged to the second substrate110b.

In this case, since only the third passivation layer115and the second protective layer116are disposed on one surface of the second substrate110bin the first sub pixel SPX1, the light emitted from the first LED120of one surface of the first substrate110amay be discharged through the second substrate110b.

Referring toFIG.7O,FIG.7Ois a cross-sectional view of the second sub pixel SPX2after bonding the first substrate110aand the second substrate110b.

Referring toFIG.7O, in the second sub pixel SPX2, in order to electrically connect the driving unit DP and the plurality of wiring lines of one surface of the first substrate110aand the second LED130of one surface of the second substrate110b, the first connecting unit181and the second connecting unit182are bonded at the time of bonding the first substrate110aand the second substrate110b.

Specifically, the conductive ball may be formed so as to be in contact with the first connecting unit181of the first substrate110aor the second connecting unit182of the second substrate110b.

Next, the first substrate110aand the second substrate110bmay be aligned so that the first connecting unit181of the first substrate110aand the second connecting unit182of the second substrate110bmay overlap each other.

As the first connecting unit181of the first substrate110aand the second connecting unit182of the second substrate110bare electrically connected to each other using a conductive ball, the first substrate110aand the second substrate110bmay be bonded. In this case, as described above, the first connecting unit181of the first substrate110aand the second connecting unit182of the second substrate110bmay be bonded to each other by the Eutectic bonding method.

Finally, the filling member117may be charged between the first substrate110aand the second substrate110b. The filling member117may be formed to fill the space between the first substrate110aand the second substrate110b.

In the related art, since the growth efficiency of the plurality of LEDs which emits different colored light varies depending on the type of the substrate, it is difficult to grow the plurality of LEDs which emits different colored light on one substrate. For example, the red LED has high growth efficiency in the gallium arsenic substrate or the gallium phosphide substrate and the green LED and the blue LED have high growth efficiency in the sapphire substrate or gallium nitride substrate. Therefore, the green LED and the blue LED may be grown on the same substrate, but the red LED should be grown on a separate substrate. Therefore, in order to implement the display device using the substrate on which the plurality of LEDs is grown, the green LED and the blue LED are transferred onto the substrate on which the red LED is grown or the red LED is transferred onto the substrate on which the green LED and the blue LED are grown. Alternatively, the red LED, the green LED, and the blue LED should be individually transferred onto a backplane substrate on which the driving unit is formed. However, in order to transfer the plurality of LEDs, a process time is increased and an alignment problem of the plurality of LEDs and the semiconductor elements is caused.

Therefore, in the display device100according to an exemplary embodiment of the present disclosure and the method of manufacturing the display device100, after growing the plurality of LEDs120,130, and140on the first substrate110aand the second substrate110b, individually, the first substrate110aand the second substrate110bare bonded to manufacture the display device100. Therefore, the plurality of LEDs120,130, and140may be formed in the display device100in a non-transfer manner. First, the first epitaxial layer120mis grown on the first substrate110ahaving high growth efficiency to form the first LED120. The second epitaxial layer130mand the third epitaxial layer140mare grown on the second substrate110bhaving high growth efficiency to form the second LED130and the third LED140. In this case, the plurality of driving units DP and the plurality of wiring lines which drive the first LED120, the second LED130, and the third LED140are formed together on the first substrate110a. Next, the first connecting unit181of the first substrate110aand the second connecting unit182of the second substrate110bare aligned and bonded to electrically connect the plurality of driving units DP and the plurality of wiring lines of the first substrate110ato the second LED130and the third LED140of the second substrate110b. Therefore, the first LED120of the first substrate110aand the second LED130and the third LED140of the second substrate110bmay be driven by the plurality of driving units DP and the plurality of wiring lines of the first substrate110aand may be implemented as one display device100. Therefore, in consideration of the growth efficiency, even though the first LED120, the second LED130, and the third LED140are grown on different substrates110aand110b, the first substrate110aand the second substrate110bare bonded to implement one display device100. Therefore, the plurality of LEDs120,130, and140may be disposed in the display device100by adopting the non-transfer manner. Therefore, in the display device100according to an exemplary embodiment of the present disclosure and the method of manufacturing the display device100, the plurality of LEDs120,130, and140may be formed in the display device100in a non-transfer manner. Therefore, the transferring process is simplified, and the process time may be shortened.

FIG.8is a schematic cross-sectional view of one pixel of a display device according to another exemplary embodiment of the present disclosure.FIG.9is a plan view of one pixel on one surface of a first substrate of a display device according to another exemplary embodiment of the present disclosure.FIG.10is a plan view of one pixel on one surface of a second substrate of a display device according to another exemplary embodiment of the present disclosure.FIG.11is a cross-sectional view of a display device taken along the line XI-XI′ ofFIG.10. Configurations of a display device800ofFIGS.8to11are substantially the same as the display device100ofFIGS.1to7Oexcept for some driving unit DP of the plurality of driving units DP, so that a redundant description will be omitted.

Referring toFIG.8, in a display device800according to another exemplary embodiment of the present disclosure, a first LED120and a driving unit DP and a plurality of wiring lines for driving the first LED120are disposed on one surface of the first substrate110a. Further, a second LED130, a third LED140, and a driving unit DP which drives the second LED130and the third LED140are disposed on one surface of the second substrate110b.

In this case, the second LED130and the driving unit DP of the second sub pixel SPX2on one surface of the second substrate110bmay be electrically connected to the plurality of wiring lines of one surface of the first substrate110athrough the plurality of connecting units180. Therefore, the second LED130and the driving unit DP of the second sub pixel SPX2of one surface of the second substrate110bare supplied with the voltage from the plurality of wiring lines to be driven.

The third LED140and the driving unit DP of the third sub pixel SPX3on one surface of the second substrate110bmay be electrically connected to the plurality of wiring lines of one surface of the first substrate110athrough the plurality of connecting units180. Therefore, the third LED140and the driving unit DP of the third sub pixel SPX3of one surface of the second substrate110bare supplied with the voltage from the plurality of wiring lines to be driven.

In the meantime, inFIG.8, it is illustrated that the driving unit DP for driving the first LED120is disposed on one surface of the first substrate110aand two driving units DP for driving the second LED130and the third LED140are disposed on one surface of the second substrate110b. However, all the plurality of driving units DP may be disposed on one surface of the second substrate110bor only some of the plurality of driving units DP may be disposed on the first substrate110aand the second substrate110b, respectively, and the arrangement of the plurality of driving units DP is not limited.

Hereinafter, the plurality of sub pixels SPX1, SPX2, and SPX3of the first substrate110aand the second substrate110bwill be described in more detail with reference toFIGS.9to11.

Referring toFIG.9, the first LED120, the driving unit DP for driving the first LED120, the plurality of wiring lines, and the first connecting unit181are disposed on one surface of the first substrate110a.

In the first sub pixel SPX1, the first LED120and the driving unit DP are disposed on one surface of the first substrate110a. In the second sub pixel SPX2and the third sub pixel SPX3, only the first connecting unit181which is connected to the plurality of wiring lines is disposed on one surface of the first substrate110a.

Specifically, the first LED120, a first semiconductor element150, a second semiconductor element160, and a capacitor170of the driving unit DP may be disposed in the first sub pixel SPX1.

A first connecting unit181which is connected to the gate line GL, the data line DL, the power line PL, and the common line CL disposed along the boundary between the plurality of sub pixels SPX1, SPX2, and SPX3is disposed in the second sub pixel SPX2.

A first connecting unit181which is connected to the gate line GL, the data line DL, the power line PL, and the common line CL disposed along the boundary between the plurality of sub pixels SPX1, SPX2, and SPX3is disposed in the third sub pixel SPX3.

Referring toFIG.10, a second LED130, a third LED140, and a driving unit DP which is connected to the second LED130and the fourth LED140, respectively, and a second connecting unit182are disposed on one surface of the second substrate110b.

In the first sub pixel SPX1of one surface of the second substrate110b, in order to discharge the light emitted from the first LED120of one surface of the first substrate110athrough the second substrate110b, only the third passivation layer115, a fourth passivation layer818, and the second protective layer116are disposed, but a separate configuration may not be disposed.

In the second sub pixel SPX2, the second LED130, the first semiconductor element850, the second semiconductor element860, and the capacitor870of the driving unit DP, and the second connecting unit182connected to the second LED130and the driving unit DP are disposed. Specifically, the second connecting unit182is disposed so as to be in contact with the second p-type electrode133P of the second LED130, a first source pad electrode852P electrically connected to a first source region852of the first semiconductor element850, a first gate pad electrode851P electrically connected to the first gate electrode851of the first semiconductor element850, a second source pad electrode862P electrically connected to a second source region862of the second semiconductor element860, and a second capacitor electrode873, respectively.

In the third sub pixel SPX3, the third LED140, the first semiconductor element850, the second semiconductor element860, and the capacitor870of the driving unit DP and the second connecting unit182connected to the third LED140and the driving unit DP are disposed. Specifically, the second connecting unit182is disposed so as to be in contact with the third p-type electrode143P of the third LED140, a first source pad electrode852P electrically connected to a first source region852of the first semiconductor element850, a first gate pad electrode851P electrically connected to the first gate electrode851of the first semiconductor element850, a second source pad electrode862P electrically connected to a second source region862of the second semiconductor element860, and a second capacitor electrode873.

Referring toFIG.11, the power line PL, the gate line GL, the common line CL, the data line DL, the first passivation layer112, the second passivation layer113, and the first protective layer114are disposed on one surface of the first substrate110a.

The first passivation layer112is disposed on one surface of the first substrate110aand the power line PL and the gate line GL are disposed on the first passivation layer112.

The power line PL supplies the power voltage to the second p-type electrode133P and the second p-type semiconductor layer133of the second LED130to drive the second LED130. Therefore, the first connecting unit181is connected to the power line PL to electrically connect the power line PL of one surface of the first substrate110ato the second LED130of one surface of the second substrate110b. The first connecting unit181may be in contact with an upper surface of the power line PL through a contact hole formed in the second passivation layer113and the first protective layer114on the power line PL.

The gate line GL supplies the gate voltage to first gate electrodes151and851of the first semiconductor elements150and850of the plurality of driving units DP to turn on or off the first semiconductor elements150or850. Therefore, the first connecting unit181is connected to the gate line GL to electrically connect the gate line GL of one surface of the first substrate110ato the first gate electrode851of one surface of the second substrate110b. The first connecting unit181may be in contact with an upper surface of the gate line GL through a contact hole formed in the second passivation layer113and the first protective layer114on the gate line GL.

The second passivation layer113is disposed on the power line PL and the gate line GL and the common line CL and the data line DL are disposed on the second passivation layer113.

The common line CL may supply the common voltage to the second capacitor electrodes173and873of the plurality of driving units DP and the second source regions162and862of the second semiconductor elements160and860. Therefore, the first connecting unit181is connected to the common line CL to electrically connect the common line CL of one surface of the first substrate110ato the plurality of driving units DP of one surface of the second substrate110b. The first connecting unit181may be in contact with the upper surface of the common line CL through the contact hole formed on the first protective layer114on the common line CL.

The data line DL transmits a data voltage to the first source regions152and852of the first semiconductor elements150and850of the plurality of driving units DP. Therefore, the first connecting unit181is connected to the data line DL to electrically connect the data line DL of one surface of the first substrate110ato the plurality of driving units DP of one surface of the second substrate110b. The first connecting unit181may be in contact with the upper surface of the data line DL through the contact hole formed on the first protective layer114on the data line DL.

The first protective layer114is disposed on one surface of the first substrate110aso as to cover the common line CL and the data line DL. A plurality of contact holes is formed in the first protective layer114and the first connecting unit181may be connected to the power line PL, the gate line GL, the common line CL, and the data line DL below the first protective layer114through the plurality of contact holes of the first protective layer114.

Referring toFIGS.10and11, the second LED130, the driving unit DP, an additional gate insulating layer111′, a third passivation layer115, a fourth passivation layer818, a second protective layer116, and the second connecting unit182are disposed in the second sub pixel SPX2of one surface of the second substrate110b.

The second LED130and the first semiconductor element850and the second semiconductor element860of the driving unit DP are disposed on one surface of the second substrate110b.

The second LED130includes a second n-type semiconductor layer131which is in contact with one surface of the second substrate110b, a second light emitting layer132on the second n-type semiconductor layer131, a second p-type semiconductor layer133on the second light emitting layer132, and a second n-type electrode131P and a second p-type electrode133P. In this case, the second n-type semiconductor layer131of the second LED130may be supplied with the voltage from the second drain region863of the second semiconductor element860of the driving unit DP. The second p-type semiconductor layer133may be supplied with the voltage from the power line PL of one surface of the first substrate110a. Therefore, in order to electrically connect the second p-type electrode133P of the second LED130of one surface of the second substrate110band the power line PL of one surface of the first substrate110a, the second connecting unit182is connected to the second p-type electrode133P. The second connecting unit182may be in contact with the upper surface of the second p-type electrode133P through the contact hole formed in the fourth passivation layer818and the second protective layer116on the second p-type electrode133P. Therefore, the second connecting unit182may be in contact with the second p-type electrode133P to be electrically connected to the second LED130.

In this case, the second connecting unit182which is connected to the second p-type electrode133P may be in contact with the first connecting unit181connected to the power line PL of one surface of the first substrate110a. Therefore, the second LED130of one surface of the second substrate110bmay be electrically connected to the power line PL of one surface of the first substrate110athrough the second connecting unit182which is in contact with the second p-type electrode133P and the first connecting unit181which is in contact with the second connecting unit182.

The first semiconductor element850of the driving unit DP is disposed on one surface of the second substrate110b. The first semiconductor element850is supplied with the gate voltage from the gate electrode851through the gate line GL to be turned on or off. Therefore, in order to electrically connect the first gate electrode851of the first semiconductor element850of one surface of the second substrate110band the gate line GL of one surface of the first substrate110a, the second connecting unit182is connected to the first gate electrode851. The second connecting unit182may be in contact with the upper surface of the first gate pad electrode851P which is electrically connected to the first gate electrode851through the contact hole formed in the fourth passivation layer818and the second protective layer116on the first gate electrode851. Therefore, the second connecting unit182is in contact with the first gate pad electrode851P to be electrically connected to the first gate electrode851of the first semiconductor element850.

In this case, the second connecting unit182which is connected to the first gate pad electrode851P may be in contact with the first connecting unit181connected to the gate line GL of one surface of the first substrate110a. Therefore, the first gate electrode851of one surface of the second substrate110bmay be electrically connected to the gate line GL of one surface of the first substrate110athrough the first gate pad electrode851P, the second connecting unit182, and the first connecting unit181.

In the meantime, even though inFIGS.10and11, it is illustrated that the first gate electrode851of the first semiconductor element850and the second connecting unit182are connected through the first gate pad electrode851P, the first gate pad electrode851P may be omitted and the second connecting unit182may be directly connected to the first gate electrode851. The present disclosure is not limited thereto.

In the meantime, when the first semiconductor element850is turned on, the first source region852of the first semiconductor element850is supplied with the data voltage from the data line DL to transmit the data voltage to the second semiconductor element860and the capacitor870. Therefore, in order to electrically connect the first source region852of the first semiconductor element850of one surface of the second substrate110band the data line DL of one surface of the first substrate110a, the second connecting unit182is connected to the first source region852. The second connecting unit182may be in contact with the upper surface of the first source pad electrode852P which is electrically connected to the first source electrode852through the contact hole formed in the fourth passivation layer818and the second protective layer116on the first source region852. Therefore, the second connecting unit182is in contact with the first source pad electrode852P to be electrically connected to the first source region852of the first semiconductor element850.

In this case, the second connecting unit182which is connected to the first source pad electrode852P may be in contact with the first connecting unit181connected to the data line DL of one surface of the first substrate110a. Therefore, the first source region852of one surface of the second substrate110bmay be electrically connected to the data line DL of one surface of the first substrate110athrough the first source pad electrode852P, the second connecting unit182, and the first connecting unit181.

The second semiconductor element860of the second sub pixel SPX2is disposed on one surface of the second substrate110b. The second semiconductor element860is supplied with the voltage from the first drain region853of the first semiconductor element850from the second gate electrode861to be turned on or off. When the second semiconductor element860is turned on, the second source region862of the second semiconductor element860is supplied with the common voltage from the common line CL to transmit the common voltage to the second LED130. In this case, the common voltage from the common line CL may be supplied to the second source pad electrode862P which is electrically connected to the second source region862and the second capacitor electrode873which is integrally formed with the second source pad electrode862P. Therefore, in order to electrically connect the second source region862, the second source pad electrode862P, and the second capacitor electrode873of the second semiconductor element860of one surface of the second substrate110bto the common line CL of one surface of the first substrate110a, the second connecting unit182is connected to the second source pad electrode862P and the second capacitor electrode873which are integrally formed with each other. The second connecting unit182may be electrically connected to the second source pad electrode862P which is electrically connected to the second source region862and the second capacitor electrode873through the contact hole formed in the second protective layer116on the second source pad electrode862P and the second capacitor electrode873.

In this case, the second connecting unit182which is connected to the second source pad electrode862P and the second capacitor electrode873may be in contact with the first connecting unit181connected to the common line CL of one surface of the first substrate110a. Therefore, the second source region862of one surface of the second substrate110bmay be electrically connected to the common line CL of one surface of the first substrate110athrough the second source pad electrode862P, the second capacitor electrode873, the second connecting unit182, and the first connecting unit181.

In the meantime, as some driving units DP among the plurality of driving units DP are disposed on one surface of the second substrate110b, the additional gate insulating layer111′ is disposed on one surface of the second substrate110b. The additional gate insulating layer111′ insulates the first gate electrode851of the first semiconductor element850of one surface of the second substrate110bfrom the first source region852and the first drain region853and insulates the second gate electrode861of the second semiconductor element860from the second source region862and the second drain region863.

In the display device800according to another exemplary embodiment of the present disclosure, the plurality of LEDs120,130, and140and the driving units DP for driving the plurality of LEDs120,130, and140are disposed on the same substrate, thereby minimizing an alignment error between the plurality of LEDs120,130, and140and the plurality of driving units DP. Specifically, the first LED120and the driving unit DP for driving the first LED120are disposed on one surface of the first substrate110a. The second LED130and the driving unit DP for driving the second LED130and the third LED140and the driving unit DP for driving the third LED140are disposed on one surface of the second substrate110b. That is, in the display device800according to another exemplary embodiment of the present disclosure, in accordance with the arrangement of the plurality of LEDs120,130, and140, the plurality of driving units DP may be disposed on both the first substrate110aand the second substrate110b. Further, even though the plurality of wiring lines is disposed on the first substrate110aand some driving units DP of the plurality of driving units DP are disposed on the second substrate110b, the plurality of wiring lines and the plurality of driving units DP are electrically connected through the plurality of connecting units180. Therefore, in the display device800according to another exemplary embodiment of the present disclosure, in accordance with the arrangement of the plurality of LEDs120,130, and140, the plurality of driving units DP may be disposed on the same substrate as the plurality of LEDs120,130, and140and an alignment error between the plurality of LEDs120,130, and140and the plurality of driving units DP may be minimized.

According to an embodiment of the present disclosure, there is provided a display device. The display device includes a first substrate and a second substrate which are formed of different materials, a first LED disposed on the first substrate, and a second LED and a third LED disposed on the second substrate. The first LED, the second LED, and the third LED are disposed between the first substrate and the second substrate.

The first LED may be a red LED and any one of the second LED and the third LED may be a blue LED and the other one is a green LED.

The display device may further include a plurality of driving units which drives the first LED, the second LED, and the third LED. At least one of the plurality of driving units may be disposed on the first substrate.

Each of the plurality of driving units may include a first semiconductor element including a first drain region, a second semiconductor element including a second gate electrode which is electrically connected to the first drain region, and a capacitor which includes a first capacitor electrode between the first drain region and the second gate electrode and a second capacitor electrode electrically connected to a second drain region of the second semiconductor element. The second drain region of the second semiconductor element of each of the plurality of driving units may be electrically connected to the first LED, the second LED, and the third LED.

The plurality of driving units may be disposed on the first substrate, and a driving unit which is electrically connected to the second LED or the third LED, among the plurality of driving units, may further include a connecting unit extending from the second drain region of the second semiconductor element to the second substrate.

Some of the plurality of driving units may be disposed on the first substrate, and the others of the plurality of driving units may be disposed on the second substrate.

The display device may further include a reflective layer which is disposed on the first substrate so as to overlap the second LED and the third LED.

The display device may further include a first protective layer which is disposed on the entire first substrate so as to cover the first LED, a second protective layer which is disposed on the entire second substrate so as to cover the second LED and the third LED, and a filling member disposed between the first protective layer and the second protective layer.

Light emitted from the first LED, the second LED, and the third LED may be discharged through the second substrate.

According to another embodiment of the present disclosure, there is provided a display device. The display device includes a first substrate in which a first LED is disposed on one surface, and a second substrate in which a second LED and a third LED are disposed on one surface. The first substrate is disposed on one surface of the second substrate so as to be opposite to the second LED and the third LED, the second substrate is disposed on one surface of the first substrate so as to be opposite to the first LED, and growth efficiency of the first LED on the first substrate is higher than that on the second substrate, and growth efficiency of the second LED and the third LED on the second substrate is higher than that on the first substrate.

The first substrate may be an opaque substrate and the second substrate is a transparent substrate.

The second LED and the third LED may emit blue light and green light, respectively, and the second substrate may be any one of a sapphire substrate and a gallium nitride substrate.

The first LED may emit red light, and the first substrate may be any one of a gallium arsenic substrate and a gallium phosphide substrate.

The display device may further include a filling member and a reflective layer between the first substrate and the second substrate. The reflective layer may overlap an area excluding an area in which the first LED is disposed.

The first LED may include a first n-type semiconductor layer which is in contact with one surface of the first substrate, a first light emitting layer on the first n-type semiconductor layer, and a first p-type semiconductor layer on the first light emitting layer. The second LED may include a second n-type semiconductor layer which is in contact with one surface of the second substrate, a second light emitting layer on the second n-type semiconductor layer, and a second p-type semiconductor layer on the second light emitting layer. The third LED may include a third n-type semiconductor layer which is in contact with one surface of the second substrate, a third light emitting layer on the third n-type semiconductor layer, and a third p-type semiconductor layer on the third light emitting layer.

Light emitted from the first light emitting layer may be incident onto the first p-type semiconductor layer, and light emitted from the second light emitting layer and the third light emitting layer may be incident onto the second n-type semiconductor layer and the third n-type semiconductor layer, respectively.

According to still another embodiment of the present disclosure, there is provided a method of manufacturing a display device. The method of manufacturing a display device includes forming a first LED on one surface of a first substrate, forming a second LED and a third LED on one surface of a second substrate and bonding the first substrate and the second substrate such that one surface of the first substrate and one surface of the second substrate are opposite to each other.

The method of manufacturing a display device may further include forming a first driving unit for driving the first LED, a second driving unit for driving the second LED, and a third driving unit for driving the third LED on one surface of the first substrate, forming a first protective layer on the entire first substrate so as to cover the first LED, the first driving unit, the second driving unit, and the third driving unit, and forming a connecting unit which extends from the second driving unit and the third driving unit to an upper surface of the first protective layer.

The method of manufacturing a display device may further include forming a first driving unit for driving the first LED on the first substrate, and forming a second driving unit for driving the second LED and a third driving unit for driving the third LED on the second substrate. The first LED may overlap an area excluding an area where the second LED, the third LED, the second driving unit, and the third driving unit are disposed in the second substrate.

The forming of a first LED on one surface of a first substrate may include growing a first epitaxial layer which is formed of a first n-type semiconductor material layer, a first light emitting material layer, and a first p-type semiconductor material layer on one surface of the first substrate, etching the first epitaxial layer to form a first n-type semiconductor layer, a first light emitting layer, and a first p-type semiconductor layer, and forming a first n-type electrode and a first p-type electrode which are in contact with the first n-type semiconductor layer and the first p-type semiconductor layer, respectively, and one surface of the first n-type semiconductor layer may outwardly protrude from the first p-type semiconductor layer and the first light emitting layer.

The forming of the second LED and the third LED on one surface of the second substrate may include growing a second epitaxial layer which is formed of a second n-type semiconductor material layer, a second light emitting material layer, and a second p-type semiconductor material layer on one surface of the second substrate, etching the second epitaxial layer to form a second n-type semiconductor layer, a second light emitting layer, and a second p-type semiconductor layer, growing a third epitaxial layer which is formed of a third p-type semiconductor material layer, a third light emitting material layer, and a third n-type semiconductor material layer on one surface of the second substrate, etching the third epitaxial layer to form a third n-type semiconductor layer, a third light emitting layer, and a third p-type semiconductor layer, and forming a second n-type electrode, a second p-type electrode, a third n-type electrode, and a third p-type electrode which are in contact with the second n-type semiconductor layer, the second p-type semiconductor layer, the third n-type semiconductor layer, and the third p-type semiconductor layer, respectively.

During the etching of the second epitaxial layer to form the second n-type semiconductor layer, the second light emitting layer, and the second p-type semiconductor layer, a lower portion of the second p-type semiconductor material layer may be left in an area overlapping an area where the third LED is formed and only an upper portion of the second semiconductor material layer may be etched. During the growing of the third epitaxial layer, the third p-type semiconductor material layer, the third light emitting material layer, and the third n-type semiconductor material layer may be grown on a lower portion of the second p-type semiconductor material layer of one surface of the second substrate.