Semiconductor device having silicide layer completely occupied amorphous layer formed in the substrate and an interface junction of (111) silicon plane

A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes.

BACKGROUND OF THE INVENTION

1. Field of the invention

The invention relates to a semiconductor device formed on a bulk substrate or SOI (silicon on insulator) substrate and a method of manufacturing the same and, more specifically, to a semiconductor device having an interface of a silicon material and a metal silicide wherein the silicon material and the metal silicide have a high grid alignment at their interface.

2. Description of the related art

In the related art, a metal silicide is formed by forming a metal layer on a silicon layer by a well-known sputtering method, and by a subsequent thermal treatment. The metal silicide is widely used to minimize parasitic resistances of a transistor in a semiconductor device because the resistivity of the metal silicide is much smaller than that of silicon. To form the metal silicide in a semiconductor wafer process, a metal layer is formed on the entire surface of a silicon substrate after transistors including sources, drains and patterned gates, are formed. Then, the semiconductor wafer is subjected to heat. By this thermal treatment, the metal silicide is formed by reacting silicon with metal, wherein heat is applied only at an area where silicon contacts the metal. This method of forming the metal silicide is called “self-aligned silicide” or “salicide” because a patterning process or an alignment process of the silicide is not required. In the method, since the remaining metal, which is not reacted with silicon, is removed by using an anmoniacal solution bath, isolation between semiconductor elements can be maintained.

Currently, titanium (Ti), nickel (Ni) and cobalt (Co) are used as the metal material in the salicide process. Each of the metal silicides formed from these metals has more than two stable phases, which are determined by the temperature at which the metal silicide is formed. For example, when cobalt is reacted with silicon to form cobalt silicide, CoSi or CoSi2is formed. CoSi is stable when the reaction is performed at a relatively low temperature. On the other hand, CoSi2is stable when the reaction is performed at a relatively high temperature.

Using the metal silicide in the lowest resistivity phase is effective in reducing the parasitic resistance of the transistor. However, the thermal treatment at a high temperature is required to form the metal silicide in the lowest resistivity phase. When the thermal treatment at the high temperature is performed, the metal silicide reaction is apt to progress horizontally beneath the field oxide layer. As a result, isolation between the transistors may not be maintained. To avoid this problem, the thermal treatment is divided into more than two operations. In a first treatment process, a first metal silicide in a first stable phase is formed at a low temperature. Then, after unreacted metal is removed using an anmoniacal solution bath, the first metal silicide is transformed to a second metal silicide in a second stable phase by a second thermal treatment at a high temperature. The second metal silicide in the second stable phase has low resistivity characteristic because it is formed at a high temperature.

For example, cobalt silicide is formed by the following process. First, a cobalt layer is formed on the entire surface of the silicon substrate after transistors having sources, drains and patterned gates, are formed. Next, by subjecting the silicon substrate to a first thermal treatment at 550° C. for 30 seconds, a first cobalt silicide in a phase in which cobalt mono-silicide (CoSi) layer is a core, is formed from the cobalt and silicon. The first cobalt silicide also includes some metal-rich Co2Si. Then, after the unreacted cobalt is removed by using an anmoniacal solution bath, the silicon substrate is subjected in a second thermal treatment at 800° C. for 30 seconds to form a second cobalt silicide in a second phase. The second cobalt silicide is composed of a stable cobalt di-silicide (CoSi2) phase having low resistivity. In this silicidation process, the relationship between silicon, cobalt and cobalt silicide is as follows. When the entire cobalt layer is transformed to the cobalt silicide, CoSi2consumes twice the amount of silicon as compared to CoSi. On the other hand, when a fixed amount of silicon is transformed to the cobalt silicide, CoSi consumes twice the amount of cobalt as compared to CO Si2.

In the salicide process of the related art described above, the quality of the interface junction structure between the silicon layer of the channel region and the metal silicide layer is not good. That is, the crystallographic structure of the silicon is not harmonized with the crystallographic structure of the silicide. The reason of this phenomenon is not clear. However, it is considered that this phenomenon relates to the direction in which the silicidation progresses. In other words, the silicidation progresses in multiple directions in the related art. As a result of this phenomenon, problems of junction leakage or parasitic resistance (explained later) may occur.

SUMMARY OF THE INVENTION

It is therefore an objective of the invention to resolve the above-described problem and to provide a semiconductor device having low parasitic resistance and small junction leakage.

The objective is achieved by a semiconductor device having a silicon substrate having a top surface and a bottom surface, an insulator formed on the entire top surface, a silicon layer formed on the insulator, which acts as a channel region, silicon diffusion layers sandwiching the channel region, and silicide layers formed on the insulator by reacting silicon and metal, sandwiching the silicon diffusion layers, each silicide layer forming an interface junction with one of the diffusion layers, wherein each interface junction includes a (111) silicon plane.

The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First of all, (1) junction leakage and (2) parasitic resistance in a transistor of a semiconductor device are explained as follows.

As described in the description of the related art, it is known that highly doped silicon diffusion layers (hereinafter simply called diffusion layers), which are a source and drain of a transistor, are transformed to a metal silicide layer in part by reacting the diffusion layer and a metal layer formed on the diffusion layer in order to minimize the parasitic resistance of the transistor. Since parts of the diffusion layers are transformed to the metal silicide layer, an interface junction between each diffusion layer and metal silicide layer inevitably is formed. When the metal silicide layer expands excessively into the diffusion layer in the vertical direction or horizontal direction, the metal silicide layer becomes an undesirable passage for current leakage at the channel region under the gate electrode. In fact, even if the metal silicide layers do not contact to the silicon substrate at the channel region, the leak pass is formed at the channel region when the metal silicide layers are formed closely enough. Therefore, it is necessary to form the metal silicide layers to be smaller than the diffusion layers. However, the depth of the diffusion layer must be getting shallower to suppress a short channel effect caused by the requirements of the shrinkage of transistors. Therefore, the depth of the metal silicide layer is also greatly restricted. However, when a thin metal silicide layer is formed, sheet resistance is increased. This contradicts the object for forming the metal silicide layer for minimizing the parasitic resistance.

To resolve this problem, the following approaches are proposed to reduce the sheet resistance. That is, (a) the interface junction between the metal silicide layer and the diffusion layer is formed to be flat, (b) the metal silicide layer is formed to be spaced from an interface junction between the diffusion layer and the silicon layer at the channel region, and (3) the metal silicide layer is formed to be thick as possible.

Referring toFIG. 6, an SOI-FET (Silicon On Insulator-Field Effect Transistor)10is disclosed. The SOI-FET is formed on an insulator2, which is formed on a silicon substrate1. The SOI-FET, which is defined by a field oxide layer6, includes a source/drain, a gate electrode5, a silicon layer4acting as a channel region and a side wall7. The source/drain includes a diffusion layer8and a metal silicide layer9, which are formed in the silicon layer3formed on the insulator2.

As described below, the parasitic resistance of the transistor10is influenced by the diffusion layer8and the interface between the diffusion layer and the metal silicide layer. In the case of a single drain transistor such as the transistor10shown inFIG. 6, the total serial parasitic resistance Rtot is calculated by the following formula:
Rtot=2×(Rac+Rsp+Rsh+Rsh-s+Rco)
where Rac is a storage resistance at an edge of the silicon layer4, Rsp is an expansion resistance around the bottom of the diffusion layer8, Rsh is a resistance of the diffusion layer8, Rsh-s is a resistance of the metal silicide layer, and Rco is a contact resistance at the interface between the diffusion layer4and metal silicide layer.

Since the storage resistance Rac, the expansion resistance Rsp and the metal suicide resistance Rsh-s are negligibly small and are difficult to measure accurately, it is possible to neglect them. Therefore, the diffusion resistance Rsh and the contact resistance Rco influence the parasitic resistance of the transistor. When the metal silicide layer9is formed uncontrollably, it is expected that defects in the interface between the diffusion layer8and the metal silicide layer9may occur. Therefore, it is also expected that Schottky barrier heights of the interface between the diffusion layer8and the metal silicide layer9may be uneven at particular areas thereof. This may cause the contact resistance changed or increased. The problem as to the increase or the change of the contact resistance becomes significant when seeking to minimize the size of transistors. It is therefore an objective of the invention to resolve the above-described problem.

First Preferred Embodiment

Referring toFIG. 1, an SOI-FET100formed on a SOI substrate11is shown. The SOI substrate11is formed of a silicon substrate52and an insulator51, which is formed on the silicon substrate52. The SOI-FET is defined and isolated from other transistors by a field oxide layer50. The SOI-FET100includes a source/drain, a gate electrode13, a silicon layer16acting as a channel region and a side wall14. The source/drain includes a diffusion layer15and a metal silicide layer17. The diffusion layer15is formed by implanting impurities in the silicon layer. The diffusion layer15includes a (111) silicon plane at the interface of the metal silicide layer17.

The metal suicide layer17includes a (111) metal suicide plane at its interface with the diffusion layer15, when the diffusion layer15includes the (111) silicon plane, because the (111) silicon plane has a high grid alignment with the metal silicide layer17whose crystallographic structure is a cubic system. Therefore, at the interface junction18, the diffusion layer15includes a (111) silicon plane, and the metal silicide layer17includes a (111) metal silicide plane.

When the diffusion layer15including the (111) silicon plane, and the metal silicide layer17including the (111) metal silicide plane are formed, the structures of the interface therebetween shown inFIGS. 2A and 2Bmay be formed. Referring toFIG. 2A, a first type interface18is shown. In this case, a single flat (111) silicon plane is formed. Referring toFIG. 2B, a second type interface19is shown. In this case, the second type interface includes several (111) silicon planes18-1,18-2,18-3, which are formed in parallel.

A process of manufacturing the semiconductor device100having the first type interface structure is explained with reference toFIGS. 3A through 3C. In this process, as the typical example, cobalt is used for forming the metal silicide layer17. Referring toFIG. 3A, the SOI layer12having a thickness of 32 nm is formed on the SOI substrate11that includes the insulator52that is formed on the silicon substrate51. The SOI layer12has the (111) silicon plane as its crystal orientation. After forming the field oxide layer50for defining an active area, the gate electrode13and the side wall14are formed on the SOI layer12, and then, diffusion layer15is formed in the SOI layer12. Next, a cobalt layer55having a thickness of 7 nm is formed on the entire surface of the SOI layer12. Then, the SOI substrate11is heated at 550° C. for about 30 seconds as a first thermal treatment. As a result of the first thermal treatment, a cobalt mono-silicide (CoSi) layer20-1in a first phase, is formed in the diffusion layer15by reacting the cobalt layer55and diffusion layer15. The cobalt mono-silicide layer20-1, which is formed stable at the low temperature, includes some metal-rich Co2Si.

In general, the amount of the metal silicide layer formed by the condition described above, is determined by proportion of the thickness of the SOI layer12to the thickness of the cobalt layer55. As shown inFIG. 3A, unreacted silicon remains in the diffusion layer15under the condition described above.

Next, after an unreacted cobalt layer55is removed by using an anmoniacal solution bath, the SOI substrate11is heated at 800° C. for about 30 seconds as a second thermal treatment. As a result of the second thermal treatment, the cobalt mono-silicide (CoSi) layer20-1in the first phase is transformed to a cobalt di-silicide (CoSi2)20-2in a second phase, which is stable at high temperatures. Further, referring toFIG. 3B, since the amount of silicon that is indispensable to transform the CoSi to CoSi2is insufficient in the CoSi layer20-1, surplus cobalt is transferred into the diffusion layer in the horizontal direction and the vertical direction. However, as shown inFIG. 3B, the expansion of the CoSi2layer20-2in the vertical direction is stopped when the CoSi2layer20-2reaches the isolator52. Therefore, the insulator52acts as a stopper against the progress of silicidation in the vertical direction. Therefore, once the CoSi2layer20-2has reached the isolator52, surplus cobalt in the CoSi2layer20-2is transferred into the diffusion layer15in the horizontal direction only toward the channel region16as indicated by the arrows inFIG. 3B. Since cobalt is transferred from the CoSi2layer20-2into the diffusion layer15, cobalt is supplied into the diffusion layer15gradually. Therefore, cobalt reacts with silicon of the diffusion layer15in a thermodynamic equilibrium condition. As a result, the cobalt silicide layer17shown inFIG. 3Cis formed by layer-by-layer growth along the (111) silicon plane, which is the stable plane of silicon because the crystal growth of metal silicide is progressed along a low energy stable plane. Therefore, as shown inFIG. 3C, after the second thermal treatment is completed, the SOI-FET, which includes the interface junction18between the diffusion layer15and the metal silicide layer17having the (111) silicon plane and the (111) metal silicide plane, is formed. Accordingly, high degrees of grid alignment and evenness at its interface junction18, can be expected. It is not clear the reason why the (111) silicon plane is formed at the interface junction18in this process. However, it is believed that the (111) silicon plane is formed because the silicidation progresses in the horizontal direction only toward the channel region16.

It is well-known that Fermi level is pinned because of the interface level of silicon so that the Schottky barrier height is held when the junction between the metal and silicon is formed. Generally, it is considered that the interface level of silicon is caused by the grid defects or grid misalignment of these materials for forming the interface junction.

According to the first embodiment of the invention, since the grid defects at the interface junction18are dramatically reduced, the contact resistance at the interface junction18between silicon and metal suicide is effectively reduced. Further, since an area of the (111) silicon plane at the interface junction is 22% larger than that of the (110) silicon plane, the contact resistance is further reduced because the area of contact between silicon and metal suicide is increased. As a result, the parasitic resistance and the junction leakage of the SOI-FET can be reduced.

Second Preferred Embodiment

The difference between the first and second embodiment is the process of manufacturing the SOI-FET100shown inFIG. 1. In the first embodiment, although the thermal treatment is performed twice, the thermal treatment is performed three times in the second embodiment. The details of the manufacturing process in the second embodiment are described below with reference toFIGS. 4A through 4D. In the second embodiment, as a typical example, cobalt is used for forming the metal silicide layer17.

Referring toFIG. 4A, the SOI layer12having a thickness of 32 nm is formed on the SOI substrate11that includes the insulator52that is formed on the silicon substrate51. The SOI layer12has the (111) silicon plane as its crystal orientation. After forming the field oxide layer50for defining an active area, the gate electrode13and the side wall14are formed on the SOI layer12, and then, diffusion layer15is formed in the SOI layer12. Next, a cobalt layer55having a thickness of 7 nm is formed on the entire surface of the SOI layer12. Then the SOI substrate11is heated at 550° C. for about 30 seconds as a first thermal treatment. As a result of the first thermal treatment, a cobalt mono-silicide (CoSi) layer21-1in a first phase, is formed in the diffusion layer15by reacting the cobalt layer55and diffusion layer15. The cobalt mono-silicide layer21-1, which is formed stable at the low temperature, includes some metal-rich Co2Si.

Next, referring toFIG. 4B, after an unreacted cobalt layer55is removed by using an anmoniacal solution bath, the CoSi layer21-1is phase-transferred to a CoSix (1<×<2) layer21-2in a second phase by performing a second thermal treatment. The second thermal treatment is performed at the relatively high temperature around 800° C., which is higher than the temperature of the first thermal treatment. According to the second thermal treatment, the diffusion layer15except for an area under the side wall14is transformed to the CoSix (1<×<2) layer21-2. That is, the bottom of the CoSix (1<×<2) layer21-2reaches the insulator52under the second thermal treatment. However, since the insulator52acts as a stopper against the progress of the silicidation in the vertical direction, the metal silicide layer is not formed in the silicon substrate51under the insulator52.

Next, referring toFIG. 4C, a cobalt di-silicide (CoSi2) layer21-3having a stoichiometric composition, which is a third phase, is phase-transferred from the CoSix (1<×<2) layer21-2by performing a third thermal treatment. The third thermal treatment is performed at the relatively high temperature around 800° C., which is higher than the temperature of the first thermal treatment. When formed at a high temperature, the cobalt silicide layer21-3is stable in the phase of CoSi2, and has small resistivity. When the phase of cobalt silicide is transformed from CoSix (1<×<2) to CoSi2, surplus cobalt in the CoSix (1<×<2) layer20-2is transferred into the diffusion layer15in the horizontal direction only toward the channel region16as indicated by as arrows inFIG. 3C. As described above with reference toFIG. 4B, since the bottom of the metal silicide layer21-2has reached to the insulator52, silicon of the diffusion layer, which is unreacted with cobalt, exists under the side wall.

Since cobalt is transferred from the CoSi2layer21-3into the diffusion layer15, cobalt is supplied into the diffusion layer15gradually. Therefore, cobalt reacts with silicon of the diffusion layer15in a thermodynamic equilibrium condition. As a result, the cobalt silicide layer17shown inFIG. 4Dis formed by layer-by-layer growth along the (111) silicon plane, which is the stable plane of silicon because the crystal growth of metal silicide is progressed along a low energy stable plane. Therefore, as shown inFIG. 4D, after the third thermal treatment is completed, the SOI-FET200, which includes the interface junction18between the diffusion layer15and the metal silicide layer17having the (111) silicon plane, is formed.

The diffusion layer15having the (111) silicon plane has high degree of grid alignment with the cobalt silicide17at its interface junction. Further, since the crystallographic structure of the cobalt silicide17is a cubic system, the cobalt silicide17includes the (111) cobalt silicide plane. Therefore, the interface junction structure between the silicon and metal silicide having high degrees of grid alignment and evenness can be obtained because the interface junction is formed with the (111) silicon plane and the (111) metal silicide plane.

In the second embodiment, the second and third thermal treatments are defined as follows. The second thermal treatment is the operation for forming the CoSix layer21-2, which reaches the insulator52. The third treatment is the operation for forming the CoSi2layer21-3and for making the (111) silicon plane at the interface18between the diffusion layer15and the CoSi2layer17by progressing silicidation in the horizontal direction only high degree toward the channel REGION16.

According to the second embodiment, since the CoSi2layer17is formed by three thermal treatments, higher degree of grid alignment of silicon and metal silicide and higher degree of evenness at the interface are expected in comparison with the transistor100formed in the process described in the first embodiment.

Third Preferred Embodiment

In the third embodiment, a metal silicide layer is formed of cobalt as well as the other embodiments. However, a bulk substrate made of silicon is used in the third embodiment, instead of using the SOI substrate.

Referring toFIG. 5A, a field oxide layer32is formed in a silicon substrate31to define an active area X. Then, a gate electrode33and a side wall34are formed on the silicon substrate31in the active area X. Then, after a cobalt layer80having a thickness of 7 nm, is formed on the entire surface of the silicon substrate31, a cobalt silicide (CoSi) layer31in a first phase is formed by a first thermal treatment in the silicon substrate31with reaction between cobalt and silicon. The first thermal treatment is performed at 550° C. for about 30 seconds.

Next, referring toFIG. 5B, after an unreacted cobalt layer80is removed by using an anmoniacal solution bath, an amorphous layer43is formed in the silicon substrate31by ion implantation. In the embodiment, germanium (Ge) is used for the ion implantation. Here, the pre-amorphization energy of the ion implantation depends on the thickness of the amorphous layer43to be formed. For example, the amorphous layer43having the thickness of 35 nm is formed with 20 KeV, and the amorphous layer43having the thickness of 45 nm is formed with 30 KeV.

Referring toFIG. 5C, the CoSi layer39is phase-transferred to a CoSix (1<×<2) layer40in a second phase by a second thermal treatment. The second thermal treatment is performed at the relatively high temperature around 800° C., which is higher than the temperature of the first thermal treatment. According to the second thermal treatment, the CoSix layer reaches the bottom of the amorphous layer43.

Referring toFIG. 5D, the CoSix layer40is phase-transferred to a CoSi2layer41in a third phase by a third thermal treatment. The third thermal treatment is performed at the relatively high temperature around 800° C., which is higher than the temperature of the first thermal treatment. As indicated by the arrows inFIG. 5D, surplus cobalt in the CoSix layer40is transferred in the horizontal direction only toward the channel region36because amorphous silicon is transformed to metal silicide much easier than crystallized silicon. Therefore, in the third embodiment, the silicon substrate31itself acts as a stopper against the progress of the silicidation in the vertical direction.

Since cobalt is transferred from the CoSi2layer41into the amorphous layer43of the silicon substrate31in the horizontal direction only, cobalt is supplied into the amorphous layer43of the silicon substrate31gradually. Therefore, cobalt reacts on silicon in the amorphous layer43in a thermodynamic equilibrium condition. As a result, the cobalt silicide layer42shown inFIG. 5Eis formed by layer-by-layer growth along the (111) silicon plane, which is the stable plane of silicon because the crystal growth of silicide is progressed along a low energy stable plane. Therefore, as shown inFIG. 5E, after the third thermal treatment is completed, the SOI-FET300, which includes the interface junction38between the silicon substrate31in the channel region36and the metal silicide layer42having the (111) silicon plane, is formed.

The silicon substrate31having the (111) silicon plane has a high grid alignment with the cobalt silicide42at its interface junction. Further, since the crystallographic structure of the cobalt silicide42is a cubic system, the cobalt silicide42includes the (111) cobalt silicide plane. Therefore, the interface junction structure between silicon and metal silicide having high degreed of grid alignment and evenness can be obtained because the interface junction is formed with the (111) silicon plane and the (111) metal silicide plane.

In the third embodiment, the second and third thermal treatments are defined as follows. The second thermal treatment is the operation for forming the CoSix layer40, which reaches the bottom of the amorphous layer43. The third thermal treatment is the operation for forming the CoSi2layer41and for making the (111) silicon plane at the interface38between the silicon substrate31in the channel region36and the CoSi2layer42by progressing the silicidation in the horizontal direction only toward the channel region36.

According to the third embodiment, is possible to reduce the parasitic resistance and the junction leakage of the transistor, which is formed in the bulk substrate.

Various other modifications of the illustrated embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. For example, in the third embodiment, the second and third thermal treatments can be combined into a single thermal treatment. Therefore, the appended claims are intended to cover any such modifications or embodiments as fall within the true scope of the invention.