Information processing system and image forming apparatus capable of accurately predicting lifetime of semiconductor device, and control method therefor

An information processing system that is capable of accurately predicting a lifetime of a semiconductor device that carries out communications related to reading and writing of data from and to a storage device. The information processing system has an image forming apparatus having a nonvolatile memory and a first controller that controls reading and writing of data from and to the nonvolatile memory. The information processing system also has a server that monitors a lifetime of the first controller. The server has a receiving I/F that receives information indicating a communication data size of reading and writing of data from and to the nonvolatile memory, and a second controller that predicts the lifetime of the first controller based on the received information indicating the communication data size.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an information processing system, an image forming apparatus, and a control method therefor.

Description of the Related Art

An image forming apparatus equipped with a semiconductor device such as a CPU (Central Processing Unit) is known (see, for example, Japanese Laid-Open Patent Publication (Kokai) No. 2015-198377). As semiconductor manufacturing processes have been becoming sophisticated, high integration and high speed communication have become possible while durability of semiconductor devices has been decreasing. For example, the greater the number of accesses to a storage device is, the higher is the likelihood that an interface unit of the CPU, which carries out communications related to writing and reading of data to and from a storage device, is broken. Semiconductor devices have their lifetime, and thus when a semiconductor device has come close to the end of its life, electronic components including this semiconductor device need to be replaced. There is a strong demand for a technique for accurately predicting the lifetime of a semiconductor device so that it can be replaced without delay, before it is broken. For example, predicting the lifetime of a semiconductor device based on a size of data written from the semiconductor device is under consideration.

However, with information on only a data size of written data, it is impossible to accurately predict the lifetime of a CPU that carries out communications related to reading and writing of data from and to a storage device.

SUMMARY OF THE INVENTION

The present invention provides an information processing system and an image forming apparatus that are capable of accurately predicting the lifetime a CPU, which carries out communications related to reading and writing of data from and to a storage device, and a control method therefor.

Accordingly, the present invention provides an information processing system comprising an image forming apparatus having a nonvolatile memory and a first controller that controls reading and writing of data from and to the nonvolatile memory, and a server configured to monitor a lifetime of the first controller in the image forming apparatus, wherein the sever comprises a receiving I/F configured to receive information indicating a communication data size of reading and writing of data from and to the nonvolatile memory, and a second controller configured to predict a lifetime of the first controller based on the received information indicating the communication data size.

According to the present invention, the lifetime of a semiconductor device that carries out communications related to reading and writing of data from and to a storage device is accurately predicted.

DESCRIPTION OF THE EMBODIMENTS

A description will now be given of an information processing system according to a first embodiment of the present invention.

FIG.1is a view schematically showing an arrangement of the information processing system100according to the first embodiment of the present invention. Referring toFIG.1, the information processing system100has an image forming apparatus101a, an image forming apparatus101b, a server102, and a communication terminal103. It should be noted that in the present embodiment, the arrangement of the information processing system100is just one example, and the information processing system100has only to be have one or more image forming apparatuses. The information processing system100may also have a plurality of communication terminals. The server102is connected to the image forming apparatus101aand the image forming apparatus101bvia a network104, and also connected to the communication terminal103via a network105. It should be noted that in the present embodiment, the image forming apparatus101aand the image forming apparatus101bhave the same functions and arrangement, and hence the functions and arrangement of only the image forming apparatus101awill be described by way of example.

The image forming apparatus101ais an MFP (Multi Functional Peripheral) equipped with a plurality of functions such as a copying function, a scanning function, a faxing function, and a communicating function. The image forming apparatus101areceives, for example, print job data, which is sent from an external apparatus, via the server102. The image forming apparatus101agenerates image data by scanning in an original and uploads the image data to the server102. The network104and the network105are a WAN (Wide Area Network) and/or a LAN (Local Area Network). In the network104and the network105, for example, TCP/IP (Transmission Control Protocol/Internet Protocol) is used as a communication protocol.

The server102is, for example, a cloud server. The server102manages information about the image forming apparatus101aand the image forming apparatus101b. The server102monitors the lifetime of each electronic component in the image forming apparatus101aand the image forming apparatus101b. For example, the server102predicts the lifetime of an electronic component which the image forming apparatus101ahas based on information received from the image forming apparatus101a, and upon predicting that the electronic component will soon reach its end of life, the server102notifies the communication terminal103of this prediction.

The communication terminal103is a communication apparatus, which is capable of communicating with the server102, such as a PC (Personal Computer), a smartphone, or a tablet terminal. The communication terminal103is operated by a serviceperson or operator who remotely monitors the operating status of the image forming apparatus101aand the image forming apparatus101b.

FIG.2is a block diagram schematically showing a hardware arrangement of the image forming apparatus101ainFIG.1. Referring toFIG.2, the image forming apparatus101ahas an arithmetic processing unit201, a nonvolatile memory202, a volatile memory203, a nonvolatile memory204, a communication control unit205, an image processing unit206, a volatile memory207, an image reading unit208, and an image forming unit209.

The arithmetic processing unit201is a semiconductor device and more specifically, a CPU. The arithmetic processing unit201includes a communication data size counter214and a PHY (Physical Layer)215. The arithmetic processing unit201loads programs stored in the nonvolatile memory202to the volatile memory203and successively executes the programs in response to operation of a program counter (not shown) which the arithmetic processing unit201has.

The nonvolatile memory202is a storage device capable of holding data even when the supply of power is stopped and is, for example, an eMMC (embedded Multi Media Card). The nonvolatile memory202stores programs. The programs are those which control the entire system of the image forming apparatus101asuch as a program or boot loader for starting an OS (Operating System). The nonvolatile memory202is connected to the PHY215of the arithmetic processing unit201via buses210to213. The bus210is for transferring a clock signal A generated by the arithmetic processing unit201to the nonvolatile memory202. The bus211is for transferring a clock signal B generated by the nonvolatile memory202to the arithmetic processing unit201. The bus212is for transferring a command signal. The bus213is for transferring a data signal.

The clock signal A is output from the arithmetic processing unit201, which is a host, to the nonvolatile memory202. In the image forming apparatus101a, the clock signal A is usually used as a reference clock at the time of communication. The eMMC standard which the nonvolatile memory202is compliant with supports a plurality of communication modes. To carry out a communication between the arithmetic processing unit201and the nonvolatile memory202in a communication mode named HS400, a reference clock used for sampling of data output from the nonvolatile memory202, which is a device, performed by the arithmetic processing unit201, which is the host, needs to be output from the nonvolatile memory202. A clock signal that is used in this case is the clock signal B. Also, the arithmetic processing unit201sends the command signal, which is an instruction for reading, writing, or the like, and the data signal including data corresponding to the instruction, to the nonvolatile memory202.

Data is read from and written to the nonvolatile memory202on a block-by-block basis, and a data size per block is managed by a file system (not shown) of the image forming apparatus101a. The data size per block is, for example, about 512 bytes. In the present embodiment, the communication data size counter214of the arithmetic processing unit201counts the number of reading/writing operations that have been performed while the image forming apparatus101ais energized, on a block-by-block basis. A result of counting by the communication data size counter214is held by the nonvolatile memory202. For example, the communication data size counter214obtains a count of ten as the number of reading operations performed for one block at a time, two as the number of writing operations performed for one block at a time, a count of five as the number of reading operations performed for two blocks at a time, a count of one as the number of writing operations performed for two blocks at a time, a count of three as the number of reading operations performed for four blocks at a time, a count of two as the number of writing operations performed for four blocks at a time.

A predetermined operating rate is determined in advance for the PHY215, and when the operating rate of the PHY215becomes greater than the predetermined operating rate, it becomes impossible for the PHY215to operate normally. The operating rate is a rate at which the PHY215is allowed to operate per unit time. In the present embodiment, an operating rate of 80% for the clock signal A is determined as the predetermined operating rate. For example, in the image forming apparatus101aconfigured to operate for five years, when a cumulative total of hours for which the arithmetic processing unit201has output the clock signal A is longer than four years, there is a very high possibility that the PHY215will fail. To prevent a failure of the PHY215, the arithmetic processing unit201performs clock gating control on the clock signal A that is output to the nonvolatile memory202. In the clock gating control, control is performed to stop generating the clock signal A during a time period during which neither the command signal nor the data signal is communicated, that is, a time period during which no data is read or written. Operations in the clock gating control will be described later.

The volatile memory203is a DRAM. The volatile memory203is used as an area to which the programs stored in the nonvolatile memory202are loaded. The volatile memory203is used as a work memory for the arithmetic processing unit201and as a temporary storage area where arithmetic processing data is temporarily stored. The nonvolatile memory204is a storage device that is used for a different purpose from that of the nonvolatile memory202and, for example, stores identification information about the image forming apparatus101asuch as a product serial number uniquely assigned to the image forming apparatus101a.

The communication control unit205carries out communications via the network104with the server102, which is connected to the image forming apparatus101a, according to the communication protocol TCP/IP. In the present embodiment, it is assumed that the image forming apparatus101ais connected to the server102via an Ethernet cable. The image forming apparatus101ais also capable of being peer-to-peer connected to an information processing apparatus such as a PC via the Ethernet cable, and the communication control unit205outputs PDL (Page Description Language) data received from the information processing apparatus to the arithmetic processing unit201.

The image processing unit206performs, for example, image processing on image data received from the image reading unit208, image processing on image data to be output to the image forming unit209, or the like. Examples of the image processing include a packetization process, a compression process, a rotation process, and a halftoning process. The image processing unit206also has an arithmetic processing unit (not shown) and uses the volatile memory207as a work memory when performing image processing.

The image reading unit208has a contact image sensor (not shown), which converts characters and images on sheets to electronic data, and functions as an input unit in copying and scanning that are basic functions of the image forming apparatus101a. The image forming unit209is an output unit that is used in copying and printing and forms an image on a sheet using a photosensitive body (not shown), toner (not shown), a fixing unit (not shown), and so forth provided in the image forming apparatus101a.

A description will now be given of the clock gating control that is performed on the clock signal A to be output to the nonvolatile memory202by the arithmetic processing unit201.

The clock gating control is a control intended mainly to reduce power consumption of a semiconductor device. A CPU, which is a semiconductor device, generally keeps outputting a clock signal while the power is on. The CPU, however, does not keep sending or receiving the command signal or data signal while outputting the clock signal. In the clock gating control, when it is detected that sending or receiving the command signal or data signal is not performed, the CPU outputting the clock signal stops generation of the clock signal is stopped, whereby the power consumption of the CPU is reduced. In recent years when semiconductor devices have been increasingly finer, the clock gating control is useful in not only reducing power consumption but also delaying the time when a PHY of the CPU fails.

In the present embodiment, the clock gating control function is enabled when predetermined setting values are set in a register (not shown) of the arithmetic processing unit201through a software module such as a BIOS (Basic Input Output System) or OS.

FIG.3is a conceptual view useful in explaining the clock gating control performed by the arithmetic processing unit201inFIG.2. When the clock gating control function is disabled, the arithmetic processing unit201continues outputting the clock signal A while the power is supplied to the arithmetic processing unit201, irrespective of whether or not there is an access to the nonvolatile memory202such as reading or writing (see, for example, (a) inFIG.3). On the other hand, when the clock gating control function is enabled, the arithmetic processing unit201outputs the clock signal A only during a time period during which there is the access to the nonvolatile memory202, and the arithmetic processing unit201does not generate the clock signal A during a time period during which there is not the access to the nonvolatile memory202(see, for example, (b) inFIG.3). The time period during which there is the access to the nonvolatile memory202means a time period from the start to completion of reading from or writing to the nonvolatile memory202, and the time period during which the clock signal A is output increases in proportion to the size of data to be read or written. Thus, in the clock gating control, the operating rate of the clock signal A depends on the size of data that is read from or written to the nonvolatile memory202by the arithmetic processing unit201.

In the present embodiment, in the clock gating control, attention is focused on that the operating rate of the clock signal A is proportional to the size of data that is read from or written to the nonvolatile memory202by the arithmetic processing unit201, and based on this information, the lifetime of the PHY215is predicted.

For example, in a case where the arithmetic processing unit201has continued outputting the clock signal A at a frequency of 200 MHz for five years, about 3.2×1016clocks are output in theory. This means that data with a data size of about 4.0×1015bytes (hereafter referred to as “the maximum data size”) can be read from and written to the nonvolatile memory202. In the present embodiment, since there is an upper limit of 80% to the operating rate of the clock signal A, a total cumulative data size of data to be read from or written to the nonvolatile memory202needs to fall within a data size of about 3.2×1015bytes (hereafter referred to as “the communication limit data size”) corresponding to 80% of the maximum data size. In the present embodiment, a total cumulative size of data to be read from and written to the nonvolatile memory202is controlled to fall within a data size (hereafter referred to as “the failure prediction threshold value”) that is determined in consideration of a predetermined margin allowed for the communication limit data size. The failure prediction threshold value is a value that corresponds to 90% of the communication limit data size. When the operating rate of the clock signal A exceeds the failure prediction threshold value, the server102determines that the PHY215is nearing the end of its life, carries out the process in step S604to be described later, and notifies the communication terminal103to that effect.

FIG.4is a block diagram schematically showing a hardware arrangement of the server102inFIG.1. Referring toFIG.4, the server102has an arithmetic processing unit401, a volatile memory402, a storage device403, and a communication control unit404. The arithmetic processing unit401is connected to the volatile memory402, the storage device403, and the communication control unit404.

At the time of system startup, in the server102, the arithmetic processing unit401loads programs stored in the storage device403to the volatile memory402. The arithmetic processing unit401executes the loaded programs to perform various types of control. For example, the arithmetic processing unit401performs arithmetic operations regarding various types of data received via the network104and the network105.

The storage device403is a nonvolatile memory with a relatively large capacity such as an HDD (Hard Disk Drive) or SSD (Solid State Drive). It should be noted that in the present embodiment, the server102needs to store an enormous amount of data and thus may be configured to be equipped with a plurality of storage devices403.

The communication control unit404is connected to the image forming apparatus101a, the image forming apparatus101b, and the communication terminal103via Ethernet cables. It should be noted that in the present embodiment, the server102may be equipped with only one physical interface (connector) (not shown), to which an Ethernet cable is connected, and be logically split into a plurality of networks by a virtual LAN. The server102may be configured to be equipped with a plurality of physical interfaces (I/Fs), to which Ethernet cables are connected, and a plurality of communication control units for the respective interfaces.

FIG.5is a flowchart showing the procedure of a communication data size information storage process that is carried out by the image forming apparatus101ainFIG.1. The process inFIG.5is implemented by the arithmetic processing unit201executing a program loaded from the nonvolatile memory202to the volatile memory203. The process inFIG.5is carried out when the arithmetic processing unit201has received a shutdown interrupt signal. The shutdown interrupt signal is an interrupt signal output to the arithmetic processing unit201from a circuit of the image forming apparatus101a, which has detected an event indicating issuance of a shutdown instruction, for example, a depression of a power switch of the image forming apparatus101aby the user.

Referring toFIG.5, the arithmetic processing unit201stands by until it receives the shutdown interrupt signal (step S501). Upon receiving the shutdown interrupt signal (YES in the step S501), the arithmetic processing unit201stores communication data size information in the nonvolatile memory202(step S502). The communication data size information includes the number of reads and writes for each block, which is counted by the communication data size counter214during a time period from the start of the power supply to the image forming apparatus101ato receipt of the shutdown interrupt signal by the arithmetic processing unit201in the step S501, and a data size per block. Then, the arithmetic processing unit201causes the communication data size counter214to stop counting, clears a count value indicating a result of counting by the communication data size counter214(step S503), carries out a shutdown process for the image forming apparatus101ato end the communication data size information storage process.

As described above, in the present embodiment, the communication data size information including the information about the size of data read from and written to the nonvolatile memory202by the arithmetic processing unit201during a time period from startup to shutdown of the image forming apparatus101ais held. In the following description, this communication data size information is referred to as “the communication data size information during the previous operation”.

FIG.6is a flowchart showing the procedure of a communication data size information sending process that is carried out by the image forming apparatus101ainFIG.1. The process inFIG.6is implemented by the arithmetic processing unit201executing a program loaded from the nonvolatile memory202to the volatile memory203. The process inFIG.6is carried out when the power is started to be supplied to the arithmetic processing unit201and the arithmetic processing unit201ended an initialization process for an eMNC driver (not shown), which controls the nonvolatile memory202, and an initialization process for the file system (not shown).

Referring toFIG.6, the arithmetic processing unit201causes the communication data size counter214to start counting (step S601). Next, the arithmetic processing unit201obtains the communication data size information during the previous operation, which was stored in the step S502described above, from the nonvolatile memory202(step S602). Then, the arithmetic processing unit201obtains identification information about the image forming apparatus101afrom the nonvolatile memory204(step S603). After that, the arithmetic processing unit201causes the communication control unit205to send the communication data size information during the previous operation and the identification information about the image forming apparatus101ato the server102(step S604), and ends the communication data size information sending process.

FIG.7is a flowchart showing the procedure of a lifetime prediction process that is carried out by the server102inFIG.1. The process inFIG.7is implemented by the arithmetic processing unit401of the server102executing a program loaded from the storage device403to the volatile memory402. It is assumed that in the process inFIG.7, an operating rate management file800inFIG.8, to be described later, is stored beforehand in the storage device403.

Referring toFIG.7, first, the arithmetic processing unit401stands by until it receives the communication data size information during the previous operation and the identification information from the image forming apparatus101aor the image forming apparatus101b(step S701). For example, upon receiving the communication data size information during the previous operation and the identification information about the image forming apparatus101afrom the image forming apparatus101a(YES in the step S701), the arithmetic processing unit401obtains the operating rate management file800from the storage device403(step S702).

The operating rate management file800is a file for managing information about a plurality of image forming apparatuses connected to the server102, such as the image forming apparatus101aand the image forming apparatus101a.

The operating rate management file800includes a product serial number801, a reception date and time802, a total read data size803, a total written data size804, a total cumulative communication data size805, and a notification sending date and time806. Identification information received from, for example, the image forming apparatus101aby the server102is set as the product serial number801. A date and time at which the server102received the communication data size information during the previous operation and the identification information from, for example, the image forming apparatus101a, is set as the reception date and time802. A total read data size calculated using the number of reads per block and a data size (for example, 512 [Bytes]) of each block included in the communication data size information during the previous operation received from, for example, the image forming apparatus101aby the server102is set as the total read data size803.

A total written data size calculated by using the number of writes per block and a data size (for example, 512 [Bytes]) of each block included in the communication data size information during the previous operation received from, for example, the image forming apparatus101aby the server102is set as the total written data size804. A communication data size obtained by adding a value of the total read data size803and the total written data size804in, for example, the image forming apparatus101atogether is set as the total cumulative communication data size805. A date and time at which a notification was provided to the communication terminal103when the total cumulative communication data size805became greater than the failure prediction threshold value is set as the notification sending date and time806. Information about sizes of communication data of reading and writing of data from and to nonvolatile memory (eMMC) by arithmetic processing units in all of image forming apparatuses monitored by the server102is managed in the operating rate management file800.

Then, the arithmetic processing unit401calculates a total cumulative communication data size (step S703). Specifically, the arithmetic processing unit401obtains a value of the total cumulative communication data size805from the operating rate management file800and adds a communication data size, which is calculated based on the communication data size information during the previous operation obtained in the step S701, to the obtained value of the total cumulative communication data size805. The arithmetic processing unit401also obtains a value of the total read data size803from the operating rate management file800and adds a total read data size, which is calculated based on the communication data size information during the previous operation obtained in the step S701, to the obtained value of the total read data size803. Further, the arithmetic processing unit401obtains a value of the total written data size804from the operating rate management file800and adds a total written data size, which is calculated based on the communication data size information during the previous operation obtained in the step S701, to the obtained value of the total written data size804. Then, the arithmetic processing unit401determines whether or not the total cumulative communication data size calculated in the step S703is greater than the failure prediction threshold value (step S704). The failure prediction threshold value is a value corresponding to 90% of the communication limit data size as described above.

As a result of the determination in the step S704, when the total cumulative communication data size calculated in the step S703is greater than the failure prediction threshold value, the arithmetic processing unit401controls the communication control unit404to send a failure prediction notification to the communication terminal103(step S705). The failure prediction notification includes the identification information received in the step S701and the total cumulative communication data size, the total read data size, and the total written data size calculated in the step S703. After that, the lifetime prediction process is ended. The failure prediction notification enables a serviceperson or operator, who is operating the communication terminal103and remotely monitoring the image forming apparatus101a, to know that the arithmetic processing unit201of the image forming apparatus101ais nearing the end of its life, and replace a module including the arithmetic processing unit201, for example, a printed circuit board on which the arithmetic processing unit201is mounted with a new printed circuit board before the arithmetic processing unit201fails. When the replacement of the printed circuit board is completed, a circuit board replacement completion notification including the identification information about the image forming apparatus101ais sent from the communication terminal103to the server102.

As a result of the determination in the step S704, when the total cumulative communication data size calculated in the step S703is not greater than the failure prediction threshold value, the arithmetic processing unit401updates the operating rate management file800(step S706). Specifically, the arithmetic processing unit401writes the cumulative communication data size, the total read data size, and the total written data size calculated in the step S701over corresponding items in the operating rate management file800. After that, the lifetime prediction process is ended.

FIG.9is a flowchart showing the procedure of a data size reset process that is carried out by the server102inFIG.1. The process inFIG.9is implemented by the arithmetic processing unit401of the server102executing a program loaded from the storage device403to the volatile memory402.

Referring toFIG.9, upon receiving a circuit board replacement completion notification from the communication terminal103(YES in the step S901), the arithmetic processing unit401overwrites a value of the total cumulative communication data size805corresponding to identification information included in the circuit board replacement completion notification in the operating rate management file800with 0 (zero) (step S902). After that, the data size reset process is ended.

According to the first embodiment described above, the lifetime of the arithmetic processing unit201in the image forming apparatus101ais predicted based on the communication data size information received from the image forming apparatus101a. Namely, the lifetime of the arithmetic processing unit201in the image forming apparatus101ais predicted based on a size of communication data of reading and writing of data from and to the nonvolatile memory202by the arithmetic processing unit201. As a result, the lifetime of the arithmetic processing unit201, which carries out communications related to reading and writing of data with the nonvolatile memory202, is accurately predicted.

Moreover, in the first embodiment described above, the arithmetic processing unit201performs the clock gating control. In the clock gating control, as described above, the operating rate of the clock signal A output from the image forming apparatus101adepends on a size of data read from and written to the nonvolatile memory202by the arithmetic processing unit201. By using the operating rate of the clock signal A determined based on this data size, an operating state of the arithmetic processing unit201can be kept track of to accurately predict the lifetime of the arithmetic processing unit201.

Furthermore, in the first embodiment described above, the nonvolatile memory202is an eMMC, and hence the lifetime of a semiconductor device, which carries out communications related to reading and writing of data with the eMMC, is accurately predicted.

In the first embodiment described above, at startup of the image forming apparatus101a, the image forming apparatus101asends the communication data size information during the previous operation of the image forming apparatus101ato the server102. As a result, whenever the image forming apparatus101ais started, the lifetime of the arithmetic processing unit201in the image forming apparatus101ais accurately predicted with consideration given to a previous operating state.

In the first embodiment described above, the server102monitors the lifetimes of respective arithmetic processing units201of a plurality of image forming apparatuses such as the image forming apparatus101aand the image forming apparatus101b. As a result, in a user environment in which the plurality of image forming apparatuses is installed, the lifetime of the arithmetic processing unit201in each image forming apparatus is accurately predicted.

It should be noted that the present invention is not limited to the embodiment described above. For example, the process in the step S703may be carried out by the image forming apparatus101a, and communication data size information including each data size calculated by the image forming apparatus101amay be sent to the server102.

Moreover, in the first embodiment described above, a plurality of nonvolatile memories202may be connected to the PHY215. In this arrangement, a value obtained by totaling sizes of data read from and written to those nonvolatile memories202connected to the PHY215is set as the total cumulative communication data size805in the operating rate management file800.

A description will now be given of an image forming apparatus and a control method therefor according to a second embodiment of the present invention.

The second embodiment is basically the same as the first embodiment described above in terms of its arrangement and effects, and differs from the first embodiment described above in that in the second embodiment, the image forming apparatus101apredicts the lifetime of the arithmetic processing unit201. Therefore, description of arrangements and effects corresponding to those in the first embodiment is omitted, and hence a description will be given below only of arrangements and effects different from those in the first embodiment.

FIG.10is a view schematically showing an arrangement of an information processing system1000according to the second embodiment. Referring toFIG.10, the information processing system1000has the image forming apparatus101aand the communication terminal103. It should be noted that in the present embodiment, the arrangement of the information processing system1000shown inFIG.10is just one example, and the information processing system1000may have a plurality of image forming apparatuses and may have a plurality of communication terminals. The image forming apparatus101ais connected to the communication terminal103via a network1001. The network1001is a WAN or LAN as with the network104and the network105described above. In the network1001, for example, TCP/IP is used as a communication protocol.

In the information processing system1000that does not include the server102, the arithmetic processing unit201of the image forming apparatus101acarries out processes corresponding to the lifetime prediction process and the data size reset process described above. Moreover, in the information processing system1000, an operating rate management file is stored in the nonvolatile memory202of the image forming apparatus101a. It should be noted that in the information processing system1000, there is no need for centralized management of information about a plurality of image forming apparatuses, as is distinct from the server102, because the image forming apparatus101apredicts the lifetime of its own the arithmetic processing unit201. For this reason, the operating rage management file stored in the nonvolatile memory202includes only values, related to the image forming apparatus101a, of the product serial number801, the reception date and time802, the total read data size803, the total written data size804, the total cumulative communication data size805, and the notification sending date and time806.

FIG.11is a flowchart showing the procedure of a communication data size information storage process that is carried out by the image forming apparatus101ain the information processing system1000inFIG.10. The process inFIG.11is implemented by the arithmetic processing unit201executing a program loaded from the nonvolatile memory202to the volatile memory203. As with the communication data size information storage process inFIG.5, the process inFIG.11is carried out when the arithmetic processing unit201has received the shutdown interrupt signal mentioned above.

Referring toFIG.11, the arithmetic processing unit201stands by until it receives the shutdown interrupt signal (step S1101). Upon receiving the shutdown interrupt signal (YES in the step S1101), the arithmetic processing unit201stores the communication data size information mentioned above in the nonvolatile memory202(step S1102). Then, the arithmetic processing unit201causes the communication data size counter214to stop counting, clears a count value indicating a result of counting by the communication data size counter214(step S1103) to end the communication data size information storage process.

FIG.12is a flowchart showing the procedure of a lifetime prediction process that is carried out by the image forming apparatus101ain the information processing system1000inFIG.10. The process inFIG.12is implemented by the arithmetic processing unit201executing a program loaded from the nonvolatile memory202to the volatile memory203. As with the communication data size information sending process inFIG.6, the lifetime prediction process inFIG.12is carried out when the power is started to be supplied to the arithmetic processing unit201and the arithmetic processing unit201ended an initialization process for the eMMC driver (not shown), which controls the nonvolatile memory202, and an initialization process for the file system (not shown). It is assumed that in the lifetime prediction process inFIG.12, the operating rate management file described above is stored beforehand in the nonvolatile memory202.

Referring toFIG.12, the arithmetic processing unit201causes the communication data size counter214to start counting (step S1201). Next, the arithmetic processing unit201obtains the operating rate management file and the communication data size information during the previous operation from the nonvolatile memory202(step S1202). The communication data size information during the previous operation is the communication data size information stored in the nonvolatile memory202in the step S1102described above. Then, the arithmetic processing unit201obtains the identification information about the image forming apparatus101afrom the nonvolatile memory204(step S1203). After that, the arithmetic processing unit201calculates, in a similar manner of step S703, a total cumulative communication data size based on the operating rate management file and the communication data size information during the previous operation obtained in the step S1202(step S1204). The arithmetic processing unit201then determines whether or not the total cumulative communication data size calculated in the step S1204is greater than the failure prediction threshold value mentioned above (step S1205).

As a result of the determination in the step S1205, when the total cumulative communication data size calculated in the step S1204is greater than the failure prediction threshold value, the arithmetic processing unit201controls the communication control unit205to send the failure prediction notification mentioned above to the communication terminal103(step S1206). After that, the lifetime prediction process is ended.

As a result of the determination in the step S1205, when the total cumulative communication data size calculated in the step S1204is not greater than the failure prediction threshold value mentioned above, the arithmetic processing unit201updates the operating rate management file800using the total cumulative communication data size, the total read data size, and the total written data size calculated in the step S1204(step S1207) as with the step S706. After that, the lifetime prediction process is ended.

FIG.13is a flowchart showing the procedure of a data size reset process that is carried out by the image forming apparatus101ain the information processing system1000inFIG.10. The process inFIG.13is implemented by the arithmetic processing unit201executing a program loaded from the nonvolatile memory202to the volatile memory203.

Referring toFIG.13, upon receiving a circuit board replacement completion notification from the communication terminal103(YES in step S1301), the arithmetic processing unit201overwrite a value of the total cumulative communication data size, which corresponds to identification information included in the circuit board replacement completion notification in the operating rate management file800, with 0 (zero) (step S1302). After that, the data size reset process is ended.

In the second embodiment described above, the image forming apparatus101apredicts the lifetime of the arithmetic processing unit201in the image forming apparatus101abased on the calculated total cumulative communication data size. As a result, the lifetime of the arithmetic processing unit201in the image forming apparatus101ais accurately predicted without a server that monitors the lifetime of the arithmetic processing unit201in the image forming apparatus101a.

OTHER EMBODIMENTS

This application claims the benefit of Japanese Patent Application No. 2020-098846, filed Jun. 5, 2020, which is hereby incorporated by reference herein in its entirety.