Display apparatus and gate driving method thereof

A display apparatus and a gate driving method thereof are provided. The display apparatus includes a display panel and a gate driver. The display panel has a plurality of gate lines. Output terminals of the gate driver are coupled to the gate lines in a one-to-one manner. The gate driver is configured to drive the gate lines according to a scrambled scan sequence.

BACKGROUND

Technical Field

The invention relates to an electronic device, and particularly relates to a display apparatus and a gate driving method thereof.

Related Art

FIG. 1is a conventional driving timing schematic diagram of a thin film transistor (TFT) liquid crystal display (LCD). The conventional LCD includes a display panel100. The display panel100is composed of two substrates, and a liquid crystal material is filled there between to form an LCD layer. The display panel100is configured with a plurality of source lines (or referred to as data lines, for example, source lines S(1), S(2), S(3), . . . , S(n−1) and S(n) shown inFIG. 1), a plurality of gate lines (or referred to as scan lines, for example, gate lines G(1), G(2), G(3), G(4) . . . , G(m) shown inFIG. 1), and a plurality of pixel units (for example, pixel units P(1,1), P(1,2), P(1,n−1), P(2,1), P(2,2), P(2,n−1), P(3,1), P(3,2), P(3,n−1), P(m,1), P(m,2) and P(m,n−1) shown inFIG. 1). The source lines S(1)-S(n) are perpendicular to the gate lines G(1)-G(m). The pixel units P(1,1)-P(m,n−1) are arranged on the display panel100in an array. InFIG. 1, an exemplary circuit diagram of the pixel unit P(m,n−1) is illustrated, and other pixel units can be deduced with reference of the pixel unit P(m,n−1).

In the conventional LCD, the gate lines of the LCD panel are generally scanned in a fixed sequence. A gate driver (not shown) can output scan signals to the gate lines G(1)-G(m) of the display panel100, so as to drive the gate lines G(1)-G(m) one-by-one in turns in a fixed sequence. Generally, the gate line G(1) is first driven, and then the gate lines G(2), G(3), . . . etc., are sequentially driven. In collaboration with a scan timing of the gate driver (not shown) on the gate lines G(1)-G(m), a source driver (not shown) can write source driving signals to the pixel units (for example, the pixel units P(1,1), P(1,2), P(1,n−1), P(2,1), P(2,2), P(2,n−1), P(3,1), P(3,2), P(3,n−1), P(m,1), P(m,2) and P(m,n−1) shown inFIG. 1) of the display panel100through the source lines S(1)-S(n) to display an image.

When the conventional LCD displays a specific display pattern, the source driver (not shown) probably consumes a lot of power or even produces a high temperature due to that the source driver frequently and dramatically changes the source driving signals.FIG. 2is a signal waveform diagram of the LCD ofFIG. 1in a certain specific display pattern. A horizontal axis inFIG. 2represents time, Vcom represents a common voltage. It is assumed that the aforementioned specific display pattern is that “gray levels of pixel units in odd rows are 0, and gray levels of pixel units in even rows are 255”. For example, the gray levels of the pixel units P(1,1)-P(1,n−1) of a first row and the pixel units P(3,1)-P(3,n−1) of a third row are 0, and the gray levels of the pixel units P(2,1)-P(2,n−1) of a second row are 255. When the specific display pattern is displayed, as shown inFIG. 2, the source driving signals of the source lines S(1)-S(n) are frequently and dramatically changed, such that the source driver (not shown) probably consumes a lot of power or even produces a high temperature.

According to the driving method of the conventional gate driver (not shown), a fixed sequence is adopted to scan the gate lines of the LCD panel. The driving method of the fixed sequence must have one or a plurality of specific display patterns, such that the source driver (not shown) is liable to have a large power consumption. Under the driving method of the fixed sequence, if the specific display pattern is regularly appeared, the temperature of the source driver (not shown) can be excessively high to cause abnormal image display.

SUMMARY

The invention is directed to a display apparatus and a gate driving method thereof, by which a driving circuit of a display panel is avoided to regularly operate in a large power output.

An embodiment of the invention provides a display apparatus including a display panel and a gate driver. The display panel has a plurality of gate lines. Output terminals of the gate driver are coupled to the gate lines in a one-to-one manner. The gate driver is configured to drive the gate lines according to a scrambled scan sequence.

An embodiment of the invention provides a gate driving method adopted in a display apparatus. The gate driving method includes providing a display panel; and driving a plurality of gate lines of the display panel by a gate driver according to a scrambled scan sequence.

According to the above descriptions, according to the display apparatus and the gate driving method thereof, the scrambled scan sequence is used to drive the gate lines of the display panel. Therefore, the driving circuit of the display panel is avoided to regularly operate in a large power output.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

A term “couple” used in the full text of the disclosure (including the claims) refers to any direct and indirect connections. For example, if a first device is described to be coupled to a second device, it is interpreted as that the first device is directly coupled to the second device, or the first device is indirectly coupled to the second device through other devices or connection means. Moreover, wherever possible, components/members/steps using the same referential numbers in the drawings and description refer to the same or like parts. Components/members/steps using the same referential numbers or using the same terms in different embodiments may cross-refer related descriptions.

FIG. 3is a circuit block schematic diagram of a display apparatus300according to an embodiment of the invention. The display apparatus300includes a display panel100, one or a plurality of gate drivers310, one or a plurality of source drivers320and a timing controller330. The display panel100has a plurality of gate lines (for example, gate lines G(1) and G(m) shown inFIG. 3and a plurality of source lines (for example, source lines S(1) and S(n) shown inFIG. 3), where m and n are integers. The display panel100ofFIG. 3may refer to related description of the display panel100ofFIG. 1, and details thereof are not repeated.

The gate drivers310are coupled between the timing controller330and the display panel100. A plurality of output terminals of the gate drivers310are coupled to the gate lines of the display panel100in a one-to-one manner. After the gate drivers310receive a vertical start signal provided by the timing controller330, the gate drivers310drive the gate lines of the display panel100according to a scrambled scan sequence. The source drivers320are coupled between the timing controller330and the display panel100. In collaboration with the scrambled scan sequence of the gate drivers310, the timing controller330can output corresponding line data (display data, image data) to the source drivers320. The source drivers320convert the received image data into source driving signals, and drive the source lines S(1)-S(n) of the display panel100through the source driving signals. Under control of a source clock signal and a horizontal start signal outputted by the timing controller330, the source drivers320can write the source driving signals into different pixel units of the display panel100in collaboration with scan timing of the gate drivers310, so as to display an image.

For example, the gate drivers310can randomly select the gate lines G(1)-G(m) to decide a scan sequence of the gate lines to drive the display panel100.FIG. 4is a signal timing schematic diagram of the circuit shown inFIG. 3according to an embodiment of the invention. InFIG. 4, a horizontal axis represent time. Referring toFIG. 3andFIG. 4, the gate drivers310drive the gate lines G(1)-G(m) of the display panel100according to a scrambled scan sequence. In collaboration with the scrambled scan sequence of the gate drivers310, the source drivers320can use a scrambled data sequence to output the corresponding source driving signals to the source lines S(1)-S(n).

In some embodiments, the gate drivers310can use a pseudo-random binary sequence (PRBS) to determine the scrambled scan sequence, so as to randomly select the gate lines G(1)-G(m). Implementation of the PRBS is not limited by the invention. In some embodiments, the PRBS can be produced/decided by a conventional PRBS circuit. In some embodiment, the gate drivers310includes a random number table. The gate drivers310can determine the scrambled scan sequence according to the random number table, so as to randomly select the gate lines G(1)-G(m).

In some embodiments, the gate drivers310may use different PRBSs to drive the gate lines G(1)-G(m) of the display panel100in different frames, so as to reduce a chance that the source drivers320are operated in a large power output. For example, the gate drivers310can use a first PRBS to decide the scrambled scan sequence of a first frame period (for example, a front frame F1), so as to drive the gate lines G(1)-G(m) of the display panel100. The gate drivers310can also use a second PRBS different to the first PRBS to decide the scrambled scan sequence of a second frame period (for example, a rear frame F2), so as to drive the gate lines G(1)-G(m) of the display panel100. Therefore, the scan sequence of the gate lines G(1)-G(m) for the front frame F1can be different to the scan sequence of the gate lines G(1)-G(m) for the rear frame F2.

For example,FIG. 5is a signal timing schematic diagram of the circuit shown inFIG. 3according to an application example. InFIG. 5, a horizontal axis represents time. In the application example ofFIG. 5, it is assumed that the number m of the gate lines G(1)-G(m) shown inFIG. 3is 4, and the number n of the source lines S(1)-S(n) is 4. Referring toFIG. 3andFIG. 5, the scrambled scan sequence of the gate driver310for the gate lines G(1)-G(4) in the front frame F1can be 3, 1, 2, 4, and the scrambled scan sequence of the gate driver310for the gate lines G(1)-G(4) in the rear frame F2can be 1, 4, 2, 3. The gate drivers310drive the gate lines G(1)-G(4) of the display panel100according to the scrambled scan sequence. In collaboration with the scrambled scan sequence of the gate drivers310, the source drivers320can use a scrambled data sequence to output the corresponding source driving signals to the source lines S(1)-S(4), as shown inFIG. 5. The gate lines of the display panel100are driven according to the scrambled scan sequence, so that the driving circuit of the display panel100is avoided to regularly operate in a large power output.

In some other embodiments, the gate drivers310may include a first random number table and a second random number table. The gate drivers310may use the first random number table to decide the scrambled scan sequence of the first frame period (for example, the front frame F1), and the gate drivers310may use the second random number table different to the first random number table to decide the scrambled scan sequence of the second frame period (for example, the rear frame F2).

In any circumstances, implementation of the gate driving method of the display apparatus300is not limited toFIG. 5. In some embodiments, the gate lines G(1)-G(m) can be categorized into a plurality of gate line groups GG(1)-GG(k), where k is an integer. The number of the gate lines included in each of the gate line groups can be different. Different gate line groups may have different scan sequences, so as to reduce a chance that the source drivers320operate in the large power output. For example, in some embodiments, the gate drivers310can use one PRBS to arrange a selection sequence of the gate line groups GG(1)-GG(k), and use different PRBSs to drive the gate lines G(1)-G(m) in different selected gate line groups, so as to reduce the chance that the source drivers320operate in the large power output. Implementation of the PRBS is not limited by the present embodiment. In some embodiments, different PRBSs can be determined by using different conventional PRBS circuit.

For example,FIG. 6is a signal timing schematic diagram of the circuit shown inFIG. 3according to another application example. InFIG. 6, a horizontal axis represents time. In the application example ofFIG. 6, it is assumed that the number m of the gate lines G(1)-G(m) shown inFIG. 3is 8, and the number n of the source lines S(1)-S(n) is 8. Referring toFIG. 3andFIG. 6, for example (but is not limited thereto), the gate lines G(1)-G(8) can be categorized into a first gate line group GG(1) and a second gate line group GG(2), where the first gate line group GG(1) includes the gate lines G(1), G(2), G(3) and G(4), and the second gate line group GG(2) includes the gate lines G(5), G(6), G(7) and G(8). The scan sequence for the gate lines of the first gate line group GG(1) can be different to the scan sequence for the gate lines of the second gate line group GG(2). For example (but is not limited thereto), the gate drivers310may use one PRBS to arrange a selection sequence of the gate line groups as GG(2) and GG(1), as shown inFIG. 6. The gate drivers310may use a second PRBS to decide the scrambled scan sequence of the second gate line group GG(2), where the second PRBS can be 1, 4, 2, 3 (i.e. G(5), G(8), G(6), G(7)) or other sequence. The gate drivers310may use a first PRBS different to the second PRBS to decide the scrambled scan sequence of the first gate line group GG(1), where the first PRBS can be 3, 1, 2, 4 (i.e. G(3), G(1), G(2), G(4)) or other sequence. The scrambled scan sequence of the rear frame F2may refer to related description of the front frame F1, as shown inFIG. 6. Since different gate line groups use different scrambled scan sequences in different frames, the chance that the source drivers320operate in the large power output is effectively decreased.

In some other embodiments, the gate drivers310may include a first random number table and a second random number table. The gate drivers310may use the first random number table to decide the scrambled scan sequence of the first gate line group GG(1), and the gate drivers310may use the second random number table different to the first random number table to decide the scrambled scan sequence of the second gate line group GG(2).

In some other embodiments, the timing controller330can detect image data of one frame period to obtain a detection result. According to the detection result, the timing controller330can control the gate drivers310to select one of a “non-scrambled scan sequence” and the “scrambled scan sequence” to drive the gate lines G(1)-G(m). The “non-scrambled scan sequence” can be the scan sequence shown inFIG. 2or other conventional scan sequence. The “scrambled scan sequence” can be the scan sequence shown inFIG. 4,FIG. 5orFIG. 6. For example, when the detection result indicates that the image data is complied with a specific display pattern, the timing controller330can control the gate drivers310to select the “scrambled scan sequence” to drive the gate lines G(1)-G(m). The “specific display pattern” may refer to related description ofFIG. 2, and detail thereof is not repeated. When the detection result indicates that the image data is not complied with the specific display pattern, the timing controller330can control the gate drivers310to select the “non-scrambled scan sequence” to drive the gate lines G(1)-G(m).

In some embodiments, a thermal detector (not shown) can be configured in at least one of the source drivers320, or configured nearby the source drivers320to detect a temperature of the source drivers320. The thermal detector (not shown) reports a detecting result to the timing controller330and/or the gate drivers310, so as to change the scan sequence for cooling down. Therefore, the timing controller330and/or the gate drivers310can get to learn the temperature of the source drivers320. When the temperature of the source drivers320is higher than a certain high-temperature range, the gate drivers310can select the “scrambled scan sequence” to drive the gate lines G(1)-G(m), so as to change the scan sequence for cooling down. When the temperature of the source drivers320is lower than a certain low-temperature range, the gate drivers310can select the “non-scrambled scan sequence” to drive the gate lines G(1)-G(m). The “high-temperature range” and the “low-temperature range” can be determined according to an actual design requirement.

In some other embodiments, the source drivers320can detect power consumption of the source drivers320themselves. The source drivers320can report detecting result to the timing controller330and/or the gate drivers310, so as to change the scan sequence to decrease the power consumption. Therefore, the timing controller330and/or the gate drivers310can get to learn the power consumption of the source drivers320. When the power consumption of the source drivers320is higher than a certain high-power range, the gate drivers310can select the “scrambled scan sequence” to drive the gate lines G(1)-G(m), so as to change the scan sequence to decrease the power consumption. When the power consumption of the source drivers320is lower than a certain low-power range, the gate drivers310can select the “non-scrambled scan sequence” to drive the gate lines G(1)-G(m). The “high-power range” and the “low-power range” can be determined according to an actual design requirement.

In summary, the display apparatus and the gate driving method thereof disclosed by the embodiments of the invention can scramble the scan sequence of the gate lines G(1)-G(m). By scrambling the scan sequence of the gate lines G(1)-G(m), a chance that the source drivers320operate in a large power output is effectively decreased.