Pixel unit, LCD panel, and method for forming the same

The present invention discloses a pixel unit, a liquid crystal display panel and method for forming the same. The liquid crystal display panel comprises a common line, a first shading line, and a second shading line, all of which are under the pixel electrode and are formed by a metallic layer. A lateral side of the first or second shading line, which is not covered by the pixel electrode is a curve edge. The curve first or second shading line expands an area of the common line, resulting in an increase of a storage capacitor. Even if a G/D overlay tolerance exists during the process of forming an LCD panel, a problem of uneven display brightness occurring in the LCD panel is still being improved.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a pixel unit, a liquid crystal display (LCD) panel, and method for forming the same, and more particularly, to a pixel unit, an LCD panel, and method for forming the same for improving the problem of uneven display brightness due to a G/D overlay tolerance between a gate electrode (GE) layer and a source/drain electrode (SD) layer.

2. Description of Prior Art

A monitor with multiple functions is a key element for use in current consumer electronic products. The demand for the novelty and colorful monitors with high resolution, e.g., liquid crystal displays (LCDs), are indispensable components used in various electronic products such as monitors for notebook computers, personal digital assistants (PDAs), digital cameras, and projectors.

While the size of an LCD panel becomes larger, a mura phenomenon due to uneven brightness in a panel occurs more frequently than ever. Currently two main types of forming processes for LCD panels exist: a four-mask process and a five-mask process. The four-mask process has gradually become the mainstream owing to its short production cycle time and high rates of capacity utilization. However, the four-mask process is more complicated in alignment than the five-mask process, so it is more difficult to achieve high standards of production yields now for the four-mask process.

Currently, an LCD panel formed by using a four-mask process undergoes the following steps: At First, a metallic layer on a glass substrate is exposed and etched through a first mask to form a gate electrode (GE) layer of a switch unit. Next, an isolation layer and an active layer are formed on the GE layer. Subsequently, another metallic layer is deposited on the isolation layer and the active layer. At last, the metallic layer is exposed and etched through a second mask to form a source/drain electrode (SD) layer of the switch unit and a data line. Nowadays, the industry primarily utilizes a mask aligner to adopt a so-called mix-and-match approach to enhance capacity utilization. That is to say, while the GE layer and the SD layer are being formed, the metallic layers are exposed by different mask aligners, respectively. But, due to different processes in the utilization of different mask aligners, a tolerance in a G/D overlay between the GE layer and the SD layer tends to occur, causing a local shift in patterns to happen more frequently.

Please refer toFIGS. 1 through 3.FIG. 1andFIG. 2illustrate schematic diagrams of a shift of formed data lines relatively to pixel electrodes.FIG. 3is an equivalent circuit diagram of a combination ofFIG. 1andFIG. 2. For the pixel electrodes14aand14bdisposed on the same scan line11, as shown inFIG. 1, the distance between the data line12band the pixel electrode14bappears left shifted compared with the distance between the data line12aand the pixel electrode14a. So a coupling capacitor Cpd2between the data line12band the pixel electrode14bis larger than a coupling capacitor Cpd1between the data line12aand the pixel electrode14a, as shown inFIG. 3. Although a data voltage which the data line12afeeds into the pixel electrode14ais consistent with a data voltage which the data line12bfeeds into the pixel electrode14b, a charging voltage of the pixel electrode14bis smaller than a charging voltage of the pixel electrode14a, practically, so that the deflection polarity of liquid crystals (LCs) between an LC capacitor Clc1and an LC capacitor Clc2is not consistent. Accordingly, a gray level of the pixel electrode14bis brighter than a gray level of the pixel electrode14a. Relatively, for pixel electrodes14cand14ddisposed on the same scan line11, as shown inFIG. 2, the distance between the data line12dand the pixel electrode14dappears right shifted compared with the distance between the data line12cand the pixel electrode14c. So a coupling capacitor Cpd4between the data line12dand the pixel electrode14dis smaller than a coupling capacitor Cpd3between the data line12cand the pixel electrode14c, as shown inFIG. 3. Although a data voltage which the data line12cfeeds into the pixel electrode14cis consistent with a data voltage which the data line12dfeeds into the pixel electrode14d, a charging voltage of the pixel electrode14dis larger than a charging voltage of the pixel electrode14c, practically, so that the deflection polarity of liquid crystals (LCs) between an LC capacitor Clc3and an LC capacitor Clc4is not consistent. Accordingly, a gray level of the pixel electrode14dis darker than a gray level of the pixel electrode14c. In other words, if the GE layer and the SD layer have a slight tolerance in a G/D overlay, a problem of uneven display brightness may occur in an LCD panel.

It is necessary to consider the following capacitors for each pixel capacitor Cpix: an LC capacitor Clc, a storage capacitor Cs between a pixel electrode14and a common line16, a parasitic capacitor Cgs between a gate and a source of a switch unit, and a coupling capacitor Cpd between a data line and a pixel electrode14. As described above, a G/D overlay tolerance tends to cause a coupling capacitor Cpd to change. Besides, each pixel capacitor Cpix is a sum of the LC capacitor Clc, the storage capacitor Cs, the parasitic capacitor Cgs, and the coupling capacitor Cpd (i.e., Cpix=Clc+Cs+Cgs+Cpd). So, the more a ratio Q of the coupling capacitor Cpd to the pixel capacitor Cpix is, the more uneven display brightness in an LCD panel caused by a G/D overlay tolerance tends to becomes. Therefore, the industry needs to put effort into improving the problem of uneven display brightness due to change in the coupling capacitor Cpd caused by a G/D overlay tolerance.

SUMMARY OF THE INVENTION

In one aspect of the present, a pixel unit electrically connected to a switch unit comprises a pixel electrode, a common line, a first shading line, and a second shading line. A common line under the pixel electrode is used for supplying a common voltage. A first shading line and a second shading line are under the pixel electrode and connected to the common line. At least one lateral side of the first shading line and the second shading line is a curve edge, and the first shading line, the second shading line, and the common line are formed by a metallic layer.

In another aspect of the present, a liquid crystal display panel comprising a switch unit, a pixel electrode electrically connected to the switch unit, a pixel electrode, a common line, a first shading line, and a second shading line. A common line under the pixel electrode is used for supplying a common voltage. A first shading line and a second shading line are under the pixel electrode and connected to the common line. At least one lateral side of the first shading line and the second shading line is a curve edge, and the first shading line, the second shading line, and the common line are formed by a metallic layer.

In still another aspect of the present invention, a method of forming a liquid crystal display panel comprises the steps of: providing a glass substrate; etching a first metallic layer formed on the glass substrate to form a gate of a thin film transistor, a common line, a first shading line, and a second shading line, the first shading line and the second shading line being a curve edge; depositing an isolation layer, an active layer, an ohmic contact layer, and a second metallic layer on the glass substrate and the first metallic layer in sequence; simultaneously etching the active layer, the ohmic contact layer, and the second metallic layer to form an opening on top of the active layer and over the gate and to form a source and a drain of the thin film transistor; depositing a passivation layer on the second metallic layer and the isolation layer; etching the passivation layer to form a via hole over the gate; depositing a transparent conducting layer on the passivation layer and the via hole; and etching the transparent conducting layer to form a pixel electrode connected to the drain.

In yet another aspect of the present invention, a lateral side of the first or second shading line, which is not covered by the pixel electrode is a curve edge.

In yet another aspect of the present invention, a lateral side of the first or second shading line, which is not covered by the pixel electrode, is a triangular-waveform-like edge or a square-waveform-like edge.

In yet another aspect of the present invention, a lateral side of the first or second shading line, which is not covered by the pixel electrode, is asymmetrical to another lateral side of the first or second shading line, which is covered by the pixel electrode.

In contrast to the prior art, when a first metallic layer of the LCD panel in the present invention is etched, a gate of a switch unit, a common line, a first shading line, and a second shading line are formed on the first metallic layer. The common line is electrically connected to the first shading line and the second shading line, so that the first shading line, the second shading line, and the common line all serve as a bottom electrode plate of a storage capacitor simultaneously. The curved first and second shading lines connected to the common line increase not only the area of the bottom electrode plate but also the area of the storage capacitor.

These and other features, aspects and advantages of the present disclosure will become understood with reference to the following description, appended claims and accompanying figures.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Refer toFIG. 4, which is a schematic diagram of a pixel unit50of a LCD panel according to a first embodiment of the present invention. The LCD panel comprises a plurality of pixel units50. Each of the pixel units50comprises a switch unit13and a pixel electrode15. The switch unit13can be a thin-film transistor (TFT) or any other unit having a switch function. When a scan voltage is applied to the switch unit13through a scan line32, a data voltage from a data line30is transmitted to the pixel electrode15through the switch unit13. The voltage difference of the data voltage transmitted to the pixel electrode15determines a rotation direction of LC molecules so as to determine the transmittance of light beams. A first shading line41and a second shading line42are connected to a common line43. The first and second shading lines41and42and the common line43are all formed by the same metallic layer. A process of the formation of the pixel unit50is provided as follows.

Please refer toFIGS. 5 through 8, which illustrate schematic diagrams of forming an LCD panel100with four mask processes according to the present invention. Each of the figures stands for a mask process; that is, the LCD panel100needs to undergo a four-mask process to be finished.

Refer toFIG. 5. During this stage of the process, firstly, a first metallic layer (not shown) is deposited on a glass substrate101. Meanwhile, a developing process is conducted through a first mask. The developing process contains the following steps: coating a photoresist (not shown) on the first metallic layer, exposing the photoresist through the first mask having a specific pattern with a mask aligner, and then washing out the exposed photoresist with a developer. Afterwards, the first metallic layer undergoes an etching process. The etching process includes the steps of removing the first metallic layer which is not covered by the photoresist with a strong acid, forming a gate131of the switch unit13and a bottom electrode plate141on the first metallic layer (roughly showing the specific pattern) covered with the photoresist, and then washing out the residual photoresist. The bottom electrode plate141comprises the common line43, the first shading line41, and the second shading line42(shown inFIG. 4.). Because the gate131is formed during this stage of the process, all elements formed by etching the first metallic layer through the same mask belong to a GE layer.

Refer toFIG. 6. During this stage of the process, firstly, an isolation layer16is deposited. Secondly, an active layer17is deposited. Thirdly, an ohmic layer18is deposited. Finally, a second metallic layer (not shown) is deposited. Subsequently, a developing process is conducted through a second mask. Meanwhile, the active layer17, the ohmic contact layer18, and the second metallic layer undergo an etching process. During this stage of the process, the ohmic contact layer18and the second metallic layer on the top of the gate131are removed, and an opening21and a drain132and a source133of the switch unit13are formed. Because the drain132and the source133are formed during this process, all elements formed by etching the second metallic layer through the same mask belong to a SD layer. It is notified that, the GE layer and the SD layer can be exposed using a single mask aligner or different mask aligners.

Refer toFIG. 7. During this stage of the process, firstly, a passivation layer19is deposited. Next, a developing process is conducted through a third mask. Meanwhile, the passivation layer19undergoes an etching process to form a via20on the source133.

At last, please refer toFIG. 8. During this stage of the process, firstly, a transparent conducting layer is deposited. Next, a developing process is conducted through a fourth mask. Meanwhile, the transparent conducting layer undergoes an etching process to form a pixel electrode15.

Refer toFIG. 4andFIG. 8.FIG. 8is a cross section view along a line from point A to point B to point C inFIG. 4. AsFIG. 8shows, between point A and point B, the gate131of the switch unit13is formed by the first metallic layer (i.e., GE layer), and the drain132and source133of the switch unit13are formed by the second metallic layer (i.e., SD layer). Between point B and point C, the bottom electrode plate141is also formed by the first metallic layer. A storage capacitor Cs is formed by an overlap of the pixel electrode15and the bottom electrode plate141. The first shading line41and the second shading line42are connected to the common line43, so the first and second shading lines41and42and the common line43maintain the same voltage level. Because the first and second shading lines41and42and the common line43maintain the same voltage level, each of them can be regarded as a part of the bottom electrode plate141. Moreover, one lateral side411of the first shading line41and one lateral side421of the second shading line42, both of which are near to the data line30and the data line31, respectively, are a curve edge. Preferably, each of the lateral side411and the lateral side421is an edge with a triangular-waveform-like line, and the lateral side411and the lateral side421are asymmetrical. The bottom electrode plate141comprises the common line43, the shading line41having the curve lateral side411, and the shading line42having the curve lateral side421. The total area of the bottom electrode plate141is larger than that of the combination of the linear shading lines and the common line (as shown inFIG. 1andFIG. 2). The storage capacitor Cs is formed by an overlap of the pixel electrode15and the bottom electrode plate141. Therefore, the larger the area of the bottom electrode plate141is, the higher the capacitance of the storage capacitor Cs becomes.

Refer toFIG. 9andFIG. 10.FIG. 9is a schematic diagram of the pixel unit50of the LCD panel according to a second embodiment of the present invention.FIG. 10is a schematic diagram of the pixel unit50of the LCD panel according to a third embodiment of the present invention. The curve lateral sides411and421are not restricted to be triangular-waveform-like edges. As shown inFIG. 9, the lateral side411of the first shading line41and the lateral side421of the second shading line42display a square-waveform-like edges. As shown inFIG. 10, the lateral side411of the first shading line41and the lateral side421of the second shading line42are undulation-like edges.

With regard to the LCD panel100and method for forming the same of the present invention, the gate131of the switch unit13, the common line43, the first shading line41, and the second shading line42are simultaneously formed when the first metallic layer is etched. The common line43is electrically connected to the first shading line41and the second shading line42, so that the first and second shading lines41and42and the common line43all serve as the bottom electrode plate141of the storage capacitor Cs simultaneously. The shading line41having the curve lateral side411and the shading line42having the curve lateral side421are connected to the pixel electrode15, so the area of the bottom electrode plate141of the storage capacitor Cs is increased, and the storage capacitor Cs is enlarged as well. In sum, because the storage capacitor Cs is enlarged, the ratio Q of the coupling capacitor Cpd to each pixel capacitor Cpix (Cpix=Clc+Cs+Cgs+Cpd) decreases. In other words, even if a G/D overlay tolerance still exists, the ratio Q of each of the pixel unit50tends to be decreased using the first shading line41and the second shading line42electrically connected to the common line43for enlarging the storage capacitor Cs. It represents that the impact of a G/D overlay tolerance on each of the pixel unit50is greatly reduced. Even if a G/D overlay tolerance still exists during the process of forming an LCD panel100, a problem of uneven display brightness occurring in the LCD panel100is still being improved.