Chip package structure

A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a chip package structure. More particularly, the present invention relates to a chip package structure with better reliability.

2. Description of Related Art

Following the increase of input/output contacts of an integrated circuit, chip package technology has become more and more diversified. This is due to the fact that Flip Chip (FC) Interconnect technology minimizes the thickness of the chip package, and reduces signal transmission path, etc. The most common used chip package structures applying the flip chip interconnect technology is, for example, Flip Chip Ball Grid Array (FC/BGA) package and the Flip Chip Pin Grid Array (FC/PGA) package.

Flip chip interconnect technology employs the method of defining area array by disposing a plurality of bonding pads onto the active surface of the chip and forming a plurality of bumps on the bonding pads, respectively. Next, the chip is flipped to connect the bonding bumps of the chip and a plurality of contact pads disposed on a carrier such as a circuit substrate. Therefore, the chip is electrically and mechanically connected to the carrier through the bumps. Further, the chip can be electrically connected to external electronic devices via the internal circuits of the carrier. Generally speaking, the bumps has several types such as the solder bump, the gold bump, the copper bump, the conductive polymer bump, the polymer bump, etc.

FIG. 1is a schematic cross-sectional view showing a flip chip package structure having polymer bumps. Referring toFIG. 1, the flip chip package structure100comprises a substrate110, a plurality of polymer bumps120, a chip130and solder140. The substrate110has a surface110aand a plurality of contact pads112disposed on the surface110a. The chip130has an active surface130aand a plurality of bonding pads132disposed on the active surface130a. The polymer bumps120made of polymer material with conductive property are respectively arranged between the contact pads112and the bonding pads132for electrically connecting the substrate110and the chip130. The surface A of the solder140is adhered to the contact pad112and the surface B of the solder140is adhered to the polymer bump120. Therefore, when external force or thermal stress (not shown) is applied to the flip chip package structure100, the solder140may peel from the contact pads112such that the polymer bumps120can not be electrically connected to the contact pads112. Obviously, the reliability of the flip chip package structure100is lower.

SUMMARY OF THE INVENTION

The present invention is to provide a chip package structure having enhanced reliability.

As embodied and broadly described herein, the present invention provides a chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps. The first B-staged adhesive layer and the second B-staged adhesive layer can be whole layers or patterned layers.

According to an embodiment of the present invention, the bumps may be stud bumps or plating bumps.

According to an embodiment of the present invention, the first B-staged adhesive layer and the second B-staged adhesive layer are non-conductive.

According to an embodiment of the present invention, the first B-staged adhesive layer comprises a plurality of first B-staged adhesive pillars and the second B-staged adhesive layer comprises a plurality of second B-staged adhesive pillars. In an alternative embodiment, the first B-staged adhesive pillars are conductive while the second B-staged adhesive pillars are conductive or non-conductive. In another embodiment, the first B-staged adhesive pillars are non-conductive while the second B-staged adhesive pillars are conductive or non-conductive.

According to an embodiment of the present invention, the first substrate and the second substrate can be both chips.

According to an embodiment of the present invention, one of the first substrate and the second substrate can be a chip.

According to an embodiment of the present invention, the glass transition temperature of the first B-staged adhesive layer may be greater than, equal to or smaller than the glass transition temperature of the second B-staged adhesive layer.

According to an embodiment of the present invention, the chip package structure further comprises a carrier and a plurality of bonding wires. The first substrate and the second substrate are disposed on the carrier, and the first substrate is electrically connected to the carrier through the bonding wires.

According to an embodiment of the present invention, the size of the first B-staged adhesive layer is smaller than the size of the second B-staged adhesive layer. Additionally, the first B-staged adhesive layer may comprise a plurality of first B-staged adhesive pillars.

In summary, the chip package structure of the present invention utilizes a first B-staged adhesive layer and a second B-staged adhesive layer to encapsulate the bumps disposed between the first substrate and the second substrate. When an external force or thermal stress is applied to the chip package structure, the first B-staged adhesive layer and the second B-staged adhesive layer are capable of preventing the bumps from damage, such that reliability of the chip package structure is further enhanced.

DESCRIPTION OF THE EMBODIMENTS

FIG. 2AandFIG. 2Bare schematic cross-sectional views illustrating chip package structures according to an embodiment of the present invention. Referring toFIG. 2AandFIG. 2B, the chip package structure200of the present invention comprises a first substrate210, a second substrate220, a plurality of bumps230, a first B-staged adhesive layer240aand a second B-staged adhesive layer240b. The first substrate210has a plurality of first bonding pads212. The second substrate220has a plurality of second bonding pads222, and the second substrate220is disposed above the first substrate210. The bumps230are disposed between the first substrate210and the second substrate220, wherein each of the first bonding pads212is respectively electrically connected to one of the second bonding pads222via one of the bumps230. The first B-staged adhesive layer240ais adhered on the first substrate210. The second B-staged adhesive layer240bis adhered between the first B-staged adhesive layer240aand the second substrate220, wherein the first B-staged adhesive layer240aand the second B-staged adhesive layer240bencapsulate the bumps230. Additionally, composition of the first B-staged adhesive layer240acan be different from or substantially the same with that of the second B-staged adhesive layer240b. As shown inFIG. 2AandFIG. 2B, the first B-staged adhesive layer240ais adhered on the surface S1of the first substrate210and the second B-staged adhesive layer240bis adhered on the surface S2of the second substrate220. It is noted that the invention utilizes the first B-staged adhesive layer240aand the second B-staged adhesive layer240bto enhance the adhesion between the first substrate210and the second substrate220, such that reliability of the chip package structure200can be enhanced.

As shown inFIG. 2AandFIG. 2B, in the present embodiment, the thickness of the first B-staged adhesive layer240ais substantially equal to the thickness of the second B-staged adhesive layer240b. However, base on actual design requirements, the thickness of the first B-staged adhesive layer240amay also be different from that of the second B-staged adhesive layer240b.

The first substrate210comprises a plurality of first bonding pads212arranged on a surface S1thereof. The second substrate220is arranged above the first substrate210and also comprises a plurality of second bonding pads222arranged on a surface S2thereof. According to the present embodiment, the first substrate210and the second substrate220can be both chips. In another embodiment of the invention, one of the first substrate210and the second substrate220is chip. The types of the first substrate210and the second substrate220are not limited in the present invention. The bumps230are arranged between the first bonding pads212and the second bonding pads222. Specifically, the upper end of each bump230contacts with the second bonding pad222and the lower end of each bump230contacts with the first bonding pads212.

In the present embodiment, the bumps230are stud bumps230a(shown inFIG. 2A), and the stud bumps230acan be gold stud bumps or copper stud bumps. In another embodiment of the present invention, the bumps230may be plating bumps230b(shown inFIG. 2B). The plating bumps230bmay be gold bumps, copper bumps or other conductive bumps. Each of the stud bumps230aor each of the plating bumps230bis encapsulated by one of the adhesive pillars240a′.

According to the present embodiment, the first B-staged adhesive layer240acomprises a plurality of first B-staged adhesive pillars240a′ and the second B-staged adhesive layer240bcomprises a plurality of second B-staged adhesive pillars240b′, wherein the first B-staged adhesive pillars240a′ are adhered on the surface S1of the first substrate210and the second B-staged adhesive pillars240b′ are adhered on the surface S2of the second substrate220. In the present embodiment, the first B-staged adhesive pillars240a′ are conductive or non-conductive while the second B-staged adhesive pillars240b′ are conductive or non-conductive. Since the first B-staged adhesive pillars240a′ are electrically insulated from one another and the second B-staged adhesive pillars240b′ are electrically insulated from one another, the short circuit between the bumps230can be prevented even though the first B-staged adhesive pillars240a′ and the second B-staged adhesive pillars240b′ are both conductive.

In the present embodiment, the first B-staged adhesive layer240aand the second B-staged adhesive layer240bcan be obtained from 8008 or 8008HT of ABLESTIK, and the glass transition temperature of which is between about 80° C. and about 300° C. Additionally, the first B-staged adhesive layer240aand the second B-staged adhesive layer240bcan also be obtained from 6200, 6201 or 6202C of ABLESTIK or obtained from SA-200-6, SA-200-10 provided by HITACHI Chemical CO., Ltd., and the glass transition temperature of which is between about −40° C. and about 150° C. The glass transition temperature of the first B-staged adhesive layer240ais greater than, equal to or smaller than the glass transition temperature of the second B-staged adhesive layer240b. Additionally, some conductive particles (e.g. silver particles, copper particles, gold particles) are doped in the first B-staged adhesive layer240aand the second B-staged adhesive layer240b, for example.

FIG. 3AtoFIG. 3Dare schematic cross-sectional views illustrating chip package structures according to another embodiment of the present invention. Referring toFIG. 3AandFIG. 3B, the chip package structure200′ of the present embodiment is similar to the chip package structure200shown inFIG. 2AandFIG. 2Bexcept that the first B-staged adhesive layer240aand the second B-staged adhesive layer240bentirely fill the gaps between the bumps230. Specifically, the first B-staged adhesive layer240aand the second B-staged adhesive layer240bare both non-conductive so as to prevent short circuit between the bumps230.

Referring toFIG. 3C, the chip package structure200″ of the present embodiment is similar to the chip package structure200′ shown inFIG. 3Aexcept that the size D2of the first B-staged adhesive layer240ais different from the size D2of the second B-staged adhesive layer240b. As shown inFIG. 3C, the size D1of the first B-staged adhesive layer240ais smaller than the size D2of the second B-staged adhesive layer240bsuch that a portion area of the first substrate210is exposed by the first B-staged adhesive layer240a. The first B-staged adhesive layer240aentirely covers the surface S1of the first substrate210except areas occupied by the bumps230, and the second B staged adhesive layer240bexposes peripheral region of the surface S2of the second substrate220.

Referring toFIG. 3D, the chip package structure200″′ of the present embodiment is similar to the chip package structure200″ shown inFIG. 3Cexcept that the first B-staged adhesive layer240acomprises a plurality of first B-staged adhesive pillars240a′.

FIG. 4is a schematic cross-sectional view illustrating a stacked-type chip package structure according to an embodiment of the present invention. Referring toFIG. 4, the stacked-type chip package structure400comprises a carrier410, a first chip210′, a second chip220′, a plurality of bumps230, a first B-staged adhesive layer240a, a second B-staged adhesive layer240band a plurality of bonding wires420. The arrangement of the first chip210′, the second chip220′, the bumps230, the first B-staged adhesive pillars240a′ and the second B-staged adhesive pillars240b′ is substantially the same with the arrangement as shown inFIG. 2AorFIG. 2B. In the present embodiment, the first chip210′ is bonded to the carrier410through an adhesive layer430(e.g. epoxy, silver paste, DAF, and so on), and is electrically connected to the carrier410via the bonding wires420. The carrier410such as the printed circuit board (PCB). The PCB may be FR4, FR5, BT, PI circuit substrate. Specifically, the first chip210′ has wire bonding pads214electrically connected to the carrier410via the bonding wires420.

FIGS. 5-7are schematic cross-sectional views illustrating stacked-type chip package structures according to various embodiments of the present invention. Referring toFIG. 5, the stacked-type chip package structure400acomprises a carrier410, a first chip210′, a second chip220′, a plurality of bumps230, a first B-staged adhesive layer240a, a second B-staged adhesive layer240band a plurality of bonding wires420. The arrangement of the first chip210′, the second chip220′, the bumps230, the first B-staged adhesive layer240aand the second B-staged adhesive layer240bis substantially the same with the arrangement as shown inFIG. 3AorFIG. 3B. The first chip210′ is bonded to the carrier410through an adhesive layer430(e.g. epoxy, silver paste, DAF, and so on), and is electrically connected to the carrier410via the bonding wires420. Specifically, the first chip210′ has wire bonding pads214electrically connected to the carrier410via the bonding wires420. An end of the bonding wires420connected to the wire bonding pads214is encapsulated by the first B-staged adhesive layer240a. The stand-off between the first chip210′ and the second chip220′ is maintained by at least one of the first B-staged adhesive layer240aand the second B-staged adhesive layer240b, such that the bonding wires420can be protected from damage.

Referring toFIG. 6andFIG. 7, in the stacked-type chip package structure400band400c, the arrangement of the first chip210′, the second chip220′, the bumps230, the first B-staged adhesive layer240aand the second B-staged adhesive layer240bmay also be the same as or similar with the above-mentioned embodiments shown inFIG. 3CandFIG. 3D. As shown inFIG. 6andFIG. 7, wire bonding pads214of the first chip210′ are exposed by the first B-staged adhesive layer240aor the first B-staged adhesive pillars240a′ such that the bonding wires420are not encapsulated by the first B-staged adhesive layer240aor the first B-staged adhesive pillars240a′.