Failsafe display of frame locked graphics

The invention describes a system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input vertical refresh rate and displays the image data at a vertical refresh rate that is a predetermined fraction of the input vertical refresh rate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a system adapted to visually display digital image data and, more particularly, to a system including a failsafe mechanism adapted to visually display digital image data and a method therefor.

2. Description of the Prior Art

Digital image data is input to a system adapted to visually display digital image data on a display device. Digital image data is input to a frame locked system one frame at a time at a vertical refresh or frame rate. A frame is an image displayed for viewing on a display device or panel at one time, i.e., one frame of data fits on the display device screen or panel. Each frame includes a rectangular array of pixels. Each pixel has one or more values, for example, a gray scale luminance value for a monochrome display or red, green, and blue (RGB) luminance values for a color display. The resolution of the array, i.e., the number of horizontal and vertical pixels, is often referred to as an image frame resolution. Common display frame resolutions include that shown in Table 1 indicating, in the second and third columns, the number of pixels in the vertical and horizontal dimensions, respectively:

Display monitors must be refreshed many times per second. The refresh rate for a display device is measured in hertz (Hz) and is also called the vertical refresh rate, vertical frequency, vertical scan rate, or frame rate. Put differently, digital image data is input at an input frame rate. An input vertical refresh or frame rate is the rate at which a frame of data is received by the system. A display vertical refresh rate is the rate at which digital image data is provided to a display device for visually displaying the input image data. Common input and display vertical refresh rates include 60, 75, and 85 Hz and the like.

Where the display vertical refresh rate and/or resolution match the input vertical refresh rate and/or resolution, the frame of image data is displayed directly without issue. If, however, the input and display vertical refresh rates and/or the resolutions differ substantially, the image data might not be properly displayed on the display device. This is particularly true in frame locked systems where small line memories are commonplace since these line memories do not allow for full conversion of the input vertical refresh rate to a vertical refresh rate that matches the display vertical refresh rate.

When the input and display vertical refresh rates differ, the display device and, more particularly, the software that drives the display device might enter an unrecoverable error mode. For example, assume UXGA image data input at 85 Hz and a VGA display running at 60 Hz. In this circumstance, the system is incapable of displaying the image data. The VGA display device might go blank except perhaps for a single line error message that reads SYNCH ERROR or OUT OF RANGE.

A system reset will not generally cure the error because the system will continue to deliver image data at a display vertical refresh rate and/or resolution that exceeds the capability of the display device. The software and/or hardware driving the display device will not give a perplexed user a way of changing its settings to ensure the error does not recur.

Accordingly, a need remains for a system including a failsafe mechanism adapted to visually display digital image data and a method therefor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring toFIG. 1, an embodiment of a system100for visually displaying digital images includes an analog-to-digital (ADC) converter or phase locked loop (PLL) circuit108for receiving an RGB analog input signal104from an image source (not shown). The ADC/PLL circuit108converts the analog input signal to digital image data118and provides the image data118to the display controller102. Likewise, a video decoder110receives an analog video input106from an analog video source (not shown). The video decoder110converts the analog video input to digital image data118and provides the image data118to the display controller102. A person of reasonable skill in the art should recognize that the image data118might be encoded in a variety of formats. All manner of encoding a digital image comes within the scope of the invention including RGB signals using 8, 6, or 4-bit luminance, red chroma, blue chroma (YCRB), and the like.

Display controller102processes image data118to generate display data120. Display controller102provides the display data120to the display116. Clocks112synchronize the display controller102. The system100optionally includes memory114. Memory114couples to the display controller102and stores bitmaps, scalar coefficients, and the like. In one embodiment, memory102includes read-only and random access type memories (not shown). ADC/PLL circuit108, video decoder circuit110, clocks112, and memory114are well known to a person of reasonable skill in the art and will not be explained in further detail.

Referring toFIG. 2, a display controller200provides data220to a display216. Image data218includes data220and an input vertical refresh or frame rate204. Examples of the input vertical refresh rate204are 60, 75, 85 Hz, and the like.

The display216is any device capable of displaying data220. The data220might, for example, be encoded in RGB signals (not shown) but the invention is not limited in this regard. The display216might be, for example, a pixelated display that has a fixed pixel structure. Examples of pixelated displays are a liquid crystal display (LCD) projector, flat panel monitor, plasma display (PDP), field emissive display (FED), electro-luminescent (EL) display, micro-mirror technology display, and the like.

The display216is capable of displaying data220up to a display vertical refresh rate208. Examples of the display vertical refresh rate208are 60, 75, 85 Hz, and the like. Referring additionally toFIG. 5, the display216properly displays the data220when the input vertical refresh rate204equals or is less than the display vertical refresh rate208. As shown inFIG. 5, one input vertical refresh rate pulse502exists for every display vertical refresh pulse504. The display216, therefore, includes a vertical active time (not shown) that approximately matches the input vertical active time (not shown). As mentioned earlier, the display216is incapable of displaying the image data218when the input vertical refresh rate204exceeds the display vertical refresh rate208.

The controller200includes an enable circuit206. The enable circuit206compares the input vertical refresh rate204with the display vertical refresh rate208. The enable circuit206asserts an enable signal214when the input vertical refresh rate204exceeds the display vertical refresh rate208. A person of reasonable skill in the art should recognize that the enable circuit206might be implemented in a variety of manners including software and hardware, all encompassed within the scope of the present invention.

The failsafe circuit202generates an internal vertical refresh rate210by manipulating the input vertical refresh rate204responsive to the enable signal214. The failsafe circuit202generates the internal vertical refresh rate210to be less than the input vertical refresh rate204. The internal vertical refresh rate210, for example, is a predetermined fraction, i.e., ¼, ⅓, ½, and the like, of the input vertical refresh rate204. The failsafe circuit202provides the internal vertical refresh rate210to the display216. The display216, in turn, uses the internal vertical refresh rate210to synchronize its display of the data220. By doing so, the failsafe circuit202allows for the display of a useful image, at full color depth, when the input refresh rate204exceeds the capability of the display216. That is, when the input vertical refresh rate204is greater than the display vertical refresh rate208.

FIG. 3is a schematic diagram of an embodiment of the failsafe circuit202shown inFIG. 2. Referring toFIG. 3, a failsafe circuit300includes a flip flop302, an inverter304, an AND gate306, and a multiplexer308. The flip-flop302generates a signal VSEN responsive to the input vertical refresh rate signal VSYNCIN. The flip-flop302receives the input vertical refresh rate signal VSYNCIN at its clock input. The inverter304inverts the signal VSEN and provides it to an input terminal of the flip-flop302. The AND gate306logically manipulates the signal VSEN and the internal vertical refresh rate signal VSYNCIN to thereby generate the internal vertical refresh rate signal VSYNCINTERNAL. The AND gate306provides the internal vertical refresh rate signal VSYNCINTERNAL to the multiplexer308that, in turn, outputs the VSYNCINTERNAL signal responsive to the FAILSAFE ENABLE signal.

FIG. 4is a timing diagram of an embodiment of the signals associated with the failsafe circuit300shown inFIG. 3.FIG. 6is a timing diagram of the input vertical refresh rate and data and the internal vertical refresh rate and display data according to an embodiment of the failsafe circuit shown inFIG. 3. As shown inFIGS. 4 and 6, two input vertical refresh rate pulses402and602exist for every internal vertical refresh rate pulse404and604, respectively. Put differently, the internal vertical refresh rate210(FIG. 2) is half the input vertical refresh rate204(FIG. 2) with the resulting output image being vertically compressed relative to the received image data218and filling a corresponding fraction, e.g., approximately ½, of the display216. Thus, the display216includes a vertical active time approximately equal to two input vertical active times as shown by the shaded lines inFIG. 6.

A line memory222together with a scalar circuit224might further improve the size and/or quality of the image displayed on the display216. Embodiments of the scalar circuit224include circuits that scale the image in a variety of manners including simple, temporal, and/or spatial interpolation, digital signal processing techniques, and/or using filters such as those described in U.S. Pat. No. 6,339,434 to West, herein incorporated by reference. The line memory222and scalar circuit are well known to a person of reasonable skill in the art and will not be discussed in further detail.

Since a plurality of input frames are displayed during one output frame, the failsafe circuit shown inFIG. 2includes the following several possible display modes:

Display first—display the first input frame and discard other input frames received during a single output frame, for example, by filling the second input frame with black (where the internal refresh rate is half the input refresh rate). This mode is shown inFIG. 6.

Display last—display the last input frame and discard other input frames received during a single output frame, for example, by filling the first received input frames with black.

Display all—display both the input and output frames in a single output frame. In this case, the display216will show, for example, two half-height images where the internal vertical refresh rate210is half the input vertical refresh rate204.

A person of reasonable skill in the art should recognize that other display modes are possible depending on the chosen relationship between the input and internal vertical refresh rates204and210, respectively.

A person skilled in the art should recognize that the system provided above receives a color image represented by RGB signals at the input vertical refresh rate and generates an internal vertical refresh rate used by the display216to synchronize its display of the data220. The display216, therefore, vertically compresses data220. By doing so, the user (not shown) avoids an irrecoverable error mode and has the opportunity to change the settings on the display system such that the input vertical refresh rate does not exceed the capabilities of the display, that is, does not exceed the display vertical refresh rate thereby ensuring that the display is capable of displaying a full color version of the image input.

An embodiment of the failsafe circuit202shown inFIG. 2is integrated into a monolithic integrated circuit. Alternatively, any number of discrete logic and other components might implement the invention. A dedicated processor system that includes a microcontroller or a microprocessor might alternatively implement the present invention.

The invention additionally provides methods, which are described below. The invention provides apparatus that performs or assists in performing the methods of the invention. This apparatus might be specially constructed for the required purposes or it might comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. The methods and algorithms presented herein are not necessarily inherently related to any particular computer or other apparatus. In particular, various general-purpose machines might be used with programs in accordance with the teachings herein or it might prove more convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these machines will appear from this description.

Useful machines or articles for performing the operations of the present invention include general-purpose digital computers or other similar devices. In all cases, there should be borne in mind the distinction between the method of operating a computer and the method of computation itself. The present invention relates also to method steps for operating a computer and for processing electrical or other physical signals to generate other desired physical signals.

The invention additionally provides a program and a method of operation of the program. The program is most advantageously implemented as a program for a computing machine, such as a general-purpose computer, a special purpose computer, a microprocessor, and the like.

The invention also provides a storage medium that has the program of the invention stored thereon. The storage medium is a computer-readable medium, such as a memory, and is read by the computing machine mentioned above.

This detailed description is presented largely in terms of block diagrams, timing diagrams, flowcharts, display images, algorithms, and symbolic representations of operations of data bits within a computer readable medium, such as a memory. Such descriptions and representations are the type of convenient labels used by those skilled in programming and/or the data processing arts to effectively convey the substance of their work to others skilled in the art. A person skilled in the art of programming may use this description to readily generate specific instructions for implementing a program according to the present invention.

Often, for the sake of convenience only, it is preferred to implement and describe a program as various interconnected distinct software modules or features, collectively also known as software. This is not necessary, however, and there may be cases where modules are equivalently aggregated into a single program with unclear boundaries. In any event, the software modules or features of the present invention may be implemented by themselves, or in combination with others. Even though it is said that the program may be stored in a computer-readable medium, it should be clear to a person skilled in the art that it need not be a single memory, or even a single machine. Various portions, modules or features of it may reside in separate memories or separate machines where the memories or machines reside in the same or different geographic location. Where the memories or machines are in different geographic locations, they may be connected directly or through a network such as a local access network (LAN) or a global computer network like the Internet®.

In the present case, methods of the invention are implemented by machine operations. In other words, embodiments of the program of the invention are made such that they perform methods of the invention that are described in this document. These may be optionally performed in conjunction with one or more human operators performing some, but not all of them. As per the above, the users need not be collocated with each other, but each only with a machine that houses a portion of the program. Alternately, some of these machines may operate automatically, without users and/or independently from each other.

Methods of the invention are now described. A person having ordinary skill in the art should recognize that the boxes described below may be implemented in different combinations, and in different order. Some methods may be used for determining a location of an object, some to determine an identity of an object, and some both.

FIG. 7is a flowchart of an embodiment of the method of failsafe display700according to the present invention. Referring toFIG. 7, the method700compares the input vertical refresh rate with the display vertical refresh rate at702. If the input vertical refresh rate does not exceed the display vertical refresh rate (704), the method700displays data without issue using the input vertical refresh rate (706). If the input vertical refresh rate exceeds the display vertical refresh rate, the method700generates an enable signal (708) and an internal vertical refresh rate (710). The internal vertical refresh rate is generated as described above with reference toFIGS. 2-6and is, in one embodiment, a predetermined fraction of the input vertical refresh rate. The method700displays the data synchronized using the internal vertical refresh rate (712). By doing so, the method displays the data vertically compressed relative to the data received. At714, the method allows a user to change the settings of his system to adjust to the input vertical refresh rate.

Having illustrated and described the principles of my invention in a preferred embodiment thereof, it should be readily apparent to those skilled in the art that the invention20can be modified in arrangement and detail without departing from such principles. I claim all modifications coming within the spirit and scope of the accompanying claims.