Uninterruptible power supply apparatus

A control device of an uninterruptible power supply apparatus turns on a first switch and a second switch and turns off a third switch in an inverter power feed mode, turns on the first and third switches and turns off the second switch in a bypass power feed mode, and executes a lap power feed mode of turning off the first switch and turning on the second and third switches in a switching period in which one mode of the inverter power feed mode and the bypass power feed mode is switched to the other mode.

TECHNICAL FIELD

The present invention relates to an uninterruptible power supply apparatus, and more particularly to an uninterruptible power supply apparatus having an inverter power feed mode in which AC power is supplied from an inverter to a load, a bypass power feed mode in which AC power is supplied from a bypass AC power supply to the load, and a lap power feed mode in which AC power is supplied from both of the inverter and the bypass AC power supply to the load.

BACKGROUND ART

For example, WO2017/017719 (PTL 1) discloses an uninterruptible power supply apparatus having an inverter power feed mode, a bypass power feed mode, and a lap power feed mode. This uninterruptible power supply apparatus includes a converter configured to convert AC voltage supplied from a commercial AC power supply to DC voltage, a capacitor configured to smooth DC output voltage from the converter, an inverter configured to convert terminal-to-terminal voltage of the capacitor to AC voltage, a first switch having one terminal receiving AC output voltage of the inverter and the other terminal connected to a load, and a second switch having one terminal receiving AC voltage supplied from a bypass AC power supply and the other terminal connected to the load.

In the inverter power feed mode, the first switch is turned on and the second switch is turned off. In the bypass power feed mode, the second switch is turned on and the first switch is turned off. In the lap power feed mode, both the first and second switches are turned on. In the lap power feed mode, a switching period of switching between the inverter power feed mode and the bypass power feed mode is executed.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

Unfortunately, in the conventional uninterruptible power supply apparatus, the commercial AC power supply and the bypass AC power supply each include a three phase AC power supply star-connected to a neutral point, and when both of the neutral points of the commercial AC power supply and the bypass AC power supply are grounded, circulating current may flow from one AC power supply of the commercial AC power supply and the bypass AC power supply to the other AC power supply through the capacitor in the lap power feed mode (seeFIG. 6,FIG. 7). If a large circulating current flows, overcurrent is detected, or overvoltage of the capacitor is detected, so that the operation of the uninterruptible power supply apparatus is stopped, and the operation of the load is stopped.

A main object of the present invention is therefore to provide an uninterruptible power supply apparatus capable of preventing circulating current from flowing even when the neutral points of the first and second AC power supplies are grounded.

Solution to Problem

An uninterruptible power supply apparatus according to the present invention includes a forward converter, a capacitor, a reverse converter, a bidirectional chopper, a first switch, a second switch, a third switch, a first control unit, and a second control unit. The forward converter converts three phase AC voltage to DC voltage. The capacitor smooths DC output voltage of the forward converter. The reverse converter converts terminal-to-terminal voltage of the capacitor to three phase AC voltage. The bidirectional chopper exchanges DC power between the capacitor and a power storage device.

The first switch is disposed corresponding to each phase of three phase AC voltage supplied from a first AC power supply and has one terminal receiving AC voltage of a corresponding phase and another terminal connected to the forward converter. The second switch is disposed corresponding to each phase of three phase AC voltage supplied from the reverse converter and has one terminal receiving AC voltage of a corresponding phase and another terminal connected to a load. The third switch is disposed corresponding to each phase of three phase AC voltage supplied from a second AC power supply and has one terminal receiving AC voltage of a corresponding phase and another terminal connected to the load.

The first control unit is configured to turn on the first and second switches and turn off the third switch in a first mode of supplying three phase AC voltage from the reverse converter to the load, to turn on the first and third switches and turn off the second switch in a second mode of supplying three phase AC voltage from the second AC power supply to the load, and to turn off the first switch and turn on the second and third switches and execute a third mode of supplying three phase AC voltage from both of the reverse converter and the second AC power supply to the load in a switching period in which one mode of the first and second modes is switched to another mode.

The second control unit is configured to control the reverse converter in synchronization with three phase AC voltage supplied from the second AC power supply, to control the forward converter such that terminal-to-terminal voltage of the capacitor becomes a first reference voltage and control the bidirectional chopper such that terminal-to-terminal voltage of the power storage device becomes a second reference voltage, in the first and second modes, and to stop operation of the forward converter and control the bidirectional chopper such that terminal-to-terminal voltage of the capacitor becomes a third reference voltage, in the switching period.

Advantageous Effects of Invention

In the uninterruptible power supply apparatus according to the present invention, in the switching period in which the first mode and the second mode are switched, the first switch is turned off to electrically isolate the first AC power supply from the forward converter. This can prevent circulating current from flowing even when both of the neutral points of the first and second AC power supplies are grounded.

DESCRIPTION OF EMBODIMENTS

First Embodiment

FIG. 1is a circuit block diagram showing a configuration of an uninterruptible power supply apparatus according to a first embodiment of the present invention. InFIG. 1, this uninterruptible power supply apparatus includes switches S1to S9, capacitors C1to C6and Cd, reactors L1to L6, current detectors CT1to CT6, a converter1, a DC positive bus Lp, a DC negative bus Ln, a bidirectional chopper2, an inverter3, an operation unit4, and a control device5.

This uninterruptible power supply apparatus receives three phase AC power with a commercial frequency from a commercial AC power supply6and a bypass AC power supply7and supplies three phase AC power with a commercial frequency to a load8. Commercial AC power supply6outputs three phase AC voltages Vu1, Vv1, and Vw1to AC output terminals6ato6c, respectively. A neutral point terminal6dof commercial AC power supply6receives ground voltage GND.

Instantaneous values of three phase AC voltages Vu1, Vv1, and Vw1are detected by control device5. Control device5detects whether a power failure of commercial AC power supply6has occurred, based on AC output voltages Vu1, Vv1, and Vw1of commercial AC power supply6.

Bypass AC power supply7outputs three phase AC voltages Vu2, Vv2, and Vw2to AC output terminals7ato7c, respectively. A neutral point terminal7dof bypass AC power supply7receives ground voltage GND. Instantaneous values of three phase AC voltages Vu2, Vv2, and Vw2are detected by control device5. AC input terminals8ato8cof load8receive three phase AC voltage from the uninterruptible power supply apparatus. Load8is driven by three phase AC power supplied from the uninterruptible power supply apparatus.

One terminal of each of switches S1to S3is connected to the corresponding one of AC output terminals6ato6cof commercial AC power supply6. Capacitor C1to C3each have one electrode connected to the other terminal of the corresponding one of switches S1to S3and have the other electrodes connected to each other. Reactors L1to L3each have one terminal connected to the other terminal of the corresponding one of switches S1to S3and have the other terminals connected to three input nodes of converter1.

Switches S1to S6are controlled by control device5. In an inverter power feed mode (first power feed mode) in which three phase AC power generated by inverter3is supplied to load8, control device5turns on switches S1to S6and turns off switches S7to S9. In a bypass power feed mode (second power feed mode) in which three phase AC power from bypass AC power supply7is supplied to load8, control device5turns on switches S1to S3and S7to S9and turns off switches S4to S6. In a switching period in which one power feed mode of the inverter power feed mode and the bypass power feed mode is switched to the other power feed mode, the control device5turns off switches S1to S3to electrically isolate commercial AC power supply6from converter1.

Capacitors C1to C3and reactors L1to L3constitute an AC filter F1. AC filter F1is a low pass filter, allows AC current with a commercial frequency to flow from commercial AC power supply6to converter1, and prevents a signal with a switching frequency from flowing from converter1to commercial AC power supply6. Current detectors CT1to CT3detect AC currents I1to I3flowing through reactors L1to L3, respectively, and apply a signal indicating a detected value to control device5.

The positive-side output node of converter1is connected to the positive-side input node of inverter3through DC positive bus Lp. The negative-side output node of converter1is connected to the negative-side input node of inverter3through DC negative bus Ln. Capacitor Cd is connected between buses Lp and Ln and smooths DC voltage VDC between buses Lp and Ln. An instantaneous value of DC voltage VDC is detected by control device5.

Converter1is controlled by control device5and converts three phase AC power from commercial AC power supply6to DC power when three phase AC power is supplied normally from commercial AC power supply6(in a sound state of commercial AC power supply6). DC power generated by converter1is supplied to bidirectional chopper2and inverter3through buses Lp and Ln.

In a sound state of commercial AC power supply6, control device5controls converter1such that terminal-to-terminal voltage VDC of capacitor Cd becomes reference voltage VDCr1(first reference voltage), based on AC output voltages Vu1, Vv1, and Vw1of commercial AC power supply6, AC currents I1to I3, and terminal-to-terminal voltage VDC of capacitor Cd. When supply of three phase AC power from commercial AC power supply6is stopped (at the time of a power failure of commercial AC power supply6), control device5stops the operation of converter1.

In a switching period in which one power feed mode of the inverter power feed mode and the bypass power feed mode is switched to the other power feed mode, control device5stops the operation of converter1. AC filter F1and converter1constitute a forward converter that converts three phase AC power from commercial AC power supply6to DC power.

Bidirectional chopper2is controlled by control device5, stores DC power generated by converter1into battery9in a sound state of commercial AC power supply6, and supplies DC power in battery9to inverter3through buses Lp and Ln in response to occurrence of a power failure of commercial AC power supply6. An instantaneous value of terminal-to-terminal voltage VB of battery9is detected by control device5.

Control device5controls bidirectional chopper2, based on terminal-to-terminal voltage VDC of capacitor Cd and terminal-to-terminal voltage VB of battery9. In a sound state of commercial AC power supply6, control device5controls bidirectional chopper2such that terminal-to-terminal voltage VB of battery9becomes reference voltage VBr (second reference voltage). At the time of a power failure of commercial AC power supply6, control device5controls bidirectional chopper2such that terminal-to-terminal voltage VDC of capacitor Cd becomes reference voltage VDCr2(third reference voltage).

In the switching period in which one power feed mode of the inverter power feed mode and the bypass power feed mode is switched to the other power feed mode, control device5controls bidirectional chopper2such that terminal-to-terminal voltage VDC of capacitor Cd becomes reference voltage VDCr2. It is noted that VBr<VDC2r<VDC1. VDCr2is a voltage slightly lower than VDCr1.

Inverter3is controlled by control device5and converts DC power supplied from converter1and bidirectional chopper2to three phase AC power with a commercial frequency. Each of three output nodes of inverter3is connected to one terminal of the corresponding one of reactors L4to L6. The other terminal of each of reactors L4to L6is connected to one terminal of the corresponding one of switches S4to S6, and the other terminals of switches S4to S6are respectively connected to three AC input terminals8ato8cof load8. One electrode of each of capacitors C4to C6is connected to the other terminal of the corresponding one of reactors L4to L6, and the other electrodes of capacitors C4to C6are connected together to the other electrodes of capacitors C1to C3.

Capacitors C4to C6and reactors L4to L6constitute an AC filter F2. AC filter F2is a low pass filter, allows AC current with a commercial frequency to flow from inverter3to load8, and prevents a signal with a switching frequency from flowing from inverter3to load8. In other words, AC filter F2converts three phase rectangular wave voltage output from inverter3to sinusoidal three phase AC voltages Va, Vb, and Vc.

Instantaneous values of three phase AC voltages Va to Vc are detected by control device5. Current detectors CT4to CT6detect AC currents I4to I6flowing through reactors L4to L6, respectively, and apply a signal indicating a detected value to control device5.

Control device5controls inverter3such that AC output voltages Va to Vc become AC output voltages Vu2, Vv2, and Vw2, respectively, based on AC output voltages Va to Vc of inverter3, AC output voltages Vu2, Vv2, and Vw2of bypass AC power supply7, and AC currents I4to I6.

Switches S7to S9each have one terminal connected to the corresponding one of AC output terminals7ato7cof bypass AC power supply7and have the other terminals respectively connected to AC input terminals8ato8cof load8. Switches S7to S9are controlled by control device5and are turned off in the inverter power feed mode and turned on in the bypass power feed mode and the lap power feed mode.

Operation unit4(selector) includes a plurality of buttons operated by a user of the uninterruptible power supply apparatus and an image display unit presenting a variety of information. The user can operate operation unit4to power on and off the uninterruptible power supply apparatus and select one mode of the automatic operation mode, the bypass power feed mode, and the inverter power feed mode.

Control device5controls the entire uninterruptible power supply apparatus based on a signal from operation unit4, AC output voltages Vu1, Vv1, and Vw1of commercial AC power supply6, AC input currents I1to I3, terminal-to-terminal voltage VDC of capacitor Cd, terminal-to-terminal voltage VB of battery9, AC output currents I4to I6, AC output voltages Va to Vc, and AC output voltages Vu2, Vv2, and Vw2of bypass AC power supply7, and the like.

The operation of this uninterruptible power supply apparatus will now be described briefly. When the automatic operation mode is selected using operation unit4in a sound state of commercial AC power supply6, switches S1to S3are turned on so that commercial AC power supply6is connected to converter1through AC filter F1, switches S4to S6are turned on so that inverter3is connected to load8through AC filter F2, and switches S7to S9are turned off so that bypass AC power supply7is electrically isolated from load8.

Converter1is controlled such that terminal-to-terminal voltage VDC of capacitor Cd becomes reference voltage VDCr1, bidirectional chopper2is controlled such that terminal-to-terminal voltage VB of battery9becomes reference voltage VBr, and inverter3is controlled such that AC output voltages Va to Vc become AC output voltages Vu2, Vv2, and Vw2, respectively, of bypass AC power supply7. AC output voltages Va to Vc are thus supplied to load8through switches S4to S6to drive load8.

When a power failure of commercial AC power supply6occurs, switches S1to S3are turned off, the operation of converter1is stopped, bidirectional chopper2is controlled such that terminal-to-terminal voltage VDC of capacitor Cd becomes reference voltage VDCr2, and inverter3is controlled such that AC output voltages Va to Vc become AC output voltages Vu2, Vv2, and Vw2, respectively, of bypass AC power supply7.

When DC power of battery9is consumed and terminal-to-terminal voltage VB of battery9reaches a lower limit value, the operation of bidirectional chopper2and inverter3is stopped. Thus, even when a power failure of commercial AC power supply6occurs, the operation of load8can be continued for a period until the terminal-to-terminal voltage VB of battery9reaches the lower limit value.

When the inverter power feed mode is selected using operation unit4in a sound state of commercial AC power supply6, switches S1to S6are turned on and switches S7to S9are turned off, converter1is controlled such that terminal-to-terminal voltage VDC of capacitor Cd becomes reference voltage VDCr1, and bidirectional chopper2is controlled such that terminal-to-terminal voltage VB of battery9becomes reference voltage VBr, in the same manner as in the automatic operation mode. Inverter3is controlled such that AC output voltages Va to Vc become AC output voltages Vu2, Vv2, and Vw2, respectively, of bypass AC power supply7.

When the bypass power feed mode is selected using operation unit4in the inverter power feed mode, switches S1to S3are turned off, the operation of converter1is stopped, and bidirectional chopper2is controlled such that terminal-to-terminal voltage VDC of capacitor Cd becomes reference voltage VDCr2. Subsequently, the lap power feed mode is performed for a predetermined period of time, switches S4to S9are turned on, and three phase AC power is supplied from both of inverter3and bypass AC power supply7to load8. At this point of time, since switches S1to S3are off, circulating current does not flow through the uninterruptible power supply apparatus.

When the lap power feed mode ends, switches S4to S6are turned off and only switches S7to S9are turned on. Subsequently, switches S1to S3are turned on, converter1is controlled so that terminal-to-terminal voltage VDC of capacitor Cd is raised to reference voltage VDCr1, and the switching from the inverter power feed mode to the bypass power feed mode is completed. When the operation of converter1is resumed, DC power generated by converter1is stored into battery9through bidirectional chopper2.

In the bypass power feed mode, three phase AC power is supplied from bypass AC power supply7to load8through switches S7to S9to drive load8. In the bypass power feed mode, converter1, bidirectional chopper2, and inverter3are operated in preparation for the next time the inverter power feed mode is selected, and for example, battery9is charged. Alternatively, in the bypass power feed mode, switches S1to S3are turned off, and for example, repair or routine check of converter1, bidirectional chopper2, inverter3, battery9, etc. is performed.

When the inverter power feed mode is selected using operation unit4in the bypass power feed mode, switches S1to S3are turned off, the operation of converter1is stopped, and bidirectional chopper2is controlled such that terminal-to-terminal voltage VDC of capacitor Cd becomes reference voltage VDCr2. Subsequently, the lap power feed mode is performed for a predetermined period of time, switches S4to S9are turned on, and three phase AC power is supplied from both of inverter3and bypass AC power supply7to load8. At this point of time, since switches S1to S3are off, circulating current does not flow through the uninterruptible power supply apparatus.

When the lap power feed mode ends, switches S7to S9are turned off, switches S1to S6are turned on, converter1raises terminal-to-terminal voltage VDC of capacitor Cd to reference voltage VDCr1, and the switching from the bypass power feed mode to the inverter power feed mode is completed. When converter1is operated, DC power generated by converter1is stored into battery9through bidirectional chopper2.

Circulating current flowing through such an uninterruptible power supply apparatus will now be described.FIG. 2is a circuit diagram showing a configuration of converter1and inverter3. InFIG. 2, converter1includes IGBTs (Insulated Gate Bipolar Transistors) Q1to Q6and diodes D1to D6. The IGBTs constitute a switching element. The collectors of IGBTs Q1to Q3are connected together to DC positive bus Lp, and the emitters thereof are respectively connected to input nodes1a,1b, and1c.

Input nodes1a,1b, and1care respectively connected to the other terminals of reactors L1to L3(FIG. 1). The collectors of IGBTs Q4to Q6are respectively connected to input nodes1a,1b, and1c, and the emitters thereof are connected together to DC negative bus Ln. Diodes D1to D6are respectively connected in anti-parallel with IGBTs Q1to Q6.

IGBTs Q1to Q3turn on when gate signals A1, A2, and A3are brought to “H” level, respectively, and turn off when gate signals A1, A2, and A3are brought to “L” level, respectively. IGBTs Q4to Q6turn on when gate signals B1, B2, and B3are brought to “H” level, respectively, and turn off when gate signals B1, B2, and B3are brought to “L” level, respectively.

Each of gate signals A1, B1, A2, B2, A3, and B3is a pulse signal train and a PWM (Pulse Width Modulation) signal. The phase of gate signal A1, B1, the phase of gate signal A2, B2, and the phase of gate signal A3, B3are basically shifted from each other by 120 degrees. Gate signals A1, B1, A2, B2, A3, and B3are generated by control device5.

For example, when the level of AC input voltage Vu1is higher than the level of AC input voltage Vv1, IGBTs Q1and Q5are turned on, and current flows from input node1ato input node1bthrough IGBT Q1, DC positive bus Lp, capacitor Cd, DC negative bus Ln, and IGBT Q5to charge capacitor Cd.

Conversely, when the level of AC input voltage Vv1is higher than the level of AC input voltage Vu1, IGBTs Q2and Q4are turned on, and current flows from input node1bto input node1athrough IGBT Q2, DC positive bus Lp, capacitor Cd, DC negative bus Ln, and IGBT Q4to charge capacitor Cd. This is the same in other cases.

Each of IGBTs Q1to Q6is turned on and off at a predetermined timing by gate signals A1, B1, A2, B2, A3, and B3, and the ON time of each of IGBTs Q1to Q6is adjusted, whereby three phase AC voltage applied to input nodes6ato6ccan be converted to DC voltage VDC (terminal-to-terminal voltage of capacitor Cd).

Inverter3includes IGBTs Q11to Q16and diodes D11to D16. The IGBTs constitute a switching element. The collectors of IGBTs Q11to Q13are connected together to DC positive bus Lp, and the emitters thereof are respectively connected to output nodes3a,3b, and3c. Each of output nodes3a,3b, and3cis connected to one terminal of the corresponding one of reactors L4to L6(FIG. 1). The collectors of IGBTs Q14to Q16are respectively connected to output nodes3a,3b, and3c, and the emitters thereof are connected together to DC negative bus Ln. Diodes D11to D16are respectively connected in anti-parallel with IGBTs Q11to Q16.

IGBTs Q11to Q13turn on when gate signals X1, X2, and X3are brought to “H” level, respectively, and turn off when gate signals X1, X2, and X3are brought to “L” level, respectively. IGBTs Q14to Q16turn on when gate signals Y1, Y2, and Y3are brought to “H” level, respectively, and turn off when gate signals Y1, Y2, and Y3are brought to “L” level, respectively.

Each of gate signals X1, Y2, X3, Y1, X2, and Y3is a pulse signal train and a PWM signal. The phase of gate signal X1, Y1, the phase of gate signal X2, Y2, and the phase of gate signal X3, Y3are basically shifted from each other by 120 degrees. Gate signals X1, Y1, X2, Y2, X3, and Y3are generated by control device5.

For example, when IGBTs Q11and Q15turn on, DC positive bus Lp is connected to output node3athrough IGBT Q11, output node3bis connected to DC negative bus Ln through IGBT Q15, and a positive voltage is output between output nodes3aand3b.

When IGBTs Q12and Q14turn on, DC positive bus Lp is connected to output node3bthrough IGBT Q12, output node3ais connected to DC negative bus Ln through IGBT Q14, and a negative voltage is output between output nodes3aand3b.

Each of IGBTs Q11to Q16is turned on and off at a predetermined timing by gate signals X1, Y1, X2, Y2, X3, and Y3, and the ON time of each of IGBTs Q11to Q16is adjusted, whereby DC voltage VDC between buses Lp and Ln can be converted to three phase AC voltages Va, Vb, and Vc.

FIG. 3is an equivalent circuit diagram showing a configuration of commercial AC power supply6. InFIG. 3, commercial AC power supply6includes three phase AC power supplies6U,6V, and6W star-connected (Y-connected) to neutral point terminal6d. AC power supply6U is connected between AC output terminal6aand neutral point terminal6dand outputs AC voltage Vu1to AC output terminal6a. AC power supply6V is connected between AC output terminal6band neutral point terminal6dand outputs AC voltage Vv1to AC output terminal6b. AC power supply6W is connected between AC output terminal6cand neutral point terminal6dand outputs AC voltage Vw1to AC output terminal6c.

Each of AC voltages Vu1, Vv1, and Vw1changes sinusoidally at a commercial frequency (for example, 60 Hz). The peak values (√2 times the effective value) of AC voltages Vu1, Vv1, and Vw1are the same, and the phases thereof are shifted from each other by 120 degrees. AC power supplies6U,6V, and6W correspond to, for example, three phase windings at the last stage included in a three phase transformer at the last stage of commercial AC power supply6.

FIG. 4is an equivalent circuit diagram showing a configuration of bypass AC power supply7. InFIG. 4, bypass AC power supply7includes three phase AC power supplies7U,7V, and7W star-connected to neutral point terminal7d. AC power supply7U is connected between AC output terminal7aand neutral point terminal7dand outputs AC voltage Vu2to AC output terminal7a. AC power supply7V is connected between AC output terminal7band neutral point terminal7dand outputs AC voltage Vv2to AC output terminal7b. AC power supply7W is connected between AC output terminal7cand neutral point terminal7dand outputs AC voltage Vw2to AC output terminal7c.

Each of AC voltages Vu2, Vv2, and Vw2changes sinusoidally at a commercial frequency. The peak values of AC voltages Vu2, Vv2, and Vw2are the same, and the phases thereof are shifted from each other by 120 degrees. AC power supplies7U,7V, and7W correspond to, for example, a three phase coil of a self-generator.

In the inverter power feed mode and the bypass power feed mode, the phases (and peak values) of AC voltages Vu2, Vv2, and Vw2of bypass AC power supply7match the phases (and peak values) of AC voltages Vu1, Vv1, and Vw1of commercial AC power supply6, respectively, and switches S7to S9or switches S4to S6are off. In this state, no circulating current flows through the uninterruptible power supply apparatus.

However, in the lap power feed mode, when switches S7to S9or switches S4to S6turn on, load current of bypass AC power supply7significantly fluctuates, and the phases and peak values of AC voltages Vu2, Vv2, and Vw2fluctuate. AC voltages Vu2, Vv2, and Vw2then do not match AC voltages Vu1, Vv1, and Vw1, respectively.

FIGS. 5(A) to 5(C)are diagrams showing the relation between AC voltages Vu1, Vv1, and Vw1of commercial AC power supply6and AC voltages Vu2, Vv2, and Vw2of bypass AC power supply7. Each of AC voltages Vu1, Vv1, Vw1, Vu2, Vv2, and Vw2is illustrated by a vector. AC voltages Vu1, Vv1, and Vw1are out of phase by 120 degrees, and AC voltages Vu2, Vv2, and Vw2are out of phase by 120 degrees.FIG. 5(A)shows a case where the phases of AC voltages Vu2, Vv2, and Vw2match the phases of AC voltages Vu1, Vv1, and Vw1, respectively.

FIG. 5(B)shows a case where the phases of AC voltages Vu2, Vv2, and Vw2lag behind the phases of AC voltages Vu1, Vv1, and Vw1, respectively, by 60 degrees. For example, AC voltage Vu1and AC voltage Vw2are out of phase by 180 degrees. When AC voltage Vu1is a positive peak value and AC voltage Vw2is a negative peak value, voltage ΔV12=Vu1−Vw2that is the difference between AC voltage Vu1and AC voltage Vw2is the sum of peak values of AC voltages Vu1and Vw2.

Conversely, when AC voltage Vu1is a negative peak value and AC voltage Vw2is a positive peak value, voltage ΔV21=Vw2−Vu1that is the difference between AC voltage Vw2and AC voltage Vu1is the sum of peak values of AC voltages Vu1and Vw2.

FIG. 5(C)shows a case where the phases of AC voltages Vu2, Vv2, and Vw2are ahead of the phases of AC voltages Vu1, Vv1, and Vv1, respectively, by 60 degrees. For example, AC voltage Vu1and AC voltage Vv2are out of phase by 180 degrees. When AC voltage Vu1is a positive peak value and AC voltage Vv2is a negative peak value, voltage ΔV12=Vu1−Vv2that is the difference between AC voltage Vu1and AC voltage Vv2is the sum of peak values of AC voltages Vu1and Vv2. Conversely, when AC voltage Vu1is a negative peak value and AC voltage Vv2is a positive peak value, voltage ΔV21=Vv2−Vu1that is the difference between AC voltage Vv2and AC voltage Vu1is the sum of peak values of AC voltages Vu1and Vv2.

If in the lap power feed mode, switches S1to S3are turned on and terminal-to-terminal voltage VDC of capacitor Cd is smaller than the sum of peak values of AC voltages Vu1, Vv1, and Vw1and peak values of AC voltages Vu2, Vv2, and Vw2, the following problem arises. For example, as shown inFIG. 5(B), when AC voltages Vu1and Vw2are out of phase 180 degrees and voltage ΔV12=Vu1−Vw2that is the difference between AC voltages Vu1and Vw2is the sum of peak values of AC voltages Vu1and Vw2, circulating current IC flows through the path shown inFIG. 6.

That is, circulating current IC flows through a path from one terminal (output terminal6a) of AC power supply6U to the other terminal of AC power supply6U through input node1aof converter1, diode D1(FIG. 2), DC positive bus Lp, capacitor Cd, DC negative bus Ln, diode D16(FIG. 2), output node3cof inverter3, AC power supply7W, neutral point terminal7d, the line of ground voltage GND, and neutral point terminal6d. InFIG. 6, for the sake of simplicity of the drawing and the description, filters F1, F2, switches S1to S9turned on, and the like are not illustrated.

Conversely, when voltage ΔV21=Vw2−Vu1that is the difference between AC voltages Vw2and Vu1is the sum of peak values of AC voltages Vu1and Vw2, circulating current IC flows through the path shown inFIG. 7. That is, circulating current IC flows through a path from one terminal (output terminal7c) of AC power supply7W to the other terminal of AC power supply7U through output node3cof inverter3, diode D13(FIG. 2), DC positive bus Lp, capacitor Cd, DC negative bus Ln, diode D4(FIG. 2), input node1aof converter1, AC power supply6U, neutral point terminal6d, the line of ground voltage GND, and neutral point terminal7d.

When circulating current IC flows, circulating current IC charges capacitor Cd, terminal-to-terminal voltage VDC of capacitor Cd may exceed upper limit value VDCH, and control device5may determine that abnormality has occurred, so that the operation of the uninterruptible power supply apparatus may be stopped and the operation of load8may be stopped. The detected values of current detectors CT1to CT6may exceed upper limit value HI, and the control device5may determine that abnormality has occurred, so that the uninterruptible power supply apparatus may be stopped and the operation of load8may be stopped.

Then, in the present first embodiment, in the switching period in which one power feed mode of the inverter power feed mode and the bypass power feed mode is switched to the other power feed mode, switches S1to S3are turned off to prevent circulating current IC from flowing through the uninterruptible power supply apparatus. The lap power feed mode is performed in the switching period.

In the present first embodiment, terminal-to-terminal voltage VDC of capacitor Cd is set to reference voltages VDCr1, VDCr2lower than the voltage of the sum of peak values of AC voltages Vu1, Vv1, Vw1and peak values of AC voltages Vu2, Vv2, Vw2to reduce power consumption and improve the efficiency.

When bypass AC power supply7is stable, AC output voltages Vu2, Vv2, and Vw2of bypass AC power supply7match AC output voltages Vu1, Vv1, and Vw1of commercial AC power supply6, and therefore the voltage of the sum of peak values of AC voltages Vu1, Vv1, and Vw1and peak values of AC voltages Vu2, Vv2, and Vw2is equal to the voltage twice the peak values of AC voltages Vu1, Vv1, and Vw1. The peak values of AC voltages Vu1, Vv1, and Vw1are the same value.

For example, the effective value of AC voltage Vu1is 277 V and the peak value thereof is 392 V. The voltage twice the peak value of AC voltage Vu1is 784 V. Reference voltage VDCr1is set to 750 V lower than 784 V. Reference voltage VDCr2is set to 730 V slightly lower than reference voltage VDCr1. Reference voltage VDCr1is set to a value lower than upper limit value VDCH (for example, 1000 V) of terminal-to-terminal voltage VDC of capacitor Cd.

A method of controlling converter1and switches S1to S9will now be described.FIG. 8is a block diagram showing a configuration of a part of control device5that is related to control of converter1and switches S1to S9. InFIG. 8, control device5includes a signal generating circuit11, a timer12, a power failure detector13, and control units14to16.

Operation unit4(FIG. 1) brings mode select signal MS to “L” level when the user of the uninterruptible power supply apparatus selects the inverter power feed mode, and brings mode select signal MS to “H” level when the user selects the bypass power feed mode. Signal generating circuit11raises switch command signal PC to “H” level for a predetermined period of time, in response to each of the rising edge and the falling edge of mode select signal MS from operation unit4.

Timer12successively measures first time T1, second time T2, and third time T3, in response to the rising edge of switch command signal PC. Timer12brings switch signal ϕC to “H” level that is the active level from the rising edge of switch command signal PC to third time T3. Further, timer12brings overlap command signal ϕOL to “H” level that is the active level from first time T1to second time T2.

Power failure detector13determines whether a power failure has occurred, based on three phase AC voltages Vu1, Vv1, and Vw1supplied from commercial AC power supply6, and outputs power failure detection signal ϕF indicating the determination result. For example, power failure detector13determines that commercial AC power supply6is sound when the levels of AC voltages Vu1, Vv1, and Vw1are higher than a lower limit value, and determines that a power failure has occurred when the levels of AC voltages Vu1, Vv1, and Vw1become lower than a lower limit value. When commercial AC power supply6is sound, power failure detection signal ϕF is brought to “L” level that is the inactive level. When a power failure has occurred, power failure detection signal ϕF is brought to “H” level that is the active level.

Control unit14controls switches S4to S9in accordance with mode select signal MS and overlap command signal ϕOL. When both of mode select signal MS and overlap command signal ϕOL are “L” level, control unit14turns on switches S4to S6and turns off switches S7to S9.

When overlap command signal ϕOL is “H” level, control unit14turns on switches S4to S9. When mode select signal MS is “H” level and overlap command signal ϕOL is “L” level, control unit14turns on switches S7to S9and turns off switches S4to S6.

Control unit15turns off switches S1to S3when at least one of switch signal4C and power failure detection signal ϕF is brought to “H” level that is the active level, and turns on switches S1to S3when both of switch signal ϕC and power failure detection signal ϕF are “L” level that is the inactive level.

When both of switch signal ϕC and power failure detection signal ϕF are “L” level that is the inactive level, control unit16operates based on AC input voltages Vu1, Vv1, and Vw1, three phase input currents I1to I3, and DC voltage VDC and controls converter1such that terminal-to-terminal voltage VDC of capacitor Cd matches reference voltage VDCr1(or VDCr2). Control unit16stops the operation of converter1when at least one of switch signal ϕC and power failure detection signal ϕF is brought to “H” level that is the active level.

FIG. 9is a circuit block diagram showing a configuration of control unit16. InFIG. 9, control unit16includes voltage detectors20and28, a reference voltage generating circuit21, subtracters22and26A to26C, a DC voltage control circuit23, a sine wave generating circuit24, multipliers25A to25C, a current control circuit27, adders29A to29C, a PWM circuit30, an OR gate31, and a gate circuit32.

Voltage detector20detects terminal-to-terminal voltage VDC of capacitor Cd and outputs a signal indicating the detected value. Reference voltage generating circuit21generates reference voltage VDCr1. Subtracter22subtracts terminal-to-terminal voltage VDC of capacitor Cd from reference voltage VDCr1to obtain deviation ΔVDC=VDCr1−VDC between reference voltage VDCr1and DC voltage VDC.

DC voltage control circuit23calculates current command value Ic for controlling AC input currents I1to I3of converter1such that deviation ΔVDC=VDCr1−VDC becomes zero. DC voltage control circuit23calculates current command value Ic, for example, by performing proportional operation or proportional integral operation of deviation ΔVDC.

Sine wave generating circuit24generates three phase sine wave signals having the same phase as three phase AC voltages Vu1, Vv1, and Vw1from commercial AC power supply6. Multipliers25A to25C multiply the three phase sine wave signals by current command value Ic to generate three phase current command values I1cto I3c, respectively.

Subtracter26A calculates deviation ΔI1=I1c−I1between current command value I1cand AC current I1detected by current detector CT1. Subtracter26B calculates deviation ΔI2=I2c−I2between current command value I2cand AC current I2detected by current detector CT2. Subtracter26C calculates deviation ΔI3=I3c−I3between current command value I3cand AC current I3detected by current detector CT3.

Current control circuit27generates voltage command values V1a, V2a, and V3asuch that each of deviations ΔI1, ΔI2, and ΔI3becomes zero. Current control circuit27generates voltage command values V1a, V2a, and V3a, for example, by performing proportional control or proportional integral control of deviations ΔI1, ΔI2, and ΔI3. Voltage detector28detects instantaneous values of three phase AC voltages Vu1, Vv1, and Vw1from commercial AC power supply6and outputs signals indicating their detected values.

Adder29A adds voltage command value V1ato AC voltage Vu1detected by voltage detector28to generate voltage command value V1c. Adder29B adds voltage command value V2ato AC voltage Vv1detected by voltage detector28to generate voltage command value V2c. Adder29C adds voltage command value V3ato AC voltage Vw1detected by voltage detector28to generate voltage command value V3c.

PWM circuit30generates PWM control signals ϕ1to ϕ3for controlling converter1, based on voltage command values V1cto V3c. OR gate31outputs OR signal ϕ31of switch signal ϕC and power failure detection signal ϕF. When output signal ϕ31of OR gate31is “L” level, gate circuit32generates gate signals A1to A3and B1to B3(FIG. 2) based on PWM control signals ϕ1to ϕ3.

When output signal ϕ31of OR gate31is “H” level (that is, in the switching period or at the time of a power failure of commercial AC power supply6), gate circuit32brings gate signals A1to A3and B1to B3to “L” level and turns off IGBTs Q1to Q6to stop the operation of converter1.

The configuration and the control method of bidirectional chopper2will now be described.FIG. 10is a circuit diagram showing a configuration of bidirectional chopper2. InFIG. 10, bidirectional chopper2includes IGBTs Q21and Q22, diodes D21and D22, a reactor35, and a capacitor36. Bidirectional chopper2is controlled by a control unit37included in control device5.

The collector of IGBT Q21is connected to high voltage-side node2a, and the emitter thereof is connected to low voltage-side node2cthrough reactor35and connected to the collector of IGBT Q22. The emitter of IGBT Q22is connected to high voltage-side node2band low voltage-side node2d. Diodes D21and D22are respectively connected in anti-parallel with IGBTs Q21and Q22. Capacitor36is connected between high voltage-side nodes2aand2bto stabilize DC voltage VDC between high voltage-side nodes2aand2b.

IGBT Q21is controlled by gate signal G1from control unit37. When output signal ϕ31of OR gate31(FIG. 9) is “L” level, control unit37brings gate signal G1to “H” level and “L” level at a predetermined frequency, and when signal ϕ31is “H” level (that is, in the switching period and at the time of a power failure of commercial AC power supply6), control unit37fixes gate signal G1to “L” level. IGBT Q21turns on when gate signal G1is brought to “H” level, and IGBT Q21turns off when gate signal G1is brought to “L” level.

When IGBT Q21is turned on with VDC>VB, current Ib flows through a path from DC positive bus Lp to DC negative bus Ln through IGBT Q21, reactor35, and battery9, so that battery9is charged and electromagnetic energy is stored into reactor35.

When IGBT Q21is turned off, current flows through a path from one terminal (the terminal on the battery9side) of reactor35to the other terminal of reactor35through battery9and diode D22, so that battery9is charged and electromagnetic energy of reactor35is emitted.

The ratio between the period of time in which gate signal G1is brought to “H” level (pulse width) and one period is called duty ratio. When output signal ϕ31of OR gate31is “L” level, control unit37adjusts the duty ratio of gate signal G1such that terminal-to-terminal voltage VB of battery9becomes reference voltage VBr.

IGBT Q22is controlled by gate signal G2from control unit37. When output signal ϕ31of OR gate31(FIG. 9) is “H” level (that is, in the switching period and at the time of a power failure of commercial AC power supply6), control unit37brings gate signal G2to “H” level and “L” level at a predetermined frequency, and when signal ϕ31is “L” level, control unit37fixes gate signal G2to “L” level. IGBT Q22turns on when gate signal G2is brought to “H” level, and IGBT Q22turns off when gate signal G22is brought to “L” level.

When IGBT Q2is turned on, current flows from the positive electrode of battery9to the negative electrode of battery9through reactor35and IGBT Q22, and electromagnetic energy is stored into reactor35. When IGBT Q22is turned off, current flowing from reactor35to IGBT Q22is commutated from reactor35to diode D21and flows to the negative electrode of battery9through capacitors36and Cd, so that capacitors36and Cd are charged and electromagnetic energy of reactor35is emitted. When signal ϕ31is “H” level, control unit37adjusts the duty ratio of gate signal G2such that terminal-to-terminal voltage VDC of capacitor Cd becomes reference voltage VDC2.

FIGS. 11(A) to 11(H)are time charts showing the operation of control device5shown inFIG. 8toFIG. 10. InFIG. 11, (A) shows the waveform of mode select signal MS, (B) shows the waveform of switch command signal PC, (C) shows the waveform of switch signal ϕC, and (D) shows the waveform of overlap command signal ϕOL.

(E) shows terminal-to-terminal voltage VDC of capacitor Cd, (F) shows the state of switches S1to S3, (G) shows the state of switches S4to S6, and (H) shows the state of switches S7to S9.FIG. 11shows the operation in a case where the inverter power feed mode is switched to the bypass power feed mode.

At time t0, the inverter power feed mode is executed, and all of mode select signal MS, switch command signal PC, switch signal ϕC, and overlap command signal ϕOL are brought to “L” level. Terminal-to-terminal voltage VDC of capacitor Cd is brought to reference voltage VDCr1, switches S1to S6are turned on, and switches S7to S9are turned off.

When the bypass power feed mode is selected using operation unit4at a certain time t1, mode select signal MS is raised from “L” level to “H” level, and switch command signal PC is raised to “H” level by signal generating circuit11for a predetermined period of time. In response to the rising edge of switch command signal PC, timer12(FIG. 8) successively measures first time T1, second time T2, and third time T3and generates switch signal ϕC and overlap command signal ϕOL based on the time measurement result.

Switch signal ϕC is brought to “H” level from the rising edge of switch command signal PC (time t1) to third time T3(time t4). Overlap command signal ϕOL is brought to “H” level from first time T1(time t2) to second time T2(time t3).

When switch signal ϕC is raised from “L” level to “H” level (time t1), switches S1to S3(FIG. 1) are turned off, the operation of converter1is stopped by control unit16(FIG. 8,FIG. 9), and bidirectional chopper2is controlled by control unit37(FIG. 10) such that terminal-to-terminal voltage VDC of capacitor Cd becomes reference voltage VDCr2.

In the switching period in which switches S1to S3are turned off, lap command signal ϕOL is brought to “H” level, and the lap power feed mode is executed. When lap command signal ϕOL is raised to “H” level (time t2), switches S7to S9are turned on. At this point of time, since switches S1to S3are off, circulating current IC (FIG. 6,FIG. 7) does not flow. When lap command signal ϕOL is lowered to “L” level (time t3), switches S4to S6are turned off, and the lap power feed mode ends.

When switch signal ϕC is lowered to “L” level (time t4), switches S1to S3are turned on, the operation of converter1is resumed, charging of battery9by bidirectional chopper2is resumed, and the switching from the inverter power feed mode to the bypass power feed mode is completed. Terminal-to-terminal voltage VDC of capacitor Cd is raised from reference voltage VDCr2to reference voltage VDCr1by converter1. At this point of time, since reference voltage VDCr1is set to a voltage slightly higher than reference voltage VDCr2, terminal-to-terminal voltage VDC of capacitor Cd can be quickly returned to reference voltage VDCr1.

FIGS. 12(A) to 12(H)are other time charts showing the operation of control device5shown inFIG. 8toFIG. 10, in comparison withFIGS. 11(A) to 11(H).FIG. 12(A) to 12(H)show the operation in a case where the bypass power feed mode is switched to the inverter power feed mode.

At time t0, the bypass power feed mode is executed, mode select signal MS is brought to “H” level, and all of switch command signal PC, switch signal ϕC, and overlap command signal ϕOL are set to “L” level. Terminal-to-terminal voltage VDC of capacitor Cd is brought to reference voltage VDCr1by converter1, switches S1to S3and S7to S9are turned on, and switches S4to S6are turned off.

When the inverter power feed mode is selected using operation unit4at a certain time t1, mode select signal MS is lowered from “H” level to “L” level, and switch command signal PC is raised to “H” level by signal generating circuit11for a predetermined period of time. In response to the rising edge of switch command signal PC, timer12(FIG. 8) successively measures first time T1, second time T2, and third time T3and generates switch signal ϕC and overlap command signal ϕOL based on the time measurement result.

Switch signal ϕC is brought to “H” level from the rising edge of switch command signal PC (time t1) to third time T3(time t4). Overlap command signal ϕOL is set to “H” level from first time T1(time t2) to second time T2(time t3).

When switch signal ϕC is raised from “L” level to “H” level (time t1), the operation of converter1is stopped by control unit16(FIG. 8,FIG. 9), and bidirectional chopper2is controlled by control unit37(FIG. 10) such that terminal-to-terminal voltage VDC of capacitor Cd becomes reference voltage VDCr2.

In the period in which switches S1to S3are turned off, lap command signal ϕOL is brought to “H” level, and the lap power feed mode is executed. When lap command signal ϕOL is raised to “H” level (time t2), switches S4to S6are turned on.

At this point of time, since switches S1to S3are off, circulating current IC (FIG. 6,FIG. 7) does not flow. When lap command signal ϕOL is lowered to “L” level (time t3), switches S7to S9are turned off, and the lap power feed mode ends.

When switch signal ϕC is lowered to “L” level (time t4), switches S1to S3are turned on, the operation of converter1is resumed, charging of battery9by bidirectional chopper2is resumed, and the switching from the bypass power feed mode to the inverter power feed mode is completed. Terminal-to-terminal voltage VDC of capacitor Cd is raised from reference voltage VDCr2to reference voltage VDCr1by converter1. At this point of time, since reference voltage VDCr1is set to a voltage slightly higher than reference voltage VDCr2, terminal-to-terminal voltage VDC of capacitor Cd can be quickly returned to reference voltage VDCr1.

As described above, in the present first embodiment, in the switching period in which the inverter power feed mode and the bypass power feed mode are switched, switches S1to S3are turned off to electrically isolate converter1from commercial AC power supply6. Therefore, even when both of neutral point terminal6dof commercial AC power supply6and neutral point terminal7dof bypass AC power supply7are grounded, flowing of circulating current IC through a path including capacitor Cd can be prevented.

Second Embodiment

FIG. 13is a circuit block diagram showing the main part of an uninterruptible power supply apparatus according to a second embodiment of the present invention, in comparison withFIG. 8. Referring toFIG. 13, this uninterruptible power supply apparatus differs from the first embodiment in that timer12and control units14and15are replaced by a control unit40and auxiliary switches Sa, Sb, and Sc and state detectors44to46are added.

Switches S1to S3and auxiliary switch Sa constitute an electromagnetic contact41. Auxiliary switch Sa is interlocked with switches S1to S3. For example, when switches S1to S3turn on, switch Sa also turns on. Conversely, when switches S1to S3turn off, switch Sa may turn on. Switch Sa is connected to state detector44. State detector44detects whether switch Sa turns on or turns off (that is, whether switches S1to S3turn on or turn off) and outputs signal ϕ44indicating the detection result to control unit40.

Switches S4to S6and auxiliary switch Sb constitute an electromagnetic contact42. Auxiliary switch Sb is interlocked with switches S4to S6. For example, when switches S4to S6turn on, switch Sb also turns on. Conversely, when switches S4to S6turn off, switch Sb may turn on. Switch Sb is connected to state detector45. State detector45detects whether switch Sb turns on or turns off (that is, whether switches S4to S6turn on or turn off) and outputs signal ϕ45indicating the detection result to control unit40.

Switches S7to S9and auxiliary switch Sc constitute an electromagnetic contact43. Auxiliary switch Sc is interlocked with switches S7to S9. For example, when switches S7to S9turn on, switch Sc also turns on. Conversely, when switches S7to S9turn off, switch Sc may turn on. Switch Sc is connected to state detector46. State detector46detects whether switch Sc turns on or turns off (that is, whether switches S7to S9turn on or turn off) and outputs signal ϕ46indicating the detection result to control unit40.

Control unit40controls electromagnetic contacts41to43and outputs switch signal ϕC, based on output signal PS of signal generating circuit11, output signals ϕ44to ϕ46of state detectors44to46, and mode select signal MS. Control unit40turns off electromagnetic contact41when output signal ϕF of power failure detector13is “H” level that is the active level.

FIGS. 14(A) to 14(F)are time charts showing the operation of control unit40shown inFIG. 13. InFIG. 14, (A) shows the waveform of mode select signal MS, (B) shows the waveform of switch command signal PC, (C) shows the waveform of switch signal ϕC, (D) shows the state of switches S1to S3and Sa, (E) shows the state of switches S4to S6and Sb, and (F) shows the state of switches S7to S9and Sc.FIG. 14shows the operation in a case where the inverter power feed mode is switched to the bypass power feed mode.

At time t0, the inverter power feed mode is executed, and all of mode select signal MS, switch command signal PC, and switch signal ϕC are set to “L” level. Switches S1to S3and Sa and switches S4to S6and Sb are turned on, and switches S7to S9and Sc are turned off.

When the bypass power feed mode is selected using operation unit4at a certain time t1, mode select signal MS is raised from “L” level to “H” level, and switch command signal PC is raised to “H” level by signal generating circuit11for a predetermined period of time. In response to switch command signal PC being raised to “H” level, control unit40raises switch signal ϕC to “H” level and turns off switches S1to S3and Sa (time t2).

In response to auxiliary switch Sa being turned off, control unit40turns on switches S7to S9and Sc to execute the lap power feed mode (time t3). At this point of time, since switches S1to S3are off, circulating current IC (FIG. 6,FIG. 7) does not flow.

In response to auxiliary switch Sc being turned off, control unit40turns off switches S4to S6and Sb to terminate the lap power feed mode (time t4). In response to auxiliary switch Sb being turned off, control unit40turns on switches S1to S3and Sa and lowers switch signal ϕC to “L” level (time t5). The switching from the inverter power feed mode to the bypass power feed mode then ends.

FIGS. 15(A) to 15(F)are other time charts showing the operation of control unit40shown inFIG. 13. InFIG. 15, (A) shows the waveform of mode select signal MS, (B) shows the waveform of switch command signal PC, (C) shows the waveform of switch signal ϕC, (D) shows the state of switches S1to S3and Sa, (E) shows the state of switches S4to S6and Sb, and (F) shows the state of switches S7to S9and Sc.FIG. 15shows the operation in a case where the bypass power feed mode is switched to the inverter power feed mode.

At time t0, the bypass power feed mode is executed, mode select signal MS is brought to “H” level, and both of switch command signal PC and switch signal ϕC are brought to “L” level. Switches S1to S3and Sa and switches S7to S9and Sc are turned on, and switches S4to S6and Sb are turned off.

When the inverter power feed mode is selected using operation unit4at a certain time t1, mode select signal MS is lowered from “H” level to “L” level, and switch command signal PC is raised to “H” level by signal generating circuit11for a predetermined period of time. In response to switch command signal PC being raised to “H” level, control unit40raises switch signal ϕC to “H” level and turns off switches S1to S3and Sa (time t2).

In response to auxiliary switch Sa being turned off, control unit40turns on switches S4to S6and Sb to execute the lap power feed mode (time t3). At this point of time, since switches S1to S3are off, circulating current IC (FIG. 6,FIG. 7) does not flow.

In response to auxiliary switch Sb being turned off, control unit40turns off switches S7to S9and Sc to terminate the lap power feed mode (time t4). In response to auxiliary switch Sc being turned off, control unit40turns on switches S1to S3and Sa and lowers switch signal ϕC to “L” level (time t5). The switching from the bypass power feed mode to the inverter power feed mode then ends.

The other configuration and operation is similar to the first embodiment and a description thereof is not repeated. The present second embodiment achieves the same effect as the first embodiment.

The embodiments disclosed here should be understood as being illustrative in all respects and should not be construed as being limiting. The present invention is shown not in the foregoing description but in the claims, and it is intended that all modifications that come within the meaning and range of equivalence to the claims are embraced here.

REFERENCE SIGNS LIST