Analog switching system for low cross-talk

A system includes a voltage pump to generate a first pump voltage from an analog voltage signal. The system further includes switching pad to receive an analog signal from an external source and route the analog signal to analog processing circuitry over one or more analog signal busses based on the first pump voltage and the analog voltage signal.

TECHNICAL FIELD

This disclosure relates generally to electronic circuits, and more particularly to analog switching systems.

BACKGROUND

Many electronic devices include analog processing circuitry, such as analog-to-digital converters or analog signal filters, which can process analog signals. These electronic devices typically receive analog signals from an external source and route them to the analog processing circuitry through an analog switching system.

Conventional analog switching systems introduce or inject noise and/or cross-talk into the analog signals while being routed to the analog processing circuitry. Although some level of noise or cross-talk can ordinarily be allowed for non-precision applications, such as a touch-screen activation signaling, when an application requires more precise analog signals, the noise and cross-talk introduced by conventional analog switching systems can be intolerable and degrade the overall performance of the electronic devices.

SUMMARY

The patent application discloses embodiments of an analog signal switching system. In some embodiments, a system includes a voltage pump to generate a first pump voltage from an analog voltage signal. The system further includes a switching pad to receive an analog signal from an external source and route the analog signal to analog processing circuitry over one or more analog signal busses based on the first pump voltage and the analog voltage signal.

In some embodiments, a device includes an interface to receive analog signals to be routed to analog processing circuitry, and multiple analog switching circuits to receive the analog signals from the interface and to selectively forward the analog signal to the analog processing circuitry over respective bus lines. The one or more of the analog switching circuits can include non-overlapping circuitry to electrically decouple the one or more analog switching circuits from the respective bus lines between analog signal transfers over the respective bus lines.

In some embodiments, a method includes receiving an analog signal to be routed to analog processing circuitry over one or more analog busses, and receiving control signaling that identifies which of the one or more analog busses is to transfer the analog signal. The method further includes activating one or more switching devices to selectively forward the analog signal over the one or more analog busses responsive to the control signaling, wherein each of the switching devices is driven by different voltage pumps to avoid noise from one of the analog busses being transferred to at least another bus.

DETAILED DESCRIPTION

A programmable system on a chip (PSOC) or other electronic system can include programmable analog circuitry, such as analog-to-digital converters or analog signal filters, which can process analog signals. The programmable system on a chip includes a programmable switching system to receive analog signals from an external source and route the analog signals to the programmable analog circuitry. The programmable switching system includes various components and employs various techniques to reduce noise and cross-talk that would ordinarily be introduced into the received analog signals during routing to the programmable analog circuitry. Embodiments are shown and described below in greater detail.

FIG. 1is a block diagram of an example programmable system on a chip100including a programmable switching system according to embodiments of the invention. Referring toFIG. 1, the programmable system on a chip100includes programmable circuitry110to process analog signals for various system applications. For instance, the programmable circuitry110can include analog-to-digital converters, analog signal filters, bandgap reference circuitry, etc, which can be configured through commands issued by a system controller120. The system controller120can be a processor coupled to a computer readable memory storing instruction that, when executed by the processor, causes the processor to reconfigure the operations of the programmable circuitry110and/or direct operations of other components in the programmable system on a chip100. In some embodiments, the system controller120can be implemented as firmware or a discrete set of electrical hardware components.

The programmable system on a chip100includes a programmable switching system that can include multiple switching pads200and202as well as a switching device150. The multiple programmable switching pads200and202can receive analog input signals104and106, respectively, from an external source and route them to the switching device150. The switching device150can then selectively forward the analog signals to the programmable circuitry110for performance of various processing operations. AlthoughFIG. 1shows two pads200and202, in some embodiments, the programmable system on a chip100can include any number of pads, which can receive analog and/or digital signals.

The pads200and202and switching device150, when directed by the system controller120, e.g., through control signaling122and124, can route or forward the received analog input signals104and106to the programmable circuitry110. In some embodiments, the pad200can connect to at least two busses, for example, a first caged analog global (AG) bus400A and a second caged AG bus400B, and the pad202can connect to at least two busses, for example, a third caged AG bus400C and a fourth caged AG bus400D, available for routing the analog signal to programmable circuitry110. The pads200and202can switch and forward the analog input signals104and106, respectively, onto any of the available busses400A-D at the direction of the system controller120. As will be discussed below in greater detail, the use of caged bus routing helps to reduce cross-talk between busses or with other electrical components in the programmable system on a chip100.

The programmable system on a chip100includes an analog voltage (VDA) pad500to receive an external analog voltage VDA102, which can be used to power various other on-chip electrical components. For instance, the VDA pad500can route analog voltage VDA to a voltage pump130, route analog voltage VDA to pad200, route analog voltage VDA to switching device150, route analog voltage VDA to pad202, and route analog voltage VDA to a voltage pump140. Although not shown inFIG. 1, the VDA pad500can also route the analog voltage VDA to the programmable circuitry110and the system controller120.

In some embodiments, the VDA pad500can be configured in a star-configuration, which allows the VDA pad500to independently route the analog voltage VDA to the various on-chip components. By separating the routing of the analog voltage VDA, the VDA pad500can eliminate cross-talk that could have been introduced to a shared supply voltage line and propagated to other on-chip components. Also, since the use of shared supply routing can increase a voltage drop of the analog voltage VDA as it is routed to the various on-chip components, for example, due to the aggregate current draw for all of the components receiving a shared supply voltage, the separation of the analog voltages VDA routed to the on-chip components allows for a more consistent and higher level of voltage to drive the components. Embodiments of the VDA pad500will be described below in greater detail.

The programmable system on a chip100includes multiple voltage pumps130and140to generate pump voltages Vpump1and Vpump2, respectively. The voltage pumps130and140can provide the pump voltages Vpump1and Vpump2to the pads200and202and the switching device150for use in the switching and routing of the analog input signals104and106, respectively, to the programmable circuitry110. In some embodiments, the pads200and202can have separate switching circuitry for each of the caged busses400, and can be driven by a different pump voltage Vpump1or Vpump2. This separation of switching circuitry can help ensure noise present on one of the busses does not get transferred to the other bus via voltage pump130or140.

FIG. 2is a block diagram of an example programmable switching pad200shown inFIG. 1. Referring toFIG. 2, the pad200includes an input/output interface210to receive analog input signal104from an external source (not shown). The input/output interface210forwards the analog input signal104to a first analog global switch300A and a second analog global switch300B. The first analog global switch300A is coupled to the first caged AG bus400A, and can forward the analog input signal104over the first caged AG bus400A as output signal260A responsive to control signaling122from a system controller120. The second AG switch300B is coupled to the second caged AG bus400B, and can forward the analog input signal104over the second caged AG bus400B as output signal260B responsive to control signaling122from a system controller120. In some embodiments, the first caged AG bus400A is a quiet bus that is used to transfer data signals for precision applications, while the second caged bus400B can be considered a noisy bus that can be used to transfer any signal to the programmable circuitry110.

The pad200receives three different voltages, the analog voltage VDA from the VDA pad500, pump voltage Vpump1from the voltage pump130, and pump voltage Vpump2from the voltage pump140. In some embodiments, the analog voltage VDA is provided to both the first AG switch300A and the second AG switch300B, while the pump voltage Vpump1is provided to the first AG switch300A via a filter220, and the pump voltage Vpump2is provided to the second AG switch300B via a filter230.

The filter220is configured to receive pump voltage Vpump1from the voltage pump130and filters the pump voltage Vpump1for presentation to the first AG switch300A. In some embodiments, the filter220can be configured to remove noise from the pump voltage Vpump1that was introduced by the voltage pump130. For example, the filter220can be a bypass capacitor or resistor-capacitor (RC) filter configured to remove frequency components introduced by the voltage pump130during the generation of the pump voltage Vpump1from the analog voltage VDA. The filter220can also be configured to remove noise introduced to the pump voltage Vpump1during the routing from the voltage pump130to the pad200.

The filter230is configured to receive pump voltage Vpump2from the voltage pump140and filters the pump voltage Vpump2for presentation to the second AG switch300B. In some embodiments, the filter230can be configured to remove noise from the pump voltage Vpump2that was introduced by the voltage pump140. For example, the filter230can be a bypass capacitor or resistor-capacitor (RC) filter configured to remove frequency components introduced by the voltage pump140during the generation of the pump voltage Vpump2from the analog voltage VDA. The filter230can also be configured to remove noise introduced to the pump voltage Vpump2during the routing from the voltage pump140to the pad200.

In some embodiments, each pad in the system on a chip100can include the same or similar filters as pad200, which allows for the effective removal of noise introduced by the voltage pumps130and140. The distribution of the filters to the respective pads also allows the programmable system on a chip100the flexibility to remove noise introduced by routing the pump voltages to the respective pads.

Since the first AG switch300A and the second AG switch300B receive separate and independent pump voltages Vpump1and Vpump2(or voltages222and232after filtering), the pad200reduces the ability of noise from one of the caged AG busses400A or400B to propagate to the other bus400A or400B. For instance, if both of the AG switches300A and300B received the same pump voltage, it is possible that noise from one AG bus400A or400B could propagate to the other bus via the shared pump voltage and the shared voltage pump.

FIG. 3is a block diagram of an example switch300that can be included in the programmable switching pad200shown inFIGS. 1 and 2. Referring toFIG. 3, the switch300includes a field-effect transistor (FET) based T-switch configuration to route the analog input signal104received from the input/output interface210of the programmable switching pad200to a caged AG bus400A or400B that corresponds to the switch300. The switch300also includes control circuitry340to direct the operations of the T-switch that route the analog signal104.

The control circuitry340includes multiple inverters341-345to provide various activation signals or voltages V1-V5, respectively, to the T-switch. The inverters341-345can select between a high voltage, which can be a pump voltage Vpump or the analog voltage VDA, and a ground voltage based on signaling from non-overlapping logic346. For instance, inverters341and343can receive the pump voltage Vpump1or Vpump2, while the other inverters342and344-345can receive the analog voltage VDA. The selection between the high voltage and ground for each activation signal can direct the T-switch to operate in different operational states.

The T-switch includes a pair of circuit switches310and320coupled at a node350, which can bidirectionally transfer signals between their respective inputs and outputs. The T-switch also includes a decoupling circuit330to pull node350to a ground voltage when the T-switch is electrically decoupled from the caged AG bus400A or400B. This decoupling helps to ensure that noise present on the bus is not propagated back into the pad, or that noise in the pad is not propagated onto the caged bus400A or400B.

The circuit switch310can include a PMOS transistor312which is source-drain coupled with an NMOS transistor314. The PMOS transistor312can receive a voltage V4at a gate from the control circuitry340, and NMOS transistor314can receive a voltage V1at a gate from the control circuitry. In some embodiments, the voltage V4can be set to either a ground voltage or to the pump voltage Vpump, while the voltage V1can be set to either a ground voltage or to the analog voltage VDA. In operation, the voltages V1and V4can be set to turn-on the circuit switch310and pass the analog input signal104to circuit switch320through node350, or set to turn-off the circuit switch310and not allow voltage to pass over through the circuit switch310.

The circuit switch320can include a PMOS transistor322which is source-drain coupled with an NMOS transistor324. The PMOS transistor322can receive a voltage V5at a gate from the control circuitry340, and NMOS transistor324can receive a voltage V3at a gate from the control circuitry. In some embodiments, the voltage V5can be set to either a ground voltage or to the pump voltage Vpump, while the voltage V3can be set to either a ground voltage or to the analog voltage VDA. In operation, the voltages V3and V5can be set to turn-on the circuit switch320and output the analog input signal104received from circuit switch310over the caged AG bus400A or400B, or set to turn-off the circuit switch320and not allow voltage to pass through the circuit switch320.

The decoupling circuitry330can include an NMOS transistor with a drain coupled to node350, a source coupled to ground, and a gate coupled to voltage V2. In some embodiments, the voltage V2can be set to either a ground voltage or to the analog voltage VDA. In operation, the voltage V2can be set to turn-on the NMOS transistor and pull node350to a ground voltage, effectively discharging any voltage on node350. The voltage V2can be set to turn-off the NMOS transistor, allowing the switches310and320to pass data signals to each other.

The non-overlapping logic346of the control circuitry340can receive control signaling122from the system controller120and coordinate the selection of the various activation signals V1-V5outputted from the inverters341-345. The non-overlapping logic346can also delay turning on the decoupling circuit330until after both switches310and320are turned off, to help ensure that there are no glitches on the signal through the T-switch.

As discussed above, activation signals or voltages V4and V5are provided to circuit switches310and320with either a voltage level of a ground voltage or a pump voltage Vpump. Since it is possible that a capacitance between the output signal260and the gate of the PMOS transistors322can alter the voltage level of the gate or the output signal260, and that a capacitance between the input signal104and the gate of the PMOS transistors312can alter the voltage level of the gate or the input signal104, in some embodiments, the control circuitry340provides separate and independent signals V4and V5to the gates of the two PMOS transistors312and322. In other words, due to the characteristics of the PMOS transistors312and322, by providing separate signals V4and V5to their respective gates, the T-switch can avoid noise from being introduced into the input signal104or the output signal260.

FIGS. 4A and 4Bare block diagrams illustrating examples of caged bus routing shown inFIGS. 1 and 2. Referring toFIG. 4A, a cross-sectional view of a caged bus route400is shown. The caged bus route400includes multiple signal paths422and424which can carry the analog signals104or106from the pads200and202to the switching device150. The signal paths422and424can be substantially surrounded by grounding components, such as ground layer410, ground layer430, ground paths421,423, and425, and corresponding vias426A-B,427A-B, and428A-B. By substantially surrounding the signal paths422and424with grounding components, cross-talk between the signal paths422and424and noise infiltration can be reduced.

The caged bus route400has three main layers, a signal path layer420located in between two grounding layers410and430. The signal path layer420is configured to interleave signal paths422and424with ground paths421,423, and425. The caged bus route400can include grounding vias426A-426B,427A-B, and428A-B located in between the signal path layer420and the ground layers410and430and over the ground paths421,423, and425. In some embodiments, these grounding vias can be arranged in a picket fence configuration. The picket fence configuration is shown inFIG. 4B, which illustrates a top-view of the caged bus route400.

Although the addition of grounding components substantially reduces cross-talk and noise, the signal path layer420can be variously configured to trade-off the remaining noise and cross-talk for particular applications. For example, a size of a signal path, shown as “A”, a distance between a signal path and a ground path, shown as “B”, and a size of a ground path, shown as “C” can be configured or optimized to trade-off cross-talk between the signal paths, as well as noise and signal integrity due to parasitic resistance and/or parasitic capacitance.

FIG. 5is a block diagram of an example analog voltage (VDA) pad500according to embodiments of the invention. According toFIG. 5, the VDA pad500can receive the VDA voltage102and provide the VDA voltage102to a VDA filter520. The VDA filter520can filter or remove at least a portion of noise on the VDA voltage102. For instance, the VDA voltage102can include high frequency components that were introduced during generation off-chip, which can be removed or reduced by the VDA filter520. The VDA filter520can also remove or reduce noise that is introduced to the VDA voltage102during routing to the VDA pad500.

The VDA filter520can provide a filtered VDA voltage to multiple VDA routing paths530-1to530-N that are arranged in a star-configuration. The star-configuration allows the VDA pad500to output filtered VDA signals502-1to502-N to various on-chip components over separate and independent routing lines. By separating the transmission of the filtered VDA signals502over independent routing lines, the VDA pad500in combination with the VDA filter520and the multiple VDA routing paths530-1to530-N can eliminate cross-talk that could have been introduced to a shared supply route line and propagated to other on-chip components. Also, since the use of a shared supply route can increase a voltage drop of the analog voltage VDA as it is routed to the various on-chip components, for example, due to the aggregate current draw for all of the components receiving a shared supply voltage, the separation of the filtered VDA route502to the on-chip components allows for a more consistent and higher level of voltage to drive the components.

FIG. 6is an example operational flowchart for the programmable system on a chip as shown inFIGS. 1-5. Referring toFIG. 6, in a block610, the programmable switching system is configured to receive an analog signal to be routed to analog processing circuitry over one or more analog busses. The analog signal can be received from an off-chip source that is providing the analog signals to the programmable system on a chip100for analog processing.

In a block620, the programmable switching system is configured to receive control signaling that identifies which of the one or more analog busses is to transfer the analog signal. The control signaling can be generated and provided to the programmable switching system by a system controller. The control signaling can be an on/off signal that indicates to the programmable switching which switches should be allowed to pass the analog signal to the processing circuitry over their particular analog busses.

In a block630, the programmable switching system is configured to receive multiple drive voltages from different voltage pumps. As discussed above, the use of multiple drive voltages can be used for different switches within the programmable switching system to reduce cross-talk between multiple busses.

In a block640, the programmable switching system is configured to separately filter the drive voltages received from the different voltage pumps based, at least in part, on characteristics of respective voltage pumps that generated the drive voltages. In some embodiments, the drive voltages can include high frequency components that were introduced by the voltage pumps during generation, which are undesirable. The separate filtering of the drive voltages can remove these high frequency components, as well as remove noise introduced during routing between the voltage pumps and the programmable switching system.

In a block650, the programmable switching system is configured to activate one or more switching devices to selectively forward the analog signal over the one more analog busses responsive to the control signaling. In a block660, the programmable switching system is configured to deactivate the one or more switching devices after the analog signal is forwarded over the one more analog busses responsive to control signaling.

In a block670, the programmable switching system is configured to electrically decouple the switching devices from the respective analog busses after the deactivating of the one or more switching devices. The programmable switching system includes distributed non-overlap logic that sequences the local switching operations of individual switches in programmable switching system. This allows for the system controller to issue control signaling that provides a high-level on/off decision regarding the transfer of analog signals over a bus line, without having to micro-manage the actual sequence of the switching operations to ensure that the switching system does not have signal transfer overlap.

One of skill in the art will recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated embodiments are but one of many alternative implementations that will become apparent upon reading this disclosure.

The preceding embodiments are examples. Although the specification may refer to “an”, “one”, “another”, or “some” embodiment(s) in several locations, this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment.