Method of manufacturing a thinned gate electrode utilizing protective films and etching

The reduction of length of a gate electrode is suppressed in the process of thinning it. A hard mask (5a) is thinned and used to etch a gate electrode material film (4) to form a gate electrode. At this time, a resist mask (10) having an opening (11) over an active region (1) is formed; the resist mask (10) covers at least both ends in the length direction of the hard mask (5a) and exposes in the opening (11) at least the entirety of the part of the hard mask (5a) which lies right above the active region (1). The hard mask (5a) is thinned by etching using the resist mask (10) as a mask and therefore the hard mask (5a) is thinned in the part over the active region (1) without being shortened in the length direction. As a result, the gate electrode formed by using the thinned hard mask (5a) is not shortened in length.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having a gate electrode and its manufacturing method, and particularly to a technique for thinning the gate electrode.

2. Description of the Background Art

The requirements of making finer circuit patterns for more highly integrated semiconductor devices are constantly bringing about finer gate electrode structures. Also, the technique for reducing the gate length (channel length) of transistors, i.e. for thinning the gate electrode structures, is important for the purpose of increasing the speed of devices. However, since the resolution in lithography is limited by the limited wavelength of the light source, it is difficult to form gate electrodes having widths of about 100 nm or less by using common gate electrode formation process; therefore the methods shown below are used to form such thin gate electrodes.

FIGS. 22A,22B,23A,23B,24A and24B are process diagrams showing a conventional semiconductor device manufacturing method. In these drawings,FIG. 22Bshows the cross section taken along the direction P1-Q1inFIG. 22A,FIG. 23Bshows the cross section taken along the direction P2-Q2inFIG. 23A, andFIG. 24Bshows the cross section taken along the direction P3-Q3in FIG.24A. First, as shown inFIGS. 22A and 22B, a gate oxide film103and a gate electrode material film104are formed on a silicon substrate having an active region101and isolation oxide films102, and a resist mask105, in the shape of a line crossing the active region101, is formed thereon by lithography. Next, the resist mask105is lightly ashed and thus slimmed (thinned). This results in, as shown inFIGS. 23A and 23B, a resist mask105aof a reduced width (hereinafter referred to as a thinned resist mask). Then the gate electrode material film104is anisotropically etched using the thinned resist mask105aas a mask, so as to form a thinned gate electrode104aas shown inFIGS. 24A and 24B.

Clearly, the gate electrode104athus obtained has a smaller width than the resist mask105shown inFIGS. 22A and 22Bwhich was formed by lithography and which has not yet been thinned. This means that the width of the gate electrode104acan be reduced beyond the limit of resolution in the lithography technique. As can be seen fromFIGS. 24A and 24B, thinning the gate electrode and reducing its width shortens the gate length (channel length) of the transistor, which contributes to achievement of higher operation speed of the semiconductor device.

FIGS. 25A and 25Bare diagrams used to describe a problem of this conventional semiconductor device.FIG. 25Ais the top view of the semiconductor device having the thinned gate electrode104ashown inFIG. 24A, andFIG. 25Bis an enlarged view of the part Z inFIG. 25A, where the broken line115shows the shape of the resist mask105ofFIG. 22Awhich are not yet thinned. The ashing process for thinning the resist mask105in this method reduces the entire dimensions of the resist mask105. That is to say, the resist mask105is made smaller not only in the width direction but also in the length direction to form the thinned resist mask105a. Accordingly, as shown inFIG. 25B, the length of the resultant gate electrode104ais shorter by dS than the length of the resist mask105not thinned yet. As a countermeasure, it may be suggested that, prior to the process of thinning the gate electrode, a longer resist mask105be formed before it is thinned, considering the lengthwise size reduction. However, forming a longer resist mask105increases the chip size and therefore hinders achievement of higher integration of the semiconductor device.

FIGS. 26A,26B,27A,27B,28A,28B,29A and29B are process diagrams showing another conventional semiconductor device manufacturing method. In these drawings,FIG. 26Bshows the cross section taken along the direction P4-Q4inFIG. 26A,FIG. 27Bshows the cross section taken along the direction P5-Q5inFIG. 27A, andFIG. 28Bshows the cross section taken along the direction P6-Q6in FIG.28A.FIG. 29Bshows the cross section taken along the direction P7-Q7in FIG.29A. First, as shown inFIGS. 26A and 26B, a gate oxide film103, a gate electrode material film104, and a hard mask material film106of, e.g. SiO2, are formed on a silicon substrate having an active region101and isolation oxide films102, and a resist mask107in the shape of a line crossing the active region101is formed thereon by lithography. Then the hard mask material film106is etched by using the resist mask107as a mask to form a hard mask106aas shown inFIGS. 27A and 27B. Next, the hard mask106ais thinned by isotropic etching, e.g. wet etching. This results in a hard mask106bof a reduced width (hereinafter referred to as a thinned hard mask) as shown inFIGS. 28A and 28B. Then the gate electrode material film104is anisotropically etched using the thinned hard mask106bas a mask, so as to form a thinned gate electrode104bas shown inFIGS. 29A and 29B.

The process of thinning the hard mask106ain this method provides the thinned hard mask106bwhich has been made smaller not only in the width direction but also in the length direction than the hard mask106anot thinned yet. That is to say, the resultant gate electrode104b, too, is shorter in length than the hard mask106anot thinned yet. That is, this manufacturing method, too, raises the problem described referring toFIGS. 25A and 25B.

As described above, the gate electrode thinning techniques in the conventional semiconductor device manufacturing methods involve a reduction of the length of the gate electrode. This requires that the gate electrode be designed longer in advance, considering the reduction of length (i.e. in the processes shown above, forming a longer resist mask105(or107) before it is thinned), or that larger pads be designed at both ends of the gate electrode to which interconnections are connected, but such approaches result in an increase in chip size.

SUMMARY OF THE INVENTION

An object of the invention is to provide a semiconductor device and a manufacturing method thereof in which the reduction of length of the gate electrode can be suppressed when it is thinned.

According to a first aspect of the invention, a semiconductor device manufacturing method includes the following steps (a) to (e) of: (a) forming a gate insulating film on a semiconductor substrate having an active region formed in its surface and forming a gate electrode material film on the gate insulating film; (b) forming on the gate electrode material film a first protective film in the shape of a line crossing the active region; (c) forming a second protective film which covers at least both ends in the length direction of the first protective film and which leaves uncovered at least the part of the first protective film which lies right above the active region; (d) thinning the first protective film using the second protective film as a mask; and (e) etching the gate electrode material film using the thinned first protective film as a mask, so as to form a gate electrode.

In the step (d), the second protective film used as a mask prevents the first protective film from being shortened in the length direction. As a result the gate electrode formed in the step (e) is not shortened, either, and therefore it is not necessary to size the first resist mask longer prior to the thinning process, which contributes to achievement of higher integration of the semiconductor device. On the other hand, the part of the gate electrode which lies on the active region is thinned and therefore the gate length (channel length) is shortened, which contributes to achievement of higher operation speed of the semiconductor device.

According to a second aspect of the invention, a semiconductor device manufacturing method includes the following steps (a) to (e) of: (a) forming a gate insulating film on a semiconductor substrate having an active region formed in its surface and forming a gate electrode material film on the gate insulating film; (b) forming on the gate electrode material film a first protective film in the shape of a line crossing the active region; (c) etching the gate electrode material film using the first protective film as a mask to form a gate electrode; (d) forming a second protective film which covers at least both ends in the length direction of the gate electrode and which leaves uncovered at least the part of the gate electrode which lies on the active region; and (e) thinning the gate electrode by etching using the second protective film as a mask.

In the step (e), the second protective film used as a mask prevents the gate electrode from being shortened in the length direction. As a result it is not necessary to size the first protective film longer prior to the thinning process, which contributes to achievement of higher integration of the semiconductor device. On the other hand, the part of the gate electrode which lies on the active region is thinned and therefore the gate length (channel length) is shortened, which contributes to achievement of higher operation speed of the semiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1A,1B,2A,2B,3A,3B,3C,4A,4B,4C,5A,5B,6A,6B and6C are process diagrams showing a semiconductor device manufacturing method according to a first preferred embodiment. In these diagrams,FIG. 1Bshows the cross section taken along the direction A1-B1inFIG. 1A,FIG. 2Bshows the cross section taken along the direction A2-B2inFIG. 2A,FIGS. 3B and 3Cshow the cross sections taken along the directions A3-B3and C3-D3inFIG. 3A, respectively,FIGS. 4B and 4Cshow the cross sections taken along the directions A4-B4and C4-D4inFIG. 4A, respectively,FIG. 5Bshows the cross section taken along the direction A5-B5inFIG. 5A,FIG. 6Bshows the cross section taken along the direction A6-B6inFIG. 6A, andFIG. 6Cis an enlarged view of the part E in FIG.6A. The semiconductor device manufacturing method of this preferred embodiment is now described referring to these drawings.

First, as shown inFIGS. 1A and 1B, a gate oxide film3, a gate electrode material film4, and a hard mask material film5, e.g. TEOS oxide film or silicon nitride film, are formed on a silicon substrate having an active region1and isolation oxide films2, and a first resist mask6, in the shape of a line crossing the active region1, is formed thereon by lithography. Then the hard mask material film5is etched using the first resist mask6as a mask and then the first resist mask6is removed to obtain a hard mask5a, or a first protective film, as shown inFIGS. 2A and 2B.

Subsequently, as shown inFIGS. 3Ato3C, a second resist mask10, or a second protective film, having an opening11right above the active region1is formed by lithography. At this time, as shown inFIGS. 3A and 3C, the second resist mask10is formed so that it covers at least both ends, in the length direction, of the hard mask5a, and so that it leaves uncovered at least the entirety of the part of the hard mask5awhich lies right above the active region1(so that at least the part of the hard mask5athat lies right above the active region1is entirely exposed in the opening11). Considering alignment error in formation of the opening11, it is desirable to size the opening11somewhat larger than the width of the active region1so that the part of the hard mask5aright above the active region1can certainly be exposed entirely. However, note that care should be taken so that both ends of the hard mask5aare not exposed in the opening11.

Next, the surface of the hard mask5ais etched and thinned by isotropic etching, e.g. wet etching, using the second resist mask10as a mask. As a result, as shown inFIGS. 4Ato4C, the sides and top surface of the hard mask5a, which are exposed in the opening11, are etched. During this process, both ends in the length direction of the hard mask5a, covered by the second resist mask10, are not etched. Then, the second resist mask10is removed by ashing, and as shown inFIGS. 5A and 5B, a hard mask5bis obtained which has been thinned only in the part located right over the active region1.

In the description below, a resist mask, a hard mask, and a gate electrode obtained as a result of the thinning process, which are thinner than the first resist mask6not thinned, are referred to as “a thinned resist mask,” “a thinned hard mask,” and “a thinned gate electrode.”

Subsequently, the gate electrode material film4is anisotropically etched using the thinned hard mask5bas a mask and then the thinned hard mask5bis removed to obtain a thinned gate electrode4athat is thinned only in the part that is on the active region1as shown inFIGS. 6Ato6C. Now, the broken line15inFIG. 6Cshows the shape of the resist mask6shown inFIG. 1Awhich are not thinned yet. In this preferred embodiment, the etching process for thinning the hard mask5ais performed by using the second resist mask10as a mask, so that both ends of the hard mask5aare not etched. That is to say, the length of the resultant thinned hard mask5bis not shortened from the length of the hard mask5anot thinned yet. Therefore the thinned gate electrode4aobtained by etching using the thinned hard mask5bis not shortened in the length direction, either, as shown in FIG.6C.

The thinned hard mask5bis removed by a different method depending on its material. For example, when TEOS oxide film is used as the material of the thinned hard mask5b, etching the hard mask5baway after the etching for forming the thinned gate electrode4amay unnecessarily etch the gate oxide film3and the isolation oxide films2because of a small etch selectivity ratio. Accordingly, in this case, it is desirable to previously adjust the film thickness of the thinned hard mask5bso that the TEOS oxide film, i.e. the thinned hard mask5b, will be removed simultaneously by the etching for forming the thinned gate electrode4a. When silicon nitride film is used as the hard mask, it may be removed by this method, or it may be removed, after the etching for forming the thinned gate electrode4a, by an etching process exhibiting a high etch selectivity ratio between nitride film and oxide film. Needless to say, if the device structure allows the thinned hard mask5bto remain on the thinned gate electrode4a, the thinned hard mask5bdoes not necessarily have to be removed.

As shown inFIGS. 6Ato6C, the semiconductor device of this preferred embodiment, formed by the process above, has the thinned gate electrode4athat is thinned only in the part on the active region1. That is to say, in the thinned gate electrode4a, the width of the whole part located right on the active region is smaller than the width of both its ends in the length direction. That is to say, the part of the thinned gate electrode4alocated on the active region1is thinned and therefore the gate length (channel length) of the transistor is shortened, which contributes to achievement of higher operation speed of the semiconductor device. On the other hand, as can be understood from the process described above, the length of the thinned gate electrode4ais not shortened from the length of the first resist mask6and therefore it is not necessary to previously form the first resist mask6longer, which contributes to achievement of higher integration of the semiconductor device. While the width of both ends of the thinned gate electrode4a, which are located outside the active region1, remains unthinned, the width of these parts is clearly not related to the gate length and therefore does not hinder the achievement of higher operation speed of the device.

As for the material of the thinned gate electrode4ain this preferred embodiment, Poly-Si or any other gate electrode materials, such as metal materials like W, are applicable. The first resist mask6, the second resist mask10, etc. can be formed by any lithography techniques using electron-beam exposure, X-ray exposure, etc., as well as optical exposure.

Further, prior to the formation of the second resist mask10, an antireflection agent may be applied to or formed as a film on the underlayer in order to suppress reflection from the underlayer during the exposure for forming the opening11in the second resist mask10over the active region.FIGS. 7Ato7C are diagrams that show the structure obtained in this case immediately after the formation of the opening11.FIGS. 7B and 7Cshow the cross sections taken along the directions A7-B7and C7-D7ofFIG. 7A, respectively. As shown in these diagrams, immediately after the opening11has been formed, the hard mask5ain the opening11is covered by an antireflection coating16. Accordingly, in this case, before thinning the hard mask5a, the antireflection coating16in the opening11is first removed by, e.g. ashing, to expose the hard mask5a, and subsequently the exposed hard mask5ais thinned by etching.

In this preferred embodiment, as shown inFIGS. 3Ato3C, the second resist mask10has a rectangular opening11which opens entirely over the active region1in plan view. However, the second resist mask10may be arbitrarily shaped as long as it at least covers both ends in the length direction of the hard mask5aand it at least leaves uncovered the entirety of the part of the hard mask5athat is right above the active region1. In other words, the effect of this preferred embodiment can be obtained when the second resist mask10is formed to cover the part of the gate electrode where dimension reduction should be prevented (i.e. the part not to be thinned) and not to cover the part to be thinned.

When a plurality of devices having gate electrodes are formed on a semiconductor substrate, the devices may include those which require thinning the gate electrode to shorten the gate length and those which require keeping the gate electrode unthinned and hence the gate length unchanged. In such a case, the second resist mask10is formed to also cover the gate electrodes of the latter devices, i.e. those which do not require thinning the gate electrode. Also, desirably, the second resist mask10is formed to cover the regions where interconnections among the devices are formed, since they do not require thinning.

In the first preferred embodiment, TEOS oxide film or silicon nitride film is used as the material of the hard mask used to form the thinned gate electrode; in this preferred embodiment, an organic compound, such as SiC, SiOC, or amorphous carbon, is used as the material of the hard mask. Hard masks made of such organic compounds can be removed by ashing.

FIGS. 8A,8B,8C,9A and9B are process diagrams used to explain a semiconductor device manufacturing method of the second preferred embodiment. In these diagrams,FIGS. 8B and 8Cshow the cross sections taken along the directions A8-B8and C8-D8inFIG. 8A, respectively, andFIG. 9Bshows the cross section taken along the direction A9-B9in FIG.9A. The semiconductor device manufacturing method of this preferred embodiment is now described referring to these diagrams.

First, by the same processes described in the first preferred embodiment, the gate oxide film3and the gate electrode material film4are formed on a silicon substrate having the active region1and the isolation oxide films2. Then, as shown inFIGS. 8Ato8C, a hard mask20of an organic compound in the shape of a line crossing the active region1, i.e. the first protective film, is formed thereon and the second resist mask10having the opening11above the active region1, i.e. the second protective film, is formed. As in the first preferred embodiment, the second resist mask10is formed to cover at least both ends of the hard mask5ain the length direction and to leave uncovered at least the entirety of the part of the hard mask20which lies right above the active region1. Note that, in this preferred embodiment, the second resist mask10is made of a material which exhibits a higher ashing rate than the organic-compound hard mask20and offers a high selectivity with respect to the hard mask20during ashing.

Resist materials which satisfy these conditions with respect to the hard mask of organic compound such as SiC, SiOC, or amorphous carbon, include resists for KrF excimer laser, of acetal, t-BOC (tertiary Butoxy Carbonyl), and ESCAP based, and resists for ArF excimer laser, of acrylic, polynorbornene, and COMA (Cyclo-Olefin Maleic Anhydride) classes, for example. Common resists for F2 laser or EB laser also provide selectivity with respect to the hard mask during ashing.

Next, isotropic ashing process is performed using the second resist mask10as a mask to thin the hard mask20. The second resist mask10is removed by the ashing since the material of the second resist mask10exhibits a higher ashing rate than the hard mask20. In other words, the second resist mask10having a higher ashing rate is completely removed by the ashing, while the hard mask20having a slower ashing rate is removed only in the surface portion and is thus thinned. That is to say, the ashing process achieves the thinning of the hard mask20and the removal of the second resist mask10at the same time. On the other hand, during this process, both ends of the hard mask20are not ashed and therefore remain unthinned until the second resist mask10covering these parts has been completely removed. As a result, after the second resist mask10has been removed by the ashing, as shown inFIG. 9A, a thinned hard mask20aof organic compound is obtained which is thinned only in the part above the active region1.

Subsequently, the gate electrode material film4is anisotropically etched by using the thinned hard mask20aas a mask and then the thinned hard mask20ais removed, so as to obtain, as in the first preferred embodiment, a thinned gate electrode4aas shown inFIGS. 6Ato6C in which only the part residing on the active region1is thinned. In this preferred embodiment, during the ashing process for thinning the hard mask20, both of its ends are not ashed because they are covered by the second resist mask10. That is to say, the resultant thinned hard mask20ais not shortened in the length direction from the length of the hard mask20not thinned yet. Accordingly, the thinned gate electrode4aobtained by etching using the thinned hard mask20aas a mask is not shortened in the length direction, either, as shown in FIG.6C.

Now, as for the removal of the thinned organic-compound hard mask20a, it may be removed by ashing after the thinned gate electrode4ahas been formed by etching, or the film thickness of the thinned hard mask20amay be previously adjusted so that the thinned hard mask20acan also be removed by the etching for formation of the thinned gate electrode4a. Needless to say, if the device structure allows the thinned hard mask20ato remain on the thinned gate electrode4a, the thinned hard mask20adoes not necessarily have to be removed.

As shown above, in the semiconductor device of this preferred embodiment, as in the first preferred embodiment, the part of the thinned gate electrode4that lies on the active region1is thinned and so the gate length (channel length) of the transistor is shortened, which contributes to achievement of higher operation speed of the semiconductor device. Furthermore, as can be understood from the process described above, the length of the thinned gate electrode4ais not shortened from the length of the first resist mask6, which contributes to achievement of higher integration of the semiconductor device.

Moreover, in the semiconductor device manufacturing method of this preferred embodiment, as shown above, the thinning of the organic-compound hard mask20and the removal of the second resist mask10can be achieved by a single ashing process, and the manufacturing process is thus simpler than that of the first preferred embodiment.

Also in this preferred embodiment, the first resist mask6, the second resist mask10, etc. can be formed by any lithography techniques using electron-beam exposure, X-ray exposure, etc., as well as optical exposure.

Also in this preferred embodiment, the thinned gate electrode4amay be made of Poly-Si or any other gate electrode materials, such as metal materials like W. However, if a sufficient etch selectivity ratio cannot be obtained between the organic-compound hard mask and the gate electrode material, the following modification will work.FIGS. 10A and 10Bare diagrams used to describe a modification of the second preferred embodiment, whereFIG. 10Bshows the cross section taken along the direction A10-B10in FIG.10A. That is to say, in the manufacturing process of this preferred embodiment, a TEOS oxide film is previously formed between the gate electrode material film4and the organic-compound hard mask material film. As a result, after the hard mask20has been thinned, as shown inFIGS. 10A and 10B, a TEOS oxide film25resides on the gate electrode material film4and the thinned hard mask20aresides thereon. First, the TEOS oxide film25is patterned by etching using the thinned hard mask20aas a mask and then the thinned gate electrode4ais patterned by using the patterned TEOS oxide film25. Thus, this preferred embodiment can be applied also to gate electrode materials which cannot offer sufficient etch selectivity ratio with respect to the hard mask of organic compound.

Furthermore, in this preferred embodiment, before the formation of the second resist mask10, an antireflection agent may be applied to or formed as a film on the underlayer in order to suppress reflection from the underlayer during the exposure for forming the opening11in the second resist mask10over the active region. In this case, as has been described in the first preferred embodiment, the antireflection coating16in the opening11is first removed to expose the hard mask20, and then ashing is applied to thin the hard mask20and to remove the second resist mask10.

FIGS. 11A,11B,12A,12B,13A and13B are process diagrams used to explain a semiconductor device manufacturing method according to a third preferred embodiment. In these diagrams,FIG. 11Bshows the cross section taken along the direction A11-B11inFIG. 11A,FIG. 12Bshows the cross section taken along the direction A12-B12in FIG.12A, andFIG. 13Bshows the cross section taken along the direction A13-B13in FIG.13A. The semiconductor device manufacturing method of this preferred embodiment is now described referring to these diagrams.

First, as shown inFIGS. 1A and 1B, the gate oxide film3and the gate electrode material film4are formed on the silicon substrate having the active region1and the isolation oxide films2, and the first resist mask6in the shape of a line crossing the active region1, i.e. the first protective film, is formed thereon by lithography. Then the first resist mask6undergoes a resist curing process with electron-beam radiation, ultraviolet (UV) radiation, ion implantation, etc.

Subsequently, as shown inFIGS. 12A and 12B, the second resist mask10having an opening11over the active region1, i.e. the second protective film, is formed by lithography. The second resist mask10is formed to cover at least both ends in the length direction of the first resist mask6, and to leave uncovered at least the entirety of the part of the first resist mask6which extends right above the active region1. Considering alignment error in the formation of the opening1, it is desirable to size the opening11somewhat larger than the width of the active region1so that it certainly contains the entirety of the part of the first resist mask6right above the active region1. Note that care should be taken so that both ends of the first resist mask6are not exposed in the opening11.

Next, the first resist mask6is thinned by isotropic ashing using the second resist mask10as a mask. In this preferred embodiment, the first resist mask6is cured as mentioned before and therefore the second resist mask10exhibits a higher ashing rate than the first resist mask6, so that the second resist mask10is removed by this ashing process. In other words, the second resist mask10having a higher ashing rate is completely removed by this ashing process, while the first resist mask6having a lower ashing rate is removed only in the surface portion and is thus thinned. That is to say, this ashing process simultaneously achieves the thinning of the first resist mask6and the removal of the second resist mask10. Also, during this process, both ends of the first resist mask6are not ashed and therefore remain unthinned until the second resist mask10covering these portions has been completely removed. As a result, after the second resist mask10has been removed by the ashing, as shown inFIG. 13A, the first resist mask6a(thinned resist mask6a) is obtained in which only the part over the active region1is thinned.

Subsequently, the gate electrode material film4is anisotropically etched by using the thinned resist mask6aas a mask and then the thinned resist mask6ais removed, so as to obtain, as in the first preferred embodiment, the thinned gate electrode4athat is thinned only in the part on the active region1as shown inFIGS. 6Ato6C. In this preferred embodiment, during the ashing process for thinning the first resist mask6, both its ends are not ashed because they are covered by the second resist mask10. That is to say, the resultant thinned resist mask6ais not shortened in the length direction from the length of the first resist mask6not thinned yet. Accordingly, the thinned gate electrode4aobtained by etching using the thinned resist mask6aas a mask is not shortened in the length direction, either, as shown in FIG.6C.

As shown above, in the semiconductor device of this preferred embodiment, as in the first preferred embodiment, the part of the thinned gate electrode4which resides on the active region1is thinned and so the gate length (channel length) of the transistor is shortened, which contributes to achievement of higher operation speed of the semiconductor device. Furthermore, as can be understood from the process described above, during the process of forming the thinned gate electrode4a, it is not shortened from the length of the first resist mask6, which contributes to achievement of higher integration of the semiconductor device.

Also in this preferred embodiment, the formation of the first resist mask6, the second resist mask10, etc. can use any lithography techniques using electron-beam exposure, X-ray exposure, etc., as well as optical exposure.

Also in this preferred embodiment, the thinned gate electrode4amay be made of Poly-Si or any other gate electrode materials such as metal materials like W. However, if a sufficient etch selectivity ratio cannot be obtained between the resist mask and the gate electrode material, the following modification will work.FIGS. 14A and 14Bare diagrams used to describe a modification of the third preferred embodiment, whereFIG. 14Bshows the cross section taken along the direction A14-B14in FIG.14A. That is to say, in the manufacturing process of this preferred embodiment, a TEOS oxide film is previously formed between the gate electrode material film4and the first resist mask6. As a result, after the first resist mask6has been thinned, as shown inFIGS. 14A and 14B, the TEOS oxide film25resides on the gate electrode material film4and the thinned resist mask6aresides thereon. During the formation of the thinned gate electrode4a, first, the TEOS oxide film25is patterned by etching using the thinned resist mask6aas a mask and then the thinned gate electrode4ais patterned by using the patterned TEOS oxide film25. Thus, this preferred embodiment can be applied also to gate electrode materials which cannot offer sufficient etch selectivity ratio with respect to the resist mask.

FIGS. 15A,15B,16A,16B,17A,17B,18A,18B and18C are process diagrams used to explain a semiconductor device manufacturing method according to a fourth preferred embodiment. In these diagrams,FIG. 15Bshows the cross section taken along the direction A15-B15inFIG. 15A,FIG. 16Bshows the cross section taken along the direction A16-B16inFIG. 16A,FIG. 17Bshows the cross section taken along the direction A17-B17inFIG. 17A, andFIGS. 18B and 18Cshow the cross sections taken along the directions A18-B18and C18-D18inFIG. 18A, respectively. The semiconductor device manufacturing method of this preferred embodiment is now described referring to these diagrams.

First, as shown inFIGS. 15A and 15B, the gate oxide film3and the gate electrode material film4are formed on the silicon substrate having the active region1and the isolation oxide films2, and the first resist mask6in the shape of a line crossing the active region1, i.e. the first protective film, is formed thereon by lithography. Then, in this preferred embodiment, without thinning the first resist mask6, the gate electrode material film4is anisotropically etched by using the first resist mask6as a mask to form a gate electrode4bas shown inFIGS. 16A and 16B.

Subsequently, as shown inFIGS. 17A and 17B, the second resist mask10having the opening11above the active region1, i.e. the second protective film, is formed by lithography. The second resist mask10is formed to cover at least both ends in the length direction of the gate electrode4b, and to leave uncovered at least the entirety of the part of the gate electrode4bwhich lies right on the active region1. Considering alignment error in the formation of the opening11, it is desirable to size the opening11somewhat larger than the width of the active region1so that it will certainly contain the entirety of the part of the gate electrode4bthat lies right on the active region1. Note that care should be taken so that both ends of the gate electrode4bare not exposed in the opening11.

Next, the gate electrode4bis lightly etched by isotropic dry etching or wet etching using the second resist mask10as a mask and it is thus thinned. During this process, both ends of the gate electrode4b, covered by the second resist mask10, are not etched and therefore remains unthinned.

After that, the second resist mask10is removed by ashing and, as shown inFIG. 18A, a thinned gate electrode4cis obtained in which only the part located on the active region1has been thinned. In this preferred embodiment, as shown inFIG. 18C, the thinned gate electrode4cthus obtained has a smaller vertical thickness in the part located on the active region1than in the portions at both ends, since the upper surface of the part on the active region1(i.e. the thinned portion) is also etched during the etching for thinning it. On the other hand, both ends of the gate electrode4bare not etched during the etching and therefore the thinned gate electrode4cis not shortened in the length direction from the length of the gate electrode4bnot thinned yet.

As shown above, in the semiconductor device of this preferred embodiment, as in the first preferred embodiment, the part of the thinned gate electrode4cwhich lies on the active region1is thinned and so the gate length (channel length) of the transistor is shortened, which contributes to achievement of higher operation speed of the semiconductor device. Furthermore, as can be understood from the process described above, the process of thinning the gate electrode4bdoes not shorten its length and therefore it is not necessary to size the gate electrode4blarger before it is thinned, which contributes to achievement of higher integration of the semiconductor device.

Also in this preferred embodiment, the thinned gate electrode4cmay be made of Poly-Si or any other gate electrode materials such as metal materials like W. Further, the formation of the first resist mask6, the second resist mask10, etc. can use any lithography techniques using electron-beam exposure, X-ray exposure, etc., as well as optical exposure.

Furthermore, also in this preferred embodiment, before formation of the second resist mask10, an antireflection agent may be applied to or formed as a film on the underlayer in order to suppress reflection from the underlayer during the exposure for forming the opening11in the second resist mask10over the active region. In this case, as has been described in the first preferred embodiment, the antireflection coating16in the opening11is first removed to expose the gate electrode4b, and then the gate electrode4bis thinned.

If the purpose is just to prevent the thinned gate electrode4cfrom being shortened, the second resist mask10can be arbitrarily shaped as long as it covers at least both ends in the length direction of the gate electrode4band it leaves uncovered at least the part of the gate electrode4bwhich lies right on the active region1. However, in this preferred embodiment, shaping the second resist mask10to cover the isolation oxide films2as shown inFIGS. 17A and 17Bprevents the isolation oxide films2from being unnecessarily etched during the thinning of the gate electrode4b.

In the first to third preferred embodiments, the second resist mask10as the second protective film is shaped so that it covers both ends in the length direction of the first protective film before it is thinned (the hard mask5ain the first preferred embodiment, the hard mask20in the second preferred embodiment, and the first resist mask6in the third preferred embodiment), and so that it leaves uncovered the entirety of the part of the first protective film which lies right above the active region1. Furthermore, in the fourth preferred embodiment, it is shaped so that it covers both ends in the length direction of the gate electrode4bwhich has been patterned using the first protective film (first resist mask6) and so that it leaves uncovered the entirety of the part of the gate electrode4bwhich lies right over the active region1. This preferred embodiment describes a method for forming the pattern for the second resist mask10.

FIGS. 19A and 19Bare diagrams used to explain a method for forming the pattern of the second protective film (the second resist mask10) according to a fifth preferred embodiment. First, with a CAD system, as shown inFIG. 19A, the pattern41of the first protective film (i.e. the pattern of the gate electrode before thinned) and the pattern42of the active region1are superimposed and the pattern42of the active region1which contains the overlap portion with the pattern41of the first protective film is extracted (i.e. the region43shown with slanting lines in the diagram). Then, by CAD processing, a pattern50afor the second protective film is formed in which the region43forms an opening. At this time, as shown inFIG. 19B, the region43is somewhat enlarged by CAD to form the opening, considering dimension variation and positional shift due to alignment error.

With this CAD processing, the pattern50afor the second protective film is obtained, where it contains both ends of the pattern41of the first protective film and has an opening in the part where the pattern41of the first protective film and the pattern42of the active region1overlap.

The second protective film is formed by using the pattern50athus obtained and the second protective film (the second resist mask10) of the present invention can be formed so as to cover both ends of the first protective film (or the gate electrode formed by using it) before it is thinned and so as to leave uncovered the entirety of the part of the first protective film (or the gate electrode formed using it) which lies right over the active region1.

FIGS. 20A and 20Bare diagrams used to explain a method for forming the pattern for the second protective film (the second resist mask10) according to a sixth preferred embodiment. First, with a CAD system, as shown inFIG. 20A, the pattern41of the first protective film (i.e. the pattern of the gate electrode before thinned) and the pattern42of the active region1are superimposed and the region44where the pattern41of the first protective film and the pattern42of the active region1overlap is extracted. Then, by CAD processing, a pattern50bfor the second protective film is formed in which the region44forms an opening. At this time, as shown inFIG. 20B, the region44is somewhat enlarged by CAD to form the opening, considering dimension variation and positional shift due to alignment error.

With this CAD processing, the pattern50bfor the second protective film is obtained, where it contains both ends of the pattern41of the first protective film and has an opening in the part where the pattern41of the first protective film and the pattern42of the active region1overlap.

The second protective film is formed by using the pattern50bthus obtained and the second protective film (the second resist mask10) of the present invention can be formed so as to cover both ends of the first protective film (or the gate electrode formed by using it) before it is thinned and so as to leave uncovered the entirety of the part of the first protective film (or the gate electrode formed using it) which lies right over the active region1.

FIGS. 21A and 21Bare diagrams used to explain a method for forming the pattern for the second protective film (the second resist mask10) according to a seventh preferred embodiment. First, with a CAD system, as shown inFIG. 21A, the pattern41of the first protective film (i.e. the pattern of the gate electrode before thinned) and the pattern42of the active region1are superimposed and the regions45of the pattern41of the first protective film which are located outside the pattern42of the active region1are extracted. Then, by CAD processing, a pattern50cfor the second protective film is formed in the positions of the regions45. At this time, as shown inFIG. 21B, considering dimension variation and positional shift due to alignment error, the regions45are somewhat enlarged by CAD so that the pattern50cof the second protective film certainly covers both ends of the pattern41of the first protective film, and a margin is formed by CAD between the regions45and the pattern42of the active region1to ensure that the pattern42of the active region1is not covered by the pattern50cof the second protective film.

With this CAD processing, the pattern50cfor the second protective film is obtained, where it contains both ends of the pattern41of the first protective film and does not contain the part where the pattern41of the first protective film and the pattern42of the active region1overlap.

The second protective film is formed by using the pattern50cthus obtained and the second protective film (the second resist mask10) of the present invention can be formed so as to cover both ends of the first protective film (or the gate electrode formed by using it) before it is thinned and so as to leave uncovered the entirety of the part of the first protective film (or the gate electrode formed using it) which lies right over the active region1.