Phase change memory device and method of fabricating the same

A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode. A phase change layer is electrically connected to the second conductor pattern and a top electrode is connected to the phase change layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application claims the benefit of foreign priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2006-89318, filed on Sep. 14, 2006, the entire contents of which are hereby incorporated by reference.

BACKGROUND

1. Field of Invention

Embodiments exemplarily disclosed herein generally relate to semiconductor devices and methods of fabricating the same, and more particularly, to a phase change memory device and a method of fabricating the same.

2. Discussion of the Related Art

A phase change memory device stores data by using a stable state of a phase change material. The phase change material can stably exhibit one of two states depending upon a temperature applied thereto. After heating the phase change material at a temperature higher than a melting temperature of the phase change material and then cooling it down, the phase change material layer exhibits a substantially amorphous state. After heating the phase change material at a temperature higher than a crystallization temperature and lower than the melting temperature and then cooling it down, the phase change material layer exhibits a substantially crystalline state.

The electrical resistivity of the phase change material layer exhibiting a substantially amorphous state is higher than the electrical resistivity of the phase change material layer exhibiting a substantially crystalline state. Accordingly, the logic state of a memory cell formed of phase change material can be differentiated as either logic 1 or logic 0 by detecting a current that flows through the phase change material layer during a read mode.

A cell of a typical phase change memory device includes one access transistor and one phase change element.FIG. 1is an equivalent circuit of a cell array in a conventional access transistor-type phase change memory device.

Referring toFIG. 1, an access transistor Tx and a phase change device R are connected between word lines WL and bit lines BL. A gate of the access transistor Tx is connected to the word line WL, its drain is connected to the bit line BL, and its source is connected to the phase change device R.

In the device shown inFIG. 1, a unit cell has a structure similar to that of DRAM. In a case of a NOR cell array structure, the size of a cell may have an 8F2structure, which is 8 times of a minimum feature size F. However, when using the minimum size access transistor, a sufficient current may not be supplied for phase change. Therefore, a big size transistor of 15 through 20F2structure is required.

Recently, diode-type access phase change memory devices have been proposed.FIG. 2is an equivalent circuit of a cell array in a conventional access diode-type phase change memory device.

Referring toFIG. 2, the cell array includes a structure where an access diode Dx and a phase change device R are connected in series between word lines WL and bit lines BL. In this structure, the access diode Dx and the phase change device R are connected in series between the word lines WL and bit lines BL such that the size of a memory cell can be reduced as compared to the size of the memory cell shown inFIG. 1.

FIG. 3Ais a plan view of a conventional phase change memory device.FIG. 3Bis a sectional view of the conventional phase change memory device, taken along line I-I′ ofFIG. 3A.

Referring toFIGS. 3A and 3B, a word line10extends toward one direction and is disposed on a semiconductor substrate. A first conductor pattern12and a second conductor pattern14are sequentially stacked on the word line10. The word line10is typically formed as an impurity diffusion layer having a first conductivity type, and the first conductor pattern12and the second conductor pattern14are formed as an impurity diffusion layer having a second conductivity type. For example, the word line10is formed of an n-type impurity diffusion layer, and the first and second conductor patterns12and14are formed of a p-type impurity diffusion layer. The word line10and the first conductor pattern12constitute PN-junction to form a diode.

A bottom electrode16is formed on the second conductor pattern12and a heater18is formed on the bottom electrode16. A phase change layer20and a bit line22are formed on the heater18. The bit line22corresponds to the top electrode and extends along a direction perpendicular to the word line10.

When forming the word line10and the bit line22having a minimum line width, the area occupied by a unit cell may be two times the minimum line width. Accordingly, this improves the degree of integration as compared to traditional transistors. However, when the area occupied by the PN junction of the word line10and the first conductor pattern12is F2. As a result, a sufficient current to induce phase change within the phase change layer20cannot be applied. Therefore, the degree of integration of the phase change memory device is reduced as the size of cell increases.

SUMMARY

Embodiments exemplarily described herein provide a highly integrated semiconductor device such as a phase change memory device capable of increasing a current of a diode, and a method of fabricating the same.

Embodiments exemplarily described herein also provide a semiconductor device such as a phase change memory device capable of reducing an amount of current required to induce phase change within a phase change layer, and a method of fabricating the same.

One embodiment exemplarily described herein can be characterized as a semiconductor device that includes a diode formed on a semiconductor substrate. The diode may include a first conductor pattern of a first conductivity type and having a sidewall defining a structure and a second conductor pattern connected to the sidewall of the first conductor pattern. A phase change layer may be electrically connected to the second conductor pattern and a top electrode may be connected to the phase change layer.

Another embodiment exemplarily described herein can be characterized as a semiconductor device that includes an insulating layer having a hole on a semiconductor substrate. A first conductor pattern of a first conductivity type is formed in a lower region of the hole such that the first conductor pattern is a substantially cylindrical structure having a sidewall and a bottom. An insulator pattern is formed in an upper region of the hole and on the first conductor pattern such that the insulator pattern is a substantially cylindrical structure having a sidewall. A second conductor pattern fills an area surrounded by the first conductor pattern such that the first conductor pattern and the second conductor pattern form a diode. A bottom electrode is formed on the second conductor pattern in an area surrounded by the insulator pattern. A phase change layer and a top electrode are sequentially stacked on the bottom electrode.

Yet another embodiment exemplarily described herein can be characterized as a method for forming a semiconductor device that includes forming a first conductor pattern of a first conductivity type on a semiconductor substrate such that the first conductor pattern has a sidewall defining a structure, forming a second conductor pattern connected to the sidewall of the first conductor pattern to form a diode, forming a phase change layer electrically connected to the second conductor pattern and forming a top electrode connected to the phase change layer.

DETAILED DESCRIPTION

Exemplary embodiments will now be described below in more detail with reference to the accompanying drawings. These embodiments may, however, be realized in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

FIG. 4Ais a plan view of a phase change memory device according to a first embodiment.FIG. 4Bis a sectional view of the phase change memory device according to the first embodiment, taken along line II-II′ ofFIG. 4A.

Referring toFIGS. 4A and 4B, a phase change memory device may, for example, include a first conductor pattern106shaving a sidewall and a second conductor pattern110connected to the first conductor pattern106s. In one embodiment, the sidewall of the first conductor pattern106smay define a substantially cylindrical shape and the second conductor pattern110may fill an area defined by the sidewall of the first conductor pattern106s. In one embodiment, the second conductor pattern110may be connected to the sidewall of the first conductor pattern106sto form a diode. Accordingly, a contact area between the first and second conductor patterns106sand110can be increased while occupying a relatively small area over a semiconductor substrate.

A bottom electrode124is connected to the second conductor pattern110. A phase change layer116and the second conductor pattern110are electrically connected to each other through the bottom electrode124. For example, the bottom electrode124may be formed on the second conductor pattern110. In one embodiment, the bottom electrode124may include a first electrode112and a second electrode114. The first electrode112may have a substantially cylindrical shape having a sidewall and a bottom. The second electrode114may fill an area surrounded by the sidewall of the first electrode112.

The first conductor pattern106smay include a semiconductor material having a first conductivity type. The second conductor pattern110may include a semiconductor material having a second conductivity type. Accordingly, a PN junction may be formed between first and second conductor patterns106sand110. In one embodiment, the second conductor pattern110may include a material that can establish a Schottky contact with the first conductor pattern106s.

In the illustrated embodiment, the first conductor pattern106smay be formed inside a hole104extending through an insulating layer102. The hole104may expose a portion of a word line100formed on a semiconductor substrate. The first conductor pattern106smay be formed in a lower region of the hole104to continuously cover the word line100and sidewalls of the lower region of the hole104. An insulator pattern108may be formed on an upper region of the sidewall of the hole104such that the insulator pattern108overlies the first conductor pattern106s. Accordingly, the insulator pattern108may define an area where the second conductor pattern110and the bottom electrode124are formed. In one embodiment, the insulator pattern108may be substantially cylindrically shaped with an open top and open bottom. In one embodiment, a sidewall of the insulator pattern108may be substantially aligned with a sidewall of the first conductor pattern106s. In another embodiment, the sidewall of the insulator pattern108may be substantially flush with the sidewall of the first conductor pattern106s.

In one embodiment, the top surface of the second conductor pattern110may be substantially coplanar with the top surface of the first conductor pattern106s. In another embodiment, the top surface of the second conductor pattern110may be higher than the top surface of the first conductor pattern106sand may contact the sidewall of the insulator pattern108.

The phase change layer116is formed on the bottom electrode124and a top electrode118is formed on the phase change layer116. Accordingly, the phase change layer116and the top electrode118are sequentially stacked on the bottom electrode124. In one embodiment, the top electrode118may extend along a first direction to form a bit line.

In one embodiment, the word line100may be a diffusion layer having a conductivity type that is the same as the conductivity type of the first conductor pattern106s. The word line100may extend along a second direction so as to cross beneath the top electrode118. In the illustrated embodiment, the bit line118and the word line100may extend substantially perpendicularly with respect to each other.

The cell array includes a plurality of word lines100crossing under a plurality of bit lines118. The first conductor pattern106s, the second conductor pattern110, and the bottom electrode124may be formed over an area of the semiconductor substrate where the word line100and the bit line118cross each other (hereinafter referred to as a “crossing area”). In one embodiment, the phase change layer116can be aligned with a top electrode118and extend along the same direction as the bit line118. In such an embodiment, the phase change layer116may extend through a plurality of crossing areas. In another embodiment, the phase change layer116may be restrictively formed on the bottom electrode124. In such an embodiment, the phase change layer116is present within a single crossing area.

As mentioned above, the word line100and the first conductor pattern106smay have a first conductivity type and the second conductor pattern110may have a second conductivity type. In one embodiment, an impurity concentration of the first conductivity type within the first conductor pattern106smay be lower than an impurity concentration of the first conductivity type within the word line100.

The first conductor pattern106smay ohmically contact the word line100. The first conductor pattern106sand the second conductor pattern110may include a material such as an epitaxially grown semiconductor layer. The first electrode112may include a material such as a metal, a metal alloy, or the like or a combination thereof. For example, the first electrode112may include titanium, titanium nitride, or the like or a combination thereof. The second electrode114may include a material such as a metal, a metal silicide, or the like or a combination thereof.

In one embodiment, a top surface of the second conductor pattern110may be substantially coplanar with a top surface of the insulating layer102, thereby substantially filling the hole104. In such an embodiment, the bottom electrode124may be formed on the top surface of the insulating layer102and be connected to the second conductor pattern110. The phase change layer116and the top electrode118may be sequentially stacked on the bottom electrode124.

FIGS. 5 through 10are sectional views illustrating an exemplary method of fabricating a phase change memory device according to the first embodiment.

Referring toFIG. 5, an insulating layer102with a hole104is formed on a semiconductor substrate. In a cell array region of the semiconductor substrate, the insulating layer102may have a plurality of holes104and a plurality of word lines100may be formed below the insulating layer102and be exposed by the plurality of holes104. In one embodiment, the word lines100may include a diffusion layer of a first conductivity type. In another embodiment, the word lines100include a conductive metal pattern, or the like. The holes104may be spaced apart from each other along a row direction and a column direction by a predetermined pitch.

Referring toFIG. 6, a conductive pattern106may be formed inside the hole104. The conductive pattern106may include a semiconductor material doped with an impurity having a first conductivity type. For example, the conductive pattern106may include a semiconductor material epitaxially grown from a portion of the semiconductor substrate exposed through the hole104. In one embodiment, the conductive pattern106may be formed by epitaxially growing an epitaxial layer to a predetermined height within the hole104. In another embodiment, the conductive pattern106may be formed by epitaxially growing an epitaxial layer to completely fill the hole104followed by etching the epitaxial layer to form the conductive pattern106that fills the hole104up to the predetermined height. The conductive pattern106may, for example, be doped during the epitaxial growing process or may be doped using an ion implantation process after the epitaxial growing process (e.g., after etching the epitaxial layer). The conductive pattern106may be doped in a low concentration. For example, the conductive pattern106may have an impurity concentration of the first conductivity type that is lower than an impurity concentration of the word lines100.

Referring toFIG. 7, an insulator pattern108may be formed to cover the sidewall of the hole104and be disposed on the conductive pattern106. The insulator pattern108may be formed along the sidewall of the hole104such that it has a substantially cylindrical shape. In one embodiment, the insulator pattern108may be formed using a spacer formation process. For example, a spacer layer may be formed over the insulating layer102and within the hole104so as to cover the conductive pattern106. Subsequently, the spacer layer may be anisotropically etched to form the insulator pattern108. The spacer layer has etching rate different from that of the insulating layer102. That is, the spacer layer may include a material that is capable of being etched selectively with respect to a material of the insulating layer102. For example, the insulating layer102may include silicon oxide and the spacer layer may include silicon nitride.

Referring toFIG. 8, the conductive pattern106is etched using the insulator pattern108as an etching mask. As a result, a first conductor pattern106shaving a closed bottom is formed such that a portion of the conductive pattern106remains on the word line100. Moreover, a sidewall of the first conductor pattern106smay be formed on the sidewall of the hole104. Accordingly, a sidewall of the insulator pattern108may be substantially aligned with the sidewall of the first conductor pattern106s. That is, the sidewall of the insulator pattern108may be substantially flush with the sidewall of the first conductor pattern106s. As shown, the insulator pattern108may have a substantially cylindrical shape with an open top and open bottom.

Referring toFIG. 9, a second conductor pattern110is formed in the first conductor pattern106s. The second conductor pattern110may have a second conductivity type. For example, the second conductor pattern110may include a semiconductor material having a second conductivity type. In one embodiment, the second conductor pattern110may include an epitaxial layer grown from the first conductor pattern106s. In such an embodiment, the second conductor pattern110may be doped during the epitaxial growing process, or may be doped using an ion implantation process after completing the epitaxial growing process. Therefore, the second conductor pattern110can have the second conductivity type. In one embodiment, the second conductive pattern110may be formed by epitaxially growing an epitaxial layer to a predetermined height within the hole104. In another embodiment, the second conductive pattern110may be formed by epitaxially growing an epitaxial layer to completely fill the hole104followed by etching the epitaxial layer to form the second conductive pattern110that fills the hole104up to the predetermined height.

As mentioned above, the second conductor pattern110has the second conductivity type. Accordingly, the second conductor pattern110can form a PN-junction with the first conductor pattern106s. The second conductor pattern110may fill an area defined by the sidewall of the first conductor pattern106s. Accordingly, the first conductor pattern106sand the second conductor pattern110can form a PN-junction diode. In one embodiment, a top surface of the second conductor pattern110may be substantially coplanar with a top surface of the first conductor pattern106s. In another embodiment, the top surface of the second conductor pattern110may be higher than the top surface of the first conductor pattern106s.

In one embodiment, the second conductor pattern110may not include a semiconductor material with the second conductivity type. In such an embodiment, the second conductor pattern110may include a material that can form a Schottky contact with the first conductor pattern106s. Accordingly, the first conductor pattern106sand the second conductor pattern110can form a Schottky diode.

Referring toFIG. 10, a bottom electrode124is formed on the second conductor pattern110. In one embodiment, the bottom electrode124may be formed by forming a substantially uniform first electrode layer along a curvature of the entire surface of the semiconductor substrate having the second conductor pattern110so as to form a groove on the second conductor pattern110. A second electrode layer may then be formed on the first electrode layer to substantially fill the groove. Then, the first electrode layer and the second electrode layer are patterned (e.g., planarized) to form a first electrode112and the second electrode114. As exemplarily illustrated, the first electrode112is formed on the second conductor pattern110in the hole104and the second electrode114substantially fills the groove formed by the first electrode112.

Although not illustrated, a phase change layer and a top electrode can then be formed on the bottom electrode124to obtain the structure exemplarily shown inFIGS. 4A and 4B. As described above, the bottom electrode124is formed in the hole. In another embodiment, however, the second conductor pattern110may substantially fill the hole104. In such an embodiment, the bottom electrode124may be formed on the second conductor pattern110and the insulating layer102and the phase change layer and top electrode may then be formed on the bottom electrode124.

FIG. 11Ais a plan view of a phase change memory device according to a second embodiment.FIG. 11Bis a sectional view of the phase change memory device according to the second embodiment, taken along line III-III′ ofFIG. 11A.

Referring toFIGS. 11A and 11B, a phase change memory device of the second embodiment may, for example, include a substantially cylindrical bottom electrode124athat contacts a phase change layer116in, for example, a substantially circular contact area. An insulating core114amay be disposed over the bottom electrode124a. Because the contact area between the bottom electrode124aand the phase change layer116is substantially circular, the contact area between the bottom electrode124aand the phase change layer116may be less than the contact area between the bottom electrode124and the phase change layer116described above with respect toFIGS. 4A and 4B. Accordingly, phase change occurs at a lower current because heat generation may be increased.

An exemplary method of forming a bottom electrode124amay be similar to the above-described method of forming the bottom electrode124. For example, as illustrated inFIG. 10, a substantially uniform first electrode layer may be formed along a curvature on the entire surface of the semiconductor substrate having the second conductor pattern110so as to form a groove on the second conductor pattern110. Next, an insulating layer may be formed on the first electrode layer to substantially fill the groove. Then, the first electrode layer and the insulating layer may be patterned (e.g., planarized) to form a first electrode112and an insulating core114a. The first electrode112may be formed on the second conductor pattern110in the hole and the insulating core114asubstantially fills the groove formed by the first electrode112.

FIG. 12Ais a plan view of a phase change memory device according to a third embodiment.FIG. 12Bis a sectional view of the phase change memory device according to the third embodiment, taken along line IV-IV′ ofFIG. 12A.

Referring toFIGS. 12A and 12B, a phase change memory device of the third embodiment may, for example, include a bottom electrode124bthat substantially fills the hole104on the second conductor pattern110. The bottom electrode124bmay include at least one layer including a material such as titanium, titanium silicide layer, or the like or a combination thereof. In one embodiment, the bottom electrode124bmay consist of a single metal layer.

According to the embodiments exemplarily described above with respect toFIGS. 4A,4B,11A,11B,12A and12B, a heater may be formed to be interposed between the bottom electrode124and the phase change layer116. In this case, an insulating layer may be formed with an opening and then a heater material may fill the opening, thereby forming a heater. Additionally, a spacer may be formed in the opening, thereby reducing the width of the opening within which the heater is formed. Consequently, the contact area between the phase change layer and the heater can be decreased such that a sufficient amount of heat can be generated using a relatively low current.

FIGS. 13 and 14are sectional views of a phase change memory device according to fourth and fifth embodiments, respectively.

Referring toFIGS. 13 and 14, the phase change layer116amay be formed in an opening (also referred to herein as a “pin hole”) to increase a sheet resistance. For example, an insulating structure115having a pin hole117that exposes a bottom electrode124or124bmay be formed on the insulating layer102, and then the phase change layer116amay be formed to substantially fill the pin hole117. The phase change layer116aincreases the sheet resistance by reducing a sectional area. Thus, phase change may occur anywhere in the pin hole, due to the heat generated from the increased sheet resistance when a current flows. That is, the phase change layer116amay undergo a phase change due to a contact resistance between the phase change layer and the bottom electrode124or124b, or self-generated heat caused by the sheet resistance.

According to some embodiments, the insulator pattern108may be removed before forming the second conductor pattern110. In such embodiments, the second conductor pattern110may contact the sidewall of the first conductor pattern106sas well as a sidewall of an upper region of the hole104. In such a structure, a diode junction area between the first conductor pattern106sand the second conductor pattern110can be further increased. As a result, current flow can be increased.

According to the embodiments exemplarily described above, the sidewall of the first conductor pattern is contacted by the second conductor pattern to increase the contact area therebetween while occupying a relatively small area over the semiconductor substrate. Accordingly, the degree of integration does not need to be lowered to increase a driving current.

According to the embodiments exemplarily described above, phase change within the phase change layer can occur at a low current by reducing a contact area between the bottom electrode and the phase change layer or by applying various heating mechanisms to induce phase change.