Cascode power amplifier with voltage limiter

Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.

BACKGROUND

Field

The present disclosure generally relates to power amplifiers.

Description of the Related Art

In a cascode power amplifier, the voltage at the output is divided between the various devices used in the cascode ladder, reducing the voltage across each device to below a breakdown voltage of the device. In some implementations, each device of the cascode is biased at a different voltage to achieve enhanced performance. However, in most cascode architectures, the voltage bias is only optimized at one voltage.

SUMMARY

In accordance with some implementations, the present disclosure relates to a power amplification system. The power amplification system includes an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification system includes an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system includes a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter is configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.

In some embodiments, the high voltage limiter can include a high voltage limiter transistor having a high voltage limiter transistor gate coupled to the output transistor drain, a high voltage limiter transistor drain coupled to the output transistor drain, and a high voltage limiter transistor source coupled to the output transistor gate.

In some embodiments, the output transistor drain can be coupled to a supply voltage via an inductor.

In some embodiments, the power amplification system can include one or more middle transistors coupling the input transistor drain to the output transistor source. In some embodiments, the one or more middle transistors can include a first middle transistor having a first middle transistor gate coupled to the bias voltage and a first middle transistor drain coupled to the output transistor source.

In some embodiments, the power amplification system can include a low voltage limiter coupled between the supply voltage and the first middle transistor gate. The low voltage limiter can be configured to prevent the gate voltage of the first middle transistor from dropping below a low voltage threshold.

In some embodiments, the low voltage limiter can include a low voltage limiter transistor having a low voltage limiter transistor source coupled to the first middle transistor gate, a low voltage limiter transistor drain coupled to the supply voltage, and a low voltage limiter gate coupled to a supplemental bias voltage. In some embodiments, the supplemental bias voltage can be higher than the bias voltage.

In some embodiments, the power amplification system can include a second middle transistor having a second middle transistor gate coupled to the bias voltage, a second middle transistor drain coupled to the first middle transistor source, and a second middle transistor source coupled to the input transistor drain.

In some embodiments, the first middle transistor gate can be coupled to the bias voltage via a first RC circuit including a first resistor coupled between the first middle transistor gate and the bias voltage and a first capacitor coupled between the first middle transistor gate and the ground voltage. In some embodiments, the second middle transistor gate can be coupled to the bias voltage via a second RC circuit including a second resistor coupled between the second middle transistor gate and the bias voltage and a second capacitor coupled between the first middle transistor gate and the ground voltage. In some embodiments, the first capacitor can have a first capacitance and the second capacitor can have a second capacitance, the second capacitance being larger than the first capacitance.

In some embodiments, the output transistor gate is coupled to the bias voltage via an RC circuit including a resistor coupled between the output transistor gate and the bias voltage and a capacitor coupled between the output transistor gate and the ground voltage.

In some embodiments, the power amplification system can include an input bias circuit disposed at the input transistor gate.

In some embodiments, the power amplification can include an output match circuit disposed at the output transistor drain.

In some implementations, the present disclosure relates to a radio-frequency (RF) module including a packaging substrate configured to receive a plurality of components. The RF module includes a power amplification system implemented on the packaging substrate. The power amplification system includes an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification system includes an output transistor having an output transistor drain configured to output transistor gate configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system includes a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter is configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.

In some embodiments, the packaging substrate can include a silicon-on-insulator (SOI) substrate.

In some embodiments, the input transistor and output transistor can be complementary metal-oxide semiconductor (CMOS) transistors.

In some implementations, the present disclosure relates to a wireless device including a transceiver configured to generate a radio-frequency (RF) signal. The wireless device includes a front-end module (FEM) in communication with the transceiver. The FEM includes a packaging substrate configured to receive a plurality of components. The FEM further includes a power amplification system implemented on the packaging substrate. The power amplification system includes an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification system includes an output transistor having an output transistor drain configured to output transistor gate configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system includes a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter is configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold. The wireless device further includes an antenna in communication with the FEM. The antenna is configured to transmit the amplified RF signal received from the power amplification system.

In some embodiments, the power amplification system further includes a low voltage limiter configured to prevent a gate voltage of a transistor from dropping below a low voltage threshold.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

Described herein are circuits, systems, and methods for a dynamic biasing technique to set the gate voltages of cascode devices of a power amplification stage. The various implementations described herein may be beneficially used in processes where low breakdown voltages prohibit the use of one device as the power amplification stage, for example, in CMOS (complementary metal-oxide semiconductor) and SOI (silicon-on-insulator) processes, where devices can have a low drain-source and/or gate-drain breakdown voltage when compared to the desired output voltage levels needed to deliver a required amount of power.

FIG. 1shows an example architecture of a power amplification system100. The power amplification system100includes a power amplifier110with one or more transistors111. The power amplifier110receives a radio-frequency (RF) signal to be amplified at an RF input (RFin) terminal101and yields an amplified version of the RF signal (referred to as an amplified RF signal) at an RF output (RFout) terminal102. The power amplifier110is powered by a supply voltage (Vcc) received at a supply voltage terminal103and enabled or disabled by one or more bias voltages received at one or more bias terminals104. In particular, the bias voltages can bias one or more of the transistors111(e.g., to operate the transistors111in an active mode).

The power amplification system100further includes a voltage limitation system120which limits voltages across certain components of the power amplifier110, e.g., the transistors111. The voltage limitation system120includes a high voltage limiter121that prevents voltages from exceeding a high voltage threshold. For example, the high voltage limiter121can prevent voltages across one or more of the transistors from exceeding a breakdown voltage. The voltage limitation system120includes a low voltage limiter122that prevents voltages from dropping below a low voltage threshold. For example, the low voltage limiter122can prevent a gate voltage at one or more of the transistors from dropping below a bias voltage that places the transistor in an active mode.

FIG. 2shows that, in some implementations, a power amplification system200can include a cascode power amplifier. The power amplification system200includes four transistors211-214in a cascode topology. Each of the transistors211-214(and the other transistors described herein) can be MOSFET (metal-oxide-semiconductor field-effect transistor) transistors, such as those found in typical SOI processes. In some implementations, the transistors can be JFET (junction gate field-effect transistor), IGFET (insulated-gate field-effect transistor), BJT (bipolar junction transistor), or other types of transistors.

The power amplification system200includes an input transistor211having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification system200further includes an output transistor214having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage (Bias0), and an output transistor source. The output transistor drain is coupled to a supply voltage (Vcc) via an inductor251.

Coupling the input transistor drain and the output transistor source are one or more middle transistors212-213. In the implementation ofFIG. 2, the power amplification system200includes a first middle transistor213having a first middle transistor gate coupled to the bias voltage and a first middle transistor drain coupled to the output transistor source and further includes a second middle transistor212having a second middle transistor gate coupled to the bias voltage, a second middle transistor drain coupled to the first middle transistor source, and a second middle transistor source coupled to the input transistor drain.

As mentioned above, when an RF signal is applied to the gate of the input transistor211, an amplified version of the RF signal is output at the drain of the output transistor214. In some circumstances, the amplified version of the RF signal may include high voltages (e.g., during a positive half-cycle) such that the difference between the amplified version of the RF signal and the bias voltage applied to the gate of the output transistor would exceed a breakdown voltage of the output transistor214(e.g., approximately 3 to 4 volts). To prevent such an occurrence, the power amplification system200includes a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter is configured to prevent a gate-drain voltage of the output transistor214from exceeding a high voltage threshold, e.g., a breakdown voltage.

In the implementation ofFIG. 2, the high voltage limiter is implemented as a high voltage limiter transistor221having a high voltage limiter transistor gate coupled to the output transistor drain, a high voltage limiter transistor drain coupled to the output transistor drain, and a high voltage limiter transistor source coupled to the output transistor gate. When the voltage between the output transistor drain (the output signal) and the output transistor gate approaches or exceeds a high voltage threshold, the high voltage limiter transistor221feeds back the output signal to the output transistor gate and thereby provide one of several bias sources for the output transistor gate.

As the output transistor gate is coupled to the middle transistor gates (via RC elements described further below), the fed back output signal also provides one of several bias sources for the middle transistor gates, thereby preventing the gate-drain voltages of the middle transistors from exceeding a breakdown voltage.

As mentioned above, when an RF signal is applied to the gate of the input transistor211, an amplified version of the RF signal is output at the drain of the output transistor214. A less-amplified version of the RF signal is also present at the drain of the first middle transistor213. Similarly, an even-less-amplified version of the RF signal is also present at the drain of the second middle transistor212.

Due to the gate-drain capacitance of the first middle transistor213, the less-amplified version of the RF signal affects the voltage at the gate of the first cascode amplifier213. In some circumstances, this effect, particularly when the less-amplified version of the RF signal includes low voltages (e.g., during a negative half-cycle), could reduce the gate voltage to such an extent that the first middle transistor213is no longer in an active mode. To prevent such an occurrence, the power amplification system200includes a low voltage limiter coupled between the supply voltage and first middle transistor gate. Thee low voltage limiter is configured to prevent the gate voltage of the first middle transistor213from dropping below a low voltage threshold.

In the implementation ofFIG. 2, the low voltage limiter is implemented as a low voltage limiter transistor231having a low voltage limiter transistor source coupled to the first middle transistor gate, a low voltage limiter transistor drain coupled to the supply voltage, and a low voltage limiter gate coupled to a supplemental bias voltage (Bias1). The low voltage limiter transistor231feeds the supply voltage to the first middle transistor gate (and via the RC elements, other gates) and thereby provides one of several bias sources for the first middle transistor gate.

The output transistor gate is coupled to the bias voltage via an RC circuit including a resistor263coupled between the output transistor gate and the bias voltage and a capacitor273coupled between the output transistor gate and the ground voltage. The resistor263and capacitor273may be chosen to permit the amplified RF signal to pass (from the high voltage limiter transistor221) with some attenuation and thereby provide one of several bias sources for the gates of the middle transistors.

The first middle transistor gate is also coupled to the bias voltage via an RC circuit including a resistor262coupled between the first middle transistor gate and the bias voltage and a capacitor272coupled between the first middle transistor gate and the ground voltage. The resistor262and capacitor272may be chosen to provide sufficient attenuation of the amplified RF signal (the output signal) that will be present due to the gate-drain and gate-source capacitance of the first middle transistor213.

The second middle transistor gate is also coupled to the bias voltage via a RC circuit including a resistor261coupled between the second middle transistor gate and the bias voltage and a capacitor271coupled between the first middle transistor gate and the ground voltage. The resistor261and capacitor271may be chosen to remove any AC component and provide a DC bias voltage to the second middle transistor212. In particular, where the capacitor272has a first capacitance and the capacitor271has a second capacitance, the second capacitance may be larger than the first capacitance.

FIG. 3shows an example plot of the voltages at the drains of the transistors211-214ofFIG. 2over time when the amplified RF signal is greater than 10 volts. The voltage at the input transistor drain is shown by a first curve M30D, the voltage at the second middle transistor drain is shown by a second curve M31D, the voltage at the first middle transistor drain is shown by a third curve M32D, and the voltage at the output transistor drain is shown by a fourth curve M33D. As shown inFIG. 3, the differences between the drain voltages (and thus, the source-drain voltages M0, M1, M4are each below 3 volts and approximately equal.

FIG. 4shows an example plot of the voltages at the drains of the transistors211-214ofFIG. 2over time when the amplified RF signal is below 8.5 volts. As inFIG. 3, the voltage at the input transistor drain is shown by a first curve M30D, the voltage at the second middle transistor drain is shown by a second curve M31D, the voltage at the first middle transistor drain is shown by a third curve M32D, and the voltage at the output transistor drain is shown by a fourth curve M33D. As shown inFIG. 4, the differences between the drain voltages (and thus, the source-drain voltages M0, M2, M4are each below 3 volts and approximately equal. Further, the source-drain voltages M0, M2, M4are less inFIG. 4than inFIG. 3.

FIG. 5shows that, in some implementations, a power amplification system500can include multiple voltage limiters. The power amplification system500includes five transistors511-514in a cascode arrangement. Whereas the power amplification system200ofFIG. 2includes two middle transistors212-213, the power amplification system500ofFIG. 5includes three middle transistors512-514. In various implementations, a power amplification system can include any number of middle transistors, such as zero, one, two (as inFIG. 2), three, (as inFIG. 5), four, or more.

The power amplification system500ofFIG. 5includes an input transistor511having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. Coupled to the input transistor gate is an input bias circuit550configured to provide a bias voltage that places the input transistor511into an active mode. Although not shown, such an input bias circuit can also be implemented in the power amplification system200ofFIG. 2.

The power amplification system500further includes an output transistor515having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage (Bias0), and an output transistor source. The output transistor drain is coupled to a supply voltage (Vcc) via an inductor551. The output transistor drain is also coupled to an output match circuit540configured to provide impedance matching functionality for the power amplification system500. The output matching circuit540can, for example, be a low-pass/low-pass Class E output matching circuit. Although not shown, such an output matching circuit can also be implemented in the power amplification system200ofFIG. 2.

The power amplification system500further includes a high voltage limiter coupled between the output transistor drain and output transistor gate. As noted above, the high voltage limiter is configured to prevent a gate-drain voltage of the output transistor515from exceeding a high voltage threshold, e.g., a breakdown voltage of the output transistor515. As also noted above, in many implementations, a single high voltage limiter transistor and the connection of the output transistor gate and gates of the middle transistors512-514is sufficient to prevent the gate-drain voltage of the middle transistors512-514from exceeding a breakdown voltage. However, in other implementations (e.g., as shown inFIG. 5), the high voltage limiter includes multiple high voltage limiter transistors.

For example, the power amplification system500ofFIG. 5includes a first high voltage limiter transistor521having a first high voltage limiter transistor gate coupled to the output transistor drain, a first high voltage limiter transistor drain coupled to the output transistor drain, and a first high voltage limiter transistor source coupled to the output transistor gate. When the voltage between the output transistor drain (the output signal) and the output transistor gate approaches or exceeds a high voltage threshold, the first high voltage limiter transistor521feeds back the output signal to the output transistor gate. The power amplification system500further includes a second high voltage limiter transistor522having a second high voltage limiter transistor gate coupled to a middle transistor drain, a second high voltage limiter transistor drain coupled to a middle transistor drain, and a second high voltage limiter transistor source coupled to a middle transistor gate. When the voltage between the middle transistor drain and the middle transistor gate approaches or exceeds a high voltage threshold, the second high voltage limiter transistor521feeds voltage to the middle transistor gate.

The power amplification system500also includes a low voltage limiter coupled between the supply voltage and one or more middle transistor gates. As noted above, the low voltage limiter configured to prevent the gate voltage of the middle transistors from dropping below a low voltage threshold. As also noted above, in many implementations, a single low voltage limiter transistor and the connection of the gates of the middle transistors512-514is sufficient to prevent the gate-drain voltage of the middle transistors512-514from dropping below a low voltage threshold. However, in other implementations (e.g., as shown inFIG. 5), the low voltage limiter includes multiple low voltage limiter transistors.

For example, the power amplification system500ofFIG. 5includes a first low voltage limiter transistor531having a first low voltage limiter transistor source coupled to a first middle transistor gate, a first low voltage limiter transistor drain coupled to the supply voltage, and a first low voltage limiter transistor gate coupled to a first supplemental bias voltage (Bias1). The power amplification system500further includes a second low voltage limiter transistor532having a second low voltage limiter transistor source coupled to a second middle transistor gate, a second low voltage limiter transistor drain coupled to the supply voltage, and a second low voltage limiter gate coupled to a second supplemental bias voltage (Bias2). In some implementations, the first supplemental bias voltage and the second supplemental bias voltages are identical. For example, a single supplemental bias source can be coupled to both the first low voltage limiter transistor gate and the second low voltage limiter transistor gate. In other implementations, the second supplemental bias voltage is greater than (or less than) the first supplemental bias voltage.

The power amplification system500can include RC circuits (not shown) between the bias voltage and the gates of the middle transistors512-514and output transistor515as described above with respect to the power amplification system200ofFIG. 2.

FIG. 6shows a flowchart representation of a method600of amplifying an RF signal. In some implementations (and as detailed below as an example), the method600is at least partially performed by a power amplification system, such as the power amplification system200ofFIG. 2. In some implementations, the method600is at least partially performed by processing logic, including hardware, firmware, software, or a combination thereof. In some implementations, the method600is at least partially performed by a processor executing code stored in a non-transitory computer-readable medium (e.g., a memory).

The method600begins, at block610, with the power amplification system610receiving an RF signal at a gate of an input transistor. At block620, the power amplification system emits an amplified version of the RF signal from a drain of an output transistor. At block630, the power amplification system dynamically biases the voltage on the gate of the output transistor based on the amplified version of the RF signal.

In some implementations, dynamically biasing the voltage on the gate of the output transistor further includes dynamically biasing the voltage on the gate of one or more middle transistors. In some implementations, dynamically biasing the voltage on the gate of the output transistor includes providing a feedback signal from the drain of the output transistor to the gate of the output transistor. In some implementations, dynamically biasing the voltage on the gate of the output transistor includes limiting a voltage between the drain of the output transistor and the gate of the output transistor. In some implementations, dynamically biasing the voltage on the gate of the output transistor further includes limiting a voltage between the drain of a middle transistor and a gate of a middle transistor.

In some implementations, the feedback signal from the drain of the output transistor to the gate of the output transistor is provided by a high voltage limiter transistor coupled between the drain of the output transistor and the gate of the output transistor. In some implementations, the feedback signal is provided without a use of any transformer or balun.

FIG. 7shows that in some embodiments, some or all of the configurations (e.g., those shown inFIGS. 2 and 5) can be implemented, wholly or partially, in a module. Such a module can be, for example, a front-end module (FEM). In the example ofFIG. 7, a module700can include a packaging substrate702, and a number of components can be mounted on such a packaging substrate702. For example, an FE-PMIC component704, a power amplifier assembly706(which can include a voltage limiter707), a match component708, and a multiplexer assembly710can be mounted and/or implemented on and/or within the packaging substrate702. Other components such as a number of SMT devices714and an antenna switch module (ASM)712can also be mounted on the packaging substrate702. Although all of the various components are depicted as being laid out on the packaging substrate702, it will be understood that some component(s) can be implemented over other component(s).

In some implementations, a device and/or a circuit having one or more features described herein can be included in an RF electronic device such as a wireless device. Such a device and/or a circuit can be implemented directly in the wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, etc.

FIG. 8depicts an example wireless device800having one or more advantageous features described herein. In the context of a module having one or more features as described herein, such a module can be generally depicted by a dashed box700, and can be implemented as, for example, a front-end module (FEM).

Referring toFIG. 8, power amplifiers (PAs)820can receive their respective RF signals from a transceiver810that can be configured and operated in known manners to generate RF signals to be amplified and transmitted, and to process received signals. The transceiver810is shown to interact with a baseband sub-system808that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver810. The transceiver810can also be in communication with a power management component806that is configured to manage power for the operation of the wireless device800. Such power management can also control operations of the baseband sub-system808and the module700.

The baseband sub-system808is shown to be connected to a user interface8020to facilitate various input and output of voice and/or data provided to and received from the user. The baseband sub-system808can also be connected to a memory804that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user.

In the example wireless device800, outputs of the PAs820are shown to be matched (via respective match circuits822) and routed to their respective diplexers824. Such amplified and filtered signals can be routed to an antenna816(or multiple antennas) through an antenna switch814for transmission. In some embodiments, the diplexers824can allow transmit and receive operations to be performed simultaneously using a common antenna (e.g.,816). InFIG. 8, received signals are shown to be routed to “Rx” paths (not shown) that can include, for example, a low-noise amplifier (LNA).

A number of other wireless device configurations can utilize one or more features described herein. For example, a wireless device does not need to be a multi-band device. In another example, a wireless device can include additional antennas such as diversity antenna, and additional connectivity features such as Wi-Fi, Bluetooth, and GPS.