Memory system and method for operating the same

There are provided a memory system and a method for operating the same. A memory system includes: a controller for queuing a plurality of commands and outputting control signals in response to the plurality of queued commands; and a memory device for performing a program operation in response to the control signals, wherein, when the program operation fails, the controller holds the plurality of queued commands.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2017-0134676, filed on Oct. 17, 2017, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of Invention

Various exemplary embodiments of the present disclosure generally to relate to an electronic device. Particularly, the embodiments relate to a memory system including a nonvolatile memory device and a method for operating the memory system.

2. Description of the Related Art

The computer environment has evolved to the point where it is ubiquitous. That is, computing systems can be used anywhere and anytime. This promotes increased usage of portable electronic devices, such as mobile phones, digital cameras, notebook computers, and the like. Such portable electronic devices may generally include a memory system with a memory device, i.e., a data storage device. In such portable electronic devices, the data storage device is used as a main memory device or an auxiliary memory device.

A data storage device employed as a memory device has excellent stability and durability, high information access speed, and low power consumption, since there is no mechanical driving part. In memory systems having such advantages, the data storage device includes a universal serial bus (USB) memory device, memory cards having various interfaces, a solid state drive (SSD), and the like.

SUMMARY

Embodiments provide a memory system and a method for operating the same, which can improve the reliability of data by holding a read command waiting when a program operation of the memory system fails and then performing a recovery operation.

According to an aspect of the present disclosure, there is provided a memory system including: a controller configured to queue a plurality of commands and output control signals in response to the plurality of queued commands; and a memory device configured to perform a program operation in response to the control signals, wherein, when the program operation fails, the controller holds the plurality of queued commands.

According to an aspect of the present disclosure, there is provided a memory system including: a controller configured to queue a plurality of commands and output control signals in response to the plurality of queued commands; and a memory device configured to perform a program operation in response to the control signals, wherein, when the program operation fails, the memory device stores data in a new memory block by performing a recovery operation, wherein the controller holds the plurality of queued commands and then corrects a position corresponding to a read command among the plurality of commands to a position of the new memory block.

According to an aspect of the present disclosure, there is provided a method for operating a memory system, the method including: queuing a plurality of commands input from a host in a controller; generating control signals according to an order of the plurality of commands queued in the controller, and performing operations of a memory device, including a program operation, based on the control signals; and when a program operation among the operations fails, holding the generating of the control signals and performing a recovery operation of the program operation.

According to an aspect of the present disclosure, there is provided an electronic device comprising: a controller including a processor and a NAND flash controller; the processor being configured to queue a plurality of commands input from an external source in the NAND flash controller, and the NAND flash controller being configured to generate and output control signals in response to the plurality of queued commands; and a memory configured to perform a program operation on a select unit of data in response to the control signals, and after the program operation is completed, perform a status check operation to determine whether the program operation was successfully performed; wherein, when the status check operation indicates that the program operation was not successfully performed, the memory outputs a program status signal indicating that the program operation was not successfully performed, and in response to the program status signal, the NAND flash controller holds the operation of generating and outputting the control signals.

DETAILED DESCRIPTION

In the following detailed description, exemplary embodiments of the present disclosure are described. Such embodiments are described by way of illustration, not limitation. As those skilled in the art would realize from the following description, the described embodiments may be modified in various different ways, without departing from the spirit or scope of the present disclosure. Accordingly, the following description, along with the referenced drawings, are to be regarded as illustrative in nature and not restrictive.

Throughout the specification, when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the another element or be indirectly connected or coupled to the another element with one or more intervening elements interposed therebetween. In addition, when an element is referred to as “including” a component, such expression indicates that the element may further include one or more additional components instead of excluding additional component(s), unless clearly stated otherwise.

FIG. 1is a diagram illustrating an example of a data processing system including a memory system in accordance with an embodiment of the present disclosure.

Referring toFIG. 1, the data processing system100may include a host102and a memory system110.

The host102may include portable electronic devices such as mobile phones, MP3 players, and laptop computers or electronic devices such as desktop computers, game consoles, TVs, and projectors.

Memory system110operates in response to a request of the host102, which may access data stored by the memory system110. Memory system110may be used as a main memory device or auxiliary memory device of the host102. In one or more embodiments of the present disclosure, the memory system110may be implemented with any of various types of storage devices in accordance with a host interface protocol coupled to the host102. For example, the memory system110may be implemented with any of various types of storage devices such as a solid state drive (SSD), a multi-media card (MMC), embedded MMC (eMMC), reduced size MMC (RS-MMC) or micro-MMC, a secure digital (SD) card, mini-SD or micro-SD, an universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SMC) card, and a memory stick.

In addition, the storage devices for implementing the memory system110may be classified into (i) volatile memory devices such as dynamic random access memory (DRAM) and static random access memory (SRAM), and (ii) non-volatile memory devices such as read only memory (ROM), mask read only memory (MROM), programmable read only memory (PROM), electrically programmable read only memory (EPROM), electrically erasable and programmable read only memory (EEPROM), ferromagnetic random access memory (FRAM), phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and flash memory.

Also, the memory system110may include a memory device150that stores data accessed by the host102and a controller130that controls data to be stored in the memory device150.

In one or more embodiments of the present disclosure, the controller130and the memory device150may be integrated into one semiconductor device. As an example, the controller130and the memory device150may be integrated as a single semiconductor device to constitute an SSD. When the memory system110is used as the SSD, the operating speed of the host102coupled to the memory system110can be remarkably improved.

For example, the controller130and the memory device150may be integrated as a single semiconductor device to constitute a memory card. As another example, the controller130and the memory device150may be integrated as a single semiconductor device, to constitute a memory card such as a PC card (personal computer memory card international association (PCMCIA)), a compact flash (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC or MMCmicro), an SD card (SD, mini-SD, micro-SD or SDHC), or a universal flash storage (UFS).

To provide yet another example, the memory system110may constitute one of various components of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage that constitutes a data center, a device capable of transmitting/receiving information in a wireless environment, one of various electronic devices that constitute a home network, one of various electronic devices that constitute a computer network, one of various electronic devices that constitute a telemetics network, an RFID device, or one of various components that constitute a computing system.

Memory device150of the memory system110retains stored data even when power is not supplied. Memory system110stores data provided from the host102through a write operation, and provides stored data to the host102through a read operation.

In one or more embodiments of the present disclosure, memory device150may include a plurality of memory blocks152,154, and156, each of which includes a plurality of pages. In addition, each of the pages includes a plurality of memory cells coupled to a plurality of word lines. Also, the memory device150may include a plurality of planes in which the plurality of memory blocks152,154, and156are respectively included. In particular, the memory device150may include a plurality of memory dies in which the plurality of planes are respectively included. The memory device150may be a nonvolatile memory device, e.g., a flash memory. In such example, the flash memory may have a three-dimensional stack structure.

An exemplary structure of the memory device150including a three-dimensional stack structure of the memory device150is described in more detail with reference toFIGS. 2 to 4.

The controller130of the memory system110controls the memory device150in response to a request from the host102. The controller130provides data read from the memory device150to the host102, and stores data provided from the host102in the memory device150. To this end, the controller130controls read, write, program, and erase operations of the memory device150.

The controller130may include a host interface (host I/F) unit132, a processor134, an error correction code (ECC) unit138, a power management unit (PMU)140, a memory interface142such as a NAND flash controller (NFC), a queue holding controller144, and a memory146. The memory interface142and the queue holding controller144may be separate components as shown, for example, inFIG. 1. However, other arrangements are possible. For example, the queue holding controller144may be included in the memory interface142.

The host I/F unit132may process commands and data of the host102and may communicate with the host102through at least one of various interface protocols, such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a Serial-ATA protocol, a Parallel-ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

When data stored in the memory device150is read, the ECC unit138detects and corrects any error included in the read data. In other words, the ECC unit138may perform ECC decoding on the data read from the memory device150, determine whether the ECC decoding has succeeded, output an instruction signal based on the determined result, and correct error bits of the read data by using parity bits generated in an ECC encoding process. However, if the number of error bits is greater than or equal to a correctable error bit threshold value, ECC unit138cannot correct the error bits, and thus may output an error correction fail signal indicating that the error bits are not corrected.

The processor134controls overall operations of the memory system110, including a write or read operation on the memory device150in response to a write or read request from the host102. For example, the processor134drives firmware such as a flash translation layer (hereinafter referred to as ‘FTL’) to control the overall operations of memory system110. Processor134may be implemented with a microprocessor, a central processing unit (CPU), or the like. Also, the processor134may queue commands received from the host102in the memory interface142by allowing the commands to be arranged in an order of priority. Also, the processor134controls the memory device150to perform a recovery operation when it is determined that a program operation of the memory device150has failed. Also, the processor134may search for a read command having an address corresponding to that at which the program operation failed by reading commands held in the memory interface142. When the read command is identified, the processor134may correct the address of the read command to a recovered address and queue commands including the corrected read command in the memory interface142.

The ECC unit138may perform error correction by using coded modulation including low density parity check (LDPC) code, Bose, Chaudhuri, and Hocquenghem (BCH) code, turbo code, Reed-Solomon code, convolution code, recursive systematic code (RSC), trellis-coded modulation (TCM), block coded modulation, Hamming code, and the like, but the present disclosure is not limited to such error correction techniques. Rather, any other suitable error correction techniques may be used. Also, the ECC unit138may include a circuit, system, or device for error correction.

The PMU140provides and manages power of the controller130, i.e., power of components included in the controller130.

The memory interface142is a memory interface that performs interfacing between the controller130and the memory device150to control the memory device150in response to a request from the host102. When the memory device150is a flash memory, particularly a NAND flash memory, the memory interface142generates a control signal of the memory device150and processes data based on the control of the processor134.

Also, the memory interface142may store a plurality of commands queued by the processor134. The memory interface142may generate control signals corresponding to the queued commands sequentially in response to the commands and output or transmit the generated control signals to the memory device150. Also, the memory interface142may stop generating and transmitting the control signals by holding the queued commands, or re-perform the previously-stopped generating and transmitting operation of the control signals by releasing the held commands.

The queue holding controller144may selectively hold a command output operation or release the hold of the command output operation in response to a status check operation result P/S in the program operation of the memory device150. For example, the queue holding controller144holds the command output operation of the memory interface142when it is determined that the program operation of the memory device150has failed, and releases the held command output operation after the memory interface142stores commands newly queued by the processor134.

The memory146of the memory system110and the controller130may operate to store data for driving the memory system110and the controller130. For example, when the controller130controls operations such as a read operation, a write operation, a program operation, or an erase operation, the controller130stores data required to perform the operations in the memory146.

The memory146may be implemented with a volatile memory, such as a static random access memory (SRAM), a dynamic random access memory (DRAM), or the like. Also, the memory146stores data required to perform operations such as data write and read operations between the host102and the memory device150and data when the operations such as data write and read operations are performed. In order to store such data, the memory146may include a program memory, a data memory, a write buffer/cache, a read buffer/cache, a map buffer/cache, and the like.

The controller130may perform an operation requested from the host102in the memory device150through the processor134implemented with the microprocessor, the CPU, or the like. For example, the controller130performs, together with the memory device150, a command operation corresponding to a command received from the host102. In this example, the controller130may perform a foreground operation as a command operation corresponding to the command received from the host102.

Also, the controller130may perform a background operation on the memory device150through the processor134implemented with the microprocessor, the CPU, or the like. For example, the background operation on the memory device150may include an operation of performing a process by copying data stored in an arbitrary memory block in the memory blocks152,154, and156of the memory device150to another arbitrary memory block, e.g., a garbage collection operation, an operation of performing a process by swapping between the memory blocks152,154, and156of the memory device150or between data stored in the memory blocks152,154, and156, e.g., a wear leveling operation, an operation of allowing map data stored in the controller130to be stored in the memory blocks152,154, and156of the memory device150, e.g., a map flash operation, an operation of performing bad management on the memory device150, e.g., a bad block management operation of performing a process by checking bad blocks in a plurality of memory blocks152,154, and156included in the memory device150, or the like.

FIG. 2is a diagram illustrating the memory device in the memory system in accordance with an embodiment of the present disclosure.FIG. 3is a diagram illustrating an exemplary circuit of a memory cell array of memory blocks in the memory system in accordance with an embodiment of the present disclosure.FIG. 4is a diagram illustrating an exemplary structure of the memory device in the memory system in accordance with an embodiment of the present disclosure.

The memory device in the memory system in accordance with one or more embodiments of the present disclosure is described in more detail with reference toFIGS. 2 to 4.

Referring toFIG. 2, the memory device150may include a plurality of memory blocks, e.g., BLOCK0210, BLOCK1220, BLOCK2230, . . . and BLOCKN−1240(hereinafter, referred to as ‘block210to240’), each of which includes a plurality of pages, e.g., 2Mpages (labeled 2MPAGES inFIG. 2). For convenience of description, an arrangement in which each of the plurality of memory blocks includes 2Mpages is illustrated as an example, but each of the plurality of memory blocks may include a different number of pages, e.g., M pages. Each of the pages may include a plurality of memory cells to which a plurality of word lines are coupled.

Also, in the memory device150, the plurality of memory blocks may include a single level cell (SLC) memory block, a multi-level cell (MLC), and the like based on the number of bits of data stored in one memory cell. Here, the SLC memory block may include a plurality of pages implemented by memory cells each storing data of one bit, and has fast data calculation performance and high durability. The MLC memory block may include a plurality of pages implemented by memory cells each storing multiple bits of data (e.g., two or more bits of data), and has a data storage space larger than that of the SLC memory block. The MLC memory block including a plurality of pages implemented by memory cells each storing data of three or four bits may be classified as a triple level cell (TLC) or quad level cell (QLC) memory block.

Each of the blocks210to240stores data provided from the host102through a write operation, and provides the stored data to the host102through a read operation.

Referring toFIG. 3, in the plurality of memory blocks152,154, and156included in the memory device150of the memory system110, each memory block330may include a plurality of cell strings340implemented as a memory cell array respectively coupled to bit lines BL0to BLm−1. The cell string340of each column may include at least one drain select transistor SST, a plurality of memory cells MC0to MCn−1, and at least one source select transistor GST. The plurality of memory cells MC0to MCn−1 may be coupled in series between the select transistors SST and GST. Each of the memory cells MC0to MCn−1 may be configured as an MLC that stores information on data of a plurality of bits per cell. The cell strings340may be electrically coupled to corresponding bit lines BL0to BLm−1, respectively.

InFIG. 3, each memory block330configured as a NAND flash memory is illustrated by way of example only. However, the configuration of the plurality of memory blocks152,154, and156included in the memory device150is not limited to NAND flash memory. Rather, the memory block structure of memory device150may be implemented with a NOR flash memory, a hybrid flash memory in which at least two types of memory cells are combined, a One-NAND flash memory in which a controller is embedded in a memory chip, or the like. In addition, the memory block structure of memory device150may be implemented not only with a flash memory device in which a charge storage layer is configured with a conductive floating gate but also with a charge trap flash (CTF) memory device in which a charge storage layer is configured with an insulating layer, or the like.

A voltage supply unit310of the memory device150may provide word line voltages (e.g., a program voltage, a read voltage, a pass voltage, and the like) to be supplied to each of the word lines and a voltage to be supplied to a bulk (e.g., a well region) in which memory cells are formed based on an operation mode. In this case, a voltage generating operation of the voltage supply unit310may be performed under the control of a control circuit (not shown). Also, the voltage supply unit310may generate a plurality of variable read voltages to generate a plurality of read data. The voltage supply unit310may select one of memory blocks (or sectors) of the memory cell array and select one of word lines of the selected memory block in response to the control of the control circuit. The voltage supply unit310may provide a word line voltage to each selected word line and the other unselected word lines.

A read/write circuit320of the memory device150may be controlled by the control circuit and operate as a sense amplifier or a write driver based on an operation mode. For example, in a verify/normal read operation, the read/write circuit320may operate as a sense amplifier for reading data from the memory cell array. Also, in a program operation, the read/write circuit320may operate as a write driver for driving bit lines based on data to be stored in the memory cell array. In the program operation, the read/write circuit320may receive data to be written in the memory cell array from a buffer (not shown), and drive bit lines based on the received data. To this end, the read/write circuit320may include a plurality of page buffers (PB)322,324, and326, respectively corresponding to columns (or bit lines) or column pairs (or bit line pairs). A plurality of latches (not shown) may be included in each of the page buffers322,324, and326.

In addition, the memory device150may be implemented as a two-dimensional or three-dimensional memory device. In particular, the memory device150may be implemented as a nonvolatile memory device having a three-dimensional stack structure as shown inFIG. 4. When the memory device150is implemented in a three-dimensional structure, the memory device150may include a plurality of memory blocks BLK0to BLKN−1.FIG. 4is a block diagram illustrating the memory blocks152,154, and156of the memory device150shown inFIG. 1. Each of the memory blocks152,154, and156may be implemented in a three-dimensional structure (or vertical structure). For example, each of the memory blocks152,154, and156may include structures with dimensions extending along first to third directions, e.g., x-axis, y-axis, and z-axis directions, and be implemented in a three-dimensional structure.

FIG. 5is a flowchart illustrating an exemplary method for operating a memory system in accordance with one or more embodiments of the present disclosure.

Such a method will be described with reference not only toFIG. 5, but toFIGS. 1 to 4as well.

If a plurality of commands are input from the host102, the processor134queues commands in the memory interface142by allowing the commands to be arranged in an order of priority, at step S510. In addition, data corresponding to a program command among the plurality of commands are stored in the memory146.

The memory interface142generates control signals for operating the memory device150sequentially in response to the plurality of queued commands and processes the data. As an example, the memory interface142generates a plurality of control signals in response to the program command and transmits the generated control signals to the memory device. The memory interface142allows the data stored in the memory146to be transmitted to the memory device150.

The memory device150programs the data to at least one selected memory block among the plurality of memory blocks152,154, and156in response to the control signals transmitted from the memory interface142in a program operation, at step S520.

The program operation may be performed in units of pages. If the program operation of a selected page is completed, the memory device150performs a program status check operation to determine whether the program operation has been successfully performed, e.g. whether the status check operation passed, at step S530.

If it is determined that the status check operation on the selected page has passed (that is, ‘PASS’ at step S530), the memory device150performs a program operation of a next page. If it is determined that the status check operation has passed after the program operation of the last page is completed, the memory device150ends the program operation.

After that, the memory interface142generates control signals for operating the memory device150in response to a command queued next to the program command and processes data. As an example, when the command queued next to the program command is a read command for just previously programmed data, the memory interface142generates the control signals for operating the memory device150in response to the read command. The memory device reads data stored in the selected memory block and stores the read data in the page buffers (PB)322,324, and326and stores the stored data in the memory, at step S540. The data stored in the memory146are output to the host102.

Returning to step S530inFIG. 5, if the status check operation performed indicates that the program operation has failed (that is, ‘FAIL’ at step S530), the memory device150outputs a program status signal P/S that is a status check operation result, which in this instance, is indicative of program operation failure, and the queue holding controller144holds a control signal generating operation of the memory interface142in response to the program status signal P/S. That is, when it is determined that the status check operation has failed indicating failure of the program operation, the queue holding controller144holds the control signal generating operation of the memory interface142, at step S550.

When it is determined that the program operation has failed as indicated by the status check operation result of the memory device150, the processor134controls the memory device150to perform a recovery operation. That is, the processor134controls the memory interface142to perform a recovery operation based on stored firmware, and the memory interface142outputs control signals corresponding to the recovery operation to the memory device150.

If it is determined that the program operation has failed as indicated by the status check operation result of the memory device150, the memory device150transmits data stored in already programmed pages in the selected memory block on which program operation has failed to a new memory block and programs the data to the new memory block. That is, the memory device150transmits data stored in pages of which program operation has passed in the selected memory block on which program operation has failed to a new memory block and programs the data to the new memory block. After that, the memory device150performs a recovery operation by transmitting data of a page on which program operation has failed to a new memory block, using the data stored in the page buffers (PB)322,324, and326, and programming the data to the new memory block, at step S560.

The processor134reads the queued command stored in the memory interface142after the recovery operation of the memory device150, and checks whether, among the read commands, there is a read command for a memory block on which program operation has failed. At this time, when such a read command exists, the processor134corrects the memory block corresponding to the read command as a new recovered memory block, and newly queues the plurality of commands including the corrected read command in the memory interface142to be reconfigured, at step S570.

After the commands including the corrected read command are newly queued or re-queued in the memory interface142, the queue holding controller144controls the held memory interface142to be re-operated, at step S580. Therefore, the memory interface142generates control signals based on the newly queued commands and outputs the generated control signals to the memory device150. For example, when the program operation is completed after the recovery operation, and a next queued command is a read command for just previously programmed data, the memory interface142generates control signals for operating the memory device150in response to the read command. The memory device150reads data stored in the selected memory block and stores the read data in the page buffers (PB)322,324, and326. The stored data are stored in the memory146, at step S540.

To summarize, in accordance with one or more embodiments of the present disclosure, when the program operation has failed as indicated by the status check operation result, queued commands are held. When a read command exists among queued commands after the recovery operation of the memory device150, the address of the read command is corrected to include the position of a new recovered memory block, so that data recovered in the read operation can be read, thereby improving the reliability of data.

FIG. 6is a diagram schematically illustrating an example of the data processing system including the memory system in accordance with an embodiment of the present disclosure, and more particularly illustrating a memory card system to which the memory system of the present disclosure may be applied.

Referring toFIG. 6, the memory card system6100includes a memory controller6120, a memory device6130, and a connector6110.

More specifically, the memory controller6120is coupled to, and configured to access, the memory device6130, which may be implemented with a nonvolatile memory. For example, the memory controller6120is configured to control a read operation, a write operation, an erase operation, a background operation, and the like. Also, the memory controller6120is configured to provide an interface between the memory device6130and a host. The memory controller6120may be configured to drive firmware for controlling the memory device6130. That is, the memory controller6120may correspond to the controller130in the memory system110described inFIG. 1, and the memory device6130may correspond to the memory device150in the memory system110described inFIG. 1.

Accordingly, the memory controller6120may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, an ECC unit, and a queue holding control unit.

In addition, the memory controller6120may communicate with an external device, e.g., the host102described inFIG. 1through the connector6110. For example, the memory controller6120, as described inFIG. 1, may be configured to communicate with the external device through at least one of various communication protocols such as such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a Serial-ATA protocol, a Parallel-ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, FireWire, a universal flash storage (UFS) protocol, Wi-Fi, and Bluetooth. Accordingly, the memory system and the data processing system in accordance with one or more embodiments of the present disclosure can be applied to wired/wireless electronic devices, particularly, mobile electronic devices and the like.

In addition, the memory device6130may be implemented with a nonvolatile memory. For example, the memory device6130may be implemented with various nonvolatile memory devices such as an electrically erasable and programmable ROM (EPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), and a spin-torque magnetic RAM (STT-MRAM).

In addition, the memory controller6120and the memory device6130may be integrated into a single semiconductor device. As an example, the memory controller6120and the memory device6130may be integrated into a single semiconductor device to constitute a solid state drive (SSD). The memory controller6120and the memory device6130may be integrated into a single semiconductor device to constitute a memory card such as a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, mini-SD, micro-SD, SDHC) or a universal flash storage (UFS).

FIG. 7is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment of the present disclosure.

Referring toFIG. 7, the data processing system6200includes a memory device6230implemented with at least one nonvolatile memory and a memory controller6220that controls the memory device6230. Here, the data processing system6200shown inFIG. 7, as described inFIG. 1, may be a storage medium such as a memory card (CF, SD, micro-SD, etc.) or a USB storage. The memory device6230may correspond to the memory device150in the memory system110described inFIG. 1, and the memory controller6220may correspond to the controller130in the memory system110described inFIG. 1.

In addition, the memory controller6220controls a read operation, a write operation, an erase operation, and the like on the memory device6230in response to a request of a host6210, and the memory controller6220includes at least one CPU6221, a buffer memory, e.g., a RAM6222, an ECC circuit6223, a host interface6224, and a memory interface, e.g., an NVM interface6225. In addition, the queue holding controller144ofFIG. 1may be included in the NVM interface6225and hold an operation of the NVM interface6225when a program operation fails.

The CPU6221may control overall operations of the memory device6230, e.g., read, write, file system management, bad page management, and the like. In addition, the RAM6222operates based on the control of the CPU6221, and may be used as a work memory, a buffer memory, a cache memory, or the like. When the RAM6222is used as a work memory, data processed by the CPU6221may be temporarily stored. When the RAM6222is used as a buffer memory, the RAM6222may be used to buffer data transmitted from the host6210to the memory device6230or data transmitted from the memory device6230to the host6210. When the RAM6222is used as a cache memory, the RAM6222may be used to allow the low-speed memory device6230to operate at high speed.

In addition, the ECC circuit6223corresponds to the ECC unit138of the controller130described inFIG. 1, and generates an error correction code (ECC) for correcting a fail bit or error bit of data received from the memory device6230as described inFIG. 1. Also, the ECC circuit6223performs error correction encoding on data provided to the memory device6230to generate data to which a parity bit is added. Here, the parity bit may be stored in the memory device6230. Also, the ECC circuit6223may perform error correction decoding on data output from the memory device6230. In this case, the ECC circuit6223may correct an error using a parity. For example, the ECC circuit6223, as described inFIG. 1, may correct an error using various coded modulations such as LDPC code, BCH code, turbo code, Reed-Solomon code, convolution code, RSC, TCM, and BCM.

In addition, the memory controller6220communicates data, and the like with the host6210through the host interface6224, and communicates data, and the like with the memory device6230through the NVM interface6225. Here, the host interface6225may be coupled to the host6210through a PATA bus, SATA bus, SCSI, USB, PCIe, a NAND interface, and the like. Also, the memory controller6220may be coupled to the external device, e.g., the host6210or another external device except the host6210as a wireless communication function, Wi-Fi or long term evolution (LTE) as a mobile communication standard, or the like is implemented, and then communicate data, and the like, with the external device. In particular, the memory controller6220is configured to communicate with the external device through at least one of various communication standards. Accordingly, the memory system and the data processing system in accordance with one or more embodiments of the present disclosure can be applied to wired/wireless electronic devices, particularly, mobile electronic devices, and the like.

FIG. 8is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment of the present disclosure, and more particularly illustrating a solid state drive (SSD) to which the memory system is applied.

Referring toFIG. 8, the SSD6300includes a memory device6340including a plurality of nonvolatile memories and a controller6320. The controller6320may correspond to the controller130in the memory system110described inFIG. 1, and the memory device6340may correspond to the memory device150in the memory system110described inFIG. 1.

More specifically, the controller6320is coupled to the memory device6340through a plurality of channels CH1, CH2, CH3, . . . , and CHi. Also, the controller6320includes at least one processor6321, a buffer memory6325, an ECC circuit6322, a host interface6324, and a memory interface, e.g., a nonvolatile memory interface6326. The nonvolatile memory interface6326may be configured to include the queue holding controller144ofFIG. 1.

The buffer memory6325temporarily stores data received from a host6310or data received from a plurality of flash memories NVMs included in the memory device6340, or temporarily stores meta data of the plurality of flash memories NVMs, e.g., map data included in a mapping table. Also, the buffer memory6325may be implemented with volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, SRAM, and GRAM or nonvolatile memories such as FRAM ReRAM, STT-MRAM, and PRAM. For convenience of description, an example in which the buffer memory6325is inside the controller6320is illustrated inFIG. 8, but the buffer memory6325may be outside the controller6320.

The ECC circuit6322calculates an error correction code value of data to be programmed to the memory device6340in a program operation, performs an error correction operation on data read from the memory device6340in a read operation, based on the error correction code value, and performs an error correction operation on data restored from the memory device6340in a restore operation of fail data.

In addition, the host interface6324provides an interface function between the controller6320and an external device, e.g., the host6310, and the nonvolatile memory interface6326provides an interface function between the controller6320and the memory device6340coupled to the controller6320through the plurality of channels.

In addition, the SSD6300to which the memory system110described inFIG. 1may be applied in multiple instances to implement a data processing system, e.g., a redundant array of independent disks (RAID) system. In this case, a plurality of SSDs6300and a RAID controller that controls the plurality of SSDs6300. When a program operation is performed by receiving a write command from the host6310, the RAID controller may select at least one memory system, i.e., an SSD6300among the plurality of SSDs6300, corresponding to a plurality of RAID levels, i.e., RAID level information of the write command received from the host6310, and then output data corresponding to the write command to the selected SSD6300. Also, when a read operation is performed by receiving a read command from the host6310, the RAID controller may select at least one memory system, i.e., an SSD6300among the plurality of SSDs6300, corresponding to a plurality of RAID levels, i.e., RAID level information of the read command received from the host6310, and then provided data from the selected SSD6300to the host6310.

FIG. 9is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment of the present disclosure, and more particularly illustrating an embedded multimedia card (eMMC) to which the memory system is applied.

Referring toFIG. 9, the eMMC6400includes a memory device6440implemented with at least one NAND flash memory and a controller6430. Here, the controller6430may correspond to the controller130in the memory system110described inFIG. 1, and the memory device6440may correspond to the memory device150in the memory system110described inFIG. 1.

More specifically, the controller6430is coupled to the memory device6440through a plurality of channels. Also, the controller6430includes at least one core6432, a host interface6431, and a memory interface, e.g., a NAND interface6433. The NAND interface6433may be configured to include the queue holding controller144ofFIG. 1.

Here, the core6432controls overall operations of the eMMC6400, the host interface6431provides an interface function between the controller6430and a host6410, and the NAND interface6433provides an interface function between the memory device6440and the controller6430. For example, the host interface6431, as described inFIG. 1, may be a parallel interface, e.g., an MMC interface. In addition, the host interface6431may be a serial interface, e.g., an ultra high speed (UHS)-I/UHS-II, UFS interface.

In accordance with one or more embodiments of the present disclosure, when a program operation of the memory system fails, a recovery operation is performed after queued commands are held. The held commands are released after the address of a read command among the held commands is changed to the recovered position, thereby improving the reliability of data.