Alignment pattern for package singulation

A method includes forming an alignment pattern over an insulating layer formed over a carrier. A die is mounted over the carrier and encapsulated. Connectors are formed and the structure is attached to a debond tape. The carrier is removed. A cutting device is aligned to a backside of the insulating layer using the alignment pattern. The first insulating layer and encapsulant are cut from the backside of the insulating layer. Another method includes scanning a backside of a packages structure for an alignment pattern in a first package area of the packages structure. A cutting device is aligned to a cut-line in a non-package area of the packages structure based on the alignment pattern and packages are singulated. An InFO package includes an insulating layer on the backside, the insulating layer having a laser marking thereon. The InFO package also includes an alignment pattern proximate to the insulating layer.

BACKGROUND

As semiconductor technologies further advance, stacked and bonded semiconductor devices have emerged as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits and the like are fabricated at least partially on separate substrates and then physically and electrically bonded together in order to form a functional device. Such bonding processes utilize sophisticated techniques, and improvements are desired.

DETAILED DESCRIPTION

In packaged device manufacturing, dies or devices can be formed or placed on a carrier. A molding compound can be deposited over the dies or devices. A redistribution layer (RDL) structure can be formed over the devices and provide interconnects to the dies or devices. A contact pad layer can provide contact pads on a front surface of the packaged device. The contact pads can feature a connector, such as a solder ball or conductive pillar, disposed thereon for connection to another device, interposer, or the like. The front side of the package can be considered the side with the contact pads and the back side of the package can be considered the side of the package that is mounted to the carrier. The package can feature logic dies, memory dies, or a combination thereof. The dies can include for example, a dynamic random access memory (DRAM) die and a system-on-chip (SoC) die. Other dies and devices can be used as well. The RDL structure can provide an integrated fan out (InFO) connection to the dies, thereby internally routing signals between dies, between connectors of a single die, and between dies and one or more external contact pads. After the packaged devices are formed on the carrier, they are singulated into individual packages.

Embodiments, such as those discussed herein, provide singulation of a packaged semiconductor device, such as an integrated fan out (InFO) package. A plurality of InFO packages can be developed and formed on a carrier substrate, such as a carrier substrate wafer. An InFO package or multiple InFO packages can be formed on a front side of the carrier. The InFO package can include a backside alignment pattern to provide an alignment identifier for a saw or other cutting device for singulation of the InFO packages. After the package is created on the carrier, external connectors (e.g., a ball grid array (BGA)) are formed, debond tape can be attached to the external connectors, and the carrier can be removed. The packages can be laser marked on their backsides. Then the device can be singulated from the backside. The alignment pattern can be detected on the backside by an alignment detection device. The alignment detection device can align the saw or other cutting device and the cutting device can singulate the InFO package or multiple InFO packages by cutting the backside of the InFO packages.

FIGS. 1athrough 10cillustrate cross-sectional views of intermediate steps in forming a die package100in accordance with some embodiments.FIGS. 1a, 2a, 3a, 4a, and 10aillustrate embodiments where an alignment pattern is embedded in an encapsulant.FIGS. 1b, 2b, 3b, 4b, and 10billustrate embodiments where an alignment pattern is in a layer along with an insulating material and optional conductive features and/or a seal ring.FIGS. 1c, 2c, 3c, 4c, and 10cillustrate embodiments where an alignment pattern is in a layer along with an insulating material, while optional conductive features and/or a seal ring are in a separate adjacent layer.FIGS. 5-9illustrate embodiments such as those consistent withFIG. 1b, however, the features discussed therein can readily be applied to the other illustrated embodiments. These embodiments are explained in detail below.

FIG. 1aincludes a group of packages, such as package100aand100b, which includes a glue layer103formed over a carrier substrate101, a first insulating layer105formed over the glue layer103, and alignment pattern115formed over the first insulating layer105.

The carrier substrate101may be a wafer including glass, silicon (e.g., a silicon wafer), silicon oxide, aluminum oxide, metal plate, a ceramic material, an organic material, or the like. In some embodiments, the carrier101can be a tape. The carrier substrate101includes package regions150and non-package regions160. Packages, such as package100aand100b, are formed in the package regions150. Package regions150include design areas for forming features of the packages, including features such as one or more die mounting areas, fan-out redistribution layer(s), metal lines, a connector array, and so forth.

Non-package regions160are reserved for dicing streets or scribe lines for package singulation. Non-package regions160are free from design features, such as metal lines and devices. After formation of the packages100, the packages100can be separated into, for example package100aand100b, by cutting the packages apart through the dicing streets. It should be understood that, although packages100aand100bare specifically illustrated, the group of packages100can comprise additional packages formed on carrier101. Additional packages can each be identical to one another, different from one another, or a combination thereof.

Referring toFIG. 1a, the adhesive layer103is disposed on the carrier substrate101in order to assist in the adherence of overlying structures, for example, the first insulating layer105to the carrier substrate101. In later steps, the adhesive layer103also aids in the debonding of the carrier101from the packages. In some embodiments, the adhesive layer103can include an ultra-violet glue, which loses its adhesive properties when exposed to ultra-violet light. However, other types of adhesives, such as pressure sensitive adhesives, radiation curable adhesives, epoxies, combinations of these, or the like, may also be used. The adhesive layer103can be placed onto the first carrier substrate101in a semi-liquid or gel form, which is readily deformable under pressure.

A first insulating layer105is disposed over the adhesive layer103. The first insulating layer105is placed over the adhesive layer103and is utilized in order to provide protection to the package, e.g., once completed, the underlying devices and structures of the package. The first insulating layer105also provides a surface on which manufacturer marking can occur, to mark the package with information, such as identification or manufacturing information. In an embodiment the first insulating layer105may be a polymer such as polybenzoxazole (PBO), although any suitable material, such as polyimide, a polyimide derivative, benzocycloutene (BCB), or an epoxy, may alternatively be utilized. The first insulating layer105may be placed using, e.g., a spin-coating process to a thickness of between about 0.5 μm and about 10 μm, such as about 5 μm, although any suitable method and thickness may alternatively be used. The first insulating layer105can be transparent or translucent. In some embodiments, the first insulating layer105can be colored.

An alignment pattern115is disposed over the first insulating layer105. In some embodiments, alignment pattern115is formed on a front side105A of the first insulating layer105. In some embodiments, the alignment pattern115is made of conductive material. In some embodiments, the alignment pattern115is a dummy structure which is electrically decoupled or electrically isolated from any of the subsequently formed conductive elements. In other embodiments, the alignment pattern115can be electrically and/or physically coupled to subsequently bonded dies or other conductive elements, such as metal lines, traces, or electrical connectors.

In some embodiments, the alignment pattern115is formed by depositing a seed layer over the first insulating layer105. The seed layer (not shown) can be made of copper (Cu), tungsten (W), gold (Au), silver (Ag), aluminum, (Al), lead (Pb), tin (Sn), alloys of the same, or the like. A sacrificial layer, such as a photoresist, is deposited over the seed layer and patterned to form openings therein according to the layout of the alignment pattern115. Generally, photolithography techniques involve depositing a photoresist material (not shown), which is subsequently irradiated (exposed) and developed to remove a portion of the photoresist material. The remaining photoresist material prevents the formation of other materials thereon, such as the conductive material of alignment pattern115.

Conductive material is deposited in the openings over the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. In an embodiment, the conductive material of the alignment pattern115is copper (Cu), tungsten (W), gold (Au), silver (Ag), aluminum, (Al), lead (Pb), tin (Sn), alloys of the same, or the like. Subsequently, the photoresist is removed, for example by an ashing technique, and the exposed seedlayer is stripped using a suitable etchant.

In another embodiment, the alignment pattern115is formed by depositing conductive material over the first insulating material105, for example, by CVD, ALD, PVD, the like, or a combination thereof. A photoresist is deposited over the conductive material and patterned using photolithography techniques to form openings where the conductive material will be removed. The remaining photoresist material protects the underlying material, such as the conductive material of alignment pattern115from subsequent processing steps, such as etching. A suitable etching process, such as a reactive ion etch (RIE) or other dry etch, an isotropic or anisotropic wet etch, or any other suitable etch or patterning process may be applied to the conductive material to remove exposed portions of the conductive material and form the alignment pattern115. Subsequently, the photoresist material may be removed using, for example, an ashing process followed by a wet clean process.

In some embodiments, the alignment pattern115is made of a non-conductive material, such as an insulating material, including a polymer or dielectric. In such embodiments, the insulating material should be visibly different than first insulating layer105and any overlying structures such that a visible difference can be distinguished between the non-conductive alignment pattern115and overlying layers when viewed from the back side. In some embodiments, the alignment pattern115can be formed and cured differently than other non-conductive material surrounding the alignment pattern such that the differently cured alignment pattern is distinguishable from the surrounding material. For example, curing the alignment pattern at 220° C. for 1 hour and the surrounding material at 190° C. for 3 hours (or vice versa) may provide alignment pattern115as distinguishable from the first insulating layer105.

In an embodiment, non-conductive alignment pattern115may be a polymer, such as PBO, an epoxy, BCB, polyimide, or a polyimide derivative. The non-conductive alignment pattern115may be formed by depositing a second insulating layer, such as a polymer, using, e.g., a spin-coating process to a thickness of between about 5 μm and about 20 μm, such as about 10 μm and cured to result in a cured thickness of about 2 μm to about 10 μm, such as about 4 μm, although any suitable method and thickness may alternatively be used. In another embodiment, the second insulating layer may be another suitable dielectric such as silicon nitride, silicon carbide, silicon oxide, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, or a combination thereof, although other relatively soft, often organic, dielectric materials can also be used. The second insulating layer may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), a spin-on-dielectric process, the like, or a combination thereof.

Subsequently, the non-conductive alignment pattern115is formed from the second insulating layer using a photolithography process similar to the process described above, and is not repeated here. It should be noted, however, that in such embodiments, it may be desirable to form the second insulating layer from a material other than the material of the first insulating layer105to provide the ability to selectively etch the portions of the second insulating layer without damaging the first insulating layer105. Alternatively, an etch stop layer (not shown) can be formed between the first insulating layer and the second insulating layer to prevent etching first insulating layer105when removing portions of the second insulating layer.

Referring toFIG. 1a, an embedded alignment pattern115eis illustrated as being embedded in the first insulating layer, in accordance with some embodiments. The alignment pattern115eis formed by making recesses or openings (not shown) in the first insulating layer105. Such recesses may be formed to embed the alignment pattern115einto the first insulating layer105. The recesses may be formed, for example, by etching the first insulating layer105using a photolithography technique to form recesses or openings therein. In some embodiments where the alignment pattern115eis a conductive material, a seed layer can be deposited in the recesses or openings and a second patterned photoresist can be formed (before or after removing the first photoresist) over the first insulating layer105. The recesses or openings can then be plated, such as by electroplating or electroless plating, or the like to form the alignment pattern115e. The photoresists are removed along with the exposed seed layer. In some embodiments where the alignment pattern115eis a non-conductive material, a second insulating material can be deposited in the recesses or openings as part of a second insulating layer over the first insulating layer105. In some embodiments, the second insulating layer can be patterned using photolithography techniques and excess portions removed by a suitable etchant. In some embodiments, the second insulating layer can be removed using a mechanical process, such as by CMP or grinding to remove the second insulating layer from the top of the first insulating layer105, thereby leaving a portion of the second insulating layer in the recesses or openings in the first insulating layer105to form the alignment pattern115e.

In some embodiments, an embedded alignment pattern115ecan be combined with other embodiments to form alignment patterns in different layers of the packages. Although the alignment pattern115eis not specifically described in the other embodiments discussed below, it should be understood that forming an embedded alignment pattern115ecan also be performed in the other discussed embodiments below instead of, or in addition to, the alignment pattern115discussed below.

Referring toFIG. 1b, in some embodiments, additional conductive features120can be formed on the first insulating layer105. The conductive features120can include traces, shields, conductive lines, contacts, contact pads, vias, and so forth in the package regions150of the packages100. It should be understood that the conductive features120can be discontinuous and go in and out of the page. In some embodiments, the conductive features120can include a portion of a redistribution layer (RDL) structure or interconnect layer to provide interconnects between devices, pins, or contacts contained in the packaged device.

Still referring toFIG. 1b, in some embodiments, a seal ring structure125can be formed on the first insulating layer105. In some embodiments, the conductive features120and seal ring125can be made at the same time and of the same materials as alignment pattern115. As such, the alignment pattern115, conductive features120, and seal ring125can each have the same thickness. The process for making conductive features120and seal ring125is similar to the process for making the alignment pattern115and is not repeated.

The areas on the first insulating layer105which do not have an alignment pattern115, conductive features120, or seal ring125can be filled with a second insulating material130to create a second layer110. In some embodiments, the second insulating material130can be added after the formation of the formation of the alignment pattern115, conductive features120, and seal ring125. The second insulating material130can include a polymer, such as PBO, an epoxy, BCB, polyimide, or a polyimide derivative. The second insulating material130may be placed using, e.g., a spin-coating process to a thickness of between about 5 μm and about 20 μm, such as about 10 μm and cured to result in a cured thickness of about 2 μm to about 10 μm, such as about 4 μm, although any suitable method and thickness may alternatively be used. In another embodiment, second insulating material130may be a suitable dielectric such as silicon nitride, silicon carbide, silicon oxide, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, or a combination thereof, although other relatively soft, often organic, dielectric materials can also be used. The second insulating material130may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), a spin-on-dielectric process, the like, or a combination thereof.

In some embodiments, the alignment pattern115, conductive features120, and seal ring125can each be made of different materials in different processing steps. For example, the alignment pattern115can be made using a mask as described above with respect toFIG. 1a, and in a separate step another mask can be used to make conductive features120and/or seal ring125. In some embodiments, alignment pattern115can be made of the same material as the seal ring125. In some embodiments, the conductive features120and seal ring125can be made of the same material. The conductive features120and seal ring125are optionally included in the layer110.

Referring toFIG. 1c, in some embodiments, conductive features120and seal ring125can be formed in or carried through in additional layers, such as layer111over the layer110. In some embodiments, alternating insulating layers and conductive layers can be formed and patterned to form a backside redistribution layer (not shown). A process of forming a redistribution layer is further described below with reference toFIG. 4.

Second insulating material130can be included in layer111in areas of layer111which do not contain a seal ring125or conductive features120. Second insulating material130of layer111(and other layers) can be formed in a manner consistent with that described above in relation toFIG. 1b and is not repeated.

In some embodiments, additional layers, such as layer111and subsequent layers can be included in the embodiments illustrated inFIGS. 1aand 1b. Referring to any ofFIGS. 1a-1c, alignment pattern115can be formed in a subsequent layer. In other words, alignment pattern115need not be in the first layer over first insulating layer105. For example, layer111and layer110(containing the alignment pattern115) can be in reverse positions. In some embodiments alignment pattern115can be repeated in multiple layers, e.g., in both layer110and111, and so forth.

Referring to any ofFIGS. 1a-1c, alignment pattern115can be disposed within the package region150close to an edge of the package region150. In some embodiments, alignment pattern115is disposed outside of a die mounting region (151ofFIG. 3) of the chip package device100a/100band not within any die mounting region, for example, outside die mounting region151between an edge of a die and seal ring125.

FIG. 2aillustrates a plan view of a portion of the workpiece featured inFIG. 1a. The dashed box indicates the package region150. Areas outside the dashed boxes indicate the non-package region160. An alignment pattern115is located in each package region150. The line AA indicates a cross section cut-line forFIG. 1a. Carrier101is under first insulating layer105.

FIG. 2billustrates a plan view of a portion of the workpiece featured inFIG. 1b. The dashed box indicates the package region150. An alignment pattern115is located in each package region150. Additional conductive features120are illustrated by the textured rectangular shape. As discussed above, the conductive features120block represents various lines that may be used for signal, power, and ground routing purposes. A seal ring125is formed around near the perimeter of the package region150. The line AA indicates a cross section cut-line forFIG. 1b. Layer110is visible.

FIG. 2cillustrates a plan view of a portion of the workpiece featured inFIG. 1c. The dashed box indicates the package region150. An alignment pattern115is located in each package region150. The lighter alignment pattern115indicates that it is covered by layer111, but is still visible. Additional conductive features120are illustrated by the textured rectangular shape. A seal ring125is formed around near the perimeter of the package region150. The line AA indicates a cross section cut-line forFIG. 1c. Layer111is visible.

Referring to any ofFIGS. 2a-2c, although one alignment pattern is located in each of the package regions for package100aand100b, it should be understood that multiple alignment patterns may be included. Further, the alignment pattern115depicted is merely an example, and other shapes can be used, as explained in greater detail below.

Referring further toFIG. 3a, conductive vias205are formed on the first insulating layer105. In some embodiments the conductive vias205are formed over the first insulating layer105and extend from the first insulating layer105in a direction that is substantially perpendicular to the first side105A (e.g.,FIG. 1a) of the first insulating layer105.

In some embodiments, a seed layer (not shown) may be interposed between the conductive vias205and the first insulating layer105. In some embodiments the seed layer may comprise copper, titanium, nickel, gold, the like, or a combination thereof, and may be formed using an electro-chemical plating process, ALD, PVD, sputtering, the like, or a combination thereof.

In some embodiments, a sacrificial layer is formed over the seed layer. Openings are formed in the sacrificial layer to expose portions of the seed layer disposed in the openings. In some embodiments wherein the sacrificial layer comprises a photoresist material, the sacrificial layer may be patterned using suitable photolithography methods. Conductive vias205can be formed in the openings by filling them with a conductive material such as copper, aluminum, nickel, gold, silver, palladium, the like, or a combination thereof using an electro-chemical plating process, an electroless plating process, ALD, PVD, the like, or a combination thereof to form conductive vias205. After the formation of the conductive vias205is completed, the sacrificial layer is removed. In some embodiments wherein the sacrificial layer comprises a photoresist material, the sacrificial layer may be removed using, for example, an ashing process followed by a wet clean process. Subsequently, exposed portions of the seed layer are removed using, for example, a suitable etching process.

In some embodiments, the conductive vias205may be stud bumps, which are formed by wire bonding on the seed layer or on a conductive pad, and cutting the bond wire with a portion of bond wire left attached to the seed layer of the conductive pad. The upper portion of the conductive via205may have a uniform width and a uniform shape that are uniform throughout the top part, the middle part, and the bottom part of upper portion. The conductive vias205may be formed of non-solder metallic materials that can be bonded by a wire bonder. In some embodiments, the conductive vias205are made of copper wire, gold wire, the like, or a combination thereof, and may have a composite structure including a plurality of layers.

Referring toFIG. 3b, in some embodiments wherein a layer110is formed and includes the alignment pattern115and second insulting material130, as well as other features such as conductive features120and seal ring125, such as inFIG. 1b, the conductive vias205can be formed on the second insulating material130or on the conductive features120of layer110. Conductive vias205can be formed using the processes described above with respect toFIG. 3aand is not repeated.

Referring toFIG. 3c, in some embodiments, wherein a layer110is formed and includes the alignment pattern115and second insulating material130, in addition to one or more additional layers including other features such as conductive features120, seal ring125, or insulating material130in a separate layer111, such as illustrated inFIG. 1c, the conductive vias205can be formed on the insulating material130or on the conductive features120of layer111. These conductive vias205can be formed using the processes described above with respect toFIG. 3aand is not repeated.

Referring toFIG. 4a, one or more integrated circuit dies210/215are attached to the first insulating layer105using adhesive layers212. In some embodiments, the integrated circuit dies210/215are placed on the first insulating layer105using, for example, a pick-and-place apparatus. In other embodiments, the integrated circuit dies210/215may be placed on the first insulating layer105manually, or using any other suitable method. In some embodiments, the adhesive layer212may comprise an LTHC material, a UV adhesive, a die attach film, or the like, and may be formed using a spin-on coating process, a printing process, a lamination process, or the like.

In some embodiments, the alignment pattern115is used to precisely align the die(s)210/215on the first insulating layer105. In embodiments using a backside RDL structure, for example, precise alignment can avoid shifting of the dies210/215, which may cause electrical failures of the package100a, for example. The dies210/215are not bonded to the alignment pattern115and the alignment pattern115is still visible from above after the dies210/215are attached. A first die stack includes die210and corresponding adhesive layer211. A second die stack includes die215and corresponding adhesive layer211. As seen inFIG. 4a, in some embodiments the bottom of the first and second die stacks can be substantially coplanar with the bottom of the alignment pattern115. Similarly, the top of the alignment pattern115can be in a plane higher than the plane of the bottom of the dies210/215and the bottom of the first and second die stacks.

Integrated circuit dies210/215can include one or more dies suited for the package design. For example, dies can include a logic die215such as a system on chip (SoC) die, central processing unit (CPU), a graphics processing unit (GPU), or the like and/or a memory die210such as a DRAM memory device. In other embodiments, integrated circuit die210/215can be a Power Management Integrated Circuit (PMIC) die, a Transceiver (TRX) die, or the like. In some embodiments, the die(s)110includes a die stack (not shown) which may include both logic dies and memory dies. The die(s)210/215may include an input/output (I/O) die, such as a wide I/O die. Although two dies210/215are illustrated, it should be understood that in some embodiments only one die or more than two dies can be used.

In some embodiments, the integrated circuit dies210/215are mounted to the first insulating layer105such that die contacts220are facing away from or distal to the first insulating layer105. The die contacts220provide an electrical connection to the electrical circuitry formed on the integrated circuit dies210/215. The die contacts220may be formed on active sides of the integrated circuit dies210/215, or may be formed on backsides and comprise through-vias. The die contacts220may further comprise through-vias providing an electrical connection between first sides and second sides of the integrated circuit dies210/215. In some embodiments, the die contacts220may comprise copper, tungsten, aluminum, silver, gold, tin, a combination thereof, or the like. In some embodiments, the die contacts220may be formed using similar materials and methods as the alignment pattern115discussed above with reference to, for example,FIG. 1a, and the description is not repeated herein.

Still referring toFIG. 4a, an encapsulant235is formed over the carrier101, and over and surrounding the integrated circuit dies210/215, the conductive vias205, and the alignment pattern115. In some embodiments, the encapsulant235may comprise a molding compound such as an epoxy, a resin, a moldable polymer, or the like. The molding compound may be applied while substantially liquid, and then may be cured through a chemical reaction, such as in an epoxy or resin. In other embodiments, the molding compound may be an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid capable of being disposed around and between the integrated circuit dies210/215, the conductive vias205, and the alignment pattern115.

Referring further toFIG. 4a, in some embodiments, a resulting structure is planarized, for example, using a CMP process, a grinding process, the like, or a combination thereof. In some embodiments, the planarization process is performed to expose the die contacts220of the integrated circuit dies210/215. In some embodiments, the top surfaces the conductive vias205are substantially coplanar with top surfaces of the die contacts220and the encapsulant235within process variations. The die layer201includes the attached dies210/215, the encapulant235, and the conductive vias205.

Referring toFIG. 4b, in some embodiments wherein a layer110is formed and includes the alignment pattern115and second insulting material130, as well as other features such as conductive features120and seal ring125, such as inFIG. 1b, the integrated circuit dies210/215can be placed on the second insulating material130and/or over the conductive features120of layer110. The integrated circuit dies210/215can be placed using any of the processes described above with respect toFIG. 4a, including that the alignment pattern115can be used to precisely place the dies210/215on the layer110.

Referring toFIG. 4c, in some embodiments, wherein a layer110is formed and includes the alignment pattern115and second insulating material130, in addition to one or more additional layers including other features such as conductive features120, seal ring125, or insulating material130in a separate layer111, such as illustrated inFIG. 1c, the integrated circuit dies210/215can be placed on the insulating material130and/or over the conductive features120of layer111. The integrated circuit dies210/215can be placed using any of the processes described above with respect toFIG. 4a, including that the alignment pattern115can be used to precisely place the dies210/215on the layer111.

Referring toFIG. 4bor4c, in some embodiments, an encapsulant235is formed over the carrier101, and over and surrounding the integrated circuit dies210/215and the conductive vias205. In some embodiments, the encapsulant235may comprise the same materials and be formed in the same way as described above with respect toFIG. 4a. A planarization process, such as a CMP process, a grinding process, the like, or a combination thereof, may be performed. In some embodiments, the planarization process is performed to expose the die contacts220of the integrated circuit dies210/215. In some embodiments, the top surfaces the conductive vias205are substantially coplanar with top surfaces of the die contacts220and the encapsulant235within process variations.

InFIGS. 5-9, an embodiment is illustrated of the layers110which is consistent with the embodiment described above with respect toFIGS. 1b, 2b, 3b, and 4b. Figures and specific descriptions of the embodiments consistent withFIG. 1aor1chave not been repeated for the sake of brevity. One of skill will understand, however, thatFIGS. 5-9can be directed to each of these embodiments by modifying the corresponding layers in a manner consistent with those embodiments.

Referring toFIG. 5, a redistribution structure240is formed over the integrated circuit dies210/215, the conductive vias205and the encapsulant230. In some embodiments, the redistribution structure240comprises one or more metallization patterns245disposed within one or more dielectric layers250.

The formation of redistribution structure240can include any appropriate method. In some embodiments, a dielectric layer250is deposited on the encapsulant235, through vias205, and die contacts220. In some embodiments, the dielectric layer250is an insulating layer formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a lithography mask. In other embodiments, the dielectric layer250is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer250may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer250is then patterned. The patterning forms openings to expose portions of the through vias205and the die connectors220. The patterning may be by an acceptable process, such as by exposing the dielectric layer250to light when the dielectric layer250is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer250is a photo-sensitive material, the dielectric layer250can be developed after the exposure.

A metallization pattern245with vias247is formed on the dielectric layer250. As an example to form metallization pattern245, a seed layer (not shown) is formed over the dielectric layer250and in openings (corresponding to via247) through the dielectric layer250. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to a metallization pattern245in a metal layer of redistribution structure240. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the metallization pattern245and vias247. The vias247are formed in openings through the dielectric layer250to, e.g., the through vias205and/or the die connectors220.

Additional dielectric layers250and metallization patterns245can be deposited in alternating layers using the processes and materials described above.

The front-side redistribution structure240is shown as an example. More or fewer dielectric layers and metallization patterns may be formed in the front-side redistribution structure240. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed above may be repeated. One having ordinary skill in the art will readily understand which steps and processes would be omitted or repeated.

Still referring toFIG. 5, conductive connectors260are formed on the UBMs255. The conductive connectors260may be BGA connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors260may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors260are formed by initially forming a layer of solder through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors260are metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on the top of the metal pillar connectors260. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

The front-side redistribution structure240may be utilized to couple the die package100a, for example, via the connectors260to one or more packages, package substrates, components, the like, or a combination thereof.

Although only a few connectors260and layers of redistribution structure240layers are illustrated, it should be understood that these are provided merely as an example. The packages can have many connectors in a grid, array, or other arrangement, and each connector260may be coupled to one or more metallization patterns245of redistribution structure240. Some connectors260can be coupled to a die contact220. Some connectors260can be coupled to conductive vias205.

Referring toFIG. 6, a carrier tape or debond tape305can be applied to the connectors260of the packages100. The debond tape305has an adhesive surface that is used to attach the electrical connectors250to the debond tape305. The debond tape305can be attached before or after flipping the carrier101over.

Referring toFIG. 7the carrier101is removed from the backside of the packages100. The carrier101can be removed by any suitable method depending on how it was attached to the package. For example, in embodiments in which the adhesive layer103is formed of a light-sensitive adhesive, the carrier substrate100bcan be removed by exposing adhesive layer103to ultraviolet light or a laser, causing it to lose its adhesive property. In some embodiments, the carrier101can be removed by grinding or etching. If used, adhesive layer103is also cleaned from the packages100.

Referring toFIG. 8, the packaged devices100are further processed. In some embodiments, a laser marking device505is used to mark the backside of the device with informational marks510. For example, the first insulating layer105can be marked with lot numbers, design numbers, revision numbers, logos, other markings, and so forth. Informational marks510can be seen as recesses in first insulating layer105and may carry the information for the respective package, for example, package100aor100b. Informational marks510may include letters, number, or other identifiable patterns. The laser marking device505can be a laser suitable for marking on the packaged device, such as a laser drill.

In some embodiments, prior to the laser marking, the first insulating layer105can be thinned using, for example, a grinding, CMP, or etching process. The thinning can expose the alignment pattern115, for example if the alignment pattern was deposited in first insulating layer105. The thinning can also expose backside contact pads which can have been included in the first insulating layer105in a manner similar to that described above with the alignment pattern115. Such backside contact pads can be used to form additional connectors on the backside of the packages100.

In some embodiments, additional processing can include forming one or more backside redistribution structures in a manner similar to and using materials such as those described above with respect to the forming of front-side redistribution structure240. In some embodiments, additional processing of the workpiece can include mounting other devices on the backside of the packages100, such as by a pick and place process or manual process, and coupling the other devices to the backside of the packages100directly or via connectors.

In the additional processing, alignment pattern115should not be covered with any material or devices which would block it from being seen or recognized by a cutting alignment device, which will be discussed in greater detail below.

Referring toFIG. 9, the packages are cut from one another from the backside of the workpiece without turning the workpiece back over. The cut is through the non-package region160along the dicing streets, through first insulating layer105, layer110(in accordance with some embodiments), molding material235, and redistribution structure240. A cutting device610, such as a saw, can be used. In some embodiments, cutting device610can be another device suitable for cutting the packages, such as a cutting laser or plasma etchant. Embodiments such as those discussed herein are to be singulated from the backside of the device using alignment pattern115as a guide for saw alignment and using debond tape305as a saw tape, rather than bonding the structure to a saw tape, turned over, debonded from the debond tape, and cut from the front (connector side).

An alignment device620can include an optical sensor which can scan the backside of the package structure100over the first insulating layer105for a particular alignment pattern115and align the cutting device610to be a distance d1from the alignment pattern115. Any other suitable sensor technologies can be used for detecting the alignment pattern115. Alignment device620can also determine a rotational position of the cutting device610based on the alignment pattern115. For example, cutting device610can be aligned to cut parallel or at a respective angle to an edge of the alignment pattern115in plan view.

In some embodiments, a first cut can be made partially into the first insulating layer105to define scribe lines for a subsequent second cut to complete the singulation process of the packages100.

Alignment device620can be used to recognize the alignment pattern115through the first insulating layer105and use the alignment pattern115to determine a distance d1in an x and/or y direction (in top down view) from the alignment pattern115to cut the packages for singulation. This will be described in greater detail below. Multiple alignment patterns115can be included, for example, located near corners of the package region150.

Referring toFIG. 10a, the cutting device can singulate the packages, for example, into package100aand package100b. The cutting device610cuts through the first insulating layer105, molding compound235, and the dielectric layers of the redistribution structure240. In some embodiments, the cutting device610can also cut through the debond tape305. In other embodiments, the cutting device610can stop short of cutting through the debond tape305. Following the cutting, the debond tape is removed from the packages100aand100b.

The packages100aand100bcan be used in further processing, for example by bonding another package on top or bonding to another package, interposer, or the like. In some embodiments, the packages100aand100bcan be further processed after singulation, either prior to removing the debond tape305or after, for example, to add connectors, packages, or other devices, on the backside of packages100aand100b. In some embodiments, alignment pattern115can be used in further processing of the singulated packages, for example, to align other devices thereto in a package on package structure.

Referring toFIG. 10b, alignment pattern115is contained within a separate layer110along with second insulating material130, in accordance with some embodiments, e.g., those consistent withFIGS. 1b, 2b, 3b, and 4b. The cutting device610cuts through the first insulating layer105, layer110, molding compound235, and the dielectric layers of the redistribution structure240. The rest of the singulation process is the same as described above with respect toFIG. 10aand is not repeated.

Referring toFIG. 10c, alignment pattern115is contained within a separate layer110along with second insulating material130, in accordance with some embodiments, e.g., those consistent withFIGS. 1c, 2c, 3c, and 4c. The cutting device610cuts through the first insulating layer105, layer110, additional layers111, molding compound235, and the dielectric layers of the redistribution structure240. The rest of the singulation process is the same as described above with respect toFIG. 10aand is not repeated.

Referring toFIGS. 10a-10c, if other layers have been included which are not specifically addressed herein, such as a layer resulting from further processing of the backside of the packages, such as discussed with respect toFIG. 8, then those layers will also be cut through by cutting device610in the singulation process.

Referring toFIG. 11, a top down view of the backside of a corner portion of an InFO package is illustrated, in accordance with some embodiments. Alignment pattern115is visible through first insulating layer105, which contains conductive features120, such as trace routing or contacts. The conductive features120can couple to dies and other contacts or connectors in the package. In some embodiments, conductive features120can include an ornamental design or pattern. In some embodiments, conductive features120can include a shield. An optional seal ring125can be formed around the design, enclosing the design within the seal ring125in plan view. The seal ring125is considered to be in the design area of the package region150.

Referring toFIG. 12possible alignment pattern designs are illustrated, in accordance with some embodiments.FIG. 12illustrates a cross shape115a, el-shape115b, bullseye115c, and a diamond115d. These are only some examples of marks that can be used. Any shape can be used as an alignment pattern115. The shape of alignment patterns115a,115b,115c, and115dare provided for illustrative purposes only and are not meant to limit the scope of the embodiments described herein.

Referring toFIG. 13, a top down view of packages100prior to singulation is illustrated, in accordance with some embodiments. A circle shown in phantom represents a carrier wafer101that has been removed. Multiple packages100are mounted to a debonding/saw tape305by their connectors260(not shown). For example, individual packages100aand100bare illustrated. Each packages has one or more die mounting regions151illustrated by the dashed rectangle. One or more alignment patterns115are included in the package area150. A non-package area160is located between the individual packages100, thereby defining dicing streets. As illustrated inFIG. 13, multiple alignment patterns115can be included in each package. Although it is illustrated that four different marks are included in each package, alignment patterns115can each be identical to each other, set in pairs, or set in any other arrangement of similar or dissimilar marks. Fewer or more alignment patterns can be included as well. For example, one or more alignment patterns115can be included as visible in the top down view. Alignment patterns115need not be placed in corners of the packages, but can be anywhere within the package. Alignment patterns115can be included outside the die mounting region151, as illustrated, or in some embodiments, can be included inside the die mounting region151, if including it would not interfere with the ability of alignment device620to scan the surface and find the alignment patterns115.

FIG. 14illustrates dimensions of an alignment pattern115, in accordance with some embodiments. Conductive features120can be visible from the top down view, for example, in layer110or in an additional layer111. The alignment pattern115can be a minimum specified distance S1in a first dimension away from the conductive features120and a minimum specified distance S2in a second dimension away from the conductive features120. In some embodiments, the minimum distance S1and S2can be about 30 μm or more. In some embodiments, the minimum distance can be less than 30 μm, such as about 20 μm. Having a minimum distance can help the optical sensor of alignment device620distinguish between alignment pattern115and conductive features120. In some embodiments the minimum specified distance S1is the same as the minimum specified distance S2. In other embodiments, the distances S1and S2are different.

In some embodiments, seal ring125can be visible from the top down view, for example, in layer110or in an additional layer111. The alignment pattern115can be a minimum specified distance S7in the first dimension away from the seal ring125and a minimum specified distance S8in the second dimension away from the seal ring125. In some embodiments, the minimum distance S7and S8can be about 30 μm or more. In some embodiments, the minimum distance can be less than 30 μm, such as about 20 μm. In some embodiments the distance S7is the same as the distance S8. In other embodiments, the distances S7and S8are different. In some embodiments the distances S1, S2, S7, and S8, are the same. In other embodiments, on or more of S1, S2, S7, and S8can be different from the others. In some embodiments, the distances S1, S2, S7, and S8may be less than about 30 μm.

Still referring toFIG. 14, the alignment pattern115is shown as an el-shape, but it can be any alignment shape, such as discussed above with respect toFIG. 12. The dimensions S3and S6represent a minimum width for the alignment pattern115in the second dimension (y-direction) and the first dimension (x-direction), respectively. In some embodiments, the minimum width of the alignment pattern115is about 40 μm up to about the maximum width, which is discussed below. In some embodiments, the minimum width of the alignment pattern can be less than 40 μm, such as about 10 μm. The dimensions S4and S5represent a maximum width for the alignment pattern115in the x-direction and y-direction, respectively. The maximum width is only limited by the alignment pattern115used and the overall width of the package area150. In other words, the maximum dimensions of alignment pattern115correspond to the dimensions of the package area150. For example, alignment pattern115can be 1000 μm or more in either dimension.

FIG. 15illustrates a top down view of alignment pattern115-1and115-2in packages100aand100b, respectively. The distance d1is measured between the alignment pattern115-1and a cut-line635. The distance d2is measured between the alignment pattern115-2and the cut-line635. The distance d3is measured between the alignment pattern115-2and the cut-line640. The distance d4is measured between the alignment pattern115-1and the cut-line640. The distances d1, d2, d3, and d4can be predetermined such that once the optical sensor of alignment device620detects the alignment pattern115, the cut-line635/640can be determined by measuring a distance from the alignment pattern115. In some embodiments, cut-line640can be determined by being a distance from alignment pattern115-2, such as measurements d3, such that the cutline640is parallel to an edge (115-2edge) of the pattern115-2. In some embodiments, the distances from the alignment pattern115to the cut-line635/640, for example d1and d2, can be substantially equal. In some embodiments, the distances from the alignment pattern115to the cut-line635/640can be different. The alignment patterns115-1/115-2in adjacent packages can be the same or different, as illustrated.

In some embodiments, a single alignment pattern in one package can determine the cut-line635and the cut-line640. In some embodiments, alignment pattern115-1can be used to determine a horizontal cutline640and alignment pattern115-2can be used to determine a vertical cutline635, or vice versa. In some embodiments, multiple alignment patterns115-1/115-2can be used to determine both cut-line635and640.

FIG. 16illustrates a flow diagram for providing an alignment pattern, in accordance with some embodiments. The particulars of each step are described in detail above, and are not repeated here. At10, an alignment pattern can be formed in a layer over a carrier. As described above, an adhesive layer can be used between the alignment pattern and the carrier. Also, other features, such as conductive features or seal rings can be formed in the same layer as the alignment pattern or in a different layer. At15, one or more dies are mounted, as described above. Vias can also be added and a molding material can be used to fill in gaps and provide structural support to the layer. At20, interconnects can be formed over the dies, including a redistribution layer. At25, connectors can be formed on the package over the redistribution layer.

At30, the packages can be attached to a debond or saw tape, flipped over, and debonded from the carrier. In some embodiments, the debonding can occur before the flipping. With the backside of the packages now facing up, the backside can optionally be processed at35. For example, the backside can be thinned or connectors can be added to the backside, possibly for mounting another package to the backside. As described above, the backside can be marked with a laser marking device. At40, a sensor is used to detect the alignment patterns by scanning the backside of the packages. At45, a cutting device is aligned to the alignment patterns by a predetermined offset and the packages are singulated into individual packages. The individual packages may then be further processed and incorporated, for example, into other packages or devices.

FIG. 17illustrates a flow diagram for singulating packages where the packages have an alignment pattern formed within a visible layer of the backside of the package within a design area of the package. At60, an alignment device with an optical sensor is used to scan the backside of the packages looking for alignment patterns. Using the alignment patterns, the alignment device determines where to cut the backside of the device. At65, the cut-line can be determined by measuring a predetermined offset distance from the alignment pattern to the cut-line. The cutting device will cut along the cut-line.

At70, an optional initial cut can be performed to scribe the backside of the packages. In some embodiments, the initial cut can be performed to establish the scribe lines and then subsequent processing performed thereafter. For example, connectors can be formed over the packages or other devices or packages mounted to the packages. At75, the packages can be singulated along the cut-lines (or scribe-lines if an initial cut was made at70). In some embodiments multiple cutting devices and/or multiple different types of cutting devices can be used to perform the singulation. For example, a combination of cutting with a saw, plasma etch, or laser can be used.

In embodiments where an initial cut was made, the initial cut and singulation cut can be made by the same or different cutting devices. For example, the initial cut can be made by a first cutting device, such as a laser, and the full singulation can be made by a second cutting device, such as a saw. Any combination of cutting devices can be used.

In some embodiments, the singulated packages may be further processed after singulation, either prior to removing the debond tape or after, for example, to add connectors, packages, or other devices, on the backside of the packages. In some embodiments, the alignment patterns of the singulated packages can be used in further processing of the singulated packages, for example by aligning another package on top or bonding to another package, interposer, or the like.

Embodiments provide an alignment pattern for aligning a cutting device to cut-lines to singulate packages, such as InFO packages. Rather than turning the packages over and singulating from the front side of the packages, the packages can be singulated from the backside of the packages, thereby saving several processing steps in forming a plurality of packages on a carrier.

One embodiment includes a method which includes forming a first insulating layer over a carrier. An alignment pattern is formed proximate a front side of the first insulating layer. A die is mounted over the front side of the first insulating layer. The die is encapsulated with an encapsulant. Connectors are formed over the die, the connectors being coupled to the die. The connectors are attached to a dicing tape and the carrier is removed. A cutting device is aligned to a backside of the first insulating layer using the alignment pattern. The first insulating layer and encapsulant are cut from the backside of the first insulating layer.

Another embodiment includes a method which includes scanning a backside of a packages structure for an alignment pattern. An alignment pattern is detected in a first package area of the packages structure. A cutting device is aligned to a cut-line in a non-package area of the packages structure based on a predetermined distance from the alignment pattern. One or more packages are singulated from the packages structure.

Another embodiment is an integrated fan-out (InFO) package which includes a first insulating layer having a first laser marking. An alignment pattern is proximate to the first insulating layer. An encapsulated die is over the first insulating layer and a redistribution structure is over the die. A plurality of connectors is disposed over the redistribution structure on a top of the package, where a first connector of the plurality of connectors is electrically coupled to the die.