Fan-out semiconductor package

A fan-out semiconductor package includes: a fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a reinforcing layer disposed on the encapsulant. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korean Patent Application Nos. 10-2016-0036258 filed on Mar. 25, 2016, 10-2016-0083565 filed on Jul. 1, 2016 and 10-2016-0107713 filed on Aug. 24, 2016 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor package, and more particularly, to a fan-out semiconductor package in which connection terminals may extend outwardly of a region in which a semiconductor chip is disposed.

BACKGROUND

A significant recent trend in the development of technology related to semiconductor chips has been to reduce the size of semiconductor chips. Therefore, in the case of package technology, in accordance with a rapid increase in demand for small-sized semiconductor chips, or the like, the implementation of a semiconductor package having a compact size while including a plurality of pins has been demanded.

One type of package technology suggested to satisfy the technical demand described above is a fan-out package. Such a fan-out package has a compact size and may allow a plurality of pins to be implemented by redistributing connection terminals outwardly of a region in which a semiconductor chip is disposed.

SUMMARY

An aspect of the present disclosure may provide a fan-out semiconductor package in which a warpage problem may be effectively solved.

According to an aspect of the present disclosure, a fan-out semiconductor package may be provided, in which a reinforcing layer that may control warpage of the fan-out semiconductor package is attached to an encapsulant encapsulating a semiconductor chip.

According to an aspect of the present disclosure, a fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a reinforcing layer disposed on the encapsulant. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated or omitted for clarity.

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

Herein, an upper portion, a lower portion, an upper side, a lower side, an upper surface, a lower surface, and the like, are decided in the attached drawings. For example, a first interconnection member is disposed on a level above a redistribution layer. However, the claims are not limited thereto. In addition, a vertical direction refers to the abovementioned upward and downward directions, and a horizontal direction refers to a direction perpendicular to the abovementioned upward and downward directions. In this case, a vertical cross section refers to a case taken along a plane in the vertical direction, and an example thereof may be a cross-sectional view illustrated in the drawings. In addition, a horizontal cross section refers to a case taken along a plane in the horizontal direction, and an example thereof may be a plan view illustrated in the drawings.

Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context.

Electronic Device

Referring toFIG. 1, an electronic device1000may accommodate a main board1010therein. The main board1010may include chip-related components1020, network-related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines1090.

FIG. 2is a schematic perspective view illustrating an example of an electronic device.

Referring toFIG. 2, a semiconductor package may be used for various purposes in the various electronic devices1000as described above. For example, a main board1110may be accommodated in a body1101of a smartphone1100, and various electronic components1120may be physically or electrically connected to the main board1110. In addition, other components that may or may not be physically or electrically connected to the main board1110, such as a camera module1130, may be accommodated in the body1101. Some of the electronic components1120may be the chip-related components, and the semiconductor package100may be, for example, an application processor among the chip-related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone1100, but may be other electronic devices as described above.

Semiconductor Package

Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a finished semiconductor product itself, and may be damaged due to external physical or chemical impacts. Therefore, the semiconductor chip itself may not be used, but may be packaged and used in an electronic device, or the like, in a packaged state.

Here, semiconductor packaging is required due to the existence of a difference in circuit widths between the semiconductor chip and a main board of the electronic device in terms of electrical connections. In detail, a size of connection pads of the semiconductor chip and intervals between the connection pads of the semiconductor chip are very fine, while sizes of component mounting pads of the main board used in the electronic device and intervals between the component mounting pads of the main board are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the main board, and packaging technology for buffering a difference in circuit widths between the semiconductor chip and the main board is required.

A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof.

The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the drawings.

Fan-in Semiconductor Package

FIGS. 3A and 3Bare schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged.

FIG. 4is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, a semiconductor chip2220may be, for example, an integrated circuit (IC) in a bare state, including a body2221including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads2222formed on one surface of the body2221and including a conductive material such as aluminum (Al), or the like, and a passivation layer2223such as an oxide film, a nitride film, or the like, formed on one surface of the body2221and covering at least portions of the connection pads2222. In this case, since the connection pads2222are significantly small, it is difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the main board of the electronic device, or the like.

Therefore, a interconnection member2240may be formed on the semiconductor chip2220depending on a size thereof in order to redistribute the connection pads2222. The interconnection member2240may be formed by forming an insulating layer2241on the semiconductor chip2220using an insulating material such as photoimagable dielectric (PID) resin, forming via holes2243hopening the connection pads2222, and then forming a redistribution layer2242and vias2243. Then, a passivation layer2250protecting the interconnection member2240may be formed, an opening2251may be formed, and an under-bump metal layer2260, or the like, may be formed. That is, a fan-in semiconductor package2200including, for example, the semiconductor chip2220, the interconnection member2240, the passivation layer2250, and the under-bump metal layer2260may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip are disposed inside the semiconductor chip, may have excellent electrical characteristics and may be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to allow rapid signal transfer to be implemented while having a compact size.

However, since all I/O terminals need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has a large spatial limitation. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a compact size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not be directly mounted and used on the main board of the electronic device. Here, even in the case that a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the main board of the electronic device.

FIG. 5is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is ultimately mounted on a main board of an electronic device.

FIG. 6is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is ultimately mounted on a main board of an electronic device.

Referring to the drawings, in a fan-in semiconductor package2200, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more through an interposer substrate2301, and the fan-in semiconductor package2200may be ultimately mounted on a main board2500of an electronic device in a state of being mounted on the interposer substrate2301. In this case, solder balls2270, and the like, may be fixed by an underfill resin2280, or the like, and an external surface of the semiconductor chip2220may be covered with a molding material2290, or the like. Alternatively, a fan-in semiconductor package2200may be embedded in a separate interposer substrate2302, connection pads2222, that is, I/O terminals, of the semiconductor chip2220may again be redistributed by the interposer substrate2302in a state in which the fan-in semiconductor package2200is embedded in the interposer substrate2302, and the fan-in semiconductor package2200may be ultimately mounted on a main board2500of an electronic device.

As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the main board of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate and be then mounted on the main board of the electronic device through a packaging process or may be mounted and used on the main board of the electronic device in a state in which it is embedded in the interposer substrate.

Fan-out Semiconductor Package

Referring to the drawing, in a fan-out semiconductor package2100, for example, an external surface of a semiconductor chip2120may be protected by an encapsulant2130, and connection pads2122of the semiconductor chip2120may be redistributed outwardly of the semiconductor chip2120by a interconnection member2140. In this case, a passivation layer2150may further be formed on the interconnection member2140, and an under-bump metal layer2160may further be formed in openings of the passivation layer2150. Solder balls2170may further be formed on the under-bump metal layer2160. The semiconductor chip2120may be an integrated circuit (IC) including a body2121, the connection pads2122, a passivation layer (not illustrated), and the like. The interconnection member2140may include an insulating layer2141, redistribution layers2142formed on the insulating layer2141, and vias2143electrically connecting the connection pads2122and the redistribution layers2142to each other.

As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the interconnection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when a size of the semiconductor chip is reduced, a size and a pitch of balls need to be reduced, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the interconnection member formed on the semiconductor chip as described above. Therefore, even in the case that a size of the semiconductor chip is reduced, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the main board of the electronic device without using a separate interposer substrate, as described below.

FIG. 8is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a main board of an electronic device.

Referring to the drawing, a fan-out semiconductor package2100may be mounted on a main board2500of an electronic device through solder balls2170, or the like. That is, as described above, the fan-out semiconductor package2100includes the interconnection member2140formed on the semiconductor chip2120and capable of redistributing the connection pads2122to a fan-out region outside of an area of the semiconductor chip2120, such that the standardized ball layout may be used in the fan-out semiconductor package2100as it is. As a result, the fan-out semiconductor package2100may be mounted on the main board2500of the electronic device without using a separate interposer substrate, or the like.

As described above, since the fan-out semiconductor package may be mounted on the main board of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented to have a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type semiconductor package using a printed circuit board (PCB), and may solve a problem occurring due to occurrence of a warpage phenomenon.

Meanwhile, the fan-out semiconductor package refers to package technology for mounting the semiconductor chip on the main board of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is conceptually different from a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein.

A fan-out semiconductor package in which a warpage problem may be effectively solved will hereinafter be described with reference to the drawings.

FIG. 9is a schematic cross-sectional view illustrating an example of a fan-out semiconductor package.

FIG. 10is a schematic plan view taken along line I-I′ of the fan-out semiconductor package ofFIG. 9.

FIGS. 11A through 11Dare schematic cross-sectional views illustrating various forms of vias formed in a first interconnection member of the fan-out semiconductor package ofFIG. 9.

Referring to the drawings, a fan-out semiconductor package100A according to an exemplary embodiment in the present disclosure may include a first interconnection member110having a through-hole110H, a semiconductor chip120disposed in the through-hole110H of the first interconnection member110and having an active surface having connection pads122disposed thereon and an inactive surface opposing the active surface, an encapsulant130encapsulating at least portions of the first interconnection member110and the inactive surface of the semiconductor chip120, a second interconnection member140disposed on the first interconnection member110and the active surface of the semiconductor chip120, a reinforcing layer181disposed on the encapsulant130, a resin layer182disposed on the reinforcing layer181, and openings182H penetrating through the resin layer182, the reinforcing layer181, and the encapsulant130and exposing at least portions of a third redistribution layer112cof the first interconnection member110. The fan-out semiconductor package100A according to the exemplary embodiment may further include a passivation layer150disposed on the second interconnection member140, an under-bump metal layer160disposed in openings150H of the passivation layer150, and connection terminals170disposed on the under-bump metal layer160. The reinforcing layer181may have an elastic modulus greater than that of the encapsulant130, and may have a coefficient of thermal expansion (CTE) lower than that of the encapsulant130.

Meanwhile, as illustrated inFIG. 26, a thermosetting resin film that may firmly fix a first interconnection member510, a semiconductor chip520, and the like, may be used in order to form an encapsulant530encapsulating the first interconnection member510, the semiconductor chip520, and the like. In detail, the thermosetting resin film having a high CTE, generally having good resin flowability, may be used to form the encapsulant530, in order to completely fill a space of a through-hole510H between the first interconnection member510and the semiconductor chip520with a resin and increase close adhesion between the first interconnection member510and the semiconductor chip520. However, in this thermosetting resin film, heat-hardening contraction of the resin is large, such that warpage W1may be severely generated in a package after the resin is hardened. Therefore, it may be difficult to form fine circuit patterns on an active surface of the semiconductor chip520later.

Meanwhile, as illustrated inFIG. 27, in order to solve this problem, it may be considered that a thermosetting resin film having a low CTE is used to form an encapsulant540. In this case, warpage W2may be suppressed as compared to in a case of using the thermosetting resin film having the high CTE. However, as illustrated inFIG. 28, a content of inorganic filler in the thermosetting resin film is generally increased in order to reduce a CTE, such that a resin may not sufficiently fill a fine space due to a reduction in resin flowability, leading to formation of a void, or the like. In addition, delamination between a first interconnection member and a semiconductor chip, or the like, may be generated due to a reduction in close adhesion between the first interconnection member and the semiconductor chip.

On the other hand, in a case in which the reinforcing layer181having a relatively large elastic modulus or a relatively small CTE is introduced as in the fan-out semiconductor package100A according to the exemplary embodiment, the reinforcing layer181may suppress hardening contraction of a material of the encapsulant130, such as the thermosetting resin film, such that generation of warpage of the fan-out semiconductor package100A may be significantly reduced after the material is hardened. Therefore, a material having a high CTE may be used as a material of the encapsulant130. Resultantly, a problem such as a void, delamination, or the like, may not occur.

Meanwhile, in the fan-out semiconductor package100A according to the exemplary embodiment, the reinforcing layer181may include a glass cloth, an inorganic filler, and an insulating resin. In this case, it may not be easy to form openings in the reinforcing layer181. However, in a case in which the resin layer182is disposed on the reinforcing layer181, this problem may be solved. For example, in a case in which a material the same as or similar to that of the encapsulant130, for example, an insulating material that includes an inorganic filler and an insulating resin, but does not include a core material such as a glass cloth (or a class fabric), or the like, that is, Ajinomoto Build-up Film (ABF), or the like, is used as a material of the resin layer182, the openings182H may be easily formed. Wirings exposed through the openings182H may be used as markings, pads, or the like.

The respective components included in the fan-out semiconductor package100A according to the exemplary embodiment will hereinafter be described in more detail.

The first interconnection member110may include redistribution layers112aand112bredistributing the connection pads122of the semiconductor chip120to thus reduce the number of layers of the second interconnection member140. If necessary, the first interconnection member110may maintain rigidity of the fan-out semiconductor package100A depending on materials of the encapsulant130, and serve to secure uniformity of a thickness of the encapsulant130. In some cases, due to the first interconnection member110, the fan-out semiconductor package100A according to the exemplary embodiment may be used as a portion of a package-on-package semiconductor package. The first interconnection member110may have the through-hole110H. The through-hole110H may have the semiconductor chip120disposed therein to be spaced apart from the first interconnection member110by a predetermined distance. Side surfaces of the semiconductor chip120may be surrounded by the first interconnection member110. However, such a form is only an example and the present disclosure may be variously modified to have other forms, and the fan-out semiconductor package100A may perform another function depending on such a form.

The first interconnection member110may include a first insulating layer111ain contact with the second interconnection member140, a first redistribution layer112ain contact with the second interconnection member140and embedded in the first insulating layer111a, a second redistribution layer112bdisposed on the other surface of the first insulating layer111aopposing one surface of the first insulating layer111ain which the first redistribution layer112ais embedded, a second insulating layer111bdisposed on the first insulating layer111aand covering the second redistribution layer112b, and the third redistribution layer112cdisposed on the second insulating layer111b. The first to third redistribution layers112a,112b, and112cmay be electrically connected to the connection pads122. The first interconnection member110may include first and second vias113aand113bpenetrating through the first and second insulating layers111aand111b, respectively, and electrically connecting the first and second redistribution layers112aand112band the second and third redistribution layers112band112cto each other, respectively. Since the first redistribution layer112ais embedded, an insulating distance of an insulating layer141aof the second interconnection member140may be substantially constant, as described above. Since the first interconnection member110may include a large number of redistribution layers112a,112b, and112c, the second interconnection member140may be further simplified. Therefore, a decrease in a yield depending on a defect occurring in a process of forming the second interconnection member140may be improved.

A case in which the first interconnection member110includes two insulating layers111aand111bis illustrated in the drawing, but the number of insulating layers constituting the first interconnection member110may be greater than two. In this case, the number of redistribution layers disposed in the first interconnection member110may be increased, and additional vias connecting the redistribution layers to each other may be formed.

A material of each of the insulating layers111aand111bis not particularly limited. For example, an insulating material may be used as a material of each of the insulating layer111aand111b. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is impregnated together with an inorganic filler in a core material such as a glass cloth (or a glass fabric), for example, prepreg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. Alternatively, a photoimagable dielectric (PID) resin may also be used as the insulating material. The first insulating layer111aand the second insulating layer111bmay include the same insulating material, and a boundary between the first insulating layer111aand the second insulating layer111bmay not be apparent. However, the first insulating layer111aand the second insulating layer111bare not limited thereto.

The redistribution layers112a,112b, and112cmay serve to redistribute the connection pads122of the semiconductor chip120, and a material of each of the redistribution layers112a,112b, and112cmay be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers112a,112b, and112cmay have various functions depending on designs of layers corresponding thereto. For example, the redistribution layers112a,112b, and112cmay include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals except for the ground (GND) pattern, the power (PWR) pattern, and the like, such as data signals, and the like. In addition, the redistribution layers112a,112b, and112cmay include a via pad, a connection terminal pad, and the like. As a non-restrictive example, both of the redistribution layers112a,112b, and112cmay include a ground pattern. In this case, the number of ground patterns formed on the redistribution layers142aand142bof the second interconnection member140may be significantly reduced, such that a degree of wiring design freedom may be improved.

A surface treatment layer (not illustrated) may further be formed on the third redistribution layer112cexposed from the redistribution layers112a,112b, and112cthrough the openings182H, if necessary. The surface treatment layer (not illustrated) is not particularly limited as long as it is known in the related art, and may be formed by, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating/substituted gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), or the like.

The vias113aand113bmay electrically connect the redistribution layers112a,112b, and112cformed on different layers to each other, resulting in an electrical path in the first interconnection member110. A material of each of the vias113aand113bmay be a conductive material. As illustrated inFIGS. 11A through 11D, each of the vias113may be entirely filled with the conductive material or the conductive material may also be formed along a wall of respective via holes. In addition, each of the vias113aand113bmay have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like. Meanwhile, as can be seen from a process to be described below, some of pads of the first redistribution layer112amay serve as a stopper when holes for the first vias113aare formed, and some of pads of the second redistribution layer112bmay serve as a stopper when holes for the second vias113bare formed, and it may thus be advantageous in a process that each of the first and second vias113aand113bhas the tapered shape of which a width of an upper surface is greater than that of a lower surface. In this case, the first vias113amay be integrated with portions of the second redistribution layer112b, and the second vias113bmay be integrated with portions of the third redistribution layer112c.

The semiconductor chip120may be an integrated circuit (IC) provided in an amount of several hundreds to several millions of elements or more integrated in a single chip. The IC may be, for example, an application processor chip such as a central processor (for example, a CPU), a graphics processor (for example, a GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like, but is not limited thereto. The semiconductor chip120may be formed on the basis of an active wafer. In this case, a base material of a body121may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body121. The connection pads122may electrically connect the semiconductor chip120to other components. A material of the connection pads122may be a conductive material such as aluminum (Al), or the like. A passivation layer123exposing the connection pads122may be formed on the body121, and may be an oxide film, a nitride film, or the like, or a double layer formed of an oxide layer and a nitride layer. A lower surface of the connection pads122may have a step portion with respect to a lower surface of the encapsulant130through the passivation layer123. Resultantly, a phenomenon in which the encapsulant130bleeds into the lower surface of the connection pads122may be prevented to some extent. An insulating layer (not illustrated), and the like, may also be further disposed in other required positions.

The inactive surface of the semiconductor chip120may be disposed on a level below an upper surface of the third redistribution layer112cof the first interconnection member110. For example, the inactive surface of the semiconductor chip120may be disposed on a level below an upper surface of the second insulating layer111bof the first interconnection member110. A height difference between the inactive surface of the semiconductor chip120and the upper surface of the third redistribution layer112cof the first interconnection member110may be 2 μm or more, for example, 5 μm or more. In this case, the generation of cracks in corners of the inactive surface of the semiconductor chip120may be effectively prevented. In addition, a deviation of an insulating distance on the inactive surface of the semiconductor chip120in a case in which the encapsulant130is used may be significantly reduced.

The second redistribution layer112bof the first interconnection member110may be disposed on a level between the active surface and the inactive surface of the semiconductor chip120. The first interconnection member110may be formed to a thickness corresponding to that of the semiconductor chip120. Therefore, the second redistribution layer112bformed in the first interconnection member110may be disposed on the level between the active surface and the inactive surface of the semiconductor chip120.

The encapsulant130may protect the first interconnection member110and/or the semiconductor chip120. An encapsulation form of the encapsulant130is not particularly limited, but may be a form in which the encapsulant130surrounds at least portions of the first interconnection member110and/or the semiconductor chip120. For example, the encapsulant130may cover the first interconnection member110and the inactive surface of the semiconductor chip120, and fill spaces between walls of the through-hole110H and the side surfaces of the semiconductor chip120. In addition, the encapsulant130may also fill at least a portion of a space between the passivation layer123of the semiconductor chip120and the second interconnection member140. Meanwhile, the encapsulant130may fill the through-hole110H to thus serve as an adhesive and reduce buckling of the semiconductor chip120depending on materials of the encapsulant130.

The materials of the encapsulant130are not particularly limited. For example, an insulating material may be used as the materials of the encapsulant130. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcing material such as an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, for example, ABF, FR-4, BT, a PID resin, or the like. In addition, a known molding material such as an epoxy molding compound (EMC), or the like, may also be used. Alternatively, a resin in which a thermosetting resin or a thermoplastic resin is impregnated together with an inorganic filler in a core material such as a glass cloth (or a glass fabric) may also be used as the insulating material.

The encapsulant130may include a plurality of layers formed of a plurality of materials. For example, a space within the through-hole110H may be filled with a first encapsulant, and the first interconnection member110and the semiconductor chip120may be covered with a second encapsulant. Alternatively, the first encapsulant may cover the first interconnection member110and the semiconductor chip120at a predetermined thickness while filling the space within the through-hole110H, and the second encapsulant may cover the first encapsulant at a predetermined thickness. In addition to the form described above, various forms may be used.

The encapsulant130may include conductive particles in order to block electromagnetic waves, if necessary. For example, the conductive particles may be any material that may block electromagnetic waves, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), a solder, or the like. However, this is only an example, and the conductive particles are not limited thereto.

The second interconnection member140may be configured to redistribute the connection pads122of the semiconductor chip120. Several tens to several hundreds of connection pads122having various functions may be redistributed by the second interconnection member140, and may be physically or electrically connected to an external source through connection terminals170to be described below depending on the functions. The second interconnection member140may include insulating layers141aand141b, the redistribution layers142aand142bdisposed on the insulating layers141aand141b, and vias143aand143bpenetrating through the insulating layers141aand141band connecting the redistribution layers142aand142bto each other. In the fan-out semiconductor package100A according to the exemplary embodiment, the second interconnection member140may include a plurality of redistribution layers142aand142b, but is not limited thereto. That is, the second interconnection member140may also include a single layer. In addition, the second interconnection member140may also include different numbers of layers.

An insulating material may be used as a material of each of the insulating layers141aand141b. In this case, a photosensitive insulating material such as a photoimagable dielectric (PID) resin may also be used as the insulating material. In this case, each of the insulating layers141aand141bmay be formed to have a smaller thickness, and a fine pitch of each of the vias143aand143bmay be achieved more easily. Materials of the insulating layers141aand141bmay be the same as each other or may be different from each other, if necessary. The insulating layers141aand141bmay be integrated with each other depending on processes, so that a boundary therebetween may not be readily apparent.

The redistribution layers142aand142bmay serve to substantially redistribute the connection pads122. A material of each of the redistribution layers142aand142bmay be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers142aand142bmay have various functions depending on designs of layers corresponding thereto. For example, the redistribution layers142aand142bmay include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals except for the ground (GND) pattern, the power (PWR) pattern, and the like, such as data signals, and the like. In addition, the redistribution layers142aand142bmay include a via pad, a connection terminal pad, and the like.

A surface treatment layer (not illustrated) may further be formed on portions of the redistribution layer142bexposed from the redistribution layers142aand142b, if necessary. The surface treatment layer (not illustrated) is not particularly limited as long as it is known in the related art, and may be formed by, for example, electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating/substituted gold plating, DIG plating, HASL, or the like.

The vias143aand143bmay electrically connect the redistribution layers142aand142b, the connection pads122, or the like, formed on different layers, to each other, resulting in an electrical path in the fan-out semiconductor package100A. A material of each of the vias143aand143bmay be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the vias143aand143bmay be entirely filled with the conductive material, or the conductive material may also be formed along a wall of each of the vias. In addition, each of the vias143aand143bmay have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like.

Thicknesses of the redistribution layers112a,112b, and112cof the first interconnection member110may be greater than those of the redistribution layers142aand142bof the second interconnection member140. Since the first interconnection member110may have a thickness equal to or greater than that of the semiconductor chip120, the redistribution layers112a,112b, and112cformed in the first interconnection member110may be formed to be large depending on a scale of the first interconnection member110. On the other hand, the redistribution layers142aand142bof the second interconnection member140may be formed to have sizes relatively smaller than those of the redistribution layers112a,112b, and112cof the first interconnection member110for thinness of the second interconnection member140.

The reinforcing layer181may suppress warpage generated in the fan-out semiconductor package100A. For example, the reinforcing layer181may suppress the hardening contraction of the material of the encapsulant130, such as the thermosetting resin film to suppress warpage of the fan-out semiconductor package100A. The reinforcing layer181may have an elastic modulus relatively greater than that of the encapsulant130, and may have a CTE smaller than that of the encapsulant130. In this case, a warpage suppression effect may be particularly excellent.

The reinforcing layer181may include a core material, an inorganic filler, and an insulating resin. For example, the reinforcing layer181may be formed of an unclad copper clad laminate (CCL), prepreg, or the like. In a case in which the reinforcing layer181includes the core material such as a glass cloth (or a glass fabric), the reinforce layer181may be implemented to have a relatively large elastic modulus, and in case in which the reinforcing layer181includes the inorganic filler, the reinforce layer181may be implemented to have a relatively small CTE by adjusting a content of the inorganic filler. The reinforcing layer181may be attached in a hardened state (a c-stage) to the encapsulant130. In this case, a boundary surface between the encapsulant130and the reinforcing layer181may have an approximately linear shape. Meanwhile, the inorganic filler may be silica, alumina, or the like, and the resin may be an epoxy resin, or the like. However, the inorganic filler and the resin are not limited thereto.

The resin layer182may be disposed on the reinforcing layer181. The resin layer182may be formed of a material the same as or similar to that of the encapsulant130, for example, an insulating material that includes an inorganic filler and an insulating resin, but does not include a core material, that is, Ajinomoto Build-up Film (ABF), or the like. In a case in which the reinforcing layer181includes the core material, or the like, it is difficult to form the openings182H in the reinforcing layer181itself, but in a case in which the resin layer182is added, the openings182H may be easily formed. The openings182H may penetrate through the encapsulant130, the reinforcing layer181, and the resin layer182, and may expose at least portions of the third redistribution layer112cof the first interconnection member110. The openings182H may be utilized as openings for marking. Alternatively, the openings182H may be utilized as openings for exposing pads in a package-on-package structure. Alternatively, the openings182H may be utilized as openings for mounting a surface mounted technology (SMT) component. In a case in which the resin layer182is disposed, the warpage may be more easily suppressed.

The passivation layer150may be additionally configured to protect the second interconnection member140from external physical or chemical damage. The passivation layer150may have the openings150H exposing at least portions of one142bof redistribution layers142aand142bof the second interconnection member140. The openings150H may expose the entirety or only a portion of a surface of the redistribution layer142b. A material of the passivation layer150is not particularly limited, but may be a photosensitive insulating material such as a PID resin. Alternatively, a solder resist may also be used as a material of the passivation layer150. Alternatively, an insulating resin that does not include a core material, but includes a filler, for example, ABF including an inorganic filler and an epoxy resin, may be used as the material of the passivation layer150. In a case in which an insulating material that includes an inorganic filler and an insulating resin, but does not include a core material, for example, the ABF, or the like, is used as the material of the passivation layer150, the passivation layer150and the resin layer182may have a symmetrical effect to each other, which may be more effective in controlling the warpage.

When the insulating material including the inorganic filler and the insulating resin, for example, the ABF, or the like, is used as the material of the passivation layer150, the insulating layers141aand141bof the second interconnection member140may also include an inorganic filler and an insulating resin. In this case, a weight percentage of inorganic filler included in the passivation layer150may be greater than that of an inorganic filler included in the insulating layers141aand141bof the second interconnection member140. In this case, the passivation layer150may have a relatively low CTE, and may be utilized to control the warpage, similar to the reinforcing layer181.

The passivation layer150may be formed of a material satisfying Equations 1 to 4, if necessary. In this case, board level reliability of the electronic component package may be improved. An elastic modulus is defined as a ratio between stress and deformation, and may be measured through a standard tension test specified in, for example, JIS C-6481, KS M 3001, KS M 527-3, ASTM D882, and the like. In addition, a CTE may refer to a CTE measured using a thermomechanical analyzer (TMA) or a dynamic mechanical analyzer (DMA). In addition, a thickness refers to a thickness of the passivation layer150after being hardened, and may be measured using a general thickness measuring apparatus. In addition, a surface roughness may be formed by a known method such as a surface treatment using cubic zirconia (CZ), and may be measured using a general roughness measuring apparatus. In addition, a moisture absorption ratio may be measured using a general measuring apparatus.
Elastic Modulus×Coefficient of Thermal Expansion=230 GPa·ppm/° C.  Equation 1:
Thickness=10 μm  Equation 2:
Surface Roughness=1 nm  Equation 3:
Moisture Absorption Ratio=1.5%  Equation 4:

The under-bump metal layer160may be additionally configured to improve connection reliability of the connection terminals170to improve board level reliability of the fan-out sensor package100A. The under-bump metal layer160may be disposed on walls in the openings150H of the passivation layer150and the exposed redistribution layer142bof the second interconnection member140. The under-bump metal layer160may be formed by a known metallization method using a known conductive material such as a metal.

The connection terminals170may be additionally configured to physically or electrically externally connect the fan-out semiconductor package100A. For example, the fan-out semiconductor package100A may be mounted on the main board of the electronic device through the connection terminals170. Each of the connection terminals170may be formed of a conductive material, for example, a solder, or the like. However, this is only an example, and a material of each of the connection terminals170is not limited thereto. Each of the connection terminals170may be a land, a ball, a pin, or the like. The connection terminals170may be formed as a multilayer or single layer structure. When the connection terminals170are formed as a multilayer structure, the connection terminals170may include a copper (Cu) pillar and a solder. When the connection terminals170are formed as a single layer structure, the connection terminals170may include a tin-silver solder or copper (Cu). However, this is only an example, and the connection terminals170are not limited thereto. The number, interval, disposition, or the like, of the connection terminals170is not particularly limited, and may be sufficiently modified by a person skilled in the art depending on design particulars. For example, the connection terminals170may be provided in an amount of several tens to several thousands according to the number of connection pads122of the semiconductor chip120, but are not limited thereto, and may also be provided in an amount of several tens to several thousands or more or several tens to several thousands or less.

At least one of the connection terminals170may be disposed in a fan-out region. The fan-out region is a region except for the region in which the semiconductor chip120is disposed. That is, the fan-out semiconductor package100A according to the exemplary embodiment may be a fan-out package. The fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a 3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be mounted on an electronic device without a separate board. Thus, the fan-out package may be manufactured to have a reduced thickness, and may have price competitiveness.

If necessary, a plurality of semiconductor chips (not illustrated) may be disposed in the through-hole110H of the first interconnection member110, and the number of through-holes110H of the first interconnection member110may be plural (not illustrated) and semiconductor chips (not illustrated) may be disposed in the through-holes, respectively. In addition, separate passive components (not illustrated) such as a condenser, an inductor, and the like, may be encapsulated, together with the semiconductor chip, in the through-hole110H. In addition, a surface mounted technology component (not illustrated) may be mounted on the passivation layer150.

FIGS. 12 through 16are schematic views illustrating an example of processes of manufacturing the fan-out semiconductor package ofFIG. 9.

Referring toFIG. 12, a carrier film301may first be prepared. The carrier film301may have metal layers302and303formed on one surface or opposite surfaces thereof. A surface treatment may be performed on a bonded surface between the metal layers302and303in order to facilitate separation in the subsequent separating process. Alternatively, a release layer may be provided between the metal layers302and303to facilitate separation in the subsequent process. The carrier film301may be a known insulating substrate, and a material of the carrier film301is not particularly limited. The metal layers302and303may be generally copper (Cu) foil, but are not limited thereto. That is, the metal layers302and303may be thin films formed of other conductive materials. Then, patterning for forming the first redistribution layer112amay be performed using a dry film304. The first redistribution layer112amay be formed using a known photolithography method. The dry film304may be a known dry film formed of a photosensitive material. Then, a conductive material may be disposed in a patterned space of the dry film304to form the first redistribution layer112a. The first redistribution layer112amay be formed using a plating process. In this case, the metal layer303may serve as a seed layer. The plating process may be electroplating or electroless plating, more specifically, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, a subtractive process, an additive process, a semi-additive process (SAP), a modified semi-additive process (MSAP), or the like, but is not limited thereto. Then, the dry film304may be removed. The dry film304may be removed by a known method such as an etching process, or the like.

Referring toFIG. 13, then, the first insulating layer111aembedding at least a portion of the first redistribution layer112atherein may be formed on the metal layer303. Then, the first vias113apenetrating through the first insulating layer111amay be formed. In addition, the second redistribution layer112bmay be formed on the first insulating layer111a. The first insulating layer111amay be formed by a method of laminating a precursor of the first insulating layer111aby a known lamination method and then hardening the precursor, a method of applying a precursor of the first insulating layer111ausing a known applying method and then hardening the precursor, or the like. The first vias113aand the second redistribution layer112bmay be formed by a method of forming via holes in the first insulating layers111ausing a photolithography method, mechanical drilling, laser drilling, or the like, performing patterning using a dry film, or the like, and filling the via holes and the patterned space by a plating process, or the like. Then, the second insulating layer111bcovering the second redistribution layer112bmay be formed on the first insulating layer111a. Then, the second vias113bpenetrating through the second insulating layer111bmay be formed. In addition, the third redistribution layer112cmay be formed on the second insulating layer111b. A method of forming the second vias113band the third redistribution layer112cmay be the same as that described above. Then, the carrier film301may be peeled off. In this case, the peel-off may indicate that the metal layers302and303are separated from each other. Here, the metal layers may be separated from each other using a blade, but are not limited thereto. That is, all known methods may be used to separate the metal layers from each other. Meanwhile, an example in which the first interconnection member110is formed before the carrier film301is peeled off is described in a series of processes. However, the present disclosure is not limited thereto. For example, the first interconnection member110may also be formed according to the process described above after the carrier film301is peeled off. That is, a sequence is not necessarily limited to the abovementioned sequence.

Referring toFIG. 14, then, the remaining metal layer303may be removed by a known etching method, or the like, and the through-hole110H may be formed in the first interconnection member110. The through-hole110H may be formed using mechanical drilling or laser drilling. However, the through-hole110H is not limited thereto, and may also be formed by a sand blasting method using particles for polishing, a dry etching method using plasma, or the like. In a case in which the through-hole110H is formed using mechanical drilling or laser drilling, a desmearing process such as a permanganate method, or the like, may be performed to remove resin smear in the through-hole110H. Next, an adhesive film305may be attached on one surface of the first interconnection member110. Any material that may fix the first interconnection member110may be used as the adhesive film305. As a non-restrictive example, a known tape, or the like, may be used. An example of the known tape may include a thermosetting adhesive tape of which adhesion is weakened by heat treatments, an ultraviolet-curable adhesive tape of which adhesion is weakened by ultraviolet ray irradiation, or the like. Then, the semiconductor chip120may be disposed in the through-hole110H of the first interconnection member110. For example, the semiconductor chip120may be disposed by a method of attaching the semiconductor chip120to the adhesive film305in the through-hole110H. The semiconductor chip120may be disposed in a face-down form so that the connection pads122are attached to the adhesive film305.

Referring toFIG. 15, then, the semiconductor chip120may be encapsulated using the encapsulant130. The encapsulant130may cover the first interconnection member110and the inactive surface of the semiconductor chip120, and may fill a space within the through-hole110H. The encapsulant130may be formed by a known method. For example, the encapsulant130may be formed by a method of laminating a resin for forming the encapsulant130in a non-hardened state and then hardening the resin. Alternatively, the encapsulant130may be formed by a method of applying a resin for forming the encapsulant130in a non-hardened state on the adhesive film305to encapsulate the first interconnection member110and the semiconductor chip120and then hardening the resin. The semiconductor chip120may be fixed by hardening. As the method of laminating the resin, for example, a method of performing a hot press process of compressing the resin for a predetermined time at a high temperature, decompressing the resin, and then cooling the resin to room temperature, cooling the resin in a cold press process, and then separating a work tool, or the like, may be used. As the method of applying the resin, for example, a screen printing method of applying ink with a squeegee, a spray printing method of applying ink in a mist form, or the like, may be used. Then, the reinforcing layer181may be formed on the encapsulant130. The reinforcing layer181may be attached in a hardened state (a c-stage) such as an unclad CCL, or the like, to the encapsulant130. Therefore, a boundary surface between the encapsulant130and the reinforcing layer181may have an approximately linear form after the reinforcing layer181is attached to the encapsulant130. The encapsulant130may be hardened after the reinforcing layer181is attached to the encapsulant130. In this case, the reinforcing layer181may control warpage due to hardening contraction of the encapsulant130. In addition, in this case, close adhesion between the reinforcing layer181and the encapsulant130may be excellent. Then, the adhesive film305may be peeled off. A method of peeling the adhesive film off is not particularly limited, but may be a known method. For example, in a case in which the thermosetting adhesive tape of which adhesion is weakened by heat treatment, the ultraviolet-curable adhesive tape of which adhesion is weakened by ultraviolet ray irradiation, or the like, is used as the adhesive film305, the adhesive film305may be peeled off after the adhesion of the adhesive film305is weakened by heat-treating the adhesive film305or may be peeled off after the adhesion of the adhesive film305is weakened by irradiating the adhesive film305with ultraviolet light. Then, the second interconnection member140may be formed on the first interconnection member110and the active surface of the semiconductor chip120from which the adhesive film305is removed. The second interconnection member140may be formed by sequentially forming the insulating layers141aand141band then forming the redistribution layers142aand142band the vias143aand143bon and in the insulating layers141aand141b, respectively, by the plating process as described above, or the like. In addition, the resin layer182may be formed on the reinforcing layer181. In addition, the passivation layer150may be formed on the second interconnection member140. The resin layer182and the passivation layer150may also be formed by a method of laminating precursors of the resin layer182and the passivation layer150and then hardening the precursors, a method of applying materials for forming the resin layer182and the passivation layer150and then hardening the materials, or the like.

Referring toFIG. 16, then, the openings150H may be formed in the passivation layer150to expose at least portions of the redistribution layer142bof the second interconnection member140, and the under-bump metal layer160may be formed in the openings150H by a known metallization method. In addition, the openings182H penetrating through the encapsulant130, the reinforcing layer181, and the resin layer182and exposing at least portions of the third redistribution layer112cof the first interconnection member110may be formed. The openings182H may be formed by mechanical drilling, laser drilling, a sand blasting method using particles for polishing, a dry etching method using plasma, or the like. Then, the connection terminals170may be formed on the under-bump metal layer160. A method of forming the connection terminals170is not particularly limited. That is, the connection terminals170may be formed by the method well-known in the related art depending on a structure or a form thereof. The connection terminals170may be fixed by reflow, and portions of the connection terminals170may be embedded in the passivation layer150in order to enhance fixing force, and the remaining portions of the connection terminals170may be externally exposed, such that reliability may be improved.

Meanwhile, a series of processes may be processes of preparing the carrier film301having a large size, manufacturing a plurality of fan-out semiconductor packages100A, and then singulating the plurality of fan-out semiconductor packages into individual fan-out semiconductor packages100A through a cutting process in order to facilitate mass production. In this case, productivity may be excellent.

FIG. 17is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring to the drawing, in a fan-out semiconductor package100B according to another exemplary embodiment in the present disclosure, only a reinforcing layer181may be attached to an encapsulant130. Even in a case in which a separate resin layer182, or the like, is not attached to the reinforcing layer181as described above, warpage may be controlled. The reinforcing layer181may be formed of, for example, an unclad CCL, prepreg, or the like, including a core material, an inorganic filler, and an insulating resin. The reinforcing layer181may have an elastic modulus relatively greater than that of the encapsulant130, and may have a CTE smaller than that of the encapsulant130. In this case, a warpage suppression effect may be particularly good. The reinforcing layer181may be attached in a hardened state (a c-stage) to the encapsulant130. In this case, a boundary surface between the encapsulant130and the reinforcing layer181may have an approximately linear shape.

A description, or the like, of configurations other than the abovementioned configuration may overlap the description provided above, and is thus omitted. In addition, a description of processes of manufacturing the fan-out semiconductor package100B in which the resin layer182is not formed may overlap the description provided above, and is thus omitted.

FIG. 18is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring to the drawing, in a fan-out semiconductor package100C according to another exemplary embodiment in the present disclosure, only a reinforcing layer181may be attached to an encapsulant130. In this case, openings181H penetrating through the encapsulant130and the reinforcing layer181and exposing at least portions of a third redistribution layer112cof a first interconnection member110may be formed in the reinforcing layer181. Even in a case in which a separate resin layer182, or the like, is not attached to the reinforcing layer181as described above, the openings181H may be formed in the reinforcing layer181. However, in this case, it may be more difficult to form the openings181H than in a case in which the resin layer182is present, due to characteristics of a material of the reinforcing layer181including a core material. In addition, the core material of the reinforcing layer181may be exposed to walls of the openings181H, and an additional process for removing the exposed core material may thus be required. The reinforcing layer181may be attached to the encapsulant130in a hardened state (a c-stage). In this case, a boundary surface between the encapsulant130and the reinforcing layer181may have an approximately linear shape.

A description, or the like, of configurations other than the abovementioned configuration may overlap the description provided above, and is thus omitted. In addition, a description of processes of manufacturing the fan-out semiconductor package100C in which the resin layer182is not formed may overlap the description provided above, and is thus omitted.

FIG. 19is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring to the drawing, in a fan-out semiconductor package100D according to another exemplary embodiment in the present disclosure, a reinforcing layer183may be formed of, for example, prepreg, or the like, including a core material, an inorganic filler, and an insulating resin, and an encapsulant130may be formed of, for example, ABF, or the like, that includes an inorganic filler and an insulating resin, but does not include a core material. In this case, when a weight percentage of the inorganic filler included in the encapsulant130is a1and a weight percentage of the inorganic filler included in the reinforcing layer183is a2, a1<a2. For example, 1.10<a2/a1<1.95. That is, the reinforcing layer183of which a concentration of the inorganic filler is relatively high may have a relatively low CTE, and the encapsulant130of which a concentration of the inorganic filler is relatively low may have a relatively high CTE. Therefore, the encapsulant130may have excellent resin flowability, and the reinforcing layer183may be advantageous in controlling warpage. In addition, when a thickness of the reinforcing layer183is t1, a thickness of a portion of the encapsulant130covering a first interconnection member110is t2, and a thickness of a portion of the encapsulant130covering an inactive surface of a semiconductor chip120is t3, t2<t1, and t3<t1. For example, 0.2<t2/t1<0.6, and 0.2<t3/t1<0.6. That is, the thickness of the reinforcing layer183may be greater than those of the portions of encapsulant130covering the first interconnection member110and the inactive surface of the semiconductor chip120, which may be more advantageous in controlling warpage.

Meanwhile, the reinforcing layer183may be attached to the encapsulant130in a non-hardened state and be then hardened. Therefore, a material of the reinforcing layer183having a relatively small CTE may permeate into a through-hole110H due to movement of a mixing or boundary surface between heterogeneous materials in contact with each other. For example, the prepreg, or the like, including the core material, the inorganic filler, and the insulating resin may be attached to the encapsulant130in a semi-hardened state in an b-stage and may then be hardened by the subsequent process in a c-stage, such that the reinforcing layer183may be formed. In this case, a mixing or boundary surface between materials may move due to a difference between concentrations of the inorganic fillers of the reinforcing layer183and the encapsulant130. Resultantly, the boundary surface between the encapsulant130and the reinforcing layer183may have a non-linear shape. For example, the boundary surface between the encapsulant130and the reinforcing layer183may have curved portions183P bent toward spaces between walls of the through-hole110H of the first interconnection member110and the semiconductor chip120. In this case, a contact area between the reinforcing layer183and the encapsulant130may be increased, such that close adhesion between the reinforcing layer183and the encapsulant130may be further improved.

A description, or the like, of configurations other than the abovementioned configuration may overlap the description provided above, and is thus omitted. In addition, a description of processes of manufacturing the fan-out semiconductor package100D in which a resin layer182is not formed and the reinforcing layer183of which a material and a hardened state are different from those of the reinforcing layer181described above overlaps descriptions provided above, and is thus omitted.

FIG. 20is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring to the drawing, in a fan-out semiconductor package100E according to another exemplary embodiment in the present disclosure, a reinforcing layer184may be formed of, for example, asymmetrical prepreg, or the like, which includes a core material, an inorganic filler, and an insulating layer, and in which a weight percentage of inorganic filler included in one side184aof the reinforcing layer184in contact with an encapsulant130and a weight percentage of inorganic filler included in the other side184bof the reinforcing layer184opposing one side184ain relation to the core material184care different from each other. The encapsulant130may be formed of, for example, ABF, or the like, including an inorganic filler and an insulating resin, but not including a core material. In this case, when a weight percentage of the inorganic filler included in the encapsulant130is a1, a weight percentage of the inorganic filler included in one side184aof the reinforcing layer184in contact with the encapsulant130is a2, and a weight percentage of the inorganic filler included in the other side184bof the reinforcing layer184opposing one side184ais a3, a1<a2<a3. For example,1.10<a3/a1<1.95. That is, a CTE of the other side184bof the reinforcing layer184may be lowest, a CTE of one side184aof the reinforcing layer184may be intermediate, and a CTE of the encapsulant130may be highest. Therefore, the encapsulant130may have excellent resin flowability, one side184aof the reinforcing layer184may secure excellent close adhesion with the encapsulant130, and the other side184bof the reinforcing layer184may effectively control warpage. In addition, when a thickness of the reinforcing layer184is t1, a thickness of a portion of the encapsulant130covering a first interconnection member110is t2, and a thickness of a portion of the encapsulant130covering an inactive surface of a semiconductor chip120is t3, t2<t1, and t3<t1. For example,0.2<t2/t1<0.6, and 0.2<t3/t1<0.6. In this case, warpage may be more easily controlled.

Meanwhile, the reinforcing layer184may be attached, in a non-hardened state, to the encapsulant130, in a semi-hardened state, and then hardened. Therefore, a material of the reinforcing layer184having a relatively small CTE may permeate into a through-hole110H due to movement of a mixing or boundary surface between heterogeneous materials in contact with each other. That is, for example, the asymmetrical prepreg, or the like, including the core material, the inorganic filler, and the insulating resin may be attached to the encapsulant130in a b-stage and may then be hardened by the subsequent process in a c-stage, such that the reinforcing layer184may be formed. In this case, a mixing or boundary surface between materials may move due to a difference between weight percentages of the inorganic fillers of one side184aof the reinforcing layer184and the encapsulant130. Resultantly, the boundary surface between the encapsulant130and the reinforcing layer184may have a non-linear shape. For example, portions of one side184aof the reinforcing layer184may dimple toward the encapsulant130filling spaces between the first interconnection member110and the semiconductor chip120within the through-hole110H of the first interconnection member110, such that curved portions184P may be formed. In this case, a contact area between the reinforcing layer184and the encapsulant130may be increased, such that close adhesion between the reinforcing layer184and the encapsulant130may be further improved.

A description, or the like, of configurations other than the abovementioned configuration may overlap the description provided above, and is thus omitted. In addition, a description of processes of manufacturing the fan-out semiconductor package100E in which a resin layer182is not formed and the reinforcing layer184of which a material and a hardened state are different from those of the reinforcing layer181described above overlaps descriptions provided above, and is thus omitted.

FIG. 21is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring to the drawing, in a fan-out semiconductor package100F according to another exemplary embodiment in the present disclosure, only a reinforcing layer185may be attached to an encapsulant130. In this case, the reinforcing layer185may be formed of, for example, ABF, or the like, that includes an inorganic filler and an insulating resin, but does not include a core material. In addition, the encapsulant130may also be formed of, for example, ABF, or the like, that includes an inorganic filler and an insulating resin, but does not include a core material. However, the reinforcing layer185may have an elastic modulus greater than that of the encapsulant130or a CTE smaller than that of the encapsulant130to suppress warpage. The reinforcing layer185may be attached to the encapsulant130in a hardened state (a c-stage). In this case, a boundary surface between the encapsulant130and the reinforcing layer185may have an approximately linear shape.

A description, or the like, of configurations other than the abovementioned configuration may overlap the description provided above, and is thus omitted. In addition, a description of processes of manufacturing the fan-out semiconductor package100F in which a resin layer182is not formed and the reinforcing layer185of which a material and a hardened state are different from those of the reinforcing layer181described above overlaps descriptions provided above, and is thus omitted.

FIG. 22is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring to the drawing, in a fan-out semiconductor package100G according to another exemplary embodiment in the present disclosure, only a reinforcing layer185may be attached to an encapsulant130. In this case, openings185H penetrating through the reinforcing layer185and exposing at least portions of a third redistribution layer112cof a first interconnection member110may be formed in the reinforcing layer185. In a case in which the reinforcing layer185does not include a core material, the openings185H may be easily formed. The reinforcing layer185may be attached in a hardened state (a c-stage) to the encapsulant130, and a boundary surface between the encapsulant130and the reinforcing layer185may thus have an approximately linear shape.

A description, or the like, of configurations other than the abovementioned configuration may overlap the description provided above, and is thus omitted. In addition, a description of processes of manufacturing the fan-out semiconductor package100G in which a resin layer182is not formed and the reinforcing layer185of which a material and a hardened state are different from those of the reinforcing layer181described above overlaps descriptions provided above, and is thus omitted.

FIG. 23is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring to the drawing, in a fan-out semiconductor package100H according to another exemplary embodiment in the present disclosure, a reinforcing layer186may be formed of, for example, ABF, or the like, that includes an inorganic filler and an insulating resin, but does not include a core material, and an encapsulant130may also be formed of, for example, ABF, or the like, that includes an inorganic filler and an insulating resin, but does not include a core material. In this case, when a weight percentage of the inorganic filler included in the encapsulant130is a1and a weight percentage of the inorganic filler included in the reinforcing layer186is a2, a1<a2. For example, 1.10<a2/a1<1.95. That is, the reinforcing layer186of which a concentration of the inorganic filler is relatively high may have a relatively low CTE, and the encapsulant130of which a concentration of the inorganic filler is relatively low may have a relatively high CTE. Therefore, the encapsulant130may have excellent resin flowability, and the reinforcing layer186may be advantageous in controlling warpage. In addition, when a thickness of the reinforcing layer186is t1, a thickness of a portion of the encapsulant130covering a first interconnection member110is t2, and a thickness of a portion of the encapsulant130covering an inactive surface of a semiconductor chip120is t3, t2<t1, and t3<t1. For example, 0.2<t2/t1<0.6, and 0.2<t3/t1<0.6. That is, the thickness of the reinforcing layer186may be greater than those of the encapsulant130covering the first interconnection member110and the inactive surface of the semiconductor chip120, which may be more advantageous in controlling warpage.

Meanwhile, the reinforcing layer186may be attached, in a non-hardened state, to the encapsulant130, in a semi-hardened state, and then hardened. Therefore, a material of the reinforcing layer186having a relatively small CTE may permeate into a through-hole110H due to movement of a mixing or boundary surface between heterogeneous materials in contact with each other. That is, for example, the ABF, or the like, that includes the inorganic filler and the insulating resin, but does not include a glass cloth may be attached in a b-stage to the encapsulant130and be then hardened in a c-stage by the subsequent process, such that the reinforcing layer186may be formed. In this case, a mixing or boundary surface between materials may move due to a difference between weight percentages of the inorganic fillers of the reinforcing layer186and the encapsulant130. Resultantly, the boundary surface between the encapsulant130and the reinforcing layer186may have an approximately non-linear shape. For example, portions of the reinforcing layer186may dimple toward the encapsulant130filling spaces between the first interconnection member110and the semiconductor chip120within the through-hole110H of the first interconnection member110, such that curved portions186P may be formed. In this case, a contact area between the reinforcing layer186and the encapsulant130may be increased, such that close adhesion between the reinforcing layer186and the encapsulant130may be further improved.

A description, or the like, of configurations other than the abovementioned configuration may overlap the description provided above, and is thus omitted. In addition, a description of processes of manufacturing the fan-out semiconductor package100H in which a resin layer182is not formed and the reinforcing layer186of which a material and a hardened state are different from those of the reinforcing layer181described above overlaps descriptions provided above, and is thus omitted.

FIG. 24is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring to the drawing, in a fan-out semiconductor package100I according to another exemplary embodiment in the present disclosure, a first redistribution layer112amay be recessed in a first insulating layer111a, such that a lower surface of the first insulating layer111amay have a step portion with respect to a lower surface of the first redistribution layer112a. Resultantly, when an encapsulant130is formed, a phenomenon in which a material of the encapsulant130bleeds to pollute the first redistribution layer112amay be prevented. Meanwhile, since the first redistribution layer112ais recessed in the first insulating layer111aas described above, a lower surface of the first redistribution layer112aof a first interconnection member110may be disposed on a level above a lower surface of a connection pad122of a semiconductor chip120. In addition, a distance between a redistribution layer142aof a second interconnection member140and the first redistribution layer112aof the first interconnection member110may be greater than that between the redistribution layer142aof the second interconnection member140and the connection pad122of the semiconductor chip120.

A description, or the like, of configurations other than the abovementioned configuration may overlap the description provided above, and is thus omitted. In addition, a description of processes of manufacturing the fan-out semiconductor package100I in which the step portion is formed by partially removing the first redistribution layer112aat the time of removing a metal layer303may overlap the description provided above, and is thus omitted. Meanwhile, the features of the fan-out semiconductor packages100B to100H may also be applied to the fan-out semiconductor package100I.

FIG. 25is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring to the drawing, in a fan-out semiconductor package100J according to another exemplary embodiment in the present disclosure, a first interconnection member110may include a first insulating layer111a, a first redistribution layer112aand a second redistribution layer112bdisposed on opposite surfaces of the first insulating layer111a, respectively, a second insulating layer111bdisposed on the first insulating layer111aand covering the first redistribution layer112a, a third redistribution layer112cdisposed on the second insulating layer111b, a third insulating layer111cdisposed on the first insulating layer111aand covering the second redistribution layer112b, and a fourth redistribution layer112ddisposed on the third insulating layer111c. The first to fourth redistribution layers112a,112b,112c, and112dmay be electrically connected to connection pads122of a semiconductor chip120. Since the first interconnection member110may include a larger number of redistribution layers112a,112b,112c, and112d, a second interconnection member140may be further simplified. Therefore, a decrease in a yield depending on a defect occurring in a process of forming the second interconnection member140may be improved. Meanwhile, although not illustrated in the drawing, the first to fourth redistribution layers112a,112b,112c, and112dmay be electrically connected to each other by first to third vias penetrating through the first to third insulating layers111a,111b, and111c.

The first insulating layer111amay have a thickness greater than those of the second insulating layer111band the third insulating layer111c. The first insulating layer111amay be relatively thick in order to maintain rigidity, and the second insulating layer111band the third insulating layer111cmay be introduced in order to form a larger number of redistribution layers112cand112d. The first insulating layer111amay include an insulating material different from those of the second insulating layer111band the third insulating layer111c. For example, the first insulating layer111amay be, for example, prepreg including a core material, an inorganic filler, and an insulating resin, and the second insulating layer111band the third insulating layer111cmay be an ABF or a photosensitive insulating film including an inorganic filler and an insulating resin. However, the materials of the first insulating layer111aand the second and third insulating layers111band111care not limited thereto.

A lower surface of the third redistribution layer112cof the first interconnection member110may be disposed on a level below a lower surface of the connection pads122of the semiconductor chip120. In addition, a distance between a redistribution layer142of the second interconnection member140and the third redistribution layer112cof the first interconnection member110may be smaller than that between the redistribution layer142of the second interconnection member140and the connection pads122of the semiconductor chip120. Here, the third redistribution layer112cmay be disposed in a protruding form on the second insulating layer111b, resulting in contact with the second interconnection member140. The first redistribution layer112aand the second redistribution layer112bof the first interconnection member110may be disposed on a level between an active surface and an inactive surface of the semiconductor chip120. The first interconnection member110may be formed to a thickness corresponding to that of the semiconductor chip120. Therefore, the first redistribution layer112aand the second redistribution layer112bformed in the first interconnection member110may be disposed on a level between the active surface and the inactive surface of the semiconductor chip120.

Thicknesses of the redistribution layers112a,112b,112c, and112dof the first interconnection member110may be greater than that of the redistribution layer142of the second interconnection member140. Since the first interconnection member110may have a thickness equal to or greater than that of the semiconductor chip120, the redistribution layers112a,112b,112c, and112dmay also be formed to be large. On the other hand, the redistribution layer142of the second interconnection member140may be formed to have a relatively small size for thinness.

A description, or the like, of configurations other than the abovementioned configuration may overlap the description provided above, and is thus omitted. In addition, a description of processes of manufacturing the fan-out semiconductor package100J except for a configuration of a first interconnection member110may overlap the description provided above, and is thus omitted. Meanwhile, the features of the fan-out semiconductor packages100B to100H may also be applied to the fan-out semiconductor package100J.

FIG. 26is schematic views illustrating a case in which warpage is generated in a fan-out semiconductor package.

Referring to the drawing, a thermosetting resin film that may firmly fix a first interconnection member510including an insulating layer511, redistribution layers512aand512b, vias513, and the like, and a semiconductor chip520including a body521, electrode pads522, and the like, may be used as a material of an encapsulant530encapsulating the first interconnection member510and the semiconductor chip520. In detail, the thermosetting resin film having a high CTE, generally having good resin flowability, may be used to form the encapsulant530, in order to completely fill a space of a through-hole510H between the first interconnection member510and the semiconductor chip520with a resin and increase close adhesion between the first interconnection member510and the semiconductor chip520. However, it may be appreciated that in this thermosetting resin film, heat-hardening contraction of the resin is large, such that warpage W1is severely generated in a package after the resin is hardened. Therefore, it may be difficult to form fine circuit patterns later.

FIG. 27is schematic views illustrating a case in which warpage of a fan-out semiconductor package is suppressed.

Referring to the drawings, it may be considered that a thermosetting resin film having a low CTE is used as a material of an encapsulant540encapsulating a first interconnection member510including an insulating layer511, redistribution layers512aand512b, vias513, and the like, and a semiconductor chip510including a body521, electrode pads522, and the like. It may be appreciated that in a case of using the thermosetting resin film having the low CTE as the material of the encapsulant540, warpage W2is suppressed as compared to in a case of using a thermosetting resin film having a high CTE. However, a content of inorganic filler in the thermosetting resin film is generally increased in order to reduce a CTE, such that a resin does not sufficiently fill a fine space due to a reduction in resin flowability, which causes a void, or the like. In addition, delamination between a first interconnection member and a semiconductor chip, or the like, may be generated due to a reduction in close adhesion between the first interconnection member and the semiconductor chip.

FIG. 29is a graph for comparing warpage suppressing effects of fan-out semiconductor packages with one another.

Referring to the drawing, Comparative Example 1 refers to a case in which a thermosetting resin film having a high CTE, having good resin flowability, is used as a material of an encapsulant as illustrated inFIG. 26. It may be appreciated that in Comparative Example 1, warpage is severely generated due to high heat-hardening contraction of the encapsulant. Comparative Example 2 refers to a case in which a thermosetting resin film having a low CTE is used as a material of an encapsulant in order to suppress warpage, as illustrated inFIG. 27. In Comparative Example 2, warpage might be suppressed due to low heat-hardening contraction of the encapsulant, but the problems such as the void, the delamination, and the like, as described above, have additionally occurred. The Inventive Example refers to a case in which a thermosetting resin film having a high CTE, having good resin flowability, is used as a material of an encapsulant and a reinforcing layer having an elastic modulus greater than that of the encapsulant and having a CTE smaller than that of the encapsulant is introduced on the encapsulant as in the present disclosure. In the Inventive Example, warpage might be suppressed at a level similar to that of Comparative Example 2 without causing problems such as voids and delamination.

As set forth above, according to the exemplary embodiment in the present disclosure, a fan-out semiconductor package in which a warpage problem may be effectively solved may be provided.