Three-dimensional integrated circuit systems in a package and methods therefor

A method for making a packaged semiconductor device includes dispensing a first adhesive into a first cavity of a substrate having a first major surface and a second major surface. The first cavity extends into the substrate from the second major surface. The method further includes placing a first component having a thickness less than a thickness of the substrate into the first cavity such that the first adhesive physically contacts a first major surface of the first component and at least partially fills a gap between sidewalls of the first component and sidewalls of the first cavity. After placing the first component, a second major surface of the first component is coplanar with the second major surface of the substrate.

BACKGROUND

Field

This disclosure relates generally to semiconductor devices, and more specifically, to stacked integrated circuit systems in a package, and methods therefor.

Related Art

Three-dimensional integrated circuit (ICs) systems in package (SiP) may comprise a number of package layers stacked one upon another with inter-package connection comprising through-vias. Three-dimensional IC SiP packaging technologies usually have lengthy process. For example, a three-dimensional fan-out wafer level package requires panels containing one or more components to be joined together, through-package vias to be formed, and build-up layers to be formed. In addition, components on different layers of the package can have different heights or thicknesses. The complex processes required to form SiPs can present manufacturing challenges, increased cost, and reliability issues. It is therefore desirable to develop three-dimensional packaging technology with reduced process complexity to improve manufacturability, and reduce cost and cycle time.

DETAILED DESCRIPTION

Embodiments of systems and methods disclosed herein include embedding die and other components in cavities in a prefabricated substrate. Vias are formed through the substrate to allow components to be connected on either side of the substrate. The “bottom side” of the substrate has routing layers which can act as a “metal 0” layer in the package. The “top side” of the substrate has solder mask openings to receive one or more packages or surface mount devices. The components to be placed in the cavities can have different thicknesses, which would ordinarily complicate manufacturing due to the resulting uneven surface. To solve this problem, the variation in thickness is compensated by using epoxy to hold the die and components in the cavity and create an even surface at the top surface of the substrate by embedding the components at different depths in the cavities. A relatively high viscosity epoxy can be used to make sure the die and component stay in the place after placement. An oversized nozzle on an automated component placement system, also referred to as a pick & place machine or other suitable technique, can be used to make sure the components are placed coplanar to the top surface of substrate. Additional epoxy can be dispensed to fill the gap between the components and substrate. The interconnect layer is built-up and a ball grid array is formed after the epoxy is cured. The product can be processed in a large panel form then singulated into single packages. Package on package and surface mount devices can be assembled after singulation or during printed circuit board assembly.

FIG. 1is a flow diagram of an embodiment of a method100for manufacturing a three-dimensional system in a package (SiP). Method100is described with reference toFIGS. 2-7, which illustrate a three-dimensional SiP200in various stages of manufacture according to the method ofFIG. 1. Referring toFIGS. 1 and 2, process102of method100includes placing a laminated substrate202onto an adhesive carrier tape204to hold substrate in place during subsequent manufacturing. Substrate202can be also made by other technology or materials, for instance monolithic substrate is made of organic or inorganic (i.e. ceramic, glass, silicon or metal). Tape204is not permanently attached and will typically be removed during a subsequent stage of manufacturing.

With one embodiment, substrate202can be a laminate substrate that includes an electrically non-conductive portion206with one of more cavities208,210of the same or different sizes. Cavities208,210typically extend completely through non-conductive portion206from a first or top major surface of substrate202to a second or bottom major surface of substrate202. Cavities208,210can extend only partially through substrate202in other implementations. Multiple electrically conductive through hole vias (THVs)210,211,212can be formed in non-conductive portion206by mechanical or laser drill followed by metallization processes, e.g. copper plating and connected between respective electrically conductive routing traces218,220,222on the upper major surface of non-conductive portion206and contact pads224,226,228on the bottom major surface of non-conductive portion206. The bottom major surface layer may include routing traces as well.

Solder mask230is formed on the bottom major surface to leave openings around contact pads224. Solder mask is shown directly adjacent and in contact with tape204to retain substrate202and close one side of cavities208,210while the other side of cavities208,210are open at the top major surface of substrate202. In some embodiments, solder mask can be formed on the top major surface (not shown).

Referring toFIGS. 1 and 3,FIG. 3illustrates a cross-sectional view of an embodiment of a three-dimensional package200during a subsequent stage of manufacture according to process104of method100ofFIG. 1. Process104includes dispensing an adhesive304,306such as epoxy or other suitable adhesive through dispenser302into cavities208,210. The volume of a component to be placed in a particular cavity208,210added to the volume of adhesive304,306dispensed in a respective cavity208,210is generally less than the total volume of cavity208,210. Adhesive304,306has a viscosity that is high enough to prevent a component from sinking further into the cavity after being placed in the cavity. Examples of adhesives suitable for use as adhesive304,306are glob top dam epoxy, commercially available from several manufacturers. The material can consist of an epoxy resin, anhydride hardener, silica filler particles, and rheological agents. The material's viscosity during the dispense process may be less than 1,000 Pascal-second (Pa-s) and after the dispense process may be greater than 1,000 Pa-s. Depending on the material system used, the viscosities may be lower and provide the same effect. For example, the viscosity during dispense may be less than 500 Pa-s and after dispense may be greater than 500 Pa-s. Dispenser302can be operated manually or by automated equipment programmed to dispense a desired amount of adhesive304,306in each cavity208,210. Note that the volume of each cavity208,210may be different, or two or more cavities208,210may have the same volume that is different from the volume of one or more other cavities208,210.

Referring toFIGS. 1 and 4,FIG. 4illustrates a cross-sectional view of an embodiment of a three-dimensional package200during a subsequent stage of manufacture according to process106of method100ofFIG. 1. Process106includes placing components406,408such as integrated circuit die for processing logic, memory, and/or other digital and analog circuitry, discrete components such as resistors, capacitors, and inductors, as well as discrete semiconductor devices such as transistors and diodes. Components406,408can be placed using an automated component placement system (also referred to as a “pick and place machine) with a nozzle402that is configured to grasp a component406,408from a holding area, and release the component406,408in a specified cavity208,210(FIG. 3) where adhesive306,304has already been deposited.

Nozzle402can have side extensions404that are wider than cavities208,210. As nozzle402is lowered, side extensions404prevent the top surface of components406,408from being placed lower than the surrounding top surface of substrate202, since side extensions404meet the top surface of substrate202. The top surface of components406,408are typically held against the bottom surface of nozzle402with a vacuum force during movement and placement. Once placed, the vacuum is removed and components406,408remain in place due to the relatively high viscosity of adhesive304,306. Once adhesive304,306cures, components406,408are immovably positioned so that the upper surface of substrate202remains even with the upper surface of components406,408to create a flat surface on which the interconnection layers can be formed using various known technologies, e.g. build up or lamination processes.

Referring toFIGS. 1 and 5,FIG. 5illustrates a cross-sectional view of an embodiment of package200during a subsequent stage of manufacture according to process108of method100ofFIG. 1. Process108includes using dispenser502to dispense additional adhesive504on top of adhesive304,306to fill any gap in cavities208,210between the top of adhesive304,306and the top surface of substrate202and components406,408. Additional adhesive504can be lower viscosity than adhesive304,306. The viscosity during dispense may be less than 100 Pa-s. The height of additional adhesive504is approximately is sufficient to maintain a relatively flat surface among substrate202, components406,408. In an alternative embodiment, the adhesive504may not be necessary. The gap in cavities208,210between the top of adhesive304,306and the top surface of substrate202and components406,408can be subsequently filled with dielectric material602.

Referring toFIGS. 1 and 6,FIG. 6illustrates a cross-sectional view of an embodiment of package200during a subsequent stage of manufacture according to process110of method100ofFIG. 1. Once additional adhesive504cures, process110includes forming interconnect layer600over the top of substrate202, components406,408, and adhesive504. Even though components406,408have different thicknesses, the level surface of package200that results from embedding components at different levels in viscous adhesive304,306allows interconnect layer600to be formed using standard processes, alleviating problems associated with having components406,408at different heights.

Interconnect layer600can include one or more layers of dielectric material602with vias604,606,608filled with conductive material between contacts610,612,616on the upper surface of interconnect layer600and contacts218,220,222on the upper surface of substrate202. Additional vias618,620can be formed between contacts622,624on component406and contacts626,628on the top surface of interconnect layer600. Although not shown, other interconnects including vias and contacts can be included for component408as well as other components in a package and contacts on substrate202. Additional layers of dielectric material with vias formed between contacts can also be included as part of package200. A solder mask layer (not shown) can be formed over contacts610,612,616,626to define solder ball contact area. The interconnection layer600can be formed using various known technologies e.g. build up or lamination processes.

Once interconnect layer600is formed, solder balls630,632,634,636can be formed on respective contacts610,612,626,636to allow package to be attached to another substrate such as a printed circuit board or other suitable device. After solder balls630-636are formed, package200can be singulated to separate package200from other packages (not shown) that can include similar or different components as package200. Tape204can be removed before or after package200is singulated.

Referring toFIGS. 1 and 7,FIG. 7illustrates a cross-sectional view of an embodiment of three-dimensional package200during a subsequent stage of manufacture according to process112of method100ofFIG. 1. Process112includes adding package700and surface mount device (SMD)706to package200. Package700is attached to contacts228,226with solder balls702,703. SMD706is attached to contact224with solder704. In other embodiments, additional packages and components can be added to package200, whether being attached to contacts on package200, or contacts (not shown) on package700.

FIG. 8is a flow diagram of another embodiment of a method800for manufacturing a three-dimensional system in a package (SiP). Method800is described with reference toFIGS. 9-13, which illustrate a three-dimensional SiP900in various stages of manufacture according to the method ofFIG. 8. Referring toFIGS. 8 and 9, process802of method800includes placing a substrate202onto an adhesive carrier tape204to hold substrate in place during subsequent manufacturing. Substrate202can be also made by other technology or materials, for instance monolithic substrate is made of organic or inorganic (i.e. ceramic, glass, silicon or metal). Tape204is not permanently attached and will typically be removed during a subsequent stage of manufacturing.

With one embodiment, substrate202can be a laminate substrate that includes an electrically non-conductive portion206with one of more cavities208,210of the same or different sizes. Cavities208,210typically extend completely through non-conductive portion206from a first or top major surface of substrate202to a second or bottom major surface of substrate202. Cavities208,210can extend only partially through substrate202in other implementations. Multiple electrically conductive through hole vias (THVs)210,211,212can be formed in non-conductive portion206by mechanical or laser drill followed by metallization processes, e.g. copper plating, and connected between respective electrically conductive routing traces218,220,222on the upper major surface of non-conductive portion206and contact pads224,226,228on the bottom major surface of non-conductive portion206. The bottom major surface layer may include routing traces as well.

Solder mask230is formed on the bottom major surface to leave openings around contact pads224. Solder mask is shown directly adjacent and in contact with tape204to retain substrate202and close one side of cavities208,210while the other side of cavities208,210are open at the top major surface of substrate202. In some embodiments, solder mask can be formed on the top major surface (not shown).

Referring toFIG. 8, process804of method800includes determining the volume of cavities208,210. Process804can be performed by a controller in an automated component placement machine (not shown) that includes or has access to information regarding the volume or information such as height, width, and length to calculate the volume of cavities208,210, as well as the volume or height, width, and length of components to placed in respective cavities208,210. The volume of cavities208,210less the volume of a respective component to be placed in the cavity208,210is the volume of adhesive to be dispensed in a respective cavity208,210.

Referring toFIGS. 8 and 10,FIG. 10illustrates a cross-sectional view of an embodiment of a three-dimensional package900during a subsequent stage of manufacture according to process806of method800ofFIG. 8. Process806includes dispensing an adhesive1002,1004such as epoxy or other suitable adhesive through dispenser302into cavities208,210. The volume of a component to be placed in a particular cavity208,210added to the volume of adhesive1002,1004dispensed in a respective cavity208,210is ideally the same as the total volume of cavity208,210. Adhesive1002,1004has a viscosity that is high enough to prevent a component from sinking further into the cavity208,210after being placed in the cavity208,210. Examples of adhesives suitable for use as adhesive304,306is glob top dam epoxy that is commercially available from several manufacturers. The material can consist of an epoxy resin, anhydride hardener, silica filler particles, and rheological agents. The material's viscosity during the dispense process may be less than 1,000 Pascal-second (Pa-s) and after the dispense process may be greater than 1,000 Pa-s. Depending on the material system used, the viscosities may be lower and provide the same effect. For example, the viscosity during dispense may be less than 500 Pa-s and after dispense may be greater than 500 Pa-s. Other suitable material may be used. Dispenser302can be operated manually or by automated equipment programmed to dispense a predetermined amount of adhesive1002,1004in each cavity208,210. Note that the volume of each cavity208,210may be different, or two or more cavities208,210may have the same volume that is different from the volume of one or more other cavities208,210.

Referring toFIGS. 8 and 11,FIG. 11illustrates a cross-sectional view of an embodiment of a three-dimensional package900during a subsequent stage of manufacture according to process808of method800ofFIG. 8. Process808includes placing components406,408such as integrated circuit die for processing logic, memory, and/or other digital and analog circuitry, discrete components such as resistors, capacitors, and inductors, as well as discrete semiconductor devices such as transistors and diodes. Components406,408can be placed using an automated component placement system (also referred to as a “pick and place” machine) with a nozzle402that is configured to grasp a component406,408from a holding area, and release the component406,408in a specified cavity208,210(FIG. 10) where adhesive1004,1002has already been deposited.

Nozzle402can have side extensions404that are wider than cavities208,210. As nozzle402is lowered, side extensions404prevent the top surface of components406,408from being placed lower than the surrounding top surface of substrate202, since side extensions404meet the top surface of substrate202. The top surface of components406,408are typically held against the bottom surface of nozzle402with a vacuum force during movement and placement. Once placed, the vacuum is removed and components406,408remain in place due to the relatively high viscosity of adhesive1002,1004. Once adhesive1002,1004cures, components406,408are immovably positioned so that the upper surface of substrate202remains even with the upper surface of components406,408to create a flat surface on which the interconnection layers can be formed using various known technologies, e.g. build up or lamination processes.

Referring toFIGS. 8 and 12,FIG. 12illustrates a cross-sectional view of an embodiment of package900during a subsequent stage of manufacture according to process810of method800ofFIG. 8. Once additional adhesive504cures, process810includes forming interconnect layer600over the top of substrate202, components406,408, and adhesive504. Even though components406,408have different thicknesses, the level surface of package900that results from embedding components at different levels in viscous adhesive1002,1004allows interconnect layer600to be formed using standard processes, alleviating problems associated with having components406,408at different heights.

Interconnect layer600can include one or more layers of dielectric material602with vias604,606,608filled with conductive material between contacts610,612,616on the upper surface of interconnect layer600and contacts218,220,222on the upper surface of substrate202. Additional vias618,620can be formed between contacts622,624on component406and contacts626,628on the top surface of interconnect layer600. Although not shown, other interconnects including vias and contacts can be included for component408as well as other components in a package and contacts on substrate202. Additional layers of dielectric material with vias formed between contacts can also be included as part of package900. A solder mask layer (not shown) can be formed over contacts610,612,616,626to define solder ball contact area. The interconnection layer600can be formed using various known technologies e.g. build up or lamination processes.

Once interconnect layer600is formed, solder balls630,632,634,636can be formed on respective contacts610,612,626,636to allow package to be attached to another substrate such as a printed circuit board or other suitable device. After solder balls630-636are formed, package900can be singulated to separate package900from other packages (not shown) that can include similar or different components as package900. Tape204can be removed before or after package900is singulated.

Referring toFIGS. 1 and 13,FIG. 13illustrates a cross-sectional view of an embodiment of three-dimensional package900during a subsequent stage of manufacture according to process812of method800ofFIG. 8. Process812includes adding package700and surface mount device (SMD)706to package900. Package700is attached to contacts228,226with solder balls702,703. SMD706is attached to contact224with solder704. In other embodiments, additional packages and components can be added to package900, whether being attached to contacts on package900, or contacts (not shown) on package700.

By now it should be appreciated that packages200,900, and methods100,800have been disclosed that use automated component placement equipment such as a pick and place machine and viscous adhesive in cavities of substrate202to manufacture three-dimensional systems in package. Components406,408can have different thicknesses but are positioned so that the top surface of each component406,408is coplanar with the top surface of substrate202to simplify subsequent buildup of interconnect layer600. An active side of a die used for component406in the embodiments disclosed is placed face up in cavity208, which also simplifies connecting contacts622,624on component406to interconnect layer600. In addition, no chemical-mechanical polishing or planarizing process is required to achieve a level or planar surface at the top of substrate200, as shown inFIGS. 6 and 12.

In some embodiments, a method for making a packaged semiconductor device (200,900) includes dispensing a first adhesive (306,304,1002, or1004) into a first cavity (208or210) of a substrate (202) having a first major surface and a second major surface. The first cavity extends into the substrate from the second major surface. The method further includes placing a first component (406or408) having a thickness less than a thickness of the substrate into the first cavity such that the first adhesive physically contacts a first major surface of the first component and at least partially fills a gap between sidewalls of the first component and sidewalls of the first cavity. After placing the first component, a second major surface of the first component is coplanar with the second major surface of the substrate.

In another aspect, the method can further comprise, after placing the first component into the first cavity, dispensing a second adhesive (504) over the first adhesive to fill a remaining gap between the sidewalls of the first component and the sidewalls of the first cavity such that a surface of the second adhesive is coplanar with the second major surface of the substrate.

In another aspect, placing the first component is performed using a pick and place tool (402,404).

In another aspect, placing the first component can comprise: using a nozzle (404) of the pick and place tool to grasp the first component; and lowering the nozzle to place the first component into the first cavity, wherein the nozzle prevents the second major surface of the first component being placed lower than the second major surface of the substrate.

In another aspect, the method can further comprise, prior to dispensing the first adhesive into the first cavity, placing the first major surface of the substrate onto a carrier (204).

In another aspect, the first cavity can extend from the second major surface of the substrate to the first major surface of the substrate.

In another aspect, the substrate can include through substrate vias (216) which extend from the second major surface to the first major surface of the substrate.

In another aspect, dispensing the first adhesive can comprise dispensing the first adhesive into a second cavity (210) of the substrate, and the method can further comprise placing a second component (408) having a thickness less than the thickness of the substrate into the second cavity such that the first adhesive physically contacts a first major surface of the second component and at least partially fills a gap between sidewalls of the second component and sidewalls of the second cavity, wherein, after placing the second component, a second major surface of the second component is coplanar with the second major surface of the first component and the second major surface of the substrate.

In another aspect, the method can further comprise, after placing the first and second components, dispensing a second adhesive (504) over the first adhesive in the first cavity to fill a remaining gap between the sidewalls of the first component and the sidewalls of the first cavity and over the first adhesive in the second cavity to fill a remaining gap between the sidewalls of the second component and the sidewalls of the second cavity such that a surface of the second adhesive in the first and second cavities is coplanar with the second major surface of the substrate.

In another aspect, the thickness of the first component can be different from the thickness of the second component.

In another aspect, an active surface of the first component can be at the second major surface of the first component, the method can further comprise forming an interconnect layer (600) on the second major surface of the substrate and second major surface of the first component.

In another aspect, the method can further comprise singulating (110,810) the substrate to form a singulated package having the first component; and attaching a semiconductor device to the first major surface of the substrate of the singulated package, wherein the semiconductor device is one of a packaged device (700) or a surface mount device (706).

In other embodiments, a method for making a packaged semiconductor device, can comprise dispensing a first adhesive (306) into a first cavity (208) and a second cavity (210) of a substrate (202) having a first major surface and a second major surface. The first and second cavity can each extend into the substrate from the second major surface of the substrate. A first component (406) having a thickness less than a thickness of the substrate can be placed into the first cavity such that the first adhesive in the first cavity physically contacts a first major surface of the first component and at least partially fills a gap between sidewalls of the first component and sidewalls of the first cavity. After placing the first component, a second major surface of the first component is coplanar with the second major surface of the substrate. A second component (408) having a thickness less than the thickness of the substrate can be placed into the second cavity such that the first adhesive in the second cavity physically contacts a first major surface of the second component and at least partially fills a gap between sidewalls of the second component and sidewalls of the second cavity. After placing the second component, a second major surface of the second component is coplanar with the second major surface of the substrate.

In another aspect, an active surface of the first component can be at the second major surface of the first component and an active surface of the second component is at the second major surface of the second component. The method can further comprise forming an interconnect layer (600) on the second major surface of the substrate, second major surface of the first component, and second major surface of the second component.

In another aspect, the method can further comprise after placing the first component into the first cavity and the second component in the second cavity, dispensing a second adhesive (504) over the first adhesive in the first cavity to fill a remaining gap between the sidewalls of the first component and the sidewalls of the first cavity and over the first adhesive in the second cavity to fill a remaining gap between the sidewalls of the second component and the sidewalls of the second cavity such that a surface of the second adhesive in the first and second cavities is coplanar with the second major surface of the substrate.

In another aspect, the method can further comprise singulating (110,810) the substrate to form a singulated package having the first and second components; and attaching a semiconductor device to the first major surface of the substrate of the singulated package, wherein the semiconductor device is one of a packaged device or a surface mount device.

In another aspect, placing the first component and placing the second component can be performed using a pick and place tool (402,404).

In still other embodiments, a system in package can comprise a substrate (202) having a first thickness; a first component (406) in a first cavity of the substrate, the first component having a second thickness less than the first thickness; and a second component (408) in a second cavity of the substrate. The second component can have a third thickness less than the first thickness and different from the second thickness. An active surface of the first component is at a first major surface of the first component. An active surface of the second component is at a first major surface of the second component. The first major surfaces of the first and second components are coplanar with a first major surface of the substrate. An epoxy (306,504) is on a second major surface of the first component and surrounding sidewalls of the first component in the first cavity and on a second major surface of the second component and surrounding sidewalls of the second component in the second cavity. An interconnect layer (600) is on the first major surfaces of the first component, second component, and substrate.

In another aspect, the system can further comprise a plurality of conductive balls (636) on contacts of the interconnect layer. The interconnect layer is between the conductive balls and the substrate.

In another aspect, the substrate can comprise a conductive through substrate via (216). The system can further comprise a packaged device (700) attached to a second major surface of the substrate and electrically connected to the conductive through substrate via.

Because the apparatus implementing the present disclosure is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present disclosure and in order not to obfuscate or distract from the teachings of the present disclosure.