Systems and methods for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing. A stimulus component applies a plurality of different stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the applied plurality of different stimuli. An analysis component determines a logic state of each memory cell of the plurality of memory cells as a function of the sensed characteristic of each memory cell of the plurality of memory cells.

TECHNICAL FIELD

This disclosure relates generally to systems for sensing memory devices and in particular, but not exclusively, relates to reference-free sampled sensing of memory devices.

BACKGROUND

A wide variety of memory devices can be used to maintain and store data and instructions for various computers and similar systems, including non-volatile memory devices that do not require power to retain information (e.g., EPROM, EEPROM, and Flash memory).

Memory devices contain memory cells, which store information in the form of binary bit(s) (e.g., logic state “0”, “1”, “00”, “01”, “10”, or “11”). Conventional technology senses the logic state of memory cells utilizing fixed and/or dynamic tracking references, comparing a sensed current/voltage with a fixed and/or dynamic tracking reference current/voltage. For example, if the sensed current drawn by a memory cell exceeds a reference current, the memory cell's logic state is evaluated as a logic 1; otherwise, the memory cell's logic state is evaluated as a logic 0.

One concern with conventional memory sensing technology is that fixed references may not correctly evaluate the logic state of a memory cell when one or more characteristics of the memory cell (e.g., threshold voltage, drain current) change and/or degrade over time. For example, if at the beginning of life of a memory cell, the current sensed during a read operation of the memory cell exceeds a fixed reference current, the logic state of the memory cell is evaluated as a logic 1. However, if characteristics of the memory cell change after a period of time, causing current sensed during a read operation of the memory cell to be below the fixed reference current, the logic state of the memory cell is evaluated as a logic 0—data stored in the memory cell cannot reliably be determined. Therefore, the usable life of a memory cell terminates when a fixed reference cannot account for changes in the memory cell's characteristics.

Another concern with conventional memory sensing technology is that dynamic tracking references may not correctly evaluate the logic state of a memory cell when one or more characteristics of the memory cell shift over time—a memory cell's characteristics can change inconsistently compared to characteristics of a dynamic tracking reference. Therefore, when a fixed reference cannot account for changes in the memory cell's characteristics, data stored in the memory cell cannot reliably be determined. Therefore, the usable life of a memory cell terminates when a fixed reference cannot account for changes in the memory cell's characteristics.

It is therefore desirable to have systems and methods that can extend the usable lifetime of memory cells by avoiding limitations of conventional sensing techniques.

SUMMARY

The claimed subject matter relates to systems and methods for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing. Conventional sensing techniques are limited since these techniques may not fully account for changes in a memory cell's characteristics. Compared to traditional sensing methods, the novel reference-free sampled sensing systems and methods of the claimed subject matter increase the usable lifetime of memory cells by determining a memory cell's logic state from sampled data.

The following presents a simplified summary of the innovation in order to provide a basic understanding of some aspects described herein. This summary is not an extensive overview of the disclosed subject matter. It is intended to neither identify key or critical elements of the disclosed subject matter nor delineate the scope of the subject innovation. Its sole purpose is to present some concepts of the disclosed subject matter in a simplified form as a prelude to the more detailed description that is presented later.

The subject invention provides systems and methods for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing. In accordance with one aspect of the disclosed subject matter, a stimulus component can apply a plurality of different stimuli to a plurality of memory cells of a memory device. A sense component can sense a characteristic of each memory cell of the plurality of memory cells as a function of the applied plurality of different stimuli. An analysis component can determine a logic state of each memory cell of the plurality of memory cells as a function of the sensed characteristic of each memory cell of the plurality of memory cells.

In accordance with another aspect of the disclosed subject matter, a data store component can store the sensed characteristic of each memory cell of the plurality of memory cells. The analysis component can determine the logic state of each memory cell of the plurality of memory cells as a function of the stored sensed characteristic of each memory cell of the plurality of memory cells. In accordance with yet another aspect of the disclosed subject matter, the stimulus component comprises at least one of applying a bit-line voltage to the plurality of memory cells, applying a word-line voltage to the plurality of memory cells, pre-charging an output of one or more memory cells of the plurality of memory cells to a reference voltage, or applying a current to bit-lines of the plurality of memory cells.

In accordance with one aspect of the disclosed subject matter, the sense component comprises at least one of sensing the rate of current discharge of an output of one or more memory cells of the plurality of memory cells, sensing a voltage of an output of one or more memory cells of the plurality of memory cells, or sensing a current of an output of one or more memory cells of the plurality of memory cells. The analysis component comprises at least one of determining the logic state of each memory cell of the plurality of memory cells by comparing the sensed characteristic of each memory cell of the plurality of memory cells with one or more numbers, each of the one or more numbers representing a number of memory cells of the plurality of memory cells known to be programmed to a particular logic state; or determining the logic state of each memory cell of the plurality of memory cells by associating the logic state with a minimum number of change of sensed logic states as a function of the applied plurality of different stimuli.

In accordance with another aspect of the disclosed subject matter, the sense component comprises one or more sense amplifiers, the one or more sense amplifiers comprising at least one of a resistor, a transistor, a pass gate, a latch, an operational amplifier, a comparator, or a window comparator. An output of each memory cell of the plurality of memory cells is coupled to a first input of one of the one or more sense amplifiers. A fixed comparison voltage is coupled to a second input of the one of the one or more sense amplifiers. The sense component senses the characteristic of each memory cell of the plurality of memory cells as a function of an output of at least one of the one or more sense amplifiers.

In accordance with yet another aspect of the disclosed subject matter, an output of the one or more sense amplifiers is coupled to a tri-state logic device, an output of each tri-state logic device is coupled to a latch, and an output of each latch is coupled to a pass gate. The sense component can sense the characteristic of each memory cell of the plurality of memory cells as a function of an output of at least one pass gate. In accordance with one aspect of the disclosed subject matter, an output of the one or more sense amplifiers is coupled to a first input of one or more other sense amplifiers. A target voltage is coupled to a second input of the one or more other sense amplifiers and is associated with a number of memory cells expected to be sensed at a logic state. The sense component can sense the characteristic of each memory cell of the plurality of memory cells as a function of the output of the one or more other sense amplifiers.

DETAILED DESCRIPTION

Embodiments of systems and methods that extend the usable lifetime of memory cells by utilizing reference-free sampled sensing are described herein.

The subject invention provides systems and methods that extend the usable lifetime of memory cells by utilizing reference-free sampled sensing. Embodiments of the invention include techniques for determining a memory cell's logic state from sampled data, avoiding limitations of fixed and dynamic tracking sensing.FIG. 1is a demonstrative system100for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing, in accordance with an embodiment of the invention. System100and the systems and processes explained below may constitute machine-executable instructions embodied within a machine (e.g., computer) readable medium, which when executed by a machine will cause the machine to perform the operations described. Additionally, the systems and processes may be embodied within hardware, such as an application specific integrated circuit (“ASIC”) or the like. The order in which some or all of the process blocks appear in each process should not be deemed limiting. Rather, it should be understood by a person of ordinary skill in the art having the benefit of the instant disclosure that some of the process blocks may be executed in a variety of orders not illustrated.

In system100, a stimulus component105can apply a plurality of different stimuli to a plurality of memory cells110. A sense component115can sense a characteristic of each memory cell of the plurality of memory cells110as a function of the applied plurality of different stimuli. An analysis component120can determine a logic state of each memory cell of the plurality of memory cells110based on the characteristic of each memory cell sensed as a function of the applied different stimuli. The subject invention avoids limitations of sensing memory cells utilizing fixed and dynamic tracking references—it extends the usable lifetime of memory cells by determining a memory cell's logic state as a function of the sensed characteristic of each memory cell of the plurality of memory cells110.

In accordance with one embodiment, each memory cell of the plurality of memory cells110can be a non-volatile memory that is at least one of a flash memory (e.g., single-bit flash memory, multi-bit flash memory), read only memory (“ROM”), programmable ROM (“PROM”), erasable PROM (“EPROM”), electronically erasable PROM (“EEPROM”), or a combination thereof. In one embodiment, stimulus component105can apply at least one of a bit-line voltage to the plurality of memory cells110, a word-line voltage to the plurality of memory cells110, or pre-charge an output of one or more memory cells of the plurality of memory cells110to a reference voltage. Further, the sensed characteristic of each memory cell of the plurality of memory cells110comprises at least one of drain current, threshold voltage, gain, or logic state. However, it should be appreciated that stimulus component105can apply any stimulus to each memory cell of the plurality of memory cells110, and sense component115can sense any characteristic of each memory cell of the plurality of memory cells110.

In system100, analysis component120can determine the logic state of each memory cell of the plurality of memory cells110by comparing the sensed characteristic of each memory cell of the plurality of memory cells110with one or more numbers, each of the one or more numbers representing a number of memory cells of the plurality of memory cells110known to be programmed to a particular logic state. Thus, although logic states of particular memory cells are unknown, the subject invention can determine the logic state of each memory cell when a total number of bits in a particular state is known. Analysis component120can also determine the logic state of each memory cell of the plurality of memory cells110by associating the logic state with a minimum number in change of sensed logic states as a function of the applied plurality of different stimuli. Unlike conventional sensing systems and/or methods, which can decrease the usable lifetime of memory cells and suffer from issues concerning lack of sensitivity of static and dynamic tracking references to changes in memory cell characteristics, the subject invention provides systems and methods that extend the usable lifetime of memory cells by determining a memory cell's logic state from sampled data.

FIG. 2is a demonstrative data store based system200for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing, in accordance with an embodiment of the invention. Data store system200can contain data store component210, which can store a sensed characteristic of each memory cell of the plurality of memory cells110. In one embodiment, data store component comprises a memory location. In other embodiments, data store component comprises a latch. In yet other embodiments, data store component can comprise a capacitor, the capacitor storing data in the form of retained charge. However, it should be appreciated that data store component210can comprise any type of device or function that is capable of retaining a state of a sensed characteristic of each memory cell of the plurality of memory cells110. Analysis component120can determine the logic state of each memory cell based on the characteristic of each memory cell stored as a function of the applied different stimuli.

In accordance with an embodiment of the invention demonstrated byFIG. 3, an artificial intelligence based system300can extend the usable lifetime of memory cells by utilizing reference-free sampled sensing. Artificial intelligence based system300can contain an artificial intelligence component310, in which data store component210can store a characteristic of each memory cell of the plurality of memory cells110, the characteristic sensed by sense component115as a function of a plurality of different stimuli applied by stimulus component105. Analysis component120can automatically determine the logic state of each memory cell of the plurality of memory cells110as a function of the characteristics stored by data store component210. In one embodiment of artificial intelligence based system300, artificial intelligence component310is a closed-loop feedback system that automatically determines the logic state of each memory cell of the plurality of memory cells110based on values sensed by sense component115and stored by data store component210.

FIG. 4is a schematic block diagram illustrating a sense circuit400, in accordance with an embodiment of the invention. An output of memory cell410is coupled to a first input415of sense amplifier405. Fixed comparison voltage420is coupled to a second input425of sense amplifier405. Further, an output of memory cell470is coupled to a first input475of sense amplifier465. Fixed comparison voltage480is coupled to a second input485of sense amplifier465. In response to stimulus component105applying a different stimulus to memory cells410and470, sense component115can sense the logic state of memory cell410as a function of sense amplifier output435, and sense component115can sense the logic state of memory cell470as a function of sense amplifier output495.

In accordance with one embodiment, sense component115can sense a rate of current discharge of outputs415and475. In accordance with another embodiment, sense component115can sense a voltage or current of outputs415and475. In one embodiment, sense amplifiers405and465are resistors. In other embodiments, sense amplifiers405and465are transistors. In yet another embodiment, sense amplifiers405and465are comparators. However, it should be appreciated that sense amplifiers405and465can comprise any type of device or function that is capable of sensing, amplifying, and/or translating a sensed characteristic of each memory cell of the plurality of memory cells110.

FIG. 5is a flow chart illustrating a process500for determining a logic state of each memory cell of the plurality of memory cells, in accordance with an embodiment of the invention. At505, stimulus component105can apply a different stimulus to each memory cell of the plurality of memory cells110. In a process block510, sense component115can sense a characteristic of each memory cell of the plurality of memory cells110. At515, data store component210can store the sensed characteristic of each memory cell of the plurality of memory cells110. At a decision block520, it can be decided whether to continue applying a different stimulus to each memory cell of the plurality of memory cells110. If process500does not continue applying different stimuli, process500continues to process block530, in which analysis component120can determine the logic state of each memory cell based on the characteristic of each memory cell stored as a function of the applied different stimuli.

FIG. 6is a schematic block diagram illustrating a sense circuit600with latches650and690, in accordance with an embodiment of the invention. Output635of sense amplifier605is coupled to tri-state logic device640. Output686of sense amplifier665is coupled to tri-state logic device688. It should be appreciated that tri-state logic devices640and688can be any logic devices that perform a hi-impedance function (e.g., tri-state inverter). Output645of tri-state logic device640is coupled to latch650. Output689of tri-state logic device688is coupled to latch690. It should be appreciated that latches650and690can be any devices or functions that can store data.

In response to stimulus component105applying a different stimulus to memory cells610and670, data store component220can store the logic states of memory cells610and670by enabling tri-state logic devices640and688(at641and699) at a particular time (i.e., as a function of the applied different stimuli). In addition, analysis component120can determine the logic state of each memory cell of the plurality of memory cells110as a function of the logic states stored in latches650and690, the logic states stored as a function of the applied different stimuli. Analysis component120can enable pass gate660at661to access a logic state stored in latch650. Analysis component120can enable pass gate693at695to access a logic state stored in latch690. In the embodiment illustrated byFIG. 6, the output of pass gate660is coupled to the output of pass gate693. In other embodiments, an output of a pass gate is not coupled to an output of other pass gates.

FIG. 7is a flow chart illustrating a process700for determining a logic state of each memory cell as a function of an output of a pass gate, in accordance with an embodiment of the invention. At705, stimulus component105can apply a bit-line voltage to the plurality of memory cells110. In a process block710, sense component115can sense a logic state of each memory cell of the plurality of memory cells110. At715, data store component210can store the logic state of each memory cell of the plurality of memory cells110. At a decision block720, it can be decided whether to continue to apply a different bit-line voltage to the plurality of memory cells110. If process700does not apply a different bit-line voltage, process700continues to730, in which analysis component120can determine the logic state of each memory cell based on the logic state of each memory cell stored as a function of the applied different bit-line voltages.

FIG. 8is a schematic block diagram illustrating a sense circuit800sensing a summation of logic states of more than one memory cell, in accordance with an embodiment of the invention. At860, outputs of sense amplifiers805and835are coupled to a first input of sense amplifier880. Target voltage870is coupled to a second input of sense amplifier880at875. In one embodiment, target voltage870is associated with a number of memory cells expected to be sensed at a logic state. In response to stimulus component105applying a different stimulus to memory cells810and840, sense component115can sense the sum of the logic states of memory cells810and840as a function of sense amplifier output885.

FIG. 9is a flow chart illustrating a process900for determining a logic state of each memory cell as a function of sensing a summation of a characteristic of more than one memory cell, in accordance with an embodiment of the invention. At905, stimulus component105can set a target voltage associated with a number of memory cells expected to be sensed at a logic state. At907, stimulus component105can apply a bit-line voltage to the plurality of memory cells110. In a process block910, sense component115can sense a logic state of each memory cell of the plurality of memory cells110at the output of a sense amplifier, the sense amplifier performing a summation of a characteristic of more than one memory cell. At915, data store component210can store the logic state of each memory cell of the plurality of memory cells110. At a decision block920, it can be decided whether to continue to apply a different bit-line voltage to the plurality of memory cells110. If process900does not apply a different bit-line voltage, process900continues to930, in which analysis component120can determine the logic state of each memory cell based on the logic state of each memory cell stored as a function of the applied different stimuli.

FIG. 10is a more detailed demonstrative system1000for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing, in accordance with an embodiment of the invention. System control1005can receive input from sense logic1030and can control stimulus output logic1010. System control1005may include a computer that contains a central processing unit for making computations and performing various program and data transfers, and may also contain memory for program and data storage. Stimulus output logic1010can receive information from system control1005, and may include decode logic that decodes the information received from system control1005to control stimulus output circuit1015. Stimulus output circuit1015can receive control logic from stimulus output logic1010and can translate the control logic into at least one of voltage or current.

A memory cell of memory cells1020may be a non-volatile memory that is at least one of flash memory, multi-bit flash memory, read only memory (ROM), programmable ROM (PROM), erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), or a combination thereof. Sense circuit1025can sense at least one of drain current, threshold voltage, gain, or logic state. Also, sense circuit1025can transmit signals to sense logic1030. Sense circuit1025may include multiple static references, comparators, window comparators, sense amplifiers, and any other elements that comprise sense circuits. Sense logic1030can receive signals sent by sense circuit1025and can translate the signals into logic that can be received by system controller1005. Sense logic1030may translate the signals using encoding logic. It should be understood by a person of ordinary skill in the art having the benefit of the instant disclosure that system1000may comprise any hardware and/or software necessary to perform the above illustrated embodiments of the invention.

Inference can also refer to techniques employed for composing higher-level events from a set of events and/or data. Such inference results in the construction of new events or actions from a set of observed events and/or stored event data, whether or not the events are correlated in close temporal proximity, and whether the events and data come from one or several event and data sources. Various classification schemes and/or systems (e.g., support vector machines, neural networks, expert systems, Bayesian belief networks, fuzzy logic, data fusion engines . . . ) can be employed in connection with performing automatic and/or inferred action in connection with the disclosed subject matter.

Furthermore, the disclosed subject matter may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof to control a computer to implement the disclosed subject matter. The term “article of manufacture” as used herein is intended to encompass a computer program accessible from any computer-readable device, carrier, or media. For example, computer readable media can include but are not limited to magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips . . . ), optical disks (e.g., CD, DVD . . . ), smart cards, and flash memory devices (e.g., card, stick, key drive . . . ).

Further, it should be appreciated that a carrier wave can be employed to carry computer-readable electronic data such as those used in transmitting and receiving electronic mail or in accessing a network such as the Internet or a local area network (LAN). Of course, those skilled in the art will recognize many modifications may be made to this configuration without departing from the scope or spirit of the disclosed subject matter. Moreover, the word “exemplary” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs.

In order to provide a context for the various aspects of the disclosed subject matter,FIGS. 11 and 12, as well as the following discussion, are intended to provide a brief, general description of a suitable environment in which the various aspects of the disclosed subject matter may be implemented. While the subject matter has been described above in the general context of computer-executable instructions of a computer program that runs on a computer and/or computers, those skilled in the art will recognize that the subject innovation also may be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and/or implement particular abstract data types.

Moreover, those skilled in the art will appreciate that the inventive systems may be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, mini-computing devices, mainframe computers, as well as personal computers, hand-held computing devices (e.g. PDA, phone, watch), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all aspects of the claimed innovation can be practiced on stand-alone computers. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

With reference toFIG. 11, a suitable environment1100for implementing various aspects of the claimed subject matter includes a computer1112. The computer1112includes a processing unit1114, a system memory1116, and a system bus1118. The system bus1118couples system components including, but not limited to, the system memory1116to the processing unit1114. The processing unit1114can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit1114.

The system memory1116includes volatile memory1120and nonvolatile memory1122. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer1112, such as during start-up, is stored in nonvolatile memory1122. By way of illustration, and not limitation, nonvolatile memory1122can include ROM, PROM, EPROM, EEPROM, or flash memory. Volatile memory1120includes RAM, which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as SRAM, dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM).

It is to be appreciated thatFIG. 11describes software that acts as an intermediary between users and the basic computer resources described in the suitable operating environment1100. Such software includes an operating system1128. Operating system1128, which can be stored on disk storage1124, acts to control and allocate resources of the computer system1112. System applications1130take advantage of the management of resources by operating system1128through program modules1132and program data1134stored either in system memory1116or on disk storage1124. It is to be appreciated that the disclosed subject matter can be implemented with various operating systems or combinations of operating systems.

A user enters commands or information into the computer1112through input device(s)1136. Input devices1136include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit1114through the system bus1118via interface port(s)1138. Interface port(s)1138include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device(s)1140use some of the same type of ports as input device(s)1136.

Thus, for example, a USB port may be used to provide input to computer1112, and to output information from computer1112to an output device1140. Output adapter1142is provided to illustrate that there are some output devices1140like monitors, speakers, and printers, among other output devices1140, which require special adapters. The output adapters1142include, by way of illustration and not limitation, video and sound cards that provide a means of connection between the output device1140and the system bus1118. It should be noted that other devices and/or systems of devices provide both input and output capabilities such as remote computer(s)1144.

Computer1112can operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s)1144. The remote computer(s)1144can be a personal computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device or other common network node and the like, and typically includes many or all of the elements described relative to computer1112.

For purposes of brevity, only a memory storage device1146is illustrated with remote computer(s)1144. Remote computer(s)1144is logically connected to computer1112through a network interface1148and then physically connected via communication connection1150. Network interface1148encompasses wire and/or wireless communication networks such as local-area networks (LAN) and wide-area networks (WAN). LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring and the like. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL).

Communication connection(s)1150refer(s) to the hardware/software employed to connect the network interface1148to the bus1118. While communication connection1150is shown for illustrative clarity inside computer1112, it can also be external to computer1112. The hardware/software necessary for connection to the network interface1148includes, for exemplary purposes only, internal and external technologies such as, modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

FIG. 12is a schematic block diagram of a sample-computing environment1200with which the subject innovation can interact. The system1200includes one or more client(s)1210. The client(s)1210can be hardware and/or software (e.g., threads, processes, computing devices). The system1200also includes one or more server(s)1220. Thus, system1200can correspond to a two-tier client server model or a multi-tier model (e.g., client, middle tier server, data server), amongst other models. The server(s)1220can also be hardware and/or software (e.g., threads, processes, computing devices). The servers1220can house threads to perform transformations by employing the subject innovation, for example. One possible communication between a client1210and a server1220may be in the form of a data packet transmitted between two or more computer processes.

The system1200includes a communication framework1230that can be employed to facilitate communications between the client(s)1210and the server(s)1220. The client(s)1210are operatively connected to one or more client data store(s)1240that can be employed to store information local to the client(s)1210. Similarly, the server(s)1220are operatively connected to one or more server data store(s)1250that can be employed to store information local to the servers1220.