Fully molded bridge interposer and method of making the same

A semiconductor device may comprise a bridge die comprising copper studs. Copper posts may be disposed in a periphery of the bridge die. An encapsulant may be disposed on five sides of the bridge die, on sides of the copper studs, and on sides of the copper posts that leave ends of the copper studs and opposing first and second ends of the copper posts exposed from the encapsulant. A frontside build-up interconnect structure may be formed over the copper studs of the bridge die and coupled to second ends of the copper posts opposite the first ends of the copper posts. The frontside build-up interconnect structure comprising first pads at a first pitch within a footprint of the bridge die and second pads at a second pitch outside a footprint of the bridge die. The first pitch may be at least 1.5 times less than the second pitch.

TECHNICAL FIELD

This disclosure relates to a fully molded bridge interposer and methods of making the same.

BACKGROUND

Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, for example, light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, memories, analog to digital or digital to analog converters, power management and charged-coupled devices (CCDs), as well as microelectromechanical systems (MEMS) devices including digital micro-mirror devices (DMDs).

Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, storing information, and creating visual projections for displays. Semiconductor devices are found in many fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

A semiconductor device contains active and passive electrical structures. Active structures, including bipolar, complementary metal oxide semiconductors, and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.

Semiconductor devices are generally manufactured using two complex manufacturing processes, that is, front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of semiconductor die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. More recently, back-end manufacturing has been expanded to included emerging technology that allows multiple semiconductor die to be interconnected within a single package or device unit, thereby expanding the conventional definition of back-end technology. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly can refer to both a single semiconductor device and multiple semiconductor devices.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, can be produced more efficiently, have a smaller form factor, and may be less cumbersome when integrated within wearable electronics, portable handheld communication devices, such as phones, and in other applications. In other words, smaller semiconductor devices may have a smaller footprint, a reduced height, or both, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

SUMMARY

An opportunity exists for improved semiconductor manufacturing, packaging, and devices. Accordingly, in an aspect of the disclosure, a semiconductor device may comprise a molded bridge interposer, further comprising a bridge die comprising ultra-high density copper studs with a pitch of less than or equal to 60 μm. Copper posts may be disposed in a periphery of the bridge die and comprise a height greater than or equal to a height of the bridge die and the copper studs. An encapsulant may be disposed on five sides of the bridge die, on sides of the copper studs, and on sides of the copper posts that leave ends of the copper studs and opposing first and second ends of the copper posts exposed from the encapsulant. A backside build-up interconnect structure may be formed over a backside of the bridge die and coupled to first ends of the copper posts. A frontside build-up interconnect structure may be formed over the copper studs of the bridge die and coupled to second ends of the copper posts opposite the first ends of the copper posts. The frontside build-up interconnect structure may comprise ultra-high density pads within a footprint of the bridge die with a pitch less than 60 μm and high density pads with a pitch of greater than or equal to 60 μm outside a footprint of the bridge die. A first via layer of the frontside build-up interconnect structure comprises vias aligned to centers of the copper studs with an r2value greater than 0.5 relative to difference between an offset between a first side of the bridge die and a copper post adjacent the first side of the bridge die and a second offset between a second side of the bridge die opposite the first side of the bridge die and a copper post adjacent the second side of the bridge die for a lot of devices. A first component may comprise a system on chip (SOC) integrated circuit, memory, memory controller or high bandwidth memory (HBM) controller, voltage regulator, a serializer/deserializer (SERDES), or active semiconductor die. The first component may comprise ultra-high density interconnects coupled with a first portion of the ultra-high density pads within a footprint of the bridge die, and high density interconnects coupled with a first portion of the high density pads outside a footprint of the bridge die. A second component comprising a SOC integrated circuit, memory controller or HBM controller, voltage regulator, SERDES, or active semiconductor die. The second component comprising ultra-high density interconnects coupled with a second portion of the ultra-high density pads within a footprint of the bridge die, and high density interconnects coupled with a second portion of the high density pads outside a footprint of the bridge die.

Particular embodiments of the semiconductor device may further comprise a second bridge die disposed within the molded bridge interposer. The bridge die may further comprise the high density copper studs formed with a pitch of less than or equal 60 μm. The copper posts may be disposed in a periphery of the bridge die at a pitch of 250 μm or less. The molded bridge interposer is disposed over, and is coupled to, a package substrate, a printed circuit board (PCB), a multilayer ceramic capacitors (MLCC), or a passive device.

According to an aspect of the disclosure, a semiconductor device may comprise a bridge die comprising copper studs. Copper posts may be disposed in a periphery of the bridge die. An encapsulant may be disposed on five sides of the bridge die, on sides of the copper studs, and on sides of the copper posts that leave ends of the copper studs and opposing first and second ends of the copper posts exposed from the encapsulant. A frontside build-up interconnect structure may be formed over the copper studs of the bridge die and coupled to second ends of the copper posts opposite the first ends of the copper posts. The frontside build-up interconnect structure comprising first pads at a first pitch within a footprint of the bridge die and second pads at a second pitch outside a footprint of the bridge die.

In another aspect, particular embodiments of the semiconductor device may comprise a first component comprising a SOC integrated circuit, memory controller or HBM controller, voltage regulator, a SERDES, or active semiconductor die, the first component comprising, the first semiconductor device comprising high density interconnects coupled with a first portion of the high density pads, and low density interconnects coupled with a first portion of the low density pads. A second component comprising a SOC integrated circuit, memory controller or HBM controller, voltage regulator, a SERDES, or active semiconductor die, the second component comprising, the second semiconductor device comprising high density interconnects coupled with a second portion of the high density pads, and low density interconnects coupled with a second portion of the low density pads. The semiconductor device may further comprise a backside build-up interconnect structure formed over a backside of the bridge die and coupled to first ends of the copper posts. The first pitch may be less than or equal to 60 μm and the first pitch may be at least 1.5 times less than the second pitch.

The copper posts may comprise a height greater than or equal to a height of the bridge die and the copper studs. For a lot of devices, a first via layer of the frontside build-up interconnect structure may comprise vias aligned to centers of the copper studs with an r2value greater than 0.5 relative to difference between an offset between a first side of the bridge die and an copper post adjacent the first side of the bridge die and a second offset between a second side of the bridge die opposite the first side of the bridge die and a copper post adjacent the second side of the bridge die. The bridge die may be formed as an active device. The bridge die may be formed with conductive redistribution layers coupled to the copper studs of the bridge die.

According to an aspect of the disclosure, a method of making a semiconductor device may comprise providing a carrier, and disposing copper posts in a periphery of the bridge die. The method may include disposing a bridge die over the carrier, the bridge die comprising copper studs. The method may include forming an encapsulant disposed on five sides of the bridge die, on sides of the copper studs, and on sides of the copper posts that leave ends of the copper studs and opposing first and second ends of the copper posts exposed from the encapsulant. Together, the bridge die, copper posts, and encapsulant form a molded bridge interposer. The method may further comprise forming a frontside build-up interconnect structure over the copper studs of the bridge die and coupled to second ends of the copper posts opposite the first ends of the copper posts. The frontside build-up interconnect structure may comprise first pads at a first pitch within a footprint of the bridge die and second pads at a second pitch outside a footprint of the bridge die. The first pitch may be at least two times less than the second pitch.

In another aspect, particular embodiments of the method of making a semiconductor device may comprise removing at least a portion of the carrier and removing a portion of the encapsulant from over the copper posts and the copper studs. A pitch of the copper studs may be less than or equal to 60 μm, and the first pitch may be at least 1.5 times less than the second pitch. The method may further comprise forming a backside build-up interconnect structure formed over the temporary carrier before disposing the bridge die over the temporary carrier and over the backside build-up interconnect structure. The method may include coupling a first component comprising a SOC integrated circuit, memory controller or HBM controller, voltage regulator, a SERDES, or active semiconductor die to the molded bridge interposer. The first component may comprise interconnects coupled with a first portion of the first pads, and lower density interconnects coupled with a first portion of the second pads. The method may include coupling a second component comprising a SOC integrated circuit, memory controller or HBM controller, voltage regulator, a SERDES, or active semiconductor die. The second component may comprise interconnects coupled with a second portion of the first pads, and lower density interconnects coupled with a second portion of the second pads. For a lot of devices, a first via layer of the frontside build-up interconnect structure may comprise vias aligned to centers of the copper studs with an r2value greater than 0.5 relative to difference between an offset between a first side of the bridge die and an copper post adjacent the first side of the bridge die and a second offset between a second side of the bridge die opposite the first side of the bridge die and a copper post adjacent the second side of the bridge die.

The foregoing and other aspects, features, and advantages will be apparent to those of ordinary skill in the art from the specification, drawings, and the claims.

DETAILED DESCRIPTION

This disclosure relates to fully molded semiconductor structures, devices, and packages, and more particularly to a fully molded bridge interposer. In some instances, the fully molded semiconductor structures may comprise routing for semiconductor devices comprising different pitches, such as high density and ultra-high density as described more fully herein.

The fully molded semiconductor structures or bridge interposer (and method for making and using the same) may comprise, or provide: (i) a simplified supply chain, (ii) when compared with a conventional interposer—removing a need for an expensive large silicon die with through silicon vias (TSVs), which can be very large die that are very expensive because (at least in part) because of TSV technology, (iii) when compared with Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology, providing the advantage of no need for specialized substate technology—a enabling or facilitating the use of a low-cost substrate, (iv) improved electrical performance from using plated Cu Post vs TSVs, (v) have available ultra-high density connections (of or about a 10 μm area array bond pad pitch) where bridge die are embedded, high density (of or about a 20 μm area array bond pad pitch) elsewhere, and (vi) high density connections between bridge die and other devices or packages.

At least some of the above advantages are available at least in part by using unit specific patterning (such as patterning (custom lithography) and build up interconnect structures such as a frontside build-up interconnect structure, which is also known under the trademark “Adaptive Patterning”) with respect the bridge die. Unit specific patterning: (i) allows to use high-speed chip attach for bridge die and AP will ensure alignment for high density interconnects between M-Series interposer and attached devices, (ii) aligns via to Cu Studs allowing largest contact vias with smallest studs (fine pitch), (iii) with respect to an interposer makes the molded bridge interposer including a frontside build-up interconnect structure much cheaper that a giant interposer die, (iv) with respect to EMIB, vias can be large compared to stud size and capture pad size, lithography defined vias (not laser drilled), (v) allows connections between devices inside the molded bridge interposer with unit specific patterning or routing to compensate for die shift (including bridge die shift) between embedded devices, which may include memory controllers, voltage regulators, SERDES, etc., and (vi) make embedding active devices more useful.

This disclosure, its aspects and implementations, are not limited to the specific package types, material types, or other system component examples, or methods disclosed herein. Many additional components, manufacturing and assembly procedures known in the art consistent with semiconductor manufacture and packaging are contemplated for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any components, models, types, materials, versions, quantities, and/or the like as is known in the art for such systems and implementing components, consistent with the intended operation.

Where the following examples, embodiments and implementations reference examples, it should be understood by those of ordinary skill in the art that other manufacturing devices and examples could be intermixed or substituted with those provided. In places where the description above refers to particular embodiments, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these embodiments and implementations may be applied to other technologies as well. Accordingly, the disclosed subject matter is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the disclosure and the knowledge of one of ordinary skill in the art.

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. In one embodiment, the portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. In another embodiment, the portion of the photoresist pattern not subjected to light, the negative photoresist, is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, such as by a stripping process, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

Patterning is the basic operation by which portions of the photoresist material are partially removed, so as to provide a pattern or electroplating template for the subsequent formation of structures, such as patterning redistribution layers (RDLs), under bump mentalization (UBM), copper posts, vertical interconnects, or other desirable structures. Portions of the semiconductor wafer can be removed using photolithography, photomasking, masking, oxide or metal removal, photography and stenciling, and microlithography. Photolithography includes forming a pattern in reticles or a photomask and transferring the pattern into the surface layers of the semiconductor wafer. Photolithography forms the horizontal dimensions of active and passive components on the surface of the semiconductor wafer in a two-step process. First, the pattern on the reticle, masks, or direct write imaging design file are transferred into a layer of photoresist. Photoresist is a light-sensitive material that undergoes changes in structure and properties when exposed to light. The process of changing the structure and properties of the photoresist occurs as either negative-acting photoresist or positive-acting photoresist. Second, the photoresist layer is transferred into the wafer surface. The transfer occurs when etching removes or electroplating adds the portion of the top layers of semiconductor wafer not covered by the photoresist. The chemistry of photoresists is such that the photoresist remains substantially intact and resists removal by chemical etching solutions while the portion of the top layers of the semiconductor wafer not covered by the photoresist is removed by etching or a layer is added by electroplating. The process of forming, exposing, and removing the photoresist, as well as the process of removing or adding a portion of the semiconductor wafer can be modified according to the particular resist used and the desired results. Negative or positive tones resist can be designed for solvent or base develop solutions.

In negative-acting photoresists, photoresist is exposed to light and is changed from a soluble condition to an insoluble condition in a process known as polymerization. In polymerization, unpolymerized material is exposed to a light or energy source and polymers form a cross-linked material that is etch-resistant. In most negative resists, the polymers are polyisopremes. Removing the soluble portions (i.e. the portions not exposed to light) with chemical solvents or base developers leaves a hole in the resist layer that corresponds to the opaque pattern on the reticle. A mask whose pattern exists in the opaque regions is called a clear-field mask.

In positive-acting photoresists, photoresist is exposed to light and is changed from relatively nonsoluble condition to much more soluble condition in a process known as photosolubilization. In photosolubilization, the relatively insoluble resist is exposed to the proper light energy and is converted to a more soluble state. The photosolubilized part of the resist can be removed by a solvent or a base in the development process. The basic positive photoresist polymer is the phenol-formaldehyde polymer, also called the phenol-formaldehyde novolak resin. Removing the soluble portions (i.e. the portions exposed to light) with chemical solvents or base developers leaves a hole in the resist layer that corresponds to the transparent pattern on the reticle. A mask whose pattern exists in the transparent regions is called a dark-field mask.

After removal of the top portion of the semiconductor wafer not covered by the photoresist, the remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface can be beneficial or required to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. Alternatively, mechanical abrasion without the use of corrosive chemicals is used for planarization. In some embodiments, purely mechanical abrasion is achieved by using a belt grinding machine, a standard wafer backgrinder, or other similar machine. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.

Back-end manufacturing as disclosed herein also does more than merely packaging an embedded device or the semiconductor die for structural support and environmental isolation. The packaging described herein further provides non-monolithic electrical interconnection of die for increased functionality & performance. Previously, nearly all advanced semiconductor die were monolithic systems on chips (SoCs) where all electrical interconnect occurred on the silicon wafer during front-end processing. Now, however, work that was traditionally the domain of front-end domain work may be handled or moved to the back-end manufacturing, allowing many semiconductor die (chiplets) to be connected with packaging technology to form a chiplet-based SoC (which is non monolithic) and provides a composite package with greater functionality. The chiplet approach may also decrease waste from defects, increase production efficiency, reliability, and performance.

The electrical system can be a stand-alone system that uses the semiconductor device to perform one or more electrical functions. Alternatively, the electrical system can be a subcomponent of a larger system. For example, the electrical system can be part of a portable hand-held electronic device, such as smart phone, a wearable electronic device, or other video or electronic communication device. Additionally, the electrical system may comprise a graphics component, network interface component, or other signal processing component that can be inserted into a computer or electronics device and may assist with such functions as mobile computing, artificial intelligence, and autonomous functions such as autonomous driving. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction can be beneficial or essential for the products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.

By combining one or more semiconductor devices, structures, or packages with fan-out technology, manufacturers can incorporate multiple components or elements into more highly compact and integrated electronic devices and systems. Because the semiconductor devices include sophisticated functionality, electronic devices can be manufactured less expensively and as part of a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIGS.1A-1Fshow prior art relative to connecting multiple semiconductor die or semiconductor packages together, that may be used for high intensity or high demand computing, such as computing utilizing or dealing with graphics cards.FIG.1Aillustrates an existing packaging technology or structure10comprising a graphics processing unit (GPU12) coupled to an HBM controller die14with bumps or microbumps15and through a silicon interposer16comprising silicon vias formed in, and extending therethrough. The silicon interposer16may then be disposed over and coupled to a package substrate18, with conductive or solder interconnects, bumps, or balls17. The package substrate18may then be disposed over and coupled to a graphics card or PCB20with conductive or solder interconnects, bumps, or balls22. The graphics card20may comprise a multi-layer PCB, and the conductive bumps20may be used for: display connections, electrical current, as well as for peripheral component interconnect express (PCIe) interconnections or high-speed serial computer expansion bus connections.

FIG.1Billustrates a representation of a cross-section structure11that could be seen by a scanning electron microscope (SEM) of an HBM14stacked on- and coupled to-a silicon interposer16, which may further be coupled to a substrate, PCB, or graphics card20. The structure11integrates HBM memories14(which may comprise DRAM die and Logic Die connected with via-middle TSV and micro-bumps) and the GPU12stacked onto the silicon interposer16, wherein the silicon interposer16comprises via-middle through silicon vias (TSVs).

FIGS.1C-1Fillustrates an existing technology of Intel's Embedded Multi-die Interconnect Bridge (EMIB)30, that was developed to provide a cost-effective approach to in-package high density interconnect of heterogeneous chips or semiconductor die32.

FIG.1Cillustrates the EMIB30embedded in a cavity34of an organic substrate36, the EMIB30comprises conductive pads or contact pads38coupled together with a conductive redistribution layer (RDL)40.FIG.1Dillustrates resin42formed over the EMIB30, and vias44formed in, or extending through, the resin42with the vias44further coupled with the EMIB30. RDLs46may be formed over the resin42and over the EMIB30and coupled with the vias44for lateral connection that extend from the EMIB30and vias44to mounting sites48for heterogeneous chips32.FIG.1Eillustrates additional vias44and layers of resin42formed over the EMIB30with contact pads for microbumps50formed over the EMIB30and contact pads for ordinary bumps52formed at semiconductor die mounting sites48.FIG.1Fillustrates a first semiconductor die32aon the left and a second semiconductor die32bon the right, each mounted over respective semiconductor die sites48with microbumps54and ordinary bumps56and RDLs40,46and vias44for routing of signals and interconnections for the semiconductor die32a,32bbeing routed through the organic substrate36and through the EMIB30.

FIGS.2A-2Cillustrate a chiplet60or grouping of multiple semiconductor die, semiconductor chips, or semiconductor devices62interconnected and molded together.FIG.2Aillustrates a chiplet60(without encapsulant) comprising a central, larger, semiconductor die, semiconductor chip, or semiconductor device62, with multiple, additional, smaller semiconductor die64to show the multiple semiconductor die, semiconductor chips, or semiconductor devices64disposed around and grouped together with semiconductor device62, such as in a fan-out arrangement. Chip type or function of the various semiconductor die62,64within the chiplet60may comprise a central processing unit (CPU), a modem, a graphics processing unit (GPU), chips, semiconductor die, or processors specialized for running artificial intelligence (AI) algorithms, chips, semiconductor die or processors specialized for input/output (I/O), Serializer/Deserializer (SERDES) devices, and various other memory devices such as chips or semiconductor die specialized for Cache or storing data, and chips specialized for high bandwidth memory (HBM) or high-speed computer memory.FIGS.2B and2Cillustrate the same or similar chiplet60shown inFIG.2Aovermolded with encapsulant material and in a fan-out arrangement. InFIG.2C, the overmolded semiconductor die chiplet60is coupled to, or disposed over (or on) a substrate or package substrate66, which may be further coupled to, or mounted on, a motherboard, a printed circuit board (PCB), an interposer, or another semiconductor device or package. The method and device described herein may be advantageously used for applications in which the device is mounted to a substrate, and may also be used for instances in which it is not mounted to a substrate, like for applications within a handheld mobile electronic device, such as a smartphone or other wearable technology.

FIGS.3A-3Cshow various views of a semiconductor wafer110and the formation and separation of individual semiconductor die114therefrom.FIG.3Aillustrates a plan view of a semiconductor wafer or native wafer110with a base substrate material112, such as, without limitation, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of semiconductor die or components114can be formed on wafer110separated by a non-active, inter-die wafer area or saw street116as described above. The saw street116can provide cutting areas to singulate the semiconductor wafer110into the individual semiconductor die114.

Each semiconductor die114may comprise a backside or back surface118and an active surface120opposite the backside118. The active surface120may contain analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the semiconductor die114. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuits. The semiconductor die114may also contain IPDs such as inductors, capacitors, and resistors, such as for power management, RF signal processing, and clocking or other functions. The semiconductor die114may be formed on a native wafer in a wafer level process as one of many packages being formed simultaneously on a carrier. In other instances, the semiconductor die114may be formed as part of a reconstituted wafer, and may comprise multiple die molded together. The semiconductor die114may also be another suitable embedded device, which is subsequently formed within the fully-molded bride interposer300, and surrounded (partially or entirely) by encapsulant256. The semiconductor die114within the fully molded bridge interposer300may be an active die, a bridge die, and in other instances may be formed without an active surface, and with copper studs of the bridge die electrically connected or coupled with wiring, routing, or RDLs.

FIG.3B. illustrates a cross sectional sideview of the wafer110, as shown taken along the section line3B-3B inFIG.3A.FIG.3Balso illustrates an optional dielectric, insulating. or passivation layer126conformally applied over the active surface120and over conductive layer122. Insulating layer126can include one or more layers that are applied using PVD, CVD, screen printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable process. Insulating layer126can contain, without limitation, one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), polymer, polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), or other material having similar insulating and structural properties. Alternatively, semiconductor die114are packaged without the use of any PBO layers, and insulating layer126can be formed of a different material or omitted entirely. In another embodiment, insulating layer126includes a passivation layer formed over the active surface120without being disposed over conductive layer122. When insulating layer126is present and formed over conductive layer122, openings are formed completely through insulating layer126to expose at least a portion of conductive layer122for subsequent mechanical and electrical interconnection. Alternatively, when insulating layer126is omitted, conductive layer122is exposed for subsequent electrical interconnection without the formation of openings.

FIG.3Balso illustrates conductive bumps, conductive interconnects, or electrical interconnect structures128that can be formed as columns, pillars, posts, thick RDLs, bumps, or studs that are formed of copper or other suitable conductive material, which are disposed over, and coupled or connected to, conductive layer122. When formed as posts128, the posts will have a height greater than a thickness, whereas a pillar has a tin cap and a stud is wider than it is tall. Conductive bumps128can be formed directly on conductive layer122using patterning and metal deposition processes such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. Conductive bumps128can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, palladium (Pd), or other suitable electrically conductive material and can include one or more layers. In some instances, one or more UBM layers of Al, Cu, Sn, Ni, Au, Ag, Pd, or other suitable electrically conductive material can optionally be disposed between conductive layer122and conductive bumps128. In some embodiments, conductive bumps128can be formed by depositing a photoresist layer over the semiconductor die114and conductive layer122while the semiconductor die114are part of the semiconductor wafer110. A portion of the photoresist layer can be exposed and removed by an etching development process, and the conductive bumps128can be formed as copper pillars in the removed portion of the photoresist and over conductive layer122using a selective plating process. The photoresist layer can be removed leaving conductive bumps128that provide for subsequent mechanical and electrical interconnection and a standoff with respect to active surface120. Conductive bumps128can include a height H1in a range of 5-100 micrometers (μm) or a height in a range of 20-50 μm, or a height of about 25 μm.

FIG.3Balso illustrates the semiconductor wafer110can undergo an optional grinding operation with a grinder129to planarize the surface and reduce a thickness of the semiconductor wafer110. A chemical etch can also be used to remove and planarize a portion of the semiconductor wafer110.

FIG.3Cillustrates attaching a die attach film (DAF)130to the semiconductor wafer110that can be disposed over, and in direct contact with, the backsides118of the semiconductor die114. The DAF130can comprise epoxy, thermal epoxy, epoxy resin, B-stage epoxy laminating film, ultraviolet (UV) B-stage film adhesive layer, UV B-stage film adhesive layer including acrylic polymer, thermo-setting adhesive film layer, a suitable wafer backside coating, epoxy resin with organic filler, silica filler, or polymer filler, acrylate based adhesive, epoxy-acrylate adhesive, a polyimide (PI) based adhesive, or other adhesive material.

FIG.3Calso illustrates semiconductor wafer110can be singulated through gaps or saw streets116using laser grooving, a saw blade or laser cutting tool132, or both to singulate the semiconductor wafer110into individual semiconductor die114with conductive bumps128. The semiconductor die114can then be used as part of a subsequently formed semiconductor component package as discussed in greater detail below with respect toFIGS.4A-4H.

FIGS.4A-5C, illustrate a structure, method, process flow for forming the semiconductor device or molded bridge interposer that may comprise a bridge die and peripheral posts.FIG.4Aillustrates providing a temporary carrier or substrate140, on which subsequent processing of the fully-molded bridge interposer300can occur, as described in greater detail herein. Carrier140may be a temporary or sacrificial carrier or substrate, and in other instances may be or a reusable carrier or substrate. The carrier140may be of any desirable or suitable size, including a circular shape comprising a diameter of 300 mm.

The carrier140can contain one or more base materials formed in one or more layers, which may comprise base materials such as metal, silicon, polymer, polymer composite, ceramic, perforated ceramic, glass, glass epoxy, stainless steel, mold compound, mold compound with filler, or other suitable low-cost, rigid material or bulk semiconductor material for structural support. When a UV release is used with a temporary carrier140, the carrier140may comprise one or more transparent or translucent materials, such as glass. When a thermal release is used with a temporary carrier140, the carrier140may comprise opaque materials. The carrier140can be circular, square, rectangular, or other suitable or desirable shape and can include any desirable size, such as a size equal to, similar to, or slightly larger or smaller than a reconstituted wafer or panel that is subsequently formed on or over the carrier140. In some instances, a diameter, length, or width of the temporary carrier can be equal to, or about, 200 millimeters (mm), 300 mm, or more.

The carrier140can comprise a plurality of semiconductor die mounting sites or die attach areas142spaced or disposed across a surface of the carrier140, according to a design and configuration of the final fully-molded bridge interposer semiconductor devices300, to provide a peripheral area or space143. The peripheral area143can partially or completely surround the die attach areas142to provide space for subsequent vertical, through package interconnections, and an area for fan-out routing or build-up interconnect structures. For example, the peripheral area143can surround, or be offset from, one side of the semiconductor die114, or more than one side of the semiconductor die114, such as 2, 3, 4, or more sides of the semiconductor die114.

When a temporary carrier140is used, an optional release layer, interface layer or double-sided tape144can be formed over carrier140as a temporary adhesive bonding film or etch-stop layer. The release layer144may be a film or laminate, and may also be applied by spin coating or other suitable process. The temporary carrier can be subsequently removed by strip etching, chemical etching, mechanical peel-off, CMP, plasma etching, thermal, light releasing process, mechanical grinding, thermal bake, laser scanning, UV light, or wet stripping.

FIG.4Afurther illustrates forming a build-up interconnect structure170over the carrier140to electrically connect, and provide routing between, conductive interconnects252, the conductive bumps128, and other device mounted on, or coupled with, the fully-molded bridge interposer300. While the build-up interconnect structure170is shown comprising three conductive layers and three insulating layer, a person of ordinary skill in the art will appreciate that fewer layers or more layers can be used depending on the configuration and design of the fully-molded bridge interposer or semiconductor device300. The build-up interconnect structure170can optionally comprise a first insulating or passivation layer172formed or disposed over the carrier140. The first insulating layer172can comprise one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polymer, polyimide, BCB, PBO, or other material having similar insulating and structural properties. The insulating layer172can be formed using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. Openings or first level conductive vias can be formed through the insulating layer172for subsequent interconnection with bumps296.

A first conductive layer174can be formed over the substrate140and over the first insulating layer172as a first RDL layer to extend through the openings in the first insulating layer172, to electrically connect with the first level conductive vias, and to electrically connect with the conductive bumps128and the conductive interconnects252. Conductive layer174can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating, or other suitable process.

A second insulating or passivation layer176, which can be similar or identical to the first insulating layer172, can be disposed or formed over the substrate140, the first conductive layer174, and the first insulating layer172. An opening or second level conductive via can be formed through the second insulating layer176to connect with the first conductive layer174.

A second conductive layer178, when desirable and when present, may be similar or identical to the first conductive layer174, can be formed as a second RDL layer over substrate140, over the first insulating layer172, over the first conductive layer174, over the second level conductive via, or within an opening of the second insulating layer172, to electrically connect with the first conductive layer174, the first level and second level conductive vias, and the semiconductor die114.

A third insulating or passivation layer180, when desirable and when present, may be similar or identical to the first insulating layer172, can be disposed or formed over the second conductive layer178and the second insulating layer176. An opening or a third level conductive via can also be formed in or through the third insulating layer280to connect with the second conductive layer178.

A third conductive layer182, when desirable and when present, may be similar or identical to the second conductive layer178, can be formed as a third RDL layer—or as vias or vertical interconnects through the third insulating layer180—and further disposed over the second insulating layer176, over the second conductive layer178, over the second level conductive via, or within an opening of the second insulating layer176, to electrically connect with the second conductive layer178, and the semiconductor die114.

FIG.4Bfurther illustrates forming a seed layer190over the build-up interconnect structure170. The seed layer190can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Titanium (Ti), Tungsten (W) or other suitable electrically conductive material. In some instances, the seed layer190will be, or may include, Ti/Cu, TiW/Cu, W/Cu or a coupling agent/Cu. The formation, placement, or deposition of the seed layer190can be with PVD, CVD, electrolytic plating, electroless plating, or other suitable process. The seed layer190can be deposited by sputtering, electroless plating, or by depositing laminated foil, such as Cu foil, combined with electroless plating.

FIG.4Cillustrates forming or depositing a resist layer or photosensitive layer248over and directly contacting seed layer190, over build-up interconnect structure170, and over the temporary carrier140. After formation of the resist layer248over the temporary carrier, the resist layer248can then be exposed and developed to form openings250in the resist layer248. In some instances, more than one photoresist layer248may be used. Openings250may be formed in the photoresist248, and can be positioned over, or within a footprint of, the peripheral area143of the carrier140. The openings250can extend completely through the resist layer248, such as from a first surface or bottom surface249of the resist layer248to second surface or top surface251of the resist layer248opposite the first surface249. An after development inspection (ADI) of the developed resist layer248and the openings250can be performed to detect the condition or quality of the openings250. After the ADI of resist layer248and openings250, a descum operation can be performed on the developed resist layer248.

FIG.4Dshows the formation of a plurality of conductive interconnects252that were formed within the openings250in resist layer248. The conductive interconnects252can be formed as columns, pillars, posts, bumps, or studs that are formed of copper or other suitable conductive material. Conductive interconnects252can be formed using patterning and metal deposition processes such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. When conductive interconnects252are formed by plating, the seed layer190can be used as part of the plating process. Conductive interconnects of posts252can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Pd, solder, or other suitable electrically conductive material and can include one or more layers.

After formation of the conductive interconnects252, the resist layer248can be removed, such as by a stripping process, leaving conductive interconnects252in the peripheral area143around the semiconductor die mounting sites142to provide for subsequent vertical or three dimensional (3D) electrical interconnection for the fully-molded bridge interposer300. Conductive interconnects252can include a height H2in a range of 80-300 μm or a height in a range of 100-150 μm, or a height thereabout. In other instances, conductive vertical interconnects252may include a height in a range of 10-600 μm, 60-100 μm, 70-90 μm, or about, 80 μm. As used herein, “thereabout,” “about,” or “substantially” means a percent difference in a range of 0-5%, 1-10%, 1-20%, 1-30%, or 1-50% of the number or range indicated.

After removal of the resist layer248, the semiconductor die mounting sites142on or over the temporary carrier140, the build-up interconnect structure170, or both, can be exposed and ready to receive the semiconductor die114. The orientation of semiconductor die114can be either face up with active surface120oriented away from the temporary carrier140to which the semiconductor die114are mounted, or alternatively can be mounted face down with the active surface120oriented toward the temporary carrier140to which the semiconductor die114are mounted. After mounting the semiconductor die114to the temporary carrier140in a face up orientation, the DAF130can undergo a curing process to cure the DAF130and to lock the semiconductor die114in place to the build-up interconnect structure70and over the temporary carrier140.

FIG.4Eshows a top or plan view of a portion of the temporary carrier140and the conductive interconnects252taken along the section line4E fromFIG.4D.FIG.4Eshows that the conductive interconnects252can be formed within, and extend intermittently across, the peripheral area143and surround the semiconductor die mounting sites142(and the semiconductor die114) without being formed within the semiconductor die mounting sites142. Additionally,FIG.4Eshows that after the semiconductor die114is mounted at the mounting side142, a first side114aof semiconductor die114is offset by an offset O1from the conductive posts252adjacent the first side114a. A second side114bof semiconductor die114(which is opposite the first side114a) is offset by an offset O2from the conductive posts252adjacent the first side114b.

FIG.4F, continuing fromFIGS.4D and4E, illustrates that after mounting the semiconductor die114to the carrier140, a mold compound or encapsulant256can be deposited around the plurality of semiconductor die114using a paste printing, compression molding, transfer molding, liquid encapsulant molding, lamination, vacuum lamination, spin coating, or other suitable applicator. The encapsulant256can be a polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, PBO, polyimide, polymer with or without proper filler. Semiconductor die114can be embedded in encapsulant256, which can be non-conductive and environmentally protect the semiconductor die114from external elements and contaminants. The encapsulant256can be formed as a single encapsulant in a single step adjacent to and directly contacting all lateral sides of the semiconductor die (such as four sides), as well as be formed over the active surface120of the semiconductor die114. The same single encapsulant256can also be formed around and directly contact the sides of the conductive bumps128and the sides252aof conductive interconnects252in a single step to form at least part of a molded bridge interposer panel or molded panel258. The molded bridge interposer panel or molded panel258may comprise one build-up interconnect structure170, as shown inFIG.4F, or may comprise two opposing build-up interconnect structures170,270, as illustrated inFIG.4G. While a method is shown of forming build-up interconnect structure170first, followed by building build-up interconnect structure270, the order may be reversed. In some instances, the encapsulation and frontside build-up interconnect structure270may be built first, followed by removal of the temporary carrier140, and further followed by the formation of the backside build-up interconnect structure170.

The molded panel258can optionally undergo a curing process or post mold cure (PMC) to cure the encapsulant256. In some instances, a top surface, front surface, or first surface262of the encapsulant256can be substantially coplanar with first end253of the conductive interconnects252. Alternatively, the top surface262of the encapsulant256can be over, offset, or vertically separated from the first ends253of the conductive interconnects252, such that the first ends253of the conductive interconnects252are exposed with respect to the encapsulant256after the reconstituted wafer258undergoes a grinding operation, or through a recess257in the encapsulant256to expose the first end253.

The molded panel258can also undergo an optional grinding operation with grinder264to planarize the top surface, front surface, or first surface268of the molded panel258and to reduce a thickness of the molded panel258, and to planarize the top surface262of the encapsulant256and to planarize the top surface268of the molded panel258. The top surface268of the molded panel258can comprise the top surface262of the encapsulant256, the first ends of the conductive interconnects252, or both. A chemical etch can also be used to remove and planarize the encapsulant256and the molded panel258. Thus, the top surface268of the conductive interconnects252can be exposed with respect to encapsulant256in the peripheral area143to provide for electrical connection between semiconductor die114and a subsequently formed redistribution layer or build-up interconnect structure170.

The reconstituted wafer258can also undergo a panel trim or trimming to remove excess encapsulant256that has remained in undesirable locations as a result of a molding process, such as eliminating a flange present for a mold chase. The molded panel258can include a footprint or form factor of any shape and size including a circular, rectangular, or square shape, the reconstituted wafer258comprising a diameter, length, or width of, or about, 200 millimeter (mm), 300 mm, or any other desirable size.

FIG.4Falso shows that actual positions of the semiconductor die114within the molded panel258may be measured with an inspection device or optical inspection device259. As such, subsequent processing of the fully molded panel258as shown and described with respect to subsequent FIGs. can be performed with respect to the actual positions of the semiconductor die114within the molded panel258.

FIG.4G. shows forming a build-up interconnect structure270—such as a second or active side build-up interconnect structure—over the molded panel258to electrically connect, and provide routing between, conductive interconnects252and the conductive bumps128. While the build-up interconnect structure270is shown comprising three conductive layers and three insulating layer, a person of ordinary skill in the art will appreciate that fewer layers or more layers can be used depending on the configuration and design of the fully-molded bridge interposer300. The build-up interconnect structure270can optionally comprise a first insulating or passivation layer272formed or disposed over the molded panel258. The first insulating layer272can comprise one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polymer, polyimide, BCB, PBO, or other material having similar insulating and structural properties. The insulating layer272can be formed using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. Openings or first level conductive vias can be formed through the insulating layer272over the conductive interconnects252and the conductive bumps128to connect with the semiconductor die114.

A first conductive layer274can be formed over the molded panel258and over the first insulating layer272as a first RDL layer to extend through the openings in the first insulating layer272, to electrically connect with the first level conductive vias, and to electrically connect with the conductive bumps128and the conductive interconnects252. As used herein, the term RDL includes distribution, redistribution, or movement, of signal through the conductive material in a vertical direction, horizontal direction, or both. As such, an RDL may, but need not have, a horizontal component. Conductive layer274can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating, or other suitable process.

When the first conductive layer274is formed, it may be formed at least partially within a corresponding first via layer formed within the first insulating layer272of the frontside build-up interconnect structure270. The first conductive layer274may comprises vias aligned to centers128cof the copper studs128. The alignment with the centers128cof studs or conductive bumps128may be measured with an r2(or R-squared) value for a lot (or statistically significant number) of die114or devices300. The R-squared value (also known as the coefficient of correlation) is a statistical measure of how closely data is fitted to a regression line, which in this case is based on the lot of die114or devices300. Stated another way, an R-squared value is the proportion of the variation in the dependent variable that is predictable from the independent variable. The alignment with the centers128cof studs or conductive bumps128may have an r2value greater than or equal to 0.5, 0.6, 0.7, 0.8, or in a range greater than or equal to 0.5-0.8 relative to a difference between an offset O1between a first side114aof the bridge die114and a copper post252aadjacent the first side114aof the bridge die114and a second offset O2between a second side114bof the bridge die114opposite the first side114aof the bridge die114and a corresponding copper post252badjacent the second side114bof the bridge die114. As such, the r2value of greater than about 0.5 (or 50%), 0.6 (or 60%), 0.7 (or 70%), 0.8 (or (0%), or more between the centers128cand the centers of the vias274vof the conductive layer274when compared with the difference in the offsets between O1and O2provides a structural way of identifying that the processing of the build-up interconnect structure270was performed with respect to the actual positions of the semiconductor die114within the molded panel258, thereby allowing for finer pitch connections with the high density and ultra-high density interconnection with the bridge die114and the build-up interconnect structure270. Stated another way, the differences, offsets, or misalignments between the centers128cand the centers of the vias274vof the conductive layer274is less than (or more closely aligned), than the differences, offsets, or misalignments between the differences in offsets O1and O2between the copper posts252of the bridge die114for the lot of die114or devices300. Stated yet another way, for a lot of die114or devices300, the differences, offsets, or misalignments between the centers128cand the centers of the vias274vis not statistically correlated (or has an r2value less than 0.5) to the alignment of the die to the copper posts252on each side of the die114(measured by looking at the offsets O1and O2).

A second insulating or passivation layer276, which can be similar or identical to the first insulating layer272, can be disposed or formed over the molded panel258, the first conductive layer274, and the first insulating layer272. An opening or second level conductive via can be formed through the second insulating layer276to connect with the first conductive layer274.

A second conductive layer278, when desirable and when present, may be similar or identical to the first conductive layer274, can be formed as a second RDL layer over molded panel258, over the first insulating layer272, over the first conductive layer274, over the second level conductive via, or within an opening of the second insulating layer272, to electrically connect with the first conductive layer274, the first level and second level conductive vias, and the semiconductor die114.

A third insulating or passivation layer280, when desirable and when present, may be similar or identical to the first insulating layer272, can be disposed or formed over the second conductive layer278and the second insulating layer276. An opening or a third level conductive via can also be formed in or through the third insulating layer280to connect with the second conductive layer278.

A third conductive layer282, when desirable and when present, may be similar or identical to the second conductive layer278, can be formed as a third RDL layer—or as vias or vertical interconnects through the third insulating layer280—and be further disposed over the second insulating layer276, over the second conductive layer278, over the second level conductive via, or within an opening of the second insulating layer276. The third conductive layer282can electrically connect with the second conductive layer278, and be coupled with the conductive interconnects252and the semiconductor die114.

In some instances, the third (or final) conductive layer within the build-up interconnect structure270cam be formed as UBMs282that are formed over the third insulating layer80to electrically connect with the other conductive layers and conductive vias within the build-up interconnect structure270, as well as electrically connect to the semiconductor die114, the conductive bumps128, and the conductive interconnects252. UBMs282, like all of the layers, plating layers, or conductive layers formed by a plating process as presented herein, can be a multiple metal stack comprising one or more of an adhesion layer, barrier layer, seed layer, or wetting layer. The adhesion layer can comprise titanium (Ti), or titanium nitride (TiN), titanium tungsten (TiW), Al, or chromium (Cr). The barrier layer can be formed over the adhesion layer and can be made of Ni, NiV, platinum (Pt), palladium (Pd), TiW, or chromium copper (CrCu). In some instances, the barrier layer can be a sputtered layer of TiW or Ti and can serve as both the adhesion layer and the barrier layer. In either event, the barrier layer can inhibit unwanted diffusion of material, like Cu. The seed layer can be Cu, Ni, NiV, Au, Al, or other suitable material. For example, the seed layer can be a sputtered layer of Cu comprising a thickness of about 2000 angstroms (e.g., 2000 plus or minus 0-600 angstroms). The seed layer can be formed over the barrier layer and can act as an intermediate conductive layer below subsequently formed upper bumps, balls, or interconnect structures290. In some instances, the wetting layer can comprise a layer of Cu with a thickness in a range of about 5-11 μm or 7-9 μm. Upper bumps290, such as when formed of SnAg solder, can consume some of the Cu UBM during reflow and forms an intermetallic compound at the interface between the solder bump290and the Cu of the wetting layer. However, the Cu of the wetting layer can be made thick enough to prevent full consumption of the Cu pad by the solder during high temperature aging.

UBMs282may be formed as a PoP UBM pad, UBM structure, or land pad, such as for stacked PoP structure, an additional electronic component. In some instances, the UBMs282can comprise Ni, Pd and Au. UBMs282can provide a low resistive interconnect to build-up interconnect structure270as well as a barrier to solder diffusion and seed layer for solder wettability.

The upper bumps290can be formed on or coupled to the UBMs282. The bumps290can be formed by depositing an electrically conductive bump material over the UBMs282using an evaporation, electrolytic plating, electroless plating, ball drop, or screen-printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, bismuth (Bi), Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material can be bonded to the UBMs282using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps290. In some applications, bumps290are reflowed a second time to improve electrical contact to UBMs282. The bumps290can also be compression bonded or thermocompression bonded to the UBMs282. Bumps290represent one type of interconnect structure that can be formed over the conductive interconnects252, and other desirable structures, such as conductive paste, stud bump, micro bump, or other electrical interconnects may also be used as desired.

FIG.4Hillustrates singulation of the molded panel258and build-up interconnect structures170,270with saw blade or laser cutting tool294to form individual fully-molded bridge interposers300. The final interposer structure300may be thinner than previous packages, comprising an overall height or thickness of, or on the order of, or about, 50-250, 100-200, or less than or about 150 μm. Stacks of multiple layers can be correspondingly thicker, and increase in multiples of the above ranges, resulting in an overall thickness in a range of 200-1,000 μm. As part of the reduced height of the structure, the final structure may be made without an interposer, comprising the build-up interconnect layers and conductive vertical providing the function of an interposer, and serving as s sort of embedded interposer.

FIG.4Hillustrates removing the temporary carrier140, to expose the second ends254of the conductive interconnects252. The carrier140can be removed, e.g., by grinding the carrier140, by exposing UV release tape144to UV radiation separate the UV tape144from the glass substrate140, by thermal release, or other suitable method. After removal of the carrier140, the molded panel258can also undergo an etching process, such as a wet etch, to clean the surface of the molded panel258exposed by removal of the temporary carrier140, including the exposed second ends254of the conductive interconnects252. The exposed second ends254of the conductive interconnects252can also undergo a coating or pad finishing process, such as by an Organic Solderability Preservative (OSP) coating, solder printing, electroless plating, or other suitable process, to form a PoP UBM pad, UBM structures, land pads, or other suitable structure, as desired.

Lower bumps, balls, or interconnect structures296, can be formed on or coupled to the exposed second ends254of the conductive interconnects252, as shown, for example, inFIG.5C. The bumps296can be formed by depositing an electrically conductive bump material over the exposed second ends254of the conductive interconnects252using an evaporation, electrolytic plating, electroless plating, ball drop, or screen-printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material can be bonded to the exposed second ends254of the conductive interconnects252using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps296. In some applications, bumps296are reflowed a second time to improve electrical contact to conductive interconnects252. The bumps296can also be compression bonded or thermocompression bonded to the conductive interconnects252. Bumps296represent one type of interconnect structure that can be formed over the conductive interconnects252, and other desirable structures, such as conductive paste, stud bump, micro bump, or other electrical interconnects may also be used as desired.

FIG.5Aillustrates a high-level perspective view of a fully molded bridge interposer300disposed (or sandwiched) between: (i) a chiplet arrangement310of semiconductor devices (e.g., a System On Chip (SOC)312and High Bandwidth Memory (HBM) devices314), and (ii) a substrate or package substrate320, similar to what was shown inFIGS.2A-2C. In the past, a chiplet60or arrangement of semiconductor devices62,64similar to what was shown inFIG.2Amay have been coupled together with silicon interposers comprising TSVS, or EMIBs, as shown and described above with respect toFIGS.1A-1F. However,FIGS.5A-5Cshow the new technology of a fully molded bridge interposer300to replace the existing technology of a silicon interposer or EMIB.

FIG.5Bshows a cross-sectional profile view taken along the section-line or box labeled “5B” inFIG.2B.FIG.5Bshows a cross-sectional profile view of the fully-molded bridge interposer300, similar to the view shown inFIG.4H. Moreover, the view ofFIG.5Bfurther includes the features of the fully-molded bridge interposer300shown more closely to scale.FIG.5Bshows the peripheral conductive interconnect structures252disposed around, and laterally offset from, the semiconductor die114and within the encapsulant material256. The peripheral conductive interconnect structures252can extend completely through the encapsulant256in a vertical direction from, or adjacent, the top surface262of the encapsulant256to, or adjacent, the bottom surface266of the encapsulant256opposite top surface262to provide vertical electrical interconnection through the fully-molded bridge interposer300, which can facilitate stacking of packages in PoP arrangements.FIG.5Bfurther shows a fully molded bridge interposer300disposed between a chiplet arrangement310of at least two semiconductor devices (such as a SOC312and a HBM314) and a package substrate320.

FIG.5Cshows a close-up sectional profile view of a portion of the fully molded bridge interposer300ofFIG.5Bshown within the section-line or box designated5C.FIG.5Cshows the semiconductor die114, conductive or copper bumps or interconnects128, and conductive or copper posts252, included within the encapsulant256. Electrical build-up interconnect structures170,270comprising RDLs are formed above and below opposing surfaces262,266of the encapsulant256as well as above and below the semiconductor die114and conductive or copper studs128, and conductive or copper posts252. The semiconductor die114, conductive or copper studs128, and conductive or copper posts252, are electrically coupled to, or interconnected with, the chiplet arrangement310, which may include a SOC312, HBMs314, and any other number of desired semiconductor devices within the chiplet310or SOC312.

Attachment options for the molded bridge interposer300, to chiplet arrangement310include upper bumps, balls, or interconnect structures290. Attachment options for the molded bridge interposer300to the substrate320include lower bumps, balls, or interconnect structures296. Bumps290and296may each include: 1) solder bumps, 2) plated copper plus a solder post, and 3) direct copper to copper bonding. Additional design options for the fully molded bridge interposer300include: 1) underfill, and 2) over mold, as desired or as applicable.

FIG.5Calso shows exemplary layers labeled with dimensions that are about, or approximately, the dimensions indicated. The semiconductor die114may comprise a height or thickness (with or without to die attach material115) of about 100 μm and the conductive posts252may comprise a height of about 125 μm. As used herein “about” and “approximately” mean within a percent difference of less than or equal to 50%, 40%, 30%, 20%, 10%, 5%, 3%, 2%, or 1%.

The fully-molded bridge interposers300provide cost advantages for high density integration, which includes integrations comprising 2 μm line and space pitch, and 20 μm area array bond pad pitch. Advantages include: (i) cost reduction greater than or equal to 80% for extending die size with respect to growing monolithic silicon (e.g., $0.01 per mm2versus $0.06 per mm2), and (ii) cost reduction greater than or equal to 50% compared to laminate embedded bridges (e.g., $0.01 per mm2vs. $0.03 per mm2. For ultra-high density integration with the fully molded bridge interposer300, an enabled 20 μm area array bond pad pitch allows for increased or improved input/output (IO) on advanced node silicon without a die size penalty so that the integrated circuit (IC) device IO count is no longer constrained by a number of bond pads which will fit in minimum possible device size. As such, as much as an 80% reduction in die size is possible when total size has been based bond pad area requirements when using existing technology.

While this disclosure includes a number of embodiments in different forms, the drawings and written descriptions present detail of particular embodiments with the understanding that the present disclosure is to be considered as an exemplification of the principles of the disclosed methods and systems, and is not intended to limit the broad aspect of the disclosed concepts to the embodiments illustrated. Additionally, it should be understood by those of ordinary skill in the art that other manufacturing devices and examples could be intermixed or substituted with those provided. In places where the description above refers to particular embodiments, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these embodiments and implementations may be applied to other technologies as well. Accordingly, the disclosed subject matter is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the disclosure and the knowledge of one of ordinary skill in the art.