Slicer and decision feedback equalization circuitry

One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

FIELD

The present disclosure relates to a slicer and decision feedback equalization circuitry, in particular to, enhanced slicer circuitry and decision feedback equalization circuitry.

BACKGROUND

Receivers utilized in communication systems (e.g., Ethernet physical layer (PHY)) may include Decision feedback equalizers (DFE). The receivers are configured to receive transmitted digital data that has been serialized and modulated onto a carrier signal and transmitted over a channel and to recover the digital data. The received signal may be degraded by non-ideal characteristics of the channel (e.g., finite bandwidth). As a result, a sample of the received signal corresponding to a digital data bit may include contributions from previously transmitted bits (i.e., inter-symbol interference). DFEs are configured to utilize one or more prior decisions to reduce the effects of inter-symbol interference to facilitate recovery of the transmitted digital data.

Increasing data rates to on the order of tens and/or hundreds of gigabits per second (Gbps) creates challenges for DFE circuitry. For example, DFE circuitry contains a feedback loop and the feedback timing may be limited by the TCO (timing from clock to output) of clocked comparator circuitry (i.e., decision element) included in the DFE circuitry. Thus, operation of the DFE circuitry may be constrained by characteristics of the clocked comparator circuitry. Increasing the speed and/or the accuracy of the clocked comparator circuitry may result in an increase in size and/or an increase in power consumption of the DFE and associated receiver.

DFE circuitry may include a plurality of taps. Each tap corresponds to a respective prior decision weighted by a respective weight. Respective outputs of each tap of a plurality of taps are typically combined with a representation of the received signal, e.g., input data, in a summation node. Each tap acts as a load on the summation node and thus, may limit the bandwidth of the feedback loop. As the number of taps increases, the resulting load increases and the associated bandwidth may decrease. Bandwidth limitations may then result in an increased delay between an input to the DFE circuitry and an output from the DFE circuitry. Such delay can detrimentally affect timing, particularly at relatively high frequencies and corresponding relatively high data rates. The bandwidth limitations may limit loop gain. The limited loop gain may then be compensated by an increase in a number of variable gain amplifier (VGA) stages preceding the DFE circuitry. Increasing the number of VGA stages may increase a size and/or power consumption of the receiver circuitry.

DETAILED DESCRIPTION

Generally, this disclosure relates to an enhanced slicer and/or decision feedback equalization (DFE) circuitry. The DFE circuitry includes a slicer that may or may not be enhanced. As used herein, “slicer” corresponds to an internal latch comparator (i.e., a clocked comparator) that includes comparator circuitry and a latch circuitry. In some embodiments, the clocked comparator may be coupled to current path circuitry. The current path circuitry is configured to enhance current flow between at least one output node of the clocked comparator and a reference node (e.g., a supply voltage or ground) of the clocked comparator, in response to a clock signal. Thus, as used herein, an “enhanced slicer” corresponds to a combination of a clocked comparator and current path circuitry.

The current path circuitry is configured to reduce a duration of a time interval between the slicer exiting a reset state and outputting a decision. The reset state may be exited based, at least in part, on a clock signal. The decision corresponds to the slicer output achieving a stable value. In other words, in response to a clock trigger (e.g., a rising or falling edge and/or a change of state), a differential output of the slicer may begin to transition from a zero value to a positive or negative value. Whether the differential slicer output transitions to a positive or negative value depends, at least in part, on the relative voltages applied to the differential inputs of the clocked comparator. The current path circuitry is configured to reduce a duration of a time interval between the clock trigger and the slicer entering a positive feedback phase.

The current path circuitry is further configured to increase a trans conductance of a slicer (i.e., increase a ratio of a change in output current, e.g., IDS, to a change in input voltage, e.g., VGS). Operation of the clocked comparator is triggered by the clock signal and an impedance of the current path between the output nodes and the reference node of the clocked comparator depends on the relative voltages applied to the differential inputs of the clocked comparator. Operation of the current path circuitry is generally controlled by the clock signal. The impedance of the current path provided by the current path circuitry does not depend on the relative voltages applied to the differential inputs of the clocked comparator. In response to the clock signal, current flow through the current path circuitry may reduce a time interval between the clock signal and the clocked comparator entering the positive feedback phase. Thus, an enhanced slicer, consistent with the present disclosure, may be utilized in a relatively high frequency receiver without a decrease in sensitivity and/or without an increase in power consumption.

DFE circuitry may generally include summation node circuitry, a slicer, a set/reset (SR) latch and one or more additional (e.g., DFE) latches. The summation node circuitry is configured to combine (e.g., sum) an input signal and one or more tap outputs. Each tap output corresponds to a weighted prior decision. The weights are related to channel characteristics, e.g., channel bandwidth. An output of the summation node circuitry may then correspond to an equalized representation of the input signal. The output of the summation node circuitry may then be provided to the slicer and utilized for determining a current decision.

In some embodiments, the DFE circuitry may be configured to close at least some of a number of decision feedback loops onto a reference input signal (i.e., at a reference summation node) rather than onto a data input signal (i.e., at a data summation node). In one example, all of the decision feedback loops may be coupled to the reference summation node. In another example, some of the decision feedback loops may be coupled to the reference summation node and some of the decision feedback loops may be coupled to the data summation node.

Closing the feedback loop on the reference summation node is configured to reduce a load (e.g., parasitic capacitance) on the data input and to, thus, facilitate high-speed operation of the DFE circuitry. Gain penalties associated with closing the feedback loop on the data summation node may be avoided. Closing the feedback loop on the reference summation node may facilitate equalizing each eye of a multilevel modulation technique, e.g., four level pulse amplitude modulation PAM4. In other words, each voltage reference may be equalized separately, thus equalizing each eye independently. Thus, amplitude-dependent channel characteristics and/or receiver gain stages that are not linear may be accommodated.

Closing the feedback loop on the reference summation node, using current summation techniques, avoids bandwidth penalties that may be associated with closing the feedback loop on the data summation node. Closing the feedback loop on the reference summation node may be combined with other techniques, e.g., loop unrolling, cascaded summation nodes, integrated summation, etc.

Thus, relatively high data rates may be accommodated utilizing an enhanced slicer and/or closing a DFE feedback loop on a reference node.

FIG. 1Aillustrates a functional block diagram of a network system100consistent with several embodiments of the present disclosure. Network system100includes a source node102A, an end node102B and a communications link104. Each node102A,102B includes a respective network controller108A,108B. Each source node102A,102B includes respective other circuitry122A,122B that may include, for example, processor circuitry, memory, a network application, etc. (not shown), configured to communicate via network controllers108A,108B and communications link104.

Each network controller108A,108B includes a respective physical layer (PHY) circuitry110A,110B configured to interface the source node102A with the end node102B, via communications link104. PHY circuitry110A,110B may comply or be compatible with, an Institute of Electrical and Electronic Engineers (IEEE) 802.3™ Ethernet communications protocol, as described herein. As used herein, “Ethernet PHY” corresponds to PHY circuitry (e.g., PHY circuitry110A and/or110B) that complies and/or is compatible with one or more IEEE 802.3™ Ethernet communications protocols, as described herein. The IEEE 802.3™ Ethernet communication protocol may include, for example, single-lane PHY protocols such as 10GBASE-KX, 10GBASE-KR, etc., and/or multi-lane PHY protocols such as 10GBASE-KX4, 40GBASE-KR4, 40GBASE-CR4, 100GBASE-CR10, 100GBASE-CR4, 100GBASE-KR4, and/or 100GBASE-KP4, etc., and/or other PHY circuitry that is compliant with the IEEE 802.3™ Ethernet communications protocol and/or compliant with an after-developed communications protocol and/or emerging PHY technology specifications such as 25GBASE-CR and/or 25GBASE-KR, etc.

Each PHY circuitry110A,110B includes a respective transmit circuitry (Tx)112A,112B and a respective receive circuitry (Rx)114A,114B. Tx112A is configured to transmit data packets and/or frames to the end node102B, via link104, and receive circuitry114A is configured to receive data packets and/or frames from the end node102B, via link104. Similarly, Tx112B is configured to transmit data packets and/or frames to the source node102A, via link104, and Rx114B is configured to receive data packets and/or frames from the source node102A, via link104. Of course, each PHY circuitry110A,110B may also include encoding/decoding circuitry (not shown) configured to perform analog-to-digital and digital-to-analog conversion, encoding and decoding of data, analog parasitic cancellation (for example, cross talk cancellation), and recovery of received data. Each Rx114A,114B may include phase lock loop circuitry (PLL, not shown) configured to coordinate timing of data reception from the respective transmitting node102B,102A.

Source node102A and end node102B may each include respective ports120A,120B which define the number of lanes of the source node102A and end node102B, respectively. Each lane of the port120A,120B may include a plurality of logical and/or physical channels (e.g., differential pair channels) that provide separate connections between, for example, the Tx112A and Rx114A of the source node102A and the Rx114B and Tx112B, respectively, of the end node102B. A “single-lane link”, as used herein, is defined as a single Tx/Rx transmission pair. A “multi-lane link”, as used herein, is defined as two or more Tx/Rx transmission pairs. “Link width”, as used herein, refers to the number of lanes in the communication link. The PHY circuitry110A,110B of each network controller108A,108B may be duplicated, depending on the number of lanes associated with the respective port120A,120B. Thus for example, port120A may include a 4-lanes and the PHY circuitry110A may be compliant with 10GBASE-KX4, 40GBASE-KR4, 40GBASE-CR4, 100GBASE-CR4, 100GBASE-KR4, and/or 100GBASE-KP4.

FIG. 1Billustrates a functional block diagram of a communication system130, including a transmitter circuitry132, a channel134and a receiver circuitry136, consistent with several embodiments of the present disclosure. Transmitter circuitry132corresponds to Tx circuitry112A and/or112B ofFIG. 1B. Receiver circuitry136is one example of Rx circuitry114A and/or114B. Channel134may be included in communications link104. Thus, PHY circuitry110A and/or110B may contain receiver circuitry136and transmitter circuitry132, channel134and/or receiver circuitry136may comply and/or be compatible with one or more communication protocols, e.g., one or more IEEE 802.3™ standards, as described herein.

The transmitter circuitry132is configured to receive a serial data input, e.g., Bitstream In, to modulate the input serial data onto a carrier signal and to transmit the modulated data signal onto channel134. Channel134is configured to carry the data signal to receiver circuitry136. For example, channel134may include wire(s), printed circuit board trace(s), fiber-optic link(s), etc. Receiver circuitry136is configured to receive the data signal, to recover the transmitted data and to provide a serial data output, e.g., Bitstream out.

Transmitter circuitry132, channel134and/or receiver circuitry136may be configured to transmit, carry, and/or receive serial data at a data rate. For example, the data rate may be of on the order of 0.1, 1, 10 or 100 Gb per second. For example, the data rate may be greater than or equal to 25 Gb per second. In one example, the data rate may be 50 Gb per second. In another example, the data rate may be 100 Gb per second. In another example, the data rate may be less than 25 Gb per second.

Channel134may exhibit one or more non-ideal characteristics including, but not limited to, finite bandwidth, etc. Transmitter circuitry132, channel134and/or receiver circuitry136may also be susceptible to noise and/or introduce noise into the transmitted serial data, the modulated data signal and/or received serial data. The nonideal characteristics of the channel134may result in intersymbol interference in the data signal at the receiver136.

Receiver circuitry136may include front end equalization circuitry140, gain stage (variable gain amplifier (VGA)) circuitry142, clock and data recovery (CDR) circuitry144, reference source circuitry146and decision feedback equalization (DFE) circuitry150. The front end equalization circuitry140is configured to account for at least some nonideal channel characteristics. In other words, the front end equalization circuitry140is configured to filter the received data signal. For example, front end equalization circuitry140may include continuous time linear equalization (CTLE) circuitry. In another example, front end equalization circuitry140may include feedforward equalization (FFE) circuitry.

Gain stage circuitry142is configured to amplify the received data signal that is output from the front end equalization circuitry140. The received data signal output from the front end equalization circuitry140may be filtered. Gain stage circuitry142may include one or more variable gain amplifiers. Increasing the number of variable gain amplifiers may increase in the amount of gain (e.g., amplification) of gain stage circuitry142. Increasing the number of VGAs may increase a physical size and/or power consumption of receiver circuitry136. Clock and data recovery circuitry144is configured to recover a clock signal from the received serial data. Reference source circuitry146may include, e.g., a power supply (voltage or current) and/or ground. Reference source circuitry146is configured to provide a reference voltage (e.g., a non-zero voltage or ground) to DFE circuitry150. DFE circuitry150is configured to receive input data (e.g., a filtered and amplified input data stream) from VGA circuitry142, a reference signal from reference source circuitry146and the clock signal from CDR circuitry144. DFE circuitry150is further configured to provide an output, e.g., Bitstream out, that contains serial data recovered from the received serial data. The received serial data is related to the transmitted serial data.

FIG. 2illustrates decision feedback equalization (DFE) circuitry consistent200with several embodiments of the present disclosure. DFE circuitry200is one example of DFE circuitry150ofFIG. 1B. DFE circuitry200includes summation node circuitry202, slicer circuitry204, set/reset (SR) circuitry206and one or more DFE latches, e.g., latch circuitries208-1,208-2, . . . ,208-N. As used herein, the terms “slicer”, “clocked comparator”, “latch comparator” and “internal latch comparator” are used interchangeably. Slicer circuitry204may thus contain a comparator circuitry and a latch circuitry, as will be described in more detail below. An initial state of the slicer circuitry204may be a reset state. Slicer circuitry204compare and latch operations are triggered by a clock signal, CLK. For example, slicer circuitry204may contain a single stage latch comparator, e.g., a “strong arm” latch comparator. In another example, slicer circuitry204may contain a two stage latch comparator, e.g., a “double tail” latch comparator, that includes a first stage clocked comparator circuitry and a second stage clocked comparator circuitry.

Summation node circuitry202is configured to receive one or more outputs of one or more of latch circuitries208-1,208-2, . . . ,208-N. In some embodiments, summation node circuitry202may correspond to data summation node circuitry configured to receive input data, Data_in210and to output equalized data214, as will be described in more detail below. In these embodiments, slicer circuitry204may be configured to receive a reference in signal, Ref_in212. In some embodiments, summation node circuitry202may correspond to reference summation node circuitry configured to receive Ref_in212and to output an equalized reference216, as will be described in more detail below. In these embodiments, slicer circuitry204may be configured to receive Data_in210. In some embodiments, summation node circuitry202may include both data summation node circuitry and reference node circuitry, as will be described in more detail below. In these embodiments, slicer circuitry204may be configured to receive both equalized data214and equalized reference216.

Slicer circuitry204is further configured to receive a clock signal (CLK). Slicer circuitry204is configured to provide a differential slicer output218A,218B, that may be received by set/reset (SR) circuitry206. For example, SR circuitry206may correspond to a set/reset (SR) latch. SR circuitry206is configured to store a decision218that corresponds to the differential slicer output signal218A,218B. An output of SR circuitry206may then correspond to one bit of recovered data, e.g., one bit of Bitstream Out220.

Bitstream out220may be input to a first latch circuitry208-1and to summation node circuitry202. An output of the first latch circuitry208-1may be input to a second latch circuitry208-2and to summation node circuitry202, and so on to Nth latch circuitry208-N. Each latch circuitry208-1,208-2, . . . ,208-N is configured to temporarily store one output bit (i.e., decision). For example, SR circuitry206may store decision Do, latch circuitry208-1may store prior decision D−1, latch circuitry208-2may store prior decision D−2and so on to latch circuitry208-N that may store decision D−N. For each decision, the subscript corresponds to a prior decision index. Each stored output bit may then be provided to summation node circuitry202and utilized to mitigate intersymbol interference, as described herein.

In some embodiments, DFE200may include current path circuitry230coupled to slicer circuitry204. Thus, as used herein, the combination of slicer circuitry204and current path circuitry230corresponds to enhanced slicer circuitry. In these embodiments, DFE200may further include current path management circuitry232coupled to current path circuitry230, as will be described in more detail below.

FIG. 3illustrates an enhanced slicer circuitry300, consistent with several embodiments of the present disclosure. Enhanced slicer circuitry300includes a clocked comparator circuitry302and a current path circuitry304. Clocked comparator circuitry302is configured to receive a clock signal, CLK, and is coupled to reference voltages Vref_P and Vref_N. Clocked comparator circuitry302is configured to receive a differential input signal at input nodes In_P and In_N and to provide a differential output signal at output nodes Out_P and Out_N. In operation, if a voltage at In_P (Vin_P) is greater than a voltage at In_N (Vin_N) then, at steady-state, a voltage at Out_P (Vout_P) is configured to equal Vref_P and a voltage at Out_N (Vout_N) is configured to equal Vref_N. Conversely, if Vin_P is less than Vin_N then, at steady-state, output Vout_P is configured to equal Vref_N and output Vout_N is configured to equal Vref_P. For example, Vref_P may equal a positive supply voltage, Vcc, and Vref_N may correspond to a negative supply voltage, e.g., ground (i.e., zero Volts).

Current path circuitry304corresponds to current path circuitry230ofFIG. 2. Current path circuitry304includes parallel latch circuitry308and may include current path regulation circuitry306. Parallel latch circuitry308is coupled to enhanced slicer output nodes, Out_N and Out_P. Current path circuitry304is coupled to clock signal, CLK. Parallel latch circuitry308is coupled to CLK directly or, in some embodiments, via current path regulation circuitry306. Parallel latch circuitry308may be directly coupled to a reference node (Ref node) when current path regulation circuitry306is not present. In embodiments that include current path regulation circuitry306, parallel latch circuitry308may be coupled to Ref node via current path regulation circuitry306, as described herein.

Current path circuitry304is configured to provide an additional current path between at least one output node Out_P and/or Out_N, and Ref node. Current path circuitry304is configured to enhance the current flow between at least one output node Out_P and/or Out_N, and Ref node, in response to a clock signal, CLK. The additional current path is configured to reduce the time interval between receipt of a clock trigger and clocked comparator circuitry302entering the positive feedback phase. In other words, the additional current path is configured to speed up the transition of clocked comparator circuitry302from the reset state to the positive feedback phase, in response to the clock signal CLK.

In some embodiments, current path circuitry304may include current path regulation circuitry306. Current path regulation circuitry306is configured to regulate the enhanced current flow between the output node(s), Out_P and/or Out_N, and the reference node, Ref node. Current path regulation circuitry306is configured to be controllable and thus, the corresponding effect of current path circuitry304on the operation of enhanced slicer300may likewise be controllable, i.e., adjustable. For example, the control may correspond to voltage control, digital control and/or time-based control, as will be described in more detail below. In some embodiments, current path circuitry304may not include current path regulation circuitry306. In these embodiments, parallel latch circuitry308may be directly coupled to the reference node and the effect of current path circuitry304(e.g., enhanced current flow) on the operation of enhanced slicer300may be fixed.

Current path circuitry304is configured to provide a current path between the output nodes Out_P and Out_N and the Ref node that is relatively independent of the input voltages at the input nodes In_P and In_N. The current path circuitry304is configured to reduce a duration of a time interval between the clock signal CLK enabling clocked comparator circuitry302and the clocked comparator circuitry302entering a positive feedback phase. Decreasing the duration of this time interval is configured to decrease a decision time interval, e.g., a duration of a time interval between the clock trigger and a decision by enhanced slicer300.

FIGS. 4A, 4B and 4Cillustrate an example enhanced N-type slicer400, an example enhanced N-type low kickback slicer430and an example enhanced P-type slicer450, respectively, consistent with several embodiments of the present disclosure. The example enhanced slicers400,430,450are each respective examples of enhanced slicer300ofFIG. 3. The example enhanced low kickback N-type slicer430is configured to operate similar to the enhanced N-type slicer400with transistors M8and M9instead of transistor M7, as described herein. The example enhanced P-type slicer450is configured to operate similar to the enhanced N-type slicer400with the supply and ground nodes swapped and the polarity of the clock trigger opposite the polarity of the clock trigger in the N-type slicer400.

The example enhanced slicers400,430,450, utilize metal oxide semiconductor field effect transistors (MOSFETs). Of course, in other embodiments, other transistor technologies may be utilized to implement other enhanced slicers, consistent with the present disclosure. Other transistor technologies may include, but are not limited to, bipolar junction transistor (BJT) technologies (e.g., npn BJTs, pnp BJTs, heterojunction BJTs), other field effect transistor (FET) technologies (e.g., junction field effect transistors (JFETs), finFETs, insulated gate FETs (IGFETs), etc.), etc.

Turning first toFIG. 4A, the example enhanced N-type slicer400includes a single stage N-type clocked comparator circuitry402and current path circuitry404. N-type clocked comparator circuitry402includes two transistor switches, S1, S2. In this example, the transistor switches are P-type MOSFETs. A respective gate of each of transistors S1and S2is configured to receive the clock signal CLK. The sources of the two transistors are coupled to supply voltage Vcc (i.e., Vref_P). The drain of transistor S1is coupled to output node Out_N. The drain of transistor S2is coupled to output node Out_P.

N-type clocked comparator circuitry402further includes transistors M1, M2, M3, M4, M5, M6and M7. In this example, transistors M1, M2, M3, M4and M7are N-type MOSFETs and transistors M5and M6are P-type MOSFETs. A gate of transistor M1is coupled to input node In_P and a gate of transistor M2is coupled to input node In_N. The sources of transistors M1and M2are coupled to each other and to a drain of transistor M7. The gate of transistor M7is configured to receive the clock signal CLK and the source of transistor M7is coupled to ground (i.e., Vref_N). The drain of transistor M1is coupled to the source of transistor M3and the drain of transistor M2is coupled to the source of transistor M4. The gate of transistor M3is coupled to output node Out_P and the gate of transistor M4is coupled to output node Out_N. The drain of transistor M3is coupled to output node Out_N and the drain of transistor M4is coupled to output node Out_P.

The sources of transistors M5and M6are coupled to Vcc (i.e., Vref_P). The gate of transistor M5and the drain of transistor M6are coupled to each other and to output node Out_P. The gate of transistor M6and the drain of transistor M5are coupled to each other and to output node Out_N.

In operation, initially, N-type clocked comparator402and, thus, N-type enhanced slicer circuitry400may be in a reset state. For example, in the reset state, the clock signal, CLK, may be low, e.g., may be equal to zero. Switches S1and S2may thus be on, i.e., conducting, coupling Vcc to Out_N and Out_P. Transistors M5and M6may then be off, i.e., not conducting. Output nodes Out_N and Out_P may both be equal to a logic one, i.e., may be equal to supply voltage Vcc. In the reset state, transistor M7may be off, i.e., not conducting.

When the clock signal, CLK, transitions from low to high, switches S1and S2may then turn off, decoupling output nodes Out_N and Out_P from the supply voltage Vcc, and transistor M7may turn on coupling the sources of transistors M1and M2to ground. Transistor M2and/or transistor M1may begin to conduct when the voltage applied to the respective input node increases to greater than the threshold voltage of the respective transistor. If the voltage applied to input node In_N is greater than the voltage applied to input node In_P, transistor M2may begin to conduct before transistor M1conducts. When transistor M2begins to conduct, transistor M4may also conduct providing a current path between output node Out_P and ground. The current path may include transistors M4, M2and M7. As the voltage on output node Out_P decreases from Vcc toward ground, transistor M5may turn on when the voltage at output node Out_P minus the voltage at output node Out_N is more negative than the threshold voltage of transistor M5.

Similarly, if the voltage applied to input node In_P is greater than the voltage applied to input node In_N, transistor M1may begin to conduct before transistor M2conducts. When transistor M1begins to conduct, transistor M3may also conduct providing a current path between output node Out_N and ground. The current path may include transistors M3, M1and M7. As the voltage on output node Out_N decreases from Vcc toward ground, transistor M6may turn on when the voltage on output node Out_N minus the voltage on output node Out_P is more negative than the threshold voltage of transistor M6.

Thus, after N-type clocked comparator402is enabled (by CLK), the differential voltage across output nodes Out_P and Out_N may correspond to a decision of the clocked comparator402based, at least in part, on relative input voltages applied to input nodes In_P, In_N. Current path circuitry404, in this example, includes transistors M10, M11and M12. In this example, transistors M10, M11and M12are N-type MOSFETs. The sources of transistors M10and M11are coupled to each other and to the drain of transistor M12. The drain of transistor M10is coupled to output node Out_N and the drain of transistor M11is coupled to output node Out_P. The gate of transistor M10is coupled to output node Out_P and the gate of transistor M11is coupled to output node Out_N. The source of transistor M12is coupled to ground and the gate of transistor M12is coupled to CLK.

Current path circuitry404is one example of current path circuitry304ofFIG. 3. Current path circuitry404does not include current path regulation circuitry. In other words, current path circuitry404may be enabled by the clock signal CLK coupled to the gate of transistor M12. Unlike the paths between the output nodes and the reference node via transistors M3, M1and M7or transistors M4, M2and M7, the paths between the output nodes, Out_P, Out_N, and the reference node (e.g., ground) via current path circuitry404include only two transistors. The conductance of transistors M10and M11are controlled by the voltages Vout_P, Vout_N on the output nodes, Out_P, Out_N, referenced to ground. In other words, the conductances of the transistors M10and M11are not directly dependent on the input voltages, Vin_P, Vin_N. Thus, current path circuitry404is configured to provide a relatively low impedance path between at least one output node (Out_P, Out_N) and a reference node, e.g., ground, in response to a clock trigger. Current path circuitry404is configured to enhance the current flow between at least one output node Out_P and/or Out_N, and ground, in response to CLK.

Turning now toFIG. 4B, the example enhanced low kickback N-type slicer circuitry430includes a single stage N-type clocked low kickback comparator circuitry432and the current path circuitry404. The N-type clocked low kickback comparator circuitry432is one example of clocked comparator circuitry302ofFIG. 3. Clocked comparator circuitry432is similar to clocked comparator circuitry402ofFIG. 4A, with the following exceptions. The clocked N-type low kickback comparator432does not include transistor M7. The sources of transistors M1and M2are coupled to ground. Clocked N-type low kickback comparator circuitry432includes transistor M8coupled drain to source between transistors M2and M4and transistor M9coupled drain to source between transistors M1and M3. The gates of transistors M8and M9are coupled to the clock input CLK. Operation of enhanced low kickback slicer circuitry430, including current path circuitry404, is similar to operation of enhanced slicer circuitry400.

Turning now toFIG. 4C, the example enhanced P-type slicer450includes a single stage P-type clocked comparator circuitry452and a current path circuitry454. The clocked P-type comparator circuitry452is one example of clocked comparator circuitry302and the current path circuitry454is one example of current path circuitry304ofFIG. 3. In this example, current path circuitry454includes parallel latch circuitry but does not include current path regulation circuitry.

Current path circuitry454includes transistors M60, M61and M62. In this example, transistors M60, M61and M62are P-type MOSFETs. The drain of transistor M60is coupled to output node Out_N and the drain of transistor M61is coupled to output node Out_P. The sources of transistors M60and M61are coupled to each other and to the drain of transistor M62. The source of transistor M62is coupled to a reference node, e.g., supply voltage Vcc, and the gate of transistor M62is coupled to the clock input signal CLK. Similar to the N-type comparator circuitry452, current path circuitry454is configured to provide an additional current path between at least one output node and a reference node. In this case, the reference node corresponds to the supply voltage, Vcc. The additional current path is configured to decrease a time interval between receiving the clock trigger (e.g., the clock signal changing state) and the P-type clocked comparator circuitry452entering the positive feedback phase. Decreasing this time interval is configured to decrease a time interval between the clock trigger and a decision by enhanced slicer circuitry450. In other words, the conductances of the transistors M60and M61are not directly dependent on the voltages at input nodes In_P, In_N. Thus, current path circuitry454is configured to provide a relatively low impedance path to a reference node, e.g., ground, in response to a clock trigger. Current path circuitry454is configured to enhance the current flow between at least one output node Out_P and/or Out_N, and Vcc, in response to CLK.

Thus, example enhanced slicer circuitries400,430,450, including current path circuitries404,454, are configured to provide an additional current path between at least one output node, Out_P, Out_N, and a reference node. The current path circuitries404,454are configured to enhance the current flow between at least one output node Out_P and/or Out_N, and the reference node, in response to CLK. The additional current path is configured to decrease a time interval between receiving the clock trigger and the clocked comparator entering the positive feedback phase. Decreasing the duration of this time interval is configured to decrease a time interval between the clock trigger and a decision by example enhanced slicer circuitry400,430,450.

The respective current path circuitries404,434,454, ofFIGS. 4A, 4B, 4Ccorrespond to respective parallel latch circuitries. In other words, in the example enhanced slicer circuitries400,430,450, the respective current path circuitries404,434,454do not include current path regulation circuitry, as described herein. It should be noted that any of the current path circuitries404,434,454may be modified to include current path regulation circuitry, as described herein, within the scope of the present disclosure.

FIGS. 5A, 5B and 5Cillustrate three example current path circuitries504,534,554, including respective example current path regulation circuitries506,536,556, consistent with several embodiments of the present disclosure. Each example current path circuitry504,534,554is a respective example of current path circuitry304ofFIG. 3. Each example current path circuitry504,534,554is configured to enhance current flow between at least one output node, Out_N, Out_P, and a reference node. Each example current path circuitry504,534,554includes a respective example of current path regulation circuitry506,536,556. Each example current path regulation circuitry506,536,556is configured to regulate the enhanced current flow between at least one output node, Out_N, Out_P, and a reference node. Current path regulation circuitry506is one example of a voltage controlled current path regulation circuitry. Current path regulation circuitry536is one example of a digitally controlled current path regulation circuitry. Current path regulation circuitry556is one example of a time-based current path regulation circuitry.

An amount of current path regulation may be set in advance and/or may be adjusted during operation. In some embodiments, the amount of current path regulation may be set and/or adjusted based, at least in part, on one or more operational parameters including, but not limited to, data rate, bit error rate (BER), etc. For example, for relatively higher data rates, the current path regulation circuitry may be configured to pass a relatively higher current through the current path circuitry. In another example, for relatively lower data rates, the current path regulation circuitry may be configured to pass a relatively lower current through the current path circuitry. A relatively higher current may correspond to a relatively faster response (i.e., a relatively shorter TCO).

In some embodiments, the amount of current path regulation may be set for a given data rate based, at least in part, on a specified operating frequency of clocked comparator circuitry that is coupled to the current path circuitry. For example, for a relatively lower specified operating frequency, the current path regulation circuitry may be configured to pass a relatively higher current through the current path circuitry. In another example, for a relatively higher specified operating frequency, the current path regulation circuitry may be configured to pass a relatively lower current through the current path circuitry. Thus, variation in operating frequency may be accommodated.

Each current path circuitry504,534,554includes parallel latch circuitry508and the respective current path regulation circuitry506,536,556, respectively. The parallel latch circuitry508is configured to be coupled to output nodes Out_P, Out_N of a clocked comparator, as described herein. Each current path regulation circuitry506,536,556is a respective example of current path regulation circuitry306ofFIG. 3. The parallel latch circuitry508includes three transistors M10, M11and M12that are configured to provide an additional current path between at least one output node and a reference node, as described herein.

The example current path circuitry504,534,554, are illustrated with MOSFETs. Of course, in other embodiments, other transistor technologies may be utilized to implement current path circuitry, consistent with the present disclosure. Other transistor technologies may include, but are not limited to, BJT technologies (e.g., npn BJTs, pnp BJTs, heterojunction BJTs), other FET technologies (e.g., JFETs, finFETs, IGFETs, etc.), etc.

Turning first toFIG. 5A, current path regulation circuitry506includes transistor M13. A drain of transistor M13is coupled to a source of transistor M12and a source of transistor M13is coupled to ground (i.e., reference node). A gate of transistor M13is configured to receive a control input signal, control_in. The gate of transistor M13may be coupled to, for example, current path management circuitry232ofFIG. 2. Control_in may then correspond to a controlled bias signal (e.g., a voltage) configured to control the bias on transistor M13and to thus, increase, decrease or eliminate current flow through current path circuitry504. Current path management circuitry232may be configured to control the bias voltage applied to the gate of transistor M13. For example, for an N-type transistor (M13), Control_in may be set to a relatively higher voltage (i.e., increased current through current path circuitry504) when sampling at higher frequencies (i.e., lower TCO). In another example, for an N-type transistor (M13), Control_in may be set to a relatively lower voltage, and thus a relatively lower current may flow through current path circuitry504at relatively lower frequencies.

Turning now toFIG. 5B, current path regulation circuitry536includes three additional transistors M20, M21and M22. In some embodiments, current path circuitry534may include more than three additional transistors or fewer than three additional transistors. The drains of the additional transistors M20, M21and M22are coupled to the source of transistor M12. The sources of the additional transistors M20, M21, M22are coupled to ground (i.e., Ref node). The respective gate of each additional transistor M20, M21, M22is coupled to a respective digital input signal. The respective digital input signals may be provided by, for example, current path management circuitry232ofFIG. 2. Control_in may then correspond to the digital input signals provided to the gates of the additional transistors M20, M21, M22. The digital input signals may correspond to respective enable bits. For example, enabling all of the additional transistors M20, M21, M22is configured to turn the transistors M20, M21, M22on (i.e., conducting) and may thus correspond to a maximum current flow through current path circuitry534. In another example, disabling all of the additional transistors M20, M21, M22may correspond to zero current flow through current path circuitry534. In another example, enabling some of the additional transistors may correspond to a current flow that is greater than zero and less than the maximum current flow through current path circuitry534.

Thus, current path circuitry534may be digitally controlled. For example, for relatively low frequency input data signals, none or fewer than all of the transistors M20, M21and M22may be enabled. Thus, current flow through current path circuitry534may be decreased or eliminated when an enhanced slicer that includes current path circuitry534is enabled. In another example, for relatively high frequency input data signals, all or nearly all of the transistors M20, M21, M22may be enabled, increasing current flow through current path circuitry534, when the enhanced slicer is enabled.

Turning now toFIG. 5C, current path regulation circuitry556is one example of time-based control. Current path regulation circuitry556corresponds to an adjustable delay circuitry. The gate of transistor M12is coupled to the clock signal, CLK, through the adjustable delay circuitry556. Control_in may then correspond to the delay associated with the clock input signal to transistor M12. Adjusting the delay on the clock input signal CLK is configured to adjust a corresponding impact of current path circuitry554on operation of an enhanced slicer circuitry that includes current path circuitry554. The delay on the clock input signal is related to the impact of the current path circuitry554on the decision. A relatively longer delay may correspond to a relatively smaller impact on the decision compared to a relatively shorter delay. In other words, a relatively shorter delay corresponds to a relatively longer time for current to flow through current path circuitry554and a relatively longer delay corresponds to a relatively shorter time for current to flow through current path circuitry554. For example, for a relatively higher frequency data signal, the delay may be relatively short, e.g., at or near zero. In another example, or a relatively lower frequency data signal, the delay may be relatively longer.

An enhanced slicer circuitry may thus include any combination of controllable current path circuitry504,534,554and clocked comparator circuitry, as described herein. Thus, current path regulation circuitries506,536and556illustrate examples of voltage control, digital control and time-based control, respectively.

FIG. 6illustrates one example multistage enhanced slicer600that includes current path circuitry604consistent with several embodiments of the present disclosure. Multistage slicer600includes a first stage clocked comparator circuitry602and a second stage clocked comparator circuitry610. The first stage clocked comparator circuitry602and second stage clocked comparator circuitry610, together, may correspond to a double tail topology, as described herein.

The first stage clocked comparator circuitry602is coupled to current path circuitry604. The first stage clocked comparator circuitry602and current path circuitry604correspond to enhanced slicer circuitry400ofFIG. 4A. In other words, the first stage clocked comparator circuitry602corresponds to clocked comparator circuitry402and current path circuitry604corresponds to current path circuitry404ofFIG. 4A. It may be appreciated the current path circuitry604may be replaced with any one of current path circuitries504,534or554ofFIGS. 5A, 5B, 5C, respectively. In other words, current path circuitry604may be configured to provide a fixed or controllable current path, as described herein.

The output nodes Out_N_first_stage and Out_P_first_stage of the first stage clocked comparator circuitry602are coupled to input nodes of the second stage clocked comparator circuitry610. The second stage clocked comparator circuitry610includes two switches S61, S62and five transistors M61, M62, M63, M64, M65. The gate of each switch S61and S62is coupled to a respective output node of the first stage clocked comparator circuitry602, Out_N_first_stage and Out_P_first_stage. The sources of switches S61and S62are coupled to a voltage supply, Vss. The drain of switch S61is coupled to a second stage first output node Out_P_second_stage. The drain of switch S62is coupled to a second stage second output node Out_N_second_stage. Transistors M63and M64are N-type transistors. The sources of transistors M63and M64are coupled to voltage supply, Vss. A drain of transistor M63is coupled to output node Out_P_second stage and a drain of transistor M64is coupled to output node Out_N_second_stage. A gate of transistor M64is coupled to output node, Out_P_second stage. A gate of transistor M63is coupled to output node, Out_N_second_stage.

Transistors M61, M62and M65are P-type transistors. The gate of transistor M62is coupled to Out_P_second_stage and the gate of transistor M61is coupled to Out_N_second_stage. The drain of transistor M61is coupled to Out_P_second_stage and the drain of transistor M62is coupled to Out_N_second_stage. The sources of transistors M61and M62are coupled to each other and to the source of transistor M65. The drain of transistor M65is coupled to voltage supply, Vcc, and the gate of transistor M65is coupled to the clock signal CLK.

Thus, current path circuitry, e.g., current path circuitry604, may be included in a multistage enhanced slicer. In one example, current path circuitry may be coupled to the first stage outputs, Out_N_first_stage, Out_P_first_stage. In another example, current path circuitry may be coupled to the second stage outputs, Out_N_second_stage, Out_P_second_stage. In another example, a first current path circuitry may be coupled to the first stage outputs, Out_N_first_stage, Out_P_first_stage and a second current path circuitry may be coupled to the second stage outputs, Out_N_second_stage, Out_P_second_stage.

FIG. 7illustrates a decision feedback equalization (DFE) circuitry700consistent with several embodiments of the present disclosure. DFE circuitry700is one example of DFE circuitry150ofFIG. 1B. DFE circuitry700is configured to receive a differential reference input, Ref_in712, and a differential data input, Data_in710. Ref_in712may be output of a gain stage722. Data_in710is output from a gain stage720that may include one or more variable gain amplifiers (VGAs). Gain stage720is one example of gain stage circuitry142ofFIG. 1B.

DFE circuitry700includes a slicer704, a set/reset (SR) latch706and one or more other (i.e., DFE) latches708-1, . . . ,708-N. In some embodiments, slicer704may correspond to an enhanced slicer, as described herein. DFE circuitry700may include a reference summation node circuitry702A and/or a data summation node circuitry702B, as will be described in more detail below. Summation node circuitry702A and/or702B is/are configured to sum an input signal and at least one weighted prior decision, as will be described in more detail below. In an embodiment, summation node circuitry702A and/or summation node circuitry702B correspond(s) to current summation node circuitry configured to sum a plurality of electrical currents.

In some embodiments, DFE circuitry700may include the reference summation node circuitry702A and may not include the data summation node circuitry702B. In these embodiments, slicer704is configured to receive an equalized reference input, Eq_ref718from reference summation node circuitry702A. Slicer704may be further configured to receive the data input, Data_in710. In these embodiments, all of the decisions, i.e., all of the outputs, from SR latch706and latches708-1, . . . ,708-N may be fed back to the reference summation node circuitry702A. Reference summation node702A may then be configured to sum the reference input signal Ref_in712and one or more weighted prior decisions output from SR latch706and one or more DFE latches708-1, . . . ,708-N. Reference summation node702A may then be configured to output an equalized reference signal, Eq_ref718. The output equalized reference signal, Eq_ref718may the correspond to a slicer reference input.

In some embodiments, DFE circuitry700may include the data summation node circuitry702B and may not include the reference summation node circuitry702A. In these embodiments, slicer704is configured to receive an equalized data input, Eq_data716. Slicer704may be further configured to receive the reference input, Ref_in712. In these embodiments, all of the decisions, i.e., all of the outputs, from SR latch706and latches708-1, . . . ,708-N may be fed back to the data summation node circuitry702B. Data summation node702B may then be configured to sum the data input signal Data_in710and one or more weighted prior decisions output from SR latch706and one or more DFE latches708-1, . . . ,708-N. Data summation node702B may then be configured to output an equalized data signal, Eq_data716. The output equalized data signal, Eq_data716may then correspond to a slicer data input.

In some embodiments, DFE circuitry700may include both the reference summation node circuitry702A and the data summation node circuitry702B. In these embodiments, slicer704is configured to receive Eq_data716and Eq_ref718. In these embodiments, a first portion, i.e., some of the outputs from SR latch706and latches708-1, . . . ,708-N may be fed back to the reference summation node circuitry702A and a second portion of the outputs from SR latch706and latches708-1, . . . ,708-N may be fed back to the data summation node circuitry702B. In these embodiments, the first portion and the second portion may not overlap, i.e., may not include a same output from SR latch706and latches708-1, . . . ,708-N. The combination of the first portion and the second portion are configured to include all of the outputs from SR latch706and latches708-1, . . . ,708-N. Reference summation node702A may then be configured to sum the reference input signal Ref_in712and one or more weighted prior decisions output from SR latch706and/or one or more DFE latches708-1, . . . ,708-N. Data summation node702B may then be configured to sum the data input signal Data_in710and one or more weighted prior decisions output from SR latch706and one or more DFE latches708-1, . . . ,708-N. Reference summation node702A may then be configured to output an equalized reference signal, Eq_ref718and data summation node702B may then be configured to output an equalized data signal, Eq_data716. The output equalized reference signal, Eq_ref718may then correspond to a slicer reference input and the output equalized data signal, Eq_data716may then correspond to a slicer data input.

Each summation node circuitry702A,702B includes a respective differential amplifier circuitry703A,703B and one or more taps A0, A1, . . . , AN and B0, B1, . . . , BM, respectively. Reference differential amplifier703A includes two reference transistors (e.g., MOSFETs) Q1A and Q2A, a reference current source, Iref, and two resistors R1A, R2A. Respective gates of the reference transistors Q1A, Q2A are coupled to the differential reference input, Ref_in712. Sources of the reference transistors Q1A, Q2A are coupled to the reference current source Iref. Respective drains of the reference transistors Q1A, Q2A are coupled to a supply voltage Vcc via respective resistors R1A, R2A. A first reference summation current, I1A, through resistor R1A and a second reference summation current, I2A, through resistor R2A are related to Ref_in and the decisions stored to one or more of SR706and latches708-1, . . . ,708-N. The output, Eq_ref718, of reference summation node circuitry702A is related to a difference between I1A and I2A. Each reference tap A0, A1, . . . , AN may be coupled to a respective output of SR latch706and latches708-1, . . . ,708-N. For example, reference tap A0may be coupled to the output of SR latch706, reference tap A1may be coupled to an output of latch708-1and reference tap AN may be coupled to an output of latch708-N. Each reference tap A0, A1. . . , AN includes two reference tap transistors, a reference tap current source and a reference tap inverter. For example, reference tap A0includes two reference tap transistors Q10A, Q20A, a reference tap current source IA0, and a reference tap inverter D1A. A gate of the first reference tap transistor Q10A is coupled to an output of the reference tap inverter D1A. An input of the reference tap inverter D1A is coupled to a gate of the second reference tap transistor Q20A and the output of SR latch706. The sources of the reference tap transistors Q10A, Q20A are coupled to the reference tap current source IA0. Respective drains of the reference tap transistors Q10A, Q20A are coupled to respective drains of reference transistors Q1A, Q2A.

A value of a reference tap current provided by each reference tap current source corresponds to a tap weight and may be related to channel characteristics. Each reference tap is configured to add a corresponding reference tap current to, or subtract the corresponding reference tap current from, the reference differential amplifier703A output. Whether the corresponding reference tap current is added or subtracted is related to the contents of respective latches706,708-1, . . . ,708-N, i.e., is related to the decision value stored by each respective latch. Thus, for R1A=R2A=R, Eq_ref is equal to R*(I1A−I2A) where I1A includes contributions from latches storing logic zeros and I2A includes contributions from latches storing logic ones. Whether I1A or I2A includes a contribution from reference current Iref is related to Ref_in712. If Ref_in712is positive, then Iref may be included in I1A and if Ref_in712is negative, then Iref may be included in I2A. The differential output of reference summation node circuitry702A may then correspond to the equalized reference, Eq_ref718.

Similarly, for data summation node circuitry702B, data differential amplifier703B includes two data transistors (e.g., MOSFETs) Q1B and Q2B, a data current source, Idata, and two resistors R1B, R2B. Respective gates of the data transistors Q1B, Q2B are coupled to the differential data input, Data_in710. Sources of the data transistors Q1B, Q2B are coupled to the data current source Idata. Respective drains of the data transistors Q1B, Q2B are coupled to a supply voltage Vcc via respective resistors R1B, R2B. A first data summation current, I1B, through resistor R1B and a second data summation current, I2B, through resistor R2B are related to Data_in and the decisions stored to one or more of SR706and latches708-1, . . . ,708-N. The output, Eq_data716, of data summation node circuitry702B is related to a difference between I1B and I2B.

Each data tap B0, B1, . . . , BM may be coupled to a respective output of SR latch706and latches708-1, . . . ,708-N. For example, data tap B0may be coupled to the output of SR latch706, data tap B1may be coupled to an output of latch708-1, etc. Each data tap B0, B1, . . . , BM includes two data tap transistors, a data tap current source and a data tap inverter. For example, data tap B0includes two data tap transistors Q10B, Q20B, a data tap current source IB0and a data tap inverter D1B. A gate of the first data tap transistor Q10B is coupled to an output of the data tap inverter D1B. An input of the data tap inverter D1B is coupled to a gate of the second data tap transistor Q20B and the output of SR latch706. The sources of the data tap transistors Q10B, Q20B are coupled to the data tap current source IB0. Respective drains of the data tap transistors Q10B, Q20B are coupled to respective drains of data transistors Q1B, Q2B.

A value of a data tap current provided by each data tap current source corresponds to a tap weight and may be related to channel characteristics. Each data tap is configured to add a corresponding data tap current to, or subtract the corresponding data tap current from, the data differential amplifier703B output. Whether the corresponding data tap current is added or subtracted is related to the contents of respective latches706,708-1, . . . ,708-N, i.e., is related to the decision value stored by each respective latch. Thus, for R1B=R2B=R, Eq_data is equal to R*(I1B−I2B) where I1B includes contributions from latches storing logic zeros and I2B includes contributions from latches storing logic ones. Whether I1B or I2B includes a contribution from data current Idata is related to Data_in710. If Data_in710is positive, then Idata may be included in I1B and if Data_in710is negative, then Idata may be included in I2B. The differential output of data summation node circuitry702B may then correspond to the equalized data, Eq_data716.

The reference tap currents, e.g., reference tap current IA0, and the data tap currents, e.g., data tap current IB0, correspond to tap weights and are related to channel characteristics, as described herein. Each tap weight corresponds to a respective post-cursor, i.e., a previously received symbol. It may be appreciated that, a sign, i.e., polarity, of a selected tap weight is related to whether the corresponding tap current is a data tap current or a reference tap current. In other words, adding a reference tap current to an equalized reference is equivalent to subtracting a corresponding data tap current from equalized data. Thus, a selected feedback loop from an output of SR latch706or a respective one of latches708-1, . . . ,708-N, may be closed onto reference summation node circuitry702A or data summation node circuitry702B with a same magnitude of selected tap weight but an opposite polarity.

In operation, slicer704is configured to compare a slicer data input to a slicer reference input and to output a first voltage to the S (set) input of SR latch706and a second voltage to the R (reset) input of the SR latch706, in response to the clock signal CLK. Initially, slicer704may be in a reset state and may be configured to output a supply voltage, Vcc, to both the S input and the R input of SR latch706. SR latch706may be configured to not change state in response to a clock signal when both the S input and the R input are receiving the supply voltage, Vcc. In this manner, SR latch706may serve as a “memory” element for DFE700.

If the slicer data input is greater than the slicer reference input, then slicer704may be configured to output the supply voltage, Vcc, onto the S input of the SR latch706and a reference voltage, e.g., zero volts, on to the R input of the SR latch706. Conversely, if the slicer data input is less than the slicer reference input, then slicer704may be configured to output the reference voltage on to the S input of the SR latch706and the supply voltage, Vcc, on to the R input of the SR latch706. In response to the clock signal, the SR latch706may then be configured to store a decision. Thus, if the S input of SR latch706is coupled to the supply voltage and the R input is coupled to the reference voltage, then the decision and corresponding output, Data out, may be a logic one and if the S input of SR latch706is coupled to the reference voltage and the R input is coupled to the supply voltage, then the decision and corresponding output, Data out, may be a logic zero.

In the embodiments that include reference summation node circuitry702A, the slicer reference input corresponds to the equalized reference, Eq_ref718. In the embodiments that include data summation node circuitry702B, the slicer input corresponds to the equalized data, Eq_data716. In the embodiments that do not include reference summation node circuitry702A, the slicer reference input corresponds to Ref_in712. In the embodiments that do not include data summation node circuitry702B, the slicer data input corresponds to Data_in710.

Thus, DFE circuitry700may be configured to receive a reference input, Ref_in712, and a data input, Data_in710and to equalize the data input and/or the reference input. DFE circuitry700may be further configured to compare the equalized data input to the reference input, to compare the data input to the equalized reference input or to compare the equalized data input to the equalized reference input, (i.e., to make a decision) and to output the result of the comparison, i.e., Data out. Closing at least a portion of the feedback loops on to reference summation node circuitry702A is configured to reduce a load on the data input and to, thus, facilitate high speed operation of DFE circuitry700.

FIG. 8is a plot800illustrating a comparison of slicer and SR latch outputs for example slicers, with and without current path circuitry. The horizontal axis is time in picoseconds and the vertical axis is voltage. Waveforms802nand802pcorrespond to a differential clock signal (e.g., CLK) in volts and include a sample phase803A and a reset phase803B. Waveforms804nand804pcorrespond to enhanced slicer differential outputs for, e.g., enhanced slicer400ofFIG. 4A, and waveforms805nand805pcorrespond to slicer differential outputs for a strong arm slicer, as described herein. The slicer outputs are in millivolts. Waveforms806nand806pcorrespond to SR latch differential outputs for enhanced slicer outputs804nand804pand waveforms807nand807pcorrespond to SR latch differential outputs for slicer outputs805nand805p. The SR latch outputs are in millivolts.

Thus, an enhanced slicer and/or decision feedback equalization (DFE) circuitry have been described herein. The DFE circuitry includes a slicer that may or may not be enhanced. An enhanced slicer corresponds to a clocked comparator coupled to current path circuitry. The current path circuitry is configured to enhance current flow between at least one output node of the clocked comparator and a reference node (i.e., a supply voltage or ground) of the clocked comparator, in response to a clock signal.

In some embodiments, the DFE circuitry may be configured to close at least some of a number of decision feedback loops onto a reference input signal (i.e., at a reference summation node) rather than onto a data input signal (i.e., at a data summation node). In one example, all of the decision feedback loops may be coupled to the reference summation node. In another example, some of the decision feedback loops may be coupled to the reference summation node and some of the decision feedback loops may be coupled to the data summation node.

Closing the feedback loop on the reference summation node is configured to reduce a load (e.g., parasitic capacitance) on the data input and to, thus, facilitate high-speed operation of the DFE circuitry. Gain penalties associated with closing the feedback loop on the data summation node may be avoided. Closing the feedback loop on the reference summation node may facilitate equalizing each eye of a multilevel modulation technique, e.g., four level pulse amplitude modulation PAM4. In other words, each voltage reference may be equalized separately, thus equalizing each eye independently. Thus, amplitude-dependent channel characteristics and/or receiver gain stages that are not linear may be accommodated.

“Circuitry,” as used in any embodiment herein, may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, logic and/or firmware that stores instructions executed by programmable circuitry. The circuitry may be embodied as an integrated circuit, such as an integrated circuit chip.

Network controller108A,108B, PHY circuitry110A,110B, Tx112A,112B, Rx114A,114B, communications link104, transmitter circuitry132, channel134and/or receiver circuitry136may be capable of communicating using a selected network communications protocol. One example communications protocol may include an Ethernet communications protocol. The Ethernet protocol may comply or be compatible with an Ethernet standard published by the Institute of Electrical and Electronics Engineers (IEEE), for example, the IEEE standard Std 802.3™-2015, titled “IEEE Standard for Ethernet”, published September 2015 and/or earlier (e.g., IEEE Std 802.3™-2012) and/or later and/or related versions of this standard, e.g., an after-developed communication protocol and/or emerging PHY technology specification such as IEEE 802.3bs™ “Standard for Ethernet Amendment: Media Access Control Parameters, Physical Layers and Management Parameters for 200 Gb/s and 400 Gb/s Operation” and/or IEEE 802.3cd™ related to 50 Gb/s Ethernet over a Single Lane and Next Generation 100 Gb/s and 200 Gb/s.

In some embodiments, a hardware description language (HDL) may be used to specify circuit and/or logic implementation(s) for the various logic and/or circuitry described herein. For example, in one embodiment the hardware description language may comply or be compatible with a very high speed integrated circuits (VHSIC) hardware description language (VHDL) that may enable semiconductor fabrication of one or more circuits and/or logic described herein. The VHDL may comply or be compatible with IEEE Standard 1076-1987, IEEE Standard 1076.2, IEEE1076.1, IEEE Draft 3.0 of VHDL-2006, IEEE Draft 4.0 of VHDL-2008 and/or other versions of the IEEE VHDL standards and/or other hardware description standards.

In some embodiments, a Verilog hardware description language (HDL) may be used to specify circuit and/or logic implementation(s) for the various logic and/or circuitry described herein. For example, in one embodiment, the HDL may comply or be compatible with IEEE standard 62530-2011: SystemVerilog—Unified Hardware Design, Specification, and Verification Language, dated Jul. 7, 2011; IEEE Std 1800™-2012: IEEE Standard for SystemVerilog-Unified Hardware Design, Specification, and Verification Language, released Feb. 21, 2013; IEEE standard 1364-2005: IEEE Standard for Verilog Hardware Description Language, dated Apr. 18, 2006 and/or other versions of Verilog HDL and/or SystemVerilog standards.

EXAMPLES

Examples of the present disclosure include subject material such as a method, means for performing acts of the method, a device, or of an apparatus or system related to a slicer and/or decision feedback equalization circuitry, as discussed below.

According to this example, there is provided an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

This example includes the elements of example 1, wherein the current path circuitry includes a parallel latch circuitry coupled to the output nodes and the reference node.

This example includes the elements of example 1, wherein the current path circuitry includes a parallel latch circuitry and a current path regulation circuitry, the parallel latch circuitry coupled to the output nodes and the current path regulation circuitry to regulate the enhanced current flow.

This example includes the elements of example 3, wherein the current path regulation circuitry is selected from the group including voltage controlled current path regulation circuitry, digitally controlled current path regulation circuitry or time-based current path regulation circuitry.

This example includes the elements according to any one of examples 1 through 3, wherein the current path circuitry includes transistors selected from the group including N-type metal oxide semiconductor field effect transistors (MOSFETs), P-type MOSFETs, npn bipolar junction transistors (BJTs), pnp BJTs, heterojunction BJTs, junction field effect transistors (JFETs), finFETs, insulated gate FETs (IGFETs).

This example includes the elements according to any one of examples 1 through 3, wherein the current path circuitry includes N-type metal oxide semiconductor field effect transistors (MOSFETs) or P-type MOSFETs.

This example includes the elements according to any one of examples 1 through 3, wherein the first clocked comparator circuitry is selected from the group including N-type clocked comparator circuitry, N-type low kickback clocked comparator circuitry and P-type clocked comparator circuitry.

This example includes the elements according to any one of examples 1 through 3, further including a second clocked comparator circuitry coupled to Out_P and Out_N, the first clocked comparator circuitry corresponding to a first stage and the second clocked comparator circuitry corresponding to a second stage.

According to this example, there is provided a decision feedback equalizer (DFE). The DFE includes a summation node circuitry; an enhanced slicer circuitry; a set/reset (SR) circuitry; and at least one DFE latch circuitry. The enhanced slicer circuitry includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

This example includes the elements of example 9, wherein the current path circuitry includes a parallel latch circuitry coupled to the output nodes and the reference node.

This example includes the elements of example 9, wherein the current path circuitry includes a parallel latch circuitry and a current path regulation circuitry, the parallel latch circuitry coupled to the output nodes and the current path regulation circuitry to regulate the enhanced current flow.

This example includes the elements of example 9, wherein the summation node circuitry includes a reference summation node circuitry to sum a reference input signal and one or more weighted prior decisions.

This example includes the elements of example 11, wherein the current path regulation circuitry is selected from the group including voltage controlled current path regulation circuitry, digitally controlled current path regulation circuitry or time-based current path regulation circuitry.

This example includes the elements according to any one of examples 9 through 12, wherein the summation node circuitry includes data summation node circuitry.

This example includes the elements according to any one of examples 9 through 12, wherein the current path circuitry includes transistors selected from the group including N-type metal oxide semiconductor field effect transistors (MOSFETs), P-type MOSFETs, npn bipolar junction transistors (BJTs), pnp BJTs, heterojunction BJTs, junction field effect transistors (JFETs), finFETs, insulated gate FETs (IGFETs).

This example includes the elements according to any one of examples 9 through 12, wherein the current path circuitry includes N-type metal oxide semiconductor field effect transistors (MOSFETs) or P-type MOSFETs.

This example includes the elements according to any one of examples 9 through 12, wherein the first clocked comparator circuitry is selected from the group including N-type clocked comparator circuitry, N-type low kickback clocked comparator circuitry and P-type clocked comparator circuitry.

This example includes the elements according to any one of examples 9 through 12, wherein the enhanced slicer further includes a second clocked comparator circuitry coupled to Out_P and Out_N, the first clocked comparator circuitry corresponding to a first stage and the second clocked comparator circuitry corresponding to a second stage.

This example includes the elements according to any one of examples 9 through 12, wherein the summation node circuitry corresponds to current summation node circuitry.

According to this example, there is provided a receiver. The receiver includes a gain stage circuitry; a clock and data recovery circuitry; a reference source circuitry; and a decision feedback equalizer (DFE) circuitry. The DFE circuitry includes a summation node circuitry; an enhanced slicer circuitry; a set/reset (SR) circuitry; and at least one DFE latch circuitry. The enhanced slicer circuitry includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

This example includes the elements of example 20, wherein the current path circuitry includes a parallel latch circuitry coupled to the output nodes and the reference node.

This example includes the elements of example 20, wherein the current path circuitry includes a parallel latch circuitry and a current path regulation circuitry, the parallel latch circuitry coupled to the output nodes and the current path regulation circuitry to regulate the enhanced current flow.

This example includes the elements of example 20, wherein the summation node circuitry includes a reference summation node circuitry to sum a reference input signal and one or more weighted prior decisions.

This example includes the elements of example 22, wherein the current path regulation circuitry is selected from the group including voltage controlled current path regulation circuitry, digitally controlled current path regulation circuitry or time-based current path regulation circuitry.

This example includes the elements according to any one of examples 20 through 23, wherein the summation node circuitry includes data summation node circuitry.

This example includes the elements according to any one of examples 20 through 23, wherein the current path circuitry includes transistors selected from the group including N-type metal oxide semiconductor field effect transistors (MOSFETs), P-type MOSFETs, npn bipolar junction transistors (BJTs), pnp BJTs, heterojunction BJTs, junction field effect transistors (JFETs), finFETs, insulated gate FETs (IGFETs).

This example includes the elements according to any one of examples 20 through 23, wherein the current path circuitry includes N-type metal oxide semiconductor field effect transistors (MOSFETs) or P-type MOSFETs.

This example includes the elements according to any one of examples 20 through 23, wherein the first clocked comparator circuitry is selected from the group including N-type clocked comparator circuitry, N-type low kickback clocked comparator circuitry and P-type clocked comparator circuitry.

This example includes the elements according to any one of examples 20 through 23, wherein the enhanced slicer further includes a second clocked comparator circuitry coupled to Out_P and Out_N, the first clocked comparator circuitry corresponding to a first stage and the second clocked comparator circuitry corresponding to a second stage.

This example includes the elements according to any one of examples 20 through 23, wherein the summation node circuitry corresponds to current summation node circuitry.

This example includes the elements according to any one of examples 20 through 23, wherein the receiver further includes front end equalizer circuitry.

According to this example, there is provided a method. The method includes comparing, by a first clocked comparator circuitry, a slicer data input and a slicer reference input. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The method further includes enhancing, by a current path circuitry, a current flow between at least one of the output nodes and the reference node. The current path circuitry is coupled to the output nodes and the reference node. The enhancing is in response to a clock signal.

This example includes the elements of example 32, wherein the current path circuitry includes a parallel latch circuitry coupled to the output nodes and the reference node.

This example includes the elements of example 32, further including regulating, by a current path regulation circuitry, the enhanced current flow.

This example includes the elements of example 32, further including summing by a summation node circuitry, an input signal and at least one weighted prior decision and outputting, by the summation node circuitry, at least one of the slicer data input and/or the slicer reference input.

This example includes the elements of example 34, wherein the current path regulation circuitry is selected from the group including voltage controlled current path regulation circuitry, digitally controlled current path regulation circuitry or time-based current path regulation circuitry.

This example includes the elements of example 35, wherein the summation node circuitry includes at least one of a reference summation node circuitry and/or a data summation node circuitry.

This example includes the elements of example 32, wherein the current path circuitry includes transistors selected from the group including N-type metal oxide semiconductor field effect transistors (MOSFETs), P-type MOSFETs, npn bipolar junction transistors (BJTs), pnp BJTs, heterojunction BJTs, junction field effect transistors (JFETs), finFETs, insulated gate FETs (IGFETs).

This example includes the elements of example 32, wherein the current path circuitry includes N-type metal oxide semiconductor field effect transistors (MOSFETs) or P-type MOSFETs.

This example includes the elements of example 32, wherein the first clocked comparator circuitry is selected from the group including N-type clocked comparator circuitry, N-type low kickback clocked comparator circuitry and P-type clocked comparator circuitry.

This example includes the elements of example 32, wherein the enhanced slicer further includes a second clocked comparator circuitry coupled to Out_P and Out_N, the first clocked comparator circuitry corresponding to a first stage and the second clocked comparator circuitry corresponding to a second stage.

This example includes the elements of example 32, wherein the summation node circuitry corresponds to current summation node circuitry.

This example includes the elements of example 32, further including recovering, by a clock and data recovery circuitry, the clock signal from received serial data.

According to this example, there is provided a decision feedback equalizer (DFE). The DFE includes a summation node circuitry; a slicer circuitry; a set/reset (SR) circuitry; and at least one DFE latch circuitry. The summation node circuitry includes a reference summation node circuitry to sum a reference input signal and one or more weighted prior decisions.

This example includes the elements of example 44, wherein the summation node circuitry further includes a data summation node circuitry.

This example includes the elements of example 44, wherein the summation node circuitry corresponds to current summation node circuitry.

This example includes the elements according to any one of examples 44 to 46, wherein the slicer circuitry includes a first clocked comparator circuitry, the first clocked comparator circuitry including a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N); and a current path circuitry coupled to the output nodes and a reference node, the current path circuitry to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

This example includes the elements of example 47, wherein the current path circuitry includes a parallel latch circuitry coupled to the output nodes and the reference node.

This example includes the elements of example 47, wherein the current path circuitry includes a parallel latch circuitry and a current path regulation circuitry, the parallel latch circuitry coupled to the output nodes and the current path regulation circuitry to regulate the enhanced current flow.

This example includes the elements of example 49, wherein the current path regulation circuitry is selected from the group including voltage controlled current path regulation circuitry, digitally controlled current path regulation circuitry or time-based current path regulation circuitry.

This example includes the elements of example 47, wherein the current path circuitry includes transistors selected from the group including N-type metal oxide semiconductor field effect transistors (MOSFETs), P-type MOSFETs, npn bipolar junction transistors (BJTs), pnp BJTs, heterojunction BJTs, junction field effect transistors (JFETs), finFETs, insulated gate FETs (IGFETs).

This example includes the elements of example 47, wherein the current path circuitry includes N-type metal oxide semiconductor field effect transistors (MOSFETs) or P-type MOSFETs.

This example includes the elements of example 47, wherein the first clocked comparator circuitry is selected from the group including N-type clocked comparator circuitry, N-type low kickback clocked comparator circuitry and P-type clocked comparator circuitry.

This example includes the elements of example 47, wherein the slicer circuitry further includes a second clocked comparator circuitry coupled to Out_P and Out_N, the first clocked comparator circuitry corresponding to a first stage and the second clocked comparator circuitry corresponding to a second stage.

According to this example, there is provided a receiver. The receiver includes a gain stage circuitry; a clock and data recovery circuitry; a reference source circuitry; and a decision feedback equalizer (DFE) circuitry. The DFE circuitry includes a summation node circuitry; a slicer circuitry; a set/reset (SR) circuitry; and at least one DFE latch circuitry. The summation node circuitry includes a reference summation node circuitry to sum a reference input signal and one or more weighted prior decisions.

This example includes the elements of example 55, wherein the summation node circuitry further includes a data summation node circuitry.

This example includes the elements of example 55, wherein the summation node circuitry corresponds to current summation node circuitry.

This example includes the elements according to any one of examples 55 to 57, wherein the slicer circuitry includes a first clocked comparator circuitry, the first clocked comparator circuitry including a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N); and a current path circuitry coupled to the output nodes and a reference node, the current path circuitry to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

This example includes the elements of example 58, wherein the current path circuitry includes a parallel latch circuitry coupled to the output nodes and the reference node.

This example includes the elements of example 58, wherein the current path circuitry includes a parallel latch circuitry and a current path regulation circuitry, the parallel latch circuitry coupled to the output nodes and the current path regulation circuitry to regulate the enhanced current flow.

This example includes the elements of example 60, wherein the current path regulation circuitry is selected from the group including voltage controlled current path regulation circuitry, digitally controlled current path regulation circuitry or time-based current path regulation circuitry.

This example includes the elements of example 58, wherein the current path circuitry includes transistors selected from the group including N-type metal oxide semiconductor field effect transistors (MOSFETs), P-type MOSFETs, npn bipolar junction transistors (BJTs), pnp BJTs, heterojunction BJTs, junction field effect transistors (JFETs), finFETs, insulated gate FETs (IGFETs).

This example includes the elements of example 58, wherein the current path circuitry includes N-type metal oxide semiconductor field effect transistors (MOSFETs) or P-type MOSFETs.

This example includes the elements of example 58, wherein the first clocked comparator circuitry is selected from the group including N-type clocked comparator circuitry, N-type low kickback clocked comparator circuitry and P-type clocked comparator circuitry.

This example includes the elements of example 58, wherein the slicer circuitry further includes a second clocked comparator circuitry coupled to Out_P and Out_N, the first clocked comparator circuitry corresponding to a first stage and the second clocked comparator circuitry corresponding to a second stage.

This example includes the elements according to any one of examples 55 to 57, wherein the receiver further includes front end equalizer circuitry.

According to this example, there is provided a system. The system includes at least one device arranged to perform the method of any one of examples 32 to 43.

According to this example, there is provided a device. The device includes means to perform the method of any one of examples 32 to 43.

According to this example, there is provided an Ethernet physical layer (PHY). The Ethernet PHY includes a transmitter; and a receiver. The receiver includes a gain stage circuitry; a clock and data recovery circuitry; a reference source circuitry; and a decision feedback equalizer (DFE) circuitry. The DFE circuitry includes a summation node circuitry; an enhanced slicer circuitry; a set/reset (SR) circuitry; and at least one DFE latch circuitry. The enhanced slicer circuitry includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node, the current path circuitry to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

This example includes the elements of example 69, wherein the current path circuitry includes a parallel latch circuitry coupled to the output nodes and the reference node.

This example includes the elements of example 69, wherein the current path circuitry includes a parallel latch circuitry and a current path regulation circuitry, the parallel latch circuitry coupled to the output nodes and the current path regulation circuitry to regulate the enhanced current flow.

This example includes the elements of example 69, wherein the summation node circuitry includes a reference summation node circuitry to sum a reference input signal and one or more weighted prior decisions.

This example includes the elements of example 71, wherein the current path regulation circuitry is selected from the group including voltage controlled current path regulation circuitry, digitally controlled current path regulation circuitry or time-based current path regulation circuitry.

This example includes the elements according to any one of examples 69 through 72, wherein the summation node circuitry includes data summation node circuitry.

This example includes the elements according to any one of examples 69 through 72, wherein the current path circuitry includes transistors selected from the group including N-type metal oxide semiconductor field effect transistors (MOSFETs), P-type MOSFETs, npn bipolar junction transistors (BJTs), pnp BJTs, heterojunction BJTs, junction field effect transistors (JFETs), finFETs, insulated gate FETs (IGFETs).

This example includes the elements according to any one of examples 69 through 72, wherein the current path circuitry includes N-type metal oxide semiconductor field effect transistors (MOSFETs) or P-type MOSFETs.

This example includes the elements according to any one of examples 69 through 72, wherein the first clocked comparator circuitry is selected from the group including N-type clocked comparator circuitry, N-type low kickback clocked comparator circuitry and P-type clocked comparator circuitry.

This example includes the elements according to any one of examples 69 through 72, wherein the enhanced slicer further includes a second clocked comparator circuitry coupled to Out_P and Out_N, the first clocked comparator circuitry corresponding to a first stage and the second clocked comparator circuitry corresponding to a second stage.

This example includes the elements according to any one of examples 69 through 72, wherein the summation node circuitry corresponds to current summation node circuitry.

This example includes the elements according to any one of examples 69 through 72, wherein the receiver further includes front end equalizer circuitry.

According to this example, there is provided an Ethernet physical layer (PHY). The Ethernet PHY includes a transmitter; and a receiver. The receiver includes a gain stage circuitry; a clock and data recovery circuitry; a reference source circuitry; and a decision feedback equalizer (DFE) circuitry. The DFE circuitry includes a summation node circuitry, a slicer circuitry, a set/reset (SR) circuitry, and at least one DFE latch circuitry. The summation node circuitry includes a reference summation node circuitry to sum a reference input signal and one or more weighted prior decisions.

This example includes the elements of example 81, wherein the summation node circuitry further includes a data summation node circuitry.

This example includes the elements of example 81, wherein the summation node circuitry corresponds to current summation node circuitry.

This example includes the elements according to any one of examples 81 to 83, wherein the slicer circuitry includes a first clocked comparator circuitry, the first clocked comparator circuitry including a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N); and a current path circuitry coupled to the output nodes and a reference node, the current path circuitry to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

This example includes the elements of example 84, wherein the current path circuitry includes a parallel latch circuitry coupled to the output nodes and the reference node.

This example includes the elements of example 84, wherein the current path circuitry includes a parallel latch circuitry and a current path regulation circuitry, the parallel latch circuitry coupled to the output nodes and the current path regulation circuitry to regulate the enhanced current flow.

This example includes the elements of example 86, wherein the current path regulation circuitry is selected from the group including voltage controlled current path regulation circuitry, digitally controlled current path regulation circuitry or time-based current path regulation circuitry.

This example includes the elements of example 84, wherein the current path circuitry includes transistors selected from the group including N-type metal oxide semiconductor field effect transistors (MOSFETs), P-type MOSFETs, npn bipolar junction transistors (BJTs), pnp BJTs, heterojunction BJTs, junction field effect transistors (JFETs), finFETs, insulated gate FETs (IGFETs).

This example includes the elements of example 84, wherein the current path circuitry includes N-type metal oxide semiconductor field effect transistors (MOSFETs) or P-type MOSFETs.

This example includes the elements of example 84, wherein the first clocked comparator circuitry is selected from the group including N-type clocked comparator circuitry, N-type low kickback clocked comparator circuitry and P-type clocked comparator circuitry.

This example includes the elements of example 84, wherein the slicer circuitry further includes a second clocked comparator circuitry coupled to Out_P and Out_N, the first clocked comparator circuitry corresponding to a first stage and the second clocked comparator circuitry corresponding to a second stage.

This example includes the elements according to any one of examples 81 to 83, wherein the receiver further includes front end equalizer circuitry.