FinFET device with different liners for PFET and NFET and method of fabricating thereof

A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

BACKGROUND

The semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs. As this progression takes place, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as fin-like field effect transistor (FinFET) device. A typical FinFET device is fabricated with a thin “fin” (or fin-like structure) extending from a substrate. The fin usually includes silicon and forms the body of the transistor device. The channel of the transistor is formed in this vertical fin. A gate is provided over (e.g., wrapping around) the fin. This type of gate allows greater control of the channel. Other advantages of FinFET devices include reduced short channel effect and higher current flow.

However, conventional FinFET devices may still have certain drawbacks. For example, the shallow trench isolation (STI) liner for conventional FinFET devices have not been configured to optimize the performance of the FinFET devices.

Therefore, while existing FinFET devices and the fabrication thereof have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

DETAILED DESCRIPTION

The present disclosure is directed to, but not otherwise limited to, a fin-like field-effect transistor (FinFET) device. The FinFET device, for example, may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor FinFET device and an N-type metal-oxide-semiconductor FinFET device. The following disclosure will continue with one or more FinFET examples to illustrate various embodiments of the present disclosure. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed.

The use of FinFET devices has been gaining popularity in the semiconductor industry. Referring toFIG. 1, a perspective view of an example FinFET device50is illustrated. The FinFET device50is a non-planar multi-gate transistor that is built over a substrate (such as a bulk substrate). A thin silicon-containing “fin-like” structure (hereinafter referred to as a “fin”) forms the body of the FinFET device50. The fin extends along an X-direction shown inFIG. 1. The fin has a fin width Wfinmeasured along a Y-direction that is orthogonal to the X-direction. A gate60of the FinFET device50wraps around this fin, for example around the top surface and the opposing sidewall surfaces of the fin. Thus, a portion of the gate60is located over the fin in a Z-direction that is orthogonal to both the X-direction and the Y-direction.

LGdenotes a length (or width, depending on the perspective) of the gate60measured in the X-direction. The gate60may include a gate electrode component60A and a gate dielectric component60B. The gate dielectric60B has a thickness toxmeasured in the Y-direction. A portion of the gate60is located over a dielectric isolation structure such as shallow trench isolation (STI). A source70and a drain80of the FinFET device50are formed in extensions of the fin on opposite sides of the gate60. A portion of the fin being wrapped around by the gate60serves as a channel of the FinFET device50. The effective channel length of the FinFET device50is determined by the dimensions of the fin.

FinFET devices offer several advantages over traditional Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) devices (also referred to as planar transistor devices). These advantages may include better chip area efficiency, improved carrier mobility, and fabrication processing that is compatible with the fabrication processing of planar devices. FinFET devices are also compatible with a high-k metal gate (HKMG) process flow. Thus, FinFET devices may be implemented as HKMG devices where the gates each that have a high-k gate dielectric and a metal gate electrode. For these benefits discussed above, it may be desirable to design an integrated circuit (IC) chip using FinFET devices for a portion of, or the entire IC chip.

However, traditional FinFET fabrication methods may still have shortcomings. For example, conventional FinFET fabrication may use the same type of shallow trench isolation (STI) liner material for both NFETs and PFETs. This approach does not optimize the performance of FinFET transistors. To improve the performance for FinFET devices, the present disclosure utilizes a dual STI liner approach to simultaneously improve the performance for both NFETs and PFETs, as discussed in more detail below with reference toFIGS. 2-18.

FIGS. 2-17are diagrammatic fragmentary cross-sectional side views of a FinFET device100at various stages of fabrication. Referring toFIG. 2, the FinFET device100includes an N-well110and a P-well120each formed in a substrate. The substrate may be a semiconductor substrate, for example a silicon substrate. The N-well110and the P-well120may be formed using one or more ion implantation processes and are doped differently, so as to have different types of conductivity. The dopant ions may include an n-type material in some embodiments, for example arsenic (As) or phosphorous (P), or they may include a p-type material in some other embodiments, for example boron (B), depending on whether an NFET or a PFET is needed.

A semiconductor layer130is formed over the N-well110and over the P-well120. In some embodiments, the semiconductor layer130includes silicon. The silicon material of the semiconductor layer130may be grown over the N-well110and the P-well120using an epitaxial growth process. The semiconductor layer130is grown to have a thickness140. In some embodiments, the thickness140is in a range between about 30 nanometers (nm) and about 70 nm. A portion of the semiconductor layer130(after undergoing a patterning process) will serve as the fin for the NFET (also referred to as an NMOS) of the FinFET device100, as will be discussed in more detail below.

Referring now toFIG. 3, a dielectric layer150is formed over the semiconductor layer130. In some embodiments, the dielectric layer150includes an oxide material, for example silicon oxide. The dielectric layer150may be formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or combinations thereof. The dielectric layer150is formed to have a thickness160. In some embodiments, the thickness160is in a range between about 10 nm and about 20 nm. The dielectric layer150will serve as a hard mask in a patterning process discussed below.

Referring now toFIG. 4, a patterned photoresist layer170is formed over the dielectric layer150. In some embodiments, the patterned photoresist layer170is formed by one or more processes such as photoresist coating (e.g., photoresist spin-coating), exposing, post-exposure baking, developing, and rinsing. After being developed, the patterned photoresist layer170is formed by the remaining portions of the photoresist material. As is shown inFIG. 4, the patterned photoresist layer170is formed over the P-well120but not over the N-well110. In other words, the patterned photoresist layer170is aligned vertically (e.g., in the Z-direction shown inFIG. 1) with the P-well120, but not with the N-well110.

Referring now toFIG. 5, the dielectric layer150is patterned by the patterned photoresist layer170, thereby forming a patterned hard mask150A. The patterned photoresist layer170is then removed, for example using a photoresist stripping process or a photoresist ashing process. Using the patterned hard mask150A as a protective mask, an etching process is then performed to etch away portions of the semiconductor layer130. In other words, the patterned hard mask150A protects a portion130B of the semiconductor layer130therebelow from being etched during the etching process, while portions of the semiconductor layer130not protected by the patterned hard mask150A are removed.

As is shown inFIG. 5, the etching process is performed in a manner such that a portion130A of the semiconductor layer130still remains over the N-well110. The portion130A and the rest of the semiconductor layer130have the same material compositions (e.g., they both contain Si), since the portion130A is a part of the layer130. The portion130A of the semiconductor layer130is formed to have a thickness190. In some embodiments, the thickness190is in a range between about 2 nm and about 8 nm. One of the reasons for preserving the portion130A of the semiconductor layer130is for better epi-growth of a silicon germanium material in a later process. For example, the portion130A of the semiconductor layer130helps isolate the N-well110from the silicon germanium material to be grown over the semiconductor layer130later.

Referring now toFIG. 6, a semiconductor layer200is formed over the portion130A of the semiconductor layer130. The semiconductor layer200has a different material composition than the semiconductor layer130. For example, in some embodiments, the semiconductor layer200includes silicon germanium (SiGe). The semiconductor layer200may be grown using an epitaxial growth process. As discussed above, due to the presence of the portion130A of the semiconductor layer130, the semiconductor layer200is not formed directly on the N-well110but on the portion130A of the semiconductor layer130. The portion130A of the semiconductor layer130provides isolation between the N-well110and the semiconductor layer200and allows the semiconductor layer200to be formed with better epitaxial growth quality. The semiconductor layer200is formed to have a thickness210. In some embodiments, the thickness210is in a range from about 40 nm and about 60 nm. The semiconductor layer200will serve as the fin for a PFET (also referred to as a PMOS) of the FinFET device100, as will be discussed in more detail below.

Referring now toFIG. 7, the patterned hard mask150A is removed, for example using a polishing process such as chemical-mechanical-polishing (CMP). The CMP process may also remove a small portion of the semiconductor layer200and the portion130B of the semiconductor layer130. As a result of the polishing process, the FinFET device100now has a substantially flat or planarized upper surface220.

Referring now toFIG. 8, a capping layer230is formed on the planarized upper surface220of the semiconductor layers200and130B. In some embodiments, the capping layer230includes silicon and may be referred to as a silicon capping layer. The capping layer230is formed to have a thickness240. In some embodiments, the thickness240is in a range from about 0.5 nm and about 5 nm. The capping layer230protects the semiconductor layer200from undesirable oxidation. For example, if exposed to ambient air (which contains oxygen), the silicon germanium material in the semiconductor layer200is easy to become oxidized, which is undesirable as it may adversely affect the intended function of the silicon germanium material (e.g., to serve as a semi-conductive material). The formation of the capping layer230prevents the semiconductor layer200from air exposure, and as such it prevents the potential oxidation of the silicon germanium material of the semiconductor layer200. The capping layer230will be removed in a later process.

Referring now toFIG. 9, a dielectric layer270is formed over the capping layer230. In some embodiments, the dielectric layer270includes silicon oxide and may be referred to as a pad oxide layer270. A dielectric layer280is then formed over the dielectric layer280is formed over the dielectric layer270. In some embodiments, the dielectric layer280includes silicon nitride and may be referred to as a pad nitride layer280. The dielectric layers270and280may serve as materials for a hard mask for a subsequent photolithography patterning process.

Referring now toFIG. 10, an OD (active region) patterning process290is performed to form upwardly-protruding (e.g., upwardly in the Z-direction ofFIG. 1) fin structures295. As a part of the OD patterning process290, the dielectric layers270and280may be patterned (e.g., using a patterned photoresist layer) to form patterned hard masks that define the lateral dimensions of the fin structures295. The patterned hard masks270/280are then used to pattern the layers therebelow. For example, portions of the layers230,200and130B and the N-well110and P-well120not protected by the patterned masks270/280are etched away in one or more etching processes. It can be seen that the N-well110is etched so that a segment110A thereof protrudes out of a segment110B that is not etched away, and the P-well120is etched so that a segment120A thereof protrudes out of a segment120B that is not etched away. It is understood that the segment110A and the segment110B have the same material compositions, and that the segment120A and the segment120B have the same material compositions. However, the doping concentration levels may be different between the segments110A and110B, and between the segments120A and120B. For example, the segment110B may have a lower doping concentration level than the segment110A, and the segment120B may have a lower doping concentration level than the segment120A. The remaining portions of the layers230and200, the portion130A, and the upwardly-protruding segments of the N-well110A collectively form the fin structures295for the PFET, and the remaining portions of the semiconductor layers130B and the upwardly-protruding segments of the P-well120A collectively form the fin structures295for the NFET. The channel and source/drain regions of the NFET and the PFET may be formed in the fin structures295, for example in the semiconductor layers200and130B.

Referring now toFIG. 11, a deposition process300is performed to form a nitride-containing liner layer310on the top surfaces and side surfaces of each of the fin structures295. In some embodiments, the deposition process300includes a CVD process with a deposition process temperature range between about 550 degrees Celsius and about 950 degrees Celsius. For example, in the PFET, the nitride-containing liner layer310is formed on the sidewall surfaces of the semiconductor layer200and on the sidewall surfaces of the segment110A of the N-well110. In some embodiments, the nitride-containing liner layer310is in direct physical contact with the sidewall surfaces of the semiconductor layer200and with the sidewall surfaces of the segment110A of the N-well110. In some embodiments, the nitride-containing liner layer310may include a silicon nitride material. The nitride-containing liner layer310is formed to have a thickness320. In some embodiments, the deposition process300is configured such that the thickness320is in a range from about 2 nm to about 5 nm.

The silicon-nitride material of the liner layer310prevents the silicon germanium material of the semiconductor layer200from being exposed to the oxygen in the air. As discussed above, silicon germanium is prone to undesirable oxidation. After the performance of the OD patterning process290discussed above with reference toFIG. 10, the sidewalls of the semiconductor layer200(containing silicon germanium) in the fin structures295are exposed. If no other measures are taken, the exposure of the semiconductor layer200to air would oxidize the silicon germanium in the semiconductor layer200, thereby degrading device performance.

To suppress the oxidation of the semiconductor layer200, the present disclosure forms the nitride-containing liner layer310(e.g., containing silicon nitride) on the sidewalls of the semiconductor layer200to prevent semiconductor layer200from being exposed to air. The presence of the nitride-containing liner layer310thus reduces the likelihood of undesirable oxidation of the semiconductor layer200. The range of the thickness320is also configured to optimize the function of the nitride-containing liner layer310, for example with respect to preventing the oxidation of the semiconductor layer200. It is understood that although silicon nitride is used as an example of the nitride-containing liner layer310, other suitable materials may also be used, as long as those materials are suitable to prevent the oxidation of the silicon germanium of the semiconductor layer200.

Note that the nitride-containing liner layer310is also formed on the fin structures295for the NFET. However, this is not needed, and thus the nitride-containing liner layer310for the NFET may be removed in a later process.

Referring now toFIG. 12, a patterned photoresist layer330is formed to cover up the PFET of FinFET device100while leaving the NFET exposed. In other words, the patterned photoresist layer330is formed over the fin structures295that are formed over the N-well110B, but not over the fin structures295that are formed over the P-well120B. As such, the segment of the nitride-containing liner layer310of the PFET is covered up by the patterned photoresist layer330, while the segment of the nitride-containing liner layer310of the NFET is exposed. The patterned photoresist layer330may be formed by processes such as deposition, exposure, developing, baking, etc. (not necessarily performed in that order).

Referring now toFIG. 13, an etching process350is performed to the FinFET device100to remove the portion of the nitride-containing liner layer310that is disposed in the NFET region of the FinFET device100. The patterned photoresist layer330protects the nitride-containing liner layer310therebelow from being etched during the etching process350. As such, the portion of the nitride-containing liner layer310in the PFET remains intact and not removed by the etching process350. However, since the portion of the nitride-containing liner layer310that is disposed in the NFET is not protected by the patterned photoresist330, the nitride-containing liner layer310is removed for the NFET, thereby exposing the upper surfaces and the sidewall surfaces of the fin structures295of the NFET. For example, the sidewall surfaces of the semiconductor layer130B are exposed, as are the sidewall surfaces of the segments120A of the P-well.

Referring now toFIG. 14, the patterned photoresist layer330is removed, for example using a photoresist stripping process or a photoresist ashing process. The removal of the patterned photoresist layer330leaves the nitride-containing liner layer310(cover the fin structures295in the PFET) exposed.

Referring now toFIG. 15, a deposition process400is performed to form an oxide-containing liner layer410on the top surfaces and side surfaces of each of the fin structures295. In some embodiments, the deposition process400includes a CVD process with a deposition process temperature range between about 550 degrees Celsius and about 950 degrees Celsius. For example, in the PFET, the oxide-containing liner layer410is formed on the nitride-containing liner layer310. In some embodiments, the oxide-containing liner layer410is in direct physical contact with the nitride-containing liner layer310. In the NFET, the oxide-containing liner layer410is formed on the sidewall surfaces of the semiconductor layer130B and on the sidewall surfaces of the segment120A of the P-well120. In some embodiments, the oxide-containing liner layer410is in direct physical contact with the sidewall surfaces of the semiconductor layer130B and with the sidewall surfaces of the segment120A of the P-well120.

In some embodiments, the oxide-containing liner layer410may include a silicon oxide material. In some other embodiments, the oxide-containing liner layer410may include an aluminum oxide material. The oxide-containing liner layer410is formed to have a thickness420. In some embodiments, the deposition process300is configured such that the thickness420is in a range from about 2 nm to about 5 nm.

The silicon oxide material of the liner layer410causes stress. For example, since the channel of the NFET will be formed in the semiconductor layer130B, the proximity (e.g., in direct physical contact) of the liner layer410with the semiconductor layer130B may cause tensile stress to the channel of the NFET. The stressed channel may lead to performance improvements such as boosted carrier mobility and as such may be desirable. While a nitride liner such as the nitride-containing liner310may also cause some stress to the channel of the NFET (had the nitride-containing liner310been used for the NFET in place of the oxide-containing liner layer410), the nitride material may not cause as much stress as the oxide would. In addition, the nitride material may be positively charged. The positive charge may cause the NFET to turn on too easily, which is undesirable. Among other things, if the NFET is turned on too easily, it may induce high leakage. Therefore, it is desirable for the liner layer that is in proximity of the NFET to be neutral (e.g., no charge) or have a negative charge.

For these reasons discussed above, the material composition of the oxide-containing liner layer410is configured to cause stress to the channel of the NFET while being neutral or positively charged. The silicon oxide material or aluminum oxide material composition may satisfy these conditions, and as such the oxide-containing liner layer410may include silicon oxide, aluminum oxide, or a combination thereof in various embodiments. Note that at the stage of fabrication shown inFIG. 15, a plurality of gaps or trenches450exist between the fin structures295. These gaps or trenches450will be filled in a later process discussed below.

Referring now toFIG. 16, a dielectric isolation structure500is formed, for example by a deposition process such as Furnace Chemical Vapor Deposition (FCVD). The dielectric isolation structure500is formed to fill the gaps or trenches450between the fin structures295. The dielectric isolation structure500may include a shallow-trench-isolation (STI) in some embodiments. The dielectric isolation structure500may include an oxide material, for example silicon oxide. Before or after the formation of the dielectric isolation structure500, a polishing process such as a CMP process may be performed to remove the dielectric layers270and280(as well as portions of the dielectric isolation structure500). The polishing process may also remove the capping layer230in the fin structures295for the PFET.

Referring now toFIG. 17, a fin recess process600is performed to the FinFET device100to selectively remove portions of the oxide-containing liner layer410for both the PFET and the NFET, as well as to selectively remove portions of the nitride-containing liner layer310for the PFET. In more detail, the portions of the oxide-containing liner layer410are removed for the NFET such that the semiconductor layer130B is exposed, including its upper surface and its sidewall surfaces. Similarly, the portions of the oxide-containing liner layer410as well as portions of the nitride-containing liner layer310are removed for the PFET such that the semiconductor layer200is exposed, including its upper surface and its sidewall surfaces. Portions of the dielectric isolation structure500are also removed as a part of the fin recess process600, so as to help expose the side surfaces of the semiconductor layers200and130B.

Meanwhile, the fin recess process600is configured such that it does not substantially affect the portions of the liner layers310and410that are not disposed on the semiconductor layers200and130B. For example, after the fin recess process600is performed, a segment of the nitride-containing liner layer310still remains disposed on the sidewall surfaces of the segments110A and130A of the N-well and on the upper surfaces of the segment110B of the N-well. A segment of the oxide-containing liner layer410also remains disposed on the nitride-containing liner layer310in the PFET. For the NFET, another segment of the oxide-containing liner layer410remains disposed on the sidewall surfaces of the segment120A of the P-well and on the upper surfaces of the segment120B of the P-well. The oxide-containing liner layer410surrounds the side and bottom surfaces of the dielectric isolation structure500in the cross-sectional view ofFIG. 17. Since the present disclosure utilizes different liner layers for the NFET and the PFET, it may be said that the FinFET device100of the present disclosure is a “dual-liner” device.

In some embodiments, the fin recess process600includes one or more etching processes, such as dry etching, wet etching, reactive ion etching (RIE), etc. Various etching parameters can be tuned to selectively etch away a desired amount (for example, just enough to expose the semiconductor layers200and130B) of the liner layers310and410. These etching parameters may include, but are not limited to: etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source power, RF (radio-frequency) bias voltage, RF bias power, etchant flow rate, or combinations thereof.

FIG. 18is a flowchart of a method900for fabricating a FinFET device in accordance with various aspects of the present disclosure. The method900includes a step910of forming a first semiconductor layer over an N-well. In some embodiments, the forming of the first semiconductor layer comprises epitaxially growing silicon germanium as the first semiconductor layer over the N-well.

The method900includes a step920of forming a second semiconductor layer over a P-well. In some embodiments, the forming of the second semiconductor layer comprises epitaxially growing silicon as the second semiconductor layer over the P-well. In some embodiments, the second semiconductor layer is formed before the first semiconductor layer. In some embodiments, the epitaxially growing of the silicon is performed such that the silicon is grown over both the N-well and the P-well. In some embodiments, after the forming of the second semiconductor layer but before the forming of the first semiconductor layer, the second semiconductor layer over the N-well is partially removed. The first semiconductor layer is epitaxially grown over a remaining portion of the second semiconductor layer that is located over the N-well after the partially removing of the second semiconductor layer.

The method900includes a step930of performing a patterning process to form a first fin structure and a second fin structure. The first fin structure includes a portion of the first semiconductor layer and a portion of the N-well, and the second fin structure includes a portion of the second semiconductor layer and a portion of the P-well.

The method900includes a step940of forming a first liner layer over the first fin structure, the N-well, the second fin structure, and the P-well. In some embodiments, the forming of the first liner layer comprises forming a nitride-containing layer as the first liner layer. In some embodiments, the nitride-containing liner layer includes silicon nitride.

The method900includes a step950of selectively removing the first liner layer such that the first liner layer formed over the second fin structure and the P-well is removed. A remaining portion of the first liner layer formed over the first fin structure and the N-well is unaffected by the selectively removing.

The method900includes a step960of forming a second liner layer over the second fin structure, the P-well, and the remaining portion of the first liner layer. The second liner layer and the first liner layer have different material compositions. In some embodiments, the forming of the second liner layer comprises forming an oxide-containing layer as the second liner layer. In some embodiments, the oxide-containing layer includes silicon oxide.

In some embodiments, the method900may further include steps of removing portions of the first liner layer and the second liner layer formed over the first semiconductor layer, as well as removing portions of the second liner layer formed over the second semiconductor layer.

It is understood that additional process steps may be performed before, during, or after the steps910-960discussed above to complete the fabrication of the semiconductor device. For example, the method900may further perform processes to form gate structures. The gate structures may be formed using either a “gate-first” or a “gate-last” process. The method900may further include steps of forming source/drain features, as well as forming an inter-layer dielectric (ILD) layer. Furthermore, an interconnect structure including conductive contacts, vias, and interconnect lines may be formed. Additionally, testing and packaging steps may be performed to complete the fabrication of an integrated circuit.

Based on the above discussions, it can be seen that the present disclosure offers advantages over conventional FinFET and the fabrication thereof. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that, through the use of a nitride-containing liner, the present disclosure can reduce or prevent the undesirable oxidation of a silicon germanium material in the fin of the PFET. Another advantage is that, through the use of an oxide-containing liner, the present disclosure can add stress to the channel of the NFET. The oxide-containing liner also does not have a positive charge, which means that the NFET is not too easily turned on. For these reasons, the FinFET device performance is improved. In addition, the various aspects of the present disclosure are compatible with current fabrication process flow and are easy to implement.

One embodiment of the present disclosure involves a semiconductor device. The semiconductor device includes a P-type Field Effect Transistor (PFET) that includes: an N-well disposed in a substrate; a first fin structure disposed over the N-well; a first liner layer disposed over the N-well; and a second liner layer disposed over the first liner layer, wherein the first liner layer and the second liner layer include different materials. The semiconductor device also includes an N-type Field Effect Transistor (NFET) that includes: a P-well disposed in the substrate; a second fin structure disposed over the P-well; and a third liner layer disposed over the P-well, wherein the third liner layer and the second liner layer include same materials. In some embodiments, the first fin structure includes a silicon germanium layer; the second fin structures include a silicon layer; the first liner layer includes a material configured to prevent the silicon germanium layer from being oxidized; and the second liner layer includes a material configured to provide stress to the NFET. In some embodiments, the first liner layer includes a nitride-containing material; the second liner layer includes an oxide-containing material; and the third liner layer includes the oxide-containing material. In some embodiments, the first liner layer includes silicon nitride; and the second liner layer and the third liner layer each include silicon oxide. In some embodiments, no portion of the first liner layer and the second liner layer is disposed on sidewalls of the silicon germanium layer; and no portion of the third liner layer is disposed on sidewalls of the silicon layer. In some embodiments, a portion of the first liner layer is disposed on a side surface of the N-well; and a portion of the second liner layer is disposed on a side surface of the P-well. In some embodiments, the semiconductor device further includes: a dielectric isolation structure located between the PFET and the NFET, wherein the dielectric isolation structure is surrounded by the second liner layer and the third liner layer in a cross-sectional side view.

Another embodiment of the present disclosure involves a FinFET device. The FinFET device includes a P-type Field Effect Transistor (PFET) that includes: an N-well formed in a substrate, wherein the N-well includes a first portion and a second portion that protrudes out of the first portion; a first semiconductor layer located over the second portion of the N-well, wherein the first semiconductor layer includes silicon germanium; a first liner layer located over the N-well but not over the first semiconductor layer, wherein the first liner layer includes a material that prevents an oxidation of the silicon germanium; and a first segment of a second liner layer located over the first liner layer, wherein the second liner layer includes a material that causes stress to silicon. The FinFET device also includes an N-type Field Effect Transistor (NFET) that includes: a P-well formed in the substrate, wherein the P-well includes a first portion and a second portion that protrudes out of the first portion; a second semiconductor layer located over the second portion of the P-well, wherein the second semiconductor layer includes silicon; and a second segment of the second liner layer located over the P-well but not over the second semiconductor layer. In some embodiments, the first liner layer includes a silicon nitride, and the first segment and the second segment of the second liner layer each include silicon oxide. In some embodiments, the first liner layer is in direct physical contact with a sidewall of the first portion of the N-well, and the second segment of the second liner layer is in direct physical contact with a sidewall of the first portion of the P-well. In some embodiments, the FinFET device further includes: a dielectric isolation structure located between the PFET and the NFET. The dielectric isolation structure is in direct physical contact with both the first segment and the second segment of the second liner layer.

Another embodiment of the present disclosure involves a method of fabricating a semiconductor device. The method includes: forming a first semiconductor layer over an N-well; forming a second semiconductor layer over a P-well; performing a patterning process to form a first fin structure and a second fin structure, wherein the first fin structure includes a portion of the first semiconductor layer and a portion of the N-well, and the second fin structure includes a portion of the second semiconductor layer and a portion of the P-well; forming a first liner layer over the first fin structure, the N-well, the second fin structure, and the P-well; selectively removing the first liner layer such that the first liner layer formed over the second fin structure and the P-well is removed, wherein a remaining portion of the first liner layer formed over the first fin structure and the N-well is unaffected by the selectively removing; and after the selectively removing of the first liner layer, forming a second liner layer over the second fin structure, the P-well, and the remaining portion of the first liner layer, wherein the second liner layer and the first liner layer have different material compositions. In some embodiments, the method further includes steps of removing portions of the first liner layer and the second liner layer formed over the first semiconductor layer and removing portions of the second liner layer formed over the second semiconductor layer. In some embodiments, the forming of the first liner layer comprises forming a nitride-containing layer as the first liner layer. In some embodiments, the nitride-containing layer includes silicon nitride. In some embodiments, the forming of the second liner layer comprises forming an oxide-containing layer as the second liner layer. In some embodiments, the oxide-containing layer includes silicon oxide. In some embodiments, the forming of the first semiconductor layer comprises epitaxially growing silicon germanium as the first semiconductor layer over the N-well; and the forming of the second semiconductor layer comprises epitaxially growing silicon as the second semiconductor layer over the P-well. In some embodiments, the second semiconductor layer is formed before the first semiconductor layer; and the epitaxially growing of the silicon is performed such that the silicon is grown over both the N-well and the P-well. In some embodiments, the method further includes steps of: after the forming of the second semiconductor layer but before the forming of the first semiconductor layer, partially removing the second semiconductor layer over the N-well, wherein the first semiconductor layer is epitaxially grown over a remaining portion of the second semiconductor layer that is located over the N-well after the partially removing of the second semiconductor layer.