Data transfer in memory card system

A memory card system includes a host that issues a read command and a memory card that upon receiving the read command sends read data to the host in synchronism with a read clock signal generated within the memory card. In addition, the memory card sends the read clock signal to the host, and the host receives the read data in synchronism with the read clock signal, for increasing the allowable setup time period at the host.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2006-74291, filed on Aug. 7, 2006, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present invention relates generally to memory card systems, and more particularly, to increasing allowable setup time at a host by transferring read data from a memory card to a host along with a read clock signal generated at the memory card.

BACKGROUND OF THE INVENTION

FIG. 1shows an example memory card system100of the prior art, including a memory card102and a host104. The host104may be a portable electronic device such as a mobile phone, a MP3 player, or a PMP (portable media player). The memory card102may be a flash memory card as one example. The host104includes a host controller106and a host connection unit108. The card102includes a card connection unit110, a card controller112, and a memory unit114.

For writing data from the host104to the memory card102, the host104sends a write command (WR_CMD), a clock signal CLK, and data to be written to the memory card102through the host connection unit108. The memory card102receives the write command, the clock signal CLK, and the data through the card connection unit110.

The card connection unit110receives the data from the host104in synchronism with the clock signal CLK from the host. The card controller112responds to the received write command by writing the received data into the memory unit114in synchronism with an internal clock signal generated by a clock signal generator within the card controller112.

For reading of data from the memory card102by the host104, the host104sends a read command (RD_CMD) and the clock signal CLK to the memory card102through the host connection unit108. The memory card102receives the read command and the clock signal CLK through the card connection unit110.

In the conventional memory card system100, the host104generates and sends the clock signal CLK to be used by the memory card110for the write and read operations. Referring to the memory card system100inFIG. 2, the host104includes a host clock generator116for generating such a clock signal CLK.

Further referring toFIG. 2, the host104includes a host I/O (input/output) circuit118having a plurality of data flip flops HF1, HF2, . . . , and HFn that are clocked with the clock signal CLK from the host clock generator116. The memory card102includes a card I/O (input/output) circuit120having a plurality of data flip flops CF1, CF2, . . . , and CFn that are also clocked with the clock signal CLK from the host clock generator116. A card internal circuit122illustrated inFIG. 2includes the card controller112and the memory unit114ofFIG. 1.

FIG. 3shows a flowchart of steps when the host104reads data from the memory card102.FIG. 4shows a timing diagram of signals when the host104reads data from the memory card102.

Referring toFIGS. 2 and 3, the host generates and sends the read command (RD_CMD) and the clock signal CLK to the memory card102through the host connection unit108(step S1132ofFIG. 3). The memory card102upon receiving the read command through the card connection unit110reads data from the memory unit114in synchronism with an internal clock signal generated within the card controller112(step S134ofFIG. 3).

The memory card102then transfers the read data back to the host104in synchronism with the clock signal CLK from the host104(step S1136ofFIG. 3). In that case, the flip flops CF1, CF2, . . . , and CFn of the card I/O circuit120are clocked with the clock signal CLK from the host104for latching out such read data from the memory unit114.

The host104receives and transfers such read data to the host controller106in synchronism to the clock signal CLK generated by the clock signal generator116at the host104(step S138ofFIG. 3). In that case, the flip flops HF1, HF2, . . . , and HFn of the host I/O circuit118are clocked with the clock signal CLK generated by the clock signal generator116at the host104.

FIG. 4shows a timing diagram of signals for the read operation within the memory card system100ofFIG. 2.FIG. 4shows the original CLK signal S10generated by the clock signal generator116at the host104.FIG. 4also shows the transmitted CLK signal S20received at the memory card102which is time delayed by time period t1from the original CLK signal S10.

Additionally referring toFIG. 4, data S30is output from the card I/O circuit120at a time delay t2from the transmitted CLK signal S20received at the memory card102. The time delay t2is a portion of the time period required for the memory controller112to retrieve the read data S30from the memory114with respect to the received CLK signal S20after receiving the read command. The total time delay t I+t2=t3is also termed an output delay.

For example, the first data D0begins to be generated at time point tp1by the card controller112after the read command has been received by the controller112at a prior time. For example, the read command may have been received at the C0transition of the CLK signal S20received at the card102. Thus, the data S30is invalid (shown as shaded inFIG. 4) before the time point tp1.

Further referring toFIG. 4, data S40is received at the host104with a bus delay t4which is the time period required for transferring the data from the card102to the host104. Once the data S40arrives at the host connection unit108, the host I/O circuit118has a maximum allowable setup time period t5for transferring such data S40to the host controller106. The maximum allowable setup time period t5is from the end of the time period t4until the subsequent transition of the original clock signal CLK at the host104when the flip flops HF1, HF2, . . . , and HFn of the host I/O circuit118are controlled to latch the received data S40.

Thus, in the prior art, the maximum allowable setup time period t5is limited by the output delay t3and the bus delay t4. However, such allowable setup time period t5may limit high frequency operation of the memory card system100. Thus, a mechanism is desired for increasing the allowable setup time period t5for faster speed performance of the memory card system.

SUMMARY OF THE INVENTION

Accordingly, in a general aspect of the present invention, the memory card generates and transmits a read clock signal when sending read data to the host for increasing the allowable setup time period at the host.

A memory card system according to a general aspect of the present invention includes a host that issues a read command and a memory card that upon receiving the read command sends read data to the host in synchronism with a read clock signal generated within the memory card. In addition, the memory card sends the read clock signal to the host, and the host receives the read data in synchronism with the received read clock signal.

In one embodiment of the present invention, the host includes at least one flip flop that latches in the read data from the memory card clocked with the read clock signal from the memory card.

In another embodiment of the present invention, the memory card includes at least one flip flop that latches out the read data to the host clocked with the read clock signal.

In an example embodiment of the present invention, the host includes a host data processor and a host memory device having sequences of instructions stored thereon. In that case, execution of the sequences of instructions by the host data processor causes the host data processor to perform the step of sending the read command to the memory card.

In another embodiment of the present invention, the memory card includes a read clock signal generator that is controlled to generate the read clock signal when the memory card receives the read command.

In another example embodiment of the present invention, the memory card includes a card data processor and a card memory device having sequences of instructions stored thereon. In that case, execution of the sequences of instructions by the card data processor causes the card data processor upon receiving the read command to perform the steps of:

reading the read data from a memory unit of the memory card in synchronism with an internal clock signal of the memory card;

controlling the read clock generator to generate the read clock signal to be sent to the host; and

sending the read data and the read clock signal to the host.

In another aspect of the present invention, an allowable setup time for receiving the read data at the host is determined by a phase relationship between the read data and the read clock signal received at the host.

In a further embodiment of the present invention, the memory card includes a memory unit that receives another read command issued from a card controller of the memory card. In that case, the memory unit upon receiving the other read command provides the read data to the card controller in synchronism with another read clock signal generated within the memory unit. For example, the memory unit includes another read clock signal generator that is controlled to generate the other read clock signal when the memory unit receives the other read command. The memory unit is a flash memory in an example embodiment of the present invention.

In another embodiment of the present invention, the host transfers a write command, write data, and a write clock signal to the memory card. In that case, the memory card receives the write data in synchronism with the write clock signal.

In this manner, the read data and the read clock signal sent from the memory card arrive at the host with a substantially same time delay. In that case, the allowable setup time for receiving the read data at the host is determined by the phase relationship between the read data and the read clock signal received at the host. Thus, an output delay from the memory card is eliminated for increasing the allowable setup time at the host.

These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.

The figures referred to herein are drawn for clarity of illustration and are not necessarily drawn to scale. Elements having the same reference number inFIGS. 1,2,3,4,5,6,7,8,9,10, and11refer to elements having similar structure and/or function.

DETAILED DESCRIPTION

FIG. 5shows a block diagram of a memory card system200having increased allowable setup time according to an embodiment of the present invention. The memory card system200includes a host202and a memory card204.

The host202may be a portable electronic device such as a mobile phone, a MP3 player, or a PMP (portable media player), for example. The memory card204may be a smart card, a SIM (subscriber identification module) card, or a flash memory card, for example. The present invention may be practiced when the memory card204is any type of electronic card having read data accessed by the host202that is any electronic device having a coupling with such a memory card204.

The host202includes a host controller206, a host I/O circuit208, a host connection unit210, and a write clock signal generator223. The host I/O circuit208includes a plurality of n data flip flops HF1, HF2, . . . , and HFn for latching data to/from the memory card204.FIG. 10shows an example embodiment of the host controller206including a host data processor412and a host memory device414having sequences of instructions (i.e., software) stored thereon. Execution of such sequences of instructions by the host data processor412causes the host data processor412to perform any function/process/step as described herein as being performed by the host controller206.

The memory card204includes a card internal circuit comprised of a card controller214and a memory unit216. The memory card204also includes a card I/O circuit218, a card connection unit220, and a read clock generator222. The card I/O circuit218includes a plurality of n data flip flops CF1, CF2, . . . , and CFn for latching data to/from the host202.

FIG. 11shows an example embodiment of the card controller214including a card data processor422and a card memory device424having sequences of instructions (i.e., software) stored thereon. Execution of such sequences of instructions by the card data processor422causes the card data processor412to perform any function/process/step as described herein as being performed by the card controller214.

FIG. 6shows a flow-chart of steps during a read operation of the memory card system200ofFIG. 5, in an example embodiment of the present invention. Referring toFIGS. 5 and 6, the host controller206generates a read command RD_CMD sent to the memory card204through the host connection unit210(step S232ofFIG. 6).

The card controller214upon receiving the read command RD_CMD reads data from the memory unit216in synchronism with an internal clock signal generated within the card controller214(step S234ofFIG. 6). In addition, the card controller214upon receiving the read command RD_CMD controls the read clock generator222to generate a read clock signal RD_CLK (step S236ofFIG. 6).

Subsequently, the memory card204transfers the read data generated by the card controller214from the memory unit216to the host202in synchronism with the read clock signal RD_CLK from the read clock generator222(step S238ofFIG. 6). To that end, the data flip flops CF1, CF2, and CFn in the card I/O circuit218are clocked with the read clock signal RD_CLK from the read clock generator222for latching such read data to the host202through the card connection unit220.

In addition, the memory card204also transfers the read clock signal RD_CLK from the read clock generator222to the host202through the card connection unit220(step S238ofFIG. 6). The host202receives the read data and the read clock signal RD_CLK through the host connection unit210(step S240ofFIG. 6). The host I/O circuit208transfers such read data to the host controller206in synchronism with the received RD_CLK signal (step S240ofFIG. 6).

To that end, the data flip flops HF1, HF2, . . . , and HFn in the host I/O circuit208are clocked with the read clock signal RD_CLK received from the memory card204for latching such read data to the host controller206from the host connection unit210.FIG. 7illustrates a timing diagram of the read clock signal RD_CLK S50and the read data S60received at the host connection unit210.

Referring toFIG. 7, the read clock signal RD_CLK S50and the read data S60are received at the host connection unit210with a transfer delay t6between such signals S50and S60. Such a transfer delay t6may arise from the different signal paths for such signals S50and S60. For example, the data path for the read data S60may have a pad associated with a higher delay than the pad for the read clock signal RD_CLK S50. Alternatively, the data path for the read data S60may be longer with higher time delay than the data path for the read clock signal RD_CLK S50.

In any case, a maximum allowable setup time t7for the host I/O circuit208to transfer the read data S60to the host controller206is from the end of the time delay t6to the subsequent transition (i.e., Cl inFIG. 7) of the received read clock signal RD_CLK S50when the flip flops HF1, HF2, . . . , and HFn latch the read data S60. Such a maximum allowable setup time t7inFIG. 7is advantageously longer than the maximum allowable setup time t5in the prior art ofFIG. 4.

The reason for such an increased maximum allowable setup time t7inFIG. 7is that the output delay t3=t1+t2is eliminated with the memory card system200ofFIG. 5with the read clock signal RD_CLK being generated and transmitted from the memory card202for clocking the host I/O circuit208. Such an increased maximum allowable setup time t7inFIG. 7is advantageous for increasing the operating frequency of the memory card system200according to an aspect of the present invention.

In addition, the read clock signal RD_CLK from the read clock generator222is transferred to the host202substantially only during a read operation when read data is also being transferred to the host202in one embodiment of the present invention. The card connection unit220may determine the time duration for sending such read data and read clock signal RD_CLK from an estimation of the size of the read data to be sent to the host202. Alternatively, the host202may send an acknowledge command back to the card connection unit220indicating when all of the desired read data has been received by the host202.

FIG. 8shows a flow-chart of steps performed by the memory card system200ofFIG. 5for a write operation. Referring toFIGS. 5 and 8, the host202sends a write command WR_CMD, a write clock signal WR_CLK, and write data to be written to the memory card204through the host connection unit210(step S242ofFIG. 8). To that end, the host202includes a write clock signal generator223for generating the write clock signal WR_CLK.

Further referring toFIGS. 5 and 8, the data flip flops CF1, CF2, . . . , and CFn of the card I/O circuit218latch such write data received at the card connection unit220in synchronism to the write clock signal WR_CLK received at the card connection unit220(step S244ofFIG. 8). In addition, the card controller214receives such latched write data from the card I/O circuit218and writes the latched write data into the memory unit216in synchronism with an internal clock signal generated within the card controller214(step S246ofFIG. 8).

FIG. 9shows a memory card system500according to an alternative embodiment of the present invention. Elements having the same reference number inFIGS. 5 and 11refer to elements having similar structure and/or function. The memory card system500ofFIG. 9has a memory card502with a memory unit504including a first read clock signal generator505and with a card controller506having a second read clock signal generator507.

When the memory unit504is transferring read data to the card controller506, the memory unit504also transfers a first read clock signal RD_CLK1from the first read clock signal generator505to the card controller506. Thus, the card controller506and the memory unit504ofFIG. 9operate similarly for any read operation as already described between the host202and the card204, respectively, forFIG. 5.

Similarly, when the card controller506is transferring read data to the card connection unit220, the card controller506also transfers a second read clock signal RD_CLK2from the second read clock signal generator507to the card connection unit220. Thus, the card connection unit220and the card controller506ofFIG. 9operate similarly for any read operation as already described between the host202and the card204, respectively, forFIG. 5.

The foregoing is by way of example only and is not intended to be limiting. For example, any number of elements as illustrated and described herein is by way of example. The present invention is limited only as defined in the following claims and equivalents thereof.