Memory device comprising status circuit and operating method thereof

A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2.016-0182659 filed Dec. 29, 2016, in the Korean Intellectual Property Office, the entire contents of which are incorporated by reference herein.

Technical Field

Embodiments of the inventive concept disclosed herein relate to a semiconductor memory device, and more particularly, to a memory device including a status circuit and an operating method thereof.

Discussion of the Related Art

In a process of manufacturing a memory cell, an error may occur in the memory cell due to a nanofabrication process. The error may be roughly classified as a hard error or a soft error. The hard error may refer to a case where a memory cell hardware is damaged. The soft error may refer to a case where a memory cell hardware is not damaged, but data of the memory cell temporarily transitions due to alpha particles and so on. The hard error may be corrected through the spare memory cell SMC or an error correction operation. The soft error may be corrected through an error correction operation.

In addition to errors occurring from the manufacture of memory cells, operation error or failure of the memory device may occur due to decreases in supply voltage. As memory cell characteristics deteriorate due to nanofabrication processes or supply voltage decreases or variations, a volatile memory device such as a dynamic random access memory (DRAM) may require excessive refresh operations to retain data stored therein. To cope with a high-performance trend, also, memory devices are made to perform, for example, a write, operation, a read operation, etc. at higher speeds.

In the above-described case of a refresh, read, and write operations being performed, a voltage may not be smoothly supplied within the memory device because current consumption temporarily increases. Accordingly, issues may occur in the memory device such as a decrease in the timing margin and instability of a supply voltage. As a result, an operation failure of the memory device may occur.

SUMMARY

Embodiments of the inventive concept provide a memory device including a status circuit that stores operational information when an operation failure of the memory device occurs and an operating method thereof.

According to an aspect of an embodiment of the inventive concept, a memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal. The status circuit may be configured to update operation information and store the updated operation information in response to an update control signal being received from the command decoder.

According to an embodiment of the inventive concept, an operating method of a memory device includes sequentially storing, at a status circuit included in the memory device, operational information of the memory device determined based on a command, receiving, at the status circuit, an output control signal, and providing, at the status circuit, the plurality of operational information, which are sequentially stored, to a host in response to the output control signal.

According to an embodiment of the inventive concept, an operating method of a memory device includes detecting, at a host, an operational failure of the memory device and generating an update control signal, storing, at a status circuit included in the memory device, operational information of the memory device, which is determined based on a command from the host, in response to the update control signal, and providing, at the status circuit, the stored operational information to the host in response to an output control signal from the host.

According to an embodiment of the inventive concept, a memory device includes: a logic circuit disposed on a substrate; at least first and second memory circuits vertically stacked on the logic circuit, the first and second memory circuits having a respective first input/output (i/o) interface and a second i/o interface; a status circuit configured to communicate with the first and second memory circuits via the first i/o interface and the second i/o interface, respectively, and the status circuit is configured to communicate with a host; wherein the status circuit receives and stores operation status information from each of the at least first and second memory circuits in response to an update control signal being received, and wherein the status circuit provides the stored operation status information of the at least first and second memory circuits in response to a single output control signal being received.

The status circuit may periodically update the stored operation status information of the at least first and second memory circuits in response to an update control signal being provided from the host.

The at least first and second memory circuits are connected to each other by through silicon vias (TSVs).

The status circuit may be additionally configured to communicate with the at least first and second memory circuit using the TSVs.

The logic circuit may include the status circuit.

The status circuit is configured to receive and store operation status information from the at least first and second memory devices through the first and second interfaces and the TSVs.

The status circuit may receives the output control signal from the host when the host compares output data of the at least first and second memory circuits of the memory device with expected data and detects an operation failure of the memory device.

The status circuit may receive the update control signal from the host when the host detects the operation failure of the memory device.

In response to the output control signal being received by the status circuit, the stored operation status information provided to the host may include status information periodically provided to the status circuit prior to the operation failure of the memory device detected by the host.

A plurality of solder balls may be connected to a substrate, and the status circuit provides the stored operation status information to the host through at least a portion of the plurality of solder balls.

The operation status information includes at least one of a command, an address, and input/output data that correspond to an operation of each of the at least first and second memory devices.

At least one operation information output by the status circuit comprises operation status information provided at random time intervals, or periodically provided to the status circuit prior to the operation failure of the memory device.

According to an embodiment of the inventive concept, a memory device includes: a substrate; an interposer disposed on the substrate; one or more processors arranged on the interposer; a memory circuit arranged on the interposer; and a status circuit connected to the memory circuit that is controlled by the one or more processors, the status circuit is configured to store operation status information. In response to a command sent from the one or more processors, the status circuit provides operation status of the memory circuit that includes information prior to the one or more processors detecting an operation failure of the memory circuit.

In response to an update control signal received by the status circuit, the operation status of the memory circuit is updated and stored.

The memory circuit may include a plurality of vertically stacked memory circuits having respective input/output (i/o) interfaces, and the operation status of the plurality of vertically stacked memory circuits may be provided by the status circuit to the one or more processors in response to a single output control signal.

The memory circuit may communicate with the one or more processors through the interposer.

The plurality of vertically stacked memory circuits are connected to each other by through silicon vias (TSVs).

DETAILED DESCRIPTION

Embodiments of the inventive concept may be described in detail to permit a person of ordinary skill in the art to implement the inventive concept.

FIG. 1is a block diagram illustrating a memory system according to an embodiment of the inventive concept. Referring toFIG. 1, a memory system1000may include a host1100and a memory device1200. For example, the memory system1000may be a single system that includes both the host1100and the memory device1200. Alternatively, the host1100and the memory device1200of the memory system1000may be implemented with separate devices, respectively.

The host1100may be a processor circuit or system that includes a general-purpose processor or an application processor. Alternatively, the host1100may be one the following computing devices including one or more processors: a personal computer, a peripheral device, a digital camera, personal digital assistant (PDA), a portable media player (PMP), a smartphone, a tablet computer, or a wearable device, just to name some non-limiting possibilities. The processors include integrated circuits operable in hardware or in conjunction with software.

The memory device1200may store data provided from the host1100or data to be provided to the host1100. The memory device1200may be implemented with storage media of any known type, each of which includes a volatile memory or a nonvolatile memory. For example, in the case where the memory device1200comprises a volatile memory, the memory device1200may include, for example, a dynamic random access memory (DRAM), a static RAM (SRAM), a thyristor RAM (TRAM), a zero capacitor RAM (Z-RAM), a twin transistor RAM (TTRAM), a magnetoresistive RAM (MRAM), etc. For example, in the case where the memory device1200includes a volatile memory, the memory device1200may include an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), Non Volatile DIMM (NVDIMM), a high bandwidth memory (HBM), etc.

For example, in the case where the memory device1200comprises a nonvolatile memory, the memory device1200may be embodied as an electrically erasable programmable read-only memory (EEPROM), a flash memory, an MRAM, a spin-transfer torque MRAM (STT-MRAM), a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM (RRAM), a polymer RAM (PoRAM), a nano-floating gate memory (NFGM), a holographic memory, a molecular electronics memory device, or an insulator resistance change memory. One or more bits may be stored in a unit cell of the nonvolatile memory. The above-described examples do not limit the scope of the inventive concept.

Below, for ease of description, it is assumed that the memory device1200includes a single memory device. However, as described above, a person of ordinary skill in the art should understand that the embodiments may be applied to various types storage devices in addition to those mentioned herein above.

The memory device1200may communicate with the host1100through an interface utilizing a communication protocol. For example, the memory device1200may communicate with the host1100based on one or more of various wired communication protocols, such as a universal serial bus (USB), a small computer system interface (SCSI), PCIe, a mobile PCIe (M-PCIe), advanced technology attachment (ATA), parallel ATA (PATA), serial ATA (SATA), serial attached SCSI (SAS), integrated drive electronics (IDE), Firewire, universal flash storage (UFS), a transmission control protocol/Internet protocol (TCP/IP), and various wireless communication protocols, such as long term evolution (LTE), WiMax, global system for mobile communication (GSM), code division multiple access (CDMA), high speed packet access (HSPA), Bluetooth, near field communication (NFC), Wi-Fi, and radio frequency identification (RFID). A person of ordinary skill in the art should understand and appreciate that the above-described examples do not limit the scope of the inventive concept.

The memory device1200may perform, for example, a write operation and/or a read operation in response to a command/address CMD/ADDR from the host1100. The read operation and the write operation of the memory device1200are explained as follows.

For example, in the case of the read operation, the host1100provides an active command and a row address to the memory device1200. After a reference time, the host1100provides a column address to the memory device1200. Next, the memory device1200provides requested data DATA to the host1100after a specific time.

For example, in the case of the write operation, the host1100provides an active command and a row address to the memory device1200. After a reference time, the host1100provides a write command and a column address to the memory device1200. Afterwards, the host1100provides the memory device1200with data to be written. The memory device1200writes the received data in a memory area that is defined by the column and row addresses.

An operation failure occurs in the case where the memory device1200fails to perform an operation normally may occur during the above-described read or write operation. The operation failure may occur because of various reasons. For example, in the case where the memory device1200continuously performs the refresh operation, the read operation, the write operation, etc., an internal supply voltage of the memory device1200may become unstable because a current is being excessively used by a large quantity of operations.

In the case where a core voltage is not being supplied normally to a memory cell array (not illustrated) due to instability of the internal supply voltage, a memory cell of the memory cell array may not be selected or activated normally during the read operation or the write operation. Moreover, a supply voltage of a peripheral circuit that controls an operation of the memory device1200may become unstable for the same reasons discussed hereinabove. In such a case, a transmission timing of signals transmitted in the memory device1200may change. The changed transmission timing may be one reason that a timing margin of the signals is insufficient.

Alternatively, voltages provided by a voltage generator may become unstable for a number of reasons in addition to the reasons discussed herein above.

For example, a level of a reference voltage, which is provided by the voltage generator to a data input driver (not illustrated) of the memory device1200, may become unstable. In this case, the data input driver may fail to determine a logical level of data DATA provided from the host1100normally. The inability of the data driver to determine a logical level of data can result in a retry of the operation, which will slow the performance of the memory device. On the other hand, the operation being executed may have a catastrophic failure if the data driver is not able to determine the logical level of data even for a relatively brief period of time. Thus, the memory device1200may fail to perform the read operation, the write operation, etc. normally due to such above-described causes such as an unstable supply voltage, insufficient timing margin, and an unstable reference voltage.

According to an embodiment of the inventive concept, the memory device1200may include a status circuit1260. The status circuit permits a more exact determination as to the cause of the failure. In the case where the above-described operation failure occurs, the status circuit1260stores operation status information associated with the operation failure. Also, the status circuit1260may output the stored operation status information to the host1100. For example, the status circuit1260may operate in response to a control signal received or generated during a test operation. For example, the control signal may be provided from the host1100, or the control signal may be generated as a result of sensing an internal signal of the memory device1200.

A configuration of the memory device1200that includes the status circuit1260storing the operation status information when the operation failure of the memory device1200occurs is briefly described above. Through the above-described configuration, in the case where the operation failure of the memory device1200occurs, the memory device1200may provide the operation status information to the host1100or a user. The inclusion of the status circuit in the configuration of the memory may make analysis of the operation failure of the memory device1200easier, and may reduce the time utilized to test the memory device1200when a failure occurs.

FIG. 2is a block diagram providing more detail with regard to the memory device illustrated inFIG. 1. The block diagram ofFIG. 2will be described with reference toFIG. 1. Referring toFIG. 2, a memory device1200amay include, for example, a command/address latch1210, a clock buffer1220, a command decoder1230, a voltage generator1240, a core area1250, the status circuit1260referred to herein above, and a data input/output driver1270.

The command/address latch1210may receive a command CMD and an address ADDR from the host1100. The command/address latch1210provides the received command to the command decoder1230. Also, the command/address latch1210provides the received address of a memory cell to a row decoder1253and a column decoder1254. The address of the memory cell may include a row address RA and a column address CA.

The clock buffer1220is provided with an input of a clock signal CLK and a clock bar signal CLKb from the host1100through a clock pad CLK_p and a clock bar pad CLKb_p. For example, the clock buffer1220may be implemented to include a differential input buffer. The clock buffer1220may generate an internal clock signal based on the clock signal CLK and the clock bar signal CLKb that are received, for example, from an external device. The internal clock signal generated by the clock buffer is provided to the command decoder1230.

The command decoder1230is provided with various commands through the command/address latch1210that are decoded. The command decoder1230is provided with the internal clock signal generated by the clock buffer1220. The command decoder1230decodes the command from the command/address latch1210based on the internal clock signal received from the clock buffer1220, and generates a decoding command CMD_i. The command decoder1230provides the decoding command CMD_i to components such as the row decoder1253, the column decoder1254, and the status circuit1260. Also, the command decoder1230may generate a control signal CTRL for controlling the status circuit1260based on the provided internal clock signal from the clock buffer or command received from the command/address latch1210. The control signal CTRL is provided to the status circuit1260. The control signal CTRL will be more fully described with reference toFIGS. 3 and 6herein below.

The voltage generator1240generates various voltages that are utilized for an operation of the memory device1200a. For example, the voltage generator1240may generate a reference voltage provided to the data input/output driver1270to determine logic of data provided from the host1100and may provide the reference voltage to the data input/output driver1270. Alternatively, the voltage generator1240may generate a word line voltage, a bit line voltage, an operating voltage of a core, etc. that are needed for an operation of a memory cell array1251and may provide these generated voltages to the core area1250. To generate various voltages, the voltage generator1240may include a voltage pump circuit (not illustrated) for boosting a voltage. Although not illustrated inFIG. 2, to generate various voltages, the voltage generator1240may be provided with a voltage from a source (e.g., the host1100) external to the memory device1200a.

The core area1250may include the memory cell array1251, a sense amplifier1252, the row decoder1253, and the column decoder1254. The memory cell array1251, the sense amplifier1252, the row decoder1253, and the column decoder1254may operate using the various voltages provided from the voltage generator1240.

Data stored in the memory cell array1251may be provided to the data input/output driver1270through the sense amplifier1252. The sense amplifier1252may have an interface to receive data from the memory cell array and output the data to the data input/output driver. Alternatively, data provided from the host1100may be stored in the memory cell array1251through the sense amplifier1252and the data input/output driver1270. An address that is used to store or read data in or from a memory cell may be provided to the memory cell array1251through the command/address latch1210, the row decoder1253, and the column decoder1254. In such a case, the column decoder provides the decoded column address (CA) and the row decoder1253provides the decoded row address (RA) to the memory cell array1251.

With continued reference toFIG. 2, the status circuit1260may store operation status information STATUS associated with an operation failure in response to the control signal CTRL provided from the command decoder1230. For example, the status circuit1260may operate only during a test operation of the memory device1200a. Also, the status circuit1260may output the stored operation status information STATUS to the host1100through the data input/output driver1270and a DQ pad DQ_p in response to the control signal CTRL. Moreover, the status circuit may include, the status output information for a predetermined number of test operations, or for a predetermined period, at which point the status information may be stored externally from the memory device for access by the host.

For example, the operation status information STATUS may include at least one of the row address RA and the column address CA from the command/address latch.1210, the decoding command CMD_i from the command decoder1230, data DATA provided from the host1100to the data input/output driver1270during a write operation, and data DATA to be output to the host1100during a read operation, in the case where an operation failure of the memory device1200aoccurs.

Alternatively, the operation status information STATUS may include at least one of the decoding command CMD_i, the row address RA and the column address CA, and data DATA input and output by the data input/output driver1270at a plurality of time points before an operation failure occurs. By providing information at a plurality of time points before an operation failure occurs, the determination of the cause of operation failure can be enhanced. This information may be stored in a buffer and may be written over with new information as operations progress without an operation failure.

The status circuit1260may be reset only at power up of the memory device1200a. For example, the status circuit1260may not be reset by an external reset signal after the memory device1200astarts to operate by a power-up operation. Accordingly, even in a case where the memory device1200aresets an operating environment in response to receiving the external reset signal after the operation failure occurs, the operation status information STATUS that is associated with the operation failure and is stored in the status circuit1260may not be reset.

The status circuit1260may be implemented, for example, with a multi-purpose register. Information of an operation status stored in the status circuit1260implemented with the multi-purpose register may be output to the host1100in response to a command provided from the host1100. However, the inventive concept is not limited to an implementation of a multi-purpose register. An operation of the multi-purpose register may be defined by the JEDEC (Joint Electron Device Engineering Council) specification.

With continued reference toFIG. 2, the data input/output driver1270determines a logical level of data DATA provided from the host1100through the DQ pad DQ_p, based on the reference voltage (Vref) that is output by the voltage generator1240. The data input/output driver1270provides the determined data DATA to the sense amplifier1252. The data input/output driver1270may output data read from the memory cell array1251to the host1100through the DQ pad DQ_p. To this end, memory cells of the memory cell array1251, in which data for input/output are stored, may be selected by the row decoder1253and the column decoder1254that are provided with the address. The data input/output driver1270may provide the status circuit1260with input/output data DATA_io provided to the sense amplifier1252or from the sense amplifier1252. The data input/output driver1270outputs the operation status information STATUS provided from the status circuit1260to the host1100.

FIG. 3is a block diagram illustrating the status circuit shown inFIG. 2. The block diagram ofFIG. 3will be described with reference toFIGS. 1 and 2. Referring toFIG. 3, a status circuit1260amay include first, second and third registers1261,1262and1263, and an AND gate.

The status circuit1260aofFIG. 3may store a first operation status information STATUS [0] when an operation failure of the memory device1200aoccurs, and a second and a third operation status information (STATUS [1] and STATUS [2]) at two time points prior to the occurrence of the operation failure. A point in time when the second and third operation status information STATUS [1] and STATUS [2] are stored may change according to a way an update control signal CTRL_u is provided. The update control signal CTRL_u will be more fully described below.

The control signal CTRL illustrated inFIG. 2may include the update control signal CTRL_u and an output control signal CTRL_o. The update control signal CTRL_u is used to allow the status circuit1260ato update and store operation status information. For example, in the case where the update control signal CTRL_u is activated, the first to third registers1261to1263update and store the first to third operation status information STATUS[0], STATUS[1] and STATUS[2], As shown in the example inFIG. 3, there is an AND gate in which the update control signal CTRL_u is one input and the output control signal CTRL_o is the other input.

In the embodiment ofFIGS. 2 and 3, the update control signal CTRL_u may be provided from the command decoder1230. For example, the update control signal CTRL_u may be generated by the command decoder1230whenever a valid command for a write, read, activation, or precharge operation, etc. is provided from the host1100to the memory device1200a. Alternatively, the update control signal CTRL_u may be generated by the command decoder1230whenever an operation state of the memory device1200ais changed.

In an embodiment of the inventive concept, the update control signal CTRL_u may be formed of the internal clock signal provided front the clock buffer1220. The first to third registers1261to1263periodically update and store the first to third operation status information STATUS [0], STATUS [1] and STATUS [2] in response to the update control signal CTRL_u formed of the internal clock signal. In this case, the status circuit1260amay be provided with the update control signal CTRL_u from the clock buffer1220and the output control signal CTRL_o from the command decoder1230.

Below, for ease of description, it is assumed that the update control signal CTRL_u is generated by the command decoder1230whenever a valid command for a write, read, activation, or precharge operation, etc. is provided from the host1100. The update control signal CTRL_u is provided to the status circuit1260a. However, it may be understood from various embodiments to be described below that examples of the above-described update control signal CTRL_u may be easily applied.

With continued reference toFIG. 3, the update control signal CTRL_u is provided to each of the first to third registers1261,1262and1263as a register control signal CTRL_r through the AND gate. The AND gate is provided with the update control signal CTRL_u and the output control signal CTRL_o. The AND gate outputs the update control signal CTRL_u as the register control signal CTRL_r without modification when the output control signal CTRL_o is activated to logic “1”. The AND gate outputs the output control signal CTRL_o as the register control signal CTRL_r regardless of the update control signal CTRL_u when the output control signal CTRL_o is deactivated to logic “0”.

The output control signal CTRL_o is used to output the first to third operation status information STATUS [0:2] being stored in the status circuit1260ato the host1100. In the embodiment shown inFIGS. 2 and 3, the output control signal CTRL_o may be provided from the host1100when an operation failure of the memory device1200ais detected.

For example, the host1100may determine the operation failure of the memory device1200aby comparing data read from the memory device1200awith expected data. The host1100commands that the memory device1200aoutputs the operation status information STATUS, by using a combination of a command and an address. The command decoder1230of the memory device1200adecodes the provided command and address to generate the output control signal CTRL_o. The first to third registers1261to1263output the first to third operation status information STATUS [0] to STATUS [2] to the host1100through the data input/output driver1270in response to the provided output control signal CTRL_o.

In an embodiment of the inventive concept, the output control signal CTRL_o may be generated when an abnormal situation of a specific signal or voltage being monitored in the memory device1200ais detected. Alternatively, the output control signal CTRL_o may be provided from the host1100through a dedicated pad. Various embodiments will be discussed herein below in which the output control signal CTRL_o is provided.

With reference toFIG. 3, the first to third registers1261to1263may constitute a shift register. An operation of the first to third registers1261to1263is as follows. In response to the update control signal CTRL_u from the command decoder1230or the clock buffer1220, the first to third registers1261to1263store the operation status information periodically or randomly provided before an operation failure of the memory device1200aoccurs. In the case where the operation failure of the memory device1200aoccurs, in response to receiving the output control signal CTRL_o from the host1100, the first to third registers1261to1263output the operation status information that corresponds to a time point at which the operation failure of the memory device1200aoccurs, and a plurality of time points before the operation failure occurs.

The first to third registers1261to1263may be configured the same. Three registers are illustrated inFIG. 3as one possible example. However, embodiments of the inventive concept may not be limited thereto. For example, the number of registers may be changed according to the number of time points, which correspond to a target to be checked, from among time points before the operation failure occurs. Below, the first register1261of the first to third registers1261to1263will be described as an example.

The first register1261may include a plurality of sub registers1261_1,1261_2,1261_3. The sub registers1261_1to1261_3are provided with the row and column addresses RA and CA, the decoding command CMD_i, and the input/output data DATA_io from the command/address latch1210, the command decoder1230, and the data input/output driver1270, respectively. In the case where the register control signal CTRL_r is activated, the sub registers1261_1to1261_3may update and store the row and column addresses RA and CA, the decoding command CMD_i, and the input/output data DATA_io, by which an operation of the memory device1200awhen it is determined that the register control signal CTRL_r is activated.

In the embodiment shown inFIG. 3, the sub register1261_1may be an address-dedicated register configured to store the row address RA and the column address CA. The sub register1261_2may be a command-dedicated register configured to store the decoding command CMD_i. The sub register1261_3may be a data-dedicated register configured to store the input/output data DATA_io.

AlthoughFIG. 3shows the number of sub registers1261_1to1261_3being three, a person of ordinary skill it the art should appreciate that the inventive concept is not be limited to three sub registers. For example, the number of the sub registers1261_1to1261_3and sizes thereof may be determined to store all of the above-described data RA, CA, CMD_i, and DATA_io.

For example, the input/output data DATA_io may be provided to the status circuit1260awith a bus size corresponding to the number of DQ pads DQ_p. For example, in the case where the number of DQ pads DQ_p is “16”, the bus of the input/output data DATA_io may include 16 transmission lines. Accordingly, the input/output data DATA_io may be provided to the status circuit1260athrough the bus including 16 transmission lines. Also, the input/output data DATA_io may include a serial bit stream of a length that is determined according to a burst length. The input/output data DATA_io including the serial bit stream may be input and output in response to one command. The sub register1261_3may be configured to store data including the size of the bus and a plurality of serial bit streams, in size and number.

In the case where the register control signal CTRL_r is activated, the first register1261provides the second register1262with the operation status information composed of an address, a command, and data stored in the first register1261. Also, the first register1261updates and stores the operation status information in response to the activated register control signal CTRL_r.

Similar to the above description, in the case where the register control signal CTRL_r is activated, the second register1262provides the third register1263with the operation status information composed of an address, a command, and data stored in the second register1262. Next, the second register1262updates and stores the operation status information in response to the activated register control signal CTRL_r. In the case where the register control signal CTRL_r is activated, the third register1263updates and stores the operation status information. In the above description, the first to third registers1261to1263may collectively constitute a shift register. The first to third registers1261to1263output the stored first, second and third operation status information STATUS[0], STATUS [1], STATUS[2] to the host1100through the data input/output driver1270and the DQ pad DQ_p in response to the output control signal CTRL_o.

FIG. 4is a flowchart illustrating an operation of the status circuit1260aofFIG. 3, andFIG. 5is a timing diagram illustrating an operation of the status circuit ofFIG. 3.FIGS. 4 and 5will be described with reference to the structure shown inFIGS. 1 to 3.

Referring toFIG. 4, in operation S110, the status circuit1260aof the memory device1200aupdates and stores the operation status information STATUS in response to the update control signal CTRL_u and the register control signal CTRL_r. As described above, the status circuit1260astores the operation status information at periodic or random points until the output control signal CTRL_o is activated.

In operation S120, an operation failure of the memory device1200ais detected. For example, as described above, the host1100may determine the operation failure of the memory device1200aby comparing data read from the memory device1200awith expected data. If the read data are different from the expected data, the host1100may determine that an operation failure of the memory device1200ahas occurred.

In an embodiment of the inventive concept, in the case where the memory device1200aincludes a comparator for comparing test data, the memory device1200amay detect the operation failure through a data comparison operation. Alternatively, the memory device1200amay detect the operation failure based on a result of monitoring a voltage drop of a specific voltage of the memory device1200a. Various embodiments in which the operation failure of the memory device1200ais detected and the output control signal CTRL_o is generated will be more fully described below. A person of ordinary skill in the art understands that the example embodiments disclosed herein below are provided for illustrative purposes, and the inventive concept is not limited to the examples.

If the operation failure is detected, in operation S130, the status circuit1260ais provided with the output control signal CTRL_o. In the case where the operation failure is detected by the above-described methods, the output control signal CTRL may be generated in the host1100or the memory device1200a. The status circuit1260ais provided with the generated output control signal CTRL_o.

In operation S140, the status circuit1260aoutputs the first to third operation status information STATUS [0:2] to the host1100in response to the output control signal CTRL_o.

FIG. 5illustrates a timing diagram of internal signals of the memory device1200agenerated according to an operation of the status circuit1260ais illustrated inFIG. 5. In a time period from t0to t1, the memory device1200aperforms a write or read operation in response to a command and an address provided from the host1100. For example, in the case where an operation of the memory device1200ais tested by the host1100, under control of the host1100, the memory device1200amay perform an operation based on a pattern of IDD5, IDD7, etc. that are defined by the JEDEC specification.

Before the time point t1, the status circuit1260astores the operation status information STATUS of the memory device1200ain response to the update control signal CTRL_u. The update control signal CTRL_u is illustrated inFIG. 5as being generated whenever a valid command Valid is provided to the memory device1200a. However, as described above, the update control signal CTRL_u as may be generated whenever an operation status of the memory device1200ais changed or may be provided as a clock signal. At the time point t1, an operation failure of the memory device1200amay be detected.

In a time period from t1to t2, the output control signal CTRL_o is generated due to the operation failure of the memory device1200aoccurring at the time point t1. The status circuit1260aoutputs the first to third operation status information STATUS [0:2] to the host1100in response to the generated output control signal CTRL_o.

In a time period from t2to t3, the host1100resets an operating environment of the memory device1200a. For example, the operating environment may include an operating voltage, an operating frequency, etc. of the memory device1200a. The host1100analyzes the operation status information of the memory device1200ain which the operation failure occurs. Next, the host1100may change the operating environment of the memory device1200asuch that the memory device1200aoperates normally in the corresponding operation status. In the corresponding time period, the memory device1200ais deselected (DES) and does not operate. However, as described above, the status circuit1260ais not reset such that the stored first to third operation status information STATUS [0:2] are retained.

With continued reference toFIG. 5, in a time period from t3to t4, the memory device1200aoperates normally after being reset between t2to t3. In a time period from t3to t5, operations of the host1100and the memory device1200aare the same as those in a time period from t0to t2. For example, in the time period from t3to t4, the status circuit1260astores the operation status information STATUS of the memory device1200ain response to the update control signal CTRL_u. In the time point t4, an operation failure of the memory device1200ais detected. In a time period from t4to t5, the status circuit1260aoutputs the stored first to third operation status information. STATUS [0:2] to the host1100in response to the generated output control signal CTRL_o. After the time point t5, the memory device1200ais reset by the host1100.

FIG. 6is a block diagram illustrating the status circuit illustrated inFIG. 2, according to an embodiment of the inventive concept. The block diagram ofFIG. 6will be described with reference toFIGS. 1 and 2. Referring toFIG. 6, a status circuit1260bmay include a register1264. As described above, the control signal CTRL may include the update control signal CTRL_u and the output control signal CTRL_o.

Compared with the status circuit1260aofFIG. 3, the status circuit1260bofFIG. 6may store the operation status information STATUS in response to the update control signal CTRL_u that is generated when the operation failure of the memory device1200aoccurs. For example, the status circuit1260bdoes not operate before the operation failure occurs. After the status circuit1260bstores the operation status information STATUS, the status circuit1260boutputs the stored operation status information STATUS to the host1100in response to the output control signal CTRL_o.

In the embodiments ofFIGS. 2 and 6, it may be possible to detect the operation failure of the memory device1200athrough the various methods described with reference toFIGS. 4 and 5. In this case, the update control signal CTRL_u may be provided from the host1100, or may be generated in the memory device1200a.

For example, the update control signal CTRL_u may be provided from the host1100when the operation failure of the memory device1200ais detected. The host1100may determine the operation failure of the memory device1200aby comparing data read from the memory device1200awith expected data. The host1100controls the memory device1200ato output the operation status information STATUS, by using a combination of a command and an address. The command decoder1230of the memory device1200adecodes the provided command and address to generate the update control signal CTRL_u. The register1264outputs the operation status information STATUS to the host1100through the data input/output driver1270in response to the provided update control signal CTRL_u.

In an embodiment of the inventive concept, the update control signal CTRL_u may be generated when an abnormal situation of a specific signal or voltage being monitored in the memory device1200ais detected. For example, in the case where at least one of voltages generated by the voltage generator1240is lower than a preset level, the voltage generator1240may generate the update control signal. CTRL_u. The update control signal CTRL_u may be generated through in a number of ways as previously discussed.

The status circuit1260boutputs the stored operation status information STATUS in response to receiving the output control signal CTRL_o. In the embodiment ofFIG. 6, the output control signal CTRL_o is provided from the command decoder1230under control of the host1100.

A configuration and an operation of the register1264are similar to those of each of the first to third registers1261to1263illustrated inFIG. 3. For example, the register1264may include a plurality of sub registers1264_1to1264_3. Configurations and operations of the sub registers1264_1to1264_3are the same or similar as described with reference toFIG. 3and a description thereof is thus omitted.

The sub registers1264_1to1264_3are provided with the row and column addresses RA and CA, the decoding command CMD_i, and the input/output data DATA_io from the command/address latch1210, the command decoder1230, and the data input/output driver1270, respectively. In the case where the update control signal CTRL_u is activated, the sub registers1264_1to1264_3update and store the row and column addresses RA and CA, the decoding command CMD_i, and the input/output data DATA_io, by which an operation of the memory device1200awhen the update control signal CTRL_u is activated is determined. The status circuit1264boutputs the operation status information STATUS to the host1100through the data input/output driver1270and the DQ pad DQ_p in response to the output control signal CTRL_o.

FIG. 7is a flowchart illustrating an operation of the status circuit1260bofFIG. 6, andFIG. 8is a timing diagram further illustrating an operation of the status circuit ofFIG. 6.FIGS. 7 and 8will be described with reference toFIGS. 1, 2, and 6.

In operation S210, an operation failure of the memory device1200ais detected. An example of one way the operation failure of the memory device1200amay be detected is described with reference toFIGS. 4 and 6. Also, as described above, another way the operation failure may be detected win be described with reference toFIG. 10. In the case where the operation failure of the memory device1200ais detected, the update control signal CTRL_u may be generated in the host1100or by the memory device1200a. The update control signal CTRL_u is provided to the status circuit1260b.

In operation S220, the status circuit1260bupdates and stores the operation status information STATUS in response to the provided update control signal CTRL_u. The updated status information can be used to analyze the operation failure.

In operation S230, the status circuit1260bis provided with the output control signal. CTRL_o from the host1100. In operation S240, the status circuit1260boutputs the operation status information STATUS to the host1100in response to the output control signal CTRL_o. The host will typically analyze status information and control action of the memory device in view of the operation failure.

FIG. 8provides a timing diagram of internal signals of the memory device1200agenerated according to an operation of the status circuit1260b. In a time period from t0to t1, the memory device1200aperforms a write or read operation, etc. in response to a command and an address provided from the host1100. As described in the time period from t0to t1ofFIG. 5, under control of the host1100, the memory device1200amay perform an operation based on a pattern of IDD5, IDD7, etc. that are defined by the JEDEC specification.

At a time point t1, an operation failure of the memory device1200ais detected, and the update control signal CTRL_u is activated to a logic “0”. Also, in response to the activated update control signal CTRL_u, the status circuit1260bupdates and stores the operation status information STATUS of the memory device1200aat the time point t1.

With continued reference toFIG. 8, in a time period from t1to t2, the host1100resets an operating environment of the memory device1200a. In the corresponding time period, the memory device1200ais deselected and does not operate. However, as described above, the status circuit1260bis not reset such that the stored operation status information STATUS is retained.

In a time period from t2to t3, the memory device1200aoperates in the reset operating environment. At a time point t3, the memory device1200ais provided with a command from the host1100for outputting the operation status information STATUS. The command decoder1230of the memory device1200agenerates the output control signal CTRL_o of logic “1” based on the provided command.

In a time period from t3to t4, the status circuit1260boutputs the operation status information STATUS to the host1100in response to receiving the output control signal CTRL_o. The operation status information STATUS includes operation status information of the memory device1200awhen the operation failure occurs. At a time point t4, an operation failure of the memory device1200ais detected as described at the time point t1As the operation failure of the memory device1200ais detected, the update control signal CTRL_u is activated to the logic “0”. The status circuit1260bupdates and stores the operation status information STATUS of the memory=device1200aat the time point t4. After the operation status information STATUS is updated, the host1100resets an operating environment of the memory device1200a.

FIGS. 9 to 11are block diagrams illustrating the memory device illustrated inFIG. 1, according to an embodiment of the inventive concept. The block diagrams ofFIGS. 9 to 11will now be described with reference toFIGS. 1 to 8.

Referring now toFIG. 9, a memory device1200bmay include the command/address latch1210, the clock buffer1220, the command decoder1230, the voltage generator1240, the core area1250, the status circuit1260, and the data input/output driver1270. Also, the memory device1200bmay further include a CTRL pad CTRL_p for receiving the control signal CTRL, which is shown as being connected to the status circuit1260.

Compared with the status circuit1260of the memory device1200aofFIG. 2, the status circuit1260of the memory device1200bshown inFIG. 9is provided with the control signal CTRL through the CTRL pad CTRL_p from the host1100. InFIG. 2, the status circuit1260receives the control signal CTRL from the command decoder1230. Accordingly, the command decoder1230shown inFIG. 9provides the decoding command CMD_i to the status circuit1260, but does not provide the control signal CTRL to the status circuit1260.

As described above, the control signal CTRL may include both the update control signal CTRL_u and the output control signal CTRL_o. Accordingly, although not illustrated inFIG. 9, the CTRL pad CTRL_p may include two pads for receiving the update control signal CTRL_u and the output control signal CTRL_o, respectively.

The CTRL pad CTRL_p may include an existing pad that is used for an operation of the memory device1200b. For example, the CTRL pad CTRL_p may include a data bus inversion (DBI) pad, a data mask (DM) pad, a PAR pad, etc. For example, the memory device1200bmay use a pad, which is not used during an operation such as a read operation or a write operation, as the CTRL pad CTRL_p.

Except for the above description, configurations and operations of the command/address latch1210, the clock buffer1220, the command decoder1230, the voltage generator1240, the core area1250, the status circuit1260, and the data input/output driver1270are similar to or the same as described with reference toFIG. 2.

The status information STATUS of the memory device1200bwill be stored and output as follows. In the case where an operation failure of the memory device1200boccurs, the status circuit1260is provided with the update control signal CTRL_u from the host1100through the CTRL pad CTRL_p. In response to the update control signal CTRL_u, the status circuit1260stores the operation status information STATUS associated with the operation failure that is occurring.

Next, the status circuit1260is provided with the output control signal CTRL_o from the host1100through the CTRL pad CTRL_p. The status circuit1260outputs the stored operation status information STATUS to the host1100through the data input/output driver1270and the DQ pad DQ_p in response to the output control signal CTRL_o.

Referring toFIG. 10, a memory device1200cmay include the command/address latch1210, the clock buffer1220, the command decoder1230, the voltage generator1240, the core area1250, the status circuit1260, and the data input/output driver1270.

Compared with the status circuit1260of the memory device1200aofFIG. 2, the status circuit1260of the memory device1200cinFIG. 10is provided with the output control signal CTRL_o from the voltage generator1240, whereas inFIG. 2the output control signal CTRL_o is received from the command decoder1230. Accordingly, the command decoder1230provides the decoding command CMD_i and the update control signal CTRL_u to the status circuit1260and does not provide the output control signal CTRL_o to the status circuit1260. However, as described with reference toFIG. 2, the status circuit1260may be provided with the internal clock signal from the clock buffer1220as the update control signal CTRL_u.

The voltage generator1240generates various voltages that are needed for an operation of the memory device1200c. In the case where at least one of voltages generated by the voltage generator1240is lower than a preset voltage due to an unstable supply voltage, the memory device1200cmay fail to perform a normal operation. In this case, the voltage generator1240may determine that an operation failure of the memory device1200chas occurred and may generate the output control signal CTRL_o. The generated output control signal CTRL_o is provided to the status circuit1260.

Except for the above description regardingFIG. 10, the configurations and operations of the command/address latch1210, the clock buffer1220, the command decoder1230, the voltage generator1240, the core area1250, the status circuit1260, and the data input/output driver1270are similar to or the same as described with reference toFIG. 2.

The status information STATUS of the memory device1200cwill be stored and output as follows. First, in response to the update control signal CTRL_u provided from the command decoder1230, the status circuit1260stores operation status information periodically or randomly prior to the output control signal CTRL_o is provided from the voltage generator1240. In the case where the operation failure that a voltage generated by the voltage generator1240is lower than a preset voltage is detected, the voltage generator1240generates the output control signal CTRL_o. The status circuit1260is provided with the output control signal CTRL_o from the voltage generator1240. The status circuit1260outputs the stored operation status information STATUS to the host1100through the data input/output driver1270and the DQ pad DQ_p in response to the output control signal CTRL_o.

Referring now toFIG. 11, a memory device1200dmay include the command/address latch1210, the clock buffer1220, the command decoder1230, the voltage generator1240, the core area1250, the status circuit1260, and the data input/output driver1270. The memory device1200dmay further include a status input/output driver1280, the CTRL pad CTRL_p, and a status pad STA_p.

Compared with the status circuit1260of the memory device1200aofFIG. 2, the status circuit1260of the memory device1200dis provided with the control signal CTRL through the CTRL pad CTRL_p and the status input/output driver1280from the host1100, whereas inFIG. 2the control signal CTRL is received by the status circuit1260from the command decoder1230. Accordingly, the command decoder1230provides the decoding command CMD_i to the status circuit1260, but in the configuration shown inFIG. 11does not provide the control signal CTRL to the status circuit1260. The status input/output driver1280provides the control signal CTRL to the status circuit1260.

As described above, the control signal CTRL may include the update control signal CTRL_u and the output control signal CTRL_o. Accordingly, although not illustrated inFIG. 11, the CTRL pad CTRL_p may include two pads for receiving the update control signal CTRL_u and the output control signal CTRL_o, respectively. Compared with the CTRL pad CTRL_p of the memory device1200bofFIG. 9, the CTRL pad CTRL_p may be implemented with a separate pad that is not associated with an operation of the memory device1200d.

The status circuit1260stores an operation status of the memory device1200din response to the control signal CTRL provided through the CTRL pad CTRL_p and the status input/output driver1280. The status circuit1260outputs the stored operation status information STATUS to the host1100through the status input/output driver1280and the status pad STA_p in response to receiving the control signal CTRL.

With continued reference toFIG. 11, the status input/output driver1280may communicate with the host1100by an interface that is separate from an interface for communicating between the host1100and memory device1200dto perform normal operations such as a read operation and a write operation. Accordingly, the memory device1200dmay receive the control signal CTRL from the host1100even while performing an operation such as the read operation or the write operation. Also, the memory device1200dmay provide the operation status information STATUS to the host1100while performing an operation such as the read operation or the write operation. With the above description, the control signal CTRL may be received from the host1100regardless of the clock signal CLK, and the operation status information STATUS may be output to the host1100regardless of the clock signal CLK. In other words, in this example there is not a dependency on the clock signal CLK to receive the control signal CTRL and to output operation status information.

For example, the status input/output driver1280may communicate with the host1100through the IEEE 1500 interface that is defined by the JEDEC specification. In the case where the status input/output driver1280communicates with the host1100through the IEEE 1500 interface, the CTRL pad CTRL_p may include a wrapper scan in (WSI) pad, and the status pad STA_P may include a wrapper scan out (WSO) pad.

Except for the above description, configurations and operations of the command/address latch1210, the clock buffer1220, the command decoder1230, the voltage generator1240, the core area1250, the status circuit1260, and the data input/output driver1270are similar or the same as described with reference toFIG. 2.

The status information STATUS of the memory device1200dwill be stored and output as follows. In the case where an operation failure of the memory device1200doccurs, the status circuit1260is provided with the update control signal CTRL_u from the host1100through the CTRL pad CTRL_p and the status input/output driver1280. In response to the update control signal CTRL_u, the status circuit1260stores the operation status information STATUS associated with the operation failure that is occurring.

With regard to output of the status information, the status circuit1260is provided with the output control signal CTRL_o from the host1100through the CTRL pad CTRL_p and the status input/output driver1280. The status circuit1260outputs the stored operation status information STATUS to the host1100through the status input/output driver1280and the status pad STA_p in response to the output control signal CTRL_o.

Various embodiments of the status circuit1260and the memory device1200including the status circuit1260according to the inventive concept are described above. However, the inventive concept is not limited to the embodiments described with reference toFIGS. 1 to 11. For example, various embodiments described in this specification may be implemented in which some of the teachings of the embodiments may be combined or some thereof may be omitted. For example, in the memory device1200dofFIG. 11, the status circuit1260may be configured to receive the output control signal CTRL_o from the voltage generator1240as the memory device1200cofFIG. 10. As such, embodiments described in this specification may be easily combined by one skilled in the art.

FIGS. 12 and 13are block diagrams illustrating a memory module including the status circuit, according to an embodiment of the inventive concept. Memory modules10000and20000illustrated inFIGS. 12 and 13have a registered dual in-line memory module (RDIMM) structure. Each of the memory modules10000and20000may include the status circuit1260described with reference toFIGS. 1 to 11.

An A-type memory module10000having the RDIMM form is illustrated inFIG. 12. The A-type memory module10000may include a memory device11000, a command/address (CA) register12000, and a CA transmission line13000.

The memory device11000is connected with the CA register12000through the CA transmission line13000. To reduce the load of an output part of a host, the CA register12000may serve as a buffer of an address or a command to be sent from the host to the memory device11000. The CA transmission line13000may include termination resistors T at ends of the CA transmission line13000to remove a reflected wave generated when a command/address is transmitted.

In the RDIMM structure, in the case where a host accesses the memory device11000, the host directly exchanges data with the memory device11000through an independent transmission line DQ_G. In contrast, the host provides an address or a command to each memory device11000through the CA register12000.

The CA register12000may include a status circuit12100. In response to the update control signal CTRL_u provided from the host, the status circuit12100of the CA register12000may receive and store operation status information from the memory device11000through the CA transmission line13000. Also, in response to the output control signal provided from the host, the status circuit12100provides the stored operation status information to the host through a CA line CA. Here, the operation status information may include a command and an address that correspond to an operation of the memory device11000. However, the operation status information may not include input/output data that correspond to an operation of the memory device11000.

The CA line CA may have both a direction from the CA register12000to the host and a direction from the host to the CA register12000. In the embodiment ofFIG. 12, since the host is provided with the operation status information associated with a plurality of memory devices including the memory device11000from the status circuit12100by using one command, it may be possible to easily manage the operation status information.

A B-type memory module20000having the LRDIMM form is illustrated inFIG. 13. The B-type memory module20000may include a memory device21000, a memory buffer22000, and a CA transmission line23000, and a data transmission line24000.

Each of a plurality of memory devices including the memory device21000is connected with the memory buffer22000through the CA transmission line23000and the data transmission line24000. The memory buffer22000performs a role of reducing the load of the output part of the host. The CA transmission line23000may include termination resistors T at ends of the CA transmission line23000to remove a reflected wave generated when a command/address is transmitted. The data transmission line24000may include a plurality of transmission lines for receiving data from each of the plurality of memory devices including the memory device21000or for providing data to each of the plurality of memory devices. The plurality of transmission lines may respectively correspond to the plurality of memory devices, and each transmission line may be connected between the memory buffer22000and the corresponding memory device.

In the LRDIMM structure, in the case where the host accesses the memory device21000, the host indirectly exchange commands, addresses, and data with the memory device21000through the memory buffer22000, the CA transmission line23000, and the data transmission line24000.

The memory buffer22000may include a status circuit22100. In response to the update control signal CTRL_u provided from the host, the status circuit22100may receive and store operation status information from the memory device21000through the CA transmission line23000and the data transmission line24000. Also, in response to the output control signal CTRL_o provided from the host, the status circuit22100provides the stored operation status information to the host through a DATA line. Here, the operation status information may include a command, an address, and input/output data that correspond to an operation of the memory device21000.

In the embodiment ofFIG. 13, the host is provided with the operation status information associated with a plurality of memory devices including the memory device21000from the status circuit22100by using one command, and it may be possible to easily manage the operation status information.

FIG. 14is a block diagram illustrating a stacked memory including the status circuit, according to an embodiment of the inventive concept. Referring toFIG. 14, a stacked memory device30000may include first and second memory devices31000and32000, a logic die33000, and solder balls34000. The number of stacked memory devices is not limited to that illustrated inFIG. 14.

The first and second memory devices31000and32000may include interfaces31100and32100, respectively. The first and second memory devices31000and32000may be connected to each other through silicon vias (TSVs). Also, the first and second memory devices31000and32000may be connected to the logic die33000through the TSVs. Accordingly, the first and second memory devices31000and32000may communicate with a status circuit33100of the logic die33000through the interfaces31100and32100and the TSVs. There may be certain communications that are sent through the interfaces, and other communications that utilize the TSVs.

The logic die33000(e.g. logic circuit) may include the status circuit33100and may be arranged on substrate34500. The status circuit33100may include the status circuit1260described with reference toFIGS. 1 to 11. In response to receiving the update control signal CTRL_u provided from the host, the status circuit33100may receive and store operation status information from each of the first and second memory devices31000and32000connected through the interfaces31100and32100and the TSVs. Also, in response to the output control signal provided from the host, the status circuit33100provides the stored operation status information to the host through the solder balls34000. Here, the operation status information may include a command, an address, and input/output data that correspond to an operation of each of the first and second memory devices31000and32000. The update control signal CTRL_u may be periodically or at random intervals provided from the host during normal operations so that certain operation information that occurs can be subsequently analyzed in the event of an operation failure. The failure may be analyzed faster and in a more exact manner with the operation status information that occurred during a time prior to the detection of an operation failure.

In the embodiment ofFIG. 14, since the host is provided with operation status information of each of the first and second memory devices31000and32000by one command, it may be possible to increase the efficiency in which the operation status information is managed. A structure of memory devices (e.g. memory circuits) stacked and communicatively connected by the TSVs is illustrated inFIG. 14as an example of the stacked memory device30000. However, the embodiments of the inventive concept are not limited thereto. It should be understood and appreciated by a person of ordinary skill in the art that the example ofFIG. 14is applicable to all stackable memory forms including a package on package (PoP) as well as the TSV. Moreover, as there may be a plurality of stacked memory devices, while there has been a discussion herein above regarding a single output control signal can result in all of the vertically stacked memories to report operation status information to the status circuit for output to the host, the inventive concept also includes an embodiment in which a portion (e.g. more than one, but not all) of the vertically stacked memory devices may provide operation status information to the status circuit in response to one command provided by the host. A single memory device (e.g. memory circuit) may also provide operation status information.

FIG. 15is a view illustrating a processor in memory (PIM) including a memory device, according to an embodiment of the inventive concept. Referring toFIG. 15, a PIM40000may include a processor41000, a memory device42000, an interposer43000, and solder balls44000.

The processor41000may correspond to the host1100illustrated inFIG. 1. For example, the processor41000may be a processor circuit or system that includes a general-purpose processor or an application processor. Alternatively, the processor41000may be the following computing device including one or more processors: a personal computer, a peripheral device, a digital camera, personal digital assistant (PDA), a portable media player (PMP), a smartphone, a tablet computer, or a wearable device.

The memory device42000may include at least one of memory devices1200ato12000ddescribed with reference toFIGS. 1 to 11. The memory device42000may include a status circuit42100. The status circuit42100may include the status circuit1260described with reference toFIGS. 1 to 11. The memory device42000may include the memory modules10000and20000described with reference toFIGS. 12 and 13. Alternatively, the memory device42000may include the stacked memory device30000described with reference toFIG. 14.

The memory device42000may communicate with the processor41000through the interposer43000. The interposer may be arranged on a substrate, and for example, one or more processors, the logic die, etc. may be disposed on the interposer. The interposer may be constructed of known materials (e.g. silicon), and may be attached to a substrate using, for example, bumps. The substrate may, on an opposite side, include bumps for connection to, for example, a board, etc. The interposer may provide a communication path between the memory device, and, for example, one or more processors. The memory device42000including the status circuit42100may operate according to the method described with reference toFIGS. 1 to 14under control of the processor41000. The memory device42000may provide stored operation status information STATUS to the processor41000in response to a command of the processor41000. According to the embodiment ofFIG. 15, the processor41000or a user may be provided with the operation status information STATUS of the memory device42000and may analyze an operation failure of the memory device42000.

FIGS. 16A and 16Bare flowcharts that illustrate the operation of a memory device according to an embodiment of the inventive concept.FIG. 16Ais a general overview of the operation of a memory device receiving control signals from a host or processor, andFIG. 16Bis directed to an operation failure.

Referring now toFIG. 16A, at1600the operations begin. At1610, a memory device is provided that includes a logic die (e.g. logic circuit) disposed on a substrate, and a plurality of memory circuits vertically stacked on the logic die. It should be understood and appreciated by a person of ordinary skill in the art that the term “memory circuit” may include the structure of a memory device, for example, a memory device having vertically-stacked memory circuits that are connected for communication via TSVs.

In addition, a status circuit is provided, that may be included with the logic die or separately arranged on the substrate. The status circuit is configured to operate in response to receiving control signals. For example an update control signal or an output control signal. The status circuit may be comprised of gates configured for operation, and is part of an integrated circuit.

At operation1620, it is determined whether an update control signal has been received from a host (or a processor from one or more processors). If the update control signal has been received, the status circuit will update and store operation status information, for example, a command, an address, and input/output data that corresponds to an operation of the plurality of memory devices.

At operation1630, when the determination at operation1620is affirmative, the status circuit updates and stores the operation status information. If the determination at operation1620is negative, the status circuit is not updated and continues to store the information from the last update.

At operation1640, it is determined whether an output control signal is received by a host or processor. When it is determined that the output control signal is received, in response, at operation1650the status circuit outputs the operation status information to the host or processor. According to the inventive concept, the information regarding multiple memory devices may be provided to the host with a single output control signal. The operation inFIG. 16Awould end at this point pending the receipt of further control signals from the host or processor.

If it is determined at operation1640that an output control signal is not received, the operation inFIG. 16Aalso would end at this point pending the receipt of further control signals from the host or processor.

FIG. 16Bis a flowchart illustrating further operation of a memory device according to the inventive concept.FIG. 16Billustrates that there may be periodic or random updates of the operation status information, and the actions that occur in the event that an operation failure is detected.

Referring toFIG. 16B, the operation for detection of an operation begins. At operation1635, according to this embodiment of the inventive concept, if a periodic or random time has passed, the status circuit may update and store status information of the memory devices (memory circuits). The host may send a control signal to the memory device with the time being monitored at the host. On the other hand, the memory device itself may include a processor or controller that is configured to do an automatic update without a control signal being provided by the host or processor.

In addition to the random or periodic update, at operation1637, if the host detects an operation failure (such as by the ways disclosed at least in the examples herein above), the host will signal the status circuit to provide operation status information.

At operation1638, if an operation failure is detected, this information may include operation status from a predetermined time period prior to the operation failure. By providing this additional information, according to the inventive concept, a more exact and faster error analysis may result. The time of failure may be based on, for example, the time that the host initially recognized a reference voltage may have been below a threshold value. In addition, the status circuit may have a relatively small storage area and thus, a dump of the storage at the time the host recognizes a failure may include a certain time prior to the operation failure.

At operation1639, the control circuit may output the operation status information to the host or processor for analysis.

According to an embodiment of the inventive concept, a memory device including a status circuit and an operating method thereof may provide operation information of the memory device when an operation failure occurs. According to the inventive concept, various data may be provided upon analyzing an operation failure of the memory device. More effective failure analyze and test operations may be performed on the memory device and accuracy of analysis may increase.