Wiring substrate

A wiring substrate includes a coil wiring and a magnetic layer that is in contact with a lower surface of the coil wiring and includes an opening extending through in a thickness-wise direction. The wiring substrate further includes a first insulation layer covering the coil wiring, an upper surface of the magnetic layer, and a wall surface of the opening and a signal wiring structure formed so that a signal of a semiconductor element, when mounted on the wiring substrate, travels through the opening of the magnetic layer. The signal wiring structure includes a first wiring portion located on an upper surface of the first insulation layer and a first via wiring located inward from the opening of the magnetic layer and connected to the first wiring portion. The magnetic layer is not in contact with the signal wiring structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2017-124580, filed on Jun. 26, 2017, the entire contents of which are incorporated herein by reference.

FIELD

This disclosure relates to a wiring substrate.

BACKGROUND

A semiconductor element is mounted on a wiring substrate. Japanese Laid-Open Patent Publication No. 2005-183890 describes a wiring substrate incorporating a coil.

SUMMARY

There is a demand for a wiring substrate that limits adverse effects on properties of signals.

One embodiment is a wiring substrate. The wiring substrate includes a coil wiring, a magnetic layer, a first insulation layer, and a signal wiring structure. The magnetic layer is in contact with a lower surface of the coil wiring. The magnetic layer includes an opening extending through in a thickness-wise direction. The first insulation layer covers the coil wiring, an upper surface of the magnetic layer, and a wall surface of the opening. The signal wiring structure that transmits a signal of a semiconductor element in the wiring substrate when the semiconductor element is mounted on the wiring substrate. The signal wiring structure is formed so that the signal of the semiconductor element travels through the opening of the magnetic layer. The signal wiring structure includes a first wiring portion located on an upper surface of the first insulation layer and a first via wiring located inward from the opening of the magnetic layer and connected to the first wiring portion. The magnetic layer is not in contact with the signal wiring structure.

Another embodiment is a wiring substrate. The wiring substrate includes an insulation layer including an upper surface and a lower surface, a coil wiring formed on the lower surface of the insulation layer, a magnetic layer covering the lower surface of the insulation layer and the coil wiring and including an opening extending through in a thickness-wise direction, and a signal wiring structure that transmits a signal of a semiconductor element in the wiring substrate when the semiconductor element is mounted on the wiring substrate. The signal wiring structure is formed so that the signal of the semiconductor element travels through the opening of the magnetic layer. The magnetic layer is not in contact with the signal wiring structure.

Other embodiments and advantages thereof will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

DESCRIPTION OF THE EMBODIMENTS

Each embodiment will now be described with reference to the accompanying drawings. Elements in the drawings may be partially enlarged for simplicity and clarity and thus have not necessarily been drawn to scale. To facilitate understanding, hatching lines may not be illustrated or be replaced by shadings in the cross-sectional drawings.

In the specification hereafter, “plan view” refers to a view of a subject taken in a vertical direction (for example, upper-lower direction inFIG. 1A), and “planar shape” refers to a shape of a subject as viewed in the vertical direction.

First Embodiment

The first embodiment will now be described.

As illustrated inFIG. 1A, a semiconductor device1includes a wiring substrate10and a semiconductor element51mounted on the wiring substrate10.

The semiconductor element51is connected to external connection pads P11of the wiring substrate10by external connection terminals52. The semiconductor element51is flip-chip-connected to the external connection pads P11of the wiring substrate10. The semiconductor element51may be, for example, a logic chip such as a central processing unit (CPU) or a graphics processing unit (GPU) or a memory chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). The external connection terminals52are, for example, solder bumps or gold bumps. The material of the solder bumps may be, for example, an alloy containing lead, an alloy of tin and gold, an alloy of tin and copper, an alloy of tin and silver, or an alloy of tin, silver, and copper.

An underfill resin53is formed between the semiconductor element51and the wiring substrate10. The material of the underfill resin53may be, for example, an insulative resin such as an epoxy resin.

The wiring substrate10includes external connection pads P12A and P12B. The external connection pads P12A and P12B are exposed from the lower surface of the wiring substrate10. The external connection pads P12A and P12B are connected to external connection terminals55A and55B. The external connection terminals55A and55B are used to mount the wiring substrate10on, for example, a mount board such as a motherboard. The external connection terminals55A and55B are, for example, solder bumps. The material of the solder bumps may be, for example, an alloy containing lead (Pb), an alloy of Sn and Cu, an alloy of Sn and silver (Ag), or an alloy of Sn, Ag, and Cu. The external connection terminals55A and55B may be solder balls or lead pins.

The semiconductor element51, which is mounted on the wiring substrate10, sends signals to the external connection pads P11and receives signals from the external connection pads P11. The wiring substrate10transmits signals between the external connection pads P11and the external connection pads P12A. The wiring substrate10includes a conductor (signal wiring structure) arranged between the external connection pads P11and the external connection pads P12A to transmit signals. The signal wiring structure of the wiring substrate10transmits a signal output from the semiconductor element51through the external connection pads P11to the external connection pads P12A. The signal is provided to the mount board via the external connection terminals55A, which are connected to the external connection pads P12A. Also, when receiving a signal output from the mount board via the external connection terminals55A, the signal wiring structure of the wiring substrate10transmits the signal from the external connection pads P12A to the external connection pads P11. The signal is provided to the semiconductor element51via the external connection terminals52, which are connected to the external connection pads P12A.

The wiring substrate10incorporates a coil41. In the first embodiment, the coil41is connected to the external connection pads P12B of the wiring substrate10.

As illustrated inFIG. 1B, the wiring substrate10includes a wiring layer11, an insulation layer12, a magnetic layer13, a wiring layer14, an insulation layer15, a wiring layer16, an insulation layer17, and a wiring layer18that are stacked. The wiring layer14includes a coil wiring14P of the coil41.

The wiring layer11includes wiring portions11A and11B. The wiring portions11A and11B respectively have lower surfaces11Ab and11Bb exposed from the lower surface of the insulation layer12. The insulation layer12covers part of upper surfaces11Aa and11Ba of the wiring portions11A and11B and side surfaces11Ac and11Bc of the wiring portions11A and11B.

In the first embodiment, the wiring layer11(wiring portions11A and11B) includes a first metal layer and a second metal layer formed one on the other. The second metal layer covers the upper surface of the first metal layer. The material of the first metal layer may be, for example, a metal such as nickel (Ni), titanium (Ti), chromium (Cr), or tin (Sn) or an alloy containing at least one kind of metal selected from these metals. The material of the second metal layer may be, for example, copper (Cu) or a Cu alloy.

The insulation layer12covers part of the upper surface of the wiring layer11and the side surface of the wiring layer11. The insulation layer12includes openings12X, which partially expose the upper surfaces11Aa of the wiring portions11A of the wiring layer11, and openings12Y, which partially expose the upper surfaces11Ba of the wiring portions11B of the wiring layer11. In the first embodiment, the insulation layer12has a lower surface12blocated at a lower position than the lower surfaces11Ab and11Bb of the wiring portions11A and11B of the wiring layer11. Thus, the insulation layer12includes openings12bX and12bY exposing the lower surfaces11Ab and11Bb of the wiring portions11A and11B. The openings12bX and12bY facilitate formation of the external connection terminals55A and55B illustrated inFIG. 1A. The material of the insulation layer12may be, for example, an insulative resin, the main component of which is a photosensitive resin such as a phenol resin or a polyimide resin, or a thermosetting insulative resin, the main component of which is an epoxy resin. The insulative resin may contain, for example, a filler such as silica or alumina.

The insulation layer12has an upper surface12acovered by the magnetic layer13. The magnetic layer13includes openings13X and13Y, which partially expose the upper surfaces11Aa and11Ba of the wiring portions11A and11B of the wiring layer11. In the first embodiment, the openings13X of the magnetic layer13are continuous with the openings12X of the insulation layer12. For example, the openings13X and12X are formed so that the wall surfaces of the openings13X of the magnetic layer13are continuous with the wall surfaces of the respective openings12X of the insulation layer12. In the same manner, the openings13Y of the magnetic layer13are continuous with the openings12Y of the insulation layer12. For example, the openings13Y and12Y are formed so that the wall surfaces of the openings13Y of the magnetic layer13are continuous with the wall surfaces of the respective openings12Y of the insulation layer12.

The magnetic layer13may be formed from a magnetic material in which a magnetic filler is mixed with an insulative resin. The insulative resin may be, for example, an epoxy resin or a polyimide resin. The magnetic filler may be, for example, manganese (Mn)-Zinc (Zn) ferrite, Ni—Zn ferrite, an iron (Fe)-cobalt (Co) alloy, or an Fe-silicon (Si) alloy. The magnetic layer13containing an insulative resin as describe above has a resistance value that is, for example, the same level as that of the insulation layer12. The resistance value of the magnetic layer13is higher than that of a wiring layer of, for example, Cu or a Cu alloy. Thus, signals will not transmit between the two wirings that are in contact with the magnetic layer13. Additionally, the magnetic layer13contains the magnetic filler. This improves the L value of the coil41.

The wiring layer14is formed on an upper surface13aof the magnetic layer13. The wiring layer14includes the coil wiring14P, which is formed on the upper surface13aof the magnetic layer13, and via wirings14V formed in the openings13Y of the magnetic layer13and the openings12Y of the insulation layer12. The coil wiring14P of the first embodiment is a planar coil spirally formed on the upper surface13aof the magnetic layer13. The via wirings14V electrically connect the coil wiring14P to the wiring portions11B of the wiring layer11at two opposite ends of the coil wiring14P. The material of the wiring layer14may be Cu or a Cu alloy.

The insulation layer15is formed on the upper surface13aof the magnetic layer13. The insulation layer15covers the upper surface13aof the magnetic layer13, the wall surfaces of the openings13X of the magnetic layer13, the wall surfaces of the openings12X of the insulation layer12, and the wiring layer14. The insulation layer15includes a first insulation layer15A, which covers the upper surface13aof the magnetic layer13and the wiring layer14, and a second insulation layer15B, which covers the wall surfaces of the openings13X of the magnetic layer13and the wall surfaces of the openings12X of the insulation layer12.

The insulation layer15includes openings15X, which partially expose the upper surfaces11Aa of the wiring portions11A of the wiring layer11. The openings15X are located inward from the openings13X of the magnetic layer13and the openings12X of the insulation layer12and extend through the first insulation layer15A and the second insulation layer15B. The material of the insulation layer15may be, for example, an insulative resin, the main component of which is a photosensitive resin such as a phenol resin or a polyimide resin, or a thermosetting insulative resin, the main component of which is an epoxy resin. The insulative resin may contain, for example, a filler such as silica or alumina.

The wiring layer16is formed on an upper surface15aof the insulation layer15. The wiring layer16includes wiring portions16P, which are formed on the upper surface15aof the insulation layer15, and via wirings16V, which are formed in the openings15X of the insulation layer15. The via wirings16V electrically connect the wiring portions16P of the wiring layer16to the wiring portions11A of the wiring layer11. The material of the wiring layer16may be Cu or a Cu alloy.

The insulation layer17covers the upper surface15aof the insulation layer15and the wiring layer16. The insulation layer17includes openings17X, which partially expose an upper surface16aof the wiring layer16. The material of the insulation layer17may be, for example, an insulative resin, the main component of which is a photosensitive resin such as a phenol resin or a polyimide resin, or a thermosetting insulative resin, the main component of which is an epoxy resin. The insulative resin may contain, for example, a filler such as silica or alumina.

The wiring layer18is formed on an upper surface17aof the insulation layer17. The wiring layer18includes wiring portions18P, which are formed on the upper surface17aof the insulation layer17, and via wirings18V, which are formed in the openings17X of the insulation layer17. The via wirings18V electrically connect the wiring portions18P of the wiring layer18to the wiring portions16P of the wiring layer16. The material of the wiring layer18may be Cu or a Cu alloy.

A solder resist layer19is formed on the upper surface17aof the insulation layer17. The solder resist layer19covers the upper surface17aof the insulation layer17and part of the wiring layer18. The solder resist layer19includes openings19X, which partially expose an upper surface18aof the wiring layer18as the external connection pads P11. The material of the solder resist layer19may be, for example, an insulative resin such as an epoxy resin or an acrylic resin.

As necessary, an OSP process may be performed on the upper surface of the wiring layer18exposed from the openings19X of the solder resist layer19to form an OSP film. Also, a metal layer may be formed on the upper surface of the wiring layer18exposed from the openings19X. The metal layer is, for example, an Au layer, a Ni layer/Au layer (metal layer in which Au layer is formed on Ni layer that serves as bottom layer), or a Ni layer/Pd layer/Au layer (metal layer in which Ni layer serves as bottom layer, and Ni layer, Pd layer, and Au layer are sequentially stacked). The wiring layer18(or OSP film or metal layer formed on wiring layer18) exposed from the openings19X may be used as the external connection pads P11.

Manufacturing Steps

The steps of manufacturing the wiring substrate10will now be described.

As illustrated inFIG. 2A, a support substrate60is prepared. The support substrate60may be, for example, a carrier-added metal foil. The support substrate60may be a different known support substrate. The support substrate60includes a carrier plate61and an ultrathin metal foil62formed on one surface (upper surface inFIG. 2A) of the carrier plate61with a delamination layer (not illustrated) located in between. The material of the carrier plate61may be, for example, Cu or a Cu alloy. The material of the metal foil62may be, for example, Cu or a Cu alloy.

In the step illustrated inFIG. 2B, a metal layer63and the wiring layer11are sequentially formed on the upper surface of the metal foil62. For example, a resist layer including openings is formed on the upper surface of the metal foil62. The openings are formed in positions corresponding to the wiring portions11A and11B illustrated inFIGS. 1A and 1B. The resist layer may be formed from a material having, for example, resistance to a process (e.g., plating) that forms the metal layer63and the wiring layer11. The material of the resist layer may be, for example, a photosensitive dry film resist (e.g., novolac resin or acrylic resin).

The metal layer63and the wiring layer11are sequentially formed on the upper surface of the metal foil62through electrolytic plating (electrolytic copper plating) that uses the resist layer as a plating mask and the metal foil62as a power feeding layer. When the wiring layer11is formed by a first metal layer and a second metal layer as described above, the first metal layer and the second metal layer are sequentially formed on the upper surface of the metal layer63. Subsequently, the resist layer is removed, for example, through asking or with an alkaline stripping solution.

In the step illustrated inFIG. 2C, the insulation layer12and the magnetic layer13are formed. The insulation layer12is formed to cover the upper surface of the metal foil62, the wiring layer11, and the metal layer63. The material of the insulation layer12may be, for example, an organic resin such as an epoxy resin or a polyimide resin or a resin material in which such an organic resin is mixed with a filler such as silica or alumina. The insulation layer12is obtained, for example, by vacuum-laminating with a resin film and curing the resin film with application of heat. Alternatively, the insulation layer12may be formed by applying a resin paste or liquid and heating the resin. The magnetic layer13is formed to cover the upper surface12aof the insulation layer12. The magnetic layer13may be, for example, an uncured film formed from a magnetic material in which a magnetic filler is mixed with an insulative resin. The magnetic layer13is obtained, for example, by vacuum-laminating a film of a magnetic material and curing the film with application of heat.

In the step illustrated inFIG. 3A, the openings13Y are formed in the magnetic layer13, and the openings12Y are formed in the insulation layer12. The openings13Y and12Y may be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are emitted toward the upper surface13aof the magnetic layer13to form the openings13Y extending through the magnetic layer13and the openings12Y extending through the insulation layer12. The openings13Y and12Y partially expose the upper surfaces of the wiring portions11B of the wiring layer11. As necessary, a desmear process may be performed.

In the step illustrated inFIG. 3B, the wiring layer14is formed. The wiring layer14includes the via wirings14V formed in the openings13Y and12Y and the coil wiring14P formed on the upper surface13aof the magnetic layer13. A seed layer (not illustrated) is formed on the upper surface13aof the magnetic layer13, the wall surfaces of the openings13Y of the magnetic layer13, the wall surfaces of the openings12Y of the insulation layer12, and the upper surfaces of the wiring portions11B of the wiring layer11exposed in the openings13Y and12Y. The material of the seed layer may be, for example, copper or a copper alloy. The seed layer may be formed through, for example, electroless plating or sputtering.

The seed layer is covered by a resist layer (not illustrated) including openings in given locations. The openings are formed in positions corresponding to the coil wiring14P of the wiring layer14. The resist layer may be formed from a material having, for example, resistance to plating performed in the next step. Electrolytic plating (electrolytic copper plating) that uses the seed layer as a power feeding electrode is performed to deposit and develop a plating metal on the seed layer exposed in the openings of the resist layer. The resist layer is removed, for example, through asking or with an alkaline stripping solution. Subsequently, the exposed seed layer is removed through etching. This obtains the wiring layer14including the via wirings14V and the coil wiring14P.

In the step illustrated inFIG. 3C, the openings13X are formed in the magnetic layer13, and the openings12X are formed in the insulation layer12. The openings13X and12X may be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are emitted toward the upper surface13aof the magnetic layer13to form the openings13X extending through the magnetic layer13and the openings12X extending through the insulation layer12. The openings13X and12X partially expose the upper surfaces of the wiring portions11A of the wiring layer11. As necessary, a desmear process may be performed.

In the step illustrated inFIG. 4A, the insulation layer15is formed to cover the upper surface of the magnetic layer13and the wiring layer14. The material of the insulation layer15may be, for example, an organic resin such as an epoxy resin or a polyimide resin or a resin material in which such an organic resin is mixed with a filler such as silica or alumina. The insulation layer15is obtained, for example, by vacuum-laminating a resin film and curing the resin film with application of heat. Alternatively, the insulation layer15may be formed by applying a resin paste or liquid and heating the resin.

In the step illustrated inFIG. 4B, the openings15X are formed in the insulation layer15. The openings15X may be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are positioned in accordance with the openings13X of the magnetic layer13and emitted toward the upper surface15aof the insulation layer15. This forms the openings15X extending through the insulation layer15inward from the openings13X of the magnetic layer13and the openings12X of the insulation layer12. The openings15X partially expose the upper surfaces of the wiring portions11A of the wiring layer11. As necessary, a desmear process may be performed.

In the step illustrated inFIG. 4C, the wiring layer16is formed. A seed layer (not illustrated) is formed on the upper surface of the insulation layer15, the wall surfaces of the openings15X of the insulation layer15, and the upper surface of the wiring layer11(wiring portions11A) exposed in the openings15X of the insulation layer15. The material of the seed layer may be, for example, copper or a copper alloy. The seed layer may be formed through, for example, electroless plating or sputtering. The seed layer is covered by a resist layer (not illustrated) including openings in given locations. The openings are formed in positions corresponding to the wiring portions16P of the wiring layer16. The resist layer may have, for example, resistance to plating performed in the next step. Electrolytic plating (electrolytic copper plating) that uses the seed layer as a power feeding electrode is performed to deposit and develop a plating metal on the seed layer exposed in the openings of the resist layer. The resist layer is removed, for example, through asking or with an alkaline stripping solution. Subsequently, the exposed seed layer is removed through etching to obtain the wiring layer16.

In the step illustrated inFIG. 5A, the insulation layer17including the openings17X is formed. The upper surface15aof the insulation layer15and the wiring layer16are, for example, vacuum-laminated with an epoxy resin film. The resin film is cured by application of heat. This forms the insulation layer17. Alternatively, the insulation layer17may be formed by applying a resin paste or liquid and heating the resin. The openings17X are formed in the insulation layer17. The openings17X may be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are emitted toward the upper surface17aof the insulation layer17to form the openings17X extending through the insulation layer17. The openings17X partially expose the upper surface of the wiring layer16. As necessary, a desmear process may be performed.

In the step illustrated inFIG. 5B, the wiring layer18is formed. A seed layer (not illustrated) is formed on the upper surface of the insulation layer17, the wall surfaces of the openings17X of the insulation layer17, and the upper surface of the wiring layer16exposed in the openings17X of the insulation layer17. The material of the seed layer may be, for example, copper or a copper alloy. The seed layer may be formed through, for example, electroless plating or sputtering. The seed layer is covered by a resist layer (not illustrated) including openings in given locations. The openings are formed in positions corresponding to the wiring portions18P of the wiring layer18. The resist layer may be formed from a material having, for example, resistance to plating performed in the next step. Electrolytic plating (electrolytic copper plating) that uses the seed layer as a power feeding electrode is performed to deposit and develop a plating metal on the seed layer exposed in the openings of the resist layer. The resist layer is removed, for example, through asking or with an alkaline stripping solution. Subsequently, the exposed seed layer is removed through etching to obtain the wiring layer18.

In the step illustrated inFIG. 6A, the solder resist layer19including the openings19X is formed. The solder resist layer19is obtained, for example, by laminating with a photosensitive solder resist film or applying a liquid solder resist and exposing and developing the resist through photolithography to be patterned in a desired shape.

In the step illustrated inFIG. 6B, the carrier plate61illustrated inFIG. 6Ais removed. The carrier plate61is delaminated from the metal foil62of the support substrate60. The delamination layer located between the carrier plate61and the metal foil62helps delaminate the carrier plate61. Then, the metal foil62and the metal layer63are removed. The metal foil62and the metal layer63are removed, for example, through wet etching that uses a hydrogen peroxide/sulfuric acid solution, a sodium persulfate solution, or an ammonium persulfate solution. At this time, the etching time is controlled so that the wiring portions11A and11B remain. When the wiring layer11includes a first metal layer (e.g., Ni) and a second metal layer (e.g., Cu) as described above, the first metal layer functions as an etching stop layer so that the wiring portions11A and11B remain. This obtains the wiring substrate10illustrated inFIG. 1B.

Operation

The wiring substrate10of the first embodiment includes the coil wiring14P on the upper surface13aof the magnetic layer13. Thus, the magnetic layer13is in contact with the lower surface of the coil wiring14P. The coil wiring14P is spiral in a plan view.

The coil41of the wiring substrate10of the first embodiment, which includes the magnetic layer13adhering to the coil wiring14P, will now be compared with a coil of a wiring substrate that does not include the magnetic layer13. For the sake of brevity, in the description hereafter, a coil having the coil wiring14P adhering to the magnetic layer13is referred to as “the magnetic coil,” and a coil of a wiring substrate that does not include the magnetic layer13is referred to as “the non-magnetic coil.” The inductance (L value) of “the magnetic coil” is greater than the L value of “the non-magnetic coil.” When the L value of “the magnetic coil” is set to be equal to the L value of “the non-magnetic coil,” the wiring length of “the magnetic coil” is shorter than the wiring length of “the non-magnetic coil.” Thus, use of “the magnetic coil” decreases the area occupied by “the magnetic coil” and reduces the number of wiring layers. As a result, the magnetic layer13adhering to the coil wiring14P, that is, the wiring substrate10of the first embodiment including “the magnetic coil,” may be reduced in area and thinned.

As illustrated inFIG. 1A, in the semiconductor device1of the first embodiment, signals input to and output from the semiconductor element51are transmitted between the external connection terminals55A and52via the wiring portions11A of the wiring layer11, the wiring layer16, and the wiring layer18of the wiring substrate10. The external connection terminals55A are connected to the external connection pads P12A of the wiring portions11A of the wiring layer11. The external connection terminals52are connected to the external connection pads P11of the wiring portions18P of the wiring layer18. Thus, the wiring portions11A of the wiring layer11, the via wirings16V and the wiring portions16P of the wiring layer16, and the via wirings18V and the wiring portions18P of the wiring layer18serve as a line (signal wiring structure) that transmit signals through the wiring substrate10. In the wiring layer16, the via wirings16V, which connect the wiring portions16P of the wiring layer16and the wiring portions11A of the wiring layer11, are located inward from the openings13X extending through the magnetic layer13. Thus, the line transmitting signals to and from the semiconductor element51extends through the magnetic layer13, but is not in contact with the magnetic layer13.

The magnetic layer13has a lower surface13bcovered by the insulation layer12. The upper surface13aof the magnetic layer13is covered by the insulation layer15. The wall surfaces of the openings13X of the magnetic layer13are covered by the second insulation layer15B of the insulation layer15. Thus, the magnetic layer13is not in contact with the via wirings16V, which are formed in the openings15X extending through the second insulation layer15B. In other words, in the first embodiment, the magnetic layer13of the wiring substrate10is not in direct contact with the signal wiring structure of the wiring substrate10. With such a structure, the signal transmission performance is improved in the wiring substrate10including the magnetic layer13, and the insertion loss is reduced.

FIGS. 7A to 7Dare cross-sectional views of various wiring substrate models70ato70dfor measurement of S-parameters (S21) corresponding to transmission of signals.

FIG. 7Aillustrates a first model70a.The first model70ais a wiring substrate including a wiring layer71, an insulation layer81, a wiring layer72, an insulation layer82, a wiring layer73, an insulation layer83, a wiring layer74, an insulation layer84, a wiring layer75, an insulation layer85, a wiring layer76, an insulation layer86, a wiring layer77, an insulation layer87, and a wiring layer78that are sequentially stacked. An external connection terminal91is connected to the lower surface of an external connection pad71P of the wiring layer71. The wiring layers72to77include via wirings extending through the insulation layers81to86to connect the wiring layers72to77to the wiring layers71to76, respectively. The first model70adoes not include a magnetic layer.

FIG. 7Billustrates a second model70b.In the second model70b,the insulation layer81of the first model70ais replaced with the magnetic layer13. In the second model70b,the magnetic layer13is in contact with the wiring layer71and the wiring layer72.

FIG. 7Cillustrates a third model70c.The third model70cdiffers from the first model70ain that the external connection terminal91covers the lower and side surfaces of the external connection pad71P of the wiring layer71. Additionally, in the third model70c,the magnetic layer13covers the lower surface of the insulation layer81, the lower surface and the side surfaces of the wiring layer71except for the external connection pad71P, and part of the external connection terminal91. The magnetic layer13of the third model70cis not in direct contact with the wiring that serves as the signal transmission line.

FIG. 7Dillustrates a fourth model70d.The fourth model70ddiffers from the second model70bin that the magnetic layer13includes the opening13X while covering the lower surface of the wiring layer72. However, the magnetic layer13includes the openings13X. Additionally, the fourth model70dincludes an insulation layer81acovering the lower surface of the magnetic layer13and filling the openings13X of the magnetic layer13. Thus, in the fourth model70d,the wiring serving as the signal transmission line extends through the magnetic layer13, and the insulation layer81ais located between the wiring of the signal transmission line and the magnetic layer13. That is, the wiring of the signal transmission line is not in contact with the magnetic layer13.

In each of the models70ato70d,a signal is provided to the wiring layer77. The signal is transmitted to the external connection terminal91via the wiring layers77to71. The signal is observed at the external connection terminal91. The S-parameter (insertion loss; S21) of each of the models70ato70dis calculated based on the level of the signal provided to the wiring layer77and the level of the signal observed at the external connection terminal91.

FIG. 8illustrates the results of simulations of the S-parameters (insertion loss: S21) of the models70ato70dillustrated inFIGS. 7A to 7D. InFIG. 8, the horizontal axis indicates frequencies (GHz) of the signals, and the vertical axis indicates S21(insertion loss; dB). In the horizontal axis ofFIG. 8, the frequency increases toward the right. In the vertical axis ofFIG. 8, S21(insertion loss) increases toward the lower side. InFIG. 8, curve lines La to Ld illustrate S21(insertion loss) of the first to fourth models70ato70dillustrated inFIGS. 7A to 7D.

In the second model70billustrated inFIG. 7B, the magnetic layer13is in direct contact with the wiring layers71and72. In this case, as indicated by the curve line Lb inFIG. 8, the insertion loss of the second model70bcorresponding to high frequency signals largely increases as compared to the insertion loss (curve line La inFIG. 8) of the first model70a,which does not include the magnetic layer13.

In the third model70cillustrated inFIG. 7C, the magnetic layer13is not in direct contact with the wiring of the wiring layers71and72transmitting signals. In this case, as indicated by the curve line Lc inFIG. 8, the insertion loss of the third model70ccorresponding to high frequency signals is smaller than the insertion loss (curve line Lb inFIG. 8) of the second model70b.Thus, when the magnetic layer13is not in direct contact with the wiring of the signal transmission line, the insertion loss is reduced, and the transmission performance of a high frequency signal is improved.

In the fourth model70dillustrated inFIG. 7D, the magnetic layer13is not in contact with the wiring of the wiring layers71and72transmitting signals. In this case, as indicated by the curve line Ld inFIG. 8, the insertion loss of the fourth model70dcorresponding to high frequency signals is smaller than the insertion losses (curve lines Lb and Lc inFIG. 8) of the second and third models70band70c.Thus, when the magnetic layer13is not in contact with the wiring of the signal transmission line, the insertion loss is further reduced, and the transmission performance of a high frequency signal is further improved.

The first embodiment has the advantages described below.

(1-1) The semiconductor device1includes the wiring substrate10and the semiconductor element51mounted on the wiring substrate10. The wiring substrate10includes the wiring layer11, the insulation layer12, the magnetic layer13, the wiring layer14, the insulation layer15, the wiring layer16, the insulation layer17, and the wiring layer18that are stacked. The wiring layer14is formed on the upper surface13aof the magnetic layer13. The wiring layer14includes the coil wiring14P located on the upper surface13aof the magnetic layer13. The coil wiring14P is a planar coil, for example, spirally formed on the upper surface13aof the magnetic layer13. The wiring portions11A of the wiring layer11, the via wirings16V and the wiring portions16P of the wiring layer16, and the via wirings18V and the wiring portions18P of the wiring layer18form the line (signal wiring structure) that transmits signals in the wiring substrate10. The magnetic layer13is not in contact with the via wirings16V, which are formed in the openings15X extending through the second insulation layer15B. In other words, in the first embodiment, the magnetic layer13of the wiring substrate10is not in direct contact with the signal wiring structure of the wiring substrate10. With such a structure, the signal transmission performance is improved in the wiring substrate10including the magnetic layer13, and the insertion loss is reduced.

(1-2) The magnetic layer13may be formed from a magnetic material in which a magnetic filler is mixed with an insulative resin. The magnetic layer13containing the insulative resin has a resistance value that is, for example, at the same level as that of the insulation layer12. The resistance value of the magnetic layer13is higher than that of a wiring layer of, for example, Cu or a Cu alloy. This allows the magnetic layer13to adhere to the coil wiring14P. Additionally, the magnetic layer13contains the magnetic filler. This improves the L value of the coil41.

Second Embodiment

A second embodiment will now be described. In the second embodiment, the same reference characters are given to those components that are the same as the corresponding components of the first embodiment. Such components may not be described in detail.

As illustrated inFIG. 9A, a semiconductor device101includes a wiring substrate110and the semiconductor element51mounted on the wiring substrate110.

The semiconductor element51is connected to external connection pads P21of the wiring substrate110by the external connection terminals52. The semiconductor element51is flip-chip-connected to the external connection pads P21of the wiring substrate110. The semiconductor element51is, for example, a logic chip such as a central processing unit (CPU) or a graphics processing unit (GPU) or a memory chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). The external connection terminals52are, for example, solder bumps or gold bumps. The material of the solder bumps may be, for example, an alloy containing lead, an alloy of tin and gold, an alloy of tin and copper, an alloy of tin and silver, or an alloy of tin, silver, and copper.

The underfill resin53is formed between the semiconductor element51and the wiring substrate110. The material of the underfill resin53may be, for example, an insulative resin such as an epoxy resin.

The wiring substrate110includes external connection pads P22A and P22B. The external connection pads P22A and P22B are exposed from the lower surface of the wiring substrate110. The external connection terminals55A and55B are connected to the external connection pads P22A and P22B. The external connection terminals55A and55B are used to mount the wiring substrate110on, for example, a mount board such as a motherboard. The external connection terminals55A and55B are, for example, solder bumps. The material of the solder bumps may be, for example, an alloy containing lead (Pb), an alloy of Sn and Cu, an alloy of Sn and silver (Ag), or an alloy of Sn, Ag, and Cu. The external connection terminals55A and55B may be solder balls or lead pins.

The semiconductor element51, which is mounted on the wiring substrate110, sends signals to the external connection pads P21and receives signals from the external connection pads P21. The wiring substrate110transmits signals between the external connection pads P21and the external connection pads P22A. The wiring substrate110includes a conductor (signal wiring structure) arranged between the external connection pads P21and the external connection pads P22A to transmit signals. The signal wiring structure of the wiring substrate110transmits a signal output from the semiconductor element51through the external connection pads P21to the external connection pads P22A. The signal is provided to the mount board via the external connection terminals55A, which are connected to the external connection pads P22A. Also, when receiving a signal output from the mount board via the external connection terminals55A, the signal wiring structure of the wiring substrate110transmits the signal from the external connection pads P22A to the external connection pads P21. The signal is provided to the semiconductor element51via the external connection terminals52, which are connected to the external connection pads P21.

The wiring substrate110incorporates a coil141. In the second embodiment, the coil141is connected to the external connection pads P22B of the wiring substrate110.

As illustrated inFIG. 9B, the wiring substrate110includes a wiring layer111, a magnetic layer113, a wiring layer114, an insulation layer115, a wiring layer116, an insulation layer117, and a wiring layer118that are stacked. The wiring layer114includes a coil wiring114P of the coil141.

The wiring layer111includes wiring portions111A and111B. The wiring portions111B are in contact with the magnetic layer113. The wiring portions111B are embedded in the magnetic layer113so that the lower surfaces of the wiring portions111B are exposed.

The magnetic layer113includes openings113X extending through the magnetic layer113in the thickness-wise direction. The openings113X are filled with the insulation layer115, which covers an upper surface113aof the magnetic layer113. The wiring portions111A of the wiring layer111are embedded in the insulation layer115so that the lower surfaces of the wiring portions111A are exposed. The magnetic layer113includes openings113Y, which partially expose upper surfaces111Ba of the wiring portions111B of the wiring layer111.

The wiring portions111A has lower surfaces111Ab, which are located inward from the openings113X of the magnetic layer113and exposed from the insulation layer115. The insulation layer115covers part of upper surfaces111Aa of the wiring portions111A and side surfaces111Ac of the wiring portions111A. The wiring portions111B have lower surfaces111Bb exposed from a lower surface113bof the magnetic layer113. The magnetic layer113covers side surfaces111Bc of the wiring portions111B and part of the upper surfaces111Ba of the wiring portions111B.

In the second embodiment, the wiring layer111includes a first metal layer and a second metal layer formed one on the other. The second metal layer covers the upper surface of the first metal layer. The material of the first metal layer may be, for example, a metal such as nickel (Ni), titanium (Ti), chromium (Cr), or tin (Sn) or an alloy containing at least one kind of metal selected from these metals. The material of the second metal layer may be, for example, copper (Cu) or a Cu alloy.

The magnetic layer113may be formed from a magnetic material in which a magnetic filler is mixed with an insulative resin. The insulative resin may be, for example, an epoxy resin or a polyimide resin. The magnetic filler may be, for example, manganese (Mn)-Zinc (Zn) ferrite, Ni—Zn ferrite, an iron (Fe)-cobalt (Co) alloy, or an Fe-silicon (Si) alloy.

The wiring layer114is formed on the upper surface113aof the magnetic layer113. The wiring layer114includes the coil wiring114P, which is formed on the upper surface113aof the magnetic layer113, and via wirings114V, which are formed in the openings113Y of the magnetic layer113. The coil wiring114P of the second embodiment is a planar coil spirally formed on the upper surface113aof the magnetic layer113. The via wirings114V electrically connect the coil wiring114P to the wiring portions111B of the wiring layer111at two opposite ends of the coil wiring114P. The material of the wiring layer114may be Cu or a Cu alloy.

The insulation layer115covers the upper surface113aof the magnetic layer113, the wall surfaces of the openings113X of the magnetic layer113, the wiring portions111A of the wiring layer111, and the coil wiring114P of the wiring layer114. The insulation layer115includes a first insulation layer115A and a second insulation layer115B. The first insulation layer115A covers the upper surface113aof the magnetic layer113and the coil wiring114P of the wiring layer114. The second insulation layer115B covers the wall surfaces of the openings113X of the magnetic layer113and the upper and side surfaces of the wiring portions111A of the wiring layer111.

The insulation layer115includes openings115X, which partially expose the upper surfaces111Aa of the wiring portions111A of the wiring layer111. The openings115X are located inward from the openings113X of the magnetic layer113and extend through the first insulation layer115A and the second insulation layer115B. The material of the insulation layer115may be, for example, an insulative resin, the main component of which is a photosensitive resin such as a phenol resin or a polyimide resin, or a thermosetting insulative resin, the main component of which is an epoxy resin. The insulative resin may contain, for example, a filler such as silica or alumina.

The wiring layer116is formed on an upper surface115aof the insulation layer115. The wiring layer116includes wiring portions116P, which are formed on the upper surface115aof the insulation layer115and via wirings116V, which are formed in the openings115X of the insulation layer115. The via wirings116V electrically connect the wiring portions116P of the wiring layer116to the wiring portions111A of the wiring layer111. The material of the wiring layer116may be Cu or a Cu alloy.

The insulation layer117covers the upper surface115aof the insulation layer115and the wiring layer116. The insulation layer117includes openings117X, which partially expose an upper surface116aof the wiring portions116P. The material of the insulation layer117may be, for example, an insulative resin, the main component of which is a photosensitive resin such as a phenol resin or a polyimide resin, or a thermosetting insulative resin, the main component of which is an epoxy resin. The insulative resin may contain, for example, a filler such as silica or alumina.

The wiring layer118is formed on an upper surface117aof the insulation layer117. The wiring layer118includes wiring portions118P, which are formed on the upper surface117aof the insulation layer117, and via wirings118V, which are formed in the openings117X of the insulation layer117. The via wirings118V electrically connect the wiring portions118P of the wiring layer118to the wiring portions116P of the wiring layer116. The material of the wiring layer118may be Cu or a Cu alloy.

A solder resist layer119is formed on the upper surface117aof the insulation layer117. The solder resist layer119covers the upper surface117aof the insulation layer117and part of the wiring layer118. The solder resist layer119includes openings119X, which partially expose an upper surface118aof the wiring layer118as the external connection pads P21. The material of the solder resist layer119may be, for example, an insulative resin such as an epoxy resin or an acrylic resin.

As necessary, an OSP process may be performed on the upper surface of the wiring layer118exposed from the openings119X of the solder resist layer119to form an OSP film. Also, a metal layer may be formed on the upper surface of the wiring layer118exposed from the openings119X. The metal layer is, for example, an Au layer, a Ni layer/Au layer (metal layer in which Au layer is formed on Ni layer that serves as bottom layer), or a Ni layer/Pd layer/Au layer (metal layer in which Ni layer serves as bottom layer, and Ni layer, Pd layer, and Au layer are sequentially stacked). The wiring layer118(or OSP film or metal layer formed on wiring layer118) exposed from the openings119X may be used as the external connection pads P21.

Manufacturing Steps

The steps of manufacturing the wiring substrate110of the second embodiment will now be described.

As illustrated inFIG. 10A, a support substrate60is prepared. The support substrate60may be, for example, a carrier-added metal foil. The support substrate60may be a different known support substrate. The support substrate60includes a carrier plate61and an ultrathin metal foil62formed on one surface (upper surface inFIG. 10A) of the carrier plate61with a delamination layer (not illustrated) located in between. The material of the carrier plate61may be, for example, Cu or a Cu alloy. The material of the metal foil62may be, for example, Cu or a Cu alloy.

The metal layer63and the wiring layer111are sequentially formed on the upper surface of the metal foil62. For example, a resist layer including openings is formed on the upper surface of the metal foil62. The openings are formed in positions corresponding to the wiring portions111A and111B. The resist layer may be formed from a material having, for example, resistance to a process (e.g., plating) that forms the metal layer63and the wiring layer111. The material of the resist layer may be, for example, a photosensitive dry film resist (e.g., novolac resin or acrylic resin).

The metal layer63and the wiring layer111are sequentially formed on the upper surface of the metal foil62through electrolytic plating (electrolytic copper plating) that uses the resist layer as a plating mask and the metal foil62as a power feeding layer. When the wiring layer111is formed by a first metal layer and a second metal layer as described above, the first metal layer and the second metal layer are sequentially formed on the upper surface of the metal layer63. Subsequently, the resist layer is removed, for example, through asking or with an alkaline stripping solution.

In the step illustrated inFIG. 10B, the magnetic layer113including the openings113Y is formed. The magnetic layer113is formed to cover the upper surface of the metal foil62, the wiring layer111, and the metal layer63. The magnetic layer113may be, for example, an uncured film formed from a magnetic material in which a magnetic filler is mixed with an insulative resin. The magnetic layer113is obtained, for example, by vacuum-laminating a film of a magnetic material and curing the film with application of heat.

The openings113Y are formed in the magnetic layer113. The openings113Y may be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are emitted toward the upper surface113aof the magnetic layer113to form the openings113Y extending through the magnetic layer113. The openings113Y partially expose the upper surfaces of the wiring portions111B. As necessary, a desmear process may be performed.

In the step illustrated inFIG. 10C, the wiring layer114is formed. The wiring layer114includes the via wirings114V, which are formed in the openings113Y, and the coil wiring114P, which is formed on the upper surface113aof the magnetic layer113. A seed layer (not illustrated) is formed on the upper surface113aof the magnetic layer113, the wall surfaces of the openings113X of the magnetic layer113, and the upper surfaces of the wiring portions111B exposed in the openings113X. The material of the seed layer may be, for example, copper or a copper alloy. The seed layer may be formed through, for example, electroless plating or sputtering.

The seed layer is covered by a resist layer (not illustrated) including openings in given locations. The openings are formed in positions corresponding to the coil wiring114P of the wiring layer114. The resist layer may be formed from a material having, for example, resistance to plating performed in the next step.

Electrolytic plating (electrolytic copper plating) that uses the seed layer as a power feeding electrode is performed to deposit and develop a plating metal on the seed layer exposed in the openings of the resist layer. The resist layer is removed, for example, through asking or with an alkaline stripping solution. Subsequently, the exposed seed layer is removed through etching. This obtains the wiring layer114including the via wirings114V and the coil wiring114P.

In the step illustrated inFIG. 11A, the openings113X are formed in the magnetic layer113to expose the wiring portions111A. The openings113X may be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are emitted toward the upper surface113aof the magnetic layer113to form the openings113X extending through the magnetic layer113. The openings113X expose the entire part of the wiring portions111A, the side surfaces of the metal layer63, and the upper surface of the metal foil62located around the wiring portions111A. As necessary, a desmear process may be performed.

In the step illustrated inFIG. 11B, the insulation layer115is formed. The insulation layer115covers the upper surface113aof the magnetic layer113, the wall surfaces of the openings113X of the magnetic layer113, the coil wiring114P of the wiring layer114, the wiring portions111A, the metal layer63, and the metal foil62located around the wiring portions111A. The material of the insulation layer115may be, for example, an organic resin such as an epoxy resin or a polyimide resin or a resin material in which such an organic resin is mixed with a filler such as silica or alumina. The insulation layer115is obtained, for example, by vacuum-laminating with a resin film and curing the resin film with application of heat. Alternatively, the insulation layer115may be formed by applying a resin paste or liquid and heating the resin.

In the step illustrated inFIG. 12A, the openings115X are formed in the insulation layer115. The openings115X may be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are emitted toward the upper surface115aof the insulation layer115to form the openings115X extending through the insulation layer115. The openings115X partially expose the upper surfaces of the wiring portions111A. As necessary, a desmear process may be performed.

In the step illustrated inFIG. 12B, the wiring layer116is formed. A seed layer (not illustrated) is formed on the upper surface115aof the insulation layer115, the wall surfaces of the openings115X of the insulation layer115, and the upper surfaces of the wiring portions111A exposed in the openings115X of the insulation layer115. The material of the seed layer may be, for example, copper or a copper alloy. The seed layer may be formed through, for example, electroless plating or sputtering. The seed layer is covered by a resist layer (not illustrated) including openings in given locations. The openings are formed in positions corresponding to the wiring portions116P of the wiring layer116. The resist layer may be formed from a material having, for example, resistance to plating performed in the next step. Electrolytic plating (electrolytic copper plating) that uses the seed layer as a power feeding electrode is performed to deposit and develop a plating metal on the seed layer exposed in the openings of the resist layer. The resist layer is removed, for example, through asking or with an alkaline stripping solution. Subsequently, the exposed seed layer is removed through etching. This obtains the wiring layer116.

In the step illustrated inFIG. 13A, the insulation layer117including the openings117X is formed. The upper surface of the insulation layer115and the wiring layer116are, for example, vacuum-laminated with an epoxy resin film. The resin film is cured by application of heat. This forms the insulation layer117. Alternatively, the insulation layer117may be formed by applying a resin paste or liquid and heating the resin. The openings117X are formed in the insulation layer117. The openings117X may be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are emitted toward the upper surface117aof the insulation layer117to form the openings117X extending through the insulation layer117. The openings117X partially expose the upper surface of the wiring layer116. As necessary, a desmear process may be performed.

In the step illustrated inFIG. 13B, the wiring layer118is formed. A seed layer (not illustrated) is formed on the upper surface of the insulation layer117, the wall surfaces of the openings117X of the insulation layer117, and the upper surface of the wiring layer116exposed in the openings117X of the insulation layer117. The material of the seed layer may be, for example, copper or a copper alloy. The seed layer may be formed through, for example, electroless plating or sputtering. The seed layer is covered by a resist layer (not illustrated) including openings in given locations. The openings are formed in positions corresponding to the wiring portions118P of the wiring layer118. The resist layer may be formed from a material having, for example, resistance to plating performed in the next step. Electrolytic plating (electrolytic copper plating) that uses the seed layer as a power feeding electrode is performed to deposit and develop a plating metal on the seed layer exposed in the openings of the resist layer. The resist layer is removed, for example, through asking or with an alkaline stripping solution. Subsequently, the exposed seed layer is removed through etching. This obtains the wiring layer118.

In the step illustrated inFIG. 14A, the solder resist layer119including the openings119X is formed. The solder resist layer119is obtained, for example, by laminating with a photosensitive solder resist film or applying a liquid solder resist and exposing and developing the resist through photolithography to be patterned in a desired shape.

In the step illustrated inFIG. 14B, the carrier plate61illustrated inFIG. 14Ais removed. The carrier plate61is delaminated from the metal foil62of the support substrate60. The delamination layer located between the carrier plate61and the metal foil62helps delaminate the carrier plate61. Then, the metal foil62and the metal layer63are removed. The metal foil62and the metal layer63are removed, for example, through wet etching that uses a hydrogen peroxide/sulfuric acid solution, a sodium persulfate solution, or an ammonium persulfate solution. At this time, the etching time is controlled so that the wiring portions111A and111B remain. When the wiring portions111A and111B include a first metal layer (e.g., Ni) and a second metal layer (e.g., Cu) as described above, the first metal layer functions as an etching stop layer so that the wiring layer111remains. This obtains the wiring substrate110illustrated inFIG. 9B.

The second embodiment has the advantages described below.

(2-1) The wiring substrate110of the second embodiment includes the line (signal wiring structure) that transmits signals in the wiring substrate110. In the example illustrated inFIG. 9B, the signal wiring structure of the wiring substrate110includes the wiring portions111A of the wiring layer111, the via wirings116V and the wiring portions116P of the wiring layer116, and the via wirings118V and the wiring portions118P of the wiring layer118. The magnetic layer113is not in direct contact with the signal wiring structure of the wiring substrate110. Thus, the wiring substrate110of the second embodiment has the same advantages as those obtained by the wiring substrate10of the first embodiment.

(2-2) The insulation layer12of the first embodiment is omitted from the wiring substrate110of the second embodiment. Thus, the wiring substrate110of the second embodiment is thinner than the wiring substrate10of the first embodiment.

Third Embodiment

The third embodiment will now be described. In the third embodiment, the same reference characters are given to those components that are the same as the corresponding components of the embodiments described above. Such components may not be described in detail.

As illustrated inFIG. 15A, a semiconductor device201includes a wiring substrate210and a semiconductor element251mounted on the wiring substrate210.

The semiconductor element251is connected to external connection pads P31A and P31B of the wiring substrate210by external connection terminals252A and252B. The semiconductor element251is flip-chip-connected to the external connection pads P31A and P31B of the wiring substrate210. The semiconductor element251is, for example, a logic chip such as a central processing unit (CPU) or a graphics processing unit (GPU). The external connection terminals252A and252B are, for example, solder bumps or gold bumps. The material of the solder bumps is, for example, an alloy containing lead, an alloy of tin and gold, an alloy of tin and copper, an alloy of thin and silver, or an alloy of tin, silver, and copper.

An underfill resin253is formed between the semiconductor element251and the wiring substrate210. The material of the underfill resin253may be, for example, an insulative resin such as an epoxy resin.

The wiring substrate210includes external connection pads P32. The external connection pads P32are exposed from the lower surface of the wiring substrate210. The external connection pads P32are connected to external connection terminals255. The external connection terminals255are used to mount the wiring substrate210on, for example, a mount board such as a motherboard. The external connection terminals255are, for example, solder bumps. The material of the solder bumps may be, for example, an alloy containing lead (Pb), an alloy of Sn and Cu, an alloy of Sn and silver (Ag), or an alloy of Sn, Ag, and Cu. The external connection terminals255may be solder balls or lead pins.

The semiconductor element251, which is mounted on the wiring substrate210, sends signals to the external connection pads P31A and receives signals from the external connection pads P31A. The wiring substrate210transmits signals between the external connection pads P31A and the external connection pads P32. The wiring substrate210includes a conductor (signal wiring structure) arranged between the external connection pads P31A and the external connection pads P32to transmit signals. The signal wiring structure of the wiring substrate210transmits a signal output from the semiconductor element251through the external connection pads P31A to the external connection pads P32. The signal is provided to the mount board via the external connection terminals255, which are connected to the external connection pads P32. Also, when receiving a signal output from the mount board via the external connection terminals255, the signal wiring structure of the wiring substrate210transmits the signal from the external connection pads P32to the external connection pads P31A. The signal is transmitted to the semiconductor element251via the external connection terminals252A, which are connected to the external connection pads P31A.

The wiring substrate210incorporates a coil241. In the third embodiment, the coil241is connected to the external connection pads P31B of the wiring substrate210. The external connection pads P31B are connected to the semiconductor element251. Thus, in the third embodiment, the coil241of the wiring substrate210is connected to the semiconductor element251.

As illustrated inFIG. 15B, the wiring substrate210includes a core substrate211. The core substrate211is located substantially in the middle of the wiring substrate210in the thickness-wise direction. The core substrate211includes through holes211X and211Y extending through the core substrate211from an upper surface211ato a lower surface211bin give locations. Through electrodes212A and212B are formed in the through holes211X and211Y.

The material of the core substrate211may be, for example, a glass-epoxy resin obtained by impregnating a glass cloth (glass woven cloth), which functions as a reinforcement material, with a thermosetting insulative resin, the main component of which is an epoxy resin, and curing the resin. The reinforcement material is not limited to a glass cloth and may be, for example, a glass non-woven cloth, an aramid woven cloth, an aramid non-woven cloth, a liquid crystal polymer (LCP) woven cloth, or an LCP non-woven cloth. The thermosetting insulative resin is not limited to an epoxy resin and may be, for example, a resin material such as a polyimide resin or a cyanate resin. The material of the through electrodes212A and212B may be, for example, copper (Cu) or a Cu alloy.

The wiring substrate210includes a wiring layer221, a magnetic layer222, and an insulation layer223at the side of the lower surface211bof the core substrate211. The wiring substrate210further includes a wiring layer231, an insulation layer232, and a wiring layer233at the side of the upper surface211aof the core substrate211.

The wiring layer221is formed on the lower surface211bof the core substrate211. The wiring layer221includes wiring portions221A and a coil wiring221P, which is included in the coil241. The coil wiring221P of the third embodiment is a planar coil spirally formed on the lower surface211bof the core substrate211. The two opposite ends of the coil wiring221P are connected to the through electrodes212B. The wiring portions221A are connected to the through electrodes212A. The material of the wiring layer221may be, for example, Cu or a Cu alloy.

The magnetic layer222is formed on the lower surface211bof the core substrate211to cover the coil wiring221P of the wiring layer221. The magnetic layer222includes openings222X, which expose the wiring portions221A of the wiring layer221. The openings222X expose the lower surface211bof the core substrate211located around the wiring portions221A. The magnetic layer222may be formed from a magnetic material in which a magnetic filler is mixed with an insulative resin. The insulative resin may be, for example, an epoxy resin or a polyimide resin. The magnetic filler may be, for example, manganese (Mn)-zinc (Zn) ferrite, Ni—Zn ferrite, an iron (Fe)-cobalt (Co) alloy, or an Fe-silicon (Si) alloy.

The insulation layer223covers a lower surface222bof the magnetic layer222and the wall surfaces of the openings222X of the magnetic layer222. The insulation layer223also covers part of the wiring portions221A of the wiring layer221located inward from the openings222X of the magnetic layer222and the lower surface211bof the core substrate211located around the wiring portions221A. The insulation layer223includes openings223X, which partially expose lower surfaces221Ab of the wiring portions221A of the wiring layer221inward from the openings222X of the magnetic layer222. The openings223X partially expose the lower surfaces221Ab of the wiring portions221A as the external connection pads P32. The material of the insulation layer223may be, for example, an insulative resin, the main component of which is a photosensitive resin such as a phenol resin or a polyimide resin, or a thermosetting insulative resin, the main component of which is an epoxy resin. The insulative resin may contain, for example, a filler such as silica or alumina.

InFIG. 15A, the lower surfaces of the wiring portions221A partially exposed by the openings223X serve as the external connection pads P32. Instead, a wiring layer including via wirings filling the openings223X and wiring portions connected to the wiring portions221A by the via wirings may be formed on the lower surface of the insulation layer223. Further, an additional insulation layer and an additional wiring layer may be stacked at the lower surface side of the insulation layer223. In this structure, the lower surface of the lowermost wiring layer may be used as the external connection pads. Additionally, the lowermost wiring layer may be partially covered by a solder resist layer.

The wiring layer231is formed on the upper surface211aof the core substrate211. The wiring layer231includes wiring portions231A and231B. The wiring portions231A are connected via the through electrodes212A to the wiring portions221A, which are located on the lower surface211bof the core substrate211. The wiring portions231B are connected via the through electrodes212B to the coil wiring221P, which is located on the lower surface211bof the core substrate211. The material of the wiring layer231may be, for example, Cu or a Cu alloy.

The insulation layer232is formed on the upper surface211aof the core substrate211to cover the wiring layer231. The insulation layer232includes openings232X and232Y, which partially expose the upper surface of the wiring layer231. The openings232X partially expose the upper surfaces of the wiring portions231A of the wiring layer231. The openings232Y partially expose the upper surfaces of the wiring portions231B of the wiring layer231. The material of the insulation layer232may be, for example, an insulative resin, the main component of which is a photosensitive resin such as a phenol resin or a polyimide resin, or a thermosetting insulative resin, the main component of which is an epoxy resin. The insulative resin may contain, for example, a filler such as silica or alumina.

The wiring layer233is formed on an upper surface232aof the insulation layer232. The wiring layer233includes wiring portions233A and233B, which are formed on the upper surface232aof the insulation layer232, and via wirings233AV and233BV, which are formed in the openings232X and232Y of the insulation layer232. The via wirings233AV connect the wiring portions233A of the wiring layer233to the wiring portions231A of the wiring layer231. The via wirings233BV connect the wiring portions233B of the wiring layer233to the wiring portions231B of the wiring layer231. The material of the wiring layer233may be, for example, Cu or a Cu alloy.

A solder resist layer234is formed on the upper surface232aof the insulation layer232. The solder resist layer234covers the upper surface232aof the insulation layer232and part of the wiring layer233. The solder resist layer234includes openings234X, which partially expose the upper surfaces of the wiring portions233A of the wiring layer233as the external connection pads P31A, and openings234Y, which partially expose the upper surfaces of the wiring portions233B of the wiring layer233as the external connection pads P31B. The material of the solder resist layer234may be, for example, an insulative resin such as an epoxy resin or an acrylic resin.

As necessary, an OSP process may be performed on the upper surface of the wiring layer233exposed from the openings234X and234Y of the solder resist layer234to form an OSP film. Also, a metal layer may be formed on the upper surface of the wiring portions233A and233B exposed from the openings234X and234Y. The metal layer is, for example, an Au layer, a Ni layer/Au layer (metal layer in which Au layer is formed on Ni layer that serves as bottom layer), or a Ni layer/Pd layer/Au layer (metal layer in which Ni layer serves as bottom layer, and Ni layer, Pd layer, and Au layer are sequentially stacked). The wiring portions233A and233B (or OSP film or metal layer formed on wiring portions233A and233B) exposed from the openings234X and234Y may be used as the external connection pads P31A and P31B.

Manufacturing Steps

The steps of manufacturing the wiring substrate210of the third embodiment will now be described.

As illustrated inFIG. 16A, the core substrate211is prepared. The core substrate211may be, for example, a copper clad laminate (CCL). The through holes211X and211Y are formed in the core substrate211. The through electrodes212A and212B are formed in the through holes211X and211Y, for example, through electrolytic plating or conductive paste filling. Subsequently, the wiring layers221(221A,221P) and231(231A,231B) are formed through a subtractive process.

In the step illustrated inFIG. 16B, the magnetic layer222and the insulation layer232are formed. The magnetic layer222is formed to cover the lower surface211bof the core substrate211and the wiring layer221. The magnetic layer222may be, for example, an uncured film formed from a magnetic material in which a magnetic filler is mixed with an insulative resin. The magnetic layer222is obtained, for example, by vacuum-laminating a film of a magnetic material and curing the film with application of heat. Additionally, the insulation layer232is formed to cover the upper surface211aof the core substrate211and the wiring layer231. The material of the insulation layer232may be, for example, an organic resin such as an epoxy resin or a polyimide resin or a resin material in which such an organic resin is mixed with a filler such as silica or alumina. The insulation layer232is obtained, for example, by vacuum-laminating with a resin film and curing the resin film with application of heat. Alternatively, the insulation layer232may be formed by applying a resin paste or liquid and heating the resin.

In the step illustrated inFIG. 16C, the openings222X are formed in the magnetic layer222, and the openings232X and232Y are formed in the insulation layer232. The openings222X may be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are emitted toward the lower surface222bof the magnetic layer222to form the openings222X extending through the magnetic layer222. The openings222X expose the entire part of the wiring portions221A and the lower surface211bof the core substrate211located around the wiring portions221A. As necessary, a desmear process may be performed. Laser beams are also emitted toward the upper surface232aof the insulation layer232to form the openings232X and232Y extending through the insulation layer232. The openings232X and232Y partially expose the upper surfaces of the wiring portions231A and231B. As necessary, a desmear process may be performed.

In the step illustrated inFIG. 17A, the insulation layer223is formed to cover the magnetic layer222. The material of the insulation layer223may be, for example, an organic resin such as an epoxy resin or a polyimide resin or a resin material in which such an organic resin is mixed with a filler such as silica or alumina. The insulation layer223is obtained, for example, by vacuum-laminating with a resin film and curing the resin film with application of heat. Alternatively, the insulation layer223may be formed by applying a resin paste or liquid and heating the resin.

In the step illustrated inFIG. 17B, the wiring layer233is formed on the upper surface of the insulation layer232. The wiring layer233includes the via wirings233AV and233BV, which are formed in the openings232X and232Y of the insulation layer232, and the wiring portions233A and233B, which are formed on the upper surface232aof the insulation layer232. A seed layer (not illustrated) is formed on the upper surface232aof the insulation layer232, the wall surfaces of the openings232X and232Y of the insulation layer232, and the upper surface of the wiring layer231(upper surfaces of wiring portions231A and231B) exposed in the openings232X and232Y. The material of the seed layer may be, for example, copper or a copper alloy. The seed layer may be formed through, for example, electroless plating or sputtering.

The seed layer is covered by a resist layer (not illustrated) including openings in given locations. The openings are formed in positions corresponding to the wiring portions233A and233B of the wiring layer233. The resist layer may be formed from a material having, for example, resistance to plating performed in the next step. Electrolytic plating (electrolytic copper plating) that uses the seed layer as a power feeding electrode is performed to deposit and develop a plating metal on the seed layer exposed in the openings of the resist layer. The resist layer is removed, for example, through ashing or with an alkaline stripping solution. Subsequently, the exposed seed layer is removed through etching. This obtains the wiring layer233including the via wirings233AV and233BV and the wiring portions233A and233B.

In the step illustrated inFIG. 18A, the openings223X are formed in the insulation layer223. The openings223X may be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are emitted toward a lower surface223bof the insulation layer223to form the openings223X located inward from the openings222X of the magnetic layer222and extending through the insulation layer223. The openings223X partially expose the lower surfaces of the wiring portions221A of the wiring layer221. As necessary, a desmear process may be performed.

In the step illustrated inFIG. 18B, the solder resist layer234including the openings234X and234Y is formed. The solder resist layer234is obtained, for example, by laminating with a photosensitive solder resist film or applying a liquid solder resist and exposing and developing the resist through photolithography to be patterned in a desired shape.

The third embodiment has the advantages described below.

(3-1) The wiring substrate210of the third embodiment includes the line (signal wiring structure) that transmits signals in the wiring substrate210. In the example illustrated inFIG. 15B, the signal wiring structure of the wiring substrate210includes the wiring portions221A of the wiring layer221, the through electrodes212A, the wiring portions231A of the wiring layer231, and the via wirings233AV and the wiring portions233A of the wiring layer233. The magnetic layer222is not in direct contact with the signal wiring structure of the wiring substrate210. Thus, the wiring substrate210of the third embodiment including the core substrate211has the same advantages as those obtained by the wiring substrate10of the first embodiment.

Fourth Embodiment

A fourth embodiment will now be described. In the fourth embodiment, the same reference characters are given to those components that are the same as the corresponding components of the first embodiment. Such components may not be described in detail.

As illustrated inFIG. 19A, a semiconductor device301includes a wiring substrate310and the semiconductor element251mounted on the wiring substrate310.

The semiconductor element251is connected to external connection pads P41A and P41B of the wiring substrate310by the external connection terminals252A and252B. The semiconductor element251is flip-chip-connected to the external connection pads P41A and P41B of the wiring substrate310. The semiconductor element251is, for example, a logic chip such as a central processing unit (CPU) or a graphics processing unit (GPU). The external connection terminals252A and252B are, for example, solder bumps or gold bumps. The material of the solder bumps may be, for example, an alloy containing lead, an alloy of tin and gold, an alloy of tin and copper, an alloy of tin and silver, or an alloy of tin, silver, and copper.

The underfill resin253is formed between the semiconductor element251and the wiring substrate310. The material of the underfill resin253may be, for example, an insulative resin such as an epoxy resin.

The wiring substrate310includes external connection pads P42. The external connection pads P42are exposed from the lower surface of the wiring substrate310. The external connection terminals255are connected to the external connection pads P42. The external connection terminals255are used to mount the wiring substrate310on, for example, a mount board such as a motherboard. The external connection terminals255are, for example, solder bumps. The material of the solder bumps may be, for example, an alloy containing lead (Pb), an alloy of Sn and Cu, an alloy of Sn and silver (Ag), or an alloy of Sn, Ag, and Cu. The external connection terminals255may be solder balls or lead pins.

The semiconductor element251, which is mounted on the wiring substrate310, sends signals to the external connection pads P41A and receives signals from the external connection pads P41A. The wiring substrate310transmits signals between the external connection pads P41A and the external connection pads P42. The wiring substrate310includes a conductor (signal wiring structure) arranged between the external connection pads P41A and the external connection pads P42to transmit signals. The signal wiring structure of the wiring substrate310transmits a signal output from the semiconductor element251through the external connection pads P41A to the external connection pads P42. The signal is provided to the mount board via the external connection terminals255, which are connected to the external connection pads P42. Also, when receiving a signal output from the mount board via the external connection terminals255, the signal wiring structure of the wiring substrate310transmits the signal from the external connection pads P42to the external connection pads P41A. The signal is provided to the semiconductor element251via the external connection terminals252A, which are connected to the external connection pads P41A.

The wiring substrate310incorporates a coil341. In the fourth embodiment, the coil341is connected to the external connection pads P41B of the wiring substrate310. The external connection pads P41B are connected to the semiconductor element251. Thus, in the fourth embodiment, the coil341of the wiring substrate310is connected to the semiconductor element251.

As illustrated inFIG. 19B, the wiring substrate310includes a core substrate311. The core substrate311is located substantially in the middle of the wiring substrate310in the thickness-wise direction. The core substrate311includes through holes311X and311Y extending through the core substrate311from an upper surface311ato a lower surface311bin given locations. Through electrodes312A and312B are formed in the through holes311X and311Y.

The material of the core substrate311may be, for example, a glass-epoxy resin obtained by impregnating a glass cloth (glass woven cloth), which functions as a reinforcement material, with a thermosetting insulative resin, the main component of which is an epoxy resin, and curing the resin. The reinforcement material is not limited to a glass cloth and may be, for example, a glass non-woven cloth, an aramid woven cloth, an aramid non-woven cloth, a liquid crystal polymer (LCP) woven cloth, or an LCP non-woven cloth. The thermosetting insulative resin is not limited to an epoxy resin and may be, for example, a resin material such as a polyimide resin or a cyanate resin. The material of the through electrodes312A and312B may be, for example, copper (Cu) or a Cu alloy.

The wiring substrate310includes a wiring layer321, an insulation layer322, a wiring layer323, and a magnetic layer324at the side of the lower surface311bof the core substrate311. The wiring substrate310further includes a wiring layer331, an insulation layer332, and a wiring layer333at the side of the upper surface311aof the core substrate311.

The wiring layer321is formed on the lower surface311bof the core substrate311. The wiring layer321includes a coil wiring321P and wiring portions321A. Two opposite sides of the coil wiring321P are connected to the through electrodes312B. The wiring portions321A are connected to the through electrodes312A. The material of the wiring layer321may be, for example, Cu or a Cu alloy.

The insulation layer322is formed on the lower surface311bof the core substrate311to cover the wiring layer321. The insulation layer322includes openings322Y, which partially expose a lower surface321Pb of the coil wiring321P of the wiring layer321, and openings322X, which partially expose lower surfaces321Ab of the wiring portions321A of the wiring layer321.

The wiring layer323is formed on a lower surface322bof the insulation layer322. The wiring layer323includes a coil wiring323P and wiring portions323A, which are formed on the lower surface322bof the insulation layer322, and via wirings323PV and323AV, which are formed in the openings322Y and322X of the insulation layer322. The material of the wiring layer323may be, for example, Cu or a Cu alloy.

The coil wiring323P of the wiring layer323is connected to the coil wiring321P of the wiring layer321by the via wirings323PV of the wiring layer323. The wiring portions323A of the wiring layer323are connected to the wiring portions321A of the wiring layer321by the via wirings323AV of the wiring layer323.

The coil wiring321P of the wiring layer321, the coil wiring323P of the wiring layer323, and the via wirings323PV of the wiring layer323form a helical coil. Thus, the coil341of the wiring substrate310of the fourth embodiment is formed by the coil wirings321P and323P, which are located in two layers, and the via wirings323PV connecting the coil wirings321P and323P.

The magnetic layer324is formed on the lower surface322bof the insulation layer322to cover the coil wiring323P of the wiring layer323. The magnetic layer324includes openings324X, which expose the wiring portions323A of the wiring layer323. The openings324X expose the lower surface322bof the insulation layer322located around the wiring portions323A.

The magnetic layer324may be formed from a magnetic material in which a magnetic filler is mixed with an insulative resin. The insulative resin may be, for example, an epoxy resin or a polyimide resin. The magnetic filler may be, for example, manganese (Mn)-Zinc (Zn) ferrite, Ni—Zn ferrite, an iron (Fe)-cobalt (Co) alloy, or an Fe-silicon (Si) alloy.

The wiring layer331is formed on the upper surface311aof the core substrate311. The wiring layer331includes wiring portions331B and331A. The wiring portions331B are connected via the through electrodes312B to the coil wiring321P, which is located on the lower surface311bof the core substrate311. The wiring portions331A are connected via the through electrodes312A to the wiring portions321A, which are located on the lower surface311bof the core substrate311. The material of the wiring layer331may be, for example, Cu or a Cu alloy.

The insulation layer332is formed on the upper surface311aof the core substrate311to cover the wiring layer331. The insulation layer332includes openings332X and332Y, which partially expose the upper surface of the wiring layer331. The openings332X partially expose the upper surfaces of the wiring portions331A of the wiring layer331. The openings332Y partially expose the upper surfaces of the wiring portions331B of the wiring layer331. The material of the insulation layer332may be, for example, an insulative resin, the main component of which is a photosensitive resin such as a phenol resin or a polyimide resin, or a thermosetting insulative resin, the main component of which is an epoxy resin. The insulative resin may contain, for example, a filler such as silica or alumina.

The wiring layer333is formed on an upper surface332aof the insulation layer332. The wiring layer333includes wiring portions333A and333B, which are formed on the upper surface332aof the insulation layer332, and via wirings333AV and333BV, which are formed in the openings332X and332Y of the insulation layer332. The via wirings333AV connect the wiring portions333A of the wiring layer333to the wiring portions331A of the wiring layer331. The via wirings333BV connect the wiring portions333B of the wiring layer333to the wiring portions331B of the wiring layer331. The material of the wiring layer333may be, for example, Cu or a Cu alloy.

A solder resist layer334is formed on the upper surface332aof the insulation layer332. The solder resist layer334covers the upper surface332aof the insulation layer332and part of the wiring layer333. The solder resist layer334includes openings334X, which partially expose the upper surfaces of the wiring portions333A of the wiring layer333as the external connection pads P41A, and openings334Y, which partially expose the upper surfaces of the wiring portions333B of the wiring layer333as the external connection pads P41B. The material of the solder resist layer334may be, for example, an insulative resin such as an epoxy resin or an acrylic resin.

As necessary, an OSP process may be performed on the upper surfaces of the wiring portions333A and333B exposed from the openings334X and334Y of the solder resist layer334to form an OSP film. Also, a metal layer may be formed on the upper surfaces of the wiring portions333A and333B exposed from the openings334X and334Y. The metal layer is, for example, an Au layer, a Ni layer/Au layer (metal layer in which Au layer is formed on Ni layer that serves as bottom layer), or a Ni layer/Pd layer/Au layer (metal layer in which Ni layer serves as bottom layer, and Ni layer, Pd layer, and Au layer are sequentially stacked). The wiring portions333A and333B (or OSP film or metal layer formed on wiring portions333A and333B) exposed from the openings334X and334Y may be used as the external connection pads P41A and P41B.

Manufacturing Steps

The steps of manufacturing the wiring substrate310of the fourth embodiment will now be described.

In the step illustrated inFIG. 20A, the through electrodes312A and312B and the wiring layers321and331are formed on the core substrate311. The core substrate311may be, for example, a copper clad laminate (CCL). The through holes311X and311Y are formed in the core substrate311. The through electrodes312A and312B are formed in the through holes311X and311Y, for example, through electrolytic plating or conductive paste filling. Subsequently, the wiring layers321and331are formed through a subtractive process. The wiring layer321includes the wiring portions321A and the coil wiring321P. The wiring layer331includes the wiring portions331A and331B.

In the step illustrated inFIG. 20B, the insulation layer322including the openings322X and322Y and the insulation layer332including the openings332X and332Y are formed. The material of the insulation layers322and332may be, for example, an organic resin such as an epoxy resin or a polyimide resin or a resin material in which such an organic resin is mixed with a filler such as silica or alumina. For example, the lower surface311bof the core substrate311and the wiring layer321are laminated with a resin film, and the resin film is cured by application of heat to form the insulation layer322. In the same manner, the upper surface311aof the core substrate311and the wiring layer331are laminated with a resin film, and the resin film is cured by application of heat to form the insulation layer332.

The openings322X and322Y may be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are emitted toward the lower surface322bof the insulation layer322to form the openings322X and322Y extending through the insulation layer322. The openings322Y partially expose the lower surface of the coil wiring321P of the wiring layer321. In the same manner, the openings322X partially expose the lower surfaces of the wiring portions321A. As necessary, a desmear process may be performed.

The openings332X and332Y may also be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are emitted toward the upper surface332aof the insulation layer332to form the openings332X and332Y extending through the insulation layer332. The openings332X partially expose the upper surfaces of the wiring portions331A of the wiring layer331. In the same manner, the openings332Y partially expose the upper surfaces of the wiring portions331B. As necessary, a desmear process may be performed.

In the step illustrated inFIG. 21A, the wiring layers323and333are formed. Seed layers (not illustrated) are formed on the surfaces of the insulation layers322and332. In the example illustrated inFIG. 21A, a seed layer is formed on the lower surface of the insulation layer322, the wall surfaces of the openings322X and322Y, and the lower surface of the wiring layer321exposed in the openings322X and322Y. In the same manner, a seed layer is formed on the upper surface of the insulation layer332, the wall surfaces of the openings332X and332Y, and the upper surface of the wiring layer331exposed in the openings332X and332Y. The material of the seed layers may be, for example, copper or a copper alloy. The seed layers may be formed through, for example, electroless plating or sputtering.

Each of the seed layers is covered by a resist layer (not illustrated) including openings in given locations. The openings are formed in positions corresponding to the shapes of the wiring layers323and333.

The resist layer may be formed from a material having, for example, resistance to plating performed in the next step. Electrolytic plating (electrolytic copper plating) that uses the seed layers as power feeding electrodes is performed to deposit and develop a plating metal on the seed layers exposed in the openings of the resist layers. The resist layers are removed, for example, through asking or with an alkaline stripping solution. Subsequently, the exposed seed layers are removed through etching. This obtains the wiring layer323including the via wirings323AV and323PV, the wiring portions323A, and the coil wiring323P and also obtains the wiring layer333including the via wirings333AV and333BV and the wiring portions333A and333B.

In the step illustrated inFIG. 21B, the magnetic layer324is formed to cover the lower surface322bof the insulation layer322and the wiring layer323. The magnetic layer324may be, for example, an uncured film formed from a magnetic material in which a magnetic filler is mixed with an insulative resin. The magnetic layer324is obtained, for example, by vacuum-laminating a film of a magnetic material and curing the film with application of heat.

In the step illustrated inFIG. 22A, the openings324X are formed in the magnetic layer324. The openings324X may be formed, for example, with a laser drilling machine such as a CO2laser or a UV-YAG layer. Laser beams are emitted toward a lower surface324bof the magnetic layer324to form the openings324X extending through the magnetic layer324. The openings324X expose the entire part of the wiring portions323A of the wiring layer323and the lower surface322bof the insulation layer322located around the wiring portions323A. As necessary, a desmear process may be performed.

In the step illustrated inFIG. 22B, the solder resist layer334including the openings334X,334Y is formed. The solder resist layer334is obtained, for example, by laminating with a photosensitive solder resist film or applying a liquid solder resist and exposing and developing the resist through photolithography to be patterned in a desired shape.

The fourth embodiment has the advantages described below.

(4-1) The wiring substrate310of the fourth embodiment includes the line (signal wiring structure) that transmits signals in the wiring substrate310. In the example illustrated inFIG. 19B, the signal wiring structure of the wiring substrate310includes the wiring portions323A and the via wirings323AV of the wiring layer323, the wiring portions321A of the wiring layer321, the through electrodes312A, the wiring portions331A of the wiring layer331, and the via wirings333AV and the wiring portions333A of the wiring layer333. The magnetic layer324is not in direct contact with the signal wiring structure of the wiring substrate310. Thus, the wiring substrate310of the fourth embodiment including the core substrate311has the same advantages as those obtained by the wiring substrate10of the first embodiment.

COMPARATIVE EXAMPLE

A comparative example will now be described. In the comparative example, the same reference characters are given to those components that are the same as the corresponding components of the above embodiments. Such components may not be described in detail.

In the comparative example illustrated inFIG. 23, a semiconductor device401includes a wiring substrate410and the semiconductor element251mounted on the wiring substrate410.

The semiconductor element251is connected to the external connection pads P41A and P41B of the wiring substrate410by the external connection terminals252A and252B. The semiconductor element251is flip-chip-connected to the external connection pads P41A and P41B of the wiring substrate410. The semiconductor element251is, for example, a logic chip such as a central processing unit (CPU) or a graphics processing unit (GPU). The external connection terminals252A and252B are, for example, solder bumps or gold bumps. The material of solder bumps may be, for example, an alloy containing lead, an alloy of tin and gold, an alloy of tin and copper, an alloy of tin and silver, or an alloy of tin, silver, and copper.

The underfill resin253is formed between the semiconductor element251and the wiring substrate410. The material of the underfill resin253may be, for example, an insulative resin such as an epoxy resin.

The wiring substrate410includes external connection pads P52. The external connection pads P52are exposed from the lower surface of the wiring substrate410. The external connection terminals255are connected to the external connection pads P52. The external connection terminals255are used to mount the wiring substrate410on, for example, a mount board such as a motherboard. The external connection terminals255are, for example, solder bumps. The material of the solder bumps may be, for example, an alloy containing lead (Pb), an alloy of Sn and Cu, an alloy of Sn and silver (Ag), or an alloy of Sn, Ag, and Cu. The external connection terminals255may be solder balls or lead pins.

The semiconductor element251, which is mounted on the wiring substrate410, sends signals to the external connection pads P41A and receives signals from the external connection pads P41A. The wiring substrate410transmits signals between the external connection pads P41A and the external connection pads P52. The wiring substrate410includes a conductor (signal wiring structure) arranged between the external connection pads P41A and the external connection pads P52to transmit signals. The signal wiring structure of the wiring substrate410transmits a signal output from the semiconductor element251through the external connection pads P41A to the external connection pads P52. The signal is provided to the mount board via the external connection terminals255, which are connected to the external connection pads P52. Also, when receiving a signal output from the mount board via the external connection terminals255, the signal wiring structure of the wiring substrate410transmits the signal from the external connection pads P52to the external connection pads P41A. The signal is provided to the semiconductor element251via the external connection terminals252A, which are connected to the external connection pads P41A.

The wiring substrate410incorporates the coil341. The coil341is connected to the external connection pads P41B of the wiring substrate410. The external connection pads P41B are connected to the semiconductor element251. Thus, the coil341of the wiring substrate410is connected to the semiconductor element251.

As illustrated inFIG. 23B, the wiring substrate410includes the core substrate311. The core substrate311is arranged substantially in the middle of the wiring substrate410in the thickness-wise direction. The core substrate311includes the through holes311X and311Y extending through the core substrate311from the upper surface311ato the lower surface311bin given locations. The through electrodes312A and312B are formed in the through holes311X and311Y.

The material of the core substrate311may be, for example, a glass-epoxy resin obtained by impregnating a glass cloth (glass woven cloth), which functions as a reinforcement material, with a thermosetting insulative resin, the main component of which is an epoxy resin, and curing the resin. The reinforcement material is not limited to a glass cloth and may be, for example, a glass non-woven cloth, an aramid woven cloth, an aramid non-woven cloth, a liquid crystal polymer (LCP) woven cloth, or an LCP non-woven cloth. The thermosetting insulative resin is not limited to an epoxy resin and may be, for example, a resin material such as a polyimide resin or a cyanate resin. The material of the through electrodes312A and312B may be, for example, copper (Cu) or a Cu alloy.

The wiring substrate410includes the wiring layer321, the insulation layer322, the wiring layer323, and a magnetic layer424at the side of the lower surface311bof the core substrate311. The wiring substrate410further includes the wiring layer331, the insulation layer332, and the wiring layer333at the side of the upper surface311aof the core substrate311.

The wiring layer321is formed on the lower surface311bof the core substrate311. The wiring layer321includes the coil wiring321P and the wiring portions321A. Two opposite ends of the coil wiring321P are connected to the through electrodes312B. The wiring portions321A are connected to the through electrodes312A. The material of the wiring layer321may be, for example, Cu or a Cu alloy.

The insulation layer322is formed on the lower surface311bof the core substrate311to cover the wiring layer321. The insulation layer322includes the openings322Y, which partially expose the lower surface321Pb of the coil wiring321P of the wiring layer321, and the openings322X, which partially expose the lower surfaces321Ab of the wiring portions321A of the wiring layer321.

The wiring layer323is formed on the lower surface322bof the insulation layer322. The wiring layer323includes the coil wiring323P and the wiring portions323A, which are formed on the lower surface322bof the insulation layer322, and the via wirings323PV and323AV, which are formed in the openings322Y and322X of the insulation layer322. The material of the wiring layer323may be, for example, Cu or a Cu alloy.

The coil wiring323P of the wiring layer323is connected to the coil wiring321P of the wiring layer321by the via wirings323PV of the wiring layer323. The wiring portions323A of the wiring layer323are connected to the wiring portions321A of the wiring layer321by the via wirings323AV of the wiring layer323.

The coil wiring321P of the wiring layer321, the coil wiring323P of the wiring layer323, and the via wirings323PV of the wiring layer323form a helical coil. Thus, the coil341of the wiring substrate410is formed by the coil wirings321P and323P, which are located in two layers, and the via wirings323PV connecting the coil wirings321P and323P.

The magnetic layer424is formed on the lower surface322bof the insulation layer322to cover the coil wiring323P of the wiring layer323. The magnetic layer424includes openings424X, which partially expose the lower surfaces of the wiring portions323A of the wiring layer323.

The material of the magnetic layer424may be the same as that of the embodiments described above and be a magnetic material in which a magnetic filler is mixed with an insulative resin. The insulative resin may be, for example, an epoxy resin or a polyimide resin. The magnetic filler may be, for example, manganese (Mn)-Zinc (Zn) ferrite, Ni—Zn ferrite, an iron (Fe)-cobalt (Co) alloy, or an Fe-silicon (Si) alloy.

The wiring layer331is formed on the upper surface311aof the core substrate311. The wiring layer331includes the wiring portions331B and331A. The wiring portions331B are connected via the through electrodes312B to the coil wiring321P, which is located on the lower surface311bof the core substrate311. The wiring portions331A are connected via the through electrodes312A to the wiring portions321A, which are located on the lower surface311bof the core substrate311. The material of the wiring layer331may be, for example, Cu or a Cu alloy.

The insulation layer332is formed on the upper surface311aof the core substrate311to cover the wiring layer331. The insulation layer332includes the openings332X and332Y, which partially expose the upper surface of the wiring layer331. The openings332X partially expose the upper surfaces of the wiring portions331A of the wiring layer331. The openings332Y partially expose the upper surfaces of the wiring portions331B of the wiring layer331. The material of the insulation layer332may be, for example, an insulative resin, the main component of which is a photosensitive resin such as a phenol resin or a polyimide resin, or a thermosetting insulative resin, the main component of which is an epoxy resin. The insulative resin may contain, for example, a filler such as silica or alumina.

The wiring layer333is formed on the upper surface332aof the insulation layer332. The wiring layer333includes the wiring portions333A and333B, which are formed on the upper surface332aof the insulation layer332, and the via wirings333AV and333BV, which are formed in the openings332X and332Y of the insulation layer332. The via wirings333AV connect the wiring portions333A of the wiring layer333to the wiring portions331A of the wiring layer331. The via wirings333BV connect the wiring portions333B of the wiring layer333to the wiring portions331B of the wiring layer331. The material of the wiring layer333may be, for example, Cu or a Cu alloy.

The solder resist layer334is formed on the upper surface332aof the insulation layer332. The solder resist layer334covers the upper surface332aof the insulation layer332and part of the wiring layer333. The solder resist layer334includes the openings334X, which partially expose the upper surfaces of the wiring portions333A of the wiring layer333as the external connection pads P41A, and the openings334Y, which partially expose the upper surfaces of the wiring portions333B of the wiring layer333as the external connection pads P41B. The material of the solder resist layer334may be, for example, an insulative resin such as an epoxy resin or an acrylic resin.

As necessary, an OSP process may be performed on the upper surfaces of the wiring portions333A and333B exposed from the openings334X and334Y of the solder resist layer334to form an OSP film. Also, a metal layer may be formed on the upper surfaces of the wiring portions333A and333B exposed from the openings334X and334Y. The metal layer is, for example, an Au layer, a Ni layer/Au layer (metal layer in which Au layer is formed on Ni layer that serves as bottom layer), or a Ni layer/Pd layer/Au layer (metal layer in which Ni layer serves as bottom layer, and Ni layer, Pd layer, and Au layer are sequentially stacked).

In the comparative example, the magnetic layer424is in direct contact with part of the lower surfaces of the wiring portions323A of the wiring layer323and the side surfaces of the wiring portions323A of the wiring layer323. The magnetic layer424affects signals transmitted through the signal wiring structure of the wiring substrate410and increases the transmission loss as compared to the wiring substrate310of the fourth embodiment.

It should be apparent to those skilled in the art that the foregoing embodiments may be implemented in many other specific forms without departing from the scope of this disclosure. Particularly, it should be understood that the foregoing embodiments may be implemented in the following forms.

In the first embodiment, as illustrated inFIG. 1B, the lower surfaces11Ab,11Bb of the wiring layer11(wiring portions11A and11B) are located at higher positions than a lower surface12bof the insulation layer12so that the lower surfaces11Ab,11Bb of the wiring layer11(wiring portions11A and11B) and the openings12bX and12bY in the lower surface12bof the insulation layer12form recesses. Instead, the lower surfaces11Ab,11Bb of the wiring layer11(wiring portions11A and11B) may be located at the same position as the lower surface12bof the insulation layer12. In the same manner, in the second embodiment, the lower surface of the wiring layer111(wiring portions111A and111B) may be located at the same position as the lower surfaces of the magnetic layer113and the insulation layer115.

In the first embodiment, a solder resist layer may be formed on the lower surface of the insulation layer12. In the same manner, in the second embodiment, a solder resist layer may be formed on the lower surface of the magnetic layer113.

In the first embodiment, the wiring substrate10includes the spiral coil wiring14P of the wiring layer14located on the upper surface13aof the magnetic layer13. Instead, in the same manner as the fourth embodiment, the wiring substrate10may include a helical coil wiring including wiring portions of multiple wiring layers. In the same manner, the wiring substrate110of the second embodiment may include a helical coil wiring including wiring portions of multiple wiring layers. Also, the wiring substrate210of the third embodiment may include a helical coil wiring including wiring portions of multiple wiring layers.

In the fourth embodiment, the coil is formed by the coil wirings321P and323P of the two wiring layers321and323and the via wirings323PV connecting the coil wirings321P and323P. Instead, a coil may be formed by coil wirings included in three or more wiring layers and via wirings connecting the coil wirings.

In the first embodiment, the wiring substrate10may be configured so that the coil wiring14P of the wiring layer14is connected to the semiconductor element51. In the same manner, the wiring substrate110of the second embodiment may be configured so that the coil wiring114P of the wiring layer114is connected to the semiconductor element51.

In the third embodiment, the wiring substrate210may be configured so that the coil wiring221P of the wiring layer221is connected to external connection terminals and so that the coil wiring221P is connected to the mount board for the wiring substrate210. In the same manner, the wiring substrate310of the fourth embodiment may be configured so that the coil wiring323P of the wiring layer323is connected to external connection terminals and so that the coil wiring323P is connected the mount board for the wiring substrate310.

In the first embodiment, the coil wiring14P may be formed on the lower surface of the magnetic layer13so that the magnetic layer13is in contact with the upper surface of the coil wiring14P. For example, the coil wiring14P illustrated inFIG. 3Bis formed on the upper surface12aof the insulation layer12illustrated inFIG. 2C. The magnetic layer13is formed to cover the upper surface12aof the insulation layer12and the coil wiring14P. With such a structure, the L value of the coil is improved.

In the third and fourth embodiments, the order of the steps may be changed.

For example, in the step illustrated inFIG. 16C, the openings222X of the magnetic layer222and the openings232X of the insulation layer232are formed. Instead, after the openings222X are formed in the magnetic layer222, the insulation layer223illustrated inFIG. 17Amay be formed before the openings232X are formed in the insulation layer232. Then, after the openings232X are formed in the insulation layer232, the wiring layer233illustrated inFIG. 17Bmay be formed.