Semiconductor device assemblies and systems with one or more dies at least partially embedded in a redistribution layer (RDL) and methods for making the same

A semiconductor device assembly is provided. The assembly includes a redistribution layer (RDL) including a plurality of external contacts on a first side and a plurality of internal contacts on a second side opposite the first side. The assembly further includes a first die at least partially embedded in the RDL and having an active surface between the first side and the second side of the RDL. The assembly further includes one or more second dies disposed over the controller die and the RDL, wherein the one or more second dies electrically coupled to the internal contacts. The assembly further includes an encapsulant at least partially encapsulating the one or more second dies.

TECHNICAL FIELD

The present disclosure generally relates to semiconductor devices, and more particularly relates to semiconductor device assemblies and systems with one or more dies at least partially embedded in a redistribution layer (RDL) and methods for making the same.

BACKGROUND

Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include one or more semiconductor dies mounted on a substrate and encased in a protective covering or capped with a heat-conducting lid. In many applications, it is desirable for a semiconductor device assembly to be as thin as practicable. Accordingly, thinner semiconductor device assembly designs and methods for making the same are desired.

DETAILED DESCRIPTION

Semiconductor device assemblies are incorporated in many products where package height is a concern, such as mobile phones, tablets, laptop computers and the like. Designing a thinner assembly can be a particular challenge when the various devices in the assembly vary widely in size. For example, a memory controller die may be so much smaller than a memory die disposed thereon that spacers are required to support the peripheries of the larger die over the smaller die, adding thickness, cost, and complexity to the assembly design.

To address these challenges, embodiments of the present technology provide semiconductor device assemblies with a redistribution layer (RDL) in which a die is embedded, and on which are provided one or more additional dies. The embedded die and the one or more additional dies can be electrically coupled to each other and/or to external contacts of the assembly by one or more vias and traces formed in the RDL. By embedding a die (e.g., a controller die) in the RDL, the assembly thickness can be greatly reduced, and manufacturing can be performed more easily (e.g., at a panel, wafer, or strip level, and without the need for spacers or thick organic substrates).

In this regard,FIGS.1A-1Iillustrate simplified schematic cross-sectional views of a semiconductor device assembly100at various stages of manufacture in accordance with various embodiments of the present technology. As can be seen with reference toFIG.1A, a die (e.g., a memory controller die)120is disposed on a temporary carrier wafer103. The die120has an active surface120band a back surface120a, and in the present embodiment the back surface120ais attached (e.g., with a temporary adhesive) to the temporary carrier wafer103. Turning toFIG.1B, a layer of dielectric material (e.g. photosensitive polyimide (PSPI))111is formed over the carrier wafer103and around the die120. The dielectric material111is then patterned, as shown inFIG.1C, and a conductive material is plated into the patterned dielectric material111, as shown inFIG.1D, to form a variety of conductive features, such as internal contact112, via113, and trace114. These conductive features can provide electrical connections (e.g., power, ground, and signals) to the embedded die120, the internal contact112, and/or external contacts (illustrated in greater detail below).

This process of disposing and patterning a dielectric material and plating conductive features is iterated until RDL110is complete, as shown inFIG.1E, with a height defined between a first side110aon which are provided a plurality of external contacts and a second side110bon which are provided the plurality of internal contacts. In accordance with one aspect of the present technology, the height of RDL110can be less than 100 μm, or less than 75 μm, or even less than 50 μm, depending upon the thickness of the embedded die120and the thickness of each iteratively formed layer of conductive features.

With RDL110complete, a second carrier wafer104is attached (e.g., with a temporary adhesive) to the first side of the RDL110a, as shown inFIG.1F, and the assembly100is flipped so that the first temporary carrier wafer103can be removed, exposing the back side120aof the embedded die120and the first side of the RDL110a, as shown inFIG.1G.

Turning toFIG.1H, one or more dies (e.g., memory dies such as DRAM and/or NAND dies)130a-130dcan be disposed over the RDL110and embedded die120(e.g., using die attach film or a similar adhesive), and can be electrically connected to the RDL110by forming wirebonds132between contact pads131on each of the dies and the internal contacts112on the first side110aof the RDL110, as shown inFIG.1H. An encapsulant material140can then be formed around the one or more dies130a-130dand wirebonds132to provide structural integrity and environmental sealing therefor. The second carrier wafer104can then be removed, and a plurality of solder balls115can be formed on the corresponding plurality of external contacts on the second side110bof the RDL110.

In accordance with one aspect of the present technology, some or all of the foregoing steps can be performed at a wafer, panel, or strip level, to facilitate volume manufacturing. At this stage, or optionally earlier, the assembly100can be singulated (e.g., by sawing, plasma dicing, lasing, etc.) from the wafer, panel, or strip in which it was formed, separating it from other concurrently-formed assemblies. The finished assembly100enjoys a number of advantages over conventional assemblies, in that the embedded die120reduces the overall package thickness, and obviates the need for spacers to support one or more larger dies (e.g., dies with a larger plan area) thereupon. Moreover, the foregoing process has no need expensive underfill materials, and enjoys a lower thermal budget (e.g., due to the plating of the conductive features in the RDL110) than other methods of manufacture.

Although in the foregoing example, a semiconductor device assembly has been illustrated and described with a die partially embedded within an RDL (e.g., with one surface of the die exposed flush with a surface of the RDL), in another embodiment of the present technology one or more dies can be completely embedded within (e.g., surrounded on all sides by) an RDL as set forth in greater detail below.

In this regard,FIGS.2A-2Iillustrate simplified schematic cross-sectional views of a semiconductor device assembly200at various stages of manufacture in accordance with various embodiments of the present technology. As can be seen with reference toFIG.2A, a layer of dielectric material (e.g. photosensitive polyimide (PSPI))211is formed over a carrier wafer204, and then (optionally iteratively) patterned and plated to form part of an RDL, as shown inFIG.2B. Subsequently, a die (e.g., a memory controller die)220is disposed over the partially-fabricated RDL, as shown inFIG.2C. The die220has an active surface220band a back surface220a, and in the present embodiment the back surface220ais disposed face-down over the partially-fabricated RDL (e.g., with the back side facing what will be to the external contacts of the assembly200). Turning toFIG.2D, a further layer of dielectric material (e.g. photosensitive polyimide (PSPI))211is formed over the partially-fabricated RDL, continuing its fabrication, and around the die220. The dielectric material211is again patterned, as shown inFIG.2E, and a conductive material is again plated into the patterned dielectric material211, as shown inFIG.2F, to form a variety of conductive features, such as via213, and trace214. These conductive features can provide electrical connections (e.g., power, ground, and signals) to the embedded die220, the internal contacts (described in greater detail below) of the RDL, and/or the external contacts (illustrated in greater detail below) of the RDL.

This process of disposing and patterning a dielectric material and plating conductive features can be iterated until RDL210is complete, as shown inFIG.2G, with a height defined between a first side210aon which are provided a plurality of internal contacts212and a second side210bon which are provided the plurality of external contacts. In accordance with one aspect of the present technology, the height of RDL210can be less than 100 μm, or less than 75 μm, or even less than 50 μm, depending upon the thickness of the embedded die220and the thickness of each iteratively formed layer of conductive features.

With RDL210complete, one or more dies (e.g., memory dies such as DRAM and/or NAND dies)230a-230dcan be disposed over the RDL210(e.g., using die attach film or a similar adhesive), and can be electrically connected to the RDL210by forming wirebonds232between contact pads231on each of the dies and the internal contacts212on the first side210athe RDL210, as shown inFIG.2H. An encapsulant material240can then be formed around the one or more dies230a-230dand wirebonds232to provide structural integrity and environmental sealing therefor. The carrier wafer204can then be removed, and a plurality of solder balls215can be formed on the corresponding plurality of external contacts on the second side210bof the RDL210.

In accordance with one aspect of the present technology, some or all of the foregoing steps can be performed at a wafer, panel, or strip level, to facilitate volume manufacturing. At this stage, or optionally earlier, the assembly200can be singulated (e.g., by sawing, plasma dicing, lasing, etc.) from the wafer, panel, or strip in which it was formed, separating it from other concurrently-formed assemblies. The finished assembly200enjoys a number of advantages over conventional assemblies, in that the embedded die220reduces the overall package thickness, and obviates the need for spacers to support one or more larger dies (e.g., dies with a larger plan area) thereupon. Moreover, the foregoing process has no need expensive underfill materials, and enjoys a lower thermal budget (e.g., due to the plating of the conductive features in the RDL210) than other methods of manufacture.

Although in the foregoing examples, semiconductor device assemblies have been described and illustrated as including a plurality of memory die arranged in shingled stacks and connected to an RDL with wirebonds, in other embodiments of the present technology other arrangements of dies can similarly benefit from a design incorporating an RDL with an embedded die. For example, in addition to or in place of dies arranged in a shingled stack and connected by wirebonds, dies can be provided in vertical stacks and connected with other connection methodologies, such as TSVS, solder interconnects, copper-copper connections, hybrid bonding, etc. In some embodiments, rather than a plurality of dies, a semiconductor device assembly may include only a single die over an RDL in which another die is embedded (e.g., attached via direct chip attach (DCA)). Those of skill in the art will appreciate that the foregoing list of examples is not exhaustive, but rather that many other semiconductor device assemblies can be similarly configured with an RDL in which is at least partially embedded one or more die, mutatis mutandis.

Although in the foregoing examples, semiconductor device assemblies have been described and illustrated as including an RDL having a single embedded die, in other embodiments of the present technology multiple dies can be embedded within an RDL of a semiconductor device assembly in a manner similar to those described above. The foregoing approaches to partially embedding and completely embedding a die can be combined, in some embodiments, to provide embedded dies at different heights within an RDL. Alternatively, due to the iterative nature of dielectric disposition, patterning, and plating conductive features, multiple dies can be embedded with overlapping or vertically-aligned positions.

Moreover, although the embedded dies in the above-described examples have been identified as controller dies (e.g., for a managed NAND (mNAND) device), and the one or more dies in a stack have been identified as memory dies (e.g., NAND or DRAM, or combinations thereof), those of skill in the art will readily appreciate that the foregoing assembly topologies can be adapted to other die types. For example, in addition to or in place of memory dies, other kinds of semiconductor devices can be provided in a semiconductor device assembly, such as logic dies, application-specific integrated circuit (ASIC) dies, field-programmable gate array (FPGA) dies, etc. In place of an embedded controller die, other die types can be embedded in an RDL (e.g., memory dies, other logic dies, ASIC dies, FPGA dies, etc.).

FIG.3is a flow chart illustrating a method of making a semiconductor device assembly. The method includes disposing a first die over a first carrier wafer (box310), forming a redistribution layer (RDL) around and over the first die (box320), and attaching a second carrier wafer to the first side of the RDL (box330). The method further includes removing the first carrier wafer to expose the first die and the second side of the RDL (box340), attaching one or more second dies to the second side of the RDL (box350), and encapsulating the one or more second dies (box360). The method further includes singulating the semiconductor device package from a panel, wafer, or strip (box370) and attaching a corresponding plurality of solder balls to the plurality of external contacts (box380).

FIG.4is a flow chart illustrating a method of making a semiconductor device assembly. The method includes disposing a first die over a carrier wafer (box410), forming a redistribution layer (RDL) around and over the first die (box420), and attaching one or more second dies to the second side of the RDL (box430). The method further includes encapsulating the one or more second dies (box440), singulating the semiconductor device package from a panel, wafer, or strip (box450), and attaching a corresponding plurality of solder balls to the plurality of external contacts (box460).

Any one of the die support structures and/or semiconductor device assemblies described above with reference toFIGS.1A through4can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system500shown schematically inFIG.5. The system500can include a semiconductor device assembly510, a power source520, a driver530, a processor540, and/or other subsystems or components550. The semiconductor device assembly510can include features generally similar to those of the semiconductor device assemblies described above. The resulting system500can perform any of a wide variety of functions such as memory storage, data processing, and/or other suitable functions. Accordingly, representative systems500can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicle and other machines and appliances. Components of the system500may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system500can also include remote devices and any of a wide variety of computer readable media.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the disclosure and appended claims. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

It should be noted that the methods described above describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, embodiments from two or more of the methods may be combined.