Integrated circuit package system with leads having multiple sides exposed

An integrated circuit package system includes forming an integrated circuit stack having a bottom non-active side and a top non-active side; connecting an internal interconnect between a lead, having a top side and a bottom side, and the integrated circuit stack; and forming an encapsulation, having both a non-elevated portion and an elevated portion, around the integrated circuit stack and the internal interconnect with the top side exposed at the non-elevated portion, and with the bottom side, the bottom non-active side, and the top non-active side exposed.

TECHNICAL FIELD

The present invention relates generally to integrated circuit package systems, and more particularly to a system for integrated circuit package systems having stacked packages.

BACKGROUND ART

To interface an integrated circuit with other circuitry, it is common to mount it on a lead frame or substrate. Each integrated circuit has bonding pads that are individually connected to the lead frame's lead finger pads using extremely fine gold or aluminum wires. The assemblies are then packaged by individually encapsulating them in molded plastic or ceramic bodies to create an integrated circuit package.

Integrated circuit packaging technology has seen an increase in the number of integrated circuits mounted on a single circuit board or substrate. The new packaging designs are more compact in form factors, such as the physical size and shape of an integrated circuit, and providing a significant increase in overall integrated circuit density.

However, integrated circuit density continues to be limited by the “real estate” available for mounting individual integrated circuits on a substrate. Even larger form factor systems, such as PC's, compute servers, and storage servers, need more integrated circuits in the same or smaller “real estate”. Particularly acute, the needs for portable personal electronics, such as cell phones, digital cameras, music players, PDA's, and location-based devices, have further driven the need for integrated circuit density.

This need for increased integrated circuit density, has led to the development of multi-chip packages in which more than one integrated circuit can be packaged. Each package provides mechanical support for the individual integrated circuits and one or more layers of interconnect lines that enable the integrated circuits to be connected electrically to surrounding circuitry.

Current multi-chip packages, also commonly referred to as multi-chip modules, typically consist of one or more substrates onto each of which one or more integrated circuit components is directly attached. Such multi-chip packages have been found to increase integrated circuit density and miniaturization, improve signal propagation speed, reduce overall integrated circuit size and weight, improve performance, and lower costs—all primary goals of the computer industry.

There is always a limitation on the number of die that can be stacked in a package, especially for big memory dice. Same die stacking with all bond pads at one side allows stacking in the staircase manner that eliminates the need for thick spacers between the dice. However, stacking is still restricted by the package size where over-stacking cause die protrusion requiring extra long packages.

Thus, a need still remains for improved packaging methods, systems, and designs. In view of the shrinking size of consumer electronics and the demand for more sophisticated functions in the restricted space, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, increasing consumer expectations, and diminishing opportunities for meaningful product differentiation in the marketplace, it is increasingly critical that answers be found to these problems. Moreover, the ever-increasing need to save costs, improve efficiencies, and meet such competitive pressures adds even greater urgency to the critical necessity that answers be found to these problems.

Disclosure of the Invention

The present invention provides an integrated circuit package system that includes forming an integrated circuit stack having a bottom non-active side and a top non-active side; connecting an internal interconnect between a lead, having a top side and a bottom side, and the integrated circuit stack; and forming an encapsulation, having both an non-elevated portion and an elevated portion, around the integrated circuit stack and the internal interconnect with the top side exposed at the non-elevated portion, and with the bottom side, the bottom non-active side, and the top non-active side exposed.

BEST MODES FOR CARRYING OUT THE INVENTION

Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs. Generally, the invention can be operated in any orientation. The terms first, second, and third embodiments are used merely as a convenience and do not have any other significance.

For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the package substrate, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements. The term “system” means the method and the apparatus of the present invention, as appropriate and as evident from context. The term “processing” as used herein includes stamping, forging, patterning, exposure, development, etching, cleaning, and/or removal of the material or laser trimming as required in forming a described structure.

Referring now toFIG. 1, therein is shown a top view of an integrated circuit package system100in a first embodiment of the present invention. The top view depicts a top integrated circuit die102exposed by an encapsulation104, such as a cover of an epoxy molding compound. The top integrated circuit die102is shown not centered relative to the integrated circuit package system100, as an example. The encapsulation104includes a non-elevated portion106and an elevated portion108. The non-elevated portion106exposed a top side110of leads112. The top side110of the leads112does not extend to the edge of the encapsulation104, as an example.

For illustrative purposes, the integrated circuit package system100is shown with the leads112at opposite sides, although it is understood that the integrated circuit package system100can have the leads112in different configurations. For example, the leads112may be along all the sides, some of the sides, or one side of the integrated circuit package system100. As another example, the integrated circuit package system100may have multiple rows of the leads112.

Referring now toFIG. 2, therein is shown a bottom view of the integrated circuit package system100ofFIG. 1. The bottom view depicts a bottom integrated circuit die214exposed by the encapsulation104. The bottom integrated circuit die214is shown not centered relative to the integrated circuit package system100, as an example. The encapsulation104exposes a bottom side216of the leads112. The bottom side216of the leads112extends to the edge of the encapsulation104, as an example.

Referring now toFIG. 3, therein is shown a cross-sectional view of the integrated circuit package system100along3-3ofFIG. 1. The cross-sectional view depicts a bottom non-active side318of the bottom integrated circuit die214substantially coplanar with the bottom side216of the leads112and a bottom surface320of the encapsulation104. A top surface322of the encapsulation104includes the non-elevated portion106and the elevated portion108. The leads112include a protrusion324having the top side110exposed at the non-elevated portion106of the encapsulation104. Sides326of the protrusion324are surrounded by the encapsulation104allowing the leads112to function as a mold interlock thereby improving reliability, such as in moisture sensitivity level (MSL) performance.

A first integrated circuit die328can be over the bottom integrated circuit die214in an offset configuration. An adhesive330, such as a die-attach adhesive, is between the bottom integrated circuit die214and the first integrated circuit die328. A second integrated circuit die332can be over the first integrated circuit die328in an offset configuration in a similar direction to the bottom integrated circuit die214. A third integrated circuit die334can be over the second integrated circuit die332in an offset configuration in a similar direction to the first integrated circuit die328. The top integrated circuit die102can be over the third integrated circuit die334.

The adhesive330is also between the first integrated circuit die328and the second integrated circuit die332, the second integrated circuit die332and the third integrated circuit die334, and the third integrated circuit die334and the top integrated circuit die102. Internal interconnects336, such as bond wires or ribbon bond wires, connect the bottom integrated circuit die214, the first integrated circuit die328, the second integrated circuit die332, and the third integrated circuit die334with the leads112.

The encapsulation104covers an integrated circuit stack338of the bottom integrated circuit die214, the first integrated circuit die328, the second integrated circuit die332, the third integrated circuit die334, and the top integrated circuit die102with the bottom non-active side318and a top non-active side340of the top integrated circuit die102exposed. The encapsulation104also covers the internal interconnects336and the leads112with the top side110and the bottom side216exposed. The elevated portion108of the encapsulation104is above the height of the protrusion324of the leads112.

The integrated circuit stack338can serve to provide mechanical rigidity for the integrated circuit package system100. The offset configuration of the integrated circuit stack338may also function as a mold interlock for the integrated circuit package system100.

For illustrative purposes, the integrated circuit stack338includes an offset configuration of the integrated circuit dice such that the integrated circuit dice or the adhesive330do not interfere with the connections of the internal interconnects336, although it is understood that the bottom integrated circuit die214, the first integrated circuit die328, the integrated circuit stack338may be stacked differently. For example, the integrated circuit stack338can include a spacer, such as a wire-in-film, as the adhesive330within the integrated circuit stack338allowing the internal interconnects336to connect to one or more of the integrated circuit dice within the spacer.

Also for illustrative purposes, the integrated circuit package system100is shown with the top integrated circuit die102, although it is understood that the integrated circuit package system100can have a different structure. For example, the top integrated circuit die102can represent a dummy semiconductor structure that is not an integrated circuit for providing clearance of the internal interconnects336attached with the third integrated circuit die334and for providing structural support to resist warpage.

Referring now toFIG. 4, therein is shown a top view of an integrated circuit package system400in a second embodiment of the present invention. The top view depicts a top integrated circuit die402exposed by an encapsulation404, such as a cover of an epoxy molding compound. The top integrated circuit die402is shown not centered relative to the integrated circuit package system400, as an example. The encapsulation404includes a non-elevated portion406and an elevated portion408. The non-elevated portion406exposed a top side410of leads412. The leads412extend to the edge of the encapsulation404, as an example.

For illustrative purposes, the integrated circuit package system400is shown with the leads412at opposite sides, although it is understood that the integrated circuit package system400can have the leads412in different configurations. For example, the leads412may be along all the sides, some of the sides, or one side of the integrated circuit package system400. As another example, the integrated circuit package system400may have multiple rows of the leads412.

Referring now toFIG. 5, therein is shown a bottom view of the integrated circuit package system400ofFIG. 4. The bottom view depicts a bottom integrated circuit die514exposed by the encapsulation404. The bottom integrated circuit die514is shown not centered relative to the integrated circuit package system400, as an example. The encapsulation404exposes a bottom side516of the leads412.

Referring now toFIG. 6, therein is shown a cross-sectional view of the integrated circuit package system400along6-6ofFIG. 4. The cross-sectional view depicts a bottom non-active side518of the bottom integrated circuit die514substantially coplanar with the bottom side516of the leads412and a bottom surface520of the encapsulation404. A top surface522of the encapsulation404includes the non-elevated portion406and the elevated portion408. The top side410of the leads412is also shown as coplanar with the non-elevated portion406of the encapsulation404, as an example.

A first integrated circuit die528can be over the bottom integrated circuit die514in an offset configuration. An adhesive530, such as a die-attach adhesive, is between the bottom integrated circuit die514and the first integrated circuit die528. A second integrated circuit die532can be over the first integrated circuit die528in an offset configuration in a similar direction to the bottom integrated circuit die514. A third integrated circuit die534can be over the second integrated circuit die532in an offset configuration in a similar direction to the first integrated circuit die528. The top integrated circuit die402can be over the third integrated circuit die534.

The adhesive530is also between the first integrated circuit die528and the second integrated circuit die532, the second integrated circuit die532and the third integrated circuit die534, and the third integrated circuit die534and the top integrated circuit die402. Internal interconnects536, such as bond wires or ribbon bond wires, connect the bottom integrated circuit die514, the first integrated circuit die528, the second integrated circuit die532, and the third integrated circuit die534with the leads412.

The encapsulation404covers an integrated circuit stack538, wherein the integrated circuit stack538includes the bottom integrated circuit die514, the first integrated circuit die528, the second integrated circuit die532, the third integrated circuit die534, and the top integrated circuit die402with the bottom non-active side518and a top non-active side540of the top integrated circuit die402exposed. The encapsulation404also covers the internal interconnects536and the leads412with the top side410and the bottom side516exposed. The height of the elevated portion408of the encapsulation404is above the height of a protrusion524of the leads412.

The integrated circuit stack538can serve to provide mechanical rigidity for the integrated circuit package system400. The offset configuration of the integrated circuit stack538may also function as a mold interlock for the integrated circuit package system400.

For illustrative purposes, the integrated circuit stack538includes an offset configuration of the integrated circuit dice such that the integrated circuit dice or the adhesive530do not interfere with the connections of the internal interconnects536, although it is understood that the bottom integrated circuit die514, the first integrated circuit die528, the integrated circuit stack538may be stacked differently. For example, the integrated circuit stack538can include a spacer, such as a wire-in-film, as the adhesive530within the integrated circuit stack538allowing the internal interconnects536to connect to one or more of the integrated circuit dice within the spacer.

Referring now toFIG. 7, therein is shown a cross-sectional view of an integrated circuit package system700in a third embodiment of the present invention. The integrated circuit package system700is an integrated circuit package-in-package system with a stack having the integrated circuit package system100mounted over a carrier742, such as a substrate.

The elevated portion108of the encapsulation104functions as a spacer allowing package interconnects744, such as bond wires or ribbon bond wires, to connect to the top side110of the leads112and the carrier742. This eliminates the need for separate or discrete spacer structures thereby reducing manufacturing complexity, reducing the package profile, and lowering cost.

A package encapsulation746, such as a cover of an epoxy molding compound, covers the stack of the integrated circuit package system100and the package interconnects744over the carrier742. External interconnects748, such as solder balls, can attach to the bottom of the carrier742for connection to the next system level (not shown), such as a printed circuit board or another integrated circuit package system.

For illustrative purposes, the integrated circuit package system100adjacent to the carrier742is shown connected to the carrier742with the package interconnects744, although it is understood that the integrated circuit package system100may be connected to the carrier742differently. For example, conductive paste (not shown), such as solder paste, may be used to connect the bottom side216of the leads112and the carrier742or in combination with the package interconnects744.

Referring now toFIG. 8, therein is shown a cross-sectional view of an integrated circuit package system800in a fourth embodiment of the present invention. The integrated circuit package system800is an integrated circuit package-in-package system with a stack having the integrated circuit package system400mounted over a carrier842, such as a substrate.

The elevated portion408of the encapsulation404functions as a spacer allowing package interconnects844, such as bond wires or ribbon bond wires, to connect to the top side410of the leads412and the carrier842. This eliminates the need for separate or discrete spacer structures thereby reducing manufacturing complexity, reducing the package profile, and lowering cost.

A package encapsulation846, such as a cover of an epoxy molding compound, covers the stack of the integrated circuit package system400and the package interconnects844over the carrier842. External interconnects848, such as solder balls, can attach to the bottom of the carrier842for connection to the next system level (not shown), such as a printed circuit board or another integrated circuit package system.

For illustrative purposes, the lower of the integrated circuit package system400is shown connected to the carrier842with the package interconnects844, although it is understood that the integrated circuit package system400may be connected to the carrier842differently. For example, conductive paste (not shown), such as solder paste, may be used to connect the bottom side516of the leads412and the carrier842or in combination with the package interconnects844.

Referring now toFIG. 9, therein is shown a cross-sectional view of a portion of a lead frame902in a die attaching step of a portion the integrated circuit stack338ofFIG. 3. The cross-sectional view depicts the leads112as part of the lead frame902and attached with a mounting structure904, such as a coverlay tape.

A portion of the integrated circuit stack338can be formed between the leads112with the bottom non-active side318of the bottom integrated circuit die214attached with the mounting structure904. The first integrated circuit die328mounts over the bottom integrated circuit die214in an offset configuration.

Referring now toFIG. 10, therein is shown the structure ofFIG. 9in a connecting step of the internal interconnects336. The internal interconnects336attach between the leads112and the bottom integrated circuit die214. The internal interconnects336also attach between the leads112and the first integrated circuit die328.

The second integrated circuit die332mounts over the first integrated circuit die328in an offset configuration in a similar direction to the bottom integrated circuit die214. The third integrated circuit die334mounts over the second integrated circuit die332in an offset configuration in a similar direction to the first integrated circuit die328. The top integrated circuit die102mounts over the third integrated circuit die334. The adhesive330is between the integrated circuit dice in the integrated circuit stack338. The top non-active side340of the top integrated circuit die102faces away from the mounting structure904.

The internal interconnects336continue to attach between the leads112and both the second integrated circuit die332and the third integrated circuit die334in the integrated circuit stack338. The offset configuration of the integrated circuit dice in the integrated circuit stack338provides clearance for the connection of the internal interconnects336with the integrated circuit stack338.

Referring now toFIG. 11, therein is shown the structure ofFIG. 10in a forming step of the encapsulation104. The cross-sectional view depicts portions of adjacent structures ofFIG. 10with the leads112still attached to each other from the adjacent structures in the lead frame902. The encapsulation104is formed surrounding the internal interconnects336and the integrated circuit stack338in each of the adjacent structures. The top non-active side340and the bottom non-active side318are exposed from the encapsulation104. The encapsulation104also exposes the top side110and the bottom side216of the leads112.

The mounting structure904ofFIG. 9is removed from the encapsulated structure. The encapsulated structure can undergo post molding cure. The encapsulated structure can optionally be plated, such as with copper alloy, nickel/palladium, or gold alloy, and can undergo device marking.

Referring now toFIG. 12, therein is shown the structure ofFIG. 11in a singulating step of the integrated circuit package system100ofFIG. 3. A singulation element1202, such as a saw, may cut the leads112that are attached without cutting the protrusion324forming the integrated circuit package system100.

Referring now toFIG. 13, therein is shown a flow chart of an integrated circuit package system1300for manufacturing of the integrated circuit package system100in an embodiment of the present invention. The system1300includes forming an integrated circuit stack having a bottom non-active side and a top non-active side in a block1302; connecting an internal interconnect between a lead, having a top side and a bottom side, and the integrated circuit stack in a block1304; and forming an encapsulation, having both an non-elevated portion and an elevated portion, around the integrated circuit stack and the internal interconnect with the top side exposed at the non-elevated portion, and with the bottom side, the bottom non-active side, and the top non-active side exposed in a block1306.

Thus, it has been discovered that the integrated circuit package-on-package stacking system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for developing and manufacturing package-on-package stacked solutions. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, and effective, can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing package-on-package stacked devices fully compatible with conventional manufacturing processes and technologies. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.