Stack capacitor structure and method for forming the same

The stack capacitor structure includes a substrate, first, second, third, and fourth support layers, first, second, and third insulating layers, first, second, and third holes, and a capacitor. The first support layer is disposed over the substrate. The first insulating layer is disposed on the first support layer. The second support layer is disposed on the first insulating layer. The third support layer is disposed on the second support layer. The second insulating layer is disposed on the third support layer. The third insulating layer is disposed on the second insulating layer. The fourth support layer is disposed on the third insulating layer. The first hole penetrates through from the second support layer to the first support layer. The second and third holes penetrate through from the fourth support layer to the third support layer. The capacitor is disposed in the first, second, and third holes.

BACKGROUND

Field of Invention

The present invention relates to a stack capacitor structure and method for forming the same.

Description of Related Art

In recent years there has been a dramatic increase in the packing density of DRAMs. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capacitor. This large integration of DRAMs has been accomplished by a reduction in individual cell size. However, a decrease in storage capacitance, which results from the reduction in cell size, leads to draw backs, such as a lowering source/drain ratio and undesirable signal problems in terms of reliability. In order to achieve the desired higher level of integration, it requires the technology to keep almost the same storage capacitance on a greatly reduced cell area.

It is well known that in the art of integrated circuit device manufacture, one of the primary goals is increasing the number of device that can be placed into a given unit space on the semiconductor chip. As the traditional fabrication process begin to approach the limit of reduction, considerable attention has been applied to forming device elements on over and above the wafer to take advantage of extra versatility of third dimension.

One of the successful vertically oriented integrated circuit devices is the stacked capacitor. Briefly, a stacked capacitor is formed by forming the stacked capacitor structures laying over the gate electrode on active and field oxide regions and diffusion region. The processing of such structures have become very complicated which are not in step with the very small dimensions required in the present and future state of the art. Although there has been much work done in accomplishing these small size devices and increased capacitance therein, there is still great need for devices with even greater capacitance for a given space in order to achieve even greater packing densities, and improve the DRAM products of the future.

SUMMARY

Accordingly, it is a primary object of the invention to provide a stack capacitor structure with a greater capacitance per unit area and a method of forming the same.

According to one aspect of the present disclosure, a stack capacitor structure is provided. The stack capacitor structure includes a substrate, a first support layer, a first insulating layer, a second support layer, a third support layer, a second insulating layer, a third insulating layer, a fourth support layer, a first hole, a second hole, a third hole, and a capacitor. The first support layer is disposed over the substrate. The first insulating layer is disposed on the first support layer. The second support layer is disposed on the first insulating layer. The third support layer is disposed on the second support layer. The second insulating layer is disposed on the third support layer. The third insulating layer is disposed on the second insulating layer. The fourth support layer is disposed on the third insulating layer. The first hole penetrates through from a top surface of the second support layer to a bottom surface of the first support layer. The second hole penetrates through from the third insulating layer to a bottom surface of the third support layer, wherein the second hole communicates with the first hole. The third hole penetrates through from a top surface of the fourth support layer to the third insulating layer, wherein the third hole is aligned with the second hole. The capacitor is disposed in the first, second, and third holes.

In some embodiments of the present disclosure, the stack capacitor structure further includes a wiring layer disposed between the substrate and the first support layer.

In some embodiments of the present disclosure, the first hole penetrates through a portion of the wiring layer and the capacitor electrically connects the wiring layer.

In some embodiments of the present disclosure, a material of the first insulating layer is different from that of the second insulating layer, and the second insulating layer comprises SiO doped with boro-phospho-silicate glass (BPSG).

In some embodiments of the present disclosure, materials of the first, second and fourth support layer are the same, the material of the first support layer is different from that of the third support layer, and the third support layer comprises SiN doped with carbon.

In some embodiments of the present disclosure, the stack capacitor structure further includes a fourth insulating layer disposed between the first support layer and the first insulating layer.

In some embodiments of the present disclosure, the capacitor comprises an outer electrode, a dielectric layer and an inner electrode in direct contact with each other.

In some embodiments of the present disclosure, the stack capacitor structure further includes a conductive material in direct contacts with the inner electrode, wherein the conductive material fills up the first and second hole and extends into a portion of the third hole.

In some embodiments of the present disclosure, the stack capacitor structure further includes a source/drain (S/D) feature disposed in the third hole and surrounded by the inner electrode.

In some embodiments of the present disclosure, the stack capacitor structure further includes a transistor electrically connecting to the source/drain (S/D) feature.

According to another aspect of the present disclosure, a method of forming a stack capacitor structure is provided. The method includes the operations described below. A first support layer is firstly formed over a substrate. A first insulating layer is then formed on the first support layer. A second support layer is then formed on the first insulating layer. Subsequently, a first hole penetrates through from a top surface of the second support layer to a bottom surface of the first support layer. A third support layer is then formed on the second support layer, wherein the first hole is sealed off by the third support layer. A second insulating layer is then formed on the third support layer. A third insulating layer is then formed on the second insulating layer. A fourth support layer is then formed on the third insulating layer. Subsequently, a second hole penetrates through from third insulating layer to a bottom surface of the third support layer and a third hole penetrates through from a top surface of the fourth support layer to the third insulating layer, wherein the first hole communicates with the second hole and the third hole. Thereafter, a capacitor is formed in the first, second, and third holes.

In some embodiments of the present disclosure, the method further includes the steps described below. A wiring layer is disposed between the substrate and the first support layer, wherein the wiring layer electrically connects to the capacitor.

In some embodiments of the present disclosure, the method further includes the steps described below. A fourth insulating layer is disposed between the first support layer and the first insulating layer.

In some embodiments of the present disclosure, the operation for forming the first hole includes the following steps: (i) removing first portions of the second support layer, the first insulating layer, the fourth insulating layer, and the first support layer to form a first initial hole, wherein an upper edge of the first initial hole has a first width, a lower edge of the first initial hole has a second width, and the first width is greater than the second width; and (ii) removing second portions of the second support layer, the first insulating layer, a fourth insulating layer, and the first support layer to form the first hole, wherein an upper edge of the first hole has a third width, a lower edge of the first hole has a fourth width, and the third width is substantially equal to the fourth width.

In some embodiments of the present disclosure, the operation for forming the second hole and the third hole includes the following steps: (i) removing first portions of the fourth support layer, the third insulating layer, the second insulating layer, and the third support layer to form a second initial hole, wherein an upper edge of the second initial hole has a fifth width, a lower edge of the second initial hole has a sixth width, and the fifth width is greater than the sixth width; and (ii) removing second portions of the fourth support layer, the third insulating layer, a second insulating layer, and the third support layer to form the second hole, wherein an upper edge of the second hole has a seventh width, a lower edge of the second hole has an eighth width, and the seventh width is substantially equal to the eighth width.

In some embodiments of the present disclosure, the operation for forming the capacitor includes the following steps: (i) forming an outer electrode conformally along walls of the first and second hole; (ii) forming a dielectric layer conformally on the outer electrode and a sidewall of the third hole; and (iii) forming an inner electrode conformally on the dielectric layer.

In some embodiments of the present disclosure, the method further includes the operations described below. A conductive material is formed in direct contacting with the inner electrode, wherein the conductive material fills up the first and second hole and extends into a portion of the third hole.

In some embodiments of the present disclosure, the method further includes the operations described below. A source/drain (S/D) feature is formed in the third hole, wherein the source/drain (S/D) feature is disposed on the conductive material and surrounded by the inner electrode.

In some embodiments of the present disclosure, a material of the first insulating layer is different from that of the second insulating layer, and the second insulating layer comprises SiO doped with boro-phospho-silicate glass (BPSG).

In some embodiments of the present disclosure, materials of the first, second and fourth support layer are the same, the material of the first support layer is different from that of the third support layer, and the third support layer comprises SiN doped with carbon.

DETAILED DESCRIPTION

In order to increase the capacitance of the capacitor and achieve even greater packing densities, the present disclose provides stack capacitor structures20a,20bas shown inFIGS. 9-10. In addition, the method for forming these stack capacitor structures20a,20bis also novel.

Please refer toFIG. 1.FIG. 1is a flow chart of a method10of forming a stack capacitor structure according to some embodiments of the present disclosure. The method10of forming the stack capacitor structure includes operation110, operation120, operation130, operation140, operation150, operation160, operation170, operation180, operation190, and operation1100.

In operation110, a first support layer220is formed over a substrate210. According to some embodiments, operation110may be further understood with reference toFIG. 2, which is cross-sectional view illustrating one of various process stages of forming the stack capacitor structure. In some embodiments, the substrate210may be a printed circuit board (PCB), a semiconductor substrate or other substrates known in the art. Illustrative examples of the materials of the PCB include glass fiber, epoxy resins, phenolic resins, polyimide (PI), and other suitable material, for example. Illustrative examples of the materials of the semiconductor substrate include silicon, bulk silicon, polysilicon or silicon on insulator (SOI), and a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The semiconductor substrate may include various doping configurations, depending on the requirements known in the art (e.g., p-type substrate or n-type substrate). In one embodiment, the first support layer220includes silicon nitride (SiN). In some embodiments, the first support layer220may be formed over the substrate210by using a chemical vapor deposition (CVD) process, atomic layer deposition (ALD), physical vapor deposition (PVD), molecular-beam deposition (MBD), and other suitable processes known in the art.

In other embodiments, a wiring layer211may be formed between the substrate210and the first support layer220. In some embodiment, the material of the wiring layer211may be a metal, for example, tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), cobalt (Co), titanium (Ti), or other suitable metal materials. The wiring layer211is used to electrically connect the subsequent capacitors. The wiring layer211may be formed on the substrate210by sputtering, evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular-beam deposition (MBD), atomic layer deposition (ALD), or other suitable processes.

The method10continues to operation120, a first insulating layer230is formed on the first support layer220. According to some embodiments, operation120may be further understood with reference toFIG. 2, which is cross-sectional view illustrating one of various process stages of forming the stack capacitor structure. In one embodiment, the first insulating layer230includes silicon oxide (SiO). In some embodiments, the first insulating layer230may be formed over the first support layer220by using a chemical vapor deposition (CVD) process, atomic layer deposition (ALD), physical vapor deposition (PVD), molecular-beam deposition (MBD), and other suitable processes known in the art.

In other embodiments, a fourth insulating layer221may be selectively formed between the first support layer220and the first insulating layer230. It is noted that the material of the fourth insulating layer221is different from that of the first insulating layer230. To be specific, the fourth insulating layer221includes SiO doped with boro-phospho-silicate glass (BPSG). In some embodiments, the fourth insulating layer221may be formed on the first support layer220by using a chemical vapor deposition (CVD) process, atomic layer deposition (ALD), physical vapor deposition (PVD), molecular-beam deposition (MBD), and other suitable processes known in the art.

The method10continues to operation130, a second support layer240is formed on the first insulating layer230. According to some embodiments, operation130may be further understood with reference toFIG. 2, which is a cross-sectional view illustrating one of various process stages of forming the stack capacitor structure. In one embodiment, the second support layer240is a silicon nitride layer. In other words, the material of the second support layer240is the same as that of the first support layer220. In some embodiments, the second support layer240may be formed over the first insulating layer230by using a chemical vapor deposition (CVD) process, atomic layer deposition (ALD), physical vapor deposition (PVD), molecular-beam deposition (MBD), and other suitable processes known in the art.

The method10continues to operation140, a first hole250penetrates through from a top surface of the second support layer240to a bottom surface of the first support layer220. According to some embodiments, operation140may be further understood with reference toFIGS. 3-4, which are cross-sectional view illustrating various process stages of forming the stack capacitor structure. It should be understand that the number of the first hole250is not limited to three as shown inFIG. 4. For example, the number of the first hole250may be four, five, six, or the number according to design requirements. In some embodiments, the formation of the first hole250includes the steps described below. Please refer toFIG. 3, the first portions of the second support layer240, the first insulating layer230, the fourth insulating layer221, and the first support layer220are removed to form a first initial hole250′. In some embodiments, the first initial hole250′ may be formed by appropriate processes such as a photolithography-etching process, a machine drilling process and a laser drilling process. It should be understand that an upper edge of the first initial hole250′ has a first width W1, a lower edge of the first initial hole250′ has a second width W2, and the first width W1is greater than the second width W2. In other words, the horizontal (direction of parallel to the surface of the second support layer240) distances between two sidewalls of the first initial hole250′ at different heights (direction of normal of the surface of the second support layer240) are about linearly and monotonically decrease from top to bottom. In the embodiment of including the wiring layer, the first initial hole250′ extends into the wiring layer211, but do not penetrate through the wiring layer211.

Please refer toFIG. 4, the second portions of the second support layer240, the first insulating layer230, a fourth insulating layer221, and the first support layer220are removed to form the first hole250. In some embodiments, the first hole250may be formed by an etching process with high selection ratio. It is worth mentioning that comparing to the first insulating layer230; the fourth insulating layer221has low quality because of doping boro-phospho-silicate glass (BPSG), so that the second portion of the fourth insulating layer221may easily be removed by the etching process with high selection ratio, thereby increasing the width of the first hole250in the fourth insulating layer221. The removed second portion of the fourth insulating layer221is greater than the removed second portions of the second support layer240and the first insulating layer230. Therefore, an upper edge of the first hole250has a third width W3, a lower edge of the first hole250has a fourth width W4, and the third width W3is substantially equal to the fourth width W4. In the embodiment of including the wiring layer, the first hole250extends into the wiring layer211, but do not penetrate through the wiring layer211.

The method10continues to operation150, a third support layer260is formed on the second support layer240. According to some embodiments, operation150may be further understood with reference toFIG. 5, which is a cross-sectional view illustrating various process stages of forming the stack capacitor structure. It is noted that the first hole250is sealed off by the third support layer260. In various embodiments, the material of the third support layer260is different from that of the second support layer240. Specifically, third support layer260includes SiN doped with carbon. In some embodiments, third support layer260may be formed on the second support layer240by using a chemical vapor deposition (CVD) process, atomic layer deposition (ALD), physical vapor deposition (PVD), molecular-beam deposition (MBD), and other suitable processes known in the art. It is worth mentioning that the third support layer260with SiN doped with carbon has stronger mechanical properties, therefore the first hole250may be rapidly sealed off by the third support layer260, thereby preventing the subsequent layers filling into the hole.

The method10continues to operation160, a second insulating layer270is formed on the third support layer260. According to some embodiments, operation160may be further understood with reference toFIG. 6, which is a cross-sectional view illustrating one of various process stages of forming the stack capacitor structure. In some embodiments, the material of the second insulating layer270is the same as that of the fourth insulating layer221but is different from that of the first insulating layer230. Specifically, the second insulating layer270includes SiO doped with boro-phospho-silicate glass (BPSG). In some embodiments, the second insulating layer270may be formed on the third support layer260by using a chemical vapor deposition (CVD) process, atomic layer deposition (ALD), physical vapor deposition (PVD), molecular-beam deposition (MBD), and other suitable processes known in the art.

The method10continues to operation170, a third insulating layer280is formed on the second insulating layer270. According to some embodiments, operation170may be further understood with reference toFIG. 6, which is cross-sectional view illustrating one of various process stages of forming the stack capacitor structure. In some embodiments, the material of the third insulating layer280is the same as that of the first insulating layer230. Specifically, the third insulating layer280includes silicon oxide (SiO). In some embodiments, the third insulating layer280may be formed over the second insulating layer270by using a chemical vapor deposition (CVD) process, atomic layer deposition (ALD), physical vapor deposition (PVD), molecular-beam deposition (MBD), and other suitable processes known in the art.

The method10continues to operation180, a fourth support layer290is formed on the third insulating layer280. According to some embodiments, operation180may be further understood with reference toFIG. 6, which is a cross-sectional view illustrating one of various process stages of forming the stack capacitor structure. In some embodiments, the material of the fourth support layer290is the same as that of the first support layer220and the second support layer240. Specifically, the fourth support layer290includes silicon nitride (SiN). In some embodiments, the fourth support layer290may be formed over the substrate210by using a chemical vapor deposition (CVD) process, atomic layer deposition (ALD), physical vapor deposition (PVD), molecular-beam deposition (MBD), and other suitable processes known in the art.

The method10continues to operation190, a second hole310penetrates through from the third insulating layer280to a bottom surface of the third support layer260and a third hole320penetrates through from a top surface of the fourth support layer290to the third insulating layer280. According to some embodiments, operation190may be further understood with reference toFIGS. 7-8, which are cross-sectional view illustrating various process stages of forming the stack capacitor structure. It should be understand that the number of the second hole310is not limited to three as shown inFIG. 8. For example, the number of the second hole310may be four, five, six, or the number according to design requirements. In some embodiments, the formation of the second hole310includes the steps described below. Please refer toFIG. 7, the first portions of the fourth support layer290, the third insulating layer280, the second insulating layer270, and the third support layer260are removed to form a second initial hole310′. In some embodiments, the second initial hole310′ may be formed by appropriate processes such as a photolithography-etching process, a machine drilling process and a laser drilling process. It should be understand that an upper edge of the second initial hole310′ has a fifth width W5, a lower edge of the second initial hole310′ has a sixth width W6, and the fifth width W5is greater than the sixth width W6. In other words, the horizontal (direction of parallel to the surface of the fourth support layer290) distances between two sidewalls of the second initial hole310′ at different heights (direction of normal of the surface of the fourth support layer290) are about linearly and monotonically decrease from top to bottom.

Please refer toFIG. 8, the second portions of the fourth support layer290, the third insulating layer280, the second insulating layer270, and the third support layer260are removed to form the second hole310and the third hole320. It can be understand that the second hole310and the third hole320are formed simultaneously, and the third hole320is on the second hole310and communicate with each other. Because of forming simultaneously, the third hole320is aligned with the second hole310. In various embodiments, the second hole310and the third hole320are defined by the subsequent capacitor. It will be described in detail below. In some embodiments, the second hole310and the third hole320may be formed by an etching process with high selection ratio. It is worth mentioning that comparing to the third insulating layer280; the second insulating layer270has low quality because of doping boro-phospho-silicate glass (BPSG), so that the second portion of the second insulating layer270may easily be removed by the etching process with high selection ratio, thereby increasing the width of the holes310,320in the second insulating layer270. The removed second portion of the second insulating layer270is greater than the removed second portions of the fourth support layer290and third insulating layer280. Therefore, an upper edge of the third hole320has a seventh width W7, a lower edge of the second hole310has an eighth width W8, and the seventh width W7is substantially equal to the eighth width W8. It should be understand that the first hole250communicates with the second hole310and the third hole320. In one embodiment, the second hole310is aligned with the first hole250. In another embodiment, the second hole310is offset from the first hole250.

The method10continues to operation1100, a capacitor330is formed in the first, second, and third holes250,310, and320. According to some embodiments, operation190may be further understood with reference toFIG. 9, which is a cross-sectional view illustrating a stack capacitor structure20aaccording to some embodiments of the present disclosure. In some embodiments, the formation of the capacitor330includes the steps described below. Firstly, an outer electrode331is formed on walls of the first and second hole250,310. Specifically, the outer electrode331is formed conformally along walls of the first and second hole250,310. It is noted that the second hole310and the third hole320are defined after forming the outer electrode331. In order to define the subsequent source/drain (S/D) feature, therefore the outer electrode331do not form in the third hole320. In some embodiments, the outer electrode331includes titanium nitride (TiN). In some embodiments, the outer electrode331may be formed by using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

Please continue to referFIG. 9. A dielectric layer332is then formed on the outer electrode331and along the wall of the third hole320. Specifically, the dielectric layer332is formed conformally along the sidewall of the outer electrode331and wall of the third hole320. In some embodiments, the dielectric layer332is a high dielectric constant layer, and the material is, for example, aluminium oxide (AlO3), titanium oxide (TiO), aluminum nitride (AlN), hafnium oxide (HfO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum (V) oxide (TaO), zirconium oxide (ZrO), gadolinium (GdO), or a combination thereof. In some embodiments, the dielectric layer332may be formed by using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

Please continue to referFIG. 9. Subsequently, an inner electrode333is formed on the dielectric layer332. Specifically, the inner electrode333is formed conformally along the sidewall of the dielectric layer332. In some embodiments, the inner electrode333includes titanium nitride (TiN). In some embodiments, the inner electrode333may be formed by using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

The method10further includes a conductive material340is formed in direct contacting with the inner electrode333with reference toFIG. 9. Specifically, the conductive material340fills up the first and second hole250,310and extends into a portion of the third hole320. In some embodiments, the conductive material340may be a metal material or a semiconductor material. For example, the metal material may include tungsten (W), and the semiconductor material may include silicon (Si), and germanium (Ge). In some embodiments, the conductive material340may be formed in the holes250,310,320by using a physical vapor deposition process, a chemical vapor deposition process, and other suitable processes known in the art. It is noted that the conductive material340is used to provide support for the stack capacitor structure, thereby preventing collapse of the stack capacitor structure.

The method10further includes a source/drain (S/D) feature350is formed in the third hole320with reference toFIG. 9. Specifically, the source/drain (S/D) feature350is disposed on the conductive material340and surrounded by the inner electrode333. In various embodiments, the source/drain (S/D) feature350may include, but not limited to, Si, SiP, SiAs, SiGe, Ge, a III-V group compound semiconductor, or graphene.

According to another aspect of the present disclosure, a stack capacitor structure20ais provided.FIG. 9is a cross-sectional view illustrating a stack capacitor structure according to some embodiments of the present disclosure. To make it easy to compare differences between various embodiments and simplify the descriptions, the same symbols are used to label the same members in the following various embodiments and mainly the differences between the various embodiments are described while duplicate parts are not described again.

Please refer toFIG. 9. The stack capacitor structure20aincludes a substrate210, a first support layer220, a first insulating layer230, a second support layer240, a third support layer260, a second insulating layer270, a third insulating layer280, a fourth support layer290, a first hole250, a second hole310, a third hole320, and a capacitor330. The first support layer220is disposed over the substrate210. The first insulating layer230is disposed on the first support layer220. The second support layer240is disposed on the first insulating layer230. The material and other features of the substrate210, the first support layer220, the first insulating layer230, and the second support layer240are as described in relation to the substrate210, the first support layer220, the first insulating layer230, and the second support layer240shown inFIG. 2, and so will not be described here.

In some embodiments, the stack capacitor structure20amay further include a wiring layer211disposed between the substrate210and the first support layer220as shown inFIG. 9. The material and other features of the wiring layer211are as described in relation to the wiring layer211shown inFIG. 2, and so will not be described here. In some embodiments, the stack capacitor structure20amay further include a fourth insulating layer221disposed between the first support layer220and the first insulating layer230as shown inFIG. 9. The material and other features of the fourth insulating layer221are as described in relation to the fourth insulating layer221shown inFIG. 2, and so will not be described here.

The third support layer260is disposed on the second support layer240. The material and other features of the third support layer260are as described in relation to the third support layer260shown inFIG. 5, and so will not be described here. The second insulating layer270is disposed on the third support layer260. The third insulating layer280is disposed on the second insulating layer270. The fourth support layer290is disposed on the third insulating layer280. The material and other features of the second insulating layer270, the third insulating layer280, and the fourth support layer290are as described in relation to the second insulating layer270, the third insulating layer280, and the fourth support layer290shown inFIG. 6, and so will not be described here. It is noted that the material of the first insulating layer230is different from that of the second insulating layer270, and the second insulating layer270includes SiO doped with boro-phospho-silicate glass (BPSG), in various embodiments. It is noted that the material of the first, second and fourth support layer220,240,290are the same and the material of the first support layer220is different from that of the third support layer260. Specifically, the third support layer260includes SiN doped with carbon.

The first hole250penetrates through from a top surface of the second support layer240to a bottom surface of the first support layer220. In the embodiment of excluding the fourth insulating layer221, an upper edge of the first hole250has a width W3, a lower edge of the first hole250has a width W4, and the width W3is greater than the width W4. In the embodiment of including the fourth insulating layer221, an upper edge of the first hole250has a width W3, a lower edge of the first hole250has a width W4, and the width W3is substantially equal to the width W4. The formation and other features of the first hole250are as described in relation to the first hole250shown inFIGS. 3-4, and so will not be described here.

The second hole310penetrates through from the third insulating layer280to a bottom surface of the third support layer260. To be specific, the first hole250communicates with the second hole310. The third hole320penetrates through from a top surface of the fourth support layer290to the third insulating layer280. To be specific, the second hole310is aligned with the third hole320. In one embodiment, the first hole250is aligned with the second and third holes310,320. In another embodiment, the first hole250is offset from the second and third holes310,320. The formation and other features of the second hole310and the third hole320are as described in relation to the second hole310and the third hole320shown inFIGS. 7-8, and so will not be described here.

The capacitor330disposed in the first, second, and third holes250,310,320. In the embodiment of including the wiring layer, the first hole250penetrates through a portion of the wiring layer211and the capacitor330electrically connects the wiring layer211. It is noted that the first hole250extends into the wiring layer211, but do not penetrate through the wiring layer211. In some embodiments, the capacitor330includes an outer electrode331, a dielectric layer332and an inner electrode333in direct contact with each other. To be specific, the outer electrode331is conformally formed on sidewalls of the first and second hole250,310. The dielectric layer332is conformally formed on the sidewall of the outer electrode331and further extends to a sidewall of the third hole320. The inner electrode333is conformally formed on the sidewall of the dielectric layer332. In the embodiment of the second hole310being offset from the first hole250, the capacitor330has a staircase profile between the second support layer240and the third support layer260. The formation and other detail features of the capacitor330are as described in relation to the foregoing capacitor330, and so will not be described here.

In some embodiments, the stack capacitor structure20amay further include a conductive material340in direct contacts with the inner electrode333. In some embodiments, the conductive material340fills up the first and second hole250,310and extends into a portion of the third hole320. The formation and other detail features of the conductive material340are as described in relation to the foregoing conductive material340, and so will not be described here.

In some embodiments, the stack capacitor structure20amay further include a source/drain (S/D) feature350disposed in the third hole320and surrounded by the inner electrode333. In some embodiments, the top surface of the source/drain (S/D) feature350is leveled with the top surface of the fourth support layer290. In some embodiments, the bottom surface of the source/drain (S/D) feature350in direct contacts with the inner electrode333and the conductive material340. In some embodiments, the bottom surface of the source/drain (S/D) feature350is greater than a top surface of the conductive material340. The formation and other detail features of the source/drain (S/D) feature350are as described in relation to the foregoing source/drain (S/D) feature350, and so will not be described here.

In some embodiments, the stack capacitor structure20amay further include a transistor (not shown) electrically connecting to the source/drain (S/D) feature350.

FIG. 10is a cross-sectional view illustrating a stack capacitor structure according to some embodiments of the present disclosure. With reference toFIG. 10, the stack capacitor structure20bis the same as or similar in structure to the stack capacitor structure20a. Further, the stack capacitor structure20bmay be formed by the same method as forming the stack capacitor structure20a. Briefly, the difference between the stack capacitor structure20band the stack capacitor structure20ais that, in this embodiment, the stack capacitor structure20bdoes not include the fourth insulating layer221between the substrate210and the first support layer220.

As is apparent from the above detailed description, the stack capacitor structure according to the invention can be made large enough to provide a sufficient capacity of the capacitor. Moreover, the present invention uses the high etching selectivity of the second insulating layer and the fourth insulating layer to increase the electrical contacting area thereby avoiding poor electrical contact of the subsequent capacitors. Therefore, a semiconductor memory device particularly suitable for large scale integration can be manufactured without problem.