Three-dimensional magnetic random access memory with high speed writing

One embodiment of a magnetic random access memory includes a transistor formed on a substrate and having a gate width, a plurality of magnetoresistive elements disposed above the transistor and jointly electrically coupled to the transistor at their first terminals, a plurality of parallel conductive lines formed above magnetoresistive elements and independently electrically coupled to their second terminals. A magnetoresistive element includes, a pinned layer having a fixed magnetization direction, a free layer having a reversible magnetization direction, a tunnel barrier layer disposed between the free and pinned layers, and an element width that is substantially smaller than the gate width. The magnetization directions of the pinned and free layers are directed substantially perpendicular to the substrate. The magnetization direction of the free layer is reversed by a joint effect of a bias magnetic field and a spin-polarized current applied to the magnetoresistive element. Other embodiments are described and shown.

FEDERALLY SPONSORED RESEARCH

Not Applicable

SEQUENCE LISTING OR PROGRAM

Not Applicable

FIELD OF THE APPLICATION

The present application relates to a magnetic random access memory (MRAM) and, more specifically, to a perpendicular MRAM with high-speed writing that can be arranged in a three-dimensional architecture.

BACKGROUND

Magnetic random access memory (MRAM) is a new memory technology that will likely provide a superior performance over existing semiconductor memories including flash memory and may even replace hard disk drives in certain applications requiring a compact non-volatile memory device. In MRAM bit of data is represented by a magnetic configuration of a small volume of ferromagnetic material and its magnetic state that can be measured during a read-back operation. The MRAM typically includes a two-dimensional array of memory cells wherein each cell comprises one magnetic tunnel junction (MTJ) (or magnetoresistive (MR)) element that can store at least one bit of data, one selection transistor (T) and intersecting conductor lines (so-called 1T-1MTJ design).

Conventional MTJ element represents a patterned thin film multilayer that includes at least a pinned magnetic layer and a free magnetic layer separated from each other by a thin tunnel barrier layer. The free layer has two stable directions of magnetization that are parallel or anti-parallel to the fixed direction of the magnetization in the pinned layer. Resistance of the MTJ depends on a mutual orientation of the magnetizations in the free and pinned layers and can be effectively measured. A resistance difference between the parallel and anti-parallel states of the MTJ can exceed 600% at room temperature.

The direction of the magnetization in the free layer may be changed from parallel to anti-parallel or vice-versa by applying two orthogonal magnetic fields to the selected MTJ, by passing a spin-polarized current through the selected junction in a direction perpendicular to the junction plane, or by using a hybrid switching mechanism that assumes a simultaneous application of the external magnetic field and spin-polarized current to the selected MTJ. The hybrid switching mechanism looks the most attractive among all others since it can provide good cell selectivity in the array, relatively low switching current and high write speed.

FIGS. 1A and 1Bshow a schematic cross-sectional and top down views of MRAM cell10employing the hybrid switching mechanism according to a prior art disclosed in U.S. Pat. No. 7,006,375 (Covington). The cross-section was taken alone the line1A-1A shown in theFIG. 1B. The memory cell10includes a semiconductor wafer11with a selection transistor12, MTJ element21, a word line16and a bit line19that are orthogonal to each other (1T-1MTJ design). The bit line19and the MTJ element21are connected in series to a source region13of the selection transistor12. The MTJ element21includes a pinned magnetic layer22with a fixed in-plane magnetization direction (shown by an arrow), a free magnetic layer23with a changeable in-plane magnetization direction (shown by arrows), a thin tunnel barrier layer24positioned between the free23and pinned22layers, and a pinning anti-ferromagnetic layer25exchange coupled with the pinned layer22. The MTJ element21has an elliptical shape with a major axis of the ellipse being oriented in parallel to the word line19. An easy magnetic axis of the pinned and free layers coincides with the major axis. The transistor12comprises a gate15having a width W of about a width F of the MTJ element21(W=F). A drain region14of the transistor12is connected to a ground line18through a contact plug17.

To write a data to the MTJ element21, a bias electric current IBis applied to the bit line19. The current IBinduces a magnetic bias field HBthat affects the free layer23along its hard magnetic axis. The field HBforces the magnetization direction in the free layer23from its equilibrium state that is parallel to the major axis of the MTJ element21. By applying a voltage to the gate15through the word line16the selection transistor12can be turned on. The transistor12delivers a spin-polarized current Isto the MTJ element21. The current ISrunning through the element21produces a spin momentum transfer that together with the bias field HBprovides a reversal of the magnetization direction in the free layer23. The magnetization direction in the free layer23is controlled by a direction of the spin-polarized current Is. Magnitude of the spin-polarized current Isrequired to reverse the magnetization in the free layer23depends on the strength of the bias field HBthat tilts the magnetization direction in the free layer relatively its equilibrium state. The switching current Iscan be reduced more than twice by the relatively small bias magnetic field HB.

The MTJ with in-plane magnetization direction requires a high magnitude of the switching current Iseven with applied magnetic bias field HB. Magnitude of the spin-polarized current Isdefines a write speed of the memory cell; the speed increases with the current. The spin-polarized current Isof the cell10is limited by a saturation current of the transistor12that is proportional to a gate width W. The selection transistor12has the gate width W=comparable to the width F of the elliptical MTJ element21. This gate width is incapable to deliver the required magnitude of the current Is. To overcome the above obstacles the gate width W of the transistor12needs to be substantially increased. However that will result in considerable increase of memory cell size and in MRAM density reduction.

Majority of the current MRAM designs uses the free and pinned layers made of magnetic materials with in-plane anisotropy. The in-plane MRAM (i-MRAM) suffers from a large cell size, low thermal stability, poor scalability, necessity to use MTJ with a special elliptical shape, and from other issues, which substantially limit a possibility of i-MRAM application at technology nodes below 90 nm.

MRAM with a perpendicular direction of the magnetization in the free and pinned layers (p-MRAM) does not suffer from the above problems since perpendicular magnetic materials have a high intrinsic crystalline anisotropy. The high anisotropy provides the p-MRAM with the excellent thermal stability and scalability, and with a possibility to use junctions of any shape. Nevertheless the existing p-MRAM designs have a large cell size and require a relatively high switching current.

What is needed is a simple design of p-MRAM having a high switching speed at low current, small cell size, high capacity and excellent scalability.

SUMMARY

The present application provides a three-dimensional magnetic random access memory (3D-MRAM) with a perpendicular magnetization for high-speed writing.

In accordance with one embodiment a magnetic random access memory comprises a substrate, a plurality of transistors formed on the substrate and arranged in a matrix, each transistor comprising a gate width; a memory layer formed on the substrate and comprising a plurality of memory cells arranged in the matrix, each memory cell overlaid a transistor and comprising a plurality of magnetoresistive elements jointly electrically coupled to the transistor at first terminals, each magnetoresistive element comprising an element width, a pinned ferromagnetic layer comprising a fixed magnetization direction directed substantially perpendicular to the substrate, a free ferromagnetic layer comprising a reversible magnetization direction directed substantially perpendicular to the substrate in an equilibrium state, a tunnel barrier layer disposed between the pinned and free ferromagnetic layers; and a plurality of parallel conductive lines disposed above the memory layer and independently electrically coupled to second terminals of the magnetoresistive elements, wherein the gate width is substantially larger than the element width.

In accordance with another embodiment a method of writing to a magnetic random access memory includes providing a substrate, a transistor formed on the substrate and comprising a gate width, a memory cell disposed above the transistor and comprising a plurality of magnetoresistive elements jointly electrically coupled to the transistor at first terminals, each magnetoresistive element comprising an element width, a pinned ferromagnetic layer disposed adjacent to a first terminal and comprising a fixed magnetization direction directed substantially perpendicular to the substrate, a free ferromagnetic layer disposed adjacent to a second terminal and comprising a reversible magnetization direction directed substantially perpendicular to the substrate in an equilibrium state, a tunnel barrier layer disposed between the pinned and free ferromagnetic layers, and a plurality of parallel conductive lines independently electrically coupled to second terminals of the magnetoresistive elements; driving a bias current through a conductive line for producing a bias magnetic field directed along a hard magnetic axis of the free ferromagnetic layer; and driving a spin-polarized current through the magnetoresistive element between the first and second terminals in a direction perpendicular to the substrate for producing a spin momentum transfer. The magnetization direction of the free ferromagnetic layer is reversed by a joint effect of the bias and spin-polarized currents applied simultaneously.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown be way of illustration specific embodiments in which the application may be practiced. It is understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present application.

The leading digits of reference numbers appearing in the Figures generally corresponds to the Figure number in which that component is first introduced, such that the same reference number is used throughout to refer to an identical component which appears in multiple Figures.

FIG. 2Ashow a schematic cross-sectional view of a memory cell20according to an embodiment of the present application. The cross-section is taken along line2A-2A that is shown in theFIG. 2B. The memory cell20comprises a semiconductor substrate11with a selection transistor12, a MTJ (or magnetoresistive) element21, a word line16and a bit line19; the lines16and19overlap each other. The MTJ element21comprises a pinned layer22with a fixed magnetization direction (shown by an arrow) directed substantially perpendicular to a layer plane, a free layer23with a changeable magnetization direction (shown by two arrows) directed substantially perpendicular to a layer plane in its equilibrium state, a tunnel barrier layer24sandwiched between the pinned22and free23layers, a seed layer26and a cap layer27. The free layer23has two stable directions of the magnetization in its equilibrium state: up or down. The MTJ element21is electrically connected to the bit line19and to the source region13of the transistor12through a contact plug17. The word line16is coupled to the gate region15through an insulator layer (not shown). The memory cell20comprises two MTJ elements21-1and21-2, and two parallel bit lines19-1and19-2. The MTJ element21-1is electrically connected to the line19-1at one end adjacent to the free layer23. Respectively, the MTJ element21-2is connected to the line19-2. Both the MTJ elements at their second ends are jointly connected to the source region13of the transistor12through the contact plug17. The transistor12has a footprint size comparable with the size of the cell20(shown by a dash-dot line) and the gate width of about W=3F, where F is a diameter of the MTJ elements. The large gate width W provides the transistor12with a high saturation current, which is important for high-speed writing.

The memory cell20has a 1T-2MTJ (one transistor-two MTJs) design. Number of the MTJ elements in the cell20can be any. Each MTJ element of the memory cell20has a unique combination of the bit and word lines that provides its selection in the MRAM array. For instance, to write data to the MTJ element21-1the bias current IBneeds to be run in the bit line19-1and the spin-polarized current Isshould run through the element in direction perpendicular to its plane. The spin-polarized current Isis controlled by the word line16that intersects the bit line19-1in vicinity of the MTJ element21-1. Combined effect of the bias IBand spin-polarized Iscurrents can reverse the magnetization direction in the free layer23of the element21-1.

In some embodiments the MTJ element21has a multilayer structure of the pinned22and free23layers. TheFIG. 3illustrates a memory cell30according to another embodiment with a bilayer structure of the pinned22and free23layers. The free layer23comprises a storage layer34having a perpendicular anisotropy and a first coercivity, and a soft magnetic underlayer32having a second coercivity. The soft magnetic underlayer32is disposed between the tunnel barrier layer24and the storage layer34and is substantially magnetically coupled to the storage layer34. The coercivity of the storage layer34is significantly higher than the coercivity of the soft magnetic underlayer32. The pinned layer22comprises the reference layer38with a perpendicular anisotropy and a third coercivity, and a spin-polarizing layer37with a fourth coercivity. The coercivity of the reference layer38is substantially higher than the coercivity of the storage layer34. The spin-polarizing layer37is disposed between the tunnel barrier layer24and the reference layer38and is substantially magnetically coupled to the reference layer38. The soft magnetic underlayer32can be made of a soft magnetic material with perpendicular or in-plane crystalline anisotropy. However due to a strong magnetic coupling to the storage layer34the orientation of magnetization in the soft magnetic underlayer32can be maintained perpendicular to layer plane in its equilibrium state.

A pulse of the bias current IBrunning in the bit line19induces a bias magnetic field HBthat is applied to the free layer23along its hard axis. The field HBtilts the magnetization M32in the soft magnetic underlayer32on the angle Θ32but does not change the direction of the magnetizations M22and M34in the pinned22and storage34layers, respectively. The angle Θ32depends on the bias current magnitude, on thickness and magnetic properties of the soft magnetic underlayer32and the storage layer34, and on the strength of the magnetic coupling between them. Tilting of the magnetization M32in the soft magnetic underlayer32provides a significant reduction of the magnitude of spin-polarized current pulse ISthat is required to reverse the magnetization direction in the storage layer34. The spin-polarizing layer37offers a high spin polarization of the switching current that is also important for reduction of ISmagnitude. The material of the spin-polarizing layer can have perpendicular or in-plane anisotropy. The direction of magnetization in the spin polarizing layer37does not change under the bias field HBdue to its strong magnetic coupling with the reference layer38. The magnetizations directions in the soft magnetic underlayer32and in the spin-polarizing layer37are substantially collinear (parallel or anti-parallel) in the equilibrium state. That is important for providing a high output signal during read operation. The saturation current of the transistor12does not limit the magnitude of the spin-polarized current ISsince the transistor has a large gate width W. At the same time, the bias field HBoffers a significant reduction of the spin-polarized current ISand an additional opportunity of the write speed increase.

FIGS. 4A and 4Billustrate two memory cells40according to yet another embodiment of the present application wherein one of the cells is shown by a dash-dot line. The cells have a common ground line18connected to the common drain region14of two selection transistors12. Footprints of the selection transistor12and the memory cell40coincide. The cells40have 1T-4MTJ design with four MTJ elements21-1,21-2,21-3and21-4, and four parallel bit lines19-1,19-2,19-3and19-4separately connected to the appropriate elements at their second ends adjacent to the free layer23. All MTJ elements of the memory cells40are jointly connected at their first ends adjacent to the pinned layer24with the source region13of the proper transistor12through the contact plug17. Selection of a MTJ element in the MRAM array is provided by unique combination of bit and word lines overlapping at the MTJ location. The transistors12have a gate width of about W=7F and can deliver a considerable spin-polarized current to the MTJ elements21for high-speed writing.

FIG. 4Bshows a schematic cross-sectional view of the cells40given inFIG. 4A. The cross section was taken along4B-4B line. Elements of the cells40have functions similar to those inFIGS. 2A and 2B. Each of the cells40additionally includes a local conductor line42. The MTJ elements21of the memory cell40are jointly electrically connected to the source region13of the proper transistor12.

FIG.5shows a schematic cross sectional view of two cells50of three-dimensional MRAM according to yet another embodiment of the present application. Each of the cells50comprises two memory layers54-1and54-2that include a plurality of MTJ elements21, and two conductor layers disposed above the memory layers54-1and54-2. Each of the conductor layers comprises a plurality of parallel bit lines19. The bit lines19disposed in the different conductor layers are parallel to each other and overlap the word lines16. Selection of the MTJ in the 3D-MRAM is provided by a unique combination of the word line16, the bit line19and the memory layer. Elements of the cells50have functions similar to those in theFIGS. 2A and 2B. The three-dimensional memory cell50provides a possibly of substantial MRAM density increase. The MTJ elements of the 3D-MRAM can have different interconnection schemes.

FIG. 6shows a circuit diagram of 3D-memory cell60according to still another embodiment of the present application. The memory cell60has 1T-2MTJ-2L design, where 2are two memory layers. It includes one selection transistor12, two MTJ elements21per memory layer and two memory layers54-1and54-2. The number of MTJ elements in the memory layer and the number of memory layers can be any. All MTJ elements21of the memory cell60are jointly connected to the source of the selection transistor12at their first ends that are adjacent to the pinned layers22and separately connected to an appropriate word line19at their second ends that are adjacent to the free layer23(FIG.5). The word line16is connected to a word line circuitry62. The bit lines19are connected to the bit line circuitry64. The bit line circuitry can includes several bit line drivers with one driver per conductor layer. For instance, the lines19-1-1and19-2-1of the bottom conductor layer are connected to the bit line driver64-1and the bit lines19-1-2and19-2-2of the top conductor layer are connected to the bit line driver64-2. The number of the bit line drivers can be any.

FIG. 7shows a circuitry diagram of 3D-memory cell70according to still another embodiment of the present application. The memory cell70has 1T-2MTJ-2L design but distinguishes from the cell60shown in theFIG.6by electrical connection between the overlaying MTJ elements19of the different memory layers54-1and54-2. The MTJ elements19of the layers54-1and54-2are connected in series to each other to form columns of the MTJ elements. The columns of the MTJ elements are jointly connected to the selection transistor12.

There is wide latitude for the choice of materials and their thicknesses within the embodiments.

The pinned layer22has a thickness of about 10-100 nm and more specifically of about 25-50 nm and coercivity measured along its easy axis above 1000 Oe and more specifically of about 2000-5000 Oe. The layer22is made of magnetic material with perpendicular anisotropy such as Co, Fe or Ni-based alloys or their multilayers such as Co/Pt, Co/Pd, Co/Au, CoFe/Pt, Fe/Pt, Fe/Pd, Ni/Cu or similar.

The free layer23has a thickness of about 1-30 nm and more specifically of about 5-15 nm and coercivity less than 1000 Oe and more specifically of about 100-300 Oe. The layer23is made of soft magnetic material with perpendicular anisotropy such as Co, Fe or Ni-based alloys or multilayers such as Co/Pt, Co/Pd, Co/Au, CoFe/Pt, Fe/Pt, Fe/Pd, Ni/Cu or similar.

The tunnel barrier layer24has a thickness of about 0.5-25 nm and more specifically of about 0.5-1.5 nm. The tunnel barrier layer is made of MgO, Al2O3, Ta2O5, TiO2, Mg—MgO and similar materials or their based laminates.

The seed26and cap27layers have a thickness of 1-100 nm and more specifically of about 5-25 nm. The layers are made of Ta, W, Ti, Cr, Ru, NiFe, NiFeCr, PtMn, IrMn or similar conductive materials or their based laminates.

The conductor lines18and19are made of Cu, Al, Au, Ag, AlCu, Ta/Au/Ta, Cr/Cu/Cr and similar materials or their based laminates.

The soft magnetic underlayer32is 0.5-5 nm thick and is made of a soft magnetic material with a substantial spin polarization and coercivity of about 1-200 Oe such as CoFe, CoFeB, NiFe, Co, Fe, CoPt, FePt, CoPtCu, FeCoPt and similar or their based laminates such as CoFe/Pt, CoFeB/Pd and similar. The material of the soft magnetic underlayer74can have either in-plane or perpendicular anisotropy.

The storage layer34has a thickness of 5-25 nm and more specifically of about 8-15 nm; and coercivity less than 1000 Oe and more specifically of about 200-500 Oe. The storage layer76is made of magnetic material with a substantial perpendicular anisotropy such as Co, Fe or Ni-based alloys or multilayers such as Co/Pt, Co/Pd, Co/Au, CoFe/Pt, Fe/Pt, Fe/Pd, Ni/Cu or similar.

The spin-polarizing layer37has a thickness of 0.5-5 nm and is made of a soft magnetic material with a coercivity of about 1-200 Oe and a substantial spin polarization such as CoFe, CoFeB, NiFe, Co, Fe, CoPt, FePt, CoPtCu, FeCoPt and similar or their based laminates such as CoFe/Pt, CoFeB/Pd and similar. The material of the spin-polarizing layer37can have either in-plane or perpendicular anisotropy.

The reference layer38has a thickness of 10-100 nm and more specifically of about 20-50 nm; and coercivity above 1000 Oe and more specifically of about 2000-5000 Oe. The reference layer38is made of magnetic material with a substantial perpendicular anisotropy such as Co, Fe or Ni-based alloys or multilayers such as Co/Pt, Co/Pd, Co/Au, CoFe/Pt, Fe/Pt, Fe/Pd, Ni/Cu or similar.

It is understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the application should be, therefore, determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.