High voltage semiconductor devices and methods for fabricating the same

High voltage semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device capable of high-voltage operation, comprising a substrate comprising a first well formed therein. A gate stack is formed overlying the substrate, comprising a gate dielectric layer and a gate electrode formed thereon. A channel well and a second well are formed in portions of the first well. A source region is formed in a portion of the channel well. A drain region is formed in a portion of the second well, wherein the gate dielectric layer comprises a relatively thinner portion at one end of the gate stack adjacent to the source region and a relatively thicker portion at one end of the gate stack adjacent to and directly contacts the drain region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuit fabrication, and in particular to semiconductor devices capable of sustaining high-voltage and methods for fabricating the same

2. Description of the Related Art

In current integrated circuit processing, controllers, memories, operation of low-voltage circuits and high-voltage (HV) power devices are largely integrated into a single chip, thus achieving a single-chip system. To handle high voltage and current, DMOS (double-diffused metal oxide semiconductor) transistors are conventionally used for the power devices, which can operate with low on-resistance while sustaining high voltage.

LDMOS (lateral double-diffused metal oxide semiconductor) transistors in particular have a simple structure suitable for incorporation into the VLSI logic circuits, however, they have been considered inferior to VDMOS (vertically double-diffused metal oxide semiconductor) transistors as they have high on-resistance. Recently, RESURF (reduced surface field) LDMOS devices, capable of providing low on-resistance, have been introduced and are increasingly used in power devices.

FIG. 1illustrates a portion of a conventional LDMOS transistor, including a substrate100, a well region102, a first oxide region104, a second oxide region106, a gate oxide layer108, a gate electrode110, a channel well region112, a source region114, and a drain region116.

As shown inFIG. 1, the second oxide region106is formed over the substrate100and the gate electrode110partially covers a portion of the second oxide region106, therefore enabling high-voltage (HV) operation of the LDMOS transistor. Nevertheless, one problem of the conventional LDMOS transistor ofFIG. 1is that the second oxide region106interrupts current flowing from the source region114to the drain region116. This eventually increases on-resistance of the LDMOS transistor.

Moreover, a semiconductor device having the conventional LDMOS transistor ofFIG. 1needs a large cell pitch and is therefore disadvantageous when the size of the semiconductor device is reduced.

BRIEF SUMMARY OF THE INVENTION

High voltage semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device capable of high-voltage operation, comprising a substrate comprising a first well formed therein. A gate stack is formed overlying the substrate, wherein the gate stack comprises a gate dielectric layer and a gate electrode formed thereon. A channel well and a second well are formed in portions of the first well, located on opposite sides of the gate stack. A source region is formed in a portion of the channel well. A drain region is formed in a portion of the second well, wherein the first well and the second well is formed with a conductivity type opposite to that of the substrate, the channel well is formed with a conductivity type the same as that of the substrate, wherein the gate dielectric layer comprises a relatively thinner portion at one end of the gate stack adjacent to the source region and a relatively thicker portion at one end of the gate stack adjacent to and directly contacts the drain region.

Another embodiment of a method for fabricating a semiconductor device capable of high-voltage operation, comprises providing a substrate formed with a first well therein. A channel well is formed in a first portion of the first well. A patterned composite layer is formed over a portion of the-substrate, covering the channel well and exposing a portion of the first well, wherein the patterned composite layer comprises a dielectric layer, a conductive layer and a mask layer sequentially stacked over the substrate. A second well is formed in a second portion of the exposed first well. An oxide layer is simultaneously formed over the conductive layer and the surface of the substrate exposed by the conductive layer, and an oxide portion is formed in a portion of the conductive layer adjacent to the second well region after removal the mask layer of the patterned the composite layer. The oxide layer formed over the conductive layer and the exposed surface of the substrate are removed, leaving the dielectric layer integrated with the oxide portion protruding at the end of the conductive layer adjacent to the second well as a gate dielectric layer. The conductive layer and the gate dielectric layer are next patterned and a gate stack is thus formed overlying the substrate exposing a portion of the channel well region and a portion of the second well region. A source region is next formed in a portion of the exposed channel region and a drain region is formed in a portion of the exposed second well region, wherein the first well, the second well, the source region and the drain region are formed with a conductivity type opposite to that of the substrate, the channel well is formed with a conductivity type the same as that of the substrate, and the gate dielectric layer directly contacts the drain region.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 2-6illustrate an exemplary embodiment of a method for fabricating a semiconductor device including an LDMOS with reduced size and improved electrical performance.

InFIG. 2, a semiconductor substrate200is provided with two isolation structures202thereon, defining an active area A. The semiconductor substrate200can be, for example a silicon on insulator (SOI) substrate, a bulk silicon substrate or silicon epitaxy layer formed over a substrate. The semiconductor substrate200can be formed with a first conductive type such as P-type or N-type conductivity. The isolation structures202inFIG. 1are illustrated as field oxide (FOX) regions here but are not limited thereto, other isolation structures such as conventional shallow trench isolation (STI) structures can be also adopted. Next, a first well region204is formed in the substrate200, having a conductive type opposite to that of the substrate200. The doping concentration of the first well region204can be, for example, between 1E12 atoms/cm2and 1E13 atoms/cm2. Formation of the first well region204can be achieved by the well known well implantation method using a patterned implant mask (not shown). A channel well region206is next formed in a portion of the first well region204, having a conductive type the same as that of the substrate200. The doping concentration of the channel well region206can be, for example, between 1E13 atoms/cm2and 1E14 atoms/cm2. Formation of the first well region204and the channel well region206can be achieved by conventional well implantation techniques using a patterned implant mask (not shown) and well known P-type or N-type dopants.

InFIG. 3, a dielectric layer208is next formed on the substrate200within the active area A. A conductive layer210is sequentially formed over the substrate200, covering the dielectric layer208and the isolation structures202. Next, a patterned mask layer212is formed over the conductive layer210and exposes a portion of the conductive layer210in the active area A. An etching (not shown) is next performed to remove the conductive layer210and the dielectric layer208exposed by the patterned mask layer212, thereby exposing a portion of the substrate200in the active area A. Next, an ion implantation214is performed to implant dopants of the same conductive type as that of the first well region204, forming a second well region216in the first well region204. The doping concentration of the ion implantation214is about, for example, 1E12 atoms/cm2and 1E14 atoms/cm2. Doping concentration in the formed second well region216can be, for example, 1E12 atoms/cm2and 1E14 atoms/cm2and is larger than that of the first well region204, thereby providing an additional resistant for the finally formed LDMOS breakdown and on-resistance trade off during HV operation. The dielectric layer208can be a silicon oxide layer formed by, for example, thermal oxidation and the conductive layer210may be silicon-containing conductive layer, for example a polysilicon layer. The patterned mask layer212may be, for example, a resist layer.

InFIG. 4, the patterned mask layer212is removed and an annealing process217is sequentially performed under an oxygen-containing atmosphere and a temperature between about 800-1000° C. Therefore, silicon oxide layers218aand218brespectively forms over exposed portions of the conductive layer210and the surface of the substrate200over the second well region216. Since the conductive layer210is formed by silicon-containing conductive layer such as polysilicon and the substrate is formed of silicon, growth rates of the silicon oxide layers218aand218bare therefore different. Typically, the growth rate of the silicon oxide layer218aformed over the patterned conductive layer210is greater than that of the silicon oxide layer218bformed over the substrate. Thus, the silicon oxide layer218ais formed at a thickness greater than that of the silicon oxide layer218bafter the thermal annealing process216. Moreover, oxidation also occurs at an interface between the patterned conductive layer210and the patterned dielectric layer208at a side wall adjacent to the second well region216during the annealing process217and further protrudes into the patterned conductive layer210along the interface, thus forming an oxide portion218cin an end adjacent to the second well region216.

InFIG. 5, an etching (not shown) is next performed to remove both the silicon oxide layers218aand218b, thereby leaving the patterned conductive layer210and the patterned dielectric layer208over the substrate200, wherein the patterned conductive layer210is formed with oxide portion218ctherein at the end adjacent to the second well region216. Next, a patterned mask layer (not shown) is formed over the substrate200, exposing a portion of the patterned conductive layer210and the patterned dielectric layer208at the end adjacent to the channel well region206and a sequential etching is performed thereon, using the patterned mask layer as an etching mask, thereby forming a gate stack G over the substrate200after removal of the patterned mask layer.

As shown inFIG. 5, the gate stack G includes a gate electrode210aand an underlying gate dielectric layer220, wherein the gate dielectric layer220comprises a patterned dielectric layer208aand a thermally formed oxide portion218cwhich protrudes into the gate stack G at the end adjacent to the second well region216, having a triangle-like shape but is not limited thereto.

InFIG. 6, a source/drain implantation (not shown) is performed on the substrate200and the gate stack G under protection of properly formed mask patterns (not shown) formed over the substrate200, thereby forming a source region230in the channel well region206and a drain region240in the second well region216, each directly contacting the gate stack G. The source region230and the drain region240are formed with a conductive type the same as that of the first well region204and have a doping concentration of about 1E15 atoms/cm2and 7E15 atoms/cm2.

Moreover, the gate dielectric layer220of the LDMOS transistor shown inFIG. 6is now integrally formed with a relatively thicker portion protruding into the gate electrode210aat the end of the gate stack G adjacent the drain region240, thus providing the formed LDMOS transistor with HV operating capability, such as the capability to operate at 5 voltage or above. Typically, the other portion of the gate dielectric layer220is formed with a substantially uniform thickness of about 30-200 Å, extending from the source region230toward the drain region240, and is relatively thinner than that of the above mentioned relatively thicker portion. The relatively thicker portion of the gate dielectric layer220is formed at a various thickness between 300-2000 Å and the thickness therefore increases progressively and continuously toward the drain region240. Therefore, an LDMOS transistor with reduced size and on-resistance is obtained, since there is no additional bulk oxide layer (i.e. the second oxide region106inFIG. 1) formed over the substrate200and the gate stack G of the LDMOS transistor directly contacts the drain region240.