SEMICONDUCTOR DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL AND METHOD OF MANUFACTURING THE SAME

A semiconductor device may include a two-dimensional (2D) material layer, a source electrode and a drain electrode spaced apart from each other on the 2D material layer, a gate insulating layer and a gate electrode on the 2D material layer between the source electrode and the drain electrode, and graphene layers on both sides of the gate insulating layer. The 2D material layer may include a 2D semiconductor material having a polycrystalline structure. The 2D material layer may include a sheet member and a protrusion. The sheet member may extend along one plane. The protrusion may extend in one direction perpendicular to the one plane. The graphene layer may cover a part of the sheet member and the protrusion.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0096993, filed on Aug. 3, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The disclosure relates to a semiconductor device including a two-dimensional (2D) material and a method of manufacturing the semiconductor device.

2. Description of the Related Art

A transistor is a semiconductor device that performs an electrical switching function, and is used in various semiconductor products such as memories, driving integrated circuits (ICs), etc. When the size of a semiconductor device is reduced, the number of semiconductor devices that may be integrated into one wafer may increase, and the driving speed of the semiconductor device may increase. Accordingly, research for miniaturizing semiconductor devices and improving device integration has been actively conducted.

Recently, research using two-dimensional (2D) materials has been conducted as a solution for miniaturization of semiconductor devices. A 2D material is in the spotlight as a material capable of overcoming the limitation of performance degradation due to a decrease in the size of a semiconductor device because the 2D material has stable and excellent properties even in a thin thickness equal to or less than 1 nm.

SUMMARY

Provided are a semiconductor device including a two-dimensional (2D) material and a method of manufacturing the semiconductor device.

According to an example embodiment, a semiconductor device may include a two-dimensional (2D) material layer including a 2D semiconductor material having a polycrystalline structure; a source electrode and a drain electrode spaced apart from each other on the 2D material layer; a gate insulating layer and a gate electrode on the 2D material layer between the source electrode and the drain electrode; and graphene layers on both sides of the gate insulating layer. The 2D material layer may include a sheet member and a protrusion. The sheet member may extend along one plane and the protrusion may extend in one direction perpendicular to the one plane. The graphene layers may cover a part of the sheet member and the protrusion.

In some embodiments, the graphene layers may be on the part of the sheet member and an upper portion of the protrusion through a horizontal junction along the one plane and a vertical junction in the one direction perpendicular to the one plane.

In some embodiments, the protrusion may be a single protrusion or a plurality of protrusions.

In some embodiments, the 2D material layer may include a first region and second regions. The first region may correspond to the gate electrode, and the second regions may correspond to the source electrode and the drain electrode. The protrusion may be in the second regions. The graphene layers may be in the second regions between the source electrode and the 2D material layer and between the drain electrode and the 2D material layer.

In some embodiments, a thickness of the sheet member in the first region and a thickness of the sheet member in the second regions may be equal to each other.

In some embodiments, a thickness of the sheet member in the second regions may exceed a thickness of the sheet member in the first region.

In some embodiments, the semiconductor device may further include spacers. The 2D material layer may include a first region and second regions. The first region may correspond to the gate electrode. The second regions may correspond to a region between the source electrode and the gate electrode and a region between the drain electrode and the gate electrode. The protrusion may be in the second regions. The graphene layers may be between the 2D material layer and the spacers in the second regions. The spacers may be between the source electrode and the gate electrode and between the drain electrode and the gate electrode in the second regions.

In some embodiments, the graphene layers may extend under the source electrode and the drain electrode.

In some embodiments, the 2D semiconductor material may include a material having a bandgap greater than or equal to about 0.5 eV and less than or equal to about 3.0 eV.

In some embodiments, the 2D semiconductor material may include transition metal dichalcogenide (TMD) or black phosphorus.

In some embodiments, the TMD may include a metal element and a chalcogen element. The metal element may include at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc or Re. The chalcogen element may include at least one of S, Se or Te.

In some embodiments, the 2D material layer may include one to ten layers.

In some embodiments, the 2D material layer may include one to five layers.

In some embodiments, the graphene layers may include graphene, and the graphene may have a crystal size of about 0.5 nm or more and about 500 nm or less.

In some embodiments, the graphene layers may include graphene, and the graphene may have a ratio of carbons having a sp2 combination structure with respect to all carbons of about 50% or more and about 99% or less.

In some embodiments, the graphene layers may include graphene, and the graphene may have hydrogen in a range of about 1 at % or more and about 20 at % or less.

In some embodiments, the semiconductor device may include a mixing region where the 2D material layer and the graphene layers coexist in the one direction. In the mixing region, a content of graphene in the graphene layers may be about 20 vol % or more and about 80 vol % or less.

In some embodiments, the mixing region may include a region of one to five layers.

According to an embodiment, an electronic device may include any one of the semiconductor devices described above.

According to an example embodiment, a method of manufacturing a semiconductor device may include forming a two-dimensional (2D) material layer on a substrate, the 2D material layer including a 2D semiconductor material having a polycrystalline structure, the 2D material layer including a sheet member and a protrusion, the sheet member extending along one plane and the protrusion extending in one direction perpendicular to the one plane; forming a graphene layer covering a part of the sheet member and the protrusion; forming a gate insulating layer and a gate electrode on the 2D material layer; and forming a source electrode and a drain electrode spaced apart from each other on the 2D material layer.

In some embodiments, the forming the graphene layer may include growing graphene in one or more directions from the part of the sheet member and a circumference of the protrusion.

In some embodiments, the protrusion may be a single protrusion or a plurality of protrusions.

In some embodiments, the 2D material layer may include a first region and second regions. The first region may correspond to the gate electrode. The second regions may correspond to the source electrode and the drain electrode. The protrusion may be in the second regions. The graphene layer may be in the second regions between the source electrode and the 2D material layer and between drain electrode and the 2D material layer.

In some embodiments, the forming the graphene layer may be performed using one or more of low temperature chemical vapor deposition (LTCVD), inductively coupled plasma-chemical vapor deposition (ICP-CVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), metal organic chemical vapor deposition (MOCVD), and plasma-enhanced chemical vapor deposition (PECVD).

In some embodiments, the 2D semiconductor material may include a material having a bandgap of about 0.5 eV to about 3.0 eV.

In some embodiments, the 2D semiconductor material may include transition metal dichalcogenide (TMD) or black phosphorus.

In some embodiments, the 2D semiconductor material layer may include one to ten layers.

In some embodiments, the graphene layer may include graphene, and the graphene may have a crystal size of about 0.5 nm to about 500 nm.

In some embodiments, the graphene layer may include graphene, and the graphene may have a ratio of carbons having a sp2 combination structure with respect to all carbons of about 50% to about 99%.

In some embodiments, the graphene layer may include graphene, and the graphene may have hydrogen in a range of about 1 at % to about 20 at %.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of A, B, and C,” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”) may be construed as A only, B only, C only, or any combination of two or more of A, B, and C, such as, for instance, ABC, AB, BC, and AC.

Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings. In the following drawings, like reference numerals refer to like elements, and the size of each component in the drawings may be exaggerated for clarity and convenience of description. The embodiments of the disclosure may be variously modified and may be embodied in many different forms.

Hereinafter, what is described as “upper” or “on” may include those directly above, below, left, and right in contact, as well as above, below, left, and right in non-contact. The singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. When a part “comprises” or “includes” an element in the specification, unless otherwise defined, it is not excluding other elements but may further include other elements.

The term “above” and similar directional terms may be applied to both singular and plural. Operations of all methods described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context and are not necessarily limited to the described order.

Also, in the specification, the term “unit” or “module” denote a unit or a module that processes at least one function or operation, and may be implemented by hardware, software, or a combination of hardware and software.

Also, the connections of lines and connection members between constituent elements depicted in the drawings are examples of functional connection and/or physical or circuitry connections, and thus, in practical devices, may be expressed as replicable or additional functional connections, physical connections, or circuitry connections.

The use of any and all examples, or example language provided herein, is intended merely to better illuminate the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed.

FIG.1is a cross-sectional view of a semiconductor device according to an embodiment.FIG.2schematically illustrates a partial cross-section of a semiconductor device according to an embodiment. A semiconductor device100illustrated inFIG.1may be, for example, a field effect transistor (FET).

Referring toFIGS.1and2, a two-dimensional (2D) material layer110as a channel layer may be disposed on a substrate101according to an embodiment. The substrate101may include various materials such as a semiconductor material, an insulating material, and a metal material. When the 2D material layer110to be described below is formed by depositing a 2D semiconductor material on the substrate101, the substrate101may be a substrate for growth of the 2D semiconductor material.

The 2D material layer110may include a 2D semiconductor material having a polycrystalline structure. The 2D semiconductor material refers to a 2D material having a layered structure in which constituent atoms are two-dimensionally combined. The 2D semiconductor material has excellent electrical properties and may maintain high mobility without significantly changing its properties even when its thickness is reduced to a nanoscale.

The 2D semiconductor material may include a material having a bandgap equal to or greater than about 0.5 eV and equal to or smaller than 3.0 eV. For example, the 2D semiconductor material may include transition metal dichalcogenide (TMD) or black phosphorus. However, the disclosure is not limited thereto.

TMD is a 2D material having semiconductor properties, and is a compound of a transition metal and a chalcogen element. Here, the transition metal may include, for example, at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Co, Tc, or Re, and the chalcogen element may include, for example, at least one of S, Se, or Te. As a specific example, TMD may include MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReSe2, etc. However, the disclosure is not limited thereto. Black phosphorus is a semiconductor material having a structure in which phosphorus (P) atoms are two-dimensionally combined.

The 2D semiconductor material may be doped with a p-type dopant or an n- type dopant to control mobility. The 2D material layer110may have a monolayer or multilayer structure, where each layer may have an atomic level thickness. The 2D material layer110may include, for example, one to ten layers. As a specific example, the 2D material layer110may include one to five layers. However, the disclosure is not limited thereto.

The 2D material layer110may include a first region110aand second regions110bprovided on both sides of the first region110a.The first region110amay be located in the center of the 2D material layer110. According to an embodiment, the first region110amay be a channel region corresponding to a gate electrode160to be described below. The second regions110bmay be respectively located on both sides of the 2D material layer110. According to an embodiment, the second region110bmay be a source region and a drain region respectively provided to correspond to a source electrode151and a drain electrode152to be described below.

Graphene layers130may be disposed on both sides of a gate insulating layer140, and may be disposed to cover a part of a sheet member111and a protrusion112included in the 2D material layer110. According to an embodiment, the graphene layers130may be disposed in the second regions110b respectively located on both sides of the 2D material layer110with the gate insulating layer140disposed therebetween. Graphene included in the graphene layers130, according to an embodiment, may be a stable 2D material having one atomic layer. As an example, graphene included in the graphene layers130may include crystals with the size equal to or greater than about 0.5 nm and equal to or smaller than about 500 nm. In addition, in the graphene, a ratio of carbons having a sp2 combination structure with respect to all carbons may be equal to or greater than about 50% and equal to or less than about 99%. In addition, graphene may include hydrogen equal to or greater than about 1 at % and equal to or smaller than about 20 at %. In addition, graphene may have a density equal to or greater than about 1.6 g/cc and equal to or smaller than about 2.1 g/cc. In addition, graphene very easily grows one-dimensionally or two-dimensionally because graphene includes only carbon which is a relatively lightweight element. Accordingly, the graphene layers130may grow in one or more directions from one surface of the 2D material layer110disposed in the second region110b, for example, the source region and the drain region.

The graphene layers130according to an embodiment may include low temperature chemical vapor deposition (LTCVD), inductively coupled plasma- chemical vapor deposition (ICP-CVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), metal organic chemical vapor deposition (MOCVD), or plasma-enhanced chemical vapor deposition (PECVD), etc., but are not limited thereto.

As described above, the graphene layers130of sem imetal property may be disposed between the 2D material layer110and the source electrode151and the drain electrode152including a metal material to be described below, and thus, Fermi-level pinning of the 2D material layer120may be limited and/or suppressed. Accordingly, the contact resistance may be reduced in the second region110bof the 2D material layer110, that is, the source region and the drain region.

The gate insulating layer140and a gate electrode160may be sequentially stacked on the first region110aof the 2D material layer110. The gate insulating layer140may include, for example, silicon nitride, etc., but is not limited thereto.

The gate electrode160may include a metal material or a conductive oxide. Here, the metal material may include, for example, at least one selected from the group consisting of Au, Ti, TiN, TaN, W, Mo, WN, Pt, and Ni. In addition, the conductive oxide may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), etc. However, this is merely an example.

The source electrode151and the drain electrode152are respectively provided on both sides of the gate electrode160. The source electrode151and the drain electrode152are provided in the second region110bof the 2D material layer110, that is, the source region and the drain region. Here, the source electrode151may be provided to contact the source region of the 2D material layer110, and the drain electrode152may be provided to contact the drain region of the 2D material layer110. The source electrode151and the drain electrode152may include, for example, a metal material having excellent electrical conductivity such as Ag, Au, Pt, or Cu, but are not limited thereto.

In the Si-based semiconductor device of the related art, as the channel thickness decreases, the mobility decreases, the threshold voltage distribution increases, and as the channel length decreases, the performance degradation due to the channel effect is severe, and thus, there is a limit to reducing the size of the semiconductor device.

The semiconductor device100according to example embodiments may have excellent performance even at a thin thickness equal to or less than 1 nm by using a 2D semiconductor material as a channel, and may also reduce the short channel effect, thereby overcoming the limitation of performance degradation due to the miniaturization of the semiconductor device100.

The 2D material layer110according to an embodiment may include the sheet member111and the protrusion112disposed on one surface of the sheet member111. The sheet member111according to an embodiment may have a sheet shape extending along one plane (XY plane). The sheet member111may include, for example, one to ten layers. As a specific example, the sheet member111may include one to five layers. However, the disclosure is not limited thereto.

The protrusion112may extend from one surface of the sheet member111in one direction (Z direction) perpendicular to one plane (XY plane). According to an embodiment, the protrusion112may be formed as a single protrusion or a plurality of protrusions. As an example, the protrusion112may be disposed to have a shape having a certain constant pattern. However, the disclosure is not limited thereto, and the protrusion112may be disposed to have a shape having an irregular pattern. According to an embodiment, the sheet member111and the protrusion112may be integrally formed. As another example, the sheet member111and the protrusion112may be a combination structure in which separate structures are combined. Also, according to an amendment, the sheet member111and the protrusion112may include the same 2D material. However, the disclosure is not limited thereto, and the sheet member111and the protrusion112may include different 2D materials.

According to an embodiment, the protrusion112may extend in one direction (X direction or Y direction). When a plurality of protrusions112extending in one direction (X direction or Y direction) are disposed on one surface of the sheet member111, a trench shape may be disposed in one surface of the sheet member111. In addition, according to another example, when the plurality of protrusions112extending in one direction (X direction or Y direction) are disposed on one surface of the sheet member111, a grid shape having a certain pattern may be disposed on one surface of the sheet member111. In addition, according to another example, when the plurality of protrusions112are disposed to be spaced apart from each other on one surface of the sheet member111, a protruding structure having a certain pattern may be disposed on one surface of the sheet member111.

According to an embodiment, the protrusion112may be formed to have a certain pattern on an upper portion of the sheet member111using a certain pattern mask process and an etching process. Also, according to another example, the protrusion112may be additionally deposited on a certain pattern region of the sheet member111using a certain process. Accordingly, the protrusion112may be formed to have a certain pattern on the upper portion of the sheet member111. However, the disclosure is not limited thereto, and one or more protrusions112having an irregular pattern may be formed on one surface of the sheet member111in a process of manufacturing the sheet member111.

As described above, the graphene included in the graphene layer130may include only carbon, which is a relatively lightweight element, and may grow very easily one-dimensionally or two-dimensionally. According to an embodiment, the graphene layers130may grow in one or more directions from the surface of the 2D material layer110. As an example, the graphene layers130may grow such that a horizontal junction is formed in a first direction Lz with an upper surface of the sheet member111extending along one plane (XY plane). In addition, the graphene layers130may grow such that a vertical junction is formed with the protrusion112in one direction (Z direction) perpendicular to one plane (XY plane). For example, when the cross-section of the protrusion112has a rectangular shape inFIG.2, the graphene layer130may grow in the first direction Lz to form a horizontal junction with the upper surface of the sheet member111and an upper surface1120of the protrusion112. In addition, the graphene layer130may grow in a second direction Lx to form a vertical junction with a side surface1121of the protrusion112. Accordingly, the graphene layers130may be disposed on a part of the sheet member111and the upper portion of the protrusion112. In the embodiment described above, the protrusion112has been described to have a rectangular cross-section, but the disclosure is not limited thereto. As an example, when the protrusion112has a three-dimensional (3D) arbitrary shape, the graphene layers130may grow from one surface of the sheet member111and the surface of the protrusion112in one or more directions.

According to an embodiment, the 2D material layer110and the graphene layer130may be disposed together in a mixing region M in one direction (Z direction) perpendicular to one plane (XY plane). As described above, the graphene layer130may grow from the surfaces of the sheet member111and the protrusion112. Accordingly, the graphene layers130may be disposed around the protrusion112extending in one direction (Z direction) perpendicular to one plane (XY plane). As an example, the mixing region M may include a region of one or more layers and five or less layers. Also, as an example, the content of graphene in the mixing region M may be equal to or greater than about 20 vol % and equal to or smaller than about 80 vol %.

As described above, the 2D material layer110includes the sheet member111extending in one plane (XY plane) and the protrusion112extending in one direction (Z direction) perpendicular to one plane (XY plane), and thus, the graphene layers130may grow in one or more directions. Accordingly, a contact region between the 2D material layer110and the graphene layers130may increase, and the contact resistance in the second region110bof the 2D material layer110, that is, the source region and the drain region, may be reduced.

FIG.3is a cross-sectional view of a semiconductor device according to another embodiment. Hereinafter, differences from the embodiment described above are mainly described.

Referring toFIG.3, a 2D material layer210according to an embodiment may include a sheet member211having different thicknesses according to regions. According to an embodiment, the sheet member211may extend along one plane (XY plane). In this regard, the sheet member211disposed in a first region210athat is a channel region may have a first thickness h1in one direction (Z direction). Also, the sheet member211disposed in a second region210bthat is a source/drain region may have a second thickness h2different from the first thickness h1in one direction (Z direction). According to an embodiment, the second thickness h2may exceed the first thickness h1. A protrusion212and a graphene layer230included in the 2D material layer210have been described above, and thus, detailed descriptions thereof are omitted.

In the embodiment, the sheet member211may have a greater thickness in the second region210b(the source/drain region) than the first region210a(the channel region) of the 2D material layer210. Specifically, the sheet member211disposed in the source/drain regions210aand210bin which the source/drain electrodes151and152are disposed may have a relatively great thickness. The sheet member211of a greater thickness may be disposed in the second region210bthrough an additional deposition process. Accordingly, the contact resistance between the source/drain electrodes151and152and the source/drain region may be further reduced.

FIG.4is a cross-sectional view of a semiconductor device according to another embodiment. Hereinafter, differences from the embodiment described above are mainly described.

Referring toFIG.4, a 2D material layer310may include a first region310aand second regions310bprovided on both sides of the first region310a. The first region310amay be located in the center of the 2D material layer310. According to an embodiment, the first region310amay be a channel region corresponding to a gate electrode360. The second regions310bmay be respectively located on both sides of the 2D material layer310. According to an embodiment, the second regions310bmay correspond to regions between a source electrode351and a gate electrode360and between a drain electrode352and the gate electrode360.

According to an embodiment, spacers353may be disposed on the second regions310bcorresponding to the regions between the source/drain electrodes351and352and the gate electrode360. The 2D material layer310according to an embodiment may include a sheet member311extending along the first region310aand the second region310balong one plane (XY plane) and a protrusion312disposed on the second region310b. In this regard, the protrusion312may be disposed on lower portion of the spacer353.

According to an embodiment, the graphene layers330may extend along a part of the sheet member311and a surface of the protrusion312in the second region310b. Accordingly, the graphene layer330may be disposed between the spacer353and the 2D material layer310, for example, a part of the sheet member311and the protrusion312in the second region310b. Also, the graphene layers330may extend to source/drain regions in which the source electrode351and the drain electrode352are disposed.

In the embodiment, resistance may increase between the source/drain electrodes351and352on which the spacers353are disposed and the gate electrode360. The 2D material layer310including the protrusion312between the source/drain electrodes351and352and the gate electrode360may be disposed, and thus, the entire resistance of the semiconductor device may be further reduced.

Hereinafter, a method of manufacturing the semiconductor device100according to the embodiment described above is described.FIGS.5A to5Dare diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment.

Referring toFIG.5A, the 2D material layer110including the sheet member111extending along one plane (XY plane) and the protrusion112extending in one direction (Z direction) perpendicular to one plane (XY plane) is formed on the substrate101. Here, the 2D material layer110includes a 2D semiconductor material having a polycrystalline structure. The substrate101may include various materials such as a semiconductor material, an insulating material, and a metal material.

The 2D semiconductor material may include a material having a bandgap equal to or greater than about 0.5 eV and equal to or smaller than 3.0 eV. For example, the 2D semiconductor material may include TMD or black phosphorus. However, the disclosure is not limited thereto.

TMD is a 2D material having semiconductor properties, and is a compound of a transition metal and a chalcogen element. Here, the transition metal may include, for example, at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Co, Tc, or Re, and the chalcogen element may include, for example, at least one of S, Se, or Te. As a specific example, TMD may include MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReSe2, etc. However, the disclosure is not limited thereto. Black phosphorus is a semiconductor material having a structure in which phosphorus (P) atoms are two-dimensionally combined. The 2D semiconductor material may be doped with a p-type dopant or an n-type dopant to control mobility.

The 2D material layer110may have a monolayer or multilayer structure, where each layer may have an atomic level thickness. The 2D material layer110may include, for example, one to ten layers. As a specific example, the 2D material layer110may include one to five layers. However, the disclosure is not limited thereto.

The sheet member112according to an embodiment may be formed by depositing and growing the 2D semiconductor material on a surface of the substrate101. The deposition of the 2D semiconductor material may be performed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., but this is merely an example.

According to an embodiment, the protrusion112may be formed to have a certain pattern on an upper portion of the sheet member111using a certain pattern mask process and an etching process. Also, according to another example, the protrusion112may be additionally deposited on a certain pattern region of the sheet member111using a certain process. Accordingly, the protrusion112may be formed to have a certain pattern on the upper portion of the sheet member111. However, the disclosure is not limited thereto, and one or more protrusions112having an irregular pattern may be formed on one surface of the sheet member111in a process of manufacturing the sheet member111.

Referring toFIG.5B, the graphene layers130may be formed to cover a part of the sheet member111and the protrusion112. According to an embodiment, the graphene layers130may be disposed in the second regions110brespectively located on both sides of the 2D material layer110. In this regard, graphene included in the graphene layers130may grow in one or more directions from a part of the sheet member111and a circumference of the protrusion112.

As an example, the graphene layers130may grow such that a horizontal junction is formed in the first direction Lz with an upper surface of the sheet member111extending along one plane (XY plane). In addition, the graphene layers130may grow such that a vertical junction is formed with the protrusion112in one direction (Z direction) perpendicular to one plane (XY plane). Accordingly, the mixing region M in which the 2D material layer110and the graphene layers130coexist may be formed. As an example, the mixing region M may include a region of one or more layers and five or less layers. Also, as an example, the content of graphene in the mixing region M may be equal to or greater than about 20 vol % and equal to or smaller than about 80 vol %.

The graphene layers130according to an embodiment may be formed using low temperature chemical vapor deposition (LTCVD), inductively coupled plasma- chemical vapor deposition (ICP-CVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), metal organic chemical vapor deposition (MOCVD), or plasma-enhanced chemical vapor deposition (PECVD), etc., but are not limited thereto.

Referring toFIG.5C, the gate insulating layer140is formed in the first region110aof the 2D material layer110. The gate insulating layer140may include, for example, silicon nitride, etc., but is not limited thereto.

Referring toFIG.5D, the gate electrode160is deposited on the gate insulating layer140, and a source electrode and a drain electrode are deposited on the second region110bof the 2D material layer110. The gate electrode160may be provided on the first region110aof the 2D material layer110. The source electrode151and the drain electrode152are provided in the second region110bof the 2D material layer110, that is, the source region and the drain region. The source electrode151may be provided to contact the source region of the 2D material layer110, and the drain electrode152may be provided to contact the drain region of the 2D material layer110. The source electrode151and the drain electrode152may be spaced apart from each other on the 2D material layer110. The gate electrode160may be spaced apart from the source electrode151and the drain electrode152.

In the embodiments described above, the semiconductor devices100to300having a sheet channel structure have been described. However, the disclosure is not limited thereto, and for example, a semiconductor device (FinFET) having a Fin channel structure or a semiconductor device (multi bridge channel FET (MBCFET)) having a gate-all-around channel structure may be provided.

FIG.6is a perspective view illustrating a semiconductor device according to another embodiment, andFIG.7is a cross-sectional view taken along line A-A′ ofFIG.6.

Referring toFIGS.6and7, an insulator505may be provided on a substrate501perpendicular to the substrate501, and a 2D material layer510may be disposed as a channel layer to cover the insulator505. Here, the 2D material layer510may have a fin-shape. The 2D material layer510according to an embodiment may include a first region510aand second regions510bprovided on both sides of the first region510a. The first region510amay be a channel region located in the center of the 2D material layer510. The second regions510bmay be source/drain regions located on both sides of the 2D material layer510.

As an example, the 2D material layer510may include a sheet member511extending to cover the insulator505and a protrusion512formed in the second regions510b. The graphene layer530according to an embodiment may be disposed to cover the sheet member511and the protrusion512in the second regions510b. The 2D material layer510including the sheet member511and the protrusion512and the graphene layer530have been described above, and thus, detailed descriptions thereof are omitted.

A gate insulating layer540is provided in a first region510aof the 2D material layer510, and a gate electrode560is provided in the gate insulating layer540. Here, the gate insulating layer540may be provided to surround the graphene layer530, specifically, three surfaces of the first region510aof the 2D material layer510, and the gate electrode560may be provided to surround three surfaces of the gate insulating layer540. Meanwhile, although not shown in the drawings, the source and drain electrodes may be provided in the second regions510bof the 2D material layer510.

FIG.8is a perspective view illustrating a semiconductor device according to another embodiment, andFIG.9is a cross-sectional view taken along line B-B′ ofFIG.8.

Referring toFIGS.8and9, one or more 2D material layers610are disposed on an upper portion of a substrate601to be spaced apart from the substrate601. Here, each of the 2D material layers610may have a sheet shape disposed in parallel on the substrate601.FIGS.8and9illustrate the two 2D material layers610vertically disposed on the upper portion of the substrate601.

The 2D material layers610according to an embodiment may include a first region610aand second regions610bprovided on both sides of the first region610a. The first region610amay be a channel region located in the center of the 2D material layer610. The second regions610bmay be source/drain regions located on both sides of the 2D material layer610.

As an example, the 2D material layer610may include a sheet member611extending along one plane (XY plane) and a protrusion612formed on the second regions610b. The graphene layer630according to an embodiment may be disposed to cover the sheet member611and the protrusion612in the second regions610b. The 2D material layer610including the sheet member611and the protrusion612and the graphene layer630have been described above, and thus, detailed descriptions thereof are omitted.

A gate insulating layer640is provided in the first region610aof the 2D material layer610, and a gate electrode660is provided in the gate insulating layer640. Here, the gate insulating layer640is provided to surround the graphene layer630, specifically, four surfaces of the first region610aof the 2D material layer610, and the gate electrode660may be provided to surround four surfaces of the gate insulating layer640. Although not shown in the drawings, the source and drain electrodes may be provided in the second regions610bof the 2D material layer610. Meanwhile, an insulator (not shown) may be disposed on the substrate601in parallel to the substrate601, and the graphene layer630may be provided to surround the insulator.

The semiconductor devices100to600described above may be applied to, for example, a memory device such as a DRAM device. The memory device may have a structure in which each of the semiconductor devices100to600described above is electrically connected to a capacitor. Also, the semiconductor devices100to600may be applied to various electronic devices. For example, the semiconductor devices100to600described above may be used to perform arithmetic operations, execute programs, and maintain temporary data in electronic devices such as a mobile device, a computer, a notebook computer, a sensor, a network device, a neuromorphic device, etc.

FIGS.10and11are conceptual diagrams schematically illustrating an electronic device architecture that may be applied to an electronic device according to an embodiment.

Referring toFIG.10, an electronic device architecture1000may include a memory unit1010, an arithmetic logic unit (ALU)1020, and a control unit1030. The memory unit1010, the ALU1020, and the control unit1030may be electrically connected to each other. For example, the electronic device architecture1000may be implemented as one chip including the memory unit1010, the ALU1020, and the control unit1030.

Specifically, the memory unit1010, the ALU1020, and the control unit1030may be interconnected through a metal line in an on-chip to directly communicate with each other. The memory unit1010, the ALU1020, and the control unit1030may be monolithically integrated on one substrate to configure one chip. Input/output devices2000may be connected to the electronic device architecture (chip)1000.

The ALU1020and the control unit1030may each independently include the semiconductor devices100to600described above, and the memory unit1010may include the semiconductor devices100to600, a capacitor, or a combination thereof. The memory unit1010may include both a main memory and a cache memory. The electronic device architecture (chip)1000may be an on-chip memory processing unit.

Referring toFIG.11, a cache memory1510, an ALU1520, and a control unit1530may configure a central processing unit (CPU)1500. The cache memory1510may be formed as a static random access memory (SRAM), and may include the semiconductor devices100to600described above. Separately from the CPU1500, a main memory1600, an auxiliary storage1700may be provided. The main memory1600may include a dynamic random access memory (DRAM) device. Input/output devices2500may be connected to the CPU1500, main memory1600, and auxiliary storage1700. The auxiliary storage1700may include the semiconductor devices100to600described above.

In some cases, an electronic device architecture may be implemented in a form in which computing unit devices and memory unit devices are adjacent to each other in a single chip without distinction of sub-units. Although the embodiments have been described above, these are merely an example, and various modifications are possible therefrom by those of ordinary skill in the art.

The semiconductor device according to an embodiment may have excellent performance even at a thin thickness equal to or less than 1 nm by using a 2D semiconductor material as a channel layer, and may also reduce a short channel effect, thereby overcoming the limitation of performance degradation due to the miniaturization of the semiconductor device.

In addition, the graphene layers of sem imetal property may be disposed between the 2D material layer configuring the channel layer and the source electrode and the drain electrode including a metal material, and thus, the semiconductor device according to an embodiment may limit and/or suppress Fermi-level pinning of the 2D material layer. Accordingly, the semiconductor device according to an embodiment may reduce the contact resistance in the source region and the drain region of the 2D material layer.

In addition, in the semiconductor device according to an embodiment, the 2D material layer configuring the channel layer has a flat plate structure extending along one plane and the protrusion protruding from one plane, and thus, graphene may grow in a lateral direction of the protrusion provided in the 2D material layer as well as in a vertical direction. Accordingly, the contact region between the graphene layer and the 2D material layer is improved, and thus, the contact resistance in the source region and the drain region of the 2D material layer may be reduced.