Integrated circuit having boosted array voltage and method therefor

An integrated circuit comprises a global power supply conductor, a plurality of circuit blocks, a plurality of voltage converters, and control logic. The global power supply conductor is configured to distribute a supply voltage. The circuit blocks are selectively coupled to the global power supply conductor. The plurality of voltage converters are coupled to the global power supply conductor. An output voltage of individual voltage converters of the plurality of voltage converters are selectively coupled to one or more of the plurality of circuit blocks. The control logic is configured to control the selective coupling of at least one of the supply voltage and the output voltage of individual voltage converters of the plurality of voltage converters to corresponding ones of the plurality of circuit blocks. Also, the control logic controls a magnitude of the output voltage of individual voltage converters of the plurality of voltage converters.

BACKGROUND

This disclosure relates generally to integrated circuits, and more specifically, to an integrated circuit having a boosted array voltage and method therefor.

2. Related Art

Static random access memories (SRAMs) are generally used in applications requiring high speed, such as memory in a data processing system. Each SRAM cell stores one bit of data and is implemented as a pair of cross-coupled inverters. The SRAM cell is only stable in one of two possible voltage levels. The logic state of the cell is determined by whichever of the two inverter outputs is a logic high, and can be made to change states by applying a voltage of sufficient magnitude and duration to the appropriate cell input. The stability of a SRAM cell is an important issue. The SRAM cell must be stable against transients, process variations, soft error, and power supply fluctuations which may cause the cell to inadvertently change logic states. Also, the SRAM cell must provide good stability during read operations without harming the ability to write to the cell.

However, today's integrated circuits are required to operate at increasingly lower power supply voltages. Also, logic circuits on an integrated circuit can generally operate with lower supply voltages than SRAM arrays. The lower power supply voltages can reduce the stability of the SRAM cell. Also, SRAM cells operating at the lower supply voltages are more susceptible to soft error and process variations. In addition, production yields can be reduced because fewer cells will operate reliably at the reduced voltages One way to solve the above problems is to operate the memory array at a higher voltage than the rest of the integrated circuit. However, operating the SRAM arrays at a higher voltage can consume more power.

Therefore, what is needed is an integrated circuit and method that solves the above problems.

DETAILED DESCRIPTION

Generally, there is provided, an integrated circuit having logic circuits and memory circuits. In one embodiment, the integrated circuit is a system on a chip (SOC). A charge pump and voltage detector is associated with each memory array. The charge pumps are each independently controlled to selectively provide a boosted supply voltage to supply voltage terminals of the memory cells. The memory arrays can be selectively coupled to receive a boosted supply voltage or a normal supply voltage. Also, a voltage detector is coupled to an output of each of the charge pumps to detect the boosted supply voltage. In response to detecting that the boosted supply voltage is below a predetermined voltage, the voltage detector causes the charge pump to increase the supply voltage of a memory array associated with the charge pump.

By independently controlling the charge pumps, selected memory arrays can receive an adjustable boosted supply voltage as needed. The selection of memory arrays requiring a boosted supply voltage can be determined by monitoring the low voltage production yield of memory cells contained within the memory arrays. The low voltage production yield can be monitored immediately following fabrication of the integrated circuit or even by periodic testing of the integrated circuits after it has already been shipped to the customer. Those memory arrays that show bitcell failures at a relatively low supply voltage are likely to benefit from a local power supply which is boosted with respect to the normal supply voltage. However, memory arrays that do not fail at the low supply voltage are unlikely to benefit from a boosted supply and it is preferred that these memory arrays receive a normal supply voltage. This approach can improve production yields while minimizing the overall power consumed by the integrated circuit. It is understood that “low voltage” can also mean the nominal supply voltage of the integrated circuit.

The integrated circuit described herein can be formed on any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.

The conductors as discussed herein may be illustrated or described in reference to being a single conductor, a plurality of conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, separate unidirectional conductors may be used rather than bidirectional conductors and vice versa. Also, a plurality of conductors may be replaced with a single conductor that transfers multiple signals serially or in a time multiplexed manner. Likewise, single conductors carrying multiple signals may be separated out into various different conductors carrying subsets of these signals. Therefore, many options exist for transferring signals.

In one aspect, there is provided, an integrated circuit comprising: a global power supply conductor configured to distribute a supply voltage; a plurality of circuit blocks, the circuit blocks being selectively coupled to the global power supply conductor; a plurality of voltage converters coupled to the global power supply conductor, wherein an output voltage of individual voltage converters of the plurality of voltage converters are selectively coupled to one or more circuit blocks of the plurality of circuit blocks; and control logic configured to (i) control the selective coupling of at least one of (i)(a) the supply voltage and (i)(b) the output voltage of individual voltage converters of the plurality of voltage converters to corresponding ones of the plurality of circuit blocks, and (ii) control a magnitude of the output voltage of individual voltage converters of the plurality of voltage converters. The control logic may independently control the magnitude of the output voltage of individual voltage converters of the plurality of voltage converters according to local power supply requirements of corresponding one or more selectively coupled circuit blocks. The individual voltage converters may be located physically proximate to the corresponding one or more selectively coupled circuit blocks, where physically proximate may further comprise being immediately adjacent. The supply voltage may comprise a first voltage, and the output voltage of an individual voltage converter may comprise a second voltage. The second voltage may comprise a magnitude that is different than a magnitude of the first voltage. The plurality of voltage converters may comprise charge pumps. At least one of the circuit blocks may include a charge storage capacitor, and wherein the charge storage capacitor may be coupled to the output voltage of a corresponding charge pump of the plurality of charge pumps. The output voltage of individual charge pumps may comprise a voltage magnitude greater than a magnitude of the supply voltage. The plurality of voltage converters may comprise voltage regulators. The circuit blocks may comprise memory circuits, the memory circuits including at least one memory array. The memory circuits may comprise static random access memory (SRAM). The control logic may include a control storage element having a number of bit fields, each bit field including one or more control bits adapted to provide a desired control of (i) the selective coupling and (ii) the magnitude of output voltage of individual voltage converters. The control logic may further comprise a voltage detector per at least one circuit block of the plurality of circuit blocks, wherein the voltage detector is responsive to a control input and an input voltage to the corresponding at least one circuit block for producing a magnitude control signal that is input to the corresponding voltage converter, the integrated circuit further comprise at least one multiplexer per one or more circuit blocks of the plurality of circuit blocks, the at least one multiplexer having first and second inputs and an output, the first input being coupled to the global power supply conductor, the second input being coupled to the output voltage of an individual voltage converter of a corresponding one or more circuit blocks of the plurality of circuit blocks, and the output being coupled to the corresponding one or more circuit blocks of the plurality of circuit blocks.

In another aspect, there is provided, an integrated circuit comprising: a global power supply conductor configured to distribute a supply voltage; a plurality of circuit blocks, the circuit blocks being selectively coupled to the global power supply conductor; a plurality of voltage converters coupled to the global power supply conductor, wherein an output voltage of individual voltage converters of the plurality of voltage converters are selectively coupled to one or more circuit blocks of the plurality of circuit blocks; and control logic configured to (i) control the selective coupling of at least one of (i)(a) the supply voltage and (i)(b) the output voltage of individual voltage converters of the plurality of voltage converters to corresponding ones of the plurality of circuit blocks, and (ii) control a magnitude of the output voltage of individual voltage converters of the plurality of voltage converters, wherein the control logic independently controls the magnitude of the output voltage of individual voltage converters of the plurality of voltage converters according to local power supply requirements of corresponding one or more selectively coupled circuit blocks, the control logic including a control storage element having a number of bit fields, each bit field including one or more control bits adapted to provide a desired control of (i) the selective coupling and (ii) the magnitude of output voltage of individual voltage converters.

In yet another aspect, there is provided, a method for providing local supply voltages in an integrated circuit comprising: configuring a global power supply conductor to distribute a supply voltage; selectively coupling a plurality of circuit blocks to the global power supply conductor; coupling a plurality of voltage converters to the global power supply conductor, wherein an output voltage of individual voltage converters of the plurality of voltage converters are selectively coupled to one or more circuit blocks of the plurality of circuit blocks; and controlling, via control logic (i) the selective coupling of at least one of (i)(a) the supply voltage and (i)(b) the output voltage of individual voltage converters of the plurality of voltage converters to corresponding ones of the plurality of circuit blocks, and (ii) a magnitude of the output voltage of individual voltage converters of the plurality of voltage converters, wherein controlling includes independently controlling the magnitude of the output voltage of individual voltage converters of the plurality of voltage converters according to local power supply requirements of corresponding one or more selectively coupled circuit blocks. The step of controlling may further comprise independently controlling the magnitude of the output voltage of individual voltage converters of the plurality of voltage converters according to local power supply requirements of corresponding one or more selectively coupled circuit blocks, wherein the control logic includes a control storage element having a number of bit fields, each bit field including one or more control bits adapted to provide a desired control of (i) the selective coupling and (ii) the magnitude of output voltage of individual voltage converters. The plurality of voltage converters may comprise charge pumps, wherein at least one of the circuit blocks includes a charge storage capacitor, and wherein the charge storage capacitor is coupled to the output voltage of a corresponding charge pump of the plurality of charge pumps, and wherein the output voltage of individual charge pumps comprises a boost voltage having a magnitude greater than a magnitude of the supply voltage.

FIG. 1illustrates, in block diagram form, an integrated circuit10according to an embodiment. Generally, integrated circuit10includes circuit blocks comprising a plurality of logic blocks and a plurality of memory blocks. More specifically, integrated circuit10includes memory blocks14-20, logic blocks21-23, and voltage converters25-29. In the illustrated embodiment, voltage converters25-29comprise charge pumps. In other embodiments, the voltage converters may be voltage regulators. A power supply voltage conductor is formed as a power supply grid12. Power supply grid12is formed in one or more metal layers on the integrated circuit to provide a power supply voltage VDD to each of the plurality of memory blocks14-20, each of logic blocks21-23, and each of the charge pumps25-29. Logic circuits21-23can be any type of digital or analog circuits, such as for example, analog-to-digital converters, logic gates, arithmetic units, amplifiers, and the like. Each of charge pumps25-29is associated with one or more circuits, such as for example, memories14-20. For example, charge pump25is selectively coupled to provide boosted supply voltage VBOOST0to memories14and15in response to control signals from control logic including registers50Charge pump26is coupled to provide boosted supply voltage VBOOST1to memory16. Charge pump27is coupled to provide boosted supply voltage VBOOST2to memories17and18. Charge pump28is coupled to provide boosted supply voltage VBOOST3to memories19and20. A redundant charge pump29is coupled to memory arrays14and15. Either of charge pumps25or29can be used to provide boosted supply voltage VBOOST0. In the event that charge pump25is discovered to be non-functional, redundant charge pump29can be substituted by, for example, blowing a fuse, setting a bit in a control register, programming a bit in a non-volatile memory, or the like. In another embodiment, both charge pumps may be used at the same time to increase the charging current if the current from one charge pump is not adequate. Each of the charge pumps are located physically proximate to one or more corresponding memories and preferably immediately adjacent.

FIG. 2illustrates, in block diagram form, a portion30of integrated circuit10ofFIG. 1. Portion30includes memory15, charge pump25, voltage detector40, multiplexers35and36, capacitor45, and control storage element50. In the illustrated embodiment, control storage element50is a register and provides a selective coupling of a boosted voltage to a corresponding memory and a magnitude of the boosted voltage. Memory15includes memory array33, column logic32, and word line drivers34. For the purposes of simplicity and clarity, memory15has been greatly simplified. In a preferred embodiment, memory array33is a conventional SRAM array and includes a plurality of SRAM cells organized in rows and columns, where a column includes a bit line pair and all of the memory cells coupled to the bit line pair and a row includes a word line and all of the memory cells coupled to the word line. In another embodiment, the memory arrays may include any type of memory that benefits from a boosted supply voltage as compared to other circuits on the integrated circuit. Word line drivers34receive a plurality of row address signals labeled “ROW ADDRESS”, and in response, selected one of the word lines during a write or read access to memory array33. Column logic32receives a column address labeled “COLUMN ADDRESS” and selects a column during a read or write access. The column logic includes column decoders, sense amplifiers, precharge and equalization circuits, bit line loads, and other circuits necessary for accessing memory array33. In the illustrated embodiment, all of the other memories in integrated circuit10are similar to memory15. However, in other embodiments, there could be memories that are unaffiliated with any boost circuitry. Multiplexer35selectively couples one of either boosted output voltage VBOOST0or VDD to memory array33in response to receiving a predetermined bit from CONTROL0. Output voltage VBOOST0is at a different magnitude than power supply voltage VDD, and preferably VBOOST0has a greater magnitude than VDD. Multiplexer36selectively couples one or either VBOOST0or VDD to word line drivers34. Boosting the word line above the supply voltage during an access to the memory array can reduce the time it takes to access the memory for a read or write operation. In another embodiment, the boosted supply voltage VBOOST0may be provided only to columns selected for a read operation as determined by the column address. Columns selected for a write operation are supplied by VDD. In yet another embodiment, all columns receive VDD during a standby operation where the array is neither being read or written.

Register50includes a plurality of bit fields for storing logic bits for controlling the operation of a plurality of charge pumps such as charge pumps25-29. For example, bit field52includes one or more bits coupled to provide control signals CONTROL0to voltage detector40. Also, bit field54includes one or more bits coupled to provide control signals CONTROL1to another memory. In addition, bit field56includes one or more bits coupled to provide control signals CONTROL N to another memory of the integrated circuit.

Charge pump25is a conventional charge pump and includes ring oscillator42and pump stages44. Ring oscillator42generates a clock signal labeled “PUMP CLK” in response to the supply voltage VDD. The pump clock is turned on and off by control signal PUMP CONTROL from voltage detector40. Pump stages44includes one or more pump stages to pump up the supply voltage VDD from a lower voltage to a higher voltage VBOOST0. A magnitude of the output voltage VBOOST0is controlled by controlling a frequency of ring oscillator42. For example, pump stages44may receive VDD as an input of about 0.6 volts and provide VBOOST0at about 0.9 volts. Capacitor45has a first plate electrode coupled to the output of charge pump25, and a second plate electrode coupled to VSS. Capacitor45functions to maintain the voltage VBOOST0provided to the input of multiplexers35and36.

In register50one or more bits of bit field52are used to selectively enable and control the output of charge pump25. Register50may be programmable by a user or a processor. Register50may also be programmable by either an external tester or internal test logic that identifies the memory arrays which would benefit from a boosted supply voltage in order to improve low voltage production yield. Register50includes bit fields for controlling each individual charge pump or group of charge pumps according to local power supply requirements of corresponding memories coupled to the charge pumps. Also, one of more bits of bit field52is used to control multiplexer35to control whether memory array33is powered by boosted voltage VBOOST0or by supply voltage VDD. For example, charge pump25may be disabled and multiplexer35used to decouple boosted voltage VBOOST0and couple power supply voltage VDD to a power supply voltage terminal of memory array33. In the case where memory array33includes a plurality of conventional six transistor SRAM cells, the boosted voltage VBOOST0is provided to supply terminals of each cell. Also, one or more bits of bit field52may be used to selectively control multiplexer36to selectively couple one of boosted voltage VBOOST0and power supply voltage VDD to word line drivers34during, for example, a read access or a write access to memory array33. That is, when memory array33is being read, a selected word line receives boosted voltage VBOOST0instead of the power supply voltage VDD. The boosted word line voltage improves a write margin and the speed of writing to the selected cell. In addition, in a preferred embodiment, bit field52includes one or more bits for independently controlling the output voltage level, or magnitude, of VBOOST0as discussed in connection withFIG. 3below. Also, one or more bits of bit field52are used for controlling the frequency of PUMP CLK produced by ring oscillator42. In other embodiments, register50can be implemented using any type of memory device or control logic. For example, register50may be any type of volatile or non-volatile random access memory, such as for example, flash, dynamic random access memory (DRAM), or SRAM. Also, register50may be implemented as fuses or may be external to integrated circuit10.

In the illustrated embodiment, charge pump25is used to provide the boosted supply voltage. In another embodiment, charge pump25can be replaced with another type of voltage converter, such as for example, a voltage regulator. Also, in an effort to prevent an over-voltage problem, a clamp circuit (not shown) may be included with charge pump25to clamp VBOOST0below or equal to a predetermined voltage.

FIG. 3illustrates, in partial block diagram form and partial schematic diagram form, voltage detector40. Voltage detector40includes bias generator64, bias generator66, P-channel transistor60, N-channel transistor62, and inverter68. Bias generator64has a plurality of input terminals for receiving control bits labeled “CONTROL0P”, a supply voltage terminal labeled “VDD”, and an output terminal for providing a bias voltage labeled “PBIAS”. Bias generator66has a plurality of input terminals for receiving control bits labeled “CONTROL0N”, a supply voltage terminal labeled “VDD”, and an output terminal for providing a bias voltage labeled “NBIAS”. P-channel transistor60has a first current electrode (source) for receiving array supply voltage VARRAY, a control electrode (gate) coupled to receive bias voltage PBIAS, and a second current electrode (drain). N-channel transistor62has a first current electrode (DRAIN) coupled to the second current electrode of transistor60at a node labeled N1, a control electrode (gate) coupled to receive bias voltage NBIAS, and a second current electrode coupled to a power supply voltage terminal labeled “VSS”. Transistor60and transistor62form an inverter with an output node N1. In the illustrated embodiment, VDD is a positive voltage and VSS is ground. In other embodiments, the power supply voltage can be different. Inverter68has an input coupled to the second current electrode of transistor60, and an output for providing pump control signal PUMP CONTROL to an input of ring oscillator42.

In operation, control bits CONTROL0P controls the voltage of bias voltage PBIAS and control bits CONTROL0N controls the voltage of bias voltage NBIAS. Control bits CONTROL0P and CONTROL0N are provided as part of control signals CONTROL0from register bit field52inFIG. 2. In the illustrated embodiment, CONTROL0P includes four bits and CONTROL0N includes four bits. In other embodiments, the number of bits can be different. The bias voltages provided to the gates of transistors60and62determine their relative conductances thereby determining their trip point for a given magnitude of VARRAY. Hence, the voltage at node N1is determined by NBIAS, PBIAS, and VARRAY. The level of the voltage at node N1determines the logic state of the output of inverter68. If the voltage provided at node N1is low, indicating that the array voltage is low, then the output of inverter68is a logic high, causing pump signal PUMP CONTROL to enable the operation of charge pump25. If the voltage at node N1is high, indicating that the array voltage is high, then the output of inverter68is a logic low, causing pump signal PUMP CONTROL to disable the operation of charge pump25. The bias voltages to transistors60and62determine the voltage at node N1, and thus the point at which charge pump25is turned on.

FIG. 4illustrates, in schematic diagram form, one embodiment of PBIAS generator64ofFIG. 3. Note thatFIG. 4illustrates only one embodiment of PBIAS generator64. Those skilled in the art will know there are other ways to generate a bias voltage. PBIAS generator64includes a plurality of parallel-connected P-channel transistors, including parallel-connected transistors70and72, coupled between VDD and an output terminal for providing PBIAS. NBIAS generator66is implemented similarly. Each control gate of the plurality of parallel-connected transistors is coupled to receive one bit of multi-bit control signals CONTROL0P1-CONTROL0PM. For example, a gate of transistor70is coupled to receive CONTROL0P1and a gate of transistor72is coupled to receive CONTROL0PM. N-channel transistor74has a drain and a gate coupled to the output terminal for providing PBIAS, and a source coupled to VSS. The voltage PBIAS is controlled by controlling the number of parallel-connected P-channel transistors that are conductive. Increasing the number of conductive P-channel transistors that are conductive increases the voltage of PBIAS. Likewise, decreasing the number of conductive P-channel transistors decreases the voltage of PBIAS. Alternatively, transistors70and72might be sized differently such that they possess different conductances. Control signals CONTROL0P1and CONTROL0PM are then used to select either transistor70or transistor72such that the voltage level of PBIAS is changed appropriately.

FIG. 5illustrates a timing diagram of various signals of integrated circuit portion30ofFIG. 2during operation. In response to sensing a drop in array supply voltage VARRAY (not shown inFIG. 5), voltage detector40provides a logic high PUMP CONTROL signal to charge pump25at time T1. The voltage drop of VARRAY may be due to, for example, multiple accesses to memory array33within a short period of time. The logic high PUMP CONTROL signal increases a frequency of the PUMP CLK signal from ring oscillator42as can be seen inFIG. 5between times T1and T2. At time T2, the array voltage VARRAY is high enough to cause PUMP CONTROL to become a logic low, thus turning off ring oscillator42. Between times T3and T4, and between times T5and T6, control signal PUMP CONTROL again transitions to a logic high and causes ring oscillator42to provide signal PUMP CLK to cause charge pump25to provide VBOOST0to memory array33via multiplexer35. When the voltage VARRAY is at a predetermined voltage, as determined by control signals CONTROL0from register bit field52, control signal PUMP CONTROL again returns to a logic low to stop charge pump25.

Some of the above embodiments, as applicable, may be implemented using a variety of different information processing systems. For example, althoughFIG. 1and the discussion thereof describe an exemplary integrated circuit, this exemplary integrated circuit is presented merely to provide a useful reference in discussing various aspects of the invention. Of course, the description of the integrated circuit has been simplified for purposes of discussion, and it is just one of many different types of appropriate integrated circuits that may be used in accordance with the invention. Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements.

Also for example, in one embodiment, the illustrated elements of integrated circuit10are circuitry located on a single integrated circuit or within a same device. Alternatively, integrated circuit10may include any number of separate integrated circuits or separate devices interconnected with each other. For example, memory15may be located on a same integrated circuit as memories14and16-20or on a separate integrated circuit.