Half tone display method for a display panel

Kinds of an input video signal is discriminated. Sub-frames are disposed in such an arrangement that a sub-frame corresponding to a most heavy weight bit is located at a central portion of the unit display period, and sub-frames, each of which corresponds to a lighter weight bit than the most heavy weight bit, are disposed at positions before and after the most heavy sub-frame when the input video signal is discriminated as a still picture. Each of sub-frames which correspond to heavy weight bits including a most heavy weight bit is divided into two small sub-frames. The sub-frames are disposed in such an arrangement that small sub-frames corresponding to the most heavy weight bit are located at portions of the unit display period, small sub-frames, each of which corresponds to a lighter weight bit than the most heavy weight bit, at positions before and after the most heavy sub-frame when the input video signal is discriminated as a moving picture.

BACKGROUND OF THE INVENTION 
The present invention relates to a method for displaying half tone for a 
display panel such as a plasma display panel (PDP) and a liquid crystal 
display (LCD) of a matrix display type. In the method, a unit display 
period (one frame or one field) is divided into a plurality of sub-frames 
corresponding to a display tone. The number of display pulses (discharge 
sustaining pulses) of each sub-frame is weighted corresponding to each 
bit. 
Recently, as a display device becomes large in size, thickness of the 
display device is desired to be thin. Therefore, various types of display 
devices of thin thickness are provided. As one of the display devices, an 
ACPDP is known. 
A conventional ACPDP comprises a plurality of data electrodes, and a 
plurality of row electrodes formed in pairs and disposed to intersect the 
data electrodes. A pair of row electrodes form one row (one scanning line) 
of an image. The data electrodes and the row electrodes are covered by 
dielectric layers respectively, at a discharge space. At the intersection 
of each of the data electrodes and each pair of row electrodes, a 
discharge cell (pixel) is formed. 
As a method for displaying an image on the PDP by controlling a tone of the 
image, each frame (field) of a video signal is divided into N pieces of 
sub-frames (sub-fields), and each sub-frame (sub-field) emits the light 
for a time length corresponding to a weight applied to each bit of n-bit 
pixel data (sub-frame method). 
In the method, if a pixel data for each pixel has 6 bits, each frame is 
divided into six sub-frames, SF1, SF2, . . . SF6. The sub-frames SF1 to 
SF6 emit the light by sustaining discharge at 1 time, 2 times, 4 times, 8 
times, 16 times and 32 times, respectively, in order. Thus, the tone of 64 
steps can be obtained by combining the six sub-frames. 
There are two cases in the PDP that, a video signal (interlace video 
signal) produced by the interlace scanning as used in the NTSC system is 
displayed, and that a video signal (non-interlace video signal) produced 
by the non-interlace scanning as used in the personal computer is 
displayed. 
In the NTSC system, the interlace video signal is normally used for 
displaying a moving picture. On the other hand, in the personal computer, 
the non-interlace video signal is used for displaying the computer picture 
image which consists of a still picture without a moving picture or a 
moving picture without a still picture. 
In order to display both of the still picture and the moving picture by the 
half tone display method, since the display order of the sub-frames is 
constant fixed), false contours are recognized irrespective of he still 
picture or the moving picture. 
The false contour of the still picture is a flicker caused by brightness 
fluctuation with time of the same pixel (discharge cell). In the false 
contour of the moving picture, when an image is moved in plane on the PDP, 
false contours of bright stripes or dark stripes are recognized as if the 
tone of the image is lost near the area where the image crosses the border 
at the tone level of the n power of 2. Therefore, the quality of display 
is extremely deteriorated. 
SUMMARY OF THE INVENTION 
An object of the present invention is to provide a half tone display method 
for a display panel which may improve the quality of display in both of 
the still picture and the moving picture. 
According to the present invention, there is provided a half tone display 
method for a display panel, wherein an input video signal is converted to 
pixel data, each of which comprises a plurality of bits, a unit display 
period of the input video signal is divided into a plurality of 
sub-frames, each of the sub-frames has a light emitting period 
corresponding to weight at a corresponding figure of the pixel data. 
The method comprises the steps of discriminating kinds of the input video 
signal, disposing the sub-frames in such an arrangement that a sub-frame 
corresponding to a most heavy weight bit is located at a portion of the 
unit display period, sub-frames, each of which corresponds to a lighter 
weight bit than the most heavy weight bit, at positions before and after 
the most heavy sub-frame when the input video signal is discriminated as a 
still picture, dividing each of sub-frames which correspond to heavy 
weight bits including a most heavy weight bit into small sub-frames, and 
disposing the sub-frames in such an arrangement that small sub-frames 
corresponding to the most heavy weight bit are located at portions of the 
unit display period, small sub-frames, each of which corresponds to a 
lighter weight bit than the most heavy weight bit, at positions before and 
after the most heavy sub-frame when the input video signal is 
discriminated as a moving picture. 
In an aspect of the present invention, the sub-frames are disposed in such 
an arrangement that a sub-frame corresponding to a most heavy weight bit 
is located at a central portion of the unit display period, sub-frames, 
each of which corresponds to a lighter weight bit than the most heavy 
weight bit, at positions before and after the most heavy sub-frame when 
the input video signal is discriminated as a still picture, each of 
sub-frames which correspond to heavy weight bits including a most heavy 
weight bit is divided into two small sub-frames, and the sub-frames are 
disposed in such an arrangement that small sub-frames corresponding to the 
most heavy weight bit are located at central portions of the unit display 
period, small sub-frames, each of which corresponds to a lighter weight 
bit than the most heavy weight bit, are symmetrically disposed at 
positions before and after the most heavy sub-frame in descending order of 
weight when the input video signal is discriminated as a moving picture. 
The display panel is driven by line sequential scanning when the input 
video signal is discriminated as a still picture of non-interlace 
scanning. 
The method further comprises driving neighboring two rows as one unit of 
scanning by line sequential scanning, and shifting the rows scanned at the 
same time by one row electrode in a first field when the input video 
signal is discriminated as a moving of interlace scanning. 
These and other objects and features of the present invention will become 
more apparent from the following detailed description with reference to 
the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
FIG. 1 shows an ACPDP of a reflection type of three-electrode according to 
the present invention. An ACPDP 11 comprises a pair of glass substrates 1 
and 2 disposed opposite to each other, interposing a discharge space 7 
therebetween. The glass substrate 1 as a display portion has row 
electrodes (sustain electrodes) X and Y which are alternately disposed in 
pairs to be parallel with each other at the inside portion thereof. The 
row electrodes X and Y are covered by a dielectric layer 5 for producing 
wall charge. A protection layer 6 made of MgO is coated on the dielectric 
layer 5. 
Each of the row electrodes X and Y comprises a transparent electrode 4 
formed by a transparent conductive film having a large width and bus 
electrode (metallic electrode) 3 formed by a metallic film having a small 
width and layered on the transparent electrode 4. 
On the glass substrate 2 as a rear member, a plurality of elongated 
barriers 10 are provided at the inside portion thereof for defining the 
discharge space 7. The barrier 10 extends in the direction perpendicular 
to the row electrodes X, Y. Between the barriers 10, data electrodes 
(address electrodes) D are formed to intersect the row electrodes X and Y 
of the glass substrate 1. A phosphor layer 8 having a predetermined 
luminous color R, G or B covers each of the data electrodes D and opposite 
side portions of the barrier 10. The discharge space 7 is filled with 
discharge gas consisting of neon mixed with xenon. Thus, a discharge cell 
(pixel) is formed at the intersection of the row electrodes in pairs and 
the data electrodes. 
Referring to FIG. 2 showing a driving system for displaying the half tone 
for the PDP 11, the driving system comprises a video signal discriminating 
circuit 28 applied with an input video signal for determining whether the 
input video signal is for a moving picture or a still picture and 
producing a first discriminating signal. The video signal is further 
determined whether it is produced by interlace scanning or non-interlace 
scanning. The video signal produced by the interlace scanning (as 
aforementioned, the interlace video signal used in the display of the NTSC 
system) is formed by N scanning lines of one frame (for example, 262.5 
lines) at a first horizontal scanning frequency (for example, 15.75 kHz). 
The video signal produced by the non-interlace scanning (as 
aforementioned, the non-interlace video signal used in the display of the 
personal computer) is formed by M scanning lines of one frame (M&gt;N, for 
example, 525 lines) at a second horizontal scanning frequency (for 
example, 31.5 kHz). The video signal discriminating circuit 28 produces a 
second discriminating signal. Furthermore, the video signal discriminating 
circuit 28 detects whether the input video signal is a fast moving picture 
or a slow moving picture when the video signal is a moving picture, and 
produces a moving detection signal. These first and second discriminating 
signals and the moving detection signal are applied to a control circuit 
22. 
Responsive to the first and second discriminating signals and the moving 
detection signal, the control circuit 22 produces a control signal which 
is applied to a frame memory 24. 
The control circuit 22 is further applied with the video signal for 
extracting horizontal and vertical synchronizing signals. The control 
circuit 22 produces various timing signals for generating reset, scanning, 
sustaining and erasing signals corresponding to the horizontal and 
vertical synchronizing signals. The timing signals are applied to row 
electrode drivers 25a and 25b. 
The control circuit 22 further produces clock signals such as a sampling 
clock signal and selection signals. The sampling clock signal is applied 
to an A/D converter 21. 
The A/D converter 21 is further applied with the video signal such as 
interlace or non-interlace video signal and operated for sampling the 
input video signal to obtain a pixel data of n-bit (for example, 8 bits) 
for each pixel corresponding to the sampling clock signal from the control 
circuit 22. The pixel data is applied to a pixel data processing circuit 
23. 
The pixel data processing circuit 23 comprises a pixel data converting 
circuit. The pixel data converting circuit is applied with the clock 
signal, horizontal and vertical synchronizing signals and selection signal 
from the control circuit 22 for producing a false contour correcting pixel 
data. When the pixel data applied to the pixel data processing circuit 23 
is for the moving picture, the circuit is operated to correct a false 
contour of the pixel data for the moving picture and produces a correcting 
pixel data of (n+m) bit (for example, 12 bits) for compensating the false 
contour. The false contour correcting pixel data is applied to a signal 
changeover selecting circuit 27. 
A scanning line interpolation processing circuit 29 is operated to 
interpolate the scanning line of the input pixel data, thereby converting 
the interlace signal into the non-interlace pixel data. The converted 
signal is applied to the signal changeover selecting circuit 27. 
The signal changeover selecting circuit 27 is a relay section and has three 
input terminals a, b and c, and one output terminal d having a movable 
contact 27a. The input terminal a is connected to the A/D converter 21, 
the input terminal b is connected to the pixel data processing circuit 23, 
and the input terminal c is connected to the scanning line interpolation 
processing circuit 29. The output terminal d is connected to the frame 
memory 24. The movable contact 27a is operated by the changeover signal 
from the control circuit 22 for selectively connecting one of the input 
terminals a-c to the output terminal d. 
When the video signal is the non-interlace signal for the still picture or 
the moving picture signal of the slow movement, the movable contact 27a is 
operated to connect to the input terminal a. Thus, the pixel data from the 
A/D converter 21 is applied to the frame memory 24. 
When the video signal is the moving picture signal of the fast movement, 
the movable contact 27a is operated to connect to the input terminal b. 
Thus, the false contour correcting pixel data of the pixel data processing 
circuit 23 is applied to the frame memory 24. 
When the video signal is the interlace signal for the still picture, the 
movable contact 27a is operated to selectively connect to the input 
terminal c. Thus, the scanning line interpolated pixel data from the 
scanning line interpolation processing circuit 29 is applied to the frame 
memory 24. 
The frame memory 24 is further applied with the control signal from the 
control circuit 22 for controlling writing address and reading address 
thereof, thereby changing allotments thereof. 
The frame memory 24 is operated to store the pixel data in order in 
dependency on the write-in control signal from the control circuit 22, and 
to read the pixel data stored therein in dependency on the read-out 
control signal from the control circuit 22. The read-out pixel data is 
applied to a pixel data electrode driver 26. 
The frame memory 24 reads the pixel data of the bit corresponding to each 
sub-frame in order in accordance with the display order of the sub-frame 
as described hereinafter. 
The frame memory 24 has at least a capacity for storing the pixel data for 
one frame of the non-interlace video signal. 
In the PDP 11, a pair of row electrodes X and Y are provided to form one 
row (one scanning line). The row electrodes X1-Xn are connected to the row 
electrode driver 25a. The row electrodes Y1-Yn are connected to the row 
electrode driver 25b. 
The row electrode driver 25a produces a reset pulse for initializing wall 
charges of all of the discharge cells all at once, a scanning pulse 
(selecting and writing pulse or selecting and erasing pulse) for 
selectively forming or erasing the wall charge in dependency on the pixel 
data, thereby selecting a lighted pixel (cell) or unlighted pixel (cell), 
a sustaining pulse for sustaining the lighted pixel or unlighted pixel 
(namely, sustaining the discharge and emission of light), and an erasing 
pulse for erasing the wall charge of the discharge cell, corresponding to 
the timing signals from the control circuit 22. These pulses are applied 
to the row electrodes X1-Xn. The scanning pulse is sequentially applied 
from the row electrode X1 to the row electrode Xn in order. 
The row electrode driver 25b produces a reset pulse for initializing wall 
charges of all of the discharge cells all at once, and a sustaining pulse 
for sustaining the lighted pixel or unlighted pixel (sustaining the 
discharge and emission of light), corresponding to the timing signals from 
the control circuit 22. These reset and sustaining pulses are applied to 
the row electrodes Y1-Yn at the respective timings. 
The pixel data electrode driver 26 is connected to pixel data electrodes 
D1-Dm. The pixel data electrode driver 26 produces a pixel data pulse 
having voltage corresponding to the logic value "1" or "0" of each bit of 
the pixel data corresponding to the sub-frame which is applied from the 
frame memory 24. The pixel data pulse is applied to the pixel data 
electrodes D1-Dm. 
FIG. 3 shows the pixel data converting circuit of the pixel data processing 
circuit 23. The pixel data converting circuit comprises first and second 
converting circuits 31 and 32, and a selector 33. 
The first data converting circuit 31 converts the pixel data Z of 8 bits 
applied from the A/D converter 21 to a correcting pixel data AZ of 12 bits 
of the corresponding luminance level in accordance with a first converting 
table as shown in FIGS. 4a to 7c. The correcting pixel data AZ is applied 
to the selector 33. 
Similarly, the second data converting circuit 32 converts the pixel data Z 
of8 bits to a correcting pixel data BZ of12 bits of the corresponding 
luminance level in accordance with a second converting table of FIGS. 8a 
to 11c. The correcting pixel data BZ is applied to the selector 33. 
The logic value "1" of each bit of the correcting pixel data AZ and BZ 
shown in FIGS. 4a to 7c and FIGS. 8a to 11c indicates the emission of 
light, and the logic value "0 (blank)" indicates the non-emission of 
light. 
The light emitting period and figure position of each sub-frame in FIG. 12 
shows a display period of one frame which is divided into eight sub-frames 
SF0 to SF7 corresponding to each bit figure of the pixel data of 8 bits. 
Then, in the eight sub-frames SF0 to SF7, the sub-frames SF4 to SF7 of 
high-figure 4 bits having the heavy weight are further divided into small 
sub-frames SF4a and SF4b, SF5a and SF5b, SF6a and SF6b, and SF7a and SF7b, 
respectively as shown in FIG. 13. Thus, the frame having twelve sub-frames 
SF0, SF1, SF2, SF3, SF4a, SF4b, SF5a, SF5b, SF6a, SF6b, SF7a, and SF7b is 
formed. This corresponds to twelve bits of pixel data AZ and BZ D0, D1, 
D2, D3, D4, D5, D6, D7, D8, D9, DA and DB. The sub-frames SF0 to SF7b emit 
the light by sustaining discharge at 1 time, 2 times, 4 times, 8 times, 8 
times, 8 times, 16 times, 16 times, 32 times, 32 times, 64 times and 64 
times, respectively, in order. 
The selector 33 selects one of the correcting pixel data AZ and BZ for each 
pixel corresponding to the selection signal from the control circuit 22 
and produces the correcting pixel data which is applied to the frame 
memory 24. 
In the embodiment, two converting patterns (light emitting patterns) are 
provided by the first and second converting tables. Each of the light 
emitting patterns has the same luminance level and the the same light 
emitting period of the sub-frames in one frame. However, the light 
emitting positions of the sub-frames are different from each other. Thus, 
the light emitting pattern is changed for each pixel, thereby reducing the 
false contour. 
The half tone display method employed with the driving system of FIG. 2 
will be described. 
When the non-interlace video signal for the still picture is discriminated, 
the movable contact 27a is connected to the input terminal a in accordance 
with the changeover signal from the control circuit 22. Thus, the pixel 
data of 8 bits of the A/D converter 21 is applied to the frame memory 24 
and stored therein as it is. The pixel data stored in the frame memory are 
read in accordance with the display order of FIG. 12. 
In other words, the unit display period of one the sub-frames in the 
display period of each frame of input image signal is divided into eight 
periods corresponding to the pixel data of 8 bits. Namely, one frame is 
divided into eight sub-frames SF0 to SF7 as shown in FIG. 12 as 
aforementioned. The sub-frames SF0 to SF7b emit the light by sustaining 
discharge at 1 time, 2 times, 4 times, 8 times, 16 times, 32 times, 64 
times and 128 times, respectively, in order. The display order of the 
sub-frames is SF0, SF2, SF4, SF6, SF7, SF5, SF3, and SF1. The sub-frame 
SF7 having the largest weight (the highest bit) is disposed in the central 
portion of the frame, and the other sub-frames SF6 to SF0 are separately 
disposed before and after the sub-frame SF7 in descending order of weight. 
The data read from the frame memory 24 is applied to the pixel data driver 
26. In display operation on the PDP, the PDP is driven by line sequential 
scanning. 
When the interlace video signal for the still picture is discriminated, the 
movable contact 27a is manually connected to the input terminal a or c in 
accordance with the changeover signal from the control circuit 22. Thus, 
the pixel data of 8 bits of the A/D converter 21 or the scanning line 
interpolation processing circuit 29 is applied to the frame memory 24 and 
stored therein as it is. The bit data corresponding to the sub-frames are 
read in order so as to obtain the display order of the sub-frames in the 
display period of each frame shown in FIG. 12. 
In display operation, in accordance with the pixel data from the A/D 
converter 21, the two row electrodes are written at the same time as 
aforementioned. By the pixel data from the scanning line interpolation 
processing circuit 29, the PDP is driven by line sequential scanning. 
On the other hand, when the non-interlace video signal for the moving 
picture of the slow movement is discriminated, the movable contact 27a is 
connected to the input terminal a in accordance with the selection signal 
from the control circuit 22. Thus, the pixel data of 8 bits of the A/D 
converter 21 is applied to the frame memory 24 and stored therein as it 
is. 
The bit data corresponding to the sub-frames are read in order so as to 
obtain the display order of the sub-frames in the display period of each 
frame shown in FIG. 13. In display operation, the two row electrodes are 
written at the same time. When the pixel data is stored in the frame 
memory, the writing address is controlled so as to compress the pixel data 
half in the vertical direction (thinning out). 
As shown in FIG. 13, the display order of the sub-frames is SF0, SF4a, 
SF6a, SF7a, SF5a, SF2, SF3, SF5b, SF7b, SF6b, SF4b, and SF1. The divided 
sub-frames SF4a to SF7a and SF4b to SF7b are symmetrically disposed at the 
center of the frame, while the sub-frames SF7a and SF7b each of which has 
the largest weight (the highest bit) are disposed in the central portions 
of the opposite sides. The other divided sub-frames SF4a to SF6a and SF4b 
to SF6b are separately disposed before and after the respective sub-frames 
SF7a and SF7b in descending order of weight. 
When the interlace video signal for the moving picture of a slow movement 
is discriminated, the movable contact 27a is connected to the input 
terminal a in accordance with the selection signal from the control 
circuit 22. Thus, the pixel data of 8 bits of the A/D converter 21 is 
applied to the frame memory 24 and stored therein as it is. 
The bit data corresponding to the sub-frames are read in order so as to 
obtain the display order of the sub-frames in the display period of each 
frame shown in FIG. 13. In display operation, the two row electrodes are 
written at the same time. 
When the non-interlace video signal for the moving picture of a fast 
movement is discriminated, the movable contact 27a of the signal 
changeover selecting circuit 27 is connected to the input terminal b in 
accordance with the selection signal from the control circuit 22. Thus, 
the false contour correcting pixel data of 12 bits of the pixel data 
processing circuit 23 is applied to the frame memory 24 and stored therein 
as it is. 
The bit data corresponding to the sub-frames are read in order so as to 
obtain the display order of the sub-frames in the display period of each 
frame shown in FIG. 13. In display operation, the two row electrodes are 
written at the same time. 
When the pixel data is stored in the frame memory, the writing address is 
controlled so as to compress the pixel data half in the vertical direction 
(thinning out). 
When the interlace video signal for the moving picture of fast movement is 
discriminated, the movable contact 27a of the signal changeover selecting 
circuit 27 is connected to the input terminal b in accordance with the 
selection signal from the control circuit 22. Thus, the false contour 
correcting pixel data of 12 bits of the pixel data processing circuit 23 
is applied to the frame memory 24 and stored therein as it is. 
The bit data corresponding to the sub-frames are read in order so as to 
obtain the display order of the sub-frames in the display period of each 
frame shown in FIG. 13. In display operation, the two row electrodes are 
written at the same time. 
In order to display the video signal for the moving picture of fast 
movement, a plurality of light emitting patterns which have the same light 
emitting period and a different position for emitting the light may be 
provided. If the light emitting pattern of each pixel is changed, the 
false contour can be reduced. 
The frame memory 24 reads out the pixel data stored therein from the first 
line to the sequential line in order at each display period of the 
sub-frame. The read pixel data is applied to the data electrode driver 26 
as the pixel data driving data. 
In order to display the video signal for the moving picture on the PDP, 
sequential two row electrodes (X1, Y1 and X2, Y2) are driven as one 
scanning unit by the line sequential scanning, while one scanning unit of 
the row electrodes which are driven at the same time is shifted by one row 
electrode in a first field (odd number field) and a second field (even 
number field) respectively as shown in FIGS. 14a to 14f. 
FIGS. 14a to 14c show row electrodes in the first field selected for 
scanning to write the data every horizontal scanning period. FIGS. 14d to 
14f show row electrodes in the second field selected for scanning to write 
the data every horizontal scanning period. In the horizontal scanning 
period, the same data is written on the two rows (neighboring two row 
electrodes). 
From the foregoing, in the interlace video signal for the moving picture, 
the pixel data are written on the two row electrodes at the same time. 
Thus, the amount of pixel data is reduced half compared with the 
non-interlace video signal, and the address period is also reduced half. 
Therefore, even if the number of sub-frames is increased for reducing the 
false contour, it is not necessary to increase the capacity of the frame 
memory 24. 
In the non-interlace video signal for the moving picture, the number of 
scanning lines is compressed, and the two row electrodes are written at 
the same time. Thus, the amount of pixel data is reduced half compared 
with the non-interlace video signal for the still picture, and the address 
period is also reduced half. Therefore, the capacity of the frame memory 
24 is prevented from increasing. 
If the number of sub-frames (bit number) is increased, the number of tones 
can be increased from 64 tones (6 bits) to 256 tones (8 bits). 
Furthermore, by using a surplus capacity of the memory, the pixel data can 
be temporarily stored therein. 
In the half tone display method, the video signal for the moving picture or 
the still picture is discriminated. The video signal only for the moving 
picture is processed to the false contour correction. Alternatively, the 
user may manually operate to select whether the false contour correction 
is processed to the input video signal (and two row electrodes are driven 
at the same time) or not. 
In the method, if the video signal for the moving picture of fast movement 
is discriminated, a plurality of light emitting patterns which have the 
same light emitting period and a different position for emitting the light 
may be provided for changing the light emitting pattern of each pixel. 
Alternatively, in the case of the video signal for the moving picture 
irrespective of the speed of movement, one of the false contour correcting 
processes for the fast movement and the slow movement may be uniformly 
employed. 
In the embodiment, although the driving system is applied to the ACPDP of 
the reflection type of three-electrode, the driving system of the present 
invention can be applied to other types of PDP such as a DCPDP. 
In accordance with the present invention, the false contour correction is 
processed only to the video signal for the moving picture. Thus, the 
capacity of the memory is prevented from increasing, and the quality of 
display is increased. 
In display operation, when the interlace video signal for the moving 
picture is discriminated, sequential two row electrodes are driven as one 
scanning unit by line sequential scanning, while the row electrodes of one 
scanning unit which are driven in the first and second fields at the same 
time are scanned to be shifted by one row electrode. Thus, the scanning 
period for writing is shortened, thereby obtaining time for increasing the 
sub-frames for the false contour correcting process. 
In the non-interlace video signal for the still picture, the PDP is driven 
by line sequential scanning. Thus, the quality of display is prevented. 
When the video signal for the moving picture is discriminated, a plurality 
of light emitting patterns which have the same light emitting period and a 
different position for emitting the light may be provided for changing the 
light emitting pattern of each pixel. Thus, in the moving picture of the 
fast movement, the false contour is further reduced. 
While the invention has been described in conjunction with preferred 
specific embodiment thereof, it will be understood that this description 
is intended to illustrate and not limit the scope of the invention, which 
is defined by the following claims.