ELECTRONIC DEVICE WITH VOLTAGE LINEAR REGULATOR AND METHOD OF OPERATING THEREOF

The present disclosure relates to a device having a supply input receiving a supply voltage, a switched-mode power supply comprising an output at which is generated a supply voltage, and a voltage linear regulator supplying a load, the regulator receiving the supply voltages, the regulator including two transistors coupled between the supply input, respectively the output of the supply, and an output node of the regulator. When the current drawn by the load is below a threshold, an output current delivered to the load is equal to a current flowing through the transistor, so that, when the current drawn by the load is above the threshold, the output current is equal to a current flowing through the transistor plus a current flowing through the transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of French Patent Application No. 2210179, filed on Oct. 10, 2022, entitled “Dispositif électronique,” which is hereby incorporated herein by reference to the maximum extent allowable by law.

TECHNICAL FIELD

The present disclosure generally relates the electronic devices and methods, and, more particularly, to devices comprising a voltage linear regulator and methods of operating thereof.

BACKGROUND

In electronics, a linear regulator is a voltage regulator based on an active component operating in its linear area or on a passive component, such as a Zener diode, operating in its reverse area.

A Low DropOut (LDO) voltage regulator is a type of voltage linear regulator capable of regulating the output voltage even when the power supply voltage is in the vicinity of the output voltage.

SUMMARY

One embodiment addresses all or some of the drawbacks of known electronic devices.

An embodiment provides an electronic device comprising:a first supply input configured to receive a first supply voltage;a first switched-mode power supply comprising a first output, the first switched-mode power supply being configured to generate a second supply voltage at the first output; anda voltage linear regulator configured to supply a load included in the device, the regulator being configured to receive the first and second supply voltages, the regulator comprising:a first transistor coupled between the first supply input and an output node of the regulator; anda second transistor coupled between the output of the first switched-mode power supply and the output node of the regulator,the regulator being configured so that, when the current, drawn by the load, is below a threshold, a first output current, delivered to the load by the output node of the regulator, is equal to a third current flowing through the second transistor, and so that, when the current is above the threshold, the first output current is equal to the addition of a fourth current flowing through the first transistor and the third current flowing through the second transistor, the fourth current being non-zero.

Another embodiment provides a method for controlling an electronic device comprising:a first supply input receiving a first supply voltage;a first switched-mode power supply comprising a first output, the first switched-mode power supply generating a second supply voltage at the first output; anda voltage linear regulator supplying a load included in the device, the regulator receiving the first and second supply voltages, the regulator comprising:a first transistor coupled between the first supply input and an output node of the regulator; anda second transistor coupled between the output of the first switched-mode power supply and the output node of the regulator,when the current, drawn by the load, is below a threshold, a first output current, delivered to the load by the output node of the regulator, is equal to a third current flowing through the second transistor, and when the current is above the threshold, the first output current is equal to the addition of a fourth current flowing through the first transistor and the third current flowing through the second transistor, the fourth current being non-zero.

According to an embodiment, the regulator is configured so that when the current drawn by the load is above the threshold, the greater the drawn current, the greater the fourth current flowing through the first transistor.

According to an embodiment, the regulator comprises:an error amplifier configured to receive as an input a set point voltage, and a voltage representative of the output voltage of the regulator, and configured to generate an error voltage;a voltage-to-current converter, comprising an input configured to receive the error voltage, and generating a fifth current at a second output of the converter, and a sixth current at a third output of the converter; anda first gate-driving circuit driving the first transistor, and a second gate-driving circuit driving the second transistor, the converter being configured to deliver the fifth current to the first driving circuit, and the sixth current to the second driving circuit.

According to an embodiment, the regulator comprises a voltage dividing bridge the input of which is coupled with the output node of the regulator, and the output of which is coupled with an input of the amplifier such a way to deliver the voltage representative of the output voltage.

According to an embodiment, the converter comprises a third transistor coupled between a first node and a node for applying a reference voltage, the third transistor being configured to be controlled by the error voltage, the converter comprising a fourth transistor coupling the first node with the second output and at least one fifth transistor coupling the first node with the third output.

According to an embodiment, the first node and the third output are coupled via a set of at least two fifth transistors connected in parallel.

According to an embodiment, the second gate-driving circuit comprises a sixth transistor diode-coupled between the second output of the converter and the output of the first switched-mode power supply, the driving terminal of the sixth transistor being coupled with an output of the second driving circuit.

According to an embodiment, the second driving circuit comprises:a seventh transistor diode-coupled between an input configured to receive a set point current and the output of the first switched-mode power supply, andan eighth transistor coupled between the second output of the converter and the output of the first switched-mode power supply, the driving terminal of the eighth transistor being coupled with the driving terminal of the seventh transistor.

According to an embodiment, the first gate-driving circuit comprises a ninth diode-connected transistor, the ninth transistor and a resistor being coupled between the first output of the converter and the first input of the device, the driving terminal of the ninth transistor being coupled with an output of the first driving circuit.

According to an embodiment, the first gate-driving circuit comprises:a tenth transistor diode-connected between an input configured to receive a set point current and the first input of the device, andan eleventh transistor coupled between the first output of the converter and the first input of the device, the driving terminal of the tenth transistor being coupled with the driving terminal of the eleventh transistor.

According to an embodiment, the first driving circuit comprises:a twelfth transistor coupled between the first output of the converter and the first input of the device;a first switch coupled between the driving terminal of the twelfth transistor and the input configured to receive the set point current; anda second switch coupled between the driving terminal of the twelfth transistor and the first input of the device.

According to an embodiment, the device comprises at least one second switched-mode power supply, and comprises for each second switched-mode power supply, a second transistor, coupled between the output of the corresponding second switched-mode power supply and the output node, the regulator being configured so that only a current flowing through one of the second transistors is non-zero at once.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

For the sake of clarity, only the operations and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail.

FIG.1illustrates an embodiment of an electronic device10comprising a voltage linear regulator12. The voltage regulator12is a low dropout voltage regulator or LDO regulator.

The regulator12is configured to energize a load14. The load14is for example an analog circuit. The load14is for example a logic circuit. The load14is for example an analog circuit controlling a switched-mode power supply (SMPS).

The regulator12comprises an output at which an output voltage VOUT is generated. The voltage VOUT is the power supply voltage of the circuit14. The output is coupled, preferably connected, to a supply input of the circuit14.

The device10can for example operate in a low power mode. In order to guarantee a low power, the regulator12can be supplied by at least two voltage sources, at least one having a value less than the supply voltage of the device10. The voltage sources delivering different supply voltages. The regulator12generates the output voltage VOUT from one of the power supply voltages. The regulator generates a current IOUT at the output.

In the example ofFIG.1, the regulator12is coupled with three supply sources. The regulator12may thus be supplied by one or more of these voltage sources. According to the load14and according to the power used by the load14, the power supply voltage of the regulator may come from one of these sources, or from several of them.

The regulator12is for example supplied by a supply voltage VDD of the device10. The voltage VDD is for example higher than 3 V, for example equal to 5 V. In other words, the regulator12comprises a supply input coupled with, preferably connected to, a node16for applying the voltage VDD. The regulator thus receives at the input a current IBAT.

The regulator12is for example supplied by at least one voltage generated by a switched-mode power supply. In the example ofFIG.1, the device comprises two switched-mode power supplies18and20. Each of the power supplies18and20thus comprises an output coupled with, preferably connected to, a supply input of the regulator12. For example, the power supplies18and20are down-converting supplies (buck).

The power supply18generates a supply voltage VBUCK1at the output coupled with, preferably connected to, the regulator12. The regulator12thus receives the voltage VBUCK1at a supply input. Similarly, the power supply18generates a current IBUCK1at the output. The regulator12thus receives the current IBUCK1at a supply input. Similarly, the power supply20generates a supply voltage VBUCK2at the output coupled with, preferably connected to, the regulator12. The regulator12thus receives the voltage VBUCK2at a supply input. Similarly, the power supply20generates a current IBUCK2at the output. The regulator12thus receives the current IBUCK2at a supply input. The voltages VBUCK1and VBUCK2are for example lower than the power supply voltage VDD, for example lower than 3.3 V.

The power supplies18and20are preferably different. The power supplies18and20are for example configured to supply different ranges of voltage or current.

The device10is preferably configured so that only one of the power supplies18and20can be active at once. In other words, if the regulator12is supplied by the power supply18, the regulator is not supplied by the power supply20. Similarly, if the regulator12is supplied by the power supply20, the regulator is not supplied by the power supply18. The device10is thus configured such a way that the regulator12does not receive non-zero currents IBUCK1and IBUCK2at once.

The device10is configured such a way that the current IOUT is equal to the addition of the current IBAT and the current IBUCK, the current IBUCK corresponding to the current IBUCK1or to the current IBUCK2, according to the power supply18or20supplying the regulator.

The current IBAT is configured to be determined by the following equation: IBAT=β*IBUCK−IOS, IOS being a constant value, and β being for example a variable, for example depending on the current used by the load. Preferably, the larger the current requested by the load, the higher the value β.

During the operation of the regulator, for example in low power mode, as the value β is so that the value of the term β *IBUCK is lower than the value of the constant IOS, the value of the current IBAT is zero, the value of the current IBAT could not be negative. The current IOUT is thus equal to the current IBUCK.

During the operation of the regulator, for example in low power mode, as the value β is so that the value of the term β *IBUCK is higher than the value of the constant IOS, the value of the current IBAT is not zero. Thus, the current IOUT depends on the value of the current IBAT and of the current IBUCK. The value VOUT depends on the value of the voltage VDD and of the voltage VBUCK. The regulator is thus supplied by the supply voltage VDD and by the power supply18or20delivering the voltage VBUCK.

Thus, as the current used by the load is lower than a threshold, the regulator is supplied by a switched-mode power supply, and as the current used by the load is higher than the threshold, the regulator is supplied by the switched-mode power supply and by the supply voltage source VDD. Preferably, the greater the current used by the load, the larger the part of the current IOUT constituted by the current IBAT.

FIG.2illustrates an embodiment of the voltage linear regulator12.

The regulator12comprises an error amplifier22. The amplifier22is for example an operational amplifier. The amplifier22comprises a first input, for example a positive input (+), at which are delivered a set point voltage VREF and a current IREF. The first input is thus coupled with, preferably connected to, a node for applying the voltage VREF. The amplifier22comprises a second input, for example a negative input (−), at which a loop voltage VFB is applied. The loop voltage depends on the output voltage VOUT, is for example proportional to the output voltage VOUT.

The regulator12comprises a voltage-to-current converter (V to I converter)24. The converter24comprises an input coupled with, preferably connected to, an output of the amplifier22. The converter24comprises at least two outputs, each output delivering a current representative of the voltage received as an input by the converter24.

The regulator12comprises gate-driving circuits26,28,30. The regulator12comprises as many gate-driving circuits as possible supply sources for the regulator12. In other words, in the example ofFIG.1, the regulator12comprises the gate-driving circuit30associated with the source of the voltage VDD and the gate-driving circuits26, and28associated with the power supplies18and20, respectively.

The driving circuits26,28, and30are configured to receive each a current generated by the converter24. Thus, each circuit26,28,30comprises an input coupled with, preferably connected to, an output of the converter24.

Preferably, the converter24is configured so that the current supplied to the gate-driving circuits26and28, i.e. the gate-driving circuits associated with the switched-mode power supplies18and20, that is n times higher than the current supplied to the gate-driving circuit30, i.e. the driving circuit associated with the source of the supply voltage VDD. The value n is preferably an integer value, for example positive, for example higher than two.

Each gate-driving circuit is configured to receive the supply voltage to which it is associated. Thus, the circuits26and28receive the voltage VBUCK1and VBUCK2, respectively, and the circuit30receives the voltage VDD. In other words, the circuit26comprises a supply input coupled with, preferably connected to, a node for applying the voltage VBUCK1, for example the output of the power supply18. The circuit28comprises a supply input coupled with, preferably connected to, a node for applying the voltage VBUCK2, for example the output of the power supply20. The circuit30comprises a supply input coupled with, preferably connected to, a node for applying the voltage VDD.

Each gate-driving circuit26,28,30generates a driving voltage of a gate of a transistor. The circuit26generates the gate-driving voltage VGBUCK1of a transistor32. The circuit28generates the gate-driving voltage VGBUCK2of a transistor34. The circuit30generates the gate-driving voltage VGBAT of a transistor36.

The transistor32is connected in series with a transistor38between a node for applying the voltage VBUCK1and an output node40, at which is generated the output voltage VOUT of the regulator12. The transistor34is connected in series with a transistor42between a node for applying the voltage VBUCK2and the output node40. The transistor36is connected between a node for applying the voltage VDD and the output node40.

A conduction terminal, for example the source, of the transistor32is coupled with, preferably connected to, the node for applying the voltage VBUCK1, and another conduction terminal, for example the drain, of the transistor32is coupled with, preferably connected to, a node44. A conduction terminal, for example the source, of the transistor38is coupled with, preferably connected to, the node40, and another conduction terminal, for example the drain, of the transistor38is coupled with, preferably connected to, the node44. The body of the transistor32is for example coupled with, preferably connected to, the node for applying the voltage VBUCK1. The body of the transistor38is for example coupled with, preferably connected to, the node40.

A conduction terminal, for example the source, of the transistor34is coupled with, preferably connected to, the node for applying the voltage VBUCK2, and another conduction terminal, for example the drain, of the transistor34is coupled with, preferably connected to, a node46. A conduction terminal, for example the source, of the transistor42is coupled with, preferably connected to, the node40, and another conduction terminal, for example the drain, of the transistor42is coupled with, preferably connected to, the node44. The body of the transistor34is for example coupled with, preferably connected to, the node for applying the voltage VBUCK2. The body of the transistor42is for example coupled with, preferably connected to, the node40.

A conduction terminal, for example the source, of the transistor36is coupled with, preferably connected to, the node for applying the voltage VDD, and another conduction terminal, for example the drain, of the transistor36is coupled with, preferably connected to, the node40.

The current flowing through the transistor36, i.e. the current reaching the node40from the node for applying the voltage VDD, is the current IBAT. The current flowing through the transistor34and the transistor42, that is the current reaching the node40from the node for applying the voltage VBUCK2, is the current IBUCK2. The current flowing through the transistor32and the transistor44, i.e. the current reaching the node40from the node for applying the voltage VBUCK1, is the current IBUCK1.

The output current IOUT, i.e. the courant delivered at the output of the regulator12, corresponds to the addition of the currents IBAT, IBUCK1, and IBUCK2, the currents IBUCK1and IBUCK2couldn't be non-zero at once.

The regulator12comprises a control circuit not illustrated. The control circuit is configured to generate the control voltages of the transistors38and42.

The regulator12comprises for example a capacitor48coupled between the node40and a node for applying a reference voltage GND, for example ground. In other words, a terminal of the capacitor48is coupled with, preferably connected to, the node40and another terminal of the capacitor48is coupled with, preferably connected to, the node for applying the voltage GND.

The regulator comprises two resistors50and52. The resistors50and52form a voltage dividing bridge generation the voltage VFB. The resistors50and52are connected in series between the node40and the node for applying the voltage GND. A terminal of the resistor50is coupled with, preferably connected to, the node40and another terminal of the resistor50is coupled with, preferably connected to, a node54at which the voltage VFB is generated. A terminal of the resistor52is coupled with, preferably connected to, the node54and another terminal of the resistor52is coupled with, preferably connected to, the node for applying the voltage GND. The node54is coupled with, preferably connected to, the second input of the amplifier22. The node40thus corresponds to the input node of the voltage dividing bridge and the node54corresponds to the output node of the voltage dividing bridge.

FIG.3illustrates in more detail a part of the embodiment ofFIG.2. More precisely,FIG.3illustrates an embodiment of the V to I converter24ofFIG.2.

The converter24comprises an input56coupled with, preferably connected to, the output of the amplifier22.

The converter comprises a transistor58. The transistor58is for example a MOSFET transistor, for example an N-channel transistor. The transistor58is controlled by the input voltage, i.e. the voltage delivered at node56by the amplifier22. The driving terminal of the transistor58is coupled with, preferably connected to, the node56.

The converter comprises a resistor60. The resistor60is connected in series to the transistor58between a node62and a node for applying the reference voltage GND. In other words, a conduction terminal of the transistor58, for example the drain, is coupled with, preferably connected to, the node62, and another conduction terminal of the transistor58, for example the source, is coupled with, preferably connected to, a node64. The transistor58and the resistor60are flowed through by a current IG.

The node62is coupled with an output node66of the converter24. The converter24delivers, via the output66, a current IMBAT. The current IMBAT is the current supplied to the driving circuit30ofFIG.2.

The converter24comprises a transistor68and a transistor70. The transistors68and70are preferably MOSFET transistors, for example N-channel transistors. The transistors68and70are connected in series between the node62and the output66. In other words, a conduction terminal, for example the drain, of the transistor68is coupled with, preferably connected to, the output66, and another conduction terminal, for example the source, of the transistor68is coupled with, preferably connected to, a node72. A conduction terminal, for example the drain, of the transistor70is coupled with, preferably connected to, the node72, and another conduction terminal, for example the source, of the transistor70is coupled with, preferably connected to, the node62.

The node62is coupled with an output node74of the converter24. The converter24delivers, via the output74, a current IMBUCK1. The current IMBUCK1is the current supplied to the driving circuit26ofFIG.2.

The converter24comprises a transistor76and a set of transistors78. The transistor76and the transistors of the set78are for example MOSFET transistors, for example N-channel transistors. The set of transistors78comprises n transistors, connected in parallel. In other words, the drains of the transistors of the set78are coupled with, preferably connected to, each other and the sources of the transistors of the set78are coupled with, preferably connected to, each other. Further, the driving terminals of the transistors of the set78are coupled with, preferably connected to, each other.

The transistor76and the set78are connected in series between the node62and the output74. In other words, a conduction terminal, for example the drain, of the transistor76is coupled with, preferably connected to, the output74and another conduction terminal, for example the source, of the transistor76is coupled with, preferably connected to, a node80. A conduction terminal, for example the drain, of the set78, i.e. the drains of the transistors of the set78, is coupled with, preferably connected to, the node80, and another conduction terminal, for example the source, of the set78is coupled with, preferably connected to, the node62.

The node62is coupled to an output node82of the converter24. The converter24delivers, via the output82, a current IMBUCK2. The current IMBUCK2is the current supplied to the driving circuit28ofFIG.2.

The converter24comprises a transistor84and a set of transistors86. The transistor84and the transistors of the set86are for example MOSFET transistors, for example N-channel transistors. The set of transistors86comprises several transistors preferably as many transistors as the set78, preferably n transistors, connected in parallel. In other words, the drains of the transistors of the set86are coupled with, preferably connected to, each other, and the sources of the transistors of the set86are coupled with, preferably connected to, each other. Further, the driving terminals of the transistors of the set86are coupled with, preferably connected to, each other.

The transistor84and the set86are connected in series between the node62and the output82. In other words, a conduction terminal, for example the source, of the transistor84is coupled with, preferably connected to, the output82and another conduction terminal, for example the drain, of the transistor84is coupled with, preferably connected to, a node88. A conduction terminal, for example the source, of the set86, i.e. the sources of the transistors of the set86, is coupled with, preferably connected to, the node88, and another conduction terminal, for example the drain, of the set86, i.e. the drains of the transistors of the set86, is coupled with, preferably connected to, the node62.

The driving terminals of the transistors68,76, and84are coupled with, preferably connected to, each other. The transistors68,76, and84are controlled by a voltage VCAS. The voltage VCAS is a cascode voltage, configured so that the source voltages of the transistors68,76, and84are identical.

The transistor70and the sets78and86are controlled by voltages generated by the non-illustrated control circuit of the regulator12. During the operation of the converter24, the driving voltage of the transistor70is so that the transistor70is switched-on, for example is equal to the voltage VDD. During the operation of the converter24, the driving voltage of the set78or86corresponding to the switched-mode power supply supplying the regulator12is so that the set is switched-on, for example is equal to the voltage VDD. The driving voltage of the other set is so that the set is switched-off, for example significantly equal to 0V.

Preferably, the transistors of the set78are identical to each other. Preferably, the transistors of the set86are identical to each other. Preferably, the transistors of the set78are identical to the transistors of the set86. Preferably, the transistor70is identical to the transistors of the sets78and86.

The currents IMBUCK1and IMBUCK2are thus n times higher than the current IBAT. The control voltages of the sets78and86are such that the currents IMBUCK1and IMBUCK2cannot be non-zero during the same operating periods.

The current IG is equal, during the operation of the device10, to the addition of the current IMBAT and of the currents IMBUCK1and IMBUCK2, one of the currents IMBUCK1and IMBUCK2being zero. Thus, the non-zero current among the currents IMBUCK1and IMBUCK2is equal to n/(n+1) IG and the current IMBAT is equal to 1/(n+1) IG.

FIG.4illustrates in more detail another part of the embodiment ofFIG.2. More precisely, theFIG.4illustrates an embodiment of a circuit89. The circuit89corresponds to the circuits26and28, i.e. the gate-driving circuits of the transistors32and34, in other words the gate-driving circuits associated with the supply voltages VBUCK1and VBUCK2. The regulator12thus comprises two circuits89. More generally, the regulator12comprises for example as many circuits89as possible supply voltages from a switched-mode power supply.

The circuit89comprises an input90at which is applied the supply voltage VBUCK, corresponding to the voltages VBUCK1or VBUCK2according whether the circuit89corresponds to the circuit26or28. The circuit89comprises an input92at which is supplied the current IMBUCK, corresponding to the current IMBUCK1or to the current IMBUCK2. In other words, the input92is coupled with, preferably connected to, the output of the circuit24associated to the supply voltage VBUCK. The circuit89comprises an input94at which is supplied the set point current IREF. The current IREF is for example generated by the control circuit not illustrated described in relation withFIG.2. The current IREF is for example approximatively constant during the operation of the circuit89. The circuit89comprises an output96at which is generated a voltage VGBUCK, corresponding to the voltage VGBUCK1or the voltage VGBUCK2.

The circuit89comprises a transistor98. The transistor98is for example a MOSFET transistor, for example a P-channel transistor. The transistor98is coupled between the input90and the input94. In other words, a conduction terminal of the transistor98, for example the drain, is coupled with, preferably connected to, the input94and another conduction terminal of the transistor98, for example the source, is coupled with, preferably connected to, the input90. The driving terminal of the transistor98is coupled with, preferably connected to, a node100. The transistor98is for example diode-connected. The node100is for example coupled with, preferably connected to, the input94.

The circuit89comprises a transistor102. The transistor102is for example a MOSFET transistor, for example a P-channel transistor. The transistor102is coupled between the input90and the input92. In other words, a conduction terminal of the transistor102, for example the drain, is coupled with, preferably connected to, the input92and another conduction terminal of the transistor102, for example the source, is coupled with, preferably connected to, the input90. The driving terminal of the transistor102is coupled with, preferably connected to, the node100.

The circuit89comprises a transistor104. The transistor104is for example a MOSFET transistor, for example a P-channel transistor. The transistor104is coupled between the input90and the input92. The transistor104is coupled in parallel to the transistor102. In other words, a conduction terminal of the transistor104, for example the drain, is coupled with, preferably connected to, the input92and another conduction terminal of the transistor104, for example the source, is coupled with, preferably connected to, the input90. The driving terminal of the transistor104is coupled with, preferably connected to the input96.

Preferably, the surface of the transistor32or34to which corresponds the circuit89is equal to m times the surface of the transistor104, m being a constant value, preferably a positive integer value.

The current IBUCK is equal to a times a current IC flowing through the transistor104. The value α is equal to m as the transistor32or34is at saturation.

Preferably, the transistors98and102are identical. The current IMBUCK is thus equal to the addition of the current IC and of the current IREF.

FIG.5illustrates in more detail another part of the embodiment ofFIG.2. More precisely,FIG.5illustrates an embodiment of the circuit30, i.e. the gate-driving circuit of the transistor36, in other words the gate-driving circuit associated to the supply voltage VDD.

The circuit30comprises an input106at which the supply voltage VDD is applied. The circuit30comprises an input108at which the current IMBAT is supplied. In other words, the input108is coupled with, preferably connected to, the output of the circuit24associated to the supply voltage VDD. The circuit30comprises an input no at which the set point current IREF is supplied. The current IREF is for example generated by the control circuit not illustrated described in relation withFIG.2. The current IREF is for example approximatively constant during the operation of the circuit30. The circuit30comprises an output112at which the voltage VGBAT is generated.

The circuit30comprises a transistor114. The transistor114is for example a MOSFET transistor, for example a P-channel transistor. The transistor114is coupled between the input106and the input110. In other words, a conduction terminal of the transistor114, for example the drain, is coupled with, preferably connected to, the input no and another conduction terminal of the transistor114, for example the source, is coupled with, preferably connected to, the input106. The driving terminal of the transistor114is coupled with, preferably connected to, a node116. The transistor114is for example diode-connected. The node116is for example coupled with, preferably connected to, the input110.

The circuit30comprises a transistor118. The transistor118is for example a MOSFET transistor, for example a P-channel transistor. The transistor118is coupled between the input106and the input108. In other words, a conduction terminal of the transistor118, for example the drain, is coupled with, preferably connected to, the input108and another conduction terminal of the transistor118, for example the source, is coupled with, preferably connected to, the input106. The driving terminal of the transistor118, is coupled with, preferably connected to, the node116.

The circuit30comprises a transistor120. The transistor120is for example a MOSFET transistor, for example a P-channel transistor. The transistor120is coupled between the input106and the input108. The transistor120is connected in parallel with the transistor118. In other words, a conduction terminal of the transistor120, for example the drain, is coupled with, preferably connected to, the input108and another conduction terminal of the transistor120, for example the source, is coupled with, preferably connected to, the input106. The driving terminal of the transistor120is coupled with the input no via a switch122. Further, the driving terminal of the transistor120is coupled with the input106via a switch124. In other words, a terminal of the switch122is coupled with, preferably connected to, the driving terminal of the transistor120and another terminal of the switch122is coupled with, preferably connected to, the node116. Similarly, a terminal of the switch124is coupled with, preferably connected to, the driving terminal of the transistor120and the other terminal of the switch124is coupled with, preferably connected to, the input106. The switches122and124are for example controlled by the non-illustrated control circuit described in relation withFIG.2.

The circuit30comprises for example a transistor126and a resistor128connected in series between the input106and the input108. The transistor128is for example a MOSFET transistor, for example a P-channel transistor. A terminal of the resistor128is for example coupled with, preferably connected to, the input106and the other terminal of the resistor128is for example coupled with, preferably connected to, a node130. A conduction terminal of the transistor126, for example the source, is coupled with, preferably connected to, the node130and another conduction terminal of the transistor126, for example the drain, is coupled with, preferably connected to, the input108. The driving terminal of the transistor126is coupled with, preferably connected to, the output112at which is applied the voltage VGBAT. The output112is further coupled with, preferably connected to, the input108, such a way to diode-connect the transistor126.

Preferably, the surface of the transistor36is equal to m times the surface of the transistor126. The transistor36is always at saturation. The current IBAT is thus equal to m times the value of the current ICB, the current ICB being the current flowing through the transistor126. Further, the current IMBAT is equal to the addition of p times the current IREF and the current ICB, p being a constant value defined by the circuit24.

Thus, the current IBAT is configured to be determined by the following equation:

As the current used by the load is low, the current IOUT is equal to the current IBUCK, the part IBAT of the current IOUT being zero.

As the voltage drop is high, i.e. as the voltage difference between VBUCK and the regulated voltage is high, the value α becomes equal to the value m, and the current IOUT is equal to the addition of the current IBAT and the current IBUCK, the current IBAT being non-zero and the current IBUCK being equal to n times the current IBAT. The current IOUT is thus mostly delivered by the switched-mode power supply generating IBUCK.

As the voltage drop decreases, the transistor32or34, corresponding to the switched-mode power supply generating a non-zero current, enters the triode region. The value α thus becomes less than the value m. The current IBUCK thus becomes less than n times the current IBAT.

The more the voltage drop decreases, the more the transistor enters the triode region, and the value α becomes increasingly lower than the value m. Thus, the ratio of the value of the current IBUCK on the value of the current IBAT decreases up to become less than 1. The current IBUCK becomes less than the current IBAT. The most part of the current IOUT thus comes from the current IBAT.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily occur to those skilled in the art. In particular, although the described embodiments comprise two switched-mode power supplies, it is understood that the device could comprise a single switched-mode power supply, or a larger number of switched-mode power supplies.

Further, although the described embodiments comprise a transistor70and sets78and86, the transistor70could be replaced with a set of transistors, preferably identical, connected in parallel such as the sets78and86. The sets78and86then comprise n times more transistors than the set70.

Finally, the practical implementation of the embodiments and variants described herein is within the capabilities of those skilled in the aft based on the functional description provided hereinabove.