MEMORY CELLS AND MEMORY ARRAY STRUCTURES AND METHODS OF THEIR FABRICATION

Memory cells, and memories and memory array structures containing such memory cells, might include a control gate, a channel, a gate dielectric between the channel and the control gate, a charge-storage node between the gate dielectric and the control gate, a charge-blocking material between the charge-storage node and the control gate, a laminated dielectric between the charge-blocking material and the control gate, and a high-K dielectric between the laminated dielectric and the control gate, wherein the laminated dielectric comprises an instance of a first dielectric material between the charge-blocking material and the high-K dielectric and an instance of a second dielectric material between the instance of the first dielectric material and the high-K dielectric, and wherein the instance of the first dielectric material has a higher oxygen areal density than an oxygen areal density of the instance of the second dielectric material.

TECHNICAL FIELD

The present disclosure relates generally to integrated circuits, and, in particular, in one or more embodiments, the present disclosure relates to memory cells and memory array structures and methods of their fabrication, as well as apparatus containing such memory array structures.

BACKGROUND

Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.

A NAND flash memory is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor. Each source select transistor might be connected to a source, while each drain select transistor might be connected to a data line, such as column bit line. Variations using more than one select gate between a string of memory cells and the source, and/or between the string of memory cells and the data line, are known.

Memory cells are typically erased before they are programmed to a desired data state. For example, memory cells of a particular block of memory cells may first be erased and then selectively programmed. For a NAND array, a block of memory cells is typically erased by grounding all of the access lines (e.g., word lines) in the block and applying an erase voltage to the channel regions of the memory cells (e.g., through data lines and source connections) in order to remove charges that might be stored to charge-storage structures (e.g., floating gates or charge traps) of the block of memory cells. Typical erase voltages might be on the order of 20V or more before completion of an erase operation. As memory cells experience higher numbers of program-erase cycles, erasing of memory cells typically becomes more difficult as electrons become trapped in the memory cell structure.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments might be utilized and structural, logical and electrical changes might be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.

The term “semiconductor” used herein can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. “Semiconductor” is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, previous process steps might have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/junctions.

The term “conductive” as used herein, as well as its various related forms, e.g., conduct, conductively, conducting, conduction, conductivity, etc., refers to electrically conductive unless otherwise apparent from the context. Similarly, the term “connecting” as used herein, as well as its various related forms, e.g., connect, connected, connection, etc., refers to electrically connecting by an electrically conductive path unless otherwise apparent from the context.

It is recognized herein that even where values might be intended to be equal, variabilities and accuracies of industrial processing and operation might lead to differences from their intended values. These variabilities and accuracies will generally be dependent upon the technology utilized in fabrication and operation of the integrated circuit device. As such, if values are intended to be equal, those values are deemed to be equal regardless of their resulting values.

FIG.1is a simplified block diagram of a first apparatus, in the form of a memory (e.g., memory device)100, in communication with a second apparatus, in the form of a processor130, as part of a third apparatus, in the form of an electronic system, according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and the like. The processor130, e.g., a controller external to the memory device100, might be a memory controller or other external host device.

Memory device100includes an array of memory cells104that might be logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line) while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line might be associated with more than one logical row of memory cells and a single data line might be associated with more than one logical column. Memory cells (not shown inFIG.1) of at least a portion of array of memory cells104are capable of being programmed to one of at least two target data states. At least a portion of the memory cells of the array of memory cells104might have a structure in accordance with an embodiment.

A row decode circuitry108and a column decode circuitry110are provided to decode address signals. Address signals are received and decoded to access the array of memory cells104. Memory device100also includes input/output (I/O) control circuitry112to manage input of commands, addresses and data to the memory device100as well as output of data and status information from the memory device100. An address register114is in communication with I/O control circuitry112and row decode circuitry108and column decode circuitry110to latch the address signals prior to decoding. A command register124is in communication with I/O control circuitry112and control logic116to latch incoming commands.

A controller (e.g., the control logic116internal to the memory device100) controls access to the array of memory cells104in response to the commands and might generate status information for the external processor130, i.e., control logic116is configured to perform array operations (e.g., sensing operations [which might include read operations and verify operations], programming operations and/or erase operations) on the array of memory cells104. The control logic116is in communication with row decode circuitry108and column decode circuitry110to control the row decode circuitry108and column decode circuitry110in response to the addresses. The control logic116might include instruction registers128which might represent computer-usable memory for storing computer-readable instructions. For some embodiments, the instruction registers128might represent firmware. Alternatively, the instruction registers128might represent a grouping of memory cells, e.g., reserved block(s) of memory cells, of the array of memory cells104.

Control logic116might also be in communication with a cache register118. Cache register118latches data, either incoming or outgoing, as directed by control logic116to temporarily store data while the array of memory cells104is busy writing or reading, respectively, other data. During a programming operation (e.g., write operation), data might be passed from the cache register118to the data register120for transfer to the array of memory cells104, then new data might be latched in the cache register118from the I/O control circuitry112. During a read operation, data might be passed from the cache register118to the I/O control circuitry112for output to the external processor130, then new data might be passed from the data register120to the cache register118. The cache register118and/or the data register120might form (e.g., might form a portion of) a page buffer of the memory device100. A data register120might further include sense circuits (not shown inFIG.1) to sense a data state of a memory cell of the array of memory cells104, e.g., by sensing a state of a data line connected to that memory cell. A status register122might be in communication with I/O control circuitry112and control logic116to latch the status information for output to the processor130.

Memory device100receives control signals at control logic116from processor130over a control link132. The control signals might include a chip enable CE #, a command latch enable CLE, an address latch enable ALE, a write enable WE #, a read enable RE #, and a write protect WP #. Additional or alternative control signals (not shown) might be further received over control link132depending upon the nature of the memory device100. Memory device100receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor130over a multiplexed input/output (I/O) bus134and outputs data to processor130over I/O bus134.

For example, the commands might be received over input/output (I/O) pins [7:0] of I/O bus134at I/O control circuitry112and might then be written into command register124. The addresses might be received over input/output (I/O) pins [7:0] of I/O bus134at I/O control circuitry112and might then be written into address register114. The data might be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry112and then might be written into cache register118. The data might be subsequently written into data register120for programming the array of memory cells104. For another embodiment, cache register118might be omitted, and the data might be written directly into data register120. Data might also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. Although reference might be made to I/O pins, they might include any conductive nodes providing for electrical connection to the memory device100by an external device (e.g., processor130), such as conductive pads or conductive bumps as are commonly used.

Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins (or other I/O node structures) might be used in the various embodiments.

FIG.2Ais a schematic of a portion of an array of memory cells200A, such as a NAND memory array, as could be used in a memory of the type described with reference toFIG.1, e.g., as a portion of array of memory cells104. Memory array200A includes access lines (e.g., word lines)2020to202N, and data lines (e.g., bit lines)2040to204M. The access lines202might be connected to global access lines (e.g., global word lines), not shown inFIG.2A, in a many-to-one relationship. For some embodiments, memory array200A might be formed over a semiconductor that, for example, might be conductively doped to have a conductivity type, such as a p-type conductivity, e.g., to form a p-well, or an n-type conductivity, e.g., to form an n-well.

Memory array200A might be arranged in rows (each corresponding to an access line202) and columns (each corresponding to a data line204). Each column might include a string of series-connected memory cells (e.g., non-volatile memory cells), such as one of NAND strings2060to206M. Each NAND string206might be connected (e.g., selectively connected) to a common source (SRC)216and might include memory cells2080to208N. The memory cells208might represent non-volatile memory cells for storage of data, and might have a structure in accordance with an embodiment. The memory cells2080to208Nmight include memory cells intended for storage of data, and might further include other memory cells not intended for storage of data, e.g., dummy memory cells. Dummy memory cells are typically not accessible to a user of the memory, and are instead typically incorporated into the string of series-connected memory cells for operational advantages that are well understood.

The memory cells208of each NAND string206might be connected in series between a select gate210(e.g., a field-effect transistor), such as one of the select gates2100to210M(e.g., that might be source select transistors, commonly referred to as select gate source), and a select gate212(e.g., a field-effect transistor), such as one of the select gates2120to212M(e.g., that might be drain select transistors, commonly referred to as select gate drain). Select gates2100to210Mmight be commonly connected to a select line214, such as a source select line (SGS), and select gates2120to212Mmight be commonly connected to a select line215, such as a drain select line (SGD). Although depicted as traditional field-effect transistors, the select gates210and212might utilize a structure similar to (e.g., the same as) the memory cells208. The select gates210and212might represent a plurality of select gates connected in series, with each select gate in series configured to receive a same or independent control signal. Although not depicted inFIG.2A, the select gates210and212might further represent a combination of select gates and GIDL (gate-induced drain leakage) generator gates connected in series, with each select gate in series configured to receive a same or independent control signal and with each GIDL generator gate in series configured to receive a same or independent control signal.

A source of each select gate210might be connected to common source216. The drain of each select gate210might be connected to a memory cell2080of the corresponding NAND string206. For example, the drain of select gate2100might be connected to memory cell2080of the corresponding NAND string2060. Therefore, each select gate210might be configured to selectively connect a corresponding NAND string206to common source216. A control gate of each select gate210might be connected to select line214.

The drain of each select gate212might be connected to the data line204for the corresponding NAND string206. For example, the drain of select gate2120might be connected to the data line2040for the corresponding NAND string2060. The source of each select gate212might be connected to a memory cell208Nof the corresponding NAND string206. For example, the source of select gate2120might be connected to memory cell208Nof the corresponding NAND string2060. Therefore, each select gate212might be configured to selectively connect a corresponding NAND string206to the corresponding data line204. A control gate of each select gate212might be connected to select line215.

The memory array inFIG.2Amight be a quasi-two-dimensional memory array and might have a generally planar structure, e.g., where the common source216, NAND strings206and data lines204extend in substantially parallel planes. Alternatively, the memory array inFIG.2Amight be a three-dimensional memory array, e.g., where NAND strings206might extend substantially perpendicular to a plane containing the common source216and to a plane containing the data lines204that might be substantially parallel to the plane containing the common source216.

Typical construction of memory cells208includes a charge-storage node234(e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine a data state of the memory cell (e.g., through changes in threshold voltage), and a control gate336, as shown inFIG.2A. The charge-storage structure234might include conductive and/or dielectric structures while the control gate336is generally formed of one or more conductive materials. In some cases, memory cells208might further have a defined source/drain (e.g., source)230and a defined source/drain (e.g., drain)232. Memory cells208have their control gates336connected to (and in some cases form) an access line202.

A column of the memory cells208might be a NAND string206or a plurality of NAND strings206selectively connected to a given data line204. A row of the memory cells208might be memory cells208commonly connected to a given access line202. A row of memory cells208can, but need not, include all memory cells208commonly connected to a given access line202. Rows of memory cells208might often be divided into one or more groups of physical pages of memory cells208, and physical pages of memory cells208often include every other memory cell208commonly connected to a given access line202. For example, memory cells208commonly connected to access line202Nand selectively connected to even data lines204(e.g., data lines2040,2042,2044, etc.) might be one physical page of memory cells208(e.g., even memory cells) while memory cells208commonly connected to access line202Nand selectively connected to odd data lines204(e.g., data lines2041,2043,2045, etc.) might be another physical page of memory cells208(e.g., odd memory cells). Although data lines2043-2045are not explicitly depicted inFIG.2A, it is apparent from the figure that the data lines204of the array of memory cells200A might be numbered consecutively from data line2040to data line204M. Other groupings of memory cells208commonly connected to a given access line202might also define a physical page of memory cells208. For certain memory devices, all memory cells commonly connected to a given access line might be deemed a physical page of memory cells. The portion of a physical page of memory cells (which, in some embodiments, could still be the entire row) that is read during a single read operation or programmed during a single programming operation (e.g., an upper or lower page of memory cells) might be deemed a logical page of memory cells. A block of memory cells might include those memory cells that are configured to be erased together, such as all memory cells connected to access lines2020-202N(e.g., all NAND strings206sharing common access lines202). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells.

Although the example ofFIG.2Ais discussed in conjunction with NAND flash, the embodiments and concepts described herein are not limited to a particular array architecture, and can include other architectures (e.g., AND arrays, NOR arrays, etc.).

FIG.2Bis another schematic of a portion of an array of memory cells200B as could be used in a memory of the type described with reference toFIG.1, e.g., as a portion of array of memory cells104. Like numbered elements inFIG.2Bcorrespond to the description as provided with respect toFIG.2A.FIG.2Bprovides additional detail of one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array200B might incorporate vertical structures which might include semiconductor pillars, which might be solid or hollow, where a portion of a pillar might act as a channel region of the memory cells of NAND strings206, e.g., a region through which current might flow when a memory cell, e.g., a field-effect transistor, is activated. The NAND strings206might be each selectively connected to a data line2040-204Mby a select transistor212(e.g., that might be drain select transistors, commonly referred to as select gate drain) and to a common source216by a select transistor210(e.g., that might be source select transistors, commonly referred to as select gate source). Multiple NAND strings206might be selectively connected to the same data line204. Subsets of NAND strings206can be connected to their respective data lines204by biasing the select lines2150-215Kto selectively activate particular select transistors212each between a NAND string206and a data line204. The select transistors210can be activated by biasing the select line214. Each access line202might be connected to multiple rows of memory cells of the memory array200B. Rows of memory cells that are commonly connected to each other by a particular access line202might collectively be referred to as tiers.

The three-dimensional NAND memory array200B might be formed over peripheral circuitry226. The peripheral circuitry226might represent a variety of circuitry for accessing the memory array200B. The peripheral circuitry226might include complementary circuit elements. For example, the peripheral circuitry226might include both n-channel region and p-channel region transistors formed overlying a same semiconductor substrate, a process commonly referred to as CMOS, or complementary metal-oxide-semiconductors. Although CMOS often no longer utilizes a strict metal-oxide-semiconductor construction due to advancements in integrated circuit fabrication and design, the CMOS designation remains as a matter of convenience.

FIG.3Adepicts various components of a memory cell of the related art. As depicted inFIG.3A, a memory cell might include a channel material (e.g., a semiconductor)352. The channel material352might function as a channel for future memory cells and other transistors having a same structure, and might include one or more semiconductor materials, which might be conductively doped to provide desired threshold voltage characteristics.

The memory cell ofFIG.3Amight further include a gate dielectric354adjacent to (e.g., immediately adjacent to and/or in direct contact with) the channel material352. The gate dielectric354might include one or more dielectric materials. As one example, the gate dielectric354might contain a first instance (354A) of silicon dioxide adjacent to the channel material352, an instance (354B) of silicon nitride adjacent to the first instance (354A) of silicon dioxide, and a second instance (354C) of silicon dioxide adjacent to the instance (354B) of silicon nitride. Such a structure might be referred to as a band-engineered gate dielectric.

The memory cell ofFIG.3Amight further include a charge-storage material356adjacent to (e.g., immediately adjacent to and/or in direct contact with) the gate dielectric354. The charge-storage material356might function as a charge-storage node for the memory cell and might include materials capable of storing a charge.

The memory cell ofFIG.3Amight further include a charge-blocking material358adjacent to (e.g., immediately adjacent to and/or in direct contact with) the charge-storage material356. The charge-blocking material358might function as a charge-blocking node for the memory cell, and might include dielectric material.

The memory cell ofFIG.3Amight further include a high-K dielectric360adjacent to (e.g., immediately adjacent to and/or in direct contact with) the charge-blocking material358. The high-K dielectric360might contain one or more high-K dielectric materials. High-K dielectric materials as used herein means a material having a dielectric constant greater than that of silicon dioxide.

The memory cell ofFIG.3Amight further include a control gate336adjacent to (e.g., immediately adjacent to and/or in direct contact with) the high-K dielectric360. The control gate336might be a portion of an access line of an array of memory cells. The control gate336might contain one or more conductive materials. In the example ofFIG.3A, the control gate336includes a conductive barrier362adjacent to (e.g., immediately adjacent to and/or in direct contact with) the high-K dielectric360, and a conductor364adjacent to (e.g., immediately adjacent to and/or in direct contact with) the conductive barrier362.

FIG.3Bdepicts an energy band diagram for the structure ofFIG.3A.FIG.3Bdepicts that a dipole layer366might be formed at an interface between the charge-blocking material358and the high-K dielectric360to mitigate back-tunneling of electrons from the control gate336.

Various embodiments seek to facilitate an improvement in erase saturation characteristics of a memory cell through the addition of a laminated dielectric between a control gate and a charge-blocking layer of the memory cell. The laminated dielectric might include alternating instances of a first dielectric material and of a second dielectric material. The first dielectric material might have a higher oxygen areal density than the second dielectric material. This differential in oxygen areal density might aid in the formation of additional dipole layers in the structure of a memory cell, which can lead to an improvement in erase saturation characteristics. The first dielectric material might further have higher dielectric constant than the second dielectric material.

FIG.4Adepicts various components of a memory cell in accordance with an embodiment. As depicted inFIG.4A, a memory cell might include a channel material (e.g., a semiconductor)352. The channel material352might function as a channel for the memory cell or other transistors having a same structure, and might include one or more semiconductor materials, which might be conductively doped to provide desired threshold voltage characteristics. The channel material352might include polycrystalline silicon, commonly referred to as polysilicon. Other semiconductor materials might include amorphous or monocrystalline silicon, or germanium in polycrystalline, amorphous, or monocrystalline forms, for example.

The memory cell ofFIG.4Amight further include a gate dielectric354adjacent to (e.g., immediately adjacent to and/or in direct contact with) the channel material352. The gate dielectric354might include one or more dielectric materials. The gate dielectric354might comprise, consist of, or consist essentially of an oxide, e.g., silicon dioxide (SiO2), and/or might comprise, consist of, or consist essentially of a high-K dielectric material, such as silicon nitride (Si3N4), an aluminum oxide (AlOx), a hafnium oxide (HfOx), a lanthanum oxide (LaOx), scandium(III) oxide (Sc2O3), a tantalum oxide (TaOx), a zirconium oxide (ZrOx), an aluminum hafnium oxide (AlHfOx), an aluminum zirconium oxide (AlZrOx), a hafnium silicon oxide (HfSiOx), a hafnium zirconium oxide (HfZrOx), a hafnium aluminum zirconium oxide (HfAlZrOx), or yttrium(III) oxide (Y2O3), as well as any other dielectric material. As one example, the gate dielectric354might contain a first instance (354A) of silicon dioxide adjacent to the channel material352, an instance (354B) of silicon nitride adjacent to the first instance (354A) of silicon dioxide, and a second instance (354C) of silicon dioxide adjacent to the instance (354B) of silicon nitride.

The memory cell ofFIG.4Amight further include a charge-storage material356adjacent to (e.g., immediately adjacent to and/or in direct contact with) the gate dielectric354. The charge-storage material356might function as a charge-storage node for the memory cell or other transistors having a same structure, and might include one or more conductive and/or dielectric materials capable of storing a charge. The charge-storage material356might further contain both dielectric and conductive materials, e.g., conductive nano-particles in a dielectric bulk material. For charge-storage material356containing a conductive material as its bulk, or contiguous, structure, resulting memory cells might typically be referred to as floating-gate memory cells. For charge-storage material356containing a dielectric material as its bulk, or contiguous, structure, resulting memory cells might typically be referred to as charge-trap memory cells.

The memory cell ofFIG.4Amight further include a charge-blocking material358adjacent to (e.g., immediately adjacent to and/or in direct contact with) the charge-storage material356. The charge-blocking material358might function as a charge-blocking node for future memory cells and other transistors having a same structure, and might comprise, consist of, or consist essentially of an oxide, e.g., silicon dioxide (SiO2), and/or might comprise, consist of, or consist essentially of a high-K dielectric material, such as silicon nitride (Si3N4), an aluminum oxide (AlOx), a hafnium oxide (HfOx), a lanthanum oxide (LaOx), scandium(III) oxide (Sc2O3), a tantalum oxide (TaOx), a zirconium oxide (ZrOx), an aluminum hafnium oxide (AlHfOx), an aluminum zirconium oxide (AlZrOx), a hafnium silicon oxide (HfSiOx), a hafnium zirconium oxide (HfZrOx), a hafnium aluminum zirconium oxide (HfAlZrOx), or yttrium(III) oxide (Y2O3), as well as any other dielectric material. As one example, the charge-blocking material358might include silicon dioxide. Collectively, the charge-blocking material358, the charge-storage material356, and the gate dielectric354might be referred to as a data-storage node.

The memory cell ofFIG.4Amight further include a laminated dielectric470adjacent to (e.g., immediately adjacent to and/or in direct contact with) the charge-blocking material358. The laminated dielectric470contains at least one instance of a first dielectric material472and at least one instance of a second dielectric material474different than the first dielectric material472. The embodiment depicted inFIG.4Acontains an instance of the first dielectric material472adjacent to (e.g., immediately adjacent to and/or in direct contact with) the charge-blocking material358, and an instance of the second dielectric material474adjacent to (e.g., immediately adjacent to and/or in direct contact with) the instance of the first dielectric material472. For embodiments of a laminated dielectric470having more than one instance of the first dielectric material472and/or more than one instance of the second dielectric material474, the instances of the first dielectric material472and the instances of the second dielectric material474are arranged in an alternating fashion such that each instance of the first dielectric material472is separated from any other instance of the first dielectric material472by an instance of the second dielectric material474, and each instance of the second dielectric material474is separated from any other instance of the second dielectric material474by an instance of the first dielectric material472. For some embodiments, each instance of the first dielectric material472and each instance of the second dielectric material474might have a respective thickness (e.g., measured left to right inFIG.4A) in a range of 0.5 nm to 5 nm.

The first dielectric material472has an oxygen areal density that is higher than an oxygen areal density of the second dielectric material474. For some embodiments, each instance of the first dielectric material472of a laminated dielectric470contains a same dielectric material. For some embodiments, each instance of the second dielectric material474of a laminated dielectric470contains a same dielectric material. However, different instances of the first dielectric material472of a laminated dielectric470could utilize different dielectric materials provided that each instance of the first dielectric material472has a higher oxygen areal density than each immediately adjacent instance of the second dielectric material474of the laminated dielectric470, and different instances of the second dielectric material474of a laminated dielectric470could utilize different dielectric materials provided that each instance of the second dielectric material474has a lower oxygen areal density than each immediately adjacent instance of the first dielectric material472of the laminated dielectric470.

InFIG.4A, an electric dipole layer might be formed at the interface between the instance of the first dielectric material472and the instance of the second dielectric material474due to the oxygen density difference. The dipole layer formation may be driven by the migration or displacement of negatively charged oxygen ions from the material with the higher oxygen density to the material with the lower oxygen density. This dipole layer might induce flat band voltage (Vfb) shift, which might facilitate an increase of potential barrier between the control gate and the channel of a memory cell and an increase of the effective work function (eWF) of a metal control gate. As a result, erase saturation characteristics might be improved. Embodiments incorporating more than one instance of the first dielectric material472and more than one instance of the second dielectric material474might further improve this Vfb shift and erase saturation characteristics by forming additional dipole layers.

Examples of dielectric material for instances of the first dielectric material472might include scandium(III) oxide (Sc2O3), magnesium oxide (MgO), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), and aluminum(III) oxide (Al2O3), although other dielectric materials could also be used. Examples of dielectric material for instances of the second dielectric material474might include silicon dioxide (SiO2) and germanium dioxide (GeO2), although other dielectric materials could also be used. For some embodiments, the oxygen areal density of the first dielectric material472is greater than or equal to 20% higher than the oxygen areal density of the second dielectric material474. Higher differentials in oxygen areal density might be expected to produce higher levels of effect of the formed dipole layer.

The memory cell ofFIG.4Amight further include a high-K dielectric360adjacent to (e.g., immediately adjacent to and/or in direct contact with) the laminated dielectric470. The high-K dielectric360might contain one or more high-K dielectric materials. For example, the high-K dielectric360might comprise, consist of, or consist essentially of a high-K dielectric material, such as an aluminum oxide (AlOx), a hafnium oxide (HfOx), a lanthanum oxide (LaOx), scandium(III) oxide (Sc2O3), a tantalum oxide (TaOx), a zirconium oxide (ZrOx), an aluminum hafnium oxide (AlHfOx), an aluminum zirconium oxide (AlZrOx), a hafnium silicon oxide (HfSiOx), a hafnium zirconium oxide (HfZrOx), a hafnium aluminum zirconium oxide (HfAlZrOx), or yttrium(III) oxide (Y2O3), as well as any other high-K dielectric material. The high-K dielectric360might be a different dielectric material than one or more, which might include all, instances of the first dielectric material472. Alternatively, the high-K dielectric360might be a same dielectric material as one or more, which might include all, instances of the first dielectric material472. For some embodiments, the high-K dielectric360might have a higher oxygen areal density than an instance of the second dielectric material474adjacent to (e.g., immediately adjacent to and/or in direct contact with) the high-K dielectric360. For some embodiments, the high-K dielectric360comprises a dielectric material selected from a group consisting of aluminum(III) oxide (Al2O3), a hafnium oxide (HfOx), scandium(III) oxide (Sc2O3), tantalum pentoxide (Ta2O5), a zirconium oxide (ZrOx), an aluminum hafnium oxide (AlHfOx), an aluminum zirconium oxide (AlZrOx), a hafnium zirconium oxide (HfZrOx), and a hafnium aluminum zirconium oxide (HfAlZrOx).

The memory cell ofFIG.4Amight further include a control gate336adjacent to (e.g., immediately adjacent to and/or in direct contact with) the high-K dielectric360. The control gate336might be a portion of an access line of an array of memory cells. The control gate336might contain one or more conductive materials. The control gate336might comprise, consist of, or consist essentially of conductively doped polysilicon. Alternatively or in addition, the control gate336might comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material. The metals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti), tungsten (W), vanadium (V) and zirconium (Zr) are generally recognized as refractory metals. In the example ofFIG.4A, the control gate336includes a conductive barrier362adjacent to (e.g., immediately adjacent to and/or in direct contact with) the high-K dielectric360, and a conductor364adjacent to (e.g., immediately adjacent to and/or in direct contact with) the conductive barrier362. For example, the conductive barrier362might contain titanium nitride, and the conductor364might contain tungsten.

FIG.4Bdepicts an energy band diagram for the structure ofFIG.4A.FIG.4Bdepicts that a first dipole layer4660might be formed at an interface between the charge-blocking material358and an instance of the first dielectric material472, and a second dipole layer4661might be formed at an interface between an instance of the second dielectric material474and the high-K dielectric360to mitigate back-tunneling of electrons from the control gate336. Additional dipole layers (not shown inFIG.4B) might be formed by inserting additional alternating instances of the first dielectric material472and of the second dielectric material474in the laminated dielectric470.

FIG.5depicts a graph of normalized oxygen areal density as a function of cation radius of a number of dielectric materials that might be suitable candidates for the instances of the first dielectric material472and for the instances of the second dielectric material474. The values of oxygen areal density are normalized to the oxygen areal density of silicon dioxide having a value of 1. Using the example of silicon dioxide as an instance of the second dielectric material474, and only looking to dielectric materials represented inFIG.5, an adjacent (e.g., immediately adjacent) instance of the first dielectric material472might be selected from a group of dielectric materials including scandium(III) oxide (Sc2O3), magnesium oxide (MgO), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), and aluminum(III) oxide (Al2O3). Continuing the example, and further restricting the dielectric materials represented inFIG.5to those having an oxygen areal density of greater than or equal to 20% higher than the oxygen areal density of silicon dioxide, the adjacent (e.g., immediately adjacent) instance of the first dielectric material472might be selected from a group of dielectric materials including hafnium dioxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), and aluminum(III) oxide (Al2O3).

FIG.6Adepicts a cross-sectional view of a memory array structure to aid description of various embodiments. For example, the memory array structure might correspond to a portion (e.g., upper or drain-side portion) of a string of series-connected memory cells and corresponding drain select gates depicting connectivity to a data line.FIG.6Bdepicts an exploded portion of the memory array structure ofFIG.6Aproviding additional detail of a memory cell structure within the memory array structure. Like numbered elements inFIGS.6A-6Bcorrespond to the description as provided with respect toFIG.4A.

As noted, memory cells and select gates might utilize a same structure, e.g., the structure of a programmable field-effect transistor (FET). These transistors might be formed from alternating layers of conductive materials and dielectric materials, formed around a pillar that acts as a common channel for the transistors, and which might be hollow.

InFIG.6A, a transistor might be formed at each intersection of a control gate336and a channel-material structure680. Although the channel-material structure680inFIG.6Ais depicted as a hollow pillar containing a void682, the channel-material structure680could alternatively be a solid pillar. The channel-material structure680might include a charge-blocking material358, a charge-storage material356, a gate dielectric354, and a channel material352. The portion684is depicted in further detail inFIG.6B. The instances of control gates336might be isolated from one another by instances of a dielectric686.

Each instance of control gate336might be formed of one or more conductive materials. A control gate336might comprise, consist of, or consist essentially of conductively doped polysilicon. Alternatively or in addition, each control gate336might comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material.

Each instance of dielectric686might be formed of one or more dielectric materials. A dielectric686might comprise, consist of, or consist essentially of an oxide, e.g., silicon dioxide (SiO2), and/or might comprise, consist of, or consist essentially of a high-K dielectric material, such as silicon nitride (Si3N4), an aluminum oxide (AlOx), a hafnium oxide (HfOx), a lanthanum oxide (LaOx), scandium(III) oxide (Sc2O3), a tantalum oxide (TaOx), a zirconium oxide (ZrOx), an aluminum hafnium oxide (AlHfOx), an aluminum zirconium oxide (AlZrOx), a hafnium silicon oxide (HfSiOx), a hafnium zirconium oxide (HfZrOx), a hafnium aluminum zirconium oxide (HfAlZrOx), or yttrium(III) oxide (Y2O3), as well as any other dielectric material. A dielectric686might further comprise, consist of, or consist essentially of a spin-on dielectric material, e.g., hydrogen silsesquioxane (HSQ), hexamethyldisiloxane, octamethyltrisiloxane, etc., or a high-density-plasma (HDP) oxide. As one example, the dielectric686might contain silicon dioxide.

For embodiments utilizing a hollow channel-material structure680, a dielectric688might be formed inside the channel-material structure680to close access to the void682from subsequently formed materials. The dielectric688might comprise, consist of, or consist essentially of an oxide, e.g., silicon dioxide (SiO2). The dielectric688might further comprise, consist of, or consist essentially of a spin-on dielectric material, e.g., hydrogen silsesquioxane (HSQ), hexamethyldisiloxane, octamethyltrisiloxane, etc., or a high-density-plasma (HDP) oxide. The dielectric688might further comprise, consist of, or consist essentially of any other dielectric material. The dielectric688might contain one or more dielectric materials that can be selectively removed without adversely affecting the materials of the instances of dielectric686, the materials of the channel-material structure680. Although depicted to be in contact with the entire length of the depicted channel-material structure680, the dielectric688might not extend a full length of the channel-material structure680. For example, the dielectric688might pinch off at the top of the void682before sufficient dielectric688can enter lower portions of the void682.

A conductive plug690might be formed overlying the dielectric688to be electrically connected to the channel material352of the channel-material structure680. The conductive plug690might contain one or more conductive materials. The conductive plug690might comprise, consist of, or consist essentially of conductively doped polysilicon and/or might comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material. For some embodiments, the conductive plug690might contain an n+-type conductively-doped polysilicon.

As depicted inFIG.6B, the channel-material structure680of the portion684might include a charge-blocking material358formed adjacent to, and surrounded by, the instances of control gates336and dielectrics686, e.g., overlying the sidewalls of the void682. For example, the charge-blocking material358might be formed overlying sidewalls of the void682. A charge-storage material356might be formed overlying the charge-blocking material358, a gate dielectric354might be formed overlying the charge-storage material356, and a channel material (e.g., a semiconductor)352might be formed overlying the gate dielectric354. The channel material352might be a portion of a contiguous semiconductor structure for each transistor formed around the channel-material structure680, or might otherwise be electrically connected, which might include selectively electrically connected, to channels of each such transistor. The channel material352might have a conductivity type, e.g., a p-type conductivity or an n-type conductivity. For some embodiments, the channel material352might contain an n+-type conductively-doped polysilicon. For embodiments utilizing a solid channel-material structure680, the channel material352might be formed to fill the void682, and the dielectric688might be eliminated. For embodiments utilizing a hollow channel-material structure680, the dielectric688might be formed overlying at least a portion of the channel material352.

A laminated dielectric470might be formed to be adjacent the charge-blocking material358, a high-K dielectric360might be formed to be adjacent to the laminated dielectric470, and a control gate336might be formed to be adjacent to the high-K dielectric360. Although not depicted inFIGS.6A-6B, each instance of the control gate336might include more than one conductive layer, such as depicted inFIG.4A. For example, for a control gate336, a conductive barrier might be formed to be adjacent to the high-K dielectric360, and a conductor might be formed to be adjacent to the conductive barrier. Continuing with the example, the conductive barrier might contain titanium nitride, and the conductor might contain tungsten.

A contact (e.g., contact plug)692might be formed in a dielectric694, and might be overlying and in physical contact with the channel-material structure680, and in electrical contact with its channel material352. The contact692might be further overlying and in electrical contact with the conductive plug690. The contact692might contain one or more conductive materials, such as described with reference to the control gates336. As one example, the contact692might comprise, consist of, or consist essentially of a conductively-doped semiconductor material, such as conductively-doped polysilicon. The dielectric694might contain one or more dielectric materials, such as described with reference to the dielectric686. As one example, the dielectric694might comprise, consist of, or consist essentially of silicon dioxide.

A contact (e.g., contact via)696might be formed in a dielectric698, and might be overlying and in electrical contact with the contact692. The contact696might further be in physical contact with the contact692. The contact696might contain one or more conductive materials, such as described with reference to the control gates336. As one example, the contact696might comprise, consist of, or consist essentially of a conductively-doped semiconductor material, such as conductively-doped polysilicon. For example, the contact692and the contact696might both contain conductively-doped polysilicon of a same conductivity type. Alternatively or in addition, the contact696might comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material. The dielectric698might contain one or more dielectric materials, such as described with reference to the dielectric686. As one example, the dielectric698might comprise, consist of, or consist essentially of silicon dioxide.

A data line204might be formed to be overlying and in electrical contact with the contact696. The data line204might further be in physical contact with the contact696. The data line204might contain one or more conductive materials, such as described with reference to the control gates336. As one example, the data line204might comprise, consist of, or consist essentially of a refractory metal, such as tungsten.

InFIGS.6A-6B, the laminated dielectric470is formed to surround the control gate336. Alternatively, the laminated dielectric470might be formed as part of the channel-material structure680.FIGS.7A-7Bdepict placing the laminated dielectric470within the channel-material structure680.

FIG.7Adepicts a cross-sectional view of a memory array structure to aid description of various embodiments. For example, the memory array structure might correspond to a portion (e.g., upper or drain-side portion) of a string of series-connected memory cells and corresponding drain select gates depicting connectivity to a data line.FIG.7Bdepicts an exploded portion of the memory array structure ofFIG.7Aproviding additional detail of a memory cell structure within the memory array structure. Like numbered elements inFIGS.7A-7Bcorrespond to the description as provided with respect toFIGS.6A-6B.

InFIG.7A, a transistor might be formed at each intersection of a control gate336and a channel-material structure680. Although the channel-material structure680inFIG.7Ais depicted as a hollow pillar containing a void682, the channel-material structure680could alternatively be a solid pillar. The channel-material structure680might include a laminated dielectric470, a charge-blocking material358, a charge-storage material356, a gate dielectric354, and a channel material352. The portion684′ is depicted in further detail inFIG.7B. The instances of control gates336might be isolated from one another by instances of a dielectric686.

Each instance of control gate336might be formed of one or more conductive materials. A control gate336might comprise, consist of, or consist essentially of conductively doped polysilicon. Alternatively or in addition, each control gate336might comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material.

Each instance of dielectric686might be formed of one or more dielectric materials. A dielectric686might comprise, consist of, or consist essentially of an oxide, e.g., silicon dioxide (SiO2), and/or might comprise, consist of, or consist essentially of a high-K dielectric material, such as silicon nitride (Si3N4), an aluminum oxide (AlOx), a hafnium oxide (HfOx), a lanthanum oxide (LaOx), scandium(III) oxide (Sc2O3), a tantalum oxide (TaOx), a zirconium oxide (ZrOx), an aluminum hafnium oxide (AlHfOx), an aluminum zirconium oxide (AlZrOx), a hafnium silicon oxide (HfSiOx), a hafnium zirconium oxide (HfZrOx), a hafnium aluminum zirconium oxide (HfAlZrOx), or yttrium(III) oxide (Y2O3), as well as any other dielectric material. A dielectric686might further comprise, consist of, or consist essentially of a spin-on dielectric material, e.g., hydrogen silsesquioxane (HSQ), hexamethyldisiloxane, octamethyltrisiloxane, etc., or a high-density-plasma (HDP) oxide. As one example, the dielectric686might contain silicon dioxide.

For embodiments utilizing a hollow channel-material structure680, a dielectric688might be formed inside the channel-material structure680to close access to the void682from subsequently formed materials. The dielectric688might comprise, consist of, or consist essentially of an oxide, e.g., silicon dioxide (SiO2). The dielectric688might further comprise, consist of, or consist essentially of a spin-on dielectric material, e.g., hydrogen silsesquioxane (HSQ), hexamethyldisiloxane, octamethyltrisiloxane, etc., or a high-density-plasma (HDP) oxide. The dielectric688might further comprise, consist of, or consist essentially of any other dielectric material. The dielectric688might contain one or more dielectric materials that can be selectively removed without adversely affecting the materials of the instances of dielectric686, the materials of the channel-material structure680. Although depicted to be in contact with the entire length of the depicted channel-material structure680, the dielectric688might not extend a full length of the channel-material structure680. For example, the dielectric688might pinch off at the top of the void682before sufficient dielectric688can enter lower portions of the void682.

A conductive plug690might be formed overlying the dielectric688to be electrically connected to the channel material352of the channel-material structure680. The conductive plug690might contain one or more conductive materials. The conductive plug690might comprise, consist of, or consist essentially of conductively doped polysilicon and/or might comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material. For some embodiments, the conductive plug690might contain an n+-type conductively-doped polysilicon.

As depicted inFIG.7B, the channel-material structure680of the portion684′ might include a laminated dielectric470formed adjacent to, and surrounded by, the instances of control gates336and dielectrics686. For example, the laminated dielectric470might be formed overlying sidewalls of the void682. A charge-blocking material358might be formed overlying the laminated dielectric470, a charge-storage material356might be formed overlying the charge-blocking material358, a gate dielectric354might be formed overlying the charge-storage material356, and a channel material (e.g., a semiconductor)352might be formed overlying the gate dielectric354. The channel material352might be a portion of a contiguous semiconductor structure for each transistor formed around the channel-material structure680, or might otherwise be electrically connected, which might include selectively electrically connected, to channels of each such transistor. The channel material352might have a conductivity type, e.g., a p-type conductivity or an n-type conductivity. For some embodiments, the channel material352might contain an n″-type conductively-doped polysilicon. For embodiments utilizing a solid channel-material structure680, the channel material352might be formed to fill the void682, and the dielectric688might be eliminated. For embodiments utilizing a hollow channel-material structure680, the dielectric688might be formed overlying at least a portion of the channel material352.

The high-K dielectric360might be formed to be adjacent to the laminated dielectric470, and the control gate336might be formed to be adjacent to the high-K dielectric360. Although not depicted inFIGS.7A-7B, each instance of the control gate336might include more than one conductive layer, such as depicted inFIG.4A. For example, for a control gate336, a conductive barrier might be formed to be adjacent to the high-K dielectric360, and a conductor might be formed to be adjacent to the conductive barrier. Continuing with the example, the conductive barrier might contain titanium nitride, and the conductor might contain tungsten.

A contact (e.g., contact plug)692might be formed in a dielectric694, and might be overlying and in physical contact with the channel-material structure680, and in electrical contact with its channel material352. The contact692might be further overlying and in electrical contact with the conductive plug690. The contact692might contain one or more conductive materials, such as described with reference to the control gates336. As one example, the contact692might comprise, consist of, or consist essentially of a conductively-doped semiconductor material, such as conductively-doped polysilicon. The dielectric694might contain one or more dielectric materials, such as described with reference to the dielectric686. As one example, the dielectric694might comprise, consist of, or consist essentially of silicon dioxide.

A contact (e.g., contact via)696might be formed in a dielectric698, and might be overlying and in electrical contact with the contact692. The contact696might further be in physical contact with the contact692. The contact696might contain one or more conductive materials, such as described with reference to the control gates336. As one example, the contact696might comprise, consist of, or consist essentially of a conductively-doped semiconductor material, such as conductively-doped polysilicon. For example, the contact692and the contact696might both contain conductively-doped polysilicon of a same conductivity type. Alternatively or in addition, the contact696might comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material. The dielectric698might contain one or more dielectric materials, such as described with reference to the dielectric686. As one example, the dielectric698might comprise, consist of, or consist essentially of silicon dioxide.

A data line204might be formed to be overlying and in electrical contact with the contact696. The data line204might further be in physical contact with the contact696. The data line204might contain one or more conductive materials, such as described with reference to the control gates336. As one example, the data line204might comprise, consist of, or consist essentially of a refractory metal, such as tungsten.

Although the embodiment ofFIGS.6A-6Bplaced the laminated dielectric either entirely outside of the channel-material structure680, and the embodiment ofFIGS.7A-7Bplaced the laminated dielectric either entirely within the channel-material structure680, a combination could be used. For example, a portion of the structure of a laminated dielectric470might be formed within the channel-material structure680as depicted inFIG.7B, and a remaining portion of the structure of the laminated dielectric470might be formed outside of the channel-material structure680as depicted inFIG.6B.

FIG.8Adepicts various components of a memory cell in accordance with an embodiment.FIG.8Adepicts an example of a laminated dielectric470including more than one instance of the first dielectric material472and more than one instance of the second dielectric material474. As depicted inFIG.8A, the laminated dielectric470includes X+1 instances of the first dielectric material472and X+1 instances of the second dielectric material474. The value X might be any integer value greater than or equal to one.

FIG.8Bdepicts various components of a memory cell in accordance with another embodiment. For embodiments where dipole layer formation is not anticipated at an interface between the charge-blocking material358and an immediately adjacent instance of the first dielectric material472, an instance of the second dielectric material474might be formed between the charge-blocking material358and the instance of the first dielectric material472.FIG.8Bdepicts such an embodiment.FIG.8Bdepicts an example of a laminated dielectric470including more than one instance of the first dielectric material472and more than one instance of the second dielectric material474. As depicted inFIG.8B, the laminated dielectric470includes X+1 instances of the first dielectric material472and X+2 instances of the second dielectric material474. The value X might be any integer value greater than or equal to zero.

While a dipole layer might be formed at an interface from an instance of the second dielectric material474to an instance of the first dielectric material472in a direction toward the control gate336(e.g., left to right inFIGS.8A-8B), an opposite dipole layer might be formed at an interface from the instance of the second dielectric material474to an instance of the first dielectric material472in a direction away from the control gate336(e.g., right to left inFIGS.8A-8B). The formation of opposite dipole layers on both sides of an instance of the second dielectric material474could be counter-productive to improving erase saturation characteristics. However, formation of an opposite dipole layer might be mitigated by forming the interfaces to have characteristics favorable to dipole layer formation when transitioning from an instance of the second dielectric material474to an instance of the first dielectric material472in a direction toward the control gate336, and to have characteristics less favorable to dipole layer formation when transitioning from an instance of the first dielectric material472to an instance of the second dielectric material474in the direction toward the control gate336. For example, a transition from the second dielectric material474to the first dielectric material474might be more abrupt for one case than the other in terms of concentration of materials and/or in terms of surface roughness.

FIG.9Adepicts different interfaces of an embodiment for use in discussing differences in concentration of dielectric materials across interfaces. The example ofFIG.9Adepicts a laminated dielectric470containing two instances of the first dielectric material472, e.g., instances of the first dielectric material4720and4721, and two instances of the second dielectric material474, e.g., instances of the second dielectric material4740and4741. In the example ofFIG.9A, there might be a first interface9010between the charge-blocking material358and the first instance of the first dielectric material4720, a second interface9011between the first instance of the first dielectric material4720and the first instance of the second dielectric material4740, a third interface9012between the first instance of the second dielectric material4740and the second instance of the first dielectric material4721, a fourth interface9013between the second instance of the first dielectric material4721and the second instance of the second dielectric material4741, and a fifth interface9014between the second instance of the second dielectric material4741and the high-K dielectric360.

InFIG.9A, a cross-section903of the second interface9011might have a depth, e.g., left to right inFIG.9A, and a cross-section905of the third interface9012might have a depth, e.g., left to right inFIG.9A.FIG.9Bdepicts a graph of concentration of the first dielectric material472and of the second dielectric material474across the cross-section903of the second interface9011. To produce a concentration profile such as depicted inFIG.9B, a formation rate of the first dielectric material472might be reduced gradually while a formation rate of the second dielectric material474might be increased gradually.FIG.9Cdepicts a graph of concentration of the first dielectric material472and of the second dielectric material474across the cross-section905of the third interface9012. To produce a concentration profile such as depicted inFIG.9C, a formation rate of the second dielectric material474might be reduced abruptly while a formation rate of the first dielectric material472might be increased abruptly, or the formation of the second dielectric material474might be stopped before initiating formation of the first dielectric material472. The fourth interface9013might have a concentration profile similar to the graph ofFIG.9B, e.g., similar to the second interface9011. The first interface9010and the fifth interface9014might have concentration profiles of their respective materials that might be similar to the graph ofFIG.9C, similar to the third interface9012.

FIG.10depicts different interfaces of an embodiment for use in discussing differences in surface roughness of interfaces. The example ofFIG.10depicts a laminated dielectric470containing two instances of the first dielectric material472, e.g., instances of the first dielectric material4720and4721, and two instances of the second dielectric material474, e.g., instances of the second dielectric material4740and4741. In the example ofFIG.10, there might be a first interface9070between the charge-blocking material358and the first instance of the first dielectric material4720, a second interface9011between the first instance of the first dielectric material4720and the first instance of the second dielectric material4740, a third interface9012between the first instance of the second dielectric material4740and the second instance of the first dielectric material4721, a fourth interface9013between the second instance of the first dielectric material4721and the second instance of the second dielectric material4741, and a fifth interface9014between the second instance of the second dielectric material4741and the high-K dielectric360.

InFIG.10, the second interface9011might have a first level of surface roughness, illustrated conceptually as a wavy line, while the third interface9012might have a second level of surface roughness, lower than the first level of surface roughness, illustrated conceptually as a straight line. Lower levels of surface roughness might be associated with more favorable conditions for formation of a dipole layer than higher levels of surface roughness. The fourth interface9013might have a level of surface roughness similar to the level of surface roughness of the second interface9011. The first interface9010and the fifth interface9014might have levels of surface roughness similar to the level of surface roughness of the third interface9012. Variations of surface roughness might be produced by changing reaction conditions, e.g., pressure and/or temperature, during formation of the materials.

FIGS.11A-11Ndepict a memory array structure, which might correspond to a portion of the structure ofFIG.6A, during various stages of fabrication in accordance with an embodiment.FIGS.11A-11Nmight be used to describe fabrication of an array of memory cells and associated transistors in accordance with an embodiment, for example. Although transistors depicted to be formed inFIGS.11A-11Nmight typically correspond to select gates or GIDL generator gates, their formation as detailed inFIGS.11A-11Nis descriptive of the process to form memory cells.

InFIG.11A, instances of a dielectric686and instances of a sacrificial material1004might be formed in an alternating manner. The instances of the sacrificial material1004might contain a material that can be subjected to removal without significantly affecting the material(s) of the dielectric686or exposed materials of a future channel-material structure680. As one example, the instances of the sacrificial material1004might contain silicon nitride for instances of the dielectric686containing silicon dioxide. Additional instances of the dielectric686and instances of the sacrificial material1004might be formed, depending upon the number of transistors intended to be formed, e.g., memory cells, dummy memory cells, GIDL generator gates, and select gates. While all intended instances of the dielectric686and instances of the sacrificial material1004might be formed before proceeding to the processing ofFIG.11B, typical processing of such stacked structures might be performed in stages as the aspect ratio of a via formed through the instances of the dielectric686and the instances of the sacrificial material1004might become too large to form the entire structure reliably as a contiguous entity.

InFIG.11B, a via or void682might be formed through the instances of the dielectric686and the instances of the sacrificial material1004. For example, an anisotropic removal process, e.g., reactive ion etching (RIE), might be used with a contact to the common source216(not depicted inFIG.11B) acting as an etch stop. As such, the void682might extend through all instances of the dielectric686and through all instances of the sacrificial material1004.

InFIG.11C, a channel-material structure680might be formed to line the sidewalls of the void682, e.g., formed overlying the sidewalls of the instances of the dielectric686and the instances of the sacrificial material1004. The channel-material structure680might have a structure such as depicted inFIG.6B. Formation of the channel-material structure680will be described in more detail with reference toFIGS.12A-12F.

InFIG.11D, the dielectric688might be formed in the void682. The dielectric688might be deposited overlying the structure ofFIG.11C, and then removed to the level of an upper surface of the upper instance of dielectric686, such as by chemical-mechanical planarization (CMP). A portion of the void682might remain after forming the dielectric688.

InFIG.11E, a portion of the dielectric688might be removed to recess the upper surface of the dielectric688. For example, the dielectric688might be recessed to expose portions of the channel-material structure680, and its channel material352, to a level of the upper instance of sacrificial material1004. To recess the dielectric688, the structure ofFIG.11Dmight be subjected to an isotropic or anisotropic removal process for a particular time expected to recess the dielectric688level of the upper instance of sacrificial material1004. The time expected to result in a desired level of recessing might, for example, be determined experimentally, empirically or through simulation. Isotropic removal processes might involve wet etching processes, e.g., exposing the structure ofFIG.11Dto a dilute hydrofluoric acid (HF) solution (e.g., 100:1 H2O:HF). Isotropic removal processes might alternatively involve dry etching processes, e.g., exposing the structure ofFIG.11Dto an oxygen-rich plasma (e.g., 10-100% oxygen by volume). Anisotropic removal processes might involve reactive ion etching. InFIG.11F, a conductive plug690might be formed overlying the dielectric688and electrically connected to the channel material352of the channel-material structure680.

InFIG.11G, the instances of sacrificial material1004might be removed to define voids1006. The removal might include an isotropic removal process, e.g., a plasma etching process. InFIG.11H, instances of the laminated dielectric470might be formed to line the voids1006. Formation of an instance of the laminated dielectric470might include forming an instance of the first dielectric material472overlying exposed surfaces of adjacent instances of the dielectric686and the exposed surface of an adjacent portion of the channel-material structure680, and forming an instance of the second dielectric material474overlying the instance of the first dielectric material472. This process could be repeated to produce a desired number of instances of the first dielectric material472and the second dielectric material474formed in an alternating manner. InFIG.11I, instances of the high-K dielectric360might be formed in the voids1006overlying the instances of the laminated dielectric470. InFIG.11J, instances of the conductive barrier362might be formed in the voids1006overlying the instances of the high-K dielectric360. And inFIG.11K, instances of the conductor364might be formed in the voids1006overlying the instances of the conductive barrier362. The process ofFIGS.11G-11Kmight be referred to as a replacement gate process, e.g., replacing instances of the sacrificial material with control gates for the transistors.

InFIG.11L, the contact (e.g., contact plug)692might be formed in a dielectric694, and might be overlying and in physical contact with the channel-material structure680, and in electrical contact with its channel material352. The contact692might further be overlying and in electrical contact with the conductive plug690. InFIG.11M, the contact (e.g., contact via)696might be formed in a dielectric698, and might be overlying and in electrical contact with the contact692. And inFIG.11N, the data line204might be formed to be overlying and in electrical contact with the conductive via696.

FIGS.12A-12Fdepict a memory array structure during various stages of fabrication in accordance with an embodiment.FIGS.12A-12Fmight depict how a memory array structure formed as described with reference toFIGS.11A-11Ncould be connected to a common source216.

IfFIG.12A, a dielectric1210might be formed overlying a common source216, and a contact (e.g., contact plug)1212might be formed in the dielectric1210. The contact1212might be overlying and electrically connected to the common source216. The contact1212might contain one or more conductive materials, such as described with reference to the control gates336. As one example, the contact1212might comprise, consist of, or consist essentially of a conductively-doped semiconductor material, such as conductively-doped polysilicon. The dielectric1210might contain one or more dielectric materials, such as described with reference to the dielectric686. As one example, the dielectric1210might comprise, consist of, or consist essentially of silicon dioxide.

InFIG.12B, the instances of the dielectric686and the instances of the sacrificial material1004might be formed in an alternating manner (e.g., as described with reference toFIG.11A) overlying the dielectric1210and the contact1212. InFIG.12C, the via or void682might be formed through the instances of the dielectric686and the instances of the sacrificial material1004as described with reference toFIG.11B. The void682might expose the contact1212.

InFIG.12D, the charge-blocking material358might be formed overlying the sidewalls of the void682(e.g., sidewalls of the instances of the dielectric686and the instances of the sacrificial material1004) and formed overlying the contact1212. The charge-storage material356might be formed overlying the charge-blocking material358, and the gate dielectric354might be formed overlying the charge-storage material356.

InFIG.12E, a portion of the charge-blocking material358, the charge-storage material356, and the gate dielectric354might be removed to expose at least a portion of the contact1212. For example, a portion of the contact1212might be exposed by subjecting the structure ofFIG.12Dto an anisotropic removal process, such as reactive ion etching. InFIG.12F, the channel material352might be formed overlying remaining portions of the gate dielectric354and overlying the exposed portion of the contact1212. The channel material352might be electrically connected to the contact1212, and thus electrically connected to the common source216. The charge-blocking material358, the charge-storage material356, the gate dielectric354, and the channel material352overlying the sidewalls of the void682might collectively correspond to the channel-material structure680. Further processing could proceed as described with reference toFIGS.11D-11Nto form all memory cells of a NAND string and their corresponding select gates and other transistors for selective connection to the data line204and to the common source216.

CONCLUSION

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose might be substituted for the specific embodiments shown. Many adaptations of the embodiments will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the embodiments.