POWER DEVICE AND METHOD OF MANUFACTURING THE SAME

Provided are a power device and a manufacturing method thereof. A power device includes a compound semiconductor layer epitaxially grown on a substrate, a gate formed on the compound semiconductor layer, a source and a drain provided on either side of the gate, a passivation layer provided to cover the source, drain, and gate, and a cooling space region provided to form a cooling path inside the substrate. The cooling space region may be formed to a predetermined depth from the surface of the substrate and include an enlargement region having a width increasing according to a depth from the surface of the substrate. The width of an inlet of the cooling space region is less than a maximum width of the enlargement region, and the passivation layer and the compound semiconductor layer are provided to open the cooling space region.

CROSS-REFERENCE TO RELATED APPLICATION

BACKGROUND

The disclosure relates to a power device and a method of manufacturing the same.

2. Description of the Related Art

Generally, a power conversion system includes a power device that controls the flow of current through on/off switching. In the power conversion system, the efficiency of the power device may determine the efficiency of the entire system.

A power device based on silicon (Si) may not increase the efficiency of the entire system due to limitations in the physical properties of silicon and limitations in a manufacturing process. In order to overcome these limitations, research and development have been conducted to increase the conversion efficiency by applying a compound semiconductor to a power device. In the case of a power device to which a compound semiconductor is applied, the efficiency tends to decrease as the temperature increases, and various methods have been attempted to prevent this.

SUMMARY

Provided are a power device including a cooling system and a method of manufacturing the power device including the cooling system.

According to an aspect of the disclosure, there is provided a power device including: a substrate; a compound semiconductor layer epitaxially grown on the substrate; a gate formed on the compound semiconductor layer; a source provided on a first side of the gate and a drain provided on a second side of the gate; a passivation layer provided to on the source, drain, and gate; and a cooling space region configured to form a cooling path inside the substrate, wherein the cooling space region comprises an enlargement region having a width, which increases according to a depth from a surface of the substrate, wherein the width of an inlet of the cooling space region is less than a maximum width of the enlargement region, and wherein the passivation layer and the compound semiconductor layer are configured to form an opening for the cooling space region.

The power device may further include one or more trenches formed on the passivation layer and the compound semiconductor layer, and may be connected to the cooling space region.

The cooling space region may be connected to outside through the one or more trenches to form a cooling path.

The power device may further include a pump structure provided to form an inner space openly connected to the cooling space region on the passivation layer; and a cooling fluid filling an inner space of the pump structure and the cooling space region, wherein the cooling fluid flows according to driving of the pump structure to form a cooling path in the cooling space region and the inner space of the pump structure.

The pump structure may include: a first plate with a plurality of openings corresponding to the plurality of trenches to be openly connected to the cooling space region; a second plate spaced apart from the first plate to form an inner space of the pump structure; a sidewall connecting the first plate with the second plate; and a piezoelectric member provided on the second plate.

The passivation layer and the layer below the passivation layer may be diced at a position spaced apart from both ends of the gate to open the cooling space region.

The width of the inlet of the cooling space region may have a critical size for allowing epitaxial growth on the substrate.

The power device may further include a blocking layer formed in the inlet of the cooling space region, the blocking layer comprising a material of the substrate.

The substrate may be a Si-based substrate, and the blocking layer may include the material comprising one of Si, SiN, or SiO.

The compound semiconductor layer may include a GaN-based material, and may form a channel.

According to another aspect of the disclosure, there is provided a method of manufacturing a power device, the method including: preparing a substrate; forming a cooling path inside the substrate by forming a cooling space region including an enlargement region having a width, which increases according to a depth from a surface of the substrate and a width of an inlet of the cooling space region is less than a maximum width of the enlargement region; epitaxially growing a compound semiconductor layer on the substrate on which the cooling space region is formed; forming a gate on the compound semiconductor layer; forming a source on a first side of the gate; forming a drain on a second side of the gate; forming a passivation layer on the source, the drain, and the gate, and opening the cooling space region through the passivation layer and the compound semiconductor layer.

The forming of the cooling space region may include: forming a mask pattern having an opening at a position corresponding to an inlet of the cooling space region on the substrate; forming a trench by performing a first etching process on the substrate; forming a second passivation layer in a region including an opening of the mask pattern and an inlet of the cooling space region; and performing a second etching process on the substrate to increase the depth and width of the trench, wherein the forming of the second passivation layer and the performing of the second etching process are performed at least once to form the cooling space region.

The method may further include forming a plurality of trenches in the passivation layer and the compound semiconductor layer to form an opening for the cooling space region.

The method may further include forming a pump structure on the passivation layer to form an inner space openly connected to the cooling space region through the plurality of trenches; and filling the cooling space region and an inner space of the pump structure with a cooling fluid, and sealing the pump structure.

The method may further include dicing the passivation layer and the layer below the passivation layer at a position spaced apart from both ends of the gate to open the cooling space region.

The width of the inlet of the cooling space region may have a critical size for allowing epitaxial growth on the substrate.

The method may further include forming a blocking layer in the inlet of the cooling space region, the blocking layer including a material of the substrate.

DETAILED DESCRIPTION

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of description. Meanwhile, the embodiments described below are merely exemplary, and various modifications are possible from these embodiments.

Hereinafter, the term “upper portion” or “on” may also include “to be present above, below, or in the left or right on a non-contact basis” as well as “to be on the top portion, the bottom portion, or in the left or right in directly contact with”. Singular expressions include plural expressions unless they are explicitly meant differently in context. In addition, when a part “includes” a component, this means that it may include more other components, rather than excluding other components, unless otherwise stated.

The use of the term “the” and similar indicative terms may correspond to both singular and plural. If there is no explicit description or contrary description of the steps constituting the method, these steps may be carried out in an appropriate order and are not necessarily limited to the stated order.

Further, the terms “unit”, “module” or the like mean a unit that processes at least one function or operation, which may be implemented in hardware or software or implemented in a combination of hardware and software.

The connection or connection members of lines between the components shown in the drawings exemplarily represent functional connection and/or physical or circuit connections, and may be replaceable or represented as various additional functional connections, physical connections, or circuit connections in an actual apparatus.

The use of all examples or exemplary terms is simply for describing a technical idea in detail and the scope is not limited by these examples or exemplary terms unless limited by the claims.

In a power conversion system, the efficiency of a power device for switching may determine the efficiency of an entire system. In order to solve the limitation of efficiency due to a material limitation of silicon, research has been conducted to increase conversion efficiency by manufacturing a transistor using a group III-V based compound semiconductor, for example, a GaN-based semiconductor material, which is a new material. For example, in the case of a GaN power device, a cooling system application is required to prevent a decrease in efficiency due to an increase in temperature.

According to a power device and a method of manufacturing the power device according to various example embodiments described below, an empty space usable as a cooling path may be formed inside a substrate without a bonding and backside process under a lower portion of an epitaxial-grown compound semiconductor, for example, a GaN epitaxial layer or a lower thin film. The power device and the manufacturing method thereof according to an example embodiment, enable a cooling system to be constructed with only a frontside process, thereby increasing a cooling effect and reducing process costs.

FIGS.1and2are plan views schematically illustrating a power device50according to an example embodiment,FIG.3is a cross-sectional view taken along line I-I′ ofFIGS.1and2, andFIG.4is a cross-sectional view taken along line II-II′ ofFIGS.1and2.FIG.1illustrates an example in which one cooling path15is formed inside a substrate1.FIG.2illustrates an example in which a plurality of cooling paths15are formed inside a substrate1in a form repeated at predetermined intervals.

Referring toFIGS.1to4, a power device50includes a substrate1, a compound semiconductor layer20, a gate25, a source23and a drain27, a passivation layer30, and a cooling space region10provided to form a cooling path15inside the substrate1. The source23and the drain27may be provided on both sides of the gate25, respectively. The passivation layer30may be provided to on the source23, the drain27, and the gate25. According to an example embodiment, the passivation layer30may be provided directly on the source23, the drain27, and the gate25. According to an example embodiment, the passivation layer30may cover the source23, the drain27, and the gate25. According to an example embodiment, the source23, the drain27, and the gate25may be embedded in the passivation layer30. The passivation layer30and the compound semiconductor layer20may be provided to open the cooling space region10formed inside the substrate1. For example, the passivation layer30and the compound semiconductor layer20may have an opening connected to the cooling space region10formed inside the substrate1. Although a passivation layer30is not shown inFIGS.1and2, the cross-sectional view inFIGS.3and4show the passivation layer30according to an example embodiment. Moreover,FIG.4illustrates the passivation layer30and the compound semiconductor layer20having openings41and45, which are described below in detail.

The substrate1may be, for example, a substrate based on Si. For example, the substrate1may be a Si substrate or a SiC substrate. As another example, the substrate1may include sapphire or GaN. The substrate may further include various other materials.

The cooling space region10may be formed in a trench shape from the surface of the substrate1to a predetermined depth so as to form a cooling path15inside the substrate1. The trench forming the cooling space region10has an enlargement region Wc whose width increases with depth from the surface of the substrate1as shown inFIGS.5to7. For example, as shown inFIG.5, the enlargement region Wc may reach an intermediate depth from an inlet10aof the cooling space region10. In another example, the enlargement region Wc may reach the bottom depth of the trench which forms the cooling space region10from the inlet10aas shown inFIGS.6and7. That is, the entire region of the cooling space region10may be formed as an enlargement region Wc, or only a partial section may be formed as an enlargement region Wc.

FIG.5is an enlarged view of the cooling space region10ofFIG.3.FIG.5shows an example where the enlargement region Wc extends from the inlet10aof the cooling space region10to an intermediate depth, but the embodiment is not limited thereto. As such, according to another example embodiment, the enlargement region Wc may extend to from the inlet10aof the cooling space region10to a different depth. The cooling space region10has at least one enlargement region Wc within a range from the inlet10ato the bottom of the trench, and the width of the cooling space region10may be changed in various forms.

Referring toFIG.5, the inlet10ain which the cooling space region10starts may be positioned on the surface of the substrate1or adjacent to the surface of the substrate1. The cooling space region10may be formed such that the width Wa of the inlet10ais less than the maximum width Wb of the enlargement region Wc. InFIG.5, Wa denotes the width of the inlet10aof the cooling space region10, and Wb denotes the maximum width of the enlargement region Wc. The cooling space region10may be formed to satisfy a condition of Wa<Wb.

As shown inFIG.5, the cooling space region10may be formed in a shape in which an enlargement region Wc is formed to a middle depth of the cooling space region10and a width thereof is gradually decreased at a depth less than the middle depth. That is, the cooling space region10may have a maximum width Wb at an intermediate depth, and may be formed in a form in which the width decreases with the depth at a position deeper than the middle. However, the disclosure is not limited thereto, and as such, according to an example embodiment, the enlargement region Wc may be formed to a depth different that the middle depth of the cooling space region10.

According to another example embodiment, the cooling space region10may have a form in which the width increases with the depth from the surface of the substrate1to the entire depth, as shown inFIGS.6and7. In this case, the cooling space region10may correspond to the overall enlargement region Wc, and the cooling space region10may be formed in a form in which the width Wa of the inlet10ais formed in the minimum size and the maximum width Wb is formed at the bottom. As illustrated inFIG.6, the cooling space region10may be formed in a shape in which a width thereof linearly increases with a depth or as illustrated inFIG.7, the cooling space region10may be formed in a shape in which a width thereof is non-linearly increased with a depth. In addition, the cooling space region10may be formed in a flat bottom part as shown inFIG.6, or may be formed in a shape in which the bottom part is not flat as shown inFIG.7, for example, a convex shape. In addition, the cooling space region10may be formed in various forms including an enlargement region Wc in at least a partial section. The power device50ofFIG.3and the power devices of various example embodiments to be described later show an example in which the cooling space region10is in the form ofFIG.5. The cooling space region10may be formed in the form shown inFIGS.6and7, or may be formed in other various trench forms including the enlargement region Wc.

The cooling space region10may be formed, for example, by applying a deep trench process to the silicon substrate1. In this case, instead of a deep trench in the shape of a general rod, a trench in which the width of the intermediate depth or the bottom depth is larger than the width Wa of the inlet10aof the cooling space region10may be configured. For example, when the compound semiconductor layer20or the like is epitaxially grown, the inlet10aof this small width Wa may lower the risk in terms of defects, and the width of the relatively large intermediate depth or bottom depth may enlarge the size of the cooling path15.

Meanwhile, in the power device50according to an example embodiment, the width Wa of the inlet10of the cooling space region10may be formed to have a critical dimension (CD) capable of epitaxial growth of the compound material layer20or other semiconductor material layer on the substrate1. The width Wa of the inlet10aof the cooling space region10may be formed to have a critical size of, for example, about 1 μm to 5 μm or less.

The cross-sectional views of the power device50ofFIG.3and the power device of various example embodiments to be described later show the single cooling space region10inside the substrate1, which is only illustrated as an example. However, as can be inferred from the plan views ofFIGS.1and2, for one power device, a plurality of cooling space regions10may be repeatedly arranged inside the substrate at predetermined intervals.

Meanwhile, as can be seen from the plan view shown inFIG.1, in the power device50according to an example embodiment, the cooling space region10formed inside the substrate1may be provided such that a first part15aalong the length direction (y-axis) direction) of the gate25and a second part15balong the width direction (x-axis direction) of the gate25are repeated, and the first part15aand the second part15bare connected to each other to form one cooling path15.FIG.1shows an example in which the first part15ais parallel to the length direction (y-axis direction) of the gate25and the second part15bis parallel to the width direction (x-axis direction) of the gate25, but the embodiment is not limited thereto. The first part15aof the cooling path15may be formed at a predetermined angle with respect to the length direction (y-axis direction) of the gate25, and the second part15bmay be formed at a predetermined angle with the width direction (x-axis direction) of the gate25.

Referring toFIGS.1,2, and4, the power device50according to an example embodiment may include, for example, a plurality of trenches, for example, first and second trenches41and45formed over the passivation layer (30) and the compound semiconductor layer20to open the cooling space region10. As shown inFIG.1, when one cooling path15is formed inside the substrate1, the first and second trenches41and45that open the cooling space region10may be formed at one end and the last end of the cooling path15. The first and second trenches41and45may be formed to open the cooling space region10over the passivation layer30and the compound semiconductor layer20. InFIG.1, the dashed box indicates a first trench41is formed at a first end of the cooling path15and a second trench41is formed at a second end of the cooling path15. For example, the first trench41may be formed at an entrance of the cooling path15and the second trench41is formed at an exit of the cooling path15. However, the disclosure is not limited to an entrance and an exit, and the arrangement may be reversed.

As another example, as shown in the plan view illustrated inFIG.2, in the power device50according to an example embodiment, the cooling space region10formed inside the substrate1may be provided to form a plurality of cooling paths15in a form repeated at predetermined intervals.

That is, the cooling space region10formed inside the substrate1may be provided to form a plurality of cooling paths15, for example, in a manner that the first part15ainFIG.1is repeated at predetermined intervals along the length direction (y-axis direction) of the gate25. InFIG.2, an example in which the cooling path15is parallel to the length direction (y-axis direction) of the gate25is illustrated, but the disclosure is not limited thereto. As such, according to another example embodiment, the cooling path15may be formed to have a predetermined angle with the length direction (y-axis direction) of the gate25.

As shown inFIG.2, when the cooling space region10is formed to have a plurality of cooling paths15separated from each other inside the substrate1, the first and second trenches41and45that open the cooling space region10may be formed at one end and the last end of each cooling path15so as to be formed at positions spaced apart from both ends of the gate25. The first and second trenches41and45may be formed across the passivation layer30and the compound semiconductor layer20, for example, to open the cooling space region10of each cooling path15. InFIG.2, the dashed box indicates first and second trenches41and45formed at one end and the last end of the cooling path15. Each of the first and second trenches41and45may be formed over the entire plurality of cooling paths15, as illustrated inFIG.2. The power device50according to the embodiment may be provided so that the cooling space region10is connected to the outside through the first and second trenches41and45to form a cooling path. According to another example embodiment described later, when the passivation layer30and layers below the passivation layer30are diced at positions spaced apart from both ends of the gate25to open the cooling space region10of each power device50, the dashed box inFIG.2may correspond to a position where the power device50is diced for separation in units of chips. When a power device array manufactured at a wafer level is diced in units of chips, the cooling space region10of each power device50may be opened simultaneously.

Referring toFIGS.3and4, the compound semiconductor layer20may be epitaxially grown on the substrate1. The compound semiconductor layer20may include a first semiconductor material. The first semiconductor material may include a group III-V based compound semiconductor material, but is not limited thereto. The compound semiconductor layer20may be, for example, a GaN-based material layer, as a specific example, a GaN layer. The compound semiconductor layer20may form a channel. The compound semiconductor layer20may be, for example, an undoped GaN layer, and in some cases, may be a doped GaN layer doped with certain impurities. For example, the compound semiconductor layer20may be a GaN layer epitaxially grown on the substrate1, and may form a channel.

According to an example embodiment, the compound semiconductor layer20may further include a buffer layer. The buffer layer may alleviate the difference in a lattice constant and a thermal expansion coefficient between the substrate1and the compound semiconductor layer20forming a channel. The buffer layer may include a nitride including at least one of Al, Ga, In, and B, and may have a single-layer or multi-layer structure. For example, the buffer layer may include at least one of materials made of AlN, GaN, AlGaN, InGaN, AlInN, or AlGaInN. According to an example embodiment, a seed layer for growing the buffer layer may be further provided between the substrate1and the buffer layer.

Meanwhile, referring toFIGS.30and31, a barrier layer21may be provided on a channel of the compound semiconductor layer20. A depletion forming layer24may be further provided on the barrier layer21.FIGS.30and31show examples in which the power device50according to the embodiments further includes a barrier layer21and a depletion forming layer24, in correspondence toFIGS.3and4, respectively.

In addition to the power device50of this embodiment, the power device of various example embodiments to be described later may further include a barrier layer21and/or a depletion forming layer24. Since an example in which the power device of various example embodiments to be described later further includes a barrier layer21and/or a depletion forming layer24may be sufficiently inferred from the examples ofFIGS.30and31, repeated illustrations and descriptions of an example further including the barrier layer21and/or the depletion forming layer24will be omitted.

The barrier layer21may generate a two-dimensional electron gas (2DEG) in the channel. Here, the two-dimensional electron gas (2DEG) may be formed in the compound semiconductor layer20below an interface of the compound semiconductor layer20forming the channel and the barrier layer21. The barrier layer21may include a second semiconductor material different from the first semiconductor material forming the compound semiconductor layer20. The second semiconductor material may differ from the first semiconductor material in at least one of polarization characteristics, an energy bandgap, and a lattice constant.

At least one of a polarization rate and an energy band gap of the second semiconductor material may be greater than that of the first semiconductor material. The barrier layer21may contain, for example, a nitride including at least one of Al, Ga, In, and B, and may have a single-layer or multi-layer structure. As a specific example, the barrier layer21may include at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. However, embodiments are not limited thereto. The barrier layer21may be an undoped layer, but may be a layer doped with predetermined impurities.

The depletion forming layer24may include, for example, a p-type semiconductor material. That is, the depletion forming layer24may be a semiconductor layer doped with p-type impurities. The depletion forming layer24may include a group III-V based nitride semiconductor. For example, the depletion forming layer24may include a material in which p-type impurity is doped into at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN. As a specific example, the depletion forming layer24may be a p-GaN layer.

Since the depletion forming layer24may increase the energy bandgap of the barrier layer21therebelow, a depletion region of two-dimensional electron gas (2DEG) may be formed in the compound semiconductor layer20corresponding to the depletion forming layer24. Accordingly, a portion of the two-dimensional electron gas (2DEG) corresponding to the depletion forming layer24may be disconnected or may have different characteristics (e.g., electron concentration, etc.). The region where the two-dimensional electronic gas (2DEG) is disconnected may be referred to as a “disconnection region”, and the power device50may have a normally-off characteristic by the disconnection region in which the current between the drain27and the source23is turned off when the gate voltage is 0 V.

Meanwhile, a gate25may be formed on the compound semiconductor layer20, and a source23and a drain27may be formed on both sides of the gate25. When the barrier layer21is provided on the channel of the compound semiconductor layer20, the source23and the drain27may be formed on the channels of both sides of the barrier layer21, for example. The source23and the drain27may be provided to extend parallel to each other in the y-axis direction. The source23and the drain27may include, for example, a conductive material such as Ti, Al, or the like. The source23and the drain27may be electrically connected to the 2D electronic gas (2DEG). Meanwhile, the source23and the drain27may be provided in the barrier layer21.

The gate25may be provided to extend in the y-axis direction parallel to the source23and the drain27. The gate25may include a conductive material such as a metal material or a metal compound. For example, the gate25may include Ti, Al, TiN, TiAl, or W, but is not limited thereto. When the barrier layer21is provided on the channel of the compound semiconductor layer20, and the depletion forming layer24is further provided on the barrier layer21, the gate25may be provided on the depletion forming layer24to extend along the y-axis direction in parallel with the source23and drain27.

The passivation layer30may be formed on the compound semiconductor layer20to cover the source23, the drain27, and the gate25. Here, the passivation layer30may be one dielectric layer integrally formed. The passivation layer30may include, for example, silicon oxide, silicon nitride, organic polymer, or the like, but is not limited thereto.

According to the power device50according to an example embodiment, the cooling space region10having the enlargement region We whose width increases with depth from the surface of the substrate1is formed to form have cooling path15inside the substrate1, and thus it is possible to implement a cooling system integrated power device with high chip integration and increased cooling effect. According to the power device50according to an example embodiment, a cooling path may be formed only by a frontside process without a bonding or backside process requiring high process difficulty and high process unit cost, thereby having an advantage in terms of the process unit cost. Here, the bonding or backside process may be performed, for example, by removing silicon from the backside of the wafer or applying a material having a heat dissipation effect to the surface.

Meanwhile, in the power device50according to an example embodiment, the cooling space region10may be maintained in an empty state or may be filled with a material having good thermal conductivity.

FIGS.8to12are diagrams for describing a method of manufacturing a power device50according to an example embodiment.

Referring toFIG.8, a substrate1is prepared. The substrate1may be, for example, a substrate based on Si. For example, the substrate1may be a Si substrate or a SiC substrate. As another example, the substrate1may include sapphire, GaN, or the like. In addition, the substrate1may include various other materials.

Referring toFIG.9, a mask pattern5having an opening5aat a position corresponding to the inlet10aof the cooling space region10to be formed is formed on the substrate1, and the cooling space region10is formed from the surface of the substrate1to a certain depth. The mask pattern5may be a hard mask pattern. The cooling space region10may include an enlargement region Wc whose width increases with depth from the surface of the substrate1, and as described with reference toFIGS.5to7, the width Wa of the inlet10amay be less than the maximum width Wb of the enlargement region Wc.

The cooling space region10may be formed by applying a deep trench process to the substrate1. For example, the substrate1may be a silicon substrate. The cooling space region10may be configured as a trench having a larger width of an intermediate depth or a bottom depth compared to the width of the inlet10a. For example, when the compound semiconductor layer20or the like is epitaxially grown, the inlet10aof this small width Wa may lower the risk in terms of defects, and the width of the relatively large intermediate depth or bottom depth may enlarge the size of the cooling path15.

As described above with reference toFIG.5, the cooling space region10may have a shape in which an enlargement region Wc is formed to a middle depth of the cooling space region10and a width thereof is gradually decreased at a depth therebelow. As another example, as described with reference toFIGS.6and7, the cooling space region10may be formed in a form in which a width thereof linearly or nonlinearly increases according to a depth from the surface of the substrate1to the entire depth. In addition, as described with reference toFIGS.6and7, the cooling space region10may have a flat bottom portion, or may be formed in a non-flat shape, for example, in a convex shape. In addition, the cooling space region10may be formed in various forms including an enlargement region We in at least a partial section.

The cooling space region10may be formed, for example, through the manufacturing process ofFIGS.29A to29C.

FIGS.29A to29Cillustrate a method of forming a cooling space region10forming a cooling path15inside a substrate1through a deep trench process.

Referring toFIG.29A, a mask pattern5having an opening5aat a position corresponding to the inlet10aof the cooling space region10is formed on the substrate1and then a first etching process is performed on the substrate1to form a trench. The mask pattern5may be patterned to form, for example, the cooling path15ofFIG.1or2. The first etching process may apply, for example, a high bias voltage and, for example, use an etching gas based on SF6. When a high bias voltage is applied during etching by applying an etching gas based on SF6, a reverse taper profile may be formed by ion bombardment. Accordingly, an inlet10aof the cooling space region10having a small width may be formed.

Next, as shown inFIG.29B, a passivation layer6may be formed in a region including an opening5aof the mask pattern5and an inlet10aof the cooling space region10, and a second etching process may be performed on the substrate1to increase the depth and width of the trench. According to an example embodiment, the passivation layer6may be formed on the sides of the mask pattern5at the opening5A. Moreover, the passivation layer6may be formed on a portions of the surface of the substrate1. For the formation of the passivation layer6, for example, a gas based on C4F8may be used. The etched inlet10aof the cooling space region10may be prevented from being widened by the passivation layer6. In addition, when the second etching process is performed with SF6-based etching gas, an isotropic etching by ions may be strengthened rather than vertical etching in the case that the SF6 flow rate is increased under low bias voltage condition. The etching profile shape formed by this process may have a jar structure in which the inlet10ais narrow and the inside is wide.

When the process of forming the passivation layer6and the process of performing the second etching process are repeated once or multiple times, as shown inFIG.29C, a cooling space region10having a small inlet10aand an enlargement region We whose width increases with depth from the surface of the substrate1may be formed.

Meanwhile, the width Wa of the inlet10aof the cooling space region10may be formed to have a critical dimension (CD) capable of epitaxial growth of the compound semiconductor layer20or other semiconductor material layer on the substrate1. The width Wa of the inlet10aof the cooling space region10may be formed to have a critical size of, for example, about 1 μm to 5 μm or less. In this case, the inlet10aof the cooling space region10may be blocked during epitaxial growth of the compound semiconductor layer20or another semiconductor material layer on the substrate1. Here, the other semiconductor material layer may be, for example, a material based on the material of the substrate1.

Here, like the power device120according to other embodiments ofFIGS.21and22to be described later, when a material region17blocking the inlet10aof the cooling space region10is separately formed, the inlet10aof the space region10may have a critical size capable of epitaxial growth or may be larger than the critical size.

Meanwhile, as described above, for example, with reference toFIG.1, the cooling space region10formed inside the substrate1through the processes ofFIGS.29A to29Cmay form one cooling path15inside the substrate1in which the first part15ain the length direction (y-axis direction) of the gate25and the second part15bin the width direction (x-axis direction) of the gate25are repeated, and the first part15aand the second part15bmay be connected to each other.

As another example, the cooling space region10formed inside the substrate1through the processes ofFIGS.29A to29Cmay form a plurality of cooling paths15inside the substrate1in a form repeated at predetermined intervals, as described with reference toFIG.2.

After forming the cooling space region10from the surface of the substrate1to a certain depth, removing the mask pattern5as shown inFIG.10provides a structure of having a narrow inlet10aon the surface of the substrate1and forming a void-shaped cooling space region10to form a desired arrangement of the cooling path15inside the substrate1.

Next, referring toFIGS.11A and11B, a compound semiconductor layer20may be epitaxially grown on a substrate1with a cooling space region10formed therein, a gate25and a source23and a drain27provided on both sides of the gate25may be formed on the compound semiconductor layer20, and then a passivation layer30may be formed to cover the source23, the drain27, and the gate25. The passivation layer30may be provided to open the cooling space region10formed inside the substrate1.FIG.11Acorresponds to a cross-sectional view taken along line I-I′ ofFIGS.1and2, andFIG.11Bcorresponds to a cross-sectional view taken along line II-II′ ofFIGS.1and2.

The compound semiconductor layer20may be epitaxially grown on the substrate1. The compound semiconductor layer20may include a first semiconductor material. The first semiconductor material may include a group III-V based compound semiconductor material, but is not limited thereto. The compound semiconductor layer20may be, for example, a GaN-based material layer, as a specific example, a GaN layer. The compound semiconductor layer20may form a channel. The compound semiconductor layer20may be, for example, an undoped GaN layer, and in some cases, may be a doped GaN layer doped with certain impurities. For example, the compound semiconductor layer20may be a GaN layer epitaxially grown on the substrate1, and may form a channel.

According to an example embodiment, the compound semiconductor layer20may further include a buffer layer. The buffer layer may alleviate the difference in a lattice constant and a thermal expansion coefficient between the substrate1and the compound semiconductor layer20forming a channel. The buffer layer may include a nitride including at least one of Al, Ga, In, and B, and may have a single-layer or multi-layer structure. For example, the buffer layer may include at least one of materials made of AlN, GaN, AlGaN, InGaN, AlInN, or AlGaInN. According to an example embodiment, a seed layer for growing the buffer layer may be further provided between the substrate1and the buffer layer.

As described with reference toFIGS.30and31, a barrier layer21may be further provided on the channel of the compound semiconductor layer20, and a depletion forming layer24may be further provided on the barrier layer21.

The barrier layer21may generate a two-dimensional electron gas (2DEG) in the channel. Here, the 2DEG may be formed in the compound semiconductor layer20below the interface of the channel and the barrier layer21. The barrier layer21may include a second semiconductor material different from the first semiconductor material forming the compound semiconductor layer20. The second semiconductor material may differ from the first semiconductor material in at least one of polarization characteristics, an energy bandgap, and a lattice constant.

At least one of a polarization rate and an energy band gap of second semiconductor material may be greater than that of the first semiconductor material. The barrier layer21may contain, for example, a nitride including at least one of Al, Ga, In, and B, and may have a single-layer or multi-layer structure. As a specific example, the barrier layer21may include at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. However, embodiments are not limited thereto. The barrier layer21may be an undoped layer, but may be a layer doped with predetermined impurities.

The depletion forming layer24may include, for example, a p-type semiconductor material. That is, the depletion forming layer24may be a semiconductor layer doped with p-type impurities. The depletion forming layer24may include a group III-V based nitride semiconductor. For example, the depletion forming layer24may include a material in which p-type impurity is doped into at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN. As a specific example, the depletion forming layer24may be a p-GaN layer.

Since the depletion forming layer24may increase the energy bandgap of the barrier layer21therebelow, a depletion region of two-dimensional electron gas (2DEG) may be formed in the compound semiconductor layer20corresponding to the depletion forming layer24. Accordingly, a portion of the two-dimensional electron gas (2DEG) corresponding to the depletion forming layer24may be disconnected or may have different characteristics (e.g., electron concentration, etc.). The region where the two-dimensional electronic gas (2DEG) is disconnected may be referred to as a “disconnection region”, and the power device50may have a normally-off characteristic by the disconnection region in which the current between the drain27and the source23is turned off when the voltage of the gate25is 0 V.

Meanwhile, a gate25may be formed on the compound semiconductor layer20, and a source23and a drain27may be formed on both sides of the gate25. When the barrier layer21is provided on the channel of the compound semiconductor layer20, the source23and the drain27may be formed on the channel of both sides of the barrier layer21, for example. The source23and the drain27may be provided to extend parallel to each other in the y-axis direction. The source23and the drain27may include, for example, a conductive material such as Ti, Al, or the like. The source23and the drain27may be electrically connected to the 2DEG. Meanwhile, the source23and the drain27may be provided in the barrier layer21.

The gate25may be provided to extend in the y-axis direction parallel to the source23and the drain27. The gate25may include a conductive material such as a metal material or a metal compound. For example, the gate25may include Ti, Al, TiN, TiAl, or W, but is not limited thereto. When the barrier layer21is provided on the channel of the compound semiconductor layer20, and the depletion forming layer24is further provided on the barrier layer21, the gate25may be provided on the depletion forming layer24to extend along the y-axis direction in parallel with the source23and drain27.

The passivation layer30may be formed on the compound semiconductor layer20to cover the source23, the drain27, and the gate25. Here, the passivation layer30may be one dielectric layer integrally formed. The passivation layer30may include, for example, silicon oxide, silicon nitride, organic polymer, or the like, but is not limited thereto.

Next, referring toFIG.12, a plurality of trenches, for example, first and second trenches41and45formed over the passivation layer30and the compound semiconductor layer20may be formed to open the cooling space region10. In this case, as shown inFIG.1, when one cooling path15is formed inside the substrate1, the first and second trenches41and45that open the cooling space region10may be formed at a first end and a second end of the cooling path15. In addition, as shown inFIG.2, when the cooling space region10is formed to have a plurality of cooling paths15separated from each other inside the substrate1, the first and second trenches41and45that open the cooling space region10may be formed at one end and the last end of each cooling path15so as to be formed at positions spaced apart from both ends of the gate25. The first and second trenches41and45may be formed across the passivation layer30and the compound semiconductor layer20, for example, to open the cooling space region10of each cooling path15. Accordingly, the power device50according to the embodiment may be obtained.

FIG.13is a diagram for describing a method of manufacturing a power device50′ according to another example embodiment. In order to manufacture the power device50′ according to another example embodiment, a process of manufacturing the power device50according to the embodiment described with reference toFIGS.8to11Bmay be applied, except that the passivation layer30and the layers below the passivation layer30are diced at positions spaced apart from both ends of the gate25, to open the cooling space region10.

InFIG.13, the left-hand view corresponds toFIG.11Band shows the state before the cooling space region10is opened. InFIG.13, the right-hand view shows a state after the cooling space region10is opened by dicing, and a cooling path15may be formed inside the substrate1by the opened cooling space region10.

In the power device50′ according to another example embodiment, a portion in which dicing is performed may correspond to, for example, a dashed box position inFIG.2. As illustrated inFIG.13, when the cooling space region10is opened by dicing, the cooling space region10may be formed to have a plurality of cooling paths15separated from each other inside the substrate1as illustrated inFIG.2.

As another example, even when the cooling space region10is formed to have the one cooling path15inside the substrate1, as illustrated inFIG.1, the passivation layer30and layers below the passivation layer30may be diced at positions separated from both ends of the gate25to open the cooling space region10. In this case, only the first end and the second end of the cooling path15may be diced to be opened, and the first end and the second end of the cooling path15may be formed to protrude from the second part15bto enable such an open structure. According to another example embodiment, the passivation layer30and the layers below the passivation layer30may be diced to remove the second part15bof the cooling path15inFIG.1. In this case, a plurality of cooling paths15separated from each other may be formed inside the substrate1.

FIGS.14to18are diagrams for describing a method of manufacturing a power device100according to another example embodiment. The power device100according to another example embodiment is the same as or similar to the structure and manufacturing process of the power device50according to the embodiments described with reference toFIGS.8to13, except that the material layer11, for example, an Si epitaxial layer is further included on the substrate1, and thus redundant description thereof will be omitted. The substrate1in which the cooling space region10is formed to a predetermined depth shown inFIG.14may be formed by applying the above-described manufacturing processes with reference toFIGS.8to10and29A to29C. In this case, the cooling path15as described with reference toFIGS.1and2may be formed inside the substrate1.

Referring toFIG.14, a material layer11based on the material of the substrate1may be epitaxially grown on the substrate1in which the cooling space region10is formed to a predetermined depth. For example, when the substrate1is a Si substrate, the material layer11may be a Si epitaxial layer. The material layer11may be epitaxially grown on the substrate1to block the inlet10aof the cooling space region10. As another example, the inlet10aof the cooling space region10may be blocked with a material such as Si, SiN, SiO, etc., and then the material layer11may be epitaxially grown on the substrate1.FIGS.14to18show example cases where the material layer11is epitaxially grown on the substrate1to block the inlet10aof the cooling space region10.

Next, as shown inFIGS.15A and15B, the compound semiconductor layer20may be epitaxially grown on the material layer11, a gate25, a source23, and a drain27may be formed on the compound semiconductor layer20, and a passivation layer30may be formed to cover the gate25, the source23, and the drain27.

Then, a plurality of trenches, e.g., first and second trenches41and45may be formed across the passivation layer30, the compound semiconductor layer20, and the material layer11, as shown inFIGS.16and17, whereby the cooling space region10may be opened. Alternatively, the passivation layer30and lower layers thereof may be diced at positions spaced apart from both ends of the gate25as shown inFIG.18, whereby the cooling space region10may be opened.

FIGS.16and17are cross-sectional views schematically illustrating a power device100according to an example embodiment. An example of forming a plurality of trenches, for example, first and second trenches41and45across the passivation layer30, the compound semiconductor layer20, and the material layer11is shown. The power device100ofFIGS.16and17is the same as the configuration of the power device50according to the embodiments described with reference toFIGS.3and4, except that the material layer11, for example, a Si epitaxial layer is further included.FIG.16corresponds to a cross-sectional view taken along line I-I′ ofFIGS.1and2, andFIG.17corresponds to a cross-sectional view taken along line II-II′ ofFIGS.1and2.

FIG.18is a view showing an example in which the power device100according to another example embodiment is formed to open the cooling space region10by dicing, and as inFIG.13, the left-hand view shows the state before opening the cooling space region10by dicing, and the right-hand view shows the state after opening the cooling space region10by dicing.

Referring toFIG.18, in order to manufacture the power device100according to another example embodiment, the cooling space region10may be opened by dicing the passivation layer30and the lower layers thereof at positions spaced apart from both ends of the gate25.

In this case, in the power device100according to another example embodiment, the cooling space region10may be formed to have multiple cooling paths15separated from each other inside the substrate1, and a part in which the dicing is performed may correspond to a dashed box position inFIG.2, for example. As another example, even when the cooling space region10is formed to have one cooling path15inside the substrate1, as illustrated inFIG.1, the passivation layer30and lower layers thereof may be diced at positions separated from both ends of the gate25to open the cooling space region10. In this case, only one end and the last end of the cooling path15may be diced to be opened, and the one end and the last end of the cooling path15may be formed to protrude from the second part15bto enable such an open structure. In addition, the passivation layer30and lower layers thereof may be diced to remove the second part15bof the cooling path15inFIG.1. In this case, the power device100may have a plurality of cooling paths15separated from each other inside the substrate1.

FIGS.19to23are diagrams for describing a method of manufacturing a power device120according to another example embodiment. The structure and manufacturing process of the power device120according to another example embodiment are the same as or similar to the structure and manufacturing process of the power device50according to the embodiments described with reference toFIGS.8to13, except that the material region17blocking the inlet10aof the cooling space region10is provided, and thus redundant description thereof will be omitted. The substrate1in which the cooling space region10is formed to a predetermined depth shown inFIG.19may be formed by applying the above-described manufacturing processes with reference toFIGS.8to10and29A to29C. In this case, the cooling path15as described with reference toFIGS.1and2may be formed inside the substrate1.

Referring toFIG.19, for the substrate1where the cooling space region10is formed to a certain depth, a material region17may be formed to block the inlet10aof the cooling space region10. The material region17may be formed to block the inlet10aof the cooling space region10with any one of Si, SiN, and SiO, for example. When the material region17blocking the inlet10aof the cooling space region10is separately formed, the inlet10aof the space region10may have a critical size capable of epitaxial growth or may be larger than the critical size.

Next, as shown inFIGS.20A and20B, the compound semiconductor layer20may be epitaxially grown on the substrate1, a gate25, a source23, and a drain27may be formed on the compound semiconductor layer20, and a passivation layer30may be formed to cover the gate25, the source23, and the drain27.

Then, a plurality of trenches, e.g., first and second trenches41and45may be formed across the passivation layer30and the compound semiconductor layer20as shown inFIGS.21and22, whereby the cooling space region may be opened. Alternatively, the passivation layer30and lower layers thereof may be diced at positions spaced apart from both ends of the gate25as shown inFIG.23, whereby the cooling space region10may be opened.

FIGS.21and22are cross-sectional views schematically illustrating a power device120according to an example embodiment. An example of forming a plurality of trenches, for example, first and second trenches41and45across the passivation layer30and the compound semiconductor layer20is shown. Except that the power device120according to the embodiments ofFIGS.21and22further includes a material region17to block the inlet10aof the cooling space region10, the remaining configuration of the power device120according to the embodiments may be the same as that of the power device50according to the embodiments described with reference toFIGS.3and4.FIG.21corresponds to a cross-sectional view taken along line I-I′ ofFIGS.1and2, andFIG.22corresponds to a cross-sectional view taken along line II-II′ ofFIGS.1and2.

FIG.23is a view showing an example in which the power device120according to another example embodiment is formed to open the cooling space region10by dicing, and as inFIG.13, the left-hand view shows the state before opening the cooling space region10by dicing, and the right-hand view shows the state after opening the cooling space region10by dicing.

Referring toFIG.23, in order to manufacture the power device120according to another example embodiment, the cooling space region10may be opened by dicing the passivation layer30and the lower layers thereof at positions spaced apart from both ends of the gate25.

In this case, in the power device120according to another example embodiment, the cooling space region10may be formed to have multiple cooling paths15separated from each other inside the substrate1, and a part in which the dicing is performed may correspond to a dashed box position inFIG.2, for example. As another example, even when the cooling space region10is formed to have one cooling path15inside the substrate1, as illustrated inFIG.1, the passivation layer30and lower layers thereof may be diced at positions spaced apart from both ends of the gate25to open the cooling space region10. In this case, only one end and the last end of the cooling path15may be diced to be opened, and the one end and the last end of the cooling path15may be formed to protrude from the second part15bto enable such an open structure. In addition, the passivation layer30and lower layers thereof may be diced to remove the second part15bof the cooling path15inFIG.1. In this case, the power device120may have a plurality of cooling paths15separated from each other inside the substrate1.

FIGS.24to27are diagrams for describing a method of manufacturing a power device130according to another example embodiment. The power device130according to another example embodiment is the same as or similar to the power device50′ according to the embodiment described with reference toFIGS.8to11B and13, except that, in a state in which the cooling space region10formed inside the substrate1is filled with a filling material13, epitaxial growth and subsequent processes of the compound semiconductor layer20are performed, and the cooling space region10is opened by a dicing process, and thus redundant descriptions will be omitted herein. The substrate1in which the cooling space region10is formed to a predetermined depth shown inFIG.24may be formed by applying the above-described manufacturing processes with reference toFIGS.8to10and29A to29C. In this case, the cooling path15as described with reference toFIGS.1and2may be formed inside the substrate1.

Referring toFIG.24, for the substrate1where the cooling space region10is formed to a certain depth, the empty space inside the substrate1, that is, the cooling space region10may be filled with the filling material13. The filling material13may be, for example, a material capable of wet etching. The filling material13may include, for example, at least one of SiO2and SiN.

Next, as shown inFIGS.25A and25B, the compound semiconductor layer20may be epitaxially grown on the substrate1, a gate25, a source23, and a drain27may be formed on the compound semiconductor layer20, and a passivation layer30may be formed to cover the gate25, the source23, and the drain27. FIG.25A corresponds to a cross-sectional view taken along line I-I′ ofFIGS.1and2, andFIG.25Bcorresponds to a cross-sectional view taken along line II-II′ ofFIGS.1and2.

Then, as shown inFIG.26, the cooling space region10may be opened by dicing the passivation layer30and the lower layers thereof at positions spaced apart from both ends of the gate25. Then, when the filling material13filling the cooling space region10opened is removed by a wet etching process, the cooling space region10is opened as shown inFIG.27to obtain the power device130with the cooling path15formed therein.FIG.27shows a power device130in which a cooling path15is formed by an opened cooling space region inside the substrate1by opening the cooling space region10by dicing and removing the filling material13by a wet etching process.

In this case, in the power device130, the cooling space region10may form multiple cooling paths15separated from each other inside the substrate1, and a part in which the dicing is performed may correspond to a dashed box position inFIG.2, for example. As another example, even when the cooling space region10is formed to have one cooling path15inside the substrate1, as illustrated inFIG.1, the passivation layer30and lower layers thereof may be diced to remove the second part15bof the cooling path15at positions spaced apart from both ends of the gate25to open the cooling space region10. Even in this case, the power device130may have a plurality of cooling paths15separated from each other inside the substrate1.

In the power devices50,50′,100,120, and130according to various example embodiments described above, the cooling space region10may be maintained in an empty state or may be filled with a material having good thermal conductivity.

FIG.28is a cross-sectional view schematically illustrating a power device200according to another example embodiment. Compared to the power devices50,50′,100,120, and130of the above various example embodiments, the power device200according to another example embodiment further includes a pump structure150having an inner space160openly connected to a cooling space region10through a trench on the passivation layer30.FIG.28shows an example where the power device200according to another example embodiment further includes the pump structure150in the structure ofFIG.22, but the embodiment is not limited thereto. The power device200may have a structure in which the pump structure150is further provided in any of the structures of the power devices50,50′,100,120, and130of the various example embodiments described above.

Referring toFIG.28, in the power device200according to another example embodiment, the pump structure150may be formed on the passivation layer30and may include a first plate151, a second plate153spaced apart from the first plate151, and a sidewall155connecting the first plate151and the second plate153to form the inner space160connected to the cooling space region10to be opened. A plurality of openings may be formed in the first plate151to correspond to a plurality of trenches so as to be openly connected to the cooling space region10. For example, first and second openings151aand151bmay be formed on the first plate151to correspond to the first and second trenches41and45. A piezoelectric member157may be further provided on the second plate153. The power device200may further include a cooling fluid170filling the cooling space region10and the inner space160of the pump structure150. The cooling fluid170may include a liquid or a refrigerant having good thermal conductivity.

As shown inFIG.28, when the power device200further includes the pump structure150, a cooling fluid170may flow according to the driving of the pump structure150to form a cooling path in the cooling space region10and the inner space160of the pump structure150.

In order to manufacture the power device200according to another example embodiment, a plurality of trenches, for example, first and second trenches41and45may be formed to open the cooling space region10over the passivation layer30and the compound semiconductor layer20, and a pump structure150may be formed on the passivation layer30to form an internal space160openly connected to the cooling space region10through the first and second trenches41and45. Then, the cooling space region10and the inner space160of the pump structure150may be filled with the cooling fluid170, and the pump structure150may be sealed. A sealed region159may be sealed. As another example, the sealed region159may be provided to be opened and closed so that the cooling fluid170may be replaced or replenished as necessary.

In this way, when the pump structure150having the piezoelectric member157, that is, the piezoelectric pump structure is integrally configured and embedded in the power device200, a power device enabling a small and a more smooth control of the cooling effect may be implemented.

Meanwhile, according to the power devices50,50′,100,120,130, and200according to various example embodiments, when the cooling space region10is opened by forming trenches41and45, the cooling path15may be opened to the front of the chip without being opened at the side of the chip. In this case, the cooling path15may be secured at the wafer level even before reaching the package level. In addition, an additional process using the cooling path15is possible. As another example, when the cooling space region10is opened by dicing, the cooling path15may be formed in units of chips.

In the power device and the manufacturing method thereof according to the embodiments, the cooling space region having the enlargement region whose width increases with depth from the surface of the substrate is formed to have the cooling path inside the substrate, and thus it is possible to implement a cooling system integrated power device with high chip integration and increased cooling effect.

According to the power device and the manufacturing method thereof according to the embodiments, the cooling path may be formed only by a frontside process, which is benefits in terms of process unit cost.