Semiconductor device

A semiconductor device includes a semiconductor chip having a front electrode and a rear electrode; a conductive plate having a main surface connected to the rear electrode of the semiconductor chip; an insulating plate fixed to a surface of the conductive plate opposite to the main surface; and a ceramic case having first and second terminals buried therein, a cavity accommodating the semiconductor chip, the conductive plate, and the insulating plate, and an electrode surface opposite to an opening portion of the cavity. The first terminal has one end connected to the front electrode of the semiconductor chip, and another end exposed from the electrode surface. The second terminal has one end connected to the main surface of the conductive plate, and another end exposed from the electrode surface. The ceramic case and the insulating plate form a housing.

TECHNICAL FIELD

The present invention relates to a semiconductor device.

BACKGROUND ART

FIG. 19is a cross-sectional view illustrating a main portion of a power semiconductor device. Here, a power semiconductor device1000is given as an example of a power semiconductor device including a plurality of semiconductor chips (for example, 20 chips). However, inFIG. 19, only one semiconductor chip is illustrated as a representative.

The power semiconductor device1000includes an insulating substrate64, a semiconductor chip66, a base plate70, and a case68.

The insulating substrate64is formed by laminating an insulating plate61, a circuit plate62, and a metal plate63. The semiconductor chip66is fixed to the circuit plate62through a bonding material65such as solder. In addition, the semiconductor chip66is a power semiconductor chip such as an insulated gate bipolar transistor (IGBT) chip or a diode chip.

An external terminal69of the case68is connected to the semiconductor chip66by a bonding wire67. The rear surface of the insulating substrate64is fixed to the base plate70by a bonding material65. The case68is filled with a sealing resin71, such as gel, and an opening portion of the case68is covered with an upper cover72.

In recent years, a technique has been developed in which an integrated circuit (IC) chip is accommodated in a ceramic case having a cavity to reduce the size of an integrated circuit device. The integrated circuit device includes a ceramic case which has a terminal provided therein and a cavity and an IC chip which is accommodated in the cavity, and is called a cavity package. Since a small amount of current flows to the IC chip, the thickness of the terminal buried in the cavity package is generally in the range of about 10 μm to 20 μm.

Patent Document 1 discloses a structure in which a power semiconductor chip is provided in a step portion of an uneven circuit board and a circuit element is provided on a surface opposite to the step portion.

CITATION LIST

Patent Document

DISCLOSURE OF THE INVENTION

Problem to be Solved by the Invention

The power semiconductor device1000has the following problems.

(1) It is difficult to arrange the external terminal69above the semiconductor chip66, so the external terminal69is arranged in an outer circumferential portion of the case68. As a result, it is difficult to reduce the size of the housing.

(2) Since the sealing resin71is generally a gel, it is necessary to separately provide the case68or the upper cover72in order to maintain the outer shape.

(3) When about 20 semiconductor chips66are mounted, about 10 bonding wires67are connected to each semiconductor chip66. Therefore, a considerable number of bonding wires67is required, resulting in considerable amount of time consumption for a wiring process.

An example in which not the IC chip but the power semiconductor chip is accommodated in the cavity package has not been found. It is suggested that this is because the terminal needs to have a thickness of 100 μm or more in terms of current capacity in the power semiconductor chip and it is difficult to manufacture the cavity package having the thick terminal buried therein.

Patent Document 1 does not disclose a structure in which the housing of the power semiconductor device is formed only by the circuit board. In addition, Patent Document 1 does not disclose a structure in which the terminal corresponding to the rear electrode of the power semiconductor chip leads to the upper surface of the housing.

The invention has been made in order to solve the above-mentioned problems and an object of the invention is to provide a semiconductor device that is assembled by a small number of processes and has a low manufacturing cost, high reliability, and a small size.

Means for Solving Problem

According to an aspect of the invention, there is provided a semiconductor device including: a semiconductor chip that includes a front electrode and a rear electrode; a conductive plate that has a main surface connected to the rear electrode of the semiconductor chip; an insulating plate that is fixed to a surface of the conductive plate which is opposite to the main surface; and a ceramic case. The ceramic case includes a first terminal and a second terminal which are buried therein; a cavity accommodating the semiconductor chip, the conductive plate, and the insulating plate; and an electrode surface which is opposite to an opening portion of the cavity. The first terminal has one end which is connected to the front electrode of the semiconductor chip and the other end which is exposed from the electrode surface. The second terminal has one end which is connected to the main surface of the conductive plate and the other end which is exposed from the electrode surface. The ceramic case and the insulating plate form a housing.

According to another aspect of the invention, there is provided a semiconductor device including: a semiconductor chip that includes a front electrode and a rear electrode; a wiring substrate that includes a conductive wiring plate which is buried therein, an exposure surface of the wiring plate being connected to the rear electrode of the semiconductor chip; and a ceramic case that includes a first terminal and a second terminal which are buried therein, a cavity in which the semiconductor chip is accommodated, and an electrode surface which is opposite to an opening portion of the cavity. The first terminal has one end which is connected to the front electrode of the semiconductor chip and the other end which is exposed from the electrode surface. The second terminal has one end which is connected to the exposure surface of the wiring plate and the other end which is exposed from the electrode surface. The ceramic case and the wiring substrate form a housing.

According to still another aspect of the invention, there is provided a semiconductor device including: a semiconductor chip that includes a front electrode and a rear electrode; a wiring substrate that includes a conductive wiring plate which is buried therein, an exposure surface of the wiring plate being connected to the rear electrode of the semiconductor chip; and a ceramic case that includes a first terminal and a second terminal which are buried therein, a cavity in which the semiconductor chip is accommodated, and an electrode surface which is opposite to an opening portion of the cavity. The first terminal has one end which is connected to the front electrode of the semiconductor chip and the other end which is exposed from the electrode surface. The second terminal has one end which is connected to the exposure surface of the wiring plate and the other end which protrudes from a surface perpendicular to the electrode surface. The ceramic case and the wiring substrate form a housing.

Effect of the Invention

The invention provides a semiconductor device that is assembled by a small number of processes and has a low manufacturing cost, high reliability, and a small size.

These and other objects, features, and advantages of the invention will be apparent from the following description taken in conjunction with the accompanying drawings illustrating the preferred embodiments of the invention.

MODE(S) FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments will be described according to the drawings.

The term “electrically and mechanically connected” used in the following description is not limited to a case in which objects are connected to each other by direct bonding and includes a case in which objects are connected to each other through a conductive bonding material such as solder or a sintered metal material.

First Embodiment

FIGS. 1(a), 1(b)are diagrams illustrating the structure of a power semiconductor device according to a first embodiment.FIG. 1(a)is a plan view andFIG. 1(b)is a cross-sectional view taken along the line1(b)-1(b) ofFIG. 1(a). In addition,FIG. 1(a)is a perspective plan view as viewed from the direction of an arrow A inFIG. 1(b).

A power semiconductor device100includes a semiconductor chip2, a conductive plate1, an insulating plate4, and a ceramic case11. The ceramic case11and the insulating plate4form a housing. In addition, the power semiconductor device100includes a sealing material15.

The semiconductor chip2is a vertical switching element, such as an IGBT or a power metal-oxide-semiconductor field effect transistor (MOSFET), and includes a front electrode2aand a rear electrode2b. The rear electrode2bof the semiconductor chip2is electrically and mechanically connected to a main surface1aof the conductive plate1by a conductive bonding material3such as solder. The insulating plate4is fixed to a surface1bof the conductive plate1opposite to the main surface1a.

The ceramic case11includes a ceramic20. A second terminal6and first terminals7and8are buried in the ceramic case11. In addition, the ceramic case11includes a first cavity9and a second cavity10which have a concave shape. An opening portion10aof the second cavity10is smaller than an opening portion9aof the first cavity9. The ceramic case11has an electrode surface11awhich is opposite to the opening portions9aand10aof the first and second cavities9and10.

The conductive plate1and the insulating plate4are accommodated in the first cavity9and the semiconductor chip2is accommodated in the second cavity10. The sealing material15is provided in a gap14between the cavities.

The gap14has a sufficient width to accurately position the target to be accommodated and to accommodate the sealing material15. When the width of the gap14is less than 50 μm, it is difficult for the sealing material15to be infiltrated into the gap. Therefore, the width of the gap14may be equal to or greater than 50 μm. The width of the gap14is preferably in the range of about 0.1 mm to 0.2 mm.

The front electrode2aof the semiconductor chip2accommodated in the second cavity10is electrically and mechanically connected to one end (end surfaces7aand8a) of each of the first terminals7and8buried in the ceramic case11by a conductive bonding material12. For example, when the semiconductor chip2is an IGBT, the first terminal7is connected to an emitter electrode and the first terminal8is connected to a gate electrode. In addition, the other ends (end surfaces7band8b) of the first terminals7and8are exposed from the electrode surface11aof the ceramic case11.

The main surface1aof the conductive plate1accommodated in the first cavity9is electrically and mechanically connected to one end (end surface6a) of the second terminal6buried in the ceramic case11by the conductive bonding material12. That is, the second terminal6is electrically connected to the rear electrode of the semiconductor chip2(a collector electrode in the case of an IGBT). In addition, the other end (end surface6b) of the second terminal6is exposed from the electrode surface11aof the ceramic case11.

The first terminals7and8and the second terminal6buried in the ceramic case11may be arranged in the vertical direction or the horizontal direction. InFIGS. 1(a), 1(b), one layer of the first terminal8is arranged in the horizontal direction. However, multiple layers of the first terminal8may be arranged. A portion of the first terminal8which is horizontally arranged has a thickness of about several hundreds of micrometers and a width of about several micrometers.

The first terminals7and8are fixed to the semiconductor chip2by the bonding material12and the second terminal6is fixed to the conductive plate1by the bonding material12. Then, the sealing material15is injected into the gap14through an inlet17provided in the ceramic case11. The injected sealing material15is infiltrated into the entire gap14by a capillary phenomenon and covers the semiconductor chip2or the conductive plate1.

The sealing material15has a function of sealing, electrically insulating, and protecting the semiconductor chip2or the conductive plate1. In addition, the sealing material15has a function of preventing humidity from being infiltrated into the bonding materials3and12and of preventing the deterioration of the bonding materials3and12. The sealing material15also has a function of fixing the ceramic case11, the semiconductor chip2, and the conductive plate1. Therefore, a material which has high electrical insulation and adhesion, high viscosity before hardening, and is likely to be infiltrated into the gap14by the capillary phenomenon is selected as the sealing material15. For example, an epoxy resin is preferable as the sealing material15.

Protrusions (not illustrated) with a size of about 0.1 mm to 0.2 mm may be provided on the inner wall of the first cavity9or the second cavity10to ensure the gap14such that the semiconductor chip2or the conductive plate1can be reliably covered with the sealing material15.

The conductive plate1has a function of making a current flow from the rear electrode2bof the semiconductor chip2to the second terminal6, a function of effectively dissipating heat generated from the semiconductor chip2to the outside (for example, a heat dissipation base (not illustrated) through the insulating plate4, and a function of supporting the semiconductor chip2. The conductive plate1is made of, for example, copper or aluminum. When the conductive plate1is a copper plate, nickel plating may be performed to prevent oxidation.

The insulating plate4may be made of a material with high electrical insulation and thermal conductivity. For example, a ceramic plate which is made of alumina, silicon nitride, or aluminum nitride and has a thickness of about 0.2 mm is suitable as the insulating plate4. In addition, an insulating resin, such as polyimide, may be used.

A bottom11bof the ceramic case11is substantially flush with a rear surface4bof the insulating plate4. In this case, it is possible to ensure high adhesion between the rear surface4bof the insulating plate4and a base plate provided on the rear surface4b.

In the power semiconductor device100according to this embodiment, the first terminals7and8and the second terminal6are provided in the ceramic case11in which the semiconductor chip2is accommodated. Therefore, a terminal for connection to the outside can be arranged immediately above the semiconductor chip2. In addition, since the semiconductor chip2and the conductive plate1are accommodated in the first cavity9and the second cavity10of the ceramic case11, it is possible to reduce the occupation area of the power semiconductor device100. Furthermore, the first terminals7and8and the second terminal are buried in the ceramic case11and are directly electrically and mechanically connected to the semiconductor chip2or the conductive plate1. Therefore, it is possible to reduce the thickness of the power semiconductor device100to about several millimeters. As a result, it is possible to reduce the size of the power semiconductor device100.

In the power semiconductor device1000(FIG. 19), the terminal for connection to the outside is arranged in the outer circumference of the case68. In contrast, in the power semiconductor device100, the ends (end surfaces7b,8b, and6b) of the first terminals7and8and the second terminal6are provided at arbitrary positions of the electrode surface11aof the ceramic case11. Therefore, the size of the power semiconductor device100is reduced and it is possible to significantly reduce a wiring length. In addition, it is possible to increase the cross-sectional area of a wire, as compared to the bonding wire67(FIG. 19). As a result, the inductance of the wire is reduced and it is possible to significantly reduce Joule heat generated from the wire.

Next, a method for manufacturing the ceramic case11will be described with reference toFIGS. 2(a)-2(d).

FIGS. 2(a)-2(d)are diagrams illustrating the method for manufacturing the ceramic case including the cavities and the terminals according to the first embodiment.

For example, the ceramic case11is obtained by laminating low-temperature cofired ceramic sheets (hereinafter, simply referred to as sheets), filling a predetermined opening portion with conductive paste, and performing sintering. The low-temperature cofired ceramic is a ceramic obtained by sintering glass and alumina at a low temperature of 1000° C. or less at the same time.

First, first to fifth opening portions25to29with different opening areas are formed in a plurality of (for example, four) sheets21to24(FIG. 2(a)). The first opening portion25formed in the sheet21and the sheet22becomes the first cavity9, and the second opening portion26formed in the sheet23becomes the second cavity10. The third to fifth opening portions27to29are filled with conductive paste30and become the first terminals7and8and the second terminal6, respectively. The opening portions25to29can be formed by, for example, punching.

Then, the third to fifth opening portions27to29are filled with the conductive paste30such as copper paste or silver paste (FIG. 2(b)). In this case, for example, a printing process may be used. Then, the sheets21to24are laminated (FIG. 2(c)).

Then, the laminated sheets21to24are sintered (FIG. 2(d)). Then, the sheets are fixed to each other. At the same time, the conductive paste30is sintered, and the first terminals7and8and the second terminal6are formed. Then, the first terminals7and8and the second terminal6are buried. In this way, the ceramic case11including the first and second cavities9and10is completed.

The size or thickness of the ceramic case11can be arbitrarily determined. In addition, the thickness of the sheets and the number of sheets to be laminated can be changed to form the first terminals7and8and the second terminal6in various shapes. The thickness of the first terminal8, which extends in the horizontal direction in the ceramic case11, in the horizontal direction may be in the range of, for example, about 0.2 mm to 1 mm, in terms of current capacity.

Next, modifications of the power semiconductor device100according to the first embodiment will be described.

First Modification

FIG. 3is a cross-sectional view illustrating a power semiconductor device according to a first modification.

A power semiconductor device101differs from the power semiconductor device100in that a first cavity9is shallow and a rear surface4bof an insulating plate4slightly protrudes from a ceramic case11. The slight protrusion (for example, about 0.1 mm) makes it possible to increase the adhesion between the rear surface4bof the insulating plate4and a base plate provided on the rear surface4band to reduce contact thermal resistance. Therefore, it is possible to improve the heat dissipation characteristics of a semiconductor chip2.

Second Modification

FIG. 4is a cross-sectional view illustrating a power semiconductor device according to a second modification.

A power semiconductor device102differs from the power semiconductor device100in that the second cavity10is not formed and a first cavity9is formed deep to be a one-stage cavity. The one-stage cavity makes it possible to reduce the number of sheets used to form the cavity and thus to reduce manufacturing costs.

A semiconductor chip2, a conductive plate1, and an insulating plate4are accommodated in the first cavity9which is a one-stage deep cavity. Therefore, a large gap P corresponding to the thickness of the semiconductor chip2can be formed between a main surface1aof the conductive plate1and an end surface6aof a second terminal6. A thick bonding material12amay be provided in the gap or, for example, a conductive block may be separately provided in the gap.

Third Modification

FIG. 5is a cross-sectional view illustrating a power semiconductor device according to a third modification.

A power semiconductor device103differs from the power semiconductor device100in that a metal plate5, such as a copper plate, is added to an insulating plate4in a first cavity9. That is, a conductive plate1, the insulating plate4, and the metal plate5can be replaced with a direct copper bonding (DCB) substrate18. The addition of the metal plate5makes it possible to bond the metal plate5and a base plate provided on the lower surface of metal plate5with solder. Therefore, it is possible to further reduce thermal resistance.

Second Embodiment

FIGS. 6(a)to9are diagrams illustrating a process of manufacturing a power semiconductor device according to a second embodiment.

First, a main surface1aof a conductive plate1and a rear electrode2bof a semiconductor chip2are bonded to each other by a conductive bonding material3. In addition, an insulating plate4is bonded to a surface1bof the conductive plate1opposite to the main surface1a(FIG. 6(a)). A ceramic case11is prepared by the manufacturing method illustrated inFIGS. 2(a)-2(d)(FIG. 6(b)).

Then, the ceramic case11is placed on a supporting table40, with an opening portion9aof a first cavity9down. Then, a bonding material12, such as solder plate, is placed on the end surfaces7aand8aof first terminals7and8and the end surface6aof a second terminal6which are exposed from the first and second cavities9and10(FIG. 7).

Then, a unit including the semiconductor chip2, the conductive plate1, and the insulating plate4illustrated inFIG. 6(a)is turned upside down and is then fitted to the first and second cavities9and10of the ceramic case11(FIG. 8). At that time, the gap14is in the range of about 0.1 mm to 0.2 mm. In addition, at that time, the end surface6aof the second terminal6contacts the main surface1aof the conductive plate1through the bonding material12. The end surfaces7aand8aof the first terminals7and8contact a front electrode (not illustrated) of the semiconductor chip2through the bonding material12. Then, all of the above-mentioned components are put into a reflow furnace13and a reflow process is performed in a defoamed atmosphere to bond the contact portions with the bonding material12.

Then, a dispenser16is used to pour a sealing material into the gap14between the unit and the ceramic case11through an inlet17(FIG. 9). Finally, for example, a heat treatment is performed to harden the sealing material15filled in the gap14. In this way, the power semiconductor device100illustrated inFIGS. 1(a), 1(b)is completed.

FIG. 10is a diagram illustrating the inlet through which the sealing material of the power semiconductor device according to the second embodiment is injected.FIG. 10is a plan view as viewed from the bottom11bof the ceramic case11.

In the power semiconductor device1000(FIG. 19), since a large amount of Joule heat is generated, a plurality of bonding wires67is provided on the front electrode of the semiconductor chip66. In contrast, in the power semiconductor device100according to this embodiment, it is possible to increase the cross-sectional area of the first terminals7and8and the second terminal6. Therefore, one terminal may be provided on the front electrode2aof the semiconductor chip2. In this way, it is possible to simplify an assembly process. Therefore, for example, it is possible to shorten an assembly time, to improve yield, and to reduce the number of quality managers. As a result, it is possible to reduce the manufacturing costs of the power semiconductor device100.

Third Embodiment

FIG. 11is a cross-sectional view illustrating a power semiconductor device according to a third embodiment.

A power semiconductor device200differs from the power semiconductor device100in that two semiconductor chips2are fixed to one conductive plate.

The two semiconductor chips2are, for example, an IGBT chip and a free wheeling diode (FWD) chip. A collector electrode of the IGBT chip and a cathode electrode of the FWD chip are electrically and mechanically connected to a conductive plate1. An emitter electrode of the IGBT chip and an anode electrode of the FWD chip are electrically and mechanically connected to one end of each of two first terminals7buried in a ceramic case11. The other ends of the two first terminals7are electrically connected to each other to form an anti-parallel circuit of the IGBT and the FWD.

Fourth Embodiment

FIG. 12is a cross-sectional view illustrating a power semiconductor device according to a fourth embodiment.

A power semiconductor device300includes a ceramic case11having two sets of first and second cavities9and10and the above-mentioned units which are accommodated in the first and second cavities9and10. In this example, two sets of the first and second cavities9and10are illustrated inFIG. 12. However, the invention is not limited to this. In addition,FIG. 12illustrates a case in which one semiconductor chip2is fixed to one conductive plate1and two semiconductor chips2are fixed to the other conductive plate1.

As in this embodiment, plural sets of the first and second cavities9and10are provided in one ceramic case11and plural sets of units are mounted. Therefore, it is possible to provide the power semiconductor device300which has a small size and a complicated circuit structure at a low cost.

Fifth Embodiment

FIG. 13is a cross-sectional view illustrating a power semiconductor device according to a fifth embodiment.

A power semiconductor device400is obtained by connecting the ceramic cases11of two power semiconductor devices100with an attachment19. In the power semiconductor device400, the two power semiconductor devices100are integrated with each other. A main body of the attachment19is an insulator. Conductors19awhich are electrically connected to the first terminals7and8and the second terminals6are provided in the attachment19. In this example, two power semiconductor devices100are integrated with each other. However, the number of power semiconductor devices100to be integrated with each other is arbitrary. According to this structure, it is possible to provide the power semiconductor devices400with various ratings, without increasing the number of systems.

Sixth Embodiment

FIG. 14is a cross-sectional view illustrating a power semiconductor device according to a sixth embodiment. In the sixth embodiment, the same members as those in the power semiconductor device100illustrated inFIGS. 1(a), 1(b)are denoted by the same reference numerals and the description thereof will not be repeated.

A power semiconductor device500includes a semiconductor chip2, a wiring substrate32, and a ceramic case31. The ceramic case31and the wiring substrate32form a housing. In addition, the power semiconductor device500includes a sealing material15.

The wiring substrate32has a conductive wiring plate33buried therein. A rear electrode2bof the semiconductor chip2is electrically and mechanically connected to an exposure surface33aof the wiring plate33.

The ceramic case31includes ceramic20. First terminals7and8and a second terminal6are buried in the ceramic case31. In addition, the ceramic case31has a second cavity10with a concave shape. The ceramic case31further has an electrode surface31awhich is opposite to an opening portion of the second cavity10.

The semiconductor chip2is accommodated in the second cavity10. A sealing material15is provided in a gap14between the semiconductor chip2and the second cavity10.

A front electrode2aof the semiconductor chip2accommodated in the second cavity10is electrically and mechanically connected to one end (end surfaces7aand8a) of each of the first terminals7and8buried in the ceramic case31. In addition, the other ends of the first terminals7and8are exposed from the electrode surface31aof the ceramic case31.

The exposure surface33aof the wiring plate33is electrically and mechanically connected to one end (end surface6a) of the second terminal6buried in the ceramic case31. That is, the second terminal6and the rear electrode of the semiconductor chip2are electrically connected to each other. The other end of the second terminal6is exposed from the electrode surface31aof the ceramic case31.

The sealing material15is injected through an inlet17provided in the ceramic case31and fills up the gap14. The sealing material15is also used to fix the ceramic case31and the wiring substrate32. In addition, an adhesive different from the sealing material15may be used to fix the ceramic case31and the wiring substrate32. The inlet17for the sealing material15may be provided in the wiring substrate32.

As in this embodiment, when the wiring substrate32is used to wire the rear electrode2bof the semiconductor chip2, it is possible to respond to a high voltage.

Next, modifications of the power semiconductor device500will be described.

Fourth Modification

FIG. 15is a cross-sectional view illustrating a power semiconductor device according to a fourth modification.

A power semiconductor device501differs from the power semiconductor device500in that dummy conductive films34are provided in a ceramic case31and a wiring substrate32and are bonded to each other by a bonding material12such as solder.

In this modification, a process of providing the dummy conductive film34can be performed at the same time as a process of providing the first terminals7and8and the second terminal6or a process of providing the wiring plate33. In addition, the bonding material12can be collectively formed by the above-mentioned reflow process. Therefore, an additional process is not required. In addition, it is possible to improve the bonding strength between the ceramic case31and the wiring substrate32. As a result, it is possible to improve reliability.

Fifth Modification

FIG. 16is a cross-sectional view illustrating a power semiconductor device according to a fifth modification.

A power semiconductor device502differs from the power semiconductor device500in that a concave portion35is provided in a ceramic case31, a convex portion36corresponding to the concave portion35is provided in a wiring substrate32, and the concave portion35and the convex portion36are fitted to each other to fix the ceramic case31and the wiring substrate32. For example, the concave portion35and the convex portion36are provided in a ring shape so as to surround a semiconductor chip2. Therefore, it is possible to increase the length of an interface37between the ceramic case31and the wiring substrate32. As a result, it is possible to improve the function of preventing the infiltration of humidity or a foreign material from the interface37. In addition, it is possible to weaken creeping discharge at the interface37.

Seventh Embodiment

FIGS. 17(a), 17(b)are diagrams illustrating the structure of a power semiconductor device according to a seventh embodiment.FIG. 17(a)is a plan view andFIG. 17(b)is a cross-sectional view taken along the line17(b)-17(b) ofFIG. 17(a).FIG. 17(a)is a plan view as viewed from the direction of an arrow A inFIG. 17(b).

A power semiconductor device600includes a ceramic case31having a cavity10, a wiring substrate32having a cavity38, and a semiconductor chip2accommodated in the cavity38and the second cavity10. A wiring plate33which is buried in the wiring substrate32has an exposure surface33awhich is exposed from the bottom of the cavity38.

Eighth Embodiment

FIG. 18is a cross-sectional view illustrating a power semiconductor device according to an eighth embodiment.

A power semiconductor device700differs from the power semiconductor device500in that a second terminal39is buried in the ceramic case31and protrudes from a side surface31cperpendicular to an electrode surface31aof the ceramic case31. The second terminal39is electrically and mechanically connected to a wiring plate33of a wiring substrate32by a bonding material12such as solder.

In some cases, the protrusion of the second terminal39from the side surface31cof the ceramic case31facilitates the assembly of a power conversion apparatus using the power semiconductor device700. The second terminal39may have a thickness W of about 1 mm or more, in terms of current capacity.

Only the principle of the invention has been described above. Various modifications and changes of the invention can be made by those skilled in the art. The invention is not limited to the above-described accurate structures and applications and all of the corresponding modifications and equivalents fall within the scope of the invention defined by the appended claims and equivalents thereof.

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