Manufacturing method and structure for a substrate with vertically embedded capacitor

A manufacturing method and structure for substrate with vertically embedded capacitors includes the steps of providing a plurality of conductive layers having a first dielectric layer and a leading wire layer formed on the first dielectric layer, providing a plurality of composite layers having a second dielectric layer and a patterned electrode layer formed on the second dielectric layer, laminating the conductive layers and the composite layers to form a block which defines a plurality of substrates with vertically embedded capacitors and a plurality of sawing streets between the substrates, and sawing the block along the sawing streets to singularize the substrates.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a substrate with embedded capacitors, and more particularly, to a substrate with vertically embedded capacitors.

2. Description of the Prior Art

Referring toFIG. 1, a conventional substrate10with embedded capacitors typically includes a top surface11, a bottom surface12, a plurality of leading wires14, and a plurality of embedded capacitors13electrically connected to the leading wires14. The embedded capacitors13further includes a first electrode131, a dielectric layer132, and a second electrode133, in which the first electrode131and the second electrodes132are disposed in a parallel manner on the top surface11and the bottom surface12respectively. A chip50is electrically connected to the embedded capacitors13through the leading wires14. Preferably, the layout of the first electrode131and the second electrode133of the embedded capacitors13is designed with respect to a horizontal manner, in which the electrodes are placed in a parallel manner on the top surface11and the bottom surface12. This design not only reduces the utilization space but also limits the number of embedded capacitors13that can be placed on the substrates. If the number of embedded capacitors13becomes insufficient and extra capacitors were to be added externally, an additional surface mount process may be required and the overall cost and size of the package would increase accordingly.

SUMMARY OF THE INVENTION

It is an objective of the present invention to provide a substrate with vertically embedded capacitors and method for fabricating the same. Preferably, the method of the present invention not only eliminates the need of using surface mount technique for adding extra capacitors, but also reduces the overall volume and the fabrication cost of the package significantly.

A method for fabricating a substrate with vertically embedded capacitors is disclosed, in which the method includes the steps of providing a plurality of conductive layers having a first dielectric layer and a leading wire layer formed on the first dielectric layer; providing a plurality of composite layers having a second dielectric layer and a patterned electrode layer formed on the second dielectric layer; laminating the conductive layers and the composite layers for forming a block that defines a plurality of substrates with vertically embedded capacitors and a plurality of sawing streets between the substrates; and sawing the block along the sawing streets for singularizing the substrates, in which each of the substrates has a first surface and a second surface.

Another method for fabricating a substrate with vertically embedded capacitors is disclosed, in which the method includes the steps of providing a plurality of conductive layers having a first dielectric layer and a leading wire layer formed on the first dielectric layer; providing a plurality of first composite layers having a second dielectric layer and a patterned electrode layer formed on the second dielectric layer; providing a plurality of second composite layers having a third dielectric layer and a sheet electrode layer formed on the third dielectric layer; laminating the conductive layers, the first composite layers, and the second composite layers for forming a block that defines a plurality of substrates with vertically embedded capacitors and a plurality of sawing streets between the substrates; and sawing the block along the sawing streets for singularizing the substrates, in which each of the substrates has a first surface and a second surface.

According to another aspect of the present invention, a substrate with vertically embedded capacitors is also provided. Specifically, the substrate includes a plurality of conductive layers and a plurality of first composite layers. Each of the conductive layers includes a first dielectric layer and a leading wire layer formed on the first dielectric layer, and each of the first composite layers having a patterned electrode layer and a second dielectric layer is disposed between the conductive layers, in which the patterned electrode layer includes a plurality of electrodes.

DETAILED DESCRIPTION

Please refer toFIGS. 2A-2C.FIGS. 2A-2Cillustrate a method for fabricating a substrate with vertically embedded capacitors according the first embodiment of the present invention. As shown inFIG. 2A, a plurality of conductive layers21is provided, in which each of the conductive layers21is composed of a first dielectric layer212and a leading wire layer211formed thereon. In the present embodiment, the leading wire layer211is fabricated from a sheet metal layer via a series of photolithography processes. Preferably, the leading wire layer211is composed of a plurality of leading wires21la, in which the leading wires21la are used to replace the conventional through holes of a substrate.

As shown inFIG. 2B, a plurality of composite layers22is provided, in which each of the composite layers22is composed of a second dielectric layer222and a patterned electrode layer221formed thereon. Preferably, the patterned electrode layer221is also fabricated from a sheet metal layer via a series of photolithography processes (not shown). The patterned electrode layer221also includes a plurality of electrodes221a for forming a plurality of capacitors C, as shown inFIG. 2C. Depending on the demand of the product, the capacitors C can be electrically connected in parallel or series. According to the preferred embodiment of the present invention, the electrodes221a are arranged in an array, and the second dielectric layers222and the first dielectric layers212are made of such as epoxy resin, FR4, BT resin, high polymer materials, or ceramic materials.

Next, as shown inFIG. 2C, the conductive layers21and the composite layers22are laminated to form a block B. The block B specifically defines a plurality of substrates20having vertically embedded capacitors and a plurality of sawing streets B1 between the substrates20. Preferably, the size of the substrate20with vertically embedded capacitors can be adjusted according to the specification of the product. Thereafter, as shown inFIG. 2D, the block B is being sawed along the sawing streets B1to singularize the substrates20. Each of the singularized substrates20has a first surface201and a second surface202, in which the first surface201and the second surface202expose the leading wires211aand the electrodes221a. The leading wires211aand the electrodes221acan be used to electrically connect at least a chip or a circuit device (not shown).

With reference toFIG. 3, at least a wiring layer23can also be formed on the first surface201and the second surface202of the substrate20. Preferably, the wiring layer23can be utilized to establish a connection between the aforementioned chips, circuit devices and the substrate20by electrically connecting the leading wires211aof the leading wire layer211and the electrodes221aof the patterned electrode layer221. Alternatively, as shown inFIG. 4, a plurality of bumps24can be formed on the wiring layer23to establish a connection between the chips and the substrate20with vertically embedded capacitors.

Please refer toFIGS. 5A-5E.FIGS. 5A-5Eillustrate a method for fabricating a substrate30with vertically embedded capacitors according to the second embodiment of the present invention. As shown inFIG. 5A, a plurality of conductive layers31is provided, in which each of the conductive layers31includes a first dielectric layer312and a leading wire layer311formed thereon. The leading wire layer311is composed of a plurality of leading wires31la. As shown inFIG. 5B, a plurality of first composite layers32is provided, in which each of the first composite layers32includes a second dielectric layer322and a patterned electrode layer321formed thereon. Preferably, each patterned electrode layer321includes a plurality of electrodes321aand the electrodes321aare arranged in an array. As shown inFIG. 5C, a plurality of second composite layers33is provided, in which each of the second composite layers33includes a third dielectric layer332and a sheet electrode layer331formed on the third dielectric layer332. The third dielectric layer332, the second dielectric layer322, and the first dielectric layer312can be made of same or different material. Next, as shown inFIG. 5D, the conductive layers31, the first composite layers32, and the second composite layers33are laminated to form a block B. The block B specifically defines a plurality of substrates30with vertically embedded capacitors and a plurality of sawing streets B1between the substrates30. Subsequently, as shown inFIG. 5E, the block B is being sawed along the sawing streets B1to singularize the substrates30. Each of the singularized substrates30has a first surface301and a second surface302, in which the first surface301and the second surface302expose the leading wires31la, the electrodes321a, and the sheet electrode layers331. The leading wires311a, the electrodes321a, and the sheet electrode layer331can be used to electrically connect at least a chip or a circuit device (not shown).

Referring toFIG. 6, at least a wiring layer34can be formed on the first surface301and the second surface302of the substrate30with vertically embedded capacitors. The wiring layer34is electrically connected to the leading wires311aof the leading wires layer311, the electrodes321aof the patterned electrode layer321, and the sheet electrode layer331, such that the chips or the circuit devices can be electrically connected to substrate30through the wiring layer34. Alternatively, as shown inFIG. 7, a plurality of bumps35can be formed on the wiring layer34, such that the chip or the circuit devices can be electrically connected to the substrate30through the bumps35.

FIGS. 5E and 6further illustrate the structure of the substrate with vertically embedded capacitors of the present invention. As shown in the figures, the substrate30includes a plurality of conductive layers31and a plurality of first composite layers32. Each of the conductive layers31includes a first dielectric layer312and a leading wire layer311formed on the first dielectric layer312, in which the leading wire layer311is composed of a plurality of leading wires311a. The first composite layers32are disposed between the conductive layers31, in which each of the first composite layers32includes a patterned electrode layer321and a second dielectric layer322. The patterned electrode layer321is composed of a plurality of electrodes321aarranged corresponding to an array. In the present embodiment, the substrate30also includes a plurality of second composite layers33formed between the conductive layers31, in which each of the second composite layers33includes a sheet electrode layer331and a third dielectric layer332. Alternatively, the second composite layers33can be formed between the first composite layers32, which are also within the scope of the present invention. By using the vertically embedded capacitors composed of the patterned electrode layers321and the second dielectric layers322, or the sheet electrode layers331and the third dielectric layers332, the present invention could expand the overall space for designing circuit layout and increase the flexibility of the design significantly. Moreover, this fabricating method also minimizes the need for adding external capacitors via surface mount technology, thereby reducing the overall volume and fabrication cost of the package.