Removing unwanted flux from an integrated circuit package

A surface-mounted integrated circuit (IC) package is disclosed that has unwanted flux removed from surface-mounted IC. A bottom termination component (BTC) includes lands and a thermal pad. The lands provide an electrical connection from the BTC and the thermal pad provides heat transfer from the BTC. The thermal pad includes vias that are configured to remove flux generated from solder applied to the surface-mounted IC as the surface-mounted IC is assembled. A printed circuit board (PCB) is mounted to the BTC and is electrically connected to the BTC via the lands and receives heat transfer from the BTC via the thermal pad and includes a reservoir. The reservoir is configured to pull flux positioned between the lands into the reservoir as the flux is generated from the solder applied to the surface-mounted IC as the BTC is mounted to the PCB and as the surface-mounted IC is assembled.

BACKGROUND

The present disclosure relates generally to surface-mounted integrated circuit (IC) packages and specifically to removing unwanted flux from IC packages.

Conventional bottom termination components (BTC) packages having lands positioned along the bottom surface of the BTC packages lowers the risk of damage to the lands as compared to the exposed pins, terminals, and/or wire leads of conventional packages. Further, the conventional BTC packages having lands positioned along the bottom surface of the BTC packages also enables an increased PCB design density where an increased quantity of BTC packages may be positioned on a single PCB as the BTC packages may be positioned closer together due to the BTC packages having lands positioned along the bottom surface of the BTC packages, as opposed to pins, terminals, and/or wire leads extending further out from the perimeter of conventional packages.

However, conventional BTC packages also have traits that may result in an increased amount of flux residue that remains after the conventional BTC package is mounted to the PCB. The short die to PCB path results in a decreased space between the conventional BTC package and the PCB which hinders the amount of unwanted flux residue that is flushed out from between the conventional BTC package and the PCB. The soldering of the thermal pad to the PCB results in voids that are difficult to avoid. Thus, unwanted flux residues remain after the conventional BTC package is mounted to the PCB if not addressed.

Current leakage unnecessarily drains the battery life of the system. Lower signal-to-surface insulation resistance (SIR) values indicate undesired paths for current leakage that results in unnecessary battery drain. Unwanted flux residues that remain on the conventional BTC packages after being mounted to the PCBs included in the system create opportunities for electro-chemical migration, dendritic growth, and/or corrosion and thus provides an increased opportunity of current leakage that unnecessarily drains the battery life of the battery source of the system. Thus, eliminating unwanted flux residue during the mounting of the conventional BTC package to the PCB is critical in decreasing current leakage that may unnecessarily drain the battery life of the battery source of the system.

BRIEF SUMMARY

Embodiments of the present disclosure relate to surface mounting an integrated circuit (IC) package with bottom termination components (BTCs) onto a printed circuit board (PCB) and in doing so removing unwanted flux from the assembled IC. In an embodiment, a surface-mounted integrated circuit (IC) package includes at least one bottom termination component (BTC) that includes a plurality of lands and a thermal pad. The plurality of lands provides an electrical connection from the BTC and the thermal pad provides heat transfer from the BTC and the thermal pad includes a plurality of vias that is configured to remove flux generated from solder applied to the surface-mounted IC as the surface-mounted IC is assembled. A printed circuit board (PCB) is mounted to the BTC and is electrically connected to the BTC via the plurality of lands and receives the heat transfer from the BTC via the thermal pad and includes at least one reservoir. The at least one reservoir is configured to pull flux positioned between the plurality of lands into the at least one reservoir as the flux is generated from the solder applied to the surface-mounted IC as the BTC is mounted to the PCB as the surface-mounted IC is assembled.

In one embodiment, a method removes flux generated from solder is applied to a surface-mounted integrated circuit (IC) as the surface-mounted IC is assembled. At least one bottom termination component (BTC) is mounted that includes a plurality of lands and a thermal pad to a printed circuit board (BTC) that includes at least one reservoir. An electrical connection between the BTC and the PCB is provided via the plurality of lands. Heat transfer from the BTC to the PCB is provided via the thermal pad. The thermal pad includes a plurality of vias. Flux generated from the solder applied to the surface-mounted ITC is removed as the surface-mounted IC is assembled via the plurality of vias included in the thermal pad. Flux positioned between the plurality of lands is pulled into the at least one reservoir as the flux is generated from the solder applied to the surface-mounted IC as the surface-mounted IC is assembled.

In another embodiment, a surface-mounted integrated circuit (IC) package includes at least one bottom termination component (BTC) that includes a thermal pad that provides heat transfer from the BTC. The thermal pad includes a plurality of vias that is configured to remove flux generated from solder applied to the surface-mounted IC as the surface-mounted IC is assembled. A printed circuit board (PCB) is mounted to the BTC and receives the heat transfer from the BTC via the thermal pad. A plurality of lands with each land including a peripheral terminal that is electrically connected to a corresponding terminal from the plurality of terminals associated with the BTC and a trace that extends from the corresponding peripheral terminal and extends beyond a solder mask that is applied to the surface-mounted IC package. Each trace is connected to a corresponding peripheral terminal and is configured to prevent the BTC from tilting as the BTC is mounted PCB.

In another embodiment, a system controls an access control device via a controller incorporated into a surface-mounted integrated circuit (IC) package. An access control device is configured to execute an action to regulate access to a space. At least one component associated with the access control device is configured to detect data associated with activity involving access to the space. A controller is configured to instruct the access control device to execute the action based on the data detected by the at least one component to regulate the space. The controller includes at least one bottom termination component (BTC) that includes a plurality of lands and a thermal pad. The plurality of lands provides an electrical connection from the BTC and the thermal pad provides heat transfer from the BTC. The thermal pad includes a plurality of vias that is configured to remove flux generated from solder applied to the surface-mounted IC as the surface-mounted IC is assembled. A printed circuit board (PCB) is mounted to the BTC and is electrically connected to the BTC via the plurality of lands and receives the heat transfer from the BTC via the thermal pad and includes at least one reservoir. The at least one reservoir is configured to pull flux positioned between the plurality of lands into the at least one reservoir as the flux is generated from the solder applied to the surface-mounted IC as the BTC is mounted to the PCB as the surface-mounted IC is assembled.

DETAILED DESCRIPTION OF THE PRESENT DISCLOSURE

The following Detailed Description refers to accompanying drawings to illustrate exemplary embodiments consistent with the present disclosure. References in the Detailed Description to “one exemplary embodiment,” an “exemplary embodiment,” an “example exemplary embodiment,” etc., indicate the exemplary embodiment described may include a particular feature, structure, or characteristic, but every exemplary embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same exemplary embodiment. Further, when a particular feature, structure, or characteristic may be described in connection with an exemplary embodiment, it is within the knowledge of those skilled in the art(s) to effect such feature, structure, or characteristic in connection with other exemplary embodiments whether or not explicitly described.

The exemplary embodiments described herein are provided for illustrative purposes, and are not limiting. Other exemplary embodiments are possible, and modifications may be made to the exemplary embodiments within the spirit and scope of the present disclosure. Therefore, the Detailed Description is not meant to limit the present disclosure. Rather, the scope of the present disclosure is defined only in accordance with the following claims and their equivalents.

For purposes of this discussion, each of the various components discussed may be considered a module, and the term “module” shall be understood to include at least one software, firmware, and hardware (such as one or more circuit, microchip, or device, or any combination thereof), and any combination thereof. In addition, it will be understood that each module may include one, or more than one, component within an actual device, and each component that forms a part of the described module may function either cooperatively or independently from any other component forming a part of the module. Conversely, multiple modules described herein may represent a single component within an actual device. Further, components within a module may be in a single device or distributed among multiple devices in a wired or wireless manner.

Conventional Approaches to Mounting BTC Packages to a PCB

FIG. 1illustrates a top-elevational view of a conventional QFN package configuration100based on the IPC-7351 standard. In a conventional approach, a user may enter the dimensions of the conventional QFN package that the user requests and the IPC-7351 standard may then generate the conventional QFN package configuration100based on the dimensions entered by the user and the requirements provided under the IPC-7351 standard. The conventional QFN package configuration100includes a plurality of conventional lands110(a-n), where n is an integer equal to or greater than one, and is based on the dimensions of the conventional QFN package that the user requests and the requirements provided under the IPC-7351 standard.

The conventional lands110(a-n) have rounded edges and are a single structure in that each of the conventional lands110(a-n) simply include the rounded edged structure that protrude under the conventional QFN package130as well as beyond the boundary120of the conventional QFN package130. For example, the conventional land110aincludes a first portion115athat protrudes under the conventional QFN package130as well as the second portion115bthat protrudes well beyond the boundary120of the conventional QFN package130. However, both the first portion115aand the second portion115bare part of the same conventional land110awith simply the first portion115apositioned under the conventional QFN package130and the second portion115bprotruding well beyond the boundary120of the conventional QFN package130. Further the dimensions of the first portion115aof the conventional land110athat protrudes under the conventional QFN package130fails to match the dimensions of the corresponding terminal (not shown) of the conventional QFN package130. Similarly, each of the dimensions of the first portions for each of the corresponding conventional lands110(b-n) also fail to match the dimensions of the corresponding terminals (not shown) of the conventional QFN package130.

In applying solder to each of the conventional lands110(a-n) to electrically connect each of the corresponding terminals to each of the conventional lands110(a-n) in order to electrically connect the conventional QFN package130to the conventional PCB140, an immense amount of flux residue generated from the solder application may result in between the conventional QFN package130and the conventional PCB140as well as around the QFN package130. Such excess flux residue may provide an increased risk in electro-chemical migration, dendritic growth, and/or corrosion and thus providing an increased opportunity of current leakage.

Further, the second portion115bof the conventional lands110(a-n) may protrude a significant distance beyond the boundary120of the conventional QFN package130such that the second portion115bof the conventional lands110(a-n) may be sawed and/or sheared when the conventional QFN package configuration100is removed from the PCB panel (not shown). After the second portion115bof the conventional lands110(a-n) have been sawed and/or sheared through when the conventional QFN package configuration100is removed from the PCB panel, sheared portions of the QFN package configuration100are not replated. The exposed metal lead frames included in the conventional PCB140then begin to oxidize and fail to wet when solder and heat are applied to the exposed metal lead frames. In doing so, the further that the second portion115bof the conventional lands110(a-n) protrude beyond the boundary120of the conventional QFN package130, a greater surface area of the conventional lands110(a-n) are wet, but as the solder cools a solder joint between the conventional QFN package130and the conventional PCB140fails to form. Rather, a useless solder ball forms outside of the boundary120of the conventional QFN package130and generates flux residue that may trigger an increased opportunity of current leakage.

FIG. 2illustrates a top-elevational view of a conventional QFN package configuration200based on the IPC-7351 standard that incorporates rectangular lands. The conventional QFN package configuration200includes a plurality of conventional rectangular lands210(a-n), where n is an integer equal to or greater than one, and is based on the dimensions of the conventional QFN package that the user requests and the requirements provided under the IPC-7351 standard.

Rather than being rounded, each of the conventional rectangular lands210(a-n) are rectangular shaped and are a single structure in that each of the conventional rectangular lands210(a-n) simply include the rectangular shaped structure that protrude under the conventional QFN package230as well as beyond the boundary220of the conventional QFN package230. For example, the conventional rectangular land210aincludes a first portion215athat protrudes under the conventional QFN package230as well as the second portion215bthat protrudes well beyond the boundary220of the conventional QFN package230. However, both the first portion215aand the second portion215bare part of the same conventional rectangular land215awith simply the first portion215apositioned under the conventional QFN package230and the second portion215bprotruding well beyond the boundary220of the conventional QFN package230. The conventional rectangular lands210(a-n) have similar issues regarding excess flux residue as discussed above regarding the conventional lands210(a-n).

Further, the solder when applied to the conventional rectangular lands210(a-n) to electrically connect the conventional QFN package230to the conventional PCB240coalesces back into a ball when the solder cools thereby generating rounded solder joints. However, the conventional rectangular lands210(a-n) are not circular but are rather rectangular. Thus, the elliptical shaped solder joint that is formed fails to match the rectangular shape of the conventional rectangular lands210(a-n) thereby does not adequately attach the conventional rectangular lands210(a-n) to the corresponding terminal (not shown) of the conventional QFN package230. Rather, a useless rounded solder ball forms outside of the boundary220of the conventional QFN package230and generates flux residue that may trigger an increased opportunity of current leakage.

FIG. 3illustrates a top-elevational view of a conventional QFN package300that portrays a conventional via in pad plated over (VIPPO) configuration. The conventional QFN package300includes a thermal pad310that has a plurality of vias320(a-n), where n is an integer equal to or greater than one. The plurality of vias320(a-n) is then plated over to fill the vias320(a-n) via the conventional VIPPO configuration. However, on a top surface330of the thermal pad310that is opposite a bottom surface of the thermal pad310that is coupled to a conventional340PCB, air is trapped between each via320(a-n) at the top surface330of the thermal pad310and the screen print paste that is placed on the conventional QFN package300in plating over each of the vias320(a-n) via the conventional VIPPO configuration. In doing so, a divot is created on the top surface330of the thermal pad310at each of the vias320(a-n) from the air that is trapped between the screen print paste and the vias320(a-n) via the conventional VIPPO configuration. Each of the divots created in the top surface330of the thermal pad310is not substantially planar causing issues for the conventional QFN package300.

FIG. 4illustrates a top-elevational view of a conventional QFN package400that portrays a conventional VIPPO configuration where strips of solder applied in each of the vias to connect the vias to the solder mask that is applied to the conventional QFN package400. The conventional QFN package400includes a thermal pad410that has a plurality of vias420(a-n), where n is an integer value equal to or greater than one. The plurality of vias is then plated over with a solder mask to fill the vias420(a-n) via the conventional VIPPO configuration. In addition to the solder mask being applied via the conventional VIPPO configuration, strips of solder are positioned in each of the vias420(a-n) to attach each of the strips of solder to the solder mask applied at the top surface430of the thermal pad410to prevent the solder mask from peeling off the top surface430of the thermal pad410at each of the vias420(a-n). However, in placing strips of solder into each of the vias420(a-n) to attach each of the strips of solder to the solder mask that is applied to the top surface430of the thermal pad410, voids are generated in each of the vias420(a-n). Voids prevent the gas generated from the flux inside each of the vias420(a-n) from escaping which in turn generates flux residue that may trigger an increased opportunity of current leakage.

FIG. 5illustrates a top-elevational view of a conventional QFN package configuration500that portrays a conventional windowpane paste that is applied to the thermal land where the thermal pad is electrically connected to the thermal land positioned on the conventional PCB. The conventional QFN package configuration500includes a conventional thermal land510is positioned on top surface the conventional PCB540which is where the bottom surface of the thermal pad is electrically connected to the conventional thermal land510of the conventional PCB540. The conventional thermal land510includes a plurality of solder areas520(a-n) where solder is applied to electrically connect the thermal pad to the conventional thermal land510of the conventional PCB540. However, insufficient heat is able to reach the solder to generate sufficient flux for the flux to coalesce at each of the solder areas520(a-n) to adequately electrically connect the thermal pad to the conventional thermal land510.

Thus, BTC packages best perform when excess flux is able to be purged from the BTC package when the BTC package is mounted to the PCB in order to remove any flux residue that may remain from the excess flux. As noted above, the excess flux residue may increase the likelihood of electro-chemical migration, dendritic growth, and/or corrosion and thus providing an increased opportunity of current leakage thereby unnecessarily draining the battery life of the battery source of the system that the BTC package is associated. Specifically, BTC packages have an increase in performance when uneven solder joint variation is limited thus resulting in the BTC package being substantially planar relative to the PCB. BTC packages also have an increase in performance when voiding is avoided in the thermal pad, robust solder joints are generated to withstand shock, an acceptably high SIR to limit the current leakage of the BTC package, and the BTC package is encapsulated from the environment.

Bottom termination components (BTC) are surface-mounted ICs that have contacts shifted to the bottom surface of the package. For example, BTCs include but are not limited to quad-flat no-leads (QFN) packages and dual-flat no-leads (DFN) packages where the IC packages are surface mounted to printed circuit boards (PCB) and electrically connected to the PCBs via lands positioned along the perimeter of the package and along the bottom surface of the package. Other examples of BTCs include but are not limited to quad-flat packages and ball grid arrays (BGA).

Approaches to Reduce Flux Residue of a BTC Package

FIG. 6illustrates a top-elevational view of a BTC package configuration600that reduces flux residue of the BTC package according to an exemplary embodiment of the present disclosure. The BTC package configuration600includes a plurality of vias620(a-n), where n is an integer equal to or greater than one. The vias620(a-n) provide an electrical connection between the layers of the BTC package configuration600where the vias620(a-n) pass through the adjacent layers of the BTC package configuration600.

In an embodiment, each of the vias620(a-n) may be positioned in a staggered row and column formation such that each row of vias620(a-n) is not aligned with each immediate adjacent row of vias620(a-n) and each column of vias is not aligned with each immediate adjacent column of vias. For example, the row of vias620a,620b,and620care not aligned with the adjacent row of vias620dand620e.Further the column of vias including620ais not aligned with the adjacent column of vias including620d.In an embodiment, each of the vias620(a-n) may be positioned in a uniform matrix such that each row of vias620(a-n) is aligned with each immediate adjacent row of vias620(a-n) and each column of vias is aligned with each immediate adjacent column of vias. For example, the row of vias620a,620b,and620care aligned with the adjacent row of vias620dand620e.Further the column of vias including620ais aligned with the adjacent column of vias including620d.

The vias620(a-n) may remove flux generated from solder applied to the BTC package configuration600as the BTC package630is mounted to the PCB640. Each of the vias620(a-n) may extend from a first surface650of a thermal pad660of the BTC package630where the first surface650is the top surface of the thermal pad660and extend through the thermal pad660to a second surface (not shown) of the thermal pad660that is mounted to the PCB640where the second surface is the bottom surface of the thermal pad660opposite the first surface650of the thermal pad660. The vias620(a-n) may purge flux from the first surface650of the thermal pad660and from between a plurality of lands610(a-n), where n is an integer equal to or greater than one as the flux is generated from the solder applied to the BTC package configuration600. The flux may be pushed through the vias620(a-n) from the second surface of the thermal pad660out onto a bottom surface (not shown) of the PCB640that is positioned opposite a top surface670of the PCB640that the BTC package630is mounted so that the flux is removed from between the thermal pad660and the PCB640and from between the lands610(a-n).

As the solder paste is printed on the BTC package configuration600, the solder paste covers the BTC package configuration600and some of the solder may wick into the vias620(a-n). The solder may then be heated and flux in the solder may be generated as the solder begins to boil as the solder transfers from a liquid state to a gas state. The generated flux may then escape from the metal positioned in the PCB640and coalesce into a spherical shaped balls of solder where the spherical shaped balls push out the flux. The vias620(a-n) positioned in the thermal pad660that extend down through PCB640and onto the bottom surface of the PCB640may enable the flux that accumulates to be blown out of the bottom surface of the PCB640such that the flux is purged out of the bottom surface of the PCB640. Even after the flux begins to cool and transitions from the gas state to a liquid state, the liquid flux may continue to run out of the bottom surface of the PCB640from the vias620(a-n) such that any flux residue is removed from between the thermal pad660and the PCB640as well as from between the lands610(a-n).

The wetting process of soldering may take an activated solderable surface such as but not limited to copper, tin, and/or gold such that the solder may crawl along the activated solderable surface due to the wetted solder is attracted to the metals included in the activated solderable surface. The solder itself may push the liquid flux down through the vias620(a-n) and out of the bottom surface of the PCB640. Any remaining flux that is present on the bottom surface of the PCB640may then be exposed to heat during the reflow process and may be dried such that the remaining dried flux residue positioned on the bottom surface of the PCB640may have little risk of transitioning into dendritic growth and/or corrosion and thus providing an increased opportunity of current leakage thereby unnecessarily draining the battery life of the battery source of the system that the BTC package is associated. Thus, the vias620(a-n) may allow flux to purge out of the bottom surface of the PCB640such that the flux is removed from between the thermal pad660and the PCB640as well as from the between the lands610(a-n).

In an embodiment, the quantity of vias620(a-n) as well as the diameter of each of the vias620(a-n) may be selected such that an excess volume of flux that is generated from the solder that is applied to the BTC package configuration600is prevented from purging through the vias620(a-n). In doing so, a solder bond with an adequate thickness may be generated to attach the BTC630to the PCB640while maintaining adequate spacing between the BTC630and the PCB640via the solder bond to allow flux to be flushed out from between the BTC630and the PCB640.

As mentioned above, the vias620(a-n) enable the flux to be pulled through the vias620(a-n) and purged out through the bottom surface of the PCB640. However, purging the flux at an increased volume may result in the BTC630being pulled so close to the PCB640that the spacing between the BTC630and the PCB640is insufficient for the flux to be flushed out from between the BTC630and the PCB640. Further, having a quantity of vias620(a-n) as well as the diameter of each of the vias620(a-n) that may result in an insufficient amount of flux that is generated from the solder that is applied to the BTC package600that is removed from the between the BTC630and the PCB640as well as from between the lands610(a-n). In doing so, significant flux residue may remain thereby increasing the risk of transitioning into dendritic growth and/or corrosion and thus providing an increased opportunity of current leakage thereby unnecessarily draining the battery life of the battery source of the system that the BTC package is associated.

Further, having a diameter of each of the vias620(a-n) that requires an increased quantity of vias620(a-n) to be added to the thermal pad660in order to adequately purge the flux through the vias620(a-n) to remove the flux from between the BTC630and the PCB640as well as from between the lands610(a-n) may unnecessarily increase the drill wear of the BTC package configuration600as well as unnecessarily increase the drill time to manufacturing the BTC package configuration600as well as increasing the drill wear-out of the BTC package configuration600thereby decreasing the yield of the BTC package configuration600and increasing the cost.

Thus, an optimal quantity of vias620(a-n) included in the thermal pad660with each via620(a-n) having an optimal diameter may enable an adequate amount of flux to be purged through the vias620(a-n) to remove the flux from between the BTC630and the PCB640and from between the lands610(a-n). However, the optimal quantity of vias620(a-n) with each via620(a-n) having an optimal diameter may also prevent the excess volume of flux from being purged through the vias620(a-n) that reduces the spacing between the BTC630and the PCB640thereby preventing the flux from being flushed out between the BTC630and the PCB640.

In an embodiment, a thickness of the solder bond to adequately electrically connect the BCT630to the PCB640while maintaining adequate spacing between the BTC630and the PCB640to enable flux to be sufficiently flushed out between the BTC630and the PCB640is between 25 and 75 microns. In an embodiment, the quantity of vias620(a-n) as well as the diameter of the vias620(a-n) may be selected such that an average of 1.39 vias per square millimeter be positioned on the thermal pad660to enable flux to be sufficiently purged from the vias620(a-n) while maintaining the spacing between the BTC630and the PCB640to enable flux to be sufficiently flushed out between the BTC630and the PCB640. In an embodiment, the average of vias per square millimeter positioned on the thermal pad660may be selected from range of 1.38 vias per square millimeter to 1.43 vias per square millimeter. In an embodiment, the diameter of the vias620(a-n) may be selected such that each diameter is 200 microns to enable flux to be sufficiently purged from the vias620(a-n) while maintaining the spacing between the BTC630and the PCB640to enable flux to be sufficiently flushed out between the BTC630and the PCB640. In another embodiment, the diameter of the vias620(a-n) may be selected from a range of diameters that range from 180 microns to 250 microns.

In an embodiment, the BTC630is mounted to the PCB640and is electrically connected to the BTC630via the lands610(a-n) and receives the heat transfer from the BTC630via the thermal pad660and includes at least one reservoir680(a-n), where n is an integer equal to or greater than one. The reservoirs680(a-n) may pull flux positioned between the lands610(a-n) into the reservoirs680(a-n) as the flux is generated from the solder applied to the BTC package configuration600as the BTC630is mounted to the PCB640. The reservoirs680(a-n) may be openings in the solder mask690that is applied to the BTC package configuration600such that the reservoirs may pull the flux positioned between the lands610(a-n) into the opening in the solder mask690that is associated with the reservoirs680(a-n) as the flux transitions into a liquid.

Each of the reservoirs680(a-n) may be shaped as an elliptical pattern in the opening of the solder mask690such that the reservoirs pull the flux positioned between the lands610(a-n) into the elliptical pattern in the opening of the solder mask690as the flux transforms into a spherical shape based on a capillary action as the flux transitions into the liquid. The elliptical pattern is a pattern that is a curved shape in in the opening of the solder mask690. As reservoirs680(a-n) widen into the elliptical pattern and extend from the BTC630, a capillary action occurs and the flux transitions into the gas state and begins to blow out each of the corners of the BTC630as well as in between the lands610(a-n). As the flux transitions back from the gas state into the liquid state, the flux pulls up into the elliptical shaped reservoirs680(a-n). In doing so, the flux is pulled from between the lands610(a-n) into each of the elliptical shaped reservoirs680(a-n) positioned at each of the four corners of the BTC630.

Once the flux is pulled into the reservoirs680(a-n), the flux is exposed to heat and evaporates and any flux residue that remains may be dried such that the flux residue does not have a risk of transitioning into dendritic growth and/or corrosion and thus providing an increased opportunity of current leakage thereby unnecessarily draining the battery life of the battery source of the system that the BTC package is associated. Further, each of the reservoirs680(a-n) shaped as the elliptical pattern may be positioned between a ground land and a power land to prevent current leakage between the current land and the ground land. Any flux residue that is trapped between a power land and a ground land may result in an ideal path to have dendrites and/or corrosion grow resulting in an increased risk of current leakage. Thus, the positioning of the reservoirs680(a-n) between the current land and the ground land may decrease the risk of current leakage.

In an embodiment, each of the lands610(a-n) include a peripheral terminal615(a-n) that is electrically connected to a corresponding terminal (not shown) associated with the BTC630and a trace625(a-n) that extends from the corresponding peripheral terminal615(a-n). The trace625(a-n) also extends beyond a solder mask690that is applied to the BTC package configuration600. Each trace625(a-n) includes a width that is less than a width of each corresponding peripheral terminal and may prevent the BTC630from tilting as the BTC630is mounted to the PCB640.

Each of the peripheral terminals615(a-n) may have a substantially similar surface area and each of the traces625(a-n) that extend from the corresponding peripheral terminals615(a-n) may also have a substantially similar surface area. The solder deposits that are positioned between each land610(a-n) and each corresponding terminal of the BTC630may also include a substantially equal volume of solder. Since each of the peripheral terminals615(a-n) have substantially similar surface areas and each of the traces625(a-n) have substantially similar surface areas and the solder deposits have substantially equal volumes of solder, the solder deposits of substantially equal volumes may conform to the substantially similar surface area of each corresponding peripheral terminal615(a-n) and the substantially similar surface area of each corresponding trace625(a-n).

Each of the solder deposits of substantially equal volume that are positioned between each corresponding land610(a-n) and each corresponding terminal of the BTC630may ensure that the BTC630is mounted to the PCB640such that the BTC630is substantially planar relative to the PCB640. In doing so, the substantially equal volume of each solder deposit conforms to the substantially similar surface area of each corresponding peripheral terminal615(a-n) and each corresponding trace625(a-n) thereby pulling the BTC630to be substantially planar to the PCB640when mounted to the PCB640.

Often times different conventional devices require that only a portion of conventional lands have solder deposits positioned between the portion of conventional lands and corresponding terminals of the conventional device. However, if the remaining conventional lands that do not require being soldered to the corresponding terminals are indeed not connected via solder deposits of substantially equal volume, then the conventional device may tilt such that the conventional device is not planar to the conventional PCB when mounted to the conventional PCB. The conventional device that is tilted may have open solder joints along the portion of the conventional device that has tilted up such a distance from the surface of the PCB that the solder joints are unable to electrically connect the conventional lands with the corresponding terminals of the conventional device.

Further, the conventional device that is tilted may have short circuits and/or near short circuits between the conventional lands and the corresponding terminals of the conventional device that are positioned on the conventional device that has pivoted due to the tilt of the conventional device such that the conventional lands and the corresponding terminals are directly touching due to the solder joints being crushed among the pivot thereby causing a short circuit and/or near short circuit. Thus, the positioning of solder deposits of substantially equal volume between each peripheral terminal615(a-n) and each trace625(a-n) of substantially surface area and each corresponding terminal of the BTC630may ensure that the BTC630is mounted to the PCB640in a substantially planar manner.

In an embodiment, the traces625(a-n) provide a route from each of the corresponding peripheral terminals615(a-n) with each of the traces625(a-n) having a surface area that is less than the peripheral terminals625(a-n). The traces625(a-n) extend outward from the BTC630in a fan-out pattern and is defined by the solder mask690where each of the traces625(a-n) terminate in the solderable area of each land610(a-n) out on the corresponding traces625(a-n). The terminals molded on the bottom surface of the BTC630may have a substantially similar shape and surface area as each corresponding peripheral terminal625(a-n).

FIG. 7illustrates a top-elevational view of an example BTC package configuration700that depicts an example of the lands that have the trace and the peripheral terminal configuration. As shown inFIG. 7each of the lands610(a-n) include the corresponding peripheral terminal615(a-n) and the corresponding trace625(a-n). Example dimensions of the peripheral terminals615(a-n) include the dimensions of 0.3 mm and 0.5 mm. In an embodiment, the dimensions of the peripheral terminals615(a-n) may be in a 1×1 relationship with the BTC package configuration700such that each of the peripheral terminals615(a-n) have substantially similar surface areas relative to the BTC package configuration700. Example dimensions of the traces625(a-n) extend 0.2 mm and fan out from the BTC630. In such an example, the 0.2 mm may be sufficiently long for the traces625(a-n) to extend beyond the solder mask690while not extending a significantly increased distance from the solder mask690such that the traces625(a-n) may be sawn and remain unplated resulting in an unformed solder ball that fails to join anything together.

In an embodiment, lands610(a-n) may be rounded as opposed to be rectangular lands. Solder stencils with rectangular apertures correspond to square corners of the rectangular lands. However, using square or rectangular corners in stencils may not be best practice for printing as sharp corners tend to collect solder deposits as compared to stencils that have rounded corners. Further, solder does not naturally form square and/or rectangular joints and may coalesce into the solder joint leaving thin and/or uncoated areas at the sharp land corners.

In an embodiment, VIPPO thermal vias may be avoided to avoid air being trapped between the via and the solder mask resulting in a divot at the surface of the via and the BTC. Solder strips electrically connecting the vias to the solder mask may also be avoided to avoid defined voids from forming. In an embodiment, a no-clean solder process that mitigates flux residues while obtaining low thermal voiding and adequate solder joints may be obtained by determining the quantity and size of the vias, incorporating encroached vias on the non-device side, incorporating reservoirs, incorporating uniform land size for peripheral terminals, incorporating rounded D-lands with trace fan-outs, incorporating gang solder mask relief, incorporating 75 microns form joint toe area, eliminating conductor traces from terminals to thermal lands, incorporating a 125 micron thick stencil with polished nanocoated apertures, and incorporating 90% paste area on the thermal paddle land and 50% paste area on the peripheral lands.

FIG. 8is a block diagram of another exemplary BTC package configuration800and provides a three-dimensional view of the exemplary BTC package configuration600depicted inFIG. 6according to an exemplary embodiment of the present disclosure. Specifically,FIG. 8depicts a three-dimensional view of the BTC package630after the BTC package630has been mounted to the PCB. A plurality of terminals820(a-n), where n is an integer equal to or greater than one, is positioned on a bottom surface840of the BTC package630and are positioned under the BTC package630. Each of the lands610(a-n) is electrically connected to each of the corresponding terminals820(a-n) such that each of the peripheral terminals615(a-n) are mounted to each of the corresponding terminals820(a-n) and then each of the traces625(a-n) extend outward from the BTC package630in a fan-out configuration.

FIG. 9is a block diagram of another exemplary BTC package configuration900and provides a three-dimensional view of the exemplary BTC package configuration600depicted inFIG. 6according to an exemplary embodiment of the present disclosure. Specifically,FIG. 9depicts a three-dimensional view of the BTC package630after the BTC package630has been mounted to the PCB640. A plurality of terminals820(a-n), where n is an integer equal to or greater than one, is positioned on a bottom surface840of the BTC package630and are positioned under the BTC package630. Each of the lands610(a-n) is electrically connected to each of the corresponding terminals820(a-n) such that each of the peripheral terminals615(a-n) are mounted to each of the corresponding terminals820(a-n) and then each of the traces625(a-n) extend outward from the BTC package630in a fan-out configuration.

Further, a plurality of openings960(a-n) is positioned on the bottom surface950of the PCB640. The bottom surface840of the BTC package630may be mounted to the top surface of the PCB640and the bottom surface950of the PCB640may include the openings960(a-n). Each of the openings960(a-n) may be coupled to each of the vias620(a-n) such that as the flux is purged through the vias620(a-n) from between the BTC package630and the PCB640as well as from between the lands610(a-n), the flux is pushed out of the vias620(a-n) and through the PCB640and out from the bottom surface of the950of the PCB640via the openings960(a-n). Any remaining flux residue that is present at the openings960(a-n) may be baked and hardened such that the remaining flux residue has no negative impact on the BTC package configuration900.

FIG. 10is a block diagram of an exemplary access device configuration1000that incorporates the BTC package configurations discussed in detail above. For example, the access device configuration1000may incorporate the BTC package configuration600into the BTC package configuration1020which operates as the controller for the access control device. In doing so the, BTC package configuration1020as operating as the controller of the access control device1010may control one or more components of the access control device1010as the access control device1010operates. For example, the access control device1010may be a locking system and the BTC package configuration1020may determine when the door latch of the locking mechanism included in the access control device1010is to extend when the access control device1010is to be locked and when the door latch is to retract when the access control device1010is to be unlocked.

The access control device1010that the BTC package configuration1020may act as the controller for may include but is not limited to door closers, door operators, auto-operators, credential readers, hotspot readers, electronic locks including mortise, cylindrical, and/or tabular locks, exit devices, panic bars, wireless reader interfaces, gateway devices, plug-in devices, peripheral devices, doorbell camera systems, access control surveillance systems and/or any other type of access control device that regulates access to a space that will be apparent to those skilled in the relevant art(s) without departing from the spirit and scope of the disclosure.

The BTC package configuration1020when operating as the controller for the access control device1010may control one or more components of the access control device1010as the access control device1010operates such as but not limited to, extending/retracting a door latch, engaging/disengaging a dogging mechanism on an exit device, opening/closing a door via a door closer/operator, moving a primer mover, controlling an electric motor, and/or any other type of action that enables the access control device1010to regulate access to a space that will be apparent to those skilled in the relevant art(s) without departing from the spirit and scope of the disclosure.

The BTC package configuration1020when operating as the controller for the access control device1010may receive data from the access control device1010as well any type of component included in the access control device1010that may provide data to the BTC configuration1020for the BTC package configuration1020to adequately instruct the access control device1010as to how to operate to adequately regulate access to the space.

For example, sensors included in a locking mechanism may send data to the BTC package configuration1020indicating that a person has departed from the door after the door closed behind the person. The BTC package configuration1020may then instruct the door latch to extend thereby locking the door. The BTC package configuration1020may receive data from any type of component included in the access control device1010that includes but is not limited to sensors, credential readers, biometric sensing devices, user interface devices, and/or any other component that may provide data to the BTC package configuration1020to adequately instruct the access control device1010to execute actions to regulate access to the space that will be apparent to those skilled in the relevant art(s) without departing from the spirit and scope of the disclosure.

The BTC package configuration1020may communicate to with the access control device1010via wire-line communication and/or wireless communication. The BTC package configuration1020may engage in wireless communication with the access control device1300that includes but is not limited to Bluetooth, BLE, Wi-Fi, and/or any other wireless communication protocol that will be apparent to those skilled in the relevant art(s) without departing from the spirit and scope of the disclosure.

CONCLUSION