Full CMOS SRAM

A full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) may have a reduced cell size by arranging a word line of a pair of transistors arranged on the uppermost layer of the SRAM. First and second transistors may be arranged on first and second active regions. Third and fourth transistors may be arranged on first and second semiconductor layers formed over the first and second active regions. Fifth and sixth transistors may be arranged on the third and fourth semiconductor layers over the first and second semiconductor layers. A word line may be arranged in a straight line between the first and second gates of the first and second transistors and between the third and fourth gates of the third and fourth transistors.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2009-0007386, filed on Jan. 30, 2009, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

1. Field of the Invention

The inventive concept relates to a semiconductor memory device, and more particularly, to a full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) device having a layout in which the cell size can be readily reduced

2. Description of the Related Art

Of the semiconductor memory devices, SRAMs have characteristics such as low power consumption and fast response time when compared to dynamic random access memories (DRAMs), and are widely used in cache memory devices or mobile electronic products. Unit memory cells of an SRAM are classified as SRAM cells that use high value resistors as load devices and CMOS SRAM cells that use PMOS transistors as load devices. Also, the unit memory cells of the SRAM are classified as thin film transistor SRAM cells that use thin film transistors as load devices and bulk CMOS SRAM cells that use bulk transistors as load devices.

A bulk CMOS SRAM cell includes a pair of driving transistors, a pair of load transistors, and a pair of transmission transistors. The pair of driving transistors and the pair of transmission transistors are NMOS transistors and the pair of load transistors includes PMOS transistors. The bulk CMOS SRAM cell has high cell stability, but it has a low degree of integration and poor latch-up immunity due to a large cell size, since source and drain regions of the six transistors and channel regions of the six transistors are arranged in a plane on a substrate.

In a stack-type SRAM, the three pairs of transistors are stacked on layers different from each other to increase integration. In the stack-type SRAM, word lines, which are arranged on the uppermost layer and are connected to transistors, are arranged in a zigzag shape having a slant line, and thus, there is a limit to an ability to reduce cell size. Also, due to the slant line of the word lines, an align margin between neighboring bit line contact nodes is narrow and the current distribution of the transistors is not uniform. The align margin between the word lines and the bit line contact nodes is further reduced with the increase in integration. Accordingly, it is further difficult to perform a photographic process with respect to the word lines, and thus, the cell size cannot be readily reduced.

SUMMARY

The present general inventive concept provides a full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) in which the cell size can be readily reduced by improving an align margin between a word line and bit line contact nodes through arranging the word line in a straight line.

According to an aspect of the inventive concept, there is provided a full CMOS SRAM. The full CMOS SRAM may include a semiconductor substrate having a plurality of cell regions arranged in an array form in first direction and second direction perpendicular to the first direction, and a plurality of memory cells arranged in each of the cell regions. Each of the memory cells may include a pair of first transistors arranged on the semiconductor substrate, a pair of second transistors arranged on a first layer over the semiconductor substrate, and a pair of third transistors arranged over the first layer. A word line that includes gates of the pair of third transistors may be arranged in a straight line in the first direction. A pair of bit lines may be arranged to cross the word line in the second direction. The word line may be extended in a straight line in the first direction across cell regions which are arranged in the first direction. The word line may be arranged parallel to the word lines arranged in the cell regions neighboring in a second direction which crosses the first direction.

Additional features and/or utilities of the present general inventive concept may be realized by a full CMOS SRAM. The full CMOS SRAM may include a semiconductor substrate having a first active region and a second active region which are arranged apart from each other and both extend in a first direction. A first transistor may be arranged in the first active region and may include a first gate, a first source region, and a first drain region. A second transistor may be arranged in the second active region and may include a second gate, a second source region, and a second drain region. A third transistor may be arranged in a first layer on the semiconductor substrate and may include a third gate, a third source region, and a third drain region. A fourth transistor may be arranged in the first layer and may include a fourth gate, a fourth source region, and a fourth drain region. A fifth transistor may be arranged in a second layer over the first layer and may include a fifth gate, a fifth source region, and a fifth drain region. A sixth transistor may be arranged on the second layer and may include a sixth gate, a sixth source region, and a sixth drain region. A word line may be arranged in a straight line over the second layer in a second direction crossing the first direction between the first gate and the second gate and between the third gate and the fourth gate.

The first drain region, the third drain region, and the fifth source region may be electrically connected to each other through a first contact node. The second drain region, the fourth drain region, and the sixth source region may be electrically connected to each other through a second contact node. The word line may be arranged in a straight line in the second direction between the first contact node and the second contact node.

The first layer may include first and second semiconductor layers arranged over the semiconductor substrate to overlap the first and second active regions. The second layer may include third and fourth semiconductor layers that are arranged over the first and second semiconductor layers to overlap the first and second active regions and the first and second semiconductor layers.

The fifth gate may include a first portion of the word line that overlaps the third semiconductor layer, and the sixth gate may include a second portion of the word line that overlaps the fourth semiconductor layer. The first and second gates may cross the first and second active regions in the second direction, and the third and fourth gates may cross the first and second semiconductor layers in the second direction. The first and second gates may overlap the third and fourth gates.

Additional features and/or utilities of the present general inventive concept may be realized by a CMOS SRAM device including at least one cell. The cell may include a first layer including a first transistor and a second transistor, a second layer above the first layer including a third transistor and a fourth transistor, and a third layer including a fifth transistor and a sixth transistor. Each transistor of the first through sixth transistors may include a source and a drain, each extending in a first direction, and a gate extending in a second direction to cross the first direction, and a gate of the fifth transistor may be connected to and linearly contiguous with a gate of the sixth transistor.

A source of the third and fourth transistors may be connected to a first voltage source and a source of the first and second transistors may be connected to a second voltage source. The second voltage source is a ground source.

The CMOS SRAM device may include a first electrical node and a second electrical node. The first electrical node may be connected to a drain of the first and third transistors, a source of the fifth transistor, and a gate of the second and fourth transistors. The second electrical node may be connected to a drain of the second and fourth transistors, a source of the sixth transistor, and a gate of the first and third transistors. Each node may include a conductive plug.

The gates of the first through fourth transistors, respectively, may include a main portion extending in a first direction and an offset portion extending in the first direction and offset from the main portion by a predetermined distance in a second direction perpendicular to the first direction. The main portions of the first through fourth transistors may be connected to the sources and drains of the respective first through fourth transistors, and the offset portions of the gates of the first through fourth transistors may be connected to the respective nodes.

The first layer may include a substrate and a first sub-layer above the substrate. The sources and drains of the first and second transistors may be located in the substrate, may be separated from each other, and may be substantially parallel to each other. The gates of the first and second transistors may extend parallel to each other in the first sub-layer.

The second layer may include a first semiconductor layer and a second sub-layer above the first semiconductor layer. The sources and drains of the third and fourth transistors may be located in the first semiconductor layer, may be separated from each other, and may be substantially parallel to each other. The gates of the third and fourth transistors may extend parallel to each other in the second sub-layer.

The third layer may include a second semiconductor layer and a third sub-layer above the second semiconductor layer. The sources and drains of the fifth and sixth transistors may be located in the second semiconductor layer, may be separated from each other, and may be substantially parallel to each other. A word line may extend across the first cell in a line between the gates of the first through fourth transistors and may include a gate of the fifth transistor and a gate of the sixth transistor.

The CMOS SRAM device may further include a plurality of bit lines extending in lines parallel to each other and crossing the word line, a first bit line of the plurality of bit lines connected to a drain of the fifth transistor and a second bit line of the plurality of bit lines connected to a drain of the sixth transistor.

The source and drain of the first transistor may be located in a main portion of a first active region of the substrate, the source and drain of the second transistor may be located in a main portion of a second active region of the substrate, the main portions of the first and second active regions of the substrate may extend parallel to each other, and each of the first and second active regions of the substrate may include protrusions located at an end of the main portion and extending perpendicular to the main portion.

The source and drain of the third transistor may be located in a first main portion of the first semiconductor layer, the source and drain of the fourth transistor may be located in a second main portion of the first semiconductor layer, and the first and second main portions of the first semiconductor layer may extend parallel to each other. The first semiconductor layer may further include a first protrusion connected to an end of the first main portion of the first semiconductor layer and extending perpendicular to the first main portion and a second protrusion connected to an end of the second main portion of the first semiconductor layer and extending perpendicular to the second main portion.

The source and drain of the fifth transistor may be located in a first main portion of the second semiconductor layer, the source and drain of the sixth transistor may be located in a second main portion of the second semiconductor layer, and the first and second main portions of the second semiconductor layer may extend parallel to each other. The second semiconductor layer may further include a first protrusion connected to an end of the first main portion of the second semiconductor layer and extending perpendicular to the first main portion, and a second protrusion connected to an end of the second main portion of the second semiconductor layer and extending perpendicular to the second main portion.

The first and second main portions of the second semiconductor layer may extend in a first direction, the first and second protrusions may extend in a second direction perpendicular to the first direction, and the sources of the first, third, and fifth transistors may be stacked one above the other in a third direction perpendicular to both the first and second directions. The drains of the second, second, fourth, and sixth transistors may be stacked one above the other in the third direction, the gates of the first and third transistors may be stacked one above the other in the third direction, and the gates of the second and fourth transistors may be stacked one above the other in the third direction.

The gates of the first through sixth transistors may include at least one of a single layer formed of polysilicon, a stack of polysilicon film layers, a metal layer, and a metal silicide layer.

The CMOS SRAM device may include a plurality of cells arranged in an array, and

a structure of one cell may mirror a structure of an adjacent cell.

Additional features and/or utilities of the present general inventive concept may be realized by a computing device including a CMOS SRAM device, the computing device including at least one cell and a controller. The cell may include a first layer including a first transistor and a second transistor, a second layer above the first layer including a third transistor and a fourth transistor, and a third layer including a fifth transistor and a sixth transistor. Each transistor of the first through sixth transistors may include a source and a drain, each extending in a first direction, and a gate extending in a second direction to cross the first direction. A gate of the fifth transistor may be connected to and linearly contiguous with a gate of the sixth transistor. The controller may control an on/off state of each of the first through sixth transistors.

The at least one cell may include a first electrical node and a second electrical node, and the controller may read data from the at least one cell by detecting a state of at least one of the first and second electrical nodes.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1is an equivalent circuit of a full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) according to an embodiment of the inventive concept. The full CMOS SRAM may include unit SRAM cells or a cell array in which unit SRAM cells are arranged in an array form.

Referring toFIG. 1, the full CMOS SRAM may include a pair of bit lines BL and/BL, a word line WL, and six transistors, for example, a pair of transmission transistors PG1and PG2, a pair of load transistors PU1and PU2, and a pair of driving transistors PD1and PD2. The first and second load transistors PU1and PU2may be PMOS transistors, and the first and second transmission transistors PG1and PG2and the first and second driving transistors PD1and PD2may be NMOS transistors.

Gates G(PG1) and G(PG2) of the first and second transmission transistors PG1and PG2may be connected to the word line WL, and drains D(PG1) and D(PG2) of the first and second transmission transistors PG1and PG2may be respectively connected to the pair of bit lines BL and/BL. Sources S(PU1) and S(PU2) of the first and second load transistors PU1and PU2may be connected to a first power source line Vdd, and sources S(PD1) and S(PD2) of the first and second driving transistors PD1and PD2may be connected to a second power supply source line GND. The first power source line Vdd may include a power line and the second power source line GND may include a ground line.

A source S(PG1) of the first transmission transistor PG1, a drain D(PU1) of the first load transistor PU1, and a drain D(PD1) of the first driving transistor PD1may be commonly connected to a first contact node N1. A source S(PG2) of the second transmission transistor PG2, a drain D(PU2) of the second load transistor PU2, and a drain D(PD2) of the second driving transistor PD2may be commonly connected to a second contact node N2. A gate G(PU1) of the first load transistor PU1and a gate G(PD1) of the first driving transistor PD1may be commonly connected to the second contact node N2to constitute a first latch formed of a first CMOS inverter. A gate G(PU2) of the second load transistor PU2and a gate G(PD2) of the second driving transistor PD2may be commonly connected to the first contact node N1to constitute a first latch formed of a second CMOS inverter.

When the first contact node N1is in a high level, the second load transistor PU2is turned off and the second driving transistor PD2is turned on, and thus, the second contact node N2transitions to a low level. As the second contact node N2is in a low level, the first load transistor PU1is turned on and the first driving transistor PD1is turned off, and thus, the first contact node N1maintains its high level.

When the second contact node N2is in a high level, the first load transistor PU1is turned off and the first driving transistor PD1is turned on, and thus, the first contact node N1transitions to a low level. As the first contact node N1is in a low level, the second load transistor PU2is turned on and the second driving transistor PD2is turned off, and thus, the second contact node N2maintains its high level.

Therefore, when the first and second transmission transistors PG1and PG2are turned on based on a gate driving signal being applied to the word line WL, a data signal supplied to the first and second bit lines BL and/BL can be latched to the first and second contact nodes N1and N2through the first and second transmission transistors PG1and PG2. Meanwhile, the data signal latched to the first and second contact nodes N1and N2is provided to the first and second bit lines BL and/BL through the first and second transmission transistors PG1and PG2when the first and second transmission transistors PG1and PG2are turned on. Thus, the data latched to the first and second contact nodes N1and N2may be read by sensing the data signals provided to the first and second bit lines BL and/BL through a sensing amplifier (not shown).

FIGS. 2A through 2Jare plan views to illustrate a method of manufacturing the full CMOS SRAM ofFIG. 1, according to an embodiment of the inventive concept.FIGS. 3A through 3Gare cross-sectional views taken along lines A-A′ ofFIGS. 2A through 2G, as viewed from a direction D1to illustrate a method of manufacturing a full CMOS SRAM.FIG. 3His a cross-sectional view taken along line B-B′ and C-C′ ofFIG. 2H.FIG. 3Iis a cross-sectional view taken along lines A-A′ and G-G′ ofFIG. 2Ito illustrate a method of manufacturing a full CMOS SRAM.FIG. 3Jis a cross-sectional view taken along lines A-A′ and H-H′ ofFIG. 2J.

Referring toFIGS. 1,2A,2B,3A, and3B, a semiconductor substrate100may include a plurality of cell regions101where SRAM cells may be arranged respectively. The cell regions101, for example, 2×2 cell regions, may be arranged in an array in a first direction (an X direction) and a second direction (a Y direction) perpendicular to the first direction. In each of the cell regions101on the semiconductor substrate100, a first active region120aand a second active region120bare located in the substrate, and extend substantially linearly in the second direction. The first and second active regions120a,120bare separated from each other in the first direction. The first and second active regions120aand120bmay include active regions of the first and second driving transistors PD1and PD2. The first and second active regions120aand120bare mirrored in cell regions101neighboring in the first direction and/or the second direction. The cell regions101may also include non-active regions110.

The first active region120amay include a first protrusion120cthat protrudes in the first direction. The first protrusion120cmay be arranged over an interface of two neighboring cell regions101in the second direction. In other words, as shown inFIG. 2A, a first protrusion120cof a first active region120aof a cell may be adjacent to, in direct contact with, or formed integrally with a first protrusion120cof a first active region120aof an adjacent cell. The second active region120bmay include a second protrusion120dthat protrudes in the first direction. The second protrusion120dmay be arranged over an interface of two neighboring cell regions101in the first direction.

Next, the first and second driving transistors PD1and PD2may be formed on the semiconductor substrate100. A first gate130a(G(PD1) ofFIG. 1) of the first driving transistor PD1may be arranged on the semiconductor substrate100to cross the first active region120a, and a second gate130b(G(PD2) ofFIG. 1) may be arranged on the semiconductor substrate100to cross the second active region120a.

The first and second gates130aand130bmay be mirrored in the neighboring cell regions101in the first direction and/or the second direction. Each of the first and second gates130aand130bmay include a gate insulating film131arranged on the semiconductor substrate100, a gate electrode material132arranged on the gate insulating film131, and gate spacers133arranged on both sides of the gate electrode material132. The gate electrode material132may include a single layer formed of polysilicon or a stack layer of a polysilicon film, a metal layer, and/or a metal silicide layer.

A first source region141aand a first drain region145amay be formed on both sides of the first gate130ain the first active region120a, and a second source region141band a second drain region145bmay be formed on both sides of the second gate130bin the second active region120b. A first intermediate region146amay be located beneath the gate130abetween the first source region141aand the first drain region145a, and a second intermediate region146bmay be located beneath the second gate130bbetween the second source region141band the second drain region145b. The intermediate region may be an un-doped region, for example.

When the first and second source regions141aand141band the first and second drain regions145aand145bare formed, a first connection region141cextending from the first source region141amay be formed on the first protrusion unit120c, and a second connection region141dextending from the second source region141bmay be formed on the second protrusion unit120d. The first and second connection regions141cand141d, the first and second source regions141aand141b, and the first and second drain regions145aand145bmay be formed by implanting a highly concentrated N+ type dopant using a blanket ion injection process.

Referring toFIGS. 1,2C and3C, a first insulating film150may be formed on the semiconductor substrate100on which the first and second driving transistors PD1and PD2are arranged. The first insulating film150may include an interlayer insulating film. First and second contact holes150aand150bmay be formed in the first insulating film150by etching the first insulating film150. First and second contact plugs151aand151bmay be formed in the first and second contact holes150aand150b. The first and second contact plugs151aand151bmay be metal plugs or silicon plugs.

The first contact hole150amay expose a portion of the first drain region145aof the first driving transistor PD1and a portion of the second gate130bof the second driving transistor PD2. The second contact hole150bmay expose a portion of the second drain region145bof the second driving transistor PD2and a portion of the first gate130aof the first driving transistor PD1. Side walls of the gate electrode material132may be exposed due to etching of the gate spacers133on side walls of the first and second gates130aand130bduring the etching process.

Referring toFIGS. 1,2D,2E,3D, and3E, first and second semiconductor layers160aand160bmay be formed on the first insulating film150. The first and second semiconductor layers160aand160bmay include active layers of the first and second load transistors PU1and PU2. The first and second semiconductor layers160aand160bmay include a silicon layer. The first and second semiconductor layers160a,160bmay be located directly above the active regions120a,120bof the substrate in the second direction. The first and second semiconductor layers160aand160bmay respectively include third and fourth protrusions160cand160dthat may protrude in the first direction.

The first and second semiconductor layers160aand160bmay be arranged to overlap the first and second active regions120aand120band to cross the first and second gates130aand130b. The third and fourth protrusions160cand160dmay be arranged in a direction opposite to the first and second protrusions120cand120d. The third and fourth protrusions160cand160dmay be arranged in the second direction on an interface between two neighboring cell regions101. The first and second semiconductor layers160aand160bmay be mirrored in the neighboring cell regions101in the first direction and/or the second direction.

Next, the first load transistor PU1may be formed on the first semiconductor layer160a, and the second load transistor PU2may be formed on the second semiconductor layer160b. A third gate170aoverlapping the first gate130amay be arranged on the first insulating film150to cross the first semiconductor layer160ain the first direction. A fourth gate170boverlapping the second gate130bmay be arranged on the first insulating film150in the first direction. The third and fourth gates170aand170bmay be mirrored in the cell regions101neighboring in the first direction and/or the second direction

Each of the third and fourth gates170aand170bmay include a gate insulating film131formed on the first and second semiconductor layers160aand160b, a gate electrode material132formed on the gate insulating film131, and gate spacers133arranged on both sides of the gate electrode material132. The gate electrode132may include a single layer formed of polysilicon or a stack layer of a polysilicon film, a metal layer, and/or a metal silicide layer.

A third source region181aand a third drain region185aof the first load transistor PU1may be formed in the first semiconductor layer160aon both sides of the third gate170a. A fourth source region181band a fourth drain region185bof the second load transistor PU2may be formed in the second semiconductor layer160bon both sides of the fourth gate170b. The third and fourth source and drain regions181a,181b,185a,185bmay be formed in the semiconductor layers160a,160beither before or after the gates170a,170bor formed on the semiconductor layers160a,160b. The third drain region185aof the first load transistor PU1may be electrically connected to the first drain region145aof the first driving transistor PD1through the first contact plug151a. The fourth drain region185bof the second load transistor PU2may be electrically connected to the second drain region145bof the second driving transistor PD2through the second contact plug151b. Portions of the first and second semiconductor layers160aand160bbetween the third and fourth source regions181aand181band the third and fourth drain regions185aand185bmay function as channel regions of the first and second load transistors PU1and PU2.

When the third and fourth source regions181aand181band the third and fourth drain regions185aand185bare formed, a third connection region181cextending from the third source region181amay be formed on the third protrusion160c, and a fourth connection region181dextending from the fourth source region181bmay be formed on the fourth protrusion160d. The third and fourth connection regions181cand181d, the third and fourth source regions181aand181b, and the third and fourth drain regions185aand185bmay be formed by implanting a highly concentrated P+ type dopant using a blanket ion injection process. When a plurality of cells101are arranged in an array, the third and fourth connection regions181cand181dmay extend toward a center line between two adjacent cells101and may be contiguous with third and fourth connection regions181cand181dof the adjacent cell. The third and fourth connection regions181cand181dmay also be contiguous with respective connection regions of an adjacent cell in a direction perpendicular to the direction in which the connection regions extend. For example, as shown inFIG. 2E, the third connection region181cextends in a first direction X and is contiguous with a corresponding connection region in the adjacent cell in the direction X. However, the third connection region181cis also contiguous with a connection region in the cell adjacent in the direction Y, perpendicular to the direction X.

Referring toFIGS. 1,2F, and3F, a second insulating film152may be formed on the first insulating film150and on the first and second semiconductor layers160aand160b, on which the first and second load transistors PU1and PU2are arranged. The second insulating film152may include an interlayer insulating layer. Third and fourth contact holes152aand152bmay be formed in the second insulating film152by etching the second insulating film152. Third and fourth contact plugs153aand153bmay be formed in the third and fourth contact holes152aand152b. The third and fourth contact plugs153aand153bmay be metal plugs or silicon plugs

The third contact hole152amay expose a portion of the third drain region185aof the first load transistor PU1and a portion of the fourth gate170bof the second load transistor PU2. The fourth contact hole152bmay expose a portion of the fourth drain region185of the second load transistor PU2and a portion of the third gate170aof the first load transistor PU1. Side walls of the gate electrode material172may be exposed due to etching of the gate spacers173on side walls of the third and fourth gates170aand170bduring the etching process.

According to an embodiment of the inventive concept, instead of separately performing the etching process of the first and second insulating films150,152and the forming process of the first through fourth contact plugs151a,151b,153a,153bofFIGS. 3C and 3F, through holes and contact plugs may be formed in a single process. For example, referring toFIG. 3F, after the insulation layers150,152are formed, holes may be formed through the insulation layers150,152to expose portions of the first and second drain regions145aand145band the first and second gates130aand130bof the first and second driving transistors PD1and PD2and portions of the third and fourth drain regions185aand185band the third and fourth gates170aand170bof the first and second load transistors PU1and PU2, and contact plugs may be formed in the through holes.

Referring toFIGS. 1,2G, and3G, third and fourth semiconductor layers190aand190bmay be formed on the second insulating film152. The third and fourth semiconductor layers190aand190bmay include silicon layers. The third and fourth semiconductor layers190aand190bmay include active layers of the first and second transmission transistors PG1and PG2. The third and fourth semiconductor layers190aand190bmay include fifth and sixth protrusions190cand190dprotruding in the first direction. The fifth and sixth protrusions190cand190dmay be arranged in the same direction as the first and fourth protrusion units120cand160drespectively. The fifth and sixth protrusions190cand190dmay be arranged on an interface between two cell regions101neighboring in the second direction. The third and fourth semiconductor layers190aand190bmay be mirrored in the cell regions101neighboring in the first direction X and/or the second direction Y.

Next, the first transmission transistor PG1may be formed on the third semiconductor layer190a, and the second transmission transistor PG2may be formed on the fourth semiconductor layer190b. A word line200crossing the third and fourth semiconductor layers190aand190bis formed on the second insulating film152. The word line200is arranged in a straight line in the first direction between the third and fourth gates170aand170bor between the first and second gates130aand130bso as not to overlap the third and fourth gates170aand170band/or the first and second gates130aand130b.

The word lines200may be arranged in parallel to the word lines200of the cell regions101neighboring in the second direction Y, and may be arranged in a straight line in the first direction across the cell regions101neighboring in the first direction X. A first portion200aof the word line200that overlaps the third semiconductor layer190amay include the fifth gate G(PG1) of the first transmission transistor PG1and a second portion200bof the word line200that overlaps the fourth semiconductor layer190bmay include the sixth gate G(PG2) of the second transmission transistor PG2. The word line200may be mirrored in the cell regions101neighboring in the first direction and/or the second direction.

The word line200may include a gate insulating film131formed on the third and fourth semiconductor layers190aand190b, a gate electrode material132formed on the gate insulating film201, and gate spacers133arranged on both side walls of the gate electrode material202. The gate electrode material202may include a single layer formed of polysilicon or a stack layer of a polysilicon film, a metal layer, and/or a metal silicide layer.

A fifth source region211aand a fifth drain region215aof the first transmission transistor PG1may be arranged in the third semiconductor layer190aon both sides of the fifth gate200a. A sixth source region211band a sixth drain region215bof the second transmission transistor PG2may be arranged in the fourth semiconductor layer190bon both sides of the sixth gate200b. The fifth source region211aof the first transmission transistor PG1may be electrically connected to the first drain region145aof the first driving transistor PD1, the third drain region185aof the first load transistor PU1, the second gate130bof the second driving transistor PD2, and the fourth gate170bof the second load transistor PU2through the first and third contact plugs151aand153a.

The sixth source region211bof the second transmission transistor PG2may be electrically connected to the second drain region145bof the second driving transistor PD2, the fourth drain region185bof the second load transistor PU2, the first gate130aof the first driving transistor PD1, and the third gate170aof the first load transistor PU1through the second and fourth contact plugs151band153b. Portions of the third and fourth semiconductor layers190aand190bbetween the fifth and sixth source regions211aand211band the fifth and sixth drain regions215aand215bmay function as channel regions of the first and second transmission transistors PG1and PG2.

When the fifth and sixth source regions211aand211band the fifth and sixth drain regions215aand215bare formed, a fifth connection region215cextending from the fifth drain region215amay be formed on the fifth protrusion190c, and a sixth connection region215dextending from the sixth drain region215bmay be formed on the sixth protrusion190d. The fifth and sixth connection regions215cand215d, the fifth and sixth source regions211aand211b, and the fifth and sixth drain regions215aand215bmay be formed by implanting a highly concentrated N+ type dopant into them using a blanket ion injection process.

Referring toFIGS. 1,2H, and3H,FIG. 3His a cross-section taken along a plane defined by line B-B′ between an end of the cell and lines E-E′ and F-F′, and taken along a plane defined by line C-C′ between lines E-E′ and F-F′, and as seen from a direction D2. The cell101is so shown to illustrate a geographic relationship between the second power (or ground) lines220and the other elements of the cell101. A third insulating film154may be formed on the second insulating film152and the third and fourth semiconductor layers190aand190bon which the first and second transmission transistors PG1and PG2are formed. The third insulating film154may include an interlayer insulating layer. A fifth contact hole154amay be formed to expose a portion of the first connection region141carranged on the first protrusion unit120c, and a sixth contact hole154bmay be formed to expose a portion of the second connection region141darranged on the second protrusion unit120d. The contact holes154a,154bmay be formed by etching the third insulating film154, for example. The fifth and sixth contact holes154aand154bmay be formed to expose portions of the first and second connection regions141cand141darranged on the four cell regions101neighboring in the first direction and the second direction.

Next, fifth and sixth contact plugs155aand155bmay be formed in the fifth and sixth contact holes154aand154brespectively. The fifth and sixth contact plugs155aand155bmay be silicon plugs or metal plugs. A second power source line220connected to the fifth and sixth contact plugs155aand155bmay be formed. The second power source line220may include a metal line. The second power source line220may be electrically connected to the first and second source regions141aand141bof the first and second driving transistors PD1and PD2in the four cell regions101through the first and second connection regions141cand141darranged on the four neighboring cell regions101.

Referring toFIGS. 1,2I, and3I,FIG. 3Iis a cross-section as seen from a direction D1of the cell as intersected along line G-G′ between an end of the cell and lines E-E′ and F-F′, and along a plane defined by line A-A′ between lines E-E′ and F-F′. The cell101is so shown to illustrate a geographic relationship between the first power line230and the other elements of the cell101. A fourth insulating film156may be formed on the second power source line220and the third insulating film154. The fourth insulating film156may include an interlayer insulating layer. Seventh and eighth contact holes156aand156bmay be formed in the fourth insulating film156by etching the fourth insulating film156. The seventh and eighth contact holes156aand156bmay expose portions of the third and fourth connection regions181cand181dwhich are extended from the third and fourth source regions181aand181bof the first and second load transistors PU1and PU2. The seventh and eighth contact holes156aand156bmay be formed to expose portions of the third and fourth connection regions181cand181darranged on the four cell regions101neighboring in the first direction and the second direction.

Seventh and eighth contact plugs157aand157bmay be formed in the seventh and eighth contact holes156aand156brespectively. The seventh and eighth contact plugs157aand157bmay be silicon plugs or metal plugs. A first power source line230that is electrically connected to the seventh and eighth contact plugs157aand157bmay be formed on the fourth insulating film156. The first power source line230may include a metal line. The first power source line230may be electrically connected to the third and fourth source regions181aand181bof the first and second load transistors PU1and PU2in the four cell regions101through the third and fourth connection regions181cand181darranged in the four neighboring cell regions101.

Referring toFIGS. 1,2J, and3J,FIG. 3Jis a cross-section taken along a plane defined by line H-H′ between an end of the cell and lines E-E′ and F-F′, and taken along a plane defined by line A-A′ between lines E-E′ and F-F′, and as seen from a direction D1. The cell101is so shown to illustrate a geographic relationship between the contact plug159aconnected to the bit line240and the other elements of the cell101. A fifth insulating film158may be formed on the first power source line230and the fourth insulating film156. The fifth insulating film158may include an interlayer insulating layer. Ninth and tenth contact holes158aand158bmay be formed in the fifth insulating film158by etching the fifth insulating film158. The ninth and the tenth contact holes158aand158bmay expose portions of the fifth and sixth connection regions215cand215dwhich are extended from the fifth and sixth drain regions215aand215bof the first and second transmission transistors PG1and PG2. Ninth and tenth contact plugs159aand159bmay be formed in the ninth and tenth contact holes158aand158brespectively. The ninth and tenth contact plugs159aand159bmat be silicon plugs or metal plugs.

First and second bit lines240and245, which are electrically connected to the ninth and tenth contact plugs158aand158b, may be formed on the fifth insulating film158. The first and second bit lines240and245may be metal lines, for example. The first and second bit lines240and245may be electrically connected to the fifth and sixth drain regions215aand215bof the first and second transmission transistors PG1and PG2in each of the cell regions101through the fifth and sixth connection regions215cand215darranged in the cell regions101.

In the full CMOS SRAM according to an embodiment of the inventive concept, SRAM cells arranged in each of the cell regions101may be mirrored in the first direction and the second direction.

FIG. 4illustrates a computing device400including a controller402, an interface404, and a CMOS SRAM device406. The CMOS SRAM device includes one or more cells110illustrated inFIGS. 1-3J. The controller402may receive commands from the interface404to access the CMOS SRAM406. For example, the controller402may read data from or write data to the CMOS device406. The controller402may be a processor, a processor combined with memory, or other hardware capable of accessing the CMOS device406. The interface404may be a user interface or any other type of interface integral with the computing device400. For example, the interface404may be a keypad or keyboard and a display. Alternatively, the interface404may be a port or other connection to connect with an external device to communicate with the external device. The interface404may communicate with an external device via wires, wirelessly, or any other communication means.