MULTI-LAYER TOPOLOGICAL INTERCONNECT WITH PROXIMAL DOPING LAYER

An interconnect structure including conducting layers of topological semi-metals and/or topological insulators. To increase charge carrier density in the conducting layers, a charge carrier doping layer present on at least one surface of the one or more conductive layers of topological semi-metals. The charge carrying doping layers have a charge carrier density greater than the topological semi-metals and/or topological insulators of the one or more conductive layers.

BACKGROUND

The present disclosure relates to interconnects for transmitting electrical signal, and more particularly to methods of reducing resistivity in interconnects.

Interconnects are the wiring schemes in integrated circuits, which may be formed during back-end-of-line (BEOL) processing. Interconnects can distribute clock and other signals, provide power and ground for various electronic system components, and interconnect the transistors within the integrated circuit (IC) chip front-end-of-line (FEOL).

As interconnect dimensions continue to shrink, increases in line resistance degrade transistor device performance. Extendibility of copper (Cu) interconnects is questionable, because copper (Cu) requires thick barrier & adhesion layers, which reduces the copper (Cu) volume in the line and increasing resistance of the line.

Among the alternative candidate materials for back end of the line (BEOL) interconnects, topological semimetal niobium arsenic (NbAs) has shown a 300K resistivity as low as ˜1 μΩ-cm in the sub-micron scale, enabling potential >50% RC reductions at 5 nm node dimensions. More generally, owing to significant surface-state contributions to carrier transport, both the resistance-area (RA) product and grain-boundary resistivity in the broad class of topological semimetals decrease with reducing dimensions, which makes them promising candidates for beyond Cu interconnects

However, despite the favorable resistance-area (RA) scaling, topological semimetals contain lower carrier densities compared to conventional copper (Cu).

SUMMARY

In some embodiments, to take advantage of topological semimetals as a material for interconnects, while overcoming the lower carrier densities inherent in topological semimetals, structures and methods are described herein that allow for doping the topological semimetals with regions of high carrier concentration materials. In some embodiments, the structures and methods provided herein place one or more carrier-doping layers in contact with the interconnect wiring layers composed of topological semimetals to boost surface-state carrier density and conductivity of the topological semimetal material. In some embodiments, multilayer interconnect are provided herein that include topological semi-metal or topological insulator wiring layer(s) and one or more carrier doping layers in contact with the topological materials. In some embodiments, the carrier doping layer(s) can be discontinuous patches. The structures and methods described herein can provide desirable resistance-area (RA) scaling in reduced dimensions, while simultaneously providing excess carrier concentrations and preserving mobility. In some examples, when compared to interconnect wiring layers composed of the same topological semi-metal, the doped topological semi-metal wiring layers can provide orders of magnitude improvement in conductivity.

In one embodiment, an interconnect structures is provided that includes one or more conducting layers comprised of topological semi-metals and charge carrier doping layers present on at least one surface of the one or more conductive layers of topological semi-metals, wherein the charge carrying doping layers have a charge carrier density greater than the topological semi-metals of the one or more conductive layers. This embodiment increases charge carriers in topological semi-metals.

In another embodiment, an interconnect structure is provided that includes one or more conducting layers comprised of topological insulator and charge carrier doping layers present on at least one surface of the one or more conductive layers of topological insulator, wherein the charge carrying doping layers have a charge carrier density greater than the topological insulator of the one or more conductive layers. This embodiment increases charge carriers in topological insulators.

In yet another embodiment, an interconnect structure is provided that includes one or more conducting layers comprised a conductive material selected from the group consisting of topological semi-metals, topological insulators and combinations thereof.

The interconnect structure may also include discontinuous islands of charge carrier dopants present on at least one surface of the one or more conductive layers of topological insulators, topological semi-metals, or combinations thereof. The discontinuous islands of charge carrying dopants have a charge carrier density greater than the topological insulator of the one or more conductive layers. The discontinuous islands can serve to better distribute charge carriers throughout the topological semi-metals or topological insulators.

In an even further embodiment, an interconnect structure is provided that includes one or more conducting layers comprised a conductive material selected from the group consisting of topological semi-metals, topological insulators and combinations thereof. The interconnect structure may also include a core of charge carrier dopants present on at least one surface of the one or more conductive layers of topological insulators or topological semi-metals. The core of charge carrying dopants have a charge carrier density greater than the topological insulator or topological semi-metal of the one or more conductive layers. The core and shell all for positioning carrier dopants through out the structure.

In one embodiment, a method of forming an interconnect is provided. Metal lines are patterned of a topological semi-metal or topological insulator. Charge carrier concentration in the metal lines of the topological semi-metal is increased by depositing a charge carrier dopant material on at least one surface of the metal lines.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments are intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present description. For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the embodiments of the disclosure, as it is oriented in the drawing figures. The terms “present on” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g., interface layer, may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

In some embodiments, the structures and methods provided herein place one or more carrier-doping layers in contact with the interconnect wiring layers composed of topological semi-metals or topological insulators to boost surface-state carrier density and conductivity of the topological semi-metal material. In some embodiments, multilayer interconnect are provided herein that include topological semi-metal or topological insulator wiring layer(s) and one or more carrier doping layers in contact with the topological materials.

“Topological semi-metals” refer to a class of materials in which conduction and valence bands touch at discrete nodal points or along a loop in the first Brillouin zone near the Fermi energy. Such band-crossing points are robust in 3D materials with either broken inversion symmetry or broken time-reversal symmetry, namely, in 3D non-centrosymmetric or 3D magnetic materials. The band-crossing point locations may shift in the Brillouin zone, but they cannot be removed by small perturbations in material parameters. These band-crossing points are generally referred to as the Weyl nodes. One can define an integer-value topological invariant (called Chern number) for each Weyl node as the flux of its “Berry curvature,” where Berry curvature is the momentum-space analogue of the magnetic field. The Weyl nodes thus correspond to the momentum-space magnetic monopoles, namely, the sources or sinks of the Berry curvature. Just as magnetic flux lines must form closed loops, Weyl nodes with opposite Chern numbers appear in pairs in the Brillouin zone.

Another defining attribute of the topological semi-metals is the presence of topological surface states connecting the two Weyl nodes in pairs, forming open Fermi arcs at the Fermi energy. The number of surface bands emanating from one Weyl node to the other is equal to the Chern number associated with the Weyl nodes. Again, small perturbations in structural or material parameters cannot remove the Fermi arcs unless pairs of Weyl nodes annihilate each other, which implies that the topology of the material band structure must change for this to happen. Therefore, both the Weyl nodes and the Fermi arcs are said to be topologically protected.

There are many types of topological semi-metals. We roughly categorize them according to the dimensionality of the band crossings and band degeneracies at the nodes.

Those with 0D band crossings include Weyl semi-metals and multifold-fermion semi-metals. The former has a 2-fold band degeneracy, while the latter can have 3-, 4-, 6-, or 8-fold band degeneracies at the nodes. The non-magnetic, non-centrosymmetric Weyl semi-metals include the TaAs, TaP, NbAs, NbP family, (Mo,W)Te2, LaAlGe, and TaIrTe4. The magnetic Weyl semi-metals include: Co3Sn2S2, Mn3+xSn1−x, EuCd2As2, RAlGe (where R is a rare earth metal), and PrAlGe. The multifold-fermion semi-metals include CoSi, RhSi, CoGe, RhGe, and AlPt. The double-Weyl fermion may also be used in some embodiments.

Besides the topological semi-metals described above, there is yet another distinct type of topological conducting materials—the triple-point topological metals. They feature topologically protected Weyl nodes of three bands, two of which are degenerate along a high-symmetry direction in the Brillouin zone. They are distinct from the topological semi-metals in that the band gap between the conduction and the valence bands closes along this high-symmetry line. Examples of triple-point topological metals include WC, MoC, MoP, MoN, ZrTe, etc.

It is noted that the above compositions for the topological semi-metals is provided for illustrative purposes only. Although those compositions may be used for the topological semi-metals in the followings methods and structures that are described with reference toFIGS.1-20, the present disclosure is not limited to only those examples.

Unlike topological insulators, topological semi-metals have a much higher carrier density at the Fermi level and also high carrier mobility, enabling high current-carrying capacity. As the dimension of the topological semi-metal scales below˜10 nm, carrier transport via the Fermi-arc states becomes pronounced, potentially dominating over the bulk-state transport. Depending on the types of impurity scattering and the type of topological semi-metals, significant surface-state transport may persist up to˜100 μm.

As noted above, in some embodiments, the interconnect wiring layers may be provided by a topological insulator. A “topological insulator” is a material that behaves as an insulator in its interior, but whose surface contains conducting states. This means that electrons can only move along the surface of the material. Topological insulators have non-trivial symmetry-protected topological order. What is special about topological insulators is that their surface states are symmetry-protected Dirac fermions by particle number conservation and time-reversal symmetry. In two-dimensional (2D) systems, this ordering is analogous to a conventional electron gas subject to a strong external magnetic field causing electronic excitation gap in the sample bulk and metallic conduction at the boundaries or surfaces. Topological insulators has been focused on bismuth and antimony chalcogenide based materials. Some examples of topological insulators include Bi2Se3, Bi2Te3, Sb2Te3, (Bi(1−x)Sbx)2Te3, Bi1.1Sb0.9Te2S, Bi1−xSbxand combinations thereof.

It is noted that the above compositions for the topological semi-metals is provided for illustrative purposes only. Although those compositions may be used for the topological semi-metals in the followings methods and structures that are described with reference toFIGS.1-20, the present disclosure is not limited to only those examples.

The interconnect structures of the present disclosure are now described with reference toFIGS.1-9. In some embodiments, the structures provided herein place one or more carrier-doping layers in contact with the interconnect wiring layers composed of topological semimetals or topological insulators to boost surface-state carrier density and conductivity of the topological semimetal material. The carrier doping layers are metallic with high carrier density, and provide excess charge to the surface states of the topological interconnect layers. The structures and methods described herein can provide desirable resistance-area (RA) scaling in reduced dimensions, while simultaneously providing excess carrier concentrations and preserving mobility. In some examples, when compared to interconnect wiring layers composed of the same topological semi-metal, the doped topological semi-metal wiring layers can provide orders of magnitude improvement in conductivity.

FIG.1illustrates one embodiment of interconnect100that is present atop a substrate5. The substrate5may be any substrate with pre-built devices/structures. For example, the substrate may be a type IV semiconductor substrate, such as a silicon (Si) substrate, in which the pre-built devices/structures can include field effect transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), fin type field effect transistors (FinFETs), and vertical field effect transistors (VFET), as well as field effect transistors including nanosheets, etc.

The interconnect100may be atop the substrate5, and can include an interconnect10line composed of a topological semi-metal or a topological insulator. Any of the aforementioned compositions for the topological semi-metal and/or the topological insulator may be employed for the interconnect line10. The interconnect100may include a portion that is in electrical communication with the pre-built devices/structures of the substrate5.

In some embodiments, the interconnect lines10have a thickness of 1 nm to 20 nm. AlthoughFIGS.1-9illustrate interconnect lines10, these wiring layers may also be patterned into vias.

Some embodiments of topological insulators that are suitable for the interconnect lines10depicted inFIGS.1-9can include Bi2Se3, Bi2Te3, Sb2Te3, Bi1.1Sb0.9Te2S, Bi1−xSbxand combinations thereof.

Still referring toFIGS.1-9, in each of the depicted embodiments, carrier doping layers15a,15b,15c,15d,15e,15f,15g,15h,15imay be present in contact with the interconnect lines10. The carrier doping layers15a,15b,15c,15d,15e,15f,15g,15h,15iare metallic with high carrier density, providing excess charge to the surface states of the topological interconnect lines10. The composition of the carrier doping layers15a,15b,15c,15d,15e,15f,15g,15h,15iis selected to provide that charge carriers be introduced to the topological material wiring layer(s), e.g., topological semi-metal and/or topological insulator for the interconnect lines10. The charge carriers from the carrier doping layers15a,15b,15c,15d,15e,15f,15g,15h,15iincrease the charge carrier density in the interconnect lines10. In some examples, the composition of the carrier doping layers15a,15bcan be selected from NiSi, TiSi2, Nb, Ta, TaN, CoSi2, Rh, Ru, Ir, Pt etc.

In some embodiments, the carrier doping layers15a,15b,15c,15d,15e,15f,15g,15h,15imay each comprise a 2-D monolayer (s). In some embodiments, the thickness of the carrier doping layers15a,15b,15c,15d,15e,15f,15g,15h,15iranges from 0.2 nm to 5 nm. The carrier doping layers15a,15bcan act as an ion diffusion barrier and/or ambient encapsulant.

In some embodiments, the carrier doping layers15a,15b,15c,15d,15e,15f,15g,15h,15iare composed of a material having a charger carrier density ranging from 1×1022carriers/cm3to 1×1023carriers/cm3. In some embodiments, the carrier doping layers15a,15b,15c,15d,15e,15f,15g,15h,15iare composed of a material having a low room-temperature resistivity on the order of 1-100 μQ-cm.

In the embodiment depicted inFIG.1, the interconnect lines10are in contact, e.g., in direct contact with, a first carrier doping layer15aat a base of the interconnect line10, and a second carrier doping layer15bat an upper surface of the interconnect line10. In the example, depicted inFIG.1, carrier doping material, e.g., the first and second carrier doping layers15a,15bare not present on the sidewalls of the interconnect lines.

FIG.2illustrates another embodiment of the present disclosure. The example depicted inFIG.2is similar to the example depicted inFIG.1. In the example, depicted inFIG.2, the first carrier doping layer15ais present at the base of the interconnect line10, i.e., between the base of the interconnect line10and the substrate5, but the second carrier doping layer15bthat is depicted inFIG.1is omitted. Although not illustrated other embodiments have been contemplated in which the first carrier doping layer15ais omitted from the interface between the substrate5and the interconnect line10, while the second carrier doping layer15bis present at the upper surface of the interconnect line10.

FIG.3illustrates another embodiment of the present disclosure.FIG.3an interconnect line of multiple carrier doping layers15cthat are alternating with layers of electrically conductive material for the interconnect line10. Similar to the embodiments illustrated inFIGS.1and2, the layers of the interconnect line10may be composed of a topological semi-metal composition or a topological insulator, as described above. The carrier doping layers15cthat alternate with the composition layers of the interconnect line10may be selected from the group consisting of Nb, Ta, TaN, CoSi2, Rh, Ru, Ir, Pt and combinations thereof. Similar to the examples depicted inFIGS.1and2, in the embodiment depicted inFIG.3, the multiple carrier doping layers15care not present on the sidewalls of the interconnect lines10. Each of the multiple carrier doping layers15cmay a 2-D monolayer (s). Each of the multiple carrier doping layers15ccan have a thickness that ranges from 0.2 nm to 5 nm. Each of the multiple carrier doping layers15chave a high carrier density, and provide excess charge to the surface states of the topological interconnect layers10.

FIG.4illustrates yet another embodiment of the present disclosure. InFIG.4, the carrier doping layer15dis present on the exterior sidewalls and upper surface of the interconnect line10. The carrier doping layer15dcan be referred to as an encapsulant layer. The encapsulant layer may have a conformal thickness. In some embodiments, the thickness of the carrier doping layer15dmay range from 0.2 nm to 5 nm. The compositions for the first, second and alternating carrier doping layers15a,15b,15cthat are described above are equally applicable to the encapsulant layer carrier doping layer15dthat is depicted inFIG.4. The encapsulant carrier doping layers15dhas a high carrier density, and provide excess charge to the surface states of the topological interconnect layers10.

FIGS.5and6illustrate one embodiment of the present disclosure in which carrier dopants are introduced to the interconnect lines10by islands15e,15fof carrier dopants. The islands of carrier dopants are discontinuous patches of dopant material, as opposed to the continuous layers of the carrier doping layers having reference numbers15a,15b,15c,15dthat extend across an entirety of a surface, such as an entirety of an upper surface of the interconnect lines10, an entire height of sidewall surfaces of the interconnect lines10, or entirety of the base surface of the interconnect lines10. More specifically, the islands of carrier dopants are present on only a portion of a surface of the interconnect lines10, such as a portion of the upper surface of the interconnect lines10, a portion of the height of sidewall surfaces of the interconnect lines10, or a portion of the base surface of the interconnect lines10. In some examples, the islands may be provided by a dopant that is in the form of nanoparticles or quantum dots distributed on the surface(s) and/or bulk of the interconnect layer. The compositions for the first, second and alternating carrier doping layers15a,15b,15cthat are described above are equally applicable to the composition of the islands15e,15fof carrier dopants that are depicted inFIGS.5and6. The islands of carrier dopants15e,15fhave a high carrier density, and provide excess charge to the surface states of the topological interconnect layers10.

FIGS.7and8illustrate some embodiments of the present disclosure in which core shell configurations are considered for the interconnect lines10and the carrier doping materials15g,15h. InFIG.7, the core is provided by the interconnect lines10, while the shell (also referred to as cladding) is composed of a carrier doping material15g. InFIG.8, the carrier doping material15hprovides the core of the structure, whereas the shell (also referred to as cladding) provides the interconnect lines10. The compositions for the first, second and alternating carrier doping layers15a,15b,15cthat are described above are equally applicable to the composition of the carrier doping materials15g,15hthat are illustrated inFIGS.7and8. The carrier dopants15g,15hhave a high carrier density, and provide excess charge to the surface states of the topological interconnect layers10.

In the embodiment depicted inFIG.9, the interconnect lines10are in contact, e.g., in direct contact with, a sidewall carrier doping layer15ion the sidewalls of the interconnect line10. In the example, depicted inFIG.1, carrier doping material, e.g., the sidewall carrier doping layer15i, is not present on the upper surface of the interconnect lines10. Similar to the embodiments described with reference toFIGS.1-8, the interconnect lines10are composed of topological semi-metals or topological insulators. The compositions for the first, second and alternating carrier doping layers15a,15b,15cthat are described above are equally applicable to the composition of the sidewall carrier doping layer15ithat is illustrated inFIG.9. The sidewall carrier doping layer15ihave a high carrier density, and provide excess charge to the surface states of the topological interconnect lines10.

Each of the interconnect arrangement depicted inFIGS.1-9also include dielectric capping20. The dielectric capping20may be provided by a nitride, such as silicon nitride, or oxide dielectric material.

FIGS.10-15illustrate one embodiment for forming an interconnect including interconnect lines10composed of at least one of topological semi-metals or topological insulators, in which charge carriers in the interconnect lines is increased by carrier doping materials.

In particular,FIG.10is a cross-sectional view depicting a topological interconnect10(comprising a set of vias) at an intermediate stage of the manufacturing process. In the embodiment depicted inFIG.10, the substrate includes prebuilt devices that may have been processed to be in electrical communication with interconnect structures being processed inFIGS.10-14.FIG.10shows the topological interconnect10after the initial formation of a first carrier doping layer15aon top of a substrate5(or dielectric) followed the formation of one of a topological material11, e.g., topological semi-metal or topological insulator, on the first carrier doping layer15a.

The first carrier doping layer15amay be composed of any carrier material that has been described herein. For example, the description of the compositions of the carrier doping material for the structures having reference numbers15a,15b,15c,15d,15e,15f,15g,15hand15iare suitable for providing the composition of the first carrier doping layer15athat is deposited atop the substrate5. In some embodiments, the material of the first carrier doping layer15amay be selected from the group consisting of Nb, Ta, TaN, CoSi2, Rh, Ru, Ir, Pt and combinations thereof. In some examples, the first carrier doping layer15ais selected to be a silicide, such as cobalt disilicide (CoSi2). A number of deposition processes are suitable for forming the first carrier doping layer15a. For example, the first carrier doping layer15amay be formed by at least one of phase segregation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electro deposition, ion implantation, vapor phase reaction, liquid phase reaction, solid state reaction, or reaction with the substrate or liner material. In some embodiments, to provide monolayer thicknesses, atomic layer deposition (ALD) is selected. The thickness of the first carrier doping layer15amay range from 0.2 nm to 5 nm.

It is noted that the first carrier doping layer15adepicted inFIG.10may provide a carrier doping material between the topological material, e.g., topological semi-meal or topological insulator, for the interconnect line and the substrate, as illustrated in any of the embodiments depicted inFIGS.1,2and7, in which a continuous carrier doping layer at the base of the interconnect line is present. To provide a discontinuous doping material, such as the islands of doping material, as depicted inFIGS.5and6, additional processing may be applied. In some embodiments, the islands of doping material can be provided by selective dry and wet etching applied to the deposited material layer of the first carrier doping layer15ato provide either dry or wet etching across grain boundaries. For example, in one embodiment, in which the first carrier doping layer15ais a silicide, such as cobalt disilicide, the carrier doping layer can be converted to discontinuous islands of carrier dopant material by a surface composition modification by reactive ion etch (RIE) along the grain boundaries. In some embodiments, discontinuous islands of carrier dopant material as illustrated by the structures identified by reference numbers15fand15einFIGS.5and6can be provided by a wet etch. For example, when the carrier doping layer15ais a silicide, such as cobalt silicide, the wet etch can selectively target cobalt (Co) to create silicon rich dopant areas near the surface (e.g., having a stoichiometry closer to CoSi2). Alternatively, the wet etch can remove oxygen (O) content with a dilute hafnium fluoride (HF) composition.

Referring back toFIG.10, the topological material11that is deposited on the first carrier doping layer15ahas a composition that is selected to provide the interconnect lines10. For example, the topological material11may be any suitable topological semi-metal or topological insulator, as discussed herein. For example, the topological semi-metal may be NbAs. Additionally, forming the topological semi-metal11on the substrate5(or dielectric) may be done using any suitable fabrication process for depositing a semi-metal on a semiconductor or a dielectric. For example, blanket deposition techniques (e.g., PVD or CVD) may be used to deposit NbAs on the substrate5. For completeness other deposition processes may be considered. For example, “deposition” is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Another deposition technology is plasma enhanced chemical vapor deposition (PECVD), which is a process which uses the energy within the plasma to induce reactions at the wafer surface that would otherwise require higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the film's electrical and mechanical properties.

Referring now toFIG.11, subtractive line patterning is performed to create one or more lines10of topological semi-metal704with gaps between them. The subtractive line10patterning may utilize any suitable fabrication process for removing part of the topological material11. For example, etching may be used to remove portions of the topological material11.

Additionally, via patterning is performed to create multiple vias10a. Any suitable fabrication process for via patterning may be performed. For example, masks may be used during the etching process to prevent etching (or substantially etching) topological material where the vias10aare to be formed.

FIG.12illustrates one embodiment of forming a second carrier doping layer15bon top surface of the interconnect lines10and vias10a. In some embodiments, before the second carrier doping layer15bis formed, oxidized portions of the topological material for the interconnect lines10and vias10acan be removed. The oxidation can be removed by wet cleaning processes or etch processes. Following, the cleaning and/or etch processes to removed oxidation, the second carrier doping layer15bis formed. The second carrier doping layer15bmay be composed of any carrier material that has been described herein. For example, the description of the compositions of the carrier doping material for the structures having reference numbers15a,15b,15c,15d,15e,15f,15g,15hand15iare suitable for providing the composition of the second carrier doping layer15bthat is deposited atop the interconnect lines10and vias10a. In some embodiments, the material of the second carrier doping layer15bmay be selected from the group consisting of Nb, Ta, TaN, CoSi2, Rh, Ru, Ir, Pt and combinations thereof. In some examples, the first carrier doping layer15ais selected to be a silicide, such as cobalt disilicide (CoSi2). A number of deposition processes are suitable for forming the second carrier doping layer15b. For example, the second carrier doping layer15bmay be formed by at least one of phase segregation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electro deposition, ion implantation, vapor phase reaction, liquid phase reaction, solid state reaction, or reaction with the substrate or liner material. In some embodiments, to provide monolayer thicknesses, atomic layer deposition (ALD) is selected. The thickness of the second carrier doping layer15bmay range from 0.2 nm to 5 nm.

It is noted that the second carrier doping layer15bdepicted inFIG.12may provide a carrier doping material on the upper surface of the topological material, e.g., topological semi-meal or topological insulator, as illustrated in any of the embodiments depicted inFIGS.1,3and7, in which a continuous carrier doping layer on the upper surface of the interconnect line10is present. To provide a discontinuous doping material, such as the islands of doping material, on the upper surface of the interconnect lines10, as depicted inFIGS.5and6, additional processing may be applied. In some embodiments, the islands of doping material can be provided by selective dry and wet etching applied to the deposited material layer of the second carrier doping layer15bto provide either dry or wet etching across grain boundaries. For example, in one embodiment, in which the second carrier doping layer15bis a silicide, such as cobalt disilicide, the carrier doping layer can be converted to discontinuous islands of carrier dopant material by a surface composition modification by reactive ion etch (RIE) along the grain boundaries. In some embodiments, discontinuous islands of carrier dopant material as illustrated by the structures identified by reference numbers15finFIG.5can be provided by a wet etch. For example, when the second carrier doping layer15bis a silicide, such as cobalt disilicide, the wet etch can selectively target cobalt (Co) to create silicon rich dopant areas near the surface (e.g., having a stoichiometry closer to CoSi2). Alternatively, the wet etch can remove oxygen (O) content with a dilute hafnium fluoride (HF) composition.

As illustrated by the different embodiments depicted inFIGS.1-9, in the embodiments in which a carrier doping material is not present atop and upper surface of the via10aand/or upper surface of the metal lines10; the second carrier doping layer15bmay be omitted. In these embodiments, when the second carrier doping layer15bis omitted, the subsequently described protective layer15may be formed directly atop the topological material, e.g., topological semi-metal and/or topological insulator, that provides the interconnect lines10and vias10a.

It is further noted, that in some embodiments, the deposition sequence, as well as the order of the deposition sequence, for the materials that provide the topological material11, e.g., the topological material for the topological semi-metal and the topological insulator, as well as the materials for the first and/or second carrier doping layer15a,15bmay be repeated in process flows to provide the structures depicted inFIG.3. The embodiment illustrated inFIG.3includes multiple carrier doping layers identified by reference number15c.

Referring back toFIG.12, following the formation of the second carrier doping layer15b, a protective layer17is formed over the second carrier doping layer15bthat was formed on the tops and sides of the topological material that provides the interconnect lines10and vias10a. In some embodiments (not shown), the protective layer17may also be formed on top of the substrate5between the interconnect lines10.

The protective layer17may be any suitable layer that protects the topological semi-metal704from oxidation. For example, the protective layer17may be a dielectric, e.g., SiCN, SiN, SiC, or metal, such as a metal nitride, e.g., TaN, TiN or combinations thereof. The protective layer17may be formed on the second carrier doping layer15band the substrate5using any suitable fabrication process. For example, a proactive layer17may be formed using a deposition technique. Available deposition techniques may include physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others.

The protective layer17may only be deposited on top of the interconnect lines10and vias10a. Additionally, the protective layer17may be deposited on the sides of the vias10a.

Referring now toFIG.13, a dielectric layer20is formed on top of the protective layer17. The dielectric layer20may be formed using any suitable dielectric material and fabrication technique. The dielectric layer20may have a composition selected from the group consisting of silicon-containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds; the above-mentioned silicon-containing materials with some or all of the Si replaced by Ge; carbon-doped oxides; inorganic oxides; inorganic polymers; hybrid polymers; organic polymers such as polyamides or SiLK™; other carbon-containing materials; organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials; and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, α-C:H). The dielectric layer20can fill in the gaps between the interconnect lines10and vias10a. Additionally, the dielectric layer20is formed on top of the vias10a.

Referring now toFIGS.14, the dielectric layer20undergoes a polishing process (e.g., a dielectric CMP process). The dielectric layer20may be removed such that it fills the gaps between the vias10a. For example, as shown inFIGS.14and15, the dielectric layer20is removed such that the top parts of the dielectric layer20is flush with the highest parts of the protective layer17(i.e., the parts that are on top of the vias10a). This results in the protective layer17on top of the vias10abeing exposed.

Although not depicted in the supplied figures, a dielectric cap is formed on top of the exposed parts of the protective layer17and the dielectric layer20. The dielectric cap may be formed using any suitable fabrication process. For example, forming the dielectric cap may include depositing a dielectric (e.g., low-k) material on top of the protective layer17and the dielectric layer20.

FIGS.16-20illustrate some embodiments of forming carrier dopant material layers on sidewalls of interconnect lines10and vias10a, such as in the structure depicted inFIG.9. The methods illustrated inFIGS.16-20may be combined with the methods illustrated inFIGS.10-15to provide carrier dopant material on base surfaces of interconnect structures, sidewall surfaces of interconnect structures and upper surfaces of interconnect structures, as desired.

FIG.16illustrates one embodiment of forming a mask atop a topological material11. The topological material10may be a topological semi-metal or a topological insulator, as described above with reference toFIGS.1-15. Similarly, the topological material10may be atop a substrate5. The mask18structure may be a photoresist mask that is patterned using photolithography and development processes.

FIG.17illustrates etching the topological material10using the mask18depicted inFIG.16to pattern the structure. In the embodiment, depicted inFIG.17, the pattern provides an interconnect line10. However, other geometries and structures may also be patterned.

FIG.18depicts blanket depositing a carrier dopant layer15ion the structure depicted inFIG.17including the patterned topological material, e.g., interconnect line10. The carrier dopant layer15iis deposited using a conformal deposition method, such as plasma enhanced chemical vapor deposition.

FIG.19is a side cross-sectional view of etching the blanket deposited carrier dopant layer that is depicted inFIG.18with an anisotropic etch that removed the horizontally orientated portions of the carrier dopant layer15i, while the vertically orientated portions of the carrier dopant layer15iremain on sidewalls of the interconnect structure10. As used herein, an “anisotropic etch process” denotes a material removal process in which the etch rate in the direction normal to the surface to be etched is greater than in the direction parallel to the surface to be etched. The anisotropic etch may include reactive-ion etching (RIE). Other examples of anisotropic etching that can be used at this point of the present invention include ion beam etching, plasma etching or laser ablation.

FIG.20illustrating depositing a dielectric20on the structure depicted inFIG.19. The dielectric20depicted inFIG.20is similar to the dielectric layers described in other embodiments of the present disclosure that also have reference number20.

The embodiments of the disclosure that include core/shell arrangements, which are also referred to core and cladding arrangements, can be formed using deposition and etch processes similar to the other embodiments described herein. In one example, the material for the cladding or shell may first be deposited to provide the base shell/cladding portion. A material layer for the core may then be deposited atop the base shell/cladding portion. The material layer for the core can then be patterned to provide the appropriate dimensions to be positioned substantially centrally in the core/shell or core/cladding arrangement. Thereafter, a second material layer for the sidewall and upper surfaces of the cladding or shell be deposited encapsulating the core material between the base portion of the shell/cladding and the sidewall and upper surface portions of the shell/cladding. In some embodiments, such as those described with reference toFIG.7, the core may be provided by a topological material, e.g., topological semi-metal or topological insulator, and the cladding/shell may be provided by a carrier doping layer15g. In embodiments, such as those described with reference toFIG.8, the core may be provided by the carrier doping material15h, and the cladding/shell may be provided by a topological material, e.g., topological semi-metal or topological insulator.

Having described preferred embodiments of a multi-layer topological interconnect with proximal doping layer, it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.