Storage scheme for built-in ECC operations

A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to integrated circuit memory devices, and to circuitry using error correcting codes ECCs.

Description of Related Art

High density memory devices are being designed that include arrays of flash memory cells, or other types of memory cells. In one example, a memory device includes a memory array storing data pages and error correcting codes ECCs for corresponding data pages. The device includes ECC logic to detect and correct errors in the corresponding data pages using the ECCs. The device includes a page buffer coupled to the memory array, to the ECC logic, and to a data path. The page buffer includes sense amplifiers for read operations, a program buffer for write operations, and a cache for read and write operations on data in a data page.

For read operations, data from a data page and error correcting codes ECCs for the page are moved from the memory array to the sense amplifiers, and then from the sense amplifiers to the cache. If the ECC logic is enabled, the ECC logic is then applied on the data using corresponding ECCs, and corrected data is stored in the cache. Corrected data is then moved from the cache to the data path. However, data from a next data page cannot be moved to the cache until after the corrected data in the cache has been moved from the cache to the data path. This results in a lower read throughput for the memory device.

It is desirable to improve the read throughput of a memory device that uses built-in error correcting codes ECCs.

SUMMARY

A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, an input/output data path, and a multi-level buffer structure between the memory array and the input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.

The device includes an interface between the first buffer and the second buffer that provides for movement of a page of data between the first and second buffers in one read or write cycle. The device also includes an interface between the second buffer and the third buffer that provides for movement of a page of data between the second and third buffers in one read or write cycle. The second buffer stores error correcting codes ECCs for corresponding data.

The third buffer of the buffer structure can include a first memory unit and a second memory unit. The first memory unit is coupled to the second buffer of the buffer structure by a storage bus. The second memory unit is coupled to the second buffer of the buffer structure by the storage bus or by a second storage bus. The device includes logic to move data from the second buffer to one of the first memory unit and the second memory unit, while moving data from another of the first memory unit and the second memory unit to the input/output data path.

The device includes ECC logic to detect and correct errors in the data using the corresponding ECCs. The device includes a controller coupled to the multi-level buffer structure, the ECC logic and the memory array. The ECC logic can include logic to move data of a sequence of pages from the memory array, including logic for time-overlapping operations to move error corrected data of a first page from the third buffer to the data path, to move data of a second page from the second buffer to the third buffer, to move data of a third page from the first buffer to the second buffer, and to apply the ECC logic for error detection to data of pages in the sequence before the data is moved out of the second buffer.

The ECC logic can be applied for error correction to data of pages in the sequence before the data is moved out of the third buffer or while the data is moved from one of the first memory unit and the second memory unit to the input/output data path.

The device can include logic to move data from one of the first memory unit and the second memory unit to the second buffer, while moving data from the input/output data path to another of the first memory unit and the second memory unit.

The ECC logic can include logic to move data of a sequence of pages to the memory array, including logic for time-overlapping operations to move data of a second page from the data path to the third buffer, to move data of the second page from the third buffer to the second buffer with ECCs computed by the ECC logic, to move data of a first page out of the first buffer to the memory array with the ECCs, to move data of the second page from the second buffer to the first buffer, and to apply the ECC logic to compute an ECC for data of pages in the sequence before the data is moved out of the second buffer.

DETAILED DESCRIPTION

A detailed description of embodiments of the present invention is provided with reference toFIGS. 1-14.

As used in the present application, a bit is the basic unit of digital data in the memory array. A bit can have only two possible values: either digital one (1) or zero (0). A byte is a unit of digital data in the memory array. A byte contains 8 bits. A word is a unit of digital data in the memory array. A word contains 2 bytes corresponding to 16 bits. A page as used herein refers to an amount of data that is stored in a second buffer or a third buffer in a multi-level buffer structure, on which the ECC logic is applied to either compute ECCs for write operations, or detect and correct errors using the ECCs for read operations. A page can have a fixed size such as 2,048 bytes where each byte has 8 bits. A first page, a second page, a third page, etc., refer to the relative order in which the ECC logic is applied on the data pages, where the order is not associated with any logical or physical locations of data in the memory array.

FIG. 1is a block diagram illustrating a memory device using built-in error correcting codes ECCs (prior art). A memory device100includes a memory array110storing data112and error correcting codes ECCs114for corresponding data. The device100includes ECC logic150to detect and correct errors in the corresponding data using the ECCs. The device100includes a page buffer120coupled to the memory array110, to the ECC logic150, and to a data path170. The page buffer120includes sense amplifiers and a program buffer in block121, and ECC buffer122for ECCs corresponding to data stored by the sense amplifiers and the program buffer. The sense amplifiers and the program buffer are coupled with the memory array110, a cache123for processing data in a data page, and an ECC buffer124storing ECCs corresponding to the data in cache123. The data path170is coupled to an input/output system160, which in turn can be coupled to circuitry external to the device100.

For read operations, data112of a data page in the memory array110and the error correcting codes ECCs114for the data are moved from the memory array110to the sense amplifiers for data in block121and the ECC buffer122, respectively. The data and the ECCs of the data page are then moved from the sense amplifiers to the cache123, and the ECC buffer124, respectively. If the ECC logic is enabled, the ECC logic150is then applied on the data in the cache123for error correction using corresponding ECCs. Corrected data is then output from the cache123via the data path170and the IO system160. If the ECC logic is not enabled, data is moved from the cache123to the data path170without correction of errors.

Accordingly, if the ECC logic is enabled, data from a next data page cannot be moved to the cache123until after the ECC logic150has completed error correction on the data in the cache123, and the corrected data in the cache123has been moved from the cache123to the data path170. The page can have a width (i.e. number of bits) that is much greater than the width of the data path170. In this case, moving the data out of the cache can take many cycles.

For write operations, data is moved from a source external to the device100via the IO system160and the data path170to the cache123. If the ECC logic150is enabled, the data is then moved from the cache123to the program buffer in block121with ECCs computed by the ECC logic150. If the ECC logic is not enabled, the data is then moved from the cache123to the program buffer in block121without ECCs. The memory array110is then programmed with the data from the program buffer in block121.

If the ECC logic is enabled, since the write throughput of the memory device is dominated by the array programming time, and the memory array can be programmed with data of a data page from the program buffer in block121, while data for a next data page can be moved from the data path170to the cache123and then the ECC logic150can compute ECCs for the data in the cache123for the next data page, thus applying the ECC logic causes less timing impact on the write throughput than on the read throughput of the memory device.

FIG. 2is a simplified block diagram of a first embodiment of a memory device200using built-in error correcting ECC logic. The memory device200includes a memory array210storing data212and error correcting codes ECCs214corresponding to the data, and a multi-level buffer structure290between the memory array and an input/output data path270. The memory array includes a plurality of data lines211for page mode operations. The buffer structure includes a first buffer220having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer230coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer240coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.

The device200includes an interface between the first buffer220and the second buffer230that provides for movement of a page of data between the first and second buffers in one read or write cycle. The device200also includes an interface between the second buffer230and the third buffer240that provides for movement of a page of data between the second and third buffers in one read or write cycle. The second buffer230stores error correcting codes ECCs for corresponding data in ECC buffer235.

The third buffer240of the buffer structure290in this example includes a first memory unit241and a second memory unit242. The first memory unit241is coupled to the second buffer230of the buffer structure290by a storage bus (e.g.231-1) and via the data path270. The second memory unit242is coupled to the second buffer230of the buffer structure290by the storage bus (e.g.231-1) or by a second storage bus (e.g.231-2) and via the input/output data path270. The memory device200can include logic to move data from the second buffer to one of the first memory unit and the second memory unit, while moving data from another of the first memory unit and the second memory unit to the input/output data path270. The second data bus221coupling the second buffer230to the first buffer220has a second data bus width of Y bits greater than a width of Z bits of the input/output data path270. For instance, the second data bus221can have a width of 2048 bits if a page size is 2048 bytes, while the input/output data path270can have a width of 8 or 16 bits.

The device includes ECC logic to detect and correct errors in the data using the corresponding ECCs. The device includes a controller (Control Logic inFIG. 14) coupled to the multi-level buffer structure290, the ECC logic250and the memory array210. The ECC logic can include logic to move data of a sequence of pages from the memory array, including logic for time-overlapping operations to move error corrected data of a first page from the third buffer240to the data path270, to move data of a second page from the second buffer230to the third buffer240, to move data of a third page from the first buffer220to the second buffer230, and to apply the ECC logic250for error detection to data of pages in the sequence before the data is moved out of the second buffer230.

The ECC logic250can be applied for error correction to data of pages in the sequence before the data is moved out of the third buffer240or while the data is moved from one of the first memory unit241and the second memory unit242to the input/output data path270.

The memory device200can include logic to move data from one of the first memory unit241and the second memory unit242to the second buffer230, while moving data from the input/output data path270to another of the first memory unit and the second memory unit.

The ECC logic250can include logic to move data of a sequence of pages to the memory array, including logic for time-overlapping operations to move data of a second page from the data path270to the third buffer240, to move data of the second page from the third buffer240to the second buffer230with ECCs computed by the ECC logic250, to move data of a first page out of the first buffer220to the memory array210with the ECCs, to move data of the second page from the second buffer230to the first buffer220, and to apply the ECC logic to compute an ECC for data of pages in the sequence before the data is moved out of the second buffer230.

The ECC logic250on the memory device200can support any suitable ECC scheme. Representative ECC schemes include Hamming code, extended Hamming code, multi-dimensional parity-check code, Reed-Solomon code, BCH code (Bose-Chaudhuri-Hocquenghem), Turbo code, and low-density parity-check code. The length of the error correcting code ECC associated with a particular data set depends on 3 factors: (1) ECC scheme; (2) Maximum corrected bit number; (3) Data length of one page. The BCH code is a class of cyclic error-correcting codes that can correct multiple bit errors. For example, to provide maximum corrected bit number of 40 bits in a page of 8 Kilo-bits of data, the length of the BCH ECC code is 560 bits. For another example, to provide maximum corrected bit number of 24 bits in a 8 Kilo-bits page, the length of the BCH ECC code is 336 bits.

The ECC logic250is coupled to the data path270with a width of Z bits. The data path270is coupled to the second buffer230, the third buffer240, and an input/output system260with a width of Z bits, where Z can be 8 or 16 for example. In read operations, if the ECC logic250is enabled, data is moved from the third buffer240to the input/output system260via the data path270. In read operations, if the ECC logic250is not enabled, data is moved from the second buffer230to the input/output system260via the data path270. In write operations, data is moved from the input/output system260to the third buffer240via the data path270. The data path270with associated control logic configures the buffer structure to allow time-overlapping operations that involve movement of sequences of pages between the second buffer230and the third buffer240, and between one of the two buffers and the input/output system260. For example, in a write mode, time-overlapping operations can include programming the memory array210with data of a first data page from the first buffer220while inputting data of a second data page to the third buffer240. In a read mode, time-overlapping operations can include outputting data from the third buffer240while moving data from the memory array210to the first buffer220.

The first buffer220is coupled with the memory array210via X data lines, and with the second buffer230of the buffer structure290via a bus of Y bits, where the second buffer230can have a width equal to a width of the first buffer220.

The second buffer230can be implemented with a cache memory that has a one row by multiple column architecture. For instance, the second buffer230can have one row with 2048 columns or a width of 2048 bits. The first memory unit241and the second memory unit242can be implemented with SRAMs (static random access memory) that have a multiple row by multiple column architecture. The first memory unit241and the second memory unit242can have a width equal to the width of the data path270and a capacity of up to the width of the second buffer230of the buffer structure290.

FIG. 3is an example flowchart illustrating read operations of the first embodiment. Data of a data page and corresponding ECCs for the data are moved from the memory array (e.g.210,FIG. 2) to the first buffer (e.g.220,FIG. 2) and the ECC buffer (e.g.225,FIG. 2), respectively (Step310). The data and the ECCs are then moved from the first buffer and ECC buffer (e.g.220and225) to the second buffer (e.g.230,FIG. 2) in the buffer structure290before error correction using the ECCs, where the ECCs are stored in the ECC buffer (e.g.235,FIG. 2) associated with the second buffer (Step320).

If the ECC logic250is enabled, the ECC logic is applied on the data of the data page for error detection in the second buffer using corresponding ECCs, while the data of the data page is moved from the second buffer (e.g.230,FIG. 2) to the first memory unit (e.g.241,FIG. 2) or the second memory unit (e.g.242,FIG. 2) in the third buffer (e.g.240,FIG. 2) (Step330). After Step330, the data of the data page is in the third buffer, and the ECC logic has information from error detection for error correction. Error correction can then be executed on the data before the data is moved out of the third buffer, or while the data is moved from one of the first memory unit and the second memory unit to the data path, depending on time allowed by operating specifications for the memory device. If there is enough time, the ECC logic is applied for error correction on the data in the third buffer (Step340), and the data is then moved from the third buffer to the data path (e.g.270,FIG. 2) (Step350). If there is not enough time, the ECC logic is applied for error correction on the data while the data is moved from the third buffer to the data path (e.g.270,FIG. 2) (Step360). If the ECC logic is not enabled, data in the data page can be moved from the second buffer to the data path (e.g.270,FIG. 2), bypassing the third buffer (Step370).

FIG. 4Ais an example timing diagram illustrating read operations associated with the first embodiment with ECC enabled. The timing diagram illustrates time-overlapping read operations for multiple data pages during a first time period T1and a second time period T2. The first time period T1and second time period T2are repeatable for reading more data pages. The first time period T1and the second time period T2alternately use the first memory unit (e.g.241,FIG. 2) and the second memory unit (e.g.242,FIG. 2) in the third buffer (e.g.240,FIG. 2). The timing diagram also illustrates read operations during an initial time period T0prior to the first time period. Signal RDBYB indicates whether the memory device200is ready to output data to a data path (e.g.270inFIG. 2). Read operations in the timing diagram correspond to Steps310-340illustrated in the flowchart inFIG. 3.

During the first time period T1inFIG. 4A, different time-overlapping read operations can be executed on data of three data pages. Data of a first page, Page 1, is moved from the first memory unit (e.g.241,FIG. 2) in the third buffer to the data path (e.g.270,FIG. 2), followed by a wait time, TW, for outputting the next data page (Step350). Data of a second page, Page 2, is moved from the first buffer (e.g.220,FIG. 2) to the second buffer (e.g.230,FIG. 2) (Step320). The ECC logic is then applied on data of Page 2 for error detection in the second buffer using corresponding ECCs while data of Page 2 is moved from the second buffer to the second memory unit (e.g.242,FIG. 2) in the third buffer (Step330). After Step330, data of Page 2 is in the second memory unit, and the ECC logic has information from error detection for error correction. The ECC logic can then be applied for error correction on data of Page 2 in the second memory unit before the data is moved out of the third buffer (Step340). Data and corresponding ECCs for a third page, Page 3, are moved from the memory array (e.g.210,FIG. 2) to the first buffer after Page 2 is moved out of the first buffer to the second buffer (Step310). As used inFIG. 4A, “-2” in “330-2” indicates that the second memory unit is used with Step330. Similarly, “-2” in “340-2” indicates that the second memory unit is used with Step340.

Thus, the ECC logic is applied on data of Page 2 (Step330-2), and data and corresponding ECCs for Page 3 are moved from the memory array to the first buffer (Step310), within the same first time period T1as when data of Page 1 is moved from the first memory unit in the third buffer to the data path. Accordingly, the read throughput of the memory device is improved by not requiring extra time for those read operations for Page 2 and Page 3.

During the second time period T2subsequent to T1inFIG. 4A, different time-overlapping read operations can be executed on data of three data pages. Data of Page 2 is moved from the second memory unit (e.g.242,FIG. 2) in the third buffer to the data path (e.g.270,FIG. 2), followed by the wait time, TW, for outputting the next data page (Step350). Data of Page 3 is moved from the first buffer (e.g.220,FIG. 2) to the second buffer (e.g.230,FIG. 2) (Step320). The ECC logic is then applied on data of Page 3 for error detection in the second buffer using corresponding ECCs while data of Page 3 is moved from the second buffer to the first memory unit (e.g.241,FIG. 2) in the third buffer (Step330). After Step330, data of Page 3 is in the first memory unit, and the ECC logic has information from error detection for error correction. The ECC logic can then be applied for error correction on data of Page 3 in the first memory unit before the data is moved out of the third buffer (Step340). Data and corresponding ECCs for a fourth page, Page 4, are moved from the memory array (e.g.210,FIG. 2) to the first buffer after data of Page 3 is moved out of the first buffer to the second buffer (Step310). As used inFIG. 4A, “-1” in “330-1” indicates that the first memory unit is used with Step330. Similarly, “-1” in “340-1” indicates that the first memory unit is used with Step340.

Thus, the ECC logic is applied on data of Page 3 (Step330-1), and data and corresponding ECCs for Page 4 are moved from the memory array to the first buffer (Step310), within the same first time period T2as when data of Page 2 is moved from the second memory unit in the third buffer to the data path. Accordingly, the read throughput of the memory device is improved by not requiring extra time for those read operations for Page 3 and Page 4.

During an initial time period T0prior to the first time period T1inFIG. 4A, data and corresponding ECCs for the first page, Page 1, are moved from the memory array to the first buffer (Step310). The data of Page 1 is then moved from the first buffer to the second buffer (Step320). The ECC logic is then applied on data of Page 1 for error detection in the second buffer using corresponding ECCs while data of Page 1 is moved from the second buffer to the first memory unit (e.g.241,FIG. 2) in the third buffer (Step330). After Step330, data of Page 1 is in the first memory unit, and the ECC logic has information from error detection for error correction. The ECC logic can then be applied for error correction on data of Page 1 in the first memory unit before the data is moved out of the third buffer (Step340). Data and corresponding ECCs for the second page, Page 2, are moved from the memory array to the first buffer after Page 1 is moved out of the first buffer to the second buffer (Step310).

For example, the initial time period T0can be from about 45 μs (microseconds) to about 70 μs. The time to output a data page (e.g. Page 1 during T1or Page 2 during T2) depends on an output clock frequency and the number of bytes in the data page. For instance, if the output clock has a period of 25 ns (nanoseconds) and there are 2,048 bytes in the data page, then the time to output the data page is about 50 μs (=25 ns×2,048) at a rate of one byte per output clock period, or about 25 μs (=25 ns×2,048/2) at a rate of two bytes per output clock period. The time to read a data page (e.g. Page 3 during T1) from the memory array to the first buffer can be about 20 μs. The time to move a data page (e.g. Page 2 during T1at Step320) from first buffer (e.g.220,FIG. 2) to the second buffer (e.g.230,FIG. 2) can be about 3 μs. The time to apply the ECC logic on a data page for error detection and error correction can range from about 20 μs to about 45 μs.

In general, the time to read data for a data page (e.g. Page 3) from the memory array (Step310) is about constant for every data page. The time to apply the ECC logic for error detection and error correction on another data page (e.g. Page 2) (Steps330and340) can vary depending on the number of failed bits in the data page on which the ECC logic is applied (e.g. Page 2). The first time period T1is the longer of the time to read data (Step310) and the time to apply the ECC logic for error detection and correction (Steps330and340).

FIG. 4Bis an example timing diagram illustrating alternative read operations associated with the first embodiment with ECC enabled. Description aboutFIG. 4Ais generally applicable toFIG. 4B. The difference is that inFIG. 4A, the ECC logic is applied for error correction to data of pages before the data is moved out of the third buffer, while inFIG. 4B, the ECC logic is applied for error correction to data of pages while the data is moved from one of the first memory unit and the second memory unit in the third buffer to the data path. Read operations in the timing diagram correspond to Steps310,320,330and360illustrated in the flowchart inFIG. 3.

During the first time period T1inFIG. 4B, the ECC logic is applied for error correction on data of Page 1 in the first memory unit (e.g.241,FIG. 2) in the third buffer while the data is moved from the first memory unit to the data path (e.g.270,FIG. 2), followed by a wait time, TW, for outputting the next data page (Step360). Data of a second page, Page 2, is moved from first buffer (e.g.220,FIG. 2) to the second buffer (e.g.230,FIG. 2) (Step320). The ECC logic is then applied on data of Page 2 for error detection in the second buffer using corresponding ECCs while data of Page 2 is moved from the second buffer to the second memory unit (e.g.242,FIG. 2) in the third buffer. (Step330). After Step330, data of Page 2 is in the second memory unit, and the ECC logic has information from error detection for error correction. Data and corresponding ECCs for a third page, Page 3, are moved from the memory array (e.g.210,FIG. 2) to the first buffer after Page 2 is moved out of the first buffer to the second buffer (Step310). As used inFIG. 4B, “-2” in “330-2” indicates that the second memory unit is used with Step330.

During the second time period T2subsequent to T1inFIG. 4B, the ECC logic is applied for error correction on data of Page 2 in the second memory unit (e.g. the second memory unit242,FIG. 2) in the third buffer while the data is moved from the second memory unit to the data path (e.g.270,FIG. 2), followed by the wait time, TW, for outputting the next data page (Step360). Data of Page 3 is moved from first buffer (e.g.220,FIG. 2) to the second buffer (e.g.230,FIG. 2) (Step320). The ECC logic is then applied on data of Page 3 for error detection in the second buffer using corresponding ECCs while data of Page 3 is moved from the second buffer to the first memory unit (e.g.241,FIG. 2) in the third buffer (Step330). After Step330, data of Page 3 is in the first memory unit, and the ECC logic has information from error detection for error correction. Data and corresponding ECCs for a fourth page, Page 4, are moved from the memory array (e.g.210,FIG. 2) to the first buffer after data of Page 3 is moved out of the first buffer to the second buffer (Step310). As used inFIG. 4B, “-1” in “330-1” indicates that the first memory unit is used with Step330.

During an initial time period T0prior to the first time period T1inFIG. 4B, data and corresponding ECCs for the first page, Page 1, are moved from the memory array to the first buffer (Step310). The data of Page 1 is then moved from the first buffer to the second buffer (Step320). The ECC logic is then applied on data of Page 1 for error detection in the second buffer using corresponding ECCs while data of Page 1 is moved from the second buffer to the first memory unit (e.g.241,FIG. 2) in the third buffer (Step330). After Step330, data of Page 1 is in the first memory unit, and the ECC logic has information from error detection for error correction. Data and corresponding ECCs for the second page, Page 2, are moved from the memory array to the first buffer after Page 1 is moved out of the first buffer to the second buffer (Step310).

FIG. 4Cis an example timing diagram illustrating read operations associated with the first embodiment with ECC disabled. The timing diagram illustrates read operations for multiple data pages during a first time period T1. The first time period T1is repeatable for reading more data pages. For instance, a second time period T2repeats read operations in T1for subsequent data pages. The timing diagram also illustrates read operations during an initial time period T0prior to the first time period. Signal RDBYB indicates whether the memory device200is ready to output data to a data path (e.g.270inFIG. 2). Read operations in the timing diagram correspond to Steps310-340illustrated in the flowchart inFIG. 3.

During an initial time period T0prior to the first time period T1inFIG. 4C, data of a first page, Page 1, is moved from the memory array to the first buffer (Step310). Data of Page 1 is then moved from the first buffer to the second buffer (Step320).

During the first time period T1inFIG. 4C, data of Page 1 is moved from the second buffer (e.g.230,FIG. 2) to the data path (e.g.270,FIG. 2), followed by a wait time, TW, for outputting the next data page (Step370). Data of a second page, Page 2, is moved from the memory array to the first buffer (Step310), and then from the first buffer (e.g.220,FIG. 2) to the second buffer (e.g.230,FIG. 2) (Step320). In the second time period T2, data of a third page, Page 3, is moved from the memory array (e.g.210,FIG. 2) to the first buffer after Page 2 is moved from the first buffer to the second buffer (Step310).

The control logic includes logic to move data of a sequence of pages to the memory array in a write mode. In the write mode, using time-overlapping operations, data of the first page is moved out of the first buffer to the memory array with the ECCs (e.g.220inFIG. 2), data of a second page is moved from the data path (e.g.270inFIG. 2) to the third buffer (e.g.240inFIG. 2), then data of the second page is moved from the third buffer to the second buffer (e.g.230inFIG. 2) with ECCs computed by the ECC logic (e.g.250inFIG. 2), and then data of the second page is moved from the second buffer to the first buffer with the ECCs after data of the first page is moved out of the first buffer to the memory array with the ECCs. The ECC logic is applied to compute an ECC for data of pages in the sequence before the data is moved out of the second buffer.

FIG. 5is an example flowchart illustrating write operations associated with the first embodiment. Data is moved from the data path (e.g.270inFIG. 2) to the first memory unit (e.g.241,FIG. 2) or the second memory unit (e.g.242,FIG. 2) in the third buffer (e.g.240inFIG. 2) (Step510).

If the ECC logic is enabled, the data is then moved from the first memory unit or the second memory unit in the third buffer to the second buffer (e.g.230inFIG. 2) with ECCs computed by the ECC logic (Steps520and525). The data is then moved from the second buffer to the first buffer (e.g.220inFIG. 2) with the ECCs (Step530), and then moved from the first buffer to the memory array (e.g.210inFIG. 2) with the ECCs (Step540). For the first embodiment, the ECC logic is applied to compute an ECC for the data while the data is moved from the data path to the first memory unit (e.g.241,FIG. 2) or the second memory unit (e.g.241,FIG. 2) in the third buffer.

If the ECC logic is not enabled, the data is then moved from the first memory unit or the second memory unit in the third buffer to the second buffer (Step525), then from the second buffer to the first buffer (Step530), and then moved from the first buffer to the memory array without ECCs (Step540).

FIG. 6is an example timing diagram illustrating write operations associated with the first embodiment with ECC enabled. Write operations in the timing diagram correspond to steps510,520,530, and540illustrated in the flowchart inFIG. 5. The timing diagram illustrates write operations on multiple data pages during a first time period T1and a second time period T2. The first time period T1and second time period T2are repeatable for writing more data pages. The first time period T1and the second time period T2alternately use the first memory unit (e.g.241,FIG. 2) and the second memory unit (e.g.242,FIG. 2) in the third buffer (e.g.240,FIG. 2), as described below. The timing diagram also illustrates write operations during an initial time period T0prior to the first time period. Signal RDBYB indicates whether the memory device200is ready to input data from the data path (e.g.270,FIG. 2).

During the first time period T1inFIG. 6, different time-overlapping write operations can be executed on two data pages. Data of a first page, Page 1, is moved out of the first buffer to the memory array with the ECCs (Step540). Data of a second page, Page 2, is moved from the data path to the first memory unit in the third buffer (Step510), then from the first memory unit in the third buffer to the second buffer with ECCs computed by the ECC logic (Steps520and525), and then from the second buffer to the first buffer with the ECCs after data of Page 1 is moved out of the first buffer to the memory array (Step530). The ECC logic is applied to compute an ECC for data of Page 2 while the data is moved from the first memory unit (e.g.241,FIG. 2) in the third buffer to the second buffer (e.g.230,FIG. 2). The ECCs computed by the ECC logic is stored in ECC buffer235as illustrated inFIG. 2.

Thus, data of Page 2 is moved from the data path to the first memory unit in the third buffer, and then to the second buffer with ECCs computed by the ECC logic, within the same first time period T1as when data of Page 1 is moved to the memory array. Accordingly, ECC write operations on a data page (e.g. Page 2,FIG. 6) causes almost no timing impact on the write throughput of the memory device.

During the second time period T2subsequent to T1inFIG. 6, different time-overlapping write operations can be executed on two data pages. Data of Page 2 is moved out of the first buffer to the memory array with the ECCs (Step540). Data of a third page, Page 3, is moved from the data path to the second memory unit in the third buffer (Step510), then from the second memory unit in the third buffer to the second buffer with ECCs computed by the ECC logic (Steps520and525), and then from the second buffer to the first buffer with the ECCs after data of Page 2 is moved out of the first buffer to the memory array (Step530). The ECC logic is applied to compute an ECC for data of Page 3 while the data is moved from the second memory unit (e.g.242,FIG. 2) in the third buffer to the second buffer (e.g.230,FIG. 2). The ECCs computed by the ECC logic is stored in ECC buffer235as illustrated inFIG. 2.

Thus, data of Page 3 is moved from the data path to the second memory unit in the third buffer, and then to the second buffer with the ECCs computed by the ECC logic, within the same time period T2as when data of Page 2 is moved to the memory array. Accordingly, ECC write operations on a data page (e.g. Page 3,FIG. 6) causes almost no timing impact on the write throughput of the memory device.

During an initial time period T0prior to the first time period T1inFIG. 6, data of an initial page, Page 0, is moved from the data path (e.g.270,FIG. 2) to the first memory unit (e.g.241,FIG. 2) in the third buffer, then from the first memory unit in the third buffer to the second buffer (e.g.230inFIG. 2) with ECCs computed by the ECC logic (e.g.250inFIG. 2), and then from the second buffer to the first buffer (e.g.220inFIG. 2) with the ECCs, and then data of Page 0 is moved out of the first buffer to the memory array with the ECCs.

During the same initial time period T0, after data of the initial page, Page 0, is moved to the first memory unit, data of the first page, Page 1, is moved from the data path to the second memory unit (e.g.242,FIG. 2) in the third buffer, then from the second memory unit in the third buffer to the second buffer with ECCs computed by the ECC logic, and then from the second buffer to the first buffer with the ECCs after data of Page 0 is moved out of the first buffer to the memory array.

FIG. 7is a simplified block diagram of a second embodiment of a memory device700using built-in error correcting ECC logic. The device700includes a memory array710storing data712and error correcting codes ECCs714corresponding to the data, an input/output data path, and a multi-level buffer structure790between the memory array and the input/output data path. The memory array includes a plurality of data lines711for page mode operations. The multi-level buffer structure290includes a first buffer720having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer730coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer740coupled to the second buffer and to the input/output data path. The device700includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.

In this example, the data path includes a first data path770A and a second data path770B. The first data path770A couples the ECC logic750to the second buffer730with a width of Z bits. The second data path770B couples an input/output system760to the third buffer740with a width of Z bits, where Z can be 8 or 16 for example. In read and write operations, data is moved between the third buffer740and the input/output system760via the second data path770B.

The device700includes an interface between the first buffer720and the second buffer730that provides for movement of a page of data between the first and second buffers in one read or write cycle. The device700also includes an interface between the second buffer730and the third buffer740that provides for movement of a page of data between the second and third buffers in one read or write cycle. The second buffer730stores error correcting codes ECCs for corresponding data in ECC buffer735.

The device includes ECC logic to detect and correct errors in the data using the corresponding ECCs. The device includes a controller (e.g. Control Logic inFIG. 14) coupled to the multi-level buffer structure790, the ECC logic750and the memory array710. The ECC logic can include logic to move data of a sequence of pages from the memory array, including logic for time-overlapping operations to move error corrected data of a first page from the third buffer740to the second data path770B, to move data of a second page from the second buffer730to the third buffer740, to move data of a third page from the first buffer720to the second buffer730, and to apply the ECC logic750for error detection to data of pages in the sequence before the data is moved out of the second buffer730.

The ECC logic750can include logic to move data of a sequence of pages to the memory array, including logic for time-overlapping operations to move data of a second page from the second data path770B to the third buffer740, to move data of the second page from the third buffer740to the second buffer730with ECCs computed by the ECC logic750, to move data of a first page out of the first buffer720to the memory array710with the ECCs, to move data of the second page from the second buffer730to the first buffer720, and to apply the ECC logic to compute an ECC for data of pages in the sequence before the data is moved out of the second buffer730.

Error correcting codes ECCs for corresponding data in the second buffer730are stored in ECC buffer735. Error correcting codes ECCs for corresponding data in the third buffer740are stored in ECC buffer745. The third buffer740has a width equal to or matching a width of the second buffer730. For instance, the second buffer730and the third buffer740can both have a width of 2048 bits. The second buffer730and the third buffer740can be placed in close proximity in the buffer structure790to achieve compact silicon area and faster transmission time between the two buffers.

A first data bus711with X data lines coupling the first buffer720to the memory array710has a first data bus width equal to or greater than a second data bus width of Y bits of a second data bus721coupling the second buffer730to the first buffer720, where the second data bus width is greater than a width of the first data path770A or the second data path770B.

The third buffer740is coupled to the second buffer730via a third data bus731, and coupled to the second data path770B. The third data bus731has a data bus width of Y bits greater than a width of Z bits of the second data path770B. For instance, the third data bus731can have a data bus width of 2048 bits, while the second data path770B can have a width of 8 or 16 bits. Both the second buffer730and the third buffer740can be implemented with a cache memory that has a one row by multiple column architecture. For instance, both the second buffer730and the third buffer740can have one row with 2048 columns or a width of 2048 bits. Multi-level cache arrangement including the second buffer730and the third buffer740for example can be utilized for procedures requiring operations on data moving into and out of the memory array710, such as in support of ECC operations.

FIG. 7illustrates an alternative arrangement of the second and third buffers of the buffer structure available to the peripheral circuitry that can be effectively utilized for the ECC operations described herein. In the illustrated example, the second buffer730of the buffer structure790can be implemented physically adjacent the first buffer720for example. Also, in the illustrated example, the third buffer740of the buffer structure790can be implemented physically adjacent the second buffer730for example.

FIG. 8is an example flowchart illustrating read operations of the second embodiment. Data and corresponding ECCs of a data page are moved from the memory array (e.g.710,FIG. 7) to the first buffer (e.g.720) and the ECC buffer (e.g.725,FIG. 7), respectively (Step810). The data and the ECCs of the data page are then moved from the first buffer and ECC buffer (e.g.720and725,FIG. 7) to the second buffer (e.g.730,FIG. 7) before error correction using the ECCs, where the ECCs are stored in the ECC buffer (e.g.735,FIG. 7) associated with the second buffer (Step820).

If the ECC logic is enabled, the ECC logic750is applied on the data for error detection and then error correction, using corresponding ECCs (Step830), before the data is moved out of the second buffer. Corrected data of the data page is then moved from the second buffer (e.g.730,FIG. 7) to the third buffer (e.g.740,FIG. 7) (Step840). Corrected data of the data page is then moved from the third buffer to the data path (e.g.770B,FIG. 7) (Step850). If the ECC logic is not enabled, data of the data page is moved from the second buffer to the third buffer (Step840), and then to the data path without error correction (Step850).

FIG. 9is an example timing diagram illustrating read operations associated with the second embodiment with ECC enabled. The timing diagram illustrates read operations for multiple data pages during a first time period T1. The first time period T1is repeatable for reading more data pages. As an example, a second time period T2repeats read operations in the time period T1for more data pages. The timing diagram also illustrates read operations during an initial time period T0prior to the first time period. Signal RDBYB indicates whether the memory device700is ready to output data to a data path (e.g.770B inFIG. 7). Read operations in the timing diagram correspond to Steps810-850illustrated in the flowchart inFIG. 8.

During the first time period T1inFIG. 9, different read operations can be executed on three data pages. Data of a first page, Page 1, is moved from the third buffer (e.g.740,FIG. 7) to the data path (e.g.770B,FIG. 7), followed by a wait time, TW, for outputting the next data page (Step850). Data of a second page, Page 2, is moved from first buffer (e.g.720,FIG. 7) to the second buffer (e.g.730,FIG. 7) (Step820). The ECC logic is applied on the data of Page 2 for error detection and then error correction using corresponding ECCs (Step830). Data of Page 2 is then moved from the second buffer to the third buffer, where the third buffer becomes available for Page 2 during the wait time TW after Page 1 is moved from the third buffer to the data path (Step840). Data and corresponding ECCs for a third page, Page 3, are moved from the memory array (e.g.710,FIG. 7) to the first buffer after Page 2 is moved from the first buffer to the second buffer (Step810).

Thus, the ECC logic is applied on data of Page 2 (Step830), and data and corresponding ECCs for Page 3 are moved from the memory array to the first buffer (Step810), within the same first time period T1as when data of Page 1 is moved from the third buffer to the data path. Accordingly, the read throughput of the memory device is improved by not requiring extra time for those read operations for Page 2 and Page 3.

During an initial time period T0prior to the first time period T1, data and corresponding ECCs for Page 1 are moved from the memory array to the first buffer (Step810), and then from the first buffer to the second buffer (Step820). The ECC logic is applied on the data of Page 1 for error detection and then error correction using corresponding ECCs (Step830). Data of Page 1 is then moved from the second buffer to the third buffer (Step840).

During the same initial time period T0, data and corresponding ECCs for Page 2 are moved from the memory array to the first buffer after Page 1 is moved from the first buffer to the second buffer (Step810).

FIG. 10is an example timing diagram illustrating read operations associated with the second embodiment when ECC is disabled. The timing diagram illustrates read operations for multiple data pages during a first time period T1and a second time period T2. The first time period T1and second time period T2are repeatable for reading more data pages. As an example, a time period T3and a time period T4repeat read operations in the time periods T1and T2for more data pages. The timing diagram also illustrates read operations during an initial time period T0prior to the first time period. Signal RDBYB indicates whether the memory device700is ready to output data to a data path (e.g.770B inFIG. 7). Read operations in the timing diagram correspond to Steps810,820,840and850illustrated in the flowchart inFIG. 8. Step830in the flowchart inFIG. 8is bypassed because ECC is disabled.

During the first time period T1, data of a first page, Page 1, is moved from the third buffer (e.g.740,FIG. 7) to the data path (e.g.770B inFIG. 7) (Step850), and data of a second page, Page 2, is moved from the memory array to the first buffer (e.g.720,FIG. 7) (Step810).

During a second time period T2subsequent to the first time period T1, Page 2 is moved from the first buffer to the second buffer (Step820) and then from the second buffer to the third buffer (Step840), and data of a third page, Page 3, is moved from the memory array to the first buffer after Page 2 is moved from the first buffer to the second buffer (Step810).

During an initial time period T0prior to the first time period T1, data of the first page, Page 1, is moved from the memory array to the first buffer (Step810), then from the first buffer to the second buffer (Step820), and then from the second buffer to the third buffer (Step840). Data of the second page, Page 2, is moved from the memory array to the first buffer after Page 1 is moved from the first buffer to the second buffer after Page 1 is moved from the first buffer to the second buffer (Step810).

FIG. 11is an example flowchart illustrating write operations associated with the second embodiment. Data is moved from the data path (e.g.770B inFIG. 7) to the third buffer (e.g.740inFIG. 7) without ECCs (Step1110).

If the ECC logic is enabled, the data is moved from the third buffer to the second buffer (e.g.730inFIG. 7) with ECCs computed by the ECC logic (Steps1120and1130). The data is moved from the second buffer to the first buffer (e.g.720inFIG. 7) with the ECCs (Step1140), and then moved from the first buffer to the memory array (e.g.710inFIG. 7) with the ECCs (Step1150). For the second embodiment, the ECC logic is applied to compute an ECC for the data while the data is moved from the third buffer (e.g.740inFIG. 7) to the second buffer (e.g.730inFIG. 7) and before the data is moved out of the second buffer.

If the ECC logic is not enabled, the data is moved from the third buffer to the second buffer (Step1120), then from the second buffer to the first buffer (Step1140), and then from the first buffer to the memory array (Step1150).

FIG. 12is an example timing diagram illustrating write operations associated with the second embodiment with ECC enabled. Write operations in the timing diagram correspond to steps1110-1150illustrated in the flowchart inFIG. 11. The timing diagram illustrates write operations on multiple data pages during a first time period T1. The first time period T1is repeatable for writing more data pages. The timing diagram also illustrates write operations during an initial time period T0prior to the first time period. Signal RDBYB indicates whether the memory device700is ready to input data from the data path (e.g.770B,FIG. 7).

During the first time period T1, the data of the first page, Page 1, is moved out of the first buffer to the memory array with the ECCs (Step1150). Data of a second page, Page 2, is moved from the data path to the third buffer without ECCs (Step1110) and then moved from the third buffer to the second buffer without ECCs (Step1120). The ECC logic is applied to compute ECCs on data of Page 2 before the data is moved out of the second buffer (Step1130). Data of Page 2 is then moved from the second buffer to the first buffer with the ECCs computed by the ECC logic after data of Page 1 is moved out of the first buffer to the memory array (Step1140).

Thus, data of Page 2 is moved from the data path to the third buffer without ECCs, and then to the second buffer without ECCs, and the ECC logic is applied to compute ECCs on the data in the second buffer, within the same first time period T1as when data of Page 1 is moved to the memory array. Accordingly, ECC write operations on a data page (e.g. Page 2,FIG. 12) causes almost no timing impact on the write throughput of the memory device.

During an initial time period T0prior to the first time period T1, data of an initial page, Page 0, is moved from the data path to the third buffer without ECCs (Step1110), then from the third buffer to the second buffer without (Step1120). The ECC logic is applied to compute ECCs on data of Page 0 before the data is moved out of the second buffer (Step1130). Data of Page 0 is then moved from the second buffer to the first buffer with the ECCs computed by the ECC logic (Step1140). Data of Page 0 is then moved out of the first buffer to the memory array with the ECCs (Step1150).

During the same initial time period T0, after data of Page 0 is moved from the third buffer to the second buffer, data of Page 1 is moved from the data path to the third buffer without ECCs (Step1110), then from the third buffer to the second buffer without ECCs (Step1120). The ECC logic is applied to compute ECCs on data of Page 1 before the data is moved out of the second buffer (Step1130). Data of Page 1 is then moved from the second buffer to the first buffer with the ECCs computed by the ECC logic after data of Page 0 is moved out of the first buffer to the memory array (Step1140).

FIG. 13is an example timing diagram illustrating write operations associated with the second embodiment when ECC is disabled. The timing diagram illustrates write operations on multiple data pages during a first time period T1. The first time period T1is repeatable for writing more data pages. The timing diagram also illustrates write operations during an initial time period T0prior to the first time period T1. Signal RDBYB indicates whether the memory device700is ready to input data from a data path (e.g.770B inFIG. 7). Write operations in the timing diagram correspond to Steps1110,1120,1140and1150illustrated in the flowchart inFIG. 11. Step1130in the flowchart inFIG. 11is bypassed because ECC is disabled.

During the first time period T1, data of Page 1 is moved out of the first buffer to the memory array (Step1150), data of a second page, Page 2, is moved from the data path to the third buffer (Step1110), then from the third buffer to the second buffer (Step1120), and then from the second buffer to the first buffer after data of Page 1 is moved out of the first buffer to the memory array (Step1140).

During an initial time period T0prior to the first time period T1, data of an initial page, Page 0, is moved from the data path to the third buffer (Step1110), then from the third buffer to the second buffer (Step1120), and then from the second buffer to the first buffer (Step1140), and then data of Page 0 is moved out of the first buffer to the memory array (Step1150).

During the same initial time period T0, Page 1 is moved from the data path to the third buffer after Page 0 is moved from the third buffer to the second buffer (Step1110), then Page 1 is moved from the third buffer to the second buffer (Step1120), and then from the second buffer to the first buffer after data of Page 0 is moved out of the first buffer to the memory array (Step1140).

FIG. 14is a simplified chip block diagram of an integrated circuit memory device according to an embodiment. The integrated circuit1400includes a memory array1460that stores data with ECCs, on an integrated circuit substrate.

A row decoder1440is coupled to a plurality of word lines1445, and arranged along rows in the memory array1460. A column decoder1470is coupled to a plurality of bit lines1465arranged along columns in the memory array1460for reading data from and writing data to the memory array1460. Addresses are supplied on bus1430from control logic1410to column decoder1470, and row decoder1440. A multi-level buffer structure1480is coupled to the column decoder1470, in this example via a first data bus1475, and coupled to input/output circuits1490, in this example via a second data bus1485. The input/output circuits1490are coupled to the input/output data path (e.g.270inFIG. 2, 770A and 770BinFIG. 7). The multi-level buffer structure1480includes a first buffer (e.g.220inFIG. 2, 720inFIG. 7) including sense amplifiers for read operations and a program buffer for write operations. The multi-level buffer structure1480can include a second buffer (e.g.230inFIG. 2, 730inFIG. 7) and a third buffer (e.g.240inFIG. 2, 740inFIG. 7). Input/output circuits1490drive the data to destinations external to the integrated circuit1400. Input/output data and control signals are moved via data bus1405between the input/output circuits1490, the control logic1410and input/output ports on the integrated circuit1400or other data sources internal or external to the integrated circuit1400, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the memory array1460.

In the example shown inFIG. 14, control logic1410using a bias arrangement state machine controls the application of bias arrangement supply voltage generated or provided through the voltage supply or supplies in block1420, such as read and program voltages. The control logic1410is coupled to the multi-level buffer structure1480, the ECC logic1495, and the memory array with ECCs1460. The control logic1410includes logic to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.

In the read mode, during a time period, error corrected data of a first page is moved from a third buffer to the data path, data of a second page is moved from the second buffer to the third buffer, and data of a third page is moved from the memory array to the second buffer. The ECC logic is applied for error detection to data of pages in the sequence before the data is moved out of the second buffer. In one embodiment, the ECC logic is applied for error correction to data of pages in the sequence before the data is moved out of the third buffer or while the data is moved from one of the first memory unit and the second memory unit to the data path. In another embodiment, the ECC logic is applied for error correction to data of pages in the sequence before the data is moved out of the second buffer.

In the write mode, during a time period, data of a first page is moved out of the first buffer to the memory array with the ECCs, data of a second page is moved from the data path to the third buffer, then data of the second page is moved from the third buffer to the second buffer with ECCs computed by ECC logic1495, and then data of the second page is moved from the second buffer to the first buffer with the ECCs after data of the first page is moved out of the first buffer to the memory array. The ECC logic is applied to compute an ECC for data of pages in the sequence before the data is moved out of the second buffer.

The control logic1410can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the control logic comprises a general-purpose processor, which can be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor can be utilized for implementation of the control logic.

Although the storage scheme disclosed is described for ECC operations, the storage scheme can be used for other page mode operations, such as data compression and decompression, to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer.