Pulsed level shifter circuitry

Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.

BACKGROUND

Technical Field

This disclosure relates generally to voltage level-shifting circuitry and more particularly to level-shifting circuitry with time borrowing.

Description of the Related Art

Time borrowing is a circuit technique in which edge-to-edge timing requirements are relaxed such that a longer combinational path can borrow some time from a shorter path in a subsequent stage. For example, an output signal from first circuitry borrowing from second circuitry may arrive after an active clock edge, but still be properly received by the second circuitry.

Circuits often include different voltage domains, with level-shifting circuitry between the domains. Sense amplifiers are one example of level shifting circuitry. For example, a sense amplifier may receive an input value at a relatively lower voltage from a memory cell and output the value at a relatively higher voltage to other circuitry.

Traditional circuitry does not allow time borrowing across voltage domains.

This specification includes references to various embodiments, to indicate that the present disclosure is not intended to refer to one particular implementation, but rather a range of embodiments that fall within the spirit of the present disclosure, including the appended claims. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation—[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical, such as an electronic circuit). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. A “level shifting flip flop” is intended to cover, for example, a circuit that performs this function during operation, even if the circuit in question is not currently being used (e.g., power is not connected to it). Thus, an entity described or recited as “configured to” perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.

The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function, although it may be “configurable to” perform that function. After appropriate programming, the FPGA may then be configured to perform that function.

Further, as used herein, the terms “first,” “second,” “third,” etc. do not necessarily imply an ordering (e.g., temporal) between elements. For example, a referring to a “first” graphics operation and a “second” graphics operation does not imply an ordering of the graphics operation, absent additional language constraining the temporal relationship between these operations. In short, references such as “first,” “second,” etc. are used as labels for ease of reference in the description and the appended claims.

DETAILED DESCRIPTION

Overview of Time Borrowing Across Voltage Domains

In disclosed embodiments, level-shifting circuitry is configured to operate based on an input signal at a first voltage level and generate an output at a second voltage level while allowing time borrowing. For example, pulse circuitry may generate a pulse signal beginning at an active clock edge, and the input to the level-shifting circuitry may be allowed to change during the pulse. Thus, the circuitry may transparently pass and level shift the input during the pulse, which may allow upstream circuitry to borrow time by changing its output during the pulse.

In some embodiments, one set of circuitry drives the output of the level-shifter during the clock pulse and another set of circuitry maintains the output of the level-shifter after the clock pulse. Examples of circuitry discussed herein include flip-flops and static to dynamic converters (SDCs), but the disclosed techniques are not limited to these specific circuit implementations.

FIG. 1is a block diagram illustrating an example latch-based level shifter, according to some embodiments. In the illustrated embodiment, circuitry100includes latch110, pull circuit120, feedback circuit130, and pulse generator140.

Pulse generator140, in the illustrated embodiment, is configured to generate a pulse signal PU and its inverse !PU based on an input clock signal CLK. In some embodiments, the pulse signal is high for an interval after an active clock edge and then remains low until the next active clock edge. An example circuit implementation for pulse generator140is discussed in detail below with reference toFIG. 2A.

Latch110, in some embodiments, is a cross-coupled D-latch that is configured to hold its current value when the pulse signal is low (e.g., when enabled by the feedback circuit130, as discussed in detail below). In the illustrated embodiment, latch110outputs both an output signal Q and its inverse !Q. In other embodiments, latch110may generate a single output. In some embodiments, the data input is in a different voltage domain than the data output Q.

Pull circuit120, in the illustrated embodiment, is configured to perform level conversion to drive the output signal Q to a different voltage level during the pulse. In some embodiments, this allows the data input signal to change during the pulse (e.g., to enable time borrowing by an upstream path) and still be properly output and stored. In the illustrated embodiment, pull circuit120operates based on the data input, the inverse of the data input, and the pulse signal. In detailed embodiments discussed below, pull circuit120is a pull-down circuit, but circuit120may be a pull-up circuit in other embodiments.

Feedback circuit130, in the illustrated embodiment, is configured to maintain the level conversion after the pulse signal, e.g., by enabling cross-coupled circuitry of latch110such that it stores the input signal. After the pulse, the pull circuit120may be tri-stated such that level shifting does not occur after the pulse. In the illustrated embodiment, feedback circuit130operates based on the inverse of the pulse signal. In some embodiments such as SDC implementations, feedback circuit130may also operate based on the CLK signal.

Note that various specific circuit examples discussed herein are included for purposes of illustration but are not intended to limit the scope of the present disclosure. As one example, complementary metal oxide (CMOS) transistor technology is shown in certain figures, but any of various other transistor technologies may be used. Similarly, various polarities of signals are shown but may be represented using other polarities in other embodiments. As one particular example, pull-up circuitry may be replaced with pull-down circuitry and controlled by an inverse of similar input signals. Similarly, the active clock edge may vary (e.g., may be the rising edge, falling edge, or both edges may be active).

FIG. 2Ais a block diagram illustrating an example pulse generator circuit, according to some embodiments. In the illustrated embodiment, the pulse circuit includes multiple inverters210A-210N, NAND gate214, and inverter222.FIG. 2Bis a timing diagram illustrating example pulse signals generated by the circuitry ofFIG. 2A, according to some embodiments. In the illustrated embodiment, the rising clock edge is the active edge.

As shown, in response to the clock transitioning from low to high, NAND gate214generates an inverted pulse corresponding to the delay imposed by inverters210A-210N. As discussed above, in some embodiments, the length of the pulse corresponds to the duration of a window in which time borrowing is allowed to occur.

Example Level Shifting Flip-Flop that Allows Time Borrowing

FIG. 3Ais a circuit diagram illustrating an example level-shifting flip-flop circuit300that allows time borrowing, according to some embodiments. In the illustrated embodiment, circuit300includes transistors T1-T17and inverters312,314, and324. Circuit300receives a data input, PU, and !PU, and generates outputs Q and !Q. As is well-understood by those skilled in the art, an edge-triggered flip flop typically stores the input value in response to an active clock edge and outputs that value until the next active clock edge.

In the illustrated embodiment, the data input and inverter324are in the input voltage domain corresponding to Vddiand Vssiwhile the remaining circuitry is in the output voltage domain corresponding to Vddand Vss. The different domains may have different supply voltages, reference voltages, or both. Note that Vddand Vssrepresent a supply voltage and a reference voltage respectively, with Vddtypically having a larger voltage than Vss(which may be a ground).

Transistors T6, T7, T14, and T15represent an example implementation of pull circuit120while transistors T2, T4, T11, and T16represent an example implementation of feedback circuit130, which may operate in conjunction with the latch. Remaining transistors may operate according to a well-understood cross-coupled latch implementation, when enabled by the feedback circuitry.

During the pulse signal, in the illustrated embodiment, transistors T6and T14are on and transistors T2, T11, T4, and T16are off. Note that the terms “on” and “off” are used herein to indicate conducting and non-conducting states respectively, in disclosed embodiments in which transistors are used as three-terminal switches with a control terminal that controls whether the transistor conducts between the two other terminals. In this situation, if the data input is high, node326is driven low by transistors T6and T7(providing the correct high output at Q via inverter312) while node328is driven high by transistors T12and T13. If the data input changes during the pulse, the change is propagated to nodes326and328via one of the pull-down stacks (e.g., T6and T7or T14and T15).

When the pulse signal ends, transistors T6and T14are turned off and transistors T2, T11, T4, and T16are turned on. In the illustrated embodiment, this de-couples the cross-coupled circuitry from the data input and enables feedback between nodes326and328by properly connecting the cross-coupled circuitry to Vddand Vss. In these embodiments, the cross-coupled latch maintains the output signals in the output domain after expiration of the pulse. For example, if node326is high, it pushes node328low via transistors T17and T16and is similarly pushed high by node328via transistors T2and T3, maintaining the stored value. After the pulse, the level-shifting pull circuitry (e.g., transistors T7and T15) is tri-stated (e.g., by transistors T6and T14being turned off) and the feedback circuitry maintains the outputs at their current level.

In the illustrated embodiment, circuitry300implements an edge-triggered flip-flop that allows the data input to change late, during the pulse, which may allow upstream circuitry to time borrow from circuitry300.

FIG. 3Bis a circuit diagram illustrating an example wide range level shifting flip flop circuit350that allows time borrowing, according to some embodiments. InFIG. 3B, elements numbered similarly to elements ofFIG. 3Amay function as described above with reference toFIG. 3A. In the illustrated embodiment,FIG. 3Balso includes four additional transistors T22-T27.

In the illustrated embodiment, in contrast toFIG. 3A, transistors T3and T13are drain-coupled rather than being controlled by the cross-coupling. Transistors T26and T27are controlled by the cross-coupling. Further, transistors T22and T24and T23and T25drive nodes328and328based on the data input and voltages at other circuit nodes. In various embodiments, the disclosed circuitry ofFIG. 3Bmay allow a wider range of level shifting, relative to the circuitry ofFIG. 3A.

Example Level Shifting SDC that Allows Time Borrowing

FIG. 4Ais a circuit diagram illustrating an example level shifting SDC circuit400that allows time borrowing, according to some embodiments. In the illustrated embodiment, circuit400includes transistors T1-T21and inverters312,314, and324. Circuit400receives a data input, CLK, PU, and !PU, and generates output Q and !Q. As is well-understood by those skilled in the art, an SDC typically passes the data input through to the Q terminal when the clock is high and outputs a low signal on the Q terminal when the clock is low. Similarly, if a complimentary output such as !Q is implemented, the SDC inverts the data input on the !Q terminal when the clock is high but outputs a low signal on the !Q terminal when the clock is low. This converts a static data input signal into a dynamically encoded output, in some embodiments.

InFIG. 4A, elements numbered similarly to elements ofFIG. 3Amay function as described above with reference toFIG. 3A. In the illustrated embodiment,FIG. 4Aalso includes four additional transistors T18-T21. Transistors T18and T19, in the illustrated embodiment, drive the Q and !Q outputs low when the clock is low. Transistors T20and T21are off when the clock signal is low, disabling the cross-coupled feedback. In the illustrated embodiment, the pull circuitry drives the outputs during the pulse, the feedback circuitry maintains the outputs from the end of the pulse to the next falling clock edge, and transistors T18and T19drive the outputs until the next rising clock edge and pulse. In the illustrated embodiment, circuitry400implements an SDC that allows the data input to change late, during the pulse, and still affect the dynamic output.

FIG. 4Bis a circuit diagram illustrating an example wide range level shifting SDC circuit450that allows time borrowing, according to some embodiments. InFIG. 4B, elements numbered similarly to elements ofFIGS. 3A, 3B, and 4Amay function as described above with reference to those figures. In the illustrated embodiment,FIG. 4Balso includes four additional transistors T28and T29.

In the illustrated embodiment, in contrast toFIG. 4A, transistors T3and T13are drain-coupled rather than being controlled by the cross-coupling. Transistors T26and T27are controlled by the cross-coupling. Further, transistors T22and T24and T23and T25drive nodes328and328based on the data input and voltages at other circuit nodes.

In the illustrated embodiment, transistors T28and T29are configured to drive the outputs Q and Q! low when the clock signal is low. In various embodiments, the disclosed circuitry ofFIG. 4Bmay allow a wider range of level shifting, relative to the circuitry ofFIG. 4A.

In some embodiments, level-shifting circuitry may be implemented with a single output (e.g., with the Q output but not the !Q output). This may allow additional time borrowing on a certain data transition (e.g., the 0 to 1 data transition). For example, inFIG. 4Athe inverter314may be replaced with a transistor coupled between node328and Vssand controlled by the inverse of the CLK signal, in these embodiments. Similarly, any of the various circuits discussed herein with complementary outputs may be implemented with a single output.

Example Method

FIG. 5is a flow diagram illustrating a method500for operating a pulsed level shifting circuit, according to some embodiments. The method shown inFIG. 5may be used in conjunction with any of the computer circuitry, systems, devices, elements, or components disclosed herein, among others. In various embodiments, some of the method elements shown may be performed concurrently, in a different order than shown, or may be omitted. Additional method elements may also be performed as desired.

At510, in the illustrated embodiment, pulse circuitry generates a pulse signal in response to an active clock edge. The circuitry ofFIG. 2Ais one example of pulse circuitry. The active clock edge may be a rising edge of a clock signal or a falling edge of the clock signal. The pulse may begin at the active clock edge and end before a next clock edge or before a next active clock edge.

At520, in the illustrated embodiment, pull circuitry drives, during the pulse signal, an output of latch circuitry to match a logical value of an input signal, where the input signal has a first voltage level and the output has a second voltage level. In some embodiments, the pull circuitry includes a transistor stack coupled between the output of the latch circuitry and a source voltage or reference voltage (e.g., Vddor Vss). The transistor stack may include a first transistor controlled by the pulse signal (which includes being controlled by an inverse of the pulse signal) and a second transistor controlled by the input signal (which includes being controlled by an inverse of the pulse signal).

At530, in the illustrated embodiment, feedback circuitry maintains the output of the latch circuitry at the second voltage level after the pulse signal. In some embodiments, this includes enabling cross-coupled circuitry of the latch circuitry after the pulse signal (e.g., by turning on transistors T2, T11, T4, and T16). In some embodiments, the latch circuitry stores a value of the input signal, e.g., when enabled by the feedback circuitry.

In some embodiments, the method implements flip-flop functionality with level shifting. In some embodiments, the method implements SDC functionality with level shifting. In some SDC embodiments, one or more transistors drive the output of the latch to a logical zero when the clock is low and disable at least a portion of the feedback circuitry when the clock is low.

In some embodiments, circuitry configured to generate the input signal at the first voltage level time borrows from the latch circuitry by changing the input signal after the active clock edge and during the pulse signal. In some embodiments, the pull circuitry changes the output of the latch circuitry during the pulse to match the change in the input signal.

In various embodiments, the disclosed techniques may allow time borrowing across voltage domains.

Example Device

Referring now toFIG. 6, a block diagram illustrating an example embodiment of a device600is shown. In some embodiments, elements of device600may be included within a system on a chip. In some embodiments, device600may be included in a mobile device, which may be battery-powered. Therefore, power consumption by device600may be an important design consideration. In the illustrated embodiment, device600includes fabric610, compute complex620input/output (I/O) bridge650, cache/memory controller645, graphics unit670, and display unit665. In some embodiments, device600may include other components (not shown) in addition to and/or in place of the illustrated components, such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

The techniques disclosed herein may be utilized in various processors of various types of computing devices. For example, disclosed circuitry may be implemented in a memory controller, graphics unit, processor core, etc.

Fabric610may include various interconnects, buses, MUX's, controllers, etc., and may be configured to facilitate communication between various elements of device600. In some embodiments, portions of fabric610may be configured to implement various different communication protocols. In other embodiments, fabric610may implement a single communication protocol and elements coupled to fabric610may convert from the single communication protocol to other communication protocols internally.

In the illustrated embodiment, compute complex620includes bus interface unit (BIU)625, cache630, and cores635and640. In various embodiments, compute complex620may include various numbers of processors, processor cores and/or caches. For example, compute complex620may include 1, 2, or 4 processor cores, or any other suitable number. In one embodiment, cache630is a set associative L2 cache. In some embodiments, cores635and/or640may include internal instruction and/or data caches. In some embodiments, a coherency unit (not shown) in fabric610, cache630, or elsewhere in device600may be configured to maintain coherency between various caches of device600. BIU625may be configured to manage communication between compute complex620and other elements of device600. Processor cores such as cores635and640may be configured to execute instructions of a particular instruction set architecture (ISA) which may include operating system instructions and user application instructions.

Cache/memory controller645may be configured to manage transfer of data between fabric610and one or more caches and/or memories. For example, cache/memory controller645may be coupled to an L3 cache, which may in turn be coupled to a system memory. In other embodiments, cache/memory controller645may be directly coupled to a memory. In some embodiments, cache/memory controller645may include one or more internal caches.

As used herein, the term “coupled to” may indicate one or more connections between elements, and a coupling may include intervening elements. For example, inFIG. 6, graphics unit670may be described as “coupled to” a memory through fabric610and cache/memory controller645. In contrast, in the illustrated embodiment ofFIG. 6, graphics unit670is “directly coupled” to fabric610because there are no intervening elements.

Graphics unit670may include one or more processors and/or one or more graphics processing units (GPU's). Graphics unit670may receive graphics-oriented instructions, such as OPENGL®, Metal, or DIRECT3D® instructions, for example. Graphics unit670may execute specialized GPU instructions or perform other operations based on the received graphics-oriented instructions. Graphics unit670may generally be configured to process large blocks of data in parallel and may build images in a frame buffer for output to a display. Graphics unit670may include transform, lighting, triangle, and/or rendering engines in one or more graphics processing pipelines. Graphics unit670may output pixel information for display images. Programmable shader675, in various embodiments, may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and compute tasks (which may or may not be graphics-related).

Display unit665may be configured to read data from a frame buffer and provide a stream of pixel values for display. Display unit665may be configured as a display pipeline in some embodiments. Additionally, display unit665may be configured to blend multiple frames to produce an output frame. Further, display unit665may include one or more interfaces (e.g., MIPI® or embedded display port (eDP)) for coupling to a user display (e.g., a touchscreen or an external display).

Example Computer-Readable Medium

The present disclosure has described various example circuits in detail above. It is intended that the present disclosure cover not only embodiments that include such circuitry, but also a computer-readable storage medium that includes design information that specifies such circuitry. Accordingly, the present disclosure is intended to support claims that cover not only an apparatus that includes the disclosed circuitry, but also a storage medium that specifies the circuitry in a format that is recognized by a fabrication system configured to produce hardware (e.g., an integrated circuit) that includes the disclosed circuitry. Claims to such a storage medium are intended to cover, for example, an entity that produces a circuit design, but does not itself fabricate the design.

FIG. 7is a block diagram illustrating an example non-transitory computer-readable storage medium that stores circuit design information, according to some embodiments. In the illustrated embodiment semiconductor fabrication system720is configured to process the design information715stored on non-transitory computer-readable medium710and fabricate integrated circuit730based on the design information715.

Design information715may be specified using any of various appropriate computer languages, including hardware description languages such as, without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information715may be usable by semiconductor fabrication system720to fabricate at least a portion of integrated circuit730. The format of design information715may be recognized by at least one semiconductor fabrication system720. In some embodiments, design information715may also include one or more cell libraries which specify the synthesis and/or layout of integrated circuit730. In some embodiments, the design information is specified in whole or in part in the form of a netlist that specifies cell library elements and their connectivity. Design information715, taken alone, may or may not include sufficient information for fabrication of a corresponding integrated circuit. For example, design information715may specify the circuit elements to be fabricated but not their physical layout. In this case, design information715may need to be combined with layout information to actually fabricate the specified circuitry.

Integrated circuit730may, in various embodiments, include one or more custom macrocells, such as memories, analog or mixed-signal circuits, and the like. In such cases, design information715may include information related to included macrocells. Such information may include, without limitation, schematics capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to graphic data system (GDSII), or any other suitable format.

Semiconductor fabrication system720may include any of various appropriate elements configured to fabricate integrated circuits. This may include, for example, elements for depositing semiconductor materials (e.g., on a wafer, which may include masking), removing materials, altering the shape of deposited materials, modifying materials (e.g., by doping materials or modifying dielectric constants using ultraviolet processing), etc. Semiconductor fabrication system720may also be configured to perform various testing of fabricated circuits for correct operation.

In various embodiments, integrated circuit730is configured to operate according to a circuit design specified by design information715, which may include performing any of the functionality described herein. For example, integrated circuit730may include any of various elements shown inFIG. 1, 2A, 3A, 3B, 4A, or4B. Further, integrated circuit730may be configured to perform various functions described herein in conjunction with other components. Further, the functionality described herein may be performed by multiple connected integrated circuits.