Power converting system with function of reducing dead-time

A driving circuit includes a dead-time detecting circuit, a duty-cycle controlling circuit, and a switch controlling circuit. The dead-time detecting circuit is coupled to an output of a power switch set for detecting a switching voltage on the output of the power switch set and accordingly outputting a dead-time detecting signal. The output of the power switch set is coupled to the first end of an inductive load, and the second end of the inductive load provides an output voltage. The duty-cycle controlling circuit is coupled to the second end of the inductive load for generating a set/reset signal according to the output voltage. The switch controlling circuit controls the power switch set to be away from a dead state according to the set/reset signal and the dead-time detecting signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a power converting system, and more particularly, to a power converting system with function of reducing the dead-time.

2. Description of the Prior Art

In the PWM/PFM circuit, controlling the dead-time is very important. In the prior art, the dead-time generator is composed only of logic gates so that the generated dead-time is easily affected by the fabrication or the temperature. If the generated dead-time is too short, then the power switches of the output-stage circuit of the PWM/PFM circuit may be simultaneously turned-on, generating the large current, causing the power switches overheated and even broken-down. If the generated dead-time is too long, the efficiency of the PWM/PFM circuit is reduced. Therefore, in design for the PWM/PFM circuit, the dead-time has to be properly designed and steadily controlled.

SUMMARY OF THE INVENTION

The present invention provides a driving circuit with function of reducing dead-time. The driving circuit comprises a dead-time detecting circuit, a duty-cycle controlling circuit, and a switch-controlling circuit. The dead-time detecting circuit is coupled to an output of a power switch set for detecting a switching voltage on the output of the power switch set and accordingly generating a dead-time detecting signal. The output of the power switch set is coupled to a first end of an inductive load. A second end of the inductive load provides an output voltage. The duty-cycle controlling circuit is coupled to the second end of the inductive load. The duty-cycle controlling circuit is utilized for generating a set/reset signal according to the output voltage. The switch-controlling circuit is utilized for changing the state of the power switch set from a dead-time state according to the set/reset signal and the dead-timed detecting signal.

The present invention further provides a power converting system with function of reducing dead-time. The power converting system comprises a power switch set, a dead-time detecting circuit, a duty-cycle controlling circuit, and a switch-controlling circuit. The power switch set is coupled to an inductive load. The power switch set has a first power switch and a second power switch. The power switch set is controlled to be away from a dead-time state according to a first switch-driving signal and a second switch-driving signal. The dead-time detecting circuit is coupled to a first end of the inductive load. The dead-time detecting circuit is utilized for detecting a switch voltage on the first end of the inductive load and accordingly generating a dead-time detecting signal. The duty-cycle controlling circuit is coupled to a second end of the inductive load. The duty-cycle controlling circuit is utilized for generating a set/reset signal according to an output voltage of the power converting system. The switch-controlling circuit is utilized for generating the first switch-controlling signal and the second switch-controlling signal according to the set/reset signal and the dead-time detecting signal.

DETAILED DESCRIPTION

The present invention provides a power converting system capable of determining if the power converting system is in a dead-time state. When the power converting system is in the dead-time state, the corresponding power switch is turned on in time for reducing the dead-time and improving the efficiency.

Please refer toFIG. 1.FIG. 1is a diagram illustrating a power converting system100according to a preferred embodiment of the present invention. The power converting system100can be determined to operate in a Continuous Current Mode (CCM) or in a Discontinuous Current Mode (DCM) for converting an input voltage source VINinto an output voltage source VOUT. The power converting system100comprises a driving circuit700, a power switch set200, an inductive load L, and an output capacitor COUT. The power switch set200comprises power switches Q1and Q2. In the power converting system100, the power switch set200can be treated as a PWM/PFM circuit. The power switch Q1can be a P channel Metal Oxide Semiconductor (PMOS) transistor, and D1is a parasitic diode of the power switch Q1; the power switch Q2can be an N channel Metal Oxide Semiconductor (NMOS) transistor, and D2is a parasitic diode of the power switch Q2. When the power switch Q1is turned on and the power switch Q2is turned off, the input voltage source VINcharges the output capacitor COUTthrough the power switch Q1and the inductive load L so that the output voltage VOUTrises; when the power switch Q1is turned off and the power switch Q2is turned on, the voltage polarity of the inductive load L reverses so that the output voltage VOUTfalls, wherein when the power switch is turned off, the inductive load L drains a current from the voltage source VSSthrough the power switch Q2and the parasitic diode D2for maintaining the current passing through the inductive load L and providing the current to the output capacitor so as to slow down the speed of the output voltage VOUTfalling. In the above-mentioned situation, the inductive load L is in a discharging state. In this way, the output voltage VOUTcan be repeatedly controlled to rise/fall for the output voltage VOUTkeeping at a predetermined voltage level by means of controlling on/off states of the power switches Q1and Q2.

The driving circuit700is utilized for controlling on/off states of the power switches Q1and Q2according to the output voltage VOUTand a switching voltage VSon an output O of the power switch set200. In addition, for avoiding turning on the power switches Q1and Q2at the same time, the driving circuit700simultaneously turns off the power switches Q1and Q2for a predetermined period so that the power switch set200(or the PWM/PFM circuit) enters the dead-time state (which means the power switch set200is in the dead-time state). For example, when the power switch Q1is turned off and the power switches is not turned on in time, the above-mentioned circuit enters the dead-time state. Meanwhile, since the current passing through the inductive load L has to be continuous because of the characteristic of the inductive load L, the inductive load L generates a reverse electromotive force so that the voltage level of the switching voltage VSof the output O of the power switch set200is lower than the voltage source VSS, causing the parasitic diode D2of the power switch Q2to be turned on, generating the discharging path consequently.

The driving circuit700comprises a duty-cycle controlling circuit300, a dead-time detecting circuit400, a switch-controlling circuit500and a voltage divider600.

The voltage divider600is utilized for dividing the output voltage VOUTso as to generate a feedback voltage VFB, and the voltage divider600comprises two feedback resistors RFB1and RFB2.

The duty-cycle controlling circuit300comprises a duty-cycle controller310and an inverter INV1. When the duty-cycle controlling circuit300determines the voltage level of the feedback voltage VFBis so high that the duty-cycle controlling circuit300is to lower down the output voltage VOUT, the duty-cycle controller310outputs a duty-cycle controlling signal SDUTYrepresenting “reducing” (low voltage level) so that the inverter INV1generates a set/reset signal SS/Rrepresenting “resetting” (high voltage level); when the duty-cycle controlling circuit300determines the voltage level of the feedback voltage VFBis so low that the duty-cycle controlling circuit300is to raise up the output voltage VOUT, the duty-cycle controller310outputs the duty-cycle controlling signal representing “raising” (high voltage level) so that the inverter INV1generates the set/reset signal SS/Rrepresenting “setting” (low voltage level).

The dead-time detecting circuit400is utilized for generating a dead-time detecting signal SDNaccording to the switching voltage VSon the output O of the power switch set200.

The switch-controlling circuit500is utilized for generating switch-driving signals SSWD1and SSWD2according to the set/reset signal SS/Rand the dead-time detecting signal SDNso as to respectively control the power switches Q1and Q2of the power switch set200to be turned on/off. The switch-controlling circuit500comprises a latch circuit510, a logic-calculating module520, and a buffer circuit520. The latch circuit510comprises an R-type latch511, and an S-type latch512. The logic-calculating module520comprises logic-calculating circuits521and522. The buffer circuit530comprises buffers531and532.

The R-type latch511is utilized for outputting a control signal SC1according to a logic signal SH, the set/reset signal SS/R, and the dead-time detecting signal SDN. The R-type latch511comprises an input end I, a reset end R, a clock-control end CLK, and an output end O. The logic signal SHinputted to the input end I of the R-type latch511is determined to always represent the logic “1” (high voltage level). The reset end R of the R-type latch511is utilized for receiving the set/reset signals SS/R; the clock-control end CLK of the R-type latch511is utilized for receiving the dead-time detecting signals SDN; the output end O of the R-type latch511is utilized for outputting the control signal SC1. The R-type latch511is a latch with reset function. That is, when the reset end R of the R-type latch511receives a signal of high voltage level, the control signal SC1outputted by the R-type latch511is reset to be the logic “0” (low voltage level). Moreover, when the set/reset signal SS/Rrepresents “resetting” (high voltage level), the control signal SC1represents the logic “0” (low voltage level); when the set/reset signal SS/Rrepresents “setting” and the dead-time detecting signal SDNrepresents “turning-off”, the control signal SC1remains unchanged (keeps the previous logic); when the set/reset signal SS/Rrepresents “setting” and the dead-time detecting signal SDNrepresents “turning-on”, the control signal SC1becomes representing the logic “1”.

The S-type latch512is utilized for outputting a control signal SC2according to a logic signal SL, the set/reset signal SS/R, and the dead-time detecting signal SDN. The S-type latch comprises an input end I, a set end S, a clock-control end CLK, and an output end O. The logic signal SLinputted to the input end I of the S-type latch512is determined to always represent the logic “0” (low voltage level). The set end S of the S-type latch512is utilized for receiving the set/reset signals SS/R; the clock-control end CLK of the S-type latch512is utilized for receiving the dead-time detecting signals SDN; the output end O of the S-type latch512is utilized for outputting the control signal SC2. The S-type latch512is a latch with set function. That is, when the set end S of the S-type latch512receives a signal of low voltage level, the control signal SC2outputted by the S-type latch512is set to be the logic “1” (high voltage level). Furthermore, when the set/reset signal SS/Rrepresents “setting” (low voltage level), the control signal SC2represents the logic “1” (high voltage level); when the set/reset signal SS/Rrepresents “resetting” and the dead-time detecting signal SDNrepresents “turning-off”, the control signal SC2remains unchanged (keeps the previous logic); when the set/reset signal SS/Rrepresents “resetting” and the dead-time detecting signal SDNrepresents “turning-on”, the control signal SC2becomes representing the logic “0”.

The logic-calculating circuit521comprises a NOR gate NOR1, and an OR gate OR1. When the control signal SC1represents the logic “1”, the OR gate OR1outputs a switch signal SSW1representing the logic “1”; when the control signal SC1represents the logic “0”, the logic of the output signal of the OR gate OR1is determined by the output signal of the NOR gate NOR1. If the set/reset signal SS/Rrepresents “setting” (low voltage level) and the switch-controlling signal SSWD2represents “turning-off” (low voltage level), the signal outputted by the NOR gate NOR1is at the high voltage level. As a result, the logic-calculating circuit521outputs the switch signal SSW1representing the logic “1” at the time; otherwise, If the set/reset signal SS/Rrepresents “resetting” (high voltage level) or the switch-controlling signal SSWD2represents “turning-on” (high voltage level), the signal outputted by the NOR gate NOR1is at the low voltage level. Therefore, the logic-calculating circuit521outputs the switch signal SSW1representing the logic “0” at the time.

The logic-calculating circuit522comprises a NAND gate NAND1, and an AND gate AND1. When the control signal SC2represents the logic “0”, the AND gate AND1outputs a switch signal SSW2representing the logic “0”; when the control signal SC2represents the logic “1”, the logic of the output signal of the AND gate AND1is determined by the output signal of the NAND gate NAND1. If the set/reset signal SS/Rrepresents “resetting” (high voltage level) and the switch-controlling signal SSWD1represents “turning-off” (high voltage level), the signal outputted by the NAND gate NAND1is at the low voltage level. The logic-calculating circuit522outputs the switch signal SSW2representing the logic “0” at the time; otherwise, If the set/reset signal SS/Rrepresents “setting” (low voltage level) or the switch-controlling signal SSWD1represents “turning-on” (low voltage level), the signal outputted by the NAND gate NAND1is at the high voltage level. Thus, the logic-calculating circuit521outputs the switch signal SSW2representing the logic “1” at the time.

The buffers531and532are utilized for generating the switch-controlling signals SSWD1and SSWD2according to the switch signals SSW1and SSW2, respectively. When the switch signal SSW1represents the logic “1”, the switch-driving signal SSWD1represents “turning-on”. Meanwhile, the switch-driving signal SSWD1is at the low voltage level so that the power switch Q1is turned on; when the switch signal SSW1represents the logic “0”, the switch-driving signal SSWD1represents “turning-off”. Meanwhile, the switch-driving signal SSWD1is at the high voltage level so that the power switch Q1is turned off. When the switch signal SSW2represents the logic “1”, the switch-driving signal SSWD2represents “turning-off”. Meanwhile, the switch-driving signal SSWD2is at the low voltage level so that the power switch Q1is turned off; when the switch signal SSW2represents the logic “0”, the switch-driving signal SSWD2represents “turning-on”. Meanwhile, the switch-driving signal SSWD2is at the high voltage level so that the power switch Q2is turned on.

Since when the set/reset signal SS/Rrepresents “resetting” (high voltage level), the R-type latch511outputs the control signal SC1representing the logic “0” (low voltage level), and the signal outputted by the NOR gate NOR1is at the low voltage level as well, so that the OR gate OR1outputs the switch signal SSW1representing the logic “0”. In this way, the buffer531accordingly generates the switch-driving signal SSWD1representing “turning-off” (high voltage level) so as to turn off the power switch Q1; otherwise, when the set/reset signal SS/Rrepresents “setting” (low voltage level), the S-type latch512outputs the control signal SC2representing the logic “1” (high voltage level) and the signal outputted by the NAND gate NAND1is at the high voltage level as well, so that the AND gate AND1outputs the switch signal SSW2representing the logic “1”. In this way, the buffer532accordingly generates the switch-driving signal SSWD2representing “turning-off” (low voltage level) so as to turn off the power switch Q2. Consequently, the power switches Q1and Q2can be controlled to be turned off by means of controlling the set/reset signal SS/R. In this way, the duty-cycle controlling circuit300can detect the magnitude of the output voltage VOUTby means of the feedback voltage VFBfor determining the set/reset signal SS/Rto represent “setting” or “resetting” so as to turn on/off the power switches Q1or Q2through the switch-controlling circuit500.

The dead-time detecting circuit400is utilized for detecting the switching voltage VSon the output end O of the power switch set200(a first end1of the inductive load L) and accordingly generating the dead-time detecting signal SDN. For instance, it is assumed that the power converting system100operates in the CCM mode. When the power switches Q1and Q2are both turned off, the power switch set200is in the dead-time state at the time. That is, the voltage polarity of the inductive load L reverses so that the inductive load L enters the discharging state and drains a current from the voltage source VSSthrough the parasitic diode D2of the power switch Q2. Thus, the voltage level of the switching voltage VSis equal to the voltage source VSS(for example, 0 volt) deducting the forward voltage VD1(around 0.7 volt) of the parasitic diode D2. As a result, the dead-time detecting circuit400outputs the dead-time detecting signal SDNrepresenting “turning-on” (high voltage level); otherwise, when the voltage level of the switching voltage VSis higher than (VSS−VD2), it means the power switch set200does not enter the dead-time state (one of the power switches Q1and Q2is turned on). Therefore, the dead-time detecting circuit400outputs the dead-time detecting signal SDNrepresenting “turning-off” (low voltage level) at the time.

Since when the dead-time detecting signal SDNrepresents “turning-on”, if the set/reset signal SS/Rrepresents “resetting” at the time, the S-type latch512outputs the control signal SC2representing the logic “0”. In this way, AND gate AND1outputs the switch signal SSW2representing the logic “0” so that the buffer532accordingly outputs the switch-driving signal SSWD2representing “turning-on” for turning on the power switch Q2; otherwise, if the set/reset signal SS/Rrepresents “setting” at the time, the R-type latch511outputs the control signal SC1representing the logic “1”. In this way, OR gate OR1outputs the switch signal SSW1representing the logic “1” so that the buffer531accordingly outputs the switch-driving signal SSWD1representing “turning-on” to turn on the power switch Q1.

When the set/reset signal SS/Rrepresents “resetting”, if the dead-time detecting signal SDNchanges from “turning-on” to “turning-off”, the R-type latch511still outputs the control signal SC1representing the logic “0”, and the logic of the control signal SC2outputted by the S-type latch512remains unchanged. Hence, when the dead-time detecting signal SDNchanges from “turning-on” to “turning-off”, the switch-driving signals SSWD1and SSWD2both remain unchanged; when the set/reset signal SS/Rrepresents “setting”, if the dead-time detecting signal SDNchanges from “turning-on” to “turning-off”, the S-type latch512still outputs the control signal SC2representing the logic “1”, and the logic of the control signal SC1outputted by the R-type latch511remains unchanged. Thus, when the dead-time detecting signal SDNchanges from “turning-on” to “turning-off”, both the switch-driving signals SSWD1and SSWD2remain unchanged. That is, when the dead-time detecting signal SDNchanges from “turning-on” to “turning-off”, the on/off states of the power switches Q1and Q2do not change.

In addition, if the power converting system100operates in the DCM mode, when the power switch Q2remains turned-off and the power switch Q1changes from turned-on to turned-off so that the power switch set200enters the dead-time state, the inductive load L still drains the current from the voltage source VSSthrough the parasitic diode D2of the power switch Q2. As a result, the voltage level of the switching voltage VSis equal to the voltage source VSS(0 volt) deducting the forward voltage VD1(around 0.7 volt) of the parasitic diode D2. As a result, the dead-time detecting circuit400outputs the dead-time detecting signal SDNrepresenting “turning-on” (high voltage level) so as to turn on the power switch Q2in time for the power switch set200away from the dead-time state. However, when the power switch Q1remains turned-off and the power switch Q2changes from turned-on to turned-off so that the power switch set200enters the dead-time state, since the power converting system100operates in the DCM mode at the time, the magnitude of the current passing through the inductive load L is reduced to zero. That, the inductive load L does not drain the current from the voltage source VSSthrough the parasitic diode D2of the power switch Q2at the time. In this way, the voltage level of the switching voltage VSis higher than (VSS−VD2). In other words, the dead-time detecting circuit400still outputs the dead-time detecting signal SDNrepresenting “turning-off” (low voltage level) at the time. Hence, the states of the power switch set200cannot be correctly detected.

However, when the power switch Q1remains turned-off and the power switch Q2changes from turned-on to turned-off, it means that the switch-driving signal SSWD2changes from “turning-on” (high voltage level” to “turning-off” (low voltage level) and the set/reset signal SS/Rrepresents “setting” (low voltage level) at the time. Meanwhile, the output logic of NOR gate NOR1of the logic-calculating module520is determined by the switch-driving signal SSWD2. Since the switch-driving signal SSWD2changes from “turning-on” (high voltage level) to “turning-off” (low voltage level), the NOR gate NOR1outputs a high voltage level signal. More particularly, by means of designing the transient voltage of the NOR gate NOR1, when the switch-driving signal SSWD2is lower than the threshold voltage VT2of the power switch Q2, the NOR gate NOR1can determine that the switch-driving signal SSWD2has already changed from the high voltage level to the low voltage level and the power switch Q2has already been turned-off. Therefore, the NOR gate NOR1outputs the high voltage level signal so that the logic-calculating circuit522outputs the switch signal SSW1representing the logic “1”. In this way, the buffer531outputs the switch-driving signal SSWD1representing “turning-on” so as to turn on the power switch Q1for the power switch set200away from the dead-time state.

In summary, in the power converting system100of the present invention, the switch-controlling circuit500detects the output voltage VOUTby means of the voltage divider600, and controls the logic of the set/reset signal SS/Rfor turning on/off the power switches Q1and Q2of the power switch set200through the duty-cycle controlling circuit300. If the power converting system100of the present invention operates in the CCM mode, when the power switch set200enters the dead-time state, the dead-time detecting circuit400detects the power switch set200in the dead-time state so as to output the dead-time detecting signal SDNrepresenting “turning-on”. In this way, the switch-controlling circuit500turns on the corresponding power switch (for instance, the power switch Q2) in time because of the dead-time detecting signal SDNrepresenting “turning-on”. Besides, if the power converting system100of the present invention operates in the DCM mode, when the power switch Q2remains turned-off and the power switch Q1changes from turned-on to turned-off, the dead-time detecting circuit400still can detect the power switch set200in the dead-time state so as to turn on the power switch Q2in time through the switch control circuit500; otherwise, when the power switch Q1remains turned-off and the power switch Q2changes from turned-on to turned-off, the logic-calculating circuit522of the logic-calculating module520, by means of determining the voltage level of the switch-driving signal SSWD2is lower than the threshold voltage VTof the power switch Q2(that is, the power switch Q2has already been turned off), can output the switch signal SSW1representing the logic “1” for the buffer531outputting the switch-driving signal SSWD1so as to turn on the power switch Q1, urging the power switch set200to be away from the dead-time state. In this way, no matter the power converting system100operates in the CCM mode or in the DCM mode, by means of the dead-time detecting circuit400detecting the change of the switching voltage VSand the logic-calculating module520detecting the change of the switch-driving signal SSWD1, the power converting system100can determine if the power switch set200is in the dead-time state so that the switch-controlling circuit500can turn on the corresponding power switch in time for the power switch set200away from the dead-time state. In this way, the dead-time is reduced, improving the efficiency of the power converting system100.

Please refer toFIG. 2. The dead-time detecting circuit400comprises a transistor Q3, two resistors RXNand RL, and a waveform trimmer410. The transistor Q3can be an NMOS transistor. The source of the transistor Q3is coupled to the input end I of the dead-time detecting circuit400(the output O of the power switch set200) for receiving the switching voltage VS; the drain of the transistor Q3is coupled to the resistor RXN, for generating a previous-stage dead-time detecting signal SDNP; the gate of the transistor Q3is utilized for receiving a gate-controlling voltage VG—BIASN. The resistor RXNis coupled between the drain of the transistor Q3and the voltage source VDDfor maintaining the voltage level of the previous-stage dead-time detecting signal SDNPthrough the voltage source VDDwhen the transistor Q3does not generate the previous-stage dead-time detecting signal SDNPrepresenting “turning-on”. The resistor RLis coupled between the source of the transistor Q3and the output O of the power switch set200as a current-limiting resistor, for avoiding the inductive load L discharging too much current to the dead-time detecting circuit400.

The waveform trimmer410is coupled between the drain of the transistor Q3and the output end O of the dead-time detecting circuit400, for trimming the waveform of the previous-stage dead-time detecting signal SDNP, and accordingly outputting the dead-time detecting signal SDN. The waveform trimmer410can be realized with an inverter INVN. In addition, assuming that the voltage drop across the current-limiting resistor RL, and the voltage drops across the power switches Q1and Q2can be ignored, the gate-controlling voltage VG—BIASNcan be designed as following formulas:
(VSS+VT3)>VG—BIASN>VT3+(VSS−VD2)  (1), and
VGS3≧[VT3+(VSS−VD2)−VO];
wherein VO=VSS−VD2, and VT3represents the threshold voltage of the transistor Q3, VD2represents the forward voltage of the parasitic diode D2. The operation principle of the dead-time detecting circuit400is illustrated as below.

When the switching voltage VSis higher than (VSS−VD2), the gate-source voltage VGS3is not higher than the threshold voltage VT3of the transistor Q3at the time so that the transistor Q3is turned off. In this way, the previous-stage dead-time detecting signal SDNPis pulled up to the high voltage level VDDby the voltage source VDDthrough the resistor RXN; the inverter INVNoutputs the dead-time detecting signal SDNrepresenting “turning-off” by inverting the previous-stage dead-time detecting signal SDNP, and the dead-time detecting signal SDNis at the low voltage level at the time. When the switching voltage VSis equal or lowered to (VSS−VD2), it means that the power switch set200is in the dead-time state (both the power switches Q1and Q2are turned-off) and the inductive load L is in the discharging state. The voltage level of the gate-source voltage VGS3of the transistor Q3is [VT3+(VSS−VD2)−VS] at the time. The gate-source voltage VGS3is higher than the threshold voltage VT3of the transistor Q3at the time so that the transistor Q3is turned on. In this way, the previous-stage dead-time detecting signal SDNPis pulled down to the low voltage level through the transistor Q3; the inverter INVNoutputs the dead-time detecting signal SDNrepresenting “turning-on” by inverting the previous-stage dead-time detecting signal SDNP, and the dead-time detecting signal SDNis at the high voltage level.

Hereinafter, it is assumed that the power switch Q1changes from turned-on to turned-off and the power switch Q2is turned-off for further illustrating the operation principle of the dead-time detecting circuit400.

Please refer toFIG. 3, a diagram illustrating the current passing through the inductive load L of the power converting system100when the power switch Q1is turned on and the power switch Q2is turned off. Meanwhile, the switch-driving signal SSWD1represents “turning-on” (low voltage level), and the switch-driving signal SSWD2represents “turning-off” (low voltage level). The input voltage source VINcharges the output capacitor COUTthrough the power switch Q1and the inductive load L so that the output voltage VOUTrises. The voltage level of the switching voltage VSis between the input voltage VINand the output voltage VOUT. Thus, the voltage level of the switching voltage VSis higher than (VSS−VD2) so that the dead-time detecting signal SDNoutputted by the dead-time detecting circuit400represents “turning-off”.

Please refer toFIG. 4, a diagram illustrating when the power switch Q1shown inFIG. 3changes from turned-on to turned-off. Meanwhile, the set/reset signal SS/Rrepresents “resetting” (high voltage level) so as to control the switch-driving signal representing “turning-off” (high voltage level). Meanwhile, the voltage polarity of the inductive load L reverses; the inductive load L drains a current ILD2from the voltage source VSSthrough the parasitic diode D2of the power switch Q2for maintaining the current passing through the inductive load L; and the power switch set200is in the dead-state. The voltage level of the switching voltage VSis equal to the voltage VSS(0 volt) deducting the forward voltage VD2of the parasitic diode D2(around 0.7 volt) at the time. Hence, the S-type latch512generates the control signal SC1representing the logic “0” according to the dead-time detecting signal SDNrepresenting “turning-on” and the set/reset signal SS/Rrepresenting “resetting”. The AND gate AND1outputs the switch signal SSW2representing the logic “0” so that the buffer532generates the switch-driving signal SSWD2representing “turning-on” (high voltage level) so as to turn on the power switch Q2. When the power switch Q2is turned on, the inductive load L can drain a current ILQ2from the voltage source VSSthrough the power switch Q2. Meanwhile, the forward voltage VD2of the parasitic diode D2is equal to the gate-drain voltage VGD2of the power switch Q2(around 0.2 volt). Therefore, the switching voltage VSis raised up to (VSS−VGD2) so that the dead-time detecting signal SDNchanges to represent “turning-off”, which does not affect the on/off states of the power switches Q1and Q2.

Please refer toFIG. 5.FIG. 5is a diagram illustrating the change of the switching voltage VSwhen the power switch Q1changes from turned-on (inFIG. 3) to turned-off (inFIG. 4). At first, the power switch Q1is turned on and the power switch Q2is turned off. The voltage level of the switching voltage VSis between the input voltage VINand the output voltage VOUT. The switching voltage VLis higher that (VSS−VD2) at the time so that the transistor Q3of the dead-time detecting circuit400is turned off. As a result, the dead-time detecting signal SDNoutputted by the dead-time detecting circuit400represents “turning-off” (low voltage level). When the power switch Q1is turned off, the inductive load L drains the current ILD2from the voltage source VSSthrough the parasitic diode D2of the power switch Q2. Meanwhile, the switching voltage is equal to (VSS−VD2) so that the transistor Q3of the dead-time detecting circuit400is turned on. Hence, the dead-time detecting signal SDNoutputted by the dead-time detecting circuit400represents “turning-on” (high voltage level). When the dead-time detecting signal SDNrepresents “turning-on”, the S-type latch512turns on the power switch Q2through the AND gate AND1and the buffer532according to the dead-time detecting signal SDNrepresenting “turning-on” and the set/reset signal SS/Rrepresenting “resetting”. Meanwhile, the inductive load L drains the current ILQ2from the voltage source VSSthrough the power switch Q2. The voltage level of the forward voltage VD2of the parasitic diode D2is equal to the source-drain voltage VGD2(around 0.2 volt). Thus, the switching voltage VSis raised up to (VSS−VGD2) so that the dead-time detecting signal SDNchanges to represent “turning-off”.

Please refer toFIG. 6. The R-type latch511comprises three inverters INV2, INV3, and INV4, a switch SW1, an inverted switch SWN1, and a NOR gate NOR2. The coupling relation between the components of the R-type latch511and the truth table of the R-type latch511are shown inFIG. 6. The operation principle of the R-type latch511is well known to those skilled in the art, and hence will not be repeated again for brevity.

Please refer toFIG. 7. The S-type latch512comprises three inverters INV5, INV6, and INV7, a switch SW2, an inverted switch SWN2, and a NAND gate NAND2. The coupling relation between the components of the S-type latch512and the truth table of the S-type latch512are shown inFIG. 7. The operation principle of the S-type latch512is well known to those skilled in the art, and hence will not be repeated again for brevity.

Please refer toFIG. 8.FIG. 8is a diagram illustrating a buffer800of the present invention. The buffer800can utilized as the buffers531or532of the buffer circuit530. The buffer800comprises N inverters INVC1˜INVCNcoupled in series, and N represents an odd integer. Each inverter is a Complementary Metal Oxide Semiconductor (CMOS) transistor, comprising a PMOS transistor and an NMOS transistor. The ratios of length to width of each CMOS transistor of the buffer800become larger in sequence for buffering. The signal inputted to the buffer800are inverted N times by the N inverters INVC1˜INVCN. Since N is an odd integer, the logic of the output signal of the buffer800is inverted to the logic of the input signal of the buffer800.

In conclusion, no matter the power converting system provided by the present invention operates in the CCM mode or in the DCM mode, the power converting system of the present invention can determine if the power switch set is in the dead-time state by means of the dead-time detecting circuit detecting the change of the switching voltage and the logic-calculating module detecting the change of the switch-driving signal. When the power switch set is in the dead-time state, the dead-time detecting circuit or the logic-calculating module controls the switch-controlling circuit to output the corresponding control signal for turning on the corresponding power switch in time, urging the power switch to be away from the dead-time state. In this way, the dead-time is reduced and the efficiency of the power converting system is improved, causing a great convenience.