METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING SEMICONDUCTOR DEVICE AND MOUNTING ASSEMBLY

A “package-less” integrated circuit semiconductor device is produced by laminating first and second insulating films on opposed first and second surfaces of a semiconductor wafer having semiconductor dice integrated therein. Electrically conductive formations towards die pads of the semiconductor dice are provided in vias to the semiconductor wafer opened through the first insulating film laminated on the first surface of the semiconductor wafer. The semiconductor wafer provided with these electrically conductive formations is singulated at separation lines between neighboring semiconductor dice to produce individual semiconductor devices. Each device has: opposed first and second device surfaces having protective portions of the first and second insulating films laminated thereon, and side surfaces extending between the opposed first and second device surfaces, these side surfaces being left uncovered by the first and second insulating films.

PRIORITY CLAIM

This application claims the priority benefit of Italian Application for U.S. Pat. No. 10,202,3000005985 filed on Mar. 29, 2023, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

TECHNICAL FIELD

The description relates to manufacturing semiconductor devices.

Solutions as described herein can be applied to power (integrated circuit) semiconductor devices for automotive or consumer products, for instance.

BACKGROUND

Various manufacturing methods exist for producing devices for the automotive and/or consumer market.

Desirable qualities of such manufacturing methods include: low production costs, simplicity of the manufacturing process and package size reduction.

A conventional approach that aims at reducing package size is the so-called wafer level chip scale packaging (WLCSP). This approach involves (solder) ball mounting of the final device on a substrate like a printed circuit board (PCB). It is recognized, however, that ball mounting on the package is not a simple assembly step.

Another conventional, and extensively applied, approach is based on the so-called quad flat no leads (QFN) package which is based on the use of a substrate (e.g., a leadframe).

Substrates for use in QFN packaging need an ad-hoc design, that is, depending on the particular device design, and such customized leadframes may involve high costs.

Moreover, conventional approaches are based on wires interconnections which are observed to introduce undesired resistances thus reducing electrical performance of the device. By way of background, the following documents, which are incorporated herein by reference:

N. Kumbhat, et al.: “Chip-last fan-out package with embedded power ICs in ultra-thin laminates” Proceedings-Electronic Components and Technology Conference, 1372-1377; and

are exemplary of various recent advances in manufacturing methods of semiconductor devices aiming at achieving low production costs, simplicity of the manufacturing process and package size reduction.

There is a need in the art for solutions which aim at addressing the issues discussed in the foregoing.

SUMMARY

One or more embodiments relate to a method.

One or more embodiments relate to a corresponding (integrated circuit) semiconductor device.

One or more embodiments relate to a corresponding mounting assembly (namely a semiconductor device mounted on a support member such as a printed circuit board-PCB).

Solutions as described herein propose a simple and cost-effective manufacturing method of semiconductor device aiming at reducing the size of the final package.

In solutions as described herein the manufacturing process may be carried out entirely at wafer level.

In solutions as described herein external metallic pads are finished with a solderable layer facilitating final mounting on a substrate.

In solutions as described herein, wire interconnects are advantageously replaced with direct metallic interconnects provided via electroplating process.

Solutions as described herein may also be used to provide a final device with wettable flanks.

DETAILED DESCRIPTION

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

The edges of features drawn in the figures do not necessarily indicate the termination of the extent of the feature.

Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

For simplicity and ease of explanation, throughout this description, and unless the context indicates otherwise, like parts or elements are indicated in the various figures with like reference signs, and a corresponding description will not be repeated for each and every figure. Various manufacturing processes exist that involve concurrent processing of a plurality of (integrated circuit) semiconductor devices.

As mentioned in the foregoing, such conventional approaches may suffer from various drawbacks. For instance, standard wafer level chip scale packaging (WLCSP) involves ball mounting of the final device on the substrate (a printed circuit board (PCB) for example) and providing solder balls to the package is not a simple processing step.

On the other hand, quad flat no leads (QFN) packages do not involve ball mounting as the leadframe may be directly soldered on the PCB: however, providing customized leadframes depending on the device design may involve high production costs.

The sequence ofFIG.1A to1Jillustrates a conventional manufacturing process of integrated circuits semiconductor devices.

Such a process is oftentimes referred to as wafer/panel level fan-out packaging.

FIG.1Ais illustrative of an insulating film100provided on a semiconductor (silicon, for instance) wafer14including integrated circuits, ICs (chips or dice) formed therein, to be possibly processed together. As used throughout this description, the terms chip/s and die/dice are regarded as synonymous.

For simplicity, these circuits (which can be provided in the wafer14any manner known to those of skill in the art) are not visible as such in the in the figures.

The film100can be laminated on a first (active) surface of the wafer14.

FIG.1Bis illustrative of vias181′ opened (e.g., via laser beam) to the die pads (not visible in the figures for scale reasons) towards the active surface of the wafer14.

The wafer14can be cut (singulated) into individual dice or chips140in a first singulation step, performed via a blade or saw B, for instance, as illustrated inFIG.1C.

As illustrated inFIG.1A to1Cthe steps discussed are performed at wafer level.

According to a conventional approach, after a first singulation step (as exemplified inFIG.1C), concurrent processing of a plurality of devices may be carried out after a wafer or a panel has been reconstituted; that is, individual (singulated) dice140are arranged on a carrier (wafer or panel shaped) in order to facilitate concurrent processing of the devices.

FIG.1Dis illustrative of individual chips/dice140arranged on a first carrier C (a stainless-steel carrier, for instance) having a release tape (not referenced in the figures for simplicity) laminated thereon.

As known to those skilled in the art, such a release tape facilitates detachment and subsequent transfer of the dice140from the carrier C.

As illustrated inFIG.1D, in this step dice140may be flipped (that is, turned over so that their active surface faces the carrier C, e.g., with the active surface facing down) and arranged by allowing for a larger spacing between neighboring dice140as conventionally done for fan-out wafer (panel) level packaging processes-FOW (P) LP.

As illustrated in the following a fan-out region may be used to provide room for a redistribution layer. The actual size of the “fan-out” region may depend on the desired device design.

FIG.1Eis illustrative of a molding step wherein an insulating molding compound16(e.g., an epoxy resin) is molded onto the dice140in order to provide a protective plastic package.

As illustrated inFIG.1F, the wafer/panel (that is, devices140kept together by the molding compound16) is released from the first carrier C and transferred to a second carrier (again indicated with a same reference in the figures for simplicity, being otherwise understood that a different carrier may be used) with the active surface facing up (that is, opposed to the carrier) to facilitate further processing of that surface of the wafer/panel.

FIG.1Gis illustrative of a redistribution layer RL being provided at the active surface of the dice140in the panel. As known to those skilled in the art, a redistribution layer (e.g., RL inFIG.1G) is a metallic (e.g., copper) layer comprising electrically conductive lines/traces used to reroute input/output (I/O) pads of an integrated circuit.

It is noted that vias181are now plated with metal (e.g., copper) in order to provide an electrically conductive path from the die pads on the active surface of the dice140(not visible in the figures for scale reasons) to the redistribution layer RL.

A redistribution layer RL as exemplified inFIG.1Gmay be provided via a photolithographic deposition/growth process, per se conventional in the art. A more detailed description of such a process will be given in the following when describing embodiments of the present description.

A redistribution layer RL as exemplified inFIG.1Gcomprises only one layer; in certain cases, several layers may be provided in order to reroute the die pads to the external pads (the studs12illustrated inFIGS.1H to1J, for instance), each layer being provided via a photolithographic/electroplating deposition process.

FIG.1His illustrative of studs/external pads12being provided on top of the redistribution layer RL. Studs12may be grown via a process similar to the one used to form the redistribution layer RL.

FIG.1Iis illustrative of an insulating film110(e.g., another-possibly different-ABF) laminated on the wafer/panel assembly to provide an insulating/protective layer to the devices.

Alternatively, the protective plastic package may be completed via a second molding step of an insulating molding compound such as an epoxy resin, for instance.

Either option (e.g., laminating a sufficiently thick film or applying a second compression molding layer) facilitates encapsulating device traces and studs.

Film (e.g., ABF) lamination may use a laminator to heat a film foil that is as large as an entire panel, which is deployed over the panel via a combined action of vacuum and pressure. After completion of the package, e.g., via insulating film lamination or resin molding, the wafer/panel may be detached from the carrier.

FIG.1Jis illustrative of a second (final) singulation step wherein a panel/wafer is cut (e.g., via sawing) into individual devices10. Such a second singulation step may be performed after a final plating step of the input/output (I/O) studs12for the purpose of enhancing solderability (on a final substrate such a printed circuit board-PCB—for instance).

As described so far, such manufacturing process-oftentimes referred to as fan-out wafer (panel) level packaging (FOW (P) LP)—is conventional in the art, which makes it unnecessary to provide a more detailed description herein.

Otherwise, the sequence ofFIGS.1A to1Jaims at giving only a schematic description of a conventional manufacturing process.

In particular: one or more steps illustrated inFIGS.1A to1Jcan be omitted, performed in a different manner (with other tools, for instance) and/or replaced by other steps; additional steps may be added; one or more steps can be carried out in a sequence different from the sequence illustrated.

Cases exist where a simpler process is desirable. For example, certain products for the automotive or consumer market may benefit from a simplification of the manufacturing process that translates in lower production costs and shorter processing time.

Solutions as described herein aim at providing a simple and cost-effective manufacturing method of semiconductor devices.

In solutions as described herein, the manufacturing process may be carried out entirely at wafer level.

In solutions as described herein, insulating films laminated on opposed surfaces of a wafer replace a conventional plastic package, thus reducing the size of the device and making unnecessary a molding step.

In solutions as described herein, external pads provided on the active surface of the wafer may be finished with a solderable protective layer.

Solutions as described herein in connection withFIGS.2A to2Kmay optionally be modified as exemplified inFIGS.4A to4Cin order to provide final devices with wettable flanks.

It is otherwise noted that the sequences ofFIGS.2A to2KandFIGS.4A to4Caim at giving only an exemplary representation of a related process.

For instance: one or more steps illustrated inFIGS.2A to2KandFIGS.4A to4Ccan be omitted, performed in a different manner (with other tools, for instance) and/or replaced by other steps; additional steps may be added; one or more steps can be carried out in a sequence different from the sequence illustrated.

The representation inFIGS.2A and2Bis per se identical to the representation inFIGS.1A and1B.

FIG.2Ais again illustrative of an insulating film101laminated on a first (upper in the figure) surface of a semiconductor (silicon, for instance) wafer14having integrated circuits, ICs, already formed therein in a manner known to those of skill in the art so that these can be concurrently processed.

Again, the film101may be, for instance, a film such as an Ajinomoto Build-up Film (ABF), already mentioned in the foregoing.

FIG.2Bis illustrative of opening of vias181′ to the die pads141located at the first active surface of the wafer14. As indicated by LB, vias181′ can be provided via laser ablation at desired locations of the insulating film101.

However, contrary toFIG.1C, the assembly ofFIG.2Bis not “singulated” and is in fact subjected to various types of processing.

For instance, a grinding step as illustrated by G inFIG.2Cmay advantageously be performed in order to reduce the thickness of the wafer14. This step may be useful in reducing in as much as possible the thickness of the final device.

FIG.2Dis illustrative of a second insulating film102laminated on the second surface of the wafer14, opposed to the surface onto which the film101was laminated.

For instance, the second insulating film102may again be a film such as an Ajinomoto Build-up Film (ABF), already mentioned in the foregoing, but not necessarily of the same type of the first insulating film101. For example, a different thickness and/or chemical composition may be envisaged for the second insulating film102.

For instance, the film102may differ from the film101and/or either film101,102can be a mold film used to protect an (e.g., back) side in a semiconductor wafer.

Different types of ABF/mold film can be used as desired, e.g., according to specific requirements.

As illustrated, applying the second insulating film102on the second surface of the wafer14may involve turning over the wafer14as this may facilitate the related processing.

However implemented, laminating insulating films (e.g.,101and102) on both surfaces of the wafer14may facilitate providing a protection to the wafer14(and thus the ICs formed therein) without using of an, e.g., plastics, package (as provided by the molding compound illustrated inFIG.1J, for instance) which involves an additional molding step.

Replacing a conventional package with insulating films (e.g.,101and102) may be advantageous both in terms of simplicity of the assembly flow and final package size.

As it will be described in the following, after the singulation (illustrated inFIGS.2K and4C) of the wafer assembly, final devices20produced according to embodiments of the present description may have the semiconductor material of the wafer14(e.g., silicon) exposed on their lateral surfaces (or, in any case, left uncovered by the films101and102).

That is, as illustrated herein, singulating (e.g., via a blade B) the semiconductor wafer14produces individual semiconductor devices20each having opposed first and second device surfaces (corresponding to the opposed surfaces of the wafer14) having respective portions of the first and second insulating films101,102laminated thereon as well as side surfaces142extending between the opposed first and second device surfaces.

It has been observed that laminating insulating films101,102(only) on the opposed first and second surfaces of the wafer14(and after singulation, of the final device) facilitates providing adequate protection to the ICs comprised in the wafer14(the device20) while, at the same time, facilitating a reduced package dimension.

FIGS.2E to21illustrate steps that can be performed on the assembly ofFIG.2Dhaving insulating films101,102laminated on both its opposed surfaces.

FIG.2Eis illustrative of a (photolithographic) process providing external pads to the ICs in the wafer14by growing metallic (e.g., copper) material on the first (active) surface of the wafer14.

FIG.2Eis illustrative of a growth/deposition (e.g., via sputtering) of a seed layer200on the first insulating film101. As known to those skilled in the art, growing such a seed layer200may comprise, for instance, a first deposition of a Ti layer followed by the deposition of a Cu layer.

A seed layer (e.g.,200) facilitates growing additional metallic (e.g., copper) material via electrolytic/galvanic plating, for instance.

FIG.2Fis illustrative of photoresist material DF provided on the first (active) surface of the wafer14, that is, on the seed layer200thereon.

A dry film DF may be advantageously used for this step; the thickness of the dry film DF may be chosen according to device design in as much as the “height” of the external pads (illustrated inFIG.2Iand referenced therein with the reference12) is determined by the thickness of the dry film DF.

For instance, the thickness of the dry film DF can be selected taking into account a desired thickness (height) for, e.g., copper pads that are grown therein.

FIG.2Gis illustrative of the dry film DF being patterned via laser direct imaging (LDI) and subsequently developed in order to transfer a desired pattern to the dry film DF.

It is noted that such patterning may advantageously replace providing (e.g., via back end of the line or BEOL processes) “redistribution” layer as used in certain conventional device designs to redistribute the pads of the (IC) dice formed in the wafer14.

In solutions as described herein, such a redistribution layer (like the redistribution layer RL illustrated inFIG.1G) can be avoided, with the pattern transferred to the dry film DF (illustrated inFIG.2G) comprising simply openings located at the pads of the dice in the wafer14, and no metallic traces or lines.

Consequently, as illustrated inFIG.2G, the pattern transferred (via a laser beam, LB) to the dry film DF may consist (only) of holes/openings located at vias openings181′.

FIG.2His illustrative of electrically conductive (e.g., metal such as copper) material deposited/grown on the patterned dry film DF, facilitated by the seed layer200. Such a plating step may be performed, for example, via electrolytic/galvanic plating.

Studs or (external) pads12are formed at vias181of the first insulating film101; openings181′ (as illustrated and referenced inFIG.2G, for instance) of the first insulating film101are now plated with conductive material, e.g., copper.

These are referenced with the reference181(no accent any longer) thus providing electrical coupling between the pads of the ICs on the first (active) surface of the wafer14and the studs12.

Dry film DF is stripped and the seed layer200etched away (where it is not covered with the metallic material of the vias181and studs12) resulting in the assembly illustrated inFIG.2I.

FIG.2Jis illustrative of a pads/studs12finishing steps wherein an additional layer300can be deposited on pads12to enhance solderability.

This layer may comprise a Ni layer (e.g., provided via an electroless plating process) and an Au layer (e.g., provided via immersion in a gold salts bath) resulting in what is generally referred to as electroless-nickel immersion-gold (ENIG) finishing.

ENIG finishing, per se conventional in the art, enhances solderability of external pads12and provides a protective layer countering oxidation of external pads12.

Alternatively, the metallic layer300may be an electroless Ni-electroless Pd-immersion Au (ENEPIG) finishing with the same purpose as the ENIG layer (that is, enhanced solderability and protection from oxidation).

FIG.2Killustrates a singulation step wherein the wafer14is finally cut (portioned) into individual devices20via sawing with a blade B, for instance.

Individual devices20as illustrated inFIG.2Kcomprise respective portions of the semiconductor (e.g., silicon) wafer14each having at least one semiconductor dice integrated therein.

A final device20as illustrated inFIG.3may be mounted on a substrate S such as a printed circuit board (PCB) via solder material SM.

To summarize, a device20as illustrated inFIG.3comprises first and second insulating films101,102laminated on opposed first and second surfaces of a portion of a semiconductor wafer14. The device has integrated therein one or more semiconductor dice140having die pads141at the first surface.

Electrically conductive formations12,181are provided towards the die pads141including, e.g., metal such as copper (Cu).

The electrically conductive formations12,181extending in the vias181′ opened (e.g., via laser beam LB) in the first insulating film101laminated on the first surface.

A device20as illustrated inFIG.3comprises side surfaces142extending between the opposed first and second surfaces.

These side surfaces142are left uncovered by the first and second insulating films101,102.

As illustrated inFIG.3, the final devices20may have semiconducting material of the wafer14(e.g., silicon) exposed on their lateral surfaces142. For instance, if not covered otherwise, the semiconductor die140is visible on the side faces142of the device20, insofar as this is “covered” by the films101,102laminated (only) on its first and second opposed surfaces.

That is, as illustrated herein, singulating (e.g., via a blade B) the semiconductor wafer14produces individual semiconductor devices20each having opposed first and second device surfaces (corresponding to the opposed surfaces of the wafer14) having respective portions of the first and second insulating films101,102laminated thereon as well as side surfaces142extending between the opposed first and second device surfaces.

As visible, the side surfaces142are left uncovered by the first and second insulating films101and102. As further visible, the individual semiconductor device20is not encapsulated by a package material other than said first and second insulating films.

As mentioned, laminating insulating films101,102on (only) the opposed first and second surfaces of the device20has been observed to be able to provide an adequate protection to the ICs comprised the device (in the absence of other package material) while, at the same time, maintaining reduced package dimension.

This primarily in comparison to conventional arrangements where a molding compound (e.g., an epoxy resin) is molded onto the device to complete the plastic package thereof, thus covering also the side surfaces (seeFIG.1J, for instance).

The external pads12may be advantageously finished with a ENIG or ENEPIG layer for enhanced solderability and protection (against oxidation, for instance).

The metallic formations (vias181and pads/studs12) may be provided with a photolithographic plating process (as discussed in the foregoing) possibly leaving a seed layer200beneath the metallic formations181,12.

The sequence ofFIGS.4A to4Cillustrates optional processing steps aiming at providing a device20with wettable flanks.

As known to those skilled in the art, wettable flanks are a desirable feature which facilitate the formation of a solder meniscus when mounting (via solder material) a device on the final substrate (e.g., a PCB).

In addition to being beneficial for the integrity/reliability of the solder joint, a solder meniscus facilitates visual checking and testing of solder joints via automated optical inspection (AOI).

FIG.4Aillustrates a partial cut performed (via a first blade B2, for instance) on a semiconductor wafer14having metallic formations181,12formed on the first/active surface thereof. That is,FIG.4Aresults from performing a partial cut on a processed wafer14as illustrated inFIG.2I, the sequence ofFIGS.4A to4Crepresenting an alternative sequence of steps.

The partial cut is performed at the cutting lines CL of the final singulation cut (illustrated inFIG.4C) in order to expose (at the periphery of the device) the lateral surface of pads12that are located at the periphery of the device.

FIG.4Bis illustrative of a pads/studs12finishing steps wherein a ENIG or ENEPIG layer300is deposited on pads12to enhance solderability and provide protection from oxidation. This step is similar to what is illustrated inFIG.2J.

FIG.4Cillustrates a final singulation step wherein the wafer14is cut (e.g., via sawing with a second blade B) into singulated devices20.

A second blade B different from the first blade B2may be used to perform the singulation step illustrated; for example, a second blade B thinner than the first blade B2may be used, this resulting in the “step” (a sort of undercut) illustrated inFIG.4Cand referred therein with the reference WF.

The claims are an integral part of the technical teaching provided in respect of the embodiments.

Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only without departing from the extent of protection. The extent of protection is determined by the annexed claims.