LDMOS transistor double diffused region formation process

Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 9° or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.

FIELD OF THE INVENTION

This invention generally relates to semiconductor devices and methods for their manufacture, and, more particularly, to lateral double diffused metal oxide semiconductor (LDMOS) transistors and methods for their manufacture.

BACKGROUND OF THE INVENTION

Lateral double-diffused metal oxide semiconductor (LDMOS) transistors require that the LDMOS transistors have a low on resistance, a high off resistance, and a large electrical safe operating area. To increase the current handling capability of the LDMOS transistors on an integrated circuit, a number of LDMOS transistors are often tied together forming, for example, multi-fingered LDMOS. With the LDMOS transistors connected in parallel, the current flow can be shared among the various LDMOS transistors. To ensure the proper distribution of current among the various LDMOS transistors, it is important that the threshold voltage (Vt) of the individual LDMOS transistor structures be closely matched.

The threshold voltage (Vt) of the LDMOS transistor is set by the multiple ion implantation processes used to form the transistor channel region. During the multiple ion implantation processes, a patterned photoresist (PR) masking layer is formed over the substrate and the dopant species are implanted through patterned openings formed in the PR masking layer. In forming the LDMOS transistors required for high current applications, a major limitation to obtaining closely matched threshold voltages is the variation in the photoresist sidewall angle of the various openings through which the dopants are implanted. For example, the photoresist sidewall angle is significantly decreased depending on local resist density, such as after the photoresist hard bake step of a conventional photolithography process.

Thus, there is a need to overcome these and other problems of the prior art and to provide methods for forming LDMOS transistors with closely matched threshold voltages.

SUMMARY OF THE INVENTION

According to various embodiments, the present teachings include a method for forming a doped region in a semiconductor. In the method, a hard-bakeless photolithography process can be used to form a photoresist (PR) layer over a semiconductor with the PR layer patterned to have at least one opening. Through each opening of the PR layer, a first dopant species can be implanted into the semiconductor to sequentially form a first doped region, and a second doped region, which is shallower than the first doped region. Through each opening of the PR layer, the second dopant species can further be implanted into the semiconductor to form a third doped region.

According to various embodiments, the present teachings also include a method of forming a double diffused region. First, a hard-bakeless photolithography process can be used to form a photoresist (PR) layer over a semiconductor having at least one opening in the PR layer. Through each opening of the PR layer, a first doped region can be formed by implanting a boron-containing species into a region of the semiconductor in a high energy tool; a second doped region that is shallower than the first doped region can be formed by implanting a boron-containing species into the semiconductor region in a reduced energy tool; and a third doped region can be formed by implanting an arsenic-containing species into the semiconductor region in a reduced energy tool. The semiconductor can then be thermally annealed.

According to various embodiments, the present teachings further include a method for forming a LDMOS transistor. In this method, a deep n-well region can be formed in an epitaxial layer on a semiconductor substrate. A patterned PR layer with at least one opening can then be formed over the deep n-well region using a hard-bakeless photolithography process. Through each opening of the patterned PR layer, first, a boron species can be implanted into the deep n-well region at a high energy; second, the boron species can be implanted into the deep n-well region at a reduced energy and with an implant angle of about 9° or higher; and, third, an arsenic species can be implanted into the deep n-well region at a reduced energy. A plurality of isolation structures can then be formed in the deep n-well region followed by the formation of a gate dielectric layer on the deep n-well region.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present embodiments (exemplary embodiments) of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the invention. The following description is, therefore, merely exemplary.

Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer (i.e., PR profile). The multiple ion implantation processes can be performed in a sequence of, for example, forming a first doped region having a first conductivity using a high energy; forming a second doped region having a first conductivity using a reduced energy; and forming a third doped region having a second conductivity using a reduced energy. In addition, during the implantation of the second doped region (having a first conductivity), the ion implant angle, for example, a boron implant angle, can be increased, e.g., about 9° or higher, to make the implantation processes less sensitive to the PR profile. In various embodiments, the doped region can be, for example, a double diffused region used in transistor devices such as LDMOS transistors.

As used herein, the term “hard-bakeless photolithography process” refers to a photolithography process that removes the hard-bake step from a conventional photolithography process. In general, a conventional photolithography process can include, for example, forming a PR layer on a substrate such as a wafer, soft-baking the PR coated wafer to drive off excess solvent, exposing the PR layer using a pattern of intense light, developing the PR layer and removing some of the PR by, for example, a chemical solution, and hard-baking the resulting wafer to solidify the remaining PR and to make a more durable protecting layer for such as future ion implantation, wet chemical etching and/or plasma etching. By removing the photoresist hard-bake step, i.e., using the “hard-bakeless photolithography process”, the patterned PR layer can be formed having a sidewall angle of, for example, about 85° to about 90°, such that lot-to-lot, wafer-to-wafer and across wafer Vt variation of resulting transistor devices can be avoided.

The hard-bakeless photolithography process with the hard-bake step removed can be combined with the multiple ion implantation processes to form the disclosed doped region. The multiple ion implantation process can be performed in the sequence of, for example, high energy ion implantation for the first doped region; low energy ion implantation having an increased ion implant angle for the second doped region; and low energy ion implantation for the third doped region. This is because the PR hard bake is not necessary for the high energy implantation of the first region. But this high energy can facilitate the patterned PR layer to be cured to a certain extent to reduce out gassing of the PR layer during the subsequent implantations, where the high-energy cured patterned PR layer can be used as an implantation mask. In the subsequent shallow (second) region implantation, the increased ion implant angle, for example, about 9° or higher, can be used to compensate the implant tail from the previous high energy implantation and/or to decrease the Vt sensitivity to the profile of the patterned PR layer and thus to control Vt and Vt variations of the resulting transistor devices.

FIG. 1depicts an exemplary method100for forming a doped region in a semiconductor in accordance with the present teachings. More specifically, the doped region can be formed in the semiconductor using multiple ion implantation processes through a patterned PR layer formed by the hard-bakeless photolithography process.

At110, a patterned photoresist (PR) layer can be formed on a semiconductor. The patterned PR layer can include one or more openings, through which various dopant species can be implanted into desired regions, for example, a doped deep well (Dwell) region for LDMOS devices, of the underlying semiconductor. In an exemplary embodiment where the patterned PR layer has a single opening, the resulting semiconductor device can be used to form a single-fingered LDMOS transistor. In another exemplary embodiment where the patterned PR layer has multiple openings with each opening formed on one of the doped regions, the resulting semiconductor device can be used to form a multi-fingered LDMOS transistor. In various embodiments, a LDMOS transistor can include both single-fingers and multi-fingers.

The patterned PR layer can be formed using, for example, the hard-bakeless photolithography process. The patterned PR layer can have a thickness of, for example, on the order of about 1.8 μm to about 4 μm, in order to effectively mask the dopant species that can be subsequently implanted into the underlying semiconductor. In an exemplary embodiment, the patterned PR layer can be about 2 μm to about 3 μm thick, for example, about 2.5 μm. In various embodiments, an oxide layer can be formed between the patterned PR layer and the semiconductor.

At120, a first ion implantation of a first dopant species can be performed through each opening of the patterned PR layer and into the doped Dwell region of the semiconductor. The first dopant species can include, for example, a boron-containing species or any other light mass implant species including, for example, elements in the periodic table below the element silicon. The first ion implantation of the first dopant species can be performed using a high energy, for example, using energies on an order of several hundreds of KeV for the first region. For example, a 1-3 μm deep boron implantation into a silicon can require an acceleration energy of approximately 300-600 KeV. The boron ions can be accelerated through the semiconductor until these ions lose energy and become implanted.

In various embodiments, the first ion implantation of the first dopant species (e.g., boron) can form a first region in the doped Dwell region having a first conductivity type, which can be opposite to the conductivity type of the doped Dwell region. For example, the first region can be a P-type region formed in an N-type Dwell region. In various embodiments, the use of P and N type semiconductor regions can be reversed for the resulting semiconductor structures/devices. For example, the first region can be an N-type semiconductor region and the doped Dwell region can be a P-type semiconductor region, and vice versa.

At130, a second ion implantation of the first dopant species can be performed through each opening of the patterned PR layer and into the doped Dwell region of the semiconductor. A second region that is shallower than the first region can then be formed in the doped Dwell region. The second region can be implanted at a reduced energy and in a different implant tool as compared with the implantation for the fist region, yet have the same conductivity as to that of the first region in the doped Dwell region. For example, the second region can be formed by implanting a boron-containing species in a mid-current tool.

In various embodiments, the exemplary shallow boron implantation can include an increased implant angle, for example, about 9° or higher as compared with a general implant angle for such as about 2° in the art. The higher shallow implant angle as disclosed herein can compensate the implant tail from the previous high energy boron implantation. As a result, the higher shallow implant angle can provide the resulting semiconductor transistor (e.g., a LDMOS) with a higher threshold voltage and with less sensitivity to the profile of the patterned PR layer.

At140, a third region can be formed by implanting a second dopant species through each opening of the patterned PR layer and into the doped Dwell region of the semiconductor. The second dopant species can include, for example, an arsenic-containing species or any other heavy mass implant species including, for example, elements in the periodic table above the element silicon. In various embodiments, the third region can have a second conductivity type opposite to that of both the first and the second regions in the doped Dwell region. For example, the third region can be an N-type region and the first or the second region can be a P-type region formed in an N-type Dwell region.

FIGS. 2A-2Fdepict an exemplary LDMOS device having a doped region fabricated using the method100described inFIG. 1in accordance with the present teachings. Specifically,FIGS. 2A-2Fshow cross-sectional views for the exemplary LDMOS device at various stages of fabrication. It should be readily apparent to one of ordinary skill in the art that the LDMOS device depicted inFIGS. 2A-2Frepresents a generalized schematic illustration and that other regions/wells/layers can be added or existing regions/wells/layers can be removed or modified.

InFIG. 2A, the exemplary LDMOS device can include a semiconductor202including a substrate205and an epitaxial layer210having a doped Dwell220, an pad oxide layer240, and a patterned PR layer250having an opening255. As shown, the LDMOS device can provide a layered structure having the patterned PR layer250formed over the pad oxide layer240over the semiconductor202(i.e., the epitaxial layer210on the substrate205).

The semiconductor202can include the epitaxial layer210formed on a substrate205using known semiconductor manufacturing methods. It should be noted that the formation of an epitaxial layer (e.g.,210) on a semiconductor substrate (e.g.,205) can be optional, and the method100can be used to form the exemplary LDMOS device on any suitable semiconductor substrate (e.g.,205) without the epitaxial layer (e.g.,210). In other words, the semiconductor202can be a semiconductor substrate (e.g.,205) that includes a doped Dwell (e.g.,220) in accordance with various embodiments.

The doped Dwell220can be formed inside the semiconductor202, for example, inside the epitaxial layer210or inside the substrate205if there is no epitaxial layer involved. The doped Dwell220can be formed after the formation of the overlaid pad oxide layer240on the semiconductor202. In various embodiments, the doped Dwell220can be formed having an opposite conductivity to, for example, the epitaxial layer210. In an exemplary embodiment where the epitaxial layer210is P-type, the doped Dwell220can be N-type. Similarly, an N-type epitaxial layer210can require the formation of a P-type Dwell220.

The pad oxide layer240can be formed on the semiconductor202following the formation of the epitaxial layer210and prior to the formation of the doped Dwell220. In various embodiments, the pad oxide layer240can be used to reduce the damage caused by the subsequent implantation processes.

The patterned PR layer250can be formed over the pad oxide layer240after the formation of the doped Dwell220. The patterned PR layer250can be formed using the hard-bakeless photolithography process with a thickness of about 1.8 μm to about 4 μm. In an additional example, the thickness of the patterned PR layer250can be about 2 μm to about 3 μm, such us, about 2.5 μm.

The patterned PR layer250can include a single opening255as illustrated inFIG. 2A, which can be used to form a single-fingered LDMOS transistor. However, the semiconductor devices and the methods for their manufacturing should not be limited to PR layers having a single opening. For example, if a multi-fingered LDMOS transistor is required, the doped Dwell220(e.g., a deep n-well) and the patterned PR layer250illustrated inFIG. 2Acan be repeated multiple times along a line in the epitaxial layer210of the semiconductor202.

Still referring toFIG. 2A, the patterned PR layer250can further include a sidewall angle257(also referred herein as “PR profile angle” or “PR profile sidewall angle”), which is an angle made by an edge of the patterned PR layer250that is adjacent to the opening255with the surface of the underlying layer, for example, the pad oxide layer240. In a conventional photolithography process that includes a hard-bake step for forming the patterned PR layer, the sidewall of the PR layer250can be pulled back after the hard-bake and thus the sidewall angle257can be reduced. This reduction can lead to penetration of high-energy boron species into masked regions of the doped deep region beneath the patterned PR layer. Further, because the change of angles can be different across the different fingers, for example, for multi-fingered LDMOS transistors, large variations in LDMOS threshold voltages Vt can result. By using the disclosed hard-bakeless photolithography process to form the patterned PR layer250, such Vt delta (i.e., variations of LDMOS Vt) can be avoided. In various embodiments, the PR sidewall angle257can be in a range of about 85° to about 90°. Table 1 depicts Vt delta of exemplary LDMOS devices formed using the hard-bakeless photolithography process (i.e., with PR hard-bake step removed) as compared to that using a conventional photolithography process with PR hard-bake step involved.

In this example, the Vt delta can be a threshold voltage difference between a single-finger and a double-finger of each of the exemplary LDMOS devices (i.e., D45H_VTL, D45HMVTL, D45H_VTL, and D45HMVTL). As shown in Table 1, the threshold voltage difference (i.e., Vt delta) for each device fabricated by the hard-bakeless photolithography process can be about 0.047 V, which is reduced for more than about 4 times as compared with each LDMOS device fabricated by the conventional photolithography process having an exemplary Vt delta of about 0.204 V. Because of the use of the hard-bakeless photolithography process, the threshold voltage mismatches can be significantly reduced. For each device listed in table 1, the exemplary shallow boron implant angle is about 2 degree and a plurality of data, for example, about 18 data or more, are taken for the purpose of statistic comparison.

Referring toFIG. 2B, the exemplary LDMOS device can further include a first doped region232formed in the doped Dwell220through the opening255of the patterned PR layer250. The first doped region232can be doped using a high energy, for example, on the order of several hundreds KeV in a MeV tool. In various embodiment, the high energy implantation can be performed by implanting a boron-containing species or other light species at energies of, for example, about 300 KeV to about 600 KeV, and doses of, for example, about 1×1012cm−2to about 1×1014cm−2. In an exemplary embodiment, the high energy boron ion implantation of the first doped region232can be performed at an energy of about 0.375 MeV and a dose of about 2×1013cm−2in a MeV tool. In various embodiments, the first doped region232in the doped Dwell220can have opposite conductivities with one another. For example, when the doped Dwell220is an N-type Dwell, the first doped region232can be a P-type doped with the exemplary boron-containing-species. On the other hand, the first doped region232can be doped with, for example, arsenic-containing-species having an N-type conductivity in a P-type Dwell220.

InFIG. 2C, following the formation of the first doped region232in the doped Dwell220, the exemplary LDMOS device can further include a second doped region234, i.e., a shallow doped region, formed using the patterned PR layer250as a mask. The second (shallow) doped region234can have the same conductivity as that of the first doped region232. For example, the second (shallow) doped region234can be doped with boron-containing species or other light dopants to provide a P-type region, when the first doped region232is a P-type region. The second doped region234can be doped by, for example, an ion implantation process, using, for example, a reduced energy, such as, about 20 KeV to about 200 KeV in a mid-current tool. The second doped region234can also be doped with an exemplary dose of about 1×1013cm−2to about 5×1014cm−2.

In an exemplary embodiment, the ion implantation process of the second doped region234using a low energy and a high ion dosage can dominantly facilitate to set the threshold voltage (Vt) of the resulting LDMOS transistor. In various embodiments, the exemplary shallow ion (e.g., boron) implantation can be performed with a desired implant angle, such as, for example, about 9° or higher.FIG. 3Ais a schematic showing an exemplary shallow ion implant angle360for forming a second doped region334in a Dwell320through an opening355of a patterned PR layer350in accordance with the present teachings. The PR profile can be determined by the sidewall angle357, which is defined by the edge of the patterned PR layer350and the opening355making with the surface of the underlying layer340.

Various shallow boron implant angles360can be used.FIG. 3Bdepicts exemplary results showing the effect of the shallow boron implant angle on the threshold voltage (Vt) dependence upon the PR profile in accordance with the present teachings. As shown,FIG. 3Bincludes curves302,304, and306for a shallow boron implant angle (e.g.,360) of about 2°, 9° and 20°, respectively. As indicated, the resulting threshold voltage Vt for the 20° implant angle (see the curve306) is greater than that for the 9° implant angle (see the curve304), which is greater than that for the 2° implant angle (see the curve302). That is, a higher titled shallow boron implant angle360can result a higher Vt. It is also noted that, when the PR profile sidewall angle357is higher than 86°, the higher titled shallow boron implant angle360can decrease the Vt sensitivity to Dwell PR profile. This solves the problem in the prior art that the Vt of LDMOS devices strongly depends on the Dwell PR profile if the PR sidewall angle is above 80°.

Furthermore, when an increased shallow boron implant angle360(e.g., about 9° or higher) is used, the across-wafer Vt variations of the resulting LDMOS devices can also be improved significantly.FIG. 4depicts an exemplary result showing the effect of shallow boron implant angles (e.g.,360inFIG. 3A) on the across-wafer Vt variations for LDMOS devices in accordance with the present teachings. Specifically,FIG. 4includes three sets of devices shown as410,420and430formed using various shallow boron implant angles (e.g.,360inFIG. 3A) of about 2°, 9°, and 12°, respectively. As shown, when the shallow boron implant angle is increased, for example, from about 2° to about 12°, the across-wafer Vt variations for LDMOS devices can be decreased and thus Vt mismatches between, for example, single-fingered LDMOS and multi-fingered LDMOS can be decreased.

Referring toFIG. 2D, following the formation of the second doped region234in the doped Dwell220, the exemplary LDMOS device can further include a third doped region236formed through the opening255using the patterned PR layer250as a mask. The third doped region236can have an opposite conductivity as to that of both the first and the second doped regions232and234. For example, the third doped region236can be doped with arsenic-containing species or other heavy dopants to provide an N-type region, when the first and the second doped regions232and234are P-type regions. The third doped region236can be doped by, for example, an ion implantation process, using an exemplary energy at about 120 KeV to about 200 Kev in a mid-current tool and an exemplary dose at about 1×1013cm−2to about 2×1014cm−2.

InFIG. 2E, the exemplary LDMOS device can be completed using technologies and methods known to one of the ordinary skill in the art. For example, the LDMOS device can further include isolation regions270, double defused regions233,235, and237, a second patterned PR (PR) layer280and the regions282and286.

The isolation regions270can be formed following the multiple ion implantation processes as described inFIGS. 2B-2D. However, one of ordinary skill in the art will understand that the isolation regions270can be formed in the doped Dwell region220(seeFIG. 2A) prior to the multiple ion implantation processes described inFIGS. 2B-2D. In various embodiments, the isolation regions270can be formed using known isolation structures, such as, for example, local oxide isolation structures (LOCOS) or STI (shallow trench isolation) structures.

The double defused regions233,235, and237can then be formed following the formation of the isolation regions270. In various embodiments, the double defused regions233,235, and237can be formed prior to the formation of the isolation regions270that includes the LOCOS structures or the STI structures.

In an exemplary embodiment where LOCOS structures (seeFIG. 2E) are used for the isolation regions270, the LOCOS can be formed by first removing patterned PR layer250or any addition processes, and then forming, for example, patterned silicon nitride layers (not shown) on the pad oxide240. The patterned silicon nitride layers can be formed in those areas where no LOCOS isolation structures270are desired. Following the formation of the patterned silicon nitride layers, the LOCOS structures270can be formed using, for example, thermal oxidation. During the exemplary LOCOS thermal oxidation process, the patterned silicon nitride layers can block the oxidation process in the regions of the epitaxial layer210that underlies the layers. The thermal oxidation process used to form the LOCOS structures270can take place at temperatures, for example, above 800° C.

In various embodiments, this LOCOS thermal oxidation process can be used as a thermal annealing process to form the double diffused regions233,235, and237by diffusing the implanted exemplary boron and arsenic species. Generally, the boron species have a temperature dependent intrinsic diffusivity constant that is almost an order of magnitude greater than that of the arsenic species. The lateral diffusion of the boron species (e.g., in the first and the second doped regions232and234) that occurs during the LOCOS thermal oxidation process can therefore be greater than that of the arsenic species (e.g., in the third doped region236). The difference in lateral diffusion of the boron and arsenic species can result in the formation of the double diffused regions233,235, and237. In some embodiments, the double diffused regions233,235and237can be formed prior to the formation of the LOCOS isolation regions by, for example, an independent thermal annealing process having a temperature of, for example, about 800° C. or higher.

In another exemplary embodiment where STI structures (not shown) are used for the isolation regions270, the double diffused regions233,235, and237can be formed after the formation of the STI isolation regions by, for example, an independent thermal annealing cycle (or cycles), using a temperature of, for example, about 800° C. to about 1200° C. Alternatively, the double diffused regions233,235, and237can be formed prior to the formation of the STI insolation regions (not shown) by the exemplary independent thermal annealing cycle (or cycles) at a temperature of about 800° C. to about 1200° C.

In this manner, the diffused region237, for example, an N-type diffused region in the final LDMOS device, can be used as the source of the transistor. And the inversion channel of the transistor can be formed in the exemplary P-type diffused regions233and235.

The second patterned PR layer280can be formed after the formation of the isolation structures270and the double diffused regions233,235and237. The second patterned PR layer280can be used as an ion implantation mask for the subsequent ion implantation process.

The regions282and286can function as the drain regions of the resulting LDMOS transistor and can be, for example, N-type regions. Suitable N-type dopant species can be implanted use the second patterned PR layer280as an ion implantation mask. During this implantation process, N-type dopant species can also be implanted into the source region237to further increase the n-doping concentration.

InFIG. 2F, the exemplary LDMOS device can further include a gate dielectric layer290, and doped polysilicon structures292and294to form LDMOS transistors297and299. The gate dielectric layer290can be formed above the double diffused regions233,235, and237. The gate dielectric layer290can include a material selected from the group consisting of silicon oxide, nitrogen-containing silicon oxide, and silicon nitrogen. The doped polysilicon structures292and294can be formed using known processing methods and function as the gate electrodes for the LDMOS transistors297and299, respectively. The LDMOS transistors297and299can share a common source region237. The LDMOS transistor297can also include the gate electrode region292and the drain region290. Similarly, in addition to the common source region237the LDMOS transistor299can also include the gate electrode296and the drain region295.