Analog-to-digital converter with offset calibration

An analog-to-digital converter (ADC) circuit including error correction circuitry for correcting offset drifts in an ADC, such as a successive approximation register (SAR) ADC. The offset drifts can be reduced, such as by sampling the offset following an analog-to-digital conversion and subsequently providing an error correction signal based on the sampled offset.

FIELD OF THE DISCLOSURE

The present disclosure relates to systems and methods for providing error correction in an analog-to-digital converter (ADC).

BACKGROUND

Certain analog-to-digital converters (ADCs) include a digital-to-analog converter (DAC) that can sample an analog input voltage and provide a digital output. ADCs can be used in a wide variety of applications including audio and video recording, digital signal processing, and scientific instruments including radar, temperature sensors, and light intensity sensors.

SUMMARY OF THE DISCLOSURE

Analog-to-digital converters (ADCs), such as successive approximation register (SAR) ADCs can suffer from offset drift. Such offset drift can be due to capacitor mismatch drift, comparator offset drift, and pedestal effect error. Certain approaches for reducing or minimizing capacitor mismatch drift can include dynamic element matching and/or background calibration. Certain approaches for reducing or minimizing comparator offset drift can include auto-zeroing the comparator before using it. Pedestal effect error can arise from clock feedthrough or channel charge injection from one or more field-effect transistor (FET) switches used with a switched-capacitor DAC, and approaches for reducing or minimizing such pedestal error are described herein. In a high resolution, high accuracy SAR ADC, it can be challenging to reduce offset drifts to a level of less than a least significant bit (LSB) of the SAR ADC. The present inventors have recognized a need for providing an error correction signal, such as to reduce an offset drift of the SAR ADC, such as to reduce conversion errors at the output of the SAR ADC.

In an aspect, the disclosure can feature a method of providing error correction in an analog-to-digital conversion system. The method can include sampling a first analog signal, such as to introduce a first additive error to the sampled first analog signal. The method can also include converting the sampled first analog signal to a first digital value, such as to introduce a second additive error to the first digital value. The method can also include providing the first digital value to a first digital-to-analog converter (DAC). The method can also include converting the first digital value to a second analog signal, and the second analog signal can include the first analog signal and the first and second additive errors. The method can also include sampling the second analog signal, such as to introduce a third additive error to the sampled second analog signal. The method can also include converting the sampled second analog signal to a second digital value, such as to introduce a fourth additive error to the second digital value. The method can also include providing a digital error correction signal, such as that based on the difference between the first digital value and the second digital value. The first analog to digital converter (ADC) can convert the sampled first analog signal to the first digital value and a second ADC can convert the sampled second analog signal to the second digital value. An ADC can convert the sampled first analog signal to the first digital value, store the first digital value in a register, and then convert the sampled second analog signal to the second digital value. The method can also include digitally filtering the digital error correction value. The method can also include providing the digitally filtered error correction value to a second DAC. The method can also include converting the digitally filtered error correction value to an analog error correction signal. The method can also include adding the analog error correction signal to the sampled first analog signal. The first additive error and the third additive error can include contributions from a sampling pedestal effect.

In an aspect, the disclosure can feature a method of providing error correction in an analog-to-digital conversion system. The method can include sampling a first analog signal onto the first CDAC, such as to introduce a first additive error to the sampled first analog signal. The method can also include converting the sampled first analog signal into a first digital value, such as to introduce a second additive error to the first digital value. The method can also include storing the first digital value in the first CDAC, such as to produce a second analog signal. The method can also include sampling the second analog signal, such as to introduce a third additive error to the sampled second analog signal. The method can also include converting the sampled second analog signal into a second digital value, such as to introduce a fourth additive error to the second digital value. The method can also include providing a corrected digital value, such as that based on the difference between the first digital value and the second digital value. The method can also include providing a digital error correction value to the input of the first CDAC, such as to reduce an additive error introduced by sampling. The method can also include loading an upper portion of the first CDAC with a digital value, such as that based on the conversion of the first analog signal to a first digital value, then converting the second analog signal to a second digital value using a lower portion of the first CDAC. The method can also include providing a digital error correction value to the input of the lower portion of the first CDAC, such as to reduce an additive error introduced by sampling. A second CDAC can be coupled to the first CDAC and converting the second analog signal to a second digital value can be performed using the second CDAC. The method can also include providing a digital error correction value to the input of the second CDAC, such as to reduce an additive error introduced by sampling. The first additive error and the third additive error can include contributions from a pedestal effect.

In an aspect, the disclosure can feature an analog-to-digital conversion system for converting an analog signal to a digital value and providing error correction. The system can include a first capacitor digital-to-analog converter (CDAC) that can be configured to sample a first analog signal such as to introduce a first additive error to the sampled first analog signal. The system can also include an analog-to-digital converter (ADC) that can be configured to convert the sampled first analog signal to a first digital value, such as to introduce a second additive error to the first digital value. The system can also include a second CDAC configured to sample a third additive error, such as that created by the closing and re-opening of a sampling switch, and the ADC can convert the sampled third additive error to a second digital value, such as to introduce a fourth additive error to the second digital value. The system can also include a summation circuit that can be configured to provide a corrected ADC digital value, such as that based on the difference between the first digital value and the second digital value. The second CDAC can be further configured to receive an error correction value, such as that based on digitally filtered second digital values. The first additive error can be approximately equal to the third additive error and the second additive error can be approximately equal to the fourth additive error. The first CDAC can include capacitive elements corresponding to n digital bits and the second CDAC can include capacitive elements corresponding to m digital bits, and n can be greater than m.

In an aspect, the disclosure can feature an analog-to-digital conversion system for converting an analog signal to a digital value and providing error correction. The system can include a capacitor digital-to-analog converter (CDAC) that can be configured to sample a first analog signal, such as to introduce a first additive error to the sampled first analog signal. The system can also include an analog-to-digital converter (ADC) that can be configured to convert the sampled first analog signal to a first digital value, such as to introduce a second additive error to the first digital value. A lower portion of the CDAC can then be re-configured to sample a third additive error, such as that created by the closing and re-opening of a sampling switch. The ADC can convert the sampled third additive error to a second digital value, such as to introduce a fourth additive error to the second digital value. The system can also include a summation circuit that can be configured to provide a corrected ADC digital value, such as that based on the difference between the first digital value and the second digital value. The lower portion of the CDAC can be further configured to receive an error correction value, such as that based on digitally filtered second digital values. The first additive error can be approximately equal to the third additive error and the second additive error can be approximately equal to the fourth additive error.

Further features of the disclosure are provided in the detailed description and the appended claims, which features may optionally be combined with each other in any permutation or combination, unless expressly indicated otherwise elsewhere in this document.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE DISCLOSURE

Analog-to-digital converters (ADCs), such as successive approximation register (SAR) ADCs can sample an analog input voltage and provide a digital output. Certain SAR ADCs can suffer from offset drift. Such offset drift can be due to capacitor mismatch drift, comparator offset drift, and pedestal error. In a high resolution, high accuracy SAR ADC, it can be challenging to reduce offset drifts to a level of less than a least significant bit (LSB) of the SAR ADC. The present inventors have recognized a need for providing an error correction signal, such as to reduce an offset drift of the SAR ADC, such as to reduce conversion errors at the output of the SAR ADC.

FIG. 1shows a functional block diagram of an example of an analog-to-digital converter (ADC) circuit and error correction circuitry100. The ADC circuit and error correction circuitry100can include a switch102, a sample and hold circuit105, a first ADC circuit115, a digital-to-analog converter (DAC) circuit125, a second ADC circuit130, and a summation circuit140. The switch102can provide a connection from an analog input voltage (Vin) to an input of the sample and hold circuit105. The switch102can also provide a connection from the output of DAC circuit125to the input of the sample and hold circuit105. The output of the sample and hold circuit105can be connected to the first ADC circuit115and the second ADC circuit130. The first ADC circuit115can be connected to the input of the DAC circuit125and to an input of the summation circuit140. The second ADC circuit130can be connected to an input of the summation circuit140. During operation, the switch102can connect an analog input voltage signal (Vin) to the input of the sample and hold circuit105. The sample and hold circuit105can introduce an additive error represented conceptually at110, such as that due to charge injection onto the sampled analog input voltage signal. In an example, the analog input voltage signal can be 1V and the sample and hold circuit can introduce and additive error of 0.1V, such as which can provide for a sampled analog input voltage signal of 1.1 V where the additive error of 0.1V introduced by the sample and hold circuit can add to the analog input voltage signal. The sampled analog input voltage signal and the additive error110introduced by the sample and hold circuit105can be provided to the input of the first ADC circuit115. The first ADC circuit115can convert the sampled analog input voltage signal and the additive error110introduced by the sample and hold circuit105into a first digital value. The first digital value can include an additive error represented conceptually at135A introduced by the ADC circuit115, such as during the analog-to-digital conversion process. The first digital value can be provided to the input of the DAC circuit125. The DAC circuit125can convert the first digital value into a first analog voltage that includes the sampled analog input voltage, the additive error110introduced by the sample and circuit105, and the additive error135A introduced by the first ADC circuit115. The switch102can then be activated, such as to connect the first analog voltage to the input of the sample and hold circuit105. The sample and hold circuit105can introduce an additional additive error110, such as due to charge injection onto the sampled first analog voltage, and the sampled first analog voltage and the additional additive error110introduced by the sample and hold circuit105can be provided, such as to the input of the second ADC circuit130. The second ADC circuit130can convert the sampled first analog voltage and the additional additive error110introduced by the sample and hold circuit105into a second digital value. The second digital value can include two additive errors110, such as introduced by the sample and hold circuit105, and two additive errors represented conceptually by135A-B, such as respectively introduced by the first ADC circuit115and the second ADC circuit130. The second digital value can be subtracted from the first digital value, such as by the summation circuit140. Based on the subtraction, an error correction signal can be provided at the output of the summation circuit140, and the error correction signal can include an additive error110such as that introduced by the sample and hold circuit105and an additive error135A-B, such has that introduced by the first ADC circuit115or the second ADC circuit130. The error correction signal can then be subtracted from the first digital value, such as to provide an error corrected analog-to-digital conversion of the analog input voltage signal (e.g., the first digital value where the additive errors such as those due to the sample and hold circuit105and the ADC circuit115have been subtracted). As described below with respect toFIG. 3, the error correction signal can be digitally filtered and provided to a second DAC and the digitally filtered error correction signal can be converted to an analog error correction signal for providing error correction in an analog-to-digital conversion, such as that using ADC circuit and error correction circuitry100. In an example, the sample and hold circuit can include a capacitor and a switch. In the example, the switch can close such as to connect a voltage source to the capacitor, such as which can charge the capacitor to a voltage of the voltage source (e.g., 2V). After the capacitor has been charged to the voltage, the switch can be opened and the capacitor can remain charged. In an example, the summation circuit140can include an operational amplifier and a network of resistors. In an example, the summation circuit140can include a digital adder. In the example, the non-inverting terminal of the operational amplifier can be connected through a first resistor to a first voltage, and the inverting terminal of the operational amplifier can be connected through a second resistor to a second voltage. A third resistor can be connected from the non-inverting terminal of the operational amplifier to ground and a fourth resistor can be connected from the inverting terminal of the operational amplifier to an output terminal of the operational amplifier. In the example, the voltage at the output of the operational amplifier can be proportional to the difference between the first voltage and the second voltage.

FIG. 2shows a functional block diagram of an example of an analog-to-digital converter (ADC) circuit and error correction circuitry200. The ADC circuit and error correction circuitry200can include a switch202, a sample and hold circuit205, a first ADC circuit215, a digital-to-analog converter (DAC) circuit225, register circuit230, and a summation circuit240. The switch202can provide a connection from an analog input voltage to an input of the sample and hold circuit205. The switch can also provide a connection from the output of DAC circuit225to the input of the sample and hold circuit205. The output of the sample and hold circuit205can be connected to the first ADC circuit215. The first ADC circuit215can be connected to in input of the register circuit230, an input of the DAC225, and to an input of the summation circuit240. The output of the register circuit230can be connected to an input of the summation circuit240. During operation, the switch202can connect an analog input voltage signal to the input of the sample and hold circuit205. The sample and hold circuit205can introduce an additive error represented conceptually at210, such as due to charge injection onto the sampled analog input voltage signal, and the sampled analog input voltage signal and the additive error210introduced by the sample and hold circuit205can be provided to the input of the first ADC circuit215. The first ADC circuit215can convert the sampled analog input voltage signal and the additive error210introduced by the sample and hold circuit205into a first digital value. The first digital value can include an additive error represented conceptually at235introduced by the ADC circuit215, such as during the analog-to-digital conversion process. The first digital value can be provided to the input of the register circuit230and to the input of the DAC circuit225. The register circuit230can store the first digital value at an output of the register circuit230and provide the first digital value to an input of the summation circuit240. The DAC circuit225can convert the first digital value into a first analog voltage that includes the sampled analog input voltage, the additive error210introduced by the sample and circuit205, and the additive error235introduced by the first ADC circuit215. The switch202can then be activated, such as to connect the first analog voltage to the input of the sample and hold circuit205. The sample and hold circuit205can introduce an additional additive error210, such as due to charge injection onto the sampled first analog voltage, and the sampled first analog voltage and the additional additive error210introduced by the sample and hold circuit205can be provided, such as to the input of the first ADC circuit215. The first ADC circuit215can convert the sampled first analog voltage and the additional additive error210introduced by the sample and hold circuit205into a second digital value. The second digital value can include two additive errors210, such as introduced by the sample and hold circuit205, and two additive errors235, such as introduced by the first ADC circuit215. The second digital value can be subtracted from the first digital value, such as by the summation circuit240. Based on the subtraction, an error correction signal can be provided at the output of the summation circuit240, and the error correction signal can include an additive error210such as that introduced by the sample and hold circuit205and an additive error235, such has that introduced by the first ADC circuit215. The error correction signal can be digitally filtered (e.g., such as shown inFIG. 3) and provided to a second DAC and the digitally filtered error correction voltage signal can be converted to an analog error correction signal for providing error correction in an analog-to-digital conversion, such as that using ADC circuit and error correction circuitry200.

FIG. 3shows a functional block diagram of an analog-to-digital converter (ADC) circuit and error correction circuitry300. The ADC circuit and error correction circuitry300can include a switch302, a sample and hold circuit305, a first ADC circuit315, a digital-to-analog converter (DAC) circuit325, a second ADC circuit330, a summation circuit340, digital filter350, a second DAC355, and a summation circuit360. The switch302can provide a connection from an analog input voltage to an input of the sample and hold circuit305. The switch can also provide a connection from the output of DAC circuit325to the input of the sample and hold circuit305. The output of the sample and hold circuit305can be connected to the first ADC circuit315, the second ADC circuit330, and the summation circuit360. The first ADC circuit315can be connected to in input of the DAC circuit325and to an input of the summation circuit340. The second ADC circuit330can be connected to an input of the summation circuit340. The output of the summation circuit340can be connected to an input of the digital filter350. The output of the digital filter350can be connected to the input of the second DAC355. The output of the second DAC355can be connected to the summation circuit360. During operation, the switch302can connect an analog input voltage signal to the input of the sample and hold circuit305. The sample and hold circuit305can introduce an additive error represented conceptually at310, such as due to charge injection onto the sampled analog input voltage signal, and the sampled analog input voltage signal and the additive error310introduced by the sample and hold circuit305can be provided to the input of the first ADC circuit315. The first ADC circuit315can convert the sampled analog input voltage signal and the additive error310introduced by the sample and hold circuit305into a first digital value. The first digital value can include an additive error represented conceptually at335A introduced by the ADC circuit315, such as during the analog-to-digital conversion process. The first digital value can be provided to the input of the DAC circuit325. The DAC circuit325can convert the first digital value into a first analog voltage that includes the sampled analog input voltage, the additive error310introduced by the sample and circuit305, and the additive error335introduced by the first ADC circuit315. The switch302can then be activated, such as to connect the first analog voltage to the input of the sample and hold circuit305. The sample and hold circuit305can introduce an additional additive error310, such as due to charge injection onto the sampled first analog voltage, and the sampled first analog voltage and the additional additive error310introduced by the sample and hold circuit305can be provided, such as to the input of the second ADC circuit330. The second ADC circuit330can convert the sampled first analog voltage and the additional additive error310introduced by the sample and hold circuit305into a second digital value. The second digital value can include two additive errors310, such as introduced by the sample and hold circuit305, and two additive errors represented conceptually by335A-B, such as respectively introduced by the first ADC circuit315and the second ADC circuit330. The second digital value can be subtracted from the first digital value, such as by the summation circuit340. Based on the subtraction, an error correction signal can be provided at the output of the summation circuit340, and the error correction signal can include an additive error310such as that introduced by the sample and hold circuit305and an additive error335, such has that introduced by the first ADC circuit315or the second ADC circuit330. The error correction signal can be provided to the digital filter350. The digital filter350can provide a digitally filtered version of the error correction signal to the input of the second DAC355. The second DAC355can convert the digitally filtered error correction signal into an analog error correction voltage signal. The analog error correction voltage signal can be provided to the summation circuit360and the summation circuit can subtract the analog error correction signal from the sampled analog input voltage signal and the additive error310provided at the output of the sample and hold circuit. In an example, the digital filter350can include a 1storder, low-pass, infinite-impulse-response (IIR) filter. In an example, the digital filter350can be an averaging filter. In an example, the digital filter can include an IIR filter of any order, a finite-impulse-filter having any number of taps and coefficients for those taps. The digital filter can be selected such as to minimize noise in the error correction signal, respond quickly to changes in the error correction signal, and minimize area and power in a circuit.

FIG. 4shows an analog-to-digital converter (ADC) circuit and error correction circuitry400. The ADC circuit and error correction circuitry400can include a first capacitor digital-to-analog converter (CDAC)405, a sampling switch410, an ADC circuit415, a second CDAC420, a first DAC control circuit435, a second DAC control circuit440. The first CDAC405can be connected to the first DAC control circuit435, the sampling switch410, and to the input of the ADC circuit415. The output of the ADC circuit415can be connected to the first DAC control circuit435and the second DAC control circuit440. The second CDAC420can be connected to the second DAC control circuit440, the sampling switch410, and to the input of the ADC circuit415. During operation, a first clock can be provided to the first DAC control circuit435and a second clock can be provided to the second DAC control circuit440to facilitate operation of the ADC circuit and error correction circuitry400. The first CDAC405can be configured to sample a first analog voltage, such as by closing the sampling switch410and connecting internal switches within the first CDAC405to the first analog voltage. After the first analog voltage has been sampled, the sampling switch410can be opened and the internal switches within the first CDAC405can be disconnected from the first analog voltage, such as to provide a sampled first analog voltage at the input of the ADC circuit415. The closing and re-opening of the sampling switch410can introduce an additive error (which can sometimes be referred to as a pedestal error) onto the sampled first analog voltage, such as due to charge injection (e.g., the first analog voltage can be 2.1V, the additive error can be 0.1V, and the sampled first analog voltage can be 2.2V). The ADC circuit415can convert the sampled first analog voltage to a first digital value. The ADC circuit415can introduce an additive error onto the sampled first analog voltage (e.g., the sampled first analog voltage can be 2.2V, the additive error can be 0.1V, and the first digital value can represent 2.3V). The ADC circuit415can include a comparator circuit as shown inFIG. 4A. The first digital value can be loaded onto capacitive elements of the first CDAC405, and a voltage at the input of the ADC circuit415can have a magnitude of less than one half of a least-significant bit of the first CDAC405after conversion of the sampled first analog voltage to the first digital value. After conversion of the sampled first analog voltage to the first digital value, the sampling switch410can be closed and then re-opened, such as to sample an additive error, such as caused by charge injection, onto the second CDAC440. The ADC circuit415can then convert the sampled additive error into a second digital value. The ADC circuit415can introduce an additive error onto the sampled additive error (e.g., the sampled additive error can be 0.1V, the additive error can be 0.1V, and the second digital value can represent 0.2V). The second digital value can be loaded onto capacitive elements of the second CDAC440, and a voltage at the input of the ADC circuit415can have a magnitude of less than one half of a least-significant bit of the second CDAC440after conversion of the sampled additive error to the second digital value. In an example, the second digital value can be subtracted from the first digital value such as to provide correction of errors, such as those introduced by sampling switch410and ADC circuit415. In an example, an analog voltage based on the second digital value can be applied to the input of the ADC circuit415during sampling of the first analog voltage to provide cancellation of errors, such as those introduced by sampling switch410and ADC circuit415. In an example, the ADC circuit415can include a comparator. In an example, the first CDAC405can be part of a first SAR ADC, and the second CDAC420can be part of a second SAR ADC. In an example, the first CDAC405can include capacitive elements corresponding to n digital bits, and the second CDAC420can include capacitive elements corresponding to m digital bits, and n can be greater than m. In an example the resolution of a CDAC can be determined by the number of digital bits represented by the CDAC (e.g., the resolution of a CDAC can be finer for a greater number of digital bits).

FIG. 5Ashows an analog-to-digital converter (ADC) circuit and error correction circuitry500. The ADC circuit and error correction circuitry500can include a capacitor digital-to-analog converter (CDAC)505, a sampling switch510, an ADC circuit515, a first DAC control circuit535, and a second DAC control circuit540. The CDAC505can include a first portion505aand a second portion505b. The CDAC505can be connected to the first DAC control circuit535, the second DAC control circuit540, the sampling switch510, and to the input of the ADC circuit515. The output of the ADC circuit515can be connected to the first DAC control circuit535and the second DAC control circuit540. During operation, a first clock can be provided to the first DAC control circuit535and a second clock can be provided to the second DAC control circuit540to facilitate operation of the ADC circuit and error correction circuitry500. The CDAC505can be configured to sample a first analog voltage, such as by closing the sampling switch510and connecting internal switches within the CDAC505to the first analog voltage. After the first analog voltage has been sampled, the sampling switch510can be opened and the internal switches within the CDAC505can be disconnected from the first analog voltage, such as to provide a sampled first analog voltage at the input of the ADC circuit515. The closing and re-opening of the sampling switch510can introduce an additive error onto the sampled first analog voltage, such as due to charge injection (e.g., the first analog voltage can be 2.1V, the additive error can be 0.1V, and the sampled first analog voltage can be 2.2V). The ADC circuit515can convert the sampled first analog voltage to a first digital value. The ADC circuit515can introduce an additive error onto the sampled first analog voltage (e.g., the sampled first analog voltage can be 2.2V, the additive error can be 0.1 V, and the first digital value can represent 2.3V). The first digital value can be loaded onto capacitive elements of the CDAC505, and a voltage at the input of the ADC circuit515can have a magnitude of less than one half of a least-significant bit of the CDAC505after conversion of the sampled first analog voltage to the first digital value. After conversion of the sampled first analog voltage to the first digital value, the sampling switch510can be closed and then re-opened, such as to sample an additive error, such as caused by charge injection, onto the second portion of the CDAC505b. The ADC circuit515can then convert the sampled additive error into a second digital value. The ADC circuit515can introduce an additive error onto the sampled additive error (e.g., the sampled additive error can be 0.1V, the additive error can be 0.1V, and the second digital value can represent 0.2V). The second digital value can be loaded onto capacitive elements of the second portion of the CDAC505b, and a voltage at the input of the ADC circuit515can have a magnitude of less than one half of a least-significant bit of the second portion of the CDAC505bafter conversion of the sampled additive error to the second digital value. In an example, the second digital value can be subtracted from the first digital value such as to provide correction of errors, such as those introduced by sampling switch510and ADC circuit515. In an example, an analog voltage based on the second digital value can be applied to the input of the ADC circuit515during sampling of the first analog voltage to provide cancellation of errors, such as those introduced by sampling switch510and ADC circuit515. In an example, the ADC circuit515can include a comparator. In an example, the CDAC505can be part of a SAR ADC. In an example, such as that shown inFIG. 5B, the ADC circuit and error correction circuitry500can include an auxiliary ADC550. The auxiliary ADC can sample the first analog voltage (Vin) and can convert the sampled first analog voltage to an auxiliary digital output. The auxiliary digital output can be provided to the first DAC control circuit535and the second DAC control circuit540. Based on the auxiliary digital output, the first DAC control circuit535and the second DAC control circuit540can load charge onto capacitive elements corresponding to the first few most significant bits (MSBs) of the first CDAC505aand the second CDAC505b, respectively. In an example, such as that shown inFIG. 5C, the ADC circuit and error correction circuitry500can include a switch560, an amplifier564, a second ADC circuit568, and a filter572. During operation, after conversion of the sampled first analog voltage to the first digital value by the ADC circuit515, the voltage at the input of the ADC circuit515can be provided to the amplifier564, such as by closing the switch560. The amplifier564can provide an amplified signal to the ADC circuit568. The ADC circuit568can convert the amplified signal to a digital value. The digital value can be filtered by digital filter572and then be provided to the DAC control circuit540and loaded onto capacitive elements of the CDAC505, such as to improve the accuracy of the conversion of the analog input to a digital value. In an example, the digitally filtered value can be provided to the second DAC control circuit540and the digitally filtered values can be loaded onto the second portion of CDAC505b.

FIG. 6shows a method of providing error correction in an analog-to-digital converter (ADC) such as that shown inFIG. 1. The sample and hold circuit102can sample a first analog signal (Vin) and can introduce a first additive error represented at110(step610). The ADC115can convert the sampled first analog signal to a first digital value and can introduce a second additive error represented at135(step620). The DAC125can convert the first digital value to a second analog signal that can include the first analog signal and the first and second additive errors (step630). The sample and hold circuit102can sample the second analog signal and can introduce a third additive error (step640). The ADC130can convert the sampled second analog signal to a second digital value and can introduce a fourth additive error (step650). The summation circuit140can provide a digital error correction signal based on the difference between the first digital value and the second digital value (step660).