Method of operating physically unclonable function circuit, physically unclonable function circuit and semiconductor chip

A physically unclonable function includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. A method of operating the physically unclonable function circuit includes the controller setting the plurality of memory cells to an initial data state, the controller setting the plurality of memory cells between the initial data state and an adjacent data state of the initial data state, the current comparator reading a first current from a memory cell in a first section of the plurality of the memory cells, the current comparator reading a second current from a memory cell in a second section of the plurality of the memory cells, and the current comparator outputting a random bit according to the first current and the second current.

CROSS REFERENCE TO RELATED APPLICATION

This non-provisional application claims priority of China patent application No. 202110191569.0, filed on 19 Feb. 2021, included herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to data security, and in particular, to an operating method of a physical unclonable function circuit, a physical unclonable function circuit and a semiconductor chip.

2. Description of the Prior Art

A physical unclonable function (PUF) circuit utilizes a unique “digital fingerprint” of each semiconductor device to prevent data theft and ensure data security. The PUF circuit in the related art sets memory cells to a marginal range near a read current level, and uses the read current level to read the memory cells to generate random data. However, when the read current level is not in the center of the marginal range, the randomness of random data will be reduced, resulting in reduced data security.

SUMMARY OF THE INVENTION

According to an embodiment of the invention, a method of operating a physically unclonable function (PUF) circuit is provided. The physical unclonable function circuit includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. The method includes the controller setting the plurality of memory cells to an initial data state, the controller setting the plurality of memory cells to a state between the initial data state and an adjacent data state of the initial data state, the current comparator reading a first current from a memory cell in a first section of the plurality of memory cells, the current comparator reading a second current from a memory cell in a second section of the plurality of memory cells, and the current comparator outputting a random bit according to the first current and the second current.

According to another embodiment of the invention, a physical unclonable function circuit includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. The current comparator is coupled to a memory cell in a first section of the plurality of memory cells and a memory cell in a second section of the plurality of memory cells. The controller is coupled to the flash memory and the current comparator. The controller is used to set the plurality of memory cells to an initial data state, and set the plurality of memory cells to a state between the initial data state and an adjacent data state of the initial data state. The current comparator is used to read the first current from the memory cell in the first section, read the second current from the memory cell in the second section, and output a random bit according to the first current and the second current.

According to another embodiment of the invention, a semiconductor chip includes a physical unclonable function circuit and a key generator. The physical unclonable function circuit includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. The current comparator is coupled to a memory cell in a first section of the plurality of memory cells and a memory cell in a second section of the plurality of memory cells. The controller is coupled to the flash memory and the current comparator. The key generator is coupled to the physical unclonable function circuit. The controller is used to set the plurality of memory cells to an initial data state, and set the plurality of memory cells to a state between the initial data state and an adjacent data state of the initial data state. The current comparator is used to read the first current from the memory cell in the first section, read the second current from the memory cell in the second section, and output a random bit according to the first current and the second current. The key generator is configured to generate a key according to the random bit.

DETAILED DESCRIPTION

FIG. 1is a block diagram of a physical unclonable function (PUF) circuit according to an embodiment of the invention. The PUF circuit1may generate a random bit Dpuf without using a read current level, thereby increasing the randomness of the random bit Dpuf. The random bit Dpuf may have a first logical value or a second logical value, and the probability of the random bit Dpuf being the first logical value and the probability of the random bit Dpuf being the second logical value may be substantially equal. The first logical value may be, but is not limited to, a logic “0”, and the second logical value may be, but is not limited to, a logic “1”.

The PUF circuit1may include a row decoder10, a flash memory12, a controller14and a current comparator16. The flash memory12may be a NAND flash memory, and may include memory blocks121and122. The memory block121may include memory cells M1(1,1) to M1(M,N) arranged in N rows, and the N rows of memory cells in the memory block121may be coupled to the row decoder10via the word lines WL1(1) to WL1(N) and may be coupled to the current comparator16via the bit lines BL1(1) to BL1(M), M, N being positive integers larger than 1. The memory block122may include memory cells M2(1,1) to M2(M,N) arranged in N rows, and the N rows of memory cells in the memory block122may be coupled to the row decoder10via the word lines WL2(1) to WL2(N) and may be coupled to the current comparator16via the bit lines BL2(1) to BL2(M). The memory cells M1(1,1) to M1(M,N) and M2(1,1) to M2(M,N) may be single-level cells or multi-level cells. The current comparator16may be a sense amplifier or a differential current comparator. The controller14may be coupled to the current comparator16, and coupled to the flash memory12via the row decoder10.

The memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) may be set to an erased state, a programming state or a metastable state. The metastable state may be located between the erased state and the programming state. In a normal operation, each memory cell M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) may be set to the erased state or the programming state, but not to the metastable state. When generating the random bit Dpuf, the memory cells M1(1,1) to M1(M,N) and M2(1,1) to M2(M,N) are set to the metastable state. The controller14may set the memory cells M1(1,1) to M1(M, N) and M2(1,1) to M2(M, N) to the metastable state during a factory test or a reset mode.FIG. 2shows the current distributions of memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N), where the horizontal axis represents the current and the vertical axis represents the number of memory cells. When reading data, the controller14may apply a predetermined read voltage via the row decoder10, for example, 0V to the control terminals of the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N), the current comparator16may read currents flowing through the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to determine the states thereof. According to the states of the memory cells M1(1,1) to M1(M,N), and M2(1,1) to M2(M,N), the read currents I may form distributions D1, Dm or D0. The distributions D1, Dm, and D0represent current distributions of the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) in the programming state, the metastable state and the erased state, respectively. Current levels L1, Lm, and L0are the averages of the distributions D1, Dm, and D0, respectively. For example, the current levels L1, Lm, and L0may be 0 μA, 10 μA, and 20 μA, respectively. When setting the metastable state, the controller14may first erase the data in the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) (Distribution D0), and then program the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to the programming state (Distribution D1), and then perform a weak erasing procedure to set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to the metastable state (Distribution Dm). In some embodiments, when setting the metastable state, the controller14may first erase the data in the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) (Distribution D0), and then perform a weak programming procedure to set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to the metastable state (Distribution Dm).

When generating a random bit Dpuf, the current comparator16may read a first current from one of the memory cells M1(1,1) to M1(M,N), and read a second current from the memory cell M2(1,1) to M2(M,N), and output a random bit Dpuf according to the first current and the second current. Specifically, the current comparator16may compare the first current and the second current to generate a comparison result, and generate the random bit Dpuf according to the comparison result. If the comparison result shows that the first current is higher than the second current, the current comparator16outputs the first logical value of the random bit Dpuf; and if the comparison result shows that the first current is less than the second current, the current comparator16outputs the second logical value of the random bit Dpuf. Since the PUF circuit1outputs the random bit Dpuf according to the first current and the second current, the randomness of the random bit Dpuf is not affected by the read current level, thereby enhancing the randomness of the random bit Dpuf. In addition,FIG. 2shows that the distribution Dm of the metastable state is wider than the distribution D1of the programming state and the distribution D0of the erased state. Therefore, the difference between the first current and the second current may be larger, increasing the randomness of the random bit Dpuf and accelerating generation of the random bit Dpuf.

FIG. 3is a flowchart of a method300of operating the PUF circuit1. The method300includes Step S302to S310to generate the random bit Dpuf. Any reasonable step change or adjustment is within the scope of the disclosure. Steps S302to S310are detailed as follows:

Step S302: The controller14sets the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to the initial data state;

Step S304: The controller14sets the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to the metastable state between the initial data state and the adjacent data state of the initial data state;

Step S306: The current comparator16reads the first current from a memory cell in a first section of the memory cells M1(1,1) to M1(M,N);

Step S308: The current comparator16reads the second current from a memory cell in a second section of the memory cells M2(1,1) to M2(M,N);

Step S310: The current comparator16outputs the random bit Dpuf according to the first current and the second current.

In Step S302, the initial data state may be the programming state or the erased state. In Step S304, if the initial data state is the programming state, the adjacent data state is the erased state, and the controller14applies a weak erasing pulse to the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to the metastable state between the programming state and the erased state. Specifically, the controller14may apply the weak erasing pulse to the control terminals of the memory cells M1(1,1) to M1(M, N), M2(1,1) to M2(M,N), and apply a high voltage to the common P-type well of the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M, N). The weak erasing pulse may be 7-8V. If the initial data state is the erased state, the adjacent data state is the programming state, and the controller14applies a weak programming pulse to the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to the metastable state between the erased state and the programming state. Specifically, the controller14may apply the weak programming pulses to the control terminals of the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) via the word lines WL1(1) to WL1(N), WL2(1) to WL2(N), and apply a positive voltage to the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) via the bit lines BL1(1) to BL1(M), BL2(1) to BL2(M). The weak programming pulse may be 7-8V. In Steps S306and S308, the memory cell in the first section is located in a specific area in the memory block121, and the memory cell in the second section is located in a specific area in the memory block122. In some embodiments, the memory cell in the first section is located in an nth row in the memory block121, and the memory cell in the second section is located in an nth row in the memory block122. Upon receiving a request for generating a random bit Dpuf, the controller14enables the nth row of the memory block121and the nth row of the memory block122using the word lines WL1(n) and WL2(n), respectively, and the current comparator16reads the first current from the memory cell M1(m,n) in the nth row and mth column of the memory block121, and reads the second current from the memory cell M2(m,n) in the nth row and the mth column of the memory block122, where n is a positive integer between 1 and N, and m is a positive integer between 1 and M. In some embodiments, the memory cell in the first section is located in the (n1)th row of the memory block121, and the memory cell in the second section is located in the (n2)th row of the memory block122, and n1 and n2 are positive Integers between 1 and N. The controller14may respectively enable the (n1)th row of the memory block121and the (n2)th row of the memory block122via the word lines WL1(n1) and WL2(n2), so that the current comparator16reads the first current from the memory cell M1(m,n1) in the (n1)th row and mth column of block121and reads the second current from the memory cell M2(m,n2) in the (n2)th row and mth column of the memory block122, m being a positive integer from 1 to M. In Step S310, if the comparison result shows that the first current is higher than the second current, the current comparator16outputs the first logical value (logic “0”) of the random bit Dpuf; and if the comparison result shows that the first current is less than the second current, the current comparator16outputs the second logical value (logic “1”) of the random bit Dpuf. In some embodiments, the current comparator16may also read a plurality of memory cells from the nth row of the memory block121and the nth row of the memory block122respectively to generate k first currents and k second currents, respectively, and compare the k first currents and the k corresponding second currents to generate k random bits Dpuf, k being a positive integer between 1 and M. Please refer to Table 1, the current comparator16reads the memory cells M1(m,n) coupled to the word line WL1(n) and the memory cells M2(m,n) coupled to the word line WL2(n) to obtain 7 first currents and 7 second currents, respectively, and compares the 7 first currents {8 μA, 7 μA, 12 μA, 4 μA, 15 μA, 9 μA, 9 μA} and the 7 corresponding second currents {4 μA, 12 μA, 14 μA, 5 μA, 12 μA, 3 μA, 15 μA}, respectively, to generate 7-bit random bits Dpuf {0(8>4), 1(7<12), 1(12<14), 1(4<5), 0(15>12), 0(9>3), 1(9<15)}.

The operation method300outputs random bits Dpuf according to the first currents and the second currents. Therefore, the randomness of the random bits Dpuf is not affected by the read current level, enhancing the randomness of the random bits Dpuf.

FIG. 4is a schematic diagram of the current comparator16according to an embodiment of the invention. The current comparator16includes transistors410,412,440and442, inverters400and460, current sources414and444, and an operation amplifier420. The current comparator16may output the random bit Dpuf according to the first current I1and the second current I2.

The transistor410includes a first terminal configured to receive a supply voltage VDD; a second terminal; and a control terminal coupled to the second terminal of the transistor410. The transistor412includes a first terminal coupled to the second terminal of the transistor410; a second terminal; and a control terminal. The current source414includes a first terminal coupled to the second terminal of the transistor412, and a second terminal configured to receive a ground voltage VSS. The inverter400includes a first terminal coupled to the first terminal of the current source414; and a second terminal coupled to the control terminal of the transistor412. The transistor440includes a first terminal configured to receive the supply voltage VDD; a second terminal; and a control terminal coupled to the control terminal of the transistor410. The transistor442includes a first terminal coupled to the second terminal of the transistor440; a second terminal; and a control terminal. The current source444includes a first terminal coupled to the second terminal of the transistor442, and a second terminal configured to receive the ground voltage VSS. The inverter460includes a first terminal coupled to the first terminal of the current source444; and a second terminal coupled to the control terminal of the transistor442. The operation amplifier420includes a first input terminal coupled to the second terminal of the transistor412; a second input terminal coupled to the second terminal of the transistor442; and an output terminal. The first input terminal of the operation amplifier420may be a non-inverting input terminal, and the second input terminal of the operation amplifier420may be an inverting input terminal. The transistors410and440may be P-type transistors, and the transistors412and442may be N-type transistors.

The transistors410and440may serve as a current mirror. The transistors412and442may serve as current clamps. In the initial state, the first current I1and the second current I2are 0, and the control terminal of the transistor412and the control terminal of the transistor442may receive a fixed bias voltage, e.g., 0.8V, to clamp the voltages at the first input terminal and the second input terminal of the operation amplifier420. When generating the random bit Dpuf, if the first current I1is higher than the second current I2, the current source414increases the voltage at the first terminal of the current source414according to the first current I1, the inverter400reduces the voltage at the second terminal thereof, and the transistor412will reduce the voltage at the first input terminal of the operation amplifier420. Similarly, the current source444increases the voltage at the first terminal of the current source444according to the second current I2, and the inverter460reduces the voltage at the second terminal thereof, and the transistor442will reduce the voltage at the second input terminal of the operation amplifier420. Since the first current I1is higher than the second current I2, the voltage at the first input terminal of the operation amplifier420will be less than the second input terminal of the operation amplifier420, and the output terminal of the operation amplifier420will output a logic “0” as the random bit Dpuf. If the first current I1is less than the second current I2, the voltage at the first input terminal of the operation amplifier420will be higher than the voltage at the second input terminal, and the output terminal of the operation amplifier420will output a logic “1” as the random bit Dpuf.

FIG. 5is a schematic diagram of the current comparator16according to another embodiment of the invention. The current comparator16includes current sources500,502,540and542, transistors510and530, and inverters520and522. The current comparator16may output the random bit Dpuf according to the first current I1and the second current I2.

The current source500includes a first terminal configured to receive the supply voltage VDD; and a second terminal. The current source502includes a first terminal coupled to the second terminal of the current source500, and a second terminal configured to receive the ground voltage VSS. The transistor510includes a first terminal; a second terminal configured to receive the ground voltage VSS; and a control terminal coupled to the second terminal of the current source500and the first terminal of the current source502. The current source540includes a first terminal configured to receive the supply voltage VDD; and a second terminal. The current source542includes a first terminal coupled to the second terminal of the current source540, and a second terminal configured to receive the ground voltage VSS. The transistor530includes a first terminal; a second terminal configured to receive the ground voltage VSS; and a control terminal coupled to the second terminal of the current source540and the first terminal of the current source542. The inverter522includes a first terminal coupled to the first terminal of the transistor510; and a second terminal coupled to the first terminal of the transistor530. The inverter520includes a first terminal coupled to the first terminal of the transistor530; and a second terminal coupled to the first terminal of the transistor510. The transistors510and530may be N-type transistors.

The current sources500and540may generate a reference current Iref. The current source502may generate a first current I1, and the current source542may generate a second current I2. Inverters520and522may form a latch. In the initial state, the first current I1and the second current I2are 0, and the control terminal of the transistor510and the control terminal of the transistor530may receive a fixed bias voltage to establish equal voltages at the first terminal of the transistor510and the first terminal of the transistor530. When generating the random bit Dpuf, if the first current I1is higher than the second current I2, the current sources500and502will establish a voltage at the control terminal of the transistor510according to the difference between the reference current Iref and the first current I1. The current sources540and542will establish a voltage at the control terminal of the transistor530according to the difference between the reference current Iref and the second current I2. If the first current I1is higher than the second current I2, the voltage at the control terminal of the transistor510will be less than the voltage at the control terminal of the transistor530, the voltage at the first terminal of the transistor510will be higher than the voltage at the first terminal of the transistor530, and the latch will output a logic “0” as the random bit Dpuf. If the first current I1is less than the second current I2, the voltage at the control terminal of the transistor510will be higher than the voltage at the control terminal of the transistor530, the voltage at the first terminal of the transistor510will be less than the voltage at the first terminal of the transistor530, and the latch will output a logic “1” as the random bit Dpuf.

FIG. 6shows a relationship between the weak erasing pulse and the current difference between the first current and the second current, where the horizontal axis represents the weak erasing pulse, and the vertical axis represents the current difference between the first current I1and the second current I2. When the weak erasing pulse is between 6V and 8V, the current difference between the first current I1and the second current I2has a normal distribution centered at0. When the weak erasing pulse is increased from 6V to 8V, the current difference between the first current I1and the second current I2also expands from ±5 μA to ±20 μA. When the weak erasing pulse is less than 7V, the current difference between the first current I1and the second current I2will exceed ±10 μA. Therefore, the PUF circuit1may use the weak erasing pulses ranging from 7V to 8V to set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to the metastable state.

FIG. 7shows the relationship between weak erasing pulse and the random bit, where the horizontal axis represents the weak erasing pulse, and the vertical axis represents the percentage. The curve70represents that the random bit Dpuf is the first logical value; the curve72represents that the random bit Dpuf is the second logical value. When the weak erasing pulse increases from 6V to 8V, the curves70and72gradually approach 50%. When the weak erasing pulse is between 7V and 8V, the percentage of the random bit Dpuf being the first logical value and the percentage of the random bit Dpuf being the second logical value are approximately 50% each. Therefore, the PUF circuit1may use weak erasing pulses ranging from 7V to 8V to set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to the metastable state, thereby enhancing randomness.

FIG. 8is a block diagram of a semiconductor chip8according to an embodiment of the invention. The semiconductor chip8includes a PUF circuit1, a key generator80and a codec82. The PUF circuit1, the key generator80and the codec82are sequentially coupled. The configurations and the operations of the PUF circuit1have been explained in the preceding paragraphs, and will not be repeated here.

When performing encoding/decoding, the PUF circuit1may receive a request for generating a random bit Dpuf, the key generator80may generate a public key Kpb and a private key Kprv according to the random bit Dpuf, and the codec82may encode or decode the input data Din according to the private key Kprv to generate the output data Dout. The input data Din may be data without encoding, address without encoding, encoded data, and/or encoded address. After encoding, the codec82may output the output data Dout to an external circuit, the key generator80may output the public key Kpb to the external circuit, and the external circuit may decode the output data Dout according to the public key Kpb to obtain input data Din. Since the random bit Dpuf has the enhanced randomness, the data security of the input data Din may be ensured.