Semiconductor device having depletion region for improving breakdown voltage characteristics

A semiconductor device having a wide depletion region for increasing the breakdown voltage of the device includes an epitaxial layer of a first conductive type. An anode electrode and a cathode electrode are arranged on the epitaxial layer to be separated from each other. A first drift layer of the first conductive type formed in the epitaxial layer. A Schottky contact area is at a region of contact between the anode electrode and the first drift layer. An impurity region of a second conductive type is different from the first conductive type at the epitaxial layer. An insular impurity region is formed below the Schottky contact area.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2013-0105513 filed on Sep. 3, 2013 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which in their entirety are herein incorporated by reference.

BACKGROUND

1. Technical Field

The present inventive concept relates to a semiconductor device and method for fabricating the same.

2. Description of the Related Art

A conventional semiconductor device that is fabricated to include a semiconductor substrate is typically developed to perform a high speed operation at a low voltage. Further, semiconductor device fabricating processes are developed to improve integration density.

Examples of the semiconductor device can include a transistor, a diode and the like. A Schottky diode may be fabricated using a semiconductor substrate can exhibit excellent characteristics at high frequencies and can rely on a rectifying action that occurs at a contact surface between metal and semiconductor.

SUMMARY

Therefore, it is an aspect of the present inventive concept to provide a semiconductor device with improved operating characteristics.

It is another aspect of the present inventive concept to provide a method for fabricating a semiconductor device with improved operating characteristics.

However, aspects of the present inventive concept are not restricted to those set forth herein. The above and other aspects of the present inventive concept will become more apparent to one of ordinary skill in the art to which the present inventive concept pertains by referencing the detailed description of the present inventive concept given below.

According to an aspect of the present invention, there is provided a semiconductor device comprising: an epitaxial layer of a first conductive type; an anode electrode and a cathode electrode on the epitaxial layer; a first drift layer of the first conductive type at the epitaxial layer; a Schottky contact area at a region of contact between the anode electrode and the first drift layer; an impurity region of a second conductive type different from the first conductive type at the epitaxial layer; and an insular impurity region formed below the Schottky contact area.

In some embodiments, the insular impurity region includes a region having a maximum cross-sectional diameter that is equal to or less than 5 μm, and having an impurity concentration that is 10 times to 1,000 times an impurity concentration of the epitaxial layer.

In some embodiments, the semiconductor device comprises a Schottky diode.

In some embodiments, a conductive type of the insular impurity region is the same as the first conductive type.

In some embodiments, the first drift layer comprises a plurality of insular impurity regions separated from each other, and one of the plurality of insular impurity regions includes the insular impurity region below the Schottky contact area.

In some embodiments, the impurity region of the second conductive type comprises wells of the second conductive type arranged on both sides of the insular impurity region.

In some embodiments, the anode electrode and the cathode electrode are arranged in a grid shape.

In some embodiments, the cathode electrode comprises first and second cathode electrodes, the first cathode electrode has a dot shape, the anode electrode is constructed and arranged to surround the first cathode electrode, and the second cathode electrode is constructed and arranged to surround the anode electrode.

In some embodiments, a conductive type of the insular impurity region is the same as the second conductive type.

In some embodiments, the first drift layer is constructed and arranged to surround the insular impurity region.

In some embodiments, the impurity region of the second conductive type comprises a second drift layer of the second conductive type at the first drift layer.

In some embodiments, the second drift layer and the insular impurity region are constructed and arranged to be separated from each other.

In some embodiments, an impurity concentration of the insular impurity region is higher than an impurity concentration of the second drift layer.

In some embodiments, the impurity region of the second conductive type comprises a plurality of second drift layers of the second conductive type at the first drift layer, and wherein the insular impurity region is one of the plurality of second drift layers.

In some embodiments, the first conductive type includes an N type conductivity type and the second conductive type includes a P type conductivity type.

In some embodiments, the semiconductor device, further comprises a semiconductor substrate of the second conductive type; and a buried layer of the first conductive type formed on the semiconductor substrate, wherein the epitaxial layer is formed on the buried layer.

According to another aspect of the present invention, there is provided a semiconductor device comprising: an epitaxial layer of a first conductive type; a plurality of insular impurity regions having the first conductive type at the epitaxial layer, and separated from each other; first wells formed in the epitaxial layer, the first wells separated from each other and having a second conductive type that is different from the first conductive type; first and second electrodes on the epitaxial layer, the first and second electrodes separated from each other by an element isolation film; and second wells in the plurality of insular impurity regions and in contact with the first electrode, wherein at least one of the plurality of insular impurity regions is below the second electrode.

In some embodiments, the second wells have a conductive type that is the same as the first conductive type.

In some embodiments, a Schottky barrier is at a contact surface between the second electrode and one of the plurality of insular impurity regions.

In some embodiments, an impurity concentration of the plurality of insular impurity regions is higher than an impurity concentration of the epitaxial layer.

According to still another aspect of the present invention, there is provided a semiconductor device comprising: an epitaxial layer of a first conductive type; a first drift layer of the first conductive type on the epitaxial layer; first and second electrodes on the first drift layer, the first and second electrodes separated from each other by an element isolation film; second drift layers in the first drift layer and separated from each other, the second drift layers having a second conductive type different from the first conductive type; a plurality of wells formed in the first drift layer, the wells in contact with the first electrode; and a body region of the second conductive type at the first drift layer below the second electrode, wherein the body region is an insular impurity region that is separated from the second electrode by the first drift layer.

In some embodiments, the first electrode comprises a cathode electrode, and the second electrode comprises an anode electrode.

In some embodiments, an impurity concentration of the body region is 10 times to 1,000 times an impurity concentration of the first drift layer.

In some embodiments, a depth of lower surfaces of the second drift layers is larger than a depth of a lower surface of the body region.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a rectifier that converts first and second outputs provided from a resonator into a third output, wherein the rectifier comprises: at least one Schottky diode that provides at least one of the first and second outputs to an anode electrode; and an insular impurity region below the anode electrode of the Schottky diode.

According to another aspect of the present invention, there is provided a semiconductor device comprising: an epitaxial layer; an anode electrode on the epitaxial layer; and an insular impurity region at a region of the epitaxial layer below the anode electrode to provide a distance between the anode electrode and an electric field formed during operation of the device field.

In some embodiments, the semiconductor device further comprises a Schottky contact area at a region of contact between the anode electrode and the first drift layer, wherein the insular impurity region formed below the Schottky contact area.

In some embodiments, the insular impurity region includes a region having a maximum cross-sectional diameter that is equal to or less than 5 μm, and having an impurity concentration that is 10 times to 1,000 times an impurity concentration of the epitaxial layer.

In some embodiments, the semiconductor device further comprises at least one drift layer, the insular impurity region below the anode electrode corresponding to a draft layer of the at least one drift layer.

In some embodiments, the semiconductor device further comprises an impurity region comprises wells of the different conductive type than that of the epitaxial layer, the wells arranged on both sides of the insular impurity region.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The present invention will be described with reference to perspective views, cross-sectional views, and/or plan views, in which preferred embodiments of the invention are shown. Thus, the profile of an exemplary view may be modified according to manufacturing techniques and/or allowances. That is, the embodiments of the invention are not intended to limit the scope of the present invention but cover all changes and modifications that can be caused due to a change in manufacturing process. Thus, regions shown in the drawings are illustrated in schematic form and the shapes of the regions are presented simply by way of illustration and not as a limitation.

Hereinafter, a semiconductor device according to an embodiment of the present inventive concept will be described with reference toFIGS. 1 and 2.

FIG. 1is a plan view of a semiconductor device according to an embodiment of the present inventive concept.FIG. 2is a cross-sectional view taken along line A-A ofFIG. 1. An example of a semiconductor device according to embodiments of the present inventive concept can include a Schottky diode, described herein. However, the present inventive concept is not limited thereto.

Referring toFIGS. 1 and 2, a semiconductor device1includes a substrate10, a buried layer20, an epitaxial layer30, first drift layers40, a plurality of first wells80, a plurality of second wells85, a plurality of third wells75, an anode electrode52, and a cathode electrode54.

The substrate10may include a semiconductor material. The substrate10may be made of at least one semiconductor material selected from the group consisting of, for example, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP.

In some embodiments of the present inventive concept, an insulating substrate may be used as the substrate10. Specifically, a silicon-on-insulator (SOI) substrate may be used as the substrate10. In embodiments that include an SOI substrate, there is an advantage of reducing delay time in an operation process of the semiconductor device1.

In this embodiment, a conductive type of the substrate10may be, for example, a P type. A concentration of impurities in the substrate10may be lower than a concentration of impurities in the first wells80.

The buried layer20may be formed on the substrate10. In this embodiment, a conductive type of the buried layer20may be, for example, an N type.

In some embodiments of the present inventive concept, the buried layer20may be formed inside the substrate10and/or over the substrate10. That is, the buried layer20may be formed at a boundary between the substrate10and the epitaxial layer30. In order that a portion of the buried layer20be formed on the substrate10and the remaining portion of the buried layer20be formed on the epitaxial layer30, after the buried layer20is formed in the substrate10and the epitaxial layer30is formed on the substrate10, a heat treatment may be performed. When the heat treatment is in progress, since the buried layer20is diffused into the substrate10and the epitaxial layer30, a portion of the buried layer20may be formed on the substrate10and the remaining portion of the buried layer20may be formed on the epitaxial layer30.

In other embodiments of the present inventive concept, the buried layer20may be omitted.

The epitaxial layer30may be formed on the buried layer20. In this embodiment, a conductive type of the epitaxial layer30may be, for example, an N type. Further, in this case, a concentration of impurities in the epitaxial layer30may be lower than a concentration of impurities in the buried layer20and the first drift layers40.

The first drift layers40, the first wells80, the second wells85and the like may be formed in the epitaxial layer30.

In this embodiment, as illustrated, the first drift layers40may include a plurality of insular impurity regions that are separated from each other. As used herein, an insular impurity region refers to a region having a maximum cross-sectional diameter that can be equal to or less than 5 μm, and an impurity concentration that can be 10 times to 1,000 times the impurity concentration of the epitaxial layer30. In the present embodiment, by forming the first drift layers40as a plurality of insular impurity regions separated from each other as described above, it is possible to improve operating characteristics of the semiconductor device1. A detailed description thereof will be described later.

In this embodiment, the first drift layers40may have a conductive type, for example, an N type. Specifically, the concentration of impurities \in the first drift layers40may be, for example, 1e15 to 1e18 atoms/cm2. However, the present inventive concept is not limited thereto.

A conductive type of the first wells80formed in the epitaxial layer30may be, for example, a P type. Accordingly, the first wells80and the epitaxial layer30may form a PN junction. The concentration of impurities contained in the first wells80may be higher than the concentration of impurities contained in the substrate10.

As illustrated, the first wells80may be arranged to be separated from each other by the first drift layers40arranged below the anode electrode52. In this case, the first wells80may be arranged to overlap the first drift layers40as illustrated. The first wells80may be arranged to overlap an element isolation film70as illustrated.

In the present embodiment, the first wells80may be formed to have a thickness that is less than a thickness of the first drift layers40. Specifically, the depth of the lower surfaces of the first wells80may be less than the depth of the lower surfaces of the first drift layers40.

The second wells85may be arranged in the first drift layers40. Specifically, the second wells85may be arranged in the first drift layers40positioned below the cathode electrode54. The second wells85may be in contact with the cathode electrode54. Accordingly, the second wells85may be electrically connected to the cathode electrode54.

A conductive type of the second wells85may be, for example, an N type. As illustrated, the second wells85may be arranged so as not to overlap the element isolation film70. The first drift layers40arranged below the cathode electrode54may be arranged to overlap the element isolation film70as illustrated.

The third wells75may be arranged in the first wells80. Specifically, the third wells75may be arranged in the first wells80below the anode electrode52. The third wells75may be in contact with the anode electrode52. Accordingly, the third wells75may be electrically connected to the anode electrode52. A conductive type of the third wells75may be, for example, a P type.

The anode electrode52and the cathode electrode54may be formed on the epitaxial layer30. The anode electrode52and the cathode electrode54may be separated from each other by the element isolation film70as illustrated.

In this embodiment, the element isolation film70may be formed by, for example, Shallow Trench Isolation (STI), but the present inventive concept is not limited thereto.

In this embodiment, the cathode electrode54may be arranged to surround the anode electrode52. Further, the anode electrode52may be formed to extend in one direction (e.g., vertical direction ofFIG. 1).

A Schottky contact area60may be defined in a region where the anode electrode52is in contact with the first drift layers40. A Schottky barrier may be formed in a contact surface between the first drift layers40and the anode electrode52of the Schottky contact area60. The semiconductor device1according to the present embodiment may be activated, turned on, or the like even at a low voltage by using this Schottky barrier.

The operating characteristics of the semiconductor device1may be affected by resistance characteristics and breakdown voltage (BV) characteristics.

Specifically, the resistance of the semiconductor device1should preferably be low for a high-speed operation of the semiconductor device1. Further, in order to decrease the resistance of the semiconductor device1, the carrier mobility can be increased by increasing a concentration of impurities in the semiconductor device1.

In order that the semiconductor device1operates reliably even at a high voltage, the breakdown voltage of the semiconductor device1should be high. Further, in order to increase the breakdown voltage of the semiconductor device1, a wide depletion region in the semiconductor device1can be formed.

In the semiconductor device1according to the present embodiment, by forming the depletion region widely while maintaining the concentration of impurities in the semiconductor device1to be high as necessary, it is possible to improve the operating characteristics of the semiconductor device1. Hereinafter, the effects of the semiconductor device according to the embodiment of the present inventive concept will be described with reference toFIGS. 3 to 5.

FIG. 3is a diagram illustrating an electric field EF1formed in the semiconductor device1according to the embodiment of the present inventive concept.FIG. 4is a diagram illustrating an electric field EF2formed in a semiconductor device99. Accordingly,FIGS. 3 and 4are illustrated to draw comparisons between a conventional semiconductor device and a semiconductor device in accordance with an embodiment of the inventive concept.

In the semiconductor device1ofFIG. 3according to the present embodiment, due to an insular impurity region (corresponding to one of the first drift layers40in the present embodiment) formed below the anode electrode52, the electric field EF1is formed away from the anode electrode52. However, in the exemplary semiconductor device99ofFIG. 4that is not in accordance with the embodiment of the present inventive concept, since an insular impurity region is not formed below an anode electrode52a, the electric field EF2is formed adjacent to the anode electrode52.

Specifically, inFIG. 3, a first depth P is about 2 μm, and a second depth Q is about 3.15 μm. However, inFIG. 4, a third depth R is about 1 μm, and a fourth depth S is about 2.5 μm. In other words, the depletion region of the semiconductor device1ofFIG. 3according to the present embodiment is formed to be wider than the depletion region of the exemplary semiconductor device99ofFIG. 4, which is not in accordance with the embodiment of the present inventive concept. Accordingly, the breakdown voltage characteristics of the semiconductor device1may be improved.

FIG. 5is a graph showing the breakdown voltage characteristics of the semiconductor device1ofFIG. 4and the semiconductor device99ofFIG. 5.

InFIG. 5, A graph M is obtained by measuring the current flowing through the anode electrode52awhile applying different voltages to the anode electrode52aof the exemplary semiconductor device99that is not in accordance with the present embodiment. A graph N is obtained by measuring the current flowing through the anode electrode52while applying different voltages to the anode electrode52of the semiconductor device1according to the present embodiment.

AtFIG. 5, it can be seen that a maximum breakdown voltage of graph M is about −25 V, while a maximum breakdown voltage of graph N is about −37 V. In other words, it can be seen that the breakdown voltage is improved in the semiconductor device1according to the present embodiment.

Next, a semiconductor device according to another embodiment of the present inventive concept will be described with reference toFIGS. 6 and 7.

FIG. 6is a plan view of a semiconductor device according to another embodiment of the present inventive concept.FIG. 7is a cross-sectional view taken along line B-B ofFIG. 6. Hereinafter, a repeated description will be omitted in order to avoid redundancy, and a description will be given focusing on differences from the above-described embodiment.

Referring toFIGS. 6 and 7, in a semiconductor device2according to the present embodiment, the shapes or other configuration-related features of an anode electrode94and a cathode electrode92and96may be different from those of the above-described embodiment.

Specifically, in the semiconductor device2according to the present embodiment, the anode electrode94and the cathode electrode92and96may be arranged in a grid shape.

In the semiconductor device2according to the present embodiment, a first cathode electrode92and a second cathode electrode96may be provided. Further, as shown inFIG. 6, the first cathode electrode92may be arranged in the form of dots. The anode electrode94may be arranged to surround the first cathode electrode92arranged in the form of dots. The second cathode electrode96may be arranged to surround the anode electrode94.

In this embodiment, by arranging the anode electrode94and the cathode electrode92and96as described above, the resistance characteristics of the semiconductor device2can be improved. As a result, the operating characteristics of the semiconductor device2can be improved.

Next, a semiconductor device according to another embodiment of the present inventive concept will be described with reference toFIGS. 8 and 9.

FIG. 8is a plan view of a semiconductor device according to still another embodiment of the present inventive concept.FIG. 9is a cross-sectional view taken along line C-C ofFIG. 8.

Referring toFIGS. 8 and 9, a semiconductor device3includes a substrate10, a buried layer20, an epitaxial layer30, a first drift layer42, second drift layers82, a body region84, second wells85, third wells75, an anode electrode52, and a cathode electrode54.

The substrate10may include a semiconductor material. The substrate10may be made of at least one semiconductor material selected from the group consisting of, for example, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP.

In some embodiments of the present inventive concept, an insulating substrate may be used as the substrate10. Specifically, a silicon-on-insulator (SOI) substrate may be used as the substrate10. In the case of using the SOI substrate, there is an advantage of reducing delay time in an operation process of the semiconductor device3.

In this embodiment, a conductive type of the substrate10may be, for example, a P type. Further, in this case, a concentration of impurities in the substrate10may be lower than a concentration of impurities in the second drift layers82and the body region84.

The buried layer20may be formed on the substrate10. In this embodiment, a conductive type of the buried layer20may be, for example, an N type.

The epitaxial layer30may be formed on the buried layer20. In this embodiment, a conductive type of the epitaxial layer30may be, for example, an N type. Further, in this case, a concentration of impurities in the epitaxial layer30may be lower than a concentration of impurities in the buried layer20and the first drift layer42.

The first drift layer42, the second drift layers82, the body region84, and/or the second wells85and the like may be formed in the epitaxial layer30.

In the semiconductor device3according to the present embodiment, the first drift layer42may be formed on the entire surface of the epitaxial layer30. Specifically, the first drift layers40ofFIG. 2can be formed as a plurality of insular impurity regions separated from each other in the above-described embodiments. However, the first drift layer42may be formed on the entire surface of the epitaxial layer30in the present embodiment. Accordingly, in this embodiment, the second drift layers82, the body region84, the second wells85and the like may be formed in the first drift layer42.

In this embodiment, a conductive type of the first drift layer42may be, for example, an N type. Specifically, the concentration of impurities contained in the first drift layer42may be, for example, 1e15 to 1e18 atoms/cm2, but the present inventive concept is not limited thereto.

The second wells85may be arranged in the first drift layer42. Specifically, the second wells85may be arranged in the first drift layer42arranged below the cathode electrode54. The second wells85may be in contact with the cathode electrode54. Accordingly, the second wells85may be electrically connected to the cathode electrode54.

A conductive type of the second wells85may be, for example, an N type. As illustrated herein, the second wells85may be arranged so as not to overlap the element isolation film70.

A conductive type of the second drift layers82formed in the first drift layer42may be, for example, a P type. Further, as illustrated, the first drift layer42may be arranged to surround the second drift layers82. Accordingly, the second drift layers82and the first drift layer42may form a PN junction.

A concentration of impurities in the second drift layers82may be higher than a concentration of impurities in the substrate10. Specifically, the concentration of impurities in the second drift layers82may be, for example, 1e14 to 1e18 atoms/cm2, but the present inventive concept is not limited thereto.

As illustrated, the second drift layers82may be separated from each other by the body region84. In this case, the second drift layers82may be formed to be deeper than the body region84. Specifically, the depth of the lower surfaces of the second drift layers82may be larger than the depth of the lower surface of the body region84.

As illustrated, the second drift layers82may be arranged to also overlap the element isolation film70. Further, the second drift layers82may be arranged so as not to overlap the body region84. In other words, the second drift layers82and the body region84may be separated from each other.

The body region84may be formed below the anode electrode52. In this embodiment, the body region84may be formed in the form of an insular impurity region.

A conductive type of the body region84may be, for example, a P type. Further, a concentration of P-type impurities in the body region84may be higher than a concentration of P-type impurities in the second drift layers82. Specifically, the concentration of P-type impurities in the body region84may be, for example, 1e16 to 1e20 atoms/cm2, but the present inventive concept is not limited thereto.

The first drift layer42may surround the body region84as illustrated. Accordingly, a Schottky barrier may be formed in the Schottky contact area60defined when the first drift layer42is in contact with the anode electrode52. Thus, the semiconductor device3according to the present embodiment may be turned on even at a low voltage by using the Schottky barrier.

The third wells75may be disposed in the first drift layer42. Specifically, the third wells75may be arranged in the first drift layer42arranged below the anode electrode52. The third wells75may be abut or be otherwise in contact with the anode electrode52. Accordingly, the third wells75may be electrically connected to the anode electrode52. A conductive type of the third wells75may be, for example, a P type.

The anode electrode52and the cathode electrode54may be formed on the first drift layer42. The anode electrode52and the cathode electrode54may be separated from each other by the element isolation film70as illustrated.

In this embodiment, the cathode electrode54may be constructed and arranged to surround the anode electrode52. Further, the anode electrode52may be formed to extend in one direction, for example, a vertical direction as shown inFIG. 8).

Although not shown in detail, in some embodiments of the present inventive concept, the shapes of a cathode electrode and the anode electrode may be arranged in a grid shape, for example, as shown inFIG. 6. In this case, the resistance characteristics of the semiconductor device3can be further improved.

FIGS. 10 to 11are diagrams for explaining the effects of a semiconductor device3according to another embodiment of the present inventive concept.

In particular,FIG. 10is a diagram illustrating an electric field EF3formed in the semiconductor device3according to the present embodiment. Due to an insular impurity region, for example, corresponding to the body region84in the present embodiment, formed below the anode electrode52, the electric field EF3can be formed at a distance or away from the anode electrode52. That is, the depletion region in the semiconductor device3according to the present embodiment is wider than the depletion region in a semiconductor device99, see, for example,FIG. 4, which is not in accordance with the embodiment of the present inventive concept. Accordingly, the breakdown voltage characteristics of the semiconductor device3can be improved.

Further, in the case of the semiconductor device3according to the present embodiment, the first drift layer42may be formed on the entire surface of the epitaxial layer30. Thus, since a concentration of impurities in the semiconductor device3becomes higher than those of the above-described embodiments, the resistance characteristics of the semiconductor device3can be improved.

FIG. 11is a graph showing the breakdown voltage characteristics of a semiconductor device according to the present embodiment as distinguished from a conventional semiconductor device, i.e., a device that is not in accordance with the present embodiment. In describing the graph ofFIG. 11, reference can be made to the semiconductor device3referred to in embodiments herein and the semiconductor device99referred to herein.

Specifically, inFIG. 11, M refers to a graph obtained by measuring a current flowing through the anode electrode52awhile applying different voltages to the anode electrode52aof the exemplary semiconductor device99(seeFIG. 4) which is not in accordance with the present embodiment. O refers to a graph obtained by measuring a current flowing through the anode electrode52while applying different voltages to the anode electrode52of the semiconductor device3according to the present embodiment.

Referring toFIG. 11, it can be seen that a maximum breakdown voltage of graph M is about −25 V, while a maximum breakdown voltage of graph O is about −38 V. In other words, it can be seen that the breakdown voltage is improved in the semiconductor device3according to the present embodiment.

FIG. 12is a cross-sectional view of a semiconductor device according to another embodiment of the present inventive concept. Hereinafter, a repeated description will be omitted to avoid redundancy, and a description will be given focusing on differences from the above-described embodiment.

Referring toFIG. 12, in a semiconductor device4according to the present embodiment, the body region84described with reference toFIG. 9. is replaced by a second drift layers82. In other words, in the semiconductor device4according to the present embodiment, the second drift layers82are formed as a plurality of insular impurity regions separated from each other, and one of the insular impurity regions may be formed below the Schottky contact area60as illustrated.

In this case, the depletion region in the semiconductor device4may be formed widely by the second drift layers82disposed below the Schottky contact area60. Accordingly, the breakdown voltage characteristics of the semiconductor device4can be improved.

FIG. 13is a block diagram of a semiconductor system according to an embodiment of the present inventive concept.FIG. 14is an exemplary circuit diagram of a rectifier shown inFIG. 13. The following description will be given in conjunction with a wireless power transmission system as an example of a semiconductor system according to an embodiment of the present inventive concept, but the present inventive concept is not limited thereto.

Referring toFIG. 13, the semiconductor system according to the present embodiment includes a source device110and a target device120.

The source device110may include an AC/DC converter111, a power detector113, a power converter114, a control unit115and a source resonator116.

The target device120may include a target resonator121, a rectifier122, a DC/DC converter123, a switch unit124, a charger125and a control unit126.

The AC/DC converter111may produce a DC voltage by rectifying an AC voltage having a bandwidth of several tens of Hz, which is output from a power supply112. The AC/DC converter111may output a certain level of DC voltage, or adjust an output level of the DC voltage under control of the control unit115.

The power detector113may detect a current and voltage output from the AC/DC converter111, and transmit information about the detected current and voltage to the control unit115. Further, the power detector113may detect a current and voltage input to the power converter114.

The power converter114may convert a DC voltage into an AC voltage in response to a switching pulse signal having a bandwidth ranging from several MHz to several tens of MHz to generate power. That is, the power converter114may convert a DC voltage into an AC voltage using a resonant frequency to generate “communication power” or “charging power” that is used in the target device120.

In this case, “communication power” may refer to energy for activating a communication module and a processor of the target device120. As a meaning of energy for activating, “communication power” may also be referred to as wake-up power.

The communication power may be transmitted for a predetermined period of time in the form of constant waves (CW). The “charging power” may refer to energy for charging a battery connected to the target device120or included in the target device120. The charging power may be transmitted continuously for a predetermined period of time, and may be transmitted at a power level higher than that of the “communication power.” For example, the power level of the communication power may be 0.1˜1 Watt, and the power level of the charging power may be 1˜20 Watt.

The control unit115may control a frequency of a switching pulse signal. The frequency of the switching pulse signal may be determined by the control unit115. The control unit115may generate a modulation signal for transmission to the target device120by controlling the power converter114. That is, the control unit115may transmit various messages to the target device120through an in-band communication. Further, the control unit115may detect a reflected wave and demodulate a signal received from the target device120through an envelope of the reflected wave.

The control unit115may generate a modulation signal for performing in-band communication by various methods. The control unit115may generate a modulation signal by turning on/off a switching pulse signal. Further, the control unit115may generate a modulation signal by performing a delta-sigma modulation. The control unit115may generate a pulse width modulation signal having a constant envelope.

The control unit115may perform an out-of-band communication using a separate communication channel rather than the resonant frequency. The control unit115may include a communication module such as Zigbee™ and/or Bluetooth™ technology. The control unit115may transmit/receive data to/from the target device120through an out-of-band communication.

The source resonator116may transfer electromagnetic energy to the target resonator121. That is, the source resonator116may transfer communication power or charging power to the target device120through magnetic coupling with the target resonator121.

The target resonator121may receive the electromagnetic energy from the source resonator116. That is, the target resonator121may receive the communication power or charging power from the source device110through magnetic coupling with the source resonator116. Further, the target resonator121may receive various messages from the source device110through in-band communication.

The rectifier122may generate a DC voltage by rectifying an AC voltage. That is, the rectifier122may rectify an AC voltage provided to the target resonator121through wireless communication.

Specifically, referring toFIG. 14, the rectifier122according to the present embodiment may include a full-bridge diode rectifier circuit. In this full-bridge diode rectifier circuit, there are two diodes in one path. That is, the current flowing through one path passes through two diodes.

The rectifier122may receive a first output (RF+) and a second output (RF−) of the target resonator121, and convert them into a third output (DC+). The first output (RF+) and the second output (RF−) may include differential signals output from the target resonator121. The first output (RF+) and the second output (RF−) may include RF differential input signals. The first output (RF+) may include a signal having a positive (+) phase. The second output (RF−) may include a signal having a negative (−) phase.

The third output (DC+) may include a signal output from the rectifier122after the signal is rectified by the rectifier122. In some embodiments of the present inventive concept, the third output (DC+) may include a DC voltage.

The rectifier122according to the present embodiment may include first to fourth Schottky diodes SD1to SD4, and a capacitor Cr.

As shown inFIG. 14, the anode electrode of the first Schottky diode SD1may be connected to an RF− connector, and the cathode electrode of the first Schottky diode SD1may be connected to a DC+ connector. The anode electrode of the second Schottky diode SD2may be connected to an RF+ connector, and the cathode electrode of the second Schottky diode SD2may be connected to the DC+ connector. The anode electrode of the third Schottky diode SD3may be connected to a ground, and the cathode electrode of the third Schottky diode SD3may be connected to the RF− connector. The anode electrode of the fourth Schottky diode SD4may be connected to the ground, and the cathode electrode of the fourth Schottky diode SD4may be connected to the RF+ connector.

The capacitor Cr may be connected between the DC+ connector and the ground. That is, one terminal of the capacitor Cr may be connected to the DC+ connector, and the other terminal of the capacitor Cr may be connected to the ground.

The semiconductor devices1to4according to the above-described embodiments of the present inventive concept may be employed as first to fourth Schottky diodes SD1to SD4. Accordingly, as described above, the insular impurity regions may be formed below the anode electrodes of the first to fourth Schottky diodes SD1to SD4.

Referring again toFIG. 13, the DC/DC converter123may adjust the level of the DC voltage output from the rectifier122to correspond to the capacity of the charger125. For example, the DC/DC converter123may adjust the level of the DC voltage output from the rectifier122to 3˜10 Volts.

The switch unit124may be turned on/off under the control of the control unit126. If the switch unit124is turned off, the control unit115of the source device110may detect a reflected wave. That is, if the switch unit124is turned off, the magnetic coupling between the source resonator116and the target resonator121may be removed.

In this embodiment, the charger125may include a battery. The charger125may charge the battery using the DC voltage output from the DC/DC converter123.

The control unit126may establish an in-band communication to transmit/receive data using the resonant frequency. In this case, the control unit126may demodulate a received signal by detecting a signal between the target resonator121and the rectifier122, or demodulate a received signal by detecting an output signal of the rectifier122. In other words, the control unit126may demodulate the messages received through in-band communication.

Further, the control unit126may modulate a signal to be transmitted to the source device110by adjusting the impedance of the target resonator121. Further, the control unit126may demodulate a signal to be transmitted to the source device110by turning on/off the switch unit124. For example, the control unit126may increase the impedance of the target resonator121such that a reflected wave can be detected in the control unit115of the source device110. The control unit115of the source device110may detect a binary number, i.e., “0” or “1”, depending on whether the reflected wave is generated.

The control unit126may perform an out-of-band communication using a communication channel. The control unit126may include a communication module such as Zigbee™ and/or Bluetooth™. The control unit126may exchange data with the source device110through the out-of-band communication.

FIG. 15is a block diagram of a semiconductor system according to another embodiment of the present inventive concept.

Referring toFIG. 15, the semiconductor system according to the present embodiment may include a battery410, a power management IC (PMIC)420and a plurality of modules431-434. The PMIC420converts a voltage provided from the battery410into a voltage having a level that is required for each of the modules431to434, and provides the voltage to each of the modules431to434. In this case, the PMIC420may include at least one of the semiconductor devices1to4according to the above-described embodiments of the present inventive concept.

FIG. 16is a block diagram of a semiconductor system according to still another embodiment of the present inventive concept.

Referring toFIG. 16, the semiconductor system according to the present embodiment includes a controller510, a PMIC512, a battery515, a signal processing unit523, an audio processing unit525, a memory unit530, a display unit550, and the like.

A keypad527may include keys for inputting numeric and text information and may further include function keys for setting various functions.

The signal processing unit523may perform a wireless communication function of a mobile terminal. In doing so, the signal processing unit523may include a RF unit and a modem. The RF unit may include a RF transmitter for frequency up-conversion and amplification of a transmitted signal, a RF receiver for low noise amplification and frequency down-conversion of a received signal, and the like. The modem may include a transmitter for coding and modulating a signal to be transmitted, a receiver for demodulating and decoding a signal to be received in the RF unit, and the like.

The audio processing unit525may include a codec. The codec may include a data codec and/or an audio codec. The data codec may process packet data and the like. The audio codec may process an audio signal such as a multimedia file and voice. Further, the audio processing unit525may convert a digital audio signal received from the modem into an analog audio signal through the audio codec, and reproduce the analog audio signal. Alternatively, or in addition, the audio processing unit525may convert an analog audio signal generated from a microphone into a digital audio signal through the audio codec, and transmit the digital audio signal to the modem. The codec may be provided separately, or be included in the controller510of the semiconductor system.

The memory unit530may include a read only memory (ROM) and a random access memory (RAM). The memory unit530include a program memory and data memories, and may store programs for controlling an operation of the mobile terminal and data for booting.

The display unit550may display a video signal and user data on a screen, or display data associated with calling. In this case, the display unit550may include a liquid crystal display (LCD) or organic light emitting diodes (OLEDs). In the case of implementing a LCD or OLEDs as a touch screen, the display unit550and the keypad527may be operated as an input unit to control the mobile terminal.

The controller510may serve to control the overall operation of the semiconductor system. The controller510may include the PMIC512as illustrated. The PMIC512may convert a voltage provided from the battery515into a voltage having a required level. Further, the PMIC512may rectify a signal such as an AC voltage provided from the outside into a DC voltage, and charge the battery515using the rectified DC voltage. In this case, the PMIC512may include at least one of the semiconductor devices1to4according to the above-described embodiments of the present inventive concept.

FIG. 17is a block diagram showing a configuration of an exemplary electronic system900in which a semiconductor system according to the embodiments of the present inventive concept can be employed.

Referring toFIG. 17, the electronic system900may include a memory system902, a processor904, a RAM906, a user interface908, a communication system912and a power management system914.

The memory system902, the processor904, the RAM906, the user interface908, the communication system912and the power management system914may perform a data communication with each other via a bus920or the like. In some embodiments of the present inventive concept, the bus920may be, for example, a multi-layer bus, but the present inventive concept is not limited thereto.

The processor904may be constructed and arranged to execute a program and control the electronic system900. The processor904may include at least one of at least one micro-processor, a digital signal processor, a micro-controller and logic devices capable of performing functions similar to those thereof. In some embodiments of the present inventive concept, the processor904may include an operation cache such as L1 and L2 to improve an operating speed.

The RAM906may be used an operating memory of the processor904. The RAM906may be formed of a volatile memory such as a DRAM.

Meanwhile, the processor904and the RAM906may be implemented to be packaged in one semiconductor device or semiconductor package. In some embodiments of the present inventive concept, the processor904and the RAM906may be implemented to be packaged in the form of Package on Package (PoP), but the present inventive concept is not limited thereto.

The user interface908may be used to exchange data with the electronic system900. As examples of the user interface908, there are a keypad, a keyboard, a touch sensor, a display device and the like. The user interface908may be implemented as an independent system in the electronic system900. For example, the keypad, the keyboard, the touch sensor, and/or the like may be implemented as an input system, and the display device may be implemented as a display system. The display system may include a data driving IC (DDIC) for driving the display device and the like.

The memory system902may include at least one non-volatile memory device for storing codes for the operation of the processor904, data processed by the processor904, and/or data input from the outside. The memory system902may include a separate controller for driving.

The controller may be configured to connect the host to the non-volatile memory device. In response to a request from the host, the controller may access the non-volatile memory device. For example, the controller may be configured to control read, write, erase and background operations of the non-volatile memory device.

The controller may be configured to provide an interface between the non-volatile memory device and the host. Further, the controller may be configured to drive firmware for controlling the non-volatile memory device.

As an example, the controller may further include well-known components such as a random access memory (RAM), a processing unit, a host interface and a memory interface. The RAM may be used as at least one of an operating memory of the processing unit, a cache memory between the host and the non-volatile memory device, and a buffer memory between the host and the non-volatile memory device. The processing unit may control the overall operation of the controller.

The host interface may include a protocol for performing data exchange between the host and the controller. The controller may be configured to communicate with an external device (host) through at least one of various interface protocols, e.g., a universal serial bus (USB) protocol, multimedia card (MMC) protocol, peripheral component interconnection (PCI) protocol, PCI-express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial-ATA protocol, parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, and integrated drive electronics (IDE) protocol. The memory interface may interface with the non-volatile memory device. For example, the memory interface may include a NAND interface or NOR interface.

The memory system902may be configured to include an error correction block. The error correction block may be configured to detect and correct a data error or the like at the memory system902using an error correction code (ECC). For example, the error correction block may be provided as a component of the above-described controller. However, the present inventive concept is not limited thereto, and the error correction block may be provided as a component of the non-volatile memory device.

In an information processing system such as a mobile device and desktop computer, a flash memory or other non-volatile memory device may be constructed and arranged as the memory system902. This flash memory may be configured as a solid state drive (SSD). In this case, the electronic system900may reliably store a large capacity of data in the flash memory or other memory device.

The memory system902may be integrated into a single semiconductor device. For example, the memory system902may be integrated into a single semiconductor device to form a memory card. As examples of the memory card, a PC card (PCMCIA, personal computer memory card international association), a compact flash card (CF), a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), and a universal flash storage (UFS) may be mentioned.

The memory system902may be mounted as various types of packages. For example, the memory system902may be mounted as a package such as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), thin quad flat pack (TQFP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), and wafer-level processed stack package (WSP).

The communication system912may process a communication between the electronic system900and an external device. The power management system914may manage power in the electronic system900. In the power management system914, the semiconductor system according to the above-described embodiments of the present inventive concept may be employed.

The electronic system900shown inFIG. 17may be applied to an electronic control unit of a variety of electronic devices.

FIG. 18is a diagram illustrating an example in which the electronic system900ofFIG. 17can be applied to a smart phone1000or related electronic device. In this case, a part of the electronic system shown inFIG. 13or the electronic system900ofFIG. 17may be constructed and arranged as an application processor (AP) implemented in the form of System On Chip (SoC).

The electronic system900(seeFIG. 17) may be employed in other electronic devices. For example, as shown inFIG. 19, the electronic system900ofFIG. 17can be applied to a tablet PC1100.FIG. 20shows an example in which the electronic system900ofFIG. 17is applied to a laptop1200.

The electronic system900(seeFIG. 17) may be provided as one of various components of an electronic device such as a computer, a ultra mobile personal computer (UMPC), a workstation, a net-book, a personal digital assistance (PDA), a portable computer (PC), a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device for transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, and/or one of various components constituting a computing system.

In the case where the electronic system900, for example, described with reference toFIG. 17, is an apparatus which can perform wireless communication, the electronic system900ofFIG. 17may be used in a communication system such as Code Division Multiple Access (CDMA), Global System for Mobile communication (GSM), North American Digital Cellular (NADC), Enhanced-Time Division Multiple Access (E-TDMA), Wideband Code Division Multiple Access (WCDAM), and/or CDMA2000 network.

FIGS. 21 to 24are diagrams showing intermediate steps of a method for fabricating a semiconductor device according to an embodiment of the present inventive concept.

First, referring toFIG. 21, the buried layer (NBL)20and the epitaxial layer (N-EPI)30are sequentially formed on a substrate (P-SUB)10.

The substrate10may include a semiconductor material. The substrate10may be made of at least one semiconductor material selected from the group consisting of, for example, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP. In the present embodiment, a conductive type of the substrate10may be, for example, a P type (P-SUB) substrate.

In some embodiments of the present inventive concept, the buried layer20may be formed at a boundary between the substrate10and the epitaxial layer30. More specifically, a portion of the buried layer20is formed on the substrate10and the remaining portion of the buried layer20is formed on the epitaxial layer30. In doing so, after the buried layer20is formed in the substrate10and the epitaxial layer30is formed on the substrate10, heat treatment may be performed. When the heat treatment is in progress, since the buried layer20is diffused into the substrate10and the epitaxial layer30, a portion of the buried layer20may be formed on the substrate10and the remaining portion of the buried layer20may be formed on the epitaxial layer30. In this embodiment, a conductive type of the buried layer20may be, for example, an N type. Further, in this embodiment, a conductive type of the epitaxial layer30may be, for example, an N type. In this case, the concentration of N-type impurities contained in the epitaxial layer30may be lower than the concentration of N-type impurities contained in the buried layer20. Further, in some embodiments of the present inventive concept, the buried layer20may be omitted.

Referring again to the method, atFIG. 22, a first mask M1is formed on the epitaxial layer30. Then, a plurality of first drift layers40are formed in the epitaxial layer30using the first mask M1. In this case, each of the first drift layers (N DRIFT)40may be formed as an insular impurity region. In other words, each of the first drift layers40may be formed such that a maximum cross-sectional diameter is equal to or less than 5 μm, and the impurity concentration in the region is 10 times to 1,000 times the impurity concentration of the epitaxial layer30.

In this embodiment, a conductive type of the first drift layers40may be, for example, an N type. Further, the concentration of N-type impurities contained in the first drift layers40may be, for example, 1e15 to 1e18 atoms/cm2, but the present inventive concept is not limited thereto.

Referring toFIG. 23, the element isolation film70is formed in the epitaxial layer30. Subsequently, a second mask M2is formed on the epitaxial layer30. Then, the second wells85are formed in the first drift layers40using the second mask M2. In this embodiment, a conductive type of the second wells85may be, for example, an N type.

Referring toFIG. 24, a third mask M3is formed on the epitaxial layer30. Subsequently, first wells80are formed in the epitaxial layer30using the third mask M3.

In this embodiment, a conductive type of the first wells80may be, for example, a P type. Accordingly, the first wells80and the epitaxial layer30may form a PN junction. Meanwhile, the concentration of impurities contained in the first wells80may be higher than the concentration of impurities contained in the substrate10.

As illustrated, the first wells80may be arranged to be separated from each other by the first drift layers40. Further, the first wells80may overlap the first drift layers40as illustrated. Meanwhile, the first wells80also may overlap an element isolation film70as illustrated. Further, the first wells80may be formed to be thinner than the first drift layers40. Specifically, as illustrated, the first wells80may be formed such that the depth of the lower surfaces of the first wells80is smaller than the depth of the lower surfaces of the first drift layers40.

Then, the semiconductor device1shown inFIG. 2may be fabricated by forming the third wells75(see for exampleFIG. 2) in the first wells80, forming a cathode electrode54(seeFIG. 2) on the second wells85to be in contact with the second wells85, and forming an anode electrode52(see for exampleFIG. 2) on the first drift layers40formed between the first wells80to be in contact with the third wells75(see for exampleFIG. 2).

If the arrangement of the cathode electrode54and the anode electrode52, for example, illustrated atFIG. 2is formed in a different way, the semiconductor device2shown inFIGS. 6 and 7may be fabricated.

FIGS. 25 to 27are diagrams showing intermediate steps for explaining a method for fabricating a semiconductor device according to another embodiment of the present inventive concept. The following description will be given focusing on differences from the above-described embodiment.

Referring toFIG. 25, a buried layer20, an epitaxial layer30and a first drift layer42are sequentially formed on a substrate10.

In this embodiment, the first drift layer42may be formed on the entire surface of the epitaxial layer30rather than being formed in the form of an insular impurity region as in the above-described embodiment.

Referring toFIG. 26, a fourth mask M4is formed on the first drift layer42. Subsequently, second drift layers82are formed in the first drift layer42using the fourth mask M4.

A conductive type of the second drift layers82may be, for example, a P type. Further, as illustrated, the first drift layer42may surround the second drift layers82. Accordingly, the second drift layers82and the first drift layer42may form a PN junction.

The concentration of impurities contained in the second drift layers82may be higher than the concentration of impurities contained in the substrate10. Specifically, the concentration of P-type impurities contained in the second drift layers82may be, for example, 1e14 to 1e18 atoms/cm2, but the present inventive concept is not limited thereto.

Then, referring toFIG. 27, the element isolation film70is formed in the first drift layer42. Subsequently, a fifth mask M5is formed on the first drift layer42. The body region84is formed in the first drift layer42using the fifth mask M5.

The body region84may be formed between the second drift layers82as illustrated. Further, the body region84may be formed to be thinner than the second drift layers82. Specifically, the body region84may be formed such that the depth of the lower surface of the body region84is smaller than the depth of the lower surfaces of the second drift layers82.

In this embodiment, the body region84may be formed in the form of an insular impurity region. In other words, the body region84may be formed such that a maximum cross-sectional diameter is equal to or less than 5 μm, and the impurity concentration in the region is 10 times to 1,000 times the impurity concentration of the first drift layer42.

A conductive type of the body region84may be, for example, a P type. Further, the concentration of P-type impurities contained in the body region84may be higher than the concentration of P-type impurities contained in the second drift layers82. Specifically, the concentration of P-type impurities contained in the body region84may be, for example, 1e16 to 1e20 atoms/cm2, but the present inventive concept is not limited thereto.

Then, the semiconductor device3shown inFIG. 10may be fabricated by forming the second wells85(see for example,FIG. 10) and the third wells75(see for exampleFIG. 10) in the first drift layer42, forming a cathode electrode54(see for exampleFIG. 10) on the second wells85(seeFIG. 10) to be in contact with the second wells85(see for example,FIG. 10), and forming an anode electrode52(see for exampleFIG. 10) on the body region84to be in contact with the third wells75

The semiconductor device4shown inFIG. 12may be fabricated by omitting the formation of the body region84and forming the second drift layers82as a plurality of insular impurity regions.