Semiconductor memory device

Disclosed is a semiconductor memory device capable of realizing reduction in an SRAM unit cell area. Using as a standard configuration a parallel-type SRAM unit cell having each pair of load transistors, driver transistors and transfer transistors, all or a part of the gate electrodes and active regions configuring at least any one of the pairs of the transistors, for example, the pair of the transfer transistors are configured obliquely in a predetermined direction from the standard configuration. As a result, a size in a cell outside part including the driver transistor and the transfer transistor is reduced. At the same time, a distance between the load transistors in the central part is reduced as compared with that in the standard configuration. Thus, area reduction in the whole SRAM unit cell is realized.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefits of priority from the prior Japanese Patent Application No. 2006-216578, filed on Aug. 9, 2006, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a static-type semiconductor memory device.

2. Description of the Related Art

A Static Random Access Memory (SRAM) as one type of volatile memory requires no refresh operation and has a high operation speed. Therefore, the SRAM is currently used in various devices. In recent years, higher speed up, miniaturization of unit cells and improvement in a degree of integration have progressed. Therefore, applications of the SRAM have more spread.

Herein, one example of conventional SRAM unit cells will be described with reference toFIGS. 12 to 15.FIGS. 12 to 15illustrate by an example an SRAM unit cell including a bulk layer having formed thereon a transistor and including first to third wiring layers sequentially formed on the bulk layer.

FIG. 12is an essential-part schematic plan view between a bulk layer and a first wiring layer of a conventional SRAM unit cell.FIG. 13is an essential-part schematic plan view between a bulk layer and a second wiring layer of a conventional SRAM unit cell.FIG. 14is an essential-part schematic plan view between a bulk layer and a third wiring layer of a conventional SRAM unit cell.FIG. 15is an equivalent circuit diagram of an SRAM unit cell.

An SRAM unit cell100comprises a total of six transistors composed of load transistors L1and L2, driver transistors D1and D2, and transfer transistors T1and T2.

These six transistors have the following configuration. For example, as shown inFIG. 12, a gate electrode101of the load transistor L1and the driver transistor D1, a gate electrode102of the load transistor L2and the driver transistor D2, and gate electrodes103and104of the transfer transistors T1and T2each have a linear shape in the major axis direction and are configured parallel to each other. Well region boundaries151and152have boundaries for injecting different conductivity-type impurities. In the left and right regions of these boundaries, P type well/N type transistors and N type well/P type transistors are configured in the well regions153and155and in the well region154, respectively.

Active regions105,106,107and108are extended in the direction perpendicular to the major axis direction of the gate electrodes101,102,103and104, respectively. The active regions105and106are configured to intersect the gate electrodes101and102, respectively. The active region107is configured to intersect the gate electrodes101and103. The active region108is configured to intersect the gate electrodes102and104.

On ends of the respective gate electrodes101,102,103and104as well as within the active regions105,106,107and108(a source/drain of each transistor) on both sides of the respective gate electrodes101,102,103and104, contact electrodes connected to each of the gate electrodes and active regions are configured. On the gate electrode101of the load transistor L1as well as within the active region106of the load transistor L2, for example, the contact electrodes using a shared contact technology are configured. Similarly, on the gate electrode102of the load transistor L2as well as within the active region105of the load transistor L1, for example, the contact electrodes using a shared contact technology are configured.

Each of the gate electrodes101,102,103and104and active regions105,106,107and108of the respective transistors is connected to a first wiring M1(chain line in the drawing) through the contact electrode.

Each of the respective first wirings M1is further connected to a second wiring M2(dotted line in the drawing) through the contact electrode, as shown inFIG. 13. Among these, the second wiring M2for connecting between the first wirings M1connected to the gate electrodes103and104of the transfer transistors T1and T2serves as a word line WL of the SRAM.

Each of the respective second wirings M2is further connected to a third wiring M3(dashed line in the drawing) through the contact electrode, as shown inFIG. 14. Through the third wiring, the load transistors L1and L2are connected to a power supply line Vcc, the driver transistors D1and D2are connected to a grounding line Vss and the transfer transistors T1and T2are connected to the bit lines BL1and BL2, respectively.

As a result, a circuit as shown inFIG. 15is realized.

Thus, the conventional SRAM unit cell generally has the following configuration. That is, the gate electrodes each have a linear shape and are configured parallel to each other. Further, the active regions are each extended linearly in the direction perpendicular to the gate electrodes and are configured parallel to each other. The SRAM unit cell using such a configuration is called as a “parallel-type unit cell” and has a merit that design and manufacture (process) are easy. In addition to the above merit, the unit cell further has a merit that by configuring the respective transistors in an orderly manner, reduction in a unit cell area and improvement in a degree of integration can be realized.

In the SRAM, further miniaturization of the unit cell is now desired strongly with spreading of its application and a demand for its large capacity.

In order to realize miniaturization of the SRAM, a SRAM unit cell having various configurations is recently proposed. For example, there is proposed the following SRAM unit cell. Gate electrodes and active regions are configured parallel to each other, respectively. Further, the gate electrodes and the active regions are configured obliquely to a word line and to bit line perpendicular thereto. Thus, the area reduction in the SRAM unit cell is realized (see, e.g., Japanese Unexamined Patent Application Publication No. Hei 10-335487). Further, there is proposed the following SRAM unit cell. Gate electrodes and active regions are configured obliquely between two parallel strip-shaped branch word lines (see, e.g., Japanese Unexamined Patent Application Publication No. Hei 6-169071). Further, there is proposed the following SRAM unit cell. A power supply line and a grounding line are configured parallel to each other as well as a word line is configured parallel to the power supply line and the grounding line. Then, each transistor is configured. Thus, a width in the word line direction is reduced (see, e.g., Japanese Unexamined Patent Application Publication No. Hei 8-97298).

In the case of a parallel-type SRAM unit cell heretofore widely used, area reduction thereof can be realized by using the following configuration. For example, gate electrodes and active regions are configured parallel to each other, respectively. At the same time, a distance therebetween is reduced within a technically-feasible range.

However, the following problems now occur upon a further miniaturization request of an SRAM unit cell. That is, it becomes difficult to reduce the unit cell area while securing a distance margin between a gate electrode of each transistor and a contact electrode connected to an active region of each transistor.

Further, it becomes difficult to secure the distance margin between constituents of different transistors only by simply reducing a distance between gate electrodes or between active regions. For example, in the above-described parallel-type SRAM unit cell, it becomes difficult to secure the distance margin between a gate electrode end of a transfer transistor and a shared contact electrode of a load transistor.

SUMMARY OF THE INVENTION

Therefore, one possible object is to provide a semiconductor memory device having a high-reliable and small unit cell.

In particular, an example embodiment of the improved semiconductor memory device includes a unit cell including first and second load transistors configured in a central part and including a first driver transistor and a first transfer transistor as well as a second driver transistor and a second transfer transistor configured on each side of the central part, wherein: using as a standard configuration a cell configuration in which a first gate electrode of the first load transistor and the first driver transistor, a second gate electrode of the second load transistor and the second driver transistor, a third gate electrode of the first transfer transistor, the third gate electrode being configured in a major axis direction of the second gate electrode, and a fourth gate electrode of the second transfer transistor, the fourth gate electrode being configured in a major axis direction of the first gate electrode, each have a linear shape and are configured parallel to each other, and first and second active regions each having formed therein the first and second gate electrodes, a third active region having formed therein the first and third gate electrodes, and a fourth active region having formed therein the second and fourth gate electrodes are each extended linearly in the direction perpendicular to the major axis direction of the first to fourth gate electrodes and are configured parallel to each other, gate electrodes and active regions of at least any one of the pairs of transistors selected from a pair of the first and second load transistors, a pair of the first and second driver transistors, and a pair of the first and second transfer transistors are configured obliquely from the standard configuration.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout.

FIGS. 1A,1B,1C and1D are explanatory drawings of a basic functional configuration.FIG. 1Ais an essential-part schematic plan view of a normally designed transistor.FIG. 1Bis an essential-part schematic plan view of a transistor obtained by the manufacturing based on the design ofFIG. 1A.FIG. 1Cis an essential-part schematic plan view of an obliquely configured and designed transistor.FIG. 1Dis an essential-part schematic plan view of a transistor obtained by the manufacturing based on the design ofFIG. 1C.

As shown inFIG. 1A, a transistor10has the following configuration. A gate electrode11linearly extending in the horizontal direction in the drawing is configured, and active region12extending in the direction (gate length direction) perpendicular to a major axis direction of the electrode11is configured to intersect the electrode11. Further, on an end of the gate electrode11as well as within the active regions12on both sides of the electrode11, contact electrodes13a,13band13cconnected to each of the electrode11and regions12are configured.

In designing such a transistor10, the configuration of the respective contact electrodes13band13cis determined such that a constant distance (e.g., a distance in a minimum design rule) X is secured between the gate electrode11and each of the contact electrodes13band13con both sides of the gate electrode11.

This is because when the constant distance X is not secured, the following problem occurs. In actually performing manufacturing based on the design, when displacement occurs in a formed position of the gate electrode11or in a formed position of a contact hole, a short circuit may occur between the gate electrode11and each of the contact electrodes13band13c(active regions12). Accordingly, in order to avoid occurrence of the short circuit even if such displacement occurs, the contact electrodes13band13care configured while securing the constant distance X with the gate electrode11.

When actually performing manufacturing based on such a design, any of the gate electrode11, the active region12and the contact electrodes13a,13band13cwhich are configured (drawn) in a rectangle shape in terms of design are formed to have rounded corners as shown inFIG. 1B. Particularly, the contact electrodes13a,13band13chave a circular shape depending on sizes thereof.

On the other hand, the transistor10shown inFIG. 1Cis a transistor obtained by obliquely designing the transistor10shown inFIG. 1A(by designing the transistor10obliquely only by an angle of θ). The transistor10has the following configuration. The gate electrode11linearly extending is obliquely configured, and the active region12is configured in the direction perpendicular to the major axis direction of the gate electrode11. Further, on an end of the gate electrode11as well as within the active region12, the contact electrodes13a,13band13cconnected to each of the electrode11and regions12are configured.

In the case of obliquely configuring and designing the transistor10, the rectangular contact electrodes13a,13band13care configured (drawn) without being designed obliquely for convenience of design. Therefore, in a stage of design, the gate electrode11and each of the contact electrodes13band13chave a configuration relationship in which a distance therebetween is shorter than the distance X shown inFIGS. 1A and 1B.

When actually performing manufacturing based on the design ofFIG. 1C, the gate electrode11, active region12, and contact electrodes13a,13band13ceach having rounded corners are formed as shown inFIG. 1D. At this time, each of the contact electrodes13a,13band13cis formed to a round shape. Therefore, between the gate electrode11and each of the contact electrodes13band13chaving a configuration relationship in which a distance therebetween is shorter than the distance X in a stage of design, a constant distance X is secured after actual formation.

ComparingFIGS. 1B and 1D, the transistor10inFIG. 1Dhas a configuration in which the transistor10inFIG. 1Bis configured obliquely by an angle θ. However, when the transistor10is manufactured to have a configuration as shown inFIG. 1B, spaces such as regions14aand14bexist in terms of the layout. When the transistor10is configured obliquely from a state ofFIG. 1Bto that ofFIG. 1D, such regions14aand14bcan be efficiently used in terms of the layout.

Specifically, when the transistor10is configured obliquely from a state ofFIG. 1Bto that ofFIG. 1Don the basis of a center position of the contact electrode13b, a part of the gate electrode11and of the active region12can be configured using the regions14aand14b. At this time, the center position of the contact electrode13cis shifted by a distance Y in the downward direction in the drawing. As a result, size reduction in the vertical direction in the drawing can be realized without reducing the distance X between the gate electrode11and each of the contact electrodes13band13c.

When the transistor10is thus configured obliquely, the center position of the contact electrode13aconnected to the gate electrode11is shifted by a distance Z in the left direction in the drawing.

The size reduction effect in the vertical direction in the drawing as shown inFIG. 1becomes more remarkable when plural transistors are adjacent to each other.

When the transistor10is included in a specific unit cell, for example, in a unit cell which is long in the horizontal direction in the drawing and is short in the vertical direction in the drawing, the following effect is provided. When making a comparison in terms of areas, even if the size in the horizontal direction in the drawing increases, the size reduction effect in the vertical direction in the drawing is apt to be larger than the size increase effect in the horizontal direction in the drawing.

FIGS. 2 and 3are explanatory drawings of the size reduction effect in adjacent transistors.

For example, assume that two transistors20and30are configured adjacent to each other as shown inFIGS. 2 and 3. Herein, the transistors20and30have the following configuration. Each of linear gate electrodes21and31is formed to intersect an active region40. On ends of the gate electrodes21and31, contact electrodes21aand31aare formed, respectively. Within the active region40, contact electrodes41a,41band41care formed.

FIG. 2shows a configuration in which one transistor20of the adjacent transistors20and30is configured obliquely by an angle θ from the standard configuration (This configuration means a configuration in which the transistor20is not configured obliquely. InFIG. 2, this configuration is shown by a dotted line.). At this time, the gate electrodes21and31have a non-parallel configuration relationship. Further, the active region40has not a linear shape but a curved shape in the region between the gate electrodes21and31. By adopting such a configuration, the position of the contact electrode41ccan be shifted in the downward direction in the drawing while keeping a distance between the contact electrode41cand the gate electrode21. Accordingly, a size S between the adjacent transistors20and30in the vertical direction in the drawing can be reduced as compared with that in the standard configuration.

FIG. 3shows a configuration in which both of the adjacent transistors20and30are configured obliquely by an angle θ in the direction opposite each other away from the standard configuration (This configuration means a configuration in which the transistors20and30are not configured obliquely. InFIG. 3, this configuration is shown by a dotted line.). At this time, the gate electrodes21and31have a non-parallel configuration relationship. Further, the active region40in the region between the gate electrodes21and31has a more curved shape than that ofFIG. 2. By adopting such a configuration, the position of the contact electrode41ccan be shifted in the downward direction in the drawing while keeping a distance between the contact electrode41cand the gate electrode21. At the same time, the position of the contact electrode41acan be shifted in the upward direction in the drawing while keeping a distance between the contact electrode41aand the gate electrode31. Accordingly, a size S between the adjacent transistors20and30in the vertical direction in the drawing can be more reduced as compared with that in the standard configuration.

As described above, by adopting a configuration in which the transistor is configured obliquely by a constant angle θ from the standard configuration, size reduction in a predetermined direction can be realized while securing a distance margin between the gate electrode and the contact electrode.

Herein, the angle θ is set in the range of 0°<θ≦45°. When the angle θ is more than 45°, the following disadvantages occur. That is, there is an increasing possibility that interference among constituents occurs in terms of the layout. Further, the need to largely change the layout of wirings formed on an upper layer may arise. When the angle θ is set in the relatively small range of 45° or less, the following advantages are provided. That is, the interference among constituents or the problem in layout change can be avoided. Therefore, no significant difficulty is encountered in obliquely configuring and designing a transistor. Further, no significant difficulty is encountered also in manufacturing a transistor based on the design.

In the above description, there is described a case where the whole one transistor, more specifically, both of the gate electrode and active region constituting the transistor are configured obliquely by a constant angle θ. In addition, the following case is possible. In one transistor, only the active region or only the gate electrode is obliquely configured in consideration of a distance margin between the gate electrode and the contact electrode.

In the case where only the active region is obliquely configured in consideration of a distance margin between the gate electrode and the contact electrode, size reduction in the direction perpendicular to the major axis direction of the gate electrode can be realized according to the above example.

In the case where only the gate electrode is obliquely configured in consideration of a distance margin between the gate electrode and the contact electrode, size reduction can be realized depending on the configuration of the transistor. Further, other transistor constituents can also be configured on an empty space formed by obliquely configuring the gate electrode. This point will be described later.

Further, the following case is also possible. In one transistor, only apart of the gate electrode (e.g., a protruded part from the active region) is obliquely configured without changing a configuration of an essential-part of the gate electrode as well as a configuration of the active region. Also in this case, other transistor constituents can be configured on an empty space formed by obliquely configuring a part of the gate electrode. This point will be described later.

A case of applying the above-described principle to an SRAM will be described in detail below.

A first application example will be first described.

FIG. 4is an essential-part schematic plan view of a standard parallel-type SRAM unit cell.FIG. 5is an essential-part schematic plan view of an SRAM unit cell of the first application example.

First, a standard cell configuration (standard configuration) will be described with reference toFIG. 4.

As shown inFIG. 4, a standard SRAM unit cell50acomprises a total of six transistors composed of load transistors L1and L2configured in the central part, driver transistors D1and D2and transfer transistors T1and T2configured outside of the central part. Well region boundaries161and162have boundaries for injecting different conductivity-type impurities. In the left and right regions of these boundaries, different conductivity-type transistors are configured. The driver transistors D1and D2and transfer transistors T1and T2in the well regions163and165are configured as an N-type transistor. The load transistors L1and L2in the well region164are configured as a P-type transistor.

These six transistors have the following configuration. A gate electrode51of the load transistor L1and the driver transistor D1, a gate electrode52of the load transistor L2and the driver transistor D2, and gate electrodes53and54of the transfer transistors T1and T2each have a linear shape in the major axis direction and are configured parallel to each other.

Active regions55,56,57and58are extended in the direction perpendicular to the major axis direction of the gate electrodes51,52,53and54, respectively. The active region55is configured to intersect the gate electrode51. The active region56is configured to intersect the gate electrode52. The active region57is configured to intersect the gate electrodes51and53. The active region58is configured to intersect the gate electrodes52and54.

On ends of the respective gate electrodes51,52,53and54as well as within the active regions55,56,57and58on both sides of the respective gate electrodes51,52,53and54, contact electrodes59ato59lconnected to each of the gate electrodes and active regions are configured.

Both of the contact electrodes59aand59dof the load transistors L1and L2are connected to a power supply line Vcc in the upper layer. That is, sources of the load transistors L1and L2are connected to the power supply line Vcc.

Both of the contact electrodes59eand59jof the driver transistors D1and D2are connected to a grounding line Vss in the upper layer. That is, sources of the driver transistors D1and D2are connected to the grounding line Vss.

The contact electrode59gof the transfer transistor T1is connected to a first bit line BL1in the upper layer, and the contact electrode59hof the transfer transistor T2is connected to a second bit line BL2in the upper layer. That is, a source of the transfer transistor T1is connected to the first bit line BL1, and a source of the transfer transistor T2is connected to the second bit line BL2.

The contact electrodes59kand59lconnected to the gate electrodes53and54of the transfer transistors T1and T2are connected to a common word line WL in the upper layer.

A shared contact technology is applied to the contact electrodes59band59cconnected to the gate electrodes52and51. The contact electrode59bis connected to the contact electrode59fin the upper layer, and the contact electrode59cis connected to the contact electrode59iin the upper layer. In other words, the gate electrode52of the load transistor L2and the driver transistor D2is connected to each drain of the load transistor L1, the driver transistor D1and the transfer transistor T1. Further, the gate electrode51of the load transistor L1and the driver transistor D1is connected to each drain of the load transistor L2, the driver transistor D2and the transfer transistor T2.

As a result, a circuit as shown inFIG. 15is realized.

When a cell configuration of the SRAM unit cell50aas shown inFIG. 4is used as a standard configuration, an SRAM unit cell50shown inFIG. 5has the following configuration. That is, the transfer transistors T1and T2are configured obliquely in the counterclockwise direction in the drawing without changing an electrical connection relationship among constituents (seeFIG. 2).

Therefore, sizes in the transfer transistor T1and driver transistor D1in the vertical direction in the drawing as well as sizes in the transfer transistor T2and driver transistor D2in the vertical direction in the drawing are reduced as compared with those in the standard configuration.

Further, the SRAM unit cell50shown inFIG. 5has the following configuration. That is, accompanying such miniaturization of outside portions, a distance between the load transistors L1and L2in the central part is reduced as compared with that in the SRAM unit cell50ashown inFIG. 4.

Specifically, sizes of the active regions55and56are appropriately changed to bring the gate electrode51and the contact electrode59ccloser to the gate electrode52side or to bring the gate electrode52and the contact electrode59bcloser to the gate electrode51side. Between the gate electrode51and the contact electrode59bas well as between the gate electrode52and the contact electrode59c, a space allowing such a configuration change to be performed is left even in the standard configuration.

Thus, the size reduction in the outside portion, namely, the size reduction in the transfer transistor T1and driver transistor D1in the vertical direction in the drawing as well as in the transfer transistor T2and driver transistor D2in the vertical direction in the drawing is performed. Further, a distance between the load transistors L1and L2is reduced such that the contact electrodes59a,59eand59has well as the contact electrodes59d,59gand59jare configured on the cell boundary line and at the same time, the gate electrodes51and52are configured parallel to each other.

By adopting such a configuration, a size in the short-side direction (in the vertical direction in the drawing) of the SRAM unit cell50shown inFIG. 5, which is viewed as a cell having a planar rectangular shape, can be reduced as compared with that in the SRAM unit cell50ashown inFIG. 4.

At this time, a size in the long-side direction (in the horizontal direction in the drawing) increases slightly. However, since the SRAM unit cell50has a long rectangular shape in the horizontal direction in the drawing, the amount of reduction in the cell area due to the size reduction in the short-side direction exceeds the amount of increase in the cell area due to the size increase in the long-side direction. As a result, reduction in the cell area can be realized.

Even in the case of thus configuring obliquely the transfer transistors T1and T2, displacement in the contact electrodes59gand59hof the active regions57and58as well as in the contact electrodes59kand59lof the gate electrodes53and54is relatively small. Therefore, wirings connected to the contact electrodes in the upper layer may be configured according to oblique angles of the transfer transistors T1and T2while undergoing a parallel movement from positions in the case of not configuring the transistors T1and T2obliquely. This is also true for the first and second bit lines BL1and BL2, and the word line WL. Accordingly, in configuring the SRAM unit cell60as shown inFIG. 5, a large design change is unnecessary for the wiring structure of the upper layer.

Next, a second application example will be described.

FIG. 6is an essential-part schematic plan view of an SRAM unit cell of the second application example. InFIG. 6, the same elements as those shown inFIGS. 4 and 5are indicated by the same reference numerals as inFIGS. 4 and 5and the detailed description is omitted.

When a cell configuration of the SRAM unit cell50aas shown inFIG. 4is used as a standard configuration, an SRAM unit cell60shown inFIG. 6has the following configuration. That is, the load transistors L1and L2are configured obliquely in the counterclockwise direction in the drawing without changing an electrical connection relationship among constituents. At this time, the gate electrodes61and62are formed in a shape corresponding to the configuration relationship between the driver transistor D1and the obliquely configured load transistor L1as well as between the driver transistor D2and the obliquely configured load transistor L2, respectively. A distance between the load transistors L1and L2is set such that the contact electrodes59a,59eand59has well as the contact electrodes59d,59gand59jare configured on the cell boundary line.

Further, the SRAM unit cell60shown inFIG. 6has the following configuration. That is, the driver transistor D1and the transfer transistor T1as well as the driver transistor D2and the transfer transistor T2are configured closer to the load transistor L1and L2sides, respectively, than those of the standard configuration.

Thus, in the SRAM unit cell60shown inFIG. 6, the load transistors L1and L2in the central part are configured obliquely. By doing so, as compared with the case where the transistors L1and L2are not configured obliquely, new spaces can be formed with the outer driver transistor D1and transfer transistor T1as well as with the outer driver transistor D2and transfer transistor T2.

Further, using the empty spaces, the driver transistors D1and D2as well as the transfer transistors T1and T2are configured. By doing so, the size in the horizontal direction in the drawing can be reduced as compared with that in the SRAM unit cell50ashown inFIG. 4. As a result, the cell area can be reduced.

In configuring the SRAM unit cell60shown inFIG. 6, a large design change is unnecessary for the wiring structure of the upper layer.

Next, a third application example will be described.

FIG. 7is an essential-part schematic plan view of the SRAM unit cell of the third application example. InFIG. 7, the same elements as those shown inFIGS. 4 and 5are indicated by the same reference numerals as inFIGS. 4 and 5and the detailed description is omitted.

When a cell configuration of the SRAM unit cell50aas shown inFIG. 4is used as a standard configuration, an SRAM unit cell70shown inFIG. 7has the following configuration. That is, without changing an electrical connection relationship among constituents, the transfer transistors T1and T2are configured obliquely in the counterclockwise direction in the drawing as well as the load transistors L1and L2are configured obliquely in the counterclockwise direction in the drawing. Further, using spaces formed by configuring obliquely the load transistors L1and L2, the driver transistors D1and D2as well as the transfer transistors T1and T2are configured.

The gate electrodes71and72are formed in a shape corresponding to the configuration relationship between the driver transistor D1and the obliquely configured load transistor L1as well as between the driver transistor D2and the obliquely configured load transistor L2, respectively. A distance between the load transistors L1and L2is set such that the contact electrodes59a,59eand59has well as the contact electrodes59d,59gand59jare configured on the cell boundary line.

Thus, in the SRAM unit cell70shown inFIG. 7, the size reduction in the vertical direction in the drawing is realized by obliquely configuring the transfer transistors T1and T2. At the same time, the size reduction in the horizontal direction in the drawing is realized by obliquely configuring the load transistors L1and L2. As a result, the cell area is reduced.

In configuring the SRAM unit cell70shown inFIG. 7, a large design change is unnecessary for the wiring structure of the upper layer.

Next, a fourth application example will be described.

FIG. 8is an essential-part schematic plan view of the SRAM unit cell of the fourth application example. InFIG. 8, the same elements as those shown inFIGS. 4 and 5are indicated by the same reference numerals as inFIGS. 4 and 5and the detailed description is omitted.

When a cell configuration of the SRAM unit cell50aas shown inFIG. 4is used as a standard configuration, an SRAM unit cell80shown inFIG. 8has the following configuration. That is, without changing an electrical connection relationship among constituents, the transfer transistors T1and T2are configured obliquely in the counterclockwise direction in the drawing as well as the driver transistors D1and D2are configured obliquely in the clockwise direction in the drawing (seeFIG. 3).

The gate electrodes81and82are formed in a shape corresponding to the configuration relationship between the obliquely configured driver transistor D1and the load transistor L1as well as between the obliquely configured driver transistor D2and the load transistor L2, respectively. Further, the SRAM unit cell80shown inFIG. 8has the following configuration. That is, as compared with the case in the SRAM unit cell50ashown inFIG. 4, a distance between the load transistors L1and L2is reduced such that the contact electrodes59a,59eand59has well as the contact electrodes59d,59gand59jare configured on the cell boundary line.

Thus, in the SRAM unit cell80shown inFIG. 8, the transfer transistors T1and T2and the driver transistors D1and D2are each configured obliquely in the predetermined direction and the distance between the load transistors L1and L2is reduced, whereby the size reduction in the vertical direction in the drawing is realized. Therefore, even if a size in the long-side direction of the rectangular SRAM unit cell80slightly increases, a size in the short-side direction thereof is reduced. As a result, the cell area can be effectively reduced.

In configuring the SRAM unit cell80shown inFIG. 8, a large design change is unnecessary for the wiring structure of the upper layer.

Next, a fifth application example will be described.

FIG. 9is an essential-part schematic plan view of an SRAM unit cell of the fifth application example. InFIG. 9, the same elements as those shown inFIGS. 4 and 5are indicated by the same reference numerals as inFIGS. 4 and 5and the detailed description is omitted.

When a cell configuration of the SRAM unit cell50aas shown inFIG. 4is used as a standard configuration, an SRAM unit cell90shown inFIG. 9has the following configuration. That is, without changing an electrical connection relationship among constituents, the transfer transistors T1and T2are configured obliquely in the counterclockwise direction in the drawing, the driver transistors D1and D2are configured obliquely in the clockwise direction in the drawing and at the same time, the load transistors L1and L2are configured obliquely in the counterclockwise direction in the drawing. Further, using spaces formed by obliquely configuring the load transistors L1and L2, the driver transistors D1and D2as well as the transfer transistors T1and T2are configured.

The gate electrodes91and92are formed in a shape corresponding to the configuration relationship between the obliquely configured driver transistor D1and load transistor L1as well as between the obliquely configured driver transistor D2and load transistor L2, respectively. A distance between the load transistors L1and L2is set such that the contact electrodes59a,59eand59has well as the contact electrodes59d,59gand59jare configured on the cell boundary line.

Thus, in the SRAM unit cell90shown inFIG. 9, the size reduction in the vertical direction in the drawing is realized by obliquely configuring the transfer transistors T1and T2and the driver transistors D1and D2. At the same time, the size reduction in the horizontal direction in the drawing is realized by obliquely configuring the load transistors L1and L2. As a result, the cell area is reduced.

In the case of the SRAM unit cell90shown inFIG. 9, the cell area reduction of at least about 5% can be realized as compared with that in the SRAM unit cell50ashown inFIG. 4.

In configuring the SRAM unit cell90shown inFIG. 9, a large design change is unnecessary for the wiring structure of the upper layer.

Next, a sixth application example will be described.

FIG. 10is an essential-part schematic plan view of an SRAM unit cell of the sixth application example. InFIG. 10, the same elements as those shown inFIG. 6are indicated by the same reference numerals as inFIG. 6and the detailed description is omitted.

An SRAM unit cell60ashown inFIG. 10has the following configuration. That is, ends of the gate electrodes53aand54aof the transfer transistors T1and T2are configured obliquely in the direction apart from the contact electrodes59band59c, respectively. In this point, the SRAM unit cell60adiffers from the SRAM unit cell60of the second application example shown inFIG. 6.

According to the above-described SRAM unit cell60a, the driver transistor D1and the transfer transistor T1as well as the driver transistor D2and the transfer transistor T2are configured closer to the load transistor L1and L2sides while securing a distance margin between the end of the gate electrode53aand the contact electrode59bas well as between the end of the gate electrode54aand the contact electrode59c, respectively.

Next, a seventh application example will be described.

FIG. 11is an essential-part schematic plan view of an SRAM unit cell of the seventh application example. InFIG. 11, the same elements as those shown inFIG. 6are indicated by the same reference numerals as inFIG. 6and the detailed description is omitted.

An SRAM unit cell60bshown inFIG. 11has the following configuration. That is, all of the gate electrodes53band54bof the transfer transistors T1and T2are configured obliquely in the direction apart from the contact electrodes59band59c, respectively. In this point, the SRAM unit cell60bdiffers from the SRAM unit cell60of the second application example shown inFIG. 6.

According to the above-described SRAM unit cell60b, in the same manner as in the sixth application example, the driver transistor D1and the transfer transistor T1as well as the driver transistor D2and the transfer transistor T2are configured closer to the load transistor L1and L2sides while securing a distance margin between the end of the gate electrode53aand the contact electrode59bas well as between the end of the gate electrode54aand the contact electrode59c, respectively.

Further, in comparison with the gate electrodes53aand54aof the sixth application example, even if displacement in the horizontal direction in the drawing occurs on the gate electrodes53band54b, the configuration relationship among constituents in the transfer transistors T1and T2is not greatly changed. Therefore, a constant characteristic can be stably obtained.

As described above, using as a standard configuration the parallel-type unit cell having each pair of the load transistors, the driver transistors and the transfer transistors, at least any one of the pairs of the transistors is configured obliquely from the standard configuration. In the pair of the obliquely configured transistors, a constant distance, for example, a minimum rule distance in design and in processing is secured between the gate electrode and the contact electrode formed in the active region. As a result, reduction in the SRAM unit cell can be realized without impairing reliability. Therefore, a high-reliable and small SRAM can be realized. In addition, an SRAM suppressed in size and improved in a degree of integration can be realized.

In the present invention, using as a standard configuration the parallel-type unit cell having each pair of the load transistors, the driver transistors and the transfer transistors, at least any one of the pairs of the transistors is configured obliquely from the standard configuration. As a result, reduction in the SRAM unit cell can be realized without impairing reliability. Therefore, a small semiconductor memory device can be realized or a semiconductor memory device suppressed in size and improved in a degree of integration can be realized.