DISPLAY PANELS

A display panel includes pixel circuitry disposed on a substrate. The pixel circuitry includes a plurality of transistor groups and a plurality of signal line groups. The plurality of transistor groups are divided into a plurality of transistor group columns by the signal line groups. Each transistor group is disposed between two adjacent signal line groups. Each signal line group includes a power supply signal line and a first data signal line. The power supply signal line at least partially overlaps the first data signal line in a thickness direction of the display panel. The power supply signal line is provided with at least one through hole. The first data signal line overlaps the through hole in the thickness direction.

TECHNICAL FIELD

The present application relates to display technologies, and more particularly, to display panels.

BACKGROUND

With the development of display technology, a display panel has been widely used in people's lives, such as in a display screen of a cell phone, a computer, a television, or the like. With the development of life and technology, requirements for display performance of the display panel are increased, the resolution of the display panel is increased, the number of lines in wiring in the display panel is increased, and the wiring becomes denser. In particular, in an organic light-emitting diode (OLED) display panel, light-emitting devices are driven by a complex pixel drive circuit, and thus the wiring in the organic light-emitting display panel further becomes denser.

However, due to the denser wiring in the current display panel, there are overlaps between lines of different potentials in a thickness direction of the display panel, and large parasitic capacitances are generated at the overlaps, so that signal crosstalk (interference) occurs between different lines, thereby reducing the display quality of the display panel.

SUMMARY

In view of the above, an embodiment of the present application provides a display panel including a substrate and pixel circuitry disposed on the substrate, wherein the pixel circuitry comprises a plurality of transistor groups and a plurality of signal line groups, each of the signal line groups comprises a power supply signal line and a first data signal line both extending in a first direction, the plurality of transistor groups are divided into a plurality of transistor group columns by the signal line groups, each of the signal line groups is disposed between two adjacent ones of the transistor group columns, and each of the transistor groups is disposed between two adjacent ones of the signal line groups; andin each of the signal line groups, a width of the power supply signal line is greater than a width of the first data signal line, the power supply signal line at least partially overlaps the first data signal line in a thickness direction of the display panel, a part of the power supply signal line overlapping the first data signal line is provided with at least one through hole, and the first data signal line overlaps the through hole in the thickness direction of the display panel.

Alternatively, in some embodiments of the present application, each of the signal line groups further comprises a second data signal line, and in each of the signal line groups, the second data signal line and the first data signal line are arranged side by side in parallel, and the second data signal line does not overlap the power supply signal line in the thickness direction of the display panel.

Alternatively, in some embodiments of the present application, the first data signal line and the second data signal line respectively in every two adjacent ones of the signal line groups are configured to drive ones of the transistor groups respectively in different rows each being in a second direction perpendicular to the first direction, the first data signal line and the second data signal line in each of the signal line groups are configured to drive ones of the transistor groups in a same row in the second direction, and each of the transistor groups is coupled to one of the first data signal line and the second data signal line.

Alternatively, in some embodiments of the present application, the first data signal line is straight, and the power supply signal line is not straight.

Alternatively, in some embodiments of the present application, the power supply signal line comprises a first segment and a second segment both extending in the first direction, and a third segment connected between the first segment and the second segment, the first segment being not aligned with the second segment, in each of the signal line groups, the first segment overlaps the first data signal line in the thickness direction of the display panel, the through hole is disposed in the first segment, and the second segment does not overlap the first data signal line in the thickness direction of the display panel.

Alternatively, in some embodiments of the present application, the through hole extends in the first direction.

Alternatively, in some embodiments of the present application, a width of the through hole in a second direction perpendicular to the first direction is greater than the width of the first data signal line.

Alternatively, in some embodiments of the present application, a distance between two outermost edges of the first segment away from the through hole in a second direction perpendicular to the first direction is greater than a width of the second segment.

Alternatively, in some embodiments of the present application, the display panel has a layer structure includes:an active layer disposed on the substrate, the active layer comprising semiconductor layers respectively corresponding to a plurality of thin film transistors;a first metal layer disposed on a side of the active layer away from the substrate, wherein the first metal layer comprises a source, a drain, and the power supply signal line, and the source and the drain are at least electrically connected to one of the semiconductor layers corresponding to one of the thin film transistors;a first insulating layer disposed on a side of the first metal layer away from the substrate; anda second metal layer disposed on a side of the first insulating layer away from the substrate, the second metal layer comprising the first data signal line.

Alternatively, in some embodiments of the present application, a material of the first metal layer is same as that of the second metal layer, and a thickness of the first metal layer is greater than a thickness of the second metal layer.

Alternatively, in some embodiments of the present application, the first metal layer comprises a laminate of titanium-layer/aluminum-layer/titanium-layer, and a thickness of the aluminum-layer is greater than or equal to 7000 angstroms.

Alternatively, in some embodiments of the present application, a width of a part of the first segment at either side of the through hole in a second direction perpendicular to the first direction is greater than or equal to 1.9 microns.

DETAILED DESCRIPTION

Technical solutions in embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are merely a portion of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without involving any inventive effort are within the scope of the present application. Furthermore, it is to be understood that the embodiments described herein are for illustration and explanation only and are not intended to limit the application. In the present application, unless indicated to the contrary, the use of positional terms such as “upper” and “lower” are generally used to refer to upper and lower parts of the device in actual use or operation, in an embodiment, the orientation of the drawing. However, “inner/inside” and “outer/outside” refer to the contours of the device.

FIG.1is a schematic top view of a portion of wiring in a display panel in the related art. As the resolution of the display panel is increased, the number of lines in the wiring in the display panel is increased, and the wiring in the display panel becomes denser.FIG.1illustrates that both a power supply signal line and a first data signal line222overlap a transistor group301in a thickness direction of the display panel in the related art. It is easy to understand that the transistor group may include a plurality of thin film transistors of a driving circuit, and the power supply signal line does not overlap the first data signal line222in the thickness direction of the display panel. such a design results in a coupling capacitance between an element such as an electrode in the transistor group301and the power supply signal line and a coupling capacitance between an element such as an electrode in the transistor group301and the first data signal line222. An electric signal through an element such as an electrode in the transistor group301and an electric signal through the power supply signal line are influenced by each other, and an electric signal through an element such as an electrode in the transistor group301and an electric signal through the first data signal line222are influenced by each other, so that the electric signal through the power supply signal line and the electric signal through the first data signal line222both have a degraded phenomenon such as the signal delay.

FIG.2is a schematic top view of a portion of wiring according to a first initial design by the inventors. Based on the above problem inFIG.1, the power supply signal line and the first data signal line222are provided on a same side of the transistor group301. Therefore, the power supply signal line and the first data signal line222do not overlap the transistor group in the thickness direction of the display panel. However, due to the greater resolution of the display panel, a layout space (or layout) of the display panel is limited, and the power supply signal line and the first data signal line222may not be expected to be arranged with the overlap in the thickness direction of the display panel, that is, there is not enough space on the layout to set the design inFIG.2.

FIG.3is a schematic top view of a portion of wiring according to a second initial design by the inventors. Based on the above problem inFIG.2, the power supply signal line overlaps the first data signal line222in the thickness direction of the display panel. Although the problem that the layout space of the display panel inFIG.2is limited is solved, a large parasitic capacitance is generated at the overlap between the power supply signal line and the first data signal line222, so that signal crosstalk (interference) occurs between different lines in the wiring, thereby reducing the display quality of the display panel. For example, the first data signal line222is a data signal wiring (Data) and the power supply signal line203is a VDD signal wiring. When the signal through the first data signal line222changes or varies, the potential on the power supply signal line203is changed to a certain extent by the capacitive coupling effect, so that the signal through the power supply signal line203is not stable enough, thereby reducing the brightness stability of the display panel.

FIG.4is a schematic top view of a portion of wiring according to an embodiment of the present application, and is also a wiring arrangement proposed in the present application. The arrangement ofFIG.4is provided to solve the problems in the designs ofFIGS.1,2, and3. The subsequent embodiments will be described or illustrated in detail with reference to this embodiment.

To solve the above-described problems, in an embodiment of the present application, a display panel is provided. The display panel includes a substrate and pixel circuitry disposed on the substrate. The pixel circuitry includes a plurality of transistor groups and a plurality of signal line groups. The signal line group includes a power supply signal line and a first data signal line each extending in a first direction. The plurality of transistor groups are divided into a plurality of transistor group columns by the signal line groups. The signal line group is disposed between two adjacent ones of the transistor group columns. The transistor group is disposed between two adjacent ones of the signal line groups. A width of the power supply signal line is greater than a width of the first data signal line. The power supply signal line at least partially overlaps the first data signal line in the thickness direction of the display panel. A part of the power supply signal line overlapping the first data signal line is provided with at least one through hole, and the first data signal line overlaps the through hole in the thickness direction of the display panel.

Detailed descriptions are given below. It should be noted that the order in which the following embodiments are described is not intended to limit the preferred order of the examples.

FIG.4is a schematic top view of a portion of wiring according to an embodiment of the present application.FIG.5is an enlarged schematic top view of a portion of wiring according to an embodiment of the present application.FIG.6is a schematic cross-sectional view of a portion of film layers of a display panel according to one or more embodiments of the present application. To more clearly view the arrangement of the wiring of the present application,FIG.5is an enlarged schematic diagram of the wiring ofFIG.4.

In an embodiment of the present application, a display panel100includes a substrate11and pixel circuitry disposed on the substrate11. The pixel circuitry includes a plurality of transistor groups301and a plurality of signal line groups302. The signal line group302includes a power supply signal line203and a first data signal line222each extending in a first direction X. The plurality of transistor groups are divided into a plurality of transistor group columns300by the signal line groups302. Each of the signal line groups302is disposed between two adjacent ones of the transistor group columns300. Each of the transistor groups301is disposed between two adjacent ones of the signal line groups302. A width of the power supply signal line203is greater than a width of the first data signal line222. The power supply signal line203at least partially overlaps the first data signal line222in the thickness direction of the display panel100. A part of the power supply signal line203overlapping the first data signal line222is provided with at least one through hole203W, and the first data signal line222overlaps the through hole203W in the thickness direction of the display panel100.

In an embodiment, the power supply signal line203may be a VDD signal line, the first data signal line222may be a first Data signal line, and the transistor group301may include a plurality of thin film transistors of a pixel circuit.

In an embodiment, the pixel circuitry includes a plurality of transistor groups301and a plurality of signal line groups302. The plurality of transistor groups are divided into a plurality of transistor group columns300by the signal line groups302. Each of the signal line group302is disposed between two adjacent ones of the transistor group columns300. Each of the transistor groups301is disposed between two adjacent ones of the signal line groups302. Therefore, the arrangement may avoid the overlapping of the transistor group301and the signal line group302in the thickness direction of the display panel, and the large parasitic capacitance and the serious signal interference between the transistor group301and the signal line group302, as described inFIGS.1to3. The arrangement may cause the power supply signal line203at least partially overlaps the first data signal line222in the thickness direction of the display panel100due to the limited layout space.

In an embodiment, in order to solve the problem inFIG.3, the power supply signal line203includes at least one through hole203W at a portion of the power supply signal line203overlapped with the first data signal line222, and the first data signal line222overlaps the through hole203W in the thickness direction of the display panel100. This arrangement reduces an effective overlap area of the power supply signal line203and the first data signal line222, reduces the size of the parasitic capacitance, thereby reducing the signal crosstalk between the power supply signal line203and the first data signal line222, and improves the display quality of the display panel.

In some embodiments, with reference toFIG.4, the signal line group302further includes a second data signal line223. In each of the signal line groups, the second data signal line223and the first data signal line222are arranged side by side in parallel. The second data signal line223does not overlap the power supply signal line203in the thickness direction of the display panel.

In an embodiment, in some arrangements of the display panel, for example, in a display panel driving configuration using Ramless IC, the signal line group302further includes a second data signal line223.

In an embodiment, in each of the signal line groups, the second data signal line223and the first data signal line222are arranged side by side and in parallel, and the second data signal line223does not overlap the power supply signal line203in the thickness direction of the display panel, so that the limitation on the layout space may be improved, thereby further making the power supply signal line203at least partially overlap the first data signal line222in the thickness direction of the display panel100.

In an embodiment, in order to avoid the larger parasitic capacitance and the signal interference between the first data signal line222and the second data signal line223and the power supply signal line203, the second data signal line223does not overlap the power supply signal line203in the thickness direction of the display panel.

In some embodiments, the first data signal line222and the second data signal line223respectively in every two adjacent ones of the signal line groups302are configured to drive ones of the transistor groups301respectively in different rows each being in a second direction perpendicular to the first direction. The first data signal line222and the second data signal line223in each signal line group302are configured to drive ones of the transistor groups301in the same row in the second direction. Each of the transistor groups301is coupled to the first data signal line222or the second data signal line223.

In an embodiment, as shown inFIG.4, the first data signal line222and the second data signal line223in the signal line group302in an odd column are configured to drive the transistor groups301in an even row, respectively, and the first data signal line222and the second data signal line223in the signal line group302in an even column are configured to drive the transistor groups301in an odd row, respectively. Alternatively, the first data signal line222and the second data signal line223in the signal line group302in the odd column respectively are configured to drive the transistor group301in the odd row, respectively, and the first data signal line222and the second data signal line223in the signal line group302in the even column are configured to drive the transistor group301in the even row, respectively.

In an embodiment, as shown inFIG.4, the first data signal line222and the second data signal line223are coupled or connected to the transistor groups301through first connection lines2210, respectively, and the power supply signal line203is coupled or connected to the transistor group301through a second connection line2030.

In some embodiments, the first data signal line222is straight, and the power supply signal line203is not straight.

In an embodiment, in order to reduce the impedance of the first data signal line222, the first data signal line222is straight, and the second data signal line223may also be straight.

In an embodiment, in order to reduce the overlap area of the first data signal line222and the power supply signal line203, the power supply signal line203may be not straight, that is, the first data signal line222at least partially overlaps the power supply signal line203.

In some embodiments, the power supply signal line203includes a first segment2031and a second segment2032each extending in the first direction, and a third segment2033connected between the first segment2031and the second segment2032. The first segment2031is not aligned with the second segment2032. In each of the signal line groups, the first segment2031overlaps the first data signal line222in the thickness direction of the display panel. The through hole203W is disposed in the first segment2031. The second segment2032does not overlap the first data signal line222in the thickness direction of the display panel.

In an embodiment, the first segment2031overlaps with the first data signal line222in the thickness direction of the display panel, and the second segment2032does not overlap with the first data signal line222in the thickness direction of the display panel, thereby further reducing the effective overlap area of the power supply signal line203and the first data signal line222, and reducing the size of the parasitic capacitance, thereby reducing the signal crosstalk between the power supply signal line203and the first data signal line222, thereby improving the display quality of the display panel.

In some embodiments, the through hole203W extends along a same direction as that of the first data signal line222.

In an embodiment, the through hole203W extends along the same direction as that of a portion of the first data signal line222at the through hole203W, that is, at the overlap, the through hole203W extends along the same direction as that of the first data signal line222, so that an effective overlap area of the power supply signal line203and the first data signal line222at the overlap may be minimized to the greatest extent, while avoiding excessive reduction of the width of the power supply signal line203and excessive increase of the resistance of the power supply signal line203.

In some embodiments, a width of the through hole203W is greater than the width of the first data signal line222in a direction perpendicular to the extension direction of the first data signal line222.

In an embodiment, the width of the through hole203W is greater than the width of the first data signal line222in the direction perpendicular to the extension direction of the first data signal line222, that is, a fourth width d4is greater than a third width d3inFIG.5. Therefore, the power supply signal lines203at both sides of the through hole203W and the first data signal line222are arranged spaced apart from each other at the overlap in a plane parallel to the substrate11, so that an effective overlap area of the power supply signal line203and the first data signal line222at the overlap may be minimized to the greatest extent, and the size of the parasitic capacitance is reduced to the greatest extent.

In some embodiments, in the direction perpendicular to the extension direction of the first data signal line222, a distance between two outermost edges of the first segment2031away from the through hole203W is greater than a width of the second segment2032or a width of the third segment2033.

In an embodiment, in the first direction X, the distance between the two outermost edges of the first segment2031away from the through hole203W is greater than the width of the second segment2032or the width of the third segment2033, that is, a first width d1is greater than a second width d2inFIG.5, so that the through hole203W may be provided in the first segment2031while the first segment2031at the through hole203W has a larger effective width, thereby avoiding an excessive increase in the resistance of the first segment2031.

In some embodiments, referring toFIG.6, a layer structure of the display panel100includes an active layer13, a first metal layer20, a first insulating layer21, and a second metal layer22. The active layer13including semiconductor layers of a plurality of thin film transistors101is provided on the substrate11. The first metal layer20is disposed on a side of the active layer13away from the substrate11. The first metal layer20includes a source201and a drain202, and a power supply signal line203. The source201and the drain202are electrically connected to the semiconductor layer of at least one thin film transistor101. The first insulating layer21is provided on a side of the first metal layer20away from the substrate11. The second metal layer22is provided on a side of the first insulating layer21away from the substrate11, and includes a first data signal line222.

In an embodiment, the second metal layer22may further include a second data signal line223.

In an embodiment, inFIG.6, a film lamination of the display panel includes a substrate11, a buffer layer12, an active layer13, a first gate insulating layer14, a first gate metal layer15, a second gate insulating layer16, a second gate metal layer17, a first interlayer insulating layer18, a second interlayer insulating layer19, a first metal layer20, a first insulating layer21, a second metal layer22, a second flat layer23, an anode24, and a pixel definition layer25, which are sequentially laminated. The display panel100further includes a thin film transistor101including a semiconductor layer formed by patterning the active layer13, a first gate151located at the first gate metal layer15, and a source201and a drain202located at the first metal layer20. A second gate or capacitor electrode171located at the second gate metal layer17or a capacitor electrode metal layer forms a capacitor with the first gate151, and a first connection electrode221located at the second metal layer22is connected between the anode24and the drain202.

In an embodiment, as shown inFIG.6, the power supply signal line203is located in the first metal layer20, the first data signal line222is located in the second metal layer22, and the second data signal line223is located in the second metal layer22, but it is not limited thereto.

In some embodiments, the material of the first metal layer20is same as that of the second metal layer22, and the thickness of the first metal layer20is greater than the thickness of the second metal layer22.

In an embodiment, as shown inFIG.6, the material of the power supply signal line203is same as that of the first data signal line222, and the thickness of the power supply signal line203is greater than the thickness of the first data signal line222, so that the resistance of the power supply signal line203is reduced by increasing the thickness of the power supply signal line203, and the resistance of the power supply signal line203is prevented from being increased due to the through hole203W.

In some embodiments, the first metal layer20includes a laminate of titanium-layer/aluminum-layer/titanium-layer, and a thickness of the aluminum-layer is greater than or equal to 7000 angstroms.

In an embodiment, each of the power supply signal line203and the first data signal line222includes a laminate of titanium-layer/aluminum-layer/titanium-layer (Ti/Al/Ti), and a thickness of the aluminum-layer in the power supply signal line203is greater than or equal to 7000 angstroms, so that the resistance of the power supply signal line203may be reduced.

In an embodiment, the thickness of the aluminum-layer in the power supply signal line203is greater than or equal to 7000 angstroms, the thickness of the aluminum layer in the first data signal line222is greater than or equal to 6000 angstroms, and the thickness of the aluminum layer in the power supply signal line203is greater than the thickness of the aluminum layer in the first data signal line222, so that the resistance of the power supply signal line203is prevented from being increased due to the through hole203W.

In some embodiments, the width of a part of the first segment2031at either side of the through hole203W in a second direction perpendicular to the first direction is greater than or equal to 1.9 microns.

In an embodiment, inFIG.5, the width of the first segment2031at either side of the through hole203W is greater than or equal to 1.9 microns, that is, a fifth width d5and a sixth width d6are both greater than or equal to 1.9 microns, so that the power supply signal line203at the through hole203W is prevented from being broken due to etching or the like.

Note that inFIG.4, the edges of the power supply signal line203at one side of the through hole203W are a first edge20311and a second edge20312, respectively, and the edges of the power supply signal line203at the other side of the through hole203W are the third edge20313and the fourth edge20314, respectively.

FIG.7is a schematic diagram of a verification result of fluctuation of a VDD signal according to the present application. InFIG.7, the condition “B→W” indicates that a black picture is switched to a white picture, the condition “W→B” indicates that the white picture is switched to the black picture, the condition “before optimization” indicates that the power supply signal line203inFIG.4orFIG.5is not provided with the through hole203W, and the condition “after optimization” indicates that the power supply signal line203inFIG.4orFIG.5is provided with the through hole203W. As can be seen fromFIG.7, the optimized condition in an embodiment of the present application reduces the fluctuation of the electrical signal through the power supply signal line203from 95 mV to 65 mV. The optimized condition makes the fluctuation of the electrical signal through the power supply signal line203less than or equal to 65 mV, thereby achieving a very good improvement.

It should be noted that both the power supply signal line203and the first data signal line222extend in the first direction X, and the second direction Y is a direction perpendicular to the direction in which the data signal line222extends, that is, the first direction X is perpendicular to the second direction Y.

The display panels according to some embodiments of the present application are described above in detail. Specific examples are used to illustrate the principles and embodiments of the present application. The description of the above embodiments is merely provided to assist in understanding the method of the present application and the core concept thereof. Meantime, variations will occur for those skilled in the art in both the detailed description and the scope of the present application in accordance with the teachings of the present application. In view of the foregoing, the presented description should not be construed as limiting the application.