Semiconductor memory device having vertical semiconductor films with narrowing widths and gate insulating films with different thickness

A semiconductor memory device according to an embodiment includes: a substrate; a plurality of first gate electrodes; a first semiconductor film facing the plurality of first gate electrodes; and a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film. Moreover, this semiconductor memory device includes: a plurality of second gate electrodes; a second semiconductor film facing the plurality of second gate electrodes; and a second gate insulating film provided between the plurality of second gate electrodes and the second semiconductor film. Moreover, this semiconductor memory device includes: a third gate electrode that is provided between the plurality of first gate electrodes and the plurality of second gate electrodes, and extends in a second direction; and a third gate insulating film provided between the third gate electrode and the first semiconductor film. Moreover, a thickness in a first direction of the third gate insulating film is larger than a width in the second direction of the first gate insulating film and the second gate insulating film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of Japanese Patent Application No. 2018-163858, filed on Aug. 31, 2018, the entire contents of which are incorporated herein by reference.

BACKGROUND

Field

Embodiments described herein relate to a semiconductor memory device.

Description of the Related Art

There is known a semiconductor memory device that includes: a substrate; a plurality of gate electrodes arranged in a first direction intersecting a surface of the substrate; a semiconductor film extending in the first direction to face these plurality of gate electrodes; and a gate insulating film provided between the plurality of gate electrodes and the semiconductor film.

DETAILED DESCRIPTION

A semiconductor memory device according to one embodiment includes: a substrate; a plurality of first gate electrodes that are arranged in a first direction intersecting a surface of the substrate and extend in a second direction intersecting the first direction; a first semiconductor film that extends in the first direction and faces the plurality of first gate electrodes, a width in the second direction of one end on a substrate side of the first semiconductor film being smaller than a width in the second direction of an other end of the first semiconductor film; and a first gate insulating film that extends in the first direction and is provided between the plurality of first gate electrodes and the first semiconductor film. Moreover, this semiconductor memory device includes: a plurality of second gate electrodes that are arranged in the first direction, extend in the second direction, and are further from the substrate than the plurality of first gate electrodes are; a second semiconductor film that extends in the first direction and faces the plurality of second gate electrodes, a width in the second direction of one end on the substrate side of the second semiconductor film being smaller than the width in the second direction of the other end of the first semiconductor film, a width in the second direction of an other end of the second semiconductor film being larger than the width in the second direction of the one end of the second semiconductor film, and the one end of the second semiconductor film being connected to the other end of the first semiconductor film; and a second gate insulating film that extends in the first direction and is provided between the plurality of second gate electrodes and the second semiconductor film. Moreover, this semiconductor memory device includes: a third gate electrode that is provided between the plurality of first gate electrodes and the plurality of second gate electrodes, extends in the second direction, and faces the other end of the first semiconductor film at a surface on the substrate side; and a third gate insulating film that is provided between the third gate electrode and the other end of the first semiconductor film, and is connected to the first gate insulating film and the second gate insulating film. Moreover, the third gate electrode faces the second semiconductor film via the second gate insulating film, and faces the other end of the first semiconductor film via the third gate insulating film. Moreover, a thickness in the first direction of the third gate insulating film is larger than a thickness in the second direction of the first gate insulating film and the second gate insulating film.

Next, embodiments of a semiconductor memory device will be described in detail with reference to the drawings. Note that these embodiments are merely examples, and are not shown with the intention of limiting the present invention.

Moreover, in the present specification, a direction intersecting a surface of a substrate will be called a first direction, a direction intersecting the first direction will be called a second direction, and a direction intersecting the first direction and the second direction will be called a third direction. Moreover, a certain direction parallel to the surface of the substrate will be called an X direction, a direction parallel to the surface of the substrate and perpendicular to the X direction will be called a Y direction, and a direction perpendicular to the surface of the substrate will be called a Z direction. The X direction, the Y direction, and the Z direction may or may not each respectively correspond to any one of the first through third directions.

Moreover, in the present specification, expressions such as “up” or “down” will be defined with reference to the substrate. For example, an orientation of moving away from the substrate along the above-described first direction will be called up, and an orientation of coming closer to the substrate along the first direction will be called down. Moreover, when a lower surface or a lower end is referred to for a certain configuration, this will be assumed to mean a surface or end section on a substrate side of the configuration, and when an upper surface or an upper end is referred to for a certain configuration, this will be assumed to mean a surface or end section on an opposite side to the substrate of the configuration. Moreover, a surface intersecting the second direction or the third direction will be called a side surface, and so on.

Moreover, in the present specification, when a “radial direction” is referred to for the likes of a cylinder-shaped or ring-shaped member or a through-hole, this will be assumed to mean a direction of coming closer to a central axis of the cylinder or ring or a direction of moving away from the central axis of the cylinder or ring, in a plane perpendicular to this central axis. Moreover, when a “thickness in the radial direction”, and so on, is referred to, this will be assumed to mean a difference between a distance from the central axis to an inner circumferential surface and a distance from the central axis to an outer circumferential surface, in such a plane.

Moreover, in the present specification, when a “width” or “thickness” in a certain direction is referred to for a configuration, a member, and so on, this will sometimes be assumed to mean a width or thickness in a cross section observed by the likes of SEM (Scanning Electron Microscopy) or TEM (Transmission Electron Microscopy), and so on.

First Embodiment

Configuration

FIG. 1is a schematic equivalent circuit diagram of a semiconductor memory device according to a first embodiment. For convenience of description, part of a configuration is omitted inFIG. 1.

The semiconductor memory device according to the present embodiment includes: a memory cell array MA; and a peripheral circuit PC that controls the memory cell array MA.

The memory cell array MA includes a plurality of memory blocks MB. These plurality of memory blocks MB each include a plurality of sub-blocks SB. These plurality of sub-blocks SB each include a plurality of memory units MU. One ends of these plurality of memory units MU are respectively connected to the peripheral circuit PC via bit lines BL. Moreover, the other ends of these plurality of memory units MU are each connected to the peripheral circuit PC via a common lower wiring SC and common source line SL.

The memory unit MU includes a drain select transistor STD, a memory string MS, and a source select transistor STS that are connected in series between the bit line BL and the lower wiring SC. Hereafter, the drain select transistor STD and the source select transistor STS will sometimes simply be called select transistors (STD, STS).

The memory string MS includes a plurality of memory cells MC connected in series. The memory cell MC is a field effect transistor that includes a semiconductor film, a gate insulating film, and a gate electrode. The semiconductor film functions as a channel region. The gate insulating film includes a memory section capable of storing data. This memory section is a charge accumulating film such as a silicon nitride film (SiN) or a floating gate, for example. In this case, a threshold voltage of the memory cell MC changes according to an amount of charge in the charge accumulating film. The gate electrode is connected to a word line WL. The word lines WL are provided corresponding to the plurality of memory cells MC belonging to one memory string MS, and are commonly connected to all of the memory strings MS in one memory block MB.

The select transistor (STD, STS) is a field effect transistor that includes a semiconductor film, a gate insulating film, and a gate electrode. The semiconductor film functions as a channel region. The gate electrode of the drain select transistor STD is connected to a drain select line SGD. The drain select line SGD is provided corresponding to the sub-block SB and is commonly connected to all of the drain select transistors STD in one sub-block SB. The gate electrode of the source select transistor STS is connected to a source select line SGS. The source select line SGS is commonly connected to all of the source select transistors STS in one memory block MB.

The peripheral circuit PC generates a voltage required for a read operation, a write operation, and an erase operation, and applies the voltage to the bit line BL, the source line SL, the word line WL, and the select gate line (SGD, SGS), for example. The peripheral circuit PC includes a plurality of transistors and wirings provided on the same chip as the memory cell array MA, for example.

FIG. 2is a schematic perspective view of the semiconductor memory device according to the present embodiment. For convenience of description, part of a configuration is omitted inFIG. 2.

As shown inFIG. 2, the semiconductor memory device according to the present embodiment includes: a substrate S; a circuit layer CL provided above the substrate S; and the memory cell array MA provided above the circuit layer CL. Moreover, the memory cell array MA includes: a memory layer MLa; and a memory layer MLb provided above the memory layer MLa.

The substrate S is a semiconductor substrate configured from the likes of single crystal silicon (Si), for example. The substrate S has a double well structure in which, for example, an n type impurity layer is included in a surface of the semiconductor substrate, and a p type impurity layer is further included in this n type impurity layer.

The circuit layer CL includes: a plurality of transistors Tr; and a plurality of wirings and contacts connected to these plurality of transistors Tr, that, together with the plurality of transistors Tr, configure the peripheral circuit PC (FIG. 1). The transistor Tr is a field effect transistor that utilizes as a channel region the surface of the substrate S, for example.

The memory cell array MA includes: a plurality of conductive films110arranged in the Z direction; a plurality of semiconductor films120extending in the Z direction to face the plurality of conductive films110; and a gate insulating film130provided between these conductive films110and semiconductor films120.

The conductive film110functions as the word line WL (FIG. 1) and the gate electrodes of the plurality of memory cells MC connected to this word line WL, or as the drain select line SGD (FIG. 1) and the gate electrodes of the plurality of drain select transistors STD (FIG. 1) connected to this drain select line SGD. Moreover, a conductive film111and a conductive film112are provided below the plurality of conductive films110. The conductive film111functions as the source select line SGS (FIG. 1) and the gate electrodes of the plurality of source select transistors STS (FIG. 1) connected to this source select line SGS. The conductive film112functions as the lower wiring SC (FIG. 1). Moreover, an interlayer insulating film101of the likes of silicon oxide (SiO2) is provided between the conductive films110,111,112.

The conductive films110,111include a plurality of through-holes formed in a certain pattern, and the semiconductor film120and gate insulating film130are disposed inside this through-hole. End sections in the X direction of the conductive films110,111are connected to contacts CC that extend in the Z direction.

The conductive film112includes: a semiconductor film113connected to the semiconductor film120; and a conductive film114provided on a lower surface of the semiconductor film113. The semiconductor film113is a conductive semiconductor film of the likes of polycrystalline silicon (Si) implanted with an n type impurity such as phosphorus (P), for example. The conductive film114is, for example, a conductive film of polycrystalline silicon implanted with an n type impurity such as phosphorus, a conductive film of a metal such as tungsten (W), or a conductive film of a silicide, and so on.

Hereafter, a conductive film110included in the memory layer MLa, of the plurality of conductive films110will sometimes be written as “conductive film110a”, or the like. Moreover, a conductive film110included in the memory layer MLb, of the plurality of conductive films110will sometimes be written as “conductive film110b”, or the like. Moreover, a conductive film110positioned between the conductive film110aand the conductive film110b, of the plurality of conductive films110will sometimes be written as “conductive film110c”, or the like.

The semiconductor film120functions as the channel regions of the plurality of memory cells MC, the drain select transistor STD, and the source select transistor STS that are arranged in the Z direction, and so on. The semiconductor film120is a semiconductor film of the likes of non-doped polycrystalline silicon, for example. Moreover, an insulating film140of silicon dioxide (SiO2) or the like is embedded in a central portion of the semiconductor film120.

Hereafter, a semiconductor film120and insulating film140included in the memory layer MLa, of the plurality of semiconductor films120and insulating films140will sometimes be written as “semiconductor film120a” and “insulating film140a”, or the like. Moreover, a semiconductor film120and insulating film140included in the memory layer MLb, of the plurality of semiconductor films120and insulating films140will sometimes be written as “semiconductor film120b” and “insulating film140b”, or the like.

The semiconductor films120a,120beach have a substantially cylindrical shape extending in the Z direction. Moreover, outer diameters of the semiconductor films120a,120bbecome smaller as the substrate is approached. Therefore, outer diameters of lower end sections of the semiconductor films120a,120bare respectively smaller than outer diameters of upper end sections of the semiconductor films120a,120b. The semiconductor film120ais connected at its lower end section to the semiconductor film113, and is connected at its upper end section to the semiconductor film120b. The semiconductor film120bis connected at its upper end section to a semiconductor film102, and is connected to the bit line BL via this semiconductor film102. The semiconductor film102is a conductive semiconductor film of the likes of polycrystalline silicon implanted with an n type impurity such as phosphorus, for example.

The gate insulating film130is a gate insulating film that includes, for example, the likes of a charge accumulating film of silicon nitride (Si3N4), and so on.

Hereafter, a gate insulating film130included in the memory layer MLa, of the gate insulating films130will sometimes be written as “gate insulating film130a”, or the like. Moreover, a gate insulating film130included in the memory layer MLb, of the gate insulating films130will sometimes be written as “gate insulating film130b”, or the like. Moreover, a gate insulating film130positioned between the memory layers MLa, MLb, of the gate insulating films130will sometimes be written as “gate insulating film130c”, or the like.

The gate insulating films130a,130beach have a substantially cylindrical shape extending in the Z direction. Moreover, outer diameters of the gate insulating films130a,130bbecome smaller as a lower side is approached. Therefore, outer diameters of lower end sections of the gate insulating films130a,130bare respectively smaller than outer diameters of upper end sections of the gate insulating films130a,130b.

The gate insulating film130chas a substantially disk-like or substantially ring-like shape including a through-hole. An outer circumferential portion of the gate insulating film130cis connected to the upper end section of the gate insulating film130a. Moreover, an inner circumferential portion of the through-hole of the gate insulating film130cis connected to the lower end section of the gate insulating film130b.

Hereafter, a substantially circular column shaped configuration including the likes of the semiconductor films120a,120b, the gate insulating films130a,130b,130c, the insulating films140a,140b, and the semiconductor film102will sometimes be written as “memory structure MH”, or the like.

FIG. 3is a schematic YZ cross-sectional view showing a more specific configuration example of a structure exemplified inFIG. 2.FIG. 4is a schematic enlarged view of a portion indicated by A ofFIG. 3. Note that for convenience of description, part of a configuration is omitted inFIGS. 3 and 4.

As shown inFIG. 4, the conductive films110a,110b,110ceach include: a metal film115of tungsten (W) or the like; and a barrier metal film116of titanium nitride (TiN) or the like provided on an upper surface and a lower surface of this metal film115and on an inner circumferential surface of a through-hole of the metal film115. Note that the inner circumferential surface of the conductive film110cfaces an outer circumferential surface of the semiconductor film120bvia the gate insulating film130b. Moreover, part of a lower surface of the conductive film110cfaces an upper end section E120aof the semiconductor film120avia the gate insulating film130c.

As mentioned above, the upper end section E120aof the semiconductor film120ais connected to a lower end section E120bof the semiconductor film120b. As illustrated, a level difference is formed in this connecting portion.

The gate insulating films130a,130b,130crespectively include tunnel insulating films131a,131b,131cof silicon oxide or the like, charge accumulating films132a,132b,132cof silicon nitride or the like, block insulating films133a,133b,133cof silicon oxide or the like, and parts of high-permittivity insulating films134a,134b,134cof alumina (Al2O3) or the like. The tunnel insulating films131a,131b, the charge accumulating films132a,132b, and the block insulating films133a,133bextend in the Z direction. The tunnel insulating film131c, the charge accumulating film132c, and the block insulating film133ceach extend in the X direction and the Y direction, and are respectively connected to upper end sections of the tunnel insulating film131a, the charge accumulating film132a, and the block insulating film133a, and lower end sections of the tunnel insulating film131b, the charge accumulating film132b, and the block insulating film133b. A plurality of the high-permittivity insulating films134a,134b,134care provided corresponding to the conductive films110, and the high-permittivity insulating films134a,134b,134ceach cover an upper surface and a lower surface of the conductive film110, and an inner circumferential surface of a through-hole of the conductive film110.

Now, in the present embodiment, a thickness W102in the Z direction of the gate insulating film130cis larger than a thickness W101in the radial direction of the gate insulating films130a,130b. Therefore, a shortest distance from the upper end section E120aof the semiconductor film120ato the conductive film110cis larger than a shortest distance from the semiconductor film120ato the conductive film110a, and is larger than a shortest distance from the semiconductor film120bto the conductive film110b.

Moreover, in the present embodiment, a thickness W112in the Z direction of the block insulating film133cis larger than a thickness W111in the radial direction of the block insulating films133a,133b. Note that the block insulating films133a,133bare provided also on an inner circumferential surface of a through-hole of the interlayer insulating film101. A thickness W113in the radial direction of this portion is smaller than the thickness W111in the radial direction of portions provided in the through-holes of the conductive films110a,110b.

Note that thicknesses in the Z direction of the tunnel insulating film131c, the charge accumulating film132c, and the high-permittivity insulating film134care respectively of the same degree as thicknesses in the radial direction of the tunnel insulating films131a,131b, the charge accumulating films132a,132b, and the high-permittivity insulating films134a,134b. At least, a difference between the above-described thickness W112and the above-described thickness W111is larger than differences between the thicknesses in the Z direction of the tunnel insulating film131c, the charge accumulating film132c, and the high-permittivity insulating film134c, and the thicknesses in the radial direction of the tunnel insulating films131a,131b, the charge accumulating films132a,132b, and the high-permittivity insulating films134a,134b. The same applies also to a difference between the above-described thickness W113and the above-described thickness W111.

In the description below, the tunnel insulating films131a,131b,131cwill sometimes be collectively called a tunnel insulating film131. Similarly, the charge accumulating films132a,132b,132cwill sometimes be collectively called a charge accumulating film132. Similarly, the block insulating films133a,133b,133cwill sometimes be collectively called a block insulating film133. Similarly, the high-permittivity insulating films134a,134b,134cwill sometimes be collectively called a high-permittivity insulating film134.

Method of Manufacturing

Next, a method of manufacturing the semiconductor memory device according to the present embodiment will be described with reference toFIGS. 5-22.

As shown inFIG. 5, in same method of manufacturing, above the circuit layer CL, the conductive film114, a semiconductor film113A of silicon or the like, an insulating film113B of silicon oxide or the like, a semiconductor film113C of silicon or the like, an insulating film113D of silicon oxide or the like, and a semiconductor film113E of silicon or the like, are formed. Moreover, above these, the interlayer insulating film101and the conductive film111are formed. Moreover, above these, a plurality of the interlayer insulating films101and sacrifice films110A of silicon nitride or the like, that correspond to the memory layer MLa, are alternately formed. This step is performed by a method such as PECVD (Plasma-Enhanced Chemical Vapor Deposition), for example.

Next, as shown inFIG. 6, an opening op1is formed. The opening op1is an opening that extends in the Z direction and penetrates the sacrifice films110A, the interlayer insulating films101, the conductive film111, the semiconductor film113E, the insulating film113D, the semiconductor film113C, and the insulating film113B to expose the semiconductor film113A. This step is performed by a method such as RIE (Reactive Ion Etching), for example.

Next, as shown inFIG. 7, a cover film130A of silicon nitride or the like and a sacrifice film120A of silicon or the like, are formed on an inside of the opening op1. This step is performed by, for example, forming the cover film130A and the sacrifice film120A by LPCVD (Low-Pressure Chemical Vapor Deposition) or the like, and exposing an upper surface of an uppermost level interlayer insulating film101by RIE or the like.

Next, as shown inFIG. 8, a plurality of the interlayer insulating films101and the sacrifice films110A that correspond to the memory layer MLb, are alternately formed. This step is performed by a method such as PECVD, for example.

Next, as shown inFIGS. 9 and 10, an opening op2is formed. The opening op2is an opening that extends in the Z direction and penetrates the sacrifice films110A and the interlayer insulating films101to expose the sacrifice film120A. This step is performed by a method such as RIE, for example.

Next, as shown inFIG. 11, a cover film130B of silicon nitride or the like, a sacrifice film120B of silicon or the like, and a cover film120C of silicon oxide or the like, are formed on an inner circumferential surface and a bottom surface of the opening op2. This step is performed by a method such as LPCVD, for example.

Next, as shown inFIG. 12, portions formed on the bottom surface of the opening op2, of the cover film130B, the sacrifice film120B, and the cover film120C, are removed. This step is performed by a method such as RIE, for example.

Next, as shown inFIG. 13, the cover film120C is removed. In addition, part of the cover film130B is removed. In the example illustrated, the cover film130B is removed leaving a portion covering a side surface of the sacrifice film110A corresponding to the conductive film110c. This step is performed by a method such as wet etching, for example.

Next, as shown inFIG. 14, the sacrifice film120A and the sacrifice film120B are removed. This step is performed by a method such as wet etching, for example.

Next, as shown inFIGS. 15 and 16, the block insulating film133is formed. This step is performed by, for example, performing oxidation treatment on the cover film130A, the cover film130B, and part of the sacrifice film110A.

Now, in the present embodiment, the sacrifice films110A and the cover films130A,130B are both films of silicon nitride or the like. However, due to differences in methods of film formation and conditions of film formation, and so on, the cover films130A,130B sometimes have a larger density than the sacrifice films110A. In such a case, it is sometimes more difficult for the cover films130A,130B to be oxidized than for the sacrifice films110A to be oxidized.

In the example illustrated, the sacrifice films110A are basically covered by the cover films130A,130B. However, a vicinity of a contact surface with the cover films130A,130B is sometimes oxidized. In such a case, the thickness W111in the radial direction of a portion provided on an inner circumferential surface of a through-hole of the sacrifice film110A, of the block insulating film133becomes larger than the thickness W113in the radial direction of a portion provided on an inner circumferential surface of a through-hole of the interlayer insulating film101, of the block insulating film133.

Moreover, in the example ofFIG. 14, part of a lower surface of a sacrifice film110A corresponding to the conductive film110C is not covered by the cover films130A,130B, but exposed to the opening op2. If oxidation treatment is performed in such a state, an oxidized film which is thicker than that of a portion covered by the cover films130A,130B is sometimes formed as shown inFIG. 15. In such a case, the thickness W112in the Z direction of the block insulating film133cbecomes larger than the thickness W111in the radial direction of the block insulating films133a,133b.

Next, as shown inFIGS. 17 and 18, a laminated film130C, the semiconductor film120, and the insulating film140are formed on insides of the openings op1, op2. The laminated film130C is a laminated film that includes the block insulating film133, the charge accumulating film132, and the tunnel insulating film131. This step is performed by a method such as LPCVD, for example.

Next, as shown inFIG. 19, an opening op3is formed. The opening op3is a trench that extends in the Z direction and the X direction, divides in the Y direction the sacrifice films110A, the interlayer insulating films101, the conductive film111, the semiconductor film113E, and the insulating film113D, and exposes an upper surface of the semiconductor film113C. This step is performed by a method such as RIE, for example.

Next, as shown inFIG. 20, an insulating film105of silicon nitride or the like is formed on a side surface in the Y direction of the opening op3. This step is performed by a method such as LPCVD, for example.

Next, as shown inFIG. 21, the semiconductor film113C, the insulating films113B,113D, and part of the laminated film130C, are removed to expose a lower end section of the semiconductor film120. This step is performed by the likes of wet etching, for example.

Next, as shown inFIG. 22, a semiconductor film is formed on an upper surface of the semiconductor film113A, a lower surface of the semiconductor film113E, and part of an outer circumferential surface of the semiconductor film120, thereby forming the semiconductor film113. This step is performed by a method such as CVD or an epitaxial crystal growth method, for example.

Subsequently, the insulating film105is removed by a method such as wet etching, surfaces exposed to the opening op3of the conductive film111and the semiconductor film113are selectively oxidized to form insulating films106,107, the sacrifice films110A are removed by a method such as wet etching, the high-permittivity insulating film134, the barrier metal film116, and the metal film115are formed by a method such as CVD, and an insulating film ST is formed in the opening op3, whereby the configuration described with reference toFIGS. 3 and 4is formed.

First Comparative Example

Next, a first comparative example will be described.FIG. 23is a schematic cross-sectional view for describing a method of manufacturing according to the first comparative example.

The method of manufacturing according to the first comparative example is similar to that of the first embodiment up to the step described with reference toFIG. 6.

In the first embodiment, as described with reference toFIG. 7, the cover film130A of silicon nitride or the like has been formed on the inside of the opening op1. This makes it possible for the semiconductor films113A,113C,113E, and the conductive film111to be protected when removing the sacrifice film120A.

On the other hand, in the comparative example, as shown inFIG. 23, the cover film130A is not formed after the opening op1has been formed, but instead, oxidation treatment is performed, and an oxidized film130A′ is formed on surfaces exposed to the opening op1of the semiconductor films113A,113C,113E, and the conductive film111.

Now, as shown inFIG. 24, when forming the opening op1, an opening op1′ larger than the opening op1has sometimes ended up being formed. In such a case, the conductive film114has sometimes ended up being exposed to the opening op1′. Sometimes, when oxidation treatment has been performed in this state, abnormal oxidation has occurred in the conductive film114, and a structure has ended up being broken over a wide range.

Second Comparative Example

Next, a second comparative example will be described.FIG. 25is a schematic cross-sectional view for describing a method of manufacturing according to the second comparative example.

The method of manufacturing according to the second comparative example is similar to that of the first embodiment up to the step described with reference toFIG. 9.

In the second comparative example, after having performed the step described with reference toFIG. 9, the sacrifice film120A is removed and oxidation treatment is performed, whereby block insulating films133a′,133b′ are formed. The block insulating film133a′ is an insulating film formed by oxidizing the cover film130A. The block insulating film133b′ is an insulating film formed by oxidizing part of the sacrifice film110A.

In the second comparative example, an oxidation treatment of the kind described with reference toFIG. 23is not performed. Therefore, a problem of abnormal oxidation of the kind described with reference toFIG. 24does not occur.

However, in the second comparative example, the likes of film thicknesses or film qualities end up differing between the block insulating film133a′ and the block insulating film133b′. Therefore, characteristics of the formed memory cells MC sometimes end up varying greatly.

Third Comparative Example

Next, a third comparative example will be described.FIGS. 26 and 27are schematic cross-sectional view for describing a method of manufacturing according to the third comparative example.FIG. 28is a schematic cross-sectional view for describing a configuration of a semiconductor memory device according to the third comparative example.

The method of manufacturing according to the third comparative example is similar to that of the first embodiment up to the step described with reference toFIG. 9.

In the third comparative example, after having performed the step described with reference toFIG. 9, the sacrifice film120A and the cover film130A are removed, and, as shown inFIG. 26, an insulating film130A″ of silicon nitride or the like is formed on inner circumferential surfaces of the opening op1and the opening op2. Moreover, as shown inFIG. 27, a block insulating film130″ is formed by oxidation treatment.

Now, whereas in the first embodiment, a lower surface of some of the sacrifice films110A has been exposed to the opening op2during oxidation treatment (refer toFIG. 14), in the comparative example, this portion too is covered by the insulating film130A″. Therefore, a thickness W112′of an oxidized film formed in this portion will be of the same degree as the thickness W111of an oxidized film formed on the inner circumferential surface of the through-hole of the sacrifice film110A. Therefore, as shown inFIG. 28, a thickness W102′in the Z direction of the gate insulating film130calso will be of the same degree as the thickness W101in the radial direction of the gate insulating films130a,130b. Moreover, a shortest distance from the upper end section E120aof the semiconductor film120ato the conductive film110calso will be of the same degree as shortest distances from the semiconductor films120a,120bto the conductive films110a,110b.

In the third comparative example, similarly to in the second comparative example, the problem of abnormal oxidation does not occur. Moreover, in the third comparative example, it is possible to suppress the above-mentioned kind of variation in characteristics of the memory cells MC.

Advantages of First Embodiment

In the method of manufacturing according to the first embodiment, the problem of abnormal oxidation of the kind described with reference toFIG. 24does not occur. Moreover, the problem of variation in characteristics of the memory cells MC of the kind described with reference toFIG. 25does not occur either.

In addition, as a result of study by the inventors, it has been understood that the larger the distance between the upper end section E120aof the semiconductor film120aand the conductive film110cis, the more preferably the erase operation of the memory cell MC whose gate electrode is the conductive film110c, can be performed.

As mentioned above, due to the present embodiment, the distance between the upper end section E120aof the semiconductor film120aand the conductive film110C can be made larger compared to in the semiconductor memory device according to the third comparative example. It is therefore possible to provide a semiconductor memory device that can be preferably controlled, by improving erase characteristics of the memory cell MC whose gate electrode is the conductive film110c.

Modified Examples of First Embodiment

In the step described with reference toFIG. 13, part of the cover film130B is removed by a method such as wet etching. In the example shown inFIG. 13, removal of the cover film130B has been ended at a timing when a height (a distance from the substrate S or position in the Z direction) of a lower end of the cover film130B has reached a height of an upper end of the cover film130A. However, removal of the cover film130B may be ended before the height of the lower end of the cover film130B reaches the height of the upper end of the cover film130A, or may be ended after the height of the lower end of the cover film130B has reached the height of the upper end of the cover film130A.

When, for example, as shown inFIG. 29, removal of the cover film130B has been ended before the height of the lower end of the cover film130B reaches the height of the upper end of the cover film130A, it results in a lower end of the block insulating film133bbeing positioned more downwardly than an upper end of the block insulating film133ais, as shown inFIG. 30.

In the semiconductor memory device formed in this way, lower ends of the tunnel insulating film131b, the charge accumulating film132b, and the block insulating film133bwill be positioned more downwardly than upper ends of the tunnel insulating film131a, the charge accumulating film132a, and the block insulating film133aare, as shown inFIG. 31.

Moreover, as illustrated, the charge accumulating film232cwill sometimes have a shape that includes: a first portion p1connected to the upper end of the charge accumulating film132aand extending in the radial direction; a second portion p2connected to the lower end of the charge accumulating film132band extending in the radial direction; and a third portion p3connected to these first portion p1and second portion p2and extending in the Z direction.

Moreover, when, for example, as shown inFIG. 32, removal of the cover film130B has been ended after the height of the lower end of the cover film130B has reached the height of the upper end of the cover film130A, part of the sacrifice film110A is also sometimes removed. In such a case, it results in the lower end of the block insulating film133bbeing positioned more upwardly than the upper end of the block insulating film133ais, as shown inFIG. 33. Moreover, in such a case, a block insulating film333cis sometimes not connected to the block insulating film133a.

In the semiconductor memory device formed in this way, lower ends of the tunnel insulating film131b, the charge accumulating film132b, and the block insulating film133bwill be positioned more upwardly than upper ends of the tunnel insulating film131a, the charge accumulating film132a, and the block insulating film133aare, as shown inFIG. 34.

Moreover, sometimes, as illustrated, a curved surface is formed at the upper end of the semiconductor film120a, and a tunnel insulating film331c, a charge accumulating film332c, a block insulating film333c, a high-permittivity insulating film334c, and part of the barrier metal film116will each be shaped in such a manner as to form a curved surface following this curved surface.

Others